From 06052776f5cfb6261b5675e04b11e48dc5c16afc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1s=20Pinho?= Date: Mon, 5 Aug 2019 22:42:22 +0100 Subject: [PATCH] Bring in sources from endlessm at 937be30d1142c74a2b82291d63c6b3d1911b7498 - Realtek v5.5.2 --- Makefile | 655 +- core/efuse/rtw_efuse.c | 911 +- core/mesh/rtw_mesh.c | 4097 + core/mesh/rtw_mesh.h | 534 + core/mesh/rtw_mesh_hwmp.c | 1665 + core/mesh/rtw_mesh_hwmp.h | 60 + core/mesh/rtw_mesh_pathtbl.c | 1185 + core/mesh/rtw_mesh_pathtbl.h | 206 + core/rtw_ap.c | 2809 +- core/rtw_beamforming.c | 131 +- core/rtw_br_ext.c | 12 +- core/rtw_bt_mp.c | 11 +- core/rtw_btcoex.c | 49 +- core/rtw_btcoex_wifionly.c | 19 +- core/rtw_chplan.c | 1184 + core/rtw_chplan.h | 179 + core/rtw_cmd.c | 1565 +- core/rtw_debug.c | 2134 +- core/rtw_eeprom.c | 9 +- core/rtw_ieee80211.c | 455 +- core/rtw_io.c | 308 +- core/rtw_ioctl_query.c | 9 +- core/rtw_ioctl_rtl.c | 15 +- core/rtw_ioctl_set.c | 516 +- core/rtw_iol.c | 33 +- core/rtw_mem.c | 14 + core/rtw_mi.c | 561 +- core/rtw_mlme.c | 1880 +- core/rtw_mlme_ext.c | 4715 +- core/rtw_mp.c | 694 +- core/rtw_mp_ioctl.c | 9 +- core/rtw_odm.c | 156 +- core/rtw_p2p.c | 375 +- core/rtw_pwrctrl.c | 630 +- core/rtw_recv.c | 2153 +- core/rtw_rf.c | 1072 +- core/rtw_rm.c | 2470 + core/rtw_rm_fsm.c | 998 + core/rtw_rson.c | 595 + core/rtw_sdio.c | 72 +- core/rtw_security.c | 466 +- core/rtw_sreset.c | 90 +- core/rtw_sta_mgt.c | 333 +- core/rtw_tdls.c | 836 +- core/rtw_vht.c | 570 +- core/rtw_wapi.c | 86 +- core/rtw_wapi_sms4.c | 14 + core/rtw_wlan_util.c | 1757 +- core/rtw_xmit.c | 1433 +- hal/HalPwrSeqCmd.c | 40 +- hal/btc/halbtc8821c1ant.c | 6801 +- hal/btc/halbtc8821c1ant.h | 714 +- hal/btc/halbtc8821c2ant.c | 7348 +- hal/btc/halbtc8821c2ant.h | 752 +- hal/btc/halbtc8821cwifionly.c | 27 + hal/btc/halbtc8821cwifionly.h | 19 + hal/btc/halbtcoutsrc.h | 266 +- hal/btc/mp_precomp.h | 61 +- hal/efuse/efuse_mask.h | 50 +- hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c | 31 +- hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h | 31 +- hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.c | 31 +- hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.h | 31 +- hal/efuse/rtl8821c/HalEfuseMask8821C_USB.c | 31 +- hal/efuse/rtl8821c/HalEfuseMask8821C_USB.h | 31 +- hal/hal_btcoex.c | 1723 +- hal/hal_btcoex_wifionly.c | 78 +- hal/hal_com.c | 5278 +- hal/hal_com_c2h.h | 18 +- hal/hal_com_phycfg.c | 2955 +- hal/hal_dm.c | 1182 +- hal/hal_dm.h | 88 +- hal/hal_dm_acs.c | 554 + hal/hal_dm_acs.h | 167 + hal/hal_halmac.c | 3814 +- hal/hal_halmac.h | 167 +- hal/hal_hci/hal_pci.c | 9 +- hal/hal_intf.c | 620 +- hal/hal_mcc.c | 2205 +- hal/hal_mp.c | 738 +- hal/hal_phy.c | 45 +- hal/halmac/halmac_2_platform.h | 35 +- .../halmac_8821c/halmac_8821c_cfg.h | 120 +- .../halmac_8821c/halmac_cfg_wmac_8821c.c | 145 + .../halmac_8821c/halmac_cfg_wmac_8821c.h | 40 + .../halmac_8821c/halmac_common_8821c.c | 182 + .../halmac_8821c/halmac_common_8821c.h | 36 + .../halmac_8821c/halmac_gpio_8821c.c | 846 + .../halmac_8821c/halmac_gpio_8821c.h | 37 + .../halmac_8821c/halmac_init_8821c.c | 890 + .../halmac_8821c/halmac_init_8821c.h | 43 + .../halmac_8821c/halmac_pcie_8821c.c | 356 + .../halmac_8821c/halmac_pcie_8821c.h | 45 + .../halmac_8821c/halmac_phy_8821c.c | 76 + .../halmac_8821c/halmac_pwr_seq_8821c.c | 905 + .../halmac_8821c/halmac_pwr_seq_8821c.h | 37 + hal/halmac/halmac_88xx/halmac_88xx_cfg.h | 181 +- hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c | 395 + hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h | 57 + hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c | 1133 + hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h | 126 + hal/halmac/halmac_88xx/halmac_common_88xx.c | 2895 + hal/halmac/halmac_88xx/halmac_common_88xx.h | 155 + hal/halmac/halmac_88xx/halmac_efuse_88xx.c | 1905 + hal/halmac/halmac_88xx/halmac_efuse_88xx.h | 105 + hal/halmac/halmac_88xx/halmac_flash_88xx.c | 316 + hal/halmac/halmac_88xx/halmac_flash_88xx.h | 39 + hal/halmac/halmac_88xx/halmac_fw_88xx.c | 1167 + hal/halmac/halmac_88xx/halmac_fw_88xx.h | 61 + hal/halmac/halmac_88xx/halmac_gpio_88xx.c | 421 + hal/halmac/halmac_88xx/halmac_gpio_88xx.h | 59 + hal/halmac/halmac_88xx/halmac_init_88xx.c | 992 + hal/halmac/halmac_88xx/halmac_init_88xx.h | 68 + hal/halmac/halmac_88xx/halmac_mimo_88xx.c | 876 + hal/halmac/halmac_88xx/halmac_mimo_88xx.h | 83 + hal/halmac/halmac_88xx/halmac_pcie_88xx.c | 537 + hal/halmac/halmac_88xx/halmac_pcie_88xx.h | 102 + hal/halmac/halmac_api.c | 720 +- hal/halmac/halmac_api.h | 133 +- hal/halmac/halmac_bit2.h | 69675 ++++++++++++---- hal/halmac/halmac_bit_8197f.h | 14214 ++-- hal/halmac/halmac_bit_8814b.h | 27965 +++++-- hal/halmac/halmac_bit_8821c.h | 16849 +++- hal/halmac/halmac_bit_8822b.h | 14719 +++- hal/halmac/halmac_bit_8822c.h | 21838 +++++ hal/halmac/halmac_fw_info.h | 124 +- hal/halmac/halmac_fw_offload_c2h_ap.h | 652 +- hal/halmac/halmac_fw_offload_c2h_nic.h | 482 +- hal/halmac/halmac_fw_offload_h2c_ap.h | 1403 +- hal/halmac/halmac_fw_offload_h2c_nic.h | 987 +- hal/halmac/halmac_gpio_cmd.h | 101 + hal/halmac/halmac_h2c_extra_info_ap.h | 283 +- hal/halmac/halmac_h2c_extra_info_nic.h | 212 +- hal/halmac/halmac_hw_cfg.h | 84 +- hal/halmac/halmac_intf_phy_cmd.h | 31 +- hal/halmac/halmac_original_c2h_ap.h | 980 +- hal/halmac/halmac_original_c2h_nic.h | 657 +- hal/halmac/halmac_original_h2c_ap.h | 2465 +- hal/halmac/halmac_original_h2c_nic.h | 1678 +- hal/halmac/halmac_pcie_reg.h | 28 + hal/halmac/halmac_pwr_seq_cmd.h | 138 +- hal/halmac/halmac_reg2.h | 8324 +- hal/halmac/halmac_reg_8197f.h | 20 +- hal/halmac/halmac_reg_8814b.h | 802 +- hal/halmac/halmac_reg_8821c.h | 115 +- hal/halmac/halmac_reg_8822b.h | 41 +- hal/halmac/halmac_reg_8822c.h | 877 + hal/halmac/halmac_rx_bd_nic.h | 36 +- hal/halmac/halmac_rx_desc_ap.h | 630 +- hal/halmac/halmac_rx_desc_chip.h | 845 +- hal/halmac/halmac_rx_desc_nic.h | 478 +- hal/halmac/halmac_sdio_reg.h | 29 +- hal/halmac/halmac_state_machine.h | 157 + hal/halmac/halmac_tx_bd_nic.h | 105 +- hal/halmac/halmac_tx_desc_ap.h | 2164 +- hal/halmac/halmac_tx_desc_buffer_ap.h | 1078 + hal/halmac/halmac_tx_desc_buffer_chip.h | 509 + hal/halmac/halmac_tx_desc_buffer_nic.h | 491 + hal/halmac/halmac_tx_desc_chip.h | 3688 +- hal/halmac/halmac_tx_desc_ie_ap.h | 1005 + hal/halmac/halmac_tx_desc_ie_chip.h | 438 + hal/halmac/halmac_tx_desc_ie_nic.h | 450 + hal/halmac/halmac_tx_desc_nic.h | 1118 +- hal/halmac/halmac_type.h | 2838 +- hal/halmac/halmac_usb_reg.h | 19 +- hal/led/hal_led.c | 254 + hal/led/hal_pci_led.c | 71 +- hal/phydm/ap_makefile.mk | 174 + hal/phydm/halhwimg.h | 60 +- hal/phydm/halrf/halphyrf_ap.c | 1340 + hal/phydm/halrf/halphyrf_ap.h | 134 + hal/phydm/halrf/halphyrf_ce.c | 918 + hal/phydm/halrf/halphyrf_ce.h | 110 + hal/phydm/halrf/halphyrf_iot.c | 478 + hal/phydm/halrf/halphyrf_iot.h | 124 + hal/phydm/halrf/halphyrf_win.c | 836 + hal/phydm/halrf/halphyrf_win.h | 122 + hal/phydm/halrf/halrf.c | 1806 + hal/phydm/halrf/halrf.h | 471 + hal/phydm/halrf/halrf_debug.c | 259 + hal/phydm/halrf/halrf_debug.h | 123 + hal/phydm/halrf/halrf_dpk.h | 74 + hal/phydm/halrf/halrf_features.h | 43 + hal/phydm/halrf/halrf_iqk.h | 92 + hal/phydm/halrf/halrf_kfree.c | 1013 + hal/phydm/halrf/halrf_kfree.h | 111 + hal/phydm/halrf/halrf_powertracking.c | 152 + hal/phydm/halrf/halrf_powertracking.h | 41 + hal/phydm/halrf/halrf_powertracking_ap.c | 1219 + hal/phydm/halrf/halrf_powertracking_ap.h | 397 + hal/phydm/halrf/halrf_powertracking_ce.c | 840 + hal/phydm/halrf/halrf_powertracking_ce.h | 325 + hal/phydm/halrf/halrf_powertracking_iot.c | 690 + hal/phydm/halrf/halrf_powertracking_iot.h | 347 + hal/phydm/halrf/halrf_powertracking_win.c | 859 + hal/phydm/halrf/halrf_powertracking_win.h | 302 + hal/phydm/halrf/halrf_psd.c | 301 + hal/phydm/halrf/halrf_psd.h | 52 + hal/phydm/halrf/halrf_txgapcal.c | 298 + hal/phydm/halrf/halrf_txgapcal.h | 31 + hal/phydm/halrf/rtl8821c/halrf_8821c.c | 469 + hal/phydm/halrf/rtl8821c/halrf_8821c.h | 60 + hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.c | 3777 + hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.h | 62 + hal/phydm/mp_precomp.h | 17 +- hal/phydm/phydm.c | 5212 +- hal/phydm/phydm.h | 1775 +- hal/phydm/phydm.mk | 217 + hal/phydm/phydm_adaptivity.c | 1504 +- hal/phydm/phydm_adaptivity.h | 263 +- hal/phydm/phydm_adc_sampling.c | 1383 +- hal/phydm/phydm_adc_sampling.h | 149 +- hal/phydm/phydm_antdect.c | 1008 +- hal/phydm/phydm_antdect.h | 91 +- hal/phydm/phydm_antdiv.c | 8464 +- hal/phydm/phydm_antdiv.h | 642 +- hal/phydm/phydm_api.c | 2410 + hal/phydm/phydm_api.h | 168 + hal/phydm/phydm_auto_dbg.c | 671 + hal/phydm/phydm_auto_dbg.h | 113 + hal/phydm/phydm_beamforming.c | 2303 +- hal/phydm/phydm_beamforming.h | 459 +- hal/phydm/phydm_cck_pd.c | 1076 + hal/phydm/phydm_cck_pd.h | 154 + hal/phydm/phydm_ccx.c | 2049 +- hal/phydm/phydm_ccx.h | 310 +- hal/phydm/phydm_cfotracking.c | 666 +- hal/phydm/phydm_cfotracking.h | 86 +- hal/phydm/phydm_debug.c | 6060 +- hal/phydm/phydm_debug.h | 669 +- hal/phydm/phydm_dfs.c | 1855 +- hal/phydm/phydm_dfs.h | 207 +- hal/phydm/phydm_dig.c | 4140 +- hal/phydm/phydm_dig.h | 504 +- hal/phydm/phydm_dynamictxpower.c | 852 +- hal/phydm/phydm_dynamictxpower.h | 163 +- hal/phydm/phydm_features.h | 218 +- hal/phydm/phydm_features_ap.h | 196 + hal/phydm/phydm_features_ce.h | 205 + hal/phydm/phydm_features_ce2_kernel.h | 84 + hal/phydm/phydm_features_iot.h | 174 + hal/phydm/phydm_features_win.h | 185 + hal/phydm/phydm_hwconfig.c | 4027 +- hal/phydm/phydm_hwconfig.h | 587 +- hal/phydm/phydm_interface.c | 1364 +- hal/phydm/phydm_interface.h | 563 +- hal/phydm/phydm_lna_sat.c | 1354 + hal/phydm/phydm_lna_sat.h | 173 + hal/phydm/phydm_math_lib.c | 211 + hal/phydm/phydm_math_lib.h | 114 + hal/phydm/phydm_mp.c | 317 + hal/phydm/phydm_mp.h | 94 + hal/phydm/phydm_noisemonitor.c | 501 +- hal/phydm/phydm_noisemonitor.h | 49 +- hal/phydm/phydm_pathdiv.c | 911 +- hal/phydm/phydm_pathdiv.h | 268 +- hal/phydm/phydm_phystatus.c | 3089 + hal/phydm/phydm_phystatus.h | 1137 + hal/phydm/phydm_pmac_tx_setting.c | 522 + hal/phydm/phydm_pmac_tx_setting.h | 149 + hal/phydm/phydm_pow_train.c | 183 + hal/phydm/phydm_pow_train.h | 84 + hal/phydm/phydm_pre_define.h | 1019 +- hal/phydm/phydm_precomp.h | 306 +- hal/phydm/phydm_primary_cca.c | 173 + hal/phydm/phydm_primary_cca.h | 87 + hal/phydm/phydm_psd.c | 824 +- hal/phydm/phydm_psd.h | 169 +- hal/phydm/phydm_rainfo.c | 4677 +- hal/phydm/phydm_rainfo.h | 675 +- hal/phydm/phydm_reg.h | 203 +- hal/phydm/phydm_regdefine11ac.h | 88 +- hal/phydm/phydm_regdefine11n.h | 201 +- hal/phydm/phydm_regtable.h | 725 + hal/phydm/phydm_rssi_monitor.c | 170 + hal/phydm/phydm_rssi_monitor.h | 55 + hal/phydm/phydm_smt_ant.c | 2253 + hal/phydm/phydm_smt_ant.h | 210 + hal/phydm/phydm_soml.c | 963 + hal/phydm/phydm_soml.h | 210 + hal/phydm/phydm_types.h | 230 +- hal/phydm/rtl8821c/halhwimg8821c_bb.c | 2924 +- hal/phydm/rtl8821c/halhwimg8821c_bb.h | 92 +- hal/phydm/rtl8821c/halhwimg8821c_mac.c | 164 +- hal/phydm/rtl8821c/halhwimg8821c_mac.h | 50 +- hal/phydm/rtl8821c/halhwimg8821c_rf.c | 4868 +- hal/phydm/rtl8821c/halhwimg8821c_rf.h | 89 +- hal/phydm/rtl8821c/mp_precomp.h | 14 + hal/phydm/rtl8821c/phydm_hal_api8821c.c | 1211 +- hal/phydm/rtl8821c/phydm_hal_api8821c.h | 233 +- hal/phydm/rtl8821c/phydm_regconfig8821c.c | 291 +- hal/phydm/rtl8821c/phydm_regconfig8821c.h | 96 +- hal/phydm/rtl8821c/version_rtl8821c.h | 38 +- hal/phydm/sd4_phydm_2_kernel.mk | 188 + hal/phydm/txbf/halcomtxbf.c | 550 +- hal/phydm/txbf/halcomtxbf.h | 188 +- hal/phydm/txbf/haltxbf8192e.c | 403 +- hal/phydm/txbf/haltxbf8192e.h | 89 +- hal/phydm/txbf/haltxbf8814a.c | 619 +- hal/phydm/txbf/haltxbf8814a.h | 130 +- hal/phydm/txbf/haltxbf8822b.c | 953 +- hal/phydm/txbf/haltxbf8822b.h | 109 +- hal/phydm/txbf/haltxbfinterface.c | 1296 +- hal/phydm/txbf/haltxbfinterface.h | 192 +- hal/phydm/txbf/haltxbfjaguar.c | 516 +- hal/phydm/txbf/haltxbfjaguar.h | 116 +- hal/phydm/txbf/phydm_hal_txbf_api.c | 126 +- hal/phydm/txbf/phydm_hal_txbf_api.h | 92 +- hal/rtl8821c/hal8821c_fw.c | 53388 +++++++----- hal/rtl8821c/hal8821c_fw.h | 17 +- hal/rtl8821c/pci/rtl8821ce.h | 30 +- hal/rtl8821c/pci/rtl8821ce_halinit.c | 35 +- hal/rtl8821c/pci/rtl8821ce_halmac.c | 167 +- hal/rtl8821c/pci/rtl8821ce_io.c | 9 +- hal/rtl8821c/pci/rtl8821ce_led.c | 19 +- hal/rtl8821c/pci/rtl8821ce_ops.c | 107 +- hal/rtl8821c/pci/rtl8821ce_recv.c | 42 +- hal/rtl8821c/pci/rtl8821ce_xmit.c | 352 +- hal/rtl8821c/rtl8821c.h | 70 +- hal/rtl8821c/rtl8821c_cmd.c | 1182 +- hal/rtl8821c/rtl8821c_dm.c | 188 +- hal/rtl8821c/rtl8821c_halinit.c | 97 +- hal/rtl8821c/rtl8821c_mac.c | 121 +- hal/rtl8821c/rtl8821c_ops.c | 1840 +- hal/rtl8821c/rtl8821c_phy.c | 579 +- halmac.mk | 68 + ifcfg-wlan0 | 6 +- include/Hal8188EPhyCfg.h | 25 +- include/Hal8188EPhyReg.h | 9 +- include/Hal8188EPwrSeq.h | 11 +- include/Hal8188FPhyCfg.h | 25 +- include/Hal8188FPhyReg.h | 9 +- include/Hal8188FPwrSeq.h | 14 + include/Hal8192EPhyCfg.h | 21 +- include/Hal8192EPhyReg.h | 14 + include/Hal8192EPwrSeq.h | 14 + include/Hal8192FPhyCfg.h | 131 + include/Hal8192FPhyReg.h | 1134 + include/Hal8192FPwrSeq.h | 221 + include/Hal8703BPhyCfg.h | 29 +- include/Hal8703BPhyReg.h | 9 +- include/Hal8703BPwrSeq.h | 14 + include/Hal8710BPhyCfg.h | 127 + include/Hal8710BPhyReg.h | 1134 + include/Hal8710BPwrSeq.h | 167 + include/Hal8723BPhyCfg.h | 25 +- include/Hal8723BPhyReg.h | 9 +- include/Hal8723BPwrSeq.h | 14 + include/Hal8723DPhyCfg.h | 27 +- include/Hal8723DPhyReg.h | 9 +- include/Hal8723DPwrSeq.h | 15 +- include/Hal8723PwrSeq.h | 14 + include/Hal8812PhyCfg.h | 29 +- include/Hal8812PhyReg.h | 11 +- include/Hal8812PwrSeq.h | 19 +- include/Hal8814PhyCfg.h | 37 +- include/Hal8814PhyReg.h | 11 +- include/Hal8814PwrSeq.h | 11 +- include/Hal8821APwrSeq.h | 14 + include/HalPwrSeqCmd.h | 9 +- include/HalVerDef.h | 26 +- include/autoconf.h | 97 +- include/basic_types.h | 50 +- include/byteorder/big_endian.h | 9 +- include/byteorder/generic.h | 9 +- include/byteorder/little_endian.h | 9 +- include/byteorder/swab.h | 9 +- include/byteorder/swabb.h | 9 +- include/circ_buf.h | 11 +- include/cmd_osdep.h | 9 +- include/cmn_info/rtw_sta_info.h | 250 + include/custom_gpio.h | 14 + include/drv_conf.h | 208 +- include/drv_types.h | 397 +- include/drv_types_ce.h | 9 +- include/drv_types_gspi.h | 9 +- include/drv_types_linux.h | 9 +- include/drv_types_pci.h | 9 +- include/drv_types_sdio.h | 9 +- include/drv_types_xp.h | 9 +- include/ethernet.h | 9 +- include/gspi_hal.h | 9 +- include/gspi_ops.h | 9 +- include/gspi_ops_linux.h | 9 +- include/gspi_osintf.h | 9 +- include/h2clbk.h | 9 +- include/hal_btcoex.h | 12 +- include/hal_btcoex_wifionly.h | 36 +- include/hal_com.h | 214 +- include/hal_com_h2c.h | 138 +- include/hal_com_led.h | 123 +- include/hal_com_phycfg.h | 137 +- include/hal_com_reg.h | 102 +- include/hal_data.h | 239 +- include/hal_gspi.h | 9 +- include/hal_ic_cfg.h | 106 +- include/hal_intf.h | 169 +- include/hal_pg.h | 161 +- include/hal_phy.h | 51 +- include/hal_phy_reg.h | 9 +- include/hal_sdio.h | 36 +- include/ieee80211.h | 303 +- include/ieee80211_ext.h | 9 +- include/if_ether.h | 9 +- include/ip.h | 9 +- include/linux/wireless.h | 9 +- include/mlme_osdep.h | 14 +- include/mp_custom_oid.h | 9 +- include/nic_spec.h | 9 +- include/osdep_intf.h | 14 +- include/osdep_service.h | 163 +- include/osdep_service_bsd.h | 1442 +- include/osdep_service_ce.h | 321 +- include/osdep_service_linux.h | 140 +- include/osdep_service_xp.h | 363 +- include/pci_hal.h | 13 +- include/pci_ops.h | 20 +- include/pci_osintf.h | 12 +- include/recv_osdep.h | 19 +- include/rtl8188e_cmd.h | 18 +- include/rtl8188e_dm.h | 9 +- include/rtl8188e_hal.h | 40 +- include/rtl8188e_led.h | 11 +- include/rtl8188e_recv.h | 15 +- include/rtl8188e_rf.h | 11 +- include/rtl8188e_spec.h | 8 +- include/rtl8188e_sreset.h | 9 +- include/rtl8188e_xmit.h | 9 +- include/rtl8188f_cmd.h | 17 +- include/rtl8188f_dm.h | 12 +- include/rtl8188f_hal.h | 33 +- include/rtl8188f_led.h | 11 +- include/rtl8188f_recv.h | 9 +- include/rtl8188f_rf.h | 11 +- include/rtl8188f_spec.h | 20 +- include/rtl8188f_sreset.h | 9 +- include/rtl8188f_xmit.h | 20 +- include/rtl8192e_cmd.h | 18 +- include/rtl8192e_dm.h | 9 +- include/rtl8192e_hal.h | 32 +- include/rtl8192e_led.h | 12 +- include/rtl8192e_recv.h | 20 +- include/rtl8192e_rf.h | 11 +- include/rtl8192e_spec.h | 8 +- include/rtl8192e_sreset.h | 9 +- include/rtl8192e_xmit.h | 17 +- include/rtl8192f_cmd.h | 194 + include/rtl8192f_dm.h | 28 + include/rtl8192f_hal.h | 315 + include/rtl8192f_led.h | 42 + include/rtl8192f_recv.h | 111 + include/rtl8192f_rf.h | 22 + include/rtl8192f_spec.h | 534 + include/rtl8192f_sreset.h | 24 + include/rtl8192f_xmit.h | 531 + include/rtl8703b_cmd.h | 17 +- include/rtl8703b_dm.h | 12 +- include/rtl8703b_hal.h | 33 +- include/rtl8703b_led.h | 14 +- include/rtl8703b_recv.h | 9 +- include/rtl8703b_rf.h | 11 +- include/rtl8703b_spec.h | 8 +- include/rtl8703b_sreset.h | 9 +- include/rtl8703b_xmit.h | 17 +- include/rtl8710b_cmd.h | 175 + include/rtl8710b_dm.h | 39 + include/rtl8710b_hal.h | 277 + include/rtl8710b_led.h | 44 + include/rtl8710b_lps_poff.h | 56 + include/rtl8710b_recv.h | 85 + include/rtl8710b_rf.h | 20 + include/rtl8710b_spec.h | 481 + include/rtl8710b_sreset.h | 24 + include/rtl8710b_xmit.h | 522 + include/rtl8723b_cmd.h | 17 +- include/rtl8723b_dm.h | 13 +- include/rtl8723b_hal.h | 35 +- include/rtl8723b_led.h | 12 +- include/rtl8723b_recv.h | 9 +- include/rtl8723b_rf.h | 11 +- include/rtl8723b_spec.h | 8 +- include/rtl8723b_sreset.h | 9 +- include/rtl8723b_xmit.h | 17 +- include/rtl8723d_cmd.h | 38 +- include/rtl8723d_dm.h | 12 +- include/rtl8723d_hal.h | 41 +- include/rtl8723d_led.h | 12 +- include/rtl8723d_lps_poff.h | 9 +- include/rtl8723d_recv.h | 10 +- include/rtl8723d_rf.h | 11 +- include/rtl8723d_spec.h | 14 +- include/rtl8723d_sreset.h | 9 +- include/rtl8723d_xmit.h | 27 +- include/rtl8812a_cmd.h | 19 +- include/rtl8812a_dm.h | 9 +- include/rtl8812a_hal.h | 49 +- include/rtl8812a_led.h | 20 +- include/rtl8812a_recv.h | 9 +- include/rtl8812a_rf.h | 11 +- include/rtl8812a_spec.h | 8 +- include/rtl8812a_sreset.h | 9 +- include/rtl8812a_xmit.h | 10 +- include/rtl8814a_cmd.h | 12 +- include/rtl8814a_dm.h | 9 +- include/rtl8814a_hal.h | 27 +- include/rtl8814a_led.h | 12 +- include/rtl8814a_recv.h | 9 +- include/rtl8814a_rf.h | 11 +- include/rtl8814a_spec.h | 15 +- include/rtl8814a_sreset.h | 9 +- include/rtl8814a_xmit.h | 20 +- include/rtl8821a_spec.h | 8 +- include/rtl8821a_xmit.h | 9 +- include/rtl8821c_dm.h | 11 +- include/rtl8821c_hal.h | 19 +- include/rtl8821c_spec.h | 30 +- include/rtl8821ce_hal.h | 9 +- include/rtl8821cs_hal.h | 9 +- include/rtl8821cu_hal.h | 9 +- include/rtl8822b_hal.h | 38 +- include/rtl8822be_hal.h | 11 +- include/rtl8822bs_hal.h | 13 +- include/rtl8822bu_hal.h | 16 +- include/rtw_android.h | 14 +- include/rtw_ap.h | 54 +- include/rtw_beamforming.h | 39 +- include/rtw_br_ext.h | 9 +- include/rtw_bt_mp.h | 11 +- include/rtw_btcoex.h | 18 +- include/rtw_btcoex_wifionly.h | 11 +- include/rtw_byteorder.h | 9 +- include/rtw_cmd.h | 119 +- include/rtw_debug.h | 222 +- include/rtw_eeprom.h | 9 +- include/rtw_efuse.h | 26 +- include/rtw_event.h | 9 +- include/rtw_ht.h | 64 +- include/rtw_io.h | 23 +- include/rtw_ioctl.h | 9 +- include/rtw_ioctl_query.h | 9 +- include/rtw_ioctl_rtl.h | 9 +- include/rtw_ioctl_set.h | 14 +- include/rtw_iol.h | 9 +- include/rtw_mcc.h | 81 +- include/rtw_mem.h | 9 +- include/rtw_mi.h | 126 +- include/rtw_mlme.h | 451 +- include/rtw_mlme_ext.h | 496 +- include/rtw_mp.h | 80 +- include/rtw_mp_ioctl.h | 9 +- include/rtw_mp_phy_regdef.h | 9 +- include/rtw_odm.h | 68 +- include/rtw_p2p.h | 17 +- include/rtw_pwrctrl.h | 82 +- include/rtw_qos.h | 48 +- include/rtw_recv.h | 214 +- include/rtw_rf.h | 143 +- include/rtw_rm.h | 88 + include/rtw_rm_fsm.h | 389 + include/rtw_rson.h | 61 + include/rtw_sdio.h | 8 +- include/rtw_security.h | 63 +- include/rtw_sreset.h | 24 +- include/rtw_tdls.h | 72 +- include/rtw_version.h | 4 +- include/rtw_vht.h | 70 +- include/rtw_wapi.h | 18 +- include/rtw_wifi_regd.h | 15 +- include/rtw_xmit.h | 100 +- include/sdio_hal.h | 17 +- include/sdio_ops.h | 78 +- include/sdio_ops_ce.h | 9 +- include/sdio_ops_linux.h | 20 +- include/sdio_ops_xp.h | 9 +- include/sdio_osintf.h | 9 +- include/sta_info.h | 274 +- include/usb_hal.h | 21 +- include/usb_ops.h | 36 +- include/usb_ops_linux.h | 9 +- include/usb_osintf.h | 9 +- include/usb_vendor_req.h | 9 +- include/wifi.h | 93 +- include/wlan_bssdef.h | 41 +- include/xmit_osdep.h | 9 +- os_dep/linux/custom_gpio_linux.c | 10 +- os_dep/linux/ioctl_cfg80211.c | 4441 +- os_dep/linux/ioctl_cfg80211.h | 90 +- os_dep/linux/ioctl_linux.c | 1782 +- os_dep/linux/ioctl_mp.c | 480 +- os_dep/linux/mlme_linux.c | 45 +- os_dep/linux/os_intfs.c | 1453 +- os_dep/linux/pci_intf.c | 180 +- os_dep/linux/pci_ops_linux.c | 8 +- os_dep/linux/recv_linux.c | 380 +- os_dep/linux/rhashtable.c | 844 + os_dep/linux/rhashtable.h | 827 + os_dep/linux/rtw_android.c | 107 +- os_dep/linux/rtw_cfgvendor.c | 918 +- os_dep/linux/rtw_cfgvendor.h | 512 +- os_dep/linux/rtw_proc.c | 1632 +- os_dep/linux/rtw_proc.h | 9 +- os_dep/linux/rtw_rhashtable.c | 74 + os_dep/linux/rtw_rhashtable.h | 55 + os_dep/linux/wifi_regd.c | 260 +- os_dep/linux/xmit_linux.c | 131 +- os_dep/osdep_service.c | 576 +- platform/custom_country_chplan.h | 11 +- platform/platform_ARM_SUN50IW1P1_sdio.c | 9 +- platform/platform_ARM_SUNnI_sdio.c | 9 +- platform/platform_ARM_SUNxI_sdio.c | 9 +- platform/platform_ARM_SUNxI_usb.c | 9 +- platform/platform_ARM_WMT_sdio.c | 9 +- platform/platform_RTK_DMP_usb.c | 9 +- platform/platform_aml_s905_sdio.c | 54 + platform/platform_aml_s905_sdio.h | 28 + platform/platform_arm_act_sdio.c | 9 +- platform/platform_hisilicon_hi3798_sdio.c | 110 + platform/platform_hisilicon_hi3798_sdio.h | 28 + platform/platform_ops.c | 9 +- platform/platform_ops.h | 9 +- platform/platform_sprd_sdio.c | 9 +- platform/platform_zte_zx296716_sdio.c | 53 + platform/platform_zte_zx296716_sdio.h | 25 + rtl8821c.mk | 63 +- 624 files changed, 363611 insertions(+), 132765 deletions(-) create mode 100644 core/mesh/rtw_mesh.c create mode 100644 core/mesh/rtw_mesh.h create mode 100644 core/mesh/rtw_mesh_hwmp.c create mode 100644 core/mesh/rtw_mesh_hwmp.h create mode 100644 core/mesh/rtw_mesh_pathtbl.c create mode 100644 core/mesh/rtw_mesh_pathtbl.h create mode 100644 core/rtw_chplan.c create mode 100644 core/rtw_chplan.h create mode 100644 core/rtw_rm.c create mode 100644 core/rtw_rm_fsm.c create mode 100644 core/rtw_rson.c create mode 100644 hal/hal_dm_acs.c create mode 100644 hal/hal_dm_acs.h create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.c create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.h create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.c create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.h create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.c create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.h create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.c create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.h create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.c create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.h create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_phy_8821c.c create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.c create mode 100644 hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.h create mode 100644 hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_common_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_common_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_efuse_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_efuse_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_flash_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_flash_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_fw_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_fw_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_gpio_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_gpio_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_init_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_init_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_mimo_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_mimo_88xx.h create mode 100644 hal/halmac/halmac_88xx/halmac_pcie_88xx.c create mode 100644 hal/halmac/halmac_88xx/halmac_pcie_88xx.h create mode 100644 hal/halmac/halmac_bit_8822c.h create mode 100644 hal/halmac/halmac_gpio_cmd.h create mode 100644 hal/halmac/halmac_reg_8822c.h create mode 100644 hal/halmac/halmac_state_machine.h create mode 100644 hal/halmac/halmac_tx_desc_buffer_ap.h create mode 100644 hal/halmac/halmac_tx_desc_buffer_chip.h create mode 100644 hal/halmac/halmac_tx_desc_buffer_nic.h create mode 100644 hal/halmac/halmac_tx_desc_ie_ap.h create mode 100644 hal/halmac/halmac_tx_desc_ie_chip.h create mode 100644 hal/halmac/halmac_tx_desc_ie_nic.h create mode 100644 hal/led/hal_led.c create mode 100644 hal/phydm/ap_makefile.mk create mode 100644 hal/phydm/halrf/halphyrf_ap.c create mode 100644 hal/phydm/halrf/halphyrf_ap.h create mode 100644 hal/phydm/halrf/halphyrf_ce.c create mode 100644 hal/phydm/halrf/halphyrf_ce.h create mode 100644 hal/phydm/halrf/halphyrf_iot.c create mode 100644 hal/phydm/halrf/halphyrf_iot.h create mode 100644 hal/phydm/halrf/halphyrf_win.c create mode 100644 hal/phydm/halrf/halphyrf_win.h create mode 100644 hal/phydm/halrf/halrf.c create mode 100644 hal/phydm/halrf/halrf.h create mode 100644 hal/phydm/halrf/halrf_debug.c create mode 100644 hal/phydm/halrf/halrf_debug.h create mode 100644 hal/phydm/halrf/halrf_dpk.h create mode 100644 hal/phydm/halrf/halrf_features.h create mode 100644 hal/phydm/halrf/halrf_iqk.h create mode 100644 hal/phydm/halrf/halrf_kfree.c create mode 100644 hal/phydm/halrf/halrf_kfree.h create mode 100644 hal/phydm/halrf/halrf_powertracking.c create mode 100644 hal/phydm/halrf/halrf_powertracking.h create mode 100644 hal/phydm/halrf/halrf_powertracking_ap.c create mode 100644 hal/phydm/halrf/halrf_powertracking_ap.h create mode 100644 hal/phydm/halrf/halrf_powertracking_ce.c create mode 100644 hal/phydm/halrf/halrf_powertracking_ce.h create mode 100644 hal/phydm/halrf/halrf_powertracking_iot.c create mode 100644 hal/phydm/halrf/halrf_powertracking_iot.h create mode 100644 hal/phydm/halrf/halrf_powertracking_win.c create mode 100644 hal/phydm/halrf/halrf_powertracking_win.h create mode 100644 hal/phydm/halrf/halrf_psd.c create mode 100644 hal/phydm/halrf/halrf_psd.h create mode 100644 hal/phydm/halrf/halrf_txgapcal.c create mode 100644 hal/phydm/halrf/halrf_txgapcal.h create mode 100644 hal/phydm/halrf/rtl8821c/halrf_8821c.c create mode 100644 hal/phydm/halrf/rtl8821c/halrf_8821c.h create mode 100644 hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.c create mode 100644 hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.h create mode 100644 hal/phydm/phydm.mk create mode 100644 hal/phydm/phydm_api.c create mode 100644 hal/phydm/phydm_api.h create mode 100644 hal/phydm/phydm_auto_dbg.c create mode 100644 hal/phydm/phydm_auto_dbg.h create mode 100644 hal/phydm/phydm_cck_pd.c create mode 100644 hal/phydm/phydm_cck_pd.h create mode 100644 hal/phydm/phydm_features_ap.h create mode 100644 hal/phydm/phydm_features_ce.h create mode 100644 hal/phydm/phydm_features_ce2_kernel.h create mode 100644 hal/phydm/phydm_features_iot.h create mode 100644 hal/phydm/phydm_features_win.h create mode 100644 hal/phydm/phydm_lna_sat.c create mode 100644 hal/phydm/phydm_lna_sat.h create mode 100644 hal/phydm/phydm_math_lib.c create mode 100644 hal/phydm/phydm_math_lib.h create mode 100644 hal/phydm/phydm_mp.c create mode 100644 hal/phydm/phydm_mp.h create mode 100644 hal/phydm/phydm_phystatus.c create mode 100644 hal/phydm/phydm_phystatus.h create mode 100644 hal/phydm/phydm_pmac_tx_setting.c create mode 100644 hal/phydm/phydm_pmac_tx_setting.h create mode 100644 hal/phydm/phydm_pow_train.c create mode 100644 hal/phydm/phydm_pow_train.h create mode 100644 hal/phydm/phydm_primary_cca.c create mode 100644 hal/phydm/phydm_primary_cca.h create mode 100644 hal/phydm/phydm_regtable.h create mode 100644 hal/phydm/phydm_rssi_monitor.c create mode 100644 hal/phydm/phydm_rssi_monitor.h create mode 100644 hal/phydm/phydm_smt_ant.c create mode 100644 hal/phydm/phydm_smt_ant.h create mode 100644 hal/phydm/phydm_soml.c create mode 100644 hal/phydm/phydm_soml.h create mode 100644 hal/phydm/rtl8821c/mp_precomp.h create mode 100644 hal/phydm/sd4_phydm_2_kernel.mk create mode 100644 halmac.mk create mode 100644 include/Hal8192FPhyCfg.h create mode 100644 include/Hal8192FPhyReg.h create mode 100644 include/Hal8192FPwrSeq.h create mode 100644 include/Hal8710BPhyCfg.h create mode 100644 include/Hal8710BPhyReg.h create mode 100644 include/Hal8710BPwrSeq.h create mode 100644 include/cmn_info/rtw_sta_info.h create mode 100644 include/rtl8192f_cmd.h create mode 100644 include/rtl8192f_dm.h create mode 100644 include/rtl8192f_hal.h create mode 100644 include/rtl8192f_led.h create mode 100644 include/rtl8192f_recv.h create mode 100644 include/rtl8192f_rf.h create mode 100644 include/rtl8192f_spec.h create mode 100644 include/rtl8192f_sreset.h create mode 100644 include/rtl8192f_xmit.h create mode 100644 include/rtl8710b_cmd.h create mode 100644 include/rtl8710b_dm.h create mode 100644 include/rtl8710b_hal.h create mode 100644 include/rtl8710b_led.h create mode 100644 include/rtl8710b_lps_poff.h create mode 100644 include/rtl8710b_recv.h create mode 100644 include/rtl8710b_rf.h create mode 100644 include/rtl8710b_spec.h create mode 100644 include/rtl8710b_sreset.h create mode 100644 include/rtl8710b_xmit.h create mode 100644 include/rtw_rm.h create mode 100644 include/rtw_rm_fsm.h create mode 100644 include/rtw_rson.h create mode 100644 os_dep/linux/rhashtable.c create mode 100644 os_dep/linux/rhashtable.h create mode 100644 os_dep/linux/rtw_rhashtable.c create mode 100644 os_dep/linux/rtw_rhashtable.h create mode 100644 platform/platform_aml_s905_sdio.c create mode 100644 platform/platform_aml_s905_sdio.h create mode 100644 platform/platform_hisilicon_hi3798_sdio.c create mode 100644 platform/platform_hisilicon_hi3798_sdio.h create mode 100644 platform/platform_zte_zx296716_sdio.c create mode 100644 platform/platform_zte_zx296716_sdio.h diff --git a/Makefile b/Makefile index 7c011c8..9a88cdc 100755 --- a/Makefile +++ b/Makefile @@ -20,8 +20,7 @@ ifeq ($(GCC_VER_49),1) EXTRA_CFLAGS += -Wno-date-time # Fix compile error && warning on gcc 4.9 and later endif -EXTRA_CFLAGS += -I$(src)/include -EXTRA_CFLAGS += -I$(src)/hal/phydm +EXTRA_CFLAGS += -I$(srctree)/$(src)/include EXTRA_LDFLAGS += --strip-debug @@ -37,9 +36,12 @@ CONFIG_RTL8723B = n CONFIG_RTL8814A = n CONFIG_RTL8723C = n CONFIG_RTL8188F = n +CONFIG_RTL8188GTV = n CONFIG_RTL8822B = n CONFIG_RTL8723D = n CONFIG_RTL8821C = y +CONFIG_RTL8710B = n +CONFIG_RTL8192F = n ######################### Interface ########################### CONFIG_USB_HCI = n CONFIG_PCI_HCI = y @@ -56,10 +58,11 @@ CONFIG_INTEL_WIDI = n CONFIG_WAPI_SUPPORT = n CONFIG_EFUSE_CONFIG_FILE = y CONFIG_EXT_CLK = n -CONFIG_TRAFFIC_PROTECT = y +CONFIG_TRAFFIC_PROTECT = n CONFIG_LOAD_PHY_PARA_FROM_FILE = y CONFIG_TXPWR_BY_RATE_EN = auto CONFIG_TXPWR_LIMIT_EN = auto +CONFIG_RTW_CHPLAN = 0xFF CONFIG_RTW_ADAPTIVITY_EN = disable CONFIG_RTW_ADAPTIVITY_MODE = normal CONFIG_SIGNAL_SCALE_MAPPING = n @@ -72,17 +75,27 @@ CONFIG_MCC_MODE = n CONFIG_APPEND_VENDOR_IE_ENABLE = n CONFIG_RTW_NAPI = y CONFIG_RTW_GRO = y +CONFIG_RTW_NETIF_SG = y +CONFIG_TX_CSUM_OFFLOAD = n +CONFIG_RTW_IPCAM_APPLICATION = n +CONFIG_RTW_REPEATER_SON = n +CONFIG_RTW_WIFI_HAL = n +CONFIG_ICMP_VOQ = n ########################## Debug ########################### CONFIG_RTW_DEBUG = y # default log level is _DRV_INFO_ = 4, # please refer to "How_to_set_driver_debug_log_level.doc" to set the available level. -CONFIG_RTW_LOG_LEVEL = 3 +CONFIG_RTW_LOG_LEVEL = 4 ######################## Wake On Lan ########################## CONFIG_WOWLAN = n +#bit2: deauth, bit1: unicast, bit0: magic pkt. +CONFIG_WAKEUP_TYPE = 0x7 CONFIG_GPIO_WAKEUP = n -CONFIG_DEFAULT_PATTERNS_EN = n CONFIG_WAKEUP_GPIO_IDX = default -CONFIG_HIGH_ACTIVE = n +CONFIG_HIGH_ACTIVE_DEV2HST = n +######### only for USB ######### +CONFIG_ONE_PIN_GPIO = n +CONFIG_HIGH_ACTIVE_HST2DEV = n CONFIG_PNO_SUPPORT = n CONFIG_PNO_SET_DEBUG = n CONFIG_AP_WOWLAN = n @@ -134,22 +147,30 @@ CONFIG_PLATFORM_ACTIONS_ATV5201 = n CONFIG_PLATFORM_ACTIONS_ATM705X = n CONFIG_PLATFORM_ARM_SUN50IW1P1 = n CONFIG_PLATFORM_ARM_RTD299X = n +CONFIG_PLATFORM_ARM_LGE = n CONFIG_PLATFORM_ARM_SPREADTRUM_6820 = n CONFIG_PLATFORM_ARM_SPREADTRUM_8810 = n CONFIG_PLATFORM_ARM_WMT = n CONFIG_PLATFORM_TI_DM365 = n CONFIG_PLATFORM_MOZART = n CONFIG_PLATFORM_RTK119X = n +CONFIG_PLATFORM_RTK119X_AM = n CONFIG_PLATFORM_RTK129X = n +CONFIG_PLATFORM_RTK390X = n CONFIG_PLATFORM_NOVATEK_NT72668 = n CONFIG_PLATFORM_HISILICON = n +CONFIG_PLATFORM_HISILICON_HI3798 = n CONFIG_PLATFORM_NV_TK1 = n +CONFIG_PLATFORM_NV_TK1_UBUNTU = n CONFIG_PLATFORM_RTL8197D = n -############################################################### +CONFIG_PLATFORM_AML_S905 = n +CONFIG_PLATFORM_ZTE_ZX296716 = n +########### CUSTOMER ################################ +CONFIG_CUSTOMER_HUAWEI_GENERAL = n CONFIG_DRVEXT_MODULE = n -export TopDIR ?= $(shell pwd) +export TopDIR ?= $(srctree)/$(src) ########### COMMON ################################# ifeq ($(CONFIG_GSPI_HCI), y) @@ -181,7 +202,8 @@ _OS_INTFS_FILES := os_dep/osdep_service.o \ os_dep/linux/rtw_cfgvendor.o \ os_dep/linux/wifi_regd.o \ os_dep/linux/rtw_android.o \ - os_dep/linux/rtw_proc.o + os_dep/linux/rtw_proc.o \ + os_dep/linux/rtw_rhashtable.o ifeq ($(CONFIG_MP_INCLUDED), y) _OS_INTFS_FILES += os_dep/linux/ioctl_mp.o @@ -203,66 +225,20 @@ _HAL_INTFS_FILES := hal/hal_intf.o \ hal/hal_com_phycfg.o \ hal/hal_phy.o \ hal/hal_dm.o \ + hal/hal_dm_acs.o \ hal/hal_btcoex_wifionly.o \ hal/hal_btcoex.o \ hal/hal_mp.o \ hal/hal_mcc.o \ hal/hal_hci/hal_$(HCI_NAME).o \ + hal/led/hal_led.o \ hal/led/hal_$(HCI_NAME)_led.o - -_OUTSRC_FILES := hal/phydm/phydm_debug.o \ - hal/phydm/phydm_antdiv.o\ - hal/phydm/phydm_antdect.o\ - hal/phydm/phydm_interface.o\ - hal/phydm/phydm_hwconfig.o\ - hal/phydm/phydm.o\ - hal/phydm/halphyrf_ce.o\ - hal/phydm/phydm_dig.o\ - hal/phydm/phydm_pathdiv.o\ - hal/phydm/phydm_rainfo.o\ - hal/phydm/phydm_dynamicbbpowersaving.o\ - hal/phydm/phydm_powertracking_ce.o\ - hal/phydm/phydm_dynamictxpower.o\ - hal/phydm/phydm_adaptivity.o\ - hal/phydm/phydm_cfotracking.o\ - hal/phydm/phydm_noisemonitor.o\ - hal/phydm/phydm_acs.o\ - hal/phydm/phydm_beamforming.o\ - hal/phydm/phydm_dfs.o\ - hal/phydm/txbf/halcomtxbf.o\ - hal/phydm/txbf/haltxbfinterface.o\ - hal/phydm/txbf/phydm_hal_txbf_api.o\ - hal/phydm/phydm_adc_sampling.o\ - hal/phydm/phydm_kfree.o\ - hal/phydm/phydm_ccx.o\ - hal/phydm/phydm_psd.o - -EXTRA_CFLAGS += -I$(src)/platform -_PLATFORM_FILES := platform/platform_ops.o -EXTRA_CFLAGS += -I$(src)/hal/btc -_OUTSRC_FILES += hal/btc/halbtc8723bwifionly.o \ - hal/btc/halbtc8822bwifionly.o \ - hal/btc/halbtc8821cwifionly.o -ifeq ($(CONFIG_BT_COEXIST), y) -_OUTSRC_FILES += hal/btc/halbtc8192e1ant.o \ - hal/btc/halbtc8192e2ant.o \ - hal/btc/halbtc8723b1ant.o \ - hal/btc/halbtc8723b2ant.o \ - hal/btc/halbtc8812a1ant.o \ - hal/btc/halbtc8812a2ant.o \ - hal/btc/halbtc8821a1ant.o \ - hal/btc/halbtc8821a2ant.o \ - hal/btc/halbtc8703b1ant.o \ - hal/btc/halbtc8723d1ant.o \ - hal/btc/halbtc8723d2ant.o \ - hal/btc/halbtc8822b1ant.o \ - hal/btc/halbtc8822b2ant.o \ - hal/btc/halbtc8821c1ant.o \ - hal/btc/halbtc8821c2ant.o -endif +EXTRA_CFLAGS += -I$(srctree)/$(src)/platform +_PLATFORM_FILES := platform/platform_ops.o +EXTRA_CFLAGS += -I$(srctree)/$(src)/hal/btc ########### HAL_RTL8188E ################################# ifeq ($(CONFIG_RTL8188E), y) @@ -323,15 +299,6 @@ ifeq ($(CONFIG_SDIO_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_SDIO.o endif -#hal/OUTSRC/$(RTL871X)/Hal8188EFWImg_CE.o -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\ - hal/phydm/$(RTL871X)/halphyrf_8188e_ce.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\ - hal/phydm/$(RTL871X)/hal8188erateadaptive.o\ - hal/phydm/$(RTL871X)/phydm_rtl8188e.o - endif ########### HAL_RTL8192E ################################# @@ -387,13 +354,10 @@ ifeq ($(CONFIG_SDIO_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_SDIO.o endif -#hal/OUTSRC/$(RTL871X)/HalHWImg8188E_FW.o -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\ - hal/phydm/$(RTL871X)/halphyrf_8192e_ce.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\ - hal/phydm/$(RTL871X)/phydm_rtl8192e.o +ifeq ($(CONFIG_BT_COEXIST), y) +_BTC_FILES += hal/btc/halbtc8192e1ant.o \ + hal/btc/halbtc8192e2ant.o +endif endif @@ -462,14 +426,6 @@ endif ifeq ($(CONFIG_RTL8812A), y) EXTRA_CFLAGS += -DCONFIG_RTL8812A _HAL_INTFS_FILES += hal/rtl8812a/hal8812a_fw.o - -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\ - hal/phydm/$(RTL871X)/halphyrf_8812a_ce.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\ - hal/phydm/$(RTL871X)/phydm_rtl8812a.o\ - hal/phydm/txbf/haltxbfjaguar.o endif ifeq ($(CONFIG_RTL8821A), y) @@ -496,18 +452,20 @@ endif EXTRA_CFLAGS += -DCONFIG_RTL8821A _HAL_INTFS_FILES += hal/rtl8812a/hal8821a_fw.o -_OUTSRC_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\ - hal/phydm/rtl8821a/halhwimg8821a_bb.o\ - hal/phydm/rtl8821a/halhwimg8821a_rf.o\ - hal/phydm/rtl8812a/halphyrf_8812a_ce.o\ - hal/phydm/rtl8821a/halphyrf_8821a_ce.o\ - hal/phydm/rtl8821a/phydm_regconfig8821a.o\ - hal/phydm/rtl8821a/phydm_rtl8821a.o\ - hal/phydm/rtl8821a/phydm_iqk_8821a_ce.o\ - hal/phydm/txbf/haltxbfjaguar.o endif +ifeq ($(CONFIG_BT_COEXIST), y) +ifeq ($(CONFIG_RTL8812A), y) +_BTC_FILES += hal/btc/halbtc8812a1ant.o \ + hal/btc/halbtc8812a2ant.o +endif +ifeq ($(CONFIG_RTL8821A), y) +_BTC_FILES += hal/btc/halbtc8821a1ant.o \ + hal/btc/halbtc8821a2ant.o +endif +endif + endif ########### HAL_RTL8723B ################################# @@ -560,13 +518,11 @@ ifeq ($(CONFIG_SDIO_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_SDIO.o endif -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\ - hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\ - hal/phydm/$(RTL871X)/halphyrf_8723b_ce.o\ - hal/phydm/$(RTL871X)/phydm_rtl8723b.o +_BTC_FILES += hal/btc/halbtc8723bwifionly.o +ifeq ($(CONFIG_BT_COEXIST), y) +_BTC_FILES += hal/btc/halbtc8723b1ant.o \ + hal/btc/halbtc8723b2ant.o +endif endif @@ -626,15 +582,6 @@ ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_PCIE.o endif -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\ - hal/phydm/$(RTL871X)/phydm_iqk_8814a.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\ - hal/phydm/$(RTL871X)/halphyrf_8814a_ce.o\ - hal/phydm/$(RTL871X)/phydm_rtl8814a.o\ - hal/phydm/txbf/haltxbf8814a.o - endif ########### HAL_RTL8723C ################################# @@ -687,11 +634,10 @@ ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_PCIE.o endif -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\ - hal/phydm/$(RTL871X)/halphyrf_8703b.o +ifeq ($(CONFIG_BT_COEXIST), y) +_BTC_FILES += hal/btc/halbtc8703b1ant.o +endif + endif ########### HAL_RTL8723D ################################# @@ -746,12 +692,11 @@ ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_PCIE.o endif -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\ - hal/phydm/$(RTL871X)/phydm_rtl8723d.o\ - hal/phydm/$(RTL871X)/halphyrf_8723d.o +ifeq ($(CONFIG_BT_COEXIST), y) +_BTC_FILES += hal/btc/halbtc8723d1ant.o \ + hal/btc/halbtc8723d2ant.o +endif + endif ########### HAL_RTL8188F ################################# @@ -802,25 +747,185 @@ ifeq ($(CONFIG_SDIO_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_SDIO.o endif -_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\ - hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\ - hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\ - hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\ - hal/phydm/$(RTL871X)/halphyrf_8188f.o \ - hal/phydm/$(RTL871X)/phydm_rtl8188f.o +endif + +########### HAL_RTL8188GTV ################################# +ifeq ($(CONFIG_RTL8188GTV), y) + +RTL871X = rtl8188gtv +ifeq ($(CONFIG_USB_HCI), y) +MODULE_NAME = 8188gtvu +endif +ifeq ($(CONFIG_SDIO_HCI), y) +MODULE_NAME = 8189gtvs +endif + +EXTRA_CFLAGS += -DCONFIG_RTL8188GTV + +_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \ + hal/$(RTL871X)/Hal8188GTVPwrSeq.o\ + hal/$(RTL871X)/$(RTL871X)_sreset.o + +_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \ + hal/$(RTL871X)/$(RTL871X)_phycfg.o \ + hal/$(RTL871X)/$(RTL871X)_rf6052.o \ + hal/$(RTL871X)/$(RTL871X)_dm.o \ + hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ + hal/$(RTL871X)/$(RTL871X)_cmd.o \ + hal/$(RTL871X)/hal8188gtv_fw.o + +_HAL_INTFS_FILES += \ + hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \ + hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \ + hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \ + hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o + +ifeq ($(CONFIG_PCI_HCI), y) +_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o +else +_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o +endif + +ifeq ($(CONFIG_USB_HCI), y) +_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_USB.o +endif + +ifeq ($(CONFIG_SDIO_HCI), y) +_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188GTV_SDIO.o +endif endif ########### HAL_RTL8822B ################################# ifeq ($(CONFIG_RTL8822B), y) -include $(TopDIR)/rtl8822b.mk +RTL871X := rtl8822b +ifeq ($(CONFIG_USB_HCI), y) +ifeq ($(CONFIG_BT_COEXIST), n) +MODULE_NAME = 8812bu +else +MODULE_NAME = 88x2bu +endif +endif +ifeq ($(CONFIG_PCI_HCI), y) +MODULE_NAME = 88x2be +endif +ifeq ($(CONFIG_SDIO_HCI), y) +MODULE_NAME = 88x2bs endif +endif ########### HAL_RTL8821C ################################# ifeq ($(CONFIG_RTL8821C), y) -include $(TopDIR)/rtl8821c.mk +RTL871X := rtl8821c +ifeq ($(CONFIG_USB_HCI), y) +MODULE_NAME = 8821cu +endif +ifeq ($(CONFIG_PCI_HCI), y) +MODULE_NAME = 8821ce +endif +ifeq ($(CONFIG_SDIO_HCI), y) +MODULE_NAME = 8821cs +endif + +endif + +########### HAL_RTL8710B ################################# +ifeq ($(CONFIG_RTL8710B), y) + +RTL871X = rtl8710b +ifeq ($(CONFIG_USB_HCI), y) +MODULE_NAME = 8710bu +MODULE_SUB_NAME = 8710bu +endif + +EXTRA_CFLAGS += -DCONFIG_RTL8710B + +_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \ + hal/$(RTL871X)/Hal8710BPwrSeq.o\ + hal/$(RTL871X)/$(RTL871X)_sreset.o + +_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \ + hal/$(RTL871X)/$(RTL871X)_phycfg.o \ + hal/$(RTL871X)/$(RTL871X)_rf6052.o \ + hal/$(RTL871X)/$(RTL871X)_dm.o \ + hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ + hal/$(RTL871X)/$(RTL871X)_cmd.o \ + hal/$(RTL871X)/hal8710b_fw.o \ + hal/$(RTL871X)/$(RTL871X)_lps_poff.o + + +_HAL_INTFS_FILES += \ + hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \ + hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \ + hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \ + hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o + +_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o + +ifeq ($(CONFIG_USB_HCI), y) +_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8710B_USB.o +endif + +endif + +########### HAL_RTL8192F ################################# +ifeq ($(CONFIG_RTL8192F), y) + +RTL871X = rtl8192f +ifeq ($(CONFIG_USB_HCI), y) +MODULE_NAME = 8192fu +MODULE_SUB_NAME = 8192fu +endif +ifeq ($(CONFIG_PCI_HCI), y) +MODULE_NAME = 8192fe +MODULE_SUB_NAME = 8192fe +endif +ifeq ($(CONFIG_SDIO_HCI), y) +MODULE_NAME = 8192fs +MODULE_SUB_NAME = 8192fs +endif + +EXTRA_CFLAGS += -DCONFIG_RTL8192F + +_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \ + hal/$(RTL871X)/Hal8192FPwrSeq.o\ + hal/$(RTL871X)/$(RTL871X)_sreset.o + +_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \ + hal/$(RTL871X)/$(RTL871X)_phycfg.o \ + hal/$(RTL871X)/$(RTL871X)_rf6052.o \ + hal/$(RTL871X)/$(RTL871X)_dm.o \ + hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ + hal/$(RTL871X)/$(RTL871X)_cmd.o \ + hal/$(RTL871X)/hal8192f_fw.o \ + hal/$(RTL871X)/$(RTL871X)_lps_poff.o + + +_HAL_INTFS_FILES += \ + hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \ + hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_led.o \ + hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_xmit.o \ + hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_SUB_NAME)_recv.o + +ifeq ($(CONFIG_PCI_HCI), y) +_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops_linux.o +else +_HAL_INTFS_FILES += hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_ops.o +endif + +ifeq ($(CONFIG_SDIO_HCI), y) +_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_SDIO.o +endif + +ifeq ($(CONFIG_USB_HCI), y) +_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_USB.o +endif + +ifeq ($(CONFIG_PCI_HCI), y) +_HAL_INTFS_FILES += hal/efuse/$(RTL871X)/HalEfuseMask8192F_PCIE.o endif +endif ########### AUTO_CFG ################################# ifeq ($(CONFIG_AUTOCFG_CP), y) @@ -915,8 +1020,7 @@ endif ifeq ($(CONFIG_LOAD_PHY_PARA_FROM_FILE), y) EXTRA_CFLAGS += -DCONFIG_LOAD_PHY_PARA_FROM_FILE #EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER -#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/lib/firmware/\" -EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"\" +EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/lib/firmware/\" endif ifeq ($(CONFIG_TXPWR_BY_RATE_EN), n) @@ -935,6 +1039,10 @@ else ifeq ($(CONFIG_TXPWR_LIMIT_EN), auto) EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=2 endif +ifneq ($(CONFIG_RTW_CHPLAN), 0xFF) +EXTRA_CFLAGS += -DCONFIG_RTW_CHPLAN=$(CONFIG_RTW_CHPLAN) +endif + ifeq ($(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY), y) EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_BY_REGULATORY endif @@ -964,13 +1072,10 @@ EXTRA_CFLAGS += -DCONFIG_IEEE80211W endif ifeq ($(CONFIG_WOWLAN), y) -EXTRA_CFLAGS += -DCONFIG_WOWLAN +EXTRA_CFLAGS += -DCONFIG_WOWLAN -DRTW_WAKEUP_EVENT=$(CONFIG_WAKEUP_TYPE) ifeq ($(CONFIG_SDIO_HCI), y) EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER endif -ifeq ($(CONFIG_DEFAULT_PATTERNS_EN), y) -EXTRA_CFLAGS += -DCONFIG_DEFAULT_PATTERNS_EN -endif endif ifeq ($(CONFIG_AP_WOWLAN), y) @@ -989,11 +1094,20 @@ endif ifeq ($(CONFIG_GPIO_WAKEUP), y) EXTRA_CFLAGS += -DCONFIG_GPIO_WAKEUP -ifeq ($(CONFIG_HIGH_ACTIVE), y) -EXTRA_CFLAGS += -DHIGH_ACTIVE=1 +ifeq ($(CONFIG_ONE_PIN_GPIO), y) +EXTRA_CFLAGS += -DCONFIG_RTW_ONE_PIN_GPIO +endif +ifeq ($(CONFIG_HIGH_ACTIVE_DEV2HST), y) +EXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=1 else -EXTRA_CFLAGS += -DHIGH_ACTIVE=0 +EXTRA_CFLAGS += -DHIGH_ACTIVE_DEV2HST=0 +endif endif + +ifeq ($(CONFIG_HIGH_ACTIVE_HST2DEV), y) +EXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=1 +else +EXTRA_CFLAGS += -DHIGH_ACTIVE_HST2DEV=0 endif ifneq ($(CONFIG_WAKEUP_GPIO_IDX), default) @@ -1037,6 +1151,38 @@ ifeq ($(CONFIG_RTW_GRO), y) EXTRA_CFLAGS += -DCONFIG_RTW_GRO endif +ifeq ($(CONFIG_RTW_REPEATER_SON), y) +EXTRA_CFLAGS += -DCONFIG_RTW_REPEATER_SON +endif + +ifeq ($(CONFIG_RTW_IPCAM_APPLICATION), y) +EXTRA_CFLAGS += -DCONFIG_RTW_IPCAM_APPLICATION +ifeq ($(CONFIG_WIFI_MONITOR), n) +EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR +endif +endif + +ifeq ($(CONFIG_RTW_NETIF_SG), y) +EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG +endif + +ifeq ($(CONFIG_TX_CSUM_OFFLOAD), y) +EXTRA_CFLAGS += -DCONFIG_TX_CSUM_OFFLOAD +endif + +ifeq ($(CONFIG_ICMP_VOQ), y) +EXTRA_CFLAGS += -DCONFIG_ICMP_VOQ +endif + +ifeq ($(CONFIG_RTW_WIFI_HAL), y) +#EXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL_DEBUG +EXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL +EXTRA_CFLAGS += -DCONFIG_RTW_CFGVEDNOR_LLSTATS +EXTRA_CFLAGS += -DCONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI +EXTRA_CFLAGS += -DCONFIG_RTW_CFGVEDNOR_RSSIMONITOR +EXTRA_CFLAGS += -DCONFIG_RTW_CFGVENDOR_WIFI_LOGGER +endif + ifeq ($(CONFIG_MP_VHT_HW_TX_MODE), y) EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE ifeq ($(CONFIG_PLATFORM_I386_PC), y) @@ -1084,17 +1230,26 @@ EXTRA_CFLAGS += -DCONFIG_RADIO_WORK EXTRA_CFLAGS += -DRTW_VENDOR_EXT_SUPPORT EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC ARCH ?= arm -# for ubuntu environment -#CROSS_COMPILE ?= -#KVER := $(shell uname -r) -#KSRC := /lib/modules/$(KVER)/build -#MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ -#INSTALL_PREFIX := + CROSS_COMPILE := /mnt/newdisk/android_sdk/nvidia_tk1/android_L/prebuilts/gcc/linux-x86/arm/arm-eabi-4.8/bin/arm-eabi- KSRC :=/mnt/newdisk/android_sdk/nvidia_tk1/android_L/out/target/product/shieldtablet/obj/KERNEL/ MODULE_NAME = wlan endif +ifeq ($(CONFIG_PLATFORM_NV_TK1_UBUNTU), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1 +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT + +ARCH ?= arm + +CROSS_COMPILE ?= +KVER := $(shell uname -r) +KSRC := /lib/modules/$(KVER)/build +MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ +INSTALL_PREFIX := +endif + ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM702X), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ACTIONS_ATM702X #ARCH := arm @@ -1174,8 +1329,12 @@ endif ifeq ($(CONFIG_PLATFORM_MSTAR), y) EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT -EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_USE_USB_BUFFER_ALLOC_TX -DCONFIG_FIX_NR_BULKIN_BUFFER +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR_HIGH +ifeq ($(CONFIG_USB_HCI), y) +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX -DCONFIG_FIX_NR_BULKIN_BUFFER +endif ARCH:=arm CROSS_COMPILE:= /usr/src/bin/arm-none-linux-gnueabi- KVER:= 3.1.10 @@ -1476,17 +1635,6 @@ KVER:= 2.6.31.6 KSRC:= ../code/linux-2.6.31.6-2020/ endif -#Add setting for MN10300 -ifeq ($(CONFIG_PLATFORM_MN10300), y) -EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MN10300 -ARCH := mn10300 -CROSS_COMPILE := mn10300-linux- -KVER := 2.6.32.2 -KSRC := /home/winuser/work/Plat_sLD2T_V3010/usr/src/linux-2.6.32.2 -INSTALL_PREFIX := -endif - - ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUNxI @@ -1640,10 +1788,9 @@ endif ifeq ($(CONFIG_PLATFORM_ARM_RTD299X), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -EXTRA_CFLAGS += -DUSB_XMITBUF_ALIGN_SZ=1024 -DUSB_PACKET_OFFSET_SZ=0 EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE -ifeq ($(CONFIG_ANDROID), y) EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +ifeq ($(CONFIG_ANDROID), y) # Enable this for Android 5.0 EXTRA_CFLAGS += -DCONFIG_RADIO_WORK endif @@ -1651,6 +1798,32 @@ endif INSTALL_PREFIX := endif +ifeq ($(CONFIG_PLATFORM_ARM_RTD299X_LG), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1 +EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3 +#EXTRA_CFLAGS += -DCONFIG_FIX_HWPORT +EXTRA_CFLAGS += -DLGE_PRIVATE +EXTRA_CFLAGS += -DPURE_SUPPLICANT +EXTRA_CFLAGS += -DCONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP -DCONFIG_RTW_IOCTL_SET_COUNTRY +EXTRA_CFLAGS += -DDBG_RX_DFRAME_RAW_DATA +EXTRA_CFLAGS += -DRTW_REDUCE_SCAN_SWITCH_CH_TIME +ARCH ?= arm +KVER ?= + +ifneq ($(PLATFORM), WEBOS) +$(info PLATFORM is empty) +CROSS_COMPILE ?= /mnt/newdisk/LGE/arm-lg115x-linux-gnueabi-4.8-2016.03-x86_64/bin/arm-lg115x-linux-gnueabi- +KSRC ?= /mnt/newdisk/LGE/linux-rockhopper_k3lp_drd4tv_423 +endif + +CROSS_COMPILE ?= +KSRC ?= $(LINUX_SRC) +INSTALL_PREFIX ?= +endif + ifeq ($(CONFIG_PLATFORM_HISILICON), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_HISILICON ifeq ($(SUPPORT_CONCURRENT),y) @@ -1667,6 +1840,41 @@ ifeq ($(KSRC),) endif endif +ifeq ($(CONFIG_PLATFORM_HISILICON_HI3798), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON +EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798 +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +# default setting for Android +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 +EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT +# default setting for Android 5.x and later +#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK + +# If system could power on and recognize Wi-Fi SDIO automatically, +# platfrom operations are not necessary. +#ifeq ($(CONFIG_SDIO_HCI), y) +#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +#_PLATFORM_FILES += platform/platform_hisilicon_hi3798_sdio.o +#EXTRA_CFLAGS += -DCONFIG_HISI_SDIO_ID=1 +#endif + +ARCH ?= arm +CROSS_COMPILE ?= /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/tools/linux/toolchains/arm-histbv310-linux/bin/arm-histbv310-linux- +ifndef KSRC +KSRC := /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/source/kernel/linux-3.18.y +KSRC += O=/HiSTBAndroidV600R003C00SPC021_git_0512/out/target/product/Hi3798MV200/obj/KERNEL_OBJ +endif + +ifeq ($(CONFIG_RTL8822B), y) +ifeq ($(CONFIG_SDIO_HCI), y) +CONFIG_RTL8822BS ?= m +USER_MODULE_NAME := rtl8822bs +endif +endif + +endif + # Platform setting ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_6820), y) ifeq ($(CONFIG_ANDROID_2X), y) @@ -1720,7 +1928,6 @@ EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT # default setting for Android 4.1, 4.2 EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE -EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3 EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT #EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION @@ -1746,6 +1953,26 @@ MODULE_NAME := 8192eu endif +ifeq ($(CONFIG_PLATFORM_RTK119X_AM), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK119X_AM +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE -DCONFIG_FULL_CH_IN_P2P_HANDSHAKE +EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3 +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT + +ifeq ($(CONFIG_USB_HCI), y) +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX +endif + +ARCH := arm + +#CROSS_COMPILE := arm-linux-gnueabihf- +KVER := 3.10.24 +#KSRC := +CROSS_COMPILE := +endif + ifeq ($(CONFIG_PLATFORM_RTK129X), y) EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN EXTRA_CFLAGS += -DRTK_129X_PLATFORM @@ -1782,6 +2009,22 @@ CROSS_COMPILE := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/phoenix/toolchain KSRC := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/linux-kernel endif +ifeq ($(CONFIG_PLATFORM_RTK390X), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_PLATFORM_RTK390X +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG +ifeq ($(CONFIG_USB_HCI), y) +EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX +endif + +ARCH:=rlx + +CROSS_COMPILE:=mips-linux- +KSRC:= /home/realtek/share/Develop/IPCAM_SDK/RealSil/rts3901_sdk_v1.2_vanilla/linux-3.10 + +endif + ifeq ($(CONFIG_PLATFORM_NOVATEK_NT72668), y) EXTRA_CFLAGS += -DCONFIG_PLATFORM_NOVATEK_NT72668 EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN @@ -1815,6 +2058,77 @@ CROSS_COMPILE:= $(DIR_LINUX)/../toolchain/rsdk-1.5.5-5281-EB-2.6.30-0.9.30.3-110 KSRC := $(DIR_LINUX) endif +ifeq ($(CONFIG_PLATFORM_AML_S905), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_AML_S905 +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -fno-pic +# default setting for Android +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 +EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT +# default setting for Android 5.x and later +EXTRA_CFLAGS += -DCONFIG_RADIO_WORK + +ifeq ($(CONFIG_SDIO_HCI), y) +EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +_PLATFORM_FILES += platform/platform_aml_s905_sdio.o +endif + +ARCH ?= arm64 +CROSS_COMPILE ?= /4.4_S905L_8822bs_compile/gcc-linaro-aarch64-linux-gnu-4.9-2014.09_linux/bin/aarch64-linux-gnu- +ifndef KSRC +KSRC := /4.4_S905L_8822bs_compile/common +# To locate output files in a separate directory. +KSRC += O=/4.4_S905L_8822bs_compile/KERNEL_OBJ +endif + +ifeq ($(CONFIG_RTL8822B), y) +ifeq ($(CONFIG_SDIO_HCI), y) +CONFIG_RTL8822BS ?= m +USER_MODULE_NAME := 8822bs +endif +endif + +endif + +ifeq ($(CONFIG_PLATFORM_ZTE_ZX296716), y) +EXTRA_CFLAGS += -Wno-error=date-time +EXTRA_CFLAGS += -DCONFIG_PLATFORM_ZTE_ZX296716 +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +# default setting for Android +EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 +EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT +# default setting for Android 5.x and later +#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK + +ifeq ($(CONFIG_SDIO_HCI), y) +# mark this temporarily +#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS +#_PLATFORM_FILES += platform/platform_zte_zx296716_sdio.o +endif + +ARCH ?= arm64 +CROSS_COMPILE ?= +KSRC ?= + +ifeq ($(CONFIG_RTL8822B), y) +ifeq ($(CONFIG_SDIO_HCI), y) +CONFIG_RTL8822BS ?= m +USER_MODULE_NAME := 8822bs +endif +endif + +endif + +########### CUSTOMER ################################ +ifeq ($(CONFIG_CUSTOMER_HUAWEI_GENERAL), y) +CONFIG_CUSTOMER_HUAWEI = y +endif + +ifeq ($(CONFIG_CUSTOMER_HUAWEI), y) +EXTRA_CFLAGS += -DCONFIG_HUAWEI_PROC +endif + ifeq ($(CONFIG_MULTIDRV), y) ifeq ($(CONFIG_SDIO_HCI), y) @@ -1839,6 +2153,19 @@ endif ifneq ($(KERNELRELEASE),) +########### this part for *.mk ############################ +include $(srctree)/$(src)/hal/phydm/phydm.mk + +########### HAL_RTL8822B ################################# +ifeq ($(CONFIG_RTL8822B), y) +include $(srctree)/$(src)/rtl8822b.mk +endif + +########### HAL_RTL8821C ################################# +ifeq ($(CONFIG_RTL8821C), y) +include $(srctree)/$(src)/rtl8821c.mk +endif + rtk_core := core/rtw_cmd.o \ core/rtw_security.o \ core/rtw_debug.o \ @@ -1853,11 +2180,16 @@ rtk_core := core/rtw_cmd.o \ core/rtw_vht.o \ core/rtw_pwrctrl.o \ core/rtw_rf.o \ + core/rtw_chplan.o \ core/rtw_recv.o \ core/rtw_sta_mgt.o \ core/rtw_ap.o \ + core/mesh/rtw_mesh.o \ + core/mesh/rtw_mesh_pathtbl.o \ + core/mesh/rtw_mesh_hwmp.o \ core/rtw_xmit.o \ core/rtw_p2p.o \ + core/rtw_rson.o \ core/rtw_tdls.o \ core/rtw_br_ext.o \ core/rtw_iol.o \ @@ -1866,6 +2198,8 @@ rtk_core := core/rtw_cmd.o \ core/rtw_btcoex.o \ core/rtw_beamforming.o \ core/rtw_odm.o \ + core/rtw_rm.o \ + core/rtw_rm_fsm.o \ core/efuse/rtw_efuse.o ifeq ($(CONFIG_SDIO_HCI), y) @@ -1881,7 +2215,8 @@ $(MODULE_NAME)-$(CONFIG_WAPI_SUPPORT) += core/rtw_wapi.o \ $(MODULE_NAME)-y += $(_OS_INTFS_FILES) $(MODULE_NAME)-y += $(_HAL_INTFS_FILES) -$(MODULE_NAME)-y += $(_OUTSRC_FILES) +$(MODULE_NAME)-y += $(_PHYDM_FILES) +$(MODULE_NAME)-y += $(_BTC_FILES) $(MODULE_NAME)-y += $(_PLATFORM_FILES) $(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o @@ -1959,7 +2294,7 @@ clean: cd hal ; rm -fr */*/*.mod.c */*/*.mod */*/*.o */*/.*.cmd */*/*.ko cd hal ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko - cd core/efuse ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko + cd core ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko diff --git a/core/efuse/rtw_efuse.c b/core/efuse/rtw_efuse.c index 25f3a2c..dc9ec64 100644 --- a/core/efuse/rtw_efuse.c +++ b/core/efuse/rtw_efuse.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_EFUSE_C_ #include @@ -67,7 +62,7 @@ BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset) if (pAdapter->registrypriv.boffefusemask) return FALSE; -#if DEV_BUS_TYPE == RT_USB_INTERFACE +#ifdef CONFIG_USB_HCI #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) return (IS_MASKED(8188E, _MUSB, Offset)) ? TRUE : FALSE; @@ -104,6 +99,10 @@ BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset) if (IS_HARDWARE_TYPE_8188F(pAdapter)) return (IS_MASKED(8188F, _MUSB, Offset)) ? TRUE : FALSE; #endif +#if defined(CONFIG_RTL8188GTV) + if (IS_HARDWARE_TYPE_8188GTV(pAdapter)) + return (IS_MASKED(8188GTV, _MUSB, Offset)) ? TRUE : FALSE; +#endif #if defined(CONFIG_RTL8822B) if (IS_HARDWARE_TYPE_8822B(pAdapter)) return (IS_MASKED(8822B, _MUSB, Offset)) ? TRUE : FALSE; @@ -112,13 +111,22 @@ BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset) if (IS_HARDWARE_TYPE_8723D(pAdapter)) return (IS_MASKED(8723D, _MUSB, Offset)) ? TRUE : FALSE; #endif - +#if defined(CONFIG_RTL8710B) + if (IS_HARDWARE_TYPE_8710B(pAdapter)) + return (IS_MASKED(8710B, _MUSB, Offset)) ? TRUE : FALSE; +#endif #if defined(CONFIG_RTL8821C) if (IS_HARDWARE_TYPE_8821CU(pAdapter)) return (IS_MASKED(8821C, _MUSB, Offset)) ? TRUE : FALSE; #endif -#elif DEV_BUS_TYPE == RT_PCI_INTERFACE +#if defined(CONFIG_RTL8192F) + if (IS_HARDWARE_TYPE_8192FU(pAdapter)) + return (IS_MASKED(8192F, _MUSB, Offset)) ? TRUE : FALSE; +#endif +#endif /*CONFIG_USB_HCI*/ + +#ifdef CONFIG_PCI_HCI #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) return (IS_MASKED(8188E, _MPCIE, Offset)) ? TRUE : FALSE; @@ -152,7 +160,13 @@ BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset) return (IS_MASKED(8821C, _MPCIE, Offset)) ? TRUE : FALSE; #endif -#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE +#if defined(CONFIG_RTL8192F) + if (IS_HARDWARE_TYPE_8192FE(pAdapter)) + return (IS_MASKED(8192F, _MPCIE, Offset)) ? TRUE : FALSE; +#endif +#endif /*CONFIG_PCI_HCI*/ + +#ifdef CONFIG_SDIO_HCI #ifdef CONFIG_RTL8188E_SDIO if (IS_HARDWARE_TYPE_8188E(pAdapter)) return (IS_MASKED(8188E, _MSDIO, Offset)) ? TRUE : FALSE; @@ -161,10 +175,14 @@ BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset) if (IS_HARDWARE_TYPE_8723BS(pAdapter)) return (IS_MASKED(8723B, _MSDIO, Offset)) ? TRUE : FALSE; #endif -#ifdef CONFIG_RTL8188F_SDIO +#ifdef CONFIG_RTL8188F if (IS_HARDWARE_TYPE_8188F(pAdapter)) return (IS_MASKED(8188F, _MSDIO, Offset)) ? TRUE : FALSE; #endif +#ifdef CONFIG_RTL8188GTV + if (IS_HARDWARE_TYPE_8188GTV(pAdapter)) + return (IS_MASKED(8188GTV, _MSDIO, Offset)) ? TRUE : FALSE; +#endif #ifdef CONFIG_RTL8192E if (IS_HARDWARE_TYPE_8192ES(pAdapter)) return (IS_MASKED(8192E, _MSDIO, Offset)) ? TRUE : FALSE; @@ -181,7 +199,11 @@ BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset) if (IS_HARDWARE_TYPE_8822B(pAdapter)) return (IS_MASKED(8822B, _MSDIO, Offset)) ? TRUE : FALSE; #endif +#if defined(CONFIG_RTL8192F) + if (IS_HARDWARE_TYPE_8192FS(pAdapter)) + return (IS_MASKED(8192F, _MSDIO, Offset)) ? TRUE : FALSE; #endif +#endif /*CONFIG_SDIO_HCI*/ return FALSE; } @@ -190,7 +212,7 @@ void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); -#if DEV_BUS_TYPE == RT_USB_INTERFACE +#ifdef CONFIG_USB_HCI #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) GET_MASK_ARRAY(8188E, _MUSB, pArray); @@ -219,6 +241,10 @@ void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray) if (IS_HARDWARE_TYPE_8188F(pAdapter)) GET_MASK_ARRAY(8188F, _MUSB, pArray); #endif +#if defined(CONFIG_RTL8188GTV) + if (IS_HARDWARE_TYPE_8188GTV(pAdapter)) + GET_MASK_ARRAY(8188GTV, _MUSB, pArray); +#endif #if defined(CONFIG_RTL8814A) if (IS_HARDWARE_TYPE_8814A(pAdapter)) GET_MASK_ARRAY(8814A, _MUSB, pArray); @@ -231,9 +257,13 @@ void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray) if (IS_HARDWARE_TYPE_8821CU(pAdapter)) GET_MASK_ARRAY(8821C, _MUSB, pArray); #endif +#if defined(CONFIG_RTL8192F) + if (IS_HARDWARE_TYPE_8192FU(pAdapter)) + GET_MASK_ARRAY(8192F, _MUSB, pArray); +#endif +#endif /*CONFIG_USB_HCI*/ - -#elif DEV_BUS_TYPE == RT_PCI_INTERFACE +#ifdef CONFIG_PCI_HCI #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) GET_MASK_ARRAY(8188E, _MPCIE, pArray); @@ -266,9 +296,13 @@ void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray) if (IS_HARDWARE_TYPE_8821CE(pAdapter)) GET_MASK_ARRAY(8821C, _MPCIE, pArray); #endif +#if defined(CONFIG_RTL8192F) + if (IS_HARDWARE_TYPE_8192FE(pAdapter)) + GET_MASK_ARRAY(8192F, _MPCIE, pArray); +#endif +#endif /*CONFIG_PCI_HCI*/ - -#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE +#ifdef CONFIG_SDIO_HCI #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) GET_MASK_ARRAY(8188E, _MSDIO, pArray); @@ -281,6 +315,10 @@ void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray) if (IS_HARDWARE_TYPE_8188F(pAdapter)) GET_MASK_ARRAY(8188F, _MSDIO, pArray); #endif +#if defined(CONFIG_RTL8188GTV) + if (IS_HARDWARE_TYPE_8188GTV(pAdapter)) + GET_MASK_ARRAY(8188GTV, _MSDIO, pArray); +#endif #if defined(CONFIG_RTL8192E) if (IS_HARDWARE_TYPE_8192ES(pAdapter)) GET_MASK_ARRAY(8192E, _MSDIO, pArray); @@ -297,14 +335,18 @@ void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray) if (IS_HARDWARE_TYPE_8822B(pAdapter)) GET_MASK_ARRAY(8822B , _MSDIO, pArray); #endif -#endif /*#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE*/ +#if defined(CONFIG_RTL8192F) + if (IS_HARDWARE_TYPE_8192FS(pAdapter)) + GET_MASK_ARRAY(8192F, _MSDIO, pArray); +#endif +#endif /*CONFIG_SDIO_HCI*/ } u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); -#if DEV_BUS_TYPE == RT_USB_INTERFACE +#ifdef CONFIG_USB_HCI #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) return GET_MASK_ARRAY_LEN(8188E, _MUSB); @@ -333,6 +375,10 @@ u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter) if (IS_HARDWARE_TYPE_8188F(pAdapter)) return GET_MASK_ARRAY_LEN(8188F, _MUSB); #endif +#if defined(CONFIG_RTL8188GTV) + if (IS_HARDWARE_TYPE_8188GTV(pAdapter)) + return GET_MASK_ARRAY_LEN(8188GTV, _MUSB); +#endif #if defined(CONFIG_RTL8814A) if (IS_HARDWARE_TYPE_8814A(pAdapter)) return GET_MASK_ARRAY_LEN(8814A, _MUSB); @@ -345,9 +391,13 @@ u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter) if (IS_HARDWARE_TYPE_8821CU(pAdapter)) return GET_MASK_ARRAY_LEN(8821C, _MUSB); #endif +#if defined(CONFIG_RTL8192F) + if (IS_HARDWARE_TYPE_8192FU(pAdapter)) + return GET_MASK_ARRAY_LEN(8192F, _MUSB); +#endif +#endif /*CONFIG_USB_HCI*/ - -#elif DEV_BUS_TYPE == RT_PCI_INTERFACE +#ifdef CONFIG_PCI_HCI #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) return GET_MASK_ARRAY_LEN(8188E, _MPCIE); @@ -380,9 +430,13 @@ u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter) if (IS_HARDWARE_TYPE_8821CE(pAdapter)) return GET_MASK_ARRAY_LEN(8821C, _MPCIE); #endif +#if defined(CONFIG_RTL8192F) + if (IS_HARDWARE_TYPE_8192FE(pAdapter)) + return GET_MASK_ARRAY_LEN(8192F, _MPCIE); +#endif +#endif /*CONFIG_PCI_HCI*/ - -#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE +#ifdef CONFIG_SDIO_HCI #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(pAdapter)) return GET_MASK_ARRAY_LEN(8188E, _MSDIO); @@ -395,6 +449,10 @@ u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter) if (IS_HARDWARE_TYPE_8188F(pAdapter)) return GET_MASK_ARRAY_LEN(8188F, _MSDIO); #endif +#if defined(CONFIG_RTL8188GTV) + if (IS_HARDWARE_TYPE_8188GTV(pAdapter)) + return GET_MASK_ARRAY_LEN(8188GTV, _MSDIO); +#endif #if defined(CONFIG_RTL8192E) if (IS_HARDWARE_TYPE_8192ES(pAdapter)) return GET_MASK_ARRAY_LEN(8192E, _MSDIO); @@ -411,37 +469,370 @@ u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter) if (IS_HARDWARE_TYPE_8822B(pAdapter)) return GET_MASK_ARRAY_LEN(8822B, _MSDIO); #endif +#if defined(CONFIG_RTL8192F) + if (IS_HARDWARE_TYPE_8192FS(pAdapter)) + return GET_MASK_ARRAY_LEN(8192F, _MSDIO); #endif +#endif/*CONFIG_SDIO_HCI*/ return 0; } +static void rtw_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) +{ + u16 i = 0; + + if (padapter->registrypriv.boffefusemask == 0) { + + for (i = 0; i < cnts; i++) { + if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { + if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask.*/ + data[i] = 0xff; + } else { + /*RTW_INFO(" %s , data[%d] = %x\n", __func__, i, data[i]);*/ + if (efuse_IsMasked(padapter, addr + i)) { + data[i] = 0xff; + /*RTW_INFO(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/ + } + } + } + + } +} + u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) { u8 ret = _SUCCESS; - u16 mapLen = 0, i = 0; + u16 mapLen = 0; EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); ret = rtw_efuse_map_read(padapter, addr, cnts , data); - if (padapter->registrypriv.boffefusemask == 0) { + rtw_mask_map_read(padapter, addr, cnts , data); - for (i = 0; i < cnts; i++) { - if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { - if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask.*/ - data[i] = 0xff; + return ret; + +} + +/* *********************************************************** + * Efuse related code + * *********************************************************** */ +static u8 hal_EfuseSwitchToBank( + PADAPTER padapter, + u8 bank, + u8 bPseudoTest) +{ + u8 bRet = _FALSE; + u32 value32 = 0; +#ifdef HAL_EFUSE_MEMORY + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; +#endif + + + RTW_INFO("%s: Efuse switch bank to %d\n", __FUNCTION__, bank); + if (bPseudoTest) { +#ifdef HAL_EFUSE_MEMORY + pEfuseHal->fakeEfuseBank = bank; +#else + fakeEfuseBank = bank; +#endif + bRet = _TRUE; + } else { + value32 = rtw_read32(padapter, 0x34); + bRet = _TRUE; + switch (bank) { + case 0: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); + break; + case 1: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0); + break; + case 2: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1); + break; + case 3: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2); + break; + default: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); + bRet = _FALSE; + break; + } + rtw_write32(padapter, 0x34, value32); + } + + return bRet; +} + +void rtw_efuse_analyze(PADAPTER padapter, u8 Type, u8 Fake) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &(pHalData->EfuseHal); + u16 eFuse_Addr = 0; + u8 offset, wden; + u16 i, j; + u8 u1temp = 0; + u8 efuseHeader = 0, efuseExtHdr = 0, efuseData[EFUSE_MAX_WORD_UNIT*2] = {0}, dataCnt = 0; + u16 efuseHeader2Byte = 0; + u8 *eFuseWord = NULL;// [EFUSE_MAX_SECTION_NUM][EFUSE_MAX_WORD_UNIT]; + u8 offset_2_0 = 0; + u8 pgSectionCnt = 0; + u8 wd_cnt = 0; + u8 max_section = 64; + u16 mapLen = 0, maprawlen = 0; + boolean bExtHeader = _FALSE; + u8 efuseType = EFUSE_WIFI; + boolean bPseudoTest = _FALSE; + u8 bank = 0, startBank = 0, endBank = 1-1; + boolean bCheckNextBank = FALSE; + u8 protectBytesBank = 0; + u16 efuse_max = 0; + u8 ParseEfuseExtHdr, ParseEfuseHeader, ParseOffset, ParseWDEN, ParseOffset2_0; + + eFuseWord = rtw_zmalloc(EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2)); + + RTW_INFO("\n"); + if (Type == 0) { + if (Fake == 0) { + RTW_INFO("\n\tEFUSE_Analyze Wifi Content\n"); + efuseType = EFUSE_WIFI; + bPseudoTest = FALSE; + startBank = 0; + endBank = 0; + } else { + RTW_INFO("\n\tEFUSE_Analyze Wifi Pseudo Content\n"); + efuseType = EFUSE_WIFI; + bPseudoTest = TRUE; + startBank = 0; + endBank = 0; + } + } else { + if (Fake == 0) { + RTW_INFO("\n\tEFUSE_Analyze BT Content\n"); + efuseType = EFUSE_BT; + bPseudoTest = FALSE; + startBank = 1; + endBank = EFUSE_MAX_BANK - 1; + } else { + RTW_INFO("\n\tEFUSE_Analyze BT Pseudo Content\n"); + efuseType = EFUSE_BT; + bPseudoTest = TRUE; + startBank = 1; + endBank = EFUSE_MAX_BANK - 1; + if (IS_HARDWARE_TYPE_8821(padapter)) + endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/ + } + } + + RTW_INFO("\n\r 1Byte header, [7:4]=offset, [3:0]=word enable\n"); + RTW_INFO("\n\r 2Byte header, header[7:5]=offset[2:0], header[4:0]=0x0F\n"); + RTW_INFO("\n\r 2Byte header, extHeader[7:4]=offset[6:3], extHeader[3:0]=word enable\n"); + + EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest); + EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAX_SECTION, (PVOID)&max_section, bPseudoTest); + EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_PROTECT_BYTES_BANK, (PVOID)&protectBytesBank, bPseudoTest); + EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, (PVOID)&efuse_max, bPseudoTest); + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&maprawlen, _FALSE); + + _rtw_memset(eFuseWord, 0xff, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2)); + _rtw_memset(pEfuseHal->fakeEfuseInitMap, 0xff, EFUSE_MAX_MAP_LEN); + + if (IS_HARDWARE_TYPE_8821(padapter)) + endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/ + + for (bank = startBank; bank <= endBank; bank++) { + if (!hal_EfuseSwitchToBank(padapter, bank, bPseudoTest)) { + RTW_INFO("EFUSE_SwitchToBank() Fail!!\n"); + return; + } + + eFuse_Addr = bank * EFUSE_MAX_BANK_SIZE; + + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); + + if (efuseHeader == 0xFF && bank == startBank && Fake != TRUE) { + RTW_INFO("Non-PGed Efuse\n"); + return; + } + RTW_INFO("EFUSE_REAL_CONTENT_LEN = %d\n", maprawlen); + + while ((efuseHeader != 0xFF) && ((efuseType == EFUSE_WIFI && (eFuse_Addr < maprawlen)) || (efuseType == EFUSE_BT && (eFuse_Addr < (endBank + 1) * EFUSE_MAX_BANK_SIZE)))) { + + RTW_INFO("Analyzing: Offset: 0x%X\n", eFuse_Addr); + + /* Check PG header for section num.*/ + if (EXT_HEADER(efuseHeader)) { + bExtHeader = TRUE; + offset_2_0 = GET_HDR_OFFSET_2_0(efuseHeader); + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); + + if (efuseExtHdr != 0xff) { + if (ALL_WORDS_DISABLED(efuseExtHdr)) { + /* Read next pg header*/ + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); + continue; + } else { + offset = ((efuseExtHdr & 0xF0) >> 1) | offset_2_0; + wden = (efuseExtHdr & 0x0F); + efuseHeader2Byte = (efuseExtHdr<<8)|efuseHeader; + RTW_INFO("Find efuseHeader2Byte = 0x%04X, offset=%d, wden=0x%x\n", + efuseHeader2Byte, offset, wden); + } + } else { + RTW_INFO("Error, efuse[%d]=0xff, efuseExtHdr=0xff\n", eFuse_Addr-1); + break; + } + } else { + offset = ((efuseHeader >> 4) & 0x0f); + wden = (efuseHeader & 0x0f); + } + + _rtw_memset(efuseData, '\0', EFUSE_MAX_WORD_UNIT * 2); + dataCnt = 0; + + if (offset < max_section) { + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + /* Check word enable condition in the section */ + if (!(wden & (0x01<> 8; + ParseEfuseHeader = (efuseHeader2Byte & 0xff); + ParseOffset2_0 = GET_HDR_OFFSET_2_0(ParseEfuseHeader); + ParseOffset = ((ParseEfuseExtHdr & 0xF0) >> 1) | ParseOffset2_0; + ParseWDEN = (ParseEfuseExtHdr & 0x0F); + RTW_INFO("Header=0x%x, ExtHeader=0x%x, ", ParseEfuseHeader, ParseEfuseExtHdr); } else { - /*RTW_INFO(" %s , data[%d] = %x\n", __func__, i, data[i]);*/ - if (efuse_IsMasked(padapter, addr + i)) { - data[i] = 0xff; - /*RTW_INFO(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/ + ParseEfuseHeader = efuseHeader; + ParseOffset = ((ParseEfuseHeader >> 4) & 0x0f); + ParseWDEN = (ParseEfuseHeader & 0x0f); + RTW_INFO("Header=0x%x, ", ParseEfuseHeader); + } + RTW_INFO("offset=0x%x(%d), word enable=0x%x\n", ParseOffset, ParseOffset, ParseWDEN); + + wd_cnt = 0; + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + if (!(wden & (0x01 << i))) { + RTW_INFO("Map[ %02X ] = %02X %02X\n", ((offset * EFUSE_MAX_WORD_UNIT * 2) + (i * 2)), efuseData[wd_cnt * 2 + 0], efuseData[wd_cnt * 2 + 1]); + wd_cnt++; } } + + pgSectionCnt++; + bExtHeader = FALSE; + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); + if (efuseHeader == 0xFF) { + if ((eFuse_Addr + protectBytesBank) >= efuse_max) + bCheckNextBank = TRUE; + else + bCheckNextBank = FALSE; + } } + if (!bCheckNextBank) { + RTW_INFO("Not need to check next bank, eFuse_Addr=%d, protectBytesBank=%d, efuse_max=%d\n", + eFuse_Addr, protectBytesBank, efuse_max); + break; + } + } + /* switch bank back to 0 for BT/wifi later use*/ + hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); + /* 3. Collect 16 sections and 4 word unit into Efuse map.*/ + for (i = 0; i < max_section; i++) { + for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) { + pEfuseHal->fakeEfuseInitMap[(i*8)+(j*2)] = (eFuseWord[(i*8)+(j*2)]); + pEfuseHal->fakeEfuseInitMap[(i*8)+((j*2)+1)] = (eFuseWord[(i*8)+((j*2)+1)]); + } } - return ret; + RTW_INFO("\n\tEFUSE Analyze Map\n"); + i = 0; + j = 0; + + for (i = 0; i < mapLen; i++) { + if (i % 16 == 0) + RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i); + _RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s" + , pEfuseHal->fakeEfuseInitMap[i] + , ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ") + ); + } + _RTW_PRINT_SEL(RTW_DBGDUMP, "\n"); + if (eFuseWord) + rtw_mfree((u8 *)eFuseWord, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2)); +} + +VOID efuse_PreUpdateAction( + PADAPTER pAdapter, + pu4Byte BackupRegs) +{ + if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) { + /* <20131115, Kordan> Turn off Rx to prevent from being busy when writing the EFUSE. (Asked by Chunchu.)*/ + BackupRegs[0] = phy_query_mac_reg(pAdapter, REG_RCR, bMaskDWord); + BackupRegs[1] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord); + BackupRegs[2] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord); +#ifdef CONFIG_RTL8812A + BackupRegs[3] = phy_query_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord); +#endif + PlatformEFIOWrite4Byte(pAdapter, REG_RCR, 0x1); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+1, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+2, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+3, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+4, 0); + PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+5, 0); +#ifdef CONFIG_RTL8812A + /* <20140410, Kordan> 0x11 = 0x4E, lower down LX_SPS0 voltage. (Asked by Chunchu)*/ + phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskByte1, 0x4E); +#endif + RTW_INFO(" %s , done\n", __func__); + + } +} + + +VOID efuse_PostUpdateAction( + PADAPTER pAdapter, + pu4Byte BackupRegs) +{ + if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) { + /* <20131115, Kordan> Turn on Rx and restore the registers. (Asked by Chunchu.)*/ + phy_set_mac_reg(pAdapter, REG_RCR, bMaskDWord, BackupRegs[0]); + phy_set_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord, BackupRegs[1]); + phy_set_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord, BackupRegs[2]); +#ifdef CONFIG_RTL8812A + phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord, BackupRegs[3]); +#endif + RTW_INFO(" %s , done\n", __func__); + } } @@ -666,40 +1057,52 @@ u8 rtw_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) u8 *efuse = NULL; u32 size, i; int err; + u32 backupRegs[4] = {0}; + u8 status = _SUCCESS; + efuse_PreUpdateAction(adapter, backupRegs); d = adapter_to_dvobj(adapter); err = rtw_halmac_get_logical_efuse_size(d, &size); - if (err) - return _FAIL; - + if (err) { + status = _FAIL; + goto exit; + } /* size error handle */ if ((addr + cnts) > size) { if (addr < size) cnts = size - addr; - else - return _FAIL; + else { + status = _FAIL; + goto exit; + } } if (cnts > 16) efuse = rtw_zmalloc(size); if (efuse) { - err = rtw_halmac_read_logical_efuse_map(d, efuse, size); + err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0); if (err) { rtw_mfree(efuse, size); - return _FAIL; + status = _FAIL; + goto exit; } _rtw_memcpy(data, efuse + addr, cnts); rtw_mfree(efuse, size); } else { err = rtw_halmac_read_logical_efuse(d, addr, cnts, data); - if (err) - return _FAIL; + if (err) { + status = _FAIL; + goto exit; + } } + status = _SUCCESS; +exit: + efuse_PostUpdateAction(adapter, backupRegs); - return _SUCCESS; + return status; } u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) @@ -710,23 +1113,34 @@ u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) int err; u8 mask_buf[64] = ""; u16 mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(adapter); + u32 backupRegs[4] = {0}; + u8 status = _SUCCESS;; + + efuse_PreUpdateAction(adapter, backupRegs); d = adapter_to_dvobj(adapter); err = rtw_halmac_get_logical_efuse_size(d, &size); - if (err) - return _FAIL; + if (err) { + status = _FAIL; + goto exit; + } - if ((addr + cnts) > size) - return _FAIL; + if ((addr + cnts) > size) { + status = _FAIL; + goto exit; + } efuse = rtw_zmalloc(size); - if (!efuse) - return _FAIL; + if (!efuse) { + status = _FAIL; + goto exit; + } - err = rtw_halmac_read_logical_efuse_map(d, efuse, size); + err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0); if (err) { rtw_mfree(efuse, size); - return _FAIL; + status = _FAIL; + goto exit; } _rtw_memcpy(efuse + addr, data, cnts); @@ -751,12 +1165,16 @@ u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) if (err) { rtw_mfree(efuse, size); - return _FAIL; + status = _FAIL; + goto exit; } rtw_mfree(efuse, size); + status = _SUCCESS; +exit : + efuse_PostUpdateAction(adapter, backupRegs); - return _SUCCESS; + return status; } int Efuse_PgPacketRead(PADAPTER adapter, u8 offset, u8 *data, BOOLEAN test) @@ -1240,118 +1658,28 @@ hal_EfusePgPacketWriteData( if (badworden != 0x0F) { RTW_INFO("%s: Fail!!\n", __FUNCTION__); return _FALSE; - } else - RTW_INFO("%s: OK!!\n", __FUNCTION__); - - return _TRUE; -} - -/* *********************************************************** - * Efuse related code - * *********************************************************** */ -static u8 -hal_EfuseSwitchToBank( - PADAPTER padapter, - u8 bank, - u8 bPseudoTest) -{ - u8 bRet = _FALSE; - u32 value32 = 0; -#ifdef HAL_EFUSE_MEMORY - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; -#endif - - - RTW_INFO("%s: Efuse switch bank to %d\n", __FUNCTION__, bank); - if (bPseudoTest) { -#ifdef HAL_EFUSE_MEMORY - pEfuseHal->fakeEfuseBank = bank; -#else - fakeEfuseBank = bank; -#endif - bRet = _TRUE; - } else { - value32 = rtw_read32(padapter, 0x34); - bRet = _TRUE; - switch (bank) { - case 0: - value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); - break; - case 1: - value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0); - break; - case 2: - value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1); - break; - case 3: - value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2); - break; - default: - value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); - bRet = _FALSE; - break; - } - rtw_write32(padapter, 0x34, value32); - } - - return bRet; -} - - -#define EFUSE_CTRL 0x30 /* E-Fuse Control. */ - -/* 11/16/2008 MH Read one byte from real Efuse. */ -u8 -efuse_OneByteRead( - IN PADAPTER pAdapter, - IN u16 addr, - IN u8 *data, - IN BOOLEAN bPseudoTest) -{ - u32 tmpidx = 0; - u8 bResult; - u8 readbyte; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - if (IS_HARDWARE_TYPE_8723B(pAdapter) || - (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) || - (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id)) - ) { - /* <20130121, Kordan> For SMIC EFUSE specificatoin. */ - /* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */ - /* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */ - rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) & (~BIT11)); - } - - /* -----------------e-fuse reg ctrl --------------------------------- */ - /* address */ - rtw_write8(pAdapter, EFUSE_CTRL + 1, (u8)(addr & 0xff)); - rtw_write8(pAdapter, EFUSE_CTRL + 2, ((u8)((addr >> 8) & 0x03)) | - (rtw_read8(pAdapter, EFUSE_CTRL + 2) & 0xFC)); + } else + RTW_INFO("%s: OK!!\n", __FUNCTION__); - /* rtw_write8(pAdapter, EFUSE_CTRL+3, 0x72); */ /* read cmd */ - /* Write bit 32 0 */ - readbyte = rtw_read8(pAdapter, EFUSE_CTRL + 3); - rtw_write8(pAdapter, EFUSE_CTRL + 3, (readbyte & 0x7f)); + return _TRUE; +} - while (!(0x80 & rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 1000)) { - rtw_mdelay_os(1); - tmpidx++; - } - if (tmpidx < 100) { - *data = rtw_read8(pAdapter, EFUSE_CTRL); - bResult = _TRUE; - } else { - *data = 0xff; - bResult = _FALSE; - RTW_INFO("%s: [ERROR] addr=0x%x bResult=%d time out 1s !!!\n", __FUNCTION__, addr, bResult); - RTW_INFO("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL)); - } +u8 efuse_OneByteRead(struct _ADAPTER *a, u16 addr, u8 *data, u8 bPseudoTest) +{ + struct dvobj_priv *d; + int err; + u8 ret = _TRUE; - return bResult; -} + d = adapter_to_dvobj(a); + err = rtw_halmac_read_physical_efuse(d, addr, 1, data); + if (err) { + RTW_ERR("%s: addr=0x%x FAIL!!!\n", __FUNCTION__, addr); + ret = _FALSE; + } + return ret; + +} static u16 hal_EfuseGetCurrentSize_BT( @@ -1492,47 +1820,6 @@ u8 EfusePgPacketWrite_BT( #define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ /* ------------------------------------------------------------------------------ */ -VOID efuse_PreUpdateAction( - PADAPTER pAdapter, - pu4Byte BackupRegs) -{ -#if defined(CONFIG_RTL8812A) - if (IS_HARDWARE_TYPE_8812AU(pAdapter)) { - /* <20131115, Kordan> Turn off Rx to prevent from being busy when writing the EFUSE. (Asked by Chunchu.)*/ - BackupRegs[0] = phy_query_mac_reg(pAdapter, REG_RCR, bMaskDWord); - BackupRegs[1] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord); - BackupRegs[2] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord); - BackupRegs[3] = phy_query_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord); - - PlatformEFIOWrite4Byte(pAdapter, REG_RCR, 0x1); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0, 0); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+1, 0); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+2, 0); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+3, 0); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+4, 0); - PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+5, 0); - - /* <20140410, Kordan> 0x11 = 0x4E, lower down LX_SPS0 voltage. (Asked by Chunchu)*/ - phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskByte1, 0x4E); - } -#endif -} - -VOID efuse_PostUpdateAction( - PADAPTER pAdapter, - pu4Byte BackupRegs) -{ -#if defined(CONFIG_RTL8812A) - if (IS_HARDWARE_TYPE_8812AU(pAdapter)) { - /* <20131115, Kordan> Turn on Rx and restore the registers. (Asked by Chunchu.)*/ - phy_set_mac_reg(pAdapter, REG_RCR, bMaskDWord, BackupRegs[0]); - phy_set_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord, BackupRegs[1]); - phy_set_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord, BackupRegs[2]); - phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord, BackupRegs[3]); - } -#endif -} - BOOLEAN Efuse_Read1ByteFromFakeContent( @@ -1662,7 +1949,7 @@ ReadEFuseByte( u32 value32; u8 readbyte; u16 retry; - /* u32 start=rtw_get_current_time(); */ + /* systime start=rtw_get_current_time(); */ if (bPseudoTest) { Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf); @@ -1777,6 +2064,14 @@ efuse_OneByteRead( return bResult; } +#ifdef CONFIG_RTL8710B + /* <20171208, Peter>, Dont do the following write16(0x34) */ + if (IS_HARDWARE_TYPE_8710B(pAdapter)) { + bResult = pAdapter->hal_func.efuse_indirect_read4(pAdapter, addr, data); + return bResult; + } +#endif + if (IS_HARDWARE_TYPE_8723B(pAdapter) || (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) || (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id)) @@ -2085,8 +2380,9 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) return _FAIL; \ } + u8 *efuse = NULL; u8 offset, word_en; - u8 *map; + u8 *map = NULL; u8 newdata[PGPKT_DATA_SIZE]; s32 i, j, idx, chk_total_byte; u8 ret = _SUCCESS; @@ -2105,26 +2401,36 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */ RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */ + efuse = rtw_zmalloc(mapLen); + if (!efuse) + return _FAIL; + map = rtw_zmalloc(mapLen); - if (map == NULL) + if (map == NULL) { + rtw_mfree(efuse, mapLen); return _FAIL; + } _rtw_memset(map, 0xFF, mapLen); ret = rtw_efuse_map_read(padapter, 0, mapLen, map); + if (ret == _FAIL) goto exit; + _rtw_memcpy(efuse , map, mapLen); + _rtw_memcpy(efuse + addr, data, cnts); + if (padapter->registrypriv.boffefusemask == 0) { for (i = 0; i < cnts; i++) { if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask. */ - data[i] = map[addr + i]; + efuse[addr + i] = map[addr + i]; } else { if (efuse_IsMasked(padapter, addr + i)) - data[i] = map[addr + i]; + efuse[addr + i] = map[addr + i]; } - RTW_INFO("%s , data[%d] = %x, map[addr+i]= %x\n", __func__, i, data[i], map[addr + i]); + RTW_INFO("%s ,Write data[%d] = %x, map[%d]= %x\n", __func__, addr + i, efuse[ addr + i], addr + i, map[addr + i]); } } /*Efuse_PowerSwitch(padapter, _TRUE, _TRUE);*/ @@ -2137,7 +2443,7 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) word_en = 0xF; j = (addr + idx) & 0x7; for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) { - if (data[idx] != map[addr + idx]) + if (efuse[addr + idx] != map[addr + idx]) word_en &= ~BIT(i >> 1); } @@ -2178,9 +2484,9 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) j = (addr + idx) & 0x7; _rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE); for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) { - if (data[idx] != map[addr + idx]) { + if (efuse[addr + idx] != map[addr + idx]) { word_en &= ~BIT(i >> 1); - newdata[i] = data[idx]; + newdata[i] = efuse[addr + idx]; #ifdef CONFIG_RTL8723B if (addr + idx == 0x8) { if (IS_C_CUT(pHalData->version_id) || IS_B_CUT(pHalData->version_id)) { @@ -2215,6 +2521,7 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) exit: rtw_mfree(map, mapLen); + rtw_mfree(efuse, mapLen); return ret; } @@ -2341,67 +2648,6 @@ Efuse_ReadAllMap( Efuse_PowerSwitch(pAdapter, _FALSE, _FALSE); } -/*----------------------------------------------------------------------------- - * Function: efuse_ShadowRead1Byte - * efuse_ShadowRead2Byte - * efuse_ShadowRead4Byte - * - * Overview: Read from efuse init map by one/two/four bytes !!!!! - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/12/2008 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -static VOID -efuse_ShadowRead1Byte( - IN PADAPTER pAdapter, - IN u16 Offset, - IN OUT u8 *Value) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - - *Value = pHalData->efuse_eeprom_data[Offset]; - -} /* EFUSE_ShadowRead1Byte */ - -/* ---------------Read Two Bytes */ -static VOID -efuse_ShadowRead2Byte( - IN PADAPTER pAdapter, - IN u16 Offset, - IN OUT u16 *Value) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - - *Value = pHalData->efuse_eeprom_data[Offset]; - *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8; - -} /* EFUSE_ShadowRead2Byte */ - -/* ---------------Read Four Bytes */ -static VOID -efuse_ShadowRead4Byte( - IN PADAPTER pAdapter, - IN u16 Offset, - IN OUT u32 *Value) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - - *Value = pHalData->efuse_eeprom_data[Offset]; - *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8; - *Value |= pHalData->efuse_eeprom_data[Offset + 2] << 16; - *Value |= pHalData->efuse_eeprom_data[Offset + 3] << 24; - -} /* efuse_ShadowRead4Byte */ - - /*----------------------------------------------------------------------------- * Function: efuse_ShadowWrite1Byte * efuse_ShadowWrite2Byte @@ -2472,38 +2718,6 @@ efuse_ShadowWrite4Byte( } /* efuse_ShadowWrite1Byte */ -/*----------------------------------------------------------------------------- - * Function: EFUSE_ShadowRead - * - * Overview: Read from efuse init map !!!!! - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/12/2008 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -void -EFUSE_ShadowRead( - IN PADAPTER pAdapter, - IN u8 Type, - IN u16 Offset, - IN OUT u32 *Value) -{ - if (Type == 1) - efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value); - else if (Type == 2) - efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value); - else if (Type == 4) - efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value); - -} /* EFUSE_ShadowRead */ - /*----------------------------------------------------------------------------- * Function: EFUSE_ShadowWrite * @@ -2575,6 +2789,87 @@ Efuse_InitSomeVar( _rtw_memset((PVOID)&fakeBTEfuseModifiedMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN); } #endif /* !RTW_HALMAC */ +/*----------------------------------------------------------------------------- + * Function: efuse_ShadowRead1Byte + * efuse_ShadowRead2Byte + * efuse_ShadowRead4Byte + * + * Overview: Read from efuse init map by one/two/four bytes !!!!! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +static VOID +efuse_ShadowRead1Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN OUT u8 *Value) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + *Value = pHalData->efuse_eeprom_data[Offset]; + +} /* EFUSE_ShadowRead1Byte */ + +/* ---------------Read Two Bytes */ +static VOID +efuse_ShadowRead2Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN OUT u16 *Value) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + *Value = pHalData->efuse_eeprom_data[Offset]; + *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8; + +} /* EFUSE_ShadowRead2Byte */ + +/* ---------------Read Four Bytes */ +static VOID +efuse_ShadowRead4Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN OUT u32 *Value) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + *Value = pHalData->efuse_eeprom_data[Offset]; + *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8; + *Value |= pHalData->efuse_eeprom_data[Offset + 2] << 16; + *Value |= pHalData->efuse_eeprom_data[Offset + 3] << 24; + +} /* efuse_ShadowRead4Byte */ + +/*----------------------------------------------------------------------------- + * Function: EFUSE_ShadowRead + * + * Overview: Read from pHalData->efuse_eeprom_data + *---------------------------------------------------------------------------*/ +void +EFUSE_ShadowRead( + IN PADAPTER pAdapter, + IN u8 Type, + IN u16 Offset, + IN OUT u32 *Value) +{ + if (Type == 1) + efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value); + else if (Type == 2) + efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value); + else if (Type == 4) + efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value); + +} /* EFUSE_ShadowRead */ + /* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */ u8 Efuse_CalculateWordCnts(IN u8 word_en) @@ -2676,7 +2971,7 @@ void EFUSE_ShadowMapUpdate( } if (pHalData->bautoload_fail_flag == _FALSE) { - err = rtw_halmac_read_logical_efuse_map(adapter_to_dvobj(pAdapter), efuse_map, mapLen); + err = rtw_halmac_read_logical_efuse_map(adapter_to_dvobj(pAdapter), efuse_map, mapLen, NULL, 0); if (err) RTW_ERR("%s: fail to get efuse map!\n", __FUNCTION__); } @@ -2702,6 +2997,8 @@ void EFUSE_ShadowMapUpdate( /* (PVOID)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen); */ #endif /* !RTW_HALMAC */ + rtw_mask_map_read(pAdapter, 0x00, mapLen, pHalData->efuse_eeprom_data); + rtw_dump_cur_efuse(pAdapter); } /* EFUSE_ShadowMapUpdate */ @@ -2808,7 +3105,7 @@ u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len) return _FALSE; count = rtw_retrieve_from_file(filepatch, ptmpbuf, bufsize); - if (count <= 100) { + if (count <= 90) { rtw_mfree(ptmpbuf, bufsize); RTW_ERR("%s, filepatch %s, size=%d, FAIL!!\n", __FUNCTION__, filepatch, count); return _FALSE; diff --git a/core/mesh/rtw_mesh.c b/core/mesh/rtw_mesh.c new file mode 100644 index 0000000..8eaedac --- /dev/null +++ b/core/mesh/rtw_mesh.c @@ -0,0 +1,4097 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_MESH_C_ + +#ifdef CONFIG_RTW_MESH +#include + +const char *_rtw_mesh_plink_str[] = { + "UNKNOWN", + "LISTEN", + "OPN_SNT", + "OPN_RCVD", + "CNF_RCVD", + "ESTAB", + "HOLDING", + "BLOCKED", +}; + +const char *_rtw_mesh_ps_str[] = { + "UNKNOWN", + "ACTIVE", + "LSLEEP", + "DSLEEP", +}; + +const char *_action_self_protected_str[] = { + "ACT_SELF_PROTECTED_RSVD", + "MESH_OPEN", + "MESH_CONF", + "MESH_CLOSE", + "MESH_GK_INFORM", + "MESH_GK_ACK", +}; + +inline u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len) +{ + return rtw_set_ie(buf, WLAN_EID_MESH_ID, id_len, mesh_id, buf_len); +} + +inline u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len + , u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto + , u8 num_of_peerings, bool cto_mgate, bool cto_as + , bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding + , bool mbca_en, bool tbtt_adj, bool ps_level) +{ + + u8 conf[7] = {0}; + + SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(conf, path_sel_proto); + SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(conf, path_sel_metric); + SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(conf, congest_ctl_mode); + SET_MESH_CONF_ELE_SYNC_METHOD_ID(conf, sync_method); + SET_MESH_CONF_ELE_AUTH_PROTO_ID(conf, auth_proto); + + SET_MESH_CONF_ELE_CTO_MGATE(conf, cto_mgate); + SET_MESH_CONF_ELE_NUM_OF_PEERINGS(conf, num_of_peerings); + SET_MESH_CONF_ELE_CTO_AS(conf, cto_as); + + SET_MESH_CONF_ELE_ACCEPT_PEERINGS(conf, accept_peerings); + SET_MESH_CONF_ELE_MCCA_SUP(conf, mcca_sup); + SET_MESH_CONF_ELE_MCCA_EN(conf, mcca_en); + SET_MESH_CONF_ELE_FORWARDING(conf, forwarding); + SET_MESH_CONF_ELE_MBCA_EN(conf, mbca_en); + SET_MESH_CONF_ELE_TBTT_ADJ(conf, tbtt_adj); + SET_MESH_CONF_ELE_PS_LEVEL(conf, ps_level); + + return rtw_set_ie(buf, WLAN_EID_MESH_CONFIG, 7, conf, buf_len); +} + +inline u8 *rtw_set_ie_mpm(u8 *buf, u32 *buf_len + , u8 proto_id, u16 llid, u16 *plid, u16 *reason, u8 *chosen_pmk) +{ + u8 data[24] = {0}; + u8 *pos = data; + + RTW_PUT_LE16(pos, proto_id); + pos += 2; + + RTW_PUT_LE16(pos, llid); + pos += 2; + + if (plid) { + RTW_PUT_LE16(pos, *plid); + pos += 2; + } + + if (reason) { + RTW_PUT_LE16(pos, *reason); + pos += 2; + } + + if (chosen_pmk) { + _rtw_memcpy(pos, chosen_pmk, 16); + pos += 16; + } + + return rtw_set_ie(buf, WLAN_EID_MPM, pos - data, data, buf_len); +} + +bool rtw_bss_is_forwarding(WLAN_BSSID_EX *bss) +{ + u8 *ie; + int ie_len; + bool ret = 0; + + ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, + BSS_EX_TLV_IES_LEN(bss)); + if (!ie || ie_len != 7) + goto exit; + + ret = GET_MESH_CONF_ELE_FORWARDING(ie + 2); + +exit: + return ret; +} + +bool rtw_bss_is_cto_mgate(WLAN_BSSID_EX *bss) +{ + u8 *ie; + int ie_len; + bool ret = 0; + + ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, + BSS_EX_TLV_IES_LEN(bss)); + if (!ie || ie_len != 7) + goto exit; + + ret = GET_MESH_CONF_ELE_CTO_MGATE(ie + 2); + +exit: + return ret; +} + +int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b) +{ + int ret = 0; + u8 *a_mconf_ie, *b_mconf_ie; + sint a_mconf_ie_len, b_mconf_ie_len; + + if (a->InfrastructureMode != Ndis802_11_mesh) + goto exit; + a_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(a), WLAN_EID_MESH_CONFIG, &a_mconf_ie_len, BSS_EX_TLV_IES_LEN(a)); + if (!a_mconf_ie || a_mconf_ie_len != 7) + goto exit; + if (b->InfrastructureMode != Ndis802_11_mesh) + goto exit; + b_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(b), WLAN_EID_MESH_CONFIG, &b_mconf_ie_len, BSS_EX_TLV_IES_LEN(b)); + if (!b_mconf_ie || b_mconf_ie_len != 7) + goto exit; + + if (a->mesh_id.SsidLength != b->mesh_id.SsidLength + || _rtw_memcmp(a->mesh_id.Ssid, b->mesh_id.Ssid, a->mesh_id.SsidLength) == _FALSE) + goto exit; + + if (_rtw_memcmp(a_mconf_ie + 2, b_mconf_ie + 2, 5) == _FALSE) + goto exit; + + ret = 1; + +exit: + return ret; +} + +int rtw_bss_is_candidate_mesh_peer(WLAN_BSSID_EX *self, WLAN_BSSID_EX *target, u8 ch, u8 add_peer) +{ + int ret = 0; + u8 *mconf_ie; + sint mconf_ie_len; + int i, j; + + if (!rtw_bss_is_same_mbss(self, target)) + goto exit; + + if (ch && self->Configuration.DSConfig != target->Configuration.DSConfig) + goto exit; + + if (add_peer) { + /* Accept additional mesh peerings */ + mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(target), WLAN_EID_MESH_CONFIG, &mconf_ie_len, BSS_EX_TLV_IES_LEN(target)); + if (!mconf_ie || mconf_ie_len != 7) + goto exit; + if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mconf_ie + 2) == 0) + goto exit; + } + + /* BSSBasicRateSet */ + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (target->SupportedRates[i] == 0) + break; + if (target->SupportedRates[i] & 0x80) { + u8 match = 0; + + if (!ch) { + /* off-channel, check target with our hardcode capability */ + if (target->Configuration.DSConfig > 14) + match = rtw_is_basic_rate_ofdm(target->SupportedRates[i]); + else + match = rtw_is_basic_rate_mix(target->SupportedRates[i]); + } else { + for (j = 0; j < NDIS_802_11_LENGTH_RATES_EX; j++) { + if (self->SupportedRates[j] == 0) + break; + if (self->SupportedRates[j] == target->SupportedRates[i]) { + match = 1; + break; + } + } + } + if (!match) + goto exit; + } + } + + + /* BSSBasicMCSSet */ + + /* 802.1X connected to AS ? */ + + ret = 1; + +exit: + return ret; +} + +void rtw_mesh_bss_peering_status(WLAN_BSSID_EX *bss, u8 *nop, u8 *accept) +{ + u8 *ie; + int ie_len; + + if (nop) + *nop = 0; + if (accept) + *accept = 0; + + ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, + BSS_EX_TLV_IES_LEN(bss)); + if (!ie || ie_len != 7) + goto exit; + + if (nop) + *nop = GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2); + if (accept) + *accept = GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2); + +exit: + return; +} + +#if CONFIG_RTW_MESH_ACNODE_PREVENT +void rtw_mesh_update_scanned_acnode_status(_adapter *adapter, struct wlan_network *scanned) +{ + bool acnode; + u8 nop, accept; + + rtw_mesh_bss_peering_status(&scanned->network, &nop, &accept); + + acnode = !nop && accept; + + if (acnode && scanned->acnode_stime == 0) { + scanned->acnode_stime = rtw_get_current_time(); + if (scanned->acnode_stime == 0) + scanned->acnode_stime++; + } else if (!acnode) { + scanned->acnode_stime = 0; + scanned->acnode_notify_etime = 0; + } +} + +bool rtw_mesh_scanned_is_acnode_confirmed(_adapter *adapter, struct wlan_network *scanned) +{ + return scanned->acnode_stime + && rtw_get_passing_time_ms(scanned->acnode_stime) + > adapter->mesh_cfg.peer_sel_policy.acnode_conf_timeout_ms; +} + +static bool rtw_mesh_scanned_is_acnode_allow_notify(_adapter *adapter, struct wlan_network *scanned) +{ + return scanned->acnode_notify_etime + && rtw_time_after(scanned->acnode_notify_etime, rtw_get_current_time()); +} + +bool rtw_mesh_acnode_prevent_allow_sacrifice(_adapter *adapter) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct sta_priv *stapriv = &adapter->stapriv; + bool allow = 0; + + if (!mcfg->peer_sel_policy.acnode_prevent + || mcfg->max_peer_links <= 1 + || stapriv->asoc_list_cnt < mcfg->max_peer_links) + goto exit; + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + if (rtw_mesh_cto_mgate_required(adapter)) + goto exit; +#endif + + allow = 1; + +exit: + return allow; +} + +static bool rtw_mesh_acnode_candidate_exist(_adapter *adapter) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct sta_priv *stapriv = &adapter->stapriv; + struct mlme_priv *mlme = &adapter->mlmepriv; + _queue *queue = &(mlme->scanned_queue); + _list *head, *list; + _irqL irqL; + struct wlan_network *scanned = NULL; + struct sta_info *sta = NULL; + bool need = 0; + + _enter_critical_bh(&(mlme->scanned_queue.lock), &irqL); + + head = get_list_head(queue); + list = get_next(head); + while (!rtw_end_of_queue_search(head, list)) { + scanned = LIST_CONTAINOR(list, struct wlan_network, list); + list = get_next(list); + + if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms + && rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned) + && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi) + #if CONFIG_RTW_MACADDR_ACL + && rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE + #endif + && rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1) + #if CONFIG_RTW_MESH_PEER_BLACKLIST + && !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress) + #endif + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + && rtw_mesh_cto_mgate_network_filter(adapter, scanned) + #endif + ) { + need = 1; + break; + } + } + + _exit_critical_bh(&(mlme->scanned_queue.lock), &irqL); + +exit: + return need; +} + +static int rtw_mesh_acnode_prevent_sacrifice_chk(_adapter *adapter, struct sta_info **sac, struct sta_info *com) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + int updated = 0; + + /* + * TODO: compare next_hop reference cnt of forwarding info + * don't sacrifice working next_hop or choose sta with least cnt + */ + + if (*sac == NULL) { + updated = 1; + goto exit; + } + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + if (mcfg->peer_sel_policy.cto_mgate_require + && !mcfg->dot11MeshGateAnnouncementProtocol + ) { + if (IS_CTO_MGATE_CONF_TIMEOUT(com->plink)) { + if (!IS_CTO_MGATE_CONF_TIMEOUT((*sac)->plink)) { + /* blacklist > not blacklist */ + updated = 1; + goto exit; + } + } else if (!IS_CTO_MGATE_CONF_DISABLED(com->plink)) { + if (IS_CTO_MGATE_CONF_DISABLED((*sac)->plink)) { + /* confirming > disabled */ + updated = 1; + goto exit; + } + } + } +#endif + +exit: + if (updated) + *sac = com; + + return updated; +} + +struct sta_info *_rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter) +{ + struct sta_priv *stapriv = &adapter->stapriv; + _list *head, *list; + struct sta_info *sta, *sacrifice = NULL; + u8 nop; + + head = &stapriv->asoc_list; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + sta = LIST_CONTAINOR(list, struct sta_info, asoc_list); + list = get_next(list); + + if (!sta->plink || !sta->plink->scanned) { + rtw_warn_on(1); + continue; + } + + rtw_mesh_bss_peering_status(&sta->plink->scanned->network, &nop, NULL); + if (nop < 2) + continue; + + rtw_mesh_acnode_prevent_sacrifice_chk(adapter, &sacrifice, sta); + } + + return sacrifice; +} + +struct sta_info *rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sacrifice = NULL; + + enter_critical_bh(&stapriv->asoc_list_lock); + + sacrifice = _rtw_mesh_acnode_prevent_pick_sacrifice(adapter); + + exit_critical_bh(&stapriv->asoc_list_lock); + + return sacrifice; +} + +static void rtw_mesh_acnode_rsvd_chk(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + u8 acnode_rsvd = 0; + + if (rtw_mesh_acnode_prevent_allow_sacrifice(adapter) + && rtw_mesh_acnode_prevent_pick_sacrifice(adapter) + && rtw_mesh_acnode_candidate_exist(adapter)) + acnode_rsvd = 1; + + if (plink_ctl->acnode_rsvd != acnode_rsvd) { + plink_ctl->acnode_rsvd = acnode_rsvd; + RTW_INFO(FUNC_ADPT_FMT" acnode_rsvd = %d\n", FUNC_ADPT_ARG(adapter), plink_ctl->acnode_rsvd); + update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, 1); + } +} + +static void rtw_mesh_acnode_set_notify_etime(_adapter *adapter, u8 *rframe_whdr) +{ + if (adapter->mesh_info.plink_ctl.acnode_rsvd) { + struct wlan_network *scanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, get_addr2_ptr(rframe_whdr)); + + if (rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned)) { + scanned->acnode_notify_etime = rtw_get_current_time() + + rtw_ms_to_systime(adapter->mesh_cfg.peer_sel_policy.acnode_notify_timeout_ms); + if (scanned->acnode_notify_etime == 0) + scanned->acnode_notify_etime++; + } + } +} + +void dump_mesh_acnode_prevent_settings(void *sel, _adapter *adapter) +{ + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + + RTW_PRINT_SEL(sel, "%-6s %-12s %-14s\n" + , "enable", "conf_timeout", "nofity_timeout"); + RTW_PRINT_SEL(sel, "%6u %12u %14u\n" + , peer_sel_policy->acnode_prevent + , peer_sel_policy->acnode_conf_timeout_ms + , peer_sel_policy->acnode_notify_timeout_ms); +} +#endif /* CONFIG_RTW_MESH_ACNODE_PREVENT */ + +#if CONFIG_RTW_MESH_PEER_BLACKLIST +int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_add(&plink_ctl->peer_blacklist, addr + , mcfg->peer_sel_policy.peer_blacklist_timeout_ms); +} + +int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_del(&plink_ctl->peer_blacklist, addr); +} + +int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_search(&plink_ctl->peer_blacklist, addr); +} + +void rtw_mesh_peer_blacklist_flush(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + rtw_blacklist_flush(&plink_ctl->peer_blacklist); +} + +void dump_mesh_peer_blacklist(void *sel, _adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + dump_blacklist(sel, &plink_ctl->peer_blacklist, "blacklist"); +} + +void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter) +{ + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + + RTW_PRINT_SEL(sel, "%-12s %-17s\n" + , "conf_timeout", "blacklist_timeout"); + RTW_PRINT_SEL(sel, "%12u %17u\n" + , peer_sel_policy->peer_conf_timeout_ms + , peer_sel_policy->peer_blacklist_timeout_ms); +} +#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */ + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST +u8 rtw_mesh_cto_mgate_required(_adapter *adapter) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + return mcfg->peer_sel_policy.cto_mgate_require + && !rtw_bss_is_cto_mgate(&(mlmeext->mlmext_info.network)); +} + +u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + return !rtw_mesh_cto_mgate_required(adapter) + || (rtw_bss_is_cto_mgate(&scanned->network) + && !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress)); +} + +int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_add(&plink_ctl->cto_mgate_blacklist, addr + , mcfg->peer_sel_policy.cto_mgate_blacklist_timeout_ms); +} + +int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_del(&plink_ctl->cto_mgate_blacklist, addr); +} + +int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + return rtw_blacklist_search(&plink_ctl->cto_mgate_blacklist, addr); +} + +void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + rtw_blacklist_flush(&plink_ctl->cto_mgate_blacklist); +} + +void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + dump_blacklist(sel, &plink_ctl->cto_mgate_blacklist, "blacklist"); +} + +void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter) +{ + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + + RTW_PRINT_SEL(sel, "%-12s %-17s\n" + , "conf_timeout", "blacklist_timeout"); + RTW_PRINT_SEL(sel, "%12u %17u\n" + , peer_sel_policy->cto_mgate_conf_timeout_ms + , peer_sel_policy->cto_mgate_blacklist_timeout_ms); +} + +static void rtw_mesh_cto_mgate_blacklist_chk(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + _queue *blist = &plink_ctl->cto_mgate_blacklist; + _list *list, *head; + struct blacklist_ent *ent = NULL; + struct wlan_network *scanned = NULL; + + enter_critical_bh(&blist->lock); + head = &blist->queue; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + continue; + } + + scanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, ent->addr); + if (!scanned) + continue; + + if (rtw_bss_is_forwarding(&scanned->network)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } + } + + exit_critical_bh(&blist->lock); +} +#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ + +void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct mlme_priv *mlme = &adapter->mlmepriv; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + bool acnode = 0; + + if (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl)) + goto exit; + + if (plink_ctl->num >= RTW_MESH_MAX_PEER_CANDIDATES) + goto exit; + +#if CONFIG_RTW_MESH_ACNODE_PREVENT + if (plink_ctl->acnode_rsvd) { + acnode = rtw_mesh_scanned_is_acnode_confirmed(adapter, scanned); + if (acnode && !rtw_mesh_scanned_is_acnode_allow_notify(adapter, scanned)) + goto exit; + } +#endif + + /* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */ + if (plink_ctl->num >= mcfg->max_peer_links + acnode ? 1 : 0) + goto exit; + + if (rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms + || (mcfg->rssi_threshold && mcfg->rssi_threshold > scanned->network.Rssi) + || !rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1) + #if CONFIG_RTW_MACADDR_ACL + || rtw_access_ctrl(adapter, scanned->network.MacAddress) == _FALSE + #endif + || rtw_mesh_plink_get(adapter, scanned->network.MacAddress) + #if CONFIG_RTW_MESH_PEER_BLACKLIST + || rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress) + #endif + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + || !rtw_mesh_cto_mgate_network_filter(adapter, scanned) + #endif + ) + goto exit; + +#if CONFIG_RTW_MESH_ACNODE_PREVENT + if (acnode) { + scanned->acnode_notify_etime = 0; + RTW_INFO(FUNC_ADPT_FMT" acnode "MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(scanned->network.MacAddress)); + } +#endif + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev + , scanned->network.MacAddress + , BSS_EX_TLV_IES(&scanned->network) + , BSS_EX_TLV_IES_LEN(&scanned->network) + , GFP_ATOMIC + ); +#endif + +exit: + return; +} + +void rtw_mesh_peer_status_chk(_adapter *adapter) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *plink; + _list *head, *list; + struct sta_info *sta = NULL; + struct sta_priv *stapriv = &adapter->stapriv; + int stainfo_offset; +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + u8 cto_mgate, forwarding, mgate; +#endif + u8 flush; + s8 flush_list[NUM_STA]; + u8 flush_num = 0; + int i; + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + if (rtw_mesh_cto_mgate_required(adapter)) { + /* active scan on operating channel */ + issue_probereq_ex(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, NULL, 0, 0, 0, 0); + } +#endif + + enter_critical_bh(&(plink_ctl->lock)); + + /* check established peers */ + enter_critical_bh(&stapriv->asoc_list_lock); + + head = &stapriv->asoc_list; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + sta = LIST_CONTAINOR(list, struct sta_info, asoc_list); + list = get_next(list); + + if (!sta->plink || !sta->plink->scanned) { + rtw_warn_on(1); + continue; + } + plink = sta->plink; + flush = 0; + + /* remove unsuitable peer */ + if (!rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &plink->scanned->network, 1, 0) + #if CONFIG_RTW_MACADDR_ACL + || rtw_access_ctrl(adapter, plink->addr) == _FALSE + #endif + ) { + flush = 1; + goto flush_add; + } + + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + cto_mgate = rtw_bss_is_cto_mgate(&(plink->scanned->network)); + forwarding = rtw_bss_is_forwarding(&(plink->scanned->network)); + mgate = rtw_mesh_gate_search(minfo->mesh_paths, sta->cmn.mac_addr); + + /* CTO_MGATE required, remove peer without CTO_MGATE */ + if (rtw_mesh_cto_mgate_required(adapter) && !cto_mgate) { + flush = 1; + goto flush_add; + } + + /* cto_mgate_conf status update */ + if (IS_CTO_MGATE_CONF_DISABLED(plink)) { + if (cto_mgate && !forwarding && !mgate) + SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms); + else + rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr); + } else { + /* cto_mgate_conf ongoing */ + if (cto_mgate && !forwarding && !mgate) { + if (IS_CTO_MGATE_CONF_TIMEOUT(plink)) { + rtw_mesh_cto_mgate_blacklist_add(adapter, sta->cmn.mac_addr); + + /* CTO_MGATE required, remove peering can't achieve CTO_MGATE */ + if (rtw_mesh_cto_mgate_required(adapter)) { + flush = 1; + goto flush_add; + } + } + } else { + SET_CTO_MGATE_CONF_DISABLED(plink); + rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr); + } + } + #endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ + +flush_add: + if (flush) { + rtw_list_delete(&sta->asoc_list); + stapriv->asoc_list_cnt--; + STA_SET_MESH_PLINK(sta, NULL); + + stainfo_offset = rtw_stainfo_offset(stapriv, sta); + if (stainfo_offset_valid(stainfo_offset)) + flush_list[flush_num++] = stainfo_offset; + else + rtw_warn_on(1); + } + } + + exit_critical_bh(&stapriv->asoc_list_lock); + + /* check non-established peers */ + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + plink = &plink_ctl->ent[i]; + if (plink->valid != _TRUE || plink->plink_state == RTW_MESH_PLINK_ESTAB) + continue; + + /* remove unsuitable peer */ + if (!rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &plink->scanned->network, 1, 1) + #if CONFIG_RTW_MACADDR_ACL + || rtw_access_ctrl(adapter, plink->addr) == _FALSE + #endif + ) { + _rtw_mesh_expire_peer_ent(adapter, plink); + continue; + } + + #if CONFIG_RTW_MESH_PEER_BLACKLIST + /* peer confirm check timeout, add to black list */ + if (IS_PEER_CONF_TIMEOUT(plink)) { + rtw_mesh_peer_blacklist_add(adapter, plink->addr); + _rtw_mesh_expire_peer_ent(adapter, plink); + } + #endif + } + + exit_critical_bh(&(plink_ctl->lock)); + + if (flush_num) { + u8 sta_addr[ETH_ALEN]; + u8 updated = _FALSE; + + for (i = 0; i < flush_num; i++) { + sta = rtw_get_stainfo_by_offset(stapriv, flush_list[i]); + _rtw_memcpy(sta_addr, sta->cmn.mac_addr, ETH_ALEN); + + updated |= ap_free_sta(adapter, sta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _FALSE); + rtw_mesh_expire_peer(adapter, sta_addr); + } + + associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL); + } + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + /* loop cto_mgate_blacklist to remove ent according to scan_r */ + rtw_mesh_cto_mgate_blacklist_chk(adapter); +#endif + +#if CONFIG_RTW_MESH_ACNODE_PREVENT + rtw_mesh_acnode_rsvd_chk(adapter); +#endif + + return; +} + +#if CONFIG_RTW_MESH_OFFCH_CAND +static u8 rtw_mesh_offch_cto_mgate_required(_adapter *adapter) +{ +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct mlme_priv *mlme = &adapter->mlmepriv; + _queue *queue = &(mlme->scanned_queue); + _list *head, *pos; + struct wlan_network *scanned = NULL; + u8 ret = 0; + + if (!rtw_mesh_cto_mgate_required(adapter)) + goto exit; + + enter_critical_bh(&(mlme->scanned_queue.lock)); + + head = get_list_head(queue); + pos = get_next(head); + while (!rtw_end_of_queue_search(head, pos)) { + scanned = LIST_CONTAINOR(pos, struct wlan_network, list); + + if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms + && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi) + #if CONFIG_RTW_MACADDR_ACL + && rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE + #endif + && rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1) + && rtw_bss_is_cto_mgate(&scanned->network) + #if CONFIG_RTW_MESH_PEER_BLACKLIST + && !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress) + #endif + && !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress) + ) + break; + + pos = get_next(pos); + } + + if (rtw_end_of_queue_search(head, pos)) + ret = 1; + + exit_critical_bh(&(mlme->scanned_queue.lock)); + +exit: + return ret; +#else + return 0; +#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ +} + +u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + u8 ret = 0; + + if (!adapter->mesh_cfg.peer_sel_policy.offch_cand) + goto exit; + + ret = MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter) + && (!plink_ctl->num || rtw_mesh_offch_cto_mgate_required(adapter)) + ; + +#ifdef CONFIG_CONCURRENT_MODE + if (ret) { + struct mi_state mstate_no_self; + + rtw_mi_status_no_self(adapter, &mstate_no_self); + if (MSTATE_STA_LD_NUM(&mstate_no_self)) + ret = 0; + } +#endif + +exit: + return ret; +} + +/* + * this function is called under off channel candidate is required + * the channel with maximum candidate count is selected +*/ +u8 rtw_mesh_select_operating_ch(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct mlme_priv *mlme = &adapter->mlmepriv; + _queue *queue = &(mlme->scanned_queue); + _list *head, *pos; + _irqL irqL; + struct wlan_network *scanned = NULL; + int i; + /* statistics for candidate accept peering */ + u8 cand_ap_cnt[MAX_CHANNEL_NUM] = {0}; + u8 max_cand_ap_ch = 0; + u8 max_cand_ap_cnt = 0; + /* statistics for candidate including not accept peering */ + u8 cand_cnt[MAX_CHANNEL_NUM] = {0}; + u8 max_cand_ch = 0; + u8 max_cand_cnt = 0; + + _enter_critical_bh(&(mlme->scanned_queue.lock), &irqL); + + head = get_list_head(queue); + pos = get_next(head); + while (!rtw_end_of_queue_search(head, pos)) { + scanned = LIST_CONTAINOR(pos, struct wlan_network, list); + pos = get_next(pos); + + if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms + && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi) + #if CONFIG_RTW_MACADDR_ACL + && rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE + #endif + && rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 0, 0) + #if CONFIG_RTW_MESH_PEER_BLACKLIST + && !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress) + #endif + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + && rtw_mesh_cto_mgate_network_filter(adapter, scanned) + #endif + ) { + int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scanned->network.Configuration.DSConfig); + + if (ch_set_idx >= 0 + && !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx]) + ) { + u8 nop, accept; + + rtw_mesh_bss_peering_status(&scanned->network, &nop, &accept); + cand_cnt[ch_set_idx]++; + if (max_cand_cnt < cand_cnt[ch_set_idx]) { + max_cand_cnt = cand_cnt[ch_set_idx]; + max_cand_ch = rfctl->channel_set[ch_set_idx].ChannelNum; + } + if (accept) { + cand_ap_cnt[ch_set_idx]++; + if (max_cand_ap_cnt < cand_ap_cnt[ch_set_idx]) { + max_cand_ap_cnt = cand_ap_cnt[ch_set_idx]; + max_cand_ap_ch = rfctl->channel_set[ch_set_idx].ChannelNum; + } + } + } + } + } + + _exit_critical_bh(&(mlme->scanned_queue.lock), &irqL); + + return max_cand_ap_ch ? max_cand_ap_ch : max_cand_ch; +} + +void dump_mesh_offch_cand_settings(void *sel, _adapter *adapter) +{ + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + + RTW_PRINT_SEL(sel, "%-6s %-11s\n" + , "enable", "find_int_ms"); + RTW_PRINT_SEL(sel, "%6u %11u\n" + , peer_sel_policy->offch_cand, peer_sel_policy->offch_find_int_ms); +} +#endif /* CONFIG_RTW_MESH_OFFCH_CAND */ + +void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter) +{ + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + + RTW_PRINT_SEL(sel, "%-12s\n", "scanr_exp_ms"); + RTW_PRINT_SEL(sel, "%12u\n", peer_sel_policy->scanr_exp_ms); +} + +void dump_mesh_networks(void *sel, _adapter *adapter) +{ +#if CONFIG_RTW_MESH_ACNODE_PREVENT +#define NSTATE_TITLE_FMT_ACN " %-5s" +#define NSTATE_VALUE_FMT_ACN " %5d" +#define NSTATE_TITLE_ARG_ACN , "acn" +#define NSTATE_VALUE_ARG_ACN , (acn_ms < 99999 ? acn_ms : 99999) +#else +#define NSTATE_TITLE_FMT_ACN "" +#define NSTATE_VALUE_FMT_ACN "" +#define NSTATE_TITLE_ARG_ACN +#define NSTATE_VALUE_ARG_ACN +#endif + + struct mlme_priv *mlme = &(adapter->mlmepriv); + _queue *queue = &(mlme->scanned_queue); + struct wlan_network *network; + _list *list, *head; + u8 same_mbss; + u8 candidate; + struct mesh_plink_ent *plink; + u8 blocked; + u8 established; + s32 age_ms; +#if CONFIG_RTW_MESH_ACNODE_PREVENT + s32 acn_ms; +#endif + u8 *mesh_conf_ie; + sint mesh_conf_ie_len; + struct wlan_network **mesh_networks; + u8 mesh_network_cnt = 0; + int i; + + mesh_networks = rtw_zvmalloc(mlme->max_bss_cnt * sizeof(struct wlan_network *)); + if (!mesh_networks) + return; + + enter_critical_bh(&queue->lock); + head = get_list_head(queue); + list = get_next(head); + + while (rtw_end_of_queue_search(head, list) == _FALSE) { + network = LIST_CONTAINOR(list, struct wlan_network, list); + list = get_next(list); + + if (network->network.InfrastructureMode != Ndis802_11_mesh) + continue; + + mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG + , &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network)); + if (!mesh_conf_ie || mesh_conf_ie_len != 7) + continue; + + mesh_networks[mesh_network_cnt++] = network; + } + + exit_critical_bh(&queue->lock); + + RTW_PRINT_SEL(sel, " %-17s %-3s %-4s %-5s %-32s %-3s %-3s %-3s" + NSTATE_TITLE_FMT_ACN + "\n" + , "bssid", "ch", "rssi", "age", "mesh_id", "nop", "fwd", "cto" + NSTATE_TITLE_ARG_ACN + ); + + for (i = 0; i < mesh_network_cnt; i++) { + network = mesh_networks[i]; + + if (network->network.InfrastructureMode != Ndis802_11_mesh) + continue; + + mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG + , &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network)); + if (!mesh_conf_ie || mesh_conf_ie_len != 7) + continue; + + age_ms = rtw_get_passing_time_ms(network->last_scanned); + #if CONFIG_RTW_MESH_ACNODE_PREVENT + if (network->acnode_stime == 0) + acn_ms = 0; + else + acn_ms = rtw_get_passing_time_ms(network->acnode_stime); + #endif + same_mbss = 0; + candidate = 0; + plink = NULL; + blocked = 0; + established = 0; + + if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) { + plink = rtw_mesh_plink_get(adapter, network->network.MacAddress); + if (plink && plink->plink_state == RTW_MESH_PLINK_ESTAB) + established = 1; + else if (plink && plink->plink_state == RTW_MESH_PLINK_BLOCKED) + blocked = 1; + else if (plink) + ; + else if (rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &network->network, 0, 1)) + candidate = 1; + else if (rtw_bss_is_same_mbss(&mlme->cur_network.network, &network->network)) + same_mbss = 1; + } + + RTW_PRINT_SEL(sel, "%c "MAC_FMT" %3d %4ld %5d %-32s %c%2u %3u %c%c " + NSTATE_VALUE_FMT_ACN + "\n" + , established ? 'E' : (blocked ? 'B' : (plink ? 'N' : (candidate ? 'C' : (same_mbss ? 'S' : ' ')))) + , MAC_ARG(network->network.MacAddress) + , network->network.Configuration.DSConfig + , network->network.Rssi + , age_ms < 99999 ? age_ms : 99999 + , network->network.mesh_id.Ssid + , GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mesh_conf_ie + 2) ? '+' : ' ' + , GET_MESH_CONF_ELE_NUM_OF_PEERINGS(mesh_conf_ie + 2) + , GET_MESH_CONF_ELE_FORWARDING(mesh_conf_ie + 2) + , GET_MESH_CONF_ELE_CTO_MGATE(mesh_conf_ie + 2) ? 'G' : ' ' + , GET_MESH_CONF_ELE_CTO_AS(mesh_conf_ie + 2) ? 'A' : ' ' + NSTATE_VALUE_ARG_ACN + ); + } + + rtw_vmfree(mesh_networks, mlme->max_bss_cnt * sizeof(struct wlan_network *)); +} + +void rtw_mesh_adjust_chbw(u8 req_ch, u8 *req_bw, u8 *req_offset) +{ + if (req_ch >= 5 && req_ch <= 9) { + /* prevent secondary channel offset mismatch */ + if (*req_bw > CHANNEL_WIDTH_20) { + *req_bw = CHANNEL_WIDTH_20; + *req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + } +} + +int rtw_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx) +{ + const u8 *frame_body = buf + sizeof(struct rtw_ieee80211_hdr_3addr); + u16 alg; + u16 seq; + u16 status; + int ret = 0; + + alg = RTW_GET_LE16(frame_body); + if (alg != 3) + goto exit; + + seq = RTW_GET_LE16(frame_body + 2); + status = RTW_GET_LE16(frame_body + 4); + + RTW_INFO("RTW_%s:AUTH alg:0x%04x, seq:0x%04x, status:0x%04x\n" + , (tx == _TRUE) ? "Tx" : "Rx", alg, seq, status); + + ret = 1; + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + if (tx && seq == 1) + rtw_mesh_plink_set_peer_conf_timeout(adapter, GetAddr1Ptr(buf)); +#endif + +exit: + return ret; +} + +#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS +#ifdef CONFIG_RTW_MESH_AEK +static int rtw_mpm_ampe_dec(_adapter *adapter, struct mesh_plink_ent *plink + , u8 *fhead, size_t flen, u8* fbody, u8 *mic_ie, u8 *ampe_buf) +{ + int ret = _FAIL, verify_ret; + const u8 *aad[] = {adapter_mac_addr(adapter), plink->addr, fbody}; + const size_t aad_len[] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody}; + u8 *iv_crypt; + size_t iv_crypt_len = flen - (mic_ie + 2 - fhead); + + iv_crypt = rtw_malloc(iv_crypt_len); + if (!iv_crypt) + goto exit; + + _rtw_memcpy(iv_crypt, mic_ie + 2, iv_crypt_len); + + verify_ret = aes_siv_decrypt(plink->aek, iv_crypt, iv_crypt_len + , 3, aad, aad_len, ampe_buf); + + rtw_mfree(iv_crypt, iv_crypt_len); + + if (verify_ret) { + RTW_WARN("verify error, aek_valid=%u\n", plink->aek_valid); + goto exit; + } else if (*ampe_buf != WLAN_EID_AMPE) { + RTW_WARN("plaintext is not AMPE IE\n"); + goto exit; + } else if (AES_BLOCK_SIZE + 2 + *(ampe_buf + 1) > iv_crypt_len) { + RTW_WARN("plaintext AMPE IE length is not valid\n"); + goto exit; + } + + ret = _SUCCESS; + +exit: + return ret; +} + +static int rtw_mpm_ampe_enc(_adapter *adapter, struct mesh_plink_ent *plink + , u8* fbody, u8 *mic_ie, u8 *ampe_buf, bool inverse) +{ + int ret = _FAIL, protect_ret; + const u8 *aad[3]; + const size_t aad_len[3] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody}; + u8 *ampe_ie; + size_t ampe_ie_len = *(ampe_buf + 1) + 2; /* including id & len */ + + if (inverse) { + aad[0] = plink->addr; + aad[1] = adapter_mac_addr(adapter); + } else { + aad[0] = adapter_mac_addr(adapter); + aad[1] = plink->addr; + } + aad[2] = fbody; + + ampe_ie = rtw_malloc(ampe_ie_len); + if (!ampe_ie) + goto exit; + + _rtw_memcpy(ampe_ie, ampe_buf, ampe_ie_len); + + protect_ret = aes_siv_encrypt(plink->aek, ampe_ie, ampe_ie_len + , 3, aad, aad_len, mic_ie + 2); + + rtw_mfree(ampe_ie, ampe_ie_len); + + if (protect_ret) { + RTW_WARN("protect error, aek_valid=%u\n", plink->aek_valid); + goto exit; + } + + ret = _SUCCESS; + +exit: + return ret; +} +#endif /* CONFIG_RTW_MESH_AEK */ + +static int rtw_mpm_tx_ies_sync_bss(_adapter *adapter, struct mesh_plink_ent *plink + , u8 *fhead, size_t flen, u8* fbody, u8 tlv_ies_offset, u8 *mpm_ie, u8 *mic_ie + , u8 **nbuf, size_t *nlen) +{ + int ret = _FAIL; + struct mlme_priv *mlme = &(adapter->mlmepriv); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); + WLAN_BSSID_EX *network = &(mlmeinfo->network); + uint left; + u8 *pos; + + uint mpm_ielen = *(mpm_ie + 1); + u8 *fpos; + u8 *new_buf = NULL; + size_t new_len = 0; + + u8 *new_fhead; + size_t new_flen; + u8 *new_fbody; + u8 *new_mic_ie; + +#ifdef CONFIG_RTW_MESH_AEK + u8 *ampe_buf = NULL; + size_t ampe_buf_len = 0; + + /* decode */ + if (mic_ie) { + ampe_buf_len = flen - (mic_ie + 2 + AES_BLOCK_SIZE - fhead); + ampe_buf = rtw_malloc(ampe_buf_len); + if (!ampe_buf) + goto exit; + + if (rtw_mpm_ampe_dec(adapter, plink, fhead, flen, fbody, mic_ie, ampe_buf) != _SUCCESS) + goto exit; + + if (*(ampe_buf + 1) >= 68) { + _rtw_memcpy(plink->sel_pcs, ampe_buf + 2, 4); + _rtw_memcpy(plink->l_nonce, ampe_buf + 6, 32); + _rtw_memcpy(plink->p_nonce, ampe_buf + 38, 32); + } + } +#endif + + /* count for new frame length */ + new_len = sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset; + left = BSS_EX_TLV_IES_LEN(network); + pos = BSS_EX_TLV_IES(network); + while (left >= 2) { + u8 id, elen; + + id = *pos++; + elen = *pos++; + left -= 2; + + if (elen > left) + break; + + switch (id) { + case WLAN_EID_SSID: + case WLAN_EID_DS_PARAMS: + case WLAN_EID_TIM: + break; + default: + new_len += 2 + elen; + } + + left -= elen; + pos += elen; + } + new_len += mpm_ielen + 2; + if (mic_ie) + new_len += AES_BLOCK_SIZE + 2 + ampe_buf_len; + + /* alloc new frame */ + new_buf = rtw_malloc(new_len); + if (!new_buf) { + rtw_warn_on(1); + goto exit; + } + + /* build new frame */ + _rtw_memcpy(new_buf, fhead, sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset); + new_fhead = new_buf; + new_flen = new_len; + new_fbody = new_fhead + sizeof(struct rtw_ieee80211_hdr_3addr); + + fpos = new_fbody + tlv_ies_offset; + left = BSS_EX_TLV_IES_LEN(network); + pos = BSS_EX_TLV_IES(network); + while (left >= 2) { + u8 id, elen; + + id = *pos++; + elen = *pos++; + left -= 2; + + if (elen > left) + break; + + switch (id) { + case WLAN_EID_SSID: + case WLAN_EID_DS_PARAMS: + case WLAN_EID_TIM: + break; + default: + fpos = rtw_set_ie(fpos, id, elen, pos, NULL); + if (id == WLAN_EID_MESH_CONFIG) + fpos = rtw_set_ie(fpos, WLAN_EID_MPM, mpm_ielen, mpm_ie + 2, NULL); + } + + left -= elen; + pos += elen; + } + if (mic_ie) { + new_mic_ie = fpos; + *fpos++ = WLAN_EID_MIC; + *fpos++ = AES_BLOCK_SIZE; + } + +#ifdef CONFIG_RTW_MESH_AEK + /* encode */ + if (mic_ie) { + int enc_ret = rtw_mpm_ampe_enc(adapter, plink, new_fbody, new_mic_ie, ampe_buf, 0); + if (enc_ret != _SUCCESS) + goto exit; + } +#endif + + *nlen = new_len; + *nbuf = new_buf; + + ret = _SUCCESS; + +exit: + if (ret != _SUCCESS && new_buf) + rtw_mfree(new_buf, new_len); + +#ifdef CONFIG_RTW_MESH_AEK + if (ampe_buf) + rtw_mfree(ampe_buf, ampe_buf_len); +#endif + + return ret; +} +#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */ + +struct mpm_frame_info { + u8 *aid; + u16 aid_v; + u8 *pid; + u16 pid_v; + u8 *llid; + u16 llid_v; + u8 *plid; + u16 plid_v; + u8 *reason; + u16 reason_v; + u8 *chosen_pmk; +}; + +/* +* pid:00000 llid:00000 chosen_pmk:0x00000000000000000000000000000000 +* aid:00000 pid:00000 llid:00000 plid:00000 chosen_pmk:0x00000000000000000000000000000000 +* pid:00000 llid:00000 plid:00000 reason:00000 chosen_pmk:0x00000000000000000000000000000000 +*/ +#define MPM_LOG_BUF_LEN 92 /* this length is limited for legal combination */ +static void rtw_mpm_info_msg(struct mpm_frame_info *mpm_info, u8 *mpm_log_buf) +{ + int cnt = 0; + + if (mpm_info->aid) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "aid:%u ", mpm_info->aid_v); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + if (mpm_info->pid) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "pid:%u ", mpm_info->pid_v); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + if (mpm_info->llid) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "llid:%u ", mpm_info->llid_v); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + if (mpm_info->plid) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "plid:%u ", mpm_info->plid_v); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + if (mpm_info->reason) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "reason:%u ", mpm_info->reason_v); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + if (mpm_info->chosen_pmk) { + cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "chosen_pmk:0x"KEY_FMT, KEY_ARG(mpm_info->chosen_pmk)); + if (cnt >= MPM_LOG_BUF_LEN - 1) + goto exit; + } + +exit: + return; +} + +static int rtw_mpm_check_frames(_adapter *adapter, u8 action, const u8 **buf, size_t *len, u8 tx) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *plink = NULL; + u8 *nbuf = NULL; + size_t nlen = 0; + u8 *fhead = (u8 *)*buf; + size_t flen = *len; + u8 *peer_addr = tx ? GetAddr1Ptr(fhead) : get_addr2_ptr(fhead); + u8 *frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr); + struct mpm_frame_info mpm_info; + u8 tlv_ies_offset; + u8 *mpm_ie = NULL; + uint mpm_ielen = 0; + u8 *mic_ie = NULL; + uint mic_ielen = 0; + int ret = 0; + u8 mpm_log_buf[MPM_LOG_BUF_LEN] = {0}; + + if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN) + tlv_ies_offset = 4; + else if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) + tlv_ies_offset = 6; + else if (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE) + tlv_ies_offset = 2; + else { + rtw_warn_on(1); + goto exit; + } + + plink = rtw_mesh_plink_get(adapter, peer_addr); + if (!plink && (tx == _TRUE || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)) { + /* warning message if no plink when: 1.TX all MPM or 2.RX CONF */ + RTW_WARN("RTW_%s:%s without plink of "MAC_FMT"\n" + , (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action), MAC_ARG(peer_addr)); + goto exit; + } + + _rtw_memset(&mpm_info, 0, sizeof(struct mpm_frame_info)); + + if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) { + mpm_info.aid = (u8 *)frame_body + 4; + mpm_info.aid_v = RTW_GET_LE16(mpm_info.aid); + } + + mpm_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset + , WLAN_EID_MPM, &mpm_ielen + , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset); + if (!mpm_ie || mpm_ielen < 2 + 2) + goto exit; + + mpm_info.pid = mpm_ie + 2; + mpm_info.pid_v = RTW_GET_LE16(mpm_info.pid); + mpm_info.llid = mpm_info.pid + 2; + mpm_info.llid_v = RTW_GET_LE16(mpm_info.llid); + + switch (action) { + case RTW_ACT_SELF_PROTECTED_MESH_OPEN: + /* pid:2, llid:2, (chosen_pmk:16) */ + if (mpm_info.pid_v == 0 && mpm_ielen == 4) + ; + else if (mpm_info.pid_v == 1 && mpm_ielen == 20) + mpm_info.chosen_pmk = mpm_info.llid + 2; + else + goto exit; + break; + case RTW_ACT_SELF_PROTECTED_MESH_CONF: + /* pid:2, llid:2, plid:2, (chosen_pmk:16) */ + mpm_info.plid = mpm_info.llid + 2; + mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid); + if (mpm_info.pid_v == 0 && mpm_ielen == 6) + ; + else if (mpm_info.pid_v == 1 && mpm_ielen == 22) + mpm_info.chosen_pmk = mpm_info.plid + 2; + else + goto exit; + break; + case RTW_ACT_SELF_PROTECTED_MESH_CLOSE: + /* pid:2, llid:2, (plid:2), reason:2, (chosen_pmk:16) */ + if (mpm_info.pid_v == 0 && mpm_ielen == 6) { + /* MPM, without plid */ + mpm_info.reason = mpm_info.llid + 2; + mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason); + } else if (mpm_info.pid_v == 0 && mpm_ielen == 8) { + /* MPM, with plid */ + mpm_info.plid = mpm_info.llid + 2; + mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid); + mpm_info.reason = mpm_info.plid + 2; + mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason); + } else if (mpm_info.pid_v == 1 && mpm_ielen == 22) { + /* AMPE, without plid */ + mpm_info.reason = mpm_info.llid + 2; + mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason); + mpm_info.chosen_pmk = mpm_info.reason + 2; + } else if (mpm_info.pid_v == 1 && mpm_ielen == 24) { + /* AMPE, with plid */ + mpm_info.plid = mpm_info.llid + 2; + mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid); + mpm_info.reason = mpm_info.plid + 2; + mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason); + mpm_info.chosen_pmk = mpm_info.reason + 2; + } else + goto exit; + break; + }; + + if (mpm_info.pid_v == 1) { + mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset + , WLAN_EID_MIC, &mic_ielen + , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset); + if (!mic_ie || mic_ielen != AES_BLOCK_SIZE) + goto exit; + } + +#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS + if ((action == RTW_ACT_SELF_PROTECTED_MESH_OPEN || action == RTW_ACT_SELF_PROTECTED_MESH_CONF) + && tx == _TRUE + ) { +#define DBG_RTW_MPM_TX_IES_SYNC_BSS 0 + + if (mpm_info.pid_v == 1 && (!plink || !MESH_PLINK_AEK_VALID(plink))) { + RTW_WARN("AEK not ready, IEs can't sync with BSS\n"); + goto bypass_sync_bss; + } + + if (DBG_RTW_MPM_TX_IES_SYNC_BSS) { + RTW_INFO(FUNC_ADPT_FMT" before:\n", FUNC_ADPT_ARG(adapter)); + dump_ies(RTW_DBGDUMP + , fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset + , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset); + } + + rtw_mpm_tx_ies_sync_bss(adapter, plink + , fhead, flen, frame_body, tlv_ies_offset, mpm_ie, mic_ie + , &nbuf, &nlen); + if (!nbuf) + goto exit; + + /* update pointer & len for new frame */ + fhead = nbuf; + flen = nlen; + frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr); + if (mpm_info.pid_v == 1) { + mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset + , WLAN_EID_MIC, &mic_ielen + , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset); + } + + if (DBG_RTW_MPM_TX_IES_SYNC_BSS) { + RTW_INFO(FUNC_ADPT_FMT" after:\n", FUNC_ADPT_ARG(adapter)); + dump_ies(RTW_DBGDUMP + , fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset + , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset); + } + } +bypass_sync_bss: +#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */ + + if (!plink) + goto mpm_log; + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN) { + if (tx) + rtw_mesh_plink_set_peer_conf_timeout(adapter, peer_addr); + + } else +#endif +#if CONFIG_RTW_MESH_ACNODE_PREVENT + if (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE) { + if (tx && mpm_info.reason && mpm_info.reason_v == WLAN_REASON_MESH_MAX_PEERS) { + if (rtw_mesh_scanned_is_acnode_confirmed(adapter, plink->scanned) + && rtw_mesh_acnode_prevent_allow_sacrifice(adapter) + ) { + struct sta_info *sac = rtw_mesh_acnode_prevent_pick_sacrifice(adapter); + + if (sac) { + struct sta_priv *stapriv = &adapter->stapriv; + _irqL irqL; + u8 sta_addr[ETH_ALEN]; + u8 updated = _FALSE; + + _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + if (!rtw_is_list_empty(&sac->asoc_list)) { + rtw_list_delete(&sac->asoc_list); + stapriv->asoc_list_cnt--; + STA_SET_MESH_PLINK(sac, NULL); + } + _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + RTW_INFO(FUNC_ADPT_FMT" sacrifice "MAC_FMT" for acnode\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sac->cmn.mac_addr)); + + _rtw_memcpy(sta_addr, sac->cmn.mac_addr, ETH_ALEN); + updated = ap_free_sta(adapter, sac, 0, 0, 1); + rtw_mesh_expire_peer(stapriv->padapter, sta_addr); + + associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL); + } + } + } + } else +#endif + if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) { + _irqL irqL; + u8 *ies = NULL; + u16 ies_len = 0; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + + plink = _rtw_mesh_plink_get(adapter, peer_addr); + if (!plink) + goto release_plink_ctl; + + if (tx == _FALSE) { + ies = plink->rx_conf_ies; + ies_len = plink->rx_conf_ies_len; + plink->rx_conf_ies = NULL; + plink->rx_conf_ies_len = 0; + + plink->llid = mpm_info.plid_v; + plink->plid = mpm_info.llid_v; + plink->peer_aid = mpm_info.aid_v; + if (mpm_info.pid_v == 1) + _rtw_memcpy(plink->chosen_pmk, mpm_info.chosen_pmk, 16); + } + #ifdef CONFIG_RTW_MESH_DRIVER_AID + else { + ies = plink->tx_conf_ies; + ies_len = plink->tx_conf_ies_len; + plink->tx_conf_ies = NULL; + plink->tx_conf_ies_len = 0; + } + #endif + + if (ies && ies_len) + rtw_mfree(ies, ies_len); + + #ifndef CONFIG_RTW_MESH_DRIVER_AID + if (tx == _TRUE) + goto release_plink_ctl; /* no need to copy tx conf ies */ + #endif + + /* copy mesh confirm IEs */ + if (mpm_info.pid_v == 1) /* not include MIC & encrypted AMPE */ + ies_len = (mic_ie - fhead) - sizeof(struct rtw_ieee80211_hdr_3addr) - 2; + else + ies_len = flen - sizeof(struct rtw_ieee80211_hdr_3addr) - 2; + + ies = rtw_zmalloc(ies_len); + if (ies) { + _rtw_memcpy(ies, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + 2, ies_len); + if (tx == _FALSE) { + plink->rx_conf_ies = ies; + plink->rx_conf_ies_len = ies_len; + } + #ifdef CONFIG_RTW_MESH_DRIVER_AID + else { + plink->tx_conf_ies = ies; + plink->tx_conf_ies_len = ies_len; + } + #endif + } + +release_plink_ctl: + _exit_critical_bh(&(plink_ctl->lock), &irqL); + } + +mpm_log: + rtw_mpm_info_msg(&mpm_info, mpm_log_buf); + RTW_INFO("RTW_%s:%s %s\n" + , (tx == _TRUE) ? "Tx" : "Rx" + , action_self_protected_str(action) + , mpm_log_buf + ); + + ret = 1; + +exit: + if (nbuf) { + if (ret == 1) { + *buf = nbuf; + *len = nlen; + } else + rtw_mfree(nbuf, nlen); + } + + return ret; +} + +static int rtw_mesh_check_frames(_adapter *adapter, const u8 **buf, size_t *len, u8 tx) +{ + int is_mesh_frame = -1; + const u8 *frame_body; + u8 category, action; + + frame_body = *buf + sizeof(struct rtw_ieee80211_hdr_3addr); + category = frame_body[0]; + + if (category == RTW_WLAN_CATEGORY_SELF_PROTECTED) { + action = frame_body[1]; + switch (action) { + case RTW_ACT_SELF_PROTECTED_MESH_OPEN: + case RTW_ACT_SELF_PROTECTED_MESH_CONF: + case RTW_ACT_SELF_PROTECTED_MESH_CLOSE: + rtw_mpm_check_frames(adapter, action, buf, len, tx); + is_mesh_frame = action; + break; + case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM: + case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK: + RTW_INFO("RTW_%s:%s\n", (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action)); + is_mesh_frame = action; + break; + default: + break; + }; + } + +exit: + return is_mesh_frame; +} + +int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len) +{ + return rtw_mesh_check_frames(adapter, buf, len, _TRUE); +} + +int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len) +{ + return rtw_mesh_check_frames(adapter, &buf, &len, _FALSE); +} + +int rtw_mesh_on_auth(_adapter *adapter, union recv_frame *rframe) +{ + u8 *whdr = rframe->u.hdr.rx_data; + +#if CONFIG_RTW_MACADDR_ACL + if (rtw_access_ctrl(adapter, get_addr2_ptr(whdr)) == _FALSE) + return _SUCCESS; +#endif + + if (!rtw_mesh_plink_get(adapter, get_addr2_ptr(whdr))) { + #if CONFIG_RTW_MESH_ACNODE_PREVENT + rtw_mesh_acnode_set_notify_etime(adapter, whdr); + #endif + + if (adapter_to_rfctl(adapter)->offch_state == OFFCHS_NONE) + issue_probereq(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, get_addr2_ptr(whdr)); + + /* only peer being added (checked by notify conditions) is allowed */ + return _SUCCESS; + } + + rtw_cfg80211_rx_mframe(adapter, rframe, NULL); + return _SUCCESS; +} + +unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe) +{ + unsigned int ret = _FAIL; + struct sta_info *sta = NULL; + u8 *pframe = rframe->u.hdr.rx_data; + uint frame_len = rframe->u.hdr.len; + u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 category; + u8 action; + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(adapter), GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_SELF_PROTECTED) + goto exit; + + action = frame_body[1]; + switch (action) { + case RTW_ACT_SELF_PROTECTED_MESH_OPEN: + case RTW_ACT_SELF_PROTECTED_MESH_CONF: + case RTW_ACT_SELF_PROTECTED_MESH_CLOSE: + case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM: + case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK: + if (!(MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter))) + goto exit; +#ifdef CONFIG_IOCTL_CFG80211 + #if CONFIG_RTW_MACADDR_ACL + if (rtw_access_ctrl(adapter, get_addr2_ptr(pframe)) == _FALSE) + goto exit; + #endif + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + if (rtw_mesh_cto_mgate_required(adapter) + /* only peer being added (checked by notify conditions) is allowed */ + && !rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe))) + goto exit; + #endif + rtw_cfg80211_rx_action(adapter, rframe, NULL); + ret = _SUCCESS; +#endif /* CONFIG_IOCTL_CFG80211 */ + break; + default: + break; + } + +exit: + return ret; +} + +const u8 ae_to_mesh_ctrl_len[] = { + 6, + 12, /* MESH_FLAGS_AE_A4 */ + 18, /* MESH_FLAGS_AE_A5_A6 */ + 0, +}; + +unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe) +{ + unsigned int ret = _FAIL; + struct sta_info *sta = NULL; + struct sta_priv *stapriv = &adapter->stapriv; + u8 *pframe = rframe->u.hdr.rx_data; + uint frame_len = rframe->u.hdr.len; + u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 category; + u8 action; + + if (!MLME_IS_MESH(adapter)) + goto exit; + + /* check stainfo exist? */ + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_MESH) + goto exit; + + action = frame_body[1]; + switch (action) { + case RTW_ACT_MESH_HWMP_PATH_SELECTION: + rtw_mesh_rx_path_sel_frame(adapter, rframe); + ret = _SUCCESS; + break; + default: + break; + } + +exit: + return ret; +} + +bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + u8 num_of_peerings = stapriv->asoc_list_cnt; + bool accept_peerings = stapriv->asoc_list_cnt < mcfg->max_peer_links; + u8 *ie; + int ie_len; + bool updated = 0; + +#if CONFIG_RTW_MESH_ACNODE_PREVENT + accept_peerings |= plink_ctl->acnode_rsvd; +#endif + + ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, BSS_EX_TLV_IES_LEN(bss)); + if (!ie || ie_len != 7) { + rtw_warn_on(1); + goto exit; + } + + if (GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2) != num_of_peerings) { + SET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2, num_of_peerings); + updated = 1; + } + + if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2) != accept_peerings) { + SET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2, accept_peerings); + updated = 1; + } + +exit: + return updated; +} + +bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + u8 cto_mgate = (minfo->num_gates || mcfg->dot11MeshGateAnnouncementProtocol); + u8 cto_as = 0; + u8 *ie; + int ie_len; + bool updated = 0; + + ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, + BSS_EX_TLV_IES_LEN(bss)); + if (!ie || ie_len != 7) { + rtw_warn_on(1); + goto exit; + } + + if (GET_MESH_CONF_ELE_CTO_MGATE(ie + 2) != cto_mgate) { + SET_MESH_CONF_ELE_CTO_MGATE(ie + 2, cto_mgate); + updated = 1; + } + + if (GET_MESH_CONF_ELE_CTO_AS(ie + 2) != cto_as) { + SET_MESH_CONF_ELE_CTO_AS(ie + 2, cto_as); + updated = 1; + } + +exit: + return updated; +} + +bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + u8 forward = mcfg->dot11MeshForwarding; + u8 *ie; + int ie_len; + bool updated = 0; + + ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, + BSS_EX_TLV_IES_LEN(bss)); + if (!ie || ie_len != 7) { + rtw_warn_on(1); + goto exit; + } + + if (GET_MESH_CONF_ELE_FORWARDING(ie + 2) != forward) { + SET_MESH_CONF_ELE_FORWARDING(ie + 2, forward); + updated = 1; + } + +exit: + return updated; +} + +struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + int i; + + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + if (plink_ctl->ent[i].valid == _TRUE + && _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE + ) { + ent = &plink_ctl->ent[i]; + break; + } + } + +exit: + return ent; +} + +struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + ent = _rtw_mesh_plink_get(adapter, hwaddr); + _exit_critical_bh(&(plink_ctl->lock), &irqL); + +exit: + return ent; +} + +struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + int i, j = 0; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + if (plink_ctl->ent[i].valid == _TRUE + && plink_ctl->ent[i].plink_state != RTW_MESH_PLINK_ESTAB + ) { + if (j == idx) { + ent = &plink_ctl->ent[i]; + break; + } + j++; + } + } + _exit_critical_bh(&(plink_ctl->lock), &irqL); + + return ent; +} + +int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + u8 exist = _FALSE; + int i; + + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + if (plink_ctl->ent[i].valid == _TRUE + && _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE + ) { + ent = &plink_ctl->ent[i]; + exist = _TRUE; + break; + } + + if (ent == NULL && plink_ctl->ent[i].valid == _FALSE) + ent = &plink_ctl->ent[i]; + } + + if (exist == _FALSE && ent) { + _rtw_memcpy(ent->addr, hwaddr, ETH_ALEN); + ent->valid = _TRUE; + #ifdef CONFIG_RTW_MESH_AEK + ent->aek_valid = 0; + #endif + ent->llid = 0; + ent->plid = 0; + _rtw_memset(ent->chosen_pmk, 0, 16); + #ifdef CONFIG_RTW_MESH_AEK + _rtw_memset(ent->sel_pcs, 0, 4); + _rtw_memset(ent->l_nonce, 0, 32); + _rtw_memset(ent->p_nonce, 0, 32); + #endif + ent->plink_state = RTW_MESH_PLINK_LISTEN; + #ifndef CONFIG_RTW_MESH_DRIVER_AID + ent->aid = 0; + #endif + ent->peer_aid = 0; + SET_PEER_CONF_DISABLED(ent); + SET_CTO_MGATE_CONF_DISABLED(ent); + plink_ctl->num++; + } + +exit: + return exist == _TRUE ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL); +} + +int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + _irqL irqL; + int ret; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + ret = _rtw_mesh_plink_add(adapter, hwaddr); + _exit_critical_bh(&(plink_ctl->lock), &irqL); + + return ret; +} + +int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + ent = _rtw_mesh_plink_get(adapter, hwaddr); + if (ent) + ent->plink_state = state; + _exit_critical_bh(&(plink_ctl->lock), &irqL); + +exit: + return ent ? _SUCCESS : _FAIL; +} + +#ifdef CONFIG_RTW_MESH_AEK +int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + ent = _rtw_mesh_plink_get(adapter, hwaddr); + if (ent) { + _rtw_memcpy(ent->aek, aek, 32); + ent->aek_valid = 1; + } + _exit_critical_bh(&(plink_ctl->lock), &irqL); + +exit: + return ent ? _SUCCESS : _FAIL; +} +#endif + +#if CONFIG_RTW_MESH_PEER_BLACKLIST +int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + ent = _rtw_mesh_plink_get(adapter, hwaddr); + if (ent) { + if (IS_PEER_CONF_DISABLED(ent)) + SET_PEER_CONF_END_TIME(ent, mcfg->peer_sel_policy.peer_conf_timeout_ms); + } + _exit_critical_bh(&(plink_ctl->lock), &irqL); + +exit: + return ent ? _SUCCESS : _FAIL; +} +#endif + +void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + + ent->valid = _FALSE; + #ifdef CONFIG_RTW_MESH_DRIVER_AID + if (ent->tx_conf_ies && ent->tx_conf_ies_len) + rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len); + ent->tx_conf_ies = NULL; + ent->tx_conf_ies_len = 0; + #endif + if (ent->rx_conf_ies && ent->rx_conf_ies_len) + rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len); + ent->rx_conf_ies = NULL; + ent->rx_conf_ies_len = 0; + if (ent->scanned) + ent->scanned = NULL; + plink_ctl->num--; +} + +int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent = NULL; + u8 exist = _FALSE; + int i; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + if (plink_ctl->ent[i].valid == _TRUE + && _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE + ) { + ent = &plink_ctl->ent[i]; + exist = _TRUE; + break; + } + } + + if (exist == _TRUE) + _rtw_mesh_plink_del_ent(adapter, ent); + + _exit_critical_bh(&(plink_ctl->lock), &irqL); + +exit: + return exist == _TRUE ? _SUCCESS : RTW_ALREADY; +} + +void rtw_mesh_plink_ctl_init(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + int i; + + _rtw_spinlock_init(&plink_ctl->lock); + plink_ctl->num = 0; + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) + plink_ctl->ent[i].valid = _FALSE; + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + _rtw_init_queue(&plink_ctl->peer_blacklist); +#endif +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + _rtw_init_queue(&plink_ctl->cto_mgate_blacklist); +#endif +} + +void rtw_mesh_plink_ctl_deinit(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent; + int i; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + ent = &plink_ctl->ent[i]; + #ifdef CONFIG_RTW_MESH_DRIVER_AID + if (ent->tx_conf_ies && ent->tx_conf_ies_len) + rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len); + #endif + if (ent->rx_conf_ies && ent->rx_conf_ies_len) + rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len); + } + _exit_critical_bh(&(plink_ctl->lock), &irqL); + + _rtw_spinlock_free(&plink_ctl->lock); + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + rtw_mesh_peer_blacklist_flush(adapter); + _rtw_deinit_queue(&plink_ctl->peer_blacklist); +#endif +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + rtw_mesh_cto_mgate_blacklist_flush(adapter); + _rtw_deinit_queue(&plink_ctl->cto_mgate_blacklist); +#endif +} + +void dump_mesh_plink_ctl(void *sel, _adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *ent; + int i; + + RTW_PRINT_SEL(sel, "num:%u\n", plink_ctl->num); + #if CONFIG_RTW_MESH_ACNODE_PREVENT + RTW_PRINT_SEL(sel, "acnode_rsvd:%u\n", plink_ctl->acnode_rsvd); + #endif + + for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) { + ent = &plink_ctl->ent[i]; + if (!ent->valid) + continue; + + RTW_PRINT_SEL(sel, "\n"); + RTW_PRINT_SEL(sel, "peer:"MAC_FMT"\n", MAC_ARG(ent->addr)); + RTW_PRINT_SEL(sel, "plink_state:%s\n", rtw_mesh_plink_str(ent->plink_state)); + + #ifdef CONFIG_RTW_MESH_AEK + if (ent->aek_valid) + RTW_PRINT_SEL(sel, "aek:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->aek), KEY_ARG(ent->aek + 16)); + #endif + + RTW_PRINT_SEL(sel, "llid:%u, plid:%u\n", ent->llid, ent->plid); + #ifndef CONFIG_RTW_MESH_DRIVER_AID + RTW_PRINT_SEL(sel, "aid:%u\n", ent->aid); + #endif + RTW_PRINT_SEL(sel, "peer_aid:%u\n", ent->peer_aid); + + RTW_PRINT_SEL(sel, "chosen_pmk:"KEY_FMT"\n", KEY_ARG(ent->chosen_pmk)); + + #ifdef CONFIG_RTW_MESH_AEK + RTW_PRINT_SEL(sel, "sel_pcs:%02x%02x%02x%02x\n" + , ent->sel_pcs[0], ent->sel_pcs[1], ent->sel_pcs[2], ent->sel_pcs[3]); + RTW_PRINT_SEL(sel, "l_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->l_nonce), KEY_ARG(ent->l_nonce + 16)); + RTW_PRINT_SEL(sel, "p_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->p_nonce), KEY_ARG(ent->p_nonce + 16)); + #endif + + #ifdef CONFIG_RTW_MESH_DRIVER_AID + RTW_PRINT_SEL(sel, "tx_conf_ies:%p, len:%u\n", ent->tx_conf_ies, ent->tx_conf_ies_len); + #endif + RTW_PRINT_SEL(sel, "rx_conf_ies:%p, len:%u\n", ent->rx_conf_ies, ent->rx_conf_ies_len); + RTW_PRINT_SEL(sel, "scanned:%p\n", ent->scanned); + + #if CONFIG_RTW_MESH_PEER_BLACKLIST + if (!IS_PEER_CONF_DISABLED(ent)) { + if (!IS_PEER_CONF_TIMEOUT(ent)) + RTW_PRINT_SEL(sel, "peer_conf:%d\n", rtw_systime_to_ms(ent->peer_conf_end_time - rtw_get_current_time())); + else + RTW_PRINT_SEL(sel, "peer_conf:TIMEOUT\n"); + } + #endif + + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + if (!IS_CTO_MGATE_CONF_DISABLED(ent)) { + if (!IS_CTO_MGATE_CONF_TIMEOUT(ent)) + RTW_PRINT_SEL(sel, "cto_mgate_conf:%d\n", rtw_systime_to_ms(ent->cto_mgate_conf_end_time - rtw_get_current_time())); + else + RTW_PRINT_SEL(sel, "cto_mgate_conf:TIMEOUT\n"); + } + #endif + } +} + +/* this function is called with plink_ctl being locked */ +int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta) +{ +#ifndef DBG_RTW_MESH_PEER_ESTABLISH +#define DBG_RTW_MESH_PEER_ESTABLISH 0 +#endif + + struct sta_priv *stapriv = &adapter->stapriv; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + u8 *tlv_ies; + u16 tlv_ieslen; + struct rtw_ieee802_11_elems elems; + _irqL irqL; + int i; + int ret = _FAIL; + + if (!plink->rx_conf_ies || !plink->rx_conf_ies_len) { + RTW_INFO(FUNC_ADPT_FMT" no rx confirm from sta "MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + goto exit; + } + + if (plink->rx_conf_ies_len < 4) { + RTW_INFO(FUNC_ADPT_FMT" confirm from sta "MAC_FMT" too short\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + goto exit; + } + +#ifdef CONFIG_RTW_MESH_DRIVER_AID + if (!plink->tx_conf_ies || !plink->tx_conf_ies_len) { + RTW_INFO(FUNC_ADPT_FMT" no tx confirm to sta "MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + goto exit; + } + + if (plink->tx_conf_ies_len < 4) { + RTW_INFO(FUNC_ADPT_FMT" confirm to sta "MAC_FMT" too short\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + goto exit; + } +#endif + + tlv_ies = plink->rx_conf_ies + 4; + tlv_ieslen = plink->rx_conf_ies_len - 4; + + if (DBG_RTW_MESH_PEER_ESTABLISH) + dump_ies(RTW_DBGDUMP, tlv_ies, tlv_ieslen); + + if (rtw_ieee802_11_parse_elems(tlv_ies, tlv_ieslen, &elems, 1) == ParseFailed) { + RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" sent invalid confirm\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + goto exit; + } + + SET_PEER_CONF_DISABLED(plink); + if (rtw_bss_is_cto_mgate(&plink->scanned->network) + && !rtw_bss_is_forwarding(&plink->scanned->network)) + SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms); + else + SET_CTO_MGATE_CONF_DISABLED(plink); + + sta->state &= (~WIFI_FW_AUTH_SUCCESS); + sta->state |= WIFI_FW_ASSOC_STATE; + + rtw_ap_parse_sta_capability(adapter, sta, plink->rx_conf_ies); + + if (rtw_ap_parse_sta_supported_rates(adapter, sta, tlv_ies, tlv_ieslen) != _STATS_SUCCESSFUL_) + goto exit; + + if (rtw_ap_parse_sta_security_ie(adapter, sta, &elems) != _STATS_SUCCESSFUL_) + goto exit; + + rtw_ap_parse_sta_wmm_ie(adapter, sta, tlv_ies, tlv_ieslen); + + rtw_ap_parse_sta_ht_ie(adapter, sta, &elems); + rtw_ap_parse_sta_vht_ie(adapter, sta, &elems); + + /* AID */ +#ifdef CONFIG_RTW_MESH_DRIVER_AID + sta->cmn.aid = RTW_GET_LE16(plink->tx_conf_ies + 2); +#else + sta->cmn.aid = plink->aid; +#endif + stapriv->sta_aid[sta->cmn.aid - 1] = sta; + RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" aid:%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr), sta->cmn.aid); + + sta->state &= (~WIFI_FW_ASSOC_STATE); + sta->state |= WIFI_FW_ASSOC_SUCCESS; + + sta->local_mps = RTW_MESH_PS_ACTIVE; + + rtw_ewma_err_rate_init(&sta->metrics.err_rate); + rtw_ewma_err_rate_add(&sta->metrics.err_rate, 1); + /* init data_rate to 1M */ + sta->metrics.data_rate = 10; + + _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&sta->asoc_list)) { + STA_SET_MESH_PLINK(sta, plink); + /* TBD: up layer timeout mechanism */ + /* sta->expire_to = mcfg->plink_timeout / 2; */ + rtw_list_insert_tail(&sta->asoc_list, &stapriv->asoc_list); + stapriv->asoc_list_cnt++; + } + _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + + bss_cap_update_on_sta_join(adapter, sta); + sta_info_update(adapter, sta); + report_add_sta_event(adapter, sta->cmn.mac_addr); + + ret = _SUCCESS; + +exit: + return ret; +} + +void rtw_mesh_expire_peer_notify(_adapter *adapter, const u8 *peer_addr) +{ + u8 null_ssid[2] = {0, 0}; + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev + , peer_addr + , null_ssid + , 2 + , GFP_ATOMIC + ); +#endif + +exit: + return; +} + +static u8 *rtw_mesh_construct_peer_mesh_close(_adapter *adapter, struct mesh_plink_ent *plink, u16 reason, u32 *len) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + u8 *frame = NULL, *pos; + u32 flen; + struct rtw_ieee80211_hdr *whdr; + + if (minfo->mesh_auth_id && !MESH_PLINK_AEK_VALID(plink)) + goto exit; + + flen = sizeof(struct rtw_ieee80211_hdr_3addr) + + 2 /* category, action */ + + 2 + minfo->mesh_id_len /* mesh id */ + + 2 + 8 + (minfo->mesh_auth_id ? 16 : 0) /* mpm */ + + (minfo->mesh_auth_id ? 2 + AES_BLOCK_SIZE : 0) /* mic */ + + (minfo->mesh_auth_id ? 70 : 0) /* ampe */ + ; + + pos = frame = rtw_zmalloc(flen); + if (!frame) + goto exit; + + whdr = (struct rtw_ieee80211_hdr *)frame; + _rtw_memcpy(whdr->addr1, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memcpy(whdr->addr2, plink->addr, ETH_ALEN); + _rtw_memcpy(whdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); + + set_frame_sub_type(frame, WIFI_ACTION); + + pos += sizeof(struct rtw_ieee80211_hdr_3addr); + *(pos++) = RTW_WLAN_CATEGORY_SELF_PROTECTED; + *(pos++) = RTW_ACT_SELF_PROTECTED_MESH_CLOSE; + + pos = rtw_set_ie_mesh_id(pos, NULL, minfo->mesh_id, minfo->mesh_id_len); + + pos = rtw_set_ie_mpm(pos, NULL + , minfo->mesh_auth_id ? 1 : 0 + , plink->plid + , &plink->llid + , &reason + , minfo->mesh_auth_id ? plink->chosen_pmk : NULL); + +#ifdef CONFIG_RTW_MESH_AEK + if (minfo->mesh_auth_id) { + u8 ampe_buf[70]; + int enc_ret; + + *pos = WLAN_EID_MIC; + *(pos + 1) = AES_BLOCK_SIZE; + + ampe_buf[0] = WLAN_EID_AMPE; + ampe_buf[1] = 68; + _rtw_memcpy(ampe_buf + 2, plink->sel_pcs, 4); + _rtw_memcpy(ampe_buf + 6, plink->p_nonce, 32); + _rtw_memcpy(ampe_buf + 38, plink->l_nonce, 32); + + enc_ret = rtw_mpm_ampe_enc(adapter, plink + , frame + sizeof(struct rtw_ieee80211_hdr_3addr) + , pos, ampe_buf, 1); + if (enc_ret != _SUCCESS) { + rtw_mfree(frame, flen); + frame = NULL; + goto exit; + } + } +#endif + + *len = flen; + +exit: + return frame; +} + +void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink) +{ +#if defined(CONFIG_RTW_MESH_STA_DEL_DISASOC) + _rtw_mesh_plink_del_ent(adapter, plink); + rtw_cfg80211_indicate_sta_disassoc(adapter, plink->addr, 0); +#else + u8 *frame = NULL; + u32 flen; + + if (plink->plink_state == RTW_MESH_PLINK_ESTAB) + frame = rtw_mesh_construct_peer_mesh_close(adapter, plink, WLAN_REASON_MESH_CLOSE, &flen); + + if (frame) { + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct wireless_dev *wdev = adapter->rtw_wdev; + s32 freq = rtw_ch2freq(mlmeext->cur_channel); + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, flen, GFP_ATOMIC); + #else + cfg80211_rx_action(adapter->pnetdev, freq, frame, flen, GFP_ATOMIC); + #endif + + rtw_mfree(frame, flen); + } else { + rtw_mesh_expire_peer_notify(adapter, plink->addr); + RTW_INFO(FUNC_ADPT_FMT" set "MAC_FMT" plink unknown\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(plink->addr)); + plink->plink_state = RTW_MESH_PLINK_UNKNOWN; + } +#endif +} + +void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *plink; + _irqL irqL; + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + + plink = _rtw_mesh_plink_get(adapter, peer_addr); + if (!plink) + goto exit; + + _rtw_mesh_expire_peer_ent(adapter, plink); + +exit: + _exit_critical_bh(&(plink_ctl->lock), &irqL); +} + +u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps) +{ + _irqL irqL; + _list *head, *list; + struct sta_info *sta; + struct sta_priv *stapriv = &adapter->stapriv; + u8 sta_alive_num = 0, i; + char sta_alive_list[NUM_STA]; + u8 annc_cnt = 0; + + if (rtw_linked_check(adapter) == _FALSE) + goto exit; + + _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + + head = &stapriv->asoc_list; + list = get_next(head); + while ((rtw_end_of_queue_search(head, list)) == _FALSE) { + int stainfo_offset; + + sta = LIST_CONTAINOR(list, struct sta_info, asoc_list); + list = get_next(list); + + stainfo_offset = rtw_stainfo_offset(stapriv, sta); + if (stainfo_offset_valid(stainfo_offset)) + sta_alive_list[sta_alive_num++] = stainfo_offset; + } + _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + + for (i = 0; i < sta_alive_num; i++) { + sta = rtw_get_stainfo_by_offset(stapriv, sta_alive_list[i]); + if (!sta) + continue; + + issue_qos_nulldata(adapter, sta->cmn.mac_addr, 7, ps, 3, 500); + annc_cnt++; + } + +exit: + return annc_cnt; +} + +static void mpath_tx_tasklet_hdl(void *priv) +{ + _adapter *adapter = (_adapter *)priv; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct xmit_frame *xframe; + _list *list, *head; + _list tmp; + u32 tmp_len; + s32 res; + + _rtw_init_listhead(&tmp); + + while (1) { + tmp_len = 0; + enter_critical_bh(&minfo->mpath_tx_queue.lock); + if (minfo->mpath_tx_queue_len) { + rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp); + tmp_len = minfo->mpath_tx_queue_len; + minfo->mpath_tx_queue_len = 0; + } + exit_critical_bh(&minfo->mpath_tx_queue.lock); + + if (!tmp_len) + break; + + head = &tmp; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + xframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&xframe->list); + res = rtw_xmit_posthandle(adapter, xframe, xframe->pkt); + if (res < 0) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__); + #endif + adapter->xmitpriv.tx_drop++; + } + } + } +} + +static void rtw_mpath_tx_queue_flush(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct xmit_frame *xframe; + _list *list, *head; + _list tmp; + + _rtw_init_listhead(&tmp); + + enter_critical_bh(&minfo->mpath_tx_queue.lock); + rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp); + minfo->mpath_tx_queue_len = 0; + exit_critical_bh(&minfo->mpath_tx_queue.lock); + + head = &tmp; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + xframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&xframe->list); + rtw_free_xmitframe(&adapter->xmitpriv, xframe); + } +} + +#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */ +#if defined(CONFIG_SLUB) +#include +#elif defined(CONFIG_SLAB) +#include +#endif +typedef struct kmem_cache rtw_mcache; +#endif + +rtw_mcache *rtw_mcache_create(const char *name, size_t size) +{ +#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */ + return kmem_cache_create(name, size, 0, 0, NULL); +#else + #error "TBD\n"; +#endif +} + +void rtw_mcache_destroy(rtw_mcache *s) +{ +#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */ + kmem_cache_destroy(s); +#else + #error "TBD\n"; +#endif +} + +void *_rtw_mcache_alloc(rtw_mcache *cachep) +{ +#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */ + return kmem_cache_alloc(cachep, GFP_ATOMIC); +#else + #error "TBD\n"; +#endif +} + +void _rtw_mcache_free(rtw_mcache *cachep, void *objp) +{ +#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */ + kmem_cache_free(cachep, objp); +#else + #error "TBD\n"; +#endif +} + +#ifdef DBG_MEM_ALLOC +inline void *dbg_rtw_mcache_alloc(rtw_mcache *cachep, const enum mstat_f flags, const char *func, const int line) +{ + void *p; + u32 sz = cachep->size; + + if (match_mstat_sniff_rules(flags, sz)) + RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz); + + p = _rtw_mcache_alloc(cachep); + + rtw_mstat_update( + flags + , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , sz + ); + + return p; +} + +inline void dbg_rtw_mcache_free(rtw_mcache *cachep, void *pbuf, const enum mstat_f flags, const char *func, const int line) +{ + u32 sz = cachep->size; + + if (match_mstat_sniff_rules(flags, sz)) + RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz); + + _rtw_mcache_free(cachep, pbuf); + + rtw_mstat_update( + flags + , MSTAT_FREE + , sz + ); +} + +#define rtw_mcache_alloc(cachep) dbg_rtw_mcache_alloc(cachep, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_mcache_free(cachep, objp) dbg_rtw_mcache_free(cachep, objp, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#else +#define rtw_mcache_alloc(cachep) _rtw_mcache_alloc(cachep) +#define rtw_mcache_free(cachep, objp) _rtw_mcache_free(cachep, objp) +#endif /* DBG_MEM_ALLOC */ + +/* Mesh Received Cache */ +#define RTW_MRC_BUCKETS 256 /* must be a power of 2 */ +#define RTW_MRC_QUEUE_MAX_LEN 4 +#define RTW_MRC_TIMEOUT_MS (3 * 1000) + +/** + * struct rtw_mrc_entry - entry in the Mesh Received Cache + * + * @seqnum: mesh sequence number of the frame + * @exp_time: expiration time of the entry + * @msa: mesh source address of the frame + * @list: hashtable list pointer + * + * The Mesh Received Cache keeps track of the latest received frames that + * have been received by a mesh interface and discards received frames + * that are found in the cache. + */ +struct rtw_mrc_entry { + rtw_hlist_node list; + systime exp_time; + u32 seqnum; + u8 msa[ETH_ALEN]; +}; + +struct rtw_mrc { + rtw_hlist_head bucket[RTW_MRC_BUCKETS]; + u32 idx_mask; + rtw_mcache *cache; +}; + +static int rtw_mrc_init(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + char cache_name[IFNAMSIZ + 8 + 1]; + int i; + + minfo->mrc = rtw_malloc(sizeof(struct rtw_mrc)); + if (!minfo->mrc) + return -ENOMEM; + minfo->mrc->idx_mask = RTW_MRC_BUCKETS - 1; + for (i = 0; i < RTW_MRC_BUCKETS; i++) + rtw_hlist_head_init(&minfo->mrc->bucket[i]); + + sprintf(cache_name, "rtw_mrc_%s", ADPT_ARG(adapter)); + minfo->mrc->cache = rtw_mcache_create(cache_name, sizeof(struct rtw_mrc_entry)); + + return 0; +} + +static void rtw_mrc_free(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mrc *mrc = minfo->mrc; + struct rtw_mrc_entry *p; + rtw_hlist_node *np, *n; + int i; + + if (!mrc) + return; + + for (i = 0; i < RTW_MRC_BUCKETS; i++) { + rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[i], list) { + rtw_hlist_del(&p->list); + rtw_mcache_free(mrc->cache, p); + } + } + + rtw_mcache_destroy(mrc->cache); + + rtw_mfree(mrc, sizeof(struct rtw_mrc)); + minfo->mrc = NULL; +} + +/** + * rtw_mrc_check - Check frame in mesh received cache and add if absent. + * + * @adapter: interface + * @msa: mesh source address + * @seq: mesh seq number + * + * Returns: 0 if the frame is not in the cache, nonzero otherwise. + * + * Checks using the mesh source address and the mesh sequence number if we have + * received this frame lately. If the frame is not in the cache, it is added to + * it. + */ +static int rtw_mrc_check(_adapter *adapter, const u8 *msa, u32 seq) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mrc *mrc = minfo->mrc; + int entries = 0; + u8 idx; + struct rtw_mrc_entry *p; + rtw_hlist_node *np, *n; + u8 timeout; + + if (!mrc) + return -1; + + idx = seq & mrc->idx_mask; + rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[idx], list) { + ++entries; + timeout = rtw_time_after(rtw_get_current_time(), p->exp_time); + if (timeout || entries == RTW_MRC_QUEUE_MAX_LEN) { + if (!timeout) + minfo->mshstats.mrc_del_qlen++; + + rtw_hlist_del(&p->list); + rtw_mcache_free(mrc->cache, p); + --entries; + } else if ((seq == p->seqnum) && _rtw_memcmp(msa, p->msa, ETH_ALEN) == _TRUE) + return -1; + } + + p = rtw_mcache_alloc(mrc->cache); + if (!p) + return 0; + + p->seqnum = seq; + p->exp_time = rtw_get_current_time() + rtw_ms_to_systime(RTW_MRC_TIMEOUT_MS); + _rtw_memcpy(p->msa, msa, ETH_ALEN); + rtw_hlist_add_head(&p->list, &mrc->bucket[idx]); + return 0; +} + +static int rtw_mesh_decache(_adapter *adapter, const u8 *msa, u32 seq) +{ + return rtw_mrc_check(adapter, msa, seq); +} + +#ifndef RTW_MESH_SCAN_RESULT_EXP_MS +#define RTW_MESH_SCAN_RESULT_EXP_MS (10 * 1000) +#endif + +#ifndef RTW_MESH_ACNODE_PREVENT +#define RTW_MESH_ACNODE_PREVENT 0 +#endif +#ifndef RTW_MESH_ACNODE_CONF_TIMEOUT_MS +#define RTW_MESH_ACNODE_CONF_TIMEOUT_MS (20 * 1000) +#endif +#ifndef RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS +#define RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS (2 * 1000) +#endif + +#ifndef RTW_MESH_OFFCH_CAND +#define RTW_MESH_OFFCH_CAND 1 +#endif +#ifndef RTW_MESH_OFFCH_CAND_FIND_INT_MS +#define RTW_MESH_OFFCH_CAND_FIND_INT_MS (10 * 1000) +#endif + +#ifndef RTW_MESH_PEER_CONF_TIMEOUT_MS +#define RTW_MESH_PEER_CONF_TIMEOUT_MS (20 * 1000) +#endif +#ifndef RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS +#define RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS (20 * 1000) +#endif + +#ifndef RTW_MESH_CTO_MGATE_REQUIRE +#define RTW_MESH_CTO_MGATE_REQUIRE 0 +#endif +#ifndef RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS +#define RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS (20 * 1000) +#endif +#ifndef RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS +#define RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS (20 * 1000) +#endif + +void rtw_mesh_cfg_init_peer_sel_policy(struct rtw_mesh_cfg *mcfg) +{ + struct mesh_peer_sel_policy *sel_policy = &mcfg->peer_sel_policy; + + sel_policy->scanr_exp_ms = RTW_MESH_SCAN_RESULT_EXP_MS; + +#if CONFIG_RTW_MESH_ACNODE_PREVENT + sel_policy->acnode_prevent = RTW_MESH_ACNODE_PREVENT; + sel_policy->acnode_conf_timeout_ms = RTW_MESH_ACNODE_CONF_TIMEOUT_MS; + sel_policy->acnode_notify_timeout_ms = RTW_MESH_ACNODE_NOTIFY_TIMEOUT_MS; +#endif + +#if CONFIG_RTW_MESH_OFFCH_CAND + sel_policy->offch_cand = RTW_MESH_OFFCH_CAND; + sel_policy->offch_find_int_ms = RTW_MESH_OFFCH_CAND_FIND_INT_MS; +#endif + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + sel_policy->peer_conf_timeout_ms = RTW_MESH_PEER_CONF_TIMEOUT_MS; + sel_policy->peer_blacklist_timeout_ms = RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS; +#endif + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + sel_policy->cto_mgate_require = RTW_MESH_CTO_MGATE_REQUIRE; + sel_policy->cto_mgate_conf_timeout_ms = RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS; + sel_policy->cto_mgate_blacklist_timeout_ms = RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS; +#endif +} + +void rtw_mesh_cfg_init(_adapter *adapter) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + + mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS; + mcfg->plink_timeout = RTW_MESH_PEER_LINK_TIMEOUT; + + mcfg->dot11MeshTTL = RTW_MESH_TTL; + mcfg->element_ttl = RTW_MESH_DEFAULT_ELEMENT_TTL; + mcfg->dot11MeshHWMPmaxPREQretries = RTW_MESH_MAX_PREQ_RETRIES; + mcfg->path_refresh_time = RTW_MESH_PATH_REFRESH_TIME; + mcfg->min_discovery_timeout = RTW_MESH_MIN_DISCOVERY_TIMEOUT; + mcfg->dot11MeshHWMPactivePathTimeout = RTW_MESH_PATH_TIMEOUT; + mcfg->dot11MeshHWMPpreqMinInterval = RTW_MESH_PREQ_MIN_INT; + mcfg->dot11MeshHWMPperrMinInterval = RTW_MESH_PERR_MIN_INT; + mcfg->dot11MeshHWMPnetDiameterTraversalTime = RTW_MESH_DIAM_TRAVERSAL_TIME; + mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_ROOTMODE_NO_ROOT; + mcfg->dot11MeshHWMPRannInterval = RTW_MESH_RANN_INTERVAL; + mcfg->dot11MeshGateAnnouncementProtocol = _FALSE; + mcfg->dot11MeshForwarding = _TRUE; + mcfg->rssi_threshold = 0; + mcfg->dot11MeshHWMPactivePathToRootTimeout = RTW_MESH_PATH_TO_ROOT_TIMEOUT; + mcfg->dot11MeshHWMProotInterval = RTW_MESH_ROOT_INTERVAL; + mcfg->dot11MeshHWMPconfirmationInterval = RTW_MESH_ROOT_CONFIRMATION_INTERVAL; + mcfg->path_gate_timeout_factor = 3; + rtw_mesh_cfg_init_peer_sel_policy(mcfg); +#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK + mcfg->sane_metric_delta = RTW_MESH_SANE_METRIC_DELTA; + mcfg->max_root_add_chk_cnt = RTW_MESH_MAX_ROOT_ADD_CHK_CNT; +#endif + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + mcfg->b2u_flags_msrc = 0; + mcfg->b2u_flags_mfwd = RTW_MESH_B2U_GA_UCAST; +#endif +} + +void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + + mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS; + + if (mcfg->max_peer_links > stack_conf) + mcfg->max_peer_links = stack_conf; +} + +void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + + mcfg->plink_timeout = stack_conf; +} + +void rtw_mesh_init_mesh_info(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + + _rtw_memset(minfo, 0, sizeof(struct rtw_mesh_info)); + + rtw_mesh_plink_ctl_init(adapter); + + minfo->last_preq = rtw_get_current_time(); + /* minfo->last_sn_update = rtw_get_current_time(); */ + minfo->next_perr = rtw_get_current_time(); + + ATOMIC_SET(&minfo->mpaths, 0); + rtw_mesh_pathtbl_init(adapter); + + _rtw_init_queue(&minfo->mpath_tx_queue); + tasklet_init(&minfo->mpath_tx_tasklet + , (void(*)(unsigned long))mpath_tx_tasklet_hdl + , (unsigned long)adapter); + + rtw_mrc_init(adapter); + + _rtw_init_listhead(&minfo->preq_queue.list); + _rtw_spinlock_init(&minfo->mesh_preq_queue_lock); + + rtw_init_timer(&adapter->mesh_path_timer, adapter, rtw_ieee80211_mesh_path_timer, adapter); + rtw_init_timer(&adapter->mesh_path_root_timer, adapter, rtw_ieee80211_mesh_path_root_timer, adapter); + rtw_init_timer(&adapter->mesh_atlm_param_req_timer, adapter, rtw_mesh_atlm_param_req_timer, adapter); + _init_workitem(&adapter->mesh_work, rtw_mesh_work_hdl, NULL); +} + +void rtw_mesh_deinit_mesh_info(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + + tasklet_kill(&minfo->mpath_tx_tasklet); + rtw_mpath_tx_queue_flush(adapter); + _rtw_deinit_queue(&adapter->mesh_info.mpath_tx_queue); + + rtw_mrc_free(adapter); + + rtw_mesh_pathtbl_unregister(adapter); + + rtw_mesh_plink_ctl_deinit(adapter); + + _cancel_workitem_sync(&adapter->mesh_work); + _cancel_timer_ex(&adapter->mesh_path_timer); + _cancel_timer_ex(&adapter->mesh_path_root_timer); + _cancel_timer_ex(&adapter->mesh_atlm_param_req_timer); +} + +/** + * rtw_mesh_nexthop_resolve - lookup next hop; conditionally start path discovery + * + * @skb: 802.11 frame to be sent + * @sdata: network subif the frame will be sent through + * + * Lookup next hop for given skb and start path discovery if no + * forwarding information is found. + * + * Returns: 0 if the next hop was found and -ENOENT if the frame was queued. + * skb is freeed here if no mpath could be allocated. + */ +int rtw_mesh_nexthop_resolve(_adapter *adapter, + struct xmit_frame *xframe) +{ + struct pkt_attrib *attrib = &xframe->attrib; + struct rtw_mesh_path *mpath; + struct xmit_frame *xframe_to_free = NULL; + u8 *target_addr = attrib->mda; + int err = 0; + int ret = _SUCCESS; + + rtw_rcu_read_lock(); + err = rtw_mesh_nexthop_lookup(adapter, target_addr, attrib->msa, attrib->ra); + if (!err) + goto endlookup; + + /* no nexthop found, start resolving */ + mpath = rtw_mesh_path_lookup(adapter, target_addr); + if (!mpath) { + mpath = rtw_mesh_path_add(adapter, target_addr); + if (IS_ERR(mpath)) { + xframe->pkt = NULL; /* free pkt outside */ + rtw_mesh_path_discard_frame(adapter, xframe); + err = PTR_ERR(mpath); + ret = _FAIL; + goto endlookup; + } + } + + if (!(mpath->flags & RTW_MESH_PATH_RESOLVING)) + rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START); + + enter_critical_bh(&mpath->frame_queue.lock); + + if (mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) { + xframe_to_free = LIST_CONTAINOR(get_next(get_list_head(&mpath->frame_queue)), struct xmit_frame, list); + rtw_list_delete(&(xframe_to_free->list)); + mpath->frame_queue_len--; + } + + rtw_list_insert_tail(&xframe->list, get_list_head(&mpath->frame_queue)); + mpath->frame_queue_len++; + + exit_critical_bh(&mpath->frame_queue.lock); + + ret = RTW_RA_RESOLVING; + if (xframe_to_free) + rtw_mesh_path_discard_frame(adapter, xframe_to_free); + +endlookup: + rtw_rcu_read_unlock(); + return ret; +} + +/** + * rtw_mesh_nexthop_lookup - put the appropriate next hop on a mesh frame. Calling + * this function is considered "using" the associated mpath, so preempt a path + * refresh if this mpath expires soon. + * + * @skb: 802.11 frame to be sent + * @sdata: network subif the frame will be sent through + * + * Returns: 0 if the next hop was found. Nonzero otherwise. + */ +int rtw_mesh_nexthop_lookup(_adapter *adapter, + const u8 *mda, const u8 *msa, u8 *ra) +{ + struct rtw_mesh_path *mpath; + struct sta_info *next_hop; + const u8 *target_addr = mda; + int err = -ENOENT; + + rtw_rcu_read_lock(); + mpath = rtw_mesh_path_lookup(adapter, target_addr); + + if (!mpath || !(mpath->flags & RTW_MESH_PATH_ACTIVE)) + goto endlookup; + + if (rtw_time_after(rtw_get_current_time(), + mpath->exp_time - + rtw_ms_to_systime(adapter->mesh_cfg.path_refresh_time)) && + _rtw_memcmp(adapter_mac_addr(adapter), msa, ETH_ALEN) == _TRUE && + !(mpath->flags & RTW_MESH_PATH_RESOLVING) && + !(mpath->flags & RTW_MESH_PATH_FIXED)) { + rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH); + } + + next_hop = rtw_rcu_dereference(mpath->next_hop); + if (next_hop) { + _rtw_memcpy(ra, next_hop->cmn.mac_addr, ETH_ALEN); + err = 0; + } + +endlookup: + rtw_rcu_read_unlock(); + return err; +} + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC +static bool rtw_mesh_data_bmc_to_uc(_adapter *adapter + , const u8 *da, const u8 *sa, const u8 *mda, const u8 *msa + , u8 ae_need, const u8 *ori_ta, u8 mfwd_ttl + , _list *b2u_list, u8 *b2u_num, u32 *b2u_mseq) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct xmit_priv *xmitpriv = &adapter->xmitpriv; + _irqL irqL; + _list *head, *list; + struct sta_info *sta; + char b2u_sta_id[NUM_STA]; + u8 b2u_sta_num = 0; + bool bmc_need = _FALSE; + int i; + + _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + head = &stapriv->asoc_list; + list = get_next(head); + + while ((rtw_end_of_queue_search(head, list)) == _FALSE) { + int stainfo_offset; + + sta = LIST_CONTAINOR(list, struct sta_info, asoc_list); + list = get_next(list); + + stainfo_offset = rtw_stainfo_offset(stapriv, sta); + if (stainfo_offset_valid(stainfo_offset)) + b2u_sta_id[b2u_sta_num++] = stainfo_offset; + } + _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + + if (!b2u_sta_num) + goto exit; + + for (i = 0; i < b2u_sta_num; i++) { + struct xmit_frame *b2uframe; + struct pkt_attrib *attrib; + + sta = rtw_get_stainfo_by_offset(stapriv, b2u_sta_id[i]); + if (!(sta->state & _FW_LINKED) + || _rtw_memcmp(sta->cmn.mac_addr, msa, ETH_ALEN) == _TRUE + || (ori_ta && _rtw_memcmp(sta->cmn.mac_addr, ori_ta, ETH_ALEN) == _TRUE) + || is_broadcast_mac_addr(sta->cmn.mac_addr) + || is_zero_mac_addr(sta->cmn.mac_addr)) + continue; + + b2uframe = rtw_alloc_xmitframe(xmitpriv); + if (!b2uframe) { + bmc_need = _TRUE; + break; + } + + if ((*b2u_num)++ == 0 && !ori_ta) { + *b2u_mseq = (cpu_to_le32(adapter->mesh_info.mesh_seqnum)); + adapter->mesh_info.mesh_seqnum++; + } + + attrib = &b2uframe->attrib; + + attrib->mb2u = 1; + attrib->mseq = *b2u_mseq; + attrib->mfwd_ttl = ori_ta ? mfwd_ttl : 0; + _rtw_memcpy(attrib->ra, sta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memcpy(attrib->mda, mda, ETH_ALEN); + _rtw_memcpy(attrib->msa, msa, ETH_ALEN); + _rtw_memcpy(attrib->dst, da, ETH_ALEN); + _rtw_memcpy(attrib->src, sa, ETH_ALEN); + attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA; + + rtw_list_insert_tail(&b2uframe->list, b2u_list); + } + +exit: + return bmc_need; +} + +void dump_mesh_b2u_flags(void *sel, _adapter *adapter) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + + RTW_PRINT_SEL(sel, "%4s %4s\n", "msrc", "mfwd"); + RTW_PRINT_SEL(sel, "0x%02x 0x%02x\n", mcfg->b2u_flags_msrc, mcfg->b2u_flags_mfwd); +} +#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */ + +int rtw_mesh_addr_resolve(_adapter *adapter, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list) +{ + struct pkt_file pktfile; + struct ethhdr etherhdr; + struct pkt_attrib *attrib; + struct rtw_mesh_path *mpath = NULL, *mppath = NULL; + u8 is_da_mcast; + u8 ae_need; +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + bool bmc_need = _TRUE; + u8 b2u_num = 0; + u32 b2u_mseq = 0; +#endif + int res = _SUCCESS; + + _rtw_open_pktfile(pkt, &pktfile); + if (_rtw_pktfile_read(&pktfile, (u8 *)ðerhdr, ETH_HLEN) != ETH_HLEN) { + res = _FAIL; + goto exit; + } + + xframe->pkt = pkt; +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + _rtw_init_listhead(b2u_list); +#endif + + is_da_mcast = IS_MCAST(etherhdr.h_dest); + if (!is_da_mcast) { + struct sta_info *next_hop; + bool mpp_lookup = 1; + + mpath = rtw_mesh_path_lookup(adapter, etherhdr.h_dest); + if (mpath) { + mpp_lookup = 0; + next_hop = rtw_rcu_dereference(mpath->next_hop); + if (!next_hop + || !(mpath->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING)) + ) { + /* mpath is not valid, search mppath */ + mpp_lookup = 1; + } + } + + if (mpp_lookup) { + mppath = rtw_mpp_path_lookup(adapter, etherhdr.h_dest); + if (mppath) + mppath->exp_time = rtw_get_current_time(); + } + + if (mppath && mpath) + rtw_mesh_path_del(adapter, mpath->dst); + + ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE + || (mppath && _rtw_memcmp(mppath->mpp, etherhdr.h_dest, ETH_ALEN) == _FALSE); + } else { + ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE; + + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (rtw_msrc_b2u_policy_chk(adapter->mesh_cfg.b2u_flags_msrc, etherhdr.h_dest)) { + bmc_need = rtw_mesh_data_bmc_to_uc(adapter + , etherhdr.h_dest, etherhdr.h_source + , etherhdr.h_dest, adapter_mac_addr(adapter), ae_need, NULL, 0 + , b2u_list, &b2u_num, &b2u_mseq); + if (bmc_need == _FALSE) { + res = RTW_BMC_NO_NEED; + goto exit; + } + } + #endif + } + + attrib = &xframe->attrib; + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (b2u_num) { + attrib->mb2u = 1; + attrib->mseq = b2u_mseq; + } else + attrib->mb2u = 0; +#endif + + attrib->mfwd_ttl = 0; + _rtw_memcpy(attrib->dst, etherhdr.h_dest, ETH_ALEN); + _rtw_memcpy(attrib->src, etherhdr.h_source, ETH_ALEN); + _rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN); + + if (is_da_mcast) { + attrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA; + _rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN); + _rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN); + } else { + attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA; + _rtw_memcpy(attrib->mda, (mppath && ae_need) ? mppath->mpp : attrib->dst, ETH_ALEN); + _rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN); + /* RA needs to be resolved */ + res = rtw_mesh_nexthop_resolve(adapter, xframe); + } + +exit: + return res; +} + +s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib) +{ + u8 ret = 0; + switch (mesh_frame_mode) { + case MESH_UCAST_DATA: + attrib->hdrlen = WLAN_HDR_A4_QOS_LEN; + /* mesh flag + mesh TTL + Mesh SN. no ext addr. */ + attrib->meshctrl_len = 6; + break; + case MESH_BMCAST_DATA: + attrib->hdrlen = WLAN_HDR_A3_QOS_LEN; + /* mesh flag + mesh TTL + Mesh SN. no ext addr. */ + attrib->meshctrl_len = 6; + break; + case MESH_UCAST_PX_DATA: + attrib->hdrlen = WLAN_HDR_A4_QOS_LEN; + /* mesh flag + mesh TTL + Mesh SN + extaddr1 + extaddr2. */ + attrib->meshctrl_len = 18; + break; + case MESH_BMCAST_PX_DATA: + attrib->hdrlen = WLAN_HDR_A3_QOS_LEN; + /* mesh flag + mesh TTL + Mesh SN + extaddr1 */ + attrib->meshctrl_len = 12; + break; + default: + RTW_WARN("Invalid mesh frame mode:%u\n", mesh_frame_mode); + ret = -1; + break; + } + + return ret; +} + +void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf) +{ + struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)buf; + + _rtw_memset(mctrl, 0, XATTRIB_GET_MCTRL_LEN(attrib)); + + if (attrib->mfwd_ttl + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + || attrib->mb2u + #endif + ) { + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (!attrib->mfwd_ttl) + mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL; + else + #endif + mctrl->ttl = attrib->mfwd_ttl; + + mctrl->seqnum = (cpu_to_le32(attrib->mseq)); + } else { + mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL; + mctrl->seqnum = (cpu_to_le32(adapter->mesh_info.mesh_seqnum)); + adapter->mesh_info.mesh_seqnum++; + } + + switch (attrib->mesh_frame_mode){ + case MESH_UCAST_DATA: + case MESH_BMCAST_DATA: + break; + case MESH_UCAST_PX_DATA: + mctrl->flags |= MESH_FLAGS_AE_A5_A6; + _rtw_memcpy(mctrl->eaddr1, attrib->dst, ETH_ALEN); + _rtw_memcpy(mctrl->eaddr2, attrib->src, ETH_ALEN); + break; + case MESH_BMCAST_PX_DATA: + mctrl->flags |= MESH_FLAGS_AE_A4; + _rtw_memcpy(mctrl->eaddr1, attrib->src, ETH_ALEN); + break; + case MESH_MHOP_UCAST_ACT: + /* TBD */ + break; + case MESH_MHOP_BMCAST_ACT: + /* TBD */ + break; + default: + break; + } +} + +u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib + , u16 *fctrl, struct rtw_ieee80211_hdr *whdr) +{ + switch (attrib->mesh_frame_mode) { + case MESH_UCAST_DATA: /* 1, 1, RA, TA, mDA(=DA), mSA(=SA) */ + case MESH_UCAST_PX_DATA: /* 1, 1, RA, TA, mDA, mSA, [DA, SA] */ + SetToDs(fctrl); + SetFrDs(fctrl); + _rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN); + _rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN); + _rtw_memcpy(whdr->addr3, attrib->mda, ETH_ALEN); + _rtw_memcpy(whdr->addr4, attrib->msa, ETH_ALEN); + break; + case MESH_BMCAST_DATA: /* 0, 1, RA(DA), TA, mSA(SA) */ + case MESH_BMCAST_PX_DATA: /* 0, 1, RA(DA), TA, mSA, [SA] */ + SetFrDs(fctrl); + _rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN); + _rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN); + _rtw_memcpy(whdr->addr3, attrib->msa, ETH_ALEN); + break; + case MESH_MHOP_UCAST_ACT: + /* TBD */ + RTW_INFO("MESH_MHOP_UCAST_ACT\n"); + break; + case MESH_MHOP_BMCAST_ACT: + /* TBD */ + RTW_INFO("MESH_MHOP_BMCAST_ACT\n"); + break; + default: + RTW_WARN("Invalid mesh frame mode\n"); + break; + } + + return 0; +} + +int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib; + u8 *whdr = get_recvframe_data(rframe); + u8 is_ra_bmc = 0; + u8 a4_shift = 0; + u8 ps; + u8 *qc; + u8 mps_mode = RTW_MESH_PS_UNKNOWN; + sint ret = _FAIL; + + if (!(MLME_STATE(adapter) & WIFI_ASOC_STATE)) + goto exit; + + if (!rattrib->qos) + goto exit; + + switch (rattrib->to_fr_ds) { + case 1: + if (!IS_MCAST(GetAddr1Ptr(whdr))) + goto exit; + *sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr)); + if (*sta == NULL) { + ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */ + goto exit; + } + _rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->mda, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->msa, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ + _rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->src, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */ + _rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN); + is_ra_bmc = 1; + break; + case 3: + if (IS_MCAST(GetAddr1Ptr(whdr))) + goto exit; + *sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr)); + if (*sta == NULL) { + ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */ + goto exit; + } + _rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN); + _rtw_memcpy(rattrib->mda, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ + _rtw_memcpy(rattrib->msa, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */ + _rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */ + _rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */ + _rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN); + a4_shift = ETH_ALEN; + break; + default: + goto exit; + } + + qc = whdr + WLAN_HDR_A3_LEN + a4_shift; + ps = GetPwrMgt(whdr); + mps_mode = ps ? (is_ra_bmc || (get_mps_lv(qc)) ? RTW_MESH_PS_DSLEEP : RTW_MESH_PS_LSLEEP) : RTW_MESH_PS_ACTIVE; + + if (ps) { + if (!((*sta)->state & WIFI_SLEEP_STATE)) + stop_sta_xmit(adapter, *sta); + } else { + if ((*sta)->state & WIFI_SLEEP_STATE) + wakeup_sta_to_xmit(adapter, *sta); + } + + if (is_ra_bmc) + (*sta)->nonpeer_mps = mps_mode; + else { + (*sta)->peer_mps = mps_mode; + if (mps_mode != RTW_MESH_PS_ACTIVE && (*sta)->nonpeer_mps == RTW_MESH_PS_ACTIVE) + (*sta)->nonpeer_mps = RTW_MESH_PS_DSLEEP; + } + + if (get_frame_sub_type(whdr) & BIT(6)) { + /* No data, will not indicate to upper layer, temporily count it here */ + count_rx_stats(adapter, rframe, *sta); + ret = RTW_RX_HANDLED; + goto exit; + } + + rattrib->mesh_ctrl_present = get_mctrl_present(qc) ? 1 : 0; + if (!rattrib->mesh_ctrl_present) + goto exit; + + ret = _SUCCESS; + +exit: + return ret; +} + +int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe + , const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa + , u8 *mctrl_len + , const u8 **da, const u8 **sa) +{ + struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib; + u8 mlen; + u8 ae; + int ret = _SUCCESS; + + ae = mctrl->flags & MESH_FLAGS_AE; + mlen = ae_to_mesh_ctrl_len[ae]; + switch (rattrib->to_fr_ds) { + case 1: + *da = mda; + if (ae == MESH_FLAGS_AE_A4) + *sa = mctrl->eaddr1; + else if (ae == 0) + *sa = msa; + else + ret = _FAIL; + break; + case 3: + if (ae == MESH_FLAGS_AE_A5_A6) { + *da = mctrl->eaddr1; + *sa = mctrl->eaddr2; + } else if (ae == 0) { + *da = mda; + *sa = msa; + } else + ret = _FAIL; + break; + default: + ret = _FAIL; + } + + if (ret == _FAIL) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" invalid tfDS:%u AE:%u combination ra="MAC_FMT" ta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), rattrib->to_fr_ds, ae, MAC_ARG(rattrib->ra), MAC_ARG(rattrib->ta)); + #endif + *mctrl_len = 0; + } else + *mctrl_len = mlen; + + return ret; +} + +inline int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe) +{ + struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib; + const u8 *da, *sa; + int ret; + + ret = rtw_mesh_rx_data_validate_mctrl(adapter, rframe + , (struct rtw_ieee80211s_hdr *)(get_recvframe_data(rframe) + rattrib->hdrlen + rattrib->iv_len) + , rattrib->mda, rattrib->msa + , &rattrib->mesh_ctrl_len + , &da, &sa); + + if (ret == _SUCCESS) { + _rtw_memcpy(rattrib->dst, da, ETH_ALEN); + _rtw_memcpy(rattrib->src, sa, ETH_ALEN); + } + + return ret; +} + +/** + * rtw_mesh_rx_nexthop_resolve - lookup next hop; conditionally start path discovery + * + * @skb: 802.11 frame to be sent + * @sdata: network subif the frame will be sent through + * + * Lookup next hop for given skb and start path discovery if no + * forwarding information is found. + * + * Returns: 0 if the next hop was found and -ENOENT if the frame was queued. + * skb is freeed here if no mpath could be allocated. + */ +static int rtw_mesh_rx_nexthop_resolve(_adapter *adapter, + const u8 *mda, const u8 *msa, u8 *ra) +{ + struct rtw_mesh_path *mpath; + struct xmit_frame *xframe_to_free = NULL; + int err = 0; + int ret = _SUCCESS; + + rtw_rcu_read_lock(); + err = rtw_mesh_nexthop_lookup(adapter, mda, msa, ra); + if (!err) + goto endlookup; + + /* no nexthop found, start resolving */ + mpath = rtw_mesh_path_lookup(adapter, mda); + if (!mpath) { + mpath = rtw_mesh_path_add(adapter, mda); + if (IS_ERR(mpath)) { + err = PTR_ERR(mpath); + ret = _FAIL; + goto endlookup; + } + } + + if (!(mpath->flags & RTW_MESH_PATH_RESOLVING)) + rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START); + + ret = _FAIL; + +endlookup: + rtw_rcu_read_unlock(); + return ret; +} + +#define RTW_MESH_DECACHE_BMC 1 +#define RTW_MESH_DECACHE_UC 0 + +#define RTW_MESH_FORWARD_MDA_SELF_COND 0 +#define DBG_RTW_MESH_FORWARD_MDA_SELF_COND 0 +int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe + , const u8 *mda, const u8 *msa + , const u8 *da, const u8 *sa + , struct rtw_ieee80211s_hdr *mctrl + , struct xmit_frame **fwd_frame, _list *b2u_list) +{ + _adapter *adapter = rframe->u.hdr.adapter; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib; + struct rtw_mesh_path *mppath; + u8 is_mda_bmc = IS_MCAST(mda); + u8 is_mda_self = !is_mda_bmc && _rtw_memcmp(mda, adapter_mac_addr(adapter), ETH_ALEN); + struct xmit_frame *xframe; + struct pkt_attrib *xattrib; + u8 fwd_ra[ETH_ALEN] = {0}; + u8 fwd_mpp[ETH_ALEN] = {0}; /* forward to other gate */ + u32 fwd_mseq; + int act = 0; + u8 ae_need; +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + bool bmc_need = _TRUE; + u8 b2u_num = 0; +#endif + + /* fwd info lifetime update */ + #if 0 + if (!is_mda_self) + mDA(A3) fwinfo.lifetime + mSA(A4) fwinfo.lifetime + Precursor-to-mDA(A2) fwinfo.lifetime + #endif + + /* update/create pxoxy info for SA, mSA */ + if ((mctrl->flags & MESH_FLAGS_AE) + && sa != msa && _rtw_memcmp(sa, msa, ETH_ALEN) == _FALSE + ) { + const u8 *proxied_addr = sa; + const u8 *mpp_addr = msa; + + rtw_rcu_read_lock(); + mppath = rtw_mpp_path_lookup(adapter, proxied_addr); + if (!mppath) + rtw_mpp_path_add(adapter, proxied_addr, mpp_addr); + else { + enter_critical_bh(&mppath->state_lock); + if (_rtw_memcmp(mppath->mpp, mpp_addr, ETH_ALEN) == _FALSE) + _rtw_memcpy(mppath->mpp, mpp_addr, ETH_ALEN); + mppath->exp_time = rtw_get_current_time(); + exit_critical_bh(&mppath->state_lock); + } + rtw_rcu_read_unlock(); + } + + /* mSA is self, need no further process */ + if (_rtw_memcmp(msa, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE) + goto exit; + + fwd_mseq = le32_to_cpu(mctrl->seqnum); + + /* check duplicate MSDU from mSA */ + if (((RTW_MESH_DECACHE_BMC && is_mda_bmc) + || (RTW_MESH_DECACHE_UC && !is_mda_bmc)) + && rtw_mesh_decache(adapter, msa, fwd_mseq) + ) { + minfo->mshstats.dropped_frames_duplicate++; + goto exit; + } + + if (is_mda_bmc) { + /* mDA is bmc addr */ + act |= RTW_RX_MSDU_ACT_INDICATE; + if (!mcfg->dot11MeshForwarding) + goto exit; + goto fwd_chk; + + } else if (!is_mda_self) { + /* mDA is unicast but not self */ + if (!mcfg->dot11MeshForwarding) { + rtw_mesh_path_error_tx(adapter + , adapter->mesh_cfg.element_ttl + , mda, 0 + , WLAN_REASON_MESH_PATH_NOFORWARD + , rattrib->ta + ); + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") not self, !dot11MeshForwarding\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(mda)); + #endif + goto exit; + } + + if (rtw_mesh_rx_nexthop_resolve(adapter, mda, msa, fwd_ra) != _SUCCESS) { + /* mDA is unknown */ + rtw_mesh_path_error_tx(adapter + , adapter->mesh_cfg.element_ttl + , mda, 0 + , WLAN_REASON_MESH_PATH_NOFORWARD + , rattrib->ta + ); + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") unknown\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(mda)); + #endif + minfo->mshstats.dropped_frames_no_route++; + goto exit; + + } else { + /* mDA is known in fwd info */ + #if 0 + if (TA is not in precursors) + goto exit; + #endif + goto fwd_chk; + } + + } else { + /* mDA is self */ + #if RTW_MESH_FORWARD_MDA_SELF_COND + if (da == mda + || _rtw_memcmp(da, adapter_mac_addr(adapter), ETH_ALEN) + ) { + /* DA is self, indicate */ + act |= RTW_RX_MSDU_ACT_INDICATE; + goto exit; + } + + if (rtw_get_iface_by_macddr(adapter, da)) { + /* DA is buddy, indicate */ + act |= RTW_RX_MSDU_ACT_INDICATE; + #if DBG_RTW_MESH_FORWARD_MDA_SELF_COND + RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is buddy("ADPT_FMT")\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(da), ADPT_ARG(rtw_get_iface_by_macddr(adapter, da))); + #endif + goto exit; + } + + /* DA is not self or buddy */ + if (rtw_mesh_nexthop_lookup(adapter, da, msa, fwd_ra) == 0) { + /* DA is known in fwd info */ + if (!mcfg->dot11MeshForwarding) { + /* path error to? */ + #if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") not self, !dot11MeshForwarding\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(da)); + #endif + goto exit; + } + mda = da; + #if DBG_RTW_MESH_FORWARD_MDA_SELF_COND + RTW_INFO(FUNC_ADPT_FMT" fwd to DA("MAC_FMT"), fwd_RA("MAC_FMT")\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(fwd_ra)); + #endif + goto fwd_chk; + } + + rtw_rcu_read_lock(); + mppath = rtw_mpp_path_lookup(adapter, da); + if (mppath) { + if (_rtw_memcmp(mppath->mpp, adapter_mac_addr(adapter), ETH_ALEN) == _FALSE) { + /* DA is proxied by others */ + if (!mcfg->dot11MeshForwarding) { + /* path error to? */ + #if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), !dot11MeshForwarding\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp)); + #endif + rtw_rcu_read_unlock(); + goto exit; + } + _rtw_memcpy(fwd_mpp, mppath->mpp, ETH_ALEN); + mda = fwd_mpp; + msa = adapter_mac_addr(adapter); + rtw_rcu_read_unlock(); + + /* resolve RA */ + if (rtw_mesh_nexthop_lookup(adapter, mda, msa, fwd_ra) != 0) { + minfo->mshstats.dropped_frames_no_route++; + #if defined(DBG_RX_DROP_FRAME) || DBG_RTW_MESH_FORWARD_MDA_SELF_COND + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), RA resolve fail\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp)); + #endif + goto exit; + } + #if DBG_RTW_MESH_FORWARD_MDA_SELF_COND + RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by ("MAC_FMT"), fwd_RA("MAC_FMT")\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp), MAC_ARG(fwd_ra)); + #endif + goto fwd_chk; /* forward to other gate */ + } else { + #if DBG_RTW_MESH_FORWARD_MDA_SELF_COND + RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") is proxied by self\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(da)); + #endif + } + } + rtw_rcu_read_unlock(); + + if (!mppath) { + #if DBG_RTW_MESH_FORWARD_MDA_SELF_COND + RTW_INFO(FUNC_ADPT_FMT" DA("MAC_FMT") unknown\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(da)); + #endif + /* DA is unknown */ + #if 0 /* TODO: flags with AE bit */ + rtw_mesh_path_error_tx(adapter + , adapter->mesh_cfg.element_ttl + , mda, adapter->mesh_info.last_sn_update + , WLAN_REASON_MESH_PATH_NOPROXY + , msa + ); + #endif + } + + /* + * indicate to DS for both cases: + * 1.) DA is proxied by self + * 2.) DA is unknown + */ + #endif /* RTW_MESH_FORWARD_MDA_SELF_COND */ + act |= RTW_RX_MSDU_ACT_INDICATE; + goto exit; + } + +fwd_chk: + + if (adapter->stapriv.asoc_list_cnt <= 1) + goto exit; + + if (mctrl->ttl == 1) { + minfo->mshstats.dropped_frames_ttl++; + if (!act) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" ttl reaches 0, not forwarding\n" + , FUNC_ADPT_ARG(adapter)); + #endif + } + goto exit; + } + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + _rtw_init_listhead(b2u_list); +#endif + + ae_need = _rtw_memcmp(da , mda, ETH_ALEN) == _FALSE + || _rtw_memcmp(sa , msa, ETH_ALEN) == _FALSE; + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (is_mda_bmc + && rtw_mfwd_b2u_policy_chk(mcfg->b2u_flags_mfwd, mda, rattrib->to_fr_ds == 3) + ) { + bmc_need = rtw_mesh_data_bmc_to_uc(adapter + , da, sa, mda, msa, ae_need, rframe->u.hdr.psta->cmn.mac_addr, mctrl->ttl - 1 + , b2u_list, &b2u_num, &fwd_mseq); + } + + if (bmc_need == _TRUE) +#endif + { + xframe = rtw_alloc_xmitframe(&adapter->xmitpriv); + if (!xframe) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME "FUNC_ADPT_FMT" rtw_alloc_xmitframe fail\n" + , FUNC_ADPT_ARG(adapter)); + #endif + goto exit; + } + + xattrib = &xframe->attrib; + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (b2u_num) + xattrib->mb2u = 1; + else + xattrib->mb2u = 0; +#endif + xattrib->mfwd_ttl = mctrl->ttl - 1; + xattrib->mseq = fwd_mseq; + _rtw_memcpy(xattrib->dst, da, ETH_ALEN); + _rtw_memcpy(xattrib->src, sa, ETH_ALEN); + _rtw_memcpy(xattrib->mda, mda, ETH_ALEN); + _rtw_memcpy(xattrib->msa, msa, ETH_ALEN); + _rtw_memcpy(xattrib->ta, adapter_mac_addr(adapter), ETH_ALEN); + + if (is_mda_bmc) { + xattrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA; + _rtw_memcpy(xattrib->ra, mda, ETH_ALEN); + } else { + xattrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA; + _rtw_memcpy(xattrib->ra, fwd_ra, ETH_ALEN); + } + + *fwd_frame = xframe; + } + + act |= RTW_RX_MSDU_ACT_FORWARD; + if (is_mda_bmc) + minfo->mshstats.fwded_mcast++; + else + minfo->mshstats.fwded_unicast++; + minfo->mshstats.fwded_frames++; + +exit: + return act; +} + +void dump_mesh_stats(void *sel, _adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_stats *stats = &minfo->mshstats; + + RTW_PRINT_SEL(sel, "fwd_bmc:%u\n", stats->fwded_mcast); + RTW_PRINT_SEL(sel, "fwd_uc:%u\n", stats->fwded_unicast); + + RTW_PRINT_SEL(sel, "drop_ttl:%u\n", stats->dropped_frames_ttl); + RTW_PRINT_SEL(sel, "drop_no_route:%u\n", stats->dropped_frames_no_route); + RTW_PRINT_SEL(sel, "drop_congestion:%u\n", stats->dropped_frames_congestion); + RTW_PRINT_SEL(sel, "drop_dup:%u\n", stats->dropped_frames_duplicate); + + RTW_PRINT_SEL(sel, "mrc_del_qlen:%u\n", stats->mrc_del_qlen); +} +#endif /* CONFIG_RTW_MESH */ + diff --git a/core/mesh/rtw_mesh.h b/core/mesh/rtw_mesh.h new file mode 100644 index 0000000..6f7f707 --- /dev/null +++ b/core/mesh/rtw_mesh.h @@ -0,0 +1,534 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_MESH_H_ +#define __RTW_MESH_H_ + +#ifndef CONFIG_AP_MODE + #error "CONFIG_RTW_MESH can't be enabled when CONFIG_AP_MODE is not defined\n" +#endif + +#define RTW_MESH_TTL 31 +#define RTW_MESH_PERR_MIN_INT 100 +#define RTW_MESH_DEFAULT_ELEMENT_TTL 31 +#define RTW_MESH_RANN_INTERVAL 5000 +#define RTW_MESH_PATH_TO_ROOT_TIMEOUT 6000 +#define RTW_MESH_DIAM_TRAVERSAL_TIME 50 +#define RTW_MESH_PATH_TIMEOUT 5000 +#define RTW_MESH_PREQ_MIN_INT 10 +#define RTW_MESH_MAX_PREQ_RETRIES 4 +#define RTW_MESH_MIN_DISCOVERY_TIMEOUT (2 * RTW_MESH_DIAM_TRAVERSAL_TIME) +#define RTW_MESH_ROOT_CONFIRMATION_INTERVAL 2000 +#define RTW_MESH_PATH_REFRESH_TIME 1000 +#define RTW_MESH_ROOT_INTERVAL 5000 + +#define RTW_MESH_SANE_METRIC_DELTA 100 +#define RTW_MESH_MAX_ROOT_ADD_CHK_CNT 2 + +#define RTW_MESH_PLINK_UNKNOWN 0 +#define RTW_MESH_PLINK_LISTEN 1 +#define RTW_MESH_PLINK_OPN_SNT 2 +#define RTW_MESH_PLINK_OPN_RCVD 3 +#define RTW_MESH_PLINK_CNF_RCVD 4 +#define RTW_MESH_PLINK_ESTAB 5 +#define RTW_MESH_PLINK_HOLDING 6 +#define RTW_MESH_PLINK_BLOCKED 7 + +extern const char *_rtw_mesh_plink_str[]; +#define rtw_mesh_plink_str(s) ((s <= RTW_MESH_PLINK_BLOCKED) ? _rtw_mesh_plink_str[s] : _rtw_mesh_plink_str[RTW_MESH_PLINK_UNKNOWN]) + +#define RTW_MESH_PS_UNKNOWN 0 +#define RTW_MESH_PS_ACTIVE 1 +#define RTW_MESH_PS_LSLEEP 2 +#define RTW_MESH_PS_DSLEEP 3 + +extern const char *_rtw_mesh_ps_str[]; +#define rtw_mesh_ps_str(mps) ((mps <= RTW_MESH_PS_DSLEEP) ? _rtw_mesh_ps_str[mps] : _rtw_mesh_ps_str[RTW_MESH_PS_UNKNOWN]) + +#define GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 0, 0, 8) +#define GET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 1, 0, 8) +#define GET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 2, 0, 8) +#define GET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 3, 0, 8) +#define GET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 4, 0, 8) + +#define GET_MESH_CONF_ELE_MESH_FORMATION(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 8) +#define GET_MESH_CONF_ELE_CTO_MGATE(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 1) +#define GET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 1, 6) +#define GET_MESH_CONF_ELE_CTO_AS(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 7, 1) + +#define GET_MESH_CONF_ELE_MESH_CAP(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 8) +#define GET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 1) +#define GET_MESH_CONF_ELE_MCCA_SUP(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 1, 1) +#define GET_MESH_CONF_ELE_MCCA_EN(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 2, 1) +#define GET_MESH_CONF_ELE_FORWARDING(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 3, 1) +#define GET_MESH_CONF_ELE_MBCA_EN(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 4, 1) +#define GET_MESH_CONF_ELE_TBTT_ADJ(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 5, 1) +#define GET_MESH_CONF_ELE_PS_LEVEL(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 6, 1) + +#define SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 0, 0, 8, _val) +#define SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 1, 0, 8, _val) +#define SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 2, 0, 8, _val) +#define SET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 3, 0, 8, _val) +#define SET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 4, 0, 8, _val) + +#define SET_MESH_CONF_ELE_CTO_MGATE(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 0, 1, _val) +#define SET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 1, 6, _val) +#define SET_MESH_CONF_ELE_CTO_AS(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 7, 1, _val) + +#define SET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 0, 1, _val) +#define SET_MESH_CONF_ELE_MCCA_SUP(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 1, 1, _val) +#define SET_MESH_CONF_ELE_MCCA_EN(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 2, 1, _val) +#define SET_MESH_CONF_ELE_FORWARDING(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 3, 1, _val) +#define SET_MESH_CONF_ELE_MBCA_EN(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 4, 1, _val) +#define SET_MESH_CONF_ELE_TBTT_ADJ(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 5, 1, _val) +#define SET_MESH_CONF_ELE_PS_LEVEL(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 6, 1, _val) + +/* Mesh flags */ +#define MESH_FLAGS_AE 0x3 /* mask */ +#define MESH_FLAGS_AE_A4 0x1 +#define MESH_FLAGS_AE_A5_A6 0x2 + +/* Max number of paths */ +#define RTW_MESH_MAX_PATHS 1024 + +#define RTW_PREQ_Q_F_START 0x1 +#define RTW_PREQ_Q_F_REFRESH 0x2 +#define RTW_PREQ_Q_F_CHK 0x4 +#define RTW_PREQ_Q_F_PEER_AKA 0x8 +struct rtw_mesh_preq_queue { + _list list; + u8 dst[ETH_ALEN]; + u8 flags; +}; + +extern const u8 ae_to_mesh_ctrl_len[]; + +enum mesh_frame_type { + MESH_UCAST_DATA = 0x0, + MESH_BMCAST_DATA = 0x1, + MESH_UCAST_PX_DATA = 0x2, + MESH_BMCAST_PX_DATA = 0x3, + MESH_MHOP_UCAST_ACT = 0x4, + MESH_MHOP_BMCAST_ACT = 0x5, +}; + +enum mpath_sel_frame_type { + MPATH_PREQ = 0, + MPATH_PREP, + MPATH_PERR, + MPATH_RANN +}; + +/** + * enum rtw_mesh_deferred_task_flags - mesh deferred tasks + * + * + * + * @RTW_MESH_WORK_HOUSEKEEPING: run the periodic mesh housekeeping tasks + * @RTW_MESH_WORK_ROOT: the mesh root station needs to send a frame + * @RTW_MESH_WORK_DRIFT_ADJUST: time to compensate for clock drift relative to other + * mesh nodes + * @RTW_MESH_WORK_MBSS_CHANGED: rebuild beacon and notify driver of BSS changes + */ +enum rtw_mesh_deferred_task_flags { + RTW_MESH_WORK_HOUSEKEEPING, + RTW_MESH_WORK_ROOT, + RTW_MESH_WORK_DRIFT_ADJUST, + RTW_MESH_WORK_MBSS_CHANGED, +}; + +#define RTW_MESH_MAX_PEER_CANDIDATES 15 /* aid consideration */ +#define RTW_MESH_MAX_PEER_LINKS 8 +#define RTW_MESH_PEER_LINK_TIMEOUT 20 + +#define RTW_MESH_PEER_CONF_DISABLED 0 /* special time value means no confirmation ongoing */ +#if CONFIG_RTW_MESH_PEER_BLACKLIST +#define IS_PEER_CONF_DISABLED(plink) ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED) +#define IS_PEER_CONF_TIMEOUT(plink)(!IS_PEER_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->peer_conf_end_time)) +#define SET_PEER_CONF_DISABLED(plink) (plink)->peer_conf_end_time = RTW_MESH_PEER_CONF_DISABLED +#define SET_PEER_CONF_END_TIME(plink, timeout_ms) \ + do { \ + (plink)->peer_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \ + if ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED) \ + (plink)->peer_conf_end_time++; \ + } while (0) +#else +#define IS_PEER_CONF_DISABLED(plink) 1 +#define IS_PEER_CONF_TIMEOUT(plink) 0 +#define SET_PEER_CONF_DISABLED(plink) do {} while (0) +#define SET_PEER_CONF_END_TIME(plink, timeout_ms) do {} while (0) +#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */ + +#define RTW_MESH_CTO_MGATE_CONF_DISABLED 0 /* special time value means no confirmation ongoing */ +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST +#define IS_CTO_MGATE_CONF_DISABLED(plink) ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED) +#define IS_CTO_MGATE_CONF_TIMEOUT(plink)(!IS_CTO_MGATE_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->cto_mgate_conf_end_time)) +#define SET_CTO_MGATE_CONF_DISABLED(plink) (plink)->cto_mgate_conf_end_time = RTW_MESH_CTO_MGATE_CONF_DISABLED +#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) \ + do { \ + (plink)->cto_mgate_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \ + if ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED) \ + (plink)->cto_mgate_conf_end_time++; \ + } while (0) +#else +#define IS_CTO_MGATE_CONF_DISABLED(plink) 1 +#define IS_CTO_MGATE_CONF_TIMEOUT(plink) 0 +#define SET_CTO_MGATE_CONF_DISABLED(plink) do {} while (0) +#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) do {} while (0) +#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ + +struct mesh_plink_ent { + u8 valid; + u8 addr[ETH_ALEN]; + u8 plink_state; + +#ifdef CONFIG_RTW_MESH_AEK + u8 aek_valid; + u8 aek[32]; +#endif + + u16 llid; + u16 plid; +#ifndef CONFIG_RTW_MESH_DRIVER_AID + u16 aid; /* aid assigned from upper layer */ +#endif + u16 peer_aid; /* aid assigned from peer */ + + u8 chosen_pmk[16]; + +#ifdef CONFIG_RTW_MESH_AEK + u8 sel_pcs[4]; + u8 l_nonce[32]; + u8 p_nonce[32]; +#endif + +#ifdef CONFIG_RTW_MESH_DRIVER_AID + u8 *tx_conf_ies; + u16 tx_conf_ies_len; +#endif + u8 *rx_conf_ies; + u16 rx_conf_ies_len; + + struct wlan_network *scanned; + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + systime peer_conf_end_time; +#endif +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + systime cto_mgate_conf_end_time; +#endif +}; + +#ifdef CONFIG_RTW_MESH_AEK +#define MESH_PLINK_AEK_VALID(ent) ent->aek_valid +#else +#define MESH_PLINK_AEK_VALID(ent) 0 +#endif + +struct mesh_plink_pool { + _lock lock; + u8 num; /* current ent being used */ + struct mesh_plink_ent ent[RTW_MESH_MAX_PEER_CANDIDATES]; + +#if CONFIG_RTW_MESH_ACNODE_PREVENT + u8 acnode_rsvd; +#endif + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + _queue peer_blacklist; +#endif +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + _queue cto_mgate_blacklist; +#endif +}; + +struct mesh_peer_sel_policy { + u32 scanr_exp_ms; + +#if CONFIG_RTW_MESH_ACNODE_PREVENT + u8 acnode_prevent; + u32 acnode_conf_timeout_ms; + u32 acnode_notify_timeout_ms; +#endif + +#if CONFIG_RTW_MESH_OFFCH_CAND + u8 offch_cand; + u32 offch_find_int_ms; /* 0 means no offch find triggerred by driver self*/ +#endif + +#if CONFIG_RTW_MESH_PEER_BLACKLIST + u32 peer_conf_timeout_ms; + u32 peer_blacklist_timeout_ms; +#endif + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + u8 cto_mgate_require; + u32 cto_mgate_conf_timeout_ms; + u32 cto_mgate_blacklist_timeout_ms; +#endif +}; + +/* b2u flags */ +#define RTW_MESH_B2U_ALL BIT0 +#define RTW_MESH_B2U_GA_UCAST BIT1 /* Group addressed unicast frame, forward only */ +#define RTW_MESH_B2U_BCAST BIT2 +#define RTW_MESH_B2U_IP_MCAST BIT3 + +#define rtw_msrc_b2u_policy_chk(flags, mda) ( \ + (flags & RTW_MESH_B2U_ALL) \ + || ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \ + || ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \ + ) + +#define rtw_mfwd_b2u_policy_chk(flags, mda, ucst) ( \ + (flags & RTW_MESH_B2U_ALL) \ + || ((flags & RTW_MESH_B2U_GA_UCAST) && ucst) \ + || ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \ + || ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \ + ) + +/** + * @sane_metric_delta: Controlling if trigger additional path check mechanism + * @max_root_add_chk_cnt: The retry cnt to send additional root confirmation + * PREQ through old(last) path + */ +struct rtw_mesh_cfg { + u8 max_peer_links; /* peering limit */ + u32 plink_timeout; /* seconds */ + + u8 dot11MeshTTL; + u8 element_ttl; + u32 path_refresh_time; + u16 dot11MeshHWMPpreqMinInterval; + u16 dot11MeshHWMPnetDiameterTraversalTime; + u32 dot11MeshHWMPactivePathTimeout; + u8 dot11MeshHWMPmaxPREQretries; + u16 min_discovery_timeout; + u16 dot11MeshHWMPconfirmationInterval; + u16 dot11MeshHWMPperrMinInterval; + u8 dot11MeshHWMPRootMode; + BOOLEAN dot11MeshForwarding; + s32 rssi_threshold; /* in dBm, 0: no specified */ + u16 dot11MeshHWMPRannInterval; + BOOLEAN dot11MeshGateAnnouncementProtocol; + u32 dot11MeshHWMPactivePathToRootTimeout; + u16 dot11MeshHWMProotInterval; + u8 path_gate_timeout_factor; +#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK + u16 sane_metric_delta; + u8 max_root_add_chk_cnt; +#endif + + struct mesh_peer_sel_policy peer_sel_policy; + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + u8 b2u_flags_msrc; + u8 b2u_flags_mfwd; +#endif +}; + +struct rtw_mesh_stats { + u32 fwded_mcast; /* Mesh forwarded multicast frames */ + u32 fwded_unicast; /* Mesh forwarded unicast frames */ + u32 fwded_frames; /* Mesh total forwarded frames */ + u32 dropped_frames_ttl; /* Not transmitted since mesh_ttl == 0*/ + u32 dropped_frames_no_route; /* Not transmitted, no route found */ + u32 dropped_frames_congestion;/* Not forwarded due to congestion */ + u32 dropped_frames_duplicate; + + u32 mrc_del_qlen; /* MRC entry deleted cause by queue length limit */ +}; + +struct rtw_mrc; + +struct rtw_mesh_info { + u8 mesh_id[NDIS_802_11_LENGTH_SSID]; + size_t mesh_id_len; + /* Active Path Selection Protocol Identifier */ + u8 mesh_pp_id; + /* Active Path Selection Metric Identifier */ + u8 mesh_pm_id; + /* Congestion Control Mode Identifier */ + u8 mesh_cc_id; + /* Synchronization Protocol Identifier */ + u8 mesh_sp_id; + /* Authentication Protocol Identifier */ + u8 mesh_auth_id; + + struct mesh_plink_pool plink_ctl; + + u32 mesh_seqnum; + /* MSTA's own hwmp sequence number */ + u32 sn; + systime last_preq; + systime last_sn_update; + systime next_perr; + /* Last used Path Discovery ID */ + u32 preq_id; + + ATOMIC_T mpaths; + struct rtw_mesh_table *mesh_paths; + struct rtw_mesh_table *mpp_paths; + int mesh_paths_generation; + int mpp_paths_generation; + + int num_gates; + struct rtw_mesh_path *max_addr_gate; + bool max_addr_gate_is_larger_than_self; + + struct rtw_mesh_stats mshstats; + + _queue mpath_tx_queue; + u32 mpath_tx_queue_len; + struct tasklet_struct mpath_tx_tasklet; + + struct rtw_mrc *mrc; + + _lock mesh_preq_queue_lock; + struct rtw_mesh_preq_queue preq_queue; + int preq_queue_len; +}; + +extern const char *_action_self_protected_str[]; +#define action_self_protected_str(action) ((action < RTW_ACT_SELF_PROTECTED_NUM) ? _action_self_protected_str[action] : _action_self_protected_str[0]) + +u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len); +u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len + , u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto + , u8 num_of_peerings, bool cto_mgate, bool cto_as + , bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding + , bool mbca_en, bool tbtt_adj, bool ps_level); + +int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b); +int rtw_bss_is_candidate_mesh_peer(WLAN_BSSID_EX *self, WLAN_BSSID_EX *target, u8 ch, u8 add_peer); + +void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned); + +void rtw_mesh_peer_status_chk(_adapter *adapter); + +#if CONFIG_RTW_MESH_ACNODE_PREVENT +void rtw_mesh_update_scanned_acnode_status(_adapter *adapter, struct wlan_network *scanned); +bool rtw_mesh_scanned_is_acnode_confirmed(_adapter *adapter, struct wlan_network *scanned); +bool rtw_mesh_acnode_prevent_allow_sacrifice(_adapter *adapter); +struct sta_info *rtw_mesh_acnode_prevent_pick_sacrifice(_adapter *adapter); +void dump_mesh_acnode_prevent_settings(void *sel, _adapter *adapter); +#endif + +#if CONFIG_RTW_MESH_OFFCH_CAND +u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter); +u8 rtw_mesh_select_operating_ch(_adapter *adapter); +void dump_mesh_offch_cand_settings(void *sel, _adapter *adapter); +#endif + +#if CONFIG_RTW_MESH_PEER_BLACKLIST +int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr); +int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr); +int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr); +void rtw_mesh_peer_blacklist_flush(_adapter *adapter); +void dump_mesh_peer_blacklist(void *sel, _adapter *adapter); +void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter); +#endif +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST +u8 rtw_mesh_cto_mgate_required(_adapter *adapter); +u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned); +int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr); +int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr); +int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr); +void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter); +void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter); +void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter); +#endif +void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter); +void dump_mesh_networks(void *sel, _adapter *adapter); + +void rtw_mesh_adjust_chbw(u8 req_ch, u8 *req_bw, u8 *req_offset); + +int rtw_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx); +int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len); +int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len); + +int rtw_mesh_on_auth(_adapter *adapter, union recv_frame *rframe); +unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe); + +bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss); +bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss); +bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss); + +struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr); +struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr); +struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx); +int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr); +int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr); +int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state); +#ifdef CONFIG_RTW_MESH_AEK +int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek); +#endif +#if CONFIG_RTW_MESH_PEER_BLACKLIST +int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr); +#endif +void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent); +int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr); +void rtw_mesh_plink_ctl_init(_adapter *adapter); +void rtw_mesh_plink_ctl_deinit(_adapter *adapter); +void dump_mesh_plink_ctl(void *sel, _adapter *adapter); + +int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta); +void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink); +void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr); +u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps); + +unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe); + +void rtw_mesh_cfg_init(_adapter *adapter); +void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf); +void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf); +void rtw_mesh_init_mesh_info(_adapter *adapter); +void rtw_mesh_deinit_mesh_info(_adapter *adapter); + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC +void dump_mesh_b2u_flags(void *sel, _adapter *adapter); +#endif + +int rtw_mesh_addr_resolve(_adapter *adapter, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list); + +s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib); +void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf); +u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib + , u16 *fctrl, struct rtw_ieee80211_hdr *whdr); + +int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta); +int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe + , const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa + , u8 *mctrl_len, const u8 **da, const u8 **sa); +int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe); + +int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe + , const u8 *mda, const u8 *msa + , const u8 *da, const u8 *sa + , struct rtw_ieee80211s_hdr *mctrl + , struct xmit_frame **fwd_frame, _list *b2u_list); + +void dump_mesh_stats(void *sel, _adapter *adapter); + +#if defined(PLATFORM_LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)) +#define rtw_lockdep_assert_held(l) lockdep_assert_held(l) +#define rtw_lockdep_is_held(l) lockdep_is_held(l) +#else +#error "TBD\n" +#endif + +#include "rtw_mesh_pathtbl.h" +#include "rtw_mesh_hwmp.h" +#endif /* __RTW_MESH_H_ */ + diff --git a/core/mesh/rtw_mesh_hwmp.c b/core/mesh/rtw_mesh_hwmp.c new file mode 100644 index 0000000..f64aa3d --- /dev/null +++ b/core/mesh/rtw_mesh_hwmp.c @@ -0,0 +1,1665 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_HWMP_C_ + +#ifdef CONFIG_RTW_MESH +#include +#include + +#define RTW_TEST_FRAME_LEN 8192 +#define RTW_MAX_METRIC 0xffffffff +#define RTW_ARITH_SHIFT 8 +#define RTW_LINK_FAIL_THRESH 95 +#define RTW_MAX_PREQ_QUEUE_LEN 64 +#define RTW_ATLM_REQ_CYCLE 1000 + +#define rtw_ilog2(n) \ +( \ + (n) < 2 ? 0 : \ + (n) & (1ULL << 63) ? 63 : \ + (n) & (1ULL << 62) ? 62 : \ + (n) & (1ULL << 61) ? 61 : \ + (n) & (1ULL << 60) ? 60 : \ + (n) & (1ULL << 59) ? 59 : \ + (n) & (1ULL << 58) ? 58 : \ + (n) & (1ULL << 57) ? 57 : \ + (n) & (1ULL << 56) ? 56 : \ + (n) & (1ULL << 55) ? 55 : \ + (n) & (1ULL << 54) ? 54 : \ + (n) & (1ULL << 53) ? 53 : \ + (n) & (1ULL << 52) ? 52 : \ + (n) & (1ULL << 51) ? 51 : \ + (n) & (1ULL << 50) ? 50 : \ + (n) & (1ULL << 49) ? 49 : \ + (n) & (1ULL << 48) ? 48 : \ + (n) & (1ULL << 47) ? 47 : \ + (n) & (1ULL << 46) ? 46 : \ + (n) & (1ULL << 45) ? 45 : \ + (n) & (1ULL << 44) ? 44 : \ + (n) & (1ULL << 43) ? 43 : \ + (n) & (1ULL << 42) ? 42 : \ + (n) & (1ULL << 41) ? 41 : \ + (n) & (1ULL << 40) ? 40 : \ + (n) & (1ULL << 39) ? 39 : \ + (n) & (1ULL << 38) ? 38 : \ + (n) & (1ULL << 37) ? 37 : \ + (n) & (1ULL << 36) ? 36 : \ + (n) & (1ULL << 35) ? 35 : \ + (n) & (1ULL << 34) ? 34 : \ + (n) & (1ULL << 33) ? 33 : \ + (n) & (1ULL << 32) ? 32 : \ + (n) & (1ULL << 31) ? 31 : \ + (n) & (1ULL << 30) ? 30 : \ + (n) & (1ULL << 29) ? 29 : \ + (n) & (1ULL << 28) ? 28 : \ + (n) & (1ULL << 27) ? 27 : \ + (n) & (1ULL << 26) ? 26 : \ + (n) & (1ULL << 25) ? 25 : \ + (n) & (1ULL << 24) ? 24 : \ + (n) & (1ULL << 23) ? 23 : \ + (n) & (1ULL << 22) ? 22 : \ + (n) & (1ULL << 21) ? 21 : \ + (n) & (1ULL << 20) ? 20 : \ + (n) & (1ULL << 19) ? 19 : \ + (n) & (1ULL << 18) ? 18 : \ + (n) & (1ULL << 17) ? 17 : \ + (n) & (1ULL << 16) ? 16 : \ + (n) & (1ULL << 15) ? 15 : \ + (n) & (1ULL << 14) ? 14 : \ + (n) & (1ULL << 13) ? 13 : \ + (n) & (1ULL << 12) ? 12 : \ + (n) & (1ULL << 11) ? 11 : \ + (n) & (1ULL << 10) ? 10 : \ + (n) & (1ULL << 9) ? 9 : \ + (n) & (1ULL << 8) ? 8 : \ + (n) & (1ULL << 7) ? 7 : \ + (n) & (1ULL << 6) ? 6 : \ + (n) & (1ULL << 5) ? 5 : \ + (n) & (1ULL << 4) ? 4 : \ + (n) & (1ULL << 3) ? 3 : \ + (n) & (1ULL << 2) ? 2 : \ + 1 \ +) + +enum rtw_mpath_frame_type { + RTW_MPATH_PREQ = 0, + RTW_MPATH_PREP, + RTW_MPATH_PERR, + RTW_MPATH_RANN +}; + +static inline u32 rtw_u32_field_get(const u8 *preq_elem, int shift, BOOLEAN ae) +{ + if (ae) + shift += 6; + return LE_BITS_TO_4BYTE(preq_elem + shift, 0, 32); +} + +static inline u16 rtw_u16_field_get(const u8 *preq_elem, int shift, BOOLEAN ae) +{ + if (ae) + shift += 6; + return LE_BITS_TO_2BYTE(preq_elem + shift, 0, 16); +} + +/* HWMP IE processing macros */ +#define RTW_AE_F (1<<6) +#define RTW_AE_F_SET(x) (*x & RTW_AE_F) +#define RTW_PREQ_IE_FLAGS(x) (*(x)) +#define RTW_PREQ_IE_HOPCOUNT(x) (*(x + 1)) +#define RTW_PREQ_IE_TTL(x) (*(x + 2)) +#define RTW_PREQ_IE_PREQ_ID(x) rtw_u32_field_get(x, 3, 0) +#define RTW_PREQ_IE_ORIG_ADDR(x) (x + 7) +#define RTW_PREQ_IE_ORIG_SN(x) rtw_u32_field_get(x, 13, 0) +#define RTW_PREQ_IE_LIFETIME(x) rtw_u32_field_get(x, 17, RTW_AE_F_SET(x)) +#define RTW_PREQ_IE_METRIC(x) rtw_u32_field_get(x, 21, RTW_AE_F_SET(x)) +#define RTW_PREQ_IE_TARGET_F(x) (*(RTW_AE_F_SET(x) ? x + 32 : x + 26)) +#define RTW_PREQ_IE_TARGET_ADDR(x) (RTW_AE_F_SET(x) ? x + 33 : x + 27) +#define RTW_PREQ_IE_TARGET_SN(x) rtw_u32_field_get(x, 33, RTW_AE_F_SET(x)) + +#define RTW_PREP_IE_FLAGS(x) RTW_PREQ_IE_FLAGS(x) +#define RTW_PREP_IE_HOPCOUNT(x) RTW_PREQ_IE_HOPCOUNT(x) +#define RTW_PREP_IE_TTL(x) RTW_PREQ_IE_TTL(x) +#define RTW_PREP_IE_ORIG_ADDR(x) (RTW_AE_F_SET(x) ? x + 27 : x + 21) +#define RTW_PREP_IE_ORIG_SN(x) rtw_u32_field_get(x, 27, RTW_AE_F_SET(x)) +#define RTW_PREP_IE_LIFETIME(x) rtw_u32_field_get(x, 13, RTW_AE_F_SET(x)) +#define RTW_PREP_IE_METRIC(x) rtw_u32_field_get(x, 17, RTW_AE_F_SET(x)) +#define RTW_PREP_IE_TARGET_ADDR(x) (x + 3) +#define RTW_PREP_IE_TARGET_SN(x) rtw_u32_field_get(x, 9, 0) + +#define RTW_PERR_IE_TTL(x) (*(x)) +#define RTW_PERR_IE_TARGET_FLAGS(x) (*(x + 2)) +#define RTW_PERR_IE_TARGET_ADDR(x) (x + 3) +#define RTW_PERR_IE_TARGET_SN(x) rtw_u32_field_get(x, 9, 0) +#define RTW_PERR_IE_TARGET_RCODE(x) rtw_u16_field_get(x, 13, 0) + +#define RTW_TU_TO_SYSTIME(x) (rtw_us_to_systime((x) * 1024)) +#define RTW_TU_TO_EXP_TIME(x) (rtw_get_current_time() + RTW_TU_TO_SYSTIME(x)) +#define RTW_MSEC_TO_TU(x) (x*1000/1024) +#define RTW_SN_GT(x, y) ((s32)(y - x) < 0) +#define RTW_SN_LT(x, y) ((s32)(x - y) < 0) +#define RTW_MAX_SANE_SN_DELTA 32 + +static inline u32 RTW_SN_DELTA(u32 x, u32 y) +{ + return x >= y ? x - y : y - x; +} + +#define rtw_net_traversal_jiffies(adapter) \ + rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPnetDiameterTraversalTime) +#define rtw_default_lifetime(adapter) \ + RTW_MSEC_TO_TU(adapter->mesh_cfg.dot11MeshHWMPactivePathTimeout) +#define rtw_min_preq_int_jiff(adapter) \ + (rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPpreqMinInterval)) +#define rtw_max_preq_retries(adapter) (adapter->mesh_cfg.dot11MeshHWMPmaxPREQretries) +#define rtw_disc_timeout_jiff(adapter) \ + rtw_ms_to_systime(adapter->mesh_cfg.min_discovery_timeout) +#define rtw_root_path_confirmation_jiffies(adapter) \ + rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPconfirmationInterval) + +static inline BOOLEAN rtw_ether_addr_equal(const u8 *addr1, const u8 *addr2) +{ + return _rtw_memcmp(addr1, addr2, ETH_ALEN); +} + +#ifdef PLATFORM_LINUX +#define rtw_print_ratelimit() printk_ratelimit() +#define rtw_mod_timer(ptimer, expires) mod_timer(&(ptimer)->timer, expires) +#else + +#endif + +#define RTW_MESH_EWMA_PRECISION 20 +#define RTW_MESH_EWMA_WEIGHT_RCP 8 +#define RTW_TOTAL_PKT_MIN_THRESHOLD 1 +inline void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e) +{ + e->internal = 0; +} +inline unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e) +{ + return e->internal >> (RTW_MESH_EWMA_PRECISION); +} +inline void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e, + unsigned long val) +{ + unsigned long internal = e->internal; + unsigned long weight_rcp = rtw_ilog2(RTW_MESH_EWMA_WEIGHT_RCP); + unsigned long precision = RTW_MESH_EWMA_PRECISION; + + (e->internal) = internal ? (((internal << weight_rcp) - internal) + + (val << precision)) >> weight_rcp : + (val << precision); +} + +static const u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + +static int rtw_mesh_path_sel_frame_tx(enum rtw_mpath_frame_type mpath_action, u8 flags, + const u8 *originator_addr, u32 originator_sn, + u8 target_flags, const u8 *target, + u32 target_sn, const u8 *da, u8 hopcount, u8 ttl, + u32 lifetime, u32 metric, u32 preq_id, + _adapter *adapter) +{ + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + struct xmit_frame *pmgntframe = NULL; + struct rtw_ieee80211_hdr *pwlanhdr = NULL; + struct pkt_attrib *pattrib = NULL; + u8 category = RTW_WLAN_CATEGORY_MESH; + u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION; + u16 *fctrl = NULL; + u8 *pos, ie_len; + + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return -1; + + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapter, pattrib); + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pos; + + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pos, WIFI_ACTION); + + pos += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen)); + pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen)); + + switch (mpath_action) { + case RTW_MPATH_PREQ: + RTW_HWMP_DBG("sending PREQ to "MAC_FMT"\n", MAC_ARG(target)); + ie_len = 37; + pattrib->pktlen += (ie_len + 2); + *pos++ = WLAN_EID_PREQ; + break; + case RTW_MPATH_PREP: + RTW_HWMP_DBG("sending PREP to "MAC_FMT"\n", MAC_ARG(originator_addr)); + ie_len = 31; + pattrib->pktlen += (ie_len + 2); + *pos++ = WLAN_EID_PREP; + break; + case RTW_MPATH_RANN: + RTW_HWMP_DBG("sending RANN from "MAC_FMT"\n", MAC_ARG(originator_addr)); + ie_len = sizeof(struct rtw_ieee80211_rann_ie); + pattrib->pktlen += (ie_len + 2); + *pos++ = WLAN_EID_RANN; + break; + default: + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + return _FAIL; + } + *pos++ = ie_len; + *pos++ = flags; + *pos++ = hopcount; + *pos++ = ttl; + if (mpath_action == RTW_MPATH_PREP) { + _rtw_memcpy(pos, target, ETH_ALEN); + pos += ETH_ALEN; + *(u32 *)pos = cpu_to_le32(target_sn); + pos += 4; + } else { + if (mpath_action == RTW_MPATH_PREQ) { + *(u32 *)pos = cpu_to_le32(preq_id); + pos += 4; + } + _rtw_memcpy(pos, originator_addr, ETH_ALEN); + pos += ETH_ALEN; + *(u32 *)pos = cpu_to_le32(originator_sn); + pos += 4; + } + *(u32 *)pos = cpu_to_le32(lifetime); + pos += 4; + *(u32 *)pos = cpu_to_le32(metric); + pos += 4; + if (mpath_action == RTW_MPATH_PREQ) { + *pos++ = 1; /* support only 1 destination now */ + *pos++ = target_flags; + _rtw_memcpy(pos, target, ETH_ALEN); + pos += ETH_ALEN; + *(u32 *)pos = cpu_to_le32(target_sn); + pos += 4; + } else if (mpath_action == RTW_MPATH_PREP) { + _rtw_memcpy(pos, originator_addr, ETH_ALEN); + pos += ETH_ALEN; + *(u32 *)pos = cpu_to_le32(originator_sn); + pos += 4; + } + + pattrib->last_txcmdsz = pattrib->pktlen; + dump_mgntframe(adapter, pmgntframe); + return 0; +} + +int rtw_mesh_path_error_tx(_adapter *adapter, + u8 ttl, const u8 *target, u32 target_sn, + u16 perr_reason_code, const u8 *ra) +{ + + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + struct xmit_frame *pmgntframe = NULL; + struct rtw_ieee80211_hdr *pwlanhdr = NULL; + struct pkt_attrib *pattrib = NULL; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + u8 category = RTW_WLAN_CATEGORY_MESH; + u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION; + u8 *pos, ie_len; + u16 *fctrl = NULL; + + if (rtw_time_before(rtw_get_current_time(), minfo->next_perr)) + return -1; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return -1; + + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapter, pattrib); + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pos; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pos, WIFI_ACTION); + + pos += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen)); + pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen)); + + ie_len = 15; + pattrib->pktlen += (2 + ie_len); + *pos++ = WLAN_EID_PERR; + *pos++ = ie_len; + /* ttl */ + *pos++ = ttl; + /* The Number of Destinations N */ + *pos++ = 1; + /* Flags format | B7 | B6 | B5:B0 | = | rsvd | AE | rsvd | */ + *pos = 0; + pos++; + _rtw_memcpy(pos, target, ETH_ALEN); + pos += ETH_ALEN; + *(u32 *)pos = cpu_to_le32(target_sn); + pos += 4; + *(u16 *)pos = cpu_to_le16(perr_reason_code); + + adapter->mesh_info.next_perr = RTW_TU_TO_EXP_TIME( + adapter->mesh_cfg.dot11MeshHWMPperrMinInterval); + pattrib->last_txcmdsz = pattrib->pktlen; + /* Send directly. Rewrite it if deferred tx is needed */ + dump_mgntframe(adapter, pmgntframe); + + RTW_HWMP_DBG("TX PERR toward "MAC_FMT", ra = "MAC_FMT"\n", MAC_ARG(target), MAC_ARG(ra)); + + return 0; +} + +static u32 rtw_get_vht_bitrate(u8 mcs, u8 bw, u8 nss, u8 sgi) +{ + static const u32 base[4][10] = { + { 6500000, + 13000000, + 19500000, + 26000000, + 39000000, + 52000000, + 58500000, + 65000000, + 78000000, + /* not in the spec, but some devices use this: */ + 86500000, + }, + { 13500000, + 27000000, + 40500000, + 54000000, + 81000000, + 108000000, + 121500000, + 135000000, + 162000000, + 180000000, + }, + { 29300000, + 58500000, + 87800000, + 117000000, + 175500000, + 234000000, + 263300000, + 292500000, + 351000000, + 390000000, + }, + { 58500000, + 117000000, + 175500000, + 234000000, + 351000000, + 468000000, + 526500000, + 585000000, + 702000000, + 780000000, + }, + }; + u32 bitrate; + int bw_idx; + + if (mcs > 9) { + RTW_HWMP_INFO("Invalid mcs = %d\n", mcs); + return 0; + } + + if (nss > 4 || nss < 1) { + RTW_HWMP_INFO("Now only support nss = 1, 2, 3, 4\n"); + } + + switch (bw) { + case CHANNEL_WIDTH_160: + bw_idx = 3; + break; + case CHANNEL_WIDTH_80: + bw_idx = 2; + break; + case CHANNEL_WIDTH_40: + bw_idx = 1; + break; + case CHANNEL_WIDTH_20: + bw_idx = 0; + break; + default: + RTW_HWMP_INFO("bw = %d currently not supported\n", bw); + return 0; + } + + bitrate = base[bw_idx][mcs]; + bitrate *= nss; + + if (sgi) + bitrate = (bitrate / 9) * 10; + + /* do NOT round down here */ + return (bitrate + 50000) / 100000; +} + +static u32 rtw_get_ht_bitrate(u8 mcs, u8 bw, u8 sgi) +{ + int modulation, streams, bitrate; + + /* the formula below does only work for MCS values smaller than 32 */ + if (mcs >= 32) { + RTW_HWMP_INFO("Invalid mcs = %d\n", mcs); + return 0; + } + + if (bw > 1) { + RTW_HWMP_INFO("Now HT only support bw = 0(20Mhz), 1(40Mhz)\n"); + return 0; + } + + modulation = mcs & 7; + streams = (mcs >> 3) + 1; + + bitrate = (bw == 1) ? 13500000 : 6500000; + + if (modulation < 4) + bitrate *= (modulation + 1); + else if (modulation == 4) + bitrate *= (modulation + 2); + else + bitrate *= (modulation + 3); + + bitrate *= streams; + + if (sgi) + bitrate = (bitrate / 9) * 10; + + /* do NOT round down here */ + return (bitrate + 50000) / 100000; +} + +/** + * @bw: 0(20Mhz), 1(40Mhz), 2(80Mhz), 3(160Mhz) + * @rate_idx: DESC_RATEXXXX & 0x7f + * @sgi: DESC_RATEXXXX >> 7 + * Returns: bitrate in 100kbps + */ +static u32 rtw_desc_rate_to_bitrate(u8 bw, u8 rate_idx, u8 sgi) +{ + u32 bitrate; + + if (rate_idx <= DESC_RATE54M){ + u16 ofdm_rate[12] = {10, 20, 55, 110, + 60, 90, 120, 180, 240, 360, 480, 540}; + bitrate = ofdm_rate[rate_idx]; + } else if ((DESC_RATEMCS0 <= rate_idx) && + (rate_idx <= DESC_RATEMCS31)) { + u8 mcs = rate_idx - DESC_RATEMCS0; + bitrate = rtw_get_ht_bitrate(mcs, bw, sgi); + } else if ((DESC_RATEVHTSS1MCS0 <= rate_idx) && + (rate_idx <= DESC_RATEVHTSS4MCS9)) { + u8 mcs = (rate_idx - DESC_RATEVHTSS1MCS0) % 10; + u8 nss = ((rate_idx - DESC_RATEVHTSS1MCS0) / 10) + 1; + bitrate = rtw_get_vht_bitrate(mcs, bw, nss, sgi); + } else { + /* 60Ghz ??? */ + bitrate = 1; + } + + return bitrate; +} + +static u32 rtw_airtime_link_metric_get(_adapter *adapter, struct sta_info *sta) +{ + struct dm_struct *dm = adapter_to_phydm(adapter); + int device_constant = phydm_get_plcp(dm, sta->cmn.mac_id) << RTW_ARITH_SHIFT; + u32 test_frame_len = RTW_TEST_FRAME_LEN << RTW_ARITH_SHIFT; + u32 s_unit = 1 << RTW_ARITH_SHIFT; + u32 err; + u16 rate; + u32 tx_time, estimated_retx; + u64 result; + /* The fail_avg should <= 100 here */ + u32 fail_avg = (u32)rtw_ewma_err_rate_read(&sta->metrics.err_rate); + + if (fail_avg > RTW_LINK_FAIL_THRESH) + return RTW_MAX_METRIC; + + rate = sta->metrics.data_rate; + /* rate unit is 100Kbps, min rate = 10 */ + if (rate < 10) { + RTW_HWMP_INFO("rate = %d\n", rate); + return RTW_MAX_METRIC; + } + + err = (fail_avg << RTW_ARITH_SHIFT) / 100; + + /* test_frame_len*10 to adjust the unit of rate(100kbps/unit) */ + tx_time = (device_constant + 10 * test_frame_len / rate); + estimated_retx = ((1 << (2 * RTW_ARITH_SHIFT)) / (s_unit - err)); + result = (tx_time * estimated_retx) >> (2 * RTW_ARITH_SHIFT); + /* Convert us to 0.01 TU(10.24us). x/10.24 = x*100/1024 */ + result = (result * 100) >> 10; + + return (u32)result; +} + +void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id, + u8 per, u8 rate, + u8 bw, u8 total_pkt) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct sta_info *sta; + u8 rate_idx; + u8 sgi; + + sta = macid_ctl->sta[mac_id]; + if (!sta) + return; + + /* if RA, use reported rate */ + if (adapter->fix_rate == 0xff) { + rate_idx = rate & 0x7f; + sgi = rate >> 7; + } else { + rate_idx = adapter->fix_rate & 0x7f; + sgi = adapter->fix_rate >> 7; + } + sta->metrics.data_rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi); + + if (total_pkt < RTW_TOTAL_PKT_MIN_THRESHOLD) + return; + + /* TBD: sta->metrics.overhead = phydm_get_plcp(void *dm_void, u16 macid); */ + sta->metrics.total_pkt = total_pkt; + + rtw_ewma_err_rate_add(&sta->metrics.err_rate, per); + if (rtw_ewma_err_rate_read(&sta->metrics.err_rate) > + RTW_LINK_FAIL_THRESH) + rtw_mesh_plink_broken(sta); +} + +static void rtw_hwmp_preq_frame_process(_adapter *adapter, + struct rtw_ieee80211_hdr_3addr *mgmt, + const u8 *preq_elem, u32 originator_metric) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_path *path = NULL; + const u8 *target_addr, *originator_addr; + const u8 *da; + u8 target_flags, ttl, flags, to_gate_ask = 0; + u32 originator_sn, target_sn, lifetime, target_metric = 0; + BOOLEAN reply = _FALSE; + BOOLEAN forward = _TRUE; + BOOLEAN preq_is_gate; + + /* Update target SN, if present */ + target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem); + originator_addr = RTW_PREQ_IE_ORIG_ADDR(preq_elem); + target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem); + originator_sn = RTW_PREQ_IE_ORIG_SN(preq_elem); + target_flags = RTW_PREQ_IE_TARGET_F(preq_elem); + /* PREQ gate announcements */ + flags = RTW_PREQ_IE_FLAGS(preq_elem); + preq_is_gate = !!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG); + + RTW_HWMP_DBG("received PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr)); + + if (rtw_ether_addr_equal(target_addr, adapter_mac_addr(adapter))) { + RTW_HWMP_DBG("PREQ is for us\n"); +#ifdef CONFIG_RTW_MESH_ON_DMD_GANN + rtw_rcu_read_lock(); + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (path) { + if (preq_is_gate) + rtw_mesh_path_add_gate(path); + else if (path->is_gate) { + enter_critical_bh(&path->state_lock); + rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); + exit_critical_bh(&path->state_lock); + } + } + path = NULL; + rtw_rcu_read_unlock(); +#endif + forward = _FALSE; + reply = _TRUE; + to_gate_ask = 1; + target_metric = 0; + if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update + + rtw_net_traversal_jiffies(adapter)) || + rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) { + ++minfo->sn; + minfo->last_sn_update = rtw_get_current_time(); + } + target_sn = minfo->sn; + } else if (is_broadcast_mac_addr(target_addr) && + (target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) { + rtw_rcu_read_lock(); + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (path) { + if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) { + reply = _TRUE; + target_addr = adapter_mac_addr(adapter); + target_sn = ++minfo->sn; + target_metric = 0; + minfo->last_sn_update = rtw_get_current_time(); + } + + if (preq_is_gate) { + lifetime = RTW_PREQ_IE_LIFETIME(preq_elem); + path->gate_ann_int = lifetime; + path->gate_asked = false; + rtw_mesh_path_add_gate(path); + } else if (path->is_gate) { + enter_critical_bh(&path->state_lock); + rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); + exit_critical_bh(&path->state_lock); + } + } + rtw_rcu_read_unlock(); + } else { + rtw_rcu_read_lock(); +#ifdef CONFIG_RTW_MESH_ON_DMD_GANN + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (path) { + if (preq_is_gate) + rtw_mesh_path_add_gate(path); + else if (path->is_gate) { + enter_critical_bh(&path->state_lock); + rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); + exit_critical_bh(&path->state_lock); + } + } + path = NULL; +#endif + path = rtw_mesh_path_lookup(adapter, target_addr); + if (path) { + if ((!(path->flags & RTW_MESH_PATH_SN_VALID)) || + RTW_SN_LT(path->sn, target_sn)) { + path->sn = target_sn; + path->flags |= RTW_MESH_PATH_SN_VALID; + } else if ((!(target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) && + (path->flags & RTW_MESH_PATH_ACTIVE)) { + reply = _TRUE; + target_metric = path->metric; + target_sn = path->sn; + /* Case E2 of sec 13.10.9.3 IEEE 802.11-2012*/ + target_flags |= RTW_IEEE80211_PREQ_TO_FLAG; + } + } + rtw_rcu_read_unlock(); + } + + if (reply) { + lifetime = RTW_PREQ_IE_LIFETIME(preq_elem); + ttl = mshcfg->element_ttl; + if (ttl != 0 && !to_gate_ask) { + RTW_HWMP_DBG("replying to the PREQ\n"); + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, 0, originator_addr, + originator_sn, 0, target_addr, + target_sn, mgmt->addr2, 0, ttl, + lifetime, target_metric, 0, + adapter); + } else if (ttl != 0 && to_gate_ask) { + RTW_HWMP_DBG("replying to the PREQ (PREQ for us)\n"); + if (mshcfg->dot11MeshGateAnnouncementProtocol) { + /* BIT 7 is used to identify the prep is from mesh gate */ + to_gate_ask = RTW_IEEE80211_PREQ_IS_GATE_FLAG | BIT(7); + } else { + to_gate_ask = 0; + } + + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, to_gate_ask, originator_addr, + originator_sn, 0, target_addr, + target_sn, mgmt->addr2, 0, ttl, + lifetime, target_metric, 0, + adapter); + } else { + minfo->mshstats.dropped_frames_ttl++; + } + } + + if (forward && mshcfg->dot11MeshForwarding) { + u32 preq_id; + u8 hopcount; + + ttl = RTW_PREQ_IE_TTL(preq_elem); + lifetime = RTW_PREQ_IE_LIFETIME(preq_elem); + if (ttl <= 1) { + minfo->mshstats.dropped_frames_ttl++; + return; + } + RTW_HWMP_DBG("forwarding the PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr)); + --ttl; + preq_id = RTW_PREQ_IE_PREQ_ID(preq_elem); + hopcount = RTW_PREQ_IE_HOPCOUNT(preq_elem) + 1; + da = (path && path->is_root) ? + path->rann_snd_addr : bcast_addr; + + if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) { + target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem); + target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem); + } + + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, originator_addr, + originator_sn, target_flags, target_addr, + target_sn, da, hopcount, ttl, lifetime, + originator_metric, preq_id, adapter); + if (!is_multicast_mac_addr(da)) + minfo->mshstats.fwded_unicast++; + else + minfo->mshstats.fwded_mcast++; + minfo->mshstats.fwded_frames++; + } +} + +static inline struct sta_info * +rtw_next_hop_deref_protected(struct rtw_mesh_path *path) +{ + return rtw_rcu_dereference_protected(path->next_hop, + rtw_lockdep_is_held(&path->state_lock)); +} + +static void rtw_hwmp_prep_frame_process(_adapter *adapter, + struct rtw_ieee80211_hdr_3addr *mgmt, + const u8 *prep_elem, u32 metric) +{ + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats; + struct rtw_mesh_path *path; + const u8 *target_addr, *originator_addr; + u8 ttl, hopcount, flags; + u8 next_hop[ETH_ALEN]; + u32 target_sn, originator_sn, lifetime; + + RTW_HWMP_DBG("received PREP from "MAC_FMT"\n", + MAC_ARG(RTW_PREP_IE_TARGET_ADDR(prep_elem))); + + originator_addr = RTW_PREP_IE_ORIG_ADDR(prep_elem); + if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) { + /* destination, no forwarding required */ + rtw_rcu_read_lock(); + target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem); + path = rtw_mesh_path_lookup(adapter, target_addr); + if (path && path->gate_asked) { + flags = RTW_PREP_IE_FLAGS(prep_elem); + if (flags & BIT(7)) { + enter_critical_bh(&path->state_lock); + path->gate_asked = false; + exit_critical_bh(&path->state_lock); + if (!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG)) { + enter_critical_bh(&path->state_lock); + rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); + exit_critical_bh(&path->state_lock); + } + } + } + + rtw_rcu_read_unlock(); + return; + } + + if (!mshcfg->dot11MeshForwarding) + return; + + ttl = RTW_PREP_IE_TTL(prep_elem); + if (ttl <= 1) { + mshstats->dropped_frames_ttl++; + return; + } + + rtw_rcu_read_lock(); + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (path) + enter_critical_bh(&path->state_lock); + else + goto fail; + if (!(path->flags & RTW_MESH_PATH_ACTIVE)) { + exit_critical_bh(&path->state_lock); + goto fail; + } + _rtw_memcpy(next_hop, rtw_next_hop_deref_protected(path)->cmn.mac_addr, ETH_ALEN); + exit_critical_bh(&path->state_lock); + --ttl; + flags = RTW_PREP_IE_FLAGS(prep_elem); + lifetime = RTW_PREP_IE_LIFETIME(prep_elem); + hopcount = RTW_PREP_IE_HOPCOUNT(prep_elem) + 1; + target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem); + target_sn = RTW_PREP_IE_TARGET_SN(prep_elem); + originator_sn = RTW_PREP_IE_ORIG_SN(prep_elem); + + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, flags, originator_addr, originator_sn, 0, + target_addr, target_sn, next_hop, hopcount, + ttl, lifetime, metric, 0, adapter); + rtw_rcu_read_unlock(); + + mshstats->fwded_unicast++; + mshstats->fwded_frames++; + return; + +fail: + rtw_rcu_read_unlock(); + mshstats->dropped_frames_no_route++; +} + +static void rtw_hwmp_perr_frame_process(_adapter *adapter, + struct rtw_ieee80211_hdr_3addr *mgmt, + const u8 *perr_elem) +{ + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats; + struct rtw_mesh_path *path; + u8 ttl; + const u8 *ta, *target_addr; + u32 target_sn; + u16 perr_reason_code; + + ta = mgmt->addr2; + ttl = RTW_PERR_IE_TTL(perr_elem); + if (ttl <= 1) { + mshstats->dropped_frames_ttl++; + return; + } + ttl--; + target_addr = RTW_PERR_IE_TARGET_ADDR(perr_elem); + target_sn = RTW_PERR_IE_TARGET_SN(perr_elem); + perr_reason_code = RTW_PERR_IE_TARGET_RCODE(perr_elem); + + RTW_HWMP_DBG("received PERR toward target "MAC_FMT"\n", MAC_ARG(target_addr)); + + rtw_rcu_read_lock(); + path = rtw_mesh_path_lookup(adapter, target_addr); + if (path) { + struct sta_info *sta; + + enter_critical_bh(&path->state_lock); + sta = rtw_next_hop_deref_protected(path); + if (path->flags & RTW_MESH_PATH_ACTIVE && + rtw_ether_addr_equal(ta, sta->cmn.mac_addr) && + !(path->flags & RTW_MESH_PATH_FIXED) && + (!(path->flags & RTW_MESH_PATH_SN_VALID) || + RTW_SN_GT(target_sn, path->sn) || target_sn == 0)) { + path->flags &= ~RTW_MESH_PATH_ACTIVE; + if (target_sn != 0) + path->sn = target_sn; + else + path->sn += 1; + exit_critical_bh(&path->state_lock); + if (!mshcfg->dot11MeshForwarding) + goto endperr; + rtw_mesh_path_error_tx(adapter, ttl, target_addr, + target_sn, perr_reason_code, + bcast_addr); + } else + exit_critical_bh(&path->state_lock); + } +endperr: + rtw_rcu_read_unlock(); +} + +static void rtw_hwmp_rann_frame_process(_adapter *adapter, + struct rtw_ieee80211_hdr_3addr *mgmt, + const struct rtw_ieee80211_rann_ie *rann) +{ + struct sta_info *sta; + struct sta_priv *pstapriv = &adapter->stapriv; + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats; + struct rtw_mesh_path *path; + u8 ttl, flags, hopcount; + const u8 *originator_addr; + u32 originator_sn, metric, metric_txsta, interval; + BOOLEAN root_is_gate; + + ttl = rann->rann_ttl; + flags = rann->rann_flags; + root_is_gate = !!(flags & RTW_RANN_FLAG_IS_GATE); + originator_addr = rann->rann_addr; + originator_sn = le32_to_cpu(rann->rann_seq); + interval = le32_to_cpu(rann->rann_interval); + hopcount = rann->rann_hopcount; + hopcount++; + metric = le32_to_cpu(rann->rann_metric); + + /* Ignore our own RANNs */ + if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) + return; + + RTW_HWMP_DBG("received RANN from "MAC_FMT" via neighbour "MAC_FMT" (is_gate=%d)\n", + MAC_ARG(originator_addr), MAC_ARG(mgmt->addr2), root_is_gate); + + rtw_rcu_read_lock(); + sta = rtw_get_stainfo(pstapriv, mgmt->addr2); + if (!sta) { + rtw_rcu_read_unlock(); + return; + } + + metric_txsta = rtw_airtime_link_metric_get(adapter, sta); + + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (!path) { + path = rtw_mesh_path_add(adapter, originator_addr); + if (IS_ERR(path)) { + rtw_rcu_read_unlock(); + mshstats->dropped_frames_no_route++; + return; + } + } + + if (!(RTW_SN_LT(path->sn, originator_sn)) && + !(path->sn == originator_sn && metric < path->rann_metric)) { + rtw_rcu_read_unlock(); + return; + } + + if ((!(path->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING)) || + (rtw_time_after(rtw_get_current_time(), path->last_preq_to_root + + rtw_root_path_confirmation_jiffies(adapter)) || + rtw_time_before(rtw_get_current_time(), path->last_preq_to_root))) && + !(path->flags & RTW_MESH_PATH_FIXED) && (ttl != 0)) { + u8 preq_node_flag = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH; + + RTW_HWMP_DBG("time to refresh root path "MAC_FMT"\n", + MAC_ARG(originator_addr)); +#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK + if (RTW_SN_LT(path->sn, originator_sn) && + (path->rann_metric + mshcfg->sane_metric_delta < metric) && + _rtw_memcmp(bcast_addr, path->rann_snd_addr, ETH_ALEN) == _FALSE) { + RTW_HWMP_DBG("Trigger additional check for root " + "confirm PREQ. rann_snd_addr = "MAC_FMT + "add_chk_rann_snd_addr= "MAC_FMT"\n", + MAC_ARG(mgmt->addr2), + MAC_ARG(path->rann_snd_addr)); + _rtw_memcpy(path->add_chk_rann_snd_addr, + path->rann_snd_addr, ETH_ALEN); + preq_node_flag |= RTW_PREQ_Q_F_CHK; + + } +#endif + rtw_mesh_queue_preq(path, preq_node_flag); + path->last_preq_to_root = rtw_get_current_time(); + } + + path->sn = originator_sn; + path->rann_metric = metric + metric_txsta; + path->is_root = _TRUE; + /* Recording RANNs sender address to send individually + * addressed PREQs destined for root mesh STA */ + _rtw_memcpy(path->rann_snd_addr, mgmt->addr2, ETH_ALEN); + + if (root_is_gate) { + path->gate_ann_int = interval; + path->gate_asked = false; + rtw_mesh_path_add_gate(path); + } else if (path->is_gate) { + enter_critical_bh(&path->state_lock); + rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path); + exit_critical_bh(&path->state_lock); + } + + if (ttl <= 1) { + mshstats->dropped_frames_ttl++; + rtw_rcu_read_unlock(); + return; + } + ttl--; + + if (mshcfg->dot11MeshForwarding) { + rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, originator_addr, + originator_sn, 0, NULL, 0, bcast_addr, + hopcount, ttl, interval, + metric + metric_txsta, 0, adapter); + } + + rtw_rcu_read_unlock(); +} + +static u32 rtw_hwmp_route_info_get(_adapter *adapter, + struct rtw_ieee80211_hdr_3addr *mgmt, + const u8 *hwmp_ie, enum rtw_mpath_frame_type action) +{ + struct rtw_mesh_path *path; + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *sta; + BOOLEAN fresh_info; + const u8 *originator_addr, *ta; + u32 originator_sn, originator_metric; + unsigned long originator_lifetime, exp_time; + u32 last_hop_metric, new_metric; + BOOLEAN process = _TRUE; + + rtw_rcu_read_lock(); + sta = rtw_get_stainfo(pstapriv, mgmt->addr2); + if (!sta) { + rtw_rcu_read_unlock(); + return 0; + } + + last_hop_metric = rtw_airtime_link_metric_get(adapter, sta); + /* Update and check originator routing info */ + fresh_info = _TRUE; + + switch (action) { + case RTW_MPATH_PREQ: + originator_addr = RTW_PREQ_IE_ORIG_ADDR(hwmp_ie); + originator_sn = RTW_PREQ_IE_ORIG_SN(hwmp_ie); + originator_lifetime = RTW_PREQ_IE_LIFETIME(hwmp_ie); + originator_metric = RTW_PREQ_IE_METRIC(hwmp_ie); + break; + case RTW_MPATH_PREP: + /* Note: For coding, the naming is not consist with spec */ + originator_addr = RTW_PREP_IE_TARGET_ADDR(hwmp_ie); + originator_sn = RTW_PREP_IE_TARGET_SN(hwmp_ie); + originator_lifetime = RTW_PREP_IE_LIFETIME(hwmp_ie); + originator_metric = RTW_PREP_IE_METRIC(hwmp_ie); + break; + default: + rtw_rcu_read_unlock(); + return 0; + } + new_metric = originator_metric + last_hop_metric; + if (new_metric < originator_metric) + new_metric = RTW_MAX_METRIC; + exp_time = RTW_TU_TO_EXP_TIME(originator_lifetime); + + if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) { + process = _FALSE; + fresh_info = _FALSE; + } else { + path = rtw_mesh_path_lookup(adapter, originator_addr); + if (path) { + enter_critical_bh(&path->state_lock); + if (path->flags & RTW_MESH_PATH_FIXED) + fresh_info = _FALSE; + else if ((path->flags & RTW_MESH_PATH_ACTIVE) && + (path->flags & RTW_MESH_PATH_SN_VALID)) { + if (RTW_SN_GT(path->sn, originator_sn) || + (path->sn == originator_sn && + new_metric >= path->metric)) { + process = _FALSE; + fresh_info = _FALSE; + } + } else if (!(path->flags & RTW_MESH_PATH_ACTIVE)) { + BOOLEAN have_sn, newer_sn, bounced; + + have_sn = path->flags & RTW_MESH_PATH_SN_VALID; + newer_sn = have_sn && RTW_SN_GT(originator_sn, path->sn); + bounced = have_sn && + (RTW_SN_DELTA(originator_sn, path->sn) > + RTW_MAX_SANE_SN_DELTA); + + if (!have_sn || newer_sn) { + } else if (bounced) { + } else { + process = _FALSE; + fresh_info = _FALSE; + } + } + } else { + path = rtw_mesh_path_add(adapter, originator_addr); + if (IS_ERR(path)) { + rtw_rcu_read_unlock(); + return 0; + } + enter_critical_bh(&path->state_lock); + } + + if (fresh_info) { + rtw_mesh_path_assign_nexthop(path, sta); + path->flags |= RTW_MESH_PATH_SN_VALID; + path->metric = new_metric; + path->sn = originator_sn; + path->exp_time = rtw_time_after(path->exp_time, exp_time) + ? path->exp_time : exp_time; + rtw_mesh_path_activate(path); +#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK + if (path->is_root && (action == RTW_MPATH_PREP)) { + _rtw_memcpy(path->rann_snd_addr, + mgmt->addr2, ETH_ALEN); + path->rann_metric = new_metric; + } +#endif + exit_critical_bh(&path->state_lock); + rtw_mesh_path_tx_pending(path); + } else + exit_critical_bh(&path->state_lock); + } + + /* Update and check transmitter routing info */ + ta = mgmt->addr2; + if (rtw_ether_addr_equal(originator_addr, ta)) + fresh_info = _FALSE; + else { + fresh_info = _TRUE; + + path = rtw_mesh_path_lookup(adapter, ta); + if (path) { + enter_critical_bh(&path->state_lock); + if ((path->flags & RTW_MESH_PATH_FIXED) || + ((path->flags & RTW_MESH_PATH_ACTIVE) && + (last_hop_metric > path->metric))) + fresh_info = _FALSE; + } else { + path = rtw_mesh_path_add(adapter, ta); + if (IS_ERR(path)) { + rtw_rcu_read_unlock(); + return 0; + } + enter_critical_bh(&path->state_lock); + } + + if (fresh_info) { + rtw_mesh_path_assign_nexthop(path, sta); + path->metric = last_hop_metric; + path->exp_time = rtw_time_after(path->exp_time, exp_time) + ? path->exp_time : exp_time; + rtw_mesh_path_activate(path); + exit_critical_bh(&path->state_lock); + rtw_mesh_path_tx_pending(path); + } else + exit_critical_bh(&path->state_lock); + } + + rtw_rcu_read_unlock(); + + return process ? new_metric : 0; +} + +static void rtw_mesh_rx_hwmp_frame_cnts(_adapter *adapter, u8 *addr) +{ + struct sta_info *sta; + + sta = rtw_get_stainfo(&adapter->stapriv, addr); + if (sta) + sta->sta_stats.rx_hwmp_pkts++; +} + +void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe) +{ + struct mesh_plink_ent *plink = NULL; + struct rtw_ieee802_11_elems elems; + u32 path_metric; + struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib; + u8 *pframe = rframe->u.hdr.rx_data, *start; + uint frame_len = rframe->u.hdr.len, left; + struct rtw_ieee80211_hdr_3addr *frame_hdr = (struct rtw_ieee80211_hdr_3addr *)pframe; + u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + ParseRes parse_res; + + plink = rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe)); + if (!plink || plink->plink_state != RTW_MESH_PLINK_ESTAB) + return; + + rtw_mesh_rx_hwmp_frame_cnts(adapter, get_addr2_ptr(pframe)); + + /* Mesh action frame IE offset = 2 */ + attrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + left = frame_len - attrib->hdrlen - attrib->iv_len - attrib->icv_len - 2; + start = pframe + attrib->hdrlen + 2; + + parse_res = rtw_ieee802_11_parse_elems(start, left, &elems, 1); + if (parse_res == ParseFailed) + RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseFailed\n" + , FUNC_ADPT_ARG(adapter)); + else if (parse_res == ParseUnknown) + RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseUnknown\n" + , FUNC_ADPT_ARG(adapter)); + + if (elems.preq) { + if (elems.preq_len != 37) + /* Right now we support just 1 destination and no AE */ + return; + path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.preq, + MPATH_PREQ); + if (path_metric) + rtw_hwmp_preq_frame_process(adapter, frame_hdr, elems.preq, + path_metric); + } + if (elems.prep) { + if (elems.prep_len != 31) + /* Right now we support no AE */ + return; + path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.prep, + MPATH_PREP); + if (path_metric) + rtw_hwmp_prep_frame_process(adapter, frame_hdr, elems.prep, + path_metric); + } + if (elems.perr) { + if (elems.perr_len != 15) + /* Right now we support only one destination per PERR */ + return; + rtw_hwmp_perr_frame_process(adapter, frame_hdr, elems.perr); + } + if (elems.rann) + rtw_hwmp_rann_frame_process(adapter, frame_hdr, (struct rtw_ieee80211_rann_ie *)elems.rann); +} + +void rtw_mesh_queue_preq(struct rtw_mesh_path *path, u8 flags) +{ + _adapter *adapter = path->adapter; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_preq_queue *preq_node; + + preq_node = rtw_malloc(sizeof(struct rtw_mesh_preq_queue)); + if (!preq_node) { + RTW_HWMP_INFO("could not allocate PREQ node\n"); + return; + } + + enter_critical_bh(&minfo->mesh_preq_queue_lock); + if (minfo->preq_queue_len == RTW_MAX_PREQ_QUEUE_LEN) { + exit_critical_bh(&minfo->mesh_preq_queue_lock); + rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue)); + if (rtw_print_ratelimit()) + RTW_HWMP_INFO("PREQ node queue full\n"); + return; + } + + _rtw_spinlock(&path->state_lock); + if (path->flags & RTW_MESH_PATH_REQ_QUEUED) { + _rtw_spinunlock(&path->state_lock); + exit_critical_bh(&minfo->mesh_preq_queue_lock); + rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue)); + return; + } + + _rtw_memcpy(preq_node->dst, path->dst, ETH_ALEN); + preq_node->flags = flags; + + path->flags |= RTW_MESH_PATH_REQ_QUEUED; +#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK + if (flags & RTW_PREQ_Q_F_CHK) + path->flags |= RTW_MESH_PATH_ROOT_ADD_CHK; +#endif + if (flags & RTW_PREQ_Q_F_PEER_AKA) + path->flags |= RTW_MESH_PATH_PEER_AKA; + _rtw_spinunlock(&path->state_lock); + + rtw_list_insert_tail(&preq_node->list, &minfo->preq_queue.list); + ++minfo->preq_queue_len; + exit_critical_bh(&minfo->mesh_preq_queue_lock); + + if (rtw_time_after(rtw_get_current_time(), minfo->last_preq + rtw_min_preq_int_jiff(adapter))) + rtw_mesh_work(&adapter->mesh_work); + + else if (rtw_time_before(rtw_get_current_time(), minfo->last_preq)) { + /* systime wrapped around issue */ + minfo->last_preq = rtw_get_current_time() - rtw_min_preq_int_jiff(adapter) - 1; + rtw_mesh_work(&adapter->mesh_work); + } else + rtw_mod_timer(&adapter->mesh_path_timer, minfo->last_preq + + rtw_min_preq_int_jiff(adapter) + 1); +} + +static const u8 *rtw_hwmp_preq_da(struct rtw_mesh_path *path, + BOOLEAN is_root_add_chk, BOOLEAN da_is_peer) +{ + const u8 *da; + + if (da_is_peer) + da = path->dst; + else if (path->is_root) +#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK + da = is_root_add_chk ? path->add_chk_rann_snd_addr: + path->rann_snd_addr; +#else + da = path->rann_snd_addr; +#endif + else + da = bcast_addr; + + return da; +} + +void rtw_mesh_path_start_discovery(_adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_preq_queue *preq_node; + struct rtw_mesh_path *path; + u8 ttl, target_flags = 0; + const u8 *da; + u32 lifetime; + u8 flags = 0; + BOOLEAN is_root_add_chk = _FALSE; + BOOLEAN da_is_peer; + + enter_critical_bh(&minfo->mesh_preq_queue_lock); + if (!minfo->preq_queue_len || + rtw_time_before(rtw_get_current_time(), minfo->last_preq + + rtw_min_preq_int_jiff(adapter))) { + exit_critical_bh(&minfo->mesh_preq_queue_lock); + return; + } + + preq_node = rtw_list_first_entry(&minfo->preq_queue.list, + struct rtw_mesh_preq_queue, list); + rtw_list_delete(&preq_node->list); /* list_del_init(&preq_node->list); */ + --minfo->preq_queue_len; + exit_critical_bh(&minfo->mesh_preq_queue_lock); + + rtw_rcu_read_lock(); + path = rtw_mesh_path_lookup(adapter, preq_node->dst); + if (!path) + goto enddiscovery; + + enter_critical_bh(&path->state_lock); + if (path->flags & (RTW_MESH_PATH_DELETED | RTW_MESH_PATH_FIXED)) { + exit_critical_bh(&path->state_lock); + goto enddiscovery; + } + path->flags &= ~RTW_MESH_PATH_REQ_QUEUED; + if (preq_node->flags & RTW_PREQ_Q_F_START) { + if (path->flags & RTW_MESH_PATH_RESOLVING) { + exit_critical_bh(&path->state_lock); + goto enddiscovery; + } else { + path->flags &= ~RTW_MESH_PATH_RESOLVED; + path->flags |= RTW_MESH_PATH_RESOLVING; + path->discovery_retries = 0; + path->discovery_timeout = rtw_disc_timeout_jiff(adapter); + } + } else if (!(path->flags & RTW_MESH_PATH_RESOLVING) || + path->flags & RTW_MESH_PATH_RESOLVED) { + path->flags &= ~RTW_MESH_PATH_RESOLVING; + exit_critical_bh(&path->state_lock); + goto enddiscovery; + } + + minfo->last_preq = rtw_get_current_time(); + + if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update + + rtw_net_traversal_jiffies(adapter)) || + rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) { + ++minfo->sn; + minfo->last_sn_update = rtw_get_current_time(); + } + lifetime = rtw_default_lifetime(adapter); + ttl = mshcfg->element_ttl; + if (ttl == 0) { + minfo->mshstats.dropped_frames_ttl++; + exit_critical_bh(&path->state_lock); + goto enddiscovery; + } + + if (preq_node->flags & RTW_PREQ_Q_F_REFRESH) + target_flags |= RTW_IEEE80211_PREQ_TO_FLAG; + else + target_flags &= ~RTW_IEEE80211_PREQ_TO_FLAG; + +#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK + is_root_add_chk = !!(path->flags & RTW_MESH_PATH_ROOT_ADD_CHK); +#endif + da_is_peer = !!(path->flags & RTW_MESH_PATH_PEER_AKA); + exit_critical_bh(&path->state_lock); + + da = rtw_hwmp_preq_da(path, is_root_add_chk, da_is_peer); + +#ifdef CONFIG_RTW_MESH_ON_DMD_GANN + flags = (mshcfg->dot11MeshGateAnnouncementProtocol) + ? RTW_IEEE80211_PREQ_IS_GATE_FLAG : 0; +#endif + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter), minfo->sn, + target_flags, path->dst, path->sn, da, 0, + ttl, lifetime, 0, minfo->preq_id++, adapter); + rtw_mod_timer(&path->timer, rtw_get_current_time() + path->discovery_timeout); + +enddiscovery: + rtw_rcu_read_unlock(); + rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue)); +} + +void rtw_mesh_path_timer(void *ctx) +{ + struct rtw_mesh_path *path = (void *) ctx; + _adapter *adapter = path->adapter; + int ret; + u8 retry = 0; +#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; +#endif + /* TBD: Proctect for suspend */ +#if 0 + if (suspending) + return; +#endif + enter_critical_bh(&path->state_lock); + if (path->flags & RTW_MESH_PATH_RESOLVED || + (!(path->flags & RTW_MESH_PATH_RESOLVING))) { + path->flags &= ~(RTW_MESH_PATH_RESOLVING | + RTW_MESH_PATH_RESOLVED | + RTW_MESH_PATH_ROOT_ADD_CHK | + RTW_MESH_PATH_PEER_AKA); + exit_critical_bh(&path->state_lock); + } else if (path->discovery_retries < rtw_max_preq_retries(adapter)) { + ++path->discovery_retries; + path->discovery_timeout *= 2; + path->flags &= ~RTW_MESH_PATH_REQ_QUEUED; +#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK + if (path->discovery_retries > mshcfg->max_root_add_chk_cnt) + path->flags &= ~RTW_MESH_PATH_ROOT_ADD_CHK; +#endif + if (path->gate_asked) + retry |= RTW_PREQ_Q_F_REFRESH; + + exit_critical_bh(&path->state_lock); + rtw_mesh_queue_preq(path, retry); + } else { + path->flags &= ~(RTW_MESH_PATH_RESOLVING | + RTW_MESH_PATH_RESOLVED | + RTW_MESH_PATH_REQ_QUEUED | + RTW_MESH_PATH_ROOT_ADD_CHK | + RTW_MESH_PATH_PEER_AKA); + path->exp_time = rtw_get_current_time(); + exit_critical_bh(&path->state_lock); + if (!path->is_gate && rtw_mesh_gate_num(adapter) > 0) { + ret = rtw_mesh_path_send_to_gates(path); + if (ret) + RTW_HWMP_DBG("no gate was reachable\n"); + } else + rtw_mesh_path_flush_pending(path); + } +} + + +void rtw_mesh_path_tx_root_frame(_adapter *adapter) +{ + struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + u32 interval = mshcfg->dot11MeshHWMPRannInterval; + u8 flags, target_flags = 0; + + flags = (mshcfg->dot11MeshGateAnnouncementProtocol) + ? RTW_RANN_FLAG_IS_GATE : 0; + + switch (mshcfg->dot11MeshHWMPRootMode) { + case RTW_IEEE80211_PROACTIVE_RANN: + rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, adapter_mac_addr(adapter), + ++minfo->sn, 0, NULL, 0, bcast_addr, + 0, mshcfg->element_ttl, + interval, 0, 0, adapter); + break; + case RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP: + flags |= RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG; + case RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP: + interval = mshcfg->dot11MeshHWMPactivePathToRootTimeout; + target_flags |= RTW_IEEE80211_PREQ_TO_FLAG | + RTW_IEEE80211_PREQ_USN_FLAG; + rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter), + ++minfo->sn, target_flags, + (u8 *) bcast_addr, 0, bcast_addr, + 0, mshcfg->element_ttl, interval, + 0, minfo->preq_id++, adapter); + break; + default: + RTW_HWMP_INFO("Proactive mechanism not supported\n"); + return; + } +} + +void rtw_mesh_work(_workitem *work) +{ + /* use kernel global workqueue */ + _set_workitem(work); +} + +void rtw_ieee80211_mesh_path_timer(void *ctx) +{ + _adapter *adapter = (_adapter *)ctx; + rtw_mesh_work(&adapter->mesh_work); +} + +void rtw_ieee80211_mesh_path_root_timer(void *ctx) +{ + _adapter *adapter = (_adapter *)ctx; + + rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags); + + rtw_mesh_work(&adapter->mesh_work); +} + +static void rtw_ieee80211_mesh_rootpath(_adapter *adapter) +{ + u32 interval; + + rtw_mesh_path_tx_root_frame(adapter); + + if (adapter->mesh_cfg.dot11MeshHWMPRootMode == RTW_IEEE80211_PROACTIVE_RANN) + interval = adapter->mesh_cfg.dot11MeshHWMPRannInterval; + else + interval = adapter->mesh_cfg.dot11MeshHWMProotInterval; + + rtw_mod_timer(&adapter->mesh_path_root_timer, + RTW_TU_TO_EXP_TIME(interval)); +} + +BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter) +{ + BOOLEAN root_enabled = _FALSE; + + if (adapter->mesh_cfg.dot11MeshHWMPRootMode > RTW_IEEE80211_ROOTMODE_ROOT) { + rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags); + root_enabled = _TRUE; + } + else { + rtw_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags); + /* stop running timer */ + _cancel_timer_ex(&adapter->mesh_path_root_timer); + root_enabled = _FALSE; + } + + return root_enabled; +} + +void rtw_mesh_work_hdl(_workitem *work) +{ + _adapter *adapter = container_of(work, _adapter, mesh_work); + + while(adapter->mesh_info.preq_queue_len) { + if (rtw_time_after(rtw_get_current_time(), + adapter->mesh_info.last_preq + rtw_min_preq_int_jiff(adapter))) + /* It will consume preq_queue_len */ + rtw_mesh_path_start_discovery(adapter); + else { + struct rtw_mesh_info *minfo = &adapter->mesh_info; + + rtw_mod_timer(&adapter->mesh_path_timer, + minfo->last_preq + rtw_min_preq_int_jiff(adapter) + 1); + break; + } + } + + if (rtw_test_and_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags)) + rtw_ieee80211_mesh_rootpath(adapter); +} + +#ifndef RTW_PER_CMD_SUPPORT_FW +static void rtw_update_metric_directly(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 i; + + for (i = 0; i < macid_ctl->num; i++) { + u8 role; + role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]); + if (role == H2C_MSR_ROLE_MESH) { + struct sta_info *sta = macid_ctl->sta[i]; + u8 rate_idx, sgi, bw; + u32 rate; + + if (!sta) + continue; + rate_idx = rtw_get_current_tx_rate(adapter, sta); + sgi = rtw_get_current_tx_sgi(adapter, sta); + bw = sta->cmn.bw_mode; + rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi); + sta->metrics.data_rate = rate; + } + } +} +#endif + +void rtw_mesh_atlm_param_req_timer(void *ctx) +{ + _adapter *adapter = (_adapter *)ctx; + u8 ret = _FAIL; + +#ifdef RTW_PER_CMD_SUPPORT_FW + ret = rtw_req_per_cmd(adapter); + if (ret == _FAIL) + RTW_HWMP_INFO("rtw_req_per_cmd fail\n"); +#else + rtw_update_metric_directly(adapter); +#endif + _set_timer(&adapter->mesh_atlm_param_req_timer, RTW_ATLM_REQ_CYCLE); +} + +#endif /* CONFIG_RTW_MESH */ + diff --git a/core/mesh/rtw_mesh_hwmp.h b/core/mesh/rtw_mesh_hwmp.h new file mode 100644 index 0000000..9433417 --- /dev/null +++ b/core/mesh/rtw_mesh_hwmp.h @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_MESH_HWMP_H_ +#define __RTW_MESH_HWMP_H_ + +#ifndef DBG_RTW_HWMP +#define DBG_RTW_HWMP 0 +#endif +#if DBG_RTW_HWMP +#define RTW_HWMP_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg) +#else +#define RTW_HWMP_DBG(fmt, arg...) RTW_DBG(fmt, ##arg) +#endif + +#ifndef INFO_RTW_HWMP +#define INFO_RTW_HWMP 0 +#endif +#if INFO_RTW_HWMP +#define RTW_HWMP_INFO(fmt, arg...) RTW_PRINT(fmt, ##arg) +#else +#define RTW_HWMP_INFO(fmt, arg...) RTW_INFO(fmt, ##arg) +#endif + + +void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e); +unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e); +void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e, unsigned long val); +int rtw_mesh_path_error_tx(_adapter *adapter, + u8 ttl, const u8 *target, u32 target_sn, + u16 target_rcode, const u8 *ra); +void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id, + u8 per, u8 rate, + u8 bw, u8 total_pkt); +void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe); +void rtw_mesh_queue_preq(struct rtw_mesh_path *mpath, u8 flags); +void rtw_mesh_path_start_discovery(_adapter *adapter); +void rtw_mesh_path_timer(void *ctx); +void rtw_mesh_path_tx_root_frame(_adapter *adapter); +void rtw_mesh_work_hdl(_workitem *work); +void rtw_ieee80211_mesh_path_timer(void *ctx); +void rtw_ieee80211_mesh_path_root_timer(void *ctx); +BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter); +void rtw_mesh_work(_workitem *work); +void rtw_mesh_atlm_param_req_timer(void *ctx); + +#endif /* __RTW_MESH_HWMP_H_ */ + + diff --git a/core/mesh/rtw_mesh_pathtbl.c b/core/mesh/rtw_mesh_pathtbl.c new file mode 100644 index 0000000..5e778f6 --- /dev/null +++ b/core/mesh/rtw_mesh_pathtbl.c @@ -0,0 +1,1185 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_MESH_PATHTBL_C_ + +#ifdef CONFIG_RTW_MESH +#include +#include + +#ifdef PLATFORM_LINUX +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath) +{ + kfree_rcu(mpath, rcu); + rtw_mstat_update(MSTAT_TYPE_PHY, MSTAT_FREE, sizeof(struct rtw_mesh_path)); +} +#else +static void rtw_mpath_free_rcu_callback(rtw_rcu_head *head) +{ + struct rtw_mesh_path *mpath; + + mpath = container_of(head, struct rtw_mesh_path, rcu); + rtw_mfree(mpath, sizeof(struct rtw_mesh_path)); +} + +static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath) +{ + call_rcu(&mpath->rcu, rtw_mpath_free_rcu_callback); +} +#endif +#endif /* PLATFORM_LINUX */ + +static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath); + +static u32 rtw_mesh_table_hash(const void *addr, u32 len, u32 seed) +{ + /* Use last four bytes of hw addr as hash index */ + return jhash_1word(*(u32 *)(addr+2), seed); +} + +static const rtw_rhashtable_params rtw_mesh_rht_params = { + .nelem_hint = 2, + .automatic_shrinking = true, + .key_len = ETH_ALEN, + .key_offset = offsetof(struct rtw_mesh_path, dst), + .head_offset = offsetof(struct rtw_mesh_path, rhash), + .hashfn = rtw_mesh_table_hash, +}; + +static inline bool rtw_mpath_expired(struct rtw_mesh_path *mpath) +{ + return (mpath->flags & RTW_MESH_PATH_ACTIVE) && + rtw_time_after(rtw_get_current_time(), mpath->exp_time) && + !(mpath->flags & RTW_MESH_PATH_FIXED); +} + +static void rtw_mesh_path_rht_free(void *ptr, void *tblptr) +{ + struct rtw_mesh_path *mpath = ptr; + struct rtw_mesh_table *tbl = tblptr; + + rtw_mesh_path_free_rcu(tbl, mpath); +} + +static struct rtw_mesh_table *rtw_mesh_table_alloc(void) +{ + struct rtw_mesh_table *newtbl; + + newtbl = rtw_malloc(sizeof(struct rtw_mesh_table)); + if (!newtbl) + return NULL; + + rtw_hlist_head_init(&newtbl->known_gates); + ATOMIC_SET(&newtbl->entries, 0); + _rtw_spinlock_init(&newtbl->gates_lock); + + return newtbl; +} + +static void rtw_mesh_table_free(struct rtw_mesh_table *tbl) +{ + rtw_rhashtable_free_and_destroy(&tbl->rhead, + rtw_mesh_path_rht_free, tbl); + rtw_mfree(tbl, sizeof(struct rtw_mesh_table)); +} + +/** + * + * rtw_mesh_path_assign_nexthop - update mesh path next hop + * + * @mpath: mesh path to update + * @sta: next hop to assign + * + * Locking: mpath->state_lock must be held when calling this function + */ +void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta) +{ + struct xmit_frame *xframe; + _list *list, *head; + + rtw_rcu_assign_pointer(mpath->next_hop, sta); + + enter_critical_bh(&mpath->frame_queue.lock); + head = &mpath->frame_queue.queue; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + xframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + _rtw_memcpy(xframe->attrib.ra, sta->cmn.mac_addr, ETH_ALEN); + } + + exit_critical_bh(&mpath->frame_queue.lock); +} + +static void rtw_prepare_for_gate(struct xmit_frame *xframe, char *dst_addr, + struct rtw_mesh_path *gate_mpath) +{ + struct pkt_attrib *attrib = &xframe->attrib; + char *next_hop; + + if (attrib->mesh_frame_mode == MESH_UCAST_DATA) + attrib->mesh_frame_mode = MESH_UCAST_PX_DATA; + + /* update next hop */ + rtw_rcu_read_lock(); + next_hop = rtw_rcu_dereference(gate_mpath->next_hop)->cmn.mac_addr; + _rtw_memcpy(attrib->ra, next_hop, ETH_ALEN); + rtw_rcu_read_unlock(); + _rtw_memcpy(attrib->mda, dst_addr, ETH_ALEN); +} + +/** + * + * rtw_mesh_path_move_to_queue - Move or copy frames from one mpath queue to another + * + * This function is used to transfer or copy frames from an unresolved mpath to + * a gate mpath. The function also adds the Address Extension field and + * updates the next hop. + * + * If a frame already has an Address Extension field, only the next hop and + * destination addresses are updated. + * + * The gate mpath must be an active mpath with a valid mpath->next_hop. + * + * @mpath: An active mpath the frames will be sent to (i.e. the gate) + * @from_mpath: The failed mpath + * @copy: When true, copy all the frames to the new mpath queue. When false, + * move them. + */ +static void rtw_mesh_path_move_to_queue(struct rtw_mesh_path *gate_mpath, + struct rtw_mesh_path *from_mpath, + bool copy) +{ + struct xmit_frame *fskb; + _list *list, *head; + _list failq; + u32 failq_len; + _irqL flags; + + if (rtw_warn_on(gate_mpath == from_mpath)) + return; + if (rtw_warn_on(!gate_mpath->next_hop)) + return; + + _rtw_init_listhead(&failq); + + _enter_critical_bh(&from_mpath->frame_queue.lock, &flags); + rtw_list_splice_init(&from_mpath->frame_queue.queue, &failq); + failq_len = from_mpath->frame_queue_len; + from_mpath->frame_queue_len = 0; + _exit_critical_bh(&from_mpath->frame_queue.lock, &flags); + + head = &failq; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + if (gate_mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) { + RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM is full!\n" + , FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst); + break; + } + + fskb = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + + rtw_list_delete(&fskb->list); + failq_len--; + rtw_prepare_for_gate(fskb, gate_mpath->dst, gate_mpath); + _enter_critical_bh(&gate_mpath->frame_queue.lock, &flags); + rtw_list_insert_tail(&fskb->list, get_list_head(&gate_mpath->frame_queue)); + gate_mpath->frame_queue_len++; + _exit_critical_bh(&gate_mpath->frame_queue.lock, &flags); + + #if 0 /* TODO: copy */ + skb = rtw_skb_copy(fskb); + if (rtw_warn_on(!skb)) + break; + + rtw_prepare_for_gate(skb, gate_mpath->dst, gate_mpath); + skb_queue_tail(&gate_mpath->frame_queue, skb); + + if (copy) + continue; + + __skb_unlink(fskb, &failq); + rtw_skb_free(fskb); + #endif + } + + RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM has %d frames\n" + , FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst, gate_mpath->frame_queue_len); + + if (!copy) + return; + + _enter_critical_bh(&from_mpath->frame_queue.lock, &flags); + rtw_list_splice(&failq, &from_mpath->frame_queue.queue); + from_mpath->frame_queue_len += failq_len; + _exit_critical_bh(&from_mpath->frame_queue.lock, &flags); +} + + +static struct rtw_mesh_path *rtw_mpath_lookup(struct rtw_mesh_table *tbl, const u8 *dst) +{ + struct rtw_mesh_path *mpath; + + if (!tbl) + return NULL; + + mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, dst, rtw_mesh_rht_params); + + if (mpath && rtw_mpath_expired(mpath)) { + enter_critical_bh(&mpath->state_lock); + mpath->flags &= ~RTW_MESH_PATH_ACTIVE; + exit_critical_bh(&mpath->state_lock); + } + return mpath; +} + +/** + * rtw_mesh_path_lookup - look up a path in the mesh path table + * @sdata: local subif + * @dst: hardware address (ETH_ALEN length) of destination + * + * Returns: pointer to the mesh path structure, or NULL if not found + * + * Locking: must be called within a read rcu section. + */ +struct rtw_mesh_path * +rtw_mesh_path_lookup(_adapter *adapter, const u8 *dst) +{ + return rtw_mpath_lookup(adapter->mesh_info.mesh_paths, dst); +} + +struct rtw_mesh_path * +rtw_mpp_path_lookup(_adapter *adapter, const u8 *dst) +{ + return rtw_mpath_lookup(adapter->mesh_info.mpp_paths, dst); +} + +static struct rtw_mesh_path * +__rtw_mesh_path_lookup_by_idx(struct rtw_mesh_table *tbl, int idx) +{ + int i = 0, ret; + struct rtw_mesh_path *mpath = NULL; + rtw_rhashtable_iter iter; + + if (!tbl) + return NULL; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return NULL; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto err; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + if (i++ == idx) + break; + } +err: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); + + if (IS_ERR(mpath) || !mpath) + return NULL; + + if (rtw_mpath_expired(mpath)) { + enter_critical_bh(&mpath->state_lock); + mpath->flags &= ~RTW_MESH_PATH_ACTIVE; + exit_critical_bh(&mpath->state_lock); + } + return mpath; +} + +/** + * rtw_mesh_path_lookup_by_idx - look up a path in the mesh path table by its index + * @idx: index + * @sdata: local subif, or NULL for all entries + * + * Returns: pointer to the mesh path structure, or NULL if not found. + * + * Locking: must be called within a read rcu section. + */ +struct rtw_mesh_path * +rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx) +{ + return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mesh_paths, idx); +} + +/** + * rtw_mpp_path_lookup_by_idx - look up a path in the proxy path table by its index + * @idx: index + * @sdata: local subif, or NULL for all entries + * + * Returns: pointer to the proxy path structure, or NULL if not found. + * + * Locking: must be called within a read rcu section. + */ +struct rtw_mesh_path * +rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx) +{ + return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mpp_paths, idx); +} + +/** + * rtw_mesh_path_add_gate - add the given mpath to a mesh gate to our path table + * @mpath: gate path to add to table + */ +int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath) +{ + struct rtw_mesh_cfg *mcfg; + struct rtw_mesh_info *minfo; + struct rtw_mesh_table *tbl; + int err, ori_num_gates; + + rtw_rcu_read_lock(); + tbl = mpath->adapter->mesh_info.mesh_paths; + if (!tbl) { + err = -ENOENT; + goto err_rcu; + } + + enter_critical_bh(&mpath->state_lock); + mcfg = &mpath->adapter->mesh_cfg; + mpath->gate_timeout = rtw_get_current_time() + + rtw_ms_to_systime(mcfg->path_gate_timeout_factor * + mpath->gate_ann_int); + if (mpath->is_gate) { + err = -EEXIST; + exit_critical_bh(&mpath->state_lock); + goto err_rcu; + } + + minfo = &mpath->adapter->mesh_info; + mpath->is_gate = true; + _rtw_spinlock(&tbl->gates_lock); + ori_num_gates = minfo->num_gates; + minfo->num_gates++; + rtw_hlist_add_head_rcu(&mpath->gate_list, &tbl->known_gates); + + if (ori_num_gates == 0 + || rtw_macaddr_is_larger(mpath->dst, minfo->max_addr_gate->dst) + ) { + minfo->max_addr_gate = mpath; + minfo->max_addr_gate_is_larger_than_self = + rtw_macaddr_is_larger(mpath->dst, adapter_mac_addr(mpath->adapter)); + } + + _rtw_spinunlock(&tbl->gates_lock); + + exit_critical_bh(&mpath->state_lock); + + if (ori_num_gates == 0) { + update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE); + #if CONFIG_RTW_MESH_CTO_MGATE_CARRIER + if (!rtw_mesh_cto_mgate_required(mpath->adapter)) + rtw_netif_carrier_on(mpath->adapter->pnetdev); + #endif + } + + RTW_MPATH_DBG( + FUNC_ADPT_FMT" Mesh path: Recorded new gate: %pM. %d known gates\n", + FUNC_ADPT_ARG(mpath->adapter), + mpath->dst, mpath->adapter->mesh_info.num_gates); + err = 0; +err_rcu: + rtw_rcu_read_unlock(); + return err; +} + +/** + * rtw_mesh_gate_del - remove a mesh gate from the list of known gates + * @tbl: table which holds our list of known gates + * @mpath: gate mpath + */ +void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath) +{ + struct rtw_mesh_cfg *mcfg; + struct rtw_mesh_info *minfo; + int ori_num_gates; + + rtw_lockdep_assert_held(&mpath->state_lock); + if (!mpath->is_gate) + return; + + mcfg = &mpath->adapter->mesh_cfg; + minfo = &mpath->adapter->mesh_info; + + mpath->is_gate = false; + enter_critical_bh(&tbl->gates_lock); + rtw_hlist_del_rcu(&mpath->gate_list); + ori_num_gates = minfo->num_gates; + minfo->num_gates--; + + if (ori_num_gates == 1) { + minfo->max_addr_gate = NULL; + minfo->max_addr_gate_is_larger_than_self = 0; + } else if (minfo->max_addr_gate == mpath) { + struct rtw_mesh_path *gate, *max_addr_gate = NULL; + rtw_hlist_node *node; + + rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) { + if (!max_addr_gate || rtw_macaddr_is_larger(gate->dst, max_addr_gate->dst)) + max_addr_gate = gate; + } + minfo->max_addr_gate = max_addr_gate; + minfo->max_addr_gate_is_larger_than_self = + rtw_macaddr_is_larger(max_addr_gate->dst, adapter_mac_addr(mpath->adapter)); + } + + exit_critical_bh(&tbl->gates_lock); + + if (ori_num_gates == 1) { + update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE); + #if CONFIG_RTW_MESH_CTO_MGATE_CARRIER + if (rtw_mesh_cto_mgate_required(mpath->adapter)) + rtw_netif_carrier_off(mpath->adapter->pnetdev); + #endif + } + + RTW_MPATH_DBG( + FUNC_ADPT_FMT" Mesh path: Deleted gate: %pM. %d known gates\n", + FUNC_ADPT_ARG(mpath->adapter), + mpath->dst, mpath->adapter->mesh_info.num_gates); +} + +/** + * rtw_mesh_gate_search - search a mesh gate from the list of known gates + * @tbl: table which holds our list of known gates + * @addr: address of gate + */ +bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr) +{ + struct rtw_mesh_path *gate; + rtw_hlist_node *node; + bool exist = 0; + + rtw_rcu_read_lock(); + rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) { + if (_rtw_memcmp(gate->dst, addr, ETH_ALEN) == _TRUE) { + exist = 1; + break; + } + } + + rtw_rcu_read_unlock(); + + return exist; +} + +/** + * rtw_mesh_gate_num - number of gates known to this interface + * @sdata: subif data + */ +int rtw_mesh_gate_num(_adapter *adapter) +{ + return adapter->mesh_info.num_gates; +} + +bool rtw_mesh_is_primary_gate(_adapter *adapter) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + + return mcfg->dot11MeshGateAnnouncementProtocol + && !minfo->max_addr_gate_is_larger_than_self; +} + +void dump_known_gates(void *sel, _adapter *adapter) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_table *tbl; + struct rtw_mesh_path *gate; + rtw_hlist_node *node; + + if (!rtw_mesh_gate_num(adapter)) + goto exit; + + rtw_rcu_read_lock(); + + tbl = minfo->mesh_paths; + if (!tbl) + goto unlock; + + RTW_PRINT_SEL(sel, "num:%d\n", rtw_mesh_gate_num(adapter)); + + rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) { + RTW_PRINT_SEL(sel, "%c"MAC_FMT"\n" + , gate == minfo->max_addr_gate ? '*' : ' ' + , MAC_ARG(gate->dst)); + } + +unlock: + rtw_rcu_read_unlock(); +exit: + return; +} + +static +struct rtw_mesh_path *rtw_mesh_path_new(_adapter *adapter, + const u8 *dst) +{ + struct rtw_mesh_path *new_mpath; + + new_mpath = rtw_zmalloc(sizeof(struct rtw_mesh_path)); + if (!new_mpath) + return NULL; + + _rtw_memcpy(new_mpath->dst, dst, ETH_ALEN); + _rtw_memset(new_mpath->rann_snd_addr, 0xFF, ETH_ALEN); + new_mpath->is_root = false; + new_mpath->adapter = adapter; + new_mpath->flags = 0; + new_mpath->gate_asked = false; + _rtw_init_queue(&new_mpath->frame_queue); + new_mpath->frame_queue_len = 0; + new_mpath->exp_time = rtw_get_current_time(); + _rtw_spinlock_init(&new_mpath->state_lock); + rtw_init_timer(&new_mpath->timer, adapter, rtw_mesh_path_timer, new_mpath); + + return new_mpath; +} + +/** + * rtw_mesh_path_add - allocate and add a new path to the mesh path table + * @dst: destination address of the path (ETH_ALEN length) + * @sdata: local subif + * + * Returns: 0 on success + * + * State: the initial state of the new path is set to 0 + */ +struct rtw_mesh_path *rtw_mesh_path_add(_adapter *adapter, + const u8 *dst) +{ + struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths; + struct rtw_mesh_path *mpath, *new_mpath; + int ret; + + if (!tbl) + return ERR_PTR(-ENOTSUPP); + + if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE) + /* never add ourselves as neighbours */ + return ERR_PTR(-ENOTSUPP); + + if (is_multicast_mac_addr(dst)) + return ERR_PTR(-ENOTSUPP); + + if (ATOMIC_INC_UNLESS(&adapter->mesh_info.mpaths, RTW_MESH_MAX_MPATHS) == 0) + return ERR_PTR(-ENOSPC); + + new_mpath = rtw_mesh_path_new(adapter, dst); + if (!new_mpath) + return ERR_PTR(-ENOMEM); + + do { + ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead, + &new_mpath->rhash, + rtw_mesh_rht_params); + + if (ret == -EEXIST) + mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, + dst, + rtw_mesh_rht_params); + + } while (unlikely(ret == -EEXIST && !mpath)); + + if (ret && ret != -EEXIST) + return ERR_PTR(ret); + + /* At this point either new_mpath was added, or we found a + * matching entry already in the table; in the latter case + * free the unnecessary new entry. + */ + if (ret == -EEXIST) { + rtw_mfree(new_mpath, sizeof(struct rtw_mesh_path)); + new_mpath = mpath; + } + adapter->mesh_info.mesh_paths_generation++; + return new_mpath; +} + +int rtw_mpp_path_add(_adapter *adapter, + const u8 *dst, const u8 *mpp) +{ + struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths; + struct rtw_mesh_path *new_mpath; + int ret; + + if (!tbl) + return -ENOTSUPP; + + if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE) + /* never add ourselves as neighbours */ + return -ENOTSUPP; + + if (is_multicast_mac_addr(dst)) + return -ENOTSUPP; + + new_mpath = rtw_mesh_path_new(adapter, dst); + + if (!new_mpath) + return -ENOMEM; + + _rtw_memcpy(new_mpath->mpp, mpp, ETH_ALEN); + ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead, + &new_mpath->rhash, + rtw_mesh_rht_params); + + adapter->mesh_info.mpp_paths_generation++; + return ret; +} + +void dump_mpp(void *sel, _adapter *adapter) +{ + struct rtw_mesh_path *mpath; + int idx = 0; + char dst[ETH_ALEN]; + char mpp[ETH_ALEN]; + + RTW_PRINT_SEL(sel, "%-17s %-17s\n", "dst", "mpp"); + + do { + rtw_rcu_read_lock(); + + mpath = rtw_mpp_path_lookup_by_idx(adapter, idx); + if (mpath) { + _rtw_memcpy(dst, mpath->dst, ETH_ALEN); + _rtw_memcpy(mpp, mpath->mpp, ETH_ALEN); + } + + rtw_rcu_read_unlock(); + + if (mpath) { + RTW_PRINT_SEL(sel, MAC_FMT" "MAC_FMT"\n" + , MAC_ARG(dst), MAC_ARG(mpp)); + } + + idx++; + } while (mpath); +} + +/** + * rtw_mesh_plink_broken - deactivates paths and sends perr when a link breaks + * + * @sta: broken peer link + * + * This function must be called from the rate control algorithm if enough + * delivery errors suggest that a peer link is no longer usable. + */ +void rtw_mesh_plink_broken(struct sta_info *sta) +{ + _adapter *adapter = sta->padapter; + struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths; + static const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + struct rtw_mesh_path *mpath; + rtw_rhashtable_iter iter; + int ret; + + if (!tbl) + return; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto out; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + if (rtw_rcu_access_pointer(mpath->next_hop) == sta && + mpath->flags & RTW_MESH_PATH_ACTIVE && + !(mpath->flags & RTW_MESH_PATH_FIXED)) { + enter_critical_bh(&mpath->state_lock); + mpath->flags &= ~RTW_MESH_PATH_ACTIVE; + ++mpath->sn; + exit_critical_bh(&mpath->state_lock); + rtw_mesh_path_error_tx(adapter, + adapter->mesh_cfg.element_ttl, + mpath->dst, mpath->sn, + WLAN_REASON_MESH_PATH_DEST_UNREACHABLE, bcast); + } + } +out: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); +} + +static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl, + struct rtw_mesh_path *mpath) +{ + _adapter *adapter = mpath->adapter; + + enter_critical_bh(&mpath->state_lock); + mpath->flags |= RTW_MESH_PATH_RESOLVING | RTW_MESH_PATH_DELETED; + rtw_mesh_gate_del(tbl, mpath); + exit_critical_bh(&mpath->state_lock); + _cancel_timer_ex(&mpath->timer); + ATOMIC_DEC(&adapter->mesh_info.mpaths); + ATOMIC_DEC(&tbl->entries); + _rtw_spinlock_free(&mpath->state_lock); + + rtw_mesh_path_flush_pending(mpath); + + rtw_mpath_free_rcu(mpath); +} + +static void __rtw_mesh_path_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath) +{ + rtw_rhashtable_remove_fast(&tbl->rhead, &mpath->rhash, rtw_mesh_rht_params); + rtw_mesh_path_free_rcu(tbl, mpath); +} + +/** + * rtw_mesh_path_flush_by_nexthop - Deletes mesh paths if their next hop matches + * + * @sta: mesh peer to match + * + * RCU notes: this function is called when a mesh plink transitions from + * PLINK_ESTAB to any other state, since PLINK_ESTAB state is the only one that + * allows path creation. This will happen before the sta can be freed (because + * sta_info_destroy() calls this) so any reader in a rcu read block will be + * protected against the plink disappearing. + */ +void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta) +{ + _adapter *adapter = sta->padapter; + struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths; + struct rtw_mesh_path *mpath; + rtw_rhashtable_iter iter; + int ret; + + if (!tbl) + return; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto out; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + + if (rtw_rcu_access_pointer(mpath->next_hop) == sta) + __rtw_mesh_path_del(tbl, mpath); + } +out: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); +} + +static void rtw_mpp_flush_by_proxy(_adapter *adapter, + const u8 *proxy) +{ + struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths; + struct rtw_mesh_path *mpath; + rtw_rhashtable_iter iter; + int ret; + + if (!tbl) + return; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto out; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + + if (_rtw_memcmp(mpath->mpp, proxy, ETH_ALEN) == _TRUE) + __rtw_mesh_path_del(tbl, mpath); + } +out: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); +} + +static void rtw_table_flush_by_iface(struct rtw_mesh_table *tbl) +{ + struct rtw_mesh_path *mpath; + rtw_rhashtable_iter iter; + int ret; + + if (!tbl) + return; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto out; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + __rtw_mesh_path_del(tbl, mpath); + } +out: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); +} + +/** + * rtw_mesh_path_flush_by_iface - Deletes all mesh paths associated with a given iface + * + * This function deletes both mesh paths as well as mesh portal paths. + * + * @sdata: interface data to match + * + */ +void rtw_mesh_path_flush_by_iface(_adapter *adapter) +{ + rtw_table_flush_by_iface(adapter->mesh_info.mesh_paths); + rtw_table_flush_by_iface(adapter->mesh_info.mpp_paths); +} + +/** + * rtw_table_path_del - delete a path from the mesh or mpp table + * + * @tbl: mesh or mpp path table + * @sdata: local subif + * @addr: dst address (ETH_ALEN length) + * + * Returns: 0 if successful + */ +static int rtw_table_path_del(struct rtw_mesh_table *tbl, + const u8 *addr) +{ + struct rtw_mesh_path *mpath; + + if (!tbl) + return -ENXIO; + + rtw_rcu_read_lock(); + mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, addr, rtw_mesh_rht_params); + if (!mpath) { + rtw_rcu_read_unlock(); + return -ENXIO; + } + + __rtw_mesh_path_del(tbl, mpath); + rtw_rcu_read_unlock(); + return 0; +} + + +/** + * rtw_mesh_path_del - delete a mesh path from the table + * + * @addr: dst address (ETH_ALEN length) + * @sdata: local subif + * + * Returns: 0 if successful + */ +int rtw_mesh_path_del(_adapter *adapter, const u8 *addr) +{ + int err; + + /* flush relevant mpp entries first */ + rtw_mpp_flush_by_proxy(adapter, addr); + + err = rtw_table_path_del(adapter->mesh_info.mesh_paths, addr); + adapter->mesh_info.mesh_paths_generation++; + return err; +} + +/** + * rtw_mesh_path_tx_pending - sends pending frames in a mesh path queue + * + * @mpath: mesh path to activate + * + * Locking: the state_lock of the mpath structure must NOT be held when calling + * this function. + */ +void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath) +{ + if (mpath->flags & RTW_MESH_PATH_ACTIVE) { + struct rtw_mesh_info *minfo = &mpath->adapter->mesh_info; + _list q; + u32 q_len = 0; + + _rtw_init_listhead(&q); + + /* move to local queue */ + enter_critical_bh(&mpath->frame_queue.lock); + if (mpath->frame_queue_len) { + rtw_list_splice_init(&mpath->frame_queue.queue, &q); + q_len = mpath->frame_queue_len; + mpath->frame_queue_len = 0; + } + exit_critical_bh(&mpath->frame_queue.lock); + + if (q_len) { + /* move to mpath_tx_queue */ + enter_critical_bh(&minfo->mpath_tx_queue.lock); + rtw_list_splice_tail(&q, &minfo->mpath_tx_queue.queue); + minfo->mpath_tx_queue_len += q_len; + exit_critical_bh(&minfo->mpath_tx_queue.lock); + + /* schedule mpath_tx_tasklet */ + tasklet_hi_schedule(&minfo->mpath_tx_tasklet); + } + } +} + +/** + * rtw_mesh_path_send_to_gates - sends pending frames to all known mesh gates + * + * @mpath: mesh path whose queue will be emptied + * + * If there is only one gate, the frames are transferred from the failed mpath + * queue to that gate's queue. If there are more than one gates, the frames + * are copied from each gate to the next. After frames are copied, the + * mpath queues are emptied onto the transmission queue. + */ +int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath) +{ + _adapter *adapter = mpath->adapter; + struct rtw_mesh_table *tbl; + struct rtw_mesh_path *from_mpath = mpath; + struct rtw_mesh_path *gate; + bool copy = false; + rtw_hlist_node *node; + + tbl = adapter->mesh_info.mesh_paths; + if (!tbl) + return 0; + + rtw_rcu_read_lock(); + rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) { + if (gate->flags & RTW_MESH_PATH_ACTIVE) { + RTW_MPATH_DBG(FUNC_ADPT_FMT" Forwarding to %pM\n", + FUNC_ADPT_ARG(adapter), gate->dst); + rtw_mesh_path_move_to_queue(gate, from_mpath, copy); + from_mpath = gate; + copy = true; + } else { + RTW_MPATH_DBG( + FUNC_ADPT_FMT" Not forwarding to %pM (flags %#x)\n", + FUNC_ADPT_ARG(adapter), gate->dst, gate->flags); + } + } + + rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) { + RTW_MPATH_DBG(FUNC_ADPT_FMT" Sending to %pM\n", + FUNC_ADPT_ARG(adapter), gate->dst); + rtw_mesh_path_tx_pending(gate); + } + rtw_rcu_read_unlock(); + + return (from_mpath == mpath) ? -EHOSTUNREACH : 0; +} + +/** + * rtw_mesh_path_discard_frame - discard a frame whose path could not be resolved + * + * @skb: frame to discard + * @sdata: network subif the frame was to be sent through + * + * Locking: the function must me called within a rcu_read_lock region + */ +void rtw_mesh_path_discard_frame(_adapter *adapter, + struct xmit_frame *xframe) +{ + rtw_free_xmitframe(&adapter->xmitpriv, xframe); + adapter->mesh_info.mshstats.dropped_frames_no_route++; +} + +/** + * rtw_mesh_path_flush_pending - free the pending queue of a mesh path + * + * @mpath: mesh path whose queue has to be freed + * + * Locking: the function must me called within a rcu_read_lock region + */ +void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath) +{ + struct xmit_frame *xframe; + _list *list, *head; + _list tmp; + + _rtw_init_listhead(&tmp); + + enter_critical_bh(&mpath->frame_queue.lock); + rtw_list_splice_init(&mpath->frame_queue.queue, &tmp); + mpath->frame_queue_len = 0; + exit_critical_bh(&mpath->frame_queue.lock); + + head = &tmp; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + xframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&xframe->list); + rtw_mesh_path_discard_frame(mpath->adapter, xframe); + } +} + +/** + * rtw_mesh_path_fix_nexthop - force a specific next hop for a mesh path + * + * @mpath: the mesh path to modify + * @next_hop: the next hop to force + * + * Locking: this function must be called holding mpath->state_lock + */ +void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop) +{ + enter_critical_bh(&mpath->state_lock); + rtw_mesh_path_assign_nexthop(mpath, next_hop); + mpath->sn = 0xffff; + mpath->metric = 0; + mpath->hop_count = 0; + mpath->exp_time = 0; + mpath->flags = RTW_MESH_PATH_FIXED | RTW_MESH_PATH_SN_VALID; + rtw_mesh_path_activate(mpath); + exit_critical_bh(&mpath->state_lock); + rtw_ewma_err_rate_init(&next_hop->metrics.err_rate); + /* init it at a low value - 0 start is tricky */ + rtw_ewma_err_rate_add(&next_hop->metrics.err_rate, 1); + rtw_mesh_path_tx_pending(mpath); +} + +int rtw_mesh_pathtbl_init(_adapter *adapter) +{ + struct rtw_mesh_table *tbl_path, *tbl_mpp; + int ret; + + tbl_path = rtw_mesh_table_alloc(); + if (!tbl_path) + return -ENOMEM; + + tbl_mpp = rtw_mesh_table_alloc(); + if (!tbl_mpp) { + ret = -ENOMEM; + goto free_path; + } + + rtw_rhashtable_init(&tbl_path->rhead, &rtw_mesh_rht_params); + rtw_rhashtable_init(&tbl_mpp->rhead, &rtw_mesh_rht_params); + + adapter->mesh_info.mesh_paths = tbl_path; + adapter->mesh_info.mpp_paths = tbl_mpp; + + return 0; + +free_path: + rtw_mesh_table_free(tbl_path); + return ret; +} + +static +void rtw_mesh_path_tbl_expire(_adapter *adapter, + struct rtw_mesh_table *tbl) +{ + struct rtw_mesh_path *mpath; + rtw_rhashtable_iter iter; + int ret; + + if (!tbl) + return; + + ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter); + if (ret) + return; + + ret = rtw_rhashtable_walk_start(&iter); + if (ret && ret != -EAGAIN) + goto out; + + while ((mpath = rtw_rhashtable_walk_next(&iter))) { + if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN) + continue; + if (IS_ERR(mpath)) + break; + if ((!(mpath->flags & RTW_MESH_PATH_RESOLVING)) && + (!(mpath->flags & RTW_MESH_PATH_FIXED)) && + rtw_time_after(rtw_get_current_time(), mpath->exp_time + RTW_MESH_PATH_EXPIRE)) + __rtw_mesh_path_del(tbl, mpath); + + if (mpath->is_gate && /* need not to deal with non-gate case */ + rtw_time_after(rtw_get_current_time(), mpath->gate_timeout)) { + RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] expired systime is %lu systime is %lu\n", + FUNC_ADPT_ARG(adapter), mpath->dst, + mpath->gate_timeout, rtw_get_current_time()); + enter_critical_bh(&mpath->state_lock); + if (mpath->gate_asked) { /* asked gate before */ + rtw_mesh_gate_del(tbl, mpath); + exit_critical_bh(&mpath->state_lock); + } else { + mpath->gate_asked = true; + mpath->gate_timeout = rtw_get_current_time() + rtw_ms_to_systime(mpath->gate_ann_int); + exit_critical_bh(&mpath->state_lock); + rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH); + RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] ask mesh gate existence (is_root=%d)\n", + FUNC_ADPT_ARG(adapter), mpath->dst, mpath->is_root); + } + } + } + +out: + rtw_rhashtable_walk_stop(&iter); + rtw_rhashtable_walk_exit(&iter); +} + +void rtw_mesh_path_expire(_adapter *adapter) +{ + rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mesh_paths); + rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mpp_paths); +} + +void rtw_mesh_pathtbl_unregister(_adapter *adapter) +{ + if (adapter->mesh_info.mesh_paths) { + rtw_mesh_table_free(adapter->mesh_info.mesh_paths); + adapter->mesh_info.mesh_paths = NULL; + } + + if (adapter->mesh_info.mpp_paths) { + rtw_mesh_table_free(adapter->mesh_info.mpp_paths); + adapter->mesh_info.mpp_paths = NULL; + } +} +#endif /* CONFIG_RTW_MESH */ + diff --git a/core/mesh/rtw_mesh_pathtbl.h b/core/mesh/rtw_mesh_pathtbl.h new file mode 100644 index 0000000..7f5a26b --- /dev/null +++ b/core/mesh/rtw_mesh_pathtbl.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_MESH_PATHTBL_H_ +#define __RTW_MESH_PATHTBL_H_ + +#ifndef DBG_RTW_MPATH +#define DBG_RTW_MPATH 1 +#endif +#if DBG_RTW_MPATH +#define RTW_MPATH_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg) +#else +#define RTW_MPATH_DBG(fmt, arg...) do {} while (0) +#endif + +/** + * enum rtw_mesh_path_flags - mesh path flags + * + * @RTW_MESH_PATH_ACTIVE: the mesh path can be used for forwarding + * @RTW_MESH_PATH_RESOLVING: the discovery process is running for this mesh path + * @RTW_MESH_PATH_SN_VALID: the mesh path contains a valid destination sequence + * number + * @RTW_MESH_PATH_FIXED: the mesh path has been manually set and should not be + * modified + * @RTW_MESH_PATH_RESOLVED: the mesh path can has been resolved + * @RTW_MESH_PATH_REQ_QUEUED: there is an unsent path request for this destination + * already queued up, waiting for the discovery process to start. + * @RTW_MESH_PATH_DELETED: the mesh path has been deleted and should no longer + * be used + * @RTW_MESH_PATH_ROOT_ADD_CHK: root additional check in root mode. + * With this flag, It will try the last used rann_snd_addr + * @RTW_MESH_PATH_PEER_AKA: only used toward a peer, only used in active keep + * alive mechanism. PREQ's da = path dst + * + * RTW_MESH_PATH_RESOLVED is used by the mesh path timer to + * decide when to stop or cancel the mesh path discovery. + */ +enum rtw_mesh_path_flags { + RTW_MESH_PATH_ACTIVE = BIT(0), + RTW_MESH_PATH_RESOLVING = BIT(1), + RTW_MESH_PATH_SN_VALID = BIT(2), + RTW_MESH_PATH_FIXED = BIT(3), + RTW_MESH_PATH_RESOLVED = BIT(4), + RTW_MESH_PATH_REQ_QUEUED = BIT(5), + RTW_MESH_PATH_DELETED = BIT(6), + RTW_MESH_PATH_ROOT_ADD_CHK = BIT(7), + RTW_MESH_PATH_PEER_AKA = BIT(8), +}; + +/** + * struct rtw_mesh_path - mesh path structure + * + * @dst: mesh path destination mac address + * @mpp: mesh proxy mac address + * @rhash: rhashtable list pointer + * @gate_list: list pointer for known gates list + * @sdata: mesh subif + * @next_hop: mesh neighbor to which frames for this destination will be + * forwarded + * @timer: mesh path discovery timer + * @frame_queue: pending queue for frames sent to this destination while the + * path is unresolved + * @rcu: rcu head for freeing mesh path + * @sn: target sequence number + * @metric: current metric to this destination + * @hop_count: hops to destination + * @exp_time: in jiffies, when the path will expire or when it expired + * @discovery_timeout: timeout (lapse in jiffies) used for the last discovery + * retry + * @discovery_retries: number of discovery retries + * @flags: mesh path flags, as specified on &enum rtw_mesh_path_flags + * @state_lock: mesh path state lock used to protect changes to the + * mpath itself. No need to take this lock when adding or removing + * an mpath to a hash bucket on a path table. + * @rann_snd_addr: the RANN sender address + * @rann_metric: the aggregated path metric towards the root node + * @last_preq_to_root: Timestamp of last PREQ sent to root + * @is_root: the destination station of this path is a root node + * @is_gate: the destination station of this path is a mesh gate + * + * + * The dst address is unique in the mesh path table. Since the mesh_path is + * protected by RCU, deleting the next_hop STA must remove / substitute the + * mesh_path structure and wait until that is no longer reachable before + * destroying the STA completely. + */ +struct rtw_mesh_path { + u8 dst[ETH_ALEN]; + u8 mpp[ETH_ALEN]; /* used for MPP or MAP */ + rtw_rhash_head rhash; + rtw_hlist_node gate_list; + _adapter *adapter; + struct sta_info __rcu *next_hop; + _timer timer; + _queue frame_queue; + u32 frame_queue_len; + rtw_rcu_head rcu; + u32 sn; + u32 metric; + u8 hop_count; + systime exp_time; + systime discovery_timeout; + systime gate_timeout; + u32 gate_ann_int; /* gate announce interval */ + u8 discovery_retries; + enum rtw_mesh_path_flags flags; + _lock state_lock; + u8 rann_snd_addr[ETH_ALEN]; +#ifdef CONFIG_RTW_MESH_ADD_ROOT_CHK + u8 add_chk_rann_snd_addr[ETH_ALEN]; +#endif + u32 rann_metric; + unsigned long last_preq_to_root; + bool is_root; + bool is_gate; + bool gate_asked; +}; + +/** + * struct rtw_mesh_table + * + * @known_gates: list of known mesh gates and their mpaths by the station. The + * gate's mpath may or may not be resolved and active. + * @gates_lock: protects updates to known_gates + * @rhead: the rhashtable containing struct mesh_paths, keyed by dest addr + * @entries: number of entries in the table + */ +struct rtw_mesh_table { + rtw_hlist_head known_gates; + _lock gates_lock; + rtw_rhashtable rhead; + ATOMIC_T entries; +}; + +#define RTW_MESH_PATH_EXPIRE (600 * HZ) + +/* Maximum number of paths per interface */ +#define RTW_MESH_MAX_MPATHS 1024 + +/* Number of frames buffered per destination for unresolved destinations */ +#define RTW_MESH_FRAME_QUEUE_LEN 10 + +int rtw_mesh_nexthop_lookup(_adapter *adapter, + const u8 *mda, const u8 *msa, u8 *ra); +int rtw_mesh_nexthop_resolve(_adapter *adapter, + struct xmit_frame *xframe); + +struct rtw_mesh_path *rtw_mesh_path_lookup(_adapter *adapter, + const u8 *dst); +struct rtw_mesh_path *rtw_mpp_path_lookup(_adapter *adapter, + const u8 *dst); +int rtw_mpp_path_add(_adapter *adapter, + const u8 *dst, const u8 *mpp); +void dump_mpp(void *sel, _adapter *adapter); + +struct rtw_mesh_path * +rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx); +struct rtw_mesh_path * +rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx); +void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop); +void rtw_mesh_path_expire(_adapter *adapter); + +struct rtw_mesh_path * +rtw_mesh_path_add(_adapter *adapter, const u8 *dst); + +int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath); +void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath); +bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr); +int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath); +int rtw_mesh_gate_num(_adapter *adapter); +bool rtw_mesh_is_primary_gate(_adapter *adapter); +void dump_known_gates(void *sel, _adapter *adapter); + +void rtw_mesh_plink_broken(struct sta_info *sta); + +void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta); +void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath); +void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath); +int rtw_mesh_pathtbl_init(_adapter *adapter); +void rtw_mesh_pathtbl_unregister(_adapter *adapter); +int rtw_mesh_path_del(_adapter *adapter, const u8 *addr); + +void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta); +void rtw_mesh_path_discard_frame(_adapter *adapter, + struct xmit_frame *xframe); + +static inline void rtw_mesh_path_activate(struct rtw_mesh_path *mpath) +{ + mpath->flags |= RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVED; +} + +void rtw_mesh_path_flush_by_iface(_adapter *adapter); + +#endif /* __RTW_MESH_PATHTBL_H_ */ + diff --git a/core/rtw_ap.c b/core/rtw_ap.c index 80678e5..223489a 100644 --- a/core/rtw_ap.c +++ b/core/rtw_ap.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_AP_C_ #include @@ -32,13 +27,10 @@ extern unsigned char WFD_OUI[]; void init_mlme_ap_info(_adapter *padapter) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); _rtw_spinlock_init(&pmlmepriv->bcn_update_lock); - /* pmlmeext->bstart_bss = _FALSE; */ - } void free_mlme_ap_info(_adapter *padapter) @@ -50,6 +42,49 @@ void free_mlme_ap_info(_adapter *padapter) } +/* +* Set TIM IE +* return length of total TIM IE +*/ +u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period + , const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie) +{ + u8 *p = tim_ie; + u8 i, n1, n2; + u8 bmp_len; + + if (rtw_bmp_not_empty(tim_bmp, tim_bmp_len)) { + /* find the first nonzero octet in tim_bitmap */ + for (i = 0; i < tim_bmp_len; i++) + if (tim_bmp[i]) + break; + n1 = i & 0xFE; + + /* find the last nonzero octet in tim_bitmap, except octet 0 */ + for (i = tim_bmp_len - 1; i > 0; i--) + if (tim_bmp[i]) + break; + n2 = i; + bmp_len = n2 - n1 + 1; + } else { + n1 = n2 = 0; + bmp_len = 1; + } + + *p++ = WLAN_EID_TIM; + *p++ = 2 + 1 + bmp_len; + *p++ = dtim_cnt; + *p++ = dtim_period; + *p++ = (rtw_bmp_is_set(tim_bmp, tim_bmp_len, 0) ? BIT0 : 0) | n1; + _rtw_memcpy(p, tim_bmp + n1, bmp_len); + +#if 0 + RTW_INFO("n1:%u, n2:%u, bmp_offset:%u, bmp_len:%u\n", n1, n2, n1 / 2, bmp_len); + RTW_INFO_DUMP("tim_ie: ", tim_ie + 2, 2 + 1 + bmp_len); +#endif + return 2 + 2 + 1 + bmp_len; +} + static void update_BCNTIM(_adapter *padapter) { struct sta_priv *pstapriv = &padapter->stapriv; @@ -62,15 +97,12 @@ static void update_BCNTIM(_adapter *padapter) /* update TIM IE */ - /* if(pstapriv->tim_bitmap) */ + /* if(rtw_tim_map_anyone_be_set(padapter, pstapriv->tim_bitmap)) */ #endif if (_TRUE) { u8 *p, *dst_ie, *premainder_ie = NULL, *pbackup_remainder_ie = NULL; - u16 tim_bitmap_le; uint offset, tmp_len, tim_ielen, tim_ie_offset, remainder_ielen; - tim_bitmap_le = cpu_to_le16(pstapriv->tim_bitmap); - p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, _TIM_IE_, &tim_ielen, pnetwork_mlmeext->IELength - _FIXED_IE_LENGTH_); if (p != NULL && tim_ielen > 0) { tim_ielen += 2; @@ -117,39 +149,8 @@ static void update_BCNTIM(_adapter *padapter) _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); } - *dst_ie++ = _TIM_IE_; - - if ((pstapriv->tim_bitmap & 0xff00) && (pstapriv->tim_bitmap & 0x00fe)) - tim_ielen = 5; - else - tim_ielen = 4; - - *dst_ie++ = tim_ielen; - - *dst_ie++ = 0;/*DTIM count*/ - *dst_ie++ = 1;/*DTIM period*/ - - if (pstapriv->tim_bitmap & BIT(0))/*for bc/mc frames*/ - *dst_ie++ = BIT(0);/*bitmap ctrl */ - else - *dst_ie++ = 0; - - if (tim_ielen == 4) { - u8 pvb = 0; - - if (pstapriv->tim_bitmap & 0x00fe) - pvb = (u8)tim_bitmap_le; - else if (pstapriv->tim_bitmap & 0xff00) - pvb = (u8)(tim_bitmap_le >> 8); - else - pvb = (u8)tim_bitmap_le; - - *dst_ie++ = pvb; - - } else if (tim_ielen == 5) { - _rtw_memcpy(dst_ie, &tim_bitmap_le, 2); - dst_ie += 2; - } + /* append TIM IE */ + dst_ie += rtw_set_tim_ie(0, 1, pstapriv->tim_bitmap, pstapriv->aid_bmp_len, dst_ie); /*copy remainder IE*/ if (pbackup_remainder_ie) { @@ -274,8 +275,8 @@ u8 chk_sta_is_alive(struct sta_info *psta) u8 ret = _FALSE; #ifdef DBG_EXPIRATION_CHK RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", expire_to:%u, %s%ssq_len:%u\n" - , MAC_ARG(psta->hwaddr) - , psta->rssi_stat.undecorated_smoothed_pwdb + , MAC_ARG(psta->cmn.mac_addr) + , psta->cmn.rssi_stat.rssi /* , STA_RX_PKTS_ARG(psta) */ , STA_RX_PKTS_DIFF_ARG(psta) , psta->expire_to @@ -290,6 +291,12 @@ u8 chk_sta_is_alive(struct sta_info *psta) #if 0 if (psta->state & WIFI_SLEEP_STATE) ret = _TRUE; +#endif +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(psta->padapter) && + (psta->sta_stats.last_rx_hwmp_pkts != + psta->sta_stats.rx_hwmp_pkts)) + ret = _TRUE; #endif } else ret = _TRUE; @@ -299,6 +306,52 @@ u8 chk_sta_is_alive(struct sta_info *psta) return ret; } +/** + * issue_aka_chk_frame - issue active keep alive check frame + * aka = active keep alive + */ +static int issue_aka_chk_frame(_adapter *adapter, struct sta_info *psta) +{ + int ret = _FAIL; + u8 *target_addr = psta->cmn.mac_addr; + + if (MLME_IS_AP(adapter)) { + /* issue null data to check sta alive */ + if (psta->state & WIFI_SLEEP_STATE) + ret = issue_nulldata(adapter, target_addr, 0, 1, 50); + else + ret = issue_nulldata(adapter, target_addr, 0, 3, 50); + } + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + struct rtw_mesh_path *mpath; + + rtw_rcu_read_lock(); + mpath = rtw_mesh_path_lookup(adapter, target_addr); + if (!mpath) { + mpath = rtw_mesh_path_add(adapter, target_addr); + if (IS_ERR(mpath)) { + rtw_rcu_read_unlock(); + RTW_ERR(FUNC_ADPT_FMT" rtw_mesh_path_add for "MAC_FMT" fail.\n", + FUNC_ADPT_ARG(adapter), MAC_ARG(target_addr)); + return _FAIL; + } + } + if (mpath->flags & RTW_MESH_PATH_ACTIVE) + ret = _SUCCESS; + else { + u8 flags = RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_PEER_AKA; + /* issue PREQ to check peer alive */ + rtw_mesh_queue_preq(mpath, flags); + ret = _FALSE; + } + rtw_rcu_read_unlock(); + } +#endif + return ret; +} + void expire_timeout_chk(_adapter *padapter) { _irqL irqL; @@ -310,6 +363,22 @@ void expire_timeout_chk(_adapter *padapter) char chk_alive_list[NUM_STA]; int i; +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter) + && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) + ) { + struct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg; + + rtw_mesh_path_expire(padapter); + + /* TBD: up layer timeout mechanism */ + /* if (!mcfg->plink_timeout) + return; */ +#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + return; +#endif + } +#endif #ifdef CONFIG_MCC_MODE /* then driver may check fail due to not recv client's frame under sitesurvey, @@ -327,8 +396,8 @@ void expire_timeout_chk(_adapter *padapter) /* check auth_queue */ #ifdef DBG_EXPIRATION_CHK if (rtw_end_of_queue_search(phead, plist) == _FALSE) { - RTW_INFO(FUNC_NDEV_FMT" auth_list, cnt:%u\n" - , FUNC_NDEV_ARG(padapter->pnetdev), pstapriv->auth_list_cnt); + RTW_INFO(FUNC_ADPT_FMT" auth_list, cnt:%u\n" + , FUNC_ADPT_ARG(padapter), pstapriv->auth_list_cnt); } #endif while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { @@ -338,7 +407,7 @@ void expire_timeout_chk(_adapter *padapter) #ifdef CONFIG_ATMEL_RC_PATCH - if (_TRUE == _rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->hwaddr), ETH_ALEN)) + if (_rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE) continue; if (psta->flag_atmel_rc) continue; @@ -349,8 +418,8 @@ void expire_timeout_chk(_adapter *padapter) rtw_list_delete(&psta->auth_list); pstapriv->auth_list_cnt--; - RTW_INFO("auth expire %02X%02X%02X%02X%02X%02X\n", - psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2], psta->hwaddr[3], psta->hwaddr[4], psta->hwaddr[5]); + RTW_INFO(FUNC_ADPT_FMT" auth expire "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); @@ -376,8 +445,8 @@ void expire_timeout_chk(_adapter *padapter) /* check asoc_queue */ #ifdef DBG_EXPIRATION_CHK if (rtw_end_of_queue_search(phead, plist) == _FALSE) { - RTW_INFO(FUNC_NDEV_FMT" asoc_list, cnt:%u\n" - , FUNC_NDEV_ARG(padapter->pnetdev), pstapriv->asoc_list_cnt); + RTW_INFO(FUNC_ADPT_FMT" asoc_list, cnt:%u\n" + , FUNC_ADPT_ARG(padapter), pstapriv->asoc_list_cnt); } #endif while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { @@ -385,8 +454,8 @@ void expire_timeout_chk(_adapter *padapter) plist = get_next(plist); #ifdef CONFIG_ATMEL_RC_PATCH RTW_INFO("%s:%d psta=%p, %02x,%02x||%02x,%02x \n\n", __func__, __LINE__, - psta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->hwaddr[0], psta->hwaddr[5]); - if (_TRUE == _rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->hwaddr), ETH_ALEN)) + psta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->cmn.mac_addr[0], psta->cmn.mac_addr[5]); + if (_rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE) continue; if (psta->flag_atmel_rc) continue; @@ -421,7 +490,7 @@ void expire_timeout_chk(_adapter *padapter) RTW_INFO("asoc check by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to - psta->expire_to) * 2); psta->under_exist_checking = 1; /* tear down TX AMPDU */ - send_delba(padapter, 1, psta->hwaddr);/* */ /* originator */ + send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */ psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ } @@ -473,7 +542,7 @@ void expire_timeout_chk(_adapter *padapter) RTW_INFO("issue addba_req to check if sta alive, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt); - issue_addba_req(padapter, psta->hwaddr, (u8)priority); + issue_addba_req(padapter, psta->cmn.mac_addr, (u8)priority); _set_timer(&psta->addba_retry_timer, ADDBA_TO); @@ -497,38 +566,32 @@ void expire_timeout_chk(_adapter *padapter) psta->expire_to = pstapriv->expire_to; psta->state |= WIFI_STA_ALIVE_CHK_STATE; - /* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->hwaddr)); */ + /* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->cmn.mac_addr)); */ /* to update bcn with tim_bitmap for this station */ - pstapriv->tim_bitmap |= BIT(psta->aid); + rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid); update_beacon(padapter, _TIM_IE_, NULL, _TRUE); if (!pmlmeext->active_keep_alive_check) continue; } } -#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK - if (pmlmeext->active_keep_alive_check) { + + { int stainfo_offset; stainfo_offset = rtw_stainfo_offset(pstapriv, psta); if (stainfo_offset_valid(stainfo_offset)) chk_alive_list[chk_alive_num++] = stainfo_offset; - continue; } -#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ - rtw_list_delete(&psta->asoc_list); - pstapriv->asoc_list_cnt--; - RTW_INFO("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state); - updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); } else { /* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */ if (psta->sleepq_len > (NR_XMITFRAME / pstapriv->asoc_list_cnt) && padapter->xmitpriv.free_xmitframe_cnt < ((NR_XMITFRAME / pstapriv->asoc_list_cnt) / 2) ) { - RTW_INFO("%s sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n", __func__ - , MAC_ARG(psta->hwaddr) + RTW_INFO(FUNC_ADPT_FMT" sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) , psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt); wakeup_sta_to_xmit(padapter, psta); } @@ -537,115 +600,142 @@ void expire_timeout_chk(_adapter *padapter) _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); -#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK if (chk_alive_num) { - - u8 backup_ch = 0, backup_bw, backup_offset; - u8 union_ch = 0, union_bw, union_offset; - u8 switch_channel = _TRUE; +#if defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) + u8 backup_ch = 0, backup_bw = 0, backup_offset = 0; + u8 union_ch = 0, union_bw = 0, union_offset = 0; + u8 switch_channel_by_drv = _TRUE; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; +#endif + char del_asoc_list[NUM_STA]; - if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) - || pmlmeext->cur_channel != union_ch) - goto bypass_active_keep_alive; + _rtw_memset(del_asoc_list, NUM_STA, NUM_STA); -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - /* driver doesn't switch channel under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) - switch_channel = _FALSE; - } -#endif - /* switch to correct channel of current network before issue keep-alive frames */ - if (switch_channel == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { - backup_ch = rtw_get_oper_ch(padapter); - backup_bw = rtw_get_oper_bw(padapter); - backup_offset = rtw_get_oper_choffset(padapter); - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + if (pmlmeext->active_keep_alive_check) { + #ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter)) { + /* driver doesn't switch channel under MCC */ + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + switch_channel_by_drv = _FALSE; + } + #endif + + if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) + || pmlmeext->cur_channel != union_ch) + switch_channel_by_drv = _FALSE; + + /* switch to correct channel of current network before issue keep-alive frames */ + if (switch_channel_by_drv == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { + backup_ch = rtw_get_oper_ch(padapter); + backup_bw = rtw_get_oper_bw(padapter); + backup_offset = rtw_get_oper_choffset(padapter); + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + } } + #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ - /* issue null data to check sta alive*/ + /* check loop */ for (i = 0; i < chk_alive_num; i++) { + #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK int ret = _FAIL; + #endif psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); -#ifdef CONFIG_ATMEL_RC_PATCH - if (_TRUE == _rtw_memcmp(pstapriv->atmel_rc_pattern, psta->hwaddr, ETH_ALEN)) + + #ifdef CONFIG_ATMEL_RC_PATCH + if (_rtw_memcmp(pstapriv->atmel_rc_pattern, psta->cmn.mac_addr, ETH_ALEN) == _TRUE) continue; if (psta->flag_atmel_rc) continue; -#endif + #endif + if (!(psta->state & _FW_LINKED)) continue; - if (psta->state & WIFI_SLEEP_STATE) - ret = issue_nulldata(padapter, psta->hwaddr, 0, 1, 50); - else - ret = issue_nulldata(padapter, psta->hwaddr, 0, 3, 50); + #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + if (pmlmeext->active_keep_alive_check) { + /* issue active keep alive frame to check */ + ret = issue_aka_chk_frame(padapter, psta); - psta->keep_alive_trycnt++; - if (ret == _SUCCESS) { - RTW_INFO("asoc check, sta(" MAC_FMT ") is alive\n", MAC_ARG(psta->hwaddr)); - psta->expire_to = pstapriv->expire_to; - psta->keep_alive_trycnt = 0; - continue; - } else if (psta->keep_alive_trycnt <= 3) { - RTW_INFO("ack check for asoc expire, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt); - psta->expire_to = 1; - continue; + psta->keep_alive_trycnt++; + if (ret == _SUCCESS) { + RTW_INFO(FUNC_ADPT_FMT" asoc check, "MAC_FMT" is alive\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + psta->expire_to = pstapriv->expire_to; + psta->keep_alive_trycnt = 0; + continue; + } else if (psta->keep_alive_trycnt <= 3) { + RTW_INFO(FUNC_ADPT_FMT" asoc check, "MAC_FMT" keep_alive_trycnt=%d\n" + , FUNC_ADPT_ARG(padapter) , MAC_ARG(psta->cmn.mac_addr), psta->keep_alive_trycnt); + psta->expire_to = 1; + continue; + } } + #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ psta->keep_alive_trycnt = 0; - RTW_INFO("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state); + del_asoc_list[i] = chk_alive_list[i]; _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; - updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); + STA_SET_MESH_PLINK(psta, NULL); } _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - } - /* back to the original operation channel */ - if (switch_channel && backup_ch > 0) - set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); + /* delete loop */ + for (i = 0; i < chk_alive_num; i++) { + u8 sta_addr[ETH_ALEN]; + + if (del_asoc_list[i] >= NUM_STA) + continue; + + psta = rtw_get_stainfo_by_offset(pstapriv, del_asoc_list[i]); + _rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN); + + RTW_INFO(FUNC_ADPT_FMT" asoc expire "MAC_FMT", state=0x%x\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state); + updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _FALSE); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_expire_peer(padapter, sta_addr); + #endif + } -bypass_active_keep_alive: - ; + #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + if (pmlmeext->active_keep_alive_check) { + /* back to the original operation channel */ + if (switch_channel_by_drv == _TRUE && backup_ch > 0) + set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); + } + #endif } -#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); } -void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_update_bw) +void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta) { - int i; - u8 rf_type; unsigned char sta_band = 0; u64 tx_ra_bitmap = 0; - struct ht_priv *psta_ht = NULL; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; -#ifdef CONFIG_80211N_HT - if (psta) - psta_ht = &psta->htpriv; - else + if (!psta) return; -#endif /* CONFIG_80211N_HT */ if (!(psta->state & _FW_LINKED)) return; - rtw_hal_update_sta_rate_mask(padapter, psta); - tx_ra_bitmap = psta->ra_mask; + rtw_hal_update_sta_ra_info(padapter, psta); + tx_ra_bitmap = psta->cmn.ra_info.ramask; if (pcur_network->Configuration.DSConfig > 14) { if (tx_ra_bitmap & 0xffff000) - sta_band |= WIRELESS_11_5N ; + sta_band |= WIRELESS_11_5N; if (tx_ra_bitmap & 0xff0) sta_band |= WIRELESS_11A; @@ -655,7 +745,6 @@ void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_u if (psta->vhtpriv.vht_option) sta_band = WIRELESS_11_5AC; #endif - } else { if (tx_ra_bitmap & 0xffff000) sta_band |= WIRELESS_11_24N; @@ -668,16 +757,181 @@ void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_u } psta->wireless_mode = sta_band; - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + rtw_hal_update_sta_wset(padapter, psta); + RTW_INFO("%s=> mac_id:%d , tx_ra_bitmap:0x%016llx, networkType:0x%02x\n", + __FUNCTION__, psta->cmn.mac_id, tx_ra_bitmap, psta->wireless_mode); +} - if (psta->aid < NUM_STA) { - RTW_INFO("%s=> mac_id:%d , raid:%d, tx_ra_bitmap:0x%016llx, networkType:0x%02x\n", - __FUNCTION__, psta->mac_id, psta->raid, tx_ra_bitmap, psta->wireless_mode); +#ifdef CONFIG_BMC_TX_RATE_SELECT +u8 rtw_ap_find_mini_tx_rate(_adapter *adapter) +{ + _irqL irqL; + _list *phead, *plist; + u8 miini_tx_rate = ODM_RATEVHTSS4MCS9, sta_tx_rate; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &adapter->stapriv; - rtw_update_ramask(padapter, psta, psta->mac_id, rssi_level, is_update_bw); - } else - RTW_INFO("station aid %d exceed the max number\n", psta->aid); + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + sta_tx_rate = psta->cmn.ra_info.curr_tx_rate & 0x7F; + if (sta_tx_rate < miini_tx_rate) + miini_tx_rate = sta_tx_rate; + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + return miini_tx_rate; +} + +u8 rtw_ap_find_bmc_rate(_adapter *adapter, u8 tx_rate) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + u8 tx_ini_rate = ODM_RATE6M; + + switch (tx_rate) { + case ODM_RATEVHTSS3MCS9: + case ODM_RATEVHTSS3MCS8: + case ODM_RATEVHTSS3MCS7: + case ODM_RATEVHTSS3MCS6: + case ODM_RATEVHTSS3MCS5: + case ODM_RATEVHTSS3MCS4: + case ODM_RATEVHTSS3MCS3: + case ODM_RATEVHTSS2MCS9: + case ODM_RATEVHTSS2MCS8: + case ODM_RATEVHTSS2MCS7: + case ODM_RATEVHTSS2MCS6: + case ODM_RATEVHTSS2MCS5: + case ODM_RATEVHTSS2MCS4: + case ODM_RATEVHTSS2MCS3: + case ODM_RATEVHTSS1MCS9: + case ODM_RATEVHTSS1MCS8: + case ODM_RATEVHTSS1MCS7: + case ODM_RATEVHTSS1MCS6: + case ODM_RATEVHTSS1MCS5: + case ODM_RATEVHTSS1MCS4: + case ODM_RATEVHTSS1MCS3: + case ODM_RATEMCS15: + case ODM_RATEMCS14: + case ODM_RATEMCS13: + case ODM_RATEMCS12: + case ODM_RATEMCS11: + case ODM_RATEMCS7: + case ODM_RATEMCS6: + case ODM_RATEMCS5: + case ODM_RATEMCS4: + case ODM_RATEMCS3: + case ODM_RATE54M: + case ODM_RATE48M: + case ODM_RATE36M: + case ODM_RATE24M: + tx_ini_rate = ODM_RATE24M; + break; + case ODM_RATEVHTSS3MCS2: + case ODM_RATEVHTSS3MCS1: + case ODM_RATEVHTSS2MCS2: + case ODM_RATEVHTSS2MCS1: + case ODM_RATEVHTSS1MCS2: + case ODM_RATEVHTSS1MCS1: + case ODM_RATEMCS10: + case ODM_RATEMCS9: + case ODM_RATEMCS2: + case ODM_RATEMCS1: + case ODM_RATE18M: + case ODM_RATE12M: + tx_ini_rate = ODM_RATE12M; + break; + case ODM_RATEVHTSS3MCS0: + case ODM_RATEVHTSS2MCS0: + case ODM_RATEVHTSS1MCS0: + case ODM_RATEMCS8: + case ODM_RATEMCS0: + case ODM_RATE9M: + case ODM_RATE6M: + tx_ini_rate = ODM_RATE6M; + break; + case ODM_RATE11M: + case ODM_RATE5_5M: + case ODM_RATE2M: + case ODM_RATE1M: + tx_ini_rate = ODM_RATE1M; + break; + default: + tx_ini_rate = ODM_RATE6M; + break; + } + if (hal_data->current_band_type == BAND_ON_5G) + if (tx_ini_rate < ODM_RATE6M) + tx_ini_rate = ODM_RATE6M; + + return tx_ini_rate; +} + +void rtw_update_bmc_sta_tx_rate(_adapter *adapter) +{ + struct sta_info *psta = NULL; + u8 tx_rate; + + psta = rtw_get_bcmc_stainfo(adapter); + if (psta == NULL) { + RTW_ERR(ADPT_FMT "could not get bmc_sta !!\n", ADPT_ARG(adapter)); + return; + } + + if (adapter->bmc_tx_rate != MGN_UNKNOWN) { + psta->init_rate = adapter->bmc_tx_rate; + goto _exit; + } + + if (adapter->stapriv.asoc_sta_count <= 2) + goto _exit; + + tx_rate = rtw_ap_find_mini_tx_rate(adapter); + #ifdef CONFIG_BMC_TX_LOW_RATE + tx_rate = rtw_ap_find_bmc_rate(adapter, tx_rate); + #endif + + psta->init_rate = hw_rate_to_m_rate(tx_rate); + +_exit: + RTW_INFO(ADPT_FMT" BMC Tx rate - %s\n", ADPT_ARG(adapter), MGN_RATE_STR(psta->init_rate)); +} +#endif + +void rtw_init_bmc_sta_tx_rate(_adapter *padapter, struct sta_info *psta) +{ +#ifdef CONFIG_BMC_TX_LOW_RATE + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); +#endif + u8 rate_idx = 0; + u8 brate_table[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, + MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}; + + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) + return; + + if (padapter->bmc_tx_rate != MGN_UNKNOWN) + psta->init_rate = padapter->bmc_tx_rate; + else { + #ifdef CONFIG_BMC_TX_LOW_RATE + if (IsEnableHWOFDM(pmlmeext->cur_wireless_mode) && (psta->cmn.ra_info.ramask && 0xFF0)) + rate_idx = get_lowest_rate_idx_ex(psta->cmn.ra_info.ramask, 4); /*from basic rate*/ + else + rate_idx = get_lowest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/ + #else + rate_idx = get_highest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/ + #endif + if (rate_idx < 12) + psta->init_rate = brate_table[rate_idx]; + else + psta->init_rate = MGN_1M; + } + + RTW_INFO(ADPT_FMT" BMC Init Tx rate - %s\n", ADPT_ARG(padapter), MGN_RATE_STR(psta->init_rate)); } void update_bmc_sta(_adapter *padapter) @@ -690,8 +944,13 @@ void update_bmc_sta(_adapter *padapter) struct sta_info *psta = rtw_get_bcmc_stainfo(padapter); if (psta) { - psta->aid = 0;/* default set to 0 */ - psta->qos_option = 0; + psta->cmn.aid = 0;/* default set to 0 */ +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + psta->qos_option = 1; + else +#endif + psta->qos_option = 0; #ifdef CONFIG_80211N_HT psta->htpriv.ht_option = _FALSE; #endif /* CONFIG_80211N_HT */ @@ -702,7 +961,6 @@ void update_bmc_sta(_adapter *padapter) /* psta->dot118021XPrivacy = _NO_PRIVACY_; */ /* !!! remove it, because it has been set before this. */ - /* prepare for add_RATid */ supportRateNum = rtw_get_rateset_len((u8 *)&pcur_network->SupportedRates); network_type = rtw_check_network_type((u8 *)&pcur_network->SupportedRates, supportRateNum, pcur_network->Configuration.DSConfig); if (IsSupportedTxCCK(network_type)) @@ -716,21 +974,52 @@ void update_bmc_sta(_adapter *padapter) update_sta_basic_rate(psta, network_type); psta->wireless_mode = network_type; - rtw_hal_update_sta_rate_mask(padapter, psta); - - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + rtw_hal_update_sta_ra_info(padapter, psta); _enter_critical_bh(&psta->lock, &irqL); psta->state = _FW_LINKED; _exit_critical_bh(&psta->lock, &irqL); rtw_sta_media_status_rpt(padapter, psta, 1); - rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); + rtw_init_bmc_sta_tx_rate(padapter, psta); + } else RTW_INFO("add_RATid_bmc_sta error!\n"); } +#if defined(CONFIG_80211N_HT) && defined(CONFIG_BEAMFORMING) +void update_sta_info_apmode_ht_bf_cap(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; + struct ht_priv *phtpriv_sta = &psta->htpriv; + + u8 cur_beamform_cap = 0; + + /*Config Tx beamforming setting*/ + if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP((u8 *)(&phtpriv_sta->ht_cap))) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + /*Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 6); + } + + if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP((u8 *)(&phtpriv_sta->ht_cap))) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + /*Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4); + } + if (cur_beamform_cap) + RTW_INFO("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->cmn.aid, cur_beamform_cap); + + phtpriv_sta->beamform_cap = cur_beamform_cap; + psta->cmn.bf_info.ht_beamform_cap = cur_beamform_cap; + +} +#endif /*CONFIG_80211N_HT && CONFIG_BEAMFORMING*/ + /* notes: * AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode */ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) @@ -743,7 +1032,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; struct ht_priv *phtpriv_sta = &psta->htpriv; #endif /* CONFIG_80211N_HT */ - u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0; /* set intf_tag to if1 */ /* psta->intf_tag = 0; */ @@ -751,10 +1040,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) /*alloc macid when call rtw_alloc_stainfo(),release macid when call rtw_free_stainfo()*/ - /* ap mode */ - rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); - - if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) + if (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) psta->ieee8021x_blocked = _TRUE; else psta->ieee8021x_blocked = _FALSE; @@ -774,15 +1060,19 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) /* bwmode */ if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) - psta->bw_mode = CHANNEL_WIDTH_40; + psta->cmn.bw_mode = CHANNEL_WIDTH_40; else - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; + + if (phtpriv_sta->op_present + && !GET_HT_OP_ELE_STA_CHL_WIDTH(phtpriv_sta->ht_op)) + psta->cmn.bw_mode = CHANNEL_WIDTH_20; if (psta->ht_40mhz_intolerant) - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; - if (pmlmeext->cur_bwmode < psta->bw_mode) - psta->bw_mode = pmlmeext->cur_bwmode; + if (pmlmeext->cur_bwmode < psta->cmn.bw_mode) + psta->cmn.bw_mode = pmlmeext->cur_bwmode; phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; @@ -793,7 +1083,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) /* check if sta support s Short GI 40M */ if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) { - if (psta->bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */ + if (psta->cmn.bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */ phtpriv_sta->sgi_40m = _TRUE; else phtpriv_sta->sgi_40m = _FALSE; @@ -805,52 +1095,36 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) if (TEST_FLAG(phtpriv_ap->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP((u8 *)(&phtpriv_sta->ht_cap))) { SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX)); - RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->aid); + RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->cmn.aid); } /* B7 B8 B9 Config STBC setting */ if (TEST_FLAG(phtpriv_ap->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC((u8 *)(&phtpriv_sta->ht_cap))) { SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX)); - RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->aid); - } - -#ifdef CONFIG_BEAMFORMING - /*Config Tx beamforming setting*/ - if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && - GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP((u8 *)(&phtpriv_sta->ht_cap))) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); - /*Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ - SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 6); + RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->cmn.aid); } - if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && - GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP((u8 *)(&phtpriv_sta->ht_cap))) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); - /*Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ - SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4); - } - if (cur_beamform_cap) - RTW_INFO("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->aid, cur_beamform_cap); -#endif /*CONFIG_BEAMFORMING*/ + #ifdef CONFIG_BEAMFORMING + update_sta_info_apmode_ht_bf_cap(padapter, psta); + #endif } else { phtpriv_sta->ampdu_enable = _FALSE; phtpriv_sta->sgi_20m = _FALSE; phtpriv_sta->sgi_40m = _FALSE; - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; } phtpriv_sta->ldpc_cap = cur_ldpc_cap; phtpriv_sta->stbc_cap = cur_stbc_cap; - phtpriv_sta->beamform_cap = cur_beamform_cap; /* Rx AMPDU */ - send_delba(padapter, 0, psta->hwaddr);/* recipient */ + send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */ /* TX AMPDU */ - send_delba(padapter, 1, psta->hwaddr);/* */ /* originator */ + send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */ phtpriv_sta->agg_enable_bitmap = 0x0;/* reset */ phtpriv_sta->candidate_tid_bitmap = 0x0;/* reset */ #endif /* CONFIG_80211N_HT */ @@ -858,7 +1132,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) #ifdef CONFIG_80211AC_VHT update_sta_vht_info_apmode(padapter, psta); #endif - + psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta)); update_ldpc_stbc_cap(psta); /* todo: init other variables */ @@ -869,19 +1143,24 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) /* add ratid */ /* add_RATid(padapter, psta); */ /* move to ap_sta_info_defer_update() */ + /* ap mode */ + rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); _enter_critical_bh(&psta->lock, &irqL); - psta->state |= _FW_LINKED; - _exit_critical_bh(&psta->lock, &irqL); + /* Check encryption */ + if (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) + psta->state |= WIFI_UNDER_KEY_HANDSHAKE; + psta->state |= _FW_LINKED; + + _exit_critical_bh(&psta->lock, &irqL); } static void update_ap_info(_adapter *padapter, struct sta_info *psta) { struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; - struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); #ifdef CONFIG_80211N_HT struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; @@ -913,7 +1192,7 @@ static void update_ap_info(_adapter *padapter, struct sta_info *psta) phtpriv_ap->sgi_40m = _FALSE; } - psta->bw_mode = pmlmeext->cur_bwmode; + psta->cmn.bw_mode = pmlmeext->cur_bwmode; phtpriv_ap->ch_offset = pmlmeext->cur_ch_offset; phtpriv_ap->agg_enable_bitmap = 0x0;/* reset */ @@ -932,7 +1211,7 @@ static void update_ap_info(_adapter *padapter, struct sta_info *psta) static void rtw_set_hw_wmm_param(_adapter *padapter) { - u8 ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime; + u8 AIFS, ECWMin, ECWMax, aSifsTime; u8 acm_mask; u16 TXOP; u32 acParm, i; @@ -943,11 +1222,13 @@ static void rtw_set_hw_wmm_param(_adapter *padapter) struct registry_priv *pregpriv = &padapter->registrypriv; acm_mask = 0; - - if (is_supported_5g(pmlmeext->cur_wireless_mode) || - (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) +#ifdef CONFIG_80211N_HT + if (pregpriv->ht_enable && + (is_supported_5g(pmlmeext->cur_wireless_mode) || + (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))) aSifsTime = 16; else +#endif /* CONFIG_80211N_HT */ aSifsTime = 10; if (pmlmeinfo->WMM_enable == 0) { @@ -1077,12 +1358,11 @@ static void rtw_set_hw_wmm_param(_adapter *padapter) } } - +#ifdef CONFIG_80211N_HT static void update_hw_ht_param(_adapter *padapter) { unsigned char max_AMPDU_len; unsigned char min_MPDU_spacing; - struct registry_priv *pregpriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -1122,7 +1402,7 @@ static void update_hw_ht_param(_adapter *padapter) /* pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; */ } - +#endif /* CONFIG_80211N_HT */ static void rtw_ap_check_scan(_adapter *padapter) { _irqL irqL; @@ -1146,13 +1426,13 @@ static void rtw_ap_check_scan(_adapter *padapter) } _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); -#ifdef CONFIG_AUTO_CHNL_SEL_NHM +#ifdef CONFIG_RTW_ACS if (padapter->registrypriv.acs_auto_scan) { do_scan = _TRUE; reason |= RTW_AUTO_SCAN_REASON_ACS; - rtw_acs_start(padapter, _TRUE); + rtw_acs_start(padapter); } -#endif +#endif/*CONFIG_RTW_ACS*/ if (_TRUE == do_scan) { RTW_INFO("%s : drv scans by itself and wait_completed\n", __func__); @@ -1160,10 +1440,11 @@ static void rtw_ap_check_scan(_adapter *padapter) rtw_scan_wait_completed(padapter); } -#ifdef CONFIG_AUTO_CHNL_SEL_NHM +#ifdef CONFIG_RTW_ACS if (padapter->registrypriv.acs_auto_scan) - rtw_acs_start(padapter, _FALSE); + rtw_acs_stop(padapter); #endif + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); phead = get_list_head(queue); @@ -1176,7 +1457,7 @@ static void rtw_ap_check_scan(_adapter *padapter) pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); - if (rtw_chset_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 + if (rtw_chset_search_ch(adapter_to_chset(padapter), pnetwork->network.Configuration.DSConfig) >= 0 && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))) { delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned); @@ -1212,9 +1493,9 @@ static void rtw_ap_check_scan(_adapter *padapter) } _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - +#ifdef CONFIG_80211N_HT pmlmepriv->num_sta_no_ht = 0; /* reset to 0 after ap do scanning*/ - +#endif } void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter) @@ -1246,10 +1527,58 @@ void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter) update_ap_info(adapter, sta); } +#ifdef CONFIG_FW_HANDLE_TXBCN +bool rtw_ap_nums_check(_adapter *adapter) +{ + if (rtw_ap_get_nums(adapter) < CONFIG_LIMITED_AP_NUM) + return _TRUE; + return _FALSE; +} +u8 rtw_ap_allocate_vapid(struct dvobj_priv *dvobj) +{ + u8 vap_id; + + for (vap_id = 0; vap_id < CONFIG_LIMITED_AP_NUM; vap_id++) { + if (!(dvobj->vap_map & BIT(vap_id))) + break; + } + + if (vap_id < CONFIG_LIMITED_AP_NUM) + dvobj->vap_map |= BIT(vap_id); + + return vap_id; +} +u8 rtw_ap_release_vapid(struct dvobj_priv *dvobj, u8 vap_id) +{ + if (vap_id >= CONFIG_LIMITED_AP_NUM) { + RTW_ERR("%s - vapid(%d) failed\n", __func__, vap_id); + rtw_warn_on(1); + return _FAIL; + } + dvobj->vap_map &= ~ BIT(vap_id); + return _SUCCESS; +} +#endif +static void _rtw_iface_undersurvey_chk(const char *func, _adapter *adapter) +{ + int i; + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct mlme_priv *pmlmepriv; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if ((iface) && rtw_is_adapter_up(iface)) { + pmlmepriv = &iface->mlmepriv; + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) + RTW_ERR("%s ("ADPT_FMT") under survey\n", func, ADPT_ARG(iface)); + } + } +} void start_bss_network(_adapter *padapter, struct createbss_parm *parm) { #define DUMP_ADAPTERS_STATUS 0 - + u8 mlme_act = MLME_ACTION_UNKNOWN; u8 val8; u16 bcn_interval; u32 acparm; @@ -1261,22 +1590,31 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network); struct dvobj_priv *pdvobj = padapter->dvobj; - s16 req_ch = -1, req_bw = -1, req_offset = -1; - bool ch_setting_changed = _FALSE; + s16 req_ch = REQ_CH_NONE, req_bw = REQ_BW_NONE, req_offset = REQ_OFFSET_NONE; u8 ch_to_set = 0, bw_to_set, offset_to_set; u8 doiqk = _FALSE; /* use for check ch bw offset can be allowed or not */ u8 chbw_allow = _TRUE; + int i; + u8 ifbmp_ch_changed = 0; if (parm->req_ch != 0) { /* bypass other setting, go checking ch, bw, offset */ + mlme_act = MLME_OPCH_SWITCH; req_ch = parm->req_ch; req_bw = parm->req_bw; req_offset = parm->req_offset; goto chbw_decision; } else { - /* inform this request comes from upper layer */ + /* request comes from upper layer */ + if (MLME_IS_AP(padapter)) + mlme_act = MLME_AP_STARTED; + else if (MLME_IS_MESH(padapter)) + mlme_act = MLME_MESH_STARTED; + else + rtw_warn_on(1); req_ch = 0; + _rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length); } bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod; @@ -1312,7 +1650,9 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) if (pmlmepriv->cur_network.join_res != _TRUE) { /* setting only at first time */ /* WEP Key will be set before this function, do not clear CAM. */ - if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)) + if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_) + && !MLME_IS_MESH(padapter) /* mesh group key is set before this function */ + ) flush_all_cam_entry(padapter); /* clear CAM */ } @@ -1322,21 +1662,6 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) /* Set BSSID REG */ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pnetwork->MacAddress); - /* Set EDCA param reg */ -#ifdef CONFIG_CONCURRENT_MODE - acparm = 0x005ea42b; -#else - acparm = 0x002F3217; /* VO */ -#endif - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); - acparm = 0x005E4317; /* VI */ - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); - /* acparm = 0x00105320; */ /* BE */ - acparm = 0x005ea42b; - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); - acparm = 0x0000A444; /* BK */ - rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); - /* Set Security */ val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf; rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); @@ -1344,17 +1669,31 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) /* Beacon Control related register */ rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval)); + rtw_hal_rcr_set_chk_bssid(padapter, mlme_act); + chbw_decision: - ch_setting_changed = rtw_ap_chbw_decision(padapter, req_ch, req_bw, req_offset - , &ch_to_set, &bw_to_set, &offset_to_set, &chbw_allow); + ifbmp_ch_changed = rtw_ap_chbw_decision(padapter, parm->ifbmp, parm->excl_ifbmp + , req_ch, req_bw, req_offset + , &ch_to_set, &bw_to_set, &offset_to_set, &chbw_allow); + + for (i = 0; i < pdvobj->iface_nums; i++) { + if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i]) + continue; + + /* let pnetwork_mlme == pnetwork_mlmeext */ + _rtw_memcpy(&(pdvobj->padapters[i]->mlmepriv.cur_network.network) + , &(pdvobj->padapters[i]->mlmeextpriv.mlmext_info.network) + , pdvobj->padapters[i]->mlmeextpriv.mlmext_info.network.Length); - /* let pnetwork_mlmeext == pnetwork_mlme. */ - _rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length); + rtw_start_bss_hdl_after_chbw_decided(pdvobj->padapters[i]); - rtw_start_bss_hdl_after_chbw_decided(padapter); + /* Set EDCA param reg after update cur_wireless_mode & update_capinfo */ + if (pregpriv->wifi_spec == 1) + rtw_set_hw_wmm_param(pdvobj->padapters[i]); + } #if defined(CONFIG_DFS_MASTER) - rtw_dfs_master_status_apply(padapter, MLME_AP_STARTED); + rtw_dfs_rd_en_decision(padapter, mlme_act, parm->excl_ifbmp); #endif #ifdef CONFIG_MCC_MODE @@ -1377,8 +1716,10 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) rtw_hal_mcc_issue_null_data(padapter, chbw_allow, 1); #endif /* CONFIG_MCC_MODE */ - doiqk = _TRUE; - rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + if (!IS_CH_WAITING(adapter_to_rfctl(padapter))) { + doiqk = _TRUE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + } if (ch_to_set != 0) { set_channel_bwmode(padapter, ch_to_set, offset_to_set, bw_to_set); @@ -1393,70 +1734,124 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm) rtw_hal_set_mcc_setting_start_bss_network(padapter, chbw_allow); #endif +#if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + for (i = 0; i < pdvobj->iface_nums; i++) { + if (!(ifbmp_ch_changed & BIT(i)) || !pdvobj->padapters[i]) + continue; + + /* pure AP is not needed*/ + if (MLME_IS_GO(pdvobj->padapters[i]) + || MLME_IS_MESH(pdvobj->padapters[i]) + ) { + u8 ht_option = 0; + + #ifdef CONFIG_80211N_HT + ht_option = pdvobj->padapters[i]->mlmepriv.htpriv.ht_option; + #endif + + rtw_cfg80211_ch_switch_notify(pdvobj->padapters[i] + , pdvobj->padapters[i]->mlmeextpriv.cur_channel + , pdvobj->padapters[i]->mlmeextpriv.cur_bwmode + , pdvobj->padapters[i]->mlmeextpriv.cur_ch_offset + , ht_option); + } + } +#endif /* defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */ + if (DUMP_ADAPTERS_STATUS) { RTW_INFO(FUNC_ADPT_FMT" done\n", FUNC_ADPT_ARG(padapter)); dump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter)); } +#ifdef CONFIG_MCC_MODE update_beacon: - /* update beacon content only if bstart_bss is _TRUE */ - if (_TRUE == pmlmeext->bstart_bss) { +#endif - _irqL irqL; + for (i = 0; i < pdvobj->iface_nums; i++) { + struct mlme_priv *mlme; - if ((ATOMIC_READ(&pmlmepriv->olbc) == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc_ht) == _TRUE)) { - /* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */ + if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i]) + continue; - pmlmepriv->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK); - pmlmepriv->ht_op_mode |= OP_MODE_MAY_BE_LEGACY_STAS; - update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE); + /* update beacon content only if bstart_bss is _TRUE */ + if (pdvobj->padapters[i]->mlmeextpriv.bstart_bss != _TRUE) + continue; + + mlme = &(pdvobj->padapters[i]->mlmepriv); + + #ifdef CONFIG_80211N_HT + if ((ATOMIC_READ(&mlme->olbc) == _TRUE) || (ATOMIC_READ(&mlme->olbc_ht) == _TRUE)) { + /* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */ + mlme->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK); + mlme->ht_op_mode |= OP_MODE_MAY_BE_LEGACY_STAS; + update_beacon(pdvobj->padapters[i], _HT_ADD_INFO_IE_, NULL, _FALSE); } + #endif - update_beacon(padapter, _TIM_IE_, NULL, _FALSE); + update_beacon(pdvobj->padapters[i], _TIM_IE_, NULL, _FALSE); + } + + if (mlme_act != MLME_OPCH_SWITCH + && pmlmeext->bstart_bss == _TRUE + ) { +#ifdef CONFIG_SUPPORT_MULTI_BCN + _irqL irqL; -#ifdef CONFIG_SWTIMER_BASED_TXBCN _enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL); if (rtw_is_list_empty(&padapter->list)) { + #ifdef CONFIG_FW_HANDLE_TXBCN + padapter->vap_id = rtw_ap_allocate_vapid(pdvobj); + #endif rtw_list_insert_tail(&padapter->list, get_list_head(&pdvobj->ap_if_q)); pdvobj->nr_ap_if++; pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if; } _exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL); + #ifdef CONFIG_SWTIMER_BASED_TXBCN + rtw_ap_set_mbid_num(padapter, pdvobj->nr_ap_if); rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space)); + #endif /*CONFIG_SWTIMER_BASED_TXBCN*/ -#endif /*CONFIG_SWTIMER_BASED_TXBCN*/ +#endif /*CONFIG_SUPPORT_MULTI_BCN*/ + #ifdef CONFIG_HW_P0_TSF_SYNC + correct_TSF(padapter, mlme_act); + #endif } rtw_scan_wait_completed(padapter); + _rtw_iface_undersurvey_chk(__func__, padapter); /* send beacon */ - if (!rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY)) { - - /*update_beacon(padapter, _TIM_IE_, NULL, _TRUE);*/ - + ResumeTxBeacon(padapter); + { #if !defined(CONFIG_INTERRUPT_BASED_TXBCN) #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) #ifdef CONFIG_SWTIMER_BASED_TXBCN - if (pdvobj->nr_ap_if == 1) { + if (pdvobj->nr_ap_if == 1 + && mlme_act != MLME_OPCH_SWITCH + ) { RTW_INFO("start SW BCN TIMER!\n"); _set_timer(&pdvobj->txbcn_timer, bcn_interval); } #else - /* other case will tx beacon when bcn interrupt coming in. */ - if (send_beacon(padapter) == _FAIL) - RTW_INFO("issue_beacon, fail!\n"); + for (i = 0; i < pdvobj->iface_nums; i++) { + if (!(parm->ifbmp & BIT(i)) || !pdvobj->padapters[i]) + continue; + + if (send_beacon(pdvobj->padapters[i]) == _FAIL) + RTW_INFO(ADPT_FMT" issue_beacon, fail!\n", ADPT_ARG(pdvobj->padapters[i])); + } #endif #endif #endif /* !defined(CONFIG_INTERRUPT_BASED_TXBCN) */ - } - /*Set EDCA param reg after update cur_wireless_mode & update_capinfo*/ - if (pregpriv->wifi_spec == 1) - rtw_set_hw_wmm_param(padapter); - - /*pmlmeext->bstart_bss = _TRUE;*/ +#ifdef CONFIG_FW_HANDLE_TXBCN + if (mlme_act != MLME_OPCH_SWITCH) + rtw_ap_mbid_bcn_en(padapter, padapter->vap_id); +#endif + } } int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) @@ -1468,22 +1863,23 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) u16 cap, ht_cap = _FALSE; uint ie_len = 0; int group_cipher, pairwise_cipher; + u8 mfp_opt = MFP_NO; u8 channel, network_type, supportRate[NDIS_802_11_LENGTH_RATES_EX]; int supportRateNum = 0; u8 OUI1[] = {0x00, 0x50, 0xf2, 0x01}; - u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; + HT_CAP_AMPDU_DENSITY best_ampdu_density; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); WLAN_BSSID_EX *pbss_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; - struct sta_priv *pstapriv = &padapter->stapriv; u8 *ie = pbss_network->IEs; u8 vht_cap = _FALSE; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u8 rf_num = 0; - + int ret_rm; /* SSID */ /* Supported rates */ /* DS Params */ @@ -1497,7 +1893,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) RTW_INFO("%s, len=%d\n", __FUNCTION__, len); - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) return _FAIL; @@ -1511,8 +1907,12 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) _rtw_memcpy(ie, pbuf, pbss_network->IELength); - if (pbss_network->InfrastructureMode != Ndis802_11APMode) + if (pbss_network->InfrastructureMode != Ndis802_11APMode + && pbss_network->InfrastructureMode != Ndis802_11_mesh + ) { + rtw_warn_on(1); return _FAIL; + } rtw_ap_check_scan(padapter); @@ -1544,6 +1944,18 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) #endif } +#ifdef CONFIG_RTW_MESH + /* Mesh ID */ + if (MLME_IS_MESH(padapter)) { + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, WLAN_EID_MESH_ID, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) { + _rtw_memset(&pbss_network->mesh_id, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(pbss_network->mesh_id.Ssid, (p + 2), ie_len); + pbss_network->mesh_id.SsidLength = ie_len; + } + } +#endif + /* chnnel */ channel = 0; pbss_network->Configuration.Length = 0; @@ -1558,6 +1970,13 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) /* get supported rates */ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); if (p != NULL) { + if (padapter->registrypriv.wireless_mode == WIRELESS_11B) { + ret_rm = rtw_remove_ie_g_rate(ie , &len, _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_); + RTW_DBG("%s, rtw_remove_ie_g_rate=%d\n", __FUNCTION__,ret_rm); + ie_len = ie_len - ret_rm; + pbss_network->IELength=pbss_network->IELength - ret_rm; + } + RTW_DBG("%s, ie_len=%u\n", __FUNCTION__, ie_len); _rtw_memcpy(supportRate, p + 2, ie_len); supportRateNum = ie_len; } @@ -1565,8 +1984,15 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) /* get ext_supported rates */ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->IELength - _BEACON_IE_OFFSET_); if (p != NULL) { - _rtw_memcpy(supportRate + supportRateNum, p + 2, ie_len); - supportRateNum += ie_len; + if (padapter->registrypriv.wireless_mode == WIRELESS_11B) { + pbss_network->IELength = pbss_network->IELength-*(p+1) -2; + ret_rm = rtw_ies_remove_ie(ie , &len,_BEACON_IE_OFFSET_, + _EXT_SUPPORTEDRATES_IE_,NULL,0); + RTW_DBG("%s, remove_ie of ext_supported rates =%d\n", __FUNCTION__, ret_rm); + } else { + _rtw_memcpy(supportRate + supportRateNum, p + 2, ie_len); + supportRateNum += ie_len; + } } @@ -1577,8 +2003,16 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) /* parsing ERP_IE */ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); - if (p && ie_len > 0) - ERP_IE_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p); + if (p && ie_len > 0) { + if(padapter->registrypriv.wireless_mode == WIRELESS_11B ) { + + pbss_network->IELength = pbss_network->IELength - *(p+1) - 2; + ret_rm = rtw_ies_remove_ie(ie , &len, _BEACON_IE_OFFSET_, _ERPINFO_IE_,NULL,0); + RTW_DBG("%s, remove_ie of ERP_IE=%d\n", __FUNCTION__, ret_rm); + } else + ERP_IE_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p); + + } /* update privacy/security */ if (cap & BIT(4)) @@ -1595,9 +2029,9 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_; p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); if (p && ie_len > 0) { - if (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + if (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) { psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; - + psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; psecuritypriv->dot8021xalg = 1;/* psk, todo:802.1x */ psecuritypriv->wpa_psk |= BIT(1); @@ -1655,7 +2089,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) if ((p) && (_rtw_memcmp(p + 2, OUI1, 4))) { if (rtw_parse_wpa_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; - + psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK; psecuritypriv->dot8021xalg = 1;/* psk, todo:802.1x */ psecuritypriv->wpa_psk |= BIT(0); @@ -1711,9 +2145,26 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) } +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* MFP is mandatory for secure mesh */ + if (padapter->mesh_info.mesh_auth_id) + mfp_opt = MFP_REQUIRED; + } else +#endif + if (mfp_opt == MFP_INVALID) { + RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter)); + return _FAIL; + } + psecuritypriv->mfp_opt = mfp_opt; + /* wmm */ ie_len = 0; pmlmepriv->qospriv.qos_option = 0; +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + pmlmepriv->qospriv.qos_option = 1; +#endif if (pregistrypriv->wmm_enable) { for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) { p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); @@ -1728,6 +2179,8 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) *(p + 18) &= ~BIT(4); /* VI */ *(p + 22) &= ~BIT(4); /* VO */ + WMM_param_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p); + break; } @@ -1736,126 +2189,138 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) } } #ifdef CONFIG_80211N_HT - /* parsing HT_CAP_IE */ - p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); - if (p && ie_len > 0) { - u8 rf_type = 0; - HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor = MAX_AMPDU_FACTOR_64K; - struct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2); - - if (0) { - RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE from upper layer:\n", FUNC_ADPT_ARG(padapter)); - dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len); - } + if(padapter->registrypriv.ht_enable && + is_supported_ht(padapter->registrypriv.wireless_mode)) { + /* parsing HT_CAP_IE */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) { + u8 rf_type = 0; + HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor = MAX_AMPDU_FACTOR_64K; + struct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2); + + if (0) { + RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE from upper layer:\n", FUNC_ADPT_ARG(padapter)); + dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len); + } - pHT_caps_ie = p; + pHT_caps_ie = p; - ht_cap = _TRUE; - network_type |= WIRELESS_11_24N; + ht_cap = _TRUE; + network_type |= WIRELESS_11_24N; - rtw_ht_use_default_setting(padapter); + rtw_ht_use_default_setting(padapter); - /* Update HT Capabilities Info field */ - if (pmlmepriv->htpriv.sgi_20m == _FALSE) - pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_20); + /* Update HT Capabilities Info field */ + if (pmlmepriv->htpriv.sgi_20m == _FALSE) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_20); - if (pmlmepriv->htpriv.sgi_40m == _FALSE) - pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_40); + if (pmlmepriv->htpriv.sgi_40m == _FALSE) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_40); - if (!TEST_FLAG(pmlmepriv->htpriv.ldpc_cap, LDPC_HT_ENABLE_RX)) - pht_cap->cap_info &= ~(IEEE80211_HT_CAP_LDPC_CODING); + if (!TEST_FLAG(pmlmepriv->htpriv.ldpc_cap, LDPC_HT_ENABLE_RX)) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_LDPC_CODING); - if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_TX)) - pht_cap->cap_info &= ~(IEEE80211_HT_CAP_TX_STBC); + if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_TX)) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_TX_STBC); - if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_RX)) - pht_cap->cap_info &= ~(IEEE80211_HT_CAP_RX_STBC_3R); + if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_RX)) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_RX_STBC_3R); - /* Update A-MPDU Parameters field */ - pht_cap->ampdu_params_info &= ~(IEEE80211_HT_CAP_AMPDU_FACTOR | IEEE80211_HT_CAP_AMPDU_DENSITY); + /* Update A-MPDU Parameters field */ + pht_cap->ampdu_params_info &= ~(IEEE80211_HT_CAP_AMPDU_FACTOR | IEEE80211_HT_CAP_AMPDU_DENSITY); - if ((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) || - (psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) - pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (0x07 << 2)); - else - pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00); + if ((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) || + (psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) { + rtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density); + pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2)); + } else + pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00); - rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); - pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_FACTOR & max_rx_ampdu_factor); /* set Max Rx AMPDU size to 64K */ + rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); + pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_FACTOR & max_rx_ampdu_factor); /* set Max Rx AMPDU size to 64K */ - _rtw_memcpy(&(pmlmeinfo->HT_caps), pht_cap, sizeof(struct HT_caps_element)); + _rtw_memcpy(&(pmlmeinfo->HT_caps), pht_cap, sizeof(struct HT_caps_element)); - /* Update Supported MCS Set field */ - { - struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); - u8 rx_nss = 0; - int i; + /* Update Supported MCS Set field */ + { + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + u8 rx_nss = 0; + int i; - rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); - rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num); + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num); - /* RX MCS Bitmask */ - switch (rx_nss) { - case 1: - set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_1R); - break; - case 2: - set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_2R); - break; - case 3: - set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_3R); - break; - case 4: - set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_4R); - break; - default: - RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", rf_type, hal_spec->rx_nss_num); + /* RX MCS Bitmask */ + switch (rx_nss) { + case 1: + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_1R); + break; + case 2: + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_2R); + break; + case 3: + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_3R); + break; + case 4: + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_4R); + break; + default: + RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", rf_type, hal_spec->rx_nss_num); + } + for (i = 0; i < 10; i++) + *(HT_CAP_ELE_RX_MCS_MAP(pht_cap) + i) &= padapter->mlmeextpriv.default_supported_mcs_set[i]; } - for (i = 0; i < 10; i++) - *(HT_CAP_ELE_RX_MCS_MAP(pht_cap) + i) &= padapter->mlmeextpriv.default_supported_mcs_set[i]; - } #ifdef CONFIG_BEAMFORMING - /* Use registry value to enable HT Beamforming. */ - /* ToDo: use configure file to set these capability. */ - pht_cap->tx_BF_cap_info = 0; - - /* HT Beamformer */ - if (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { - /* Transmit NDP Capable */ - SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(pht_cap, 1); - /* Explicit Compressed Steering Capable */ - SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pht_cap, 1); - /* Compressed Steering Number Antennas */ - SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, 1); - rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num); - SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pht_cap, rf_num); - } + /* Use registry value to enable HT Beamforming. */ + /* ToDo: use configure file to set these capability. */ + pht_cap->tx_BF_cap_info = 0; + + /* HT Beamformer */ + if (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { + /* Transmit NDP Capable */ + SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(pht_cap, 1); + /* Explicit Compressed Steering Capable */ + SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pht_cap, 1); + /* Compressed Steering Number Antennas */ + SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, 1); + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num); + SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pht_cap, rf_num); + } - /* HT Beamformee */ - if (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) { - /* Receive NDP Capable */ - SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(pht_cap, 1); - /* Explicit Compressed Beamforming Feedback Capable */ - SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pht_cap, 2); - rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); - SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, rf_num); - } + /* HT Beamformee */ + if (TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) { + /* Receive NDP Capable */ + SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(pht_cap, 1); + /* Explicit Compressed Beamforming Feedback Capable */ + SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pht_cap, 2); + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); + SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, rf_num); + } #endif /* CONFIG_BEAMFORMING */ - _rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p + 2, ie_len); + _rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p + 2, ie_len); - if (0) { - RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE driver masked:\n", FUNC_ADPT_ARG(padapter)); - dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len); + if (0) { + RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE driver masked:\n", FUNC_ADPT_ARG(padapter)); + dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len); + } } - } - /* parsing HT_INFO_IE */ - p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); - if (p && ie_len > 0) - pHT_info_ie = p; + /* parsing HT_INFO_IE */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) { + pHT_info_ie = p; + if (channel == 0) + pbss_network->Configuration.DSConfig = GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2); + else if (channel != GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2)) { + RTW_INFO(FUNC_ADPT_FMT" ch inconsistent, DSSS:%u, HT primary:%u\n" + , FUNC_ADPT_ARG(padapter), channel, GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2)); + } + } + } #endif /* CONFIG_80211N_HT */ + switch (network_type) { case WIRELESS_11B: pbss_network->NetworkTypeInUse = Ndis802_11DS; @@ -1886,7 +2351,9 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) } /* ht_cap */ - if (pregistrypriv->ht_enable && ht_cap == _TRUE) { + if (padapter->registrypriv.ht_enable && + is_supported_ht(padapter->registrypriv.wireless_mode) && ht_cap == _TRUE) { + pmlmepriv->htpriv.ht_option = _TRUE; pmlmepriv->qospriv.qos_option = 1; @@ -1899,53 +2366,43 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) #endif #ifdef CONFIG_80211AC_VHT - - /* Parsing VHT CAP IE */ - p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); - if (p && ie_len > 0) - vht_cap = _TRUE; - /* Parsing VHT OPERATION IE */ - - + pmlmepriv->ori_vht_en = 0; pmlmepriv->vhtpriv.vht_option = _FALSE; - /* if channel in 5G band, then add vht ie . */ - if ((pbss_network->Configuration.DSConfig > 14) - && (pmlmepriv->htpriv.ht_option == _TRUE) - && REGSTY_IS_11AC_ENABLE(pregistrypriv) - && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent)) - ) { - if (vht_cap == _TRUE) - pmlmepriv->vhtpriv.vht_option = _TRUE; - else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) { - u8 cap_len, operation_len; - - rtw_vht_use_default_setting(padapter); - - { - /* VHT Operation mode notifiy bit in Extended IE (127) */ - uint len = 0; - - SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1); - pmlmepriv->ext_capab_ie_len = 10; - rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); - pbss_network->IELength += pmlmepriv->ext_capab_ie_len; - } - /* VHT Capabilities element */ - cap_len = rtw_build_vht_cap_ie(padapter, pbss_network->IEs + pbss_network->IELength); - pbss_network->IELength += cap_len; + if (pmlmepriv->htpriv.ht_option == _TRUE + && pbss_network->Configuration.DSConfig > 14 + && REGSTY_IS_11AC_ENABLE(pregistrypriv) + && is_supported_vht(pregistrypriv->wireless_mode) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) + ) { + /* Parsing VHT CAP IE */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) + vht_cap = _TRUE; - /* VHT Operation element */ - operation_len = rtw_build_vht_operation_ie(padapter, pbss_network->IEs + pbss_network->IELength, pbss_network->Configuration.DSConfig); - pbss_network->IELength += operation_len; + /* Parsing VHT OPERATION IE */ + if (vht_cap == _TRUE + && MLME_IS_MESH(padapter) /* allow only mesh temporarily before VHT IE checking is ready */ + ) { + rtw_check_for_vht20(padapter, ie + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_); + pmlmepriv->ori_vht_en = 1; pmlmepriv->vhtpriv.vht_option = _TRUE; + } else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) { + rtw_vht_ies_detach(padapter, pbss_network); + rtw_vht_ies_attach(padapter, pbss_network); } } + + if (pmlmepriv->vhtpriv.vht_option == _FALSE) + rtw_vht_ies_detach(padapter, pbss_network); #endif /* CONFIG_80211AC_VHT */ - if(pbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1) { +#ifdef CONFIG_80211N_HT + if(padapter->registrypriv.ht_enable && + is_supported_ht(padapter->registrypriv.wireless_mode) && + pbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1 && + pbss_network->IELength + 10 <= MAX_IE_SZ) { uint len = 0; SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1); @@ -1953,11 +2410,12 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); pbss_network->IELength += pmlmepriv->ext_capab_ie_len; } +#endif /* CONFIG_80211N_HT */ pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network); rtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_ - , &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset); + , &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset, 1, 1); rtw_warn_on(pmlmepriv->ori_ch == 0); { @@ -1993,14 +2451,24 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) } #if CONFIG_RTW_MACADDR_ACL -void rtw_macaddr_acl_init(_adapter *adapter) +void rtw_macaddr_acl_init(_adapter *adapter, u8 period) { struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; - _queue *acl_node_q = &acl->acl_node_q; + struct wlan_acl_pool *acl; + _queue *acl_node_q; int i; _irqL irqL; + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + return; + } + + acl = &stapriv->acl_list[period]; + acl_node_q = &acl->acl_node_q; + + _rtw_spinlock_init(&(acl_node_q->lock)); + _enter_critical_bh(&(acl_node_q->lock), &irqL); _rtw_init_listhead(&(acl_node_q->queue)); acl->num = 0; @@ -2012,15 +2480,23 @@ void rtw_macaddr_acl_init(_adapter *adapter) _exit_critical_bh(&(acl_node_q->lock), &irqL); } -void rtw_macaddr_acl_deinit(_adapter *adapter) +static void _rtw_macaddr_acl_deinit(_adapter *adapter, u8 period, bool clear_only) { struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; - _queue *acl_node_q = &acl->acl_node_q; + struct wlan_acl_pool *acl; + _queue *acl_node_q; _irqL irqL; _list *head, *list; struct rtw_wlan_acl_node *acl_node; + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + return; + } + + acl = &stapriv->acl_list[period]; + acl_node_q = &acl->acl_node_q; + _enter_critical_bh(&(acl_node_q->lock), &irqL); head = get_list_head(acl_node_q); list = get_next(head); @@ -2036,24 +2512,42 @@ void rtw_macaddr_acl_deinit(_adapter *adapter) } _exit_critical_bh(&(acl_node_q->lock), &irqL); + if (!clear_only) + _rtw_spinlock_free(&(acl_node_q->lock)); + rtw_warn_on(acl->num); acl->mode = RTW_ACL_MODE_DISABLED; } -void rtw_set_macaddr_acl(_adapter *adapter, int mode) +void rtw_macaddr_acl_deinit(_adapter *adapter, u8 period) +{ + _rtw_macaddr_acl_deinit(adapter, period, 0); +} + +void rtw_macaddr_acl_clear(_adapter *adapter, u8 period) +{ + _rtw_macaddr_acl_deinit(adapter, period, 1); +} + +void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode) { struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; + struct wlan_acl_pool *acl; - RTW_INFO(FUNC_ADPT_FMT" mode=%d\n", FUNC_ADPT_ARG(adapter), mode); + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + return; + } - acl->mode = mode; + acl = &stapriv->acl_list[period]; - if (mode == RTW_ACL_MODE_DISABLED) - rtw_macaddr_acl_deinit(adapter); + RTW_INFO(FUNC_ADPT_FMT" p=%u, mode=%d\n" + , FUNC_ADPT_ARG(adapter), period, mode); + + acl->mode = mode; } -int rtw_acl_add_sta(_adapter *adapter, const u8 *addr) +int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr) { _irqL irqL; _list *list, *head; @@ -2061,8 +2555,17 @@ int rtw_acl_add_sta(_adapter *adapter, const u8 *addr) int i = -1, ret = 0; struct rtw_wlan_acl_node *acl_node; struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; - _queue *acl_node_q = &acl->acl_node_q; + struct wlan_acl_pool *acl; + _queue *acl_node_q; + + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + ret = -1; + goto exit; + } + + acl = &stapriv->acl_list[period]; + acl_node_q = &acl->acl_node_q; _enter_critical_bh(&(acl_node_q->lock), &irqL); @@ -2109,26 +2612,34 @@ int rtw_acl_add_sta(_adapter *adapter, const u8 *addr) if (!existed && (i < 0 || i >= NUM_ACL)) ret = -1; - RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" %s (acl_num=%d)\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(addr) + RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n" + , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr) , (existed ? "existed" : ((i < 0 || i >= NUM_ACL) ? "no room" : "added")) , acl->num); - +exit: return ret; } -int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr) +int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr) { _irqL irqL; _list *list, *head; int ret = 0; struct rtw_wlan_acl_node *acl_node; struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; - _queue *acl_node_q = &acl->acl_node_q; + struct wlan_acl_pool *acl; + _queue *acl_node_q; u8 is_baddr = is_broadcast_mac_addr(addr); u8 match = 0; + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + goto exit; + } + + acl = &stapriv->acl_list[period]; + acl_node_q = &acl->acl_node_q; + _enter_critical_bh(&(acl_node_q->lock), &irqL); head = get_list_head(acl_node_q); @@ -2150,51 +2661,59 @@ int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr) _exit_critical_bh(&(acl_node_q->lock), &irqL); - RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" %s (acl_num=%d)\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(addr) + RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n" + , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr) , is_baddr ? "clear all" : (match ? "match" : "no found") , acl->num); +exit: return ret; } #endif /* CONFIG_RTW_MACADDR_ACL */ -u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta) +u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk) { - struct cmd_obj *ph2c; - struct set_stakey_parm *psetstakey_para; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_obj *cmd; + struct set_stakey_parm *param; u8 res = _SUCCESS; - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { res = _FAIL; goto exit; } - psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); - if (psetstakey_para == NULL) { - rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + param = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); + if (param == NULL) { + rtw_mfree((u8 *) cmd, sizeof(struct cmd_obj)); res = _FAIL; goto exit; } - init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); - - - psetstakey_para->algorithm = (u8)psta->dot118021XPrivacy; - - _rtw_memcpy(psetstakey_para->addr, psta->hwaddr, ETH_ALEN); + init_h2fwcmd_w_parm_no_rsp(cmd, param, _SetStaKey_CMD_); - _rtw_memcpy(psetstakey_para->key, &psta->dot118021x_UncstKey, 16); + _rtw_memcpy(param->addr, addr, ETH_ALEN); + param->algorithm = alg; + param->keyid = keyid; + _rtw_memcpy(param->key, key, 16); + param->gk = gk; - - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(cmdpriv, cmd); exit: - return res; +} +u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta) +{ + return rtw_ap_set_sta_key(padapter + , psta->cmn.mac_addr + , psta->dot118021XPrivacy + , psta->dot118021x_UncstKey.skey + , 0 + , 0 + ); } static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set_tx) @@ -2311,7 +2830,7 @@ u8 rtw_ap_bmc_frames_hdl(_adapter *padapter) _enter_critical_bh(&pxmitpriv->lock, &irqL); - if ((pstapriv->tim_bitmap & BIT(0)) && (psta_bmc->sleepq_len > 0)) { + if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) { int tx_counts = 0; _update_beacon(padapter, _TIM_IE_, NULL, _FALSE, "update TIM with TIB=1"); @@ -2356,11 +2875,11 @@ u8 rtw_ap_bmc_frames_hdl(_adapter *padapter) /*RTW_INFO("sleepq_len of bmc_sta = %d\n", psta_bmc->sleepq_len);*/ - if (pstapriv->tim_bitmap & BIT(0)) + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) update_tim = _TRUE; - pstapriv->tim_bitmap &= ~BIT(0); - pstapriv->sta_dz_bitmap &= ~BIT(0); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0); + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0); if (update_tim == _TRUE) { RTW_INFO("clear TIB\n"); @@ -2393,13 +2912,13 @@ static void associated_stainfo_update(_adapter *padapter, struct sta_info *psta, { struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->hwaddr), sta_info_type); - + RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->cmn.mac_addr), sta_info_type); +#ifdef CONFIG_80211N_HT if (sta_info_type & STA_INFO_UPDATE_BW) { if ((psta->flags & WLAN_STA_HT) && !psta->ht_20mhz_set) { if (pmlmepriv->sw_to_20mhz) { - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; /*psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;*/ psta->htpriv.sgi_40m = _FALSE; } else { @@ -2407,7 +2926,7 @@ static void associated_stainfo_update(_adapter *padapter, struct sta_info *psta, } } } - +#endif /* CONFIG_80211N_HT */ /* if (sta_info_type & STA_INFO_UPDATE_RATE) { @@ -2454,12 +2973,6 @@ static void update_bcn_ext_capab_ie(_adapter *padapter) } -static void update_bcn_fixed_ie(_adapter *padapter) -{ - RTW_INFO("%s\n", __FUNCTION__); - -} - static void update_bcn_erpinfo_ie(_adapter *padapter) { struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -2502,6 +3015,7 @@ static void update_bcn_htcap_ie(_adapter *padapter) static void update_bcn_htinfo_ie(_adapter *padapter) { +#ifdef CONFIG_80211N_HT /* u8 beacon_updated = _FALSE; u32 sta_info_update_type = STA_INFO_UPDATE_NONE; @@ -2580,7 +3094,7 @@ static void update_bcn_htinfo_ie(_adapter *padapter) } /*associated_clients_update(padapter, beacon_updated, sta_info_update_type);*/ - +#endif /* CONFIG_80211N_HT */ } static void update_bcn_rsn_ie(_adapter *padapter) @@ -2695,83 +3209,70 @@ void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *ta { _irqL irqL; struct mlme_priv *pmlmepriv; - struct mlme_ext_priv *pmlmeext; - /* struct mlme_ext_info *pmlmeinfo; */ - - /* RTW_INFO("%s\n", __FUNCTION__); */ + struct mlme_ext_priv *pmlmeext; + bool updated = 1; /* treat as upadated by default */ if (!padapter) return; pmlmepriv = &(padapter->mlmepriv); pmlmeext = &(padapter->mlmeextpriv); - /* pmlmeinfo = &(pmlmeext->mlmext_info); */ - if (_FALSE == pmlmeext->bstart_bss) + if (pmlmeext->bstart_bss == _FALSE) return; _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); switch (ie_id) { - case 0xFF: - - update_bcn_fixed_ie(padapter);/* 8: TimeStamp, 2: Beacon Interval 2:Capability */ - - break; - case _TIM_IE_: - update_BCNTIM(padapter); - break; case _ERPINFO_IE_: - update_bcn_erpinfo_ie(padapter); - break; case _HT_CAPABILITY_IE_: - update_bcn_htcap_ie(padapter); - break; case _RSN_IE_2_: - update_bcn_rsn_ie(padapter); - break; case _HT_ADD_INFO_IE_: - update_bcn_htinfo_ie(padapter); - break; case _EXT_CAP_IE_: - update_bcn_ext_capab_ie(padapter); + break; +#ifdef CONFIG_RTW_MESH + case WLAN_EID_MESH_CONFIG: + updated = rtw_mesh_update_bss_peering_status(padapter, &(pmlmeext->mlmext_info.network)); + updated |= rtw_mesh_update_bss_formation_info(padapter, &(pmlmeext->mlmext_info.network)); + updated |= rtw_mesh_update_bss_forwarding_state(padapter, &(pmlmeext->mlmext_info.network)); break; +#endif case _VENDOR_SPECIFIC_IE_: - update_bcn_vendor_spec_ie(padapter, oui); - break; + case 0xFF: default: break; } - pmlmepriv->update_bcn = _TRUE; + if (updated) + pmlmepriv->update_bcn = _TRUE; _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); #ifndef CONFIG_INTERRUPT_BASED_TXBCN #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - if (tx) { + if (tx && updated) { /* send_beacon(padapter); */ /* send_beacon must execute on TSR level */ if (0) RTW_INFO(FUNC_ADPT_FMT" ie_id:%u - %s\n", FUNC_ADPT_ARG(padapter), ie_id, tag); @@ -2783,7 +3284,6 @@ void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *ta } #endif #endif /* !CONFIG_INTERRUPT_BASED_TXBCN */ - } #ifdef CONFIG_80211N_HT @@ -3020,11 +3520,8 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_preamble++; if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && - (pmlmepriv->num_sta_no_short_preamble == 1)) { + (pmlmepriv->num_sta_no_short_preamble == 1)) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } - } } else { if (psta->no_short_preamble_set) { @@ -3033,11 +3530,8 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_preamble--; if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && - (pmlmepriv->num_sta_no_short_preamble == 0)) { + (pmlmepriv->num_sta_no_short_preamble == 0)) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } - } } @@ -3058,7 +3552,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) if (pmlmepriv->num_sta_non_erp == 1) { beacon_updated = _TRUE; - update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE); } } @@ -3070,7 +3564,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) if (pmlmepriv->num_sta_non_erp == 0) { beacon_updated = _TRUE; - update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE); } } @@ -3095,11 +3589,8 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_slot_time++; if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && - (pmlmepriv->num_sta_no_short_slot_time == 1)) { + (pmlmepriv->num_sta_no_short_slot_time == 1)) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } - } } else { if (psta->no_short_slot_time_set) { @@ -3108,68 +3599,89 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_no_short_slot_time--; if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && - (pmlmepriv->num_sta_no_short_slot_time == 0)) { + (pmlmepriv->num_sta_no_short_slot_time == 0)) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } } } #ifdef CONFIG_80211N_HT + if(padapter->registrypriv.ht_enable && + is_supported_ht(padapter->registrypriv.wireless_mode)) { + if (psta->flags & WLAN_STA_HT) { + u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info); - if (psta->flags & WLAN_STA_HT) { - u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info); + RTW_INFO("HT: STA " MAC_FMT " HT Capabilities Info: 0x%04x\n", + MAC_ARG(psta->cmn.mac_addr), ht_capab); - RTW_INFO("HT: STA " MAC_FMT " HT Capabilities " - "Info: 0x%04x\n", MAC_ARG(psta->hwaddr), ht_capab); + if (psta->no_ht_set) { + psta->no_ht_set = 0; + pmlmepriv->num_sta_no_ht--; + } - if (psta->no_ht_set) { - psta->no_ht_set = 0; - pmlmepriv->num_sta_no_ht--; - } + if ((ht_capab & IEEE80211_HT_CAP_GRN_FLD) == 0) { + if (!psta->no_ht_gf_set) { + psta->no_ht_gf_set = 1; + pmlmepriv->num_sta_ht_no_gf++; + } + RTW_INFO("%s STA " MAC_FMT " - no " + "greenfield, num of non-gf stations %d\n", + __FUNCTION__, MAC_ARG(psta->cmn.mac_addr), + pmlmepriv->num_sta_ht_no_gf); + } - if ((ht_capab & IEEE80211_HT_CAP_GRN_FLD) == 0) { - if (!psta->no_ht_gf_set) { - psta->no_ht_gf_set = 1; - pmlmepriv->num_sta_ht_no_gf++; + if ((ht_capab & IEEE80211_HT_CAP_SUP_WIDTH) == 0) { + if (!psta->ht_20mhz_set) { + psta->ht_20mhz_set = 1; + pmlmepriv->num_sta_ht_20mhz++; + } + RTW_INFO("%s STA " MAC_FMT " - 20 MHz HT, " + "num of 20MHz HT STAs %d\n", + __FUNCTION__, MAC_ARG(psta->cmn.mac_addr), + pmlmepriv->num_sta_ht_20mhz); } - RTW_INFO("%s STA " MAC_FMT " - no " - "greenfield, num of non-gf stations %d\n", - __FUNCTION__, MAC_ARG(psta->hwaddr), - pmlmepriv->num_sta_ht_no_gf); - } - if ((ht_capab & IEEE80211_HT_CAP_SUP_WIDTH) == 0) { - if (!psta->ht_20mhz_set) { - psta->ht_20mhz_set = 1; - pmlmepriv->num_sta_ht_20mhz++; + if (((ht_capab & RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT) != 0) && + (psta->ht_40mhz_intolerant == 0)) { + psta->ht_40mhz_intolerant = 1; + pmlmepriv->num_sta_40mhz_intolerant++; + RTW_INFO("%s STA " MAC_FMT " - 40MHZ_INTOLERANT, ", + __FUNCTION__, MAC_ARG(psta->cmn.mac_addr)); } - RTW_INFO("%s STA " MAC_FMT " - 20 MHz HT, " - "num of 20MHz HT STAs %d\n", - __FUNCTION__, MAC_ARG(psta->hwaddr), - pmlmepriv->num_sta_ht_20mhz); - } - } else { - if (!psta->no_ht_set) { - psta->no_ht_set = 1; - pmlmepriv->num_sta_no_ht++; + } else { + if (!psta->no_ht_set) { + psta->no_ht_set = 1; + pmlmepriv->num_sta_no_ht++; + } + if (pmlmepriv->htpriv.ht_option == _TRUE) { + RTW_INFO("%s STA " MAC_FMT + " - no HT, num of non-HT stations %d\n", + __FUNCTION__, MAC_ARG(psta->cmn.mac_addr), + pmlmepriv->num_sta_no_ht); + } } - if (pmlmepriv->htpriv.ht_option == _TRUE) { - RTW_INFO("%s STA " MAC_FMT - " - no HT, num of non-HT stations %d\n", - __FUNCTION__, MAC_ARG(psta->hwaddr), - pmlmepriv->num_sta_no_ht); + + if (rtw_ht_operation_update(padapter) > 0) { + update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE); + beacon_updated = _TRUE; } } +#endif /* CONFIG_80211N_HT */ - if (rtw_ht_operation_update(padapter) > 0) { - update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); - update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); - /*beacon_updated = _TRUE;*/ +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + struct sta_priv *pstapriv = &padapter->stapriv; + + update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE); + if (pstapriv->asoc_list_cnt == 1) + _set_timer(&padapter->mesh_atlm_param_req_timer, 0); + beacon_updated = _TRUE; } +#endif -#endif /* CONFIG_80211N_HT */ + if (beacon_updated) + update_beacon(padapter, 0xFF, NULL, _TRUE); /* update associcated stations cap. */ associated_clients_update(padapter, beacon_updated, STA_INFO_UPDATE_ALL); @@ -3181,20 +3693,25 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) { u8 beacon_updated = _FALSE; + struct sta_priv *pstapriv = &padapter->stapriv; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); if (!psta) return beacon_updated; + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) { + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); + beacon_updated = _TRUE; + update_beacon(padapter, _TIM_IE_, NULL, _FALSE); + } + if (psta->no_short_preamble_set) { psta->no_short_preamble_set = 0; pmlmepriv->num_sta_no_short_preamble--; if (pmlmeext->cur_wireless_mode > WIRELESS_11B - && pmlmepriv->num_sta_no_short_preamble == 0) { + && pmlmepriv->num_sta_no_short_preamble == 0) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } } if (psta->nonerp_set) { @@ -3202,7 +3719,7 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_non_erp--; if (pmlmepriv->num_sta_non_erp == 0) { beacon_updated = _TRUE; - update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE); } } @@ -3210,14 +3727,11 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) psta->no_short_slot_time_set = 0; pmlmepriv->num_sta_no_short_slot_time--; if (pmlmeext->cur_wireless_mode > WIRELESS_11B - && pmlmepriv->num_sta_no_short_slot_time == 0) { + && pmlmepriv->num_sta_no_short_slot_time == 0) beacon_updated = _TRUE; - update_beacon(padapter, 0xFF, NULL, _TRUE); - } } #ifdef CONFIG_80211N_HT - if (psta->no_ht_gf_set) { psta->no_ht_gf_set = 0; pmlmepriv->num_sta_ht_no_gf--; @@ -3233,15 +3747,32 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) pmlmepriv->num_sta_ht_20mhz--; } - + if (psta->ht_40mhz_intolerant) { + psta->ht_40mhz_intolerant = 0; + if (pmlmepriv->num_sta_40mhz_intolerant > 0) + pmlmepriv->num_sta_40mhz_intolerant--; + else + rtw_warn_on(1); + } if (rtw_ht_operation_update(padapter) > 0) { update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); - update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE); } - #endif /* CONFIG_80211N_HT */ +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE); + if (pstapriv->asoc_list_cnt == 0) + _cancel_timer_ex(&padapter->mesh_atlm_param_req_timer); + beacon_updated = _TRUE; + } +#endif + + if (beacon_updated == _TRUE) + update_beacon(padapter, 0xFF, NULL, _TRUE); + #if 0 /* update associated stations cap. */ associated_clients_update(padapter, beacon_updated, STA_INFO_UPDATE_ALL); /* move it to avoid deadlock */ @@ -3257,9 +3788,6 @@ u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reaso { _irqL irqL; u8 beacon_updated = _FALSE; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct sta_priv *pstapriv = &padapter->stapriv; if (!psta) return beacon_updated; @@ -3267,54 +3795,56 @@ u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reaso if (active == _TRUE) { #ifdef CONFIG_80211N_HT /* tear down Rx AMPDU */ - send_delba(padapter, 0, psta->hwaddr);/* recipient */ + send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */ /* tear down TX AMPDU */ - send_delba(padapter, 1, psta->hwaddr);/* */ /* originator */ + send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */ #endif /* CONFIG_80211N_HT */ - issue_deauth(padapter, psta->hwaddr, reason); + if (!MLME_IS_MESH(padapter)) + issue_deauth(padapter, psta->cmn.mac_addr, reason); } +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_path_flush_by_nexthop(psta); +#endif + #ifdef CONFIG_BEAMFORMING - beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->hwaddr, ETH_ALEN, 1); + beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->cmn.mac_addr, ETH_ALEN, 1); #endif +#ifdef CONFIG_80211N_HT psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ +#endif /* clear cam entry / key */ rtw_clearstakey_cmd(padapter, psta, enqueue); _enter_critical_bh(&psta->lock, &irqL); - psta->state &= ~_FW_LINKED; + psta->state &= ~(_FW_LINKED | WIFI_UNDER_KEY_HANDSHAKE); _exit_critical_bh(&psta->lock, &irqL); + if (!MLME_IS_MESH(padapter)) { #ifdef CONFIG_IOCTL_CFG80211 - if (1) { -#ifdef COMPAT_KERNEL_RELEASE - rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason); -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) - rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason); -#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ + #ifdef COMPAT_KERNEL_RELEASE + rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason); + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason); + #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ /* will call rtw_cfg80211_indicate_sta_disassoc() in cmd_thread for old API context */ -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ - } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { + #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ +#else rtw_indicate_sta_disassoc_event(padapter, psta); +#endif } - report_del_sta_event(padapter, psta->hwaddr, reason, enqueue, _FALSE); - beacon_updated = bss_cap_update_on_sta_leave(padapter, psta); - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - rtw_free_stainfo(padapter, psta); - /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - + report_del_sta_event(padapter, psta->cmn.mac_addr, reason, enqueue, _FALSE); return beacon_updated; @@ -3346,7 +3876,7 @@ int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset) psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); plist = get_next(plist); - issue_action_spct_ch_switch(padapter, psta->hwaddr, new_ch, ch_offset); + issue_action_spct_ch_switch(padapter, psta->cmn.mac_addr, new_ch, ch_offset); psta->expire_to = ((pstapriv->expire_to * 2) > 5) ? 5 : (pstapriv->expire_to * 2); } _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); @@ -3363,14 +3893,12 @@ int rtw_sta_flush(_adapter *padapter, bool enqueue) int ret = 0; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; u8 flush_num = 0; char flush_list[NUM_STA]; int i; - if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) return ret; RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); @@ -3387,6 +3915,7 @@ int rtw_sta_flush(_adapter *padapter, bool enqueue) rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; + STA_SET_MESH_PLINK(psta, NULL); stainfo_offset = rtw_stainfo_offset(pstapriv, psta); if (stainfo_offset_valid(stainfo_offset)) @@ -3398,11 +3927,20 @@ int rtw_sta_flush(_adapter *padapter, bool enqueue) /* call ap_free_sta() for each sta picked */ for (i = 0; i < flush_num; i++) { + u8 sta_addr[ETH_ALEN]; + psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]); + _rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN); + ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, enqueue); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_expire_peer(padapter, sta_addr); + #endif } - issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING); + if (!MLME_IS_MESH(padapter)) + issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING); associated_clients_update(padapter, _TRUE, STA_INFO_UPDATE_ALL); @@ -3458,14 +3996,12 @@ void sta_info_update(_adapter *padapter, struct sta_info *psta) void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta) { if (psta->state & _FW_LINKED) - rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); /* DM_RATR_STA_INIT */ + rtw_hal_update_ra_mask(psta); /* DM_RATR_STA_INIT */ } /* restore hw setting from sw data structures */ void rtw_ap_restore_network(_adapter *padapter) { - struct mlme_priv *mlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta; struct security_priv *psecuritypriv = &(padapter->securitypriv); @@ -3475,7 +4011,10 @@ void rtw_ap_restore_network(_adapter *padapter) char chk_alive_list[NUM_STA]; int i; - rtw_setopmode_cmd(padapter, Ndis802_11APMode, _FALSE); + rtw_setopmode_cmd(padapter + , MLME_IS_AP(padapter) ? Ndis802_11APMode : Ndis802_11_mesh + , RTW_CMDF_DIRECTLY + ); set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); @@ -3531,7 +4070,9 @@ void start_ap_mode(_adapter *padapter) struct sta_priv *pstapriv = &padapter->stapriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); +#ifdef CONFIG_CONCURRENT_MODE struct security_priv *psecuritypriv = &padapter->securitypriv; +#endif pmlmepriv->update_bcn = _FALSE; @@ -3572,13 +4113,9 @@ void start_ap_mode(_adapter *padapter) psecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID; #endif - for (i = 0 ; i < NUM_STA ; i++) + for (i = 0 ; i < pstapriv->max_aid; i++) pstapriv->sta_aid[i] = NULL; -#if CONFIG_RTW_MACADDR_ACL - rtw_macaddr_acl_init(padapter); -#endif - psta = rtw_get_bcmc_stainfo(padapter); /*_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ if (psta) @@ -3592,16 +4129,45 @@ void start_ap_mode(_adapter *padapter) } +void rtw_ap_bcmc_sta_flush(_adapter *padapter) +{ +#ifdef CONFIG_CONCURRENT_MODE + int cam_id = -1; + u8 *addr = adapter_mac_addr(padapter); + + cam_id = rtw_iface_bcmc_id_get(padapter); + if (cam_id != INVALID_SEC_MAC_CAM_ID) { + RTW_PRINT("clear group key for "ADPT_FMT" addr:"MAC_FMT", camid:%d\n", + ADPT_ARG(padapter), MAC_ARG(addr), cam_id); + clear_cam_entry(padapter, cam_id); + rtw_camid_free(padapter, cam_id); + rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); /*init default value*/ + } +#else + invalidate_cam_all(padapter); +#endif +} + void stop_ap_mode(_adapter *padapter) { - _irqL irqL; + u8 self_action = MLME_ACTION_UNKNOWN; struct sta_info *psta = NULL; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; +#ifdef CONFIG_SUPPORT_MULTI_BCN struct dvobj_priv *pdvobj = padapter->dvobj; - + _irqL irqL; +#endif + RTW_INFO("%s -"ADPT_FMT"\n", __func__, ADPT_ARG(padapter)); + if (MLME_IS_AP(padapter)) + self_action = MLME_AP_STOPPED; + else if (MLME_IS_MESH(padapter)) + self_action = MLME_MESH_STOPPED; + else + rtw_warn_on(1); + pmlmepriv->update_bcn = _FALSE; /*pmlmeext->bstart_bss = _FALSE;*/ padapter->netif_up = _FALSE; @@ -3613,49 +4179,72 @@ void stop_ap_mode(_adapter *padapter) padapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled; #ifdef CONFIG_DFS_MASTER - rtw_dfs_master_status_apply(padapter, MLME_AP_STOPPED); + rtw_dfs_rd_en_decision(padapter, self_action, 0); #endif /* free scan queue */ rtw_free_network_queue(padapter, _TRUE); #if CONFIG_RTW_MACADDR_ACL - rtw_macaddr_acl_deinit(padapter); + rtw_macaddr_acl_clear(padapter, RTW_ACL_PERIOD_BSS); #endif rtw_sta_flush(padapter, _TRUE); + rtw_ap_bcmc_sta_flush(padapter); /* free_assoc_sta_resources */ rtw_free_all_stainfo(padapter); psta = rtw_get_bcmc_stainfo(padapter); - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - rtw_free_stainfo(padapter, psta); - /*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ + if (psta) { + rtw_sta_mstatus_disc_rpt(padapter, psta->cmn.mac_id); + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + rtw_free_stainfo(padapter, psta); + /*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ + } rtw_free_mlme_priv_ie_data(pmlmepriv); -#ifdef CONFIG_SWTIMER_BASED_TXBCN +#ifdef CONFIG_SUPPORT_MULTI_BCN if (pmlmeext->bstart_bss == _TRUE) { + #ifdef CONFIG_FW_HANDLE_TXBCN + u8 free_apid = CONFIG_LIMITED_AP_NUM; + #endif + _enter_critical_bh(&pdvobj->ap_if_q.lock, &irqL); pdvobj->nr_ap_if--; if (pdvobj->nr_ap_if > 0) pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL / pdvobj->nr_ap_if; else pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL; - + #ifdef CONFIG_FW_HANDLE_TXBCN + rtw_ap_release_vapid(pdvobj, padapter->vap_id); + free_apid = padapter->vap_id; + padapter->vap_id = CONFIG_LIMITED_AP_NUM; + #endif rtw_list_delete(&padapter->list); _exit_critical_bh(&pdvobj->ap_if_q.lock, &irqL); + #ifdef CONFIG_FW_HANDLE_TXBCN + rtw_ap_mbid_bcn_dis(padapter, free_apid); + #endif + #ifdef CONFIG_SWTIMER_BASED_TXBCN rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pdvobj->inter_bcn_space)); if (pdvobj->nr_ap_if == 0) _cancel_timer_ex(&pdvobj->txbcn_timer); + #endif } #endif pmlmeext->bstart_bss = _FALSE; + rtw_hal_rcr_set_chk_bssid(padapter, self_action); + +#ifdef CONFIG_HW_P0_TSF_SYNC + correct_TSF(padapter, self_action); +#endif + #ifdef CONFIG_BT_COEXIST rtw_btcoex_MediaStatusNotify(padapter, 0); /* disconnect */ #endif @@ -3668,10 +4257,32 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, { #define UPDATE_VHT_CAP 1 #define UPDATE_HT_CAP 1 - #ifdef CONFIG_80211AC_VHT + struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv; +#endif { - struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv; + u8 *p; + int ie_len; + u8 old_ch = bss->Configuration.DSConfig; + bool change_band = _FALSE; + + if ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14)) + change_band = _TRUE; + + /* update channel in IE */ + p = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + if (p && ie_len > 0) + *(p + 2) = ch; + + bss->Configuration.DSConfig = ch; + + /* band is changed, update ERP, support rate, ext support rate IE */ + if (change_band == _TRUE) + change_band_update_ie(adapter, bss, ch); + } + +#ifdef CONFIG_80211AC_VHT + if (vhtpriv->vht_option == _TRUE) { u8 *vht_cap_ie, *vht_op_ie; int vht_cap_ielen, vht_op_ielen; u8 center_freq; @@ -3764,65 +4375,283 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, } } #endif /* CONFIG_80211N_HT */ +} - { - u8 *p; - int ie_len; - u8 old_ch = bss->Configuration.DSConfig; - bool change_band = _FALSE; +static u8 rtw_ap_update_chbw_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp + , u8 cur_ie_ch[], u8 cur_ie_bw[], u8 cur_ie_offset[] + , u8 dec_ch[], u8 dec_bw[], u8 dec_offset[] + , const char *caller) +{ + _adapter *iface; + struct mlme_ext_priv *mlmeext; + WLAN_BSSID_EX *network; + u8 ifbmp_ch_changed = 0; + int i; - if ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14)) - change_band = _TRUE; + for (i = 0; i < dvobj->iface_nums; i++) { + if (!(ifbmp & BIT(i)) || !dvobj->padapters) + continue; - /* update channel in IE */ - p = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); - if (p && ie_len > 0) - *(p + 2) = ch; + iface = dvobj->padapters[i]; + mlmeext = &(iface->mlmeextpriv); - bss->Configuration.DSConfig = ch; + if (MLME_IS_ASOC(iface)) { + RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u%s\n", caller, ADPT_ARG(iface) + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset + , dec_ch[i], dec_bw[i], dec_offset[i] + , MLME_IS_OPCH_SW(iface) ? " OPCH_SW" : ""); + } else { + RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u%s\n", caller, ADPT_ARG(iface) + , cur_ie_ch[i], cur_ie_bw[i], cur_ie_offset[i] + , dec_ch[i], dec_bw[i], dec_offset[i] + , MLME_IS_OPCH_SW(iface) ? " OPCH_SW" : ""); + } + } - /* band is changed, update ERP, support rate, ext support rate IE */ - if (change_band == _TRUE) - change_band_update_ie(adapter, bss, ch); + for (i = 0; i < dvobj->iface_nums; i++) { + if (!(ifbmp & BIT(i)) || !dvobj->padapters) + continue; + + iface = dvobj->padapters[i]; + mlmeext = &(iface->mlmeextpriv); + network = &(mlmeext->mlmext_info.network); + + /* ch setting differs from mlmeext.network IE */ + if (cur_ie_ch[i] != dec_ch[i] + || cur_ie_bw[i] != dec_bw[i] + || cur_ie_offset[i] != dec_offset[i]) + ifbmp_ch_changed |= BIT(i); + + /* ch setting differs from existing one */ + if (MLME_IS_ASOC(iface) + && (mlmeext->cur_channel != dec_ch[i] + || mlmeext->cur_bwmode != dec_bw[i] + || mlmeext->cur_ch_offset != dec_offset[i]) + ) { + if (rtw_linked_check(iface) == _TRUE) { + #ifdef CONFIG_SPCT_CH_SWITCH + if (1) + rtw_ap_inform_ch_switch(iface, dec_ch[i], dec_offset[i]); + else + #endif + rtw_sta_flush(iface, _FALSE); + } + } + + mlmeext->cur_channel = dec_ch[i]; + mlmeext->cur_bwmode = dec_bw[i]; + mlmeext->cur_ch_offset = dec_offset[i]; + + rtw_ap_update_bss_chbw(iface, network, dec_ch[i], dec_bw[i], dec_offset[i]); } + return ifbmp_ch_changed; } -bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offset - , u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow) +static u8 rtw_ap_ch_specific_chk(_adapter *adapter, u8 ch, u8 *bw, u8 *offset, const char *caller) { - u8 cur_ie_ch, cur_ie_bw, cur_ie_offset; - u8 dec_ch, dec_bw, dec_offset; - u8 u_ch = 0, u_offset, u_bw; - bool changed = _FALSE; - struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); - WLAN_BSSID_EX *network = &(adapter->mlmepriv.cur_network.network); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + RT_CHANNEL_INFO *chset = adapter_to_chset(adapter); + u8 ret = _SUCCESS; + + if (rtw_chset_search_ch(chset, ch) < 0) { + RTW_WARN("%s ch:%u doesn't fit in chplan\n", caller, ch); + ret = _FAIL; + goto exit; + } + + rtw_adjust_chbw(adapter, ch, bw, offset); + + if (!rtw_get_offset_by_chbw(ch, *bw, offset)) { + RTW_WARN("%s %u,%u has no valid offset\n", caller, ch, *bw); + ret = _FAIL; + goto exit; + } + + while (!rtw_chset_is_chbw_valid(chset, ch, *bw, *offset) + || (rtw_odm_dfs_domain_unknown(dvobj) && rtw_is_dfs_chbw(ch, *bw, *offset)) + ) { + if (*bw > CHANNEL_WIDTH_20) + (*bw)--; + if (*bw == CHANNEL_WIDTH_20) { + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + } + + if (rtw_odm_dfs_domain_unknown(dvobj) && rtw_is_dfs_chbw(ch, *bw, *offset)) { + RTW_WARN("%s DFS channel %u can't be used\n", caller, ch); + ret = _FAIL; + goto exit; + } + +exit: + return ret; +} + +static bool rtw_ap_choose_chbw(_adapter *adapter, u8 sel_ch, u8 max_bw, u8 cur_ch + , u8 *ch, u8 *bw, u8 *offset, u8 mesh_only, const char *caller) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + bool ch_avail = _FALSE; + +#if defined(CONFIG_DFS_MASTER) + if (!rtw_odm_dfs_domain_unknown(dvobj)) { + if (rfctl->radar_detected + && rfctl->dbg_dfs_choose_dfs_ch_first + ) { + ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw + , ch, bw, offset + , RTW_CHF_2G | RTW_CHF_NON_DFS + , cur_ch + , rfctl->ch_sel_same_band_prefer, mesh_only); + if (ch_avail == _TRUE) { + RTW_INFO("%s choose 5G DFS channel for debug\n", caller); + goto exit; + } + } + + if (rfctl->radar_detected + && rfctl->dfs_ch_sel_d_flags + ) { + ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw + , ch, bw, offset + , rfctl->dfs_ch_sel_d_flags + , cur_ch + , rfctl->ch_sel_same_band_prefer, mesh_only); + if (ch_avail == _TRUE) { + RTW_INFO("%s choose with dfs_ch_sel_d_flags:0x%02x for debug\n" + , caller, rfctl->dfs_ch_sel_d_flags); + goto exit; + } + } + + ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw + , ch, bw, offset + , 0 + , cur_ch + , rfctl->ch_sel_same_band_prefer, mesh_only); + } else +#endif /* defined(CONFIG_DFS_MASTER) */ + { + ch_avail = rtw_choose_shortest_waiting_ch(rfctl, sel_ch, max_bw + , ch, bw, offset + , RTW_CHF_DFS + , cur_ch + , rfctl->ch_sel_same_band_prefer, mesh_only); + } + +exit: + if (ch_avail == _FALSE) + RTW_WARN("%s no available channel\n", caller); + + return ch_avail; +} + +u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp + , s16 req_ch, s8 req_bw, s8 req_offset + , u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + RT_CHANNEL_INFO *chset = adapter_to_chset(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + bool ch_avail = _FALSE; + u8 cur_ie_ch[CONFIG_IFACE_NUMBER] = {0}; + u8 cur_ie_bw[CONFIG_IFACE_NUMBER] = {0}; + u8 cur_ie_offset[CONFIG_IFACE_NUMBER] = {0}; + u8 dec_ch[CONFIG_IFACE_NUMBER] = {0}; + u8 dec_bw[CONFIG_IFACE_NUMBER] = {0}; + u8 dec_offset[CONFIG_IFACE_NUMBER] = {0}; + u8 u_ch = 0, u_bw = 0, u_offset = 0; + struct mlme_ext_priv *mlmeext; + WLAN_BSSID_EX *network; struct mi_state mstate; - bool set_u_ch = _FALSE, set_dec_ch = _FALSE; + struct mi_state mstate_others; + bool set_u_ch = _FALSE; + u8 ifbmp_others = 0xFF & ~ifbmp & ~excl_ifbmp; + u8 ifbmp_ch_changed = 0; + bool ifbmp_all_mesh = 0; + _adapter *iface; + int i; + +#ifdef CONFIG_RTW_MESH + for (i = 0; i < dvobj->iface_nums; i++) + if ((ifbmp & BIT(i)) && dvobj->padapters) + if (!MLME_IS_MESH(dvobj->padapters[i])) + break; + ifbmp_all_mesh = i >= dvobj->iface_nums ? 1 : 0; +#endif + + RTW_INFO("%s ifbmp:0x%02x excl_ifbmp:0x%02x req:%d,%d,%d\n", __func__ + , ifbmp, excl_ifbmp, req_ch, req_bw, req_offset); + rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate); + rtw_mi_status_by_ifbmp(dvobj, ifbmp_others, &mstate_others); + RTW_INFO("%s others ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u\n" + , __func__, MSTATE_STA_LD_NUM(&mstate_others), MSTATE_STA_LG_NUM(&mstate_others) + , MSTATE_AP_NUM(&mstate_others), MSTATE_MESH_NUM(&mstate_others)); + + for (i = 0; i < dvobj->iface_nums; i++) { + if (!(ifbmp & BIT(i)) || !dvobj->padapters[i]) + continue; + iface = dvobj->padapters[i]; + mlmeext = &(iface->mlmeextpriv); + network = &(mlmeext->mlmext_info.network); + + /* get current IE channel settings */ + rtw_ies_get_chbw(BSS_EX_TLV_IES(network), BSS_EX_TLV_IES_LEN(network) + , &cur_ie_ch[i], &cur_ie_bw[i], &cur_ie_offset[i], 1, 1); + + /* prepare temporary channel setting decision */ + if (req_ch == 0) { + /* request comes from upper layer, use cur_ie values */ + dec_ch[i] = cur_ie_ch[i]; + dec_bw[i] = cur_ie_bw[i]; + dec_offset[i] = cur_ie_offset[i]; + } else { + /* use chbw of cur_ie updated with specifying req as temporary decision */ + dec_ch[i] = (req_ch <= REQ_CH_NONE) ? cur_ie_ch[i] : req_ch; + if (req_bw <= REQ_BW_NONE) { + if (req_bw == REQ_BW_ORI) + dec_bw[i] = iface->mlmepriv.ori_bw; + else + dec_bw[i] = cur_ie_bw[i]; + } else + dec_bw[i] = req_bw; + dec_offset[i] = (req_offset <= REQ_OFFSET_NONE) ? cur_ie_offset[i] : req_offset; + } + } - rtw_ies_get_chbw(network->IEs + sizeof(NDIS_802_11_FIXED_IEs) - , network->IELength - sizeof(NDIS_802_11_FIXED_IEs) - , &cur_ie_ch, &cur_ie_bw, &cur_ie_offset); + if (MSTATE_STA_LD_NUM(&mstate_others) || MSTATE_STA_LG_NUM(&mstate_others) + || MSTATE_AP_NUM(&mstate_others) || MSTATE_MESH_NUM(&mstate_others) + ) { + /* has linked/linking STA or has AP/Mesh mode */ + rtw_warn_on(!rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp_others, &u_ch, &u_bw, &u_offset)); + RTW_INFO("%s others union:%u,%u,%u\n", __func__, u_ch, u_bw, u_offset); + } #ifdef CONFIG_MCC_MODE - if (MCC_EN(adapter)) { + if (MCC_EN(adapter) && req_ch == 0) { if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) { - /* check channel settings are the same */ - if (cur_ie_ch == mlmeext->cur_channel - && cur_ie_bw == mlmeext->cur_bwmode - && cur_ie_offset == mlmeext->cur_ch_offset) { + u8 if_id = adapter->iface_id; + mlmeext = &(adapter->mlmeextpriv); - RTW_INFO(FUNC_ADPT_FMT"req ch settings are the same as current ch setting, go to exit\n" - , FUNC_ADPT_ARG(adapter)); + /* check channel settings are the same */ + if (cur_ie_ch[if_id] == mlmeext->cur_channel + && cur_ie_bw[if_id] == mlmeext->cur_bwmode + && cur_ie_offset[if_id] == mlmeext->cur_ch_offset) { - *chbw_allow = _FALSE; - goto exit; + RTW_INFO(FUNC_ADPT_FMT"req ch settings are the same as current ch setting, go to exit\n" + , FUNC_ADPT_ARG(adapter)); + + *chbw_allow = _FALSE; + goto exit; } else { - RTW_INFO(FUNC_ADPT_FMT"request channel settings are not the same as current channel setting(%d,%d,%d,%d,%d,%d), restart MCC\n" - , FUNC_ADPT_ARG(adapter) - , cur_ie_ch, cur_ie_bw, cur_ie_bw - , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + RTW_INFO(FUNC_ADPT_FMT"request channel settings are not the same as current channel setting(%d,%d,%d,%d,%d,%d), restart MCC\n" + , FUNC_ADPT_ARG(adapter) + , cur_ie_ch[if_id], cur_ie_bw[if_id], cur_ie_offset[if_id] + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); rtw_hal_set_mcc_setting_disconnect(adapter); } @@ -3830,201 +4659,278 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse } #endif /* CONFIG_MCC_MODE */ - /* use chbw of cur_ie updated with specifying req as temporary decision */ - dec_ch = (req_ch <= 0) ? cur_ie_ch : req_ch; - dec_bw = (req_bw < 0) ? cur_ie_bw : req_bw; - dec_offset = (req_offset < 0) ? cur_ie_offset : req_offset; - - rtw_mi_status_no_self(adapter, &mstate); - RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num%u, ap_num:%u\n" - , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate), MSTATE_AP_NUM(&mstate)); + if (MSTATE_STA_LG_NUM(&mstate_others) && !MSTATE_STA_LD_NUM(&mstate_others)) { + /* has linking STA but no linked STA */ - if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) { - /* has linked STA or AP mode, follow */ + for (i = 0; i < dvobj->iface_nums; i++) { + if (!(ifbmp & BIT(i)) || !dvobj->padapters[i]) + continue; + iface = dvobj->padapters[i]; - rtw_warn_on(!rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset)); + rtw_adjust_chbw(iface, dec_ch[i], &dec_bw[i], &dec_offset[i]); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(iface)) + rtw_mesh_adjust_chbw(dec_ch[i], &dec_bw[i], &dec_offset[i]); + #endif - RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); - RTW_INFO(FUNC_ADPT_FMT" req: %d,%d,%d\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset); + if (rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch[i], dec_bw[i], dec_offset[i])) { + rtw_chset_sync_chbw(chset + , &dec_ch[i], &dec_bw[i], &dec_offset[i] + , &u_ch, &u_bw, &u_offset); + set_u_ch = _TRUE; - rtw_adjust_chbw(adapter, u_ch, &dec_bw, &dec_offset); -#ifdef CONFIG_MCC_MODE - if (MCC_EN(adapter)) { - if (!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch, dec_bw, dec_offset)) { - mlmeext->cur_channel = *ch = dec_ch; - mlmeext->cur_bwmode = *bw = dec_bw; - mlmeext->cur_ch_offset = *offset = dec_offset; - /* channel bw offset can not be allowed, need MCC */ - *chbw_allow = _FALSE; - RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(adapter) - , *ch, *bw, *offset); - goto exit; - } else /* channel bw offset can be allowed, not need MCC */ *chbw_allow = _TRUE; - } -#endif /* CONFIG_MCC_MODE */ - rtw_sync_chbw(&dec_ch, &dec_bw, &dec_offset - , &u_ch, &u_bw, &u_offset); + } else { + #ifdef CONFIG_MCC_MODE + if (MCC_EN(iface)) { + mlmeext = &(iface->mlmeextpriv); + mlmeext->cur_channel = *ch = dec_ch[i]; + mlmeext->cur_bwmode = *bw = dec_bw[i]; + mlmeext->cur_ch_offset = *offset = dec_offset[i]; + + /* channel bw offset can not be allowed, need MCC */ + *chbw_allow = _FALSE; + RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(iface) + , *ch, *bw, *offset); + goto exit; + } + #endif /* CONFIG_MCC_MODE */ - rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) - , dec_ch, dec_bw, dec_offset); + /* set this for possible ch change when join down*/ + set_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING); + } + } - set_u_ch = _TRUE; - } else if (MSTATE_STA_LG_NUM(&mstate)) { - /* has linking STA */ + } else if (MSTATE_STA_LD_NUM(&mstate_others) + || MSTATE_AP_NUM(&mstate_others) || MSTATE_MESH_NUM(&mstate_others) + ) { + /* has linked STA mode or AP/Mesh mode */ - rtw_warn_on(!rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset)); + for (i = 0; i < dvobj->iface_nums; i++) { + if (!(ifbmp & BIT(i)) || !dvobj->padapters[i]) + continue; + iface = dvobj->padapters[i]; - RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); - RTW_INFO(FUNC_ADPT_FMT" req: %d,%d,%d\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset); + rtw_adjust_chbw(iface, u_ch, &dec_bw[i], &dec_offset[i]); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(iface)) + rtw_mesh_adjust_chbw(u_ch, &dec_bw[i], &dec_offset[i]); + #endif - rtw_adjust_chbw(adapter, dec_ch, &dec_bw, &dec_offset); + #ifdef CONFIG_MCC_MODE + if (MCC_EN(iface)) { + if (!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch[i], dec_bw[i], dec_offset[i])) { + mlmeext = &(iface->mlmeextpriv); + mlmeext->cur_channel = *ch = dec_ch[i] = cur_ie_ch[i]; + mlmeext->cur_bwmode = *bw = dec_bw[i] = cur_ie_bw[i]; + mlmeext->cur_ch_offset = *offset = dec_offset[i] = cur_ie_offset[i]; + /* channel bw offset can not be allowed, need MCC */ + *chbw_allow = _FALSE; + RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(iface) + , *ch, *bw, *offset); + goto exit; + } else + /* channel bw offset can be allowed, not need MCC */ + *chbw_allow = _TRUE; + } + #endif /* CONFIG_MCC_MODE */ + + if (req_ch == 0 && dec_bw[i] > u_bw + && rtw_is_dfs_chbw(u_ch, u_bw, u_offset) + ) { + /* request comes from upper layer, prevent from additional channel waiting */ + dec_bw[i] = u_bw; + if (dec_bw[i] == CHANNEL_WIDTH_20) + dec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } - if (rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch, dec_bw, dec_offset)) { + /* follow */ + rtw_chset_sync_chbw(chset + , &dec_ch[i], &dec_bw[i], &dec_offset[i] + , &u_ch, &u_bw, &u_offset); + } - rtw_sync_chbw(&dec_ch, &dec_bw, &dec_offset - , &u_ch, &u_bw, &u_offset); + set_u_ch = _TRUE; - rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) - , dec_ch, dec_bw, dec_offset); + } else { + /* autonomous decision */ + u8 ori_ch = 0; + u8 max_bw; - set_u_ch = _TRUE; + /* autonomous decision, not need MCC */ + *chbw_allow = _TRUE; - /* channel bw offset can be allowed, not need MCC */ - *chbw_allow = _TRUE; - } else { -#ifdef CONFIG_MCC_MODE - if (MCC_EN(adapter)) { - mlmeext->cur_channel = *ch = dec_ch; - mlmeext->cur_bwmode = *bw = dec_bw; - mlmeext->cur_ch_offset = *offset = dec_offset; + if (req_ch <= REQ_CH_NONE) /* channel is not specified */ + goto choose_chbw; - /* channel bw offset can not be allowed, need MCC */ - *chbw_allow = _FALSE; - RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(adapter) - , *ch, *bw, *offset); - goto exit; + /* get tmp dec union of ifbmp */ + for (i = 0; i < dvobj->iface_nums; i++) { + if (!(ifbmp & BIT(i)) || !dvobj->padapters[i]) + continue; + if (u_ch == 0) { + u_ch = dec_ch[i]; + u_bw = dec_bw[i]; + u_offset = dec_offset[i]; + rtw_adjust_chbw(adapter, u_ch, &u_bw, &u_offset); + rtw_get_offset_by_chbw(u_ch, u_bw, &u_offset); + } else { + u8 tmp_ch = dec_ch[i]; + u8 tmp_bw = dec_bw[i]; + u8 tmp_offset = dec_offset[i]; + + rtw_adjust_chbw(adapter, tmp_ch, &tmp_bw, &tmp_offset); + rtw_get_offset_by_chbw(tmp_ch, tmp_bw, &tmp_offset); + + rtw_warn_on(!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, tmp_ch, tmp_bw, tmp_offset)); + rtw_sync_chbw(&tmp_ch, &tmp_bw, &tmp_offset, &u_ch, &u_bw, &u_offset); } -#endif /* CONFIG_MCC_MODE */ - /* set this for possible ch change when join down*/ - set_fwstate(&adapter->mlmepriv, WIFI_OP_CH_SWITCHING); } - } else { - /* single AP mode */ - RTW_INFO(FUNC_ADPT_FMT" req: %d,%d,%d\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset); + #ifdef CONFIG_RTW_MESH + /* if ifbmp are all mesh, apply bw restriction */ + if (ifbmp_all_mesh) + rtw_mesh_adjust_chbw(u_ch, &u_bw, &u_offset); + #endif - /* check temporary decision first */ - rtw_adjust_chbw(adapter, dec_ch, &dec_bw, &dec_offset); - if (!rtw_get_offset_by_chbw(dec_ch, dec_bw, &dec_offset)) { - if (req_ch == -1 || req_bw == -1) - goto choose_chbw; - RTW_WARN(FUNC_ADPT_FMT" req: %u,%u has no valid offset\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw); - *chbw_allow = _FALSE; - goto exit; - } - - if (!rtw_chset_is_chbw_valid(mlmeext->channel_set, dec_ch, dec_bw, dec_offset)) { - if (req_ch == -1 || req_bw == -1) - goto choose_chbw; - RTW_WARN(FUNC_ADPT_FMT" req: %u,%u,%u doesn't fit in chplan\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset); - *chbw_allow = _FALSE; - goto exit; - } + RTW_INFO("%s ifbmp:0x%02x tmp union:%u,%u,%u\n", __func__, ifbmp, u_ch, u_bw, u_offset); - if (rtw_odm_dfs_domain_unknown(adapter) && rtw_is_dfs_chbw(dec_ch, dec_bw, dec_offset)) { - if (req_ch >= 0) - RTW_WARN(FUNC_ADPT_FMT" DFS channel %u,%u,%u can't be used\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset); + /* check if tmp dec union is usable */ + if (rtw_ap_ch_specific_chk(adapter, u_ch, &u_bw, &u_offset, __func__) == _FAIL) { + /* channel can't be used */ if (req_ch > 0) { /* specific channel and not from IE => don't change channel setting */ - *chbw_allow = _FALSE; goto exit; } goto choose_chbw; - } - - if (rtw_chset_is_ch_non_ocp(mlmeext->channel_set, dec_ch, dec_bw, dec_offset) == _FALSE) + } else if (rtw_chset_is_chbw_non_ocp(chset, u_ch, u_bw, u_offset)) { + RTW_WARN("%s DFS channel %u,%u under non ocp\n", __func__, u_ch, u_bw); + if (req_ch > 0 && req_bw > REQ_BW_NONE) { + /* change_chbw with specific channel and specific bw, goto update_bss_chbw directly */ + goto update_bss_chbw; + } + } else goto update_bss_chbw; choose_chbw: - if (req_bw < 0) - req_bw = cur_ie_bw; + req_ch = req_ch > 0 ? req_ch : 0; + max_bw = req_bw > REQ_BW_NONE ? req_bw : CHANNEL_WIDTH_20; + for (i = 0; i < dvobj->iface_nums; i++) { + if (!(ifbmp & BIT(i)) || !dvobj->padapters[i]) + continue; + iface = dvobj->padapters[i]; + mlmeext = &(iface->mlmeextpriv); + + if (req_bw <= REQ_BW_NONE) { + if (req_bw == REQ_BW_ORI) { + if (max_bw < iface->mlmepriv.ori_bw) + max_bw = iface->mlmepriv.ori_bw; + } else { + if (max_bw < cur_ie_bw[i]) + max_bw = cur_ie_bw[i]; + } + } -#if defined(CONFIG_DFS_MASTER) - if (!rtw_odm_dfs_domain_unknown(adapter)) { - /* choose 5G DFS channel for debug */ - if (adapter_to_rfctl(adapter)->dbg_dfs_master_choose_dfs_ch_first - && rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_2G | RTW_CHF_NON_DFS) == _TRUE) - RTW_INFO(FUNC_ADPT_FMT" choose 5G DFS channel for debug\n", FUNC_ADPT_ARG(adapter)); - else if (adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags - && rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags) == _TRUE) - RTW_INFO(FUNC_ADPT_FMT" choose with dfs_ch_sel_d_flags:0x%02x for debug\n", FUNC_ADPT_ARG(adapter), adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags); - else if (rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, 0) == _FALSE) { - RTW_WARN(FUNC_ADPT_FMT" no available channel\n", FUNC_ADPT_ARG(adapter)); - *chbw_allow = _FALSE; - goto exit; + if (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate)) { + if (ori_ch == 0) + ori_ch = mlmeext->cur_channel; + else if (ori_ch != mlmeext->cur_channel) + rtw_warn_on(1); + } else { + if (ori_ch == 0) + ori_ch = cur_ie_ch[i]; + else if (ori_ch != cur_ie_ch[i]) + rtw_warn_on(1); } - } else -#endif /* defined(CONFIG_DFS_MASTER) */ - if (rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_DFS) == _FALSE) { - RTW_WARN(FUNC_ADPT_FMT" no available channel\n", FUNC_ADPT_ARG(adapter)); - *chbw_allow = _FALSE; - goto exit; } -update_bss_chbw: - rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) - , dec_ch, dec_bw, dec_offset); + ch_avail = rtw_ap_choose_chbw(adapter, req_ch, max_bw + , ori_ch, &u_ch, &u_bw, &u_offset, ifbmp_all_mesh, __func__); + if (ch_avail == _FALSE) + goto exit; - /* channel bw offset can be allowed for single AP, not need MCC */ - *chbw_allow = _TRUE; - set_dec_ch = _TRUE; - } +update_bss_chbw: + for (i = 0; i < dvobj->iface_nums; i++) { + if (!(ifbmp & BIT(i)) || !dvobj->padapters[i]) + continue; + iface = dvobj->padapters[i]; - if (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY)) { - /* scanning, leave ch setting to scan state machine */ - set_u_ch = set_dec_ch = _FALSE; - } + dec_ch[i] = u_ch; + if (dec_bw[i] > u_bw) + dec_bw[i] = u_bw; + if (dec_bw[i] == CHANNEL_WIDTH_20) + dec_offset[i] = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + else + dec_offset[i] = u_offset; - if (mlmeext->cur_channel != dec_ch - || mlmeext->cur_bwmode != dec_bw - || mlmeext->cur_ch_offset != dec_offset) - changed = _TRUE; + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(iface)) + rtw_mesh_adjust_chbw(dec_ch[i], &dec_bw[i], &dec_offset[i]); + #endif + } - if (changed == _TRUE && rtw_linked_check(adapter) == _TRUE) { -#ifdef CONFIG_SPCT_CH_SWITCH - if (1) - rtw_ap_inform_ch_switch(adapter, dec_ch, dec_offset); - else -#endif - rtw_sta_flush(adapter, _FALSE); + set_u_ch = _TRUE; } - mlmeext->cur_channel = dec_ch; - mlmeext->cur_bwmode = dec_bw; - mlmeext->cur_ch_offset = dec_offset; + ifbmp_ch_changed = rtw_ap_update_chbw_by_ifbmp(dvobj, ifbmp + , cur_ie_ch, cur_ie_bw, cur_ie_offset + , dec_ch, dec_bw, dec_offset + , __func__); if (u_ch != 0) - RTW_INFO(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + RTW_INFO("%s union:%u,%u,%u\n", __func__, u_ch, u_bw, u_offset); - RTW_INFO(FUNC_ADPT_FMT" dec: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset); + if (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY)) { + /* scanning, leave ch setting to scan state machine */ + set_u_ch = _FALSE; + } if (set_u_ch == _TRUE) { *ch = u_ch; *bw = u_bw; *offset = u_offset; - } else if (set_dec_ch == _TRUE) { - *ch = dec_ch; - *bw = dec_bw; - *offset = dec_offset; } exit: - return changed; + return ifbmp_ch_changed; } -/*#define DBG_SWTIMER_BASED_TXBCN*/ +u8 rtw_ap_sta_states_check(_adapter *adapter) +{ + struct sta_info *psta; + struct sta_priv *pstapriv = &adapter->stapriv; + _list *plist, *phead; + _irqL irqL; + u8 rst = _FALSE; + if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) + return _FALSE; + + if (pstapriv->auth_list_cnt !=0) + return _TRUE; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + if (!(psta->state & _FW_LINKED)) { + RTW_INFO(ADPT_FMT"- SoftAP/Mesh - sta under linking, its state = 0x%x\n", ADPT_ARG(adapter), psta->state); + rst = _TRUE; + break; + } else if (psta->state & WIFI_UNDER_KEY_HANDSHAKE) { + RTW_INFO(ADPT_FMT"- SoftAP/Mesh - sta under key handshaking, its state = 0x%x\n", ADPT_ARG(adapter), psta->state); + rst = _TRUE; + break; + } + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + return rst; +} + +/*#define DBG_SWTIMER_BASED_TXBCN*/ #ifdef CONFIG_SWTIMER_BASED_TXBCN void tx_beacon_handlder(struct dvobj_priv *pdvobj) { @@ -4036,6 +4942,7 @@ void tx_beacon_handlder(struct dvobj_priv *pdvobj) u64 time; u32 cur_tick, time_offset; /* unit : usec */ u32 inter_bcn_space_us; /* unit : usec */ + u32 txbcn_timer_ms; /* unit : ms */ int nr_vap, idx, bcn_idx; int i; u8 val8, late = 0; @@ -4135,20 +5042,28 @@ void tx_beacon_handlder(struct dvobj_priv *pdvobj) #ifdef DBG_SWTIMER_BASED_TXBCN RTW_INFO("set sw bcn timer %d us\n", time_offset); #endif - _set_timer(&pdvobj->txbcn_timer, time_offset / NET80211_TU_TO_US); + txbcn_timer_ms = time_offset / NET80211_TU_TO_US; + _set_timer(&pdvobj->txbcn_timer, txbcn_timer_ms); if (padapter) { +#ifdef CONFIG_BCN_RECOVERY + rtw_ap_bcn_recovery(padapter); +#endif /*CONFIG_BCN_RECOVERY*/ + +#ifdef CONFIG_BCN_XMIT_PROTECT + rtw_ap_bcn_queue_empty_check(padapter, txbcn_timer_ms); +#endif /*CONFIG_BCN_XMIT_PROTECT*/ + #ifdef DBG_SWTIMER_BASED_TXBCN RTW_INFO("padapter=%p, PORT=%d\n", padapter, padapter->hw_port); #endif /* bypass TX BCN queue if op ch is switching/waiting */ if (!check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) - #ifdef CONFIG_DFS_MASTER && !IS_CH_WAITING(adapter_to_rfctl(padapter)) - #endif ) { /*update_beacon(padapter, _TIM_IE_, NULL, _FALSE);*/ - issue_beacon(padapter, 0); + /*issue_beacon(padapter, 0);*/ + send_beacon(padapter); } } @@ -4174,4 +5089,318 @@ void tx_beacon_timer_handlder(void *ctx) } #endif +void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap) +{ + sta->capability = RTW_GET_LE16(cap); + if (sta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) + sta->flags |= WLAN_STA_SHORT_PREAMBLE; + else + sta->flags &= ~WLAN_STA_SHORT_PREAMBLE; +} + +u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len) +{ + u8 rate_set[12]; + u8 rate_num; + int i; + u16 status = _STATS_SUCCESSFUL_; + + rtw_ies_get_supported_rate(tlv_ies, tlv_ies_len, rate_set, &rate_num); + if (rate_num == 0) { + RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" with no supported rate\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr)); + status = _STATS_FAILURE_; + goto exit; + } + + _rtw_memcpy(sta->bssrateset, rate_set, rate_num); + sta->bssratelen = rate_num; + + if (MLME_IS_AP(adapter)) { + /* this function force only CCK rates to be bassic rate... */ + UpdateBrateTblForSoftAP(sta->bssrateset, sta->bssratelen); + } + + /* if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G) */ /* ? */ + sta->flags |= WLAN_STA_NONERP; + for (i = 0; i < sta->bssratelen; i++) { + if ((sta->bssrateset[i] & 0x7f) > 22) { + sta->flags &= ~WLAN_STA_NONERP; + break; + } + } + +exit: + return status; +} + +u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems) +{ + struct security_priv *sec = &adapter->securitypriv; + u8 *wpa_ie; + int wpa_ie_len; + int group_cipher = 0, pairwise_cipher = 0; + u8 mfp_opt = MFP_NO; + u16 status = _STATS_SUCCESSFUL_; + + sta->dot8021xalg = 0; + sta->wpa_psk = 0; + sta->wpa_group_cipher = 0; + sta->wpa2_group_cipher = 0; + sta->wpa_pairwise_cipher = 0; + sta->wpa2_pairwise_cipher = 0; + _rtw_memset(sta->wpa_ie, 0, sizeof(sta->wpa_ie)); + + if ((sec->wpa_psk & BIT(1)) && elems->rsn_ie) { + wpa_ie = elems->rsn_ie; + wpa_ie_len = elems->rsn_ie_len; + + if (rtw_parse_wpa2_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) { + sta->dot8021xalg = 1;/* psk, todo:802.1x */ + sta->wpa_psk |= BIT(1); + + sta->wpa2_group_cipher = group_cipher & sec->wpa2_group_cipher; + sta->wpa2_pairwise_cipher = pairwise_cipher & sec->wpa2_pairwise_cipher; + + if (!sta->wpa2_group_cipher) + status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; + + if (!sta->wpa2_pairwise_cipher) + status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; + } else + status = WLAN_STATUS_INVALID_IE; + + } + else if ((sec->wpa_psk & BIT(0)) && elems->wpa_ie) { + wpa_ie = elems->wpa_ie; + wpa_ie_len = elems->wpa_ie_len; + + if (rtw_parse_wpa_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + sta->dot8021xalg = 1;/* psk, todo:802.1x */ + sta->wpa_psk |= BIT(0); + + sta->wpa_group_cipher = group_cipher & sec->wpa_group_cipher; + sta->wpa_pairwise_cipher = pairwise_cipher & sec->wpa_pairwise_cipher; + + if (!sta->wpa_group_cipher) + status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; + + if (!sta->wpa_pairwise_cipher) + status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; + } else + status = WLAN_STATUS_INVALID_IE; + + } else { + wpa_ie = NULL; + wpa_ie_len = 0; + } + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + /* MFP is mandatory for secure mesh */ + if (adapter->mesh_info.mesh_auth_id) + sta->flags |= WLAN_STA_MFP; + } else +#endif + if ((sec->mfp_opt == MFP_REQUIRED && mfp_opt == MFP_NO) || mfp_opt == MFP_INVALID) + status = WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION; + else if (sec->mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL) + sta->flags |= WLAN_STA_MFP; + + if (status != _STATS_SUCCESSFUL_) + goto exit; + + if (!MLME_IS_AP(adapter)) + goto exit; + + sta->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS); + /* if (hapd->conf->wps_state && wpa_ie == NULL) { */ /* todo: to check ap if supporting WPS */ + if (wpa_ie == NULL) { + if (elems->wps_ie) { + RTW_INFO("STA included WPS IE in " + "(Re)Association Request - assume WPS is " + "used\n"); + sta->flags |= WLAN_STA_WPS; + /* wpabuf_free(sta->wps_ie); */ + /* sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, */ + /* elems.wps_ie_len - 4); */ + } else { + RTW_INFO("STA did not include WPA/RSN IE " + "in (Re)Association Request - possible WPS " + "use\n"); + sta->flags |= WLAN_STA_MAYBE_WPS; + } + + /* AP support WPA/RSN, and sta is going to do WPS, but AP is not ready */ + /* that the selected registrar of AP is _FLASE */ + if ((sec->wpa_psk > 0) + && (sta->flags & (WLAN_STA_WPS | WLAN_STA_MAYBE_WPS)) + ) { + struct mlme_priv *mlme = &adapter->mlmepriv; + + if (mlme->wps_beacon_ie) { + u8 selected_registrar = 0; + + rtw_get_wps_attr_content(mlme->wps_beacon_ie, mlme->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR, &selected_registrar, NULL); + + if (!selected_registrar) { + RTW_INFO("selected_registrar is _FALSE , or AP is not ready to do WPS\n"); + status = _STATS_UNABLE_HANDLE_STA_; + goto exit; + } + } + } + + } else { + int copy_len; + + if (sec->wpa_psk == 0) { + RTW_INFO("STA " MAC_FMT + ": WPA/RSN IE in association request, but AP don't support WPA/RSN\n", + MAC_ARG(sta->cmn.mac_addr)); + status = WLAN_STATUS_INVALID_IE; + goto exit; + } + + if (elems->wps_ie) { + RTW_INFO("STA included WPS IE in " + "(Re)Association Request - WPS is " + "used\n"); + sta->flags |= WLAN_STA_WPS; + copy_len = 0; + } else + copy_len = ((wpa_ie_len + 2) > sizeof(sta->wpa_ie)) ? (sizeof(sta->wpa_ie)) : (wpa_ie_len + 2); + + if (copy_len > 0) + _rtw_memcpy(sta->wpa_ie, wpa_ie - 2, copy_len); + } + +exit: + return status; +} + +void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; + u8 *p; + + sta->flags &= ~WLAN_STA_WME; + sta->qos_option = 0; + sta->qos_info = 0; + sta->has_legacy_ac = _TRUE; + sta->uapsd_vo = 0; + sta->uapsd_vi = 0; + sta->uapsd_be = 0; + sta->uapsd_bk = 0; + + if (!mlme->qospriv.qos_option) + goto exit; + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + /* QoS is mandatory in mesh */ + sta->flags |= WLAN_STA_WME; + } +#endif + + p = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, WMM_IE, 6, NULL, NULL); + if (!p) + goto exit; + + sta->flags |= WLAN_STA_WME; + sta->qos_option = 1; + sta->qos_info = *(p + 8); + sta->max_sp_len = (sta->qos_info >> 5) & 0x3; + + if ((sta->qos_info & 0xf) != 0xf) + sta->has_legacy_ac = _TRUE; + else + sta->has_legacy_ac = _FALSE; + + if (sta->qos_info & 0xf) { + if (sta->qos_info & BIT(0)) + sta->uapsd_vo = BIT(0) | BIT(1); + else + sta->uapsd_vo = 0; + + if (sta->qos_info & BIT(1)) + sta->uapsd_vi = BIT(0) | BIT(1); + else + sta->uapsd_vi = 0; + + if (sta->qos_info & BIT(2)) + sta->uapsd_bk = BIT(0) | BIT(1); + else + sta->uapsd_bk = 0; + + if (sta->qos_info & BIT(3)) + sta->uapsd_be = BIT(0) | BIT(1); + else + sta->uapsd_be = 0; + } + +exit: + return; +} + +void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + + sta->flags &= ~WLAN_STA_HT; + +#ifdef CONFIG_80211N_HT + if (mlme->htpriv.ht_option == _FALSE) + goto exit; + + /* save HT capabilities in the sta object */ + _rtw_memset(&sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap)); + if (elems->ht_capabilities && elems->ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) { + sta->flags |= WLAN_STA_HT; + sta->flags |= WLAN_STA_WME; + _rtw_memcpy(&sta->htpriv.ht_cap, elems->ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap)); + + if (elems->ht_operation && elems->ht_operation_len == HT_OP_IE_LEN) { + _rtw_memcpy(sta->htpriv.ht_op, elems->ht_operation, HT_OP_IE_LEN); + sta->htpriv.op_present = 1; + } + } +exit: +#endif + + return; +} + +void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + + sta->flags &= ~WLAN_STA_VHT; + +#ifdef CONFIG_80211AC_VHT + if (mlme->vhtpriv.vht_option == _FALSE) + goto exit; + + _rtw_memset(&sta->vhtpriv, 0, sizeof(struct vht_priv)); + if (elems->vht_capabilities && elems->vht_capabilities_len == VHT_CAP_IE_LEN) { + sta->flags |= WLAN_STA_VHT; + _rtw_memcpy(sta->vhtpriv.vht_cap, elems->vht_capabilities, VHT_CAP_IE_LEN); + + if (elems->vht_operation && elems->vht_operation_len== VHT_OP_IE_LEN) { + _rtw_memcpy(sta->vhtpriv.vht_op, elems->vht_operation, VHT_OP_IE_LEN); + sta->vhtpriv.op_present = 1; + } + + if (elems->vht_op_mode_notify && elems->vht_op_mode_notify_len == 1) { + _rtw_memcpy(&sta->vhtpriv.vht_op_mode_notify, elems->vht_op_mode_notify, 1); + sta->vhtpriv.notify_present = 1; + } + } +exit: +#endif + + return; +} #endif /* CONFIG_AP_MODE */ + diff --git a/core/rtw_beamforming.c b/core/rtw_beamforming.c index 64de508..5adc83a 100644 --- a/core/rtw_beamforming.c +++ b/core/rtw_beamforming.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_BEAMFORMING_C_ #include @@ -50,10 +45,10 @@ static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 * * a DLS or TDLS peer STA */ - aid = sta->aid; + aid = sta->cmn.aid; bssid = adapter_mac_addr(adapter); RTW_INFO("%s: AID=0x%x BSSID=" MAC_FMT "\n", - __FUNCTION__, sta->aid, MAC_ARG(bssid)); + __FUNCTION__, sta->cmn.aid, MAC_ARG(bssid)); /* AID[0:8] */ aid &= 0x1FF; @@ -75,7 +70,7 @@ static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 * *g_id = 63; } else { /* Addressed to AP */ - bssid = sta->hwaddr; + bssid = sta->cmn.mac_addr; RTW_INFO("%s: BSSID=" MAC_FMT "\n", __FUNCTION__, MAC_ARG(bssid)); /* BSSID[39:47] */ @@ -167,7 +162,7 @@ static void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta, #endif /* CONFIG_80211AC_VHT */ } -static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, CHANNEL_WIDTH bw) +static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw) { /* General */ struct xmit_priv *pxmitpriv; @@ -265,7 +260,7 @@ static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, CHANNEL_WIDTH bw) return _TRUE; } -static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw) +static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_width bw) { /* General */ struct xmit_priv *pxmitpriv; @@ -371,7 +366,7 @@ static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, CHANNEL_WIDTH return _TRUE; } -static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, CHANNEL_WIDTH bw) +static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, enum channel_width bw) { /* General */ struct xmit_priv *pxmitpriv; @@ -1013,7 +1008,7 @@ static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter, mlme = &adapter->mlmepriv; info = GET_BEAMFORM_INFO(adapter); - bfer = _bfer_get_entry_by_addr(adapter, sta->hwaddr); + bfer = _bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr); if (!bfer) { bfer = _bfer_get_free_entry(adapter); if (!bfer) @@ -1022,14 +1017,14 @@ static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter, bfer->used = _TRUE; _get_txvector_parameter(adapter, sta, &bfer->g_id, &bfer->p_aid); - _rtw_memcpy(bfer->mac_addr, sta->hwaddr, ETH_ALEN); + _rtw_memcpy(bfer->mac_addr, sta->cmn.mac_addr, ETH_ALEN); bfer->cap = bf_cap; bfer->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT; bfer->NumofSoundingDim = sounding_dim; if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_MU)) { info->beamformer_mu_cnt += 1; - bfer->aid = sta->aid; + bfer->aid = sta->cmn.aid; } else if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) { info->beamformer_su_cnt += 1; @@ -1073,22 +1068,20 @@ static void _bfer_remove_entry(PADAPTER adapter, struct beamformer_entry *entry) static u8 _bfer_set_entry_gid(PADAPTER adapter, u8 *addr, u8 *gid, u8 *position) { - struct beamformer_entry *bfer = NULL; + struct beamformer_entry bfer; - - bfer = _bfer_get_entry_by_addr(adapter, addr); - if (!bfer) { - RTW_INFO("%s: Cannot find BFer entry!!\n", __FUNCTION__); - return _FAIL; - } + memset(&bfer, 0, sizeof(bfer)); + memcpy(bfer.mac_addr, addr, ETH_ALEN); /* Parsing Membership Status Array */ - _rtw_memcpy(bfer->gid_valid, gid, 8); + memcpy(bfer.gid_valid, gid, 8); + /* Parsing User Position Array */ - _rtw_memcpy(bfer->user_position, position, 16); + memcpy(bfer.user_position, position, 16); /* Config HW GID table */ - rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_GID_TABLE, (u8*)&bfer, sizeof(struct beamformer_entry *), 1); + rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_GID_TABLE, (u8 *) &bfer, + sizeof(bfer), 1); return _SUCCESS; } @@ -1200,7 +1193,7 @@ static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter, mlme = &adapter->mlmepriv; info = GET_BEAMFORM_INFO(adapter); - bfee = _bfee_get_entry_by_addr(adapter, sta->hwaddr); + bfee = _bfee_get_entry_by_addr(adapter, sta->cmn.mac_addr); if (!bfee) { bfee = _bfee_get_free_entry(adapter); if (!bfee) @@ -1208,15 +1201,15 @@ static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter, } bfee->used = _TRUE; - bfee->aid = sta->aid; - bfee->mac_id = sta->mac_id; - bfee->sound_bw = sta->bw_mode; + bfee->aid = sta->cmn.aid; + bfee->mac_id = sta->cmn.mac_id; + bfee->sound_bw = sta->cmn.bw_mode; _get_txvector_parameter(adapter, sta, &bfee->g_id, &bfee->p_aid); - sta->txbf_gid = bfee->g_id; - sta->txbf_paid = bfee->p_aid; + sta->cmn.bf_info.g_id = bfee->g_id; + sta->cmn.bf_info.p_aid = bfee->p_aid; - _rtw_memcpy(bfee->mac_addr, sta->hwaddr, ETH_ALEN); + _rtw_memcpy(bfee->mac_addr, sta->cmn.mac_addr, ETH_ALEN); bfee->txbf = _FALSE; bfee->sounding = _FALSE; bfee->sound_period = 40; @@ -1387,15 +1380,15 @@ static void _beamforming_enter(PADAPTER adapter, void *p) info = GET_BEAMFORM_INFO(adapter); sta_copy = (struct sta_info *)p; - sta = rtw_get_stainfo(&adapter->stapriv, sta_copy->hwaddr); + sta = rtw_get_stainfo(&adapter->stapriv, sta_copy->cmn.mac_addr); if (!sta) { RTW_ERR("%s: Cann't find STA info for " MAC_FMT "\n", - __FUNCTION__, MAC_ARG(sta_copy->hwaddr)); + __FUNCTION__, MAC_ARG(sta_copy->cmn.mac_addr)); return; } if (sta != sta_copy) { RTW_WARN("%s: Origin sta(fake)=%p realsta=%p for " MAC_FMT "\n", - __FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->hwaddr)); + __FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->cmn.mac_addr)); } /* The current setting does not support Beaforming */ @@ -1799,6 +1792,7 @@ void rtw_bf_init(PADAPTER adapter) info->beamformee_mu_reg_maping = 0; info->first_mu_bfee_index = 0xFF; info->mu_bfer_curidx = 0xFF; + info->cur_csi_rpt_rate = HALMAC_OFDM24; _sounding_init(&info->sounding_info); rtw_init_timer(&info->sounding_timer, adapter, _sounding_timer_handler, adapter); @@ -1837,7 +1831,7 @@ void rtw_bf_cmd_hdl(PADAPTER adapter, u8 type, u8 *pbuf) break; case BEAMFORMING_CTRL_SET_GID_TABLE: - rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_SET_GID_TABLE, *(void**)pbuf); + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_SET_GID_TABLE, pbuf); break; case BEAMFORMING_CTRL_SET_CSI_REPORT: @@ -1907,8 +1901,8 @@ u8 rtw_bf_cmd(PADAPTER adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue) void rtw_bf_update_attrib(PADAPTER adapter, struct pkt_attrib *attrib, struct sta_info *sta) { if (sta) { - attrib->txbf_g_id = sta->txbf_gid; - attrib->txbf_p_aid = sta->txbf_paid; + attrib->txbf_g_id = sta->cmn.bf_info.g_id; + attrib->txbf_p_aid = sta->cmn.bf_info.p_aid; } } @@ -1932,7 +1926,8 @@ void rtw_bf_update_traffic(PADAPTER adapter) u16 tp[MAX_BEAMFORMEE_ENTRY_NUM] = {0}; u8 tx_rate[MAX_BEAMFORMEE_ENTRY_NUM] = {0}; u64 tx_bytes, last_bytes; - u32 time, last_timestamp; + u32 time; + systime last_timestamp; u8 set_timer = _FALSE; @@ -1967,7 +1962,7 @@ void rtw_bf_update_traffic(PADAPTER adapter) time = rtw_get_time_interval_ms(last_timestamp, bfee->tx_timestamp); time = (time > 1000) ? time/1000 : 1; tp[i] = toMbps(tx_bytes, time); - tx_rate[i] = rtw_get_current_tx_rate(adapter, bfee->mac_id); + tx_rate[i] = rtw_get_current_tx_rate(adapter, sta); RTW_INFO("%s: BFee idx(%d), MadId(%d), TxTP=%lld bytes (%d Mbps), txrate=%d\n", __FUNCTION__, i, bfee->mac_id, tx_bytes, tp[i], tx_rate[i]); } @@ -2059,7 +2054,7 @@ struct beamforming_entry *beamforming_get_free_entry(struct mlme_priv *pmlmepriv struct beamforming_entry *beamforming_add_entry(PADAPTER adapter, u8 *ra, u16 aid, - u16 mac_id, CHANNEL_WIDTH bw, BEAMFORMING_CAP beamfrom_cap, u8 *idx) + u16 mac_id, enum channel_width bw, BEAMFORMING_CAP beamfrom_cap, u8 *idx) { struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); struct beamforming_entry *pEntry = beamforming_get_free_entry(pmlmepriv, idx); @@ -2121,8 +2116,10 @@ void beamforming_dym_ndpa_rate(PADAPTER adapter) { u16 NDPARate = MGN_6M; PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + s8 min_rssi = 0; - if (pHalData->min_undecorated_pwdb_for_dm > 30) /* link RSSI > 30% */ + min_rssi = rtw_phydm_get_min_rssi(adapter); + if (min_rssi > 30) /* link RSSI > 30% */ NDPARate = MGN_24M; else NDPARate = MGN_6M; @@ -2175,7 +2172,7 @@ void beamforming_dym_period(PADAPTER Adapter) rtw_hal_set_hwreg(Adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&Idx); } -BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; @@ -2254,7 +2251,7 @@ BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 q } -BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; @@ -2329,11 +2326,11 @@ BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx return _TRUE; } -BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx) { return issue_ht_ndpa_packet(Adapter, ra, bw, qidx); } -BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; @@ -2427,7 +2424,7 @@ BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDT return _TRUE; } -BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; @@ -2513,7 +2510,7 @@ BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH b return _TRUE; } -BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx) +BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx) { return issue_vht_ndpa_packet(Adapter, ra, aid, bw, qidx); } @@ -2571,9 +2568,9 @@ u16 beamforming_sounding_time(struct beamforming_info *pBeamInfo, SOUNDING_MODE return sounding_time; } -CHANNEL_WIDTH beamforming_sounding_bw(struct beamforming_info *pBeamInfo, SOUNDING_MODE mode, u8 idx) +enum channel_width beamforming_sounding_bw(struct beamforming_info *pBeamInfo, SOUNDING_MODE mode, u8 idx) { - CHANNEL_WIDTH sounding_bw = CHANNEL_WIDTH_20; + enum channel_width sounding_bw = CHANNEL_WIDTH_20; struct beamforming_entry BeamEntry = pBeamInfo->beamforming_entry[idx]; sounding_bw = BeamEntry.sound_bw; @@ -2710,7 +2707,7 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx) u8 *ra; u16 aid, mac_id; u8 wireless_mode; - CHANNEL_WIDTH bw = CHANNEL_WIDTH_20; + enum channel_width bw = CHANNEL_WIDTH_20; BEAMFORMING_CAP beamform_cap = BEAMFORMING_CAP_NONE; /* The current setting does not support Beaforming */ @@ -2723,11 +2720,11 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx) return _FALSE; } - aid = psta->aid; - ra = psta->hwaddr; - mac_id = psta->mac_id; + aid = psta->cmn.aid; + ra = psta->cmn.mac_addr; + mac_id = psta->cmn.mac_id; wireless_mode = psta->wireless_mode; - bw = psta->bw_mode; + bw = psta->cmn.bw_mode; if (is_supported_ht(wireless_mode) || is_supported_vht(wireless_mode)) { /* 3 */ /* HT */ @@ -2779,8 +2776,8 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx) } pBeamformEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - psta->txbf_paid = pBeamformEntry->p_aid; - psta->txbf_gid = pBeamformEntry->g_id; + psta->cmn.bf_info.p_aid = pBeamformEntry->p_aid; + psta->cmn.bf_info.g_id = pBeamformEntry->g_id; RTW_INFO("%s Idx %d\n", __FUNCTION__, *idx); } else @@ -2919,7 +2916,7 @@ u32 rtw_beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_ u32 ret = _SUCCESS; #if (BEAMFORMING_SUPPORT == 1) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); ret = beamforming_get_report_frame(pDM_Odm, precv_frame); @@ -2966,7 +2963,7 @@ void rtw_beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_f { #if (BEAMFORMING_SUPPORT == 1) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); beamforming_get_ndpa_frame(pDM_Odm, precv_frame); @@ -3042,13 +3039,13 @@ void rtw_beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_f void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); #if (BEAMFORMING_SUPPORT == 1) /*(BEAMFORMING_SUPPORT == 1)- for PHYDM beamfoming*/ switch (type) { case BEAMFORMING_CTRL_ENTER: { struct sta_info *psta = (PVOID)pbuf; - u16 staIdx = psta->mac_id; + u16 staIdx = psta->cmn.mac_id; beamforming_enter(pDM_Odm, staIdx); break; @@ -3089,8 +3086,14 @@ u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enque struct cmd_obj *ph2c; struct drvextra_cmd_parm *pdrvextra_cmd_parm; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u8 res = _SUCCESS; + /*20170214 ad_hoc mode and mp_mode not support BF*/ + if ((padapter->registrypriv.mp_mode == 1) + || (pmlmeinfo->state == WIFI_FW_ADHOC_STATE)) + return res; if (enqueue) { u8 *wk_buf; @@ -3143,8 +3146,8 @@ u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enque void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta) { if (psta) { - pattrib->txbf_g_id = psta->txbf_gid; - pattrib->txbf_p_aid = psta->txbf_paid; + pattrib->txbf_g_id = psta->cmn.bf_info.g_id; + pattrib->txbf_p_aid = psta->cmn.bf_info.p_aid; } } #endif /* !RTW_BEAMFORMING_VERSION_2 */ diff --git a/core/rtw_br_ext.c b/core/rtw_br_ext.c index b330edf..9a0effd 100644 --- a/core/rtw_br_ext.c +++ b/core/rtw_br_ext.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_BR_EXT_C_ #ifdef __KERNEL__ @@ -306,7 +301,7 @@ static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char return 0; } - +#ifdef SUPPORT_RX_UNI2MCAST static void convert_ipv6_mac_to_mc(struct sk_buff *skb) { struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN); @@ -324,6 +319,7 @@ static void convert_ipv6_mac_to_mc(struct sk_buff *skb) #endif } #endif /* CL_IPV6_PASS */ +#endif /* SUPPORT_RX_UNI2MCAST */ static __inline__ int __nat25_network_hash(unsigned char *networkAddr) diff --git a/core/rtw_bt_mp.c b/core/rtw_bt_mp.c index a0597d8..9b4fc24 100644 --- a/core/rtw_bt_mp.c +++ b/core/rtw_bt_mp.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include @@ -471,7 +466,7 @@ MPTBT_FwC2hBtMpCtrl( PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)tmpBuf; - if (Adapter->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0) { + if (GET_HAL_DATA(Adapter)->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0) { /* RTW_INFO("Ignore C2H BT MP Info since not in MP mode\n"); */ return; } diff --git a/core/rtw_btcoex.c b/core/rtw_btcoex.c index 696efd2..d1d8355 100644 --- a/core/rtw_btcoex.c +++ b/core/rtw_btcoex.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,18 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifdef CONFIG_BT_COEXIST - + *****************************************************************************/ #include -#include #include - +#ifdef CONFIG_BT_COEXIST +#include void rtw_btcoex_Initialize(PADAPTER padapter) { @@ -34,6 +27,11 @@ void rtw_btcoex_PowerOnSetting(PADAPTER padapter) hal_btcoex_PowerOnSetting(padapter); } +void rtw_btcoex_AntInfoSetting(PADAPTER padapter) +{ + hal_btcoex_AntInfoSetting(padapter); +} + void rtw_btcoex_PowerOffSetting(PADAPTER padapter) { hal_btcoex_PowerOffSetting(padapter); @@ -245,6 +243,16 @@ void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type) hal_btcoex_switchband_notify(under_scan, band_type); } +void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length) +{ + hal_btcoex_WlFwDbgInfoNotify(padapter, tmpBuf, length); +} + +void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id) +{ + hal_btcoex_rx_rate_change_notify(padapter, is_data_frame, rate_id); +} + void rtw_btcoex_SwitchBtTRxMask(PADAPTER padapter) { hal_btcoex_SwitchBtTRxMask(padapter); @@ -1734,3 +1742,22 @@ void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType) } #endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ #endif /* CONFIG_BT_COEXIST */ + +void rtw_btcoex_set_ant_info(PADAPTER padapter) +{ +#ifdef CONFIG_BT_COEXIST + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); + + if (hal->EEPROMBluetoothCoexist == _TRUE) { + u8 bMacPwrCtrlOn = _FALSE; + + rtw_btcoex_AntInfoSetting(padapter); + rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + if (bMacPwrCtrlOn == _TRUE) + rtw_btcoex_PowerOnSetting(padapter); + } + else +#endif + rtw_btcoex_wifionly_AntInfoSetting(padapter); +} + diff --git a/core/rtw_btcoex_wifionly.c b/core/rtw_btcoex_wifionly.c index f61ad2b..d9872b0 100644 --- a/core/rtw_btcoex_wifionly.c +++ b/core/rtw_btcoex_wifionly.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #include #include @@ -31,6 +26,11 @@ void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter) hal_btcoex_wifionly_scan_notify(padapter); } +void rtw_btcoex_wifionly_connect_notify(PADAPTER padapter) +{ + hal_btcoex_wifionly_connect_notify(padapter); +} + void rtw_btcoex_wifionly_hw_config(PADAPTER padapter) { hal_btcoex_wifionly_hw_config(padapter); @@ -40,3 +40,8 @@ void rtw_btcoex_wifionly_initialize(PADAPTER padapter) { hal_btcoex_wifionly_initlizevariables(padapter); } + +void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter) +{ + hal_btcoex_wifionly_AntInfoSetting(padapter); +} diff --git a/core/rtw_chplan.c b/core/rtw_chplan.c new file mode 100644 index 0000000..b2432ca --- /dev/null +++ b/core/rtw_chplan.c @@ -0,0 +1,1184 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#define _RTW_CHPLAN_C_ + +#include + +#define RTW_DOMAIN_MAP_VER "35e" +#define RTW_COUNTRY_MAP_VER "20" + +#ifdef LEGACY_CHANNEL_PLAN_REF +/******************************************************** +ChannelPlan definitions +*********************************************************/ +static RT_CHANNEL_PLAN legacy_channel_plan[] = { + /* 0x00, RTW_CHPLAN_FCC */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 32}, + /* 0x01, RTW_CHPLAN_IC */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 31}, + /* 0x02, RTW_CHPLAN_ETSI */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 32}, + /* 0x03, RTW_CHPLAN_SPAIN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 0x04, RTW_CHPLAN_FRANCE */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 0x05, RTW_CHPLAN_MKK */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 0x06, RTW_CHPLAN_MKK1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 0x07, RTW_CHPLAN_ISRAEL */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64}, 21}, + /* 0x08, RTW_CHPLAN_TELEC */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52, 56, 60, 64}, 22}, + /* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14}, + /* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 0x0B, RTW_CHPLAN_TAIWAN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 26}, + /* 0x0C, RTW_CHPLAN_CHINA */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 149, 153, 157, 161, 165}, 18}, + /* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 24}, + /* 0x0E, RTW_CHPLAN_KOREA */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 31}, + /* 0x0F, RTW_CHPLAN_TURKEY */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64}, 19}, + /* 0x10, RTW_CHPLAN_JAPAN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 32}, + /* 0x11, RTW_CHPLAN_FCC_NO_DFS */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 149, 153, 157, 161, 165}, 20}, + /* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48}, 17}, + /* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 37}, + /* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 56, 60, 64, 149, 153, 157, 161, 165}, 19}, +}; +#endif + +enum rtw_rd_2g { + RTW_RD_2G_NULL = 0, + RTW_RD_2G_WORLD = 1, /* Worldwird 13 */ + RTW_RD_2G_ETSI1 = 2, /* Europe */ + RTW_RD_2G_FCC1 = 3, /* US */ + RTW_RD_2G_MKK1 = 4, /* Japan */ + RTW_RD_2G_ETSI2 = 5, /* France */ + RTW_RD_2G_GLOBAL = 6, /* Global domain */ + RTW_RD_2G_MKK2 = 7, /* Japan */ + RTW_RD_2G_FCC2 = 8, /* US */ + RTW_RD_2G_IC1 = 9, /* Canada */ + RTW_RD_2G_WORLD1 = 10, /* Worldwide 11 */ + RTW_RD_2G_KCC1 = 11, /* Korea */ + + RTW_RD_2G_MAX, +}; + +enum rtw_rd_5g { + RTW_RD_5G_NULL = 0, /* */ + RTW_RD_5G_ETSI1 = 1, /* Europe */ + RTW_RD_5G_ETSI2 = 2, /* Australia, New Zealand */ + RTW_RD_5G_ETSI3 = 3, /* Russia */ + RTW_RD_5G_FCC1 = 4, /* US */ + RTW_RD_5G_FCC2 = 5, /* FCC w/o DFS Channels */ + RTW_RD_5G_FCC3 = 6, /* Bolivia, Chile, El Salvador, Venezuela */ + RTW_RD_5G_FCC4 = 7, /* Venezuela */ + RTW_RD_5G_FCC5 = 8, /* China */ + RTW_RD_5G_FCC6 = 9, /* */ + RTW_RD_5G_FCC7 = 10, /* US(w/o Weather radar) */ + RTW_RD_5G_IC1 = 11, /* Canada(w/o Weather radar) */ + RTW_RD_5G_KCC1 = 12, /* Korea */ + RTW_RD_5G_MKK1 = 13, /* Japan */ + RTW_RD_5G_MKK2 = 14, /* Japan (W52, W53) */ + RTW_RD_5G_MKK3 = 15, /* Japan (W56) */ + RTW_RD_5G_NCC1 = 16, /* Taiwan, (w/o Weather radar) */ + RTW_RD_5G_NCC2 = 17, /* Taiwan, Band2, Band4 */ + RTW_RD_5G_NCC3 = 18, /* Taiwan w/o DFS, Band4 only */ + RTW_RD_5G_ETSI4 = 19, /* Europe w/o DFS, Band1 only */ + RTW_RD_5G_ETSI5 = 20, /* Australia, New Zealand(w/o Weather radar) */ + RTW_RD_5G_FCC8 = 21, /* Latin America */ + RTW_RD_5G_ETSI6 = 22, /* Israel, Bahrain, Egypt, India, China, Malaysia */ + RTW_RD_5G_ETSI7 = 23, /* China */ + RTW_RD_5G_ETSI8 = 24, /* Jordan */ + RTW_RD_5G_ETSI9 = 25, /* Lebanon */ + RTW_RD_5G_ETSI10 = 26, /* Qatar */ + RTW_RD_5G_ETSI11 = 27, /* Russia */ + RTW_RD_5G_NCC4 = 28, /* Taiwan, (w/o Weather radar) */ + RTW_RD_5G_ETSI12 = 29, /* Indonesia */ + RTW_RD_5G_FCC9 = 30, /* (w/o Weather radar) */ + RTW_RD_5G_ETSI13 = 31, /* (w/o Weather radar) */ + RTW_RD_5G_FCC10 = 32, /* Argentina(w/o Weather radar) */ + RTW_RD_5G_MKK4 = 33, /* Japan (W52) */ + RTW_RD_5G_ETSI14 = 34, /* Russia */ + RTW_RD_5G_FCC11 = 35, /* US(include CH144) */ + RTW_RD_5G_ETSI15 = 36, /* Malaysia */ + RTW_RD_5G_MKK5 = 37, /* Japan */ + RTW_RD_5G_ETSI16 = 38, /* Europe */ + RTW_RD_5G_ETSI17 = 39, /* Europe */ + RTW_RD_5G_FCC12 = 40, /* FCC */ + RTW_RD_5G_FCC13 = 41, /* FCC */ + RTW_RD_5G_FCC14 = 42, /* FCC w/o Weather radar(w/o 5600~5650MHz) */ + RTW_RD_5G_FCC15 = 43, /* FCC w/o Band3 */ + RTW_RD_5G_FCC16 = 44, /* FCC w/o Band3 */ + RTW_RD_5G_ETSI18 = 45, /* ETSI w/o DFS Band2&3 */ + RTW_RD_5G_ETSI19 = 46, /* Europe */ + RTW_RD_5G_FCC17 = 47, /* FCC w/o Weather radar(w/o 5600~5650MHz) */ + RTW_RD_5G_ETSI20 = 48, /* Europe */ + RTW_RD_5G_IC2 = 49, /* Canada(w/o Weather radar), include ch144 */ + RTW_RD_5G_ETSI21 = 50, /* Australia, New Zealand(w/o Weather radar) */ + RTW_RD_5G_FCC18 = 51, /* */ + RTW_RD_5G_WORLD = 52, /* Worldwide */ + RTW_RD_5G_CHILE1 = 53, /* Chile */ + RTW_RD_5G_ACMA1 = 54, /* Australia, New Zealand (w/o Weather radar) (w/o Ch120~Ch128) */ + RTW_RD_5G_WORLD1 = 55, /* 5G Worldwide Band1&2 */ + RTW_RD_5G_CHILE2 = 56, /* Chile (Band2,Band3) */ + RTW_RD_5G_KCC2 = 57, /* Korea (New standard) */ + + /* === Below are driver defined for legacy channel plan compatible, DON'T assign index ==== */ + RTW_RD_5G_OLD_FCC1, + RTW_RD_5G_OLD_NCC1, + RTW_RD_5G_OLD_KCC1, + + RTW_RD_5G_MAX, +}; + +struct ch_list_t { + u8 *len_ch; +}; + +#define CH_LIST_ENT(_len, arg...) \ + {.len_ch = (u8[_len + 1]) {_len, ##arg}, } + +#define CH_LIST_LEN(_ch_list) (_ch_list.len_ch[0]) +#define CH_LIST_CH(_ch_list, _i) (_ch_list.len_ch[_i + 1]) + +struct chplan_ent_t { + u8 rd_2g; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + u8 rd_5g; +#endif + u8 regd; /* value of REGULATION_TXPWR_LMT */ +}; + +#ifdef CONFIG_IEEE80211_BAND_5GHZ +#define CHPLAN_ENT(i2g, i5g, regd) {i2g, i5g, regd} +#else +#define CHPLAN_ENT(i2g, i5g, regd) {i2g, regd} +#endif + +static struct ch_list_t RTW_ChannelPlan2G[] = { + /* 0, RTW_RD_2G_NULL */ CH_LIST_ENT(0), + /* 1, RTW_RD_2G_WORLD */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 2, RTW_RD_2G_ETSI1 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 3, RTW_RD_2G_FCC1 */ CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11), + /* 4, RTW_RD_2G_MKK1 */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14), + /* 5, RTW_RD_2G_ETSI2 */ CH_LIST_ENT(4, 10, 11, 12, 13), + /* 6, RTW_RD_2G_GLOBAL */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14), + /* 7, RTW_RD_2G_MKK2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 8, RTW_RD_2G_FCC2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 9, RTW_RD_2G_IC1 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 10, RTW_RD_2G_WORLD1 */ CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11), + /* 11, RTW_RD_2G_KCC1 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), +}; + +#ifdef CONFIG_IEEE80211_BAND_5GHZ +static struct ch_list_t RTW_ChannelPlan5G[] = { + /* 0, RTW_RD_5G_NULL */ CH_LIST_ENT(0), + /* 1, RTW_RD_5G_ETSI1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 2, RTW_RD_5G_ETSI2 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 3, RTW_RD_5G_ETSI3 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165), + /* 4, RTW_RD_5G_FCC1 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 5, RTW_RD_5G_FCC2 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), + /* 6, RTW_RD_5G_FCC3 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 7, RTW_RD_5G_FCC4 */ CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161), + /* 8, RTW_RD_5G_FCC5 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), + /* 9, RTW_RD_5G_FCC6 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), + /* 10, RTW_RD_5G_FCC7 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 11, RTW_RD_5G_IC1 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 12, RTW_RD_5G_KCC1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161), + /* 13, RTW_RD_5G_MKK1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 14, RTW_RD_5G_MKK2 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), + /* 15, RTW_RD_5G_MKK3 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 16, RTW_RD_5G_NCC1 */ CH_LIST_ENT(16, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 17, RTW_RD_5G_NCC2 */ CH_LIST_ENT(8, 56, 60, 64, 149, 153, 157, 161, 165), + /* 18, RTW_RD_5G_NCC3 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), + /* 19, RTW_RD_5G_ETSI4 */ CH_LIST_ENT(4, 36, 40, 44, 48), + /* 20, RTW_RD_5G_ETSI5 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 21, RTW_RD_5G_FCC8 */ CH_LIST_ENT(4, 149, 153, 157, 161), + /* 22, RTW_RD_5G_ETSI6 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), + /* 23, RTW_RD_5G_ETSI7 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 24, RTW_RD_5G_ETSI8 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), + /* 25, RTW_RD_5G_ETSI9 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 26, RTW_RD_5G_ETSI10 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), + /* 27, RTW_RD_5G_ETSI11 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165), + /* 28, RTW_RD_5G_NCC4 */ CH_LIST_ENT(17, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 29, RTW_RD_5G_ETSI12 */ CH_LIST_ENT(4, 149, 153, 157, 161), + /* 30, RTW_RD_5G_FCC9 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 31, RTW_RD_5G_ETSI13 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140), + /* 32, RTW_RD_5G_FCC10 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161), + /* 33, RTW_RD_5G_MKK4 */ CH_LIST_ENT(4, 36, 40, 44, 48), + /* 34, RTW_RD_5G_ETSI14 */ CH_LIST_ENT(11, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140), + /* 35, RTW_RD_5G_FCC11 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165), + /* 36, RTW_RD_5G_ETSI15 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165), + /* 37, RTW_RD_5G_MKK5 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 38, RTW_RD_5G_ETSI16 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 39, RTW_RD_5G_ETSI17 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 40, RTW_RD_5G_FCC12*/ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 41, RTW_RD_5G_FCC13 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 42, RTW_RD_5G_FCC14 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 43, RTW_RD_5G_FCC15 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 44, RTW_RD_5G_FCC16 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 45, RTW_RD_5G_ETSI18 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), + /* 46, RTW_RD_5G_ETSI19 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 47, RTW_RD_5G_FCC17 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140), + /* 48, RTW_RD_5G_ETSI20 */ CH_LIST_ENT(9, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 49, RTW_RD_5G_IC2 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 144, 149, 153, 157, 161, 165), + /* 50, RTW_RD_5G_ETSI21 */ CH_LIST_ENT(13, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 51, RTW_RD_5G_FCC18 */ CH_LIST_ENT(8, 100, 104, 108, 112, 116, 132, 136, 140), + /* 52, RTW_RD_5G_WORLD */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165), + /* 53, RTW_RD_5G_CHILE1 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165), + /* 54, RTW_RD_5G_ACMA1 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 55, RTW_RD_5G_WORLD1 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), + /* 56, RTW_RD_5G_CHILE2 */ CH_LIST_ENT(16, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144), + /* 57, RTW_RD_5G_KCC2 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + + /* === Below are driver defined for legacy channel plan compatible, NO static index assigned ==== */ + /* RTW_RD_5G_OLD_FCC1 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165), + /* RTW_RD_5G_OLD_NCC1 */ CH_LIST_ENT(15, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165), + /* RTW_RD_5G_OLD_KCC1 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165), +}; +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ + +static struct chplan_ent_t RTW_ChannelPlanMap[RTW_CHPLAN_MAX] = { + /* ===== 0x00 ~ 0x1F, legacy channel plan ===== */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_KCC1, TXPWR_LMT_FCC), /* 0x00, RTW_CHPLAN_FCC */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_FCC1, TXPWR_LMT_FCC), /* 0x01, RTW_CHPLAN_IC */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x02, RTW_CHPLAN_ETSI */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x03, RTW_CHPLAN_SPAIN */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x04, RTW_CHPLAN_FRANCE */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x05, RTW_CHPLAN_MKK */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x06, RTW_CHPLAN_MKK1 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI), /* 0x07, RTW_CHPLAN_ISRAEL */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_FCC6, TXPWR_LMT_MKK), /* 0x08, RTW_CHPLAN_TELEC */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_NCC1, TXPWR_LMT_FCC), /* 0x0B, RTW_CHPLAN_TAIWAN */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI), /* 0x0C, RTW_CHPLAN_CHINA */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC3, TXPWR_LMT_WW), /* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ /* ETSI:Singapore, India. FCC:Mexico => WW */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_KCC1, TXPWR_LMT_ETSI), /* 0x0E, RTW_CHPLAN_KOREA */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI), /* 0x0F, RTW_CHPLAN_TURKEY */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_MKK), /* 0x10, RTW_CHPLAN_JAPAN */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x11, RTW_CHPLAN_FCC_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK), /* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_WW), /* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC), /* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC7, TXPWR_LMT_ETSI), /* 0x15, RTW_CHPLAN_ETSI_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NCC1, TXPWR_LMT_ETSI), /* 0x16, RTW_CHPLAN_KOREA_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK), /* 0x17, RTW_CHPLAN_JAPAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI), /* 0x18, RTW_CHPLAN_PAKISTAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x19, RTW_CHPLAN_TAIWAN2_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1A, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_FCC1, TXPWR_LMT_WW), /* 0x1F, RTW_CHPLAN_WORLD_WIDE_ONLY_5G */ + + /* ===== 0x20 ~ 0x7F, new channel plan ===== */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x20, RTW_CHPLAN_WORLD_NULL */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x21, RTW_CHPLAN_ETSI1_NULL */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NULL, TXPWR_LMT_FCC), /* 0x22, RTW_CHPLAN_FCC1_NULL */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x23, RTW_CHPLAN_MKK1_NULL */ + CHPLAN_ENT(RTW_RD_2G_ETSI2, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x24, RTW_CHPLAN_ETSI2_NULL */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC1, TXPWR_LMT_FCC), /* 0x25, RTW_CHPLAN_FCC1_FCC1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x26, RTW_CHPLAN_WORLD_ETSI1 */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK1, TXPWR_LMT_MKK), /* 0x27, RTW_CHPLAN_MKK1_MKK1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_KCC1, TXPWR_LMT_KCC), /* 0x28, RTW_CHPLAN_WORLD_KCC1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x29, RTW_CHPLAN_WORLD_FCC2 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_NULL, TXPWR_LMT_FCC), /* 0x2A, RTW_CHPLAN_FCC2_NULL */ + CHPLAN_ENT(RTW_RD_2G_IC1, RTW_RD_5G_IC2, TXPWR_LMT_IC), /* 0x2B, RTW_CHPLAN_IC1_IC2 */ + CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x2C, RTW_CHPLAN_MKK2_NULL */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_CHILE1, TXPWR_LMT_CHILE), /* 0x2D, RTW_CHPLAN_WORLD_CHILE1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD1, RTW_RD_5G_WORLD1, TXPWR_LMT_WW), /* 0x2E, RTW_CHPLAN_WORLD1_WORLD1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_CHILE2, TXPWR_LMT_CHILE), /* 0x2F, RTW_CHPLAN_WORLD_CHILE2 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC3, TXPWR_LMT_FCC), /* 0x30, RTW_CHPLAN_WORLD_FCC3 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC4, TXPWR_LMT_FCC), /* 0x31, RTW_CHPLAN_WORLD_FCC4 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x32, RTW_CHPLAN_WORLD_FCC5 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC6, TXPWR_LMT_FCC), /* 0x33, RTW_CHPLAN_WORLD_FCC6 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x34, RTW_CHPLAN_FCC1_FCC7 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI2, TXPWR_LMT_ETSI), /* 0x35, RTW_CHPLAN_WORLD_ETSI2 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI3, TXPWR_LMT_ETSI), /* 0x36, RTW_CHPLAN_WORLD_ETSI3 */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK2, TXPWR_LMT_MKK), /* 0x37, RTW_CHPLAN_MKK1_MKK2 */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK3, TXPWR_LMT_MKK), /* 0x38, RTW_CHPLAN_MKK1_MKK3 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC1, TXPWR_LMT_FCC), /* 0x39, RTW_CHPLAN_FCC1_NCC1 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x3A, RTW_CHPLAN_ETSI1_ETSI1 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ACMA1, TXPWR_LMT_ACMA), /* 0x3B, RTW_CHPLAN_ETSI1_ACMA1 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI), /* 0x3C, RTW_CHPLAN_ETSI1_ETSI6 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI12, TXPWR_LMT_ETSI), /* 0x3D, RTW_CHPLAN_ETSI1_ETSI12 */ + CHPLAN_ENT(RTW_RD_2G_KCC1, RTW_RD_5G_KCC2, TXPWR_LMT_KCC), /* 0x3E, RTW_CHPLAN_KCC1_KCC2 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3F, */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC), /* 0x40, RTW_CHPLAN_FCC1_NCC2 */ + CHPLAN_ENT(RTW_RD_2G_GLOBAL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x41, RTW_CHPLAN_GLOBAL_NULL */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI4, TXPWR_LMT_ETSI), /* 0x42, RTW_CHPLAN_ETSI1_ETSI4 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x43, RTW_CHPLAN_FCC1_FCC2 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC3, TXPWR_LMT_FCC), /* 0x44, RTW_CHPLAN_FCC1_NCC3 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ACMA1, TXPWR_LMT_ACMA), /* 0x45, RTW_CHPLAN_WORLD_ACMA1 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC8, TXPWR_LMT_FCC), /* 0x46, RTW_CHPLAN_FCC1_FCC8 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI), /* 0x47, RTW_CHPLAN_WORLD_ETSI6 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI7, TXPWR_LMT_ETSI), /* 0x48, RTW_CHPLAN_WORLD_ETSI7 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI), /* 0x49, RTW_CHPLAN_WORLD_ETSI8 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4A, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4F, */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI9, TXPWR_LMT_ETSI), /* 0x50, RTW_CHPLAN_WORLD_ETSI9 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI10, TXPWR_LMT_ETSI), /* 0x51, RTW_CHPLAN_WORLD_ETSI10 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI11, TXPWR_LMT_ETSI), /* 0x52, RTW_CHPLAN_WORLD_ETSI11 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC4, TXPWR_LMT_FCC), /* 0x53, RTW_CHPLAN_FCC1_NCC4 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI12, TXPWR_LMT_ETSI), /* 0x54, RTW_CHPLAN_WORLD_ETSI12 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC9, TXPWR_LMT_FCC), /* 0x55, RTW_CHPLAN_FCC1_FCC9 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI13, TXPWR_LMT_ETSI), /* 0x56, RTW_CHPLAN_WORLD_ETSI13 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC10, TXPWR_LMT_FCC), /* 0x57, RTW_CHPLAN_FCC1_FCC10 */ + CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK4, TXPWR_LMT_MKK), /* 0x58, RTW_CHPLAN_MKK2_MKK4 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI14, TXPWR_LMT_ETSI), /* 0x59, RTW_CHPLAN_WORLD_ETSI14 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5A, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5F, */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x60, RTW_CHPLAN_FCC1_FCC5 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x61, RTW_CHPLAN_FCC2_FCC7 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC1, TXPWR_LMT_FCC), /* 0x62, RTW_CHPLAN_FCC2_FCC1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI15, TXPWR_LMT_ETSI), /* 0x63, RTW_CHPLAN_WORLD_ETSI15 */ + CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK5, TXPWR_LMT_MKK), /* 0x64, RTW_CHPLAN_MKK2_MKK5 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI16, TXPWR_LMT_ETSI), /* 0x65, RTW_CHPLAN_ETSI1_ETSI16 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC14, TXPWR_LMT_FCC), /* 0x66, RTW_CHPLAN_FCC1_FCC14 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x67, RTW_CHPLAN_FCC1_FCC12 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC14, TXPWR_LMT_FCC), /* 0x68, RTW_CHPLAN_FCC2_FCC14 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x69, RTW_CHPLAN_FCC2_FCC12 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI17, TXPWR_LMT_ETSI), /* 0x6A, RTW_CHPLAN_ETSI1_ETSI17 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC16, TXPWR_LMT_FCC), /* 0x6B, RTW_CHPLAN_WORLD_FCC16 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC13, TXPWR_LMT_FCC), /* 0x6C, RTW_CHPLAN_WORLD_FCC13 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC15, TXPWR_LMT_FCC), /* 0x6D, RTW_CHPLAN_FCC2_FCC15 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x6E, RTW_CHPLAN_WORLD_FCC12 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI), /* 0x6F, RTW_CHPLAN_NULL_ETSI8 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI18, TXPWR_LMT_ETSI), /* 0x70, RTW_CHPLAN_NULL_ETSI18 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI17, TXPWR_LMT_ETSI), /* 0x71, RTW_CHPLAN_NULL_ETSI17 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI19, TXPWR_LMT_ETSI), /* 0x72, RTW_CHPLAN_NULL_ETSI19 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x73, RTW_CHPLAN_WORLD_FCC7 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC17, TXPWR_LMT_FCC), /* 0x74, RTW_CHPLAN_FCC2_FCC17 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI20, TXPWR_LMT_ETSI), /* 0x75, RTW_CHPLAN_WORLD_ETSI20 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC11, TXPWR_LMT_FCC), /* 0x76, RTW_CHPLAN_FCC2_FCC11 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI21, TXPWR_LMT_ETSI), /* 0x77, RTW_CHPLAN_WORLD_ETSI21 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC18, TXPWR_LMT_FCC), /* 0x78, RTW_CHPLAN_FCC1_FCC18 */ + CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK1, TXPWR_LMT_MKK), /* 0x79, RTW_CHPLAN_MKK2_MKK1 */ +}; + +static struct chplan_ent_t RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE = + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_FCC); /* 0x7F, Realtek Define */ + +u8 rtw_chplan_get_default_regd(u8 id) +{ + u8 regd; + + if (id == RTW_CHPLAN_REALTEK_DEFINE) + regd = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd; + else + regd = RTW_ChannelPlanMap[id].regd; + + return regd; +} + +bool rtw_chplan_is_empty(u8 id) +{ + struct chplan_ent_t *chplan_map; + + if (id == RTW_CHPLAN_REALTEK_DEFINE) + chplan_map = &RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE; + else + chplan_map = &RTW_ChannelPlanMap[id]; + + if (chplan_map->rd_2g == RTW_RD_2G_NULL + #ifdef CONFIG_IEEE80211_BAND_5GHZ + && chplan_map->rd_5g == RTW_RD_5G_NULL + #endif + ) + return _TRUE; + + return _FALSE; +} + +bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch) +{ + int i; + + for (i = 0; i < MAX_CHANNEL_NUM; i++) { + if (regsty->excl_chs[i] == 0) + break; + if (regsty->excl_chs[i] == ch) + return _TRUE; + } + return _FALSE; +} + +inline static u8 rtw_rd_5g_band1_passive(u8 rtw_rd_5g) +{ + u8 passive = 0; + + switch (rtw_rd_5g) { + case RTW_RD_5G_FCC13: + case RTW_RD_5G_FCC16: + case RTW_RD_5G_ETSI18: + case RTW_RD_5G_ETSI19: + case RTW_RD_5G_WORLD: + case RTW_RD_5G_WORLD1: + passive = 1; + }; + + return passive; +} + +inline static u8 rtw_rd_5g_band4_passive(u8 rtw_rd_5g) +{ + u8 passive = 0; + + switch (rtw_rd_5g) { + case RTW_RD_5G_MKK5: + case RTW_RD_5G_ETSI16: + case RTW_RD_5G_ETSI18: + case RTW_RD_5G_ETSI19: + case RTW_RD_5G_WORLD: + passive = 1; + }; + + return passive; +} + +u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set) +{ + struct registry_priv *regsty = adapter_to_regsty(padapter); + u8 index, chanset_size = 0; + u8 b5GBand = _FALSE, b2_4GBand = _FALSE; + u8 rd_2g = 0, rd_5g = 0; +#ifdef CONFIG_DFS_MASTER + int i; +#endif + + if (!rtw_is_channel_plan_valid(ChannelPlan)) { + RTW_ERR("ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan); + return chanset_size; + } + + _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); + + if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_2G)) + b2_4GBand = _TRUE; + + if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_5G)) + b5GBand = _TRUE; + + if (b2_4GBand == _FALSE && b5GBand == _FALSE) { + RTW_WARN("HW band_cap has no intersection with SW wireless_mode setting\n"); + return chanset_size; + } + + if (b2_4GBand) { + if (ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE) + rd_2g = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.rd_2g; + else + rd_2g = RTW_ChannelPlanMap[ChannelPlan].rd_2g; + + for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan2G[rd_2g]); index++) { + if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan2G[rd_2g], index)) == _TRUE) + continue; + + if (chanset_size >= MAX_CHANNEL_NUM) { + RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM); + break; + } + + channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan2G[rd_2g], index); + + if (ChannelPlan == RTW_CHPLAN_GLOBAL_DOAMIN + || rd_2g == RTW_RD_2G_GLOBAL + ) { + /* Channel 1~11 is active, and 12~14 is passive */ + if (channel_set[chanset_size].ChannelNum >= 1 && channel_set[chanset_size].ChannelNum <= 11) + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + else if ((channel_set[chanset_size].ChannelNum >= 12 && channel_set[chanset_size].ChannelNum <= 14)) + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + } else if (ChannelPlan == RTW_CHPLAN_WORLD_WIDE_13 + || ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G + || rd_2g == RTW_RD_2G_WORLD + ) { + /* channel 12~13, passive scan */ + if (channel_set[chanset_size].ChannelNum <= 11) + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + else + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + } else + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + + chanset_size++; + } + } + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (b5GBand) { + if (ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE) + rd_5g = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.rd_5g; + else + rd_5g = RTW_ChannelPlanMap[ChannelPlan].rd_5g; + + for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan5G[rd_5g]); index++) { + if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan5G[rd_5g], index)) == _TRUE) + continue; + #ifndef CONFIG_DFS + if (rtw_is_dfs_ch(CH_LIST_CH(RTW_ChannelPlan5G[rd_5g], index))) + continue; + #endif + + if (chanset_size >= MAX_CHANNEL_NUM) { + RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM); + break; + } + + channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan5G[rd_5g], index); + + if ((ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G) /* all channels passive */ + || (rtw_is_5g_band1(channel_set[chanset_size].ChannelNum) + && rtw_rd_5g_band1_passive(rd_5g)) /* band1 passive */ + || (rtw_is_5g_band4(channel_set[chanset_size].ChannelNum) + && rtw_rd_5g_band4_passive(rd_5g)) /* band4 passive */ + || (rtw_is_dfs_ch(channel_set[chanset_size].ChannelNum)) /* DFS channel(band2, 3) passive */ + ) + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + else + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + + chanset_size++; + } + } + + #ifdef CONFIG_DFS_MASTER + for (i = 0; i < chanset_size; i++) + channel_set[i].non_ocp_end_time = rtw_get_current_time(); + #endif +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ + + if (chanset_size) + RTW_INFO(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n" + , FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size); + else + RTW_WARN(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, final chset has no channel\n" + , FUNC_ADPT_ARG(padapter), ChannelPlan); + + return chanset_size; +} + +#ifdef CONFIG_80211AC_VHT +#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val) +#else +#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) +#endif + +#if RTW_DEF_MODULE_REGULATORY_CERT +#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val) , .def_module_flags = (_val) +#else +#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val) +#endif + +/* has def_module_flags specified, used by common map and HAL dfference map */ +#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac, _def_module_flags) \ + {.alpha2 = (_alpha2), .chplan = (_chplan) \ + COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \ + COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \ + } + +#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP + +#include "../platform/custom_country_chplan.h" + +#elif RTW_DEF_MODULE_REGULATORY_CERT + +/* leave def_module_flags empty, def_module_flags check is done on country_chplan_map */ +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) /* 2013 certify */ +static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0), /* Chile */ + COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0), /* China */ + COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */ + COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */ + COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */ + COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */ + COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ + COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0), /* Malaysia */ + COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */ + COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */ + COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */ + COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */ + COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) /* 2014 certify */ +static const struct country_chplan RTL8821AU_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) /* 2014 certify */ +static const struct country_chplan RTL8812AENF_NGFF_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) /* 2013 certify */ +static const struct country_chplan RTL8812AEBT_HMC_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) /* 2012 certify */ +static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0), /* Aruba */ + COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0), /* Barbados */ + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */ + COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */ + COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */ + COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */ + COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */ + COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0), /* Haiti */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ + COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */ + COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */ + COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */ + COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */ + COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */ + COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0), /* Seychelles */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0), /* Saint Vincent and the Grenadines */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) /* 2013 certify */ +static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0), /* Aruba */ + COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0), /* Bahamas */ + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */ + COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */ + COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */ + COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */ + COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ + COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */ + COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */ + COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */ + COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */ + COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) /* 2014 certify */ +static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0), /* Barbados */ + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */ + COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */ + COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */ + COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */ + COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */ + COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0), /* Haiti */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ + COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */ + COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */ + COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */ + COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */ + COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) /* 2013 certify */ +static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0), /* Aruba */ + COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0), /* Colombia */ + COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0), /* Costa Rica */ + COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0), /* Dominican Republic */ + COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0), /* Ecuador */ + COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0), /* Guatemala */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ + COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0), /* Nicaragua */ + COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0), /* Panama */ + COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0), /* Peru */ + COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0), /* Puerto Rico */ + COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0), /* Paraguay */ + COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0), /* Seychelles */ + COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0), /* Sao Tome and Principe */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723DE_NGFF1630) /* 2016 certify */ +static const struct country_chplan RTL8723DE_NGFF1630_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("CA", 0x2A, 1, 0), /* Canada */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822BE) /* 2016 certify */ +static const struct country_chplan RTL8822BE_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */ +}; +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821CE) /* 2016 certify */ +static const struct country_chplan RTL8821CE_country_chplan_exc_map[] = { + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0), /* South Korea */ +}; +#endif + +/** + * rtw_def_module_get_chplan_from_country - + * @country_code: string of country code + * @return: + * Return NULL for case referring to common map + */ +static const struct country_chplan *rtw_def_module_get_chplan_from_country(const char *country_code) +{ + const struct country_chplan *ent = NULL; + const struct country_chplan *hal_map = NULL; + u16 hal_map_sz = 0; + int i; + + /* TODO: runtime selection for multi driver */ +#if (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AE_HMC_M2) + hal_map = RTL8821AE_HMC_M2_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AU) + hal_map = RTL8821AU_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8821AU_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AENF_NGFF) + hal_map = RTL8812AENF_NGFF_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AEBT_HMC) + hal_map = RTL8812AEBT_HMC_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8188EE_HMC_M2) + hal_map = RTL8188EE_HMC_M2_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BE_HMC_M2) + hal_map = RTL8723BE_HMC_M2_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BS_NGFF1216) + hal_map = RTL8723BS_NGFF1216_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8192EEBT_HMC_M2) + hal_map = RTL8192EEBT_HMC_M2_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723DE_NGFF1630) + hal_map = RTL8723DE_NGFF1630_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8723DE_NGFF1630_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8822BE) + hal_map = RTL8822BE_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8822BE_country_chplan_exc_map) / sizeof(struct country_chplan); +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821CE) + hal_map = RTL8821CE_country_chplan_exc_map; + hal_map_sz = sizeof(RTL8821CE_country_chplan_exc_map) / sizeof(struct country_chplan); +#endif + + if (hal_map == NULL || hal_map_sz == 0) + goto exit; + + for (i = 0; i < hal_map_sz; i++) { + if (strncmp(country_code, hal_map[i].alpha2, 2) == 0) { + ent = &hal_map[i]; + break; + } + } + +exit: + return ent; +} +#endif /* CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP or RTW_DEF_MODULE_REGULATORY_CERT */ + +static const struct country_chplan country_chplan_map[] = { + COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x000), /* Andorra */ + COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0x7FB), /* United Arab Emirates */ + COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x000), /* Afghanistan */ + COUNTRY_CHPLAN_ENT("AG", 0x26, 1, 0x000), /* Antigua & Barbuda */ + COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x000), /* Anguilla(UK) */ + COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0x7F1), /* Albania */ + COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0x6B0), /* Armenia */ + COUNTRY_CHPLAN_ENT("AN", 0x26, 1, 0x7F1), /* Netherlands Antilles */ + COUNTRY_CHPLAN_ENT("AO", 0x47, 1, 0x6E0), /* Angola */ + COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x000), /* Antarctica */ + COUNTRY_CHPLAN_ENT("AR", 0x61, 1, 0x7F3), /* Argentina */ + COUNTRY_CHPLAN_ENT("AS", 0x76, 1, 0x000), /* American Samoa */ + COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0x7FB), /* Austria */ + COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0x7FB), /* Australia */ + COUNTRY_CHPLAN_ENT("AW", 0x76, 1, 0x0B0), /* Aruba */ + COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0x7F1), /* Azerbaijan */ + COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0x7F1), /* Bosnia & Herzegovina */ + COUNTRY_CHPLAN_ENT("BB", 0x76, 1, 0x650), /* Barbados */ + COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0x7F1), /* Bangladesh */ + COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0x7FB), /* Belgium */ + COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0x6B0), /* Burkina Faso */ + COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0x7F1), /* Bulgaria */ + COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0x7F1), /* Bahrain */ + COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0x6B0), /* Burundi */ + COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0x6B0), /* Benin */ + COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x610), /* Brunei */ + COUNTRY_CHPLAN_ENT("BO", 0x73, 1, 0x7F1), /* Bolivia */ + COUNTRY_CHPLAN_ENT("BR", 0x62, 1, 0x7F1), /* Brazil */ + COUNTRY_CHPLAN_ENT("BS", 0x76, 1, 0x620), /* Bahamas */ + COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0x6F1), /* Botswana */ + COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0x7F1), /* Belarus */ + COUNTRY_CHPLAN_ENT("BZ", 0x76, 1, 0x000), /* Belize */ + COUNTRY_CHPLAN_ENT("CA", 0x2B, 1, 0x7FB), /* Canada */ + COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x000), /* Cocos (Keeling) Islands (Australia) */ + COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0x6B0), /* Congo, Republic of the */ + COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0x6B0), /* Central African Republic */ + COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0x6B0), /* Congo, Democratic Republic of the. Zaire */ + COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0x7FB), /* Switzerland */ + COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0x7F1), /* Cote d'Ivoire */ + COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x000), /* Cook Islands */ + COUNTRY_CHPLAN_ENT("CL", 0x2D, 1, 0x7F1), /* Chile */ + COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0x6B0), /* Cameroon */ + COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0x7FB), /* China */ + COUNTRY_CHPLAN_ENT("CO", 0x76, 1, 0x7F1), /* Colombia */ + COUNTRY_CHPLAN_ENT("CR", 0x76, 1, 0x7F1), /* Costa Rica */ + COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0x6B0), /* Cape Verde */ + COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x000), /* Christmas Island (Australia) */ + COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0x7FB), /* Cyprus */ + COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0x7FB), /* Czech Republic */ + COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0x7FB), /* Germany */ + COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x680), /* Djibouti */ + COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0x7FB), /* Denmark */ + COUNTRY_CHPLAN_ENT("DM", 0x76, 1, 0x000), /* Dominica */ + COUNTRY_CHPLAN_ENT("DO", 0x76, 1, 0x7F1), /* Dominican Republic */ + COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0x7F1), /* Algeria */ + COUNTRY_CHPLAN_ENT("EC", 0x76, 1, 0x7F1), /* Ecuador */ + COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0x7FB), /* Estonia */ + COUNTRY_CHPLAN_ENT("EG", 0x47, 1, 0x7F1), /* Egypt */ + COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x680), /* Western Sahara */ + COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x000), /* Eritrea */ + COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0x7FB), /* Spain, Canary Islands, Ceuta, Melilla */ + COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0x4B0), /* Ethiopia */ + COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0x7FB), /* Finland */ + COUNTRY_CHPLAN_ENT("FJ", 0x76, 1, 0x600), /* Fiji */ + COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x000), /* Falkland Islands (Islas Malvinas) (UK) */ + COUNTRY_CHPLAN_ENT("FM", 0x76, 1, 0x000), /* Micronesia, Federated States of (USA) */ + COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x000), /* Faroe Islands (Denmark) */ + COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0x7FB), /* France */ + COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0x6B0), /* Gabon */ + COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0x7FB), /* Great Britain (United Kingdom; England) */ + COUNTRY_CHPLAN_ENT("GD", 0x34, 1, 0x0B0), /* Grenada */ + COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x600), /* Georgia */ + COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x080), /* French Guiana */ + COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x000), /* Guernsey (UK) */ + COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0x7F1), /* Ghana */ + COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x600), /* Gibraltar (UK) */ + COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x600), /* Greenland (Denmark) */ + COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0x6B0), /* Gambia */ + COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x610), /* Guinea */ + COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x600), /* Guadeloupe (France) */ + COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0x6B0), /* Equatorial Guinea */ + COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0x7FB), /* Greece */ + COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x000), /* South Georgia and the Sandwich Islands (UK) */ + COUNTRY_CHPLAN_ENT("GT", 0x61, 1, 0x7F1), /* Guatemala */ + COUNTRY_CHPLAN_ENT("GU", 0x76, 1, 0x600), /* Guam (USA) */ + COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0x6B0), /* Guinea-Bissau */ + COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x000), /* Guyana */ + COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0x7FB), /* Hong Kong */ + COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x000), /* Heard and McDonald Islands (Australia) */ + COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0x7F1), /* Honduras */ + COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0x7F9), /* Croatia */ + COUNTRY_CHPLAN_ENT("HT", 0x76, 1, 0x650), /* Haiti */ + COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0x7FB), /* Hungary */ + COUNTRY_CHPLAN_ENT("ID", 0x3D, 0, 0x7F3), /* Indonesia */ + COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0x7FB), /* Ireland */ + COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0x7F1), /* Israel */ + COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x000), /* Isle of Man (UK) */ + COUNTRY_CHPLAN_ENT("IN", 0x48, 1, 0x7F1), /* India */ + COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x000), /* Iraq */ + COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x000), /* Iran */ + COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0x7FB), /* Iceland */ + COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0x7FB), /* Italy */ + COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x000), /* Jersey (UK) */ + COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0x7F1), /* Jamaica */ + COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0x7FB), /* Jordan */ + COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0x7FF), /* Japan- Telec */ + COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0x7F9), /* Kenya */ + COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0x7F1), /* Kyrgyzstan */ + COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0x7F1), /* Cambodia */ + COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x000), /* Kiribati */ + COUNTRY_CHPLAN_ENT("KN", 0x76, 1, 0x000), /* Saint Kitts and Nevis */ + COUNTRY_CHPLAN_ENT("KR", 0x3E, 1, 0x7FB), /* South Korea */ + COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0x7FB), /* Kuwait */ + COUNTRY_CHPLAN_ENT("KY", 0x76, 1, 0x000), /* Cayman Islands (UK) */ + COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x700), /* Kazakhstan */ + COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x000), /* Laos */ + COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0x7F1), /* Lebanon */ + COUNTRY_CHPLAN_ENT("LC", 0x76, 1, 0x000), /* Saint Lucia */ + COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0x7FB), /* Liechtenstein */ + COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0x7F1), /* Sri Lanka */ + COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0x6B0), /* Liberia */ + COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0x7F1), /* Lesotho */ + COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0x7FB), /* Lithuania */ + COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0x7FB), /* Luxembourg */ + COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0x7FB), /* Latvia */ + COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x000), /* Libya */ + COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0x7F1), /* Morocco */ + COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0x7FB), /* Monaco */ + COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0x7F1), /* Moldova */ + COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0x7F1), /* Montenegro */ + COUNTRY_CHPLAN_ENT("MF", 0x76, 1, 0x000), /* Saint Martin */ + COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x620), /* Madagascar */ + COUNTRY_CHPLAN_ENT("MH", 0x76, 1, 0x000), /* Marshall Islands (USA) */ + COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0x7F1), /* Republic of Macedonia (FYROM) */ + COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0x6B0), /* Mali */ + COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x000), /* Burma (Myanmar) */ + COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x000), /* Mongolia */ + COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x600), /* Macau */ + COUNTRY_CHPLAN_ENT("MP", 0x76, 1, 0x000), /* Northern Mariana Islands (USA) */ + COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x640), /* Martinique (France) */ + COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0x6A0), /* Mauritania */ + COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x000), /* Montserrat (UK) */ + COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0x7FB), /* Malta */ + COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0x6B0), /* Mauritius */ + COUNTRY_CHPLAN_ENT("MV", 0x47, 1, 0x000), /* Maldives */ + COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0x6B0), /* Malawi */ + COUNTRY_CHPLAN_ENT("MX", 0x61, 1, 0x7F1), /* Mexico */ + COUNTRY_CHPLAN_ENT("MY", 0x63, 1, 0x7F1), /* Malaysia */ + COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0x7F1), /* Mozambique */ + COUNTRY_CHPLAN_ENT("NA", 0x26, 1, 0x700), /* Namibia */ + COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x000), /* New Caledonia */ + COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0x6B0), /* Niger */ + COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x000), /* Norfolk Island (Australia) */ + COUNTRY_CHPLAN_ENT("NG", 0x75, 1, 0x7F9), /* Nigeria */ + COUNTRY_CHPLAN_ENT("NI", 0x76, 1, 0x7F1), /* Nicaragua */ + COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0x7FB), /* Netherlands */ + COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0x7FB), /* Norway */ + COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0x6F0), /* Nepal */ + COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x000), /* Nauru */ + COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x000), /* Niue */ + COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0x7FB), /* New Zealand */ + COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0x7F9), /* Oman */ + COUNTRY_CHPLAN_ENT("PA", 0x76, 1, 0x7F1), /* Panama */ + COUNTRY_CHPLAN_ENT("PE", 0x76, 1, 0x7F1), /* Peru */ + COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x000), /* French Polynesia (France) */ + COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0x7F1), /* Papua New Guinea */ + COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0x7F1), /* Philippines */ + COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0x7F1), /* Pakistan */ + COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0x7FB), /* Poland */ + COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x000), /* Saint Pierre and Miquelon (France) */ + COUNTRY_CHPLAN_ENT("PR", 0x76, 1, 0x7F1), /* Puerto Rico */ + COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0x7FB), /* Portugal */ + COUNTRY_CHPLAN_ENT("PW", 0x76, 1, 0x000), /* Palau */ + COUNTRY_CHPLAN_ENT("PY", 0x76, 1, 0x7F1), /* Paraguay */ + COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0x7F9), /* Qatar */ + COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x000), /* Reunion (France) */ + COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0x7F1), /* Romania */ + COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0x7F1), /* Serbia, Kosovo */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0x7FB), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0x0B0), /* Rwanda */ + COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0x7FB), /* Saudi Arabia */ + COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x000), /* Solomon Islands */ + COUNTRY_CHPLAN_ENT("SC", 0x76, 1, 0x690), /* Seychelles */ + COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0x7FB), /* Sweden */ + COUNTRY_CHPLAN_ENT("SG", 0x35, 1, 0x7FB), /* Singapore */ + COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x000), /* Saint Helena (UK) */ + COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0x7FB), /* Slovenia */ + COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x000), /* Svalbard (Norway) */ + COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0x7FB), /* Slovakia */ + COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0x6B0), /* Sierra Leone */ + COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x000), /* San Marino */ + COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0x7F1), /* Senegal */ + COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x000), /* Somalia */ + COUNTRY_CHPLAN_ENT("SR", 0x74, 1, 0x000), /* Suriname */ + COUNTRY_CHPLAN_ENT("ST", 0x76, 1, 0x680), /* Sao Tome and Principe */ + COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0x7F1), /* El Salvador */ + COUNTRY_CHPLAN_ENT("SX", 0x76, 1, 0x000), /* Sint Marteen */ + COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x020), /* Swaziland */ + COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x000), /* Turks and Caicos Islands (UK) */ + COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0x6B0), /* Chad */ + COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x680), /* French Southern and Antarctic Lands (FR Southern Territories) */ + COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0x6B0), /* Togo */ + COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0x7F1), /* Thailand */ + COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x640), /* Tajikistan */ + COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x000), /* Tokelau */ + COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x000), /* Turkmenistan */ + COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0x7F1), /* Tunisia */ + COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x000), /* Tonga */ + COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0x7F1), /* Turkey, Northern Cyprus */ + COUNTRY_CHPLAN_ENT("TT", 0x42, 1, 0x3F1), /* Trinidad & Tobago */ + COUNTRY_CHPLAN_ENT("TW", 0x76, 1, 0x7FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0x6F0), /* Tanzania */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 1, 0x7FB), /* Ukraine */ + COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0x6F1), /* Uganda */ + COUNTRY_CHPLAN_ENT("US", 0x76, 1, 0x7FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("UY", 0x30, 1, 0x7F1), /* Uruguay */ + COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0x6F0), /* Uzbekistan */ + COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x000), /* Holy See (Vatican City) */ + COUNTRY_CHPLAN_ENT("VC", 0x76, 1, 0x010), /* Saint Vincent and the Grenadines */ + COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0x7F1), /* Venezuela */ + COUNTRY_CHPLAN_ENT("VI", 0x76, 1, 0x000), /* United States Virgin Islands (USA) */ + COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0x7F1), /* Vietnam */ + COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x000), /* Vanuatu */ + COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x000), /* Wallis and Futuna (France) */ + COUNTRY_CHPLAN_ENT("WS", 0x76, 1, 0x000), /* Samoa */ + COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x040), /* Yemen */ + COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x680), /* Mayotte (France) */ + COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0x7F1), /* South Africa */ + COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0x6B0), /* Zambia */ + COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0x7F1), /* Zimbabwe */ +}; + +/* +* rtw_get_chplan_from_country - +* @country_code: string of country code +* +* Return pointer of struct country_chplan entry or NULL when unsupported country_code is given +*/ +const struct country_chplan *rtw_get_chplan_from_country(const char *country_code) +{ +#if RTW_DEF_MODULE_REGULATORY_CERT + const struct country_chplan *exc_ent = NULL; +#endif + const struct country_chplan *ent = NULL; + const struct country_chplan *map = NULL; + u16 map_sz = 0; + char code[2]; + int i; + + code[0] = alpha_to_upper(country_code[0]); + code[1] = alpha_to_upper(country_code[1]); + +#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP + map = CUSTOMIZED_country_chplan_map; + map_sz = sizeof(CUSTOMIZED_country_chplan_map) / sizeof(struct country_chplan); +#else + #if RTW_DEF_MODULE_REGULATORY_CERT + exc_ent = rtw_def_module_get_chplan_from_country(code); + #endif + map = country_chplan_map; + map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan); +#endif + + for (i = 0; i < map_sz; i++) { + if (strncmp(code, map[i].alpha2, 2) == 0) { + ent = &map[i]; + break; + } + } + + #if RTW_DEF_MODULE_REGULATORY_CERT + if (!ent || !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT)) + exc_ent = ent = NULL; + if (exc_ent) + ent = exc_ent; + #endif + + return ent; +} + +void dump_country_chplan(void *sel, const struct country_chplan *ent) +{ + RTW_PRINT_SEL(sel, "\"%c%c\", 0x%02X%s\n" + , ent->alpha2[0], ent->alpha2[1], ent->chplan + , COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : "" + ); +} + +void dump_country_chplan_map(void *sel) +{ + const struct country_chplan *ent; + u8 code[2]; + +#if RTW_DEF_MODULE_REGULATORY_CERT + RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT:0x%x\n", RTW_DEF_MODULE_REGULATORY_CERT); +#endif +#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP + RTW_PRINT_SEL(sel, "CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\n"); +#endif + + for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) { + for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) { + ent = rtw_get_chplan_from_country(code); + if (!ent) + continue; + + dump_country_chplan(sel, ent); + } + } +} + +void dump_chplan_id_list(void *sel) +{ + u8 first = 1; + int i; + + for (i = 0; i < RTW_CHPLAN_MAX; i++) { + if (!rtw_is_channel_plan_valid(i)) + continue; + + if (first) { + RTW_PRINT_SEL(sel, "0x%02X ", i); + first = 0; + } else + _RTW_PRINT_SEL(sel, "0x%02X ", i); + } + + _RTW_PRINT_SEL(sel, "0x7F\n"); +} + +void dump_chplan_test(void *sel) +{ + int i, j; + + /* check invalid channel */ + for (i = 0; i < RTW_RD_2G_MAX; i++) { + for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan2G[i]); j++) { + if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan2G[i], j)) == 0) + RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan2G[i], j), i, j); + } + } + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + for (i = 0; i < RTW_RD_5G_MAX; i++) { + for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan5G[i]); j++) { + if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan5G[i], j)) == 0) + RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan5G[i], j), i, j); + } + } +#endif +} + +void dump_chplan_ver(void *sel) +{ + RTW_PRINT_SEL(sel, "%s-%s\n", RTW_DOMAIN_MAP_VER, RTW_COUNTRY_MAP_VER); +} diff --git a/core/rtw_chplan.h b/core/rtw_chplan.h new file mode 100644 index 0000000..232cbcd --- /dev/null +++ b/core/rtw_chplan.h @@ -0,0 +1,179 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_CHPLAN_H__ +#define __RTW_CHPLAN_H__ + +enum rtw_chplan_id { + /* ===== 0x00 ~ 0x1F, legacy channel plan ===== */ + RTW_CHPLAN_FCC = 0x00, + RTW_CHPLAN_IC = 0x01, + RTW_CHPLAN_ETSI = 0x02, + RTW_CHPLAN_SPAIN = 0x03, + RTW_CHPLAN_FRANCE = 0x04, + RTW_CHPLAN_MKK = 0x05, + RTW_CHPLAN_MKK1 = 0x06, + RTW_CHPLAN_ISRAEL = 0x07, + RTW_CHPLAN_TELEC = 0x08, + RTW_CHPLAN_GLOBAL_DOAMIN = 0x09, + RTW_CHPLAN_WORLD_WIDE_13 = 0x0A, + RTW_CHPLAN_TAIWAN = 0x0B, + RTW_CHPLAN_CHINA = 0x0C, + RTW_CHPLAN_SINGAPORE_INDIA_MEXICO = 0x0D, + RTW_CHPLAN_KOREA = 0x0E, + RTW_CHPLAN_TURKEY = 0x0F, + RTW_CHPLAN_JAPAN = 0x10, + RTW_CHPLAN_FCC_NO_DFS = 0x11, + RTW_CHPLAN_JAPAN_NO_DFS = 0x12, + RTW_CHPLAN_WORLD_WIDE_5G = 0x13, + RTW_CHPLAN_TAIWAN_NO_DFS = 0x14, + + /* ===== 0x20 ~ 0x7F, new channel plan ===== */ + RTW_CHPLAN_WORLD_NULL = 0x20, + RTW_CHPLAN_ETSI1_NULL = 0x21, + RTW_CHPLAN_FCC1_NULL = 0x22, + RTW_CHPLAN_MKK1_NULL = 0x23, + RTW_CHPLAN_ETSI2_NULL = 0x24, + RTW_CHPLAN_FCC1_FCC1 = 0x25, + RTW_CHPLAN_WORLD_ETSI1 = 0x26, + RTW_CHPLAN_MKK1_MKK1 = 0x27, + RTW_CHPLAN_WORLD_KCC1 = 0x28, + RTW_CHPLAN_WORLD_FCC2 = 0x29, + RTW_CHPLAN_FCC2_NULL = 0x2A, + RTW_CHPLAN_IC1_IC2 = 0x2B, + RTW_CHPLAN_MKK2_NULL = 0x2C, + RTW_CHPLAN_WORLD_CHILE1= 0x2D, + RTW_CHPLAN_WORLD1_WORLD1 = 0x2E, + RTW_CHPLAN_WORLD_CHILE2 = 0x2F, + RTW_CHPLAN_WORLD_FCC3 = 0x30, + RTW_CHPLAN_WORLD_FCC4 = 0x31, + RTW_CHPLAN_WORLD_FCC5 = 0x32, + RTW_CHPLAN_WORLD_FCC6 = 0x33, + RTW_CHPLAN_FCC1_FCC7 = 0x34, + RTW_CHPLAN_WORLD_ETSI2 = 0x35, + RTW_CHPLAN_WORLD_ETSI3 = 0x36, + RTW_CHPLAN_MKK1_MKK2 = 0x37, + RTW_CHPLAN_MKK1_MKK3 = 0x38, + RTW_CHPLAN_FCC1_NCC1 = 0x39, + RTW_CHPLAN_ETSI1_ETSI1 = 0x3A, + RTW_CHPLAN_ETSI1_ACMA1 = 0x3B, + RTW_CHPLAN_ETSI1_ETSI6 = 0x3C, + RTW_CHPLAN_ETSI1_ETSI12 = 0x3D, + RTW_CHPLAN_KCC1_KCC2 = 0x3E, + RTW_CHPLAN_FCC1_NCC2 = 0x40, + RTW_CHPLAN_GLOBAL_NULL = 0x41, + RTW_CHPLAN_ETSI1_ETSI4 = 0x42, + RTW_CHPLAN_FCC1_FCC2 = 0x43, + RTW_CHPLAN_FCC1_NCC3 = 0x44, + RTW_CHPLAN_WORLD_ACMA1 = 0x45, + RTW_CHPLAN_FCC1_FCC8 = 0x46, + RTW_CHPLAN_WORLD_ETSI6 = 0x47, + RTW_CHPLAN_WORLD_ETSI7 = 0x48, + RTW_CHPLAN_WORLD_ETSI8 = 0x49, + RTW_CHPLAN_WORLD_ETSI9 = 0x50, + RTW_CHPLAN_WORLD_ETSI10 = 0x51, + RTW_CHPLAN_WORLD_ETSI11 = 0x52, + RTW_CHPLAN_FCC1_NCC4 = 0x53, + RTW_CHPLAN_WORLD_ETSI12 = 0x54, + RTW_CHPLAN_FCC1_FCC9 = 0x55, + RTW_CHPLAN_WORLD_ETSI13 = 0x56, + RTW_CHPLAN_FCC1_FCC10 = 0x57, + RTW_CHPLAN_MKK2_MKK4 = 0x58, + RTW_CHPLAN_WORLD_ETSI14 = 0x59, + RTW_CHPLAN_FCC1_FCC5 = 0x60, + RTW_CHPLAN_FCC2_FCC7 = 0x61, + RTW_CHPLAN_FCC2_FCC1 = 0x62, + RTW_CHPLAN_WORLD_ETSI15 = 0x63, + RTW_CHPLAN_MKK2_MKK5 = 0x64, + RTW_CHPLAN_ETSI1_ETSI16 = 0x65, + RTW_CHPLAN_FCC1_FCC14 = 0x66, + RTW_CHPLAN_FCC1_FCC12 = 0x67, + RTW_CHPLAN_FCC2_FCC14 = 0x68, + RTW_CHPLAN_FCC2_FCC12 = 0x69, + RTW_CHPLAN_ETSI1_ETSI17 = 0x6A, + RTW_CHPLAN_WORLD_FCC16 = 0x6B, + RTW_CHPLAN_WORLD_FCC13 = 0x6C, + RTW_CHPLAN_FCC2_FCC15 = 0x6D, + RTW_CHPLAN_WORLD_FCC12 = 0x6E, + RTW_CHPLAN_NULL_ETSI8 = 0x6F, + RTW_CHPLAN_NULL_ETSI18 = 0x70, + RTW_CHPLAN_NULL_ETSI17 = 0x71, + RTW_CHPLAN_NULL_ETSI19 = 0x72, + RTW_CHPLAN_WORLD_FCC7 = 0x73, + RTW_CHPLAN_FCC2_FCC17 = 0x74, + RTW_CHPLAN_WORLD_ETSI20 = 0x75, + RTW_CHPLAN_FCC2_FCC11 = 0x76, + RTW_CHPLAN_WORLD_ETSI21 = 0x77, + RTW_CHPLAN_FCC1_FCC18 = 0x78, + RTW_CHPLAN_MKK2_MKK1 = 0x79, + + RTW_CHPLAN_MAX, + RTW_CHPLAN_REALTEK_DEFINE = 0x7F, + RTW_CHPLAN_UNSPECIFIED = 0xFF, +}; + +u8 rtw_chplan_get_default_regd(u8 id); +bool rtw_chplan_is_empty(u8 id); +#define rtw_is_channel_plan_valid(chplan) (((chplan) < RTW_CHPLAN_MAX || (chplan) == RTW_CHPLAN_REALTEK_DEFINE) && !rtw_chplan_is_empty(chplan)) +#define rtw_is_legacy_channel_plan(chplan) ((chplan) < 0x20) + +struct _RT_CHANNEL_INFO; +u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, struct _RT_CHANNEL_INFO *channel_set); + +#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF) + +#define RTW_MODULE_RTL8821AE_HMC_M2 BIT0 /* RTL8821AE(HMC + M.2) */ +#define RTW_MODULE_RTL8821AU BIT1 /* RTL8821AU */ +#define RTW_MODULE_RTL8812AENF_NGFF BIT2 /* RTL8812AENF(8812AE+8761)_NGFF */ +#define RTW_MODULE_RTL8812AEBT_HMC BIT3 /* RTL8812AEBT(8812AE+8761)_HMC */ +#define RTW_MODULE_RTL8188EE_HMC_M2 BIT4 /* RTL8188EE(HMC + M.2) */ +#define RTW_MODULE_RTL8723BE_HMC_M2 BIT5 /* RTL8723BE(HMC + M.2) */ +#define RTW_MODULE_RTL8723BS_NGFF1216 BIT6 /* RTL8723BS(NGFF1216) */ +#define RTW_MODULE_RTL8192EEBT_HMC_M2 BIT7 /* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */ +#define RTW_MODULE_RTL8723DE_NGFF1630 BIT8 /* RTL8723DE(NGFF1630) */ +#define RTW_MODULE_RTL8822BE BIT9 /* RTL8822BE */ +#define RTW_MODULE_RTL8821CE BIT10 /* RTL8821CE */ + +struct country_chplan { + char alpha2[2]; + u8 chplan; +#ifdef CONFIG_80211AC_VHT + u8 en_11ac; +#endif +#if RTW_DEF_MODULE_REGULATORY_CERT + u16 def_module_flags; /* RTW_MODULE_RTLXXX */ +#endif +}; + +#ifdef CONFIG_80211AC_VHT +#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac) +#else +#define COUNTRY_CHPLAN_EN_11AC(_ent) 0 +#endif + +#if RTW_DEF_MODULE_REGULATORY_CERT +#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) ((_ent)->def_module_flags) +#else +#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) 0 +#endif + +const struct country_chplan *rtw_get_chplan_from_country(const char *country_code); + +void dump_country_chplan(void *sel, const struct country_chplan *ent); +void dump_country_chplan_map(void *sel); +void dump_chplan_id_list(void *sel); +void dump_chplan_test(void *sel); +void dump_chplan_ver(void *sel); + +#endif /* __RTW_CHPLAN_H__ */ diff --git a/core/rtw_cmd.c b/core/rtw_cmd.c index fef8033..8888312 100644 --- a/core/rtw_cmd.c +++ b/core/rtw_cmd.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_CMD_C_ #include @@ -38,9 +33,7 @@ sint _rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) _rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0); /* _rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); */ - /*_rtw_init_sema(&(pcmdpriv->terminate_cmdthread_sema), 0);*/ _rtw_init_sema(&(pcmdpriv->start_cmdthread_sema), 0); - _rtw_init_completion(&pcmdpriv->cmdthread_comp); _rtw_init_queue(&(pcmdpriv->cmd_queue)); @@ -152,7 +145,6 @@ sint _rtw_init_evt_priv(struct evt_priv *pevtpriv) #ifdef CONFIG_EVENT_THREAD_MODE _rtw_init_sema(&(pevtpriv->evt_notify), 0); - _rtw_init_sema(&(pevtpriv->terminate_evtthread_sema), 0); pevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4); if (pevtpriv->evt_allocated_buf == NULL) { @@ -205,8 +197,6 @@ void _rtw_free_evt_priv(struct evt_priv *pevtpriv) #ifdef CONFIG_EVENT_THREAD_MODE _rtw_free_sema(&(pevtpriv->evt_notify)); - _rtw_free_sema(&(pevtpriv->terminate_evtthread_sema)); - if (pevtpriv->evt_allocated_buf) rtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4); @@ -237,7 +227,6 @@ void _rtw_free_cmd_priv(struct cmd_priv *pcmdpriv) _rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock)); _rtw_free_sema(&(pcmdpriv->cmd_queue_sema)); /* _rtw_free_sema(&(pcmdpriv->cmd_done_sema)); */ - /*_rtw_free_sema(&(pcmdpriv->terminate_cmdthread_sema));*/ _rtw_free_sema(&(pcmdpriv->start_cmdthread_sema)); if (pcmdpriv->cmd_allocated_buf) @@ -463,7 +452,7 @@ u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) #ifdef CONFIG_CONCURRENT_MODE /* change pcmdpriv to primary's pcmdpriv */ - if (padapter->adapter_type != PRIMARY_ADAPTER) + if (!is_primary_adapter(padapter)) pcmdpriv = &(GET_PRIMARY_ADAPTER(padapter)->cmdpriv); #endif @@ -513,8 +502,6 @@ void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv) void rtw_free_cmd_obj(struct cmd_obj *pcmd) { - struct drvextra_cmd_parm *extra_parm = NULL; - if (pcmd->parmbuf != NULL) { /* free parmbuf in cmd_obj */ rtw_mfree((unsigned char *)pcmd->parmbuf, pcmd->cmdsz); @@ -528,19 +515,15 @@ void rtw_free_cmd_obj(struct cmd_obj *pcmd) /* free cmd_obj */ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); - } void rtw_stop_cmd_thread(_adapter *adapter) { - if (adapter->cmdThread && - ATOMIC_READ(&(adapter->cmdpriv.cmdthd_running)) == _TRUE && - adapter->cmdpriv.stop_req == 0) { - adapter->cmdpriv.stop_req = 1; + if (adapter->cmdThread) { _rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema); - /*_rtw_down_sema(&adapter->cmdpriv.terminate_cmdthread_sema);*/ - rtw_wait_for_thread_stop(&adapter->cmdpriv.cmdthread_comp); + rtw_thread_stop(adapter->cmdThread); + adapter->cmdThread = NULL; } } @@ -549,7 +532,7 @@ thread_return rtw_cmd_thread(thread_context context) u8 ret; struct cmd_obj *pcmd; u8 *pcmdbuf, *prspbuf; - u32 cmd_start_time; + systime cmd_start_time; u32 cmd_process_time; u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf); void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd); @@ -562,10 +545,7 @@ thread_return rtw_cmd_thread(thread_context context) pcmdbuf = pcmdpriv->cmd_buf; prspbuf = pcmdpriv->rsp_buf; - - pcmdpriv->stop_req = 0; ATOMIC_SET(&(pcmdpriv->cmdthd_running), _TRUE); - /*_rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema);*/ _rtw_up_sema(&pcmdpriv->start_cmdthread_sema); @@ -576,16 +556,10 @@ thread_return rtw_cmd_thread(thread_context context) } if (RTW_CANNOT_RUN(padapter)) { - RTW_PRINT("%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\n", - __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False" - , __LINE__); - break; - } - - if (pcmdpriv->stop_req) { - RTW_PRINT(FUNC_ADPT_FMT" stop_req:%u, break\n", FUNC_ADPT_ARG(padapter), pcmdpriv->stop_req); + RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n", + FUNC_ADPT_ARG(padapter), + rtw_is_drv_stopped(padapter) ? "True" : "False", + rtw_is_surprise_removed(padapter) ? "True" : "False"); break; } @@ -644,6 +618,10 @@ thread_return rtw_cmd_thread(thread_context context) if (extra_parm && extra_parm->pbuf && extra_parm->size > 0) rtw_mfree(extra_parm->pbuf, extra_parm->size); } + #ifdef CONFIG_DFS + else if (pcmd->cmdcode == GEN_CMD_CODE(_SetChannelSwitch)) + adapter_to_rfctl(padapter)->csa_ch = 0; + #endif goto post_process; } @@ -740,6 +718,10 @@ thread_return rtw_cmd_thread(thread_context context) if (extra_parm->pbuf && extra_parm->size > 0) rtw_mfree(extra_parm->pbuf, extra_parm->size); } + #ifdef CONFIG_DFS + else if (pcmd->cmdcode == GEN_CMD_CODE(_SetChannelSwitch)) + adapter_to_rfctl(padapter)->csa_ch = 0; + #endif _enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); if (pcmd->sctx) { @@ -752,8 +734,10 @@ thread_return rtw_cmd_thread(thread_context context) rtw_free_cmd_obj(pcmd); } while (1); - /*_rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema);*/ - thread_exit(&pcmdpriv->cmdthread_comp); + RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter)); + + rtw_thread_wait_stop(); + return 0; } @@ -863,23 +847,27 @@ u8 rtw_setstandby_cmd(_adapter *padapter, uint action) return ret; } +void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + + _rtw_memset(pparm, 0, sizeof(struct sitesurvey_parm)); + pparm->scan_mode = pmlmepriv->scan_mode; +} + /* rtw_sitesurvey_cmd(~) ### NOTE:#### (!!!!) MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock */ -u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, - struct rtw_ieee80211_channel *ch, int ch_num) +u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm) { u8 res = _FAIL; struct cmd_obj *ph2c; struct sitesurvey_parm *psurveyPara; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#endif /* CONFIG_P2P */ - #ifdef CONFIG_LPS if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) @@ -901,60 +889,25 @@ u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, return _FAIL; } - rtw_free_network_queue(padapter, _FALSE); + if (pparm) + _rtw_memcpy(psurveyPara, pparm, sizeof(struct sitesurvey_parm)); + else + psurveyPara->scan_mode = pmlmepriv->scan_mode; + rtw_free_network_queue(padapter, _FALSE); init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey)); - /* psurveyPara->bsslimit = 48; */ - psurveyPara->scan_mode = pmlmepriv->scan_mode; - - /* prepare ssid list */ - if (ssid) { - int i; - for (i = 0; i < ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) { - if (ssid[i].SsidLength) { - _rtw_memcpy(&psurveyPara->ssid[i], &ssid[i], sizeof(NDIS_802_11_SSID)); - psurveyPara->ssid_num++; - if (0) - RTW_INFO(FUNC_ADPT_FMT" ssid:(%s, %d)\n", FUNC_ADPT_ARG(padapter), - psurveyPara->ssid[i].Ssid, psurveyPara->ssid[i].SsidLength); - } - } - } - - /* prepare channel list */ - if (ch) { - int i; - for (i = 0; i < ch_num && i < RTW_CHANNEL_SCAN_AMOUNT; i++) { - if (ch[i].hw_value && !(ch[i].flags & RTW_IEEE80211_CHAN_DISABLED)) { - _rtw_memcpy(&psurveyPara->ch[i], &ch[i], sizeof(struct rtw_ieee80211_channel)); - psurveyPara->ch_num++; - if (0) - RTW_INFO(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), - psurveyPara->ch[i].hw_value); - } - } - } - set_fwstate(pmlmepriv, _FW_UNDER_SURVEY); res = rtw_enqueue_cmd(pcmdpriv, ph2c); if (res == _SUCCESS) { + u32 scan_timeout_ms; pmlmepriv->scan_start_time = rtw_get_current_time(); - -#ifdef CONFIG_SCAN_BACKOP - if (rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) { - if (is_supported_5g(padapter->registrypriv.wireless_mode) - && IsSupported24G(padapter->registrypriv.wireless_mode)) /* dual band */ - mlme_set_scan_to_timer(pmlmepriv, CONC_SCANNING_TIMEOUT_DUAL_BAND); - else /* single band */ - mlme_set_scan_to_timer(pmlmepriv, CONC_SCANNING_TIMEOUT_SINGLE_BAND); - } else -#endif /* CONFIG_SCAN_BACKOP */ - mlme_set_scan_to_timer(pmlmepriv, SCANNING_TIMEOUT); + scan_timeout_ms = rtw_scan_timeout_decision(padapter); + mlme_set_scan_to_timer(pmlmepriv,scan_timeout_ms); rtw_led_control(padapter, LED_CTL_SITE_SURVEY); } else @@ -1267,17 +1220,16 @@ void rtw_readtssi_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) } static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc - , s16 req_ch, s8 req_bw, s8 req_offset) + , u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset) { struct cmd_obj *cmdobj; struct createbss_parm *parm; struct cmd_priv *pcmdpriv = &adapter->cmdpriv; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; struct submit_ctx sctx; u8 res = _SUCCESS; if (req_ch > 0 && req_bw >= 0 && req_offset >= 0) { - if (!rtw_chset_is_chbw_valid(adapter->mlmeextpriv.channel_set, req_ch, req_bw, req_offset)) { + if (!rtw_chset_is_chbw_valid(adapter_to_chset(adapter), req_ch, req_bw, req_offset)) { res = _FAIL; goto exit; } @@ -1295,6 +1247,8 @@ static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc parm->adhoc = 1; } else { parm->adhoc = 0; + parm->ifbmp = ifbmp; + parm->excl_ifbmp = excl_ifbmp; parm->req_ch = req_ch; parm->req_bw = req_bw; parm->req_offset = req_offset; @@ -1340,7 +1294,8 @@ inline u8 rtw_create_ibss_cmd(_adapter *adapter, int flags) { return rtw_createbss_cmd(adapter, flags , 1 - , 0, -1, -1 /* for now, adhoc doesn't support ch,bw,offset request */ + , 0, 0 + , 0, REQ_BW_NONE, REQ_OFFSET_NONE /* for now, adhoc doesn't support ch,bw,offset request */ ); } @@ -1348,18 +1303,57 @@ inline u8 rtw_startbss_cmd(_adapter *adapter, int flags) { return rtw_createbss_cmd(adapter, flags , 0 - , 0, -1, -1 /* excute entire AP setup cmd */ + , BIT(adapter->iface_id), 0 + , 0, REQ_BW_NONE, REQ_OFFSET_NONE /* excute entire AP setup cmd */ ); } -inline u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags, s16 req_ch, s8 req_bw, s8 req_offset) +inline u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags + , u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset) { return rtw_createbss_cmd(adapter, flags , 0 + , ifbmp, excl_ifbmp , req_ch, req_bw, req_offset ); } +#ifdef CONFIG_RTW_80211R +static void rtw_ft_validate_akm_type(_adapter *padapter, + struct wlan_network *pnetwork) +{ + struct security_priv *psecuritypriv = &(padapter->securitypriv); + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + u32 tmp_len; + u8 *ptmp; + + /*IEEE802.11-2012 Std. Table 8-101-AKM suite selectors*/ + if (rtw_ft_valid_akm(padapter, psecuritypriv->rsn_akm_suite_type)) { + ptmp = rtw_get_ie(&pnetwork->network.IEs[12], + _MDIE_, &tmp_len, (pnetwork->network.IELength-12)); + if (ptmp) { + pft_roam->mdid = *(u16 *)(ptmp+2); + pft_roam->ft_cap = *(ptmp+4); + + RTW_INFO("FT: target " MAC_FMT " mdid=(0x%2x), capacity=(0x%2x)\n", + MAC_ARG(pnetwork->network.MacAddress), pft_roam->mdid, pft_roam->ft_cap); + rtw_ft_set_flags(padapter, RTW_FT_PEER_EN); + + if (rtw_ft_otd_roam_en(padapter)) + rtw_ft_set_flags(padapter, RTW_FT_PEER_OTD_EN); + } else { + /* Don't use FT roaming if target AP cannot support FT */ + rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN)); + rtw_ft_reset_status(padapter); + } + } else { + /* It could be a non-FT connection */ + rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN)); + rtw_ft_reset_status(padapter); + } +} +#endif + u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) { u8 *auth, res = _SUCCESS; @@ -1380,11 +1374,9 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u32 tmp_len; u8 *ptmp = NULL; -#ifdef CONFIG_RTW_80211R - struct _ft_priv *pftpriv = &pmlmepriv->ftpriv; -#endif rtw_led_control(padapter, LED_CTL_START_TO_LINK); @@ -1417,17 +1409,21 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) set_fwstate(pmlmepriv, WIFI_STATION_STATE); break; - case Ndis802_11APMode: - case Ndis802_11AutoUnknown: - case Ndis802_11InfrastructureMax: - case Ndis802_11Monitor: + default: + rtw_warn_on(1); break; - } } pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->network.IEs, pnetwork->network.IELength); +#ifdef CONFIG_80211AC_VHT + /* save AP beamform_cap info for BCM IOT issue */ + if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) + pvhtpriv->ap_is_mu_bfer = + get_vht_mu_bfer_cap(pnetwork->network.IEs, + pnetwork->network.IELength); +#endif /* Modified by Arvin 2015/05/13 Solution for allocating a new WLAN_BSSID_EX to avoid race condition issue between disconnect and joinbss @@ -1464,12 +1460,19 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) if (pmlmepriv->assoc_by_bssid == _FALSE) _rtw_memcpy(&pmlmepriv->assoc_bssid[0], &pnetwork->network.MacAddress[0], ETH_ALEN); - psecnetwork->IELength = rtw_restruct_sec_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength); + /* copy fixed ie */ + _rtw_memcpy(psecnetwork->IEs, pnetwork->network.IEs, 12); + psecnetwork->IELength = 12; + + psecnetwork->IELength += rtw_restruct_sec_ie(padapter, psecnetwork->IEs + psecnetwork->IELength); pqospriv->qos_option = 0; if (pregistrypriv->wmm_enable) { +#ifdef CONFIG_WMMPS_STA + rtw_uapsd_use_default_setting(padapter); +#endif /* CONFIG_WMMPS_STA */ tmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength); if (psecnetwork->IELength != tmp_len) { @@ -1482,67 +1485,42 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) #ifdef CONFIG_80211N_HT phtpriv->ht_option = _FALSE; - ptmp = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &tmp_len, pnetwork->network.IELength - 12); - if (pregistrypriv->ht_enable && ptmp && tmp_len > 0) { - /* Added by Albert 2010/06/23 */ - /* For the WEP mode, we will use the bg mode to do the connection to avoid some IOT issue. */ - /* Especially for Realtek 8192u SoftAP. */ - if ((padapter->securitypriv.dot11PrivacyAlgrthm != _WEP40_) && - (padapter->securitypriv.dot11PrivacyAlgrthm != _WEP104_) && - (padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_)) { - rtw_ht_use_default_setting(padapter); - - rtw_build_wmm_ie_ht(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength); - - /* rtw_restructure_ht_ie */ - rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[12], &psecnetwork->IEs[0], - pnetwork->network.IELength - 12, &psecnetwork->IELength, - pnetwork->network.Configuration.DSConfig); + if (pregistrypriv->ht_enable && is_supported_ht(pregistrypriv->wireless_mode)) { + ptmp = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &tmp_len, pnetwork->network.IELength - 12); + if (ptmp && tmp_len > 0) { + /* Added by Albert 2010/06/23 */ + /* For the WEP mode, we will use the bg mode to do the connection to avoid some IOT issue. */ + /* Especially for Realtek 8192u SoftAP. */ + if ((padapter->securitypriv.dot11PrivacyAlgrthm != _WEP40_) && + (padapter->securitypriv.dot11PrivacyAlgrthm != _WEP104_) && + (padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_)) { + rtw_ht_use_default_setting(padapter); + + /* rtw_restructure_ht_ie */ + rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[12], &psecnetwork->IEs[0], + pnetwork->network.IELength - 12, &psecnetwork->IELength, + pnetwork->network.Configuration.DSConfig); + } } } #ifdef CONFIG_80211AC_VHT pvhtpriv->vht_option = _FALSE; if (phtpriv->ht_option - && REGSTY_IS_11AC_ENABLE(pregistrypriv) - && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent)) - ) { + && REGSTY_IS_11AC_ENABLE(pregistrypriv) + && is_supported_vht(pregistrypriv->wireless_mode) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) + ) { rtw_restructure_vht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, &psecnetwork->IELength); } #endif +#endif /* CONFIG_80211N_HT */ rtw_append_exented_cap(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength); -#endif /* CONFIG_80211N_HT */ - #ifdef CONFIG_RTW_80211R - /*IEEE802.11-2012 Std. Table 8-101¡XAKM suite selectors*/ - if ((rtw_chk_ft_flags(padapter, RTW_FT_STA_SUPPORTED)) && - ((psecuritypriv->rsn_akm_suite_type == 3) || (psecuritypriv->rsn_akm_suite_type == 4)) - ) { - ptmp = rtw_get_ie(&pnetwork->network.IEs[12], _MDIE_, &tmp_len, pnetwork->network.IELength-12); - if (ptmp) { - _rtw_memcpy(&pftpriv->mdid, ptmp+2, 2); - pftpriv->ft_cap = *(ptmp+4); - - RTW_INFO("FT: Target AP "MAC_FMT" MDID=(0x%2x), capacity=(0x%2x)\n", MAC_ARG(pnetwork->network.MacAddress), pftpriv->mdid, pftpriv->ft_cap); - rtw_set_ft_flags(padapter, RTW_FT_SUPPORTED); - if ((rtw_chk_ft_flags(padapter, RTW_FT_STA_OVER_DS_SUPPORTED)) && (pftpriv->ft_roam_on_expired == _FALSE) && (pftpriv->ft_cap & 0x01)) - rtw_set_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED); - } else { - /*Don't use FT roaming if Target AP cannot support FT*/ - RTW_INFO("FT: Target AP "MAC_FMT" could not support FT\n", MAC_ARG(pnetwork->network.MacAddress)); - rtw_clr_ft_flags(padapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); - rtw_reset_ft_status(padapter); - } - } else { - /*It could be a non-FT connection*/ - RTW_INFO("FT: non-FT rtw_joinbss_cmd\n"); - rtw_clr_ft_flags(padapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); - rtw_reset_ft_status(padapter); - } + rtw_ft_validate_akm_type(padapter, pnetwork); #endif #if 0 @@ -1598,8 +1576,6 @@ u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for struct submit_ctx sctx; u8 res = _SUCCESS; - - /* prepare cmd parameter */ param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param)); if (param == NULL) { @@ -1642,39 +1618,55 @@ u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for return res; } -u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue) +u8 rtw_setopmode_cmd(_adapter *adapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags) { - struct cmd_obj *ph2c; - struct setopmode_parm *psetop; - - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; - - psetop = (struct setopmode_parm *)rtw_zmalloc(sizeof(struct setopmode_parm)); + struct cmd_obj *cmdobj; + struct setopmode_parm *parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; - if (psetop == NULL) { + /* prepare cmd parameter */ + parm = (struct setopmode_parm *)rtw_zmalloc(sizeof(*parm)); + if (parm == NULL) { res = _FAIL; goto exit; } - psetop->mode = (u8)networktype; + parm->mode = (u8)networktype; - if (enqueue) { - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { - rtw_mfree((u8 *)psetop, sizeof(*psetop)); + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != setopmode_hdl(adapter, (u8 *)parm)) + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); goto exit; } - init_h2fwcmd_w_parm_no_rsp(ph2c, psetop, _SetOpMode_CMD_); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); - } else { - setopmode_hdl(padapter, (u8 *)psetop); - rtw_mfree((u8 *)psetop, sizeof(*psetop)); - } -exit: + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, _SetOpMode_CMD_); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 2000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + } + } +exit: return res; } @@ -1696,16 +1688,17 @@ u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool goto exit; } - _rtw_memcpy(psetstakey_para->addr, sta->hwaddr, ETH_ALEN); + _rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) psetstakey_para->algorithm = (unsigned char) psecuritypriv->dot11PrivacyAlgrthm; else GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE); - if (key_type == GROUP_KEY) + if (key_type == GROUP_KEY) { _rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, 16); - else if (key_type == UNICAST_KEY) + psetstakey_para->gk = 1; + } else if (key_type == UNICAST_KEY) _rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, 16); #ifdef CONFIG_TDLS else if (key_type == TDLS_KEY) { @@ -1753,15 +1746,17 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) struct set_stakey_parm *psetstakey_para; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; struct set_stakey_rsp *psetstakey_rsp = NULL; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct security_priv *psecuritypriv = &padapter->securitypriv; s16 cam_id = 0; u8 res = _SUCCESS; + if (!sta) { + RTW_ERR("%s sta == NULL\n", __func__); + goto exit; + } if (!enqueue) { - while ((cam_id = rtw_camid_search(padapter, sta->hwaddr, -1, -1)) >= 0) { - RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->hwaddr), cam_id); + while ((cam_id = rtw_camid_search(padapter, sta->cmn.mac_addr, -1, -1)) >= 0) { + RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->cmn.mac_addr), cam_id); clear_cam_entry(padapter, cam_id); rtw_camid_free(padapter, cam_id); } @@ -1791,7 +1786,7 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) ph2c->rsp = (u8 *) psetstakey_rsp; ph2c->rspsz = sizeof(struct set_stakey_rsp); - _rtw_memcpy(psetstakey_para->addr, sta->hwaddr, ETH_ALEN); + _rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN); psetstakey_para->algorithm = _NO_PRIVACY_; @@ -2031,41 +2026,58 @@ u8 rtw_reset_securitypriv_cmd(_adapter *padapter) } -u8 rtw_free_assoc_resources_cmd(_adapter *padapter) +void free_assoc_resources_hdl(_adapter *padapter, u8 lock_scanned_queue) { - struct cmd_obj *ph2c; + rtw_free_assoc_resources(padapter, lock_scanned_queue); +} + +u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags) +{ + struct cmd_obj *cmd; struct drvextra_cmd_parm *pdrvextra_cmd_parm; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct submit_ctx sctx; u8 res = _SUCCESS; - - ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (ph2c == NULL) { - res = _FAIL; - goto exit; - } - - pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); - res = _FAIL; - goto exit; + if (flags & RTW_CMDF_DIRECTLY) { + free_assoc_resources_hdl(padapter, lock_scanned_queue); } + else { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { + res = _FAIL; + goto exit; + } - pdrvextra_cmd_parm->ec_id = FREE_ASSOC_RESOURCES; - pdrvextra_cmd_parm->type = 0; - pdrvextra_cmd_parm->size = 0; - pdrvextra_cmd_parm->pbuf = NULL; + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } - init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + pdrvextra_cmd_parm->ec_id = FREE_ASSOC_RESOURCES; + pdrvextra_cmd_parm->type = lock_scanned_queue; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + init_h2fwcmd_w_parm_no_rsp(cmd, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + if (flags & RTW_CMDF_WAIT_ACK) { + cmd->sctx = &sctx; + rtw_sctx_init(&sctx, 2000); + } - /* rtw_enqueue_cmd(pcmdpriv, ph2c); */ - res = rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, cmd); + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmd->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + } + } exit: - - return res; } @@ -2110,12 +2122,12 @@ u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter) } -u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue) +u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags) { struct cmd_obj *pcmdobj; struct set_ch_parm *set_ch_parm; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - + struct submit_ctx sctx; u8 res = _SUCCESS; @@ -2134,7 +2146,13 @@ u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue) set_ch_parm->bw = bw; set_ch_parm->ch_offset = ch_offset; - if (enqueue) { + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != rtw_set_chbw_hdl(padapter, (u8 *)set_ch_parm)) + res = _FAIL; + + rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); + } else { /* need enqueue, prepare cmd_obj and enqueue */ pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmdobj == NULL) { @@ -2144,13 +2162,21 @@ u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue) } init_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, GEN_CMD_CODE(_SetChannel)); + + if (flags & RTW_CMDF_WAIT_ACK) { + pcmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 10 * 1000); + } + res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); - } else { - /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ - if (H2C_SUCCESS != set_ch_hdl(padapter, (u8 *)set_ch_parm)) - res = _FAIL; - rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + pcmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + } } /* do something based on res... */ @@ -2168,7 +2194,6 @@ u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct cou struct cmd_obj *cmdobj; struct SetChannelPlan_param *parm; struct cmd_priv *pcmdpriv = &adapter->cmdpriv; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; struct submit_ctx sctx; u8 res = _SUCCESS; @@ -2227,12 +2252,29 @@ u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct cou if (sctx.status == RTW_SCTX_SUBMITTED) cmdobj->sctx = NULL; _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status != RTW_SCTX_DONE_SUCCESS) + res = _FAIL; } - } -exit: + /* allow set channel plan when cmd_thread is not running */ + if (res != _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + parm = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(*parm)); + if (parm == NULL) { + res = _FAIL; + goto exit; + } + parm->country_ent = country_ent; + parm->channel_plan = chplan; + if (H2C_SUCCESS != set_chplan_hdl(adapter, (u8 *)parm)) + res = _FAIL; + else + res = _SUCCESS; + rtw_mfree((u8 *)parm, sizeof(*parm)); + } + } +exit: return res; } @@ -2261,7 +2303,7 @@ inline u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_ RTW_PRINT("%s country_code:\"%c%c\" mapping to chplan:0x%02x\n", __func__, country_code[0], country_code[1], ent->chplan); - return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_MAX, ent, swconfig); + return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, ent, swconfig); } u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed) @@ -2298,54 +2340,34 @@ u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed) return res; } -u8 rtw_set_csa_cmd(_adapter *padapter, u8 new_ch_no) +u8 rtw_set_csa_cmd(_adapter *adapter) { - struct cmd_obj *pcmdobj; - struct SetChannelSwitch_param *setChannelSwitch_param; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - + struct cmd_obj *cmdobj; + struct cmd_priv *cmdpriv = &adapter->cmdpriv; u8 res = _SUCCESS; - - - pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); - if (pcmdobj == NULL) { - res = _FAIL; - goto exit; - } - - setChannelSwitch_param = (struct SetChannelSwitch_param *)rtw_zmalloc(sizeof(struct SetChannelSwitch_param)); - if (setChannelSwitch_param == NULL) { - rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); + cmdobj = rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) { res = _FAIL; goto exit; } - setChannelSwitch_param->new_ch_no = new_ch_no; - - init_h2fwcmd_w_parm_no_rsp(pcmdobj, setChannelSwitch_param, GEN_CMD_CODE(_SetChannelSwitch)); - res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); + init_h2fwcmd_w_parm_no_parm_rsp(cmdobj, GEN_CMD_CODE(_SetChannelSwitch)); + res = rtw_enqueue_cmd(cmdpriv, cmdobj); exit: - - return res; } u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option) { + u8 res = _SUCCESS; +#ifdef CONFIG_TDLS struct cmd_obj *pcmdobj; struct TDLSoption_param *TDLSoption; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; - - -#ifdef CONFIG_TDLS - - pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmdobj == NULL) { res = _FAIL; @@ -2367,11 +2389,8 @@ u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option) init_h2fwcmd_w_parm_no_rsp(pcmdobj, TDLSoption, GEN_CMD_CODE(_TDLS)); res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); -#endif /* CONFIG_TDLS */ - exit: - - +#endif /* CONFIG_TDLS */ return res; } @@ -2410,24 +2429,244 @@ u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter) return res; } -/* from_timer == 1 means driver is in LPS */ -u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) +u8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter) { - u8 bEnterPS = _FALSE; - u16 BusyThresholdHigh; - u16 BusyThresholdLow; - u16 BusyThreshold; - u8 bBusyTraffic = _FALSE, bTxBusyTraffic = _FALSE, bRxBusyTraffic = _FALSE; - u8 bHigherBusyTraffic = _FALSE, bHigherBusyRxTraffic = _FALSE, bHigherBusyTxTraffic = _FALSE; + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct cmd_priv *cmdpriv = &adapter->cmdpriv; + u8 res = _SUCCESS; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); -#ifdef CONFIG_TDLS + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) { + res = _FAIL; + goto exit; + } + + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + rtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + parm->ec_id = PERIOD_TSF_UPDATE_END_WK_CID; + parm->type = 0; + parm->size = 0; + parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(cmdpriv, cmdobj); + +exit: + return res; +} +#ifdef CONFIG_LPS +#ifdef CONFIG_LPS_CHK_BY_TP +u8 _lps_chk_by_tp(_adapter *adapter, u8 from_timer) +{ + u8 enter_ps = _FALSE; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *psta; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + u32 tx_tp_mbits, rx_tp_mbits, bi_tp_mbits; + + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta == NULL) { + RTW_ERR(ADPT_FMT" sta == NULL\n", ADPT_ARG(adapter)); + rtw_warn_on(1); + return enter_ps; + } + + psta->sta_stats.acc_tx_bytes = psta->sta_stats.tx_bytes; + psta->sta_stats.acc_rx_bytes = psta->sta_stats.rx_bytes; + +#if 1 + tx_tp_mbits = psta->sta_stats.tx_tp_kbits >> 10; + rx_tp_mbits = psta->sta_stats.rx_tp_kbits >> 10; + bi_tp_mbits = tx_tp_mbits + rx_tp_mbits; +#else + tx_tp_mbits = psta->sta_stats.smooth_tx_tp_kbits >> 10; + rx_tp_mbits = psta->sta_stats.smooth_rx_tp_kbits >> 10; + bi_tp_mbits = tx_tp_mbits + rx_tp_mbits; +#endif + + if ((bi_tp_mbits >= pwrpriv->lps_bi_tp_th) || + (tx_tp_mbits >= pwrpriv->lps_tx_tp_th) || + (rx_tp_mbits >= pwrpriv->lps_rx_tp_th)) { + enter_ps = _FALSE; + pwrpriv->lps_chk_cnt = pwrpriv->lps_chk_cnt_th; + } + else { + if (pwrpriv->lps_chk_cnt && --pwrpriv->lps_chk_cnt) + enter_ps = _FALSE; + else + enter_ps = _TRUE; + } + + if (1) { + RTW_INFO(FUNC_ADPT_FMT" tx_tp:%d [%d], rx_tp:%d [%d], bi_tp:%d [%d], enter_ps(%d):%s\n", + FUNC_ADPT_ARG(adapter), + tx_tp_mbits, pwrpriv->lps_tx_tp_th, + rx_tp_mbits, pwrpriv->lps_rx_tp_th, + bi_tp_mbits, pwrpriv->lps_bi_tp_th, + pwrpriv->lps_chk_cnt, + (enter_ps == _TRUE) ? "True" : "False"); + RTW_INFO(FUNC_ADPT_FMT" tx_pkt_cnt :%d [%d], rx_pkt_cnt :%d [%d]\n", + FUNC_ADPT_ARG(adapter), + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, + pwrpriv->lps_tx_pkts, + pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod, + pwrpriv->lps_rx_pkts); + if (!adapter->bsta_tp_dump) + RTW_INFO(FUNC_ADPT_FMT" bcn_cnt:%d (per-%d second)\n", + FUNC_ADPT_ARG(adapter), + rtw_get_bcn_cnt(psta->padapter), + 2); + } + + if (enter_ps) { + if (!from_timer) + LPS_Enter(adapter, "TRAFFIC_IDLE"); + } else { + if (!from_timer) + LPS_Leave(adapter, "TRAFFIC_BUSY"); + else { + #ifdef CONFIG_CONCURRENT_MODE + #ifndef CONFIG_FW_MULTI_PORT_SUPPORT + if (adapter->hw_port == HW_PORT0) + #endif + #endif + rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_TRAFFIC_BUSY, 1); + } + } + + return enter_ps; +} +#endif + +static u8 _lps_chk_by_pkt_cnts(_adapter *padapter, u8 from_timer, u8 bBusyTraffic) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 bEnterPS = _FALSE; + + /* check traffic for powersaving. */ + if (((pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) > 8) || + #ifdef CONFIG_LPS_SLOW_TRANSITION + (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 2) + #else /* CONFIG_LPS_SLOW_TRANSITION */ + (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4) + #endif /* CONFIG_LPS_SLOW_TRANSITION */ + ) { + #ifdef DBG_RX_COUNTER_DUMP + if (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA) + RTW_INFO("(-)Tx = %d, Rx = %d\n", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod); + #endif + + bEnterPS = _FALSE; + #ifdef CONFIG_LPS_SLOW_TRANSITION + if (bBusyTraffic == _TRUE) { + if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount <= 4) + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 4; + + pmlmepriv->LinkDetectInfo.TrafficTransitionCount++; + + /* RTW_INFO("Set TrafficTransitionCount to %d\n", pmlmepriv->LinkDetectInfo.TrafficTransitionCount); */ + + if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount > 30/*TrafficTransitionLevel*/) + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 30; + } + #endif /* CONFIG_LPS_SLOW_TRANSITION */ + } else { + #ifdef DBG_RX_COUNTER_DUMP + if (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA) + RTW_INFO("(+)Tx = %d, Rx = %d\n", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod); + #endif + + #ifdef CONFIG_LPS_SLOW_TRANSITION + if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount >= 2) + pmlmepriv->LinkDetectInfo.TrafficTransitionCount -= 2; + else + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; + + if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount == 0) + bEnterPS = _TRUE; + #else /* CONFIG_LPS_SLOW_TRANSITION */ + bEnterPS = _TRUE; + #endif /* CONFIG_LPS_SLOW_TRANSITION */ + } + + #ifdef CONFIG_DYNAMIC_DTIM + if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount == 8) + bEnterPS = _FALSE; + + RTW_INFO("LowPowerTransitionCount=%d\n", pmlmepriv->LinkDetectInfo.LowPowerTransitionCount); + #endif /* CONFIG_DYNAMIC_DTIM */ + + /* LeisurePS only work in infra mode. */ + if (bEnterPS) { + if (!from_timer) { + #ifdef CONFIG_DYNAMIC_DTIM + if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount < 8) + adapter_to_pwrctl(padapter)->dtim = 1; + else + adapter_to_pwrctl(padapter)->dtim = 3; + #endif /* CONFIG_DYNAMIC_DTIM */ + LPS_Enter(padapter, "TRAFFIC_IDLE"); + } else { + /* do this at caller */ + /* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 1); */ + /* rtw_hal_dm_watchdog_in_lps(padapter); */ + } + + #ifdef CONFIG_DYNAMIC_DTIM + if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++; + #endif /* CONFIG_DYNAMIC_DTIM */ + } else { + #ifdef CONFIG_DYNAMIC_DTIM + if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount != 8) + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; + else + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++; + #endif /* CONFIG_DYNAMIC_DTIM */ + + if (!from_timer) + LPS_Leave(padapter, "TRAFFIC_BUSY"); + else { + #ifdef CONFIG_CONCURRENT_MODE + #ifndef CONFIG_FW_MULTI_PORT_SUPPORT + if (padapter->hw_port == HW_PORT0) + #endif + #endif + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_TRAFFIC_BUSY, 1); + } + } + + return bEnterPS; +} +#endif /* CONFIG_LPS */ + +/* from_timer == 1 means driver is in LPS */ +u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) +{ + u8 bEnterPS = _FALSE; + u16 BusyThresholdHigh; + u16 BusyThresholdLow; + u16 BusyThreshold; + u8 bBusyTraffic = _FALSE, bTxBusyTraffic = _FALSE, bRxBusyTraffic = _FALSE; + u8 bHigherBusyTraffic = _FALSE, bHigherBusyRxTraffic = _FALSE, bHigherBusyTxTraffic = _FALSE; + + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); +#ifdef CONFIG_TDLS struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo); struct tdls_txmgmt txmgmt; u8 baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; #endif /* CONFIG_TDLS */ - +#ifdef CONFIG_TRAFFIC_PROTECT RT_LINK_DETECT_T *link_detect = &pmlmepriv->LinkDetectInfo; +#endif #ifdef CONFIG_BT_COEXIST if (padapter->registrypriv.wifi_spec != 1) { @@ -2502,111 +2741,20 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) } #endif /* CONFIG_TDLS_AUTOSETUP */ #endif /* CONFIG_TDLS */ - #ifdef CONFIG_LPS - /* check traffic for powersaving. */ - if (((pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) > 8) || -#ifdef CONFIG_LPS_SLOW_TRANSITION - (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 2) -#else /* CONFIG_LPS_SLOW_TRANSITION */ - (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4) -#endif /* CONFIG_LPS_SLOW_TRANSITION */ - ) { -#ifdef DBG_RX_COUNTER_DUMP - if (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA) - RTW_INFO("(-)Tx = %d, Rx = %d\n", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod); -#endif - bEnterPS = _FALSE; -#ifdef CONFIG_LPS_SLOW_TRANSITION - if (bBusyTraffic == _TRUE) { - if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount <= 4) - pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 4; - - pmlmepriv->LinkDetectInfo.TrafficTransitionCount++; - - /* RTW_INFO("Set TrafficTransitionCount to %d\n", pmlmepriv->LinkDetectInfo.TrafficTransitionCount); */ - - if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount > 30/*TrafficTransitionLevel*/) - pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 30; - } -#endif /* CONFIG_LPS_SLOW_TRANSITION */ - - } else { -#ifdef DBG_RX_COUNTER_DUMP - if (padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA) - RTW_INFO("(+)Tx = %d, Rx = %d\n", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod, pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod); -#endif -#ifdef CONFIG_LPS_SLOW_TRANSITION - if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount >= 2) - pmlmepriv->LinkDetectInfo.TrafficTransitionCount -= 2; - else - pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; - - if (pmlmepriv->LinkDetectInfo.TrafficTransitionCount == 0) - bEnterPS = _TRUE; -#else /* CONFIG_LPS_SLOW_TRANSITION */ - bEnterPS = _TRUE; -#endif /* CONFIG_LPS_SLOW_TRANSITION */ - } - -#ifdef CONFIG_DYNAMIC_DTIM - if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount == 8) - bEnterPS = _FALSE; - - RTW_INFO("LowPowerTransitionCount=%d\n", pmlmepriv->LinkDetectInfo.LowPowerTransitionCount); -#endif /* CONFIG_DYNAMIC_DTIM */ - - /* LeisurePS only work in infra mode. */ - if (bEnterPS) { - if (!from_timer) { -#ifdef CONFIG_DYNAMIC_DTIM - if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount < 8) - adapter_to_pwrctl(padapter)->dtim = 1; - else - adapter_to_pwrctl(padapter)->dtim = 3; -#endif /* CONFIG_DYNAMIC_DTIM */ - LPS_Enter(padapter, "TRAFFIC_IDLE"); - } else { - /* do this at caller */ - /* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 1); */ - /* rtw_hal_dm_watchdog_in_lps(padapter); */ - } -#ifdef CONFIG_DYNAMIC_DTIM - if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) - pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++; -#endif /* CONFIG_DYNAMIC_DTIM */ - } else { -#ifdef CONFIG_DYNAMIC_DTIM - if (pmlmepriv->LinkDetectInfo.LowPowerTransitionCount != 8) - pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; + if (adapter_to_pwrctl(padapter)->bLeisurePs && MLME_IS_STA(padapter)) { + #ifdef CONFIG_LPS_CHK_BY_TP + if (adapter_to_pwrctl(padapter)->lps_chk_by_tp) + bEnterPS = _lps_chk_by_tp(padapter, from_timer); else - pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++; -#endif /* CONFIG_DYNAMIC_DTIM */ - if (!from_timer) - LPS_Leave(padapter, "TRAFFIC_BUSY"); - else { -#ifdef CONFIG_CONCURRENT_MODE - #ifndef CONFIG_FW_MULTI_PORT_SUPPORT - if (padapter->hw_port == HW_PORT0) - #endif -#endif - rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_TRAFFIC_BUSY, 1); - } + #endif /*CONFIG_LPS_CHK_BY_TP*/ + bEnterPS = _lps_chk_by_pkt_cnts(padapter, from_timer, bBusyTraffic); } - #endif /* CONFIG_LPS */ + } else { #ifdef CONFIG_LPS - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - int n_assoc_iface = 0; - int i; - - for (i = 0; i < dvobj->iface_nums; i++) { - if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE)) - n_assoc_iface++; - } - - if (!from_timer && n_assoc_iface == 0) + if (!from_timer && rtw_mi_get_assoc_if_num(padapter) == 0) LPS_Leave(padapter, "NON_LINKED"); #endif } @@ -2643,6 +2791,9 @@ static void dynamic_update_bcn_check(_adapter *padapter) if (!padapter->registrypriv.wifi_spec) return; + if (!padapter->registrypriv.ht_enable || !is_supported_ht(padapter->registrypriv.wireless_mode)) + return; + if (!MLME_IS_AP(padapter)) return; @@ -2652,7 +2803,7 @@ static void dynamic_update_bcn_check(_adapter *padapter) if (count % 10 == 0) { count = 1; - +#ifdef CONFIG_80211N_HT if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc) && _FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht)) { @@ -2661,8 +2812,10 @@ static void dynamic_update_bcn_check(_adapter *padapter) update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); } } +#endif /* CONFIG_80211N_HT */ } +#ifdef CONFIG_80211N_HT /* In 2s, there are any legacy AP, update HT info, and then reset count */ if (_FALSE != ATOMIC_READ(&pmlmepriv->olbc) @@ -2677,18 +2830,21 @@ static void dynamic_update_bcn_check(_adapter *padapter) ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE); count = 0; } - +#endif /* CONFIG_80211N_HT */ count ++; } } void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter) { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK #ifdef CONFIG_AP_MODE - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { expire_timeout_chk(padapter); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter) && MLME_IS_ASOC(padapter)) + rtw_mesh_peer_status_chk(padapter); + #endif + } #endif #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ dynamic_update_bcn_check(padapter); @@ -2707,6 +2863,11 @@ void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter) #endif /* !RTW_BEAMFORMING_VERSION_2 */ #endif +#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR + rtw_cfgvendor_rssi_monitor_evt(padapter); +#endif + + } void rtw_dynamic_chk_wk_hdl(_adapter *padapter) { @@ -2742,6 +2903,7 @@ void rtw_dynamic_chk_wk_hdl(_adapter *padapter) rtw_hal_mcc_sw_status_check(padapter); #endif /* CONFIG_MCC_MODE */ + rtw_hal_periodic_tsf_update_chk(padapter); } #ifdef CONFIG_LPS @@ -2870,7 +3032,7 @@ u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue) void rtw_dm_in_lps_hdl(_adapter *padapter) { - rtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS, NULL); + rtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS_LCLK, NULL); } u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter) @@ -3141,11 +3303,6 @@ void reset_securitypriv_hdl(_adapter *padapter) rtw_reset_securitypriv(padapter); } -void free_assoc_resources_hdl(_adapter *padapter) -{ - rtw_free_assoc_resources(padapter, 1); -} - #ifdef CONFIG_P2P u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType) { @@ -3283,9 +3440,84 @@ inline u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev { return _p2p_roch_cmd(adapter, cookie, wdev, NULL, 0, 0, flags); } + #endif /* CONFIG_IOCTL_CFG80211 */ #endif /* CONFIG_P2P */ +#ifdef CONFIG_IOCTL_CFG80211 +inline u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct mgnt_tx_parm *mgnt_parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + mgnt_parm = (struct mgnt_tx_parm *)rtw_zmalloc(sizeof(struct mgnt_tx_parm)); + if (mgnt_parm == NULL) { + res = _FAIL; + goto exit; + } + + mgnt_parm->tx_ch = tx_ch; + mgnt_parm->no_cck = no_cck; + mgnt_parm->buf = buf; + mgnt_parm->len = len; + mgnt_parm->wait_ack = wait_ack; + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != rtw_mgnt_tx_handler(adapter, (u8 *)mgnt_parm)) + res = _FAIL; + rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); + res = _FAIL; + goto exit; + } + + parm->ec_id = MGNT_TX_WK_CID; + parm->type = 0; + parm->size = sizeof(*mgnt_parm); + parm->pbuf = (u8 *)mgnt_parm; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm)); + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 10 * 1000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status != RTW_SCTX_DONE_SUCCESS) + res = _FAIL; + } + } + +exit: + return res; +} +#endif + u8 rtw_ps_cmd(_adapter *padapter) { struct cmd_obj *ppscmd; @@ -3295,7 +3527,7 @@ u8 rtw_ps_cmd(_adapter *padapter) u8 res = _SUCCESS; #ifdef CONFIG_CONCURRENT_MODE - if (padapter->adapter_type != PRIMARY_ADAPTER) + if (!is_primary_adapter(padapter)) goto exit; #endif @@ -3327,13 +3559,103 @@ u8 rtw_ps_cmd(_adapter *padapter) } +#ifdef CONFIG_DFS +void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj) +{ + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + _adapter *pri_adapter = dvobj_get_primary_adapter(dvobj); + u8 ifbmp_m = rtw_mi_get_ap_mesh_ifbmp(pri_adapter); + u8 ifbmp_s = rtw_mi_get_ld_sta_ifbmp(pri_adapter); + s16 req_ch; + + rtw_hal_macid_sleep_all_used(pri_adapter); + + if (rtw_chset_search_ch(rfctl->channel_set, rfctl->csa_ch) >= 0 + && !rtw_chset_is_ch_non_ocp(rfctl->channel_set, rfctl->csa_ch) + ) { + /* CSA channel available and valid */ + req_ch = rfctl->csa_ch; + RTW_INFO("%s valid CSA ch%u\n", __func__, rfctl->csa_ch); + } else if (ifbmp_m) { + /* no available or valid CSA channel, having AP/MESH ifaces */ + req_ch = REQ_CH_NONE; + RTW_INFO("%s ch sel by AP/MESH ifaces\n", __func__); + } else { + /* no available or valid CSA channel and no AP/MESH ifaces */ + if (!IsSupported24G(dvobj_to_regsty(dvobj)->wireless_mode) + #ifdef CONFIG_DFS_MASTER + || rfctl->radar_detected + #endif + ) + req_ch = 36; + else + req_ch = 1; + RTW_INFO("%s switch to ch%d\n", __func__, req_ch); + } + + /* issue deauth for all asoc STA ifaces */ + if (ifbmp_s) { + _adapter *iface; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface || !(ifbmp_s & BIT(iface->iface_id))) + continue; + set_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING); + + /* TODO: true op ch switching */ + issue_deauth(iface, get_bssid(&iface->mlmepriv), WLAN_REASON_DEAUTH_LEAVING); + } + } + +#ifdef CONFIG_AP_MODE + if (ifbmp_m) { + /* trigger channel selection without consideraton of asoc STA ifaces */ + rtw_change_bss_chbw_cmd(dvobj_get_primary_adapter(dvobj), RTW_CMDF_DIRECTLY + , ifbmp_m, ifbmp_s, req_ch, REQ_BW_ORI, REQ_OFFSET_NONE); + } else +#endif + { + /* no AP/MESH iface, switch DFS status and channel directly */ + rtw_warn_on(req_ch <= 0); + #ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(pri_adapter, MLME_OPCH_SWITCH, ifbmp_s); + #endif + set_channel_bwmode(pri_adapter, req_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } + + /* make asoc STA ifaces disconnect */ + /* TODO: true op ch switching */ + if (ifbmp_s) { + _adapter *iface; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface || !(ifbmp_s & BIT(iface->iface_id))) + continue; + rtw_disassoc_cmd(iface, 0, RTW_CMDF_DIRECTLY); + rtw_indicate_disconnect(iface, 0, _FALSE); + rtw_free_assoc_resources(iface, _TRUE); + rtw_free_network_queue(iface, _TRUE); + } + } + + rfctl->csa_ch = 0; + + rtw_hal_macid_wakeup_all_used(pri_adapter); + rtw_mi_os_xmit_schedule(pri_adapter); +} +#endif /* CONFIG_DFS */ + #ifdef CONFIG_AP_MODE static void rtw_chk_hi_queue_hdl(_adapter *padapter) { struct sta_info *psta_bmc; struct sta_priv *pstapriv = &padapter->stapriv; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); u8 empty = _FALSE; psta_bmc = rtw_get_bcmc_stainfo(padapter); @@ -3351,11 +3673,11 @@ static void rtw_chk_hi_queue_hdl(_adapter *padapter) if (empty == _SUCCESS) { bool update_tim = _FALSE; - if (pstapriv->tim_bitmap & BIT(0)) + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) update_tim = _TRUE; - pstapriv->tim_bitmap &= ~BIT(0); - pstapriv->sta_dz_bitmap &= ~BIT(0); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0); + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0); if (update_tim == _TRUE) _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "bmc sleepq and HIQ empty"); @@ -3402,18 +3724,18 @@ u8 rtw_chk_hi_queue_cmd(_adapter *padapter) } #ifdef CONFIG_DFS_MASTER -u8 rtw_dfs_master_hdl(_adapter *adapter) +u8 rtw_dfs_rd_hdl(_adapter *adapter) { + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - struct mlme_priv *mlme = &adapter->mlmepriv; - if (!rfctl->dfs_master_enabled) + if (!rfctl->radar_detect_enabled) goto exit; - if (rtw_get_on_cur_ch_time(adapter) == 0 - || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 300 + if (dvobj->oper_channel != rfctl->radar_detect_ch + || rtw_get_passing_time_ms(rtw_get_on_oper_ch_time(adapter)) < 300 ) { - /* offchannel , bypass radar detect */ + /* offchannel, bypass radar detect */ goto cac_status_chk; } @@ -3422,98 +3744,102 @@ u8 rtw_dfs_master_hdl(_adapter *adapter) goto cac_status_chk; } - if (!rfctl->dbg_dfs_master_fake_radar_detect_cnt + if (!rfctl->dbg_dfs_fake_radar_detect_cnt && rtw_odm_radar_detect(adapter) != _TRUE) goto cac_status_chk; - if (rfctl->dbg_dfs_master_fake_radar_detect_cnt != 0) { - RTW_INFO(FUNC_ADPT_FMT" fake radar detect, cnt:%d\n", FUNC_ADPT_ARG(adapter) - , rfctl->dbg_dfs_master_fake_radar_detect_cnt); - rfctl->dbg_dfs_master_fake_radar_detect_cnt--; + if (!rfctl->dbg_dfs_fake_radar_detect_cnt + && rfctl->dbg_dfs_radar_detect_trigger_non + ) { + /* radar detect debug mode, trigger no mlme flow */ + RTW_INFO("%s radar detected on test mode, trigger no mlme flow\n", __func__); + goto cac_status_chk; } - if (rfctl->dbg_dfs_master_radar_detect_trigger_non) { - /* radar detect debug mode, trigger no mlme flow */ - if (0) - RTW_INFO(FUNC_ADPT_FMT" radar detected, trigger no mlme flow for debug\n", FUNC_ADPT_ARG(adapter)); - } else { - /* TODO: move timer to rfctl */ - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - int i; + if (rfctl->dbg_dfs_fake_radar_detect_cnt != 0) { + RTW_INFO("%s fake radar detected, cnt:%d\n", __func__ + , rfctl->dbg_dfs_fake_radar_detect_cnt); + rfctl->dbg_dfs_fake_radar_detect_cnt--; + } else + RTW_INFO("%s radar detected\n", __func__); - for (i = 0; i < dvobj->iface_nums; i++) { - if (!dvobj->padapters[i]) - continue; - if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE) - && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE)) - break; - } + rfctl->radar_detected = 1; - if (i >= dvobj->iface_nums) { - /* what? */ - rtw_warn_on(1); - } else { - rtw_chset_update_non_ocp(dvobj->padapters[i]->mlmeextpriv.channel_set - , rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset); - rfctl->radar_detected = 1; + rtw_chset_update_non_ocp(rfctl->channel_set + , rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset); - /* trigger channel selection */ - rtw_change_bss_chbw_cmd(dvobj->padapters[i], RTW_CMDF_DIRECTLY, -1, dvobj->padapters[i]->mlmepriv.ori_bw, -1); - } + rtw_dfs_ch_switch_hdl(dvobj); - if (rfctl->dfs_master_enabled) - goto set_timer; - goto exit; - } + if (rfctl->radar_detect_enabled) + goto set_timer; + goto exit; cac_status_chk: - if (!IS_CH_WAITING(rfctl) && !IS_CAC_STOPPED(rfctl)) { + if (!IS_CAC_STOPPED(rfctl) + && ((IS_UNDER_CAC(rfctl) && rfctl->cac_force_stop) + || !IS_CH_WAITING(rfctl) + ) + ) { u8 pause = 0x00; rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause); rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED; if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) { + u8 doiqk = _TRUE; + u8 u_ch, u_bw, u_offset; + + rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk); + + if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) + set_channel_bwmode(adapter, u_ch, u_offset, u_bw); + else + rtw_warn_on(1); + + doiqk = _FALSE; + rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk); + ResumeTxBeacon(adapter); rtw_mi_tx_beacon_hdl(adapter); } } set_timer: - _set_timer(&mlme->dfs_master_timer, DFS_MASTER_TIMER_MS); + _set_timer(&rfctl->radar_detect_timer + , rtw_odm_radar_detect_polling_int_ms(dvobj)); exit: return H2C_SUCCESS; } -u8 rtw_dfs_master_cmd(_adapter *adapter, bool enqueue) +u8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue) { struct cmd_obj *cmdobj; - struct drvextra_cmd_parm *pdrvextra_cmd_parm; - struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct drvextra_cmd_parm *parm; + struct cmd_priv *cmdpriv = &adapter->cmdpriv; u8 res = _FAIL; if (enqueue) { - cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + cmdobj = rtw_zmalloc(sizeof(struct cmd_obj)); if (cmdobj == NULL) goto exit; - pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); - if (pdrvextra_cmd_parm == NULL) { - rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + parm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + rtw_mfree(cmdobj, sizeof(struct cmd_obj)); goto exit; } - pdrvextra_cmd_parm->ec_id = DFS_MASTER_WK_CID; - pdrvextra_cmd_parm->type = 0; - pdrvextra_cmd_parm->size = 0; - pdrvextra_cmd_parm->pbuf = NULL; + parm->ec_id = DFS_RADAR_DETECT_WK_CID; + parm->type = 0; + parm->size = 0; + parm->pbuf = NULL; - init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); - res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + res = rtw_enqueue_cmd(cmdpriv, cmdobj); } else { - rtw_dfs_master_hdl(adapter); + rtw_dfs_rd_hdl(adapter); res = _SUCCESS; } @@ -3521,24 +3847,25 @@ u8 rtw_dfs_master_cmd(_adapter *adapter, bool enqueue) return res; } -void rtw_dfs_master_timer_hdl(void *ctx) +void rtw_dfs_rd_timer_hdl(void *ctx) { - _adapter *adapter = (_adapter *)ctx; + struct rf_ctl_t *rfctl = (struct rf_ctl_t *)ctx; + struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); - rtw_dfs_master_cmd(adapter, _TRUE); + rtw_dfs_rd_cmd(dvobj_get_primary_adapter(dvobj), _TRUE); } -void rtw_dfs_master_enable(_adapter *adapter, u8 ch, u8 bw, u8 offset) +static void rtw_dfs_rd_enable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool bypass_cac) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - - /* TODO: move timer to rfctl */ - adapter = GET_PRIMARY_ADAPTER(adapter); + struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); + _adapter *adapter = dvobj_get_primary_adapter(dvobj); - RTW_INFO(FUNC_ADPT_FMT" on %u,%u,%u\n", FUNC_ADPT_ARG(adapter), ch, bw, offset); + RTW_INFO("%s on %u,%u,%u\n", __func__, ch, bw, offset); - if (rtw_is_cac_reset_needed(adapter, ch, bw, offset) == _TRUE) - rtw_reset_cac(adapter, ch, bw, offset); + if (bypass_cac) + rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED; + else if (rtw_is_cac_reset_needed(rfctl, ch, bw, offset) == _TRUE) + rtw_reset_cac(rfctl, ch, bw, offset); rfctl->radar_detect_by_others = _FALSE; rfctl->radar_detect_ch = ch; @@ -3550,10 +3877,14 @@ void rtw_dfs_master_enable(_adapter *adapter, u8 ch, u8 bw, u8 offset) if (IS_CH_WAITING(rfctl)) StopTxBeacon(adapter); - if (!rfctl->dfs_master_enabled) { - RTW_INFO(FUNC_ADPT_FMT" set dfs_master_enabled\n", FUNC_ADPT_ARG(adapter)); - rfctl->dfs_master_enabled = 1; - _set_timer(&adapter->mlmepriv.dfs_master_timer, DFS_MASTER_TIMER_MS); + if (!rfctl->radar_detect_enabled) { + RTW_INFO("%s set radar_detect_enabled\n", __func__); + rfctl->radar_detect_enabled = 1; + #ifdef CONFIG_LPS + LPS_Leave(adapter, "RADAR_DETECT_EN"); + #endif + _set_timer(&rfctl->radar_detect_timer + , rtw_odm_radar_detect_polling_int_ms(dvobj)); if (rtw_rfctl_overlap_radar_detect_ch(rfctl)) { if (IS_CH_WAITING(rfctl)) { @@ -3566,27 +3897,24 @@ void rtw_dfs_master_enable(_adapter *adapter, u8 ch, u8 bw, u8 offset) } } -void rtw_dfs_master_disable(_adapter *adapter, u8 ch, u8 bw, u8 offset, bool by_others) +static void rtw_dfs_rd_disable(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool by_others) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - - /* TODO: move timer to rfctl */ - adapter = GET_PRIMARY_ADAPTER(adapter); + _adapter *adapter = dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl)); rfctl->radar_detect_by_others = by_others; - if (rfctl->dfs_master_enabled) { + if (rfctl->radar_detect_enabled) { bool overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl); - RTW_INFO(FUNC_ADPT_FMT" clear dfs_master_enabled\n", FUNC_ADPT_ARG(adapter)); + RTW_INFO("%s clear radar_detect_enabled\n", __func__); - rfctl->dfs_master_enabled = 0; + rfctl->radar_detect_enabled = 0; rfctl->radar_detected = 0; rfctl->radar_detect_ch = 0; rfctl->radar_detect_bw = 0; rfctl->radar_detect_offset = 0; rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED; - _cancel_timer_ex(&adapter->mlmepriv.dfs_master_timer); + _cancel_timer_ex(&rfctl->radar_detect_timer); if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) { ResumeTxBeacon(adapter); @@ -3608,65 +3936,97 @@ void rtw_dfs_master_disable(_adapter *adapter, u8 ch, u8 bw, u8 offset, bool by_ } } -void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action) +void rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp) { + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; struct mi_state mstate; + u8 ifbmp; u8 u_ch, u_bw, u_offset; bool ld_sta_in_dfs = _FALSE; bool sync_ch = _FALSE; /* _FALSE: asign channel directly */ bool needed = _FALSE; - rtw_mi_status_no_self(adapter, &mstate); - rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset); - if (u_ch != 0) - sync_ch = _TRUE; + if (mlme_act == MLME_OPCH_SWITCH + || mlme_act == MLME_ACTION_NONE + ) { + ifbmp = ~excl_ifbmp; + rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate); + rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp, &u_ch, &u_bw, &u_offset); + } else { + ifbmp = ~excl_ifbmp & ~BIT(adapter->iface_id); + rtw_mi_status_by_ifbmp(dvobj, ifbmp, &mstate); + rtw_mi_get_ch_setting_union_by_ifbmp(dvobj, ifbmp, &u_ch, &u_bw, &u_offset); + if (u_ch != 0) + sync_ch = _TRUE; + + switch (mlme_act) { + case MLME_STA_CONNECTING: + MSTATE_STA_LG_NUM(&mstate)++; + break; + case MLME_STA_CONNECTED: + MSTATE_STA_LD_NUM(&mstate)++; + break; + case MLME_STA_DISCONNECTED: + break; +#ifdef CONFIG_AP_MODE + case MLME_AP_STARTED: + MSTATE_AP_NUM(&mstate)++; + break; + case MLME_AP_STOPPED: + break; +#endif +#ifdef CONFIG_RTW_MESH + case MLME_MESH_STARTED: + MSTATE_MESH_NUM(&mstate)++; + break; + case MLME_MESH_STOPPED: + break; +#endif + default: + rtw_warn_on(1); + break; + } - switch (self_action) { - case MLME_STA_CONNECTING: - MSTATE_STA_LG_NUM(&mstate)++; - break; - case MLME_STA_CONNECTED: - MSTATE_STA_LD_NUM(&mstate)++; - break; - case MLME_AP_STARTED: - MSTATE_AP_NUM(&mstate)++; - break; - case MLME_AP_STOPPED: - case MLME_STA_DISCONNECTED: - default: - break; - } + if (sync_ch == _TRUE) { + if (!MLME_IS_OPCH_SW(adapter)) { + if (!rtw_is_chbw_grouped(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset)) { + RTW_INFO(FUNC_ADPT_FMT" can't sync %u,%u,%u with %u,%u,%u\n", FUNC_ADPT_ARG(adapter) + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset); + goto apply; + } - if (sync_ch == _TRUE) { - if (!rtw_is_chbw_grouped(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset)) { - RTW_INFO(FUNC_ADPT_FMT" can't sync %u,%u,%u with %u,%u,%u\n", FUNC_ADPT_ARG(adapter) - , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset); - goto apply; + rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset + , &u_ch, &u_bw, &u_offset); + } + } else { + u_ch = mlmeext->cur_channel; + u_bw = mlmeext->cur_bwmode; + u_offset = mlmeext->cur_ch_offset; } - - rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset - , &u_ch, &u_bw, &u_offset); - } else { - u_ch = mlmeext->cur_channel; - u_bw = mlmeext->cur_bwmode; - u_offset = mlmeext->cur_ch_offset; } - if (MSTATE_STA_LD_NUM(&mstate) > 0) { - /* rely on AP on which STA mode connects */ - if (rtw_is_dfs_chbw(u_ch, u_bw, u_offset)) - ld_sta_in_dfs = _TRUE; + if (MSTATE_STA_LG_NUM(&mstate) > 0) { + /* STA mode is linking */ goto apply; } - if (MSTATE_STA_LG_NUM(&mstate) > 0) { - /* STA mode is linking */ + if (MSTATE_STA_LD_NUM(&mstate) > 0) { + if (rtw_is_dfs_chbw(u_ch, u_bw, u_offset)) { + /* + * if operate as slave w/o radar detect, + * rely on AP on which STA mode connects + */ + if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_odm_dfs_domain_unknown(dvobj)) + needed = _TRUE; + ld_sta_in_dfs = _TRUE; + } goto apply; } - if (MSTATE_AP_NUM(&mstate) == 0) { - /* No working AP mode */ + if (!MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) { + /* No working AP/Mesh mode */ goto apply; } @@ -3675,16 +4035,46 @@ void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action) apply: - RTW_INFO(FUNC_ADPT_FMT" needed:%d, self_action:%u\n" - , FUNC_ADPT_ARG(adapter), needed, self_action); - RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, %u,%u,%u\n" - , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate), MSTATE_AP_NUM(&mstate) + RTW_INFO(FUNC_ADPT_FMT" needed:%d, mlme_act:%u, excl_ifbmp:0x%02x\n" + , FUNC_ADPT_ARG(adapter), needed, mlme_act, excl_ifbmp); + RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u, %u,%u,%u\n" + , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate) + , MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate) , u_ch, u_bw, u_offset); if (needed == _TRUE) - rtw_dfs_master_enable(adapter, u_ch, u_bw, u_offset); + rtw_dfs_rd_enable(rfctl, u_ch, u_bw, u_offset, ld_sta_in_dfs); else - rtw_dfs_master_disable(adapter, u_ch, u_bw, u_offset, ld_sta_in_dfs); + rtw_dfs_rd_disable(rfctl, u_ch, u_bw, u_offset, ld_sta_in_dfs); +} + +u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct cmd_priv *cmdpriv = &adapter->cmdpriv; + u8 res = _FAIL; + + cmdobj = rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) + goto exit; + + parm = rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + rtw_mfree(cmdobj, sizeof(struct cmd_obj)); + goto exit; + } + + parm->ec_id = DFS_RADAR_DETECT_EN_DEC_WK_CID; + parm->type = 0; + parm->size = 0; + parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + res = rtw_enqueue_cmd(cmdpriv, cmdobj); + +exit: + return res; } #endif /* CONFIG_DFS_MASTER */ @@ -3887,23 +4277,48 @@ u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len) return res; } +#ifdef CONFIG_MP_INCLUDED static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); int ret = H2C_SUCCESS; - u8 rfreg0; + uint status = _SUCCESS; if (mp_cmd_id == MP_START) { if (padapter->registrypriv.mp_mode == 0) { + rtw_intf_stop(padapter); rtw_hal_deinit(padapter); padapter->registrypriv.mp_mode = 1; +#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1) + padapter->mppriv.CureFuseBTCoex = pHalData->EEPROMBluetoothCoexist; + pHalData->EEPROMBluetoothCoexist = _FALSE; +#endif #ifdef CONFIG_RF_POWER_TRIM if (!IS_HARDWARE_TYPE_8814A(padapter) && !IS_HARDWARE_TYPE_8822B(padapter)) { padapter->registrypriv.RegPwrTrimEnable = 1; rtw_hal_read_chip_info(padapter); } #endif /*CONFIG_RF_POWER_TRIM*/ - rtw_hal_init(padapter); + rtw_reset_drv_sw(padapter); +#ifdef CONFIG_NEW_NETDEV_HDL + if (!rtw_is_hw_init_completed(padapter)) { + status = rtw_hal_init(padapter); + if (status == _FAIL) { + ret = H2C_REJECTED; + goto exit; + } + rtw_hal_iface_init(padapter); + } +#else + status = rtw_hal_init(padapter); + if (status == _FAIL) { + ret = H2C_REJECTED; + goto exit; + } +#endif /*CONFIG_NEW_NETDEV_HDL*/ +#ifndef RTW_HALMAC + rtw_intf_start(padapter); +#endif /* !RTW_HALMAC */ #ifdef RTW_HALMAC /*for New IC*/ MPT_InitializeAdapter(padapter, 1); #endif /* CONFIG_MP_INCLUDED */ @@ -3938,27 +4353,37 @@ static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id) rtw_write8(padapter, 0x66, 0x27); /*Open BT uart Log*/ rtw_write8(padapter, 0xc50, 0x20); /*for RX init Gain*/ #endif -#ifdef CONFIG_RTL8188F - RTW_INFO("Set reg 0x88c, 0x58, 0x00\n"); - rfreg0 = phy_query_rf_reg(padapter, RF_PATH_A, 0x0, 0x1f); - phy_set_bb_reg(padapter, 0x88c, BIT21|BIT20, 0x3); - phy_set_rf_reg(padapter, RF_PATH_A, 0x58, BIT1, 0x1); - phy_set_rf_reg(padapter, RF_PATH_A, 0x0, 0xF001f, 0x2001f); - rtw_msleep_os(200); - phy_set_rf_reg(padapter, RF_PATH_A, 0x0, 0xF001f, 0x30000 | rfreg0); - phy_set_rf_reg(padapter, RF_PATH_A, 0x58, BIT1, 0x0); - phy_set_bb_reg(padapter, 0x88c, BIT21|BIT20, 0x0); - rtw_msleep_os(1000); -#endif - odm_write_dig(&pHalData->odmpriv, 0x20); } else if (mp_cmd_id == MP_STOP) { if (padapter->registrypriv.mp_mode == 1) { MPT_DeInitAdapter(padapter); + rtw_intf_stop(padapter); rtw_hal_deinit(padapter); padapter->registrypriv.mp_mode = 0; - rtw_hal_init(padapter); +#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1) + pHalData->EEPROMBluetoothCoexist = padapter->mppriv.CureFuseBTCoex; +#endif + rtw_reset_drv_sw(padapter); +#ifdef CONFIG_NEW_NETDEV_HDL + if (!rtw_is_hw_init_completed(padapter)) { + status = rtw_hal_init(padapter); + if (status == _FAIL) { + ret = H2C_REJECTED; + goto exit; + } + rtw_hal_iface_init(padapter); + } +#else + status = rtw_hal_init(padapter); + if (status == _FAIL) { + ret = H2C_REJECTED; + goto exit; + } +#endif /*CONFIG_NEW_NETDEV_HDL*/ +#ifndef RTW_HALMAC + rtw_intf_start(padapter); +#endif /* !RTW_HALMAC */ } if (padapter->mppriv.mode != MP_OFF) { @@ -4032,6 +4457,7 @@ u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags) exit: return res; } +#endif /*CONFIG_MP_INCLUDED*/ #ifdef CONFIG_RTW_CUSTOMER_STR static s32 rtw_customer_str_cmd_hdl(_adapter *adapter, u8 write, const u8 *cstr) @@ -4516,6 +4942,69 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm) return; } +#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW) +static s32 rtw_req_per_cmd_hdl(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct macid_bmp req_macid_bmp, *macid_bmp; + u8 i, ret = _FAIL; + + macid_bmp = &macid_ctl->if_g[adapter->iface_id]; + _rtw_memcpy(&req_macid_bmp, macid_bmp, sizeof(struct macid_bmp)); + + /* Clear none mesh's macid */ + for (i = 0; i < macid_ctl->num; i++) { + u8 role; + role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]); + if (role != H2C_MSR_ROLE_MESH) + rtw_macid_map_clr(&req_macid_bmp, i); + } + + /* group_macid: always be 0 in NIC, so only pass macid_bitmap.m0 + * rpt_type: 0 includes all info in 1, use 0 for now + * macid_bitmap: pass m0 only for NIC + */ + ret = rtw_hal_set_req_per_rpt_cmd(adapter, 0, 0, req_macid_bmp.m0); + + return ret; +} + +u8 rtw_req_per_cmd(_adapter *adapter) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + res = _FAIL; + goto exit; + } + + parm->ec_id = REQ_PER_CMD_WK_CID; + parm->type = 0; + parm->size = 0; + parm->pbuf = NULL; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + +exit: + return res; +} +#endif + u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) { int ret = H2C_SUCCESS; @@ -4587,7 +5076,7 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) reset_securitypriv_hdl(padapter); break; case FREE_ASSOC_RESOURCES: - free_assoc_resources_hdl(padapter); + free_assoc_resources_hdl(padapter, (u8)pdrvextra_cmd->type); break; case C2H_WK_CID: switch (pdrvextra_cmd->type) { @@ -4621,8 +5110,11 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) break; #endif #ifdef CONFIG_DFS_MASTER - case DFS_MASTER_WK_CID: - rtw_dfs_master_hdl(padapter); + case DFS_RADAR_DETECT_WK_CID: + rtw_dfs_rd_hdl(padapter); + break; + case DFS_RADAR_DETECT_EN_DEC_WK_CID: + rtw_dfs_rd_en_decision(padapter, MLME_ACTION_NONE, 0); break; #endif case SESSION_TRACKER_WK_CID: @@ -4631,17 +5123,44 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) case EN_HW_UPDATE_TSF_WK_CID: rtw_hal_set_hwreg(padapter, HW_VAR_EN_HW_UPDATE_TSF, NULL); break; + case PERIOD_TSF_UPDATE_END_WK_CID: + rtw_hal_periodic_tsf_update_chk(padapter); + break; case TEST_H2C_CID: rtw_hal_fill_h2c_cmd(padapter, pdrvextra_cmd->pbuf[0], pdrvextra_cmd->size - 1, &pdrvextra_cmd->pbuf[1]); break; case MP_CMD_WK_CID: +#ifdef CONFIG_MP_INCLUDED ret = rtw_mp_cmd_hdl(padapter, pdrvextra_cmd->type); +#endif break; #ifdef CONFIG_RTW_CUSTOMER_STR case CUSTOMER_STR_WK_CID: ret = rtw_customer_str_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); break; #endif + +#ifdef CONFIG_RTW_REPEATER_SON + case RSON_SCAN_WK_CID: + rtw_rson_scan_cmd_hdl(padapter, pdrvextra_cmd->type); + break; +#endif + +#ifdef CONFIG_IOCTL_CFG80211 + case MGNT_TX_WK_CID: + ret = rtw_mgnt_tx_handler(padapter, pdrvextra_cmd->pbuf); + break; +#endif /* CONFIG_IOCTL_CFG80211 */ +#ifdef CONFIG_MCC_MODE + case MCC_SET_DURATION_WK_CID: + ret = rtw_set_mcc_duration_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); + break; +#endif /* CONFIG_MCC_MODE */ +#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW) + case REQ_PER_CMD_WK_CID: + ret = rtw_req_per_cmd_hdl(padapter); + break; +#endif default: break; } @@ -4721,7 +5240,6 @@ void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) void rtw_create_ibss_post_hdl(_adapter *padapter, int status) { _irqL irqL; - struct sta_info *psta = NULL; struct wlan_network *pwlan = NULL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network; @@ -4768,7 +5286,6 @@ void rtw_create_ibss_post_hdl(_adapter *padapter, int status) createbss_cmd_fail: _exit_critical_bh(&pmlmepriv->lock, &irqL); -exit: return; } @@ -4786,7 +5303,7 @@ void rtw_setstaKey_cmdrsp_callback(_adapter *padapter , struct cmd_obj *pcmd) goto exit; } - /* psta->aid = psta->mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */ + /* psta->cmn.aid = psta->cmn.mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */ exit: @@ -4808,7 +5325,7 @@ void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) goto exit; } - psta->aid = psta->mac_id = passocsta_rsp->cam_id; + psta->cmn.aid = psta->cmn.mac_id = passocsta_rsp->cam_id; _enter_critical_bh(&pmlmepriv->lock, &irqL); diff --git a/core/rtw_debug.c b/core/rtw_debug.c index 46bbf2f..e43b665 100644 --- a/core/rtw_debug.c +++ b/core/rtw_debug.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_DEBUG_C_ #include @@ -65,6 +60,9 @@ void dump_drv_cfg(void *sel) #ifdef RTW_USE_CFG80211_STA_EVENT RTW_PRINT_SEL(sel, "RTW_USE_CFG80211_STA_EVENT\n"); #endif + #ifdef CONFIG_RADIO_WORK + RTW_PRINT_SEL(sel, "CONFIG_RADIO_WORK\n"); + #endif #else RTW_PRINT_SEL(sel, "WEXT\n"); #endif @@ -131,6 +129,14 @@ void dump_drv_cfg(void *sel) RTW_PRINT_SEL(sel, "CONFIG_RTW_80211R\n"); #endif +#ifdef CONFIG_RTW_NETIF_SG + RTW_PRINT_SEL(sel, "CONFIG_RTW_NETIF_SG\n"); +#endif + +#ifdef CONFIG_RTW_WIFI_HAL + RTW_PRINT_SEL(sel, "CONFIG_RTW_WIFI_HAL\n"); +#endif + #ifdef CONFIG_USB_HCI #ifdef CONFIG_SUPPORT_USB_INT RTW_PRINT_SEL(sel, "CONFIG_SUPPORT_USB_INT\n"); @@ -170,6 +176,21 @@ void dump_drv_cfg(void *sel) #ifdef CONFIG_PCI_HCI #endif + RTW_PRINT_SEL(sel, "CONFIG_IFACE_NUMBER = %d\n", CONFIG_IFACE_NUMBER); +#ifdef CONFIG_MI_WITH_MBSSID_CAM + RTW_PRINT_SEL(sel, "CONFIG_MI_WITH_MBSSID_CAM\n"); +#endif +#ifdef CONFIG_SWTIMER_BASED_TXBCN + RTW_PRINT_SEL(sel, "CONFIG_SWTIMER_BASED_TXBCN\n"); +#endif +#ifdef CONFIG_FW_HANDLE_TXBCN + RTW_PRINT_SEL(sel, "CONFIG_FW_HANDLE_TXBCN\n"); + RTW_PRINT_SEL(sel, "CONFIG_LIMITED_AP_NUM = %d\n", CONFIG_LIMITED_AP_NUM); +#endif +#ifdef CONFIG_CLIENT_PORT_CFG + RTW_PRINT_SEL(sel, "CONFIG_CLIENT_PORT_CFG\n"); +#endif + RTW_PRINT_SEL(sel, "\n=== XMIT-INFO ===\n"); RTW_PRINT_SEL(sel, "NR_XMITFRAME = %d\n", NR_XMITFRAME); RTW_PRINT_SEL(sel, "NR_XMITBUFF = %d\n", NR_XMITBUFF); @@ -260,7 +281,7 @@ void mac_reg_dump(void *sel, _adapter *adapter) #endif /* CONFIG_RTL8814A */ -#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) +#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) ||defined(CONFIG_RTL8192F) for (i = 0x1000; i < 0x1800; i += 4) { if (j % 4 == 1) RTW_PRINT_SEL(sel, "0x%04x", i); @@ -268,7 +289,8 @@ void mac_reg_dump(void *sel, _adapter *adapter) if ((j++) % 4 == 0) _RTW_PRINT_SEL(sel, "\n"); } -#endif /* CONFIG_RTL8822B */ +#endif /* CONFIG_RTL8822B or 8821c or 8192f*/ + } void bb_reg_dump(void *sel, _adapter *adapter) @@ -297,7 +319,7 @@ void bb_reg_dump(void *sel, _adapter *adapter) void bb_reg_dump_ex(void *sel, _adapter *adapter) { - int i, j = 1; + int i; RTW_PRINT_SEL(sel, "======= BB REG =======\n"); for (i = 0x800; i < 0x1000; i += 4) { @@ -343,13 +365,13 @@ void rf_reg_dump(void *sel, _adapter *adapter) } } -void rtw_sink_rtp_seq_dbg(_adapter *adapter, _pkt *pkt) +void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos) { struct recv_priv *precvpriv = &(adapter->recvpriv); if (precvpriv->sink_udpport > 0) { - if (*((u16 *)((pkt->data) + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) { + if (*((u16 *)(ehdr_pos + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) { precvpriv->pre_rtp_rxseq = precvpriv->cur_rtp_rxseq; - precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)((pkt->data) + 0x2C))); + precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)(ehdr_pos + 0x2C))); if (precvpriv->pre_rtp_rxseq + 1 != precvpriv->cur_rtp_rxseq) RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq); } @@ -416,11 +438,25 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) int i; _adapter *iface; u8 u_ch, u_bw, u_offset; - +#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG) + char str_val[64] = {'\0'}; +#endif dump_mi_status(sel, dvobj); +#if defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN) + RTW_PRINT_SEL(sel, "[AP] LIMITED_AP_NUM:%d\n", CONFIG_LIMITED_AP_NUM); + RTW_PRINT_SEL(sel, "[AP] vap_map:0x%02x\n", dvobj->vap_map); +#endif +#ifdef CONFIG_HW_P0_TSF_SYNC + RTW_PRINT_SEL(sel, "[AP] p0 tsf sync port = %d\n", dvobj->p0_tsf.sync_port); + RTW_PRINT_SEL(sel, "[AP] p0 tsf timer offset = %d\n", dvobj->p0_tsf.offset); +#endif +#ifdef CONFIG_CLIENT_PORT_CFG + RTW_PRINT_SEL(sel, "[CLT] clt_num = %d\n", dvobj->clt_port.num); + RTW_PRINT_SEL(sel, "[CLT] clt_map = 0x%02x\n", dvobj->clt_port.bmp); +#endif #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - RTW_PRINT_SEL(sel, "default port id:%d\n\n", dvobj->default_port_id); + RTW_PRINT_SEL(sel, "[MI] default port id:%d\n\n", dvobj->dft.port_id); #endif /* CONFIG_FW_MULTI_PORT_SUPPORT */ RTW_PRINT_SEL(sel, "dev status:%s%s\n\n" @@ -445,14 +481,40 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) #define P2P_INFO_VALUE_FMT "" #define P2P_INFO_VALUE_ARG #define P2P_INFO_DASH +#endif + +#ifdef DBG_TSF_UPDATE +#define TSF_PAUSE_TIME_TITLE_FMT " %-5s" +#define TSF_PAUSE_TIME_TITLE_ARG , "tsfup" +#define TSF_PAUSE_TIME_VALUE_FMT " %5d" +#define TSF_PAUSE_TIME_VALUE_ARG , ((iface->mlmeextpriv.tsf_update_required && iface->mlmeextpriv.tsf_update_pause_stime) ? (rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime) > 99999 ? 99999 : rtw_get_passing_time_ms(iface->mlmeextpriv.tsf_update_pause_stime)) : 0) +#else +#define TSF_PAUSE_TIME_TITLE_FMT "" +#define TSF_PAUSE_TIME_TITLE_ARG +#define TSF_PAUSE_TIME_VALUE_FMT "" +#define TSF_PAUSE_TIME_VALUE_ARG +#endif + +#if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG) +#define INFO_FMT " %-4s" +#define INFO_ARG , "info" +#define INFO_CNT_FMT " %-20s" +#define INFO_CNT_ARG , str_val +#else +#define INFO_FMT "" +#define INFO_ARG +#define INFO_CNT_FMT "" +#define INFO_CNT_ARG #endif RTW_PRINT_SEL(sel, "%-2s %-15s %c %-3s %-3s %-3s %-17s %-4s %-7s" P2P_INFO_TITLE_FMT - " %s\n" + TSF_PAUSE_TIME_TITLE_FMT + " %s"INFO_FMT"\n" , "id", "ifname", ' ', "bup", "nup", "ncd", "macaddr", "port", "ch" P2P_INFO_TITLE_ARG - , "status"); + TSF_PAUSE_TIME_TITLE_ARG + , "status"INFO_ARG); RTW_PRINT_SEL(sel, "---------------------------------------------------------------" P2P_INFO_DASH @@ -461,21 +523,64 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (iface) { + #if (defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN)) || defined(CONFIG_CLIENT_PORT_CFG) + _rtw_memset(&str_val, '\0', sizeof(str_val)); + #endif + #if defined(CONFIG_SUPPORT_MULTI_BCN) && defined(CONFIG_FW_HANDLE_TXBCN) + if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) { + u8 len; + char *p = str_val; + char tmp_str[10] = {'\0'}; + + len = snprintf(tmp_str, sizeof(tmp_str), "%s", "ap_id:"); + strncpy(p, tmp_str, len); + p += len; + _rtw_memset(&tmp_str, '\0', sizeof(tmp_str)); + #ifdef DBG_HW_PORT + len = snprintf(tmp_str, sizeof(tmp_str), "%d (%d,%d)", iface->vap_id, iface->hw_port, iface->client_port); + #else + len = snprintf(tmp_str, sizeof(tmp_str), "%d", iface->vap_id); + #endif + strncpy(p, tmp_str, len); + } + #endif + #ifdef CONFIG_CLIENT_PORT_CFG + if (MLME_IS_STA(iface)) { + u8 len; + char *p = str_val; + char tmp_str[10] = {'\0'}; + + len = snprintf(tmp_str, sizeof(tmp_str), "%s", "c_pid:"); + strncpy(p, tmp_str, len); + p += len; + _rtw_memset(&tmp_str, '\0', sizeof(tmp_str)); + #ifdef DBG_HW_PORT + len = snprintf(tmp_str, sizeof(tmp_str), "%d (%d,%d)", iface->client_port, iface->hw_port, iface->client_port); + #else + len = snprintf(tmp_str, sizeof(tmp_str), "%d", iface->client_port); + #endif + strncpy(p, tmp_str, len); + } + #endif + RTW_PRINT_SEL(sel, "%2d %-15s %c %3u %3u %3u "MAC_FMT" %4hhu %3u,%u,%u" P2P_INFO_VALUE_FMT - " "MLME_STATE_FMT"\n" + TSF_PAUSE_TIME_VALUE_FMT + " "MLME_STATE_FMT" " INFO_CNT_FMT"\n" , i, iface->registered ? ADPT_ARG(iface) : NULL , iface->registered ? 'R' : ' ' , iface->bup , iface->netif_up , iface->net_closed , MAC_ARG(adapter_mac_addr(iface)) - , get_hw_port(iface) + , rtw_hal_get_port(iface) , iface->mlmeextpriv.cur_channel , iface->mlmeextpriv.cur_bwmode , iface->mlmeextpriv.cur_ch_offset P2P_INFO_VALUE_ARG + TSF_PAUSE_TIME_VALUE_ARG , MLME_STATE_ARG(iface) + INFO_CNT_ARG ); } } @@ -490,11 +595,12 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) , u_ch, u_bw, u_offset ); - RTW_PRINT_SEL(sel, "%55s %3u,%u,%u\n" + RTW_PRINT_SEL(sel, "%55s %3u,%u,%u offch_state:%d\n" , "oper:" , dvobj->oper_channel , dvobj->oper_bwmode , dvobj->oper_ch_offset + , rfctl->offch_state ); #ifdef CONFIG_DFS_MASTER @@ -511,24 +617,11 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) else { u32 non_ocp_ms; u32 cac_ms; - u8 dfs_domain = rtw_odm_get_dfs_domain(dvobj_get_primary_adapter(dvobj)); + u8 dfs_domain = rtw_odm_get_dfs_domain(dvobj); _RTW_PRINT_SEL(sel, ", domain:%u", dfs_domain); - for (i = 0; i < dvobj->iface_nums; i++) { - if (!dvobj->padapters[i]) - continue; - if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE) - && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE)) - break; - } - - if (i >= dvobj->iface_nums) { - RTW_PRINT_SEL(sel, "DFS master enable without AP mode???"); - goto end_dfs_master; - } - - rtw_get_ch_waiting_ms(dvobj->padapters[i] + rtw_get_ch_waiting_ms(rfctl , rfctl->radar_detect_ch , rfctl->radar_detect_bw , rfctl->radar_detect_offset @@ -695,7 +788,6 @@ int proc_get_read_reg(struct seq_file *m, void *v) ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - struct net_device *dev = data; char tmp[16]; u32 addr, len; @@ -751,12 +843,12 @@ int proc_get_rx_stat(struct seq_file *m, void *v) if (pstats == NULL) continue; - if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(adapter), 6) != _TRUE)) { - RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(psta->hwaddr)); - RTW_PRINT_SEL(m, "data_rx_cnt :\t%llu\n", pstats->rx_data_pkts - pstats->rx_data_last_pkts); - pstats->rx_data_last_pkts = pstats->rx_data_pkts; + if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) { + RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); + RTW_PRINT_SEL(m, "data_rx_cnt :\t%llu\n", sta_rx_data_uc_pkts(psta) - pstats->last_rx_data_uc_pkts); + pstats->last_rx_data_uc_pkts = sta_rx_data_uc_pkts(psta); RTW_PRINT_SEL(m, "duplicate_cnt :\t%u\n", pstats->duplicate_cnt); pstats->duplicate_cnt = 0; RTW_PRINT_SEL(m, "rx_per_rate_cnt :\n"); @@ -781,9 +873,12 @@ int proc_get_tx_stat(struct seq_file *m, void *v) _list *plist, *phead; struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct sta_info *psta = NULL, *sta_rec[NUM_STA]; + struct sta_info *psta = NULL; + u8 sta_mac[NUM_STA][ETH_ALEN] = {{0}}; + uint mac_id[NUM_STA]; struct stainfo_stats *pstats = NULL; struct sta_priv *pstapriv = &(adapter->stapriv); + struct sta_priv *pstapriv_primary = &(GET_PRIMARY_ADAPTER(adapter))->stapriv; u32 i, macid_rec_idx = 0; u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; @@ -791,39 +886,54 @@ int proc_get_tx_stat(struct seq_file *m, void *v) _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); for (i = 0; i < NUM_STA; i++) { - sta_rec[i] = NULL; phead = &(pstapriv->sta_hash[i]); plist = get_next(phead); while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); plist = get_next(plist); - if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(adapter), 6) != _TRUE)) { - sta_rec[macid_rec_idx++] = psta; + if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) { + _rtw_memcpy(&sta_mac[macid_rec_idx][0], psta->cmn.mac_addr, ETH_ALEN); + mac_id[macid_rec_idx] = psta->cmn.mac_id; + macid_rec_idx++; } } } _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); for (i = 0; i < macid_rec_idx; i++) { - pstats = &(sta_rec[i]->sta_stats); - if (pstats == NULL) - continue; - pstapriv->c2h_sta = sta_rec[i]; - rtw_hal_reqtxrpt(adapter, sta_rec[i]->mac_id); + _rtw_memcpy(pstapriv_primary->c2h_sta_mac, &sta_mac[i][0], ETH_ALEN); + pstapriv_primary->c2h_adapter_id = adapter->iface_id; rtw_sctx_init(&gotc2h, 60); - pstapriv->gotc2h = &gotc2h; + pstapriv_primary->gotc2h = &gotc2h; + rtw_hal_reqtxrpt(adapter, mac_id[i]); if (rtw_sctx_wait(&gotc2h, __func__)) { - RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(sta_rec[i]->hwaddr)); - RTW_PRINT_SEL(m, "data_sent_cnt :\t%u\n", pstats->tx_ok_cnt + pstats->tx_fail_cnt); - RTW_PRINT_SEL(m, "success_cnt :\t%u\n", pstats->tx_ok_cnt); - RTW_PRINT_SEL(m, "failure_cnt :\t%u\n", pstats->tx_fail_cnt); - RTW_PRINT_SEL(m, "retry_cnt :\t%u\n\n", pstats->tx_retry_cnt); + psta = rtw_get_stainfo(pstapriv, &sta_mac[i][0]); + if(psta) { + pstats = &psta->sta_stats; +#ifndef ROKU_PRIVATE + RTW_PRINT_SEL(m, "data_sent_cnt :\t%u\n", pstats->tx_ok_cnt + pstats->tx_fail_cnt); + RTW_PRINT_SEL(m, "success_cnt :\t%u\n", pstats->tx_ok_cnt); + RTW_PRINT_SEL(m, "failure_cnt :\t%u\n", pstats->tx_fail_cnt); + RTW_PRINT_SEL(m, "retry_cnt :\t%u\n\n", pstats->tx_retry_cnt); +#else + RTW_PRINT_SEL(m, "MAC: " MAC_FMT " sent: %u fail: %u retry: %u\n", + MAC_ARG(&sta_mac[i][0]), pstats->tx_ok_cnt, pstats->tx_fail_cnt, pstats->tx_retry_cnt); +#endif /* ROKU_PRIVATE */ + + } else + RTW_PRINT_SEL(m, "STA is gone\n"); } else { + //to avoid c2h modify counters + pstapriv_primary->gotc2h = NULL; + _rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN); + pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER; RTW_PRINT_SEL(m, "Warming : Query timeout, operation abort!!\n"); - RTW_PRINT_SEL(m, "\n"); break; } + pstapriv_primary->gotc2h = NULL; + _rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN); + pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER; } return 0; } @@ -928,11 +1038,11 @@ int proc_get_roam_param(struct seq_file *m, void *v) _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *mlme = &adapter->mlmepriv; - RTW_PRINT_SEL(m, "%12s %12s %11s %14s\n", "rssi_diff_th", "scanr_exp_ms", "scan_int_ms", "rssi_threshold"); - RTW_PRINT_SEL(m, "%-12u %-12u %-11u %-14u\n" + RTW_PRINT_SEL(m, "%12s %15s %26s %16s\n", "rssi_diff_th", "scanr_exp_ms", "scan_interval(unit:2 sec)", "rssi_threshold"); + RTW_PRINT_SEL(m, "%-15u %-13u %-27u %-11u\n" , mlme->roam_rssi_diff_th , mlme->roam_scanr_exp_ms - , mlme->roam_scan_int_ms + , mlme->roam_scan_int , mlme->roam_rssi_threshold ); @@ -948,7 +1058,7 @@ ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t char tmp[32]; u8 rssi_diff_th; u32 scanr_exp_ms; - u32 scan_int_ms; + u32 scan_int; u8 rssi_threshold; if (count < 1) @@ -961,14 +1071,14 @@ ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhu %u %u %hhu", &rssi_diff_th, &scanr_exp_ms, &scan_int_ms, &rssi_threshold); + int num = sscanf(tmp, "%hhu %u %u %hhu", &rssi_diff_th, &scanr_exp_ms, &scan_int, &rssi_threshold); if (num >= 1) mlme->roam_rssi_diff_th = rssi_diff_th; if (num >= 2) mlme->roam_scanr_exp_ms = scanr_exp_ms; if (num >= 3) - mlme->roam_scan_int_ms = scan_int_ms; + mlme->roam_scan_int = scan_int; if (num >= 4) mlme->roam_rssi_threshold = rssi_threshold; } @@ -1027,7 +1137,7 @@ ssize_t proc_set_ft_flags(struct file *file, const char __user *buffer, size_t c int num = sscanf(tmp, "%hhx", &flags); if (num == 1) - adapter->mlmepriv.ftpriv.ft_flags = flags; + adapter->mlmepriv.ft_roam.ft_flags = flags; } return count; @@ -1039,7 +1149,7 @@ int proc_get_ft_flags(struct seq_file *m, void *v) struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - RTW_PRINT_SEL(m, "0x%02x\n", adapter->mlmepriv.ftpriv.ft_flags); + RTW_PRINT_SEL(m, "0x%02x\n", adapter->mlmepriv.ft_roam.ft_flags); return 0; } @@ -1223,65 +1333,26 @@ int proc_get_scan_abort(struct seq_file *m, void *v) return 0; } -#ifdef CONFIG_SCAN_BACKOP -int proc_get_backop_flags_sta(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - - RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_sta(mlmeext)); - - return 0; -} - -ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - - char tmp[32]; - u8 flags; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx", &flags); - - if (num == 1) - mlmeext_assign_scan_backop_flags_sta(mlmeext, flags); - } - - return count; -} - -int proc_get_backop_flags_ap(struct seq_file *m, void *v) +#ifdef CONFIG_RTW_REPEATER_SON +int proc_get_rson_data(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - - RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_ap(mlmeext)); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char rson_data_str[256]; + rtw_rson_get_property_str(padapter, rson_data_str); + RTW_PRINT_SEL(m, "%s\n", rson_data_str); return 0; } -ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - - char tmp[32]; - u8 flags; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + char tmp[64] = {0}; + int num; + u8 field[10], value[64]; if (count < 1) return -EFAULT; @@ -1292,17 +1363,21 @@ ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, s } if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx", &flags); - - if (num == 1) - mlmeext_assign_scan_backop_flags_ap(mlmeext, flags); + num = sscanf(tmp, "%s %s", field, value); + if (num != 2) { + RTW_INFO("Invalid format : echo > son_data\n"); + return count; + } + RTW_INFO("field=%s value=%s\n", field, value); + num = rtw_rson_set_property(padapter, field, value); + if (num != 1) { + RTW_INFO("Invalid field(%s) or value(%s)\n", field, value); + return count; + } } - return count; } - -#endif /* CONFIG_SCAN_BACKOP */ +#endif /*CONFIG_RTW_REPEATER_SON*/ int proc_get_survey_info(struct seq_file *m, void *v) { @@ -1321,16 +1396,25 @@ int proc_get_survey_info(struct seq_file *m, void *v) char flag_str[64]; int ielen = 0; u32 wpsielen = 0; +#ifdef CONFIG_RTW_MESH + const char *ssid_title_str = "ssid/mesh_id"; +#else + const char *ssid_title_str = "ssid"; +#endif _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); phead = get_list_head(queue); if (!phead) - return 0; + goto _exit; plist = get_next(phead); if (!plist) - return 0; + goto _exit; + +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_show_survey_info(m, plist, phead); +#else - RTW_PRINT_SEL(m, "%5s %-17s %3s %-3s %-4s %-4s %5s %32s %32s\n", "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "age", "flag", "ssid"); + RTW_PRINT_SEL(m, "%5s %-17s %3s %-3s %-4s %-4s %5s %32s %32s\n", "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "age", "flag", ssid_title_str); while (1) { if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; @@ -1346,8 +1430,9 @@ int proc_get_survey_info(struct seq_file *m, void *v) notify_signal = translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);/* dbm */ } -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(pnetwork->network.Configuration.DSConfig), &(notify_noise)); +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + if (IS_NM_ENABLE(padapter)) + notify_noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig); #endif ie_wpa = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12); @@ -1361,21 +1446,25 @@ int proc_get_survey_info(struct seq_file *m, void *v) (ie_wpa2) ? "[WPA2]" : "", (!ie_wpa && !ie_wpa && ie_cap & BIT(4)) ? "[WEP]" : "", (ie_wps) ? "[WPS]" : "", - (pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]" : "", + (pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]" : + (pnetwork->network.InfrastructureMode == Ndis802_11_mesh) ? "[MESH]" : "", (ie_cap & BIT(0)) ? "[ESS]" : "", (ie_p2p) ? "[P2P]" : ""); RTW_PRINT_SEL(m, "%5d "MAC_FMT" %3d %3d %4d %4d %5d %32s %32s\n", - ++index, - MAC_ARG(pnetwork->network.MacAddress), - pnetwork->network.Configuration.DSConfig, - (int)pnetwork->network.Rssi, - notify_signal, - notify_noise, - rtw_get_passing_time_ms((u32)pnetwork->last_scanned), - flag_str, - pnetwork->network.Ssid.Ssid); + ++index, + MAC_ARG(pnetwork->network.MacAddress), + pnetwork->network.Configuration.DSConfig, + (int)pnetwork->network.Rssi, + notify_signal, + notify_noise, + rtw_get_passing_time_ms(pnetwork->last_scanned), + flag_str, + pnetwork->network.InfrastructureMode == Ndis802_11_mesh ? pnetwork->network.mesh_id.Ssid : pnetwork->network.Ssid.Ssid + ); plist = get_next(plist); } +#endif +_exit: _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); return 0; @@ -1383,19 +1472,28 @@ int proc_get_survey_info(struct seq_file *m, void *v) ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - _irqL irqL; struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - bool need_indicate_scan_done = _FALSE; u8 _status = _FALSE; - NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; - + u8 ssc_chk; if (count < 1) return -EFAULT; +#if 1 + ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE); + if (ssc_chk != SS_ALLOW) + goto exit; + + rtw_ps_deny(padapter, PS_DENY_SCAN); + if (_FAIL == rtw_pwr_wakeup(padapter)) + goto cancel_ps_deny; + if (!rtw_is_adapter_up(padapter)) { + RTW_INFO("scan abort!! adapter cannot use\n"); + goto cancel_ps_deny; + } +#else #ifdef CONFIG_MP_INCLUDED - if (rtw_mi_mp_mode_check(padapter)) { + if (rtw_mp_mode_check(padapter)) { RTW_INFO("MP mode block Scan request\n"); goto exit; } @@ -1435,13 +1533,76 @@ ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_ goto cancel_ps_deny; } #endif - _status = rtw_set_802_11_bssid_list_scan(padapter, NULL, 0, NULL, 0); +#endif + _status = rtw_set_802_11_bssid_list_scan(padapter, NULL); cancel_ps_deny: rtw_ps_deny_cancel(padapter, PS_DENY_SCAN); exit: return count; } +#ifdef ROKU_PRIVATE +int proc_get_infra_ap(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + struct sta_info *psta; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct ht_priv_infra_ap *phtpriv = &pmlmepriv->htpriv_infra_ap; +#ifdef CONFIG_80211AC_VHT + struct vht_priv_infra_ap *pvhtpriv = &pmlmepriv->vhtpriv_infra_ap; +#endif + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct sta_priv *pstapriv = &padapter->stapriv; + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if (psta) { + unsigned int i, j; + unsigned int Rx_ss = 0, Tx_ss = 0; + struct recv_reorder_ctrl *preorder_ctrl; + + RTW_PRINT_SEL(m, "SSID=%s\n", pmlmeinfo->network.Ssid.Ssid); + RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); + RTW_PRINT_SEL(m, "Supported rate="); + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (pmlmeinfo->SupportedRates_infra_ap[i] == 0) + break; + RTW_PRINT_SEL(m, " 0x%x", pmlmeinfo->SupportedRates_infra_ap[i]); + } + RTW_PRINT_SEL(m, "\n"); +#ifdef CONFIG_80211N_HT + if (pmlmeinfo->ht_vht_received & BIT(0)) { + RTW_PRINT_SEL(m, "Supported MCS set="); + for (i = 0; i < 16 ; i++) + RTW_PRINT_SEL(m, " 0x%02x", phtpriv->MCS_set_infra_ap[i]); + RTW_PRINT_SEL(m, "\n"); + RTW_PRINT_SEL(m, "highest supported data rate=0x%x\n", phtpriv->rx_highest_data_rate_infra_ap); + RTW_PRINT_SEL(m, "HT_supported_channel_width_set=0x%x\n", phtpriv->channel_width_infra_ap); + RTW_PRINT_SEL(m, "sgi_20m=%d, sgi_40m=%d\n", phtpriv->sgi_20m_infra_ap, phtpriv->sgi_40m_infra_ap); + RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x\n", phtpriv->ldpc_cap_infra_ap, phtpriv->stbc_cap_infra_ap); + RTW_PRINT_SEL(m, "HT_number_of_stream=%d\n", phtpriv->Rx_ss_infra_ap); + } +#endif + +#ifdef CONFIG_80211AC_VHT + if (pmlmeinfo->ht_vht_received & BIT(1)) { + RTW_PRINT_SEL(m, "VHT_supported_channel_width_set=0x%x\n", pvhtpriv->channel_width_infra_ap); + RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", pvhtpriv->ldpc_cap_infra_ap, pvhtpriv->stbc_cap_infra_ap, pvhtpriv->beamform_cap_infra_ap); + RTW_PRINT_SEL(m, "Rx_vht_mcs_map=0x%x, Tx_vht_mcs_map=0x%x\n", *(u16 *)pvhtpriv->vht_mcs_map_infra_ap, *(u16 *)pvhtpriv->vht_mcs_map_tx_infra_ap); + RTW_PRINT_SEL(m, "VHT_number_of_stream=%d\n", pvhtpriv->number_of_streams_infra_ap); + } +#endif + } else + RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); + } else + RTW_PRINT_SEL(m, "this only applies to STA mode\n"); + return 0; +} + +#endif /* ROKU_PRIVATE */ int proc_get_ap_info(struct seq_file *m, void *v) { @@ -1451,21 +1612,26 @@ int proc_get_ap_info(struct seq_file *m, void *v) struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct sta_priv *pstapriv = &padapter->stapriv; + /* ap vendor */ + char vendor[VENDOR_NAME_LEN] = {0}; + get_assoc_AP_Vendor(vendor,pmlmeinfo->assoc_AP_vendor); + RTW_PRINT_SEL(m,"AP Vendor %s\n", vendor); + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); if (psta) { - int i; - struct recv_reorder_ctrl *preorder_ctrl; - RTW_PRINT_SEL(m, "SSID=%s\n", cur_network->network.Ssid.Ssid); - RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); RTW_PRINT_SEL(m, "cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); RTW_PRINT_SEL(m, "wireless_mode=0x%x, rtsen=%d, cts2slef=%d\n", psta->wireless_mode, psta->rtsen, psta->cts2self); - RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); + RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); #ifdef CONFIG_80211N_HT RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); - RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" + , psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x, beamform_cap=0x%x\n", psta->htpriv.ldpc_cap, psta->htpriv.stbc_cap, psta->htpriv.beamform_cap); @@ -1475,7 +1641,6 @@ int proc_get_ap_info(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap); RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len); #endif - sta_rx_reorder_ctl_dump(m, psta); } else RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); @@ -1487,8 +1652,7 @@ ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct recv_priv *precvpriv = &padapter->recvpriv; char cmd[32] = {0}; u8 cnt = 0; @@ -1500,13 +1664,14 @@ ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t if (buffer && !copy_from_user(cmd, buffer, count)) { int num = sscanf(cmd, "%hhx", &cnt); - if (0 == cnt) { - pdbgpriv->dbg_rx_ampdu_drop_count = 0; - pdbgpriv->dbg_rx_ampdu_forced_indicate_count = 0; - pdbgpriv->dbg_rx_ampdu_loss_count = 0; - pdbgpriv->dbg_rx_dup_mgt_frame_drop_count = 0; - pdbgpriv->dbg_rx_ampdu_window_shift_cnt = 0; - pdbgpriv->dbg_rx_conflic_mac_addr_cnt = 0; + if (num == 1 && cnt == 0) { + precvpriv->dbg_rx_ampdu_drop_count = 0; + precvpriv->dbg_rx_ampdu_forced_indicate_count = 0; + precvpriv->dbg_rx_ampdu_loss_count = 0; + precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0; + precvpriv->dbg_rx_ampdu_window_shift_cnt = 0; + precvpriv->dbg_rx_conflic_mac_addr_cnt = 0; + precvpriv->dbg_rx_drop_count = 0; } } @@ -1520,9 +1685,15 @@ int proc_get_trx_info(struct seq_file *m, void *v) _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct recv_priv *precvpriv = &padapter->recvpriv; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; struct hw_xmit *phwxmit; + u16 vo_params[4], vi_params[4], be_params[4], bk_params[4]; + + padapter->hal_func.read_wmmedca_reg(padapter, vo_params, vi_params, be_params, bk_params); + + RTW_PRINT_SEL(m, "wmm_edca_vo, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vo_params[0], vo_params[1], vo_params[2], vo_params[3]); + RTW_PRINT_SEL(m, "wmm_edca_vi, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vi_params[0], vi_params[1], vi_params[2], vi_params[3]); + RTW_PRINT_SEL(m, "wmm_edca_be, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", be_params[0], be_params[1], be_params[2], be_params[3]); + RTW_PRINT_SEL(m, "wmm_edca_bk, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", bk_params[0], bk_params[1], bk_params[2], bk_params[3]); dump_os_queue(m, padapter); @@ -1538,65 +1709,32 @@ int proc_get_trx_info(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "%d, hwq.accnt=%d\n", i, phwxmit->accnt); } + rtw_hal_get_hwreg(padapter, HW_VAR_DUMP_MAC_TXFIFO, (u8 *)m); + #ifdef CONFIG_USB_HCI RTW_PRINT_SEL(m, "rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt))); #endif + dump_rx_bh_tk(m, &GET_PRIMARY_ADAPTER(padapter)->recvpriv); + /* Folowing are RX info */ + RTW_PRINT_SEL(m, "RX: Count of Packets dropped by Driver: %llu\n", (unsigned long long)precvpriv->dbg_rx_drop_count); /* Counts of packets whose seq_num is less than preorder_ctrl->indicate_seq, Ex delay, retransmission, redundant packets and so on */ - RTW_PRINT_SEL(m, "Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_drop_count); + RTW_PRINT_SEL(m, "Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_drop_count); /* How many times the Rx Reorder Timer is triggered. */ - RTW_PRINT_SEL(m, "Rx: Reorder Time-out Trigger Counts: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_forced_indicate_count); + RTW_PRINT_SEL(m, "Rx: Reorder Time-out Trigger Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_forced_indicate_count); /* Total counts of packets loss */ - RTW_PRINT_SEL(m, "Rx: Packet Loss Counts: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_loss_count); - RTW_PRINT_SEL(m, "Rx: Duplicate Management Frame Drop Count: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_dup_mgt_frame_drop_count); - RTW_PRINT_SEL(m, "Rx: AMPDU BA window shift Count: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_window_shift_cnt); + RTW_PRINT_SEL(m, "Rx: Packet Loss Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_loss_count); + RTW_PRINT_SEL(m, "Rx: Duplicate Management Frame Drop Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_dup_mgt_frame_drop_count); + RTW_PRINT_SEL(m, "Rx: AMPDU BA window shift Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_window_shift_cnt); /*The same mac addr counts*/ - RTW_PRINT_SEL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_conflic_mac_addr_cnt); - return 0; -} - -int proc_get_dis_pwt(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 dis_pwt = 0; - rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DIS_PWT, &(dis_pwt)); - RTW_PRINT_SEL(m, " Tx Power training mode:%s\n", (dis_pwt == _TRUE) ? "Disable" : "Enable"); + RTW_PRINT_SEL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_conflic_mac_addr_cnt); return 0; } -ssize_t proc_set_dis_pwt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[4] = {0}; - u8 dis_pwt = 0; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx", &dis_pwt); - RTW_INFO("Set Tx Power training mode:%s\n", (dis_pwt == _TRUE) ? "Disable" : "Enable"); - - if (num >= 1) - rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DIS_PWT, &(dis_pwt)); - } - - return count; - -} int proc_get_rate_ctl(struct seq_file *m, void *v) { struct net_device *dev = m->private; - int i; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); u8 data_rate = 0, sgi = 0, data_fb = 0; @@ -1616,14 +1754,21 @@ int proc_get_rate_ctl(struct seq_file *m, void *v) return 0; } +#ifdef CONFIG_PHDYM_FW_FIXRATE +void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate); +#endif ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); char tmp[32]; - u8 fix_rate; - u8 data_fb; + u8 fix_rate = 0xFF; +#ifdef CONFIG_PHDYM_FW_FIXRATE + u8 bw = 0; +#else + u8 data_fb = 0; +#endif if (count < 1) return -EFAULT; @@ -1634,7 +1779,56 @@ ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t c } if (buffer && !copy_from_user(tmp, buffer, count)) { +#ifdef CONFIG_PHDYM_FW_FIXRATE + struct dm_struct *dm = adapter_to_phydm(adapter); + u8 en = 1, macid = 255; + _irqL irqL; + _list *plist, *phead; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &(adapter->stapriv); + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + uint mac_id[NUM_STA]; + int i, macid_rec_idx = 0; + int num = sscanf(tmp, "%hhx %hhu %hhu", &fix_rate, &bw, &macid); + + if (num < 1) { + RTW_INFO("Invalid input!! \"ex: echo > /proc/.../rate_ctl\"\n"); + return count; + } + + if ((fix_rate == 0) || (fix_rate == 0xFF)) + en = 0; + + if (macid != 255) { + RTW_INFO("Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\n", en, macid, bw, fix_rate); + phydm_fw_fix_rate(dm, en, macid, bw, fix_rate); + return count; + } + + /* no specific macid, apply to all macids except bc/mc macid */ + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), ETH_ALEN) != _TRUE)) { + mac_id[macid_rec_idx] = psta->cmn.mac_id; + macid_rec_idx++; + } + } + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (i = 0; i < macid_rec_idx; i++) { + RTW_INFO("Call phydm_fw_fix_rate()--en[%d] mac_id[%d] bw[%d] fix_rate[%d]\n", en, mac_id[i], bw, fix_rate); + phydm_fw_fix_rate(dm, en, mac_id[i], bw, fix_rate); + } +#else int num = sscanf(tmp, "%hhx %hhu", &fix_rate, &data_fb); if (num >= 1) { @@ -1651,15 +1845,59 @@ ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t c } if (num >= 2) adapter->data_fb = data_fb ? 1 : 0; +#endif + } + + return count; +} + +#ifdef CONFIG_AP_MODE +int proc_get_bmc_tx_rate(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) { + RTW_PRINT_SEL(m, "[ERROR] Not in SoftAP/Mesh mode !!\n"); + return 0; + } + + RTW_PRINT_SEL(m, " BMC Tx rate - %s\n", MGN_RATE_STR(adapter->bmc_tx_rate)); + return 0; +} + +ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 bmc_tx_rate; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &bmc_tx_rate); + + if (num >= 1) + /*adapter->bmc_tx_rate = hw_rate_to_m_rate(bmc_tx_rate);*/ + adapter->bmc_tx_rate = bmc_tx_rate; } return count; } +#endif /*CONFIG_AP_MODE*/ + int proc_get_tx_power_offset(struct seq_file *m, void *v) { struct net_device *dev = m->private; - int i; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); RTW_PRINT_SEL(m, "Tx power offset - %u\n", adapter->power_offset); @@ -1776,9 +2014,10 @@ ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_ int num = sscanf(tmp, "%hhx", &dump_rx_cnt_mode); - rtw_dump_phy_rxcnts_preprocess(adapter, dump_rx_cnt_mode); - adapter->dump_rx_cnt_mode = dump_rx_cnt_mode; - + if (num == 1) { + rtw_dump_phy_rxcnts_preprocess(adapter, dump_rx_cnt_mode); + adapter->dump_rx_cnt_mode = dump_rx_cnt_mode; + } } return count; @@ -1810,10 +2049,7 @@ bool rtw_fwdl_test_trigger_wintint_rdy_fail(void) ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; - int num; if (count < 1) return -EFAULT; @@ -1824,7 +2060,7 @@ ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, si } if (buffer && !copy_from_user(tmp, buffer, count)) - num = sscanf(tmp, "%hhu %hhu", &fwdl_test_chksum_fail, &fwdl_test_wintint_rdy_fail); + sscanf(tmp, "%hhu %hhu", &fwdl_test_chksum_fail, &fwdl_test_wintint_rdy_fail); return count; } @@ -1843,10 +2079,7 @@ bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void) ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; - int num; if (count < 1) return -EFAULT; @@ -1857,56 +2090,10 @@ ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *bu } if (buffer && !copy_from_user(tmp, buffer, count)) - num = sscanf(tmp, "%hhu", &del_rx_ampdu_test_no_tx_fail); - - return count; -} - -#ifdef CONFIG_DFS_MASTER -int proc_get_dfs_master_test_case(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - - RTW_PRINT_SEL(m, "%-24s %-19s\n", "radar_detect_trigger_non", "choose_dfs_ch_first"); - RTW_PRINT_SEL(m, "%24hhu %19hhu\n" - , rfctl->dbg_dfs_master_radar_detect_trigger_non - , rfctl->dbg_dfs_master_choose_dfs_ch_first - ); - - return 0; -} - -ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - char tmp[32]; - u8 radar_detect_trigger_non; - u8 choose_dfs_ch_first; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhu %hhu", &radar_detect_trigger_non, &choose_dfs_ch_first); - - if (num >= 1) - rfctl->dbg_dfs_master_radar_detect_trigger_non = radar_detect_trigger_non; - if (num >= 2) - rfctl->dbg_dfs_master_choose_dfs_ch_first = choose_dfs_ch_first; - } + sscanf(tmp, "%hhu", &del_rx_ampdu_test_no_tx_fail); return count; } -#endif /* CONFIG_DFS_MASTER */ static u32 g_wait_hiq_empty_ms = 0; @@ -1917,10 +2104,7 @@ u32 rtw_get_wait_hiq_empty_ms(void) ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; - int num; if (count < 1) return -EFAULT; @@ -1931,12 +2115,12 @@ ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, si } if (buffer && !copy_from_user(tmp, buffer, count)) - num = sscanf(tmp, "%u", &g_wait_hiq_empty_ms); + sscanf(tmp, "%u", &g_wait_hiq_empty_ms); return count; } -static u32 sta_linking_test_start_time = 0; +static systime sta_linking_test_start_time = 0; static u32 sta_linking_test_wait_ms = 0; static u8 sta_linking_test_force_fail = 0; @@ -1957,8 +2141,6 @@ bool rtw_sta_linking_test_force_fail(void) ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; if (count < 1) @@ -1983,6 +2165,47 @@ ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, return count; } +#ifdef CONFIG_AP_MODE +static u16 ap_linking_test_force_auth_fail = 0; +static u16 ap_linking_test_force_asoc_fail = 0; + +u16 rtw_ap_linking_test_force_auth_fail(void) +{ + return ap_linking_test_force_auth_fail; +} + +u16 rtw_ap_linking_test_force_asoc_fail(void) +{ + return ap_linking_test_force_asoc_fail; +} + +ssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + u16 force_auth_fail = 0; + u16 force_asoc_fail = 0; + int num = sscanf(tmp, "%hu %hu", &force_auth_fail, &force_asoc_fail); + + if (num >= 1) + ap_linking_test_force_auth_fail = force_auth_fail; + if (num >= 2) + ap_linking_test_force_asoc_fail = force_asoc_fail; + } + + return count; +} +#endif /* CONFIG_AP_MODE */ + int proc_get_ps_dbg_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -2043,7 +2266,7 @@ ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_ int num = sscanf(tmp, "%hhx", &ps_dbg_cmd_id); - if (ps_dbg_cmd_id == 1) /*Clean all*/ + if (num == 1 && ps_dbg_cmd_id == 1) /*Clean all*/ _rtw_memset(pdbgpriv, 0, sizeof(struct debug_priv)); } @@ -2359,7 +2582,7 @@ ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t int num = sscanf(tmp, "%d ", &enable); - if (regsty && enable <= 1) { + if (num == 1 && regsty && enable <= 1) { regsty->check_hw_status = enable; RTW_INFO("check_hw_status=%d\n", regsty->check_hw_status); } @@ -2368,14 +2591,68 @@ ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t return count; } -int proc_get_trx_info_debug(struct seq_file *m, void *v) +#ifdef CONFIG_HUAWEI_PROC +int proc_get_huawei_trx_info(struct seq_file *sel, void *v) { - struct net_device *dev = m->private; + struct net_device *dev = sel->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dm_struct *dm = adapter_to_phydm(padapter); + struct sta_info *psta; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct ra_sta_info *ra_info; + u8 curr_tx_sgi = _FALSE; + u8 curr_tx_rate = 0; + u8 mac_id; +#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA + u8 isCCKrate, rf_path; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info; +#endif - int i; + if (!dm->is_linked) { + RTW_PRINT_SEL(sel, "NO link\n\n"); + return 0; + } + + /*============ tx info ============ */ + for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) { + if (rtw_macid_is_used(macid_ctl, mac_id) && !rtw_macid_is_bmc(macid_ctl, mac_id)) { + psta = macid_ctl->sta[mac_id]; + if (!psta) + continue; + + RTW_PRINT_SEL(sel, "STA [" MAC_FMT "]\n", MAC_ARG(psta->cmn.mac_addr)); + + ra_info = &psta->cmn.ra_info; + curr_tx_sgi = rtw_get_current_tx_sgi(padapter, psta); + curr_tx_rate = rtw_get_current_tx_rate(padapter, psta); + RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n", + HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L"); + RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw)); + } + } + + /*============ rx info ============ */ + RTW_PRINT_SEL(sel, "rx_rate : %s\n", HDATA_RATE(dm->rx_rate)); +#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA + isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE; + for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) { + if (!isCCKrate) + _RTW_PRINT_SEL(sel , "RF_PATH_%d : rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n", + rf_path, psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]); + } +#endif + RTW_PRINT_SEL(sel, "\n"); + return 0; +} +#endif /* CONFIG_HUAWEI_PROC */ + +int proc_get_trx_info_debug(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); /*============ tx info ============ */ rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, m); @@ -2383,7 +2660,6 @@ int proc_get_trx_info_debug(struct seq_file *m, void *v) /*============ rx info ============ */ rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, m, _FALSE); - return 0; } @@ -2391,13 +2667,11 @@ int proc_get_rx_signal(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); RTW_PRINT_SEL(m, "rssi:%d\n", padapter->recvpriv.rssi); - /* RTW_PRINT_SEL(m, "rxpwdb:%d\n", padapter->recvpriv.rxpwdb); */ - RTW_PRINT_SEL(m, "signal_strength:%u\n", padapter->recvpriv.signal_strength); - RTW_PRINT_SEL(m, "signal_qual:%u\n", padapter->recvpriv.signal_qual); +#ifdef CONFIG_MP_INCLUDED if (padapter->registrypriv.mp_mode == 1) { + struct dm_struct *odm = adapter_to_phydm(padapter); if (padapter->mppriv.antenna_rx == ANTENNA_A) RTW_PRINT_SEL(m, "Antenna: A\n"); else if (padapter->mppriv.antenna_rx == ANTENNA_B) @@ -2414,11 +2688,16 @@ int proc_get_rx_signal(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "Antenna: CD\n"); else RTW_PRINT_SEL(m, "Antenna: __\n"); + + RTW_PRINT_SEL(m, "rx_rate = %s\n", HDATA_RATE(odm->rx_rate)); return 0; + } else +#endif + { + /* RTW_PRINT_SEL(m, "rxpwdb:%d\n", padapter->recvpriv.rxpwdb); */ + RTW_PRINT_SEL(m, "signal_strength:%u\n", padapter->recvpriv.signal_strength); + RTW_PRINT_SEL(m, "signal_qual:%u\n", padapter->recvpriv.signal_qual); } - - rtw_get_noise(padapter); - RTW_PRINT_SEL(m, "noise:%d\n", padapter->recvpriv.noise); #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA rtw_odm_get_perpkt_rssi(m, padapter); rtw_get_raw_rssi_info(m, padapter); @@ -2445,9 +2724,12 @@ ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t int num = sscanf(tmp, "%u %u", &is_signal_dbg, &signal_strength); + if (num < 1) + return count; + is_signal_dbg = is_signal_dbg == 0 ? 0 : 1; - if (is_signal_dbg && num != 2) + if (is_signal_dbg && num < 2) return count; signal_strength = signal_strength > 100 ? 100 : signal_strength; @@ -2465,6 +2747,36 @@ ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t return count; } + +int proc_get_mac_rptbuf(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u16 i; + u16 mac_id; + u32 shcut_addr = 0; + u32 read_addr = 0; +#ifdef CONFIG_RTL8814A + RTW_PRINT_SEL(m, "TX ShortCut:\n"); + for (mac_id = 0; mac_id < 64; mac_id++) { + rtw_write16(padapter, 0x140, 0x662 | ((mac_id & BIT5) >> 5)); + shcut_addr = 0x8000; + shcut_addr = shcut_addr | ((mac_id & 0x1f) << 7); + RTW_PRINT_SEL(m, "mac_id=%d, 0x140=%x =>\n", mac_id, 0x662 | ((mac_id & BIT5) >> 5)); + for (i = 0; i < 30; i++) { + read_addr = 0; + read_addr = shcut_addr | (i << 2); + RTW_PRINT_SEL(m, "i=%02d: MAC_%04x= %08x ", i, read_addr, rtw_read32(padapter, read_addr)); + if (!((i + 1) % 4)) + RTW_PRINT_SEL(m, "\n"); + if (i == 29) + RTW_PRINT_SEL(m, "\n"); + } + } +#endif /* CONFIG_RTL8814A */ + return 0; +} + #ifdef CONFIG_80211N_HT int proc_get_ht_enable(struct seq_file *m, void *v) @@ -2499,7 +2811,7 @@ ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t int num = sscanf(tmp, "%d ", &mode); - if (pregpriv && mode < 2) { + if ( num == 1 && pregpriv && mode < 2) { pregpriv->ht_enable = mode; RTW_INFO("ht_enable=%d\n", pregpriv->ht_enable); } @@ -2545,11 +2857,9 @@ ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t co bw_5g = mode >> 4; bw_2g = mode & 0x0f; - if (pregpriv && bw_2g <= 4 && bw_5g <= 4) { - + if (num == 1 && pregpriv && bw_2g <= 4 && bw_5g <= 4) { pregpriv->bw_mode = mode; printk("bw_mode=0x%x\n", mode); - } } @@ -2589,7 +2899,7 @@ ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size int num = sscanf(tmp, "%d ", &mode); - if (pregpriv && mode < 2) { + if (num == 1 && pregpriv && mode < 2) { pregpriv->ampdu_enable = mode; printk("ampdu_enable=%d\n", mode); } @@ -2600,34 +2910,6 @@ ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size } -int proc_get_mac_rptbuf(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u16 i; - u16 mac_id; - u32 shcut_addr = 0; - u32 read_addr = 0; -#ifdef CONFIG_RTL8814A - RTW_PRINT_SEL(m, "TX ShortCut:\n"); - for (mac_id = 0; mac_id < 64; mac_id++) { - rtw_write16(padapter, 0x140, 0x662 | ((mac_id & BIT5) >> 5)); - shcut_addr = 0x8000; - shcut_addr = shcut_addr | ((mac_id & 0x1f) << 7); - RTW_PRINT_SEL(m, "mac_id=%d, 0x140=%x =>\n", mac_id, 0x662 | ((mac_id & BIT5) >> 5)); - for (i = 0; i < 30; i++) { - read_addr = 0; - read_addr = shcut_addr | (i << 2); - RTW_PRINT_SEL(m, "i=%02d: MAC_%04x= %08x ", i, read_addr, rtw_read32(padapter, read_addr)); - if (!((i + 1) % 4)) - RTW_PRINT_SEL(m, "\n"); - if (i == 29) - RTW_PRINT_SEL(m, "\n"); - } - } -#endif /* CONFIG_RTL8814A */ - return 0; -} void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter) { @@ -2676,9 +2958,6 @@ ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t c { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); char tmp[32]; u8 accept; u8 size; @@ -2703,9 +2982,9 @@ ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t c rtw_rx_ampdu_apply(padapter); } -exit: return count; } + int proc_get_rx_ampdu_factor(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -2986,8 +3265,6 @@ int proc_get_en_fwps(struct seq_file *m, void *v) struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct registry_priv *pregpriv = &padapter->registrypriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); if (pregpriv) RTW_PRINT_SEL(m, "check_fw_ps = %d , 1:enable get FW PS state , 0: disable get FW PS state\n" @@ -3001,8 +3278,6 @@ ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t co struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct registry_priv *pregpriv = &padapter->registrypriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); char tmp[32]; u32 mode; @@ -3018,7 +3293,7 @@ ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t co int num = sscanf(tmp, "%d ", &mode); - if (pregpriv && mode < 2) { + if (num == 1 && pregpriv && mode < 2) { pregpriv->check_fw_ps = mode; RTW_INFO("pregpriv->check_fw_ps=%d\n", pregpriv->check_fw_ps); } @@ -3083,7 +3358,9 @@ void rtw_get_dft_phy_cap(void *sel, _adapter *adapter) #ifdef CONFIG_80211AC_VHT rtw_vht_use_default_setting(adapter); #endif + #ifdef CONFIG_80211N_HT rtw_dump_dft_phy_cap(sel, adapter); + #endif } void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter) @@ -3098,7 +3375,7 @@ void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter) RTW_PRINT_SEL(sel, "[DRV CAP] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index [15:8]*/ RTW_PRINT_SEL(sel, "[DRV CAP] Rx Path Num Index : %d\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index [7:0]*/ #endif - + #ifdef CONFIG_80211N_HT RTW_PRINT_SEL(sel, "[DRV CAP] STBC Capability : 0x%02x\n", pregistry_priv->stbc_cap); RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT STBC Tx*/ RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT STBC Rx*/ @@ -3110,6 +3387,7 @@ void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter) RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT LDPC Rx*/ RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT LDPC Tx*/ RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT LDPC Rx*/ + #endif /* CONFIG_80211N_HT */ #ifdef CONFIG_BEAMFORMING #if 0 RTW_PRINT_SEL(sel, "[DRV CAP] TxBF parameter : 0x%08x\n", phy_spec->txbf_param); @@ -3172,7 +3450,7 @@ ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t c int num = sscanf(tmp, "%d ", &mode); - if (pregpriv) { + if (num == 1 && pregpriv) { pregpriv->stbc_cap = mode; RTW_INFO("stbc_cap = 0x%02x\n", mode); } @@ -3212,7 +3490,7 @@ ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t co int num = sscanf(tmp, "%d ", &mode); - if (pregpriv && (mode == 0 || mode == 1 || mode == 2 || mode == 3)) { + if (num == 1 && pregpriv && (mode == 0 || mode == 1 || mode == 2 || mode == 3)) { pregpriv->rx_stbc = mode; printk("rx_stbc=%d\n", mode); } @@ -3253,7 +3531,7 @@ ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t c int num = sscanf(tmp, "%d ", &mode); - if (pregpriv) { + if (num == 1 && pregpriv) { pregpriv->ldpc_cap = mode; RTW_INFO("ldpc_cap = 0x%02x\n", mode); } @@ -3294,7 +3572,7 @@ ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t c int num = sscanf(tmp, "%d ", &mode); - if (pregpriv) { + if (num == 1 && pregpriv) { pregpriv->beamform_cap = mode; RTW_INFO("beamform_cap = 0x%02x\n", mode); } @@ -3369,7 +3647,8 @@ int proc_get_all_sta_info(struct seq_file *m, void *v) int i; _list *plist, *phead; - RTW_PRINT_SEL(m, "sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap); + RTW_MAP_DUMP_SEL(m, "sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); + RTW_MAP_DUMP_SEL(m, "tim_bitmap=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); @@ -3382,19 +3661,26 @@ int proc_get_all_sta_info(struct seq_file *m, void *v) plist = get_next(plist); - /* if(extra_arg == psta->aid) */ + /* if(extra_arg == psta->cmn.aid) */ { RTW_PRINT_SEL(m, "==============================\n"); - RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); RTW_PRINT_SEL(m, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); - RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); + RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); #ifdef CONFIG_80211N_HT RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); - RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" + , psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); RTW_PRINT_SEL(m, "tx_amsdu_enable = %d\n", psta->htpriv.tx_amsdu_enable); RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); #endif /* CONFIG_80211N_HT */ +#ifdef CONFIG_80211AC_VHT + RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m); + RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap); + RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len); +#endif RTW_PRINT_SEL(m, "sleepq_len=%d\n", psta->sleepq_len); RTW_PRINT_SEL(m, "sta_xmitpriv.vo_q_qcnt=%d\n", psta->sta_xmitpriv.vo_q.qcnt); RTW_PRINT_SEL(m, "sta_xmitpriv.vi_q_qcnt=%d\n", psta->sta_xmitpriv.vi_q.qcnt); @@ -3414,12 +3700,21 @@ int proc_get_all_sta_info(struct seq_file *m, void *v) #ifdef CONFIG_TDLS RTW_PRINT_SEL(m, "tdls_sta_state=0x%08x\n", psta->tdls_sta_state); RTW_PRINT_SEL(m, "PeerKey_Lifetime=%d\n", psta->TDLS_PeerKey_Lifetime); - RTW_PRINT_SEL(m, "rx_data_pkts=%llu\n", psta->sta_stats.rx_data_pkts); - RTW_PRINT_SEL(m, "rx_bytes=%llu\n", psta->sta_stats.rx_bytes); - RTW_PRINT_SEL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts); - RTW_PRINT_SEL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes); #endif /* CONFIG_TDLS */ + RTW_PRINT_SEL(m, "rx_data_uc_pkts=%llu\n", sta_rx_data_uc_pkts(psta)); + RTW_PRINT_SEL(m, "rx_data_mc_pkts=%llu\n", psta->sta_stats.rx_data_mc_pkts); + RTW_PRINT_SEL(m, "rx_data_bc_pkts=%llu\n", psta->sta_stats.rx_data_bc_pkts); + RTW_PRINT_SEL(m, "rx_uc_bytes=%llu\n", sta_rx_uc_bytes(psta)); + RTW_PRINT_SEL(m, "rx_mc_bytes=%llu\n", psta->sta_stats.rx_mc_bytes); + RTW_PRINT_SEL(m, "rx_bc_bytes=%llu\n", psta->sta_stats.rx_bc_bytes); + RTW_PRINT_SEL(m, "rx_avg_tp =%d (Bps)\n", psta->cmn.rx_moving_average_tp); + RTW_PRINT_SEL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts); + RTW_PRINT_SEL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes); + RTW_PRINT_SEL(m, "tx_avg_tp =%d (MBps)\n", psta->cmn.tx_moving_average_tp); +#ifdef CONFIG_RTW_80211K + RTW_PRINT_SEL(m, "rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(psta->rm_en_cap)); +#endif dump_st_ctl(m, &psta->st_ctl); if (STA_OP_WFD_MODE(psta)) @@ -3480,48 +3775,48 @@ int proc_get_best_channel(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0; - for (i = 0; i < pmlmeext->max_chan_nums && pmlmeext->channel_set[i].ChannelNum != 0; i++) { - if (pmlmeext->channel_set[i].ChannelNum == 1) + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { + if (rfctl->channel_set[i].ChannelNum == 1) index_24G = i; - if (pmlmeext->channel_set[i].ChannelNum == 36) + if (rfctl->channel_set[i].ChannelNum == 36) index_5G = i; } - for (i = 0; i < pmlmeext->max_chan_nums && pmlmeext->channel_set[i].ChannelNum != 0; i++) { + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { /* 2.4G */ - if (pmlmeext->channel_set[i].ChannelNum == 6) { - if (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_24G].rx_count) { + if (rfctl->channel_set[i].ChannelNum == 6) { + if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) { index_24G = i; - best_channel_24G = pmlmeext->channel_set[i].ChannelNum; + best_channel_24G = rfctl->channel_set[i].ChannelNum; } } /* 5G */ - if (pmlmeext->channel_set[i].ChannelNum >= 36 - && pmlmeext->channel_set[i].ChannelNum < 140) { + if (rfctl->channel_set[i].ChannelNum >= 36 + && rfctl->channel_set[i].ChannelNum < 140) { /* Find primary channel */ - if (((pmlmeext->channel_set[i].ChannelNum - 36) % 8 == 0) - && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) { + if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0) + && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { index_5G = i; - best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + best_channel_5G = rfctl->channel_set[i].ChannelNum; } } - if (pmlmeext->channel_set[i].ChannelNum >= 149 - && pmlmeext->channel_set[i].ChannelNum < 165) { + if (rfctl->channel_set[i].ChannelNum >= 149 + && rfctl->channel_set[i].ChannelNum < 165) { /* find primary channel */ - if (((pmlmeext->channel_set[i].ChannelNum - 149) % 8 == 0) - && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) { + if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0) + && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { index_5G = i; - best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + best_channel_5G = rfctl->channel_set[i].ChannelNum; } } #if 1 /* debug */ RTW_PRINT_SEL(m, "The rx cnt of channel %3d = %d\n", - pmlmeext->channel_set[i].ChannelNum, pmlmeext->channel_set[i].rx_count); + rfctl->channel_set[i].ChannelNum, rfctl->channel_set[i].rx_count); #endif } @@ -3535,7 +3830,7 @@ ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); char tmp[32]; if (count < 1) @@ -3548,8 +3843,8 @@ ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size if (buffer && !copy_from_user(tmp, buffer, count)) { int i; - for (i = 0; i < pmlmeext->max_chan_nums && pmlmeext->channel_set[i].ChannelNum != 0; i++) - pmlmeext->channel_set[i].rx_count = 0; + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) + rfctl->channel_set[i].rx_count = 0; RTW_INFO("set %s\n", "Clean Best Channel Count"); } @@ -3708,8 +4003,20 @@ int proc_get_sreset(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + if (psrtpriv->dbg_sreset_ctrl == _TRUE) { + RTW_PRINT_SEL(m, "self_dect_tx_cnt:%llu\n", psrtpriv->self_dect_tx_cnt); + RTW_PRINT_SEL(m, "self_dect_rx_cnt:%llu\n", psrtpriv->self_dect_rx_cnt); + RTW_PRINT_SEL(m, "self_dect_fw_cnt:%llu\n", psrtpriv->self_dect_fw_cnt); + RTW_PRINT_SEL(m, "tx_dma_status_cnt:%llu\n", psrtpriv->tx_dma_status_cnt); + RTW_PRINT_SEL(m, "rx_dma_status_cnt:%llu\n", psrtpriv->rx_dma_status_cnt); + RTW_PRINT_SEL(m, "self_dect_case:%d\n", psrtpriv->self_dect_case); + RTW_PRINT_SEL(m, "dbg_sreset_cnt:%d\n", pdbgpriv->dbg_sreset_cnt); + } return 0; } @@ -3717,6 +4024,8 @@ ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t cou { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; char tmp[32]; s32 trigger_point; @@ -3732,8 +4041,13 @@ ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t cou int num = sscanf(tmp, "%d", &trigger_point); + if (num < 1) + return count; + if (trigger_point == SRESET_TGP_NULL) rtw_hal_sreset_reset(padapter); + else if (trigger_point == SRESET_TGP_INFO) + psrtpriv->dbg_sreset_ctrl = _TRUE; else sreset_set_trigger_point(padapter, trigger_point); } @@ -3745,53 +4059,213 @@ ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t cou #ifdef CONFIG_PCI_HCI -int proc_get_pci_aspm(struct seq_file *m, void *v) +ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); - u8 tmp8 = 0; - u16 tmp16 = 0; - u32 tmp32 = 0; + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + struct pci_dev *bridge_pdev = pdev->bus->self; + char tmp[32] = { 0 }; + int num; - RTW_PRINT_SEL(m, "***** ASPM Capability *****\n"); + u32 reg = 0, value = 0; - pci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32); + if (count < 1) + return -EFAULT; - RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? "Enable" : "Disable"); - RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp32&BIT10) ? "Enable" : "Disable"); - RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp32&BIT11) ? "Enable" : "Disable"); + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } - tmp8 = rtw_hal_pci_l1off_capability(padapter); - RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable"); + if (buffer && !copy_from_user(tmp, buffer, count)) { - RTW_PRINT_SEL(m, "***** ASPM CTRL Reg *****\n"); + num = sscanf(tmp, "%x %x", ®, &value); + if (num != 2) { + RTW_INFO("invalid parameter!\n"); + return count; + } - pci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16); + if (reg >= 0x1000) { + RTW_INFO("invalid register!\n"); + return count; + } - RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? "Enable" : "Disable"); - RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp16&BIT0) ? "Enable" : "Disable"); - RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp16&BIT1) ? "Enable" : "Disable"); + if (value > 0xFF) { + RTW_INFO("invalid value! Only one byte\n"); + return count; + } - tmp8 = rtw_hal_pci_l1off_nic_support(padapter); - RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable"); + RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n", + FUNC_ADPT_ARG(padapter), reg, value); - RTW_PRINT_SEL(m, "***** ASPM Backdoor *****\n"); + pci_write_config_byte(bridge_pdev, reg, value); + } + return count; +} - tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); - RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp8 & BIT4) ? "Enable" : "Disable"); - tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f); - RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp8&BIT7) ? "Enable" : "Disable"); +int proc_get_pci_bridge_conf_space(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + struct pci_dev *bridge_pdev = pdev->bus->self; - tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); - RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp8 & BIT3) ? "Enable" : "Disable"); + u32 tmp[4] = { 0 }; + u32 i, j; - tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718); - RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", (tmp8 & BIT5) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "\n***** PCI Host Device Configuration Space*****\n\n"); + + for (i = 0; i < 0x1000; i += 0x10) { + for (j = 0 ; j < 4 ; j++) + pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j); + + RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF, + tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF, + tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF, + tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF); + } + return 0; +} + + +ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + + char tmp[32] = { 0 }; + int num; + + u32 reg = 0, value = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + num = sscanf(tmp, "%x %x", ®, &value); + + if (num != 2) { + RTW_INFO("invalid parameter!\n"); + return count; + } + + + if (reg >= 0x1000) { + RTW_INFO("invalid register!\n"); + return count; + } + + if (value > 0xFF) { + RTW_INFO("invalid value! Only one byte\n"); + return count; + } + + RTW_INFO(FUNC_ADPT_FMT ": register 0x%x value 0x%x\n", + FUNC_ADPT_ARG(padapter), reg, value); + + pci_write_config_byte(pdev, reg, value); + + + } + return count; +} + + +int proc_get_pci_conf_space(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + struct pci_dev *bridge_pdev = pdev->bus->self; + + u32 tmp[4] = { 0 }; + u32 i, j; + + RTW_PRINT_SEL(m, "\n***** PCI Device Configuration Space *****\n\n"); + + for (i = 0; i < 0x1000; i += 0x10) { + for (j = 0 ; j < 4 ; j++) + pci_read_config_dword(pdev, i + j * 4, tmp+j); + + RTW_PRINT_SEL(m, "%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF, + tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF, + tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF, + tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF); + } + + return 0; +} + + +int proc_get_pci_aspm(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); + u8 tmp8 = 0; + u16 tmp16 = 0; + u32 tmp32 = 0; + u8 l1_idle = 0; + + + RTW_PRINT_SEL(m, "***** ASPM Capability *****\n"); + + pci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32); + + RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp32&BIT10) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp32&BIT11) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_l1off_capability(padapter); + RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable"); + + RTW_PRINT_SEL(m, "***** ASPM CTRL Reg *****\n"); + + pci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16); + + RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp16&BIT0) ? "Enable" : "Disable"); + RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp16&BIT1) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_l1off_nic_support(padapter); + RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable"); + + RTW_PRINT_SEL(m, "***** ASPM Backdoor *****\n"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); + RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp8 & BIT4) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f); + l1_idle = tmp8 & 0x38; + RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp8&BIT7) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); + RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp8 & BIT3) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718); + RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", (tmp8 & BIT5) ? "Enable" : "Disable"); + + RTW_PRINT_SEL(m, "********* MISC **********\n"); + RTW_PRINT_SEL(m, "ASPM L1 Idel Time: 0x%x\n", l1_idle>>3); + RTW_PRINT_SEL(m, "*************************\n"); return 0; } @@ -3860,11 +4334,12 @@ int proc_get_tx_ring(struct seq_file *m, void *v) for (j = 0; j < pxmitpriv->txringcount[i]; j++) { #ifdef CONFIG_TRX_BD_ARCH struct tx_buf_desc *entry = &tx_ring->buf_desc[j]; + RTW_PRINT_SEL(m, " buf_desc[%03d]: %p\n", j, entry); #else struct tx_desc *entry = &tx_ring->desc[j]; + RTW_PRINT_SEL(m, " desc[%03d]: %p\n", j, entry); #endif - RTW_PRINT_SEL(m, " desc[%03d]: %p\n", j, entry); for (k = 0; k < sizeof(*entry) / 4; k++) { if ((k % 4) == 0) RTW_PRINT_SEL(m, " 0x%03x", k); @@ -3880,6 +4355,152 @@ int proc_get_tx_ring(struct seq_file *m, void *v) return 0; } + +#ifdef DBG_TXBD_DESC_DUMP +int proc_get_tx_ring_ext(struct seq_file *m, void *v) +{ + _irqL irqL; + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_tx_desc_backup *pbuf; + int i, j, k, idx; + + RTW_PRINT_SEL(m, "<<<< tx ring ext dump settings >>>>\n"); + RTW_PRINT_SEL(m, " - backup frame num: %d\n", TX_BAK_FRMAE_CNT); + RTW_PRINT_SEL(m, " - backup max. desc size: %d bytes\n", TX_BAK_DESC_LEN); + RTW_PRINT_SEL(m, " - backup data size: %d bytes\n\n", TX_BAK_DATA_LEN); + + if (!pxmitpriv->dump_txbd_desc) { + RTW_PRINT_SEL(m, "Dump function is disabled.\n"); + return 0; + } + + _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); + for (i = 0; i < HW_QUEUE_ENTRY; i++) { + struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i]; + + idx = rtw_get_tx_desc_backup(padapter, i, &pbuf); + + RTW_PRINT_SEL(m, "Tx ring[%d]", i); + switch (i) { + case 0: + RTW_PRINT_SEL(m, " (VO)\n"); + break; + case 1: + RTW_PRINT_SEL(m, " (VI)\n"); + break; + case 2: + RTW_PRINT_SEL(m, " (BE)\n"); + break; + case 3: + RTW_PRINT_SEL(m, " (BK)\n"); + break; + case 4: + RTW_PRINT_SEL(m, " (BCN)\n"); + break; + case 5: + RTW_PRINT_SEL(m, " (MGT)\n"); + break; + case 6: + RTW_PRINT_SEL(m, " (HIGH)\n"); + break; + case 7: + RTW_PRINT_SEL(m, " (TXCMD)\n"); + break; + default: + RTW_PRINT_SEL(m, " (?)\n"); + break; + } + + RTW_PRINT_SEL(m, " Entries: %d\n", TX_BAK_FRMAE_CNT); + RTW_PRINT_SEL(m, " Last idx: %d\n", idx); + + for (j = 0; j < TX_BAK_FRMAE_CNT; j++) { + RTW_PRINT_SEL(m, " desc[%03d]:\n", j); + + for (k = 0; k < (pbuf->tx_desc_size) / 4; k++) { + if ((k % 4) == 0) + RTW_PRINT_SEL(m, " 0x%03x", k); + + RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_desc)[k]); + + if ((k % 4) == 3) + RTW_PRINT_SEL(m, "\n"); + } + +#if 1 /* data dump */ + if (pbuf->tx_desc_size) { + RTW_PRINT_SEL(m, " data[%03d]:\n", j); + + for (k = 0; k < (TX_BAK_DATA_LEN) / 4; k++) { + if ((k % 4) == 0) + RTW_PRINT_SEL(m, " 0x%03x", k); + + RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_data_hdr)[k]); + + if ((k % 4) == 3) + RTW_PRINT_SEL(m, "\n"); + } + RTW_PRINT_SEL(m, "\n"); + } +#endif + + RTW_PRINT_SEL(m, " R/W pointer: %d/%d\n", pbuf->tx_bak_rp, pbuf->tx_bak_wp); + + pbuf = pbuf + 1; + } + RTW_PRINT_SEL(m, "\n"); + } + _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); + + return 0; +} + +ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + _irqL irqL; + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + char tmp[32]; + u32 reset = 0; + u32 dump = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%u %u", &dump, &reset); + + if (num != 2) { + RTW_INFO("invalid parameter!\n"); + return count; + } + + _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); + pxmitpriv->dump_txbd_desc = (BOOLEAN) dump; + + if (reset == 1) + rtw_tx_desc_backup_reset(); + + _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); + + } + + return count; +} + +#endif + #endif #ifdef CONFIG_WOWLAN @@ -3906,7 +4527,7 @@ int proc_get_pattern_info(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "\n======[Pattern Info.]======\n"); RTW_PRINT_SEL(m, "pattern number: %d\n", total); RTW_PRINT_SEL(m, "support default patterns: %c\n", - (pregistrypriv->default_patterns_en) ? 'Y' : 'N'); + (pwrpriv->default_patterns_en) ? 'Y' : 'N'); for (k = 0; k < total ; k++) { RTW_PRINT_SEL(m, "\npattern idx: %d\n", k); @@ -3943,6 +4564,7 @@ int proc_get_pattern_info(struct seq_file *m, void *v) return 0; } + ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { @@ -3990,6 +4612,62 @@ ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer, return count; } +int proc_get_wakeup_event(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *registry_par = &padapter->registrypriv; + + RTW_PRINT_SEL(m, "wakeup event: %#02x\n", registry_par->wakeup_event); + return 0; +} + +ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + struct registry_priv *registry_par = &padapter->registrypriv; + u32 wakeup_event = 0; + + u8 tmp[8] = {0}; + int ret = 0, num = 0; + u8 index = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) + num = sscanf(tmp, "%u", &wakeup_event); + else + return -EFAULT; + + if (num == 1 && wakeup_event <= 0x07) { + registry_par->wakeup_event = wakeup_event; + + if (wakeup_event & BIT(1)) + pwrctrlpriv->default_patterns_en = _TRUE; + else + pwrctrlpriv->default_patterns_en = _FALSE; + + rtw_wow_pattern_sw_reset(padapter); + + RTW_INFO("%s: wakeup_event: %#2x, default pattern: %d\n", + __func__, registry_par->wakeup_event, + pwrctrlpriv->default_patterns_en); + } else { + return -EINVAL; + } + + return count; +} + int proc_get_wakeup_reason(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -4039,14 +4717,28 @@ ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer, num = sscanf(tmp, "%u", &is_high_active); + if (num != 1) { + RTW_INFO("Invalid format\n"); + return count; + } + is_high_active = is_high_active == 0 ? 0 : 1; pwrpriv->is_high_active = is_high_active; rtw_ps_deny(padapter, PS_DENY_IOCTL); LeaveAllPowerSaveModeDirect(padapter); + + #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE + if (pwrpriv->is_high_active == 0) + rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX); + else + rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0); + #else val8 = (pwrpriv->is_high_active == 0) ? 1 : 0; + rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE); rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8); + #endif rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); RTW_INFO("set %s %d\n", "gpio_high_active", @@ -4090,7 +4782,7 @@ int proc_get_p2p_wowlan_info(struct seq_file *m, void *v) return 0; } #endif /* CONFIG_P2P_WOWLAN */ - +#ifdef CONFIG_BCN_CNT_CONFIRM_HDL int proc_get_new_bcn_max(struct seq_file *m, void *v) { extern int new_bcn_max; @@ -4117,7 +4809,7 @@ ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_ return count; } - +#endif #ifdef CONFIG_POWER_SAVING int proc_get_ps_info(struct seq_file *m, void *v) { @@ -4180,9 +4872,130 @@ int proc_get_ps_info(struct seq_file *m, void *v) RTW_PRINT_SEL(m, "=============================\n"); return 0; } -#endif /* CONFIG_POWER_SAVING */ -#ifdef CONFIG_TDLS +#ifdef CONFIG_WMMPS_STA +int proc_get_wmmps_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char *uapsd_max_sp_str=""; + + if (pregpriv){ + switch(pregpriv->uapsd_max_sp_len) { + case 0: + uapsd_max_sp_str = "NO_LIMIT"; + break; + case 1: + uapsd_max_sp_str = "TWO_MSDU"; + break; + case 2: + uapsd_max_sp_str = "FOUR_MSDU"; + break; + case 3: + uapsd_max_sp_str = "SIX_MSDU"; + break; + default: + uapsd_max_sp_str = "UNSPECIFIED"; + break; + } + + RTW_PRINT_SEL(m, "====== WMMPS_STA Info:======\n"); + RTW_PRINT_SEL(m, "uapsd_max_sp_len=0x%02x (%s)\n", pregpriv->uapsd_max_sp_len, uapsd_max_sp_str); + RTW_PRINT_SEL(m, "uapsd_ac_enable=0x%02x\n", pregpriv->uapsd_ac_enable); + RTW_PRINT_SEL(m, "BIT0 - AC_VO UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VO) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "BIT1 - AC_VI UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VI) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "BIT2 - AC_BK UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BK) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "BIT3 - AC_BE UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BE) ? "Enabled" : "Disabled"); + RTW_PRINT_SEL(m, "============================\n"); + } + + return 0; +} + +ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u8 uapsd_ac_setting; + u8 uapsd_max_sp_len_setting; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hhx", &uapsd_max_sp_len_setting, &uapsd_ac_setting); + + if (pregpriv) { + if (num >= 1) { + pregpriv->uapsd_max_sp_len = uapsd_max_sp_len_setting; + RTW_INFO("uapsd_max_sp_len = %d\n", pregpriv->uapsd_max_sp_len); + } + + if (num >= 2) { + pregpriv->uapsd_ac_enable = uapsd_ac_setting; + RTW_INFO("uapsd_ac_enable = 0x%02x\n", pregpriv->uapsd_ac_enable); + } + } + } + + return count; +} +#endif /* CONFIG_WMMPS_STA */ +#endif /* CONFIG_POWER_SAVING */ + +#ifdef CONFIG_TDLS +int proc_get_tdls_enable(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if (pregpriv) + RTW_PRINT_SEL(m, "TDLS is %s !\n", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "enabled" : "disabled"); + + return 0; +} + +ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 en_tdls = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &en_tdls); + + if (num == 1 && pregpriv) { + if (en_tdls > 0) + rtw_enable_tdls_func(padapter); + else + rtw_disable_tdls_func(padapter, _TRUE); + } + } + + return count; +} + static int proc_tdls_display_tdls_function_info(struct seq_file *m) { struct net_device *dev = m->private; @@ -4194,6 +5007,8 @@ static int proc_tdls_display_tdls_function_info(struct seq_file *m) int j = 0; RTW_PRINT_SEL(m, "============[TDLS Function Info]============\n"); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "_TRUE" : "_FALSE"); + RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE"); RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Prohibited", (ptdlsinfo->ap_prohibited == _TRUE) ? "_TRUE" : "_FALSE"); RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Channel Switch Prohibited", (ptdlsinfo->ch_switch_prohibited == _TRUE) ? "_TRUE" : "_FALSE"); RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Link Established", (ptdlsinfo->link_established == _TRUE) ? "_TRUE" : "_FALSE"); @@ -4257,8 +5072,6 @@ static int proc_tdls_display_tdls_function_info(struct seq_file *m) #endif RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Device Discovered", (ptdlsinfo->dev_discovered == _TRUE) ? "_TRUE" : "_FALSE"); - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (ptdlsinfo->tdls_enable == _TRUE) ? "_TRUE" : "_FALSE"); - RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE"); return 0; } @@ -4407,7 +5220,7 @@ static int proc_tdls_display_tdls_sta_info(struct seq_file *m) if (psta->tdls_sta_state != TDLS_STATE_NONE) { /* We got one TDLS sta info to show */ RTW_PRINT_SEL(m, "============[TDLS Peer STA Info: STA %d]============\n", ++NumOfTdlsStaToShow); - RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->hwaddr)); + RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->cmn.mac_addr)); RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS STA State"); SpaceBtwnItemAndValueTmp = 0; FirstMatchFound = _FALSE; @@ -4484,7 +5297,7 @@ static int proc_tdls_display_tdls_sta_info(struct seq_file *m) RTW_PRINT_SEL(m, "\n"); RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode"); - switch (psta->bw_mode) { + switch (psta->cmn.bw_mode) { case CHANNEL_WIDTH_20: RTW_PRINT_SEL(m, "%s\n", "20MHz"); break; @@ -4500,6 +5313,15 @@ static int proc_tdls_display_tdls_sta_info(struct seq_file *m) case CHANNEL_WIDTH_80_80: RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz"); break; + case CHANNEL_WIDTH_5: + RTW_PRINT_SEL(m, "%s\n", "5MHz"); + break; + case CHANNEL_WIDTH_10: + RTW_PRINT_SEL(m, "%s\n", "10MHz"); + break; + default: + RTW_PRINT_SEL(m, "(%d)%s\n", psta->cmn.bw_mode, "invalid"); + break; } RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy"); @@ -4586,7 +5408,6 @@ int proc_get_monitor(struct seq_file *m, void *v) struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; if (WIFI_MONITOR_STATE == get_fwstate(pmlmepriv)) { RTW_PRINT_SEL(m, "Monitor mode : Enable\n"); @@ -4819,11 +5640,11 @@ ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_ } if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) - && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && padapter->securitypriv.binstallBIPkey == _TRUE) { + && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) { RTW_INFO("STA:"MAC_FMT"\n", MAC_ARG(get_my_bssid(&(pmlmeinfo->network)))); /* TX unicast sa_query to AP */ issue_action_SA_Query(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, 0, (u8)key_type); - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && padapter->securitypriv.binstallBIPkey == _TRUE) { + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) { /* TX unicast sa_query to every client STA */ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); for (index = 0; index < NUM_STA; index++) { @@ -4835,7 +5656,7 @@ ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); plist = get_next(plist); - _rtw_memcpy(&mac_addr[psta->mac_id][0], psta->hwaddr, ETH_ALEN); + _rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN); } } _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); @@ -4908,6 +5729,7 @@ ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t /* TX unicast deauth to AP */ issue_deauth_11w(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, (u8)key_type); } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + u8 updated = _FALSE; if (key_type == 3) issue_deauth_11w(padapter, bc_addr, 0, IEEE80211W_RIGHT_KEY); @@ -4923,7 +5745,7 @@ ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); plist = get_next(plist); - _rtw_memcpy(&mac_addr[psta->mac_id][0], psta->hwaddr, ETH_ALEN); + _rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN); } } _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); @@ -4936,24 +5758,22 @@ ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t psta = rtw_get_stainfo(pstapriv, &mac_addr[index][0]); if (psta && key_type != IEEE80211W_WRONG_KEY && key_type != IEEE80211W_NO_KEY) { - u8 updated = _FALSE; - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; - updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE); + updated |= ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE); } _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - - associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); } RTW_INFO("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0])); } } } + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); } return count; @@ -5048,18 +5868,12 @@ int proc_get_mcc_policy_table(struct seq_file *m, void *v) return 0; } -ssize_t proc_set_mcc_policy_table(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[255]; - s32 mcc_policy_table_idx; - u32 mcc_duration; - u32 mcc_tsf_sync_offset; - u32 mcc_start_time_offset; - u32 mcc_interval; - s32 mcc_guard_offset0; - s32 mcc_guard_offset1; + u32 en_mcc = 0; if (NULL == buffer) { RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); @@ -5078,53 +5892,35 @@ ssize_t proc_set_mcc_policy_table(struct file *file, const char __user *buffer, } if (buffer && !copy_from_user(tmp, buffer, count)) { - #if 1 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); _adapter *iface = NULL; u8 i = 0; - int num = sscanf(tmp, "%d %u %u %u %u %d %d" - , &mcc_policy_table_idx, &mcc_duration, &mcc_tsf_sync_offset, &mcc_start_time_offset - , &mcc_interval, &mcc_guard_offset0, &mcc_guard_offset1); + int num = sscanf(tmp, "%u", &en_mcc); - if (num < 7) { - RTW_INFO(FUNC_ADPT_FMT ": input parameters < 7\n", FUNC_ADPT_ARG(padapter)); + if (num < 1) { + RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); return -EINVAL; } -#if 0 - RTW_INFO("mcc_policy_table_idx:%d\n", mcc_policy_table_idx); - RTW_INFO("mcc_duration:%d\n", mcc_duration); - RTW_INFO("mcc_tsf_sync_offset:%d\n", mcc_tsf_sync_offset); - RTW_INFO("mcc_start_time_offset:%d\n", mcc_start_time_offset); - RTW_INFO("mcc_interval:%d\n", mcc_interval); - RTW_INFO("mcc_guard_offset0:%d\n", mcc_guard_offset0); - RTW_INFO("mcc_guard_offset1:%d\n", mcc_guard_offset1); -#endif + + RTW_INFO("%s: en_mcc = %d\n", __func__, en_mcc); + for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (!iface) continue; - iface->registrypriv.rtw_mcc_policy_table_idx = mcc_policy_table_idx; - iface->registrypriv.rtw_mcc_duration = mcc_duration; - iface->registrypriv.rtw_mcc_tsf_sync_offset = mcc_tsf_sync_offset; - iface->registrypriv.rtw_mcc_start_time_offset = mcc_start_time_offset; - iface->registrypriv.rtw_mcc_interval = mcc_interval; - iface->registrypriv.rtw_mcc_guard_offset0 = mcc_guard_offset0; - iface->registrypriv.rtw_mcc_guard_offset1 = mcc_guard_offset1; + iface->registrypriv.en_mcc = en_mcc; } - - rtw_hal_mcc_update_switch_channel_policy_table(padapter); - #endif } return count; } -ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[255]; - u32 en_mcc = 0; + u32 enable_runtime_duration = 0, mcc_duration = 0; if (NULL == buffer) { RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter)); @@ -5143,23 +5939,26 @@ ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t } if (buffer && !copy_from_user(tmp, buffer, count)) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - _adapter *iface = NULL; - u8 i = 0; - int num = sscanf(tmp, "%u", &en_mcc); + int num = sscanf(tmp, "%u %u", &enable_runtime_duration, &mcc_duration); if (num < 1) { RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter)); return -EINVAL; } - RTW_INFO("%s: en_mcc = %d\n", __func__, en_mcc); + if (num > 2) { + RTW_INFO(FUNC_ADPT_FMT ": input parameters > 2\n", FUNC_ADPT_ARG(padapter)); + return -EINVAL; + } - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; - iface->registrypriv.en_mcc = en_mcc; + if (num >= 1) { + SET_MCC_RUNTIME_DURATION(padapter, enable_runtime_duration); + RTW_INFO("runtime duration:%s\n", enable_runtime_duration ? "enable":"disable"); + } + + if (num == 2) { + RTW_INFO("mcc duration:%d\n", mcc_duration); + rtw_set_mcc_duration_cmd(padapter, MCC_DURATION_DIRECET, mcc_duration); } } @@ -5467,7 +6266,10 @@ int proc_get_ack_timeout(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u8 ack_timeout_val, ack_timeout_val_cck; + u8 ack_timeout_val; +#ifdef CONFIG_RTL8821C + u8 ack_timeout_val_cck; +#endif ack_timeout_val = rtw_read8(padapter, REG_ACKTO); @@ -5524,4 +6326,396 @@ ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_ return count; } +ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + _adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter); + HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); + char tmp[32]; + u32 iqk_offload_enable = 0, ch_switch_offload_enable = 0; + + if (buffer == NULL) { + RTW_INFO("input buffer is NULL!\n"); + return -EFAULT; + } + + if (count < 1) { + RTW_INFO("input length is 0!\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + RTW_INFO("input length is too large\n"); + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%d %d", &iqk_offload_enable, &ch_switch_offload_enable); + + if (num < 2) { + RTW_INFO("input parameters < 1\n"); + return -EINVAL; + } + + if (hal->RegIQKFWOffload != iqk_offload_enable) { + hal->RegIQKFWOffload = iqk_offload_enable; + rtw_hal_update_iqk_fw_offload_cap(pri_adapter); + } + + if (hal->ch_switch_offload != ch_switch_offload_enable) + hal->ch_switch_offload = ch_switch_offload_enable; + } + + return count; +} + +int proc_get_fw_offload(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); + + + RTW_PRINT_SEL(m, "IQK FW offload:%s\n", hal->RegIQKFWOffload?"enable":"disable"); + RTW_PRINT_SEL(m, "Channel switch FW offload:%s\n", hal->ch_switch_offload?"enable":"disable"); + return 0; +} +#ifdef CONFIG_FW_HANDLE_TXBCN +extern void rtw_hal_set_fw_ap_bcn_offload_cmd(_adapter *adapter, bool fw_bcn_en, u8 tbtt_rpt_map); +ssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 fw_tbtt_rpt, fw_bcn_offload; + + + if (buffer == NULL) { + RTW_INFO("input buffer is NULL!\n"); + return -EFAULT; + } + + if (count < 1) { + RTW_INFO("input length is 0!\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + RTW_INFO("input length is too large\n"); + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%d %x",&fw_bcn_offload, &fw_tbtt_rpt); + + if (num < 2) { + RTW_INFO("input parameters < 2\n"); + return -EINVAL; + } + rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, fw_bcn_offload, fw_tbtt_rpt); + } + + return count; +} + +int proc_get_fw_tbtt_rpt(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + RTW_PRINT_SEL(m, "FW BCN offload:%s\n", dvobj->fw_bcn_offload ? "enable" : "disable"); + RTW_PRINT_SEL(m, "FW TBTT RPT:%x\n", dvobj->vap_tbtt_rpt_map); + return 0; +} + +#endif + +#ifdef CONFIG_DBG_RF_CAL +int proc_get_iqk_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + return 0; +} + +ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 recovery, clear, segment; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d %d %d", &recovery, &clear, &segment); + + if (num != 3) { + RTW_INFO("Invalid format\n"); + return count; + } + + rtw_hal_iqk_test(padapter, recovery, clear, segment); + } + + return count; + +} + +int proc_get_lck_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + return 0; +} + +ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 trigger; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d", &trigger); + + if (num != 1) { + RTW_INFO("Invalid format\n"); + return count; + } + + rtw_hal_lck_test(padapter); + } + + return count; +} +#endif /* CONFIG_DBG_RF_CAL */ + +#ifdef CONFIG_LPS_CHK_BY_TP +ssize_t proc_set_lps_chk_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + char tmp[32]; + u32 enable = 0; + u32 lps_tx_tp = 0, lps_rx_tp = 0, lps_bi_tp = 0; + int lps_chk_cnt_th = 0; + u32 lps_tx_pkts = 0, lps_rx_pkts = 0; + + if (buffer == NULL) { + RTW_INFO("input buffer is NULL!\n"); + return -EFAULT; + } + + if (count < 1) { + RTW_INFO("input length is 0!\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + RTW_INFO("input length is too large\n"); + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%u %u %u %u %d %u %u", + &enable, &lps_tx_tp, &lps_rx_tp, &lps_bi_tp, + &lps_chk_cnt_th, &lps_tx_pkts, &lps_rx_pkts); + + if (num < 1) { + RTW_INFO("input parameters < 1\n"); + return -EINVAL; + } + pwrpriv->lps_chk_by_tp = enable; + + if (lps_tx_tp) { + pwrpriv->lps_tx_tp_th = lps_tx_tp; + pwrpriv->lps_rx_tp_th = lps_tx_tp; + pwrpriv->lps_bi_tp_th = lps_tx_tp; + } + if (lps_rx_tp) + pwrpriv->lps_rx_tp_th = lps_rx_tp; + if (lps_bi_tp) + pwrpriv->lps_bi_tp_th = lps_bi_tp; + + if (lps_chk_cnt_th) + pwrpriv->lps_chk_cnt_th = lps_chk_cnt_th; + + if (lps_tx_pkts) + pwrpriv->lps_tx_pkts = lps_tx_pkts; + + if (lps_rx_pkts) + pwrpriv->lps_rx_pkts = lps_rx_pkts; + + RTW_INFO("%s lps_chk_by_tp:%s , lps_tx_tp_th:%d, lps_tx_tp_th:%d, lps_bi_tp:%d\n", + __func__, pwrpriv->lps_chk_by_tp ? "Y" : "N", + pwrpriv->lps_tx_tp_th, pwrpriv->lps_tx_tp_th, pwrpriv->lps_bi_tp_th); + RTW_INFO("%s lps_chk_cnt_th:%d , lps_tx_pkts:%d, lps_rx_pkts:%d\n", + __func__, pwrpriv->lps_chk_cnt_th, pwrpriv->lps_tx_pkts, pwrpriv->lps_rx_pkts); + } + + return count; +} + +int proc_get_lps_chk_tp(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + + RTW_PRINT_SEL(m, "LPS chk by tp - %s\n", pwrpriv->lps_chk_by_tp ? "enable" : "disable"); + RTW_PRINT_SEL(m, "LPS Tx TP TH - %d(Mbps)\n", pwrpriv->lps_tx_tp_th); + RTW_PRINT_SEL(m, "LPS Rx TP TH - %d(Mbps)\n", pwrpriv->lps_rx_tp_th); + RTW_PRINT_SEL(m, "LPS BI TP TH - %d(Mbps)\n", pwrpriv->lps_bi_tp_th); + + RTW_PRINT_SEL(m, "LPS CHK CNT - %d\n", pwrpriv->lps_chk_cnt_th); + RTW_PRINT_SEL(m, "LPS Tx PKTs - %d\n", pwrpriv->lps_tx_pkts); + RTW_PRINT_SEL(m, "LPS Rx PKTs - %d\n", pwrpriv->lps_rx_pkts); + return 0; +} +#endif + #endif /* CONFIG_PROC_DEBUG */ +#define RTW_BUFDUMP_BSIZE 16 +#if 1 +inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring, + bool _idx_show, const u8 *_hexdata, int _hexdatalen) +{ +#ifdef CONFIG_RTW_DEBUG + int __i; + u8 *ptr = (u8 *)_hexdata; + + if (_loglevel <= rtw_drv_log_level) { + if (_titlestring) { + if (sel == RTW_DBGDUMP) + RTW_PRINT(""); + _RTW_PRINT_SEL(sel, "%s", _titlestring); + if (_hexdatalen >= RTW_BUFDUMP_BSIZE) + _RTW_PRINT_SEL(sel, "\n"); + } + + for (__i = 0; __i < _hexdatalen; __i++) { + if (((__i % RTW_BUFDUMP_BSIZE) == 0) && (_hexdatalen >= RTW_BUFDUMP_BSIZE)) { + if (sel == RTW_DBGDUMP) + RTW_PRINT(""); + if (_idx_show) + _RTW_PRINT_SEL(sel, "0x%03X: ", __i); + } + _RTW_PRINT_SEL(sel, "%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); + if ((__i + 1 < _hexdatalen) && ((__i + 1) % RTW_BUFDUMP_BSIZE) == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + _RTW_PRINT_SEL(sel, "\n"); + } +#endif +} +#else +inline void _RTW_STR_DUMP_SEL(void *sel, char *str_out) +{ + if (sel == RTW_DBGDUMP) + _dbgdump("%s\n", str_out); + #if defined(_seqdump) + else + _seqdump(sel, "%s\n", str_out); + #endif /*_seqdump*/ +} +inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring, + bool _idx_show, u8 *_hexdata, int _hexdatalen) +{ + int __i, len; + int __j, idx; + int block_num, remain_byte; + char str_out[128] = {'\0'}; + char str_val[32] = {'\0'}; + char *p = NULL; + u8 *ptr = (u8 *)_hexdata; + + if (_loglevel <= rtw_drv_log_level) { + /*dump title*/ + p = &str_out[0]; + if (_titlestring) { + if (sel == RTW_DBGDUMP) { + len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX); + strncpy(p, str_val, len); + p += len; + } + len = snprintf(str_val, sizeof(str_val), "%s", _titlestring); + strncpy(p, str_val, len); + p += len; + } + if (p != &str_out[0]) { + _RTW_STR_DUMP_SEL(sel, str_out); + _rtw_memset(&str_out, '\0', sizeof(str_out)); + } + + /*dump buffer*/ + block_num = _hexdatalen / RTW_BUFDUMP_BSIZE; + remain_byte = _hexdatalen % RTW_BUFDUMP_BSIZE; + for (__i = 0; __i < block_num; __i++) { + p = &str_out[0]; + if (sel == RTW_DBGDUMP) { + len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX); + strncpy(p, str_val, len); + p += len; + } + if (_idx_show) { + len = snprintf(str_val, sizeof(str_val), "0x%03X: ", __i * RTW_BUFDUMP_BSIZE); + strncpy(p, str_val, len); + p += len; + } + for (__j =0; __j < RTW_BUFDUMP_BSIZE; __j++) { + idx = __i * RTW_BUFDUMP_BSIZE + __j; + len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__j + 1) % 4) == 0) ? " " : " "); + strncpy(p, str_val, len); + p += len; + } + _RTW_STR_DUMP_SEL(sel, str_out); + _rtw_memset(&str_out, '\0', sizeof(str_out)); + } + + p = &str_out[0]; + if ((sel == RTW_DBGDUMP) && remain_byte) { + len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX); + strncpy(p, str_val, len); + p += len; + } + if (_idx_show && remain_byte) { + len = snprintf(str_val, sizeof(str_val), "0x%03X: ", block_num * RTW_BUFDUMP_BSIZE); + strncpy(p, str_val, len); + p += len; + } + for (__i = 0; __i < remain_byte; __i++) { + idx = block_num * RTW_BUFDUMP_BSIZE + __i; + len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__i + 1) % 4) == 0) ? " " : " "); + strncpy(p, str_val, len); + p += len; + } + _RTW_STR_DUMP_SEL(sel, str_out); + } +} + +#endif diff --git a/core/rtw_eeprom.c b/core/rtw_eeprom.c index d7bca03..d48996e 100644 --- a/core/rtw_eeprom.c +++ b/core/rtw_eeprom.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_EEPROM_C_ #include diff --git a/core/rtw_ieee80211.c b/core/rtw_ieee80211.c index 532b2f6..c867197 100644 --- a/core/rtw_ieee80211.c +++ b/core/rtw_ieee80211.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _IEEE80211_C #ifdef CONFIG_PLATFORM_INTEL_BYT @@ -132,6 +127,19 @@ int rtw_get_bit_value_from_ieee_value(u8 val) } return 0; } +uint rtw_get_cckrate_size(u8 *rate, u32 rate_length) +{ + int i = 0; + while(i < rate_length){ + RTW_DBG("%s, rate[%d]=%u\n", __FUNCTION__, i, rate[i]); + if (((rate[i] & 0x7f) == 2) || ((rate[i] & 0x7f) == 4) || + ((rate[i] & 0x7f) == 11) || ((rate[i] & 0x7f) == 22)) + i++; + else + break; + } + return i; +} uint rtw_is_cckrates_included(u8 *rate) { @@ -196,7 +204,7 @@ u8 *rtw_set_ie u8 *pbuf, sint index, uint len, - u8 *source, + const u8 *source, uint *frlen /* frame length */ ) { @@ -207,7 +215,8 @@ u8 *rtw_set_ie if (len > 0) _rtw_memcpy((void *)(pbuf + 2), (void *)source, len); - *frlen = *frlen + (len + 2); + if (frlen) + *frlen = *frlen + (len + 2); return pbuf + len + 2; } @@ -228,9 +237,9 @@ inline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset) if (ch_offset == SCN) return HAL_PRIME_CHNL_OFFSET_DONT_CARE; else if (ch_offset == SCA) - return HAL_PRIME_CHNL_OFFSET_UPPER; - else if (ch_offset == SCB) return HAL_PRIME_CHNL_OFFSET_LOWER; + else if (ch_offset == SCB) + return HAL_PRIME_CHNL_OFFSET_UPPER; return HAL_PRIME_CHNL_OFFSET_DONT_CARE; } @@ -240,9 +249,9 @@ inline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset) if (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) return SCN; else if (ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) - return SCB; - else if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) return SCA; + else if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) + return SCB; return SCN; } @@ -268,10 +277,10 @@ inline u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, /*---------------------------------------------------------------------------- index: the information element id index, limit is the limit for search -----------------------------------------------------------------------------*/ -u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) +u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit) { sint tmp, i; - u8 *p; + const u8 *p; if (limit < 1) { return NULL; } @@ -282,7 +291,7 @@ u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) while (1) { if (*p == index) { *len = *(p + 1); - return p; + return (u8 *)p; } else { tmp = *(p + 1); p += (tmp + 2); @@ -306,17 +315,17 @@ u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) * * Returns: The address of the specific IE found, or NULL */ -u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen) +u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen) { uint cnt; - u8 *target_ie = NULL; + const u8 *target_ie = NULL; if (ielen) *ielen = 0; if (!in_ie || in_len <= 0) - return target_ie; + return (u8 *)target_ie; cnt = 0; @@ -338,7 +347,7 @@ u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, u } - return target_ie; + return (u8 *)target_ie; } /** @@ -385,6 +394,52 @@ int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 o return ret; } + /* Returns: remove size OR _FAIL: not updated*/ +int rtw_remove_ie_g_rate(u8 *ie, uint *ie_len, uint offset, u8 eid) +{ + int ret = _FAIL; + u8 *tem_target_ie; + u8 *target_ie; + u32 target_ielen,temp_target_ielen,cck_rate_size,rm_size; + u8 *start; + uint search_len; + u8 *remain_ies; + uint remain_len; + if (!ie || !ie_len || *ie_len <= offset) + goto exit; + + start = ie + offset; + search_len = *ie_len - offset; + + while (1) { + tem_target_ie=rtw_get_ie(start,eid,&temp_target_ielen,search_len); + + /*if(tem_target_ie) + RTW_INFO("%s, tem_target_ie=%u\n", __FUNCTION__,*tem_target_ie);*/ + if (tem_target_ie && temp_target_ielen) { + cck_rate_size = rtw_get_cckrate_size((tem_target_ie+2), temp_target_ielen); + rm_size = temp_target_ielen - cck_rate_size; + RTW_DBG("%s,cck_rate_size=%u rm_size=%u\n", __FUNCTION__, cck_rate_size, rm_size); + temp_target_ielen=temp_target_ielen + 2;/*org size of Supposrted Rates(include id + length)*/ + /*RTW_INFO("%s, temp_target_ielen=%u\n", __FUNCTION__,temp_target_ielen);*/ + remain_ies = tem_target_ie + temp_target_ielen; + remain_len = search_len - (remain_ies - start); + target_ielen=cck_rate_size;/*discount g mode rate 6, 9 12,18Mbps,id , length*/ + *(tem_target_ie+1)=target_ielen;/*set new length to Supposrted Rates*/ + target_ie=tem_target_ie+target_ielen + 2;/*set target ie to address of rate 6Mbps */ + + _rtw_memmove(target_ie, remain_ies, remain_len); + *ie_len = *ie_len - rm_size; + ret = rm_size; + + start = target_ie; + search_len = remain_len; + } else + break; + } +exit: + return ret; +} void rtw_set_supported_rate(u8 *SupportedRates, uint mode) { @@ -500,7 +555,7 @@ int rtw_generate_ie(struct registry_priv *pregistrypriv) #ifdef CONFIG_80211N_HT /* HT Cap. */ - if (((pregistrypriv->wireless_mode & WIRELESS_11_5N) || (pregistrypriv->wireless_mode & WIRELESS_11_24N)) + if (is_supported_ht(pregistrypriv->wireless_mode) && (pregistrypriv->ht_enable == _TRUE)) { /* todo: */ } @@ -679,79 +734,150 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis } -int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x) +int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info) { - int i, ret = _SUCCESS; - int left, count; - u8 *pos; - u8 SUITE_1X[4] = {0x00, 0x0f, 0xac, 0x01}; + const u8 *pos = ie; + u16 cnt; - if (rsn_ie_len <= 0) { - /* No RSN IE - fail silently */ - return _FAIL; - } + _rtw_memset(info, 0, sizeof(struct rsne_info)); + if (ie + ie_len < pos + 4) + goto err; - if ((*rsn_ie != _WPA2_IE_ID_) || (*(rsn_ie + 1) != (u8)(rsn_ie_len - 2))) - return _FAIL; + if (*ie != WLAN_EID_RSN || *(ie + 1) != ie_len - 2) + goto err; + pos += 2 + 2; - pos = rsn_ie; + /* Group CS */ + if (ie + ie_len < pos + 4) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + info->gcs = (u8 *)pos; pos += 4; - left = rsn_ie_len - 4; - /* group_cipher */ - if (left >= RSN_SELECTOR_LEN) { + /* Pairwise CS */ + if (ie + ie_len < pos + 2) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + cnt = RTW_GET_LE16(pos); + pos += 2; + if (ie + ie_len < pos + 4 * cnt) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + info->pcs_cnt = cnt; + info->pcs_list = (u8 *)pos; + pos += 4 * cnt; - *group_cipher = rtw_get_wpa2_cipher_suite(pos); + /* AKM */ + if (ie + ie_len < pos + 2) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + cnt = RTW_GET_LE16(pos); + pos += 2; + if (ie + ie_len < pos + 4 * cnt) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + info->akm_cnt = cnt; + info->akm_list = (u8 *)pos; + pos += 4 * cnt; - pos += RSN_SELECTOR_LEN; - left -= RSN_SELECTOR_LEN; + /* RSN cap */ + if (ie + ie_len < pos + 2) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + info->cap = (u8 *)pos; + pos += 2; - } else if (left > 0) { - return _FAIL; + /* PMKID */ + if (ie + ie_len < pos + 2) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + cnt = RTW_GET_LE16(pos); + pos += 2; + if (ie + ie_len < pos + 16 * cnt) { + if (ie + ie_len != pos) + goto err; + goto exit; } + info->pmkid_cnt = cnt; + info->pmkid_list = (u8 *)pos; + pos += 16 * cnt; - /* pairwise_cipher */ - if (left >= 2) { - /* count = le16_to_cpu(*(u16*)pos); */ - count = RTW_GET_LE16(pos); - pos += 2; - left -= 2; + /* Group Mgmt CS */ + if (ie + ie_len < pos + 4) { + if (ie + ie_len != pos) + goto err; + goto exit; + } + info->gmcs = (u8 *)pos; - if (count == 0 || left < count * RSN_SELECTOR_LEN) { - return _FAIL; - } +exit: + return _SUCCESS; - for (i = 0; i < count; i++) { - *pairwise_cipher |= rtw_get_wpa2_cipher_suite(pos); +err: + info->err = 1; + return _FAIL; +} - pos += RSN_SELECTOR_LEN; - left -= RSN_SELECTOR_LEN; - } +int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x, u8 *mfp_opt) +{ + struct rsne_info info; + int i, ret = _SUCCESS; + u8 SUITE_1X[4] = {0x00, 0x0f, 0xac, 0x01}; - } else if (left == 1) { + ret = rtw_rsne_info_parse(rsn_ie, rsn_ie_len, &info); + if (ret != _SUCCESS) + goto exit; - return _FAIL; + if (group_cipher) { + if (info.gcs) + *group_cipher = rtw_get_wpa2_cipher_suite(info.gcs); + else + *group_cipher = 0; + } + + if (pairwise_cipher) { + *pairwise_cipher = 0; + for (i = 0; i < info.pcs_cnt; i++) + *pairwise_cipher |= rtw_get_wpa2_cipher_suite(info.pcs_list + 4 * i); } if (is_8021x) { - if (left >= 6) { - pos += 2; - if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) { - *is_8021x = 1; - } - } + *is_8021x = 0; + /* here only check the first AKM suite */ + if (info.akm_cnt && _rtw_memcmp(SUITE_1X, info.akm_list, 4) == _TRUE) + *is_8021x = 1; } - return ret; + if (mfp_opt) { + *mfp_opt = MFP_NO; + if (info.cap) + *mfp_opt = GET_RSN_CAP_MFP_OPTION(info.cap); + } +exit: + return ret; } /* #ifdef CONFIG_WAPI_SUPPORT */ int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len) { int len = 0; - u8 authmode, i; + u8 authmode; uint cnt; u8 wapi_oui1[4] = {0x0, 0x14, 0x72, 0x01}; u8 wapi_oui2[4] = {0x0, 0x14, 0x72, 0x02}; @@ -794,7 +920,7 @@ int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len) int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len) { - u8 authmode, sec_idx, i; + u8 authmode, sec_idx; u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01}; uint cnt; @@ -853,23 +979,26 @@ u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen) return match; } -u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, u8 frame_type) +u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type) { u8 *wps = NULL; RTW_INFO("[%s] frame_type = %d\n", __FUNCTION__, frame_type); switch (frame_type) { - case 1: - case 3: { + case BSS_TYPE_BCN: + case BSS_TYPE_PROB_RSP: { /* Beacon or Probe Response */ wps = rtw_get_wps_ie(in_ie + _PROBERSP_IE_OFFSET_, in_len - _PROBERSP_IE_OFFSET_, wps_ie, wps_ielen); break; } - case 2: { + case BSS_TYPE_PROB_REQ: { /* Probe Request */ wps = rtw_get_wps_ie(in_ie + _PROBEREQ_IE_OFFSET_ , in_len - _PROBEREQ_IE_OFFSET_ , wps_ie, wps_ielen); break; } + default: + case BSS_TYPE_UNDEF: + break; } return wps; } @@ -883,10 +1012,10 @@ u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps * * Returns: The address of the WPS IE found, or NULL */ -u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) +u8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) { uint cnt; - u8 *wpsie_ptr = NULL; + const u8 *wpsie_ptr = NULL; u8 eid, wps_oui[4] = {0x00, 0x50, 0xf2, 0x04}; if (wps_ielen) @@ -894,11 +1023,11 @@ u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) if (!in_ie) { rtw_warn_on(1); - return wpsie_ptr; + return (u8 *)wpsie_ptr; } if (in_len <= 0) - return wpsie_ptr; + return (u8 *)wpsie_ptr; cnt = 0; @@ -925,7 +1054,7 @@ u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) } - return wpsie_ptr; + return (u8 *)wpsie_ptr; } /** @@ -1236,6 +1365,28 @@ ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, elems->vht_op_mode_notify = pos; elems->vht_op_mode_notify_len = elen; break; + case _EID_RRM_EN_CAP_IE_: + elems->rm_en_cap = pos; + elems->rm_en_cap_len = elen; + break; +#ifdef CONFIG_RTW_MESH + case WLAN_EID_PREQ: + elems->preq = pos; + elems->preq_len = elen; + break; + case WLAN_EID_PREP: + elems->prep = pos; + elems->prep_len = elen; + break; + case WLAN_EID_PERR: + elems->perr = pos; + elems->perr_len = elen; + break; + case WLAN_EID_RANN: + elems->rann = pos; + elems->rann_len = elen; + break; +#endif default: unknown++; if (!show_errors) @@ -1433,40 +1584,70 @@ void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr) } #ifdef CONFIG_80211N_HT -void dump_ht_cap_ie_content(void *sel, u8 *buf, u32 buf_len) +void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len) { - if (buf_len != 26) { - RTW_PRINT_SEL(sel, "Invalid HT capability IE len:%d != %d\n", buf_len, 26); + if (buf_len != HT_CAP_IE_LEN) { + RTW_PRINT_SEL(sel, "Invalid HT capability IE len:%d != %d\n", buf_len, HT_CAP_IE_LEN); return; } - RTW_PRINT_SEL(sel, "HT Capabilities Info:%02x%02x\n", *(buf), *(buf + 1)); + RTW_PRINT_SEL(sel, "cap_info:%02x%02x:%s\n", *(buf), *(buf + 1) + , GET_HT_CAP_ELE_CHL_WIDTH(buf) ? " 40MHz" : " 20MHz"); RTW_PRINT_SEL(sel, "A-MPDU Parameters:"HT_AMPDU_PARA_FMT"\n" , HT_AMPDU_PARA_ARG(HT_CAP_ELE_AMPDU_PARA(buf))); RTW_PRINT_SEL(sel, "Supported MCS Set:"HT_SUP_MCS_SET_FMT"\n" , HT_SUP_MCS_SET_ARG(HT_CAP_ELE_SUP_MCS_SET(buf))); } -void dump_ht_cap_ie(void *sel, u8 *ie, u32 ie_len) +void dump_ht_cap_ie(void *sel, const u8 *ie, u32 ie_len) { - u8 *pos = (u8 *)ie; - u16 id; - u16 len; - - u8 *ht_cap_ie; + const u8 *ht_cap_ie; sint ht_cap_ielen; - ht_cap_ie = rtw_get_ie(ie, _HT_CAPABILITY_IE_, &ht_cap_ielen, ie_len); + ht_cap_ie = rtw_get_ie(ie, WLAN_EID_HT_CAP, &ht_cap_ielen, ie_len); if (!ie || ht_cap_ie != ie) return; dump_ht_cap_ie_content(sel, ht_cap_ie + 2, ht_cap_ielen); } + +const char *const _ht_sc_offset_str[] = { + "SCN", + "SCA", + "SC-RSVD", + "SCB", +}; + +void dump_ht_op_ie_content(void *sel, const u8 *buf, u32 buf_len) +{ + if (buf_len != HT_OP_IE_LEN) { + RTW_PRINT_SEL(sel, "Invalid HT operation IE len:%d != %d\n", buf_len, HT_OP_IE_LEN); + return; + } + + RTW_PRINT_SEL(sel, "ch:%u%s %s\n" + , GET_HT_OP_ELE_PRI_CHL(buf) + , GET_HT_OP_ELE_STA_CHL_WIDTH(buf) ? "" : " 20MHz only" + , ht_sc_offset_str(GET_HT_OP_ELE_2ND_CHL_OFFSET(buf)) + ); +} + +void dump_ht_op_ie(void *sel, const u8 *ie, u32 ie_len) +{ + const u8 *ht_op_ie; + sint ht_op_ielen; + + ht_op_ie = rtw_get_ie(ie, WLAN_EID_HT_OPERATION, &ht_op_ielen, ie_len); + if (!ie || ht_op_ie != ie) + return; + + dump_ht_op_ie_content(sel, ht_op_ie + 2, ht_op_ielen); +} #endif /* CONFIG_80211N_HT */ -void dump_ies(void *sel, u8 *buf, u32 buf_len) +void dump_ies(void *sel, const u8 *buf, u32 buf_len) { - u8 *pos = (u8 *)buf; + const u8 *pos = buf; u8 id, len; while (pos - buf + 1 < buf_len) { @@ -1476,6 +1657,11 @@ void dump_ies(void *sel, u8 *buf, u32 buf_len) RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u\n", __FUNCTION__, id, len); #ifdef CONFIG_80211N_HT dump_ht_cap_ie(sel, pos, len + 2); + dump_ht_op_ie(sel, pos, len + 2); +#endif +#ifdef CONFIG_80211AC_VHT + dump_vht_cap_ie(sel, pos, len + 2); + dump_vht_op_ie(sel, pos, len + 2); #endif dump_wps_ie(sel, pos, len + 2); #ifdef CONFIG_P2P @@ -1489,13 +1675,13 @@ void dump_ies(void *sel, u8 *buf, u32 buf_len) } } -void dump_wps_ie(void *sel, u8 *ie, u32 ie_len) +void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len) { - u8 *pos = (u8 *)ie; + const u8 *pos = ie; u16 id; u16 len; - u8 *wps_ie; + const u8 *wps_ie; uint wps_ielen; wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen); @@ -1521,8 +1707,10 @@ void dump_wps_ie(void *sel, u8 *ie, u32 ie_len) * @ch: pointer of ch, used as output * @bw: pointer of bw, used as output * @offset: pointer of offset, used as output + * @ht: check HT IEs + * @vht: check VHT IEs, if true imply ht is true */ -void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset) +void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht) { u8 *p; int ie_len; @@ -1536,7 +1724,7 @@ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset) *ch = *(p + 2); #ifdef CONFIG_80211N_HT - { + if (ht || vht) { u8 *ht_cap_ie, *ht_op_ie; int ht_cap_ielen, ht_op_ielen; @@ -1569,44 +1757,29 @@ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset) } } } - } -#endif /* CONFIG_80211N_HT */ + #ifdef CONFIG_80211AC_VHT - { - u8 *vht_op_ie; - int vht_op_ielen; - - vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len); - if (vht_op_ie && vht_op_ielen) { - /* enable VHT 80 before check enable HT40 or not */ - if (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1) { - /* for HT40, enable VHT80 */ - if (*bw == CHANNEL_WIDTH_40) + if (vht) { + u8 *vht_op_ie; + int vht_op_ielen; + + vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len); + if (vht_op_ie && vht_op_ielen) { + if (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1) *bw = CHANNEL_WIDTH_80; - /* for HT20, enable VHT20 */ - else if (*bw == CHANNEL_WIDTH_20) { - /* modify VHT OP IE */ - SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0); - /* reset to 0 for VHT20 */ - SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0); - SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0); - } - } else { - /* - VHT OP WIDTH = 0 under HT20/HT40 - if REGSTY_BW_5G(pregistrypriv) < CHANNEL_WIDTH_80 in rtw_build_vht_operation_ie - */ } } +#endif /* CONFIG_80211AC_VHT */ + } -#endif +#endif /* CONFIG_80211N_HT */ } -void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset) +void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht) { rtw_ies_get_chbw(bss->IEs + sizeof(NDIS_802_11_FIXED_IEs) , bss->IELength - sizeof(NDIS_802_11_FIXED_IEs) - , ch, bw, offset); + , ch, bw, offset, ht, vht); if (*ch == 0) *ch = bss->Configuration.DSConfig; @@ -1673,7 +1846,7 @@ void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80) *req_offset = *g_offset; else if (*g_bw == CHANNEL_WIDTH_20) - *req_offset = rtw_get_offset_by_ch(*req_ch); + rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset); if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { RTW_ERR("%s req 80MHz BW without offset, down to 20MHz\n", __func__); @@ -1685,7 +1858,7 @@ void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80) *req_offset = *g_offset; else if (*g_bw == CHANNEL_WIDTH_20) - *req_offset = rtw_get_offset_by_ch(*req_ch); + rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset); if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { RTW_ERR("%s req 40MHz BW without offset, down to 20MHz\n", __func__); @@ -1718,7 +1891,7 @@ u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len) PNDIS_802_11_VARIABLE_IEs pIE; u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 }; int i = 0; - int j = 0, len = 0; + int len = 0; while (i < in_len) { pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie + i); @@ -1773,13 +1946,13 @@ int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie) return 0; } -void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len) +void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len) { - u8 *pos = (u8 *)ie; + const u8 *pos = ie; u8 id; u16 len; - u8 *p2p_ie; + const u8 *p2p_ie; uint p2p_ielen; p2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen); @@ -1807,10 +1980,10 @@ void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len) * * Returns: The address of the P2P IE found, or NULL */ -u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen) +u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen) { uint cnt; - u8 *p2p_ie_ptr = NULL; + const u8 *p2p_ie_ptr = NULL; u8 eid, p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09}; if (p2p_ielen) @@ -1818,11 +1991,11 @@ u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen) if (!in_ie || in_len < 0) { rtw_warn_on(1); - return p2p_ie_ptr; + return (u8 *)p2p_ie_ptr; } if (in_len <= 0) - return p2p_ie_ptr; + return (u8 *)p2p_ie_ptr; cnt = 0; @@ -1849,7 +2022,7 @@ u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen) } - return p2p_ie_ptr; + return (u8 *)p2p_ie_ptr; } /** @@ -2117,13 +2290,13 @@ void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id) } } -void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len) +void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len) { - u8 *pos = (u8 *)ie; + const u8 *pos = ie; u8 id; u16 len; - u8 *wfd_ie; + const u8 *wfd_ie; uint wfd_ielen; wfd_ie = rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen); @@ -2151,10 +2324,10 @@ void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len) * * Returns: The address of the P2P IE found, or NULL */ -u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) +u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) { uint cnt; - u8 *wfd_ie_ptr = NULL; + const u8 *wfd_ie_ptr = NULL; u8 eid, wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A}; if (wfd_ielen) @@ -2162,11 +2335,11 @@ u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) if (!in_ie || in_len < 0) { rtw_warn_on(1); - return wfd_ie_ptr; + return (u8 *)wfd_ie_ptr; } if (in_len <= 0) - return wfd_ie_ptr; + return (u8 *)wfd_ie_ptr; cnt = 0; @@ -2193,7 +2366,7 @@ u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) } - return wfd_ie_ptr; + return (u8 *)wfd_ie_ptr; } /** @@ -2508,7 +2681,7 @@ int rtw_get_cipher_info(struct wlan_network *pnetwork) pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12); if (pbuf && (wpa_ielen > 0)) { - if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x)) { + if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x, NULL)) { pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher; pnetwork->BcnInfo.group_cipher = group_cipher; pnetwork->BcnInfo.is_8021x = is8021x; diff --git a/core/rtw_io.c b/core/rtw_io.c index 00f7a5a..159894a 100644 --- a/core/rtw_io.c +++ b/core/rtw_io.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* The purpose of rtw_io.c @@ -424,9 +419,13 @@ u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int ret = _rtw_write_port(adapter, addr, cnt, pmem); - if (ret == _SUCCESS) + if (ret == _SUCCESS) { ret = rtw_sctx_wait(&sctx, __func__); + if (ret != _SUCCESS) + pxmitbuf->sctx = NULL; + } + return ret; } @@ -489,39 +488,192 @@ void rtw_reset_continual_io_error(struct dvobj_priv *dvobj) } #ifdef DBG_IO +#define RTW_IO_SNIFF_TYPE_RANGE 0 /* specific address range is accessed */ +#define RTW_IO_SNIFF_TYPE_EN 1 /* part or all sniffed range is enabled */ +#define RTW_IO_SNIFF_TYPE_DIS 2 /* part or all sniffed range is disabled */ + +struct rtw_io_sniff_ent { + u8 chip; + u8 hci; + u32 addr; + u8 type; + union { + u32 end_addr; + u32 mask; + } u; + char *tag; +}; + +const char *rtw_io_sniff_ent_get_tag(const struct rtw_io_sniff_ent *ent) +{ + return ent->tag; +} -u32 read_sniff_ranges[][2] = { - /* {0x520, 0x523}, */ +#define RTW_IO_SNIFF_RANGE_ENT(_chip, _hci, _addr, _end_addr, _tag) \ + {.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,} + +#define RTW_IO_SNIFF_EN_ENT(_chip, _hci, _addr, _mask, _tag) \ + {.chip = _chip, .hci = _hci, .addr = _addr, .u.mask = _mask, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_EN,} + +#define RTW_IO_SNIFF_DIS_ENT(_chip, _hci, _addr, _mask, _tag) \ + {.chip = _chip, .hci = _hci, .addr = _addr, .u.mask = _mask, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_DIS,} + +const struct rtw_io_sniff_ent read_sniff[] = { +#ifdef DBG_IO_HCI_EN_CHK + RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, "SDIO 0x02[8:2] not all 0"), + RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, "USB 0x02[8:5] not all 0"), + RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, "PCI 0x02[4:2] not all 0"), +#endif +#ifdef DBG_IO_SNIFF_EXAMPLE + RTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, "read TXPAUSE"), + RTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, "0x02[1:0] not all 1"), +#endif }; -u32 write_sniff_ranges[][2] = { - /* {0x520, 0x523}, */ - /* {0x4c, 0x4c}, */ +const int read_sniff_num = sizeof(read_sniff) / sizeof(struct rtw_io_sniff_ent); + +const struct rtw_io_sniff_ent write_sniff[] = { +#ifdef DBG_IO_HCI_EN_CHK + RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_SDIO, 0x02, 0x1FC, "SDIO 0x02[8:2] not all 0"), + RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_USB, 0x02, 0x1E0, "USB 0x02[8:5] not all 0"), + RTW_IO_SNIFF_EN_ENT(MAX_CHIP_TYPE, RTW_PCIE, 0x02, 0x01C, "PCI 0x02[4:2] not all 0"), +#endif +#ifdef DBG_IO_SNIFF_EXAMPLE + RTW_IO_SNIFF_RANGE_ENT(MAX_CHIP_TYPE, 0, 0x522, 0x522, "write TXPAUSE"), + RTW_IO_SNIFF_DIS_ENT(MAX_CHIP_TYPE, 0, 0x02, 0x3, "0x02[1:0] not all 1"), +#endif }; -int read_sniff_num = sizeof(read_sniff_ranges) / sizeof(u32) / 2; -int write_sniff_num = sizeof(write_sniff_ranges) / sizeof(u32) / 2; +const int write_sniff_num = sizeof(write_sniff) / sizeof(struct rtw_io_sniff_ent); + +static bool match_io_sniff_ranges(_adapter *adapter + , const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u16 len) +{ + + /* check if IO range after sniff end address */ + if (addr > sniff->u.end_addr) + return 0; + + return 1; +} + +static bool match_io_sniff_en(_adapter *adapter + , const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val) +{ + u8 sniff_len; + u8 shift; + u32 mask; + bool ret = 0; + + /* check if IO range after sniff end address */ + sniff_len = 4; + while (!(sniff->u.mask & (0xFF << ((sniff_len - 1) * 8)))) { + sniff_len--; + if (sniff_len == 0) + goto exit; + } + if (sniff->addr + sniff_len <= addr) + goto exit; + + if (sniff->addr > addr) { + shift = (sniff->addr - addr) * 8; + mask = sniff->u.mask << shift; + } else if (sniff->addr < addr) { + shift = (addr - sniff->addr) * 8; + mask = sniff->u.mask >> shift; + } else { + shift = 0; + mask = sniff->u.mask; + } + + if (sniff->type == RTW_IO_SNIFF_TYPE_DIS) { + if (len == 4) + mask &= 0xFFFFFFFF; + else if (len == 3) + mask &= 0x00FFFFFF; + else if (len == 2) + mask &= 0x0000FFFF; + else if (len == 1) + mask &= 0x000000FF; + else + mask &= 0x00000000; + } + + if ((sniff->type == RTW_IO_SNIFF_TYPE_EN && (mask & val)) + || (sniff->type == RTW_IO_SNIFF_TYPE_DIS && (mask & val) != mask) + ) { + ret = 1; + if (0) + RTW_INFO(FUNC_ADPT_FMT" addr:0x%x len:%u val:0x%x i:%d sniff_len:%u shift:%u mask:0x%x\n" + , FUNC_ADPT_ARG(adapter), addr, len, val, i, sniff_len, shift, mask); + } + +exit: + return ret; +} + +static bool match_io_sniff(_adapter *adapter + , const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val) +{ + bool ret = 0; + + if (sniff->chip != MAX_CHIP_TYPE + && sniff->chip != rtw_get_chip_type(adapter)) + goto exit; + if (sniff->hci + && !(sniff->hci & rtw_get_intf_type(adapter))) + goto exit; + if (sniff->addr >= addr + len) /* IO range below sniff start address */ + goto exit; + + switch (sniff->type) { + case RTW_IO_SNIFF_TYPE_RANGE: + ret = match_io_sniff_ranges(adapter, sniff, i, addr, len); + break; + case RTW_IO_SNIFF_TYPE_EN: + case RTW_IO_SNIFF_TYPE_DIS: + if (len == 1 || len == 2 || len == 4) + ret = match_io_sniff_en(adapter, sniff, i, addr, len, val); + break; + default: + rtw_warn_on(1); + break; + } + +exit: + return ret; +} -bool match_read_sniff_ranges(u32 addr, u16 len) +const struct rtw_io_sniff_ent *match_read_sniff(_adapter *adapter + , u32 addr, u16 len, u32 val) { int i; + bool ret = 0; + for (i = 0; i < read_sniff_num; i++) { - if (addr + len > read_sniff_ranges[i][0] && addr <= read_sniff_ranges[i][1]) - return _TRUE; + ret = match_io_sniff(adapter, &read_sniff[i], i, addr, len, val); + if (ret) + goto exit; } - return _FALSE; +exit: + return ret ? &read_sniff[i] : NULL; } -bool match_write_sniff_ranges(u32 addr, u16 len) +const struct rtw_io_sniff_ent *match_write_sniff(_adapter *adapter + , u32 addr, u16 len, u32 val) { int i; + bool ret = 0; + for (i = 0; i < write_sniff_num; i++) { - if (addr + len > write_sniff_ranges[i][0] && addr <= write_sniff_ranges[i][1]) - return _TRUE; + ret = match_io_sniff(adapter, &write_sniff[i], i, addr, len, val); + if (ret) + goto exit; } - return _FALSE; +exit: + return ret ? &write_sniff[i] : NULL; } struct rf_sniff_ent { @@ -543,7 +695,7 @@ struct rf_sniff_ent rf_write_sniff_ranges[] = { int rf_read_sniff_num = sizeof(rf_read_sniff_ranges) / sizeof(struct rf_sniff_ent); int rf_write_sniff_num = sizeof(rf_write_sniff_ranges) / sizeof(struct rf_sniff_ent); -bool match_rf_read_sniff_ranges(u8 path, u32 addr, u32 mask) +bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask) { int i; @@ -556,7 +708,7 @@ bool match_rf_read_sniff_ranges(u8 path, u32 addr, u32 mask) return _FALSE; } -bool match_rf_write_sniff_ranges(u8 path, u32 addr, u32 mask) +bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask) { int i; @@ -572,9 +724,12 @@ bool match_rf_write_sniff_ranges(u8 path, u32 addr, u32 mask) u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line) { u8 val = _rtw_read8(adapter, addr); + const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 1, val); - if (match_read_sniff_ranges(addr, 1)) - RTW_INFO("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x\n", caller, line, addr, val); + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return val; } @@ -582,9 +737,12 @@ u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line) { u16 val = _rtw_read16(adapter, addr); + const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 2, val); - if (match_read_sniff_ranges(addr, 2)) - RTW_INFO("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\n", caller, line, addr, val); + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return val; } @@ -592,38 +750,57 @@ u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int li u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line) { u32 val = _rtw_read32(adapter, addr); + const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 4, val); - if (match_read_sniff_ranges(addr, 4)) - RTW_INFO("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\n", caller, line, addr, val); + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return val; } int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line) { - if (match_write_sniff_ranges(addr, 1)) - RTW_INFO("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n", caller, line, addr, val); + const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 1, val); + + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x) %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return _rtw_write8(adapter, addr, val); } int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line) { - if (match_write_sniff_ranges(addr, 2)) - RTW_INFO("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n", caller, line, addr, val); + const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 2, val); + + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x) %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return _rtw_write16(adapter, addr, val); } int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line) { - if (match_write_sniff_ranges(addr, 4)) - RTW_INFO("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n", caller, line, addr, val); + const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 4, val); + + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x) %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return _rtw_write32(adapter, addr, val); } int dbg_rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *data, const char *caller, const int line) { - if (match_write_sniff_ranges(addr, length)) - RTW_INFO("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n", caller, line, addr, length); + const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, length, 0); + + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_writeN(0x%04x, %u) %s\n" + , caller, line, addr, length, rtw_io_sniff_ent_get_tag(ent)); + } return _rtw_writeN(adapter, addr, length, data); } @@ -634,8 +811,12 @@ u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const in u8 val = _rtw_sd_f0_read8(adapter, addr); #if 0 - if (match_read_sniff_ranges(addr, 1)) - RTW_INFO("DBG_IO %s:%d rtw_sd_f0_read8(0x%04x) return 0x%02x\n", caller, line, addr, val); + const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 1, val); + + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_sd_f0_read8(0x%04x) return 0x%02x %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } #endif return val; @@ -645,9 +826,12 @@ u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const in u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line) { u8 val = rtw_sd_iread8(adapter, addr); + const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 1, val); - if (match_read_sniff_ranges(addr, 1)) - RTW_INFO("DBG_IO %s:%d rtw_sd_iread8(0x%04x) return 0x%02x\n", caller, line, addr, val); + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_sd_iread8(0x%04x) return 0x%02x %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return val; } @@ -655,9 +839,12 @@ u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line) { u16 val = _rtw_sd_iread16(adapter, addr); + const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 2, val); - if (match_read_sniff_ranges(addr, 2)) - RTW_INFO("DBG_IO %s:%d rtw_sd_iread16(0x%04x) return 0x%04x\n", caller, line, addr, val); + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_sd_iread16(0x%04x) return 0x%04x %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return val; } @@ -665,31 +852,46 @@ u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const in u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line) { u32 val = _rtw_sd_iread32(adapter, addr); + const struct rtw_io_sniff_ent *ent = match_read_sniff(adapter, addr, 4, val); - if (match_read_sniff_ranges(addr, 4)) - RTW_INFO("DBG_IO %s:%d rtw_sd_iread32(0x%04x) return 0x%08x\n", caller, line, addr, val); + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_sd_iread32(0x%04x) return 0x%08x %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return val; } int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line) { - if (match_write_sniff_ranges(addr, 1)) - RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite8(0x%04x, 0x%02x)\n", caller, line, addr, val); + const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 1, val); + + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite8(0x%04x, 0x%02x) %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return _rtw_sd_iwrite8(adapter, addr, val); } int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line) { - if (match_write_sniff_ranges(addr, 2)) - RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite16(0x%04x, 0x%04x)\n", caller, line, addr, val); + const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 2, val); + + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite16(0x%04x, 0x%04x) %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return _rtw_sd_iwrite16(adapter, addr, val); } int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line) { - if (match_write_sniff_ranges(addr, 4)) - RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite32(0x%04x, 0x%08x)\n", caller, line, addr, val); + const struct rtw_io_sniff_ent *ent = match_write_sniff(adapter, addr, 4, val); + + if (ent) { + RTW_INFO("DBG_IO %s:%d rtw_sd_iwrite32(0x%04x, 0x%08x) %s\n" + , caller, line, addr, val, rtw_io_sniff_ent_get_tag(ent)); + } return _rtw_sd_iwrite32(adapter, addr, val); } diff --git a/core/rtw_ioctl_query.c b/core/rtw_ioctl_query.c index 4f8232d..6f7613e 100644 --- a/core/rtw_ioctl_query.c +++ b/core/rtw_ioctl_query.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_IOCTL_QUERY_C_ #include diff --git a/core/rtw_ioctl_rtl.c b/core/rtw_ioctl_rtl.c index ab4a387..5d9e76b 100644 --- a/core/rtw_ioctl_rtl.c +++ b/core/rtw_ioctl_rtl.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_IOCTL_RTL_C_ #include @@ -432,13 +427,14 @@ NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv *poid_par_priv) { NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); if (poid_par_priv->type_of_oid != QUERY_OID) { status = NDIS_STATUS_NOT_ACCEPTED; return status; } *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; - *(u16 *)poid_par_priv->information_buf = padapter->mlmepriv.ChannelPlan ; + *(u16 *)poid_par_priv->information_buf = rfctl->ChannelPlan; return status; } @@ -446,13 +442,14 @@ NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv *poid_par_priv) { NDIS_STATUS status = NDIS_STATUS_SUCCESS; PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); if (poid_par_priv->type_of_oid != SET_OID) { status = NDIS_STATUS_NOT_ACCEPTED; return status; } - padapter->mlmepriv.ChannelPlan = *(u16 *)poid_par_priv->information_buf ; + rfctl->ChannelPlan = *(u16 *)poid_par_priv->information_buf; return status; } diff --git a/core/rtw_ioctl_set.c b/core/rtw_ioctl_set.c index 9a1a311..d32a014 100644 --- a/core/rtw_ioctl_set.c +++ b/core/rtw_ioctl_set.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_IOCTL_SET_C_ #include @@ -47,7 +42,9 @@ u8 rtw_validate_bssid(u8 *bssid) u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid) { +#ifdef CONFIG_VALIDATE_SSID u8 i; +#endif u8 ret = _TRUE; @@ -79,6 +76,7 @@ u8 rtw_do_join(_adapter *padapter) _list *plist, *phead; u8 *pibss = NULL; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sitesurvey_parm parm; _queue *queue = &(pmlmepriv->scanned_queue); u8 ret = _SUCCESS; @@ -96,6 +94,10 @@ u8 rtw_do_join(_adapter *padapter) pmlmepriv->to_join = _TRUE; + rtw_init_sitesurvey_parm(padapter, &parm); + _rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + parm.ssid_num = 1; + if (_rtw_queue_empty(queue) == _TRUE) { _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); @@ -106,10 +108,17 @@ u8 rtw_do_join(_adapter *padapter) if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE || rtw_to_roam(padapter) > 0 ) { - /* submit site_survey_cmd */ - ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); - if (_SUCCESS != ret) { + u8 ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE); + + if ((ssc_chk == SS_ALLOW) || (ssc_chk == SS_DENY_BUSY_TRAFFIC) ){ + /* submit site_survey_cmd */ + ret = rtw_sitesurvey_cmd(padapter, &parm); + if (_SUCCESS != ret) + pmlmepriv->to_join = _FALSE; + } else { + /*if (ssc_chk == SS_DENY_BUDDY_UNDER_SURVEY)*/ pmlmepriv->to_join = _FALSE; + ret = _FAIL; } } else { pmlmepriv->to_join = _FALSE; @@ -155,26 +164,22 @@ u8 rtw_do_join(_adapter *padapter) /* can't associate ; reset under-linking */ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); -#if 0 - if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) { - if (_rtw_memcmp(pmlmepriv->cur_network.network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength)) { - /* for funk to do roaming */ - /* funk will reconnect, but funk will not sitesurvey before reconnect */ - if (pmlmepriv->sitesurveyctrl.traffic_busy == _FALSE) - rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); - } - - } -#endif - /* when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue */ /* we try to issue sitesurvey firstly */ if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE || rtw_to_roam(padapter) > 0 ) { - /* RTW_INFO("rtw_do_join() when no desired bss in scanning queue\n"); */ - ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); - if (_SUCCESS != ret) { + u8 ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE); + + if ((ssc_chk == SS_ALLOW) || (ssc_chk == SS_DENY_BUSY_TRAFFIC)){ + /* RTW_INFO(("rtw_do_join() when no desired bss in scanning queue\n"); */ + ret = rtw_sitesurvey_cmd(padapter, &parm); + if (_SUCCESS != ret) + pmlmepriv->to_join = _FALSE; + } else { + /*if (ssc_chk == SS_DENY_BUDDY_UNDER_SURVEY) { + } else {*/ + ret = _FAIL; pmlmepriv->to_join = _FALSE; } } else { @@ -307,7 +312,7 @@ u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid) if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) rtw_indicate_disconnect(padapter, 0, _FALSE); - rtw_free_assoc_resources(padapter, 1); + rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); @@ -344,7 +349,6 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) { _irqL irqL; u8 status = _SUCCESS; - u32 cur_time = 0; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_network *pnetwork = &pmlmepriv->cur_network; @@ -379,7 +383,7 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) rtw_indicate_disconnect(padapter, 0, _FALSE); - rtw_free_assoc_resources(padapter, 1); + rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); @@ -400,7 +404,7 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) rtw_indicate_disconnect(padapter, 0, _FALSE); - rtw_free_assoc_resources(padapter, 1); + rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); @@ -442,7 +446,6 @@ u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid) { _irqL irqL; u8 status = _SUCCESS; - u32 cur_time = 0; bool bssid_valid = _TRUE; bool ssid_valid = _TRUE; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -514,16 +517,18 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_network *cur_network = &pmlmepriv->cur_network; NDIS_802_11_NETWORK_INFRASTRUCTURE *pold_state = &(cur_network->network.InfrastructureMode); - - + u8 ap2sta_mode = _FALSE; + u8 ret = _TRUE; if (*pold_state != networktype) { /* RTW_INFO("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); */ - if (*pold_state == Ndis802_11APMode) { - /* change to other mode from Ndis802_11APMode */ + if (*pold_state == Ndis802_11APMode + || *pold_state == Ndis802_11_mesh + ) { + /* change to other mode from Ndis802_11APMode/Ndis802_11_mesh */ cur_network->join_res = -1; - + ap2sta_mode = _TRUE; #ifdef CONFIG_NATIVEAP_MLME stop_ap_mode(padapter); #endif @@ -536,7 +541,7 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) - rtw_free_assoc_resources(padapter, 1); + rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); if ((*pold_state == Ndis802_11Infrastructure) || (*pold_state == Ndis802_11IBSS)) { if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { @@ -555,6 +560,9 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, case Ndis802_11Infrastructure: set_fwstate(pmlmepriv, WIFI_STATION_STATE); + + if (ap2sta_mode) + rtw_init_bcmc_stainfo(padapter); break; case Ndis802_11APMode: @@ -566,12 +574,22 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, break; +#ifdef CONFIG_RTW_MESH + case Ndis802_11_mesh: + set_fwstate(pmlmepriv, WIFI_MESH_STATE); + start_ap_mode(padapter); + break; +#endif + case Ndis802_11AutoUnknown: case Ndis802_11InfrastructureMax: break; case Ndis802_11Monitor: set_fwstate(pmlmepriv, WIFI_MONITOR_STATE); break; + default: + ret = _FALSE; + rtw_warn_on(1); } /* SecClearAllKeys(adapter); */ @@ -580,8 +598,7 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, _exit_critical_bh(&pmlmepriv->lock, &irqL); } - - return _TRUE; + return ret; } @@ -598,7 +615,7 @@ u8 rtw_set_802_11_disassociate(_adapter *padapter) rtw_disassoc_cmd(padapter, 0, 0); rtw_indicate_disconnect(padapter, 0, _FALSE); /* modify for CONFIG_IEEE80211W, none 11w can use it */ - rtw_free_assoc_resources_cmd(padapter); + rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); if (_FAIL == rtw_pwr_wakeup(padapter)) RTW_INFO("%s(): rtw_pwr_wakeup fail !!!\n", __FUNCTION__); } @@ -610,21 +627,21 @@ u8 rtw_set_802_11_disassociate(_adapter *padapter) } #if 1 -u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num, struct rtw_ieee80211_channel *ch, int ch_num) +u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm) { _irqL irqL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; u8 res = _TRUE; _enter_critical_bh(&pmlmepriv->lock, &irqL); - res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, ch, ch_num); + res = rtw_sitesurvey_cmd(padapter, pparm); _exit_critical_bh(&pmlmepriv->lock, &irqL); return res; } #else -u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num, struct rtw_ieee80211_channel *ch, int ch_num) +u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm) { _irqL irqL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -656,7 +673,7 @@ u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, i _enter_critical_bh(&pmlmepriv->lock, &irqL); - res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, NULL, 0, ch, ch_num); + res = rtw_sitesurvey_cmd(padapter, pparm); _exit_critical_bh(&pmlmepriv->lock, &irqL); } @@ -746,374 +763,6 @@ u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep) } -u8 rtw_set_802_11_remove_wep(_adapter *padapter, u32 keyindex) -{ - - u8 ret = _SUCCESS; - - - if (keyindex >= 0x80000000 || padapter == NULL) { - - ret = _FALSE; - goto exit; - - } else { - int res; - struct security_priv *psecuritypriv = &(padapter->securitypriv); - if (keyindex < 4) { - - _rtw_memset(&psecuritypriv->dot11DefKey[keyindex], 0, 16); - - res = rtw_set_key(padapter, psecuritypriv, keyindex, 0, _TRUE); - - psecuritypriv->dot11DefKeylen[keyindex] = 0; - - if (res == _FAIL) - ret = _FAIL; - - } else - ret = _FAIL; - - } - -exit: - - - return ret; - -} - -u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key) -{ - - uint encryptionalgo; - u8 *pbssid; - struct sta_info *stainfo; - u8 bgroup = _FALSE; - u8 bgrouptkey = _FALSE;/* can be remove later */ - u8 ret = _SUCCESS; - - - if (((key->KeyIndex & 0x80000000) == 0) && ((key->KeyIndex & 0x40000000) > 0)) { - - /* It is invalid to clear bit 31 and set bit 30. If the miniport driver encounters this combination, */ - /* it must fail the request and return NDIS_STATUS_INVALID_DATA. */ - ret = _FAIL; - goto exit; - } - - if (key->KeyIndex & 0x40000000) { - /* Pairwise key */ - - - pbssid = get_bssid(&padapter->mlmepriv); - stainfo = rtw_get_stainfo(&padapter->stapriv, pbssid); - - if ((stainfo != NULL) && (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)) { - encryptionalgo = stainfo->dot118021XPrivacy; - } else { - encryptionalgo = padapter->securitypriv.dot11PrivacyAlgrthm; - } - - - - - if (key->KeyIndex & 0x000000FF) { - /* The key index is specified in the lower 8 bits by values of zero to 255. */ - /* The key index should be set to zero for a Pairwise key, and the driver should fail with */ - /* NDIS_STATUS_INVALID_DATA if the lower 8 bits is not zero */ - ret = _FAIL; - goto exit; - } - - /* check BSSID */ - if (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _TRUE) { - - ret = _FALSE; - goto exit; - } - - /* Check key length for TKIP. */ - /* if(encryptionAlgorithm == RT_ENC_TKIP_ENCRYPTION && key->KeyLength != 32) */ - if ((encryptionalgo == _TKIP_) && (key->KeyLength != 32)) { - ret = _FAIL; - goto exit; - - } - - /* Check key length for AES. */ - if ((encryptionalgo == _AES_) && (key->KeyLength != 16)) { - /* For our supplicant, EAPPkt9x.vxd, cannot differentiate TKIP and AES case. */ - if (key->KeyLength == 32) - key->KeyLength = 16; - else { - ret = _FAIL; - goto exit; - } - } - - /* Check key length for WEP. For NDTEST, 2005.01.27, by rcnjko. -> modify checking condition*/ - if (((encryptionalgo == _WEP40_) && (key->KeyLength != 5)) || ((encryptionalgo == _WEP104_) && (key->KeyLength != 13))) { - ret = _FAIL; - goto exit; - } - - bgroup = _FALSE; - - /* Check the pairwise key. Added by Annie, 2005-07-06. */ - - } else { - /* Group key - KeyIndex(BIT30==0) */ - - - /* when add wep key through add key and didn't assigned encryption type before */ - if ((padapter->securitypriv.ndisauthtype <= 3) && (padapter->securitypriv.dot118021XGrpPrivacy == 0)) { - - switch (key->KeyLength) { - case 5: - padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_; - break; - case 13: - padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_; - break; - default: - padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_; - break; - } - - encryptionalgo = padapter->securitypriv.dot11PrivacyAlgrthm; - - - } else { - encryptionalgo = padapter->securitypriv.dot118021XGrpPrivacy; - - } - - if ((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE) == _TRUE) && (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _FALSE)) { - ret = _FAIL; - goto exit; - } - - /* Check key length for TKIP */ - if ((encryptionalgo == _TKIP_) && (key->KeyLength != 32)) { - - ret = _FAIL; - goto exit; - - } else if (encryptionalgo == _AES_ && (key->KeyLength != 16 && key->KeyLength != 32)) { - - /* Check key length for AES */ - /* For NDTEST, we allow keylen=32 in this case. 2005.01.27, by rcnjko. */ - ret = _FAIL; - goto exit; - } - - /* Change the key length for EAPPkt9x.vxd. Added by Annie, 2005-11-03. */ - if ((encryptionalgo == _AES_) && (key->KeyLength == 32)) { - key->KeyLength = 16; - } - - if (key->KeyIndex & 0x8000000) /* error ??? 0x8000_0000 */ - bgrouptkey = _TRUE; - - if ((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE) == _TRUE) && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE)) - bgrouptkey = _TRUE; - - bgroup = _TRUE; - - - } - - /* If WEP encryption algorithm, just call rtw_set_802_11_add_wep(). */ - if ((padapter->securitypriv.dot11AuthAlgrthm != dot11AuthAlgrthm_8021X) && (encryptionalgo == _WEP40_ || encryptionalgo == _WEP104_)) { - u8 ret; - u32 keyindex; - u32 len = FIELD_OFFSET(NDIS_802_11_KEY, KeyMaterial) + key->KeyLength; - NDIS_802_11_WEP *wep = &padapter->securitypriv.ndiswep; - - - wep->Length = len; - keyindex = key->KeyIndex & 0x7fffffff; - wep->KeyIndex = keyindex ; - wep->KeyLength = key->KeyLength; - - - _rtw_memcpy(wep->KeyMaterial, key->KeyMaterial, key->KeyLength); - _rtw_memcpy(&(padapter->securitypriv.dot11DefKey[keyindex].skey[0]), key->KeyMaterial, key->KeyLength); - - padapter->securitypriv.dot11DefKeylen[keyindex] = key->KeyLength; - padapter->securitypriv.dot11PrivacyKeyIndex = keyindex; - - ret = rtw_set_802_11_add_wep(padapter, wep); - - goto exit; - - } - - if (key->KeyIndex & 0x20000000) { - /* SetRSC */ - if (bgroup == _TRUE) { - NDIS_802_11_KEY_RSC keysrc = key->KeyRSC & 0x00FFFFFFFFFFFFULL; - _rtw_memcpy(&padapter->securitypriv.dot11Grprxpn, &keysrc, 8); - } else { - NDIS_802_11_KEY_RSC keysrc = key->KeyRSC & 0x00FFFFFFFFFFFFULL; - _rtw_memcpy(&padapter->securitypriv.dot11Grptxpn, &keysrc, 8); - } - - } - - /* Indicate this key idx is used for TX */ - /* Save the key in KeyMaterial */ - if (bgroup == _TRUE) { /* Group transmit key */ - int res; - - if (bgrouptkey == _TRUE) - padapter->securitypriv.dot118021XGrpKeyid = (u8)key->KeyIndex; - - if ((key->KeyIndex & 0x3) == 0) { - ret = _FAIL; - goto exit; - } - - _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], 0, 16); - _rtw_memset(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16); - _rtw_memset(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16); - - if ((key->KeyIndex & 0x10000000)) { - _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); - _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); - - - } else { - _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); - _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); - - - } - - /* set group key by index */ - _rtw_memcpy(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial, key->KeyLength); - - key->KeyIndex = key->KeyIndex & 0x03; - - padapter->securitypriv.binstallGrpkey = _TRUE; - - padapter->securitypriv.bcheck_grpkey = _FALSE; - - - res = rtw_set_key(padapter, &padapter->securitypriv, key->KeyIndex, 1, _TRUE); - - if (res == _FAIL) - ret = _FAIL; - - goto exit; - - } else { /* Pairwise Key */ - u8 res; - - pbssid = get_bssid(&padapter->mlmepriv); - stainfo = rtw_get_stainfo(&padapter->stapriv , pbssid); - - if (stainfo != NULL) { - _rtw_memset(&stainfo->dot118021x_UncstKey, 0, 16); /* clear keybuffer */ - - _rtw_memcpy(&stainfo->dot118021x_UncstKey, key->KeyMaterial, 16); - - if (encryptionalgo == _TKIP_) { - padapter->securitypriv.busetkipkey = _FALSE; - - /* if TKIP, save the Receive/Transmit MIC key in KeyMaterial[128-255] */ - if ((key->KeyIndex & 0x10000000)) { - _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 16, 8); - _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 24, 8); - - } else { - _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 24, 8); - _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 16, 8); - - } - - } else if (encryptionalgo == _AES_) { - - } - - - /* Set key to CAM through H2C command */ -#if 0 - if (bgrouptkey) { /* never go to here */ - res = rtw_setstakey_cmd(padapter, stainfo, GROUP_KEY, _TRUE); - } else { - res = rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE); - } -#else - - res = rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE); -#endif - - if (res == _FALSE) - ret = _FAIL; - - } - - } - -exit: - - - return ret; -} - -u8 rtw_set_802_11_remove_key(_adapter *padapter, NDIS_802_11_REMOVE_KEY *key) -{ - - uint encryptionalgo; - u8 *pbssid; - struct sta_info *stainfo; - u8 bgroup = (key->KeyIndex & 0x4000000) > 0 ? _FALSE : _TRUE; - u8 keyIndex = (u8)key->KeyIndex & 0x03; - u8 ret = _SUCCESS; - - - if ((key->KeyIndex & 0xbffffffc) > 0) { - ret = _FAIL; - goto exit; - } - - if (bgroup == _TRUE) { - encryptionalgo = padapter->securitypriv.dot118021XGrpPrivacy; - /* clear group key by index */ - /* NdisZeroMemory(Adapter->MgntInfo.SecurityInfo.KeyBuf[keyIndex], MAX_WEP_KEY_LEN); */ - /* Adapter->MgntInfo.SecurityInfo.KeyLen[keyIndex] = 0; */ - - _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[keyIndex], 0, 16); - - /* ! \todo Send a H2C Command to Firmware for removing this Key in CAM Entry. */ - - } else { - - pbssid = get_bssid(&padapter->mlmepriv); - stainfo = rtw_get_stainfo(&padapter->stapriv , pbssid); - if (stainfo != NULL) { - encryptionalgo = stainfo->dot118021XPrivacy; - - /* clear key by BSSID */ - _rtw_memset(&stainfo->dot118021x_UncstKey, 0, 16); - - /* ! \todo Send a H2C Command to Firmware for disable this Key in CAM Entry. */ - - } else { - ret = _FAIL; - goto exit; - } - } - -exit: - - - return _TRUE; - -} - /* * rtw_get_cur_max_rate - * @adapter: pointer to _adapter structure @@ -1122,10 +771,13 @@ u8 rtw_set_802_11_remove_key(_adapter *padapter, NDIS_802_11_REMOVE_KEY *key) */ u16 rtw_get_cur_max_rate(_adapter *adapter) { + int j; int i = 0; u16 rate = 0, max_rate = 0; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; + int sta_bssrate_len = 0; + unsigned char sta_bssrate[NumRates]; struct sta_info *psta = NULL; u8 short_GI = 0; #ifdef CONFIG_80211N_HT @@ -1147,34 +799,56 @@ u16 rtw_get_cur_max_rate(_adapter *adapter) if (psta == NULL) return 0; - short_GI = query_ra_short_GI(psta, psta->bw_mode); + short_GI = query_ra_short_GI(psta, rtw_get_tx_bw_mode(adapter, psta)); #ifdef CONFIG_80211N_HT if (is_supported_ht(psta->wireless_mode)) { rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); max_rate = rtw_mcs_rate(rf_type - , (psta->bw_mode == CHANNEL_WIDTH_40) ? 1 : 0 + , (psta->cmn.bw_mode == CHANNEL_WIDTH_40) ? 1 : 0 , short_GI , psta->htpriv.ht_cap.supp_mcs_set ); } #ifdef CONFIG_80211AC_VHT else if (is_supported_vht(psta->wireless_mode)) - max_rate = ((rtw_vht_mcs_to_data_rate(psta->bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10; + max_rate = ((rtw_vht_mcs_to_data_rate(psta->cmn.bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10; #endif /* CONFIG_80211AC_VHT */ else #endif /* CONFIG_80211N_HT */ { + /*station mode show :station && ap support rate; softap :show ap support rate*/ + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + get_rate_set(adapter, sta_bssrate, &sta_bssrate_len);/*get sta rate and length*/ + + while ((pcur_bss->SupportedRates[i] != 0) && (pcur_bss->SupportedRates[i] != 0xFF)) { - rate = pcur_bss->SupportedRates[i] & 0x7F; - if (rate > max_rate) - max_rate = rate; + rate = pcur_bss->SupportedRates[i] & 0x7F;/*AP support rates*/ + /*RTW_INFO("%s rate=%02X \n", __func__, rate);*/ + + /*check STA support rate or not */ + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + for (j = 0; j < sta_bssrate_len; j++) { + /* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */ + if ((rate | IEEE80211_BASIC_RATE_MASK) + == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) { + if (rate > max_rate) { + max_rate = rate; + } + break; + } + } + } else { + + if (rate > max_rate) + max_rate = rate; + + } i++; } max_rate = max_rate * 10 / 2; } - return max_rate; } @@ -1204,9 +878,6 @@ int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode) */ int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan) { - struct registry_priv *pregistrypriv = &adapter->registrypriv; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - /* handle by cmd_thread to sync with scan operation */ return rtw_set_chplan_cmd(adapter, RTW_CMDF_WAIT_ACK, channel_plan, 1); } @@ -1223,7 +894,8 @@ int rtw_set_country(_adapter *adapter, const char *country_code) #ifdef CONFIG_RTW_IOCTL_SET_COUNTRY return rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, 1); #else - return _FAIL; + RTW_INFO("%s(): not applied\n", __func__); + return _SUCCESS; #endif } diff --git a/core/rtw_iol.c b/core/rtw_iol.c index 42d0b6b..643ec6c 100644 --- a/core/rtw_iol.c +++ b/core/rtw_iol.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include @@ -306,24 +301,36 @@ int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value) #ifdef DBG_IO int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line) { - if (match_write_sniff_ranges(addr, 1)) - RTW_INFO("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x)\n", caller, line, addr, value); + const struct rtw_io_sniff_ent *ent = match_write_sniff(xmit_frame->padapter, addr, 1, value); + + if (ent) { + RTW_INFO("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x) %s\n" + , caller, line, addr, value, rtw_io_sniff_ent_get_tag(ent)); + } return _rtw_IOL_append_WB_cmd(xmit_frame, addr, value); } int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line) { - if (match_write_sniff_ranges(addr, 2)) - RTW_INFO("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x)\n", caller, line, addr, value); + const struct rtw_io_sniff_ent *ent = match_write_sniff(xmit_frame->padapter, addr, 2, value); + + if (ent) { + RTW_INFO("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x) %s\n" + , caller, line, addr, value, rtw_io_sniff_ent_get_tag(ent)); + } return _rtw_IOL_append_WW_cmd(xmit_frame, addr, value); } int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line) { - if (match_write_sniff_ranges(addr, 4)) - RTW_INFO("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x)\n", caller, line, addr, value); + const struct rtw_io_sniff_ent *ent = match_write_sniff(xmit_frame->padapter, addr, 4, value); + + if (ent) { + RTW_INFO("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x) %s\n" + , caller, line, addr, value, rtw_io_sniff_ent_get_tag(ent)); + } return _rtw_IOL_append_WD_cmd(xmit_frame, addr, value); } diff --git a/core/rtw_mem.c b/core/rtw_mem.c index b68a456..d9f5652 100644 --- a/core/rtw_mem.c +++ b/core/rtw_mem.c @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #include #include diff --git a/core/rtw_mi.c b/core/rtw_mi.c index d7e3f20..9507d8f 100644 --- a/core/rtw_mi.c +++ b/core/rtw_mi.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2015 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_MI_C_ #include @@ -32,10 +27,88 @@ void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw) iface_state->union_offset = offset; } -/* Find union about ch, bw, ch_offset of all linked/linking interfaces */ -int _rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset, bool include_self) +#ifdef DBG_IFACE_STATUS +#ifdef CONFIG_P2P +static u8 _rtw_mi_p2p_listen_scan_chk(_adapter *adapter) { + int i; + _adapter *iface; struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 p2p_listen_scan_state = _FALSE; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN) || + rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_SCAN)) { + p2p_listen_scan_state = _TRUE; + break; + } + } + return p2p_listen_scan_state; +} +#endif +#endif + +u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter) +{ + u8 rst = _TRUE; + u8 u_ch, u_bw, u_offset; + u8 o_ch, o_bw, o_offset; + + u_ch = rtw_mi_get_union_chan(adapter); + u_bw = rtw_mi_get_union_bw(adapter); + u_offset = rtw_mi_get_union_offset(adapter); + + o_ch = rtw_get_oper_ch(adapter); + o_bw = rtw_get_oper_bw(adapter); + o_offset = rtw_get_oper_choffset(adapter); + + if ((u_ch != o_ch) || (u_bw != o_bw) || (u_offset != o_offset)) + rst = _FALSE; + + #ifdef DBG_IFACE_STATUS + if (rst == _FALSE) { + RTW_ERR("%s Not stay in union channel\n", __func__); + if (GET_HAL_DATA(adapter)->bScanInProcess == _TRUE) + RTW_ERR("ScanInProcess\n"); + #ifdef CONFIG_P2P + if (_rtw_mi_p2p_listen_scan_chk(adapter)) + RTW_ERR("P2P in listen or scan state\n"); + #endif + RTW_ERR("union ch, bw, offset: %u,%u,%u\n", u_ch, u_bw, u_offset); + RTW_ERR("oper ch, bw, offset: %u,%u,%u\n", o_ch, o_bw, o_offset); + RTW_ERR("=========================\n"); + } + #endif + return rst; +} + +u8 rtw_mi_stayin_union_band_chk(_adapter *adapter) +{ + u8 rst = _TRUE; + u8 u_ch, o_ch; + u8 u_band, o_band; + + u_ch = rtw_mi_get_union_chan(adapter); + o_ch = rtw_get_oper_ch(adapter); + u_band = (u_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G; + o_band = (o_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G; + + if (u_ch != o_ch) + if(u_band != o_band) + rst = _FALSE; + + #ifdef DBG_IFACE_STATUS + if (rst == _FALSE) + RTW_ERR("%s Not stay in union band\n", __func__); + #endif + + return rst; +} + +/* Find union about ch, bw, ch_offset of all linked/linking interfaces */ +int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 *ch, u8 *bw, u8 *offset) +{ _adapter *iface; struct mlme_ext_priv *mlmeext; int i; @@ -53,6 +126,9 @@ int _rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset, for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; + if (!iface || !(ifbmp & BIT(iface->iface_id))) + continue; + mlmeext = &iface->mlmeextpriv; if (!check_fwstate(&iface->mlmepriv, _FW_LINKED | _FW_UNDER_LINKING)) @@ -61,9 +137,6 @@ int _rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset, if (check_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING)) continue; - if (include_self == _FALSE && adapter == iface) - continue; - if (num == 0) { ch_ret = mlmeext->cur_channel; bw_ret = mlmeext->cur_bwmode; @@ -102,18 +175,17 @@ int _rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset, inline int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) { - return _rtw_mi_get_ch_setting_union(adapter, ch, bw, offset, 1); + return rtw_mi_get_ch_setting_union_by_ifbmp(adapter_to_dvobj(adapter), 0xFF, ch, bw, offset); } inline int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) { - return _rtw_mi_get_ch_setting_union(adapter, ch, bw, offset, 0); + return rtw_mi_get_ch_setting_union_by_ifbmp(adapter_to_dvobj(adapter), 0xFF & ~BIT(adapter->iface_id), ch, bw, offset); } /* For now, not return union_ch/bw/offset */ -void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, bool include_self) +void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate) { - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); _adapter *iface; int i; @@ -121,24 +193,39 @@ void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, bool include_sel for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; - - if (include_self == _FALSE && iface == adapter) + if (!iface || !(ifbmp & BIT(iface->iface_id))) continue; if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) { MSTATE_STA_NUM(mstate)++; - if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) + if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) { MSTATE_STA_LD_NUM(mstate)++; + #ifdef CONFIG_TDLS + if (iface->tdlsinfo.link_established == _TRUE) + MSTATE_TDLS_LD_NUM(mstate)++; + #endif + #ifdef CONFIG_P2P + if (MLME_IS_GC(iface)) + MSTATE_P2P_GC_NUM(mstate)++; + #endif + } if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING) == _TRUE) MSTATE_STA_LG_NUM(mstate)++; - } else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE - && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE - ) { - MSTATE_AP_NUM(mstate)++; - if (iface->stapriv.asoc_sta_count > 2) - MSTATE_AP_LD_NUM(mstate)++; +#ifdef CONFIG_AP_MODE + } else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) { + if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) { + MSTATE_AP_NUM(mstate)++; + if (iface->stapriv.asoc_sta_count > 2) + MSTATE_AP_LD_NUM(mstate)++; + #ifdef CONFIG_P2P + if (MLME_IS_GO(iface)) + MSTATE_P2P_GO_NUM(mstate)++; + #endif + } else + MSTATE_AP_STARTING_NUM(mstate)++; +#endif } else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE @@ -146,11 +233,29 @@ void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, bool include_sel MSTATE_ADHOC_NUM(mstate)++; if (iface->stapriv.asoc_sta_count > 2) MSTATE_ADHOC_LD_NUM(mstate)++; + +#ifdef CONFIG_RTW_MESH + } else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE + && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE + ) { + MSTATE_MESH_NUM(mstate)++; + if (iface->stapriv.asoc_sta_count > 2) + MSTATE_MESH_LD_NUM(mstate)++; +#endif + } if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_WPS) == _TRUE) MSTATE_WPS_NUM(mstate)++; + if (check_fwstate(&iface->mlmepriv, WIFI_SITE_MONITOR) == _TRUE) { + MSTATE_SCAN_NUM(mstate)++; + + if (mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_DISABLE + && mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_BACK_OP) + MSTATE_SCAN_ENTER_NUM(mstate)++; + } + #ifdef CONFIG_IOCTL_CFG80211 if (rtw_cfg80211_get_is_mgmt_tx(iface)) MSTATE_MGMT_TX_NUM(mstate)++; @@ -159,38 +264,91 @@ void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, bool include_sel MSTATE_ROCH_NUM(mstate)++; #endif #endif /* CONFIG_IOCTL_CFG80211 */ - +#ifdef CONFIG_P2P + if (MLME_IS_PD(iface)) + MSTATE_P2P_DV_NUM(mstate)++; +#endif } } inline void rtw_mi_status(_adapter *adapter, struct mi_state *mstate) { - return _rtw_mi_status(adapter, mstate, 1); + return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), 0xFF, mstate); } + inline void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate) { - return _rtw_mi_status(adapter, mstate, 0); + return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), 0xFF & ~BIT(adapter->iface_id), mstate); } + +inline void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate) +{ + return rtw_mi_status_by_ifbmp(adapter_to_dvobj(adapter), BIT(adapter->iface_id), mstate); +} + +/* For now, not handle union_ch/bw/offset */ +inline void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a) +{ + d->sta_num += a->sta_num; + d->ld_sta_num += a->ld_sta_num; + d->lg_sta_num += a->lg_sta_num; +#ifdef CONFIG_TDLS + d->ld_tdls_num += a->ld_tdls_num; +#endif +#ifdef CONFIG_AP_MODE + d->ap_num += a->ap_num; + d->ld_ap_num += a->ld_ap_num; +#endif + d->adhoc_num += a->adhoc_num; + d->ld_adhoc_num += a->ld_adhoc_num; +#ifdef CONFIG_RTW_MESH + d->mesh_num += a->mesh_num; + d->ld_mesh_num += a->ld_mesh_num; +#endif + d->scan_num += a->scan_num; + d->scan_enter_num += a->scan_enter_num; + d->uwps_num += a->uwps_num; +#ifdef CONFIG_IOCTL_CFG80211 + #ifdef CONFIG_P2P + d->roch_num += a->roch_num; + #endif + d->mgmt_tx_num += a->mgmt_tx_num; +#endif +} + void dump_mi_status(void *sel, struct dvobj_priv *dvobj) { RTW_PRINT_SEL(sel, "== dvobj-iface_state ==\n"); RTW_PRINT_SEL(sel, "sta_num:%d\n", DEV_STA_NUM(dvobj)); RTW_PRINT_SEL(sel, "linking_sta_num:%d\n", DEV_STA_LG_NUM(dvobj)); RTW_PRINT_SEL(sel, "linked_sta_num:%d\n", DEV_STA_LD_NUM(dvobj)); +#ifdef CONFIG_TDLS + RTW_PRINT_SEL(sel, "linked_tdls_num:%d\n", DEV_TDLS_LD_NUM(dvobj)); +#endif +#ifdef CONFIG_AP_MODE RTW_PRINT_SEL(sel, "ap_num:%d\n", DEV_AP_NUM(dvobj)); + RTW_PRINT_SEL(sel, "starting_ap_num:%d\n", DEV_AP_STARTING_NUM(dvobj)); RTW_PRINT_SEL(sel, "linked_ap_num:%d\n", DEV_AP_LD_NUM(dvobj)); +#endif RTW_PRINT_SEL(sel, "adhoc_num:%d\n", DEV_ADHOC_NUM(dvobj)); RTW_PRINT_SEL(sel, "linked_adhoc_num:%d\n", DEV_ADHOC_LD_NUM(dvobj)); +#ifdef CONFIG_RTW_MESH + RTW_PRINT_SEL(sel, "mesh_num:%d\n", DEV_MESH_NUM(dvobj)); + RTW_PRINT_SEL(sel, "linked_mesh_num:%d\n", DEV_MESH_LD_NUM(dvobj)); +#endif #ifdef CONFIG_P2P - RTW_PRINT_SEL(sel, "p2p_device_num:%d\n", rtw_mi_stay_in_p2p_mode(dvobj->padapters[IFACE_ID0])); + RTW_PRINT_SEL(sel, "p2p_device_num:%d\n", DEV_P2P_DV_NUM(dvobj)); + RTW_PRINT_SEL(sel, "p2p_gc_num:%d\n", DEV_P2P_GC_NUM(dvobj)); + RTW_PRINT_SEL(sel, "p2p_go_num:%d\n", DEV_P2P_GO_NUM(dvobj)); #endif + RTW_PRINT_SEL(sel, "scan_num:%d\n", DEV_SCAN_NUM(dvobj)); + RTW_PRINT_SEL(sel, "under_wps_num:%d\n", DEV_WPS_NUM(dvobj)); #if defined(CONFIG_IOCTL_CFG80211) #if defined(CONFIG_P2P) RTW_PRINT_SEL(sel, "roch_num:%d\n", DEV_ROCH_NUM(dvobj)); #endif RTW_PRINT_SEL(sel, "mgmt_tx_num:%d\n", DEV_MGMT_TX_NUM(dvobj)); #endif - RTW_PRINT_SEL(sel, "under_wps_num:%d\n", DEV_WPS_NUM(dvobj)); RTW_PRINT_SEL(sel, "union_ch:%d\n", DEV_U_CH(dvobj)); RTW_PRINT_SEL(sel, "union_bw:%d\n", DEV_U_BW(dvobj)); RTW_PRINT_SEL(sel, "union_offset:%d\n", DEV_U_OFFSET(dvobj)); @@ -209,12 +367,9 @@ inline void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state) struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct mi_state *iface_state = &dvobj->iface_state; struct mi_state tmp_mstate; - u8 i; u8 u_ch, u_offset, u_bw; - _adapter *iface; if (state == WIFI_MONITOR_STATE - || state == WIFI_SITE_MONITOR || state == 0xFFFFFFFF ) return; @@ -252,11 +407,11 @@ u8 rtw_mi_check_status(_adapter *adapter, u8 type) switch (type) { case MI_LINKED: - if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_NUM(iface_state) || MSTATE_ADHOC_NUM(iface_state)) /*check_fwstate(&iface->mlmepriv, _FW_LINKED)*/ + if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_NUM(iface_state) || MSTATE_ADHOC_NUM(iface_state) || MSTATE_MESH_NUM(iface_state)) /*check_fwstate(&iface->mlmepriv, _FW_LINKED)*/ ret = _TRUE; break; case MI_ASSOC: - if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_LD_NUM(iface_state) || MSTATE_ADHOC_LD_NUM(iface_state)) + if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_LD_NUM(iface_state) || MSTATE_ADHOC_LD_NUM(iface_state) || MSTATE_MESH_LD_NUM(iface_state)) ret = _TRUE; break; case MI_UNDER_WPS: @@ -282,6 +437,17 @@ u8 rtw_mi_check_status(_adapter *adapter, u8 type) ret = _TRUE; break; +#ifdef CONFIG_RTW_MESH + case MI_MESH: + if (MSTATE_MESH_NUM(iface_state)) + ret = _TRUE; + break; + case MI_MESH_ASSOC: + if (MSTATE_MESH_LD_NUM(iface_state)) + ret = _TRUE; + break; +#endif + case MI_STA_NOLINK: /* this is misleading, but not used now */ if (MSTATE_STA_NUM(iface_state) && (!(MSTATE_STA_LD_NUM(iface_state) || MSTATE_STA_LG_NUM(iface_state)))) ret = _TRUE; @@ -301,28 +467,6 @@ u8 rtw_mi_check_status(_adapter *adapter, u8 type) return ret; } -u8 rtw_mi_mp_mode_check(_adapter *padapter) -{ -#ifdef CONFIG_MP_INCLUDED -#ifdef CONFIG_CONCURRENT_MODE - int i; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - _adapter *iface = NULL; - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - - if ((iface) && (iface->registrypriv.mp_mode == 1)) - return _TRUE; - } -#else - if (padapter->registrypriv.mp_mode == 1) - return _TRUE; -#endif -#endif /* CONFIG_MP_INCLUDED */ - return _FALSE; -} - /* * return value : 0 is failed or have not interface meet condition * return value : !0 is success or interface numbers which meet condition @@ -374,27 +518,54 @@ static u8 _rtw_mi_process_without_schk(_adapter *padapter, bool exclude_self, return ret; } -static u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data) +static u8 _rtw_mi_netif_caroff_qstop(_adapter *padapter, void *data) { - bool carrier_off = *(bool *)data; struct net_device *pnetdev = padapter->pnetdev; - if (carrier_off) - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); return _TRUE; } -u8 rtw_mi_netif_stop_queue(_adapter *padapter, bool carrier_off) +u8 rtw_mi_netif_caroff_qstop(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caroff_qstop); +} +u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caroff_qstop); +} + +static u8 _rtw_mi_netif_caron_qstart(_adapter *padapter, void *data) { - bool in_data = carrier_off; + struct net_device *pnetdev = padapter->pnetdev; - return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_netif_stop_queue); + rtw_netif_carrier_on(pnetdev); + rtw_netif_start_queue(pnetdev); + return _TRUE; +} +u8 rtw_mi_netif_caron_qstart(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caron_qstart); } -u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter, bool carrier_off) +u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter) { - bool in_data = carrier_off; + return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caron_qstart); +} + +static u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data) +{ + struct net_device *pnetdev = padapter->pnetdev; - return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_netif_stop_queue); + rtw_netif_stop_queue(pnetdev); + return _TRUE; +} +u8 rtw_mi_netif_stop_queue(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_stop_queue); +} +u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_stop_queue); } static u8 _rtw_mi_netif_wake_queue(_adapter *padapter, void *data) @@ -431,6 +602,23 @@ u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter) return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_on); } +static u8 _rtw_mi_netif_carrier_off(_adapter *padapter, void *data) +{ + struct net_device *pnetdev = padapter->pnetdev; + + if (pnetdev) + rtw_netif_carrier_off(pnetdev); + return _TRUE; +} +u8 rtw_mi_netif_carrier_off(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_off); +} +u8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_off); +} + static u8 _rtw_mi_scan_abort(_adapter *adapter, void *data) { bool bwait = *(bool *)data; @@ -456,32 +644,57 @@ void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait) _rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_scan_abort); } -static u8 _rtw_mi_start_drv_threads(_adapter *adapter, void *data) +static u32 _rtw_mi_start_drv_threads(_adapter *adapter, bool exclude_self) { - rtw_start_drv_threads(adapter); - return _TRUE; + int i; + _adapter *iface = NULL; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u32 _status = _SUCCESS; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + if ((exclude_self) && (iface == adapter)) + continue; + if (rtw_start_drv_threads(iface) == _FAIL) { + _status = _FAIL; + break; + } + } + } + return _status; } -void rtw_mi_start_drv_threads(_adapter *adapter) +u32 rtw_mi_start_drv_threads(_adapter *adapter) { - _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_start_drv_threads); + return _rtw_mi_start_drv_threads(adapter, _FALSE); } -void rtw_mi_buddy_start_drv_threads(_adapter *adapter) +u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter) { - _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_start_drv_threads); + return _rtw_mi_start_drv_threads(adapter, _TRUE); } -static u8 _rtw_mi_stop_drv_threads(_adapter *adapter, void *data) +static void _rtw_mi_stop_drv_threads(_adapter *adapter, bool exclude_self) { - rtw_stop_drv_threads(adapter); - return _TRUE; + int i; + _adapter *iface = NULL; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + if ((exclude_self) && (iface == adapter)) + continue; + rtw_stop_drv_threads(iface); + } + } } void rtw_mi_stop_drv_threads(_adapter *adapter) { - _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_stop_drv_threads); + _rtw_mi_stop_drv_threads(adapter, _FALSE); } void rtw_mi_buddy_stop_drv_threads(_adapter *adapter) { - _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_stop_drv_threads); + _rtw_mi_stop_drv_threads(adapter, _TRUE); } static u8 _rtw_mi_cancel_all_timer(_adapter *adapter, void *data) @@ -540,6 +753,30 @@ void rtw_mi_buddy_intf_stop(_adapter *adapter) _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_stop); } +#ifdef CONFIG_NEW_NETDEV_HDL +static u8 _rtw_mi_hal_iface_init(_adapter *padapter, void *data) +{ + if (rtw_hal_iface_init(padapter) == _SUCCESS) + return _TRUE; + return _FALSE; +} +u8 rtw_mi_hal_iface_init(_adapter *padapter) +{ + int i; + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + u8 ret = _TRUE; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface && iface->netif_up) + rtw_hal_iface_init(padapter); + } + return ret; +} +#endif + static u8 _rtw_mi_suspend_free_assoc_resource(_adapter *padapter, void *data) { return rtw_suspend_free_assoc_resource(padapter); @@ -588,58 +825,14 @@ void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms) _rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_set_scan_deny); } -#endif - -struct nulldata_param { - unsigned char *da; - unsigned int power_mode; - int try_cnt; - int wait_ms; -}; - -static u8 _rtw_mi_issue_nulldata(_adapter *padapter, void *data) -{ - struct nulldata_param *pnulldata_param = (struct nulldata_param *)data; - - if (is_client_associated_to_ap(padapter) == _TRUE) { - /* TODO: TDLS peers */ - issue_nulldata(padapter, pnulldata_param->da, pnulldata_param->power_mode, pnulldata_param->try_cnt, pnulldata_param->wait_ms); - return _TRUE; - } - return _FALSE; -} - -u8 rtw_mi_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) -{ - struct nulldata_param nparam; - - nparam.da = da; - nparam.power_mode = power_mode;/*0 or 1*/ - nparam.try_cnt = try_cnt; - nparam.wait_ms = wait_ms; - - return _rtw_mi_process(padapter, _FALSE, &nparam, _rtw_mi_issue_nulldata); -} -u8 rtw_mi_buddy_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) -{ - struct nulldata_param nparam; - - nparam.da = da; - nparam.power_mode = power_mode; - nparam.try_cnt = try_cnt; - nparam.wait_ms = wait_ms; - - return _rtw_mi_process(padapter, _TRUE, &nparam, _rtw_mi_issue_nulldata); -} +#endif /*CONFIG_SET_SCAN_DENY_TIMER*/ static u8 _rtw_mi_beacon_update(_adapter *padapter, void *data) { - struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; - - if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE + if (!MLME_IS_STA(padapter) && check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE) { - RTW_INFO(ADPT_FMT"-WIFI_FW_AP_STATE - update_beacon\n", ADPT_ARG(padapter)); - update_beacon(padapter, 0, NULL, _TRUE); + RTW_INFO(ADPT_FMT" - update_beacon\n", ADPT_ARG(padapter)); + update_beacon(padapter, 0xFF, NULL, _TRUE); } return _TRUE; } @@ -658,7 +851,7 @@ static u8 _rtw_mi_hal_dump_macaddr(_adapter *padapter, void *data) { u8 mac_addr[ETH_ALEN] = {0}; - rtw_hal_get_macaddr_port(padapter, mac_addr); + rtw_hal_get_hwreg(padapter, HW_VAR_MAC_ADDR, mac_addr); RTW_INFO(ADPT_FMT"MAC Address ="MAC_FMT"\n", ADPT_ARG(padapter), MAC_ARG(mac_addr)); return _TRUE; } @@ -925,20 +1118,6 @@ u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter) return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_dynamic_check_timer_handlder); } -static u8 _rtw_mi_dev_unload(_adapter *adapter, void *data) -{ - rtw_dev_unload(adapter); - return _TRUE; -} -u8 rtw_mi_dev_unload(_adapter *padapter) -{ - return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_dev_unload); -} -u8 rtw_mi_buddy_dev_unload(_adapter *padapter) -{ - return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_dev_unload); -} - static u8 _rtw_mi_dynamic_chk_wk_hdl(_adapter *adapter, void *data) { rtw_iface_dynamic_chk_wk_hdl(adapter); @@ -999,6 +1178,29 @@ u8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart) return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_sreset_adapter_hdl); } + +#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE) +void rtw_mi_ap_info_restore(_adapter *adapter) +{ + int i; + _adapter *iface; + struct mlme_priv *pmlmepriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + pmlmepriv = &iface->mlmepriv; + + if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) { + RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(iface), MLME_IS_AP(iface) ? "AP" : "MESH"); + rtw_iface_bcmc_sec_cam_map_restore(iface); + } + } + } +} +#endif /*#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE)*/ + u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart) { u8 in_data = bstart; @@ -1007,9 +1209,9 @@ u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart) } static u8 _rtw_mi_tx_beacon_hdl(_adapter *adapter, void *data) { - if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE - && check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE - ) { + if ((MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) + && check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE + ) { adapter->mlmepriv.update_bcn = _TRUE; #ifndef CONFIG_INTERRUPT_BASED_TXBCN #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) @@ -1032,7 +1234,7 @@ static u8 _rtw_mi_set_tx_beacon_cmd(_adapter *adapter, void *data) { struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) { if (pmlmepriv->update_bcn == _TRUE) set_tx_beacon_cmd(adapter); } @@ -1098,7 +1300,7 @@ _adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id) return dvobj->padapters[iface_id]; } -_adapter *rtw_get_iface_by_macddr(_adapter *padapter, u8 *mac_addr) +_adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr) { int i; _adapter *iface = NULL; @@ -1190,9 +1392,10 @@ void rtw_dbg_skb_process(_adapter *padapter, union recv_frame *precvframe, union static s32 _rtw_mi_buddy_clone_bcmc_packet(_adapter *adapter, union recv_frame *precvframe, u8 *pphy_status, union recv_frame *pcloneframe) { s32 ret = _SUCCESS; +#ifdef CONFIG_SKB_ALLOCATED u8 *pbuf = precvframe->u.hdr.rx_data; +#endif struct rx_pkt_attrib *pattrib = NULL; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); if (pcloneframe) { pcloneframe->u.hdr.adapter = adapter; @@ -1218,7 +1421,7 @@ static s32 _rtw_mi_buddy_clone_bcmc_packet(_adapter *adapter, union recv_frame * rtw_dbg_skb_process(adapter, precvframe, pcloneframe); #endif - if (pattrib->physt && pphy_status) + if (pphy_status) rx_query_phy_status(pcloneframe, pphy_status); ret = rtw_recv_entry(pcloneframe); @@ -1240,6 +1443,8 @@ void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvf struct recv_priv *precvpriv = &padapter->recvpriv;/*primary_padapter*/ _queue *pfree_recv_queue = &precvpriv->free_recv_queue; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u8 *fhead = get_recvframe_data(precvframe); + u8 type = GetFrameType(fhead); for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -1247,6 +1452,8 @@ void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvf continue; if (rtw_is_adapter_up(iface) == _FALSE || iface->registered == 0) continue; + if (type == WIFI_DATA_TYPE && !adapter_allow_bmc_data_rx(iface)) + continue; pcloneframe = rtw_alloc_recvframe(pfree_recv_queue); if (pcloneframe) { @@ -1283,6 +1490,45 @@ _adapter *rtw_mi_get_ap_adapter(_adapter *padapter) } #endif +u8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + int i; + _adapter *iface = NULL; + u8 ifbmp = 0; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + if (MLME_IS_STA(iface) && MLME_IS_ASOC(iface)) + ifbmp |= BIT(i); + } + + return ifbmp; +} + +u8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + int i; + _adapter *iface = NULL; + u8 ifbmp = 0; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + if (CHK_MLME_STATE(iface, WIFI_AP_STATE | WIFI_MESH_STATE) + && MLME_IS_ASOC(iface)) + ifbmp |= BIT(i); + } + + return ifbmp; +} + void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b) { #ifdef CONFIG_CONCURRENT_MODE @@ -1307,3 +1553,20 @@ void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b) } #endif } + +u8 rtw_mi_get_assoc_if_num(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 n_assoc_iface = 0; +#if 1 + u8 i; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE)) + n_assoc_iface++; + } +#else + n_assoc_iface = DEV_STA_LD_NUM(dvobj) + DEV_AP_NUM(dvobj) + DEV_ADHOC_NUM(dvobj) + DEV_MESH_NUM(dvobj); +#endif + return n_assoc_iface; +} diff --git a/core/rtw_mlme.c b/core/rtw_mlme.c index de77103..0a64818 100644 --- a/core/rtw_mlme.c +++ b/core/rtw_mlme.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_MLME_C_ #include @@ -29,15 +24,11 @@ void rtw_init_mlme_timer(_adapter *padapter) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - rtw_init_timer(&(pmlmepriv->assoc_timer), padapter, rtw_join_timeout_handler); - rtw_init_timer(&(pmlmepriv->scan_to_timer), padapter, rtw_scan_timeout_handler); - -#ifdef CONFIG_DFS_MASTER - rtw_init_timer(&(pmlmepriv->dfs_master_timer), padapter, rtw_dfs_master_timer_hdl, padapter); -#endif + rtw_init_timer(&(pmlmepriv->assoc_timer), padapter, rtw_join_timeout_handler, padapter); + rtw_init_timer(&(pmlmepriv->scan_to_timer), padapter, rtw_scan_timeout_handler, padapter); #ifdef CONFIG_SET_SCAN_DENY_TIMER - rtw_init_timer(&(pmlmepriv->set_scan_deny_timer), padapter, rtw_set_scan_deny_timer_hdl); + rtw_init_timer(&(pmlmepriv->set_scan_deny_timer), padapter, rtw_set_scan_deny_timer_hdl, padapter); #endif #ifdef RTK_DMP_PLATFORM @@ -52,6 +43,7 @@ sint _rtw_init_mlme_priv(_adapter *padapter) u8 *pbuf; struct wlan_network *pnetwork; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); sint res = _SUCCESS; @@ -70,11 +62,7 @@ sint _rtw_init_mlme_priv(_adapter *padapter) pmlmepriv->nic_hdl = (u8 *)padapter; pmlmepriv->pscanned = NULL; - /*pmlmepriv->fw_state = WIFI_STATION_STATE; */ /*Must sync with rtw_wdev_alloc()*/ - /*init_fwstate(pmlmepriv, WIFI_STATION_STATE);*/ - init_fwstate(pmlmepriv, WIFI_NULL_STATE);/*assigned interface role(STA/AP) must after execute set_opmode*/ - - /* wdev->iftype = NL80211_IFTYPE_STATION*/ + init_fwstate(pmlmepriv, WIFI_STATION_STATE); pmlmepriv->cur_network.network.InfrastructureMode = Ndis802_11AutoUnknown; pmlmepriv->scan_mode = SCAN_ACTIVE; /* 1: active, 0: pasive. Maybe someday we should rename this varable to "active_mode" (Jeff) */ @@ -86,7 +74,15 @@ sint _rtw_init_mlme_priv(_adapter *padapter) _rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID)); - pbuf = rtw_zvmalloc(MAX_BSS_CNT * (sizeof(struct wlan_network))); + if (padapter->registrypriv.max_bss_cnt != 0) + pmlmepriv->max_bss_cnt = padapter->registrypriv.max_bss_cnt; + else if (rfctl->max_chan_nums <= MAX_CHANNEL_NUM_2G) + pmlmepriv->max_bss_cnt = MAX_BSS_CNT; + else + pmlmepriv->max_bss_cnt = MAX_BSS_CNT + MAX_BSS_CNT; + + + pbuf = rtw_zvmalloc(pmlmepriv->max_bss_cnt * (sizeof(struct wlan_network))); if (pbuf == NULL) { res = _FAIL; @@ -96,7 +92,7 @@ sint _rtw_init_mlme_priv(_adapter *padapter) pnetwork = (struct wlan_network *)pbuf; - for (i = 0; i < MAX_BSS_CNT; i++) { + for (i = 0; i < pmlmepriv->max_bss_cnt; i++) { _rtw_init_listhead(&(pnetwork->list)); rtw_list_insert_tail(&(pnetwork->list), &(pmlmepriv->free_bss_pool.queue)); @@ -115,7 +111,7 @@ sint _rtw_init_mlme_priv(_adapter *padapter) #ifdef CONFIG_LAYER2_ROAMING #define RTW_ROAM_SCAN_RESULT_EXP_MS (5*1000) #define RTW_ROAM_RSSI_DIFF_TH 10 -#define RTW_ROAM_SCAN_INTERVAL_MS (10*1000) +#define RTW_ROAM_SCAN_INTERVAL (5) /* 5*(2 second)*/ #define RTW_ROAM_RSSI_THRESHOLD 70 pmlmepriv->roam_flags = 0 @@ -130,16 +126,20 @@ sint _rtw_init_mlme_priv(_adapter *padapter) pmlmepriv->roam_scanr_exp_ms = RTW_ROAM_SCAN_RESULT_EXP_MS; pmlmepriv->roam_rssi_diff_th = RTW_ROAM_RSSI_DIFF_TH; - pmlmepriv->roam_scan_int_ms = RTW_ROAM_SCAN_INTERVAL_MS; + pmlmepriv->roam_scan_int = RTW_ROAM_SCAN_INTERVAL; pmlmepriv->roam_rssi_threshold = RTW_ROAM_RSSI_THRESHOLD; + pmlmepriv->need_to_roam = _FALSE; + pmlmepriv->last_roaming = rtw_get_current_time(); #endif /* CONFIG_LAYER2_ROAMING */ #ifdef CONFIG_RTW_80211R - memset(&pmlmepriv->ftpriv, 0, sizeof(ft_priv)); - pmlmepriv->ftpriv.ft_flags = 0 - | RTW_FT_STA_SUPPORTED - | RTW_FT_STA_OVER_DS_SUPPORTED - ; + rtw_ft_info_init(&pmlmepriv->ft_roam); +#endif +#ifdef CONFIG_LAYER2_ROAMING +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) + rtw_roam_nb_info_init(padapter); + pmlmepriv->ch_cnt = 0; +#endif #endif rtw_init_mlme_timer(padapter); @@ -297,6 +297,7 @@ int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_ void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv) { + _adapter *adapter = mlme_to_adapter(pmlmepriv); if (NULL == pmlmepriv) { rtw_warn_on(1); goto exit; @@ -307,7 +308,7 @@ void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv) rtw_mfree_mlme_priv_lock(pmlmepriv); if (pmlmepriv->free_bss_buf) - rtw_vmfree(pmlmepriv->free_bss_buf, MAX_BSS_CNT * sizeof(struct wlan_network)); + rtw_vmfree(pmlmepriv->free_bss_buf, pmlmepriv->max_bss_cnt * sizeof(struct wlan_network)); } exit: return; @@ -384,6 +385,11 @@ struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue pnetwork->network_type = 0; pnetwork->fixed = _FALSE; pnetwork->last_scanned = rtw_get_current_time(); +#if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT + pnetwork->acnode_stime = 0; + pnetwork->acnode_notify_etime = 0; +#endif + pnetwork->aid = 0; pnetwork->join_res = 0; @@ -463,53 +469,6 @@ void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network * return; } - -/* - return the wlan_network with the matching addr - - Shall be calle under atomic context... to avoid possible racing condition... -*/ -struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr) -{ - - /* _irqL irqL; */ - _list *phead, *plist; - struct wlan_network *pnetwork = NULL; - u8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; - - - if (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) { - pnetwork = NULL; - goto exit; - } - - /* _enter_critical_bh(&scanned_queue->lock, &irqL); */ - - phead = get_list_head(scanned_queue); - plist = get_next(phead); - - while (plist != phead) { - pnetwork = LIST_CONTAINOR(plist, struct wlan_network , list); - - if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) - break; - - plist = get_next(plist); - } - - if (plist == phead) - pnetwork = NULL; - - /* _exit_critical_bh(&scanned_queue->lock, &irqL); */ - -exit: - - - return pnetwork; - -} - - void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall) { _irqL irqL; @@ -650,14 +609,44 @@ void rtw_free_network_queue(_adapter *dev, u8 isfreeall) _rtw_free_network_queue(dev, isfreeall); } -/* - return the wlan_network with the matching addr +struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr) +{ + _list *phead, *plist; + struct wlan_network *pnetwork = NULL; + u8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; - Shall be calle under atomic context... to avoid possible racing condition... -*/ -struct wlan_network *rtw_find_network(_queue *scanned_queue, u8 *addr) + if (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) { + pnetwork = NULL; + goto exit; + } + + phead = get_list_head(scanned_queue); + plist = get_next(phead); + + while (plist != phead) { + pnetwork = LIST_CONTAINOR(plist, struct wlan_network , list); + + if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) + break; + + plist = get_next(plist); + } + + if (plist == phead) + pnetwork = NULL; + +exit: + return pnetwork; +} + +struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr) { - struct wlan_network *pnetwork = _rtw_find_network(scanned_queue, addr); + struct wlan_network *pnetwork; + _irqL irqL; + + _enter_critical_bh(&scanned_queue->lock, &irqL); + pnetwork = _rtw_find_network(scanned_queue, addr); + _exit_critical_bh(&scanned_queue->lock, &irqL); return pnetwork; } @@ -709,15 +698,35 @@ int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature) return _TRUE; #endif - return ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && - /* (src->Configuration.DSConfig == dst->Configuration.DSConfig) && */ - ((_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) && - ((_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) && - ((s_cap & WLAN_CAPABILITY_IBSS) == - (d_cap & WLAN_CAPABILITY_IBSS)) && - ((s_cap & WLAN_CAPABILITY_BSS) == - (d_cap & WLAN_CAPABILITY_BSS))); - + /* Wi-Fi driver doesn't consider the situation of BCN and ProbRsp sent from the same hidden AP, + * it considers these two packets are sent from different AP. + * Therefore, the scan queue may store two scan results of the same hidden AP, likes below. + * + * index bssid ch RSSI SdBm Noise age flag ssid + * 1 00:e0:4c:55:50:01 153 -73 -73 0 7044 [WPS][ESS] RTK5G + * 3 00:e0:4c:55:50:01 153 -73 -73 0 7044 [WPS][ESS] + * + * Original rules will compare Ssid, SsidLength, MacAddress, s_cap, d_cap at the same time. + * Wi-Fi driver will assume that the BCN and ProbRsp sent from the same hidden AP are the same network + * after we add an additional rule to compare SsidLength and Ssid. + * It means the scan queue will not store two scan results of the same hidden AP, it only store ProbRsp. + * For customer request. + */ + + if (((_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) && + ((s_cap & WLAN_CAPABILITY_IBSS) == (d_cap & WLAN_CAPABILITY_IBSS)) && + ((s_cap & WLAN_CAPABILITY_BSS) == (d_cap & WLAN_CAPABILITY_BSS))) { + if ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && + (((_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) || //Case of normal AP + (is_all_null(src->Ssid.Ssid, src->Ssid.SsidLength) == _TRUE || is_all_null(dst->Ssid.Ssid, dst->Ssid.SsidLength) == _TRUE))) //Case of hidden AP + return _TRUE; + else if ((src->Ssid.SsidLength == 0 || dst->Ssid.SsidLength == 0)) //Case of hidden AP + return _TRUE; + else + return _FALSE; + } else { + return _FALSE; + } } struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network) @@ -739,7 +748,7 @@ struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_n if (plist == phead) found = NULL; -exit: + return found; } @@ -778,7 +787,7 @@ struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue) pwlan = LIST_CONTAINOR(plist, struct wlan_network, list); if (pwlan->fixed != _TRUE) { - if (oldest == NULL || time_after(oldest->last_scanned, pwlan->last_scanned)) + if (oldest == NULL || rtw_time_after(oldest->last_scanned, pwlan->last_scanned)) oldest = pwlan; } @@ -791,14 +800,15 @@ struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue) void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter *padapter, bool update_ie) { +#if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1 u8 ss_ori = dst->PhyInfo.SignalStrength; u8 sq_ori = dst->PhyInfo.SignalQuality; - long rssi_ori = dst->Rssi; - u8 ss_smp = src->PhyInfo.SignalStrength; - u8 sq_smp = src->PhyInfo.SignalQuality; long rssi_smp = src->Rssi; +#endif + long rssi_ori = dst->Rssi; + u8 sq_smp = src->PhyInfo.SignalQuality; u8 ss_final; u8 sq_final; long rssi_final; @@ -925,22 +935,21 @@ Caller must hold pmlmepriv->lock first. */ -void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) +bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) { _irqL irqL; _list *plist, *phead; ULONG bssid_ex_sz; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(adapter->wdinfo); #endif /* CONFIG_P2P */ _queue *queue = &(pmlmepriv->scanned_queue); struct wlan_network *pnetwork = NULL; - struct wlan_network *oldest = NULL; + struct wlan_network *choice = NULL; int target_find = 0; u8 feature = 0; - + bool update_ie = _FALSE; _enter_critical_bh(&queue->lock, &irqL); phead = get_list_head(queue); @@ -978,14 +987,27 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) } if (rtw_roam_flags(adapter)) { - /* TODO: don't select netowrk in the same ess as oldest if it's new enough*/ + /* TODO: don't select netowrk in the same ess as choice if it's new enough*/ + } + if (pnetwork->fixed) { + plist = get_next(plist); + continue; } + #ifdef CONFIG_RSSI_PRIORITY - if ((oldest == NULL) || (pnetwork->network.PhyInfo.SignalStrength < oldest->network.PhyInfo.SignalStrength)) - oldest = pnetwork; + if ((choice == NULL) || (pnetwork->network.PhyInfo.SignalStrength < choice->network.PhyInfo.SignalStrength)) + #ifdef CONFIG_RTW_MESH + if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter) + || !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network)) + #endif + choice = pnetwork; #else - if (oldest == NULL || time_after(oldest->last_scanned, pnetwork->last_scanned)) - oldest = pnetwork; + if (choice == NULL || rtw_time_after(choice->last_scanned, pnetwork->last_scanned)) + #ifdef CONFIG_RTW_MESH + if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter) + || !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network)) + #endif + choice = pnetwork; #endif plist = get_next(plist); @@ -997,12 +1019,12 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) /* if (rtw_end_of_queue_search(phead,plist)== _TRUE) { */ if (!target_find) { if (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) { - /* If there are no more slots, expire the oldest */ - /* list_del_init(&oldest->list); */ - pnetwork = oldest; - if (pnetwork == NULL) { - goto exit; - } + /* If there are no more slots, expire the choice */ + /* list_del_init(&choice->list); */ + pnetwork = choice; + if (pnetwork == NULL) + goto unlock_scan_queue; + #ifdef CONFIG_RSSI_PRIORITY RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue (rssi:%ld , ss:%d)\n", __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Rssi, pnetwork->network.PhyInfo.SignalStrength); @@ -1019,6 +1041,10 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) /* variable initialize */ pnetwork->fixed = _FALSE; pnetwork->last_scanned = rtw_get_current_time(); + #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT + pnetwork->acnode_stime = 0; + pnetwork->acnode_notify_etime = 0; + #endif pnetwork->network_type = 0; pnetwork->aid = 0; @@ -1031,10 +1057,8 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) /* Otherwise just pull from the free list */ pnetwork = rtw_alloc_network(pmlmepriv); /* will update scan_time */ - - if (pnetwork == NULL) { - goto exit; - } + if (pnetwork == NULL) + goto unlock_scan_queue; bssid_ex_sz = get_WLAN_BSSID_EX_sz(target); target->Length = bssid_ex_sz; @@ -1057,38 +1081,63 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) * be already expired. In this case we do the same as we found a new * net and call the new_net handler */ - bool update_ie = _TRUE; + #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT + systime last_scanned = pnetwork->last_scanned; + #endif pnetwork->last_scanned = rtw_get_current_time(); - /* target.Reserved[0]==1, means that scaned network is a bcn frame. */ - if ((pnetwork->network.IELength > target->IELength) && (target->Reserved[0] == 1)) + /* target.Reserved[0]==BSS_TYPE_BCN, means that scanned network is a bcn frame. */ + if ((pnetwork->network.IELength > target->IELength) && (target->Reserved[0] == BSS_TYPE_BCN)) update_ie = _FALSE; - /* probe resp(3) > beacon(1) > probe req(2) */ - if ((target->Reserved[0] != 2) && - (target->Reserved[0] >= pnetwork->network.Reserved[0]) - ) + if (MLME_IS_MESH(adapter) + /* probe resp(3) > beacon(1) > probe req(2) */ + || (target->Reserved[0] != BSS_TYPE_PROB_REQ + && target->Reserved[0] >= pnetwork->network.Reserved[0]) + ) update_ie = _TRUE; else update_ie = _FALSE; + #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT + if (!MLME_IS_MESH(adapter) || !MLME_IS_ASOC(adapter) + || pnetwork->network.Configuration.DSConfig != target->Configuration.DSConfig + || rtw_get_passing_time_ms(last_scanned) > adapter->mesh_cfg.peer_sel_policy.scanr_exp_ms + || !rtw_bss_is_same_mbss(&pnetwork->network, target) + ) { + pnetwork->acnode_stime = 0; + pnetwork->acnode_notify_etime = 0; + } + #endif update_network(&(pnetwork->network), target, adapter, update_ie); } -exit: + #if defined(CONFIG_RTW_MESH) && CONFIG_RTW_MESH_ACNODE_PREVENT + if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) + rtw_mesh_update_scanned_acnode_status(adapter, pnetwork); + #endif + +unlock_scan_queue: _exit_critical_bh(&queue->lock, &irqL); +#ifdef CONFIG_RTW_MESH + if (pnetwork && MLME_IS_MESH(adapter) + && check_fwstate(pmlmepriv, WIFI_ASOC_STATE) + && !check_fwstate(pmlmepriv, WIFI_SITE_MONITOR) + ) + rtw_chk_candidate_peer_notify(adapter, pnetwork); +#endif + + return update_ie; } void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork); void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) { - _irqL irqL; - struct mlme_priv *pmlmepriv = &(((_adapter *)adapter)->mlmepriv); + bool update_ie; /* _queue *queue = &(pmlmepriv->scanned_queue); */ - /* _enter_critical_bh(&queue->lock, &irqL); */ #if defined(CONFIG_P2P) && defined(CONFIG_P2P_REMOVE_GROUP_INFO) @@ -1099,9 +1148,11 @@ void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) rtw_bss_ex_del_wfd_ie(pnetwork); - update_current_network(adapter, pnetwork); + /* Wi-Fi driver will update the current network if the scan result of the connected AP be updated by scan. */ + update_ie = rtw_update_scanned_network(adapter, pnetwork); - rtw_update_scanned_network(adapter, pnetwork); + if (update_ie) + update_current_network(adapter, pnetwork); /* _exit_critical_bh(&queue->lock, &irqL); */ @@ -1220,7 +1271,7 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) _rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8); _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - ibss_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress); + ibss_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress); if (ibss_wlan) { _rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8); _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); @@ -1248,6 +1299,7 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) { _irqL irqL; + struct sitesurvey_parm parm; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); #ifdef CONFIG_RTW_80211R struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; @@ -1327,8 +1379,15 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(adapter)); if (rtw_to_roam(adapter) != 0) { + u8 ssc_chk = rtw_sitesurvey_condition_check(adapter, _FALSE); + + rtw_init_sitesurvey_parm(adapter, &parm); + _rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + parm.ssid_num = 1; + if (rtw_dec_to_roam(adapter) == 0 - || _SUCCESS != rtw_sitesurvey_cmd(adapter, &pmlmepriv->assoc_ssid, 1, NULL, 0) + || (ssc_chk != SS_ALLOW && ssc_chk != SS_DENY_BUSY_TRAFFIC) + || _SUCCESS != rtw_sitesurvey_cmd(adapter, &parm) ) { rtw_set_to_roam(adapter, 0); #ifdef CONFIG_INTEL_WIDI @@ -1338,7 +1397,7 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) RTW_INFO("change to widi listen\n"); } #endif /* CONFIG_INTEL_WIDI */ - rtw_free_assoc_resources(adapter, 1); + rtw_free_assoc_resources(adapter, _TRUE); rtw_indicate_disconnect(adapter, 0, _FALSE); } else pmlmepriv->to_join = _TRUE; @@ -1353,12 +1412,8 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) && check_fwstate(pmlmepriv, _FW_LINKED)) { if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) { #ifdef CONFIG_RTW_80211R - if (rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED)) { - start_clnt_ft_action(adapter, (u8 *)pmlmepriv->roam_network->network.MacAddress); - } else { - /*wait a little time to retrieve packets buffered in the current ap while scan*/ - _set_timer(&pmlmeext->ft_roam_timer, 30); - } + rtw_ft_start_roam(adapter, + (u8 *)pmlmepriv->roam_network->network.MacAddress); #else receive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress , WLAN_REASON_ACTIVE_ROAM, _FALSE); @@ -1402,6 +1457,122 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _FALSE); #endif +#ifdef CONFIG_RTW_MESH + #if CONFIG_RTW_MESH_OFFCH_CAND + if (rtw_mesh_offch_candidate_accepted(adapter)) { + u8 ch; + + ch = rtw_mesh_select_operating_ch(adapter); + if (ch && pmlmepriv->cur_network.network.Configuration.DSConfig != ch) { + u8 ifbmp = rtw_mi_get_ap_mesh_ifbmp(adapter); + + if (ifbmp) { + /* switch to selected channel */ + rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ifbmp, 0, ch, REQ_BW_ORI, REQ_OFFSET_NONE); + issue_probereq_ex(adapter, &pmlmepriv->cur_network.network.mesh_id, NULL, 0, 0, 0, 0); + } else + rtw_warn_on(1); + } + } + #endif +#endif /* CONFIG_RTW_MESH */ +} + +u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval) +{ + u8 ss_condition = SS_ALLOW; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; +#ifdef DBG_LA_MODE + struct registry_priv *registry_par = &adapter->registrypriv; +#endif + +#ifdef CONFIG_MP_INCLUDED + if (rtw_mp_mode_check(adapter)) { + RTW_INFO("%s ("ADPT_FMT") MP mode block Scan request\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_MP_MODE; + goto _exit; + } +#endif + +#ifdef DBG_LA_MODE + if(registry_par->la_mode_en == 1 && MLME_IS_ASOC(adapter)) { + RTW_INFO("%s ("ADPT_FMT") LA debug mode block Scan request\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_LA_MODE; + goto _exit; + } +#endif + +#ifdef CONFIG_RTW_REPEATER_SON + if (adapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) { + RTW_INFO("%s ("ADPT_FMT") blocking scan for under rson scanning process\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_RSON_SCANING; + goto _exit; + } +#endif +#ifdef CONFIG_IOCTL_CFG80211 + if (adapter_wdev_data(adapter)->block_scan == _TRUE) { + RTW_INFO("%s ("ADPT_FMT") wdev_priv.block_scan is set\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_BLOCK_SCAN; + goto _exit; + } +#endif + if (rtw_is_scan_deny(adapter)) { + RTW_INFO("%s ("ADPT_FMT") : scan deny\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_BY_DRV; + goto _exit; + } + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)){ + if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!! AP mode process WPS\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_SELF_AP_UNDER_WPS; + goto _exit; + } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under linking (fwstate=0x%x)\n", + caller, ADPT_ARG(adapter), pmlmepriv->fw_state); + ss_condition = SS_DENY_SELF_AP_UNDER_LINKING; + goto _exit; + } else if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!!AP mode under survey (fwstate=0x%x)\n", + caller, ADPT_ARG(adapter), pmlmepriv->fw_state); + ss_condition = SS_DENY_SELF_AP_UNDER_SURVEY; + goto _exit; + } + } else { + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under linking (fwstate=0x%x)\n", + caller, ADPT_ARG(adapter), pmlmepriv->fw_state); + ss_condition = SS_DENY_SELF_STA_UNDER_LINKING; + goto _exit; + } else if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!!STA mode under survey (fwstate=0x%x)\n", + caller, ADPT_ARG(adapter), pmlmepriv->fw_state); + ss_condition = SS_DENY_SELF_STA_UNDER_SURVEY; + goto _exit; + } + } + +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_mi_buddy_check_fwstate(adapter, _FW_UNDER_LINKING | WIFI_UNDER_WPS)) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under linking or wps\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_BUDDY_UNDER_LINK_WPS; + goto _exit; + + } else if (rtw_mi_buddy_check_fwstate(adapter, _FW_UNDER_SURVEY)) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!! buddy_intf under survey\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_BUDDY_UNDER_SURVEY; + goto _exit; + } +#endif /* CONFIG_CONCURRENT_MODE */ + + if (rtw_mi_busy_traffic_check(adapter, check_sc_interval)) { + RTW_INFO("%s ("ADPT_FMT") : scan abort!! ifs BusyTraffic == _TRUE\n", caller, ADPT_ARG(adapter)); + ss_condition = SS_DENY_BUSY_TRAFFIC; + goto _exit; + } + +_exit : + return ss_condition; } void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf) @@ -1441,27 +1612,28 @@ static void free_scanqueue(struct mlme_priv *pmlmepriv) } -void rtw_reset_rx_info(struct debug_priv *pdbgpriv) +void rtw_reset_rx_info(_adapter *adapter) { - pdbgpriv->dbg_rx_ampdu_drop_count = 0; - pdbgpriv->dbg_rx_ampdu_forced_indicate_count = 0; - pdbgpriv->dbg_rx_ampdu_loss_count = 0; - pdbgpriv->dbg_rx_dup_mgt_frame_drop_count = 0; - pdbgpriv->dbg_rx_ampdu_window_shift_cnt = 0; + struct recv_priv *precvpriv = &adapter->recvpriv; + + precvpriv->dbg_rx_ampdu_drop_count = 0; + precvpriv->dbg_rx_ampdu_forced_indicate_count = 0; + precvpriv->dbg_rx_ampdu_loss_count = 0; + precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0; + precvpriv->dbg_rx_ampdu_window_shift_cnt = 0; + precvpriv->dbg_rx_drop_count = 0; + precvpriv->dbg_rx_conflic_mac_addr_cnt = 0; } /* *rtw_free_assoc_resources: the caller has to lock pmlmepriv->lock */ -void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) +void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue) { _irqL irqL; struct wlan_network *pwlan = NULL; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct sta_priv *pstapriv = &adapter->stapriv; struct wlan_network *tgt_network = &pmlmepriv->cur_network; - struct dvobj_priv *psdpriv = adapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; #ifdef CONFIG_TDLS @@ -1469,7 +1641,7 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) #endif /* CONFIG_TDLS */ - RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT"ssid=%s\n", + RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT" ssid=%s\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { @@ -1478,18 +1650,15 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); #ifdef CONFIG_TDLS - if (ptdlsinfo->link_established == _TRUE) { + rtw_free_all_tdls_sta(adapter, _TRUE); + rtw_reset_tdls_info(adapter); + + if (ptdlsinfo->link_established == _TRUE) rtw_tdls_cmd(adapter, NULL, TDLS_RS_RCR); - rtw_reset_tdls_info(adapter); - rtw_free_all_stainfo(adapter); - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - } else #endif /* CONFIG_TDLS */ - { - /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ - rtw_free_stainfo(adapter, psta); - } + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + rtw_free_stainfo(adapter, psta); /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ } @@ -1510,26 +1679,27 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) if (lock_scanned_queue) _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - pwlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, tgt_network); - if ((pwlan) && (!check_fwstate(pmlmepriv, WIFI_UNDER_WPS))) { - pwlan->fixed = _FALSE; + if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS) || (pmlmepriv->wpa_phase == _TRUE)){ + RTW_INFO("Dont free disconnecting network of scanned_queue due to uner %s %s phase\n\n", + check_fwstate(pmlmepriv, WIFI_UNDER_WPS) ? "WPS" : "", + (pmlmepriv->wpa_phase == _TRUE) ? "WPA" : ""); + } else { + pwlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, tgt_network); + if (pwlan) { + pwlan->fixed = _FALSE; - RTW_INFO("free disconnecting network of scanned_queue\n"); - rtw_free_network_nolock(adapter, pwlan); + RTW_INFO("Free disconnecting network of scanned_queue\n"); + rtw_free_network_nolock(adapter, pwlan); #ifdef CONFIG_P2P - if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) { - rtw_mi_set_scan_deny(adapter, 2000); - /* rtw_clear_scan_deny(adapter); */ - } + if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) { + rtw_set_scan_deny(adapter, 2000); + /* rtw_clear_scan_deny(adapter); */ + } #endif /* CONFIG_P2P */ - } else { - if (pwlan == NULL) - RTW_INFO("free disconnecting network of scanned_queue failed due to pwlan== NULL\n\n"); - if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) - RTW_INFO("donot free disconnecting network of scanned_queue when WIFI_UNDER_WPS\n\n"); + } else + RTW_ERR("Free disconnecting network of scanned_queue failed due to pwlan == NULL\n\n"); } - if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) && (adapter->stapriv.asoc_sta_count == 1)) /*||check_fwstate(pmlmepriv, WIFI_STATION_STATE)*/) { if (pwlan) @@ -1541,7 +1711,7 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) adapter->securitypriv.key_mask = 0; - rtw_reset_rx_info(pdbgpriv); + rtw_reset_rx_info(adapter); } @@ -1552,9 +1722,6 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) void rtw_indicate_connect(_adapter *padapter) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - - pmlmepriv->to_join = _FALSE; @@ -1564,16 +1731,7 @@ void rtw_indicate_connect(_adapter *padapter) rtw_led_control(padapter, LED_CTL_LINK); - -#ifdef CONFIG_DRVEXT_MODULE - if (padapter->drvextpriv.enable_wpa) - indicate_l2_connect(padapter); - else -#endif - { - rtw_os_indicate_connect(padapter); - } - + rtw_os_indicate_connect(padapter); } rtw_set_to_roam(padapter, 0); @@ -1584,7 +1742,7 @@ void rtw_indicate_connect(_adapter *padapter) RTW_INFO("change to widi listen\n"); } #endif /* CONFIG_INTEL_WIDI */ - if (!check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE)) + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) rtw_mi_set_scan_deny(padapter, 3000); @@ -1596,18 +1754,21 @@ void rtw_indicate_connect(_adapter *padapter) */ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated) { - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); +#ifdef CONFIG_WAPI_SUPPORT struct sta_info *psta; struct sta_priv *pstapriv = &padapter->stapriv; +#endif u8 *wps_ie = NULL; uint wpsie_len = 0; + if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) + pmlmepriv->wpa_phase = _TRUE; - - _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS); + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS | WIFI_OP_CH_SWITCHING | WIFI_UNDER_KEY_HANDSHAKE); /* force to clear cur_network_scanned's SELECTED REGISTRAR */ if (pmlmepriv->cur_network_scanned) { @@ -1633,7 +1794,7 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate #ifdef CONFIG_WAPI_SUPPORT psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) - rtw_wapi_return_one_sta_info(padapter, psta->hwaddr); + rtw_wapi_return_one_sta_info(padapter, psta->cmn.mac_addr); else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) rtw_wapi_return_all_sta_info(padapter); @@ -1694,7 +1855,7 @@ inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted) static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms) { - u32 start; + systime start; u32 pass_ms; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); @@ -1735,17 +1896,10 @@ static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms) void rtw_scan_wait_completed(_adapter *adapter) { - u32 scan_to = SCANNING_TIMEOUT; - -#ifdef CONFIG_SCAN_BACKOP - if (is_supported_5g(adapter->registrypriv.wireless_mode) - && IsSupported24G(adapter->registrypriv.wireless_mode)) /*dual band*/ - scan_to = CONC_SCANNING_TIMEOUT_DUAL_BAND; - else /*single band*/ - scan_to = CONC_SCANNING_TIMEOUT_SINGLE_BAND; -#endif /* CONFIG_SCAN_BACKOP */ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct ss_res *ss = &pmlmeext->sitesurvey_res; - _rtw_wait_scan_done(adapter, _FALSE, scan_to); + _rtw_wait_scan_done(adapter, _FALSE, ss->scan_timeout_ms); } u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms) @@ -1767,10 +1921,59 @@ void rtw_scan_abort(_adapter *adapter) rtw_scan_abort_timeout(adapter, 200); } +static u32 _rtw_wait_join_done(_adapter *adapter, u8 abort, u32 timeout_ms) +{ + systime start; + u32 pass_ms; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + + start = rtw_get_current_time(); + + pmlmeext->join_abort = abort; + if (abort) + set_link_timer(pmlmeext, 1); + + while (rtw_get_passing_time_ms(start) <= timeout_ms + && (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) + #ifdef CONFIG_IOCTL_CFG80211 + || rtw_cfg80211_is_connect_requested(adapter) + #endif + ) + ) { + if (RTW_CANNOT_RUN(adapter)) + break; + + RTW_INFO(FUNC_ADPT_FMT" linking...\n", FUNC_ADPT_ARG(adapter)); + rtw_msleep_os(20); + } + + if (abort) { + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) + #ifdef CONFIG_IOCTL_CFG80211 + || rtw_cfg80211_is_connect_requested(adapter) + #endif + ) { + if (!RTW_CANNOT_RUN(adapter)) + RTW_INFO(FUNC_ADPT_FMT" waiting for join_abort time out!\n", FUNC_ADPT_ARG(adapter)); + } + } + + pmlmeext->join_abort = 0; + pass_ms = rtw_get_passing_time_ms(start); + + return pass_ms; +} + +u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms) +{ + return _rtw_wait_join_done(adapter, _TRUE, timeout_ms); +} + static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork) { int i; - struct sta_info *bmc_sta, *psta = NULL; + struct sta_info *psta = NULL; struct recv_reorder_ctrl *preorder_ctrl; struct sta_priv *pstapriv = &padapter->stapriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; @@ -1782,58 +1985,51 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl if (psta) { /* update ptarget_sta */ RTW_INFO("%s\n", __FUNCTION__); - psta->aid = pnetwork->join_res; - -#if 0 /* alloc macid when call rtw_alloc_stainfo(), and release macid when call rtw_free_stainfo() */ -#ifdef CONFIG_CONCURRENT_MODE - - if (PRIMARY_ADAPTER == padapter->adapter_type) - psta->mac_id = 0; - else - psta->mac_id = 2; -#else - psta->mac_id = 0; -#endif -#endif /* removed */ + psta->cmn.aid = pnetwork->join_res; update_sta_info(padapter, psta); /* update station supportRate */ psta->bssratelen = rtw_get_rateset_len(pnetwork->network.SupportedRates); _rtw_memcpy(psta->bssrateset, pnetwork->network.SupportedRates, psta->bssratelen); - rtw_hal_update_sta_rate_mask(padapter, psta); + rtw_hal_update_sta_ra_info(padapter, psta); psta->wireless_mode = pmlmeext->cur_wireless_mode; - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); - + rtw_hal_update_sta_wset(padapter, psta); /* sta mode */ rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); /* security related */ #ifdef CONFIG_RTW_80211R - if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (psta->ft_pairwise_key_installed == _FALSE)) { + if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) + && (psta->ft_pairwise_key_installed == _FALSE)) { #else if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { #endif + u8 *ie; + sint ie_len; + u8 mfp_opt = MFP_NO; + padapter->securitypriv.binstallGrpkey = _FALSE; padapter->securitypriv.busetkipkey = _FALSE; padapter->securitypriv.bgrpkey_handshake = _FALSE; + ie = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, WLAN_EID_RSN + , &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_)); + if (ie && ie_len > 0 + && rtw_parse_wpa2_ie(ie, ie_len + 2, NULL, NULL, NULL, &mfp_opt) == _SUCCESS + ) { + if (padapter->securitypriv.mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL) + psta->flags |= WLAN_STA_MFP; + } + psta->ieee8021x_blocked = _TRUE; psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype)); - _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype)); _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype)); - - _rtw_memset((u8 *)&psta->dot11txpn, 0, sizeof(union pn48)); - psta->dot11txpn.val = psta->dot11txpn.val + 1; -#ifdef CONFIG_IEEE80211W - _rtw_memset((u8 *)&psta->dot11wtxpn, 0, sizeof(union pn48)); -#endif /* CONFIG_IEEE80211W */ - _rtw_memset((u8 *)&psta->dot11rxpn, 0, sizeof(union pn48)); } /* Commented by Albert 2012/07/21 */ @@ -1845,7 +2041,7 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl } - /* for A-MPDU Rx reordering buffer control for bmc_sta & sta_info */ + /* for A-MPDU Rx reordering buffer control for sta_info */ /* if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */ /* todo: check if AP can send A-MPDU packets */ for (i = 0; i < 16 ; i++) { @@ -1853,33 +2049,19 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl preorder_ctrl = &psta->recvreorder_ctrl[i]; preorder_ctrl->enable = _FALSE; preorder_ctrl->indicate_seq = 0xffff; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq); -#endif + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%u\n" + , FUNC_ADPT_ARG(padapter), i, preorder_ctrl->indicate_seq); + #endif preorder_ctrl->wend_b = 0xffff; preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */ preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; } + } - - bmc_sta = rtw_get_bcmc_stainfo(padapter); - if (bmc_sta) { - for (i = 0; i < 16 ; i++) { - /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */ - preorder_ctrl = &bmc_sta->recvreorder_ctrl[i]; - preorder_ctrl->enable = _FALSE; - preorder_ctrl->indicate_seq = 0xffff; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq); +#ifdef CONFIG_RTW_80211K + _rtw_memcpy(&psta->rm_en_cap, pnetwork->network.PhyInfo.rm_en_cap, 5); #endif - preorder_ctrl->wend_b = 0xffff; - preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */ - preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; - } - } - } return psta; @@ -1890,12 +2072,12 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *ptarget_wlan, struct wlan_network *pnetwork) { struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct security_priv *psecuritypriv = &padapter->securitypriv; struct wlan_network *cur_network = &(pmlmepriv->cur_network); + sint tmp_fw_state = 0x0; RTW_INFO("%s\n", __FUNCTION__); - - /* why not use ptarget_wlan?? */ _rtw_memcpy(&cur_network->network, &pnetwork->network, pnetwork->network.Length); /* some IEs in pnetwork is wrong, so we should use ptarget_wlan IEs */ @@ -1929,13 +2111,15 @@ static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network * switch (pnetwork->network.InfrastructureMode) { case Ndis802_11Infrastructure: + /* Check encryption */ + if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) + tmp_fw_state = tmp_fw_state | WIFI_UNDER_KEY_HANDSHAKE; + + if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) + tmp_fw_state = tmp_fw_state | WIFI_UNDER_WPS; + + init_fwstate(pmlmepriv, WIFI_STATION_STATE | tmp_fw_state); - if (pmlmepriv->fw_state & WIFI_UNDER_WPS) - /*pmlmepriv->fw_state = WIFI_STATION_STATE|WIFI_UNDER_WPS;*/ - init_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_UNDER_WPS); - else - /*pmlmepriv->fw_state = WIFI_STATION_STATE;*/ - init_fwstate(pmlmepriv, WIFI_STATION_STATE); break; case Ndis802_11IBSS: /*pmlmepriv->fw_state = WIFI_ADHOC_STATE;*/ @@ -1963,9 +2147,9 @@ static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network * * if join_res > 0, update "cur_network->network" from "pnetwork->network" if (ptarget_wlan !=NULL). */ /* #define REJOIN */ -void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) +void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status) { - _irqL irqL, irqL2; + _irqL irqL; static u8 retry = 0; struct sta_info *ptarget_sta = NULL, *pcur_sta = NULL; struct sta_priv *pstapriv = &adapter->stapriv; @@ -2022,9 +2206,9 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) /* s1. find ptarget_wlan */ if (check_fwstate(pmlmepriv, _FW_LINKED)) { if (the_same_macaddr == _TRUE) - ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); else { - pcur_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + pcur_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); if (pcur_wlan) pcur_wlan->fixed = _FALSE; @@ -2035,7 +2219,7 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */ } - ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress); + ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { if (ptarget_wlan) ptarget_wlan->fixed = _TRUE; @@ -2089,9 +2273,10 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) } else if (pnetwork->join_res == -4) { rtw_reset_securitypriv(adapter); + pmlmepriv->join_status = status; _set_timer(&pmlmepriv->assoc_timer, 1); - /* rtw_free_assoc_resources(adapter, 1); */ + /* rtw_free_assoc_resources(adapter, _TRUE); */ if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _TRUE) { _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); @@ -2114,9 +2299,9 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) rtw_indicate_connect(adapter); } else { #endif - + pmlmepriv->join_status = status; _set_timer(&pmlmepriv->assoc_timer, 1); - /* rtw_free_assoc_resources(adapter, 1); */ + /* rtw_free_assoc_resources(adapter, _TRUE); */ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); #ifdef REJOIN @@ -2154,21 +2339,21 @@ void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool conn return; } - if (sta->mac_id >= macid_ctl->num) { + if (sta->cmn.mac_id >= macid_ctl->num) { RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n" - , FUNC_ADPT_ARG(adapter), sta->mac_id); + , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id); rtw_warn_on(1); return; } - if (!rtw_macid_is_used(macid_ctl, sta->mac_id)) { + if (!rtw_macid_is_used(macid_ctl, sta->cmn.mac_id)) { RTW_PRINT(FUNC_ADPT_FMT" macid:%u not is used, set connected to 0\n" - , FUNC_ADPT_ARG(adapter), sta->mac_id); + , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id); connected = 0; rtw_warn_on(1); } - if (connected && !rtw_macid_is_bmc(macid_ctl, sta->mac_id)) { + if (connected && !rtw_macid_is_bmc(macid_ctl, sta->cmn.mac_id)) { miracast_enabled = STA_OP_WFD_MODE(sta) != 0 && is_miracast_enabled(adapter); miracast_sink = miracast_enabled && (STA_OP_WFD_MODE(sta) & MIRACAST_SINK); @@ -2177,39 +2362,41 @@ void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool conn role = H2C_MSR_ROLE_TDLS; else #endif - if (MLME_IS_STA(adapter)) { - if (MLME_IS_GC(adapter)) - role = H2C_MSR_ROLE_GO; - else - role = H2C_MSR_ROLE_AP; - } else if (MLME_IS_AP(adapter)) { - if (MLME_IS_GO(adapter)) - role = H2C_MSR_ROLE_GC; - else - role = H2C_MSR_ROLE_STA; - } else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter)) - role = H2C_MSR_ROLE_ADHOC; + if (MLME_IS_STA(adapter)) { + if (MLME_IS_GC(adapter)) + role = H2C_MSR_ROLE_GO; + else + role = H2C_MSR_ROLE_AP; + } else if (MLME_IS_AP(adapter)) { + if (MLME_IS_GO(adapter)) + role = H2C_MSR_ROLE_GC; + else + role = H2C_MSR_ROLE_STA; + } else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter)) + role = H2C_MSR_ROLE_ADHOC; + else if (MLME_IS_MESH(adapter)) + role = H2C_MSR_ROLE_MESH; #ifdef CONFIG_WFD if (role == H2C_MSR_ROLE_GC - || role == H2C_MSR_ROLE_GO - || role == H2C_MSR_ROLE_TDLS - ) { + || role == H2C_MSR_ROLE_GO + || role == H2C_MSR_ROLE_TDLS + ) { if (adapter->wfd_info.rtsp_ctrlport - || adapter->wfd_info.tdls_rtsp_ctrlport - || adapter->wfd_info.peer_rtsp_ctrlport) + || adapter->wfd_info.tdls_rtsp_ctrlport + || adapter->wfd_info.peer_rtsp_ctrlport) rtw_wfd_st_switch(sta, 1); } #endif } rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter - , connected - , miracast_enabled - , miracast_sink - , role - , sta->mac_id - ); + , connected + , miracast_enabled + , miracast_sink + , role + , sta->cmn.mac_id + ); } u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected) @@ -2277,7 +2464,7 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) #endif #if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) { psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr); if (psta) { u8 *passoc_req = NULL; @@ -2285,35 +2472,39 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) rtw_sta_media_status_rpt(adapter, psta, 1); -#ifndef CONFIG_AUTO_AP_MODE +#ifdef CONFIG_MCC_MODE + rtw_hal_mcc_update_macid_bitmap(adapter, psta->cmn.mac_id, _TRUE); +#endif /* CONFIG_MCC_MODE */ +#ifndef CONFIG_AUTO_AP_MODE ap_sta_info_defer_update(adapter, psta); - /* report to upper layer */ - RTW_INFO("indicate_sta_assoc_event to upper layer - hostapd\n"); -#ifdef CONFIG_IOCTL_CFG80211 - _enter_critical_bh(&psta->lock, &irqL); - if (psta->passoc_req && psta->assoc_req_len > 0) { - passoc_req = rtw_zmalloc(psta->assoc_req_len); - if (passoc_req) { - assoc_req_len = psta->assoc_req_len; - _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len); - - rtw_mfree(psta->passoc_req , psta->assoc_req_len); - psta->passoc_req = NULL; - psta->assoc_req_len = 0; + if (!MLME_IS_MESH(adapter)) { + /* report to upper layer */ + RTW_INFO("indicate_sta_assoc_event to upper layer - hostapd\n"); + #ifdef CONFIG_IOCTL_CFG80211 + _enter_critical_bh(&psta->lock, &irqL); + if (psta->passoc_req && psta->assoc_req_len > 0) { + passoc_req = rtw_zmalloc(psta->assoc_req_len); + if (passoc_req) { + assoc_req_len = psta->assoc_req_len; + _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len); + + rtw_mfree(psta->passoc_req , psta->assoc_req_len); + psta->passoc_req = NULL; + psta->assoc_req_len = 0; + } } - } - _exit_critical_bh(&psta->lock, &irqL); - - if (passoc_req && assoc_req_len > 0) { - rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len); + _exit_critical_bh(&psta->lock, &irqL); - rtw_mfree(passoc_req, assoc_req_len); + if (passoc_req && assoc_req_len > 0) { + rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len); + rtw_mfree(passoc_req, assoc_req_len); + } + #else /* !CONFIG_IOCTL_CFG80211 */ + rtw_indicate_sta_assoc_event(adapter, psta); + #endif /* !CONFIG_IOCTL_CFG80211 */ } -#else /* !CONFIG_IOCTL_CFG80211 */ - rtw_indicate_sta_assoc_event(adapter, psta); -#endif /* !CONFIG_IOCTL_CFG80211 */ #endif /* !CONFIG_AUTO_AP_MODE */ #ifdef CONFIG_BEAMFORMING @@ -2335,8 +2526,6 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) goto exit; } - rtw_hal_set_odm_var(adapter, HAL_ODM_STA_INFO, psta, _TRUE); - rtw_sta_media_status_rpt(adapter, psta, 1); if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) @@ -2351,7 +2540,7 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) { if (adapter->stapriv.asoc_sta_count == 2) { _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); pmlmepriv->cur_network_scanned = ptarget_wlan; if (ptarget_wlan) ptarget_wlan->fixed = _TRUE; @@ -2406,7 +2595,46 @@ void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf) #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_RTW_80211R -void rtw_update_ft_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork) +void rtw_ft_info_init(struct ft_roam_info *pft) +{ + _rtw_memset(pft, 0, sizeof(struct ft_roam_info)); + pft->ft_flags = 0 + | RTW_FT_EN + | RTW_FT_OTD_EN +#ifdef CONFIG_RTW_BTM_ROAM + | RTW_FT_BTM_ROAM +#endif + ; + pft->ft_updated_bcn = _FALSE; +} + +u8 rtw_ft_chk_roaming_candidate( + _adapter *padapter, struct wlan_network *competitor) +{ + u8 *pmdie; + u32 mdie_len = 0; + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + + if (!(pmdie = rtw_get_ie(&competitor->network.IEs[12], + _MDIE_, &mdie_len, competitor->network.IELength-12))) + return _FALSE; + + if (!_rtw_memcmp(&pft_roam->mdid, (pmdie+2), 2)) + return _FALSE; + + /*The candidate don't support over-the-DS*/ + if (rtw_ft_valid_otd_candidate(padapter, pmdie)) { + RTW_INFO("FT: ignore the candidate(" + MAC_FMT ") for over-the-DS\n", + MAC_ARG(competitor->network.MacAddress)); + rtw_ft_clr_flags(padapter, RTW_FT_PEER_OTD_EN); + return _FALSE; + } + + return _TRUE; +} + +void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork) { struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta = NULL; @@ -2423,37 +2651,31 @@ void rtw_update_ft_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork) psta->ieee8021x_blocked = _TRUE; psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; - psta->dot11txpn.val = psta->dot11txpn.val + 1; _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype)); _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype)); _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype)); - _rtw_memset((u8 *)&psta->dot11txpn, 0, sizeof(union pn48)); -#ifdef CONFIG_IEEE80211W - _rtw_memset((u8 *)&psta->dot11wtxpn, 0, sizeof(union pn48)); -#endif - _rtw_memset((u8 *)&psta->dot11rxpn, 0, sizeof(union pn48)); } } void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf) { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct stassoc_event *pstassoc = (struct stassoc_event *)pbuf; - ft_priv *pftpriv = &pmlmepriv->ftpriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct stassoc_event *pstassoc = (struct stassoc_event *)pbuf; + struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network); struct cfg80211_ft_event_params ft_evt_parms; _irqL irqL; _rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms)); - rtw_update_ft_stainfo(padapter, pnetwork); - ft_evt_parms.ies_len = pftpriv->ft_event.ies_len; + rtw_ft_update_stainfo(padapter, pnetwork); + ft_evt_parms.ies_len = pft_roam->ft_event.ies_len; ft_evt_parms.ies = rtw_zmalloc(ft_evt_parms.ies_len); if (ft_evt_parms.ies) - _rtw_memcpy((void *)ft_evt_parms.ies, pftpriv->ft_event.ies, ft_evt_parms.ies_len); + _rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len); else goto err_2; @@ -2463,17 +2685,14 @@ void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf) else goto err_1; - ft_evt_parms.ric_ies = pftpriv->ft_event.ric_ies; - ft_evt_parms.ric_ies_len = pftpriv->ft_event.ric_ies_len; - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - rtw_set_ft_status(padapter, RTW_FT_AUTHENTICATED_STA); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies; + ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len; + rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL); rtw_cfg80211_ft_event(padapter, &ft_evt_parms); RTW_INFO("%s: to "MAC_FMT"\n", __func__, MAC_ARG(ft_evt_parms.target_ap)); - rtw_mfree((u8 *)pftpriv->ft_event.target_ap, ETH_ALEN); + rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN); err_1: rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len); err_2: @@ -2481,23 +2700,99 @@ void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf) } #endif +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) +void rtw_roam_nb_info_init(_adapter *padapter) +{ + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + + _rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt)); + _rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list)); + _rtw_memset(&pnb->roam_target_addr, 0, ETH_ALEN); + pnb->nb_rpt_valid = _FALSE; + pnb->nb_rpt_ch_list_num = 0; + pnb->preference_en = _FALSE; + pnb->nb_rpt_is_same = _TRUE; + pnb->last_nb_rpt_entries = 0; +#ifdef CONFIG_RTW_WNM + rtw_init_timer(&pnb->roam_scan_timer, + padapter, rtw_wnm_roam_scan_hdl, + padapter); +#endif +} + +u8 rtw_roam_nb_scan_list_set( + _adapter *padapter, struct sitesurvey_parm *pparm) +{ + u8 ret = _FALSE; + u32 i; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct roam_nb_info *pnb = &(pmlmepriv->nb_info); + + if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) + return ret; + + if (!pmlmepriv->need_to_roam) + return ret; + + if ((!pmlmepriv->nb_info.nb_rpt_valid) || (!pnb->nb_rpt_ch_list_num)) + return ret; + + if (!pparm) + return ret; + + rtw_init_sitesurvey_parm(padapter, pparm); + if (rtw_roam_busy_scan(padapter, pnb)) { + pparm->ch_num = 1; + pparm->ch[pmlmepriv->ch_cnt].hw_value = + pnb->nb_rpt_ch_list[pmlmepriv->ch_cnt].hw_value; + pmlmepriv->ch_cnt++; + ret = _TRUE; + if (pmlmepriv->ch_cnt == pnb->nb_rpt_ch_list_num) { + pmlmepriv->nb_info.nb_rpt_valid = _FALSE; + pmlmepriv->ch_cnt = 0; + } + goto set_bssid_list; + } + + pparm->ch_num = (pnb->nb_rpt_ch_list_num > RTW_CHANNEL_SCAN_AMOUNT)? + (RTW_CHANNEL_SCAN_AMOUNT):(pnb->nb_rpt_ch_list_num); + for (i=0; ich_num; i++) { + pparm->ch[i].hw_value = pnb->nb_rpt_ch_list[i].hw_value; + pparm->ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN; + } + + pmlmepriv->nb_info.nb_rpt_valid = _FALSE; + pmlmepriv->ch_cnt = 0; + ret = _TRUE; + +set_bssid_list: + rtw_set_802_11_bssid_list_scan(padapter, pparm); + return ret; +} +#endif + void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id) { struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; - RTW_INFO("%s "ADPT_FMT" - mac_id=%d\n", __func__, ADPT_ARG(adapter), mac_id); - if (mac_id >= 0 && mac_id < macid_ctl->num) { - rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id); - /* - * For safety, prevent from keeping macid sleep. - * If we can sure all power mode enter/leave are paired, - * this check can be removed. - * Lucas@20131113 - */ - /* wakeup macid after disconnect. */ - /*if (MLME_IS_STA(adapter))*/ - rtw_hal_macid_wakeup(adapter, mac_id); + u8 id_is_shared = mac_id == RTW_DEFAULT_MGMT_MACID; /* TODO: real shared macid judgment */ + + RTW_INFO(FUNC_ADPT_FMT" - mac_id=%d%s\n", FUNC_ADPT_ARG(adapter) + , mac_id, id_is_shared ? " shared" : ""); + + if (!id_is_shared) { + rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id); + /* + * For safety, prevent from keeping macid sleep. + * If we can sure all power mode enter/leave are paired, + * this check can be removed. + * Lucas@20131113 + */ + /* wakeup macid after disconnect. */ + /*if (MLME_IS_STA(adapter))*/ + rtw_hal_macid_wakeup(adapter, mac_id); + } } else { RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n" , FUNC_ADPT_ARG(adapter), mac_id); @@ -2513,7 +2808,7 @@ void rtw_sta_mstatus_report(_adapter *adapter) if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); if (psta) - rtw_sta_mstatus_disc_rpt(adapter, psta->mac_id); + rtw_sta_mstatus_disc_rpt(adapter, psta->cmn.mac_id); else { RTW_INFO("%s "ADPT_FMT" - mac_addr: "MAC_FMT" psta == NULL\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress)); rtw_warn_on(1); @@ -2531,15 +2826,15 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) u8 *pibss = NULL; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); struct stadel_event *pstadel = (struct stadel_event *)pbuf; - struct sta_priv *pstapriv = &adapter->stapriv; struct wlan_network *tgt_network = &(pmlmepriv->cur_network); - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - RTW_INFO("%s(mac_id=%d)=" MAC_FMT "\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr)); rtw_sta_mstatus_disc_rpt(adapter, pstadel->mac_id); +#ifdef CONFIG_MCC_MODE + rtw_hal_mcc_update_macid_bitmap(adapter, pstadel->mac_id, _FALSE); +#endif /* CONFIG_MCC_MODE */ + psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr); if (psta == NULL) { @@ -2550,8 +2845,12 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) if (psta) rtw_wfd_st_switch(psta, 0); - /* if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) */ - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + if (MLME_IS_MESH(adapter)) { + rtw_free_stainfo(adapter, psta); + return; + } + + if (MLME_IS_AP(adapter)) { #ifdef CONFIG_IOCTL_CFG80211 #ifdef COMPAT_KERNEL_RELEASE @@ -2560,6 +2859,8 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) #endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */ #endif /* CONFIG_IOCTL_CFG80211 */ + rtw_free_stainfo(adapter, psta); + return; } @@ -2574,10 +2875,10 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) #ifdef CONFIG_LAYER2_ROAMING #ifdef CONFIG_RTW_80211R - if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED)) - pmlmepriv->ftpriv.ft_roam_on_expired = _TRUE; + if (rtw_ft_roam_expired(adapter, reason)) + pmlmepriv->ft_roam.ft_roam_on_expired = _TRUE; else - pmlmepriv->ftpriv.ft_roam_on_expired = _FALSE; + pmlmepriv->ft_roam.ft_roam_on_expired = _FALSE; #endif if (adapter->registrypriv.wifi_spec == 1) roam = _FALSE; @@ -2603,18 +2904,9 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) rtw_free_uc_swdec_pending_queue(adapter); - rtw_free_assoc_resources(adapter, 1); + rtw_free_assoc_resources(adapter, _TRUE); rtw_free_mlme_priv_ie_data(pmlmepriv); - _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - /* remove the network entry in scanned_queue */ - pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); - if ((pwlan) && (!check_fwstate(pmlmepriv, WIFI_UNDER_WPS))) { - pwlan->fixed = _FALSE; - rtw_free_network_nolock(adapter, pwlan); - } - _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); - rtw_indicate_disconnect(adapter, *(u16 *)pstadel->rsvd, pstadel->locally_generated); #ifdef CONFIG_INTEL_WIDI if (!rtw_to_roam(adapter)) @@ -2635,8 +2927,8 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) /* rtw_indicate_disconnect(adapter); */ /* removed@20091105 */ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); /* free old ibss network */ - /* pwlan = rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */ - pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); + /* pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */ + pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); if (pwlan) { pwlan->fixed = _FALSE; rtw_free_network_nolock(adapter, pwlan); @@ -2701,10 +2993,11 @@ void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf) /* * rtw_join_timeout_handler - Timeout/failure handler for CMD JoinBss */ -void rtw_join_timeout(struct mlme_priv *pmlmepriv) +void rtw_join_timeout_handler(void *ctx) { - _adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv); + _adapter *adapter = (_adapter *)ctx; _irqL irqL; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; #if 0 if (rtw_is_drv_stopped(adapter)) { @@ -2746,10 +3039,10 @@ void rtw_join_timeout(struct mlme_priv *pmlmepriv) #endif /* CONFIG_INTEL_WIDI */ RTW_INFO("%s We've try roaming but fail\n", __FUNCTION__); #ifdef CONFIG_RTW_80211R - rtw_clr_ft_flags(adapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); - rtw_reset_ft_status(adapter); + rtw_ft_clr_flags(adapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN); + rtw_ft_reset_status(adapter); #endif - rtw_indicate_disconnect(adapter, 0, _FALSE); + rtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE); break; } } @@ -2757,16 +3050,18 @@ void rtw_join_timeout(struct mlme_priv *pmlmepriv) } else #endif { - rtw_indicate_disconnect(adapter, 0, _FALSE); + rtw_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE); free_scanqueue(pmlmepriv);/* ??? */ #ifdef CONFIG_IOCTL_CFG80211 /* indicate disconnect for the case that join_timeout and check_fwstate != FW_LINKED */ - rtw_cfg80211_indicate_disconnect(adapter, 0, _FALSE); + rtw_cfg80211_indicate_disconnect(adapter, pmlmepriv->join_status, _FALSE); #endif /* CONFIG_IOCTL_CFG80211 */ } + pmlmepriv->join_status = 0; /* reset */ + _exit_critical_bh(&pmlmepriv->lock, &irqL); @@ -2776,22 +3071,17 @@ void rtw_join_timeout(struct mlme_priv *pmlmepriv) -} - -void rtw_join_timeout_handler(struct timer_list *t) { - struct mlme_priv *pmlmepriv = from_timer(pmlmepriv, t, assoc_timer); - rtw_join_timeout(pmlmepriv); } /* * rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey * @adapter: pointer to _adapter structure */ -void rtw_scan_timeout_handler(struct timer_list *t) +void rtw_scan_timeout_handler(void *ctx) { - struct mlme_priv *pmlmepriv = from_timer(pmlmepriv, t, scan_to_timer); - _adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv); + _adapter *adapter = (_adapter *)ctx; _irqL irqL; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; RTW_INFO(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); _enter_critical_bh(&pmlmepriv->lock, &irqL); @@ -2813,9 +3103,11 @@ void rtw_scan_timeout_handler(struct timer_list *t) void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason) { - struct mlme_priv *mlme = &adapter->mlmepriv; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); +#if defined(CONFIG_RTW_MESH) && defined(CONFIG_DFS_MASTER) +#if CONFIG_RTW_MESH_OFFCH_CAND + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); +#endif +#endif u8 u_ch; u32 interval_ms = 0xffffffff; /* 0xffffffff: special value to make min() works well, also means no auto scan */ @@ -2823,16 +3115,29 @@ void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason) rtw_mi_get_ch_setting_union(adapter, &u_ch, NULL, NULL); if (hal_chk_bw_cap(adapter, BW_CAP_40M) - && is_client_associated_to_ap(adapter) == _TRUE - && u_ch >= 1 && u_ch <= 14 - && adapter->registrypriv.wifi_spec - /* TODO: AP Connected is 40MHz capability? */ - ) { + && is_client_associated_to_ap(adapter) == _TRUE + && u_ch >= 1 && u_ch <= 14 + && adapter->registrypriv.wifi_spec + /* TODO: AP Connected is 40MHz capability? */ + ) { interval_ms = rtw_min(interval_ms, 60 * 1000); *reason |= RTW_AUTO_SCAN_REASON_2040_BSS; } -exit: +#ifdef CONFIG_RTW_MESH + #if CONFIG_RTW_MESH_OFFCH_CAND + if (adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms + && rtw_mesh_offch_candidate_accepted(adapter) + #ifdef CONFIG_DFS_MASTER + && (!rfctl->radar_detect_ch || (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl))) + #endif + ) { + interval_ms = rtw_min(interval_ms, adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms); + *reason |= RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND; + } + #endif +#endif /* CONFIG_RTW_MESH */ + if (interval_ms == 0xffffffff) interval_ms = 0; @@ -2842,26 +3147,28 @@ void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason) void rtw_drv_scan_by_self(_adapter *padapter, u8 reason) { + struct sitesurvey_parm parm; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct rtw_ieee80211_channel ch_for_2040_bss[14] = { - {1, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {2, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {3, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {4, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {5, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {6, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {7, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {8, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {9, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {10, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {11, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {12, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {13, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - {14, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, - }; - struct rtw_ieee80211_channel *ch_sel = NULL; - int ch_num = 0; + int i; +#if 1 + u8 ssc_chk; + + ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE); + if( ssc_chk == SS_DENY_BUSY_TRAFFIC) { + #ifdef CONFIG_LAYER2_ROAMING + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) + RTW_INFO(FUNC_ADPT_FMT" need to roam, don't care BusyTraffic\n", FUNC_ADPT_ARG(padapter)); + else + #endif + RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + else if (ssc_chk != SS_ALLOW) + goto exit; + if (!rtw_is_adapter_up(padapter)) + goto exit; +#else if (rtw_is_scan_deny(padapter)) goto exit; @@ -2893,17 +3200,30 @@ void rtw_drv_scan_by_self(_adapter *padapter, u8 reason) RTW_INFO(FUNC_ADPT_FMT", but buddy_intf is under scanning or linking or wps_phase\n", FUNC_ADPT_ARG(padapter)); goto exit; } +#endif #endif RTW_INFO(FUNC_ADPT_FMT" reason:0x%02x\n", FUNC_ADPT_ARG(padapter), reason); /* only for 20/40 BSS */ if (reason == RTW_AUTO_SCAN_REASON_2040_BSS) { - ch_sel = ch_for_2040_bss; - ch_num = 14; + rtw_init_sitesurvey_parm(padapter, &parm); + for (i=0;i<14;i++) { + parm.ch[i].hw_value = i + 1; + parm.ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN; + } + parm.ch_num = 14; + rtw_set_802_11_bssid_list_scan(padapter, &parm); + goto exit; } - rtw_set_802_11_bssid_list_scan(padapter, NULL, 0, ch_sel, ch_num); +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) + if ((reason == RTW_AUTO_SCAN_REASON_ROAM) + && (rtw_roam_nb_scan_list_set(padapter, &parm))) + goto exit; +#endif + + rtw_set_802_11_bssid_list_scan(padapter, NULL); exit: return; } @@ -2975,12 +3295,18 @@ void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter) /* auto site survey */ rtw_auto_scan_handler(adapter); -#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK #ifdef CONFIG_AP_MODE - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (MLME_IS_AP(adapter)|| MLME_IS_MESH(adapter)) { + #ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK expire_timeout_chk(adapter); -#endif -#endif /* !CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ + #endif /* !CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ + + #ifdef CONFIG_BMC_TX_RATE_SELECT + rtw_update_bmc_sta_tx_rate(adapter); + #endif /*CONFIG_BMC_TX_RATE_SELECT*/ + } +#endif /*CONFIG_AP_MODE*/ + #ifdef CONFIG_BR_EXT @@ -3013,6 +3339,70 @@ void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter) } +/*TP_avg(t) = (1/10) * TP_avg(t-1) + (9/10) * TP(t) MBps*/ +static void collect_sta_traffic_statistics(_adapter *adapter) +{ + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + struct sta_info *sta; + u64 curr_tx_bytes = 0, curr_rx_bytes = 0; + u32 curr_tx_mbytes = 0, curr_rx_mbytes = 0; + int i; + + for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { + sta = macid_ctl->sta[i]; + if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) { + if (sta->sta_stats.last_tx_bytes > sta->sta_stats.tx_bytes) + sta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes; + if (sta->sta_stats.last_rx_bytes > sta->sta_stats.rx_bytes) + sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes; + if (sta->sta_stats.last_rx_bc_bytes > sta->sta_stats.rx_bc_bytes) + sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes; + if (sta->sta_stats.last_rx_mc_bytes > sta->sta_stats.rx_mc_bytes) + sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes; + + curr_tx_bytes = sta->sta_stats.tx_bytes - sta->sta_stats.last_tx_bytes; + curr_rx_bytes = sta->sta_stats.rx_bytes - sta->sta_stats.last_rx_bytes; + sta->sta_stats.tx_tp_kbits = (curr_tx_bytes * 8 / 2) >> 10;/*Kbps*/ + sta->sta_stats.rx_tp_kbits = (curr_rx_bytes * 8 / 2) >> 10;/*Kbps*/ + + sta->sta_stats.smooth_tx_tp_kbits = (sta->sta_stats.smooth_tx_tp_kbits * 6 / 10) + (sta->sta_stats.tx_tp_kbits * 4 / 10);/*Kbps*/ + sta->sta_stats.smooth_rx_tp_kbits = (sta->sta_stats.smooth_rx_tp_kbits * 6 / 10) + (sta->sta_stats.rx_tp_kbits * 4 / 10);/*Kbps*/ + + curr_tx_mbytes = (curr_tx_bytes / 2) >> 20;/*MBps*/ + curr_rx_mbytes = (curr_rx_bytes / 2) >> 20;/*MBps*/ + + sta->cmn.tx_moving_average_tp = + (sta->cmn.tx_moving_average_tp / 10) + (curr_tx_mbytes * 9 / 10); /*MBps*/ + + sta->cmn.rx_moving_average_tp = + (sta->cmn.rx_moving_average_tp / 10) + (curr_rx_mbytes * 9 /10); /*MBps*/ + + rtw_collect_bcn_info(sta->padapter); + + if (adapter->bsta_tp_dump) + dump_sta_traffic(RTW_DBGDUMP, adapter, sta); + + sta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes; + sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes; + sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes; + sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes; + } + } +} + +void rtw_sta_traffic_info(void *sel, _adapter *adapter) +{ + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + struct sta_info *sta; + int i; + + for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { + sta = macid_ctl->sta[i]; + if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) + dump_sta_traffic(sel, adapter, sta); + } +} + /*#define DBG_TRAFFIC_STATISTIC*/ static void collect_traffic_statistics(_adapter *padapter) { @@ -3038,8 +3428,8 @@ static void collect_traffic_statistics(_adapter *padapter) pdvobjpriv->traffic_stat.last_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes; pdvobjpriv->traffic_stat.last_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes; - pdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes * 8 / 2 / 1024 / 1024); - pdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes * 8 / 2 / 1024 / 1024); + pdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes * 8 / 2 / 1024 / 1024);/*Mbps*/ + pdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes * 8 / 2 / 1024 / 1024);/*Mbps*/ #ifdef DBG_TRAFFIC_STATISTIC RTW_INFO("\n========================\n"); @@ -3049,14 +3439,21 @@ static void collect_traffic_statistics(_adapter *padapter) RTW_INFO("last_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_tx_bytes); RTW_INFO("last_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_rx_bytes); - RTW_INFO("cur_tx_tp:%d\n", pdvobjpriv->traffic_stat.cur_tx_tp); - RTW_INFO("cur_rx_tp:%d\n", pdvobjpriv->traffic_stat.cur_rx_tp); + RTW_INFO("cur_tx_tp:%d (Mbps)\n", pdvobjpriv->traffic_stat.cur_tx_tp); + RTW_INFO("cur_rx_tp:%d (Mbps)\n", pdvobjpriv->traffic_stat.cur_rx_tp); #endif + +#ifdef CONFIG_RTW_NAPI +#ifdef CONFIG_RTW_NAPI_DYNAMIC + dynamic_napi_th_chk (padapter); +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ +#endif + } -void rtw_dynamic_check_timer_handlder(struct timer_list *t) +void rtw_dynamic_check_timer_handlder(void *ctx) { - struct dvobj_priv *pdvobj = from_timer(pdvobj, t, dynamic_chk_timer); + struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx; _adapter *adapter = dvobj_get_primary_adapter(pdvobj); #if (MP_DRIVER == 1) @@ -3076,7 +3473,7 @@ void rtw_dynamic_check_timer_handlder(struct timer_list *t) goto exit; collect_traffic_statistics(adapter); - + collect_sta_traffic_statistics(adapter); rtw_mi_dynamic_check_timer_handlder(adapter); if (!is_drv_in_lps(adapter)) @@ -3102,10 +3499,9 @@ inline void rtw_clear_scan_deny(_adapter *adapter) RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); } -void rtw_set_scan_deny_timer_hdl(struct timer_list *t) +void rtw_set_scan_deny_timer_hdl(void *ctx) { - struct mlme_priv *pmlmepriv = from_timer(pmlmepriv, t, set_scan_deny_timer); - _adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv); + _adapter *adapter = (_adapter *)ctx; rtw_clear_scan_deny(adapter); } @@ -3130,12 +3526,22 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme { int updated = _FALSE; _adapter *adapter = container_of(mlme, _adapter, mlmepriv); -#ifdef CONFIG_RTW_80211R - ft_priv *pftpriv = &mlme->ftpriv; - u32 mdie_len = 0; - u8 *ptmp = NULL; -#endif + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + RT_CHANNEL_INFO *chset = rfctl->channel_set; + u8 ch = competitor->network.Configuration.DSConfig; + if (rtw_chset_search_ch(chset, ch) < 0) + goto exit; + if (IS_DFS_SLAVE_WITH_RD(rfctl) + && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)) + && rtw_chset_is_ch_non_ocp(chset, ch)) + goto exit; + +#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) + if (rtw_rson_isupdate_roamcan(mlme, candidate, competitor)) + goto update; + goto exit; +#endif if (is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE) goto exit; @@ -3149,23 +3555,9 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme #endif #ifdef CONFIG_RTW_80211R - if (rtw_chk_ft_flags(adapter, RTW_FT_SUPPORTED)) { - ptmp = rtw_get_ie(&competitor->network.IEs[12], _MDIE_, &mdie_len, competitor->network.IELength-12); - if (ptmp) { - if (!_rtw_memcmp(&pftpriv->mdid, ptmp+2, 2)) - goto exit; - - /*The candidate don't support over-the-DS*/ - if (rtw_chk_ft_flags(adapter, RTW_FT_STA_OVER_DS_SUPPORTED)) { - if ((rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && !(*(ptmp+4) & 0x01)) || - (!rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && (*(ptmp+4) & 0x01))) { - RTW_INFO("FT: ignore the candidate(" MAC_FMT ") for over-the-DS\n", MAC_ARG(competitor->network.MacAddress)); - rtw_clr_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED); - goto exit; - } - } - } else - goto exit; + if (rtw_ft_chk_flags(adapter, RTW_FT_PEER_EN)) { + if (rtw_ft_chk_roaming_candidate(adapter, competitor) == _FALSE) + goto exit; } #endif @@ -3186,9 +3578,16 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme goto exit; } #if 1 - if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms) + if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms) goto exit; +#if defined(CONFIG_RTW_80211R) && defined(CONFIG_RTW_WNM) + if (rtw_wnm_btm_diff_bss(adapter) && + rtw_wnm_btm_roam_candidate(adapter, competitor)) { + goto update; + } +#endif + if (competitor->network.Rssi - mlme->cur_network_scanned->network.Rssi < mlme->roam_rssi_diff_th) goto exit; @@ -3215,8 +3614,6 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme) _queue *queue = &(mlme->scanned_queue); struct wlan_network *pnetwork = NULL; struct wlan_network *candidate = NULL; - u8 bSupportAntDiv = _FALSE; - if (mlme->cur_network_scanned == NULL) { rtw_warn_on(1); @@ -3251,14 +3648,37 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme) } if (candidate == NULL) { + /* if parent note lost the path to root and there is no other cadidate, report disconnection */ +#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) + struct rtw_rson_struct rson_curr; + u8 rson_score; + + rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr); + rson_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi); + if (check_fwstate(mlme, _FW_LINKED) + && ((rson_score == RTW_RSON_SCORE_NOTCNNT) + || (rson_score == RTW_RSON_SCORE_NOTSUP))) + receive_disconnect(adapter, mlme->cur_network_scanned->network.MacAddress + , WLAN_REASON_EXPIRATION_CHK, _FALSE); +#endif RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__); ret = _FAIL; goto exit; } else { +#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) + struct rtw_rson_struct rson_curr; + u8 rson_score; + + rtw_get_rson_struct(&(candidate->network), &rson_curr); + rson_score = rtw_cal_rson_score(&rson_curr, candidate->network.Rssi); + RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u) rson_score:%d\n", __FUNCTION__, + candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress), + candidate->network.Configuration.DSConfig, rson_score); +#else RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__, candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress), candidate->network.Configuration.DSConfig); - +#endif mlme->roam_network = candidate; if (_rtw_memcmp(candidate->network.MacAddress, mlme->roam_tgt_addr, ETH_ALEN) == _TRUE) @@ -3283,7 +3703,35 @@ static int rtw_check_join_candidate(struct mlme_priv *mlme { int updated = _FALSE; _adapter *adapter = container_of(mlme, _adapter, mlmepriv); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + RT_CHANNEL_INFO *chset = rfctl->channel_set; + u8 ch = competitor->network.Configuration.DSConfig; + + if (rtw_chset_search_ch(chset, ch) < 0) + goto exit; + if (IS_DFS_SLAVE_WITH_RD(rfctl) + && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)) + && rtw_chset_is_ch_non_ocp(chset, ch)) + goto exit; +#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT)) + s16 rson_score; + struct rtw_rson_struct rson_data; + + if (rtw_rson_choose(candidate, competitor)) { + *candidate = competitor; + rtw_get_rson_struct(&((*candidate)->network), &rson_data); + rson_score = rtw_cal_rson_score(&rson_data, (*candidate)->network.Rssi); + RTW_INFO("[assoc_ssid:%s] new candidate: %s("MAC_FMT", ch%u) rson_score:%d\n", + mlme->assoc_ssid.Ssid, + (*candidate)->network.Ssid.Ssid, + MAC_ARG((*candidate)->network.MacAddress), + (*candidate)->network.Configuration.DSConfig, + rson_score); + return _TRUE; + } + return _FALSE; +#endif /* check bssid, if needed */ if (mlme->assoc_by_bssid == _TRUE) { @@ -3304,7 +3752,7 @@ static int rtw_check_join_candidate(struct mlme_priv *mlme #ifdef CONFIG_LAYER2_ROAMING if (rtw_to_roam(adapter) > 0) { - if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms + if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms || is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE ) goto exit; @@ -3353,8 +3801,9 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) _queue *queue = &(pmlmepriv->scanned_queue); struct wlan_network *pnetwork = NULL; struct wlan_network *candidate = NULL; +#ifdef CONFIG_ANTENNA_DIVERSITY u8 bSupportAntDiv = _FALSE; - +#endif adapter = (_adapter *)pmlmepriv->nic_hdl; @@ -3425,7 +3874,7 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) { rtw_disassoc_cmd(adapter, 0, 0); rtw_indicate_disconnect(adapter, 0, _FALSE); - rtw_free_assoc_resources(adapter, 0); + rtw_free_assoc_resources_cmd(adapter, _TRUE, 0); } } @@ -3500,7 +3949,6 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke struct cmd_obj *pcmd; struct setkey_parm *psetkeyparm; struct cmd_priv *pcmdpriv = &(adapter->cmdpriv); - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); sint res = _SUCCESS; @@ -3537,12 +3985,10 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke case _TKIP_: keylen = 16; _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); - psetkeyparm->grpkey = 1; break; case _AES_: keylen = 16; _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); - psetkeyparm->grpkey = 1; break; default: res = _FAIL; @@ -3579,12 +4025,111 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke } +#ifdef CONFIG_WMMPS_STA +/* + * rtw_uapsd_use_default_setting + * This function is used for setting default uapsd max sp length to uapsd_max_sp_len + * in qos_priv data structure from registry. In additional, it will also map default uapsd + * ac to each uapsd TID, delivery-enabled and trigger-enabled of corresponding TID. + * + * Arguments: + * @padapter: _adapter pointer. + * + * Auther: Arvin Liu + * Date: 2017/05/03 + */ +void rtw_uapsd_use_default_setting(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + + if (pregistrypriv->uapsd_ac_enable != 0) { + pqospriv->uapsd_max_sp_len = pregistrypriv->uapsd_max_sp_len; + + CLEAR_FLAGS(pqospriv->uapsd_tid); + CLEAR_FLAGS(pqospriv->uapsd_tid_delivery_enabled); + CLEAR_FLAGS(pqospriv->uapsd_tid_trigger_enabled); + + /* check the uapsd setting of AC_VO from registry then map these setting to each TID if necessary */ + if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VO)) { + SET_FLAG(pqospriv->uapsd_tid, WMM_TID7); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID7); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID7); + SET_FLAG(pqospriv->uapsd_tid, WMM_TID6); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID6); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID6); + } + + /* check the uapsd setting of AC_VI from registry then map these setting to each TID if necessary */ + if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VI)) { + SET_FLAG(pqospriv->uapsd_tid, WMM_TID5); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID5); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID5); + SET_FLAG(pqospriv->uapsd_tid, WMM_TID4); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID4); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID4); + } + + /* check the uapsd setting of AC_BK from registry then map these setting to each TID if necessary */ + if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BK)) { + SET_FLAG(pqospriv->uapsd_tid, WMM_TID2); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID2); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID2); + SET_FLAG(pqospriv->uapsd_tid, WMM_TID1); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID1); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID1); + } + + /* check the uapsd setting of AC_BE from registry then map these setting to each TID if necessary */ + if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BE)) { + SET_FLAG(pqospriv->uapsd_tid, WMM_TID3); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID3); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID3); + SET_FLAG(pqospriv->uapsd_tid, WMM_TID0); + SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID0); + SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID0); + } + + RTW_INFO("[WMMPS] UAPSD MAX SP Len = 0x%02x, UAPSD TID enabled = 0x%02x\n", + pqospriv->uapsd_max_sp_len, (u8)pqospriv->uapsd_tid); + } + +} + +/* + * rtw_is_wmmps_mode + * This function is used for checking whether Driver and an AP support uapsd function or not. + * If both of them support uapsd function, it will return true. Otherwise returns false. + * + * Arguments: + * @padapter: _adapter pointer. + * + * Auther: Arvin Liu + * Date: 2017/06/12 + */ +bool rtw_is_wmmps_mode(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + + if ((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT_MASK_TID_TC) != 0)) + return _TRUE; + + return _FALSE; +} +#endif /* CONFIG_WMMPS_STA */ /* adjust IEs for rtw_joinbss_cmd in WMM */ int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len) { +#ifdef CONFIG_WMMPS_STA + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; +#endif /* CONFIG_WMMPS_STA */ unsigned int ielength = 0; unsigned int i, j; + u8 qos_info = 0; i = 12; /* after the fixed IE */ while (i < in_len) { @@ -3607,7 +4152,42 @@ int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, u } out_ie[initial_out_len + 1] = 0x07; out_ie[initial_out_len + 6] = 0x00; - out_ie[initial_out_len + 8] = 0x00; + +#ifdef CONFIG_WMMPS_STA + switch(pqospriv->uapsd_max_sp_len) { + case NO_LIMIT: + /* do nothing */ + break; + case TWO_MSDU: + SET_FLAG(qos_info, BIT5); + break; + case FOUR_MSDU: + SET_FLAG(qos_info, BIT6); + break; + case SIX_MSDU: + SET_FLAG(qos_info, BIT5); + SET_FLAG(qos_info, BIT6); + break; + default: + /* do nothing */ + break; + }; + + /* check TID7 and TID6 for AC_VO to set corresponding Qos_info bit in WMM IE */ + if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID7)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID6))) + SET_FLAG(qos_info, WMM_IE_UAPSD_VO); + /* check TID5 and TID4 for AC_VI to set corresponding Qos_info bit in WMM IE */ + if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID5)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID4))) + SET_FLAG(qos_info, WMM_IE_UAPSD_VI); + /* check TID2 and TID1 for AC_BK to set corresponding Qos_info bit in WMM IE */ + if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID2)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID1))) + SET_FLAG(qos_info, WMM_IE_UAPSD_BK); + /* check TID3 and TID0 for AC_BE to set corresponding Qos_info bit in WMM IE */ + if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID3)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID0))) + SET_FLAG(qos_info, WMM_IE_UAPSD_BE); +#endif /* CONFIG_WMMPS_STA */ + + out_ie[initial_out_len + 8] = qos_info; break; } @@ -3657,108 +4237,90 @@ static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid) } -/* - * Check the RSN IE length - * If the RSN IE length <= 20, the RSN IE didn't include the PMKID information - * 0-11th element in the array are the fixed IE - * 12th element in the array is the IE - * 13th element in the array is the IE length - * */ - -static int rtw_append_pmkid(_adapter *adapter, int iEntry, u8 *ie, uint ie_len) +static int rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent) { struct security_priv *sec = &adapter->securitypriv; + struct rsne_info info; + u8 gm_cs[4]; + int i; - if (ie[13] > 20) { - int i; - u16 pmkid_cnt = RTW_GET_LE16(ie + 14 + 20); - if (pmkid_cnt == 1 && _rtw_memcmp(ie + 14 + 20 + 2, &sec->PMKIDList[iEntry].PMKID, 16)) { - RTW_INFO(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n" - , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[iEntry].PMKID)); - goto exit; - } - - RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n" - , FUNC_ADPT_ARG(adapter), pmkid_cnt); - - for (i = 0; i < pmkid_cnt; i++) - RTW_INFO(" "KEY_FMT"\n", KEY_ARG(ie + 14 + 20 + 2 + i * 16)); + rtw_rsne_info_parse(ie, ie_len, &info); - ie_len -= 2 + pmkid_cnt * 16; - ie[13] = 20; + if (info.err) { + RTW_WARN(FUNC_ADPT_FMT" rtw_rsne_info_parse error\n" + , FUNC_ADPT_ARG(adapter)); + return 0; } - if (ie[13] <= 20) { - /* The RSN IE didn't include the PMK ID, append the PMK information */ - - RTW_INFO(FUNC_ADPT_FMT" append PMKID:"KEY_FMT"\n" - , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[iEntry].PMKID)); - - RTW_PUT_LE16(&ie[ie_len], 1); - ie_len += 2; - - _rtw_memcpy(&ie[ie_len], &sec->PMKIDList[iEntry].PMKID, 16); - ie_len += 16; + if (i_ent < 0 && info.pmkid_cnt == 0) + goto exit; - ie[13] += 18;/* PMKID length = 2+16 */ + if (i_ent >= 0 && info.pmkid_cnt == 1 && _rtw_memcmp(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16)) { + RTW_INFO(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n" + , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[i_ent].PMKID)); + goto exit; } -exit: - return ie_len; -} - -static int rtw_remove_pmkid(_adapter *adapter, u8 *ie, uint ie_len) -{ - struct security_priv *sec = &adapter->securitypriv; - int i; - u16 pmkid_cnt = RTW_GET_LE16(ie + 14 + 20); - - if (ie[13] <= 20) - goto exit; + /* bakcup group mgmt cs */ + if (info.gmcs) + _rtw_memcpy(gm_cs, info.gmcs, 4); - RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n" - , FUNC_ADPT_ARG(adapter), pmkid_cnt); + if (info.pmkid_cnt) { + RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n" + , FUNC_ADPT_ARG(adapter), info.pmkid_cnt); + for (i = 0; i < info.pmkid_cnt; i++) + RTW_INFO(" "KEY_FMT"\n", KEY_ARG(info.pmkid_list + i * 16)); + } - for (i = 0; i < pmkid_cnt; i++) - RTW_INFO(" "KEY_FMT"\n", KEY_ARG(ie + 14 + 20 + 2 + i * 16)); + if (i_ent >= 0) { + RTW_INFO(FUNC_ADPT_FMT" append PMKID:"KEY_FMT"\n" + , FUNC_ADPT_ARG(adapter), KEY_ARG(sec->PMKIDList[i_ent].PMKID)); - ie_len -= 2 + pmkid_cnt * 16; - ie[13] = 20; + info.pmkid_cnt = 1; /* update new pmkid_cnt */ + _rtw_memcpy(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16); + } else + info.pmkid_cnt = 0; /* update new pmkid_cnt */ + + RTW_PUT_LE16(info.pmkid_list - 2, info.pmkid_cnt); + if (info.gmcs) + _rtw_memcpy(info.pmkid_list + 16 * info.pmkid_cnt, gm_cs, 4); + + ie_len = 1 + 1 + 2 + 4 + + 2 + 4 * info.pcs_cnt + + 2 + 4 * info.akm_cnt + + 2 + + 2 + 16 * info.pmkid_cnt + + (info.gmcs ? 4 : 0) + ; + + ie[1] = (u8)(ie_len - 2); exit: return ie_len; } -sint rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len) +sint rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie) { - u8 authmode = 0x0, securitytype, match; - u8 sec_ie[255], uncst_oui[4], bkup_ie[255]; - u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01}; - uint ielength, cnt, remove_cnt; + u8 authmode = 0x0; + uint ielength = 0; int iEntry; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; struct security_priv *psecuritypriv = &adapter->securitypriv; uint ndisauthmode = psecuritypriv->ndisauthtype; - uint ndissecuritytype = psecuritypriv->ndisencryptstatus; - - - /* copy fixed ie only */ - _rtw_memcpy(out_ie, in_ie, 12); - ielength = 12; if ((ndisauthmode == Ndis802_11AuthModeWPA) || (ndisauthmode == Ndis802_11AuthModeWPAPSK)) authmode = _WPA_IE_ID_; if ((ndisauthmode == Ndis802_11AuthModeWPA2) || (ndisauthmode == Ndis802_11AuthModeWPA2PSK)) authmode = _WPA2_IE_ID_; if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { - _rtw_memcpy(out_ie + ielength, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len); + _rtw_memcpy(out_ie, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len); + ielength = psecuritypriv->wps_ie_len; - ielength += psecuritypriv->wps_ie_len; } else if ((authmode == _WPA_IE_ID_) || (authmode == _WPA2_IE_ID_)) { /* copy RSN or SSN */ - _rtw_memcpy(&out_ie[ielength], &psecuritypriv->supplicant_ie[0], psecuritypriv->supplicant_ie[1] + 2); + _rtw_memcpy(out_ie, psecuritypriv->supplicant_ie, psecuritypriv->supplicant_ie[1] + 2); /* debug for CONFIG_IEEE80211W { int jj; @@ -3767,24 +4329,15 @@ sint rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len) printk(" %02x ", psecuritypriv->supplicant_ie[jj]); printk("\n"); }*/ - ielength += psecuritypriv->supplicant_ie[1] + 2; + ielength = psecuritypriv->supplicant_ie[1] + 2; rtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie); - -#ifdef CONFIG_DRVEXT_MODULE - drvext_report_sec_ie(&adapter->drvextpriv, authmode, sec_ie); -#endif } - iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid); - if (iEntry < 0) { - if (authmode == _WPA2_IE_ID_) - ielength = rtw_remove_pmkid(adapter, out_ie, ielength); - } else { - if (authmode == _WPA2_IE_ID_) - ielength = rtw_append_pmkid(adapter, iEntry, out_ie, ielength); + if (authmode == WLAN_EID_RSN) { + iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid); + ielength = rtw_rsn_sync_pmkid(adapter, out_ie, ielength, iEntry); } - return ielength; } @@ -3985,15 +4538,23 @@ void rtw_ht_use_default_setting(_adapter *padapter) /* Beamforming setting */ CLEAR_FLAGS(phtpriv->beamform_cap); #ifdef CONFIG_BEAMFORMING - rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer); - rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee); - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) { - SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); - RTW_INFO("[HT] HAL Support Beamformer\n"); - } - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) { - SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); - RTW_INFO("[HT] HAL Support Beamformee\n"); +#ifdef RTW_BEAMFORMING_VERSION_2 + /* only enable beamforming in STA client mode */ + if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter) + && !MLME_IS_ADHOC(padapter) + && !MLME_IS_MESH(padapter)) +#endif + { + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer); + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee); + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) { + SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + RTW_INFO("[HT] HAL Support Beamformer\n"); + } + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) { + SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + RTW_INFO("[HT] HAL Support Beamformee\n"); + } } #endif /* CONFIG_BEAMFORMING */ } @@ -4011,7 +4572,7 @@ void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len) padapter->mlmepriv.qospriv.qos_option = 1; } } - +#if defined(CONFIG_80211N_HT) /* the fucntion is >= passive_level */ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel) { @@ -4021,12 +4582,16 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui HT_CAP_AMPDU_DENSITY best_ampdu_density; unsigned char *p, *pframe; struct rtw_ieee80211_ht_cap ht_capie; - u8 cbw40_enable = 0, rf_type = 0, operation_bw = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0; + u8 cbw40_enable = 0, rf_type = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct ht_priv *phtpriv = &pmlmepriv->htpriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); +#ifdef CONFIG_80211AC_VHT + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; +#endif /* CONFIG_80211AC_VHT */ phtpriv->ht_option = _FALSE; @@ -4039,36 +4604,7 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui if (phtpriv->sgi_20m) ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_20; - /* Get HT BW */ - if (in_ie == NULL) { - /* TDLS: TODO 20/40 issue */ - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - operation_bw = padapter->mlmeextpriv.cur_bwmode; - if (operation_bw > CHANNEL_WIDTH_40) - operation_bw = CHANNEL_WIDTH_40; - } else - /* TDLS: TODO 40? */ - operation_bw = CHANNEL_WIDTH_40; - } else { - p = rtw_get_ie(in_ie, _HT_ADD_INFO_IE_, &ielen, in_len); - if (p && (ielen == sizeof(struct ieee80211_ht_addt_info))) { - struct HT_info_element *pht_info = (struct HT_info_element *)(p + 2); - if (pht_info->infos[0] & BIT(2)) { - switch (pht_info->infos[0] & 0x3) { - case 1: - case 3: - operation_bw = CHANNEL_WIDTH_40; - break; - default: - operation_bw = CHANNEL_WIDTH_20; - break; - } - } else - operation_bw = CHANNEL_WIDTH_20; - } - } - - /* to disable 40M Hz support while gd_bw_40MHz_en = 0 */ + /* check if 40MHz is allowed according to hal cap and registry */ if (hal_chk_bw_cap(padapter, BW_CAP_40M)) { if (channel > 14) { if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) @@ -4079,10 +4615,61 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui } } - if ((cbw40_enable == 1) && (operation_bw == CHANNEL_WIDTH_40)) { - ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH; - if (phtpriv->sgi_40m) - ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40; + if (cbw40_enable) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + RT_CHANNEL_INFO *chset = rfctl->channel_set; + u8 oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + if (in_ie == NULL) { + /* TDLS: TODO 20/40 issue */ + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + oper_bw = padapter->mlmeextpriv.cur_bwmode; + if (oper_bw > CHANNEL_WIDTH_40) + oper_bw = CHANNEL_WIDTH_40; + } else + /* TDLS: TODO 40? */ + oper_bw = CHANNEL_WIDTH_40; + } else { + p = rtw_get_ie(in_ie, WLAN_EID_HT_OPERATION, &ielen, in_len); + if (p && ielen == HT_OP_IE_LEN) { + if (GET_HT_OP_ELE_STA_CHL_WIDTH(p + 2)) { + switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(p + 2)) { + case SCA: + oper_bw = CHANNEL_WIDTH_40; + oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + case SCB: + oper_bw = CHANNEL_WIDTH_40; + oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + } + } + } + } + + /* adjust bw to fit in channel plan setting */ + if (oper_bw == CHANNEL_WIDTH_40 + && oper_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE /* check this because TDLS has no info to set offset */ + && (!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset) + || (IS_DFS_SLAVE_WITH_RD(rfctl) + && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)) + && rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset)) + ) + ) { + oper_bw = CHANNEL_WIDTH_20; + oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + rtw_warn_on(!rtw_chset_is_chbw_valid(chset, channel, oper_bw, oper_offset)); + if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))) + rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, channel, oper_bw, oper_offset)); + } + + if (oper_bw == CHANNEL_WIDTH_40) { + ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH; + if (phtpriv->sgi_40m) + ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40; + } + + cbw40_enable = oper_bw == CHANNEL_WIDTH_40 ? 1 : 0; } /* todo: disable SM power save mode */ @@ -4126,7 +4713,7 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui break; case 2: #ifdef CONFIG_DISABLE_MCS13TO15 - if (((cbw40_enable == 1) && (operation_bw == CHANNEL_WIDTH_40)) && (pregistrypriv->wifi_spec != 1)) + if (cbw40_enable && pregistrypriv->wifi_spec != 1) set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R_13TO15_OFF); else #endif @@ -4207,7 +4794,14 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(&ht_capie, 1); /* Explicit Compressed Beamforming Feedback Capable */ SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(&ht_capie, 2); + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); +#ifdef CONFIG_80211AC_VHT + /* IOT action suggested by Yu Chen 2017/3/3 */ + if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) && + !pvhtpriv->ap_is_mu_bfer) + rf_num = (rf_num >= 2 ? 2 : rf_num); +#endif SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, rf_num); } #endif/*CONFIG_BEAMFORMING*/ @@ -4372,47 +4966,8 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel) /* Config current HT Protection mode. */ /* */ pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; - - - -#if 0 /* move to rtw_update_sta_info_client() */ - /* for A-MPDU Rx reordering buffer control for bmc_sta & sta_info */ - /* if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */ - /* todo: check if AP can send A-MPDU packets */ - bmc_sta = rtw_get_bcmc_stainfo(padapter); - if (bmc_sta) { - for (i = 0; i < 16 ; i++) { - /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */ - preorder_ctrl = &bmc_sta->recvreorder_ctrl[i]; - preorder_ctrl->enable = _FALSE; - preorder_ctrl->indicate_seq = 0xffff; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq); -#endif - preorder_ctrl->wend_b = 0xffff; - preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */ - } - } - - psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress); - if (psta) { - for (i = 0; i < 16 ; i++) { - /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */ - preorder_ctrl = &psta->recvreorder_ctrl[i]; - preorder_ctrl->enable = _FALSE; - preorder_ctrl->indicate_seq = 0xffff; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq); -#endif - preorder_ctrl->wend_b = 0xffff; - preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */ - } - } -#endif - } +#endif #ifdef CONFIG_TDLS void rtw_issue_addbareq_cmd_tdls(_adapter *padapter, struct xmit_frame *pxmitframe) @@ -4445,6 +5000,7 @@ void rtw_issue_addbareq_cmd_tdls(_adapter *padapter, struct xmit_frame *pxmitfra } #endif /* CONFIG_TDLS */ +#ifdef CONFIG_80211N_HT void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe) { u8 issued; @@ -4495,7 +5051,7 @@ void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe) } } - +#endif /* CONFIG_80211N_HT */ void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -4514,6 +5070,9 @@ void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len) if (pvhtpriv->vht_option) SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(cap_content, 1); #endif /* CONFIG_80211AC_VHT */ +#ifdef CONFIG_RTW_WNM + rtw_wnm_set_ext_cap_btm(cap_content, 1); +#endif /* From 802.11 specification,if a STA does not support any of capabilities defined in the Extended Capabilities element, then the STA is not required to @@ -4583,8 +5142,8 @@ void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) else { RTW_INFO("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__, __LINE__); #ifdef CONFIG_RTW_80211R - rtw_clr_ft_flags(padapter, RTW_FT_SUPPORTED|RTW_FT_OVER_DS_SUPPORTED); - rtw_reset_ft_status(padapter); + rtw_ft_clr_flags(padapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN); + rtw_ft_reset_status(padapter); #endif rtw_indicate_disconnect(padapter, 0, _FALSE); break; @@ -4601,8 +5160,10 @@ bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset) struct registry_priv *regsty = adapter_to_regsty(adapter); u8 allowed_bw; - if (req_ch <= 14) + if (req_ch < 14) allowed_bw = REGSTY_BW_2G(regsty); + else if (req_ch == 14) + allowed_bw = CHANNEL_WIDTH_20; else allowed_bw = REGSTY_BW_5G(regsty); @@ -4623,8 +5184,9 @@ bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset) sint rtw_linked_check(_adapter *padapter) { - if ((check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) || - (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter) + || MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter) + ) { if (padapter->stapriv.asoc_sta_count > 2) return _TRUE; } else { @@ -4634,23 +5196,33 @@ sint rtw_linked_check(_adapter *padapter) } return _FALSE; } +/*#define DBG_ADAPTER_STATE_CHK*/ u8 rtw_is_adapter_up(_adapter *padapter) { if (padapter == NULL) return _FALSE; if (RTW_CANNOT_RUN(padapter)) { - RTW_INFO(FUNC_ADPT_FMT "-(bSurpriseRemoved == _TRUE) || ( bDriverStopped == _TRUE)\n", FUNC_ADPT_ARG(padapter)); + #ifdef DBG_ADAPTER_STATE_CHK + RTW_INFO(FUNC_ADPT_FMT " FALSE -bDriverStopped(%s) bSurpriseRemoved(%s)\n" + , FUNC_ADPT_ARG(padapter) + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False"); + #endif return _FALSE; } if (!rtw_is_hw_init_completed(padapter)) { - /*RTW_INFO(FUNC_ADPT_FMT "-(hw_init_completed == _FALSE)\n", FUNC_ADPT_ARG(padapter));*/ + #ifdef DBG_ADAPTER_STATE_CHK + RTW_INFO(FUNC_ADPT_FMT " FALSE -(hw_init_completed == _FALSE)\n", FUNC_ADPT_ARG(padapter)); + #endif return _FALSE; } if (padapter->bup == _FALSE) { - /*RTW_INFO(FUNC_ADPT_FMT "-(bup == _FALSE)\n", FUNC_ADPT_ARG(padapter));*/ + #ifdef DBG_ADAPTER_STATE_CHK + RTW_INFO(FUNC_ADPT_FMT " FALSE -(bup == _FALSE)\n", FUNC_ADPT_ARG(padapter)); + #endif return _FALSE; } @@ -4723,3 +5295,17 @@ inline void rtw_wfd_st_switch(struct sta_info *sta, bool on) rtw_st_ctl_unregister(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD); #endif } + +void dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx) +{ + RTW_PRINT_SEL(sel, "%s ARP da="MAC_FMT", sa="MAC_FMT"\n" + , tx ? "send" : "recv", MAC_ARG(da), MAC_ARG(sa)); + RTW_PRINT_SEL(sel, "htype=%u, ptype=0x%04x, hlen=%u, plen=%u, oper=%u\n" + , GET_ARP_HTYPE(arp), GET_ARP_PTYPE(arp), GET_ARP_HLEN(arp) + , GET_ARP_PLEN(arp), GET_ARP_OPER(arp)); + RTW_PRINT_SEL(sel, "sha="MAC_FMT", spa="IP_FMT"\n" + , MAC_ARG(ARP_SENDER_MAC_ADDR(arp)), IP_ARG(ARP_SENDER_IP_ADDR(arp))); + RTW_PRINT_SEL(sel, "tha="MAC_FMT", tpa="IP_FMT"\n" + , MAC_ARG(ARP_TARGET_MAC_ADDR(arp)), IP_ARG(ARP_TARGET_IP_ADDR(arp))); +} + diff --git a/core/rtw_mlme_ext.c b/core/rtw_mlme_ext.c index ea480b1..0ddb932 100755 --- a/core/rtw_mlme_ext.c +++ b/core/rtw_mlme_ext.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_MLME_EXT_C_ #include @@ -78,7 +73,7 @@ struct action_handler OnAction_tbl[] = { {RTW_WLAN_CATEGORY_DLS, "ACTION_DLS", &OnAction_dls}, {RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back}, {RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", on_action_public}, - {RTW_WLAN_CATEGORY_RADIO_MEASUREMENT, "ACTION_RADIO_MEASUREMENT", &DoReserved}, + {RTW_WLAN_CATEGORY_RADIO_MEAS, "ACTION_RADIO_MEAS", &on_action_rm}, {RTW_WLAN_CATEGORY_FT, "ACTION_FT", &OnAction_ft}, {RTW_WLAN_CATEGORY_HT, "ACTION_HT", &OnAction_ht}, #ifdef CONFIG_IEEE80211W @@ -90,7 +85,10 @@ struct action_handler OnAction_tbl[] = { {RTW_WLAN_CATEGORY_WNM, "ACTION_WNM", &on_action_wnm}, #endif {RTW_WLAN_CATEGORY_UNPROTECTED_WNM, "ACTION_UNPROTECTED_WNM", &DoReserved}, - {RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &DoReserved}, +#ifdef CONFIG_RTW_MESH + {RTW_WLAN_CATEGORY_MESH, "ACTION_MESH", &on_action_mesh}, + {RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &on_action_self_protected}, +#endif {RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm}, {RTW_WLAN_CATEGORY_VHT, "ACTION_VHT", &OnAction_vht}, {RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p}, @@ -116,298 +114,208 @@ unsigned char RSN_TKIP_CIPHER[4] = {0x00, 0x0f, 0xac, 0x02}; extern unsigned char REALTEK_96B_IE[]; -#ifdef LEGACY_CHANNEL_PLAN_REF -/******************************************************** -ChannelPlan definitions -*********************************************************/ -static RT_CHANNEL_PLAN legacy_channel_plan[] = { - /* 0x00, RTW_CHPLAN_FCC */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 32}, - /* 0x01, RTW_CHPLAN_IC */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 31}, - /* 0x02, RTW_CHPLAN_ETSI */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 32}, - /* 0x03, RTW_CHPLAN_SPAIN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, - /* 0x04, RTW_CHPLAN_FRANCE */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, - /* 0x05, RTW_CHPLAN_MKK */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, - /* 0x06, RTW_CHPLAN_MKK1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, - /* 0x07, RTW_CHPLAN_ISRAEL */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64}, 21}, - /* 0x08, RTW_CHPLAN_TELEC */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52, 56, 60, 64}, 22}, - /* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14}, - /* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, - /* 0x0B, RTW_CHPLAN_TAIWAN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 26}, - /* 0x0C, RTW_CHPLAN_CHINA */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 149, 153, 157, 161, 165}, 18}, - /* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 24}, - /* 0x0E, RTW_CHPLAN_KOREA */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 31}, - /* 0x0F, RTW_CHPLAN_TURKEY */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64}, 19}, - /* 0x10, RTW_CHPLAN_JAPAN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 32}, - /* 0x11, RTW_CHPLAN_FCC_NO_DFS */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 149, 153, 157, 161, 165}, 20}, - /* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48}, 17}, - /* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 37}, - /* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 56, 60, 64, 149, 153, 157, 161, 165}, 19}, -}; -#endif +static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set + , struct p2p_channels *channel_list) +{ + struct registry_priv *regsty = adapter_to_regsty(padapter); -static struct ch_list_t RTW_ChannelPlan2G[] = { - /* 0, RTW_RD_2G_NULL */ CH_LIST_ENT(0), - /* 1, RTW_RD_2G_WORLD */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), - /* 2, RTW_RD_2G_ETSI1 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), - /* 3, RTW_RD_2G_FCC1 */ CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11), - /* 4, RTW_RD_2G_MKK1 */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14), - /* 5, RTW_RD_2G_ETSI2 */ CH_LIST_ENT(4, 10, 11, 12, 13), - /* 6, RTW_RD_2G_GLOBAL */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14), - /* 7, RTW_RD_2G_MKK2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), - /* 8, RTW_RD_2G_FCC2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), -}; + struct p2p_oper_class_map op_class[] = { + { IEEE80211G, 81, 1, 13, 1, BW20 }, + { IEEE80211G, 82, 14, 14, 1, BW20 }, +#if 0 /* Do not enable HT40 on 2 GHz */ + { IEEE80211G, 83, 1, 9, 1, BW40PLUS }, + { IEEE80211G, 84, 5, 13, 1, BW40MINUS }, +#endif + { IEEE80211A, 115, 36, 48, 4, BW20 }, + { IEEE80211A, 116, 36, 44, 8, BW40PLUS }, + { IEEE80211A, 117, 40, 48, 8, BW40MINUS }, + { IEEE80211A, 124, 149, 161, 4, BW20 }, + { IEEE80211A, 125, 149, 169, 4, BW20 }, + { IEEE80211A, 126, 149, 157, 8, BW40PLUS }, + { IEEE80211A, 127, 153, 161, 8, BW40MINUS }, + { -1, 0, 0, 0, 0, BW20 } + }; -#ifdef CONFIG_IEEE80211_BAND_5GHZ -static struct ch_list_t RTW_ChannelPlan5G[] = { - /* 0, RTW_RD_5G_NULL */ CH_LIST_ENT(0), - /* 1, RTW_RD_5G_ETSI1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), - /* 2, RTW_RD_5G_ETSI2 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), - /* 3, RTW_RD_5G_ETSI3 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165), - /* 4, RTW_RD_5G_FCC1 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), - /* 5, RTW_RD_5G_FCC2 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), - /* 6, RTW_RD_5G_FCC3 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), - /* 7, RTW_RD_5G_FCC4 */ CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161), - /* 8, RTW_RD_5G_FCC5 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), - /* 9, RTW_RD_5G_FCC6 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), - /* 10, RTW_RD_5G_FCC7 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), - /* 11, RTW_RD_5G_KCC1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161), - /* 12, RTW_RD_5G_MKK1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), - /* 13, RTW_RD_5G_MKK2 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), - /* 14, RTW_RD_5G_MKK3 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), - /* 15, RTW_RD_5G_NCC1 */ CH_LIST_ENT(16, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), - /* 16, RTW_RD_5G_NCC2 */ CH_LIST_ENT(8, 56, 60, 64, 149, 153, 157, 161, 165), - /* 17, RTW_RD_5G_NCC3 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), - /* 18, RTW_RD_5G_ETSI4 */ CH_LIST_ENT(4, 36, 40, 44, 48), - /* 19, RTW_RD_5G_ETSI5 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), - /* 20, RTW_RD_5G_FCC8 */ CH_LIST_ENT(4, 149, 153, 157, 161), - /* 21, RTW_RD_5G_ETSI6 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), - /* 22, RTW_RD_5G_ETSI7 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), - /* 23, RTW_RD_5G_ETSI8 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), - /* 24, RTW_RD_5G_ETSI9 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), - /* 25, RTW_RD_5G_ETSI10 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), - /* 26, RTW_RD_5G_ETSI11 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165), - /* 27, RTW_RD_5G_NCC4 */ CH_LIST_ENT(17, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), - /* 28, RTW_RD_5G_ETSI12 */ CH_LIST_ENT(4, 149, 153, 157, 161), - /* 29, RTW_RD_5G_FCC9 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), - /* 30, RTW_RD_5G_ETSI13 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140), - /* 31, RTW_RD_5G_FCC10 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161), - /* 32, RTW_RD_5G_MKK4 */ CH_LIST_ENT(4, 36, 40, 44, 48), - /* 33, RTW_RD_5G_ETSI14 */ CH_LIST_ENT(11, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140), - /* 34, RTW_RD_5G_FCC11 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165), - /* 35, RTW_RD_5G_ETSI15 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165), - /* 36, RTW_RD_5G_MKK5 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), - /* 37, RTW_RD_5G_ETSI16 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), - /* 38, RTW_RD_5G_ETSI17 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), - /* 39, RTW_RD_5G_FCC12*/ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), - /* 40, RTW_RD_5G_FCC13 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), - /* 41, RTW_RD_5G_FCC14 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), - /* 42, RTW_RD_5G_FCC15 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), - /* 43, RTW_RD_5G_FCC16 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), - /* 44, RTW_RD_5G_ETSI18 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), - /* 45, RTW_RD_5G_ETSI19 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), - - /* === Below are driver defined for legacy channel plan compatible, NO static index assigned ==== */ - /* RTW_RD_5G_OLD_FCC1 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165), - /* RTW_RD_5G_OLD_NCC1 */ CH_LIST_ENT(15, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165), - /* RTW_RD_5G_OLD_KCC1 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165), -}; -#endif /* CONFIG_IEEE80211_BAND_5GHZ */ - -static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[] = { - /* ===== 0x00 ~ 0x1F, legacy channel plan ===== */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_KCC1, TXPWR_LMT_FCC), /* 0x00, RTW_CHPLAN_FCC */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_FCC1, TXPWR_LMT_FCC), /* 0x01, RTW_CHPLAN_IC */ - CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x02, RTW_CHPLAN_ETSI */ - CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x03, RTW_CHPLAN_SPAIN */ - CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x04, RTW_CHPLAN_FRANCE */ - CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x05, RTW_CHPLAN_MKK */ - CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x06, RTW_CHPLAN_MKK1 */ - CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI), /* 0x07, RTW_CHPLAN_ISRAEL */ - CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_FCC6, TXPWR_LMT_MKK), /* 0x08, RTW_CHPLAN_TELEC */ - CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_NCC1, TXPWR_LMT_FCC), /* 0x0B, RTW_CHPLAN_TAIWAN */ - CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI), /* 0x0C, RTW_CHPLAN_CHINA */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC3, TXPWR_LMT_WW), /* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ /* ETSI:Singapore, India. FCC:Mexico => WW */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_KCC1, TXPWR_LMT_ETSI), /* 0x0E, RTW_CHPLAN_KOREA */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI), /* 0x0F, RTW_CHPLAN_TURKEY */ - CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_MKK), /* 0x10, RTW_CHPLAN_JAPAN */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x11, RTW_CHPLAN_FCC_NO_DFS */ - CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK), /* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_WW), /* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC), /* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC7, TXPWR_LMT_ETSI), /* 0x15, RTW_CHPLAN_ETSI_NO_DFS */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NCC1, TXPWR_LMT_ETSI), /* 0x16, RTW_CHPLAN_KOREA_NO_DFS */ - CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK), /* 0x17, RTW_CHPLAN_JAPAN_NO_DFS */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI), /* 0x18, RTW_CHPLAN_PAKISTAN_NO_DFS */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x19, RTW_CHPLAN_TAIWAN2_NO_DFS */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1A, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1B, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1C, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1D, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1E, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_FCC1, TXPWR_LMT_WW), /* 0x1F, RTW_CHPLAN_WORLD_WIDE_ONLY_5G */ - - /* ===== 0x20 ~ 0x7F, new channel plan ===== */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x20, RTW_CHPLAN_WORLD_NULL */ - CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x21, RTW_CHPLAN_ETSI1_NULL */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NULL, TXPWR_LMT_FCC), /* 0x22, RTW_CHPLAN_FCC1_NULL */ - CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x23, RTW_CHPLAN_MKK1_NULL */ - CHPLAN_ENT(RTW_RD_2G_ETSI2, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x24, RTW_CHPLAN_ETSI2_NULL */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC1, TXPWR_LMT_FCC), /* 0x25, RTW_CHPLAN_FCC1_FCC1 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x26, RTW_CHPLAN_WORLD_ETSI1 */ - CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK1, TXPWR_LMT_MKK), /* 0x27, RTW_CHPLAN_MKK1_MKK1 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_KCC1, TXPWR_LMT_ETSI), /* 0x28, RTW_CHPLAN_WORLD_KCC1 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x29, RTW_CHPLAN_WORLD_FCC2 */ - CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_NULL, TXPWR_LMT_FCC), /* 0x2A, RTW_CHPLAN_FCC2_NULL */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2B, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2C, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2D, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2E, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2F, */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC3, TXPWR_LMT_FCC), /* 0x30, RTW_CHPLAN_WORLD_FCC3 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC4, TXPWR_LMT_FCC), /* 0x31, RTW_CHPLAN_WORLD_FCC4 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x32, RTW_CHPLAN_WORLD_FCC5 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC6, TXPWR_LMT_FCC), /* 0x33, RTW_CHPLAN_WORLD_FCC6 */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x34, RTW_CHPLAN_FCC1_FCC7 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI2, TXPWR_LMT_ETSI), /* 0x35, RTW_CHPLAN_WORLD_ETSI2 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI3, TXPWR_LMT_ETSI), /* 0x36, RTW_CHPLAN_WORLD_ETSI3 */ - CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK2, TXPWR_LMT_MKK), /* 0x37, RTW_CHPLAN_MKK1_MKK2 */ - CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK3, TXPWR_LMT_MKK), /* 0x38, RTW_CHPLAN_MKK1_MKK3 */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC1, TXPWR_LMT_FCC), /* 0x39, RTW_CHPLAN_FCC1_NCC1 */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3A, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3B, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3C, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3D, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3E, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3F, */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC), /* 0x40, RTW_CHPLAN_FCC1_NCC2 */ - CHPLAN_ENT(RTW_RD_2G_GLOBAL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x41, RTW_CHPLAN_GLOBAL_NULL */ - CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI4, TXPWR_LMT_ETSI), /* 0x42, RTW_CHPLAN_ETSI1_ETSI4 */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x43, RTW_CHPLAN_FCC1_FCC2 */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC3, TXPWR_LMT_FCC), /* 0x44, RTW_CHPLAN_FCC1_NCC3 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI5, TXPWR_LMT_ETSI), /* 0x45, RTW_CHPLAN_WORLD_ETSI5 */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC8, TXPWR_LMT_FCC), /* 0x46, RTW_CHPLAN_FCC1_FCC8 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI), /* 0x47, RTW_CHPLAN_WORLD_ETSI6 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI7, TXPWR_LMT_ETSI), /* 0x48, RTW_CHPLAN_WORLD_ETSI7 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI), /* 0x49, RTW_CHPLAN_WORLD_ETSI8 */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4A, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4B, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4C, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4D, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4E, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4F, */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI9, TXPWR_LMT_ETSI), /* 0x50, RTW_CHPLAN_WORLD_ETSI9 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI10, TXPWR_LMT_ETSI), /* 0x51, RTW_CHPLAN_WORLD_ETSI10 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI11, TXPWR_LMT_ETSI), /* 0x52, RTW_CHPLAN_WORLD_ETSI11 */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC4, TXPWR_LMT_FCC), /* 0x53, RTW_CHPLAN_FCC1_NCC4 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI12, TXPWR_LMT_ETSI), /* 0x54, RTW_CHPLAN_WORLD_ETSI12 */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC9, TXPWR_LMT_FCC), /* 0x55, RTW_CHPLAN_FCC1_FCC9 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI13, TXPWR_LMT_ETSI), /* 0x56, RTW_CHPLAN_WORLD_ETSI13 */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC10, TXPWR_LMT_FCC), /* 0x57, RTW_CHPLAN_FCC1_FCC10 */ - CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK4, TXPWR_LMT_MKK), /* 0x58, RTW_CHPLAN_MKK2_MKK4 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI14, TXPWR_LMT_ETSI), /* 0x59, RTW_CHPLAN_WORLD_ETSI14 */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5A, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5B, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5C, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5D, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5E, */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5F, */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x60, RTW_CHPLAN_FCC1_FCC5 */ - CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x61, RTW_CHPLAN_FCC2_FCC7 */ - CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC1, TXPWR_LMT_FCC), /* 0x62, RTW_CHPLAN_FCC2_FCC1 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI15, TXPWR_LMT_ETSI), /* 0x63, RTW_CHPLAN_WORLD_ETSI15 */ - CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK5, TXPWR_LMT_MKK), /* 0x64, RTW_CHPLAN_MKK2_MKK5 */ - CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI16, TXPWR_LMT_ETSI), /* 0x65, RTW_CHPLAN_ETSI1_ETSI16 */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC14, TXPWR_LMT_FCC), /* 0x66, RTW_CHPLAN_FCC1_FCC14 */ - CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x67, RTW_CHPLAN_FCC1_FCC12 */ - CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC14, TXPWR_LMT_FCC), /* 0x68, RTW_CHPLAN_FCC2_FCC14 */ - CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x69, RTW_CHPLAN_FCC2_FCC12 */ - CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI17, TXPWR_LMT_ETSI), /* 0x6A, RTW_CHPLAN_ETSI1_ETSI17 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC16, TXPWR_LMT_FCC), /* 0x6B, RTW_CHPLAN_WORLD_FCC16 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC13, TXPWR_LMT_FCC), /* 0x6C, RTW_CHPLAN_WORLD_FCC13 */ - CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC15, TXPWR_LMT_FCC), /* 0x6D, RTW_CHPLAN_FCC2_FCC15 */ - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x6E, RTW_CHPLAN_WORLD_FCC12 */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI), /* 0x6F, RTW_CHPLAN_NULL_ETSI8 */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI18, TXPWR_LMT_ETSI), /* 0x70, RTW_CHPLAN_NULL_ETSI18 */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI17, TXPWR_LMT_ETSI), /* 0x71, RTW_CHPLAN_NULL_ETSI17 */ - CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI19, TXPWR_LMT_ETSI), /* 0x72, RTW_CHPLAN_NULL_ETSI19 */ -}; + int cla, op; -static RT_CHANNEL_PLAN_MAP RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE = - CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_FCC); /* 0x7F, Realtek Define */ + cla = 0; -bool rtw_chplan_is_empty(u8 id) -{ - RT_CHANNEL_PLAN_MAP *chplan_map; + for (op = 0; op_class[op].op_class; op++) { + u8 ch; + struct p2p_oper_class_map *o = &op_class[op]; + struct p2p_reg_class *reg = NULL; - if (id == RTW_CHPLAN_REALTEK_DEFINE) - chplan_map = &RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE; - else - chplan_map = &RTW_ChannelPlanMap[id]; + for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) { + if (rtw_chset_search_ch(channel_set, ch) == -1) + continue; +#if defined(CONFIG_80211N_HT) || defined(CONFIG_80211AC_VHT) + if ((padapter->registrypriv.ht_enable == 0) && (o->inc == 8)) + continue; - if (chplan_map->Index2G == RTW_RD_2G_NULL - #ifdef CONFIG_IEEE80211_BAND_5GHZ - && chplan_map->Index5G == RTW_RD_5G_NULL - #endif - ) - return _TRUE; + if ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) && + ((o->bw == BW40MINUS) || (o->bw == BW40PLUS))) + continue; +#endif + if (reg == NULL) { + reg = &channel_list->reg_class[cla]; + cla++; + reg->reg_class = o->op_class; + reg->channels = 0; + } + reg->channel[reg->channels] = ch; + reg->channels++; + } + } + channel_list->reg_classes = cla; - return _FALSE; } -inline u8 rtw_rd_5g_band1_passive(u8 rtw_rd_5g) +#ifdef CONFIG_TXPWR_LIMIT +void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl) { - u8 passive = 0; + u8 regd; + struct regd_exc_ent *exc; + struct txpwr_lmt_ent *ent; + _irqL irqL; - switch (rtw_rd_5g) { - case RTW_RD_5G_FCC13: - case RTW_RD_5G_FCC16: - case RTW_RD_5G_ETSI18: - case RTW_RD_5G_ETSI19: - passive = 1; - }; + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - return passive; -} + rfctl->regd_name = NULL; -inline u8 rtw_rd_5g_band4_passive(u8 rtw_rd_5g) -{ - u8 passive = 0; + if (rfctl->txpwr_regd_num == 0) { + RTW_PRINT("there is no any txpwr_regd\n"); + goto release_lock; + } + + /* search from exception mapping */ + exc = _rtw_regd_exc_search(rfctl + , rfctl->country_ent ? rfctl->country_ent->alpha2 : NULL + , rfctl->ChannelPlan); + if (exc) { + u8 has_country = (exc->country[0] == '\0' && exc->country[1] == '\0') ? 0 : 1; + + if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_NONE)) == 0) + rfctl->regd_name = regd_str(TXPWR_LMT_NONE); + else if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_WW)) == 0) + rfctl->regd_name = regd_str(TXPWR_LMT_WW); + else { + ent = _rtw_txpwr_lmt_get_by_name(rfctl, exc->regd_name); + if (ent) + rfctl->regd_name = ent->regd_name; + } + + RTW_PRINT("exception mapping country:%c%c domain:0x%02x to%s regd_name:%s\n" + , has_country ? exc->country[0] : '0' + , has_country ? exc->country[1] : '0' + , exc->domain + , rfctl->regd_name ? "" : " unknown" + , exc->regd_name + ); + if (rfctl->regd_name) + goto release_lock; + } + + /* follow default channel plan mapping */ + regd = rtw_chplan_get_default_regd(rfctl->ChannelPlan); + if (regd == TXPWR_LMT_NONE) + rfctl->regd_name = regd_str(TXPWR_LMT_NONE); + else if (regd == TXPWR_LMT_WW) + rfctl->regd_name = regd_str(TXPWR_LMT_WW); + else { + ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd)); + if (ent) + rfctl->regd_name = ent->regd_name; + } - switch (rtw_rd_5g) { - case RTW_RD_5G_MKK5: - case RTW_RD_5G_ETSI16: - case RTW_RD_5G_ETSI18: - case RTW_RD_5G_ETSI19: - passive = 1; + RTW_PRINT("default mapping domain:0x%02x to%s regd_name:%s\n" + , rfctl->ChannelPlan + , rfctl->regd_name ? "" : " unknown" + , regd_str(regd) + ); + if (rfctl->regd_name) + goto release_lock; + + switch (regd) { + /* + * To support older chips without new predefined regd: + * - use FCC if IC or CHILE not found + * - use ETSI if KCC or ACMA not found + */ + case TXPWR_LMT_IC: + case TXPWR_LMT_KCC: + case TXPWR_LMT_ACMA: + case TXPWR_LMT_CHILE: + if (regd == TXPWR_LMT_IC || regd == TXPWR_LMT_CHILE) + regd = TXPWR_LMT_FCC; + else if (regd == TXPWR_LMT_KCC || regd == TXPWR_LMT_ACMA) + regd = TXPWR_LMT_ETSI; + ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd)); + if (ent) + rfctl->regd_name = ent->regd_name; + RTW_PRINT("alternate regd_name:%s %s\n" + , regd_str(regd) + , rfctl->regd_name ? "is used" : "not found" + ); + if (rfctl->regd_name) + break; + default: + rfctl->regd_name = regd_str(TXPWR_LMT_WW); + RTW_PRINT("assign %s for default case\n", regd_str(TXPWR_LMT_WW)); + break; }; - return passive; +release_lock: + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); } +#endif /* CONFIG_TXPWR_LIMIT */ void rtw_rfctl_init(_adapter *adapter) { struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - _rtw_memset(rfctl, 0, sizeof(*rfctl)); + rfctl->max_chan_nums = init_channel_set(adapter, rfctl->ChannelPlan, rfctl->channel_set); + init_channel_list(adapter, rfctl->channel_set, &rfctl->channel_list); + + _rtw_mutex_init(&rfctl->offch_mutex); + +#ifdef CONFIG_TXPWR_LIMIT + _rtw_mutex_init(&rfctl->txpwr_lmt_mutex); + _rtw_init_listhead(&rfctl->reg_exc_list); + _rtw_init_listhead(&rfctl->txpwr_lmt_list); +#endif + + rfctl->ch_sel_same_band_prefer = 1; #ifdef CONFIG_DFS_MASTER rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED; + rtw_init_timer(&(rfctl->radar_detect_timer), adapter, rtw_dfs_rd_timer_hdl, rfctl); +#endif +#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT + rfctl->dfs_slave_with_rd = 1; +#endif +} + +void rtw_rfctl_deinit(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - /* TODO: dfs_master_timer */ + _rtw_mutex_free(&rfctl->offch_mutex); + +#ifdef CONFIG_TXPWR_LIMIT + rtw_regd_exc_list_free(rfctl); + rtw_txpwr_lmt_list_free(rfctl); + _rtw_mutex_free(&rfctl->txpwr_lmt_mutex); #endif } #ifdef CONFIG_DFS_MASTER /* -* called in rtw_dfs_master_enable() +* called in rtw_dfs_rd_enable() * assume the request channel coverage is DFS range * base on the current status and the request channel coverage to check if need to reset complete CAC time */ -bool rtw_is_cac_reset_needed(_adapter *adapter, u8 ch, u8 bw, u8 offset) +bool rtw_is_cac_reset_needed(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); bool needed = _FALSE; u32 cur_hi, cur_lo, hi, lo; @@ -504,7 +412,7 @@ bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl) return rtw_rfctl_overlap_radar_detect_ch(rfctl) && IS_CH_WAITING(rfctl); } -bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) +bool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) { bool ret = _FALSE; u32 hi = 0, lo = 0; @@ -534,10 +442,15 @@ bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) return ret; } +bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch) +{ + return rtw_chset_is_chbw_non_ocp(ch_set, ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE); +} + u32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) { int ms = 0; - u32 current_time; + systime current_time; u32 hi = 0, lo = 0; int i; @@ -613,20 +526,19 @@ inline void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u _rtw_chset_update_non_ocp(ch_set, ch, bw, offset, ms); } -u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms) +u32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); u32 non_ocp_ms; u32 cac_ms; u8 in_rd_range = 0; /* if in current radar detection range*/ - if (rtw_chset_is_ch_non_ocp(mlmeext->channel_set, ch, bw, offset)) - non_ocp_ms = rtw_chset_get_ch_non_ocp_ms(mlmeext->channel_set, ch, bw, offset); + if (rtw_chset_is_chbw_non_ocp(rfctl->channel_set, ch, bw, offset)) + non_ocp_ms = rtw_chset_get_ch_non_ocp_ms(rfctl->channel_set, ch, bw, offset); else non_ocp_ms = 0; - if (rfctl->dfs_master_enabled) { + if (rfctl->radar_detect_enabled) { u32 cur_hi, cur_lo, hi, lo; if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) { @@ -650,7 +562,7 @@ u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non cac_ms = rtw_systime_to_ms(rfctl->cac_end_time - rtw_get_current_time()); else cac_ms = 0; - } else if (rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(adapter))) + } else if (rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(dvobj))) cac_ms = CAC_TIME_CE_MS; else cac_ms = CAC_TIME_MS; @@ -663,13 +575,12 @@ u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non return non_ocp_ms + cac_ms; } -void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset) +void rtw_reset_cac(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset) { - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); u32 non_ocp_ms; u32 cac_ms; - rtw_get_ch_waiting_ms(adapter + rtw_get_ch_waiting_ms(rfctl , ch , bw , offset @@ -688,18 +599,48 @@ void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset) if (rfctl->cac_end_time == RTW_CAC_STOPPED) rfctl->cac_end_time++; } + +u32 rtw_force_stop_cac(struct rf_ctl_t *rfctl, u32 timeout_ms) +{ + struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); + systime start; + u32 pass_ms; + + start = rtw_get_current_time(); + + rfctl->cac_force_stop = 1; + + while (rtw_get_passing_time_ms(start) <= timeout_ms + && IS_UNDER_CAC(rfctl) + ) { + if (dev_is_surprise_removed(dvobj) || dev_is_drv_stopped(dvobj)) + break; + rtw_msleep_os(20); + } + + if (IS_UNDER_CAC(rfctl)) { + if (!dev_is_surprise_removed(dvobj) && !dev_is_drv_stopped(dvobj)) + RTW_INFO("%s waiting for cac stop timeout!\n", __func__); + } + + rfctl->cac_force_stop = 0; + + pass_ms = rtw_get_passing_time_ms(start); + + return pass_ms; +} #endif /* CONFIG_DFS_MASTER */ /* choose channel with shortest waiting (non ocp + cac) time */ -bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags) +bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw + , u8 *dec_ch, u8 *dec_bw, u8 *dec_offset + , u8 d_flags, u8 cur_ch, u8 same_band_prefer, u8 mesh_only) { #ifndef DBG_CHOOSE_SHORTEST_WAITING_CH #define DBG_CHOOSE_SHORTEST_WAITING_CH 0 #endif - - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - struct registry_priv *regsty = adapter_to_regsty(adapter); + struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); + struct registry_priv *regsty = dvobj_to_regsty(dvobj); u8 ch, bw, offset; u8 ch_c = 0, bw_c = 0, offset_c = 0; int i; @@ -711,16 +652,18 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 } /* full search and narrow bw judegement first to avoid potetial judegement timing issue */ - for (bw = CHANNEL_WIDTH_20; bw <= req_bw; bw++) { - if (!hal_is_bw_support(adapter, bw)) + for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) { + if (!hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw)) continue; - for (i = 0; i < mlmeext->max_chan_nums; i++) { + for (i = 0; i < rfctl->max_chan_nums; i++) { u32 non_ocp_ms = 0; u32 cac_ms = 0; u32 waiting_ms = 0; - ch = mlmeext->channel_set[i].ChannelNum; + ch = rfctl->channel_set[i].ChannelNum; + if (sel_ch > 0 && ch != sel_ch) + continue; if ((d_flags & RTW_CHF_2G) && ch <= 14) continue; @@ -736,38 +679,46 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 continue; } + if (mesh_only && ch >= 5 && ch <= 9 && bw > CHANNEL_WIDTH_20) + continue; + if (!rtw_get_offset_by_chbw(ch, bw, &offset)) continue; - if (!rtw_chset_is_chbw_valid(mlmeext->channel_set, ch, bw, offset)) + if (!rtw_chset_is_chbw_valid(rfctl->channel_set, ch, bw, offset)) continue; - if ((d_flags & RTW_CHF_NON_OCP) && rtw_chset_is_ch_non_ocp(mlmeext->channel_set, ch, bw, offset)) + if ((d_flags & RTW_CHF_NON_OCP) && rtw_chset_is_chbw_non_ocp(rfctl->channel_set, ch, bw, offset)) continue; if ((d_flags & RTW_CHF_DFS) && rtw_is_dfs_chbw(ch, bw, offset)) continue; - if ((d_flags & RTW_CHF_LONG_CAC) && rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(adapter))) + if ((d_flags & RTW_CHF_LONG_CAC) && rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(dvobj))) continue; if ((d_flags & RTW_CHF_NON_DFS) && !rtw_is_dfs_chbw(ch, bw, offset)) continue; - if ((d_flags & RTW_CHF_NON_LONG_CAC) && !rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(adapter))) + if ((d_flags & RTW_CHF_NON_LONG_CAC) && !rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(dvobj))) continue; #ifdef CONFIG_DFS_MASTER - waiting_ms = rtw_get_ch_waiting_ms(adapter, ch, bw, offset, &non_ocp_ms, &cac_ms); + waiting_ms = rtw_get_ch_waiting_ms(rfctl, ch, bw, offset, &non_ocp_ms, &cac_ms); #endif if (DBG_CHOOSE_SHORTEST_WAITING_CH) - RTW_INFO(FUNC_ADPT_FMT":%u,%u,%u %u(non_ocp:%u, cac:%u)\n" - , FUNC_ADPT_ARG(adapter), ch, bw, offset, waiting_ms, non_ocp_ms, cac_ms); + RTW_INFO("%s:%u,%u,%u %u(non_ocp:%u, cac:%u)\n" + , __func__, ch, bw, offset, waiting_ms, non_ocp_ms, cac_ms); if (ch_c == 0 + /* first: smaller wating time */ || min_waiting_ms > waiting_ms - || (min_waiting_ms == waiting_ms && bw > bw_c) /* wider bw first */ + /* then: wider bw */ + || (min_waiting_ms == waiting_ms && bw > bw_c) + /* then: same band if requested */ + || (same_band_prefer && min_waiting_ms == waiting_ms && bw == bw_c + && !rtw_is_same_band(cur_ch, ch_c) && rtw_is_same_band(cur_ch, ch)) ) { ch_c = ch; bw_c = bw; @@ -778,8 +729,10 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 } if (ch_c != 0) { - RTW_INFO(FUNC_ADPT_FMT": d_flags:0x%02x %u,%u,%u waiting_ms:%u\n" - , FUNC_ADPT_ARG(adapter), d_flags, ch_c, bw_c, offset_c, min_waiting_ms); + RTW_INFO("%s: d_flags:0x%02x cur_ch:%u sb_prefer:%u%s %u,%u,%u waiting_ms:%u\n" + , __func__, d_flags, cur_ch, same_band_prefer + , mesh_only ? " mesh_only" : "" + , ch_c, bw_c, offset_c, min_waiting_ms); *dec_ch = ch_c; *dec_bw = bw_c; @@ -787,77 +740,14 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 return _TRUE; } - if (d_flags == 0) + if (d_flags == 0) { + RTW_INFO("%s: sel_ch:%u max_bw:%u d_flags:0x%02x cur_ch:%u sb_prefer:%u%s\n" + , __func__, sel_ch, max_bw, d_flags, cur_ch, same_band_prefer + , mesh_only ? " mesh_only" : ""); rtw_warn_on(1); - - return _FALSE; -} - -void dump_country_chplan(void *sel, const struct country_chplan *ent) -{ - _RTW_PRINT_SEL(sel, "\"%c%c\", 0x%02X%s\n" - , ent->alpha2[0], ent->alpha2[1], ent->chplan - , COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : "" - ); -} - -void dump_country_chplan_map(void *sel) -{ - const struct country_chplan *ent; - u8 code[2]; - -#if RTW_DEF_MODULE_REGULATORY_CERT - _RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT:0x%x\n", RTW_DEF_MODULE_REGULATORY_CERT); -#endif -#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP - _RTW_PRINT_SEL(sel, "CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\n"); -#endif - - for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) { - for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) { - ent = rtw_get_chplan_from_country(code); - if (!ent) - continue; - - dump_country_chplan(sel, ent); - } - } -} - -void dump_chplan_id_list(void *sel) -{ - int i; - - for (i = 0; i < RTW_CHPLAN_MAX; i++) { - if (!rtw_is_channel_plan_valid(i)) - continue; - - _RTW_PRINT_SEL(sel, "0x%02X ", i); - } - - RTW_PRINT_SEL(sel, "0x7F\n"); -} - -void dump_chplan_test(void *sel) -{ - int i, j; - - /* check invalid channel */ - for (i = 0; i < RTW_RD_2G_MAX; i++) { - for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan2G[i]); j++) { - if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan2G[i], j)) == 0) - RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan2G[i], j), i, j); - } } -#ifdef CONFIG_IEEE80211_BAND_5GHZ - for (i = 0; i < RTW_RD_5G_MAX; i++) { - for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan5G[i]); j++) { - if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan5G[i], j)) == 0) - RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan5G[i], j), i, j); - } - } -#endif + return _FALSE; } void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set) @@ -888,24 +778,23 @@ void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set) RTW_PRINT_SEL(sel, "total ch number:%d\n", i); } -void dump_cur_chset(void *sel, _adapter *adapter) +void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl) { - struct mlme_priv *mlme = &adapter->mlmepriv; - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; - struct registry_priv *regsty = adapter_to_regsty(adapter); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct dvobj_priv *dvobj = rfctl_to_dvobj(rfctl); + struct registry_priv *regsty = dvobj_to_regsty(dvobj); int i; - if (mlme->country_ent) - dump_country_chplan(sel, mlme->country_ent); + if (rfctl->country_ent) + dump_country_chplan(sel, rfctl->country_ent); else - RTW_PRINT_SEL(sel, "chplan:0x%02X\n", mlme->ChannelPlan); + RTW_PRINT_SEL(sel, "chplan:0x%02X\n", rfctl->ChannelPlan); - RTW_PRINT_SEL(sel, "2G_PLS:%u, 5G_PLS:%u\n" - , hal_data->Regulation2_4G, hal_data->Regulation5G); +#ifdef CONFIG_TXPWR_LIMIT + RTW_PRINT_SEL(sel, "PLS regd:%s\n", rfctl->regd_name); +#endif #ifdef CONFIG_DFS_MASTER - RTW_PRINT_SEL(sel, "dfs_domain:%u\n", rtw_odm_get_dfs_domain(adapter)); + RTW_PRINT_SEL(sel, "dfs_domain:%u\n", rtw_odm_get_dfs_domain(dvobj)); #endif for (i = 0; i < MAX_CHANNEL_NUM; i++) @@ -913,16 +802,16 @@ void dump_cur_chset(void *sel, _adapter *adapter) break; if (i < MAX_CHANNEL_NUM) { - _RTW_PRINT_SEL(sel, "excl_chs:"); + RTW_PRINT_SEL(sel, "excl_chs:"); for (i = 0; i < MAX_CHANNEL_NUM; i++) { if (regsty->excl_chs[i] == 0) break; _RTW_PRINT_SEL(sel, "%u ", regsty->excl_chs[i]); } - RTW_PRINT_SEL(sel, "\n"); + _RTW_PRINT_SEL(sel, "\n"); } - dump_chset(sel, mlmeext->channel_set); + dump_chset(sel, rfctl->channel_set); } /* @@ -983,6 +872,50 @@ u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) return valid; } +/** + * rtw_chset_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset to fit in channel plan + * @ch_set: channel plan to check + * @req_ch: pointer of the request ch, may be modified further + * @req_bw: pointer of the request bw, may be modified further + * @req_offset: pointer of the request offset, may be modified further + * @g_ch: pointer of the ongoing group ch + * @g_bw: pointer of the ongoing group bw, may be modified further + * @g_offset: pointer of the ongoing group offset, may be modified further + */ +void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset + , u8 *g_ch, u8 *g_bw, u8 *g_offset) +{ + u8 r_ch, r_bw, r_offset; + u8 u_ch, u_bw, u_offset; + u8 cur_bw = *req_bw; + + while (1) { + r_ch = *req_ch; + r_bw = cur_bw; + r_offset = *req_offset; + u_ch = *g_ch; + u_bw = *g_bw; + u_offset = *g_offset; + + rtw_sync_chbw(&r_ch, &r_bw, &r_offset, &u_ch, &u_bw, &u_offset); + + if (rtw_chset_is_chbw_valid(ch_set, r_ch, r_bw, r_offset)) + break; + if (cur_bw == CHANNEL_WIDTH_20) { + rtw_warn_on(1); + break; + } + cur_bw--; + }; + + *req_ch = r_ch; + *req_bw = r_bw; + *req_offset = r_offset; + *g_ch = u_ch; + *g_bw = u_bw; + *g_offset = u_offset; +} + /* * Check the @param ch is fit with setband setting of @param adapter * @adapter: the given adapter @@ -1041,9 +974,20 @@ Following are the initialization functions for WiFi MLME int init_hw_mlme_ext(_adapter *padapter) { struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 rx_bar_enble = _TRUE; - /* set_opmode_cmd(padapter, infra_client_with_mlme); */ /* removed */ + /* + * Sync driver status and hardware setting + */ + + /* Modify to make sure first time change channel(band) would be done properly */ + pHalData->current_channel = 0; + pHalData->current_channel_bw = CHANNEL_WIDTH_MAX; + pHalData->current_band_type = BAND_MAX; + /* set_opmode_cmd(padapter, infra_client_with_mlme); */ /* removed */ + rtw_hal_set_hwreg(padapter, HW_VAR_ENABLE_RX_BAR, &rx_bar_enble); set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); return _SUCCESS; @@ -1051,16 +995,40 @@ int init_hw_mlme_ext(_adapter *padapter) void init_mlme_default_rate_set(_adapter *padapter) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - - unsigned char mixed_datarate[NumRates] = {_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, _6M_RATE_, _9M_RATE_, _12M_RATE_, _18M_RATE_, _24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_, 0xff}; - unsigned char mixed_basicrate[NumRates] = {_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, _6M_RATE_, _12M_RATE_, _24M_RATE_, 0xff,}; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + unsigned char end_set[1] = {0xff}; + u8 offset_datarate = 0; + u8 offset_basicrate = 0; +#ifdef CONFIG_80211N_HT unsigned char supported_mcs_set[16] = {0xff, 0xff, 0xff, 0x00, 0x00, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; +#endif - _rtw_memcpy(pmlmeext->datarate, mixed_datarate, NumRates); - _rtw_memcpy(pmlmeext->basicrate, mixed_basicrate, NumRates); + if (IsSupportedTxCCK(padapter->registrypriv.wireless_mode)) { - _rtw_memcpy(pmlmeext->default_supported_mcs_set, supported_mcs_set, sizeof(pmlmeext->default_supported_mcs_set)); + unsigned char datarate_b[B_MODE_RATE_NUM] ={_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_}; + _rtw_memcpy(pmlmeext->datarate, datarate_b, B_MODE_RATE_NUM); + _rtw_memcpy(pmlmeext->basicrate, datarate_b, B_MODE_RATE_NUM); + offset_datarate += B_MODE_RATE_NUM; + offset_basicrate += B_MODE_RATE_NUM; + RTW_INFO("%s: support CCK\n", __func__); + } + if(IsSupportedTxOFDM(padapter->registrypriv.wireless_mode)) { + unsigned char datarate_g[G_MODE_RATE_NUM] ={_6M_RATE_, _9M_RATE_, _12M_RATE_, _18M_RATE_,_24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_}; + unsigned char basicrate_g[G_MODE_BASIC_RATE_NUM] = {_6M_RATE_, _12M_RATE_, _24M_RATE_}; + _rtw_memcpy(pmlmeext->datarate + offset_datarate, datarate_g, G_MODE_RATE_NUM); + _rtw_memcpy(pmlmeext->basicrate + offset_basicrate,basicrate_g, G_MODE_BASIC_RATE_NUM); + offset_datarate += G_MODE_RATE_NUM; + offset_basicrate += G_MODE_BASIC_RATE_NUM; + RTW_INFO("%s: support OFDM\n", __func__); + + } + _rtw_memcpy(pmlmeext->datarate + offset_datarate, end_set, 1); + _rtw_memcpy(pmlmeext->basicrate + offset_basicrate, end_set, 1); + +#ifdef CONFIG_80211N_HT + if( padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) + _rtw_memcpy(pmlmeext->default_supported_mcs_set, supported_mcs_set, sizeof(pmlmeext->default_supported_mcs_set)); +#endif } static void init_mlme_ext_priv_value(_adapter *padapter) @@ -1072,9 +1040,7 @@ static void init_mlme_ext_priv_value(_adapter *padapter) pmlmeext->mgnt_seq = 0;/* reset to zero when disconnect at client mode */ #ifdef CONFIG_IEEE80211W pmlmeext->sa_query_seq = 0; - pmlmeext->mgnt_80211w_IPN = 0; - pmlmeext->mgnt_80211w_IPN_rx = 0; -#endif /* CONFIG_IEEE80211W */ +#endif pmlmeext->cur_channel = padapter->registrypriv.channel; pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; @@ -1082,7 +1048,6 @@ static void init_mlme_ext_priv_value(_adapter *padapter) pmlmeext->retry = 0; pmlmeext->cur_wireless_mode = padapter->registrypriv.wireless_mode; - init_mlme_default_rate_set(padapter); if (pmlmeext->cur_channel > 14) @@ -1098,7 +1063,12 @@ static void init_mlme_ext_priv_value(_adapter *padapter) pmlmeext->sitesurvey_res.rx_ampdu_size = RX_AMPDU_SIZE_INVALID; #ifdef CONFIG_SCAN_BACKOP mlmeext_assign_scan_backop_flags_sta(pmlmeext, /*SS_BACKOP_EN|*/SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME); + #ifdef CONFIG_AP_MODE mlmeext_assign_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN | SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME); + #endif + #ifdef CONFIG_RTW_MESH + mlmeext_assign_scan_backop_flags_mesh(pmlmeext, /*SS_BACKOP_EN | */SS_BACKOP_PS_ANNC | SS_BACKOP_TX_RESUME); + #endif pmlmeext->sitesurvey_res.scan_cnt = 0; pmlmeext->sitesurvey_res.scan_cnt_max = RTW_SCAN_NUM_OF_CH; pmlmeext->sitesurvey_res.backop_ms = RTW_BACK_OP_CH_MS; @@ -1129,215 +1099,26 @@ static void init_mlme_ext_priv_value(_adapter *padapter) pmlmeext->action_public_rxseq = 0xffff; pmlmeext->action_public_dialog_token = 0xff; -} - -static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set - , struct p2p_channels *channel_list) -{ - struct registry_priv *regsty = adapter_to_regsty(padapter); - - struct p2p_oper_class_map op_class[] = { - { IEEE80211G, 81, 1, 13, 1, BW20 }, - { IEEE80211G, 82, 14, 14, 1, BW20 }, -#if 0 /* Do not enable HT40 on 2 GHz */ - { IEEE80211G, 83, 1, 9, 1, BW40PLUS }, - { IEEE80211G, 84, 5, 13, 1, BW40MINUS }, -#endif - { IEEE80211A, 115, 36, 48, 4, BW20 }, - { IEEE80211A, 116, 36, 44, 8, BW40PLUS }, - { IEEE80211A, 117, 40, 48, 8, BW40MINUS }, - { IEEE80211A, 124, 149, 161, 4, BW20 }, - { IEEE80211A, 125, 149, 169, 4, BW20 }, - { IEEE80211A, 126, 149, 157, 8, BW40PLUS }, - { IEEE80211A, 127, 153, 161, 8, BW40MINUS }, - { -1, 0, 0, 0, 0, BW20 } - }; - - int cla, op; - - cla = 0; - - for (op = 0; op_class[op].op_class; op++) { - u8 ch; - struct p2p_oper_class_map *o = &op_class[op]; - struct p2p_reg_class *reg = NULL; - - for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) { - if (rtw_chset_search_ch(channel_set, ch) == -1) - continue; - - if ((0 == padapter->registrypriv.ht_enable) && (8 == o->inc)) - continue; - - if ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) && - ((BW40MINUS == o->bw) || (BW40PLUS == o->bw))) - continue; - - if (reg == NULL) { - reg = &channel_list->reg_class[cla]; - cla++; - reg->reg_class = o->op_class; - reg->channels = 0; - } - reg->channel[reg->channels] = ch; - reg->channels++; - } - } - channel_list->reg_classes = cla; - -} - -bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch) -{ - int i; - - for (i = 0; i < MAX_CHANNEL_NUM; i++) { - if (regsty->excl_chs[i] == 0) - break; - if (regsty->excl_chs[i] == ch) - return _TRUE; - } - return _FALSE; -} - -static u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set) -{ - struct registry_priv *regsty = adapter_to_regsty(padapter); - u8 index, chanset_size = 0; - u8 b5GBand = _FALSE, b2_4GBand = _FALSE; - u8 Index2G = 0, Index5G = 0; - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); - int i; - - if (!rtw_is_channel_plan_valid(ChannelPlan)) { - RTW_ERR("ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan); - return chanset_size; - } - - _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); - - if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_2G)) - b2_4GBand = _TRUE; - - if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_5G)) - b5GBand = _TRUE; - - if (b2_4GBand == _FALSE && b5GBand == _FALSE) { - RTW_WARN("HW band_cap has no intersection with SW wireless_mode setting\n"); - return chanset_size; - } - - if (b2_4GBand) { - if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) - Index2G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index2G; - else - Index2G = RTW_ChannelPlanMap[ChannelPlan].Index2G; - - for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan2G[Index2G]); index++) { - if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan2G[Index2G], index)) == _TRUE) - continue; - - if (chanset_size >= MAX_CHANNEL_NUM) { - RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM); - break; - } - - channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan2G[Index2G], index); - - if (RTW_CHPLAN_GLOBAL_DOAMIN == ChannelPlan - || RTW_CHPLAN_GLOBAL_NULL == ChannelPlan - ) { - /* Channel 1~11 is active, and 12~14 is passive */ - if (channel_set[chanset_size].ChannelNum >= 1 && channel_set[chanset_size].ChannelNum <= 11) - channel_set[chanset_size].ScanType = SCAN_ACTIVE; - else if ((channel_set[chanset_size].ChannelNum >= 12 && channel_set[chanset_size].ChannelNum <= 14)) - channel_set[chanset_size].ScanType = SCAN_PASSIVE; - } else if (RTW_CHPLAN_WORLD_WIDE_13 == ChannelPlan - || RTW_CHPLAN_WORLD_WIDE_5G == ChannelPlan - || RTW_RD_2G_WORLD == Index2G - ) { - /* channel 12~13, passive scan */ - if (channel_set[chanset_size].ChannelNum <= 11) - channel_set[chanset_size].ScanType = SCAN_ACTIVE; - else - channel_set[chanset_size].ScanType = SCAN_PASSIVE; - } else - channel_set[chanset_size].ScanType = SCAN_ACTIVE; - - chanset_size++; - } - } - -#ifdef CONFIG_IEEE80211_BAND_5GHZ - if (b5GBand) { - if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) - Index5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index5G; - else - Index5G = RTW_ChannelPlanMap[ChannelPlan].Index5G; - - for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan5G[Index5G]); index++) { - if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index)) == _TRUE) - continue; - #ifndef CONFIG_DFS - if (rtw_is_dfs_ch(CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index))) - continue; - #endif - - if (chanset_size >= MAX_CHANNEL_NUM) { - RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM); - break; - } - - channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index); - - if ((ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G) /* all channels passive */ - || (rtw_is_5g_band1(channel_set[chanset_size].ChannelNum) - && rtw_rd_5g_band1_passive(Index5G)) /* band1 passive */ - || (rtw_is_5g_band4(channel_set[chanset_size].ChannelNum) - && rtw_rd_5g_band4_passive(Index5G)) /* band4 passive */ - || (rtw_is_dfs_ch(channel_set[chanset_size].ChannelNum)) /* DFS channel(band2, 3) passive */ - ) - channel_set[chanset_size].ScanType = SCAN_PASSIVE; - else - channel_set[chanset_size].ScanType = SCAN_ACTIVE; - - chanset_size++; - } - } - - #ifdef CONFIG_DFS_MASTER - for (i = 0; i < chanset_size; i++) - channel_set[i].non_ocp_end_time = rtw_get_current_time(); - #endif -#endif /* CONFIG_IEEE80211_BAND_5GHZ */ - - if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) { - hal_data->Regulation2_4G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd; - hal_data->Regulation5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd; - } else { - hal_data->Regulation2_4G = RTW_ChannelPlanMap[ChannelPlan].regd; - hal_data->Regulation5G = RTW_ChannelPlanMap[ChannelPlan].regd; - } - - if (chanset_size) - RTW_INFO(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n" - , FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size); - else - RTW_WARN(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, final chset has no channel\n" - , FUNC_ADPT_ARG(padapter), ChannelPlan); - - return chanset_size; +#ifdef ROKU_PRIVATE +/*infra mode, used to store AP's info*/ + _rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX); + pmlmeinfo->ht_vht_received = 0; +#endif /* ROKU_PRIVATE */ } void init_mlme_ext_timer(_adapter *padapter) { struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - rtw_init_timer(&pmlmeext->survey_timer, padapter, survey_timer_hdl); - rtw_init_timer(&pmlmeext->link_timer, padapter, link_timer_hdl); + rtw_init_timer(&pmlmeext->survey_timer, padapter, survey_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->link_timer, padapter, link_timer_hdl, padapter); #ifdef CONFIG_RTW_80211R - rtw_init_timer(&pmlmeext->ft_link_timer, padapter, ft_link_timer_hdl, padapter); - rtw_init_timer(&pmlmeext->ft_roam_timer, padapter, ft_roam_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->ft_link_timer, padapter, rtw_ft_link_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->ft_roam_timer, padapter, rtw_ft_roam_timer_hdl, padapter); +#endif + +#ifdef CONFIG_RTW_REPEATER_SON + rtw_init_timer(&pmlmeext->rson_scan_timer, padapter, rson_timer_hdl, padapter); #endif } @@ -1346,7 +1127,6 @@ int init_mlme_ext_priv(_adapter *padapter) int res = _SUCCESS; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ @@ -1365,8 +1145,6 @@ int init_mlme_ext_priv(_adapter *padapter) init_mlme_ap_info(padapter); #endif - pmlmeext->max_chan_nums = init_channel_set(padapter, pmlmepriv->ChannelPlan, pmlmeext->channel_set); - init_channel_list(padapter, pmlmeext->channel_set, &pmlmeext->channel_list); pmlmeext->last_scan_time = 0; pmlmeext->mlmeext_init = _TRUE; @@ -1381,6 +1159,9 @@ int init_mlme_ext_priv(_adapter *padapter) pmlmeext->fixed_chan = 0xFF; #endif + pmlmeext->tsf_update_pause_factor = pregistrypriv->tsf_update_pause_factor; + pmlmeext->tsf_update_restore_factor = pregistrypriv->tsf_update_restore_factor; + return res; } @@ -1398,12 +1179,14 @@ void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext) } } +#ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL static u8 cmp_pkt_chnl_diff(_adapter *padapter, u8 *pframe, uint packet_len) { /* if the channel is same, return 0. else return channel differential */ uint len; u8 channel; u8 *p; + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, _DSSET_IE_, &len, packet_len - _BEACON_IE_OFFSET_); if (p) { channel = *(p + 2); @@ -1414,6 +1197,7 @@ static u8 cmp_pkt_chnl_diff(_adapter *padapter, u8 *pframe, uint packet_len) } else return 0; } +#endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */ static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, union recv_frame *precv_frame) { @@ -1424,7 +1208,25 @@ static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, uni /* receive the frames that ra(a1) is my address or ra(a1) is bc address. */ if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) && !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + { + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + + if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE) + return; + + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE) + return; + + if ( pwdev_priv->pno_mac_addr[0] == 0xFF) + return; + + if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_pno_mac_addr(padapter), ETH_ALEN)) + return; + } +#else return; +#endif ptable->func(padapter, precv_frame); } @@ -1435,14 +1237,10 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) { int index; struct mlme_handler *ptable; -#ifdef CONFIG_AP_MODE - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; -#endif /* CONFIG_AP_MODE */ u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; u8 *pframe = precv_frame->u.hdr.rx_data; struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(pframe)); - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct recv_priv *precvpriv = &padapter->recvpriv; #if 0 @@ -1464,7 +1262,25 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) /* receive the frames that ra(a1) is my address or ra(a1) is bc address. */ if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) && !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + { + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + + if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) != _TRUE) + return; + + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE) + return; + + if ( pwdev_priv->pno_mac_addr[0] == 0xFF) + return; + + if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_pno_mac_addr(padapter), ETH_ALEN)) + return; + } +#else return; +#endif ptable = mlme_sta_tbl; @@ -1490,7 +1306,7 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) if (GetRetry(pframe)) { if (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum) { /* drop the duplicate management frame */ - pdbgpriv->dbg_rx_dup_mgt_frame_drop_count++; + precvpriv->dbg_rx_dup_mgt_frame_drop_count++; RTW_INFO("Drop duplicate management frame with seq_num = %d.\n", precv_frame->u.hdr.attrib.seq_num); return; } @@ -1507,7 +1323,7 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_AP_MODE switch (get_frame_sub_type(pframe)) { case WIFI_AUTH: - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) ptable->func = &OnAuth; else ptable->func = &OnAuthClient; @@ -1515,32 +1331,30 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) case WIFI_ASSOCREQ: case WIFI_REASSOCREQ: _mgt_dispatcher(padapter, ptable, precv_frame); -#ifdef CONFIG_HOSTAPD_MLME - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + #ifdef CONFIG_HOSTAPD_MLME + if (MLME_IS_AP(padapter)) rtw_hostapd_mlme_rx(padapter, precv_frame); -#endif + #endif break; case WIFI_PROBEREQ: - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { -#ifdef CONFIG_HOSTAPD_MLME + _mgt_dispatcher(padapter, ptable, precv_frame); + #ifdef CONFIG_HOSTAPD_MLME + if (MLME_IS_AP(padapter)) rtw_hostapd_mlme_rx(padapter, precv_frame); -#else - _mgt_dispatcher(padapter, ptable, precv_frame); -#endif - } else - _mgt_dispatcher(padapter, ptable, precv_frame); + #endif break; case WIFI_BEACON: _mgt_dispatcher(padapter, ptable, precv_frame); break; case WIFI_ACTION: - /* if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) */ _mgt_dispatcher(padapter, ptable, precv_frame); break; default: _mgt_dispatcher(padapter, ptable, precv_frame); - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + #ifdef CONFIG_HOSTAPD_MLME + if (MLME_IS_AP(padapter)) rtw_hostapd_mlme_rx(padapter, precv_frame); + #endif break; } #else @@ -1652,7 +1466,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) /* Commented by Kurt 2012/10/16 */ /* IOT issue: Google Nexus7 use 1M rate to send p2p_probe_req after GO nego completed and Nexus7 is client */ if (padapter->registrypriv.wifi_spec == 1) { - if (pattrib->data_rate <= 3) + if (pattrib->data_rate <= DESC_RATE11M) wifi_test_chk_rate = 0; } @@ -1682,7 +1496,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE && - check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE) == _FALSE) + check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE) return _SUCCESS; @@ -1756,41 +1570,37 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) /* generate pairing ID */ mac_addr = adapter_mac_addr(padapter); - peer_addr = psta->hwaddr; + peer_addr = psta->cmn.mac_addr; psta->pid = (u16)(((mac_addr[4] << 8) + mac_addr[5]) + ((peer_addr[4] << 8) + peer_addr[5])); /* update peer stainfo */ psta->isrc = _TRUE; - /* get a unique AID */ - if (psta->aid > 0) - RTW_INFO("old AID %d\n", psta->aid); + /* AID assignment */ + if (psta->cmn.aid > 0) + RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid); else { - for (psta->aid = 1; psta->aid <= NUM_STA; psta->aid++) - if (pstapriv->sta_aid[psta->aid - 1] == NULL) - break; - - if (psta->aid > pstapriv->max_num_sta) { - psta->aid = 0; - RTW_INFO("no room for more AIDs\n"); + if (!rtw_aid_alloc(padapter, psta)) { + RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter)); return _SUCCESS; - } else { - pstapriv->sta_aid[psta->aid - 1] = psta; - RTW_INFO("allocate new AID = (%d)\n", psta->aid); } + RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid); } psta->qos_option = 1; - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; psta->ieee8021x_blocked = _FALSE; #ifdef CONFIG_80211N_HT - psta->htpriv.ht_option = _TRUE; - psta->htpriv.ampdu_enable = _FALSE; - psta->htpriv.sgi_20m = _FALSE; - psta->htpriv.sgi_40m = _FALSE; - psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ - psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ + if(padapter->registrypriv.ht_enable && + is_supported_ht(padapter->registrypriv.wireless_mode)) { + psta->htpriv.ht_option = _TRUE; + psta->htpriv.ampdu_enable = _FALSE; + psta->htpriv.sgi_20m = _FALSE; + psta->htpriv.sgi_40m = _FALSE; + psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ + psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ + } #endif rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); @@ -1801,7 +1611,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) psta->state |= _FW_LINKED; _exit_critical_bh(&psta->lock, &irqL); - report_add_sta_event(padapter, psta->hwaddr); + report_add_sta_event(padapter, psta->cmn.mac_addr); } @@ -1836,9 +1646,20 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) goto _issue_probersp; if ((ielen != 0 && _FALSE == _rtw_memcmp((void *)(p + 2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength)) - || (ielen == 0 && pmlmeinfo->hidden_ssid_mode) - ) - return _SUCCESS; + || (ielen == 0 && pmlmeinfo->hidden_ssid_mode)) + goto exit; + + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, WLAN_EID_MESH_ID, (int *)&ielen, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); + + if (!p) + goto exit; + if (ielen != 0 && _rtw_memcmp((void *)(p + 2), (void *)cur->mesh_id.Ssid, cur->mesh_id.SsidLength) == _FALSE) + goto exit; + } + #endif _issue_probersp: if (((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && @@ -1849,16 +1670,14 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) } +exit: return _SUCCESS; } unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) { - struct sta_info *psta; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct sta_priv *pstapriv = &padapter->stapriv; u8 *pframe = precv_frame->u.hdr.rx_data; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &padapter->wdinfo; @@ -1905,7 +1724,12 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) #endif - if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) { + if ((mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) + || (MLME_IS_MESH(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) + #ifdef CONFIG_RTW_REPEATER_SON + || (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) + #endif + ) { rtw_mi_report_survey_event(padapter, precv_frame); return _SUCCESS; } @@ -1940,12 +1764,11 @@ static void rtw_check_legacy_ap(_adapter *padapter, u8 *pframe, u32 len) if (pmlmeext->bstart_bss == _TRUE) { int left; - u16 capability; unsigned char *pos; struct rtw_ieee802_11_elems elems; - struct HT_info_element *pht_info = NULL; +#ifdef CONFIG_80211N_HT u16 cur_op_mode; - +#endif /* checking IEs */ left = len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_; pos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_; @@ -1953,9 +1776,9 @@ static void rtw_check_legacy_ap(_adapter *padapter, u8 *pframe, u32 len) RTW_INFO("%s: parse fail for "MAC_FMT"\n", __func__, MAC_ARG(GetAddr3Ptr(pframe))); return; } - +#ifdef CONFIG_80211N_HT cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK; - +#endif /* for legacy ap */ if (elems.ht_capabilities == NULL && elems.ht_capabilities_len == 0) { @@ -1980,8 +1803,6 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) uint len = precv_frame->u.hdr.len; WLAN_BSSID_EX *pbss; int ret = _SUCCESS; - u8 *p = NULL; - u32 ielen = 0; #ifdef CONFIG_TDLS struct sta_info *ptdls_sta; struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; @@ -1990,33 +1811,27 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) #endif #endif /* CONFIG_TDLS */ - if (validate_beacon_len(pframe, len) == _FALSE) - return _SUCCESS; -#ifdef CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR - p = rtw_get_ie(pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ielen, - precv_frame->u.hdr.len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_); - if ((p != NULL) && (ielen > 0)) { - if ((*(p + 1 + ielen) == 0x2D) && (*(p + 2 + ielen) != 0x2D)) { - /* Invalid value 0x2D is detected in Extended Supported Rates (ESR) IE. Try to fix the IE length to avoid failed Beacon parsing. */ - RTW_INFO("[WIFIDBG] Error in ESR IE is detected in Beacon of BSSID:"MAC_FMT". Fix the length of ESR IE to avoid failed Beacon parsing.\n", MAC_ARG(GetAddr3Ptr(pframe))); - *(p + 1) = ielen - 1; - } - } -#endif + if (validate_beacon_len(pframe, len) == _FALSE) + return _SUCCESS; - if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) { + if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS) + || (MLME_IS_MESH(padapter) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) + ) { rtw_mi_report_survey_event(padapter, precv_frame); return _SUCCESS; } - +#ifdef CONFIG_RTW_REPEATER_SON + if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) + rtw_mi_report_survey_event(padapter, precv_frame); +#endif rtw_check_legacy_ap(padapter, pframe, len); if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) { if ((pmlmeinfo->state & WIFI_FW_AUTH_NULL) - && rtw_sta_linking_test_wait_done() + && (rtw_sta_linking_test_wait_done() || pmlmeext->join_abort) ) { - if (rtw_sta_linking_test_force_fail()) { + if (rtw_sta_linking_test_force_fail() || pmlmeext->join_abort) { set_link_timer(pmlmeext, 1); return _SUCCESS; } @@ -2035,12 +1850,13 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) RTW_INFO("%s: beacon keys ready\n", __func__); _rtw_memcpy(&pmlmepriv->cur_beacon_keys, &recv_beacon, sizeof(recv_beacon)); - pmlmepriv->new_beacon_cnts = 0; } else { RTW_ERR("%s: get beacon keys failed\n", __func__); _rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon)); - pmlmepriv->new_beacon_cnts = 0; } + #ifdef CONFIG_BCN_CNT_CONFIRM_HDL + pmlmepriv->new_beacon_cnts = 0; + #endif } rtw_mfree((u8 *)pbss, sizeof(WLAN_BSSID_EX)); } @@ -2050,14 +1866,8 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) /* update TSF Value */ update_TSF(pmlmeext, pframe, len); - - /* reset for adaptive_early_32k */ - pmlmeext->adaptive_tsf_done = _FALSE; - pmlmeext->DrvBcnEarly = 0xff; - pmlmeext->DrvBcnTimeOut = 0xff; pmlmeext->bcn_cnt = 0; - _rtw_memset(pmlmeext->bcn_delay_cnt, 0, sizeof(pmlmeext->bcn_delay_cnt)); - _rtw_memset(pmlmeext->bcn_delay_ratio, 0, sizeof(pmlmeext->bcn_delay_ratio)); + pmlmeext->last_bcn_cnt = 0; #ifdef CONFIG_P2P_PS /* Comment by YiWei , in wifi p2p spec the "3.3 P2P Power Management" , "These mechanisms are available in a P2P Group in which only P2P Devices are associated." */ @@ -2095,7 +1905,9 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } #endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */ - +#ifdef CONFIG_RTW_80211R + rtw_ft_update_bcn(padapter, precv_frame); +#endif ret = rtw_check_bcn_info(padapter, pframe, len); if (!ret) { RTW_PRINT("ap has changed, disconnect now\n "); @@ -2109,10 +1921,11 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) update_beacon_info(padapter, pframe, len, psta); } - pmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.RecvSignalPower; - - adaptive_early_32k(pmlmeext, pframe, len); - + pmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; + pmlmeext->bcn_cnt++; +#ifdef CONFIG_BCN_RECV_TIME + rtw_rx_bcn_time_update(padapter, len, precv_frame->u.hdr.attrib.data_rate); +#endif #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW if (rtw_tdls_is_chsw_allowed(padapter) == _TRUE) { @@ -2129,15 +1942,17 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) #endif #endif /* CONFIG_TDLS */ -#ifdef CONFIG_DFS - process_csa_ie(padapter, pframe, len); /* channel switch announcement */ -#endif /* CONFIG_DFS */ + #ifdef CONFIG_DFS + process_csa_ie(padapter + , pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_ + , len - (WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_)); + #endif #ifdef CONFIG_P2P_PS process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); #endif /* CONFIG_P2P_PS */ - if (pmlmeext->en_hw_update_tsf) + if (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf) rtw_enable_hw_update_tsf_cmd(padapter); #if 0 /* move to validate_recv_mgnt_frame */ @@ -2146,7 +1961,6 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) } } else if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { - _irqL irqL; u8 rate_set[16]; u8 rate_num = 0; @@ -2159,7 +1973,7 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) if ((sta_rx_pkts(psta) & 0xf) == 0) update_beacon_info(padapter, pframe, len, psta); - if (pmlmeext->en_hw_update_tsf) + if (pmlmeext->tsf_update_required && pmlmeext->en_hw_update_tsf) rtw_enable_hw_update_tsf_cmd(padapter); } else { rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, len - WLAN_HDR_A3_LEN - _BEACON_IE_OFFSET_, rate_set, &rate_num); @@ -2224,6 +2038,14 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) return _FAIL; + if (!MLME_IS_ASOC(padapter)) + return _SUCCESS; + +#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_RTW_MESH) + if (MLME_IS_MESH(padapter)) + return rtw_mesh_on_auth(padapter, precv_frame); +#endif + RTW_INFO("+OnAuth\n"); sa = get_addr2_ptr(pframe); @@ -2253,6 +2075,13 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) RTW_INFO("auth alg=%x, seq=%X\n", algorithm, seq); + if (rtw_ap_linking_test_force_auth_fail()) { + status = rtw_ap_linking_test_force_auth_fail(); + RTW_INFO(FUNC_ADPT_FMT" force auth fail with status:%u\n" + , FUNC_ADPT_ARG(padapter), status); + goto auth_fail; + } + if (auth_mode == 2 && psecuritypriv->dot11PrivacyAlgrthm != _WEP40_ && psecuritypriv->dot11PrivacyAlgrthm != _WEP104_) @@ -2427,7 +2256,7 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) pstat = &stat; _rtw_memset((char *)pstat, '\0', sizeof(stat)); pstat->auth_seq = 2; - _rtw_memcpy(pstat->hwaddr, sa, 6); + _rtw_memcpy(pstat->cmn.mac_addr, sa, ETH_ALEN); #ifdef CONFIG_NATIVEAP_MLME issue_auth(padapter, pstat, (unsigned short)status); @@ -2445,12 +2274,6 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) unsigned int go2asoc = 0; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); -#ifdef CONFIG_RTW_80211R - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - ft_priv *pftpriv = &pmlmepriv->ftpriv; - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta = NULL; -#endif u8 *pframe = precv_frame->u.hdr.rx_data; uint pkt_len = precv_frame->u.hdr.len; @@ -2460,7 +2283,7 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN)) return _SUCCESS; - if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE)) + if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE) || pmlmeext->join_abort) return _SUCCESS; offset = (GetPrivacy(pframe)) ? 4 : 0; @@ -2479,6 +2302,7 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) /* pmlmeinfo->reauth_count = 0; */ } + pmlmeinfo->auth_status = status; set_link_timer(pmlmeext, 1); goto authclnt_fail; } @@ -2517,29 +2341,9 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) if (go2asoc) { #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - u8 target_ap_addr[ETH_ALEN] = {0}; - - if ((rtw_chk_ft_status(padapter, RTW_FT_AUTHENTICATED_STA)) || - (rtw_chk_ft_status(padapter, RTW_FT_ASSOCIATING_STA)) || - (rtw_chk_ft_status(padapter, RTW_FT_ASSOCIATED_STA))) { - /*report_ft_reassoc_event already, and waiting for cfg80211_rtw_update_ft_ies*/ - return _SUCCESS; - } - - rtw_buf_update(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len, pframe, pkt_len); - pftpriv->ft_event.ies = pmlmepriv->auth_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6; - pftpriv->ft_event.ies_len = pmlmepriv->auth_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6; - - /*Not support RIC*/ - pftpriv->ft_event.ric_ies = NULL; - pftpriv->ft_event.ric_ies_len = 0; - _rtw_memcpy(target_ap_addr, pmlmepriv->assoc_bssid, ETH_ALEN); - report_ft_reassoc_event(padapter, target_ap_addr); + if (rtw_ft_update_auth_rsp_ies(padapter, pframe, pkt_len)) return _SUCCESS; - } #endif - RTW_PRINT("auth success, start assoc\n"); start_clnt_assoc(padapter); return _SUCCESS; @@ -2557,18 +2361,13 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) { #ifdef CONFIG_AP_MODE _irqL irqL; - u16 capab_info, listen_interval; + u16 listen_interval; struct rtw_ieee802_11_elems elems; struct sta_info *pstat; - unsigned char reassoc, *p, *pos, *wpa_ie; - unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; - int i, ie_len, wpa_ie_len, left; - u8 rate_set[16]; - u8 rate_num; + unsigned char reassoc, *pos; + int left; unsigned short status = _STATS_SUCCESSFUL_; unsigned short frame_type, ie_offset = 0; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *cur = &(pmlmeinfo->network); @@ -2615,15 +2414,6 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) goto asoc_class2_error; } - capab_info = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN); - /* capab_info = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); */ - /* listen_interval = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN+2)); */ - listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN + 2); - - left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset); - pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset); - - RTW_INFO("%s\n", __FUNCTION__); /* check if this stat has been successfully authenticated/assocated */ @@ -2640,7 +2430,6 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) pstat->state |= WIFI_FW_ASSOC_STATE; } - #if 0/* todo:tkip_countermeasures */ if (hapd->tkip_countermeasures) { resp = WLAN_REASON_MICHAEL_MIC_FAILURE; @@ -2648,8 +2437,26 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) } #endif - pstat->capability = capab_info; + if (rtw_ap_linking_test_force_asoc_fail()) { + status = rtw_ap_linking_test_force_asoc_fail(); + RTW_INFO(FUNC_ADPT_FMT" force asoc fail with status:%u\n" + , FUNC_ADPT_ARG(padapter), status); + goto OnAssocReqFail; + } + + /* now parse all ieee802_11 ie to point to elems */ + left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset); + pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset); + if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) { + RTW_INFO("STA " MAC_FMT " sent invalid association request\n", + MAC_ARG(pstat->cmn.mac_addr)); + status = _STATS_FAILURE_; + goto OnAssocReqFail; + } + + rtw_ap_parse_sta_capability(padapter, pstat, pframe + WLAN_HDR_A3_LEN); + listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN + 2); #if 0/* todo: */ /* check listen_interval */ if (listen_interval > hapd->conf->max_listen_interval) { @@ -2664,290 +2471,40 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) pstat->listen_interval = listen_interval; #endif - /* now parse all ieee802_11 ie to point to elems */ - if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed || - !elems.ssid) { - RTW_INFO("STA " MAC_FMT " sent invalid association request\n", - MAC_ARG(pstat->hwaddr)); - status = _STATS_FAILURE_; - goto OnAssocReqFail; - } - - /* now we should check all the fields... */ /* checking SSID */ - p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _SSID_IE_, &ie_len, - pkt_len - WLAN_HDR_A3_LEN - ie_offset); - if (p == NULL) - status = _STATS_FAILURE_; - - if (ie_len == 0) /* broadcast ssid, however it is not allowed in assocreq */ + if (elems.ssid == NULL + || elems.ssid_len == 0 + || elems.ssid_len != cur->Ssid.SsidLength + || _rtw_memcmp(elems.ssid, cur->Ssid.Ssid, cur->Ssid.SsidLength) == _FALSE + ) { status = _STATS_FAILURE_; - else { - /* check if ssid match */ - if (!_rtw_memcmp((void *)(p + 2), cur->Ssid.Ssid, cur->Ssid.SsidLength)) - status = _STATS_FAILURE_; - - if (ie_len != cur->Ssid.SsidLength) - status = _STATS_FAILURE_; - } - - if (_STATS_SUCCESSFUL_ != status) goto OnAssocReqFail; + } - rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset, rate_set, &rate_num); - if (rate_num == 0) { - RTW_INFO(FUNC_ADPT_FMT" RX assoc-req with no supported rate\n", FUNC_ADPT_ARG(padapter)); - status = _STATS_FAILURE_; + /* (Extended) Supported rates */ + status = rtw_ap_parse_sta_supported_rates(padapter, pstat + , pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset); + if (status != _STATS_SUCCESSFUL_) goto OnAssocReqFail; - } - _rtw_memcpy(pstat->bssrateset, rate_set, rate_num); - pstat->bssratelen = rate_num; - UpdateBrateTblForSoftAP(pstat->bssrateset, pstat->bssratelen); /* check RSN/WPA/WPS */ - pstat->dot8021xalg = 0; - pstat->wpa_psk = 0; - pstat->wpa_group_cipher = 0; - pstat->wpa2_group_cipher = 0; - pstat->wpa_pairwise_cipher = 0; - pstat->wpa2_pairwise_cipher = 0; - _rtw_memset(pstat->wpa_ie, 0, sizeof(pstat->wpa_ie)); - if ((psecuritypriv->wpa_psk & BIT(1)) && elems.rsn_ie) { - - int group_cipher = 0, pairwise_cipher = 0; - - wpa_ie = elems.rsn_ie; - wpa_ie_len = elems.rsn_ie_len; - - if (rtw_parse_wpa2_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { - pstat->dot8021xalg = 1;/* psk, todo:802.1x */ - pstat->wpa_psk |= BIT(1); - - pstat->wpa2_group_cipher = group_cipher & psecuritypriv->wpa2_group_cipher; - pstat->wpa2_pairwise_cipher = pairwise_cipher & psecuritypriv->wpa2_pairwise_cipher; - - if (!pstat->wpa2_group_cipher) - status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; - - if (!pstat->wpa2_pairwise_cipher) - status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; - } else - status = WLAN_STATUS_INVALID_IE; - - } else if ((psecuritypriv->wpa_psk & BIT(0)) && elems.wpa_ie) { - - int group_cipher = 0, pairwise_cipher = 0; - - wpa_ie = elems.wpa_ie; - wpa_ie_len = elems.wpa_ie_len; - - if (rtw_parse_wpa_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { - pstat->dot8021xalg = 1;/* psk, todo:802.1x */ - pstat->wpa_psk |= BIT(0); - - pstat->wpa_group_cipher = group_cipher & psecuritypriv->wpa_group_cipher; - pstat->wpa_pairwise_cipher = pairwise_cipher & psecuritypriv->wpa_pairwise_cipher; - - if (!pstat->wpa_group_cipher) - status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; - - if (!pstat->wpa_pairwise_cipher) - status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; - - } else - status = WLAN_STATUS_INVALID_IE; - - } else { - wpa_ie = NULL; - wpa_ie_len = 0; - } - - if (_STATS_SUCCESSFUL_ != status) + status = rtw_ap_parse_sta_security_ie(padapter, pstat, &elems); + if (status != _STATS_SUCCESSFUL_) goto OnAssocReqFail; - pstat->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS); - /* if (hapd->conf->wps_state && wpa_ie == NULL) { */ /* todo: to check ap if supporting WPS */ - if (wpa_ie == NULL) { - if (elems.wps_ie) { - RTW_INFO("STA included WPS IE in " - "(Re)Association Request - assume WPS is " - "used\n"); - pstat->flags |= WLAN_STA_WPS; - /* wpabuf_free(sta->wps_ie); */ - /* sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, */ - /* elems.wps_ie_len - 4); */ - } else { - RTW_INFO("STA did not include WPA/RSN IE " - "in (Re)Association Request - possible WPS " - "use\n"); - pstat->flags |= WLAN_STA_MAYBE_WPS; - } - - - /* AP support WPA/RSN, and sta is going to do WPS, but AP is not ready */ - /* that the selected registrar of AP is _FLASE */ - if ((psecuritypriv->wpa_psk > 0) - && (pstat->flags & (WLAN_STA_WPS | WLAN_STA_MAYBE_WPS))) { - if (pmlmepriv->wps_beacon_ie) { - u8 selected_registrar = 0; - - rtw_get_wps_attr_content(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR , &selected_registrar, NULL); - - if (!selected_registrar) { - RTW_INFO("selected_registrar is _FALSE , or AP is not ready to do WPS\n"); - - status = _STATS_UNABLE_HANDLE_STA_; - - goto OnAssocReqFail; - } - } - } - - } else { - int copy_len; - - if (psecuritypriv->wpa_psk == 0) { - RTW_INFO("STA " MAC_FMT ": WPA/RSN IE in association " - "request, but AP don't support WPA/RSN\n", MAC_ARG(pstat->hwaddr)); - - status = WLAN_STATUS_INVALID_IE; - - goto OnAssocReqFail; - - } - - if (elems.wps_ie) { - RTW_INFO("STA included WPS IE in " - "(Re)Association Request - WPS is " - "used\n"); - pstat->flags |= WLAN_STA_WPS; - copy_len = 0; - } else - copy_len = ((wpa_ie_len + 2) > sizeof(pstat->wpa_ie)) ? (sizeof(pstat->wpa_ie)) : (wpa_ie_len + 2); - - - if (copy_len > 0) - _rtw_memcpy(pstat->wpa_ie, wpa_ie - 2, copy_len); - - } - - /* check if there is WMM IE & support WWM-PS */ - pstat->flags &= ~WLAN_STA_WME; - pstat->qos_option = 0; - pstat->qos_info = 0; - pstat->has_legacy_ac = _TRUE; - pstat->uapsd_vo = 0; - pstat->uapsd_vi = 0; - pstat->uapsd_be = 0; - pstat->uapsd_bk = 0; - if (pmlmepriv->qospriv.qos_option) { - p = pframe + WLAN_HDR_A3_LEN + ie_offset; - ie_len = 0; - for (;;) { - p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, pkt_len - WLAN_HDR_A3_LEN - ie_offset); - if (p != NULL) { - if (_rtw_memcmp(p + 2, WMM_IE, 6)) { - - pstat->flags |= WLAN_STA_WME; - - pstat->qos_option = 1; - pstat->qos_info = *(p + 8); - - pstat->max_sp_len = (pstat->qos_info >> 5) & 0x3; - - if ((pstat->qos_info & 0xf) != 0xf) - pstat->has_legacy_ac = _TRUE; - else - pstat->has_legacy_ac = _FALSE; - - if (pstat->qos_info & 0xf) { - if (pstat->qos_info & BIT(0)) - pstat->uapsd_vo = BIT(0) | BIT(1); - else - pstat->uapsd_vo = 0; - - if (pstat->qos_info & BIT(1)) - pstat->uapsd_vi = BIT(0) | BIT(1); - else - pstat->uapsd_vi = 0; + rtw_ap_parse_sta_wmm_ie(padapter, pstat + , pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset); - if (pstat->qos_info & BIT(2)) - pstat->uapsd_bk = BIT(0) | BIT(1); - else - pstat->uapsd_bk = 0; - - if (pstat->qos_info & BIT(3)) - pstat->uapsd_be = BIT(0) | BIT(1); - else - pstat->uapsd_be = 0; - - } - - break; - } - } else - break; - p = p + ie_len + 2; - } - } - - -#ifdef CONFIG_80211N_HT - if (pmlmepriv->htpriv.ht_option == _FALSE) - goto bypass_ht_chk; - - /* save HT capabilities in the sta object */ - _rtw_memset(&pstat->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap)); - if (elems.ht_capabilities && elems.ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) { - pstat->flags |= WLAN_STA_HT; - - pstat->flags |= WLAN_STA_WME; - - _rtw_memcpy(&pstat->htpriv.ht_cap, elems.ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap)); - - } else - pstat->flags &= ~WLAN_STA_HT; -bypass_ht_chk: - - if ((pmlmepriv->htpriv.ht_option == _FALSE) && (pstat->flags & WLAN_STA_HT)) { - rtw_warn_on(1); - status = _STATS_FAILURE_; - goto OnAssocReqFail; - } -#endif /* CONFIG_80211N_HT */ - -#ifdef CONFIG_80211AC_VHT - if (pmlmepriv->vhtpriv.vht_option == _FALSE) - goto bypass_vht_chk; - - _rtw_memset(&pstat->vhtpriv, 0, sizeof(struct vht_priv)); - if (elems.vht_capabilities && elems.vht_capabilities_len == 12) { - pstat->flags |= WLAN_STA_VHT; - - _rtw_memcpy(pstat->vhtpriv.vht_cap, elems.vht_capabilities, 12); - - if (elems.vht_op_mode_notify && elems.vht_op_mode_notify_len == 1) - _rtw_memcpy(&pstat->vhtpriv.vht_op_mode_notify, elems.vht_op_mode_notify, 1); - else /* for Frame without Operating Mode notify ie; default: 80M */ - pstat->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80; - } else - pstat->flags &= ~WLAN_STA_VHT; -bypass_vht_chk: - - if ((pmlmepriv->vhtpriv.vht_option == _FALSE) && (pstat->flags & WLAN_STA_VHT)) { - rtw_warn_on(1); - status = _STATS_FAILURE_; - goto OnAssocReqFail; - } -#endif /* CONFIG_80211AC_VHT */ + rtw_ap_parse_sta_ht_ie(padapter, pstat, &elems); + rtw_ap_parse_sta_vht_ie(padapter, pstat, &elems); if (((pstat->flags & WLAN_STA_HT) || (pstat->flags & WLAN_STA_VHT)) && ((pstat->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) || (pstat->wpa_pairwise_cipher & WPA_CIPHER_TKIP))) { - RTW_INFO("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->hwaddr)); + RTW_INFO("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->cmn.mac_addr)); pstat->flags &= ~WLAN_STA_HT; pstat->flags &= ~WLAN_STA_VHT; @@ -2956,24 +2513,6 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) */ } - - /* - * if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G) */ /* ? */ - pstat->flags |= WLAN_STA_NONERP; - for (i = 0; i < pstat->bssratelen; i++) { - if ((pstat->bssrateset[i] & 0x7f) > 22) { - pstat->flags &= ~WLAN_STA_NONERP; - break; - } - } - - if (pstat->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) - pstat->flags |= WLAN_STA_SHORT_PREAMBLE; - else - pstat->flags &= ~WLAN_STA_SHORT_PREAMBLE; - - - if (status != _STATS_SUCCESSFUL_) goto OnAssocReqFail; @@ -2997,44 +2536,37 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) pstat->p2p_status_code = p2p_status_code; #endif /* CONFIG_P2P */ +#ifdef CONFIG_RTW_REPEATER_SON + if (rtw_rson_ap_check_sta(padapter, pframe, pkt_len, ie_offset)) + goto OnAssocReqFail; +#endif + /* TODO: identify_proprietary_vendor_ie(); */ /* Realtek proprietary IE */ /* identify if this is Broadcom sta */ /* identify if this is ralink sta */ /* Customer proprietary IE */ +#ifdef CONFIG_RTW_80211K + rtw_ap_parse_sta_rm_en_cap(padapter, pstat, &elems); +#endif - - /* get a unique AID */ - if (pstat->aid > 0) - RTW_INFO(" old AID %d\n", pstat->aid); + /* AID assignment */ + if (pstat->cmn.aid > 0) + RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid); else { - for (pstat->aid = 1; pstat->aid <= NUM_STA; pstat->aid++) { - if (pstapriv->sta_aid[pstat->aid - 1] == NULL) { - if (pstat->aid > pstapriv->max_num_sta) { - pstat->aid = 0; - - RTW_INFO(" no room for more AIDs\n"); - - status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA; - - goto OnAssocReqFail; - - - } else { - pstapriv->sta_aid[pstat->aid - 1] = pstat; - RTW_INFO("allocate new AID = (%d)\n", pstat->aid); - break; - } - } + if (!rtw_aid_alloc(padapter, pstat)) { + RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter)); + status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA; + goto OnAssocReqFail; } + RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid); } - pstat->state &= (~WIFI_FW_ASSOC_STATE); pstat->state |= WIFI_FW_ASSOC_SUCCESS; /* RTW_INFO("==================%s, %d, (%x), bpairwise_key_installed=%d, MAC:"MAC_FMT"\n" - , __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->hwaddr)); */ + , __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->cmn.mac_addr)); */ #ifdef CONFIG_IEEE80211W if (pstat->bpairwise_key_installed != _TRUE) #endif /* CONFIG_IEEE80211W */ @@ -3096,12 +2628,12 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) #endif /* CONFIG_IEEE80211W */ { /* .3-(1) report sta add event */ - report_add_sta_event(padapter, pstat->hwaddr); + report_add_sta_event(padapter, pstat->cmn.mac_addr); } #ifdef CONFIG_IEEE80211W - if (pstat->bpairwise_key_installed == _TRUE && padapter->securitypriv.binstallBIPkey == _TRUE) { - RTW_INFO(MAC_FMT"\n", MAC_ARG(pstat->hwaddr)); - issue_action_SA_Query(padapter, pstat->hwaddr, 0, 0, IEEE80211W_RIGHT_KEY); + if (pstat->bpairwise_key_installed == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) { + RTW_INFO(MAC_FMT"\n", MAC_ARG(pstat->cmn.mac_addr)); + issue_action_SA_Query(padapter, pstat->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY); } #endif /* CONFIG_IEEE80211W */ #endif /* CONFIG_NATIVEAP_MLME */ @@ -3121,7 +2653,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_NATIVEAP_MLME - pstat->aid = 0; + pstat->cmn.aid = 0; if (frame_type == WIFI_ASSOCREQ) issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); else @@ -3135,6 +2667,34 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) } +#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K) +void rtw_roam_nb_discover(_adapter *padapter, u8 bfroce) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + u8 nb_req_issue = _FALSE; + + if (!check_fwstate(pmlmepriv, _FW_LINKED)) + return; + + if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) + return; + + psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); + if (!psta) + return; + + if (bfroce || (!pmlmepriv->nb_info.nb_rpt_is_same)) + nb_req_issue = _TRUE; + + if (nb_req_issue && (psta->rm_en_cap[0] & RTW_RRM_NB_RPT_EN)) + rm_add_nb_req(padapter, psta); +} +#endif + unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) { uint i; @@ -3147,7 +2707,9 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) /* WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); */ u8 *pframe = precv_frame->u.hdr.rx_data; uint pkt_len = precv_frame->u.hdr.len; +#ifdef CONFIG_WAPI_SUPPORT PNDIS_802_11_VARIABLE_IEs pWapiIE = NULL; +#endif RTW_INFO("%s\n", __FUNCTION__); @@ -3155,7 +2717,7 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN)) return _SUCCESS; - if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE))) + if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)) || pmlmeext->join_abort) return _SUCCESS; if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) @@ -3205,6 +2767,9 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) case _HT_CAPABILITY_IE_: /* HT caps */ HT_caps_handler(padapter, pIE); +#ifdef ROKU_PRIVATE + HT_caps_handler_infra_ap(padapter, pIE); +#endif /* ROKU_PRIVATE */ break; case _HT_EXTRA_INFO_IE_: /* HT info */ @@ -3214,6 +2779,9 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) #ifdef CONFIG_80211AC_VHT case EID_VHTCapability: VHT_caps_handler(padapter, pIE); +#ifdef ROKU_PRIVATE + VHT_caps_handler_infra_ap(padapter, pIE); +#endif /* ROKU_PRIVATE */ break; case EID_VHTOperation: @@ -3232,6 +2800,23 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) padapter->tdlsinfo.ch_switch_prohibited = _TRUE; break; #endif /* CONFIG_TDLS */ + +#ifdef CONFIG_RTW_80211K + case _EID_RRM_EN_CAP_IE_: + RM_IE_handler(padapter, pIE); + break; +#endif + +#ifdef ROKU_PRIVATE + /* Infra mode, used to store AP's info , Parse the supported rates from AssocRsp */ + case _SUPPORTEDRATES_IE_: + Supported_rate_infra_ap(padapter, pIE); + break; + + case _EXT_SUPPORTEDRATES_IE_: + Extended_Supported_rate_infra_ap(padapter, pIE); + break; +#endif /* ROKU_PRIVATE */ default: break; } @@ -3255,8 +2840,11 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) else rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len); - report_join_res(padapter, res); + report_join_res(padapter, res, status); +#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K) + rtw_roam_nb_discover(padapter, _TRUE); +#endif return _SUCCESS; } @@ -3286,10 +2874,8 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); - rtw_lock_rx_suspend_timeout(8000); - #ifdef CONFIG_AP_MODE - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + if (MLME_IS_AP(padapter)) { _irqL irqL; struct sta_info *psta; struct sta_priv *pstapriv = &padapter->stapriv; @@ -3321,7 +2907,7 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } else #endif - { + if (!MLME_IS_MESH(padapter)) { int ignore_received_deauth = 0; /* Commented by Albert 20130604 */ @@ -3376,10 +2962,8 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); - rtw_lock_rx_suspend_timeout(8000); - #ifdef CONFIG_AP_MODE - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + if (MLME_IS_AP(padapter)) { _irqL irqL; struct sta_info *psta; struct sta_priv *pstapriv = &padapter->stapriv; @@ -3410,7 +2994,7 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } else #endif - { + if (!MLME_IS_MESH(padapter)) { RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n" , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe)); @@ -3446,7 +3030,7 @@ unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, struct ieee80211_info_element *ie; RTW_INFO(FUNC_NDEV_FMT" from "MAC_FMT"\n", - FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->hwaddr)); + FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->cmn.mac_addr)); for_each_ie(ie, ies, ies_len) { if (ie->id == WLAN_EID_CHANNEL_SWITCH) { @@ -3477,7 +3061,7 @@ unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, * 2. things after channel switching */ - ret = rtw_set_ch_cmd(padapter, ch, bwmode, ch_offset, _TRUE); + ret = rtw_set_chbw_cmd(padapter, ch, bwmode, ch_offset, 0); } exit: @@ -3495,8 +3079,6 @@ unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame) u8 category; u8 action; - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); - psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); if (!psta) @@ -3507,6 +3089,9 @@ unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame) goto exit; action = frame_body[1]; + + RTW_INFO(FUNC_ADPT_FMT" action:%u\n", FUNC_ADPT_ARG(padapter), action); + switch (action) { case RTW_WLAN_ACTION_SPCT_MSR_REQ: case RTW_WLAN_ACTION_SPCT_MSR_RPRT: @@ -3515,8 +3100,13 @@ unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame) break; case RTW_WLAN_ACTION_SPCT_CHL_SWITCH: #ifdef CONFIG_SPCT_CH_SWITCH - ret = on_action_spct_ch_switch(padapter, psta, &frame_body[2], - frame_len - (frame_body - pframe) - 2); + ret = on_action_spct_ch_switch(padapter, psta + , frame_body + 2, frame_len - (frame_body - pframe) - 2); +#elif defined(CONFIG_DFS) + if (MLME_IS_STA(padapter) && MLME_IS_ASOC(padapter)) { + process_csa_ie(padapter + , frame_body + 2, frame_len - (frame_body - pframe) - 2); + } #endif break; default: @@ -3542,12 +3132,13 @@ unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe) { unsigned int ret = _FAIL; struct sta_info *sta = NULL; - struct sta_priv *stapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct sta_priv *stapriv = &(adapter->stapriv); u8 *frame = rframe->u.hdr.rx_data; - uint frame_len = rframe->u.hdr.len; + u32 frame_len = rframe->u.hdr.len; u8 *frame_body = (u8 *)(frame + sizeof(struct rtw_ieee80211_hdr_3addr)); - u8 category; - u8 action; + u32 frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; int cnt = 0; char msg[16]; @@ -3562,6 +3153,15 @@ unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe) action = frame_body[1]; switch (action) { +#ifdef CONFIG_RTW_80211R + case RTW_WLAN_ACTION_WNM_BTM_REQ: + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_REQ recv.\n"); + rtw_wnm_process_btm_req(adapter, frame_body, frame_body_len); + } + ret = _SUCCESS; + break; +#endif default: #ifdef CONFIG_IOCTL_CFG80211 cnt += sprintf((msg + cnt), "ACT_WNM %u", action); @@ -3793,7 +3393,7 @@ u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta) struct mlme_priv *mlme = &adapter->mlmepriv; struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; s8 nss = -1; - u8 bw = rtw_min(sta->bw_mode, adapter->mlmeextpriv.cur_bwmode); + u8 bw = rtw_min(sta->cmn.bw_mode, adapter->mlmeextpriv.cur_bwmode); #ifdef CONFIG_80211AC_VHT if (is_supported_vht(sta->wireless_mode)) { @@ -3846,7 +3446,6 @@ u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 siz u16 rtw_rx_ampdu_apply(_adapter *adapter) { u16 adj_cnt = 0; - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; struct sta_info *sta; u8 accept = rtw_rx_ampdu_is_accept(adapter); u8 size; @@ -3856,7 +3455,7 @@ u16 rtw_rx_ampdu_apply(_adapter *adapter) else size = rtw_rx_ampdu_size(adapter); - if (mlmeext_msr(mlmeext) == WIFI_FW_STATION_STATE) { + if (MLME_IS_STA(adapter)) { sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv)); if (sta) { u8 sta_size = size; @@ -3865,8 +3464,9 @@ u16 rtw_rx_ampdu_apply(_adapter *adapter) sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta)); adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size); } + /* TODO: TDLS peer */ - } else if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE) { + } else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) { _irqL irqL; _list *phead, *plist; u8 peer_num = 0; @@ -3904,6 +3504,8 @@ u16 rtw_rx_ampdu_apply(_adapter *adapter) } } + /* TODO: ADHOC */ + return adj_cnt; } @@ -4030,28 +3632,26 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) } #ifdef CONFIG_P2P - -static int get_reg_classes_full_count(struct p2p_channels channel_list) +int get_reg_classes_full_count(struct p2p_channels *channel_list) { int cnt = 0; int i; - for (i = 0; i < channel_list.reg_classes; i++) - cnt += channel_list.reg_class[i].channels; + for (i = 0; i < channel_list->reg_classes; i++) + cnt += channel_list->reg_class[i].channels; return cnt; } void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) { - + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; u8 action = P2P_PUB_ACTION_ACTION; u32 p2poui = cpu_to_be32(P2POUI); u8 oui_subtype = P2P_GO_NEGO_REQ; u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; - u8 wpsielen = 0, p2pielen = 0, i; - u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; + u8 wpsielen = 0, p2pielen = 0; u16 len_channellist_attr = 0; #ifdef CONFIG_WFD u32 wfdielen = 0; @@ -4064,7 +3664,6 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) unsigned short *fctrl; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct wifidirect_info *pwdinfo = &(padapter->wdinfo); @@ -4276,8 +3875,8 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)(pmlmeext->channel_list.reg_classes) - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)(ch_list->reg_classes) + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) @@ -4322,36 +3921,22 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) /* Channel List */ p2pie[p2pielen++] = union_ch; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ /* Device Info */ /* Type: */ @@ -4456,17 +4041,16 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint len, u8 result) { - + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; u8 action = P2P_PUB_ACTION_ACTION; u32 p2poui = cpu_to_be32(P2POUI); u8 oui_subtype = P2P_GO_NEGO_RESP; u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; - u8 p2pielen = 0, i; + u8 p2pielen = 0; uint wpsielen = 0; u16 wps_devicepassword_id = 0x0000; uint wps_devicepassword_id_len = 0; - u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh; u16 len_channellist_attr = 0; struct xmit_frame *pmgntframe; @@ -4476,7 +4060,6 @@ void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint l unsigned short *fctrl; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #ifdef CONFIG_WFD @@ -4723,8 +4306,8 @@ void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint l /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)ch_list->reg_classes + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) @@ -4769,37 +4352,22 @@ void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint l /*Channel List*/ p2pie[p2pielen++] = union_chan; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ - /* Device Info */ /* Type: */ @@ -4895,8 +4463,8 @@ void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result) u8 action = P2P_PUB_ACTION_ACTION; u32 p2poui = cpu_to_be32(P2POUI); u8 oui_subtype = P2P_GO_NEGO_CONF; - u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; - u8 wpsielen = 0, p2pielen = 0; + u8 p2pie[255] = { 0x00 }; + u8 p2pielen = 0; struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; @@ -4905,7 +4473,6 @@ void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result) unsigned short *fctrl; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #ifdef CONFIG_WFD u32 wfdielen = 0; @@ -5125,15 +4692,14 @@ void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result) void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) { - + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; u8 action = P2P_PUB_ACTION_ACTION; u32 p2poui = cpu_to_be32(P2POUI); u8 oui_subtype = P2P_INVIT_REQ; u8 p2pie[255] = { 0x00 }; - u8 p2pielen = 0, i; + u8 p2pielen = 0; u8 dialogToken = 3; - u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; u16 len_channellist_attr = 0; #ifdef CONFIG_WFD u32 wfdielen = 0; @@ -5146,7 +4712,6 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) unsigned short *fctrl; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct wifidirect_info *pwdinfo = &(padapter->wdinfo); @@ -5279,8 +4844,8 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)ch_list->reg_classes + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) @@ -5322,36 +4887,22 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) /* Channel List */ p2pie[p2pielen++] = union_ch; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ /* P2P Group ID */ @@ -5439,14 +4990,13 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 status_code) { - + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; u8 action = P2P_PUB_ACTION_ACTION; u32 p2poui = cpu_to_be32(P2POUI); u8 oui_subtype = P2P_INVIT_RESP; u8 p2pie[255] = { 0x00 }; - u8 p2pielen = 0, i; - u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; + u8 p2pielen = 0; u16 len_channellist_attr = 0; #ifdef CONFIG_WFD u32 wfdielen = 0; @@ -5459,7 +5009,6 @@ void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken unsigned short *fctrl; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct wifidirect_info *pwdinfo = &(padapter->wdinfo); @@ -5597,8 +5146,8 @@ void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)ch_list->reg_classes + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) @@ -5640,36 +5189,22 @@ void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken /* Channel List */ p2pie[p2pielen++] = union_ch; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ } pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); @@ -5709,7 +5244,6 @@ void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 unsigned short *fctrl; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct wifidirect_info *pwdinfo = &(padapter->wdinfo); @@ -5830,7 +5364,6 @@ void issue_probersp_p2p(_adapter *padapter, unsigned char *da) unsigned char *mac; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); /* WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); */ u16 beacon_interval = 100; @@ -6157,11 +5690,8 @@ int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack) struct rtw_ieee80211_hdr *pwlanhdr; unsigned short *fctrl; unsigned char *mac; - unsigned char bssrate[NumRates]; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - int bssrate_len = 0; u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; @@ -6485,7 +6015,7 @@ int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms) { int ret; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); do { ret = _issue_probereq_p2p(adapter, da, wait_ms > 0 ? _TRUE : _FALSE); @@ -6556,7 +6086,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame) u8 *frame_body; #ifdef CONFIG_P2P u8 *p2p_ie; - u32 p2p_ielen, wps_ielen; + u32 p2p_ielen; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); u8 result = P2P_STATUS_SUCCESS; u8 empty_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; @@ -6694,7 +6224,6 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame) u8 status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; struct group_id_info group_id; u8 invitation_flag = 0; - int j = 0; merged_p2p_ielen = rtw_get_p2p_merged_ies_len(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_); @@ -6741,7 +6270,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame) u8 operatingch_info[5] = { 0x00 }; if (rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) { - if (rtw_chset_search_ch(padapter->mlmeextpriv.channel_set, (u32)operatingch_info[4]) >= 0) { + if (rtw_chset_search_ch(adapter_to_chset(padapter), (u32)operatingch_info[4]) >= 0) { /* The operating channel is acceptable for this device. */ pwdinfo->rx_invitereq_info.operation_ch[0] = operatingch_info[4]; #ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH @@ -6929,7 +6458,6 @@ unsigned int on_action_public_vendor(union recv_frame *precv_frame) { unsigned int ret = _FAIL; u8 *pframe = precv_frame->u.hdr.rx_data; - uint frame_len = precv_frame->u.hdr.len; u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); if (_rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE) { @@ -6950,7 +6478,6 @@ unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action) { unsigned int ret = _FAIL; u8 *pframe = precv_frame->u.hdr.rx_data; - uint frame_len = precv_frame->u.hdr.len; u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); u8 token; _adapter *adapter = precv_frame->u.hdr.adapter; @@ -7012,6 +6539,249 @@ unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame) return ret; } +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) +static u8 rtw_wnm_nb_elem_parsing( + u8* pdata, u32 data_len, u8 from_btm, + u32 *nb_rpt_num, u8 *nb_rpt_is_same, + struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates) +{ + u8 bfound = _FALSE, ret = _SUCCESS; + u8 *ptr, *pend, *op; + u32 elem_len, subelem_len, op_len; + u32 i, nb_rpt_entries = 0; + struct nb_rpt_hdr *pie; + struct wnm_btm_cant *pcandidate; + + if ((!pdata) || (!pnb)) + return _FAIL; + + if ((from_btm) && (!pcandidates)) + return _FAIL; + + ptr = pdata; + pend = ptr + data_len; + elem_len = data_len; + subelem_len = (u32)*(pdata+1); + + for (i=0; i < RTW_MAX_NB_RPT_NUM; i++) { + if (((ptr + 7) > pend) || (elem_len < subelem_len)) + break; + + if (*ptr != 0x34) { + RTW_ERR("WNM: invalid data(0x%2x)!\n", *ptr); + ret = _FAIL; + break; + } + + pie = (struct nb_rpt_hdr *)ptr; + if (from_btm) { + op = rtw_get_ie((u8 *)(ptr+15), + WNM_BTM_CAND_PREF_SUBEID, + &op_len, (subelem_len - 15)); + } + + ptr = (u8 *)(ptr + subelem_len + 2); + elem_len -= (subelem_len +2); + subelem_len = *(ptr+1); + if (from_btm) { + pcandidate = (pcandidates + i); + _rtw_memcpy(&pcandidate->nb_rpt, pie, sizeof(struct nb_rpt_hdr)); + if (op && (op_len !=0)) { + pcandidate->preference = *(op + 2); + bfound = _TRUE; + } else + pcandidate->preference = 0; + + RTW_DBG("WNM: preference check bssid("MAC_FMT + ") ,bss_info(0x%04X), reg_class(0x%02X), ch(%d)," + " phy_type(0x%02X), preference(0x%02X)\n", + MAC_ARG(pcandidate->nb_rpt.bssid), pcandidate->nb_rpt.bss_info, + pcandidate->nb_rpt.reg_class, pcandidate->nb_rpt.ch_num, + pcandidate->nb_rpt.phy_type, pcandidate->preference); + } else { + if (_rtw_memcmp(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr)) == _FALSE) + *nb_rpt_is_same = _FALSE; + _rtw_memcpy(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr)); + } + nb_rpt_entries++; + } + + if (from_btm) + pnb->preference_en = (bfound)?_TRUE:_FALSE; + + *nb_rpt_num = nb_rpt_entries; + return ret; +} + +/* selection sorting based on preference value + * IN : nb_rpt_entries - candidate num + * IN/OUT : pcandidates - candidate list + * return : TRUE - means pcandidates is updated. + */ +static u8 rtw_wnm_candidates_sorting( + u32 nb_rpt_entries, struct wnm_btm_cant *pcandidates) +{ + u8 updated = _FALSE; + u32 i, j, pos; + struct wnm_btm_cant swap; + struct wnm_btm_cant *pcant_1, *pcant_2; + + if ((!nb_rpt_entries) || (!pcandidates)) + return updated; + + for (i=0; i < (nb_rpt_entries - 1); i++) { + pos = i; + for (j=(i + 1); j < nb_rpt_entries; j++) { + pcant_1 = pcandidates+pos; + pcant_2 = pcandidates+j; + if ((pcant_1->preference) < (pcant_2->preference)) + pos = j; + } + + if (pos != i) { + updated = _TRUE; + _rtw_memcpy(&swap, (pcandidates+i), sizeof(struct wnm_btm_cant)); + _rtw_memcpy((pcandidates+i), (pcandidates+pos), sizeof(struct wnm_btm_cant)); + _rtw_memcpy((pcandidates+pos), &swap, sizeof(struct wnm_btm_cant)); + } + } + return updated; +} + +static void rtw_wnm_nb_info_update( + u32 nb_rpt_entries, u8 from_btm, + struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates, + u8 *nb_rpt_is_same) +{ + u8 is_found; + u32 i, j; + struct wnm_btm_cant *pcand; + + if (!pnb) + return; + + pnb->nb_rpt_ch_list_num = 0; + for (i=0; inb_rpt[i], &pcand->nb_rpt, + sizeof(struct nb_rpt_hdr)) == _FALSE) + *nb_rpt_is_same = _FALSE; + _rtw_memcpy(&pnb->nb_rpt[i], &pcand->nb_rpt, sizeof(struct nb_rpt_hdr)); + } + + RTW_DBG("WNM: bssid(" MAC_FMT + ") , bss_info(0x%04X), reg_class(0x%02X), ch_num(%d), phy_type(0x%02X)\n", + MAC_ARG(pnb->nb_rpt[i].bssid), pnb->nb_rpt[i].bss_info, + pnb->nb_rpt[i].reg_class, pnb->nb_rpt[i].ch_num, + pnb->nb_rpt[i].phy_type); + + if (pnb->nb_rpt[i].ch_num == 0) + continue; + + for (j=0; jnb_rpt[i].ch_num == pnb->nb_rpt_ch_list[j].hw_value) { + is_found = _TRUE; + break; + } + } + + if (!is_found) { + pnb->nb_rpt_ch_list[pnb->nb_rpt_ch_list_num].hw_value = pnb->nb_rpt[i].ch_num; + pnb->nb_rpt_ch_list_num++; + } + } +} + +static void rtw_wnm_btm_candidate_select(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + struct wlan_network *pnetwork; + u8 bfound = _FALSE; + u32 i; + + for (i = 0; i < pnb->last_nb_rpt_entries; i++) { + pnetwork = rtw_find_network( + &(pmlmepriv->scanned_queue), + pnb->nb_rpt[i].bssid); + + if (pnetwork) { + bfound = _TRUE; + break; + } + } + + if (bfound) { + _rtw_memcpy(pnb->roam_target_addr, pnb->nb_rpt[i].bssid, ETH_ALEN); + RTW_INFO("WNM : select btm entry(%d) - %s("MAC_FMT", ch%u) rssi:%d\n" + , i + , pnetwork->network.Ssid.Ssid + , MAC_ARG(pnetwork->network.MacAddress) + , pnetwork->network.Configuration.DSConfig + , (int)pnetwork->network.Rssi); + } else + _rtw_memset(pnb->roam_target_addr,0, ETH_ALEN); +} + +u32 rtw_wnm_btm_candidates_survey( + _adapter *padapter, u8* pframe, u32 elem_len, u8 from_btm) +{ + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + struct wnm_btm_cant *pcandidate_list = NULL; + u8 nb_rpt_is_same = _TRUE; + u32 ret = _FAIL; + u32 nb_rpt_entries = 0; + + if (from_btm) { + u32 mlen = sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM; + pcandidate_list = (struct wnm_btm_cant *)rtw_malloc(mlen); + if (pcandidate_list == NULL) + goto exit; + } + + /*clean the status set last time*/ + _rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list)); + pnb->nb_rpt_valid = _FALSE; + if (!rtw_wnm_nb_elem_parsing( + pframe, elem_len, from_btm, + &nb_rpt_entries, &nb_rpt_is_same, + pnb, pcandidate_list)) + goto exit; + + if (nb_rpt_entries != 0) { + if ((from_btm) && (rtw_wnm_btm_preference_cap(padapter))) + rtw_wnm_candidates_sorting(nb_rpt_entries, pcandidate_list); + + rtw_wnm_nb_info_update( + nb_rpt_entries, from_btm, + pnb, pcandidate_list, &nb_rpt_is_same); + } + + RTW_INFO("nb_rpt_is_same = %d, nb_rpt_entries = %d, last_nb_rpt_entries = %d\n", + nb_rpt_is_same, nb_rpt_entries, pnb->last_nb_rpt_entries); + if ((nb_rpt_is_same == _TRUE) && (nb_rpt_entries == pnb->last_nb_rpt_entries)) + pnb->nb_rpt_is_same = _TRUE; + else { + pnb->nb_rpt_is_same = _FALSE; + pnb->last_nb_rpt_entries = nb_rpt_entries; + } + + if ((from_btm) && (nb_rpt_entries != 0)) + rtw_wnm_btm_candidate_select(padapter); + + pnb->nb_rpt_valid = _TRUE; + ret = _SUCCESS; + +exit: + if (from_btm && pcandidate_list) + rtw_mfree((u8 *)pcandidate_list, sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM); + + return ret; +} +#endif + unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) { #ifdef CONFIG_RTW_80211R @@ -7029,13 +6799,13 @@ unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) struct mlme_ext_info *pmlmeinfo = NULL; struct mlme_priv *pmlmepriv = NULL; struct wlan_network *proam_target = NULL; - ft_priv *pftpriv = NULL; + struct ft_roam_info *pft_roam = NULL; _irqL irqL; - pmlmeext = &padapter->mlmeextpriv; + pmlmeext = &(padapter->mlmeextpriv); pmlmeinfo = &(pmlmeext->mlmext_info); - pmlmepriv = &padapter->mlmepriv; - pftpriv = &pmlmepriv->ftpriv; + pmlmepriv = &(padapter->mlmepriv); + pft_roam = &(pmlmepriv->ft_roam); pframe = precv_frame->u.hdr.rx_data; frame_len = precv_frame->u.hdr.len; pframe_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); @@ -7046,8 +6816,8 @@ unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) action_code = pframe_body[1]; switch (action_code) { - case RTW_WLAN_ACTION_FT_RESPONSE: - RTW_INFO("FT: %s RTW_WLAN_ACTION_FT_RESPONSE\n", __func__); + case RTW_WLAN_ACTION_FT_RSP: + RTW_INFO("FT: RTW_WLAN_ACTION_FT_RSP recv.\n"); if (!_rtw_memcmp(adapter_mac_addr(padapter), &pframe_body[2], ETH_ALEN)) { RTW_ERR("FT: Unmatched STA MAC Address "MAC_FMT"\n", MAC_ARG(&pframe_body[2])); goto exit; @@ -7066,24 +6836,24 @@ unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) pie = rtw_get_ie(pframe_body, _MDIE_, &ft_ie_len, frame_len); if (pie) { - if (!_rtw_memcmp(&pftpriv->mdid, pie+2, 2)) { + if (!_rtw_memcmp(&pft_roam->mdid, pie+2, 2)) { RTW_ERR("FT: Invalid MDID\n"); goto exit; } } - rtw_set_ft_status(padapter, RTW_FT_REQUESTED_STA); + rtw_ft_set_status(padapter, RTW_FT_REQUESTED_STA); _cancel_timer_ex(&pmlmeext->ft_link_timer); /*Disconnect current AP*/ receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress, WLAN_REASON_ACTIVE_ROAM, _FALSE); - pftpriv->ft_action_len = frame_len; - _rtw_memcpy(pftpriv->ft_action, pframe, rtw_min(frame_len, RTW_MAX_FTIE_SZ)); + pft_roam->ft_action_len = frame_len; + _rtw_memcpy(pft_roam->ft_action, pframe, rtw_min(frame_len, RTW_FT_MAX_IE_SZ)); ret = _SUCCESS; break; - case RTW_WLAN_ACTION_FT_REQUEST: - case RTW_WLAN_ACTION_FT_CONFIRM: + case RTW_WLAN_ACTION_FT_REQ: + case RTW_WLAN_ACTION_FT_CONF: case RTW_WLAN_ACTION_FT_ACK: default: RTW_ERR("FT: Unsupported FT Action!\n"); @@ -7097,10 +6867,241 @@ unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) #endif } +#ifdef CONFIG_RTW_WNM +u8 rtw_wmn_btm_rsp_reason_decision(_adapter *padapter, u8* req_mode) +{ + struct recv_priv *precvpriv = &padapter->recvpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 reason = 0; + + if (!rtw_wnm_btm_diff_bss(padapter)) { + /* Reject - No suitable BSS transition candidates */ + reason = 7; + goto candidate_remove; + } + +#ifdef CONFIG_RTW_80211R + if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) { + /* Accept */ + reason = 0; + goto under_survey; + } +#endif + + if (((*req_mode) & DISASSOC_IMMINENT) == 0) { + /* Reject - Unspecified reject reason */ + reason = 1; + goto candidate_remove; + } + + if (precvpriv->signal_strength_data.avg_val >= pmlmepriv->roam_rssi_threshold) { + reason = 1; + goto candidate_remove; + } + +under_survey: + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) { + RTW_INFO("%s reject due to _FW_UNDER_SURVEY\n", __func__); + reason = 1; + } + +candidate_remove: + if (reason !=0) + rtw_wnm_reset_btm_candidate(&padapter->mlmepriv.nb_info); + + return reason; +} + +static u32 rtw_wnm_btm_candidates_offset_get(u8* pframe) +{ + u8 *pos = pframe; + u32 offset = 0; + + if (!pframe) + return 0; + + offset += 7; + pos += offset; + + /* BSS Termination Duration check */ + if (wnm_btm_bss_term_inc(pframe)) { + offset += 12; + pos += offset; + } + + /* Session Information URL check*/ + if (wnm_btm_ess_disassoc_im(pframe)) { + /*URL length field + URL variable length*/ + offset = 1 + *(pframe + offset); + pos += offset; + } + + offset = (pos - pframe); + return offset; +} + +static void rtw_wnm_btm_req_hdr_parsing(u8* pframe, struct btm_req_hdr *phdr) +{ + u8 *pos = pframe; + u32 offset = 0; + + if (!pframe || !phdr) + return; + + _rtw_memset(phdr, 0, sizeof(struct btm_req_hdr)); + phdr->req_mode = wnm_btm_req_mode(pframe); + phdr->disassoc_timer = wnm_btm_disassoc_timer(pframe); + phdr->validity_interval = wnm_btm_valid_interval(pframe); + if (wnm_btm_bss_term_inc(pframe)) { + _rtw_memcpy(&phdr->term_duration, + wnm_btm_term_duration_offset(pframe), + sizeof(struct btm_term_duration)); + } + + RTW_DBG("WNM: req_mode(%1x), disassoc_timer(%02x), interval(%x)\n", + phdr->req_mode, phdr->disassoc_timer, phdr->validity_interval); + if (wnm_btm_bss_term_inc(pframe)) + RTW_INFO("WNM: tsf(%llx), duration(%2x)\n", + phdr->term_duration.tsf, phdr->term_duration.duration); +} + +void rtw_wnm_roam_scan_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if (rtw_is_scan_deny(padapter)) + RTW_INFO("WNM: roam scan would abort by scan_deny!\n"); + + pmlmepriv->need_to_roam = _TRUE; + rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM); +} + +static void rtw_wnm_roam_scan(_adapter *padapter) +{ + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + + if (rtw_is_scan_deny(padapter)) { + _cancel_timer_ex(&pnb->roam_scan_timer); + _set_timer(&pnb->roam_scan_timer, 1000); + } else + rtw_wnm_roam_scan_hdl((void *)padapter); +} + +void rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len) +{ + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + struct btm_req_hdr req_hdr; + u8 *ptr, reason; + u32 elem_len, offset; + + rtw_wnm_btm_req_hdr_parsing(pframe, &req_hdr); + offset = rtw_wnm_btm_candidates_offset_get(pframe); + if ((offset == 0) || ((frame_len - offset) <= 15)) + return; + + ptr = (pframe + offset); + elem_len = (frame_len - offset); + rtw_wnm_btm_candidates_survey(padapter, ptr, elem_len, _TRUE); + reason = rtw_wmn_btm_rsp_reason_decision(padapter, &pframe[3]); + rtw_wnm_issue_action(padapter, + RTW_WLAN_ACTION_WNM_BTM_RSP, reason); + + if (reason == 0) + rtw_wnm_roam_scan(padapter); +} + +void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb) +{ + pnb->preference_en = _FALSE; + _rtw_memset(pnb->roam_target_addr, 0, ETH_ALEN); +} + +void rtw_wnm_reset_btm_state(_adapter *padapter) +{ + struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info); + + pnb->last_nb_rpt_entries = 0; + pnb->nb_rpt_is_same = _TRUE; + pnb->nb_rpt_valid = _FALSE; + pnb->nb_rpt_ch_list_num = 0; + rtw_wnm_reset_btm_candidate(pnb); + _rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt)); + _rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list)); +} + +void rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct xmit_frame *pmgntframe; + struct rtw_ieee80211_hdr *pwlanhdr; + struct pkt_attrib *pattrib; + u8 category, dialog_token, termination_delay, *pframe; + u16 *fctrl; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + return ; + + pattrib = &(pmgntframe->attrib); + update_mgntframe_attrib(padapter, pattrib); + _rtw_memset(pmgntframe->buf_addr, 0, (WLANHDR_OFFSET + TXDESC_OFFSET)); + + pframe = (u8 *)(pmgntframe->buf_addr + TXDESC_OFFSET); + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + category = RTW_WLAN_CATEGORY_WNM; + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + + switch (action) { + case RTW_WLAN_ACTION_WNM_BTM_QUERY: + pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen)); + RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_QUERY sent.\n"); + break; + case RTW_WLAN_ACTION_WNM_BTM_RSP: + termination_delay = 0; + pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(termination_delay), &(pattrib->pktlen)); + if (!is_zero_mac_addr(pmlmepriv->nb_info.roam_target_addr)) { + pframe = rtw_set_fixed_ie(pframe, 6, + pmlmepriv->nb_info.roam_target_addr, &(pattrib->pktlen)); + } + RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_RSP sent. reason = %d\n", reason); + break; + default: + goto exit; + } + + pattrib->last_txcmdsz = pattrib->pktlen; + dump_mgntframe(padapter, pmgntframe); + +exit: + return; +} +#endif + unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame) { u8 *pframe = precv_frame->u.hdr.rx_data; - uint frame_len = precv_frame->u.hdr.len; u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); u8 category, action; @@ -7182,6 +7183,15 @@ unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame } #endif /* CONFIG_IEEE80211W */ +unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_RTW_80211K + return rm_on_action(padapter, precv_frame); +#else + return _SUCCESS; +#endif /* CONFIG_RTW_80211K */ +} + unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame) { return _SUCCESS; @@ -7190,9 +7200,7 @@ unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame) unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame) { #ifdef CONFIG_80211AC_VHT - struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib; u8 *pframe = precv_frame->u.hdr.rx_data; - uint frame_len = precv_frame->u.hdr.len; struct rtw_ieee80211_hdr_3addr *whdr = (struct rtw_ieee80211_hdr_3addr *)pframe; u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); u8 category, action; @@ -7401,21 +7409,13 @@ void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib) struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *pbcmc_sta = NULL; psta = rtw_get_stainfo(pstapriv, pattrib->ra); - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); pattrib->hdrlen = 24; pattrib->nr_frags = 1; pattrib->priority = 7; - - if (pbcmc_sta) - pattrib->mac_id = pbcmc_sta->mac_id; - else { - pattrib->mac_id = 0; - RTW_INFO("mgmt use mac_id 0 will affect RA\n"); - } + pattrib->mac_id = RTW_DEFAULT_MGMT_MACID; pattrib->qsel = QSLT_MGNT; pattrib->pktlen = 0; @@ -7467,23 +7467,12 @@ void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib) u8 wireless_mode; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct sta_info *pbcmc_sta = NULL; /* _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); */ - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); - pattrib->hdrlen = 24; pattrib->nr_frags = 1; pattrib->priority = 7; - - if (pbcmc_sta) - pattrib->mac_id = pbcmc_sta->mac_id; - else { - pattrib->mac_id = 1; /* use STA's BCMC sta-info macid */ - - if (MLME_IS_AP(padapter) || MLME_IS_GO(padapter)) - RTW_INFO("%s-"ADPT_FMT" get bcmc sta_info fail,use MACID=1\n", __func__, ADPT_ARG(padapter)); - } + pattrib->mac_id = RTW_DEFAULT_MGMT_MACID; pattrib->qsel = QSLT_MGNT; #ifdef CONFIG_MCC_MODE @@ -7520,24 +7509,26 @@ void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntfr { u8 *pframe; struct pkt_attrib *pattrib = &pmgntframe->attrib; -#ifdef CONFIG_BEAMFORMING +#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) struct sta_info *sta = NULL; -#endif /* CONFIG_BEAMFORMING */ +#endif pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; _rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN); _rtw_memcpy(pattrib->ta, get_addr2_ptr(pframe), ETH_ALEN); -#ifdef CONFIG_BEAMFORMING +#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) sta = pattrib->psta; if (!sta) { sta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); pattrib->psta = sta; } + #ifdef CONFIG_BEAMFORMING if (sta) update_attrib_txbf_info(padapter, pattrib, sta); -#endif /* CONFIG_BEAMFORMING */ + #endif +#endif /* defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) */ } void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe) @@ -7721,6 +7712,10 @@ void issue_beacon(_adapter *padapter, int timeout_ms) if (padapter->hw_port == HW_PORT1) pattrib->mbssid = 1; #endif +#ifdef CONFIG_FW_HANDLE_TXBCN + if (padapter->vap_id != CONFIG_LIMITED_AP_NUM) + pattrib->mbssid = padapter->vap_id; +#endif _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); @@ -7742,7 +7737,7 @@ void issue_beacon(_adapter *padapter, int timeout_ms) pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { /* RTW_INFO("ie len=%d\n", cur_network->IELength); */ #ifdef CONFIG_P2P /* for P2P : Primary Device Type & Device Name */ @@ -7866,6 +7861,12 @@ void issue_beacon(_adapter *padapter, int timeout_ms) _clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS); } +#ifdef CONFIG_RTW_80211K + pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, + sizeof(padapter->rmpriv.rm_en_cap_def), + padapter->rmpriv.rm_en_cap_def, &pattrib->pktlen); +#endif + #ifdef CONFIG_P2P if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { u32 len; @@ -7894,7 +7895,9 @@ void issue_beacon(_adapter *padapter, int timeout_ms) #endif } #endif /* CONFIG_P2P */ - +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen); +#endif #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_BEACON_VENDOR_IE_BIT); #endif @@ -7961,8 +7964,10 @@ void issue_beacon(_adapter *padapter, int timeout_ms) _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); #endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ - if ((pattrib->pktlen + TXDESC_SIZE) > 512) { - RTW_INFO("beacon frame too large\n"); + if ((pattrib->pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) { + RTW_ERR("beacon frame too large ,len(%d,%d)\n", + (pattrib->pktlen + TXDESC_SIZE), MAX_BEACON_LEN); + rtw_warn_on(1); return; } @@ -7996,9 +8001,6 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe unsigned int rate_len; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif #endif /* CONFIG_P2P */ /* RTW_INFO("%s\n", __FUNCTION__); */ @@ -8116,6 +8118,9 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe pattrib->pktlen += ssid_ielen_diff; } } +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen); +#endif #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_PROBERESP_VENDOR_IE_BIT); #endif @@ -8175,6 +8180,12 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe } +#ifdef CONFIG_RTW_80211K + pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, + sizeof(padapter->rmpriv.rm_en_cap_def), + padapter->rmpriv.rm_en_cap_def, &pattrib->pktlen); +#endif + #ifdef CONFIG_P2P if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) /* IOT issue, When wifi_spec is not set, send probe_resp with P2P IE even if probe_req has no P2P IE */ @@ -8224,7 +8235,7 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe u16 cu_ch = (u16)cur_network->Configuration.DSConfig; RTW_INFO("%s, reply rc(pid=0x%x) device "MAC_FMT" in ch=%d\n", __FUNCTION__, - psta->pid, MAC_ARG(psta->hwaddr), cu_ch); + psta->pid, MAC_ARG(psta->cmn.mac_addr), cu_ch); /* append vendor specific ie */ _rtw_memcpy(RC_INFO, RC_OUI, sizeof(RC_OUI)); @@ -8247,7 +8258,7 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe } -int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, int wait_ack) +int _issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int wait_ack) { int ret = _FAIL; struct xmit_frame *pmgntframe; @@ -8260,9 +8271,11 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); int bssrate_len = 0; u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); +#endif if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; @@ -8281,6 +8294,13 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + if ((pwdev_priv->pno_mac_addr[0] != 0xFF) + && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) + && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) + mac = pwdev_priv->pno_mac_addr; + else +#endif mac = adapter_mac_addr(padapter); fctrl = &(pwlanhdr->frame_ctl); @@ -8298,14 +8318,30 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); - pmlmeext->mgnt_seq++; +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + if ((pwdev_priv->pno_mac_addr[0] != 0xFF) + && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) + && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) { +#ifdef CONFIG_RTW_DEBUG + RTW_DBG("%s pno_scan_seq_num: %d\n", __func__, + pwdev_priv->pno_scan_seq_num); +#endif + SetSeqNum(pwlanhdr, pwdev_priv->pno_scan_seq_num); + pattrib->seqnum = pwdev_priv->pno_scan_seq_num; + pattrib->qos_en = 1; + pwdev_priv->pno_scan_seq_num++; + } else +#endif + { + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + } set_frame_sub_type(pframe, WIFI_PROBEREQ); pframe += sizeof(struct rtw_ieee80211_hdr_3addr); pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - if (pssid) + if (pssid && !MLME_IS_MESH(padapter)) pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen)); else pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen)); @@ -8321,6 +8357,15 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, if (ch) pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, &ch, &pattrib->pktlen); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + if (pssid) + pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, pssid->Ssid, pssid->SsidLength); + else + pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, NULL, 0); + } +#endif + if (append_wps) { /* add wps_ie for wps2.0 */ if (pmlmepriv->wps_probe_req_ie_len > 0 && pmlmepriv->wps_probe_req_ie) { @@ -8348,7 +8393,7 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, return ret; } -inline void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da) +inline void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da) { _issue_probereq(padapter, pssid, da, 0, 1, _FALSE); } @@ -8358,12 +8403,12 @@ inline void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da) * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX * try_cnt means the maximal TX count to try */ -int issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, +int issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms) { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; @@ -8416,14 +8461,6 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); -#ifdef CONFIG_RTW_80211R - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - ft_priv *pftpriv = &pmlmepriv->ftpriv; - u8 is_ft_roaming = _FALSE; - u8 is_ft_roaming_with_rsn_ie = _TRUE; - u8 *pie = NULL; - u32 ft_ie_len = 0; -#endif if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) return; @@ -8455,7 +8492,7 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status if (psta) { /* for AP mode */ #ifdef CONFIG_NATIVEAP_MLME - _rtw_memcpy(pwlanhdr->addr1, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); @@ -8493,11 +8530,9 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); #ifdef CONFIG_RTW_80211R - /*For Fast BSS Transition */ - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - is_ft_roaming = _TRUE; - val16 = 2; /* 2: 802.11R FTAA */ - val16 = cpu_to_le16(val16); + if (rtw_ft_roam(padapter)) { + /* 2: 802.11R FTAA */ + val16 = cpu_to_le16(2); } else #endif { @@ -8535,21 +8570,7 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); #ifdef CONFIG_RTW_80211R - if (is_ft_roaming == _TRUE) { - pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie) - pframe = rtw_set_ie(pframe, EID_WPA2, ft_ie_len, pie+2, &(pattrib->pktlen)); - else - is_ft_roaming_with_rsn_ie = _FALSE; - - pie = rtw_get_ie(pftpriv->updated_ft_ies, _MDIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie) - pframe = rtw_set_ie(pframe, _MDIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); - - pie = rtw_get_ie(pftpriv->updated_ft_ies, _FTIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie && is_ft_roaming_with_rsn_ie) - pframe = rtw_set_ie(pframe, _FTIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); - } + rtw_ft_build_auth_req_ies(padapter, pattrib, &pframe); #endif /* then checking to see if sending challenging text... */ @@ -8625,7 +8646,7 @@ void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *p fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->hwaddr, ETH_ALEN); + _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->cmn.mac_addr, ETH_ALEN); _rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); @@ -8649,7 +8670,7 @@ void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *p ie_status = cpu_to_le16(status); pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&ie_status, &(pattrib->pktlen)); - val = cpu_to_le16(pstat->aid | BIT(14) | BIT(15)); + val = cpu_to_le16(pstat->cmn.aid | BIT(14) | BIT(15)); pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen)); if (pstat->bssratelen <= 8) @@ -8805,14 +8826,13 @@ void _issue_assocreq(_adapter *padapter, u8 is_reassoc) int ret = _FAIL; struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; - unsigned char *pframe, *p; + unsigned char *pframe; struct rtw_ieee80211_hdr *pwlanhdr; unsigned short *fctrl; unsigned short val16; - unsigned int i, j, ie_len, index = 0; - unsigned char rf_type, bssrate[NumRates], sta_bssrate[NumRates]; + unsigned int i, j, index = 0; + unsigned char bssrate[NumRates], sta_bssrate[NumRates]; PNDIS_802_11_VARIABLE_IEs pIE; - struct registry_priv *pregpriv = &padapter->registrypriv; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); @@ -8829,17 +8849,13 @@ void _issue_assocreq(_adapter *padapter, u8 is_reassoc) #endif /* CONFIG_P2P */ #ifdef CONFIG_DFS + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u16 cap; /* Dot H */ u8 pow_cap_ele[2] = { 0x00 }; u8 sup_ch[30 * 2] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; /* For supported channel */ #endif /* CONFIG_DFS */ -#ifdef CONFIG_RTW_80211R - u8 *pie = NULL; - u32 ft_ie_len = 0; - ft_priv *pftpriv = &pmlmepriv->ftpriv; -#endif if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; @@ -8912,13 +8928,13 @@ void _issue_assocreq(_adapter *padapter, u8 is_reassoc) pframe = rtw_set_ie(pframe, EID_PowerCap, 2, pow_cap_ele, &(pattrib->pktlen)); /* supported channels */ - while (sup_ch_idx < pmlmeext->max_chan_nums && pmlmeext->channel_set[sup_ch_idx].ChannelNum != 0) { - if (pmlmeext->channel_set[sup_ch_idx].ChannelNum <= 14) { + while (sup_ch_idx < rfctl->max_chan_nums && rfctl->channel_set[sup_ch_idx].ChannelNum != 0) { + if (rfctl->channel_set[sup_ch_idx].ChannelNum <= 14) { /* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */ sup_ch[0] = 1; /* First channel number */ - sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; /* Number of channel */ + sup_ch[1] = rfctl->channel_set[sup_ch_idx].ChannelNum; /* Number of channel */ } else { - sup_ch[idx_5g++] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; + sup_ch[idx_5g++] = rfctl->channel_set[sup_ch_idx].ChannelNum; sup_ch[idx_5g++] = 1; } sup_ch_idx++; @@ -9008,6 +9024,16 @@ void _issue_assocreq(_adapter *padapter, u8 is_reassoc) else RTW_INFO("%s: Connect to AP without 11b and 11g data rate!\n", __FUNCTION__); +#ifdef CONFIG_RTW_80211K + if (pmlmeinfo->network.PhyInfo.rm_en_cap[0] /* RM Enabled Capabilities */ + | pmlmeinfo->network.PhyInfo.rm_en_cap[1] + | pmlmeinfo->network.PhyInfo.rm_en_cap[2] + | pmlmeinfo->network.PhyInfo.rm_en_cap[3] + | pmlmeinfo->network.PhyInfo.rm_en_cap[4]) + pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, 5, + (u8 *)padapter->rmpriv.rm_en_cap_def, &(pattrib->pktlen)); +#endif /* CONFIG_RTW_80211K */ + /* vendor specific IE, such as WPA, WMM, WPS */ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) { pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); @@ -9032,10 +9058,8 @@ void _issue_assocreq(_adapter *padapter, u8 is_reassoc) case EID_WPA2: #ifdef CONFIG_RTW_80211R - if ((is_reassoc == _TRUE) && (rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie) - pframe = rtw_set_ie(pframe, EID_WPA2, ft_ie_len, pie+2, &(pattrib->pktlen)); + if ((is_reassoc) && (rtw_ft_roam(padapter))) { + rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe); } else #endif pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen)); @@ -9232,31 +9256,14 @@ void _issue_assocreq(_adapter *padapter, u8 is_reassoc) pframe += wfdielen; pattrib->pktlen += wfdielen; #endif +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen); +#endif #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_ASSOCREQ_VENDOR_IE_BIT); #endif #ifdef CONFIG_RTW_80211R - if (rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - u8 mdieval[3] = {0}; - - _rtw_memcpy(mdieval, &(pftpriv->mdid), 2); - mdieval[2] = pftpriv->ft_cap; - pframe = rtw_set_ie(pframe, _MDIE_, 3, mdieval, &(pattrib->pktlen)); - } - - if (is_reassoc == _TRUE) { - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - u8 is_ft_roaming_with_rsn_ie = _TRUE; - - pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (!pie) - is_ft_roaming_with_rsn_ie = _FALSE; - - pie = rtw_get_ie(pftpriv->updated_ft_ies, _FTIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie && is_ft_roaming_with_rsn_ie) - pframe = rtw_set_ie(pframe, _FTIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); - } - } + rtw_ft_build_assoc_req_ies(padapter, is_reassoc, pattrib, &pframe); #endif pattrib->last_txcmdsz = pattrib->pktlen; @@ -9295,6 +9302,7 @@ static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int p struct xmit_priv *pxmitpriv; struct mlme_ext_priv *pmlmeext; struct mlme_ext_info *pmlmeinfo; + u8 a4_shift; /* RTW_INFO("%s:%d\n", __FUNCTION__, power_mode); */ @@ -9325,24 +9333,38 @@ static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int p fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) + if (MLME_IS_AP(padapter)) SetFrDs(fctrl); - else if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) + else if (MLME_IS_STA(padapter)) SetToDs(fctrl); + else if (MLME_IS_MESH(padapter)) { + SetToDs(fctrl); + SetFrDs(fctrl); + } if (power_mode) SetPwrMgt(fctrl); - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + if (get_tofr_ds(fctrl) == 3) { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN); + a4_shift = ETH_ALEN; + pattrib->hdrlen += ETH_ALEN; + } else { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + a4_shift = 0; + } SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; set_frame_sub_type(pframe, WIFI_DATA_NULL); - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pframe += sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift; + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift; pattrib->last_txcmdsz = pattrib->pktlen; @@ -9358,8 +9380,6 @@ static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int p } /* - * [IMPORTANT] Don't call this function in interrupt context - * * When wait_ms > 0, this function should be called at process context * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX @@ -9370,48 +9390,17 @@ int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mod { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct sta_info *psta; - u8 macid_sleep_reg_access = _TRUE; - -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - /* driver doesn't access macid sleep reg under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { - macid_sleep_reg_access = _FALSE; - - if (da == NULL) { - RTW_INFO("Warning: Do not tx null data to AP under MCC mode\n"); - rtw_warn_on(1); - } - - } - } -#endif if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; - /* da == NULL, assum it's null data for sta to ap*/ + /* da == NULL, assum it's null data for sta to ap */ if (da == NULL) da = get_my_bssid(&(pmlmeinfo->network)); - psta = rtw_get_stainfo(&padapter->stapriv, da); - if (psta) { - if (macid_sleep_reg_access) { - if (power_mode) - rtw_hal_macid_sleep(padapter, psta->mac_id); - else - rtw_hal_macid_wakeup(padapter, psta->mac_id); - } - } else { - RTW_INFO(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n", - FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? "sleep" : "wakeup"); - rtw_warn_on(1); - } - do { ret = _issue_nulldata(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE); @@ -9446,33 +9435,8 @@ int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mod return ret; } -/* - * [IMPORTANT] This function run in interrupt context - * - * The null data packet would be sent without power bit, - * and not guarantee success. - */ -s32 issue_nulldata_in_interrupt(PADAPTER padapter, u8 *da, unsigned int power_mode) -{ - int ret; - struct mlme_ext_priv *pmlmeext; - struct mlme_ext_info *pmlmeinfo; - - - pmlmeext = &padapter->mlmeextpriv; - pmlmeinfo = &pmlmeext->mlmext_info; - - /* da == NULL, assum it's null data for sta to ap*/ - if (da == NULL) - da = get_my_bssid(&(pmlmeinfo->network)); - - ret = _issue_nulldata(padapter, da, power_mode, _FALSE); - - return ret; -} - /* when wait_ack is ture, this function shoule be called at process context */ -static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int wait_ack) +static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int wait_ack) { int ret = _FAIL; struct xmit_frame *pmgntframe; @@ -9483,11 +9447,12 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 a4_shift; if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; - RTW_INFO("%s\n", __FUNCTION__); + /* RTW_INFO("%s\n", __FUNCTION__); */ pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) @@ -9511,14 +9476,35 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) + if (MLME_IS_AP(padapter)) SetFrDs(fctrl); - else if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) + else if (MLME_IS_STA(padapter)) + SetToDs(fctrl); + else if (MLME_IS_MESH(padapter)) { SetToDs(fctrl); + SetFrDs(fctrl); + } + + if (ps) + SetPwrMgt(fctrl); if (pattrib->mdata) SetMData(fctrl); + if (get_tofr_ds(fctrl) == 3) { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN); + a4_shift = ETH_ALEN; + pattrib->hdrlen += ETH_ALEN; + } else { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + a4_shift = 0; + } + qc = (unsigned short *)(pframe + pattrib->hdrlen - 2); SetPriority(qc, tid); @@ -9527,16 +9513,12 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i SetAckpolicy(qc, pattrib->ack_policy); - _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); pmlmeext->mgnt_seq++; set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); - pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos); - pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); + pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift; + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift; pattrib->last_txcmdsz = pattrib->pktlen; @@ -9558,11 +9540,11 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i * try_cnt means the maximal TX count to try * da == NULL for station mode */ -int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms) +int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms) { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -9574,7 +9556,7 @@ int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_c da = get_my_bssid(&(pmlmeinfo->network)); do { - ret = _issue_qos_nulldata(padapter, da, tid, wait_ms > 0 ? _TRUE : _FALSE); + ret = _issue_qos_nulldata(padapter, da, tid, ps, wait_ms > 0 ? _TRUE : _FALSE); i++; @@ -9703,7 +9685,7 @@ int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_c { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; @@ -9744,17 +9726,13 @@ int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_c void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset) { - _irqL irqL; - _list *plist, *phead; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; unsigned char *pframe; struct rtw_ieee80211_hdr *pwlanhdr; unsigned short *fctrl; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) return; @@ -9873,7 +9851,7 @@ void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned ch pmlmeext->sa_query_seq++; /* send sa query request to AP, AP should reply sa query response in 1 second */ if (pattrib->key_type == IEEE80211W_RIGHT_KEY) { - psta = rtw_get_stainfo(pstapriv, raddr); + psta = rtw_get_stainfo(pstapriv, pwlanhdr->addr1); if (psta != NULL) { /* RTW_INFO("%s, %d, set dot11w_expire_timer\n", __func__, __LINE__); */ _set_timer(&psta->dot11w_expire_timer, 1000); @@ -10123,7 +10101,7 @@ inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter))) goto exit; @@ -10201,7 +10179,7 @@ int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter))) goto exit; @@ -10241,7 +10219,7 @@ int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 return ret; } -static void issue_action_BSSCoexistPacket(_adapter *padapter) +void issue_action_BSSCoexistPacket(_adapter *padapter) { _irqL irqL; _list *plist, *phead; @@ -10482,7 +10460,7 @@ int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 New { int ret = _FAIL; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) goto exit; @@ -10563,9 +10541,9 @@ static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct if (rtw_del_rx_ampdu_test_trigger_no_tx_fail()) ret = _FAIL; else if (wait_ack) - ret = issue_del_ba_ex(adapter, sta->hwaddr, tid, 37, initiator, 3, 1); + ret = issue_del_ba_ex(adapter, sta->cmn.mac_addr, tid, 37, initiator, 3, 1); else - issue_del_ba(adapter, sta->hwaddr, tid, 37, initiator); + issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator); if (ret == _FAIL && sta->recvreorder_ctrl[tid].enable == _FALSE) sta->recvreorder_ctrl[tid].ampdu_size = ampdu_size_bak; @@ -10576,7 +10554,7 @@ static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct if (force || sta->htpriv.agg_enable_bitmap & BIT(tid)) { sta->htpriv.agg_enable_bitmap &= ~BIT(tid); sta->htpriv.candidate_tid_bitmap &= ~BIT(tid); - issue_del_ba(adapter, sta->hwaddr, tid, 37, initiator); + issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator); } #endif } @@ -10627,19 +10605,18 @@ unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr) unsigned int send_beacon(_adapter *padapter) { - u8 bxmitok = _FALSE; - int issue = 0; - int poll = 0; -#if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN) - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); -#endif - #ifdef CONFIG_PCI_HCI + #ifdef CONFIG_FW_HANDLE_TXBCN + u8 vap_id = padapter->vap_id; + + /* bypass TX BCN because vap_id is invalid*/ + if (vap_id == CONFIG_LIMITED_AP_NUM) + return _SUCCESS; + #endif + /* bypass TX BCN queue because op ch is switching/waiting */ if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) - #ifdef CONFIG_DFS_MASTER || IS_CH_WAITING(adapter_to_rfctl(padapter)) - #endif ) return _SUCCESS; @@ -10649,40 +10626,59 @@ unsigned int send_beacon(_adapter *padapter) /* 8192EE Port select for Beacon DL */ rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); + #ifdef CONFIG_FW_HANDLE_TXBCN + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id); + #endif issue_beacon(padapter, 0); -#ifdef RTL8814AE_SW_BCN - if (pHalData->bCorrectBCN != 0) + #ifdef CONFIG_FW_HANDLE_TXBCN + vap_id = 0xFF; + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id); + #endif + + #ifdef RTL8814AE_SW_BCN + if (GET_HAL_DATA(padapter)->bCorrectBCN != 0) RTW_INFO("%s, line%d, Warnning, pHalData->bCorrectBCN != 0\n", __func__, __LINE__); - pHalData->bCorrectBCN = 1; -#endif + GET_HAL_DATA(padapter)->bCorrectBCN = 1; + #endif return _SUCCESS; -#endif +#endif /*CONFIG_PCI_HCI*/ #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - u32 start = rtw_get_current_time(); + u8 bxmitok = _FALSE; + int issue = 0; + int poll = 0; + systime start = rtw_get_current_time(); + #ifdef CONFIG_FW_HANDLE_TXBCN + u8 vap_id = padapter->vap_id; + + /* bypass TX BCN because vap_id is invalid*/ + if (vap_id == CONFIG_LIMITED_AP_NUM) + return _SUCCESS; + #endif /* bypass TX BCN queue because op ch is switching/waiting */ if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) - #ifdef CONFIG_DFS_MASTER || IS_CH_WAITING(adapter_to_rfctl(padapter)) - #endif ) return _SUCCESS; -#if defined(CONFIG_USB_HCI) -#if defined(CONFIG_RTL8812A) + #if defined(CONFIG_USB_HCI) + #if defined(CONFIG_RTL8812A) if (IS_FULL_SPEED_USB(padapter)) { issue_beacon(padapter, 300); bxmitok = _TRUE; } else -#endif -#endif + #endif + #endif { rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); + #ifdef CONFIG_FW_HANDLE_TXBCN + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id); + #endif do { issue_beacon(padapter, 100); issue++; @@ -10693,6 +10689,10 @@ unsigned int send_beacon(_adapter *padapter) } while ((poll % 10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(padapter)); } while (bxmitok == _FALSE && (issue < 100) && !RTW_CANNOT_RUN(padapter)); + #ifdef CONFIG_FW_HANDLE_TXBCN + vap_id = 0xFF; + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_HEAD_SEL, &vap_id); + #endif } if (RTW_CANNOT_RUN(padapter)) return _FAIL; @@ -10700,6 +10700,9 @@ unsigned int send_beacon(_adapter *padapter) if (_FALSE == bxmitok) { RTW_INFO("%s fail! %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); + #ifdef CONFIG_BCN_RECOVERY + GET_HAL_DATA(padapter)->issue_bcn_fail++; + #endif /*CONFIG_BCN_RECOVERY*/ return _FAIL; } else { u32 passing_time = rtw_get_passing_time_ms(start); @@ -10709,12 +10712,13 @@ unsigned int send_beacon(_adapter *padapter) else if (0) RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); + #ifdef CONFIG_FW_CORRECT_BCN rtw_hal_fw_correct_bcn(padapter); - + #endif return _SUCCESS; } -#endif +#endif /*defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)*/ } @@ -10745,16 +10749,19 @@ BOOLEAN IsLegal5GChannel( u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid) { int i; - u32 len; + sint len; u8 *p; + u8 rf_path; u16 val16, subtype; u8 *pframe = precv_frame->u.hdr.rx_data; u32 packet_len = precv_frame->u.hdr.len; u8 ie_offset; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); if (len > MAX_IE_SZ) { @@ -10767,18 +10774,18 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI subtype = get_frame_sub_type(pframe); if (subtype == WIFI_BEACON) { - bssid->Reserved[0] = 1; + bssid->Reserved[0] = BSS_TYPE_BCN; ie_offset = _BEACON_IE_OFFSET_; } else { /* FIXME : more type */ if (subtype == WIFI_PROBERSP) { ie_offset = _PROBERSP_IE_OFFSET_; - bssid->Reserved[0] = 3; + bssid->Reserved[0] = BSS_TYPE_PROB_RSP; } else if (subtype == WIFI_PROBEREQ) { ie_offset = _PROBEREQ_IE_OFFSET_; - bssid->Reserved[0] = 2; + bssid->Reserved[0] = BSS_TYPE_PROB_REQ; } else { - bssid->Reserved[0] = 0; + bssid->Reserved[0] = BSS_TYPE_UNDEF; ie_offset = _FIXED_IE_LENGTH_; } } @@ -10791,9 +10798,19 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI /* get the signal strength */ /* bssid->Rssi = precv_frame->u.hdr.attrib.SignalStrength; */ /* 0-100 index. */ - bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.RecvSignalPower; /* in dBM.raw data */ - bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.SignalQuality;/* in percentage */ - bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.SignalStrength;/* in percentage */ + bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; /* in dBM.raw data */ + bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.signal_quality;/* in percentage */ + bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.signal_strength;/* in percentage */ + + /* get rx_snr */ + if (precv_frame->u.hdr.attrib.data_rate >= DESC_RATE11M) { + bssid->PhyInfo.is_cck_rate = 0; + for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) + bssid->PhyInfo.rx_snr[rf_path] = + precv_frame->u.hdr.attrib.phy_info.rx_snr[rf_path]; + } else + bssid->PhyInfo.is_cck_rate = 1; + #ifdef CONFIG_ANTENNA_DIVERSITY rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &(bssid->PhyInfo.Optimum_antenna), NULL); #endif @@ -10825,6 +10842,11 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); return _FAIL; } + if (rtw_validate_value(_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) { + rtw_absorb_ssid_ifneed(padapter, bssid, pframe); + RTW_DBG_DUMP("Invalidated Support Rate IE --", p, len+2); + return _FAIL; + } _rtw_memcpy(bssid->SupportedRates, (p + 2), len); i = len; } @@ -10835,6 +10857,11 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); return _FAIL; } + if (rtw_validate_value(_EXT_SUPPORTEDRATES_IE_, p+2, len) == _FALSE) { + rtw_absorb_ssid_ifneed(padapter, bssid, pframe); + RTW_DBG_DUMP("Invalidated EXT Support Rate IE --", p, len+2); + return _FAIL; + } _rtw_memcpy(bssid->SupportedRates + i, (p + 2), len); } @@ -10903,12 +10930,49 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid); - if (val16 & BIT(0)) { + if ((val16 & 0x03) == cap_ESS) { bssid->InfrastructureMode = Ndis802_11Infrastructure; _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN); - } else { + } else if ((val16 & 0x03) == cap_IBSS){ bssid->InfrastructureMode = Ndis802_11IBSS; _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); + } else if ((val16 & 0x03) == 0x00){ + u8 *mesh_id_ie, *mesh_conf_ie; + sint mesh_id_ie_len, mesh_conf_ie_len; + + mesh_id_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_ID, &mesh_id_ie_len, bssid->IELength - ie_offset); + mesh_conf_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_CONFIG, &mesh_conf_ie_len, bssid->IELength - ie_offset); + if (mesh_id_ie || mesh_conf_ie) { + if (!mesh_id_ie) { + RTW_INFO("cannot find Mesh ID for survey event\n"); + return _FAIL; + } + if (mesh_id_ie_len) { + if (mesh_id_ie_len > NDIS_802_11_LENGTH_SSID) { + RTW_INFO("Mesh ID too long (%d) for survey event\n", mesh_id_ie_len); + return _FAIL; + } + _rtw_memcpy(bssid->mesh_id.Ssid, (mesh_id_ie + 2), mesh_id_ie_len); + bssid->mesh_id.SsidLength = mesh_id_ie_len; + } else + bssid->mesh_id.SsidLength = 0; + + if (!mesh_conf_ie) { + RTW_INFO("cannot find Mesh config for survey event\n"); + return _FAIL; + } + if (mesh_conf_ie_len != 7) { + RTW_INFO("invalid Mesh conf IE len (%d) for survey event\n", mesh_conf_ie_len); + return _FAIL; + } + + bssid->InfrastructureMode = Ndis802_11_mesh; + _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); + } else { + /* default cases */ + bssid->InfrastructureMode = Ndis802_11IBSS; + _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); + } } if (val16 & BIT(4)) @@ -10955,6 +11019,14 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI if (bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter)) bssid->PhyInfo.SignalQuality = 101; +#ifdef CONFIG_RTW_80211K + p = rtw_get_ie(bssid->IEs + ie_offset, _EID_RRM_EN_CAP_IE_, &len, bssid->IELength - ie_offset); + if (p) + _rtw_memcpy(bssid->PhyInfo.rm_en_cap, (p + 2), *(p + 1)); + + /* save freerun counter */ + bssid->PhyInfo.free_cnt = precv_frame->u.hdr.attrib.free_cnt; +#endif return _SUCCESS; } @@ -11000,14 +11072,15 @@ void start_create_ibss(_adapter *padapter) /* issue beacon */ if (send_beacon(padapter) == _FAIL) { - report_join_res(padapter, -1); + report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE); pmlmeinfo->state = WIFI_FW_NULL_STATE; } else { rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED); join_type = 0; rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); - report_join_res(padapter, 1); + report_join_res(padapter, 1, WLAN_STATUS_SUCCESS); pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; rtw_indicate_connect(padapter); } @@ -11082,7 +11155,7 @@ void start_clnt_join(_adapter *padapter) if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE ) { - ie_offset = (scanned->network.Reserved[0] == 2 ? 0 : 12); + ie_offset = (scanned->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); if (rtw_get_p2p_ie(scanned->network.IEs + ie_offset, scanned->network.IELength - ie_offset, NULL, NULL)) has_p2p_ie = _TRUE; break; @@ -11106,23 +11179,8 @@ void start_clnt_join(_adapter *padapter) (REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout); #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - if (rtw_chk_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED)) { - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - ft_priv *pftpriv = &pmlmepriv->ftpriv; - - pmlmeinfo->state = WIFI_FW_AUTH_SUCCESS | WIFI_FW_STATION_STATE; - pftpriv->ft_event.ies = pftpriv->ft_action + sizeof(struct rtw_ieee80211_hdr_3addr) + 16; - pftpriv->ft_event.ies_len = pftpriv->ft_action_len - sizeof(struct rtw_ieee80211_hdr_3addr); - - /*Not support RIC*/ - pftpriv->ft_event.ric_ies = NULL; - pftpriv->ft_event.ric_ies_len = 0; - report_ft_event(padapter); - } else { - pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; - start_clnt_auth(padapter); - } + if (rtw_ft_roam(padapter)) { + rtw_ft_start_clnt_join(padapter); } else #endif { @@ -11139,7 +11197,7 @@ void start_clnt_join(_adapter *padapter) pmlmeinfo->state = WIFI_FW_ADHOC_STATE; - report_join_res(padapter, 1); + report_join_res(padapter, 1, WLAN_STATUS_SUCCESS); } else { /* RTW_INFO("marc: invalid cap:%x\n", caps); */ return; @@ -11164,8 +11222,8 @@ void start_clnt_auth(_adapter *padapter) pmlmeext->retry = 0; #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { - rtw_set_ft_status(padapter, RTW_FT_AUTHENTICATING_STA); + if (rtw_ft_roam(padapter)) { + rtw_ft_set_status(padapter, RTW_FT_AUTHENTICATING_STA); RTW_PRINT("start ft auth\n"); } else #endif @@ -11188,7 +11246,7 @@ void start_clnt_assoc(_adapter *padapter) pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE); #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) + if (rtw_ft_roam(padapter)) issue_reassocreq(padapter); else #endif @@ -11207,18 +11265,23 @@ unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsi RTW_INFO("%s\n", __FUNCTION__); +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_do_disconnect(padapter); +#endif if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL) pmlmeinfo->state = WIFI_FW_NULL_STATE; } else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) { - if (report_join_res(padapter, -2) != _FAIL) + if (report_join_res(padapter, -2, reason) != _FAIL) pmlmeinfo->state = WIFI_FW_NULL_STATE; } else RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(padapter)); #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && !rtw_chk_ft_status(padapter, RTW_FT_REQUESTED_STA)) - rtw_reset_ft_status(padapter); + rtw_ft_roam_status_reset(padapter); +#endif +#ifdef CONFIG_RTW_WNM + rtw_wnm_reset_btm_state(padapter); #endif } @@ -11228,6 +11291,7 @@ unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsi #ifdef CONFIG_80211D static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct registry_priv *pregistrypriv; struct mlme_ext_priv *pmlmeext; RT_CHANNEL_INFO *chplan_new; @@ -11244,7 +11308,7 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) u8 *ie, *p; u32 len; RT_CHANNEL_PLAN chplan_ap; - RT_CHANNEL_INFO chplan_sta[MAX_CHANNEL_NUM]; + RT_CHANNEL_INFO *chplan_sta = NULL; u8 country[4]; u8 fcn; /* first channel number */ u8 noc; /* number of channel */ @@ -11292,7 +11356,11 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) _RTW_INFO("}\n"); #endif - _rtw_memcpy(chplan_sta, pmlmeext->channel_set, sizeof(chplan_sta)); + chplan_sta = rtw_malloc(sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); + if (!chplan_sta) + goto done_update_chplan_from_ap; + + _rtw_memcpy(chplan_sta, rfctl->channel_set, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); #ifdef CONFIG_RTW_DEBUG i = 0; RTW_INFO("%s: STA channel plan {", __FUNCTION__); @@ -11303,8 +11371,8 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) _RTW_INFO("}\n"); #endif - _rtw_memset(pmlmeext->channel_set, 0, sizeof(pmlmeext->channel_set)); - chplan_new = pmlmeext->channel_set; + _rtw_memset(rfctl->channel_set, 0, sizeof(rfctl->channel_set)); + chplan_new = rfctl->channel_set; i = j = k = 0; if (pregistrypriv->wireless_mode & WIRELESS_11G) { @@ -11464,26 +11532,10 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) k++; } #endif - } - - /* If channel is used by AP, set channel scan type to active */ - channel = bssid->Configuration.DSConfig; - chplan_new = pmlmeext->channel_set; - i = 0; - while (i < MAX_CHANNEL_NUM && chplan_new[i].ChannelNum != 0) { - if (chplan_new[i].ChannelNum == channel) { - if (chplan_new[i].ScanType == SCAN_PASSIVE) { - /* 5G Bnad 2, 3 (DFS) doesn't change to active scan */ - if (rtw_is_dfs_ch(channel)) - break; - chplan_new[i].ScanType = SCAN_ACTIVE; - RTW_INFO("%s: change channel %d scan type from passive to active\n", - __FUNCTION__, channel); - } - break; - } - i++; +done_update_chplan_from_ap: + if (chplan_sta) + rtw_mfree(chplan_sta, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); } } #endif @@ -11505,6 +11557,7 @@ void report_survey_event(_adapter *padapter, union recv_frame *precv_frame) struct cmd_priv *pcmdpriv; /* u8 *pframe = precv_frame->u.hdr.rx_data; */ /* uint len = precv_frame->u.hdr.len; */ + RT_CHANNEL_INFO *chset = adapter_to_chset(padapter); int ch_set_idx = -1; if (!padapter) @@ -11551,14 +11604,21 @@ void report_survey_event(_adapter *padapter, union recv_frame *precv_frame) process_80211d(padapter, &psurvey_evt->bss); #endif -#ifdef CONFIG_DFS - ch_set_idx = rtw_chset_search_ch(pmlmeext->channel_set, psurvey_evt->bss.Configuration.DSConfig); + ch_set_idx = rtw_chset_search_ch(chset, psurvey_evt->bss.Configuration.DSConfig); if (ch_set_idx >= 0) { - if (psurvey_evt->bss.Ssid.SsidLength == 0 - || is_all_null(psurvey_evt->bss.Ssid.Ssid, psurvey_evt->bss.Ssid.SsidLength) == _TRUE) - pmlmeext->channel_set[ch_set_idx].hidden_bss_cnt++; + if (psurvey_evt->bss.InfrastructureMode == Ndis802_11Infrastructure) { + if (chset[ch_set_idx].ScanType == SCAN_PASSIVE + && !rtw_is_dfs_ch(psurvey_evt->bss.Configuration.DSConfig) + ) { + RTW_INFO("%s: change ch:%d to active\n", __func__, psurvey_evt->bss.Configuration.DSConfig); + chset[ch_set_idx].ScanType = SCAN_ACTIVE; + } + #ifdef CONFIG_DFS + if (hidden_ssid_ap(&psurvey_evt->bss)) + chset[ch_set_idx].hidden_bss_cnt++; + #endif + } } -#endif rtw_enqueue_cmd(pcmdpriv, pcmd_obj); @@ -11614,7 +11674,7 @@ void report_surveydone_event(_adapter *padapter) } -u32 report_join_res(_adapter *padapter, int res) +u32 report_join_res(_adapter *padapter, int aid_res, u16 status) { struct cmd_obj *pcmd_obj; u8 *pevtcmd; @@ -11653,12 +11713,12 @@ u32 report_join_res(_adapter *padapter, int res) pjoinbss_evt = (struct joinbss_event *)(pevtcmd + sizeof(struct C2HEvent_Header)); _rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); - pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = res; + pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = aid_res; - RTW_INFO("report_join_res(%d)\n", res); + RTW_INFO("report_join_res(%d, %u)\n", aid_res, status); - rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network); + rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network, status); ret = rtw_enqueue_cmd(pcmdpriv, pcmd_obj); @@ -11675,7 +11735,6 @@ void report_wmm_edca_update(_adapter *padapter) struct wmm_event *pwmm_event; struct C2HEvent_Header *pc2h_evt_hdr; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct cmd_priv *pcmdpriv = &padapter->cmdpriv; pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); @@ -11743,7 +11802,7 @@ u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned sh _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2); psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); if (psta) - mac_id = (int)psta->mac_id; + mac_id = (int)psta->cmn.mac_id; else mac_id = (-1); pdel_sta_evt->mac_id = mac_id; @@ -11879,9 +11938,9 @@ bool rtw_port_switch_chk(_adapter *adapter) } #endif /* CONFIG_WOWLAN */ - /* AP should use port0 for ctl frame's ack */ + /* AP/Mesh should use port0 for ctl frame's ack */ if ((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { - RTW_INFO("%s "ADPT_FMT" is AP/GO\n", __func__, ADPT_ARG(if_port1)); + RTW_INFO("%s "ADPT_FMT" is AP/GO/Mesh\n", __func__, ADPT_ARG(if_port1)); switch_needed = _TRUE; goto exit; } @@ -11957,6 +12016,10 @@ void update_sta_info(_adapter *padapter, struct sta_info *psta) psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap; _rtw_memcpy(&psta->htpriv.ht_cap, &pmlmeinfo->HT_caps, sizeof(struct rtw_ieee80211_ht_cap)); + #ifdef CONFIG_BEAMFORMING + psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap; + psta->cmn.bf_info.ht_beamform_cap = pmlmepriv->htpriv.beamform_cap; + #endif } else #endif /* CONFIG_80211N_HT */ { @@ -11978,7 +12041,7 @@ void update_sta_info(_adapter *padapter, struct sta_info *psta) psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ #endif /* CONFIG_80211N_HT */ - psta->bw_mode = pmlmeext->cur_bwmode; + psta->cmn.bw_mode = pmlmeext->cur_bwmode; /* QoS */ if (pmlmepriv->qospriv.qos_option) @@ -11986,8 +12049,15 @@ void update_sta_info(_adapter *padapter, struct sta_info *psta) #ifdef CONFIG_80211AC_VHT _rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv)); + if (psta->vhtpriv.vht_option) { + psta->cmn.ra_info.is_vht_enable = _TRUE; + #ifdef CONFIG_BEAMFORMING + psta->vhtpriv.beamform_cap = pmlmepriv->vhtpriv.beamform_cap; + psta->cmn.bf_info.vht_beamform_cap = pmlmepriv->vhtpriv.beamform_cap; + #endif /*CONFIG_BEAMFORMING*/ + } #endif /* CONFIG_80211AC_VHT */ - + psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta)); update_ldpc_stbc_cap(psta); _enter_critical_bh(&psta->lock, &irqL); @@ -12001,14 +12071,32 @@ static void rtw_mlmeext_disconnect(_adapter *padapter) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + u8 self_action = MLME_ACTION_UNKNOWN; u8 state_backup = (pmlmeinfo->state & 0x03); u8 ASIX_ID[] = {0x00, 0x0E, 0xC6}; - /* set_opmode_cmd(padapter, infra_client_with_mlme); */ + if (MLME_IS_AP(padapter)) + self_action = MLME_AP_STOPPED; + else if (MLME_IS_MESH(padapter)) + self_action = MLME_MESH_STOPPED; + else if (MLME_IS_STA(padapter)) + self_action = MLME_STA_DISCONNECTED; + else if (MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter)) + self_action = MLME_ADHOC_STOPPED; + else { + RTW_INFO("state:0x%x\n", MLME_STATE(padapter)); + rtw_warn_on(1); + } + /* set_opmode_cmd(padapter, infra_client_with_mlme); */ +#ifdef CONFIG_HW_P0_TSF_SYNC + if (self_action == MLME_STA_DISCONNECTED) + correct_TSF(padapter, self_action); +#endif rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr); + if (self_action == MLME_STA_DISCONNECTED) + rtw_hal_rcr_set_chk_bssid(padapter, self_action); /* set MSR to no link state->infra. mode */ Set_MSR(padapter, _HW_STATE_STATION_); @@ -12047,16 +12135,14 @@ static void rtw_mlmeext_disconnect(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_STOP_FCS_MODE, NULL); #endif -#ifdef CONFIG_DFS_MASTER - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) - rtw_dfs_master_status_apply(padapter, MLME_AP_STOPPED); - else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) - rtw_dfs_master_status_apply(padapter, MLME_STA_DISCONNECTED); -#endif - - { + if (!(MLME_IS_STA(padapter) && MLME_IS_OPCH_SW(padapter))) { + /* DFS and channel status no need to check here for STA under OPCH_SW */ u8 ch, bw, offset; + #ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(padapter, self_action, 0); + #endif + if (rtw_mi_get_ch_setting_union_no_self(padapter, &ch, &bw, &offset) != 0) { set_channel_bwmode(padapter, ch, offset, bw); rtw_mi_update_union_chan_inf(padapter, ch, offset, bw); @@ -12079,28 +12165,46 @@ static void rtw_mlmeext_disconnect(_adapter *padapter) padapter->tdlsinfo.ch_switch_prohibited = _FALSE; #endif /* CONFIG_TDLS */ +#ifdef CONFIG_WMMPS_STA + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + /* reset currently related uapsd setting when the connection has broken */ + pmlmepriv->qospriv.uapsd_max_sp_len = 0; + pmlmepriv->qospriv.uapsd_tid = 0; + pmlmepriv->qospriv.uapsd_tid_delivery_enabled = 0; + pmlmepriv->qospriv.uapsd_tid_trigger_enabled = 0; + pmlmepriv->qospriv.uapsd_ap_supported = 0; + } +#endif /* CONFIG_WMMPS_STA */ + } void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) { - struct sta_info *psta, *psta_bmc; + struct sta_info *psta; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); struct sta_priv *pstapriv = &padapter->stapriv; u8 join_type; -#ifdef CONFIG_ARP_KEEP_ALIVE struct mlme_priv *pmlmepriv = &padapter->mlmepriv; -#endif + +#ifndef CONFIG_IOCTL_CFG80211 struct security_priv *psecuritypriv = &padapter->securitypriv; +#endif + + if (pmlmepriv->wpa_phase == _TRUE) + pmlmepriv->wpa_phase = _FALSE; if (join_res < 0) { join_type = 1; rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr); + if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) + rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED); goto exit_mlmeext_joinbss_event_callback; } + #ifdef CONFIG_ARP_KEEP_ALIVE pmlmepriv->bGetGateway = 1; pmlmepriv->GetGatewayTryCnt = 0; @@ -12128,10 +12232,10 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) /* WMM, Update EDCA param */ WMMOnAssocRsp(padapter); - +#ifdef CONFIG_80211N_HT /* HT */ HTOnAssocRsp(padapter); - +#endif /* CONFIG_80211N_HT */ #ifdef CONFIG_80211AC_VHT /* VHT */ VHTOnAssocRsp(padapter); @@ -12139,14 +12243,8 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); if (psta) { /* only for infra. mode */ - /* RTW_INFO("set_sta_rate\n"); */ - psta->wireless_mode = pmlmeext->cur_wireless_mode; -#ifdef CONFIG_FW_MULTI_PORT_SUPPORT - rtw_hal_set_default_port_id_cmd(padapter, psta->mac_id); -#endif - /* set per sta rate after updating HT cap. */ set_sta_rate(padapter, psta); @@ -12154,7 +12252,7 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) /* wakeup macid after join bss successfully to ensure the subsequent data frames can be sent out normally */ - rtw_hal_macid_wakeup(padapter, psta->mac_id); + rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id); } #ifndef CONFIG_IOCTL_CFG80211 @@ -12169,8 +12267,10 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { + rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTED); + /* correcting TSF */ - correct_TSF(padapter, pmlmeext); + correct_TSF(padapter, MLME_STA_CONNECTED); /* set_link_timer(pmlmeext, DISCONNECT_TO); */ } @@ -12190,7 +12290,9 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) exit_mlmeext_joinbss_event_callback: rtw_join_done_chk_ch(padapter, join_res); - +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_join_done(padapter); +#endif RTW_INFO("=>%s - End to Connection without 4-way\n", __FUNCTION__); } @@ -12211,7 +12313,7 @@ void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta) /* update_TSF(pmlmeext, pframe, len); */ /* correcting TSF */ - correct_TSF(padapter, pmlmeext); + correct_TSF(padapter, MLME_ADHOC_STARTED); /* start beacon */ if (send_beacon(padapter) == _FAIL) @@ -12227,11 +12329,11 @@ void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta) /* update adhoc sta_info */ update_sta_info(padapter, psta); - rtw_hal_update_sta_rate_mask(padapter, psta); + rtw_hal_update_sta_ra_info(padapter, psta); /* ToDo: HT for Ad-hoc */ psta->wireless_mode = rtw_check_network_type(psta->bssrateset, psta->bssratelen, pmlmeext->cur_channel); - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); /* rate radaptive */ Update_RA_Entry(padapter, psta); @@ -12239,12 +12341,8 @@ void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta) void mlmeext_sta_del_event_callback(_adapter *padapter) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - if (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter)) rtw_mlmeext_disconnect(padapter); - } /**************************************************************************** @@ -12254,50 +12352,10 @@ Following are the functions for the timer handlers *****************************************************************************/ void _linked_info_dump(_adapter *padapter) { - int i; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - HAL_DATA_TYPE *HalData = GET_HAL_DATA(padapter); - int undecorated_smoothed_pwdb = 0; - if (padapter->bLinkInfoDump) { - - RTW_INFO("\n============["ADPT_FMT"] linked status check ===================\n", ADPT_ARG(padapter)); - - if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { - rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &undecorated_smoothed_pwdb); - - RTW_INFO("AP[" MAC_FMT "] - undecorated_smoothed_pwdb:%d\n", - MAC_ARG(padapter->mlmepriv.cur_network.network.MacAddress), undecorated_smoothed_pwdb); - } else if ((pmlmeinfo->state & 0x03) == _HW_STATE_AP_) { - _irqL irqL; - _list *phead, *plist; - - struct sta_info *psta = NULL; - struct sta_priv *pstapriv = &padapter->stapriv; - - _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); - phead = &pstapriv->asoc_list; - plist = get_next(phead); - while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); - plist = get_next(plist); - - RTW_INFO("STA[" MAC_FMT "]:undecorated_smoothed_pwdb:%d\n", - MAC_ARG(psta->hwaddr), psta->rssi_stat.undecorated_smoothed_pwdb); - } - _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - - } - - /*============ tx info ============ */ rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, RTW_DBGDUMP); - rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, RTW_DBGDUMP, _FALSE); - } - - } /******************************************************************** @@ -12327,9 +12385,9 @@ void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer) if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) { /* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */ if (!from_timer) - ret = issue_del_ba_ex(padapter, psta->hwaddr, i, 39, 0, 3, 1); + ret = issue_del_ba_ex(padapter, psta->cmn.mac_addr, i, 39, 0, 3, 1); else - issue_del_ba(padapter, psta->hwaddr, i, 39, 0); + issue_del_ba(padapter, psta->cmn.mac_addr, i, 39, 0); psta->recvreorder_ctrl[i].enable = _FALSE; if (ret != _FAIL) psta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID; @@ -12346,11 +12404,10 @@ void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer) u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta) { u8 ret = _FALSE; - int i = 0; +#ifdef DBG_EXPIRATION_CHK struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); -#ifdef DBG_EXPIRATION_CHK RTW_INFO(FUNC_ADPT_FMT" rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu" /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/ ", retry:%u\n" @@ -12366,7 +12423,7 @@ u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta) ); RTW_INFO(FUNC_ADPT_FMT" tx_pkts:%llu, link_count:%u\n", FUNC_ADPT_ARG(padapter) - , padapter->xmitpriv.tx_pkts + , sta_tx_pkts(psta) , pmlmeinfo->link_count ); #endif @@ -12381,12 +12438,6 @@ u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta) sta_update_last_rx_pkts(psta); - /* - record last rx data packets for every tid. - */ - for (i = 0; i < TID_NUM; i++) - psta->sta_stats.last_rx_data_qos_pkts[i] = psta->sta_stats.rx_data_qos_pkts[i]; - return ret; } @@ -12398,8 +12449,8 @@ u8 chk_adhoc_peer_is_alive(struct sta_info *psta) RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu" /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/ ", expire_to:%u\n" - , MAC_ARG(psta->hwaddr) - , psta->rssi_stat.undecorated_smoothed_pwdb + , MAC_ARG(psta->cmn.mac_addr) + , psta->cmn.rssi_stat.rssi , STA_RX_PKTS_DIFF_ARG(psta) , psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts , psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts @@ -12470,11 +12521,11 @@ void linked_status_chk_tdls(_adapter *padapter) if (psta->alive_count >= ALIVE_MIN) { if (chk_tdls_peer_sta_is_alive(padapter, psta) == _FALSE) { if (psta->alive_count < ALIVE_MAX) { - _rtw_memcpy(checkalive[num_checkalive].addr, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(checkalive[num_checkalive].addr, psta->cmn.mac_addr, ETH_ALEN); checkalive[num_checkalive].psta = psta; num_checkalive++; } else { - _rtw_memcpy(teardown[num_teardown].addr, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(teardown[num_teardown].addr, psta->cmn.mac_addr, ETH_ALEN); teardown[num_teardown].psta = psta; num_teardown++; } @@ -12523,7 +12574,6 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) { u32 i; struct sta_info *psta; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct sta_priv *pstapriv = &padapter->stapriv; @@ -12544,15 +12594,21 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) int rx_chk_limit; int link_count_limit; -#ifdef CONFIG_LAYER2_ROAMING +#if defined(CONFIG_RTW_REPEATER_SON) + rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_PROCESS); +#elif defined(CONFIG_LAYER2_ROAMING) if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) { RTW_INFO("signal_strength_data.avg_val = %d\n", precvpriv->signal_strength_data.avg_val); - if (precvpriv->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold) { + if ((precvpriv->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold) + && (rtw_get_passing_time_ms(pmlmepriv->last_roaming) >= pmlmepriv->roam_scan_int*2000)) { +#ifdef CONFIG_RTW_80211K + rtw_roam_nb_discover(padapter, _FALSE); +#endif pmlmepriv->need_to_roam = _TRUE; rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM); - } else { + pmlmepriv->last_roaming = rtw_get_current_time(); + } else pmlmepriv->need_to_roam = _FALSE; - } } #endif #ifdef CONFIG_MCC_MODE @@ -12565,7 +12621,7 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) return; #endif -#if defined(DBG_ROAMING_TEST) +#if defined(DBG_ROAMING_TEST) || defined(CONFIG_RTW_REPEATER_SON) rx_chk_limit = 1; #elif defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER) rx_chk_limit = 4; @@ -12580,7 +12636,7 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) pmlmepriv->bGetGateway = 0; else { _rtw_memset(pmlmepriv->gw_ip, 0, 4); - _rtw_memset(pmlmepriv->gw_mac_addr, 0, 6); + _rtw_memset(pmlmepriv->gw_mac_addr, 0, ETH_ALEN); } } #endif @@ -12624,44 +12680,53 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) if (chk_ap_is_alive(padapter, psta) == _FALSE) rx_chk = _FAIL; - if (pxmitpriv->last_tx_pkts == pxmitpriv->tx_pkts) + if (sta_last_tx_pkts(psta) == sta_tx_pkts(psta)) tx_chk = _FAIL; -#if defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER) - if (pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL) - #ifdef CONFIG_MCC_MODE - /* Driver don't know operation channel under MCC*/ - /* So driver don't do KEEP_ALIVE_CHECK */ - && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) - #endif +#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + if (!from_timer && pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL) ) { - u8 backup_ch = 0, backup_bw, backup_offset; - u8 union_ch = 0, union_bw, union_offset; - - if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) - || pmlmeext->cur_channel != union_ch) - goto bypass_active_keep_alive; - - /* switch to correct channel of current network before issue keep-alive frames */ - if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { - backup_ch = rtw_get_oper_ch(padapter); - backup_bw = rtw_get_oper_bw(padapter); - backup_offset = rtw_get_oper_choffset(padapter); - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + u8 backup_ch = 0, backup_bw = 0, backup_offset = 0; + u8 union_ch = 0, union_bw = 0, union_offset = 0; + u8 switch_channel_by_drv = _TRUE; + + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter)) { + /* driver doesn't switch channel under MCC */ + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + switch_channel_by_drv = _FALSE; + } +#endif + if (switch_channel_by_drv) { + if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) + || pmlmeext->cur_channel != union_ch) + goto bypass_active_keep_alive; + + /* switch to correct channel of current network before issue keep-alive frames */ + if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { + backup_ch = rtw_get_oper_ch(padapter); + backup_bw = rtw_get_oper_bw(padapter); + backup_offset = rtw_get_oper_choffset(padapter); + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + } } if (rx_chk != _SUCCESS) - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->hwaddr, 0, 0, 3, 1); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->cmn.mac_addr, 0, 0, 3, 1); if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) || rx_chk != _SUCCESS) { - tx_chk = issue_nulldata(padapter, psta->hwaddr, 0, 3, 1); + if (rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY)) + tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 1, 3, 1); + else + tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 3, 1); /* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */ if (tx_chk == _SUCCESS && !is_p2p_enable) rx_chk = _SUCCESS; } /* back to the original operation channel */ - if (backup_ch > 0) + if (backup_ch > 0 && switch_channel_by_drv) set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); bypass_active_keep_alive: @@ -12674,9 +12739,9 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) #ifdef DBG_EXPIRATION_CHK RTW_INFO("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry); #endif - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); - issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1)); } } @@ -12685,11 +12750,14 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) /* FW tx nulldata under MCC mode, we just check ap is alive */ && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) #endif /* CONFIG_MCC_MODE */ - ) { -#ifdef DBG_EXPIRATION_CHK + ) { + #ifdef DBG_EXPIRATION_CHK RTW_INFO("%s issue_nulldata(%d)\n", __FUNCTION__, from_timer ? 1 : 0); -#endif - tx_chk = issue_nulldata_in_interrupt(padapter, NULL, from_timer ? 1 : 0); + #endif + if (from_timer || rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY)) + tx_chk = issue_nulldata(padapter, NULL, 1, 0, 0); + else + tx_chk = issue_nulldata(padapter, NULL, 0, 1, 1); } } @@ -12708,7 +12776,7 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) if (tx_chk == _FAIL) pmlmeinfo->link_count %= (link_count_limit + 1); else { - pxmitpriv->last_tx_pkts = pxmitpriv->tx_pkts; + psta->sta_stats.last_tx_pkts = psta->sta_stats.tx_pkts; pmlmeinfo->link_count = 0; } @@ -12730,7 +12798,7 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); plist = get_next(plist); - if (is_broadcast_mac_addr(psta->hwaddr)) + if (is_broadcast_mac_addr(psta->cmn.mac_addr)) continue; if (chk_adhoc_peer_is_alive(psta) || !psta->expire_to) @@ -12753,23 +12821,20 @@ void linked_status_chk(_adapter *padapter, u8 from_timer) plist = get_next(plist); rtw_list_delete(&psta->list); RTW_INFO(FUNC_ADPT_FMT" ibss expire "MAC_FMT"\n" - , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->hwaddr)); - report_del_sta_event(padapter, psta->hwaddr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE); + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + report_del_sta_event(padapter, psta->cmn.mac_addr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE); } } } -void survey_timer_hdl(struct timer_list *t) +void survey_timer_hdl(void *ctx) { - struct mlme_ext_priv *pmlmeext = from_timer(pmlmeext, t, survey_timer); - _adapter *padapter = container_of(pmlmeext, _adapter, mlmeextpriv); + _adapter *padapter = (_adapter *)ctx; struct cmd_obj *cmd; struct sitesurvey_parm *psurveyPara; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#endif + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; if (mlmeext_scan_state(pmlmeext) > SCAN_DISABLE) { cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); @@ -12793,13 +12858,24 @@ void survey_timer_hdl(struct timer_list *t) return; } -void link_timer_hdl(struct timer_list *t) +#ifdef CONFIG_RTW_REPEATER_SON +/* 100ms pass, stop rson_scan */ +void rson_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + + rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_DISABLE); +} + +#endif + +void link_timer_hdl(void *ctx) { - struct mlme_ext_priv *pmlmeext = from_timer(pmlmeext, t, link_timer); - _adapter *padapter = container_of(pmlmeext, _adapter, mlmeextpriv); + _adapter *padapter = (_adapter *)ctx; /* static unsigned int rx_pkt = 0; */ /* static u64 tx_cnt = 0; */ /* struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); */ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); /* struct sta_priv *pstapriv = &padapter->stapriv; */ #ifdef CONFIG_RTW_80211R @@ -12811,17 +12887,28 @@ void link_timer_hdl(struct timer_list *t) if (rtw_sta_linking_test_force_fail()) RTW_INFO("rtw_sta_linking_test_force_fail\n"); + if (pmlmeext->join_abort && pmlmeinfo->state != WIFI_FW_NULL_STATE) { + RTW_INFO(FUNC_ADPT_FMT" join abort\n", FUNC_ADPT_ARG(padapter)); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + report_join_res(padapter, -4, WLAN_STATUS_UNSPECIFIED_FAILURE); + goto exit; + } + if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) { RTW_INFO("link_timer_hdl:no beacon while connecting\n"); pmlmeinfo->state = WIFI_FW_NULL_STATE; - report_join_res(padapter, -3); + report_join_res(padapter, -3, WLAN_STATUS_UNSPECIFIED_FAILURE); } else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE) { /* re-auth timer */ if (++pmlmeinfo->reauth_count > REAUTH_LIMIT) { /* if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto) */ /* { */ pmlmeinfo->state = 0; - report_join_res(padapter, -1); + if (pmlmeinfo->auth_status) { + report_join_res(padapter, -1, pmlmeinfo->auth_status); + pmlmeinfo->auth_status = 0; /* reset */ + } else + report_join_res(padapter, -1, WLAN_STATUS_UNSPECIFIED_FAILURE); return; /* } */ /* else */ @@ -12840,18 +12927,18 @@ void link_timer_hdl(struct timer_list *t) if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) { pmlmeinfo->state = WIFI_FW_NULL_STATE; #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + if (rtw_ft_roam(padapter)) { psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); if (psta) rtw_free_stainfo(padapter, psta); } #endif - report_join_res(padapter, -2); + report_join_res(padapter, -2, WLAN_STATUS_UNSPECIFIED_FAILURE); return; } #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) { + if (rtw_ft_roam(padapter)) { RTW_INFO("link_timer_hdl: reassoc timeout and try again\n"); issue_reassocreq(padapter); } else @@ -12864,12 +12951,13 @@ void link_timer_hdl(struct timer_list *t) set_link_timer(pmlmeext, REASSOC_TO); } +exit: return; } -void addba_timer_hdl(struct timer_list *t) +void addba_timer_hdl(void *ctx) { - struct sta_info *psta = from_timer(psta, t, addba_retry_timer); + struct sta_info *psta = (struct sta_info *)ctx; #ifdef CONFIG_80211N_HT struct ht_priv *phtpriv; @@ -12932,7 +13020,7 @@ void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short re psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); if (psta) - mac_id = (int)psta->mac_id; + mac_id = (int)psta->cmn.mac_id; else mac_id = (-1); @@ -12947,12 +13035,11 @@ void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short re void clnt_sa_query_timeout(_adapter *padapter) { + struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); - rtw_disassoc_cmd(padapter, 0, 0); - rtw_indicate_disconnect(padapter, 0, _FALSE); - rtw_free_assoc_resources(padapter, 1); - - RTW_INFO("SA query timeout client disconnect\n"); + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + receive_disconnect(padapter, get_my_bssid(&(mlmeinfo->network)), WLAN_REASON_SA_QUERY_TIMEOUT, _FALSE); } void sa_query_timer_hdl(void *ctx) @@ -12967,72 +13054,248 @@ void sa_query_timer_hdl(void *ctx) check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) clnt_sa_query_timeout(padapter); else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) - report_sta_timeout_event(padapter, psta->hwaddr, WLAN_REASON_PREV_AUTH_NOT_VALID); + report_sta_timeout_event(padapter, psta->cmn.mac_addr, WLAN_REASON_PREV_AUTH_NOT_VALID); } #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_RTW_80211R -void start_clnt_ft_action(_adapter *padapter, u8 *pTargetAddr) +void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + WLAN_BSSID_EX *pbss; - rtw_set_ft_status(padapter, RTW_FT_REQUESTING_STA); - issue_action_ft_request(padapter, pTargetAddr); - _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO); + if (rtw_ft_chk_status(padapter,RTW_FT_ASSOCIATED_STA) + && (pmlmepriv->ft_roam.ft_updated_bcn == _FALSE)) { + pbss = (WLAN_BSSID_EX*)rtw_malloc(sizeof(WLAN_BSSID_EX)); + if (pbss) { + if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) { + struct beacon_keys recv_beacon; + + update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE); + rtw_get_bcn_info(&(pmlmepriv->cur_network)); + + /* update bcn keys */ + if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) { + RTW_INFO("%s: beacon keys ready\n", __func__); + _rtw_memcpy(&pmlmepriv->cur_beacon_keys, + &recv_beacon, sizeof(recv_beacon)); + } else { + RTW_ERR("%s: get beacon keys failed\n", __func__); + _rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon)); + } + #ifdef CONFIG_BCN_CNT_CONFIRM_HDL + pmlmepriv->new_beacon_cnts = 0; + #endif + } + rtw_mfree((u8*)pbss, sizeof(WLAN_BSSID_EX)); + } + + /* check the vendor of the assoc AP */ + pmlmeinfo->assoc_AP_vendor = + check_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr), + (len - sizeof(struct rtw_ieee80211_hdr_3addr))); + + /* update TSF Value */ + update_TSF(pmlmeext, pframe, len); + pmlmeext->bcn_cnt = 0; + pmlmeext->last_bcn_cnt = 0; + pmlmepriv->ft_roam.ft_updated_bcn = _TRUE; + } } -void ft_link_timer_hdl(void *ctx) +void rtw_ft_start_clnt_join(_adapter *padapter) { - _adapter *padapter = (_adapter *)ctx; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - ft_priv *pftpriv = &pmlmepriv->ftpriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam); + + if (rtw_ft_otd_roam(padapter)) { + pmlmeinfo->state = WIFI_FW_AUTH_SUCCESS | WIFI_FW_STATION_STATE; + pft_roam->ft_event.ies = + (pft_roam->ft_action + sizeof(struct rtw_ieee80211_hdr_3addr) + 16); + pft_roam->ft_event.ies_len = + (pft_roam->ft_action_len - sizeof(struct rtw_ieee80211_hdr_3addr)); + + /*Not support RIC*/ + pft_roam->ft_event.ric_ies = NULL; + pft_roam->ft_event.ric_ies_len = 0; + rtw_ft_report_evt(padapter); + return; + } - if (rtw_chk_ft_status(padapter, RTW_FT_REQUESTING_STA)) { - if (pftpriv->ft_req_retry_cnt < FT_ACTION_REQ_LIMIT) { - pftpriv->ft_req_retry_cnt++; - issue_action_ft_request(padapter, (u8 *)pmlmepriv->roam_network->network.MacAddress); - _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO); - } else { - pftpriv->ft_req_retry_cnt = 0; + pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; + start_clnt_auth(padapter); +} - if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) - rtw_set_ft_status(padapter, RTW_FT_ASSOCIATED_STA); - else - rtw_reset_ft_status(padapter); - } +u8 rtw_ft_update_rsnie( + _adapter *padapter, u8 bwrite, + struct pkt_attrib *pattrib, u8 **pframe) +{ + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + u8 *pie; + u32 len; + + pie = rtw_get_ie(pft_roam->updated_ft_ies, EID_WPA2, &len, + pft_roam->updated_ft_ies_len); + + if (!bwrite) + return (pie)?_SUCCESS:_FAIL; + + if (pie) { + *pframe = rtw_set_ie(((u8 *)*pframe), EID_WPA2, len, + pie+2, &(pattrib->pktlen)); + } else + return _FAIL; + + return _SUCCESS; +} + +static u8 rtw_ft_update_mdie( + _adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe) +{ + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + u8 *pie, mdie[3]; + u32 len = 3; + + if (rtw_ft_roam(padapter)) { + if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _MDIE_, + &len, pft_roam->updated_ft_ies_len))) { + pie = (pie + 2); /* ignore md-id & length */ + } else + return _FAIL; + } else { + *((u16 *)&mdie[0]) = pft_roam->mdid; + mdie[2] = pft_roam->ft_cap; + pie = &mdie[0]; } + + *pframe = rtw_set_ie(((u8 *)*pframe), _MDIE_, len , pie, &(pattrib->pktlen)); + return _SUCCESS; } -void ft_roam_timer_hdl(void *ctx) +static u8 rtw_ft_update_ftie( + _adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe) { - _adapter *padapter = (_adapter *)ctx; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + u8 *pie; + u32 len; + + if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _FTIE_, &len, + pft_roam->updated_ft_ies_len)) != NULL) { + *pframe = rtw_set_ie(*pframe, _FTIE_, len , + (pie+2), &(pattrib->pktlen)); + } else + return _FAIL; - receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress - , WLAN_REASON_ACTIVE_ROAM, _FALSE); + return _SUCCESS; +} + +void rtw_ft_build_auth_req_ies(_adapter *padapter, + struct pkt_attrib *pattrib, u8 **pframe) +{ + u8 ftie_append = _TRUE; + + if (!pattrib || !(*pframe)) + return; + + if (!rtw_ft_roam(padapter)) + return; + + ftie_append = rtw_ft_update_rsnie(padapter, _TRUE, pattrib, pframe); + rtw_ft_update_mdie(padapter, pattrib, pframe); + if (ftie_append) + rtw_ft_update_ftie(padapter, pattrib, pframe); +} + +void rtw_ft_build_assoc_req_ies(_adapter *padapter, + u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe) +{ + if (!pattrib || !(*pframe)) + return; + + if (rtw_ft_chk_flags(padapter, RTW_FT_PEER_EN)) + rtw_ft_update_mdie(padapter, pattrib, pframe); + + if ((!is_reassoc) || (!rtw_ft_roam(padapter))) + return; + + if (rtw_ft_update_rsnie(padapter, _FALSE, pattrib, pframe)) + rtw_ft_update_ftie(padapter, pattrib, pframe); +} + +u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len) +{ + u8 ret = _SUCCESS; + u8 target_ap_addr[ETH_ALEN] = {0}; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam); + + if (!rtw_ft_roam(padapter)) + return _FAIL; + + /*rtw_ft_report_reassoc_evt already, + * and waiting for cfg80211_rtw_update_ft_ies */ + if (rtw_ft_authed_sta(padapter)) + return ret; + + if (!pframe || !len) + return _FAIL; + + rtw_buf_update(&pmlmepriv->auth_rsp, + &pmlmepriv->auth_rsp_len, pframe, len); + pft_roam->ft_event.ies = + (pmlmepriv->auth_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6); + pft_roam->ft_event.ies_len = + (pmlmepriv->auth_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6); + + /*Not support RIC*/ + pft_roam->ft_event.ric_ies = NULL; + pft_roam->ft_event.ric_ies_len = 0; + _rtw_memcpy(target_ap_addr, pmlmepriv->assoc_bssid, ETH_ALEN); + rtw_ft_report_reassoc_evt(padapter, target_ap_addr); + + return ret; +} + +static void rtw_ft_start_clnt_action(_adapter *padapter, u8 *pTargetAddr) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + rtw_ft_set_status(padapter, RTW_FT_REQUESTING_STA); + rtw_ft_issue_action_req(padapter, pTargetAddr); + _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO); +} + +void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (rtw_ft_otd_roam(padapter)) { + rtw_ft_start_clnt_action(padapter, pTargetAddr); + } else { + /*wait a little time to retrieve packets buffered in the current ap while scan*/ + _set_timer(&pmlmeext->ft_roam_timer, 30); + } } -void issue_action_ft_request(_adapter *padapter, u8 *pTargetAddr) +void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr) { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct xmit_frame *pmgntframe = NULL; - struct rtw_ieee80211_hdr *pwlanhdr = NULL; - struct pkt_attrib *pattrib = NULL; - ft_priv *pftpriv = NULL; - u8 *pframe = NULL; + struct xmit_frame *pmgntframe; + struct rtw_ieee80211_hdr *pwlanhdr; + struct pkt_attrib *pattrib; + u8 *pframe; u8 category = RTW_WLAN_CATEGORY_FT; - u8 action = RTW_WLAN_ACTION_FT_REQUEST; - u8 is_ft_roaming_with_rsn_ie = _TRUE; - u8 *pie = NULL; - u16 *fctrl = NULL; - u32 ft_ie_len = 0; + u8 action = RTW_WLAN_ACTION_FT_REQ; pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) @@ -13044,9 +13307,7 @@ void issue_action_ft_request(_adapter *padapter, u8 *pTargetAddr) pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; + pwlanhdr->frame_ctl = 0; _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); @@ -13070,45 +13331,34 @@ void issue_action_ft_request(_adapter *padapter, u8 *pTargetAddr) pframe += ETH_ALEN; pattrib->pktlen += ETH_ALEN; - pftpriv = &pmlmepriv->ftpriv; - pie = rtw_get_ie(pftpriv->updated_ft_ies, EID_WPA2, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie) - pframe = rtw_set_ie(pframe, EID_WPA2, ft_ie_len, pie+2, &(pattrib->pktlen)); - else - is_ft_roaming_with_rsn_ie = _FALSE; - - pie = rtw_get_ie(pftpriv->updated_ft_ies, _MDIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie) - pframe = rtw_set_ie(pframe, _MDIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); - - pie = rtw_get_ie(pftpriv->updated_ft_ies, _FTIE_, &ft_ie_len, pftpriv->updated_ft_ies_len); - if (pie && is_ft_roaming_with_rsn_ie) - pframe = rtw_set_ie(pframe, _FTIE_, ft_ie_len , pie+2, &(pattrib->pktlen)); + rtw_ft_update_mdie(padapter, pattrib, &pframe); + if (rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe)) + rtw_ft_update_ftie(padapter, pattrib, &pframe); pattrib->last_txcmdsz = pattrib->pktlen; dump_mgntframe(padapter, pmgntframe); } -void report_ft_event(_adapter *padapter) +void rtw_ft_report_evt(_adapter *padapter) { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - ft_priv *pftpriv = &pmlmepriv->ftpriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network); struct cfg80211_ft_event_params ft_evt_parms; _irqL irqL; _rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms)); - rtw_update_ft_stainfo(padapter, pnetwork); + rtw_ft_update_stainfo(padapter, pnetwork); if (!pnetwork) goto err_2; - ft_evt_parms.ies_len = pftpriv->ft_event.ies_len; + ft_evt_parms.ies_len = pft_roam->ft_event.ies_len; ft_evt_parms.ies = rtw_zmalloc(ft_evt_parms.ies_len); if (ft_evt_parms.ies) - _rtw_memcpy((void *)ft_evt_parms.ies, pftpriv->ft_event.ies, ft_evt_parms.ies_len); + _rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len); else goto err_2; @@ -13118,31 +13368,28 @@ void report_ft_event(_adapter *padapter) else goto err_1; - ft_evt_parms.ric_ies = pftpriv->ft_event.ric_ies; - ft_evt_parms.ric_ies_len = pftpriv->ft_event.ric_ies_len; - - _enter_critical_bh(&pmlmepriv->lock, &irqL); - rtw_set_ft_status(padapter, RTW_FT_AUTHENTICATED_STA); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies; + ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len; + rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL); rtw_cfg80211_ft_event(padapter, &ft_evt_parms); - RTW_INFO("FT: report_ft_event\n"); - rtw_mfree((u8 *)pftpriv->ft_event.target_ap, ETH_ALEN); + RTW_INFO("FT: rtw_ft_report_evt\n"); + rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN); err_1: rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len); err_2: return; } -void report_ft_reassoc_event(_adapter *padapter, u8 *pMacAddr) +void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - struct cmd_obj *pcmd_obj = NULL; - struct stassoc_event *passoc_sta_evt = NULL; - struct C2HEvent_Header *pc2h_evt_hdr = NULL; - u8 *pevtcmd = NULL; - u32 cmdsz = 0; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct cmd_obj *pcmd_obj = NULL; + struct stassoc_event *passoc_sta_evt = NULL; + struct C2HEvent_Header *pc2h_evt_hdr = NULL; + u8 *pevtcmd = NULL; + u32 cmdsz = 0; pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); if (pcmd_obj == NULL) @@ -13171,6 +13418,50 @@ void report_ft_reassoc_event(_adapter *padapter, u8 *pMacAddr) _rtw_memcpy((unsigned char *)(&(passoc_sta_evt->macaddr)), pMacAddr, ETH_ALEN); rtw_enqueue_cmd(pcmdpriv, pcmd_obj); } + +void rtw_ft_link_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam); + + if (rtw_ft_chk_status(padapter, RTW_FT_REQUESTING_STA)) { + if (pft_roam->ft_req_retry_cnt < RTW_FT_ACTION_REQ_LMT) { + pft_roam->ft_req_retry_cnt++; + rtw_ft_issue_action_req(padapter, (u8 *)pmlmepriv->roam_network->network.MacAddress); + _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO); + } else { + pft_roam->ft_req_retry_cnt = 0; + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) + rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA); + else + rtw_ft_reset_status(padapter); + } + } +} + +void rtw_ft_roam_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress + , WLAN_REASON_ACTIVE_ROAM, _FALSE); +} + +void rtw_ft_roam_status_reset(_adapter *padapter) +{ + struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam); + + if ((rtw_to_roam(padapter) > 0) && + (!rtw_ft_chk_status(padapter, RTW_FT_REQUESTED_STA))) { + rtw_ft_reset_status(padapter); + } + + padapter->mlmepriv.ft_roam.ft_updated_bcn = _FALSE; +} #endif u8 NULL_hdl(_adapter *padapter, u8 *pbuf) @@ -13179,13 +13470,47 @@ u8 NULL_hdl(_adapter *padapter, u8 *pbuf) } #ifdef CONFIG_AUTO_AP_MODE +void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos) +{ + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_info *psta = precv_frame->u.hdr.psta; + struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos; + + RTW_INFO("eth rx: got eth_type=0x%x\n", ntohs(ehdr->h_proto)); + + if (psta && psta->isrc && psta->pid > 0) { + u16 rx_pid; + + rx_pid = *(u16 *)(ehdr_pos + ETH_HLEN); + + RTW_INFO("eth rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n", + rx_pid, MAC_ARG(psta->cmn.mac_addr), psta->pid); + + if (rx_pid == psta->pid) { + int i; + u16 len = *(u16 *)(ehdr_pos + ETH_HLEN + 2); + /* u16 ctrl_type = *(u16 *)(ehdr_pos + ETH_HLEN + 4); */ + + /* RTW_INFO("eth, RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); */ + RTW_INFO("eth, RC: len=0x%x\n", len); + + for (i = 0; i < len; i++) + RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 4 + i)); + /* RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 6 + i)); */ + + RTW_INFO("eth, RC-end\n"); + } + } + +} + void rtw_start_auto_ap(_adapter *adapter) { RTW_INFO("%s\n", __FUNCTION__); rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11APMode); - rtw_setopmode_cmd(adapter, Ndis802_11APMode, _TRUE); + rtw_setopmode_cmd(adapter, Ndis802_11APMode, RTW_CMDF_WAIT_ACK); } static int rtw_auto_ap_start_beacon(_adapter *adapter) @@ -13280,12 +13605,11 @@ u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf; - if (psetop->mode == Ndis802_11APMode) { + if (psetop->mode == Ndis802_11APMode + || psetop->mode == Ndis802_11_mesh + ) { pmlmeinfo->state = WIFI_FW_AP_STATE; type = _HW_STATE_AP_; -#ifdef CONFIG_NATIVEAP_MLME - /* start_ap_mode(padapter); */ -#endif } else if (psetop->mode == Ndis802_11Infrastructure) { pmlmeinfo->state &= ~(BIT(0) | BIT(1)); /* clear state */ pmlmeinfo->state |= WIFI_FW_STATION_STATE;/* set to STATION_STATE */ @@ -13323,8 +13647,10 @@ u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) } #ifdef CONFIG_BT_COEXIST - if (psetop->mode == Ndis802_11APMode || - psetop->mode == Ndis802_11Monitor) { + if (psetop->mode == Ndis802_11APMode + || psetop->mode == Ndis802_11_mesh + || psetop->mode == Ndis802_11Monitor + ) { /* Do this after port switch to */ /* prevent from downloading rsvd page to wrong port */ rtw_btcoex_MediaStatusNotify(padapter, 1); /* connect */ @@ -13346,7 +13672,9 @@ u8 createbss_hdl(_adapter *padapter, u8 *pbuf) /* u8 initialgain; */ #ifdef CONFIG_AP_MODE - if (pmlmeinfo->state == WIFI_FW_AP_STATE) { + if ((parm->req_ch == 0 && pmlmeinfo->state == WIFI_FW_AP_STATE) + || parm->req_ch != 0 + ) { start_bss_network(padapter, parm); goto exit; } @@ -13367,14 +13695,6 @@ u8 createbss_hdl(_adapter *padapter, u8 *pbuf) pmlmeinfo->agg_enable_bitmap = 0; pmlmeinfo->candidate_tid_bitmap = 0; - /* config the initial gain under linking, need to write the BB registers */ - /* initialgain = 0x1E; */ - /*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/ - - /* disable dynamic functions, such as high power, DIG */ - rtw_phydm_ability_backup(padapter); - rtw_phydm_func_disable_all(padapter); - /* cancel link timer */ _cancel_timer_ex(&pmlmeext->link_timer); @@ -13408,7 +13728,6 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) { u8 join_type; PNDIS_802_11_VARIABLE_IEs pIE; - struct registry_priv *pregpriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); @@ -13438,6 +13757,8 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); + if (pmlmeinfo->state & WIFI_FW_STATION_STATE) + rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_DISCONNECTED); } #ifdef CONFIG_ANTENNA_DIVERSITY @@ -13460,7 +13781,10 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) pmlmeinfo->bwmode_updated = _FALSE; /* pmlmeinfo->assoc_AP_vendor = HT_IOT_PEER_MAX; */ pmlmeinfo->VHT_enable = 0; - +#ifdef ROKU_PRIVATE + pmlmeinfo->ht_vht_received = 0; + _rtw_memset(pmlmeinfo->SupportedRates_infra_ap, 0, NDIS_802_11_LENGTH_RATES_EX); +#endif /* ROKU_PRIVATE */ _rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength; @@ -13468,7 +13792,7 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) return H2C_PARAMETERS_ERROR; if (pnetwork->IELength < 2) { - report_join_res(padapter, (-4)); + report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE); return H2C_SUCCESS; } _rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength); @@ -13514,7 +13838,7 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) } rtw_bss_get_chbw(pnetwork - , &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset); + , &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset, 1, 1); rtw_adjust_chbw(padapter, pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset); @@ -13549,7 +13873,7 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) /* check channel, bandwidth, offset and switch */ if (rtw_chk_start_clnt_join(padapter, &u_ch, &u_bw, &u_offset) == _FAIL) { - report_join_res(padapter, (-4)); + report_join_res(padapter, (-4), WLAN_STATUS_UNSPECIFIED_FAILURE); return H2C_SUCCESS; } @@ -13561,8 +13885,14 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) /*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); + if (MLME_IS_STA(padapter)) + rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING); + else + rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED); + join_type = 0; rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + doiqk = _TRUE; rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); @@ -13583,34 +13913,35 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf) { +#ifdef CONFIG_DFS + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); +#endif struct disconnect_parm *param = (struct disconnect_parm *)pbuf; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); u8 val8; - if (is_client_associated_to_ap(padapter)) { -#ifdef CONFIG_DFS - if (padapter->mlmepriv.handle_dfs == _FALSE) -#endif /* CONFIG_DFS */ -#ifdef CONFIG_PLATFORM_ROCKCHIPS - /* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */ - issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); -#else - issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms / 100, 100); -#endif /* CONFIG_PLATFORM_ROCKCHIPS */ + if (is_client_associated_to_ap(padapter) + #ifdef CONFIG_DFS + && !IS_RADAR_DETECTED(rfctl) && !rfctl->csa_ch + #endif + ) { + #ifdef CONFIG_PLATFORM_ROCKCHIPS + /* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */ + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); + #else + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms / 100, 100); + #endif /* CONFIG_PLATFORM_ROCKCHIPS */ } -#ifdef CONFIG_DFS - if (padapter->mlmepriv.handle_dfs == _TRUE) - padapter->mlmepriv.handle_dfs = _FALSE; -#endif /* CONFIG_DFS */ - +#ifndef CONFIG_SUPPORT_MULTI_BCN if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { /* Stop BCN */ val8 = 0; rtw_hal_set_hwreg(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8)); } +#endif rtw_mlmeext_disconnect(padapter); @@ -13647,7 +13978,6 @@ const char *scan_state_str(u8 state) static bool scan_abort_hdl(_adapter *adapter) { struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct ss_res *ss = &pmlmeext->sitesurvey_res; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &adapter->wdinfo; @@ -13771,24 +14101,89 @@ u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_nu } } - _rtw_memset(&ch[k], 0, sizeof(struct rtw_ieee80211_channel)); + _rtw_memset(&ch[k], 0, sizeof(struct rtw_ieee80211_channel)); + + ret_num = k; + mlmeext->last_scan_time = rtw_get_current_time(); + } + +exit: + return ret_num; +} + +#ifdef CONFIG_SCAN_BACKOP +u8 rtw_scan_backop_decision(_adapter *adapter) +{ + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct mi_state mstate; + u8 backop_flags = 0; + + rtw_mi_status(adapter, &mstate); + + if ((MSTATE_STA_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN)) + || (MSTATE_STA_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(mlmeext, SS_BACKOP_EN_NL))) + backop_flags |= mlmeext_scan_backop_flags_sta(mlmeext); + +#ifdef CONFIG_AP_MODE + if ((MSTATE_AP_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN)) + || (MSTATE_AP_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(mlmeext, SS_BACKOP_EN_NL))) + backop_flags |= mlmeext_scan_backop_flags_ap(mlmeext); +#endif + +#ifdef CONFIG_RTW_MESH + if ((MSTATE_MESH_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN)) + || (MSTATE_MESH_NUM(&mstate) && mlmeext_chk_scan_backop_flags_mesh(mlmeext, SS_BACKOP_EN_NL))) + backop_flags |= mlmeext_scan_backop_flags_mesh(mlmeext); +#endif + + return backop_flags; +} +#endif + +#define SCANNING_TIMEOUT_EX 2000 +u32 rtw_scan_timeout_decision(_adapter *padapter) +{ + u32 back_op_times= 0; + u8 max_chan_num; + u16 scan_ms; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct ss_res *ss = &pmlmeext->sitesurvey_res; + + if (is_supported_5g(padapter->registrypriv.wireless_mode) + && IsSupported24G(padapter->registrypriv.wireless_mode)) + max_chan_num = MAX_CHANNEL_NUM;/* dual band */ + else + max_chan_num = MAX_CHANNEL_NUM_2G;/*single band*/ - ret_num = k; - mlmeext->last_scan_time = rtw_get_current_time(); - } + #ifdef CONFIG_SCAN_BACKOP + if (rtw_scan_backop_decision(padapter)) + back_op_times = (max_chan_num / ss->scan_cnt_max) * ss->backop_ms; + #endif -exit: - return ret_num; + if (ss->duration) + scan_ms = ss->duration; + else + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter)) + scan_ms = rtw_acs_get_adv_st(padapter); + else + #endif /*CONFIG_RTW_ACS*/ + scan_ms = ss->scan_ch_ms; + + ss->scan_timeout_ms = (scan_ms * max_chan_num) + back_op_times + SCANNING_TIMEOUT_EX; + #ifdef DBG_SITESURVEY + RTW_INFO("%s , scan_timeout_ms = %d (ms)\n", __func__, ss->scan_timeout_ms); + #endif /*DBG_SITESURVEY*/ + return ss->scan_timeout_ms; } static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out, u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num) { int i, j; - int scan_ch_num = 0; int set_idx; u8 chan; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); /* clear first */ _rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel) * out_num); @@ -13805,7 +14200,7 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel if (rtw_mlme_band_check(padapter, in[i].hw_value) == _FALSE) continue; - set_idx = rtw_chset_search_ch(pmlmeext->channel_set, in[i].hw_value); + set_idx = rtw_chset_search_ch(rfctl->channel_set, in[i].hw_value); if (set_idx >= 0) { if (j >= out_num) { RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n", @@ -13815,7 +14210,7 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel _rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel)); - if (pmlmeext->channel_set[set_idx].ScanType == SCAN_PASSIVE) + if (rfctl->channel_set[set_idx].ScanType == SCAN_PASSIVE) out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; j++; @@ -13826,8 +14221,8 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel /* if out is empty, use channel_set as default */ if (j == 0) { - for (i = 0; i < pmlmeext->max_chan_nums; i++) { - chan = pmlmeext->channel_set[i].ChannelNum; + for (i = 0; i < rfctl->max_chan_nums; i++) { + chan = rfctl->channel_set[i].ChannelNum; if (rtw_mlme_band_check(padapter, chan) == _TRUE) { if (rtw_mlme_ignore_chan(padapter, chan) == _TRUE) continue; @@ -13843,7 +14238,7 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel out[j].hw_value = chan; - if (pmlmeext->channel_set[i].ScanType == SCAN_PASSIVE) + if (rfctl->channel_set[i].ScanType == SCAN_PASSIVE) out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; j++; @@ -13860,6 +14255,7 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm) { struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res; + RT_CHANNEL_INFO *chset = adapter_to_chset(adapter); int i; ss->bss_cnt = 0; @@ -13875,7 +14271,6 @@ static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm #if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) ss->is_sw_antdiv_bl_scan = 0; #endif - ss->ssid_num = 0; for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { if (parm->ssid[i].SsidLength) { @@ -13893,10 +14288,15 @@ static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm #ifdef CONFIG_DFS for (i = 0; i < MAX_CHANNEL_NUM; i++) - adapter->mlmeextpriv.channel_set[i].hidden_bss_cnt = 0; + chset[i].hidden_bss_cnt = 0; #endif + ss->bw = parm->bw; + ss->igi = parm->igi; + ss->token = parm->token; + ss->duration = parm->duration; ss->scan_mode = parm->scan_mode; + ss->token = parm->token; } static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *type) @@ -13905,12 +14305,15 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE * u8 scan_ch = 0; RT_SCAN_TYPE scan_type = SCAN_PASSIVE; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; struct ss_res *ss = &pmlmeext->sitesurvey_res; - + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + int ch_set_idx; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &padapter->wdinfo; #endif +#ifdef CONFIG_SCAN_BACKOP + u8 backop_flags = 0; +#endif /* handle scan abort request */ scan_abort_hdl(padapter); @@ -13927,12 +14330,10 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE * * Commented by Albert 2011/06/03 * The driver is in the find phase, it should go through the social channel. */ - int ch_set_idx; - scan_ch = pwdinfo->social_chan[ss->channel_idx]; - ch_set_idx = rtw_chset_search_ch(pmlmeext->channel_set, scan_ch); + ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scan_ch); if (ch_set_idx >= 0) - scan_type = pmlmeext->channel_set[ch_set_idx].ScanType; + scan_type = rfctl->channel_set[ch_set_idx].ScanType; else scan_type = SCAN_ACTIVE; } else @@ -13940,56 +14341,66 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE * { struct rtw_ieee80211_channel *ch; -#ifdef CONFIG_DFS - if (ss->channel_idx != 0 && ss->dfs_ch_ssid_scan == 0 - && pmlmeext->sitesurvey_res.ssid_num - && rtw_is_dfs_ch(ss->ch[ss->channel_idx - 1].hw_value) - ) { - int ch_set_idx; + #ifdef CONFIG_SCAN_BACKOP + backop_flags = rtw_scan_backop_decision(padapter); + #endif - ch_set_idx = rtw_chset_search_ch(pmlmeext->channel_set, ss->ch[ss->channel_idx - 1].hw_value); - if (ch_set_idx != -1 && pmlmeext->channel_set[ch_set_idx].hidden_bss_cnt) { - ss->channel_idx--; - ss->dfs_ch_ssid_scan = 1; - } - } else - ss->dfs_ch_ssid_scan = 0; +#ifdef CONFIG_DFS + #ifdef CONFIG_SCAN_BACKOP + if (!(backop_flags && ss->scan_cnt >= ss->scan_cnt_max)) + #endif + { + #ifdef CONFIG_RTW_WIFI_HAL + if (adapter_to_dvobj(padapter)->nodfs) { + while ( ss->channel_idx < ss->ch_num && rtw_is_dfs_ch(ss->ch[ss->channel_idx].hw_value)) + ss->channel_idx++; + } else + #endif + if (ss->channel_idx != 0 && ss->dfs_ch_ssid_scan == 0 + && pmlmeext->sitesurvey_res.ssid_num + && rtw_is_dfs_ch(ss->ch[ss->channel_idx - 1].hw_value) + ) { + ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, ss->ch[ss->channel_idx - 1].hw_value); + if (ch_set_idx != -1 && rfctl->channel_set[ch_set_idx].hidden_bss_cnt + && (!IS_DFS_SLAVE_WITH_RD(rfctl) + || rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)) + || !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx])) + ) { + ss->channel_idx--; + ss->dfs_ch_ssid_scan = 1; + } + } else + ss->dfs_ch_ssid_scan = 0; + } #endif /* CONFIG_DFS */ if (ss->channel_idx < ss->ch_num) { ch = &ss->ch[ss->channel_idx]; scan_ch = ch->hw_value; - scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE; + + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(padapter) && rtw_is_acs_passiv_scan(padapter)) + scan_type = SCAN_PASSIVE; + else + #endif /*CONFIG_RTW_ACS*/ + scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE; } } if (scan_ch != 0) { next_state = SCAN_PROCESS; -#ifdef CONFIG_SCAN_BACKOP - { - struct mi_state mstate; - u8 backop_flags = 0; - - rtw_mi_status(padapter, &mstate); - if ((MSTATE_STA_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) - || (MSTATE_STA_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN_NL))) - backop_flags |= mlmeext_scan_backop_flags_sta(pmlmeext); - - if ((MSTATE_AP_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN)) - || (MSTATE_AP_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN_NL))) - backop_flags |= mlmeext_scan_backop_flags_ap(pmlmeext); - - if (backop_flags) { - if (ss->scan_cnt < ss->scan_cnt_max) - ss->scan_cnt++; - else { - mlmeext_assign_scan_backop_flags(pmlmeext, backop_flags); - next_state = SCAN_BACKING_OP; - } + #ifdef CONFIG_SCAN_BACKOP + if (backop_flags) { + if (ss->scan_cnt < ss->scan_cnt_max) + ss->scan_cnt++; + else { + mlmeext_assign_scan_backop_flags(pmlmeext, backop_flags); + next_state = SCAN_BACKING_OP; } } -#endif /* CONFIG_SCAN_BACKOP */ + #endif + } else if (rtw_p2p_findphase_ex_is_needed(pwdinfo)) { /* go p2p listen */ next_state = SCAN_TO_P2P_LISTEN; @@ -14049,30 +14460,18 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE * void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType) { struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct ss_res *ss = &pmlmeext->sitesurvey_res; u8 ssid_scan = 0; #ifdef CONFIG_P2P +#ifndef CONFIG_IOCTL_CFG80211 struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#endif #endif if (survey_channel != 0) { set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - if (ACS_ENABLE == GET_ACS_STATE(padapter)) { - ACS_OP acs_op = ACS_RESET; - - rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE); - rtw_set_acs_channel(padapter, survey_channel); -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"]-set ch:%u\n", - ADPT_ARG(padapter), rtw_get_acs_channel(padapter)); -#endif - } -#endif - #ifdef CONFIG_DFS if (ScanType == SCAN_PASSIVE && ss->dfs_ch_ssid_scan) ssid_scan = 1; @@ -14185,65 +14584,108 @@ void survey_done_set_ch_bw(_adapter *padapter) FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset); } } +#ifdef CONFIG_MCC_MODE exit: +#endif set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); } -#if 1 -/** - * sitesurvey_ps_annc - check and doing ps announcement for all the adapters of given @dvobj - * @padapter - * @ps: power saving or not - * - * Returns: 0: no ps announcement is doing. 1: ps announcement is doing - */ - -u8 sitesurvey_ps_annc(_adapter *padapter, bool ps) -{ - u8 ps_anc = 0; - - if (rtw_mi_issue_nulldata(padapter, NULL, ps, 3, 500)) - ps_anc = 1; - return ps_anc; -} -#else /** - * sitesurvey_ps_annc - check and doing ps announcement for all the adapters of given @dvobj - * @dvobj: the dvobj to check + * rtw_ps_annc - check and doing ps announcement for all the adapters + * @adapter: the requesting adapter * @ps: power saving or not * * Returns: 0: no ps announcement is doing. 1: ps announcement is doing */ - -u8 sitesurvey_ps_annc(struct dvobj_priv *dvobj, bool ps) +u8 rtw_ps_annc(_adapter *adapter, bool ps) { - _adapter *adapter; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; int i; u8 ps_anc = 0; for (i = 0; i < dvobj->iface_nums; i++) { - adapter = dvobj->padapters[i]; - if (!adapter) + iface = dvobj->padapters[i]; + if (!iface) continue; - if (ps) { - if (is_client_associated_to_ap(adapter) == _TRUE) { + if (MLME_IS_STA(iface)) { + if (is_client_associated_to_ap(iface) == _TRUE) { /* TODO: TDLS peers */ - issue_nulldata(adapter, NULL, 1, 3, 500); + #ifdef CONFIG_MCC_MODE + /* for two station case */ + if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_NEED_MCC)) { + u8 ch = iface->mlmeextpriv.cur_channel; + u8 offset = iface->mlmeextpriv.cur_ch_offset; + u8 bw = iface->mlmeextpriv.cur_bwmode; + + set_channel_bwmode(iface, ch, offset, bw); + } + #endif /* CONFIG_MCC_MODE */ + issue_nulldata(iface, NULL, ps, 3, 500); ps_anc = 1; } - } else { - if (is_client_associated_to_ap(adapter) == _TRUE) { - /* TODO: TDLS peers */ - issue_nulldata(adapter, NULL, 0, 3, 500); + #ifdef CONFIG_RTW_MESH + } else if (MLME_IS_MESH(iface)) { + if (rtw_mesh_ps_annc(iface, ps)) ps_anc = 1; - } + #endif } } return ps_anc; } + +void rtw_leave_opch(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) + return; +#endif + + _enter_critical_mutex(&rfctl->offch_mutex, NULL); + + if (rfctl->offch_state == OFFCHS_NONE) { + /* prepare to leave operating channel */ + rfctl->offch_state = OFFCHS_LEAVING_OP; + + /* clear HW TX queue */ + rtw_hal_set_hwreg(adapter, HW_VAR_CHECK_TXBUF, 0); + + rtw_hal_macid_sleep_all_used(adapter); + + rtw_ps_annc(adapter, 1); + + rfctl->offch_state = OFFCHS_LEAVE_OP; + } + + _exit_critical_mutex(&rfctl->offch_mutex, NULL); +} + +void rtw_back_opch(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) + return; #endif + _enter_critical_mutex(&rfctl->offch_mutex, NULL); + + if (rfctl->offch_state != OFFCHS_NONE) { + rfctl->offch_state = OFFCHS_BACKING_OP; + rtw_hal_macid_wakeup_all_used(adapter); + rtw_ps_annc(adapter, 0); + + rfctl->offch_state = OFFCHS_NONE; + rtw_mi_os_xmit_schedule(adapter); + } + + _exit_critical_mutex(&rfctl->offch_mutex, NULL); +} + void sitesurvey_set_igi(_adapter *adapter) { struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; @@ -14257,7 +14699,7 @@ void sitesurvey_set_igi(_adapter *adapter) case SCAN_ENTER: #ifdef CONFIG_P2P #ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(adapter)->p2p_enabled == _TRUE && pwdinfo->driver_interface == DRIVER_CFG80211) + if (pwdinfo->driver_interface == DRIVER_CFG80211 && rtw_cfg80211_is_p2p_scan(adapter)) igi = 0x30; else #endif /* CONFIG_IOCTL_CFG80211 */ @@ -14265,6 +14707,15 @@ void sitesurvey_set_igi(_adapter *adapter) igi = 0x28; else #endif /* CONFIG_P2P */ + + if (ss->igi) + igi = ss->igi; + else + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(adapter) && rtw_is_acs_igi_valid(adapter)) + igi = rtw_acs_get_adv_igi(adapter); + else + #endif /*CONFIG_RTW_ACS*/ igi = 0x1e; /* record IGI status */ @@ -14283,11 +14734,11 @@ void sitesurvey_set_igi(_adapter *adapter) #ifdef CONFIG_SCAN_BACKOP case SCAN_BACKING_OP: /* write IGI for op channel when DIG is not enabled */ - odm_write_dig(GET_ODM(adapter), ss->igi_before_scan); + odm_write_dig(adapter_to_phydm(adapter), ss->igi_before_scan); break; case SCAN_LEAVE_OP: /* write IGI for scan when DIG is not enabled */ - odm_write_dig(GET_ODM(adapter), ss->igi_scan); + odm_write_dig(adapter_to_phydm(adapter), ss->igi_scan); break; #endif /* CONFIG_SCAN_BACKOP */ default: @@ -14316,14 +14767,49 @@ void sitesurvey_set_msr(_adapter *adapter, bool enter) } Set_MSR(adapter, network_type); } + +void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + _enter_critical_mutex(&rfctl->offch_mutex, NULL); + + switch (scan_state) { + case SCAN_DISABLE: + case SCAN_BACK_OP: + rfctl->offch_state = OFFCHS_NONE; + break; + case SCAN_START: + case SCAN_LEAVING_OP: + rfctl->offch_state = OFFCHS_LEAVING_OP; + break; + case SCAN_ENTER: + case SCAN_LEAVE_OP: + rfctl->offch_state = OFFCHS_LEAVE_OP; + break; + case SCAN_COMPLETE: + case SCAN_BACKING_OP: + rfctl->offch_state = OFFCHS_BACKING_OP; + break; + default: + break; + } + + _exit_critical_mutex(&rfctl->offch_mutex, NULL); +} + u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) { struct sitesurvey_parm *pparm = (struct sitesurvey_parm *)pbuf; +#ifdef DBG_CHECK_FW_PS_STATE struct dvobj_priv *dvobj = padapter->dvobj; struct debug_priv *pdbgpriv = &dvobj->drv_dbg; +#endif struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct ss_res *ss = &pmlmeext->sitesurvey_res; +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); +#endif u8 val8; #ifdef CONFIG_P2P @@ -14358,6 +14844,21 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) goto operation_by_state; case SCAN_START: +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + if ((pwdev_priv->pno_mac_addr[0] != 0xFF) + && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) + && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) { + u16 seq_num; + + rtw_hal_pno_random_gen_mac_addr(padapter); + rtw_hal_set_hw_mac_addr(padapter, pwdev_priv->pno_mac_addr); + get_random_bytes(&seq_num, 2); + pwdev_priv->pno_scan_seq_num = seq_num & 0xFFF; + RTW_INFO("%s pno_scan_seq_num %d\n", __func__, + pwdev_priv->pno_scan_seq_num); + } +#endif + /* * prepare to leave operating channel */ @@ -14374,8 +14875,10 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) /* clear HW TX queue before scan */ rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); + rtw_hal_macid_sleep_all_used(padapter); + /* power save state announcement */ - if (sitesurvey_ps_annc(padapter, 1)) { + if (rtw_ps_annc(padapter, 1)) { mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT); mlmeext_set_scan_next_state(pmlmeext, SCAN_ENTER); set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */ @@ -14412,53 +14915,44 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) u8 next_state; u32 scan_ms; -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - if ((ACS_ENABLE == GET_ACS_STATE(padapter)) && (0 != rtw_get_acs_channel(padapter))) { - ACS_OP acs_op = ACS_SELECT; - - rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE); - } +#ifdef CONFIG_RTW_ACS + if (IS_ACS_ENABLE(padapter)) + rtw_acs_get_rst(padapter); #endif next_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &scan_type); - if (next_state != SCAN_PROCESS) { -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - if (ACS_ENABLE == GET_ACS_STATE(padapter)) { - rtw_set_acs_channel(padapter, 0); -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"]-set ch:%u\n", ADPT_ARG(padapter), rtw_get_acs_channel(padapter)); -#endif - } -#endif + if (next_state != SCAN_PROCESS) { mlmeext_set_scan_state(pmlmeext, next_state); goto operation_by_state; } /* still SCAN_PROCESS state */ - if (0) -#ifdef CONFIG_P2P - RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c\n" - , FUNC_ADPT_ARG(padapter) - , mlmeext_scan_state_str(pmlmeext) - , scan_ch + #ifdef DBG_SITESURVEY + #ifdef CONFIG_P2P + RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c%c\n" + , FUNC_ADPT_ARG(padapter) + , mlmeext_scan_state_str(pmlmeext) + , scan_ch , pwdinfo->find_phase_state_exchange_cnt, ss->channel_idx , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) , scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P' - , ss->ssid[0].SsidLength ? 'S' : ' ' - ); -#else - RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (idx:%d) at %dms, %c%c%c\n" - , FUNC_ADPT_ARG(padapter) - , mlmeext_scan_state_str(pmlmeext) - , scan_ch - , ss->channel_idx + , ss->ssid[0].SsidLength ? 'S' : ' ' + , ss->dfs_ch_ssid_scan ? 'D' : ' ' + ); + #else + RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (idx:%d) at %dms, %c%c%c%c\n" + , FUNC_ADPT_ARG(padapter) + , mlmeext_scan_state_str(pmlmeext) + , scan_ch + , ss->channel_idx , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) , scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P' - , ss->ssid[0].SsidLength ? 'S' : ' ' - ); -#endif /* CONFIG_P2P */ - + , ss->ssid[0].SsidLength ? 'S' : ' ' + , ss->dfs_ch_ssid_scan ? 'D' : ' ' + ); + #endif /* CONFIG_P2P */ + #endif /*DBG_SITESURVEY*/ #ifdef DBG_FIXED_CHAN if (pmlmeext->fixed_chan != 0xff) RTW_INFO(FUNC_ADPT_FMT" fixed_chan:%u\n", pmlmeext->fixed_chan); @@ -14472,7 +14966,12 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) else scan_ms = 40; #else - scan_ms = ss->scan_ch_ms; + #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG) + if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter)) + scan_ms = rtw_acs_get_adv_st(padapter); + else + #endif /*CONFIG_RTW_ACS*/ + scan_ms = ss->scan_ch_ms; #endif #if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) @@ -14480,18 +14979,19 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) scan_ms = scan_ms / 2; #endif -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - { - struct noise_info info; - - info.bPauseDIG = _FALSE; - info.IGIValue = 0; - info.max_time = scan_ms / 2; - info.chan = scan_ch; - rtw_hal_set_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &info, _FALSE); +#ifdef CONFIG_RTW_ACS + if (IS_ACS_ENABLE(padapter)) { + if (pparm->token) + rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_IEEE_11K_HIGH); + else + rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_ACS); } #endif +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + if (IS_NM_ENABLE(padapter)) + rtw_noise_measure(padapter, scan_ch, _FALSE, 0, scan_ms / 2); +#endif set_survey_timer(pmlmeext, scan_ms); break; } @@ -14511,14 +15011,14 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) rtw_warn_on(1); } - if (0) + #ifdef DBG_SITESURVEY RTW_INFO(FUNC_ADPT_FMT" %s ch:%u, bw:%u, offset:%u at %dms\n" , FUNC_ADPT_ARG(padapter) , mlmeext_scan_state_str(pmlmeext) , back_ch, back_bw, back_ch_offset , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) ); - + #endif /*DBG_SITESURVEY*/ set_channel_bwmode(padapter, back_ch, back_ch_offset, back_bw); sitesurvey_set_msr(padapter, _FALSE); @@ -14528,7 +15028,8 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) { sitesurvey_set_igi(padapter); - sitesurvey_ps_annc(padapter, 0); + rtw_hal_macid_wakeup_all_used(padapter); + rtw_ps_annc(padapter, 0); } mlmeext_set_scan_state(pmlmeext, SCAN_BACK_OP); @@ -14553,15 +15054,16 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) case SCAN_LEAVING_OP: /* - * prepare to leave operating channel - */ + * prepare to leave operating channel + */ /* clear HW TX queue before scan */ rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); + rtw_hal_macid_sleep_all_used(padapter); if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC) - && sitesurvey_ps_annc(padapter, 1) - ) { + && rtw_ps_annc(padapter, 1) + ) { mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT); mlmeext_set_scan_next_state(pmlmeext, SCAN_LEAVE_OP); set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */ @@ -14631,6 +15133,9 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) #endif /* CONFIG_P2P */ case SCAN_COMPLETE: +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + rtw_hal_set_hw_mac_addr(padapter, adapter_mac_addr(padapter)); +#endif #ifdef CONFIG_P2P if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) @@ -14663,8 +15168,11 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) #ifdef CONFIG_MCC_MODE /* start MCC fail, then tx null data */ if (!rtw_hal_set_mcc_setting_scan_complete(padapter)) -#endif /* CONFIG_MCC_MODE */ - sitesurvey_ps_annc(padapter, 0); +#endif + { + rtw_hal_macid_wakeup_all_used(padapter); + rtw_ps_annc(padapter, 0); + } /* apply rx ampdu setting */ rtw_rx_ampdu_apply(padapter); @@ -14672,10 +15180,25 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); report_surveydone_event(padapter); +#ifdef CONFIG_RTW_ACS + if (IS_ACS_ENABLE(padapter)) + rtw_acs_select_best_chan(padapter); +#endif +#if defined(CONFIG_BACKGROUND_NOISE_MONITOR) && defined(DBG_NOISE_MONITOR) + if (IS_NM_ENABLE(padapter)) + rtw_noise_info_dump(RTW_DBGDUMP, padapter); +#endif issue_action_BSSCoexistPacket(padapter); issue_action_BSSCoexistPacket(padapter); issue_action_BSSCoexistPacket(padapter); + +#ifdef CONFIG_RTW_80211K + if (ss->token) + rm_post_event(padapter, ss->token, RM_EV_survey_done); +#endif /* CONFIG_RTW_80211K */ + + break; } return H2C_SUCCESS; @@ -14727,23 +15250,26 @@ u8 setkey_hdl(_adapter *padapter, u8 *pbuf) cam_id = rtw_iface_bcmc_id_get(padapter); else #endif - cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, &used); + cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, 1, &used); if (cam_id < 0) goto enable_mc; #ifndef CONFIG_CONCURRENT_MODE - if (cam_id >= 0 && cam_id <= 3) + if (cam_id >= 0 && cam_id <= 3) { + /* default key camid */ addr = null_addr; - else + } else #endif { - if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) - /* for AP mode ,we will force sec cam entry_id so hw dont search cam when tx*/ + /* not default key camid */ + if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) { + /* group TX, force sec cam entry_id */ addr = adapter_mac_addr(padapter); - else - /* not default key, searched by A2 */ + } else { + /* group RX, searched by A2 (TA) */ addr = get_bssid(&padapter->mlmepriv); + } } /* cam entry searched is pairwise key */ @@ -14810,6 +15336,7 @@ u8 setkey_hdl(_adapter *padapter, u8 *pbuf) _rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_BMC)) { struct set_stakey_parm sta_pparm; + _rtw_memset(&sta_pparm, 0, sizeof(struct set_stakey_parm)); sta_pparm.algorithm = pparm->algorithm; sta_pparm.keyid = pparm->keyid; _rtw_memcpy(sta_pparm.key, pparm->key, 16); @@ -14837,11 +15364,12 @@ void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta) if ((psecuritypriv->key_mask & BIT(keyid)) && (keyid == psecuritypriv->dot11PrivacyKeyIndex)) { sta_pparm.algorithm = psecuritypriv->dot11PrivacyAlgrthm; sta_pparm.keyid = keyid; + sta_pparm.gk = 0; _rtw_memcpy(sta_pparm.key, &(psecuritypriv->dot11DefKey[keyid].skey[0]), 16); - _rtw_memcpy(sta_pparm.addr, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(sta_pparm.addr, psta->cmn.mac_addr, ETH_ALEN); RTW_PRINT(FUNC_ADPT_FMT"set WEP - PK with "MAC_FMT" keyid:%u\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->hwaddr), keyid); + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr), keyid); set_stakey_hdl(adapter, (u8 *)&sta_pparm); } @@ -14853,7 +15381,6 @@ u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf) u16 ctrl = 0; s16 cam_id = 0; bool used; - u8 kid = 0; u8 ret = H2C_SUCCESS; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -14872,14 +15399,13 @@ u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf) } pmlmeinfo->enc_algo = pparm->algorithm; - if (is_wep_enc(pparm->algorithm)) - kid = pparm->keyid; - cam_id = rtw_camid_alloc(padapter, psta, kid, &used); + + cam_id = rtw_camid_alloc(padapter, psta, pparm->keyid, pparm->gk, &used); if (cam_id < 0) goto exit; - /* cam entry searched is group key */ - if (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) { + /* cam entry searched is group key when setting pariwise key */ + if (!pparm->gk && used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) { s16 camid_clr; RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u the same key id as group key\n" @@ -14905,9 +15431,12 @@ u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf) rtw_camid_free(padapter, cam_id); } } else { - RTW_PRINT("set pairwise key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n", - cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm)); + RTW_PRINT("set %s key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n" + , pparm->gk ? "group" : "pairwise" + , cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm)); ctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid; + if (pparm->gk) + ctrl |= BIT(6); write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key); } ret = H2C_SUCCESS_RSP; @@ -14954,10 +15483,10 @@ u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf) u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf) { struct addBaRsp_parm *pparm = (struct addBaRsp_parm *)pbuf; - u8 ret = _TRUE, i = 0, try_cnt = 3, wait_ms = 50; struct recv_reorder_ctrl *preorder_ctrl; struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta; + u8 ret = _TRUE; psta = rtw_get_stainfo(pstapriv, pparm->addr); if (!psta) @@ -14970,13 +15499,17 @@ u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf) /* status = 0 means accept this addba req, so update indicate seq = start_seq under this compile flag */ if (pparm->status == 0) { preorder_ctrl->indicate_seq = pparm->start_seq; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, start_seq: %d\n", __func__, __LINE__, - preorder_ctrl->indicate_seq, pparm->start_seq); -#endif + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_UPDATE indicate_seq:%d, start_seq:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq); + #endif } #else preorder_ctrl->indicate_seq = 0xffff; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d, start_seq:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq); + #endif #endif /* @@ -15143,7 +15676,7 @@ u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf) if (!psta_bmc) return H2C_SUCCESS; - if ((pstapriv->tim_bitmap & BIT(0)) && (psta_bmc->sleepq_len > 0)) { + if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) { #ifndef CONFIG_PCI_HCI rtw_msleep_os(10);/* 10ms, ATIM(HIQ) Windows */ #endif @@ -15195,7 +15728,7 @@ u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf) u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf) { - + /*RTW_INFO(FUNC_ADPT_FMT, FUNC_ADPT_ARG(padapter));*/ #ifdef CONFIG_SWTIMER_BASED_TXBCN tx_beacon_handlder(padapter->dvobj); @@ -15223,18 +15756,33 @@ u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf) void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch) { u8 network_type, rate_len, total_rate_len, remainder_rate_len; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u8 erpinfo = 0x4; if (ch >= 36) { network_type = WIRELESS_11A; total_rate_len = IEEE80211_NUM_OFDM_RATESLEN; rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_); + #ifdef CONFIG_80211AC_VHT + /* if channel in 5G band, then add vht ie . */ + if ((pmlmepriv->htpriv.ht_option == _TRUE) + && REGSTY_IS_11AC_ENABLE(&padapter->registrypriv) + && is_supported_vht(padapter->registrypriv.wireless_mode) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) + ) { + if (REGSTY_IS_11AC_AUTO(&padapter->registrypriv) + || pmlmepriv->ori_vht_en) + rtw_vht_ies_attach(padapter, pnetwork); + } + #endif } else { network_type = WIRELESS_11BG; total_rate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN; rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1); + #ifdef CONFIG_80211AC_VHT + rtw_vht_ies_detach(padapter, pnetwork); + #endif } rtw_set_supported_rate(pnetwork->SupportedRates, network_type); @@ -15298,39 +15846,66 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res) if (!iface || iface == adapter) continue; - if (check_fwstate(mlme, WIFI_AP_STATE) + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) && check_fwstate(mlme, WIFI_ASOC_STATE) ) { + u8 ori_ch, ori_bw, ori_offset; bool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); if (is_grouped == _FALSE) { /* handle AP which need to switch ch setting */ + ori_ch = mlmeext->cur_channel; + ori_bw = mlmeext->cur_bwmode; + ori_offset = mlmeext->cur_ch_offset; + /* restore original bw, adjust bw by registry setting on target ch */ mlmeext->cur_bwmode = mlme->ori_bw; mlmeext->cur_channel = u_ch; - rtw_adjust_chbw(iface - , mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset); + rtw_adjust_chbw(iface, mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(iface)) + rtw_mesh_adjust_chbw(mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset); + #endif - rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset + rtw_chset_sync_chbw(adapter_to_chset(adapter) + , &mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset , &u_ch, &u_bw, &u_offset); + RTW_INFO(FUNC_ADPT_FMT" %u,%u,%u => %u,%u,%u\n", FUNC_ADPT_ARG(iface) + , ori_ch, ori_bw, ori_offset + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + rtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network) , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); _rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX)); rtw_start_bss_hdl_after_chbw_decided(iface); + + if (MLME_IS_GO(iface) || MLME_IS_MESH(iface)) { /* pure AP is not needed*/ + #if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + u8 ht_option = 0; + + #ifdef CONFIG_80211N_HT + ht_option = mlme->htpriv.ht_option; + #endif + + rtw_cfg80211_ch_switch_notify(iface + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset + , ht_option); + #endif + } } clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); - update_beacon(iface, 0, NULL, _TRUE); + update_beacon(iface, 0xFF, NULL, _TRUE); } } #ifdef CONFIG_DFS_MASTER - rtw_dfs_master_status_apply(adapter, MLME_STA_CONNECTED); + rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTED, 0); #endif } else { for (i = 0; i < dvobj->iface_nums; i++) { @@ -15341,19 +15916,20 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res) if (!iface || iface == adapter) continue; - if (check_fwstate(mlme, WIFI_AP_STATE) + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) && check_fwstate(mlme, WIFI_ASOC_STATE) ) { clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); - update_beacon(iface, 0, NULL, _TRUE); + update_beacon(iface, 0xFF, NULL, _TRUE); } } #ifdef CONFIG_DFS_MASTER - rtw_dfs_master_status_apply(adapter, MLME_STA_DISCONNECTED); + rtw_dfs_rd_en_decision(adapter, MLME_STA_DISCONNECTED, 0); #endif } if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) { + RTW_INFO(FUNC_ADPT_FMT" union:%u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); set_channel_bwmode(adapter, u_ch, u_offset, u_bw); rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw); } @@ -15366,7 +15942,9 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res) int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) { +#ifdef CONFIG_CONCURRENT_MODE bool chbw_allow = _TRUE; +#endif bool connect_allow = _TRUE; struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; u8 cur_ch, cur_bw, cur_ch_offset; @@ -15403,10 +15981,11 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) dvobj = adapter_to_dvobj(adapter); rtw_mi_status_no_self(adapter, &mstate); - RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, ap_num:%u\n" - , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_AP_NUM(&mstate)); + RTW_INFO(FUNC_ADPT_FMT" others ld_sta_num:%u, ap_num:%u, mesh_num:%u\n" + , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate) + , MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)); - if (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate)) { + if (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) { /* consider linking STA? */ goto connect_allow_hdl; } @@ -15415,7 +15994,7 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) dump_adapters_status(RTW_DBGDUMP , dvobj); rtw_warn_on(1); } - RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n" + RTW_INFO(FUNC_ADPT_FMT" others union:%u,%u,%u\n" , FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); /* chbw_allow? */ @@ -15458,7 +16037,7 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) } #endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */ - if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) >= 2) + if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) + MSTATE_MESH_LD_NUM(&mstate) >= 4) connect_allow = _FALSE; RTW_INFO(FUNC_ADPT_FMT" connect_allow:%d\n" @@ -15470,10 +16049,6 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) connect_allow_hdl: /* connect_allow == _TRUE */ -#ifdef CONFIG_DFS_MASTER - rtw_dfs_master_status_apply(adapter, MLME_STA_CONNECTING); -#endif - if (chbw_allow == _FALSE) { u_ch = cur_ch; u_bw = cur_bw; @@ -15487,7 +16062,7 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) if (!iface || iface == adapter) continue; - if (check_fwstate(mlme, WIFI_AP_STATE) + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) && check_fwstate(mlme, WIFI_ASOC_STATE) ) { #ifdef CONFIG_SPCT_CH_SWITCH @@ -15505,10 +16080,14 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) ) { rtw_disassoc_cmd(iface, 500, RTW_CMDF_DIRECTLY); rtw_indicate_disconnect(iface, 0, _FALSE); - rtw_free_assoc_resources(iface, 1); + rtw_free_assoc_resources(iface, _TRUE); } } } + + #ifdef CONFIG_DFS_MASTER + rtw_dfs_rd_en_decision(adapter, MLME_STA_CONNECTING, 0); + #endif } #endif /* CONFIG_CONCURRENT_MODE */ @@ -15525,10 +16104,9 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) } -u8 set_ch_hdl(_adapter *padapter, u8 *pbuf) +u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf) { struct set_ch_parm *set_ch_parm; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; if (!pbuf) @@ -15552,8 +16130,7 @@ u8 set_ch_hdl(_adapter *padapter, u8 *pbuf) u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf) { struct SetChannelPlan_param *setChannelPlan_param; - struct mlme_priv *mlme = &padapter->mlmepriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); if (!pbuf) return H2C_PARAMETERS_ERROR; @@ -15563,17 +16140,20 @@ u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf) if (!rtw_is_channel_plan_valid(setChannelPlan_param->channel_plan)) return H2C_PARAMETERS_ERROR; - mlme->country_ent = setChannelPlan_param->country_ent; - mlme->ChannelPlan = setChannelPlan_param->channel_plan; + rfctl->country_ent = setChannelPlan_param->country_ent; + rfctl->ChannelPlan = setChannelPlan_param->channel_plan; - pmlmeext->max_chan_nums = init_channel_set(padapter, setChannelPlan_param->channel_plan, pmlmeext->channel_set); - init_channel_list(padapter, pmlmeext->channel_set, &pmlmeext->channel_list); + rfctl->max_chan_nums = init_channel_set(padapter, rfctl->ChannelPlan, rfctl->channel_set); + init_channel_list(padapter, rfctl->channel_set, &rfctl->channel_list); +#ifdef CONFIG_TXPWR_LIMIT + rtw_txpwr_init_regd(rfctl); +#endif rtw_hal_set_odm_var(padapter, HAL_ODM_REGULATION, NULL, _TRUE); #ifdef CONFIG_IOCTL_CFG80211 - rtw_reg_notify_by_driver(padapter); -#endif /* CONFIG_IOCTL_CFG80211 */ + rtw_regd_apply_flags(adapter_to_wiphy(padapter)); +#endif return H2C_SUCCESS; } @@ -15587,48 +16167,22 @@ u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf) ledBlink_param = (struct LedBlink_param *)pbuf; -#ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD +#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD BlinkHandler((PLED_DATA)ledBlink_param->pLed); #endif return H2C_SUCCESS; } -u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf) +u8 set_csa_hdl(_adapter *adapter, unsigned char *pbuf) { #ifdef CONFIG_DFS - struct SetChannelSwitch_param *setChannelSwitch_param; - u8 new_ch_no; - u8 gval8 = 0x00, sval8 = 0xff; - - if (!pbuf) - return H2C_PARAMETERS_ERROR; - - setChannelSwitch_param = (struct SetChannelSwitch_param *)pbuf; - new_ch_no = setChannelSwitch_param->new_ch_no; - - rtw_hal_get_hwreg(padapter, HW_VAR_TXPAUSE, &gval8); - - rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &sval8); - - RTW_INFO("DFS detected! Swiching channel to %d!\n", new_ch_no); - set_channel_bwmode(padapter, new_ch_no, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - - rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &gval8); - - rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); - rtw_indicate_disconnect(padapter, 0, _FALSE); - rtw_free_assoc_resources(padapter, 1); - rtw_free_network_queue(padapter, _TRUE); - - if (rtw_is_dfs_ch(new_ch_no)) - RTW_INFO("Switched to DFS band (ch %u) again!!\n", new_ch_no); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + if (rfctl->csa_ch) + rtw_dfs_ch_switch_hdl(adapter_to_dvobj(adapter)); +#endif return H2C_SUCCESS; -#else - return H2C_REJECTED; -#endif /* CONFIG_DFS */ - } u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) @@ -15644,12 +16198,14 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) struct sta_info *ptdls_sta = NULL; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct sta_info *ap_sta = rtw_get_stainfo(&padapter->stapriv, get_my_bssid(&(pmlmeinfo->network))); u8 survey_channel, i, min, option; struct tdls_txmgmt txmgmt; u32 setchtime, resp_sleep = 0, wait_time; u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; u8 ret; u8 doiqk; + u64 tx_ra_bitmap = 0; if (!pbuf) return H2C_PARAMETERS_ERROR; @@ -15678,17 +16234,19 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) /* leave ALL PS when TDLS is established */ rtw_pwr_wakeup(padapter); - rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_WRCR, 0); - RTW_INFO("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->hwaddr)); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_LINKED); + RTW_INFO("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->cmn.mac_addr)); /* Set TDLS sta rate. */ /* Update station supportRate */ - rtw_hal_update_sta_rate_mask(padapter, ptdls_sta); + rtw_hal_update_sta_ra_info(padapter, ptdls_sta); + tx_ra_bitmap = ptdls_sta->cmn.ra_info.ramask; + if (pmlmeext->cur_channel > 14) { - if (ptdls_sta->ra_mask & 0xffff000) + if (tx_ra_bitmap & 0xffff000) sta_band |= WIRELESS_11_5N ; - if (ptdls_sta->ra_mask & 0xff0) + if (tx_ra_bitmap & 0xff0) sta_band |= WIRELESS_11A; /* 5G band */ @@ -15698,21 +16256,22 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) #endif } else { - if (ptdls_sta->ra_mask & 0xffff000) + if (tx_ra_bitmap & 0xffff000) sta_band |= WIRELESS_11_24N; - if (ptdls_sta->ra_mask & 0xff0) + if (tx_ra_bitmap & 0xff0) sta_band |= WIRELESS_11G; - if (ptdls_sta->ra_mask & 0x0f) + if (tx_ra_bitmap & 0x0f) sta_band |= WIRELESS_11B; } ptdls_sta->wireless_mode = sta_band; - ptdls_sta->raid = rtw_hal_networktype_to_raid(padapter, ptdls_sta); - set_sta_rate(padapter, ptdls_sta); - rtw_sta_media_status_rpt(padapter, ptdls_sta, 1); + rtw_hal_update_sta_wset(padapter, ptdls_sta); /* Sta mode */ rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, ptdls_sta, _TRUE); + + set_sta_rate(padapter, ptdls_sta); + rtw_sta_media_status_rpt(padapter, ptdls_sta, 1); break; } case TDLS_ISSUE_PTI: @@ -15724,8 +16283,10 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) case TDLS_CH_SW_RESP: _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); txmgmt.status_code = 0; - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); + if (ap_sta) + rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id); issue_nulldata(padapter, NULL, 1, 3, 3); RTW_INFO("[TDLS ] issue tdls channel switch response\n"); @@ -15734,12 +16295,12 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) /* If we receive TDLS_CH_SW_REQ at off channel which it's target is AP's channel */ /* then we just switch to AP's channel*/ if (padapter->mlmeextpriv.cur_channel == pchsw_info->off_ch_num) { - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); break; } if (ret == _SUCCESS) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_OFF_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL); else RTW_INFO("[TDLS] issue_tdls_ch_switch_rsp wait ack fail !!!!!!!!!!\n"); @@ -15757,7 +16318,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) /* switch back to base-chnl */ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); pchsw_info->ch_sw_state &= ~(TDLS_CH_SWITCH_PREPARE_STATE); @@ -15766,17 +16327,22 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) rtw_tdls_set_ch_sw_oper_control(padapter, _TRUE); break; case TDLS_CH_SW_TO_OFF_CHNL: + if (ap_sta) + rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id); issue_nulldata(padapter, NULL, 1, 3, 3); + if (padapter->registrypriv.wifi_spec == 0) { if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) _set_timer(&ptdls_sta->ch_sw_timer, (u32)(ptdls_sta->ch_switch_timeout) / 1000); + } if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_OFF_CHNL, pchsw_info->off_ch_num, pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20, ptdls_sta->ch_switch_time) == _SUCCESS) { pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE); if (pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) { - if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->hwaddr, 0, 1, 3) == _FAIL) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL); + if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->cmn.mac_addr, 0, 1, + (padapter->registrypriv.wifi_spec == 0) ? 3 : 0) == _FAIL) + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL); } } else { if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) @@ -15797,7 +16363,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) #endif if (option == TDLS_CH_SW_END_TO_BASE_CHNL) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL); break; case TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED: @@ -15809,13 +16375,15 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) /* Send unsolicited channel switch rsp. to peer */ _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); txmgmt.status_code = 0; - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); issue_tdls_ch_switch_rsp(padapter, &txmgmt, _FALSE); } } if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_BASE_CHNL, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode, ptdls_sta->ch_switch_time) == _SUCCESS) { + if (ap_sta) + rtw_hal_macid_wakeup(padapter, ap_sta->cmn.mac_id); issue_nulldata(padapter, NULL, 0, 3, 3); /* set ch sw monitor timer for responder */ if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) @@ -15825,17 +16393,19 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) break; #endif case TDLS_RS_RCR: - rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_RS_RCR, 0); - RTW_INFO("[TDLS] write REG_RCR, set bit6 on\n"); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK); break; case TDLS_TEARDOWN_STA: + case TDLS_TEARDOWN_STA_NO_WAIT: _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - txmgmt.status_code = 0; - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); + + issue_tdls_teardown(padapter, &txmgmt, (option == TDLS_TEARDOWN_STA) ? _TRUE : _FALSE); - issue_tdls_teardown(padapter, &txmgmt, _TRUE); break; case TDLS_TEARDOWN_STA_LOCALLY: + case TDLS_TEARDOWN_STA_LOCALLY_POST: #ifdef CONFIG_TDLS_CH_SW if (_rtw_memcmp(TDLSoption->addr, pchsw_info->addr, ETH_ALEN) == _TRUE) { pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE | @@ -15845,8 +16415,15 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) _rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN); } #endif - rtw_sta_media_status_rpt(padapter, ptdls_sta, 0); - free_tdls_sta(padapter, ptdls_sta); + + if (option == TDLS_TEARDOWN_STA_LOCALLY) + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + + rtw_tdls_teardown_post_hdl(padapter, ptdls_sta, _FALSE); + + if (ptdlsinfo->tdls_sctx != NULL) + rtw_sctx_done(&(ptdlsinfo->tdls_sctx)); + break; } diff --git a/core/rtw_mp.c b/core/rtw_mp.c index b6cb747..a00523d 100644 --- a/core/rtw_mp.c +++ b/core/rtw_mp.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_MP_C_ #include #ifdef PLATFORM_FREEBSD @@ -152,6 +147,7 @@ static void _init_mp_priv_(struct mp_priv *pmp_priv) pmp_priv->bloopback = _FALSE; pmp_priv->bloadefusemap = _FALSE; + pmp_priv->brx_filter_beacon = _FALSE; pnetwork = &pmp_priv->mp_network.network; _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN); @@ -164,6 +160,8 @@ static void _init_mp_priv_(struct mp_priv *pmp_priv) pmp_priv->tx.attrib.ht_en = 1; #endif + pmp_priv->mpt_ctx.mpt_rate_index = 1; + } #ifdef PLATFORM_WINDOWS @@ -225,6 +223,7 @@ static int init_mp_priv_by_os(struct mp_priv *pmp_priv) #endif #ifdef PLATFORM_LINUX +#if 0 static int init_mp_priv_by_os(struct mp_priv *pmp_priv) { int i, res; @@ -266,6 +265,7 @@ static int init_mp_priv_by_os(struct mp_priv *pmp_priv) return res; } #endif +#endif static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter) { @@ -301,6 +301,11 @@ static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter) pattrib->pktlen = 1500; + if (pHalData->rf_type == RF_2T2R) + pattrib->raid = RATEID_IDX_BGN_40M_2SS; + else + pattrib->raid = RATEID_IDX_BGN_40M_1SS; + #ifdef CONFIG_80211AC_VHT if (pHalData->rf_type == RF_1T1R) pattrib->raid = RATEID_IDX_VHT_1SS; @@ -342,7 +347,6 @@ s32 init_mp_priv(PADAPTER padapter) pmppriv->antenna_rx = ANTENNA_AB; break; case RF_2T2R: - case RF_2T2R_GREEN: pmppriv->antenna_tx = ANTENNA_AB; pmppriv->antenna_rx = ANTENNA_AB; break; @@ -367,7 +371,7 @@ void free_mp_priv(struct mp_priv *pmp_priv) pmp_priv->pmp_xmtframe_buf = NULL; } - +#if 0 static VOID PHY_IQCalibrate_default( IN PADAPTER pAdapter, IN BOOLEAN bReCovery @@ -390,10 +394,14 @@ static VOID PHY_SetRFPathSwitch_default( { RTW_INFO("%s\n", __func__); } - +#endif void mpt_InitHWConfig(PADAPTER Adapter) { + PHAL_DATA_TYPE hal; + + hal = GET_HAL_DATA(Adapter); + if (IS_HARDWARE_TYPE_8723B(Adapter)) { /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */ /* TODO: A better solution is configure it according EFUSE during the run-time. */ @@ -426,6 +434,15 @@ void mpt_InitHWConfig(PADAPTER Adapter) else if (IS_HARDWARE_TYPE_8814A(Adapter)) PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000); #endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(Adapter)) { + rtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000); + rtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800)); + } +#endif + + #ifdef CONFIG_RTL8822B else if (IS_HARDWARE_TYPE_8822B(Adapter)) { u32 tmp_reg = 0; @@ -444,112 +461,24 @@ void mpt_InitHWConfig(PADAPTER Adapter) else if (IS_HARDWARE_TYPE_8821C(Adapter)) PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000); #endif /* CONFIG_RTL8821C */ +#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) + else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) { + if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) { + RTW_INFO("%s() Active large power detection\n", __func__); + phy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv)); + } + } +#endif } static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery) { - PHAL_DATA_TYPE pHalData; - u8 b2ant; /* false:1ant, true:2-ant */ - u8 RF_Path; /* 0:S1, 1:S0 */ - - if (IS_HARDWARE_TYPE_8723B(padapter)) { -#ifdef CONFIG_RTL8723B - pHalData = GET_HAL_DATA(padapter); - b2ant = pHalData->EEPROMBluetoothAntNum == Ant_x2 ? _TRUE : _FALSE; - phy_iq_calibrate_8723b(padapter, bReCovery, _FALSE, b2ant, pHalData->ant_path); -#endif - } else if (IS_HARDWARE_TYPE_8188E(padapter)) { -#ifdef CONFIG_RTL8188E - phy_iq_calibrate_8188e(padapter, bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8814A(padapter)) { -#ifdef CONFIG_RTL8814A - phy_iq_calibrate_8814a(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8812(padapter)) { -#ifdef CONFIG_RTL8812A - phy_iq_calibrate_8812a(padapter, bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8821(padapter)) { -#ifdef CONFIG_RTL8821A - phy_iq_calibrate_8821a(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8192E(padapter)) { -#ifdef CONFIG_RTL8192E - phy_iq_calibrate_8192e(padapter, bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8703B(padapter)) { -#ifdef CONFIG_RTL8703B - phy_iq_calibrate_8703b(padapter, bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8188F(padapter)) { -#ifdef CONFIG_RTL8188F - phy_iq_calibrate_8188f(padapter, bReCovery, _FALSE); -#endif - } else if (IS_HARDWARE_TYPE_8822B(padapter)) { -#ifdef CONFIG_RTL8822B - phy_iq_calibrate_8822b(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8723D(padapter)) { -#ifdef CONFIG_RTL8723D - phy_iq_calibrate_8723d(padapter, bReCovery); -#endif - } else if (IS_HARDWARE_TYPE_8821C(padapter)) { -#ifdef CONFIG_RTL8821C - phy_iq_calibrate_8821c(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); -#endif - } - + halrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); } static void PHY_LCCalibrate(PADAPTER padapter) { - if (IS_HARDWARE_TYPE_8723B(padapter)) { -#ifdef CONFIG_RTL8723B - phy_lc_calibrate_8723b(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8188E(padapter)) { -#ifdef CONFIG_RTL8188E - phy_lc_calibrate_8188e(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8814A(padapter)) { -#ifdef CONFIG_RTL8814A - phy_lc_calibrate_8814a(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8812(padapter)) { -#ifdef CONFIG_RTL8812A - phy_lc_calibrate_8812a(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8821(padapter)) { -#ifdef CONFIG_RTL8821A - phy_lc_calibrate_8821a(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8192E(padapter)) { -#ifdef CONFIG_RTL8192E - phy_lc_calibrate_8192e(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8703B(padapter)) { -#ifdef CONFIG_RTL8703B - phy_lc_calibrate_8703b(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8188F(padapter)) { -#ifdef CONFIG_RTL8188F - phy_lc_calibrate_8188f(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8822B(padapter)) { -#ifdef CONFIG_RTL8822B - phy_lc_calibrate_8822b(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8723D(padapter)) { -#ifdef CONFIG_RTL8723D - phy_lc_calibrate_8723d(&(GET_HAL_DATA(padapter)->odmpriv)); -#endif - } else if (IS_HARDWARE_TYPE_8821C(padapter)) { -#ifdef CONFIG_RTL8821C - /*phy_iq_calibrate_8821c(&(GET_HAL_DATA(padapter)->odmpriv));*/ -#endif - } - + halrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv)); } static u8 PHY_QueryRFPathSwitch(PADAPTER padapter) @@ -583,6 +512,10 @@ static u8 PHY_QueryRFPathSwitch(PADAPTER padapter) } else if (IS_HARDWARE_TYPE_8188F(padapter)) { #ifdef CONFIG_RTL8188F bmain = PHY_QueryRFPathSwitch_8188F(padapter); +#endif + } else if (IS_HARDWARE_TYPE_8188GTV(padapter)) { +#ifdef CONFIG_RTL8188GTV + bmain = PHY_QueryRFPathSwitch_8188GTV(padapter); #endif } else if (IS_HARDWARE_TYPE_8822B(padapter)) { #ifdef CONFIG_RTL8822B @@ -606,49 +539,91 @@ static u8 PHY_QueryRFPathSwitch(PADAPTER padapter) static void PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) { + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); + struct dm_struct *phydm = &hal->odmpriv; + if (IS_HARDWARE_TYPE_8723B(padapter)) { #ifdef CONFIG_RTL8723B - phy_set_rf_path_switch_8723b(padapter, bMain); + phy_set_rf_path_switch_8723b(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8188E(padapter)) { #ifdef CONFIG_RTL8188E - phy_set_rf_path_switch_8188e(padapter, bMain); + phy_set_rf_path_switch_8188e(phydm, bMain); #endif - } else if (IS_HARDWARE_TYPE_8814A(padapter)) { + } else if (IS_HARDWARE_TYPE_8814A(padapter)) { #ifdef CONFIG_RTL8814A - phy_set_rf_path_switch_8814a(padapter, bMain); + phy_set_rf_path_switch_8814a(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) { #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) - phy_set_rf_path_switch_8812a(padapter, bMain); + phy_set_rf_path_switch_8812a(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8192E(padapter)) { #ifdef CONFIG_RTL8192E - phy_set_rf_path_switch_8192e(padapter, bMain); + phy_set_rf_path_switch_8192e(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8703B(padapter)) { #ifdef CONFIG_RTL8703B - phy_set_rf_path_switch_8703b(padapter, bMain); + phy_set_rf_path_switch_8703b(phydm, bMain); #endif - } else if (IS_HARDWARE_TYPE_8188F(padapter)) { -#ifdef CONFIG_RTL8188F - phy_set_rf_path_switch_8188f(padapter, bMain); + } else if (IS_HARDWARE_TYPE_8188F(padapter) || IS_HARDWARE_TYPE_8188GTV(padapter)) { +#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) + phy_set_rf_path_switch_8188f(phydm, bMain); +#endif + } else if (IS_HARDWARE_TYPE_8192F(padapter)) { +#ifdef CONFIG_RTL8192F + phy_set_rf_path_switch_8192f(padapter, bMain); #endif } else if (IS_HARDWARE_TYPE_8822B(padapter)) { #ifdef CONFIG_RTL8822B - phy_set_rf_path_switch_8822b(padapter, bMain); + phy_set_rf_path_switch_8822b(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8723D(padapter)) { #ifdef CONFIG_RTL8723D - phy_set_rf_path_switch_8723d(padapter, bMain); + phy_set_rf_path_switch_8723d(phydm, bMain); #endif } else if (IS_HARDWARE_TYPE_8821C(padapter)) { #ifdef CONFIG_RTL8821C - phy_set_rf_path_switch_8821c(padapter, bMain); + phy_set_rf_path_switch_8821c(phydm, bMain); #endif } } + +static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) { +#ifdef CONFIG_RTL8821C + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dm_struct *p_dm = &pHalData->odmpriv; + + if (IS_HARDWARE_TYPE_8821C(padapter)) { + config_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c); + /* Do IQK when switching to BTG/WLG, requested by RF Binson */ + if (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG) + PHY_IQCalibrate(padapter, FALSE); + } +#endif + +} + + +#ifdef CONFIG_ANTENNA_DIVERSITY +u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 cur_ant, change_ant; + + if (!pHalData->AntDivCfg) + return _FALSE; + /*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/ + change_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT; + + RTW_INFO("%s: config %s\n", __func__, (bMain == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + rtw_antenna_select_cmd(padapter, change_ant, _FALSE); + + return _TRUE; +} +#endif + s32 MPT_InitializeAdapter( IN PADAPTER pAdapter, @@ -659,7 +634,6 @@ MPT_InitializeAdapter( s32 rtStatus = _SUCCESS; PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx; u32 ledsetting; - struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; pMptCtx->bMptDrvUnload = _FALSE; pMptCtx->bMassProdTest = _FALSE; @@ -683,11 +657,12 @@ MPT_InitializeAdapter( /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/ phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0); PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/ - /*<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten. */ - if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); + + if (pHalData->PackageType == PACKAGE_DEFAULT) + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E); + } /*set ant to wifi side in mp mode*/ rtw_write16(pAdapter, 0x870, 0x300); @@ -696,7 +671,7 @@ MPT_InitializeAdapter( pMptCtx->bMptWorkItemInProgress = _FALSE; pMptCtx->CurrMptAct = NULL; - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; /* ------------------------------------------------------------------------- */ /* Don't accept any packets */ rtw_write32(pAdapter, REG_RCR, 0); @@ -818,63 +793,59 @@ void rtw_mp_trigger_lck(PADAPTER padapter) PHY_LCCalibrate(padapter); } -static void disable_dm(PADAPTER padapter) +static void init_mp_data(PADAPTER padapter) { u8 v8; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; - /* 3 1. disable firmware dynamic mechanism */ - /* disable Power Training, Rate Adaptive */ + /*disable BCN*/ v8 = rtw_read8(padapter, REG_BCN_CTRL); v8 &= ~EN_BCN_FUNCTION; rtw_write8(padapter, REG_BCN_CTRL, v8); - /* 3 2. disable driver dynamic mechanism */ - rtw_phydm_func_disable_all(padapter); - - /* enable APK, LCK and IQK but disable power tracking */ pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE; - rtw_phydm_func_set(padapter, ODM_RF_CALIBRATION); - - /* #ifdef CONFIG_BT_COEXIST */ - /* rtw_btcoex_Switch(padapter, 0); */ /* remove for BT MP Down. */ - /* #endif */ } - void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + u32 rf_ability; if (bstart == 1) { RTW_INFO("in MPT_PwrCtlDM start\n"); - rtw_phydm_func_set(padapter, ODM_RF_TX_PWR_TRACK); + + rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK; + halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability); pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE; padapter->mppriv.mp_dm = 1; } else { RTW_INFO("in MPT_PwrCtlDM stop\n"); - rtw_phydm_func_clr(padapter, ODM_RF_TX_PWR_TRACK); + rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK; + halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability); pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE; padapter->mppriv.mp_dm = 0; { - struct _TXPWRTRACK_CFG c; + struct txpwrtrack_cfg c; u1Byte chnl = 0 ; - _rtw_memset(&c, 0, sizeof(struct _TXPWRTRACK_CFG)); + _rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg)); configure_txpower_track(pDM_Odm, &c); odm_clear_txpowertracking_state(pDM_Odm); if (*c.odm_tx_pwr_track_set_pwr) { if (pDM_Odm->support_ic_type == ODM_RTL8188F) - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl); else if (pDM_Odm->support_ic_type == ODM_RTL8723D) { - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl); SetTxPower(padapter); + } else if (pDM_Odm->support_ic_type == ODM_RTL8192F) { + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_B, chnl); } else { - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl); - (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_B, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl); } } } @@ -888,7 +859,6 @@ u32 mp_join(PADAPTER padapter, u8 mode) WLAN_BSSID_EX bssid; struct sta_info *psta; u32 length; - u8 val8, join_type; _irqL irqL; s32 res = _SUCCESS; @@ -899,9 +869,6 @@ u32 mp_join(PADAPTER padapter, u8 mode) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); -#ifdef CONFIG_IOCTL_CFG80211 - struct wireless_dev *pwdev = padapter->rtw_wdev; -#endif /* #ifdef CONFIG_IOCTL_CFG80211 */ /* 1. initialize a new WLAN_BSSID_EX */ _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX)); RTW_INFO("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x\n", __func__, @@ -940,7 +907,7 @@ u32 mp_join(PADAPTER padapter, u8 mode) if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { rtw_disassoc_cmd(padapter, 500, 0); rtw_indicate_disconnect(padapter, 0, _FALSE); - rtw_free_assoc_resources(padapter, 1); + rtw_free_assoc_resources_cmd(padapter, _TRUE, 0); } pmppriv->prev_fw_state = get_fwstate(pmlmepriv); /*pmlmepriv->fw_state = WIFI_MP_STATE;*/ @@ -967,7 +934,7 @@ u32 mp_join(PADAPTER padapter, u8 mode) set_fwstate(pmlmepriv, WIFI_STATION_STATE); /* 3 3. join psudo AdHoc */ tgt_network->join_res = 1; - tgt_network->aid = psta->aid = 1; + tgt_network->aid = psta->cmn.aid = 1; _rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length); rtw_update_registrypriv_dev_network(padapter); @@ -988,12 +955,8 @@ u32 mp_join(PADAPTER padapter, u8 mode) /* set msr to WIFI_FW_ADHOC_STATE */ pmlmeinfo->state = WIFI_FW_ADHOC_STATE; Set_MSR(padapter, (pmlmeinfo->state & 0x3)); - rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); - join_type = 0; - rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); - - report_join_res(padapter, 1); + rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED); pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; } else { Set_MSR(padapter, WIFI_FW_STATION_STATE); @@ -1016,17 +979,10 @@ s32 mp_start_test(PADAPTER padapter) padapter->registrypriv.mp_mode = 1; - /* 3 disable dynamic mechanism */ - disable_dm(padapter); + init_mp_data(padapter); #ifdef CONFIG_RTL8814A rtl8814_InitHalDm(padapter); #endif /* CONFIG_RTL8814A */ -#ifdef CONFIG_RTL8822B - rtl8822b_phy_init_haldm(padapter); -#endif /* CONFIG_RTL8822B */ -#ifdef CONFIG_RTL8821C - rtl8821c_phy_init_haldm(padapter); -#endif /* CONFIG_RTL8821C */ #ifdef CONFIG_RTL8812A rtl8812_InitHalDm(padapter); #endif /* CONFIG_RTL8812A */ @@ -1042,6 +998,9 @@ s32 mp_start_test(PADAPTER padapter) #ifdef CONFIG_RTL8188F rtl8188f_InitHalDm(padapter); #endif +#ifdef CONFIG_RTL8188GTV + rtl8188gtv_InitHalDm(padapter); +#endif #ifdef CONFIG_RTL8188E rtl8188e_InitHalDm(padapter); #endif @@ -1064,7 +1023,6 @@ s32 mp_start_test(PADAPTER padapter) pmppriv->antenna_rx = ANTENNA_AB; break; case RF_2T2R: - case RF_2T2R_GREEN: pmppriv->antenna_tx = ANTENNA_AB; pmppriv->antenna_rx = ANTENNA_AB; break; @@ -1102,7 +1060,7 @@ void mp_stop_test(PADAPTER padapter) rtw_indicate_disconnect(padapter, 0, _FALSE); /* 3 2. clear psta used in mp test mode. - * rtw_free_assoc_resources(padapter, 1); */ + * rtw_free_assoc_resources(padapter, _TRUE); */ psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress); if (psta) rtw_free_stainfo(padapter, psta); @@ -1135,6 +1093,9 @@ void mp_stop_test(PADAPTER padapter) #ifdef CONFIG_RTL8188F rtl8188f_InitHalDm(padapter); #endif +#ifdef CONFIG_RTL8188GTV + rtl8188gtv_InitHalDm(padapter); +#endif #ifdef CONFIG_RTL8723D rtl8723d_InitHalDm(padapter); #endif @@ -1200,6 +1161,7 @@ static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Ch * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3. * *---------------------------------------------------------------------------*/ +#if 0 static void mpt_SwitchRfSetting(PADAPTER pAdapter) { hal_mpt_SwitchRfSetting(pAdapter); @@ -1211,6 +1173,7 @@ static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) { hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14); } +#endif /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ @@ -1272,6 +1235,13 @@ void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain) } +void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate) +{ + + phy_switch_rf_path_set(pAdapter, pstate); + +} + u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter) { return PHY_QueryRFPathSwitch(pAdapter); @@ -1282,6 +1252,7 @@ s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther) return hal_mpt_SetThermalMeter(pAdapter, target_ther); } +#if 0 static void TriggerRFThermalMeter(PADAPTER pAdapter) { hal_mpt_TriggerRFThermalMeter(pAdapter); @@ -1291,6 +1262,7 @@ static u8 ReadRFThermalMeter(PADAPTER pAdapter) { return hal_mpt_ReadRFThermalMeter(pAdapter); } +#endif void GetThermalMeter(PADAPTER pAdapter, u8 *value) { @@ -1364,6 +1336,48 @@ static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv) } +#ifdef CONFIG_PCI_HCI +static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib) +{ + u32 prio; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_tx_ring *ring; + + switch (pattrib->qsel) { + case 0: + case 3: + prio = BE_QUEUE_INX; + break; + case 1: + case 2: + prio = BK_QUEUE_INX; + break; + case 4: + case 5: + prio = VI_QUEUE_INX; + break; + case 6: + case 7: + prio = VO_QUEUE_INX; + break; + default: + prio = BE_QUEUE_INX; + break; + } + + ring = &pxmitpriv->tx_ring[prio]; + + /* + * for now we reserve two free descriptor as a safety boundary + * between the tail and the head + */ + if ((ring->entries - ring->qlen) >= 2) + return _TRUE; + else + return _FALSE; +} +#endif + static thread_return mp_xmit_packet_thread(thread_context context) { struct xmit_frame *pxmitframe; @@ -1382,6 +1396,12 @@ static thread_return mp_xmit_packet_thread(thread_context context) RTW_INFO("%s:pkTx Start\n", __func__); while (1) { pxmitframe = alloc_mp_xmitframe(pxmitpriv); +#ifdef CONFIG_PCI_HCI + if(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) { + rtw_usleep_os(1000); + continue; + } +#endif if (pxmitframe == NULL) { if (pmptx->stop || RTW_CANNOT_RUN(padapter)) @@ -1490,7 +1510,7 @@ void fill_tx_desc_8814a(PADAPTER padapter) u32 pkt_size = pattrib->last_txcmdsz; s32 bmcast = IS_MCAST(pattrib->ra); - u8 data_rate, pwr_status, offset; + u8 offset; /* SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); */ SET_TX_DESC_LAST_SEG_8814A(pDesc, 1); @@ -1744,6 +1764,37 @@ void fill_tx_desc_8188f(PADAPTER padapter) } #endif +#if defined(CONFIG_RTL8188GTV) +void fill_tx_desc_8188gtv(PADAPTER padapter) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); + u8 *ptxdesc = pmp_priv->tx.desc; + + SET_TX_DESC_AGG_BREAK_8188GTV(ptxdesc, 1); + SET_TX_DESC_MACID_8188GTV(ptxdesc, pattrib->mac_id); + SET_TX_DESC_QUEUE_SEL_8188GTV(ptxdesc, pattrib->qsel); + + SET_TX_DESC_RATE_ID_8188GTV(ptxdesc, pattrib->raid); + SET_TX_DESC_SEQ_8188GTV(ptxdesc, pattrib->seqnum); + SET_TX_DESC_HWSEQ_EN_8188GTV(ptxdesc, 1); + SET_TX_DESC_USE_RATE_8188GTV(ptxdesc, 1); + SET_TX_DESC_DISABLE_FB_8188GTV(ptxdesc, 1); + + if (pmp_priv->preamble) + if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) + SET_TX_DESC_DATA_SHORT_8188GTV(ptxdesc, 1); + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) + SET_TX_DESC_DATA_BW_8188GTV(ptxdesc, 1); + + SET_TX_DESC_TX_RATE_8188GTV(ptxdesc, pmp_priv->rateidx); + + SET_TX_DESC_DATA_RATE_FB_LIMIT_8188GTV(ptxdesc, 0x1F); + SET_TX_DESC_RTS_RATE_FB_LIMIT_8188GTV(ptxdesc, 0xF); +} +#endif + #if defined(CONFIG_RTL8723D) void fill_tx_desc_8723d(PADAPTER padapter) { @@ -1776,6 +1827,70 @@ void fill_tx_desc_8723d(PADAPTER padapter) } #endif +#if defined(CONFIG_RTL8710B) +void fill_tx_desc_8710b(PADAPTER padapter) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); + u8 *ptxdesc = pmp_priv->tx.desc; + + SET_TX_DESC_BK_8710B(ptxdesc, 1); + SET_TX_DESC_MACID_8710B(ptxdesc, pattrib->mac_id); + SET_TX_DESC_QUEUE_SEL_8710B(ptxdesc, pattrib->qsel); + + SET_TX_DESC_RATE_ID_8710B(ptxdesc, pattrib->raid); + SET_TX_DESC_SEQ_8710B(ptxdesc, pattrib->seqnum); + SET_TX_DESC_HWSEQ_EN_8710B(ptxdesc, 1); + SET_TX_DESC_USE_RATE_8710B(ptxdesc, 1); + SET_TX_DESC_DISABLE_FB_8710B(ptxdesc, 1); + + if (pmp_priv->preamble) { + if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) + SET_TX_DESC_DATA_SHORT_8710B(ptxdesc, 1); + } + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) + SET_TX_DESC_DATA_BW_8710B(ptxdesc, 1); + + SET_TX_DESC_TX_RATE_8710B(ptxdesc, pmp_priv->rateidx); + + SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(ptxdesc, 0x1F); + SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(ptxdesc, 0xF); +} +#endif + +#if defined(CONFIG_RTL8192F) +void fill_tx_desc_8192f(PADAPTER padapter) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); + u8 *ptxdesc = pmp_priv->tx.desc; + + SET_TX_DESC_BK_8192F(ptxdesc, 1); + SET_TX_DESC_MACID_8192F(ptxdesc, pattrib->mac_id); + SET_TX_DESC_QUEUE_SEL_8192F(ptxdesc, pattrib->qsel); + + SET_TX_DESC_RATE_ID_8192F(ptxdesc, pattrib->raid); + SET_TX_DESC_SEQ_8192F(ptxdesc, pattrib->seqnum); + SET_TX_DESC_HWSEQ_EN_8192F(ptxdesc, 1); + SET_TX_DESC_USE_RATE_8192F(ptxdesc, 1); + SET_TX_DESC_DISABLE_FB_8192F(ptxdesc, 1); + + if (pmp_priv->preamble) { + if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) + SET_TX_DESC_DATA_SHORT_8192F(ptxdesc, 1); + } + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) + SET_TX_DESC_DATA_BW_8192F(ptxdesc, 1); + + SET_TX_DESC_TX_RATE_8192F(ptxdesc, pmp_priv->rateidx); + + SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(ptxdesc, 0x1F); + SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(ptxdesc, 0xF); +} + +#endif static void Rtw_MPSetMacTxEDCA(PADAPTER padapter) { @@ -1793,8 +1908,8 @@ static void Rtw_MPSetMacTxEDCA(PADAPTER padapter) void SetPacketTx(PADAPTER padapter) { - u8 *ptr, *pkt_start, *pkt_end, *fctrl; - u32 pkt_size, offset, startPlace, i; + u8 *ptr, *pkt_start, *pkt_end; + u32 pkt_size, i; struct rtw_ieee80211_hdr *hdr; u8 payload; s32 bmcast; @@ -1815,13 +1930,12 @@ void SetPacketTx(PADAPTER padapter) _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); bmcast = IS_MCAST(pattrib->ra); - if (bmcast) { - pattrib->mac_id = 1; + if (bmcast) pattrib->psta = rtw_get_bcmc_stainfo(padapter); - } else { - pattrib->mac_id = 0; + else pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); - } + + pattrib->mac_id = pattrib->psta->cmn.mac_id; pattrib->mbssid = 0; pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; @@ -1889,10 +2003,24 @@ void SetPacketTx(PADAPTER padapter) fill_tx_desc_8188f(padapter); #endif +#if defined(CONFIG_RTL8188GTV) + if (IS_HARDWARE_TYPE_8188GTV(padapter)) + fill_tx_desc_8188gtv(padapter); +#endif + #if defined(CONFIG_RTL8723D) if (IS_HARDWARE_TYPE_8723D(padapter)) fill_tx_desc_8723d(padapter); #endif +#if defined(CONFIG_RTL8192F) + if (IS_HARDWARE_TYPE_8192F(padapter)) + fill_tx_desc_8192f(padapter); +#endif + +#if defined(CONFIG_RTL8710B) + if (IS_HARDWARE_TYPE_8710B(padapter)) + fill_tx_desc_8710b(padapter); +#endif /* 3 4. make wlan header, make_wlanhdr() */ hdr = (struct rtw_ieee80211_hdr *)pkt_start; @@ -1940,8 +2068,10 @@ void SetPacketTx(PADAPTER padapter) /* 3 6. start thread */ #ifdef PLATFORM_LINUX pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD"); - if (IS_ERR(pmp_priv->tx.PktTxThread)) - RTW_INFO("Create PktTx Thread Fail !!!!!\n"); + if (IS_ERR(pmp_priv->tx.PktTxThread)) { + RTW_ERR("Create PktTx Thread Fail !!!!!\n"); + pmp_priv->tx.PktTxThread = NULL; + } #endif #ifdef PLATFORM_FREEBSD { @@ -1980,11 +2110,13 @@ void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB) MAC_ARG(pmppriv->network_macaddr)); pHalData->ReceiveConfig = 0; pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF; + pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF; #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) write_bbreg(pAdapter, 0x550, BIT3, bEnable); #endif rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */ + pmppriv->brx_filter_beacon = _TRUE; } else { pHalData->ReceiveConfig |= RCR_ADF; @@ -2054,6 +2186,167 @@ u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter) return OFDM_cnt + CCK_cnt + HT_cnt; } +struct psd_init_regs { + /* 3 wire */ + int reg_88c; + int reg_c00; + int reg_e00; + int reg_1800; + int reg_1a00; + /* cck */ + int reg_800; + int reg_808; +}; + +static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs) +{ + HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter); + + switch (phal_data->rf_type) { + /* 1R */ + case RF_1T1R: + if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) { + /* 11AC 1R PSD Setting 3wire & cck off */ + regs->reg_c00 = rtw_read32(padapter, 0xC00); + phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00); + regs->reg_808 = rtw_read32(padapter, 0x808); + phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0); + } else { + /* 11N 3-wire off 1 */ + regs->reg_88c = rtw_read32(padapter, 0x88C); + phy_set_bb_reg(padapter, 0x88C, 0x300000, 0x3); + /* 11N CCK off */ + regs->reg_800 = rtw_read32(padapter, 0x800); + phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0); + } + break; + + /* 2R */ + case RF_1T2R: + case RF_2T2R: + if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) { + /* 11AC 2R PSD Setting 3wire & cck off */ + regs->reg_c00 = rtw_read32(padapter, 0xC00); + regs->reg_e00 = rtw_read32(padapter, 0xE00); + phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00); + phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00); + regs->reg_808 = rtw_read32(padapter, 0x808); + phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0); + } else { + /* 11N 3-wire off 2 */ + regs->reg_88c = rtw_read32(padapter, 0x88C); + phy_set_bb_reg(padapter, 0x88C, 0xF00000, 0xF); + /* 11N CCK off */ + regs->reg_800 = rtw_read32(padapter, 0x800); + phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0); + } + break; + + /* 3R */ + case RF_2T3R: + case RF_3T3R: + if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) { + /* 11AC 3R PSD Setting 3wire & cck off */ + regs->reg_c00 = rtw_read32(padapter, 0xC00); + regs->reg_e00 = rtw_read32(padapter, 0xE00); + regs->reg_1800 = rtw_read32(padapter, 0x1800); + phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00); + phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00); + phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00); + regs->reg_808 = rtw_read32(padapter, 0x808); + phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0); + } else { + RTW_ERR("%s: 11n don't support 3R\n", __func__); + return -1; + } + break; + + /* 4R */ + case RF_2T4R: + case RF_3T4R: + case RF_4T4R: + if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) { + /* 11AC 4R PSD Setting 3wire & cck off */ + regs->reg_c00 = rtw_read32(padapter, 0xC00); + regs->reg_e00 = rtw_read32(padapter, 0xE00); + regs->reg_1800 = rtw_read32(padapter, 0x1800); + regs->reg_1a00 = rtw_read32(padapter, 0x1A00); + phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00); + phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00); + phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00); + phy_set_bb_reg(padapter, 0x1A00, 0x3, 0x00); + regs->reg_808 = rtw_read32(padapter, 0x808); + phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0); + } else { + RTW_ERR("%s: 11n don't support 4R\n", __func__); + return -1; + } + break; + + default: + RTW_ERR("%s: unknown %d rf type\n", __func__, phal_data->rf_type); + return -1; + } + + /* Set PSD points, 0=128, 1=256, 2=512, 3=1024 */ + if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) + phy_set_bb_reg(padapter, 0x910, 0xC000, 3); + else + phy_set_bb_reg(padapter, 0x808, 0xC000, 3); + + RTW_INFO("%s: set %d rf type done\n", __func__, phal_data->rf_type); + return 0; +} + +static int rtw_mp_psd_close(PADAPTER padapter, struct psd_init_regs *regs) +{ + HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter); + + + if (!hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) { + /* 11n 3wire restore */ + rtw_write32(padapter, 0x88C, regs->reg_88c); + /* 11n cck restore */ + rtw_write32(padapter, 0x800, regs->reg_800); + RTW_INFO("%s: restore %d rf type\n", __func__, phal_data->rf_type); + return 0; + } + + /* 11ac 3wire restore */ + switch (phal_data->rf_type) { + case RF_1T1R: + rtw_write32(padapter, 0xC00, regs->reg_c00); + break; + case RF_1T2R: + case RF_2T2R: + rtw_write32(padapter, 0xC00, regs->reg_c00); + rtw_write32(padapter, 0xE00, regs->reg_e00); + break; + case RF_2T3R: + case RF_3T3R: + rtw_write32(padapter, 0xC00, regs->reg_c00); + rtw_write32(padapter, 0xE00, regs->reg_e00); + rtw_write32(padapter, 0x1800, regs->reg_1800); + break; + case RF_2T4R: + case RF_3T4R: + case RF_4T4R: + rtw_write32(padapter, 0xC00, regs->reg_c00); + rtw_write32(padapter, 0xE00, regs->reg_e00); + rtw_write32(padapter, 0x1800, regs->reg_1800); + rtw_write32(padapter, 0x1A00, regs->reg_1a00); + break; + default: + RTW_WARN("%s: unknown %d rf type\n", __func__, phal_data->rf_type); + break; + } + + /* 11ac cck restore */ + rtw_write32(padapter, 0x808, regs->reg_808); + RTW_INFO("%s: restore %d rf type done\n", __func__, phal_data->rf_type); + return 0; +} + /* reg 0x808[9:0]: FFT data x * reg 0x808[22]: 0 --> 1 to get 1 FFT data y * reg 0x8B4[15:0]: FFT data y report */ @@ -2082,7 +2375,11 @@ static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point) rtw_mdelay_os(1); psd_val = rtw_read32(pAdapter, psd_regL); +#if defined(CONFIG_RTL8821C) + psd_val = (psd_val & 0x00FFFFFF) / 32; +#else psd_val &= 0x0000FFFF; +#endif return psd_val; } @@ -2099,7 +2396,8 @@ u32 mp_query_psd(PADAPTER pAdapter, u8 *data) { u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0; u32 psd_data = 0; - + struct psd_init_regs regs = {}; + int psd_analysis = 0; #ifdef PLATFORM_LINUX if (!netif_running(pAdapter->pnetdev)) { @@ -2115,6 +2413,11 @@ u32 mp_query_psd(PADAPTER pAdapter, u8 *data) psd_pts = 128; psd_start = 64; psd_stop = 128; + } else if (strncmp(data, "analysis,", 9) == 0) { + if (rtw_mp_psd_init(pAdapter, ®s) != 0) + return 0; + psd_analysis = 1; + sscanf(data + 9, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop); } else sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop); @@ -2136,6 +2439,9 @@ u32 mp_query_psd(PADAPTER pAdapter, u8 *data) rtw_mdelay_os(100); #endif + if (psd_analysis) + rtw_mp_psd_close(pAdapter, ®s); + return strlen(data) + 1; } @@ -2711,6 +3017,17 @@ u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr) return _FAIL; } +u8 rtw_mp_mode_check(PADAPTER pAdapter) +{ + PADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter); + + if (primary_adapter->registrypriv.mp_mode == 1) + return _TRUE; + else + return _FALSE; +} + + ULONG mpt_ProQueryCalTxPower( PADAPTER pAdapter, u8 RfPath @@ -2721,7 +3038,6 @@ ULONG mpt_ProQueryCalTxPower( PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); ULONG TxPower = 1; - u1Byte rate = 0; struct txpwr_idx_comp tic; u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index); @@ -2732,10 +3048,14 @@ ULONG mpt_ProQueryCalTxPower( , TxPower, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias); pAdapter->mppriv.txpoweridx = (u8)TxPower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)TxPower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)TxPower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)TxPower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)TxPower; + if (RfPath == RF_PATH_A) + pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower; + else if (RfPath == RF_PATH_B) + pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)TxPower; + else if (RfPath == RF_PATH_C) + pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower; + else if (RfPath == RF_PATH_D) + pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)TxPower; hal_mpt_SetTxPower(pAdapter); return TxPower; diff --git a/core/rtw_mp_ioctl.c b/core/rtw_mp_ioctl.c index 33bd6d2..035d281 100644 --- a/core/rtw_mp_ioctl.c +++ b/core/rtw_mp_ioctl.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_MP_IOCTL_C_ #include diff --git a/core/rtw_odm.c b/core/rtw_odm.c index 95b7b9b..3307bbf 100644 --- a/core/rtw_odm.c +++ b/core/rtw_odm.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,23 +11,52 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #include +u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + struct dm_struct *podmpriv = &pHalData->odmpriv; + u32 result = 0; + switch (ops) { + case HAL_PHYDM_DIS_ALL_FUNC: + podmpriv->support_ability = DYNAMIC_FUNC_DISABLE; + halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, DYNAMIC_FUNC_DISABLE); + break; + case HAL_PHYDM_FUNC_SET: + podmpriv->support_ability |= ability; + break; + case HAL_PHYDM_FUNC_CLR: + podmpriv->support_ability &= ~(ability); + break; + case HAL_PHYDM_ABILITY_BK: + /* dm flag backup*/ + podmpriv->bk_support_ability = podmpriv->support_ability; + pHalData->bk_rf_ability = halrf_cmn_info_get(podmpriv, HALRF_CMNINFO_ABILITY); + break; + case HAL_PHYDM_ABILITY_RESTORE: + /* restore dm flag */ + podmpriv->support_ability = podmpriv->bk_support_ability; + halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, pHalData->bk_rf_ability); + break; + case HAL_PHYDM_ABILITY_SET: + podmpriv->support_ability = ability; + break; + case HAL_PHYDM_ABILITY_GET: + result = podmpriv->support_ability; + break; + } + return result; +} /* set ODM_CMNINFO_IC_TYPE based on chip_type */ void rtw_odm_init_ic_type(_adapter *adapter) { - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; + struct dm_struct *odm = adapter_to_phydm(adapter); u4Byte ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter)); rtw_warn_on(!ic_type); @@ -35,20 +64,6 @@ void rtw_odm_init_ic_type(_adapter *adapter) odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type); } -inline void rtw_odm_set_force_igi_lb(_adapter *adapter, u8 lb) -{ - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - - hal_data->u1ForcedIgiLb = lb; -} - -inline u8 rtw_odm_get_force_igi_lb(_adapter *adapter) -{ - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - - return hal_data->u1ForcedIgiLb; -} - void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter) { RTW_PRINT_SEL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n"); @@ -60,9 +75,6 @@ void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter) void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter) { struct registry_priv *regsty = &adapter->registrypriv; - struct mlme_priv *mlme = &adapter->mlmepriv; - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_"); @@ -91,43 +103,16 @@ void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter) _RTW_PRINT_SEL(sel, "INVALID\n"); } -#define RTW_ADAPTIVITY_DML_DISABLE 0 -#define RTW_ADAPTIVITY_DML_ENABLE 1 - -void rtw_odm_adaptivity_dml_msg(void *sel, _adapter *adapter) -{ - struct registry_priv *regsty = &adapter->registrypriv; - - RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_DML_"); - - if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_DISABLE) - _RTW_PRINT_SEL(sel, "DISABLE\n"); - else if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_ENABLE) - _RTW_PRINT_SEL(sel, "ENABLE\n"); - else - _RTW_PRINT_SEL(sel, "INVALID\n"); -} - -void rtw_odm_adaptivity_dc_backoff_msg(void *sel, _adapter *adapter) -{ - struct registry_priv *regsty = &adapter->registrypriv; - - RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_DC_BACKOFF:%u\n", regsty->adaptivity_dc_backoff); -} - void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter) { rtw_odm_adaptivity_ver_msg(sel, adapter); rtw_odm_adaptivity_en_msg(sel, adapter); rtw_odm_adaptivity_mode_msg(sel, adapter); - rtw_odm_adaptivity_dml_msg(sel, adapter); - rtw_odm_adaptivity_dc_backoff_msg(sel, adapter); } bool rtw_odm_adaptivity_needed(_adapter *adapter) { struct registry_priv *regsty = &adapter->registrypriv; - struct mlme_priv *mlme = &adapter->mlmepriv; bool ret = _FALSE; if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) @@ -138,47 +123,32 @@ bool rtw_odm_adaptivity_needed(_adapter *adapter) void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &pHalData->odmpriv; + struct dm_struct *odm = adapter_to_phydm(adapter); rtw_odm_adaptivity_config_msg(sel, adapter); - RTW_PRINT_SEL(sel, "%10s %16s %16s %22s %12s\n" - , "th_l2h_ini", "th_edcca_hl_diff", "th_l2h_ini_mode2", "th_edcca_hl_diff_mode2", "edcca_enable"); - RTW_PRINT_SEL(sel, "0x%-8x %-16d 0x%-14x %-22d %-12d\n" + RTW_PRINT_SEL(sel, "%10s %16s\n" + , "th_l2h_ini", "th_edcca_hl_diff"); + RTW_PRINT_SEL(sel, "0x%-8x %-16d\n" , (u8)odm->th_l2h_ini , odm->th_edcca_hl_diff - , (u8)odm->th_l2h_ini_mode2 - , odm->th_edcca_hl_diff_mode2 - , odm->edcca_enable - ); - - RTW_PRINT_SEL(sel, "%15s %9s\n", "AdapEnableState", "Adap_Flag"); - RTW_PRINT_SEL(sel, "%-15x %-9x\n" - , odm->adaptivity_enable - , odm->adaptivity_flag ); } -void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff, s8 th_l2h_ini_mode2, s8 th_edcca_hl_diff_mode2, u8 edcca_enable) +void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &pHalData->odmpriv; + struct dm_struct *odm = adapter_to_phydm(adapter); odm->th_l2h_ini = th_l2h_ini; odm->th_edcca_hl_diff = th_edcca_hl_diff; - odm->th_l2h_ini_mode2 = th_l2h_ini_mode2; - odm->th_edcca_hl_diff_mode2 = th_edcca_hl_diff_mode2; - odm->edcca_enable = edcca_enable; } void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter) { - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &(hal_data->odmpriv); + struct dm_struct *odm = adapter_to_phydm(adapter); - RTW_PRINT_SEL(sel, "rx_rate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n", - HDATA_RATE(odm->rx_rate), odm->RSSI_A, odm->RSSI_B); + RTW_PRINT_SEL(sel, "rx_rate = %s, rssi_a = %d(%%), rssi_b = %d(%%)\n", + HDATA_RATE(odm->rx_rate), odm->rssi_a, odm->rssi_b); } @@ -208,11 +178,10 @@ void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type) } } -inline u8 rtw_odm_get_dfs_domain(_adapter *adapter) +inline u8 rtw_odm_get_dfs_domain(struct dvobj_priv *dvobj) { #ifdef CONFIG_DFS_MASTER - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &(hal_data->odmpriv); + struct dm_struct *pDM_Odm = dvobj_to_phydm(dvobj); return pDM_Odm->dfs_region_domain; #else @@ -220,10 +189,10 @@ inline u8 rtw_odm_get_dfs_domain(_adapter *adapter) #endif } -inline u8 rtw_odm_dfs_domain_unknown(_adapter *adapter) +inline u8 rtw_odm_dfs_domain_unknown(struct dvobj_priv *dvobj) { #ifdef CONFIG_DFS_MASTER - return rtw_odm_get_dfs_domain(adapter) == PHYDM_DFS_DOMAIN_UNKNOWN; + return rtw_odm_get_dfs_domain(dvobj) == PHYDM_DFS_DOMAIN_UNKNOWN; #else return 1; #endif @@ -232,23 +201,28 @@ inline u8 rtw_odm_dfs_domain_unknown(_adapter *adapter) #ifdef CONFIG_DFS_MASTER inline VOID rtw_odm_radar_detect_reset(_adapter *adapter) { - phydm_radar_detect_reset(GET_ODM(adapter)); + phydm_radar_detect_reset(adapter_to_phydm(adapter)); } inline VOID rtw_odm_radar_detect_disable(_adapter *adapter) { - phydm_radar_detect_disable(GET_ODM(adapter)); + phydm_radar_detect_disable(adapter_to_phydm(adapter)); } /* called after ch, bw is set */ inline VOID rtw_odm_radar_detect_enable(_adapter *adapter) { - phydm_radar_detect_enable(GET_ODM(adapter)); + phydm_radar_detect_enable(adapter_to_phydm(adapter)); } inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter) { - return phydm_radar_detect(GET_ODM(adapter)); + return phydm_radar_detect(adapter_to_phydm(adapter)); +} + +inline u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj) +{ + return phydm_dfs_polling_time(dvobj_to_phydm(dvobj)); } #endif /* CONFIG_DFS_MASTER */ @@ -260,11 +234,11 @@ void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys) #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) _adapter *adapter = rframe->u.hdr.adapter; - struct PHY_DM_STRUCT *phydm = GET_ODM(adapter); + struct dm_struct *phydm = adapter_to_phydm(adapter); struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib; u8 *wlanhdr = get_recvframe_data(rframe); - if (phydm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) { + if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) { /* * 8723D: * type_0(CCK) @@ -293,7 +267,7 @@ void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys) */ if ((*phys & 0xf) == 0) { - struct _phy_status_rpt_jaguar2_type0 *phys_t0 = (struct _phy_status_rpt_jaguar2_type0 *)phys; + struct phy_status_rpt_jaguar2_type0 *phys_t0 = (struct phy_status_rpt_jaguar2_type0 *)phys; if (DBG_RX_PHYSTATUS_CHINFO) { RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n" @@ -306,7 +280,7 @@ void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys) } } else if ((*phys & 0xf) == 1) { - struct _phy_status_rpt_jaguar2_type1 *phys_t1 = (struct _phy_status_rpt_jaguar2_type1 *)phys; + struct phy_status_rpt_jaguar2_type1 *phys_t1 = (struct phy_status_rpt_jaguar2_type1 *)phys; u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc; u8 pkt_cch = 0; u8 pkt_bw = CHANNEL_WIDTH_20; @@ -427,7 +401,7 @@ void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys) attrib->ch = pkt_cch; } else { - struct _phy_status_rpt_jaguar2_type2 *phys_t2 = (struct _phy_status_rpt_jaguar2_type2 *)phys; + struct phy_status_rpt_jaguar2_type2 *phys_t2 = (struct phy_status_rpt_jaguar2_type2 *)phys; if (DBG_RX_PHYSTATUS_CHINFO) { RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n" diff --git a/core/rtw_p2p.c b/core/rtw_p2p.c index c8cc7d2..b0bd8e7 100644 --- a/core/rtw_p2p.c +++ b/core/rtw_p2p.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_P2P_C_ #include @@ -85,7 +80,7 @@ static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf) pcur += ETH_ALEN; /* P2P interface address */ - _rtw_memcpy(pcur, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(pcur, psta->cmn.mac_addr, ETH_ALEN); pcur += ETH_ALEN; *pcur = psta->dev_cap; @@ -295,7 +290,6 @@ static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8 *raddr, unsigned short *fctrl; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); pmgntframe = alloc_mgtxmitframe(pxmitpriv); @@ -757,6 +751,7 @@ u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunnel _adapter *padapter = pwdinfo->padapter; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + u16 v16 = 0; if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) goto exit; @@ -794,36 +789,43 @@ u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunnel if (is_any_client_associated(pwdinfo->padapter)) { if (pwdinfo->wfd_tdls_enable) { /* TDLS mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } else { /* WiFi Direct mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } } else { if (pwdinfo->wfd_tdls_enable) { /* available for WFD session + TDLS mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } else { /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } } } else { if (pwdinfo->wfd_tdls_enable) { /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } else { - /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); } } } else { - if (pwdinfo->wfd_tdls_enable) - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); - else - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); - + if (pwdinfo->wfd_tdls_enable) { + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); + } else { + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT; + RTW_PUT_BE16(wfdie + wfdielen, v16); + } } wfdielen += 2; @@ -2467,7 +2469,7 @@ u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint le /* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ /* issue GO Discoverability Request */ - issue_group_disc_req(pwdinfo, psta->hwaddr); + issue_group_disc_req(pwdinfo, psta->cmn.mac_addr); /* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ status = P2P_STATUS_SUCCESS; @@ -2571,14 +2573,15 @@ u8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8 return ch_no; } -u8 rtw_p2p_ch_inclusion(struct mlme_ext_priv *pmlmeext, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned) +u8 rtw_p2p_ch_inclusion(_adapter *adapter, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); int i = 0, j = 0, temp = 0; u8 ch_no = 0; for (i = 0; i < peer_ch_num; i++) { - for (j = temp; j < pmlmeext->max_chan_nums; j++) { - if (*(peer_ch_list + i) == pmlmeext->channel_set[j].ChannelNum) { + for (j = temp; j < rfctl->max_chan_nums; j++) { + if (*(peer_ch_list + i) == rfctl->channel_set[j].ChannelNum) { ch_list_inclusioned[ch_no++] = *(peer_ch_list + i); temp = j; break; @@ -2703,7 +2706,7 @@ u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt)) { peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list); - ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned); + ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned); if (ch_num_inclusioned == 0) { RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__); @@ -2803,8 +2806,6 @@ u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe u8 attr_content = 0x00; u32 attr_contentlen = 0; u8 operatingch_info[5] = { 0x00 }; - uint ch_cnt = 0; - u8 ch_content[100] = { 0x00 }; u8 groupid[38]; u16 cap_attr; u8 peer_ch_list[100] = { 0x00 }; @@ -2898,7 +2899,7 @@ u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe RTW_INFO("[%s] channel list attribute found, len = %d\n", __FUNCTION__, pwdinfo->channel_list_attr_len); peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list); - ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned); + ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned); if (ch_num_inclusioned == 0) { RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__); @@ -2970,7 +2971,9 @@ u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) { +#ifdef CONFIG_CONCURRENT_MODE _adapter *padapter = pwdinfo->padapter; +#endif u8 *ies; u32 ies_len; u8 *p2p_ie; @@ -3069,19 +3072,20 @@ void find_phase_handler(_adapter *padapter) { struct wifidirect_info *pwdinfo = &padapter->wdinfo; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - NDIS_802_11_SSID ssid; + struct sitesurvey_parm parm; _irqL irqL; u8 _status = 0; - _rtw_memset((unsigned char *)&ssid, 0, sizeof(NDIS_802_11_SSID)); - _rtw_memcpy(ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN); - ssid.SsidLength = P2P_WILDCARD_SSID_LEN; + rtw_init_sitesurvey_parm(padapter, &parm); + _rtw_memcpy(&parm.ssid[0].Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN); + parm.ssid[0].SsidLength = P2P_WILDCARD_SSID_LEN; + parm.ssid_num = 1; rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); _enter_critical_bh(&pmlmepriv->lock, &irqL); - _status = rtw_sitesurvey_cmd(padapter, &ssid, 1, NULL, 0); + _status = rtw_sitesurvey_cmd(padapter, &parm); _exit_critical_bh(&pmlmepriv->lock, &irqL); @@ -3092,8 +3096,6 @@ void p2p_concurrent_handler(_adapter *padapter); void restore_p2p_state_handler(_adapter *padapter) { struct wifidirect_info *pwdinfo = &padapter->wdinfo; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); @@ -3106,7 +3108,7 @@ void restore_p2p_state_handler(_adapter *padapter) if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP)) { set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); + rtw_back_opch(padapter); } } #endif @@ -3170,6 +3172,12 @@ void p2p_concurrent_handler(_adapter *padapter) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u8 val8; +#ifdef CONFIG_IOCTL_CFG80211 + if (pwdinfo->driver_interface == DRIVER_CFG80211 + && !rtw_cfg80211_get_is_roch(padapter)) + return; +#endif + if (rtw_mi_check_status(padapter, MI_LINKED)) { u8 union_ch = rtw_mi_get_union_chan(padapter); u8 union_bw = rtw_mi_get_union_bw(padapter); @@ -3178,10 +3186,10 @@ void p2p_concurrent_handler(_adapter *padapter) pwdinfo->operating_channel = union_ch; if (pwdinfo->driver_interface == DRIVER_CFG80211) { - RTW_INFO("%s, switch ch back to union_ch=%d\n", __func__, union_ch); + RTW_INFO("%s, switch ch back to union=%u,%u, %u\n" + , __func__, union_ch, union_bw, union_offset); set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - - rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); + rtw_back_opch(padapter); } else if (pwdinfo->driver_interface == DRIVER_WEXT) { if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) { @@ -3191,8 +3199,7 @@ void p2p_concurrent_handler(_adapter *padapter) RTW_INFO("[%s] P2P_STATE_IDLE, ext_listen_period = %d\n", __FUNCTION__, pwdinfo->ext_listen_period); if (union_ch != pwdinfo->listen_channel) { - /* Will switch to listen channel so that need to send the NULL data with PW bit to AP. */ - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); + rtw_leave_opch(padapter); set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); } @@ -3205,6 +3212,7 @@ void p2p_concurrent_handler(_adapter *padapter) /* Todo: To check the value of pwdinfo->ext_listen_period is equal to 0 or not. */ _set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period); } + } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL) || (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _FALSE) || @@ -3224,17 +3232,19 @@ void p2p_concurrent_handler(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); } rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE); - rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); + rtw_back_opch(padapter); } /* Todo: To check the value of pwdinfo->ext_listen_interval is equal to 0 or not. */ _set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval); + } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) { /* The driver had finished the P2P handshake successfully. */ val8 = 0; rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500); + rtw_back_opch(padapter); + } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) { val8 = 1; set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); @@ -3269,10 +3279,136 @@ void p2p_concurrent_handler(_adapter *padapter) #endif #ifdef CONFIG_IOCTL_CFG80211 +u8 roch_stay_in_cur_chan(_adapter *padapter) +{ + int i; + _adapter *iface; + struct mlme_priv *pmlmepriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u8 rst = _FALSE; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + pmlmepriv = &iface->mlmepriv; + + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE) == _TRUE) { + RTW_INFO(ADPT_FMT"- _FW_UNDER_LINKING |WIFI_UNDER_WPS | WIFI_UNDER_KEY_HANDSHAKE (mlme state:0x%x)\n", + ADPT_ARG(iface), get_fwstate(&iface->mlmepriv)); + rst = _TRUE; + break; + } + #ifdef CONFIG_AP_MODE + if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) { + if (rtw_ap_sta_states_check(iface) == _TRUE) { + rst = _TRUE; + break; + } + } + #endif + } + } + + return rst; +} + static int ro_ch_handler(_adapter *adapter, u8 *buf) { - /* TODO: move remain on channel logical here */ - return H2C_SUCCESS; + int ret = H2C_SUCCESS; + struct p2p_roch_parm *roch_parm = (struct p2p_roch_parm *)buf; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &adapter->cfg80211_wdinfo; +#ifdef CONFIG_CONCURRENT_MODE + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; +#ifdef RTW_ROCH_BACK_OP + struct wifidirect_info *pwdinfo = &adapter->wdinfo; +#endif +#endif + u8 ready_on_channel = _FALSE; + u8 remain_ch; + unsigned int duration; + + _enter_critical_mutex(&pwdev_priv->roch_mutex, NULL); + + if (rtw_cfg80211_get_is_roch(adapter) != _TRUE) + goto exit; + + remain_ch = (u8)ieee80211_frequency_to_channel(roch_parm->ch.center_freq); + duration = roch_parm->duration; + + RTW_INFO(FUNC_ADPT_FMT" ch:%u duration:%d, cookie:0x%llx\n" + , FUNC_ADPT_ARG(adapter), remain_ch, roch_parm->duration, roch_parm->cookie); + + if (roch_parm->wdev && roch_parm->cookie) { + if (pcfg80211_wdinfo->ro_ch_wdev != roch_parm->wdev) { + RTW_WARN(FUNC_ADPT_FMT" ongoing wdev:%p, wdev:%p\n" + , FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->ro_ch_wdev, roch_parm->wdev); + rtw_warn_on(1); + } + + if (pcfg80211_wdinfo->remain_on_ch_cookie != roch_parm->cookie) { + RTW_WARN(FUNC_ADPT_FMT" ongoing cookie:0x%llx, cookie:0x%llx\n" + , FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->remain_on_ch_cookie, roch_parm->cookie); + rtw_warn_on(1); + } + } + + if (roch_stay_in_cur_chan(adapter) == _TRUE) { + remain_ch = rtw_mi_get_union_chan(adapter); + RTW_INFO(FUNC_ADPT_FMT" stay in union ch:%d\n", FUNC_ADPT_ARG(adapter), remain_ch); + } + + #ifdef CONFIG_CONCURRENT_MODE + if (rtw_mi_check_status(adapter, MI_LINKED) && (0 != rtw_mi_get_union_chan(adapter))) { + if ((remain_ch != rtw_mi_get_union_chan(adapter)) && !check_fwstate(&adapter->mlmepriv, _FW_LINKED)) { + if (remain_ch != pmlmeext->cur_channel + #ifdef RTW_ROCH_BACK_OP + || ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1 + #endif + ) { + rtw_leave_opch(adapter); + + #ifdef RTW_ROCH_BACK_OP + RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, duration - pwdinfo->ext_listen_interval); + ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); + _set_timer(&pwdinfo->ap_p2p_switch_timer, duration - pwdinfo->ext_listen_interval); + #endif + } + } + ready_on_channel = _TRUE; + } else + #endif /* CONFIG_CONCURRENT_MODE */ + { + if (remain_ch != rtw_get_oper_ch(adapter)) + ready_on_channel = _TRUE; + } + + if (ready_on_channel == _TRUE) { + #ifndef RTW_SINGLE_WIPHY + if (!check_fwstate(&adapter->mlmepriv, _FW_LINKED)) + #endif + { + #ifdef CONFIG_CONCURRENT_MODE + if (rtw_get_oper_ch(adapter) != remain_ch) + #endif + { + /* if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) */ + set_channel_bwmode(adapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } + } + } + + #ifdef CONFIG_BT_COEXIST + rtw_btcoex_ScanNotify(adapter, _TRUE); + #endif + + RTW_INFO("%s, set ro ch timer, duration=%d\n", __func__, duration); + _set_timer(&pcfg80211_wdinfo->remain_on_ch_timer, duration); + +exit: + _exit_critical_mutex(&pwdev_priv->roch_mutex, NULL); + + return ret; } static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf) @@ -3304,6 +3440,11 @@ static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf) } } +#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE) + _cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer); + ATOMIC_SET(&pwdev_priv->switch_ch_to, 1); +#endif + if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) { if (0) RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", @@ -3325,6 +3466,7 @@ static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf) } set_channel_bwmode(padapter, ch, offset, bw); + rtw_back_opch(padapter); rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); #ifdef CONFIG_DEBUG_CFG80211 @@ -3335,7 +3477,7 @@ static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf) rtw_cfg80211_set_is_roch(padapter, _FALSE); pcfg80211_wdinfo->ro_ch_wdev = NULL; - pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); + rtw_cfg80211_set_last_ro_ch_time(padapter); rtw_cfg80211_remain_on_channel_expired(wdev , pcfg80211_wdinfo->remain_on_ch_cookie @@ -3355,14 +3497,14 @@ static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf) return ret; } -static void ro_ch_timer_process(struct timer_list *t) +static void ro_ch_timer_process(void *FunctionContext) { - struct cfg80211_wifidirect_info *pcfg80211_wdinfo = from_timer(pcfg80211_wdinfo, t, remain_on_ch_timer); - _adapter *adapter = container_of(pcfg80211_wdinfo, _adapter, cfg80211_wdinfo); + _adapter *adapter = (_adapter *)FunctionContext; p2p_cancel_roch_cmd(adapter, 0, NULL, 0); } +#if 0 static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch) { u8 *ies, *p2p_ie; @@ -3393,7 +3535,9 @@ static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); } } +#endif +#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) static void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch) { u8 *ies, *p2p_ie; @@ -3437,11 +3581,12 @@ static void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); } } +#endif +#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) static bool rtw_chk_p2pie_ch_list_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len) { bool fit = _FALSE; -#ifdef CONFIG_CONCURRENT_MODE u8 *ies, *p2p_ie; u32 ies_len, p2p_ielen; u8 union_ch = rtw_mi_get_union_chan(padapter); @@ -3483,14 +3628,14 @@ static bool rtw_chk_p2pie_ch_list_with_buddy(_adapter *padapter, const u8 *frame /* Get the next P2P IE */ p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); } -#endif + return fit; } +#if defined(CONFIG_P2P_INVITE_IOT) static bool rtw_chk_p2pie_op_ch_with_buddy(_adapter *padapter, const u8 *frame_body, u32 len) { bool fit = _FALSE; -#ifdef CONFIG_CONCURRENT_MODE u8 *ies, *p2p_ie; u32 ies_len, p2p_ielen; u8 union_ch = rtw_mi_get_union_chan(padapter); @@ -3519,13 +3664,13 @@ static bool rtw_chk_p2pie_op_ch_with_buddy(_adapter *padapter, const u8 *frame_b /* Get the next P2P IE */ p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); } -#endif + return fit; } +#endif static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *frame_body, u32 len) { -#ifdef CONFIG_CONCURRENT_MODE u8 *ies, *p2p_ie; u32 ies_len, p2p_ielen; u8 union_ch = rtw_mi_get_union_chan(padapter); @@ -3588,8 +3733,8 @@ static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *fram } -#endif } +#endif #ifdef CONFIG_WFD u32 rtw_xframe_build_wfd_ie(struct xmit_frame *xframe) @@ -3673,8 +3818,6 @@ u32 rtw_xframe_build_wfd_ie(struct xmit_frame *xframe) bool rtw_xframe_del_wfd_ie(struct xmit_frame *xframe) { #define DBG_XFRAME_DEL_WFD_IE 0 - - _adapter *adapter = xframe->padapter; u8 *frame = xframe->buf_addr + TXDESC_OFFSET; u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr); u8 *frame_tail = frame + xframe->attrib.pktlen; @@ -3721,12 +3864,9 @@ bool rtw_xframe_del_wfd_ie(struct xmit_frame *xframe) void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe) { _adapter *adapter = xframe->padapter; - u8 *frame = xframe->buf_addr + TXDESC_OFFSET; - u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr); - u8 *frame_tail = frame + xframe->attrib.pktlen; - +#ifdef CONFIG_IOCTL_CFG80211 struct wifidirect_info *wdinfo = &adapter->wdinfo; - struct mlme_priv *mlme = &adapter->mlmepriv; +#endif u8 build = 0; u8 del = 0; @@ -3734,7 +3874,7 @@ void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe) del = 1; #ifdef CONFIG_IOCTL_CFG80211 - if (_TRUE == wdinfo->wfd_info->wfd_enable) + if (wdinfo->wfd_info->wfd_enable == _TRUE) #endif del = build = 1; @@ -3754,7 +3894,6 @@ u8 *dump_p2p_attr_ch_list(u8 *p2p_ie, uint p2p_ielen, u8 *buf, u32 buf_len) int w_sz = 0; u8 ch_cnt = 0; u8 ch_list[40]; - bool continuous = _FALSE; pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, &attr_contentlen); if (pattr != NULL) { @@ -4057,10 +4196,13 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) if (!tx) { #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { + #if defined(CONFIG_P2P_INVITE_IOT) if (op_ch != -1 && rtw_chk_p2pie_op_ch_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) { RTW_INFO(FUNC_ADPT_FMT" op_ch:%u has no intersect with buddy\n", FUNC_ADPT_ARG(padapter), op_ch); rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0); - } else if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) { + } else + #endif + if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) { RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter)); rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0); } @@ -4176,24 +4318,23 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) switch (OUI_Subtype) { case P2P_NOTICE_OF_ABSENCE: - RTW_INFO("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken); + RTW_INFO("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken); break; case P2P_PRESENCE_REQUEST: - RTW_INFO("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken); + RTW_INFO("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken); break; case P2P_PRESENCE_RESPONSE: - RTW_INFO("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken); + RTW_INFO("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken); break; case P2P_GO_DISC_REQUEST: - RTW_INFO("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken); + RTW_INFO("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken); break; default: - RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", OUI_Subtype, dialogToken); + RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", OUI_Subtype, dialogToken); break; } - } else - RTW_INFO("RTW_%s:action frame category=%d\n", (tx == _TRUE) ? "TX" : "RX", category); + } return is_p2p_frame; } @@ -4204,14 +4345,13 @@ void rtw_init_cfg80211_wifidirect_info(_adapter *padapter) _rtw_memset(pcfg80211_wdinfo, 0x00, sizeof(struct cfg80211_wifidirect_info)); - rtw_init_timer(&pcfg80211_wdinfo->remain_on_ch_timer, padapter, ro_ch_timer_process); + rtw_init_timer(&pcfg80211_wdinfo->remain_on_ch_timer, padapter, ro_ch_timer_process, padapter); } #endif /* CONFIG_IOCTL_CFG80211 */ s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf) { int ret = H2C_SUCCESS; - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); switch (intCmdType) { case P2P_FIND_PHASE_WK: @@ -4288,7 +4428,6 @@ int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength) u8 p2p_attr[MAX_P2P_IE_LEN] = { 0x00 };/* NoA length should be n*(13) + 2 */ u32 attr_contentlen = 0; - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); if (IELength <= _BEACON_IE_OFFSET_) @@ -4411,7 +4550,7 @@ void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - + u32 ps_deny = 0; /* Pre action for p2p state */ switch (p2p_ps_state) { @@ -4433,6 +4572,16 @@ void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) } break; case P2P_PS_ENABLE: + _enter_pwrlock(&adapter_to_pwrctl(padapter)->lock); + ps_deny = rtw_ps_deny_get(padapter); + _exit_pwrlock(&adapter_to_pwrctl(padapter)->lock); + + if ((ps_deny & (PS_DENY_SCAN | PS_DENY_JOIN)) + || rtw_mi_check_fwstate(padapter, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING))) { + pwdinfo->p2p_ps_mode = P2P_PS_NONE; + RTW_DBG(FUNC_ADPT_FMT" Block P2P PS under site survey or LINKING\n", FUNC_ADPT_ARG(padapter)); + return; + } if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) { #ifdef CONFIG_MCC_MODE if (MCC_EN(padapter)) { @@ -4467,6 +4616,9 @@ void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) break; } +#ifdef CONFIG_MCC_MODE + rtw_hal_mcc_process_noa(padapter); +#endif /* CONFIG_MCC_MODE */ } u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue) @@ -4520,9 +4672,10 @@ u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue) } #endif /* CONFIG_P2P_PS */ -static void __reset_ch_sitesurvey_timer_process(struct wifidirect_info *pwdinfo) +static void reset_ch_sitesurvey_timer_process(void *FunctionContext) { - _adapter *adapter = container_of(pwdinfo, _adapter, wdinfo); + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) return; @@ -4538,15 +4691,10 @@ static void __reset_ch_sitesurvey_timer_process(struct wifidirect_info *pwdinfo) pwdinfo->rx_invitereq_info.scan_op_ch_only = 0; } -static void reset_ch_sitesurvey_timer_process(struct timer_list *t) +static void reset_ch_sitesurvey_timer_process2(void *FunctionContext) { - struct wifidirect_info *pwdinfo = from_timer(pwdinfo, t, reset_ch_sitesurvey); - __reset_ch_sitesurvey_timer_process(pwdinfo); -} - -static void __reset_ch_sitesurvey_timer_process2(struct wifidirect_info *pwdinfo) -{ - _adapter *adapter = container_of(pwdinfo, _adapter, wdinfo); + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) return; @@ -4562,16 +4710,10 @@ static void __reset_ch_sitesurvey_timer_process2(struct wifidirect_info *pwdinfo pwdinfo->p2p_info.scan_op_ch_only = 0; } -static void reset_ch_sitesurvey_timer_process2(struct timer_list *t) +static void restore_p2p_state_timer_process(void *FunctionContext) { - struct wifidirect_info *pwdinfo = from_timer(pwdinfo, t, reset_ch_sitesurvey2); - __reset_ch_sitesurvey_timer_process2(pwdinfo); -} - -static void restore_p2p_state_timer_process(struct timer_list *t) -{ - struct wifidirect_info *pwdinfo = from_timer(pwdinfo, t, restore_p2p_state_timer); - _adapter *adapter = container_of(pwdinfo, _adapter, wdinfo); + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) return; @@ -4579,13 +4721,12 @@ static void restore_p2p_state_timer_process(struct timer_list *t) p2p_protocol_wk_cmd(adapter, P2P_RESTORE_STATE_WK); } -static void pre_tx_scan_timer_process(struct timer_list *t) +static void pre_tx_scan_timer_process(void *FunctionContext) { - struct wifidirect_info *pwdinfo = from_timer(pwdinfo, t, pre_tx_scan_timer); - _adapter *adapter = container_of(pwdinfo, _adapter, wdinfo); + _adapter *adapter = (_adapter *) FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; _irqL irqL; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - u8 _status = 0; if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) return; @@ -4611,10 +4752,10 @@ static void pre_tx_scan_timer_process(struct timer_list *t) _exit_critical_bh(&pmlmepriv->lock, &irqL); } -static void find_phase_timer_process(struct timer_list *t) +static void find_phase_timer_process(void *FunctionContext) { - struct wifidirect_info *pwdinfo = from_timer(pwdinfo, t, find_phase_timer); - _adapter *adapter = container_of(pwdinfo, _adapter, wdinfo); + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) return; @@ -4870,11 +5011,11 @@ void rtw_init_wifidirect_timers(_adapter *padapter) { struct wifidirect_info *pwdinfo = &padapter->wdinfo; - rtw_init_timer(&pwdinfo->find_phase_timer, padapter, find_phase_timer_process); - rtw_init_timer(&pwdinfo->restore_p2p_state_timer, padapter, restore_p2p_state_timer_process); - rtw_init_timer(&pwdinfo->pre_tx_scan_timer, padapter, pre_tx_scan_timer_process); - rtw_init_timer(&pwdinfo->reset_ch_sitesurvey, padapter, reset_ch_sitesurvey_timer_process); - rtw_init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter, reset_ch_sitesurvey_timer_process2); + rtw_init_timer(&pwdinfo->find_phase_timer, padapter, find_phase_timer_process, padapter); + rtw_init_timer(&pwdinfo->restore_p2p_state_timer, padapter, restore_p2p_state_timer_process, padapter); + rtw_init_timer(&pwdinfo->pre_tx_scan_timer, padapter, pre_tx_scan_timer_process, padapter); + rtw_init_timer(&pwdinfo->reset_ch_sitesurvey, padapter, reset_ch_sitesurvey_timer_process, padapter); + rtw_init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter, reset_ch_sitesurvey_timer_process2, padapter); #ifdef CONFIG_CONCURRENT_MODE rtw_init_timer(&pwdinfo->ap_p2p_switch_timer, padapter, ap_p2p_switch_timer_process, padapter); #endif @@ -4899,7 +5040,6 @@ void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role) #ifdef CONFIG_WFD struct wifi_display_info *pwfd_info = &padapter->wfd_info; #endif - u8 union_ch = 0; pwdinfo = &padapter->wdinfo; pwdinfo->padapter = padapter; @@ -4914,6 +5054,8 @@ void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role) && pwdinfo->driver_interface != DRIVER_CFG80211 ) { #ifdef CONFIG_CONCURRENT_MODE + u8 union_ch = 0; + if (rtw_mi_check_status(padapter, MI_LINKED)) union_ch = rtw_mi_get_union_chan(padapter); @@ -5049,6 +5191,14 @@ void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role) pwdinfo->p2p_info.scan_op_ch_only = 0; } +void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) +{ + if (wdinfo->role != role) { + wdinfo->role = role; + rtw_mi_update_iface_status(&(wdinfo->padapter->mlmepriv), 0); + } +} + #ifdef CONFIG_DBG_P2P /** @@ -5197,9 +5347,6 @@ int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) struct wifidirect_info *pwdinfo = &(padapter->wdinfo); if (role == P2P_ROLE_DEVICE || role == P2P_ROLE_CLIENT || role == P2P_ROLE_GO) { - u8 channel, ch_offset; - u16 bwmode; - #if defined(CONFIG_CONCURRENT_MODE) && (!defined(RTW_P2P_GROUP_INTERFACE) || !RTW_P2P_GROUP_INTERFACE) /* Commented by Albert 2011/12/30 */ /* The driver just supports 1 P2P group operation. */ @@ -5259,8 +5406,8 @@ int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) _cancel_timer_ex(&pwdinfo->pre_tx_scan_timer); _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey2); - __reset_ch_sitesurvey_timer_process(pwdinfo); - __reset_ch_sitesurvey_timer_process2(pwdinfo); + reset_ch_sitesurvey_timer_process(padapter); + reset_ch_sitesurvey_timer_process2(padapter); #ifdef CONFIG_CONCURRENT_MODE _cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer); #endif diff --git a/core/rtw_pwrctrl.c b/core/rtw_pwrctrl.c index 3676b4c..e287c64 100644 --- a/core/rtw_pwrctrl.c +++ b/core/rtw_pwrctrl.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,25 +11,20 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_PWRCTRL_C_ #include #include #include +#ifdef DBG_CHECK_FW_PS_STATE int rtw_fw_ps_state(PADAPTER padapter) { struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; int ret = _FAIL, dont_care = 0; u16 fw_ps_state = 0; - u32 start_time; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct registry_priv *registry_par = &padapter->registrypriv; @@ -45,6 +40,15 @@ int rtw_fw_ps_state(PADAPTER padapter) , rtw_is_drv_stopped(padapter) ? "True" : "False"); goto exit_fw_ps_state; } + #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) + rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state); + if ((fw_ps_state & BIT_LPS_STATUS) == 0) + ret = _SUCCESS; + else { + pdbgpriv->dbg_poll_fail_cnt++; + RTW_INFO("%s: fw_ps_state=%04x\n", __FUNCTION__, fw_ps_state); + } + #else rtw_hal_set_hwreg(padapter, HW_VAR_SET_REQ_FW_PS, (u8 *)&dont_care); { /* 4. if 0x88[7]=1, driver set cmd to leave LPS/IPS. */ @@ -63,13 +67,13 @@ int rtw_fw_ps_state(PADAPTER padapter) RTW_INFO("%s: fw_ps_state=%04x\n", __FUNCTION__, fw_ps_state); } } - + #endif exit_fw_ps_state: _exit_pwrlock(&pwrpriv->check_32k_lock); return ret; } - +#endif /*DBG_CHECK_FW_PS_STATE*/ #ifdef CONFIG_IPS void _ips_enter(_adapter *padapter) { @@ -90,6 +94,10 @@ void _ips_enter(_adapter *padapter) if (pwrpriv->ips_mode == IPS_LEVEL_2) pwrpriv->bkeepfwalive = _TRUE; +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + pwrpriv->pwr_saving_start_time = rtw_get_current_time(); +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + rtw_ips_pwr_down(padapter); pwrpriv->rf_pwrstate = rf_off; } @@ -125,6 +133,11 @@ int _ips_leave(_adapter *padapter) result = rtw_ips_pwr_up(padapter); if (result == _SUCCESS) pwrpriv->rf_pwrstate = rf_on; + +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time); +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + RTW_PRINT("nolinked power save leave\n"); RTW_INFO("==> ips_leave.....LED(0x%08x)...\n", rtw_read32(padapter, 0x4c)); @@ -140,8 +153,10 @@ int _ips_leave(_adapter *padapter) int ips_leave(_adapter *padapter) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); +#ifdef DBG_CHECK_FW_PS_STATE struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; +#endif int ret; if (!is_primary_adapter(padapter)) @@ -188,9 +203,6 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) struct mlme_priv *pmlmepriv; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo; -#ifdef CONFIG_IOCTL_CFG80211 - struct cfg80211_wifidirect_info *pcfg80211_wdinfo; -#endif #endif bool ret = _FALSE; @@ -200,7 +212,7 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) goto exit; } - if (adapter_to_pwrctl(adapter)->ips_deny_time >= rtw_get_current_time()) { + if (rtw_time_after(adapter_to_pwrctl(adapter)->ips_deny_time, rtw_get_current_time())) { /* RTW_INFO("%s ips_deny_time\n", __func__); */ goto exit; } @@ -211,24 +223,21 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) pmlmepriv = &(iface->mlmepriv); #ifdef CONFIG_P2P pwdinfo = &(iface->wdinfo); -#ifdef CONFIG_IOCTL_CFG80211 - pcfg80211_wdinfo = &iface->cfg80211_wdinfo; -#endif #endif if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_SITE_MONITOR) - || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) - || check_fwstate(pmlmepriv, WIFI_AP_STATE) - || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) -#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) - || rtw_cfg80211_get_is_roch(iface) == _TRUE -#elif defined(CONFIG_P2P) - || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) - || rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) -#endif -#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) - || rtw_get_passing_time_ms(pcfg80211_wdinfo->last_ro_ch_time) < 3000 -#endif - ) + || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) + || MLME_IS_AP(iface) + || MLME_IS_MESH(iface) + || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) + #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) + || rtw_cfg80211_get_is_roch(iface) == _TRUE + || (rtw_cfg80211_is_ro_ch_once(adapter) + && rtw_cfg80211_get_last_ro_ch_passing_ms(adapter) < 3000) + #elif defined(CONFIG_P2P) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) + #endif + ) goto exit; } @@ -265,9 +274,6 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter) */ void rtw_ps_processor(_adapter *padapter) { -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#endif /* CONFIG_P2P */ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct dvobj_priv *psdpriv = padapter->dvobj; @@ -393,19 +399,77 @@ void rtw_ps_processor(_adapter *padapter) return; } -void pwr_state_check_handler(struct timer_list *t) +void pwr_state_check_handler(void *ctx) { - struct pwrctrl_priv *pwrpriv = from_timer(pwrpriv, t, pwr_state_check_timer); - struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); - _adapter *padapter = dvobj_get_primary_adapter(dvobj); + _adapter *padapter = (_adapter *)ctx; rtw_ps_cmd(padapter); } #ifdef CONFIG_LPS +#ifdef CONFIG_CHECK_LEAVE_LPS +#ifdef CONFIG_LPS_CHK_BY_TP +void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta) +{ + struct stainfo_stats *pstats = &sta->sta_stats; + u64 cur_acc_tx_bytes = 0, cur_acc_rx_bytes = 0; + u32 tx_tp_kbyte = 0, rx_tp_kbyte = 0; + u32 tx_tp_th = 0, rx_tp_th = 0; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + u8 leave_lps = _FALSE; + + if (tx) { /* from tx */ + cur_acc_tx_bytes = pstats->tx_bytes - pstats->acc_tx_bytes; + tx_tp_kbyte = cur_acc_tx_bytes >> 10; + tx_tp_th = pwrpriv->lps_tx_tp_th * 1024 / 8 * 2; /*KBytes @2s*/ + + if (tx_tp_kbyte >= tx_tp_th || + padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod >= pwrpriv->lps_tx_pkts){ + if (pwrpriv->bLeisurePs + && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) + #ifdef CONFIG_BT_COEXIST + && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE) + #endif + ) { + leave_lps = _TRUE; + } + } + + } else { /* from rx path */ + cur_acc_rx_bytes = pstats->rx_bytes - pstats->acc_rx_bytes; + rx_tp_kbyte = cur_acc_rx_bytes >> 10; + rx_tp_th = pwrpriv->lps_rx_tp_th * 1024 / 8 * 2; + + if (rx_tp_kbyte>= rx_tp_th || + padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod >= pwrpriv->lps_rx_pkts) { + if (pwrpriv->bLeisurePs + && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) + #ifdef CONFIG_BT_COEXIST + && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE) + #endif + ) { + leave_lps = _TRUE; + } + } + } + + if (leave_lps) { + #ifdef DBG_LPS_CHK_BY_TP + RTW_INFO("leave lps via %s, ", tx ? "Tx" : "Rx"); + if (tx) + RTW_INFO("Tx = %d [%d] (KB)\n", tx_tp_kbyte, tx_tp_th); + else + RTW_INFO("Rx = %d [%d] (KB)\n", rx_tp_kbyte, rx_tp_th); + #endif + pwrpriv->lps_chk_cnt = pwrpriv->lps_chk_cnt_th; + /* rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); */ + rtw_lps_ctrl_wk_cmd(padapter, tx ? LPS_CTRL_TX_TRAFFIC_LEAVE : LPS_CTRL_RX_TRAFFIC_LEAVE, 1); + } +} +#endif /*CONFIG_LPS_CHK_BY_TP*/ + void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets) { -#ifdef CONFIG_CHECK_LEAVE_LPS - static u32 start_time = 0; + static systime start_time = 0; static u32 xmit_cnt = 0; u8 bLeaveLPS = _FALSE; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -454,62 +518,76 @@ void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets) /* rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); */ rtw_lps_ctrl_wk_cmd(padapter, tx ? LPS_CTRL_TX_TRAFFIC_LEAVE : LPS_CTRL_RX_TRAFFIC_LEAVE, tx ? 0 : 1); } -#endif /* CONFIG_CHECK_LEAVE_LPS */ } +#endif /* CONFIG_CHECK_LEAVE_LPS */ #ifdef CONFIG_LPS_LCLK -u8 rtw_cpwm_polling(_adapter *adapter, u8 cpwm_orig) +#define LPS_CPWM_TIMEOUT_MS 10 /*ms*/ +#define LPS_RPWM_RETRY_CNT 3 + +u8 rtw_cpwm_polling(_adapter *adapter, u8 rpwm, u8 cpwm_orig) { - u8 result = _FAIL; - u8 cpwm_now; - u8 poll_cnt = 0; - u32 start_time; + u8 rst = _FAIL; + u8 cpwm_now = 0; + systime start_time; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + #ifdef DBG_CHECK_FW_PS_STATE struct debug_priv *pdbgpriv = &(adapter_to_dvobj(adapter)->drv_dbg); + #endif - /*RTW_INFO("%s.....\n", __func__);*/ - - start_time = rtw_get_current_time(); + pwrpriv->rpwm_retry = 0; - /* polling cpwm */ do { - rtw_msleep_os(1); - poll_cnt++; - cpwm_now = 0; - rtw_hal_get_hwreg(adapter, HW_VAR_CPWM, &cpwm_now); - - if ((cpwm_orig ^ cpwm_now) & 0x80) { - pwrpriv->cpwm = PS_STATE_S4; - pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE; - #ifdef DBG_CHECK_FW_PS_STATE - RTW_INFO("%s: polling cpwm OK! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\n" - , __func__, poll_cnt, cpwm_orig, cpwm_now, rtw_read8(adapter, REG_CR)); - if (rtw_fw_ps_state(adapter) == _FAIL) { - RTW_INFO("leave 32k but fw state in 32k\n"); - pdbgpriv->dbg_rpwm_toogle_cnt++; - } - #endif /* DBG_CHECK_FW_PS_STATE */ - result = _SUCCESS; - break; - } + start_time = rtw_get_current_time(); + do { + rtw_msleep_os(1); + rtw_hal_get_hwreg(adapter, HW_VAR_CPWM, &cpwm_now); - if (rtw_get_passing_time_ms(start_time) > LPS_RPWM_WAIT_MS) { - RTW_ERR("%s: polling cpwm timeout! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x\n" - , __func__, poll_cnt, cpwm_orig, cpwm_now); - #ifdef DBG_CHECK_FW_PS_STATE - if (rtw_fw_ps_state(adapter) == _FAIL) { - RTW_INFO("rpwm timeout and fw ps state in 32k\n"); - pdbgpriv->dbg_rpwm_timeout_fail_cnt++; + if ((cpwm_orig ^ cpwm_now) & 0x80) { + pwrpriv->cpwm = PS_STATE_S4; + pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE; + rst = _SUCCESS; + break; } - #endif /* DBG_CHECK_FW_PS_STATE */ + } while (rtw_get_passing_time_ms(start_time) < LPS_CPWM_TIMEOUT_MS && !RTW_CANNOT_RUN(adapter)); - #ifdef CONFIG_LPS_RPWM_TIMER - _set_timer(&pwrpriv->pwr_rpwm_timer, 1); - #endif /* CONFIG_LPS_RPWM_TIMER */ + if (rst == _SUCCESS) break; + else { + /* rpwm retry */ + cpwm_orig = cpwm_now; + rpwm &= ~PS_TOGGLE; + rpwm |= pwrpriv->tog; + rtw_hal_set_hwreg(adapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm)); + pwrpriv->tog += 0x80; } - } while (1); - return result; + } while (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT && !RTW_CANNOT_RUN(adapter)); + + if (rst == _SUCCESS) { + #ifdef DBG_CHECK_FW_PS_STATE + RTW_INFO("%s: polling cpwm OK! rpwm_retry=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\n" + , __func__, pwrpriv->rpwm_retry, cpwm_orig, cpwm_now, rtw_read8(adapter, REG_CR)); + if (rtw_fw_ps_state(adapter) == _FAIL) { + RTW_INFO("leave 32k but fw state in 32k\n"); + pdbgpriv->dbg_rpwm_toogle_cnt++; + } + #endif /* DBG_CHECK_FW_PS_STATE */ + } else { + RTW_ERR("%s: polling cpwm timeout! rpwm_retry=%d, cpwm_orig=%02x, cpwm_now=%02x\n" + , __func__, pwrpriv->rpwm_retry, cpwm_orig, cpwm_now); + #ifdef DBG_CHECK_FW_PS_STATE + if (rtw_fw_ps_state(adapter) == _FAIL) { + RTW_INFO("rpwm timeout and fw ps state in 32k\n"); + pdbgpriv->dbg_rpwm_timeout_fail_cnt++; + } + #endif /* DBG_CHECK_FW_PS_STATE */ + + #ifdef CONFIG_LPS_RPWM_TIMER + _set_timer(&pwrpriv->pwr_rpwm_timer, 1); + #endif /* CONFIG_LPS_RPWM_TIMER */ + } + + return rst; } #endif /* @@ -521,15 +599,13 @@ u8 rtw_cpwm_polling(_adapter *adapter, u8 cpwm_orig) * pslv power state level, only could be PS_STATE_S0 ~ PS_STATE_S4 * */ -void rtw_set_rpwm(PADAPTER padapter, u8 pslv) +u8 rtw_set_rpwm(PADAPTER padapter, u8 pslv) { - u8 rpwm; + u8 rpwm = 0xFF; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); #ifdef CONFIG_LPS_LCLK u8 cpwm_orig; #endif - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; pslv = PS_STATE(pslv); @@ -545,7 +621,7 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv) #endif || (pwrpriv->lps_level == LPS_NORMAL) ) { - return; + return rpwm; } } @@ -554,12 +630,12 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv) pwrpriv->cpwm = PS_STATE_S4; - return; + return rpwm; } if (rtw_is_drv_stopped(padapter)) if (pslv < PS_STATE_S2) - return; + return rpwm; rpwm = pslv | pwrpriv->tog; #ifdef CONFIG_LPS_LCLK @@ -577,9 +653,16 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv) #endif #if defined(CONFIG_LPS_RPWM_TIMER) && !defined(CONFIG_DETECT_CPWM_BY_POLLING) - if (rpwm & PS_ACK) - _set_timer(&pwrpriv->pwr_rpwm_timer, LPS_RPWM_WAIT_MS); + if (rpwm & PS_ACK) { + #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN) + if (pwrpriv->wowlan_mode != _TRUE && + pwrpriv->wowlan_ap_mode != _TRUE && + pwrpriv->wowlan_p2p_mode != _TRUE) + #endif + _set_timer(&pwrpriv->pwr_rpwm_timer, LPS_CPWM_TIMEOUT_MS); + } #endif /* CONFIG_LPS_RPWM_TIMER & !CONFIG_DETECT_CPWM_BY_POLLING */ + rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm)); pwrpriv->tog += 0x80; @@ -587,14 +670,14 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv) #ifdef CONFIG_LPS_LCLK /* No LPS 32K, No Ack */ if (rpwm & PS_ACK) { -#ifdef CONFIG_DETECT_CPWM_BY_POLLING - rtw_cpwm_polling(padapter, cpwm_orig); + #ifdef CONFIG_DETECT_CPWM_BY_POLLING + rtw_cpwm_polling(padapter, rpwm, cpwm_orig); #else #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN) if (pwrpriv->wowlan_mode == _TRUE || pwrpriv->wowlan_ap_mode == _TRUE || pwrpriv->wowlan_p2p_mode == _TRUE) - rtw_cpwm_polling(padapter, cpwm_orig); + rtw_cpwm_polling(padapter, rpwm, cpwm_orig); #endif /*#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)*/ #endif /*#ifdef CONFIG_DETECT_CPWM_BY_POLLING*/ } else @@ -603,19 +686,14 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv) pwrpriv->cpwm = pslv; } + return rpwm; } u8 PS_RDY_CHECK(_adapter *padapter) { - u32 curr_time, delta_time; + u32 delta_ms; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); -#ifdef CONFIG_IOCTL_CFG80211 - struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; -#endif /* CONFIG_IOCTL_CFG80211 */ -#endif /* CONFIG_P2P */ #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) if (_TRUE == pwrpriv->bInSuspend && pwrpriv->wowlan_mode) @@ -629,26 +707,27 @@ u8 PS_RDY_CHECK(_adapter *padapter) return _FALSE; #endif - curr_time = rtw_get_current_time(); - - delta_time = curr_time - pwrpriv->DelayLPSLastTimeStamp; - - if (delta_time < LPS_DELAY_TIME) + delta_ms = rtw_get_passing_time_ms(pwrpriv->DelayLPSLastTimeStamp); + if (delta_ms < LPS_DELAY_MS) return _FALSE; if (check_fwstate(pmlmepriv, WIFI_SITE_MONITOR) - || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) - || check_fwstate(pmlmepriv, WIFI_AP_STATE) - || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) -#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) - || rtw_cfg80211_get_is_roch(padapter) == _TRUE -#endif - || rtw_is_scan_deny(padapter) -#ifdef CONFIG_TDLS - /* TDLS link is established. */ - || (padapter->tdlsinfo.link_established == _TRUE) -#endif /* CONFIG_TDLS */ - ) + || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) + || MLME_IS_AP(padapter) + || MLME_IS_MESH(padapter) + || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) + #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) + || rtw_cfg80211_get_is_roch(padapter) == _TRUE + #endif + || rtw_is_scan_deny(padapter) + #ifdef CONFIG_TDLS + /* TDLS link is established. */ + || (padapter->tdlsinfo.link_established == _TRUE) + #endif /* CONFIG_TDLS */ + #ifdef CONFIG_DFS_MASTER + || adapter_to_rfctl(padapter)->radar_detect_enabled + #endif + ) return _FALSE; if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE)) { @@ -669,7 +748,7 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); int cnt = 0; - u32 start_time; + systime start_time; u8 val8 = 0; u8 cpwm_orig = 0, cpwm_now = 0; u8 parm[H2C_INACTIVE_PS_LEN] = {0}; @@ -783,8 +862,13 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable) void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN) struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; +#endif +#ifdef CONFIG_WMMPS_STA + struct registry_priv *pregistrypriv = &padapter->registrypriv; +#endif #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif /* CONFIG_P2P */ @@ -810,9 +894,12 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode return; #ifndef CONFIG_BT_COEXIST - if ((pwrpriv->smart_ps == smart_ps) && - (pwrpriv->bcn_ant_mode == bcn_ant_mode)) - return; +#ifdef CONFIG_WMMPS_STA + if (!rtw_is_wmmps_mode(padapter)) +#endif /* CONFIG_WMMPS_STA */ + if ((pwrpriv->smart_ps == smart_ps) && + (pwrpriv->bcn_ant_mode == bcn_ant_mode)) + return; #endif /* !CONFIG_BT_COEXIST */ } @@ -869,7 +956,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 0, 0, 0); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0); plist = get_next(plist); } } @@ -882,7 +969,8 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode if (pwrpriv->wowlan_mode == _TRUE || pwrpriv->wowlan_ap_mode == _TRUE || pwrpriv->wowlan_p2p_mode == _TRUE) { - u32 start_time, delay_ms; + systime start_time; + u32 delay_ms; u8 val8; delay_ms = 20; start_time = rtw_get_current_time(); @@ -909,10 +997,11 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode } #endif rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); + rtw_hal_set_hwreg(padapter, HW_VAR_LPS_STATE_CHK, (u8 *)(&ps_mode)); #ifdef CONFIG_LPS_PG if (pwrpriv->lps_level == LPS_PG) { - lps_pg_hdl_id = LPS_PG_RESEND_H2C; + lps_pg_hdl_id = LPS_PG_PHYDM_EN; rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id)); } #endif @@ -956,7 +1045,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 1, 0, 0); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 0, 0); plist = get_next(plist); } } @@ -975,6 +1064,17 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode pwrpriv->pwr_mode = ps_mode; pwrpriv->smart_ps = smart_ps; pwrpriv->bcn_ant_mode = bcn_ant_mode; +#ifdef CONFIG_LPS_PG + if (pwrpriv->lps_level == LPS_PG) { + lps_pg_hdl_id = LPS_PG_PHYDM_DIS; + rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id)); + } +#endif + +#ifdef CONFIG_WMMPS_STA + pwrpriv->wmm_smart_ps = pregistrypriv->wmm_smart_ps; +#endif /* CONFIG_WMMPS_STA */ + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); #ifdef CONFIG_P2P_PS @@ -1019,7 +1119,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode */ s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms) { - u32 start_time; + systime start_time; u8 bAwake = _FALSE; s32 err = 0; @@ -1055,14 +1155,14 @@ void LPS_Enter(PADAPTER padapter, const char *msg) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - int n_assoc_iface = 0; int i; char buf[32] = {0}; - +#ifdef DBG_LA_MODE + struct registry_priv *registry_par = &(padapter->registrypriv); +#endif /* RTW_INFO("+LeisurePSEnter\n"); */ - if (_FALSE == padapter->bFWReady) + if (GET_HAL_DATA(padapter)->bFWReady == _FALSE) return; #ifdef CONFIG_BT_COEXIST @@ -1070,12 +1170,14 @@ void LPS_Enter(PADAPTER padapter, const char *msg) return; #endif - /* Skip lps enter request if number of assocated adapters is not 1 */ - for (i = 0; i < dvobj->iface_nums; i++) { - if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE)) - n_assoc_iface++; +#ifdef DBG_LA_MODE + if(registry_par->la_mode_en == 1) { + RTW_INFO("%s LA debug mode lps_leave \n", __func__); + return; } - if (n_assoc_iface != 1) +#endif + /* Skip lps enter request if number of assocated adapters is not 1 */ + if (rtw_mi_get_assoc_if_num(padapter) != 1) return; #ifndef CONFIG_FW_MULTI_PORT_SUPPORT @@ -1089,6 +1191,14 @@ void LPS_Enter(PADAPTER padapter, const char *msg) return; } +#ifdef CONFIG_CLIENT_PORT_CFG + if ((rtw_hal_get_port(padapter) == CLT_PORT_INVALID) || + get_clt_num(padapter) > MAX_CLIENT_PORT_NUM){ + RTW_ERR(ADPT_FMT" cannot get client port or clt num(%d) over than 4\n", ADPT_ARG(padapter), get_clt_num(padapter)); + return; + } +#endif + #ifdef CONFIG_P2P_PS if (padapter->wdinfo.p2p_ps_mode == P2P_PS_NOA) { return;/* supporting p2p client ps NOA via H2C_8723B_P2P_PS_OFFLOAD */ @@ -1099,8 +1209,19 @@ void LPS_Enter(PADAPTER padapter, const char *msg) /* Idle for a while if we connect to AP a while ago. */ if (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */ if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) { + +#ifdef CONFIG_WMMPS_STA + if (rtw_is_wmmps_mode(padapter)) + msg = "WMMPS_IDLE"; +#endif /* CONFIG_WMMPS_STA */ + sprintf(buf, "WIFI-%s", msg); pwrpriv->bpower_saving = _TRUE; + +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + pwrpriv->pwr_saving_start_time = rtw_get_current_time(); +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + rtw_set_ps_mode(padapter, pwrpriv->power_mgnt, padapter->registrypriv.smart_ps, 0, buf); } } else @@ -1121,10 +1242,10 @@ void LPS_Leave(PADAPTER padapter, const char *msg) struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - u32 start_time; - u8 bAwake = _FALSE; char buf[32] = {0}; +#ifdef DBG_CHECK_FW_PS_STATE struct debug_priv *pdbgpriv = &dvobj->drv_dbg; +#endif /* RTW_INFO("+LeisurePSLeave\n"); */ @@ -1136,9 +1257,19 @@ void LPS_Leave(PADAPTER padapter, const char *msg) if (pwrpriv->bLeisurePs) { if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) { + +#ifdef CONFIG_WMMPS_STA + if (rtw_is_wmmps_mode(padapter)) + msg = "WMMPS_BUSY"; +#endif /* CONFIG_WMMPS_STA */ + sprintf(buf, "WIFI-%s", msg); rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, buf); +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time); +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) LPS_RF_ON_check(padapter, LPS_LEAVE_TIMEOUT_MS); } @@ -1154,20 +1285,32 @@ void LPS_Leave(PADAPTER padapter, const char *msg) * RTW_INFO("-LeisurePSLeave\n"); */ } + +void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en) +{ +#if defined(CONFIG_USB_HCI) && defined(CONFIG_LPS_LCLK) + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + + if (wow_en) { + pwrpriv->lps_level_bk = pwrpriv->lps_level; + pwrpriv->lps_level = LPS_LCLK; + } else + pwrpriv->lps_level = pwrpriv->lps_level_bk; +#endif +} #endif void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) { PADAPTER pri_padapter = GET_PRIMARY_ADAPTER(Adapter); - struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); - struct dvobj_priv *psdpriv = Adapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; +#ifdef CONFIG_LPS_LCLK #ifndef CONFIG_DETECT_CPWM_BY_POLLING - u8 cpwm_orig, cpwm_now; - u32 start_time; + u8 cpwm_orig; #endif /* CONFIG_DETECT_CPWM_BY_POLLING */ - + u8 rpwm; +#endif RTW_INFO("%s.....\n", __FUNCTION__); @@ -1190,46 +1333,15 @@ void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) cpwm_orig = 0; rtw_hal_get_hwreg(Adapter, HW_VAR_CPWM, &cpwm_orig); #endif /* CONFIG_DETECT_CPWM_BY_POLLING */ - rtw_set_rpwm(Adapter, PS_STATE_S4); + rpwm = rtw_set_rpwm(Adapter, PS_STATE_S4); #ifndef CONFIG_DETECT_CPWM_BY_POLLING - - start_time = rtw_get_current_time(); - - /* polling cpwm */ - do { - rtw_mdelay_os(1); - - rtw_hal_get_hwreg(Adapter, HW_VAR_CPWM, &cpwm_now); - if ((cpwm_orig ^ cpwm_now) & 0x80) { - pwrpriv->cpwm = PS_STATE_S4; - pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE; -#ifdef DBG_CHECK_FW_PS_STATE - RTW_INFO("%s: polling cpwm OK! cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x\n" - , __FUNCTION__, cpwm_orig, cpwm_now, rtw_read8(Adapter, REG_CR)); - if (rtw_fw_ps_state(Adapter) == _FAIL) { - RTW_INFO("%s: leave 32k but fw state in 32k\n", __FUNCTION__); - pdbgpriv->dbg_rpwm_toogle_cnt++; - } -#endif /* DBG_CHECK_FW_PS_STATE */ - break; - } - - if (rtw_get_passing_time_ms(start_time) > LPS_RPWM_WAIT_MS) { - RTW_INFO("%s: polling cpwm timeout! cpwm_orig=%02x, cpwm_now=%02x\n", __FUNCTION__, cpwm_orig, cpwm_now); -#ifdef DBG_CHECK_FW_PS_STATE - if (rtw_fw_ps_state(Adapter) == _FAIL) { - RTW_INFO("rpwm timeout and fw ps state in 32k\n"); - pdbgpriv->dbg_rpwm_timeout_fail_cnt++; - } -#endif /* DBG_CHECK_FW_PS_STATE */ - break; - } - } while (1); + if (rpwm != 0xFF && rpwm & PS_ACK) + rtw_cpwm_polling(Adapter, rpwm, cpwm_orig); #endif /* CONFIG_DETECT_CPWM_BY_POLLING */ _exit_pwrlock(&pwrpriv->lock); -#endif +#endif/*CONFIG_LPS_LCLK*/ #ifdef CONFIG_P2P_PS p2p_ps_wk_cmd(pri_padapter, P2P_PS_DISABLE, 0); @@ -1269,38 +1381,38 @@ void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) void LeaveAllPowerSaveMode(IN PADAPTER Adapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter); - struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); u8 enqueue = 0; - int n_assoc_iface = 0; int i; - - /* RTW_INFO("%s.....\n",__FUNCTION__); */ - + #ifndef CONFIG_NEW_NETDEV_HDL if (_FALSE == Adapter->bup) { RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n", FUNC_ADPT_ARG(Adapter), Adapter->bup); return; } + #endif + +/* RTW_INFO(FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(Adapter));*/ if (rtw_is_surprise_removed(Adapter)) { RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter)); return; } - for (i = 0; i < dvobj->iface_nums; i++) { - if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE)) - n_assoc_iface++; - } - - if (n_assoc_iface) { + if (rtw_mi_get_assoc_if_num(Adapter)) { /* connect */ #ifdef CONFIG_LPS_LCLK enqueue = 1; #endif #ifdef CONFIG_P2P_PS - p2p_ps_wk_cmd(Adapter, P2P_PS_DISABLE, enqueue); + for (i = 0; i < dvobj->iface_nums; i++) { + _adapter *iface = dvobj->padapters[i]; + struct wifidirect_info *pwdinfo = &(iface->wdinfo); + + if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) + p2p_ps_wk_cmd(iface, P2P_PS_DISABLE, enqueue); + } #endif /* CONFIG_P2P_PS */ #ifdef CONFIG_LPS @@ -1339,7 +1451,7 @@ void LPS_Leave_check( PADAPTER padapter) { struct pwrctrl_priv *pwrpriv; - u32 start_time; + systime start_time; u8 bReady; @@ -1368,7 +1480,7 @@ void LPS_Leave_check( break; if (rtw_get_passing_time_ms(start_time) > 100) { - RTW_INFO("Wait for cpwm event than 100 ms!!!\n"); + RTW_ERR("Wait for cpwm event than 100 ms!!!\n"); break; } rtw_msleep_os(1); @@ -1452,6 +1564,41 @@ static void dma_event_callback(struct work_struct *work) } #ifdef CONFIG_LPS_RPWM_TIMER + +#define DBG_CPWM_CHK_FAIL +#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)) +#define CPU_EXCEPTION_CODE 0xFAFAFAFA +static void rtw_cpwm_chk_fail_debug(_adapter *padapter) +{ + u32 cpu_state; + + cpu_state = rtw_read32(padapter, 0x10FC); + + RTW_INFO("[PS-DBG] Reg_10FC =0x%08x\n", cpu_state); + RTW_INFO("[PS-DBG] Reg_10F8 =0x%08x\n", rtw_read32(padapter, 0x10F8)); + RTW_INFO("[PS-DBG] Reg_11F8 =0x%08x\n", rtw_read32(padapter, 0x11F8)); + RTW_INFO("[PS-DBG] Reg_4A4 =0x%08x\n", rtw_read32(padapter, 0x4A4)); + RTW_INFO("[PS-DBG] Reg_4A8 =0x%08x\n", rtw_read32(padapter, 0x4A8)); + + if (cpu_state == CPU_EXCEPTION_CODE) { + RTW_INFO("[PS-DBG] Reg_48C =0x%08x\n", rtw_read32(padapter, 0x48C)); + RTW_INFO("[PS-DBG] Reg_490 =0x%08x\n", rtw_read32(padapter, 0x490)); + RTW_INFO("[PS-DBG] Reg_494 =0x%08x\n", rtw_read32(padapter, 0x494)); + RTW_INFO("[PS-DBG] Reg_498 =0x%08x\n", rtw_read32(padapter, 0x498)); + RTW_INFO("[PS-DBG] Reg_49C =0x%08x\n", rtw_read32(padapter, 0x49C)); + RTW_INFO("[PS-DBG] Reg_4A0 =0x%08x\n", rtw_read32(padapter, 0x4A0)); + RTW_INFO("[PS-DBG] Reg_1BC =0x%08x\n", rtw_read32(padapter, 0x1BC)); + + RTW_INFO("[PS-DBG] Reg_008 =0x%08x\n", rtw_read32(padapter, 0x08)); + RTW_INFO("[PS-DBG] Reg_2F0 =0x%08x\n", rtw_read32(padapter, 0x2F0)); + RTW_INFO("[PS-DBG] Reg_2F4 =0x%08x\n", rtw_read32(padapter, 0x2F4)); + RTW_INFO("[PS-DBG] Reg_2F8 =0x%08x\n", rtw_read32(padapter, 0x2F8)); + RTW_INFO("[PS-DBG] Reg_2FC =0x%08x\n", rtw_read32(padapter, 0x2FC)); + + rtw_dump_fifo(RTW_DBGDUMP, padapter, 5, 0, 3072); + } +} +#endif static void rpwmtimeout_workitem_callback(struct work_struct *work) { PADAPTER padapter; @@ -1462,7 +1609,6 @@ static void rpwmtimeout_workitem_callback(struct work_struct *work) pwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi); dvobj = pwrctl_to_dvobj(pwrpriv); padapter = dvobj_get_primary_adapter(dvobj); - /* RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); */ if (!padapter) return; @@ -1475,8 +1621,25 @@ static void rpwmtimeout_workitem_callback(struct work_struct *work) RTW_INFO("%s: rpwm=0x%02X cpwm=0x%02X CPWM done!\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); goto exit; } + + if (pwrpriv->rpwm_retry++ < LPS_RPWM_RETRY_CNT) { + u8 rpwm = (pwrpriv->rpwm | pwrpriv->tog | PS_ACK); + + rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm)); + + pwrpriv->tog += 0x80; + _set_timer(&pwrpriv->pwr_rpwm_timer, LPS_CPWM_TIMEOUT_MS); + goto exit; + } + + pwrpriv->rpwm_retry = 0; _exit_pwrlock(&pwrpriv->lock); +#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)) + RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); + rtw_cpwm_chk_fail_debug(padapter); +#endif + if (rtw_read8(padapter, 0x100) != 0xEA) { #if 1 struct reportpwrstate_parm report; @@ -1957,11 +2120,15 @@ void rtw_unregister_evt_alive(PADAPTER padapter) void rtw_init_pwrctrl_priv(PADAPTER padapter) { struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); - +#ifdef CONFIG_WOWLAN + struct registry_priv *registry_par = &padapter->registrypriv; +#endif +#ifdef CONFIG_GPIO_WAKEUP u8 val8 = 0; +#endif #if defined(CONFIG_CONCURRENT_MODE) - if (padapter->adapter_type != PRIMARY_ADAPTER) + if (!is_primary_adapter(padapter)) return; #endif @@ -1972,21 +2139,32 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) _init_pwrlock(&pwrctrlpriv->lock); _init_pwrlock(&pwrctrlpriv->check_32k_lock); - pwrctrlpriv->adapter = padapter; pwrctrlpriv->rf_pwrstate = rf_on; pwrctrlpriv->ips_enter_cnts = 0; pwrctrlpriv->ips_leave_cnts = 0; pwrctrlpriv->lps_enter_cnts = 0; pwrctrlpriv->lps_leave_cnts = 0; pwrctrlpriv->bips_processing = _FALSE; +#ifdef CONFIG_LPS_CHK_BY_TP + pwrctrlpriv->lps_chk_by_tp = padapter->registrypriv.lps_chk_by_tp; + pwrctrlpriv->lps_tx_tp_th = LPS_TX_TP_TH; + pwrctrlpriv->lps_rx_tp_th = LPS_RX_TP_TH; + pwrctrlpriv->lps_bi_tp_th = LPS_BI_TP_TH; + pwrctrlpriv->lps_chk_cnt = pwrctrlpriv->lps_chk_cnt_th = LPS_TP_CHK_CNT; + pwrctrlpriv->lps_tx_pkts = LPS_CHK_PKTS_TX; + pwrctrlpriv->lps_rx_pkts = LPS_CHK_PKTS_RX; +#endif pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode; pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode; + pwrctrlpriv->ips_deny_time = rtw_get_current_time(); pwrctrlpriv->lps_level = padapter->registrypriv.lps_level; pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL; pwrctrlpriv->pwr_state_check_cnts = 0; + #ifdef CONFIG_AUTOSUSPEND pwrctrlpriv->bInternalAutoSuspend = _FALSE; + #endif pwrctrlpriv->bInSuspend = _FALSE; pwrctrlpriv->bkeepfwalive = _FALSE; @@ -2020,6 +2198,7 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) pwrctrlpriv->dtim = 0; pwrctrlpriv->tog = 0x80; + pwrctrlpriv->rpwm_retry = 0; #ifdef CONFIG_LPS_LCLK rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&pwrctrlpriv->rpwm)); @@ -2035,11 +2214,12 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) #endif /* CONFIG_LPS_RPWM_TIMER */ #endif /* CONFIG_LPS_LCLK */ - rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler); + rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler, padapter); pwrctrlpriv->wowlan_mode = _FALSE; pwrctrlpriv->wowlan_ap_mode = _FALSE; pwrctrlpriv->wowlan_p2p_mode = _FALSE; + pwrctrlpriv->wowlan_in_resume = _FALSE; pwrctrlpriv->wowlan_last_wake_reason = 0; #ifdef CONFIG_RESUME_IN_WORKQUEUE @@ -2054,8 +2234,12 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) #ifdef CONFIG_GPIO_WAKEUP /*default low active*/ - pwrctrlpriv->is_high_active = HIGH_ACTIVE; - + pwrctrlpriv->is_high_active = HIGH_ACTIVE_DEV2HST; + pwrctrlpriv->hst2dev_high_active = HIGH_ACTIVE_HST2DEV; +#ifdef CONFIG_RTW_ONE_PIN_GPIO + rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE); + rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX); +#else #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE if (pwrctrlpriv->is_high_active == 0) rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX); @@ -2063,16 +2247,21 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter) rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0); #else val8 = (pwrctrlpriv->is_high_active == 0) ? 1 : 0; - rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE); rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8); RTW_INFO("%s: set GPIO_%d %d as default.\n", __func__, WAKEUP_GPIO_IDX, val8); #endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/ +#endif /* CONFIG_RTW_ONE_PIN_GPIO */ #endif /* CONFIG_GPIO_WAKEUP */ #ifdef CONFIG_WOWLAN + + if (registry_par->wakeup_event & BIT(1)) + pwrctrlpriv->default_patterns_en = _TRUE; + else + pwrctrlpriv->default_patterns_en = _FALSE; + rtw_wow_pattern_sw_reset(padapter); - pwrctrlpriv->wowlan_in_resume = _FALSE; #ifdef CONFIG_PNO_SUPPORT pwrctrlpriv->pno_inited = _FALSE; pwrctrlpriv->pnlo_info = NULL; @@ -2098,7 +2287,7 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter) struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter); #if defined(CONFIG_CONCURRENT_MODE) - if (adapter->adapter_type != PRIMARY_ADAPTER) + if (!is_primary_adapter(adapter)) return; #endif @@ -2117,6 +2306,14 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter) rtw_hal_set_hwreg(adapter, HW_VAR_LPS_POFF_DEINIT, 0); #endif +#ifdef CONFIG_LPS_LCLK + _cancel_workitem_sync(&pwrctrlpriv->cpwm_event); + _cancel_workitem_sync(&pwrctrlpriv->dma_event); + #ifdef CONFIG_LPS_RPWM_TIMER + _cancel_workitem_sync(&pwrctrlpriv->rpwmtimeoutwi); + #endif +#endif /* CONFIG_LPS_LCLK */ + #ifdef CONFIG_WOWLAN #ifdef CONFIG_PNO_SUPPORT if (pwrctrlpriv->pnlo_info != NULL) @@ -2322,9 +2519,9 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); struct mlme_priv *pmlmepriv; int ret = _SUCCESS; - int i; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); + /*RTW_INFO(FUNC_ADPT_FMT "===>\n", FUNC_ADPT_ARG(padapter));*/ /* for LPS */ LeaveAllPowerSaveMode(padapter); @@ -2332,7 +2529,7 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) padapter = GET_PRIMARY_ADAPTER(padapter); pmlmepriv = &padapter->mlmepriv; - if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms)) + if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time)) pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms); @@ -2358,7 +2555,11 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) } #endif - if (pwrpriv->bInternalAutoSuspend == _FALSE && pwrpriv->bInSuspend) { + if (pwrpriv->bInSuspend + #ifdef CONFIG_AUTOSUSPEND + && pwrpriv->bInternalAutoSuspend == _FALSE + #endif + ) { RTW_INFO("%s wait bInSuspend...\n", __func__); while (pwrpriv->bInSuspend && ((rtw_get_passing_time_ms(start) <= 3000 && !rtw_is_do_late_resume(pwrpriv)) @@ -2372,17 +2573,21 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) } /* System suspend is not allowed to wakeup */ - if ((pwrpriv->bInternalAutoSuspend == _FALSE) && (_TRUE == pwrpriv->bInSuspend)) { + if ((_TRUE == pwrpriv->bInSuspend) + #ifdef CONFIG_AUTOSUSPEND + && (pwrpriv->bInternalAutoSuspend == _FALSE) + #endif + ) { ret = _FAIL; goto exit; } - - /* block??? */ +#ifdef CONFIG_AUTOSUSPEND + /* usb autosuspend block??? */ if ((pwrpriv->bInternalAutoSuspend == _TRUE) && (padapter->net_closed == _TRUE)) { ret = _FAIL; goto exit; } - +#endif /* I think this should be check in IPS, LPS, autosuspend functions... */ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { #if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND) @@ -2450,8 +2655,9 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) } exit: - if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms)) + if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time)) pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms); + /*RTW_INFO(FUNC_ADPT_FMT "<===\n", FUNC_ADPT_ARG(padapter));*/ return ret; } @@ -2514,8 +2720,6 @@ int rtw_pm_set_ips(_adapter *padapter, u8 mode) void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason) { struct pwrctrl_priv *pwrpriv; - s32 ret; - /* RTW_INFO("+" FUNC_ADPT_FMT ": Request PS deny for %d (0x%08X)\n", * FUNC_ADPT_ARG(padapter), reason, BIT(reason)); */ diff --git a/core/rtw_recv.c b/core/rtw_recv.c index eb1e816..311a635 100755 --- a/core/rtw_recv.c +++ b/core/rtw_recv.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_RECV_C_ #include @@ -30,7 +25,7 @@ #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS -static void rtw_signal_stat_timer_hdl(struct timer_list *t); +static void rtw_signal_stat_timer_hdl(void *ctx); enum { SIGNAL_STAT_CALC_PROFILE_0 = 0, @@ -49,6 +44,14 @@ u8 signal_stat_calc_profile[SIGNAL_STAT_CALC_PROFILE_MAX][2] = { #endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ +u8 rtw_bridge_tunnel_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 }; +u8 rtw_rfc1042_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 }; +static u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37}; +static u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3}; +#ifdef CONFIG_TDLS +static u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d}; +#endif + void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv) { @@ -81,8 +84,7 @@ sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter) #ifdef CONFIG_RECV_THREAD_MODE _rtw_init_sema(&precvpriv->recv_sema, 0); - /*_rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);*/ - _rtw_init_completion(&precvpriv->recvthread_comp); + #endif _rtw_init_queue(&precvpriv->free_recv_queue); @@ -145,7 +147,7 @@ sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter) res = rtw_hal_init_recv_priv(padapter); #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS - rtw_init_timer(&precvpriv->signal_stat_timer, padapter, rtw_signal_stat_timer_hdl); + rtw_init_timer(&precvpriv->signal_stat_timer, padapter, rtw_signal_stat_timer_hdl, padapter); precvpriv->signal_stat_sampling_interval = 2000; /* ms */ /* precvpriv->signal_stat_converging_constant = 5000; */ /* ms */ @@ -166,7 +168,6 @@ void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv) _rtw_spinlock_free(&precvpriv->lock); #ifdef CONFIG_RECV_THREAD_MODE _rtw_free_sema(&precvpriv->recv_sema); - /*_rtw_free_sema(&precvpriv->terminate_recvthread_sema);*/ #endif _rtw_spinlock_free(&precvpriv->free_recv_queue.lock); @@ -607,11 +608,12 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) } } - if ((prxattrib->encrypt > 0) && ((prxattrib->bdecrypted == 0) || (psecuritypriv->sw_decrypt == _TRUE))) { - -#ifdef CONFIG_CONCURRENT_MODE - if (!IS_MCAST(prxattrib->ra)) /* bc/mc packets use sw decryption for concurrent mode */ -#endif + if (prxattrib->encrypt && !prxattrib->bdecrypted) { + if (GetFrameType(get_recvframe_data(precv_frame)) == WIFI_DATA + #ifdef CONFIG_CONCURRENT_MODE + && !IS_MCAST(prxattrib->ra) /* bc/mc packets may use sw decryption for concurrent mode */ + #endif + ) psecuritypriv->hw_decrypted = _FALSE; #ifdef DBG_RX_SW_DECRYPTOR @@ -692,6 +694,13 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) #endif } + #ifdef CONFIG_RTW_MESH + if (res != _FAIL + && !prxattrib->amsdu + && prxattrib->mesh_ctrl_present) + res = rtw_mesh_rx_validate_mctrl_non_amsdu(padapter, precv_frame); + #endif + if (res == _FAIL) { rtw_free_recvframe(return_packet, &padapter->recvpriv.free_recv_queue); return_packet = NULL; @@ -773,91 +782,166 @@ union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame) } -sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache); -sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache) +/* VALID_PN_CHK + * Return true when PN is legal, otherwise false. + * Legal PN: + * 1. If old PN is 0, any PN is legal + * 2. PN > old PN + */ +#define PN_LESS_CHK(a, b) (((a-b) & 0x800000000000) != 0) +#define VALID_PN_CHK(new, old) (((old) == 0) || PN_LESS_CHK(old, new)) +#define CCMPH_2_KEYID(ch) (((ch) & 0x00000000c0000000) >> 30) +sint recv_ucast_pn_decache(union recv_frame *precv_frame); +sint recv_ucast_pn_decache(union recv_frame *precv_frame) { + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_info *sta = precv_frame->u.hdr.psta; + struct stainfo_rxcache *prxcache = &sta->sta_recvpriv.rxcache; + u8 *pdata = precv_frame->u.hdr.rx_data; sint tid = precv_frame->u.hdr.attrib.priority; + u64 tmp_iv_hdr = 0; + u64 curr_pn = 0, pkt_pn = 0; - u16 seq_ctrl = ((precv_frame->u.hdr.attrib.seq_num & 0xffff) << 4) | - (precv_frame->u.hdr.attrib.frag_num & 0xf); - + if (tid > 15) + return _FAIL; - if (tid > 15) { + if (pattrib->encrypt == _AES_) { + tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen)); + pkt_pn = CCMPH_2_PN(tmp_iv_hdr); + tmp_iv_hdr = le64_to_cpu(*(u64*)prxcache->iv[tid]); + curr_pn = CCMPH_2_PN(tmp_iv_hdr); - return _FAIL; + if (!VALID_PN_CHK(pkt_pn, curr_pn)) { + /* return _FAIL; */ + } else { + prxcache->last_tid = tid; + _rtw_memcpy(prxcache->iv[tid], + (pdata + pattrib->hdrlen), + sizeof(prxcache->iv[tid])); + } } - if (1) { /* if(bretry) */ - if (seq_ctrl == prxcache->tid_rxseq[tid]) { - /* for non-AMPDU case */ - precv_frame->u.hdr.psta->sta_stats.duplicate_cnt++; + return _SUCCESS; +} + +sint recv_bcast_pn_decache(union recv_frame *precv_frame); +sint recv_bcast_pn_decache(union recv_frame *precv_frame) +{ + _adapter *padapter = precv_frame->u.hdr.adapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + u8 *pdata = precv_frame->u.hdr.rx_data; + u64 tmp_iv_hdr = 0; + u64 curr_pn = 0, pkt_pn = 0; + u8 key_id; + + if ((pattrib->encrypt == _AES_) && + (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) { + + tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen)); + key_id = CCMPH_2_KEYID(tmp_iv_hdr); + pkt_pn = CCMPH_2_PN(tmp_iv_hdr); - if (precv_frame->u.hdr.psta->sta_stats.duplicate_cnt % 100 == 0) - RTW_INFO("%s: seq=%d\n", __func__, precv_frame->u.hdr.attrib.seq_num); + curr_pn = le64_to_cpu(*(u64*)psecuritypriv->iv_seq[key_id]); + curr_pn &= 0x0000ffffffffffff; + if (!VALID_PN_CHK(pkt_pn, curr_pn)) return _FAIL; + + *(u64*)psecuritypriv->iv_seq[key_id] = cpu_to_le64(pkt_pn); + } + + return _SUCCESS; +} + +sint recv_decache(union recv_frame *precv_frame) +{ + struct sta_info *psta = precv_frame->u.hdr.psta; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + _adapter *adapter = psta->padapter; + sint tid = pattrib->priority; + u16 seq_ctrl = ((precv_frame->u.hdr.attrib.seq_num & 0xffff) << 4) | + (precv_frame->u.hdr.attrib.frag_num & 0xf); + u16 *prxseq; + + if (tid > 15) + return _FAIL; + + if (pattrib->qos) { + if (IS_MCAST(pattrib->ra)) + prxseq = &psta->sta_recvpriv.bmc_tid_rxseq[tid]; + else + prxseq = &psta->sta_recvpriv.rxcache.tid_rxseq[tid]; + } else { + if (IS_MCAST(pattrib->ra)) { + prxseq = &psta->sta_recvpriv.nonqos_bmc_rxseq; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" nonqos bmc seq_num:%d\n" + , FUNC_ADPT_ARG(adapter), pattrib->seq_num); + #endif + + } else { + prxseq = &psta->sta_recvpriv.nonqos_rxseq; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" nonqos seq_num:%d\n" + , FUNC_ADPT_ARG(adapter), pattrib->seq_num); + #endif } } - prxcache->tid_rxseq[tid] = seq_ctrl; + if (seq_ctrl == *prxseq) { + /* for non-AMPDU case */ + psta->sta_stats.duplicate_cnt++; + if (psta->sta_stats.duplicate_cnt % 100 == 0) + RTW_INFO("%s: tid=%u seq=%d frag=%d\n", __func__ + , tid, precv_frame->u.hdr.attrib.seq_num + , precv_frame->u.hdr.attrib.frag_num); - return _SUCCESS; + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_decache _FAIL for sta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + #endif + return _FAIL; + } + *prxseq = seq_ctrl; + return _SUCCESS; } -void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame); -void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame) +void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta) { #ifdef CONFIG_AP_MODE unsigned char pwrbit; u8 *ptr = precv_frame->u.hdr.rx_data; - struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta = NULL; - - psta = rtw_get_stainfo(pstapriv, pattrib->src); pwrbit = GetPwrMgt(ptr); - if (psta) { - if (pwrbit) { - if (!(psta->state & WIFI_SLEEP_STATE)) { - /* psta->state |= WIFI_SLEEP_STATE; */ - /* pstapriv->sta_dz_bitmap |= BIT(psta->aid); */ - - stop_sta_xmit(padapter, psta); - - /* RTW_INFO("to sleep, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); */ - } - } else { - if (psta->state & WIFI_SLEEP_STATE) { - /* psta->state ^= WIFI_SLEEP_STATE; */ - /* pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); */ - - wakeup_sta_to_xmit(padapter, psta); + if (pwrbit) { + if (!(psta->state & WIFI_SLEEP_STATE)) { + /* psta->state |= WIFI_SLEEP_STATE; */ + /* rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */ - /* RTW_INFO("to wakeup, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); */ - } + stop_sta_xmit(padapter, psta); + /* RTW_INFO_DUMP("to sleep, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */ } + } else { + if (psta->state & WIFI_SLEEP_STATE) { + /* psta->state ^= WIFI_SLEEP_STATE; */ + /* rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */ + wakeup_sta_to_xmit(padapter, psta); + /* RTW_INFO_DUMP("to wakeup, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */ + } } - #endif } -void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame); -void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame) +void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta) { #ifdef CONFIG_AP_MODE struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta = NULL; - - psta = rtw_get_stainfo(pstapriv, pattrib->src); - - if (!psta) - return; #ifdef CONFIG_TDLS if (!(psta->tdls_sta_state & TDLS_LINKED_STATE)) { @@ -902,7 +986,7 @@ void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame) xmit_delivery_enabled_frames(padapter, psta); } else { /* issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) */ - issue_qos_nulldata(padapter, psta->hwaddr, (u16)pattrib->priority, 0, 0); + issue_qos_nulldata(padapter, psta->cmn.mac_addr, (u16)pattrib->priority, 0, 0, 0); } } @@ -924,6 +1008,9 @@ sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame) u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a }; #endif /* CONFIG_WFD */ struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo); + u8 *ptr = precv_frame->u.hdr.rx_data; + struct sta_priv *pstapriv = &(adapter->stapriv); + struct sta_info *ptdls_sta = NULL; /* point to action field */ paction += pattrib->hdrlen @@ -941,41 +1028,54 @@ sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame) return ret; } - if (ptdlsinfo->tdls_enable == _FALSE) { + if (rtw_is_tdls_enabled(adapter) == _FALSE) { RTW_INFO("recv tdls frame, " "but tdls haven't enabled\n"); ret = _FAIL; return ret; } + ptdls_sta = rtw_get_stainfo(pstapriv, get_sa(ptr)); + if (ptdls_sta == NULL) { + switch (*paction) { + case TDLS_SETUP_REQUEST: + case TDLS_DISCOVERY_REQUEST: + break; + default: + RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(get_sa(ptr)), *paction); + ret = _FAIL; + goto exit; + } + } + switch (*paction) { case TDLS_SETUP_REQUEST: - ret = On_TDLS_Setup_Req(adapter, precv_frame); + ret = On_TDLS_Setup_Req(adapter, precv_frame, ptdls_sta); break; case TDLS_SETUP_RESPONSE: - ret = On_TDLS_Setup_Rsp(adapter, precv_frame); + ret = On_TDLS_Setup_Rsp(adapter, precv_frame, ptdls_sta); break; case TDLS_SETUP_CONFIRM: - ret = On_TDLS_Setup_Cfm(adapter, precv_frame); + ret = On_TDLS_Setup_Cfm(adapter, precv_frame, ptdls_sta); break; case TDLS_TEARDOWN: - ret = On_TDLS_Teardown(adapter, precv_frame); + ret = On_TDLS_Teardown(adapter, precv_frame, ptdls_sta); break; case TDLS_DISCOVERY_REQUEST: ret = On_TDLS_Dis_Req(adapter, precv_frame); break; case TDLS_PEER_TRAFFIC_INDICATION: - ret = On_TDLS_Peer_Traffic_Indication(adapter, precv_frame); + ret = On_TDLS_Peer_Traffic_Indication(adapter, precv_frame, ptdls_sta); break; case TDLS_PEER_TRAFFIC_RESPONSE: - ret = On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); + ret = On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame, ptdls_sta); break; #ifdef CONFIG_TDLS_CH_SW case TDLS_CHANNEL_SWITCH_REQUEST: - ret = On_TDLS_Ch_Switch_Req(adapter, precv_frame); + ret = On_TDLS_Ch_Switch_Req(adapter, precv_frame, ptdls_sta); break; case TDLS_CHANNEL_SWITCH_RESPONSE: - ret = On_TDLS_Ch_Switch_Rsp(adapter, precv_frame); + ret = On_TDLS_Ch_Switch_Rsp(adapter, precv_frame, ptdls_sta); break; #endif #ifdef CONFIG_WFD @@ -1010,7 +1110,6 @@ sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame) } #endif /* CONFIG_TDLS */ -void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta); void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta) { int sz; @@ -1018,8 +1117,6 @@ void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_in struct stainfo_stats *pstats = NULL; struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; struct recv_priv *precvpriv = &padapter->recvpriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); sz = get_recvframe_len(prframe); precvpriv->rx_bytes += sz; @@ -1035,39 +1132,45 @@ void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_in psta = prframe->u.hdr.psta; if (psta) { + u8 is_ra_bmc = IS_MCAST(pattrib->ra); + pstats = &psta->sta_stats; + pstats->last_rx_time = rtw_get_current_time(); pstats->rx_data_pkts++; pstats->rx_bytes += sz; + if (is_broadcast_mac_addr(pattrib->ra)) { + pstats->rx_data_bc_pkts++; + pstats->rx_bc_bytes += sz; + } else if (is_ra_bmc) { + pstats->rx_data_mc_pkts++; + pstats->rx_mc_bytes += sz; + } - pstats->rxratecnt[pattrib->data_rate]++; - /*record rx packets for every tid*/ - pstats->rx_data_qos_pkts[pattrib->priority]++; - -#ifdef CONFIG_TDLS - if (psta->tdls_sta_state & TDLS_LINKED_STATE) { - struct sta_info *pap_sta = NULL; - pap_sta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); - if (pap_sta) { - pstats = &pap_sta->sta_stats; - pstats->rx_data_pkts++; - pstats->rx_bytes += sz; - } + if (!is_ra_bmc) { + pstats->rxratecnt[pattrib->data_rate]++; + /*record rx packets for every tid*/ + pstats->rx_data_qos_pkts[pattrib->priority]++; } -#endif /* CONFIG_TDLS */ +#ifdef CONFIG_DYNAMIC_SOML + rtw_dyn_soml_byte_update(padapter, pattrib->data_rate, sz); +#endif +#if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP) + if (adapter_to_pwrctl(padapter)->lps_chk_by_tp) + traffic_check_for_leave_lps_by_tp(padapter, _FALSE, psta); +#endif /* CONFIG_LPS */ + } #ifdef CONFIG_CHECK_LEAVE_LPS - traffic_check_for_leave_lps(padapter, _FALSE, 0); -#endif /* CONFIG_LPS */ +#ifdef CONFIG_LPS_CHK_BY_TP + if (!adapter_to_pwrctl(padapter)->lps_chk_by_tp) +#endif + traffic_check_for_leave_lps(padapter, _FALSE, 0); +#endif /* CONFIG_CHECK_LEAVE_LPS */ } -sint sta2sta_data_frame( - _adapter *adapter, - union recv_frame *precv_frame, - struct sta_info **psta -); sint sta2sta_data_frame( _adapter *adapter, union recv_frame *precv_frame, @@ -1081,7 +1184,7 @@ sint sta2sta_data_frame( struct mlme_priv *pmlmepriv = &adapter->mlmepriv; u8 *mybssid = get_bssid(pmlmepriv); u8 *myhwaddr = adapter_mac_addr(adapter); - u8 *sta_addr = NULL; + u8 *sta_addr = pattrib->ta; sint bmcast = IS_MCAST(pattrib->dst); #ifdef CONFIG_TDLS @@ -1119,14 +1222,12 @@ sint sta2sta_data_frame( goto exit; } - sta_addr = pattrib->src; - } else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { #ifdef CONFIG_TDLS /* direct link data transfer */ if (ptdlsinfo->link_established == _TRUE) { - ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src); + *psta = ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->ta); if (ptdls_sta == NULL) { ret = _FAIL; goto exit; @@ -1161,7 +1262,7 @@ sint sta2sta_data_frame( #endif /* process UAPSD tdls sta */ - process_pwrbit_data(adapter, precv_frame); + process_pwrbit_data(adapter, precv_frame, ptdls_sta); /* if NULL-frame, check pwrbit */ if ((get_frame_sub_type(ptr) & WIFI_DATA_NULL) == WIFI_DATA_NULL) { @@ -1187,14 +1288,11 @@ sint sta2sta_data_frame( } if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) - process_wmmps_data(adapter, precv_frame); + process_wmmps_data(adapter, precv_frame, ptdls_sta); ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE); } - - sta_addr = pattrib->src; - } else #endif /* CONFIG_TDLS */ { @@ -1203,8 +1301,6 @@ sint sta2sta_data_frame( ret = _FAIL; goto exit; } - - sta_addr = pattrib->bssid; } } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { @@ -1220,8 +1316,6 @@ sint sta2sta_data_frame( ret = _FAIL; goto exit; } - - sta_addr = pattrib->src; } } else if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) { @@ -1235,17 +1329,10 @@ sint sta2sta_data_frame( } else ret = _FAIL; - - - if (bmcast) - *psta = rtw_get_bcmc_stainfo(adapter); - else - *psta = rtw_get_stainfo(pstapriv, sta_addr); /* get ap_info */ - #ifdef CONFIG_TDLS - if (ptdls_sta != NULL) - *psta = ptdls_sta; -#endif /* CONFIG_TDLS */ + if (ptdls_sta == NULL) +#endif + *psta = rtw_get_stainfo(pstapriv, sta_addr); if (*psta == NULL) { #ifdef CONFIG_MP_INCLUDED @@ -1263,10 +1350,6 @@ sint sta2sta_data_frame( } -sint ap2sta_data_frame( - _adapter *adapter, - union recv_frame *precv_frame, - struct sta_info **psta); sint ap2sta_data_frame( _adapter *adapter, union recv_frame *precv_frame, @@ -1289,19 +1372,20 @@ sint ap2sta_data_frame( /* filter packets that SA is myself or multicast or broadcast */ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s SA="MAC_FMT", myhwaddr="MAC_FMT"\n", - __FUNCTION__, MAC_ARG(pattrib->src), MAC_ARG(myhwaddr)); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" SA="MAC_FMT", myhwaddr="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->src), MAC_ARG(myhwaddr)); + #endif ret = _FAIL; goto exit; } /* da should be for me */ if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s DA="MAC_FMT"\n", __func__, MAC_ARG(pattrib->dst)); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->dst)); + #endif ret = _FAIL; goto exit; } @@ -1311,12 +1395,14 @@ sint ap2sta_data_frame( if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s BSSID="MAC_FMT", mybssid="MAC_FMT"\n", - __func__, MAC_ARG(pattrib->bssid), MAC_ARG(mybssid)); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" BSSID="MAC_FMT", mybssid="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->bssid), MAC_ARG(mybssid)); + #endif - if (!bmcast) { + if (!bmcast + && !IS_RADAR_DETECTED(adapter_to_rfctl(adapter)) + ) { RTW_INFO(ADPT_FMT" -issue_deauth to the nonassociated ap=" MAC_FMT " for the reason(7)\n", ADPT_ARG(adapter), MAC_ARG(pattrib->bssid)); issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); } @@ -1325,15 +1411,12 @@ sint ap2sta_data_frame( goto exit; } - if (bmcast) - *psta = rtw_get_bcmc_stainfo(adapter); - else - *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get ap_info */ - + *psta = rtw_get_stainfo(pstapriv, pattrib->ta); if (*psta == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under STATION_MODE ; drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under STATION_MODE ; drop pkt\n" + , FUNC_ADPT_ARG(adapter)); + #endif ret = _FAIL; goto exit; } @@ -1360,9 +1443,10 @@ sint ap2sta_data_frame( *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */ if (*psta == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n" + , FUNC_ADPT_ARG(adapter)); + #endif ret = _FAIL; goto exit; } @@ -1374,11 +1458,11 @@ sint ap2sta_data_frame( goto exit; } else { if (_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN) && (!bmcast)) { - *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */ + *psta = rtw_get_stainfo(pstapriv, pattrib->ta); if (*psta == NULL) { /* for AP multicast issue , modify by yiwei */ - static u32 send_issue_deauth_time = 0; + static systime send_issue_deauth_time = 0; /* RTW_INFO("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); */ @@ -1393,9 +1477,10 @@ sint ap2sta_data_frame( } ret = _FAIL; -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s fw_state:0x%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fw_state:0x%x\n" + , FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); + #endif } exit: @@ -1405,10 +1490,6 @@ sint ap2sta_data_frame( } -sint sta2ap_data_frame( - _adapter *adapter, - union recv_frame *precv_frame, - struct sta_info **psta); sint sta2ap_data_frame( _adapter *adapter, union recv_frame *precv_frame, @@ -1429,31 +1510,21 @@ sint sta2ap_data_frame( goto exit; } - *psta = rtw_get_stainfo(pstapriv, pattrib->src); + *psta = rtw_get_stainfo(pstapriv, pattrib->ta); if (*psta == NULL) { - #ifdef CONFIG_DFS_MASTER - struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - - /* prevent RX tasklet blocks cmd_thread */ - if (rfctl->radar_detected == 1) - goto bypass_deauth7; - #endif - - RTW_INFO("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src)); - - issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + if (!IS_RADAR_DETECTED(adapter_to_rfctl(adapter))) { + RTW_INFO("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src)); + issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + } -#ifdef CONFIG_DFS_MASTER -bypass_deauth7: -#endif ret = RTW_RX_HANDLED; goto exit; } - process_pwrbit_data(adapter, precv_frame); + process_pwrbit_data(adapter, precv_frame, *psta); if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) - process_wmmps_data(adapter, precv_frame); + process_wmmps_data(adapter, precv_frame, *psta); if (get_frame_sub_type(ptr) & BIT(6)) { /* No data, will not indicate to upper layer, temporily count it here */ @@ -1473,9 +1544,10 @@ sint sta2ap_data_frame( *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */ if (*psta == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n" + , FUNC_ADPT_ARG(adapter)); + #endif ret = _FAIL; goto exit; } @@ -1522,6 +1594,7 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) return _FAIL; /* for rx pkt statistics */ + psta->sta_stats.last_rx_time = rtw_get_current_time(); psta->sta_stats.rx_ctrl_pkts++; /* only handle ps-poll */ @@ -1531,7 +1604,7 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) u8 wmmps_ac = 0; aid = GetAid(pframe); - if (psta->aid != aid) + if (psta->cmn.aid != aid) return _FAIL; switch (pattrib->priority) { @@ -1563,7 +1636,7 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) psta->state ^= WIFI_STA_ALIVE_CHK_STATE; } - if ((psta->state & WIFI_SLEEP_STATE) && (pstapriv->sta_dz_bitmap & BIT(psta->aid))) { + if ((psta->state & WIFI_SLEEP_STATE) && (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid))) { _irqL irqL; _list *xmitframe_plist, *xmitframe_phead; struct xmit_frame *pxmitframe = NULL; @@ -1591,7 +1664,8 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) pxmitframe->attrib.triggered = 1; - /* RTW_INFO("handling ps-poll, q_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */ + /* RTW_INFO("handling ps-poll, q_len=%d\n", psta->sleepq_len); */ + /* RTW_INFO_DUMP("handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ #if 0 _exit_critical_bh(&psta->sleep_q.lock, &irqL); @@ -1602,9 +1676,10 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) rtw_hal_xmitframe_enqueue(padapter, pxmitframe); if (psta->sleepq_len == 0) { - pstapriv->tim_bitmap &= ~BIT(psta->aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); - /* RTW_INFO("after handling ps-poll, tim=%x\n", pstapriv->tim_bitmap); */ + /* RTW_INFO("after handling ps-poll\n"); */ + /* RTW_INFO_DUMP("after handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ /* upate BCN for TIM IE */ /* update_BCNTIM(padapter); */ @@ -1619,18 +1694,18 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) _exit_critical_bh(&pxmitpriv->lock, &irqL); /* RTW_INFO("no buffered packets to xmit\n"); */ - if (pstapriv->tim_bitmap & BIT(psta->aid)) { + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) { if (psta->sleepq_len == 0) { RTW_INFO("no buffered packets to xmit\n"); /* issue nulldata with More data bit = 0 to indicate we have no buffered packets */ - issue_nulldata_in_interrupt(padapter, psta->hwaddr, 0); + issue_nulldata(padapter, psta->cmn.mac_addr, 0, 0, 0); } else { RTW_INFO("error!psta->sleepq_len=%d\n", psta->sleepq_len); psta->sleepq_len = 0; } - pstapriv->tim_bitmap &= ~BIT(psta->aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); /* upate BCN for TIM IE */ /* update_BCNTIM(padapter); */ @@ -1641,55 +1716,282 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) #endif /* CONFIG_AP_MODE */ } else if (get_frame_sub_type(pframe) == WIFI_NDPA) { #ifdef CONFIG_BEAMFORMING - beamforming_get_ndpa_frame(padapter, precv_frame); + rtw_beamforming_get_ndpa_frame(padapter, precv_frame); #endif/*CONFIG_BEAMFORMING*/ + } else if (get_frame_sub_type(pframe) == WIFI_BAR) { + rtw_process_bar_frame(padapter, precv_frame); } return _FAIL; } -union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame); -sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame); -sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) +static sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_frame) { - /* struct mlme_priv *pmlmepriv = &adapter->mlmepriv; */ +#define DBG_VALIDATE_MGMT_PROTECT 0 +#define DBG_VALIDATE_MGMT_DEC 0 + struct security_priv *sec = &adapter->securitypriv; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_info *psta = precv_frame->u.hdr.psta; + u8 *ptr; + u8 type; + u8 subtype; + u8 is_bmc; + u8 category = 0xFF; -#if 0 - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { -#ifdef CONFIG_NATIVEAP_MLME - mgt_dispatcher(padapter, precv_frame); -#else - rtw_hostapd_mlme_rx(padapter, precv_frame); +#ifdef CONFIG_IEEE80211W + const u8 *igtk; + u16 igtk_id; + u64* ipn; #endif + + u8 *mgmt_DATA; + u32 data_len = 0; + + sint ret; + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + if (!adapter->mesh_info.mesh_auth_id) + return pattrib->privacy ? _FAIL : _SUCCESS; } else - mgt_dispatcher(padapter, precv_frame); #endif - - precv_frame = recvframe_chk_defrag(padapter, precv_frame); - if (precv_frame == NULL) { + if (SEC_IS_BIP_KEY_INSTALLED(sec) == _FALSE) return _SUCCESS; + + ptr = precv_frame->u.hdr.rx_data; + type = GetFrameType(ptr); + subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */ + is_bmc = IS_MCAST(GetAddr1Ptr(ptr)); + +#if DBG_VALIDATE_MGMT_PROTECT + if (subtype == WIFI_DEAUTH) { + RTW_INFO(FUNC_ADPT_FMT" bmc:%u, deauth, privacy:%u, encrypt:%u, bdecrypted:%u\n" + , FUNC_ADPT_ARG(adapter) + , is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted); + } else if (subtype == WIFI_DISASSOC) { + RTW_INFO(FUNC_ADPT_FMT" bmc:%u, disassoc, privacy:%u, encrypt:%u, bdecrypted:%u\n" + , FUNC_ADPT_ARG(adapter) + , is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted); + } if (subtype == WIFI_ACTION) { + if (pattrib->privacy) { + RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(?), privacy:%u, encrypt:%u, bdecrypted:%u\n" + , FUNC_ADPT_ARG(adapter) + , is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted); + } else { + RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(%u), privacy:%u, encrypt:%u, bdecrypted:%u\n" + , FUNC_ADPT_ARG(adapter), is_bmc + , *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr)) + , pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted); + } } +#endif - { - /* for rx pkt statistics */ - struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data)); - if (psta) { - psta->sta_stats.rx_mgnt_pkts++; - if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_BEACON) - psta->sta_stats.rx_beacon_pkts++; - else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ) - psta->sta_stats.rx_probereq_pkts++; - else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) { - if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE) - psta->sta_stats.rx_probersp_pkts++; - else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)) - || is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))) - psta->sta_stats.rx_probersp_bm_pkts++; - else - psta->sta_stats.rx_probersp_uo_pkts++; + if (!pattrib->privacy) { + if (!psta || !(psta->flags & WLAN_STA_MFP)) { + /* peer is not MFP capable, no need to check */ + goto exit; + } + + if (subtype == WIFI_ACTION) + category = *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr)); + + if (is_bmc) { + /* broadcast cases */ + if (subtype == WIFI_ACTION) { + if (CATEGORY_IS_GROUP_PRIVACY(category)) { + /* drop broadcast group privacy action frame without encryption */ + #if DBG_VALIDATE_MGMT_PROTECT + RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u) w/o encrypt\n" + , FUNC_ADPT_ARG(adapter), category); + #endif + goto fail; + } + if (CATEGORY_IS_ROBUST(category)) { + /* broadcast robust action frame need BIP check */ + goto bip_verify; + } + } + if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) { + /* broadcast deauth or disassoc frame need BIP check */ + goto bip_verify; + } + goto exit; + + } else { + /* unicast cases */ + #ifdef CONFIG_IEEE80211W + if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) { + if (!MLME_IS_MESH(adapter)) { + unsigned short reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN)); + + #if DBG_VALIDATE_MGMT_PROTECT + RTW_INFO(FUNC_ADPT_FMT" unicast %s, reason=%d w/o encrypt\n" + , FUNC_ADPT_ARG(adapter), subtype == WIFI_DEAUTH ? "deauth" : "disassoc", reason); + #endif + if (reason == 6 || reason == 7) { + /* issue sa query request */ + issue_action_SA_Query(adapter, psta->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY); + } + } + goto fail; + } + #endif + + if (subtype == WIFI_ACTION && CATEGORY_IS_ROBUST(category)) { + if (psta->bpairwise_key_installed == _TRUE) { + #if DBG_VALIDATE_MGMT_PROTECT + RTW_INFO(FUNC_ADPT_FMT" unicast robust action(%d) w/o encrypt\n" + , FUNC_ADPT_ARG(adapter), category); + #endif + goto fail; + } + } + goto exit; + } + +bip_verify: +#ifdef CONFIG_IEEE80211W + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + if (psta->igtk_bmp) { + igtk = psta->igtk.skey; + igtk_id = psta->igtk_id; + ipn = &psta->igtk_pn.val; + } else { + /* mesh MFP without IGTK */ + goto exit; } + } else + #endif + { + igtk = sec->dot11wBIPKey[sec->dot11wBIPKeyid].skey; + igtk_id = sec->dot11wBIPKeyid; + ipn = &sec->dot11wBIPrxpn.val; + } + + /* verify BIP MME IE */ + ret = rtw_BIP_verify(adapter + , get_recvframe_data(precv_frame) + , get_recvframe_len(precv_frame) + , igtk, igtk_id, ipn); + if (ret == _FAIL) { + /* RTW_INFO("802.11w BIP verify fail\n"); */ + goto fail; + + } else if (ret == RTW_RX_HANDLED) { + #if DBG_VALIDATE_MGMT_PROTECT + RTW_INFO(FUNC_ADPT_FMT" none protected packet\n", FUNC_ADPT_ARG(adapter)); + #endif + goto fail; + } +#endif /* CONFIG_IEEE80211W */ + goto exit; + } + + /* cases to decrypt mgmt frame */ + pattrib->bdecrypted = 0; + pattrib->encrypt = _AES_; + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* set iv and icv length */ + SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); + + /* actual management data frame body */ + data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; + mgmt_DATA = rtw_zmalloc(data_len); + if (mgmt_DATA == NULL) { + RTW_INFO(FUNC_ADPT_FMT" mgmt allocate fail !!!!!!!!!\n", FUNC_ADPT_ARG(adapter)); + goto fail; + } + +#if DBG_VALIDATE_MGMT_DEC + /* dump the packet content before decrypt */ + { + int pp; + + printk("pattrib->pktlen = %d =>", pattrib->pkt_len); + for (pp = 0; pp < pattrib->pkt_len; pp++) + printk(" %02x ", ptr[pp]); + printk("\n"); + } +#endif + + precv_frame = decryptor(adapter, precv_frame); + /* save actual management data frame body */ + _rtw_memcpy(mgmt_DATA, ptr + pattrib->hdrlen + pattrib->iv_len, data_len); + /* overwrite the iv field */ + _rtw_memcpy(ptr + pattrib->hdrlen, mgmt_DATA, data_len); + /* remove the iv and icv length */ + pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len; + rtw_mfree(mgmt_DATA, data_len); + +#if DBG_VALIDATE_MGMT_DEC + /* print packet content after decryption */ + { + int pp; + + printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len); + for (pp = 0; pp < pattrib->pkt_len; pp++) + printk(" %02x ", ptr[pp]); + printk("\n"); + } +#endif + + if (!precv_frame) { + #if DBG_VALIDATE_MGMT_PROTECT + RTW_INFO(FUNC_ADPT_FMT" mgmt descrypt fail !!!!!!!!!\n", FUNC_ADPT_ARG(adapter)); + #endif + goto fail; + } + +exit: + return _SUCCESS; + +fail: + return _FAIL; + +} +#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */ + +union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame); + +sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) +{ + struct sta_info *psta = precv_frame->u.hdr.psta + = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data)); + +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) + if (validate_mgmt_protect(padapter, precv_frame) == _FAIL) { + DBG_COUNTER(padapter->rx_logs.core_rx_pre_mgmt_err_80211w); + goto exit; + } +#endif + + precv_frame = recvframe_chk_defrag(padapter, precv_frame); + if (precv_frame == NULL) + return _SUCCESS; + + /* for rx pkt statistics */ + if (psta) { + psta->sta_stats.last_rx_time = rtw_get_current_time(); + psta->sta_stats.rx_mgnt_pkts++; + if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_BEACON) + psta->sta_stats.rx_beacon_pkts++; + else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ) + psta->sta_stats.rx_probereq_pkts++; + else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) { + if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE) + psta->sta_stats.rx_probersp_pkts++; + else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)) + || is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))) + psta->sta_stats.rx_probersp_bm_pkts++; + else + psta->sta_stats.rx_probersp_uo_pkts++; } } @@ -1742,130 +2044,146 @@ sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) #endif mgt_dispatcher(padapter, precv_frame); +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) +exit: +#endif return _SUCCESS; } -sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame); sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) { - u8 bretry; - u8 *psa, *pda, *pbssid; + u8 bretry, a4_shift; struct sta_info *psta = NULL; u8 *ptr = precv_frame->u.hdr.rx_data; struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct sta_priv *pstapriv = &adapter->stapriv; struct security_priv *psecuritypriv = &adapter->securitypriv; sint ret = _SUCCESS; - bretry = GetRetry(ptr); - pda = get_da(ptr); - psa = get_sa(ptr); - pbssid = get_hdr_bssid(ptr); - - if (pbssid == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s pbssid == NULL\n", __func__); -#endif - ret = _FAIL; - goto exit; - } + a4_shift = (pattrib->to_fr_ds == 3) ? ETH_ALEN : 0; - _rtw_memcpy(pattrib->dst, pda, ETH_ALEN); - _rtw_memcpy(pattrib->src, psa, ETH_ALEN); + /* some address fields are different when using AMSDU */ + if (pattrib->qos) + pattrib->amsdu = GetAMsdu(ptr + WLAN_HDR_A3_LEN + a4_shift); + else + pattrib->amsdu = 0; - _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + ret = rtw_mesh_rx_data_validate_hdr(adapter, precv_frame, &psta); + goto pre_validate_status_chk; + } +#endif switch (pattrib->to_fr_ds) { case 0: - _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); - _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); ret = sta2sta_data_frame(adapter, precv_frame, &psta); break; case 1: - _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); - _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, get_addr2_ptr(ptr), ETH_ALEN); ret = ap2sta_data_frame(adapter, precv_frame, &psta); break; case 2: - _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); - _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); - ret = sta2ap_data_frame(adapter, precv_frame, &psta); - break; - - case 3: _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); - ret = _FAIL; + _rtw_memcpy(pattrib->dst, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, GetAddr1Ptr(ptr), ETH_ALEN); + ret = sta2ap_data_frame(adapter, precv_frame, &psta); break; + case 3: default: + /* WDS is not supported */ ret = _FAIL; break; - } - if (ret == _FAIL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s case:%d, res:%d\n", __FUNCTION__, pattrib->to_fr_ds, ret); +#ifdef CONFIG_RTW_MESH +pre_validate_status_chk: #endif + if (ret == _FAIL) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" case:%d, res:%d, ra="MAC_FMT", ta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), pattrib->to_fr_ds, ret, MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr))); + #endif goto exit; } else if (ret == RTW_RX_HANDLED) goto exit; if (psta == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s psta == NULL\n", __func__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" psta == NULL, ra="MAC_FMT", ta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr))); + #endif ret = _FAIL; goto exit; } - /* psta->rssi = prxcmd->rssi; */ - /* psta->signal_quality= prxcmd->sq; */ precv_frame->u.hdr.psta = psta; - - - pattrib->amsdu = 0; + precv_frame->u.hdr.preorder_ctrl = NULL; pattrib->ack_policy = 0; + /* parsing QC field */ if (pattrib->qos == 1) { - pattrib->priority = GetPriority((ptr + 24)); - pattrib->ack_policy = GetAckpolicy((ptr + 24)); - pattrib->amsdu = GetAMsdu((ptr + 24)); - pattrib->hdrlen = pattrib->to_fr_ds == 3 ? 32 : 26; - + pattrib->priority = GetPriority((ptr + WLAN_HDR_A3_LEN + a4_shift)); /* point to Qos field*/ + pattrib->ack_policy = GetAckpolicy((ptr + WLAN_HDR_A3_LEN + a4_shift)); + pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN + a4_shift; if (pattrib->priority != 0 && pattrib->priority != 3) adapter->recvpriv.is_any_non_be_pkts = _TRUE; else adapter->recvpriv.is_any_non_be_pkts = _FALSE; } else { pattrib->priority = 0; - pattrib->hdrlen = pattrib->to_fr_ds == 3 ? 30 : 24; + pattrib->hdrlen = WLAN_HDR_A3_LEN + a4_shift; } - if (pattrib->order) /* HT-CTRL 11n */ pattrib->hdrlen += 4; - precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority]; - /* decache, drop duplicate recv packets */ - if (recv_decache(precv_frame, bretry, &psta->sta_recvpriv.rxcache) == _FAIL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s recv_decache return _FAIL\n", __func__); -#endif - ret = _FAIL; + ret = recv_decache(precv_frame); + if (ret == _FAIL) goto exit; - } - if (pattrib->privacy) { + if (!IS_MCAST(pattrib->ra)) { + + if (pattrib->qos) + precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority]; + if (recv_ucast_pn_decache(precv_frame) == _FAIL) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_ucast_pn_decache return _FAIL for sta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + #endif + ret = _FAIL; + goto exit; + } + } else { + if (recv_bcast_pn_decache(precv_frame) == _FAIL) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_bcast_pn_decache return _FAIL for sta="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr)); + #endif + ret = _FAIL; + goto exit; + } + } + if (pattrib->privacy) { #ifdef CONFIG_TDLS if ((psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta->dot118021XPrivacy == _AES_)) pattrib->encrypt = psta->dot118021XPrivacy; @@ -1880,128 +2198,16 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) pattrib->iv_len = pattrib->icv_len = 0; } -exit: - - - return ret; -} - -#ifdef CONFIG_IEEE80211W -static sint validate_80211w_mgmt(_adapter *adapter, union recv_frame *precv_frame) -{ - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - u8 *ptr = precv_frame->u.hdr.rx_data; - struct sta_info *psta; - struct sta_priv *pstapriv = &adapter->stapriv; - u8 type; - u8 subtype; - - type = GetFrameType(ptr); - subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */ - - if (adapter->securitypriv.binstallBIPkey == _TRUE) { - /* unicast management frame decrypt */ - if (pattrib->privacy && !(IS_MCAST(GetAddr1Ptr(ptr))) && - (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || subtype == WIFI_ACTION)) { - u8 *ppp, *mgmt_DATA; - u32 data_len = 0; - ppp = get_addr2_ptr(ptr); - - pattrib->bdecrypted = 0; - pattrib->encrypt = _AES_; - pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); - /* set iv and icv length */ - SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); - _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); - _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); - /* actual management data frame body */ - data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; - mgmt_DATA = rtw_zmalloc(data_len); - if (mgmt_DATA == NULL) { - RTW_INFO("%s mgmt allocate fail !!!!!!!!!\n", __FUNCTION__); - goto validate_80211w_fail; - } -#if 0 - /* dump the packet content before decrypt */ - { - int pp; - printk("pattrib->pktlen = %d =>", pattrib->pkt_len); - for (pp = 0; pp < pattrib->pkt_len; pp++) - printk(" %02x ", ptr[pp]); - printk("\n"); - } +#ifdef CONFIG_RTW_MESH + if (!pattrib->amsdu + && pattrib->mesh_ctrl_present + && (!pattrib->encrypt || pattrib->bdecrypted)) + ret = rtw_mesh_rx_validate_mctrl_non_amsdu(adapter, precv_frame); #endif - precv_frame = decryptor(adapter, precv_frame); - /* save actual management data frame body */ - _rtw_memcpy(mgmt_DATA, ptr + pattrib->hdrlen + pattrib->iv_len, data_len); - /* overwrite the iv field */ - _rtw_memcpy(ptr + pattrib->hdrlen, mgmt_DATA, data_len); - /* remove the iv and icv length */ - pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len; - rtw_mfree(mgmt_DATA, data_len); -#if 0 - /* print packet content after decryption */ - { - int pp; - printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len); - for (pp = 0; pp < pattrib->pkt_len; pp++) - printk(" %02x ", ptr[pp]); - printk("\n"); - } -#endif - if (!precv_frame) { - RTW_INFO("%s mgmt descrypt fail !!!!!!!!!\n", __FUNCTION__); - goto validate_80211w_fail; - } - } else if (IS_MCAST(GetAddr1Ptr(ptr)) && - (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC)) { - sint BIP_ret = _SUCCESS; - /* verify BIP MME IE of broadcast/multicast de-auth/disassoc packet */ - BIP_ret = rtw_BIP_verify(adapter, (u8 *)precv_frame); - if (BIP_ret == _FAIL) { - /* RTW_INFO("802.11w BIP verify fail\n"); */ - goto validate_80211w_fail; - } else if (BIP_ret == RTW_RX_HANDLED) { - RTW_INFO("802.11w recv none protected packet\n"); - /* drop pkt, don't issue sa query request */ - /* issue_action_SA_Query(adapter, NULL, 0, 0, 0); */ - goto validate_80211w_fail; - } - } /* 802.11w protect */ - else { - psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(ptr)); - - if (subtype == WIFI_ACTION && psta && psta->bpairwise_key_installed == _TRUE) { - /* according 802.11-2012 standard, these five types are not robust types */ - if (ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_PUBLIC && - ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_HT && - ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_UNPROTECTED_WNM && - ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_SELF_PROTECTED && - ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_P2P) { - RTW_INFO("action frame category=%d should robust\n", ptr[WLAN_HDR_A3_LEN]); - goto validate_80211w_fail; - } - } else if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) { - unsigned short reason; - reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN)); - RTW_INFO("802.11w recv none protected packet, reason=%d\n", reason); - if (reason == 6 || reason == 7) { - /* issue sa query request */ - issue_action_SA_Query(adapter, NULL, 0, 0, IEEE80211W_RIGHT_KEY); - } - goto validate_80211w_fail; - } - } - } - return _SUCCESS; - -validate_80211w_fail: - return _FAIL; - +exit: + return ret; } -#endif /* CONFIG_IEEE80211W */ static inline void dump_rx_packet(u8 *ptr) { @@ -2026,10 +2232,12 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) sint retval = _SUCCESS; struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct recv_priv *precvpriv = &adapter->recvpriv; u8 *ptr = precv_frame->u.hdr.rx_data; u8 ver = (unsigned char)(*ptr) & 0x3 ; #ifdef CONFIG_FIND_BEST_CHANNEL + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; #endif @@ -2047,9 +2255,9 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) #ifdef CONFIG_FIND_BEST_CHANNEL if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { - int ch_set_idx = rtw_chset_search_ch(pmlmeext->channel_set, rtw_get_oper_ch(adapter)); + int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, rtw_get_oper_ch(adapter)); if (ch_set_idx >= 0) - pmlmeext->channel_set[ch_set_idx].rx_count++; + rfctl->channel_set[ch_set_idx].rx_count++; } #endif @@ -2112,14 +2320,6 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) switch (type) { case WIFI_MGT_TYPE: /* mgnt */ DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt); -#ifdef CONFIG_IEEE80211W - if (validate_80211w_mgmt(adapter, precv_frame) == _FAIL) { - retval = _FAIL; - DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err_80211w); - break; - } -#endif /* CONFIG_IEEE80211W */ - retval = validate_recv_mgnt_frame(adapter, precv_frame); if (retval == _FAIL) { DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err); @@ -2169,30 +2369,32 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) pattrib->qos = (subtype & BIT(7)) ? 1 : 0; retval = validate_recv_data_frame(adapter, precv_frame); if (retval == _FAIL) { - struct recv_priv *precvpriv = &adapter->recvpriv; - precvpriv->rx_drop++; + precvpriv->dbg_rx_drop_count++; DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_err); } else if (retval == _SUCCESS) { -#ifdef DBG_RX_DUMP_EAP - u8 bDumpRxPkt; - u16 eth_type; - - /* dump eapol */ - rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt)); - /* get ether_type */ - _rtw_memcpy(ð_type, ptr + pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE, 2); - eth_type = ntohs((unsigned short) eth_type); - if ((bDumpRxPkt == 4) && (eth_type == 0x888e)) - dump_rx_packet(ptr); -#endif + #ifdef DBG_RX_DUMP_EAP + if (!pattrib->encrypt || pattrib->bdecrypted) { + u8 bDumpRxPkt; + u16 eth_type; + + /* dump eapol */ + rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt)); + /* get ether_type */ + _rtw_memcpy(ð_type, ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + LLC_HEADER_SIZE, 2); + eth_type = ntohs((unsigned short) eth_type); + if ((bDumpRxPkt == 4) && (eth_type == 0x888e)) + dump_rx_packet(ptr); + } + #endif } else DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_handled); break; default: DBG_COUNTER(adapter->rx_logs.core_rx_pre_unknown); -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME validate_recv_data_frame fail! type=0x%x\n", type); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fail! type=0x%x\n" + , FUNC_ADPT_ARG(adapter), type); + #endif retval = _FAIL; break; } @@ -2206,8 +2408,6 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) /* remove the wlanhdr and add the eth_hdr */ #if 1 - -sint wlanhdr_to_ethhdr(union recv_frame *precvframe); sint wlanhdr_to_ethhdr(union recv_frame *precvframe) { sint rmv_len; @@ -2227,8 +2427,8 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) if (pattrib->encrypt) recvframe_pull_tail(precvframe, pattrib->icv_len); - psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len); - psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE; + psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib)); + psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + SNAP_SIZE; /* convert hdr + possible LLC headers into Ethernet header */ /* eth_type = (psnap_type[0] << 8) | psnap_type[1]; */ if ((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) && @@ -2243,7 +2443,7 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) bsnaphdr = _FALSE; } - rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0); + rmv_len = pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + (bsnaphdr ? SNAP_SIZE : 0); len = precvframe->u.hdr.len - rmv_len; @@ -2251,37 +2451,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */ pattrib->eth_type = eth_type; -#ifdef CONFIG_AUTO_AP_MODE - if (0x8899 == pattrib->eth_type) { - struct sta_info *psta = precvframe->u.hdr.psta; - - RTW_INFO("wlan rx: got eth_type=0x%x\n", pattrib->eth_type); - - if (psta && psta->isrc && psta->pid > 0) { - u16 rx_pid; - - rx_pid = *(u16 *)(ptr + rmv_len + 2); - - RTW_INFO("wlan rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n", - rx_pid, MAC_ARG(psta->hwaddr), psta->pid); - - if (rx_pid == psta->pid) { - int i; - u16 len = *(u16 *)(ptr + rmv_len + 4); - /* u16 ctrl_type = *(u16*)(ptr+rmv_len+6); */ - - /* RTW_INFO("RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); */ - RTW_INFO("RC: len=0x%x\n", len); - - for (i = 0; i < len; i++) - RTW_INFO("0x%x\n", *(ptr + rmv_len + 6 + i)); - /* RTW_INFO("0x%x\n", *(ptr+rmv_len+8+i)); */ - - RTW_INFO("RC-end\n"); - } - } - } -#endif /* CONFIG_AUTO_AP_MODE */ if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)) { ptr += rmv_len ; @@ -2313,6 +2482,8 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) len = htons(len); _rtw_memcpy(ptr + 12, &len, 2); } + + rtw_rframe_set_os_pkt(precvframe); } exiting: @@ -2321,6 +2492,11 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe) } #else +static u8 SNAP_ETH_TYPE_APPLETALK_DDP[2] = {0x80, 0x9b}; +/* Datagram Delivery Protocol */ +static u8 SNAP_HDR_APPLETALK_DDP[3] = {0x08, 0x00, 0x07}; +static u8 oui_8021h[] = {0x00, 0x00, 0xf8}; +static u8 oui_rfc1042[] = {0x00, 0x00, 0x00}; sint wlanhdr_to_ethhdr(union recv_frame *precvframe) { @@ -2593,7 +2769,7 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec struct sta_priv *pstapriv; _list *phead; union recv_frame *prtnframe = NULL; - _queue *pfree_recv_queue, *pdefrag_q; + _queue *pfree_recv_queue, *pdefrag_q = NULL; pstapriv = &padapter->stapriv; @@ -2612,7 +2788,8 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec u8 type = GetFrameType(pfhdr->rx_data); if (type != WIFI_DATA_TYPE) { psta = rtw_get_bcmc_stainfo(padapter); - pdefrag_q = &psta->sta_recvpriv.defrag_q; + if (psta) + pdefrag_q = &psta->sta_recvpriv.defrag_q; } else pdefrag_q = NULL; } else @@ -2688,8 +2865,150 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec } +static int rtw_recv_indicatepkt_check(union recv_frame *rframe, u8 *ehdr_pos, u32 pkt_len) +{ + _adapter *adapter = rframe->u.hdr.adapter; + struct recv_priv *recvpriv = &adapter->recvpriv; + struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos; + int ret = _FAIL; + +#ifdef CONFIG_WAPI_SUPPORT + if (rtw_wapi_check_for_drop(adapter, rframe, ehdr_pos)) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_wapi_check_for_drop\n" + , FUNC_ADPT_ARG(adapter)); + #endif + goto exit; + } +#endif + + if (rframe->u.hdr.psta) + rtw_st_ctl_rx(rframe->u.hdr.psta, ehdr_pos); + + if (ntohs(ehdr->h_proto) == 0x888e) + parsing_eapol_packet(adapter, ehdr_pos + ETH_HLEN, rframe->u.hdr.psta, 0); +#ifdef DBG_ARP_DUMP + else if (ntohs(ehdr->h_proto) == ETH_P_ARP) + dump_arp_pkt(RTW_DBGDUMP, ehdr->h_dest, ehdr->h_source, ehdr_pos + ETH_HLEN, 0); +#endif + + if (recvpriv->sink_udpport > 0) + rtw_sink_rtp_seq_dbg(adapter, ehdr_pos); + +#ifdef DBG_UDP_PKT_LOSE_11AC + #define PAYLOAD_LEN_LOC_OF_IP_HDR 0x10 /*ethernet payload length location of ip header (DA + SA+eth_type+(version&hdr_len)) */ + + if (ntohs(ehdr->h_proto) == ETH_P_ARP) { + /* ARP Payload length will be 42bytes or 42+18(tailer)=60bytes*/ + if (pkt_len != 42 && pkt_len != 60) + RTW_INFO("Error !!%s,ARP Payload length %u not correct\n" , __func__ , pkt_len); + } else if (ntohs(ehdr->h_proto) == ETH_P_IP) { + if (be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))) != (pkt_len) - ETH_HLEN) { + RTW_INFO("Error !!%s,Payload length not correct\n" , __func__); + RTW_INFO("%s, IP header describe Total length=%u\n" , __func__ , be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR)))); + RTW_INFO("%s, Pkt real length=%u\n" , __func__ , (pkt_len) - ETH_HLEN); + } + } +#endif + +#ifdef CONFIG_AUTO_AP_MODE + if (ntohs(ehdr->h_proto) == 0x8899) + rtw_auto_ap_rx_msg_dump(adapter, rframe, ehdr_pos); +#endif + + ret = _SUCCESS; + +#ifdef CONFIG_WAPI_SUPPORT +exit: +#endif + return ret; +} + +static void recv_free_fwd_resource(_adapter *adapter, struct xmit_frame *fwd_frame, _list *b2u_list) +{ + struct xmit_priv *xmitpriv = &adapter->xmitpriv; + + if (fwd_frame) + rtw_free_xmitframe(xmitpriv, fwd_frame); + +#ifdef CONFIG_RTW_MESH +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (!rtw_is_list_empty(b2u_list)) { + struct xmit_frame *b2uframe; + _list *list; + + list = get_next(b2u_list); + while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) { + b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&b2uframe->list); + rtw_free_xmitframe(xmitpriv, b2uframe); + } + } +#endif +#endif /* CONFIG_RTW_MESH */ +} + +#ifdef CONFIG_RTW_MESH +static void recv_fwd_pkt_hdl(_adapter *adapter, _pkt *pkt + , u8 act, struct xmit_frame *fwd_frame, _list *b2u_list) +{ + struct xmit_priv *xmitpriv = &adapter->xmitpriv; + _pkt *fwd_pkt = pkt; + + if (act & RTW_RX_MSDU_ACT_INDICATE) { + fwd_pkt = rtw_os_pkt_copy(pkt); + if (!fwd_pkt) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_pkt_copy fail\n", __func__); + #endif + recv_free_fwd_resource(adapter, fwd_frame, b2u_list); + goto exit; + } + } + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (!rtw_is_list_empty(b2u_list)) { + _list *list = get_next(b2u_list); + struct xmit_frame *b2uframe; + + while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) { + b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&b2uframe->list); + + if (!fwd_frame && rtw_is_list_empty(b2u_list)) /* the last fwd_pkt */ + b2uframe->pkt = fwd_pkt; + else + b2uframe->pkt = rtw_os_pkt_copy(fwd_pkt); + if (!b2uframe->pkt) { + rtw_free_xmitframe(xmitpriv, b2uframe); + continue; + } + + rtw_xmit_posthandle(adapter, b2uframe, b2uframe->pkt); + } + } +#endif + + if (fwd_frame) { + fwd_frame->pkt = fwd_pkt; + if (rtw_xmit_posthandle(adapter, fwd_frame, fwd_pkt) < 0) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit_posthandle fail\n", __func__); + #endif + xmitpriv->tx_drop++; + } + } + +exit: + return; +} +#endif /* CONFIG_RTW_MESH */ + int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) { + struct rx_pkt_attrib *rattrib = &prframe->u.hdr.attrib; int a_len, padding_len; u16 nSubframe_Length; u8 nr_subframes, i; @@ -2697,43 +3016,96 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) _pkt *sub_pkt, *subframes[MAX_SUBFRAME_COUNT]; struct recv_priv *precvpriv = &padapter->recvpriv; _queue *pfree_recv_queue = &(precvpriv->free_recv_queue); + const u8 *da, *sa; + int act; + struct xmit_frame *fwd_frame; + _list b2u_list; + u8 mctrl_len = 0; int ret = _SUCCESS; nr_subframes = 0; - recvframe_pull(prframe, prframe->u.hdr.attrib.hdrlen); + recvframe_pull(prframe, rattrib->hdrlen); - if (prframe->u.hdr.attrib.iv_len > 0) - recvframe_pull(prframe, prframe->u.hdr.attrib.iv_len); + if (rattrib->iv_len > 0) + recvframe_pull(prframe, rattrib->iv_len); a_len = prframe->u.hdr.len; - pdata = prframe->u.hdr.rx_data; while (a_len > ETH_HLEN) { - /* Offset 12 denote 2 mac address */ nSubframe_Length = RTW_GET_BE16(pdata + 12); - if (a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length)) { RTW_INFO("nRemain_Length is %d and nSubframe_Length is : %d\n", a_len, nSubframe_Length); break; } - sub_pkt = rtw_os_alloc_msdu_pkt(prframe, nSubframe_Length, pdata); + act = RTW_RX_MSDU_ACT_INDICATE; + fwd_frame = NULL; + + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + u8 *mda = pdata, *msa = pdata + ETH_ALEN; + struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)(pdata + ETH_HLEN); + int v_ret; + + v_ret = rtw_mesh_rx_data_validate_mctrl(padapter, prframe + , mctrl, mda, msa, &mctrl_len, &da, &sa); + if (v_ret != _SUCCESS) + goto move_to_next; + + act = rtw_mesh_rx_msdu_act_check(prframe + , mda, msa, da, sa, mctrl, &fwd_frame, &b2u_list); + } else + #endif + { + da = pdata; + sa = pdata + ETH_ALEN; + } + + if (!act) + goto move_to_next; + + rtw_led_rx_control(padapter, da); + + sub_pkt = rtw_os_alloc_msdu_pkt(prframe, da, sa + , pdata + ETH_HLEN + mctrl_len, nSubframe_Length - mctrl_len); if (sub_pkt == NULL) { - RTW_INFO("%s(): allocate sub packet fail !!!\n", __FUNCTION__); + if (act & RTW_RX_MSDU_ACT_INDICATE) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__); + #endif + } + if (act & RTW_RX_MSDU_ACT_FORWARD) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__); + #endif + recv_free_fwd_resource(padapter, fwd_frame, &b2u_list); + } break; } + #ifdef CONFIG_RTW_MESH + if (act & RTW_RX_MSDU_ACT_FORWARD) { + recv_fwd_pkt_hdl(padapter, sub_pkt, act, fwd_frame, &b2u_list); + if (!(act & RTW_RX_MSDU_ACT_INDICATE)) + goto move_to_next; + } + #endif + + if (rtw_recv_indicatepkt_check(prframe, rtw_os_pkt_data(sub_pkt), rtw_os_pkt_len(sub_pkt)) == _SUCCESS) + subframes[nr_subframes++] = sub_pkt; + else + rtw_os_pkt_free(sub_pkt); + +move_to_next: /* move the data point to data content */ pdata += ETH_HLEN; a_len -= ETH_HLEN; - subframes[nr_subframes++] = sub_pkt; - if (nr_subframes >= MAX_SUBFRAME_COUNT) { - RTW_INFO("ParseSubframe(): Too many Subframes! Packets dropped!\n"); + RTW_WARN("ParseSubframe(): Too many Subframes! Packets dropped!\n"); break; } @@ -2758,7 +3130,7 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) /* Indicat the packets to upper layer */ if (sub_pkt) - rtw_os_recv_indicate_pkt(padapter, sub_pkt, &prframe->u.hdr.attrib); + rtw_os_recv_indicate_pkt(padapter, sub_pkt, prframe); } prframe->u.hdr.len = 0; @@ -2767,75 +3139,163 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) return ret; } -int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num); -int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num) +static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe) +{ + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + int ret; + + if (pattrib->amsdu) { + ret = amsdu_to_msdu(padapter, prframe); + if (ret != _SUCCESS) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" amsdu_to_msdu fail\n" + , FUNC_ADPT_ARG(padapter)); + #endif + rtw_free_recvframe(prframe, pfree_recv_queue); + goto exit; + } + } else { + int act = RTW_RX_MSDU_ACT_INDICATE; + struct xmit_frame *fwd_frame = NULL; + _list b2u_list; + + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter) && pattrib->mesh_ctrl_present) { + act = rtw_mesh_rx_msdu_act_check(prframe + , pattrib->mda, pattrib->msa + , pattrib->dst, pattrib->src + , (struct rtw_ieee80211s_hdr *)(get_recvframe_data(prframe) + pattrib->hdrlen + pattrib->iv_len) + , &fwd_frame, &b2u_list); + } + #endif + + if (!act) { + rtw_free_recvframe(prframe, pfree_recv_queue); + ret = _FAIL; + goto exit; + } + + rtw_led_rx_control(padapter, pattrib->dst); + + ret = wlanhdr_to_ethhdr(prframe); + if (ret != _SUCCESS) { + if (act & RTW_RX_MSDU_ACT_INDICATE) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n" + , FUNC_ADPT_ARG(padapter)); + #endif + } + if (act & RTW_RX_MSDU_ACT_FORWARD) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s wlanhdr_to_ethhdr fail\n", __func__); + #endif + recv_free_fwd_resource(padapter, fwd_frame, &b2u_list); + } + rtw_free_recvframe(prframe, pfree_recv_queue); + goto exit; + } + + #ifdef CONFIG_RTW_MESH + if (act & RTW_RX_MSDU_ACT_FORWARD) { + recv_fwd_pkt_hdl(padapter, prframe->u.hdr.pkt, act, fwd_frame, &b2u_list); + if (!(act & RTW_RX_MSDU_ACT_INDICATE)) { + prframe->u.hdr.pkt = NULL; + rtw_free_recvframe(prframe, pfree_recv_queue); + goto exit; + } + } + #endif + + if (!RTW_CANNOT_RUN(padapter)) { + ret = rtw_recv_indicatepkt_check(prframe + , get_recvframe_data(prframe), get_recvframe_len(prframe)); + if (ret != _SUCCESS) { + rtw_free_recvframe(prframe, pfree_recv_queue); + goto exit; + } + + /* indicate this recv_frame */ + ret = rtw_recv_indicatepkt(padapter, prframe); + if (ret != _SUCCESS) { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n" + , FUNC_ADPT_ARG(padapter)); + #endif + goto exit; + } + } else { + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DS:%u SR:%u\n" + , FUNC_ADPT_ARG(padapter) + , rtw_is_drv_stopped(padapter) + , rtw_is_surprise_removed(padapter)); + #endif + ret = _SUCCESS; /* don't count as packet drop */ + rtw_free_recvframe(prframe, pfree_recv_queue); + } + } + +exit: + return ret; +} + +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) +static int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num) { PADAPTER padapter = preorder_ctrl->padapter; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct recv_priv *precvpriv = &padapter->recvpriv; u8 wsize = preorder_ctrl->wsize_b; u16 wend = (preorder_ctrl->indicate_seq + wsize - 1) & 0xFFF; /* % 4096; */ /* Rx Reorder initialize condition. */ if (preorder_ctrl->indicate_seq == 0xFFFF) { preorder_ctrl->indicate_seq = seq_num; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d init IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, seq_num); -#endif - - /* DbgPrint("check_indicate_seq, 1st->indicate_seq=%d\n", precvpriv->indicate_seq); */ + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_INIT indicate_seq:%d, seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num); + #endif } - /* DbgPrint("enter->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ - /* Drop out the packet which SeqNum is smaller than WinStart */ if (SN_LESS(seq_num, preorder_ctrl->indicate_seq)) { - /* DbgPrint("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ - -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("%s IndicateSeq: %d > NewSeq: %d\n", __FUNCTION__, - preorder_ctrl->indicate_seq, seq_num); -#endif - - + #ifdef DBG_RX_DROP_FRAME + RTW_INFO(FUNC_ADPT_FMT" tid:%u indicate_seq:%d > seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num); + #endif return _FALSE; } - /* */ - /* Sliding window manipulation. Conditions includes: */ - /* 1. Incoming SeqNum is equal to WinStart =>Window shift 1 */ - /* 2. Incoming SeqNum is larger than the WinEnd => Window shift N */ - /* */ + /* + * Sliding window manipulation. Conditions includes: + * 1. Incoming SeqNum is equal to WinStart =>Window shift 1 + * 2. Incoming SeqNum is larger than the WinEnd => Window shift N + */ if (SN_EQUAL(seq_num, preorder_ctrl->indicate_seq)) { preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num); + #endif -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d SN_EQUAL IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, seq_num); -#endif } else if (SN_LESS(wend, seq_num)) { - /* DbgPrint("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ - /* boundary situation, when seq_num cross 0xFFF */ if (seq_num >= (wsize - 1)) preorder_ctrl->indicate_seq = seq_num + 1 - wsize; else preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1; - pdbgpriv->dbg_rx_ampdu_window_shift_cnt++; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d SN_LESS(wend, seq_num) IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, seq_num); -#endif - } - /* DbgPrint("exit->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ + precvpriv->dbg_rx_ampdu_window_shift_cnt++; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_LESS(wend, seq_num) indicate_seq:%d, seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num); + #endif + } return _TRUE; } -int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe); -int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe) +static int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe) { struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; @@ -2887,17 +3347,20 @@ int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union rec } -void recv_indicatepkts_pkt_loss_cnt(struct debug_priv *pdbgpriv, u64 prev_seq, u64 current_seq); -void recv_indicatepkts_pkt_loss_cnt(struct debug_priv *pdbgpriv, u64 prev_seq, u64 current_seq) +static void recv_indicatepkts_pkt_loss_cnt(_adapter *padapter, u64 prev_seq, u64 current_seq) { - if (current_seq < prev_seq) - pdbgpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq); + struct recv_priv *precvpriv = &padapter->recvpriv; - else - pdbgpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq); + if (current_seq < prev_seq) { + precvpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq); + precvpriv->rx_drop += (4096 + current_seq - prev_seq); + } else { + precvpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq); + precvpriv->rx_drop += (current_seq - prev_seq); + } } -int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced); -int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced) + +static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced) { /* _irqL irql; */ _list *phead, *plist; @@ -2907,8 +3370,6 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre int bPktInBuf = _FALSE; struct recv_priv *precvpriv = &padapter->recvpriv; _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_in_oder); @@ -2928,7 +3389,7 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre /* Handling some condition for forced indicate case. */ if (bforced == _TRUE) { - pdbgpriv->dbg_rx_ampdu_forced_indicate_count++; + precvpriv->dbg_rx_ampdu_forced_indicate_count++; if (rtw_is_list_empty(phead)) { /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ /* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */ @@ -2938,13 +3399,12 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre prframe = LIST_CONTAINOR(plist, union recv_frame, u); pattrib = &prframe->u.hdr.attrib; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif - recv_indicatepkts_pkt_loss_cnt(pdbgpriv, preorder_ctrl->indicate_seq, pattrib->seq_num); + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u FORCE indicate_seq:%d, seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num); + #endif + recv_indicatepkts_pkt_loss_cnt(padapter, preorder_ctrl->indicate_seq, pattrib->seq_num); preorder_ctrl->indicate_seq = pattrib->seq_num; - } /* Prepare indication list and indication. */ @@ -2970,10 +3430,10 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre if (SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num)) { preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n" + , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num); + #endif } #if 0 @@ -2997,19 +3457,8 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre /* indicate this recv_frame */ /* DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num); */ - if (!pattrib->amsdu) { - /* RTW_INFO("recv_indicatepkts_in_order, amsdu!=1, indicate_seq=%d, seq_num=%d\n", preorder_ctrl->indicate_seq, pattrib->seq_num); */ - - if (!RTW_CANNOT_RUN(padapter)) - rtw_recv_indicatepkt(padapter, prframe);/*indicate this recv_frame*/ - - } else if (pattrib->amsdu == 1) { - if (amsdu_to_msdu(padapter, prframe) != _SUCCESS) - rtw_free_recvframe(prframe, &precvpriv->free_recv_queue); - } else { - /* error condition; */ - } - + if (recv_process_mpdu(padapter, prframe) != _SUCCESS) + precvpriv->dbg_rx_drop_count++; /* Update local variables. */ bPktInBuf = _FALSE; @@ -3045,114 +3494,33 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre } -int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe); -int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) +static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) { _irqL irql; - int retval = _SUCCESS; struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl; - _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - - DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder); - - if (!pattrib->amsdu) { - /* s1. */ - retval = wlanhdr_to_ethhdr(prframe); - if (retval != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__); -#endif - return retval; - } - - /* if ((pattrib->qos!=1) || pattrib->priority!=0 || IS_MCAST(pattrib->ra) */ - /* || (pattrib->eth_type==0x0806) || (pattrib->ack_policy!=0)) */ - if (pattrib->qos != 1) { - if (!RTW_CANNOT_RUN(padapter)) { - - rtw_recv_indicatepkt(padapter, prframe); - return _SUCCESS; - - } - -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s pattrib->qos !=1\n", __FUNCTION__); -#endif - - return _FAIL; - - } - - if (preorder_ctrl->enable == _FALSE) { - /* indicate this recv_frame */ - preorder_ctrl->indicate_seq = pattrib->seq_num; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif - - rtw_recv_indicatepkt(padapter, prframe); - - preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) % 4096; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif - - return _SUCCESS; - } - -#ifndef CONFIG_RECV_REORDERING_CTRL - /* indicate this recv_frame */ - rtw_recv_indicatepkt(padapter, prframe); - return _SUCCESS; -#endif - - } else if (pattrib->amsdu == 1) { /* temp filter->means didn't support A-MSDUs in a A-MPDU */ - if (preorder_ctrl->enable == _FALSE) { - preorder_ctrl->indicate_seq = pattrib->seq_num; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif - - retval = amsdu_to_msdu(padapter, prframe); - - preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) % 4096; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq, pattrib->seq_num); -#endif - - if (retval != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__); -#endif - } + _queue *ppending_recvframe_queue = preorder_ctrl ? &preorder_ctrl->pending_recvframe_queue : NULL; + struct recv_priv *precvpriv = &padapter->recvpriv; - return retval; - } - } else { + if (!pattrib->qos || !preorder_ctrl || preorder_ctrl->enable == _FALSE) + goto _success_exit; - } + DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder); _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); - /* s2. check if winstart_b(indicate_seq) needs to been updated */ if (!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) { - pdbgpriv->dbg_rx_ampdu_drop_count++; + precvpriv->dbg_rx_ampdu_drop_count++; /* pHTInfo->RxReorderDropCounter++; */ /* ReturnRFDList(Adapter, pRfd); */ /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ /* return _FAIL; */ -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s check_indicate_seq fail\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" check_indicate_seq fail\n" + , FUNC_ADPT_ARG(padapter)); + #endif #if 0 rtw_recv_indicatepkt(padapter, prframe); @@ -3170,9 +3538,10 @@ int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) /* DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n"); */ /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ /* return _FAIL; */ -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s enqueue_reorder_recvframe fail\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" enqueue_reorder_recvframe fail\n" + , FUNC_ADPT_ARG(padapter)); + #endif goto _err_exit; } @@ -3200,6 +3569,7 @@ int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); } + return RTW_RX_HANDLED; _success_exit: @@ -3213,10 +3583,10 @@ int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) } -void rtw_reordering_ctrl_timeout_handler(struct timer_list *t) +void rtw_reordering_ctrl_timeout_handler(void *pcontext) { _irqL irql; - struct recv_reorder_ctrl *preorder_ctrl = from_timer(preorder_ctrl, t, reordering_ctrl_timer); + struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)pcontext; _adapter *padapter = preorder_ctrl->padapter; _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; @@ -3237,69 +3607,38 @@ void rtw_reordering_ctrl_timeout_handler(struct timer_list *t) _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); } +#endif /* defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) */ -int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe); -int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe) +static void recv_set_iseq_before_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller) { - int retval = _SUCCESS; - /* struct recv_priv *precvpriv = &padapter->recvpriv; */ - /* struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; */ - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; -#ifdef CONFIG_TDLS - struct sta_info *psta = prframe->u.hdr.psta; -#endif /* CONFIG_TDLS */ - -#ifdef CONFIG_80211N_HT - - struct ht_priv *phtpriv = &pmlmepriv->htpriv; - - DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate); - -#ifdef CONFIG_TDLS - if ((phtpriv->ht_option == _TRUE) || - ((psta->tdls_sta_state & TDLS_LINKED_STATE) && - (psta->htpriv.ht_option == _TRUE) && - (psta->htpriv.ampdu_enable == _TRUE))) /* B/G/N Mode */ -#else - if (phtpriv->ht_option == _TRUE) /* B/G/N Mode */ -#endif /* CONFIG_TDLS */ - { - /* prframe->u.hdr.preorder_ctrl = &precvpriv->recvreorder_ctrl[pattrib->priority]; */ - - if (recv_indicatepkt_reorder(padapter, prframe) != _SUCCESS) { /* including perform A-MPDU Rx Ordering Buffer Control */ -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s recv_indicatepkt_reorder error!\n", __FUNCTION__); -#endif - - if (!RTW_CANNOT_RUN(padapter)) { - retval = _FAIL; - return retval; - } - } - } else /* B/G mode */ -#endif - { - retval = wlanhdr_to_ethhdr(prframe); - if (retval != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__); +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) + struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl; + + if (reorder_ctrl) { + reorder_ctrl->indicate_seq = seq_num; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-B tid:%u indicate_seq:%d, seq_num:%d\n" + , caller, ADPT_ARG(reorder_ctrl->padapter) + , reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num); + #endif + } #endif - return retval; - } - - if (!RTW_CANNOT_RUN(padapter)) { - /* indicate this recv_frame */ - rtw_recv_indicatepkt(padapter, prframe); - } else { - - retval = _FAIL; - return retval; - } +} +static void recv_set_iseq_after_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller) +{ +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) + struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl; + + if (reorder_ctrl) { + reorder_ctrl->indicate_seq = (reorder_ctrl->indicate_seq + 1) % 4096; + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-A tid:%u indicate_seq:%d, seq_num:%d\n" + , caller, ADPT_ARG(reorder_ctrl->padapter) + , reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num); + #endif } - - return retval; - +#endif } #ifdef CONFIG_MP_INCLUDED @@ -3376,7 +3715,6 @@ static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe) sint ret = _SUCCESS; _adapter *adapter = precvframe->u.hdr.adapter; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; u8 *ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */ struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; @@ -3444,7 +3782,6 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) { int ret = _SUCCESS; struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib; - struct recv_priv *precvpriv = &padapter->recvpriv; _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; #ifdef CONFIG_MP_INCLUDED struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -3525,9 +3862,10 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) ret = MPwlanhdr_to_ethhdr(rframe); if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n" + , FUNC_ADPT_ARG(padapter)); + #endif rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ ret = _FAIL; goto exit; @@ -3536,20 +3874,22 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) /* indicate this recv_frame */ ret = rtw_recv_indicatepkt(padapter, rframe); if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s rtw_recv_indicatepkt fail!\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n" + , FUNC_ADPT_ARG(padapter)); + #endif rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ ret = _FAIL; goto exit; } } else { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s ecv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)\n", __func__, - rtw_is_drv_stopped(padapter) ? "True" : "False", - rtw_is_surprise_removed(padapter) ? "True" : "False"); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" + , FUNC_ADPT_ARG(padapter) + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False"); + #endif ret = _FAIL; rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ goto exit; @@ -3619,8 +3959,6 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, #endif sint ret = _SUCCESS; - _adapter *adapter = precvframe->u.hdr.adapter; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); @@ -3691,9 +4029,9 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, rt_len += 1; /* rate */ - if (pattrib->data_rate < 12) { + if (pattrib->data_rate <= DESC_RATE54M) { rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_RATE); - if (pattrib->data_rate < 4) { + if (pattrib->data_rate <= DESC_RATE11M) { /* CCK */ hdr_buf[rt_len] = data_rate[pattrib->data_rate]; } else { @@ -3718,8 +4056,8 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, else tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_5GHZ); - if (pattrib->data_rate < 12) { - if (pattrib->data_rate < 4) { + if (pattrib->data_rate <= DESC_RATE54M) { + if (pattrib->data_rate <= DESC_RATE11M) { /* CCK */ tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_CCK); } else { @@ -3733,7 +4071,7 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, /* dBm Antenna Signal */ rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL); - hdr_buf[rt_len] = pattrib->phy_info.RecvSignalPower; + hdr_buf[rt_len] = pattrib->phy_info.recv_signal_power; rt_len += 1; #if 0 @@ -3744,7 +4082,7 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, /* Signal Quality */ rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_LOCK_QUALITY); - hdr_buf[rt_len] = pattrib->phy_info.SignalQuality; + hdr_buf[rt_len] = pattrib->phy_info.signal_quality; rt_len += 1; #endif @@ -3762,7 +4100,7 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, rt_len += 2; /* MCS information */ - if (pattrib->data_rate >= 12 && pattrib->data_rate < 44) { + if (pattrib->data_rate >= DESC_RATEMCS0 && pattrib->data_rate <= DESC_RATEMCS31) { rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_MCS); /* known, flag */ hdr_buf[rt_len] |= BIT1; /* MCS index known */ @@ -3787,7 +4125,7 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, } /* VHT */ - if (pattrib->data_rate >= 44 && pattrib->data_rate < 84) { + if (pattrib->data_rate >= DESC_RATEVHTSS1MCS0 && pattrib->data_rate <= DESC_RATEVHTSS4MCS9) { rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_VHT); /* known 16 bit, flag 8 bit */ @@ -3829,16 +4167,16 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, rt_len += 1; /* mcs_nss */ - if (pattrib->data_rate >= 44 && pattrib->data_rate < 54) { + if (pattrib->data_rate >= DESC_RATEVHTSS1MCS0 && pattrib->data_rate <= DESC_RATEVHTSS1MCS9) { hdr_buf[rt_len] |= 1; hdr_buf[rt_len] |= data_rate[pattrib->data_rate] << 4; - } else if (pattrib->data_rate >= 54 && pattrib->data_rate < 64) { + } else if (pattrib->data_rate >= DESC_RATEVHTSS2MCS0 && pattrib->data_rate <= DESC_RATEVHTSS2MCS9) { hdr_buf[rt_len + 1] |= 2; hdr_buf[rt_len + 1] |= data_rate[pattrib->data_rate] << 4; - } else if (pattrib->data_rate >= 64 && pattrib->data_rate < 74) { + } else if (pattrib->data_rate >= DESC_RATEVHTSS3MCS0 && pattrib->data_rate <= DESC_RATEVHTSS3MCS9) { hdr_buf[rt_len + 2] |= 3; hdr_buf[rt_len + 2] |= data_rate[pattrib->data_rate] << 4; - } else if (pattrib->data_rate >= 74 && pattrib->data_rate < 84) { + } else if (pattrib->data_rate >= DESC_RATEVHTSS4MCS0 && pattrib->data_rate <= DESC_RATEVHTSS4MCS9) { hdr_buf[rt_len + 3] |= 4; hdr_buf[rt_len + 3] |= data_rate[pattrib->data_rate] << 4; } @@ -3869,6 +4207,7 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, ptr = skb_push(pskb, rt_len); if (ptr) { rtap_hdr->it_len = cpu_to_le16(rt_len); + rtap_hdr->it_present = cpu_to_le32(rtap_hdr->it_present); memcpy(ptr, rtap_hdr, rt_len); } else ret = _FAIL; @@ -3880,8 +4219,6 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe) { int ret = _SUCCESS; - struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib; - struct recv_priv *precvpriv = &padapter->recvpriv; _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; _pkt *pskb = NULL; @@ -3927,8 +4264,9 @@ int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe) int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe) { int ret = _SUCCESS; +#ifdef DBG_RX_COUNTER_DUMP struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib; - struct recv_priv *precvpriv = &padapter->recvpriv; +#endif _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; #ifdef DBG_RX_COUNTER_DUMP @@ -3973,30 +4311,24 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) DBG_COUNTER(padapter->rx_logs.core_rx_post); - /* DATA FRAME */ - rtw_led_control(padapter, LED_CTL_RX); - prframe = decryptor(padapter, prframe); if (prframe == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s decryptor: drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" decryptor: drop pkt\n" + , FUNC_ADPT_ARG(padapter)); + #endif ret = _FAIL; DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_err); goto _recv_data_drop; } #ifdef DBG_RX_BMC_FRAME - if (IS_MCAST(pattrib->ra)) { - u8 *pbuf = prframe->u.hdr.rx_data; - u8 *sa_addr = get_sa(pbuf); - - RTW_INFO("%s =>"ADPT_FMT" Rx BC/MC from MAC: "MAC_FMT"\n", __func__, ADPT_ARG(padapter), MAC_ARG(sa_addr)); - } + if (IS_MCAST(pattrib->ra)) + RTW_INFO("%s =>"ADPT_FMT" Rx BC/MC from "MAC_FMT"\n", __func__, ADPT_ARG(padapter), MAC_ARG(pattrib->ta)); #endif #if 0 - if (padapter->adapter_type == PRIMARY_ADAPTER) { + if (is_primary_adapter(padapter)) { RTW_INFO("+++\n"); { int i; @@ -4025,18 +4357,20 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) prframe = recvframe_chk_defrag(padapter, prframe); if (prframe == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s recvframe_chk_defrag: drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recvframe_chk_defrag: drop pkt\n" + , FUNC_ADPT_ARG(padapter)); + #endif DBG_COUNTER(padapter->rx_logs.core_rx_post_defrag_err); goto _recv_data_drop; } prframe = portctrl(padapter, prframe); if (prframe == NULL) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s portctrl: drop pkt\n", __FUNCTION__); -#endif + #ifdef DBG_RX_DROP_FRAME + RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" portctrl: drop pkt\n" + , FUNC_ADPT_ARG(padapter)); + #endif ret = _FAIL; DBG_COUNTER(padapter->rx_logs.core_rx_post_portctrl_err); goto _recv_data_drop; @@ -4048,75 +4382,30 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) rtw_wapi_update_info(padapter, prframe); #endif -#ifdef CONFIG_80211N_HT - ret = process_recv_indicatepkts(padapter, prframe); - if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s process_recv_indicatepkts fail!\n", __FUNCTION__); -#endif - rtw_free_recvframe(orig_prframe, pfree_recv_queue);/* free this recv_frame */ - DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_err); +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) + /* including perform A-MPDU Rx Ordering Buffer Control */ + ret = recv_indicatepkt_reorder(padapter, prframe); + if (ret == _FAIL) { + rtw_free_recvframe(orig_prframe, pfree_recv_queue); goto _recv_data_drop; - } -#else /* CONFIG_80211N_HT */ - if (!pattrib->amsdu) { - ret = wlanhdr_to_ethhdr(prframe); - if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__); -#endif - rtw_free_recvframe(orig_prframe, pfree_recv_queue);/* free this recv_frame */ - goto _recv_data_drop; - } - - if (!RTW_CANNOT_RUN(padapter)) { - /* indicate this recv_frame */ - ret = rtw_recv_indicatepkt(padapter, prframe); - if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s rtw_recv_indicatepkt fail!\n", __FUNCTION__); + } else if (ret == RTW_RX_HANDLED) /* queued OR indicated in order */ + goto _exit_recv_func; #endif - goto _recv_data_drop; - } - } else { - -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)\n", __func__ - , rtw_is_drv_stopped(padapter) ? "True" : "False" - , rtw_is_surprise_removed(padapter) ? "True" : "False"); -#endif - ret = _FAIL; - rtw_free_recvframe(orig_prframe, pfree_recv_queue); /* free this recv_frame */ - } - } else if (pattrib->amsdu == 1) { - - ret = amsdu_to_msdu(padapter, prframe); - if (ret != _SUCCESS) { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__); -#endif - rtw_free_recvframe(orig_prframe, pfree_recv_queue); - goto _recv_data_drop; - } - } else { -#ifdef DBG_RX_DROP_FRAME - RTW_INFO("DBG_RX_DROP_FRAME %s what is this condition??\n", __FUNCTION__); -#endif + recv_set_iseq_before_mpdu_process(prframe, pattrib->seq_num, __func__); + ret = recv_process_mpdu(padapter, prframe); + recv_set_iseq_after_mpdu_process(prframe, pattrib->seq_num, __func__); + if (ret == _FAIL) goto _recv_data_drop; - } -#endif /* CONFIG_80211N_HT */ _exit_recv_func: return ret; _recv_data_drop: - precvpriv->rx_drop++; + precvpriv->dbg_rx_drop_count++; return ret; } - -int recv_func(_adapter *padapter, union recv_frame *rframe); int recv_func(_adapter *padapter, union recv_frame *rframe) { int ret; @@ -4220,10 +4509,10 @@ s32 rtw_recv_entry(union recv_frame *precvframe) } #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS -static void rtw_signal_stat_timer_hdl(struct timer_list *t) +static void rtw_signal_stat_timer_hdl(void *ctx) { - struct recv_priv *recvpriv = from_timer(recvpriv, t, signal_stat_timer); - _adapter *adapter = container_of(recvpriv, _adapter, recvpriv); + _adapter *adapter = (_adapter *)ctx; + struct recv_priv *recvpriv = &adapter->recvpriv; u32 tmp_s, tmp_q; u8 avg_signal_strength = 0; @@ -4320,13 +4609,14 @@ static void rtw_signal_stat_timer_hdl(struct timer_list *t) static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe) { - u32 last_rssi, tmp_val; struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data; +#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ + u32 last_rssi, tmp_val; #endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - /* RTW_INFO("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength); */ + /* RTW_INFO("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->recv_signal_power,pattrib->signal_strength); */ /* if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) */ { #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS @@ -4337,7 +4627,7 @@ static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe) } signal_stat->total_num++; - signal_stat->total_val += pattrib->phy_info.SignalStrength; + signal_stat->total_val += pattrib->phy_info.signal_strength; signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; #else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ @@ -4347,9 +4637,9 @@ static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe) last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index]; padapter->recvpriv.signal_strength_data.total_val -= last_rssi; } - padapter->recvpriv.signal_strength_data.total_val += pattrib->phy_info.SignalStrength; + padapter->recvpriv.signal_strength_data.total_val += pattrib->phy_info.signal_strength; - padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.SignalStrength; + padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.signal_strength; if (padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX) padapter->recvpriv.signal_strength_data.index = 0; @@ -4370,10 +4660,11 @@ static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe) static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe) { - u32 last_evm = 0, tmpVal; struct rx_pkt_attrib *pattrib; #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS struct signal_stat *signal_stat; +#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ + u32 last_evm = 0, tmpVal; #endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ if (prframe == NULL || padapter == NULL) @@ -4394,11 +4685,11 @@ static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe) } signal_stat->total_num++; - signal_stat->total_val += pattrib->phy_info.SignalQuality; + signal_stat->total_val += pattrib->phy_info.signal_quality; signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; #else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ - if (pattrib->phy_info.SignalQuality != 0) { + if (pattrib->phy_info.signal_quality != 0) { /* */ /* 1. Record the general EVM to the sliding window. */ /* */ @@ -4407,9 +4698,9 @@ static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe) last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index]; padapter->recvpriv.signal_qual_data.total_val -= last_evm; } - padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.SignalQuality; + padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.signal_quality; - padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.SignalQuality; + padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.signal_quality; if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX) padapter->recvpriv.signal_qual_data.index = 0; @@ -4444,42 +4735,30 @@ void rx_query_phy_status( PADAPTER padapter = precvframe->u.hdr.adapter; struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct _odm_phy_status_info_ *pPHYInfo = (struct _odm_phy_status_info_ *)(&pattrib->phy_info); + struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info; u8 *wlanhdr; - struct _odm_per_pkt_info_ pkt_info; - u8 *sa; + struct phydm_perpkt_info_struct pkt_info; + u8 *ta, *ra; + u8 is_ra_bmc; struct sta_priv *pstapriv; struct sta_info *psta = NULL; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct recv_priv *precvpriv = &padapter->recvpriv; /* _irqL irqL; */ pkt_info.is_packet_match_bssid = _FALSE; pkt_info.is_packet_to_self = _FALSE; pkt_info.is_packet_beacon = _FALSE; pkt_info.ppdu_cnt = pattrib->ppdu_cnt; + pkt_info.station_id = 0xFF; wlanhdr = get_recvframe_data(precvframe); - pkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr)) - && (!pattrib->icv_err) && (!pattrib->crc_err) - && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN); + ta = get_ta(wlanhdr); + ra = get_ra(wlanhdr); + is_ra_bmc = IS_MCAST(ra); - pkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err) - && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN); - - pkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid - && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN); - - pkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid - && (get_frame_sub_type(wlanhdr) == WIFI_BEACON); - - sa = get_ta(wlanhdr); - - pkt_info.station_id = 0xFF; - - if (_rtw_memcmp(adapter_mac_addr(padapter), sa, ETH_ALEN) == _TRUE) { - static u32 start_time = 0; + if (_rtw_memcmp(adapter_mac_addr(padapter), ta, ETH_ALEN) == _TRUE) { + static systime start_time = 0; #if 0 /*For debug */ if (IsFrameTypeCtrl(wlanhdr)) { @@ -4501,36 +4780,72 @@ void rx_query_phy_status( RTW_PRINT("Warning!!! %s: Confilc mac addr!!\n", __func__); start_time = rtw_get_current_time(); } - pdbgpriv->dbg_rx_conflic_mac_addr_cnt++; + precvpriv->dbg_rx_conflic_mac_addr_cnt++; } else { pstapriv = &padapter->stapriv; - psta = rtw_get_stainfo(pstapriv, sa); + psta = rtw_get_stainfo(pstapriv, ta); if (psta) - pkt_info.station_id = psta->mac_id; + pkt_info.station_id = psta->cmn.mac_id; } + pkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr)) + && (!pattrib->icv_err) && (!pattrib->crc_err) + && ((!MLME_IS_MESH(padapter) && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN)) + || (MLME_IS_MESH(padapter) && psta)); + + pkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err) + && _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN); + + pkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid + && _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN); + + pkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid + && (get_frame_sub_type(wlanhdr) == WIFI_BEACON); + + if (psta && IsFrameTypeData(wlanhdr)) { + if (is_ra_bmc) + psta->curr_rx_rate_bmc = pattrib->data_rate; + else + psta->curr_rx_rate = pattrib->data_rate; + } pkt_info.data_rate = pattrib->data_rate; - /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ - odm_phy_status_query(&pHalData->odmpriv, pPHYInfo, pphy_status, &pkt_info); - if (psta) - psta->rssi = pattrib->phy_info.RecvSignalPower; - /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ + odm_phy_status_query(&pHalData->odmpriv, p_phy_info, pphy_status, &pkt_info); + + /* If bw is initial value, get from phy status */ + if (pattrib->bw == CHANNEL_WIDTH_MAX) + pattrib->bw = p_phy_info->band_width; { precvframe->u.hdr.psta = NULL; - if (pkt_info.is_packet_match_bssid - && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) - ) { - if (psta) { - precvframe->u.hdr.psta = psta; + if (padapter->registrypriv.mp_mode != 1) { + if ((!MLME_IS_MESH(padapter) && pkt_info.is_packet_match_bssid) + || (MLME_IS_MESH(padapter) && psta)) { + if (psta) { + precvframe->u.hdr.psta = psta; + rx_process_phy_info(padapter, precvframe); + } + } else if (pkt_info.is_packet_to_self || pkt_info.is_packet_beacon) { + if (psta) + precvframe->u.hdr.psta = psta; rx_process_phy_info(padapter, precvframe); } - } else if (pkt_info.is_packet_to_self || pkt_info.is_packet_beacon) { - - if (psta) - precvframe->u.hdr.psta = psta; - rx_process_phy_info(padapter, precvframe); + } else { +#ifdef CONFIG_MP_INCLUDED + if (padapter->mppriv.brx_filter_beacon == _TRUE) { + if (pkt_info.is_packet_beacon) { + RTW_INFO("in MP Rx is_packet_beacon\n"); + if (psta) + precvframe->u.hdr.psta = psta; + rx_process_phy_info(padapter, precvframe); + } + } else +#endif + { + if (psta) + precvframe->u.hdr.psta = psta; + rx_process_phy_info(padapter, precvframe); + } } } @@ -4561,29 +4876,65 @@ void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index) ATOMIC_SET(&sta->continual_no_rx_packet[tid_index], 0); } +u8 adapter_allow_bmc_data_rx(_adapter *adapter) +{ + if (check_fwstate(&adapter->mlmepriv, WIFI_MONITOR_STATE | WIFI_MP_STATE) == _TRUE) + return 1; + + if (MLME_IS_AP(adapter)) + return 0; + + if (rtw_linked_check(adapter) == _FALSE) + return 0; + + return 1; +} s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status) { s32 ret = _SUCCESS; -#ifdef CONFIG_CONCURRENT_MODE - u8 *pda; u8 *pbuf = precvframe->u.hdr.rx_data; - _adapter *iface = NULL; + u8 *pda = get_ra(pbuf); + u8 ra_is_bmc = IS_MCAST(pda); _adapter *primary_padapter = precvframe->u.hdr.adapter; +#ifdef CONFIG_CONCURRENT_MODE + _adapter *iface = NULL; - pda = get_ra(pbuf); + #ifdef CONFIG_MP_INCLUDED + if (rtw_mp_mode_check(primary_padapter)) + goto bypass_concurrent_hdl; + #endif - if (IS_MCAST(pda) == _FALSE) { /*unicast packets*/ + if (ra_is_bmc == _FALSE) { /*unicast packets*/ iface = rtw_get_iface_by_macddr(primary_padapter , pda); if (NULL == iface) { + #ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + if (_rtw_memcmp(pda, adapter_pno_mac_addr(primary_padapter), + ETH_ALEN) != _TRUE) + #endif RTW_INFO("%s [WARN] Cannot find appropriate adapter - mac_addr : "MAC_FMT"\n", __func__, MAC_ARG(pda)); /*rtw_warn_on(1);*/ } else precvframe->u.hdr.adapter = iface; } else /* Handle BC/MC Packets */ rtw_mi_buddy_clone_bcmc_packet(primary_padapter, precvframe, pphy_status); -#endif +bypass_concurrent_hdl: +#endif /* CONFIG_CONCURRENT_MODE */ + if (primary_padapter->registrypriv.mp_mode != 1) { + /* skip unnecessary bmc data frame for primary adapter */ + if (ra_is_bmc == _TRUE && GetFrameType(pbuf) == WIFI_DATA_TYPE + && !adapter_allow_bmc_data_rx(precvframe->u.hdr.adapter) + ) { + rtw_free_recvframe(precvframe, &precvframe->u.hdr.adapter->recvpriv.free_recv_queue); + goto exit; + } + } + + if (pphy_status) + rx_query_phy_status(precvframe, pphy_status); + ret = rtw_recv_entry(precvframe); +exit: return ret; } @@ -4593,11 +4944,13 @@ thread_return rtw_recv_thread(thread_context context) _adapter *adapter = (_adapter *)context; struct recv_priv *recvpriv = &adapter->recvpriv; s32 err = _SUCCESS; +#ifdef RTW_RECV_THREAD_HIGH_PRIORITY #ifdef PLATFORM_LINUX struct sched_param param = { .sched_priority = 1 }; sched_setscheduler(current, SCHED_FIFO, ¶m); #endif /* PLATFORM_LINUX */ +#endif /*RTW_RECV_THREAD_HIGH_PRIORITY*/ thread_enter("RTW_RECV_THREAD"); RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter)); @@ -4610,8 +4963,10 @@ thread_return rtw_recv_thread(thread_context context) } if (RTW_CANNOT_RUN(adapter)) { - RTW_INFO(FUNC_ADPT_FMT" DS:%d, SR:%d\n", FUNC_ADPT_ARG(adapter) - , rtw_is_drv_stopped(adapter), rtw_is_surprise_removed(adapter)); + RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n", + FUNC_ADPT_ARG(adapter), + rtw_is_drv_stopped(adapter) ? "True" : "False", + rtw_is_surprise_removed(adapter) ? "True" : "False"); goto exit; } @@ -4630,11 +4985,61 @@ thread_return rtw_recv_thread(thread_context context) exit: - RTW_INFO(FUNC_ADPT_FMT" exit\n", FUNC_ADPT_ARG(adapter)); + RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(adapter)); + + rtw_thread_wait_stop(); - /*_rtw_up_sema(&adapter->recvpriv.terminate_recvthread_sema);*/ - thread_exit(&adapter->recvpriv.recvthread_comp); return 0; } #endif /* CONFIG_RECV_THREAD_MODE */ +#if DBG_RX_BH_TRACKING +void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s) +{ + recv->rx_bh_stage = s; +} + +void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen) +{ + if (recv->rx_bh_cbuf) + recv->rx_bh_lbuf = recv->rx_bh_cbuf; + recv->rx_bh_cbuf = buf; + if (buf) { + recv->rx_bh_cbuf_data = data; + recv->rx_bh_cbuf_dlen = dlen; + recv->rx_bh_buf_dq_cnt++; + } else { + recv->rx_bh_cbuf_data = NULL; + recv->rx_bh_cbuf_dlen = 0; + } +} + +void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos) +{ + if (recv->rx_bh_cbuf) { + recv->rx_bh_cbuf_pos = pos - recv->rx_bh_cbuf_data; + } else { + rtw_warn_on(1); + recv->rx_bh_cbuf_pos = 0; + } +} + +void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame) +{ + recv->rx_bh_cframe = frame; +} + +void dump_rx_bh_tk(void *sel, struct recv_priv *recv) +{ + RTW_PRINT_SEL(sel, "[RXBHTK]s:%u, buf_dqc:%u, lbuf:%p, cbuf:%p, dlen:%u, pos:%u, cframe:%p\n" + , recv->rx_bh_stage + , recv->rx_bh_buf_dq_cnt + , recv->rx_bh_lbuf + , recv->rx_bh_cbuf + , recv->rx_bh_cbuf_dlen + , recv->rx_bh_cbuf_pos + , recv->rx_bh_cframe + ); +} +#endif /* DBG_RX_BH_TRACKING */ + diff --git a/core/rtw_rf.c b/core/rtw_rf.c index 1790665..f5cc458 100644 --- a/core/rtw_rf.c +++ b/core/rtw_rf.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_RF_C_ #include @@ -209,7 +204,6 @@ struct center_chs_ent_t center_chs_5g_by_bw[] = { */ u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset) { - int i; u8 t_cch = 0; if (bw == CHANNEL_WIDTH_20) { @@ -475,7 +469,6 @@ bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) u8 c_ch; u32 freq; u32 hi_ret = 0, lo_ret = 0; - int i; bool valid = _FALSE; if (hi) @@ -514,22 +507,24 @@ bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) return valid; } -const char *const _ch_width_str[] = { +const char *const _ch_width_str[CHANNEL_WIDTH_MAX] = { "20MHz", "40MHz", "80MHz", "160MHz", "80_80MHz", - "CHANNEL_WIDTH_MAX", + "5MHz", + "10MHz", }; -const u8 _ch_width_to_bw_cap[] = { +const u8 _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] = { BW_CAP_20M, BW_CAP_40M, BW_CAP_80M, BW_CAP_160M, BW_CAP_80_80M, - 0, + BW_CAP_5M, + BW_CAP_10M, }; const char *const _band_str[] = { @@ -547,459 +542,650 @@ const u8 _band_to_band_cap[] = { }; const u8 _rf_type_to_rf_tx_cnt[] = { - 1, - 2, - 2, - 1, - 2, - 2, - 3, - 3, - 4, + 1, /*RF_1T1R*/ + 1, /*RF_1T2R*/ + 2, /*RF_2T2R*/ + 2, /*RF_2T3R*/ + 2, /*RF_2T4R*/ + 3, /*RF_3T3R*/ + 3, /*RF_3T4R*/ + 4, /*RF_4T4R*/ + 1, /*RF_TYPE_MAX*/ }; const u8 _rf_type_to_rf_rx_cnt[] = { - 2, - 4, - 2, - 1, - 2, - 3, - 3, - 4, - 4, + 1, /*RF_1T1R*/ + 2, /*RF_1T2R*/ + 2, /*RF_2T2R*/ + 3, /*RF_2T3R*/ + 4, /*RF_2T4R*/ + 3, /*RF_3T3R*/ + 4, /*RF_3T4R*/ + 4, /*RF_4T4R*/ + 1, /*RF_TYPE_MAX*/ }; -#ifdef CONFIG_80211AC_VHT -#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val) -#else -#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) -#endif +const char *const _regd_str[] = { + "NONE", + "FCC", + "MKK", + "ETSI", + "IC", + "KCC", + "ACMA", + "CHILE", + "WW", +}; -#if RTW_DEF_MODULE_REGULATORY_CERT -#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val) , .def_module_flags = (_val) -#else -#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val) -#endif +#ifdef CONFIG_TXPWR_LIMIT +void _dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl) +{ + struct regd_exc_ent *ent; + _list *cur, *head; + + RTW_PRINT_SEL(sel, "regd_exc_num:%u\n", rfctl->regd_exc_num); -/* has def_module_flags specified, used by common map and HAL dfference map */ -#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac, _def_module_flags) \ - {.alpha2 = (_alpha2), .chplan = (_chplan) \ - COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \ - COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \ + if (!rfctl->regd_exc_num) + goto exit; + + RTW_PRINT_SEL(sel, "%-7s %-6s %-9s\n", "country", "domain", "regd_name"); + + head = &rfctl->reg_exc_list; + cur = get_next(head); + + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + u8 has_country; + + ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list); + cur = get_next(cur); + has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1; + + RTW_PRINT_SEL(sel, " %c%c 0x%02x %s\n" + , has_country ? ent->country[0] : '0' + , has_country ? ent->country[1] : '0' + , ent->domain + , ent->regd_name + ); } -#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP +exit: + return; +} -#include "../platform/custom_country_chplan.h" +inline void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl) +{ + _irqL irqL; -#elif RTW_DEF_MODULE_REGULATORY_CERT + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + _dump_regd_exc_list(sel, rfctl); + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); +} -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) /* 2013 certify */ -static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0x1FB), /* China */ - COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0x1F1), /* Malaysia */ - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x1FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0x1FB), /* Ukraine */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x1FF), /* United States of America (USA) */ -}; -#endif +void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen) +{ + struct regd_exc_ent *ent; + _irqL irqL; -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) /* 2014 certify */ -static const struct country_chplan RTL8821AU_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0x1FB), /* Russia(fac/gost), Kaliningrad */ - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x1FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0x1FB), /* Ukraine */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x1FF), /* United States of America (USA) */ -}; -#endif + if (!regd_name || !nlen) { + rtw_warn_on(1); + goto exit; + } -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) /* 2014 certify */ -static const struct country_chplan RTL8812AENF_NGFF_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x1FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x1FF), /* United States of America (USA) */ -}; -#endif + ent = (struct regd_exc_ent *)rtw_zmalloc(sizeof(struct regd_exc_ent) + nlen + 1); + if (!ent) + goto exit; -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) /* 2013 certify */ -static const struct country_chplan RTL8812AEBT_HMC_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0x1FB), /* Russia(fac/gost), Kaliningrad */ - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x1FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0x1FB), /* Ukraine */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x1FF), /* United States of America (USA) */ -}; -#endif + _rtw_init_listhead(&ent->list); + if (country) + _rtw_memcpy(ent->country, country, 2); + ent->domain = domain; + _rtw_memcpy(ent->regd_name, regd_name, nlen); -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) /* 2012 certify */ -static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x1FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x1FF), /* United States of America (USA) */ -}; -#endif + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) /* 2013 certify */ -static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x1FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x1FF), /* United States of America (USA) */ -}; -#endif + rtw_list_insert_tail(&ent->list, &rfctl->reg_exc_list); + rfctl->regd_exc_num++; -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) /* 2014 certify */ -static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x1FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x1FF), /* United States of America (USA) */ -}; -#endif + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) /* 2013 certify */ -static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_exc_map[] = { - COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0x1FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0x1FF), /* United States of America (USA) */ -}; -#endif +exit: + return; +} -#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723DE_NGFF1630) /* 2016 certify */ -static const struct country_chplan RTL8723DE_NGFF1630_country_chplan_exc_map[] = { -}; -#endif +inline void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name) +{ + rtw_regd_exc_add_with_nlen(rfctl, country, domain, regd_name, strlen(regd_name)); +} -/** - * rtw_def_module_get_chplan_from_country - - * @country_code: string of country code - * @return: - * Return NULL for case referring to common map - */ -static const struct country_chplan *rtw_def_module_get_chplan_from_country(const char *country_code) +struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain) { - const struct country_chplan *ent = NULL; - const struct country_chplan *hal_map = NULL; - u16 hal_map_sz = 0; - int i; + struct regd_exc_ent *ent; + _list *cur, *head; + u8 match = 0; + + head = &rfctl->reg_exc_list; + cur = get_next(head); + + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + u8 has_country; + + ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list); + cur = get_next(cur); + has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1; + + /* entry has country condition to match */ + if (has_country) { + if (!country) + continue; + if (ent->country[0] != country[0] + || ent->country[1] != country[1]) + continue; + } - /* TODO: runtime selection for multi driver */ -#if (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AE_HMC_M2) - hal_map = RTL8821AE_HMC_M2_country_chplan_exc_map; - hal_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); -#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AU) - hal_map = RTL8821AU_country_chplan_exc_map; - hal_map_sz = sizeof(RTL8821AU_country_chplan_exc_map) / sizeof(struct country_chplan); -#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AENF_NGFF) - hal_map = RTL8812AENF_NGFF_country_chplan_exc_map; - hal_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_exc_map) / sizeof(struct country_chplan); -#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AEBT_HMC) - hal_map = RTL8812AEBT_HMC_country_chplan_exc_map; - hal_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_exc_map) / sizeof(struct country_chplan); -#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8188EE_HMC_M2) - hal_map = RTL8188EE_HMC_M2_country_chplan_exc_map; - hal_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); -#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BE_HMC_M2) - hal_map = RTL8723BE_HMC_M2_country_chplan_exc_map; - hal_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); -#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BS_NGFF1216) - hal_map = RTL8723BS_NGFF1216_country_chplan_exc_map; - hal_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_exc_map) / sizeof(struct country_chplan); -#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8192EEBT_HMC_M2) - hal_map = RTL8192EEBT_HMC_M2_country_chplan_exc_map; - hal_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan); -#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723DE_NGFF1630) - hal_map = RTL8723DE_NGFF1630_country_chplan_exc_map; - hal_map_sz = sizeof(RTL8723DE_NGFF1630_country_chplan_exc_map) / sizeof(struct country_chplan); -#endif + /* entry has domain condition to match */ + if (ent->domain != 0xFF) { + if (domain == 0xFF) + continue; + if (ent->domain != domain) + continue; + } + + match = 1; + break; + } + + if (match) + return ent; + else + return NULL; +} + +inline struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain) +{ + struct regd_exc_ent *ent; + _irqL irqL; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + ent = _rtw_regd_exc_search(rfctl, country, domain); + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - if (hal_map == NULL || hal_map_sz == 0) + return ent; +} + +void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl) +{ + struct regd_exc_ent *ent; + _irqL irqL; + _list *cur, *head; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + head = &rfctl->reg_exc_list; + cur = get_next(head); + + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list); + cur = get_next(cur); + rtw_list_delete(&ent->list); + rtw_mfree((u8 *)ent, sizeof(struct regd_exc_ent) + strlen(ent->regd_name) + 1); + } + rfctl->regd_exc_num = 0; + + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); +} + +void dump_txpwr_lmt(void *sel, _adapter *adapter) +{ +#define TMP_STR_LEN 16 + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + _irqL irqL; + char fmt[16]; + char tmp_str[TMP_STR_LEN]; + s8 *lmt_idx = NULL; + int bw, band, ch_num, tlrs, ntx_idx, rs, i, path; + u8 ch, n, rfpath_num; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + _dump_regd_exc_list(sel, rfctl); + RTW_PRINT_SEL(sel, "\n"); + + if (!rfctl->txpwr_regd_num) + goto release_lock; + + lmt_idx = rtw_malloc(sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num); + if (!lmt_idx) { + RTW_ERR("%s alloc fail\n", __func__); + goto release_lock; + } + + RTW_PRINT_SEL(sel, "txpwr_lmt_2g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_2g_cck_ofdm_state); + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + RTW_PRINT_SEL(sel, "txpwr_lmt_5g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_5g_cck_ofdm_state); + RTW_PRINT_SEL(sel, "txpwr_lmt_5g_20_40_ref:0x%02x\n", rfctl->txpwr_lmt_5g_20_40_ref); + #endif + RTW_PRINT_SEL(sel, "\n"); + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; + + rfpath_num = (band == BAND_ON_2_4G ? hal_spec->rfpath_num_2g : hal_spec->rfpath_num_5g); + + for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) { + + if (bw >= CHANNEL_WIDTH_160) + break; + if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80) + break; + + if (band == BAND_ON_2_4G) + ch_num = CENTER_CH_2G_NUM; + else + ch_num = center_chs_5g_num(bw); + + if (ch_num == 0) { + rtw_warn_on(1); + break; + } + + for (tlrs = TXPWR_LMT_RS_CCK; tlrs < TXPWR_LMT_RS_NUM; tlrs++) { + + if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT) + continue; + if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK) + continue; + if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)) + continue; + if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT) + continue; + if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + continue; + + for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + struct txpwr_lmt_ent *ent; + _list *cur, *head; + + if (ntx_idx >= hal_spec->tx_nss_num) + continue; + + /* bypass CCK multi-TX is not defined */ + if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) { + if (band == BAND_ON_2_4G + && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx))) + continue; + } + + /* bypass OFDM multi-TX is not defined */ + if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) { + if (band == BAND_ON_2_4G + && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))) + continue; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (band == BAND_ON_5G + && !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))) + continue; + #endif + } + + /* bypass 5G 20M, 40M pure reference */ + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) { + if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) { + if (tlrs == TXPWR_LMT_RS_HT) + continue; + } else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) { + if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40) + continue; + } + } + #endif + + /* choose n-SS mapping rate section to get lmt diff value */ + if (tlrs == TXPWR_LMT_RS_CCK) + rs = CCK; + else if (tlrs == TXPWR_LMT_RS_OFDM) + rs = OFDM; + else if (tlrs == TXPWR_LMT_RS_HT) + rs = HT_1SS + ntx_idx; + else if (tlrs == TXPWR_LMT_RS_VHT) + rs = VHT_1SS + ntx_idx; + else { + RTW_ERR("%s invalid tlrs %u\n", __func__, tlrs); + continue; + } + + RTW_PRINT_SEL(sel, "[%s][%s][%s][%uT]\n" + , band_str(band) + , ch_width_str(bw) + , txpwr_lmt_rs_str(tlrs) + , ntx_idx + 1 + ); + + /* header for limit in db */ + RTW_PRINT_SEL(sel, "%3s ", "ch"); + + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + + sprintf(fmt, "%%%zus%%s ", strlen(ent->regd_name) >= 6 ? 1 : 6 - strlen(ent->regd_name)); + snprintf(tmp_str, TMP_STR_LEN, fmt + , strcmp(ent->regd_name, rfctl->regd_name) == 0 ? "*" : "" + , ent->regd_name); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } + sprintf(fmt, "%%%zus%%s ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? 1 : 6 - strlen(regd_str(TXPWR_LMT_WW))); + snprintf(tmp_str, TMP_STR_LEN, fmt + , strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? "*" : "" + , regd_str(TXPWR_LMT_WW)); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + + /* header for limit offset */ + for (path = 0; path < RF_PATH_MAX; path++) { + if (path >= rfpath_num) + break; + _RTW_PRINT_SEL(sel, "|"); + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + _RTW_PRINT_SEL(sel, "%3c " + , strcmp(ent->regd_name, rfctl->regd_name) == 0 ? rf_path_char(path) : ' '); + } + _RTW_PRINT_SEL(sel, "%3c " + , strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? rf_path_char(path) : ' '); + } + _RTW_PRINT_SEL(sel, "\n"); + + for (n = 0; n < ch_num; n++) { + s8 lmt; + s8 lmt_offset; + u8 base; + + if (band == BAND_ON_2_4G) + ch = n + 1; + else + ch = center_chs_5g(bw, n); + + if (ch == 0) { + rtw_warn_on(1); + break; + } + + /* dump limit in db */ + RTW_PRINT_SEL(sel, "%3u ", ch); + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + lmt = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw, tlrs, ntx_idx, ch, 0); + if (lmt == hal_spec->txgi_max) { + sprintf(fmt, "%%%zus ", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) + 1 : 6); + snprintf(tmp_str, TMP_STR_LEN, fmt, "NA"); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } else if (lmt > -hal_spec->txgi_pdbm && lmt < 0) { /* -0.xx */ + sprintf(fmt, "%%%zus-0.%%d ", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) - 4 : 1); + snprintf(tmp_str, TMP_STR_LEN, fmt, "", (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } else if (lmt % hal_spec->txgi_pdbm) { /* d.xx */ + sprintf(fmt, "%%%zud.%%d ", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) - 2 : 3); + snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm, (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } else { /* d */ + sprintf(fmt, "%%%zud ", strlen(ent->regd_name) >= 6 ? strlen(ent->regd_name) + 1 : 6); + snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } + } + lmt = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw, tlrs, ntx_idx, ch, 0); + if (lmt == hal_spec->txgi_max) { + sprintf(fmt, "%%%zus ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 6); + snprintf(tmp_str, TMP_STR_LEN, fmt, "NA"); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } else if (lmt > -hal_spec->txgi_pdbm && lmt < 0) { /* -0.xx */ + sprintf(fmt, "%%%zus-0.%%d ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) - 4 : 1); + snprintf(tmp_str, TMP_STR_LEN, fmt, "", (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } else if (lmt % hal_spec->txgi_pdbm) { /* d.xx */ + sprintf(fmt, "%%%zud.%%d ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) - 2 : 3); + snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm, (rtw_abs(lmt) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } else { /* d */ + sprintf(fmt, "%%%zud ", strlen(regd_str(TXPWR_LMT_WW)) >= 6 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 6); + snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / hal_spec->txgi_pdbm); + _RTW_PRINT_SEL(sel, "%s", tmp_str); + } + + /* dump limit offset of each path */ + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (path >= rfpath_num) + break; + + base = PHY_GetTxPowerByRateBase(adapter, band, path, rs); + + _RTW_PRINT_SEL(sel, "|"); + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + i = 0; + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + lmt_offset = phy_get_txpwr_lmt(adapter, ent->regd_name, band, bw, path, rs, ntx_idx, ch, 0); + if (lmt_offset == hal_spec->txgi_max) { + *(lmt_idx + i * RF_PATH_MAX + path) = hal_spec->txgi_max; + _RTW_PRINT_SEL(sel, "%3s ", "NA"); + } else { + *(lmt_idx + i * RF_PATH_MAX + path) = lmt_offset + base; + _RTW_PRINT_SEL(sel, "%3d ", lmt_offset); + } + i++; + } + lmt_offset = phy_get_txpwr_lmt(adapter, regd_str(TXPWR_LMT_WW), band, bw, path, rs, ntx_idx, ch, 0); + if (lmt_offset == hal_spec->txgi_max) + _RTW_PRINT_SEL(sel, "%3s ", "NA"); + else + _RTW_PRINT_SEL(sel, "%3d ", lmt_offset); + + } + + /* compare limit_idx of each path, print 'x' when mismatch */ + if (rfpath_num > 1) { + for (i = 0; i < rfctl->txpwr_regd_num; i++) { + for (path = 0; path < RF_PATH_MAX; path++) { + if (path >= rfpath_num) + break; + if (*(lmt_idx + i * RF_PATH_MAX + path) != *(lmt_idx + i * RF_PATH_MAX + ((path + 1) % rfpath_num))) + break; + } + if (path >= rfpath_num) + _RTW_PRINT_SEL(sel, " "); + else + _RTW_PRINT_SEL(sel, "x"); + } + } + _RTW_PRINT_SEL(sel, "\n"); + + } + RTW_PRINT_SEL(sel, "\n"); + } + } /* loop for rate sections */ + } /* loop for bandwidths */ + } /* loop for bands */ + + if (lmt_idx) + rtw_mfree(lmt_idx, sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num); + +release_lock: + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); +} + +/* search matcing first, if not found, alloc one */ +void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen + , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(dvobj_get_primary_adapter(rfctl_to_dvobj(rfctl))); + struct txpwr_lmt_ent *ent; + _irqL irqL; + _list *cur, *head; + s8 pre_lmt; + + if (!regd_name || !nlen) { + rtw_warn_on(1); goto exit; + } - for (i = 0; i < hal_map_sz; i++) { - if (strncmp(country_code, hal_map[i].alpha2, 2) == 0) { - ent = &hal_map[i]; - break; - } + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + /* search for existed entry */ + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + + if (strlen(ent->regd_name) == nlen + && _rtw_memcmp(ent->regd_name, regd_name, nlen) == _TRUE) + goto chk_lmt_val; + } + + /* alloc new one */ + ent = (struct txpwr_lmt_ent *)rtw_zvmalloc(sizeof(struct txpwr_lmt_ent) + nlen + 1); + if (!ent) + goto release_lock; + + _rtw_init_listhead(&ent->list); + _rtw_memcpy(ent->regd_name, regd_name, nlen); + { + u8 j, k, l, m; + + for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) + for (k = 0; k < TXPWR_LMT_RS_NUM_2G; ++k) + for (m = 0; m < CENTER_CH_2G_NUM; ++m) + for (l = 0; l < MAX_TX_COUNT; ++l) + ent->lmt_2g[j][k][m][l] = hal_spec->txgi_max; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j) + for (k = 0; k < TXPWR_LMT_RS_NUM_5G; ++k) + for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m) + for (l = 0; l < MAX_TX_COUNT; ++l) + ent->lmt_5g[j][k][m][l] = hal_spec->txgi_max; + #endif } + rtw_list_insert_tail(&ent->list, &rfctl->txpwr_lmt_list); + rfctl->txpwr_regd_num++; + +chk_lmt_val: + if (band == BAND_ON_2_4G) + pre_lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + else if (band == BAND_ON_5G) + pre_lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]; + #endif + else + goto release_lock; + + if (pre_lmt != hal_spec->txgi_max) + RTW_PRINT("duplicate txpwr_lmt for [%s][%s][%s][%s][%uT][%d]\n" + , regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1 + , band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]); + + lmt = rtw_min(pre_lmt, lmt); + if (band == BAND_ON_2_4G) + ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] = lmt; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + else if (band == BAND_ON_5G) + ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] = lmt; + #endif + + if (0) + RTW_PRINT("%s, %4s, %6s, %7s, %uT, ch%3d = %d\n" + , regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1 + , band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx] + , lmt); + +release_lock: + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + exit: - return ent; + return; } -#endif /* CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP or RTW_DEF_MODULE_REGULATORY_CERT */ - -static const struct country_chplan country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x000), /* Andorra */ - COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0x1FB), /* United Arab Emirates */ - COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x000), /* Afghanistan */ - COUNTRY_CHPLAN_ENT("AG", 0x30, 1, 0x000), /* Antigua & Barbuda */ - COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x000), /* Anguilla(UK) */ - COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0x1F1), /* Albania */ - COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0x0B0), /* Armenia */ - COUNTRY_CHPLAN_ENT("AO", 0x26, 1, 0x0E0), /* Angola */ - COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x000), /* Antarctica */ - COUNTRY_CHPLAN_ENT("AR", 0x57, 1, 0x1F3), /* Argentina */ - COUNTRY_CHPLAN_ENT("AS", 0x34, 1, 0x000), /* American Samoa */ - COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0x1FB), /* Austria */ - COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0x1FB), /* Australia */ - COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0x0B0), /* Aruba */ - COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0x1F1), /* Azerbaijan */ - COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0x1F1), /* Bosnia & Herzegovina */ - COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0x050), /* Barbados */ - COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0x1F1), /* Bangladesh */ - COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0x1FB), /* Belgium */ - COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0x0B0), /* Burkina Faso */ - COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0x1F1), /* Bulgaria */ - COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0x1F1), /* Bahrain */ - COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0x0B0), /* Burundi */ - COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0x0B0), /* Benin */ - COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x010), /* Brunei */ - COUNTRY_CHPLAN_ENT("BO", 0x30, 1, 0x1F1), /* Bolivia */ - COUNTRY_CHPLAN_ENT("BR", 0x34, 1, 0x1F1), /* Brazil */ - COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0x020), /* Bahamas */ - COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0x0F1), /* Botswana */ - COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0x1F1), /* Belarus */ - COUNTRY_CHPLAN_ENT("BZ", 0x34, 1, 0x000), /* Belize */ - COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0x1FB), /* Canada */ - COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x000), /* Cocos (Keeling) Islands (Australia) */ - COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0x0B0), /* Congo, Republic of the */ - COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0x0B0), /* Central African Republic */ - COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0x0B0), /* Congo, Democratic Republic of the. Zaire */ - COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0x1FB), /* Switzerland */ - COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0x1F1), /* Cote d'Ivoire */ - COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x000), /* Cook Islands */ - COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0x1F1), /* Chile */ - COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0x0B0), /* Cameroon */ - COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0x1FB), /* China */ - COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0x1F1), /* Colombia */ - COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0x1F1), /* Costa Rica */ - COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0x0B0), /* Cape Verde */ - COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x000), /* Christmas Island (Australia) */ - COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0x1FB), /* Cyprus */ - COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0x1FB), /* Czech Republic */ - COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0x1FB), /* Germany */ - COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x080), /* Djibouti */ - COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0x1FB), /* Denmark */ - COUNTRY_CHPLAN_ENT("DM", 0x34, 1, 0x000), /* Dominica */ - COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0x1F1), /* Dominican Republic */ - COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0x1F1), /* Algeria */ - COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0x1F1), /* Ecuador */ - COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0x1FB), /* Estonia */ - COUNTRY_CHPLAN_ENT("EG", 0x47, 0, 0x1F1), /* Egypt */ - COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x080), /* Western Sahara */ - COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x000), /* Eritrea */ - COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0x1FB), /* Spain, Canary Islands, Ceuta, Melilla */ - COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0x0B0), /* Ethiopia */ - COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0x1FB), /* Finland */ - COUNTRY_CHPLAN_ENT("FJ", 0x34, 1, 0x000), /* Fiji */ - COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x000), /* Falkland Islands (Islas Malvinas) (UK) */ - COUNTRY_CHPLAN_ENT("FM", 0x34, 1, 0x000), /* Micronesia, Federated States of (USA) */ - COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x000), /* Faroe Islands (Denmark) */ - COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0x1FB), /* France */ - COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0x0B0), /* Gabon */ - COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0x1FB), /* Great Britain (United Kingdom; England) */ - COUNTRY_CHPLAN_ENT("GD", 0x34, 1, 0x0B0), /* Grenada */ - COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x000), /* Georgia */ - COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x080), /* French Guiana */ - COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x000), /* Guernsey (UK) */ - COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0x1F1), /* Ghana */ - COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x000), /* Gibraltar (UK) */ - COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x000), /* Greenland (Denmark) */ - COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0x0B0), /* Gambia */ - COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x010), /* Guinea */ - COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x000), /* Guadeloupe (France) */ - COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0x0B0), /* Equatorial Guinea */ - COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0x1FB), /* Greece */ - COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x000), /* South Georgia and the Sandwich Islands (UK) */ - COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0x1F1), /* Guatemala */ - COUNTRY_CHPLAN_ENT("GU", 0x34, 1, 0x000), /* Guam (USA) */ - COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0x0B0), /* Guinea-Bissau */ - COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x000), /* Guyana */ - COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0x1FB), /* Hong Kong */ - COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x000), /* Heard and McDonald Islands (Australia) */ - COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0x1F1), /* Honduras */ - COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0x1F9), /* Croatia */ - COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0x050), /* Haiti */ - COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0x1FB), /* Hungary */ - COUNTRY_CHPLAN_ENT("ID", 0x54, 0, 0x1F3), /* Indonesia */ - COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0x1FB), /* Ireland */ - COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0x1F1), /* Israel */ - COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x000), /* Isle of Man (UK) */ - COUNTRY_CHPLAN_ENT("IN", 0x47, 1, 0x1F1), /* India */ - COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x000), /* Iraq */ - COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x000), /* Iran */ - COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0x1FB), /* Iceland */ - COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0x1FB), /* Italy */ - COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x000), /* Jersey (UK) */ - COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0x1F1), /* Jamaica */ - COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0x1FB), /* Jordan */ - COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0x1FF), /* Japan- Telec */ - COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0x1F9), /* Kenya */ - COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0x1F1), /* Kyrgyzstan */ - COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0x1F1), /* Cambodia */ - COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x000), /* Kiribati */ - COUNTRY_CHPLAN_ENT("KN", 0x34, 1, 0x000), /* Saint Kitts and Nevis */ - COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0x1FB), /* South Korea */ - COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0x1FB), /* Kuwait */ - COUNTRY_CHPLAN_ENT("KY", 0x34, 1, 0x000), /* Cayman Islands (UK) */ - COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x100), /* Kazakhstan */ - COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x000), /* Laos */ - COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0x1F1), /* Lebanon */ - COUNTRY_CHPLAN_ENT("LC", 0x34, 1, 0x000), /* Saint Lucia */ - COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0x1FB), /* Liechtenstein */ - COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0x1F1), /* Sri Lanka */ - COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0x0B0), /* Liberia */ - COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0x1F1), /* Lesotho */ - COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0x1FB), /* Lithuania */ - COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0x1FB), /* Luxembourg */ - COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0x1FB), /* Latvia */ - COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x000), /* Libya */ - COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0x1F1), /* Morocco */ - COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0x1FB), /* Monaco */ - COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0x1F1), /* Moldova */ - COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0x1F1), /* Montenegro */ - COUNTRY_CHPLAN_ENT("MF", 0x34, 1, 0x000), /* Saint Martin */ - COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x020), /* Madagascar */ - COUNTRY_CHPLAN_ENT("MH", 0x34, 1, 0x000), /* Marshall Islands (USA) */ - COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0x1F1), /* Republic of Macedonia (FYROM) */ - COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0x0B0), /* Mali */ - COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x000), /* Burma (Myanmar) */ - COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x000), /* Mongolia */ - COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x000), /* Macau */ - COUNTRY_CHPLAN_ENT("MP", 0x34, 1, 0x000), /* Northern Mariana Islands (USA) */ - COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x040), /* Martinique (France) */ - COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0x0A0), /* Mauritania */ - COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x000), /* Montserrat (UK) */ - COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0x1FB), /* Malta */ - COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0x0B0), /* Mauritius */ - COUNTRY_CHPLAN_ENT("MV", 0x26, 1, 0x000), /* Maldives */ - COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0x0B0), /* Malawi */ - COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x1F1), /* Mexico */ - COUNTRY_CHPLAN_ENT("MY", 0x63, 1, 0x1F1), /* Malaysia */ - COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0x1F1), /* Mozambique */ - COUNTRY_CHPLAN_ENT("NA", 0x26, 1, 0x100), /* Namibia */ - COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x000), /* New Caledonia */ - COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0x0B0), /* Niger */ - COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x000), /* Norfolk Island (Australia) */ - COUNTRY_CHPLAN_ENT("NG", 0x50, 1, 0x1F9), /* Nigeria */ - COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0x1F1), /* Nicaragua */ - COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0x1FB), /* Netherlands */ - COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0x1FB), /* Norway */ - COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0x0F0), /* Nepal */ - COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x000), /* Nauru */ - COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x000), /* Niue */ - COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0x1FB), /* New Zealand */ - COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0x1F9), /* Oman */ - COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0x1F1), /* Panama */ - COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0x1F1), /* Peru */ - COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x000), /* French Polynesia (France) */ - COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0x1F1), /* Papua New Guinea */ - COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0x1F1), /* Philippines */ - COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0x1F1), /* Pakistan */ - COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0x1FB), /* Poland */ - COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x000), /* Saint Pierre and Miquelon (France) */ - COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0x1F1), /* Puerto Rico */ - COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0x1FB), /* Portugal */ - COUNTRY_CHPLAN_ENT("PW", 0x34, 1, 0x000), /* Palau */ - COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0x1F1), /* Paraguay */ - COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0x1F9), /* Qatar */ - COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x000), /* Reunion (France) */ - COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0x1F1), /* Romania */ - COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0x1F1), /* Serbia, Kosovo */ - COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0x1FB), /* Russia(fac/gost), Kaliningrad */ - COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0x0B0), /* Rwanda */ - COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0x1FB), /* Saudi Arabia */ - COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x000), /* Solomon Islands */ - COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0x090), /* Seychelles */ - COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0x1FB), /* Sweden */ - COUNTRY_CHPLAN_ENT("SG", 0x26, 1, 0x1FB), /* Singapore */ - COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x000), /* Saint Helena (UK) */ - COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0x1FB), /* Slovenia */ - COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x000), /* Svalbard (Norway) */ - COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0x1FB), /* Slovakia */ - COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0x0B0), /* Sierra Leone */ - COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x000), /* San Marino */ - COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0x1F1), /* Senegal */ - COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x000), /* Somalia */ - COUNTRY_CHPLAN_ENT("SR", 0x34, 1, 0x000), /* Suriname */ - COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0x080), /* Sao Tome and Principe */ - COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0x1F1), /* El Salvador */ - COUNTRY_CHPLAN_ENT("SX", 0x34, 1, 0x000), /* Sint Marteen */ - COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x020), /* Swaziland */ - COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x000), /* Turks and Caicos Islands (UK) */ - COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0x0B0), /* Chad */ - COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x080), /* French Southern and Antarctic Lands (FR Southern Territories) */ - COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0x0B0), /* Togo */ - COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0x1F1), /* Thailand */ - COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x040), /* Tajikistan */ - COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x000), /* Tokelau */ - COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x000), /* Turkmenistan */ - COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0x1F1), /* Tunisia */ - COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x000), /* Tonga */ - COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0x1F1), /* Turkey, Northern Cyprus */ - COUNTRY_CHPLAN_ENT("TT", 0x42, 1, 0x1F1), /* Trinidad & Tobago */ - COUNTRY_CHPLAN_ENT("TW", 0x62, 1, 0x1FF), /* Taiwan */ - COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0x0F0), /* Tanzania */ - COUNTRY_CHPLAN_ENT("UA", 0x36, 1, 0x1FB), /* Ukraine */ - COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0x0F1), /* Uganda */ - COUNTRY_CHPLAN_ENT("US", 0x62, 1, 0x1FF), /* United States of America (USA) */ - COUNTRY_CHPLAN_ENT("UY", 0x34, 1, 0x1F1), /* Uruguay */ - COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0x0F0), /* Uzbekistan */ - COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x000), /* Holy See (Vatican City) */ - COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0x010), /* Saint Vincent and the Grenadines */ - COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0x1F1), /* Venezuela */ - COUNTRY_CHPLAN_ENT("VI", 0x34, 1, 0x000), /* United States Virgin Islands (USA) */ - COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0x1F1), /* Vietnam */ - COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x000), /* Vanuatu */ - COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x000), /* Wallis and Futuna (France) */ - COUNTRY_CHPLAN_ENT("WS", 0x34, 1, 0x000), /* Samoa */ - COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x040), /* Yemen */ - COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x080), /* Mayotte (France) */ - COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0x1F1), /* South Africa */ - COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0x0B0), /* Zambia */ - COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0x1F1), /* Zimbabwe */ -}; -/* -* rtw_get_chplan_from_country - -* @country_code: string of country code -* -* Return pointer of struct country_chplan entry or NULL when unsupported country_code is given -*/ -const struct country_chplan *rtw_get_chplan_from_country(const char *country_code) +inline void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name + , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt) { - const struct country_chplan *ent = NULL; - const struct country_chplan *map = NULL; - u16 map_sz = 0; - char code[2]; - int i; + rtw_txpwr_lmt_add_with_nlen(rfctl, regd_name, strlen(regd_name) + , band, bw, tlrs, ntx_idx, ch_idx, lmt); +} - code[0] = alpha_to_upper(country_code[0]); - code[1] = alpha_to_upper(country_code[1]); +struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name) +{ + struct txpwr_lmt_ent *ent; + _list *cur, *head; + u8 found = 0; -#if !defined(CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP) && RTW_DEF_MODULE_REGULATORY_CERT - ent = rtw_def_module_get_chplan_from_country(code); - if (ent != NULL) - goto exit; -#endif + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); -#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP - map = CUSTOMIZED_country_chplan_map; - map_sz = sizeof(CUSTOMIZED_country_chplan_map) / sizeof(struct country_chplan); -#else - map = country_chplan_map; - map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan); -#endif + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); - for (i = 0; i < map_sz; i++) { - if (strncmp(code, map[i].alpha2, 2) == 0) { - ent = &map[i]; + if (strcmp(ent->regd_name, regd_name) == 0) { + found = 1; break; } } -exit: - #if RTW_DEF_MODULE_REGULATORY_CERT - if (ent && !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT)) - ent = NULL; - #endif + if (found) + return ent; + return NULL; +} + +inline struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name) +{ + struct txpwr_lmt_ent *ent; + _irqL irqL; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name); + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); return ent; } +void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl) +{ + struct txpwr_lmt_ent *ent; + _irqL irqL; + _list *cur, *head; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + if (ent->regd_name == rfctl->regd_name) + rfctl->regd_name = regd_str(TXPWR_LMT_NONE); + rtw_list_delete(&ent->list); + rtw_vmfree((u8 *)ent, sizeof(struct txpwr_lmt_ent) + strlen(ent->regd_name) + 1); + } + rfctl->txpwr_regd_num = 0; + + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); +} +#endif /* CONFIG_TXPWR_LIMIT */ + int rtw_ch_to_bb_gain_sel(int ch) { int sel = -1; @@ -1027,7 +1213,6 @@ s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch) s8 kfree_offset = 0; #ifdef CONFIG_RF_POWER_TRIM - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); struct kfree_data_t *kfree_data = GET_KFREE_DATA(padapter); s8 bb_gain_sel = rtw_ch_to_bb_gain_sel(ch); @@ -1053,7 +1238,9 @@ s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch) void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset) { +#if !defined(CONFIG_RTL8814A) && !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8821C) u8 write_value; +#endif u8 target_path = 0; u32 val32 = 0; @@ -1092,6 +1279,12 @@ void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset) rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value); break; #endif /* CONFIG_RTL8188F */ +#ifdef CONFIG_RTL8188GTV + case RTL8188GTV: + write_value = RF_TX_GAIN_OFFSET_8188GTV(offset); + rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value); + break; +#endif /* CONFIG_RTL8188GTV */ #ifdef CONFIG_RTL8192E case RTL8192E: write_value = RF_TX_GAIN_OFFSET_8192E(offset); @@ -1105,10 +1298,11 @@ void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset) rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value); break; #endif /* CONFIG_RTL8821A */ -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) +#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8192F) case RTL8814A: case RTL8822B: case RTL8821C: + case RTL8192F: RTW_INFO("\nkfree by PhyDM on the sw CH. path %d\n", path); break; #endif /* CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */ @@ -1149,34 +1343,6 @@ void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch) } } -inline u8 rtw_is_5g_band1(u8 ch) -{ - if (ch >= 36 && ch <= 48) - return 1; - return 0; -} - -inline u8 rtw_is_5g_band2(u8 ch) -{ - if (ch >= 52 && ch <= 64) - return 1; - return 0; -} - -inline u8 rtw_is_5g_band3(u8 ch) -{ - if (ch >= 100 && ch <= 144) - return 1; - return 0; -} - -inline u8 rtw_is_5g_band4(u8 ch) -{ - if (ch >= 149 && ch <= 177) - return 1; - return 0; -} - inline u8 rtw_is_dfs_range(u32 hi, u32 lo) { return rtw_is_range_overlap(hi, lo, 5720 + 10, 5260 - 10); @@ -1204,7 +1370,7 @@ u8 rtw_is_dfs_chbw(u8 ch, u8 bw, u8 offset) bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region) { - return (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5660 + 10, 5600 - 10)) ? _TRUE : _FALSE; + return (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5650, 5600)) ? _TRUE : _FALSE; } bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region) diff --git a/core/rtw_rm.c b/core/rtw_rm.c new file mode 100644 index 0000000..6576597 --- /dev/null +++ b/core/rtw_rm.c @@ -0,0 +1,2470 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include +#include +#include "rtw_rm_fsm.h" + +#define pstr(s) s+strlen(s) + +u8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf) +{ +#ifdef CONFIG_RTW_80211K + struct rm_event *pev = (struct rm_event *)pbuf; + + _rm_post_event(padapter, pev->rmid, pev->evid); + rm_handler(padapter, pev); +#endif + return H2C_SUCCESS; +} + +#ifdef CONFIG_RTW_80211K + +/* 802.11-2012 Table E-1 Operationg classes in United States */ +static RT_OPERATING_CLASS RTW_OP_CLASS_US[] = { + /* 0, OP_CLASS_NULL */ { 0, 0, {}}, + /* 1, OP_CLASS_1 */ {115, 4, {36, 40, 44, 48}}, + /* 2, OP_CLASS_2 */ {118, 4, {52, 56, 60, 64}}, + /* 3, OP_CLASS_3 */ {124, 4, {149, 153, 157, 161}}, + /* 4, OP_CLASS_4 */ {121, 11, {100, 104, 108, 112, 116, 120, 124, + 128, 132, 136, 140}}, + /* 5, OP_CLASS_5 */ {125, 5, {149, 153, 157, 161, 165}}, + /* 6, OP_CLASS_12 */ { 81, 11, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}} +}; + +struct cmd_meas_type_ { + u8 id; + char *name; +}; + +char *rm_type_req_name(u8 meas_type) { + + switch (meas_type) { + case basic_req: + return "basic_req"; + case cca_req: + return "cca_req"; + case rpi_histo_req: + return "rpi_histo_req"; + case ch_load_req: + return "ch_load_req"; + case noise_histo_req: + return "noise_histo_req"; + case bcn_req: + return "bcn_req"; + case frame_req: + return "frame_req"; + case sta_statis_req: + return "sta_statis_req"; + } + return "unknown_req"; +}; + +char *rm_type_rep_name(u8 meas_type) { + + switch (meas_type) { + case basic_rep: + return "basic_rep"; + case cca_rep: + return "cca_rep"; + case rpi_histo_rep: + return "rpi_histo_rep"; + case ch_load_rep: + return "ch_load_rep"; + case noise_histo_rep: + return "noise_histo_rep"; + case bcn_rep: + return "bcn_rep"; + case frame_rep: + return "frame_rep"; + case sta_statis_rep: + return "sta_statis_rep"; + } + return "unknown_rep"; +}; + +char *rm_en_cap_name(enum rm_cap_en en) +{ + switch (en) { + case RM_LINK_MEAS_CAP_EN: + return "RM_LINK_MEAS_CAP_EN"; + case RM_NB_REP_CAP_EN: + return "RM_NB_REP_CAP_EN"; + case RM_PARAL_MEAS_CAP_EN: + return "RM_PARAL_MEAS_CAP_EN"; + case RM_REPEAT_MEAS_CAP_EN: + return "RM_REPEAT_MEAS_CAP_EN"; + case RM_BCN_PASSIVE_MEAS_CAP_EN: + return "RM_BCN_PASSIVE_MEAS_CAP_EN"; + case RM_BCN_ACTIVE_MEAS_CAP_EN: + return "RM_BCN_ACTIVE_MEAS_CAP_EN"; + case RM_BCN_TABLE_MEAS_CAP_EN: + return "RM_BCN_TABLE_MEAS_CAP_EN"; + case RM_BCN_MEAS_REP_COND_CAP_EN: + return "RM_BCN_MEAS_REP_COND_CAP_EN"; + + case RM_FRAME_MEAS_CAP_EN: + return "RM_FRAME_MEAS_CAP_EN"; + case RM_CH_LOAD_CAP_EN: + return "RM_CH_LOAD_CAP_EN"; + case RM_NOISE_HISTO_CAP_EN: + return "RM_NOISE_HISTO_CAP_EN"; + case RM_STATIS_MEAS_CAP_EN: + return "RM_STATIS_MEAS_CAP_EN"; + case RM_LCI_MEAS_CAP_EN: + return "RM_LCI_MEAS_CAP_EN"; + case RM_LCI_AMIMUTH_CAP_EN: + return "RM_LCI_AMIMUTH_CAP_EN"; + case RM_TRANS_STREAM_CAT_MEAS_CAP_EN: + return "RM_TRANS_STREAM_CAT_MEAS_CAP_EN"; + case RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN: + return "RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN"; + + case RM_AP_CH_REP_CAP_EN: + return "RM_AP_CH_REP_CAP_EN"; + case RM_RM_MIB_CAP_EN: + return "RM_RM_MIB_CAP_EN"; + case RM_OP_CH_MAX_MEAS_DUR0: + return "RM_OP_CH_MAX_MEAS_DUR0"; + case RM_OP_CH_MAX_MEAS_DUR1: + return "RM_OP_CH_MAX_MEAS_DUR1"; + case RM_OP_CH_MAX_MEAS_DUR2: + return "RM_OP_CH_MAX_MEAS_DUR2"; + case RM_NONOP_CH_MAX_MEAS_DUR0: + return "RM_NONOP_CH_MAX_MEAS_DUR0"; + case RM_NONOP_CH_MAX_MEAS_DUR1: + return "RM_NONOP_CH_MAX_MEAS_DUR1"; + case RM_NONOP_CH_MAX_MEAS_DUR2: + return "RM_NONOP_CH_MAX_MEAS_DUR2"; + + case RM_MEAS_PILOT_CAP0: + return "RM_MEAS_PILOT_CAP0"; /* 24-26 */ + case RM_MEAS_PILOT_CAP1: + return "RM_MEAS_PILOT_CAP1"; + case RM_MEAS_PILOT_CAP2: + return "RM_MEAS_PILOT_CAP2"; + case RM_MEAS_PILOT_TRANS_INFO_CAP_EN: + return "RM_MEAS_PILOT_TRANS_INFO_CAP_EN"; + case RM_NB_REP_TSF_OFFSET_CAP_EN: + return "RM_NB_REP_TSF_OFFSET_CAP_EN"; + case RM_RCPI_MEAS_CAP_EN: + return "RM_RCPI_MEAS_CAP_EN"; /* 29 */ + case RM_RSNI_MEAS_CAP_EN: + return "RM_RSNI_MEAS_CAP_EN"; + case RM_BSS_AVG_ACCESS_DELAY_CAP_EN: + return "RM_BSS_AVG_ACCESS_DELAY_CAP_EN"; + + case RM_AVALB_ADMIS_CAPACITY_CAP_EN: + return "RM_AVALB_ADMIS_CAPACITY_CAP_EN"; + case RM_ANT_CAP_EN: + return "RM_ANT_CAP_EN"; + case RM_RSVD: + case RM_MAX: + default: + break; + } + return "unknown"; +} + +int rm_en_cap_chk_and_set(struct rm_obj *prm, enum rm_cap_en en) +{ + int idx; + u8 cap; + + + if (en >= RM_MAX) + return _FALSE; + + idx = en / 8; + cap = prm->psta->padapter->rmpriv.rm_en_cap_def[idx]; + + if (!(cap & BIT(en - (idx*8)))) { + RTW_INFO("RM: %s incapable\n",rm_en_cap_name(en)); + rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP); + return _FALSE; + } + return _SUCCESS; +} + +static u8 rm_get_oper_class_via_ch(u8 ch) +{ + int i,j,sz; + + + sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS); + + for (i = 0; i < sz; i++) { + for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) { + if ( ch == RTW_OP_CLASS_US[i].Channel[j]) { + RTW_INFO("RM: ch %u in oper_calss %u\n", + ch, RTW_OP_CLASS_US[i].global_op_class); + return RTW_OP_CLASS_US[i].global_op_class; + break; + } + } + } + return 0; +} + +static u8 rm_get_ch_set( + struct rtw_ieee80211_channel *pch_set, u8 op_class, u8 ch_num) +{ + int i,j,sz; + u8 ch_amount = 0; + + + sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS); + + if (ch_num != 0) { + pch_set[0].hw_value = ch_num; + ch_amount = 1; + RTW_INFO("RM: meas_ch->hw_value = %u\n", pch_set->hw_value); + goto done; + } + + for (i = 0; i < sz; i++) { + + if (RTW_OP_CLASS_US[i].global_op_class == op_class) { + + for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) { + pch_set[j].hw_value = + RTW_OP_CLASS_US[i].Channel[j]; + RTW_INFO("RM: meas_ch[%d].hw_value = %u\n", + j, pch_set[j].hw_value); + } + ch_amount = RTW_OP_CLASS_US[i].Len; + break; + } + } +done: + return ch_amount; +} + +static int is_wildcard_bssid(u8 *bssid) +{ + int i; + u8 val8 = 0xff; + + + for (i=0;i<6;i++) + val8 &= bssid[i]; + + if (val8 == 0xff) + return _SUCCESS; + return _FALSE; +} + +/* for caller outside rm */ +u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct rm_obj *prm; + + + prm = rm_alloc_rmobj(padapter); + + if (prm == NULL) { + RTW_ERR("RM: unable to alloc rm obj for requeset\n"); + return _FALSE; + } + + prm->psta = psta; + prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS; + prm->q.diag_token = pmlmeinfo->dialogToken++; + prm->q.m_token = 1; + + prm->rmid = psta->cmn.aid << 16 + | prm->q.diag_token << 8 + | RM_MASTER; + + prm->q.action_code = RM_ACT_NB_REP_REQ; + + #if 0 + if (pmac) { /* find sta_info according to bssid */ + pmac += 4; /* skip mac= */ + if (hwaddr_parse(pmac, bssid) == NULL) { + sprintf(pstr(s), "Err: \nincorrect mac format\n"); + return _FAIL; + } + psta = rm_get_sta(padapter, 0xff, bssid); + } + #endif + + /* enquee rmobj */ + rm_enqueue_rmobj(padapter, prm, _FALSE); + + RTW_INFO("RM: rmid=%x add req to " MAC_FMT "\n", + prm->rmid, MAC_ARG(psta->cmn.mac_addr)); + + return _SUCCESS; +} + + +static u8 *build_wlan_hdr(_adapter *padapter, struct xmit_frame *pmgntframe, + struct sta_info *psta, u16 frame_type) +{ + u8 *pframe; + u16 *fctrl; + struct pkt_attrib *pattr; + struct rtw_ieee80211_hdr *pwlanhdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + + + /* update attribute */ + pattr = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattr); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, + get_my_bssid(&(pmlmeinfo->network)),ETH_ALEN); + + RTW_INFO("RM: dst = " MAC_FMT "\n", MAC_ARG(pwlanhdr->addr1)); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFragNum(pframe, 0); + + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattr->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + return pframe; +} + +void rm_set_rep_mode(struct rm_obj *prm, u8 mode) +{ + + RTW_INFO("RM: rmid=%x set %s\n", + prm->rmid, + mode|MEAS_REP_MOD_INCAP?"INCAP": + mode|MEAS_REP_MOD_REFUSE?"REFUSE": + mode|MEAS_REP_MOD_LATE?"LATE":""); + + prm->p.m_mode |= mode; +} + +int issue_null_reply(struct rm_obj *prm) +{ + int len=0, my_len; + u8 *pframe, m_mode; + _adapter *padapter = prm->psta->padapter; + struct pkt_attrib *pattr; + struct xmit_frame *pmgntframe; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + + + m_mode = prm->p.m_mode; + if (m_mode || prm->p.rpt == 0) { + RTW_INFO("RM: rmid=%x reply (%s repeat=%d)\n", + prm->rmid, + m_mode&MEAS_REP_MOD_INCAP?"INCAP": + m_mode&MEAS_REP_MOD_REFUSE?"REFUSE": + m_mode&MEAS_REP_MOD_LATE?"LATE":"no content", + prm->p.rpt); + } + + switch (prm->p.action_code) { + case RM_ACT_RADIO_MEAS_REQ: + len = 8; + break; + case RM_ACT_NB_REP_REQ: + len = 3; + break; + case RM_ACT_LINK_MEAS_REQ: + len = 3; + break; + default: + break; + } + + if (len==0) + return _FALSE; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__); + return _FALSE; + } + pattr = &pmgntframe->attrib; + pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION); + pframe = rtw_set_fixed_ie(pframe, 3, &prm->p.category, &pattr->pktlen); + + my_len = 0; + if (len>5) { + prm->p.len = len - 3 - 2; + pframe = rtw_set_fixed_ie(pframe, len - 3, + &prm->p.e_id, &my_len); + } + + pattr->pktlen += my_len; + pattr->last_txcmdsz = pattr->pktlen; + dump_mgntframe(padapter, pmgntframe); + + return _SUCCESS; +} + +int ready_for_scan(struct rm_obj *prm) +{ + _adapter *padapter = prm->psta->padapter; + u8 ssc_chk; + + if (!rtw_is_adapter_up(padapter)) + return _FALSE; + + ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE); + + if (ssc_chk == SS_ALLOW) + return _SUCCESS; + + return _FALSE; +} + +int rm_sitesurvey(struct rm_obj *prm) +{ + int meas_ch_num=0; + u8 ch_num=0, op_class=0, val8; + struct rtw_ieee80211_channel *pch_set; + struct sitesurvey_parm parm; + + + RTW_INFO("RM: rmid=%x %s\n",prm->rmid, __func__); + + pch_set = &prm->q.ch_set[0]; + + _rtw_memset(pch_set, 0, + sizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM); + + if (prm->q.ch_num == 0) { + /* ch_num=0 : scan all ch in operating class */ + op_class = prm->q.op_class; + + } else if (prm->q.ch_num == 255) { + /* 802.11 p.499 */ + /* ch_num=255 : scan all ch in current operating class */ + op_class = rm_get_oper_class_via_ch( + (u8)prm->psta->padapter->mlmeextpriv.cur_channel); + } else + ch_num = prm->q.ch_num; + + /* get means channel */ + meas_ch_num = rm_get_ch_set(pch_set, op_class, ch_num); + prm->q.ch_set_ch_amount = meas_ch_num; + + _rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm)); + _rtw_memcpy(parm.ch, pch_set, + sizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM); + + _rtw_memcpy(&parm.ssid[0], &prm->q.opt.bcn.ssid, IW_ESSID_MAX_SIZE); + + parm.ssid_num = 1; + parm.scan_mode = prm->q.m_mode; + parm.ch_num = meas_ch_num; + parm.igi = 0; + parm.token = prm->rmid; + parm.duration = prm->q.meas_dur; + /* parm.bw = BW_20M; */ + + rtw_sitesurvey_cmd(prm->psta->padapter, &parm); + + return _SUCCESS; +} + +static u8 translate_percentage_to_rcpi(u32 SignalStrengthIndex) +{ + s32 SignalPower; /* in dBm. */ + u8 rcpi; + + /* Translate to dBm (x=y-100) */ + SignalPower = SignalStrengthIndex - 100; + + /* RCPI = Int{(Power in dBm + 110)*2} for 0dBm > Power > -110dBm + * 0 : power <= -110.0 dBm + * 1 : power = -109.5 dBm + * 2 : power = -109.0 dBm + */ + + rcpi = (SignalPower + 110)*2; + return rcpi; +} + +static int rm_parse_ch_load_s_elem(struct rm_obj *prm, u8 *pbody, int req_len) +{ + u8 *popt_id; + int i, p=0; /* position */ + int len = req_len; + + + prm->q.opt_s_elem_len = len; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n", len); +#endif + while (len) { + + switch (pbody[p]) { + case ch_load_rep_info: + /* check RM_EN */ + rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN); + + _rtw_memcpy(&(prm->q.opt.clm.rep_cond), + &pbody[p+2], sizeof(prm->q.opt.clm.rep_cond)); + + RTW_INFO("RM: ch_load_rep_info=%u:%u\n", + prm->q.opt.clm.rep_cond.cond, + prm->q.opt.clm.rep_cond.threshold); + break; + default: + break; + + } + len = len - (int)pbody[p+1] - 2; + p = p + (int)pbody[p+1] + 2; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n",len); +#endif + } + return _SUCCESS; +} + +static int rm_parse_noise_histo_s_elem(struct rm_obj *prm, + u8 *pbody, int req_len) +{ + u8 *popt_id; + int i, p=0; /* position */ + int len = req_len; + + + prm->q.opt_s_elem_len = len; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n", len); +#endif + + while (len) { + + switch (pbody[p]) { + case noise_histo_rep_info: + /* check RM_EN */ + rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN); + + _rtw_memcpy(&(prm->q.opt.nhm.rep_cond), + &pbody[p+2], sizeof(prm->q.opt.nhm.rep_cond)); + + RTW_INFO("RM: noise_histo_rep_info=%u:%u\n", + prm->q.opt.nhm.rep_cond.cond, + prm->q.opt.nhm.rep_cond.threshold); + break; + default: + break; + + } + len = len - (int)pbody[p+1] - 2; + p = p + (int)pbody[p+1] + 2; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n",len); +#endif + } + return _SUCCESS; +} + +static int rm_parse_bcn_req_s_elem(struct rm_obj *prm, u8 *pbody, int req_len) +{ + u8 *popt_id; + int i, p=0; /* position */ + int len = req_len; + + + /* opt length,2:pbody[0]+ pbody[1] */ + /* first opt id : pbody[18] */ + + prm->q.opt_s_elem_len = len; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n", len); +#endif + + popt_id = prm->q.opt.bcn.opt_id; + while (len && prm->q.opt.bcn.opt_id_num < BCN_REQ_OPT_MAX_NUM) { + + switch (pbody[p]) { + case bcn_req_ssid: + RTW_INFO("bcn_req_ssid\n"); + +#if (DBG_BCN_REQ_WILDCARD) + RTW_INFO("DBG set ssid to WILDCARD\n"); +#else +#if (DBG_BCN_REQ_SSID) + RTW_INFO("DBG set ssid to %s\n",DBG_BCN_REQ_SSID_NAME); + i = strlen(DBG_BCN_REQ_SSID_NAME); + prm->q.opt.bcn.ssid.SsidLength = i; + _rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid), + DBG_BCN_REQ_SSID_NAME, i); + +#else /* original */ + prm->q.opt.bcn.ssid.SsidLength = pbody[p+1]; + _rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid), + &pbody[p+2], pbody[p+1]); +#endif +#endif + + RTW_INFO("RM: bcn_req_ssid=%s\n", + prm->q.opt.bcn.ssid.Ssid); + + popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p]; + break; + + case bcn_req_rep_info: + /* check RM_EN */ + rm_en_cap_chk_and_set(prm, RM_BCN_MEAS_REP_COND_CAP_EN); + + _rtw_memcpy(&(prm->q.opt.bcn.rep_cond), + &pbody[p+2], sizeof(prm->q.opt.bcn.rep_cond)); + + RTW_INFO("bcn_req_rep_info=%u:%u\n", + prm->q.opt.bcn.rep_cond.cond, + prm->q.opt.bcn.rep_cond.threshold); + + /*popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];*/ + break; + + case bcn_req_rep_detail: +#if DBG_BCN_REQ_DETAIL + prm->q.opt.bcn.rep_detail = 2; /* all IE in beacon */ +#else + prm->q.opt.bcn.rep_detail = pbody[p+2]; +#endif + popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p]; + +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: report_detail=%d\n", + prm->q.opt.bcn.rep_detail); +#endif + break; + + case bcn_req_req: + RTW_INFO("RM: bcn_req_req\n"); + + prm->q.opt.bcn.req_start = rtw_malloc(pbody[p+1]); + + if (prm->q.opt.bcn.req_start == NULL) { + RTW_ERR("RM: req_start malloc fail!!\n"); + break; + } + + for (i = 0; i < pbody[p+1]; i++) + *((prm->q.opt.bcn.req_start)+i) = + pbody[p+2+i]; + + prm->q.opt.bcn.req_len = pbody[p+1]; + popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p]; + break; + + case bcn_req_ac_ch_rep: +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: bcn_req_ac_ch_rep\n"); +#endif + popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p]; + break; + + default: + break; + + } + len = len - (int)pbody[p+1] - 2; + p = p + (int)pbody[p+1] + 2; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: opt_s_elem_len=%d\n",len); +#endif + } + + return _SUCCESS; +} + +static int rm_parse_meas_req(struct rm_obj *prm, u8 *pbody) +{ + int p; /* position */ + int req_len; + + + req_len = (int)pbody[1]; + p = 5; + + prm->q.op_class = pbody[p++]; + prm->q.ch_num = pbody[p++]; + prm->q.rand_intvl = le16_to_cpu(*(u16*)(&pbody[p])); + p+=2; + prm->q.meas_dur = le16_to_cpu(*(u16*)(&pbody[p])); + p+=2; + + if (prm->q.m_type == bcn_req) { + /* + * 0: passive + * 1: active + * 2: bcn_table + */ + prm->q.m_mode = pbody[p++]; + + /* BSSID */ + _rtw_memcpy(&(prm->q.bssid), &pbody[p], 6); + p+=6; + + /* + * default, used when Reporting detail subelement + * is not included in Beacon Request + */ + prm->q.opt.bcn.rep_detail = 2; + } + + if (req_len-(p-2) <= 0) /* without sub-element */ + return _SUCCESS; + + switch (prm->q.m_type) { + case bcn_req: + rm_parse_bcn_req_s_elem(prm, &pbody[p], req_len-(p-2)); + break; + case ch_load_req: + rm_parse_ch_load_s_elem(prm, &pbody[p], req_len-(p-2)); + break; + case noise_histo_req: + rm_parse_noise_histo_s_elem(prm, &pbody[p], req_len-(p-2)); + break; + default: + break; + } + + return _SUCCESS; +} + +/* receive measurement request */ +int rm_recv_radio_mens_req(_adapter *padapter, + union recv_frame *precv_frame, struct sta_info *psta) +{ + struct rm_obj *prm; + struct rm_priv *prmpriv = &padapter->rmpriv; + u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data + + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 *pmeas_body = &pdiag_body[5]; + u8 rmid, update = 0; + + +#if 0 + /* search existing rm_obj */ + rmid = psta->cmn.aid << 16 + | pdiag_body[2] << 8 + | RM_SLAVE; + + prm = rm_get_rmobj(padapter, rmid); + if (prm) { + RTW_INFO("RM: Found an exist meas rmid=%u\n", rmid); + update = 1; + } else +#endif + prm = rm_alloc_rmobj(padapter); + + if (prm == NULL) { + RTW_ERR("RM: unable to alloc rm obj for requeset\n"); + return _FALSE; + } + + prm->psta = psta; + prm->q.diag_token = pdiag_body[2]; + prm->q.rpt = le16_to_cpu(*(u16*)(&pdiag_body[3])); + + /* Figure 8-104 Measurement Requested format */ + prm->q.e_id = pmeas_body[0]; + prm->q.m_token = pmeas_body[2]; + prm->q.m_mode = pmeas_body[3]; + prm->q.m_type = pmeas_body[4]; + + prm->rmid = psta->cmn.aid << 16 + | prm->q.diag_token << 8 + | RM_SLAVE; + + RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid, + MAC_ARG(prm->psta->cmn.mac_addr)); + +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: element_id = %d\n", prm->q.e_id); + RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]); + RTW_INFO("RM: meas_token = %d\n", prm->q.m_token); + RTW_INFO("RM: meas_mode = %d\n", prm->q.m_mode); + RTW_INFO("RM: meas_type = %d\n", prm->q.m_type); +#endif + + if (prm->q.e_id != _MEAS_REQ_IE_) /* 38 */ + return _FALSE; + + switch (prm->q.m_type) { + case bcn_req: + RTW_INFO("RM: recv beacon_request\n"); + switch (prm->q.m_mode) { + case bcn_req_passive: + rm_en_cap_chk_and_set(prm, RM_BCN_PASSIVE_MEAS_CAP_EN); + break; + case bcn_req_active: + rm_en_cap_chk_and_set(prm, RM_BCN_ACTIVE_MEAS_CAP_EN); + break; + case bcn_req_bcn_table: + rm_en_cap_chk_and_set(prm, RM_BCN_TABLE_MEAS_CAP_EN); + break; + default: + rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP); + break; + } + break; + case ch_load_req: + RTW_INFO("RM: recv ch_load_request\n"); + rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN); + break; + case noise_histo_req: + RTW_INFO("RM: recv noise_histogram_request\n"); + rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN); + break; + default: + RTW_INFO("RM: recv unknown request type 0x%02x\n", + prm->q.m_type); + rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP); + goto done; + } + rm_parse_meas_req(prm, pmeas_body); +done: + if (!update) + rm_enqueue_rmobj(padapter, prm, _FALSE); + + return _SUCCESS; +} + +/* receive measurement report */ +int rm_recv_radio_mens_rep(_adapter *padapter, + union recv_frame *precv_frame, struct sta_info *psta) +{ + int ret = _FALSE; + struct rm_obj *prm; + u32 rmid; + u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data + + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 *pmeas_body = &pdiag_body[3]; + + + rmid = psta->cmn.aid << 16 + | pdiag_body[2] << 8 + | RM_MASTER; + + prm = rm_get_rmobj(padapter, rmid); + if (prm == NULL) + return _FALSE; + + prm->p.action_code = pdiag_body[1]; + prm->p.diag_token = pdiag_body[2]; + + /* Figure 8-140 Measuremnt Report format */ + prm->p.e_id = pmeas_body[0]; + prm->p.m_token = pmeas_body[2]; + prm->p.m_mode = pmeas_body[3]; + prm->p.m_type = pmeas_body[4]; + + RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid, + MAC_ARG(prm->psta->cmn.mac_addr)); + +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: element_id = %d\n", prm->p.e_id); + RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]); + RTW_INFO("RM: meas_token = %d\n", prm->p.m_token); + RTW_INFO("RM: meas_mode = %d\n", prm->p.m_mode); + RTW_INFO("RM: meas_type = %d\n", prm->p.m_type); +#endif + if (prm->p.e_id != _MEAS_RSP_IE_) /* 39 */ + return _FALSE; + + RTW_INFO("RM: recv %s\n", rm_type_rep_name(prm->p.m_type)); + rm_post_event(padapter, prm->rmid, RM_EV_recv_rep); + + return ret; +} + +int rm_radio_mens_nb_rep(_adapter *padapter, + union recv_frame *precv_frame, struct sta_info *psta) +{ + u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data + + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 *pmeas_body = &pdiag_body[3]; + u32 len = precv_frame->u.hdr.len; + u32 rmid; + struct rm_obj *prm; + + + rmid = psta->cmn.aid << 16 + | pdiag_body[2] << 8 + | RM_MASTER; + + prm = rm_get_rmobj(padapter, rmid); + if (prm == NULL) + return _FALSE; + + prm->p.action_code = pdiag_body[1]; + prm->p.diag_token = pdiag_body[2]; + prm->p.e_id = pmeas_body[0]; + + RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid, + MAC_ARG(prm->psta->cmn.mac_addr)); + +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: element_id = %d\n", prm->p.e_id); + RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]); +#endif + rm_post_event(padapter, prm->rmid, RM_EV_recv_rep); + +#ifdef CONFIG_LAYER2_ROAMING + if (rtw_wnm_btm_candidates_survey(padapter + ,(pdiag_body + 3) + ,(len - sizeof(struct rtw_ieee80211_hdr_3addr)) + ,_FALSE) == _FAIL) + return _FALSE; +#endif + rtw_cfg80211_rx_rrm_action(padapter, precv_frame); + + return _TRUE; +} + +unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame) +{ + u32 ret = _FAIL; + u8 *pframe = NULL; + u8 *pframe_body = NULL; + u8 action_code = 0; + u8 diag_token = 0; + struct rtw_ieee80211_hdr_3addr *whdr; + struct sta_info *psta; + + + pframe = precv_frame->u.hdr.rx_data; + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), + GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; + + whdr = (struct rtw_ieee80211_hdr_3addr *)pframe; + RTW_INFO("RM: %s bssid = " MAC_FMT "\n", + __func__, MAC_ARG(whdr->addr2)); + + psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2); + + if (!psta) { + RTW_ERR("RM: psta not found\n"); + goto exit; + } + + pframe_body = (unsigned char *)(pframe + + sizeof(struct rtw_ieee80211_hdr_3addr)); + + /* Figure 8-438 radio measurement request frame Action field format */ + /* Category = pframe_body[0] = 5 (Radio Measurement) */ + action_code = pframe_body[1]; + diag_token = pframe_body[2]; + +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: %s radio_action=%x, diag_token=%x\n", __func__, + action_code, diag_token); +#endif + + switch (action_code) { + + case RM_ACT_RADIO_MEAS_REQ: + RTW_INFO("RM: RM_ACT_RADIO_MEAS_REQ\n"); + ret = rm_recv_radio_mens_req(padapter, precv_frame, psta); + break; + + case RM_ACT_RADIO_MEAS_REP: + RTW_INFO("RM: RM_ACT_RADIO_MEAS_REP\n"); + ret = rm_recv_radio_mens_rep(padapter, precv_frame, psta); + break; + + case RM_ACT_LINK_MEAS_REQ: + RTW_INFO("RM: RM_ACT_LINK_MEAS_REQ\n"); + break; + + case RM_ACT_LINK_MEAS_REP: + RTW_INFO("RM: RM_ACT_LINK_MEAS_REP\n"); + break; + + case RM_ACT_NB_REP_REQ: + RTW_INFO("RM: RM_ACT_NB_REP_REQ\n"); + break; + + case RM_ACT_NB_REP_RESP: + RTW_INFO("RM: RM_ACT_NB_REP_RESP\n"); + ret = rm_radio_mens_nb_rep(padapter, precv_frame, psta); + break; + + default: + /* TODO reply incabable */ + RTW_ERR("RM: unknown specturm management action %2x\n", + action_code); + break; + } +exit: + return ret; +} + +static u8 *rm_gen_bcn_detail_elem(_adapter *padapter, u8 *pframe, + struct rm_obj *prm, struct wlan_network *pnetwork, + unsigned int *fr_len) +{ + WLAN_BSSID_EX *pbss = &pnetwork->network; + unsigned int my_len; + int j, k, len; + u8 *plen; + u8 *ptr; + u8 val8, eid; + + + my_len = 0; + /* Reporting Detail values + * 0: No fixed length fields or elements + * 1: All fixed length fields and any requested elements + * in the Request info element if present + * 2: All fixed length fields and elements + * 3-255: Reserved + */ + + /* report_detail = 0 */ + if (prm->q.opt.bcn.rep_detail == 0 + || prm->q.opt.bcn.rep_detail > 2) { + return pframe; + } + + /* ID */ + val8 = 1; /* 1:reported frame body */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + plen = pframe; + val8 = 0; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* report_detail = 2 */ + if (prm->q.opt.bcn.rep_detail == 2) { + pframe = rtw_set_fixed_ie(pframe, pbss->IELength - 4, + pbss->IEs, &my_len); /* -4 remove FCS */ + goto done; + } + + /* report_detail = 1 */ + /* all fixed lenght fields */ + pframe = rtw_set_fixed_ie(pframe, + _FIXED_IE_LENGTH_, pbss->IEs, &my_len); + + for (j = 0; j < prm->q.opt.bcn.opt_id_num; j++) { + switch (prm->q.opt.bcn.opt_id[j]) { + case bcn_req_ssid: + /* SSID */ +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: bcn_req_ssid\n"); +#endif + pframe = rtw_set_ie(pframe, _SSID_IE_, + pbss->Ssid.SsidLength, + pbss->Ssid.Ssid, &my_len); + break; + case bcn_req_req: + if (prm->q.opt.bcn.req_start == NULL) + break; +#if (RM_MORE_DBG_MSG) + RTW_INFO("RM: bcn_req_req"); +#endif + for (k=0; kq.opt.bcn.req_len; k++) { + eid = prm->q.opt.bcn.req_start[k]; + + val8 = pbss->IELength - _FIXED_IE_LENGTH_; + ptr = rtw_get_ie(pbss->IEs + _FIXED_IE_LENGTH_, + eid, &len, val8); + + if (!ptr) + continue; +#if (RM_MORE_DBG_MSG) + switch (eid) { + case EID_QBSSLoad: + RTW_INFO("RM: EID_QBSSLoad\n"); + break; + case EID_HTCapability: + RTW_INFO("RM: EID_HTCapability\n"); + break; + case _MDIE_: + RTW_INFO("RM: EID_MobilityDomain\n"); + break; + default: + RTW_INFO("RM: EID %d todo\n",eid); + break; + } +#endif + pframe = rtw_set_ie(pframe, eid, + len,ptr+2, &my_len); + } /* for() */ + break; + case bcn_req_ac_ch_rep: + default: + RTW_INFO("RM: OPT %d TODO\n",prm->q.opt.bcn.opt_id[j]); + break; + } + } +done: + /* + * update my length + * content length does NOT include ID and LEN + */ + val8 = my_len - 2; + rtw_set_fixed_ie(plen, 1, &val8, &j); + + /* update length to caller */ + *fr_len += my_len; + + return pframe; +} + +static u8 rm_get_rcpi(struct rm_obj *prm, struct wlan_network *pnetwork) +{ + return translate_percentage_to_rcpi( + pnetwork->network.PhyInfo.SignalStrength); +} + +static u8 rm_get_rsni(struct rm_obj *prm, struct wlan_network *pnetwork) +{ + int i; + u8 val8, snr; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(prm->psta->padapter); + + + if (pnetwork->network.PhyInfo.is_cck_rate) { + /* current HW doesn't have CCK RSNI */ + /* 255 indicates RSNI is unavailable */ + val8 = 255; + } else { + snr = 0; + for (i = 0; i < pHalData->NumTotalRFPath; i++) { + snr += pnetwork->network.PhyInfo.rx_snr[i]; + } + snr = snr / pHalData->NumTotalRFPath; + val8 = (u8)(snr + 10)*2; + } + return val8; +} + +u8 rm_bcn_req_cond_mach(struct rm_obj *prm, struct wlan_network *pnetwork) +{ + u8 val8; + + + switch(prm->q.opt.bcn.rep_cond.cond) { + case bcn_rep_cond_immediately: + return _SUCCESS; + case bcn_req_cond_rcpi_greater: + val8 = rm_get_rcpi(prm, pnetwork); + if (val8 > prm->q.opt.bcn.rep_cond.threshold) + return _SUCCESS; + break; + case bcn_req_cond_rcpi_less: + val8 = rm_get_rcpi(prm, pnetwork); + if (val8 < prm->q.opt.bcn.rep_cond.threshold) + return _SUCCESS; + break; + case bcn_req_cond_rsni_greater: + val8 = rm_get_rsni(prm, pnetwork); + if (val8 != 255 && val8 > prm->q.opt.bcn.rep_cond.threshold) + return _SUCCESS; + break; + case bcn_req_cond_rsni_less: + val8 = rm_get_rsni(prm, pnetwork); + if (val8 != 255 && val8 < prm->q.opt.bcn.rep_cond.threshold) + return _SUCCESS; + break; + default: + RTW_ERR("RM: bcn_req cond %u not support\n", + prm->q.opt.bcn.rep_cond.cond); + break; + } + return _FALSE; +} + +static u8 *rm_bcn_rep_fill_scan_resule (struct rm_obj *prm, + u8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len) +{ + int snr, i; + u8 val8, *plen; + u16 val16; + u32 val32; + u64 val64; + PWLAN_BSSID_EX pbss; + unsigned int my_len; + _adapter *padapter = prm->psta->padapter; + + + my_len = 0; + /* meas ID */ + val8 = EID_MeasureReport; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* remember position form elelment length */ + plen = pframe; + + /* meas_rpt_len */ + /* default 3 = mode + token + type but no beacon content */ + val8 = 3; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* meas_token */ + val8 = prm->q.m_token; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* meas_rpt_mode F8-141 */ + val8 = prm->p.m_mode; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* meas_type T8-81 */ + val8 = bcn_rep; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + if (pnetwork == NULL) + goto done; + + pframe = rtw_set_fixed_ie(pframe, 1, &prm->q.op_class, &my_len); + + /* channel */ + pbss = &pnetwork->network; + val8 = pbss->Configuration.DSConfig; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* Actual Measurement StartTime */ + val64 = cpu_to_le64(prm->meas_start_time); + pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len); + + /* Measurement Duration */ + val16 = prm->meas_end_time - prm->meas_start_time; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len); + + /* TODO + * ReportedFrameInformation: + * 0 :beacon or probe rsp + * 1 :pilot frame + */ + val8 = 0; /* report frame info */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* RCPI */ + val8 = rm_get_rcpi(prm, pnetwork); + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* RSNI */ + val8 = rm_get_rsni(prm, pnetwork); + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* BSSID */ + pframe = rtw_set_fixed_ie(pframe, 6, (u8 *)&pbss->MacAddress, &my_len); + + /* + * AntennaID + * 0: unknown + * 255: multiple antenna (Diversity) + */ + val8 = 0; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* ParentTSF */ + val32 = prm->meas_start_time + pnetwork->network.PhyInfo.free_cnt; + pframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len); + + /* + * Generate Beacon detail + */ + pframe = rm_gen_bcn_detail_elem(padapter, pframe, + prm, pnetwork, &my_len); +done: + /* + * update my length + * content length does NOT include ID and LEN + */ + val8 = my_len - 2; + rtw_set_fixed_ie(plen, 1, &val8, &i); + + /* update length to caller */ + *fr_len += my_len; + + return pframe; +} + +static u8 *rm_gen_bcn_rep_ie (struct rm_obj *prm, + u8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len) +{ + int snr, i; + u8 val8, *plen; + u16 val16; + u32 val32; + u64 val64; + unsigned int my_len; + _adapter *padapter = prm->psta->padapter; + + + my_len = 0; + plen = pframe + 1; + pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len); + + /* Actual Measurement StartTime */ + val64 = cpu_to_le64(prm->meas_start_time); + pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len); + + /* Measurement Duration */ + val16 = prm->meas_end_time - prm->meas_start_time; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, 2, (u8*)&val16, &my_len); + + /* TODO + * ReportedFrameInformation: + * 0 :beacon or probe rsp + * 1 :pilot frame + */ + val8 = 0; /* report frame info */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* RCPI */ + val8 = rm_get_rcpi(prm, pnetwork); + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* RSNI */ + val8 = rm_get_rsni(prm, pnetwork); + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* BSSID */ + pframe = rtw_set_fixed_ie(pframe, 6, + (u8 *)&pnetwork->network.MacAddress, &my_len); + + /* + * AntennaID + * 0: unknown + * 255: multiple antenna (Diversity) + */ + val8 = 0; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* ParentTSF */ + val32 = prm->meas_start_time + pnetwork->network.PhyInfo.free_cnt; + pframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len); + + /* Generate Beacon detail */ + pframe = rm_gen_bcn_detail_elem(padapter, pframe, + prm, pnetwork, &my_len); +done: + /* + * update my length + * content length does NOT include ID and LEN + */ + val8 = my_len - 2; + rtw_set_fixed_ie(plen, 1, &val8, &i); + + /* update length to caller */ + *fr_len += my_len; + + return pframe; +} + +static int retrieve_scan_result(struct rm_obj *prm) +{ + _irqL irqL; + _list *plist, *phead; + _queue *queue; + _adapter *padapter = prm->psta->padapter; + struct rtw_ieee80211_channel *pch_set; + struct wlan_network *pnetwork = NULL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + int i, meas_ch_num=0; + PWLAN_BSSID_EX pbss; + unsigned int matched_network; + int len, my_len; + u8 buf_idx, *pbuf = NULL, *tmp_buf = NULL; + + + tmp_buf = rtw_malloc(MAX_XMIT_EXTBUF_SZ); + if (tmp_buf == NULL) + return 0; + + my_len = 0; + buf_idx = 0; + matched_network = 0; + queue = &(pmlmepriv->scanned_queue); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + /* get requested measurement channel set */ + pch_set = prm->q.ch_set; + meas_ch_num = prm->q.ch_set_ch_amount; + + /* search scan queue to find requested SSID */ + while (1) { + + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + pbss = &pnetwork->network; + + /* + * report network if requested channel set contains + * the channel matchs selected network + */ + if (rtw_chset_search_ch(adapter_to_chset(padapter), + pbss->Configuration.DSConfig) == 0) + goto next; + + if (rtw_mlme_band_check(padapter, pbss->Configuration.DSConfig) + == _FALSE) + goto next; + + if (rtw_validate_ssid(&(pbss->Ssid)) == _FALSE) + goto next; + + /* go through measurement requested channels */ + for (i = 0; i < meas_ch_num; i++) { + + /* match channel */ + if (pch_set[i].hw_value != pbss->Configuration.DSConfig) + continue; + + /* match bssid */ + if (is_wildcard_bssid(prm->q.bssid) == FALSE) + if (_rtw_memcmp(prm->q.bssid, + pbss->MacAddress, 6) == _FALSE) { + continue; + } + /* + * default wildcard SSID. wildcard SSID: + * A SSID value (null) used to represent all SSIDs + */ + + /* match ssid */ + if ((prm->q.opt.bcn.ssid.SsidLength > 0) && + _rtw_memcmp(prm->q.opt.bcn.ssid.Ssid, + pbss->Ssid.Ssid, + prm->q.opt.bcn.ssid.SsidLength) == _FALSE) + continue; + + /* match condition */ + if (rm_bcn_req_cond_mach(prm, pnetwork) == _FALSE) { + RTW_INFO("RM: condition mismatch ch %u ssid %s bssid "MAC_FMT"\n", + pch_set[i].hw_value, pbss->Ssid.Ssid, + MAC_ARG(pbss->MacAddress)); + RTW_INFO("RM: condition %u:%u\n", + prm->q.opt.bcn.rep_cond.cond, + prm->q.opt.bcn.rep_cond.threshold); + continue; + } + + /* Found a matched SSID */ + matched_network++; + + RTW_INFO("RM: ch %u Found %s bssid "MAC_FMT"\n", + pch_set[i].hw_value, pbss->Ssid.Ssid, + MAC_ARG(pbss->MacAddress)); + + len = 0; + _rtw_memset(tmp_buf, 0, MAX_XMIT_EXTBUF_SZ); + rm_gen_bcn_rep_ie(prm, tmp_buf, pnetwork, &len); +new_packet: + if (my_len == 0) { + pbuf = rtw_malloc(MAX_XMIT_EXTBUF_SZ); + if (pbuf == NULL) + goto fail; + prm->buf[buf_idx].pbuf = pbuf; + } + + if ((MAX_XMIT_EXTBUF_SZ - (my_len+len+24+4)) > 0) { + pbuf = rtw_set_fixed_ie(pbuf, + len, tmp_buf, &my_len); + prm->buf[buf_idx].len = my_len; + } else { + if (my_len == 0) /* not enough space */ + goto fail; + + my_len = 0; + buf_idx++; + goto new_packet; + } + } /* for() */ +next: + plist = get_next(plist); + } /* while() */ +fail: + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (tmp_buf) + rtw_mfree(tmp_buf, MAX_XMIT_EXTBUF_SZ); + + RTW_INFO("RM: Found %d matched %s\n", matched_network, + prm->q.opt.bcn.ssid.Ssid); + + if (prm->buf[buf_idx].pbuf) + return buf_idx+1; + + return 0; +} + +int issue_beacon_rep(struct rm_obj *prm) +{ + int i, my_len; + u8 *pframe; + _adapter *padapter = prm->psta->padapter; + struct pkt_attrib *pattr; + struct xmit_frame *pmgntframe; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + int pkt_num; + + + pkt_num = retrieve_scan_result(prm); + + if (pkt_num == 0) { + issue_null_reply(prm); + return _SUCCESS; + } + + for (i=0;iattrib; + pframe = build_wlan_hdr(padapter, + pmgntframe, prm->psta, WIFI_ACTION); + pframe = rtw_set_fixed_ie(pframe, + 3, &prm->p.category, &pattr->pktlen); + + my_len = 0; + pframe = rtw_set_fixed_ie(pframe, + prm->buf[i].len, prm->buf[i].pbuf, &my_len); + + pattr->pktlen += my_len; + pattr->last_txcmdsz = pattr->pktlen; + dump_mgntframe(padapter, pmgntframe); + } +fail: + for (i=0;ibuf[i].pbuf) { + rtw_mfree(prm->buf[i].pbuf, MAX_XMIT_EXTBUF_SZ); + prm->buf[i].pbuf = NULL; + prm->buf[i].len = 0; + } + } + return _SUCCESS; +} + +/* neighbor request */ +int issue_nb_req(struct rm_obj *prm) +{ + _adapter *padapter = prm->psta->padapter; + struct sta_info *psta = prm->psta; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_frame *pmgntframe = NULL; + struct pkt_attrib *pattr = NULL; + u8 val8; + u8 *pframe = NULL; + + + RTW_INFO("RM: %s\n", __func__); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__); + return _FALSE; + } + pattr = &pmgntframe->attrib; + pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION); + pframe = rtw_set_fixed_ie(pframe, + 3, &prm->q.category, &pattr->pktlen); + + if (prm->q.pssid) { + + u8 sub_ie[64] = {0}; + u8 *pie = &sub_ie[2]; + + RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n", + MAC_ARG(pmlmepriv->cur_network.network.MacAddress), + pmlmepriv->cur_network.network.Ssid.Ssid); + + val8 = strlen(prm->q.pssid); + sub_ie[0] = 0; /*SSID*/ + sub_ie[1] = val8; + + _rtw_memcpy(pie, prm->q.pssid, val8); + + pframe = rtw_set_fixed_ie(pframe, val8 + 2, + sub_ie, &pattr->pktlen); + } else { + + if (!pmlmepriv->cur_network.network.Ssid.SsidLength) + RTW_INFO("RM: Send NB Req to "MAC_FMT"\n", + MAC_ARG(pmlmepriv->cur_network.network.MacAddress)); + else { + u8 sub_ie[64] = {0}; + u8 *pie = &sub_ie[2]; + + RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n", + MAC_ARG(pmlmepriv->cur_network.network.MacAddress), + pmlmepriv->cur_network.network.Ssid.Ssid); + + sub_ie[0] = 0; /*SSID*/ + sub_ie[1] = pmlmepriv->cur_network.network.Ssid.SsidLength; + + _rtw_memcpy(pie, pmlmepriv->cur_network.network.Ssid.Ssid, + pmlmepriv->cur_network.network.Ssid.SsidLength); + + pframe = rtw_set_fixed_ie(pframe, + pmlmepriv->cur_network.network.Ssid.SsidLength + 2, + sub_ie, &pattr->pktlen); + } + } + + pattr->last_txcmdsz = pattr->pktlen; + dump_mgntframe(padapter, pmgntframe); + + return _SUCCESS; +} + +static u8 *rm_gen_bcn_req_s_elem(_adapter *padapter, + u8 *pframe, unsigned int *fr_len) +{ + u8 val8; + unsigned int my_len = 0; + u8 bssid[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + + val8 = bcn_req_active; /* measurement mode T8-64 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + pframe = rtw_set_fixed_ie(pframe, 6, bssid, &my_len); + + /* update length to caller */ + *fr_len += my_len; + + /* optional subelements */ + return pframe; +} + +static u8 *rm_gen_ch_load_req_s_elem(_adapter *padapter, + u8 *pframe, unsigned int *fr_len) +{ + u8 val8; + unsigned int my_len = 0; + + + val8 = 1; /* 1: channel load T8-60 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 2; /* channel load length = 2 (extensible) */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 0; /* channel load condition : 0 (issue when meas done) T8-61 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 0; /* channel load reference value : 0 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* update length to caller */ + *fr_len += my_len; + + return pframe; +} + +static u8 *rm_gen_noise_histo_req_s_elem(_adapter *padapter, + u8 *pframe, unsigned int *fr_len) +{ + u8 val8; + unsigned int my_len = 0; + + + val8 = 1; /* 1: noise histogram T8-62 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 2; /* noise histogram length = 2 (extensible) */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 0; /* noise histogram condition : 0 (issue when meas done) T8-63 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + val8 = 0; /* noise histogram reference value : 0 */ + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + + /* update length to caller */ + *fr_len += my_len; + + return pframe; +} + +int issue_radio_meas_req(struct rm_obj *prm) +{ + u8 val8; + u8 *pframe; + u8 *plen; + u16 val16; + int my_len, i; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattr; + _adapter *padapter = prm->psta->padapter; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + + RTW_INFO("RM: %s - %s\n", __func__, rm_type_req_name(prm->q.m_type)); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__); + return _FALSE; + } + pattr = &pmgntframe->attrib; + pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION); + pframe = rtw_set_fixed_ie(pframe, 3, &prm->q.category, &pattr->pktlen); + + /* repeat */ + val16 = cpu_to_le16(prm->q.rpt); + pframe = rtw_set_fixed_ie(pframe, 2, + (unsigned char *)&(val16), &pattr->pktlen); + + my_len = 0; + plen = pframe + 1; + pframe = rtw_set_fixed_ie(pframe, 7, &prm->q.e_id, &my_len); + + /* random interval */ + val16 = 100; /* 100 TU */ + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len); + + /* measurement duration */ + val16 = 100; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len); + + /* optional subelement */ + switch (prm->q.m_type) { + case bcn_req: + pframe = rm_gen_bcn_req_s_elem(padapter, pframe, &my_len); + break; + case ch_load_req: + pframe = rm_gen_ch_load_req_s_elem(padapter, pframe, &my_len); + break; + case noise_histo_req: + pframe = rm_gen_noise_histo_req_s_elem(padapter, + pframe, &my_len); + break; + case basic_req: + default: + break; + } + + /* length */ + val8 = (u8)my_len - 2; + rtw_set_fixed_ie(plen, 1, &val8, &i); + + pattr->pktlen += my_len; + + pattr->last_txcmdsz = pattr->pktlen; + dump_mgntframe(padapter, pmgntframe); + + return _SUCCESS; +} + +/* noise histogram */ +static u8 rm_get_anpi(struct rm_obj *prm, struct wlan_network *pnetwork) +{ + return translate_percentage_to_rcpi( + pnetwork->network.PhyInfo.SignalStrength); +} + +int rm_radio_meas_report_cond(struct rm_obj *prm) +{ + u8 val8; + int i; + + + switch (prm->q.m_type) { + case ch_load_req: + + val8 = prm->p.ch_load; + switch (prm->q.opt.clm.rep_cond.cond) { + case ch_load_cond_immediately: + return _SUCCESS; + case ch_load_cond_anpi_equal_greater: + if (val8 >= prm->q.opt.clm.rep_cond.threshold) + return _SUCCESS; + case ch_load_cond_anpi_equal_less: + if (val8 <= prm->q.opt.clm.rep_cond.threshold) + return _SUCCESS; + default: + break; + } + break; + case noise_histo_req: + val8 = prm->p.anpi; + switch (prm->q.opt.nhm.rep_cond.cond) { + case noise_histo_cond_immediately: + return _SUCCESS; + case noise_histo_cond_anpi_equal_greater: + if (val8 >= prm->q.opt.nhm.rep_cond.threshold) + return _SUCCESS; + break; + case noise_histo_cond_anpi_equal_less: + if (val8 <= prm->q.opt.nhm.rep_cond.threshold) + return _SUCCESS; + break; + default: + break; + } + break; + default: + break; + } + return _FAIL; +} + +int retrieve_radio_meas_result(struct rm_obj *prm) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(prm->psta->padapter); + int i, ch = -1; + u8 val8; + + + ch = rtw_chset_search_ch(adapter_to_chset(prm->psta->padapter), + prm->q.ch_num); + + if ((ch == -1) || (ch >= MAX_CHANNEL_NUM)) { + RTW_ERR("RM: get ch(CH:%d) fail\n", prm->q.ch_num); + ch = 0; + } + + switch (prm->q.m_type) { + case ch_load_req: +#ifdef CONFIG_RTW_ACS + val8 = hal_data->acs.clm_ratio[ch]; +#else + val8 = 0; +#endif + prm->p.ch_load = val8; + break; + case noise_histo_req: +#ifdef CONFIG_RTW_ACS + /* ANPI */ + prm->p.anpi = hal_data->acs.nhm_ratio[ch]; + + /* IPI 0~10 */ + for (i=0;i<11;i++) + prm->p.ipi[i] = hal_data->acs.nhm[ch][i]; + +#else + val8 = 0; + prm->p.anpi = val8; + for (i=0;i<11;i++) + prm->p.ipi[i] = val8; +#endif + break; + default: + break; + } + return _SUCCESS; +} + +int issue_radio_meas_rep(struct rm_obj *prm) +{ + u8 val8; + u8 *pframe; + u8 *plen; + u16 val16; + u64 val64; + unsigned int my_len; + _adapter *padapter = prm->psta->padapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattr; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct sta_info *psta = prm->psta; + int i; + + + RTW_INFO("RM: %s\n", __func__); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + RTW_ERR("RM: ERR %s alloc xmit_frame fail\n",__func__); + return _FALSE; + } + pattr = &pmgntframe->attrib; + pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION); + pframe = rtw_set_fixed_ie(pframe, 3, + &prm->p.category, &pattr->pktlen); + + my_len = 0; + plen = pframe + 1; + pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len); + + /* Actual Meas start time - 8 bytes */ + val64 = cpu_to_le64(prm->meas_start_time); + pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len); + + /* measurement duration */ + val16 = prm->meas_end_time - prm->meas_start_time; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len); + + /* optional subelement */ + switch (prm->q.m_type) { + case ch_load_req: + val8 = prm->p.ch_load; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + break; + case noise_histo_req: + /* + * AntennaID + * 0: unknown + * 255: multiple antenna (Diversity) + */ + val8 = 0; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + /* ANPI */ + val8 = prm->p.anpi; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + /* IPI 0~10 */ + for (i=0;i<11;i++) { + val8 = prm->p.ipi[i]; + pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len); + } + break; + default: + break; + } +done: + /* length */ + val8 = (u8)my_len-2; + rtw_set_fixed_ie(plen, 1, &val8, &i); /* use variable i to ignore it */ + + pattr->pktlen += my_len; + pattr->last_txcmdsz = pattr->pktlen; + dump_mgntframe(padapter, pmgntframe); + + return _SUCCESS; +} + +void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter, + struct sta_info *psta, struct rtw_ieee802_11_elems *elem) +{ + if (elem->rm_en_cap) { + RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n", + RM_CAP_ARG(elem->rm_en_cap)); + _rtw_memcpy(psta->rm_en_cap, + (elem->rm_en_cap), elem->rm_en_cap_len); + } +} + +void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + int i; + + _rtw_memcpy(&padapter->rmpriv.rm_en_cap_assoc, pIE->data, pIE->Length); + RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(pIE->data)); +} + +/* Debug command */ + +#if (RM_SUPPORT_IWPRIV_DBG) +static int hex2num(char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + return -1; +} + +int hex2byte(const char *hex) +{ + int a, b; + a = hex2num(*hex++); + if (a < 0) + return -1; + b = hex2num(*hex++); + if (b < 0) + return -1; + return (a << 4) | b; +} + +static char * hwaddr_parse(char *txt, u8 *addr) +{ + size_t i; + + for (i = 0; i < ETH_ALEN; i++) { + int a; + + a = hex2byte(txt); + if (a < 0) + return NULL; + txt += 2; + addr[i] = a; + if (i < ETH_ALEN - 1 && *txt++ != ':') + return NULL; + } + return txt; +} + +void rm_dbg_list_sta(_adapter *padapter, char *s) +{ + int i; + _irqL irqL; + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + _list *plist, *phead; + + + sprintf(pstr(s), "\n"); + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, + struct sta_info, hash_list); + + plist = get_next(plist); + + sprintf(pstr(s), "=========================================\n"); + sprintf(pstr(s), "mac=" MAC_FMT "\n", + MAC_ARG(psta->cmn.mac_addr)); + sprintf(pstr(s), "state=0x%x, aid=%d, macid=%d\n", + psta->state, psta->cmn.aid, psta->cmn.mac_id); + sprintf(pstr(s), "rm_cap="RM_CAP_FMT"\n", + RM_CAP_ARG(psta->rm_en_cap)); + } + + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + sprintf(pstr(s), "=========================================\n"); +} + +void rm_dbg_help(_adapter *padapter, char *s) +{ + int i; + + + sprintf(pstr(s), "\n"); + sprintf(pstr(s), "rrm list_sta\n"); + sprintf(pstr(s), "rrm list_meas\n"); + + sprintf(pstr(s), "rrm add_meas ,m=,rpt=\n"); + sprintf(pstr(s), "rrm run_meas \n"); + sprintf(pstr(s), "rrm del_meas\n"); + + sprintf(pstr(s), "rrm run_meas rmid=xxxx,ev=xx\n"); + sprintf(pstr(s), "rrm activate\n"); + + for (i=0;istapriv; + _list *plist, *phead; + + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, + struct sta_info, hash_list); + + plist = get_next(plist); + + if (psta->cmn.aid == aid) + goto done; + + if (pbssid && _rtw_memcmp(psta->cmn.mac_addr, + pbssid, 6)) + goto done; + } + + } + psta = NULL; +done: + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + return psta; +} + +static int rm_dbg_modify_meas(_adapter *padapter, char *s) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; + struct rm_obj *prm; + struct sta_info *psta; + char *pmac, *ptr, *paid, *prpt, *pnbp, *pclm, *pnhm, *pbcn; + unsigned val; + u8 bssid[ETH_ALEN]; + + + /* example : + * rrm add_meas ,m=, + * rrm run_meas + */ + paid = strstr(s, "aid="); + pmac = strstr(s, "mac="); + pbcn = strstr(s, "m=bcn"); + pclm = strstr(s, "m=clm"); + pnhm = strstr(s, "m=nhm"); + pnbp = strstr(s, "m=nb"); + prpt = strstr(s, "rpt="); + + /* set all ',' to NULL (end of line) */ + ptr = s; + while (ptr) { + ptr = strchr(ptr, ','); + if (ptr) { + *(ptr) = 0x0; + ptr++; + } + } + prm = (struct rm_obj *)prmpriv->prm_sel; + prm->q.m_token = 1; + psta = prm->psta; + + if (paid) { /* find sta_info according to aid */ + paid += 4; /* skip aid= */ + sscanf(paid, "%u", &val); /* aid=x */ + psta = rm_get_sta(padapter, val, NULL); + + } else if (pmac) { /* find sta_info according to bssid */ + pmac += 4; /* skip mac= */ + if (hwaddr_parse(pmac, bssid) == NULL) { + sprintf(pstr(s), "Err: \nincorrect mac format\n"); + return _FAIL; + } + psta = rm_get_sta(padapter, 0xff, bssid); + } + + if (psta) { + prm->psta = psta; + +#if 0 + prm->q.diag_token = psta->rm_diag_token++; +#else + /* TODO dialog should base on sta_info */ + prm->q.diag_token = pmlmeinfo->dialogToken++; +#endif + prm->rmid = psta->cmn.aid << 16 + | prm->q.diag_token << 8 + | RM_MASTER; + } else + return _FAIL; + + prm->q.action_code = RM_ACT_RADIO_MEAS_REQ; + if (pbcn) { + prm->q.m_type = bcn_req; + } else if (pnhm) { + prm->q.m_type = noise_histo_req; + } else if (pclm) { + prm->q.m_type = ch_load_req; + } else if (pnbp) { + prm->q.action_code = RM_ACT_NB_REP_REQ; + } else + return _FAIL; + + if (prpt) { + prpt += 4; /* skip rpt= */ + sscanf(prpt, "%u", &val); + prm->q.rpt = (u8)val; + } + + return _SUCCESS; +} + +static void rm_dbg_activate_meas(_adapter *padapter, char *s) +{ + struct rm_priv *prmpriv = &(padapter->rmpriv); + struct rm_obj *prm; + + + if (prmpriv->prm_sel == NULL) { + sprintf(pstr(s), "\nErr: No inActivate measurement\n"); + return; + } + prm = (struct rm_obj *)prmpriv->prm_sel; + + /* verify attributes */ + if (prm->psta == NULL) { + sprintf(pstr(s), "\nErr: inActivate meas has no psta\n"); + return; + } + + /* measure current channel */ + prm->q.ch_num = padapter->mlmeextpriv.cur_channel; + prm->q.op_class = rm_get_oper_class_via_ch(prm->q.ch_num); + + /* enquee rmobj */ + rm_enqueue_rmobj(padapter, prm, _FALSE); + + sprintf(pstr(s), "\nActivate rmid=%x, state=%s, meas_type=%s\n", + prm->rmid, rm_state_name(prm->state), + rm_type_req_name(prm->q.m_type)); + + sprintf(pstr(s), "aid=%d, mac=" MAC_FMT "\n", + prm->psta->cmn.aid, MAC_ARG(prm->psta->cmn.mac_addr)); + + /* clearn inActivate prm info */ + prmpriv->prm_sel = NULL; +} + +static void rm_dbg_add_meas(_adapter *padapter, char *s) +{ + struct rm_priv *prmpriv = &(padapter->rmpriv); + struct rm_obj *prm; + char *pact; + + + /* example : + * rrm add_meas ,m= + * rrm run_meas + */ + prm = (struct rm_obj *)prmpriv->prm_sel; + if (prm == NULL) + prm = rm_alloc_rmobj(padapter); + + if (prm == NULL) { + sprintf(pstr(s), "\nErr: alloc meas fail\n"); + return; + } + + prmpriv->prm_sel = prm; + + pact = strstr(s, "act"); + if (rm_dbg_modify_meas(padapter, s) == _FAIL) { + + sprintf(pstr(s), "\nErr: add meas fail\n"); + rm_free_rmobj(prm); + prmpriv->prm_sel = NULL; + return; + } + prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS; + prm->q.e_id = _MEAS_REQ_IE_; /* 38 */ + + if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) + sprintf(pstr(s), "\nAdd rmid=%x, meas_type=%s ok\n", + prm->rmid, rm_type_req_name(prm->q.m_type)); + else if (prm->q.action_code == RM_ACT_NB_REP_REQ) + sprintf(pstr(s), "\nAdd rmid=%x, meas_type=bcn_req ok\n", + prm->rmid); + + if (prm->psta) + sprintf(pstr(s), "mac="MAC_FMT"\n", + MAC_ARG(prm->psta->cmn.mac_addr)); + + if (pact) + rm_dbg_activate_meas(padapter, pstr(s)); +} + +static void rm_dbg_del_meas(_adapter *padapter, char *s) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_obj *prm = (struct rm_obj *)prmpriv->prm_sel; + + + if (prm) { + sprintf(pstr(s), "\ndelete rmid=%x\n",prm->rmid); + + /* free inActivate meas - enqueue yet */ + prmpriv->prm_sel = NULL; + rtw_mfree(prmpriv->prm_sel, sizeof(struct rm_obj)); + } else + sprintf(pstr(s), "Err: no inActivate measurement\n"); +} + +static void rm_dbg_run_meas(_adapter *padapter, char *s) +{ + struct rm_obj *prm; + char *pevid, *prmid; + u32 rmid, evid; + + + prmid = strstr(s, "rmid="); /* hex */ + pevid = strstr(s, "evid="); /* dec */ + + if (prmid && pevid) { + prmid += 5; /* rmid= */ + sscanf(prmid, "%x", &rmid); + + pevid += 5; /* evid= */ + sscanf(pevid, "%u", &evid); + } else { + sprintf(pstr(s), "\nErr: incorrect attribute\n"); + return; + } + + prm = rm_get_rmobj(padapter, rmid); + + if (!prm) { + sprintf(pstr(s), "\nErr: measurement not found\n"); + return; + } + + if (evid >= RM_EV_max) { + sprintf(pstr(s), "\nErr: wrong event id\n"); + return; + } + + rm_post_event(padapter, prm->rmid, evid); + sprintf(pstr(s), "\npost %s to rmid=%x\n",rm_event_name(evid), rmid); +} + +static void rm_dbg_show_meas(struct rm_obj *prm, char *s) +{ + struct sta_info *psta; + + psta = prm->psta; + + if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) { + + sprintf(pstr(s), "\nrmid=%x, meas_type=%s\n", + prm->rmid, rm_type_req_name(prm->q.m_type)); + + } else if (prm->q.action_code == RM_ACT_NB_REP_REQ) { + + sprintf(pstr(s), "\nrmid=%x, action=neighbor_req\n", + prm->rmid); + } else + sprintf(pstr(s), "\nrmid=%x, action=unknown\n", + prm->rmid); + + if (psta) + sprintf(pstr(s), "aid=%d, mac="MAC_FMT"\n", + psta->cmn.aid, MAC_ARG(psta->cmn.mac_addr)); + + sprintf(pstr(s), "clock=%d, state=%s, rpt=%u/%u\n", + (int)ATOMIC_READ(&prm->pclock->counter), + rm_state_name(prm->state), prm->p.rpt, prm->q.rpt); +} + +static void rm_dbg_list_meas(_adapter *padapter, char *s) +{ + int meas_amount; + _irqL irqL; + struct rm_obj *prm; + struct sta_info *psta; + struct rm_priv *prmpriv = &padapter->rmpriv; + _queue *queue = &prmpriv->rm_queue; + _list *plist, *phead; + + + sprintf(pstr(s), "\n"); + _enter_critical(&queue->lock, &irqL); + phead = get_list_head(queue); + plist = get_next(phead); + meas_amount = 0; + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + prm = LIST_CONTAINOR(plist, struct rm_obj, list); + meas_amount++; + plist = get_next(plist); + psta = prm->psta; + sprintf(pstr(s), "=========================================\n"); + + rm_dbg_show_meas(prm, s); + } + _exit_critical(&queue->lock, &irqL); + + sprintf(pstr(s), "=========================================\n"); + + if (meas_amount==0) { + sprintf(pstr(s), "No Activate measurement\n"); + sprintf(pstr(s), "=========================================\n"); + } + + if (prmpriv->prm_sel == NULL) + sprintf(pstr(s), "\nNo inActivate measurement\n"); + else { + sprintf(pstr(s), "\ninActivate measurement\n"); + rm_dbg_show_meas((struct rm_obj *)prmpriv->prm_sel, s); + } +} +#endif /* RM_SUPPORT_IWPRIV_DBG */ + +void rm_dbg_cmd(_adapter *padapter, char *s) +{ + unsigned val; + char *paid; + struct sta_info *psta=NULL; + +#if (RM_SUPPORT_IWPRIV_DBG) + if (_rtw_memcmp(s, "help", 4)) { + rm_dbg_help(padapter, s); + + } else if (_rtw_memcmp(s, "list_sta", 8)) { + rm_dbg_list_sta(padapter, s); + + } else if (_rtw_memcmp(s, "list_meas", 9)) { + rm_dbg_list_meas(padapter, s); + + } else if (_rtw_memcmp(s, "add_meas", 8)) { + rm_dbg_add_meas(padapter, s); + + } else if (_rtw_memcmp(s, "del_meas", 8)) { + rm_dbg_del_meas(padapter, s); + + } else if (_rtw_memcmp(s, "activate", 8)) { + rm_dbg_activate_meas(padapter, s); + + } else if (_rtw_memcmp(s, "run_meas", 8)) { + rm_dbg_run_meas(padapter, s); + } else if (_rtw_memcmp(s, "nb", 2)) { + + paid = strstr(s, "aid="); + + if (paid) { /* find sta_info according to aid */ + paid += 4; /* skip aid= */ + sscanf(paid, "%u", &val); /* aid=x */ + psta = rm_get_sta(padapter, val, NULL); + + if (psta) + rm_add_nb_req(padapter, psta); + } + } +#else + sprintf(pstr(s), "\n"); + sprintf(pstr(s), "rrm debug command was disabled\n"); +#endif +} +#endif /* CONFIG_RTW_80211K */ diff --git a/core/rtw_rm_fsm.c b/core/rtw_rm_fsm.c new file mode 100644 index 0000000..21fb323 --- /dev/null +++ b/core/rtw_rm_fsm.c @@ -0,0 +1,998 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include +#include +#include "rtw_rm_fsm.h" + +#ifdef CONFIG_RTW_80211K + +struct fsm_state { + u8 *name; + int(*fsm_func)(struct rm_obj *prm, enum RM_EV_ID evid); +}; + +static void rm_state_initial(struct rm_obj *prm); +static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state); +static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid); +static struct rm_event *rm_dequeue_ev(_queue *queue); +static struct rm_obj *rm_dequeue_rm(_queue *queue); + +void rm_timer_callback(void *data) +{ + int i; + _adapter *padapter = (_adapter *)data; + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_clock *pclock; + + + /* deal with clock */ + for (i=0;iclock[i]; + if (pclock->prm == NULL + ||(ATOMIC_READ(&(pclock->counter)) == 0)) + continue; + + ATOMIC_DEC(&(pclock->counter)); + + if (ATOMIC_READ(&(pclock->counter)) == 0) + rm_post_event(pclock->prm->psta->padapter, + pclock->prm->rmid, prmpriv->clock[i].evid); + } + _set_timer(&prmpriv->rm_timer, CLOCK_UNIT); +} + +int rtw_init_rm(_adapter *padapter) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + + + RTW_INFO("RM: %s\n",__func__); + _rtw_init_queue(&(prmpriv->rm_queue)); + _rtw_init_queue(&(prmpriv->ev_queue)); + + /* bit 0-7 */ + prmpriv->rm_en_cap_def[0] = 0 + /*| BIT(RM_LINK_MEAS_CAP_EN)*/ + | BIT(RM_NB_REP_CAP_EN) + /*| BIT(RM_PARAL_MEAS_CAP_EN)*/ + | BIT(RM_REPEAT_MEAS_CAP_EN) + | BIT(RM_BCN_PASSIVE_MEAS_CAP_EN) + | BIT(RM_BCN_ACTIVE_MEAS_CAP_EN) + | BIT(RM_BCN_TABLE_MEAS_CAP_EN) + /*| BIT(RM_BCN_MEAS_REP_COND_CAP_EN)*/; + + /* bit 8-15 */ + prmpriv->rm_en_cap_def[1] = 0 + /*| BIT(RM_FRAME_MEAS_CAP_EN - 8)*/ +#ifdef CONFIG_RTW_ACS + | BIT(RM_CH_LOAD_CAP_EN - 8) + | BIT(RM_NOISE_HISTO_CAP_EN - 8) +#endif + /*| BIT(RM_STATIS_MEAS_CAP_EN - 8)*/ + /*| BIT(RM_LCI_MEAS_CAP_EN - 8)*/ + /*| BIT(RM_LCI_AMIMUTH_CAP_EN - 8)*/ + /*| BIT(RM_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/ + /*| BIT(RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/; + + /* bit 16-23 */ + prmpriv->rm_en_cap_def[2] = 0 + /*| BIT(RM_AP_CH_REP_CAP_EN - 16)*/ + /*| BIT(RM_RM_MIB_CAP_EN - 16)*/ + /*| BIT(RM_OP_CH_MAX_MEAS_DUR0 - 16)*/ + /*| BIT(RM_OP_CH_MAX_MEAS_DUR1 - 16)*/ + /*| BIT(RM_OP_CH_MAX_MEAS_DUR2 - 16)*/ + /*| BIT(RM_NONOP_CH_MAX_MEAS_DUR0 - 16)*/ + /*| BIT(RM_NONOP_CH_MAX_MEAS_DUR1 - 16)*/ + /*| BIT(RM_NONOP_CH_MAX_MEAS_DUR2 - 16)*/; + + /* bit 24-31 */ + prmpriv->rm_en_cap_def[3] = 0 + /*| BIT(RM_MEAS_PILOT_CAP0 - 24)*/ + /*| BIT(RM_MEAS_PILOT_CAP1 - 24)*/ + /*| BIT(RM_MEAS_PILOT_CAP2 - 24)*/ + /*| BIT(RM_MEAS_PILOT_TRANS_INFO_CAP_EN - 24)*/ + /*| BIT(RM_NB_REP_TSF_OFFSET_CAP_EN - 24)*/ + | BIT(RM_RCPI_MEAS_CAP_EN - 24) + | BIT(RM_RSNI_MEAS_CAP_EN - 24) + /*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 24)*/; + + /* bit 32-39 */ + prmpriv->rm_en_cap_def[4] = 0 + /*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 32)*/ + /*| BIT(RM_AVALB_ADMIS_CAPACITY_CAP_EN - 32)*/ + /*| BIT(RM_ANT_CAP_EN - 32)*/; + + prmpriv->enable = _TRUE; + + /* clock timer */ + rtw_init_timer(&prmpriv->rm_timer, + padapter, rm_timer_callback, padapter); + _set_timer(&prmpriv->rm_timer, CLOCK_UNIT); + + return _SUCCESS; +} + +int rtw_deinit_rm(_adapter *padapter) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_obj *prm; + struct rm_event *pev; + + + RTW_INFO("RM: %s\n",__func__); + prmpriv->enable = _FALSE; + _cancel_timer_ex(&prmpriv->rm_timer); + + /* free all events and measurements */ + while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL) + rtw_mfree((void *)pev, sizeof(struct rm_event)); + + while((prm = rm_dequeue_rm(&prmpriv->rm_queue)) != NULL) + rm_state_run(prm, RM_EV_cancel); + + _rtw_deinit_queue(&(prmpriv->rm_queue)); + _rtw_deinit_queue(&(prmpriv->ev_queue)); + + return _SUCCESS; +} + +int rtw_free_rm_priv(_adapter *padapter) +{ + return rtw_deinit_rm(padapter); +} + +static int rm_enqueue_ev(_queue *queue, struct rm_event *obj, bool to_head) +{ + _irqL irqL; + + + if (obj == NULL) + return _FAIL; + + _enter_critical(&queue->lock, &irqL); + + if (to_head) + rtw_list_insert_head(&obj->list, &queue->queue); + else + rtw_list_insert_tail(&obj->list, &queue->queue); + + _exit_critical(&queue->lock, &irqL); + + return _SUCCESS; +} + +static void rm_set_clock(struct rm_obj *prm, u32 ms, enum RM_EV_ID evid) +{ + ATOMIC_SET(&(prm->pclock->counter), (ms/CLOCK_UNIT)); + prm->pclock->evid = evid; +} + +static struct rm_clock *rm_alloc_clock(_adapter *padapter, struct rm_obj *prm) +{ + int i; + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_clock *pclock = NULL; + + + for (i=0;iclock[i]; + + if (pclock->prm == NULL) { + pclock->prm = prm; + ATOMIC_SET(&(pclock->counter), 0); + pclock->evid = RM_EV_max; + break; + } + } + return pclock; +} + +static void rm_cancel_clock(struct rm_obj *prm) +{ + ATOMIC_SET(&(prm->pclock->counter), 0); + prm->pclock->evid = RM_EV_max; +} + +static void rm_free_clock(struct rm_clock *pclock) +{ + pclock->prm = NULL; + ATOMIC_SET(&(pclock->counter), 0); + pclock->evid = RM_EV_max; +} + +static int is_list_linked(const struct list_head *head) +{ + return head->prev != NULL; +} + +void rm_free_rmobj(struct rm_obj *prm) +{ + if (is_list_linked(&prm->list)) + rtw_list_delete(&prm->list); + + if (prm->q.pssid) + rtw_mfree(prm->q.pssid, strlen(prm->q.pssid)+1); + + if (prm->q.opt.bcn.req_start) + rtw_mfree(prm->q.opt.bcn.req_start, + prm->q.opt.bcn.req_len); + + if (prm->pclock) + rm_free_clock(prm->pclock); + + rtw_mfree((void *)prm, sizeof(struct rm_obj)); +} + +struct rm_obj *rm_alloc_rmobj(_adapter *padapter) +{ + struct rm_obj *prm; + + + prm = (struct rm_obj *)rtw_malloc(sizeof(struct rm_obj)); + if (prm == NULL) + return NULL; + + _rtw_memset(prm, 0, sizeof(struct rm_obj)); + + /* alloc timer */ + if ((prm->pclock = rm_alloc_clock(padapter, prm)) == NULL) { + rm_free_rmobj(prm); + return NULL; + } + return prm; +} + +int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *prm, bool to_head) +{ + _irqL irqL; + struct rm_priv *prmpriv = &padapter->rmpriv; + _queue *queue = &prmpriv->rm_queue; + + + if (prm == NULL) + return _FAIL; + + _enter_critical(&queue->lock, &irqL); + if (to_head) + rtw_list_insert_head(&prm->list, &queue->queue); + else + rtw_list_insert_tail(&prm->list, &queue->queue); + _exit_critical(&queue->lock, &irqL); + + rm_state_initial(prm); + + return _SUCCESS; +} + +static struct rm_obj *rm_dequeue_rm(_queue *queue) +{ + _irqL irqL; + struct rm_obj *prm; + + + _enter_critical(&queue->lock, &irqL); + if (rtw_is_list_empty(&(queue->queue))) + prm = NULL; + else { + prm = LIST_CONTAINOR(get_next(&(queue->queue)), + struct rm_obj, list); + /* rtw_list_delete(&prm->list); */ + } + _exit_critical(&queue->lock, &irqL); + + return prm; +} + +static struct rm_event *rm_dequeue_ev(_queue *queue) +{ + _irqL irqL; + struct rm_event *ev; + + + _enter_critical(&queue->lock, &irqL); + if (rtw_is_list_empty(&(queue->queue))) + ev = NULL; + else { + ev = LIST_CONTAINOR(get_next(&(queue->queue)), + struct rm_event, list); + rtw_list_delete(&ev->list); + } + _exit_critical(&queue->lock, &irqL); + + return ev; +} + +static struct rm_obj *_rm_get_rmobj(_queue *queue, u32 rmid) +{ + _irqL irqL; + _list *phead, *plist; + struct rm_obj *prm = NULL; + + + if (rmid == 0) + return NULL; + + _enter_critical(&queue->lock, &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + + prm = LIST_CONTAINOR(plist, struct rm_obj, list); + if (rmid == (prm->rmid)) { + _exit_critical(&queue->lock, &irqL); + return prm; + } + plist = get_next(plist); + } + _exit_critical(&queue->lock, &irqL); + + return NULL; +} + +struct sta_info *rm_get_psta(_adapter *padapter, u32 rmid) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_obj *prm; + + + prm = _rm_get_rmobj(&prmpriv->rm_queue, rmid); + + if (prm) + return prm->psta; + + return NULL; +} + +struct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + + return _rm_get_rmobj(&prmpriv->rm_queue, rmid); +} + +u8 rtw_rm_post_envent_cmd(_adapter *padapter, u32 rmid, u8 evid) +{ + struct cmd_obj *pcmd; + struct rm_event *pev; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + + pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd == NULL) { + res = _FAIL; + goto exit; + } + pev = (struct rm_event*)rtw_zmalloc(sizeof(struct rm_event)); + + if (pev == NULL) { + rtw_mfree((u8 *) pcmd, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + pev->rmid = rmid; + pev->evid = evid; + + init_h2fwcmd_w_parm_no_rsp(pcmd, pev, GEN_CMD_CODE(_RM_POST_EVENT)); + res = rtw_enqueue_cmd(pcmdpriv, pcmd); +exit: + return res; +} + +int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid) +{ + if (padapter->rmpriv.enable == _FALSE) + return _FALSE; + + RTW_INFO("RM: post asyn %s to rmid=%x\n", rm_event_name(evid), rmid); + rtw_rm_post_envent_cmd(padapter, rmid, evid); + return _SUCCESS; +} + +int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid) +{ + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_event *pev; + + if (evid >= RM_EV_max || rmid == 0) + return _FALSE; + + pev = (struct rm_event *)rtw_malloc(sizeof(struct rm_event)); + if (pev == NULL) + return _FALSE; + + pev->rmid = rmid; + pev->evid = evid; + + RTW_INFO("RM: post sync %s to rmid=%x\n", rm_event_name(evid), rmid); + rm_enqueue_ev(&prmpriv->ev_queue, pev, FALSE); + + return _SUCCESS; +} + +static void rm_bcast_aid_handler(_adapter *padapter, struct rm_event *pev) +{ + _irqL irqL; + _list *phead, *plist; + _queue *queue = &padapter->rmpriv.rm_queue; + struct rm_obj *prm; + + + _enter_critical(&queue->lock, &irqL); + phead = get_list_head(queue); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + + prm = LIST_CONTAINOR(plist, struct rm_obj, list); + plist = get_next(plist); + if (RM_GET_AID(pev->rmid) == RM_GET_AID(prm->rmid)) { + _exit_critical(&queue->lock, &irqL); + rm_state_run(prm, pev->evid); + _enter_critical(&queue->lock, &irqL); + } + } + _exit_critical(&queue->lock, &irqL); + return; +} + +/* main handler of RM (Resource Management) */ +void rm_handler(_adapter *padapter, struct rm_event *pe) +{ + int i; + struct rm_priv *prmpriv = &padapter->rmpriv; + struct rm_obj *prm; + struct rm_event *pev; + + + /* dequeue event */ + while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL) + { + if (RM_IS_ID_FOR_ALL(pev->rmid)) { + /* apply to all aid mateched measurement */ + rm_bcast_aid_handler(padapter, pev); + rtw_mfree((void *)pev, sizeof(struct rm_event)); + continue; + } + + /* retrieve rmobj */ + prm = _rm_get_rmobj(&prmpriv->rm_queue, pev->rmid); + if (prm == NULL) { + RTW_ERR("RM: rmid=%x event=%s doesn't find rm obj\n", + pev->rmid, rm_event_name(pev->evid)); + rtw_mfree((void *)pev, sizeof(struct rm_event)); + return; + } + /* run state machine */ + rm_state_run(prm, pev->evid); + rtw_mfree((void *)pev, sizeof(struct rm_event)); + } +} + +static int rm_issue_meas_req(struct rm_obj *prm) +{ + switch (prm->q.action_code) { + case RM_ACT_RADIO_MEAS_REQ: + switch (prm->q.m_type) { + case bcn_req: + case ch_load_req: + case noise_histo_req: + issue_radio_meas_req(prm); + break; + default: + break; + } /* meas_type */ + break; + case RM_ACT_NB_REP_REQ: + /* issue neighbor request */ + issue_nb_req(prm); + break; + case RM_ACT_LINK_MEAS_REQ: + default: + return _FALSE; + } /* action_code */ + + return _SUCCESS; +} + +/* +* RM state machine +*/ + +static int rm_state_idle(struct rm_obj *prm, enum RM_EV_ID evid) +{ + _adapter *padapter = prm->psta->padapter; + u8 val8; + u32 val32; + + + prm->p.category = RTW_WLAN_CATEGORY_RADIO_MEAS; + + switch (evid) { + case RM_EV_state_in: + switch (prm->q.action_code) { + case RM_ACT_RADIO_MEAS_REQ: + /* copy attrib from meas_req to meas_rep */ + prm->p.action_code = RM_ACT_RADIO_MEAS_REP; + prm->p.diag_token = prm->q.diag_token; + prm->p.e_id = _MEAS_RSP_IE_; + prm->p.m_token = prm->q.m_token; + prm->p.m_type = prm->q.m_type; + prm->p.rpt = prm->q.rpt; + prm->p.ch_num = prm->q.ch_num; + prm->p.op_class = prm->q.op_class; + + if (prm->q.m_type == ch_load_req + || prm->q.m_type == noise_histo_req) { + /* + * phydm measure current ch periodically + * scan current ch is not necessary + */ + val8 = padapter->mlmeextpriv.cur_channel; + if (prm->q.ch_num == val8) + prm->poll_mode = 1; + } + RTW_INFO("RM: rmid=%x %s switch in repeat=%u\n", + prm->rmid, rm_type_req_name(prm->q.m_type), + prm->q.rpt); + break; + case RM_ACT_NB_REP_REQ: + prm->p.action_code = RM_ACT_NB_REP_RESP; + RTW_INFO("RM: rmid=%x Neighbor request switch in\n", + prm->rmid); + break; + case RM_ACT_LINK_MEAS_REQ: + prm->p.action_code = RM_ACT_LINK_MEAS_REP; + rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP); + RTW_INFO("RM: rmid=%x Link meas switch in\n", + prm->rmid); + break; + default: + prm->p.action_code = prm->q.action_code; + rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP); + RTW_INFO("RM: rmid=%x recv unknown action %d\n", + prm->rmid,prm->p.action_code); + break; + } /* switch() */ + + if (prm->rmid & RM_MASTER) { + if (rm_issue_meas_req(prm) == _SUCCESS) + rm_state_goto(prm, RM_ST_WAIT_MEAS); + else + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } else { + rm_state_goto(prm, RM_ST_DO_MEAS); + return _SUCCESS; + } + + if (prm->p.m_mode) { + issue_null_reply(prm); + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + if (prm->q.rand_intvl) { + /* get low tsf to generate random interval */ + val32 = rtw_read32(padapter, REG_TSFTR); + val32 = val32 % prm->q.rand_intvl; + RTW_INFO("RM: rmid=%x rand_intval=%d, rand=%d\n", + prm->rmid, (int)prm->q.rand_intvl,val32); + rm_set_clock(prm, prm->q.rand_intvl, + RM_EV_delay_timer_expire); + return _SUCCESS; + } + break; + case RM_EV_delay_timer_expire: + rm_state_goto(prm, RM_ST_DO_MEAS); + break; + case RM_EV_cancel: + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_state_out: + rm_cancel_clock(prm); + break; + default: + break; + } + return _SUCCESS; +} + +/* we do the measuring */ +static int rm_state_do_meas(struct rm_obj *prm, enum RM_EV_ID evid) +{ + _adapter *padapter = prm->psta->padapter; + u8 val8; + u64 val64; + + + switch (evid) { + case RM_EV_state_in: + if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) { + switch (prm->q.m_type) { + case bcn_req: + if (prm->q.m_mode == bcn_req_bcn_table) { + RTW_INFO("RM: rmid=%x Beacon table\n", + prm->rmid); + _rm_post_event(padapter, prm->rmid, + RM_EV_survey_done); + return _SUCCESS; + } + break; + case ch_load_req: + case noise_histo_req: + if (prm->poll_mode) + _rm_post_event(padapter, prm->rmid, + RM_EV_survey_done); + return _SUCCESS; + default: + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + + if (!ready_for_scan(prm)) { + prm->wait_busy = RM_BUSY_TRAFFIC_TIMES; + RTW_INFO("RM: wait busy traffic - %d\n", + prm->wait_busy); + rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT, + RM_EV_busy_timer_expire); + return _SUCCESS; + } + } + _rm_post_event(padapter, prm->rmid, RM_EV_start_meas); + break; + case RM_EV_start_meas: + if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) { + /* resotre measurement start time */ + prm->meas_start_time = rtw_hal_get_tsftr_by_port(padapter + , rtw_hal_get_port(padapter)); + + switch (prm->q.m_type) { + case bcn_req: + val8 = 1; /* Enable free run counter */ + rtw_hal_set_hwreg(padapter, + HW_VAR_FREECNT, &val8); + rm_sitesurvey(prm); + break; + case ch_load_req: + case noise_histo_req: + rm_sitesurvey(prm); + break; + default: + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + break; + } + } + /* handle measurement timeout */ + rm_set_clock(prm, RM_MEAS_TIMEOUT, RM_EV_meas_timer_expire); + break; + case RM_EV_survey_done: + if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) { + switch (prm->q.m_type) { + case bcn_req: + rm_cancel_clock(prm); + rm_state_goto(prm, RM_ST_SEND_REPORT); + return _SUCCESS; + case ch_load_req: + case noise_histo_req: + retrieve_radio_meas_result(prm); + + if (rm_radio_meas_report_cond(prm) == _SUCCESS) + rm_state_goto(prm, RM_ST_SEND_REPORT); + else + rm_set_clock(prm, RM_COND_INTVL, + RM_EV_retry_timer_expire); + break; + default: + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + } + break; + case RM_EV_meas_timer_expire: + RTW_INFO("RM: rmid=%x measurement timeount\n",prm->rmid); + rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE); + issue_null_reply(prm); + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_busy_timer_expire: + if (!ready_for_scan(prm) && prm->wait_busy--) { + RTW_INFO("RM: wait busy - %d\n",prm->wait_busy); + rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT, + RM_EV_busy_timer_expire); + break; + } + else if (prm->wait_busy <= 0) { + RTW_INFO("RM: wait busy timeout\n"); + rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE); + issue_null_reply(prm); + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + _rm_post_event(padapter, prm->rmid, RM_EV_start_meas); + break; + case RM_EV_request_timer_expire: + rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE); + issue_null_reply(prm); + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_retry_timer_expire: + /* expired due to meas condition mismatch, meas again */ + _rm_post_event(padapter, prm->rmid, RM_EV_start_meas); + break; + case RM_EV_cancel: + rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE); + issue_null_reply(prm); + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_state_out: + rm_cancel_clock(prm); + /* resotre measurement end time */ + prm->meas_end_time = rtw_hal_get_tsftr_by_port(padapter + , rtw_hal_get_port(padapter)); + + val8 = 0; /* Disable free run counter */ + rtw_hal_set_hwreg(padapter, HW_VAR_FREECNT, &val8); + break; + default: + break; + } + + return _SUCCESS; +} + +static int rm_state_wait_meas(struct rm_obj *prm, enum RM_EV_ID evid) +{ + u8 val8; + u64 val64; + + + switch (evid) { + case RM_EV_state_in: + /* we create meas_req, waiting for peer report */ + rm_set_clock(prm, RM_REQ_TIMEOUT, + RM_EV_request_timer_expire); + break; + case RM_EV_recv_rep: + rm_state_goto(prm, RM_ST_RECV_REPORT); + break; + case RM_EV_request_timer_expire: + case RM_EV_cancel: + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_state_out: + rm_cancel_clock(prm); + break; + default: + break; + } + return _SUCCESS; +} + +static int rm_state_send_report(struct rm_obj *prm, enum RM_EV_ID evid) +{ + u8 val8; + + + switch (evid) { + case RM_EV_state_in: + /* we have to issue report */ + switch (prm->q.m_type) { + case bcn_req: + issue_beacon_rep(prm); + break; + case ch_load_req: + case noise_histo_req: + issue_radio_meas_rep(prm); + break; + default: + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + + /* check repeat */ + if (prm->p.rpt) { + RTW_INFO("RM: rmid=%x repeat=%u/%u\n", + prm->rmid, prm->p.rpt, + prm->q.rpt); + prm->p.rpt--; + /* + * we recv meas_req, + * delay for a wihile and than meas again + */ + if (prm->poll_mode) + rm_set_clock(prm, RM_REPT_POLL_INTVL, + RM_EV_repeat_delay_expire); + else + rm_set_clock(prm, RM_REPT_SCAN_INTVL, + RM_EV_repeat_delay_expire); + return _SUCCESS; + } + /* we are done */ + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_repeat_delay_expire: + rm_state_goto(prm, RM_ST_DO_MEAS); + break; + case RM_EV_cancel: + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_state_out: + rm_cancel_clock(prm); + break; + default: + break; + } + return _SUCCESS; +} + +static int rm_state_recv_report(struct rm_obj *prm, enum RM_EV_ID evid) +{ + u8 val8; + + + switch (evid) { + case RM_EV_state_in: + /* we issue meas_req, got peer's meas report */ + switch (prm->p.action_code) { + case RM_ACT_RADIO_MEAS_REP: + /* check refuse, incapable and repeat */ + val8 = prm->p.m_mode; + if (val8) { + RTW_INFO("RM: rmid=%x peer reject (%s repeat=%d)\n", + prm->rmid, + val8|MEAS_REP_MOD_INCAP?"INCAP": + val8|MEAS_REP_MOD_REFUSE?"REFUSE": + val8|MEAS_REP_MOD_LATE?"LATE":"", + prm->p.rpt); + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + break; + case RM_ACT_NB_REP_RESP: + /* report to upper layer if needing */ + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + default: + rm_state_goto(prm, RM_ST_END); + return _SUCCESS; + } + /* check repeat */ + if (prm->p.rpt) { + RTW_INFO("RM: rmid=%x repeat=%u/%u\n", + prm->rmid, prm->p.rpt, + prm->q.rpt); + prm->p.rpt--; + /* waitting more report */ + rm_state_goto(prm, RM_ST_WAIT_MEAS); + break; + } + /* we are done */ + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_cancel: + rm_state_goto(prm, RM_ST_END); + break; + case RM_EV_state_out: + rm_cancel_clock(prm); + break; + default: + break; + } + return _SUCCESS; +} + +static int rm_state_end(struct rm_obj *prm, enum RM_EV_ID evid) +{ + switch (evid) { + case RM_EV_state_in: + _rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_out); + break; + + case RM_EV_cancel: + case RM_EV_state_out: + default: + rm_free_rmobj(prm); + break; + } + return _SUCCESS; +} + +struct fsm_state rm_fsm[] = { + {"RM_ST_IDLE", rm_state_idle}, + {"RM_ST_DO_MEAS", rm_state_do_meas}, + {"RM_ST_WAIT_MEAS", rm_state_wait_meas}, + {"RM_ST_SEND_REPORT", rm_state_send_report}, + {"RM_ST_RECV_REPORT", rm_state_recv_report}, + {"RM_ST_END", rm_state_end} +}; + +char *rm_state_name(enum RM_STATE state) +{ + return rm_fsm[state].name; +} + +char *rm_event_name(enum RM_EV_ID evid) +{ + switch(evid) { + case RM_EV_state_in: + return "RM_EV_state_in"; + case RM_EV_busy_timer_expire: + return "RM_EV_busy_timer_expire"; + case RM_EV_delay_timer_expire: + return "RM_EV_delay_timer_expire"; + case RM_EV_meas_timer_expire: + return "RM_EV_meas_timer_expire"; + case RM_EV_repeat_delay_expire: + return "RM_EV_repeat_delay_expire"; + case RM_EV_retry_timer_expire: + return "RM_EV_retry_timer_expire"; + case RM_EV_request_timer_expire: + return "RM_EV_request_timer_expire"; + case RM_EV_wait_report: + return "RM_EV_wait_report"; + case RM_EV_start_meas: + return "RM_EV_start_meas"; + case RM_EV_survey_done: + return "RM_EV_survey_done"; + case RM_EV_recv_rep: + return "RM_EV_recv_report"; + case RM_EV_cancel: + return "RM_EV_cancel"; + case RM_EV_state_out: + return "RM_EV_state_out"; + case RM_EV_max: + return "RM_EV_max"; + default: + return "RM_EV_unknown"; + } + return "UNKNOWN"; +} + +static void rm_state_initial(struct rm_obj *prm) +{ + prm->state = RM_ST_IDLE; + + RTW_INFO("\n"); + RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid, + "new measurement", rm_fsm[prm->state].name); + + rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_in); +} + +static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid) +{ + RTW_INFO("RM: rmid=%x %-18s %s\n",prm->rmid, + rm_fsm[prm->state].name,rm_event_name(evid)); + + rm_fsm[prm->state].fsm_func(prm, evid); +} + +static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state) +{ + if (prm->state == rm_state) + return; + + rm_state_run(prm, RM_EV_state_out); + + RTW_INFO("\n"); + RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid, + rm_fsm[prm->state].name, rm_fsm[rm_state].name); + + prm->state = rm_state; + rm_state_run(prm, RM_EV_state_in); +} +#endif /* CONFIG_RTW_80211K */ diff --git a/core/rtw_rson.c b/core/rtw_rson.c new file mode 100644 index 0000000..4fbdbb5 --- /dev/null +++ b/core/rtw_rson.c @@ -0,0 +1,595 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_RSON_C_ + +#include + +#ifdef CONFIG_RTW_REPEATER_SON + +/******** Custommize Part ***********************/ + +unsigned char RTW_RSON_OUI[] = {0xFA, 0xFA, 0xFA}; +#define RSON_SCORE_DIFF_TH 8 + +/* + Calculate the corresponding score. +*/ +inline u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI Rssi) +{ + if ((cand_rson_data->hopcnt == RTW_RSON_HC_NOTREADY) + || (cand_rson_data->connectible == RTW_RSON_DENYCONNECT)) + return RTW_RSON_SCORE_NOTCNNT; + + return RTW_RSON_SCORE_MAX - (cand_rson_data->hopcnt * 10) + (Rssi/10); +} + +/*************************************************/ + + +static u8 rtw_rson_block_bssid_idx = 0; +u8 rtw_rson_block_bssid[10][6] = { + /*{0x02, 0xE0, 0x4C, 0x07, 0xC3, 0xF6}*/ +}; + +/* fake root, regard a real AP as a SO root */ +static u8 rtw_rson_root_bssid_idx = 0; +u8 rtw_rson_root_bssid[10][6] = { + /*{0x1c, 0x5f, 0x2b, 0x5a, 0x60, 0x24}*/ +}; + +int is_match_bssid(u8 *mac, u8 bssid_array[][6], int num) +{ + int i; + + for (i = 0; i < num; i++) + if (_rtw_memcmp(mac, bssid_array[i], 6) == _TRUE) + return _TRUE; + return _FALSE; +} + +void init_rtw_rson_data(struct dvobj_priv *dvobj) +{ + /*Aries todo. if pdvobj->rson_data.ver == 1 */ + dvobj->rson_data.ver = RTW_RSON_VER; + dvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID; +#ifdef CONFIG_RTW_REPEATER_SON_ROOT + dvobj->rson_data.hopcnt = RTW_RSON_HC_ROOT; + dvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT; +#else + dvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY; + dvobj->rson_data.connectible = RTW_RSON_DENYCONNECT; +#endif + dvobj->rson_data.loading = 0; + _rtw_memset(dvobj->rson_data.res, 0xAA, sizeof(dvobj->rson_data.res)); +} + +void rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str) +{ + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + + sprintf(rson_data_str, "version : \t%d\nid : \t\t%08x\nhop count : \t%d\nconnectible : \t%s\nloading : \t%d\nreserve : \t%16ph\n", + pdvobj->rson_data.ver, + pdvobj->rson_data.id, + pdvobj->rson_data.hopcnt, + pdvobj->rson_data.connectible ? "connectable":"unconnectable", + pdvobj->rson_data.loading, + pdvobj->rson_data.res); +} + +int str2hexbuf(char *str, u8 *hexbuf, int len) +{ + u8 *p; + int i, slen, idx = 0; + + p = (unsigned char *)str; + if ((*p != '0') || (*(p+1) != 'x')) + return _FALSE; + slen = strlen(str); + if (slen > (len*2) + 2) + return _FALSE; + p += 2; + for (i = 0 ; i < len; i++, idx = idx+2) { + hexbuf[i] = key_2char2num(p[idx], p[idx + 1]); + if (slen <= idx+2) + break; + } + return _TRUE; +} + +int rtw_rson_set_property(_adapter *padapter, char *field, char *value) +{ + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + int num = 0; + + if (_rtw_memcmp(field, (u8 *)"ver", 3) == _TRUE) + pdvobj->rson_data.ver = rtw_atoi(value); + else if (_rtw_memcmp(field, (u8 *)"id", 2) == _TRUE) + num = sscanf(value, "%08x", &(pdvobj->rson_data.id)); + else if (_rtw_memcmp(field, (u8 *)"hc", 2) == _TRUE) + num = sscanf(value, "%hhu", &(pdvobj->rson_data.hopcnt)); + else if (_rtw_memcmp(field, (u8 *)"cnt", 3) == _TRUE) + num = sscanf(value, "%hhu", &(pdvobj->rson_data.connectible)); + else if (_rtw_memcmp(field, (u8 *)"loading", 2) == _TRUE) + num = sscanf(value, "%hhu", &(pdvobj->rson_data.loading)); + else if (_rtw_memcmp(field, (u8 *)"res", 2) == _TRUE) { + str2hexbuf(value, pdvobj->rson_data.res, 16); + return 1; + } else + return _FALSE; + return num; +} + +/* + return : TRUE -- competitor is taking advantage than condidate + FALSE -- we should continue keeping candidate +*/ +int rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor) +{ + s16 comp_score = 0, cand_score = 0; + struct rtw_rson_struct rson_cand, rson_comp; + + if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE) + return _FALSE; + + if ((competitor == NULL) + || (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE) + || (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID)) + return _FALSE; + + comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi); + if (comp_score == RTW_RSON_SCORE_NOTCNNT) + return _FALSE; + + if (*candidate == NULL) + return _TRUE; + if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE) + return _FALSE; + + cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi); + RTW_INFO("%s: competitor_score=%d, candidate_score=%d\n", __func__, comp_score, cand_score); + if (comp_score - cand_score > RSON_SCORE_DIFF_TH) + return _TRUE; + + return _FALSE; +} + +inline u8 rtw_rson_varify_ie(u8 *p) +{ + u8 *ptr = NULL; + u8 ver; + u32 id; + u8 hopcnt; + u8 allcnnt; + + ptr = p + 2 + sizeof(RTW_RSON_OUI); + ver = *ptr; + + /* for (ver == 1) */ + if (ver != 1) + return _FALSE; + + return _TRUE; +} + +/* + Parsing RTK self-organization vendor IE +*/ +int rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct rtw_rson_struct *rson_data) +{ + sint limit = 0; + u32 len; + u8 *p; + + if ((rson_data == NULL) || (bssid == NULL)) + return -EINVAL; + + /* Default */ + rson_data->id = 0; + rson_data->ver = 0; + rson_data->hopcnt = 0; + rson_data->connectible = 0; + rson_data->loading = 0; + /* fake root */ + if (is_match_bssid(bssid->MacAddress, rtw_rson_root_bssid, rtw_rson_root_bssid_idx) == _TRUE) { + rson_data->id = CONFIG_RTW_REPEATER_SON_ID; + rson_data->ver = RTW_RSON_VER; + rson_data->hopcnt = RTW_RSON_HC_ROOT; + rson_data->connectible = RTW_RSON_ALLOWCONNECT; + rson_data->loading = 0; + return _TRUE; + } + limit = bssid->IELength - _BEACON_IE_OFFSET_; + + for (p = bssid->IEs + _BEACON_IE_OFFSET_; ; p += (len + 2)) { + p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, limit); + limit -= len; + if ((p == NULL) || (len == 0)) + break; + if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE) + && rtw_rson_varify_ie(p)) { + p = p + 2 + sizeof(RTW_RSON_OUI); + rson_data->ver = *p; + /* for (ver == 1) */ + p = p + 1; + rson_data->id = le32_to_cpup((__le32 *)p); + p = p + 4; + rson_data->hopcnt = *p; + p = p + 1; + rson_data->connectible = *p; + p = p + 1; + rson_data->loading = *p; + + return _TRUE; + } + } + return -EBADMSG; +} + +u32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len) +{ + u8 *ptr, *ori, ie_len = 0; + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); +/* static int iii = 0;*/ + + if ((!pdvobj) || (!pframe)) + return 0; + ptr = ori = pframe; + *ptr++ = _VENDOR_SPECIFIC_IE_; + *ptr++ = ie_len = sizeof(RTW_RSON_OUI)+sizeof(pdvobj->rson_data); + _rtw_memcpy(ptr, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)); + ptr = ptr + sizeof(RTW_RSON_OUI); + *ptr++ = pdvobj->rson_data.ver; + *(s32 *)ptr = cpu_to_le32(pdvobj->rson_data.id); + ptr = ptr + sizeof(pdvobj->rson_data.id); + *ptr++ = pdvobj->rson_data.hopcnt; + *ptr++ = pdvobj->rson_data.connectible; + *ptr++ = pdvobj->rson_data.loading; + _rtw_memcpy(ptr, pdvobj->rson_data.res, sizeof(pdvobj->rson_data.res)); + pframe = ptr; +/* + iii = iii % 20; + if (iii++ == 0) + RTW_INFO("%s : RTW RSON IE : %20ph\n", __func__, ori); +*/ + *len += (ie_len+2); + return ie_len; + +} + +void rtw_rson_do_disconnect(_adapter *padapter) +{ + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); +#ifndef CONFIG_RTW_REPEATER_SON_ROOT + pdvobj->rson_data.ver = RTW_RSON_VER; + pdvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID; + pdvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY; + pdvobj->rson_data.connectible = RTW_RSON_DENYCONNECT; + pdvobj->rson_data.loading = 0; + rtw_mi_tx_beacon_hdl(padapter); +#endif +} + +void rtw_rson_join_done(_adapter *padapter) +{ + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + WLAN_BSSID_EX *cur_network = NULL; + struct rtw_rson_struct rson_data; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + if (!padapter->mlmepriv.cur_network_scanned) + return; + cur_network = &(padapter->mlmepriv.cur_network_scanned->network); + if (rtw_get_rson_struct(cur_network, &rson_data) != _TRUE) { + RTW_ERR("%s: try to join a improper network(%s)\n", __func__, cur_network->Ssid.Ssid); + return; + } + +#ifndef CONFIG_RTW_REPEATER_SON_ROOT + /* update rson_data */ + pdvobj->rson_data.ver = RTW_RSON_VER; + pdvobj->rson_data.id = rson_data.id; + pdvobj->rson_data.hopcnt = rson_data.hopcnt + 1; + pdvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT; + pdvobj->rson_data.loading = 0; + rtw_mi_tx_beacon_hdl(padapter); +#endif +} + +int rtw_rson_isupdate_roamcan(struct mlme_priv *mlme + , struct wlan_network **candidate, struct wlan_network *competitor) +{ + struct rtw_rson_struct rson_cand, rson_comp, rson_curr; + s16 comp_score, cand_score, curr_score; + + if ((competitor == NULL) + || (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE) + || (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID)) + return _FALSE; + + if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE) + return _FALSE; + + if ((!mlme->cur_network_scanned) + || (mlme->cur_network_scanned == competitor) + || (rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr)) != _TRUE) + return _FALSE; + + if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms) + return _FALSE; + + comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi); + curr_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi); + if (comp_score - curr_score < RSON_SCORE_DIFF_TH) + return _FALSE; + + if (*candidate == NULL) + return _TRUE; + + if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE) { + RTW_ERR("%s : Unable to get rson_struct from candidate(%s -- " MAC_FMT")\n", + __func__, (*candidate)->network.Ssid.Ssid, MAC_ARG((*candidate)->network.MacAddress)); + return _FALSE; + } + cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi); + RTW_DBG("comp_score=%d , cand_score=%d , curr_score=%d\n", comp_score, cand_score, curr_score); + if (cand_score < comp_score) + return _TRUE; + +#if 0 /* Handle 11R protocol */ +#ifdef CONFIG_RTW_80211R + if (rtw_chk_ft_flags(adapter, RTW_FT_SUPPORTED)) { + ptmp = rtw_get_ie(&competitor->network.IEs[12], _MDIE_, &mdie_len, competitor->network.IELength-12); + if (ptmp) { + if (!_rtw_memcmp(&pftpriv->mdid, ptmp+2, 2)) + goto exit; + + /*The candidate don't support over-the-DS*/ + if (rtw_chk_ft_flags(adapter, RTW_FT_STA_OVER_DS_SUPPORTED)) { + if ((rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && !(*(ptmp+4) & 0x01)) || + (!rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && (*(ptmp+4) & 0x01))) { + RTW_INFO("FT: ignore the candidate(" MAC_FMT ") for over-the-DS\n", MAC_ARG(competitor->network.MacAddress)); + rtw_clr_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED); + goto exit; + } + } + } else + goto exit; + } +#endif +#endif + return _FALSE; +} + +void rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead) +{ + struct wlan_network *pnetwork = NULL; + struct rtw_rson_struct rson_data; + s16 rson_score; + u16 index = 0; + + RTW_PRINT_SEL(m, "%5s %-17s %3s %5s %14s %10s %-3s %5s %32s\n", "index", "bssid", "ch", "id", "hop_cnt", "loading", "RSSI", "score", "ssid"); + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (!pnetwork) + break; + + _rtw_memset(&rson_data, 0, sizeof(rson_data)); + rson_score = 0; + if (rtw_get_rson_struct(&(pnetwork->network), &rson_data) == _TRUE) + rson_score = rtw_cal_rson_score(&rson_data, pnetwork->network.Rssi); + RTW_PRINT_SEL(m, "%5d "MAC_FMT" %3d 0x%08x %6d %10d %6d %6d %32s\n", + ++index, + MAC_ARG(pnetwork->network.MacAddress), + pnetwork->network.Configuration.DSConfig, + rson_data.id, + rson_data.hopcnt, + rson_data.loading, + (int)pnetwork->network.Rssi, + rson_score, + pnetwork->network.Ssid.Ssid); + plist = get_next(plist); + } + +} + +/* + Description : As a AP role, We need to check the qualify of associating STA. + We also need to check if we are ready to be associated. + + return : TRUE -- AP REJECT this STA + FALSE -- AP ACCEPT this STA +*/ +u8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset) +{ + struct wlan_network *pnetwork = NULL; + struct rtw_rson_struct rson_target; + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + int len = 0; + u8 ret = _FALSE; + u8 *p; + +#ifndef CONFIG_RTW_REPEATER_SON_ROOT + _rtw_memset(&rson_target, 0, sizeof(rson_target)); + for (p = pframe + WLAN_HDR_A3_LEN + ie_offset; ; p += (len + 2)) { + p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, pkt_len - WLAN_HDR_A3_LEN - ie_offset); + + if ((p == NULL) || (len == 0)) + break; + + if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE) + && rtw_rson_varify_ie(p)) { + p = p + 2 + sizeof(RTW_RSON_OUI); + rson_target.ver = *p; + /* for (ver == 1) */ + p = p + 1; + rson_target.id = le32_to_cpup((__le32 *)p); + p = p + 4; + rson_target.hopcnt = *p; + p = p + 1; + rson_target.connectible = *p; + p = p + 1; + rson_target.loading = *p; + break; + } + } + + if (rson_target.id == 0) /* Normal STA, not a RSON STA */ + ret = _FALSE; + else if (rson_target.id != pdvobj->rson_data.id) { + ret = _TRUE; + RTW_INFO("%s : Reject AssoReq because RSON ID not match, STA=%08x, our=%08x\n", + __func__, rson_target.id, pdvobj->rson_data.id); + } else if ((pdvobj->rson_data.hopcnt == RTW_RSON_HC_NOTREADY) + || (pdvobj->rson_data.connectible == RTW_RSON_DENYCONNECT)) { + ret = _TRUE; + RTW_INFO("%s : Reject AssoReq becuase our hopcnt=%d or connectbile=%d\n", + __func__, pdvobj->rson_data.hopcnt, pdvobj->rson_data.connectible); + } +#endif + return ret; +} + +u8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 *extra_cmd_buf; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + pdrvextra_cmd_parm->ec_id = RSON_SCAN_WK_CID; + pdrvextra_cmd_parm->type = op; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + return res; + +} + +void rtw_rson_scan_cmd_hdl(_adapter *padapter, int op) +{ + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 val8; + + if (mlmeext_chk_scan_state(pmlmeext, SCAN_DISABLE) != _TRUE) + return; + if (op == RSON_SCAN_PROCESS) { + padapter->rtw_rson_scanstage = RSON_SCAN_PROCESS; + val8 = 0x1e; + rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE); + val8 = 1; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + issue_probereq(padapter, NULL, NULL); + /* stop rson_scan after 100ms */ + _set_timer(&(pmlmeext->rson_scan_timer), 100); + } else if (op == RSON_SCAN_DISABLE) { + padapter->rtw_rson_scanstage = RSON_SCAN_DISABLE; + val8 = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + val8 = 0xff; + rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE); + /* report_surveydone_event(padapter);*/ + if (pmlmepriv->to_join == _TRUE) { + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) != _TRUE) { + int s_ret; + + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + pmlmepriv->to_join = _FALSE; + s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv); + if (s_ret == _SUCCESS) + _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); + else if (s_ret == 2) { + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + rtw_indicate_connect(padapter); + } else { + RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(padapter)); + if (rtw_to_roam(padapter) != 0) { + if (rtw_dec_to_roam(padapter) == 0) { + rtw_set_to_roam(padapter, 0); +#ifdef CONFIG_INTEL_WIDI + if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) { + _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN); + intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_WK, NULL, 0); + RTW_INFO("change to widi listen\n"); + } +#endif /* CONFIG_INTEL_WIDI */ + rtw_free_assoc_resources(padapter, _TRUE); + rtw_indicate_disconnect(padapter, 0, _FALSE); + } else + pmlmepriv->to_join = _TRUE; + } else + rtw_indicate_disconnect(padapter, 0, _FALSE); + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + } + } + } else { + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) { + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) + && check_fwstate(pmlmepriv, _FW_LINKED)) { + if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) { +#ifdef CONFIG_RTW_80211R + if (rtw_chk_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED)) { + start_clnt_ft_action(adapter, (u8 *)pmlmepriv->roam_network->network.MacAddress); + } else { + /*wait a little time to retrieve packets buffered in the current ap while scan*/ + _set_timer(&pmlmeext->ft_roam_timer, 30); + } +#else + receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress + , WLAN_REASON_ACTIVE_ROAM, _FALSE); +#endif + } + } + } + issue_action_BSSCoexistPacket(padapter); + issue_action_BSSCoexistPacket(padapter); + issue_action_BSSCoexistPacket(padapter); + } + } else { + RTW_ERR("%s : improper parameter -- op = %d\n", __func__, op); + } +} + +#endif /* CONFIG_RTW_REPEATER_SON */ diff --git a/core/rtw_sdio.c b/core/rtw_sdio.c index 817d60b..e8f49bf 100644 --- a/core/rtw_sdio.c +++ b/core/rtw_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_SDIO_C_ #include /* struct dvobj_priv and etc. */ @@ -39,22 +35,61 @@ */ static u8 sdio_io(struct dvobj_priv *d, u32 addr, void *buf, size_t len, u8 write, u8 cmd52) { + u32 addr_drv; /* address with driver defined bit */ int err; + u8 retry = 0; + u8 stop_retry = _FALSE; /* flag for stopping retry or not */ - if (cmd52) - addr = RTW_SDIO_ADDR_CMD52_GEN(addr); - - if (write) - err = d->intf_ops->write(d, addr, buf, len, 0); - else - err = d->intf_ops->read(d, addr, buf, len, 0); - if (err) { - RTW_INFO("%s: [ERROR] %s FAIL! error(%d)\n", - __FUNCTION__, write ? "write" : "read", err); + if (rtw_is_surprise_removed(dvobj_get_primary_adapter(d))) { + RTW_ERR("%s: bSurpriseRemoved, skip %s 0x%05x, %zu bytes\n", + __FUNCTION__, write?"write":"read", addr, len); return _FAIL; } + addr_drv = addr; + if (cmd52) + addr_drv = RTW_SDIO_ADDR_CMD52_GEN(addr_drv); + + do { + if (write) + err = d->intf_ops->write(d, addr_drv, buf, len, 0); + else + err = d->intf_ops->read(d, addr_drv, buf, len, 0); + if (!err) { + if (retry) { + RTW_INFO("%s: Retry %s OK! addr=0x%05x %zu bytes, retry=%u,%u\n", + __FUNCTION__, write?"write":"read", + addr, len, retry, ATOMIC_READ(&d->continual_io_error)); + RTW_INFO_DUMP("Data: ", buf, len); + } + rtw_reset_continual_io_error(d); + break; + } + RTW_ERR("%s: %s FAIL! error(%d) addr=0x%05x %zu bytes, retry=%u,%u\n", + __FUNCTION__, write?"write":"read", err, addr, len, + retry, ATOMIC_READ(&d->continual_io_error)); + + retry++; + stop_retry = rtw_inc_and_chk_continual_io_error(d); + if ((err == -1) || (stop_retry == _TRUE) || (retry > SD_IO_TRY_CNT)) { + /* critical error, unrecoverable */ + RTW_ERR("%s: Fatal error! Set surprise remove flag ON! (retry=%u,%u)\n", + __FUNCTION__, retry, ATOMIC_READ(&d->continual_io_error)); + rtw_set_surprise_removed(dvobj_get_primary_adapter(d)); + return _FAIL; + } + + /* WLAN IOREG or SDIO Local */ + if ((addr & 0x10000) || !(addr & 0xE000)) { + RTW_WARN("%s: Retry %s addr=0x%05x %zu bytes, retry=%u,%u\n", + __FUNCTION__, write?"write":"read", addr, len, + retry, ATOMIC_READ(&d->continual_io_error)); + continue; + } + return _FAIL; + } while (1); + return _SUCCESS; } @@ -88,11 +123,8 @@ u8 rtw_sdio_f0_read(struct dvobj_priv *d, u32 addr, void *buf, size_t len) addr = RTW_SDIO_ADDR_F0_GEN(addr); err = d->intf_ops->read(d, addr, buf, len, 0); - if (err) { - RTW_INFO("%s: [ERROR] Read f0 register FAIL!\n", __FUNCTION__); + if (err) ret = _FAIL; - } - return ret; } diff --git a/core/rtw_security.c b/core/rtw_security.c index 301e0d4..b537a26 100644 --- a/core/rtw_security.c +++ b/core/rtw_security.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_SECURITY_C_ #include @@ -826,7 +821,7 @@ u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe) if (stainfo != NULL) { if (IS_MCAST(prxattrib->ra)) { - static u32 start = 0; + static systime start = 0; static u32 no_gkey_bc_cnt = 0; static u32 no_gkey_mc_cnt = 0; @@ -987,13 +982,6 @@ static void next_key(u8 *key, sint round); static void byte_sub(u8 *in, u8 *out); static void shift_row(u8 *in, u8 *out); static void mix_column(u8 *in, u8 *out); -#ifndef PLATFORM_FREEBSD -static void add_round_key(u8 *shiftrow_in, - u8 *mcol_in, - u8 *block_in, - sint round, - u8 *out); -#endif /* PLATFORM_FREEBSD */ static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext); @@ -1190,11 +1178,11 @@ static void construct_mic_iv( mic_iv[1] = mpdu[24] & 0x0f; /* mute bits 7-4 */ if (!qc_exists) mic_iv[1] = 0x00; -#ifdef CONFIG_IEEE80211W +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) /* 802.11w management frame should set management bit(4) */ if (frtype == WIFI_MGT_TYPE) mic_iv[1] |= BIT(4); -#endif /* CONFIG_IEEE80211W */ +#endif for (i = 2; i < 8; i++) mic_iv[i] = mpdu[i + 8]; /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */ #ifdef CONSISTENT_PN_ORDER @@ -1224,12 +1212,12 @@ static void construct_mic_header1( { mic_header1[0] = (u8)((header_length - 2) / 256); mic_header1[1] = (u8)((header_length - 2) % 256); -#ifdef CONFIG_IEEE80211W +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) /* 802.11w management frame don't AND subtype bits 4,5,6 of frame control field */ if (frtype == WIFI_MGT_TYPE) mic_header1[2] = mpdu[0]; else -#endif /* CONFIG_IEEE80211W */ +#endif mic_header1[2] = mpdu[0] & 0xcf; /* Mute CF poll & CF ack bits */ mic_header1[3] = mpdu[1] & 0xc7; /* Mute retry, more data and pwr mgt bits */ @@ -1325,11 +1313,11 @@ static void construct_ctr_preload( ctr_preload[1] = mpdu[30] & 0x0f; /* QoC_Control */ if (qc_exists && !a4_exists) ctr_preload[1] = mpdu[24] & 0x0f; -#ifdef CONFIG_IEEE80211W +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) /* 802.11w management frame should set management bit(4) */ if (frtype == WIFI_MGT_TYPE) ctr_preload[1] |= BIT(4); -#endif /* CONFIG_IEEE80211W */ +#endif for (i = 2; i < 8; i++) ctr_preload[i] = mpdu[i + 8]; /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */ #ifdef CONSISTENT_PN_ORDER @@ -1399,8 +1387,7 @@ static sint aes_cipher(u8 *key, uint hdrlen, ((frtype | frsubtype) == WIFI_DATA_CFPOLL) || ((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) { qc_exists = 1; - if (hdrlen != WLAN_HDR_A3_QOS_LEN) - + if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN) hdrlen += 2; } /* add for CONFIG_IEEE80211W, none 11w also can use */ @@ -1409,8 +1396,7 @@ static sint aes_cipher(u8 *key, uint hdrlen, (frsubtype == 0x09) || (frsubtype == 0x0a) || (frsubtype == 0x0b))) { - if (hdrlen != WLAN_HDR_A3_QOS_LEN) - + if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN) hdrlen += 2; qc_exists = 1; } else @@ -1720,8 +1706,7 @@ static sint aes_decipher(u8 *key, uint hdrlen, ((frtype | frsubtype) == WIFI_DATA_CFPOLL) || ((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) { qc_exists = 1; - if (hdrlen != WLAN_HDR_A3_QOS_LEN) - + if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN) hdrlen += 2; } /* only for data packet . add for CONFIG_IEEE80211W, none 11w also can use */ else if ((frtype == WIFI_DATA) && @@ -1729,8 +1714,7 @@ static sint aes_decipher(u8 *key, uint hdrlen, (frsubtype == 0x09) || (frsubtype == 0x0a) || (frsubtype == 0x0b))) { - if (hdrlen != WLAN_HDR_A3_QOS_LEN) - + if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN) hdrlen += 2; qc_exists = 1; } else @@ -1938,7 +1922,6 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) sint length; - u32 prwskeylen; u8 *pframe, *prwskey; /* , *payload,*iv */ struct sta_info *stainfo; struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; @@ -1953,13 +1936,17 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) if (stainfo != NULL) { if (IS_MCAST(prxattrib->ra)) { - static u32 start = 0; + static systime start = 0; static u32 no_gkey_bc_cnt = 0; static u32 no_gkey_mc_cnt = 0; /* RTW_INFO("rx bc/mc packets, to perform sw rtw_aes_decrypt\n"); */ /* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */ - if (psecuritypriv->binstallGrpkey == _FALSE) { + if ((!MLME_IS_MESH(padapter) && psecuritypriv->binstallGrpkey == _FALSE) + #ifdef CONFIG_RTW_MESH + || !(stainfo->gtk_bmp | BIT(prxattrib->key_index)) + #endif + ) { res = _FAIL; if (start == 0) @@ -1991,12 +1978,20 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) no_gkey_bc_cnt = 0; no_gkey_mc_cnt = 0; - prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; - if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) { - RTW_DBG("not match packet_index=%d, install_index=%d\n" - , prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid); - res = _FAIL; - goto exit; + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* TODO: multiple GK? */ + prwskey = &stainfo->gtk.skey[0]; + } else + #endif + { + prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; + if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) { + RTW_DBG("not match packet_index=%d, install_index=%d\n" + , prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid); + res = _FAIL; + goto exit; + } } } else prwskey = &stainfo->dot118021x_UncstKey.skey[0]; @@ -2038,94 +2033,96 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) } #ifdef CONFIG_IEEE80211W -u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe) +u32 rtw_BIP_verify(_adapter *padapter, u8 *whdr_pos, sint flen + , const u8 *key, u16 keyid, u64* ipn) { - struct rx_pkt_attrib *pattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; - u8 *pframe; - u8 *BIP_AAD, *p; + u8 *BIP_AAD, *mme; u32 res = _FAIL; uint len, ori_len; + u16 pkt_keyid = 0; + u64 pkt_ipn = 0; struct rtw_ieee80211_hdr *pwlanhdr; u8 mic[16]; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - ori_len = pattrib->pkt_len - WLAN_HDR_A3_LEN + BIP_AAD_SIZE; - BIP_AAD = rtw_zmalloc(ori_len); + mme = whdr_pos + flen - 18; + if (*mme != _MME_IE_) + return RTW_RX_HANDLED; + + /* copy key index */ + _rtw_memcpy(&pkt_keyid, mme + 2, 2); + pkt_keyid = le16_to_cpu(pkt_keyid); + if (pkt_keyid != keyid) { + RTW_INFO("BIP key index error!\n"); + return _FAIL; + } + + /* save packet number */ + _rtw_memcpy(&pkt_ipn, mme + 4, 6); + pkt_ipn = le64_to_cpu(pkt_ipn); + /* BIP packet number should bigger than previous BIP packet */ + if (pkt_ipn <= *ipn) { /* wrap around? */ + RTW_INFO("replay BIP packet\n"); + return _FAIL; + } + + ori_len = flen - WLAN_HDR_A3_LEN + BIP_AAD_SIZE; + BIP_AAD = rtw_zmalloc(ori_len); if (BIP_AAD == NULL) { RTW_INFO("BIP AAD allocate fail\n"); return _FAIL; } - /* PKT start */ - pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data; + /* mapping to wlan header */ - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + pwlanhdr = (struct rtw_ieee80211_hdr *)whdr_pos; + /* save the frame body + MME */ - _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, pframe + WLAN_HDR_A3_LEN, pattrib->pkt_len - WLAN_HDR_A3_LEN); - /* find MME IE pointer */ - p = rtw_get_ie(BIP_AAD + BIP_AAD_SIZE, _MME_IE_, &len, pattrib->pkt_len - WLAN_HDR_A3_LEN); - /* Baron */ - if (p) { - u16 keyid = 0; - u64 temp_ipn = 0; - /* save packet number */ - _rtw_memcpy(&temp_ipn, p + 4, 6); - temp_ipn = le64_to_cpu(temp_ipn); - /* BIP packet number should bigger than previous BIP packet */ - if (temp_ipn < pmlmeext->mgnt_80211w_IPN_rx) { - RTW_INFO("replay BIP packet\n"); - goto BIP_exit; - } - /* copy key index */ - _rtw_memcpy(&keyid, p + 2, 2); - keyid = le16_to_cpu(keyid); - if (keyid != padapter->securitypriv.dot11wBIPKeyid) { - RTW_INFO("BIP key index error!\n"); - goto BIP_exit; - } - /* clear the MIC field of MME to zero */ - _rtw_memset(p + 2 + len - 8, 0, 8); + _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, whdr_pos + WLAN_HDR_A3_LEN, flen - WLAN_HDR_A3_LEN); + + /* point mme to the copy */ + mme = BIP_AAD + ori_len - 18; - /* conscruct AAD, copy frame control field */ - _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); - ClearRetry(BIP_AAD); - ClearPwrMgt(BIP_AAD); - ClearMData(BIP_AAD); - /* conscruct AAD, copy address 1 to address 3 */ - _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18); + /* clear the MIC field of MME to zero */ + _rtw_memset(mme + 10, 0, 8); - if (omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey - , BIP_AAD, ori_len, mic)) - goto BIP_exit; + /* conscruct AAD, copy frame control field */ + _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); + ClearRetry(BIP_AAD); + ClearPwrMgt(BIP_AAD); + ClearMData(BIP_AAD); + /* conscruct AAD, copy address 1 to address 3 */ + _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18); + + if (omac1_aes_128(key, BIP_AAD, ori_len, mic)) + goto BIP_exit; #if 0 - /* management packet content */ - { - int pp; - RTW_INFO("pkt: "); - for (pp = 0; pp < pattrib->pkt_len; pp++) - printk(" %02x ", pframe[pp]); - RTW_INFO("\n"); - /* BIP AAD + management frame body + MME(MIC is zero) */ - RTW_INFO("AAD+PKT: "); - for (pp = 0; pp < ori_len; pp++) - RTW_INFO(" %02x ", BIP_AAD[pp]); - RTW_INFO("\n"); - /* show the MIC result */ - RTW_INFO("mic: "); - for (pp = 0; pp < 16; pp++) - RTW_INFO(" %02x ", mic[pp]); - RTW_INFO("\n"); - } + /* management packet content */ + { + int pp; + RTW_INFO("pkt: "); + for (pp = 0; pp < flen; pp++) + printk(" %02x ", whdr_pos[pp]); + RTW_INFO("\n"); + /* BIP AAD + management frame body + MME(MIC is zero) */ + RTW_INFO("AAD+PKT: "); + for (pp = 0; pp < ori_len; pp++) + RTW_INFO(" %02x ", BIP_AAD[pp]); + RTW_INFO("\n"); + /* show the MIC result */ + RTW_INFO("mic: "); + for (pp = 0; pp < 16; pp++) + RTW_INFO(" %02x ", mic[pp]); + RTW_INFO("\n"); + } #endif - /* MIC field should be last 8 bytes of packet (packet without FCS) */ - if (_rtw_memcmp(mic, pframe + pattrib->pkt_len - 8, 8)) { - pmlmeext->mgnt_80211w_IPN_rx = temp_ipn; - res = _SUCCESS; - } else - RTW_INFO("BIP MIC error!\n"); + /* MIC field should be last 8 bytes of packet (packet without FCS) */ + if (_rtw_memcmp(mic, whdr_pos + flen - 8, 8)) { + *ipn = pkt_ipn; + res = _SUCCESS; } else - res = RTW_RX_HANDLED; + RTW_INFO("BIP MIC error!\n"); + BIP_exit: rtw_mfree(BIP_AAD, ori_len); @@ -2134,6 +2131,7 @@ u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe) #endif /* CONFIG_IEEE80211W */ #ifndef PLATFORM_FREEBSD +#if defined(CONFIG_TDLS) /* compress 512-bits */ static int sha256_compress(struct sha256_state *md, unsigned char *buf) { @@ -2210,7 +2208,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in, unsigned long n; #define block_size 64 - if (md->curlen > sizeof(md->buf)) + if (md->curlen >= sizeof(md->buf)) return -1; while (inlen > 0) { @@ -2314,10 +2312,12 @@ static u8 os_strlen(const char *s) p++; return p - s; } +#endif -static int os_memcmp(void *s1, void *s2, u8 n) +#if defined(CONFIG_TDLS) || defined(CONFIG_RTW_MESH_AEK) +static int os_memcmp(const void *s1, const void *s2, u8 n) { - unsigned char *p1 = s1, *p2 = s2; + const unsigned char *p1 = s1, *p2 = s2; if (n == 0) return 0; @@ -2332,6 +2332,7 @@ static int os_memcmp(void *s1, void *s2, u8 n) return *p1 - *p2; } +#endif /** * hmac_sha256_vector - HMAC-SHA256 over data vector (RFC 2104) @@ -2342,6 +2343,7 @@ static int os_memcmp(void *s1, void *s2, u8 n) * @len: Lengths of the data blocks * @mac: Buffer for the hash (32 bytes) */ +#if defined(CONFIG_TDLS) static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem, u8 *addr[], size_t *len, u8 *mac) { @@ -2403,6 +2405,7 @@ static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem, _len[1] = 32; sha256_vector(2, _addr, _len, mac); } +#endif /* CONFIG_TDLS */ #endif /* PLATFORM_FREEBSD */ /** * sha256_prf - SHA256-based Pseudo-Random Function (IEEE 802.11r, 8.5.1.5.2) @@ -2418,6 +2421,7 @@ static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem, * given key. */ #ifndef PLATFORM_FREEBSD /* Baron */ +#if defined(CONFIG_TDLS) static void sha256_prf(u8 *key, size_t key_len, char *label, u8 *data, size_t data_len, u8 *buf, size_t buf_len) { @@ -2454,6 +2458,7 @@ static void sha256_prf(u8 *key, size_t key_len, char *label, counter++; } } +#endif #endif /* PLATFORM_FREEBSD Baron */ /* AES tables*/ @@ -2723,7 +2728,7 @@ static void rijndaelEncrypt(u32 rk[/*44*/], u8 pt[16], u8 ct[16]) PUTU32(ct + 12, s3); } -static void *aes_encrypt_init(u8 *key, size_t len) +static void *aes_encrypt_init(const u8 *key, size_t len) { u32 *rk; if (len != 16) @@ -2773,12 +2778,12 @@ static void aes_encrypt_deinit(void *ctx) * OMAC1 was standardized with the name CMAC by NIST in a Special Publication * (SP) 800-38B. */ -static int omac1_aes_128_vector(u8 *key, size_t num_elem, - u8 *addr[], size_t *len, u8 *mac) +static int omac1_aes_128_vector(const u8 *key, size_t num_elem, + const u8 *addr[], const size_t *len, u8 *mac) { void *ctx; u8 cbc[AES_BLOCK_SIZE], pad[AES_BLOCK_SIZE]; - u8 *pos, *end; + const u8 *pos, *end; size_t i, e, left, total_len; ctx = aes_encrypt_init(key, 16); @@ -2846,12 +2851,237 @@ static int omac1_aes_128_vector(u8 *key, size_t num_elem, * OMAC1 was standardized with the name CMAC by NIST in a Special Publication * (SP) 800-38B. */ /* modify for CONFIG_IEEE80211W */ -int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac) +int omac1_aes_128(const u8 *key, const u8 *data, size_t data_len, u8 *mac) { return omac1_aes_128_vector(key, 1, &data, &data_len, mac); } #endif /* PLATFORM_FREEBSD Baron */ +#ifdef CONFIG_RTW_MESH_AEK +/* for AES-SIV */ +#define os_memset _rtw_memset +#define os_memcpy _rtw_memcpy +#define os_malloc rtw_malloc +#define bin_clear_free(bin, len) \ + do { \ + if (bin) { \ + os_memset(bin, 0, len); \ + rtw_mfree(bin, len); \ + } \ + } while (0) + +static const u8 zero[AES_BLOCK_SIZE]; + +static void dbl(u8 *pad) +{ + int i, carry; + + carry = pad[0] & 0x80; + for (i = 0; i < AES_BLOCK_SIZE - 1; i++) + pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7); + pad[AES_BLOCK_SIZE - 1] <<= 1; + if (carry) + pad[AES_BLOCK_SIZE - 1] ^= 0x87; +} + +static void xor(u8 *a, const u8 *b) +{ + int i; + + for (i = 0; i < AES_BLOCK_SIZE; i++) + *a++ ^= *b++; +} + +static void xorend(u8 *a, int alen, const u8 *b, int blen) +{ + int i; + + if (alen < blen) + return; + + for (i = 0; i < blen; i++) + a[alen - blen + i] ^= b[i]; +} + +static void pad_block(u8 *pad, const u8 *addr, size_t len) +{ + os_memset(pad, 0, AES_BLOCK_SIZE); + os_memcpy(pad, addr, len); + + if (len < AES_BLOCK_SIZE) + pad[len] = 0x80; +} + +static int aes_s2v(const u8 *key, size_t num_elem, const u8 *addr[], + size_t *len, u8 *mac) +{ + u8 tmp[AES_BLOCK_SIZE], tmp2[AES_BLOCK_SIZE]; + u8 *buf = NULL; + int ret; + size_t i; + + if (!num_elem) { + os_memcpy(tmp, zero, sizeof(zero)); + tmp[AES_BLOCK_SIZE - 1] = 1; + return omac1_aes_128(key, tmp, sizeof(tmp), mac); + } + + ret = omac1_aes_128(key, zero, sizeof(zero), tmp); + if (ret) + return ret; + + for (i = 0; i < num_elem - 1; i++) { + ret = omac1_aes_128(key, addr[i], len[i], tmp2); + if (ret) + return ret; + + dbl(tmp); + xor(tmp, tmp2); + } + if (len[i] >= AES_BLOCK_SIZE) { + buf = os_malloc(len[i]); + if (!buf) + return -ENOMEM; + + os_memcpy(buf, addr[i], len[i]); + xorend(buf, len[i], tmp, AES_BLOCK_SIZE); + ret = omac1_aes_128(key, buf, len[i], mac); + bin_clear_free(buf, len[i]); + return ret; + } + + dbl(tmp); + pad_block(tmp2, addr[i], len[i]); + xor(tmp, tmp2); + + return omac1_aes_128(key, tmp, sizeof(tmp), mac); +} + +/** + * aes_128_ctr_encrypt - AES-128 CTR mode encryption + * @key: Key for encryption (16 bytes) + * @nonce: Nonce for counter mode (16 bytes) + * @data: Data to encrypt in-place + * @data_len: Length of data in bytes + * Returns: 0 on success, -1 on failure + */ +int aes_128_ctr_encrypt(const u8 *key, const u8 *nonce, + u8 *data, size_t data_len) +{ + void *ctx; + size_t j, len, left = data_len; + int i; + u8 *pos = data; + u8 counter[AES_BLOCK_SIZE], buf[AES_BLOCK_SIZE]; + + ctx = aes_encrypt_init(key, 16); + if (ctx == NULL) + return -1; + os_memcpy(counter, nonce, AES_BLOCK_SIZE); + + while (left > 0) { + #if 0 + aes_encrypt(ctx, counter, buf); + #else + aes_128_encrypt(ctx, counter, buf); + #endif + + len = (left < AES_BLOCK_SIZE) ? left : AES_BLOCK_SIZE; + for (j = 0; j < len; j++) + pos[j] ^= buf[j]; + pos += len; + left -= len; + + for (i = AES_BLOCK_SIZE - 1; i >= 0; i--) { + counter[i]++; + if (counter[i]) + break; + } + } + aes_encrypt_deinit(ctx); + return 0; +} + +int aes_siv_encrypt(const u8 *key, const u8 *pw, + size_t pwlen, size_t num_elem, + const u8 *addr[], const size_t *len, u8 *out) +{ + const u8 *_addr[6]; + size_t _len[6]; + const u8 *k1 = key, *k2 = key + 16; + u8 v[AES_BLOCK_SIZE]; + size_t i; + u8 *iv, *crypt_pw; + + if (num_elem > ARRAY_SIZE(_addr) - 1) + return -1; + + for (i = 0; i < num_elem; i++) { + _addr[i] = addr[i]; + _len[i] = len[i]; + } + _addr[num_elem] = pw; + _len[num_elem] = pwlen; + + if (aes_s2v(k1, num_elem + 1, _addr, _len, v)) + return -1; + + iv = out; + crypt_pw = out + AES_BLOCK_SIZE; + + os_memcpy(iv, v, AES_BLOCK_SIZE); + os_memcpy(crypt_pw, pw, pwlen); + + /* zero out 63rd and 31st bits of ctr (from right) */ + v[8] &= 0x7f; + v[12] &= 0x7f; + return aes_128_ctr_encrypt(k2, v, crypt_pw, pwlen); +} + +int aes_siv_decrypt(const u8 *key, const u8 *iv_crypt, size_t iv_c_len, + size_t num_elem, const u8 *addr[], const size_t *len, + u8 *out) +{ + const u8 *_addr[6]; + size_t _len[6]; + const u8 *k1 = key, *k2 = key + 16; + size_t crypt_len; + size_t i; + int ret; + u8 iv[AES_BLOCK_SIZE]; + u8 check[AES_BLOCK_SIZE]; + + if (iv_c_len < AES_BLOCK_SIZE || num_elem > ARRAY_SIZE(_addr) - 1) + return -1; + crypt_len = iv_c_len - AES_BLOCK_SIZE; + + for (i = 0; i < num_elem; i++) { + _addr[i] = addr[i]; + _len[i] = len[i]; + } + _addr[num_elem] = out; + _len[num_elem] = crypt_len; + + os_memcpy(iv, iv_crypt, AES_BLOCK_SIZE); + os_memcpy(out, iv_crypt + AES_BLOCK_SIZE, crypt_len); + + iv[8] &= 0x7f; + iv[12] &= 0x7f; + + ret = aes_128_ctr_encrypt(k2, iv, out, crypt_len); + if (ret) + return ret; + + ret = aes_s2v(k1, num_elem + 1, _addr, _len, check); + if (ret) + return ret; + if (os_memcmp(check, iv_crypt, AES_BLOCK_SIZE) == 0) + return 0; + + return -1; +} +#endif /* CONFIG_RTW_MESH_AEK */ + #ifdef CONFIG_TDLS void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta) { @@ -2888,11 +3118,11 @@ void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta) * added by the KDF anyway.. */ - if (os_memcmp(adapter_mac_addr(padapter), psta->hwaddr, ETH_ALEN) < 0) { + if (os_memcmp(adapter_mac_addr(padapter), psta->cmn.mac_addr, ETH_ALEN) < 0) { _rtw_memcpy(data, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(data + ETH_ALEN, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(data + ETH_ALEN, psta->cmn.mac_addr, ETH_ALEN); } else { - _rtw_memcpy(data, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(data, psta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(data + ETH_ALEN, adapter_mac_addr(padapter), ETH_ALEN); } _rtw_memcpy(data + 2 * ETH_ALEN, get_bssid(pmlmepriv), ETH_ALEN); diff --git a/core/rtw_sreset.c b/core/rtw_sreset.c index 3ea40d9..03dba20 100644 --- a/core/rtw_sreset.c +++ b/core/rtw_sreset.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #include @@ -52,10 +47,9 @@ u8 sreset_get_wifi_status(_adapter *padapter) #if defined(DBG_CONFIG_ERROR_DETECT) HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct sreset_priv *psrtpriv = &pHalData->srestpriv; - u8 status = WIFI_STATUS_SUCCESS; u32 val32 = 0; - _irqL irqL; + if (psrtpriv->silent_reset_inprogress == _TRUE) return status; val32 = rtw_read32(padapter, REG_TXDMA_STATUS); @@ -109,11 +103,9 @@ bool sreset_inprogress(_adapter *padapter) void sreset_restore_security_station(_adapter *padapter) { - u8 EntryId = 0; struct mlme_priv *mlmepriv = &padapter->mlmepriv; struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta; - struct security_priv *psecuritypriv = &(padapter->securitypriv); struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; { @@ -131,31 +123,18 @@ void sreset_restore_security_station(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); } -#if 0 - if ((padapter->securitypriv.dot11PrivacyAlgrthm == _WEP40_) || - (padapter->securitypriv.dot11PrivacyAlgrthm == _WEP104_)) { - - for (EntryId = 0; EntryId < 4; EntryId++) { - if (EntryId == psecuritypriv->dot11PrivacyKeyIndex) - rtw_set_key(padapter, &padapter->securitypriv, EntryId, 1, _FALSE); - else - rtw_set_key(padapter, &padapter->securitypriv, EntryId, 0, _FALSE); - } - - } else -#endif - if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || - (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) { - psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv)); - if (psta == NULL) { - /* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */ - } else { - /* pairwise key */ - rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE); - /* group key */ - rtw_set_key(padapter, &padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE); - } + if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || + (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) { + psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv)); + if (psta == NULL) { + /* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */ + } else { + /* pairwise key */ + rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE); + /* group key */ + rtw_set_key(padapter, &padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE); } + } } void sreset_restore_network_station(_adapter *padapter) @@ -165,32 +144,14 @@ void sreset_restore_network_station(_adapter *padapter) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u8 doiqk = _FALSE; -#if 0 - { - /* ======================================================= */ - /* reset related register of Beacon control */ - - /* set MSR to nolink */ - Set_MSR(padapter, _HW_STATE_NOLINK_); - /* reject all data frame */ - rtw_write16(padapter, REG_RXFLTMAP2, 0x00); - /* reset TSF */ - rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); - - /* disable update TSF */ - SetBcnCtrlReg(padapter, BIT(4), 0); - - /* ======================================================= */ - } -#endif - - rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, _FALSE); + rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY); { u8 threshold; #ifdef CONFIG_USB_HCI /* TH=1 => means that invalidate usb rx aggregation */ /* TH=0 => means that validate usb rx aggregation, use init value. */ +#ifdef CONFIG_80211N_HT if (mlmepriv->htpriv.ht_option) { if (padapter->registrypriv.wifi_spec == 1) threshold = 1; @@ -201,6 +162,7 @@ void sreset_restore_network_station(_adapter *padapter) threshold = 1; rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold)); } +#endif /* CONFIG_80211N_HT */ #endif } @@ -218,6 +180,8 @@ void sreset_restore_network_station(_adapter *padapter) { u8 join_type = 0; + + rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING); rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); } @@ -234,14 +198,12 @@ void sreset_restore_network_station(_adapter *padapter) void sreset_restore_network_status(_adapter *padapter) { struct mlme_priv *mlmepriv = &padapter->mlmepriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) { RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); sreset_restore_network_station(padapter); - } else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) { - RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); + } else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { + RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(padapter), MLME_IS_AP(padapter) ? "AP" : "MESH"); rtw_ap_restore_network(padapter); } else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); @@ -273,7 +235,7 @@ void sreset_stop_adapter(_adapter *padapter) if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) { rtw_set_to_roam(padapter, 0); - rtw_join_timeout(pmlmepriv); + rtw_join_timeout_handler(padapter); } } @@ -311,7 +273,7 @@ void sreset_reset(_adapter *padapter) struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; _irqL irqL; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; @@ -333,6 +295,9 @@ void sreset_reset(_adapter *padapter) #ifdef CONFIG_IPS _ips_enter(padapter); _ips_leave(padapter); +#endif +#ifdef CONFIG_CONCURRENT_MODE + rtw_mi_ap_info_restore(padapter); #endif rtw_mi_sreset_adapter_hdl(padapter, _TRUE);/*sreset_start_adapter*/ @@ -342,5 +307,8 @@ void sreset_reset(_adapter *padapter) RTW_INFO("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); pdbgpriv->dbg_sreset_cnt++; + + psrtpriv->self_dect_fw = _FALSE; + psrtpriv->rx_cnt = 0; #endif } diff --git a/core/rtw_sta_mgt.c b/core/rtw_sta_mgt.c index 46e1bc9..f4fbdb4 100644 --- a/core/rtw_sta_mgt.c +++ b/core/rtw_sta_mgt.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_STA_MGT_C_ #include @@ -133,6 +128,46 @@ inline bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, return ret; } +void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos) +{ + _adapter *adapter = sta->padapter; + struct ethhdr *etherhdr = (struct ethhdr *)ehdr_pos; + + if (ntohs(etherhdr->h_proto) == ETH_P_IP) { + u8 *ip = ehdr_pos + ETH_HLEN; + + if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */ + && rtw_st_ctl_chk_reg_s_proto(&sta->st_ctl, 0x06) == _TRUE + ) { + u8 *tcp = ip + GET_IPV4_IHL(ip) * 4; + + if (rtw_st_ctl_chk_reg_rule(&sta->st_ctl, adapter, IPV4_DST(ip), TCP_DST(tcp), IPV4_SRC(ip), TCP_SRC(tcp)) == _TRUE) { + if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) { + session_tracker_add_cmd(adapter, sta + , IPV4_DST(ip), TCP_DST(tcp) + , IPV4_SRC(ip), TCP_SRC(tcp)); + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n" + , FUNC_ADPT_ARG(adapter) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); + } + if (GET_TCP_FIN(tcp)) { + session_tracker_del_cmd(adapter, sta + , IPV4_DST(ip), TCP_DST(tcp) + , IPV4_SRC(ip), TCP_SRC(tcp)); + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n" + , FUNC_ADPT_ARG(adapter) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); + } + } + + } + } +} + #define SESSION_TRACKER_FMT IP_FMT":"PORT_FMT" "IP_FMT":"PORT_FMT" %u %d" #define SESSION_TRACKER_ARG(st) IP_ARG(&(st)->local_naddr), PORT_ARG(&(st)->local_port), IP_ARG(&(st)->remote_naddr), PORT_ARG(&(st)->remote_port), (st)->status, rtw_get_passing_time_ms((st)->set_time) @@ -165,8 +200,6 @@ void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl) void _rtw_init_stainfo(struct sta_info *psta); void _rtw_init_stainfo(struct sta_info *psta) { - - _rtw_memset((u8 *)psta, 0, sizeof(struct sta_info)); _rtw_spinlock_init(&psta->lock); @@ -177,62 +210,36 @@ void _rtw_init_stainfo(struct sta_info *psta) /* _rtw_init_listhead(&psta->wakeup_list); */ _rtw_init_queue(&psta->sleep_q); - psta->sleepq_len = 0; _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); _rtw_init_sta_recv_priv(&psta->sta_recvpriv); #ifdef CONFIG_AP_MODE - _rtw_init_listhead(&psta->asoc_list); - _rtw_init_listhead(&psta->auth_list); - - psta->expire_to = 0; - - psta->flags = 0; - - psta->capability = 0; - psta->bpairwise_key_installed = _FALSE; #ifdef CONFIG_RTW_80211R psta->ft_pairwise_key_installed = _FALSE; #endif - -#ifdef CONFIG_NATIVEAP_MLME - psta->nonerp_set = 0; - psta->no_short_slot_time_set = 0; - psta->no_short_preamble_set = 0; - psta->no_ht_gf_set = 0; - psta->no_ht_set = 0; - psta->ht_20mhz_set = 0; - psta->ht_40mhz_intolerant = 0; -#endif - -#ifdef CONFIG_TX_MCAST2UNI - psta->under_exist_checking = 0; -#endif /* CONFIG_TX_MCAST2UNI */ - - psta->keep_alive_trycnt = 0; - #endif /* CONFIG_AP_MODE */ rtw_st_ctl_init(&psta->st_ctl); - - } u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) { + _adapter *adapter = container_of(pstapriv, _adapter, stapriv); + struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); struct sta_info *psta; s32 i; + u32 ret = _FAIL; + pstapriv->padapter = adapter; pstapriv->pallocated_stainfo_buf = rtw_zvmalloc(sizeof(struct sta_info) * NUM_STA + 4); - if (!pstapriv->pallocated_stainfo_buf) - return _FAIL; + goto exit; pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 - ((SIZE_PTR)(pstapriv->pallocated_stainfo_buf) & 3); @@ -262,9 +269,19 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) pstapriv->adhoc_expire_to = 4; /* 4 * 2 = 8 sec */ #ifdef CONFIG_AP_MODE - - pstapriv->sta_dz_bitmap = 0; - pstapriv->tim_bitmap = 0; + pstapriv->max_aid = macid_ctl->num; + pstapriv->rr_aid = 0; + pstapriv->started_aid = 1; + pstapriv->sta_aid = rtw_zmalloc(pstapriv->max_aid * sizeof(struct sta_info *)); + if (!pstapriv->sta_aid) + goto exit; + pstapriv->aid_bmp_len = AID_BMP_LEN(pstapriv->max_aid); + pstapriv->sta_dz_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len); + if (!pstapriv->sta_dz_bitmap) + goto exit; + pstapriv->tim_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len); + if (!pstapriv->tim_bitmap) + goto exit; _rtw_init_listhead(&pstapriv->asoc_list); _rtw_init_listhead(&pstapriv->auth_list); @@ -290,15 +307,29 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) #endif #if CONFIG_RTW_MACADDR_ACL - _rtw_init_queue(&(pstapriv->acl_list.acl_node_q)); + for (i = 0; i < RTW_ACL_PERIOD_NUM; i++) + rtw_macaddr_acl_init(adapter, i); #endif #if CONFIG_RTW_PRE_LINK_STA rtw_pre_link_sta_ctl_init(pstapriv); #endif - return _SUCCESS; + ret = _SUCCESS; +exit: + if (ret != _SUCCESS) { + if (pstapriv->pallocated_stainfo_buf) + rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info) * NUM_STA + 4); + #ifdef CONFIG_AP_MODE + if (pstapriv->sta_aid) + rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *)); + if (pstapriv->sta_dz_bitmap) + rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); + #endif + } + + return ret; } inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta) @@ -431,7 +462,8 @@ u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) rtw_mfree_sta_priv_lock(pstapriv); #if CONFIG_RTW_MACADDR_ACL - _rtw_deinit_queue(&(pstapriv->acl_list.acl_node_q)); + for (index = 0; index < RTW_ACL_PERIOD_NUM; index++) + rtw_macaddr_acl_deinit(pstapriv->padapter, index); #endif #if CONFIG_RTW_PRE_LINK_STA @@ -440,6 +472,14 @@ u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) if (pstapriv->pallocated_stainfo_buf) rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info) * NUM_STA + 4); + #ifdef CONFIG_AP_MODE + if (pstapriv->sta_aid) + rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *)); + if (pstapriv->sta_dz_bitmap) + rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); + if (pstapriv->tim_bitmap) + rtw_mfree(pstapriv->tim_bitmap, pstapriv->aid_bmp_len); + #endif } return _SUCCESS; @@ -450,15 +490,15 @@ static void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl) { _adapter *padapter = preorder_ctrl->padapter; - rtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter, rtw_reordering_ctrl_timeout_handler); - +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) + rtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter, rtw_reordering_ctrl_timeout_handler, preorder_ctrl); +#endif } /* struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) */ -struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) +struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) { - _irqL irqL, irqL2; - uint tmp_aid; + _irqL irqL2; s32 index; _list *phash_list; struct sta_info *psta; @@ -482,14 +522,11 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) rtw_list_delete(&(psta->list)); /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */ - - tmp_aid = psta->aid; - _rtw_init_stainfo(psta); psta->padapter = pstapriv->padapter; - _rtw_memcpy(psta->hwaddr, hwaddr, ETH_ALEN); + _rtw_memcpy(psta->cmn.mac_addr, hwaddr, ETH_ALEN); index = wifi_mac_hash(hwaddr); @@ -513,10 +550,13 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) * In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable. * So, we initialize the tid_rxseq variable as the 0xffff. */ - for (i = 0; i < 16; i++) + for (i = 0; i < 16; i++) { _rtw_memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2); + _rtw_memcpy(&psta->sta_recvpriv.bmc_tid_rxseq[i], &wRxSeqInitialValue, 2); + _rtw_memset(&psta->sta_recvpriv.rxcache.iv[i], 0, sizeof(psta->sta_recvpriv.rxcache.iv[i])); + } - rtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl); + rtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl, psta); #ifdef CONFIG_IEEE80211W rtw_init_timer(&psta->dot11w_expire_timer, psta->padapter, sa_query_timer_hdl, psta); #endif /* CONFIG_IEEE80211W */ @@ -527,16 +567,14 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) /* for A-MPDU Rx reordering buffer control */ for (i = 0; i < 16 ; i++) { preorder_ctrl = &psta->recvreorder_ctrl[i]; - preorder_ctrl->padapter = pstapriv->padapter; - + preorder_ctrl->tid = i; preorder_ctrl->enable = _FALSE; - preorder_ctrl->indicate_seq = 0xffff; -#ifdef DBG_RX_SEQ - RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d\n", __FUNCTION__, __LINE__, - preorder_ctrl->indicate_seq); -#endif + #ifdef DBG_RX_SEQ + RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d\n" + , FUNC_ADPT_ARG(pstapriv->padapter), i, preorder_ctrl->indicate_seq); + #endif preorder_ctrl->wend_b = 0xffff; /* preorder_ctrl->wsize_b = (NR_RECVBUFF-2); */ preorder_ctrl->wsize_b = 64;/* 64; */ @@ -549,14 +587,15 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) /* init for DM */ - psta->rssi_stat.undecorated_smoothed_pwdb = (-1); - psta->rssi_stat.undecorated_smoothed_cck = (-1); + psta->cmn.rssi_stat.rssi = (-1); + psta->cmn.rssi_stat.rssi_cck = (-1); + psta->cmn.rssi_stat.rssi_ofdm = (-1); #ifdef CONFIG_ATMEL_RC_PATCH psta->flag_atmel_rc = 0; #endif /* init for the sequence number of received management frame */ psta->RxMgmtFrameSeqNum = 0xffff; - psta->ra_rpt_linked = _FALSE; + _rtw_memset(&psta->sta_stats, 0, sizeof(struct stainfo_stats)); rtw_alloc_macid(pstapriv->padapter, psta); @@ -585,13 +624,20 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct sta_priv *pstapriv = &padapter->stapriv; struct hw_xmit *phwxmit; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int pending_qcnt[4]; u8 is_pre_link_sta = _FALSE; if (psta == NULL) goto exit; - is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->hwaddr); +#ifdef CONFIG_RTW_80211K + rm_post_event(padapter, RM_ID_FOR_ALL(psta->cmn.aid), RM_EV_cancel); +#endif + + is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr); if (is_pre_link_sta == _FALSE) { _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); @@ -678,7 +724,6 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) #ifdef CONFIG_TDLS psta->tdls_sta_state = TDLS_STATE_NONE; - rtw_free_tdls_timer(psta); #endif /* CONFIG_TDLS */ /* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */ @@ -715,7 +760,7 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) } - if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->hwaddr)) && is_pre_link_sta == _FALSE) + if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->cmn.mac_addr)) && is_pre_link_sta == _FALSE) rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE); @@ -754,14 +799,16 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) #ifdef CONFIG_NATIVEAP_MLME - pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); - pstapriv->tim_bitmap &= ~BIT(psta->aid); + if (pmlmeinfo->state == _HW_STATE_AP_) { + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); - /* rtw_indicate_sta_disassoc_event(padapter, psta); */ + /* rtw_indicate_sta_disassoc_event(padapter, psta); */ - if ((psta->aid > 0) && (pstapriv->sta_aid[psta->aid - 1] == psta)) { - pstapriv->sta_aid[psta->aid - 1] = NULL; - psta->aid = 0; + if ((psta->cmn.aid > 0) && (pstapriv->sta_aid[psta->cmn.aid - 1] == psta)) { + pstapriv->sta_aid[psta->cmn.aid - 1] = NULL; + psta->cmn.aid = 0; + } } #endif /* CONFIG_NATIVEAP_MLME */ @@ -817,7 +864,7 @@ void rtw_free_all_stainfo(_adapter *padapter) plist = get_next(plist); if (pbcmc_stainfo != psta) { - if (rtw_is_pre_link_sta(pstapriv, psta->hwaddr) == _FALSE) + if (rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr) == _FALSE) rtw_list_delete(&psta->hash_list); stainfo_offset = rtw_stainfo_offset(pstapriv, psta); @@ -841,7 +888,7 @@ void rtw_free_all_stainfo(_adapter *padapter) } /* any station allocated can be searched by hash list */ -struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) +struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) { _irqL irqL; @@ -852,7 +899,7 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) u32 index; - u8 *addr; + const u8 *addr; u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; @@ -877,7 +924,7 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); - if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN)) == _TRUE) { + if ((_rtw_memcmp(psta->cmn.mac_addr, addr, ETH_ALEN)) == _TRUE) { /* if found the matched address */ break; } @@ -909,9 +956,10 @@ u32 rtw_init_bcmc_stainfo(_adapter *padapter) goto exit; } #ifdef CONFIG_BEAMFORMING - psta->txbf_gid = 63; - psta->txbf_paid = 0; + psta->cmn.bf_info.g_id = 63; + psta->cmn.bf_info.p_aid = 0; #endif + ptxservq = &(psta->sta_xmitpriv.be_q); /* @@ -939,14 +987,75 @@ struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter) } +#ifdef CONFIG_AP_MODE +u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta) +{ + struct sta_priv *stapriv = &adapter->stapriv; + u16 aid, i, used_cnt = 0; + + for (i = 0; i < stapriv->max_aid; i++) { + aid = ((i + stapriv->started_aid - 1) % stapriv->max_aid) + 1; + if (stapriv->sta_aid[aid - 1] == NULL) + break; + if (++used_cnt >= stapriv->max_num_sta) + break; + } + + /* check for aid limit and assoc limit */ + if (i >= stapriv->max_aid || used_cnt >= stapriv->max_num_sta) + aid = 0; + + sta->cmn.aid = aid; + if (aid) { + stapriv->sta_aid[aid - 1] = sta; + if (stapriv->rr_aid) + stapriv->started_aid = (aid % stapriv->max_aid) + 1; + } + + return aid; +} + +void dump_aid_status(void *sel, _adapter *adapter) +{ + struct sta_priv *stapriv = &adapter->stapriv; + u8 *aid_bmp; + u16 i, used_cnt = 0; + + aid_bmp = rtw_zmalloc(stapriv->aid_bmp_len); + if (!aid_bmp) + return; + + for (i = 1; i <= stapriv->max_aid; i++) { + if (stapriv->sta_aid[i - 1]) { + aid_bmp[i / 8] |= BIT(i % 8); + ++used_cnt; + } + } + + RTW_PRINT_SEL(sel, "used_cnt:%u/%u\n", used_cnt, stapriv->max_aid); + RTW_MAP_DUMP_SEL(sel, "aid_map:", aid_bmp, stapriv->aid_bmp_len); + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "%-2s %-11s\n", "rr", "started_aid"); + RTW_PRINT_SEL(sel, "%2d %11d\n", stapriv->rr_aid, stapriv->started_aid); + + rtw_mfree(aid_bmp, stapriv->aid_bmp_len); +} +#endif /* CONFIG_AP_MODE */ + #if CONFIG_RTW_MACADDR_ACL -const char *const _acl_mode_str[] = { +const char *const _acl_period_str[RTW_ACL_PERIOD_NUM] = { + "DEV", + "BSS", +}; + +const char *const _acl_mode_str[RTW_ACL_MODE_MAX] = { "DISABLED", "ACCEPT_UNLESS_LISTED", "DENY_UNLESS_LISTED", }; -u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr) +u8 _rtw_access_ctrl(_adapter *adapter, u8 period, const u8 *mac_addr) { u8 res = _TRUE; _irqL irqL; @@ -954,8 +1063,20 @@ u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr) struct rtw_wlan_acl_node *acl_node; u8 match = _FALSE; struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; - _queue *acl_node_q = &acl->acl_node_q; + struct wlan_acl_pool *acl; + _queue *acl_node_q; + + if (period >= RTW_ACL_PERIOD_NUM) { + rtw_warn_on(1); + goto exit; + } + + acl = &stapriv->acl_list[period]; + acl_node_q = &acl->acl_node_q; + + if (acl->mode != RTW_ACL_MODE_ACCEPT_UNLESS_LISTED + && acl->mode != RTW_ACL_MODE_DENY_UNLESS_LISTED) + goto exit; _enter_critical_bh(&(acl_node_q->lock), &irqL); head = get_list_head(acl_node_q); @@ -975,26 +1096,42 @@ u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr) if (acl->mode == RTW_ACL_MODE_ACCEPT_UNLESS_LISTED) res = (match == _TRUE) ? _FALSE : _TRUE; - else if (acl->mode == RTW_ACL_MODE_DENY_UNLESS_LISTED) + else /* RTW_ACL_MODE_DENY_UNLESS_LISTED */ res = (match == _TRUE) ? _TRUE : _FALSE; - else - res = _TRUE; +exit: return res; } -void dump_macaddr_acl(void *sel, _adapter *adapter) +u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr) { - struct sta_priv *stapriv = &adapter->stapriv; - struct wlan_acl_pool *acl = &stapriv->acl_list; int i; - RTW_PRINT_SEL(sel, "mode:%s(%d)\n", acl_mode_str(acl->mode), acl->mode); - RTW_PRINT_SEL(sel, "num:%d/%d\n", acl->num, NUM_ACL); - for (i = 0; i < NUM_ACL; i++) { - if (acl->aclnode[i].valid == _FALSE) - continue; - RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(acl->aclnode[i].addr)); + for (i = 0; i < RTW_ACL_PERIOD_NUM; i++) + if (_rtw_access_ctrl(adapter, i, mac_addr) == _FALSE) + return _FALSE; + + return _TRUE; +} + +void dump_macaddr_acl(void *sel, _adapter *adapter) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct wlan_acl_pool *acl; + int i, j; + + for (j = 0; j < RTW_ACL_PERIOD_NUM; j++) { + RTW_PRINT_SEL(sel, "period:%s(%d)\n", acl_period_str(j), j); + + acl = &stapriv->acl_list[j]; + RTW_PRINT_SEL(sel, "mode:%s(%d)\n", acl_mode_str(acl->mode), acl->mode); + RTW_PRINT_SEL(sel, "num:%d/%d\n", acl->num, NUM_ACL); + for (i = 0; i < NUM_ACL; i++) { + if (acl->aclnode[i].valid == _FALSE) + continue; + RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(acl->aclnode[i].addr)); + } + RTW_PRINT_SEL(sel, "\n"); } } #endif /* CONFIG_RTW_MACADDR_ACL */ diff --git a/core/rtw_tdls.c b/core/rtw_tdls.c index 3bb0e23..4cb3892 100644 --- a/core/rtw_tdls.c +++ b/core/rtw_tdls.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_TDLS_C_ #include @@ -27,7 +22,12 @@ extern unsigned char MCS_rate_2R[16]; extern unsigned char MCS_rate_1R[16]; -extern void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame); + +inline void rtw_tdls_set_link_established(_adapter *adapter, bool en) +{ + adapter->tdlsinfo.link_established = en; + rtw_mi_update_iface_status(&(adapter->mlmepriv), 0); +} void rtw_reset_tdls_info(_adapter *padapter) { @@ -41,7 +41,7 @@ void rtw_reset_tdls_info(_adapter *padapter) else ptdlsinfo->ch_switch_prohibited = _TRUE; - ptdlsinfo->link_established = _FALSE; + rtw_tdls_set_link_established(padapter, _FALSE); ptdlsinfo->sta_cnt = 0; ptdlsinfo->sta_maximum = _FALSE; @@ -62,6 +62,8 @@ void rtw_reset_tdls_info(_adapter *padapter) #ifdef CONFIG_WFD ptdlsinfo->wfd_info = &padapter->wfd_info; #endif + + ptdlsinfo->tdls_sctx = NULL; } int rtw_init_tdls_info(_adapter *padapter) @@ -71,7 +73,6 @@ int rtw_init_tdls_info(_adapter *padapter) rtw_reset_tdls_info(padapter); - ptdlsinfo->tdls_enable = _TRUE; #ifdef CONFIG_TDLS_DRIVER_SETUP ptdlsinfo->driver_setup = _TRUE; #else @@ -94,6 +95,60 @@ void rtw_free_tdls_info(struct tdls_info *ptdlsinfo) } +void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + _irqL irqL; + _list *plist, *phead; + s32 index; + struct sta_info *psta = NULL; + struct sta_info *ptdls_sta[NUM_STA]; + u8 empty_hwaddr[ETH_ALEN] = { 0x00 }; + + _rtw_memset(ptdls_sta, 0x00, sizeof(ptdls_sta)); + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (index = 0; index < NUM_STA; index++) { + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + + plist = get_next(plist); + + if (psta->tdls_sta_state != TDLS_STATE_NONE) + ptdls_sta[index] = psta; + } + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (index = 0; index < NUM_STA; index++) { + if (ptdls_sta[index]) { + struct TDLSoption_param tdls_param; + + psta = ptdls_sta[index]; + + RTW_INFO("Do tear down to "MAC_FMT" by enqueue_cmd = %d\n", MAC_ARG(psta->cmn.mac_addr), enqueue_cmd); + + _rtw_memcpy(&(tdls_param.addr), psta->cmn.mac_addr, ETH_ALEN); + tdls_param.option = TDLS_TEARDOWN_STA_NO_WAIT; + tdls_hdl(padapter, (unsigned char *)&(tdls_param)); + + rtw_tdls_teardown_pre_hdl(padapter, psta); + + if (enqueue_cmd == _TRUE) + rtw_tdls_cmd(padapter, psta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + else + { + tdls_param.option = TDLS_TEARDOWN_STA_LOCALLY_POST; + tdls_hdl(padapter, (unsigned char *)&(tdls_param)); + } + } + } +} + int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len) { u8 tdls_prohibited_bit = 0x40; /* bit(38); TDLS_prohibited */ @@ -122,10 +177,86 @@ int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len) return _FALSE; } +u8 rtw_is_tdls_enabled(_adapter *padapter) +{ + return padapter->registrypriv.en_tdls; +} + +void rtw_set_tdls_enable(_adapter *padapter, u8 enable) +{ + padapter->registrypriv.en_tdls = enable; + RTW_INFO("%s: en_tdls = %d\n", __func__, rtw_is_tdls_enabled(padapter)); +} + +void rtw_enable_tdls_func(_adapter *padapter) +{ + if (rtw_is_tdls_enabled(padapter) == _TRUE) + return; + +#if 0 +#ifdef CONFIG_MCC_MODE + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC) == _TRUE) { + RTW_INFO("[TDLS] MCC is running, can't enable TDLS !\n"); + return; + } +#endif +#endif + rtw_set_tdls_enable(padapter, _TRUE); +} + +void rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd) +{ + if (rtw_is_tdls_enabled(padapter) == _FALSE) + return; + + rtw_free_all_tdls_sta(padapter, enqueue_cmd); + rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR); + rtw_reset_tdls_info(padapter); + + rtw_set_tdls_enable(padapter, _FALSE); +} + +u8 rtw_is_tdls_sta_existed(_adapter *padapter) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + int i = 0; + _irqL irqL; + _list *plist, *phead; + u8 ret = _FALSE; + + if (rtw_is_tdls_enabled(padapter) == _FALSE) + return _FALSE; + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + if (psta->tdls_sta_state != TDLS_STATE_NONE) { + ret = _TRUE; + goto Exit; + } + } + } + +Exit: + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + return ret; +} + u8 rtw_tdls_is_setup_allowed(_adapter *padapter) { struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + if (is_client_associated_to_ap(padapter) == _FALSE) + return _FALSE; + if (ptdlsinfo->ap_prohibited == _TRUE) return _FALSE; @@ -147,7 +278,7 @@ u8 rtw_tdls_is_chsw_allowed(_adapter *padapter) } #endif -int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack) +int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ms) { int ret = _FAIL; struct xmit_frame *pmgntframe; @@ -205,8 +336,8 @@ int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsi pattrib->last_txcmdsz = pattrib->pktlen; - if (wait_ack) - ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + if (wait_ms) + ret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, wait_ms); else { dump_mgntframe(padapter, pmgntframe); ret = _SUCCESS; @@ -226,7 +357,7 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig { int ret; int i = 0; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -234,9 +365,9 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig psta = rtw_get_stainfo(&padapter->stapriv, da); if (psta) { if (power_mode) - rtw_hal_macid_sleep(padapter, psta->mac_id); + rtw_hal_macid_sleep(padapter, psta->cmn.mac_id); else - rtw_hal_macid_wakeup(padapter, psta->mac_id); + rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id); } else { RTW_INFO(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n", FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? "sleep" : "wakeup"); @@ -245,7 +376,7 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig #endif do { - ret = _issue_nulldata_to_TDLS_peer_STA(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE); + ret = _issue_nulldata_to_TDLS_peer_STA(padapter, da, power_mode, wait_ms); i++; @@ -278,37 +409,6 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig return ret; } -void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta) -{ - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - struct sta_priv *pstapriv = &padapter->stapriv; - _irqL irqL; - - /* free peer sta_info */ - _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); - if (ptdlsinfo->sta_cnt != 0) - ptdlsinfo->sta_cnt--; - _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); - /* -2: AP + BC/MC sta, -4: default key */ - if (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) { - ptdlsinfo->sta_maximum = _FALSE; - _rtw_memset(&ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record)); - } - - /* clear cam */ - rtw_clearstakey_cmd(padapter, ptdls_sta, _TRUE); - - if (ptdlsinfo->sta_cnt == 0) { - rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR); - ptdlsinfo->link_established = _FALSE; - } else - RTW_INFO("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt); - - rtw_free_stainfo(padapter, ptdls_sta); - -} - - /* TDLS encryption(if needed) will always be CCMP */ void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta) { @@ -333,11 +433,13 @@ void rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 ptdls_sta->flags |= WLAN_STA_WME; _rtw_memcpy(&ptdls_sta->htpriv.ht_cap, data, sizeof(struct rtw_ieee80211_ht_cap)); - } else + } else { ptdls_sta->flags &= ~WLAN_STA_HT; + return; + } if (ptdls_sta->flags & WLAN_STA_HT) { - if (padapter->registrypriv.ht_enable == _TRUE) { + if (padapter->registrypriv.ht_enable == _TRUE && is_supported_ht(padapter->registrypriv.wireless_mode) ) { ptdls_sta->htpriv.ht_option = _TRUE; ptdls_sta->qos_option = _TRUE; } else { @@ -366,17 +468,17 @@ void rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 ptdls_sta->htpriv.rx_ampdu_min_spacing = max_AMPDU_len | min_MPDU_spacing; /* Check if sta support s Short GI 20M */ - if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)) + if ((phtpriv->sgi_20m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20))) ptdls_sta->htpriv.sgi_20m = _TRUE; /* Check if sta support s Short GI 40M */ - if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) + if ((phtpriv->sgi_40m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_40))) ptdls_sta->htpriv.sgi_40m = _TRUE; /* Bwmode would still followed AP's setting */ if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) { if (padapter->mlmeextpriv.cur_bwmode >= CHANNEL_WIDTH_40) - ptdls_sta->bw_mode = CHANNEL_WIDTH_40; + ptdls_sta->cmn.bw_mode = CHANNEL_WIDTH_40; ptdls_sta->htpriv.ch_offset = padapter->mlmeextpriv.cur_ch_offset; } @@ -415,6 +517,11 @@ u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattr { rtw_ht_use_default_setting(padapter); + if (padapter->registrypriv.wifi_spec == 1) { + padapter->mlmepriv.htpriv.sgi_20m = _FALSE; + padapter->mlmepriv.htpriv.sgi_40m = _FALSE; + } + rtw_restructure_ht_ie(padapter, NULL, pframe, 0, &(pattrib->pktlen), padapter->mlmeextpriv.cur_channel); return pframe + pattrib->pktlen; @@ -424,6 +531,7 @@ u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattr #ifdef CONFIG_80211AC_VHT void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; @@ -444,13 +552,15 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 #else ptdls_sta->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80; #endif - } else + } else { ptdls_sta->flags &= ~WLAN_STA_VHT; + return; + } if (ptdls_sta->flags & WLAN_STA_VHT) { if (REGSTY_IS_11AC_ENABLE(&padapter->registrypriv) - && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent))) + && is_supported_vht(padapter->registrypriv.wireless_mode) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))) ptdls_sta->vhtpriv.vht_option = _TRUE; else ptdls_sta->vhtpriv.vht_option = _FALSE; @@ -475,6 +585,7 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 } ptdls_sta->vhtpriv.stbc_cap = cur_stbc_cap; + #ifdef CONFIG_BEAMFORMING /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) && GET_VHT_CAPABILITY_ELE_SU_BFEE(data)) @@ -487,6 +598,7 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 ptdls_sta->vhtpriv.beamform_cap = cur_beamform_cap; if (cur_beamform_cap) RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap); + #endif /*CONFIG_BEAMFORMING*/ /* B23 B24 B25 Maximum A-MPDU Length Exponent */ ptdls_sta->vhtpriv.ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(data); @@ -498,6 +610,56 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 ptdls_sta->vhtpriv.vht_highest_rate = rtw_get_vht_highest_rate(ptdls_sta->vhtpriv.vht_mcs_map); } +void rtw_tdls_process_vht_operation(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct registry_priv *regsty = adapter_to_regsty(padapter); + u8 operation_bw = 0; + + if (GET_VHT_OPERATION_ELE_CHL_WIDTH(data) >= 1) { + + operation_bw = CHANNEL_WIDTH_80; + + if (hal_is_bw_support(padapter, operation_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, operation_bw) + && (operation_bw <= pmlmeext->cur_bwmode)) + ptdls_sta->cmn.bw_mode = operation_bw; + else + ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode; + } else + ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode; +} + +void rtw_tdls_process_vht_op_mode_notify(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct registry_priv *regsty = adapter_to_regsty(padapter); + u8 target_bw; + u8 target_rxss, current_rxss; + + if (pvhtpriv->vht_option == _FALSE) + return; + + target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(data); + target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(data) + 1); + + if (hal_is_bw_support(padapter, target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw) + && (target_bw <= pmlmeext->cur_bwmode)) + ptdls_sta->cmn.bw_mode = target_bw; + else + ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode; + + current_rxss = rtw_vht_mcsmap_to_nss(ptdls_sta->vhtpriv.vht_mcs_map); + if (target_rxss != current_rxss) { + u8 vht_mcs_map[2] = {}; + + rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, ptdls_sta->vhtpriv.vht_mcs_map); + _rtw_memcpy(ptdls_sta->vhtpriv.vht_mcs_map, vht_mcs_map, 2); + } +} + u8 *rtw_tdls_set_aid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib) { return rtw_set_ie(pframe, EID_AID, 2, (u8 *)&(padapter->mlmepriv.cur_network.aid), &(pattrib->pktlen)); @@ -537,17 +699,18 @@ u8 *rtw_tdls_set_vht_op_mode_notify(_adapter *padapter, u8 *pframe, struct pkt_a #endif -u8 *rtw_tdls_set_sup_ch(struct mlme_ext_priv *pmlmeext, u8 *pframe, struct pkt_attrib *pattrib) +u8 *rtw_tdls_set_sup_ch(_adapter *adapter, u8 *pframe, struct pkt_attrib *pattrib) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); u8 sup_ch[30 * 2] = {0x00}, ch_set_idx = 0, sup_ch_idx = 2; - while (ch_set_idx < pmlmeext->max_chan_nums && pmlmeext->channel_set[ch_set_idx].ChannelNum != 0) { - if (pmlmeext->channel_set[ch_set_idx].ChannelNum <= 14) { + while (ch_set_idx < rfctl->max_chan_nums && rfctl->channel_set[ch_set_idx].ChannelNum != 0) { + if (rfctl->channel_set[ch_set_idx].ChannelNum <= 14) { /* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */ sup_ch[0] = 1; /* First channel number */ - sup_ch[1] = pmlmeext->channel_set[ch_set_idx].ChannelNum; /* Number of channel */ + sup_ch[1] = rfctl->channel_set[ch_set_idx].ChannelNum; /* Number of channel */ } else { - sup_ch[sup_ch_idx++] = pmlmeext->channel_set[ch_set_idx].ChannelNum; + sup_ch[sup_ch_idx++] = rfctl->channel_set[ch_set_idx].ChannelNum; sup_ch[sup_ch_idx++] = 1; } ch_set_idx++; @@ -598,7 +761,9 @@ u8 *rtw_tdls_set_ftie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib _rtw_memcpy(FTIE.Anonce, ANonce, WPA_NONCE_LEN); if (SNonce != NULL) _rtw_memcpy(FTIE.Snonce, SNonce, WPA_NONCE_LEN); - return rtw_set_ie(pframe, _FTIE_ , 82, (u8 *)FTIE.mic_ctrl, &(pattrib->pktlen)); + + return rtw_set_ie(pframe, _FTIE_, TDLS_FTIE_DATA_LEN, + (u8 *)FTIE.data, &(pattrib->pktlen)); } } @@ -717,15 +882,19 @@ u8 *rtw_tdls_set_sup_reg_class(u8 *pframe, struct pkt_attrib *pattrib) return rtw_set_ie(pframe, _SRC_IE_ , sizeof(TDLS_SRC), TDLS_SRC, &(pattrib->pktlen)); } -u8 *rtw_tdls_set_linkid(u8 *pframe, struct pkt_attrib *pattrib, u8 init) +u8 *rtw_tdls_set_linkid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 init) { + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 link_id_addr[18] = {0}; + + _rtw_memcpy(link_id_addr, get_my_bssid(&(pmlmeinfo->network)), 6); + if (init == _TRUE) { - _rtw_memcpy(link_id_addr, pattrib->ra, 6); _rtw_memcpy((link_id_addr + 6), pattrib->src, 6); _rtw_memcpy((link_id_addr + 12), pattrib->dst, 6); } else { - _rtw_memcpy(link_id_addr, pattrib->ra, 6); _rtw_memcpy((link_id_addr + 6), pattrib->dst, 6); _rtw_memcpy((link_id_addr + 12), pattrib->src, 6); } @@ -758,6 +927,20 @@ u8 *rtw_tdls_set_ch_sw(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info * void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable) { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (enable == _TRUE) { +#ifdef CONFIG_TDLS_CH_SW_V2 + pHalData->ch_switch_offload = _TRUE; +#endif + +#ifdef CONFIG_TDLS_CH_SW_BY_DRV + pHalData->ch_switch_offload = _FALSE; +#endif + } + else + pHalData->ch_switch_offload = _FALSE; + if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) != enable) ATOMIC_SET(&padapter->tdlsinfo.chsw_info.chsw_on, enable); @@ -808,10 +991,14 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty ch_sw_time_start = rtw_systime_to_ms(rtw_get_current_time()); - rtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT); - /* set mac_id sleep before channel switch */ - rtw_hal_macid_sleep(padapter, ptdls_sta->mac_id); + rtw_hal_macid_sleep(padapter, ptdls_sta->cmn.mac_id); + +#if defined(CONFIG_TDLS_CH_SW_BY_DRV) || defined(CONFIG_TDLS_CH_SW_V2) + set_channel_bwmode(padapter, channel, channel_offset, bwmode); + ret = _SUCCESS; +#else + rtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT); /* channel switch IOs offload to FW */ if (rtw_hal_ch_sw_oper_offload(padapter, channel, channel_offset, bwmode) == _SUCCESS) { @@ -847,25 +1034,27 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty if (take_care_iqk == _TRUE) rtw_hal_ch_sw_iqk_info_restore(padapter, CH_SW_USE_CASE_TDLS); - ch_sw_time_spent = rtw_systime_to_ms(rtw_get_current_time()) - ch_sw_time_start; - - if (chnl_type == TDLS_CH_SW_OFF_CHNL) { - if ((u32)ch_switch_time / 1000 > ch_sw_time_spent) - wait_time = (u32)ch_switch_time / 1000 - ch_sw_time_spent; - else - wait_time = 0; - - if (wait_time > 0) - rtw_msleep_os(wait_time); - } - ret = _SUCCESS; } else RTW_INFO("[TDLS] chsw oper wait fail !!\n"); } +#endif + + if (ret == _SUCCESS) { + ch_sw_time_spent = rtw_systime_to_ms(rtw_get_current_time()) - ch_sw_time_start; + if (chnl_type == TDLS_CH_SW_OFF_CHNL) { + if ((u32)ch_switch_time / 1000 > ch_sw_time_spent) + wait_time = (u32)ch_switch_time / 1000 - ch_sw_time_spent; + else + wait_time = 0; + + if (wait_time > 0) + rtw_msleep_os(wait_time); + } + } /* set mac_id wakeup after channel switch */ - rtw_hal_macid_wakeup(padapter, ptdls_sta->mac_id); + rtw_hal_macid_wakeup(padapter, ptdls_sta->cmn.mac_id); return ret; } @@ -1027,27 +1216,24 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa RTW_INFO("[TDLS] %s\n", __FUNCTION__); - ptxmgmt->action_code = TDLS_SETUP_REQUEST; if (rtw_tdls_is_setup_allowed(padapter) == _FALSE) goto exit; - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) + if (IS_MCAST(ptxmgmt->peer)) goto exit; - pattrib = &pmgntframe->attrib; - pmgntframe->frame_tag = DATA_FRAMETAG; - pattrib->ether_type = 0x890d; - - _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); - _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); - _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer); + if (ptdlsinfo->sta_maximum == _TRUE) { + if (ptdls_sta == NULL) + goto exit; + else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) + goto exit; + } - update_tdls_attrib(padapter, pattrib); + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; - /* init peer sta_info */ - ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer); if (ptdls_sta == NULL) { ptdls_sta = rtw_alloc_stainfo(pstapriv, ptxmgmt->peer); if (ptdls_sta == NULL) { @@ -1056,10 +1242,21 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa rtw_free_xmitframe(pxmitpriv, pmgntframe); goto exit; } + ptdlsinfo->sta_cnt++; } - if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) - ptdlsinfo->sta_cnt++; + ptxmgmt->action_code = TDLS_SETUP_REQUEST; + + pattrib = &pmgntframe->attrib; + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM) ptdlsinfo->sta_maximum = _TRUE; @@ -1091,25 +1288,19 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa return ret; } -int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack) +int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta, u8 wait_ack) { struct xmit_frame *pmgntframe; struct pkt_attrib *pattrib; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *ptdls_sta = NULL; _irqL irqL; int ret = _FAIL; RTW_INFO("[TDLS] %s\n", __FUNCTION__); ptxmgmt->action_code = TDLS_TEARDOWN; - ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer); - if (ptdls_sta == NULL) { - RTW_INFO("Np tdls_sta for tearing down\n"); - goto exit; - } pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) @@ -1125,7 +1316,12 @@ int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wai _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + + if (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) + _rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN); + else + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); update_tdls_attrib(padapter, pattrib); @@ -1148,9 +1344,6 @@ int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wai ret = _SUCCESS; } - if (rtw_tdls_is_driver_setup(padapter)) - rtw_tdls_cmd(padapter, ptxmgmt->peer, TDLS_TEARDOWN_STA_LOCALLY); - exit: return ret; @@ -1158,15 +1351,28 @@ int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wai int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack) { + struct sta_info *ptdls_sta = NULL; int ret = _FAIL; - ret = _issue_tdls_teardown(padapter, ptxmgmt, wait_ack); + ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), ptxmgmt->peer); + if (ptdls_sta == NULL) { + RTW_INFO("No tdls_sta for tearing down\n"); + goto exit; + } + + ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack); if ((ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) && (ret == _FAIL)) { /* Change status code and send teardown again via AP */ ptxmgmt->status_code = _RSON_TDLS_TEAR_TOOFAR_; - ret = _issue_tdls_teardown(padapter, ptxmgmt, wait_ack); + ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack); + } + + if (rtw_tdls_is_driver_setup(padapter)) { + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptxmgmt->peer, TDLS_TEARDOWN_STA_LOCALLY_POST); } +exit: return ret; } @@ -1368,9 +1574,9 @@ int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *ptdls_sta, pmgntframe->frame_tag = DATA_FRAMETAG; pattrib->ether_type = 0x890d; - _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); update_tdls_attrib(padapter, pattrib); @@ -1413,7 +1619,7 @@ int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdl pmgntframe->frame_tag = DATA_FRAMETAG; pattrib->ether_type = 0x890d; - _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); @@ -1466,9 +1672,9 @@ int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta) pmgntframe->frame_tag = DATA_FRAMETAG; pattrib->ether_type = 0x890d; - _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN); _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); update_tdls_attrib(padapter, pattrib); @@ -1552,10 +1758,13 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib); struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo); u8 empty_addr[ETH_ALEN] = { 0x00 }; - int undecorated_smoothed_pwdb; + int rssi = 0; struct tdls_txmgmt txmgmt; int ret = _SUCCESS; + if (psta) + rssi = psta->cmn.rssi_stat.rssi; + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); /* WFDTDLS: for sigma test, not to setup direct link automatically */ ptdlsinfo->dev_discovered = _TRUE; @@ -1571,11 +1780,11 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) if (ptdlsinfo->sta_maximum == _TRUE && ptdls_sta->alive_count >= 1) { if (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) { _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN); - ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.RxPWDBAll; + ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all; } else { - if (ptdlsinfo->ss_record.RxPWDBAll < pattrib->phy_info.RxPWDBAll) { + if (ptdlsinfo->ss_record.RxPWDBAll < pattrib->phy_info.rx_pwdb_all) { _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN); - ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.RxPWDBAll; + ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all; } } } @@ -1586,7 +1795,7 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) ret = _FAIL; goto exit; } else { - if (pattrib->phy_info.RxPWDBAll > ptdlsinfo->ss_record.RxPWDBAll) { + if (pattrib->phy_info.rx_pwdb_all > ptdlsinfo->ss_record.RxPWDBAll) { _rtw_memcpy(txmgmt.peer, ptdlsinfo->ss_record.macaddr, ETH_ALEN); /* issue_tdls_teardown(padapter, ptdlsinfo->ss_record.macaddr, _FALSE); */ } else { @@ -1596,10 +1805,9 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) } } - rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &undecorated_smoothed_pwdb); - if (pattrib->phy_info.RxPWDBAll + TDLS_SIGNAL_THRESH >= undecorated_smoothed_pwdb) { - RTW_INFO("pattrib->RxPWDBAll=%d, pdmpriv->undecorated_smoothed_pwdb=%d\n", pattrib->phy_info.RxPWDBAll, undecorated_smoothed_pwdb); + if (pattrib->phy_info.rx_pwdb_all + TDLS_SIGNAL_THRESH >= rssi) { + RTW_INFO("pattrib->RxPWDBAll=%d, pdmpriv->undecorated_smoothed_pwdb=%d\n", pattrib->phy_info.rx_pwdb_all, rssi); _rtw_memcpy(txmgmt.peer, psa, ETH_ALEN); issue_tdls_setup_req(padapter, &txmgmt, _FALSE); } @@ -1611,11 +1819,10 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) } -sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) +sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; u8 *psa, *pmyid; - struct sta_info *ptdls_sta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); @@ -1640,7 +1847,13 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); psa = get_sa(ptr); - ptdls_sta = rtw_get_stainfo(pstapriv, psa); + + if (ptdlsinfo->sta_maximum == _TRUE) { + if (ptdls_sta == NULL) + goto exit; + else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) + goto exit; + } pmyid = adapter_mac_addr(padapter); ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN; @@ -1650,11 +1863,15 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; - if (ptdls_sta == NULL) + if (ptdls_sta == NULL) { ptdls_sta = rtw_alloc_stainfo(pstapriv, psa); + if (ptdls_sta == NULL) + goto exit; + + ptdlsinfo->sta_cnt++; + } else { if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) { /* If the direct link is already set up */ @@ -1698,7 +1915,7 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) case _COUNTRY_IE_: break; case _EXT_SUPPORTEDRATES_IE_: - if (supportRateNum <= sizeof(supportRate)) { + if (supportRateNum < sizeof(supportRate)) { _rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length); supportRateNum += pIE->Length; } @@ -1792,8 +2009,6 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) ptdls_sta->bssratelen = supportRateNum; _rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum); - if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) - ptdlsinfo->sta_cnt++; /* -2: AP + BC/MC sta, -4: default key */ if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM) ptdlsinfo->sta_maximum = _TRUE; @@ -1812,8 +2027,10 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) if (txmgmt.status_code == _STATS_SUCCESSFUL_) _set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME); - else - free_tdls_sta(padapter, ptdls_sta); + else { + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + } } exit: @@ -1821,11 +2038,10 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } -int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) +int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct registry_priv *pregistrypriv = &padapter->registrypriv; struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - struct sta_info *ptdls_sta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; _irqL irqL; @@ -1847,13 +2063,6 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); psa = get_sa(ptr); - ptdls_sta = rtw_get_stainfo(pstapriv, psa); - - if (ptdls_sta == NULL) { - RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __func__, MAC_ARG(psa)); - ret = _FAIL; - goto exit; - } ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN; parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len @@ -1862,14 +2071,14 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; _rtw_memcpy(&status_code, ptr + 2, 2); if (status_code != 0) { RTW_INFO("[TDLS] %s status_code = %d, free_tdls_sta\n", __FUNCTION__, status_code); - free_tdls_sta(padapter, ptdls_sta); + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); ret = _FAIL; goto exit; } @@ -1888,7 +2097,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) case _COUNTRY_IE_: break; case _EXT_SUPPORTEDRATES_IE_: - if (supportRateNum <= sizeof(supportRate)) { + if (supportRateNum < sizeof(supportRate)) { _rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length); supportRateNum += pIE->Length; } @@ -1936,7 +2145,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) rtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length); break; case EID_OpModeNotification: - rtw_process_vht_op_mode_notify(padapter, pIE->data, ptdls_sta); + rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length); break; #endif case EID_BSSCoexistence: @@ -1960,35 +2169,31 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length); #endif - if (status_code != _STATS_SUCCESSFUL_) - txmgmt.status_code = status_code; - else { - if (prx_pkt_attrib->encrypt) { - if (verify_ccmp == 1) { - txmgmt.status_code = _STATS_SUCCESSFUL_; - if (rtw_tdls_is_driver_setup(padapter) == _TRUE) { - wpa_tdls_generate_tpk(padapter, ptdls_sta); - if (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) { - RTW_INFO("[TDLS] %s tdls_verify_mic fail, free_tdls_sta\n", __FUNCTION__); - free_tdls_sta(padapter, ptdls_sta); - ret = _FAIL; - goto exit; - } - ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval; + if (prx_pkt_attrib->encrypt) { + if (verify_ccmp == 1) { + txmgmt.status_code = _STATS_SUCCESSFUL_; + if (rtw_tdls_is_driver_setup(padapter) == _TRUE) { + wpa_tdls_generate_tpk(padapter, ptdls_sta); + if (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) { + RTW_INFO("[TDLS] %s tdls_verify_mic fail, free_tdls_sta\n", __FUNCTION__); + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); + ret = _FAIL; + goto exit; } - } else - txmgmt.status_code = _STATS_INVALID_RSNIE_; - + ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval; + } } else - txmgmt.status_code = _STATS_SUCCESSFUL_; - } + txmgmt.status_code = _STATS_INVALID_RSNIE_; + } else + txmgmt.status_code = _STATS_SUCCESSFUL_; if (rtw_tdls_is_driver_setup(padapter) == _TRUE) { _rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN); issue_tdls_setup_cfm(padapter, &txmgmt); if (txmgmt.status_code == _STATS_SUCCESSFUL_) { - ptdlsinfo->link_established = _TRUE; + rtw_tdls_set_link_established(padapter, _TRUE); if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) { ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; @@ -1999,7 +2204,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) if (prx_pkt_attrib->encrypt) rtw_tdls_set_key(padapter, ptdls_sta); - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ESTABLISHED); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED); } } @@ -2012,10 +2217,9 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) } -int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) +int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - struct sta_info *ptdls_sta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; _irqL irqL; @@ -2030,13 +2234,6 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) int ret = _SUCCESS; psa = get_sa(ptr); - ptdls_sta = rtw_get_stainfo(pstapriv, psa); - - if (ptdls_sta == NULL) { - RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __FUNCTION__, MAC_ARG(psa)); - ret = _FAIL; - goto exit; - } ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN; parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len @@ -2045,14 +2242,14 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; _rtw_memcpy(&status_code, ptr + 2, 2); if (status_code != 0) { RTW_INFO("[%s] status_code = %d\n, free_tdls_sta", __FUNCTION__, status_code); - free_tdls_sta(padapter, ptdls_sta); + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); ret = _FAIL; goto exit; } @@ -2084,9 +2281,10 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) #endif #ifdef CONFIG_80211AC_VHT case EID_VHTOperation: + rtw_tdls_process_vht_operation(padapter, ptdls_sta, pIE->data, pIE->Length); break; case EID_OpModeNotification: - rtw_process_vht_op_mode_notify(padapter, pIE->data, ptdls_sta); + rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length); break; #endif case _LINK_ID_IE_: @@ -2104,14 +2302,15 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) /* Verify mic in FTIE MIC field */ if (rtw_tdls_is_driver_setup(padapter) && (tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL)) { - free_tdls_sta(padapter, ptdls_sta); + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); ret = _FAIL; goto exit; } } if (rtw_tdls_is_driver_setup(padapter)) { - ptdlsinfo->link_established = _TRUE; + rtw_tdls_set_link_established(padapter, _TRUE); if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) { ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; @@ -2127,7 +2326,7 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) _set_timer(&ptdls_sta->TPK_timer, ONE_SEC); } - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ESTABLISHED); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED); } exit: @@ -2162,8 +2361,7 @@ int On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; /* Parsing information element */ for (j = FIXED_IE; j < parsing_length;) { @@ -2176,7 +2374,7 @@ int On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame) if (psta_ap == NULL) goto exit; dst = pIE->data + 12; - if (MacAddr_isBcst(dst) == _FALSE && (_rtw_memcmp(adapter_mac_addr(padapter), dst, 6) == _FALSE)) + if (MacAddr_isBcst(dst) == _FALSE && (_rtw_memcmp(adapter_mac_addr(padapter), dst, ETH_ALEN) == _FALSE)) goto exit; break; default: @@ -2194,27 +2392,22 @@ int On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame) } -int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame) +int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { - u8 *psa; u8 *ptr = precv_frame->u.hdr.rx_data; struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *ptdls_sta = NULL; _irqL irqL; u8 reason; reason = *(ptr + prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN + 2); RTW_INFO("[TDLS] %s Reason code(%d)\n", __FUNCTION__, reason); - psa = get_sa(ptr); - - ptdls_sta = rtw_get_stainfo(pstapriv, psa); - if (ptdls_sta != NULL) { - if (rtw_tdls_is_driver_setup(padapter)) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA_LOCALLY); + if (rtw_tdls_is_driver_setup(padapter)) { + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST); } return _SUCCESS; @@ -2235,36 +2428,29 @@ u8 TDLS_check_ch_state(uint state) } #endif -int On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_frame) +int On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->src); u8 *ptr = precv_frame->u.hdr.rx_data; struct tdls_txmgmt txmgmt; ptr += pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN; _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - if (ptdls_sta != NULL) { txmgmt.dialog_token = *(ptr + 2); issue_tdls_peer_traffic_rsp(padapter, ptdls_sta, &txmgmt); - /* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 0, 0, 0); */ - } else { - RTW_INFO("from unknown sta:"MAC_FMT"\n", MAC_ARG(pattrib->src)); - return _FAIL; - } + /* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0); */ return _SUCCESS; } /* We process buffered data for 1. U-APSD, 2. ch. switch, 3. U-APSD + ch. switch here */ -int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame) +int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src); u8 wmmps_ac = 0; /* u8 state=TDLS_check_ch_state(ptdls_sta->tdls_sta_state); */ int i; @@ -2326,20 +2512,17 @@ int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame) } #ifdef CONFIG_TDLS_CH_SW -sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame) +sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; - struct sta_info *ptdls_sta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; - u8 *psa; sint parsing_length; PNDIS_802_11_VARIABLE_IEs pIE; u8 FIXED_IE = 4; u16 j; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct tdls_txmgmt txmgmt; u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000; u8 take_care_iqk; @@ -2349,15 +2532,6 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame) return _FAIL; } - _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - psa = get_sa(ptr); - ptdls_sta = rtw_get_stainfo(pstapriv, psa); - - if (ptdls_sta == NULL) { - RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __func__, MAC_ARG(psa)); - return _FAIL; - } - ptdls_sta->ch_switch_time = switch_time; ptdls_sta->ch_switch_timeout = switch_timeout; @@ -2368,8 +2542,7 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; pchsw_info->off_ch_num = *(ptr + 2); @@ -2424,7 +2597,7 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame) central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset); if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) < 0) { if (!(pchsw_info->ch_sw_state & TDLS_CH_SWITCH_PREPARE_STATE)) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_PREPARE); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE); return _FAIL; } @@ -2434,29 +2607,23 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame) if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) _cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer); - /* Todo: check status */ - txmgmt.status_code = 0; - _rtw_memcpy(txmgmt.peer, psa, ETH_ALEN); - if (_rtw_memcmp(pchsw_info->addr, zaddr, ETH_ALEN) == _TRUE) - _rtw_memcpy(pchsw_info->addr, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(pchsw_info->addr, ptdls_sta->cmn.mac_addr, ETH_ALEN); if (ATOMIC_READ(&pchsw_info->chsw_on) == _FALSE) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_RESP); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_RESP); return _SUCCESS; } -sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame) +sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta) { struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; - struct sta_info *ptdls_sta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; u8 *ptr = precv_frame->u.hdr.rx_data; struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; - u8 *psa; sint parsing_length; PNDIS_802_11_VARIABLE_IEs pIE; u8 FIXED_IE = 4; @@ -2469,20 +2636,12 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame) return _SUCCESS; } - psa = get_sa(ptr); - ptdls_sta = rtw_get_stainfo(pstapriv, psa); - - if (ptdls_sta == NULL) { - RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __func__, MAC_ARG(psa)); - return _FAIL; - } - /* If we receive Unsolicited TDLS Channel Switch Response when channel switch is running, */ /* we will go back to base channel and terminate this channel switch procedure */ if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) { if (pmlmeext->cur_channel != rtw_get_oper_ch(padapter)) { RTW_INFO("[TDLS] Rx unsolicited channel switch response\n"); - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL); goto exit; } } @@ -2494,15 +2653,14 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame) - prx_pkt_attrib->icv_len - LLC_HEADER_SIZE - ETH_TYPE_LEN - - PAYLOAD_TYPE_LEN - - FIXED_IE; + - PAYLOAD_TYPE_LEN; _rtw_memcpy(&status_code, ptr + 2, 2); if (status_code != 0) { RTW_INFO("[TDLS] %s status_code:%d\n", __func__, status_code); pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE); - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END); ret = _FAIL; goto exit; } @@ -2533,7 +2691,7 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame) if ((pmlmeext->cur_channel == rtw_get_oper_ch(padapter)) && (pchsw_info->ch_sw_state & TDLS_WAIT_CH_RSP_STATE)) { if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_OFF_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL); } exit: @@ -2548,6 +2706,7 @@ void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen) struct wifi_display_info *pwfd_info = padapter->tdlsinfo.wfd_info; u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; u32 wfdielen = 0; + u16 v16 = 0; if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) return; @@ -2579,8 +2738,9 @@ void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen) /* Value1: */ /* WFD device information */ /* available for WFD session + Preferred TDLS + WSD ( WFD Service Discovery ) */ - RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL - | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD); + v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL + | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, v16); wfdielen += 2; /* Value2: */ @@ -2632,13 +2792,12 @@ void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen) } #endif /* CONFIG_WFD */ -void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *ptdls_sta = rtw_get_stainfo((&padapter->stapriv) , pattrib->dst); - int i = 0 ; u32 time; u8 *pframe_head; @@ -2660,7 +2819,7 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr pframe = rtw_tdls_set_capability(padapter, pframe, pattrib); pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib); - pframe = rtw_tdls_set_sup_ch(&(padapter->mlmeextpriv), pframe, pattrib); + pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib); pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib); if (pattrib->encrypt) @@ -2686,7 +2845,7 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib); - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE)) pframe = rtw_tdls_set_qos_cap(pframe, pattrib); @@ -2694,8 +2853,8 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr #ifdef CONFIG_80211AC_VHT if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14) && REGSTY_IS_11AC_ENABLE(pregistrypriv) - && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent)) + && is_supported_vht(pregistrypriv->wireless_mode) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) ) { pframe = rtw_tdls_set_aid(padapter, pframe, pattrib); pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib); @@ -2709,23 +2868,18 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr } -void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *ptdls_sta; u8 k; /* for random ANonce */ u8 *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL; u32 time; u8 *pframe_head; - ptdls_sta = rtw_get_stainfo(&(padapter->stapriv) , pattrib->dst); - - if (ptdls_sta == NULL) - RTW_INFO("[%s] %d ptdls_sta is NULL\n", __FUNCTION__, __LINE__); - - if (pattrib->encrypt && ptdls_sta != NULL) { + if (pattrib->encrypt) { for (k = 0; k < 8; k++) { time = rtw_get_current_time(); _rtw_memcpy(&ptdls_sta->ANonce[4 * k], (u8 *)&time, 4); @@ -2747,7 +2901,7 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); pframe = rtw_tdls_set_capability(padapter, pframe, pattrib); pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib); - pframe = rtw_tdls_set_sup_ch(&(padapter->mlmeextpriv), pframe, pattrib); + pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib); pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib); if (pattrib->encrypt) { @@ -2782,7 +2936,7 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib); plinkid_ie = pframe; - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); /* Fill FTIE mic */ if (pattrib->encrypt && rtw_tdls_is_driver_setup(padapter) == _TRUE) @@ -2794,8 +2948,8 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr #ifdef CONFIG_80211AC_VHT if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14) && REGSTY_IS_11AC_ENABLE(pregistrypriv) - && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent)) + && is_supported_vht(pregistrypriv->wireless_mode) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) ) { pframe = rtw_tdls_set_aid(padapter, pframe, pattrib); pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib); @@ -2810,13 +2964,13 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr } -void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *ptdls_sta = rtw_get_stainfo((&padapter->stapriv) , pattrib->dst); unsigned int ie_len; unsigned char *p; @@ -2859,7 +3013,7 @@ void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitfr /* HT operation; todo */ plinkid_ie = pframe; - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE)) wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic); @@ -2871,8 +3025,8 @@ void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitfr if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (ptdls_sta->vhtpriv.vht_option == _TRUE) && (pmlmeext->cur_channel > 14) && REGSTY_IS_11AC_ENABLE(pregistrypriv) - && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) - && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent)) + && is_supported_vht(pregistrypriv->wireless_mode) + && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)) ) { pframe = rtw_tdls_set_vht_operation(padapter, pframe, pattrib, pmlmeext->cur_channel); pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode); @@ -2880,10 +3034,9 @@ void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitfr #endif } -void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *ptdls_sta = rtw_get_stainfo(&(padapter->stapriv) , pattrib->dst); u8 *pftie = NULL, *pftie_mic = NULL, *plinkid_ie = NULL; pframe = rtw_tdls_set_payload_type(pframe, pattrib); @@ -2903,9 +3056,9 @@ void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitfra plinkid_ie = pframe; if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE)) wpa_tdls_teardown_ftie_mic(ptdls_sta->tpk.kck, plinkid_ie, ptxmgmt->status_code, 1, 4, pftie, pftie_mic); @@ -2919,7 +3072,7 @@ void rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitfram pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); } @@ -2940,7 +3093,7 @@ void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfram pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib); - pframe = rtw_tdls_set_sup_ch(pmlmeext, pframe, pattrib); + pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib); if (privacy) pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, NULL); @@ -2958,17 +3111,16 @@ void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfram #endif pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib); - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); } -void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct pkt_attrib *pattrib = &pxmitframe->attrib; u8 AC_queue = 0; - struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst); pframe = rtw_tdls_set_payload_type(pframe, pattrib); pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); @@ -2976,9 +3128,9 @@ void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_ pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); /* PTI control */ /* PU buffer status */ @@ -2994,11 +3146,10 @@ void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_ } -void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst); pframe = rtw_tdls_set_payload_type(pframe, pattrib); pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); @@ -3006,18 +3157,17 @@ void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame * pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); } #ifdef CONFIG_TDLS_CH_SW -void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; struct pkt_attrib *pattrib = &pxmitframe->attrib; struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000; ptdls_sta->ch_switch_time = switch_time; @@ -3041,20 +3191,19 @@ void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxm } if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta); } -void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta) { struct pkt_attrib *pattrib = &pxmitframe->attrib; struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); pframe = rtw_tdls_set_payload_type(pframe, pattrib); pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); @@ -3062,9 +3211,9 @@ void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxm pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt); if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE); else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) - pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE); pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta); } @@ -3143,9 +3292,10 @@ void _tdls_tpk_timer_hdl(void *FunctionContext) /* TPK_timer expired in a second */ /* Retry timer should set at least 301 sec. */ if (ptdls_sta->TPK_count >= (ptdls_sta->TDLS_PeerKey_Lifetime - 3)) { - RTW_INFO("[TDLS] %s, Re-Setup TDLS link with "MAC_FMT" since TPK lifetime expires!\n", __FUNCTION__, MAC_ARG(ptdls_sta->hwaddr)); + RTW_INFO("[TDLS] %s, Re-Setup TDLS link with "MAC_FMT" since TPK lifetime expires!\n", + __FUNCTION__, MAC_ARG(ptdls_sta->cmn.mac_addr)); ptdls_sta->TPK_count = 0; - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); issue_tdls_setup_req(ptdls_sta->padapter, &txmgmt, _FALSE); } @@ -3159,7 +3309,7 @@ void _tdls_ch_switch_timer_hdl(void *FunctionContext) _adapter *padapter = ptdls_sta->padapter; struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); RTW_INFO("[TDLS] %s, can't get traffic from op_ch:%d\n", __func__, rtw_get_oper_ch(padapter)); } @@ -3191,7 +3341,7 @@ void _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext) _adapter *padapter = ptdls_sta->padapter; struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END); RTW_INFO("[TDLS] %s, does not receive ch sw req\n", __func__); } @@ -3200,37 +3350,41 @@ void _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext) void _tdls_handshake_timer_hdl(void *FunctionContext) { struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; - _adapter *padapter = ptdls_sta->padapter; + _adapter *padapter = NULL; struct tdls_txmgmt txmgmt; _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; if (ptdls_sta != NULL) { + padapter = ptdls_sta->padapter; + RTW_INFO("[TDLS] Handshake time out\n"); if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA); else - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA_LOCALLY); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY); } } void _tdls_pti_timer_hdl(void *FunctionContext) { struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; - _adapter *padapter = ptdls_sta->padapter; + _adapter *padapter = NULL; struct tdls_txmgmt txmgmt; _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN); txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_; if (ptdls_sta != NULL) { + padapter = ptdls_sta->padapter; + if (ptdls_sta->tdls_sta_state & TDLS_WAIT_PTR_STATE) { RTW_INFO("[TDLS] Doesn't receive PTR from peer dev:"MAC_FMT"; " - "Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->hwaddr)); - issue_tdls_teardown(padapter, &txmgmt, _FALSE); + "Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->cmn.mac_addr)); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA); } } } @@ -3249,7 +3403,7 @@ void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta) rtw_init_timer(&psta->pti_timer, padapter, _tdls_pti_timer_hdl, psta); } -void rtw_free_tdls_timer(struct sta_info *psta) +void rtw_cancel_tdls_timer(struct sta_info *psta) { _cancel_timer_ex(&psta->TPK_timer); #ifdef CONFIG_TDLS_CH_SW @@ -3262,35 +3416,53 @@ void rtw_free_tdls_timer(struct sta_info *psta) _cancel_timer_ex(&psta->pti_timer); } -u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta) +void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta) { - unsigned char sta_band = 0; - unsigned int tx_ra_bitmap = 0; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct sta_priv *pstapriv = &padapter->stapriv; + _irqL irqL; - rtw_hal_update_sta_rate_mask(padapter, psta); - tx_ra_bitmap = psta->ra_mask; + rtw_cancel_tdls_timer(psta); - if (pcur_network->Configuration.DSConfig > 14) { - if (tx_ra_bitmap & 0xffff000) - sta_band |= WIRELESS_11_5N | WIRELESS_11A; - else - sta_band |= WIRELESS_11A; - } else { - if (tx_ra_bitmap & 0xffff000) - sta_band |= WIRELESS_11_24N | WIRELESS_11G | WIRELESS_11B; - else if (tx_ra_bitmap & 0xff0) - sta_band |= WIRELESS_11G | WIRELESS_11B; - else - sta_band |= WIRELESS_11B; + _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + if (ptdlsinfo->sta_cnt != 0) + ptdlsinfo->sta_cnt--; + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + if (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) { + ptdlsinfo->sta_maximum = _FALSE; + _rtw_memset(&ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record)); } - psta->wireless_mode = sta_band; + if (ptdlsinfo->sta_cnt == 0) + rtw_tdls_set_link_established(padapter, _FALSE); + else + RTW_INFO("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt); +} + +void rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + + /* Clear cam */ + rtw_clearstakey_cmd(padapter, psta, enqueue_cmd); + + /* Update sta media status */ + if (enqueue_cmd) + rtw_sta_media_status_rpt_cmd(padapter, psta, 0); + else + rtw_sta_media_status_rpt(padapter, psta, 0); + + /* Set RCR if necessary */ + if (ptdlsinfo->sta_cnt == 0) { + if (enqueue_cmd) + rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR); + else + rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK); + } - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); - tx_ra_bitmap |= ((psta->raid << 28) & 0xf0000000); - return tx_ra_bitmap; + /* Free tdls sta info */ + rtw_free_stainfo(padapter, psta); } int rtw_tdls_is_driver_setup(_adapter *padapter) diff --git a/core/rtw_vht.c b/core/rtw_vht.c index fbb26f8..9a7608c 100644 --- a/core/rtw_vht.c +++ b/core/rtw_vht.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,18 +11,100 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_VHT_C #include #include #ifdef CONFIG_80211AC_VHT +const u16 _vht_max_mpdu_len[] = { + 3895, + 7991, + 11454, + 0, +}; + +const u8 _vht_sup_ch_width_set_to_bw_cap[] = { + BW_CAP_80M, + BW_CAP_80M | BW_CAP_160M, + BW_CAP_80M | BW_CAP_160M | BW_CAP_80_80M, + 0, +}; + +const char *const _vht_sup_ch_width_set_str[] = { + "80MHz", + "160MHz", + "160MHz & 80+80MHz", + "BW-RSVD", +}; + +void dump_vht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len) +{ + if (buf_len != VHT_CAP_IE_LEN) { + RTW_PRINT_SEL(sel, "Invalid VHT capability IE len:%d != %d\n", buf_len, VHT_CAP_IE_LEN); + return; + } + + RTW_PRINT_SEL(sel, "cap_info:%02x %02x %02x %02x: MAX_MPDU_LEN:%u %s%s%s%s%s RX-STBC:%u MAX_AMPDU_LEN:%u\n" + , *(buf), *(buf + 1), *(buf + 2), *(buf + 3) + , vht_max_mpdu_len(GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(buf)) + , vht_sup_ch_width_set_str(GET_VHT_CAPABILITY_ELE_CHL_WIDTH(buf)) + , GET_VHT_CAPABILITY_ELE_RX_LDPC(buf) ? " RX-LDPC" : "" + , GET_VHT_CAPABILITY_ELE_SHORT_GI80M(buf) ? " SGI-80" : "" + , GET_VHT_CAPABILITY_ELE_SHORT_GI160M(buf) ? " SGI-160" : "" + , GET_VHT_CAPABILITY_ELE_TX_STBC(buf) ? " TX-STBC" : "" + , GET_VHT_CAPABILITY_ELE_RX_STBC(buf) + , VHT_MAX_AMPDU_LEN(GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(buf)) + ); +} + +void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len) +{ + const u8 *vht_cap_ie; + sint vht_cap_ielen; + + vht_cap_ie = rtw_get_ie(ie, WLAN_EID_VHT_CAPABILITY, &vht_cap_ielen, ie_len); + if (!ie || vht_cap_ie != ie) + return; + + dump_vht_cap_ie_content(sel, vht_cap_ie + 2, vht_cap_ielen); +} + +const char *const _vht_op_ch_width_str[] = { + "20 or 40MHz", + "80MHz", + "160MHz", + "80+80MHz", + "BW-RSVD", +}; + +void dump_vht_op_ie_content(void *sel, const u8 *buf, u32 buf_len) +{ + if (buf_len != VHT_OP_IE_LEN) { + RTW_PRINT_SEL(sel, "Invalid VHT operation IE len:%d != %d\n", buf_len, VHT_OP_IE_LEN); + return; + } + + RTW_PRINT_SEL(sel, "%s, ch0:%u, ch1:%u\n" + , vht_op_ch_width_str(GET_VHT_OPERATION_ELE_CHL_WIDTH(buf)) + , GET_VHT_OPERATION_ELE_CENTER_FREQ1(buf) + , GET_VHT_OPERATION_ELE_CENTER_FREQ2(buf) + ); +} + +void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len) +{ + const u8 *vht_op_ie; + sint vht_op_ielen; + + vht_op_ie = rtw_get_ie(ie, WLAN_EID_VHT_OPERATION, &vht_op_ielen, ie_len); + if (!ie || vht_op_ie != ie) + return; + + dump_vht_op_ie_content(sel, vht_op_ie + 2, vht_op_ielen); +} + /* 20/40/80, ShortGI, MCS Rate */ const u16 VHT_MCS_DATA_RATE[3][2][30] = { { { @@ -183,43 +265,53 @@ void rtw_vht_use_default_setting(_adapter *padapter) /* Beamforming setting */ CLEAR_FLAGS(pvhtpriv->beamform_cap); #ifdef CONFIG_BEAMFORMING - rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer); - rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee); - mu_bfer = _FALSE; - mu_bfee = _FALSE; - rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer); - rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee); - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) { +#ifdef RTW_BEAMFORMING_VERSION_2 + /* only enable beamforming in STA client mode */ + if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter) + && !MLME_IS_ADHOC(padapter) + && !MLME_IS_MESH(padapter)) +#endif + { + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, + (u8 *)&bHwSupportBeamformer); + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, + (u8 *)&bHwSupportBeamformee); + mu_bfer = _FALSE; + mu_bfee = _FALSE; + rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer); + rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee); + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) { #ifdef CONFIG_CONCURRENT_MODE - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n"); + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2)) + && (_TRUE == mu_bfer)) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE); + RTW_INFO("[VHT] Support MU-MIMO AP\n"); + } + } else + RTW_INFO("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n"); +#else SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); - RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n"); + RTW_INFO("[VHT] Support Beamformer\n"); if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2)) - && (_TRUE == mu_bfer)) { + && (_TRUE == mu_bfer) + && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE); RTW_INFO("[VHT] Support MU-MIMO AP\n"); } - } else - RTW_INFO("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n"); -#else - SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); - RTW_INFO("[VHT] Support Beamformer\n"); - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2)) - && (_TRUE == mu_bfer) - && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { - SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE); - RTW_INFO("[VHT] Support MU-MIMO AP\n"); - } #endif - } - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) { - SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); - RTW_INFO("[VHT] Support Beamformee\n"); - if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3)) - && (_TRUE == mu_bfee) - && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) { - SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE); - RTW_INFO("[VHT] Support MU-MIMO STA\n"); + } + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); + RTW_INFO("[VHT] Support Beamformee\n"); + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3)) + && (_TRUE == mu_bfee) + && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE); + RTW_INFO("[VHT] Support MU-MIMO STA\n"); + } } } #endif /* CONFIG_BEAMFORMING */ @@ -266,6 +358,38 @@ u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss) return bitmap; } +#ifdef CONFIG_BEAMFORMING +void update_sta_vht_info_apmode_bf_cap(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv; + struct vht_priv *pvhtpriv_sta = &psta->vhtpriv; + u16 cur_beamform_cap = 0; + + /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */ + if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) && + GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); + /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/ + SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8); + } + + /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */ + if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) && + GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/ + SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12); + } + + if (cur_beamform_cap) + RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->cmn.aid, cur_beamform_cap); + + pvhtpriv_sta->beamform_cap = cur_beamform_cap; + psta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap; +} +#endif + void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta) { struct sta_info *psta = (struct sta_info *)sta; @@ -273,35 +397,52 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv; struct vht_priv *pvhtpriv_sta = &psta->vhtpriv; - struct ht_priv *phtpriv_sta = &psta->htpriv; - u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, bw_mode = 0; - u16 cur_beamform_cap = 0; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0; + s8 bw_mode = -1; u8 *pcap_mcs; if (pvhtpriv_sta->vht_option == _FALSE) return; - bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify); + if (pvhtpriv_sta->op_present) { + switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(pvhtpriv_sta->vht_op)) { + case 1: /* 80MHz */ + case 2: /* 160MHz */ + case 3: /* 80+80 */ + bw_mode = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */ + break; + } + } - /* if (bw_mode > psta->bw_mode) */ - psta->bw_mode = bw_mode; + if (pvhtpriv_sta->notify_present) + bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify); + else if (MLME_IS_AP(padapter)) { + /* for VHT client without Operating Mode Notify IE; minimal 80MHz */ + if (bw_mode < CHANNEL_WIDTH_80) + bw_mode = CHANNEL_WIDTH_80; + } + + if (bw_mode != -1) + psta->cmn.bw_mode = bw_mode; /* update bw_mode only if get value from VHT IEs */ + + psta->cmn.ra_info.is_vht_enable = _TRUE; /* B4 Rx LDPC */ if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) && GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) { SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX)); - RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->aid, cur_ldpc_cap); + RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->cmn.aid, cur_ldpc_cap); } pvhtpriv_sta->ldpc_cap = cur_ldpc_cap; - if (psta->bw_mode > pmlmeext->cur_bwmode) - psta->bw_mode = pmlmeext->cur_bwmode; + if (psta->cmn.bw_mode > pmlmeext->cur_bwmode) + psta->cmn.bw_mode = pmlmeext->cur_bwmode; - if (psta->bw_mode == CHANNEL_WIDTH_80) { + if (psta->cmn.bw_mode == CHANNEL_WIDTH_80) { /* B5 Short GI for 80 MHz */ pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE; /* RTW_INFO("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m); */ - } else if (psta->bw_mode >= CHANNEL_WIDTH_160) { + } else if (psta->cmn.bw_mode >= CHANNEL_WIDTH_160) { /* B5 Short GI for 80 MHz */ pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE; /* RTW_INFO("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m); */ @@ -311,29 +452,12 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta) if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) && GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) { SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX)); - RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->aid, cur_stbc_cap); + RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->cmn.aid, cur_stbc_cap); } pvhtpriv_sta->stbc_cap = cur_stbc_cap; #ifdef CONFIG_BEAMFORMING - /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */ - if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) && - GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); - /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/ - SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8); - } - - /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */ - if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) && - GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) { - SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); - /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/ - SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12); - } - pvhtpriv_sta->beamform_cap = cur_beamform_cap; - if (cur_beamform_cap) - RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->aid, cur_beamform_cap); + update_sta_vht_info_apmode_bf_cap(padapter, psta); #endif /* B23 B24 B25 Maximum A-MPDU Length Exponent */ @@ -358,6 +482,83 @@ void update_hw_vht_param(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len)); } +#ifdef ROKU_PRIVATE +u8 VHT_get_ss_from_map(u8 *vht_mcs_map) +{ + u8 i, j; + u8 ss = 0; + + for (i = 0; i < 2; i++) { + if (vht_mcs_map[i] != 0xff) { + for (j = 0; j < 8; j += 2) { + if (((vht_mcs_map[i] >> j) & 0x03) == 0x03) + break; + ss++; + } + } + + } + +return ss; +} + +void VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv_infra_ap *pvhtpriv = &pmlmepriv->vhtpriv_infra_ap; + u8 cur_stbc_cap_infra_ap = 0; + u16 cur_beamform_cap_infra_ap = 0; + u8 *pcap_mcs; + u8 *pcap_mcs_tx; + u8 Rx_ss = 0, Tx_ss = 0; + + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (pIE == NULL) + return; + + pmlmeinfo->ht_vht_received |= BIT(1); + + pvhtpriv->ldpc_cap_infra_ap = GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data); + + if (GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data)) + SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_RX); + if (GET_VHT_CAPABILITY_ELE_TX_STBC(pIE->data)) + SET_FLAG(cur_stbc_cap_infra_ap, STBC_VHT_ENABLE_TX); + pvhtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap; + + /*store ap info for channel bandwidth*/ + pvhtpriv->channel_width_infra_ap = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(pIE->data); + + /*check B11: SU Beamformer Capable and B12: SU Beamformee B19: MU Beamformer B20:MU Beamformee*/ + if (GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) + SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + if (GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) + SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); + if (GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data)) + SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE); + if (GET_VHT_CAPABILITY_ELE_MU_BFEE(pIE->data)) + SET_FLAG(cur_beamform_cap_infra_ap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE); + pvhtpriv->beamform_cap_infra_ap = cur_beamform_cap_infra_ap; + + /*store information about vht_mcs_set*/ + pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data); + pcap_mcs_tx = GET_VHT_CAPABILITY_ELE_TX_MCS(pIE->data); + _rtw_memcpy(pvhtpriv->vht_mcs_map_infra_ap, pcap_mcs, 2); + _rtw_memcpy(pvhtpriv->vht_mcs_map_tx_infra_ap, pcap_mcs_tx, 2); + + Rx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_infra_ap); + Tx_ss = VHT_get_ss_from_map(pvhtpriv->vht_mcs_map_tx_infra_ap); + if (Rx_ss >= Tx_ss) { + pvhtpriv->number_of_streams_infra_ap = Rx_ss; + } else{ + pvhtpriv->number_of_streams_infra_ap = Tx_ss; + } + +} +#endif /* ROKU_PRIVATE */ + void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) { struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); @@ -489,24 +690,28 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta) struct sta_info *psta = (struct sta_info *)sta; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct registry_priv *regsty = adapter_to_regsty(padapter); u8 target_bw; u8 target_rxss, current_rxss; u8 update_ra = _FALSE; + u8 tx_nss = 0, rf_type = RF_1T1R; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); if (pvhtpriv->vht_option == _FALSE) return; target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe); - target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1); - if (target_bw != psta->bw_mode) { + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + target_rxss = rtw_min(tx_nss, (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1)); + + if (target_bw != psta->cmn.bw_mode) { if (hal_is_bw_support(padapter, target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw) ) { update_ra = _TRUE; - psta->bw_mode = target_bw; + psta->cmn.bw_mode = target_bw; } } @@ -519,7 +724,7 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta) rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map); _rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2); - rtw_hal_update_sta_rate_mask(padapter, psta); + rtw_hal_update_sta_ra_info(padapter, psta); } if (update_ra) @@ -588,7 +793,7 @@ u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw) u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) { - u8 bw, rf_type, rf_num, rx_stbc_nss = 0; + u8 bw, rf_num, rx_stbc_nss = 0; u16 HighestRate; u8 *pcap, *pcap_mcs; u32 len = 0; @@ -596,6 +801,8 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); pcap = pvhtpriv->vht_cap; _rtw_memset(pcap, 0, 32); @@ -604,19 +811,19 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); - RTW_DBG("%s, line%d, Available RX buf size = %d bytes\n.", __FUNCTION__, __LINE__, max_recvbuf_sz - rx_packet_offset); + RTW_DBG("%s, line%d, Available RX buf size = %d bytes\n", __FUNCTION__, __LINE__, max_recvbuf_sz - rx_packet_offset); if ((max_recvbuf_sz - rx_packet_offset) >= 11454) { SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 2); - RTW_INFO("%s, line%d, Set MAX MPDU len = 11454 bytes\n.", __FUNCTION__, __LINE__); + RTW_INFO("%s, line%d, Set MAX MPDU len = 11454 bytes\n", __FUNCTION__, __LINE__); } else if ((max_recvbuf_sz - rx_packet_offset) >= 7991) { SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 1); - RTW_INFO("%s, line%d, Set MAX MPDU len = 7991 bytes\n.", __FUNCTION__, __LINE__); + RTW_INFO("%s, line%d, Set MAX MPDU len = 7991 bytes\n", __FUNCTION__, __LINE__); } else if ((max_recvbuf_sz - rx_packet_offset) >= 3895) { SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 0); - RTW_INFO("%s, line%d, Set MAX MPDU len = 3895 bytes\n.", __FUNCTION__, __LINE__); + RTW_INFO("%s, line%d, Set MAX MPDU len = 3895 bytes\n", __FUNCTION__, __LINE__); } else - RTW_ERR("%s, line%d, Error!! Available RX buf size < 3895 bytes\n.", __FUNCTION__, __LINE__); + RTW_ERR("%s, line%d, Error!! Available RX buf size < 3895 bytes\n", __FUNCTION__, __LINE__); /* B2 B3 Supported Channel Width Set */ if (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) { @@ -654,7 +861,7 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss); RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", rx_stbc_nss); } - + #ifdef CONFIG_BEAMFORMING /* B11 SU Beamformer Capable */ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1); @@ -673,8 +880,16 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) { SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1); RTW_INFO("[VHT] Declare supporting SU Bfee\n"); - /* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */ + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); + + /* IOT action suggested by Yu Chen 2017/3/3 */ +#ifdef CONFIG_80211AC_VHT + if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) && + !pvhtpriv->ap_is_mu_bfer) + rf_num = (rf_num >= 2 ? 2 : rf_num); +#endif + /* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */ SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num); /* B20 SU Beamformee Capable */ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) { @@ -682,6 +897,7 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) RTW_INFO("[VHT] Declare supporting MU Bfee\n"); } } + #endif/*CONFIG_BEAMFORMING*/ /* B21 VHT TXOP PS */ SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0); @@ -717,61 +933,109 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len) { - u32 ielen = 0, out_len = 0; - u8 cap_len = 0, notify_len = 0, notify_bw = 0, operation_bw = 0, supported_chnl_width = 0; - u8 *p, *pframe; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + RT_CHANNEL_INFO *chset = rfctl->channel_set; + u32 ielen; + u8 max_bw; + u8 oper_ch, oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + u8 *out_vht_op_ie, *ht_op_ie, *vht_cap_ie, *vht_op_ie; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; rtw_vht_use_default_setting(padapter); - p = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12); - if (p && ielen > 0) { - supported_chnl_width = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2); + ht_op_ie = rtw_get_ie(in_ie + 12, WLAN_EID_HT_OPERATION, &ielen, in_len - 12); + if (!ht_op_ie || ielen != HT_OP_IE_LEN) + goto exit; + vht_cap_ie = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12); + if (!vht_cap_ie || ielen != VHT_CAP_IE_LEN) + goto exit; + vht_op_ie = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12); + if (!vht_op_ie || ielen != VHT_OP_IE_LEN) + goto exit; - /* VHT Capabilities element */ - cap_len = rtw_build_vht_cap_ie(padapter, out_ie + *pout_len); - *pout_len += cap_len; + /* VHT Capabilities element */ + *pout_len += rtw_build_vht_cap_ie(padapter, out_ie + *pout_len); - /* Get HT BW */ - p = rtw_get_ie(in_ie + 12, _HT_EXTRA_INFO_IE_, &ielen, in_len - 12); - if (p && ielen > 0) { - struct HT_info_element *pht_info = (struct HT_info_element *)(p + 2); - if (pht_info->infos[0] & BIT(2)) - operation_bw = CHANNEL_WIDTH_40; - else - operation_bw = CHANNEL_WIDTH_20; - } - /* VHT Operation element */ - p = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12); - if (p && ielen > 0) { - out_len = *pout_len; - if (GET_VHT_OPERATION_ELE_CHL_WIDTH(p + 2) >= 1) { - if (supported_chnl_width == 2) - operation_bw = CHANNEL_WIDTH_80_80; - else if (supported_chnl_width == 1) - operation_bw = CHANNEL_WIDTH_160; - else - operation_bw = CHANNEL_WIDTH_80; + /* VHT Operation element */ + out_vht_op_ie = out_ie + *pout_len; + rtw_set_ie(out_vht_op_ie, EID_VHTOperation, VHT_OP_IE_LEN, vht_op_ie + 2 , pout_len); + + /* get primary channel from HT_OP_IE */ + oper_ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2); + + /* find the largest bw supported by both registry and hal */ + max_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv)); + + if (max_bw >= CHANNEL_WIDTH_40) { + /* get bw offset form HT_OP_IE */ + if (GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) { + switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) { + case SCA: + oper_bw = CHANNEL_WIDTH_40; + oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + case SCB: + oper_bw = CHANNEL_WIDTH_40; + oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; } - pframe = rtw_set_ie(out_ie + out_len, EID_VHTOperation, ielen, p + 2 , pout_len); } - /* find the largest bw supported by both registry and hal */ - notify_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv)); - - if (notify_bw > operation_bw) - notify_bw = operation_bw; + if (oper_bw == CHANNEL_WIDTH_40) { + switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2)) { + case 1: /* 80MHz */ + case 2: /* 160MHz */ + case 3: /* 80+80 */ + oper_bw = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */ + break; + } - /* Operating Mode Notification element */ - notify_len = rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, notify_bw); - *pout_len += notify_len; + oper_bw = rtw_min(oper_bw, max_bw); + + /* try downgrage bw to fit in channel plan setting */ + while (!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset) + || (IS_DFS_SLAVE_WITH_RD(rfctl) + && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)) + && rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset)) + ) { + oper_bw--; + if (oper_bw == CHANNEL_WIDTH_20) { + oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + } + } + } - pvhtpriv->vht_option = _TRUE; + rtw_warn_on(!rtw_chset_is_chbw_valid(chset, oper_ch, oper_bw, oper_offset)); + if (IS_DFS_SLAVE_WITH_RD(rfctl) && !rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl))) + rtw_warn_on(rtw_chset_is_chbw_non_ocp(chset, oper_ch, oper_bw, oper_offset)); + + /* update VHT_OP_IE */ + if (oper_bw < CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0); + } else if (oper_bw == CHANNEL_WIDTH_80) { + u8 cch = rtw_get_center_ch(oper_ch, oper_bw, oper_offset); + + SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 1); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, cch); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0); + } else { + RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(padapter), oper_bw); + rtw_warn_on(1); } + /* Operating Mode Notification element */ + *pout_len += rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, oper_bw); + + pvhtpriv->vht_option = _TRUE; + +exit: return pvhtpriv->vht_option; } @@ -800,4 +1064,72 @@ void VHTOnAssocRsp(_adapter *padapter) rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate)); } +void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 cap_len, operation_len; + uint len = 0; + sint ie_len = 0; + u8 *p = NULL; + + p = rtw_get_ie(pnetwork->IEs + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, + (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) + return; + + rtw_vht_use_default_setting(padapter); + + /* VHT Operation mode notifiy bit in Extended IE (127) */ + SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1); + pmlmepriv->ext_capab_ie_len = 10; + rtw_set_ie(pnetwork->IEs + pnetwork->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); + pnetwork->IELength += pmlmepriv->ext_capab_ie_len; + + /* VHT Capabilities element */ + cap_len = rtw_build_vht_cap_ie(padapter, pnetwork->IEs + pnetwork->IELength); + pnetwork->IELength += cap_len; + + /* VHT Operation element */ + operation_len = rtw_build_vht_operation_ie(padapter, pnetwork->IEs + pnetwork->IELength, + pnetwork->Configuration.DSConfig); + pnetwork->IELength += operation_len; + + rtw_check_for_vht20(padapter, pnetwork->IEs + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_); + + pmlmepriv->vhtpriv.vht_option = _TRUE; +} + +void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + rtw_remove_bcn_ie(padapter, pnetwork, EID_EXTCapability); + rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTCapability); + rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTOperation); + + pmlmepriv->vhtpriv.vht_option = _FALSE; +} + +void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len) +{ + u8 ht_ch, ht_bw, ht_offset; + u8 vht_ch, vht_bw, vht_offset; + + rtw_ies_get_chbw(ies, ies_len, &ht_ch, &ht_bw, &ht_offset, 1, 0); + rtw_ies_get_chbw(ies, ies_len, &vht_ch, &vht_bw, &vht_offset, 1, 1); + + if (ht_bw == CHANNEL_WIDTH_20 && vht_bw >= CHANNEL_WIDTH_80) { + u8 *vht_op_ie; + int vht_op_ielen; + + RTW_INFO(FUNC_ADPT_FMT" vht80 is not allowed without ht40\n", FUNC_ADPT_ARG(adapter)); + vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len); + if (vht_op_ie && vht_op_ielen) { + RTW_INFO(FUNC_ADPT_FMT" switch to vht20\n", FUNC_ADPT_ARG(adapter)); + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0); + } + } +} #endif /* CONFIG_80211AC_VHT */ diff --git a/core/rtw_wapi.c b/core/rtw_wapi.c index d23ed26..1c4279f 100644 --- a/core/rtw_wapi.c +++ b/core/rtw_wapi.c @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifdef CONFIG_WAPI_SUPPORT #include @@ -438,7 +452,8 @@ add to support WAPI to N-mode *****************************************************************************/ u8 rtw_wapi_check_for_drop( _adapter *padapter, - union recv_frame *precv_frame + union recv_frame *precv_frame, + u8 *ehdr_ops ) { PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); @@ -449,7 +464,7 @@ u8 rtw_wapi_check_for_drop( struct recv_frame_hdr *precv_hdr = &precv_frame->u.hdr; u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - u8 *ptr = precv_frame->u.hdr.rx_data; + u8 *ptr = ehdr_ops; int i; WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__); @@ -1050,7 +1065,7 @@ void wapi_test_set_key(struct _adapter *padapter, u8 *buf) void wapi_test_init(struct _adapter *padapter) { u8 keybuf[100]; - u8 mac_addr[6] = {0x00, 0xe0, 0x4c, 0x72, 0x04, 0x70}; + u8 mac_addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x72, 0x04, 0x70}; u8 UskDataKey[16] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f}; u8 UskMicKey[16] = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; u8 UskId = 0; @@ -1076,7 +1091,7 @@ void wapi_test_init(struct _adapter *padapter) keybuf[2] = 1; /* AE */ keybuf[3] = 0; /* not update */ - memcpy(keybuf + 4, mac_addr, 6); + memcpy(keybuf + 4, mac_addr, ETH_ALEN); memcpy(keybuf + 10, UskDataKey, 16); memcpy(keybuf + 26, UskMicKey, 16); keybuf[42] = UskId; @@ -1088,7 +1103,7 @@ void wapi_test_init(struct _adapter *padapter) keybuf[2] = 0; /* AE */ keybuf[3] = 0; /* not update */ - memcpy(keybuf + 4, mac_addr, 6); + memcpy(keybuf + 4, mac_addr, ETH_ALEN); memcpy(keybuf + 10, UskDataKey, 16); memcpy(keybuf + 26, UskMicKey, 16); keybuf[42] = UskId; @@ -1101,7 +1116,7 @@ void wapi_test_init(struct _adapter *padapter) keybuf[1] = 1; /* Enable TX */ keybuf[2] = 1; /* AE */ keybuf[3] = 0; /* not update */ - memcpy(keybuf + 4, mac_addr, 6); + memcpy(keybuf + 4, mac_addr, ETH_ALEN); memcpy(keybuf + 10, MskDataKey, 16); memcpy(keybuf + 26, MskMicKey, 16); keybuf[42] = MskId; @@ -1112,7 +1127,7 @@ void wapi_test_init(struct _adapter *padapter) keybuf[1] = 1; /* Enable TX */ keybuf[2] = 0; /* AE */ keybuf[3] = 0; /* not update */ - memcpy(keybuf + 4, mac_addr, 6); + memcpy(keybuf + 4, mac_addr, ETH_ALEN); memcpy(keybuf + 10, MskDataKey, 16); memcpy(keybuf + 26, MskMicKey, 16); keybuf[42] = MskId; @@ -1237,4 +1252,61 @@ bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA) return bDrop; } +void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param) +{ + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; + PRT_WAPI_STA_INFO pWapiSta; + u8 WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; + u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; + u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; + + if (param->u.crypt.set_tx == 1) { + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if (_rtw_memcmp(pWapiSta->PeerMacAddr, param->sta_addr, 6)) { + _rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16); + + pWapiSta->wapiUsk.bSet = true; + _rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16); + _rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16); + pWapiSta->wapiUsk.keyId = param->u.crypt.idx ; + pWapiSta->wapiUsk.bTxEnable = true; + + _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16); + pWapiSta->wapiUskUpdate.bTxEnable = false; + pWapiSta->wapiUskUpdate.bSet = false; + + if (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) { + /* set unicast key for ASUE */ + rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false); + } + } + } + } else { + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if (_rtw_memcmp(pWapiSta->PeerMacAddr, get_bssid(pmlmepriv), 6)) { + pWapiSta->wapiMsk.bSet = true; + _rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16); + _rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16); + pWapiSta->wapiMsk.keyId = param->u.crypt.idx ; + pWapiSta->wapiMsk.bTxEnable = false; + if (!pWapiSta->bSetkeyOk) + pWapiSta->bSetkeyOk = true; + pWapiSta->bAuthenticateInProgress = false; + + _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); + + if (psecuritypriv->sw_decrypt == false) { + /* set rx broadcast key for ASUE */ + rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false); + } + } + } + } +} #endif diff --git a/core/rtw_wapi_sms4.c b/core/rtw_wapi_sms4.c index fc01212..4b7cf95 100644 --- a/core/rtw_wapi_sms4.c +++ b/core/rtw_wapi_sms4.c @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifdef CONFIG_WAPI_SUPPORT #include diff --git a/core/rtw_wlan_util.c b/core/rtw_wlan_util.c index c2e67aa..ce2df3b 100644 --- a/core/rtw_wlan_util.c +++ b/core/rtw_wlan_util.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_WLAN_UTIL_C_ #include @@ -27,6 +22,8 @@ #define ETH_TYPE_OFFSET 12 #define PROTOCOL_OFFSET 23 #define IP_OFFSET 30 + #define IPv6_OFFSET 38 + #define IPv6_PROTOCOL_OFFSET 20 #endif unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f}; @@ -55,9 +52,6 @@ extern unsigned char RSN_TKIP_CIPHER[4]; #define WAIT_FOR_BCN_TO_MIN (6000) #define WAIT_FOR_BCN_TO_MAX (20000) -#define DISCONNECT_BY_CHK_BCN_FAIL_OBSERV_PERIOD_IN_MS 1000 -#define DISCONNECT_BY_CHK_BCN_FAIL_THRESHOLD 3 - static u8 rtw_basic_rate_cck[4] = { IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK @@ -75,8 +69,41 @@ static u8 rtw_basic_rate_mix[7] = { IEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK }; -int new_bcn_max = 3; +/* test if rate is defined in rtw_basic_rate_cck */ +bool rtw_is_basic_rate_cck(u8 rate) +{ + int i; + + for (i = 0; i < 4; i++) + if ((rtw_basic_rate_cck[i] & 0x7F) == (rate & 0x7F)) + return 1; + return 0; +} + +/* test if rate is defined in rtw_basic_rate_ofdm */ +bool rtw_is_basic_rate_ofdm(u8 rate) +{ + int i; + + for (i = 0; i < 3; i++) + if ((rtw_basic_rate_ofdm[i] & 0x7F) == (rate & 0x7F)) + return 1; + return 0; +} +/* test if rate is defined in rtw_basic_rate_mix */ +bool rtw_is_basic_rate_mix(u8 rate) +{ + int i; + + for (i = 0; i < 7; i++) + if ((rtw_basic_rate_mix[i] & 0x7F) == (rate & 0x7F)) + return 1; + return 0; +} +#ifdef CONFIG_BCN_CNT_CONFIRM_HDL +int new_bcn_max = 3; +#endif int cckrates_included(unsigned char *rate, int ratelen) { int i; @@ -104,8 +131,7 @@ int cckratesonly_included(unsigned char *rate, int ratelen) return _TRUE; } -#ifdef CONFIG_GET_RAID_BY_DRV -s8 rtw_get_tx_nss(_adapter *adapter, struct sta_info *psta) +s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta) { struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); u8 rf_type = RF_1T1R, custom_rf_type; @@ -119,154 +145,50 @@ s8 rtw_get_tx_nss(_adapter *adapter, struct sta_info *psta) if (RF_TYPE_VALID(custom_rf_type)) rf_type = custom_rf_type; -#ifdef CONFIG_80211AC_VHT - if (psta->vhtpriv.vht_option) { - nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num); + +#ifdef CONFIG_80211N_HT + #ifdef CONFIG_80211AC_VHT + if (psta->vhtpriv.vht_option) nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map)); - } else -#endif /* CONFIG_80211AC_VHT */ - if (psta->htpriv.ht_option) { - nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + else + #endif /* CONFIG_80211AC_VHT */ + if (psta->htpriv.ht_option) nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set)); - } - +#endif /*CONFIG_80211N_HT*/ RTW_INFO("%s: %d SS\n", __func__, nss); return nss; } -u8 networktype_to_raid(_adapter *adapter, struct sta_info *psta) +s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta) { - unsigned char raid; - switch (psta->wireless_mode) { - case WIRELESS_11B: - raid = RATR_INX_WIRELESS_B; - break; - case WIRELESS_11A: - case WIRELESS_11G: - raid = RATR_INX_WIRELESS_G; - break; - case WIRELESS_11BG: - raid = RATR_INX_WIRELESS_GB; - break; - case WIRELESS_11_24N: - case WIRELESS_11_5N: - raid = RATR_INX_WIRELESS_N; - break; - case WIRELESS_11A_5N: - case WIRELESS_11G_24N: - raid = RATR_INX_WIRELESS_NG; - break; - case WIRELESS_11BG_24N: - raid = RATR_INX_WIRELESS_NGB; - break; - default: - raid = RATR_INX_WIRELESS_GB; - break; - - } - return raid; - -} - -u8 networktype_to_raid_ex(_adapter *adapter, struct sta_info *psta) -{ - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - u8 raid = RATEID_IDX_BGN_40M_1SS, cur_rf_type, rf_type, custom_rf_type; - s8 tx_nss; - - tx_nss = rtw_get_tx_nss(adapter, psta); - - switch (psta->wireless_mode) { - case WIRELESS_11B: - raid = RATEID_IDX_B; - break; - case WIRELESS_11A: - case WIRELESS_11G: - raid = RATEID_IDX_G; - break; - case WIRELESS_11BG: - raid = RATEID_IDX_BG; - break; - case WIRELESS_11_24N: - case WIRELESS_11_5N: - case WIRELESS_11A_5N: - case WIRELESS_11G_24N: - if (tx_nss == 1) - raid = RATEID_IDX_GN_N1SS; - else if (tx_nss == 2) - raid = RATEID_IDX_GN_N2SS; - else if (tx_nss == 3) - raid = RATEID_IDX_BGN_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - break; - case WIRELESS_11B_24N: - case WIRELESS_11BG_24N: - if (psta->bw_mode == CHANNEL_WIDTH_20) { - if (tx_nss == 1) - raid = RATEID_IDX_BGN_20M_1SS_BN; - else if (tx_nss == 2) - raid = RATEID_IDX_BGN_20M_2SS_BN; - else if (tx_nss == 3) - raid = RATEID_IDX_BGN_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - } else { - if (tx_nss == 1) - raid = RATEID_IDX_BGN_40M_1SS; - else if (tx_nss == 2) - raid = RATEID_IDX_BGN_40M_2SS; - else if (tx_nss == 3) - raid = RATEID_IDX_BGN_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - } - break; -#ifdef CONFIG_80211AC_VHT - case WIRELESS_11_5AC: - if (tx_nss == 1) - raid = RATEID_IDX_VHT_1SS; - else if (tx_nss == 2) - raid = RATEID_IDX_VHT_2SS; - else if (tx_nss == 3) - raid = RATEID_IDX_VHT_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - break; - case WIRELESS_11_24AC: - if (psta->bw_mode >= CHANNEL_WIDTH_80) { - if (tx_nss == 1) - raid = RATEID_IDX_VHT_1SS; - else if (tx_nss == 2) - raid = RATEID_IDX_VHT_2SS; - else if (tx_nss == 3) - raid = RATEID_IDX_VHT_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - } else { - if (tx_nss == 1) - raid = RATEID_IDX_MIX1; - else if (tx_nss == 2) - raid = RATEID_IDX_MIX2; - else if (tx_nss == 3) - raid = RATEID_IDX_VHT_3SS; - else - RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); - } - break; -#endif - default: - RTW_INFO("unexpected wireless mode!(psta->wireless_mode=%x)\n", psta->wireless_mode); - break; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 rf_type = RF_1T1R, custom_rf_type; + s8 nss = 1; - } + if (!psta) + return nss; - /* RTW_INFO("psta->wireless_mode=%x, tx_nss=%d\n", psta->wireless_mode, tx_nss); */ + custom_rf_type = adapter->registrypriv.rf_config; + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + if (RF_TYPE_VALID(custom_rf_type)) + rf_type = custom_rf_type; - return raid; + nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); +#ifdef CONFIG_80211N_HT + #ifdef CONFIG_80211AC_VHT + if (psta->vhtpriv.vht_option) + nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map)); + else + #endif /* CONFIG_80211AC_VHT */ + if (psta->htpriv.ht_option) + nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set)); +#endif /*CONFIG_80211N_HT*/ + RTW_INFO("%s: %d SS\n", __func__, nss); + return nss; } -#endif + u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen) { u8 network_type = 0; @@ -615,53 +537,6 @@ u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset) return valid; } -u8 rtw_get_offset_by_ch(u8 channel) -{ - u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - - if (channel >= 1 && channel <= 4) - offset = HAL_PRIME_CHNL_OFFSET_LOWER; - else if (channel >= 5 && channel <= 14) - offset = HAL_PRIME_CHNL_OFFSET_UPPER; - else { - switch (channel) { - case 36: - case 44: - case 52: - case 60: - case 100: - case 108: - case 116: - case 124: - case 132: - case 149: - case 157: - offset = HAL_PRIME_CHNL_OFFSET_LOWER; - break; - case 40: - case 48: - case 56: - case 64: - case 104: - case 112: - case 120: - case 128: - case 136: - case 153: - case 161: - offset = HAL_PRIME_CHNL_OFFSET_UPPER; - break; - default: - offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - break; - } - - } - - return offset; - -} - u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset) { u8 center_ch = channel; @@ -696,12 +571,12 @@ u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset) return center_ch; } -inline u32 rtw_get_on_oper_ch_time(_adapter *adapter) +inline systime rtw_get_on_oper_ch_time(_adapter *adapter) { return adapter_to_dvobj(adapter)->on_oper_ch_time; } -inline u32 rtw_get_on_cur_ch_time(_adapter *adapter) +inline systime rtw_get_on_cur_ch_time(_adapter *adapter) { if (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel) return adapter_to_dvobj(adapter)->on_oper_ch_time; @@ -712,7 +587,6 @@ inline u32 rtw_get_on_cur_ch_time(_adapter *adapter) void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode) { u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; #if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE) u8 iqk_info_backup = _FALSE; #endif @@ -735,10 +609,8 @@ void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char #ifdef CONFIG_MCC_MODE if (MCC_EN(padapter)) { /* driver doesn't set channel setting reg under MCC */ - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) RTW_INFO("Warning: Do not set channel setting reg MCC mode\n"); - rtw_warn_on(1); - } } #endif @@ -795,16 +667,6 @@ void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); } -int get_bsstype(unsigned short capability) -{ - if (capability & BIT(0)) - return WIFI_FW_AP_STATE; - else if (capability & BIT(1)) - return WIFI_FW_ADHOC_STATE; - else - return 0; -} - __inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork) { return pnetwork->MacAddress; @@ -855,7 +717,7 @@ int is_IBSS_empty(_adapter *padapter) for (i = 0; i < macid_ctl->num; i++) { if (!rtw_macid_is_used(macid_ctl, i)) continue; - if (rtw_macid_get_if_g(macid_ctl, i) != padapter->iface_id) + if (!rtw_macid_is_iface_specific(macid_ctl, i, padapter)) continue; if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[i])) continue; @@ -1296,7 +1158,7 @@ s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk) return cam_id; } -s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid) +s16 rtw_get_camid(_adapter *adapter, u8 *addr, s16 kid, u8 gk) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; @@ -1317,7 +1179,7 @@ s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid) /* find cam entry which has the same addr, kid (, gk bit) */ if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC) == _TRUE) - i = _rtw_camid_search(adapter, addr, kid, sta ? _FALSE : _TRUE); + i = _rtw_camid_search(adapter, addr, kid, gk); else i = _rtw_camid_search(adapter, addr, kid, -1); @@ -1337,12 +1199,8 @@ s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid) } if (i == cam_ctl->num) { - if (sta) - RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u no room\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid); - else - RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" id:%u no room\n" - , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid); + RTW_PRINT(FUNC_ADPT_FMT" %s key with "MAC_FMT" id:%u no room\n" + , FUNC_ADPT_ARG(adapter), gk ? "group" : "pairwise", MAC_ARG(addr), kid); rtw_warn_on(1); goto _exit; } @@ -1354,7 +1212,7 @@ s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid) return cam_id; } -s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used) +s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool *used) { struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); @@ -1368,8 +1226,12 @@ s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used) if ((((mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) && !sta) { + /* + * 1. non-STA mode WEP key + * 2. group TX key + */ #ifndef CONFIG_CONCURRENT_MODE - /* AP/Ad-hoc mode group key static alloction to default key by key ID on Non-concurrent*/ + /* static alloction to default key by key ID when concurrent is not defined */ if (kid > 3) { RTW_PRINT(FUNC_ADPT_FMT" group key with invalid key id:%u\n" , FUNC_ADPT_ARG(adapter), kid); @@ -1380,13 +1242,18 @@ s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used) #else u8 *addr = adapter_mac_addr(adapter); - cam_id = rtw_get_camid(adapter, sta, addr, kid); + cam_id = rtw_get_camid(adapter, addr, kid, gk); if (1) RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" assigned cam_id:%u\n" , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), cam_id); #endif } else { - u8 *addr = sta ? sta->hwaddr : NULL; + /* + * 1. STA mode WEP key + * 2. STA mode group RX key + * 3. sta key (pairwise, group RX) + */ + u8 *addr = sta ? sta->cmn.mac_addr : NULL; if (!sta) { if (!(mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) { @@ -1395,7 +1262,7 @@ s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used) } addr = get_bssid(&adapter->mlmepriv);/*A2*/ } - cam_id = rtw_get_camid(adapter, sta, addr, kid); + cam_id = rtw_get_camid(adapter, addr, kid, gk); } @@ -1538,12 +1405,12 @@ void rtw_clean_hw_dk_cam(_adapter *adapter) void flush_all_cam_entry(_adapter *padapter) { +#ifdef CONFIG_CONCURRENT_MODE struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct security_priv *psecpriv = &padapter->securitypriv; -#ifdef CONFIG_CONCURRENT_MODE if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta; @@ -1555,7 +1422,7 @@ void flush_all_cam_entry(_adapter *padapter) } else rtw_clearstakey_cmd(padapter, psta, _FALSE); } - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + } else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { #if 1 int cam_id = -1; u8 *addr = adapter_mac_addr(padapter); @@ -1673,6 +1540,10 @@ void WMMOnAssocRsp(_adapter *padapter) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct registry_priv *pregpriv = &padapter->registrypriv; +#ifdef CONFIG_WMMPS_STA + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct qos_priv *pqospriv = &pmlmepriv->qospriv; +#endif /* CONFIG_WMMPS_STA */ acm_mask = 0; @@ -1798,10 +1669,14 @@ void WMMOnAssocRsp(_adapter *padapter) pxmitpriv->wmm_para_seq[i] = inx[i]; RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]); } -#ifdef CONFIG_WMMPS - if (pmlmeinfo->WMM_param.QoS_info & BIT(7)) + +#ifdef CONFIG_WMMPS_STA + /* if AP supports UAPSD function, driver must set each uapsd TID to coresponding mac register 0x693 */ + if (pmlmeinfo->WMM_param.QoS_info & AP_SUPPORTED_UAPSD) { + pqospriv->uapsd_ap_supported = 1; rtw_hal_set_hwreg(padapter, HW_VAR_UAPSD_TID, NULL); -#endif + } +#endif /* CONFIG_WMMPS_STA */ } } @@ -1894,10 +1769,10 @@ static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pI if (phtpriv_sta->ht_option) { /* bwmode */ - psta->bw_mode = pmlmeext->cur_bwmode; + psta->cmn.bw_mode = pmlmeext->cur_bwmode; phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; } else { - psta->bw_mode = CHANNEL_WIDTH_20; + psta->cmn.bw_mode = CHANNEL_WIDTH_20; phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; } @@ -1909,6 +1784,97 @@ static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pI #endif /* CONFIG_80211N_HT */ } +#ifdef ROKU_PRIVATE +void Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + unsigned int i; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (pIE == NULL) + return; + + for (i = 0 ; i < pIE->Length; i++) + pmlmeinfo->SupportedRates_infra_ap[i] = (pIE->data[i]); + +} + +void Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + unsigned int i, j; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (pIE == NULL) + return; + + if (pIE->Length > 0) { + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (pmlmeinfo->SupportedRates_infra_ap[i] == 0) + break; + } + for (j = 0; j < pIE->Length; j++) + pmlmeinfo->SupportedRates_infra_ap[i+j] = (pIE->data[j]); + } + +} + +void HT_get_ss_from_mcs_set(u8 *mcs_set, u8 *Rx_ss) +{ + u8 i, j; + u8 r_ss = 0, t_ss = 0; + + for (i = 0; i < 4; i++) { + if ((mcs_set[3-i] & 0xff) != 0x00) { + r_ss = 4-i; + break; + } + } + + *Rx_ss = r_ss; +} + +void HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + unsigned int i; + u8 cur_stbc_cap_infra_ap = 0; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv_infra_ap *phtpriv = &pmlmepriv->htpriv_infra_ap; + + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (pIE == NULL) + return; + + pmlmeinfo->ht_vht_received |= BIT(0); + + /*copy MCS_SET*/ + for (i = 3; i < 19; i++) + phtpriv->MCS_set_infra_ap[i-3] = (pIE->data[i]); + + /*get number of stream from mcs set*/ + HT_get_ss_from_mcs_set(phtpriv->MCS_set_infra_ap, &phtpriv->Rx_ss_infra_ap); + + phtpriv->rx_highest_data_rate_infra_ap = le16_to_cpu(GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(pIE->data)); + + phtpriv->ldpc_cap_infra_ap = GET_HT_CAP_ELE_LDPC_CAP(pIE->data); + + if (GET_HT_CAP_ELE_RX_STBC(pIE->data)) + SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_RX); + if (GET_HT_CAP_ELE_TX_STBC(pIE->data)) + SET_FLAG(cur_stbc_cap_infra_ap, STBC_HT_ENABLE_TX); + phtpriv->stbc_cap_infra_ap = cur_stbc_cap_infra_ap; + + /*store ap info SGI 20m 40m*/ + phtpriv->sgi_20m_infra_ap = GET_HT_CAP_ELE_SHORT_GI20M(pIE->data); + phtpriv->sgi_40m_infra_ap = GET_HT_CAP_ELE_SHORT_GI40M(pIE->data); + + /*store ap info for supported channel bandwidth*/ + phtpriv->channel_width_infra_ap = GET_HT_CAP_ELE_CHL_WIDTH(pIE->data); +} +#endif /* ROKU_PRIVATE */ + void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) { #ifdef CONFIG_80211N_HT @@ -1920,7 +1886,9 @@ void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct ht_priv *phtpriv = &pmlmepriv->htpriv; +#ifdef CONFIG_DISABLE_MCS13TO15 struct registry_priv *pregistrypriv = &padapter->registrypriv; +#endif struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); if (pIE == NULL) @@ -2126,9 +2094,9 @@ void HTOnAssocRsp(_adapter *padapter) min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2; rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing)); - +#ifdef CONFIG_80211N_HT rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len)); - +#endif /* CONFIG_80211N_HT */ #if 0 /* move to rtw_update_ht_cap() */ if ((pregpriv->bw_mode > 0) && (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) && @@ -2191,7 +2159,6 @@ void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) void VCS_update(_adapter *padapter, struct sta_info *psta) { struct registry_priv *pregpriv = &padapter->registrypriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -2238,21 +2205,29 @@ void update_ldpc_stbc_cap(struct sta_info *psta) #ifdef CONFIG_80211AC_VHT if (psta->vhtpriv.vht_option) { if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_TX)) - psta->ldpc = 1; + psta->cmn.ldpc_en = VHT_LDPC_EN; + else + psta->cmn.ldpc_en = 0; if (TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX)) - psta->stbc = 1; + psta->cmn.stbc_en = VHT_STBC_EN; + else + psta->cmn.stbc_en = 0; } else #endif /* CONFIG_80211AC_VHT */ if (psta->htpriv.ht_option) { if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_ENABLE_TX)) - psta->ldpc = 1; + psta->cmn.ldpc_en = HT_LDPC_EN; + else + psta->cmn.ldpc_en = 0; if (TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX)) - psta->stbc = 1; + psta->cmn.stbc_en = HT_STBC_EN; + else + psta->cmn.stbc_en = 0; } else { - psta->ldpc = 0; - psta->stbc = 0; + psta->cmn.ldpc_en = 0; + psta->cmn.stbc_en = 0; } #endif /* CONFIG_80211N_HT */ @@ -2262,7 +2237,6 @@ int check_ielen(u8 *start, uint len) { int left = len; u8 *pos = start; - int unknown = 0; u8 id, elen; while (left >= 2) { @@ -2275,7 +2249,7 @@ int check_ielen(u8 *start, uint len) id, elen, (unsigned long) left); return _FALSE; } - if ((id == WLAN_EID_VENDOR_SPECIFIC) && (elen < 4)) + if ((id == WLAN_EID_VENDOR_SPECIFIC) && (elen < 3)) return _FALSE; left -= elen; @@ -2302,6 +2276,175 @@ int validate_beacon_len(u8 *pframe, u32 len) return _TRUE; } + +u8 support_rate_ranges[] = { + IEEE80211_CCK_RATE_1MB, + IEEE80211_CCK_RATE_2MB, + IEEE80211_CCK_RATE_5MB, + IEEE80211_CCK_RATE_11MB, + IEEE80211_OFDM_RATE_6MB, + IEEE80211_OFDM_RATE_9MB, + IEEE80211_OFDM_RATE_12MB, + IEEE80211_OFDM_RATE_18MB, + IEEE80211_OFDM_RATE_24MB, + IEEE80211_OFDM_RATE_36MB, + IEEE80211_OFDM_RATE_48MB, + IEEE80211_OFDM_RATE_54MB, +}; + +inline bool match_ranges(u16 EID, u32 value) +{ + int i; + int nr_range; + + switch (EID) { + case _EXT_SUPPORTEDRATES_IE_: + case _SUPPORTEDRATES_IE_: + nr_range = sizeof(support_rate_ranges)/sizeof(u8); + for (i = 0; i < nr_range; i++) { + /* clear bit7 before searching. */ + value &= ~BIT(7); + if (value == support_rate_ranges[i]) + return _TRUE; + } + break; + default: + break; + }; + return _FALSE; +} + +/* + * rtw_validate_value: validate the IE contain. + * + * Input : + * EID : Element ID + * p : IE buffer (without EID & length) + * len : IE length + * return: + * _TRUE : All Values are validated. + * _FALSE : At least one value is NOT validated. + */ +bool rtw_validate_value(u16 EID, u8 *p, u16 len) +{ + u8 rate; + u32 i, nr_val; + + switch (EID) { + case _EXT_SUPPORTEDRATES_IE_: + case _SUPPORTEDRATES_IE_: + nr_val = len; + for (i=0; iSsid.SsidLength == 0) || + is_all_null(snetwork->Ssid.Ssid, snetwork->Ssid.SsidLength) == _TRUE); +} + +/* + Get SSID if this ilegal frame(probe resp) comes from a hidden SSID AP. + Update the SSID to the corresponding pnetwork in scan queue. +*/ +void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe) +{ + struct wlan_network *scanned = NULL; + WLAN_BSSID_EX *snetwork; + u8 ie_offset, *p=NULL, *next_ie=NULL, *mac = get_addr2_ptr(pframe); + sint len, ssid_len_ori; + u32 remain_len = 0; + u8 backupIE[MAX_IE_SZ]; + u16 subtype = get_frame_sub_type(pframe); + _irqL irqL; + + if ((!bssid) || (!pframe)) + return; + + if (subtype == WIFI_BEACON) { + bssid->Reserved[0] = BSS_TYPE_BCN; + ie_offset = _BEACON_IE_OFFSET_; + } else { + /* FIXME : more type */ + if (subtype == WIFI_PROBERSP) { + ie_offset = _PROBERSP_IE_OFFSET_; + bssid->Reserved[0] = BSS_TYPE_PROB_RSP; + } else if (subtype == WIFI_PROBEREQ) { + ie_offset = _PROBEREQ_IE_OFFSET_; + bssid->Reserved[0] = BSS_TYPE_PROB_REQ; + } else { + bssid->Reserved[0] = BSS_TYPE_UNDEF; + ie_offset = _FIXED_IE_LENGTH_; + } + } + + _enter_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL); + scanned = _rtw_find_network(&padapter->mlmepriv.scanned_queue, mac); + if (!scanned) { + _exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL); + return; + } + + snetwork = &(scanned->network); + /* scan queue records as Hidden SSID && Input frame is NOT Hidden SSID */ + if (hidden_ssid_ap(snetwork) && !hidden_ssid_ap(bssid)) { + p = rtw_get_ie(snetwork->IEs+ie_offset, _SSID_IE_, &ssid_len_ori, snetwork->IELength-ie_offset); + if (!p) { + _exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL); + return; + } + next_ie = p + 2 + ssid_len_ori; + remain_len = snetwork->IELength - (next_ie - snetwork->IEs); + scanned->network.Ssid.SsidLength = bssid->Ssid.SsidLength; + _rtw_memcpy(scanned->network.Ssid.Ssid, bssid->Ssid.Ssid, bssid->Ssid.SsidLength); + + //update pnetwork->ssid, pnetwork->ssidlen + _rtw_memcpy(backupIE, next_ie, remain_len); + *(p+1) = bssid->Ssid.SsidLength; + _rtw_memcpy(p+2, bssid->Ssid.Ssid, bssid->Ssid.SsidLength); + _rtw_memcpy(p+2+bssid->Ssid.SsidLength, backupIE, remain_len); + snetwork->IELength += bssid->Ssid.SsidLength; + } + _exit_critical_bh(&padapter->mlmepriv.scanned_queue.lock, &irqL); +} + +#ifdef DBG_RX_BCN +void rtw_debug_rx_bcn(_adapter *adapter, u8 *pframe, u32 packet_len) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *mlmeinfo = &(pmlmeext->mlmext_info); + u16 sn = ((struct rtw_ieee80211_hdr_3addr *)pframe)->seq_ctl >> 4; + u64 tsf, tsf_offset; + u8 dtim_cnt, dtim_period, tim_bmap, tim_pvbit; + + update_TSF(pmlmeext, pframe, packet_len); + tsf = pmlmeext->TSFValue; + tsf_offset = rtw_modular64(pmlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024)); + + /*get TIM IE*/ + /*DTIM Count*/ + dtim_cnt = pmlmeext->tim[0]; + /*DTIM Period*/ + dtim_period = pmlmeext->tim[1]; + /*Bitmap*/ + tim_bmap = pmlmeext->tim[2]; + /*Partial VBitmap AID 0 ~ 7*/ + tim_pvbit = pmlmeext->tim[3]; + + RTW_INFO("[BCN] SN-%d, TSF-%lld(us), offset-%lld, bcn_interval-%d DTIM-%d[%d] bitmap-0x%02x-0x%02x\n", + sn, tsf, tsf_offset, mlmeinfo->bcn_interval, dtim_period, dtim_cnt, tim_bmap, tim_pvbit); +} +#endif + /* * rtw_get_bcn_keys: get beacon keys from recv frame * @@ -2377,7 +2520,7 @@ int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len, recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA2; rtw_parse_wpa2_ie(elems.rsn_ie - 2, elems.rsn_ie_len + 2, &recv_beacon->group_cipher, &recv_beacon->pairwise_cipher, - &recv_beacon->is_8021x); + &recv_beacon->is_8021x, NULL); } /* checking WPA secon */ else if (elems.wpa_ie && elems.wpa_ie_len) { @@ -2388,50 +2531,36 @@ int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len, } else if (capability & BIT(4)) recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WEP; + if (elems.tim && elems.tim_len) { + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + + #ifdef DBG_RX_BCN + _rtw_memcpy(pmlmeext->tim, elems.tim, 4); + #endif + pmlmeext->dtim = elems.tim[1]; + } + return _TRUE; } void rtw_dump_bcn_keys(struct beacon_keys *recv_beacon) { - int i; - char *p; u8 ssid[IW_ESSID_MAX_SIZE + 1]; _rtw_memcpy(ssid, recv_beacon->ssid, recv_beacon->ssid_len); ssid[recv_beacon->ssid_len] = '\0'; RTW_INFO("%s: ssid = %s\n", __func__, ssid); - RTW_INFO("%s: channel = %x\n", __func__, recv_beacon->bcn_channel); - RTW_INFO("%s: ht_cap = %x\n", __func__, recv_beacon->ht_cap_info); - RTW_INFO("%s: ht_info_infos_0_sco = %x\n", __func__, recv_beacon->ht_info_infos_0_sco); + RTW_INFO("%s: channel = %d\n", __func__, recv_beacon->bcn_channel); + RTW_INFO("%s: ht_cap = 0x%04x\n", __func__, recv_beacon->ht_cap_info); + RTW_INFO("%s: ht_info_infos_0_sco = 0x%02x\n", __func__, recv_beacon->ht_info_infos_0_sco); RTW_INFO("%s: sec=%d, group = %x, pair = %x, 8021X = %x\n", __func__, recv_beacon->encryp_protocol, recv_beacon->group_cipher, recv_beacon->pairwise_cipher, recv_beacon->is_8021x); } - +#define DBG_BCN_CNT int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) { -#if 0 - unsigned int len; - unsigned char *p; - unsigned short val16, subtype; - struct wlan_network *cur_network = &(Adapter->mlmepriv.cur_network); - /* u8 wpa_ie[255],rsn_ie[255]; */ - u16 wpa_len = 0, rsn_len = 0; - u8 encryp_protocol = 0; - WLAN_BSSID_EX *bssid; - int group_cipher = 0, pairwise_cipher = 0, is_8021x = 0; - unsigned char *pbuf; - u32 wpa_ielen = 0; - u8 *pbssid = GetAddr3Ptr(pframe); - u32 hidden_ssid = 0; - u8 cur_network_type, network_type = 0; - struct HT_info_element *pht_info = NULL; - struct rtw_ieee80211_ht_cap *pht_cap = NULL; - u32 bcn_channel; - unsigned short ht_cap_info; - unsigned char ht_info_infos_0; -#endif unsigned int len; u8 *pbssid = GetAddr3Ptr(pframe); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; @@ -2457,13 +2586,17 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) if (rtw_get_bcn_keys(Adapter, pframe, packet_len, &recv_beacon) == _FALSE) return _TRUE; /* parsing failed => broken IE */ +#ifdef DBG_RX_BCN + rtw_debug_bcn(Adapter, pframe, packet_len); +#endif + /* don't care hidden ssid, use current beacon ssid directly */ if (recv_beacon.ssid_len == 0) { _rtw_memcpy(recv_beacon.ssid, pmlmepriv->cur_beacon_keys.ssid, pmlmepriv->cur_beacon_keys.ssid_len); recv_beacon.ssid_len = pmlmepriv->cur_beacon_keys.ssid_len; } - +#ifdef CONFIG_BCN_CNT_CONFIRM_HDL if (_rtw_memcmp(&recv_beacon, &pmlmepriv->cur_beacon_keys, sizeof(recv_beacon)) == _TRUE) pmlmepriv->new_beacon_cnts = 0; else if ((pmlmepriv->new_beacon_cnts == 0) || @@ -2478,7 +2611,7 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) RTW_DBG("%s: new beacon key\n", __func__); RTW_DBG_EXPR(rtw_dump_bcn_keys(&recv_beacon)); - memcpy(&pmlmepriv->new_beacon_keys, &recv_beacon, sizeof(recv_beacon)); + _rtw_memcpy(&pmlmepriv->new_beacon_keys, &recv_beacon, sizeof(recv_beacon)); pmlmepriv->new_beacon_cnts = 1; } else { RTW_DBG("%s: new beacon again (seq=%d)\n", __func__, GetSequence(pframe)); @@ -2486,7 +2619,11 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) } /* if counter >= max, it means beacon is changed really */ - if (pmlmepriv->new_beacon_cnts >= new_bcn_max) { + if (pmlmepriv->new_beacon_cnts >= new_bcn_max) +#else + if (_rtw_memcmp(&recv_beacon, &pmlmepriv->cur_beacon_keys, sizeof(recv_beacon)) == _FALSE) +#endif + { /* check bw mode change only? */ pmlmepriv->cur_beacon_keys.ht_cap_info = recv_beacon.ht_cap_info; pmlmepriv->cur_beacon_keys.ht_info_infos_0_sco = recv_beacon.ht_info_infos_0_sco; @@ -2494,204 +2631,35 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) sizeof(recv_beacon)) == _FALSE) { /* beacon is changed, have to do disconnect/connect */ RTW_WARN("%s: new beacon occur!!\n", __func__); + #ifdef DBG_BCN_CNT + rtw_dump_bcn_keys(&recv_beacon); + #endif return _FAIL; } - + #ifdef DBG_BCN_CNT RTW_INFO("%s bw mode change\n", __func__); RTW_INFO("%s bcn now: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, cur_network->BcnInfo.ht_cap_info, cur_network->BcnInfo.ht_info_infos_0); + #endif cur_network->BcnInfo.ht_cap_info = recv_beacon.ht_cap_info; cur_network->BcnInfo.ht_info_infos_0 = (cur_network->BcnInfo.ht_info_infos_0 & (~0x03)) | recv_beacon.ht_info_infos_0_sco; + #ifdef DBG_BCN_CNT RTW_INFO("%s bcn link: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, cur_network->BcnInfo.ht_cap_info, cur_network->BcnInfo.ht_info_infos_0); - - memcpy(&pmlmepriv->cur_beacon_keys, &recv_beacon, sizeof(recv_beacon)); + #endif + _rtw_memcpy(&pmlmepriv->cur_beacon_keys, &recv_beacon, sizeof(recv_beacon)); + #ifdef CONFIG_BCN_CNT_CONFIRM_HDL pmlmepriv->new_beacon_cnts = 0; + #endif } return _SUCCESS; - -#if 0 - bssid = (WLAN_BSSID_EX *)rtw_zmalloc(sizeof(WLAN_BSSID_EX)); - if (bssid == NULL) { - RTW_INFO("%s rtw_zmalloc fail !!!\n", __func__); - return _TRUE; - } - - if ((pmlmepriv->timeBcnInfoChkStart != 0) && (rtw_get_passing_time_ms(pmlmepriv->timeBcnInfoChkStart) > DISCONNECT_BY_CHK_BCN_FAIL_OBSERV_PERIOD_IN_MS)) { - pmlmepriv->timeBcnInfoChkStart = 0; - pmlmepriv->NumOfBcnInfoChkFail = 0; - } - - subtype = get_frame_sub_type(pframe) >> 4; - - if (subtype == WIFI_BEACON) - bssid->Reserved[0] = 1; - - bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len; - - /* below is to copy the information element */ - bssid->IELength = len; - _rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength); - - /* check bw and channel offset */ - /* parsing HT_CAP_IE */ - p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); - if (p && len > 0) { - pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2); - ht_cap_info = pht_cap->cap_info; - } else - ht_cap_info = 0; - /* parsing HT_INFO_IE */ - p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); - if (p && len > 0) { - pht_info = (struct HT_info_element *)(p + 2); - ht_info_infos_0 = pht_info->infos[0]; - } else - ht_info_infos_0 = 0; - if (ht_cap_info != cur_network->BcnInfo.ht_cap_info || - ((ht_info_infos_0 & 0x03) != (cur_network->BcnInfo.ht_info_infos_0 & 0x03))) { - RTW_INFO("%s bcn now: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, - ht_cap_info, ht_info_infos_0); - RTW_INFO("%s bcn link: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, - cur_network->BcnInfo.ht_cap_info, cur_network->BcnInfo.ht_info_infos_0); - RTW_INFO("%s bw mode change\n", __func__); - { - /* bcn_info_update */ - cur_network->BcnInfo.ht_cap_info = ht_cap_info; - cur_network->BcnInfo.ht_info_infos_0 = ht_info_infos_0; - /* to do : need to check that whether modify related register of BB or not */ - } - /* goto _mismatch; */ - } - - /* Checking for channel */ - p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _DSSET_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); - if (p) - bcn_channel = *(p + 2); - else {/* In 5G, some ap do not have DSSET IE checking HT info for channel */ - rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); - if (pht_info) - bcn_channel = pht_info->primary_channel; - else { /* we don't find channel IE, so don't check it */ - /* RTW_INFO("Oops: %s we don't find channel IE, so don't check it\n", __func__); */ - bcn_channel = Adapter->mlmeextpriv.cur_channel; - } - } - if (bcn_channel != Adapter->mlmeextpriv.cur_channel) { - RTW_INFO("%s beacon channel:%d cur channel:%d disconnect\n", __func__, - bcn_channel, Adapter->mlmeextpriv.cur_channel); - goto _mismatch; - } - - /* checking SSID */ - p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _SSID_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); - if (p == NULL) { - RTW_INFO("%s marc: cannot find SSID for survey event\n", __func__); - hidden_ssid = _TRUE; - } else - hidden_ssid = _FALSE; - - if ((NULL != p) && (_FALSE == hidden_ssid && (*(p + 1)))) { - _rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1)); - bssid->Ssid.SsidLength = *(p + 1); - } else { - bssid->Ssid.SsidLength = 0; - bssid->Ssid.Ssid[0] = '\0'; - } - - - if (_rtw_memcmp(bssid->Ssid.Ssid, cur_network->network.Ssid.Ssid, 32) == _FALSE || - bssid->Ssid.SsidLength != cur_network->network.Ssid.SsidLength) { - if (bssid->Ssid.Ssid[0] != '\0' && bssid->Ssid.SsidLength != 0) { /* not hidden ssid */ - RTW_INFO("%s(), SSID is not match\n", __func__); - goto _mismatch; - } - } - - /* check encryption info */ - val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid); - - if (val16 & BIT(4)) - bssid->Privacy = 1; - else - bssid->Privacy = 0; - - if (cur_network->network.Privacy != bssid->Privacy) { - RTW_INFO("%s(), privacy is not match\n", __func__); - goto _mismatch; - } - - rtw_get_sec_ie(bssid->IEs, bssid->IELength, NULL, &rsn_len, NULL, &wpa_len); - - if (rsn_len > 0) - encryp_protocol = ENCRYP_PROTOCOL_WPA2; - else if (wpa_len > 0) - encryp_protocol = ENCRYP_PROTOCOL_WPA; - else { - if (bssid->Privacy) - encryp_protocol = ENCRYP_PROTOCOL_WEP; - } - - if (cur_network->BcnInfo.encryp_protocol != encryp_protocol) { - RTW_INFO("%s(): enctyp is not match\n", __func__); - goto _mismatch; - } - - if (encryp_protocol == ENCRYP_PROTOCOL_WPA || encryp_protocol == ENCRYP_PROTOCOL_WPA2) { - pbuf = rtw_get_wpa_ie(&bssid->IEs[12], &wpa_ielen, bssid->IELength - 12); - if (pbuf && (wpa_ielen > 0)) { - rtw_parse_wpa_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x); - } else { - pbuf = rtw_get_wpa2_ie(&bssid->IEs[12], &wpa_ielen, bssid->IELength - 12); - - if (pbuf && (wpa_ielen > 0)) { - rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x); - } - } - - if (pairwise_cipher != cur_network->BcnInfo.pairwise_cipher || group_cipher != cur_network->BcnInfo.group_cipher) { - RTW_INFO("%s pairwise_cipher(%x:%x) or group_cipher(%x:%x) is not match\n", __func__, - pairwise_cipher, cur_network->BcnInfo.pairwise_cipher, - group_cipher, cur_network->BcnInfo.group_cipher); - goto _mismatch; - } - - if (is_8021x != cur_network->BcnInfo.is_8021x) { - RTW_INFO("%s authentication is not match\n", __func__); - goto _mismatch; - } - } - - rtw_mfree((u8 *)bssid, sizeof(WLAN_BSSID_EX)); - return _SUCCESS; - -_mismatch: - rtw_mfree((u8 *)bssid, sizeof(WLAN_BSSID_EX)); - - if (pmlmepriv->NumOfBcnInfoChkFail == 0) - pmlmepriv->timeBcnInfoChkStart = rtw_get_current_time(); - - pmlmepriv->NumOfBcnInfoChkFail++; - RTW_INFO("%s by "ADPT_FMT" - NumOfChkFail = %d (SeqNum of this Beacon frame = %d).\n", __func__, ADPT_ARG(Adapter), pmlmepriv->NumOfBcnInfoChkFail, GetSequence(pframe)); - - if ((pmlmepriv->timeBcnInfoChkStart != 0) && (rtw_get_passing_time_ms(pmlmepriv->timeBcnInfoChkStart) <= DISCONNECT_BY_CHK_BCN_FAIL_OBSERV_PERIOD_IN_MS) - && (pmlmepriv->NumOfBcnInfoChkFail >= DISCONNECT_BY_CHK_BCN_FAIL_THRESHOLD)) { - RTW_INFO("%s by "ADPT_FMT" - NumOfChkFail = %d >= threshold : %d (in %d ms), return FAIL.\n", __func__, ADPT_ARG(Adapter), pmlmepriv->NumOfBcnInfoChkFail, - DISCONNECT_BY_CHK_BCN_FAIL_THRESHOLD, rtw_get_passing_time_ms(pmlmepriv->timeBcnInfoChkStart)); - pmlmepriv->timeBcnInfoChkStart = 0; - pmlmepriv->NumOfBcnInfoChkFail = 0; - return _FAIL; - } - - return _SUCCESS; -#endif } void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta) @@ -2749,26 +2717,23 @@ void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta } #ifdef CONFIG_DFS -void process_csa_ie(_adapter *padapter, u8 *pframe, uint pkt_len) +void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); unsigned int i; - unsigned int len; PNDIS_802_11_VARIABLE_IEs pIE; - u8 new_ch_no = 0; + u8 ch = 0; - if (padapter->mlmepriv.handle_dfs == _TRUE) + /* TODO: compare with scheduling CSA */ + if (rfctl->csa_ch) return; - len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN); - - for (i = 0; i < len;) { - pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i); + for (i = 0; i + 1 < ies_len;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(ies + i); switch (pIE->ElementID) { case _CH_SWTICH_ANNOUNCE_: - padapter->mlmepriv.handle_dfs = _TRUE; - _rtw_memcpy(&new_ch_no, pIE->data + 1, 1); - rtw_set_csa_cmd(padapter, new_ch_no); + ch = *(pIE->data + 1); break; default: break; @@ -2776,9 +2741,65 @@ void process_csa_ie(_adapter *padapter, u8 *pframe, uint pkt_len) i += (pIE->Length + 2); } + + if (ch != 0) { + rfctl->csa_ch = ch; + if (rtw_set_csa_cmd(padapter) != _SUCCESS) + rfctl->csa_ch = 0; + } } #endif /* CONFIG_DFS */ +void parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type) +{ + struct security_priv *psecuritypriv = &(padapter->securitypriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &(padapter->stapriv); + struct ieee802_1x_hdr *hdr; + struct wpa_eapol_key *key; + u16 key_info, key_data_length; + char *trx_msg = trx_type ? "send" : "recv"; + + hdr = (struct ieee802_1x_hdr *) key_payload; + + /* WPS - eapol start packet */ + if (hdr->type == 1 && hdr->length == 0) { + RTW_INFO("%s eapol start packet\n", trx_msg); + return; + } + + if (hdr->type == 0) { /* WPS - eapol packet */ + RTW_INFO("%s eapol packet\n", trx_msg); + return; + } + + key = (struct wpa_eapol_key *) (hdr + 1); + key_info = be16_to_cpu(*((u16 *)(key->key_info))); + key_data_length = be16_to_cpu(*((u16 *)(key->key_data_length))); + + if (!(key_info & WPA_KEY_INFO_KEY_TYPE)) { /* WPA group key handshake */ + if (key_info & WPA_KEY_INFO_ACK) { + RTW_PRINT("%s eapol packet - WPA Group Key 1/2\n", trx_msg); + } else { + RTW_PRINT("%s eapol packet - WPA Group Key 2/2\n", trx_msg); + + /* WPA key-handshake has completed */ + if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK) + psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE); + } + } else if (key_info & WPA_KEY_INFO_MIC) { + if (key_data_length == 0) + RTW_PRINT("%s eapol packet 4/4\n", trx_msg); + else if (key_info & WPA_KEY_INFO_ACK) + RTW_PRINT("%s eapol packet 3/4\n", trx_msg); + else + RTW_PRINT("%s eapol packet 2/4\n", trx_msg); + } else { + RTW_PRINT("%s eapol packet 1/4\n", trx_msg); + } + +} + unsigned int is_ap_in_tkip(_adapter *padapter) { u32 i; @@ -2988,13 +3009,27 @@ int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bw return _FAIL; } -unsigned char get_highest_rate_idx(u32 mask) +unsigned char get_highest_rate_idx(u64 mask) +{ + int i; + unsigned char rate_idx = 0; + + for (i = 63; i >= 0; i--) { + if ((mask >> i) & 0x01) { + rate_idx = i; + break; + } + } + + return rate_idx; +} +unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit) { int i; unsigned char rate_idx = 0; - for (i = 31; i >= 0; i--) { - if (mask & BIT(i)) { + for (i = start_bit; i < 64; i++) { + if ((mask >> i) & 0x01) { rate_idx = i; break; } @@ -3005,13 +3040,13 @@ unsigned char get_highest_rate_idx(u32 mask) void Update_RA_Entry(_adapter *padapter, struct sta_info *psta) { - rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); + rtw_hal_update_ra_mask(psta); } void set_sta_rate(_adapter *padapter, struct sta_info *psta) { /* rate adaptive */ - rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); + rtw_hal_update_ra_mask(psta); } /* Update RRSR and Rate for USERATE */ @@ -3129,6 +3164,78 @@ unsigned char check_assoc_AP(u8 *pframe, uint len) return HT_IOT_PEER_UNKNOWN; } +void get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor) +{ + switch (assoc_AP_vendor) { + + case HT_IOT_PEER_UNKNOWN: + sprintf(vendor, "%s", "unknown"); + break; + + case HT_IOT_PEER_REALTEK: + case HT_IOT_PEER_REALTEK_92SE: + case HT_IOT_PEER_REALTEK_SOFTAP: + case HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP: + case HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP: + + sprintf(vendor, "%s", "Realtek"); + break; + + case HT_IOT_PEER_BROADCOM: + sprintf(vendor, "%s", "Broadcom"); + break; + + case HT_IOT_PEER_MARVELL: + sprintf(vendor, "%s", "Marvell"); + break; + + case HT_IOT_PEER_RALINK: + sprintf(vendor, "%s", "Ralink"); + break; + + case HT_IOT_PEER_CISCO: + sprintf(vendor, "%s", "Cisco"); + break; + + case HT_IOT_PEER_AIRGO: + sprintf(vendor, "%s", "Airgo"); + break; + + case HT_IOT_PEER_ATHEROS: + sprintf(vendor, "%s", "Atheros"); + break; + + default: + sprintf(vendor, "%s", "unkown"); + break; + } + +} + +#ifdef CONFIG_80211AC_VHT +unsigned char get_vht_mu_bfer_cap(u8 *pframe, uint len) +{ + unsigned int i; + unsigned int mu_bfer=0; + PNDIS_802_11_VARIABLE_IEs pIE; + + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); + + switch (pIE->ElementID) { + + case EID_VHTCapability: + mu_bfer = GET_VHT_CAPABILITY_ELE_MU_BFER(pIE->data); + break; + default: + break; + } + i += (pIE->Length + 2); + } + return mu_bfer; +} +#endif + void update_capinfo(PADAPTER Adapter, u16 updateCap) { struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; @@ -3298,8 +3405,24 @@ void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode) int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num) { - u8 *ie; + u8 *ie, *p; unsigned int ie_len; + int i, j; + + struct support_rate_handler support_rate_tbl[] = { + {IEEE80211_CCK_RATE_1MB, _FALSE, _FALSE}, + {IEEE80211_CCK_RATE_2MB, _FALSE, _FALSE}, + {IEEE80211_CCK_RATE_5MB, _FALSE, _FALSE}, + {IEEE80211_CCK_RATE_11MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_6MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_9MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_12MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_18MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_24MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_36MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_48MB, _FALSE, _FALSE}, + {IEEE80211_OFDM_RATE_54MB, _FALSE, _FALSE}, + }; if (!rate_set || !rate_num) return _FALSE; @@ -3310,14 +3433,44 @@ int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num if (ie == NULL) goto ext_rate; - _rtw_memcpy(rate_set, ie + 2, ie_len); - *rate_num = ie_len; + /* get valid supported rates */ + for (i = 0; i < 12; i++) { + p = ie + 2; + for (j = 0; j < ie_len; j++) { + if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){ + support_rate_tbl[i].existence = _TRUE; + if ((*p) & BIT(7)) + support_rate_tbl[i].basic = _TRUE; + } + p++; + } + } ext_rate: ie = rtw_get_ie(ies, _EXT_SUPPORTEDRATES_IE_, &ie_len, ies_len); if (ie) { - _rtw_memcpy(rate_set + *rate_num, ie + 2, ie_len); - *rate_num += ie_len; + /* get valid extended supported rates */ + for (i = 0; i < 12; i++) { + p = ie + 2; + for (j = 0; j < ie_len; j++) { + if ((*p & ~BIT(7)) == support_rate_tbl[i].rate){ + support_rate_tbl[i].existence = _TRUE; + if ((*p) & BIT(7)) + support_rate_tbl[i].basic = _TRUE; + } + p++; + } + } + } + + for (i = 0; i < 12; i++){ + if (support_rate_tbl[i].existence){ + if (support_rate_tbl[i].basic) + rate_set[*rate_num] = support_rate_tbl[i].rate | IEEE80211_BASIC_RATE_MASK; + else + rate_set[*rate_num] = support_rate_tbl[i].rate; + *rate_num += 1; + } } if (*rate_num == 0) @@ -3339,8 +3492,6 @@ void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr) u16 tid, start_seq, param; struct sta_priv *pstapriv = &padapter->stapriv; struct ADDBA_request *preq = (struct ADDBA_request *)paddba_req; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u8 size, accept = _FALSE; psta = rtw_get_stainfo(pstapriv, addr); @@ -3370,6 +3521,32 @@ void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr) return; } +void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + struct sta_info *psta = NULL; + struct recv_reorder_ctrl *preorder_ctrl = NULL; + u8 tid = 0; + u16 start_seq=0; + + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta == NULL) + goto exit; + + tid = ((cpu_to_le16((*(u16 *)(pframe + 16))) & 0xf000) >> 12); + preorder_ctrl = &psta->recvreorder_ctrl[tid]; + start_seq = ((cpu_to_le16(*(u16 *)(pframe + 18))) >> 4); + preorder_ctrl->indicate_seq = start_seq; + + /* for Debug use */ + if (0) + RTW_INFO(FUNC_ADPT_FMT" tid=%d, start_seq=%d\n", FUNC_ADPT_ARG(padapter), tid, start_seq); + +exit: + return; +} + void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) { u8 *pIE; @@ -3385,109 +3562,45 @@ void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) pmlmeext->TSFValue |= le32_to_cpu(*pbuf); } -void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext) +void correct_TSF(_adapter *padapter, u8 mlme_state) { - rtw_hal_set_hwreg(padapter, HW_VAR_CORRECT_TSF, 0); + u8 m_state = mlme_state; + + rtw_hal_set_hwreg(padapter, HW_VAR_CORRECT_TSF, (u8 *)&m_state); } -void adaptive_early_32k(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) +#ifdef CONFIG_BCN_RECV_TIME +/* calculate beacon receiving time + 1.RxBCNTime(CCK_1M) = [192us(preamble)] + [length of beacon(byte)*8us] + [10us] + 2.RxBCNTime(OFDM_6M) = [8us(S) + 8us(L) + 4us(L-SIG)] + [(length of beacon(byte)/3 + 1] *4us] + [10us] +*/ +inline u16 _rx_bcn_time_calculate(uint bcn_len, u8 data_rate) { - int i; - u8 *pIE; - u32 *pbuf; - u64 tsf = 0; - u32 delay_ms; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - - pmlmeext->bcn_cnt++; - - pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - pbuf = (u32 *)pIE; - - tsf = le32_to_cpu(*(pbuf + 1)); - tsf = tsf << 32; - tsf |= le32_to_cpu(*pbuf); - - /* RTW_INFO("%s(): tsf_upper= 0x%08x, tsf_lower=0x%08x\n", __func__, (u32)(tsf>>32), (u32)tsf); */ - - /* delay = (timestamp mod 1024*100)/1000 (unit: ms) */ - /* delay_ms = do_div(tsf, (pmlmeinfo->bcn_interval*1024))/1000; */ - delay_ms = rtw_modular64(tsf, (pmlmeinfo->bcn_interval * 1024)); - delay_ms = delay_ms / 1000; - - if (delay_ms >= 8) { - pmlmeext->bcn_delay_cnt[8]++; - /* pmlmeext->bcn_delay_ratio[8] = (pmlmeext->bcn_delay_cnt[8] * 100) /pmlmeext->bcn_cnt; */ - } else { - pmlmeext->bcn_delay_cnt[delay_ms]++; - /* pmlmeext->bcn_delay_ratio[delay_ms] = (pmlmeext->bcn_delay_cnt[delay_ms] * 100) /pmlmeext->bcn_cnt; */ - } - - /* - RTW_INFO("%s(): (a)bcn_cnt = %d\n", __func__, pmlmeext->bcn_cnt); - - - for(i=0; i<9; i++) - { - RTW_INFO("%s():bcn_delay_cnt[%d]=%d, bcn_delay_ratio[%d]=%d\n", __func__, i, - pmlmeext->bcn_delay_cnt[i] , i, pmlmeext->bcn_delay_ratio[i]); - } - */ - - /* dump for adaptive_early_32k */ - if (pmlmeext->bcn_cnt > 100 && (pmlmeext->adaptive_tsf_done == _TRUE)) { - u8 ratio_20_delay, ratio_80_delay; - u8 DrvBcnEarly, DrvBcnTimeOut; - - ratio_20_delay = 0; - ratio_80_delay = 0; - DrvBcnEarly = 0xff; - DrvBcnTimeOut = 0xff; - - RTW_INFO("%s(): bcn_cnt = %d\n", __func__, pmlmeext->bcn_cnt); - - for (i = 0; i < 9; i++) { - pmlmeext->bcn_delay_ratio[i] = (pmlmeext->bcn_delay_cnt[i] * 100) / pmlmeext->bcn_cnt; - - - /* RTW_INFO("%s():bcn_delay_cnt[%d]=%d, bcn_delay_ratio[%d]=%d\n", __func__, i, */ - /* pmlmeext->bcn_delay_cnt[i] , i, pmlmeext->bcn_delay_ratio[i]); */ - - ratio_20_delay += pmlmeext->bcn_delay_ratio[i]; - ratio_80_delay += pmlmeext->bcn_delay_ratio[i]; - - if (ratio_20_delay > 20 && DrvBcnEarly == 0xff) { - DrvBcnEarly = i; - /* RTW_INFO("%s(): DrvBcnEarly = %d\n", __func__, DrvBcnEarly); */ - } - - if (ratio_80_delay > 80 && DrvBcnTimeOut == 0xff) { - DrvBcnTimeOut = i; - /* RTW_INFO("%s(): DrvBcnTimeOut = %d\n", __func__, DrvBcnTimeOut); */ - } - - /* reset adaptive_early_32k cnt */ - pmlmeext->bcn_delay_cnt[i] = 0; - pmlmeext->bcn_delay_ratio[i] = 0; - } - - pmlmeext->DrvBcnEarly = DrvBcnEarly; - pmlmeext->DrvBcnTimeOut = DrvBcnTimeOut; - - pmlmeext->bcn_cnt = 0; - } + u16 rx_bcn_time = 0;/*us*/ + if (data_rate == DESC_RATE1M) + rx_bcn_time = 192 + bcn_len * 8 + 10; + else if(data_rate == DESC_RATE6M) + rx_bcn_time = 8 + 8 + 4 + (bcn_len /3 + 1) * 4 + 10; +/* + else + RTW_ERR("%s invalid data rate(0x%02x)\n", __func__, data_rate); +*/ + return rx_bcn_time; } +void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + pmlmeext->bcn_rx_time = _rx_bcn_time_calculate(bcn_len, data_rate); +} +#endif void beacon_timing_control(_adapter *padapter) { rtw_hal_bcn_related_reg_setting(padapter); } -#define CONFIG_SHARED_BMC_MACID - void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num) { RTW_PRINT_SEL(sel, "0x%08x\n", map->m0); @@ -3547,22 +3660,6 @@ inline void rtw_macid_map_set(struct macid_bmp *map, u8 id) rtw_warn_on(1); } -/*Record bc's mac-id and sec-cam-id*/ -inline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - - macid_ctl->iface_bmc[padapter->iface_id] = mac_id; -} -inline u8 rtw_iface_bcmc_id_get(_adapter *padapter) -{ - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - - return macid_ctl->iface_bmc[padapter->iface_id]; -} - inline void rtw_macid_map_clr(struct macid_bmp *map, u8 id) { if (id < 32) @@ -3593,24 +3690,48 @@ inline bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id) return rtw_macid_is_set(&macid_ctl->bmc, id); } -inline s8 rtw_macid_get_if_g(struct macid_ctl_t *macid_ctl, u8 id) +inline u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id) { int i; + u8 iface_bmp = 0; -#ifdef CONFIG_SHARED_BMC_MACID - if (rtw_macid_is_bmc(macid_ctl, id)) { - for (i = 0; i < CONFIG_IFACE_NUMBER; i++) - if (macid_ctl->iface_bmc[i] == id) - return i; - return -1; + for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { + if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) + iface_bmp |= BIT(i); } -#endif + return iface_bmp; +} + +inline bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id) +{ + int i; + u8 iface_bmp = 0; for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { - if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) - return i; + if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) { + if (iface_bmp) + return 1; + iface_bmp |= BIT(i); + } } - return -1; + + return 0; +} + +inline bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter) +{ + int i; + u8 iface_bmp = 0; + + for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { + if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) { + if (iface_bmp || i != adapter->iface_id) + return 0; + iface_bmp |= BIT(i); + } + } + + return iface_bmp ? 1 : 0; } inline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id) @@ -3624,6 +3745,33 @@ inline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id) return -1; } +/*Record bc's mac-id and sec-cam-id*/ +inline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + macid_ctl->iface_bmc[padapter->iface_id] = mac_id; +} +inline u8 rtw_iface_bcmc_id_get(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + return macid_ctl->iface_bmc[padapter->iface_id]; +} +#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE) +void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); + int cam_id = -1; + + cam_id = rtw_iface_bcmc_id_get(adapter); + if (cam_id != INVALID_SEC_MAC_CAM_ID) + rtw_sec_cam_map_set(&cam_ctl->used, cam_id); +} +#endif void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta) { int i; @@ -3636,51 +3784,31 @@ void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta) u8 last_id = 0; u8 is_bc_sta = _FALSE; - if (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), ETH_ALEN)) { - psta->mac_id = macid_ctl->num; + if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)) { + psta->cmn.mac_id = macid_ctl->num; return; } - if (_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN)) { + if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) { is_bc_sta = _TRUE; rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); /*init default value*/ } -#ifdef CONFIG_SHARED_BMC_MACID if (is_bc_sta -#ifdef CONFIG_CONCURRENT_MODE - && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) || check_fwstate(&padapter->mlmepriv, WIFI_NULL_STATE)) -#endif - ) { - /* use shared broadcast & multicast macid 1 for all ifaces which configure to station mode*/ - _enter_critical_bh(&macid_ctl->lock, &irqL); - rtw_macid_map_set(used_map, 1); - rtw_macid_map_set(&macid_ctl->bmc, 1); - rtw_macid_map_set(&macid_ctl->if_g[padapter->iface_id], 1); - macid_ctl->sta[1] = psta; - /* TODO ch_g? */ - _exit_critical_bh(&macid_ctl->lock, &irqL); - i = 1; + #ifdef CONFIG_CONCURRENT_MODE + && (MLME_IS_STA(padapter) || MLME_IS_NULL(padapter)) + #endif + ) { + /* STA mode have no BMC data TX, shared with this macid */ + /* When non-concurrent, only one BMC data TX is used, shared with this macid */ + /* TODO: When concurrent, non-security BMC data TX may use this, but will not control by specific macid sleep */ + i = RTW_DEFAULT_MGMT_MACID; goto assigned; } -#endif - -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - if (MLME_IS_AP(padapter) || MLME_IS_GO(padapter)) - /* GO/AP assign client macid from 8 */ - last_id = 8; - } -#endif /* CONFIG_MCC_MODE */ _enter_critical_bh(&macid_ctl->lock, &irqL); for (i = last_id; i < macid_ctl->num; i++) { -#ifdef CONFIG_SHARED_BMC_MACID - if (i == 1) - continue; -#endif - #ifdef CONFIG_MCC_MODE /* macid 0/1 reserve for mcc for mgnt queue macid */ if (MCC_EN(padapter)) { @@ -3691,8 +3819,7 @@ void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta) } #endif /* CONFIG_MCC_MODE */ - if (is_bc_sta) {/*for SoftAP's Broadcast sta-info*/ - /*TODO:non-security AP may allociated macid = 1*/ + if (is_bc_sta) { struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); if ((!rtw_macid_is_used(macid_ctl, i)) && (!rtw_sec_camid_is_used(cam_ctl, i))) @@ -3727,18 +3854,18 @@ void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta) _exit_critical_bh(&macid_ctl->lock, &irqL); if (i >= macid_ctl->num) { - psta->mac_id = macid_ctl->num; - RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" no available macid\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr)); + psta->cmn.mac_id = macid_ctl->num; + RTW_ERR(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" no available macid\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr)); rtw_warn_on(1); goto exit; } else goto assigned; assigned: - psta->mac_id = i; - RTW_INFO(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" macid:%u\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id); + psta->cmn.mac_id = i; + RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); exit: return; @@ -3750,65 +3877,75 @@ void rtw_release_macid(_adapter *padapter, struct sta_info *psta) u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - u8 is_bc_sta = _FALSE; - - if (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), ETH_ALEN)) - return; - - if (_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN)) - is_bc_sta = _TRUE; + u8 ifbmp; + int i; -#ifdef CONFIG_SHARED_BMC_MACID - if (is_bc_sta -#ifdef CONFIG_CONCURRENT_MODE - && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) || check_fwstate(&padapter->mlmepriv, WIFI_NULL_STATE)) -#endif - ) - return; + if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)) + goto exit; - if (psta->mac_id == 1) { - RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" with macid:%u\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id); - if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) || check_fwstate(&padapter->mlmepriv, WIFI_NULL_STATE)) - rtw_warn_on(1); - return; + if (psta->cmn.mac_id >= macid_ctl->num) { + RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not valid\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 + , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); + rtw_warn_on(1); + goto exit; } -#endif + + if (psta->cmn.mac_id == RTW_DEFAULT_MGMT_MACID) + goto msg; _enter_critical_bh(&macid_ctl->lock, &irqL); - if (psta->mac_id < macid_ctl->num) { - int i; + if (!rtw_macid_is_used(macid_ctl, psta->cmn.mac_id)) { + RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 + , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); + _exit_critical_bh(&macid_ctl->lock, &irqL); + rtw_warn_on(1); + goto exit; + } - if (!rtw_macid_is_used(macid_ctl, psta->mac_id)) { - RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" macid:%u not used\n" - , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id); - rtw_warn_on(1); - } + ifbmp = rtw_macid_get_iface_bmp(macid_ctl, psta->cmn.mac_id); + if (!(ifbmp & BIT(padapter->iface_id))) { + RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used by self\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 + , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id); + _exit_critical_bh(&macid_ctl->lock, &irqL); + rtw_warn_on(1); + goto exit; + } - rtw_macid_map_clr(&macid_ctl->used, psta->mac_id); - rtw_macid_map_clr(&macid_ctl->bmc, psta->mac_id); + if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) { + struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); + u8 id = rtw_iface_bcmc_id_get(padapter); - if (is_bc_sta) { - struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); - u8 id = rtw_iface_bcmc_id_get(padapter); + if ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num)) + rtw_sec_cam_map_clr(&cam_ctl->used, id); - if ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num)) - rtw_sec_cam_map_clr(&cam_ctl->used, id); + rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); + } - rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); - } + rtw_macid_map_clr(&macid_ctl->if_g[padapter->iface_id], psta->cmn.mac_id); - for (i = 0; i < CONFIG_IFACE_NUMBER; i++) - rtw_macid_map_clr(&macid_ctl->if_g[i], psta->mac_id); + ifbmp &= ~BIT(padapter->iface_id); + if (!ifbmp) { /* only used by self */ + rtw_macid_map_clr(&macid_ctl->used, psta->cmn.mac_id); + rtw_macid_map_clr(&macid_ctl->bmc, psta->cmn.mac_id); for (i = 0; i < 2; i++) - rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->mac_id); - macid_ctl->sta[psta->mac_id] = NULL; + rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->cmn.mac_id); + macid_ctl->sta[psta->cmn.mac_id] = NULL; } _exit_critical_bh(&macid_ctl->lock, &irqL); - psta->mac_id = macid_ctl->num; +msg: + RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1 + , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id + ); + +exit: + psta->cmn.mac_id = macid_ctl->num; } /* For 8188E RA */ @@ -3893,8 +4030,31 @@ inline void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u3 RTW_INFO("macid:%u, rate_bmp1:0x%08X\n", id, macid_ctl->rate_bmp1[id]); } +inline void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3) +{ + macid_ctl->reg_sleep_m0 = m0; +#if (MACID_NUM_SW_LIMIT > 32) + macid_ctl->reg_sleep_m1 = m1; +#endif +#if (MACID_NUM_SW_LIMIT > 64) + macid_ctl->reg_sleep_m2 = m2; +#endif +#if (MACID_NUM_SW_LIMIT > 96) + macid_ctl->reg_sleep_m3 = m3; +#endif +} + inline void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl) { + int i; + u8 id = RTW_DEFAULT_MGMT_MACID; + + rtw_macid_map_set(&macid_ctl->used, id); + rtw_macid_map_set(&macid_ctl->bmc, id); + for (i = 0; i < CONFIG_IFACE_NUMBER; i++) + rtw_macid_map_set(&macid_ctl->if_g[i], id); + macid_ctl->sta[id] = NULL; + _rtw_spinlock_init(&macid_ctl->lock); } @@ -3903,6 +4063,87 @@ inline void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl) _rtw_spinlock_free(&macid_ctl->lock); } +inline bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id) +{ + if (id / 8 >= bmp_len) + return 0; + + return bmp[id / 8] & BIT(id % 8); +} + +inline void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id) +{ + if (id / 8 < bmp_len) + bmp[id / 8] |= BIT(id % 8); +} + +inline void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id) +{ + if (id / 8 < bmp_len) + bmp[id / 8] &= ~BIT(id % 8); +} + +inline bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len) +{ + int i; + + for (i = 0; i < bmp_len; i++) { + if (bmp[i]) + return 1; + } + + return 0; +} + +inline bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len) +{ + int i; + + for (i = 0; i < bmp_len; i++) { + if (i == 0) { + if (bmp[i] & 0xFE) + return 1; + } else { + if (bmp[i]) + return 1; + } + } + + return 0; +} + +#ifdef CONFIG_AP_MODE +/* Check the id be set or not in map , if yes , return a none zero value*/ +bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id) +{ + return rtw_bmp_is_set(map, padapter->stapriv.aid_bmp_len, id); +} + +/* Set the id into map array*/ +void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id) +{ + rtw_bmp_set(map, padapter->stapriv.aid_bmp_len, id); +} + +/* Clear the id from map array*/ +void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id) +{ + rtw_bmp_clear(map, padapter->stapriv.aid_bmp_len, id); +} + +/* Check have anyone bit be set , if yes return true*/ +bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map) +{ + return rtw_bmp_not_empty(map, padapter->stapriv.aid_bmp_len); +} + +/* Check have anyone bit be set exclude bit0 , if yes return true*/ +bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map) +{ + return rtw_bmp_not_empty_exclude_bit0(map, padapter->stapriv.aid_bmp_len); +} +#endif /* CONFIG_AP_MODE */ + #if 0 unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame) { @@ -4051,31 +4292,6 @@ _adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr) return adapter; } -#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip) -{ - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct in_device *my_ip_ptr = padapter->pnetdev->ip_ptr; - u8 ipaddress[4]; - - if ((pmlmeinfo->state & WIFI_FW_LINKING_STATE) || - pmlmeinfo->state & WIFI_FW_AP_STATE) { - if (my_ip_ptr != NULL) { - struct in_ifaddr *my_ifa_list = my_ip_ptr->ifa_list ; - if (my_ifa_list != NULL) { - ipaddress[0] = my_ifa_list->ifa_address & 0xFF; - ipaddress[1] = (my_ifa_list->ifa_address >> 8) & 0xFF; - ipaddress[2] = (my_ifa_list->ifa_address >> 16) & 0xFF; - ipaddress[3] = my_ifa_list->ifa_address >> 24; - RTW_INFO("%s: %d.%d.%d.%d ==========\n", __func__, - ipaddress[0], ipaddress[1], ipaddress[2], ipaddress[3]); - _rtw_memcpy(pcurrentip, ipaddress, 4); - } - } - } -} -#endif #ifdef CONFIG_WOWLAN bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern, int *pattern_len, char *bit_mask) @@ -4158,7 +4374,10 @@ void rtw_wow_pattern_sw_reset(_adapter *adapter) int i; struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter); - pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM; + if (pwrctrlpriv->default_patterns_en == _TRUE) + pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM; + else + pwrctrlpriv->wowlan_pattern_idx = 0; for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) { _rtw_memset(pwrctrlpriv->patterns[i].content, '\0', sizeof(pwrctrlpriv->patterns[i].content)); @@ -4170,19 +4389,22 @@ void rtw_wow_pattern_sw_reset(_adapter *adapter) u8 rtw_set_default_pattern(_adapter *adapter) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); - struct registry_priv *pregistrypriv = &adapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; u8 index = 0; - u8 currentip[4]; u8 multicast_addr[3] = {0x01, 0x00, 0x5e}; u8 multicast_ip[4] = {0xe0, 0x28, 0x28, 0x2a}; + u8 unicast_mask[5] = {0x3f, 0x70, 0x80, 0xc0, 0x03}; + u8 icmpv6_mask[7] = {0x00, 0x70, 0x10, 0x00, 0xc0, 0xc0, 0x3f}; u8 multicast_mask[5] = {0x07, 0x70, 0x80, 0xc0, 0x03}; + u8 ip_protocol[3] = {0x08, 0x00, 0x45}; - u8 icmp_protocol[1] = {0x01}; - u8 tcp_protocol[1] = {0x06}; - u8 udp_protocol[1] = {0x11}; + u8 ipv6_protocol[3] = {0x86, 0xdd, 0x60}; + + u8 *target = NULL; - if (pregistrypriv->default_patterns_en == _FALSE) + if (pwrpriv->default_patterns_en == _FALSE) return 0; for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) { @@ -4193,61 +4415,109 @@ u8 rtw_set_default_pattern(_adapter *adapter) pwrpriv->patterns[index].len = 0; } - rtw_get_current_ip_address(adapter, currentip); - /*TCP/ICMP unicast*/ for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) { switch (index) { case 0: - _rtw_memcpy(pwrpriv->patterns[index].content, - adapter_mac_addr(adapter), + target = pwrpriv->patterns[index].content; + _rtw_memcpy(target, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memcpy(pwrpriv->patterns[index].content + ETH_TYPE_OFFSET, - &ip_protocol, sizeof(ip_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + PROTOCOL_OFFSET, - &tcp_protocol, sizeof(tcp_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + IP_OFFSET, - ¤tip, sizeof(currentip)); + + target += ETH_TYPE_OFFSET; + _rtw_memcpy(target, &ip_protocol, + sizeof(ip_protocol)); + + /* TCP */ + target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); + _rtw_memset(target, 0x06, 1); + + target += (IP_OFFSET - PROTOCOL_OFFSET); + + _rtw_memcpy(target, pmlmeinfo->ip_addr, + RTW_IP_ADDR_LEN); + _rtw_memcpy(pwrpriv->patterns[index].mask, &unicast_mask, sizeof(unicast_mask)); - pwrpriv->patterns[index].len = IP_OFFSET + sizeof(currentip); + + pwrpriv->patterns[index].len = + IP_OFFSET + RTW_IP_ADDR_LEN; break; case 1: - _rtw_memcpy(pwrpriv->patterns[index].content, - adapter_mac_addr(adapter), + target = pwrpriv->patterns[index].content; + _rtw_memcpy(target, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memcpy(pwrpriv->patterns[index].content + ETH_TYPE_OFFSET, - &ip_protocol, sizeof(ip_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + PROTOCOL_OFFSET, - &icmp_protocol, sizeof(icmp_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + IP_OFFSET, - ¤tip, sizeof(currentip)); + + target += ETH_TYPE_OFFSET; + _rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol)); + + /* ICMP */ + target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); + _rtw_memset(target, 0x01, 1); + + target += (IP_OFFSET - PROTOCOL_OFFSET); + _rtw_memcpy(target, pmlmeinfo->ip_addr, + RTW_IP_ADDR_LEN); + _rtw_memcpy(pwrpriv->patterns[index].mask, &unicast_mask, sizeof(unicast_mask)); - pwrpriv->patterns[index].len = IP_OFFSET + sizeof(currentip); + pwrpriv->patterns[index].len = + + IP_OFFSET + RTW_IP_ADDR_LEN; break; +#ifdef CONFIG_IPV6 case 2: - _rtw_memcpy(pwrpriv->patterns[index].content, &multicast_addr, + if (pwrpriv->wowlan_ns_offload_en == _TRUE) { + target = pwrpriv->patterns[index].content; + target += ETH_TYPE_OFFSET; + + _rtw_memcpy(target, &ipv6_protocol, + sizeof(ipv6_protocol)); + + /* ICMPv6 */ + target += (IPv6_PROTOCOL_OFFSET - + ETH_TYPE_OFFSET); + _rtw_memset(target, 0x3a, 1); + + target += (IPv6_OFFSET - IPv6_PROTOCOL_OFFSET); + _rtw_memcpy(target, pmlmeinfo->ip6_addr, + RTW_IPv6_ADDR_LEN); + + _rtw_memcpy(pwrpriv->patterns[index].mask, + &icmpv6_mask, sizeof(icmpv6_mask)); + pwrpriv->patterns[index].len = + IPv6_OFFSET + RTW_IPv6_ADDR_LEN; + } + break; +#endif /*CONFIG_IPV6*/ + case 3: + target = pwrpriv->patterns[index].content; + _rtw_memcpy(target, &multicast_addr, sizeof(multicast_addr)); - _rtw_memcpy(pwrpriv->patterns[index].content + ETH_TYPE_OFFSET, - &ip_protocol, sizeof(ip_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + PROTOCOL_OFFSET, - &udp_protocol, sizeof(udp_protocol)); - _rtw_memcpy(pwrpriv->patterns[index].content + IP_OFFSET, - &multicast_ip, sizeof(multicast_ip)); + + target += ETH_TYPE_OFFSET; + _rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol)); + + /* UDP */ + target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET); + _rtw_memset(target, 0x11, 1); + + target += (IP_OFFSET - PROTOCOL_OFFSET); + _rtw_memcpy(target, &multicast_ip, + sizeof(multicast_ip)); + _rtw_memcpy(pwrpriv->patterns[index].mask, &multicast_mask, sizeof(multicast_mask)); + pwrpriv->patterns[index].len = IP_OFFSET + sizeof(multicast_ip); break; + default: + break; } } - return index; } - - void rtw_dump_priv_pattern(_adapter *adapter, u8 idx) { struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); @@ -4654,3 +4924,16 @@ void rtw_dev_pno_debug(struct net_device *net) } #endif /* CONFIG_PNO_SET_DEBUG */ #endif /* CONFIG_PNO_SUPPORT */ + +inline void rtw_collect_bcn_info(_adapter *adapter) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + + if (!is_client_associated_to_ap(adapter)) + return; + + pmlmeext->cur_bcn_cnt = pmlmeext->bcn_cnt - pmlmeext->last_bcn_cnt; + pmlmeext->last_bcn_cnt = pmlmeext->bcn_cnt; + /*TODO get offset of bcn's timestamp*/ + /*pmlmeext->bcn_timestamp;*/ +} diff --git a/core/rtw_xmit.c b/core/rtw_xmit.c index 9a72c7b..37aa432 100644 --- a/core/rtw_xmit.c +++ b/core/rtw_xmit.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTW_XMIT_C_ #include @@ -88,8 +83,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) _rtw_spinlock_init(&pxmitpriv->lock); _rtw_spinlock_init(&pxmitpriv->lock_sctx); _rtw_init_sema(&pxmitpriv->xmit_sema, 0); - /*_rtw_init_sema(&pxmitpriv->terminate_xmitthread_sema, 0);*/ - _rtw_init_completion(&pxmitpriv->xmitthread_comp); /* Please insert all the queue initializaiton using _rtw_init_queue below @@ -351,6 +344,9 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) pxmitpriv->amsdu_debug_timeout = 0; pxmitpriv->amsdu_debug_coalesce_one = 0; pxmitpriv->amsdu_debug_coalesce_two = 0; +#endif +#ifdef DBG_TXBD_DESC_DUMP + pxmitpriv->dump_txbd_desc = 0; #endif rtw_init_xmit_block(padapter); rtw_hal_init_xmit_priv(padapter); @@ -366,7 +362,6 @@ void rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv) { _rtw_spinlock_free(&pxmitpriv->lock); _rtw_free_sema(&pxmitpriv->xmit_sema); - /*_rtw_free_sema(&pxmitpriv->terminate_xmitthread_sema);*/ _rtw_spinlock_free(&pxmitpriv->be_pending.lock); _rtw_spinlock_free(&pxmitpriv->bk_pending.lock); @@ -461,7 +456,7 @@ u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta) { u8 bw; - bw = sta->bw_mode; + bw = sta->cmn.bw_mode; if (MLME_STATE(adapter) & WIFI_ASOC_STATE) { if (adapter->mlmeextpriv.cur_channel <= 14) bw = rtw_min(bw, ADAPTER_TX_BW_2G(adapter)); @@ -476,7 +471,6 @@ void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; u8 fix_bw = 0xFF; u16 bmp_cck_ofdm = 0; u32 bmp_ht = 0; @@ -491,7 +485,7 @@ void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ for (i = 0; i < macid_ctl->num; i++) { if (!rtw_macid_is_used(macid_ctl, i)) continue; - if (rtw_macid_get_if_g(macid_ctl, i) != adapter->iface_id) + if (!rtw_macid_is_iface_specific(macid_ctl, i, adapter)) continue; if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */ @@ -509,7 +503,6 @@ void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ /* TODO: mlmeext->tx_rate*/ -exit: if (r_bmp_cck_ofdm) *r_bmp_cck_ofdm = bmp_cck_ofdm; if (r_bmp_ht) @@ -529,7 +522,7 @@ void rtw_get_shared_macid_tx_rate_bmp_by_bw(struct dvobj_priv *dvobj, u8 bw, u16 for (i = 0; i < macid_ctl->num; i++) { if (!rtw_macid_is_used(macid_ctl, i)) continue; - if (rtw_macid_get_if_g(macid_ctl, i) != -1) + if (!rtw_macid_is_iface_shared(macid_ctl, i)) continue; if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */ @@ -885,6 +878,38 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf } +#ifdef CONFIG_WMMPS_STA +/* + * update_attrib_trigger_frame_info + * For Station mode, if a specific TID of driver setting and an AP support uapsd function, the data + * frame with corresponding TID will be a trigger frame when driver is in wmm power saving mode. + * + * Arguments: + * @padapter: _adapter pointer. + * @pattrib: pkt_attrib pointer. + * + * Auther: Arvin Liu + * Date: 2017/06/05 + */ +static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib) { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + u8 trigger_frame_en = 0; + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + if ((pwrpriv->pwr_mode == PS_MODE_MIN) || (pwrpriv->pwr_mode == PS_MODE_MAX)) { + if((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT(pattrib->priority)) == _TRUE)) { + trigger_frame_en = 1; + RTW_INFO("[WMMPS]"FUNC_ADPT_FMT": This is a Trigger Frame\n", FUNC_ADPT_ARG(padapter)); + } + } + } + + pattrib->trigger_frame = trigger_frame_en; +} +#endif /* CONFIG_WMMPS_STA */ + static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta) { struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; @@ -898,36 +923,38 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri pattrib->triggered = 0; pattrib->ampdu_spacing = 0; - /* qos_en, ht_en, init rate, ,bw, ch_offset, sgi */ - pattrib->qos_en = psta->qos_option; + /* ht_en, init rate, ,bw, ch_offset, sgi */ - pattrib->raid = psta->raid; + pattrib->raid = psta->cmn.ra_info.rate_id; bw = rtw_get_tx_bw_mode(padapter, psta); pattrib->bwmode = rtw_min(bw, mlmeext->cur_bwmode); pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode); - pattrib->ldpc = psta->ldpc; - pattrib->stbc = psta->stbc; + pattrib->ldpc = psta->cmn.ldpc_en; + pattrib->stbc = psta->cmn.stbc_en; #ifdef CONFIG_80211N_HT - pattrib->ht_en = psta->htpriv.ht_option; - pattrib->ch_offset = psta->htpriv.ch_offset; - pattrib->ampdu_en = _FALSE; + if(padapter->registrypriv.ht_enable && + is_supported_ht(padapter->registrypriv.wireless_mode)) { + pattrib->ht_en = psta->htpriv.ht_option; + pattrib->ch_offset = psta->htpriv.ch_offset; + pattrib->ampdu_en = _FALSE; - if (padapter->driver_ampdu_spacing != 0xFF) /* driver control AMPDU Density for peer sta's rx */ - pattrib->ampdu_spacing = padapter->driver_ampdu_spacing; - else - pattrib->ampdu_spacing = psta->htpriv.rx_ampdu_min_spacing; - - /* check if enable ampdu */ - if (pattrib->ht_en && psta->htpriv.ampdu_enable) { - if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) { - pattrib->ampdu_en = _TRUE; - if (psta->htpriv.tx_amsdu_enable == _TRUE) - pattrib->amsdu_ampdu_en = _TRUE; - else - pattrib->amsdu_ampdu_en = _FALSE; + if (padapter->driver_ampdu_spacing != 0xFF) /* driver control AMPDU Density for peer sta's rx */ + pattrib->ampdu_spacing = padapter->driver_ampdu_spacing; + else + pattrib->ampdu_spacing = psta->htpriv.rx_ampdu_min_spacing; + + /* check if enable ampdu */ + if (pattrib->ht_en && psta->htpriv.ampdu_enable) { + if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) { + pattrib->ampdu_en = _TRUE; + if (psta->htpriv.tx_amsdu_enable == _TRUE) + pattrib->amsdu_ampdu_en = _TRUE; + else + pattrib->amsdu_ampdu_en = _FALSE; + } } } #endif /* CONFIG_80211N_HT */ @@ -941,12 +968,15 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri if (pattrib->direct_link == _TRUE) { psta = pattrib->ptdls_sta; - pattrib->raid = psta->raid; + pattrib->raid = psta->cmn.ra_info.rate_id; #ifdef CONFIG_80211N_HT - pattrib->bwmode = rtw_get_tx_bw_mode(padapter, psta); - pattrib->ht_en = psta->htpriv.ht_option; - pattrib->ch_offset = psta->htpriv.ch_offset; - pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode); + if(padapter->registrypriv.ht_enable && + is_supported_ht(padapter->registrypriv.wireless_mode)) { + pattrib->bwmode = rtw_get_tx_bw_mode(padapter, psta); + pattrib->ht_en = psta->htpriv.ht_option; + pattrib->ch_offset = psta->htpriv.ch_offset; + pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode); + } #endif /* CONFIG_80211N_HT */ } #endif /* CONFIG_TDLS */ @@ -969,7 +999,7 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib _rtw_memset(pattrib->dot118021x_UncstKey.skey, 0, 16); _rtw_memset(pattrib->dot11tkiptxmickey.skey, 0, 16); - pattrib->mac_id = psta->mac_id; + pattrib->mac_id = psta->cmn.mac_id; if (psta->ieee8021x_blocked == _TRUE) { @@ -1158,6 +1188,11 @@ static void set_qos(struct pkt_file *ppktfile, struct pkt_attrib *pattrib) UserPriority = 7; } */ + + #ifdef CONFIG_ICMP_VOQ + if(pattrib->icmp_pkt==1)/*use VO queue to send icmp packet*/ + UserPriority = 7; + #endif pattrib->priority = UserPriority; pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN; pattrib->subtype = WIFI_QOS_DATA_TYPE; @@ -1213,7 +1248,7 @@ s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib) goto exit; } - pattrib->mac_id = psta->mac_id; + pattrib->mac_id = psta->cmn.mac_id; pattrib->psta = psta; pattrib->ack_policy = 0; /* get ether_hdr_len */ @@ -1246,18 +1281,49 @@ s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib) #endif /* CONFIG_TDLS */ -/*get non-qos hw_ssn control register,mapping to REG_HW_SEQ0,1,2,3*/ +/*get non-qos hw_ssn control register,mapping to REG_HW_SEQ 0,1,2,3*/ inline u8 rtw_get_hwseq_no(_adapter *padapter) { u8 hwseq_num = 0; + #ifdef CONFIG_CONCURRENT_MODE - if (padapter->adapter_type != PRIMARY_ADAPTER) + #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) + hwseq_num = padapter->iface_id; + if (hwseq_num > 3) + hwseq_num = 3; + #else + if (!is_primary_adapter(padapter)) hwseq_num = 1; - /* else */ - /* hwseq_num = 2; */ + #endif #endif /* CONFIG_CONCURRENT_MODE */ return hwseq_num; } +#ifdef CONFIG_LPS +#define LPS_PT_NORMAL 0 +#define LPS_PT_SP 1/* only DHCP packets is as SPECIAL_PACKET*/ +#define LPS_PT_ICMP 2 + +/*If EAPOL , ARP , OR DHCP packet, driver must be in active mode.*/ +static u8 _rtw_lps_chk_packet_type(struct pkt_attrib *pattrib) +{ + u8 pkt_type = LPS_PT_NORMAL; /*normal data frame*/ + + #ifdef CONFIG_WAPI_SUPPORT + if ((pattrib->ether_type == 0x88B4) || (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1)) + pkt_type = LPS_PT_SP; + #else /* !CONFIG_WAPI_SUPPORT */ + + #ifndef CONFIG_LPS_NOT_LEAVE_FOR_ICMP + if (pattrib->icmp_pkt == 1) + pkt_type = LPS_PT_ICMP; + else + #endif + if (pattrib->dhcp_pkt == 1) + pkt_type = LPS_PT_SP; + #endif + return pkt_type; +} +#endif static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib) { uint i; @@ -1267,12 +1333,13 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr sint bmcast; struct sta_priv *pstapriv = &padapter->stapriv; - struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct qos_priv *pqospriv = &pmlmepriv->qospriv; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; sint res = _SUCCESS; - +#ifdef CONFIG_LPS + u8 pkt_type = 0; +#endif DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib); @@ -1281,11 +1348,12 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr pattrib->ether_type = ntohs(etherhdr.h_proto); + if (MLME_IS_MESH(padapter)) /* address resolve is done for mesh */ + goto get_sta_info; _rtw_memcpy(pattrib->dst, ðerhdr.h_dest, ETH_ALEN); _rtw_memcpy(pattrib->src, ðerhdr.h_source, ETH_ALEN); - if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); @@ -1307,14 +1375,15 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr } else DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown); +get_sta_info: bmcast = IS_MCAST(pattrib->ra); if (bmcast) { psta = rtw_get_bcmc_stainfo(padapter); if (psta == NULL) { /* if we cannot get psta => drop the pkt */ DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta); -#ifdef DBG_TX_DROP_FRAME + #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); -#endif + #endif res = _FAIL; goto exit; } @@ -1322,9 +1391,9 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr psta = rtw_get_stainfo(pstapriv, pattrib->ra); if (psta == NULL) { /* if we cannot get psta => drop the pkt */ DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta); -#ifdef DBG_TX_DROP_FRAME + #ifdef DBG_TX_DROP_FRAME RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); -#endif + #endif res = _FAIL; goto exit; } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & _FW_LINKED)) { @@ -1336,7 +1405,8 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr if (!(psta->state & _FW_LINKED)) { DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link); - RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != _FW_LINKED\n", __func__, ADPT_ARG(padapter), MAC_ARG(psta->hwaddr), psta->state); + RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != _FW_LINKED\n", + __func__, ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state); res = _FAIL; goto exit; } @@ -1410,29 +1480,34 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr } } else if (0x888e == pattrib->ether_type) - RTW_PRINT("send eapol packet\n"); + parsing_eapol_packet(padapter, pktfile.cur_addr, psta, 1); +#ifdef DBG_ARP_DUMP + else if (pattrib->ether_type == ETH_P_ARP) { + u8 arp[28] = {0}; + + _rtw_pktfile_read(&pktfile, arp, 28); + dump_arp_pkt(RTW_DBGDUMP, etherhdr.h_dest, etherhdr.h_source, arp, 1); + } +#endif if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1)) rtw_mi_set_scan_deny(padapter, 3000); + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && + pattrib->ether_type == ETH_P_ARP && + !IS_MCAST(pattrib->dst)) { + rtw_mi_set_scan_deny(padapter, 1000); + rtw_mi_scan_abort(padapter, _FALSE); /*rtw_scan_abort_no_wait*/ + } + #ifdef CONFIG_LPS - /* If EAPOL , ARP , OR DHCP packet, driver must be in active mode. */ -#ifdef CONFIG_WAPI_SUPPORT - if ((pattrib->ether_type == 0x88B4) || (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1)) -#else /* !CONFIG_WAPI_SUPPORT */ -#if 0 - if ((pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1)) -#else /* only ICMP/DHCP packets is as SPECIAL_PACKET, and leave LPS when tx IMCP/DHCP packets. */ - /* if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) ) */ - if (pattrib->icmp_pkt == 1) - rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); - else if (pattrib->dhcp_pkt == 1) -#endif -#endif - { + pkt_type = _rtw_lps_chk_packet_type(pattrib); + + if (pkt_type == LPS_PT_SP) {/*packet is as SPECIAL_PACKET*/ DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_active); rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SPECIAL_PACKET, 1); - } + } else if (pkt_type == LPS_PT_ICMP) + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); #endif /* CONFIG_LPS */ #ifdef CONFIG_BEAMFORMING @@ -1446,26 +1521,24 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr goto exit; } - update_attrib_phy_info(padapter, pattrib, psta); - - /* RTW_INFO("%s ==> mac_id(%d)\n",__FUNCTION__,pattrib->mac_id ); */ - - pattrib->psta = psta; - /* TODO:_unlock */ - - pattrib->pctrl = 0; - - pattrib->ack_policy = 0; /* get ether_hdr_len */ pattrib->pkt_hdrlen = ETH_HLEN;/* (pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; */ /* vlan tag */ pattrib->hdrlen = WLAN_HDR_A3_LEN; pattrib->subtype = WIFI_DATA_TYPE; + pattrib->qos_en = psta->qos_option; pattrib->priority = 0; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { - if (pattrib->qos_en) + if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE + | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) + ) { + if (pattrib->qos_en) { set_qos(&pktfile, pattrib); + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_tx_set_whdr_mctrl_len(pattrib->mesh_frame_mode, pattrib); + #endif + } } else { #ifdef CONFIG_TDLS if (pattrib->direct_link == _TRUE) { @@ -1482,6 +1555,25 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr } } } + + update_attrib_phy_info(padapter, pattrib, psta); + + /* RTW_INFO("%s ==> mac_id(%d)\n",__FUNCTION__,pattrib->mac_id ); */ + + pattrib->psta = psta; + /* TODO:_unlock */ + + pattrib->pctrl = 0; + + pattrib->ack_policy = 0; + + if (bmcast) + pattrib->rate = psta->init_rate; + + +#ifdef CONFIG_WMMPS_STA + update_attrib_trigger_frame_info(padapter, pattrib); +#endif /* CONFIG_WMMPS_STA */ /* pattrib->priority = 5; */ /* force to used VI queue, for testing */ pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; @@ -1499,7 +1591,6 @@ static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe) u8 *pframe, *payload, mic[8]; struct mic_data micdata; /* struct sta_info *stainfo; */ - struct qos_priv *pqospriv = &(padapter->mlmepriv.qospriv); struct pkt_attrib *pattrib = &pxmitframe->attrib; struct security_priv *psecuritypriv = &padapter->securitypriv; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; @@ -1583,7 +1674,6 @@ static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe) } - /* if(pqospriv->qos_option==1) */ if (pattrib->qos_en) priority[0] = (u8)pxmitframe->attrib.priority; @@ -1744,6 +1834,17 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) if (pattrib->qos_en) qos_option = _TRUE; +#ifdef CONFIG_RTW_MESH + } else if (check_fwstate(pmlmepriv, WIFI_MESH_STATE) == _TRUE) { + rtw_mesh_tx_build_whdr(padapter, pattrib, fctrl, pwlanhdr); + if (pattrib->qos_en) + qos_option = _TRUE; + else { + RTW_WARN("[%s] !qos_en in Mesh\n", __FUNCTION__); + res = _FAIL; + goto exit; + } +#endif } else { res = _FAIL; goto exit; @@ -1767,6 +1868,18 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) if(pattrib->amsdu) SetAMsdu(qc, pattrib->amsdu); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* active: don't care, light sleep: 0, deep sleep: 1*/ + set_mps_lv(qc, 0); //TBD + + /* TBD: temporary set (rspi, eosp) = (0, 1) which means End MPSP */ + set_rspi(qc, 0); + SetEOSP(qc, 1); + + set_mctrl_present(qc, 1); + } +#endif } /* TODO: fill HT Control Field */ @@ -1911,37 +2024,53 @@ s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib) int rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) { + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_info *ptdls_sta = NULL; int res = _SUCCESS; + ptdls_sta = rtw_get_stainfo((&padapter->stapriv), pattrib->dst); + if (ptdls_sta == NULL) { + switch (ptxmgmt->action_code) { + case TDLS_DISCOVERY_REQUEST: + case TUNNELED_PROBE_REQ: + case TUNNELED_PROBE_RSP: + break; + default: + RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(pattrib->dst), ptxmgmt->action_code); + res = _FAIL; + goto exit; + } + } + switch (ptxmgmt->action_code) { case TDLS_SETUP_REQUEST: - rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; case TDLS_SETUP_RESPONSE: - rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; case TDLS_SETUP_CONFIRM: - rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; case TDLS_TEARDOWN: - rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; case TDLS_DISCOVERY_REQUEST: rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe, ptxmgmt); break; case TDLS_PEER_TRAFFIC_INDICATION: - rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; #ifdef CONFIG_TDLS_CH_SW case TDLS_CHANNEL_SWITCH_REQUEST: - rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; case TDLS_CHANNEL_SWITCH_RESPONSE: - rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; #endif case TDLS_PEER_TRAFFIC_RESPONSE: - rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt); + rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta); break; #ifdef CONFIG_WFD case TUNNELED_PROBE_REQ: @@ -1956,6 +2085,7 @@ int rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pf break; } +exit: return res; } @@ -2046,7 +2176,7 @@ s32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattr pattrib->icv_len = 8; pattrib->bswenc = _FALSE; } - pattrib->mac_id = ptdls_sta->mac_id; + pattrib->mac_id = ptdls_sta->cmn.mac_id; } else { res = _FAIL; goto exit; @@ -2180,12 +2310,14 @@ u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib) { u32 len = 0; - len = pattrib->hdrlen + pattrib->iv_len; /* WLAN Header and IV */ - len += SNAP_SIZE + sizeof(u16); /* LLC */ - len += pattrib->pktlen; - if (pattrib->encrypt == _TKIP_) - len += 8; /* MIC */ - len += ((pattrib->bswenc) ? pattrib->icv_len : 0); /* ICV */ + len = pattrib->hdrlen /* WLAN Header */ + + pattrib->iv_len /* IV */ + + XATTRIB_GET_MCTRL_LEN(pattrib) + + SNAP_SIZE + sizeof(u16) /* LLC */ + + pattrib->pktlen + + (pattrib->encrypt == _TKIP_ ? 8 : 0) /* MIC */ + + (pattrib->bswenc ? pattrib->icv_len : 0) /* ICV */ + ; return len; } @@ -2218,6 +2350,9 @@ s32 check_amsdu(struct xmit_frame *pxmitframe) if (!pattrib->qos_en) ret = _FALSE; + if (IS_AMSDU_AMPDU_NOT_VALID(pattrib)) + ret = _FALSE; + return ret; } @@ -2291,7 +2426,6 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra pattrib->amsdu = 1; if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n")); RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n"); res = _FAIL; goto exit; @@ -2310,9 +2444,8 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra if (pattrib->iv_len) { _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); // queue or new? - RT_TRACE(_module_rtl871x_xmit_c_, _drv_notice_, - ("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n", - padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3))); + RTW_DBG("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n", + padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3)); pframe += pattrib->iv_len; } @@ -2327,16 +2460,28 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra _rtw_open_pktfile(pkt_queue, &pktfile_queue); _rtw_pktfile_read(&pktfile_queue, NULL, pattrib_queue->pkt_hdrlen); - /* 802.3 MAC Header DA(6) SA(6) Len(2)*/ - - _rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN); - pframe += ETH_ALEN; - - _rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN); - pframe += ETH_ALEN; - - len = (u16*) pframe; - pframe += 2; + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* mDA(6), mSA(6), len(2), mctrl */ + _rtw_memcpy(pframe, pattrib_queue->mda, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib_queue->msa, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16*)pframe; + pframe += 2; + rtw_mesh_tx_build_mctrl(padapter, pattrib_queue, pframe); + pframe += XATTRIB_GET_MCTRL_LEN(pattrib_queue); + } else + #endif + { + /* 802.3 MAC Header DA(6) SA(6) Len(2)*/ + _rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16*)pframe; + pframe += 2; + } llc_sz = rtw_put_snap(pframe, pattrib_queue->ether_type); pframe += llc_sz; @@ -2344,17 +2489,17 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra mem_sz = _rtw_pktfile_read(&pktfile_queue, pframe, pattrib_queue->pktlen); pframe += mem_sz; - *len = htons(llc_sz + mem_sz); + *len = htons(XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz); //calc padding - padding = 4 - ((ETH_HLEN + llc_sz + mem_sz) & (4-1)); + padding = 4 - ((ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz) & (4-1)); if(padding == 4) padding = 0; //_rtw_memset(pframe,0xaa, padding); pframe += padding; - pattrib->last_txcmdsz += ETH_HLEN + llc_sz + mem_sz + padding ; + pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz + padding ; } //2nd mpdu @@ -2363,16 +2508,28 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra _rtw_open_pktfile(pkt, &pktfile); _rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen); - /* 802.3 MAC Header DA(6) SA(6) Len(2) */ - - _rtw_memcpy(pframe, pattrib->dst, ETH_ALEN); - pframe += ETH_ALEN; - - _rtw_memcpy(pframe, pattrib->src, ETH_ALEN); - pframe += ETH_ALEN; - - len = (u16*) pframe; - pframe += 2; +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + /* mDA(6), mSA(6), len(2), mctrl */ + _rtw_memcpy(pframe, pattrib->mda, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib->msa, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16*)pframe; + pframe += 2; + rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe); + pframe += XATTRIB_GET_MCTRL_LEN(pattrib); + } else +#endif + { + /* 802.3 MAC Header DA(6) SA(6) Len(2) */ + _rtw_memcpy(pframe, pattrib->dst, ETH_ALEN); + pframe += ETH_ALEN; + _rtw_memcpy(pframe, pattrib->src, ETH_ALEN); + pframe += ETH_ALEN; + len = (u16*)pframe; + pframe += 2; + } llc_sz = rtw_put_snap(pframe, pattrib->ether_type); pframe += llc_sz; @@ -2381,14 +2538,14 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra pframe += mem_sz; - *len = htons(llc_sz + mem_sz); + *len = htons(XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz); //the last ampdu has no padding padding = 0; pattrib->nr_frags = 1; - pattrib->last_txcmdsz += ETH_HLEN + llc_sz + mem_sz + padding + + pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz + padding + ((pattrib->bswenc) ? pattrib->icv_len : 0) ; if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { @@ -2397,7 +2554,6 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra } if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) { - RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n")); RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"); res = _FAIL; goto exit; @@ -2405,7 +2561,7 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra xmitframe_swencrypt(padapter, pxmitframe); - pattrib->vcs_mode = NONE_VCS; + update_attrib_vcs_info(padapter, pxmitframe); exit: return res; @@ -2558,6 +2714,14 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm } if (frg_inx == 0) { + #ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe); + pframe += XATTRIB_GET_MCTRL_LEN(pattrib); + mpdu_len -= XATTRIB_GET_MCTRL_LEN(pattrib); + } + #endif + llc_sz = rtw_put_snap(pframe, pattrib->ether_type); pframe += llc_sz; mpdu_len -= llc_sz; @@ -2585,7 +2749,8 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) { pattrib->nr_frags = frg_inx; - pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + ((pattrib->nr_frags == 1) ? llc_sz : 0) + + pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + + ((pattrib->nr_frags == 1) ? (XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz) : 0) + ((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz; ClearMFrag(mem_start); @@ -2619,15 +2784,23 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm return res; } -#ifdef CONFIG_IEEE80211W -/* broadcast or multicast management pkt use BIP, unicast management pkt use CCMP encryption */ +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) +/* + * CCMP encryption for unicast robust mgmt frame and broadcast group privicy action + * BIP for broadcast robust mgmt frame + */ s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe) { +#define DBG_MGMT_XMIT_COALESEC_DUMP 0 +#define DBG_MGMT_XMIT_BIP_DUMP 0 +#define DBG_MGMT_XMIT_ENC_DUMP 0 + struct pkt_file pktfile; s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; SIZE_PTR addr; u8 *pframe, *mem_start = NULL, *tmp_buf = NULL; u8 hw_hdr_offset, subtype ; + u8 category = 0xFF; struct sta_info *psta = NULL; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct pkt_attrib *pattrib = &pxmitframe->attrib; @@ -2644,205 +2817,282 @@ s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame _irqL irqL; u32 ori_len; + union pn48 *pn = NULL; + u8 kid; + + if (pxmitframe->buf_addr == NULL) { + RTW_WARN(FUNC_ADPT_FMT" pxmitframe->buf_addr\n" + , FUNC_ADPT_ARG(padapter)); + return _FAIL; + } + mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET; pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ + + /* check if robust mgmt frame */ + if (subtype != WIFI_DEAUTH && subtype != WIFI_DISASSOC && subtype != WIFI_ACTION) + return _SUCCESS; + if (subtype == WIFI_ACTION) { + category = *(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + if (CATEGORY_IS_NON_ROBUST(category)) + return _SUCCESS; + } + if (!bmcst) { + if (pattrib->psta) + psta = pattrib->psta; + else + pattrib->psta = psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if (psta == NULL) { + RTW_INFO(FUNC_ADPT_FMT" unicast sta == NULL\n", FUNC_ADPT_ARG(padapter)); + return _FAIL; + } + if (!(psta->flags & WLAN_STA_MFP)) { + /* peer is not MFP capable, no need to encrypt */ + return _SUCCESS; + } + if (psta->bpairwise_key_installed != _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" PTK is not installed\n" + , FUNC_ADPT_ARG(padapter)); + return _FAIL; + } + } ori_len = BIP_AAD_SIZE + pattrib->pktlen; tmp_buf = BIP_AAD = rtw_zmalloc(ori_len); - subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ - if (BIP_AAD == NULL) return _FAIL; _enter_critical_bh(&padapter->security_key_mutex, &irqL); - - /* IGTK key is not install, it may not support 802.11w */ - if (padapter->securitypriv.binstallBIPkey != _TRUE) { - RTW_INFO("no instll BIP key\n"); - goto xmitframe_coalesce_success; - } - /* station mode doesn't need TX BIP, just ready the code */ if (bmcst) { - int frame_body_len; - u8 mic[16]; - - _rtw_memset(MME, 0, _MME_IE_LENGTH_); - - /* other types doesn't need the BIP */ - if (get_frame_sub_type(pframe) != WIFI_DEAUTH && get_frame_sub_type(pframe) != WIFI_DISASSOC) - goto xmitframe_coalesce_fail; - - MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - pframe += pattrib->pktlen; - - /* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */ - MME[0] = padapter->securitypriv.dot11wBIPKeyid; - /* copy packet number */ - _rtw_memcpy(&MME[2], &pmlmeext->mgnt_80211w_IPN, 6); - /* increase the packet number */ - pmlmeext->mgnt_80211w_IPN++; - - /* add MME IE with MIC all zero, MME string doesn't include element id and length */ - pframe = rtw_set_ie(pframe, _MME_IE_ , 16 , MME, &(pattrib->pktlen)); - pattrib->last_txcmdsz = pattrib->pktlen; - /* total frame length - header length */ - frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr); - - /* conscruct AAD, copy frame control field */ - _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); - ClearRetry(BIP_AAD); - ClearPwrMgt(BIP_AAD); - ClearMData(BIP_AAD); - /* conscruct AAD, copy address 1 to address 3 */ - _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18); - /* copy management fram body */ - _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len); -#if 0 - /* dump total packet include MME with zero MIC */ - { - int i; - printk("Total packet: "); - for (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++) - printk(" %02x ", BIP_AAD[i]); - printk("\n"); - } -#endif - /* calculate mic */ - if (omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey - , BIP_AAD, BIP_AAD_SIZE + frame_body_len, mic)) - goto xmitframe_coalesce_fail; + if (subtype == WIFI_ACTION && CATEGORY_IS_GROUP_PRIVACY(category)) { + /* broadcast group privacy action frame */ + #if DBG_MGMT_XMIT_COALESEC_DUMP + RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u)\n" + , FUNC_ADPT_ARG(padapter), category); + #endif -#if 0 - /* dump calculated mic result */ - { - int i; - printk("Calculated mic result: "); - for (i = 0; i < 16; i++) - printk(" %02x ", mic[i]); - printk("\n"); - } -#endif - /* copy right BIP mic value, total is 128bits, we use the 0~63 bits */ - _rtw_memcpy(pframe - 8, mic, 8); - /*/dump all packet after mic ok - { - int pp; - printk("pattrib->pktlen = %d\n", pattrib->pktlen); - for(pp=0;pp< pattrib->pktlen; pp++) - printk(" %02x ", mem_start[pp]); - printk("\n"); - }*/ - } else { /* unicast mgmt frame TX */ - /* start to encrypt mgmt frame */ - if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || - subtype == WIFI_REASSOCREQ || subtype == WIFI_ACTION) { if (pattrib->psta) psta = pattrib->psta; else - psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); - + pattrib->psta = psta = rtw_get_bcmc_stainfo(padapter); if (psta == NULL) { - - RTW_INFO("%s, psta==NUL\n", __func__); + RTW_INFO(FUNC_ADPT_FMT" broadcast sta == NULL\n" + , FUNC_ADPT_ARG(padapter)); goto xmitframe_coalesce_fail; } - - if (pxmitframe->buf_addr == NULL) { - RTW_INFO("%s, pxmitframe->buf_addr\n", __func__); + if (padapter->securitypriv.binstallGrpkey != _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" GTK is not installed\n" + , FUNC_ADPT_ARG(padapter)); goto xmitframe_coalesce_fail; } - /* RTW_INFO("%s, action frame category=%d\n", __func__, pframe[WLAN_HDR_A3_LEN]); */ - /* according 802.11-2012 standard, these five types are not robust types */ - if (subtype == WIFI_ACTION && - (pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_PUBLIC || - pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_HT || - pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_UNPROTECTED_WNM || - pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_SELF_PROTECTED || - pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_P2P)) - goto xmitframe_coalesce_fail; - /* before encrypt dump the management packet content */ - /*{ - int i; - printk("Management pkt: "); - for(i=0; ipktlen; i++) - printk(" %02x ", pframe[i]); - printk("=======\n"); - }*/ - if (pattrib->encrypt > 0) - _rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16); - - /* To use wrong key */ - if (pattrib->key_type == IEEE80211W_WRONG_KEY) { - RTW_INFO("use wrong key\n"); - pattrib->dot118021x_UncstKey.skey[0] = 0xff; + pn = &psta->dot11txpn; + kid = padapter->securitypriv.dot118021XGrpKeyid; + } else { + #ifdef CONFIG_IEEE80211W + /* broadcast robust mgmt frame, using BIP */ + int frame_body_len; + u8 mic[16]; + + /* IGTK key is not install ex: mesh MFP without IGTK */ + if (SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) != _TRUE) + goto xmitframe_coalesce_success; + + #if DBG_MGMT_XMIT_COALESEC_DUMP + if (subtype == WIFI_DEAUTH) + RTW_INFO(FUNC_ADPT_FMT" braodcast deauth\n", FUNC_ADPT_ARG(padapter)); + else if (subtype == WIFI_DISASSOC) + RTW_INFO(FUNC_ADPT_FMT" braodcast disassoc\n", FUNC_ADPT_ARG(padapter)); + else if (subtype == WIFI_ACTION) { + RTW_INFO(FUNC_ADPT_FMT" braodcast action(%u)\n" + , FUNC_ADPT_ARG(padapter), category); } + #endif - /* bakeup original management packet */ - _rtw_memcpy(tmp_buf, pframe, pattrib->pktlen); - /* move to data portion */ - pframe += pattrib->hdrlen; + _rtw_memset(MME, 0, _MME_IE_LENGTH_); - /* 802.11w unicast management packet must be _AES_ */ - pattrib->iv_len = 8; - /* it's MIC of AES */ - pattrib->icv_len = 8; + MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + pframe += pattrib->pktlen; - switch (pattrib->encrypt) { - case _AES_: - /* set AES IV header */ - AES_IV(pattrib->iv, psta->dot11wtxpn, 0); - break; - default: - goto xmitframe_coalesce_fail; - } - /* insert iv header into management frame */ - _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); - pframe += pattrib->iv_len; - /* copy mgmt data portion after CCMP header */ - _rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen); - /* move pframe to end of mgmt pkt */ - pframe += pattrib->pktlen - pattrib->hdrlen; - /* add 8 bytes CCMP IV header to length */ - pattrib->pktlen += pattrib->iv_len; -#if 0 - /* dump management packet include AES IV header */ + /* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */ + MME[0] = padapter->securitypriv.dot11wBIPKeyid; + /* increase PN and apply to packet */ + padapter->securitypriv.dot11wBIPtxpn.val++; + RTW_PUT_LE64(&MME[2], padapter->securitypriv.dot11wBIPtxpn.val); + + /* add MME IE with MIC all zero, MME string doesn't include element id and length */ + pframe = rtw_set_ie(pframe, _MME_IE_ , 16 , MME, &(pattrib->pktlen)); + pattrib->last_txcmdsz = pattrib->pktlen; + /* total frame length - header length */ + frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr); + + /* conscruct AAD, copy frame control field */ + _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); + ClearRetry(BIP_AAD); + ClearPwrMgt(BIP_AAD); + ClearMData(BIP_AAD); + /* conscruct AAD, copy address 1 to address 3 */ + _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18); + /* copy management fram body */ + _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len); + + #if DBG_MGMT_XMIT_BIP_DUMP + /* dump total packet include MME with zero MIC */ { int i; - printk("Management pkt + IV: "); - /* for(i=0; ipktlen; i++) */ - - printk("@@@@@@@@@@@@@\n"); + printk("Total packet: "); + for (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++) + printk(" %02x ", BIP_AAD[i]); + printk("\n"); } -#endif + #endif - if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { - _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); - pframe += pattrib->icv_len; - } - /* add 8 bytes MIC */ - pattrib->pktlen += pattrib->icv_len; - /* set final tx command size */ - pattrib->last_txcmdsz = pattrib->pktlen; + /* calculate mic */ + if (omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey + , BIP_AAD, BIP_AAD_SIZE + frame_body_len, mic)) + goto xmitframe_coalesce_fail; - /* set protected bit must be beofre SW encrypt */ - SetPrivacy(mem_start); -#if 0 - /* dump management packet include AES header */ + #if DBG_MGMT_XMIT_BIP_DUMP + /* dump calculated mic result */ { int i; - printk("prepare to enc Management pkt + IV: "); - for (i = 0; i < pattrib->pktlen; i++) - printk(" %02x ", mem_start[i]); - printk("@@@@@@@@@@@@@\n"); + printk("Calculated mic result: "); + for (i = 0; i < 16; i++) + printk(" %02x ", mic[i]); + printk("\n"); } -#endif - /* software encrypt */ - xmitframe_swencrypt(padapter, pxmitframe); + #endif + + /* copy right BIP mic value, total is 128bits, we use the 0~63 bits */ + _rtw_memcpy(pframe - 8, mic, 8); + + #if DBG_MGMT_XMIT_BIP_DUMP + /*dump all packet after mic ok */ + { + int pp; + printk("pattrib->pktlen = %d\n", pattrib->pktlen); + for(pp=0;pp< pattrib->pktlen; pp++) + printk(" %02x ", mem_start[pp]); + printk("\n"); + } + #endif + + #endif /* CONFIG_IEEE80211W */ + + goto xmitframe_coalesce_success; + } + } + else { + /* unicast robust mgmt frame */ + #if DBG_MGMT_XMIT_COALESEC_DUMP + if (subtype == WIFI_DEAUTH) { + RTW_INFO(FUNC_ADPT_FMT" unicast deauth to "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra)); + } else if (subtype == WIFI_DISASSOC) { + RTW_INFO(FUNC_ADPT_FMT" unicast disassoc to "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra)); + } else if (subtype == WIFI_ACTION) { + RTW_INFO(FUNC_ADPT_FMT" unicast action(%u) to "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), category, MAC_ARG(pattrib->ra)); + } + #endif + + _rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16); + + /* To use wrong key */ + if (pattrib->key_type == IEEE80211W_WRONG_KEY) { + RTW_INFO("use wrong key\n"); + pattrib->dot118021x_UncstKey.skey[0] = 0xff; } + + pn = &psta->dot11txpn; + kid = 0; } + #if DBG_MGMT_XMIT_ENC_DUMP + /* before encrypt dump the management packet content */ + { + int i; + printk("Management pkt: "); + for(i=0; ipktlen; i++) + printk(" %02x ", pframe[i]); + printk("=======\n"); + } + #endif + + /* bakeup original management packet */ + _rtw_memcpy(tmp_buf, pframe, pattrib->pktlen); + /* move to data portion */ + pframe += pattrib->hdrlen; + + /* 802.11w encrypted management packet must be _AES_ */ + if (pattrib->key_type != IEEE80211W_NO_KEY) { + pattrib->encrypt = _AES_; + pattrib->bswenc = _TRUE; + } + + pattrib->iv_len = 8; + /* it's MIC of AES */ + pattrib->icv_len = 8; + + switch (pattrib->encrypt) { + case _AES_: + /* set AES IV header */ + AES_IV(pattrib->iv, (*pn), kid); + break; + default: + goto xmitframe_coalesce_fail; + } + + /* insert iv header into management frame */ + _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); + pframe += pattrib->iv_len; + /* copy mgmt data portion after CCMP header */ + _rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen); + /* move pframe to end of mgmt pkt */ + pframe += pattrib->pktlen - pattrib->hdrlen; + /* add 8 bytes CCMP IV header to length */ + pattrib->pktlen += pattrib->iv_len; + + #if DBG_MGMT_XMIT_ENC_DUMP + /* dump management packet include AES IV header */ + { + int i; + printk("Management pkt + IV: "); + /* for(i=0; ipktlen; i++) */ + + printk("@@@@@@@@@@@@@\n"); + } + #endif + + if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { + _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); + pframe += pattrib->icv_len; + } + /* add 8 bytes MIC */ + pattrib->pktlen += pattrib->icv_len; + /* set final tx command size */ + pattrib->last_txcmdsz = pattrib->pktlen; + + /* set protected bit must be beofre SW encrypt */ + SetPrivacy(mem_start); + + #if DBG_MGMT_XMIT_ENC_DUMP + /* dump management packet include AES header */ + { + int i; + printk("prepare to enc Management pkt + IV: "); + for (i = 0; i < pattrib->pktlen; i++) + printk(" %02x ", mem_start[i]); + printk("@@@@@@@@@@@@@\n"); + } + #endif + + /* software encrypt */ + xmitframe_swencrypt(padapter, pxmitframe); + xmitframe_coalesce_success: _exit_critical_bh(&padapter->security_key_mutex, &irqL); rtw_mfree(BIP_AAD, ori_len); @@ -2854,7 +3104,7 @@ s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame return _FAIL; } -#endif /* CONFIG_IEEE80211W */ +#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */ /* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header * IEEE LLC/SNAP header contains 8 octets @@ -2955,18 +3205,15 @@ void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, int sz pstats->tx_pkts += pkt_num; pstats->tx_bytes += sz; -#ifdef CONFIG_TDLS - if (pxmitframe->attrib.ptdls_sta != NULL) { - pstats = &(pxmitframe->attrib.ptdls_sta->sta_stats); - pstats->tx_pkts += pkt_num; - pstats->tx_bytes += sz; - } -#endif /* CONFIG_TDLS */ + #if defined(CONFIG_CHECK_LEAVE_LPS) && defined(CONFIG_LPS_CHK_BY_TP) + if (adapter_to_pwrctl(padapter)->lps_chk_by_tp) + traffic_check_for_leave_lps_by_tp(padapter, _TRUE, psta); + #endif /* CONFIG_LPS */ } #ifdef CONFIG_CHECK_LEAVE_LPS /* traffic_check_for_leave_lps(padapter, _TRUE); */ -#endif /* CONFIG_LPS */ +#endif /* CONFIG_CHECK_LEAVE_LPS */ } } @@ -3003,9 +3250,6 @@ static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv, } else RTW_INFO("%s fail, no xmitbuf available !!!\n", __func__); -exit: - - return pxmitbuf; } @@ -3035,7 +3279,7 @@ struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, pcmdframe->buf_addr = pxmitbuf->pbuf; /* initial memory to zero */ - _rtw_memset(pcmdframe->buf_addr, 0, pxmitbuf->alloc_sz); + _rtw_memset(pcmdframe->buf_addr, 0, MAX_CMDBUF_SZ); pxmitbuf->priv_data = pcmdframe; @@ -3536,10 +3780,6 @@ struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame) struct registry_priv *pregpriv = &padapter->registrypriv; int i, inx[4]; -#ifdef CONFIG_USB_HCI - /* int j, tmp, acirp_cnt[4]; */ -#endif - inx[0] = 0; inx[1] = 1; inx[2] = 2; @@ -3594,10 +3834,6 @@ struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmi _adapter *padapter = pxmitpriv->adapter; struct registry_priv *pregpriv = &padapter->registrypriv; int i, inx[4]; -#ifdef CONFIG_USB_HCI - /* int j, tmp, acirp_cnt[4]; */ -#endif - inx[0] = 0; inx[1] = 1; @@ -3605,7 +3841,7 @@ struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmi inx[3] = 3; if (pregpriv->wifi_spec == 1) { - int j, tmp, acirp_cnt[4]; + int j; #if 0 if (flags < XMIT_QUEUE_ENTRY) { /* priority exchange according to the completed xmitbuf flags. */ @@ -3712,7 +3948,7 @@ __inline static struct tx_servq *rtw_get_sta_pending #ifdef CONFIG_RTL8711 - if (IS_MCAST(psta->hwaddr)) { + if (IS_MCAST(psta->cmn.mac_addr)) { ptxservq = &(psta->sta_xmitpriv.be_q); /* we will use be_q to queue bc/mc frames in BCMC_stainfo */ *ppstapending = &padapter->xmitpriv.bm_pending; } else @@ -3768,7 +4004,6 @@ s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe) struct sta_info *psta; struct tx_servq *ptxservq; struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct sta_priv *pstapriv = &padapter->stapriv; struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; sint res = _SUCCESS; @@ -3916,7 +4151,6 @@ void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry) int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb) { struct sk_buff *skb = *pskb; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; _irqL irqL; /* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */ { @@ -4136,11 +4370,6 @@ static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) qsel = pattrib->priority; -#ifdef CONFIG_CONCURRENT_MODE - /* if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) - * qsel = 7; */ -#endif - #ifdef CONFIG_MCC_MODE if (MCC_EN(padapter)) { /* Under MCC */ @@ -4173,18 +4402,18 @@ static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) { - int ret = 0; - int rtap_len; - int qos_len = 0; - int dot11_hdr_len = 24; - int snap_len = 6; - unsigned char *pdata; u16 frame_ctl; - unsigned char src_mac_addr[6]; - unsigned char dst_mac_addr[6]; - struct rtw_ieee80211_hdr *dot11_hdr; - struct ieee80211_radiotap_header *rtap_hdr; + struct ieee80211_radiotap_header rtap_hdr; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct pkt_file pktfile; + struct rtw_ieee80211_hdr *pwlanhdr; + struct pkt_attrib *pattrib; + struct xmit_frame *pmgntframe; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + unsigned char *pframe; + u8 dummybuf[32]; + int len = skb->len, rtap_len; if (skb) rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); @@ -4192,11 +4421,12 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) goto fail; - rtap_hdr = (struct ieee80211_radiotap_header *)skb->data; - if (unlikely(rtap_hdr->it_version)) + _rtw_open_pktfile((_pkt *)skb, &pktfile); + _rtw_pktfile_read(&pktfile, (u8 *)(&rtap_hdr), sizeof(struct ieee80211_radiotap_header)); + rtap_len = ieee80211_get_radiotap_len((u8 *)(&rtap_hdr)); + if (unlikely(rtap_hdr.it_version)) goto fail; - rtap_len = ieee80211_get_radiotap_len(skb->data); if (unlikely(skb->len < rtap_len)) goto fail; @@ -4204,106 +4434,116 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) RTW_INFO("radiotap len (should be 14): %d\n", rtap_len); goto fail; } + _rtw_pktfile_read(&pktfile, dummybuf, rtap_len-sizeof(struct ieee80211_radiotap_header)); + len = len - rtap_len; - /* Skip the ratio tap header */ - skb_pull(skb, rtap_len); + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + rtw_udelay_os(500); + goto fail; + } - dot11_hdr = (struct rtw_ieee80211_hdr *)skb->data; - frame_ctl = le16_to_cpu(dot11_hdr->frame_ctl); - /* Check if the QoS bit is set */ + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; +// _rtw_memcpy(pframe, (void *)checking, len); + _rtw_pktfile_read(&pktfile, pframe, len); + + /* Check DATA/MGNT frames */ + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + frame_ctl = le16_to_cpu(pwlanhdr->frame_ctl); if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) { - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - u8 *buf = skb->data; - u32 len = skb->len; - u8 category, action; - int type = -1; - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) { - rtw_udelay_os(500); - goto fail; - } pattrib = &pmgntframe->attrib; - update_monitor_frame_attrib(padapter, pattrib); - pattrib->retry_ctrl = _FALSE; - - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); - - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - - _rtw_memcpy(pframe, (void *)buf, len); - - pattrib->pktlen = len; - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - if (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1)) pattrib->rate = MGN_24M; - pmlmeext->mgnt_seq = GetSequence(pwlanhdr); - pattrib->seqnum = pmlmeext->mgnt_seq; - pmlmeext->mgnt_seq++; - - pattrib->last_txcmdsz = pattrib->pktlen; - - dump_mgntframe(padapter, pmgntframe); - } else { - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - unsigned char *pframe; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - u8 *buf = skb->data; - u32 len = skb->len; - u8 category, action; - int type = -1; - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - goto fail; pattrib = &pmgntframe->attrib; update_mgntframe_attrib(padapter, pattrib); - pattrib->retry_ctrl = _FALSE; - _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + } + pattrib->retry_ctrl = _FALSE; + pattrib->pktlen = len; + pmlmeext->mgnt_seq = GetSequence(pwlanhdr); + pattrib->seqnum = pmlmeext->mgnt_seq; + pmlmeext->mgnt_seq++; + pattrib->last_txcmdsz = pattrib->pktlen; - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + dump_mgntframe(padapter, pmgntframe); - _rtw_memcpy(pframe, (void *)buf, len); +fail: + rtw_endofpktfile(&pktfile); + rtw_skb_free(skb); + return 0; +} +#endif - pattrib->pktlen = len; +/* + * The main transmit(tx) entry post handle + * + * Return + * 1 enqueue + * 0 success, hardware will handle this xmit frame(packet) + * <0 fail + */ +s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt) +{ +#ifdef CONFIG_AP_MODE + _irqL irqL0; +#endif + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + s32 res; - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + res = update_attrib(padapter, pkt, &pxmitframe->attrib); - pmlmeext->mgnt_seq = GetSequence(pwlanhdr); - pattrib->seqnum = pmlmeext->mgnt_seq; - pmlmeext->mgnt_seq++; +#ifdef CONFIG_MCC_MODE + /* record data kernel TX to driver to check MCC concurrent TX */ + rtw_hal_mcc_calc_tx_bytes_from_kernel(padapter, pxmitframe->attrib.pktlen); +#endif /* CONFIG_MCC_MODE */ - pattrib->last_txcmdsz = pattrib->pktlen; +#ifdef CONFIG_WAPI_SUPPORT + if (pxmitframe->attrib.ether_type != 0x88B4) { + if (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) { + WAPI_TRACE(WAPI_RX, "drop for key absend when tx\n"); + res = _FAIL; + } + } +#endif + if (res == _FAIL) { + /*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/ +#ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__); +#endif + rtw_free_xmitframe(pxmitpriv, pxmitframe); + return -1; + } + pxmitframe->pkt = pkt; - dump_mgntframe(padapter, pmgntframe); + rtw_led_tx_control(padapter, pxmitframe->attrib.dst); - } + do_queue_select(padapter, &pxmitframe->attrib); -fail: +#ifdef CONFIG_AP_MODE + _enter_critical_bh(&pxmitpriv->lock, &irqL0); + if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) { + _exit_critical_bh(&pxmitpriv->lock, &irqL0); + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue); + return 1; + } + _exit_critical_bh(&pxmitpriv->lock, &irqL0); +#endif - rtw_skb_free(skb); + /* pre_xmitframe */ + if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE) + return 1; return 0; } -#endif + /* * The main transmit(tx) entry * @@ -4314,22 +4554,20 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) */ s32 rtw_xmit(_adapter *padapter, _pkt **ppkt) { - static u32 start = 0; + static systime start = 0; static u32 drop_cnt = 0; -#ifdef CONFIG_AP_MODE - _irqL irqL0; -#endif struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct xmit_frame *pxmitframe = NULL; -#ifdef CONFIG_BR_EXT - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - void *br_port = NULL; -#endif /* CONFIG_BR_EXT */ - s32 res; DBG_COUNTER(padapter->tx_logs.core_tx); + if (IS_CH_WAITING(adapter_to_rfctl(padapter))) + return -1; + + if (rtw_linked_check(padapter) == _FALSE) + return -1; + if (start == 0) start = rtw_get_current_time(); @@ -4350,70 +4588,72 @@ s32 rtw_xmit(_adapter *padapter, _pkt **ppkt) } #ifdef CONFIG_BR_EXT + if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) { + void *br_port = NULL; -#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) - br_port = padapter->pnetdev->br_port; -#else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ - rcu_read_lock(); - br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); - rcu_read_unlock(); -#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + br_port = padapter->pnetdev->br_port; + #else + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); + #endif - if (br_port && check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) { - res = rtw_br_client_tx(padapter, ppkt); - if (res == -1) { - rtw_free_xmitframe(pxmitpriv, pxmitframe); - DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx); - return -1; + if (br_port) { + res = rtw_br_client_tx(padapter, ppkt); + if (res == -1) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx); + return -1; + } } } - #endif /* CONFIG_BR_EXT */ - res = update_attrib(padapter, *ppkt, &pxmitframe->attrib); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + _list b2u_list; -#ifdef CONFIG_MCC_MODE - /* record data kernel TX to driver to check MCC concurrent TX */ - rtw_hal_mcc_calc_tx_bytes_from_kernel(padapter, pxmitframe->attrib.pktlen); -#endif /* CONFIG_MCC_MODE */ - -#ifdef CONFIG_WAPI_SUPPORT - if (pxmitframe->attrib.ether_type != 0x88B4) { - if (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) { - WAPI_TRACE(WAPI_RX, "drop for key absend when tx\n"); - res = _FAIL; - } - } -#endif - if (res == _FAIL) { - /*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/ -#ifdef DBG_TX_DROP_FRAME - RTW_INFO("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__); -#endif - rtw_free_xmitframe(pxmitpriv, pxmitframe); - return -1; - } - pxmitframe->pkt = *ppkt; + res = rtw_mesh_addr_resolve(padapter, pxmitframe, *ppkt, &b2u_list); + if (res == RTW_RA_RESOLVING) + return 1; + if (res == _FAIL) + return -1; - rtw_led_control(padapter, LED_CTL_TX); + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + if (!rtw_is_list_empty(&b2u_list)) { + _list *list = get_next(&b2u_list); + struct xmit_frame *b2uframe; + + while ((rtw_end_of_queue_search(&b2u_list, list)) == _FALSE) { + b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list); + list = get_next(list); + rtw_list_delete(&b2uframe->list); + + b2uframe->pkt = rtw_os_pkt_copy(*ppkt); + if (!b2uframe->pkt) { + if (res == RTW_BMC_NO_NEED) + res = _SUCCESS; + rtw_free_xmitframe(pxmitpriv, b2uframe); + continue; + } - do_queue_select(padapter, &pxmitframe->attrib); + rtw_xmit_posthandle(padapter, b2uframe, b2uframe->pkt); + } + } + #endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */ -#ifdef CONFIG_AP_MODE - _enter_critical_bh(&pxmitpriv->lock, &irqL0); - if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) { - _exit_critical_bh(&pxmitpriv->lock, &irqL0); - DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue); - return 1; + if (res == RTW_BMC_NO_NEED) { + rtw_free_xmitframe(&padapter->xmitpriv, pxmitframe); + return 0; + } } - _exit_critical_bh(&pxmitpriv->lock, &irqL0); -#endif +#endif /* CONFIG_RTW_MESH */ - /* pre_xmitframe */ - if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE) - return 1; + pxmitframe->pkt = NULL; /* let rtw_xmit_posthandle not to free pkt inside */ + res = rtw_xmit_posthandle(padapter, pxmitframe, *ppkt); - return 0; + return res; } #ifdef CONFIG_TDLS @@ -4473,7 +4713,7 @@ sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_fra /* Transmit TDLS PTI via AP */ if (ptdls_sta->sleepq_len == 1) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ISSUE_PTI); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ISSUE_PTI); ret = _TRUE; } @@ -4496,32 +4736,31 @@ inline bool xmitframe_hiq_filter(struct xmit_frame *xmitframe) _adapter *adapter = xmitframe->padapter; struct registry_priv *registry = &adapter->registrypriv; - if (rtw_get_intf_type(adapter) != RTW_PCIE) { - - if (adapter->registrypriv.wifi_spec == 1) - allow = _TRUE; - else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) { + if (adapter->registrypriv.wifi_spec == 1) + allow = _TRUE; + else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) { - struct pkt_attrib *attrib = &xmitframe->attrib; + struct pkt_attrib *attrib = &xmitframe->attrib; - if (attrib->ether_type == 0x0806 - || attrib->ether_type == 0x888e + if (attrib->ether_type == 0x0806 + || attrib->ether_type == 0x888e #ifdef CONFIG_WAPI_SUPPORT - || attrib->ether_type == 0x88B4 + || attrib->ether_type == 0x88B4 #endif - || attrib->dhcp_pkt - ) { - if (0) - RTW_INFO(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter) - , attrib->ether_type, attrib->dhcp_pkt ? " DHCP" : ""); - allow = _TRUE; - } - } else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL) + || attrib->dhcp_pkt + ) { + if (0) + RTW_INFO(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter) + , attrib->ether_type, attrib->dhcp_pkt ? " DHCP" : ""); allow = _TRUE; - else if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL) { - } else - rtw_warn_on(1); - } + } + } else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL) + allow = _TRUE; + else if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL) + allow = _FALSE; + else + rtw_warn_on(1); + return allow; } @@ -4534,7 +4773,6 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; struct pkt_attrib *pattrib = &pxmitframe->attrib; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; sint bmcst = IS_MCAST(pattrib->ra); bool update_tim = _FALSE; #ifdef CONFIG_TDLS @@ -4543,7 +4781,7 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p ret = xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pxmitframe); #endif /* CONFIG_TDLS */ - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _FALSE) { + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) { DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_fwstate); return ret; } @@ -4592,7 +4830,7 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p if (bmcst) { _enter_critical_bh(&psta->sleep_q.lock, &irqL); - if (pstapriv->sta_dz_bitmap) { /* if anyone sta is in ps mode */ + if (rtw_tim_map_anyone_be_set(padapter, pstapriv->sta_dz_bitmap)) { /* if anyone sta is in ps mode */ /* pattrib->qsel = QSLT_HIGH; */ /* HIQ */ rtw_list_delete(&pxmitframe->list); @@ -4603,13 +4841,14 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p psta->sleepq_len++; - if (!(pstapriv->tim_bitmap & BIT(0))) + if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))) update_tim = _TRUE; - pstapriv->tim_bitmap |= BIT(0); - pstapriv->sta_dz_bitmap |= BIT(0); + rtw_tim_map_set(padapter, pstapriv->tim_bitmap, 0); + rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, 0); - /* RTW_INFO("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */ + /* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */ + /* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ if (update_tim == _TRUE) { if (is_broadcast_mac_addr(pattrib->ra)) _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer BC"); @@ -4623,7 +4862,6 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p ret = _TRUE; DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_mcast); - } _exit_critical_bh(&psta->sleep_q.lock, &irqL); @@ -4638,7 +4876,7 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p if (psta->state & WIFI_SLEEP_STATE) { u8 wmmps_ac = 0; - if (pstapriv->sta_dz_bitmap & BIT(psta->aid)) { + if (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid)) { rtw_list_delete(&pxmitframe->list); /* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */ @@ -4671,12 +4909,13 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p psta->sleepq_ac_len++; if (((psta->has_legacy_ac) && (!wmmps_ac)) || ((!psta->has_legacy_ac) && (wmmps_ac))) { - if (!(pstapriv->tim_bitmap & BIT(psta->aid))) + if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid))) update_tim = _TRUE; - pstapriv->tim_bitmap |= BIT(psta->aid); + rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid); - /* RTW_INFO("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */ + /* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */ + /* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ if (update_tim == _TRUE) { /* RTW_INFO("sleepq_len==1, update BCNTIM\n"); */ @@ -4763,22 +5002,14 @@ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) #ifdef CONFIG_TDLS if (!(psta->tdls_sta_state & TDLS_LINKED_STATE)) #endif /* CONFIG_TDLS */ - pstapriv->sta_dz_bitmap |= BIT(psta->aid); - - + rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid); dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); - - dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); - - dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); - - dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); @@ -4786,12 +5017,16 @@ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) if (!(psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta_bmc != NULL)) { #endif /* CONFIG_TDLS */ - /* for BC/MC Frames */ pstaxmitpriv = &psta_bmc->sta_xmitpriv; + dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vo_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); + dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vi_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending); rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); - + dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->bk_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); #ifdef CONFIG_TDLS } @@ -4890,14 +5125,15 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) } #endif /* CONFIG_TDLS */ - if (pstapriv->tim_bitmap & BIT(psta->aid)) { - /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */ + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) { + /* RTW_INFO("wakeup to xmit, qlen==0\n"); */ + /* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ /* upate BCN for TIM IE */ /* update_BCNTIM(padapter); */ update_mask = BIT(0); } - pstapriv->tim_bitmap &= ~BIT(psta->aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); if (psta->state & WIFI_SLEEP_STATE) psta->state ^= WIFI_SLEEP_STATE; @@ -4908,14 +5144,14 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) psta->state ^= WIFI_STA_ALIVE_CHK_STATE; } - pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid); } /* for BC/MC Frames */ if (!psta_bmc) goto _exit; - if ((pstapriv->sta_dz_bitmap & 0xfffe) == 0x0) { /* no any sta in ps mode */ + if (!(rtw_tim_map_anyone_be_set_exclude_aid0(padapter, pstapriv->sta_dz_bitmap))) { /* no any sta in ps mode */ xmitframe_phead = get_list_head(&psta_bmc->sleep_q); xmitframe_plist = get_next(xmitframe_phead); @@ -4948,14 +5184,15 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) } if (psta_bmc->sleepq_len == 0) { - if (pstapriv->tim_bitmap & BIT(0)) { - /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */ + if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) { + /* RTW_INFO("wakeup to xmit, qlen==0\n"); */ + /* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ /* upate BCN for TIM IE */ /* update_BCNTIM(padapter); */ update_mask |= BIT(1); } - pstapriv->tim_bitmap &= ~BIT(0); - pstapriv->sta_dz_bitmap &= ~BIT(0); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0); + rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0); } } @@ -5044,9 +5281,10 @@ void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta) goto exit; } #endif /* CONFIG_TDLS */ - pstapriv->tim_bitmap &= ~BIT(psta->aid); + rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid); - /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */ + /* RTW_INFO("wakeup to xmit, qlen==0\n"); */ + /* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */ /* upate BCN for TIM IE */ /* update_BCNTIM(padapter); */ update_beacon(padapter, _TIM_IE_, NULL, _TRUE); @@ -5055,7 +5293,9 @@ void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta) } +#ifdef CONFIG_TDLS exit: +#endif /* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */ _exit_critical_bh(&pxmitpriv->lock, &irqL); @@ -5126,60 +5366,6 @@ struct xmit_buf *dequeue_pending_xmitbuf( return pxmitbuf; } -static struct xmit_buf *dequeue_pending_xmitbuf_under_survey( - struct xmit_priv *pxmitpriv) -{ - _irqL irql; - struct xmit_buf *pxmitbuf; -#ifdef CONFIG_USB_HCI - struct xmit_frame *pxmitframe; -#endif - _queue *pqueue; - - - pxmitbuf = NULL; - pqueue = &pxmitpriv->pending_xmitbuf_queue; - - _enter_critical_bh(&pqueue->lock, &irql); - - if (_rtw_queue_empty(pqueue) == _FALSE) { - _list *plist, *phead; - u8 type = 0; - - phead = get_list_head(pqueue); - plist = phead; - do { - plist = get_next(plist); - if (plist == phead) - break; - - pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); - -#ifdef CONFIG_USB_HCI - pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; - if (pxmitframe) - type = get_frame_sub_type(pxmitbuf->pbuf + TXDESC_SIZE + pxmitframe->pkt_offset * PACKET_OFFSET_SZ); - else - RTW_INFO("%s, !!!ERROR!!! For USB, TODO ITEM\n", __FUNCTION__); -#else - type = get_frame_sub_type(pxmitbuf->pbuf + TXDESC_OFFSET); -#endif - - if ((type == WIFI_PROBEREQ) || - (type == WIFI_DATA_NULL) || - (type == WIFI_QOS_DATA_NULL)) { - rtw_list_delete(&pxmitbuf->list); - break; - } - pxmitbuf = NULL; - } while (1); - } - - _exit_critical_bh(&pqueue->lock, &irql); - - return pxmitbuf; -} - static struct xmit_buf *dequeue_pending_xmitbuf_ext( struct xmit_priv *pxmitpriv) { @@ -5226,13 +5412,9 @@ struct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter) if (_TRUE == rtw_is_xmit_blocked(padapter)) return pxmitbuf; - if (rtw_xmit_ac_blocked(padapter) == _TRUE) - pxmitbuf = dequeue_pending_xmitbuf_under_survey(pxmitpriv); - else { - pxmitbuf = dequeue_pending_xmitbuf_ext(pxmitpriv); - if (pxmitbuf == NULL) - pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv); - } + pxmitbuf = dequeue_pending_xmitbuf_ext(pxmitpriv); + if (pxmitbuf == NULL && rtw_xmit_ac_blocked(padapter) != _TRUE) + pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv); return pxmitbuf; } @@ -5266,15 +5448,16 @@ thread_return rtw_xmit_thread(thread_context context) padapter = (PADAPTER)context; thread_enter("RTW_XMIT_THREAD"); - padapter->xmitpriv.stop_req = 0; do { err = rtw_hal_xmit_thread_handler(padapter); flush_signals_thread(); } while (_SUCCESS == err); - /*_rtw_up_sema(&padapter->xmitpriv.terminate_xmitthread_sema);*/ - thread_exit(&padapter->xmitpriv.xmitthread_comp); + RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter)); + + rtw_thread_wait_stop(); + return 0; } #endif @@ -5342,11 +5525,30 @@ bool rtw_is_xmit_blocked(_adapter *padapter) bool rtw_xmit_ac_blocked(_adapter *adapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); _adapter *iface; struct mlme_ext_priv *mlmeext; - struct mlme_ext_info *mlmeextinfo; bool blocked = _FALSE; int i; +#ifdef DBG_CONFIG_ERROR_DETECT +#ifdef DBG_CONFIG_ERROR_RESET +#ifdef CONFIG_USB_HCI + if (rtw_hal_sreset_inprogress(adapter) == _TRUE) { + blocked = _TRUE; + goto exit; + } +#endif/* #ifdef CONFIG_USB_HCI */ +#endif/* #ifdef DBG_CONFIG_ERROR_RESET */ +#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */ + + if (rfctl->offch_state != OFFCHS_NONE + #ifdef CONFIG_DFS + || IS_RADAR_DETECTED(rfctl) || rfctl->csa_ch + #endif + ) { + blocked = _TRUE; + goto exit; + } for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -5536,6 +5738,53 @@ void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority) } #endif /* CONFIG_TX_AMSDU */ +#ifdef DBG_TXBD_DESC_DUMP +static struct rtw_tx_desc_backup tx_backup[HW_QUEUE_ENTRY][TX_BAK_FRMAE_CNT]; +static u8 backup_idx[HW_QUEUE_ENTRY]; + +void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq) +{ + u32 tmp32; + u8 *pxmit_buf; + + if (rtw_get_hw_init_completed(padapter) == _FALSE) + return; + + pxmit_buf = pxmitframe->pxmitbuf->pbuf; + + _rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_desc, pxmit_buf, desc_size); + _rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_data_hdr, pxmit_buf+desc_size, TX_BAK_DATA_LEN); + + tmp32 = rtw_read32(padapter, get_txbd_rw_reg(hwq)); + + tx_backup[hwq][backup_idx[hwq]].tx_bak_rp = (tmp32>>16)&0xfff; + tx_backup[hwq][backup_idx[hwq]].tx_bak_wp = tmp32&0xfff; + + tx_backup[hwq][backup_idx[hwq]].tx_desc_size = desc_size; + + backup_idx[hwq] = (backup_idx[hwq] + 1) % TX_BAK_FRMAE_CNT; +} + +void rtw_tx_desc_backup_reset(void) +{ + int i, j; + + for (i = 0; i < HW_QUEUE_ENTRY; i++) { + for (j = 0; j < TX_BAK_FRMAE_CNT; j++) + _rtw_memset(&tx_backup[i][j], 0, sizeof(struct rtw_tx_desc_backup)); + + backup_idx[i] = 0; + } +} + +u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak) +{ + *pbak = &tx_backup[hwq][0]; + + return backup_idx[hwq]; +} +#endif + void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms) { sctx->timeout_ms = timeout_ms; diff --git a/hal/HalPwrSeqCmd.c b/hal/HalPwrSeqCmd.c index de709b1..389785c 100644 --- a/hal/HalPwrSeqCmd.c +++ b/hal/HalPwrSeqCmd.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /*++ Copyright (c) Realtek Semiconductor Corp. All rights reserved. @@ -54,9 +49,11 @@ u8 HalPwrSeqCmdParsing( { WLAN_PWR_CFG PwrCfgCmd = {0}; u8 bPollingBit = _FALSE; + u8 bHWICSupport = _FALSE; u32 AryIdx = 0; u8 value = 0; u32 offset = 0; + u8 flag = 0; u32 pollingCount = 0; /* polling autoload done. */ u32 maxPollingCnt = 5000; @@ -111,6 +108,14 @@ u8 HalPwrSeqCmdParsing( bPollingBit = _FALSE; offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); + + rtw_hal_get_hwreg(padapter, HW_VAR_PWR_CMD, &bHWICSupport); + if (bHWICSupport && offset == 0x06) { + flag = 0; + maxPollingCnt = 100000; + } else + maxPollingCnt = 5000; + #ifdef CONFIG_GSPI_HCI if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) offset = SPI_LOCAL_OFFSET | offset; @@ -131,7 +136,26 @@ u8 HalPwrSeqCmdParsing( if (pollingCount++ > maxPollingCnt) { RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value); - return _FALSE; + + /* For PCIE + USB package poll power bit timeout issue only modify 8821AE and 8723BE */ + if (bHWICSupport && offset == 0x06 && flag == 0) { + + RTW_ERR("[WARNING] PCIE polling(0x%X) timeout(%d), Toggle 0x04[3] and try again.\n", offset, maxPollingCnt); + if (IS_HARDWARE_TYPE_8723DE(padapter)) + PlatformEFIOWrite1Byte(padapter, 0x40, (PlatformEFIORead1Byte(padapter, 0x40)) & (~BIT3)); + + PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) | BIT3); + PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) & ~BIT3); + + if (IS_HARDWARE_TYPE_8723DE(padapter)) + PlatformEFIOWrite1Byte(padapter, 0x40, PlatformEFIORead1Byte(padapter, 0x40)|BIT3); + + /* Retry Polling Process one more time */ + pollingCount = 0; + flag = 1; + } else { + return _FALSE; + } } } while (!bPollingBit); diff --git a/hal/btc/halbtc8821c1ant.c b/hal/btc/halbtc8821c1ant.c index ff2e29f..1ec3bd2 100644 --- a/hal/btc/halbtc8821c1ant.c +++ b/hal/btc/halbtc8821c1ant.c @@ -1,34 +1,23 @@ -/* ************************************************************ - * Description: +/****************************************************************************** * - * This file is for RTL8821C Co-exist mechanism + * Copyright(c) 2016 - 2017 Realtek Corporation. * - * History - * 2012/11/15 Cosa first check in. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. * - * ************************************************************ */ - -/* ************************************************************ - * include files - * ************************************************************ */ + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #include "mp_precomp.h" #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) #if (RTL8821C_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8821c_1ant glcoex_dm_8821c_1ant; -static struct coex_dm_8821c_1ant *coex_dm = &glcoex_dm_8821c_1ant; -static struct coex_sta_8821c_1ant glcoex_sta_8821c_1ant; -static struct coex_sta_8821c_1ant *coex_sta = &glcoex_sta_8821c_1ant; -static struct psdscan_sta_8821c_1ant gl_psd_scan_8821c_1ant; -static struct psdscan_sta_8821c_1ant *psd_scan = &gl_psd_scan_8821c_1ant; -static struct rfe_type_8821c_1ant gl_rfe_type_8821c_1ant; -static struct rfe_type_8821c_1ant *rfe_type = &gl_rfe_type_8821c_1ant; - const char *const glbt_info_src_8821c_1ant[] = { "BT Info[wifi fw]", @@ -36,28 +25,25 @@ const char *const glbt_info_src_8821c_1ant[] = { "BT Info[bt auto report]", }; -u32 glcoex_ver_date_8821c_1ant = 20170310; -u32 glcoex_ver_8821c_1ant = 0x12; -u32 glcoex_ver_btdesired_8821c_1ant = 0x11; - +u32 glcoex_ver_date_8821c_1ant = 20180712; +u32 glcoex_ver_8821c_1ant = 0x32; +u32 glcoex_ver_btdesired_8821c_1ant = 0x28; -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8821c1ant_ - * ************************************************************ */ -u8 halbtc8821c1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) +#if 0 +static +u8 halbtc8821c1ant_bt_rssi_state(struct btc_coexist *btc, u8 level_num, + u8 rssi_thresh, u8 rssi_thresh1) { - s32 bt_rssi = 0; - u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + s32 bt_rssi = 0; + u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; bt_rssi = coex_sta->bt_rssi; if (level_num == 2) { - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { + if (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW || + coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW) { if (bt_rssi >= (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) bt_rssi_state = BTC_RSSI_STATE_HIGH; @@ -77,18 +63,18 @@ u8 halbtc8821c1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) return coex_sta->pre_bt_rssi_state; } - if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_LOW)) { + if (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW || + coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW) { if (bt_rssi >= (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) bt_rssi_state = BTC_RSSI_STATE_MEDIUM; else bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_bt_rssi_state == - BTC_RSSI_STATE_STAY_MEDIUM)) { + } else if (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_MEDIUM || + coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_MEDIUM) { if (bt_rssi >= (rssi_thresh1 + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) bt_rssi_state = BTC_RSSI_STATE_HIGH; @@ -108,22 +94,27 @@ u8 halbtc8821c1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) return bt_rssi_state; } +#endif -u8 halbtc8821c1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) +#if 0 +static +u8 halbtc8821c1ant_wifi_rssi_state(struct btc_coexist *btc, u8 index, + u8 level_num, u8 rssi_thresh, + u8 rssi_thresh1) { - s32 wifi_rssi = 0; - u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + s32 wifi_rssi = 0; + u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btc->btc_get(btc, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); if (level_num == 2) { - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + if (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_LOW || + coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW) { + if (wifi_rssi >= rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT) wifi_rssi_state = BTC_RSSI_STATE_HIGH; else wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; @@ -141,21 +132,21 @@ u8 halbtc8821c1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, return coex_sta->pre_wifi_rssi_state[index]; } - if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) - || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_LOW)) { - if (wifi_rssi >= (rssi_thresh + - BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + if (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_LOW || + coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW) { + if (wifi_rssi >= rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT) wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; else wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; - } else if ((coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_MEDIUM) || - (coex_sta->pre_wifi_rssi_state[index] == - BTC_RSSI_STATE_STAY_MEDIUM)) { - if (wifi_rssi >= (rssi_thresh1 + - BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + } else if (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_MEDIUM || + coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_MEDIUM) { + if (wifi_rssi >= rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT) wifi_rssi_state = BTC_RSSI_STATE_HIGH; else if (wifi_rssi < rssi_thresh) wifi_rssi_state = BTC_RSSI_STATE_LOW; @@ -173,164 +164,95 @@ u8 halbtc8821c1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, return wifi_rssi_state; } +#endif -void halbtc8821c1ant_update_ra_mask(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 dis_rate_mask) +static +void halbtc8821c1ant_limited_rx(struct btc_coexist *btc, boolean force_exec, + boolean rej_ap_agg_pkt, + boolean bt_ctrl_agg_buf_size, u8 agg_buf_size) { - coex_dm->cur_ra_mask = dis_rate_mask; + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; - if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) - btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, - &coex_dm->cur_ra_mask); - coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; + /* ============================================ + * Rx Aggregation related setting + * ============================================ + */ + btc->btc_set(btc, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btc->btc_set(btc, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work + * when BT control Rx aggregation size + */ + btc->btc_set(btc, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btc->btc_set(btc, BTC_SET_ACT_AGGREGATE_CTRL, NULL); } -void halbtc8821c1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) +static +void halbtc8821c1ant_low_penalty_ra(struct btc_coexist *btc, + boolean force_exec, boolean low_penalty_ra, + u8 thres) { - boolean wifi_under_b_mode = FALSE; - - coex_dm->cur_arfr_type = type; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + static u8 cur_thres; - if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { - switch (coex_dm->cur_arfr_type) { - case 0: /* normal mode */ - btcoexist->btc_write_4byte(btcoexist, 0x430, - coex_dm->backup_arfr_cnt1); - btcoexist->btc_write_4byte(btcoexist, 0x434, - coex_dm->backup_arfr_cnt2); - break; - case 1: - btcoexist->btc_get(btcoexist, - BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - if (wifi_under_b_mode) { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x01010101); - } else { - btcoexist->btc_write_4byte(btcoexist, - 0x430, 0x0); - btcoexist->btc_write_4byte(btcoexist, - 0x434, 0x04030201); - } - break; - default: - break; - } + if (!force_exec) { + if (low_penalty_ra == coex_dm->cur_low_penalty_ra && + thres == cur_thres) + return; } - coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; -} - -void halbtc8821c1ant_retry_limit(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) -{ - coex_dm->cur_retry_limit_type = type; - - if (force_exec || - (coex_dm->pre_retry_limit_type != - coex_dm->cur_retry_limit_type)) { - switch (coex_dm->cur_retry_limit_type) { - case 0: /* normal mode */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - coex_dm->backup_retry_limit); - break; - case 1: /* retry limit=8 */ - btcoexist->btc_write_2byte(btcoexist, 0x42a, - 0x0808); - break; - default: - break; - } - } + if (low_penalty_ra) + btc->btc_phydm_modify_RA_PCR_threshold(btc, 0, thres); + else + btc->btc_phydm_modify_RA_PCR_threshold(btc, 0, 0); - coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; + coex_dm->cur_low_penalty_ra = low_penalty_ra; + cur_thres = thres; } -void halbtc8821c1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) +static +void halbtc8821c1ant_write_scbd(struct btc_coexist *btc, u16 bitpos, + boolean state) { - coex_dm->cur_ampdu_time_type = type; - - if (force_exec || - (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { - switch (coex_dm->cur_ampdu_time_type) { - case 0: /* normal mode */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - coex_dm->backup_ampdu_max_time); - break; - case 1: /* AMPDU timw = 0x38 * 32us */ - btcoexist->btc_write_1byte(btcoexist, 0x456, - 0x38); - break; - default: - break; - } - } + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + static u16 originalval = 0x8002, preval; - coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; -} + if (state) + originalval = originalval | bitpos; + else + originalval = originalval & (~bitpos); -void halbtc8821c1ant_limited_tx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, - IN u8 retry_limit_type, IN u8 ampdu_time_type) -{ - switch (ra_mask_type) { - case 0: /* normal mode */ - halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, - 0x0); - break; - case 1: /* disable cck 1/2 */ - halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, - 0x00000003); - break; - case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ - halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, - 0x0001f1f7); - break; - default: - break; - } + coex_sta->score_board_WB = originalval; - halbtc8821c1ant_auto_rate_fallback_retry(btcoexist, force_exec, - arfr_type); - halbtc8821c1ant_retry_limit(btcoexist, force_exec, retry_limit_type); - halbtc8821c1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); + if (originalval != preval) { + preval = originalval; + btc->btc_write_2byte(btc, 0xaa, originalval); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s: return for nochange\n", __func__); + BTC_TRACE(trace_buf); + } } -void halbtc8821c1ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +static +void halbtc8821c1ant_read_scbd(struct btc_coexist *btc, + u16 *score_board_val) { - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); - - + *score_board_val = (btc->btc_read_2byte(btc, 0xaa)) & 0x7fff; } -void halbtc8821c1ant_query_bt_info(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_query_bt_info(struct btc_coexist *btc) { - u8 h2c_parameter[1] = {0}; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + u8 h2c_parameter[1] = {0}; if (coex_sta->bt_disabled) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No query BT info because BT is disabled!\n"); + "[BTCoex], No query BT info because BT is disabled!\n"); BTC_TRACE(trace_buf); return; } @@ -338,32 +260,95 @@ void halbtc8821c1ant_query_bt_info(IN struct btc_coexist *btcoexist) h2c_parameter[0] |= BIT(0); /* trigger */ - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); + btc->btc_fill_h2c(btc, 0x61, 1, h2c_parameter); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], WL query BT info!!\n"); BTC_TRACE(trace_buf); } -void halbtc8821c1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_enable_gnt_to_gpio(struct btc_coexist *btc, + boolean isenable) { - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, - cnt_autoslot_hang = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + static u8 bit_val[5] = {0, 0, 0, 0, 0}; + static boolean state; + + if (!btc->dbg_mode) + return; + + if (state == isenable) + return; + + state = isenable; + + if (isenable) { + /* enable GNT_WL, GNT_BT to GPIO for debug */ + btc->btc_write_1byte_bitmask(btc, 0x73, 0x8, 0x1); + + /* store original value */ + /*0x66[4] */ + bit_val[0] = (btc->btc_read_1byte(btc, 0x66) & BIT(4)) >> 4; + /*0x66[8] */ + bit_val[1] = (btc->btc_read_1byte(btc, 0x67) & BIT(0)); + /*0x40[19] */ + bit_val[2] = (btc->btc_read_1byte(btc, 0x42) & BIT(3)) >> 3; + /*0x64[15] */ + bit_val[3] = (btc->btc_read_1byte(btc, 0x65) & BIT(7)) >> 7; + /*0x70[18] */ + bit_val[4] = (btc->btc_read_1byte(btc, 0x72) & BIT(2)) >> 2; + + /* switch GPIO Mux */ + /*0x66[4] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x66, BIT(4), 0x0); + /*0x66[8] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x67, BIT(0), 0x0); + /*0x40[19] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x42, BIT(3), 0x0); + /*0x64[15] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x65, BIT(7), 0x0); + /*0x70[18] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x72, BIT(2), 0x0); + } else { + btc->btc_write_1byte_bitmask(btc, 0x73, 0x8, 0x0); + + /* Restore original value */ + /* switch GPIO Mux */ + /*0x66[4] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x66, BIT(4), bit_val[0]); + /*0x66[8] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x67, BIT(0), bit_val[1]); + /*0x40[19] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x42, BIT(3), bit_val[2]); + /*0x64[15] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x65, BIT(7), bit_val[3]); + /*0x70[18] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x72, BIT(2), bit_val[4]); + } +} + +static +void halbtc8821c1ant_monitor_bt_ctr(struct btc_coexist *btc) +{ + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk, cnt_slave, cnt_overhead, + cnt_autoslot_hang; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ - /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ + /* if (! (btc->btc_read_1byte(btc, 0x76e) & 0x8) ) */ reg_hp_txrx = 0x770; reg_lp_txrx = 0x774; - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + u32tmp = btc->btc_read_4byte(btc, reg_hp_txrx); reg_hp_tx = u32tmp & MASKLWORD; reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + u32tmp = btc->btc_read_4byte(btc, reg_lp_txrx); reg_lp_tx = u32tmp & MASKLWORD; reg_lp_rx = (u32tmp & MASKHWORD) >> 16; @@ -378,45 +363,42 @@ void halbtc8821c1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) BTC_TRACE(trace_buf); - if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { + if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_NCON_IDLE) { if (coex_sta->high_priority_rx >= 15) { if (cnt_overhead < 3) cnt_overhead++; if (cnt_overhead == 3) - coex_sta->is_hiPri_rx_overhead = TRUE; + coex_sta->is_hi_pri_rx_overhead = TRUE; } else { if (cnt_overhead > 0) cnt_overhead--; if (cnt_overhead == 0) - coex_sta->is_hiPri_rx_overhead = FALSE; + coex_sta->is_hi_pri_rx_overhead = FALSE; } } else - coex_sta->is_hiPri_rx_overhead = FALSE; + coex_sta->is_hi_pri_rx_overhead = FALSE; /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + btc->btc_write_1byte(btc, 0x76e, 0xc); - if ((coex_sta->low_priority_tx > 1150) && - (!coex_sta->c2h_bt_inquiry_page)) + if (coex_sta->low_priority_tx > 1150 && !coex_sta->c2h_bt_inquiry_page) coex_sta->pop_event_cnt++; - if ((coex_sta->low_priority_rx >= 1150) && - (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) - && (!coex_sta->under_ips) - && (!coex_sta->c2h_bt_inquiry_page) - && ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist))) { + if (coex_sta->low_priority_rx >= 1150 && + coex_sta->low_priority_rx >= coex_sta->low_priority_tx && + !coex_sta->under_ips && !coex_sta->c2h_bt_inquiry_page && + (bt_link_info->a2dp_exist || bt_link_info->pan_exist)) { if (cnt_slave >= 2) { bt_link_info->slave_role = TRUE; cnt_slave = 2; } else cnt_slave++; } else { - if (cnt_slave == 0) { + if (cnt_slave == 0) { bt_link_info->slave_role = FALSE; cnt_slave = 0; } else @@ -424,8 +406,8 @@ void halbtc8821c1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) } if (coex_sta->is_tdma_btautoslot) { - if ((coex_sta->low_priority_tx >= 1300) && - (coex_sta->low_priority_rx <= 150)) { + if (coex_sta->low_priority_tx >= 1300 && + coex_sta->low_priority_rx <= 15) { if (cnt_autoslot_hang >= 2) { coex_sta->is_tdma_btautoslot_hang = TRUE; cnt_autoslot_hang = 2; @@ -441,69 +423,87 @@ void halbtc8821c1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) } if (bt_link_info->hid_only) { - if (coex_sta->low_priority_rx > 50) + if (coex_sta->low_priority_tx > 100) coex_sta->is_hid_low_pri_tx_overhead = true; else coex_sta->is_hid_low_pri_tx_overhead = false; } if (!coex_sta->bt_disabled) { - if ((coex_sta->high_priority_tx == 0) && (coex_sta->high_priority_rx == 0) && (coex_sta->low_priority_tx == 0) && (coex_sta->low_priority_rx == 0)) { num_of_bt_counter_chk++; if (num_of_bt_counter_chk >= 3) { - halbtc8821c1ant_query_bt_info(btcoexist); + halbtc8821c1ant_query_bt_info(btc); num_of_bt_counter_chk = 0; } } } - } +static +void halbtc8821c1ant_monitor_wifi_ctr(struct btc_coexist *btc) +{ + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + boolean wifi_busy = FALSE, wifi_scan = FALSE; + static u8 wl_noisy_count0, wl_noisy_count1 = 3, wl_noisy_count2; + u32 cnt_cck; + static u8 cnt_ccklocking; + u8 h2c_parameter[1] = {0}; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + + /* Only enable for windows becaus 8821cu + * H2C 0x69 unknown fail @ linux + */ + if (btc->chip_interface != BTC_INTF_USB) { + /*send h2c to query WL FW dbg info */ + if ((coex_dm->cur_ps_tdma_on && coex_sta->force_lps_ctrl) || + (coex_sta->acl_busy && bt_link_info->a2dp_exist)) { + h2c_parameter[0] = 0x8; + btc->btc_fill_h2c(btc, 0x69, 1, h2c_parameter); + } + } + + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + + coex_sta->crc_ok_cck = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_VHT); + + /* CCK lock identification */ + if (coex_sta->cck_lock) + cnt_ccklocking++; + else if (cnt_ccklocking != 0) + cnt_ccklocking--; + + if (cnt_ccklocking >= 3) { + cnt_ccklocking = 3; + coex_sta->cck_lock_ever = TRUE; + } + /* WiFi environment noisy identification */ + cnt_cck = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; -void halbtc8821c1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) -{ -#if 1 - s32 wifi_rssi = 0; - boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE, - wifi_scan = FALSE; - boolean bt_idle = FALSE, wl_idle = FALSE; - static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, - wl_noisy_count1 = 3, wl_noisy_count2 = 0; - u32 total_cnt, reg_val1, reg_val2, cck_cnt; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); - - cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; - - if (cck_cnt > 250) { + if (!wifi_busy && !coex_sta->cck_lock) { + if (cnt_cck > 250) { if (wl_noisy_count2 < 3) wl_noisy_count2++; @@ -512,7 +512,7 @@ void halbtc8821c1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) wl_noisy_count1 = 0; } - } else if (cck_cnt < 50) { + } else if (cnt_cck < 100) { if (wl_noisy_count0 < 3) wl_noisy_count0++; @@ -537,771 +537,738 @@ void halbtc8821c1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) coex_sta->wl_noisy_level = 1; else coex_sta->wl_noisy_level = 0; + } +} - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + - coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; - - if ((coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY) - || - (coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } +static +void halbtc8821c1ant_monitor_bt_enable(struct btc_coexist *btc) +{ + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + static u32 bt_disable_cnt; + boolean bt_active = TRUE, bt_disabled = FALSE; + u16 u16tmp; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } + /* Read BT on/off status from scoreboard[1], + * enable this only if BT patch support this feature + */ + halbtc8821c1ant_read_scbd(btc, &u16tmp); - if (!coex_sta->pre_ccklock) { + bt_active = u16tmp & BIT(1); - if (cck_lock_counter >= 3) - coex_sta->cck_lock = TRUE; - else - coex_sta->cck_lock = FALSE; + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = FALSE; + btc->btc_set(btc, BTC_SET_BL_BT_DISABLE, &bt_disabled); } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = FALSE; - else - coex_sta->cck_lock = TRUE; - } + bt_disable_cnt++; + if (bt_disable_cnt >= 2) { + bt_disabled = TRUE; + bt_disable_cnt = 2; + } - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = TRUE; + btc->btc_set(btc, BTC_SET_BL_BT_DISABLE, &bt_disabled); + } - coex_sta->pre_ccklock = coex_sta->cck_lock; + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; -#endif + /*for win10 BT disable->enable trigger wifi scan issue */ + if (!coex_sta->bt_disabled) { + coex_sta->is_bt_reenable = TRUE; + coex_sta->cnt_bt_reenable = 15; + } else { + coex_sta->is_bt_reenable = FALSE; + coex_sta->cnt_bt_reenable = 0; + } + } } -void halbtc8821c1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +static +boolean halbtc8821c1ant_moniter_wifibt_status(struct btc_coexist *btc) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = FALSE; - boolean bt_busy = FALSE; - + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct rfe_type_8821c_1ant *rfe_type = &btc->rfe_type_8821c_1ant; + struct wifi_link_info_8821c_1ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_1ant; + static boolean pre_wifi_busy, pre_under_4way, + pre_bt_off, + pre_bt_slave, pre_hid_low_pri_tx_overhead, + pre_wifi_under_lps, pre_bt_setup_link, + pre_cck_lock, pre_cck_lock_warn; + static u8 pre_hid_busy_num, pre_wl_noisy_level; + boolean wifi_busy = FALSE, under_4way = FALSE; + boolean wifi_connected = FALSE; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + static u8 cnt_wifi_busytoidle; + u32 num_of_wifi_link = 0, wifi_link_mode = 0; + static u32 pre_num_of_wifi_link, pre_wifi_link_mode; + boolean miracast_plus_bt = FALSE; + u8 lna_lvl = 1; - coex_sta->num_of_profile = 0; + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way); - /* set link exist status */ - if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = FALSE; - coex_sta->pan_exist = FALSE; - coex_sta->a2dp_exist = FALSE; - coex_sta->hid_exist = FALSE; - coex_sta->sco_exist = FALSE; - } else { /* connection exists */ - coex_sta->bt_link_exist = TRUE; - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_FTP) { - coex_sta->pan_exist = TRUE; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = FALSE; + if (wifi_busy) { + coex_sta->gl_wifi_busy = TRUE; + cnt_wifi_busytoidle = 6; + } else { + if (coex_sta->gl_wifi_busy && cnt_wifi_busytoidle > 0) + cnt_wifi_busytoidle--; + else if (cnt_wifi_busytoidle == 0) + coex_sta->gl_wifi_busy = FALSE; + } - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_A2DP) { - coex_sta->a2dp_exist = TRUE; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = FALSE; + if (coex_sta->bt_disabled != pre_bt_off) { + pre_bt_off = coex_sta->bt_disabled; - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_HID) { - coex_sta->hid_exist = TRUE; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = FALSE; + if (coex_sta->bt_disabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) { - coex_sta->sco_exist = TRUE; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = FALSE; + BTC_TRACE(trace_buf); + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->legacy_forbidden_slot = 0; + coex_sta->le_forbidden_slot = 0; + coex_sta->bt_a2dp_vendor_id = 0; + coex_sta->bt_a2dp_device_name = 0; + return TRUE; } - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + num_of_wifi_link = wifi_link_info_ext->num_of_active_port; - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->acl_busy = coex_sta->acl_busy; + if (num_of_wifi_link != pre_num_of_wifi_link) { + pre_num_of_wifi_link = num_of_wifi_link; - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = TRUE; - bt_link_info->bt_link_exist = TRUE; + if (wifi_link_info_ext->is_p2p_connected) { + if (bt_link_info->bt_link_exist) + miracast_plus_bt = TRUE; + else + miracast_plus_bt = FALSE; + + btc->btc_set(btc, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + } + return TRUE; } - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = TRUE; - else - bt_link_info->sco_only = FALSE; + wifi_link_mode = btc->wifi_link_info.link_mode; + if (wifi_link_mode != pre_wifi_link_mode) { + pre_wifi_link_mode = wifi_link_mode; + return TRUE; + } - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = TRUE; - else - bt_link_info->a2dp_only = FALSE; + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return TRUE; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return TRUE; + } + if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { + pre_wl_noisy_level = coex_sta->wl_noisy_level; + return TRUE; + } + if (coex_sta->under_lps != pre_wifi_under_lps) { + pre_wifi_under_lps = coex_sta->under_lps; + if (coex_sta->under_lps) + return TRUE; + } + if (coex_sta->cck_lock != pre_cck_lock) { + pre_cck_lock = coex_sta->cck_lock; + return TRUE; + } + if (coex_sta->cck_lock_warn != pre_cck_lock_warn) { + pre_cck_lock_warn = coex_sta->cck_lock_warn; + return TRUE; + } + } - /* check if Pan only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->pan_only = TRUE; - else - bt_link_info->pan_only = FALSE; - - /* check if Hid only */ - if (!bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - bt_link_info->hid_exist) - bt_link_info->hid_only = TRUE; - else - bt_link_info->hid_only = FALSE; - - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_INQ_PAGE) { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_INQ_PAGE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); - } else if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); - } else if (coex_sta->bt_info == BT_INFO_8821C_1ANT_B_CONNECTION) { - /* connection exists but no busy */ - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); - } else if (((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) && - (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY)) { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); - } else if ((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) || - (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_SCO_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); - } else if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_ACL_BUSY; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); - } else { - coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_MAX; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); - } + if (!coex_sta->bt_disabled) { +#if 0 + if (coex_sta->acl_busy != pre_bt_acl_busy) { + pre_bt_acl_busy = coex_sta->acl_busy; + btc->btc_set(btc, BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL, + &lna_lvl); + return TRUE; + } +#endif + if (coex_sta->hid_busy_num != pre_hid_busy_num) { + pre_hid_busy_num = coex_sta->hid_busy_num; + return TRUE; + } - BTC_TRACE(trace_buf); + if (bt_link_info->slave_role != pre_bt_slave) { + pre_bt_slave = bt_link_info->slave_role; + return TRUE; + } - if ((BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - bt_busy = TRUE; - else - bt_busy = FALSE; + if (pre_hid_low_pri_tx_overhead != + coex_sta->is_hid_low_pri_tx_overhead) { + pre_hid_low_pri_tx_overhead = + coex_sta->is_hid_low_pri_tx_overhead; + return TRUE; + } - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + if (pre_bt_setup_link != coex_sta->is_setup_link) { + pre_bt_setup_link = coex_sta->is_setup_link; + return TRUE; + } + } + return FALSE; } -void halbtc8821c1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, - IN u8 type) +static +void halbtc8821c1ant_update_wifi_link_info(struct btc_coexist *btc, u8 reason) { - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = - 0x1; /* enable BT AFH skip WL channel for 8821c because BT Rx LO interference */ - /* h2c_parameter[0] = 0x0; */ - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct wifi_link_info_8821c_1ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_1ant; + struct btc_wifi_link_info wifi_link_info; + u8 wifi_central_chnl = 0, num_of_wifi_link = 0; + boolean isunder5G = FALSE, ismcc25g = FALSE, isp2pconnected = FALSE; + u32 wifi_link_status = 0; + + btc->btc_get(btc, BTC_GET_U4_WIFI_LINK_STATUS, &wifi_link_status); + wifi_link_info_ext->port_connect_status = wifi_link_status & 0xffff; + + btc->btc_get(btc, BTC_GET_BL_WIFI_LINK_INFO, &wifi_link_info); + btc->wifi_link_info = wifi_link_info; + + btc->btc_get(btc, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifi_central_chnl); + coex_sta->wl_center_channel = wifi_central_chnl; + + /* Check scan/connect/special-pkt action first */ + switch (reason) { + case BT_8821C_1ANT_RSN_5GSCANSTART: + case BT_8821C_1ANT_RSN_5GSWITCHBAND: + case BT_8821C_1ANT_RSN_5GCONSTART: + isunder5G = TRUE; + break; + case BT_8821C_1ANT_RSN_2GSCANSTART: + case BT_8821C_1ANT_RSN_2GSWITCHBAND: + case BT_8821C_1ANT_RSN_2GCONSTART: + isunder5G = FALSE; + break; + case BT_8821C_1ANT_RSN_2GCONFINISH: + case BT_8821C_1ANT_RSN_5GCONFINISH: + case BT_8821C_1ANT_RSN_2GMEDIA: + case BT_8821C_1ANT_RSN_5GMEDIA: + case BT_8821C_1ANT_RSN_BTINFO: + case BT_8821C_1ANT_RSN_PERIODICAL: + case BT_8821C_1ANT_RSN_5GSPECIALPKT: + case BT_8821C_1ANT_RSN_2GSPECIALPKT: + default: + switch (wifi_link_info.link_mode) { + case BTC_LINK_5G_MCC_GO_STA: + case BTC_LINK_5G_MCC_GC_STA: + case BTC_LINK_5G_SCC_GO_STA: + case BTC_LINK_5G_SCC_GC_STA: + isunder5G = TRUE; + break; + case BTC_LINK_2G_MCC_GO_STA: + case BTC_LINK_2G_MCC_GC_STA: + case BTC_LINK_2G_SCC_GO_STA: + case BTC_LINK_2G_SCC_GC_STA: + isunder5G = FALSE; + break; + case BTC_LINK_25G_MCC_GO_STA: + case BTC_LINK_25G_MCC_GC_STA: + isunder5G = FALSE; + ismcc25g = TRUE; + break; + case BTC_LINK_ONLY_STA: + if (wifi_link_info.sta_center_channel > 14) + isunder5G = TRUE; + else + isunder5G = FALSE; + break; + case BTC_LINK_ONLY_GO: + case BTC_LINK_ONLY_GC: + case BTC_LINK_ONLY_AP: + default: + if (wifi_link_info.p2p_center_channel > 14) + isunder5G = TRUE; + else + isunder5G = FALSE; - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + break; + } + break; + } - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + wifi_link_info_ext->is_all_under_5g = isunder5G; + wifi_link_info_ext->is_mcc_25g = ismcc25g; -} + if (wifi_link_status & WIFI_STA_CONNECTED) + num_of_wifi_link++; -u8 halbtc8821c1ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = FALSE; - u8 algorithm = BT_8821C_1ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; + if (wifi_link_status & WIFI_AP_CONNECTED) + num_of_wifi_link++; - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (wifi_link_status & WIFI_P2P_GO_CONNECTED) { + num_of_wifi_link++; + isp2pconnected = TRUE; + } - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; + if (wifi_link_status & WIFI_P2P_GC_CONNECTED) { + num_of_wifi_link++; + isp2pconnected = TRUE; } - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; + wifi_link_info_ext->num_of_active_port = num_of_wifi_link; + wifi_link_info_ext->is_p2p_connected = isp2pconnected; - if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_HID; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_HID_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; - } - } - } - } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_link_info: link_mode=%d, STA_Ch=%d, P2P_Ch=%d, AnyClient_Join_Go=%d !\n", + btc->wifi_link_info.link_mode, + btc->wifi_link_info.sta_center_channel, + btc->wifi_link_info.p2p_center_channel, + btc->wifi_link_info.bany_client_join_go); + BTC_TRACE(trace_buf); - return algorithm; -} + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_link_info: center_ch=%d, is_all_under_5g=%d, is_mcc_25g=%d!\n", + coex_sta->wl_center_channel, + wifi_link_info_ext->is_all_under_5g, + wifi_link_info_ext->is_mcc_25g); + BTC_TRACE(trace_buf); -void halbtc8821c1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_link_info: port_connect_status=0x%x, active_port_cnt=%d, P2P_Connect=%d!\n", + wifi_link_info_ext->port_connect_status, + wifi_link_info_ext->num_of_active_port, + wifi_link_info_ext->is_p2p_connected); + BTC_TRACE(trace_buf); - h2c_parameter[0] = 0; + switch (reason) { + case BT_8821C_1ANT_RSN_2GSCANSTART: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "2GSCANSTART"); + break; + case BT_8821C_1ANT_RSN_5GSCANSTART: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "5GSCANSTART"); + break; + case BT_8821C_1ANT_RSN_SCANFINISH: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "SCANFINISH"); + break; + case BT_8821C_1ANT_RSN_2GSWITCHBAND: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "2GSWITCHBAND"); + break; + case BT_8821C_1ANT_RSN_5GSWITCHBAND: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "5GSWITCHBAND"); + break; + case BT_8821C_1ANT_RSN_2GCONSTART: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "2GCONNECTSTART"); + break; + case BT_8821C_1ANT_RSN_5GCONSTART: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "5GCONNECTSTART"); + break; + case BT_8821C_1ANT_RSN_2GCONFINISH: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", + "2GCONNECTFINISH"); + break; + case BT_8821C_1ANT_RSN_5GCONFINISH: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", + "5GCONNECTFINISH"); + break; + case BT_8821C_1ANT_RSN_2GMEDIA: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "2GMEDIASTATUS"); + break; + case BT_8821C_1ANT_RSN_5GMEDIA: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "5GMEDIASTATUS"); + break; + case BT_8821C_1ANT_RSN_MEDIADISCON: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", + "MEDIADISCONNECT"); + break; + case BT_8821C_1ANT_RSN_2GSPECIALPKT: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "2GSPECIALPKT"); + break; + case BT_8821C_1ANT_RSN_5GSPECIALPKT: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "5GSPECIALPKT"); + break; + case BT_8821C_1ANT_RSN_BTINFO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "BTINFO"); + break; + case BT_8821C_1ANT_RSN_PERIODICAL: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "PERIODICAL"); + break; + case BT_8821C_1ANT_RSN_PNP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "PNPNotify"); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "UNKNOWN"); + break; + } - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); + BTC_TRACE(trace_buf); - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); + if (wifi_link_info_ext->is_all_under_5g || + coex_sta->num_of_profile == 0) + halbtc8821c1ant_low_penalty_ra(btc, NM_EXCU, FALSE, 0); + else if (wifi_link_info_ext->is_p2p_connected) + halbtc8821c1ant_low_penalty_ra(btc, NM_EXCU, TRUE, 30); + else + halbtc8821c1ant_low_penalty_ra(btc, NM_EXCU, TRUE, 15); } -void halbtc8821c1ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) +static +void halbtc8821c1ant_update_bt_link_info(struct btc_coexist *btc) { - coex_dm->cur_bt_auto_report = enable_auto_report; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + boolean bt_busy = FALSE, increase_scan_dev_num = FALSE; + u32 val = 0; + static u8 pre_num_of_profile, cur_num_of_profile, cnt, ble_cnt; - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; - } - halbtc8821c1ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); + if (++ble_cnt >= 3) + ble_cnt = 0; - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} + if (coex_sta->is_ble_scan_en && ble_cnt == 0) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = + btc->btc_get_ble_scan_type_from_bt(btc); + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = + btc->btc_get_ble_scan_para_from_bt(btc, 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = + btc->btc_get_ble_scan_para_from_bt(btc, 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = + btc->btc_get_ble_scan_para_from_bt(btc, 0x4); + } -void halbtc8821c1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ + coex_sta->num_of_profile = 0; -#if 1 - coex_dm->cur_low_penalty_ra = low_penalty_ra; + /* set link exist status */ + if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = FALSE; + coex_sta->pan_exist = FALSE; + coex_sta->a2dp_exist = FALSE; + coex_sta->hid_exist = FALSE; + coex_sta->sco_exist = FALSE; + coex_sta->msft_mr_exist = FALSE; + } else { /* connection exists */ + coex_sta->bt_link_exist = TRUE; + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_FTP) { + coex_sta->pan_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->pan_exist = FALSE; - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == - coex_dm->cur_low_penalty_ra) - return; - } + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_A2DP) { + coex_sta->a2dp_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->a2dp_exist = FALSE; - if (low_penalty_ra) - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); - else - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_HID) { + coex_sta->hid_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->hid_exist = FALSE; - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) { + coex_sta->sco_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->sco_exist = FALSE; -#endif + if (coex_sta->hid_busy_num == 0 && + coex_sta->hid_pair_cnt > 0 && + coex_sta->low_priority_tx > 1000 && + coex_sta->low_priority_rx > 1000 && + !coex_sta->c2h_bt_inquiry_page) + coex_sta->msft_mr_exist = true; + else + coex_sta->msft_mr_exist = false; + } -} + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + bt_link_info->acl_busy = coex_sta->acl_busy; -void halbtc8821c1ant_write_score_board( - IN struct btc_coexist *btcoexist, - IN u16 bitpos, - IN boolean state -) -{ + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = TRUE; + else + bt_link_info->sco_only = FALSE; - static u16 originalval = 0x8002, preval = 0x0; + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = TRUE; + else + bt_link_info->a2dp_only = FALSE; - if (state) - originalval = originalval | bitpos; + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = TRUE; else - originalval = originalval & (~bitpos); + bt_link_info->pan_only = FALSE; - if (originalval != preval) { + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = TRUE; + else + bt_link_info->hid_only = FALSE; - preval = originalval; - btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_INQ_PAGE) { + coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_INQ_PAGE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); + } else if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_NCON_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + } else if (coex_sta->bt_info == BT_INFO_8821C_1ANT_B_CONNECTION) { + /* connection exists but no busy */ + + if (coex_sta->msft_mr_exist) { + coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!\n"); + } else { + coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_CON_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } + } else if (((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) && + (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY)) { + coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_ACL_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); + } else if ((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + } else if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); } else { + coex_dm->bt_status = BT_8821C_1ANT_BSTATUS_MAX; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c1ant_write_score_board: return for nochange\n"); - BTC_TRACE(trace_buf); + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); } -} - -void halbtc8821c1ant_read_score_board( - IN struct btc_coexist *btcoexist, - IN u16 *score_board_val -) -{ - - *score_board_val = (btcoexist->btc_read_2byte(btcoexist, - 0xaa)) & 0x7fff; -} - -void halbtc8821c1ant_post_state_to_bt( - IN struct btc_coexist *btcoexist, - IN u16 type, - IN boolean state -) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c1ant_post_state_to_bt: type = %d, state =%d\n", - type, state); BTC_TRACE(trace_buf); - halbtc8821c1ant_write_score_board(btcoexist, (u16) type, state); -} - -boolean halbtc8821c1ant_is_wifibt_status_changed(IN struct btc_coexist - *btcoexist) -{ - static boolean pre_wifi_busy = FALSE, pre_under_4way = FALSE, - pre_bt_hs_on = FALSE, pre_bt_off = FALSE, - pre_bt_slave = FALSE, pre_hid_low_pri_tx_overhead = FALSE, - pre_wifi_under_lps = FALSE; - static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0, - pre_bt_setup_link = FALSE; - boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE; - boolean wifi_connected = FALSE; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (coex_sta->bt_disabled != pre_bt_off) { - pre_bt_off = coex_sta->bt_disabled; - - if (coex_sta->bt_disabled) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); + if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_BUSY || + coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_SCO_BUSY || + coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_SCO_BUSY) { + bt_busy = TRUE; + increase_scan_dev_num = TRUE; + } else { + bt_busy = FALSE; + increase_scan_dev_num = FALSE; + } - BTC_TRACE(trace_buf); + btc->btc_set(btc, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + btc->btc_set(btc, BTC_SET_BL_INC_SCAN_DEV_NUM, &increase_scan_dev_num); - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - coex_sta->bt_reg_vendor_ac = 0xffff; - coex_sta->bt_reg_vendor_ae = 0xffff; - return TRUE; - } + cur_num_of_profile = coex_sta->num_of_profile; + if (cur_num_of_profile != pre_num_of_profile) + cnt = 2; - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; + if (bt_link_info->a2dp_exist && (cnt > 0)) { + cnt--; + if (coex_sta->bt_a2dp_vendor_id == 0 && + coex_sta->bt_a2dp_device_name == 0) { + btc->btc_get(btc, BTC_GET_U4_BT_DEVICE_INFO, &val); - if (wifi_busy) - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, TRUE); - else - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, FALSE); - return TRUE; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return TRUE; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return TRUE; - } - if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { - pre_wl_noisy_level = coex_sta->wl_noisy_level; - return TRUE; - } - if (coex_sta->under_lps != pre_wifi_under_lps) { - pre_wifi_under_lps = coex_sta->under_lps; - if (coex_sta->under_lps == TRUE) - return TRUE; - } - } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), get BT DEVICE_INFO = %x\n", + val); + BTC_TRACE(trace_buf); - if (!coex_sta->bt_disabled) { - if (coex_sta->hid_busy_num != pre_hid_busy_num) { - pre_hid_busy_num = coex_sta->hid_busy_num; - return TRUE; + coex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff); + coex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8; } - if (bt_link_info->slave_role != pre_bt_slave) { - pre_bt_slave = bt_link_info->slave_role; - return TRUE; - } + if (coex_sta->legacy_forbidden_slot == 0 && + coex_sta->le_forbidden_slot == 0) { + btc->btc_get(btc, BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL, + &val); - if (pre_hid_low_pri_tx_overhead != coex_sta->is_hid_low_pri_tx_overhead) { - pre_hid_low_pri_tx_overhead = coex_sta->is_hid_low_pri_tx_overhead; - return TRUE; - } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), get BT FORBIDDEN_SLOT_VAL = %x\n", + val); + BTC_TRACE(trace_buf); - if (pre_bt_setup_link != coex_sta->is_setupLink) { - pre_bt_setup_link = coex_sta->is_setupLink; - return TRUE; + coex_sta->legacy_forbidden_slot = (u16)(val & 0xffff); + coex_sta->le_forbidden_slot = + (u16)((val & 0xffff0000) >> 16); } } - return FALSE; + pre_num_of_profile = coex_sta->num_of_profile; } - -void halbtc8821c1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_update_wifi_ch_info(struct btc_coexist *btc, u8 type) { - static u32 bt_disable_cnt = 0; - boolean bt_active = TRUE, bt_disabled = FALSE, wifi_under_5g = FALSE; - u16 u16tmp; - - /* This function check if bt is disabled */ -#if 0 - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = FALSE; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = FALSE; - - -#else - - /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */ - halbtc8821c1ant_read_score_board(btcoexist, &u16tmp); - - bt_active = u16tmp & BIT(1); - - -#endif - - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = FALSE; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } else { + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + struct wifi_link_info_8821c_1ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_1ant; + u8 h2c_parameter[3] = {0}, i; + u32 wifi_bw; + u8 wifi_central_chnl = 0; + u8 wifi_5g_chnl[19] = {120, 124, 128, 132, 136, 140, 144, 149, 153, 157, + 118, 126, 134, 142, 151, 159, 122, 138, 155}; + u8 bt_skip_cneter_chanl[19] = {2, 8, 17, 26, 34, 42, 51, 62, 71, 77, 2, + 12, 29, 46, 66, 76, 10, 37, 68}; + u8 bt_skip_span[19] = {4, 8, 8, 10, 8, 10, 8, 8, 10, 4, 4, 16, 16, 16, + 16, 4, 20, 34, 20}; + boolean is_any_connected = FALSE; + + if (btc->manual_control) + return; - bt_disable_cnt++; - if (bt_disable_cnt >= 2) { - bt_disabled = TRUE; - bt_disable_cnt = 2; + btc->btc_get(btc, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if (btc->stop_coex_dm || coex_sta->is_rf_state_off) { + is_any_connected = FALSE; + wifi_central_chnl = 0; + } else if (type != BTC_MEDIA_DISCONNECT || + (type == BTC_MEDIA_DISCONNECT && + wifi_link_info_ext->num_of_active_port > 0)) { + if (wifi_link_info_ext->num_of_active_port == 1) { + if (wifi_link_info_ext->is_p2p_connected) + wifi_central_chnl = + btc->wifi_link_info + .p2p_center_channel; + else + wifi_central_chnl = + btc->wifi_link_info + .sta_center_channel; + } else { /* port > 2 */ + if ((btc->wifi_link_info + .p2p_center_channel > 14) && + (btc->wifi_link_info + .sta_center_channel > 14)) + wifi_central_chnl = + btc->wifi_link_info + .p2p_center_channel; + else if (btc->wifi_link_info + .p2p_center_channel <= 14) + wifi_central_chnl = + btc->wifi_link_info + .p2p_center_channel; + else if (btc->wifi_link_info + .sta_center_channel <= 14) + wifi_central_chnl = + btc->wifi_link_info + .sta_center_channel; } - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); } - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (wifi_central_chnl > 0) + is_any_connected = TRUE; - if ((wifi_under_5g) || (bt_disabled)) - halbtc8821c1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); - else - halbtc8821c1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE); + if (is_any_connected) { + if (wifi_central_chnl <= 14) { + h2c_parameter[0] = 0x1; + h2c_parameter[1] = wifi_central_chnl; + if (wifi_bw == BTC_WIFI_BW_HT40) + h2c_parameter[2] = 0x36; + else + h2c_parameter[2] = 0x24; + } else { /* for 5G */ + for (i = 0; i <= 18; i++) { + if (wifi_central_chnl == wifi_5g_chnl[i]) + break; + } - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; + if (i <= 18) { + h2c_parameter[0] = 0x3; + h2c_parameter[1] = bt_skip_cneter_chanl[i]; + h2c_parameter[2] = bt_skip_span[i]; + } + } } -} - -void halbtc8821c1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, - boolean isenable) -{ -#if BT_8821C_1ANT_COEX_DBG - static u8 bitVal[5] = {0, 0, 0, 0, 0}; - static boolean state = FALSE; - /* - if (state ==isenable) - return; - else - state = isenable; - */ - if (isenable) { - - /* enable GNT_WL, GNT_BT to GPIO for debug */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); - - /* store original value */ - bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, - 0x66) & BIT(4)) >> 4; /*0x66[4] */ - bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, - 0x67) & BIT(0)); /*0x66[8] */ - bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, - 0x42) & BIT(3)) >> 3; /*0x40[19] */ - bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, - 0x65) & BIT(7)) >> 7; /*0x64[15] */ - bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, - 0x72) & BIT(2)) >> 2; /*0x70[18] */ - - /* switch GPIO Mux */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), - 0x0); /*0x66[4] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), - 0x0); /*0x66[8] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), - 0x0); /*0x40[19] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), - 0x0); /*0x64[15] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), - 0x0); /*0x70[18] = 0 */ - - - } else { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - /* Restore original value */ - /* switch GPIO Mux */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), - bitVal[0]); /*0x66[4] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), - bitVal[1]); /*0x66[8] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), - bitVal[2]); /*0x40[19] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), - bitVal[3]); /*0x64[15] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), - bitVal[4]); /*0x70[18] = 0 */ - } + btc->btc_fill_h2c(btc, 0x66, 3, h2c_parameter); -#endif + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], para[0:2] = 0x%x 0x%x 0x%x\n", + h2c_parameter[0], h2c_parameter[1], h2c_parameter[2]); + BTC_TRACE(trace_buf); } -u32 halbtc8821c1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, - IN u16 reg_addr) +static +u32 halbtc8821c1ant_read_indirect_reg(struct btc_coexist *btc, u16 reg_addr) { u32 j = 0, delay_count = 0; /* wait for ready bit before access 0x1700 */ while (1) { - if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) { + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; @@ -1311,15 +1278,15 @@ u32 halbtc8821c1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, break; } - btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); + btc->btc_write_4byte(btc, 0x1700, 0x800F0000 | reg_addr); - return btcoexist->btc_read_4byte(btcoexist, + return btc->btc_read_4byte(btc, 0x1708); /* get read data */ } -void halbtc8821c1ant_ltecoex_indirect_write_reg(IN struct btc_coexist - *btcoexist, - IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) +static +void halbtc8821c1ant_write_indirect_reg(struct btc_coexist *btc, u16 reg_addr, + u32 bit_mask, u32 reg_value) { u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0; @@ -1329,8 +1296,8 @@ void halbtc8821c1ant_ltecoex_indirect_write_reg(IN struct btc_coexist if (bit_mask == 0xffffffff) { /* wait for ready bit before access 0x1700/0x1704 */ while (1) { - if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) { + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; @@ -1340,11 +1307,10 @@ void halbtc8821c1ant_ltecoex_indirect_write_reg(IN struct btc_coexist break; } - btcoexist->btc_write_4byte(btcoexist, 0x1704, - reg_value); /* put write data */ + /* put write data */ + btc->btc_write_4byte(btc, 0x1704, reg_value); - btcoexist->btc_write_4byte(btcoexist, 0x1700, - 0xc00F0000 | reg_addr); + btc->btc_write_4byte(btc, 0x1700, 0xc00F0000 | reg_addr); } else { for (i = 0; i <= 31; i++) { if (((bit_mask >> i) & 0x1) == 0x1) { @@ -1354,14 +1320,13 @@ void halbtc8821c1ant_ltecoex_indirect_write_reg(IN struct btc_coexist } /* read back register value before write */ - val = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - reg_addr); + val = halbtc8821c1ant_read_indirect_reg(btc, reg_addr); val = (val & (~bit_mask)) | (reg_value << bitpos); /* wait for ready bit before access 0x1700/0x1704 */ while (1) { - if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) { + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; @@ -1371,40 +1336,58 @@ void halbtc8821c1ant_ltecoex_indirect_write_reg(IN struct btc_coexist break; } - btcoexist->btc_write_4byte(btcoexist, 0x1704, - val); /* put write data */ - - btcoexist->btc_write_4byte(btcoexist, 0x1700, - 0xc00F0000 | reg_addr); + /* put write data */ + btc->btc_write_4byte(btc, 0x1704, val); + btc->btc_write_4byte(btc, 0x1700, 0xc00F0000 | reg_addr); } - } -void halbtc8821c1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, - IN boolean enable) +static +void halbtc8821c1ant_ltecoex_enable(struct btc_coexist *btc, boolean enable) { u8 val; + /* 0x38[7] */ val = (enable) ? 1 : 0; - halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, - val); /* 0x38[7] */ + halbtc8821c1ant_write_indirect_reg(btc, 0x38, 0x80, val); +} + +static +void halbtc8821c1ant_ltecoex_table(struct btc_coexist *btc, u8 table_type, + u16 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8821C_1ANT_CTT_WL_VS_LTE: + reg_addr = 0xa0; + break; + case BT_8821C_1ANT_CTT_BT_VS_LTE: + reg_addr = 0xa4; + break; + } + /* 0xa0[15:0] or 0xa4[15:0] */ + if (reg_addr != 0x0000) + halbtc8821c1ant_write_indirect_reg(btc, reg_addr, 0xffff, + table_content); } -void halbtc8821c1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, - IN boolean wifi_control) +static +void halbtc8821c1ant_coex_ctrl_owner(struct btc_coexist *btc, + boolean wifi_control) { u8 val; + /* 0x70[26] */ val = (wifi_control) ? 1 : 0; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, - val); /* 0x70[26] */ - + btc->btc_write_1byte_bitmask(btc, 0x73, 0x4, val); } -void halbtc8821c1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) +static +void halbtc8821c1ant_set_gnt_bt(struct btc_coexist *btc, u8 control_block, + boolean sw_control, u8 state) { u32 val = 0, val_orig = 0; @@ -1415,8 +1398,7 @@ void halbtc8821c1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, else val = 0x1; - val_orig = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); + val_orig = halbtc8821c1ant_read_indirect_reg(btc, 0x38); switch (control_block) { case BT_8821C_1ANT_GNT_BLOCK_RFC_BB: @@ -1431,12 +1413,12 @@ void halbtc8821c1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, break; } - halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); + halbtc8821c1ant_write_indirect_reg(btc, 0x38, 0xffffffff, val); } -void halbtc8821c1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) +static +void halbtc8821c1ant_set_gnt_wl(struct btc_coexist *btc, u8 control_block, + boolean sw_control, u8 state) { u32 val = 0, val_orig = 0; @@ -1447,8 +1429,7 @@ void halbtc8821c1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, else val = 0x1; - val_orig = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); + val_orig = halbtc8821c1ant_read_indirect_reg(btc, 0x38); switch (control_block) { case BT_8821C_1ANT_GNT_BLOCK_RFC_BB: @@ -1463,34 +1444,13 @@ void halbtc8821c1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, break; } - halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); -} - -void halbtc8821c1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u16 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8821C_1ANT_CTT_WL_VS_LTE: - reg_addr = 0xa0; - break; - case BT_8821C_1ANT_CTT_BT_VS_LTE: - reg_addr = 0xa4; - break; - } - - if (reg_addr != 0x0000) - halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ - - + halbtc8821c1ant_write_indirect_reg(btc, 0x38, 0xffffffff, val); } - -void halbtc8821c1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u8 table_content) +#if 0 +static +void halbtc8821c1ant_ltecoex_set_break_table(struct btc_coexist *btc, + u8 table_type, u8 table_content) { u16 reg_addr = 0x0000; @@ -1509,23 +1469,25 @@ void halbtc8821c1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, break; } + /* 0xa8[15:0] or 0xb4[15:0] */ if (reg_addr != 0x0000) - halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ - - + halbtc8821c1ant_write_indirect_reg(btc, reg_addr, 0xff, + table_content); } +#endif -void halbtc8821c1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 interval, - IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, - IN u8 val0x6c4_b3) +#if 0 +static +void halbtc8821c1ant_set_wltoggle_coex_table(struct btc_coexist *btc, + boolean force_exec, u8 interval, + u8 val0x6c4_b0, u8 val0x6c4_b1, + u8 val0x6c4_b2, u8 val0x6c4_b3) { static u8 pre_h2c_parameter[6] = {0}; - u8 cur_h2c_parameter[6] = {0}; + u8 cur_h2c_parameter[6] = {0}; u8 i, match_cnt = 0; - cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ + cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ cur_h2c_parameter[1] = interval; cur_h2c_parameter[2] = val0x6c4_b0; @@ -1548,63 +1510,53 @@ void halbtc8821c1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, for (i = 1; i <= 5; i++) pre_h2c_parameter[i] = cur_h2c_parameter[i]; - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); + btc->btc_fill_h2c(btc, 0x69, 6, cur_h2c_parameter); } +#endif - -void halbtc8821c1ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +static +void halbtc8821c1ant_set_table(struct btc_coexist *btc, boolean force_exec, + u32 val0x6c0, u32 val0x6c4, u32 val0x6c8, + u8 val0x6cc) { - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + if (!force_exec) { + if (val0x6c0 == coex_dm->cur_val0x6c0 && + val0x6c4 == coex_dm->cur_val0x6c4 && + val0x6c8 == coex_dm->cur_val0x6c8 && + val0x6cc == coex_dm->cur_val0x6cc) + return; + } - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} + btc->btc_write_4byte(btc, 0x6c0, val0x6c0); + btc->btc_write_4byte(btc, 0x6c4, val0x6c4); + btc->btc_write_4byte(btc, 0x6c8, val0x6c8); + btc->btc_write_1byte(btc, 0x6cc, val0x6cc); -void halbtc8821c1ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ coex_dm->cur_val0x6c0 = val0x6c0; coex_dm->cur_val0x6c4 = val0x6c4; coex_dm->cur_val0x6c8 = val0x6c8; coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - - halbtc8821c1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; } -void halbtc8821c1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) +static +void halbtc8821c1ant_table(struct btc_coexist *btc, boolean force_exec, u8 type) { - u32 break_table; - u8 select_table; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + u32 break_table; + u8 select_table; coex_sta->coex_table_type = type; if (coex_sta->concurrent_rx_mode_on == TRUE) { - break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ - select_table = - 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ + /* set WL hi-pri can break BT */ + break_table = 0xf0ffffff; + /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ + select_table = 0x1b; } else { break_table = 0xffffff; - select_table = 0x3; + select_table = 0x13; } BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -1614,199 +1566,222 @@ void halbtc8821c1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, switch (type) { case 0: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, break_table, - select_table); + halbtc8821c1ant_set_table(btc, force_exec, 0x65555555, + 0x65555555, break_table, + select_table); break; case 1: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); + halbtc8821c1ant_set_table(btc, force_exec, 0x65555555, + 0x5a5a5a5a, break_table, + select_table); break; case 2: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0xaa5a5a5a, 0xaa5a5a5a, break_table, - select_table); + halbtc8821c1ant_set_table(btc, force_exec, 0x65555555, + 0xaaaaaaaa, break_table, + select_table); break; - case 3: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); + case 3: /* not use */ + halbtc8821c1ant_set_table(btc, force_exec, 0x65555555, + 0x5a5a5a5a, break_table, + select_table); break; case 4: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0x5a5a5a5a, break_table, - select_table); + halbtc8821c1ant_set_table(btc, force_exec, 0x65555555, + 0x5a5a5a5a, break_table, + select_table); break; case 5: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, break_table, - select_table); + halbtc8821c1ant_set_table(btc, force_exec, 0x6a5a5a5a, + 0x5a5a5a5a, break_table, + select_table); break; - case 6: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, - select_table); + case 6: /* not use */ + halbtc8821c1ant_set_table(btc, force_exec, 0x65555555, + 0x5a5a5a5a, break_table, + select_table); break; case 7: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0xaa555555, 0xaa555555, break_table, - select_table); + halbtc8821c1ant_set_table(btc, force_exec, 0x65555555, + 0xaaaa5aaa, break_table, + select_table); break; case 8: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xaaaa5aaa, break_table, - select_table); + halbtc8821c1ant_set_table(btc, force_exec, 0x65555555, + 0x6aaa6aaa, break_table, + select_table); break; case 9: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaaaa5aaa, break_table, - select_table); + halbtc8821c1ant_set_table(btc, force_exec, 0x65555555, + 0xaaaaaaaa, break_table, + select_table); break; case 10: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0xaaaaaaaa, 0xaaaaaaaa, break_table, - select_table); + halbtc8821c1ant_set_table(btc, force_exec, 0xaa5555aa, + 0xaaaaaaaa, break_table, + select_table); break; case 11: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x55a55555, 0x5aaa5a5a, break_table, - select_table); + halbtc8821c1ant_set_table(btc, force_exec, 0x65a55555, + 0x5aaa5a5a, break_table, + select_table); break; case 12: - halbtc8821c1ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5aaa5a5a, break_table, - select_table); + halbtc8821c1ant_set_table(btc, force_exec, 0x65555555, + 0x5aaa5a5a, break_table, + select_table); + break; + case 13: + halbtc8821c1ant_set_table(btc, force_exec, 0xaa5555aa, + 0x5a5a5a5a, break_table, + select_table); + break; + case 14: + halbtc8821c1ant_set_table(btc, force_exec, 0xaa5555aa, + 0x5a5a5a5a, break_table, + select_table); + break; + case 15: + halbtc8821c1ant_set_table(btc, force_exec, 0xffffffff, + 0x5a5a5a5a, break_table, + select_table); break; default: break; } } -void halbtc8821c1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) +static +void halbtc8821c1ant_ignore_wlan_act(struct btc_coexist *btc, + boolean force_exec, boolean enable) { - u8 h2c_parameter[1] = {0}; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + u8 h2c_parameter[1] = {0}; + + if (btc->manual_control || btc->stop_coex_dm) + return; + + if (!force_exec) { + if (enable == coex_dm->cur_ignore_wlan_act) + return; + } if (enable) - h2c_parameter[0] |= BIT(0); /* function enable */ + h2c_parameter[0] |= BIT(0); /* function enable */ - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); + btc->btc_fill_h2c(btc, 0x63, 1, h2c_parameter); + + coex_dm->cur_ignore_wlan_act = enable; } -void halbtc8821c1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) +static +void halbtc8821c1ant_lps_rpwm(struct btc_coexist *btc, boolean force_exec, + u8 lps_val, u8 rpwm_val) { - coex_dm->cur_ignore_wlan_act = enable; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) + if (lps_val == coex_dm->cur_lps && + rpwm_val == coex_dm->cur_rpwm) return; } - halbtc8821c1ant_set_fw_ignore_wlan_act(btcoexist, enable); - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; + btc->btc_set(btc, BTC_SET_U1_LPS_VAL, &lps_val); + btc->btc_set(btc, BTC_SET_U1_RPWM_VAL, &rpwm_val); + + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; } -void halbtc8821c1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) +static +void halbtc8821c1ant_multiport_tdma(struct btc_coexist *btc, u8 multi_port_mode) { - u8 lps = lps_val; - u8 rpwm = rpwm_val; +#if 0 + struct btc_multi_port_tdma_info multiport_tdma_para; + static u8 pre_state = BTC_MULTI_PORT_TDMA_MODE_NONE; - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); -} + if (multi_port_mode == pre_state) + return; -void halbtc8821c1ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) -{ - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; + multiport_tdma_para.btc_multi_port_tdma_mode = multi_port_mode; - if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) - return; + switch (multi_port_mode) { + case BTC_MULTI_PORT_TDMA_MODE_NONE: + multiport_tdma_para.start_time_from_bcn = 0; + multiport_tdma_para.bt_time = 0; + break; + case BTC_MULTI_PORT_TDMA_MODE_2G_SCC_GO: + multiport_tdma_para.start_time_from_bcn = 65; + multiport_tdma_para.bt_time = 35; + break; + case BTC_MULTI_PORT_TDMA_MODE_2G_P2P_GO: + multiport_tdma_para.start_time_from_bcn = 55; + multiport_tdma_para.bt_time = 45; + break; } - halbtc8821c1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; + btc->btc_set(btc, BTC_SET_WIFI_BT_COEX_MODE, &multiport_tdma_para); + + pre_state = multi_port_mode; +#endif } -void halbtc8821c1ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +static +void halbtc8821c1ant_tdma_check(struct btc_coexist *btc, boolean new_ps_state) { - u8 lps_mode = 0x0; - u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; + u8 lps_mode = 0x0; + u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + btc->btc_get(btc, BTC_GET_U1_LPS_MODE, &lps_mode); if (lps_mode) { /* already under LPS state */ if (new_ps_state) { /* keep state under LPS, do nothing. */ } else { /* will leave LPS state, turn off psTdma first */ - /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, - 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); + btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter); } } else { /* NO PS state */ if (new_ps_state) { /* will enter LPS state, turn off psTdma first */ - /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, - 8);*/ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); + btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter); } else { /* keep state under NO PS state, do nothing. */ } } } -boolean halbtc8821c1ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +static +boolean halbtc8821c1ant_power_save_state(struct btc_coexist *btc, u8 ps_type, + u8 lps_val, u8 rpwm_val) { - boolean low_pwr_disable = FALSE, result = TRUE; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + boolean low_pwr_disable = FALSE, result = TRUE; switch (ps_type) { case BTC_PS_WIFI_NATIVE: /* recover to original 32k low power setting */ coex_sta->force_lps_ctrl = FALSE; low_pwr_disable = FALSE; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); - + /* btc->btc_set(btc, BTC_SET_ACT_DISABLE_LOW_POWER, + * &low_pwr_disable); + */ + btc->btc_set(btc, BTC_SET_ACT_PRE_NORMAL_LPS, NULL); break; case BTC_PS_LPS_ON: coex_sta->force_lps_ctrl = TRUE; - halbtc8821c1ant_ps_tdma_check_for_power_save_state( - btcoexist, TRUE); - halbtc8821c1ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); + halbtc8821c1ant_tdma_check(btc, TRUE); + halbtc8821c1ant_lps_rpwm(btc, NM_EXCU, lps_val, rpwm_val); /* when coex force to enter LPS, do not enter 32k low power. */ low_pwr_disable = TRUE; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); - + btc->btc_set(btc, BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma.*/ + btc->btc_set(btc, BTC_SET_ACT_ENTER_LPS, NULL); break; case BTC_PS_LPS_OFF: coex_sta->force_lps_ctrl = TRUE; - halbtc8821c1ant_ps_tdma_check_for_power_save_state( - btcoexist, FALSE); - result = btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); - + halbtc8821c1ant_tdma_check(btc, FALSE); + result = btc->btc_set(btc, BTC_SET_ACT_LEAVE_LPS, NULL); break; default: break; @@ -1815,14 +1790,17 @@ boolean halbtc8821c1ant_power_save_state(IN struct btc_coexist *btcoexist, return result; } - -void halbtc8821c1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +static +void halbtc8821c1ant_set_tdma(struct btc_coexist *btc, u8 byte1, u8 byte2, + u8 byte3, u8 byte4, u8 byte5) { - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = FALSE, result = FALSE; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = FALSE, result = FALSE; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + u8 ps_type = BTC_PS_WIFI_NATIVE; if (byte5 & BIT(2)) coex_sta->is_tdma_btautoslot = TRUE; @@ -1831,16 +1809,22 @@ void halbtc8821c1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, /* release bt-auto slot for auto-slot hang is detected!! */ if (coex_sta->is_tdma_btautoslot) - if ((coex_sta->is_tdma_btautoslot_hang) || - (bt_link_info->slave_role)) + if (coex_sta->is_tdma_btautoslot_hang || + bt_link_info->slave_role) byte5 = byte5 & 0xfb; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); +#if 1 + btc->btc_get(btc, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable); +#else + if (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO && + btc->wifi_link_info.bhotspot && + btc->wifi_link_info.bany_client_join_go) + ap_enable = TRUE; +#endif if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c1ant_set_fw_pstdma == FW for 1Ant AP mode\n"); + "[BTCoex], %s == FW for 1Ant AP mode\n", __func__); BTC_TRACE(trace_buf); real_byte1 &= ~BIT(4); real_byte1 |= BIT(5); @@ -1848,31 +1832,25 @@ void halbtc8821c1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, real_byte5 |= BIT(5); real_byte5 &= ~BIT(6); - halbtc8821c1ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, - 0x0); + ps_type = BTC_PS_WIFI_NATIVE; + halbtc8821c1ant_power_save_state(btc, ps_type, 0x0, 0x0); } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c1ant_set_fw_pstdma == Force LPS Leave (byte1 = 0x%x)\n", byte1); + "[BTCoex], %s == Force LPS (byte1 = 0x%x)\n", + __func__, byte1); BTC_TRACE(trace_buf); -#if 0 - halbtc8821c1ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, - 0x4); -#endif - if (!halbtc8821c1ant_power_save_state(btcoexist, BTC_PS_LPS_OFF, 0x50, 0x4)) + ps_type = BTC_PS_LPS_OFF; + if (!halbtc8821c1ant_power_save_state(btc, ps_type, 0x50, 0x4)) result = TRUE; - } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c1ant_set_fw_pstdma == native power save (byte1 = 0x%x)\n", byte1); + "[BTCoex], %s == native power save (byte1 = 0x%x)\n", + __func__, byte1); BTC_TRACE(trace_buf); - halbtc8821c1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, - 0x0); + ps_type = BTC_PS_WIFI_NATIVE; + halbtc8821c1ant_power_save_state(btc, ps_type, 0x0, 0x0); } coex_sta->is_set_ps_state_fail = result; @@ -1890,32 +1868,35 @@ void halbtc8821c1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, coex_dm->ps_tdma_para[3] = byte4; coex_dm->ps_tdma_para[4] = real_byte5; - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); - + btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter); } else { coex_sta->cnt_set_ps_state_fail++; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c1ant_set_fw_pstdma == Force Leave LPS Fail (cnt = %d)\n", - coex_sta->cnt_set_ps_state_fail); + "[BTCoex], %s == Force Leave LPS Fail (cnt = %d)\n", + __func__, coex_sta->cnt_set_ps_state_fail); BTC_TRACE(trace_buf); } -} + if (ps_type == BTC_PS_WIFI_NATIVE) + btc->btc_set(btc, BTC_SET_ACT_POST_NORMAL_LPS, NULL); +} -void halbtc8821c1ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) +static +void halbtc8821c1ant_tdma(struct btc_coexist *btc, boolean force_exec, + boolean turn_on, u8 type) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - struct btc_board_info *board_info = &btcoexist->board_info; - boolean wifi_busy = FALSE; - static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; - static boolean pre_wifi_busy = FALSE; - + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + struct btc_board_info *board_info = &btc->board_info; + boolean wifi_busy = FALSE; + static u8 tdma_byte4_modify, pre_tdma_byte4_modify; + static boolean pre_wifi_busy; + u8 multiport_pstdma = BTC_MULTI_PORT_TDMA_MODE_NONE; - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; + btc->btc_set_atomic(btc, &coex_dm->setting_tdma, TRUE); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); if (wifi_busy != pre_wifi_busy) { force_exec = TRUE; @@ -1923,526 +1904,349 @@ void halbtc8821c1ant_ps_tdma(IN struct btc_coexist *btcoexist, } /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - if (bt_link_info->slave_role) - psTdmaByte4Modify = 0x1; + if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist)) + tdma_byte4_modify = 0x1; else - psTdmaByte4Modify = 0x0; + tdma_byte4_modify = 0x0; - if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { + if (pre_tdma_byte4_modify != tdma_byte4_modify) { force_exec = TRUE; - pre_psTdmaByte4Modify = psTdmaByte4Modify; + pre_tdma_byte4_modify = tdma_byte4_modify; } if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) { + if (turn_on == coex_dm->cur_ps_tdma_on && + type == coex_dm->cur_ps_tdma) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", + "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", (coex_dm->cur_ps_tdma_on ? "on" : "off"), coex_dm->cur_ps_tdma); BTC_TRACE(trace_buf); + + btc->btc_set_atomic(btc, &coex_dm->setting_tdma, FALSE); return; } } - if (coex_dm->cur_ps_tdma_on) { + if (turn_on) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); + type); BTC_TRACE(trace_buf); - } + /* enable TBTT nterrupt */ + btc->btc_write_1byte_bitmask(btc, 0x550, 0x8, 0x1); - if (turn_on) { switch (type) { default: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); + halbtc8821c1ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11, + 0x11); break; - case 3: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x30, 0x03, 0x10, 0x50); + halbtc8821c1ant_set_tdma(btc, 0x51, 0x30, 0x03, 0x10, + 0x50); break; case 4: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x21, 0x03, 0x10, 0x50); + halbtc8821c1ant_set_tdma(btc, 0x51, 0x21, 0x03, 0x10, + 0x50); break; case 5: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x11); + halbtc8821c1ant_set_tdma(btc, 0x61, 0x3a, 0x03, 0x11, + 0x11); break; case 6: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x20, 0x03, 0x11, 0x10); + halbtc8821c1ant_set_tdma(btc, 0x61, 0x20, 0x03, 0x11, + 0x11); break; case 7: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); + halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10, + 0x54 | tdma_byte4_modify); break; case 8: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); + halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10, + 0x54 | tdma_byte4_modify); break; - case 9: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x54 | - psTdmaByte4Modify); + case 9: /* not use */ + halbtc8821c1ant_set_tdma(btc, 0x51, 0x10, 0x03, 0x10, + 0x54 | tdma_byte4_modify); break; case 10: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); + halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x07, 0x10, + 0x55); break; case 11: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x25, 0x03, 0x11, 0x10 | - psTdmaByte4Modify); + halbtc8821c1ant_set_tdma(btc, 0x61, 0x25, 0x03, 0x11, + 0x11); break; case 12: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x30, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); + halbtc8821c1ant_set_tdma(btc, 0x51, 0x35, 0x03, 0x10, + 0x50 | tdma_byte4_modify); break; case 13: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x07, 0x10, 0x54 | - psTdmaByte4Modify); + halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x07, 0x10, + 0x54 | tdma_byte4_modify); break; case 14: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x15, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); + halbtc8821c1ant_set_tdma(btc, 0x51, 0x15, 0x03, 0x10, + 0x50 | tdma_byte4_modify); break; - case 15: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x20, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); + case 15: /* not use */ + halbtc8821c1ant_set_tdma(btc, 0x51, 0x20, 0x03, 0x10, + 0x50 | tdma_byte4_modify); break; - case 16: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x15 | - psTdmaByte4Modify); + case 16: /* not use */ + halbtc8821c1ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x11, + 0x11 | tdma_byte4_modify); break; case 17: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x14 | - psTdmaByte4Modify); + halbtc8821c1ant_set_tdma(btc, 0x61, 0x08, 0x03, 0x11, + 0x14 | tdma_byte4_modify); break; case 18: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x30, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); + halbtc8821c1ant_set_tdma(btc, 0x51, 0x30, 0x03, 0x10, + 0x50 | tdma_byte4_modify); break; - case 19: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x15, 0x03, 0x11, 0x10); + case 19: /* not use */ + halbtc8821c1ant_set_tdma(btc, 0x61, 0x15, 0x03, 0x11, + 0x10); break; - case 20: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); + case 20: /* not use */ + halbtc8821c1ant_set_tdma(btc, 0x61, 0x30, 0x03, 0x11, + 0x10); break; case 21: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x30, 0x03, 0x11, 0x10); + halbtc8821c1ant_set_tdma(btc, 0x61, 0x30, 0x03, 0x11, + 0x10); break; case 22: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x25, 0x03, 0x11, 0x10); + halbtc8821c1ant_set_tdma(btc, 0x61, 0x25, 0x03, 0x11, + 0x10); break; case 23: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x10); - break; - case 27: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x15); - break; - case 32: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x11); - break; - case 33: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x35, 0x03, 0x11, 0x10); - break; - case 57: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 58: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x51, 0x10, 0x03, 0x10, 0x50 | - psTdmaByte4Modify); - break; - case 67: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0x61, 0x10, 0x03, 0x11, 0x10 | - psTdmaByte4Modify); - break; - - /* 1-Ant to 2-Ant TDMA case */ - case 103: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x3a, 0x03, 0x70, 0x10); - break; - case 104: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x21, 0x03, 0x70, 0x10); - break; - case 105: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x15, 0x03, 0x71, 0x11); - break; - case 106: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x20, 0x03, 0x71, 0x11); + halbtc8821c1ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x11, + 0x10); break; - case 107: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x10, 0x03, 0x70, 0x14 | - psTdmaByte4Modify); + case 24: + halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10, + 0x54 | tdma_byte4_modify); break; - case 108: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x10, 0x03, 0x70, 0x14 | - psTdmaByte4Modify); + case 25: + halbtc8821c1ant_set_tdma(btc, 0x51, 0x3a, 0x03, 0x11, + 0x50); break; - case 113: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x25, 0x03, 0x70, 0x10 | - psTdmaByte4Modify); + case 26: + halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10, + 0x55); break; - case 114: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x15, 0x03, 0x70, 0x10 | - psTdmaByte4Modify); - break; - case 115: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xd3, 0x20, 0x03, 0x70, 0x10 | - psTdmaByte4Modify); + case 27: + halbtc8821c1ant_set_tdma(btc, 0x61, 0x08, 0x03, 0x11, + 0x15); break; - case 117: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x10, 0x03, 0x71, 0x14 | - psTdmaByte4Modify); + case 28: + halbtc8821c1ant_set_tdma(btc, 0x51, 0x08, 0x0b, 0x10, + 0x54); break; - case 119: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x15, 0x03, 0x71, 0x10); + case 32: + halbtc8821c1ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11, + 0x11); break; - case 120: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x30, 0x03, 0x71, 0x10); + case 33: + halbtc8821c1ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11, + 0x10); break; - case 121: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x30, 0x03, 0x71, 0x10); + case 36: + halbtc8821c1ant_set_tdma(btc, 0x61, 0x50, 0x03, 0x11, + 0x10); break; - case 122: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x25, 0x03, 0x71, 0x10); + case 37: + halbtc8821c1ant_set_tdma(btc, 0x61, 0x3c, 0x03, 0x11, + 0x10); break; - case 132: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x35, 0x03, 0x71, 0x11); + case 201: + multiport_pstdma = BTC_MULTI_PORT_TDMA_MODE_2G_SCC_GO; + halbtc8821c1ant_set_tdma(btc, 0x51, 0x3f, 0x3, 0x10, + 0x50); break; - case 133: - halbtc8821c1ant_set_fw_pstdma(btcoexist, - 0xe3, 0x35, 0x03, 0x71, 0x10); + case 202: + multiport_pstdma = BTC_MULTI_PORT_TDMA_MODE_2G_P2P_GO; + halbtc8821c1ant_set_tdma(btc, 0x51, 0x35, 0x3, 0x10, + 0x50); break; - } } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + type); + BTC_TRACE(trace_buf); + /* disable PS tdma */ switch (type) { case 8: /* PTA Control */ - halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x8, - 0x0, 0x0, 0x0, 0x0); + halbtc8821c1ant_set_tdma(btc, 0x8, 0x0, 0x0, 0x0, 0x0); break; case 0: default: /* Software control, Antenna at BT side */ - halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x0, 0x0); + halbtc8821c1ant_set_tdma(btc, 0x0, 0x0, 0x0, 0x0, 0x0); break; - case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */ - halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); + case 1: /* 2-Ant, 0x778=3, antenna control + * by antenna diversity + */ + halbtc8821c1ant_set_tdma(btc, 0x0, 0x0, 0x0, 0x48, 0x0); break; } } + halbtc8821c1ant_multiport_tdma(btc, multiport_pstdma); + if (!coex_sta->is_set_ps_state_fail) { /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; - } -} - -void halbtc8821c1ant_set_int_block(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 pos_type) -{ -#if 0 - u8 regval_0xcba; - u32 u32tmp1 = 0; - - coex_dm->cur_int_block_status = pos_type; - - if (!force_exec) { - if (coex_dm->pre_int_block_status == - coex_dm->cur_int_block_status) - return; - } - - coex_dm->pre_int_block_status = coex_dm->cur_int_block_status; - - regval_0xcba = btcoexist->btc_read_1byte(btcoexist, 0xcba); - - switch (pos_type) { - - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG: - regval_0xcba = (regval_0xcba | BIT(0)) & (~(BIT( - 2))); /* 0xcb8[16] = 1, 0xcb8[18] = 0, WL_G select BTG */ - regval_0xcba = regval_0xcba & 0x0f; - - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x5); */ /* Gain Table */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x2); */ /* CCK Gain Table */ - - break; - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG: - regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( - 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ - - /* regval_0xcba = regval_0xcba | BIT(4) | BIT(5) ; */ /* 0xcb8[21:20] = 2b'11, WL_G @ WLAG on */ - /* regval_0xcba = (regval_0xcba | BIT(6)) & (~(BIT(7)) ) ; */ /* 0xcb8[23:22] = 2b'01, WL_A @ WLAG off */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x0); */ /* Gain Table */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x6); */ /* CCK Gain Table */ - - break; - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG: - regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( - 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ - /*regval_0xcba = (regval_0xcba | BIT(4)) & (~(BIT(5))); */ /* 0xcb8[21:20] = 2b'01, WL_G @ WLAG off */ - /*regval_0xcba = regval_0xcba | BIT(6) | BIT(7); */ /* 0xcb8[23:22] = 2b'11, WL_A @ WLAG on */ - - break; - } - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcba, 0xff, - regval_0xcba); - - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Int Block setup) 0xcb8 = 0x%08x **********\n", - u32tmp1); - BTC_TRACE(trace_buf); - -#endif -} - -void halbtc8821c1ant_set_ext_band_switch(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 pos_type) -{ - -#if 0 - boolean switch_polatiry_inverse = FALSE; - u8 regval_0xcb6; - u32 u32tmp1 = 0, u32tmp2 = 0; - - if (!rfe_type->ext_band_switch_exist) - return; - - coex_dm->cur_ext_band_switch_status = pos_type; - - if (!force_exec) { - if (coex_dm->pre_ext_band_switch_status == - coex_dm->cur_ext_band_switch_status) - return; + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; } - coex_dm->pre_ext_band_switch_status = - coex_dm->cur_ext_band_switch_status; - - /* swap control polarity if use different switch control polarity*/ - switch_polatiry_inverse = (rfe_type->ext_band_switch_ctrl_polarity == 1 - ? ~switch_polatiry_inverse : switch_polatiry_inverse); - - /*swap control polarity for WL_A, default polarity 0xcb4[21] = 0 && 0xcb4[23] = 1 is for WL_G */ - switch_polatiry_inverse = (pos_type == - BT_8821C_1ANT_EXT_BAND_SWITCH_TO_WLA ? ~switch_polatiry_inverse - : switch_polatiry_inverse); - - regval_0xcb6 = btcoexist->btc_read_1byte(btcoexist, 0xcb6); - - /* for normal switch polrity, 0xcb4[21] =1 && 0xcb4[23] = 0 for WL_A, vice versa */ - regval_0xcb6 = (switch_polatiry_inverse == 1 ? ((regval_0xcb6 & (~(BIT( - 7)))) | BIT(5)) : ((regval_0xcb6 & (~(BIT(5)))) | BIT(7))); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb6, 0xff, - regval_0xcb6); - - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb0); - u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ext Band switch setup) 0xcb0 = 0x%08x, 0xcb4 = 0x%08x**********\n", - u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - + btc->btc_set_atomic(btc, &coex_dm->setting_tdma, FALSE); } -void halbtc8821c1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) +static +void halbtc8821c1ant_set_ant_switch(struct btc_coexist *btc, + boolean force_exec, u8 ctrl_type, + u8 pos_type) { - struct btc_board_info *board_info = &btcoexist->board_info; - boolean switch_polatiry_inverse = FALSE; - u8 regval_0xcb7 = 0, regval_0x64; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + struct rfe_type_8821c_1ant *rfe_type = &btc->rfe_type_8821c_1ant; + struct btc_board_info *board_info = &btc->board_info; + boolean polarity_inverse = FALSE; + u8 regval = 0; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; if (!rfe_type->ext_ant_switch_exist) return; - coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; - if (!force_exec) { - if (coex_dm->pre_ext_ant_switch_status == - coex_dm->cur_ext_ant_switch_status) + if (((ctrl_type << 8) + pos_type) == + coex_dm->cur_ext_ant_switch_status) return; } - coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; + coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; - /* swap control polarity if use different switch control polarity*/ - /* Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */ - /* Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG, 0xcb4[29:28] = 2b'10 => Ant to WLG */ + /* swap control polarity if use different switch control polarity + * Normal switch polarity for DPDT, + * 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, + * 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main + * Normal switch polarity for SPDT, + * 0xcb4[29:28] = 2b'01 => Ant to BTG, + * 0xcb4[29:28] = 2b'10 => Ant to WLG + */ if (rfe_type->ext_ant_switch_ctrl_polarity) - switch_polatiry_inverse = ~switch_polatiry_inverse; + polarity_inverse = !polarity_inverse; /* swap control polarity if 1-Ant at Aux */ if (rfe_type->ant_at_main_port == FALSE) - switch_polatiry_inverse = ~switch_polatiry_inverse; + polarity_inverse = !polarity_inverse; switch (pos_type) { default: - case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT: - case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE: - case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA: + case BT_8821C_1ANT_TO_BT: + case BT_8821C_1ANT_TO_NOCARE: + case BT_8821C_1ANT_TO_WLA: break; - case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG: - if (!rfe_type->wlg_Locate_at_btg) - switch_polatiry_inverse = ~switch_polatiry_inverse; + case BT_8821C_1ANT_TO_WLG: + if (!rfe_type->wlg_locate_at_btg) + polarity_inverse = !polarity_inverse; break; } if (board_info->ant_div_cfg) - ctrl_type = BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; + ctrl_type = BT_8821C_1ANT_CTRL_BY_ANTDIV; switch (ctrl_type) { default: - case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x77); /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ - - regval_0xcb7 = (switch_polatiry_inverse == FALSE ? - 0x1 : 0x2); /* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, regval_0xcb7); - + case BT_8821C_1ANT_CTRL_BY_BBSW: + /* 0x4c[23] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0); + /* 0x4c[24] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1); + /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x77); + /* 0xcb4[29:28] = 2b'01 for no switch_polarity_inverse, + * DPDT_SEL_N =1, DPDT_SEL_P =0 + */ + regval = (!polarity_inverse ? 0x1 : 0x2); + btc->btc_write_1byte_bitmask(btc, 0xcb7, 0x30, regval); break; - case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x66); /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ - - regval_0xcb7 = (switch_polatiry_inverse == FALSE ? - 0x2 : 0x1); /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, regval_0xcb7); - + case BT_8821C_1ANT_CTRL_BY_PTA: + /* 0x4c[23] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0); + /* 0x4c[24] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1); + /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x66); + /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, + * DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1 + */ + regval = (!polarity_inverse ? 0x2 : 0x1); + btc->btc_write_1byte_bitmask(btc, 0xcb7, 0x30, regval); break; - case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x88); /* */ - - /* no regval_0xcb7 setup required, because antenna switch control value by antenna diversity */ - + case BT_8821C_1ANT_CTRL_BY_ANTDIV: + /* 0x4c[23] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0); + /* 0x4c[24] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1); + btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x88); + + /* no regval_0xcb7 setup required, because antenna switch + * control value by antenna diversity + */ break; - case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x1); /* 0x4c[23] = 1 */ - - regval_0x64 = (switch_polatiry_inverse == FALSE ? 0x0 : - 0x1); /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, - regval_0x64); + case BT_8821C_1ANT_CTRL_BY_MAC: + /* 0x4c[23] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x1); + /* 0x64[0] = 1b'0 for no switch_polarity_inverse, + * DPDT_SEL_N =1, DPDT_SEL_P =0 + */ + regval = (!polarity_inverse ? 0x0 : 0x1); + btc->btc_write_1byte_bitmask(btc, 0x64, 0x1, regval); break; - case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x0); /* 0x4c[24] = 0 */ - - /* no setup required, because antenna switch control value by BT vendor 0xac[1:0] */ + case BT_8821C_1ANT_CTRL_BY_FW: + /* 0x4c[23] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0); + /* 0x4c[24] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1); + break; + case BT_8821C_1ANT_CTRL_BY_BT: + /* 0x4c[23] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0); + /* 0x4c[24] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x0); + /* no setup required, because antenna switch control value + * by BT vendor 0xac[1:0] + */ break; } /* PAPE, LNA_ON control by BT while WLAN off for current leakage issue */ - if (ctrl_type == BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT) { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x0); /* PAPE 0x64[29] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, - 0x0); /* LNA_ON 0x64[28] = 0 */ + if (ctrl_type == BT_8821C_1ANT_CTRL_BY_BT) { + /* PAPE 0x64[29] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x67, 0x20, 0x0); + /* LNA_ON 0x64[28] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x67, 0x10, 0x0); } else { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x1); /* PAPE 0x64[29] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, - 0x1); /* LNA_ON 0x64[28] = 1 */ + /* PAPE 0x64[29] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x67, 0x20, 0x1); + /* LNA_ON 0x64[28] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x67, 0x10, 0x1); } - -#if BT_8821C_1ANT_COEX_DBG - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", - u32tmp1, u32tmp2, u32tmp3); - BTC_TRACE(trace_buf); -#endif - } -void halbtc8821c1ant_set_rfe_type(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_set_rfe_type(struct btc_coexist *btc) { - struct btc_board_info *board_info = &btcoexist->board_info; - + struct btc_board_info *board_info = &btc->board_info; + struct rfe_type_8821c_1ant *rfe_type = &btc->rfe_type_8821c_1ant; /* the following setup should be got from Efuse in the future */ rfe_type->rfe_module_type = board_info->rfe_type & 0x1f; @@ -2451,305 +2255,229 @@ void halbtc8821c1ant_set_rfe_type(IN struct btc_coexist *btcoexist) switch (rfe_type->rfe_module_type) { case 0: - default: + case 8: + default: /*2-Ant, DPDT, WLG*/ rfe_type->ext_ant_switch_exist = TRUE; - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*2-Ant, DPDT, WLG*/ - rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_DPDT; + rfe_type->wlg_locate_at_btg = FALSE; rfe_type->ant_at_main_port = TRUE; break; case 1: + case 9: /*1-Ant, Main, WLG */ rfe_type->ext_ant_switch_exist = TRUE; - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, WLG */ - rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_SPDT; + rfe_type->wlg_locate_at_btg = FALSE; rfe_type->ant_at_main_port = TRUE; break; case 2: + case 10: /*1-Ant, Main, BTG */ rfe_type->ext_ant_switch_exist = TRUE; - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, BTG */ - rfe_type->wlg_Locate_at_btg = TRUE; + rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_SPDT; + rfe_type->wlg_locate_at_btg = TRUE; rfe_type->ant_at_main_port = TRUE; break; case 3: + case 11: /*1-Ant, Aux, WLG */ rfe_type->ext_ant_switch_exist = TRUE; - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, WLG */ - rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_DPDT; + rfe_type->wlg_locate_at_btg = FALSE; rfe_type->ant_at_main_port = FALSE; break; case 4: + case 12: /*1-Ant, Aux, BTG */ rfe_type->ext_ant_switch_exist = TRUE; - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, BTG */ - rfe_type->wlg_Locate_at_btg = TRUE; + rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_DPDT; + rfe_type->wlg_locate_at_btg = TRUE; rfe_type->ant_at_main_port = FALSE; break; case 5: - rfe_type->ext_ant_switch_exist = FALSE; /*2-Ant, no switch, WLG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_NONE; - rfe_type->wlg_Locate_at_btg = FALSE; + case 13: /*2-Ant, no switch, WLG*/ + rfe_type->ext_ant_switch_exist = FALSE; + rfe_type->ext_ant_switch_type = BT_8821C_1ANT_SWITCH_NONE; + rfe_type->wlg_locate_at_btg = FALSE; rfe_type->ant_at_main_port = TRUE; break; case 6: - rfe_type->ext_ant_switch_exist = FALSE; /*2-Ant, no antenna switch, WLG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_NONE; - rfe_type->wlg_Locate_at_btg = FALSE; + case 14: /*2-Ant, no antenna switch, WLG*/ + rfe_type->ext_ant_switch_exist = FALSE; + rfe_type->ext_ant_switch_type = BT_8821C_1ANT_SWITCH_NONE; + rfe_type->wlg_locate_at_btg = FALSE; rfe_type->ant_at_main_port = TRUE; break; case 7: - rfe_type->ext_ant_switch_exist = TRUE; /*2-Ant, DPDT, BTG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; - rfe_type->wlg_Locate_at_btg = TRUE; + case 15: /*2-Ant, DPDT, BTG*/ + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = BT_8821C_1ANT_USE_DPDT; + rfe_type->wlg_locate_at_btg = TRUE; rfe_type->ant_at_main_port = TRUE; break; } - -#if 0 - if (rfe_type->wlg_Locate_at_btg) - halbtc8821c1ant_set_int_block(btcoexist, FORCE_EXEC, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); - else - halbtc8821c1ant_set_int_block(btcoexist, FORCE_EXEC, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); -#endif - } - -void halbtc8821c1ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, - IN u8 phase) +static +void halbtc8821c1ant_set_ant_path(struct btc_coexist *btc, + u8 ant_pos_type, boolean force_exec, + u8 phase) { - struct btc_board_info *board_info = &btcoexist->board_info; - u32 cnt_bt_cal_chk = 0; - boolean is_in_mp_mode = FALSE; - u8 u8tmp = 0; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - u16 u16tmp1 = 0; - - - u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - /* To avoid indirect access fail */ - if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { - force_exec = TRUE; - coex_sta->gnt_error_cnt++; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + struct rfe_type_8821c_1ant *rfe_type = &btc->rfe_type_8821c_1ant; + u32 cnt_bt_cal_chk = 0, u32tmp1 = 0, u32tmp2 = 0; + u8 u8tmp = 0, ctrl_type, pos_type; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],(Before Ant Setup) 0x38= 0x%x\n", - u32tmp1); - BTC_TRACE(trace_buf); + if (!force_exec) { + if (coex_dm->cur_ant_pos_type == ((ant_pos_type << 8) + phase)) + return; } - -#if BT_8821C_1ANT_COEX_DBG - - u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0x54); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],(Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", - u32tmp3, u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],(Before Ant Setup) pre_ant_pos_type = 0x%x, cur_ant_pos_type = 0x%x\n", - coex_dm->pre_ant_pos_type, - coex_dm->cur_ant_pos_type); - BTC_TRACE(trace_buf); - + if (btc->dbg_mode) { + u32tmp1 = btc->btc_read_4byte(btc, 0xcbc); + u32tmp2 = btc->btc_read_4byte(btc, 0xcb4); + u8tmp = btc->btc_read_1byte(btc, 0x73); - if (!force_exec) { - if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) - return; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0xcbc = 0x%x, 0x73 = 0x%x\n", + u32tmp1, u32tmp2, u8tmp); + BTC_TRACE(trace_buf); } - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; - - switch (phase) { - case BT_8821C_1ANT_PHASE_COEX_POWERON: - - /* set Path control owner to WL at initial step */ - halbtc8821c1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8821C_1ANT_PCO_BTSIDE); + case BT_8821C_1ANT_PHASE_POWERON: - /* set GNT_BT to SW high */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW high */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + /* set Path control owner to BT at power-on step */ + halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_BTSIDE); - if (BTC_ANT_PATH_AUTO == ant_pos_type) + if (ant_pos_type == BTC_ANT_PATH_AUTO) ant_pos_type = BTC_ANT_PATH_BT; coex_sta->run_time_state = FALSE; - break; - case BT_8821C_1ANT_PHASE_COEX_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c1ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_1ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c1ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_1ANT_CTT_BT_VS_LTE, - 0xffff); - - /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ + case BT_8821C_1ANT_PHASE_INIT: + /* Disable LTE Coex Function in WiFi side ( + * this should be on if LTE coex is required) + */ + halbtc8821c1ant_ltecoex_enable(btc, 0x0); + + /* GNT_WL_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8821c1ant_ltecoex_table(btc, BT_8821C_1ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8821c1ant_ltecoex_table(btc, BT_8821C_1ANT_CTT_BT_VS_LTE, + 0xffff); + + /* Wait If BT IQK running, because Path control owner is at + * BT during BT IQK (setup by WiFi firmware) + */ while (cnt_bt_cal_chk <= 20) { - u8tmp = btcoexist->btc_read_1byte( - btcoexist, - 0x49c); + u8tmp = btc->btc_read_1byte(btc, 0x49c); cnt_bt_cal_chk++; if (u8tmp & BIT(1)) { - BTC_SPRINTF( - trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", - cnt_bt_cal_chk); - BTC_TRACE( - trace_buf); - delay_ms(50); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(10); } else { - BTC_SPRINTF( - trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", - cnt_bt_cal_chk); - BTC_TRACE( - trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); break; } } /* set Path control owner to WL at initial step */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); + halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE); /* set GNT_BT to SW high */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_1ANT_GNT_SET_TO_HIGH); /* Set GNT_WL to SW low */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_LOW); + BT_8821C_1ANT_GNT_SET_TO_LOW); coex_sta->run_time_state = FALSE; - if (BTC_ANT_PATH_AUTO == ant_pos_type) + if (ant_pos_type == BTC_ANT_PATH_AUTO) ant_pos_type = BTC_ANT_PATH_BT; - break; - case BT_8821C_1ANT_PHASE_WLANONLY_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c1ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_1ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c1ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_1ANT_CTT_BT_VS_LTE, - 0xffff); + case BT_8821C_1ANT_PHASE_WONLY: + /* Disable LTE Coex Function in WiFi side + *(this should be on if LTE coex is required) + */ + halbtc8821c1ant_ltecoex_enable(btc, 0x0); + + /* GNT_WL_LTE always = 1 + *(this should be config if LTE coex is required) + */ + halbtc8821c1ant_ltecoex_table(btc, BT_8821C_1ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 + *(this should be config if LTE coex is required) + */ + halbtc8821c1ant_ltecoex_table(btc, BT_8821C_1ANT_CTT_BT_VS_LTE, + 0xffff); /* set Path control owner to WL at initial step */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); + halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE); /* set GNT_BT to SW Low */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_LOW); + halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_GNT_SET_TO_LOW); /* Set GNT_WL to SW high */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_GNT_SET_TO_HIGH); coex_sta->run_time_state = FALSE; - if (BTC_ANT_PATH_AUTO == ant_pos_type) + if (ant_pos_type == BTC_ANT_PATH_AUTO) ant_pos_type = BTC_ANT_PATH_WIFI; - break; - case BT_8821C_1ANT_PHASE_WLAN_OFF: + case BT_8821C_1ANT_PHASE_WOFF: /* Disable LTE Coex Function in WiFi side */ - halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); + halbtc8821c1ant_ltecoex_enable(btc, 0x0); /* set Path control owner to BT */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_BTSIDE); - - /* Set Ext Ant Switch to BT control at wifi off step */ - halbtc8821c1ant_set_ext_ant_switch(btcoexist, - FORCE_EXEC, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE); + halbtc8821c1ant_coex_ctrl_owner(btc, + BT_8821C_1ANT_PCO_BTSIDE); coex_sta->run_time_state = FALSE; break; - case BT_8821C_1ANT_PHASE_2G_RUNTIME: - + case BT_8821C_1ANT_PHASE_2G: while (cnt_bt_cal_chk <= 20) { /* 0x49c[0]=1 WL IQK, 0x49c[1]=1 BT IQK*/ - u8tmp = btcoexist->btc_read_1byte( - btcoexist, - 0x49c); + u8tmp = btc->btc_read_1byte(btc, 0x49c); cnt_bt_cal_chk++; if (u8tmp & BIT(0)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### WL is IQK (wait cnt=%d)\n", + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ########### WL is IQK (wait cnt=%d)\n", cnt_bt_cal_chk); BTC_TRACE(trace_buf); - delay_ms(50); + delay_ms(10); } else if (u8tmp & BIT(1)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is IQK (wait cnt=%d)\n", + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is IQK (wait cnt=%d)\n", cnt_bt_cal_chk); BTC_TRACE(trace_buf); - delay_ms(50); + delay_ms(10); } else { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", cnt_bt_cal_chk); BTC_TRACE(trace_buf); break; @@ -2757,1036 +2485,1204 @@ void halbtc8821c1ant_set_ant_path(IN struct btc_coexist *btcoexist, } /* set Path control owner to WL at runtime step */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); + halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE); /* set GNT_BT to PTA */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_1ANT_SIG_STA_SET_BY_HW); + BT_8821C_1ANT_GNT_SET_BY_HW); - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_1ANT_SIG_STA_SET_BY_HW); + BT_8821C_1ANT_GNT_SET_BY_HW); coex_sta->run_time_state = TRUE; - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - if (rfe_type->wlg_Locate_at_btg) - ant_pos_type = - BTC_ANT_PATH_WIFI; + if (ant_pos_type == BTC_ANT_PATH_AUTO) { + if (rfe_type->wlg_locate_at_btg) + ant_pos_type = BTC_ANT_PATH_WIFI; else ant_pos_type = BTC_ANT_PATH_PTA; } - - if (rfe_type->wlg_Locate_at_btg) - halbtc8821c1ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); - else - halbtc8821c1ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); - break; - case BT_8821C_1ANT_PHASE_5G_RUNTIME: + case BT_8821C_1ANT_PHASE_5G: /* set Path control owner to WL at runtime step */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); + halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE); /* set GNT_BT to SW Hi */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_1ANT_SIG_STA_SET_BY_HW); + BT_8821C_1ANT_GNT_SET_BY_HW); /* Set GNT_WL to SW Hi */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_1ANT_GNT_SET_TO_HIGH); coex_sta->run_time_state = TRUE; - if (BTC_ANT_PATH_AUTO == ant_pos_type) { - /* if (rfe_type->ext_band_switch_exist) - ant_pos_type = BTC_ANT_PATH_PTA; - else */ - ant_pos_type = - BTC_ANT_PATH_WIFI5G; - } - - halbtc8821c1ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG); - + if (ant_pos_type == BTC_ANT_PATH_AUTO) + ant_pos_type = BTC_ANT_PATH_WIFI5G; break; - case BT_8821C_1ANT_PHASE_BTMPMODE: + case BT_8821C_1ANT_PHASE_BTMP: /* Disable LTE Coex Function in WiFi side */ - halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); + halbtc8821c1ant_ltecoex_enable(btc, 0x0); /* set Path control owner to WL */ - halbtc8821c1ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); + halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE); /* set GNT_BT to SW Hi */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_1ANT_GNT_SET_TO_HIGH); /* Set GNT_WL to SW Lo */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_LOW); + BT_8821C_1ANT_GNT_SET_TO_LOW); coex_sta->run_time_state = FALSE; /* Set Ext Ant Switch to BT side at BT MP mode */ - if (BTC_ANT_PATH_AUTO == ant_pos_type) + if (ant_pos_type == BTC_ANT_PATH_AUTO) ant_pos_type = BTC_ANT_PATH_BT; - break; - case BT_8821C_1ANT_PHASE_ANTENNA_DET: - halbtc8821c1ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8821C_1ANT_PCO_WLSIDE); + case BT_8821C_1ANT_PHASE_ANTDET: + halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE); /* set GNT_BT to high */ - halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_1ANT_GNT_SET_TO_HIGH); /* Set GNT_WL to high */ - halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_1ANT_GNT_SET_TO_HIGH); - if (BTC_ANT_PATH_AUTO == ant_pos_type) + if (ant_pos_type == BTC_ANT_PATH_AUTO) ant_pos_type = BTC_ANT_PATH_BT; coex_sta->run_time_state = FALSE; + break; + case BT_8821C_1ANT_PHASE_MCC: + /* set Path control owner to WL at runtime step */ + halbtc8821c1ant_coex_ctrl_owner(btc, BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to PTA */ + halbtc8821c1ant_set_gnt_bt(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_1ANT_GNT_SET_BY_HW); + + halbtc8821c1ant_set_gnt_wl(btc, BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_1ANT_GNT_SET_BY_HW); + + coex_sta->run_time_state = TRUE; + + if (ant_pos_type == BTC_ANT_PATH_AUTO) + ant_pos_type = BTC_ANT_PATH_BT; + break; + } + + if (phase == BT_8821C_1ANT_PHASE_WOFF) { + /* Set Ext Ant Switch to BT control at wifi off step */ + ctrl_type = BT_8821C_1ANT_CTRL_BY_BT; + pos_type = BT_8821C_1ANT_TO_NOCARE; + } else if (phase == BT_8821C_1ANT_PHASE_MCC) { + ctrl_type = BT_8821C_1ANT_CTRL_BY_FW; + pos_type = BT_8821C_1ANT_TO_NOCARE; + } else { + switch (ant_pos_type) { + case BTC_ANT_PATH_WIFI: + ctrl_type = BT_8821C_1ANT_CTRL_BY_BBSW; + pos_type = BT_8821C_1ANT_TO_WLG; + break; + case BTC_ANT_PATH_WIFI5G: + ctrl_type = BT_8821C_1ANT_CTRL_BY_BBSW; + pos_type = BT_8821C_1ANT_TO_WLA; + break; + case BTC_ANT_PATH_BT: + ctrl_type = BT_8821C_1ANT_CTRL_BY_BBSW; + pos_type = BT_8821C_1ANT_TO_BT; + break; + default: + case BTC_ANT_PATH_PTA: + ctrl_type = BT_8821C_1ANT_CTRL_BY_PTA; + pos_type = BT_8821C_1ANT_TO_NOCARE; + break; + } + } + + halbtc8821c1ant_set_ant_switch(btc, force_exec, ctrl_type, pos_type); + + if (btc->dbg_mode) { + u32tmp1 = btc->btc_read_4byte(btc, 0xcbc); + u32tmp2 = btc->btc_read_4byte(btc, 0xcb4); + u8tmp = btc->btc_read_1byte(btc, 0x73); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (After Ant Setup) 0xcb4 = 0x%x, 0xcbc = 0x%x, 0x73 = 0x%x\n", + u32tmp1, u32tmp2, u8tmp); + BTC_TRACE(trace_buf); + } +} + +/* ********************************************* + * + * Software Coex Mechanism start + * + * ********************************************* + */ + + + +/* ********************************************* + * + * Non-Software Coex Mechanism start + * + * ********************************************* + */ +static +u8 halbtc8821c1ant_action_algorithm(struct btc_coexist *btc) +{ + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + u8 algorithm = BT_8821C_1ANT_COEX_UNDEFINED; + u8 profile_map = 0; + + if (bt_link_info->sco_exist) + profile_map = profile_map | BIT(0); + + if (bt_link_info->hid_exist) + profile_map = profile_map | BIT(1); + + if (bt_link_info->a2dp_exist) + profile_map = profile_map | BIT(2); + + if (bt_link_info->pan_exist) + profile_map = profile_map | BIT(3); + switch (profile_map) { + default: + case 0: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_UNDEFINED; + break; + case 1: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_SCO; + break; + case 2: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_HID; + break; + case 3: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_HID; + break; + case 4: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_A2DP; + break; + case 5: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP ==> HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_HID_A2DP; + break; + case 6: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_HID_A2DP; + break; + case 7: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_HID_A2DP; break; - } - - if (phase != BT_8821C_1ANT_PHASE_WLAN_OFF) { - switch (ant_pos_type) { - case BTC_ANT_PATH_WIFI: - halbtc8821c1ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG); - break; - case BTC_ANT_PATH_WIFI5G - : - halbtc8821c1ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA); - break; - case BTC_ANT_PATH_BT: - halbtc8821c1ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT); - break; - default: - case BTC_ANT_PATH_PTA: - halbtc8821c1ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE); - break; - } - - } - -#if BT_8821C_1ANT_COEX_DBG - u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],(After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", - phase, u32tmp3, u8tmp, u32tmp1, u32tmp2); - - BTC_TRACE(trace_buf); -#endif -} - - -boolean halbtc8821c1ant_is_common_action(IN struct btc_coexist *btcoexist) -{ - boolean common = FALSE, wifi_connected = FALSE, wifi_busy = FALSE; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - if (!wifi_connected && - BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { + case 8: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); + "[BTCoex], BT Profile = PAN(EDR) only\n"); BTC_TRACE(trace_buf); - - common = TRUE; - } else if (wifi_connected && - (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status)) { + algorithm = BT_8821C_1ANT_COEX_PAN; + break; + case 9: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + "[BTCoex], BT Profile = SCO + PAN(EDR) ==> HID + PAN(EDR)\n"); BTC_TRACE(trace_buf); - - common = TRUE; - } else if (!wifi_connected && - (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { + algorithm = BT_8821C_1ANT_COEX_PAN_HID; + break; + case 10: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); + "[BTCoex], BT Profile = HID + PAN(EDR)\n"); BTC_TRACE(trace_buf); - - common = TRUE; - } else if (wifi_connected && - (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { + algorithm = BT_8821C_1ANT_COEX_PAN_HID; + break; + case 11: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi connected + BT connected-idle!!\n"); + "[BTCoex], BT Profile = SCO + HID + PAN(EDR) ==> HID + PAN(EDR)\n"); BTC_TRACE(trace_buf); - - common = TRUE; - } else if (!wifi_connected && - (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE != - coex_dm->bt_status)) { + algorithm = BT_8821C_1ANT_COEX_PAN_HID; + break; + case 12: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); + "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); BTC_TRACE(trace_buf); - - common = TRUE; - } else { - if (wifi_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); - BTC_TRACE(trace_buf); - } - - common = FALSE; + algorithm = BT_8821C_1ANT_COEX_PAN_A2DP; + break; + case 13: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_PAN_A2DP; + break; + case 14: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_PAN_A2DP; + break; + case 15: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_PAN_A2DP; + break; } - return common; + return algorithm; } - -/* ********************************************* - * - * Software Coex Mechanism start - * - * ********************************************* */ - - - -/* ********************************************* - * - * Non-Software Coex Mechanism start - * - * ********************************************* */ -void halbtc8821c1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_action_coex_all_off(struct btc_coexist *btc) { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c1ant_table(btc, NM_EXCU, 0); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 0); } -void halbtc8821c1ant_action_bt_hs(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_action_bt_whql_test(struct btc_coexist *btc) { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_1ANT_PHASE_2G); + halbtc8821c1ant_table(btc, NM_EXCU, 0); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); } -void halbtc8821c1ant_action_bt_relink(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_action_bt_relink(struct btc_coexist *btc) { - if (coex_sta->is_bt_multi_link == TRUE) - return; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + if ((!coex_sta->is_bt_multi_link && !bt_link_info->pan_exist) || + (bt_link_info->a2dp_exist && bt_link_info->hid_exist)) { + halbtc8821c1ant_table(btc, NM_EXCU, 0); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); + } } -void halbtc8821c1ant_action_bt_idle(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_action_bt_idle(struct btc_coexist *btc) { + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; boolean wifi_busy = FALSE; + u32 wifi_link_status = 0; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_U4_WIFI_LINK_STATUS, &wifi_link_status); if (!wifi_busy) { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 6); - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 3); - - } else { /* if wl busy */ - - if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + halbtc8821c1ant_table(btc, NM_EXCU, 7); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 32); + } else { /* if wl busy */ + /*for initiator scan on*/ + if ((coex_sta->bt_ble_scan_type & 0x2) && + BT_8821C_1ANT_BSTATUS_NCON_IDLE == coex_dm->bt_status) { - - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 33); + halbtc8821c1ant_table(btc, NM_EXCU, 2); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 36); } else { - - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 32); - + halbtc8821c1ant_table(btc, NM_EXCU, 2); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 33); } - } - } -void halbtc8821c1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_action_bt_inquiry(struct btc_coexist *btc) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = FALSE, wifi_busy = FALSE, - bt_busy = FALSE; - boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + boolean wifi_connected = FALSE, wifi_busy = FALSE; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + if (coex_sta->is_wifi_linkscan_process || + coex_sta->wifi_high_pri_task1 || + coex_sta->wifi_high_pri_task2) { + + if (coex_sta->bt_create_connection) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt page + wifi hi-pri task\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_table(btc, NM_EXCU, 1); - if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) - || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { + if (bt_link_info->a2dp_exist && + !bt_link_info->pan_exist) + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 17); + else if (coex_sta->wifi_high_pri_task1) + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 36); + else + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 33); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt inquiry + wifi hi-pri task\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_table(btc, NM_EXCU, 1); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 21); + } + } else if (wifi_busy) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); + "[BTCoex], bt inq/page + wifi busy\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + halbtc8821c1ant_table(btc, NM_EXCU, 1); + /* for android 6.0 remote name request */ + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 23); + } else if (wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt inq/page + wifi connected\n"); + BTC_TRACE(trace_buf); - if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 17); - else - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33); - } else if ((!wifi_connected) && (!wifi_scan)) { + halbtc8821c1ant_table(btc, NM_EXCU, 1); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 23); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt inq/page + wifi not-connected\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_table(btc, NM_EXCU, 0); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); + } +} - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); +static +void halbtc8821c1ant_action_bt_sco_hid_busy(struct btc_coexist *btc) +{ + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + boolean wifi_connected = FALSE, wifi_busy = FALSE, + wifi_cckdeadlock_ap = FALSE; + u32 wifi_bw = 1; + u8 iot_peer = BTC_IOT_PEER_UNKNOWN; - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (bt_link_info->pan_exist) { + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + btc->btc_get(btc, BTC_GET_U4_WIFI_BW, &wifi_bw); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_U1_IOT_PEER, &iot_peer); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + if (!wifi_busy) + wifi_busy = coex_sta->gl_wifi_busy; - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + if (iot_peer == BTC_IOT_PEER_ATHEROS && coex_sta->cck_lock_ever) + wifi_cckdeadlock_ap = TRUE; - } else if (bt_link_info->a2dp_exist) { + if (bt_link_info->sco_exist) { + if (coex_sta->is_bt_multi_link) { + halbtc8821c1ant_table(btc, NM_EXCU, 1); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 25); + } else { + halbtc8821c1ant_table(btc, NM_EXCU, 1); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 5); + } + } else if (coex_sta->is_hid_rcu) { + if (coex_sta->voice_over_HOGP) { /* voice by RCU */ + /* change coex table if slave latency support or not */ + if (!wifi_busy) + halbtc8821c1ant_table(btc, NM_EXCU, 7); + else if (coex_sta->bt_coex_supported_feature & BIT(11)) + halbtc8821c1ant_table(btc, NM_EXCU, 1); + else + halbtc8821c1ant_table(btc, NM_EXCU, 2); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16); + if (wifi_busy) + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 37); + else + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 6); + } else { /* RCU */ + if (!wifi_busy) + halbtc8821c1ant_table(btc, NM_EXCU, 7); + else if (coex_sta->bt_coex_supported_feature & BIT(11)) + halbtc8821c1ant_table(btc, NM_EXCU, 1); + else + halbtc8821c1ant_table(btc, NM_EXCU, 2); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + if (wifi_busy && coex_sta->wl_noisy_level == 0) + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 36); + else if (wifi_busy) + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 37); + else + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 6); + } } else { - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) - || (coex_sta->wifi_is_high_pri_task)) - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); - else - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 23); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + /* for HID exist */ + if (wifi_cckdeadlock_ap && + coex_sta->is_hid_low_pri_tx_overhead) { + halbtc8821c1ant_table(btc, NM_EXCU, 13); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 18); + } else if (coex_sta->is_hid_low_pri_tx_overhead) { + halbtc8821c1ant_table(btc, NM_EXCU, 1); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 18); + } else if (wifi_bw == 0) { /* if 11bg mode */ + halbtc8821c1ant_table(btc, NM_EXCU, 11); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 11); + } else { + halbtc8821c1ant_table(btc, NM_EXCU, 1); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 11); + } } } -void halbtc8821c1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist - *btcoexist) +static +void halbtc8821c1ant_action_bt_acl_busy(struct btc_coexist *btc) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = FALSE, wifi_busy = FALSE; - u32 wifi_bw = 1; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + boolean wifi_busy = FALSE, wifi_turbo = FALSE, + wifi_cckdeadlock_ap = FALSE, bt_slave_latency = FALSE, + ap_enable = FALSE; + u32 wifi_bw = 1; + u8 iot_peer = BTC_IOT_PEER_UNKNOWN; + + btc->btc_get(btc, BTC_GET_U4_WIFI_BW, &wifi_bw); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num); + btc->btc_get(btc, BTC_GET_U1_IOT_PEER, &iot_peer); + btc->btc_get(btc, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + if (!wifi_busy) + wifi_busy = coex_sta->gl_wifi_busy; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); + if (wifi_busy && coex_sta->wl_noisy_level == 0) + wifi_turbo = TRUE; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + if (iot_peer == BTC_IOT_PEER_ATHEROS && coex_sta->cck_lock_ever) + wifi_cckdeadlock_ap = TRUE; + if (coex_sta->bt_coex_supported_feature & BIT(11)) + bt_slave_latency = TRUE; + else + bt_slave_latency = FALSE; - if (bt_link_info->sco_exist) { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 5); - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 5); - } else { + if (bt_link_info->a2dp_exist && coex_sta->is_bt_a2dp_sink) { + if (ap_enable) + halbtc8821c1ant_table(btc, NM_EXCU, 0); + else if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 13); + else + halbtc8821c1ant_table(btc, NM_EXCU, 1); - if (coex_sta->is_hid_low_pri_tx_overhead) { - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 18); - } else if (wifi_bw == 0) { /* if 11bg mode */ + if (ap_enable) + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); + else + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 12); + } else if (bt_link_info->a2dp_only) { /* A2DP */ + if (wifi_busy && (coex_sta->bt_ble_scan_type & 0x2)) { + if (coex_sta->wl_noisy_level == 0 && + wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 10); + else if (coex_sta->wl_noisy_level == 0 && + !wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 9); + else + halbtc8821c1ant_table(btc, NM_EXCU, 1); + } else if (wifi_busy && !(coex_sta->bt_ble_scan_type & 0x2)) { + if (coex_sta->wl_noisy_level == 0 && + wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 13); + else + halbtc8821c1ant_table(btc, NM_EXCU, 1); + } else { /* wifi idle */ + halbtc8821c1ant_table(btc, NM_EXCU, 7); + } - if (coex_sta->is_bt_multi_link) { - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 11); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 11); - } else { - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 11); - } - } else { - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 11); + if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy) + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 26); + else + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 7); + } else if ((bt_link_info->a2dp_exist && bt_link_info->pan_exist) || + (bt_link_info->hid_exist && bt_link_info->a2dp_exist && + bt_link_info->pan_exist)) { + /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ + if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 13); + else if (bt_link_info->hid_exist) + halbtc8821c1ant_table(btc, NM_EXCU, 1); + else if (wifi_turbo) + halbtc8821c1ant_table(btc, NM_EXCU, 8); + else + halbtc8821c1ant_table(btc, NM_EXCU, 4); + + if (wifi_busy) + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 13); + else + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 14); + } else if (bt_link_info->hid_exist && coex_sta->is_hid_rcu && + coex_sta->voice_over_HOGP && bt_link_info->a2dp_exist) { + /* RCU voice + A2DP */ + /* change coex table if slave latency support or not */ + if (wifi_busy && !bt_slave_latency) { + if (coex_sta->wl_noisy_level == 0 && + wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 10); + else if (coex_sta->wl_noisy_level == 0 && + !wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 9); + else + halbtc8821c1ant_table(btc, NM_EXCU, 1); + } else if (wifi_busy && bt_slave_latency) { + if (coex_sta->wl_noisy_level == 0 && + wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 13); + else + halbtc8821c1ant_table(btc, NM_EXCU, 1); + } else { /* wifi idle */ + halbtc8821c1ant_table(btc, NM_EXCU, 7); + } + + if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy) + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 10); + else + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 13); + } else if (bt_link_info->hid_exist && coex_sta->is_hid_rcu && + bt_link_info->a2dp_exist) { + /* RCU + A2DP */ + /* change coex table if slave latency support or not */ + if (wifi_busy && !bt_slave_latency) { + if (coex_sta->wl_noisy_level == 0 && + wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 10); + else if (coex_sta->wl_noisy_level == 0 && + !wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 9); + else + halbtc8821c1ant_table(btc, NM_EXCU, 1); + } else if (wifi_busy && bt_slave_latency) { + if (coex_sta->wl_noisy_level == 0 && + wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 13); + else + halbtc8821c1ant_table(btc, NM_EXCU, 1); + } else { /* wifi idle */ + halbtc8821c1ant_table(btc, NM_EXCU, 7); } + + if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy) + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 26); + else + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 7); + } else if (bt_link_info->hid_exist && bt_link_info->a2dp_exist) { + /* HID+A2DP */ + if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 13); + else if (wifi_bw == 0)/* if 11bg mode */ + halbtc8821c1ant_table(btc, NM_EXCU, 12); + else + halbtc8821c1ant_table(btc, NM_EXCU, 1); + + if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy) + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 26); + else + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 7); + } else if (bt_link_info->pan_only || + (bt_link_info->hid_exist && bt_link_info->pan_exist)) { + /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) + halbtc8821c1ant_table(btc, NM_EXCU, 13); + else if (bt_link_info->hid_exist) + halbtc8821c1ant_table(btc, NM_EXCU, 1); + else if (wifi_turbo || iot_peer == BTC_IOT_PEER_CISCO) + halbtc8821c1ant_table(btc, NM_EXCU, 8); + else + halbtc8821c1ant_table(btc, NM_EXCU, 4); + + if (!wifi_busy) + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 4); + else + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 3); + } else { + /* BT no-profile busy (0x9) */ + halbtc8821c1ant_table(btc, NM_EXCU, 4); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 33); } } -void halbtc8821c1ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_action_bt_mr(struct btc_coexist *btc) { + struct wifi_link_info_8821c_1ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_1ant; - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + if (!wifi_link_info_ext->is_all_under_5g) { + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_1ANT_PHASE_2G); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8821C_1ANT_PHASE_5G_RUNTIME); -} + halbtc8821c1ant_table(btc, NM_EXCU, 8); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 32); + } else { + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_1ANT_PHASE_5G); + halbtc8821c1ant_table(btc, NM_EXCU, 0); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); + } +} -void halbtc8821c1ant_action_wifi_only(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_action_wifi_under5g(struct btc_coexist *btc) { - halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - halbtc8821c1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 10); + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_1ANT_PHASE_5G); + halbtc8821c1ant_table(btc, NM_EXCU, 0); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); } -void halbtc8821c1ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_action_wifi_only(struct btc_coexist *btc) { - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 5); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821c1ant_table(btc, FC_EXCU, 10); + halbtc8821c1ant_tdma(btc, FC_EXCU, FALSE, 8); } - -void halbtc8821c1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_action_wifi_native_lps(struct btc_coexist *btc) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - - if ((BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); - else if (!bt_link_info->pan_exist) - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - else - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); + halbtc8821c1ant_table(btc, NM_EXCU, 5); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); } - -void halbtc8821c1ant_action_wifi_linkscan_process(IN struct btc_coexist - *btcoexist) +#if 0 +static +void halbtc8821c1ant_action_wifi_cck_dead_lock(struct btc_coexist *btc) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; - if (bt_link_info->pan_exist) { + if (bt_link_info->hid_exis && bt_link_info->a2dp_exist && + !bt_link_info->pan_exist) { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + if (coex_sta->cck_lock || coex_sta->cck_lock_warn) { + halbtc8821c1ant_table(btc, NM_EXCU, 13); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 28); + } else { + halbtc8821c1ant_table(btc, NM_EXCU, 13); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 8); + } + } +} +#endif - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); +static +void halbtc8821c1ant_action_wifi_linkscan(struct btc_coexist *btc) +{ + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + if (bt_link_info->pan_exist) { + halbtc8821c1ant_table(btc, NM_EXCU, 4); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 22); } else if (bt_link_info->a2dp_exist) { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 27); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8821c1ant_table(btc, NM_EXCU, 4); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 27); } else { - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8821c1ant_table(btc, NM_EXCU, 4); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 21); } +} +static +void halbtc8821c1ant_action_wifi_not_connected(struct btc_coexist *btc) +{ + /* tdma and coex table */ + halbtc8821c1ant_table(btc, NM_EXCU, 0); + halbtc8821c1ant_tdma(btc, FC_EXCU, FALSE, 8); } -void halbtc8821c1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist - *btcoexist) +static +void halbtc8821c1ant_action_wifi_connected(struct btc_coexist *btc) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = FALSE, wifi_turbo = FALSE; - u32 wifi_bw = 1; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + u32 wifi_bw; + u8 iot_peer = BTC_IOT_PEER_UNKNOWN, algorithm; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); + btc->btc_get(btc, BTC_GET_U4_WIFI_BW, &wifi_bw); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); + if (bt_link_info->bt_link_exist) { + btc->btc_get(btc, BTC_GET_U1_IOT_PEER, &iot_peer); - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = TRUE; + if (iot_peer == BTC_IOT_PEER_CISCO) { + if (wifi_bw == BTC_WIFI_BW_HT40) + halbtc8821c1ant_limited_rx(btc, NM_EXCU, FALSE, + TRUE, 0x10); + else + halbtc8821c1ant_limited_rx(btc, NM_EXCU, FALSE, + TRUE, 0x8); + } + } - if ((coex_sta->bt_relink_downcount != 0) - && (!bt_link_info->pan_exist) && (wifi_busy)) { + algorithm = halbtc8821c1ant_action_algorithm(btc); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); + coex_dm->cur_algorithm = algorithm; - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_BUSY || + coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_SCO_BUSY) { - } else if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) { - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 12); - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - } else if (bt_link_info->a2dp_only) { /* A2DP */ + if (bt_link_info->hid_only) /* HID only */ + halbtc8821c1ant_action_bt_sco_hid_busy(btc); + else + halbtc8821c1ant_action_bt_acl_busy(btc); - halbtc8821c1ant_ps_tdma(btcoexist, - NORMAL_EXEC, TRUE, 7); + } else if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_SCO_BUSY) { + halbtc8821c1ant_action_bt_sco_hid_busy(btc); + } else { + halbtc8821c1ant_action_bt_idle(btc); + } +} - if (wifi_turbo) - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (((bt_link_info->a2dp_exist) && - (bt_link_info->pan_exist)) || - (bt_link_info->hid_exist && bt_link_info->a2dp_exist && - bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ +static +void halbtc8821c1ant_action_wifi_multiport25g(struct btc_coexist *btc) +{ + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; - if (wifi_busy) - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 13); - else - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 14); + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_1ANT_PHASE_MCC); - if (bt_link_info->hid_exist) - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - else if (wifi_turbo) - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - } else if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { /* HID+A2DP */ - - if (wifi_bw == 0) {/* if 11bg mode */ - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 12); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, - 8); - } else { - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, - 8); - } + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_BTCQDDR, TRUE); - } else if ((bt_link_info->pan_only) - || (bt_link_info->hid_exist && bt_link_info->pan_exist)) { - /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport25g(), BT Relink!!\n"); + BTC_TRACE(trace_buf); - if (!wifi_busy) - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 4); - else - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 3); - - if (bt_link_info->hid_exist) - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 1); - else if (wifi_turbo) - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - else - halbtc8821c1ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); + halbtc8821c1ant_table(btc, NM_EXCU, 15); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); + } else if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport25g(), BT Inq-Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_table(btc, NM_EXCU, 15); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); } else { - /* BT no-profile busy (0x9) */ - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33); - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); - } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport25g(), BT idle or busy!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_table(btc, NM_EXCU, 15); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); + } } -void halbtc8821c1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_action_wifi_multiport2g(struct btc_coexist *btc) { - /* tdma and coex table */ - halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + struct btc_multi_port_tdma_info multiport_tdma_para; + u32 traffic_dir; - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); -} + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_BTCQDDR, TRUE); + btc->btc_get(btc, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &traffic_dir); -void halbtc8821c1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_busy = FALSE; - boolean wifi_under_5g = FALSE; + if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, BT Relink!!\n"); + BTC_TRACE(trace_buf); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CoexForWifiConnect()===>\n"); - BTC_TRACE(trace_buf); + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_1ANT_PHASE_2G); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + halbtc8821c1ant_table(btc, NM_EXCU, 0); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); + } else if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, BT Inq-Page!!\n"); + BTC_TRACE(trace_buf); - if (wifi_under_5g) { + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_1ANT_PHASE_2G); + halbtc8821c1ant_table(btc, NM_EXCU, 1); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 33); + } else if (coex_sta->num_of_profile == 0) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!!\n"); + "[BTCoex], wifi_multiport2g, BT idle!!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_wifi_under5g(btcoexist); - return; - } + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_1ANT_PHASE_2G); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); + /* for P2P-GO only A2DP sink */ + if (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO && + traffic_dir == BTC_WIFI_TRAFFIC_RX) { + halbtc8821c1ant_table(btc, NM_EXCU, 2); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 33); + } else { + halbtc8821c1ant_table(btc, NM_EXCU, 0); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); + } + } else if (coex_sta->is_wifi_linkscan_process) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, WL scan!!\n"); + BTC_TRACE(trace_buf); - if (BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_1ANT_PHASE_2G); + halbtc8821c1ant_action_wifi_linkscan(btc); + } else { - if (bt_link_info->hid_only) /* HID only */ - halbtc8821c1ant_action_bt_sco_hid_only_busy(btcoexist); - else - halbtc8821c1ant_action_wifi_connected_bt_acl_busy( - btcoexist); - - } else if ((BT_8821C_1ANT_BT_STATUS_SCO_BUSY == - coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == - coex_dm->bt_status)) - halbtc8821c1ant_action_bt_sco_hid_only_busy(btcoexist); - else - halbtc8821c1ant_action_bt_idle(btcoexist); + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_1ANT_PHASE_2G); -} + if (!coex_sta->is_bt_multi_link && + (bt_link_info->sco_exist || bt_link_info->hid_exist || + coex_sta->is_hid_rcu)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, 2G multi-port + BT HID/HFP/RCU!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_table(btc, NM_EXCU, 0); + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); + } else { + switch (btc->wifi_link_info.link_mode) { + #if 0 + case BTC_LINK_2G_SCC_GO_STA: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, 2G_SCC_GO_STA + BT busy!!\n"); + BTC_TRACE(trace_buf); -void halbtc8821c1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) -{ - u8 algorithm = 0; + halbtc8821c1ant_table(btc, NM_EXCU, 4); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 201); + break; + case BTC_LINK_ONLY_GO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_singleport2g, Only_P2PGO with client-join + BT busy!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_table(btc, NM_EXCU, 4); + halbtc8821c1ant_tdma(btc, NM_EXCU, TRUE, 202); + break; + #endif + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, Other multi-port + BT busy!!\n"); + BTC_TRACE(trace_buf); - algorithm = halbtc8821c1ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; + if (bt_link_info->a2dp_exist) + halbtc8821c1ant_table(btc, NM_EXCU, 0); + else + halbtc8821c1ant_table(btc, NM_EXCU, 5); - if (!halbtc8821c1ant_is_common_action(btcoexist)) { - switch (coex_dm->cur_algorithm) { - case BT_8821C_1ANT_COEX_ALGO_SCO: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = SCO.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_sco(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_hid(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_a2dp(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_a2dp_pan_hs(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR).\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_pan_edr(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_PANHS: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HS mode.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_pan_hs(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_pan_edr_a2dp(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_PANEDR_HID: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_pan_edr_hid(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_hid_a2dp_pan_edr(btcoexist); */ - break; - case BT_8821C_1ANT_COEX_ALGO_HID_A2DP: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = HID+A2DP.\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_action_hid_a2dp(btcoexist); */ - break; - default: - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action algorithm = coexist All Off!!\n"); - BTC_TRACE(trace_buf); - /* halbtc8821c1ant_coex_all_off(btcoexist); */ - break; + halbtc8821c1ant_tdma(btc, NM_EXCU, FALSE, 8); + break; + } } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; } } - -void halbtc8821c1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_run_coex(struct btc_coexist *btc, u8 reason) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean wifi_connected = FALSE, bt_hs_on = FALSE; - boolean increase_scan_dev_num = FALSE; - boolean bt_ctrl_agg_buf_size = FALSE; - boolean miracast_plus_bt = FALSE, wifi_under_5g = FALSE; - u8 agg_buf_size = 5; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0, wifi_bw; - u8 iot_peer = BTC_IOT_PEER_UNKNOWN; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + struct wifi_link_info_8821c_1ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_1ant; + boolean wifi_connected = FALSE, wifi_32k = FALSE; boolean scan = FALSE, link = FALSE, roam = FALSE, under_4way = FALSE; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); + btc->btc_get(btc, BTC_GET_BL_WIFI_SCAN, &scan); + btc->btc_get(btc, BTC_GET_BL_WIFI_LINK, &link); + btc->btc_get(btc, BTC_GET_BL_WIFI_ROAM, &roam); + btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way); + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + btc->btc_get(btc, BTC_GET_BL_WIFI_LW_PWR_STATE, &wifi_32k); + + if (scan || link || roam || under_4way || + reason == BT_8821C_1ANT_RSN_2GSCANSTART || + reason == BT_8821C_1ANT_RSN_2GSWITCHBAND || + reason == BT_8821C_1ANT_RSN_2GCONSTART || + reason == BT_8821C_1ANT_RSN_2GSPECIALPKT) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + coex_sta->is_wifi_linkscan_process = TRUE; + } else { + coex_sta->is_wifi_linkscan_process = FALSE; + } + + /* update wifi_link_info variable */ + halbtc8821c1ant_update_wifi_link_info(btc, reason); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); + "[BTCoex], RunCoexistMechanism()===> reason = %d\n", + reason); BTC_TRACE(trace_buf); - if (btcoexist->manual_control) { + if (btc->manual_control) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); BTC_TRACE(trace_buf); return; } - if (btcoexist->stop_coex_dm) { + if (btc->stop_coex_dm) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); BTC_TRACE(trace_buf); return; } if (coex_sta->under_ips) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), wifi is under IPS !!!\n"); + "[BTCoex], RunCoexistMechanism(), return for wifi is under IPS !!!\n"); BTC_TRACE(trace_buf); return; } - if ((coex_sta->under_lps) && - (coex_dm->bt_status != BT_8821C_1ANT_BT_STATUS_ACL_BUSY)) { + if (coex_sta->under_lps && wifi_32k) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); + "[BTCoex], RunCoexistMechanism(), return for wifi is under LPS-32K !!!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_wifi_native_lps(btcoexist); return; } if (!coex_sta->run_time_state) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], return for run_time_state = FALSE !!!\n"); + "[BTCoex], return for run_time_state = FALSE !!!\n"); BTC_TRACE(trace_buf); return; } - if (coex_sta->freeze_coexrun_by_btinfo) { + if (coex_sta->freeze_coexrun_by_btinfo && !coex_sta->is_setup_link) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); + "[BTCoex], return for freeze_coexrun_by_btinfo\n"); BTC_TRACE(trace_buf); return; } - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + coex_sta->coex_run_cnt++; + + if (coex_sta->msft_mr_exist && wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), microsoft MR!!\n"); + BTC_TRACE(trace_buf); - if ((wifi_under_5g) && - (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G) && - (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G_NOFORSCAN)) { + coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_BTMR; + halbtc8821c1ant_action_bt_mr(btc); + return; + } + if (wifi_link_info_ext->is_all_under_5g) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], WiFi is under 5G!!!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_wifi_under5g(btcoexist); + coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_5G; + halbtc8821c1ant_action_wifi_under5g(btc); return; - } else { + } + + if (wifi_link_info_ext->is_mcc_25g) { /* not iclude scan action */ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 2G!!!\n"); + "[BTCoex], WiFi is under mcc dual-band!!!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); + coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_25GMPORT; + halbtc8821c1ant_action_wifi_multiport25g(btc); + return; } - if (coex_sta->bt_whck_test) { + if (wifi_link_info_ext->num_of_active_port > 1 || + (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO && + !btc->wifi_link_info.bhotspot && + btc->wifi_link_info.bany_client_join_go)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); + "[BTCoex], WiFi is under scc-2g/mcc-2g/p2pGO-only!!!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_bt_whql_test(btcoexist); + + if (btc->wifi_link_info.link_mode == + BTC_LINK_ONLY_GO) + coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_2GGO; + else + coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_2GMPORT; + halbtc8821c1ant_action_wifi_multiport2g(btc); return; } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is single-port 2G!!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->wl_coex_mode = BT_8821C_1ANT_WLINK_2G1PORT; + + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_1ANT_PHASE_2G); + + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_BTCQDDR, TRUE); + if (coex_sta->bt_disabled) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BT is disabled !!!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_wifi_only(btcoexist); + halbtc8821c1ant_action_wifi_only(btc); return; } - if (coex_sta->c2h_bt_inquiry_page) { + if (coex_sta->under_lps && !coex_sta->force_lps_ctrl && + !coex_sta->acl_busy) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); + "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_bt_inquiry(btcoexist); + halbtc8821c1ant_action_wifi_native_lps(btc); return; } - if (coex_sta->is_setupLink) { + if (coex_sta->bt_whck_test) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is re-link !!!\n"); + "[BTCoex], BT is under WHCK TEST!!!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_bt_relink(btcoexist); + halbtc8821c1ant_action_bt_whql_test(btc); return; } - if ((BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) - increase_scan_dev_num = TRUE; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, - &increase_scan_dev_num); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); + "[BTCoex], BT is re-link !!!\n"); BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) - miracast_plus_bt = TRUE; - else - miracast_plus_bt = FALSE; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - -#if 0 - halbtc8821c1ant_limited_rx(btcoexist, NORMAL_EXEC, FALSE, - FALSE, 0x5); -#endif - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", - scan, link, roam, under_4way); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_linkscan_process(btcoexist); - } else - halbtc8821c1ant_action_wifi_multi_port(btcoexist); - + halbtc8821c1ant_action_bt_relink(btc); return; - } else { - - miracast_plus_bt = FALSE; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - } - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - if ((bt_link_info->bt_link_exist) && (wifi_connected)) { - - btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); - - if (BTC_IOT_PEER_CISCO == iot_peer) { - - if (BTC_WIFI_BW_HT40 == wifi_bw) - halbtc8821c1ant_limited_rx(btcoexist, - NORMAL_EXEC, FALSE, TRUE, 0x10); - else - halbtc8821c1ant_limited_rx(btcoexist, - NORMAL_EXEC, FALSE, TRUE, 0x8); - } } - halbtc8821c1ant_run_sw_coexist_mechanism( - btcoexist); /* just print debug message */ - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (bt_hs_on) { + if (coex_sta->c2h_bt_inquiry_page) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is hs\n"); + "[BTCoex], BT is under inquiry/page scan !!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_bt_hs(btcoexist); + halbtc8821c1ant_action_bt_inquiry(btc); return; } - if ((BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { + if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_NCON_IDLE || + coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_CON_IDLE) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is idle\n"); + "############# [BTCoex], BT Is idle\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_bt_idle(btcoexist); + halbtc8821c1ant_action_bt_idle(btc); return; } - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", - scan, link, roam, under_4way); - BTC_TRACE(trace_buf); - + if (coex_sta->is_wifi_linkscan_process) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], wifi is under linkscan process!!\n"); BTC_TRACE(trace_buf); + halbtc8821c1ant_action_wifi_linkscan(btc); + return; + } - halbtc8821c1ant_action_wifi_linkscan_process(btcoexist); - } else if (wifi_connected) { + if (wifi_connected) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], wifi is under connected!!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_wifi_connected(btcoexist); + halbtc8821c1ant_action_wifi_connected(btc); } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], wifi is under not-connected!!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_wifi_not_connected(btcoexist); + halbtc8821c1ant_action_wifi_not_connected(btc); } } -void halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +static +void halbtc8821c1ant_init_coex_dm(struct btc_coexist *btc) { + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + /* force to reset coex mechanism */ - halbtc8821c1ant_low_penalty_ra(btcoexist, FORCE_EXEC, FALSE); + halbtc8821c1ant_low_penalty_ra(btc, FC_EXCU, FALSE, 0); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Coex Mechanism Init!!\n"); BTC_TRACE(trace_buf); coex_sta->pop_event_cnt = 0; - coex_sta->cnt_RemoteNameReq = 0; - coex_sta->cnt_ReInit = 0; - coex_sta->cnt_setupLink = 0; - coex_sta->cnt_IgnWlanAct = 0; - coex_sta->cnt_Page = 0; - coex_sta->cnt_RoleSwitch = 0; + coex_sta->cnt_remote_name_req = 0; + coex_sta->cnt_reinit = 0; + coex_sta->cnt_setup_link = 0; + coex_sta->cnt_ign_wlan_act = 0; + coex_sta->cnt_page = 0; + coex_sta->cnt_role_switch = 0; coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; + coex_dm->setting_tdma = FALSE; - halbtc8821c1ant_query_bt_info(btcoexist); + halbtc8821c1ant_query_bt_info(btc); } -void halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean back_up, IN boolean wifi_only) +static +void halbtc8821c1ant_init_hw_config(struct btc_coexist *btc, boolean back_up, + boolean wifi_only) { - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - u16 u16tmp1 = 0; - u8 i; - struct btc_board_info *board_info = &btcoexist->board_info; - + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + u16 u16tmp1 = 0; + u8 i; + struct btc_board_info *board_info = &btc->board_info; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], 1Ant Init HW Config!!\n"); BTC_TRACE(trace_buf); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u32tmp3 = btc->btc_read_4byte(btc, 0xcb4); + u32tmp1 = halbtc8821c1ant_read_indirect_reg(btc, 0x38); + u32tmp2 = halbtc8821c1ant_read_indirect_reg(btc, 0x54); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex],(Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + "[BTCoex],(Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", u32tmp3, u32tmp1, u32tmp2); BTC_TRACE(trace_buf); - +#if 0 coex_sta->bt_coex_supported_feature = 0; coex_sta->bt_coex_supported_version = 0; coex_sta->bt_ble_scan_type = 0; coex_sta->bt_ble_scan_para[0] = 0; coex_sta->bt_ble_scan_para[1] = 0; coex_sta->bt_ble_scan_para[2] = 0; +#endif coex_sta->bt_reg_vendor_ac = 0xffff; coex_sta->bt_reg_vendor_ae = 0xffff; coex_sta->isolation_btween_wb = BT_8821C_1ANT_DEFAULT_ISOLATION; @@ -3794,97 +3690,89 @@ void halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, coex_sta->bt_relink_downcount = 0; coex_sta->is_set_ps_state_fail = FALSE; coex_sta->cnt_set_ps_state_fail = 0; + coex_sta->wl_rx_rate = BTC_UNKNOWN; + coex_sta->wl_rts_rx_rate = BTC_UNKNOWN; + coex_sta->wl_center_channel = 0; + coex_sta->coex_run_cnt = 0; for (i = 0; i <= 9; i++) coex_sta->bt_afh_map[i] = 0; /* Setup RF front end type */ - halbtc8821c1ant_set_rfe_type(btcoexist); + halbtc8821c1ant_set_rfe_type(btc); /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; + coex_sta->cut_version = (btc->btc_read_1byte(btc, 0xf1) & 0xf0) >> 4; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ + /* enable TBTT nterrupt */ + btc->btc_write_1byte_bitmask(btc, 0x550, 0x8, 0x1); /* BT report packet sample rate */ - btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); + btc->btc_write_1byte(btc, 0x790, 0x5); /* Init 0x778 = 0x1 for 1-Ant */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + btc->btc_write_1byte(btc, 0x778, 0x1); /* Enable PTA (3-wire function form BT side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); + btc->btc_write_1byte_bitmask(btc, 0x40, 0x20, 0x1); + btc->btc_write_1byte_bitmask(btc, 0x41, 0x02, 0x1); /* Enable PTA (tx/rx signal form WiFi side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); + btc->btc_write_1byte_bitmask(btc, 0x4c6, 0x10, 0x1); /* set GNT_BT=1 for coex table select both */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); + btc->btc_write_1byte_bitmask(btc, 0x763, 0x10, 0x1); - halbtc8821c1ant_enable_gnt_to_gpio(btcoexist, TRUE); + halbtc8821c1ant_enable_gnt_to_gpio(btc, TRUE); #if 0 /* check if WL firmware download ok */ - /*if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)*/ - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ONOFF, TRUE); + /*if (btc->btc_read_1byte(btc, 0x80) == 0xc6)*/ + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ONOFF, TRUE); #endif /* PTA parameter */ - halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); - - halbtc8821c1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - psd_scan->ant_det_is_ant_det_available = TRUE; + halbtc8821c1ant_table(btc, FC_EXCU, 0); + halbtc8821c1ant_tdma(btc, FC_EXCU, FALSE, 8); /* Antenna config */ if (coex_sta->is_rf_state_off) { + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_1ANT_PHASE_WOFF); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_WLAN_OFF); - - btcoexist->stop_coex_dm = TRUE; + btc->stop_coex_dm = TRUE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** halbtc8821c1ant_init_hw_config (RF Off)**********\n"); + "[BTCoex], ********** %s (RF Off)**********\n", + __func__); BTC_TRACE(trace_buf); } else if (wifi_only) { coex_sta->concurrent_rx_mode_on = FALSE; - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_WLANONLY_INIT); + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_WIFI, FC_EXCU, + BT_8821C_1ANT_PHASE_WONLY); - btcoexist->stop_coex_dm = TRUE; + btc->stop_coex_dm = TRUE; } else { /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); + btc->btc_write_1byte_bitmask(btc, 0x45e, 0x8, 0x1); coex_sta->concurrent_rx_mode_on = TRUE; - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */ - - /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx, mask Tx only */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0); + btc->btc_set_rf_reg(btc, BTC_RF_A, 0x1, 0x2, 0x0); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_COEX_INIT); + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_1ANT_PHASE_INIT); - btcoexist->stop_coex_dm = FALSE; + btc->stop_coex_dm = FALSE; } - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u32tmp3 = btc->btc_read_4byte(btc, 0xcb4); + u32tmp1 = halbtc8821c1ant_read_indirect_reg(btc, 0x38); + u32tmp2 = halbtc8821c1ant_read_indirect_reg(btc, 0x54); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (After Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + "[BTCoex], (After Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", u32tmp3, u32tmp1, u32tmp2); BTC_TRACE(trace_buf); - } @@ -3894,220 +3782,302 @@ void halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, * ************************************************************ * extern function start with ex_halbtc8821c1ant_ * ************************************************************ */ -void ex_halbtc8821c1ant_power_on_setting(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c1ant_power_on_setting(struct btc_coexist *btc) { - struct btc_board_info *board_info = &btcoexist->board_info; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct btc_board_info *board_info = &btc->board_info; u8 u8tmp = 0x0; u16 u16tmp = 0x0; - u32 value = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Execute 8821c 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); - BTC_TRACE(trace_buf); + u32 value = 0; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - (board_info->btdm_ant_det_finish ? "Yes" : "No"), - board_info->btdm_ant_num_by_ant_det); + "[BTCoex], Execute %s !!\n", __func__); BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = TRUE; + btc->stop_coex_dm = TRUE; coex_sta->is_rf_state_off = FALSE; - psd_scan->ant_det_is_ant_det_available = FALSE; /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + u16tmp = btc->btc_read_2byte(btc, 0x2); + btc->btc_write_2byte(btc, 0x2, u16tmp | BIT(0) | BIT(1)); - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + /* Local setting bit define + * BIT0: "0" for no antenna inverse; "1" for antenna inverse + * BIT1: "0" for internal switch; "1" for external switch + * BIT2: "0" for one antenna; "1" for two antenna + * NOTE: here default all internal switch + * and 1-antenna ==> BIT1=0 and BIT2=0 + */ /* Set Antenna Path to BT side */ /* Check efuse 0xc3[6] for Single Antenna Path */ if (board_info->single_ant_path == 0) { - board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; u8tmp = 1; } else if (board_info->single_ant_path == 1) { - board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; u8tmp = 0; } BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d\n", + "[BTCoex], (Power On) single_ant_path = %d, btdm_ant_pos = %d\n", board_info->single_ant_path , board_info->btdm_ant_pos); BTC_TRACE(trace_buf); /* Setup RF front end type */ - halbtc8821c1ant_set_rfe_type(btcoexist); + halbtc8821c1ant_set_rfe_type(btc); /* Set Antenna Path to BT side */ - halbtc8821c1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_COEX_POWERON); - - /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */ - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_1ANT_PHASE_POWERON); + + /* Save"single antenna position" info in Local register setting for + * FW reading, because FW may not ready at power on + */ + if (btc->chip_interface == BTC_INTF_PCI) + btc->btc_write_local_reg_1byte(btc, 0x3e0, u8tmp); + else if (btc->chip_interface == BTC_INTF_USB) + btc->btc_write_local_reg_1byte(btc, 0xfe08, u8tmp); + else if (btc->chip_interface == BTC_INTF_SDIO) + btc->btc_write_local_reg_1byte(btc, 0x60, u8tmp); /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - halbtc8821c1ant_enable_gnt_to_gpio(btcoexist, TRUE); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x\n", - halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); - BTC_TRACE(trace_buf); + halbtc8821c1ant_enable_gnt_to_gpio(btc, TRUE); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n", - btcoexist->btc_read_4byte(btcoexist, 0x70), - btcoexist->btc_read_4byte(btcoexist, 0xcb4)); - BTC_TRACE(trace_buf); + if (btc->dbg_mode) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LTE coex Reg 0x38 (Power-On) = 0x%x\n", + halbtc8821c1ant_read_indirect_reg(btc, 0x38)); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MACReg 0x70/ BBReg 0xcb4 (Power-On) = 0x%x/ 0x%x\n", + btc->btc_read_4byte(btc, 0x70), + btc->btc_read_4byte(btc, 0xcb4)); + BTC_TRACE(trace_buf); + } } -void ex_halbtc8821c1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c1ant_pre_load_firmware(struct btc_coexist *btc) { } -void ex_halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) +void ex_halbtc8821c1ant_init_hw_config(struct btc_coexist *btc, + boolean wifi_only) { - halbtc8821c1ant_init_hw_config(btcoexist, TRUE, wifi_only); + halbtc8821c1ant_init_hw_config(btc, TRUE, wifi_only); } -void ex_halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c1ant_init_coex_dm(struct btc_coexist *btc) { - halbtc8821c1ant_init_coex_dm(btcoexist); + btc->stop_coex_dm = FALSE; + btc->auto_report = TRUE; + btc->dbg_mode = FALSE; + halbtc8821c1ant_init_coex_dm(btc); } -void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c1ant_display_simple_coex_info(struct btc_coexist *btc) { - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_stack_info *stack_info = &btcoexist->stack_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; - u16 u16tmp[4]; - u32 u32tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; - u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; - static u8 pop_report_in_10s = 0; - u32 phyver = 0; - boolean lte_coex_on = FALSE; - static u8 cnt = 0; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + struct btc_board_info *board_info = &btc->board_info; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + + u8 *cli_buf = btc->cli_buf; + u32 bt_patch_ver = 0, bt_coex_ver = 0; + static u8 cnt; + u8 * const p = &coex_sta->bt_afh_map[0]; + + if (!coex_sta->bt_disabled && + (coex_sta->bt_coex_supported_version == 0 || + coex_sta->bt_coex_supported_version == 0xffff) && + cnt == 0) { + btc->btc_get(btc, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + btc->btc_get(btc, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + coex_sta->bt_reg_vendor_ac = (u16)(btc->btc_get_bt_reg(btc, 3, + 0xac) & + 0xffff); + + coex_sta->bt_reg_vendor_ae = (u16)(btc->btc_get_bt_reg(btc, 3, + 0xae) & + 0xffff); + + btc->btc_get(btc, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + btc->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) + btc->btc_get_bt_afh_map_from_bt(btc, 0, p); + } + if (++cnt >= 3) + cnt = 0; CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); + "\r\n _____[BT Coexist info]____"); CL_PRINTF(cli_buf); - if (btcoexist->manual_control) { + if (btc->manual_control) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); + "\r\n __[Under Manual Control]_"); + CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); + "\r\n _________________________"); CL_PRINTF(cli_buf); } - if (btcoexist->stop_coex_dm) { + + if (btc->stop_coex_dm) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Coex is STOPPED]============"); + "\r\n ____[Coex is STOPPED]____"); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); + "\r\n _________________________"); CL_PRINTF(cli_buf); } - if (!coex_sta->bt_disabled) { - if (coex_sta->bt_coex_supported_feature == 0) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, - &coex_sta->bt_coex_supported_feature); - - if ((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, - &coex_sta->bt_coex_supported_version); - - if (coex_sta->bt_reg_vendor_ac == 0xffff) - coex_sta->bt_reg_vendor_ac = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xac) & 0xffff); - - if (coex_sta->bt_reg_vendor_ae == 0xffff) - coex_sta->bt_reg_vendor_ae = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xae) & 0xffff); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, - &bt_patch_ver); - btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; - - if (coex_sta->num_of_profile > 0) { - cnt++; - - if (cnt >= 3) { - btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, - &coex_sta->bt_afh_map[0]); - cnt = 0; - } - } - } + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / 0x%x", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + board_info->rfe_type); + CL_PRINTF(cli_buf); + + bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8821c_1ant, glcoex_ver_8821c_1ant, + glcoex_ver_btdesired_8821c_1ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8821c_1ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ", "BT status", + ((coex_sta->bt_disabled) ? ("disabled") : + ((coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + : ((BT_8821C_1ANT_BSTATUS_NCON_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8821C_1ANT_BSTATUS_CON_IDLE == + coex_dm->bt_status) ? "connected-idle" : "busy"))))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : + (coex_sta->is_tdma_btautoslot_hang ? + "(auto-slot hang!!)" : ""))); + CL_PRINTF(cli_buf); +} + +void ex_halbtc8821c1ant_display_coex_info(struct btc_coexist *btc) +{ + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + struct btc_board_info *board_info = &btc->board_info; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + + u8 *cli_buf = btc->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u16 u16tmp[4]; + u32 u32tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + static u8 pop_report_in_10s; + u32 phyver = 0; + boolean lte_coex_on = FALSE; + static u8 cnt; + u8 * const p = &coex_sta->bt_afh_map[0]; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info 8821C]============"); + CL_PRINTF(cli_buf); - if (psd_scan->ant_det_try_count == 0) { + if (btc->manual_control) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s / %d", - "Ant PG Num/ Mech/ Pos/ RFE", - board_info->pg_ant_num, board_info->btdm_ant_num, - (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT - ? "Main" : "Aux"), - rfe_type->rfe_module_type); + "\r\n ============[Under Manual Control]============"); CL_PRINTF(cli_buf); - } else { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", - board_info->pg_ant_num, - board_info->btdm_ant_num_by_ant_det, - (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT - ? "Main" : "Aux"), - rfe_type->rfe_module_type, - psd_scan->ant_det_try_count, - psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } else if (btc->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } else if (!coex_sta->run_time_state) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Run Time State = False]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } else if (coex_sta->freeze_coexrun_by_btinfo) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[freeze_coexrun_by_btinfo]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); CL_PRINTF(cli_buf); + } - if (board_info->btdm_ant_det_finish) { + if (!coex_sta->bt_disabled && + (coex_sta->bt_coex_supported_version == 0 || + coex_sta->bt_coex_supported_version == 0xffff) && + cnt == 0) { + btc->btc_get(btc, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); - if (psd_scan->ant_det_result != 12) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d", - "Ant Det PSD Value", - psd_scan->ant_det_psd_scan_peak_val - / 100); - CL_PRINTF(cli_buf); - } + btc->btc_get(btc, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + coex_sta->bt_reg_vendor_ac = (u16)(btc->btc_get_bt_reg(btc, 3, + 0xac) & + 0xffff); + + coex_sta->bt_reg_vendor_ae = (u16)(btc->btc_get_bt_reg(btc, 3, + 0xae) & + 0xffff); + + btc->btc_get(btc, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + btc->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) + btc->btc_get_bt_afh_map_from_bt(btc, 0, p); } - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + if (++cnt >= 3) + cnt = 0; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %s/ %s / 0x%x", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, + (board_info->btdm_ant_num == 1 ? "Shared" : "Non-Shared"), + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + board_info->rfe_type); + CL_PRINTF(cli_buf); + + bt_patch_ver = btc->bt_info.bt_get_fw_ver; + btc->btc_get(btc, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btc->btc_get_bt_phydm_version(btc); bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, @@ -4129,17 +4099,18 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_sta->cut_version + 65); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x (RF-Ch = %d)", "AFH Map to BT", coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); + coex_dm->wifi_chnl_info[2], coex_sta->wl_center_channel); CL_PRINTF(cli_buf); /* wifi status */ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + btc->btc_disp_dbg_msg(btc, BTC_DBG_DISP_WIFI_STATUS); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); @@ -4147,16 +4118,16 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) pop_report_in_10s++; CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", - ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") - : ((BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), - coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, - coex_sta->pop_event_cnt); + "\r\n %-35s = %s/ %ddBm/ %d/ %d", + "BT status/ rssi/ retryCnt/ popCnt", + ((coex_sta->bt_disabled) ? ("disabled") : + ((coex_sta->c2h_bt_inquiry_page) ? ("inquiry-page") : + ((coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_NCON_IDLE) + ? "non-connected-idle" : + ((coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_CON_IDLE) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, + coex_sta->pop_event_cnt); CL_PRINTF(cli_buf); if (pop_report_in_10s >= 5) { @@ -4166,110 +4137,130 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) if (coex_sta->num_of_profile != 0) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s%s%s%s%s", - "Profiles", - ((bt_link_info->a2dp_exist) ? - ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," : - "A2DP,") : ""), - ((bt_link_info->sco_exist) ? "HFP," : ""), + "\r\n %-35s = %s%s%s%s%s%s (multilink = %d)", + "Profiles", ((bt_link_info->a2dp_exist) ? + ((coex_sta->is_bt_a2dp_sink) ? + "A2DP sink," : + "A2DP,") : + ""), + ((bt_link_info->sco_exist) ? "HFP," : ""), ((bt_link_info->hid_exist) ? - ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : - "HID(2/18),") : ""), - ((bt_link_info->pan_exist) ? "PAN," : ""), - ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + ((coex_sta->is_hid_rcu) ? + "HID(RCU)" : + ((coex_sta->hid_busy_num >= 2) ? + "HID(4/18)," : + "HID(2/18),")) : + ""), + ((bt_link_info->pan_exist) ? + ((coex_sta->is_bt_opp_exist) ? "OPP," : + "PAN,") : + ""), + ((coex_sta->voice_over_HOGP) ? "Voice," : ""), + ((coex_sta->msft_mr_exist) ? "MR" : ""), + coex_sta->is_bt_multi_link); else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = None", "Profiles"); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", + "Profiles", + (coex_sta->msft_mr_exist) ? "MR" : "None"); CL_PRINTF(cli_buf); if (bt_link_info->a2dp_exist) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", - "A2DP Rate/Bitpool/Auto_Slot", - ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + "CQDDR/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "On" : "Off"), coex_sta->a2dp_bit_pool, ((coex_sta->is_autoslot) ? "On" : "Off") ); CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %d/ %d", + "V_ID/D_name/FBSlot_Legacy/FBSlot_Le", + coex_sta->bt_a2dp_vendor_id, + coex_sta->bt_a2dp_device_name, + coex_sta->legacy_forbidden_slot, + coex_sta->le_forbidden_slot + ); + CL_PRINTF(cli_buf); } if (bt_link_info->hid_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "HID PairNum/Forbid_Slot", - coex_sta->hid_pair_cnt, - coex_sta->forbidden_slot - ); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "HID PairNum", + coex_sta->hid_pair_cnt); CL_PRINTF(cli_buf); } CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", - "Role/RoleSwCnt/IgnWlact/Feature", - ((bt_link_info->slave_role) ? "Slave" : "Master"), - coex_sta->cnt_RoleSwitch, - ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), - coex_sta->bt_coex_supported_feature); + "Role/RoleSwCnt/IgnWlact/Feature", + (bt_link_info->slave_role ? "Slave" : "Master"), + coex_sta->cnt_role_switch, + (coex_dm->cur_ignore_wlan_act ? "Yes" : "No"), + coex_sta->bt_coex_supported_feature); CL_PRINTF(cli_buf); - if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + if (coex_sta->is_ble_scan_en) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "BLEScan Type/TV/Init/Ble", - coex_sta->bt_ble_scan_type, - (coex_sta->bt_ble_scan_type & 0x1 ? - coex_sta->bt_ble_scan_para[0] : 0x0), - (coex_sta->bt_ble_scan_type & 0x2 ? - coex_sta->bt_ble_scan_para[1] : 0x0), - (coex_sta->bt_ble_scan_type & 0x4 ? - coex_sta->bt_ble_scan_para[2] : 0x0)); + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "BLEScan Type/TV/Init/Ble", + coex_sta->bt_ble_scan_type, + (coex_sta->bt_ble_scan_type & 0x1 ? + coex_sta->bt_ble_scan_para[0] : 0x0), + (coex_sta->bt_ble_scan_type & 0x2 ? + coex_sta->bt_ble_scan_para[1] : 0x0), + (coex_sta->bt_ble_scan_type & 0x4 ? + coex_sta->bt_ble_scan_para[2] : 0x0)); CL_PRINTF(cli_buf); } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d/ %d/ %d %s", "ReInit/ReLink/IgnWlact/Page/NameReq", - coex_sta->cnt_ReInit, - coex_sta->cnt_setupLink, - coex_sta->cnt_IgnWlanAct, - coex_sta->cnt_Page, - coex_sta->cnt_RemoteNameReq - ); + coex_sta->cnt_reinit, + coex_sta->cnt_setup_link, + coex_sta->cnt_ign_wlan_act, + coex_sta->cnt_page, + coex_sta->cnt_remote_name_req, + (coex_sta->is_setup_link ? "(Relink!!)" : "")); CL_PRINTF(cli_buf); - halbtc8821c1ant_read_score_board(btcoexist, &u16tmp[0]); + halbtc8821c1ant_read_scbd(btc, &u16tmp[0]); - if ((coex_sta->bt_reg_vendor_ae == 0xffff) || - (coex_sta->bt_reg_vendor_ac == 0xffff)) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + if (coex_sta->bt_reg_vendor_ae == 0xffff || + coex_sta->bt_reg_vendor_ac == 0xffff) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = x/ x/ 0x%04x", + "0xae[4]/0xac[1:0]/ScBd(B->W)", u16tmp[0]); else CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", - ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), + "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x", + "0xae[4]/0xac[1:0]/ScBd(B->W)", + (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); CL_PRINTF(cli_buf); if (coex_sta->num_of_profile > 0) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", - "AFH MAP", - coex_sta->bt_afh_map[0], - coex_sta->bt_afh_map[1], - coex_sta->bt_afh_map[2], - coex_sta->bt_afh_map[3], - coex_sta->bt_afh_map[4], - coex_sta->bt_afh_map[5], - coex_sta->bt_afh_map[6], - coex_sta->bt_afh_map[7], - coex_sta->bt_afh_map[8], - coex_sta->bt_afh_map[9] - ); + "\r\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x", + "AFH MAP", + coex_sta->bt_afh_map[0], + coex_sta->bt_afh_map[1], + coex_sta->bt_afh_map[2], + coex_sta->bt_afh_map[3], + coex_sta->bt_afh_map[4], + coex_sta->bt_afh_map[5], + coex_sta->bt_afh_map[6], + coex_sta->bt_afh_map[7], + coex_sta->bt_afh_map[8], + coex_sta->bt_afh_map[9]); CL_PRINTF(cli_buf); } - for (i = 0; i < BT_INFO_SRC_8821C_1ANT_MAX; i++) { + for (i = 0; i < BT_8821C_1ANT_INFO_SRC_MAX; i++) { if (coex_sta->bt_info_c2h_cnt[i]) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)", glbt_info_src_8821c_1ant[i], coex_sta->bt_info_c2h[i][0], coex_sta->bt_info_c2h[i][1], @@ -4284,7 +4275,7 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) } - if (btcoexist->manual_control) + if (btc->manual_control) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[mechanisms] (before Manual)============"); else @@ -4300,58 +4291,89 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off")); + (coex_dm->cur_ps_tdma_on ? "TDMA-On" : "TDMA-Off")); + CL_PRINTF(cli_buf); + switch (coex_sta->wl_coex_mode) { + case BT_8821C_1ANT_WLINK_2G1PORT: + default: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "2G-SP"); + break; + case BT_8821C_1ANT_WLINK_2GMPORT: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "2G-MP"); + break; + case BT_8821C_1ANT_WLINK_25GMPORT: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "25G-MP"); + break; + case BT_8821C_1ANT_WLINK_5G: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "5G"); + break; + case BT_8821C_1ANT_WLINK_2GGO: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "2G-P2P"); + break; + case BT_8821C_1ANT_WLINK_BTMR: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "BT-MR"); + break; + } CL_PRINTF(cli_buf); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + u32tmp[0] = btc->btc_read_4byte(btc, 0x6c0); + u32tmp[1] = btc->btc_read_4byte(btc, 0x6c4); + u32tmp[2] = btc->btc_read_4byte(btc, 0x6c8); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", "Table/0x6c0/0x6c4/0x6c8", coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); CL_PRINTF(cli_buf); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); + u8tmp[0] = btc->btc_read_1byte(btc, 0x778); + u32tmp[0] = btc->btc_read_4byte(btc, 0x6cc); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x", - "0x778/0x6cc", - u8tmp[0], u32tmp[0]); + "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x/ %d", + "0x778/0x6cc/ScBd(W->B)/RunCnt", u8tmp[0], u32tmp[0], + coex_sta->score_board_WB, coex_sta->coex_run_cnt); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "AntDiv/BtCtrlLPS/LPRA/PsFail", - ((board_info->ant_div_cfg) ? "On" : "Off"), - ((coex_sta->force_lps_ctrl) ? "On" : "Off"), - ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"), - coex_sta->cnt_set_ps_state_fail); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d/ %d", + "AntDiv/BtCtrlLPS/LPRA/PsFail/g_busy", + (board_info->ant_div_cfg ? "On" : "Off"), + (coex_sta->force_lps_ctrl ? "On" : "Off"), + (coex_dm->cur_low_penalty_ra ? "On" : "Off"), + coex_sta->cnt_set_ps_state_fail, + coex_sta->gl_wifi_busy); CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "Null All/Retry/Ack/BT_Empty/BT_Late", + coex_sta->wl_fw_dbg_info[1], + coex_sta->wl_fw_dbg_info[2], + coex_sta->wl_fw_dbg_info[3], + coex_sta->wl_fw_dbg_info[4], + coex_sta->wl_fw_dbg_info[5]); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c1ant_read_indirect_reg(btc, 0x38); lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? TRUE : FALSE; if (lte_coex_on) { - - u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); + u32tmp[0] = halbtc8821c1ant_read_indirect_reg(btc, 0xa0); + u32tmp[1] = halbtc8821c1ant_read_indirect_reg(btc, 0xa4); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + "LTE Coex Table W_L/B_L", u32tmp[0] & 0xffff, + u32tmp[1] & 0xffff); CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - u32tmp[2] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - u32tmp[3] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); + u32tmp[0] = halbtc8821c1ant_read_indirect_reg(btc, 0xa8); + u32tmp[1] = halbtc8821c1ant_read_indirect_reg(btc, 0xac); + u32tmp[2] = halbtc8821c1ant_read_indirect_reg(btc, 0xb0); + u32tmp[3] = halbtc8821c1ant_read_indirect_reg(btc, 0xb4); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", @@ -4366,9 +4388,9 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) "============[Hw setting]============"); CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + u32tmp[0] = halbtc8821c1ant_read_indirect_reg(btc, 0x38); + u32tmp[1] = halbtc8821c1ant_read_indirect_reg(btc, 0x54); + u8tmp[0] = btc->btc_read_1byte(btc, 0x73); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", "LTE Coex/Path Owner", @@ -4393,7 +4415,7 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_PRINTF(cli_buf); } CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s (gnt_err = %d)", "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), @@ -4403,16 +4425,17 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_sta->gnt_error_cnt); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "GNT_WL/GNT_BT", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ 0x%x", + "GNT_WL/GNT_BT/ RF_0x1", (int)((u32tmp[1] & BIT(2)) >> 2), - (int)((u32tmp[1] & BIT(3)) >> 3)); + (int)((u32tmp[1] & BIT(3)) >> 3), + btc->btc_get_rf_reg(btc, BTC_RF_A, 0x1, 0xfffff)); CL_PRINTF(cli_buf); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); + u32tmp[0] = btc->btc_read_4byte(btc, 0xcb0); + u32tmp[1] = btc->btc_read_4byte(btc, 0xcb4); + u8tmp[0] = btc->btc_read_1byte(btc, 0xcba); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", @@ -4421,38 +4444,36 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); CL_PRINTF(cli_buf); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + u32tmp[0] = btc->btc_read_4byte(btc, 0x4c); + u8tmp[2] = btc->btc_read_1byte(btc, 0x64); + u8tmp[0] = btc->btc_read_1byte(btc, 0x4c6); + u8tmp[1] = btc->btc_read_1byte(btc, 0x40); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "4c[24:23]/64[0]/4c6[4]/40[5]", - (u32tmp[0] & (BIT(24) | BIT(23))) >> 23 , u8tmp[2] & 0x1 , - (int)((u8tmp[0] & BIT(4)) >> 4), + (int)(u32tmp[0] & (BIT(24) | BIT(23))) >> 23, + u8tmp[2] & 0x1, (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5)); CL_PRINTF(cli_buf); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50); + u32tmp[0] = btc->btc_read_4byte(btc, 0x550); + u8tmp[0] = btc->btc_read_1byte(btc, 0x522); + u8tmp[1] = btc->btc_read_1byte(btc, 0x953); + u8tmp[2] = btc->btc_read_1byte(btc, 0xc50); + u8tmp[3] = btc->btc_read_1byte(btc, 0x60a); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x", - "0x550/0x522/4-RxAGC/0xc50", - u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]); + "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x/ 0x%x", + "0x550/0x522/4-RxAGC/0xc50/0x60a", + u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", + u8tmp[2], u8tmp[3]); CL_PRINTF(cli_buf); - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_CCK); + fa_ofdm = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_FA_OFDM); + fa_cck = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_FA_CCK); + cca_ofdm = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CCA_OFDM); + cca_cck = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CCA_CCK); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", @@ -4460,8 +4481,6 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) cca_cck, fa_cck, cca_ofdm, fa_ofdm); CL_PRINTF(cli_buf); - -#if 1 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_OK CCK/11g/11n/11ac", coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, @@ -4473,16 +4492,39 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_sta->crc_err_cck, coex_sta->crc_err_11g, coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); CL_PRINTF(cli_buf); -#endif - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "WlHiPri/ Locking/ Locked/ Noisy", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s-%d/ %d (Tx macid: %d)", + "Rate RxD/RxRTS/TxD/TxRetry_ratio", + coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate, + (coex_sta->wl_tx_rate & 0x80 ? "SGI" : "LGI"), + coex_sta->wl_tx_rate & 0x7f, + coex_sta->wl_tx_retry_ratio, + coex_sta->wl_tx_macid); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %s/ %d", + "HiPr/ Locking/ warn/ Locked/ Noisy", + (coex_sta->wifi_high_pri_task1 ? "Yes" : "No"), (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No"), + (coex_sta->cck_lock_warn ? "Yes" : "No"), + (coex_sta->cck_lock_ever ? "Yes" : "No"), coex_sta->wl_noisy_level); CL_PRINTF(cli_buf); + u8tmp[0] = btc->btc_read_1byte(btc, 0xf8e); + u8tmp[1] = btc->btc_read_1byte(btc, 0xf8f); + u8tmp[2] = btc->btc_read_1byte(btc, 0xd14); + u8tmp[3] = btc->btc_read_1byte(btc, 0xd54); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "EVM_A/ EVM_B/ SNR_A/ SNR_B", + (u8tmp[0] > 127 ? u8tmp[0] - 256 : u8tmp[0]), + (u8tmp[1] > 127 ? u8tmp[1] - 256 : u8tmp[1]), + (u8tmp[2] > 127 ? u8tmp[2] - 256 : u8tmp[2]), + (u8tmp[3] > 127 ? u8tmp[3] - 256 : u8tmp[3])); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(Hi-pri rx/tx)", coex_sta->high_priority_rx, coex_sta->high_priority_tx); @@ -4495,62 +4537,53 @@ void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); + btc->btc_disp_dbg_msg(btc, BTC_DBG_DISP_COEX_STATISTICS); } - -void ex_halbtc8821c1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +void ex_halbtc8821c1ant_ips_notify(struct btc_coexist *btc, u8 type) { - if (btcoexist->manual_control || btcoexist->stop_coex_dm) + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + + if (btc->manual_control || btc->stop_coex_dm) return; - if (BTC_IPS_ENTER == type) { + if (type == BTC_IPS_ENTER) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], IPS ENTER notify\n"); BTC_TRACE(trace_buf); coex_sta->under_ips = TRUE; /* Write WL "Active" in Score-board for LPS off */ - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, - FALSE); - - halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_WLAN_OFF); - - halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - } else if (BTC_IPS_LEAVE == type) { + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE | + BT_8821C_1ANT_SCBD_ONOFF | + BT_8821C_1ANT_SCBD_SCAN | + BT_8821C_1ANT_SCBD_UNDERTEST, + FALSE); + + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_1ANT_PHASE_WOFF); + halbtc8821c1ant_action_coex_all_off(btc); + } else if (type == BTC_IPS_LEAVE) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], IPS LEAVE notify\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE, TRUE); - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ONOFF, TRUE); -#endif - halbtc8821c1ant_init_hw_config(btcoexist, FALSE, FALSE); - halbtc8821c1ant_init_coex_dm(btcoexist); + halbtc8821c1ant_init_hw_config(btc, FALSE, FALSE); + halbtc8821c1ant_init_coex_dm(btc); coex_sta->under_ips = FALSE; } } -void ex_halbtc8821c1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +void ex_halbtc8821c1ant_lps_notify(struct btc_coexist *btc, u8 type) { + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; static boolean pre_force_lps_on = FALSE; - if (btcoexist->manual_control || btcoexist->stop_coex_dm) + if (btc->manual_control || btc->stop_coex_dm) return; - if (BTC_LPS_ENABLE == type) { + if (type == BTC_LPS_ENABLE) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], LPS ENABLE notify\n"); BTC_TRACE(trace_buf); @@ -4559,358 +4592,345 @@ void ex_halbtc8821c1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) if (coex_sta->force_lps_ctrl == TRUE) { /* LPS No-32K */ /* Write WL "Active" in Score-board for PS-TDMA */ pre_force_lps_on = TRUE; - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE, TRUE); - } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ - /* Write WL "Non-Active" in Score-board for Native-PS */ + halbtc8821c1ant_write_scbd(btc, + BT_8821C_1ANT_SCBD_ACTIVE, + TRUE); + } else { /* LPS-32K, need check if this h2c 0x71 can work?? + *(2015/08/28) + * Write WL "Non-Active" in Score-board for Native-PS + */ pre_force_lps_on = FALSE; - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE, FALSE); + halbtc8821c1ant_write_scbd(btc, + BT_8821C_1ANT_SCBD_ACTIVE, + FALSE); + + halbtc8821c1ant_action_wifi_native_lps(btc); } - } else if (BTC_LPS_DISABLE == type) { + } else if (type == BTC_LPS_DISABLE) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], LPS DISABLE notify\n"); BTC_TRACE(trace_buf); coex_sta->under_lps = FALSE; /* Write WL "Active" in Score-board for LPS off */ - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE, TRUE); + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE, + TRUE); - if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl)) - halbtc8821c1ant_query_bt_info(btcoexist); + if (!pre_force_lps_on && !coex_sta->force_lps_ctrl) + halbtc8821c1ant_query_bt_info(btc); } } -void ex_halbtc8821c1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c1ant_scan_notify(struct btc_coexist *btc, + u8 type) { + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; boolean wifi_connected = FALSE; - boolean wifi_under_5g = FALSE; - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + if (btc->manual_control || + btc->stop_coex_dm) return; coex_sta->freeze_coexrun_by_btinfo = FALSE; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); if (wifi_connected) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** WL connected before SCAN\n"); + "[BTCoex], ********** WL connected before SCAN\n"); else BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** WL is not connected before SCAN\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_query_bt_info(btcoexist); - - if (BTC_SCAN_START == type) { + if (type != BTC_SCAN_FINISH) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, - &wifi_under_5g); - - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - TRUE); - - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** SCAN START notify (5g)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_under5g(btcoexist); - return; - } - - coex_sta->wifi_is_high_pri_task = TRUE; + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE | + BT_8821C_1ANT_SCBD_SCAN | + BT_8821C_1ANT_SCBD_ONOFF, + TRUE); + } + if (type == BTC_SCAN_START_5G) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** SCAN START notify (2g)\n"); + "[BTCoex], SCAN START notify (5G)\n"); BTC_TRACE(trace_buf); - /* Force antenna setup for no scan result issue */ - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - - halbtc8821c1ant_run_coexist_mechanism(btcoexist); - - return; - } - - if (BTC_SCAN_START_2G == type) { - - if (!wifi_connected) - coex_sta->wifi_is_high_pri_task = TRUE; + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_1ANT_PHASE_5G); + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_5GSCANSTART); + } else if (type == BTC_SCAN_START_2G || type == BTC_SCAN_START) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCAN START notify (2G)\n"); + "[BTCoex], SCAN START notify (2G)\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - TRUE); + if (!wifi_connected) + coex_sta->wifi_high_pri_task2 = TRUE; /* Force antenna setup for no scan result issue */ - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - - halbtc8821c1ant_run_coexist_mechanism(btcoexist); + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_1ANT_PHASE_2G); + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_2GSCANSTART); } else { - - coex_sta->wifi_is_high_pri_task = FALSE; - - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); + btc->btc_get(btc, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", coex_sta->scan_ap_num); BTC_TRACE(trace_buf); - halbtc8821c1ant_run_coexist_mechanism(btcoexist); - } - + coex_sta->wifi_high_pri_task2 = FALSE; + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_SCANFINISH); + } } -void ex_halbtc8821c1ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c1ant_switchband_notify(struct btc_coexist *btc, u8 type) { + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; - boolean wifi_connected = FALSE, bt_hs_on = FALSE; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = FALSE; - u8 agg_buf_size = 5; - - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + if (btc->manual_control || btc->stop_coex_dm) return; coex_sta->switch_band_notify_to = type; if (type == BTC_SWITCH_TO_5G) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], switchband_notify --- switch to 5G\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_wifi_under5g(btcoexist); + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_5GSWITCHBAND); } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n"); + "[BTCoex], switchband_notify --- BTC_SWITCH_TO_2G (no for scan)\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_run_coexist_mechanism(btcoexist); + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_2GSWITCHBAND); } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], switchband_notify --- switch to 2G\n"); BTC_TRACE(trace_buf); - ex_halbtc8821c1ant_scan_notify(btcoexist, - BTC_SCAN_START_2G); + ex_halbtc8821c1ant_scan_notify(btc, BTC_SCAN_START_2G); } coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; } - -void ex_halbtc8821c1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c1ant_connect_notify(struct btc_coexist *btc, u8 type) { + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + if (btc->manual_control || btc->stop_coex_dm) return; - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - TRUE); + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE | + BT_8821C_1ANT_SCBD_SCAN | + BT_8821C_1ANT_SCBD_ONOFF, + TRUE); - if ((BTC_ASSOCIATE_5G_START == type) || - (BTC_ASSOCIATE_5G_FINISH == type)) { + if (type == BTC_ASSOCIATE_5G_START || + type == BTC_ASSOCIATE_5G_FINISH) { + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_1ANT_PHASE_5G); - if (BTC_ASSOCIATE_5G_START == type) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], connect_notify --- 5G start\n"); - else + if (type == BTC_ASSOCIATE_5G_START) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], connect_notify --- 5G finish\n"); - - BTC_TRACE(trace_buf); - - halbtc8821c1ant_action_wifi_under5g(btcoexist); - return; - } + "[BTCoex], CONNECT START notify (5G)\n"); + BTC_TRACE(trace_buf); - if (BTC_ASSOCIATE_START == type) { + halbtc8821c1ant_run_coex(btc, + BT_8821C_1ANT_RSN_5GCONSTART); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify (5G)\n"); + BTC_TRACE(trace_buf); - coex_sta->wifi_is_high_pri_task = TRUE; + halbtc8821c1ant_run_coex(btc, + BT_8821C_1ANT_RSN_5GCONFINISH); + } - /* Force antenna setup for no scan result issue */ - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); + } else if (type == BTC_ASSOCIATE_START) { + coex_sta->wifi_high_pri_task1 = TRUE; + coex_dm->arp_cnt = 0; + coex_sta->connect_ap_period_cnt = 2; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], CONNECT START notify (2G)\n"); BTC_TRACE(trace_buf); - coex_dm->arp_cnt = 0; + /* Force antenna setup for no scan result issue */ + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_1ANT_PHASE_2G); - halbtc8821c1ant_run_coexist_mechanism(btcoexist); + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_2GCONSTART); /* To keep TDMA case during connect process, - to avoid changed by Btinfo and runcoexmechanism */ + * to avoid changed by Btinfo and runcoexmechanism + */ coex_sta->freeze_coexrun_by_btinfo = TRUE; } else { - - coex_sta->wifi_is_high_pri_task = FALSE; + coex_sta->wifi_high_pri_task1 = FALSE; coex_sta->freeze_coexrun_by_btinfo = FALSE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], CONNECT FINISH notify (2G)\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_run_coexist_mechanism(btcoexist); + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_2GCONFINISH); } - } -void ex_halbtc8821c1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c1ant_media_status_notify(struct btc_coexist *btc, u8 type) { - boolean wifi_under_b_mode = FALSE, wifi_under_5g = FALSE; - + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + boolean wifi_under_b_mode = FALSE; + u16 ap_beacon_interval = 100; + u8 h2c_parameter[3] = {0}; - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + if (btc->manual_control || btc->stop_coex_dm) return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + if (type == BTC_MEDIA_CONNECT || type == BTC_MEDIA_CONNECT_5G) { - if (BTC_MEDIA_CONNECT == type) { + halbtc8821c1ant_write_scbd(btc, + BT_8821C_1ANT_SCBD_ACTIVE | + BT_8821C_1ANT_SCBD_ONOFF, + TRUE); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA connect notify\n"); - BTC_TRACE(trace_buf); + if (type == BTC_MEDIA_CONNECT_5G) { - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - TRUE); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], media_status_notify --- 5G\n"); + BTC_TRACE(trace_buf); - if (wifi_under_5g) { + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, + FC_EXCU, + BT_8821C_1ANT_PHASE_5G); + halbtc8821c1ant_run_coex(btc, + BT_8821C_1ANT_RSN_5GMEDIA); + } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!!\n"); + "[BTCoex], media_status_notify --- 2G\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_wifi_under5g(btcoexist); - return; - } + /* Force antenna setup for no scan result issue */ + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, + FC_EXCU, + BT_8821C_1ANT_PHASE_2G); - /* Force antenna setup for no scan result issue */ - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { - /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */ - /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } + btc->btc_get(btc, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + /* CCK Tx */ + btc->btc_write_1byte(btc, 0x6cd, 0x00); + /* CCK Rx */ + btc->btc_write_1byte(btc, 0x6cf, 0x00); + } else { + /* CCK Tx */ + btc->btc_write_1byte(btc, 0x6cd, 0x00); + /* CCK Rx */ + btc->btc_write_1byte(btc, 0x6cf, 0x10); + } + + btc->btc_get(btc, BTC_GET_U2_BEACON_PERIOD, + &ap_beacon_interval); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], AP beacon interval = %d\n", + ap_beacon_interval); + BTC_TRACE(trace_buf); + + /* set TDMA waiting BI if BI is not equal to 100 */ + if (ap_beacon_interval < 80 && ap_beacon_interval > 0) { + h2c_parameter[0] = 0xb; + h2c_parameter[1] = (100 / ap_beacon_interval); + + if (100 % ap_beacon_interval != 0) + h2c_parameter[1] = h2c_parameter[1] + 1; + + } else if (ap_beacon_interval >= 180) { + h2c_parameter[0] = 0xb; + h2c_parameter[1] = (ap_beacon_interval / 100); + + if (ap_beacon_interval % 100 <= 80) + h2c_parameter[1] = h2c_parameter[1] - 1; + + h2c_parameter[1] = h2c_parameter[1] | 0x80; + + } else { + h2c_parameter[0] = 0xb; + h2c_parameter[1] = 0x1; + } + + btc->btc_fill_h2c(btc, 0x69, 2, h2c_parameter); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], TDMA waiting BI = 0x%x\n", + h2c_parameter[1]); + BTC_TRACE(trace_buf); - coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, - 0x430); - coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, - 0x434); - coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( - btcoexist, 0x42a); - coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( - btcoexist, 0x456); + halbtc8821c1ant_run_coex(btc, + BT_8821C_1ANT_RSN_2GMEDIA); + } } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], MEDIA disconnect notify\n"); + "[BTCoex], media disconnect notify\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE, FALSE); + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE, + FALSE); - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + btc->btc_write_1byte(btc, 0x6cd, 0x0); /* CCK Tx */ + btc->btc_write_1byte(btc, 0x6cf, 0x0); /* CCK Rx */ - coex_sta->cck_ever_lock = FALSE; + coex_sta->cck_lock_ever = FALSE; + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_MEDIADISCON); } - halbtc8821c1ant_update_wifi_channel_info(btcoexist, type); - + halbtc8821c1ant_update_wifi_ch_info(btc, type); } -void ex_halbtc8821c1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c1ant_specific_packet_notify(struct btc_coexist *btc, u8 type) { - boolean under_4way = FALSE, wifi_under_5g = FALSE; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + boolean under_4way = FALSE; - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + if (btc->manual_control || btc->stop_coex_dm) return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (wifi_under_5g) { - + if (type & BTC_5G_BAND) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!!\n"); + "[BTCoex], 5g special packet notify\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_action_wifi_under5g(btcoexist); + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_5GSPECIALPKT); return; } - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); + btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way); if (under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], specific Packet ---- under_4way!!\n"); BTC_TRACE(trace_buf); - coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->wifi_high_pri_task1 = TRUE; coex_sta->specific_pkt_period_cnt = 2; - } else if (BTC_PACKET_ARP == type) { - + } else if (type == BTC_PACKET_ARP) { coex_dm->arp_cnt++; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], specific Packet ARP notify -cnt = %d\n", @@ -4918,43 +4938,35 @@ void ex_halbtc8821c1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, BTC_TRACE(trace_buf); } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", + "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", type); BTC_TRACE(trace_buf); - coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->wifi_high_pri_task1 = TRUE; coex_sta->specific_pkt_period_cnt = 2; } - if (coex_sta->wifi_is_high_pri_task) { - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_SCAN, TRUE); - halbtc8821c1ant_run_coexist_mechanism(btcoexist); + if (coex_sta->wifi_high_pri_task1) { + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_SCAN, TRUE); + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_2GSPECIALPKT); } - } -void ex_halbtc8821c1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) +void ex_halbtc8821c1ant_bt_info_notify(struct btc_coexist *btc, u8 *tmp_buf, + u8 length) { - u8 i, rsp_source = 0; - boolean wifi_connected = FALSE; - boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE, - wifi_busy = FALSE; - static boolean is_scoreboard_scan = FALSE; - - if (psd_scan->is_AntDet_running == TRUE) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], bt_info_notify return for AntDet is running\n"); - BTC_TRACE(trace_buf); - return; - } + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + u8 i, rsp_source = 0; + boolean wifi_connected = FALSE; + boolean wifi_busy = FALSE; + static boolean is_scoreboard_scan; + const u16 type_is_scan = BT_8821C_1ANT_SCBD_SCAN; + u8 type; rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8821C_1ANT_MAX) - rsp_source = BT_INFO_SRC_8821C_1ANT_WIFI_FW; + if (rsp_source >= BT_8821C_1ANT_INFO_SRC_MAX) + rsp_source = BT_8821C_1ANT_INFO_SRC_WIFI_FW; coex_sta->bt_info_c2h_cnt[rsp_source]++; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -4962,6 +4974,19 @@ void ex_halbtc8821c1ant_bt_info_notify(IN struct btc_coexist *btcoexist, length); BTC_TRACE(trace_buf); + if (rsp_source == BT_8821C_1ANT_INFO_SRC_BT_RSP || + rsp_source == BT_8821C_1ANT_INFO_SRC_BT_ACT) { + if (coex_sta->bt_disabled) { + coex_sta->bt_disabled = FALSE; + coex_sta->is_bt_reenable = TRUE; + coex_sta->cnt_bt_reenable = 15; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT enable detected by bt_info\n"); + BTC_TRACE(trace_buf); + } + } + for (i = 0; i < length; i++) { coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; @@ -4980,45 +5005,51 @@ void ex_halbtc8821c1ant_bt_info_notify(IN struct btc_coexist *btcoexist, coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; - if (BT_INFO_SRC_8821C_1ANT_WIFI_FW != rsp_source) { - + if (rsp_source != BT_8821C_1ANT_INFO_SRC_WIFI_FW) { /* if 0xff, it means BT is under WHCK test */ - coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE : - FALSE); + coex_sta->bt_whck_test = + ((coex_sta->bt_info == 0xff) ? TRUE : FALSE); - coex_sta->bt_create_connection = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE : - FALSE); + coex_sta->bt_create_connection = + ((coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE : + FALSE); /* unit: %, value-100 to translate to unit: dBm */ - coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + - 10; + coex_sta->bt_rssi = + coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10; - coex_sta->c2h_bt_remote_name_req = (( - coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE : - FALSE); + coex_sta->c2h_bt_remote_name_req = + ((coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE : + FALSE); - coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & - 0x10) ? TRUE : FALSE); + coex_sta->is_A2DP_3M = + ((coex_sta->bt_info_c2h[rsp_source][2] & 0x10) ? TRUE : + FALSE); - coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & - 0x9) ? TRUE : FALSE); + coex_sta->acl_busy = + ((coex_sta->bt_info_c2h[rsp_source][1] & 0x8) ? TRUE : + FALSE); - coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? - TRUE : FALSE); + coex_sta->voice_over_HOGP = + ((coex_sta->bt_info_ext & 0x10) ? TRUE : FALSE); - coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & - BT_INFO_8821C_1ANT_B_INQ_PAGE) ? TRUE : FALSE); + coex_sta->c2h_bt_inquiry_page = + ((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_INQ_PAGE) ? + TRUE : + FALSE); - coex_sta->a2dp_bit_pool = ((( - coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? - (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : 0); + coex_sta->a2dp_bit_pool = + (((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == + 0x49) ? + (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : + 0); - coex_sta->is_bt_a2dp_sink = (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ? - TRUE : FALSE; + coex_sta->is_bt_a2dp_sink = + (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ? TRUE : + FALSE; - coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & - 0xf; + coex_sta->bt_retry_cnt = + coex_sta->bt_info_c2h[rsp_source][2] & 0xf; coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; @@ -5028,374 +5059,432 @@ void ex_halbtc8821c1ant_bt_info_notify(IN struct btc_coexist *btcoexist, coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; + coex_sta->is_bt_opp_exist = + (coex_sta->bt_info_ext2 & 0x1) ? TRUE : FALSE; + if (coex_sta->bt_retry_cnt >= 1) coex_sta->pop_event_cnt++; if (coex_sta->c2h_bt_remote_name_req) - coex_sta->cnt_RemoteNameReq++; + coex_sta->cnt_remote_name_req++; if (coex_sta->bt_info_ext & BIT(1)) - coex_sta->cnt_ReInit++; + coex_sta->cnt_reinit++; + + if ((coex_sta->bt_info_ext & BIT(2)) || + (coex_sta->bt_create_connection && + coex_sta->wl_pnp_wakeup_downcnt > 0)) { + coex_sta->cnt_setup_link++; + coex_sta->is_setup_link = TRUE; - if (coex_sta->bt_info_ext & BIT(2)) { - coex_sta->cnt_setupLink++; - coex_sta->is_setupLink = TRUE; - coex_sta->bt_relink_downcount = 2; + if (coex_sta->is_bt_reenable) + coex_sta->bt_relink_downcount = 6; + else + coex_sta->bt_relink_downcount = 2; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Re-Link start in BT info!!\n"); + "[BTCoex], Re-Link start in BT info!!\n"); BTC_TRACE(trace_buf); } else { - coex_sta->is_setupLink = FALSE; - coex_sta->bt_relink_downcount = 0; + coex_sta->is_setup_link = FALSE; + if (!coex_sta->is_bt_reenable) + coex_sta->bt_relink_downcount = 0; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Re-Link stop in BT info!!\n"); BTC_TRACE(trace_buf); } if (coex_sta->bt_info_ext & BIT(3)) - coex_sta->cnt_IgnWlanAct++; + coex_sta->cnt_ign_wlan_act++; if (coex_sta->bt_info_ext & BIT(6)) - coex_sta->cnt_RoleSwitch++; + coex_sta->cnt_role_switch++; if (coex_sta->bt_info_ext & BIT(7)) coex_sta->is_bt_multi_link = TRUE; else coex_sta->is_bt_multi_link = FALSE; - if (coex_sta->bt_create_connection) { - coex_sta->cnt_Page++; + if (coex_sta->bt_info_ext & BIT(0)) + coex_sta->is_hid_rcu = TRUE; + else + coex_sta->is_hid_rcu = FALSE; + + if (coex_sta->bt_info_ext & BIT(5)) + coex_sta->is_ble_scan_en = TRUE; + else + coex_sta->is_ble_scan_en = FALSE; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, - &wifi_busy); + if (coex_sta->bt_create_connection) { + coex_sta->cnt_page++; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - if ((wifi_link) || (wifi_roam) || (wifi_scan) || - (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { + if (coex_sta->is_wifi_linkscan_process || + coex_sta->wifi_high_pri_task1 || + coex_sta->wifi_high_pri_task2 || + wifi_busy) { is_scoreboard_scan = TRUE; - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_SCAN, TRUE); + halbtc8821c1ant_write_scbd(btc, type_is_scan, + TRUE); } else - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_SCAN, FALSE); + halbtc8821c1ant_write_scbd(btc, type_is_scan, + FALSE); } else { - if (is_scoreboard_scan) { - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_SCAN, FALSE); - is_scoreboard_scan = FALSE; - } + if (is_scoreboard_scan) { + halbtc8821c1ant_write_scbd(btc, type_is_scan, + FALSE); + is_scoreboard_scan = FALSE; + } } /* Here we need to resend some wifi info to BT */ /* because bt is reset and loss of the info. */ + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); - if ((!btcoexist->manual_control) && - (!btcoexist->stop_coex_dm)) { + /* Re-Init */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + if (wifi_connected) + type = BTC_MEDIA_CONNECT; + else + type = BTC_MEDIA_DISCONNECT; + halbtc8821c1ant_update_wifi_ch_info(btc, type); + } - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + /* If Ignore_WLanAct && not SetUp_Link */ + if ((coex_sta->bt_info_ext & BIT(3)) && + (!(coex_sta->bt_info_ext & BIT(2)))) { - /* Re-Init */ - if ((coex_sta->bt_info_ext & BIT(1))) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); - BTC_TRACE(trace_buf); - if (wifi_connected) - halbtc8821c1ant_update_wifi_channel_info( - btcoexist, BTC_MEDIA_CONNECT); - else - halbtc8821c1ant_update_wifi_channel_info( - btcoexist, - BTC_MEDIA_DISCONNECT); - } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_ignore_wlan_act(btc, FC_EXCU, FALSE); + } + } - /* If Ignore_WLanAct && not SetUp_Link */ - if ((coex_sta->bt_info_ext & BIT(3)) && - (!(coex_sta->bt_info_ext & BIT(2)))) { + halbtc8821c1ant_update_bt_link_info(btc); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); - BTC_TRACE(trace_buf); - halbtc8821c1ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, FALSE); - } - } + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_BTINFO); +} + +void ex_halbtc8821c1ant_wl_fwdbginfo_notify(struct btc_coexist *btc, + u8 *tmp_buf, u8 length) +{ + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + u8 i = 0; + static u8 tmp_buf_pre[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d (len = %d)\n", + tmp_buf[0], tmp_buf[1], tmp_buf[2], tmp_buf[3], tmp_buf[4], + tmp_buf[5], length); + BTC_TRACE(trace_buf); + + if (tmp_buf[0] == 0x8) { + for (i = 1; i <= 5; i++) { + coex_sta->wl_fw_dbg_info[i] = + (tmp_buf[i] >= tmp_buf_pre[i]) ? + (tmp_buf[i] - tmp_buf_pre[i]) : + (255 - tmp_buf_pre[i] + tmp_buf[i]); + tmp_buf_pre[i] = tmp_buf[i]; + } } +} + +void ex_halbtc8821c1ant_rx_rate_change_notify(struct btc_coexist *btc, + BOOLEAN is_data_frame, + u8 btc_rate_id) +{ + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct coex_dm_8821c_1ant *coex_dm = &btc->coex_dm_8821c_1ant; + BOOLEAN wifi_connected = FALSE; + + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + + if (is_data_frame) { + coex_sta->wl_rx_rate = btc_rate_id; - if ((coex_sta->bt_info_ext & BIT(5))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + "[BTCoex], rx_rate_change_notify data rate id = %d, RTS_Rate = %d\n", + coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate); BTC_TRACE(trace_buf); - coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( - btcoexist); - - if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) - coex_sta->bt_ble_scan_para[0] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x1); - if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) - coex_sta->bt_ble_scan_para[1] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x2); - if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) - coex_sta->bt_ble_scan_para[2] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x4); + } else { + coex_sta->wl_rts_rx_rate = btc_rate_id; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], rts_rate_change_notify RTS rate id = %d, RTS_Rate = %d\n", + coex_sta->wl_rts_rx_rate, coex_sta->wl_rts_rx_rate); + BTC_TRACE(trace_buf); } - halbtc8821c1ant_update_bt_link_info(btcoexist); + if (wifi_connected && + (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_BUSY || + coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_ACL_SCO_BUSY || + coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_SCO_BUSY)) { + if (coex_sta->wl_rx_rate == BTC_CCK_5_5 || + coex_sta->wl_rx_rate == BTC_OFDM_6 || + coex_sta->wl_rx_rate == BTC_MCS_0) { + coex_sta->cck_lock_warn = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck lock warning...\n"); + BTC_TRACE(trace_buf); + } else if (coex_sta->wl_rx_rate == BTC_CCK_1 || + coex_sta->wl_rx_rate == BTC_CCK_2 || + coex_sta->wl_rts_rx_rate == BTC_CCK_1 || + coex_sta->wl_rts_rx_rate == BTC_CCK_2) { + coex_sta->cck_lock = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck locking...\n"); + BTC_TRACE(trace_buf); + } else { + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; - halbtc8821c1ant_run_coexist_mechanism(btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck unlock...\n"); + BTC_TRACE(trace_buf); + } + } else { + if (coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_CON_IDLE || + coex_dm->bt_status == BT_8821C_1ANT_BSTATUS_NCON_IDLE) { + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; + } + } } +void ex_halbtc8821c1ant_tx_rate_change_notify(struct btc_coexist *btc, + u8 tx_rate, u8 tx_retry_ratio, + u8 macid) +{ + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], tx_rate_change_notify Tx_Rate = %d, Tx_Retry_Ratio = %d, macid =%d\n", + tx_rate, tx_retry_ratio, macid); + BTC_TRACE(trace_buf); + coex_sta->wl_tx_rate = tx_rate; + coex_sta->wl_tx_retry_ratio = tx_retry_ratio; + coex_sta->wl_tx_macid = macid; +} -void ex_halbtc8821c1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c1ant_rf_status_notify(struct btc_coexist *btc, u8 type) { + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); BTC_TRACE(trace_buf); - if (BTC_RF_ON == type) { - + if (type == BTC_RF_ON) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF is turned ON!!\n"); BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = FALSE; + btc->stop_coex_dm = FALSE; coex_sta->is_rf_state_off = FALSE; -#if 0 - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - TRUE); -#endif - } else if (BTC_RF_OFF == type) { - + } else if (type == BTC_RF_OFF) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF is turned OFF!!\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, - FALSE); + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE | + BT_8821C_1ANT_SCBD_ONOFF | + BT_8821C_1ANT_SCBD_SCAN | + BT_8821C_1ANT_SCBD_UNDERTEST, + FALSE); - halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_1ANT_PHASE_WOFF); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_WLAN_OFF); + halbtc8821c1ant_action_coex_all_off(btc); - btcoexist->stop_coex_dm = TRUE; + btc->stop_coex_dm = TRUE; coex_sta->is_rf_state_off = TRUE; + + /* must place in the last step */ + halbtc8821c1ant_update_wifi_ch_info(btc, BTC_MEDIA_DISCONNECT); } } -void ex_halbtc8821c1ant_halt_notify(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c1ant_halt_notify(struct btc_coexist *btc) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, - FALSE); - - halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE | + BT_8821C_1ANT_SCBD_ONOFF | + BT_8821C_1ANT_SCBD_SCAN | + BT_8821C_1ANT_SCBD_UNDERTEST, + FALSE); - halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_1ANT_PHASE_WLAN_OFF); + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_1ANT_PHASE_WOFF); - halbtc8821c1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, TRUE); + halbtc8821c1ant_action_coex_all_off(btc); - ex_halbtc8821c1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + btc->stop_coex_dm = TRUE; - btcoexist->stop_coex_dm = TRUE; + /* must place in the last step */ + halbtc8821c1ant_update_wifi_ch_info(btc, BTC_MEDIA_DISCONNECT); } -void ex_halbtc8821c1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) +void ex_halbtc8821c1ant_pnp_notify(struct btc_coexist *btc, u8 pnp_state) { - boolean wifi_under_5g = FALSE; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if ((BTC_WIFI_PNP_SLEEP == pnp_state) || - (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct wifi_link_info_8821c_1ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_1ant; + static u8 pre_pnp_state; + u8 phase; + + if (pnp_state == BTC_WIFI_PNP_SLEEP || + pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify to SLEEP\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF | - BT_8821C_1ANT_SCOREBOARD_SCAN | - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, - FALSE); + halbtc8821c1ant_write_scbd(btc, BT_8821C_1ANT_SCBD_ACTIVE | + BT_8821C_1ANT_SCBD_ONOFF | + BT_8821C_1ANT_SCBD_SCAN | + BT_8821C_1ANT_SCBD_UNDERTEST, + FALSE); - if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { - - if (wifi_under_5g) - halbtc8821c1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_1ANT_PHASE_5G_RUNTIME); + if (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) { + if (wifi_link_info_ext->is_all_under_5g) + phase = BT_8821C_1ANT_PHASE_5G; else - halbtc8821c1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_1ANT_PHASE_2G_RUNTIME); + phase = BT_8821C_1ANT_PHASE_2G; } else { - - halbtc8821c1ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_1ANT_PHASE_WLAN_OFF); + phase = BT_8821C_1ANT_PHASE_WOFF; } - btcoexist->stop_coex_dm = TRUE; - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + halbtc8821c1ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + phase); + btc->stop_coex_dm = TRUE; + } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify to WAKE UP\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_ACTIVE | - BT_8821C_1ANT_SCOREBOARD_ONOFF, - TRUE); -#endif - btcoexist->stop_coex_dm = FALSE; + coex_sta->wl_pnp_wakeup_downcnt = 3; + + /*WoWLAN*/ + if (pre_pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT || + pnp_state == BTC_WIFI_PNP_WOWLAN) { + coex_sta->run_time_state = TRUE; + btc->stop_coex_dm = FALSE; + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_PNP); + } } + pre_pnp_state = pnp_state; } - -void ex_halbtc8821c1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c1ant_coex_dm_reset(struct btc_coexist *btc) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], *****************Coex DM Reset*****************\n"); BTC_TRACE(trace_buf); - halbtc8821c1ant_init_hw_config(btcoexist, FALSE, FALSE); - halbtc8821c1ant_init_coex_dm(btcoexist); + halbtc8821c1ant_init_hw_config(btc, FALSE, FALSE); + halbtc8821c1ant_init_coex_dm(btc); } -void ex_halbtc8821c1ant_periodical(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c1ant_periodical(struct btc_coexist *btc) { - - struct btc_board_info *board_info = &btcoexist->board_info; + struct coex_sta_8821c_1ant *coex_sta = &btc->coex_sta_8821c_1ant; + struct btc_board_info *board_info = &btc->board_info; boolean wifi_busy = FALSE; u16 bt_scoreboard_val = 0; - boolean bt_relink_finish = FALSE; + boolean bt_relink_finish = FALSE, is_defreeze = FALSE; + static u8 freeze_cnt; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ************* Periodical *************\n"); BTC_TRACE(trace_buf); -#if (BT_AUTO_REPORT_ONLY_8821C_1ANT == 0) - halbtc8821c1ant_query_bt_info(btcoexist); + if (!btc->auto_report) + halbtc8821c1ant_query_bt_info(btc); -#endif - - halbtc8821c1ant_monitor_bt_ctr(btcoexist); - halbtc8821c1ant_monitor_wifi_ctr(btcoexist); - - halbtc8821c1ant_monitor_bt_enable_disable(btcoexist); - -#if 0 - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - /* halbtc8821c1ant_read_score_board(btcoexist, &bt_scoreboard_val); */ - - if (wifi_busy) { - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, TRUE); - /* - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_WLBUSY, TRUE); - - if (bt_scoreboard_val & BIT(6)) - halbtc8821c1ant_query_bt_info(btcoexist); */ - } else { - halbtc8821c1ant_post_state_to_bt(btcoexist, - BT_8821C_1ANT_SCOREBOARD_UNDERTEST, FALSE); - } -#endif + halbtc8821c1ant_monitor_bt_ctr(btc); + halbtc8821c1ant_monitor_wifi_ctr(btc); + halbtc8821c1ant_update_wifi_link_info(btc, + BT_8821C_1ANT_RSN_PERIODICAL); + halbtc8821c1ant_monitor_bt_enable(btc); if (coex_sta->bt_relink_downcount != 0) { coex_sta->bt_relink_downcount--; if (coex_sta->bt_relink_downcount == 0) { - coex_sta->is_setupLink = FALSE; + coex_sta->is_setup_link = FALSE; bt_relink_finish = TRUE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link stop by periodical count-down!!\n"); + BTC_TRACE(trace_buf); + } + } + + if (coex_sta->freeze_coexrun_by_btinfo) { + freeze_cnt++; + + if (freeze_cnt >= 5) { + freeze_cnt = 0; + coex_sta->freeze_coexrun_by_btinfo = FALSE; + is_defreeze = TRUE; } + } else { + freeze_cnt = 0; } /* for 4-way, DHCP, EAPOL packet */ if (coex_sta->specific_pkt_period_cnt > 0) { - coex_sta->specific_pkt_period_cnt--; - if ((coex_sta->specific_pkt_period_cnt == 0) && - (coex_sta->wifi_is_high_pri_task)) - coex_sta->wifi_is_high_pri_task = FALSE; + if (!coex_sta->freeze_coexrun_by_btinfo && + coex_sta->specific_pkt_period_cnt == 0) + coex_sta->wifi_high_pri_task1 = FALSE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ***************** Hi-Pri Task = %s\n", - (coex_sta->wifi_is_high_pri_task ? "Yes" : - "No")); + "[BTCoex], Hi-Pri Task = %s\n", + (coex_sta->wifi_high_pri_task1 ? "Yes" : "No")); BTC_TRACE(trace_buf); - } - if (halbtc8821c1ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish) - || (coex_sta->is_set_ps_state_fail)) - halbtc8821c1ant_run_coexist_mechanism(btcoexist); - -} - -/*#pragma optimize( "", off )*/ -void ex_halbtc8821c1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - -} - - -void ex_halbtc8821c1ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{ - -} - -void ex_halbtc8821c1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - + /*for A2DP glitch during connecting AP*/ + if (coex_sta->connect_ap_period_cnt > 0) + coex_sta->connect_ap_period_cnt--; -} - -void ex_halbtc8821c1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ + if (coex_sta->wl_pnp_wakeup_downcnt > 0) { + coex_sta->wl_pnp_wakeup_downcnt--; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wl_pnp_wakeup_downcnt = %d!!\n", + coex_sta->wl_pnp_wakeup_downcnt); + BTC_TRACE(trace_buf); + } + if (coex_sta->cnt_bt_reenable > 0) { + coex_sta->cnt_bt_reenable--; + if (coex_sta->cnt_bt_reenable == 0) { + coex_sta->is_bt_reenable = FALSE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT renable 30s finish!!\n"); + BTC_TRACE(trace_buf); + } + } + if (halbtc8821c1ant_moniter_wifibt_status(btc) || bt_relink_finish || + coex_sta->is_set_ps_state_fail || is_defreeze) + halbtc8821c1ant_run_coex(btc, BT_8821C_1ANT_RSN_PERIODICAL); } - +/*#pragma optimize( "", off )*/ #endif #endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */ diff --git a/hal/btc/halbtc8821c1ant.h b/hal/btc/halbtc8821c1ant.h index e6d2ce9..b62924e 100644 --- a/hal/btc/halbtc8821c1ant.h +++ b/hal/btc/halbtc8821c1ant.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) @@ -9,482 +23,450 @@ #define BT_8821C_1ANT_COEX_DBG 0 #define BT_AUTO_REPORT_ONLY_8821C_1ANT 1 -#define BT_INFO_8821C_1ANT_B_FTP BIT(7) -#define BT_INFO_8821C_1ANT_B_A2DP BIT(6) -#define BT_INFO_8821C_1ANT_B_HID BIT(5) +#define BT_INFO_8821C_1ANT_B_FTP BIT(7) +#define BT_INFO_8821C_1ANT_B_A2DP BIT(6) +#define BT_INFO_8821C_1ANT_B_HID BIT(5) #define BT_INFO_8821C_1ANT_B_SCO_BUSY BIT(4) #define BT_INFO_8821C_1ANT_B_ACL_BUSY BIT(3) #define BT_INFO_8821C_1ANT_B_INQ_PAGE BIT(2) #define BT_INFO_8821C_1ANT_B_SCO_ESCO BIT(1) #define BT_INFO_8821C_1ANT_B_CONNECTION BIT(0) -#define BT_INFO_8821C_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ - (((_BT_INFO_EXT_&BIT(0))) ? TRUE : FALSE) - #define BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT 2 -#define BT_8821C_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ -#define BT_8821C_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */ - - -/* for Antenna detection */ -#define BT_8821C_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 -#define BT_8821C_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 -#define BT_8821C_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 -#define BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT 35 -#define BT_8821C_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8821C_1ANT_ANTDET_SWEEPPOINT_DELAY 60000 -#define BT_8821C_1ANT_ANTDET_ENABLE 0 -#define BT_8821C_1ANT_ANTDET_BTTXTIME 100 -#define BT_8821C_1ANT_ANTDET_BTTXCHANNEL 39 -#define BT_8821C_1ANT_ANTDET_PSD_SWWEEPCOUNT 50 - -#define BT_8821C_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 +#define BT_8821C_1ANT_WIFI_NOISY_THRESH 30 +#define BT_8821C_1ANT_DEFAULT_ISOLATION 15 enum bt_8821c_1ant_signal_state { - BT_8821C_1ANT_SIG_STA_SET_TO_LOW = 0x0, - BT_8821C_1ANT_SIG_STA_SET_BY_HW = 0x0, - BT_8821C_1ANT_SIG_STA_SET_TO_HIGH = 0x1, - BT_8821C_1ANT_SIG_STA_MAX + BT_8821C_1ANT_GNT_SET_TO_LOW = 0x0, + BT_8821C_1ANT_GNT_SET_TO_HIGH = 0x1, + BT_8821C_1ANT_GNT_SET_BY_HW = 0x2, + BT_8821C_1ANT_GNT_SET_MAX }; enum bt_8821c_1ant_path_ctrl_owner { BT_8821C_1ANT_PCO_BTSIDE = 0x0, - BT_8821C_1ANT_PCO_WLSIDE = 0x1, + BT_8821C_1ANT_PCO_WLSIDE = 0x1, BT_8821C_1ANT_PCO_MAX }; enum bt_8821c_1ant_gnt_ctrl_type { - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, - BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1, BT_8821C_1ANT_GNT_TYPE_MAX }; enum bt_8821c_1ant_gnt_ctrl_block { BT_8821C_1ANT_GNT_BLOCK_RFC_BB = 0x0, - BT_8821C_1ANT_GNT_BLOCK_RFC = 0x1, - BT_8821C_1ANT_GNT_BLOCK_BB = 0x2, + BT_8821C_1ANT_GNT_BLOCK_RFC = 0x1, + BT_8821C_1ANT_GNT_BLOCK_BB = 0x2, BT_8821C_1ANT_GNT_BLOCK_MAX }; enum bt_8821c_1ant_lte_coex_table_type { - BT_8821C_1ANT_CTT_WL_VS_LTE = 0x0, - BT_8821C_1ANT_CTT_BT_VS_LTE = 0x1, + BT_8821C_1ANT_CTT_WL_VS_LTE = 0x0, + BT_8821C_1ANT_CTT_BT_VS_LTE = 0x1, BT_8821C_1ANT_CTT_MAX }; enum bt_8821c_1ant_lte_break_table_type { - BT_8821C_1ANT_LBTT_WL_BREAK_LTE = 0x0, - BT_8821C_1ANT_LBTT_BT_BREAK_LTE = 0x1, - BT_8821C_1ANT_LBTT_LTE_BREAK_WL = 0x2, - BT_8821C_1ANT_LBTT_LTE_BREAK_BT = 0x3, + BT_8821C_1ANT_LBTT_WL_BREAK_LTE = 0x0, + BT_8821C_1ANT_LBTT_BT_BREAK_LTE = 0x1, + BT_8821C_1ANT_LBTT_LTE_BREAK_WL = 0x2, + BT_8821C_1ANT_LBTT_LTE_BREAK_BT = 0x3, BT_8821C_1ANT_LBTT_MAX }; enum bt_info_src_8821c_1ant { - BT_INFO_SRC_8821C_1ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8821C_1ANT_BT_RSP = 0x1, - BT_INFO_SRC_8821C_1ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8821C_1ANT_MAX + BT_8821C_1ANT_INFO_SRC_WIFI_FW = 0x0, + BT_8821C_1ANT_INFO_SRC_BT_RSP = 0x1, + BT_8821C_1ANT_INFO_SRC_BT_ACT = 0x2, + BT_8821C_1ANT_INFO_SRC_MAX }; enum bt_8821c_1ant_bt_status { - BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8821C_1ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8821C_1ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8821C_1ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8821C_1ANT_BT_STATUS_MAX + BT_8821C_1ANT_BSTATUS_NCON_IDLE = 0x0, + BT_8821C_1ANT_BSTATUS_CON_IDLE = 0x1, + BT_8821C_1ANT_BSTATUS_INQ_PAGE = 0x2, + BT_8821C_1ANT_BSTATUS_ACL_BUSY = 0x3, + BT_8821C_1ANT_BSTATUS_SCO_BUSY = 0x4, + BT_8821C_1ANT_BSTATUS_ACL_SCO_BUSY = 0x5, + BT_8821C_1ANT_BSTATUS_MAX }; enum bt_8821c_1ant_wifi_status { - BT_8821C_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821C_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, - BT_8821C_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, - BT_8821C_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, - BT_8821C_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, - BT_8821C_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, - BT_8821C_1ANT_WIFI_STATUS_MAX + BT_8821C_1ANT_WSTATUS_NCON_IDLE = 0x0, + BT_8821C_1ANT_WSTATUS_NCON_SCAN = 0x1, + BT_8821C_1ANT_WSTATUS_CON_SCAN = 0x2, + BT_8821C_1ANT_WSTATUS_CON_SPECPKT = 0x3, + BT_8821C_1ANT_WSTATUS_CON_IDLE = 0x4, + BT_8821C_1ANT_WSTATUS_CON_BUSY = 0x5, + BT_8821C_1ANT_WSTATUS_MAX }; enum bt_8821c_1ant_coex_algo { - BT_8821C_1ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8821C_1ANT_COEX_ALGO_SCO = 0x1, - BT_8821C_1ANT_COEX_ALGO_HID = 0x2, - BT_8821C_1ANT_COEX_ALGO_A2DP = 0x3, - BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8821C_1ANT_COEX_ALGO_PANEDR = 0x5, - BT_8821C_1ANT_COEX_ALGO_PANHS = 0x6, - BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8821C_1ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8821C_1ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8821C_1ANT_COEX_ALGO_MAX = 0xb, + BT_8821C_1ANT_COEX_UNDEFINED = 0x0, + BT_8821C_1ANT_COEX_SCO = 0x1, + BT_8821C_1ANT_COEX_HID = 0x2, + BT_8821C_1ANT_COEX_A2DP = 0x3, + BT_8821C_1ANT_COEX_A2DP_PANHS = 0x4, + BT_8821C_1ANT_COEX_PAN = 0x5, + BT_8821C_1ANT_COEX_PANHS = 0x6, + BT_8821C_1ANT_COEX_PAN_A2DP = 0x7, + BT_8821C_1ANT_COEX_PAN_HID = 0x8, + BT_8821C_1ANT_COEX_HID_A2DP_PAN = 0x9, + BT_8821C_1ANT_COEX_HID_A2DP = 0xa, + BT_8821C_1ANT_COEX_MAX = 0xb, }; enum bt_8821c_1ant_ext_ant_switch_type { - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0, - BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1, - BT_8821C_1ANT_EXT_ANT_SWITCH_NONE = 0x2, - BT_8821C_1ANT_EXT_ANT_SWITCH_MAX + BT_8821C_1ANT_USE_DPDT = 0x0, + BT_8821C_1ANT_USE_SPDT = 0x1, + BT_8821C_1ANT_SWITCH_NONE = 0x2, + BT_8821C_1ANT_SWITCH_MAX }; enum bt_8821c_1ant_ext_ant_switch_ctrl_type { - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, - BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_MAX + BT_8821C_1ANT_CTRL_BY_BBSW = 0x0, + BT_8821C_1ANT_CTRL_BY_PTA = 0x1, + BT_8821C_1ANT_CTRL_BY_ANTDIV = 0x2, + BT_8821C_1ANT_CTRL_BY_MAC = 0x3, + BT_8821C_1ANT_CTRL_BY_BT = 0x4, + BT_8821C_1ANT_CTRL_BY_FW = 0x5, + BT_8821C_1ANT_CTRL_MAX }; enum bt_8821c_1ant_ext_ant_switch_pos_type { - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT = 0x0, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG = 0x1, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA = 0x2, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE = 0x3, - BT_8821C_1ANT_EXT_ANT_SWITCH_TO_MAX + BT_8821C_1ANT_TO_BT = 0x0, + BT_8821C_1ANT_TO_WLG = 0x1, + BT_8821C_1ANT_TO_WLA = 0x2, + BT_8821C_1ANT_TO_NOCARE = 0x3, + BT_8821C_1ANT_TO_MAX }; -enum bt_8821c_1ant_ext_band_switch_pos_type { - BT_8821C_1ANT_EXT_BAND_SWITCH_TO_WLG = 0x0, - BT_8821C_1ANT_EXT_BAND_SWITCH_TO_WLA = 0x1, - BT_8821C_1ANT_EXT_BAND_SWITCH_TO_MAX +enum bt_8821c_1ant_phase { + BT_8821C_1ANT_PHASE_INIT = 0x0, + BT_8821C_1ANT_PHASE_WONLY = 0x1, + BT_8821C_1ANT_PHASE_WOFF = 0x2, + BT_8821C_1ANT_PHASE_2G = 0x3, + BT_8821C_1ANT_PHASE_5G = 0x4, + BT_8821C_1ANT_PHASE_BTMP = 0x5, + BT_8821C_1ANT_PHASE_ANTDET = 0x6, + BT_8821C_1ANT_PHASE_POWERON = 0x7, + BT_8821C_1ANT_PHASE_MCC = 0x8, + BT_8821C_1ANT_PHASE_MAX }; -enum bt_8821c_1ant_int_block { - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2, - BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_MAX +enum bt_8821c_1ant_scoreboard { + BT_8821C_1ANT_SCBD_ACTIVE = BIT(0), + BT_8821C_1ANT_SCBD_ONOFF = BIT(1), + BT_8821C_1ANT_SCBD_SCAN = BIT(2), + BT_8821C_1ANT_SCBD_UNDERTEST = BIT(3), + BT_8821C_1ANT_SCBD_WLBUSY = BIT(6), + BT_8821C_1ANT_SCBD_BTCQDDR = BIT(10) }; -enum bt_8821c_1ant_phase { - BT_8821C_1ANT_PHASE_COEX_INIT = 0x0, - BT_8821C_1ANT_PHASE_WLANONLY_INIT = 0x1, - BT_8821C_1ANT_PHASE_WLAN_OFF = 0x2, - BT_8821C_1ANT_PHASE_2G_RUNTIME = 0x3, - BT_8821C_1ANT_PHASE_5G_RUNTIME = 0x4, - BT_8821C_1ANT_PHASE_BTMPMODE = 0x5, - BT_8821C_1ANT_PHASE_ANTENNA_DET = 0x6, - BT_8821C_1ANT_PHASE_COEX_POWERON = 0x7, - BT_8821C_1ANT_PHASE_MAX +enum bt_8821c_1ant_RUNREASON { + BT_8821C_1ANT_RSN_2GSCANSTART = 0x0, + BT_8821C_1ANT_RSN_5GSCANSTART = 0x1, + BT_8821C_1ANT_RSN_SCANFINISH = 0x2, + BT_8821C_1ANT_RSN_2GSWITCHBAND = 0x3, + BT_8821C_1ANT_RSN_5GSWITCHBAND = 0x4, + BT_8821C_1ANT_RSN_2GCONSTART = 0x5, + BT_8821C_1ANT_RSN_5GCONSTART = 0x6, + BT_8821C_1ANT_RSN_2GCONFINISH = 0x7, + BT_8821C_1ANT_RSN_5GCONFINISH = 0x8, + BT_8821C_1ANT_RSN_2GMEDIA = 0x9, + BT_8821C_1ANT_RSN_5GMEDIA = 0xa, + BT_8821C_1ANT_RSN_MEDIADISCON = 0xb, + BT_8821C_1ANT_RSN_2GSPECIALPKT = 0xc, + BT_8821C_1ANT_RSN_5GSPECIALPKT = 0xd, + BT_8821C_1ANT_RSN_BTINFO = 0xe, + BT_8821C_1ANT_RSN_PERIODICAL = 0xf, + BT_8821C_1ANT_RSN_PNP = 0x10, + BT_8821C_1ANT_RSN_MAX }; -enum bt_8821c_1ant_Scoreboard { - BT_8821C_1ANT_SCOREBOARD_ACTIVE = BIT(0), - BT_8821C_1ANT_SCOREBOARD_ONOFF = BIT(1), - BT_8821C_1ANT_SCOREBOARD_SCAN = BIT(2), - BT_8821C_1ANT_SCOREBOARD_UNDERTEST = BIT(3), - BT_8821C_1ANT_SCOREBOARD_WLBUSY = BIT(6) +enum bt_8821c_1ant_WL_LINK_MODE { + BT_8821C_1ANT_WLINK_2G1PORT = 0x0, + BT_8821C_1ANT_WLINK_2GMPORT = 0x1, + BT_8821C_1ANT_WLINK_25GMPORT = 0x2, + BT_8821C_1ANT_WLINK_5G = 0x3, + BT_8821C_1ANT_WLINK_2GGO = 0x4, + BT_8821C_1ANT_WLINK_BTMR = 0x5, + BT_8821C_1ANT_WLINK_MAX }; struct coex_dm_8821c_1ant { /* hw setting */ - u32 pre_ant_pos_type; u32 cur_ant_pos_type; + /* fw mechanism */ boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; + u8 cur_ps_tdma; u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; - boolean pre_ps_tdma_on; boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; + boolean cur_bt_auto_report; - u8 pre_lps; u8 cur_lps; - u8 pre_rpwm; u8 cur_rpwm; /* sw mechanism */ - boolean pre_low_penalty_ra; boolean cur_low_penalty_ra; - u32 pre_val0x6c0; + u32 cur_val0x6c0; - u32 pre_val0x6c4; u32 cur_val0x6c4; - u32 pre_val0x6c8; u32 cur_val0x6c8; - u8 pre_val0x6cc; u8 cur_val0x6cc; - boolean limited_dig; - - u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ - u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ - u16 backup_retry_limit; - u8 backup_ampdu_max_time; /* algorithm related */ - u8 pre_algorithm; u8 cur_algorithm; u8 bt_status; u8 wifi_chnl_info[3]; - u32 pre_ra_mask; - u32 cur_ra_mask; - u8 pre_arfr_type; - u8 cur_arfr_type; - u8 pre_retry_limit_type; - u8 cur_retry_limit_type; - u8 pre_ampdu_time_type; - u8 cur_ampdu_time_type; u32 arp_cnt; - u32 pre_ext_ant_switch_status; u32 cur_ext_ant_switch_status; - - u8 pre_ext_band_switch_status; - u8 cur_ext_band_switch_status; - - u8 pre_int_block_status; - u8 cur_int_block_status; - - u8 error_condition; + u32 setting_tdma; }; struct coex_sta_8821c_1ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - u8 num_of_profile; - - boolean under_lps; - boolean under_ips; - u32 specific_pkt_period_cnt; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - boolean is_hiPri_rx_overhead; - s8 bt_rssi; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - u8 bt_info_c2h[BT_INFO_SRC_8821C_1ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8821C_1ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; - boolean c2h_bt_page; /* Add for win8.1 page out issue */ - boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ - - u8 bt_info_ext; - u8 bt_info_ext2; - u32 pop_event_cnt; - u8 scan_ap_num; - u8 bt_retry_cnt; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; - - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; - u8 coex_table_type; - - boolean force_lps_ctrl; - - boolean concurrent_rx_mode_on; - - u16 score_board; - u8 isolation_btween_wb; /* 0~ 50 */ - - u8 a2dp_bit_pool; - u8 cut_version; - boolean acl_busy; - boolean bt_create_connection; - - u32 bt_coex_supported_feature; - u32 bt_coex_supported_version; - - u8 bt_ble_scan_type; - u32 bt_ble_scan_para[3]; - - boolean run_time_state; - boolean freeze_coexrun_by_btinfo; - - boolean is_A2DP_3M; - boolean voice_over_HOGP; - u8 bt_info; - boolean is_autoslot; - u8 forbidden_slot; - u8 hid_busy_num; - u8 hid_pair_cnt; - - u32 cnt_RemoteNameReq; - u32 cnt_setupLink; - u32 cnt_ReInit; - u32 cnt_IgnWlanAct; - u32 cnt_Page; - u32 cnt_RoleSwitch; - - u16 bt_reg_vendor_ac; - u16 bt_reg_vendor_ae; - - boolean is_setupLink; - u8 wl_noisy_level; - u32 gnt_error_cnt; - - u8 bt_afh_map[10]; - u8 bt_relink_downcount; - boolean is_tdma_btautoslot; - boolean is_tdma_btautoslot_hang; - - u8 switch_band_notify_to; - boolean is_rf_state_off; - - boolean is_hid_low_pri_tx_overhead; - boolean is_bt_multi_link; - boolean is_bt_a2dp_sink; - boolean is_set_ps_state_fail; - u8 cnt_set_ps_state_fail; + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + boolean msft_mr_exist; + u8 num_of_profile; + + boolean under_lps; + boolean under_ips; + u32 specific_pkt_period_cnt; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + boolean is_hi_pri_rx_overhead; + s8 bt_rssi; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + u8 bt_info_c2h[BT_8821C_1ANT_INFO_SRC_MAX][10]; + u32 bt_info_c2h_cnt[BT_8821C_1ANT_INFO_SRC_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + boolean c2h_bt_page; + + boolean wifi_high_pri_task1; + boolean wifi_high_pri_task2; + + u8 bt_info_ext; + u8 bt_info_ext2; + u32 pop_event_cnt; + u8 scan_ap_num; + u8 bt_retry_cnt; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + boolean cck_lock; + boolean cck_lock_ever; + boolean cck_lock_warn; + + u8 coex_table_type; + boolean force_lps_ctrl; + boolean concurrent_rx_mode_on; + u16 score_board; + u8 isolation_btween_wb; /* 0~ 50 */ + + u8 a2dp_bit_pool; + u8 cut_version; + boolean acl_busy; + boolean bt_create_connection; + + u32 bt_coex_supported_feature; + u32 bt_coex_supported_version; + + u8 bt_ble_scan_type; + u32 bt_ble_scan_para[3]; + + boolean run_time_state; + boolean freeze_coexrun_by_btinfo; + + boolean is_A2DP_3M; + boolean voice_over_HOGP; + u8 bt_info; + boolean is_autoslot; + u8 forbidden_slot; + u8 hid_busy_num; + u8 hid_pair_cnt; + + u32 cnt_remote_name_req; + u32 cnt_setup_link; + u32 cnt_reinit; + u32 cnt_ign_wlan_act; + u32 cnt_page; + u32 cnt_role_switch; + + u16 bt_reg_vendor_ac; + u16 bt_reg_vendor_ae; + + boolean is_setup_link; + u8 wl_noisy_level; + u32 gnt_error_cnt; + + u8 bt_afh_map[10]; + u8 bt_relink_downcount; + boolean is_tdma_btautoslot; + boolean is_tdma_btautoslot_hang; + + u8 switch_band_notify_to; + boolean is_rf_state_off; + + boolean is_hid_low_pri_tx_overhead; + boolean is_bt_multi_link; + boolean is_bt_a2dp_sink; + boolean is_set_ps_state_fail; + u8 cnt_set_ps_state_fail; + + u8 wl_fw_dbg_info[10]; + u8 wl_rx_rate; + u8 wl_tx_rate; + u8 wl_rts_rx_rate; + u8 wl_center_channel; + u8 wl_tx_macid; + u8 wl_tx_retry_ratio; + + u16 score_board_WB; + boolean is_hid_rcu; + u16 legacy_forbidden_slot; + u16 le_forbidden_slot; + u8 bt_a2dp_vendor_id; + u32 bt_a2dp_device_name; + boolean is_ble_scan_en; + + boolean is_bt_opp_exist; + boolean gl_wifi_busy; + u8 connect_ap_period_cnt; + + boolean is_bt_reenable; + u8 cnt_bt_reenable; + boolean is_wifi_linkscan_process; + u8 wl_coex_mode; + u8 wl_pnp_wakeup_downcnt; + u32 coex_run_cnt; }; #define BT_8821C_1ANT_EXT_BAND_SWITCH_USE_DPDT 0 #define BT_8821C_1ANT_EXT_BAND_SWITCH_USE_SPDT 1 - struct rfe_type_8821c_1ant { - - u8 rfe_module_type; - boolean ext_ant_switch_exist; - u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ - u8 ext_ant_switch_ctrl_polarity; /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ - - boolean ext_band_switch_exist; - u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */ - u8 ext_band_switch_ctrl_polarity; - - boolean ant_at_main_port; - - boolean wlg_Locate_at_btg; /* If TRUE: WLG at BTG, If FALSE: WLG at WLAG */ - - boolean ext_ant_switch_diversity; /* If diversity on */ + u8 rfe_module_type; + boolean ext_ant_switch_exist; + /* 0:DPDT, 1:SPDT */ + u8 ext_ant_switch_type; + /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ + u8 ext_ant_switch_ctrl_polarity; + + boolean ext_band_switch_exist; + /* 0:DPDT, 1:SPDT */ + u8 ext_band_switch_type; + u8 ext_band_switch_ctrl_polarity; + boolean ant_at_main_port; + + /* If TRUE: WLG at BTG, If FALSE: WLG at WLAG */ + boolean wlg_locate_at_btg; + + /* If diversity on */ + boolean ext_ant_switch_diversity; }; -#define BT_8821C_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ -#define BT_8821C_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ -#define BT_8821C_1ANT_ANTDET_BUF_LEN 16 - -struct psdscan_sta_8821c_1ant { - - u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ - u32 ant_det_bt_tx_time; - u32 ant_det_pre_psdscan_peak_val; - boolean ant_det_is_ant_det_available; - u32 ant_det_psd_scan_peak_val; - boolean ant_det_is_btreply_available; - u32 ant_det_psd_scan_peak_freq; - - u8 ant_det_result; - u8 ant_det_peak_val[BT_8821C_1ANT_ANTDET_BUF_LEN]; - u8 ant_det_peak_freq[BT_8821C_1ANT_ANTDET_BUF_LEN]; - u32 ant_det_try_count; - u32 ant_det_fail_count; - u32 ant_det_inteval_count; - u32 ant_det_thres_offset; - - u32 real_cent_freq; - s32 real_offset; - u32 real_span; - - u32 psd_band_width; /* unit: Hz */ - u32 psd_point; /* 128/256/512/1024 */ - u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_start_point; - u32 psd_stop_point; - u32 psd_max_value_point; - u32 psd_max_value; - u32 psd_max_value2; - u32 psd_avg_value; /* filter loop_max_value that below BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ - u32 psd_loop_max_value[BT_8821C_1ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ - u32 psd_start_base; - u32 psd_avg_num; /* 1/8/16/32 */ - u32 psd_gen_count; - boolean is_AntDet_running; - boolean is_psd_show_max_only; +struct wifi_link_info_8821c_1ant { + u8 num_of_active_port; + u32 port_connect_status; + boolean is_all_under_5g; + boolean is_mcc_25g; + boolean is_p2p_connected; }; /* ******************************************* * The following is interface which will notify coex module. * ******************************************* */ -void ex_halbtc8821c1ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8821c1ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c1ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8821c1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c1ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8821c1ant_antenna_isolation(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); - -void ex_halbtc8821c1ant_psd_scan(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8821c1ant_display_ant_detection(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_power_on_setting(struct btc_coexist *btc); +void ex_halbtc8821c1ant_pre_load_firmware(struct btc_coexist *btc); +void ex_halbtc8821c1ant_init_hw_config(struct btc_coexist *btc, + boolean wifi_only); +void ex_halbtc8821c1ant_init_coex_dm(struct btc_coexist *btc); +void ex_halbtc8821c1ant_ips_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c1ant_lps_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c1ant_scan_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c1ant_switchband_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c1ant_connect_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c1ant_media_status_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c1ant_specific_packet_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c1ant_bt_info_notify(struct btc_coexist *btc, + u8 *tmp_buf, u8 length); +void ex_halbtc8821c1ant_wl_fwdbginfo_notify(struct btc_coexist *btc, + u8 *tmp_buf, u8 length); +void ex_halbtc8821c1ant_rx_rate_change_notify(struct btc_coexist *btc, + BOOLEAN is_data_frame, + u8 btc_rate_id); +void ex_halbtc8821c1ant_tx_rate_change_notify(struct btc_coexist *btc, + u8 tx_rate, + u8 tx_retry_ratio, u8 macid); +void ex_halbtc8821c1ant_rf_status_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c1ant_halt_notify(struct btc_coexist *btc); +void ex_halbtc8821c1ant_pnp_notify(struct btc_coexist *btc, + u8 pnp_state); +void ex_halbtc8821c1ant_coex_dm_reset(struct btc_coexist *btc); +void ex_halbtc8821c1ant_periodical(struct btc_coexist *btc); +void ex_halbtc8821c1ant_display_simple_coex_info(struct btc_coexist *btc); +void ex_halbtc8821c1ant_display_coex_info(struct btc_coexist *btc); #else -#define ex_halbtc8821c1ant_power_on_setting(btcoexist) -#define ex_halbtc8821c1ant_pre_load_firmware(btcoexist) -#define ex_halbtc8821c1ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8821c1ant_init_coex_dm(btcoexist) -#define ex_halbtc8821c1ant_ips_notify(btcoexist, type) -#define ex_halbtc8821c1ant_lps_notify(btcoexist, type) -#define ex_halbtc8821c1ant_scan_notify(btcoexist, type) -#define ex_halbtc8821c1ant_switchband_notify(btcoexist,type) -#define ex_halbtc8821c1ant_connect_notify(btcoexist, type) -#define ex_halbtc8821c1ant_media_status_notify(btcoexist, type) -#define ex_halbtc8821c1ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8821c1ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8821c1ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8821c1ant_halt_notify(btcoexist) -#define ex_halbtc8821c1ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8821c1ant_coex_dm_reset(btcoexist) -#define ex_halbtc8821c1ant_periodical(btcoexist) -#define ex_halbtc8821c1ant_display_coex_info(btcoexist) -#define ex_halbtc8821c1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8821c1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8821c1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds) -#define ex_halbtc8821c1ant_display_ant_detection(btcoexist) +#define ex_halbtc8821c1ant_power_on_setting(btc) +#define ex_halbtc8821c1ant_pre_load_firmware(btc) +#define ex_halbtc8821c1ant_init_hw_config(btc, wifi_only) +#define ex_halbtc8821c1ant_init_coex_dm(btc) +#define ex_halbtc8821c1ant_ips_notify(btc, type) +#define ex_halbtc8821c1ant_lps_notify(btc, type) +#define ex_halbtc8821c1ant_scan_notify(btc, type) +#define ex_halbtc8821c1ant_switchband_notify(btc, type) +#define ex_halbtc8821c1ant_connect_notify(btc, type) +#define ex_halbtc8821c1ant_media_status_notify(btc, type) +#define ex_halbtc8821c1ant_specific_packet_notify(btc, type) +#define ex_halbtc8821c1ant_bt_info_notify(btc, tmp_buf, length) +#define ex_halbtc8821c1ant_wl_fwdbginfo_notify(btc, tmp_buf, length) +#define ex_halbtc8821c1ant_rx_rate_change_notify(btc, is_data_frame, \ + btc_rate_id) +#define ex_halbtc8821c1ant_tx_rate_change_notify(btcoexist, tx_rate, \ + tx_retry_ratio, macid) +#define ex_halbtc8821c1ant_rf_status_notify(btc, type) +#define ex_halbtc8821c1ant_halt_notify(btc) +#define ex_halbtc8821c1ant_pnp_notify(btc, pnp_state) +#define ex_halbtc8821c1ant_coex_dm_reset(btc) +#define ex_halbtc8821c1ant_periodical(btc) +#define ex_halbtc8821c1ant_display_simple_coex_info(btc) +#define ex_halbtc8821c1ant_display_coex_info(btc) #endif #endif diff --git a/hal/btc/halbtc8821c2ant.c b/hal/btc/halbtc8821c2ant.c index ce475f1..f28fd84 100644 --- a/hal/btc/halbtc8821c2ant.c +++ b/hal/btc/halbtc8821c2ant.c @@ -1,33 +1,24 @@ -/* ************************************************************ - * Description: +/****************************************************************************** * - * This file is for RTL8821C Co-exist mechanism + * Copyright(c) 2016 - 2017 Realtek Corporation. * - * History - * 2012/11/15 Cosa first check in. + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. * - * ************************************************************ */ + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ -/* ************************************************************ - * include files - * ************************************************************ */ #include "mp_precomp.h" #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) #if (RTL8821C_SUPPORT == 1) -/* ************************************************************ - * Global variables, these are static variables - * ************************************************************ */ static u8 *trace_buf = &gl_btc_trace_buf[0]; -static struct coex_dm_8821c_2ant glcoex_dm_8821c_2ant; -static struct coex_dm_8821c_2ant *coex_dm = &glcoex_dm_8821c_2ant; -static struct coex_sta_8821c_2ant glcoex_sta_8821c_2ant; -static struct coex_sta_8821c_2ant *coex_sta = &glcoex_sta_8821c_2ant; -static struct psdscan_sta_8821c_2ant gl_psd_scan_8821c_2ant; -static struct psdscan_sta_8821c_2ant *psd_scan = &gl_psd_scan_8821c_2ant; -static struct rfe_type_8821c_2ant gl_rfe_type_8821c_2ant; -static struct rfe_type_8821c_2ant *rfe_type = &gl_rfe_type_8821c_2ant; const char *const glbt_info_src_8821c_2ant[] = { "BT Info[wifi fw]", @@ -35,23 +26,18 @@ const char *const glbt_info_src_8821c_2ant[] = { "BT Info[bt auto report]", }; -u32 glcoex_ver_date_8821c_2ant = 20170310; -u32 glcoex_ver_8821c_2ant = 0x12; -u32 glcoex_ver_btdesired_8821c_2ant = 0x11; - +u32 glcoex_ver_date_8821c_2ant = 20180712; +u32 glcoex_ver_8821c_2ant = 0x32; +u32 glcoex_ver_btdesired_8821c_2ant = 0x28; -/* ************************************************************ - * local function proto type if needed - * ************************************************************ - * ************************************************************ - * local function start with halbtc8821c2ant_ - * ************************************************************ */ -u8 halbtc8821c2ant_bt_rssi_state(IN struct btc_coexist *btcoexist, - u8 *ppre_bt_rssi_state, u8 level_num, +static +u8 halbtc8821c2ant_bt_rssi_state(struct btc_coexist *btc, + u8 *ppre_bt_rssi_state, u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) { - s32 bt_rssi = 0; - u8 bt_rssi_state = *ppre_bt_rssi_state; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + s32 bt_rssi = 0; + u8 bt_rssi_state = *ppre_bt_rssi_state; bt_rssi = coex_sta->bt_rssi; @@ -106,14 +92,16 @@ u8 halbtc8821c2ant_bt_rssi_state(IN struct btc_coexist *btcoexist, return bt_rssi_state; } -u8 halbtc8821c2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, - IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh, - IN u8 rssi_thresh1) +static +u8 halbtc8821c2ant_wifi_rssi_state(struct btc_coexist *btc, + u8 *pprewifi_rssi_state, + u8 level_num, + u8 rssi_thresh, u8 rssi_thresh1) { - s32 wifi_rssi = 0; - u8 wifi_rssi_state = *pprewifi_rssi_state; + s32 wifi_rssi = 0; + u8 wifi_rssi_state = *pprewifi_rssi_state; - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btc->btc_get(btc, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); if (level_num == 2) { if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || @@ -166,82 +154,138 @@ u8 halbtc8821c2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, return wifi_rssi_state; } -void halbtc8821c2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist, - IN u8 isolation_measuared) +static +void halbtc8821c2ant_coex_switch_thres(struct btc_coexist *btc, + u8 isolation_measuared) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; s8 interference_wl_tx = 0, interference_bt_tx = 0; - interference_wl_tx = BT_8821C_2ANT_WIFI_MAX_TX_POWER - - isolation_measuared; + isolation_measuared; interference_bt_tx = BT_8821C_2ANT_BT_MAX_TX_POWER - - isolation_measuared; + isolation_measuared; + coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; + coex_sta->wifi_coex_thres2 = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2; + coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1; + coex_sta->bt_coex_thres2 = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2; - coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; - coex_sta->wifi_coex_thres2 = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2; +#if 0 + coex_sta->wifi_coex_thres = + interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES1; + coex_sta->wifi_coex_thres2 = + interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES2; + + coex_sta->bt_coex_thres = + interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES1; + coex_sta->bt_coex_thres2 = + interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES2; + + if (BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < + (isolation_measuared - BT_8821C_2ANT_DEFAULT_ISOLATION)) + coex_sta->wifi_coex_thres = + BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; + else + coex_sta->wifi_coex_thres = + BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 - + (isolation_measuared - BT_8821C_2ANT_DEFAULT_ISOLATION); + + if (BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 < + (isolation_measuared - BT_8821C_2ANT_DEFAULT_ISOLATION)) + coex_sta->bt_coex_thres = + BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1; + else + coex_sta->bt_coex_thres = + BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 - + (isolation_measuared - BT_8821C_2ANT_DEFAULT_ISOLATION); - coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1; - coex_sta->bt_coex_thres2 = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2; +#endif +} +static +void halbtc8821c2ant_low_penalty_ra(struct btc_coexist *btc, + boolean force_exec, boolean low_penalty_ra, + u8 thres) +{ + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + static u8 cur_thres; - /* - coex_sta->wifi_coex_thres = interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES1; - coex_sta->wifi_coex_thres2 = interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES2; + if (!force_exec) { + if (low_penalty_ra == coex_dm->cur_low_penalty_ra && + thres == cur_thres) + return; + } - coex_sta->bt_coex_thres = interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES1; - coex_sta->bt_coex_thres2 = interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES2; - */ + if (low_penalty_ra) + btc->btc_phydm_modify_RA_PCR_threshold(btc, 0, thres); + else + btc->btc_phydm_modify_RA_PCR_threshold(btc, 0, 0); + coex_dm->cur_low_penalty_ra = low_penalty_ra; + cur_thres = thres; +} +static +void halbtc8821c2ant_set_antdiv_hwsw(struct btc_coexist *btc, + boolean force_exec, boolean is_hw_div) +{ + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + static u8 pre_antdiv_type; + coex_dm->cur_antdiv_type = ((is_hw_div) ? 1 : 0); + if (!force_exec) { + if (coex_dm->cur_antdiv_type == pre_antdiv_type) + return; + } - /* - if ( BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - - BT_8821C_2ANT_DEFAULT_ISOLATION) ) - coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; - else - coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - - BT_8821C_2ANT_DEFAULT_ISOLATION); + btc->btc_phydm_modify_antdiv_hwsw(btc, coex_dm->cur_antdiv_type); - if ( BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - - BT_8821C_2ANT_DEFAULT_ISOLATION) ) - coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1; - else - coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - - BT_8821C_2ANT_DEFAULT_ISOLATION); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s = %d!!\n", __func__, + coex_dm->cur_antdiv_type); + BTC_TRACE(trace_buf); - */ + pre_antdiv_type = coex_dm->cur_antdiv_type; } +static +void halbtc8821c2ant_write_scbd(struct btc_coexist *btc, u16 bitpos, + boolean state) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + static u16 originalval = 0x8002, preval; + + if (state) + originalval = originalval | bitpos; + else + originalval = originalval & (~bitpos); + + coex_sta->score_board_WB = originalval; + + if (originalval != preval) { + preval = originalval; + btc->btc_write_2byte(btc, 0xaa, originalval); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], %s: return for nochange\n", __func__); + BTC_TRACE(trace_buf); + } +} -void halbtc8821c2ant_limited_rx(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean rej_ap_agg_pkt, - IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +static +void halbtc8821c2ant_read_scbd(struct btc_coexist *btc, u16 *score_board_val) { - boolean reject_rx_agg = rej_ap_agg_pkt; - boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; - u8 rx_agg_size = agg_buf_size; - - /* ============================================ */ - /* Rx Aggregation related setting */ - /* ============================================ */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, - &reject_rx_agg); - /* decide BT control aggregation buf size or not */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, - &bt_ctrl_rx_agg_size); - /* aggregation buf size, only work when BT control Rx aggregation size. */ - btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); - /* real update aggregation setting */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + *score_board_val = (btc->btc_read_2byte(btc, 0xaa)) & 0x7fff; } -void halbtc8821c2ant_query_bt_info(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_query_bt_info(struct btc_coexist *btc) { - u8 h2c_parameter[1] = {0}; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + u8 h2c_parameter[1] = {0}; if (coex_sta->bt_disabled) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -250,28 +294,90 @@ void halbtc8821c2ant_query_bt_info(IN struct btc_coexist *btcoexist) return; } - h2c_parameter[0] |= BIT(0); /* trigger */ - btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); + btc->btc_fill_h2c(btc, 0x61, 1, h2c_parameter); } -void halbtc8821c2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_enable_gnt_to_gpio(struct btc_coexist *btc, + boolean isenable) { - u32 reg_hp_txrx, reg_lp_txrx, u32tmp; - u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; - static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, - cnt_autoslot_hang = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + static u8 bit_val[5] = {0, 0, 0, 0, 0}; + static boolean state; + + if (!btc->dbg_mode) + return; + + if (state == isenable) + return; + + state = isenable; + + if (isenable) { + /* enable GNT_WL, GNT_BT to GPIO for debug */ + btc->btc_write_1byte_bitmask(btc, 0x73, 0x8, 0x1); + + /* store original value */ + /*0x66[4] */ + bit_val[0] = (btc->btc_read_1byte(btc, 0x66) & BIT(4)) >> 4; + /*0x66[8] */ + bit_val[1] = (btc->btc_read_1byte(btc, 0x67) & BIT(0)); + /*0x40[19] */ + bit_val[2] = (btc->btc_read_1byte(btc, 0x42) & BIT(3)) >> 3; + /*0x64[15] */ + bit_val[3] = (btc->btc_read_1byte(btc, 0x65) & BIT(7)) >> 7; + /*0x70[18] */ + bit_val[4] = (btc->btc_read_1byte(btc, 0x72) & BIT(2)) >> 2; + + /* switch GPIO Mux */ + /*0x66[4] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x66, BIT(4), 0x0); + /*0x66[8] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x67, BIT(0), 0x0); + /*0x40[19] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x42, BIT(3), 0x0); + /*0x64[15] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x65, BIT(7), 0x0); + /*0x70[18] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x72, BIT(2), 0x0); + } else { + btc->btc_write_1byte_bitmask(btc, 0x73, 0x8, 0x0); + + /* Restore original value */ + /* switch GPIO Mux */ + /*0x66[4] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x66, BIT(4), bit_val[0]); + /*0x66[8] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x67, BIT(0), bit_val[1]); + /*0x40[19] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x42, BIT(3), bit_val[2]); + /*0x64[15] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x65, BIT(7), bit_val[3]); + /*0x70[18] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x72, BIT(2), bit_val[4]); + } +} + +static +void halbtc8821c2ant_monitor_bt_ctr(struct btc_coexist *btc) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk, cnt_slave, cnt_overhead, + cnt_autoslot_hang; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; reg_hp_txrx = 0x770; reg_lp_txrx = 0x774; - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + u32tmp = btc->btc_read_4byte(btc, reg_hp_txrx); reg_hp_tx = u32tmp & MASKLWORD; reg_hp_rx = (u32tmp & MASKHWORD) >> 16; - u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + u32tmp = btc->btc_read_4byte(btc, reg_lp_txrx); reg_lp_tx = u32tmp & MASKLWORD; reg_lp_rx = (u32tmp & MASKHWORD) >> 16; @@ -286,38 +392,36 @@ void halbtc8821c2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) BTC_TRACE(trace_buf); - if (BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) { + if (coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_NCON_IDLE) { if (coex_sta->high_priority_rx >= 15) { if (cnt_overhead < 3) cnt_overhead++; if (cnt_overhead == 3) - coex_sta->is_hiPri_rx_overhead = TRUE; + coex_sta->is_hi_pri_rx_overhead = TRUE; } else { if (cnt_overhead > 0) cnt_overhead--; if (cnt_overhead == 0) - coex_sta->is_hiPri_rx_overhead = FALSE; + coex_sta->is_hi_pri_rx_overhead = FALSE; } } else - coex_sta->is_hiPri_rx_overhead = FALSE; + coex_sta->is_hi_pri_rx_overhead = FALSE; /* reset counter */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + btc->btc_write_1byte(btc, 0x76e, 0xc); - if ((coex_sta->low_priority_tx > 1150) && - (!coex_sta->c2h_bt_inquiry_page)) + if (coex_sta->low_priority_tx > 1150 && + !coex_sta->c2h_bt_inquiry_page) coex_sta->pop_event_cnt++; - if ((coex_sta->low_priority_rx >= 1150) && - (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) - && (!coex_sta->under_ips) - && (!coex_sta->c2h_bt_inquiry_page) - && ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist))) { + if (coex_sta->low_priority_rx >= 1150 && + coex_sta->low_priority_rx >= coex_sta->low_priority_tx && + !coex_sta->under_ips && !coex_sta->c2h_bt_inquiry_page && + (bt_link_info->a2dp_exist || bt_link_info->pan_exist)) { if (cnt_slave >= 2) { bt_link_info->slave_role = TRUE; cnt_slave = 2; @@ -332,8 +436,8 @@ void halbtc8821c2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) } if (coex_sta->is_tdma_btautoslot) { - if ((coex_sta->low_priority_tx >= 1300) && - (coex_sta->low_priority_rx <= 150)) { + if (coex_sta->low_priority_tx >= 1300 && + coex_sta->low_priority_rx <= 150) { if (cnt_autoslot_hang >= 2) { coex_sta->is_tdma_btautoslot_hang = TRUE; cnt_autoslot_hang = 2; @@ -349,116 +453,95 @@ void halbtc8821c2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) } if (coex_sta->sco_exist) { - if ((coex_sta->high_priority_tx >= 400) && - (coex_sta->high_priority_rx >= 400)) - coex_sta->is_eSCO_mode = FALSE; + if (coex_sta->high_priority_tx >= 400 && + coex_sta->high_priority_rx >= 400) + coex_sta->is_esco_mode = FALSE; else - coex_sta->is_eSCO_mode = TRUE; + coex_sta->is_esco_mode = TRUE; } if (bt_link_info->hid_only) { - if (coex_sta->low_priority_rx > 50) + if (coex_sta->low_priority_tx > 100) coex_sta->is_hid_low_pri_tx_overhead = true; else coex_sta->is_hid_low_pri_tx_overhead = false; } if (!coex_sta->bt_disabled) { - - if ((coex_sta->high_priority_tx == 0) && - (coex_sta->high_priority_rx == 0) && - (coex_sta->low_priority_tx == 0) && - (coex_sta->low_priority_rx == 0)) { + if (coex_sta->high_priority_tx == 0 && + coex_sta->high_priority_rx == 0 && + coex_sta->low_priority_tx == 0 && + coex_sta->low_priority_rx == 0) { num_of_bt_counter_chk++; if (num_of_bt_counter_chk >= 3) { - halbtc8821c2ant_query_bt_info(btcoexist); + halbtc8821c2ant_query_bt_info(btc); num_of_bt_counter_chk = 0; } } } - } - -void halbtc8821c2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_monitor_wifi_ctr(struct btc_coexist *btc) { -#if 1 - s32 wifi_rssi = 0; - boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE, - wifi_scan = FALSE; - boolean bt_idle = FALSE, wl_idle = FALSE; - static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, - wl_noisy_count1 = 3, wl_noisy_count2 = 0; - u32 total_cnt, reg_val1, reg_val2, cck_cnt; - u32 cnt_crcok = 0, cnt_crcerr = 0; - static u8 cnt = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - - coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_CCK); - coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_LEGACY); - coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_HT); - coex_sta->crc_ok_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_OK_VHT); - - coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); - coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); - coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( - btcoexist, PHYDM_INFO_CRC32_ERROR_HT); - coex_sta->crc_err_11n_vht = - btcoexist->btc_phydm_query_PHY_counter( - btcoexist, - PHYDM_INFO_CRC32_ERROR_VHT); - - cnt_crcok = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g - + coex_sta->crc_ok_11n - + coex_sta->crc_ok_11n_vht; - - cnt_crcerr = coex_sta->crc_err_cck + coex_sta->crc_err_11g - + coex_sta->crc_err_11n - + coex_sta->crc_err_11n_vht; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + boolean wifi_busy = FALSE, wifi_scan = FALSE; + static u8 wl_noisy_count0, wl_noisy_count1 = 3, wl_noisy_count2; + u32 cnt_cck; + static u8 cnt_ccklocking; + u8 h2c_parameter[1] = {0}; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + + /* Only enable for windows becaus 8821cu + * H2C 0x69 unknown fail @ linux + */ + if (btc->chip_interface != BTC_INTF_USB) { + /*send h2c to query WL FW dbg info */ + if ((coex_dm->cur_ps_tdma_on && coex_sta->force_lps_ctrl) || + (coex_sta->acl_busy && bt_link_info->a2dp_exist)) { + h2c_parameter[0] = 0x8; + btc->btc_fill_h2c(btc, 0x69, 1, h2c_parameter); + } + } - if ((wifi_busy) && (cnt_crcerr != 0)) { + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - coex_sta->now_crc_ratio = cnt_crcok/cnt_crcerr; + coex_sta->crc_ok_cck = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CRC32_ERROR_VHT); - if (cnt == 0) - coex_sta->acc_crc_ratio = coex_sta->now_crc_ratio; - else - coex_sta->acc_crc_ratio = (coex_sta->acc_crc_ratio * 7 + - coex_sta->now_crc_ratio * 3)/10; + /* CCK lock identification */ + if (coex_sta->cck_lock) + cnt_ccklocking++; + else if (cnt_ccklocking != 0) + cnt_ccklocking--; - if (cnt >= 10) - cnt = 0; - else - cnt++; + if (cnt_ccklocking >= 3) { + cnt_ccklocking = 3; + coex_sta->cck_lock_ever = TRUE; } - cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; + /* WiFi environment noisy identification */ + cnt_cck = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; - if ((coex_dm->bt_status == - BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE) || - (coex_dm->bt_status == - BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE) || - (coex_sta->bt_disabled)) - bt_idle = TRUE; - - if (cck_cnt > 250) { + if (!wifi_busy && !coex_sta->cck_lock) { + if (cnt_cck > 250) { if (wl_noisy_count2 < 3) wl_noisy_count2++; @@ -467,7 +550,7 @@ void halbtc8821c2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) wl_noisy_count1 = 0; } - } else if (cck_cnt < 50) { + } else if (cnt_cck < 100) { if (wl_noisy_count0 < 3) wl_noisy_count0++; @@ -492,132 +575,522 @@ void halbtc8821c2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) coex_sta->wl_noisy_level = 1; else coex_sta->wl_noisy_level = 0; + } +} - if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { - total_cnt = cnt_crcok; - - if ((coex_dm->bt_status == - BT_8821C_1ANT_BT_STATUS_ACL_BUSY) || - (coex_dm->bt_status == - BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY) || - (coex_dm->bt_status == - BT_8821C_1ANT_BT_STATUS_SCO_BUSY)) { - if (coex_sta->crc_ok_cck > (total_cnt - - coex_sta->crc_ok_cck)) { - if (cck_lock_counter < 3) - cck_lock_counter++; - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; - } +static +void halbtc8821c2ant_monitor_bt_enable(struct btc_coexist *btc) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + static u32 bt_disable_cnt; + boolean bt_active = TRUE, bt_disabled = FALSE; + u16 u16tmp; + + /* Read BT on/off status from scoreboard[1], + * enable this only if BT patch support this feature + */ + halbtc8821c2ant_read_scbd(btc, &u16tmp); + + bt_active = u16tmp & BIT(1); + + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = FALSE; + btc->btc_set(btc, BTC_SET_BL_BT_DISABLE, &bt_disabled); + } else { + bt_disable_cnt++; + if (bt_disable_cnt >= 2) { + bt_disabled = TRUE; + bt_disable_cnt = 2; + } + + btc->btc_set(btc, BTC_SET_BL_BT_DISABLE, &bt_disabled); + } + + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + /*for win10 BT disable->enable trigger wifi scan issue */ + if (!coex_sta->bt_disabled) { + coex_sta->is_bt_reenable = TRUE; + coex_sta->cnt_bt_reenable = 15; } else { - if (cck_lock_counter > 0) - cck_lock_counter--; + coex_sta->is_bt_reenable = FALSE; + coex_sta->cnt_bt_reenable = 0; } - } else { - if (cck_lock_counter > 0) - cck_lock_counter--; } +} + +static +boolean halbtc8821c2ant_moniter_wifibt_status(struct btc_coexist + *btc) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct wifi_link_info_8821c_2ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_2ant; + static boolean pre_wifi_busy, pre_under_4way, + pre_bt_off, pre_bt_slave, pre_hid_low_pri_tx_overhead, + pre_wifi_under_lps, pre_bt_setup_link, + pre_cck_lock, pre_cck_lock_warn; + static u8 pre_hid_busy_num, pre_wl_noisy_level; + boolean wifi_busy = FALSE, under_4way = FALSE; + boolean wifi_connected = FALSE; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + static u8 cnt_wifi_busytoidle; + u32 num_of_wifi_link = 0, wifi_link_mode = 0; + static u32 pre_num_of_wifi_link, pre_wifi_link_mode; + boolean miracast_plus_bt = FALSE; - if (!coex_sta->pre_ccklock) { + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way); - if (cck_lock_counter >= 3) - coex_sta->cck_lock = TRUE; - else - coex_sta->cck_lock = FALSE; + if (wifi_busy) { + coex_sta->gl_wifi_busy = TRUE; + cnt_wifi_busytoidle = 6; } else { - if (cck_lock_counter == 0) - coex_sta->cck_lock = FALSE; - else - coex_sta->cck_lock = TRUE; + if (coex_sta->gl_wifi_busy && cnt_wifi_busytoidle > 0) + cnt_wifi_busytoidle--; + else if (cnt_wifi_busytoidle == 0) + coex_sta->gl_wifi_busy = FALSE; } - if (coex_sta->cck_lock) - coex_sta->cck_ever_lock = TRUE; + if (coex_sta->bt_disabled != pre_bt_off) { + pre_bt_off = coex_sta->bt_disabled; - coex_sta->pre_ccklock = coex_sta->cck_lock; + if (coex_sta->bt_disabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); -#endif -} + BTC_TRACE(trace_buf); -void halbtc8821c2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) -{ + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->legacy_forbidden_slot = 0; + coex_sta->le_forbidden_slot = 0; + coex_sta->bt_a2dp_vendor_id = 0; + coex_sta->bt_a2dp_device_name = 0; + return TRUE; + } - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = FALSE; - boolean bt_busy = FALSE; + num_of_wifi_link = wifi_link_info_ext->num_of_active_port; - coex_sta->num_of_profile = 0; + if (num_of_wifi_link != pre_num_of_wifi_link) { + pre_num_of_wifi_link = num_of_wifi_link; - /* set link exist status */ - if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { - coex_sta->bt_link_exist = FALSE; - coex_sta->pan_exist = FALSE; - coex_sta->a2dp_exist = FALSE; - coex_sta->hid_exist = FALSE; - coex_sta->sco_exist = FALSE; - } else { /* connection exists */ - coex_sta->bt_link_exist = TRUE; - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_FTP) { - coex_sta->pan_exist = TRUE; - coex_sta->num_of_profile++; - } else - coex_sta->pan_exist = FALSE; + if (wifi_link_info_ext->is_p2p_connected) { + if (bt_link_info->bt_link_exist) + miracast_plus_bt = TRUE; + else + miracast_plus_bt = FALSE; - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_A2DP) { - coex_sta->a2dp_exist = TRUE; - coex_sta->num_of_profile++; - } else - coex_sta->a2dp_exist = FALSE; + btc->btc_set(btc, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + } + return TRUE; + } - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_HID) { - coex_sta->hid_exist = TRUE; - coex_sta->num_of_profile++; - } else - coex_sta->hid_exist = FALSE; + wifi_link_mode = btc->wifi_link_info.link_mode; + if (wifi_link_mode != pre_wifi_link_mode) { + pre_wifi_link_mode = wifi_link_mode; + return TRUE; + } - if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) { - coex_sta->sco_exist = TRUE; - coex_sta->num_of_profile++; - } else - coex_sta->sco_exist = FALSE; + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + return TRUE; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return TRUE; + } + if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { + pre_wl_noisy_level = coex_sta->wl_noisy_level; + return TRUE; + } + if (coex_sta->under_lps != pre_wifi_under_lps) { + pre_wifi_under_lps = coex_sta->under_lps; + if (coex_sta->under_lps) + return TRUE; + } + if (coex_sta->cck_lock != pre_cck_lock) { + pre_cck_lock = coex_sta->cck_lock; + return TRUE; + } + if (coex_sta->cck_lock_warn != pre_cck_lock_warn) { + pre_cck_lock_warn = coex_sta->cck_lock_warn; + return TRUE; + } } + if (!coex_sta->bt_disabled) { +#if 0 + if (coex_sta->acl_busy != pre_bt_acl_busy) { + pre_bt_acl_busy = coex_sta->acl_busy; + btc->btc_set(btc, BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL, + &lna_lvl); + return TRUE; + } +#endif + if (coex_sta->hid_busy_num != pre_hid_busy_num) { + pre_hid_busy_num = coex_sta->hid_busy_num; + return TRUE; + } - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + if (bt_link_info->slave_role != pre_bt_slave) { + pre_bt_slave = bt_link_info->slave_role; + return TRUE; + } - bt_link_info->bt_link_exist = coex_sta->bt_link_exist; - bt_link_info->sco_exist = coex_sta->sco_exist; - bt_link_info->a2dp_exist = coex_sta->a2dp_exist; - bt_link_info->pan_exist = coex_sta->pan_exist; - bt_link_info->hid_exist = coex_sta->hid_exist; - bt_link_info->acl_busy = coex_sta->acl_busy; + if (pre_hid_low_pri_tx_overhead != + coex_sta->is_hid_low_pri_tx_overhead) { + pre_hid_low_pri_tx_overhead = + coex_sta->is_hid_low_pri_tx_overhead; + return TRUE; + } - /* work around for HS mode. */ - if (bt_hs_on) { - bt_link_info->pan_exist = TRUE; - bt_link_info->bt_link_exist = TRUE; + if (pre_bt_setup_link != coex_sta->is_setup_link) { + pre_bt_setup_link = coex_sta->is_setup_link; + return TRUE; + } } - /* check if Sco only */ - if (bt_link_info->sco_exist && - !bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->sco_only = TRUE; - else - bt_link_info->sco_only = FALSE; + return FALSE; +} - /* check if A2dp only */ - if (!bt_link_info->sco_exist && - bt_link_info->a2dp_exist && - !bt_link_info->pan_exist && - !bt_link_info->hid_exist) - bt_link_info->a2dp_only = TRUE; - else - bt_link_info->a2dp_only = FALSE; +static +void halbtc8821c2ant_update_wifi_link_info(struct btc_coexist *btc, u8 reason) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct wifi_link_info_8821c_2ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_2ant; + struct btc_wifi_link_info wifi_link_info; + u8 wifi_central_chnl = 0, num_of_wifi_link = 0; + boolean isunder5G = FALSE, ismcc25g = FALSE, isp2pconnected = FALSE; + u32 wifi_link_status = 0; + + btc->btc_get(btc, BTC_GET_U4_WIFI_LINK_STATUS, &wifi_link_status); + wifi_link_info_ext->port_connect_status = wifi_link_status & 0xffff; + + btc->btc_get(btc, BTC_GET_BL_WIFI_LINK_INFO, &wifi_link_info); + btc->wifi_link_info = wifi_link_info; + + btc->btc_get(btc, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifi_central_chnl); + coex_sta->wl_center_channel = wifi_central_chnl; + + /* Check scan/connect/special-pkt action first */ + switch (reason) { + case BT_8821C_2ANT_RSN_5GSCANSTART: + case BT_8821C_2ANT_RSN_5GSWITCHBAND: + case BT_8821C_2ANT_RSN_5GCONSTART: + isunder5G = TRUE; + break; + case BT_8821C_2ANT_RSN_2GSCANSTART: + case BT_8821C_2ANT_RSN_2GSWITCHBAND: + case BT_8821C_2ANT_RSN_2GCONSTART: + isunder5G = FALSE; + break; + case BT_8821C_2ANT_RSN_2GCONFINISH: + case BT_8821C_2ANT_RSN_5GCONFINISH: + case BT_8821C_2ANT_RSN_2GMEDIA: + case BT_8821C_2ANT_RSN_5GMEDIA: + case BT_8821C_2ANT_RSN_BTINFO: + case BT_8821C_2ANT_RSN_PERIODICAL: + case BT_8821C_2ANT_RSN_2GSPECIALPKT: + case BT_8821C_2ANT_RSN_5GSPECIALPKT: + default: + switch (wifi_link_info.link_mode) { + case BTC_LINK_5G_MCC_GO_STA: + case BTC_LINK_5G_MCC_GC_STA: + case BTC_LINK_5G_SCC_GO_STA: + case BTC_LINK_5G_SCC_GC_STA: + isunder5G = TRUE; + break; + case BTC_LINK_2G_MCC_GO_STA: + case BTC_LINK_2G_MCC_GC_STA: + case BTC_LINK_2G_SCC_GO_STA: + case BTC_LINK_2G_SCC_GC_STA: + isunder5G = FALSE; + break; + case BTC_LINK_25G_MCC_GO_STA: + case BTC_LINK_25G_MCC_GC_STA: + isunder5G = FALSE; + ismcc25g = TRUE; + break; + case BTC_LINK_ONLY_STA: + if (wifi_link_info.sta_center_channel > 14) + isunder5G = TRUE; + else + isunder5G = FALSE; + break; + case BTC_LINK_ONLY_GO: + case BTC_LINK_ONLY_GC: + case BTC_LINK_ONLY_AP: + default: + if (wifi_link_info.p2p_center_channel > 14) + isunder5G = TRUE; + else + isunder5G = FALSE; + + break; + } + break; + } + + wifi_link_info_ext->is_all_under_5g = isunder5G; + wifi_link_info_ext->is_mcc_25g = ismcc25g; + + if (wifi_link_status & WIFI_STA_CONNECTED) + num_of_wifi_link++; + + if (wifi_link_status & WIFI_AP_CONNECTED) + num_of_wifi_link++; + + if (wifi_link_status & WIFI_P2P_GO_CONNECTED) { + num_of_wifi_link++; + isp2pconnected = TRUE; + } + + if (wifi_link_status & WIFI_P2P_GC_CONNECTED) { + num_of_wifi_link++; + isp2pconnected = TRUE; + } + + wifi_link_info_ext->num_of_active_port = num_of_wifi_link; + wifi_link_info_ext->is_p2p_connected = isp2pconnected; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_link_info: link_mode=%d, STA_Ch=%d, P2P_Ch=%d, AnyClient_Join_Go=%d !\n", + btc->wifi_link_info.link_mode, + btc->wifi_link_info.sta_center_channel, + btc->wifi_link_info.p2p_center_channel, + btc->wifi_link_info.bany_client_join_go); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_link_info: center_ch=%d, is_all_under_5g=%d, is_mcc_25g=%d!\n", + coex_sta->wl_center_channel, + wifi_link_info_ext->is_all_under_5g, + wifi_link_info_ext->is_mcc_25g); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_link_info: port_connect_status=0x%x, active_port_cnt=%d, P2P_Connect=%d!\n", + wifi_link_info_ext->port_connect_status, + wifi_link_info_ext->num_of_active_port, + wifi_link_info_ext->is_p2p_connected); + BTC_TRACE(trace_buf); + + switch (reason) { + case BT_8821C_2ANT_RSN_2GSCANSTART: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "2GSCANSTART"); + break; + case BT_8821C_2ANT_RSN_5GSCANSTART: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "5GSCANSTART"); + break; + case BT_8821C_2ANT_RSN_SCANFINISH: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "SCANFINISH"); + break; + case BT_8821C_2ANT_RSN_2GSWITCHBAND: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "2GSWITCHBAND"); + break; + case BT_8821C_2ANT_RSN_5GSWITCHBAND: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "5GSWITCHBAND"); + break; + case BT_8821C_2ANT_RSN_2GCONSTART: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "2GCONNECTSTART"); + break; + case BT_8821C_2ANT_RSN_5GCONSTART: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "5GCONNECTSTART"); + break; + case BT_8821C_2ANT_RSN_2GCONFINISH: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", + "2GCONNECTFINISH"); + break; + case BT_8821C_2ANT_RSN_5GCONFINISH: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", + "5GCONNECTFINISH"); + break; + case BT_8821C_2ANT_RSN_2GMEDIA: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "2GMEDIASTATUS"); + break; + case BT_8821C_2ANT_RSN_5GMEDIA: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "5GMEDIASTATUS"); + break; + case BT_8821C_2ANT_RSN_MEDIADISCON: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", + "MEDIADISCONNECT"); + break; + case BT_8821C_2ANT_RSN_2GSPECIALPKT: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "2GSPECIALPKT"); + break; + case BT_8821C_2ANT_RSN_5GSPECIALPKT: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "5GSPECIALPKT"); + break; + case BT_8821C_2ANT_RSN_BTINFO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "BTINFO"); + break; + case BT_8821C_2ANT_RSN_PERIODICAL: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "PERIODICAL"); + break; + case BT_8821C_2ANT_RSN_PNP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "PNPNotify"); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Update reason = %s\n", "UNKNOWN"); + break; + } + + BTC_TRACE(trace_buf); + + if (wifi_link_info_ext->is_all_under_5g || + coex_sta->num_of_profile == 0) + halbtc8821c2ant_low_penalty_ra(btc, NM_EXCU, FALSE, 0); + else if (wifi_link_info_ext->is_p2p_connected) + halbtc8821c2ant_low_penalty_ra(btc, NM_EXCU, TRUE, 30); + else + halbtc8821c2ant_low_penalty_ra(btc, NM_EXCU, TRUE, 15); +} + +static +void halbtc8821c2ant_update_bt_link_info(struct btc_coexist *btc) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + boolean bt_busy = FALSE, increase_scan_dev_num = FALSE; + u32 val = 0; + static u8 pre_num_of_profile, cur_num_of_profile, cnt, ble_cnt; + + if (++ble_cnt >= 3) + ble_cnt = 0; + + if (coex_sta->is_ble_scan_en && ble_cnt == 0) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = + btc->btc_get_ble_scan_type_from_bt(btc); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = + btc->btc_get_ble_scan_para_from_bt(btc, 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = + btc->btc_get_ble_scan_para_from_bt(btc, 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = + btc->btc_get_ble_scan_para_from_bt(btc, 0x4); + } + + coex_sta->num_of_profile = 0; + + /* set link exist status */ + if (!(coex_sta->bt_info & BT_INFO_8821C_2ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = FALSE; + coex_sta->pan_exist = FALSE; + coex_sta->a2dp_exist = FALSE; + coex_sta->hid_exist = FALSE; + coex_sta->sco_exist = FALSE; + coex_sta->msft_mr_exist = FALSE; + } else { /* connection exists */ + coex_sta->bt_link_exist = TRUE; + if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_FTP) { + coex_sta->pan_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->pan_exist = FALSE; + } + + if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_A2DP) { + coex_sta->a2dp_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->a2dp_exist = FALSE; + } + + if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_HID) { + coex_sta->hid_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->hid_exist = FALSE; + } + + if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) { + coex_sta->sco_exist = TRUE; + coex_sta->num_of_profile++; + } else { + coex_sta->sco_exist = FALSE; + } + + if (coex_sta->hid_busy_num == 0 && + coex_sta->hid_pair_cnt > 0 && + coex_sta->low_priority_tx > 1000 && + coex_sta->low_priority_rx > 1000 && + !coex_sta->c2h_bt_inquiry_page) + coex_sta->msft_mr_exist = true; + else + coex_sta->msft_mr_exist = false; + } + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + bt_link_info->acl_busy = coex_sta->acl_busy; + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = TRUE; + else + bt_link_info->sco_only = FALSE; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = TRUE; + else + bt_link_info->a2dp_only = FALSE; /* check if Pan only */ if (!bt_link_info->sco_exist && @@ -638,481 +1111,369 @@ void halbtc8821c2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) bt_link_info->hid_only = FALSE; if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_INQ_PAGE) { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_INQ_PAGE; + coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_INQ_PAGE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); } else if (!(coex_sta->bt_info & BT_INFO_8821C_2ANT_B_CONNECTION)) { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_NCON_IDLE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); } else if (coex_sta->bt_info == BT_INFO_8821C_2ANT_B_CONNECTION) { /* connection exists but no busy */ - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + if (coex_sta->msft_mr_exist) { + coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!\n"); + } else { + coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_CON_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } } else if (((coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) || (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_BUSY)) && (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_ACL_BUSY)) { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY; + coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_ACL_SCO_BUSY; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); } else if ((coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) || (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_BUSY)) { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_SCO_BUSY; + coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_SCO_BUSY; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); } else if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_ACL_BUSY) { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_ACL_BUSY; + coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_ACL_BUSY; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); } else { - coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_MAX; + coex_dm->bt_status = BT_8821C_2ANT_BSTATUS_MAX; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); } BTC_TRACE(trace_buf); - if ((BT_8821C_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || - (BT_8821C_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || - (BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + if (coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_ACL_BUSY || + coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_SCO_BUSY || + coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_ACL_SCO_BUSY) { bt_busy = TRUE; - else + increase_scan_dev_num = TRUE; + } else { bt_busy = FALSE; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); -} - -void halbtc8821c2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, - IN u8 type) -{ - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - - /* only 2.4G we need to inform bt the chnl mask */ - btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, - &wifi_central_chnl); - if ((BTC_MEDIA_CONNECT == type) && - (wifi_central_chnl <= 14)) { - h2c_parameter[0] = - 0x1; /* enable BT AFH skip WL channel for 8821c because BT Rx LO interference */ - /* h2c_parameter[0] = 0x0; */ - h2c_parameter[1] = wifi_central_chnl; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - if (BTC_WIFI_BW_HT40 == wifi_bw) - h2c_parameter[2] = 0x30; - else - h2c_parameter[2] = 0x20; - } - - coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; - coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; - coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; - - btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); - -} - -void halbtc8821c2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, - IN u8 dac_swing_lvl) -{ - u8 h2c_parameter[1] = {0}; - - /* There are several type of dacswing */ - /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ - h2c_parameter[0] = dac_swing_lvl; - - btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); -} - -void halbtc8821c2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 fw_dac_swing_lvl) -{ - coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; - - if (!force_exec) { - if (coex_dm->pre_fw_dac_swing_lvl == - coex_dm->cur_fw_dac_swing_lvl) - return; - } - - halbtc8821c2ant_set_fw_dac_swing_level(btcoexist, - coex_dm->cur_fw_dac_swing_lvl); - - coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; -} - -void halbtc8821c2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN u8 dec_bt_pwr_lvl) -{ - u8 h2c_parameter[1] = {0}; - - h2c_parameter[0] = dec_bt_pwr_lvl; - -#if 0 - btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter); -#endif -} - -void halbtc8821c2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 dec_bt_pwr_lvl) -{ - coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; - - if (!force_exec) { - if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) - return; + increase_scan_dev_num = FALSE; } - halbtc8821c2ant_set_fw_dec_bt_pwr(btcoexist, - coex_dm->cur_bt_dec_pwr_lvl); - - coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; -} + btc->btc_set(btc, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + btc->btc_set(btc, BTC_SET_BL_INC_SCAN_DEV_NUM, &increase_scan_dev_num); -void halbtc8821c2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean low_penalty_ra) -{ + cur_num_of_profile = coex_sta->num_of_profile; -#if 1 - coex_dm->cur_low_penalty_ra = low_penalty_ra; + if (cur_num_of_profile != pre_num_of_profile) + cnt = 2; - if (!force_exec) { - if (coex_dm->pre_low_penalty_ra == - coex_dm->cur_low_penalty_ra) - return; + if (btc->board_info.customer_id == RT_CID_LENOVO_CHINA) { + if (cur_num_of_profile > 0) + halbtc8821c2ant_set_antdiv_hwsw(btc, NM_EXCU, TRUE); + else + halbtc8821c2ant_set_antdiv_hwsw(btc, NM_EXCU, FALSE); } - if (low_penalty_ra) - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); - else - btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); - - coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; - -#endif - -} - - -void halbtc8821c2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean enable_auto_report) -{ - u8 h2c_parameter[1] = {0}; + if (bt_link_info->a2dp_exist && (cnt > 0)) { + cnt--; + if (coex_sta->bt_a2dp_vendor_id == 0 && + coex_sta->bt_a2dp_device_name == 0) { + btc->btc_get(btc, BTC_GET_U4_BT_DEVICE_INFO, &val); - h2c_parameter[0] = 0; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), get BT DEVICE_INFO = %x\n", + val); + BTC_TRACE(trace_buf); - if (enable_auto_report) - h2c_parameter[0] |= BIT(0); + coex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff); + coex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8; + } - btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); -} + if (coex_sta->legacy_forbidden_slot == 0 && + coex_sta->le_forbidden_slot == 0) { + btc->btc_get(btc, BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL, + &val); -void halbtc8821c2ant_bt_auto_report(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable_auto_report) -{ - coex_dm->cur_bt_auto_report = enable_auto_report; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), get BT FORBIDDEN_SLOT_VAL = %x\n", + val); + BTC_TRACE(trace_buf); - if (!force_exec) { - if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) - return; + coex_sta->legacy_forbidden_slot = (u16)(val & 0xffff); + coex_sta->le_forbidden_slot = + (u16)((val & 0xffff0000) >> 16); + } } - halbtc8821c2ant_set_bt_auto_report(btcoexist, - coex_dm->cur_bt_auto_report); - - coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; -} - -void halbtc8821c2ant_write_score_board( - IN struct btc_coexist *btcoexist, - IN u16 bitpos, - IN boolean state -) -{ - - static u16 originalval = 0x8002; - - if (state) - originalval = originalval | bitpos; - else - originalval = originalval & (~bitpos); - - - btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); + pre_num_of_profile = coex_sta->num_of_profile; } -void halbtc8821c2ant_read_score_board( - IN struct btc_coexist *btcoexist, - IN u16 *score_board_val -) +static +void halbtc8821c2ant_update_wifi_ch_info(struct btc_coexist *btc, u8 type) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + struct wifi_link_info_8821c_2ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_2ant; + u8 h2c_parameter[3] = {0}, i; + u32 wifi_bw; + u8 wifi_central_chnl = 0; + u8 wifi_5g_chnl[19] = {120, 124, 128, 132, 136, 140, 144, 149, 153, 157, + 118, 126, 134, 142, 151, 159, 122, 138, 155}; + u8 bt_skip_cneter_chanl[19] = {2, 8, 17, 26, 34, 42, 51, 62, 71, 77, 2, + 12, 29, 46, 66, 76, 10, 37, 68}; + u8 bt_skip_span[19] = {4, 8, 8, 10, 8, 10, 8, 8, 10, 4, 4, 16, 16, 16, + 16, 4, 20, 34, 20}; + boolean is_any_connected = FALSE; + + if (btc->manual_control) + return; - *score_board_val = (btcoexist->btc_read_2byte(btcoexist, - 0xaa)) & 0x7fff; -} - - -void halbtc8821c2ant_post_state_to_bt( - IN struct btc_coexist *btcoexist, - IN u16 type, - IN boolean state -) -{ - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c2ant_post_state_to_bt: type = %d, state =%d\n", - type, state); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_write_score_board(btcoexist, (u16) type, state); -} - - -boolean halbtc8821c2ant_is_wifibt_status_changed(IN struct btc_coexist - *btcoexist) -{ - static boolean pre_wifi_busy = FALSE, pre_under_4way = FALSE, - pre_bt_hs_on = FALSE, pre_bt_off = FALSE, - pre_bt_slave = FALSE, pre_hid_low_pri_tx_overhead = FALSE, - pre_wifi_under_lps = FALSE; - static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0, - pre_bt_setup_link = FALSE; - boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE; - boolean wifi_connected = FALSE; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); - - if (coex_sta->bt_disabled != pre_bt_off) { - pre_bt_off = coex_sta->bt_disabled; - - if (coex_sta->bt_disabled) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled !!\n"); - else - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is enabled !!\n"); - - BTC_TRACE(trace_buf); - - coex_sta->bt_coex_supported_feature = 0; - coex_sta->bt_coex_supported_version = 0; - coex_sta->bt_ble_scan_type = 0; - coex_sta->bt_ble_scan_para[0] = 0; - coex_sta->bt_ble_scan_para[1] = 0; - coex_sta->bt_ble_scan_para[2] = 0; - coex_sta->bt_reg_vendor_ac = 0xffff; - coex_sta->bt_reg_vendor_ae = 0xffff; - return TRUE; + btc->btc_get(btc, BTC_GET_U4_WIFI_BW, &wifi_bw); + + if (btc->stop_coex_dm || coex_sta->is_rf_state_off) { + is_any_connected = FALSE; + wifi_central_chnl = 0; + } else if (type != BTC_MEDIA_DISCONNECT || + (type == BTC_MEDIA_DISCONNECT && + wifi_link_info_ext->num_of_active_port > 0)) { + if (wifi_link_info_ext->num_of_active_port == 1) { + if (wifi_link_info_ext->is_p2p_connected) + wifi_central_chnl = + btc->wifi_link_info + .p2p_center_channel; + else + wifi_central_chnl = + btc->wifi_link_info + .sta_center_channel; + } else { /* port > 2 */ + if ((btc->wifi_link_info + .p2p_center_channel > 14) && + (btc->wifi_link_info + .sta_center_channel > 14)) + wifi_central_chnl = + btc->wifi_link_info + .p2p_center_channel; + else if (btc->wifi_link_info + .p2p_center_channel <= 14) + wifi_central_chnl = + btc->wifi_link_info + .p2p_center_channel; + else if (btc->wifi_link_info + .sta_center_channel <= 14) + wifi_central_chnl = + btc->wifi_link_info + .sta_center_channel; + } } + if (wifi_central_chnl > 0) + is_any_connected = TRUE; - if (wifi_connected) { - if (wifi_busy != pre_wifi_busy) { - pre_wifi_busy = wifi_busy; + if (is_any_connected) { + if (wifi_central_chnl <= 14) { + h2c_parameter[0] = 0x1; + h2c_parameter[1] = wifi_central_chnl; - if (wifi_busy) - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, TRUE); + if (wifi_bw == BTC_WIFI_BW_HT40) + h2c_parameter[2] = 0x36; else - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, FALSE); - return TRUE; - } - if (under_4way != pre_under_4way) { - pre_under_4way = under_4way; - return TRUE; - } - if (bt_hs_on != pre_bt_hs_on) { - pre_bt_hs_on = bt_hs_on; - return TRUE; - } - if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { - pre_wl_noisy_level = coex_sta->wl_noisy_level; - return TRUE; - } - if (coex_sta->under_lps != pre_wifi_under_lps) { - pre_wifi_under_lps = coex_sta->under_lps; - if (coex_sta->under_lps == TRUE) - return TRUE; + h2c_parameter[2] = 0x24; + } else { /* for 5G */ + for (i = 0; i <= 18; i++) { + if (wifi_central_chnl == wifi_5g_chnl[i]) + break; + } + + if (i <= 18) { + h2c_parameter[0] = 0x3; + h2c_parameter[1] = bt_skip_cneter_chanl[i]; + h2c_parameter[2] = bt_skip_span[i]; + } } } - if (!coex_sta->bt_disabled) { - if (coex_sta->hid_busy_num != pre_hid_busy_num) { - pre_hid_busy_num = coex_sta->hid_busy_num; - return TRUE; - } + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btc->btc_fill_h2c(btc, 0x66, 3, h2c_parameter); - if (bt_link_info->slave_role != pre_bt_slave) { - pre_bt_slave = bt_link_info->slave_role; - return TRUE; - } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], para[0:2] = 0x%x 0x%x 0x%x\n", + h2c_parameter[0], h2c_parameter[1], h2c_parameter[2]); + BTC_TRACE(trace_buf); +} - if (pre_hid_low_pri_tx_overhead != coex_sta->is_hid_low_pri_tx_overhead) { - pre_hid_low_pri_tx_overhead = coex_sta->is_hid_low_pri_tx_overhead; - return TRUE; - } +static +void halbtc8821c2ant_set_wl_tx_power(struct btc_coexist *btc, + boolean force_exec, u8 wl_pwr_lvl) +{ + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; - if (pre_bt_setup_link != coex_sta->is_setupLink) { - pre_bt_setup_link = coex_sta->is_setupLink; - return TRUE; - } + if (!force_exec) { + if (wl_pwr_lvl == coex_dm->cur_wl_pwr_lvl) + return; } - return FALSE; + /* btc->btc_write_1byte_bitmask(btc, 0xc5b, 0xff, wl_pwr_lvl); */ + coex_dm->cur_wl_pwr_lvl = wl_pwr_lvl; } -void halbtc8821c2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_set_bt_tx_power(struct btc_coexist *btc, + boolean force_exec, u8 bt_pwr_lvl) { - static u32 bt_disable_cnt = 0; - boolean bt_active = TRUE, bt_disabled = FALSE, wifi_under_5g = FALSE; - u16 u16tmp; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + u8 h2c_parameter[1] = {0}; + + if (!force_exec) { + if (bt_pwr_lvl == coex_dm->cur_bt_pwr_lvl) + return; + } + + h2c_parameter[0] = 0 - bt_pwr_lvl; + btc->btc_fill_h2c(btc, 0x62, 1, h2c_parameter); + + coex_dm->cur_bt_pwr_lvl = bt_pwr_lvl; +} - /* This function check if bt is disabled */ #if 0 - if (coex_sta->high_priority_tx == 0 && - coex_sta->high_priority_rx == 0 && - coex_sta->low_priority_tx == 0 && - coex_sta->low_priority_rx == 0) - bt_active = FALSE; - if (coex_sta->high_priority_tx == 0xffff && - coex_sta->high_priority_rx == 0xffff && - coex_sta->low_priority_tx == 0xffff && - coex_sta->low_priority_rx == 0xffff) - bt_active = FALSE; +static +void halbtc8821c2ant_set_wl_rx_gain(struct btc_coexist *btc, + boolean force_exec, boolean agc_table_en) +{ + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + + u32 rx_gain_value_enable[] = {0xff000003, + 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, 0xbf050003, + 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, 0xb81c0003, + 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, 0xb3260003, + 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, 0xae300003, + 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 0x8c3a0003, + 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 0x6c440003, + 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 0x674e0003, + 0x66500003, 0x65520003, 0x64540003, 0x64560003, 0x007e0403}; + + u32 rx_gain_value_disable[] = {0xff000003, + 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, 0xf80a0003, + 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, 0xef1c0003, + 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, 0xea260003, + 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 0xe5300003, + 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 0xc43a0003, + 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 0xa5440003, + 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 0x834e0003, + 0x82500003, 0x81520003, 0x80540003, 0x65560003, 0x007e0403}; + u8 i; -#else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], *************wl rx gain*************\n"); + BTC_TRACE(trace_buf); - /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */ - halbtc8821c2ant_read_score_board(btcoexist, &u16tmp); + if (!force_exec) { + if (agc_table_en == coex_dm->cur_agc_table_en) + return; + } - bt_active = u16tmp & BIT(1); + if (agc_table_en) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table On!\n"); + BTC_TRACE(trace_buf); + for (i = 0; i <= 100; i++) { + btc->btc_write_4byte(btc, + 0x81c, rx_gain_value_enable[i]); -#endif + if (rx_gain_value_enable[i] == 0x007e0403) + break; + } - if (bt_active) { - bt_disable_cnt = 0; - bt_disabled = FALSE; - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } else { + /* set Rx filter corner RCK offset */ + btc->btc_set_rf_reg(btc, BTC_RF_A, 0xde, 0x2, 0x1); + btc->btc_set_rf_reg(btc, BTC_RF_A, 0x1d, 0x3f, 0x3f); - bt_disable_cnt++; - if (bt_disable_cnt >= 2) { - bt_disabled = TRUE; - bt_disable_cnt = 2; - } + /* ADC clock 80M + * btc->btc_write_1byte_bitmask(btc, 0x8ad, 0x3, 0x3); + */ - btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, - &bt_disabled); - } + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BB Agc Table Off!\n"); + BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + for (i = 0; i <= 100; i++) { + btc->btc_write_4byte(btc, + 0x81c, rx_gain_value_disable[i]); - if ((wifi_under_5g) || (bt_disabled)) - halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); - else - halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE); + if (rx_gain_value_disable[i] == 0x007e0403) + break; + } + /* set Rx filter corner RCK offset */ + btc->btc_set_rf_reg(btc, BTC_RF_A, 0x1d, 0x3f, 0x4); + btc->btc_set_rf_reg(btc, BTC_RF_A, 0xde, 0x2, 0x0); - if (coex_sta->bt_disabled != bt_disabled) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is from %s to %s!!\n", - (coex_sta->bt_disabled ? "disabled" : "enabled"), - (bt_disabled ? "disabled" : "enabled")); - BTC_TRACE(trace_buf); - coex_sta->bt_disabled = bt_disabled; - } + /* ADC clock 160M + * btc->btc_write_1byte_bitmask(btc, 0x8ad, 0x3, 0x0); + */ + } + coex_dm->cur_agc_table_en = agc_table_en; } -void halbtc8821c2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, - boolean isenable) +static +void halbtc8821c2ant_set_bt_rx_gain(struct btc_coexist *btc, + boolean force_exec, boolean rx_gain_en) { -#if BT_8821C_2ANT_COEX_DBG - static u8 bitVal[5] = {0, 0, 0, 0, 0}; - static boolean state = FALSE; - /* - if (state ==isenable) - return; - else - state = isenable; - */ - if (isenable) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], enable_gnt_to_gpio!!\n"); - BTC_TRACE(trace_buf); + u8 lna_constrain_level = 0; - /* enable GNT_WL, GNT_BT to GPIO for debug */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); + /* use scoreboard[4] to notify BT Rx gain table change */ + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_RXGAIN, + rx_gain_en); - /* store original value */ - bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, - 0x66) & BIT(4)) >> 4; /*0x66[4] */ - bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, - 0x67) & BIT(0)); /*0x66[8] */ - bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, - 0x42) & BIT(3)) >> 3; /*0x40[19] */ - bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, - 0x65) & BIT(7)) >> 7; /*0x64[15] */ - bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, - 0x72) & BIT(2)) >> 2; /*0x70[18] */ + if (rx_gain_en) + lna_constrain_level = 1; + else + lna_constrain_level = 7; - /* switch GPIO Mux */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), - 0x0); /*0x66[4] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), - 0x0); /*0x66[8] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), - 0x0); /*0x40[19] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), - 0x0); /*0x64[15] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), - 0x0); /*0x70[18] = 0 */ + btc->btc_set(btc, BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL, + &lna_constrain_level); +} +#endif +static +void halbtc8821c2ant_bt_auto_report(struct btc_coexist *btc, + boolean force_exec, + boolean enable_auto_report) +{ + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + u8 h2c_parameter[1] = {0}; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], disable_gnt_to_gpio!!\n"); - BTC_TRACE(trace_buf); + if (!force_exec) { + if (enable_auto_report == coex_dm->cur_bt_auto_report) + return; + } - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); - /* Restore original value */ - /* switch GPIO Mux */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), - bitVal[0]); /*0x66[4] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), - bitVal[1]); /*0x66[8] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), - bitVal[2]); /*0x40[19] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), - bitVal[3]); /*0x64[15] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), - bitVal[4]); /*0x70[18] = 0 */ - } + btc->btc_fill_h2c(btc, 0x68, 1, h2c_parameter); -#endif + coex_dm->cur_bt_auto_report = enable_auto_report; } -u32 halbtc8821c2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, - IN u16 reg_addr) +static +u32 halbtc8821c2ant_read_indirect_reg(struct btc_coexist *btc, u16 reg_addr) { u32 j = 0, delay_count = 0; while (1) { - if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) { + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; @@ -1122,28 +1483,25 @@ u32 halbtc8821c2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, break; } - /* wait for ready bit before access 0x1700 */ - btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); - - return btcoexist->btc_read_4byte(btcoexist, - 0x1708); /* get read data */ + /* wait for ready bit before access 0x1700 */ + btc->btc_write_4byte(btc, 0x1700, 0x800F0000 | reg_addr); + return btc->btc_read_4byte(btc, 0x1708); /* get read data */ } -void halbtc8821c2ant_ltecoex_indirect_write_reg(IN struct btc_coexist - *btcoexist, - IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) +static +void halbtc8821c2ant_write_indirect_reg(struct btc_coexist *btc, u16 reg_addr, + u32 bit_mask, u32 reg_value) { u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0; - if (bit_mask == 0x0) return; if (bit_mask == 0xffffffff) { /* wait for ready bit before access 0x1700/0x1704 */ while (1) { - if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) { + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; @@ -1153,11 +1511,9 @@ void halbtc8821c2ant_ltecoex_indirect_write_reg(IN struct btc_coexist break; } - btcoexist->btc_write_4byte(btcoexist, 0x1704, - reg_value); /* put write data */ - - btcoexist->btc_write_4byte(btcoexist, 0x1700, - 0xc00F0000 | reg_addr); + /* put write data */ + btc->btc_write_4byte(btc, 0x1704, reg_value); + btc->btc_write_4byte(btc, 0x1700, 0xc00F0000 | reg_addr); } else { for (i = 0; i <= 31; i++) { if (((bit_mask >> i) & 0x1) == 0x1) { @@ -1167,14 +1523,13 @@ void halbtc8821c2ant_ltecoex_indirect_write_reg(IN struct btc_coexist } /* read back register value before write */ - val = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - reg_addr); + val = halbtc8821c2ant_read_indirect_reg(btc, reg_addr); val = (val & (~bit_mask)) | (reg_value << bitpos); /* wait for ready bit before access 0x1700/0x1704 */ while (1) { - if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { - delay_ms(50); + if ((btc->btc_read_1byte(btc, 0x1703) & BIT(5)) == 0) { + delay_ms(10); delay_count++; if (delay_count >= 10) { delay_count = 0; @@ -1184,39 +1539,57 @@ void halbtc8821c2ant_ltecoex_indirect_write_reg(IN struct btc_coexist break; } - btcoexist->btc_write_4byte(btcoexist, 0x1704, - val); /* put write data */ - - btcoexist->btc_write_4byte(btcoexist, 0x1700, - 0xc00F0000 | reg_addr); + /* put write data */ + btc->btc_write_4byte(btc, 0x1704, val); + btc->btc_write_4byte(btc, 0x1700, 0xc00F0000 | reg_addr); } - } -void halbtc8821c2ant_ltecoex_enable(IN struct btc_coexist *btcoexist, - IN boolean enable) +static +void halbtc8821c2ant_ltecoex_enable(struct btc_coexist *btc, boolean enable) { u8 val; + /* 0x38[7] */ val = (enable) ? 1 : 0; - halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, - val); /* 0x38[7] */ + halbtc8821c2ant_write_indirect_reg(btc, 0x38, 0x80, val); +} + +static +void halbtc8821c2ant_ltecoex_table(struct btc_coexist *btc, u8 table_type, + u16 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8821C_2ANT_CTT_WL_VS_LTE: + reg_addr = 0xa0; + break; + case BT_8821C_2ANT_CTT_BT_VS_LTE: + reg_addr = 0xa4; + break; + } + /* 0xa0[15:0] or 0xa4[15:0] */ + if (reg_addr != 0x0000) + halbtc8821c2ant_write_indirect_reg(btc, reg_addr, 0xffff, + table_content); } -void halbtc8821c2ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, - IN boolean wifi_control) +static +void halbtc8821c2ant_coex_ctrl_owner(struct btc_coexist *btc, + boolean wifi_control) { u8 val; + /* 0x70[26] */ val = (wifi_control) ? 1 : 0; - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, - val); /* 0x70[26] */ - + btc->btc_write_1byte_bitmask(btc, 0x73, 0x4, val); } -void halbtc8821c2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) +static +void halbtc8821c2ant_set_gnt_bt(struct btc_coexist *btc, u8 control_block, + boolean sw_control, u8 state) { u32 val = 0, val_orig = 0; @@ -1227,8 +1600,7 @@ void halbtc8821c2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, else val = 0x1; - val_orig = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); + val_orig = halbtc8821c2ant_read_indirect_reg(btc, 0x38); switch (control_block) { case BT_8821C_2ANT_GNT_BLOCK_RFC_BB: @@ -1243,12 +1615,12 @@ void halbtc8821c2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, break; } - halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); + halbtc8821c2ant_write_indirect_reg(btc, 0x38, 0xffffffff, val); } -void halbtc8821c2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, - IN u8 control_block, IN boolean sw_control, IN u8 state) +static +void halbtc8821c2ant_set_gnt_wl(struct btc_coexist *btc, u8 control_block, + boolean sw_control, u8 state) { u32 val = 0, val_orig = 0; @@ -1259,8 +1631,7 @@ void halbtc8821c2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, else val = 0x1; - val_orig = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); + val_orig = halbtc8821c2ant_read_indirect_reg(btc, 0x38); switch (control_block) { case BT_8821C_2ANT_GNT_BLOCK_RFC_BB: @@ -1275,34 +1646,13 @@ void halbtc8821c2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, break; } - halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, - 0x38, 0xffffffff, val); -} - -void halbtc8821c2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u16 table_content) -{ - u16 reg_addr = 0x0000; - - switch (table_type) { - case BT_8821C_2ANT_CTT_WL_VS_LTE: - reg_addr = 0xa0; - break; - case BT_8821C_2ANT_CTT_BT_VS_LTE: - reg_addr = 0xa4; - break; - } - - if (reg_addr != 0x0000) - halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ - - + halbtc8821c2ant_write_indirect_reg(btc, 0x38, 0xffffffff, val); } - -void halbtc8821c2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, - IN u8 table_type, IN u8 table_content) +#if 0 +static +void halbtc8821c2ant_ltecoex_set_break_table(struct btc_coexist *btc, + u8 table_type, u8 table_content) { u16 reg_addr = 0x0000; @@ -1321,17 +1671,19 @@ void halbtc8821c2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, break; } + /* 0xa8[15:0] or 0xb4[15:0] */ if (reg_addr != 0x0000) - halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, - 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ - - + halbtc8821c2ant_write_indirect_reg(btc, reg_addr, 0xff, + table_content); } +#endif -void halbtc8821c2ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 interval, - IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, - IN u8 val0x6c4_b3) +#if 0 +static +void halbtc8821c2ant_set_wltoggle_coex_table(struct btc_coexist *btc, + boolean force_exec, u8 interval, + u8 val0x6c4_b0, u8 val0x6c4_b1, + u8 val0x6c4_b2, u8 val0x6c4_b3) { static u8 pre_h2c_parameter[6] = {0}; u8 cur_h2c_parameter[6] = {0}; @@ -1360,245 +1712,252 @@ void halbtc8821c2ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, for (i = 1; i <= 5; i++) pre_h2c_parameter[i] = cur_h2c_parameter[i]; - btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); + btc->btc_fill_h2c(btc, 0x69, 6, cur_h2c_parameter); } +#endif - - -void halbtc8821c2ant_set_coex_table(IN struct btc_coexist *btcoexist, - IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +static +void halbtc8821c2ant_coex_table(struct btc_coexist *btc, + boolean force_exec, u32 val0x6c0, + u32 val0x6c4, u32 val0x6c8, + u8 val0x6cc) { - btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); - - btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; - btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + if (!force_exec) { + if (val0x6c0 == coex_dm->cur_val0x6c0 && + val0x6c4 == coex_dm->cur_val0x6c4 && + val0x6c8 == coex_dm->cur_val0x6c8 && + val0x6cc == coex_dm->cur_val0x6cc) + return; + } - btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); -} + btc->btc_write_4byte(btc, 0x6c0, val0x6c0); + btc->btc_write_4byte(btc, 0x6c4, val0x6c4); + btc->btc_write_4byte(btc, 0x6c8, val0x6c8); + btc->btc_write_1byte(btc, 0x6cc, val0x6cc); -void halbtc8821c2ant_coex_table(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, - IN u32 val0x6c8, IN u8 val0x6cc) -{ coex_dm->cur_val0x6c0 = val0x6c0; coex_dm->cur_val0x6c4 = val0x6c4; coex_dm->cur_val0x6c8 = val0x6c8; coex_dm->cur_val0x6cc = val0x6cc; - - if (!force_exec) { - if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && - (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && - (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && - (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) - return; - } - halbtc8821c2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, - val0x6cc); - - coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; - coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; - coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; - coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; } -void halbtc8821c2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 type) +void halbtc8821c2ant_table(struct btc_coexist *btc, boolean force_exec, u8 type) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; u32 break_table; u8 select_table; coex_sta->coex_table_type = type; if (coex_sta->concurrent_rx_mode_on == TRUE) { - break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ - select_table = - 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ + /* set WL hi-pri can break BT */ + break_table = 0xf0ffffff; + /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ + select_table = 0x1b; } else { break_table = 0xffffff; - select_table = 0x3; + select_table = 0x13; } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Table-%d **********\n", + coex_sta->coex_table_type); + BTC_TRACE(trace_buf); + switch (type) { case 0: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0xffffffff, 0xffffffff, break_table, select_table); + halbtc8821c2ant_coex_table(btc, force_exec, 0xffffffff, + 0xffffffff, break_table, + select_table); break; case 1: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, select_table); + halbtc8821c2ant_coex_table(btc, force_exec, 0x55555555, + 0xfafafafa, break_table, + select_table); break; case 2: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table); + halbtc8821c2ant_coex_table(btc, force_exec, 0x5a5a5a5a, + 0x5a5a5a5a, break_table, + select_table); break; case 3: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, select_table); + halbtc8821c2ant_coex_table(btc, force_exec, 0x55555555, + 0x5a5a5a5a, break_table, + select_table); break; case 4: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x5a5a5a5a, break_table, select_table); + halbtc8821c2ant_coex_table(btc, force_exec, 0xffff55ff, + 0xfafafafa, break_table, + select_table); break; case 5: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0x55555555, break_table, select_table); + halbtc8821c2ant_coex_table(btc, force_exec, 0x55555555, + 0x55555555, break_table, + select_table); break; case 6: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xfafafafa, break_table, select_table); + halbtc8821c2ant_coex_table(btc, force_exec, 0xaaffffaa, + 0x5afa5afa, break_table, + select_table); break; case 7: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0xa5555555, 0xaa5a5a5a, break_table, select_table); + halbtc8821c2ant_coex_table(btc, force_exec, 0xaaffffaa, + 0xfafafafa, break_table, + select_table); break; case 8: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x55555555, 0xfafa5afa, break_table, select_table); + halbtc8821c2ant_coex_table(btc, force_exec, 0xffff55ff, + 0xfafafafa, break_table, + select_table); break; case 9: - halbtc8821c2ant_coex_table(btcoexist, force_exec, - 0x5a5a5a5a, 0xaaaa5aaa, break_table, select_table); + halbtc8821c2ant_coex_table(btc, force_exec, 0x5a5a5a5a, + 0xaaaa5aaa, break_table, + select_table); + break; + case 10: + halbtc8821c2ant_coex_table(btc, force_exec, 0xaaaaaaaa, + 0xaaaaaaaa, break_table, + select_table); + break; + case 11: + halbtc8821c2ant_coex_table(btc, force_exec, 0xffffffff, + 0xfafafafa, break_table, + select_table); + break; + case 12: + halbtc8821c2ant_coex_table(btc, force_exec, 0xffff55ff, + 0x5afa5afa, break_table, + select_table); + break; + case 14: + halbtc8821c2ant_coex_table(btc, force_exec, 0xffff55ff, + 0xaaaaaaaa, break_table, + select_table); + break; + case 15: + halbtc8821c2ant_coex_table(btc, force_exec, 0x65555555, + 0xaaaaaaaa, break_table, + select_table); break; default: break; } } -void halbtc8821c2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean enable) +static +void halbtc8821c2ant_ignore_wlan_act(struct btc_coexist *btc, + boolean force_exec, boolean enable) { - u8 h2c_parameter[1] = {0}; - - if (enable) { - h2c_parameter[0] |= BIT(0); /* function enable */ - } - - btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); -} + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + u8 h2c_parameter[1] = {0}; -void halbtc8821c2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean enable) -{ - coex_dm->cur_ignore_wlan_act = enable; + if (btc->manual_control || btc->stop_coex_dm) + return; if (!force_exec) { - if (coex_dm->pre_ignore_wlan_act == - coex_dm->cur_ignore_wlan_act) + if (enable == coex_dm->cur_ignore_wlan_act) return; } - halbtc8821c2ant_set_fw_ignore_wlan_act(btcoexist, enable); - coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; -} + if (enable) + h2c_parameter[0] |= BIT(0); /* function enable */ -void halbtc8821c2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, - IN u8 lps_val, IN u8 rpwm_val) -{ - u8 lps = lps_val; - u8 rpwm = rpwm_val; + btc->btc_fill_h2c(btc, 0x63, 1, h2c_parameter); - btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); - btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); + coex_dm->cur_ignore_wlan_act = enable; } -void halbtc8821c2ant_lps_rpwm(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +static +void halbtc8821c2ant_lps_rpwm(struct btc_coexist *btc, boolean force_exec, + u8 lps_val, u8 rpwm_val) { - coex_dm->cur_lps = lps_val; - coex_dm->cur_rpwm = rpwm_val; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; if (!force_exec) { - if ((coex_dm->pre_lps == coex_dm->cur_lps) && - (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + if (lps_val == coex_dm->cur_lps && + rpwm_val == coex_dm->cur_rpwm) return; } - halbtc8821c2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); - coex_dm->pre_lps = coex_dm->cur_lps; - coex_dm->pre_rpwm = coex_dm->cur_rpwm; + btc->btc_set(btc, BTC_SET_U1_LPS_VAL, &lps_val); + btc->btc_set(btc, BTC_SET_U1_RPWM_VAL, &rpwm_val); + + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; } -void halbtc8821c2ant_ps_tdma_check_for_power_save_state( - IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +static +void halbtc8821c2ant_tdma_check(struct btc_coexist *btc, boolean new_ps_state) { - u8 lps_mode = 0x0; - u8 h2c_parameter[5] = {0, 0, 0, 0x40, 0}; + u8 lps_mode = 0x0; + u8 h2c_parameter[5] = {0, 0, 0, 0x40, 0}; - btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + btc->btc_get(btc, BTC_GET_U1_LPS_MODE, &lps_mode); if (lps_mode) { /* already under LPS state */ if (new_ps_state) { /* keep state under LPS, do nothing. */ } else { /* will leave LPS state, turn off psTdma first */ - /*halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, - 8); */ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); + btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter); } } else { /* NO PS state */ if (new_ps_state) { /* will enter LPS state, turn off psTdma first */ - /*halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, - 8);*/ - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, - h2c_parameter); + btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter); } else { /* keep state under NO PS state, do nothing. */ } } } -boolean halbtc8821c2ant_power_save_state(IN struct btc_coexist *btcoexist, - IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +static +boolean halbtc8821c2ant_power_save_state(struct btc_coexist *btc, u8 ps_type, + u8 lps_val, u8 rpwm_val) { - boolean low_pwr_disable = FALSE, result = TRUE; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + boolean low_pwr_disable = FALSE, result = TRUE; switch (ps_type) { case BTC_PS_WIFI_NATIVE: coex_sta->force_lps_ctrl = FALSE; /* recover to original 32k low power setting */ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c2ant_power_save_state == BTC_PS_WIFI_NATIVE\n"); + "[BTCoex], %s == BTC_PS_WIFI_NATIVE\n", __func__); BTC_TRACE(trace_buf); low_pwr_disable = FALSE; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, - NULL); + /* btc->btc_set(btc, BTC_SET_ACT_DISABLE_LOW_POWER, + * &low_pwr_disable); + */ + btc->btc_set(btc, BTC_SET_ACT_PRE_NORMAL_LPS, NULL); break; case BTC_PS_LPS_ON: coex_sta->force_lps_ctrl = TRUE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c2ant_power_save_state == BTC_PS_LPS_ON\n"); + "[BTCoex], %s == BTC_PS_LPS_ON\n", __func__); BTC_TRACE(trace_buf); - halbtc8821c2ant_ps_tdma_check_for_power_save_state( - btcoexist, TRUE); - halbtc8821c2ant_lps_rpwm(btcoexist, NORMAL_EXEC, - lps_val, rpwm_val); + halbtc8821c2ant_tdma_check(btc, TRUE); + halbtc8821c2ant_lps_rpwm(btc, NM_EXCU, lps_val, rpwm_val); /* when coex force to enter LPS, do not enter 32k low power. */ low_pwr_disable = TRUE; - btcoexist->btc_set(btcoexist, - BTC_SET_ACT_DISABLE_LOW_POWER, - &low_pwr_disable); - /* power save must executed before psTdma. */ - btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, - NULL); + btc->btc_set(btc, BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma.*/ + btc->btc_set(btc, BTC_SET_ACT_ENTER_LPS, NULL); break; case BTC_PS_LPS_OFF: coex_sta->force_lps_ctrl = TRUE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c2ant_power_save_state == BTC_PS_LPS_OFF\n"); + "[BTCoex], %s == BTC_PS_LPS_OFF\n", __func__); BTC_TRACE(trace_buf); - halbtc8821c2ant_ps_tdma_check_for_power_save_state( - btcoexist, FALSE); - result = btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, - NULL); + halbtc8821c2ant_tdma_check(btc, FALSE); + result = btc->btc_set(btc, BTC_SET_ACT_LEAVE_LPS, NULL); break; default: break; @@ -1607,15 +1966,17 @@ boolean halbtc8821c2ant_power_save_state(IN struct btc_coexist *btcoexist, return result; } - - -void halbtc8821c2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, - IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +static +void halbtc8821c2ant_set_tdma(struct btc_coexist *btc, u8 byte1, u8 byte2, + u8 byte3, u8 byte4, u8 byte5) { - u8 h2c_parameter[5] = {0}; - u8 real_byte1 = byte1, real_byte5 = byte5; - boolean ap_enable = FALSE, result = FALSE; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = FALSE, result = FALSE; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + u8 ps_type = BTC_PS_WIFI_NATIVE; if (byte5 & BIT(2)) coex_sta->is_tdma_btautoslot = TRUE; @@ -1624,16 +1985,22 @@ void halbtc8821c2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, /* release bt-auto slot for auto-slot hang is detected!! */ if (coex_sta->is_tdma_btautoslot) - if ((coex_sta->is_tdma_btautoslot_hang) || - (bt_link_info->slave_role)) + if (coex_sta->is_tdma_btautoslot_hang || + bt_link_info->slave_role) byte5 = byte5 & 0xfb; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, - &ap_enable); +#if 1 + btc->btc_get(btc, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable); +#else + if (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO && + btc->wifi_link_info.bhotspot && + btc->wifi_link_info.bany_client_join_go) + ap_enable = TRUE; +#endif if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c2ant_set_fw_pstdma == FW for AP mode\n"); + "[BTCoex], %s == FW for AP mode\n", __func__); BTC_TRACE(trace_buf); real_byte1 &= ~BIT(4); @@ -1642,28 +2009,25 @@ void halbtc8821c2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, real_byte5 |= BIT(5); real_byte5 &= ~BIT(6); - halbtc8821c2ant_power_save_state(btcoexist, - BTC_PS_WIFI_NATIVE, 0x0, 0x0); + ps_type = BTC_PS_WIFI_NATIVE; + halbtc8821c2ant_power_save_state(btc, ps_type, 0x0, 0x0); } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c2ant_set_fw_pstdma == Force LPS Leave (byte1 = 0x%x)\n", byte1); + "[BTCoex], %s == Force LPS (byte1 = 0x%x)\n", + __func__, byte1); BTC_TRACE(trace_buf); -#if 0 - halbtc8821c2ant_power_save_state( - btcoexist, BTC_PS_LPS_ON, 0x50, 0x4); -#endif - if (!halbtc8821c2ant_power_save_state(btcoexist, BTC_PS_LPS_OFF, 0x50, 0x4)) + ps_type = BTC_PS_LPS_OFF; + if (!halbtc8821c2ant_power_save_state(btc, ps_type, 0x50, 0x4)) result = TRUE; - } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c2ant_set_fw_pstdma == Native LPS (byte1 = 0x%x)\n", byte1); + "[BTCoex], %s == Native LPS (byte1 = 0x%x)\n", + __func__, byte1); BTC_TRACE(trace_buf); - halbtc8821c2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, - 0x0, - 0x0); + ps_type = BTC_PS_WIFI_NATIVE; + halbtc8821c2ant_power_save_state(btc, ps_type, 0x0, 0x0); } coex_sta->is_set_ps_state_fail = result; @@ -1681,501 +2045,394 @@ void halbtc8821c2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, coex_dm->ps_tdma_para[3] = byte4; coex_dm->ps_tdma_para[4] = real_byte5; - btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); + btc->btc_fill_h2c(btc, 0x60, 5, h2c_parameter); } else { coex_sta->cnt_set_ps_state_fail++; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], halbtc8821c2ant_set_fw_pstdma == Force Leave LPS Fail (cnt = %d)\n", - coex_sta->cnt_set_ps_state_fail); + "[BTCoex], %s == Force Leave LPS Fail (cnt = %d)\n", + __func__, coex_sta->cnt_set_ps_state_fail); BTC_TRACE(trace_buf); } + + if (ps_type == BTC_PS_WIFI_NATIVE) + btc->btc_set(btc, BTC_SET_ACT_POST_NORMAL_LPS, NULL); } -void halbtc8821c2ant_ps_tdma(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN boolean turn_on, IN u8 type) +static +void halbtc8821c2ant_tdma(struct btc_coexist *btc, + boolean force_exec, boolean turn_on, u8 type) { - static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + static u8 tdma_byte4_modify, pre_tdma_byte4_modify; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; - coex_dm->cur_ps_tdma_on = turn_on; - coex_dm->cur_ps_tdma = type; + btc->btc_set_atomic(btc, &coex_dm->setting_tdma, TRUE); /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ - if (bt_link_info->slave_role) - psTdmaByte4Modify = 0x1; + if (bt_link_info->slave_role && bt_link_info->a2dp_exist) + tdma_byte4_modify = 0x1; else - psTdmaByte4Modify = 0x0; + tdma_byte4_modify = 0x0; - if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { + if (pre_tdma_byte4_modify != tdma_byte4_modify) { force_exec = TRUE; - pre_psTdmaByte4Modify = psTdmaByte4Modify; + pre_tdma_byte4_modify = tdma_byte4_modify; } if (!force_exec) { - if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && - (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) { + if (turn_on == coex_dm->cur_ps_tdma_on && + type == coex_dm->cur_ps_tdma) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", + "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", (coex_dm->cur_ps_tdma_on ? "on" : "off"), coex_dm->cur_ps_tdma); BTC_TRACE(trace_buf); + + btc->btc_set_atomic(btc, &coex_dm->setting_tdma, FALSE); return; } } - if (coex_dm->cur_ps_tdma_on) { + if (turn_on) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ********** TDMA(on, %d) **********\n", - coex_dm->cur_ps_tdma); - BTC_TRACE(trace_buf); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** TDMA(off, %d) **********\n", - coex_dm->cur_ps_tdma); + type); BTC_TRACE(trace_buf); - } + /* enable TBTT nterrupt */ + btc->btc_write_1byte_bitmask(btc, 0x550, 0x8, 0x1); - if (turn_on) { switch (type) { case 1: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x91, - 0x54 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x91, + 0x50 | tdma_byte4_modify); break; case 2: default: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, - 0x11 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11, + 0x11 | tdma_byte4_modify); break; case 3: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x30, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x30, 0x3, 0x91, + 0x10 | tdma_byte4_modify); break; case 4: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x21, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x21, 0x3, 0x91, + 0x10 | tdma_byte4_modify); break; case 5: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x25, 0x3, 0x91, + 0x10 | tdma_byte4_modify); break; case 6: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x3, 0x91, + 0x10 | tdma_byte4_modify); break; case 7: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x3, 0x91, - 0x10 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x20, 0x3, 0x91, + 0x10 | tdma_byte4_modify); break; case 8: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x15, 0x03, 0x11, - 0x11); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x15, 0x03, 0x11, + 0x11); break; case 10: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x30, 0x03, 0x11, - 0x10); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x30, 0x03, 0x11, + 0x10); break; case 11: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, - 0x10 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11, + 0x10 | tdma_byte4_modify); break; case 12: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, 0x11); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11, + 0x11); break; case 13: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x1c, 0x03, 0x11, - 0x10 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x1c, 0x03, 0x11, + 0x10 | tdma_byte4_modify); break; case 14: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x20, 0x03, 0x11, - 0x11); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x20, 0x03, 0x11, + 0x11); break; case 15: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x11, - 0x14); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x11, + 0x10); break; case 16: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x11, - 0x15); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x11, + 0x11); + break; + case 17: + halbtc8821c2ant_set_tdma(btc, 0x61, 0x08, 0x03, 0x11, + 0x14 | tdma_byte4_modify); break; case 21: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x30, 0x03, 0x11, - 0x10); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x30, 0x03, 0x11, + 0x10); break; case 22: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, - 0x10); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x25, 0x03, 0x11, + 0x10); break; case 23: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x11, - 0x10); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x11, + 0x10); + break; + case 25: + halbtc8821c2ant_set_tdma(btc, 0x51, 0x3a, 0x3, 0x11, + 0x50); break; case 51: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x10, 0x03, 0x91, - 0x10 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x10, 0x03, 0x91, + 0x10 | tdma_byte4_modify); break; case 101: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x10, 0x03, 0x10, - 0x54 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10, + 0x54 | tdma_byte4_modify); break; case 102: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x35, 0x03, 0x11, - 0x11 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x35, 0x03, 0x11, + 0x11 | tdma_byte4_modify); break; case 103: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x51, 0x30, 0x3, 0x10, + 0x50 | tdma_byte4_modify); break; case 104: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x21, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x51, 0x21, 0x3, 0x10, + 0x50 | tdma_byte4_modify); break; case 105: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x51, 0x45, 0x3, 0x10, + 0x50); break; case 106: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x10, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x51, 0x1a, 0x3, 0x10, + 0x50 | tdma_byte4_modify); break; case 107: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x10, 0x7, 0x10, - 0x54 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x51, 0x08, 0x7, 0x10, + 0x54); break; case 108: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x3, 0x10, - 0x50 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x51, 0x30, 0x3, 0x10, + 0x50 | tdma_byte4_modify); break; case 109: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x10, 0x03, 0x10, - 0x54 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10, + 0x54 | tdma_byte4_modify); break; case 110: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x30, 0x03, 0x10, - 0x50 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x51, 0x30, 0x03, 0x10, + 0x50); break; case 111: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, - 0x25, 0x03, 0x11, - 0x11 | psTdmaByte4Modify); + halbtc8821c2ant_set_tdma(btc, 0x61, 0x25, 0x03, 0x11, + 0x11); break; - case 151: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, - 0x10, 0x03, 0x10, - 0x50 | psTdmaByte4Modify); + case 112: + halbtc8821c2ant_set_tdma(btc, 0x51, 0x4a, 0x3, 0x10, + 0x50); break; - } - } else { - /* disable PS tdma */ - switch (type) { - case 0: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); + case 113: + halbtc8821c2ant_set_tdma(btc, 0x61, 0x48, 0x03, 0x11, + 0x10); break; - case 1: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x48, 0x0); + case 115: + halbtc8821c2ant_set_tdma(btc, 0x51, 0x30, 0x03, 0x10, + 0x50); break; - default: - halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, - 0x0, 0x0, 0x40, 0x0); + case 116: /* Not use */ + halbtc8821c2ant_set_tdma(btc, 0x51, 0x08, 0x03, 0x10, + 0x54 | tdma_byte4_modify); + break; + case 117: /* Not use */ + halbtc8821c2ant_set_tdma(btc, 0x61, 0x08, 0x03, 0x10, + 0x10 | tdma_byte4_modify); + break; + case 119: + halbtc8821c2ant_set_tdma(btc, 0x61, 0x08, 0x03, 0x10, + 0x14 | tdma_byte4_modify); + break; + case 151: + halbtc8821c2ant_set_tdma(btc, 0x51, 0x10, 0x03, 0x10, + 0x50 | tdma_byte4_modify); break; } - } - - if (!coex_sta->is_set_ps_state_fail) { - /* update pre state */ - coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; - coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; - } -} - -void halbtc8821c2ant_set_int_block(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 pos_type) -{ -#if 0 - u8 regval_0xcba; - u32 u32tmp1 = 0; - - coex_dm->cur_int_block_status = pos_type; - - if (!force_exec) { - if (coex_dm->pre_int_block_status == - coex_dm->cur_int_block_status) - return; - } - - coex_dm->pre_int_block_status = coex_dm->cur_int_block_status; - - regval_0xcba = btcoexist->btc_read_1byte(btcoexist, 0xcba); - - switch (pos_type) { - - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG: - regval_0xcba = (regval_0xcba | BIT(0)) & (~(BIT( - 2))); /* 0xcb8[16] = 1, 0xcb8[18] = 0, WL_G select BTG */ - regval_0xcba = regval_0xcba & 0x0f; - - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x5); */ /* Gain Table */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x2); */ /* CCK Gain Table */ - - break; - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG: - regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( - 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ - - /* regval_0xcba = regval_0xcba | BIT(4) | BIT(5) ; */ /* 0xcb8[21:20] = 2b'11, WL_G @ WLAG on */ - /* regval_0xcba = (regval_0xcba | BIT(6)) & (~(BIT(7)) ) ; */ /* 0xcb8[23:22] = 2b'01, WL_A @ WLAG off */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc1d, 0x0f, 0x0); */ /* Gain Table */ - /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0xa9e, 0x0f, 0x6); */ /* CCK Gain Table */ - - break; - case BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG: - regval_0xcba = regval_0xcba & (~(BIT(2) | BIT( - 0))); /* 0xcb8[16] = 0, 0xcb8[18] = 0, WL_G select WLAG */ - /*regval_0xcba = (regval_0xcba | BIT(4)) & (~(BIT(5))); */ /* 0xcb8[21:20] = 2b'01, WL_G @ WLAG off */ - /*regval_0xcba = regval_0xcba | BIT(6) | BIT(7); */ /* 0xcb8[23:22] = 2b'11, WL_A @ WLAG on */ - - break; - } - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcba, 0xff, - regval_0xcba); - - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb8); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Int Block setup) 0xcb8 = 0x%08x **********\n", - u32tmp1); - BTC_TRACE(trace_buf); - -#endif -} - -void halbtc8821c2ant_set_ext_band_switch(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 pos_type) -{ - -#if 0 - boolean switch_polatiry_inverse = FALSE; - u8 regval_0xcb6; - u32 u32tmp1 = 0, u32tmp2 = 0; - - if (!rfe_type->ext_band_switch_exist) - return; - - coex_dm->cur_ext_band_switch_status = pos_type; - - if (!force_exec) { - if (coex_dm->pre_ext_band_switch_status == - coex_dm->cur_ext_band_switch_status) - return; - } - - coex_dm->pre_ext_band_switch_status = - coex_dm->cur_ext_band_switch_status; - - /* swap control polarity if use different switch control polarity*/ - switch_polatiry_inverse = (rfe_type->ext_band_switch_ctrl_polarity == 1 - ? ~switch_polatiry_inverse : switch_polatiry_inverse); - - /*swap control polarity for WL_A, default polarity 0xcb4[21] = 0 && 0xcb4[23] = 1 is for WL_G */ - switch_polatiry_inverse = (pos_type == - BT_8821C_2ANT_EXT_BAND_SWITCH_TO_WLA ? ~switch_polatiry_inverse - : switch_polatiry_inverse); - - regval_0xcb6 = btcoexist->btc_read_1byte(btcoexist, 0xcb6); - - /* for normal switch polrity, 0xcb4[21] =1 && 0xcb4[23] = 0 for WL_A, vice versa */ - regval_0xcb6 = (switch_polatiry_inverse == 1 ? ((regval_0xcb6 & (~(BIT( - 7)))) | BIT(5)) : ((regval_0xcb6 & (~(BIT(5)))) | BIT(7))); - - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb6, 0xff, - regval_0xcb6); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + type); + BTC_TRACE(trace_buf); - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb0); - u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + /* disable PS tdma */ + switch (type) { + case 0: + halbtc8821c2ant_set_tdma(btc, 0x0, 0x0, 0x0, 0x40, 0x0); + break; + case 1: + halbtc8821c2ant_set_tdma(btc, 0x0, 0x0, 0x0, 0x48, 0x0); + break; + default: + halbtc8821c2ant_set_tdma(btc, 0x0, 0x0, 0x0, 0x40, 0x0); + break; + } + } - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (After Ext Band switch setup) 0xcb0 = 0x%08x, 0xcb4 = 0x%08x**********\n", - u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif + if (!coex_sta->is_set_ps_state_fail) { + /* update pre state */ + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + } + btc->btc_set_atomic(btc, &coex_dm->setting_tdma, FALSE); } -void halbtc8821c2ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, - IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) +static +void halbtc8821c2ant_set_ant_switch(struct btc_coexist *btc, + boolean force_exec, u8 ctrl_type, + u8 pos_type) { - struct btc_board_info *board_info = &btcoexist->board_info; - boolean switch_polatiry_inverse = FALSE; - u8 regval_0xcb7 = 0, regval_0x64; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + struct rfe_type_8821c_2ant *rfe_type = &btc->rfe_type_8821c_2ant; + struct btc_board_info *board_info = &btc->board_info; + boolean polarity_inverse = FALSE; + u8 regval = 0; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; if (!rfe_type->ext_ant_switch_exist) return; - coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; - if (!force_exec) { - if (coex_dm->pre_ext_ant_switch_status == - coex_dm->cur_ext_ant_switch_status) + if (((ctrl_type << 8) + pos_type) == + coex_dm->cur_ext_ant_switch_status) return; } - coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; + coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; - /* swap control polarity if use different switch control polarity*/ - /* Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */ - /* Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG, 0xcb4[29:28] = 2b'10 => Ant to WLG */ + /* swap control polarity if use different switch control polarity + * Normal switch polarity for DPDT, + * 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, + * 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main + * Normal switch polarity for SPDT, + * 0xcb4[29:28] = 2b'01 => Ant to BTG, + * 0xcb4[29:28] = 2b'10 => Ant to WLG + */ if (rfe_type->ext_ant_switch_ctrl_polarity) - switch_polatiry_inverse = ~switch_polatiry_inverse; + polarity_inverse = !polarity_inverse; /* swap control polarity if 1-Ant at Aux */ if (rfe_type->ant_at_main_port == FALSE) - switch_polatiry_inverse = ~switch_polatiry_inverse; + polarity_inverse = !polarity_inverse; switch (pos_type) { default: - case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT: - case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE: - case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA: + case BT_8821C_2ANT_TO_BT: + case BT_8821C_2ANT_TO_NOCARE: + case BT_8821C_2ANT_TO_WLA: break; - case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG: - if (!rfe_type->wlg_Locate_at_btg) - switch_polatiry_inverse = ~switch_polatiry_inverse; + case BT_8821C_2ANT_TO_WLG: + if (!rfe_type->wlg_locate_at_btg) + polarity_inverse = !polarity_inverse; break; } if (board_info->ant_div_cfg) - ctrl_type = BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; + ctrl_type = BT_8821C_2ANT_CTRL_BY_ANTDIV; switch (ctrl_type) { default: - case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x77); /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ - - regval_0xcb7 = (switch_polatiry_inverse == FALSE ? - 0x1 : 0x2); /* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, regval_0xcb7); - + case BT_8821C_2ANT_CTRL_BY_BBSW: + /* 0x4c[23] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0); + /* 0x4c[24] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1); + /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x77); + /* 0xcb4[29:28] = 2b'01 for no switch_polarity_inverse, + * DPDT_SEL_N =1, DPDT_SEL_P =0 + */ + regval = (!polarity_inverse ? 0x1 : 0x2); + btc->btc_write_1byte_bitmask(btc, 0xcb7, 0x30, regval); break; - case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x66); /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ - - regval_0xcb7 = (switch_polatiry_inverse == FALSE ? - 0x2 : 0x1); /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, - 0x30, regval_0xcb7); - + case BT_8821C_2ANT_CTRL_BY_PTA: + /* 0x4c[23] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0); + /* 0x4c[24] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1); + /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x66); + /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, + * DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1 + */ + regval = (!polarity_inverse ? 0x2 : 0x1); + btc->btc_write_1byte_bitmask(btc, 0xcb7, 0x30, regval); break; - case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x1); /* 0x4c[24] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, - 0xff, 0x88); /* */ - - /* no regval_0xcb7 setup required, because antenna switch control value by antenna diversity */ - + case BT_8821C_2ANT_CTRL_BY_ANTDIV: + /* 0x4c[23] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0); + /* 0x4c[24] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1); + btc->btc_write_1byte_bitmask(btc, 0xcb4, 0xff, 0x88); + + /* no regval_0xcb7 setup required, because antenna switch + * control value by antenna diversity + */ break; - case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x1); /* 0x4c[23] = 1 */ - - regval_0x64 = (switch_polatiry_inverse == FALSE ? 0x0 : - 0x1); /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, - regval_0x64); + case BT_8821C_2ANT_CTRL_BY_MAC: + /* 0x4c[23] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x1); + /* 0x64[0] = 1b'0 for no switch_polarity_inverse, + * DPDT_SEL_N =1, DPDT_SEL_P =0 + */ + regval = (!polarity_inverse ? 0x0 : 0x1); + btc->btc_write_1byte_bitmask(btc, 0x64, 0x1, regval); break; - case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT: - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, - 0x80, 0x0); /* 0x4c[23] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, - 0x01, 0x0); /* 0x4c[24] = 0 */ - - /* no setup required, because antenna switch control value by BT vendor 0x1c[1:0] */ + case BT_8821C_2ANT_CTRL_BY_FW: + /* 0x4c[23] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0); + /* 0x4c[24] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x1); + break; + case BT_8821C_2ANT_CTRL_BY_BT: + /* 0x4c[23] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4e, 0x80, 0x0); + /* 0x4c[24] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x4f, 0x01, 0x0); + /* no setup required, because antenna switch control value + * by BT vendor 0xac[1:0] + */ break; } - /* PAPE, LNA_ON control by BT while WLAN off for current leakage issue */ - if (ctrl_type == BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT) { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x0); /* PAPE 0x64[29] = 0 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, - 0x0); /* LNA_ON 0x64[28] = 0 */ + /* PAPE, LNA_ON control by BT while WLAN off + * for current leakage issue + */ + if (ctrl_type == BT_8821C_2ANT_CTRL_BY_BT) { + /* PAPE 0x64[29] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x67, 0x20, 0x0); + /* LNA_ON 0x64[28] = 0 */ + btc->btc_write_1byte_bitmask(btc, 0x67, 0x10, 0x0); } else { - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, - 0x1); /* PAPE 0x64[29] = 1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, - 0x1); /* LNA_ON 0x64[28] = 1 */ + /* PAPE 0x64[29] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x67, 0x20, 0x1); + /* LNA_ON 0x64[28] = 1 */ + btc->btc_write_1byte_bitmask(btc, 0x67, 0x10, 0x1); } - -#if BT_8821C_2ANT_COEX_DBG - - u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", - u32tmp1, u32tmp2, u32tmp3); - BTC_TRACE(trace_buf); -#endif - } -void halbtc8821c2ant_set_rfe_type(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_set_rfe_type(struct btc_coexist *btc) { - struct btc_board_info *board_info = &btcoexist->board_info; - + struct rfe_type_8821c_2ant *rfe_type = &btc->rfe_type_8821c_2ant; + struct btc_board_info *board_info = &btc->board_info; /* the following setup should be got from Efuse in the future */ rfe_type->rfe_module_type = board_info->rfe_type & 0x1f; @@ -2184,186 +2441,143 @@ void halbtc8821c2ant_set_rfe_type(IN struct btc_coexist *btcoexist) switch (rfe_type->rfe_module_type) { case 0: - default: + case 8: + default: /*2-Ant, DPDT, WLG*/ rfe_type->ext_ant_switch_exist = TRUE; - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*2-Ant, DPDT, WLG*/ - rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_DPDT; + rfe_type->wlg_locate_at_btg = FALSE; rfe_type->ant_at_main_port = TRUE; break; case 1: + case 9: /*1-Ant, Main, WLG */ rfe_type->ext_ant_switch_exist = TRUE; - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, WLG */ - rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_SPDT; + rfe_type->wlg_locate_at_btg = FALSE; rfe_type->ant_at_main_port = TRUE; break; case 2: + case 10: /*1-Ant, Main, BTG */ rfe_type->ext_ant_switch_exist = TRUE; - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, BTG */ - rfe_type->wlg_Locate_at_btg = TRUE; + rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_SPDT; + rfe_type->wlg_locate_at_btg = TRUE; rfe_type->ant_at_main_port = TRUE; break; case 3: + case 11: /*1-Ant, Aux, WLG */ rfe_type->ext_ant_switch_exist = TRUE; - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, WLG */ - rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_DPDT; + rfe_type->wlg_locate_at_btg = FALSE; rfe_type->ant_at_main_port = FALSE; break; case 4: + case 12: /*1-Ant, Aux, BTG */ rfe_type->ext_ant_switch_exist = TRUE; - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, BTG */ - rfe_type->wlg_Locate_at_btg = TRUE; + rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_DPDT; + rfe_type->wlg_locate_at_btg = TRUE; rfe_type->ant_at_main_port = FALSE; break; case 5: - rfe_type->ext_ant_switch_exist = FALSE; /*2-Ant, no switch, WLG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_NONE; - rfe_type->wlg_Locate_at_btg = FALSE; + case 13: /*2-Ant, no switch, WLG*/ + rfe_type->ext_ant_switch_exist = FALSE; + rfe_type->ext_ant_switch_type = BT_8821C_2ANT_SWITCH_NONE; + rfe_type->wlg_locate_at_btg = FALSE; rfe_type->ant_at_main_port = TRUE; break; case 6: - rfe_type->ext_ant_switch_exist = FALSE; /*2-Ant, no switch, WLG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_NONE; - rfe_type->wlg_Locate_at_btg = FALSE; + case 14: /*2-Ant, no antenna switch, WLG*/ + rfe_type->ext_ant_switch_exist = FALSE; + rfe_type->ext_ant_switch_type = BT_8821C_2ANT_SWITCH_NONE; + rfe_type->wlg_locate_at_btg = FALSE; rfe_type->ant_at_main_port = TRUE; break; case 7: - rfe_type->ext_ant_switch_exist = TRUE; /*2-Ant, DPDT, BTG*/ - rfe_type->ext_ant_switch_type = - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; - rfe_type->wlg_Locate_at_btg = TRUE; + case 15: /*2-Ant, DPDT, BTG*/ + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = BT_8821C_2ANT_USE_DPDT; + rfe_type->wlg_locate_at_btg = TRUE; rfe_type->ant_at_main_port = TRUE; break; } - -#if 0 - if (rfe_type->wlg_Locate_at_btg) - halbtc8821c2ant_set_int_block(btcoexist, FORCE_EXEC, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); - else - halbtc8821c2ant_set_int_block(btcoexist, FORCE_EXEC, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); -#endif - } - -void halbtc8821c2ant_set_ant_path(IN struct btc_coexist *btcoexist, - IN u8 ant_pos_type, IN boolean force_exec, - IN u8 phase) +static +void halbtc8821c2ant_set_ant_path(struct btc_coexist *btc, + u8 ant_pos_type, boolean force_exec, + u8 phase) { - struct btc_board_info *board_info = &btcoexist->board_info; - u32 cnt_bt_cal_chk = 0; - boolean is_in_mp_mode = FALSE; - u8 u8tmp = 0; - u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; - u16 u16tmp1 = 0; - - u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0x38); - - /* To avoid indirect access fail */ - if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { - force_exec = TRUE; - coex_sta->gnt_error_cnt++; - } - - -#if BT_8821C_2ANT_COEX_DBG - - u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0x54); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", - u32tmp3, u8tmp, u32tmp1, u32tmp2); - BTC_TRACE(trace_buf); -#endif - - coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + struct btc_board_info *board_info = &btc->board_info; + u32 cnt_bt_cal_chk = 0, u32tmp1 = 0, u32tmp2 = 0; + u8 u8tmp = 0, ctrl_type, pos_type; if (!force_exec) { - if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) + if (coex_dm->cur_ant_pos_type == ((ant_pos_type << 8) + phase)) return; } - coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; + coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; + if (btc->dbg_mode) { + u32tmp1 = btc->btc_read_4byte(btc, 0xcbc); + u32tmp2 = btc->btc_read_4byte(btc, 0xcb4); + u8tmp = btc->btc_read_1byte(btc, 0x73); - switch (phase) { - case BT_8821C_2ANT_PHASE_COEX_POWERON: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0xcbc = 0x%x, 0x73 = 0x%x\n", + u32tmp1, u32tmp2, u8tmp); + BTC_TRACE(trace_buf); + } + switch (phase) { + case BT_8821C_2ANT_PHASE_POWERON: /* set Path control owner to WL at initial step */ - halbtc8821c2ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8821C_2ANT_PCO_BTSIDE); - - /* set GNT_BT to SW high */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - /* Set GNT_WL to SW high */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_BTSIDE); - if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (ant_pos_type == BTC_ANT_PATH_AUTO) { if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; + ant_pos_type = BTC_ANT_WIFI_AT_MAIN; else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; + ant_pos_type = BTC_ANT_WIFI_AT_AUX; } coex_sta->run_time_state = FALSE; - break; - case BT_8821C_2ANT_PHASE_COEX_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c2ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_2ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c2ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_2ANT_CTT_BT_VS_LTE, - 0xffff); - - - /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ + case BT_8821C_2ANT_PHASE_INIT: + /* Disable LTE Coex Function in WiFi side + * (this should be on if LTE coex is required) + */ + halbtc8821c2ant_ltecoex_enable(btc, 0x0); + + /* GNT_WL_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8821c2ant_ltecoex_table(btc, BT_8821C_2ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8821c2ant_ltecoex_table(btc, BT_8821C_2ANT_CTT_BT_VS_LTE, + 0xffff); + + /* Wait If BT IQK running, because Path control owner + * is at BT during BT IQK (setup by WiFi firmware) + */ while (cnt_bt_cal_chk <= 20) { - u8tmp = btcoexist->btc_read_1byte( - btcoexist, 0x49c); + u8tmp = btc->btc_read_1byte(btc, 0x49c); cnt_bt_cal_chk++; if (u8tmp & BIT(1)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is calibrating (wait cnt=%d)\n", cnt_bt_cal_chk); BTC_TRACE(trace_buf); - delay_ms(50); + delay_ms(10); } else { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)\n", cnt_bt_cal_chk); BTC_TRACE(trace_buf); break; @@ -2371,122 +2585,98 @@ void halbtc8821c2ant_set_ant_path(IN struct btc_coexist *btcoexist, } /* set Path control owner to WL at initial step */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); + halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE); /* set GNT_BT to SW high */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_2ANT_GNT_SET_TO_HIGH); /* Set GNT_WL to SW high */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_2ANT_GNT_SET_TO_HIGH); coex_sta->run_time_state = FALSE; - if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (ant_pos_type == BTC_ANT_PATH_AUTO) { if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; + ant_pos_type = BTC_ANT_WIFI_AT_MAIN; else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; + ant_pos_type = BTC_ANT_WIFI_AT_AUX; } - break; - case BT_8821C_2ANT_PHASE_WLANONLY_INIT: - /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ - halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); - - /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c2ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_2ANT_CTT_WL_VS_LTE, - 0xffff); - - /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ - halbtc8821c2ant_ltecoex_set_coex_table( - btcoexist, - BT_8821C_2ANT_CTT_BT_VS_LTE, - 0xffff); + case BT_8821C_2ANT_PHASE_WONLY: + /* Disable LTE Coex Function in WiFi side + * (this should be on if LTE coex is required) + */ + halbtc8821c2ant_ltecoex_enable(btc, 0x0); + + /* GNT_WL_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8821c2ant_ltecoex_table(btc, BT_8821C_2ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 + * (this should be config if LTE coex is required) + */ + halbtc8821c2ant_ltecoex_table(btc, BT_8821C_2ANT_CTT_BT_VS_LTE, + 0xffff); /* set Path control owner to WL at initial step */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); + halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE); /* set GNT_BT to SW Low */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_LOW); + BT_8821C_2ANT_GNT_SET_TO_LOW); /* Set GNT_WL to SW high */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_2ANT_GNT_SET_TO_HIGH); coex_sta->run_time_state = FALSE; - if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (ant_pos_type == BTC_ANT_PATH_AUTO) { if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; + ant_pos_type = BTC_ANT_WIFI_AT_MAIN; else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; + ant_pos_type = BTC_ANT_WIFI_AT_AUX; } break; - case BT_8821C_2ANT_PHASE_WLAN_OFF: + case BT_8821C_2ANT_PHASE_WOFF: /* Disable LTE Coex Function in WiFi side */ - halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); + halbtc8821c2ant_ltecoex_enable(btc, 0x0); /* set Path control owner to BT */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_BTSIDE); + halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_BTSIDE); - /* Set Ext Ant Switch to BT control at wifi off step */ - halbtc8821c2ant_set_ext_ant_switch(btcoexist, - FORCE_EXEC, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE); coex_sta->run_time_state = FALSE; break; - case BT_8821C_2ANT_PHASE_2G_RUNTIME: - case BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT: - + case BT_8821C_2ANT_PHASE_2G: while (cnt_bt_cal_chk <= 20) { /* 0x49c[0]=1 WL IQK, 0x49c[1]=1 BT IQK*/ - u8tmp = btcoexist->btc_read_1byte(btcoexist, - 0x49c); + u8tmp = btc->btc_read_1byte(btc, 0x49c); cnt_bt_cal_chk++; if (u8tmp & BIT(0)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### WL is IQK (wait cnt=%d)\n", + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ########### WL is IQK (wait cnt=%d)\n", cnt_bt_cal_chk); BTC_TRACE(trace_buf); - delay_ms(50); + delay_ms(10); } else if (u8tmp & BIT(1)) { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ########### BT is IQK (wait cnt=%d)\n", + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is IQK (wait cnt=%d)\n", cnt_bt_cal_chk); BTC_TRACE(trace_buf); - delay_ms(50); + delay_ms(10); } else { - BTC_SPRINTF(trace_buf, - BT_TMP_BUF_SIZE, - "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", cnt_bt_cal_chk); BTC_TRACE(trace_buf); break; @@ -2494,1972 +2684,1664 @@ void halbtc8821c2ant_set_ant_path(IN struct btc_coexist *btcoexist, } /* set Path control owner to WL at runtime step */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); - - if (phase == - BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT) { - /* set GNT_BT to PTA */ - halbtc8821c2ant_ltecoex_set_gnt_bt( - btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_2ANT_SIG_STA_SET_BY_HW); - - /* Set GNT_WL to SW High */ - halbtc8821c2ant_ltecoex_set_gnt_wl( - btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); - } else { - /* set GNT_BT to PTA */ - halbtc8821c2ant_ltecoex_set_gnt_bt( - btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_2ANT_SIG_STA_SET_BY_HW); - - /* Set GNT_WL to PTA */ - halbtc8821c2ant_ltecoex_set_gnt_wl( - btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_2ANT_SIG_STA_SET_BY_HW); - } - coex_sta->run_time_state = TRUE; + halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE); - if (rfe_type->wlg_Locate_at_btg) - halbtc8821c2ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); - else - halbtc8821c2ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); + /* set GNT_BT to PTA */ + halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_2ANT_GNT_SET_BY_HW); - if (BTC_ANT_PATH_AUTO == ant_pos_type) { + /* Set GNT_WL to PTA */ + halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_2ANT_GNT_SET_BY_HW); + + coex_sta->run_time_state = TRUE; + + if (ant_pos_type == BTC_ANT_PATH_AUTO) { if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; + ant_pos_type = BTC_ANT_WIFI_AT_MAIN; else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; + ant_pos_type = BTC_ANT_WIFI_AT_AUX; } break; - case BT_8821C_2ANT_PHASE_5G_RUNTIME: - + case BT_8821C_2ANT_PHASE_5G: /* set Path control owner to WL at runtime step */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); + halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE); /* set GNT_BT to SW Hi */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, - BT_8821C_2ANT_SIG_STA_SET_BY_HW); + BT_8821C_2ANT_GNT_SET_BY_HW); /* Set GNT_WL to SW Hi */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_2ANT_GNT_SET_TO_HIGH); coex_sta->run_time_state = TRUE; - halbtc8821c2ant_set_int_block(btcoexist, - NORMAL_EXEC, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG); - - - if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (ant_pos_type == BTC_ANT_PATH_AUTO) { if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; + ant_pos_type = BTC_ANT_WIFI_AT_MAIN; else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; + ant_pos_type = BTC_ANT_WIFI_AT_AUX; } - break; - case BT_8821C_2ANT_PHASE_BTMPMODE: + case BT_8821C_2ANT_PHASE_BTMP: /* Disable LTE Coex Function in WiFi side */ - halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); + halbtc8821c2ant_ltecoex_enable(btc, 0x0); /* set Path control owner to WL */ - halbtc8821c2ant_ltecoex_pathcontrol_owner( - btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); + halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE); /* set GNT_BT to SW Hi */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_2ANT_GNT_SET_TO_HIGH); /* Set GNT_WL to SW Lo */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_LOW); + BT_8821C_2ANT_GNT_SET_TO_LOW); coex_sta->run_time_state = FALSE; - if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (ant_pos_type == BTC_ANT_PATH_AUTO) { if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; + ant_pos_type = BTC_ANT_WIFI_AT_MAIN; else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; + ant_pos_type = BTC_ANT_WIFI_AT_AUX; } break; - case BT_8821C_2ANT_PHASE_ANTENNA_DET: - halbtc8821c2ant_ltecoex_pathcontrol_owner(btcoexist, - BT_8821C_2ANT_PCO_WLSIDE); + case BT_8821C_2ANT_PHASE_ANTDET: + halbtc8821c2ant_coex_ctrl_owner(btc, BT_8821C_2ANT_PCO_WLSIDE); /* set GNT_BT to high */ - halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + halbtc8821c2ant_set_gnt_bt(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_2ANT_GNT_SET_TO_HIGH); /* Set GNT_WL to high */ - halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, - BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + halbtc8821c2ant_set_gnt_wl(btc, BT_8821C_2ANT_GNT_BLOCK_RFC_BB, BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + BT_8821C_2ANT_GNT_SET_TO_HIGH); - if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (ant_pos_type == BTC_ANT_PATH_AUTO) { if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) - ant_pos_type = - BTC_ANT_WIFI_AT_MAIN; + ant_pos_type = BTC_ANT_WIFI_AT_MAIN; else - ant_pos_type = - BTC_ANT_WIFI_AT_AUX; + ant_pos_type = BTC_ANT_WIFI_AT_AUX; } coex_sta->run_time_state = FALSE; - break; } - if (phase != BT_8821C_2ANT_PHASE_WLAN_OFF) { + if (phase != BT_8821C_2ANT_PHASE_WOFF) { + /* Set Ext Ant Switch to BT control at wifi off step */ + ctrl_type = BT_8821C_2ANT_CTRL_BY_BT; + pos_type = BT_8821C_2ANT_TO_NOCARE; + } else { switch (ant_pos_type) { default: - case BTC_ANT_WIFI_AT_MAIN - : - halbtc8821c2ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG); + case BTC_ANT_WIFI_AT_MAIN: + ctrl_type = BT_8821C_2ANT_CTRL_BY_BBSW; + pos_type = BT_8821C_2ANT_TO_WLG; break; - case BTC_ANT_WIFI_AT_AUX - : - halbtc8821c2ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT); + case BTC_ANT_WIFI_AT_AUX: + ctrl_type = BT_8821C_2ANT_CTRL_BY_BBSW; + pos_type = BT_8821C_2ANT_TO_BT; break; - case BTC_ANT_WIFI_AT_DIVERSITY - : - halbtc8821c2ant_set_ext_ant_switch( - btcoexist, - force_exec, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE); + case BTC_ANT_WIFI_AT_DIVERSITY: + ctrl_type = BT_8821C_2ANT_CTRL_BY_ANTDIV; + pos_type = BT_8821C_2ANT_TO_NOCARE; break; } - - } - - - -#if BT_8821C_2ANT_COEX_DBG - u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", - phase, u32tmp3, u8tmp, u32tmp1, u32tmp2); - - BTC_TRACE(trace_buf); -#endif - -} - - -u8 halbtc8821c2ant_action_algorithm(IN struct btc_coexist *btcoexist) -{ - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean bt_hs_on = FALSE; - u8 algorithm = BT_8821C_2ANT_COEX_ALGO_UNDEFINED; - u8 num_of_diff_profile = 0; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (!bt_link_info->bt_link_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No BT link exists!!!\n"); - BTC_TRACE(trace_buf); - return algorithm; } - if (bt_link_info->sco_exist) - num_of_diff_profile++; - if (bt_link_info->hid_exist) - num_of_diff_profile++; - if (bt_link_info->pan_exist) - num_of_diff_profile++; - if (bt_link_info->a2dp_exist) - num_of_diff_profile++; + halbtc8821c2ant_set_ant_switch(btc, force_exec, ctrl_type, pos_type); - if (num_of_diff_profile == 0) { + if (btc->dbg_mode) { + u32tmp1 = btc->btc_read_4byte(btc, 0xcbc); + u32tmp2 = btc->btc_read_4byte(btc, 0xcb4); + u8tmp = btc->btc_read_1byte(btc, 0x73); - if (bt_link_info->acl_busy) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], No-Profile busy\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY; - } - } else if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP Sink\n"); + "[BTCoex], (After Ant Setup) 0xcb4 = 0x%x, 0xcbc = 0x%x, 0x73 = 0x%x\n", + u32tmp1, u32tmp2, u8tmp); BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_A2DPSINK; - } else if (num_of_diff_profile == 1) { - if (bt_link_info->sco_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; - } else { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_HID; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP only\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(HS) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], PAN(EDR) only\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR; - } - } - } - } else if (num_of_diff_profile == 2) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; - } else if (bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP ==> A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_A2DP; - } else if (bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_HID_A2DP; - } - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } - } else if (num_of_diff_profile == 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->a2dp_exist) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n"); - BTC_TRACE(trace_buf); - algorithm = BT_8821C_2ANT_COEX_ALGO_HID_A2DP; - } else if (bt_link_info->hid_exist && - bt_link_info->pan_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; - } - } else if (bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; - } - } - } else { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], HID + A2DP + PAN(EDR)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } - } else if (num_of_diff_profile >= 3) { - if (bt_link_info->sco_exist) { - if (bt_link_info->hid_exist && - bt_link_info->pan_exist && - bt_link_info->a2dp_exist) { - if (bt_hs_on) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); - BTC_TRACE(trace_buf); - algorithm = - BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; - } - } - } } - - return algorithm; -} - - - -void halbtc8821c2ant_action_coex_all_off(IN struct btc_coexist *btcoexist) -{ - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* fw all off */ - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - -} - -void halbtc8821c2ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) -{ - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); } -void halbtc8821c2ant_action_bt_hs(IN struct btc_coexist *btcoexist) +static +u8 halbtc8821c2ant_action_algorithm(struct btc_coexist *btc) { - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = FALSE, wifi_turbo = FALSE; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = TRUE; -#endif - - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + u8 algorithm = BT_8821C_2ANT_COEX_UNDEFINED; + u8 profile_map = 0; - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = FALSE; - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + if (bt_link_info->sco_exist) + profile_map = profile_map | BIT(0); - coex_dm->is_switch_to_1dot5_ant = FALSE; + if (bt_link_info->hid_exist) + profile_map = profile_map | BIT(1); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + if (bt_link_info->a2dp_exist) + profile_map = profile_map | BIT(2); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + if (bt_link_info->pan_exist) + profile_map = profile_map | BIT(3); + switch (profile_map) { + default: + case 0: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_UNDEFINED; + break; + case 1: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_SCO; + break; + case 2: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_HID; + break; + case 3: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_HID; + break; + case 4: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_A2DP; + break; + case 5: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP ==> HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_HID_A2DP; + break; + case 6: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_HID_A2DP; + break; + case 7: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_HID_A2DP; + break; + case 8: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_PAN; + break; + case 9: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(EDR) ==> HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_PAN_HID; + break; + case 10: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_PAN_HID; + break; + case 11: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(EDR) ==> HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_PAN_HID; + break; + case 12: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_PAN_A2DP; + break; + case 13: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_PAN_A2DP; + break; + case 14: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_PAN_A2DP; + break; + case 15: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR) ==> A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_PAN_A2DP; + break; + } - } else { + return algorithm; +} - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - coex_dm->is_switch_to_1dot5_ant = TRUE; +static +void halbtc8821c2ant_action_coex_all_off(struct btc_coexist *btc) +{ + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); +} - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - } +static +void halbtc8821c2ant_action_bt_whql_test(struct btc_coexist *btc) +{ + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } - -void halbtc8821c2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_bt_inquiry(struct btc_coexist *btc) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + boolean wifi_connected = FALSE, wifi_busy = FALSE; - boolean wifi_connected = FALSE; - boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE; - boolean wifi_busy = FALSE; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + halbtc8821c2ant_set_wl_tx_power(btc, FC_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + if (coex_sta->is_wifi_linkscan_process || + coex_sta->wifi_high_pri_task1 || + coex_sta->wifi_high_pri_task2) { - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + if (coex_sta->bt_create_connection) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt page + wifi hi-pri task\n"); + BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + halbtc8821c2ant_table(btc, NM_EXCU, 8); - if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) - || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { + if (bt_link_info->a2dp_exist && + !bt_link_info->pan_exist) + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 17); + else if (coex_sta->wifi_high_pri_task1) + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 113); + else + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 21); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt inquiry + wifi hi-pri task\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_table(btc, NM_EXCU, 8); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 21); + } + } else if (wifi_busy) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); + "[BTCoex], bt inq/page + wifi busy\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, - 8); - - if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 15); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 11); - } else if ((!wifi_connected) && (!wifi_scan)) { - + halbtc8821c2ant_table(btc, NM_EXCU, 8); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 23); + } else if (wifi_connected) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Wifi no-link + no-scan + BT Inq/Page!!\n"); + "[BTCoex], bt inq/page + wifi connected\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - } else if (bt_link_info->pan_exist) { - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8821c2ant_table(btc, NM_EXCU, 8); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 23); } else { - - if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) - || (coex_sta->wifi_is_high_pri_task)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 23); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt inq/page + wifi not-connected\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); } - -void halbtc8821c2ant_action_bt_relink(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_bt_relink(struct btc_coexist *btc) { - if (coex_sta->is_bt_multi_link == TRUE) - return; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + if ((!coex_sta->is_bt_multi_link && !bt_link_info->pan_exist) || + (bt_link_info->a2dp_exist && bt_link_info->hid_exist)) { + halbtc8821c2ant_table(btc, NM_EXCU, 5); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + } } - -void halbtc8821c2ant_action_bt_idle(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_bt_idle(struct btc_coexist *btc) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + boolean wifi_busy = FALSE; - boolean wifi_busy = FALSE; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); if (!wifi_busy) { - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 14); + halbtc8821c2ant_table(btc, NM_EXCU, 8); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 14); } else { /* if wl busy */ - - if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + if ((coex_sta->bt_ble_scan_type & 0x2) && + BT_8821C_2ANT_BSTATUS_NCON_IDLE == coex_dm->bt_status) { - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 14); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 12); } else { - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 8); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 12); + halbtc8821c2ant_table(btc, NM_EXCU, 8); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 12); } } - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - + halbtc8821c2ant_set_wl_tx_power(btc, FC_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); } - -/* SCO only or SCO+PAN(HS) */ -void halbtc8821c2ant_action_sco(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_bt_mr(struct btc_coexist *btc) { - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; + struct wifi_link_info_8821c_2ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_2ant; - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = FALSE; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); + if (!wifi_link_info_ext->is_all_under_5g) { + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_2ANT_PHASE_2G); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + } else { + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_2ANT_PHASE_5G); - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + } +} - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); +/* SCO only or SCO+PAN(HS) */ +static +void halbtc8821c2ant_action_sco(struct btc_coexist *btc) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + wifi_rssi_state = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { + bt_rssi_state = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; - if (coex_sta->is_eSCO_mode) - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); - else /* 2-Ant free run if SCO mode */ - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + if (coex_sta->is_bt_multi_link) { + halbtc8821c2ant_table(btc, NM_EXCU, 7); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 25); + } else { + if (coex_sta->is_esco_mode) + halbtc8821c2ant_table(btc, NM_EXCU, 1); + else /* 2-Ant free run if SCO mode */ + halbtc8821c2ant_table(btc, NM_EXCU, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 8); + } } - } - -void halbtc8821c2ant_action_hid(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_hid(struct btc_coexist *btc) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; + u8 wifi_rssi_state, bt_rssi_state; boolean wifi_busy = FALSE; u32 wifi_bw = 1; + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_U4_WIFI_BW, &wifi_bw); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); + wifi_rssi_state = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + bt_rssi_state = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; if (coex_sta->is_hid_low_pri_tx_overhead) { + halbtc8821c2ant_table(btc, NM_EXCU, 12); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 108); + } else if (coex_sta->is_hid_rcu) { + halbtc8821c2ant_table(btc, NM_EXCU, 12); - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 4); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 108); - } else if (wifi_bw == 0) { /* if 11bg mode */ - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 111); + if (wifi_busy) + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 113); + else + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 111); } else { - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 111); + halbtc8821c2ant_table(btc, NM_EXCU, 12); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 111); } } - } -void halbtc8821c2ant_action_a2dpsink(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_a2dpsink(struct btc_coexist *btc) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; + u8 wifi_rssi_state, bt_rssi_state; static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = FALSE, wifi_turbo = FALSE; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = TRUE; -#endif + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + boolean ap_enable = FALSE; - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); + btc->btc_get(btc, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); + wifi_rssi_state = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); + wifi_rssi_state2 = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); + bt_rssi_state = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + bt_rssi_state2 = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8821c2ant_table(btc, NM_EXCU, 4); if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 1); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 1); else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 16); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 16); } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = TRUE; - if ((coex_sta->bt_relink_downcount != 0) - && (wifi_busy)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - + if (ap_enable) { + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } else { - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 105); + halbtc8821c2ant_table(btc, NM_EXCU, 8); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 115); } - } - } - - /* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ -void halbtc8821c2ant_action_a2dp(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_a2dp(struct btc_coexist *btc) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; + u8 wifi_rssi_state, bt_rssi_state; static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = FALSE, wifi_turbo = FALSE; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + u8 wifi_rssi_state2, bt_rssi_state2; + static u8 prewifi_rssi_state3 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state3 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state3, bt_rssi_state3; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); + boolean wifi_busy = FALSE; + u8 iot_peer = BTC_IOT_PEER_UNKNOWN; + + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = TRUE; + wifi_rssi_state = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); + wifi_rssi_state2 = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); + wifi_rssi_state3 = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state3, 2, + 45, 0); - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); + bt_rssi_state = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); + bt_rssi_state2 = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + bt_rssi_state3 = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state3, 2, + 50, 0); if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8821c2ant_table(btc, NM_EXCU, 4); if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 1); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 1); else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 16); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 16); } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - coex_dm->is_switch_to_1dot5_ant = TRUE; + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); - if ((coex_sta->bt_relink_downcount != 0) - && (wifi_busy)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - - } else { + halbtc8821c2ant_table(btc, NM_EXCU, 8); - if (wifi_turbo) - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - else - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 7); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 101); - } + if (BTC_RSSI_HIGH(wifi_rssi_state3)) + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 119); + else + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 101); } - } -void halbtc8821c2ant_action_pan_edr(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_pan(struct btc_coexist *btc) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; + u8 wifi_rssi_state, bt_rssi_state; static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = FALSE, wifi_turbo = FALSE; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + static u8 prewifi_rssi_state3 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state3 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state3, bt_rssi_state3; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = TRUE; -#endif + wifi_rssi_state = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); + wifi_rssi_state2 = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); + wifi_rssi_state3 = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state3, 2, + 58, 0); - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); + bt_rssi_state = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); + bt_rssi_state2 = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + bt_rssi_state3 = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state3, 2, + 47, 0); #if 0 - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 8); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 21); #endif - #if 1 if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8821c2ant_table(btc, NM_EXCU, 4); if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 3); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 3); else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 4); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 4); } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = TRUE; - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); + /* for Lenovo CPT_For_WiFi OPP test */ + if (btc->board_info.customer_id == RT_CID_LENOVO_CHINA && + BTC_RSSI_HIGH(wifi_rssi_state3) && wifi_busy) { + halbtc8821c2ant_table(btc, NM_EXCU, 7); - if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 103); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 104); - } + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 103); + } else { + halbtc8821c2ant_table(btc, NM_EXCU, 7); + if (wifi_busy) + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 103); + else + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 104); + } + } #endif - } -void halbtc8821c2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_hid_a2dp(struct btc_coexist *btc) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; + u8 wifi_rssi_state, bt_rssi_state; static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = FALSE; - u32 wifi_bw = 1; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - + u8 wifi_rssi_state2, bt_rssi_state2; + static u8 prewifi_rssi_state3 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state3; + boolean wifi_busy = FALSE; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); + wifi_rssi_state = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); + wifi_rssi_state2 = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); + wifi_rssi_state3 = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state3, 2, + 45, 0); - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); + bt_rssi_state = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + bt_rssi_state2 = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8821c2ant_table(btc, NM_EXCU, 4); if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 1); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 1); else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 16); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 16); } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = TRUE; - if ((coex_sta->bt_relink_downcount != 0) - && (wifi_busy)) { - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); - BTC_TRACE(trace_buf); + halbtc8821c2ant_table(btc, NM_EXCU, 12); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); - } else { - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 8); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 109); - } + if (BTC_RSSI_HIGH(wifi_rssi_state3)) + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 119); + else + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 109); } - } - -void halbtc8821c2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_a2dp_pan_hs(struct btc_coexist *btc) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; + u8 wifi_rssi_state, bt_rssi_state; static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = FALSE, wifi_turbo = FALSE; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - -#if 1 - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = TRUE; -#endif - + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); + wifi_rssi_state = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); + wifi_rssi_state2 = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); + bt_rssi_state = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + bt_rssi_state2 = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8821c2ant_table(btc, NM_EXCU, 4); if (wifi_busy) { if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 7); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 7); else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 5); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 5); } else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 6); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 6); } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = TRUE; - if (wifi_turbo) - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 6); - else - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 7); - + halbtc8821c2ant_table(btc, NM_EXCU, 8); if (wifi_busy) { - if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 107); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 107); else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 105); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 105); } else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 106); - + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 106); } - } - - /* PAN(EDR)+A2DP */ -void halbtc8821c2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_pan_a2dp(struct btc_coexist *btc) { - static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; - - static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; - static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; - boolean wifi_busy = FALSE, wifi_turbo = FALSE; - - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", - coex_sta->scan_ap_num, coex_sta->wl_noisy_level); - BTC_TRACE(trace_buf); - - if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) - wifi_turbo = TRUE; - - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); - - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + static u8 prewifi_rssi_state3 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state3 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state3, bt_rssi_state3; - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); - - if (BTC_RSSI_HIGH(wifi_rssi_state) && - BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + boolean wifi_busy = FALSE; + u8 iot_peer = BTC_IOT_PEER_UNKNOWN; - coex_dm->is_switch_to_1dot5_ant = FALSE; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && - BTC_RSSI_HIGH(bt_rssi_state2)) { + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btc->btc_get(btc, BTC_GET_U1_IOT_PEER, &iot_peer); - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + if (!wifi_busy) + wifi_busy = coex_sta->gl_wifi_busy; - coex_dm->is_switch_to_1dot5_ant = FALSE; + wifi_rssi_state3 = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state3, 2, + 42, 0); + bt_rssi_state3 = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state3, 2, + 45, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); - if (wifi_busy) { + coex_dm->is_switch_to_1dot5_ant = TRUE; - if (((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) || - (!coex_sta->is_A2DP_3M)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 7); - else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 5); - } else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 6); + /* for Lenovo coex test case */ + if (btc->board_info.customer_id == RT_CID_LENOVO_CHINA && + coex_sta->scan_ap_num <= 10 && + iot_peer == BTC_IOT_PEER_ATHEROS) { + /* for CPT_for_WiFi */ + if (BTC_RSSI_LOW(wifi_rssi_state3)) { + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 20); + if (wifi_busy) { + halbtc8821c2ant_table(btc, NM_EXCU, 7); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 105); + } else { + halbtc8821c2ant_table(btc, NM_EXCU, 7); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 107); + } + } else { /* for CPT_for_BT */ + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 8); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 107); + } } else { + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 8); - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - coex_dm->is_switch_to_1dot5_ant = TRUE; - - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, - 8); if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 107); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 107); else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 106); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 106); } - } -void halbtc8821c2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_pan_hid(struct btc_coexist *btc) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; + u8 wifi_rssi_state, bt_rssi_state; static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; + u8 wifi_rssi_state2, bt_rssi_state2; boolean wifi_busy = FALSE; - u32 wifi_bw = 1; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + wifi_rssi_state = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); + wifi_rssi_state2 = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); - - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); - - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); + bt_rssi_state = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + bt_rssi_state2 = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8821c2ant_table(btc, NM_EXCU, 4); if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 3); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 3); else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 4); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 4); } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = TRUE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8821c2ant_table(btc, NM_EXCU, 6); if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 103); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 103); else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 104); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 104); } - } /* HID+A2DP+PAN(EDR) */ -void halbtc8821c2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_hid_a2dp_pan(struct btc_coexist *btc) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state, bt_rssi_state; + u8 wifi_rssi_state, bt_rssi_state; static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; - u8 wifi_rssi_state2, bt_rssi_state2; + u8 wifi_rssi_state2, bt_rssi_state2; boolean wifi_busy = FALSE; - u32 wifi_bw = 1; - - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, - &wifi_bw); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state, 2, - coex_sta->wifi_coex_thres, 0); + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); - wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, - &prewifi_rssi_state2, 2, - coex_sta->wifi_coex_thres2, 0); + wifi_rssi_state = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); - bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state, 2, - coex_sta->bt_coex_thres, 0); + wifi_rssi_state2 = + halbtc8821c2ant_wifi_rssi_state(btc, &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); - bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, - &pre_bt_rssi_state2, 2, - coex_sta->bt_coex_thres2, 0); + bt_rssi_state = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + bt_rssi_state2 = + halbtc8821c2ant_bt_rssi_state(btc, &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); if (BTC_RSSI_HIGH(wifi_rssi_state) && BTC_RSSI_HIGH(bt_rssi_state)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && BTC_RSSI_HIGH(bt_rssi_state2)) { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xc8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 2); coex_dm->is_switch_to_1dot5_ant = FALSE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + halbtc8821c2ant_table(btc, NM_EXCU, 4); if (wifi_busy) { - - if (((coex_sta->a2dp_bit_pool > 40) && - (coex_sta->a2dp_bit_pool < 255)) || - (!coex_sta->is_A2DP_3M)) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 7); + if ((coex_sta->a2dp_bit_pool > 40 && + coex_sta->a2dp_bit_pool < 255) || + !coex_sta->is_A2DP_3M) + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 7); else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, - TRUE, 5); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 5); } else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 6); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 6); } else { - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_dm->is_switch_to_1dot5_ant = TRUE; - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8821c2ant_table(btc, NM_EXCU, 12); if (wifi_busy) - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 107); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 107); else - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, - 106); - } + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 106); } +} - -void halbtc8821c2ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_wifi_under5g(struct btc_coexist *btc) { + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_2ANT_PHASE_5G); /* fw all off */ - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, - BT_8821C_2ANT_PHASE_5G_RUNTIME); + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } -void halbtc8821c2ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_wifi_native_lps(struct btc_coexist *btc) { - halbtc8821c2ant_coex_table_with_type(btcoexist, - NORMAL_EXEC, 2); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 2); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } -void halbtc8821c2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) -{ - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); - - /* hw all off */ - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); -} -void halbtc8821c2ant_action_wifi_linkscan_process(IN struct btc_coexist - *btcoexist) +static +void halbtc8821c2ant_action_wifi_linkscan(struct btc_coexist *btc) { - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, FC_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - if (bt_link_info->pan_exist) { - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - - } else if (bt_link_info->a2dp_exist) { - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - } else { - - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); - - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); - } + halbtc8821c2ant_table(btc, NM_EXCU, 8); + if (bt_link_info->pan_exist) + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 22); + else if (bt_link_info->a2dp_exist) + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 16); + else + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 21); } -void halbtc8821c2ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_wifi_not_connected(struct btc_coexist *btc) { - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); - /* fw all off */ - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); } -void halbtc8821c2ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_action_wifi_connected(struct btc_coexist *btc) { - switch (coex_dm->cur_algorithm) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + u8 algorithm = 0; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + + algorithm = halbtc8821c2ant_action_algorithm(btc); + + switch (algorithm) { - case BT_8821C_2ANT_COEX_ALGO_SCO: + case BT_8821C_2ANT_COEX_SCO: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_sco(btcoexist); + halbtc8821c2ant_action_sco(btc); break; - case BT_8821C_2ANT_COEX_ALGO_HID: + case BT_8821C_2ANT_COEX_HID: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action 2-Ant, algorithm = HID.\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_hid(btcoexist); + halbtc8821c2ant_action_hid(btc); break; - case BT_8821C_2ANT_COEX_ALGO_A2DP: + case BT_8821C_2ANT_COEX_A2DP: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_a2dp(btcoexist); + + /* for A2DP + OPP test but BTinfo is + * A2DP only in Lenovo test case + */ + if (coex_sta->is_bt_multi_link && coex_sta->hid_pair_cnt == 0) + halbtc8821c2ant_action_pan_a2dp(btc); + else + halbtc8821c2ant_action_a2dp(btc); break; - case BT_8821C_2ANT_COEX_ALGO_A2DPSINK: + case BT_8821C_2ANT_COEX_A2DPSINK: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action 2-Ant, algorithm = A2DP Sink.\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_a2dpsink(btcoexist); + halbtc8821c2ant_action_a2dpsink(btc); break; - case BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS: + case BT_8821C_2ANT_COEX_A2DP_PANHS: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); + "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_a2dp_pan_hs(btcoexist); + halbtc8821c2ant_action_a2dp_pan_hs(btc); break; - case BT_8821C_2ANT_COEX_ALGO_PANEDR: + case BT_8821C_2ANT_COEX_PAN: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_pan_edr(btcoexist); + halbtc8821c2ant_action_pan(btc); break; - case BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP: + case BT_8821C_2ANT_COEX_PAN_A2DP: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_pan_edr_a2dp(btcoexist); + halbtc8821c2ant_action_pan_a2dp(btc); break; - case BT_8821C_2ANT_COEX_ALGO_PANEDR_HID: + case BT_8821C_2ANT_COEX_PAN_HID: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_pan_edr_hid(btcoexist); + halbtc8821c2ant_action_pan_hid(btc); break; - case BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + case BT_8821C_2ANT_COEX_HID_A2DP_PAN: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_hid_a2dp_pan_edr( - btcoexist); + halbtc8821c2ant_action_hid_a2dp_pan(btc); break; - case BT_8821C_2ANT_COEX_ALGO_HID_A2DP: + case BT_8821C_2ANT_COEX_HID_A2DP: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_hid_a2dp(btcoexist); + halbtc8821c2ant_action_hid_a2dp(btc); break; - case BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY: + case BT_8821C_2ANT_COEX_NOPROFILEBUSY: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n"); + "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_bt_idle(btcoexist); + halbtc8821c2ant_action_bt_idle(btc); break; default: BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); + "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_coex_all_off(btcoexist); + halbtc8821c2ant_action_coex_all_off(btc); break; } - coex_dm->pre_algorithm = coex_dm->cur_algorithm; + coex_dm->cur_algorithm = algorithm; +} + +static +void halbtc8821c2ant_action_wifi_multiport25g(struct btc_coexist *btc) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); + + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_BTCQDDR, TRUE); + + if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport25g(), BT Relink!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + } else if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport25g(), BT Inq-Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_table(btc, NM_EXCU, 11); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport25g(), BT idle or busy!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_table(btc, NM_EXCU, 11); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + } } +static +void halbtc8821c2ant_action_wifi_multiport2g(struct btc_coexist *btc) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + struct btc_multi_port_tdma_info multiport_tdma_para; + u32 traffic_dir; + + btc->btc_get(btc, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &traffic_dir); + + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); + + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_BTCQDDR, TRUE); + + if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, BT Relink!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + } else if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, BT Inq-Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + } else if (coex_sta->num_of_profile == 0) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, BT idle!!\n"); + BTC_TRACE(trace_buf); + + /* for P2P-GO only A2DP sink */ + if (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO && + traffic_dir == BTC_WIFI_TRAFFIC_RX) { + halbtc8821c2ant_table(btc, NM_EXCU, 15); + halbtc8821c2ant_tdma(btc, NM_EXCU, TRUE, 11); + } else { + halbtc8821c2ant_table(btc, NM_EXCU, 5); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + } + } else if (coex_sta->is_wifi_linkscan_process) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, WL scan!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_linkscan(btc); + } else { + if (!coex_sta->is_bt_multi_link && + (bt_link_info->sco_exist || bt_link_info->hid_exist || + coex_sta->is_hid_rcu)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, 2G multi-port + BT HID/HFP/RCU!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_table(btc, NM_EXCU, 5); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + } else { + switch (btc->wifi_link_info.link_mode) { + #if 0 + case BTC_LINK_2G_SCC_GO_STA: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, 2G_SCC_GO_STA + BT busy!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + break; + case BTC_LINK_ONLY_GO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_singleport2g, Only_P2PGO with client-join + BT busy!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + break; + #endif + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi_multiport2g, Other multi-port + BT busy!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_table(btc, NM_EXCU, 0); + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + break; + } + } + } +} -void halbtc8821c2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_run_coex(struct btc_coexist *btc, u8 reason) { - u8 algorithm = 0; - u32 num_of_wifi_link = 0; - u32 wifi_link_status = 0; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - boolean miracast_plus_bt = FALSE; - boolean scan = FALSE, link = FALSE, roam = FALSE, - under_4way = FALSE, - wifi_connected = FALSE, wifi_under_5g = - FALSE, - bt_hs_on = FALSE; - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + struct wifi_link_info_8821c_2ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_2ant; + boolean wifi_connected = FALSE, wifi_32k = FALSE; + boolean scan = FALSE, link = FALSE, roam = FALSE, under_4way = FALSE; + + btc->btc_get(btc, BTC_GET_BL_WIFI_SCAN, &scan); + btc->btc_get(btc, BTC_GET_BL_WIFI_LINK, &link); + btc->btc_get(btc, BTC_GET_BL_WIFI_ROAM, &roam); + btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way); + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + btc->btc_get(btc, BTC_GET_BL_WIFI_LW_PWR_STATE, &wifi_32k); + + if (scan || link || roam || under_4way || + reason == BT_8821C_2ANT_RSN_2GSCANSTART || + reason == BT_8821C_2ANT_RSN_2GSWITCHBAND || + reason == BT_8821C_2ANT_RSN_2GCONSTART || + reason == BT_8821C_2ANT_RSN_2GSPECIALPKT) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + coex_sta->is_wifi_linkscan_process = TRUE; + } else { + coex_sta->is_wifi_linkscan_process = FALSE; + } + + /* update wifi_link_info_ext variable */ + halbtc8821c2ant_update_wifi_link_info(btc, reason); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism()===>\n"); + "[BTCoex], RunCoexistMechanism()===> reason = %d\n", + reason); BTC_TRACE(trace_buf); - if (btcoexist->manual_control) { + if (btc->manual_control) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); BTC_TRACE(trace_buf); return; } - if (btcoexist->stop_coex_dm) { + if (btc->stop_coex_dm) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); BTC_TRACE(trace_buf); return; } if (coex_sta->under_ips) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under IPS !!!\n"); + "[BTCoex], RunCoexistMechanism(), return for wifi is under IPS !!!\n"); BTC_TRACE(trace_buf); return; } - if ((coex_sta->under_lps) && - (coex_dm->bt_status != BT_8821C_2ANT_BT_STATUS_ACL_BUSY)) { + if (coex_sta->under_lps && wifi_32k) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); + "[BTCoex], RunCoexistMechanism(), return for wifi is under LPS-32K !!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_wifi_native_lps(btcoexist); return; } if (!coex_sta->run_time_state) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], return for run_time_state = FALSE !!!\n"); + "[BTCoex], return for run_time_state = FALSE !!!\n"); BTC_TRACE(trace_buf); return; } - if (coex_sta->freeze_coexrun_by_btinfo) { + if (coex_sta->freeze_coexrun_by_btinfo && !coex_sta->is_setup_link) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); + "[BTCoex], return for freeze_coexrun_by_btinfo\n"); BTC_TRACE(trace_buf); return; } - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + coex_sta->coex_run_cnt++; + + if (coex_sta->msft_mr_exist && wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), microsoft MR!!\n"); + BTC_TRACE(trace_buf); - if ((wifi_under_5g) && - (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G) && - (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G_NOFORSCAN)) { + coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_BTMR; + halbtc8821c2ant_action_bt_mr(btc); + return; + } + if (wifi_link_info_ext->is_all_under_5g) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], WiFi is under 5G!!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_wifi_under5g(btcoexist); + + coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_5G; + halbtc8821c2ant_action_wifi_under5g(btc); return; - } else { + } + if (wifi_link_info_ext->is_mcc_25g) { /* not iclude scan action */ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 2G!!!\n"); + "[BTCoex], WiFi is under mcc dual-band!!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - NORMAL_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); + + coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_25GMPORT; + halbtc8821c2ant_action_wifi_multiport25g(btc); + return; } - if (coex_sta->bt_whck_test) { + if (wifi_link_info_ext->num_of_active_port > 1 || + (btc->wifi_link_info.link_mode == BTC_LINK_ONLY_GO && + !btc->wifi_link_info.bhotspot && + btc->wifi_link_info.bany_client_join_go)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under WHCK TEST!!!\n"); + "[BTCoex], WiFi is under scc-2g/mcc-2g/p2pGO-only!!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_bt_whql_test(btcoexist); + + if (btc->wifi_link_info.link_mode == + BTC_LINK_ONLY_GO) + coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_2GGO; + else + coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_2GMPORT; + halbtc8821c2ant_action_wifi_multiport2g(btc); return; } + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is single-port 2G!!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->wl_coex_mode = BT_8821C_2ANT_WLINK_2G1PORT; + + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, NM_EXCU, + BT_8821C_2ANT_PHASE_2G); + + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_BTCQDDR, TRUE); + if (coex_sta->bt_disabled) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is disabled!!!\n"); + "[BTCoex], BT is disabled !!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_coex_all_off(btcoexist); + halbtc8821c2ant_action_coex_all_off(btc); return; } - if (coex_sta->c2h_bt_inquiry_page) { + if (coex_sta->under_lps && !coex_sta->force_lps_ctrl && + !coex_sta->acl_busy) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is under inquiry/page scan !!\n"); + "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_bt_inquiry(btcoexist); + halbtc8821c2ant_action_wifi_native_lps(btc); return; } - if (coex_sta->is_setupLink) { + if (coex_sta->bt_whck_test) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT is re-link !!!\n"); + "[BTCoex], BT is under WHCK TEST!!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_bt_relink(btcoexist); + halbtc8821c2ant_action_bt_whql_test(btc); return; } - /* for P2P */ - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, - &wifi_link_status); - num_of_wifi_link = wifi_link_status >> 16; - - if ((num_of_wifi_link >= 2) || - (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + if (coex_sta->is_setup_link || coex_sta->bt_relink_downcount != 0) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", - num_of_wifi_link, wifi_link_status); + "[BTCoex], BT is re-link !!!\n"); BTC_TRACE(trace_buf); - - if (bt_link_info->bt_link_exist) - miracast_plus_bt = TRUE; - else - miracast_plus_bt = FALSE; - - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); - - if (scan || link || roam || under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", - scan, link, roam, under_4way); - BTC_TRACE(trace_buf); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_wifi_linkscan_process(btcoexist); - } else - halbtc8821c2ant_action_wifi_multi_port(btcoexist); - + halbtc8821c2ant_action_bt_relink(btc); return; - } else { - miracast_plus_bt = FALSE; - btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, - &miracast_plus_bt); } - - btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); - - if (bt_hs_on) { + if (coex_sta->c2h_bt_inquiry_page) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "############# [BTCoex], BT Is hs\n"); + "[BTCoex], BT is under inquiry/page scan !!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_bt_hs(btcoexist); + halbtc8821c2ant_action_bt_inquiry(btc); return; } - if ((BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) || - (BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE == - coex_dm->bt_status)) { - + if (coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_NCON_IDLE || + coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_CON_IDLE) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, bt idle!!.\n"); + "############# [BTCoex], BT Is idle\n"); BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_bt_idle(btcoexist); + halbtc8821c2ant_action_bt_idle(btc); return; } - algorithm = halbtc8821c2ant_action_algorithm(btcoexist); - coex_dm->cur_algorithm = algorithm; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", - coex_dm->cur_algorithm); - BTC_TRACE(trace_buf); - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - if (scan || link || roam || under_4way) { + if (coex_sta->is_wifi_linkscan_process) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under Link Process !!\n"); + "[BTCoex], wifi is under linkscan process!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_wifi_linkscan_process(btcoexist); - } else if (wifi_connected) { + halbtc8821c2ant_action_wifi_linkscan(btc); + return; + } + if (wifi_connected) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, wifi connected!!.\n"); + "[BTCoex], wifi is under connected!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_wifi_connected(btcoexist); + halbtc8821c2ant_action_wifi_connected(btc); } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Action 2-Ant, wifi not-connected!!.\n"); + "[BTCoex], wifi is under not-connected!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_wifi_not_connected(btcoexist); + + halbtc8821c2ant_action_wifi_not_connected(btc); } } -void halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +static +void halbtc8821c2ant_init_coex_dm(struct btc_coexist *btc) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Coex Mechanism Init!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); + halbtc8821c2ant_low_penalty_ra(btc, NM_EXCU, FALSE, 0); - halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); - - /* fw all off */ - halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); - - halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); - halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_set_wl_tx_power(btc, NM_EXCU, 0xd8); + halbtc8821c2ant_set_bt_tx_power(btc, NM_EXCU, 0); coex_sta->pop_event_cnt = 0; - coex_sta->cnt_RemoteNameReq = 0; - coex_sta->cnt_ReInit = 0; - coex_sta->cnt_setupLink = 0; - coex_sta->cnt_IgnWlanAct = 0; - coex_sta->cnt_Page = 0; - coex_sta->cnt_RoleSwitch = 0; + coex_sta->cnt_remote_name_req = 0; + coex_sta->cnt_reinit = 0; + coex_sta->cnt_setup_link = 0; + coex_sta->cnt_ign_wlan_act = 0; + coex_sta->cnt_page = 0; + coex_sta->cnt_role_switch = 0; coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; + coex_dm->setting_tdma = FALSE; - halbtc8821c2ant_query_bt_info(btcoexist); -} + halbtc8821c2ant_table(btc, NM_EXCU, 0); + /* fw all off */ + halbtc8821c2ant_tdma(btc, NM_EXCU, FALSE, 0); + + halbtc8821c2ant_query_bt_info(btc); +} -void halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) +static +void halbtc8821c2ant_init_hw_config(struct btc_coexist *btc, boolean wifi_only) { - u8 u8tmp = 0; - u32 vendor; - u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + u8 u8tmp = 0; + u32 vendor; + u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; u8 i; - - u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u32tmp3 = btc->btc_read_4byte(btc, 0xcb4); + u32tmp1 = halbtc8821c2ant_read_indirect_reg(btc, 0x38); + u32tmp2 = halbtc8821c2ant_read_indirect_reg(btc, 0x54); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + "[BTCoex], (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", u32tmp3, u32tmp1, u32tmp2); BTC_TRACE(trace_buf);; @@ -4467,12 +4349,14 @@ void halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, "[BTCoex], 2Ant Init HW Config!!\n"); BTC_TRACE(trace_buf); +#if 0 coex_sta->bt_coex_supported_feature = 0; coex_sta->bt_coex_supported_version = 0; coex_sta->bt_ble_scan_type = 0; coex_sta->bt_ble_scan_para[0] = 0; coex_sta->bt_ble_scan_para[1] = 0; coex_sta->bt_ble_scan_para[2] = 0; +#endif coex_sta->bt_reg_vendor_ac = 0xffff; coex_sta->bt_reg_vendor_ae = 0xffff; coex_sta->isolation_btween_wb = BT_8821C_2ANT_DEFAULT_ISOLATION; @@ -4480,213 +4364,203 @@ void halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, coex_sta->bt_relink_downcount = 0; coex_sta->is_set_ps_state_fail = FALSE; coex_sta->cnt_set_ps_state_fail = 0; + coex_sta->wl_rx_rate = BTC_UNKNOWN; + coex_sta->coex_run_cnt = 0; for (i = 0; i <= 9; i++) coex_sta->bt_afh_map[i] = 0; /* 0xf0[15:12] --> Chip Cut information */ - coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, - 0xf1) & 0xf0) >> 4; + coex_sta->cut_version = (btc->btc_read_1byte(btc, 0xf1) & 0xf0) >> 4; coex_sta->dis_ver_info_cnt = 0; - halbtc8821c2ant_coex_switch_threshold(btcoexist, - coex_sta->isolation_btween_wb); +#if 0 /* HW antenna diversity for test */ + halbtc8821c2ant_set_antdiv_hwsw(btc, NM_EXCU, TRUE); +#endif - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, - 0x1); /* enable TBTT nterrupt */ + halbtc8821c2ant_coex_switch_thres(btc, coex_sta->isolation_btween_wb); + /* enable TBTT nterrupt */ + btc->btc_write_1byte_bitmask(btc, 0x550, 0x8, 0x1); /* BT report packet sample rate */ - btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); + btc->btc_write_1byte(btc, 0x790, 0x5); /* Init 0x778 = 0x1 for 2-Ant */ - btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + btc->btc_write_1byte(btc, 0x778, 0x1); /* Enable PTA (3-wire function form BT side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); + btc->btc_write_1byte_bitmask(btc, 0x40, 0x20, 0x1); + btc->btc_write_1byte_bitmask(btc, 0x41, 0x02, 0x1); /* Enable PTA (tx/rx signal form WiFi side) */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); + btc->btc_write_1byte_bitmask(btc, 0x4c6, 0x10, 0x1); /* set GNT_BT=1 for coex table select both */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); + btc->btc_write_1byte_bitmask(btc, 0x763, 0x10, 0x1); - halbtc8821c2ant_enable_gnt_to_gpio(btcoexist, TRUE); + halbtc8821c2ant_enable_gnt_to_gpio(btc, TRUE); #if 0 /* check if WL firmware download ok */ - /*if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)*/ - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ONOFF, TRUE); + /*if (btc->btc_read_1byte(btc, 0x80) == 0xc6)*/ + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ONOFF, TRUE); #endif /* Enable counter statistics */ - btcoexist->btc_write_1byte(btcoexist, 0x76e, - 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ + /* 0x76e[3] =1, WLAN_Act control by PTA */ + btc->btc_write_1byte(btc, 0x76e, 0x4); /* WLAN_Tx by GNT_WL 0x950[29] = 0 */ - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0); */ - - halbtc8821c2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); - - halbtc8821c2ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); - - psd_scan->ant_det_is_ant_det_available = TRUE; + /* btc->btc_write_1byte_bitmask(btc, 0x953, 0x20, 0x0); */ if (coex_sta->is_rf_state_off) { + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_2ANT_PHASE_WOFF); - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_WLAN_OFF); - - btcoexist->stop_coex_dm = TRUE; - + btc->stop_coex_dm = TRUE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** halbtc8821c2ant_init_hw_config (RF Off)**********\n"); + "[BTCoex], ********** %s (RF Off)\n", __func__); BTC_TRACE(trace_buf); } else if (wifi_only) { coex_sta->concurrent_rx_mode_on = FALSE; /* Path config */ /* Set Antenna Path */ - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_WLANONLY_INIT); - - btcoexist->stop_coex_dm = TRUE; + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_2ANT_PHASE_WONLY); + btc->stop_coex_dm = TRUE; } else { - /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ - btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); + /* Set BT polluted packet on for Tx rate adaptive not + * including Tx retry break by PTA, 0x45c[19] =1 + */ + btc->btc_write_1byte_bitmask(btc, 0x45e, 0x8, 0x1); coex_sta->concurrent_rx_mode_on = TRUE; - /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */ + /* btc->btc_write_1byte_bitmask(btc, 0x953, 0x2, 0x1); */ - /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx, mask Tx only */ - btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0); + /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 + * for con-current Rx, mask Tx only + */ + btc->btc_set_rf_reg(btc, BTC_RF_A, 0x1, 0x2, 0x0); /* Set Antenna Path */ - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_COEX_INIT); + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_2ANT_PHASE_INIT); - btcoexist->stop_coex_dm = FALSE; + btc->stop_coex_dm = FALSE; } - - + halbtc8821c2ant_table(btc, FC_EXCU, 0); + halbtc8821c2ant_tdma(btc, FC_EXCU, FALSE, 0); } - - /* ************************************************************ * work around function start with wa_halbtc8821c2ant_ * ************************************************************ * ************************************************************ * extern function start with ex_halbtc8821c2ant_ * ************************************************************ */ -void ex_halbtc8821c2ant_power_on_setting(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c2ant_power_on_setting(struct btc_coexist *btc) { - struct btc_board_info *board_info = &btcoexist->board_info; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct btc_board_info *board_info = &btc->board_info; u8 u8tmp = 0x0; u16 u16tmp = 0x0; - u32 value = 0; - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "xxxxxxxxxxxxxxxx Execute 8821c 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); - BTC_TRACE(trace_buf); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "Ant Det Finish = %s, Ant Det Number = %d\n", - (board_info->btdm_ant_det_finish ? "Yes" : "No"), - board_info->btdm_ant_num_by_ant_det); + "[BTCoex], Execute %s !!\n", __func__); BTC_TRACE(trace_buf); - - btcoexist->stop_coex_dm = TRUE; + btc->stop_coex_dm = TRUE; coex_sta->is_rf_state_off = FALSE; - psd_scan->ant_det_is_ant_det_available = FALSE; - - /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ - u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); - btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + /* enable BB, REG_SYS_FUNC_EN such that + * we can write BB Register correctly. + */ + u16tmp = btc->btc_read_2byte(btc, 0x2); + btc->btc_write_2byte(btc, 0x2, u16tmp | BIT(0) | BIT(1)); - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + /* Local setting bit define + * BIT0: "0" for no antenna inverse; "1" for antenna inverse + * BIT1: "0" for internal switch; "1" for external switch + * BIT2: "0" for one antenna; "1" for two antenna + * NOTE: here default all internal switch and 1-antenna + * ==> BIT1=0 and BIT2=0 + */ /* Check efuse 0xc3[6] for Single Antenna Path */ if (board_info->single_ant_path == 0) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Single Antenna, Antenna at Aux Port\n"); + "[BTCoex], Single Antenna, Antenna at Aux Port\n"); BTC_TRACE(trace_buf); board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; - u8tmp = 7; } else if (board_info->single_ant_path == 1) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** Single Antenna, Antenna at Main Port\n"); + "[BTCoex], Single Antenna, Antenna at Main Port\n"); BTC_TRACE(trace_buf); board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; - u8tmp = 6; } BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d\n", + "[BTCoex], (Power On) single_ant_path = %d, btdm_ant_pos = %d\n", board_info->single_ant_path , board_info->btdm_ant_pos); BTC_TRACE(trace_buf); /* Setup RF front end type */ - halbtc8821c2ant_set_rfe_type(btcoexist); + halbtc8821c2ant_set_rfe_type(btc); /* Set Antenna Path to BT side */ - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_2ANT_PHASE_COEX_POWERON); - - /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */ - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_USB) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_2ANT_PHASE_POWERON); + + /* Save"single antenna position" info in Local register setting + * for FW reading, because FW may not ready at power on + */ + if (btc->chip_interface == BTC_INTF_PCI) + btc->btc_write_local_reg_1byte(btc, 0x3e0, u8tmp); + else if (btc->chip_interface == BTC_INTF_USB) + btc->btc_write_local_reg_1byte(btc, 0xfe08, u8tmp); + else if (btc->chip_interface == BTC_INTF_SDIO) + btc->btc_write_local_reg_1byte(btc, 0x60, u8tmp); /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ - halbtc8821c2ant_enable_gnt_to_gpio(btcoexist, TRUE); - - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n", - halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); - BTC_TRACE(trace_buf); + halbtc8821c2ant_enable_gnt_to_gpio(btc, TRUE); - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n", - btcoexist->btc_read_4byte(btcoexist, 0x70), - btcoexist->btc_read_4byte(btcoexist, 0xcb4)); - BTC_TRACE(trace_buf); + if (btc->dbg_mode) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LTE coex Reg 0x38 (Power-On) = 0x%x\n", + halbtc8821c2ant_read_indirect_reg(btc, 0x38)); + BTC_TRACE(trace_buf); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MACReg 0x70/ BBReg 0xcb4 (Power-On) = 0x%x/ 0x%x\n", + btc->btc_read_4byte(btc, 0x70), + btc->btc_read_4byte(btc, 0xcb4)); + BTC_TRACE(trace_buf); + } } -void ex_halbtc8821c2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c2ant_pre_load_firmware(struct btc_coexist *btc) { - struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_board_info *board_info = &btc->board_info; u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ - /* */ - /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ - /* Local setting bit define */ - /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ - /* BIT1: "0" for internal switch; "1" for external switch */ - /* BIT2: "0" for one antenna; "1" for two antenna */ - /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ - if (btcoexist->chip_interface == BTC_INTF_USB) { + /* S0 or S1 setting and Local register setting + *(By the setting fw can get ant number, S0/S1, ... info) + * Local setting bit define + * BIT0: "0" for no antenna inverse; "1" for antenna inverse + * BIT1: "0" for internal switch; "1" for external switch + * BIT2: "0" for one antenna; "1" for two antenna + * NOTE: here default all internal switch + * and 1-antenna ==> BIT1=0 and BIT2=0 + */ + if (btc->chip_interface == BTC_INTF_USB) { /* fixed at S0 for USB interface */ u8tmp |= 0x1; /* antenna inverse */ - btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + btc->btc_write_local_reg_1byte(btc, 0xfe08, u8tmp); } else { /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ if (board_info->single_ant_path == 0) { @@ -4695,140 +4569,230 @@ void ex_halbtc8821c2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) u8tmp |= 0x1; /* antenna inverse */ } - if (btcoexist->chip_interface == BTC_INTF_PCI) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, - u8tmp); - else if (btcoexist->chip_interface == BTC_INTF_SDIO) - btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, - u8tmp); + if (btc->chip_interface == BTC_INTF_PCI) + btc->btc_write_local_reg_1byte(btc, 0x3e0, u8tmp); + else if (btc->chip_interface == BTC_INTF_SDIO) + btc->btc_write_local_reg_1byte(btc, 0x60, u8tmp); } } -void ex_halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only) +void ex_halbtc8821c2ant_init_hw_config(struct btc_coexist *btc, + boolean wifi_only) { - halbtc8821c2ant_init_hw_config(btcoexist, wifi_only); + halbtc8821c2ant_init_hw_config(btc, wifi_only); } -void ex_halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c2ant_init_coex_dm(struct btc_coexist *btc) { - - halbtc8821c2ant_init_coex_dm(btcoexist); + btc->stop_coex_dm = FALSE; + btc->auto_report = TRUE; + btc->dbg_mode = FALSE; + halbtc8821c2ant_init_coex_dm(btc); } -void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c2ant_display_simple_coex_info(struct btc_coexist *btc) { - struct btc_board_info *board_info = &btcoexist->board_info; - struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; - - u8 *cli_buf = btcoexist->cli_buf; - u8 u8tmp[4], i, ps_tdma_case = 0; - u32 u32tmp[4]; - u16 u16tmp[4]; - u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck, ratio_ofdm; - u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; - static u8 pop_report_in_10s = 0; - u32 phyver = 0; - boolean lte_coex_on = FALSE; - static u8 cnt = 0; - u32 ratio_crc, cnt_ok, cnt_err; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + struct btc_board_info *board_info = &btc->board_info; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + + u8 *cli_buf = btc->cli_buf; + u32 bt_patch_ver = 0, bt_coex_ver = 0; + static u8 cnt; + u8 * const p = &coex_sta->bt_afh_map[0]; + + if (!coex_sta->bt_disabled && + (coex_sta->bt_coex_supported_version == 0 || + coex_sta->bt_coex_supported_version == 0xffff) && + cnt == 0) { + btc->btc_get(btc, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + btc->btc_get(btc, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + coex_sta->bt_reg_vendor_ac = (u16)(btc->btc_get_bt_reg(btc, 3, + 0xac) & + 0xffff); + + coex_sta->bt_reg_vendor_ae = (u16)(btc->btc_get_bt_reg(btc, 3, + 0xae) & + 0xffff); + + btc->btc_get(btc, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + btc->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) + btc->btc_get_bt_afh_map_from_bt(btc, 0, p); + } + if (++cnt >= 3) + cnt = 0; CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[BT Coexist info]============"); + "\r\n _____[BT Coexist info]____"); CL_PRINTF(cli_buf); - if (btcoexist->manual_control) { + if (btc->manual_control) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n ============[Under Manual Control]============"); - CL_PRINTF(cli_buf); + "\r\n __[Under Manual Control]_"); + CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n =========================================="); + "\r\n _________________________"); CL_PRINTF(cli_buf); } - if (!coex_sta->bt_disabled) { - if (coex_sta->bt_coex_supported_feature == 0) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, - &coex_sta->bt_coex_supported_feature); - - if ((coex_sta->bt_coex_supported_version == 0) || - (coex_sta->bt_coex_supported_version == 0xffff)) - btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, - &coex_sta->bt_coex_supported_version); - - if (coex_sta->bt_reg_vendor_ac == 0xffff) - coex_sta->bt_reg_vendor_ac = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xac) & 0xffff); - - if (coex_sta->bt_reg_vendor_ae == 0xffff) - coex_sta->bt_reg_vendor_ae = (u16)( - btcoexist->btc_get_bt_reg(btcoexist, 3, - 0xae) & 0xffff); - - btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, - &bt_patch_ver); - btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; - - if (coex_sta->num_of_profile > 0) { - cnt++; - - if (cnt >= 3) { - btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, - &coex_sta->bt_afh_map[0]); - cnt = 0; - } - } + if (btc->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ____[Coex is STOPPED]____"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n _________________________"); + CL_PRINTF(cli_buf); } - if (psd_scan->ant_det_try_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / 0x%x", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + board_info->rfe_type); + CL_PRINTF(cli_buf); + + bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8821c_2ant, glcoex_ver_8821c_2ant, + glcoex_ver_btdesired_8821c_2ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8821c_2ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ", "BT status", + ((coex_sta->bt_disabled) ? ("disabled") : + ((coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + : ((BT_8821C_2ANT_BSTATUS_NCON_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8821C_2ANT_BSTATUS_CON_IDLE == + coex_dm->bt_status) ? "connected-idle" : "busy"))))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : + (coex_sta->is_tdma_btautoslot_hang ? + "(auto-slot hang!!)" : ""))); + CL_PRINTF(cli_buf); +} + +void ex_halbtc8821c2ant_display_coex_info(struct btc_coexist *btc) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + struct btc_board_info *board_info = &btc->board_info; + struct btc_bt_link_info *bt_link_info = &btc->bt_link_info; + + u8 *cli_buf = btc->cli_buf; + u8 u8tmp[4], i, ps_tdma_case = 0; + u32 u32tmp[4]; + u16 u16tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + static u8 pop_report_in_10s; + u32 phyver = 0; + boolean lte_coex_on = FALSE; + static u8 cnt; + u32 ratio_crc, cnt_ok, cnt_err; + u8 * const p = &coex_sta->bt_afh_map[0]; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info 8821C]============"); + CL_PRINTF(cli_buf); + + if (btc->manual_control) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s / %d", - "Ant PG Num/ Mech/ Pos/ RFE", - board_info->pg_ant_num, board_info->btdm_ant_num, - (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT - ? "Main" : "Aux"), - rfe_type->rfe_module_type); + "\r\n ============[Under Manual Control]============"); CL_PRINTF(cli_buf); - } else { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", - "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", - board_info->pg_ant_num, - board_info->btdm_ant_num_by_ant_det, - (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT - ? "Main" : "Aux"), - rfe_type->rfe_module_type, - psd_scan->ant_det_try_count, - psd_scan->ant_det_fail_count, - psd_scan->ant_det_result); + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } else if (btc->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } else if (!coex_sta->run_time_state) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Run Time State = False]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } else if (coex_sta->freeze_coexrun_by_btinfo) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[freeze_coexrun_by_btinfo]============"); CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + if (!coex_sta->bt_disabled && + (coex_sta->bt_coex_supported_version == 0 || + coex_sta->bt_coex_supported_version == 0xffff) && + cnt == 0) { + btc->btc_get(btc, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); - if (board_info->btdm_ant_det_finish) { + btc->btc_get(btc, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); - if (psd_scan->ant_det_result != 12) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s", - "Ant Det PSD Value", - psd_scan->ant_det_peak_val); - else - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %d", - "Ant Det PSD Value", - psd_scan->ant_det_psd_scan_peak_val - / 100); - CL_PRINTF(cli_buf); - } + coex_sta->bt_reg_vendor_ac = (u16)(btc->btc_get_bt_reg(btc, 3, + 0xac) & + 0xffff); + + coex_sta->bt_reg_vendor_ae = (u16)(btc->btc_get_bt_reg(btc, 3, + 0xae) & + 0xffff); + + btc->btc_get(btc, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + btc->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) + btc->btc_get_bt_afh_map_from_bt(btc, 0, p); } + if (++cnt >= 3) + cnt = 0; - bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; - btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); - phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %s/ %s / 0x%x", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, + (board_info->btdm_ant_num == 1 ? "Shared" : "Non-Shared"), + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + board_info->rfe_type); + CL_PRINTF(cli_buf); + bt_patch_ver = btc->bt_info.bt_get_fw_ver; + btc->btc_get(btc, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btc->btc_get_bt_phydm_version(btc); bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, @@ -4838,9 +4802,9 @@ void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) glcoex_ver_btdesired_8821c_2ant, bt_coex_ver, (bt_coex_ver == 0xff ? "Unknown" : - (coex_sta->bt_disabled ? "BT-disable" : - (bt_coex_ver >= glcoex_ver_btdesired_8821c_2ant ? - "Match" : "Mis-Match")))); + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8821c_2ant ? + "Match" : "Mis-Match")))); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, @@ -4850,10 +4814,11 @@ void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_sta->cut_version + 65); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x (RF-Ch = %d)", "AFH Map to BT", coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], - coex_dm->wifi_chnl_info[2]); + coex_dm->wifi_chnl_info[2], coex_sta->wl_center_channel); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ", @@ -4867,7 +4832,7 @@ void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + btc->btc_disp_dbg_msg(btc, BTC_DBG_DISP_WIFI_STATUS); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); @@ -4875,14 +4840,14 @@ void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) pop_report_in_10s++; CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", - "BT [status/ rssi/ retryCnt/ popCnt]", + "\r\n %-35s = %s/ %ddBm/ %d/ %d", + "BT status/ rssi/ retryCnt/ popCnt", ((coex_sta->bt_disabled) ? ("disabled") : (( - coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") - : ((BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == - coex_dm->bt_status) ? "non-connected idle" : - ((BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) - ? "connected-idle" : "busy")))), + coex_sta->c2h_bt_inquiry_page) ? ("inquiry-page") + : ((BT_8821C_2ANT_BSTATUS_NCON_IDLE == + coex_dm->bt_status) ? "non-connected-idle" : + ((coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_CON_IDLE) + ? "connected-idle" : "busy")))), coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, coex_sta->pop_event_cnt); CL_PRINTF(cli_buf); @@ -4892,114 +4857,124 @@ void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) pop_report_in_10s = 0; } - if (coex_sta->num_of_profile != 0) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s%s%s%s%s", - "Profiles", - ((bt_link_info->a2dp_exist) ? - ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," : + "\r\n %-35s = %s%s%s%s%s%s (multilink = %d)", + "Profiles", + ((bt_link_info->a2dp_exist) ? + ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," : "A2DP,") : ""), - ((bt_link_info->sco_exist) ? "HFP," : ""), - ((bt_link_info->hid_exist) ? + ((bt_link_info->sco_exist) ? "HFP," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->is_hid_rcu) ? "HID(RCU)" : ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : - "HID(2/18),") : ""), - ((bt_link_info->pan_exist) ? "PAN," : ""), - ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + "HID(2/18),")) : ""), + ((bt_link_info->pan_exist) ? + ((coex_sta->is_bt_opp_exist) ? "OPP," : "PAN,") : + ""), + ((coex_sta->voice_over_HOGP) ? "Voice," : ""), + ((coex_sta->msft_mr_exist) ? "MR" : ""), + coex_sta->is_bt_multi_link); else CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = None", "Profiles"); + "\r\n %-35s = %s", "Profiles", + (coex_sta->msft_mr_exist) ? "MR" : "None"); CL_PRINTF(cli_buf); - if (bt_link_info->a2dp_exist) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", - "A2DP Rate/Bitpool/Auto_Slot", - ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + "CQDDR/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "On" : "Off"), coex_sta->a2dp_bit_pool, ((coex_sta->is_autoslot) ? "On" : "Off") ); CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %d/ %d", + "V_ID/D_name/FBSlot_Legacy/FBSlot_Le", + coex_sta->bt_a2dp_vendor_id, + coex_sta->bt_a2dp_device_name, + coex_sta->legacy_forbidden_slot, + coex_sta->le_forbidden_slot + ); + CL_PRINTF(cli_buf); } if (bt_link_info->hid_exist) { - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "HID PairNum/Forbid_Slot", - coex_sta->hid_pair_cnt, - coex_sta->forbidden_slot - ); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", + "HID PairNum", + coex_sta->hid_pair_cnt); CL_PRINTF(cli_buf); } CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", - "Role/RoleSwCnt/IgnWlact/Feature", - ((bt_link_info->slave_role) ? "Slave" : "Master"), - coex_sta->cnt_RoleSwitch, - ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), - coex_sta->bt_coex_supported_feature); + "Role/RoleSwCnt/IgnWlact/Feature", + ((bt_link_info->slave_role) ? "Slave" : "Master"), + coex_sta->cnt_role_switch, + ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), + coex_sta->bt_coex_supported_feature); CL_PRINTF(cli_buf); - if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + if (coex_sta->is_ble_scan_en) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", - "BLEScan Type/TV/Init/Ble", - coex_sta->bt_ble_scan_type, - (coex_sta->bt_ble_scan_type & 0x1 ? - coex_sta->bt_ble_scan_para[0] : 0x0), - (coex_sta->bt_ble_scan_type & 0x2 ? - coex_sta->bt_ble_scan_para[1] : 0x0), - (coex_sta->bt_ble_scan_type & 0x4 ? - coex_sta->bt_ble_scan_para[2] : 0x0)); + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "BLEScan Type/TV/Init/Ble", + coex_sta->bt_ble_scan_type, + (coex_sta->bt_ble_scan_type & 0x1 ? + coex_sta->bt_ble_scan_para[0] : 0x0), + (coex_sta->bt_ble_scan_type & 0x2 ? + coex_sta->bt_ble_scan_para[1] : 0x0), + (coex_sta->bt_ble_scan_type & 0x4 ? + coex_sta->bt_ble_scan_para[2] : 0x0)); CL_PRINTF(cli_buf); } - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", - "ReInit/ReLink/IgnWlact/Page/NameReq", - coex_sta->cnt_ReInit, - coex_sta->cnt_setupLink, - coex_sta->cnt_IgnWlanAct, - coex_sta->cnt_Page, - coex_sta->cnt_RemoteNameReq - ); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d/ %d/ %d %s", + "ReInit/ReLink/IgnWlact/Page/NameReq", coex_sta->cnt_reinit, + coex_sta->cnt_setup_link, coex_sta->cnt_ign_wlan_act, + coex_sta->cnt_page, coex_sta->cnt_remote_name_req, + (coex_sta->is_setup_link ? "(Relink!!)" : "")); CL_PRINTF(cli_buf); - halbtc8821c2ant_read_score_board(btcoexist, &u16tmp[0]); + halbtc8821c2ant_read_scbd(btc, &u16tmp[0]); - if ((coex_sta->bt_reg_vendor_ae == 0xffff) || - (coex_sta->bt_reg_vendor_ac == 0xffff)) - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + if (coex_sta->bt_reg_vendor_ae == 0xffff || + coex_sta->bt_reg_vendor_ac == 0xffff) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = x/ x/ 0x%04x", + "0xae[4]/0xac[1:0]/ScBd(B->W)", u16tmp[0]); else CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ %04x", - "0xae[4]/0xac[1:0]/Scoreboard", - ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), + "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x", + "0xae[4]/0xac[1:0]/ScBd(B->W)", + (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); CL_PRINTF(cli_buf); if (coex_sta->num_of_profile > 0) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", - "AFH MAP", - coex_sta->bt_afh_map[0], - coex_sta->bt_afh_map[1], - coex_sta->bt_afh_map[2], - coex_sta->bt_afh_map[3], - coex_sta->bt_afh_map[4], - coex_sta->bt_afh_map[5], - coex_sta->bt_afh_map[6], - coex_sta->bt_afh_map[7], - coex_sta->bt_afh_map[8], - coex_sta->bt_afh_map[9] - ); + "\r\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x", + "AFH MAP", + coex_sta->bt_afh_map[0], + coex_sta->bt_afh_map[1], + coex_sta->bt_afh_map[2], + coex_sta->bt_afh_map[3], + coex_sta->bt_afh_map[4], + coex_sta->bt_afh_map[5], + coex_sta->bt_afh_map[6], + coex_sta->bt_afh_map[7], + coex_sta->bt_afh_map[8], + coex_sta->bt_afh_map[9]); CL_PRINTF(cli_buf); } - for (i = 0; i < BT_INFO_SRC_8821C_2ANT_MAX; i++) { + for (i = 0; i < BT_8821C_2ANT_INFO_SRC_MAX; i++) { if (coex_sta->bt_info_c2h_cnt[i]) { CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)", glbt_info_src_8821c_2ant[i], coex_sta->bt_info_c2h[i][0], coex_sta->bt_info_c2h[i][1], @@ -5014,7 +4989,7 @@ void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) } /* Sw mechanism */ - if (btcoexist->manual_control) + if (btc->manual_control) CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[mechanism] (before Manual)============"); else @@ -5023,79 +4998,108 @@ void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_PRINTF(cli_buf); - ps_tdma_case = coex_dm->cur_ps_tdma; - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s)", + "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)", "TDMA", coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], coex_dm->ps_tdma_para[4], ps_tdma_case, - (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"), - (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant")); + (coex_dm->cur_ps_tdma_on ? "TDMA-On" : "TDMA-Off")); + CL_PRINTF(cli_buf); + + switch (coex_sta->wl_coex_mode) { + case BT_8821C_2ANT_WLINK_2G1PORT: + default: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "2G-SP"); + break; + case BT_8821C_2ANT_WLINK_2GMPORT: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "2G-MP"); + break; + case BT_8821C_2ANT_WLINK_25GMPORT: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "25G-MP"); + break; + case BT_8821C_2ANT_WLINK_5G: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "5G"); + break; + case BT_8821C_2ANT_WLINK_2GGO: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "2G-P2P"); + break; + case BT_8821C_2ANT_WLINK_BTMR: + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", "Coex_Mode", "BT-MR"); + break; + } CL_PRINTF(cli_buf); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); - u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + u32tmp[0] = btc->btc_read_4byte(btc, 0x6c0); + u32tmp[1] = btc->btc_read_4byte(btc, 0x6c4); + u32tmp[2] = btc->btc_read_4byte(btc, 0x6c8); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", "Table/0x6c0/0x6c4/0x6c8", coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); CL_PRINTF(cli_buf); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); + u8tmp[0] = btc->btc_read_1byte(btc, 0x778); + u32tmp[0] = btc->btc_read_4byte(btc, 0x6cc); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x", - "0x778/0x6cc", - u8tmp[0], u32tmp[0]); + "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x/ %d", + "0x778/0x6cc/ScBd(W->B)/RunCnt", u8tmp[0], u32tmp[0], + coex_sta->score_board_WB, coex_sta->coex_run_cnt); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "AntDiv/BtCtrlLPS/LPRA/PsFail", - ((board_info->ant_div_cfg) ? "On" : "Off"), + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d/ %d", + "AntDiv/BtCtrlLPS/LPRA/PsFail/g_busy", + ((board_info->ant_div_cfg) ? + ((coex_dm->cur_antdiv_type) ? "On(Hw)" : "On(Sw)") : "Off"), ((coex_sta->force_lps_ctrl) ? "On" : "Off"), ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"), - coex_sta->cnt_set_ps_state_fail); + coex_sta->cnt_set_ps_state_fail, + coex_sta->gl_wifi_busy); CL_PRINTF(cli_buf); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "WL_DACSwing/ BT_Dec_Pwr", coex_dm->cur_fw_dac_swing_lvl, - coex_dm->cur_bt_dec_pwr_lvl); + "WL_Pwr/ BT_Pwr", coex_dm->cur_wl_pwr_lvl, + coex_dm->cur_bt_pwr_lvl); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "Null All/Retry/Ack/BT_Empty/BT_Late", + coex_sta->wl_fw_dbg_info[1], + coex_sta->wl_fw_dbg_info[2], + coex_sta->wl_fw_dbg_info[3], + coex_sta->wl_fw_dbg_info[4], + coex_sta->wl_fw_dbg_info[5]); CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp[0] = halbtc8821c2ant_read_indirect_reg(btc, 0x38); lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? TRUE : FALSE; if (lte_coex_on) { - u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa0); - u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa4); + u32tmp[0] = halbtc8821c2ant_read_indirect_reg(btc, 0xa0); + u32tmp[1] = halbtc8821c2ant_read_indirect_reg(btc, 0xa4); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", - "LTE Coex Table W_L/B_L", - u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + "LTE Coex Table W_L/B_L", u32tmp[0] & 0xffff, + u32tmp[1] & 0xffff); CL_PRINTF(cli_buf); - - u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xa8); - u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xac); - u32tmp[2] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xb0); - u32tmp[3] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, - 0xb4); + u32tmp[0] = halbtc8821c2ant_read_indirect_reg(btc, 0xa8); + u32tmp[1] = halbtc8821c2ant_read_indirect_reg(btc, 0xac); + u32tmp[2] = halbtc8821c2ant_read_indirect_reg(btc, 0xb0); + u32tmp[3] = halbtc8821c2ant_read_indirect_reg(btc, 0xb4); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "LTE Break Table W_L/B_L/L_W/L_B", u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); CL_PRINTF(cli_buf); - } /* Hw setting */ @@ -5103,9 +5107,9 @@ void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) "============[Hw setting]============"); CL_PRINTF(cli_buf); - u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); - u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + u32tmp[0] = halbtc8821c2ant_read_indirect_reg(btc, 0x38); + u32tmp[1] = halbtc8821c2ant_read_indirect_reg(btc, 0x54); + u8tmp[0] = btc->btc_read_1byte(btc, 0x73); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", "LTE Coex/Path Owner", @@ -5130,7 +5134,7 @@ void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) CL_PRINTF(cli_buf); } CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s (gnt_err = %d)", "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), @@ -5140,90 +5144,103 @@ void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) coex_sta->gnt_error_cnt); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", - "GNT_WL/GNT_BT", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ 0x%x", + "GNT_WL/GNT_BT/ RF_0x1", (int)((u32tmp[1] & BIT(2)) >> 2), - (int)((u32tmp[1] & BIT(3)) >> 3)); + (int)((u32tmp[1] & BIT(3)) >> 3), + btc->btc_get_rf_reg(btc, BTC_RF_A, 0x1, 0xfffff)); CL_PRINTF(cli_buf); - - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0); - u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); + u32tmp[0] = btc->btc_read_4byte(btc, 0xcb0); + u32tmp[1] = btc->btc_read_4byte(btc, 0xcb4); + u8tmp[0] = btc->btc_read_1byte(btc, 0xcba); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", "0xcb0/0xcb4/0xcb8[23:16]", u32tmp[0], u32tmp[1], u8tmp[0], - ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); + ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); CL_PRINTF(cli_buf); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + u32tmp[0] = btc->btc_read_4byte(btc, 0x4c); + u8tmp[2] = btc->btc_read_1byte(btc, 0x64); + u8tmp[0] = btc->btc_read_1byte(btc, 0x4c6); + u8tmp[1] = btc->btc_read_1byte(btc, 0x40); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "4c[24:23]/64[0]/4c6[4]/40[5]", - (u32tmp[0] & (BIT(24) | BIT(23))) >> 23 , u8tmp[2] & 0x1 , - (int)((u8tmp[0] & BIT(4)) >> 4), + (int)(u32tmp[0] & (BIT(24) | BIT(23))) >> 23, + u8tmp[2] & 0x1, (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5)); CL_PRINTF(cli_buf); - u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); - u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); - u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); - u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50); + u32tmp[0] = btc->btc_read_4byte(btc, 0x550); + u8tmp[0] = btc->btc_read_1byte(btc, 0x522); + u8tmp[1] = btc->btc_read_1byte(btc, 0x953); + u8tmp[2] = btc->btc_read_1byte(btc, 0xc50); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x", - "0x550/0x522/4-RxAGC/0xc50", - u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]); + "0x550/0x522/4-RxAGC/0xc50", u32tmp[0], u8tmp[0], + (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]); CL_PRINTF(cli_buf); - fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_OFDM); - fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_FA_CCK); - cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_OFDM); - cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, - PHYDM_INFO_CCA_CCK); - - ratio_ofdm = (fa_ofdm == 0) ? 1000 : (cca_ofdm/fa_ofdm); + fa_ofdm = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_FA_OFDM); + fa_cck = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_FA_CCK); + cca_ofdm = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CCA_OFDM); + cca_cck = btc->btc_phydm_query_PHY_counter(btc, PHYDM_INFO_CCA_CCK); CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, - "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x (%d)", + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", - cca_cck, fa_cck, cca_ofdm, fa_ofdm, - ratio_ofdm); + cca_cck, fa_cck, cca_ofdm, fa_ofdm); CL_PRINTF(cli_buf); -#if 1 - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_OK CCK/11g/11n/11ac", coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); CL_PRINTF(cli_buf); - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d (%d, %d)", + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_Err CCK/11g/11n/11ac", coex_sta->crc_err_cck, coex_sta->crc_err_11g, - coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht, - coex_sta->now_crc_ratio, coex_sta->acc_crc_ratio); + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); CL_PRINTF(cli_buf); -#endif - CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", - "WlHiPri/ Locking/ Locked/ Noisy", - (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s-%d/ %d (Tx macid: %d)", + "Rate RxD/RxRTS/TxD/TxRetry_ratio", + coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate, + (coex_sta->wl_tx_rate & 0x80 ? "SGI" : "LGI"), + coex_sta->wl_tx_rate & 0x7f, + coex_sta->wl_tx_retry_ratio, + coex_sta->wl_tx_macid); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %s/ %d", + "HiPr/ Locking/ warn/ Locked/ Noisy", + (coex_sta->wifi_high_pri_task1 ? "Yes" : "No"), (coex_sta->cck_lock ? "Yes" : "No"), - (coex_sta->cck_ever_lock ? "Yes" : "No"), + (coex_sta->cck_lock_warn ? "Yes" : "No"), + (coex_sta->cck_lock_ever ? "Yes" : "No"), coex_sta->wl_noisy_level); CL_PRINTF(cli_buf); + u8tmp[0] = btc->btc_read_1byte(btc, 0xf8e); + u8tmp[1] = btc->btc_read_1byte(btc, 0xf8f); + u8tmp[2] = btc->btc_read_1byte(btc, 0xd14); + u8tmp[3] = btc->btc_read_1byte(btc, 0xd54); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "EVM_A/ EVM_B/ SNR_A/ SNR_B", + (u8tmp[0] > 127 ? u8tmp[0] - 256 : u8tmp[0]), + (u8tmp[1] > 127 ? u8tmp[1] - 256 : u8tmp[1]), + (u8tmp[2] > 127 ? u8tmp[2] - 256 : u8tmp[2]), + (u8tmp[3] > 127 ? u8tmp[3] - 256 : u8tmp[3])); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(Hi-pri rx/tx)", coex_sta->high_priority_rx, coex_sta->high_priority_tx); @@ -5233,64 +5250,58 @@ void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) "0x774(Lo-pri rx/tx)", coex_sta->low_priority_rx, coex_sta->low_priority_tx, (bt_link_info->slave_role ? "(Slave!!)" : ( - coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); + coex_sta->is_tdma_btautoslot_hang ? + "(auto-slot hang!!)" : ""))); CL_PRINTF(cli_buf); - btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); + btc->btc_disp_dbg_msg(btc, BTC_DBG_DISP_COEX_STATISTICS); } - -void ex_halbtc8821c2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +void ex_halbtc8821c2ant_ips_notify(struct btc_coexist *btc, u8 type) { - if (btcoexist->manual_control || btcoexist->stop_coex_dm) + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + + if (btc->manual_control || btc->stop_coex_dm) return; - if (BTC_IPS_ENTER == type) { + if (type == BTC_IPS_ENTER) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], IPS ENTER notify\n"); BTC_TRACE(trace_buf); coex_sta->under_ips = TRUE; coex_sta->under_lps = FALSE; - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_ONOFF | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, - FALSE); + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE | + BT_8821C_2ANT_SCBD_ONOFF | + BT_8821C_2ANT_SCBD_SCAN | + BT_8821C_2ANT_SCBD_UNDERTEST, + FALSE); - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_WLAN_OFF); + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_2ANT_PHASE_WOFF); - halbtc8821c2ant_action_coex_all_off(btcoexist); - } else if (BTC_IPS_LEAVE == type) { + halbtc8821c2ant_action_coex_all_off(btc); + } else if (type == BTC_IPS_LEAVE) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], IPS LEAVE notify\n"); BTC_TRACE(trace_buf); coex_sta->under_ips = FALSE; -#if 0 - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, TRUE); - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ONOFF, TRUE); -#endif - halbtc8821c2ant_init_hw_config(btcoexist, FALSE); - halbtc8821c2ant_init_coex_dm(btcoexist); - halbtc8821c2ant_query_bt_info(btcoexist); + halbtc8821c2ant_init_hw_config(btc, FALSE); + halbtc8821c2ant_init_coex_dm(btc); + halbtc8821c2ant_query_bt_info(btc); } } -void ex_halbtc8821c2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +void ex_halbtc8821c2ant_lps_notify(struct btc_coexist *btc, u8 type) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; static boolean pre_force_lps_on = FALSE; - if (btcoexist->manual_control || btcoexist->stop_coex_dm) + if (btc->manual_control || btc->stop_coex_dm) return; - if (BTC_LPS_ENABLE == type) { + if (type == BTC_LPS_ENABLE) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], LPS ENABLE notify\n"); BTC_TRACE(trace_buf); @@ -5300,382 +5311,366 @@ void ex_halbtc8821c2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) if (coex_sta->force_lps_ctrl == TRUE) { /* LPS No-32K */ /* Write WL "Active" in Score-board for PS-TDMA */ pre_force_lps_on = TRUE; - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, TRUE); + halbtc8821c2ant_write_scbd(btc, + BT_8821C_2ANT_SCBD_ACTIVE, + TRUE); } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ /* Write WL "Non-Active" in Score-board for Native-PS */ pre_force_lps_on = FALSE; - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, FALSE); + halbtc8821c2ant_write_scbd(btc, + BT_8821C_2ANT_SCBD_ACTIVE, + FALSE); + + halbtc8821c2ant_action_wifi_native_lps(btc); } - } else if (BTC_LPS_DISABLE == type) { + } else if (type == BTC_LPS_DISABLE) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], LPS DISABLE notify\n"); BTC_TRACE(trace_buf); coex_sta->under_lps = FALSE; - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, TRUE); + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE, + TRUE); - if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl)) - halbtc8821c2ant_query_bt_info(btcoexist); + if (!pre_force_lps_on && !coex_sta->force_lps_ctrl) + halbtc8821c2ant_query_bt_info(btc); } } -void ex_halbtc8821c2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c2ant_scan_notify(struct btc_coexist *btc, u8 type) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; boolean wifi_connected = FALSE; - boolean wifi_under_5g = FALSE; - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], SCAN notify()\n"); BTC_TRACE(trace_buf); - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + if (btc->manual_control || btc->stop_coex_dm) return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); - - /* this can't be removed for RF off_on event, or BT would dis-connect */ - halbtc8821c2ant_query_bt_info(btcoexist); - - if (BTC_SCAN_START == type) { - - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, - &wifi_under_5g); - - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_ONOFF, - TRUE); - - if (wifi_under_5g) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** SCAN START notify (5g)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_wifi_under5g(btcoexist); - return; - } - - coex_sta->wifi_is_high_pri_task = TRUE; + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + if (wifi_connected) BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** SCAN START notify (2g)\n"); - BTC_TRACE(trace_buf); - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); + "[BTCoex], ********** WL connected before SCAN\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL is not connected before SCAN\n"); - halbtc8821c2ant_run_coexist_mechanism( - btcoexist); + BTC_TRACE(trace_buf); - return; + /* this can't be removed for RF off_on event, + * r BT would dis-connect + */ + if (type != BTC_SCAN_FINISH) { + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE | + BT_8821C_2ANT_SCBD_SCAN | + BT_8821C_2ANT_SCBD_ONOFF, TRUE); } + if (type == BTC_SCAN_START_5G) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify (5G)\n"); + BTC_TRACE(trace_buf); - if (BTC_SCAN_START_2G == type) { - - if (!wifi_connected) - coex_sta->wifi_is_high_pri_task = TRUE; + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, + FC_EXCU, BT_8821C_2ANT_PHASE_5G); + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_5GSCANSTART); + } else if (type == BTC_SCAN_START_2G || type == BTC_SCAN_START) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], SCAN START notify (2G)\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_ONOFF, - TRUE); - - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); - - halbtc8821c2ant_run_coexist_mechanism(btcoexist); - - } else if (BTC_SCAN_FINISH == type) { + if (!wifi_connected) + coex_sta->wifi_high_pri_task2 = TRUE; - coex_sta->wifi_is_high_pri_task = FALSE; + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_2ANT_PHASE_2G); - btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, - &coex_sta->scan_ap_num); + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_2GSCANSTART); + } else if (type == BTC_SCAN_FINISH) { + btc->btc_get(btc, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num); BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", coex_sta->scan_ap_num); BTC_TRACE(trace_buf); - halbtc8821c2ant_run_coexist_mechanism(btcoexist); - } + coex_sta->wifi_high_pri_task2 = FALSE; + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_SCANFINISH); + } } -void ex_halbtc8821c2ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c2ant_switchband_notify(struct btc_coexist *btc, u8 type) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; - boolean wifi_connected = FALSE, bt_hs_on = FALSE; - u32 wifi_link_status = 0; - u32 num_of_wifi_link = 0; - boolean bt_ctrl_agg_buf_size = FALSE; - u8 agg_buf_size = 5; - - - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + if (btc->manual_control || btc->stop_coex_dm) return; coex_sta->switch_band_notify_to = type; if (type == BTC_SWITCH_TO_5G) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], switchband_notify --- switch to 5G\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_wifi_under5g(btcoexist); - + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_5GSWITCHBAND); } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n"); + "[BTCoex], switchband_notify --- BTC_SWITCH_TO_2G (no for scan)\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_run_coexist_mechanism(btcoexist); - + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_2GSWITCHBAND); } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], switchband_notify --- switch to 2G\n"); BTC_TRACE(trace_buf); - ex_halbtc8821c2ant_scan_notify(btcoexist, - BTC_SCAN_START_2G); + ex_halbtc8821c2ant_scan_notify(btc, BTC_SCAN_START_2G); } coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; } - -void ex_halbtc8821c2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c2ant_connect_notify(struct btc_coexist *btc, + u8 type) { - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + + if (btc->manual_control || btc->stop_coex_dm) return; - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_ONOFF, - TRUE); + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE | + BT_8821C_2ANT_SCBD_SCAN | + BT_8821C_2ANT_SCBD_ONOFF, TRUE); - if ((BTC_ASSOCIATE_5G_START == type) || - (BTC_ASSOCIATE_5G_FINISH == type)) { + if (type == BTC_ASSOCIATE_5G_START || + type == BTC_ASSOCIATE_5G_FINISH) { + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_2ANT_PHASE_5G); - if (BTC_ASSOCIATE_5G_START == type) - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], connect_notify --- 5G start\n"); - else + if (type == BTC_ASSOCIATE_5G_START) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], connect_notify --- 5G finish\n"); - - BTC_TRACE(trace_buf); - - halbtc8821c2ant_action_wifi_under5g(btcoexist); - return; - } - + "[BTCoex], CONNECT START notify (5G)\n"); + BTC_TRACE(trace_buf); - if (BTC_ASSOCIATE_START == type) { + halbtc8821c2ant_run_coex(btc, + BT_8821C_2ANT_RSN_5GCONSTART); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify (5G)\n"); + BTC_TRACE(trace_buf); - coex_sta->wifi_is_high_pri_task = TRUE; + halbtc8821c2ant_run_coex(btc, + BT_8821C_2ANT_RSN_5GCONFINISH); + } + } else if (type == BTC_ASSOCIATE_START) { + coex_sta->wifi_high_pri_task1 = TRUE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], CONNECT START notify (2G)\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_2ANT_PHASE_2G); - halbtc8821c2ant_run_coexist_mechanism(btcoexist); + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_2GCONSTART); /* To keep TDMA case during connect process, to avoid changed by Btinfo and runcoexmechanism */ coex_sta->freeze_coexrun_by_btinfo = TRUE; - coex_dm->arp_cnt = 0; - - } else if (BTC_ASSOCIATE_FINISH == type) { - - coex_sta->wifi_is_high_pri_task = FALSE; + } else if (type == BTC_ASSOCIATE_FINISH) { + coex_sta->wifi_high_pri_task1 = FALSE; coex_sta->freeze_coexrun_by_btinfo = FALSE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], CONNECT FINISH notify (2G)\n"); + "[BTCoex], CONNECT FINISH notify (2G)\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_run_coexist_mechanism(btcoexist); + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_2GCONFINISH); } } -void ex_halbtc8821c2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c2ant_media_status_notify(struct btc_coexist *btc, u8 type) { - u8 h2c_parameter[3] = {0}; - u32 wifi_bw; - u8 wifi_central_chnl; - u8 ap_num = 0; - boolean wifi_under_b_mode = FALSE, wifi_under_5g = FALSE; - + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + u8 h2c_parameter[3] = {0}; + boolean wifi_under_b_mode = FALSE; + u16 ap_beacon_interval = 100; - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + if (btc->manual_control || btc->stop_coex_dm) return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (BTC_MEDIA_CONNECT == type) { - + if (type == BTC_MEDIA_CONNECT || type == BTC_MEDIA_CONNECT_5G) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], MEDIA connect notify\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_ONOFF, - TRUE); - - if (wifi_under_5g) { + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE | + BT_8821C_2ANT_SCBD_ONOFF, TRUE); + if (type == BTC_MEDIA_CONNECT_5G) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], WiFi is under 5G!!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_wifi_under5g(btcoexist); - return; - } + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, + FC_EXCU, + BT_8821C_2ANT_PHASE_5G); - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); + halbtc8821c2ant_run_coex(btc, + BT_8821C_2ANT_RSN_5GMEDIA); + } else { + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, + FC_EXCU, + BT_8821C_2ANT_PHASE_2G); + + btc->btc_get(btc, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + /* CCK Tx */ + btc->btc_write_1byte(btc, 0x6cd, 0x00); + /* CCK Rx */ + btc->btc_write_1byte(btc, 0x6cf, 0x00); + } else { + /* CCK Tx */ + btc->btc_write_1byte(btc, 0x6cd, 0x00); + /* CCK Rx */ + btc->btc_write_1byte(btc, 0x6cf, 0x10); + } - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, - &wifi_under_b_mode); + btc->btc_get(btc, BTC_GET_U2_BEACON_PERIOD, + &ap_beacon_interval); - /* Set CCK Tx/Rx high Pri except 11b mode */ - if (wifi_under_b_mode) { - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x00); /* CCK Rx */ - } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], AP beacon interval = %d\n", + ap_beacon_interval); + BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte(btcoexist, 0x6cd, - 0x00); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, - 0x10); /* CCK Rx */ - } + /* set TDMA waiting BI if BI is not equal to 100 */ + if (ap_beacon_interval < 80 && ap_beacon_interval > 0) { + h2c_parameter[0] = 0xb; + h2c_parameter[1] = (100 / ap_beacon_interval); + + if (100 % ap_beacon_interval != 0) + h2c_parameter[1] = h2c_parameter[1] + 1; + } else if (ap_beacon_interval >= 180) { + h2c_parameter[0] = 0xb; + h2c_parameter[1] = (ap_beacon_interval / 100); + + if (ap_beacon_interval % 100 <= 80) + h2c_parameter[1] = h2c_parameter[1] - 1; + + h2c_parameter[1] = h2c_parameter[1] | 0x80; + } else { + h2c_parameter[0] = 0xb; + h2c_parameter[1] = 0x1; + } + + btc->btc_fill_h2c(btc, 0x69, 2, h2c_parameter); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], TDMA waiting BI = 0x%x\n", + h2c_parameter[1]); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_run_coex(btc, + BT_8821C_2ANT_RSN_2GMEDIA); + } } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], MEDIA disconnect notify\n"); BTC_TRACE(trace_buf); - btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ - btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + btc->btc_write_1byte(btc, 0x6cd, 0x0); /* CCK Tx */ + btc->btc_write_1byte(btc, 0x6cf, 0x0); /* CCK Rx */ - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, FALSE); - } + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE, + FALSE); + + coex_sta->cck_lock_ever = FALSE; + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_MEDIADISCON); + } - halbtc8821c2ant_update_wifi_channel_info(btcoexist, type); + halbtc8821c2ant_update_wifi_ch_info(btc, type); } -void ex_halbtc8821c2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c2ant_specific_packet_notify(struct btc_coexist *btc, u8 type) { - boolean under_4way = FALSE, wifi_under_5g = FALSE; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + boolean under_4way = FALSE; - if (btcoexist->manual_control || - btcoexist->stop_coex_dm) + if (btc->manual_control || btc->stop_coex_dm) return; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if (wifi_under_5g) { - + if (type & BTC_5G_BAND) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], WiFi is under 5G!!!\n"); + "[BTCoex], 5g special packet notify\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_action_wifi_under5g(btcoexist); + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_5GSPECIALPKT); return; } - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, - &under_4way); + btc->btc_get(btc, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way); if (under_4way) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], specific Packet ---- under_4way!!\n"); BTC_TRACE(trace_buf); - coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->wifi_high_pri_task1 = TRUE; coex_sta->specific_pkt_period_cnt = 2; - - } else if (BTC_PACKET_ARP == type) { - + } else if (type == BTC_PACKET_ARP) { coex_dm->arp_cnt++; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], specific Packet ARP notify -cnt = %d\n", coex_dm->arp_cnt); BTC_TRACE(trace_buf); - } else { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", + "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", type); BTC_TRACE(trace_buf); - coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->wifi_high_pri_task1 = TRUE; coex_sta->specific_pkt_period_cnt = 2; } - if (coex_sta->wifi_is_high_pri_task) { - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_SCAN, TRUE); - halbtc8821c2ant_run_coexist_mechanism(btcoexist); + if (coex_sta->wifi_high_pri_task1) { + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_SCAN, TRUE); + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_2GSPECIALPKT); } - } -void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length) +void ex_halbtc8821c2ant_bt_info_notify(struct btc_coexist *btc, u8 *tmp_buf, + u8 length) { - u8 i, rsp_source = 0; - boolean wifi_connected = FALSE; - boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE, - wifi_busy = FALSE; - static boolean is_scoreboard_scan = FALSE; - + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + u8 i, rsp_source = 0; + boolean wifi_connected = FALSE; + boolean wifi_busy = FALSE; + static boolean is_scoreboard_scan; + const u16 type_is_scan = BT_8821C_2ANT_SCBD_SCAN; + u8 type; rsp_source = tmp_buf[0] & 0xf; - if (rsp_source >= BT_INFO_SRC_8821C_2ANT_MAX) - rsp_source = BT_INFO_SRC_8821C_2ANT_WIFI_FW; + if (rsp_source >= BT_8821C_2ANT_INFO_SRC_MAX) + rsp_source = BT_8821C_2ANT_INFO_SRC_WIFI_FW; coex_sta->bt_info_c2h_cnt[rsp_source]++; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, @@ -5683,6 +5678,19 @@ void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, length); BTC_TRACE(trace_buf); + if (rsp_source == BT_8821C_2ANT_INFO_SRC_BT_RSP || + rsp_source == BT_8821C_2ANT_INFO_SRC_BT_ACT) { + if (coex_sta->bt_disabled) { + coex_sta->bt_disabled = FALSE; + coex_sta->is_bt_reenable = TRUE; + coex_sta->cnt_bt_reenable = 15; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT enable detected by bt_info\n"); + BTC_TRACE(trace_buf); + } + } + for (i = 0; i < length; i++) { coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; @@ -5701,8 +5709,7 @@ void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; - if (BT_INFO_SRC_8821C_2ANT_WIFI_FW != rsp_source) { - + if (rsp_source != BT_8821C_2ANT_INFO_SRC_WIFI_FW) { /* if 0xff, it means BT is under WHCK test */ coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE : FALSE); @@ -5723,7 +5730,7 @@ void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, 0x10) ? TRUE : FALSE); coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & - 0x9) ? TRUE : FALSE); + 0x8) ? TRUE : FALSE); coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? TRUE : FALSE); @@ -5733,10 +5740,11 @@ void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, coex_sta->a2dp_bit_pool = ((( coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? - (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : 0); + (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : 0); - coex_sta->is_bt_a2dp_sink = (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ? - TRUE : FALSE; + coex_sta->is_bt_a2dp_sink = + (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ? + TRUE : FALSE; coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & 0xf; @@ -5749,355 +5757,435 @@ void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; + coex_sta->is_bt_opp_exist = + (coex_sta->bt_info_ext2 & 0x1) ? TRUE : FALSE; + if (coex_sta->bt_retry_cnt >= 1) coex_sta->pop_event_cnt++; if (coex_sta->c2h_bt_remote_name_req) - coex_sta->cnt_RemoteNameReq++; + coex_sta->cnt_remote_name_req++; if (coex_sta->bt_info_ext & BIT(1)) - coex_sta->cnt_ReInit++; - - if (coex_sta->bt_info_ext & BIT(2)) { - coex_sta->cnt_setupLink++; - coex_sta->is_setupLink = TRUE; - coex_sta->bt_relink_downcount = 2; + coex_sta->cnt_reinit++; + + if (coex_sta->bt_info_ext & BIT(2) || + (coex_sta->bt_create_connection && + coex_sta->wl_pnp_wakeup_downcnt > 0)) { + coex_sta->cnt_setup_link++; + coex_sta->is_setup_link = TRUE; + if (coex_sta->is_bt_reenable) + coex_sta->bt_relink_downcount = 6; + else + coex_sta->bt_relink_downcount = 2; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], Re-Link start in BT info!!\n"); + "[BTCoex], Re-Link start in BT info!!\n"); BTC_TRACE(trace_buf); } else { - coex_sta->is_setupLink = FALSE; - coex_sta->bt_relink_downcount = 0; + coex_sta->is_setup_link = FALSE; + if (!coex_sta->is_bt_reenable) + coex_sta->bt_relink_downcount = 0; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Re-Link stop in BT info!!\n"); BTC_TRACE(trace_buf); } - if (coex_sta->bt_info_ext & BIT(3)) - coex_sta->cnt_IgnWlanAct++; + coex_sta->cnt_ign_wlan_act++; if (coex_sta->bt_info_ext & BIT(6)) - coex_sta->cnt_RoleSwitch++; + coex_sta->cnt_role_switch++; if (coex_sta->bt_info_ext & BIT(7)) coex_sta->is_bt_multi_link = TRUE; else coex_sta->is_bt_multi_link = FALSE; - if (coex_sta->bt_create_connection) { - coex_sta->cnt_Page++; + if (coex_sta->bt_info_ext & BIT(0)) + coex_sta->is_hid_rcu = TRUE; + else + coex_sta->is_hid_rcu = FALSE; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, - &wifi_busy); + if (coex_sta->bt_info_ext & BIT(5)) + coex_sta->is_ble_scan_en = TRUE; + else + coex_sta->is_ble_scan_en = FALSE; - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + if (coex_sta->bt_create_connection) { + coex_sta->cnt_page++; - if ((wifi_link) || (wifi_roam) || (wifi_scan) || - (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { + btc->btc_get(btc, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + if (coex_sta->is_wifi_linkscan_process || + coex_sta->wifi_high_pri_task1 || + coex_sta->wifi_high_pri_task2 || + wifi_busy) { is_scoreboard_scan = TRUE; - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_SCAN, TRUE); + halbtc8821c2ant_write_scbd(btc, type_is_scan, + TRUE); } else - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_SCAN, FALSE); + halbtc8821c2ant_write_scbd(btc, type_is_scan, + FALSE); } else { - if (is_scoreboard_scan) { - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_SCAN, FALSE); - is_scoreboard_scan = FALSE; - } + if (is_scoreboard_scan) { + halbtc8821c2ant_write_scbd(btc, type_is_scan, + FALSE); + is_scoreboard_scan = FALSE; + } } /* Here we need to resend some wifi info to BT */ /* because bt is reset and loss of the info. */ + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); - if ((!btcoexist->manual_control) && - (!btcoexist->stop_coex_dm)) { + /* Re-Init */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + if (wifi_connected) + type = BTC_MEDIA_CONNECT; + else + type = BTC_MEDIA_DISCONNECT; + halbtc8821c2ant_update_wifi_ch_info(btc, type); + } - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, - &wifi_connected); + /* If Ignore_WLanAct && not SetUp_Link */ + if ((coex_sta->bt_info_ext & BIT(3)) && + (!(coex_sta->bt_info_ext & BIT(2))) && + (!(coex_sta->bt_info_ext & BIT(6)))) { - /* Re-Init */ - if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_ignore_wlan_act(btc, FC_EXCU, FALSE); + } else { + if (coex_sta->bt_info_ext & BIT(2)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + "[BTCoex], BT ignore Wlan active because Re-link!!\n"); BTC_TRACE(trace_buf); - if (wifi_connected) - halbtc8821c2ant_update_wifi_channel_info( - btcoexist, BTC_MEDIA_CONNECT); - else - halbtc8821c2ant_update_wifi_channel_info( - btcoexist, - BTC_MEDIA_DISCONNECT); - } - - - /* If Ignore_WLanAct && not SetUp_Link */ - if ((coex_sta->bt_info_ext & BIT(3)) && - (!(coex_sta->bt_info_ext & BIT(2))) && - (!(coex_sta->bt_info_ext & BIT(6)))) { - + } else if (coex_sta->bt_info_ext & BIT(6)) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_ignore_wlan_act(btcoexist, - FORCE_EXEC, FALSE); - } else { - if (coex_sta->bt_info_ext & BIT(2)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ignore Wlan active because Re-link!!\n"); - BTC_TRACE(trace_buf); - } else if (coex_sta->bt_info_ext & BIT(6)) { - BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); - BTC_TRACE(trace_buf); - } } } + } + + halbtc8821c2ant_update_bt_link_info(btc); + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_BTINFO); +} + +void ex_halbtc8821c2ant_wl_fwdbginfo_notify(struct btc_coexist *btc, + u8 *tmp_buf, u8 length) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + u8 i = 0; + static u8 tmp_buf_pre[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d (len = %d)\n", + tmp_buf[0], tmp_buf[1], tmp_buf[2], tmp_buf[3], tmp_buf[4], + tmp_buf[5], length); + BTC_TRACE(trace_buf); + + if (tmp_buf[0] == 0x8) { + for (i = 1; i <= 5; i++) { + coex_sta->wl_fw_dbg_info[i] = + (tmp_buf[i] >= tmp_buf_pre[i]) ? + (tmp_buf[i] - tmp_buf_pre[i]) : + (255 - tmp_buf_pre[i] + tmp_buf[i]); + tmp_buf_pre[i] = tmp_buf[i]; + } } +} + +void ex_halbtc8821c2ant_rx_rate_change_notify(struct btc_coexist *btc, + BOOLEAN is_data_frame, + u8 btc_rate_id) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct coex_dm_8821c_2ant *coex_dm = &btc->coex_dm_8821c_2ant; + BOOLEAN wifi_connected = FALSE; + + btc->btc_get(btc, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected); + + if (is_data_frame) { + coex_sta->wl_rx_rate = btc_rate_id; - if ((coex_sta->bt_info_ext & BIT(5))) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + "[BTCoex], rx_rate_change_notify data rate id = %d, RTS_Rate = %d\n", + coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate); BTC_TRACE(trace_buf); - coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( - btcoexist); + } else { + coex_sta->wl_rts_rx_rate = btc_rate_id; - if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) - coex_sta->bt_ble_scan_para[0] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x1); - if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) - coex_sta->bt_ble_scan_para[1] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x2); - if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) - coex_sta->bt_ble_scan_para[2] = - btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, - 0x4); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], rts_rate_change_notify RTS rate id = %d, RTS_Rate = %d\n", + coex_sta->wl_rts_rx_rate, coex_sta->wl_rts_rx_rate); + BTC_TRACE(trace_buf); + } + + if (wifi_connected && + (coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_ACL_BUSY || + coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_ACL_SCO_BUSY || + coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_SCO_BUSY)) { + if (coex_sta->wl_rx_rate == BTC_CCK_5_5 || + coex_sta->wl_rx_rate == BTC_OFDM_6 || + coex_sta->wl_rx_rate == BTC_MCS_0) { + coex_sta->cck_lock_warn = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck lock warning...\n"); + BTC_TRACE(trace_buf); + } else if (coex_sta->wl_rx_rate == BTC_CCK_1 || + coex_sta->wl_rx_rate == BTC_CCK_2 || + coex_sta->wl_rts_rx_rate == BTC_CCK_1 || + coex_sta->wl_rts_rx_rate == BTC_CCK_2) { + coex_sta->cck_lock = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck locking...\n"); + BTC_TRACE(trace_buf); + } else { + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], cck unlock...\n"); + BTC_TRACE(trace_buf); + } + } else { + if (coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_CON_IDLE || + coex_dm->bt_status == BT_8821C_2ANT_BSTATUS_NCON_IDLE) { + coex_sta->cck_lock_warn = FALSE; + coex_sta->cck_lock = FALSE; + } } +} + +void ex_halbtc8821c2ant_tx_rate_change_notify(struct btc_coexist *btc, + u8 tx_rate, u8 tx_retry_ratio, + u8 macid) +{ + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; - halbtc8821c2ant_update_bt_link_info(btcoexist); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], tx_rate_change_notify Tx_Rate = %d, Tx_Retry_Ratio = %d, macid =%d\n", + tx_rate, tx_retry_ratio, macid); + BTC_TRACE(trace_buf); - halbtc8821c2ant_run_coexist_mechanism(btcoexist); + coex_sta->wl_tx_rate = tx_rate; + coex_sta->wl_tx_retry_ratio = tx_retry_ratio; + coex_sta->wl_tx_macid = macid; } -void ex_halbtc8821c2ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type) +void ex_halbtc8821c2ant_rf_status_notify(struct btc_coexist *btc, u8 type) { + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); BTC_TRACE(trace_buf); - if (BTC_RF_ON == type) { + if (type == BTC_RF_ON) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF is turned ON!!\n"); BTC_TRACE(trace_buf); - btcoexist->stop_coex_dm = FALSE; + btc->stop_coex_dm = FALSE; coex_sta->is_rf_state_off = FALSE; -#if 0 - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, TRUE); - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ONOFF, TRUE); -#endif - } else if (BTC_RF_OFF == type) { + } else if (type == BTC_RF_OFF) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF is turned OFF!!\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_WLAN_OFF); + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE | + BT_8821C_2ANT_SCBD_ONOFF | + BT_8821C_2ANT_SCBD_SCAN | + BT_8821C_2ANT_SCBD_UNDERTEST, + FALSE); - halbtc8821c2ant_action_coex_all_off(btcoexist); + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_2ANT_PHASE_WOFF); - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_ONOFF | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, - FALSE); + halbtc8821c2ant_action_coex_all_off(btc); - btcoexist->stop_coex_dm = TRUE; + btc->stop_coex_dm = TRUE; coex_sta->is_rf_state_off = TRUE; + /* must place in the last step */ + halbtc8821c2ant_update_wifi_ch_info(btc, BTC_MEDIA_DISCONNECT); } } -void ex_halbtc8821c2ant_halt_notify(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c2ant_halt_notify(struct btc_coexist *btc) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); BTC_TRACE(trace_buf); - halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_2ANT_PHASE_WLAN_OFF); + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE | + BT_8821C_2ANT_SCBD_ONOFF | + BT_8821C_2ANT_SCBD_SCAN | + BT_8821C_2ANT_SCBD_UNDERTEST, + FALSE); - ex_halbtc8821c2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + BT_8821C_2ANT_PHASE_WOFF); - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_ONOFF | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, - FALSE); + halbtc8821c2ant_action_coex_all_off(btc); + + btc->stop_coex_dm = TRUE; + + /* must place in the last step */ + halbtc8821c2ant_update_wifi_ch_info(btc, BTC_MEDIA_DISCONNECT); } -void ex_halbtc8821c2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state) +void ex_halbtc8821c2ant_pnp_notify(struct btc_coexist *btc, u8 pnp_state) { - boolean wifi_under_5g = FALSE; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct wifi_link_info_8821c_2ant *wifi_link_info_ext = + &btc->wifi_link_info_8821c_2ant; + static u8 pre_pnp_state; + u8 phase; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); BTC_TRACE(trace_buf); - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); - - if ((BTC_WIFI_PNP_SLEEP == pnp_state) || - (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { + if (pnp_state == BTC_WIFI_PNP_SLEEP || + pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify to SLEEP\n"); BTC_TRACE(trace_buf); - /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ - /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ - /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ + /* Sinda 20150819, workaround for driver skip + * leave IPS/LPS to speed up sleep time. + * Driver do not leave IPS/LPS when driver is going to sleep, + * so BTCoexistence think wifi is still under IPS/LPS + * BT should clear UnderIPS/UnderLPS state to avoid mismatch + * state after wakeup. + */ coex_sta->under_ips = FALSE; coex_sta->under_lps = FALSE; - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE | - BT_8821C_2ANT_SCOREBOARD_ONOFF | - BT_8821C_2ANT_SCOREBOARD_SCAN | - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, - FALSE); - - if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { + halbtc8821c2ant_write_scbd(btc, BT_8821C_2ANT_SCBD_ACTIVE | + BT_8821C_2ANT_SCBD_ONOFF | + BT_8821C_2ANT_SCBD_SCAN | + BT_8821C_2ANT_SCBD_UNDERTEST, + FALSE); - if (wifi_under_5g) - halbtc8821c2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_2ANT_PHASE_5G_RUNTIME); + if (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) { + if (wifi_link_info_ext->is_all_under_5g) + phase = BT_8821C_2ANT_PHASE_5G; else - halbtc8821c2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, FORCE_EXEC, - BT_8821C_2ANT_PHASE_2G_RUNTIME); + phase = BT_8821C_2ANT_PHASE_2G; } else { - - halbtc8821c2ant_set_ant_path(btcoexist, - BTC_ANT_PATH_AUTO, - FORCE_EXEC, - BT_8821C_2ANT_PHASE_WLAN_OFF); + phase = BT_8821C_2ANT_PHASE_WOFF; } - } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + + halbtc8821c2ant_set_ant_path(btc, BTC_ANT_PATH_AUTO, FC_EXCU, + phase); + btc->stop_coex_dm = TRUE; + } else { BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify to WAKE UP\n"); BTC_TRACE(trace_buf); -#if 0 - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ACTIVE, TRUE); - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_ONOFF, TRUE); -#endif + coex_sta->wl_pnp_wakeup_downcnt = 3; + + /*WoWLAN*/ + if (pre_pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT || + pnp_state == BTC_WIFI_PNP_WOWLAN) { + coex_sta->run_time_state = TRUE; + btc->stop_coex_dm = FALSE; + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_PNP); + } } + + pre_pnp_state = pnp_state; } -void ex_halbtc8821c2ant_periodical(IN struct btc_coexist *btcoexist) +void ex_halbtc8821c2ant_periodical(struct btc_coexist *btc) { - struct btc_board_info *board_info = &btcoexist->board_info; - boolean wifi_busy = FALSE; - boolean bt_relink_finish = FALSE; + struct coex_sta_8821c_2ant *coex_sta = &btc->coex_sta_8821c_2ant; + struct btc_board_info *board_info = &btc->board_info; + boolean bt_relink_finish = FALSE, is_defreeze = FALSE; + static u8 freeze_cnt; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], ************* Periodical *************\n"); BTC_TRACE(trace_buf); -#if (BT_AUTO_REPORT_ONLY_8821C_2ANT == 0) - halbtc8821c2ant_query_bt_info(btcoexist); -#endif - - halbtc8821c2ant_monitor_bt_ctr(btcoexist); - halbtc8821c2ant_monitor_wifi_ctr(btcoexist); - halbtc8821c2ant_monitor_bt_enable_disable(btcoexist); - -#if 0 - btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + if (!btc->auto_report) + halbtc8821c2ant_query_bt_info(btc); - /* halbtc8821c2ant_read_score_board(btcoexist, &bt_scoreboard_val); */ - - if (wifi_busy) { - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, TRUE); - /* - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_WLBUSY, TRUE); - - if (bt_scoreboard_val & BIT(6)) - halbtc8821c2ant_query_bt_info(btcoexist); */ - } else { - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_UNDERTEST, FALSE); - /* - halbtc8821c2ant_post_state_to_bt(btcoexist, - BT_8821C_2ANT_SCOREBOARD_WLBUSY, - FALSE); */ - } -#endif + halbtc8821c2ant_monitor_bt_ctr(btc); + halbtc8821c2ant_monitor_wifi_ctr(btc); + halbtc8821c2ant_update_wifi_link_info(btc, + BT_8821C_2ANT_RSN_PERIODICAL); + halbtc8821c2ant_monitor_bt_enable(btc); if (coex_sta->bt_relink_downcount != 0) { coex_sta->bt_relink_downcount--; - if (coex_sta->bt_relink_downcount == 0) { - coex_sta->is_setupLink = FALSE; + coex_sta->is_setup_link = FALSE; bt_relink_finish = TRUE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link stop by periodical count-down!!\n"); + BTC_TRACE(trace_buf); + } + } + + if (coex_sta->freeze_coexrun_by_btinfo) { + freeze_cnt++; + + if (freeze_cnt >= 5) { + freeze_cnt = 0; + coex_sta->freeze_coexrun_by_btinfo = FALSE; + is_defreeze = TRUE; } + } else { + freeze_cnt = 0; } /* for 4-way, DHCP, EAPOL packet */ if (coex_sta->specific_pkt_period_cnt > 0) { - coex_sta->specific_pkt_period_cnt--; - if ((coex_sta->specific_pkt_period_cnt == 0) && - (coex_sta->wifi_is_high_pri_task)) - coex_sta->wifi_is_high_pri_task = FALSE; + if (!coex_sta->freeze_coexrun_by_btinfo && + coex_sta->specific_pkt_period_cnt == 0) + coex_sta->wifi_high_pri_task1 = FALSE; BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, - "[BTCoex], ***************** Hi-Pri Task = %s\n", - (coex_sta->wifi_is_high_pri_task ? "Yes" : - "No")); + "[BTCoex], Hi-Pri Task = %s\n", + (coex_sta->wifi_high_pri_task1 ? "Yes" : "No")); BTC_TRACE(trace_buf); - } - if (halbtc8821c2ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish) - || (coex_sta->is_set_ps_state_fail)) - halbtc8821c2ant_run_coexist_mechanism(btcoexist); -} - - -/*#pragma optimize( "", off )*/ -void ex_halbtc8821c2ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) -{ - -} - + if (coex_sta->wl_pnp_wakeup_downcnt > 0) { + coex_sta->wl_pnp_wakeup_downcnt--; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wl_pnp_wakeup_downcnt = %d!!\n", + coex_sta->wl_pnp_wakeup_downcnt); + BTC_TRACE(trace_buf); + } -void ex_halbtc8821c2ant_display_ant_detection(IN struct btc_coexist *btcoexist) -{ + if (coex_sta->cnt_bt_reenable > 0) { + coex_sta->cnt_bt_reenable--; + if (coex_sta->cnt_bt_reenable == 0) { + coex_sta->is_bt_reenable = FALSE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT renable 30s finish!!\n"); + BTC_TRACE(trace_buf); + } + } + if (halbtc8821c2ant_moniter_wifibt_status(btc) || bt_relink_finish || + coex_sta->is_set_ps_state_fail || is_defreeze) + halbtc8821c2ant_run_coex(btc, BT_8821C_2ANT_RSN_PERIODICAL); } - +/*#pragma optimize( "", off )*/ #endif #endif /* #if (RTL8821C_SUPPORT == 1) */ - - diff --git a/hal/btc/halbtc8821c2ant.h b/hal/btc/halbtc8821c2ant.h index 1ac1ff6..1ede998 100644 --- a/hal/btc/halbtc8821c2ant.h +++ b/hal/btc/halbtc8821c2ant.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) @@ -6,497 +20,467 @@ /* ******************************************* * The following is for 8821C 2Ant BT Co-exist definition * ******************************************* */ -#define BT_8821C_2ANT_COEX_DBG 0 -#define BT_AUTO_REPORT_ONLY_8821C_2ANT 1 - - -#define BT_INFO_8821C_2ANT_B_FTP BIT(7) -#define BT_INFO_8821C_2ANT_B_A2DP BIT(6) -#define BT_INFO_8821C_2ANT_B_HID BIT(5) -#define BT_INFO_8821C_2ANT_B_SCO_BUSY BIT(4) -#define BT_INFO_8821C_2ANT_B_ACL_BUSY BIT(3) -#define BT_INFO_8821C_2ANT_B_INQ_PAGE BIT(2) -#define BT_INFO_8821C_2ANT_B_SCO_ESCO BIT(1) -#define BT_INFO_8821C_2ANT_B_CONNECTION BIT(0) - -#define BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT 2 - - -#define BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 80 /* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 42 */ -#define BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 80 /* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 46 */ -#define BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 80 /* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 42 */ -#define BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2 80 /* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 46 */ -#define BT_8821C_2ANT_DEFAULT_ISOLATION 15 /* unit: dB */ -#define BT_8821C_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */ -#define BT_8821C_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */ -#define BT_8821C_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */ -#define BT_8821C_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */ -#define BT_8821C_2ANT_BT_SIR_THRES1 -15 /* unit: dB */ -#define BT_8821C_2ANT_BT_SIR_THRES2 -30 /* unit: dB */ - - -/* for Antenna detection */ -#define BT_8821C_2ANT_ANTDET_PSDTHRES_BACKGROUND 50 -#define BT_8821C_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 -#define BT_8821C_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52 -#define BT_8821C_2ANT_ANTDET_PSDTHRES_1ANT 40 -#define BT_8821C_2ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ -#define BT_8821C_2ANT_ANTDET_SWEEPPOINT_DELAY 60000 -#define BT_8821C_2ANT_ANTDET_ENABLE 0 -#define BT_8821C_2ANT_ANTDET_BTTXTIME 100 -#define BT_8821C_2ANT_ANTDET_BTTXCHANNEL 39 -#define BT_8821C_2ANT_ANTDET_PSD_SWWEEPCOUNT 50 - - -#define BT_8821C_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 +#define BT_8821C_2ANT_COEX_DBG 0 +#define BT_AUTO_REPORT_ONLY_8821C_2ANT 1 + +#define BT_INFO_8821C_2ANT_B_FTP BIT(7) +#define BT_INFO_8821C_2ANT_B_A2DP BIT(6) +#define BT_INFO_8821C_2ANT_B_HID BIT(5) +#define BT_INFO_8821C_2ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8821C_2ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8821C_2ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8821C_2ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8821C_2ANT_B_CONNECTION BIT(0) + +#define BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT 2 + +#define BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 80 +#define BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 80 +#define BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 80 +#define BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2 80 +#define BT_8821C_2ANT_DEFAULT_ISOLATION 15 +#define BT_8821C_2ANT_WIFI_MAX_TX_POWER 15 +#define BT_8821C_2ANT_BT_MAX_TX_POWER 3 +#define BT_8821C_2ANT_WIFI_SIR_THRES1 -15 +#define BT_8821C_2ANT_WIFI_SIR_THRES2 -30 +#define BT_8821C_2ANT_BT_SIR_THRES1 -15 +#define BT_8821C_2ANT_BT_SIR_THRES2 -30 enum bt_8821c_2ant_signal_state { - BT_8821C_2ANT_SIG_STA_SET_TO_LOW = 0x0, - BT_8821C_2ANT_SIG_STA_SET_BY_HW = 0x0, - BT_8821C_2ANT_SIG_STA_SET_TO_HIGH = 0x1, - BT_8821C_2ANT_SIG_STA_MAX + BT_8821C_2ANT_GNT_SET_TO_LOW = 0x0, + BT_8821C_2ANT_GNT_SET_TO_HIGH = 0x1, + BT_8821C_2ANT_GNT_SET_BY_HW = 0x2, + BT_8821C_2ANT_GNT_SET_MAX }; enum bt_8821c_2ant_path_ctrl_owner { BT_8821C_2ANT_PCO_BTSIDE = 0x0, - BT_8821C_2ANT_PCO_WLSIDE = 0x1, + BT_8821C_2ANT_PCO_WLSIDE = 0x1, BT_8821C_2ANT_PCO_MAX }; enum bt_8821c_2ant_gnt_ctrl_type { - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, - BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1, BT_8821C_2ANT_GNT_TYPE_MAX }; enum bt_8821c_2ant_gnt_ctrl_block { BT_8821C_2ANT_GNT_BLOCK_RFC_BB = 0x0, - BT_8821C_2ANT_GNT_BLOCK_RFC = 0x1, - BT_8821C_2ANT_GNT_BLOCK_BB = 0x2, + BT_8821C_2ANT_GNT_BLOCK_RFC = 0x1, + BT_8821C_2ANT_GNT_BLOCK_BB = 0x2, BT_8821C_2ANT_GNT_BLOCK_MAX }; enum bt_8821c_2ant_lte_coex_table_type { - BT_8821C_2ANT_CTT_WL_VS_LTE = 0x0, - BT_8821C_2ANT_CTT_BT_VS_LTE = 0x1, + BT_8821C_2ANT_CTT_WL_VS_LTE = 0x0, + BT_8821C_2ANT_CTT_BT_VS_LTE = 0x1, BT_8821C_2ANT_CTT_MAX }; enum bt_8821c_2ant_lte_break_table_type { - BT_8821C_2ANT_LBTT_WL_BREAK_LTE = 0x0, - BT_8821C_2ANT_LBTT_BT_BREAK_LTE = 0x1, - BT_8821C_2ANT_LBTT_LTE_BREAK_WL = 0x2, - BT_8821C_2ANT_LBTT_LTE_BREAK_BT = 0x3, + BT_8821C_2ANT_LBTT_WL_BREAK_LTE = 0x0, + BT_8821C_2ANT_LBTT_BT_BREAK_LTE = 0x1, + BT_8821C_2ANT_LBTT_LTE_BREAK_WL = 0x2, + BT_8821C_2ANT_LBTT_LTE_BREAK_BT = 0x3, BT_8821C_2ANT_LBTT_MAX }; enum bt_info_src_8821c_2ant { - BT_INFO_SRC_8821C_2ANT_WIFI_FW = 0x0, - BT_INFO_SRC_8821C_2ANT_BT_RSP = 0x1, - BT_INFO_SRC_8821C_2ANT_BT_ACTIVE_SEND = 0x2, - BT_INFO_SRC_8821C_2ANT_MAX + BT_8821C_2ANT_INFO_SRC_WIFI_FW = 0x0, + BT_8821C_2ANT_INFO_SRC_BT_RSP = 0x1, + BT_8821C_2ANT_INFO_SRC_BT_ACT = 0x2, + BT_8821C_2ANT_INFO_SRC_MAX }; enum bt_8821c_2ant_bt_status { - BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, - BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, - BT_8821C_2ANT_BT_STATUS_INQ_PAGE = 0x2, - BT_8821C_2ANT_BT_STATUS_ACL_BUSY = 0x3, - BT_8821C_2ANT_BT_STATUS_SCO_BUSY = 0x4, - BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, - BT_8821C_2ANT_BT_STATUS_MAX + BT_8821C_2ANT_BSTATUS_NCON_IDLE = 0x0, + BT_8821C_2ANT_BSTATUS_CON_IDLE = 0x1, + BT_8821C_2ANT_BSTATUS_INQ_PAGE = 0x2, + BT_8821C_2ANT_BSTATUS_ACL_BUSY = 0x3, + BT_8821C_2ANT_BSTATUS_SCO_BUSY = 0x4, + BT_8821C_2ANT_BSTATUS_ACL_SCO_BUSY = 0x5, + BT_8821C_2ANT_BSTATUS_MAX }; enum bt_8821c_2ant_coex_algo { - BT_8821C_2ANT_COEX_ALGO_UNDEFINED = 0x0, - BT_8821C_2ANT_COEX_ALGO_SCO = 0x1, - BT_8821C_2ANT_COEX_ALGO_HID = 0x2, - BT_8821C_2ANT_COEX_ALGO_A2DP = 0x3, - BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, - BT_8821C_2ANT_COEX_ALGO_PANEDR = 0x5, - BT_8821C_2ANT_COEX_ALGO_PANHS = 0x6, - BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, - BT_8821C_2ANT_COEX_ALGO_PANEDR_HID = 0x8, - BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, - BT_8821C_2ANT_COEX_ALGO_HID_A2DP = 0xa, - BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY = 0xb, - BT_8821C_2ANT_COEX_ALGO_A2DPSINK = 0xc, - BT_8821C_2ANT_COEX_ALGO_MAX + BT_8821C_2ANT_COEX_UNDEFINED = 0x0, + BT_8821C_2ANT_COEX_SCO = 0x1, + BT_8821C_2ANT_COEX_HID = 0x2, + BT_8821C_2ANT_COEX_A2DP = 0x3, + BT_8821C_2ANT_COEX_A2DP_PANHS = 0x4, + BT_8821C_2ANT_COEX_PAN = 0x5, + BT_8821C_2ANT_COEX_PANHS = 0x6, + BT_8821C_2ANT_COEX_PAN_A2DP = 0x7, + BT_8821C_2ANT_COEX_PAN_HID = 0x8, + BT_8821C_2ANT_COEX_HID_A2DP_PAN = 0x9, + BT_8821C_2ANT_COEX_HID_A2DP = 0xa, + BT_8821C_2ANT_COEX_NOPROFILEBUSY = 0xb, + BT_8821C_2ANT_COEX_A2DPSINK = 0xc, + BT_8821C_2ANT_COEX_MAX }; enum bt_8821c_2ant_ext_ant_switch_type { - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0, - BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1, - BT_8821C_2ANT_EXT_ANT_SWITCH_NONE = 0x2, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAX + BT_8821C_2ANT_USE_DPDT = 0x0, + BT_8821C_2ANT_USE_SPDT = 0x1, + BT_8821C_2ANT_SWITCH_NONE = 0x2, + BT_8821C_2ANT_SWITCH_MAX }; enum bt_8821c_2ant_ext_ant_switch_ctrl_type { - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, - BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_MAX + BT_8821C_2ANT_CTRL_BY_BBSW = 0x0, + BT_8821C_2ANT_CTRL_BY_PTA = 0x1, + BT_8821C_2ANT_CTRL_BY_ANTDIV = 0x2, + BT_8821C_2ANT_CTRL_BY_MAC = 0x3, + BT_8821C_2ANT_CTRL_BY_BT = 0x4, + BT_8821C_2ANT_CTRL_BY_FW = 0x5, + BT_8821C_2ANT_CTRL_MAX }; enum bt_8821c_2ant_ext_ant_switch_pos_type { - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT = 0x0, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG = 0x1, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA = 0x2, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE = 0x3, - BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_MAX -}; - -enum bt_8821c_2ant_ext_band_switch_pos_type { - BT_8821C_2ANT_EXT_BAND_SWITCH_TO_WLG = 0x0, - BT_8821C_2ANT_EXT_BAND_SWITCH_TO_WLA = 0x1, - BT_8821C_2ANT_EXT_BAND_SWITCH_TO_MAX -}; - -enum bt_8821c_2ant_int_block { - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2, - BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_MAX + BT_8821C_2ANT_TO_BT = 0x0, + BT_8821C_2ANT_TO_WLG = 0x1, + BT_8821C_2ANT_TO_WLA = 0x2, + BT_8821C_2ANT_TO_NOCARE = 0x3, + BT_8821C_2ANT_TO_MAX }; enum bt_8821c_2ant_phase { - BT_8821C_2ANT_PHASE_COEX_INIT = 0x0, - BT_8821C_2ANT_PHASE_WLANONLY_INIT = 0x1, - BT_8821C_2ANT_PHASE_WLAN_OFF = 0x2, - BT_8821C_2ANT_PHASE_2G_RUNTIME = 0x3, - BT_8821C_2ANT_PHASE_5G_RUNTIME = 0x4, - BT_8821C_2ANT_PHASE_BTMPMODE = 0x5, - BT_8821C_2ANT_PHASE_ANTENNA_DET = 0x6, - BT_8821C_2ANT_PHASE_COEX_POWERON = 0x7, - BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT = 0x8, + BT_8821C_2ANT_PHASE_INIT = 0x0, + BT_8821C_2ANT_PHASE_WONLY = 0x1, + BT_8821C_2ANT_PHASE_WOFF = 0x2, + BT_8821C_2ANT_PHASE_2G = 0x3, + BT_8821C_2ANT_PHASE_5G = 0x4, + BT_8821C_2ANT_PHASE_BTMP = 0x5, + BT_8821C_2ANT_PHASE_ANTDET = 0x6, + BT_8821C_2ANT_PHASE_POWERON = 0x7, BT_8821C_2ANT_PHASE_MAX }; -enum bt_8821c_2ant_Scoreboard { - BT_8821C_2ANT_SCOREBOARD_ACTIVE = BIT(0), - BT_8821C_2ANT_SCOREBOARD_ONOFF = BIT(1), - BT_8821C_2ANT_SCOREBOARD_SCAN = BIT(2), - BT_8821C_2ANT_SCOREBOARD_UNDERTEST = BIT(3), - BT_8821C_2ANT_SCOREBOARD_WLBUSY = BIT(6) +enum bt_8821c_2ant_scoreboard { + BT_8821C_2ANT_SCBD_ACTIVE = BIT(0), + BT_8821C_2ANT_SCBD_ONOFF = BIT(1), + BT_8821C_2ANT_SCBD_SCAN = BIT(2), + BT_8821C_2ANT_SCBD_UNDERTEST = BIT(3), + BT_8821C_2ANT_SCBD_RXGAIN = BIT(4), + BT_8821C_2ANT_SCBD_WLBUSY = BIT(6), + BT_8821C_2ANT_SCBD_BTCQDDR = BIT(10) }; +enum bt_8821c_2ant_RUNREASON { + BT_8821C_2ANT_RSN_2GSCANSTART = 0x0, + BT_8821C_2ANT_RSN_5GSCANSTART = 0x1, + BT_8821C_2ANT_RSN_SCANFINISH = 0x2, + BT_8821C_2ANT_RSN_2GSWITCHBAND = 0x3, + BT_8821C_2ANT_RSN_5GSWITCHBAND = 0x4, + BT_8821C_2ANT_RSN_2GCONSTART = 0x5, + BT_8821C_2ANT_RSN_5GCONSTART = 0x6, + BT_8821C_2ANT_RSN_2GCONFINISH = 0x7, + BT_8821C_2ANT_RSN_5GCONFINISH = 0x8, + BT_8821C_2ANT_RSN_2GMEDIA = 0x9, + BT_8821C_2ANT_RSN_5GMEDIA = 0xa, + BT_8821C_2ANT_RSN_MEDIADISCON = 0xb, + BT_8821C_2ANT_RSN_2GSPECIALPKT = 0xc, + BT_8821C_2ANT_RSN_5GSPECIALPKT = 0xd, + BT_8821C_2ANT_RSN_BTINFO = 0xe, + BT_8821C_2ANT_RSN_PERIODICAL = 0xf, + BT_8821C_2ANT_RSN_PNP = 0x10, + BT_8821C_2ANT_RSN_MAX +}; +enum bt_8821c_2ant_WL_LINK_MODE { + BT_8821C_2ANT_WLINK_2G1PORT = 0x0, + BT_8821C_2ANT_WLINK_2GMPORT = 0x1, + BT_8821C_2ANT_WLINK_25GMPORT = 0x2, + BT_8821C_2ANT_WLINK_5G = 0x3, + BT_8821C_2ANT_WLINK_2GGO = 0x4, + BT_8821C_2ANT_WLINK_BTMR = 0x5, + BT_8821C_2ANT_WLINK_MAX +}; struct coex_dm_8821c_2ant { /* hw setting */ - u32 pre_ant_pos_type; u32 cur_ant_pos_type; /* fw mechanism */ - u8 pre_bt_dec_pwr_lvl; - u8 cur_bt_dec_pwr_lvl; - u8 pre_fw_dac_swing_lvl; - u8 cur_fw_dac_swing_lvl; + + u8 cur_bt_pwr_lvl; + u8 cur_wl_pwr_lvl; + boolean cur_ignore_wlan_act; - boolean pre_ignore_wlan_act; - u8 pre_ps_tdma; + u8 cur_ps_tdma; u8 ps_tdma_para[5]; - u8 ps_tdma_du_adj_type; boolean reset_tdma_adjust; - boolean pre_ps_tdma_on; boolean cur_ps_tdma_on; - boolean pre_bt_auto_report; boolean cur_bt_auto_report; /* sw mechanism */ - boolean pre_rf_rx_lpf_shrink; - boolean cur_rf_rx_lpf_shrink; - u32 bt_rf_0x1e_backup; - boolean pre_low_penalty_ra; boolean cur_low_penalty_ra; - boolean pre_dac_swing_on; - u32 pre_dac_swing_lvl; - boolean cur_dac_swing_on; - u32 cur_dac_swing_lvl; - boolean pre_adc_back_off; - boolean cur_adc_back_off; - boolean pre_agc_table_en; - boolean cur_agc_table_en; - u32 pre_val0x6c0; + u32 cur_val0x6c0; - u32 pre_val0x6c4; u32 cur_val0x6c4; - u32 pre_val0x6c8; u32 cur_val0x6c8; - u8 pre_val0x6cc; u8 cur_val0x6cc; - boolean limited_dig; /* algorithm related */ - u8 pre_algorithm; u8 cur_algorithm; u8 bt_status; u8 wifi_chnl_info[3]; - boolean need_recover0x948; - u32 backup0x948; - - u8 pre_lps; u8 cur_lps; - u8 pre_rpwm; u8 cur_rpwm; boolean is_switch_to_1dot5_ant; - u8 switch_thres_offset; - u32 arp_cnt; + u32 arp_cnt; - u32 pre_ext_ant_switch_status; u32 cur_ext_ant_switch_status; - u8 pre_ext_band_switch_status; - u8 cur_ext_band_switch_status; - - u8 pre_int_block_status; - u8 cur_int_block_status; + u8 cur_antdiv_type; + u32 setting_tdma; }; struct coex_sta_8821c_2ant { - boolean bt_disabled; - boolean bt_link_exist; - boolean sco_exist; - boolean a2dp_exist; - boolean hid_exist; - boolean pan_exist; - - boolean under_lps; - boolean under_ips; - u32 high_priority_tx; - u32 high_priority_rx; - u32 low_priority_tx; - u32 low_priority_rx; - boolean is_hiPri_rx_overhead; - u8 bt_rssi; - u8 pre_bt_rssi_state; - u8 pre_wifi_rssi_state[4]; - u8 bt_info_c2h[BT_INFO_SRC_8821C_2ANT_MAX][10]; - u32 bt_info_c2h_cnt[BT_INFO_SRC_8821C_2ANT_MAX]; - boolean bt_whck_test; - boolean c2h_bt_inquiry_page; - boolean c2h_bt_remote_name_req; - - u8 bt_info_ext; - u8 bt_info_ext2; - u32 pop_event_cnt; - u8 scan_ap_num; - u8 bt_retry_cnt; - - u32 crc_ok_cck; - u32 crc_ok_11g; - u32 crc_ok_11n; - u32 crc_ok_11n_vht; - - u32 crc_err_cck; - u32 crc_err_11g; - u32 crc_err_11n; - u32 crc_err_11n_vht; - - u32 acc_crc_ratio; - u32 now_crc_ratio; - - boolean cck_lock; - boolean pre_ccklock; - boolean cck_ever_lock; - - u8 coex_table_type; - boolean force_lps_ctrl; - - u8 dis_ver_info_cnt; - - u8 a2dp_bit_pool; - u8 cut_version; - - boolean concurrent_rx_mode_on; - - u16 score_board; - u8 isolation_btween_wb; /* 0~ 50 */ - u8 wifi_coex_thres; - u8 bt_coex_thres; - u8 wifi_coex_thres2; - u8 bt_coex_thres2; - - u8 num_of_profile; - boolean acl_busy; - boolean bt_create_connection; - boolean wifi_is_high_pri_task; - u32 specific_pkt_period_cnt; - u32 bt_coex_supported_feature; - u32 bt_coex_supported_version; - - u8 bt_ble_scan_type; - u32 bt_ble_scan_para[3]; - - boolean run_time_state; - boolean freeze_coexrun_by_btinfo; - - boolean is_A2DP_3M; - boolean voice_over_HOGP; - u8 bt_info; - boolean is_autoslot; - u8 forbidden_slot; - u8 hid_busy_num; - u8 hid_pair_cnt; - - u32 cnt_RemoteNameReq; - u32 cnt_setupLink; - u32 cnt_ReInit; - u32 cnt_IgnWlanAct; - u32 cnt_Page; - u32 cnt_RoleSwitch; - - u16 bt_reg_vendor_ac; - u16 bt_reg_vendor_ae; - - boolean is_setupLink; - u8 wl_noisy_level; - u32 gnt_error_cnt; - - u8 bt_afh_map[10]; - u8 bt_relink_downcount; - boolean is_tdma_btautoslot; - boolean is_tdma_btautoslot_hang; - - boolean is_eSCO_mode; - u8 switch_band_notify_to; - boolean is_rf_state_off; - - boolean is_hid_low_pri_tx_overhead; - boolean is_bt_multi_link; - boolean is_bt_a2dp_sink; - boolean is_set_ps_state_fail; - u8 cnt_set_ps_state_fail; + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + boolean msft_mr_exist; + + boolean under_lps; + boolean under_ips; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + boolean is_hi_pri_rx_overhead; + u8 bt_rssi; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + u8 bt_info_c2h[BT_8821C_2ANT_INFO_SRC_MAX][10]; + u32 bt_info_c2h_cnt[BT_8821C_2ANT_INFO_SRC_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + + u8 bt_info_ext; + u8 bt_info_ext2; + u32 pop_event_cnt; + u8 scan_ap_num; + u8 bt_retry_cnt; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + u32 cnt_crcok_max_in_10s; + + boolean cck_lock; + boolean cck_lock_ever; + boolean cck_lock_warn; + + u8 coex_table_type; + boolean force_lps_ctrl; + + u8 dis_ver_info_cnt; + + u8 a2dp_bit_pool; + u8 cut_version; + + boolean concurrent_rx_mode_on; + + u16 score_board; + u8 isolation_btween_wb; /* 0~ 50 */ + u8 wifi_coex_thres; + u8 bt_coex_thres; + u8 wifi_coex_thres2; + u8 bt_coex_thres2; + + u8 num_of_profile; + boolean acl_busy; + boolean bt_create_connection; + + boolean wifi_high_pri_task1; + boolean wifi_high_pri_task2; + + u32 specific_pkt_period_cnt; + u32 bt_coex_supported_feature; + u32 bt_coex_supported_version; + + u8 bt_ble_scan_type; + u32 bt_ble_scan_para[3]; + + boolean run_time_state; + boolean freeze_coexrun_by_btinfo; + + boolean is_A2DP_3M; + boolean voice_over_HOGP; + u8 bt_info; + boolean is_autoslot; + u8 forbidden_slot; + u8 hid_busy_num; + u8 hid_pair_cnt; + + u32 cnt_remote_name_req; + u32 cnt_setup_link; + u32 cnt_reinit; + u32 cnt_ign_wlan_act; + u32 cnt_page; + u32 cnt_role_switch; + + u16 bt_reg_vendor_ac; + u16 bt_reg_vendor_ae; + + boolean is_setup_link; + u8 wl_noisy_level; + u32 gnt_error_cnt; + + u8 bt_afh_map[10]; + u8 bt_relink_downcount; + boolean is_tdma_btautoslot; + boolean is_tdma_btautoslot_hang; + + boolean is_esco_mode; + u8 switch_band_notify_to; + boolean is_rf_state_off; + + boolean is_hid_low_pri_tx_overhead; + boolean is_bt_multi_link; + boolean is_bt_a2dp_sink; + boolean is_set_ps_state_fail; + u8 cnt_set_ps_state_fail; + + u8 wl_fw_dbg_info[10]; + u8 wl_rx_rate; + u8 wl_tx_rate; + u8 wl_rts_rx_rate; + u8 wl_center_channel; + u8 wl_tx_macid; + u8 wl_tx_retry_ratio; + + u16 score_board_WB; + boolean is_hid_rcu; + u16 legacy_forbidden_slot; + u16 le_forbidden_slot; + u8 bt_a2dp_vendor_id; + u32 bt_a2dp_device_name; + boolean is_ble_scan_en; + + boolean is_bt_opp_exist; + boolean gl_wifi_busy; + u8 connect_ap_period_cnt; + + boolean is_bt_reenable; + u8 cnt_bt_reenable; + boolean is_wifi_linkscan_process; + u8 wl_coex_mode; + u8 wl_pnp_wakeup_downcnt; + u32 coex_run_cnt; }; - #define BT_8821C_2ANT_EXT_BAND_SWITCH_USE_DPDT 0 #define BT_8821C_2ANT_EXT_BAND_SWITCH_USE_SPDT 1 - struct rfe_type_8821c_2ant { - - u8 rfe_module_type; + u8 rfe_module_type; boolean ext_ant_switch_exist; - u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ - u8 ext_ant_switch_ctrl_polarity; /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ + /* 0:DPDT, 1:SPDT */ + u8 ext_ant_switch_type; + /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ + u8 ext_ant_switch_ctrl_polarity; boolean ext_band_switch_exist; - u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */ - u8 ext_band_switch_ctrl_polarity; + /* 0:DPDT, 1:SPDT */ + u8 ext_band_switch_type; + u8 ext_band_switch_ctrl_polarity; boolean ant_at_main_port; - boolean wlg_Locate_at_btg; /* If TRUE: WLG at BTG, If FALSE: WLG at WLAG */ + /* If TRUE: WLG at BTG, If FALSE: WLG at WLAG */ + boolean wlg_locate_at_btg; - boolean ext_ant_switch_diversity; /* If diversity on */ + /* If diversity on */ + boolean ext_ant_switch_diversity; }; -#define BT_8821C_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ -#define BT_8821C_2ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ -#define BT_8821C_2ANT_ANTDET_BUF_LEN 16 - -struct psdscan_sta_8821c_2ant { - - u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ - u32 ant_det_bt_tx_time; - u32 ant_det_pre_psdscan_peak_val; - boolean ant_det_is_ant_det_available; - u32 ant_det_psd_scan_peak_val; - boolean ant_det_is_btreply_available; - u32 ant_det_psd_scan_peak_freq; - - u8 ant_det_result; - u8 ant_det_peak_val[BT_8821C_2ANT_ANTDET_BUF_LEN]; - u8 ant_det_peak_freq[BT_8821C_2ANT_ANTDET_BUF_LEN]; - u32 ant_det_try_count; - u32 ant_det_fail_count; - u32 ant_det_inteval_count; - u32 ant_det_thres_offset; - - u32 real_cent_freq; - s32 real_offset; - u32 real_span; - - u32 psd_band_width; /* unit: Hz */ - u32 psd_point; /* 128/256/512/1024 */ - u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ - u32 psd_start_point; - u32 psd_stop_point; - u32 psd_max_value_point; - u32 psd_max_value; - u32 psd_max_value2; - u32 psd_avg_value; /* filter loop_max_value that below BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ - u32 psd_loop_max_value[BT_8821C_2ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ - u32 psd_start_base; - u32 psd_avg_num; /* 1/8/16/32 */ - u32 psd_gen_count; - boolean is_AntDet_running; - boolean is_psd_show_max_only; +struct wifi_link_info_8821c_2ant { + u8 num_of_active_port; + u32 port_connect_status; + boolean is_all_under_5g; + boolean is_mcc_25g; + boolean is_p2p_connected; }; - /* ******************************************* * The following is interface which will notify coex module. * ******************************************* */ -void ex_halbtc8821c2ant_power_on_setting(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, - IN boolean wifi_only); -void ex_halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_ips_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_lps_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_scan_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_switchband_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_connect_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_media_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, - IN u8 *tmp_buf, IN u8 length); -void ex_halbtc8821c2ant_rf_status_notify(IN struct btc_coexist *btcoexist, - IN u8 type); -void ex_halbtc8821c2ant_halt_notify(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_pnp_notify(IN struct btc_coexist *btcoexist, - IN u8 pnp_state); -void ex_halbtc8821c2ant_periodical(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist); -void ex_halbtc8821c2ant_antenna_detection(IN struct btc_coexist *btcoexist, - IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); -void ex_halbtc8821c2ant_display_ant_detection(IN struct btc_coexist *btcoexist); - +void ex_halbtc8821c2ant_power_on_setting(struct btc_coexist *btc); +void ex_halbtc8821c2ant_pre_load_firmware(struct btc_coexist *btc); +void ex_halbtc8821c2ant_init_hw_config(struct btc_coexist *btc, + boolean wifi_only); +void ex_halbtc8821c2ant_init_coex_dm(struct btc_coexist *btc); +void ex_halbtc8821c2ant_ips_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c2ant_lps_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c2ant_scan_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c2ant_switchband_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c2ant_connect_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c2ant_media_status_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c2ant_specific_packet_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c2ant_bt_info_notify(struct btc_coexist *btc, + u8 *tmp_buf, u8 length); +void ex_halbtc8821c2ant_wl_fwdbginfo_notify(struct btc_coexist *btc, + u8 *tmp_buf, u8 length); +void ex_halbtc8821c2ant_rx_rate_change_notify(struct btc_coexist *btc, + BOOLEAN is_data_frame, + u8 btc_rate_id); +void ex_halbtc8821c2ant_tx_rate_change_notify(struct btc_coexist *btc, + u8 tx_rate, + u8 tx_retry_ratio, u8 macid); +void ex_halbtc8821c2ant_rf_status_notify(struct btc_coexist *btc, + u8 type); +void ex_halbtc8821c2ant_halt_notify(struct btc_coexist *btc); +void ex_halbtc8821c2ant_pnp_notify(struct btc_coexist *btc, + u8 pnp_state); +void ex_halbtc8821c2ant_periodical(struct btc_coexist *btc); +void ex_halbtc8821c2ant_display_simple_coex_info(struct btc_coexist *btc); +void ex_halbtc8821c2ant_display_coex_info(struct btc_coexist *btc); #else -#define ex_halbtc8821c2ant_power_on_setting(btcoexist) -#define ex_halbtc8821c2ant_pre_load_firmware(btcoexist) -#define ex_halbtc8821c2ant_init_hw_config(btcoexist, wifi_only) -#define ex_halbtc8821c2ant_init_coex_dm(btcoexist) -#define ex_halbtc8821c2ant_ips_notify(btcoexist, type) -#define ex_halbtc8821c2ant_lps_notify(btcoexist, type) -#define ex_halbtc8821c2ant_scan_notify(btcoexist, type) -#define ex_halbtc8821c2ant_switchband_notify(btcoexist,type) -#define ex_halbtc8821c2ant_connect_notify(btcoexist, type) -#define ex_halbtc8821c2ant_media_status_notify(btcoexist, type) -#define ex_halbtc8821c2ant_specific_packet_notify(btcoexist, type) -#define ex_halbtc8821c2ant_bt_info_notify(btcoexist, tmp_buf, length) -#define ex_halbtc8821c2ant_rf_status_notify(btcoexist, type) -#define ex_halbtc8821c2ant_halt_notify(btcoexist) -#define ex_halbtc8821c2ant_pnp_notify(btcoexist, pnp_state) -#define ex_halbtc8821c2ant_periodical(btcoexist) -#define ex_halbtc8821c2ant_display_coex_info(btcoexist) -#define ex_halbtc8821c2ant_display_ant_detection(btcoexist) -#define ex_halbtc8821c2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds) +#define ex_halbtc8821c2ant_power_on_setting(btc) +#define ex_halbtc8821c2ant_pre_load_firmware(btc) +#define ex_halbtc8821c2ant_init_hw_config(btc, wifi_only) +#define ex_halbtc8821c2ant_init_coex_dm(btc) +#define ex_halbtc8821c2ant_ips_notify(btc, type) +#define ex_halbtc8821c2ant_lps_notify(btc, type) +#define ex_halbtc8821c2ant_scan_notify(btc, type) +#define ex_halbtc8821c2ant_switchband_notify(btc, type) +#define ex_halbtc8821c2ant_connect_notify(btc, type) +#define ex_halbtc8821c2ant_media_status_notify(btc, type) +#define ex_halbtc8821c2ant_specific_packet_notify(btc, type) +#define ex_halbtc8821c2ant_bt_info_notify(btc, tmp_buf, length) +#define ex_halbtc8821c2ant_wl_fwdbginfo_notify(btc, tmp_buf, length) +#define ex_halbtc8821c2ant_rx_rate_change_notify(btc, is_data_frame, \ + btc_rate_id) +#define ex_halbtc8821c2ant_tx_rate_change_notify(btcoexist, tx_rate, \ + tx_retry_ratio, macid) +#define ex_halbtc8821c2ant_rf_status_notify(btc, type) +#define ex_halbtc8821c2ant_halt_notify(btc) +#define ex_halbtc8821c2ant_pnp_notify(btc, pnp_state) +#define ex_halbtc8821c2ant_periodical(btc) +#define ex_halbtc8821c2ant_display_simple_coex_info(btc) +#define ex_halbtc8821c2ant_display_coex_info(btc) #endif #endif diff --git a/hal/btc/halbtc8821cwifionly.c b/hal/btc/halbtc8821cwifionly.c index 6de8db0..07693f5 100755 --- a/hal/btc/halbtc8821cwifionly.c +++ b/hal/btc/halbtc8821cwifionly.c @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #include "mp_precomp.h" static struct rfe_type_8821c_wifi_only gl_rfe_type_8821c_1ant; @@ -164,6 +178,9 @@ ex_hal8821c_wifi_only_hw_config( /*gnt_wl=1 , gnt_bt=0*/ halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700); halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); + + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x6c0, 0xffffffff, 0xaaaaaaaa); + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x6c4, 0xffffffff, 0xaaaaaaaa); } VOID @@ -184,3 +201,13 @@ ex_hal8821c_wifi_only_switchbandnotify( hal8821c_wifi_only_switch_antenna(pwifionlycfg, is_5g); } +VOID +ex_hal8821c_wifi_only_connectnotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ) +{ + hal8821c_wifi_only_switch_antenna(pwifionlycfg, is_5g); +} + + diff --git a/hal/btc/halbtc8821cwifionly.h b/hal/btc/halbtc8821cwifionly.h index afa2b2f..dfcc5de 100755 --- a/hal/btc/halbtc8821cwifionly.h +++ b/hal/btc/halbtc8821cwifionly.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __INC_HAL8821CWIFIONLYHWCFG_H #define __INC_HAL8821CWIFIONLYHWCFG_H @@ -63,6 +77,11 @@ ex_hal8821c_wifi_only_scannotify( IN u1Byte is_5g ); VOID +ex_hal8821c_wifi_only_connectnotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ); +VOID ex_hal8821c_wifi_only_switchbandnotify( IN struct wifi_only_cfg *pwifionlycfg, IN u1Byte is_5g diff --git a/hal/btc/halbtcoutsrc.h b/hal/btc/halbtcoutsrc.h index 2a6ff26..9eee929 100644 --- a/hal/btc/halbtcoutsrc.h +++ b/hal/btc/halbtcoutsrc.h @@ -1,6 +1,120 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __HALBTC_OUT_SRC_H__ #define __HALBTC_OUT_SRC_H__ +enum { + BTC_CCK_1, + BTC_CCK_2, + BTC_CCK_5_5, + BTC_CCK_11, + BTC_OFDM_6, + BTC_OFDM_9, + BTC_OFDM_12, + BTC_OFDM_18, + BTC_OFDM_24, + BTC_OFDM_36, + BTC_OFDM_48, + BTC_OFDM_54, + BTC_MCS_0, + BTC_MCS_1, + BTC_MCS_2, + BTC_MCS_3, + BTC_MCS_4, + BTC_MCS_5, + BTC_MCS_6, + BTC_MCS_7, + BTC_MCS_8, + BTC_MCS_9, + BTC_MCS_10, + BTC_MCS_11, + BTC_MCS_12, + BTC_MCS_13, + BTC_MCS_14, + BTC_MCS_15, + BTC_MCS_16, + BTC_MCS_17, + BTC_MCS_18, + BTC_MCS_19, + BTC_MCS_20, + BTC_MCS_21, + BTC_MCS_22, + BTC_MCS_23, + BTC_MCS_24, + BTC_MCS_25, + BTC_MCS_26, + BTC_MCS_27, + BTC_MCS_28, + BTC_MCS_29, + BTC_MCS_30, + BTC_MCS_31, + BTC_VHT_1SS_MCS_0, + BTC_VHT_1SS_MCS_1, + BTC_VHT_1SS_MCS_2, + BTC_VHT_1SS_MCS_3, + BTC_VHT_1SS_MCS_4, + BTC_VHT_1SS_MCS_5, + BTC_VHT_1SS_MCS_6, + BTC_VHT_1SS_MCS_7, + BTC_VHT_1SS_MCS_8, + BTC_VHT_1SS_MCS_9, + BTC_VHT_2SS_MCS_0, + BTC_VHT_2SS_MCS_1, + BTC_VHT_2SS_MCS_2, + BTC_VHT_2SS_MCS_3, + BTC_VHT_2SS_MCS_4, + BTC_VHT_2SS_MCS_5, + BTC_VHT_2SS_MCS_6, + BTC_VHT_2SS_MCS_7, + BTC_VHT_2SS_MCS_8, + BTC_VHT_2SS_MCS_9, + BTC_VHT_3SS_MCS_0, + BTC_VHT_3SS_MCS_1, + BTC_VHT_3SS_MCS_2, + BTC_VHT_3SS_MCS_3, + BTC_VHT_3SS_MCS_4, + BTC_VHT_3SS_MCS_5, + BTC_VHT_3SS_MCS_6, + BTC_VHT_3SS_MCS_7, + BTC_VHT_3SS_MCS_8, + BTC_VHT_3SS_MCS_9, + BTC_VHT_4SS_MCS_0, + BTC_VHT_4SS_MCS_1, + BTC_VHT_4SS_MCS_2, + BTC_VHT_4SS_MCS_3, + BTC_VHT_4SS_MCS_4, + BTC_VHT_4SS_MCS_5, + BTC_VHT_4SS_MCS_6, + BTC_VHT_4SS_MCS_7, + BTC_VHT_4SS_MCS_8, + BTC_VHT_4SS_MCS_9, + BTC_MCS_32, + BTC_UNKNOWN, + BTC_PKT_MGNT, + BTC_PKT_CTRL, + BTC_PKT_UNKNOWN, + BTC_PKT_NOT_FOR_ME, + BTC_RATE_MAX +}; + +enum { + BTC_MULTIPORT_SCC, + BTC_MULTIPORT_MCC_DUAL_CHANNEL, + BTC_MULTIPORT_MCC_DUAL_BAND, + BTC_MULTIPORT_MAX +}; #define BTC_COEX_OFFLOAD 0 #define BTC_TMP_BUF_SHORT 20 @@ -19,6 +133,9 @@ do {\ #define NORMAL_EXEC FALSE #define FORCE_EXEC TRUE +#define NM_EXCU FALSE +#define FC_EXCU TRUE + #define BTC_RF_OFF 0x0 #define BTC_RF_ON 0x1 @@ -100,6 +217,7 @@ typedef enum _BTC_CHIP_TYPE { /* following is for command line utility */ #define CL_SPRINTF rsprintf #define CL_PRINTF DCMD_Printf +#define CL_STRNCAT(dst, dst_size, src, src_size) rstrncat(dst, src, src_size) struct btc_board_info { /* The following is some board information */ @@ -119,6 +237,8 @@ struct btc_board_info { u8 ant_det_result; boolean ant_det_result_five_complete; u32 antdetval; + u8 customerID; + u8 customer_id; }; typedef enum _BTC_DBG_OPCODE { @@ -156,6 +276,7 @@ typedef enum _BTC_WIFI_ROLE { typedef enum _BTC_WIRELESS_FREQ { BTC_FREQ_2_4G = 0x0, BTC_FREQ_5G = 0x1, + BTC_FREQ_25G = 0x2, BTC_FREQ_MAX } BTC_WIRELESS_FREQ, *PBTC_WIRELESS_FREQ; @@ -178,6 +299,7 @@ typedef enum _BTC_WIFI_PNP { BTC_WIFI_PNP_WAKE_UP = 0x0, BTC_WIFI_PNP_SLEEP = 0x1, BTC_WIFI_PNP_SLEEP_KEEP_ANT = 0x2, + BTC_WIFI_PNP_WOWLAN = 0x3, BTC_WIFI_PNP_MAX } BTC_WIFI_PNP, *PBTC_WIFI_PNP; @@ -237,6 +359,8 @@ typedef enum _BTC_GET_TYPE { BTC_GET_BL_HS_CONNECTING, BTC_GET_BL_WIFI_FW_READY, BTC_GET_BL_WIFI_CONNECTED, + BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED, + BTC_GET_BL_WIFI_LINK_INFO, BTC_GET_BL_WIFI_BUSY, BTC_GET_BL_WIFI_SCAN, BTC_GET_BL_WIFI_LINK, @@ -250,6 +374,7 @@ typedef enum _BTC_GET_TYPE { BTC_GET_BL_WIFI_IS_IN_MP_MODE, BTC_GET_BL_IS_ASUS_8723B, BTC_GET_BL_RF4CE_CONNECTED, + BTC_GET_BL_WIFI_LW_PWR_STATE, /* type s4Byte */ BTC_GET_S4_WIFI_RSSI, @@ -264,6 +389,8 @@ typedef enum _BTC_GET_TYPE { BTC_GET_U4_VENDOR, BTC_GET_U4_SUPPORTED_VERSION, BTC_GET_U4_SUPPORTED_FEATURE, + BTC_GET_U4_BT_DEVICE_INFO, + BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL, BTC_GET_U4_WIFI_IQK_TOTAL, BTC_GET_U4_WIFI_IQK_OK, BTC_GET_U4_WIFI_IQK_FAIL, @@ -278,6 +405,9 @@ typedef enum _BTC_GET_TYPE { BTC_GET_U1_ANT_TYPE, BTC_GET_U1_IOT_PEER, + /* type u2Byte */ + BTC_GET_U2_BEACON_PERIOD, + /*===== for 1Ant ======*/ BTC_GET_U1_LPS_MODE, @@ -297,6 +427,7 @@ typedef enum _BTC_SET_TYPE { BTC_SET_BL_INC_SCAN_DEV_NUM, BTC_SET_BL_BT_TX_RX_MASK, BTC_SET_BL_MIRACAST_PLUS_BT, + BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL, /* type u1Byte */ BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, @@ -306,6 +437,9 @@ typedef enum _BTC_SET_TYPE { BTC_SET_ACT_GET_BT_RSSI, BTC_SET_ACT_AGGREGATE_CTRL, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, + + // for mimo ps mode setting + BTC_SET_MIMO_PS_MODE, /*===== for 1Ant ======*/ /* type BOOLEAN */ @@ -317,6 +451,8 @@ typedef enum _BTC_SET_TYPE { BTC_SET_ACT_LEAVE_LPS, BTC_SET_ACT_ENTER_LPS, BTC_SET_ACT_NORMAL_LPS, + BTC_SET_ACT_PRE_NORMAL_LPS, + BTC_SET_ACT_POST_NORMAL_LPS, BTC_SET_ACT_DISABLE_LOW_POWER, BTC_SET_ACT_UPDATE_RAMASK, BTC_SET_ACT_SEND_MIMO_PS, @@ -349,6 +485,7 @@ typedef enum _BTC_NOTIFY_TYPE_SCAN { BTC_SCAN_FINISH = 0x0, BTC_SCAN_START = 0x1, BTC_SCAN_START_2G = 0x2, + BTC_SCAN_START_5G = 0x3, BTC_SCAN_MAX } BTC_NOTIFY_TYPE_SCAN, *PBTC_NOTIFY_TYPE_SCAN; typedef enum _BTC_NOTIFY_TYPE_SWITCHBAND { @@ -368,6 +505,7 @@ typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE { typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS { BTC_MEDIA_DISCONNECT = 0x0, BTC_MEDIA_CONNECT = 0x1, + BTC_MEDIA_CONNECT_5G = 0x02, BTC_MEDIA_MAX } BTC_NOTIFY_TYPE_MEDIA_STATUS, *PBTC_NOTIFY_TYPE_MEDIA_STATUS; typedef enum _BTC_NOTIFY_TYPE_SPECIFIC_PACKET { @@ -396,6 +534,8 @@ typedef enum _BTC_BT_OFFON { BTC_BT_ON = 0x1, } BTC_BTOFFON, *PBTC_BT_OFFON; +#define BTC_5G_BAND 0x80 + /*================================================== For following block is for coex offload ==================================================*/ @@ -505,6 +645,49 @@ typedef struct _BTC_OFFLOAD { extern BTC_OFFLOAD gl_coex_offload; /*==================================================*/ +/* BTC_LINK_MODE same as WIFI_LINK_MODE */ +typedef enum _BTC_LINK_MODE{ + BTC_LINK_NONE=0, + BTC_LINK_ONLY_GO, + BTC_LINK_ONLY_GC, + BTC_LINK_ONLY_STA, + BTC_LINK_ONLY_AP, + BTC_LINK_2G_MCC_GO_STA, + BTC_LINK_5G_MCC_GO_STA, + BTC_LINK_25G_MCC_GO_STA, + BTC_LINK_2G_MCC_GC_STA, + BTC_LINK_5G_MCC_GC_STA, + BTC_LINK_25G_MCC_GC_STA, + BTC_LINK_2G_SCC_GO_STA, + BTC_LINK_5G_SCC_GO_STA, + BTC_LINK_2G_SCC_GC_STA, + BTC_LINK_5G_SCC_GC_STA, + BTC_LINK_MAX=30 +}BTC_LINK_MODE, *PBTC_LINK_MODE; + + +struct btc_wifi_link_info { + BTC_LINK_MODE link_mode; /* LinkMode */ + u1Byte sta_center_channel; /* StaCenterChannel */ + u1Byte p2p_center_channel; /* P2PCenterChannel */ + BOOLEAN bany_client_join_go; + BOOLEAN benable_noa; + BOOLEAN bhotspot; +}; + +typedef enum _BTC_MULTI_PORT_TDMA_MODE { + BTC_MULTI_PORT_TDMA_MODE_NONE=0, + BTC_MULTI_PORT_TDMA_MODE_2G_SCC_GO, + BTC_MULTI_PORT_TDMA_MODE_2G_P2P_GO, + BTC_MULTI_PORT_TDMA_MODE_2G_HOTSPOT_GO +} BTC_MULTI_PORT_TDMA_MODE, *PBTC_MULTI_PORT_TDMA_MODE; + +typedef struct btc_multi_port_tdma_info { + BTC_MULTI_PORT_TDMA_MODE btc_multi_port_tdma_mode; + u1Byte start_time_from_bcn; + u1Byte bt_time; +} BTC_MULTI_PORT_TDMA_INFO, *PBTC_MULTI_PORT_TDMA_INFO; + typedef u1Byte (*BFP_BTC_R1)( IN PVOID pBtcContext, @@ -567,7 +750,7 @@ typedef u4Byte typedef VOID (*BFP_BTC_SET_RF_REG)( IN PVOID pBtcContext, - IN u1Byte eRFPath, + IN enum rf_path eRFPath, IN u4Byte RegAddr, IN u4Byte BitMask, IN u4Byte Data @@ -575,7 +758,7 @@ typedef VOID typedef u4Byte (*BFP_BTC_GET_RF_REG)( IN PVOID pBtcContext, - IN u1Byte eRFPath, + IN enum rf_path eRFPath, IN u4Byte RegAddr, IN u4Byte BitMask ); @@ -656,6 +839,14 @@ typedef u4Byte IN PVOID pBtcContext ); +typedef u4Byte +(*BFP_BTC_SET_ATOMIC) ( + IN PVOID pBtcContext, + IN pu4Byte target, + IN u4Byte val + ); + + typedef VOID (*BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD)( IN PVOID pDM_Odm, @@ -669,6 +860,12 @@ typedef u4Byte IN u1Byte info_type ); +typedef VOID +(*BTC_PHYDM_MODIFY_ANTDIV_HWSW)( + IN PVOID pDM_Odm, + IN u1Byte type + ); + typedef u1Byte (*BFP_BTC_GET_ANT_DET_VAL_FROM_BT)( @@ -779,6 +976,9 @@ struct btc_statistics { u32 cnt_coex_dm_switch; u32 cnt_stack_operation_notify; u32 cnt_dbg_ctrl; + u32 cnt_rate_id_notify; + u32 cnt_halt_notify; + u32 cnt_pnp_notify; }; struct btc_coexist { @@ -788,6 +988,7 @@ struct btc_coexist { struct btc_bt_info bt_info; /*some bt info referenced by non-bt module*/ struct btc_stack_info stack_info; struct btc_bt_link_info bt_link_info; + struct btc_wifi_link_info wifi_link_info; #ifdef CONFIG_RF4CE_COEXIST struct btc_rf4ce_info rf4ce_info; @@ -802,6 +1003,8 @@ struct btc_coexist { pu1Byte cli_buf; struct btc_statistics statistics; u1Byte pwrModeVal[10]; + BOOLEAN dbg_mode; + BOOLEAN auto_report; /* function pointers */ /* io related */ @@ -839,12 +1042,59 @@ struct btc_coexist { BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE btc_get_bt_coex_supported_feature; BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION btc_get_bt_coex_supported_version; BFP_BTC_GET_PHYDM_VERSION btc_get_bt_phydm_version; + BFP_BTC_SET_ATOMIC btc_set_atomic; BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD btc_phydm_modify_RA_PCR_threshold; BTC_PHYDM_CMNINFOQUERY btc_phydm_query_PHY_counter; + BTC_PHYDM_MODIFY_ANTDIV_HWSW btc_phydm_modify_antdiv_hwsw; BFP_BTC_GET_ANT_DET_VAL_FROM_BT btc_get_ant_det_val_from_bt; BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT btc_get_ble_scan_type_from_bt; BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT btc_get_ble_scan_para_from_bt; BFP_BTC_GET_BT_AFH_MAP_FROM_BT btc_get_bt_afh_map_from_bt; + + union { + #ifdef CONFIG_RTL8822B + struct coex_dm_8822b_1ant coex_dm_8822b_1ant; + struct coex_dm_8822b_2ant coex_dm_8822b_2ant; + #endif /* 8822B */ + #ifdef CONFIG_RTL8821C + struct coex_dm_8821c_1ant coex_dm_8821c_1ant; + struct coex_dm_8821c_2ant coex_dm_8821c_2ant; + #endif /* 8821C */ + }; + + union { + #ifdef CONFIG_RTL8822B + struct coex_sta_8822b_1ant coex_sta_8822b_1ant; + struct coex_sta_8822b_2ant coex_sta_8822b_2ant; + #endif /* 8822B */ + #ifdef CONFIG_RTL8821C + struct coex_sta_8821c_1ant coex_sta_8821c_1ant; + struct coex_sta_8821c_2ant coex_sta_8821c_2ant; + #endif /* 8821C */ + }; + + union { + #ifdef CONFIG_RTL8822B + struct rfe_type_8822b_1ant rfe_type_8822b_1ant; + struct rfe_type_8822b_2ant rfe_type_8822b_2ant; + #endif /* 8822B */ + #ifdef CONFIG_RTL8821C + struct rfe_type_8821c_1ant rfe_type_8821c_1ant; + struct rfe_type_8821c_2ant rfe_type_8821c_2ant; + #endif /* 8821C */ + }; + + union { + #ifdef CONFIG_RTL8822B + struct wifi_link_info_8822b_1ant wifi_link_info_8822b_1ant; + struct wifi_link_info_8822b_2ant wifi_link_info_8822b_2ant; + #endif /* 8822B */ + #ifdef CONFIG_RTL8821C + struct wifi_link_info_8821c_1ant wifi_link_info_8821c_1ant; + struct wifi_link_info_8821c_2ant wifi_link_info_8821c_2ant; + #endif /* 8821C */ + }; + }; typedef struct btc_coexist *PBTC_COEXIST; @@ -918,6 +1168,18 @@ EXhalbtcoutsrc_RfStatusNotify( IN u1Byte type ); VOID +EXhalbtcoutsrc_WlFwDbgInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtcoutsrc_rx_rate_change_notify( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN is_data_frame, + IN u1Byte btc_rate_id + ); +VOID EXhalbtcoutsrc_StackOperationNotify( IN PBTC_COEXIST pBtCoexist, IN u1Byte type diff --git a/hal/btc/mp_precomp.h b/hal/btc/mp_precomp.h index 54125b1..abedf68 100644 --- a/hal/btc/mp_precomp.h +++ b/hal/btc/mp_precomp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __MP_PRECOMP_H__ #define __MP_PRECOMP_H__ @@ -27,6 +22,7 @@ #ifdef PLATFORM_LINUX #define rsprintf snprintf +#define rstrncat(dst, src, src_size) strncat(dst, src, src_size) #elif defined(PLATFORM_WINDOWS) #define rsprintf sprintf_s #endif @@ -64,27 +60,72 @@ extern u4Byte GLBtcDbgType[]; #define HS_SUPPORT 0 #endif -#include "halbtcoutsrc.h" +/* for wifi only mode */ +#include "hal_btcoex_wifionly.h" + +#ifdef CONFIG_BT_COEXIST + +struct wifi_only_cfg; +struct btc_coexist; + +#ifdef CONFIG_RTL8192E #include "halbtc8192e1ant.h" #include "halbtc8192e2ant.h" +#endif + +#ifdef CONFIG_RTL8723B +#include "halbtc8723bwifionly.h" #include "halbtc8723b1ant.h" #include "halbtc8723b2ant.h" +#endif + +#ifdef CONFIG_RTL8812A #include "halbtc8812a1ant.h" #include "halbtc8812a2ant.h" +#endif + +#ifdef CONFIG_RTL8821A #include "halbtc8821a1ant.h" #include "halbtc8821a2ant.h" +#endif + +#ifdef CONFIG_RTL8703B #include "halbtc8703b1ant.h" +#endif + +#ifdef CONFIG_RTL8723D #include "halbtc8723d1ant.h" #include "halbtc8723d2ant.h" +#endif + +#ifdef CONFIG_RTL8822B +#include "halbtc8822bwifionly.h" #include "halbtc8822b1ant.h" #include "halbtc8822b2ant.h" +#endif + +#ifdef CONFIG_RTL8821C +#include "halbtc8821cwifionly.h" #include "halbtc8821c1ant.h" #include "halbtc8821c2ant.h" +#endif -/* for wifi only mode */ -#include "hal_btcoex_wifionly.h" +#include "halbtcoutsrc.h" + +#else /* CONFIG_BT_COEXIST */ + +#ifdef CONFIG_RTL8723B #include "halbtc8723bwifionly.h" +#endif + +#ifdef CONFIG_RTL8822B #include "halbtc8822bwifionly.h" +#endif + +#ifdef CONFIG_RTL8821C #include "halbtc8821cwifionly.h" +#endif + +#endif /* CONFIG_BT_COEXIST */ #endif /* __MP_PRECOMP_H__ */ diff --git a/hal/efuse/efuse_mask.h b/hal/efuse/efuse_mask.h index 1ab0692..f6059e4 100644 --- a/hal/efuse/efuse_mask.h +++ b/hal/efuse/efuse_mask.h @@ -1,5 +1,19 @@ - -#if DEV_BUS_TYPE == RT_USB_INTERFACE +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifdef CONFIG_USB_HCI #if defined(CONFIG_RTL8188E) #include "rtl8188e/HalEfuseMask8188E_USB.h" @@ -37,6 +51,10 @@ #include "rtl8188f/HalEfuseMask8188F_USB.h" #endif + #if defined(CONFIG_RTL8188GTV) + #include "rtl8188gtv/HalEfuseMask8188GTV_USB.h" + #endif + #if defined(CONFIG_RTL8822B) #include "rtl8822b/HalEfuseMask8822B_USB.h" #endif @@ -44,8 +62,17 @@ #if defined(CONFIG_RTL8821C) #include "rtl8821c/HalEfuseMask8821C_USB.h" #endif + + #if defined(CONFIG_RTL8710B) + #include "rtl8710b/HalEfuseMask8710B_USB.h" + #endif + + #if defined(CONFIG_RTL8192F) + #include "rtl8192f/HalEfuseMask8192F_USB.h" + #endif +#endif /*CONFIG_USB_HCI*/ -#elif DEV_BUS_TYPE == RT_PCI_INTERFACE +#ifdef CONFIG_PCI_HCI #if defined(CONFIG_RTL8188E) #include "rtl8188e/HalEfuseMask8188E_PCIE.h" @@ -85,7 +112,11 @@ #include "rtl8821c/HalEfuseMask8821C_PCIE.h" #endif -#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE + #if defined(CONFIG_RTL8192F) + #include "rtl8192f/HalEfuseMask8192F_PCIE.h" + #endif +#endif /*CONFIG_PCI_HCI*/ +#ifdef CONFIG_SDIO_HCI #if defined(CONFIG_RTL8723B) #include "rtl8723b/HalEfuseMask8723B_SDIO.h" #endif @@ -102,6 +133,10 @@ #include "rtl8188f/HalEfuseMask8188F_SDIO.h" #endif + #if defined(CONFIG_RTL8188GTV) + #include "rtl8188gtv/HalEfuseMask8188GTV_SDIO.h" + #endif + #if defined(CONFIG_RTL8723D) #include "rtl8723d/HalEfuseMask8723D_SDIO.h" #endif @@ -121,4 +156,9 @@ #if defined(CONFIG_RTL8822B) #include "rtl8822b/HalEfuseMask8822B_SDIO.h" #endif -#endif + + #if defined(CONFIG_RTL8192F) + #include "rtl8192f/HalEfuseMask8192F_SDIO.h" + #endif + +#endif /*CONFIG_SDIO_HCI*/ diff --git a/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c b/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c index c7a30cc..d300ff2 100644 --- a/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c +++ b/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c @@ -1,22 +1,17 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ /* #include "Mp_Precomp.h" */ /* #include "../odm_precomp.h" */ diff --git a/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h b/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h index 8b20b35..a2bac91 100644 --- a/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h +++ b/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h @@ -1,22 +1,17 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ diff --git a/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.c b/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.c index 4833737..8555d56 100644 --- a/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.c +++ b/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.c @@ -1,22 +1,17 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ /* #include "Mp_Precomp.h" */ /* #include "../odm_precomp.h" */ diff --git a/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.h b/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.h index de4638b..f7880e3 100644 --- a/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.h +++ b/hal/efuse/rtl8821c/HalEfuseMask8821C_SDIO.h @@ -1,22 +1,17 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ diff --git a/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.c b/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.c index 0f49b04..f13c056 100644 --- a/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.c +++ b/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.c @@ -1,22 +1,17 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ /* #include "Mp_Precomp.h" */ /* #include "../odm_precomp.h" */ diff --git a/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.h b/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.h index 960f1ef..dceecb4 100644 --- a/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.h +++ b/hal/efuse/rtl8821c/HalEfuseMask8821C_USB.h @@ -1,22 +1,17 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ diff --git a/hal/hal_btcoex.c b/hal/hal_btcoex.c index c47a9d1..39bb165 100644 --- a/hal/hal_btcoex.c +++ b/hal/hal_btcoex.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define __HAL_BTCOEX_C__ #ifdef CONFIG_BT_COEXIST @@ -76,13 +71,14 @@ const char *const GLBtcWifiBwString[] = { "11bg", "HT20", "HT40", - "HT80", - "HT160" + "VHT80", + "VHT160" }; const char *const GLBtcWifiFreqString[] = { "2.4G", - "5G" + "5G", + "2.4G+5G" }; const char *const GLBtcIotPeerString[] = { @@ -179,8 +175,11 @@ typedef enum _bt_op_code { BT_OP_GET_BT_COEX_SUPPORTED_FEATURE = 0x2a, BT_OP_GET_BT_COEX_SUPPORTED_VERSION = 0x2b, BT_OP_GET_BT_ANT_DET_VAL = 0x2c, - BT_OP_GET_BT_BLE_SCAN_PARA = 0x2d, - BT_OP_GET_BT_BLE_SCAN_TYPE = 0x2e, + BT_OP_GET_BT_BLE_SCAN_TYPE = 0x2d, + BT_OP_GET_BT_BLE_SCAN_PARA = 0x2e, + BT_OP_GET_BT_DEVICE_INFO = 0x30, + BT_OP_GET_BT_FORBIDDEN_SLOT_VAL = 0x31, + BT_OP_SET_BT_LANCONSTRAIN_LEVEL = 0x32, BT_OP_MAX } BT_OP_CODE; @@ -357,6 +356,24 @@ void halbtcoutsrc_NormalLps(PBTC_COEXIST pBtCoexist) } } +void halbtcoutsrc_Pre_NormalLps(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + + padapter = pBtCoexist->Adapter; + + if (pBtCoexist->bt_info.bt_ctrl_lps) { + pBtCoexist->bt_info.bt_lps_on = _FALSE; + rtw_btcoex_LPS_Leave(padapter); + } +} + +void halbtcoutsrc_Post_NormalLps(PBTC_COEXIST pBtCoexist) +{ + if (pBtCoexist->bt_info.bt_ctrl_lps) + pBtCoexist->bt_info.bt_ctrl_lps = _FALSE; +} + /* * Constraint: * 1. this function will request pwrctrl->lock @@ -368,7 +385,7 @@ void halbtcoutsrc_LeaveLowPower(PBTC_COEXIST pBtCoexist) PHAL_DATA_TYPE pHalData; struct pwrctrl_priv *pwrctrl; s32 ready; - u32 stime; + systime stime; s32 utime; u32 timeout; /* unit: ms */ @@ -496,12 +513,33 @@ u8 halbtcoutsrc_is_fw_ready(PBTC_COEXIST pBtCoexist) padapter = pBtCoexist->Adapter; - return padapter->bFWReady; + return GET_HAL_DATA(padapter)->bFWReady; +} + +u8 halbtcoutsrc_IsDualBandConnected(PADAPTER padapter) +{ + u8 ret = BTC_MULTIPORT_SCC; + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(padapter) && (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))) { + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + u8 band0 = mccobjpriv->iface[0]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G; + u8 band1 = mccobjpriv->iface[1]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G; + + if (band0 != band1) + ret = BTC_MULTIPORT_MCC_DUAL_BAND; + else + ret = BTC_MULTIPORT_MCC_DUAL_CHANNEL; + } +#endif + + return ret; } u8 halbtcoutsrc_IsWifiBusy(PADAPTER padapter) { - if (rtw_mi_check_status(padapter, MI_AP_MODE)) + if (rtw_mi_check_status(padapter, MI_AP_ASSOC)) return _TRUE; if (rtw_mi_busy_traffic_check(padapter, _FALSE)) return _TRUE; @@ -578,10 +616,116 @@ u32 halbtcoutsrc_GetWifiLinkStatus(PBTC_COEXIST pBtCoexist) return retVal; } -static void _btmpoper_timer_hdl(struct timer_list *t) +struct btc_wifi_link_info halbtcoutsrc_getwifilinkinfo(PBTC_COEXIST pBtCoexist) +{ + u8 n_assoc_iface = 0, i =0, mcc_en = _FALSE; + PADAPTER adapter = NULL; + PADAPTER iface = NULL; + PADAPTER sta_iface = NULL, p2p_iface = NULL, ap_iface = NULL; + BTC_LINK_MODE btc_link_moe = BTC_LINK_MAX; + struct dvobj_priv *dvobj = NULL; + struct mlme_ext_priv *mlmeext = NULL; + struct btc_wifi_link_info wifi_link_info; + + adapter = (PADAPTER)pBtCoexist->Adapter; + dvobj = adapter_to_dvobj(adapter); + n_assoc_iface = rtw_mi_get_assoc_if_num(adapter); + + /* init value */ + wifi_link_info.link_mode = BTC_LINK_NONE; + wifi_link_info.sta_center_channel = 0; + wifi_link_info.p2p_center_channel = 0; + wifi_link_info.bany_client_join_go = _FALSE; + wifi_link_info.benable_noa = _FALSE; + wifi_link_info.bhotspot = _FALSE; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + mlmeext = &iface->mlmeextpriv; + if (MLME_IS_GO(iface)) { + wifi_link_info.link_mode = BTC_LINK_ONLY_GO; + wifi_link_info.p2p_center_channel = + rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + p2p_iface = iface; + if (rtw_linked_check(iface)) + wifi_link_info.bany_client_join_go = _TRUE; + } else if (MLME_IS_GC(iface)) { + wifi_link_info.link_mode = BTC_LINK_ONLY_GC; + wifi_link_info.p2p_center_channel = + rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + p2p_iface = iface; + } else if (MLME_IS_AP(iface)) { + wifi_link_info.link_mode = BTC_LINK_ONLY_AP; + ap_iface = iface; + wifi_link_info.p2p_center_channel = + rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + } else if (MLME_IS_STA(iface) && rtw_linked_check(iface)) { + wifi_link_info.link_mode = BTC_LINK_ONLY_STA; + wifi_link_info.sta_center_channel = + rtw_get_center_ch(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + sta_iface = iface; + } + } + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(adapter)) { + if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) + mcc_en = _TRUE; + } +#endif/* CONFIG_MCC_MODE */ + + if (n_assoc_iface == 0) { + wifi_link_info.link_mode = BTC_LINK_NONE; + } else if (n_assoc_iface == 1) { + /* by pass */ + } else if (n_assoc_iface == 2) { + if (sta_iface && p2p_iface) { + u8 band_sta = sta_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G; + u8 band_p2p = p2p_iface->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G; + if (band_sta == band_p2p) { + switch (band_sta) { + case BAND_ON_2_4G: + if (MLME_IS_GO(p2p_iface)) + wifi_link_info.link_mode = + mcc_en == _TRUE ? BTC_LINK_2G_MCC_GO_STA : BTC_LINK_2G_SCC_GO_STA; + else if (MLME_IS_GC(p2p_iface)) + wifi_link_info.link_mode = + mcc_en == _TRUE ? BTC_LINK_2G_MCC_GC_STA : BTC_LINK_2G_SCC_GC_STA; + break; + case BAND_ON_5G: + if (MLME_IS_GO(p2p_iface)) + wifi_link_info.link_mode = + mcc_en == _TRUE ? BTC_LINK_5G_MCC_GO_STA : BTC_LINK_5G_SCC_GO_STA; + else if (MLME_IS_GC(p2p_iface)) + wifi_link_info.link_mode = + mcc_en == _TRUE ? BTC_LINK_5G_MCC_GC_STA : BTC_LINK_5G_SCC_GC_STA; + break; + default: + break; + } + } else { + if (MLME_IS_GO(p2p_iface)) + wifi_link_info.link_mode = BTC_LINK_25G_MCC_GO_STA; + else if (MLME_IS_GC(p2p_iface)) + wifi_link_info.link_mode = BTC_LINK_25G_MCC_GC_STA; + } + } + } else { + if (pBtCoexist->board_info.btdm_ant_num == 1) + RTW_ERR("%s do not support n_assoc_iface > 2 (ant_num == 1)", __func__); + } + + return wifi_link_info; +} + + +static void _btmpoper_timer_hdl(void *p) { - if (GLBtcBtMpRptWait) { - GLBtcBtMpRptWait = 0; + if (GLBtcBtMpRptWait == _TRUE) { + GLBtcBtMpRptWait = _FALSE; _rtw_up_sema(&GLBtcBtMpRptSema); } } @@ -614,9 +758,9 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm if (cmd && size) _rtw_memcpy(buf + 2, cmd, size); - GLBtcBtMpRptWait = 1; - GLBtcBtMpRptWiFiOK = 0; - GLBtcBtMpRptBTOK = 0; + GLBtcBtMpRptWait = _TRUE; + GLBtcBtMpRptWiFiOK = _FALSE; + GLBtcBtMpRptBTOK = _FALSE; GLBtcBtMpRptStatus = 0; padapter = pBtCoexist->Adapter; _set_timer(&GLBtcBtMpOperTimer, BTC_MPOPER_TIMEOUT); @@ -627,18 +771,19 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm } _rtw_down_sema(&GLBtcBtMpRptSema); - /* GLBtcBtMpRptWait should be 0 here*/ + /* GLBtcBtMpRptWait should be _FALSE here*/ - if (!GLBtcBtMpRptWiFiOK) { + if (GLBtcBtMpRptWiFiOK == _FALSE) { RTW_ERR("%s: Didn't get H2C Rsp Event!\n", __FUNCTION__); ret = BT_STATUS_H2C_TIMTOUT; goto exit; } - if (!GLBtcBtMpRptBTOK) { + if (GLBtcBtMpRptBTOK == _FALSE) { RTW_DBG("%s: Didn't get BT response!\n", __FUNCTION__); ret = BT_STATUS_H2C_BT_NO_RSP; goto exit; } + if (seq != GLBtcBtMpRptSeq) { RTW_ERR("%s: Sequence number not match!(%d!=%d)!\n", __FUNCTION__, seq, GLBtcBtMpRptSeq); @@ -709,14 +854,7 @@ u32 halbtcoutsrc_GetBtPatchVer(PBTC_COEXIST pBtCoexist) s32 halbtcoutsrc_GetWifiRssi(PADAPTER padapter) { - PHAL_DATA_TYPE pHalData; - s32 undecorated_smoothed_pwdb = 0; - - pHalData = GET_HAL_DATA(padapter); - - undecorated_smoothed_pwdb = pHalData->entry_min_undecorated_smoothed_pwdb; - - return undecorated_smoothed_pwdb; + return rtw_phydm_get_min_rssi(padapter); } u32 halbtcoutsrc_GetBtCoexSupportedFeature(void *pBtcContext) @@ -781,6 +919,68 @@ u32 halbtcoutsrc_GetBtCoexSupportedVersion(void *pBtcContext) return data; } +u32 halbtcoutsrc_GetBtDeviceInfo(void *pBtcContext) +{ + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u32 btDeviceInfo = 0; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_DEVICE_INFO; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + btDeviceInfo = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return btDeviceInfo; +} + +u32 halbtcoutsrc_GetBtForbiddenSlotVal(void *pBtcContext) +{ + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u32 btForbiddenSlotVal = 0; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_FORBIDDEN_SLOT_VAL; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + btForbiddenSlotVal = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return btForbiddenSlotVal; +} + static u8 halbtcoutsrc_GetWifiScanAPNum(PADAPTER padapter) { struct mlme_priv *pmlmepriv; @@ -807,11 +1007,13 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) PADAPTER padapter; PHAL_DATA_TYPE pHalData; struct mlme_ext_priv *mlmeext; + struct btc_wifi_link_info *wifi_link_info; u8 bSoftApExist, bVwifiExist; u8 *pu8; s32 *pS4Tmp; u32 *pU4Tmp; u8 *pU1Tmp; + u16 *pU2Tmp; u8 ret; @@ -828,6 +1030,8 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) pS4Tmp = (s32 *)pOutBuf; pU4Tmp = (u32 *)pOutBuf; pU1Tmp = (u8 *)pOutBuf; + pU2Tmp = (u16*)pOutBuf; + wifi_link_info = (struct btc_wifi_link_info *)pOutBuf; ret = _TRUE; switch (getType) { @@ -849,6 +1053,10 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) *pu8 = (rtw_mi_check_status(padapter, MI_LINKED)) ? _TRUE : _FALSE; break; + case BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED: + *pu8 = halbtcoutsrc_IsDualBandConnected(padapter); + break; + case BTC_GET_BL_WIFI_BUSY: *pu8 = halbtcoutsrc_IsWifiBusy(padapter); break; @@ -876,7 +1084,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) break; case BTC_GET_BL_WIFI_UNDER_5G: - *pu8 = (pHalData->current_band_type == 1) ? _TRUE : _FALSE; + *pu8 = (pHalData->current_band_type == BAND_ON_5G) ? _TRUE : _FALSE; break; case BTC_GET_BL_WIFI_AP_MODE_ENABLE: @@ -920,6 +1128,11 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) #endif break; + case BTC_GET_BL_WIFI_LW_PWR_STATE: + /* return false due to coex do not run during 32K */ + *pu8 = FALSE; + break; + case BTC_GET_S4_WIFI_RSSI: *pS4Tmp = halbtcoutsrc_GetWifiRssi(padapter); break; @@ -974,7 +1187,9 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) case BTC_GET_U4_WIFI_LINK_STATUS: *pU4Tmp = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist); break; - + case BTC_GET_BL_WIFI_LINK_INFO: + *wifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist); + break; case BTC_GET_U4_BT_PATCH_VER: *pU4Tmp = halbtcoutsrc_GetBtPatchVer(pBtCoexist); break; @@ -990,6 +1205,14 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) *pU4Tmp = halbtcoutsrc_GetBtCoexSupportedFeature(pBtCoexist); break; + case BTC_GET_U4_BT_DEVICE_INFO: + *pU4Tmp = halbtcoutsrc_GetBtDeviceInfo(pBtCoexist); + break; + + case BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL: + *pU4Tmp = halbtcoutsrc_GetBtForbiddenSlotVal(pBtCoexist); + break; + case BTC_GET_U4_WIFI_IQK_TOTAL: *pU4Tmp = pHalData->odmpriv.n_iqk_cnt; break; @@ -1070,6 +1293,10 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) *pU1Tmp = padapter->dvobj->pwrctl_priv.pwr_mode; break; + case BTC_GET_U2_BEACON_PERIOD: + *pU2Tmp = mlmeext->mlmext_info.bcn_interval; + break; + default: ret = _FALSE; break; @@ -1078,6 +1305,30 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) return ret; } +u16 halbtcoutsrc_LnaConstrainLvl(void *pBtcContext, u8 *lna_constrain_level) +{ + PBTC_COEXIST pBtCoexist; + u16 ret = BT_STATUS_BT_OP_SUCCESS; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + _irqL irqL; + u8 op_code; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + ret = _btmpoper_cmd(pBtCoexist, BT_OP_SET_BT_LANCONSTRAIN_LEVEL, 0, lna_constrain_level, 1); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + } else { + ret = BT_STATUS_NOT_IMPLEMENT; + RTW_INFO("%s halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == FALSE\n", __func__); + } + + return ret; +} + u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) { PBTC_COEXIST pBtCoexist; @@ -1192,11 +1443,20 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) halbtcoutsrc_NormalLps(pBtCoexist); break; + case BTC_SET_ACT_PRE_NORMAL_LPS: + halbtcoutsrc_Pre_NormalLps(pBtCoexist); + break; + + case BTC_SET_ACT_POST_NORMAL_LPS: + halbtcoutsrc_Post_NormalLps(pBtCoexist); + break; + case BTC_SET_ACT_DISABLE_LOW_POWER: halbtcoutsrc_DisableLowPower(pBtCoexist, *pu8); break; case BTC_SET_ACT_UPDATE_RAMASK: + /* pBtCoexist->bt_info.ra_mask = *pU4Tmp; if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) { @@ -1205,8 +1465,9 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) cur_network = &padapter->mlmeextpriv.mlmext_info.network; psta = rtw_get_stainfo(&padapter->stapriv, cur_network->MacAddress); - rtw_hal_update_ra_mask(psta, psta->rssi_level, _FALSE); + rtw_hal_update_ra_mask(psta); } + */ break; case BTC_SET_ACT_SEND_MIMO_PS: { @@ -1268,6 +1529,9 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) ret = _FALSE; #endif break; + case BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL: + halbtcoutsrc_LnaConstrainLvl(pBtCoexist, pu8); + break; /* ===================== */ default: ret = _FALSE; @@ -1519,18 +1783,108 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist) BOOLEAN bBtHsOn = _FALSE, bLowPower = _FALSE; u8 wifiChnl = 0, wifiP2PChnl = 0, nScanAPNum = 0, FwPSState; u32 iqk_cnt_total = 0, iqk_cnt_ok = 0, iqk_cnt_fail = 0; + u16 wifiBcnInterval = 0; + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); + struct btc_wifi_link_info wifi_link_info; + + wifi_link_info = halbtcoutsrc_getwifilinkinfo(pBtCoexist); + + switch (wifi_link_info.link_mode) { + case BTC_LINK_NONE: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "None", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G; + break; + case BTC_LINK_ONLY_GO: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "ONLY_GO", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G; + break; + case BTC_LINK_ONLY_GC: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "ONLY_GC", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G; + break; + case BTC_LINK_ONLY_STA: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "ONLY_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G; + break; + case BTC_LINK_ONLY_AP: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "ONLY_AP", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G; + break; + case BTC_LINK_2G_MCC_GO_STA: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "24G_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = BTC_FREQ_2_4G; + break; + case BTC_LINK_5G_MCC_GO_STA: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "5G_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = BTC_FREQ_5G; + break; + case BTC_LINK_25G_MCC_GO_STA: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "2BANDS_MCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = BTC_FREQ_25G; + break; + case BTC_LINK_2G_MCC_GC_STA: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "24G_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = BTC_FREQ_2_4G; + break; + case BTC_LINK_5G_MCC_GC_STA: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "5G_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = BTC_FREQ_5G; + break; + case BTC_LINK_25G_MCC_GC_STA: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "2BANDS_MCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = BTC_FREQ_25G; + break; + case BTC_LINK_2G_SCC_GO_STA: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "24G_SCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = BTC_FREQ_2_4G; + break; + case BTC_LINK_5G_SCC_GO_STA: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "5G_SCC_GO_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = BTC_FREQ_5G; + break; + case BTC_LINK_2G_SCC_GC_STA: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "24G_SCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = BTC_FREQ_2_4G; + break; + case BTC_LINK_5G_SCC_GC_STA: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "5G_SCC_GC_STA", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = BTC_FREQ_5G; + break; + default: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %d/ %d", "WifiLinkMode/HotSpa/Noa/ClientJoin", + "UNKNOWN", wifi_link_info.bhotspot, wifi_link_info.benable_noa, wifi_link_info.bany_client_join_go); + wifiFreq = hal->current_channel > 14 ? BTC_FREQ_5G : BTC_FREQ_2_4G; + break; + } + + CL_PRINTF(cliBuf); wifiLinkStatus = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "STA/vWifi/HS/p2pGo/p2pGc", \ + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "STA/vWifi/HS/p2pGo/p2pGc", ((wifiLinkStatus & WIFI_STA_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_AP_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_HS_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) ? 1 : 0), - ((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0)); + ((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0)); CL_PRINTF(cliBuf); pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Link/ Roam/ Scan", \ + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Link/ Roam/ Scan", bLink, bRoam, bScan); CL_PRINTF(cliBuf); @@ -1548,20 +1902,20 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist) } pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); - pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifiChnl); - if ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) || (wifiLinkStatus & WIFI_P2P_GC_CONNECTED)) - pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_P2P_CHNL, &wifiP2PChnl); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dBm/ %d/ %d", "RSSI/ STA_Chnl/ P2P_Chnl", \ - wifiRssi -100, wifiChnl, wifiP2PChnl); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_U2_BEACON_PERIOD, &wifiBcnInterval); + wifiChnl = wifi_link_info.sta_center_channel; + wifiP2PChnl = wifi_link_info.p2p_center_channel; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dBm/ %d/ %d/ %d", "RSSI/ STA_Chnl/ P2P_Chnl/ BI", + wifiRssi-100, wifiChnl, wifiP2PChnl, wifiBcnInterval); CL_PRINTF(cliBuf); - pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifiFreq); pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_AP_NUM, &nScanAPNum); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s/ %d ", "Band/ BW/ Traffic/ APCnt", \ + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s/ %d ", "Band/ BW/ Traffic/ APCnt", GLBtcWifiFreqString[wifiFreq], ((bWifiUnderBMode) ? "11b" : GLBtcWifiBwString[wifiBw]), ((!bWifiBusy) ? "idle" : ((BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) ? "uplink" : "downlink")), nScanAPNum); @@ -1574,7 +1928,7 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist) ((halbtcoutsrc_Under32K(pBtCoexist) == _TRUE) ? ", 32k" : "")); CL_PRINTF(cliBuf); - CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)", "Power mode cmd(lps/rpwm)", \ + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)", "Power mode cmd(lps/rpwm)", pBtCoexist->pwrModeVal[0], pBtCoexist->pwrModeVal[1], pBtCoexist->pwrModeVal[2], pBtCoexist->pwrModeVal[3], pBtCoexist->pwrModeVal[4], pBtCoexist->pwrModeVal[5], @@ -1743,7 +2097,7 @@ u32 halbtcoutsrc_GetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask) return phy_query_bb_reg(padapter, RegAddr, BitMask); } -void halbtcoutsrc_SetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +void halbtcoutsrc_SetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data) { PBTC_COEXIST pBtCoexist; PADAPTER padapter; @@ -1755,7 +2109,7 @@ void halbtcoutsrc_SetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMa phy_set_rf_reg(padapter, eRFPath, RegAddr, BitMask, Data); } -u32 halbtcoutsrc_GetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask) +u32 halbtcoutsrc_GetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask) { PBTC_COEXIST pBtCoexist; PADAPTER padapter; @@ -2088,11 +2442,12 @@ u32 halbtcoutsrc_GetBleScanParaFromBt(void *pBtcContext, u8 scanType) u8 op_code; u8 status; + buf[0] = scanType; _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); op_code = BT_OP_GET_BT_BLE_SCAN_PARA; - status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 1); if (status == BT_STATUS_BT_OP_SUCCESS) data = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); else @@ -2196,6 +2551,21 @@ u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext) #ifdef CONFIG_RTL8821C return RELEASE_VERSION_8821C; #endif + +#ifdef CONFIG_RTL8192F + return RELEASE_VERSION_8192F; +#endif +} + +u32 halbtcoutsrc_SetAtomic (void *btc_ctx, u32 *target, u32 val) +{ + *target = val; + return _SUCCESS; +} + +void halbtcoutsrc_phydm_modify_AntDiv_HwSw(void *pBtcContext, u8 is_hw) +{ + /* empty function since we don't need it */ } void halbtcoutsrc_phydm_modify_RA_PCR_threshold(void *pBtcContext, u8 RA_offset_direction, u8 RA_threshold_offset) @@ -2214,7 +2584,7 @@ u32 halbtcoutsrc_phydm_query_PHY_counter(void *pBtcContext, u8 info_type) /* switch to #if 0 in case the phydm version does not provide the function */ #if 1 - return phydm_cmn_info_query((struct PHY_DM_STRUCT *)pBtCoexist->odm_priv, (enum phydm_info_query_e)info_type); + return phydm_cmn_info_query((struct dm_struct *)pBtCoexist->odm_priv, (enum phydm_info_query)info_type); #else return 0; #endif @@ -2341,7 +2711,6 @@ void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length) u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) { PBTC_COEXIST pBtCoexist = &GLBtCoexist; - u8 antNum = 1, chipType = 0, singleAntPath = 0; HAL_DATA_TYPE *pHalData = GET_HAL_DATA((PADAPTER)padapter); if (pBtCoexist->bBinded) @@ -2362,6 +2731,14 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) pBtCoexist->bt_info.increase_scan_dev_num = _FALSE; pBtCoexist->bt_info.miracast_plus_bt = _FALSE; + return _TRUE; +} + +void EXhalbtcoutsrc_AntInfoSetting(void *padapter) +{ + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + u8 antNum = 1, singleAntPath = 0; + antNum = rtw_btcoex_get_pg_ant_num((PADAPTER)padapter); EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_PG, antNum); @@ -2370,6 +2747,9 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) EXhalbtcoutsrc_SetSingleAntPath(singleAntPath); } + pBtCoexist->board_info.customerID = RT_CID_DEFAULT; + pBtCoexist->board_info.customer_id = RT_CID_DEFAULT; + /* set default antenna position to main port */ pBtCoexist->board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; @@ -2382,7 +2762,6 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) pBtCoexist->board_info.ant_div_cfg = rtw_btcoex_get_ant_div_cfg((PADAPTER)padapter); - return _TRUE; } u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter) @@ -2439,8 +2818,10 @@ u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter) pBtCoexist->btc_get_ble_scan_para_from_bt = halbtcoutsrc_GetBleScanParaFromBt; pBtCoexist->btc_get_bt_afh_map_from_bt = halbtcoutsrc_GetBtAFHMapFromBt; pBtCoexist->btc_get_bt_phydm_version = halbtcoutsrc_GetPhydmVersion; + pBtCoexist->btc_set_atomic= halbtcoutsrc_SetAtomic; pBtCoexist->btc_phydm_modify_RA_PCR_threshold = halbtcoutsrc_phydm_modify_RA_PCR_threshold; pBtCoexist->btc_phydm_query_PHY_counter = halbtcoutsrc_phydm_query_PHY_counter; + pBtCoexist->btc_phydm_modify_antdiv_hwsw = halbtcoutsrc_phydm_modify_AntDiv_HwSw; pBtCoexist->cli_buf = &GLBtcDbgBuf[0]; @@ -2457,15 +2838,15 @@ u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter) /* BT Control H2C/C2H*/ GLBtcBtMpOperSeq = 0; _rtw_mutex_init(&GLBtcBtMpOperLock); - rtw_init_timer(&GLBtcBtMpOperTimer, padapter, _btmpoper_timer_hdl); + rtw_init_timer(&GLBtcBtMpOperTimer, padapter, _btmpoper_timer_hdl, pBtCoexist); _rtw_init_sema(&GLBtcBtMpRptSema, 0); GLBtcBtMpRptSeq = 0; GLBtcBtMpRptStatus = 0; _rtw_memset(GLBtcBtMpRptRsp, 0, C2H_MAX_SIZE); GLBtcBtMpRptRspSize = 0; - GLBtcBtMpRptWait = 0; - GLBtcBtMpRptWiFiOK = 0; - GLBtcBtMpRptBTOK = 0; + GLBtcBtMpRptWait = _FALSE; + GLBtcBtMpRptWiFiOK = _FALSE; + GLBtcBtMpRptBTOK = _FALSE; return _TRUE; } @@ -2479,41 +2860,57 @@ void EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist) pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter); - /* Power on setting function is only added in 8723B currently */ if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_power_on_setting(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_power_on_setting(pBtCoexist); +#endif } - if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8703b1ant_power_on_setting(pBtCoexist); + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_power_on_setting(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_power_on_setting(pBtCoexist); } +#endif - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8821A + else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_power_on_setting(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_power_on_setting(pBtCoexist); } +#endif - if ((IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) { +#ifdef CONFIG_RTL8822B + else if ((IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_power_on_setting(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_power_on_setting(pBtCoexist); } +#endif - if ((IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) { +#ifdef CONFIG_RTL8821C + else if ((IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_power_on_setting(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_power_on_setting(pBtCoexist); } +#endif } void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist) @@ -2524,25 +2921,31 @@ void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist) pBtCoexist->statistics.cnt_pre_load_firmware++; if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_pre_load_firmware(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_pre_load_firmware(pBtCoexist); +#endif } - if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_pre_load_firmware(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_pre_load_firmware(pBtCoexist); } +#endif - if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_pre_load_firmware(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_pre_load_firmware(pBtCoexist); } +#endif } void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly) @@ -2553,57 +2956,74 @@ void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly) pBtCoexist->statistics.cnt_init_hw_config++; if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_init_hw_config(pBtCoexist, bWifiOnly); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_init_hw_config(pBtCoexist, bWifiOnly); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_init_hw_config(pBtCoexist, bWifiOnly); - #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - rtw_hal_set_default_port_id_cmd(pBtCoexist->Adapter, 0); - rtw_hal_set_wifi_port_id_cmd(pBtCoexist->Adapter); - #endif - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_init_hw_config(pBtCoexist, bWifiOnly); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_init_hw_config(pBtCoexist, bWifiOnly); - #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - rtw_hal_set_default_port_id_cmd(pBtCoexist->Adapter, 0); - rtw_hal_set_wifi_port_id_cmd(pBtCoexist->Adapter); - #endif } +#endif } void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist) @@ -2614,49 +3034,74 @@ void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist) pBtCoexist->statistics.cnt_init_coex_dm++; if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_init_coex_dm(pBtCoexist); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { - if (pBtCoexist->board_info.btdm_ant_num == 2) - ex_halbtc8723d2ant_init_coex_dm(pBtCoexist); + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8723d2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_init_coex_dm(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_init_coex_dm(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_init_coex_dm(pBtCoexist); } +#endif pBtCoexist->initilized = _TRUE; } @@ -2684,50 +3129,74 @@ void EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type) * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_ips_notify(pBtCoexist, ipsType); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_ips_notify(pBtCoexist, ipsType); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_ips_notify(pBtCoexist, ipsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_ips_notify(pBtCoexist, ipsType); } - +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -2752,49 +3221,74 @@ void EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type) } if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_lps_notify(pBtCoexist, lpsType); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_lps_notify(pBtCoexist, lpsType); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_lps_notify(pBtCoexist, lpsType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_lps_notify(pBtCoexist, lpsType); } +#endif } void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type) @@ -2819,49 +3313,74 @@ void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type) * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_scan_notify(pBtCoexist, scanType); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_scan_notify(pBtCoexist, scanType); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_scan_notify(pBtCoexist, scanType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_scan_notify(pBtCoexist, scanType); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -2896,75 +3415,94 @@ void EXhalbtcoutsrc_SetAntennaPathNotify(PBTC_COEXIST pBtCoexist, u8 type) #endif } -void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 action) +void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 assoType) { - u8 assoType; - if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; pBtCoexist->statistics.cnt_connect_notify++; if (pBtCoexist->manual_control) return; - - if (action) - assoType = BTC_ASSOCIATE_START; - else - assoType = BTC_ASSOCIATE_FINISH; - + /* All notify is called in cmd thread, don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_connect_notify(pBtCoexist, assoType); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_connect_notify(pBtCoexist, assoType); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_connect_notify(pBtCoexist, assoType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_connect_notify(pBtCoexist, assoType); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS mediaStatus) { - u8 mStatus; + u8 mStatus = BTC_MEDIA_MAX; + PADAPTER adapter = (PADAPTER)pBtCoexist->Adapter; + HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; @@ -2973,65 +3511,104 @@ void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS if (pBtCoexist->manual_control) return; - if (RT_MEDIA_CONNECT == mediaStatus) - mStatus = BTC_MEDIA_CONNECT; - else + if (RT_MEDIA_CONNECT == mediaStatus) { + if (hal->current_band_type == BAND_ON_2_4G) + mStatus = BTC_MEDIA_CONNECT; + else if (hal->current_band_type == BAND_ON_5G) + mStatus = BTC_MEDIA_CONNECT_5G; + else { + mStatus = BTC_MEDIA_CONNECT; + RTW_ERR("%s unknow band type\n", __func__); + } + } else mStatus = BTC_MEDIA_DISCONNECT; /* All notify is called in cmd thread, don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_media_status_notify(pBtCoexist, mStatus); - else -#endif +#ifdef CONFIG_RTL8821A + /* compatible for 8821A */ + if (mStatus == BTC_MEDIA_CONNECT_5G) + mStatus = BTC_MEDIA_CONNECT; if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + /* compatible for 8812A */ + if (mStatus == BTC_MEDIA_CONNECT_5G) + mStatus = BTC_MEDIA_CONNECT; if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_media_status_notify(pBtCoexist, mStatus); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_media_status_notify(pBtCoexist, mStatus); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_media_status_notify(pBtCoexist, mStatus); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType) { - u8 packetType; + u8 packetType; + PADAPTER adapter = (PADAPTER)pBtCoexist->Adapter; + HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; @@ -3050,53 +3627,88 @@ void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType) return; } + if (hal->current_band_type == BAND_ON_5G) + packetType |= BTC_5G_BAND; + /* All notify is called in cmd thread, don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_specific_packet_notify(pBtCoexist, packetType); - else -#endif +#ifdef CONFIG_RTL8821A + /* compatible for 8821A */ + if (hal->current_band_type == BAND_ON_5G) + packetType &= ~BTC_5G_BAND; + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + /* compatible for 8812A */ + if (hal->current_band_type == BAND_ON_5G) + packetType &= ~BTC_5G_BAND; + if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_specific_packet_notify(pBtCoexist, packetType); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_specific_packet_notify(pBtCoexist, packetType); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_specific_packet_notify(pBtCoexist, packetType); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -3110,55 +3722,143 @@ void EXhalbtcoutsrc_bt_info_notify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 lengt /* All notify is called in cmd thread, don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_bt_info_notify(pBtCoexist, tmpBuf, length); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_bt_info_notify(pBtCoexist, tmpBuf, length); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_bt_info_notify(pBtCoexist, tmpBuf, length); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_bt_info_notify(pBtCoexist, tmpBuf, length); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } +void EXhalbtcoutsrc_WlFwDbgInfoNotify(PBTC_COEXIST pBtCoexist, u8* tmpBuf, u8 length) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8703B + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8703b1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length); +#endif + } + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8723d1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8723d2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length); + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length); + } +#endif +} + +void EXhalbtcoutsrc_rx_rate_change_notify(PBTC_COEXIST pBtCoexist, u8 is_data_frame, u8 btc_rate_id) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cnt_rate_id_notify++; + + if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8703B + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8703b1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id); +#endif + } + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8723d1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8723d2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id); + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id); + else if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id); + } +#endif +} + VOID EXhalbtcoutsrc_RfStatusNotify( IN PBTC_COEXIST pBtCoexist, @@ -3169,29 +3869,44 @@ EXhalbtcoutsrc_RfStatusNotify( return; pBtCoexist->statistics.cnt_rf_status_notify++; - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { + if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_rf_status_notify(pBtCoexist, type); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_rf_status_notify(pBtCoexist, type); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_rf_status_notify(pBtCoexist, type); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_rf_status_notify(pBtCoexist, type); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_rf_status_notify(pBtCoexist, type); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_rf_status_notify(pBtCoexist, type); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_rf_status_notify(pBtCoexist, type); } +#endif } void EXhalbtcoutsrc_StackOperationNotify(PBTC_COEXIST pBtCoexist, u8 type) @@ -3225,50 +3940,77 @@ void EXhalbtcoutsrc_halt_notify(PBTC_COEXIST pBtCoexist) if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; + pBtCoexist->statistics.cnt_halt_notify++; + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_halt_notify(pBtCoexist); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_halt_notify(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_halt_notify(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_halt_notify(pBtCoexist); } +#endif } void EXhalbtcoutsrc_SwitchBtTRxMask(PBTC_COEXIST pBtCoexist) @@ -3287,51 +4029,77 @@ void EXhalbtcoutsrc_pnp_notify(PBTC_COEXIST pBtCoexist, u8 pnpState) if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) return; + pBtCoexist->statistics.cnt_pnp_notify++; + /* */ /* currently only 1ant we have to do the notification, */ /* once pnp is notified to sleep state, we have to leave LPS that we can sleep normally. */ /* */ - if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_pnp_notify(pBtCoexist, pnpState); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_pnp_notify(pBtCoexist, pnpState); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_pnp_notify(pBtCoexist, pnpState); - else + } #endif + +#ifdef CONFIG_RTL8821A + else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_pnp_notify(pBtCoexist, pnpState); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_pnp_notify(pBtCoexist, pnpState); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_pnp_notify(pBtCoexist, pnpState); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_pnp_notify(pBtCoexist, pnpState); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_pnp_notify(pBtCoexist, pnpState); } +#endif } void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist) @@ -3343,6 +4111,7 @@ void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist) halbtcoutsrc_LeaveLowPower(pBtCoexist); if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 1) { pBtCoexist->stop_coex_dm = TRUE; ex_halbtc8723b1ant_coex_dm_reset(pBtCoexist); @@ -3351,7 +4120,11 @@ void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist) ex_halbtc8723b2ant_init_coex_dm(pBtCoexist); pBtCoexist->stop_coex_dm = FALSE; } - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) { pBtCoexist->stop_coex_dm = TRUE; ex_halbtc8723d1ant_coex_dm_reset(pBtCoexist); @@ -3361,6 +4134,7 @@ void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist) pBtCoexist->stop_coex_dm = FALSE; } } +#endif halbtcoutsrc_NormalLowPower(pBtCoexist); } @@ -3374,53 +4148,77 @@ void EXhalbtcoutsrc_periodical(PBTC_COEXIST pBtCoexist) /* Periodical should be called in cmd thread, */ /* don't need to leave low power again * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_periodical(pBtCoexist); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) { if (!halbtcoutsrc_UnderIps(pBtCoexist)) ex_halbtc8821a1ant_periodical(pBtCoexist); } - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_periodical(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_periodical(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_periodical(pBtCoexist); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -3435,18 +4233,27 @@ void EXhalbtcoutsrc_dbg_control(PBTC_COEXIST pBtCoexist, u8 opCode, u8 opLen, u8 /* This function doesn't be called yet, */ /* default no need to leave low power to avoid deadlock * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ - if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8192E if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_dbg_control(pBtCoexist, opCode, opLen, pData); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_dbg_control(pBtCoexist, opCode, opLen, pData); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_dbg_control(pBtCoexist, opCode, opLen, pData); - } else if(IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) if(pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_dbg_control(pBtCoexist, opCode, opLen, pData); +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } @@ -3636,49 +4443,74 @@ void EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist) halbtcoutsrc_EnterPwrLock(pBtCoexist); if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) { -#if 0 - if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) - ex_halbtc8821aCsr2ant_display_coex_info(pBtCoexist); - else -#endif +#ifdef CONFIG_RTL8821A if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821a2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821a1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8723B + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723b2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8703B + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8703b1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8723D + else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8723d2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723d1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8192E + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8192e2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8192e1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8812A + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8812a1ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8822B + else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_display_coex_info(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { + } +#endif + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_display_coex_info(pBtCoexist); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_display_coex_info(pBtCoexist); } +#endif halbtcoutsrc_ExitPwrLock(pBtCoexist); @@ -3693,13 +4525,10 @@ void EXhalbtcoutsrc_DisplayAntDetection(PBTC_COEXIST pBtCoexist) halbtcoutsrc_LeaveLowPower(pBtCoexist); if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8723B if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8723b1ant_display_ant_detection(pBtCoexist); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { - if (pBtCoexist->board_info.btdm_ant_num == 2) - ex_halbtc8821c2ant_display_ant_detection(pBtCoexist); - else if (pBtCoexist->board_info.btdm_ant_num == 1) - ex_halbtc8821c1ant_display_ant_detection(pBtCoexist); +#endif } halbtcoutsrc_NormalLowPower(pBtCoexist); @@ -3707,10 +4536,12 @@ void EXhalbtcoutsrc_DisplayAntDetection(PBTC_COEXIST pBtCoexist) void ex_halbtcoutsrc_pta_off_on_notify(PBTC_COEXIST pBtCoexist, u8 bBTON) { +#ifdef CONFIG_RTL8812A if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8812a2ant_pta_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF); } +#endif } void EXhalbtcoutsrc_set_rfe_type(u8 type) @@ -3742,20 +4573,297 @@ void EXhalbtcoutsrc_switchband_notify(struct btc_coexist *pBtCoexist, u8 type) /* halbtcoutsrc_LeaveLowPower(pBtCoexist); */ if(IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) { +#ifdef CONFIG_RTL8822B if(pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8822b1ant_switchband_notify(pBtCoexist, type); else if(pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8822b2ant_switchband_notify(pBtCoexist, type); - } else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { +#endif + } + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) { if (pBtCoexist->board_info.btdm_ant_num == 2) ex_halbtc8821c2ant_switchband_notify(pBtCoexist, type); else if (pBtCoexist->board_info.btdm_ant_num == 1) ex_halbtc8821c1ant_switchband_notify(pBtCoexist, type); } +#endif /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ } +u8 EXhalbtcoutsrc_rate_id_to_btc_rate_id(u8 rate_id) +{ + u8 btc_rate_id = BTC_UNKNOWN; + + switch (rate_id) { + /* CCK rates */ + case DESC_RATE1M: + btc_rate_id = BTC_CCK_1; + break; + case DESC_RATE2M: + btc_rate_id = BTC_CCK_2; + break; + case DESC_RATE5_5M: + btc_rate_id = BTC_CCK_5_5; + break; + case DESC_RATE11M: + btc_rate_id = BTC_CCK_11; + break; + + /* OFDM rates */ + case DESC_RATE6M: + btc_rate_id = BTC_OFDM_6; + break; + case DESC_RATE9M: + btc_rate_id = BTC_OFDM_9; + break; + case DESC_RATE12M: + btc_rate_id = BTC_OFDM_12; + break; + case DESC_RATE18M: + btc_rate_id = BTC_OFDM_18; + break; + case DESC_RATE24M: + btc_rate_id = BTC_OFDM_24; + break; + case DESC_RATE36M: + btc_rate_id = BTC_OFDM_36; + break; + case DESC_RATE48M: + btc_rate_id = BTC_OFDM_48; + break; + case DESC_RATE54M: + btc_rate_id = BTC_OFDM_54; + break; + + /* MCS rates */ + case DESC_RATEMCS0: + btc_rate_id = BTC_MCS_0; + break; + case DESC_RATEMCS1: + btc_rate_id = BTC_MCS_1; + break; + case DESC_RATEMCS2: + btc_rate_id = BTC_MCS_2; + break; + case DESC_RATEMCS3: + btc_rate_id = BTC_MCS_3; + break; + case DESC_RATEMCS4: + btc_rate_id = BTC_MCS_4; + break; + case DESC_RATEMCS5: + btc_rate_id = BTC_MCS_5; + break; + case DESC_RATEMCS6: + btc_rate_id = BTC_MCS_6; + break; + case DESC_RATEMCS7: + btc_rate_id = BTC_MCS_7; + break; + case DESC_RATEMCS8: + btc_rate_id = BTC_MCS_8; + break; + case DESC_RATEMCS9: + btc_rate_id = BTC_MCS_9; + break; + case DESC_RATEMCS10: + btc_rate_id = BTC_MCS_10; + break; + case DESC_RATEMCS11: + btc_rate_id = BTC_MCS_11; + break; + case DESC_RATEMCS12: + btc_rate_id = BTC_MCS_12; + break; + case DESC_RATEMCS13: + btc_rate_id = BTC_MCS_13; + break; + case DESC_RATEMCS14: + btc_rate_id = BTC_MCS_14; + break; + case DESC_RATEMCS15: + btc_rate_id = BTC_MCS_15; + break; + case DESC_RATEMCS16: + btc_rate_id = BTC_MCS_16; + break; + case DESC_RATEMCS17: + btc_rate_id = BTC_MCS_17; + break; + case DESC_RATEMCS18: + btc_rate_id = BTC_MCS_18; + break; + case DESC_RATEMCS19: + btc_rate_id = BTC_MCS_19; + break; + case DESC_RATEMCS20: + btc_rate_id = BTC_MCS_20; + break; + case DESC_RATEMCS21: + btc_rate_id = BTC_MCS_21; + break; + case DESC_RATEMCS22: + btc_rate_id = BTC_MCS_22; + break; + case DESC_RATEMCS23: + btc_rate_id = BTC_MCS_23; + break; + case DESC_RATEMCS24: + btc_rate_id = BTC_MCS_24; + break; + case DESC_RATEMCS25: + btc_rate_id = BTC_MCS_25; + break; + case DESC_RATEMCS26: + btc_rate_id = BTC_MCS_26; + break; + case DESC_RATEMCS27: + btc_rate_id = BTC_MCS_27; + break; + case DESC_RATEMCS28: + btc_rate_id = BTC_MCS_28; + break; + case DESC_RATEMCS29: + btc_rate_id = BTC_MCS_29; + break; + case DESC_RATEMCS30: + btc_rate_id = BTC_MCS_30; + break; + case DESC_RATEMCS31: + btc_rate_id = BTC_MCS_31; + break; + + case DESC_RATEVHTSS1MCS0: + btc_rate_id = BTC_VHT_1SS_MCS_0; + break; + case DESC_RATEVHTSS1MCS1: + btc_rate_id = BTC_VHT_1SS_MCS_1; + break; + case DESC_RATEVHTSS1MCS2: + btc_rate_id = BTC_VHT_1SS_MCS_2; + break; + case DESC_RATEVHTSS1MCS3: + btc_rate_id = BTC_VHT_1SS_MCS_3; + break; + case DESC_RATEVHTSS1MCS4: + btc_rate_id = BTC_VHT_1SS_MCS_4; + break; + case DESC_RATEVHTSS1MCS5: + btc_rate_id = BTC_VHT_1SS_MCS_5; + break; + case DESC_RATEVHTSS1MCS6: + btc_rate_id = BTC_VHT_1SS_MCS_6; + break; + case DESC_RATEVHTSS1MCS7: + btc_rate_id = BTC_VHT_1SS_MCS_7; + break; + case DESC_RATEVHTSS1MCS8: + btc_rate_id = BTC_VHT_1SS_MCS_8; + break; + case DESC_RATEVHTSS1MCS9: + btc_rate_id = BTC_VHT_1SS_MCS_9; + break; + + case DESC_RATEVHTSS2MCS0: + btc_rate_id = BTC_VHT_2SS_MCS_0; + break; + case DESC_RATEVHTSS2MCS1: + btc_rate_id = BTC_VHT_2SS_MCS_1; + break; + case DESC_RATEVHTSS2MCS2: + btc_rate_id = BTC_VHT_2SS_MCS_2; + break; + case DESC_RATEVHTSS2MCS3: + btc_rate_id = BTC_VHT_2SS_MCS_3; + break; + case DESC_RATEVHTSS2MCS4: + btc_rate_id = BTC_VHT_2SS_MCS_4; + break; + case DESC_RATEVHTSS2MCS5: + btc_rate_id = BTC_VHT_2SS_MCS_5; + break; + case DESC_RATEVHTSS2MCS6: + btc_rate_id = BTC_VHT_2SS_MCS_6; + break; + case DESC_RATEVHTSS2MCS7: + btc_rate_id = BTC_VHT_2SS_MCS_7; + break; + case DESC_RATEVHTSS2MCS8: + btc_rate_id = BTC_VHT_2SS_MCS_8; + break; + case DESC_RATEVHTSS2MCS9: + btc_rate_id = BTC_VHT_2SS_MCS_9; + break; + + case DESC_RATEVHTSS3MCS0: + btc_rate_id = BTC_VHT_3SS_MCS_0; + break; + case DESC_RATEVHTSS3MCS1: + btc_rate_id = BTC_VHT_3SS_MCS_1; + break; + case DESC_RATEVHTSS3MCS2: + btc_rate_id = BTC_VHT_3SS_MCS_2; + break; + case DESC_RATEVHTSS3MCS3: + btc_rate_id = BTC_VHT_3SS_MCS_3; + break; + case DESC_RATEVHTSS3MCS4: + btc_rate_id = BTC_VHT_3SS_MCS_4; + break; + case DESC_RATEVHTSS3MCS5: + btc_rate_id = BTC_VHT_3SS_MCS_5; + break; + case DESC_RATEVHTSS3MCS6: + btc_rate_id = BTC_VHT_3SS_MCS_6; + break; + case DESC_RATEVHTSS3MCS7: + btc_rate_id = BTC_VHT_3SS_MCS_7; + break; + case DESC_RATEVHTSS3MCS8: + btc_rate_id = BTC_VHT_3SS_MCS_8; + break; + case DESC_RATEVHTSS3MCS9: + btc_rate_id = BTC_VHT_3SS_MCS_9; + break; + + case DESC_RATEVHTSS4MCS0: + btc_rate_id = BTC_VHT_4SS_MCS_0; + break; + case DESC_RATEVHTSS4MCS1: + btc_rate_id = BTC_VHT_4SS_MCS_1; + break; + case DESC_RATEVHTSS4MCS2: + btc_rate_id = BTC_VHT_4SS_MCS_2; + break; + case DESC_RATEVHTSS4MCS3: + btc_rate_id = BTC_VHT_4SS_MCS_3; + break; + case DESC_RATEVHTSS4MCS4: + btc_rate_id = BTC_VHT_4SS_MCS_4; + break; + case DESC_RATEVHTSS4MCS5: + btc_rate_id = BTC_VHT_4SS_MCS_5; + break; + case DESC_RATEVHTSS4MCS6: + btc_rate_id = BTC_VHT_4SS_MCS_6; + break; + case DESC_RATEVHTSS4MCS7: + btc_rate_id = BTC_VHT_4SS_MCS_7; + break; + case DESC_RATEVHTSS4MCS8: + btc_rate_id = BTC_VHT_4SS_MCS_8; + break; + case DESC_RATEVHTSS4MCS9: + btc_rate_id = BTC_VHT_4SS_MCS_9; + break; + } + + return btc_rate_id; +} + static void halbt_init_hw_config92C(PADAPTER padapter) { PHAL_DATA_TYPE pHalData; @@ -3869,10 +4977,6 @@ u8 hal_btcoex_Initialize(PADAPTER padapter) _rtw_memset(&GLBtCoexist, 0, sizeof(GLBtCoexist)); - hal_btcoex_SetBTCoexist(padapter, rtw_btcoex_get_bt_coexist(padapter)); - hal_btcoex_SetChipType(padapter, rtw_btcoex_get_chip_type(padapter)); - hal_btcoex_SetPgAntNum(padapter, rtw_btcoex_get_pg_ant_num(padapter)); - ret = EXhalbtcoutsrc_InitlizeVariables((void *)padapter); return ret; @@ -3883,6 +4987,15 @@ void hal_btcoex_PowerOnSetting(PADAPTER padapter) EXhalbtcoutsrc_PowerOnSetting(&GLBtCoexist); } +void hal_btcoex_AntInfoSetting(PADAPTER padapter) +{ + hal_btcoex_SetBTCoexist(padapter, rtw_btcoex_get_bt_coexist(padapter)); + hal_btcoex_SetChipType(padapter, rtw_btcoex_get_chip_type(padapter)); + hal_btcoex_SetPgAntNum(padapter, rtw_btcoex_get_pg_ant_num(padapter)); + + EXhalbtcoutsrc_AntInfoSetting(padapter); +} + void hal_btcoex_PowerOffSetting(PADAPTER padapter) { /* Clear the WiFi on/off bit in scoreboard reg. if necessary */ @@ -3922,7 +5035,25 @@ void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type) void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action) { - EXhalbtcoutsrc_connect_notify(&GLBtCoexist, action); + u8 assoType = 0; + u8 is_5g_band = _FALSE; + + is_5g_band = (padapter->mlmeextpriv.cur_channel > 14) ? _TRUE : _FALSE; + + if (action == _TRUE) { + if (is_5g_band == _TRUE) + assoType = BTC_ASSOCIATE_5G_START; + else + assoType = BTC_ASSOCIATE_START; + } + else { + if (is_5g_band == _TRUE) + assoType = BTC_ASSOCIATE_5G_FINISH; + else + assoType = BTC_ASSOCIATE_FINISH; + } + + EXhalbtcoutsrc_connect_notify(&GLBtCoexist, assoType); } void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus) @@ -3953,7 +5084,7 @@ void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) u8 extid, status, len, seq; - if (!GLBtcBtMpRptWait) + if (GLBtcBtMpRptWait == _FALSE) return; if ((length < 3) || (!tmpBuf)) @@ -3963,28 +5094,32 @@ void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) /* not response from BT FW then exit*/ switch (extid) { case C2H_WIFI_FW_ACTIVE_RSP: - GLBtcBtMpRptWiFiOK = 1; - return; + GLBtcBtMpRptWiFiOK = _TRUE; + break; case C2H_TRIG_BY_BT_FW: - _cancel_timer_ex(&GLBtcBtMpOperTimer); - GLBtcBtMpRptWait = 0; - GLBtcBtMpRptBTOK = 1; + GLBtcBtMpRptBTOK = _TRUE; + + status = tmpBuf[1] & 0xF; + len = length - 3; + seq = tmpBuf[2] >> 4; + + GLBtcBtMpRptSeq = seq; + GLBtcBtMpRptStatus = status; + _rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf + 3, len); + GLBtcBtMpRptRspSize = len; + break; default: return; } - status = tmpBuf[1] & 0xF; - len = length - 3; - seq = tmpBuf[2] >> 4; - - GLBtcBtMpRptSeq = seq; - GLBtcBtMpRptStatus = status; - _rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf + 3, len); - GLBtcBtMpRptRspSize = len; - _rtw_up_sema(&GLBtcBtMpRptSema); + if ((GLBtcBtMpRptWiFiOK == _TRUE) && (GLBtcBtMpRptBTOK == _TRUE)) { + GLBtcBtMpRptWait = _FALSE; + _cancel_timer_ex(&GLBtcBtMpOperTimer); + _rtw_up_sema(&GLBtcBtMpRptSema); + } } void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state) @@ -4003,6 +5138,10 @@ void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state) #endif break; case BTCOEX_SUSPEND_STATE_RESUME: +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + /* re-download FW after resume, inform WL FW port number */ + rtw_hal_set_wifi_btc_port_id_cmd(GLBtCoexist.Adapter); +#endif EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_WAKE_UP); break; } @@ -4547,4 +5686,14 @@ void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type) break; } } + +void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length) +{ + EXhalbtcoutsrc_WlFwDbgInfoNotify(&GLBtCoexist, tmpBuf, length); +} + +void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id) +{ + EXhalbtcoutsrc_rx_rate_change_notify(&GLBtCoexist, is_data_frame, EXhalbtcoutsrc_rate_id_to_btc_rate_id(rate_id)); +} #endif /* CONFIG_BT_COEXIST */ diff --git a/hal/hal_btcoex_wifionly.c b/hal/hal_btcoex_wifionly.c index 861bcfb..0f82bbb 100644 --- a/hal/hal_btcoex_wifionly.c +++ b/hal/hal_btcoex_wifionly.c @@ -1,6 +1,23 @@ -#include "btc/mp_precomp.h" +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #include +#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1) + +#include "btc/mp_precomp.h" + struct wifi_only_cfg GLBtCoexistWifiOnly; void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data) @@ -71,7 +88,7 @@ void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMa rtw_write8(Adapter, regAddr, data); } -void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data) { struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; PADAPTER Adapter = pwifionlycfg->Adapter; @@ -95,10 +112,16 @@ void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter) if (pHalData->current_band_type == BAND_ON_5G) is_5g = _TRUE; - if (IS_HARDWARE_TYPE_8822B(padapter)) + if (IS_HARDWARE_TYPE_8822B(padapter)) { +#ifdef CONFIG_RTL8822B ex_hal8822b_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g); +#endif + } + +#ifdef CONFIG_RTL8821C else if (IS_HARDWARE_TYPE_8821C(padapter)) ex_hal8821c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g); +#endif } void hal_btcoex_wifionly_scan_notify(PADAPTER padapter) @@ -109,22 +132,57 @@ void hal_btcoex_wifionly_scan_notify(PADAPTER padapter) if (pHalData->current_band_type == BAND_ON_5G) is_5g = _TRUE; - if (IS_HARDWARE_TYPE_8822B(padapter)) + if (IS_HARDWARE_TYPE_8822B(padapter)) { +#ifdef CONFIG_RTL8822B ex_hal8822b_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g); +#endif + } + +#ifdef CONFIG_RTL8821C else if (IS_HARDWARE_TYPE_8821C(padapter)) ex_hal8821c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g); +#endif +} + +void hal_btcoex_wifionly_connect_notify(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 is_5g = _FALSE; + + if (pHalData->current_band_type == BAND_ON_5G) + is_5g = _TRUE; + + if (IS_HARDWARE_TYPE_8822B(padapter)) { +#ifdef CONFIG_RTL8822B + ex_hal8822b_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g); +#endif + } + +#ifdef CONFIG_RTL8821C + else if (IS_HARDWARE_TYPE_8821C(padapter)) + ex_hal8821c_wifi_only_connectnotify(&GLBtCoexistWifiOnly, is_5g); +#endif } void hal_btcoex_wifionly_hw_config(PADAPTER padapter) { struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly; - if (IS_HARDWARE_TYPE_8723B(padapter)) + if (IS_HARDWARE_TYPE_8723B(padapter)) { +#ifdef CONFIG_RTL8723B ex_hal8723b_wifi_only_hw_config(pwifionlycfg); +#endif + } + +#ifdef CONFIG_RTL8822B else if (IS_HARDWARE_TYPE_8822B(padapter)) ex_hal8822b_wifi_only_hw_config(pwifionlycfg); +#endif + +#ifdef CONFIG_RTL8821C else if (IS_HARDWARE_TYPE_8821C(padapter)) ex_hal8821c_wifi_only_hw_config(pwifionlycfg); +#endif } void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter) @@ -148,9 +206,19 @@ void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter) #endif pwifionly_haldata->customer_id = CUSTOMER_NORMAL; +} + +void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter) +{ + struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly; + struct wifi_only_haldata *pwifionly_haldata = &pwifionlycfg->haldata_info; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + pwifionly_haldata->efuse_pg_antnum = pHalData->EEPROMBluetoothAntNum; pwifionly_haldata->efuse_pg_antpath = pHalData->ant_path; pwifionly_haldata->rfe_type = pHalData->rfe_type; pwifionly_haldata->ant_div_cfg = pHalData->AntDivCfg; } +#endif + diff --git a/hal/hal_com.c b/hal/hal_com.c index f3c4dca..cacb3ef 100644 --- a/hal/hal_com.c +++ b/hal/hal_com.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_COM_C_ #include @@ -36,7 +31,7 @@ void rtw_dump_fw_info(void *sel, _adapter *adapter) return; hal_data = GET_HAL_DATA(adapter); - if (adapter->bFWReady) + if (hal_data->bFWReady) RTW_PRINT_SEL(sel, "FW VER -%d.%d\n", hal_data->firmware_version, hal_data->firmware_sub_version); else RTW_PRINT_SEL(sel, "FW not ready\n"); @@ -52,7 +47,7 @@ void rtw_hal_move_sta_gk_to_dk(_adapter *adapter) int cam_id, index = 0; u8 *addr = NULL; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (!MLME_IS_STA(adapter)) return; addr = get_bssid(pmlmepriv); @@ -119,6 +114,8 @@ void dump_chip_info(HAL_VERSION ChipVersion) cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188E_"); else if (IS_8188F(ChipVersion)) cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188F_"); + else if (IS_8188GTV(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188GTV_"); else if (IS_8812_SERIES(ChipVersion)) cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8812_"); else if (IS_8192E(ChipVersion)) @@ -137,6 +134,11 @@ void dump_chip_info(HAL_VERSION ChipVersion) cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8822B_"); else if (IS_8821C_SERIES(ChipVersion)) cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8821C_"); + else if (IS_8710B_SERIES(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8710B_"); + else if (IS_8192F_SERIES(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8192F_"); + else cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_UNKNOWN_"); @@ -188,6 +190,38 @@ void dump_chip_info(HAL_VERSION ChipVersion) RTW_INFO("%s", buf); } + +u8 rtw_hal_get_port(_adapter *adapter) +{ + u8 hw_port = get_hw_port(adapter); +#ifdef CONFIG_CLIENT_PORT_CFG + u8 clt_port = get_clt_port(adapter); + + if (clt_port) + hw_port = clt_port; + +#ifdef DBG_HW_PORT + if (MLME_IS_STA(adapter) && (adapter->client_id != MAX_CLIENT_PORT_NUM)) { + if(hw_port == CLT_PORT_INVALID) { + RTW_ERR(ADPT_FMT" @@@@@ Client port == 0 @@@@@\n", ADPT_ARG(adapter)); + rtw_warn_on(1); + } + } + else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) { + if (hw_port != HW_PORT0) { + RTW_ERR(ADPT_FMT" @@@@@ AP / MESH port != 0 @@@@@\n", ADPT_ARG(adapter)); + rtw_warn_on(1); + } + } + if (0) + RTW_INFO(ADPT_FMT" - HP:%d,CP:%d\n", ADPT_ARG(adapter), get_hw_port(adapter), get_clt_port(adapter)); +#endif /*DBG_HW_PORT*/ + +#endif/*CONFIG_CLIENT_PORT_CFG*/ + + return hw_port; +} + void rtw_hal_config_rftype(PADAPTER padapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); @@ -233,11 +267,8 @@ void rtw_hal_config_rftype(PADAPTER padapter) * def_chplan channel plan used when HW/SW both invalid * AutoLoadFail efuse autoload fail or not * - * Return: - * Final channel plan decision - * */ -u8 hal_com_config_channel_plan( +void hal_com_config_channel_plan( IN PADAPTER padapter, IN char *hw_alpha2, IN u8 hw_chplan, @@ -247,6 +278,7 @@ u8 hal_com_config_channel_plan( IN BOOLEAN AutoLoadFail ) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); PHAL_DATA_TYPE pHalData; u8 force_hw_chplan = _FALSE; int chplan = -1; @@ -307,7 +339,7 @@ u8 hal_com_config_channel_plan( /* cancel hw_alpha2 because chplan is specified by sw_chplan*/ country_ent = NULL; chplan = sw_chplan; - } else if (sw_chplan != RTW_CHPLAN_MAX) + } else if (sw_chplan != RTW_CHPLAN_UNSPECIFIED) RTW_PRINT("%s unsupported sw_chplan:0x%02X\n", __func__, sw_chplan); done: @@ -320,10 +352,9 @@ u8 hal_com_config_channel_plan( } else RTW_PRINT("%s chplan:0x%02X\n", __func__, chplan); - padapter->mlmepriv.country_ent = country_ent; + rfctl->country_ent = country_ent; + rfctl->ChannelPlan = chplan; pHalData->bDisableSWChannelPlan = force_hw_chplan; - - return chplan; } BOOLEAN @@ -1104,6 +1135,8 @@ Hal_MappingOutPipe( break; case 3: case 4: + case 5: + case 6: _ThreeOutPipeMapping(pAdapter, bWIFICfg); break; case 1: @@ -1137,7 +1170,7 @@ void rtw_hal_dump_macaddr(void *sel, _adapter *adapter) for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (iface) { - rtw_hal_get_macaddr_port(iface, mac_addr); + rtw_hal_get_hwreg(iface, HW_VAR_MAC_ADDR, mac_addr); RTW_PRINT_SEL(sel, ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", ADPT_ARG(iface), iface->hw_port, MAC_ARG(mac_addr)); } @@ -1145,13 +1178,59 @@ void rtw_hal_dump_macaddr(void *sel, _adapter *adapter) #endif } -void rtw_restore_mac_addr(_adapter *adapter) +#ifdef RTW_HALMAC +void rtw_hal_hw_port_enable(_adapter *adapter) +{ +#if 1 + u8 port_enable = _TRUE; + + rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable); +#else + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rtw_halmac_bcn_ctrl bcn_ctrl; + + _rtw_memset(&bcn_ctrl, 0, sizeof(struct rtw_halmac_bcn_ctrl)); + bcn_ctrl.enable_bcn = 1; + bcn_ctrl.rx_bssid_fit = 1; + bcn_ctrl.rxbcn_rpt = 1; + + /*rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, + struct rtw_halmac_bcn_ctrl *bcn_ctrl)*/ + if (rtw_halmac_set_bcn_ctrl(dvobj, get_hw_port(adapter), &bcn_ctrl) == -1) { + RTW_ERR(ADPT_FMT" - hw port(%d) enable fail!!\n", ADPT_ARG(adapter), get_hw_port(adapter)); + rtw_warn_on(1); + } +#endif +} +void rtw_hal_hw_port_disable(_adapter *adapter) +{ + u8 port_enable = _FALSE; + + rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable); +} + +void rtw_restore_hw_port_cfg(_adapter *adapter) { #ifdef CONFIG_MI_WITH_MBSSID_CAM + +#else + int i; _adapter *iface; struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - rtw_mbid_cam_restore(adapter); + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) + rtw_hal_hw_port_enable(iface); + } +#endif +} +#endif + +void rtw_mi_set_mac_addr(_adapter *adapter) +{ +#ifdef CONFIG_MI_WITH_MBSSID_CAM + rtw_mi_set_mbid_cam(adapter); #else int i; _adapter *iface; @@ -1160,7 +1239,7 @@ void rtw_restore_mac_addr(_adapter *adapter) for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (iface) - rtw_hal_set_macaddr_port(iface, adapter_mac_addr(iface)); + rtw_hal_set_hwreg(iface, HW_VAR_MAC_ADDR, adapter_mac_addr(iface)); } #endif if (1) @@ -1174,7 +1253,12 @@ void rtw_init_hal_com_default_value(PADAPTER Adapter) pHalData->AntDetection = 1; pHalData->antenna_test = _FALSE; - pHalData->u1ForcedIgiLb = regsty->force_igi_lb; + pHalData->RegIQKFWOffload = regsty->iqk_fw_offload; + pHalData->ch_switch_offload = regsty->ch_switch_offload; +#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME + if (pHalData->ch_switch_offload == 0) + pHalData->ch_switch_offload = 1; +#endif } #ifdef CONFIG_FW_C2H_REG @@ -1216,7 +1300,7 @@ s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf) for (i = 0; i < C2H_PLEN_88XX(buf); i++) *(C2H_PAYLOAD_88XX(buf) + i) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i); - RTW_DBG_DUMP("payload:\n", C2H_PAYLOAD_88XX(buf), C2H_PLEN_88XX(buf)); + RTW_DBG_DUMP("payload: ", C2H_PAYLOAD_88XX(buf), C2H_PLEN_88XX(buf)); ret = _SUCCESS; @@ -1350,7 +1434,6 @@ int c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms) #define GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 4) #define GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 4, 4) #define GET_C2H_MAC_HIDDEN_RPT_BW(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 3) -#define GET_C2H_MAC_HIDDEN_RPT_FAB(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 3, 2) #define GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 5, 3) #define GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 2, 2) #define GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 6, 2) @@ -1378,7 +1461,6 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len) u8 wl_func; u8 hw_stype; u8 bw; - u8 fab; u8 ant_num; u8 protocol; u8 nic; @@ -1404,7 +1486,6 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len) hw_stype = GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(data); bw = GET_C2H_MAC_HIDDEN_RPT_BW(data); - fab = GET_C2H_MAC_HIDDEN_RPT_FAB(data); ant_num = GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(data); protocol = GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(data); @@ -1421,7 +1502,6 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len) RTW_PRINT("wl_func:0x%x\n", wl_func); RTW_PRINT("hw_stype:0x%x\n", hw_stype); RTW_PRINT("bw:0x%x\n", bw); - RTW_PRINT("fab:0x%x\n", fab); RTW_PRINT("ant_num:0x%x\n", ant_num); RTW_PRINT("protocol:0x%x\n", protocol); RTW_PRINT("nic:0x%x\n", nic); @@ -1442,7 +1522,6 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len) hal_spec->hci_type = hci_type; /* TODO: tr_switch */ - /* TODO: fab */ ret = _SUCCESS; @@ -1468,6 +1547,19 @@ int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len) RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i)); } + #if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) + if (IS_8188F(hal_data->version_id) || IS_8188GTV(hal_data->version_id)) { + #define GET_C2H_MAC_HIDDEN_RPT_IRV(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 4) + u8 irv = GET_C2H_MAC_HIDDEN_RPT_IRV(data); + + if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) + RTW_PRINT("irv:0x%x\n", irv); + + if(irv != 0xf) + hal_data->version_id.CUTVersion = irv; + } + #endif + ret = _SUCCESS; exit: @@ -1480,7 +1572,7 @@ int hal_read_mac_hidden_rpt(_adapter *adapter) int ret = _FAIL; int ret_fwdl; u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN] = {0}; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); u32 cnt = 0; u32 timeout_ms = 800; u32 min_cnt = 10; @@ -1791,22 +1883,191 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs) } #endif /* CONFIG_RTW_CUSTOMER_STR */ -u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta) +#ifdef RTW_PER_CMD_SUPPORT_FW +#define H2C_REQ_PER_RPT_LEN 5 +#define SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) +#define SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd + 1, 0, 32, __Value) + +u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid, + u8 rpt_type, u32 macid_bitmap) +{ + u8 ret = _FAIL; + u8 cmd_buf[H2C_REQ_PER_RPT_LEN] = {0}; + + SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(cmd_buf, group_macid); + SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(cmd_buf, rpt_type); + SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(cmd_buf, macid_bitmap); + + ret = rtw_hal_fill_h2c_cmd(adapter, + H2C_REQ_PER_RPT, + H2C_REQ_PER_RPT_LEN, + cmd_buf); + return ret; +} + +#define GET_C2H_PER_RATE_RPT_TYPE0_MACID0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_PER0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_RATE0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_BW0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2) +#define GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(_data) LE_BITS_TO_2BYTE(((u8 *)(_data)) + 4, 0, 16) +#define GET_C2H_PER_RATE_RPT_TYPE0_MACID1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_PER1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_RATE1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE0_BW1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 2) +#define GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(_data) LE_BITS_TO_2BYTE(((u8 *)(_data)) + 10, 0, 16) + +#define GET_C2H_PER_RATE_RPT_TYPE1_MACID0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_PER0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_RATE0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_BW0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2) +#define GET_C2H_PER_RATE_RPT_TYPE1_MACID1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_PER1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_RATE1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_BW1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 2) +#define GET_C2H_PER_RATE_RPT_TYPE1_MACID2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_PER2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_RATE2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 10, 0, 8) +#define GET_C2H_PER_RATE_RPT_TYPE1_BW2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 11, 0, 2) + +static void per_rate_rpt_update(_adapter *adapter, u8 mac_id, + u8 per, u8 rate, + u8 bw, u8 total_pkt) +{ +#ifdef CONFIG_RTW_MESH + rtw_ieee80211s_update_metric(adapter, mac_id, + per, rate, + bw, total_pkt); +#endif +} + +int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len) +{ + /* Now only consider type0, since it covers all params in type1 + * type0: mac_id, per, rate, bw, total_pkt + * type1: mac_id, per, rate, bw + */ + u8 mac_id[2] = {0}, per[2] = {0}, rate[2] = {0}, bw[2] = {0}; + u16 total_pkt[2] = {0}; + int ret = _FAIL, i, macid_cnt = 0; + + /* type0: + * 1 macid includes 6 bytes info + 1 byte 0xff + * 2 macid includes 2*6 bytes info + */ + if (!(len == 7 || len == 12)) { + RTW_WARN("%s len(%u) != 7 or 12\n", __FUNCTION__, len); + goto exit; + } + + macid_cnt++; + mac_id[0] = GET_C2H_PER_RATE_RPT_TYPE0_MACID0(data); + per[0] = GET_C2H_PER_RATE_RPT_TYPE0_PER0(data); + rate[0] = GET_C2H_PER_RATE_RPT_TYPE0_RATE0(data); + bw[0] = GET_C2H_PER_RATE_RPT_TYPE0_BW0(data); + total_pkt[0] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(data); + + mac_id[1] = GET_C2H_PER_RATE_RPT_TYPE0_MACID1(data); + /* 0xff means no report anymore */ + if (mac_id[1] == 0xff) + goto update_per; + if (len != 12) { + RTW_WARN("%s incorrect format\n", __FUNCTION__); + goto exit; + } + macid_cnt++; + per[1] = GET_C2H_PER_RATE_RPT_TYPE0_PER1(data); + rate[1] = GET_C2H_PER_RATE_RPT_TYPE0_RATE1(data); + bw[1] = GET_C2H_PER_RATE_RPT_TYPE0_BW1(data); + total_pkt[1] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(data); + +update_per: + for (i = 0; i < macid_cnt; i++) { + RTW_DBG("[%s] type0 rpt[%d]: macid = %u, per = %u, " + "rate = %u, bw = %u, total_pkt = %u\n", + __FUNCTION__, i, mac_id[i], per[i], + rate[i], bw[i], total_pkt[i]); + per_rate_rpt_update(adapter, mac_id[i], + per[i], rate[i], + bw[i], total_pkt[i]); + } + ret = _SUCCESS; +exit: + return ret; +} +#endif /* RTW_PER_CMD_SUPPORT_FW */ + +void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta) +{ + u8 w_set = 0; + + if (psta->wireless_mode & WIRELESS_11B) + w_set |= WIRELESS_CCK; + + if ((psta->wireless_mode & WIRELESS_11G) || (psta->wireless_mode & WIRELESS_11A)) + w_set |= WIRELESS_OFDM; + + if (psta->wireless_mode & WIRELESS_11_24N) + w_set |= WIRELESS_HT; + + if ((psta->wireless_mode & WIRELESS_11AC) || (psta->wireless_mode & WIRELESS_11_5N)) + w_set |= WIRELESS_VHT; + + psta->cmn.support_wireless_set = w_set; +} + +void rtw_hal_update_sta_mimo_type(_adapter *adapter, struct sta_info *psta) { -#ifdef CONFIG_GET_RAID_BY_DRV /*Just for 8188E now*/ - if (IS_NEW_GENERATION_IC(adapter)) - return networktype_to_raid_ex(adapter, psta); + s8 tx_nss, rx_nss; + + tx_nss = rtw_get_sta_tx_nss(adapter, psta); + rx_nss = rtw_get_sta_rx_nss(adapter, psta); + if ((tx_nss == 1) && (rx_nss == 1)) + psta->cmn.mimo_type = RF_1T1R; + else if ((tx_nss == 1) && (rx_nss == 2)) + psta->cmn.mimo_type = RF_1T2R; + else if ((tx_nss == 2) && (rx_nss == 2)) + psta->cmn.mimo_type = RF_2T2R; + else if ((tx_nss == 2) && (rx_nss == 3)) + psta->cmn.mimo_type = RF_2T3R; + else if ((tx_nss == 2) && (rx_nss == 4)) + psta->cmn.mimo_type = RF_2T4R; + else if ((tx_nss == 3) && (rx_nss == 3)) + psta->cmn.mimo_type = RF_3T3R; + else if ((tx_nss == 3) && (rx_nss == 4)) + psta->cmn.mimo_type = RF_3T4R; + else if ((tx_nss == 4) && (rx_nss == 4)) + psta->cmn.mimo_type = RF_4T4R; else - return networktype_to_raid(adapter, psta); -#else - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - u8 bw; + rtw_warn_on(1); - bw = rtw_get_tx_bw_mode(adapter, psta); + RTW_INFO("STA - MAC_ID:%d, Tx - %d SS, Rx - %d SS\n", + psta->cmn.mac_id, tx_nss, rx_nss); +} - return phydm_rate_id_mapping(&pHalData->odmpriv, psta->wireless_mode, pHalData->rf_type, bw); +void rtw_hal_update_sta_smps_cap(_adapter *adapter, struct sta_info *psta) +{ + /*Spatial Multiplexing Power Save*/ +#if 0 + if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + #ifdef CONFIG_80211N_HT + if (psta->htpriv.ht_option) { + if (psta->htpriv.smps_cap == 0) + psta->cmn.sm_ps = SM_PS_STATIC; + else if (psta->htpriv.smps_cap == 1) + psta->cmn.sm_ps = SM_PS_DYNAMIC; + else + psta->cmn.sm_ps = SM_PS_DISABLE; + } + #endif /* CONFIG_80211N_HT */ + } else #endif + psta->cmn.sm_ps = SM_PS_DISABLE; + + RTW_INFO("STA - MAC_ID:%d, SM_PS %d\n", + psta->cmn.mac_id, psta->cmn.sm_ps); } + u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type) { @@ -1826,13 +2087,11 @@ void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta) { struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); u8 i, rf_type, tx_nss; - u64 tx_ra_bitmap; + u64 tx_ra_bitmap = 0, tmp64=0; if (psta == NULL) return; - tx_ra_bitmap = 0; - /* b/g mode ra_bitmap */ for (i = 0; i < sizeof(psta->bssrateset); i++) { if (psta->bssrateset[i]) @@ -1840,6 +2099,7 @@ void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta) } #ifdef CONFIG_80211N_HT +if (padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) { rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); #ifdef CONFIG_80211AC_VHT @@ -1860,13 +2120,146 @@ void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta) } } - tx_ra_bitmap |= (rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss) << 12); + tmp64 = rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss); + tx_ra_bitmap |= (tmp64 << 12); } +} #endif /* CONFIG_80211N_HT */ - psta->ra_mask = tx_ra_bitmap; + psta->cmn.ra_info.ramask = tx_ra_bitmap; psta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f; } +void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta) +{ + rtw_hal_update_sta_mimo_type(padapter, psta); + rtw_hal_update_sta_smps_cap(padapter, psta); + rtw_hal_update_sta_rate_mask(padapter, psta); +} + +static u32 hw_bcn_ctrl_addr(_adapter *adapter, u8 hw_port) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + + if (hw_port >= hal_spec->port_num) { + RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port); + rtw_warn_on(1); + return 0; + } + + switch (hw_port) { + case HW_PORT0: + return REG_BCN_CTRL; + case HW_PORT1: + return REG_BCN_CTRL_1; + } + + return 0; +} + +static void rtw_hal_get_msr(_adapter *adapter, u8 *net_type) +{ +#ifdef RTW_HALMAC + rtw_halmac_get_network_type(adapter_to_dvobj(adapter), + adapter->hw_port, net_type); +#else /* !RTW_HALMAC */ + switch (adapter->hw_port) { + case HW_PORT0: + /*REG_CR - BIT[17:16]-Network Type for port 1*/ + *net_type = rtw_read8(adapter, MSR) & 0x03; + break; + case HW_PORT1: + /*REG_CR - BIT[19:18]-Network Type for port 1*/ + *net_type = (rtw_read8(adapter, MSR) & 0x0C) >> 2; + break; +#if defined(CONFIG_RTL8814A) + case HW_PORT2: + /*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/ + *net_type = rtw_read8(adapter, MSR1) & 0x03; + break; + case HW_PORT3: + /*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/ + *net_type = (rtw_read8(adapter, MSR1) & 0x0C) >> 2; + break; + case HW_PORT4: + /*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/ + *net_type = (rtw_read8(adapter, MSR1) & 0x30) >> 4; + break; +#endif /*#if defined(CONFIG_RTL8814A)*/ + default: + RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n", + ADPT_ARG(adapter), adapter->hw_port); + rtw_warn_on(1); + break; + } +#endif /* !RTW_HALMAC */ +} + +#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) /*For 2 hw ports - 88E/92E/8812/8821/8723B*/ +static u8 rtw_hal_net_type_decision(_adapter *adapter, u8 net_type) +{ + if ((adapter->hw_port == HW_PORT0) && (rtw_get_mbid_cam_entry_num(adapter))) { + if (net_type != _HW_STATE_NOLINK_) + return _HW_STATE_AP_; + } + return net_type; +} +#endif +static void rtw_hal_set_msr(_adapter *adapter, u8 net_type) +{ +#ifdef RTW_HALMAC + #if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) + net_type = rtw_hal_net_type_decision(adapter, net_type); + #endif + rtw_halmac_set_network_type(adapter_to_dvobj(adapter), + adapter->hw_port, net_type); +#else /* !RTW_HALMAC */ + u8 val8 = 0; + + switch (adapter->hw_port) { + case HW_PORT0: + #if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) + net_type = rtw_hal_net_type_decision(adapter, net_type); + #endif + /*REG_CR - BIT[17:16]-Network Type for port 0*/ + val8 = rtw_read8(adapter, MSR) & 0x0C; + val8 |= net_type; + rtw_write8(adapter, MSR, val8); + break; + case HW_PORT1: + /*REG_CR - BIT[19:18]-Network Type for port 1*/ + val8 = rtw_read8(adapter, MSR) & 0x03; + val8 |= net_type << 2; + rtw_write8(adapter, MSR, val8); + break; +#if defined(CONFIG_RTL8814A) + case HW_PORT2: + /*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/ + val8 = rtw_read8(adapter, MSR1) & 0xFC; + val8 |= net_type; + rtw_write8(adapter, MSR1, val8); + break; + case HW_PORT3: + /*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/ + val8 = rtw_read8(adapter, MSR1) & 0xF3; + val8 |= net_type << 2; + rtw_write8(adapter, MSR1, val8); + break; + case HW_PORT4: + /*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/ + val8 = rtw_read8(adapter, MSR1) & 0xCF; + val8 |= net_type << 4; + rtw_write8(adapter, MSR1, val8); + break; +#endif /* CONFIG_RTL8814A */ + default: + RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n", + ADPT_ARG(adapter), adapter->hw_port); + rtw_warn_on(1); + break; + } +#endif /* !RTW_HALMAC */ +} + #ifndef SEC_CAM_ACCESS_TIMEOUT_MS #define SEC_CAM_ACCESS_TIMEOUT_MS 200 #endif @@ -1880,7 +2273,7 @@ u32 rtw_sec_read_cam(_adapter *adapter, u8 addr) _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex; u32 rdata; u32 cnt = 0; - u32 start = 0, end = 0; + systime start = 0, end = 0; u8 timeout = 0; u8 sr = 0; @@ -1922,7 +2315,7 @@ void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata) { _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex; u32 cnt = 0; - u32 start = 0, end = 0; + systime start = 0, end = 0; u8 timeout = 0; u8 sr = 0; @@ -2010,8 +2403,8 @@ void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) { unsigned int i; int j; - u8 addr; - u32 wdata; + u8 addr, addr1 = 0; + u32 wdata, wdata1 = 0; /* TODO: consider other key length accordingly */ #if 0 @@ -2046,8 +2439,20 @@ void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) addr = (id << 3) + j; +#if defined(CONFIG_RTL8192F) + if(j == 1) { + wdata1 = wdata; + addr1 = addr; + continue; + } +#endif + rtw_sec_write_cam(adapter, addr, wdata); } + +#if defined(CONFIG_RTL8192F) + rtw_sec_write_cam(adapter, addr1, wdata1); +#endif } void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id) @@ -2213,14 +2618,14 @@ u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr) struct mbid_cam_ctl_t *mbid_cam_ctl = &dvobj->mbid_cam_ctl; u8 entry_num = ATOMIC_READ(&mbid_cam_ctl->mbid_entry_num); + if (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr)) + goto exit; + if (entry_num >= TOTAL_MBID_CAM_NUM) { RTW_INFO(FUNC_ADPT_FMT" failed !! MBSSID number :%d over TOTAL_CAM_ENTRY(8)\n", FUNC_ADPT_ARG(adapter), entry_num); rtw_warn_on(1); } - if (INVALID_CAM_ID != rtw_mbid_cam_search_by_macaddr(adapter, mac_addr)) - goto exit; - _enter_critical_bh(&mbid_cam_ctl->lock, &irqL); for (i = 0; i < TOTAL_MBID_CAM_NUM; i++) { if (!(mbid_cam_ctl->bitmap & BIT(i))) { @@ -2336,21 +2741,23 @@ int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name, _adapter *adapter) if (mbid_cam_ctl->bitmap & BIT(i)) { iface_id = dvobj->mbid_cam_cache[i].iface_id; - RTW_PRINT_SEL(sel, "IF_ID:%d\t", iface_id); - RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\t", MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr)); + _RTW_PRINT_SEL(sel, "IF_ID:%d\t", iface_id); + _RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\t", MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr)); iface = dvobj->padapters[iface_id]; if (iface) { - if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) - RTW_PRINT_SEL(sel, "ROLE:%s\n", "STA"); - else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE) - RTW_PRINT_SEL(sel, "ROLE:%s\n", "AP"); + if (MLME_IS_STA(iface)) + _RTW_PRINT_SEL(sel, "ROLE:%s\n", "STA"); + else if (MLME_IS_AP(iface)) + _RTW_PRINT_SEL(sel, "ROLE:%s\n", "AP"); + else if (MLME_IS_MESH(iface)) + _RTW_PRINT_SEL(sel, "ROLE:%s\n", "MESH"); else - RTW_PRINT_SEL(sel, "ROLE:%s\n", "NONE"); + _RTW_PRINT_SEL(sel, "ROLE:%s\n", "NONE"); } } else - RTW_PRINT_SEL(sel, "N/A\n"); + _RTW_PRINT_SEL(sel, "N/A\n"); } _exit_critical_bh(&mbid_cam_ctl->lock, &irqL); return 0; @@ -2405,7 +2812,7 @@ int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter) RTW_PRINT_SEL(sel, "CAM_ID = %d\t", i); _rtw_memset(mac_addr, 0, ETH_ALEN); read_mbssid_cam(adapter, i, mac_addr); - RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\n", MAC_ARG(mac_addr)); + _RTW_PRINT_SEL(sel, "MAC Addr:"MAC_FMT"\n", MAC_ARG(mac_addr)); } /*_exit_critical_bh(&mbid_cam_ctl->lock, &irqL);*/ return 0; @@ -2425,17 +2832,19 @@ static void clear_mbssid_cam(_adapter *padapter, u8 cam_addr) { rtw_hal_set_hwreg(padapter, HW_VAR_MBSSID_CAM_CLEAR, &cam_addr); } -static void enable_mbssid_cam(_adapter *adapter) + +void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num) +{ + rtw_write8(adapter, REG_MBID_NUM, + ((rtw_read8(adapter, REG_MBID_NUM) & 0xF8) | ((ap_num -1) & 0x07))); + +} +void rtw_mbid_cam_enable(_adapter *adapter) { - u8 max_cam_id = rtw_get_max_mbid_cam_id(adapter); /*enable MBSSID*/ - rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR) | RCR_ENMBID); - if (max_cam_id != INVALID_CAM_ID) { - rtw_write8(adapter, REG_MBID_NUM, - ((rtw_read8(adapter, REG_MBID_NUM) & 0xF8) | (max_cam_id & 0x07))); - } + rtw_hal_rcr_add(adapter, RCR_ENMBID); } -void rtw_mbid_cam_restore(_adapter *adapter) +void rtw_mi_set_mbid_cam(_adapter *adapter) { u8 i; struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); @@ -2451,52 +2860,298 @@ void rtw_mbid_cam_restore(_adapter *adapter) RTW_INFO("%s - cam_id:%d => mac:"MAC_FMT"\n", __func__, i, MAC_ARG(dvobj->mbid_cam_cache[i].mac_addr)); } } - enable_mbssid_cam(adapter); + rtw_mbid_cam_enable(adapter); } #endif /*CONFIG_MBSSID_CAM*/ -#ifdef CONFIG_MI_WITH_MBSSID_CAM -void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr) -{ +#ifdef CONFIG_FW_HANDLE_TXBCN +#define H2C_BCN_OFFLOAD_LEN 1 -#if 0 /*TODO - modify for more flexible*/ - u8 idx = 0; +#define SET_H2CCMD_BCN_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_BCN_ROOT_TBTT_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_BCN_VAP1_TBTT_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_H2CCMD_BCN_VAP2_TBTT_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) +#define SET_H2CCMD_BCN_VAP3_TBTT_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) +#define SET_H2CCMD_BCN_VAP4_TBTT_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) - if ((check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) && - (DEV_STA_NUM(adapter_to_dvobj(adapter)) == 1)) { - for (idx = 0; idx < 6; idx++) - rtw_write8(GET_PRIMARY_ADAPTER(adapter), (REG_MACID + idx), val[idx]); - } else { - /*MBID entry_id = 0~7 ,0 for root AP, 1~7 for VAP*/ - u8 entry_id; +void rtw_hal_set_fw_ap_bcn_offload_cmd(_adapter *adapter, bool fw_bcn_en, u8 tbtt_rpt_map) +{ + u8 fw_bcn_offload[1] = {0}; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - if ((check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) && - (DEV_AP_NUM(adapter_to_dvobj(adapter)) == 1)) { - entry_id = 0; - if (rtw_mbid_cam_assign(adapter, val, entry_id)) { - RTW_INFO(FUNC_ADPT_FMT" Root AP assigned success\n", FUNC_ADPT_ARG(adapter)); - write_mbssid_cam(adapter, entry_id, val); - } - } else { - entry_id = rtw_mbid_camid_alloc(adapter, val); - if (entry_id != INVALID_CAM_ID) - write_mbssid_cam(adapter, entry_id, val); - } - } -#else - { - /* - MBID entry_id = 0~7 ,for IFACE_ID0 ~ IFACE_IDx - */ - u8 entry_id = rtw_mbid_camid_alloc(adapter, mac_addr); + if (fw_bcn_en) + SET_H2CCMD_BCN_OFFLOAD_EN(fw_bcn_offload, 1); + if (tbtt_rpt_map & BIT(0)) + SET_H2CCMD_BCN_ROOT_TBTT_RPT(fw_bcn_offload, 1); + if (tbtt_rpt_map & BIT(1)) + SET_H2CCMD_BCN_VAP1_TBTT_RPT(fw_bcn_offload, 1); + if (tbtt_rpt_map & BIT(2)) + SET_H2CCMD_BCN_VAP2_TBTT_RPT(fw_bcn_offload, 1); + if (tbtt_rpt_map & BIT(3)) + SET_H2CCMD_BCN_VAP3_TBTT_RPT(fw_bcn_offload, 1); - if (entry_id != INVALID_CAM_ID) { - write_mbssid_cam(adapter, entry_id, mac_addr); - enable_mbssid_cam(adapter); - } - } -#endif + dvobj->vap_tbtt_rpt_map = tbtt_rpt_map; + dvobj->fw_bcn_offload = fw_bcn_en; + RTW_INFO("[FW BCN] Offload : %s\n", (dvobj->fw_bcn_offload) ? "EN" : "DIS"); + RTW_INFO("[FW BCN] TBTT RPT map : 0x%02x\n", dvobj->vap_tbtt_rpt_map); + + rtw_hal_fill_h2c_cmd(adapter, H2C_FW_BCN_OFFLOAD, + H2C_BCN_OFFLOAD_LEN, fw_bcn_offload); +} + +void rtw_hal_set_bcn_rsvdpage_loc_cmd(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 ret, vap_id; + u32 page_size = 0; + u8 bcn_rsvdpage[H2C_BCN_RSVDPAGE_LEN] = {0}; + + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_size); + #if 1 + for (vap_id = 0; vap_id < CONFIG_LIMITED_AP_NUM; vap_id++) { + if (dvobj->vap_map & BIT(vap_id)) + bcn_rsvdpage[vap_id] = vap_id * (MAX_BEACON_LEN / page_size); + } + #else +#define SET_H2CCMD_BCN_RSVDPAGE_LOC_ROOT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 8, __Value) +#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 8, __Value) +#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 8, __Value) +#define SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP4(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 8, __Value) + + if (dvobj->vap_map & BIT(0)) + SET_H2CCMD_BCN_RSVDPAGE_LOC_ROOT(bcn_rsvdpage, 0); + if (dvobj->vap_map & BIT(1)) + SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP1(bcn_rsvdpage, + 1 * (MAX_BEACON_LEN / page_size)); + if (dvobj->vap_map & BIT(2)) + SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP2(bcn_rsvdpage, + 2 * (MAX_BEACON_LEN / page_size)); + if (dvobj->vap_map & BIT(3)) + SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP3(bcn_rsvdpage, + 3 * (MAX_BEACON_LEN / page_size)); + if (dvobj->vap_map & BIT(4)) + SET_H2CCMD_BCN_RSVDPAGE_LOC_VAP4(bcn_rsvdpage, + 4 * (MAX_BEACON_LEN / page_size)); + #endif + if (1) { + RTW_INFO("[BCN_LOC] vap_map : 0x%02x\n", dvobj->vap_map); + RTW_INFO("[BCN_LOC] page_size :%d, @bcn_page_num :%d\n" + , page_size, (MAX_BEACON_LEN / page_size)); + RTW_INFO("[BCN_LOC] root ap : 0x%02x\n", *bcn_rsvdpage); + RTW_INFO("[BCN_LOC] vap_1 : 0x%02x\n", *(bcn_rsvdpage + 1)); + RTW_INFO("[BCN_LOC] vap_2 : 0x%02x\n", *(bcn_rsvdpage + 2)); + RTW_INFO("[BCN_LOC] vap_3 : 0x%02x\n", *(bcn_rsvdpage + 3)); + RTW_INFO("[BCN_LOC] vap_4 : 0x%02x\n", *(bcn_rsvdpage + 4)); + } + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_BCN_RSVDPAGE, + H2C_BCN_RSVDPAGE_LEN, bcn_rsvdpage); +} + +void rtw_ap_multi_bcn_cfg(_adapter *adapter) +{ + u8 dft_bcn_space = DEFAULT_BCN_INTERVAL; + u8 sub_bcn_space = (DEFAULT_BCN_INTERVAL / CONFIG_LIMITED_AP_NUM); + + /*enable to rx data frame*/ + rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF); + + /*Disable Port0's beacon function*/ + rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL) & ~BIT_EN_BCN_FUNCTION); + /*Reset Port0's TSF*/ + rtw_write8(adapter, REG_DUAL_TSF_RST, BIT_TSFTR_RST); + + rtw_ap_set_mbid_num(adapter, CONFIG_LIMITED_AP_NUM); + + /*BCN space & BCN sub-space 0x554[15:0] = 0x64,0x5BC[23:16] = 0x21*/ + rtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), HW_PORT0, dft_bcn_space); + rtw_write8(adapter, REG_MBSSID_BCN_SPACE3 + 2, sub_bcn_space); + + #if 0 /*setting in hw_var_set_opmode_mbid - ResumeTxBeacon*/ + /*BCN hold time 0x540[19:8] = 0x80*/ + rtw_write8(adapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF); + rtw_write8(adapter, REG_TBTT_PROHIBIT + 2, + (rtw_read8(adapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8)); + #endif + + /*ATIM window -0x55A = 0x32, reg 0x570 = 0x32, reg 0x5A0 = 0x32 */ + rtw_write8(adapter, REG_ATIMWND, 0x32); + rtw_write8(adapter, REG_ATIMWND1_V1, 0x32); + rtw_write8(adapter, REG_ATIMWND2, 0x32); + rtw_write8(adapter, REG_ATIMWND3, 0x32); + /* + rtw_write8(adapter, REG_ATIMWND4, 0x32); + rtw_write8(adapter, REG_ATIMWND5, 0x32); + rtw_write8(adapter, REG_ATIMWND6, 0x32); + rtw_write8(adapter, REG_ATIMWND7, 0x32);*/ + + /*no limit setting - 0x5A7 = 0xFF - Packet in Hi Queue Tx immediately*/ + rtw_write8(adapter, REG_HIQ_NO_LMT_EN, 0xFF); + + /*Mask all beacon*/ + rtw_write8(adapter, REG_MBSSID_CTRL, 0); + + /*BCN invalid bit setting 0x454[6] = 1*/ + /*rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL);*/ + + /*Enable Port0's beacon function*/ + rtw_write8(adapter, REG_BCN_CTRL, + rtw_read8(adapter, REG_BCN_CTRL) | BIT_DIS_RX_BSSID_FIT | BIT_P0_EN_TXBCN_RPT | BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION); + + /* Enable HW seq for BCN + * 0x4FC[0]: EN_HWSEQ / 0x4FC[1]: EN_HWSEQEXT */ + #ifdef CONFIG_RTL8822B + if (IS_HARDWARE_TYPE_8822B(adapter)) + rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01); + #endif + +} +static void _rtw_mbid_bcn_cfg(_adapter *adapter, bool mbcnq_en, u8 mbcnq_id) +{ + if (mbcnq_id >= CONFIG_LIMITED_AP_NUM) { + RTW_ERR(FUNC_ADPT_FMT"- mbid bcnq_id(%d) invalid\n", FUNC_ADPT_ARG(adapter), mbcnq_id); + rtw_warn_on(1); + } + + if (mbcnq_en) { + rtw_write8(adapter, REG_MBSSID_CTRL, + rtw_read8(adapter, REG_MBSSID_CTRL) | BIT(mbcnq_id)); + RTW_INFO(FUNC_ADPT_FMT"- mbid bcnq_id(%d) enabled\n", FUNC_ADPT_ARG(adapter), mbcnq_id); + } else { + rtw_write8(adapter, REG_MBSSID_CTRL, + rtw_read8(adapter, REG_MBSSID_CTRL) & (~BIT(mbcnq_id))); + RTW_INFO(FUNC_ADPT_FMT"- mbid bcnq_id(%d) disabled\n", FUNC_ADPT_ARG(adapter), mbcnq_id); + } +} +/*#define CONFIG_FW_TBTT_RPT*/ +void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 ap_id) +{ + RTW_INFO(FUNC_ADPT_FMT"- ap_id(%d)\n", FUNC_ADPT_ARG(adapter), ap_id); + + #ifdef CONFIG_FW_TBTT_RPT + if (rtw_ap_get_nums(adapter) >= 1) { + u8 tbtt_rpt_map = adapter_to_dvobj(adapter)->vap_tbtt_rpt_map; + + rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE, + tbtt_rpt_map | BIT(ap_id));/*H2C-0xBA*/ + } + #else + if (rtw_ap_get_nums(adapter) == 1) + rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE, 0);/*H2C-0xBA*/ + #endif + + rtw_hal_set_bcn_rsvdpage_loc_cmd(adapter);/*H2C-0x09*/ + + _rtw_mbid_bcn_cfg(adapter, _TRUE, ap_id); +} +void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 ap_id) +{ + RTW_INFO(FUNC_ADPT_FMT"- ap_id(%d)\n", FUNC_ADPT_ARG(adapter), ap_id); + _rtw_mbid_bcn_cfg(adapter, _FALSE, ap_id); + + if (rtw_ap_get_nums(adapter) == 0) + rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _FALSE, 0); + #ifdef CONFIG_FW_TBTT_RPT + else if (rtw_ap_get_nums(adapter) >= 1) { + u8 tbtt_rpt_map = adapter_to_dvobj(adapter)->vap_tbtt_rpt_map; + + rtw_hal_set_fw_ap_bcn_offload_cmd(adapter, _TRUE, + tbtt_rpt_map & ~BIT(ap_id));/*H2C-0xBA*/ + } + #endif +} +#endif +#ifdef CONFIG_SWTIMER_BASED_TXBCN +void rtw_ap_multi_bcn_cfg(_adapter *adapter) +{ + #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) + rtw_write8(adapter, REG_BCN_CTRL, DIS_TSF_UDT); + #else + rtw_write8(adapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB); + #endif + /*enable to rx data frame*/ + rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF); + + /*Beacon Control related register for first time*/ + rtw_write8(adapter, REG_BCNDMATIM, 0x02); /* 2ms */ + + /*rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);*/ + rtw_write8(adapter, REG_ATIMWND, 0x0c); /* 12ms */ + + #ifndef CONFIG_HW_P0_TSF_SYNC + rtw_write16(adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */ + #endif + + /*reset TSF*/ + rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(0)); + + /*enable BCN0 Function for if1*/ + /*don't enable update TSF0 for if1 (due to TSF update when beacon,probe rsp are received)*/ + #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) + rtw_write8(adapter, REG_BCN_CTRL, BIT_DIS_RX_BSSID_FIT | BIT_P0_EN_TXBCN_RPT | BIT_DIS_TSF_UDT |BIT_EN_BCN_FUNCTION); + #else + rtw_write8(adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB)); + #endif + #ifdef CONFIG_BCN_XMIT_PROTECT + rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL); + #endif + + if (IS_HARDWARE_TYPE_8821(adapter) || IS_HARDWARE_TYPE_8192E(adapter))/* select BCN on port 0 for DualBeacon*/ + rtw_write8(adapter, REG_CCK_CHECK, rtw_read8(adapter, REG_CCK_CHECK) & (~BIT_BCN_PORT_SEL)); + + /* Enable HW seq for BCN + * 0x4FC[0]: EN_HWSEQ / 0x4FC[1]: EN_HWSEQEXT */ + #ifdef CONFIG_RTL8822B + if (IS_HARDWARE_TYPE_8822B(adapter)) + rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01); + #endif +} +#endif + +#ifdef CONFIG_MI_WITH_MBSSID_CAM +void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr) +{ + +#if 0 /*TODO - modify for more flexible*/ + u8 idx = 0; + + if ((check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) && + (DEV_STA_NUM(adapter_to_dvobj(adapter)) == 1)) { + for (idx = 0; idx < 6; idx++) + rtw_write8(GET_PRIMARY_ADAPTER(adapter), (REG_MACID + idx), val[idx]); + } else { + /*MBID entry_id = 0~7 ,0 for root AP, 1~7 for VAP*/ + u8 entry_id; + + if ((check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) && + (DEV_AP_NUM(adapter_to_dvobj(adapter)) == 1)) { + entry_id = 0; + if (rtw_mbid_cam_assign(adapter, val, entry_id)) { + RTW_INFO(FUNC_ADPT_FMT" Root AP assigned success\n", FUNC_ADPT_ARG(adapter)); + write_mbssid_cam(adapter, entry_id, val); + } + } else { + entry_id = rtw_mbid_camid_alloc(adapter, val); + if (entry_id != INVALID_CAM_ID) + write_mbssid_cam(adapter, entry_id, val); + } + } +#else + { + /* + MBID entry_id = 0~7 ,for IFACE_ID0 ~ IFACE_IDx + */ + u8 entry_id = rtw_mbid_camid_alloc(adapter, mac_addr); + + + if (entry_id != INVALID_CAM_ID) { + write_mbssid_cam(adapter, entry_id, mac_addr); + RTW_INFO("%s "ADPT_FMT"- mbid(%d) mac_addr ="MAC_FMT"\n", __func__, + ADPT_ARG(adapter), entry_id, MAC_ARG(mac_addr)); + } + } +#endif } void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr) @@ -2517,21 +3172,35 @@ void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr) write_mbssid_cam(adapter, entry_id, mac_addr); } +#ifdef CONFIG_SWTIMER_BASED_TXBCN +u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval) +{ + if (adapter_to_dvobj(adapter)->inter_bcn_space != bcn_interval) + return adapter_to_dvobj(adapter)->inter_bcn_space; + else + return bcn_interval; +} +#endif/*CONFIG_SWTIMER_BASED_TXBCN*/ #endif/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/ -void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val) +static void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val) { u8 idx = 0; u32 reg_macid = 0; + enum _hw_port hwport; if (val == NULL) return; + hwport = get_hw_port(adapter); RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", __func__, - ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(val)); + ADPT_ARG(adapter), hwport, MAC_ARG(val)); - switch (adapter->hw_port) { +#ifdef RTW_HALMAC + rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), hwport, val); +#else /* !RTW_HALMAC */ + switch (hwport) { case HW_PORT0: default: reg_macid = REG_MACID; @@ -2552,10 +3221,12 @@ void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val) #endif/*defined(CONFIG_RTL8814A)*/ } - for (idx = 0; idx < 6; idx++) + for (idx = 0; idx < ETH_ALEN; idx++) rtw_write8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx), val[idx]); +#endif /* !RTW_HALMAC */ } -void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr) + +static void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr) { u8 idx = 0; u32 reg_macid = 0; @@ -2564,6 +3235,9 @@ void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr) return; _rtw_memset(mac_addr, 0, ETH_ALEN); +#ifdef RTW_HALMAC + rtw_halmac_get_mac_address(adapter_to_dvobj(adapter), adapter->hw_port, mac_addr); +#else /* !RTW_HALMAC */ switch (adapter->hw_port) { case HW_PORT0: default: @@ -2585,19 +3259,25 @@ void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr) #endif /*defined(CONFIG_RTL8814A)*/ } - for (idx = 0; idx < 6; idx++) + for (idx = 0; idx < ETH_ALEN; idx++) mac_addr[idx] = rtw_read8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx)); +#endif /* !RTW_HALMAC */ RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", __func__, ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(mac_addr)); } -void rtw_hal_set_bssid(_adapter *adapter, u8 *val) +static void rtw_hal_set_bssid(_adapter *adapter, u8 *val) { + u8 hw_port = rtw_hal_get_port(adapter); + +#ifdef RTW_HALMAC + rtw_halmac_set_bssid(adapter_to_dvobj(adapter), hw_port, val); +#else /* !RTW_HALMAC */ u8 idx = 0; u32 reg_bssid = 0; - switch (adapter->hw_port) { + switch (hw_port) { case HW_PORT0: default: reg_bssid = REG_BSSID; @@ -2605,7 +3285,7 @@ void rtw_hal_set_bssid(_adapter *adapter, u8 *val) case HW_PORT1: reg_bssid = REG_BSSID1; break; -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) +#if defined(CONFIG_RTL8814A) case HW_PORT2: reg_bssid = REG_BSSID2; break; @@ -2615,137 +3295,478 @@ void rtw_hal_set_bssid(_adapter *adapter, u8 *val) case HW_PORT4: reg_bssid = REG_BSSID4; break; -#endif/*defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)*/ +#endif/*defined(CONFIG_RTL8814A)*/ } - for (idx = 0 ; idx < 6; idx++) + for (idx = 0 ; idx < ETH_ALEN; idx++) rtw_write8(adapter, (reg_bssid + idx), val[idx]); +#endif /* !RTW_HALMAC */ - RTW_INFO("%s "ADPT_FMT"- hw port -%d BSSID: "MAC_FMT"\n", __func__, ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(val)); + RTW_INFO("%s "ADPT_FMT"- hw port -%d BSSID: "MAC_FMT"\n", + __func__, ADPT_ARG(adapter), hw_port, MAC_ARG(val)); } -void rtw_hal_get_msr(_adapter *adapter, u8 *net_type) +static void rtw_hal_set_tsf_update(_adapter *adapter, u8 en) { - switch (adapter->hw_port) { - case HW_PORT0: - /*REG_CR - BIT[17:16]-Network Type for port 1*/ - *net_type = rtw_read8(adapter, MSR) & 0x03; - break; - case HW_PORT1: - /*REG_CR - BIT[19:18]-Network Type for port 1*/ - *net_type = (rtw_read8(adapter, MSR) & 0x0C) >> 2; - break; -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) - case HW_PORT2: - /*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/ - *net_type = rtw_read8(adapter, MSR1) & 0x03; - break; - case HW_PORT3: - /*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/ - *net_type = (rtw_read8(adapter, MSR1) & 0x0C) >> 2; - break; - case HW_PORT4: - /*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/ - *net_type = (rtw_read8(adapter, MSR1) & 0x30) >> 4; - break; -#endif /*#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)*/ - default: - RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n", - ADPT_ARG(adapter), adapter->hw_port); + u32 addr = 0; + u8 val8; + + rtw_hal_get_hwreg(adapter, HW_VAR_BCN_CTRL_ADDR, (u8 *)&addr); + if (addr) { + val8 = rtw_read8(adapter, addr); + if (en && (val8 & DIS_TSF_UDT)) { + rtw_write8(adapter, addr, val8 & ~DIS_TSF_UDT); + #ifdef DBG_TSF_UPDATE + RTW_INFO("port%u("ADPT_FMT") enable TSF update\n", adapter->hw_port, ADPT_ARG(adapter)); + #endif + } + if (!en && !(val8 & DIS_TSF_UDT)) { + rtw_write8(adapter, addr, val8 | DIS_TSF_UDT); + #ifdef DBG_TSF_UPDATE + RTW_INFO("port%u("ADPT_FMT") disable TSF update\n", adapter->hw_port, ADPT_ARG(adapter)); + #endif + } + } else { + RTW_WARN("unknown port%d("ADPT_FMT") %s TSF update\n" + , adapter->hw_port, ADPT_ARG(adapter), en ? "enable" : "disable"); rtw_warn_on(1); - break; } } -void rtw_hal_set_msr(_adapter *adapter, u8 net_type) +static void rtw_hal_set_hw_update_tsf(PADAPTER padapter) { - u8 val8 = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - switch (adapter->hw_port) { - case HW_PORT0: -#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) /*For 2 hw ports - 88E/92E/8812/8821/8723B*/ - if (rtw_get_mbid_cam_entry_num(adapter)) { - if (net_type != _HW_STATE_NOLINK_) - net_type = _HW_STATE_AP_; - } +#if defined(CONFIG_RTL8822B) || defined(CONFIG_MI_WITH_MBSSID_CAM) + RTW_INFO("[Warn] %s "ADPT_FMT" enter func\n", __func__, ADPT_ARG(padapter)); + rtw_warn_on(1); + return; #endif - /*REG_CR - BIT[17:16]-Network Type for port 0*/ - val8 = rtw_read8(adapter, MSR) & 0x0C; - val8 |= net_type; - rtw_write8(adapter, MSR, val8); - break; - case HW_PORT1: - /*REG_CR - BIT[19:18]-Network Type for port 1*/ - val8 = rtw_read8(adapter, MSR) & 0x03; - val8 |= net_type << 2; - rtw_write8(adapter, MSR, val8); - break; -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) - case HW_PORT2: - /*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/ - val8 = rtw_read8(adapter, MSR1) & 0xFC; - val8 |= net_type; - rtw_write8(adapter, MSR1, val8); - break; - case HW_PORT3: - /*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/ - val8 = rtw_read8(adapter, MSR1) & 0xF3; - val8 |= net_type << 2; - rtw_write8(adapter, MSR1, val8); - break; - case HW_PORT4: - /*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/ - val8 = rtw_read8(adapter, MSR1) & 0xCF; - val8 |= net_type << 4; - rtw_write8(adapter, MSR1, val8); - break; -#endif /* CONFIG_RTL8814A | CONFIG_RTL8822B */ - default: - RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n", - ADPT_ARG(adapter), adapter->hw_port); - rtw_warn_on(1); - break; + + if (!pmlmeext->en_hw_update_tsf) + return; + + /* check RCR */ + if (!rtw_hal_rcr_check(padapter, RCR_CBSSID_BCN)) + return; + + if (pmlmeext->tsf_update_required) { + pmlmeext->tsf_update_pause_stime = 0; + rtw_hal_set_tsf_update(padapter, 1); } + + pmlmeext->en_hw_update_tsf = 0; } -void hw_var_port_switch(_adapter *adapter) +void rtw_iface_enable_tsf_update(_adapter *adapter) { -#ifdef CONFIG_CONCURRENT_MODE -#ifdef CONFIG_RUNTIME_PORT_SWITCH - /* - 0x102: MSR - 0x550: REG_BCN_CTRL - 0x551: REG_BCN_CTRL_1 - 0x55A: REG_ATIMWND - 0x560: REG_TSFTR - 0x568: REG_TSFTR1 - 0x570: REG_ATIMWND_1 - 0x610: REG_MACID - 0x618: REG_BSSID - 0x700: REG_MACID1 - 0x708: REG_BSSID1 - */ + adapter->mlmeextpriv.tsf_update_pause_stime = 0; + adapter->mlmeextpriv.tsf_update_required = 1; +#ifdef CONFIG_MI_WITH_MBSSID_CAM - int i; - u8 msr; - u8 bcn_ctrl; - u8 bcn_ctrl_1; - u8 atimwnd[2]; - u8 atimwnd_1[2]; - u8 tsftr[8]; - u8 tsftr_1[8]; - u8 macid[6]; - u8 bssid[6]; - u8 macid_1[6]; - u8 bssid_1[6]; +#else + rtw_hal_set_tsf_update(adapter, 1); +#endif +} - u8 hw_port; - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - _adapter *iface = NULL; +void rtw_iface_disable_tsf_update(_adapter *adapter) +{ + adapter->mlmeextpriv.tsf_update_required = 0; + adapter->mlmeextpriv.tsf_update_pause_stime = 0; + adapter->mlmeextpriv.en_hw_update_tsf = 0; +#ifdef CONFIG_MI_WITH_MBSSID_CAM - msr = rtw_read8(adapter, MSR); - bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL); - bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1); +#else + rtw_hal_set_tsf_update(adapter, 0); +#endif +} + +static void rtw_hal_tsf_update_pause(_adapter *adapter) +{ +#ifdef CONFIG_MI_WITH_MBSSID_CAM + +#else + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + int i; + u8 val8; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + rtw_hal_set_tsf_update(iface, 0); + if (iface->mlmeextpriv.tsf_update_required) { + iface->mlmeextpriv.tsf_update_pause_stime = rtw_get_current_time(); + if (!iface->mlmeextpriv.tsf_update_pause_stime) + iface->mlmeextpriv.tsf_update_pause_stime++; + } + iface->mlmeextpriv.en_hw_update_tsf = 0; + } +#endif +} + +static void rtw_hal_tsf_update_restore(_adapter *adapter) +{ +#ifdef CONFIG_MI_WITH_MBSSID_CAM + +#else + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + if (iface->mlmeextpriv.tsf_update_required) { + /* enable HW TSF update when recive beacon*/ + iface->mlmeextpriv.en_hw_update_tsf = 1; + #ifdef DBG_TSF_UPDATE + RTW_INFO("port%d("ADPT_FMT") enabling TSF update...\n" + , iface->hw_port, ADPT_ARG(iface)); + #endif + } + } +#endif +} + +void rtw_hal_periodic_tsf_update_chk(_adapter *adapter) +{ +#ifdef CONFIG_MI_WITH_MBSSID_CAM + +#else + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + struct mlme_ext_priv *mlmeext; + int i; + u32 restore_ms = 0; + + if (dvobj->periodic_tsf_update_etime) { + if (rtw_time_after(rtw_get_current_time(), dvobj->periodic_tsf_update_etime)) { + /* end for restore status */ + dvobj->periodic_tsf_update_etime = 0; + rtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE); + } + return; + } + + if (dvobj->rf_ctl.offch_state != OFFCHS_NONE) + return; + + /* + * all required ifaces can switch to restore status together + * loop all pause iface to get largest restore time required + */ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + mlmeext = &iface->mlmeextpriv; + + if (mlmeext->tsf_update_required + && mlmeext->tsf_update_pause_stime + && rtw_get_passing_time_ms(mlmeext->tsf_update_pause_stime) + > mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_pause_factor + ) { + if (restore_ms < mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_restore_factor) + restore_ms = mlmeext->mlmext_info.bcn_interval * mlmeext->tsf_update_restore_factor; + } + } + + if (!restore_ms) + return; + + dvobj->periodic_tsf_update_etime = rtw_get_current_time() + rtw_ms_to_systime(restore_ms); + if (!dvobj->periodic_tsf_update_etime) + dvobj->periodic_tsf_update_etime++; + + rtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE); + + /* set timer to end restore status */ + _set_timer(&dvobj->periodic_tsf_update_end_timer, restore_ms); +#endif +} + +void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx) +{ + struct dvobj_priv *dvobj = (struct dvobj_priv *)ctx; + + if (dev_is_surprise_removed(dvobj) || dev_is_drv_stopped(dvobj)) + return; + + rtw_periodic_tsf_update_end_cmd(dvobj_get_primary_adapter(dvobj)); +} + +static inline u8 hw_var_rcr_config(_adapter *adapter, u32 rcr) +{ + int err; + + err = rtw_write32(adapter, REG_RCR, rcr); + if (err == _SUCCESS) + GET_HAL_DATA(adapter)->ReceiveConfig = rcr; + return err; +} + +static inline u8 hw_var_rcr_get(_adapter *adapter, u32 *rcr) +{ + u32 v32; + + v32 = rtw_read32(adapter, REG_RCR); + if (rcr) + *rcr = v32; + GET_HAL_DATA(adapter)->ReceiveConfig = v32; + return _SUCCESS; +} + +/* only check SW RCR variable */ +inline u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit) +{ + PHAL_DATA_TYPE hal; + u32 rcr; + + hal = GET_HAL_DATA(adapter); + + rcr = hal->ReceiveConfig; + if ((rcr & check_bit) == check_bit) + return 1; + + return 0; +} + +inline u8 rtw_hal_rcr_add(_adapter *adapter, u32 add) +{ + PHAL_DATA_TYPE hal; + u32 rcr; + u8 ret = _SUCCESS; + + hal = GET_HAL_DATA(adapter); + + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + rcr |= add; + if (rcr != hal->ReceiveConfig) + ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + + return ret; +} + +inline u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear) +{ + PHAL_DATA_TYPE hal; + u32 rcr; + u8 ret = _SUCCESS; + + hal = GET_HAL_DATA(adapter); + + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + rcr &= ~clear; + if (rcr != hal->ReceiveConfig) + ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + + return ret; +} + +void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u32 rcr, rcr_new; + struct mi_state mstate, mstate_s; + + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + rcr_new = rcr; + +#if defined(CONFIG_MI_WITH_MBSSID_CAM) && !defined(CONFIG_CLIENT_PORT_CFG) + rcr_new &= ~(RCR_CBSSID_BCN | RCR_CBSSID_DATA); +#else + rtw_mi_status_no_self(adapter, &mstate); + rtw_mi_status_no_others(adapter, &mstate_s); + + /* only adjust parameters interested */ + switch (self_action) { + case MLME_SCAN_ENTER: + mstate_s.scan_num = 1; + mstate_s.scan_enter_num = 1; + break; + case MLME_SCAN_DONE: + mstate_s.scan_enter_num = 0; + break; + case MLME_STA_CONNECTING: + mstate_s.lg_sta_num = 1; + mstate_s.ld_sta_num = 0; + break; + case MLME_STA_CONNECTED: + mstate_s.lg_sta_num = 0; + mstate_s.ld_sta_num = 1; + break; + case MLME_STA_DISCONNECTED: + mstate_s.lg_sta_num = 0; + mstate_s.ld_sta_num = 0; + break; +#ifdef CONFIG_TDLS + case MLME_TDLS_LINKED: + mstate_s.ld_tdls_num = 1; + break; + case MLME_TDLS_NOLINK: + mstate_s.ld_tdls_num = 0; + break; +#endif +#ifdef CONFIG_AP_MODE + case MLME_AP_STARTED: + mstate_s.ap_num = 1; + break; + case MLME_AP_STOPPED: + mstate_s.ap_num = 0; + mstate_s.ld_ap_num = 0; + break; +#endif +#ifdef CONFIG_RTW_MESH + case MLME_MESH_STARTED: + mstate_s.mesh_num = 1; + break; + case MLME_MESH_STOPPED: + mstate_s.mesh_num = 0; + mstate_s.ld_mesh_num = 0; + break; +#endif + case MLME_ACTION_NONE: + case MLME_ADHOC_STARTED: + /* caller without effect of decision */ + break; + default: + rtw_warn_on(1); + }; + + rtw_mi_status_merge(&mstate, &mstate_s); + + if (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate) || MSTATE_TDLS_LD_NUM(&mstate) + #ifdef CONFIG_FIND_BEST_CHANNEL + || MSTATE_SCAN_ENTER_NUM(&mstate) + #endif + || hal_data->in_cta_test + ) + rcr_new &= ~RCR_CBSSID_DATA; + else + rcr_new |= RCR_CBSSID_DATA; + + if (MSTATE_SCAN_ENTER_NUM(&mstate) || hal_data->in_cta_test) + rcr_new &= ~RCR_CBSSID_BCN; + else if (MSTATE_STA_LG_NUM(&mstate) + || adapter_to_dvobj(adapter)->periodic_tsf_update_etime + ) + rcr_new |= RCR_CBSSID_BCN; + else if ((MSTATE_AP_NUM(&mstate) && adapter->registrypriv.wifi_spec) /* for 11n Logo 4.2.31/4.2.32 */ + || MSTATE_MESH_NUM(&mstate) + ) + rcr_new &= ~RCR_CBSSID_BCN; + else + rcr_new |= RCR_CBSSID_BCN; + + #ifdef CONFIG_CLIENT_PORT_CFG + if (get_clt_num(adapter) > MAX_CLIENT_PORT_NUM) + rcr_new &= ~RCR_CBSSID_BCN; + #endif +#endif /* CONFIG_MI_WITH_MBSSID_CAM */ + + if (rcr == rcr_new) + return; + + if (!hal_spec->rx_tsf_filter + && (rcr & RCR_CBSSID_BCN) && !(rcr_new & RCR_CBSSID_BCN)) + rtw_hal_tsf_update_pause(adapter); + + rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_new); + + if (!hal_spec->rx_tsf_filter + && !(rcr & RCR_CBSSID_BCN) && (rcr_new & RCR_CBSSID_BCN) + && self_action != MLME_STA_CONNECTING) + rtw_hal_tsf_update_restore(adapter); +} + +static void hw_var_set_rcr_am(_adapter *adapter, u8 enable) +{ + u32 rcr = RCR_AM; + + if (enable) + rtw_hal_rcr_add(adapter, rcr); + else + rtw_hal_rcr_clear(adapter, rcr); +} + +static void hw_var_set_bcn_interval(_adapter *adapter, u16 interval) +{ +#ifdef CONFIG_SWTIMER_BASED_TXBCN + interval = rtw_hal_bcn_interval_adjust(adapter, interval); +#endif + +#ifdef RTW_HALMAC + rtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), adapter->hw_port, interval); +#else + rtw_write16(adapter, REG_MBSSID_BCN_SPACE, interval); +#endif + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + RTW_INFO("%s==> bcn_interval:%d, eraly_int:%d\n", __func__, interval, interval >> 1); + rtw_write8(adapter, REG_DRVERLYINT, interval >> 1); + } + } +#endif +} + +void hw_var_port_switch(_adapter *adapter) +{ +#ifdef CONFIG_CONCURRENT_MODE +#ifdef CONFIG_RUNTIME_PORT_SWITCH + /* + 0x102: MSR + 0x550: REG_BCN_CTRL + 0x551: REG_BCN_CTRL_1 + 0x55A: REG_ATIMWND + 0x560: REG_TSFTR + 0x568: REG_TSFTR1 + 0x570: REG_ATIMWND_1 + 0x610: REG_MACID + 0x618: REG_BSSID + 0x700: REG_MACID1 + 0x708: REG_BSSID1 + */ + + int i; + u8 msr; + u8 bcn_ctrl; + u8 bcn_ctrl_1; + u8 atimwnd[2]; + u8 atimwnd_1[2]; + u8 tsftr[8]; + u8 tsftr_1[8]; + u8 macid[6]; + u8 bssid[6]; + u8 macid_1[6]; + u8 bssid_1[6]; +#if defined(CONFIG_RTL8192F) + u16 wlan_act_mask_ctrl = 0; + u16 en_port_mask = EN_PORT_0_FUNCTION | EN_PORT_1_FUNCTION; +#endif + + u8 hw_port; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface = NULL; + + msr = rtw_read8(adapter, MSR); + bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL); + bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1); +#if defined(CONFIG_RTL8192F) + wlan_act_mask_ctrl = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1); +#endif for (i = 0; i < 2; i++) atimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i); @@ -2774,6 +3795,9 @@ void hw_var_port_switch(_adapter *adapter) "msr:0x%02x\n" "bcn_ctrl:0x%02x\n" "bcn_ctrl_1:0x%02x\n" +#if defined(CONFIG_RTL8192F) + "wlan_act_mask_ctrl:0x%02x\n" +#endif "atimwnd:0x%04x\n" "atimwnd_1:0x%04x\n" "tsftr:%llu\n" @@ -2786,6 +3810,9 @@ void hw_var_port_switch(_adapter *adapter) , msr , bcn_ctrl , bcn_ctrl_1 +#if defined(CONFIG_RTL8192F) + , wlan_act_mask_ctrl +#endif , *((u16 *)atimwnd) , *((u16 *)atimwnd_1) , *((u64 *)tsftr) @@ -2801,6 +3828,10 @@ void hw_var_port_switch(_adapter *adapter) rtw_write8(adapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT); rtw_write8(adapter, REG_BCN_CTRL_1, (bcn_ctrl_1 & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT); +#if defined(CONFIG_RTL8192F) + rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1, wlan_act_mask_ctrl & ~en_port_mask); +#endif + /* switch msr */ msr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2); rtw_write8(adapter, MSR, msr); @@ -2840,6 +3871,14 @@ void hw_var_port_switch(_adapter *adapter) rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1); rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl); +#if defined(CONFIG_RTL8192F) + /* if the setting of port0 and port1 are the same, it does not need to switch port setting*/ + if(((wlan_act_mask_ctrl & en_port_mask) != 0) && ((wlan_act_mask_ctrl & en_port_mask) + != (EN_PORT_0_FUNCTION | EN_PORT_1_FUNCTION))) + wlan_act_mask_ctrl ^= en_port_mask; + rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1, wlan_act_mask_ctrl); +#endif + if (adapter->iface_id == IFACE_ID0) iface = dvobj->padapters[IFACE_ID1]; else if (adapter->iface_id == IFACE_ID1) @@ -2862,6 +3901,9 @@ void hw_var_port_switch(_adapter *adapter) msr = rtw_read8(adapter, MSR); bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL); bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1); +#if defined(CONFIG_RTL8192F) + wlan_act_mask_ctrl = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1); +#endif for (i = 0; i < 2; i++) atimwnd[i] = rtw_read8(adapter, REG_ATIMWND + i); @@ -2889,6 +3931,9 @@ void hw_var_port_switch(_adapter *adapter) "msr:0x%02x\n" "bcn_ctrl:0x%02x\n" "bcn_ctrl_1:0x%02x\n" +#if defined(CONFIG_RTL8192F) + "wlan_act_mask_ctrl:0x%02x\n" +#endif "atimwnd:%u\n" "atimwnd_1:%u\n" "tsftr:%llu\n" @@ -2901,6 +3946,9 @@ void hw_var_port_switch(_adapter *adapter) , msr , bcn_ctrl , bcn_ctrl_1 +#if defined(CONFIG_RTL8192F) + , wlan_act_mask_ctrl +#endif , *((u16 *)atimwnd) , *((u16 *)atimwnd_1) , *((u64 *)tsftr) @@ -2924,6 +3972,7 @@ const char *const _h2c_msr_role_str[] = { "GO", "TDLS", "ADHOC", + "MESH", "INVALID", }; @@ -2933,15 +3982,21 @@ s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id) s32 ret = _SUCCESS; u8 parm[H2C_DEFAULT_PORT_ID_LEN] = {0}; struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 port_id = rtw_hal_get_port(adapter); + + if ((dvobj->dft.port_id == port_id) && (dvobj->dft.mac_id == mac_id)) + return ret; - SET_H2CCMD_DFTPID_PORT_ID(parm, adapter->hw_port); + SET_H2CCMD_DFTPID_PORT_ID(parm, port_id); SET_H2CCMD_DFTPID_MAC_ID(parm, mac_id); RTW_DBG_DUMP("DFT port id parm:", parm, H2C_DEFAULT_PORT_ID_LEN); - RTW_INFO("%s port_id :%d, mad_id:%d\n", __func__, adapter->hw_port, mac_id); + RTW_INFO("%s ("ADPT_FMT") port_id :%d, mad_id:%d\n", + __func__, ADPT_ARG(adapter), port_id, mac_id); ret = rtw_hal_fill_h2c_cmd(adapter, H2C_DEFAULT_PORT_ID, H2C_DEFAULT_PORT_ID_LEN, parm); - dvobj->default_port_id = adapter->hw_port; + dvobj->dft.port_id = port_id; + dvobj->dft.mac_id = mac_id; return ret; } @@ -2950,15 +4005,11 @@ s32 rtw_set_default_port_id(_adapter *adapter) s32 ret = _SUCCESS; struct sta_info *psta; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - - if (adapter->hw_port == dvobj->default_port_id) - return ret; - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + if (is_client_associated_to_ap(adapter)) { psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv)); if (psta) - ret = rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id); + ret = rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id); } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { } else { @@ -2970,9 +4021,9 @@ s32 rtw_set_ps_rsvd_page(_adapter *adapter) { s32 ret = _SUCCESS; u16 media_status_rpt = RT_MEDIA_CONNECT; - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); - if (adapter->hw_port == dvobj->default_port_id) + if (adapter->iface_id == pwrctl->fw_psmode_iface_id) return ret; rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT, @@ -2981,40 +4032,157 @@ s32 rtw_set_ps_rsvd_page(_adapter *adapter) return ret; } -#endif - -#ifdef CONFIG_P2P_PS -#ifdef RTW_HALMAC -void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state) +#if 0 +_adapter * _rtw_search_dp_iface(_adapter *adapter) { - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct wifidirect_info *pwdinfo = &adapter->wdinfo; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - struct sta_priv *pstapriv = &adapter->stapriv; - struct sta_info *psta; - HAL_P2P_PS_PARA p2p_ps_para; - int status = -1; - u8 i; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + _adapter *target_iface = NULL; + int i; + u8 sta_num = 0, tdls_num = 0, ap_num = 0, mesh_num = 0, adhoc_num = 0; + u8 p2p_go_num = 0, p2p_gc_num = 0; + _adapter *sta_ifs[8]; + _adapter *ap_ifs[8]; + _adapter *mesh_ifs[8]; + _adapter *gc_ifs[8]; + _adapter *go_ifs[8]; - _rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA)); - _rtw_memcpy((&p2p_ps_para) , &hal->p2p_ps_offload , sizeof(hal->p2p_ps_offload)); + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; - (&p2p_ps_para)->p2p_port_id = adapter->hw_port; - (&p2p_ps_para)->p2p_group = 0; - psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); - if (psta) { - (&p2p_ps_para)->p2p_macid = psta->mac_id; - } else { - if (p2p_ps_state != P2P_PS_DISABLE) { - RTW_ERR("%s , psta was NULL\n", __func__); - return; + if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) { + if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) { + sta_ifs[sta_num++] = iface; + + #ifdef CONFIG_TDLS + if (iface->tdlsinfo.link_established == _TRUE) + tdls_num++; + #endif + #ifdef CONFIG_P2P + if (MLME_IS_GC(iface)) + gc_ifs[p2p_gc_num++] = iface; + #endif + } +#ifdef CONFIG_AP_MODE + } else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) { + if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) { + ap_ifs[ap_num++] = iface; + #ifdef CONFIG_P2P + if (MLME_IS_GO(iface)) + go_ifs[p2p_go_num++] = iface; + #endif + } +#endif + } else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE + && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE + ) { + adhoc_num++; + +#ifdef CONFIG_RTW_MESH + } else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE + && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE + ) { + mesh_ifs[mesh_num++] = iface; +#endif } } - - switch (p2p_ps_state) { + if (p2p_gc_num) { + target_iface = gc_ifs[0]; + } + else if (sta_num) { + if(sta_num == 1) { + target_iface = sta_ifs[0]; + } else if (sta_num >= 2) { + /*TODO get target_iface by timestamp*/ + target_iface = sta_ifs[0]; + } + } else if (ap_num) { + target_iface = ap_ifs[0]; + } + + RTW_INFO("[IFS_ASSOC_STATUS] - STA :%d", sta_num); + RTW_INFO("[IFS_ASSOC_STATUS] - TDLS :%d", tdls_num); + RTW_INFO("[IFS_ASSOC_STATUS] - AP:%d", ap_num); + RTW_INFO("[IFS_ASSOC_STATUS] - MESH :%d", mesh_num); + RTW_INFO("[IFS_ASSOC_STATUS] - ADHOC :%d", adhoc_num); + RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GC :%d", p2p_gc_num); + RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GO :%d", p2p_go_num); + + if (target_iface) + RTW_INFO("%s => target_iface ("ADPT_FMT")\n", + __func__, ADPT_ARG(target_iface)); + else + RTW_INFO("%s => target_iface NULL\n", __func__); + + return target_iface; +} + +void rtw_search_default_port(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *adp_iface = NULL; +#ifdef CONFIG_WOWLAN + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + + if (pwrpriv->wowlan_mode == _TRUE) { + adp_iface = adapter; + goto exit; + } +#endif + adp_iface = _rtw_search_dp_iface(adapter); + +exit : + if ((adp_iface != NULL) && (MLME_IS_STA(adp_iface))) + rtw_set_default_port_id(adp_iface); + else + rtw_hal_set_default_port_id_cmd(adapter, 0); + + if (1) { + _adapter *tmp_adp; + + tmp_adp = (adp_iface) ? adp_iface : adapter; + + RTW_INFO("%s ("ADPT_FMT")=> hw_port :%d, default_port(%d)\n", + __func__, ADPT_ARG(adapter), get_hw_port(tmp_adp), get_dft_portid(tmp_adp)); + } +} +#endif +#endif /*CONFIG_FW_MULTI_PORT_SUPPORT*/ + +#ifdef CONFIG_P2P_PS +#ifdef RTW_HALMAC +void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *psta; + HAL_P2P_PS_PARA p2p_ps_para; + int status = -1; + u8 i; + u8 hw_port = rtw_hal_get_port(adapter); + + _rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA)); + _rtw_memcpy((&p2p_ps_para) , &hal->p2p_ps_offload , sizeof(hal->p2p_ps_offload)); + + (&p2p_ps_para)->p2p_port_id = hw_port; + (&p2p_ps_para)->p2p_group = 0; + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta) { + (&p2p_ps_para)->p2p_macid = psta->cmn.mac_id; + } else { + if (p2p_ps_state != P2P_PS_DISABLE) { + RTW_ERR("%s , psta was NULL\n", __func__); + return; + } + } + + + switch (p2p_ps_state) { case P2P_PS_DISABLE: RTW_INFO("P2P_PS_DISABLE\n"); _rtw_memset(&p2p_ps_para , 0, sizeof(HAL_P2P_PS_PARA)); @@ -3126,6 +4294,9 @@ s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miraca u8 parm[H2C_MEDIA_STATUS_RPT_LEN] = {0}; int i; s32 ret; +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + u8 hw_port = rtw_hal_get_port(adapter); +#endif SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, opmode); SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, macid_ind); @@ -3135,7 +4306,7 @@ s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miraca SET_H2CCMD_MSRRPT_PARM_MACID(parm, macid); SET_H2CCMD_MSRRPT_PARM_MACID_END(parm, macid_end); #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - SET_H2CCMD_MSRRPT_PARM_PORT_NUM(parm, adapter->hw_port); + SET_H2CCMD_MSRRPT_PARM_PORT_NUM(parm, hw_port); #endif RTW_DBG_DUMP("MediaStatusRpt parm:", parm, H2C_MEDIA_STATUS_RPT_LEN); @@ -3234,7 +4405,7 @@ void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - if (IS_8723D_SERIES(pHalData->version_id) || IS_8822B_SERIES(pHalData->version_id)) + if (IS_8723D_SERIES(pHalData->version_id) || IS_8822B_SERIES(pHalData->version_id) || IS_8821C_SERIES(pHalData->version_id)) rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable)); /* * Switch GPIO_13, GPIO_14 to wlan control, or pull GPIO_13,14 MUST fail. @@ -3243,7 +4414,12 @@ void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable) * TODO: GPIO_8 multi function? */ - if (index == 13 || index == 14) + if ((index == 13 || index == 14) + #if defined(CONFIG_RTL8821A) && defined(CONFIG_SDIO_HCI) + /* 8821A's LED2 circuit(used by HW_LED strategy) needs enable WL GPIO control of GPIO[14:13], can't disable */ + && (!IS_HW_LED_STRATEGY(rtw_led_get_strategy(padapter)) || enable) + #endif + ) rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable)); } @@ -3345,16 +4521,21 @@ void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc #ifdef CONFIG_WOWLAN u8 u1H2CAoacRsvdPageParm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0}; - RTW_INFO("AOACRsvdPageLoc: RWC=%d ArpRsp=%d NbrAdv=%d GtkRsp=%d GtkInfo=%d ProbeReq=%d NetworkList=%d\n", - rsvdpageloc->LocRemoteCtrlInfo, rsvdpageloc->LocArpRsp, - rsvdpageloc->LocNbrAdv, rsvdpageloc->LocGTKRsp, - rsvdpageloc->LocGTKInfo, rsvdpageloc->LocProbeReq, - rsvdpageloc->LocNetList); + RTW_INFO("%s: RWC: %d ArpRsp: %d NbrAdv: %d LocNDPInfo: %d\n", + __func__, rsvdpageloc->LocRemoteCtrlInfo, + rsvdpageloc->LocArpRsp, rsvdpageloc->LocNbrAdv, + rsvdpageloc->LocNDPInfo); + RTW_INFO("%s:GtkRsp: %d GtkInfo: %d ProbeReq: %d NetworkList: %d\n", + __func__, rsvdpageloc->LocGTKRsp, rsvdpageloc->LocGTKInfo, + rsvdpageloc->LocProbeReq, rsvdpageloc->LocNetList); if (check_fwstate(pmlmepriv, _FW_LINKED)) { SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocRemoteCtrlInfo); SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocArpRsp); - /* SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(u1H2CAoacRsvdPageParm, rsvdpageloc->LocNbrAdv); */ + SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(u1H2CAoacRsvdPageParm, + rsvdpageloc->LocNbrAdv); + SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(u1H2CAoacRsvdPageParm, + rsvdpageloc->LocNDPInfo); #ifdef CONFIG_GTK_OL SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKRsp); SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKInfo); @@ -3394,6 +4575,26 @@ void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc #endif /* CONFIG_WOWLAN */ } +#ifdef DBG_FW_DEBUG_MSG_PKT +void rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) +{ + struct hal_ops *pHalFunc = &padapter->hal_func; + u8 u1H2C_fw_dbg_msg_pkt_parm[H2C_FW_DBG_MSG_PKT_LEN] = {0}; + u8 ret = 0; + + + RTW_INFO("RsvdPageLoc: loc_fw_dbg_msg_pkt =%d\n", rsvdpageloc->loc_fw_dbg_msg_pkt); + + SET_H2CCMD_FW_DBG_MSG_PKT_EN(u1H2C_fw_dbg_msg_pkt_parm, 1); + SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(u1H2C_fw_dbg_msg_pkt_parm, rsvdpageloc->loc_fw_dbg_msg_pkt); + ret = rtw_hal_fill_h2c_cmd(padapter, + H2C_FW_DBG_MSG_PKT, + H2C_FW_DBG_MSG_PKT_LEN, + u1H2C_fw_dbg_msg_pkt_parm); + +} +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + /*#define DBG_GET_RSVD_PAGE*/ int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size) @@ -3404,6 +4605,14 @@ int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u8 i = 0; bool rst = _FALSE; +#ifdef DBG_LA_MODE + struct registry_priv *registry_par = &adapter->registrypriv; + + if(registry_par->la_mode_en == 1) { + RTW_INFO("%s LA debug mode can't dump rsvd pg \n", __func__); + return rst; + } +#endif rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); addr = page_offset * page_size; @@ -3422,7 +4631,7 @@ int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, #else txbndy = rtw_read8(adapter, REG_TDECTRL + 1); - offset = (txbndy + page_offset) << 4; + offset = (txbndy + page_offset) * page_size / 8; count = (buffer_size / 8) + 1; rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x69); @@ -3458,7 +4667,7 @@ void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_nu if (page_num == 0) return; - RTW_PRINT_SEL(sel, "======= RSVG PAGE DUMP =======\n"); + RTW_PRINT_SEL(sel, "======= RSVD PAGE DUMP =======\n"); RTW_PRINT_SEL(sel, "page_offset:%d, page_num:%d\n", page_offset, page_num); rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); @@ -3468,7 +4677,7 @@ void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_nu if (buffer) { rtw_hal_get_rsvd_page(adapter, page_offset, page_num, buffer, buf_size); - _RTW_DUMP_SEL(sel, buffer, buf_size); + RTW_DUMP_SEL(sel, buffer, buf_size); rtw_vmfree(buffer, buf_size); } else RTW_PRINT_SEL(sel, "ERROR - rsvd_buf mem allocate failed\n"); @@ -3478,6 +4687,41 @@ void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_nu RTW_PRINT_SEL(sel, "==========================\n"); } +#ifdef CONFIG_SUPPORT_FIFO_DUMP +void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size) +{ + u8 *buffer = NULL; + u32 buff_size = 0; + static const char * const fifo_sel_str[] = { + "TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW" + }; + + if (fifo_sel > 5) { + RTW_ERR("fifo_sel:%d invalid\n", fifo_sel); + return; + } + + RTW_PRINT_SEL(sel, "========= FIFO DUMP =========\n"); + RTW_PRINT_SEL(sel, "%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[fifo_sel], fifo_addr, fifo_size); + + if (fifo_size) { + buff_size = RND4(fifo_size); + buffer = rtw_zvmalloc(buff_size); + if (buffer == NULL) + buff_size = 0; + } + + rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), fifo_sel, fifo_addr, buff_size, buffer); + + if (buffer) { + RTW_DUMP_SEL(sel, buffer, fifo_size); + rtw_vmfree(buffer, buff_size); + } + + RTW_PRINT_SEL(sel, "==========================\n"); +} +#endif + #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) static void rtw_hal_force_enable_rxdma(_adapter *adapter) { @@ -3558,12 +4802,12 @@ static u8 rtw_hal_pause_rx_dma(_adapter *adapter) } while (trycnt--); if (trycnt < 0) { - tmp = rtw_read16(adapter, REG_RXPKT_NUM + 3); + tmp = rtw_read16(adapter, REG_RXPKT_NUM + 2); RTW_PRINT("Stop RX DMA failed......\n"); - RTW_PRINT("%s, RXPKT_NUM: 0x%04x\n", - __func__, tmp); - tmp = rtw_read16(adapter, REG_RXPKT_NUM + 2); + RTW_PRINT("%s, RXPKT_NUM: 0x%02x\n", + __func__, ((tmp & 0xFF00) >> 8)); + if (tmp & BIT(3)) RTW_PRINT("%s, RX DMA has req\n", __func__); @@ -3652,12 +4896,12 @@ static u8 rtw_hal_check_wow_ctrl(_adapter *adapter, u8 chk_type) RTW_PRINT("%s REG_FE1IMR (reg120): 0x%x, REG_RXPKT_NUM(reg284): 0x%x\n", __func__, fe1_imr, rxpkt_num); while (((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) && trycnt > 1) { + rtw_msleep_os(20); fe1_imr = rtw_read32(adapter, REG_FE1IMR); rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM); RTW_PRINT("Loop index: %d :0x%x, 0x%x\n", trycnt, fe1_imr, rxpkt_num); trycnt--; - rtw_msleep_os(20); } if ((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) @@ -3746,7 +4990,7 @@ static void rtw_hal_fw_sync_cam_id(_adapter *adapter) int cam_id, index = 0; u8 *addr = NULL; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (!MLME_IS_STA(adapter)) return; addr = get_bssid(pmlmepriv); @@ -3772,72 +5016,6 @@ static void rtw_hal_fw_sync_cam_id(_adapter *adapter) rtw_write8(adapter, REG_SECCFG, 0xcc); } -static void rtw_dump_aoac_rpt(_adapter *adapter) -{ - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); - struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; - - RTW_INFO_DUMP("[AOAC-RPT] IV -", paoac_rpt->iv, 8); - RTW_INFO_DUMP("[AOAC-RPT] Replay counter of EAPOL key - ", - paoac_rpt->replay_counter_eapol_key, 8); - RTW_INFO_DUMP("[AOAC-RPT] Group key - ", paoac_rpt->group_key, 32); - RTW_INFO("[AOAC-RPT] Key Index - %d\n", paoac_rpt->key_index); - RTW_INFO("[AOAC-RPT] Security Type - %d\n", paoac_rpt->security_type); -} - -static void rtw_hal_get_aoac_rpt(_adapter *adapter) -{ - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); - struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; - u32 page_offset = 0, page_number = 0; - u32 page_size = 0, buf_size = 0; - u8 *buffer = NULL; - u8 i = 0, tmp = 0; - int ret = -1; - - /* read aoac report from rsvd page */ - page_offset = pwrctl->wowlan_aoac_rpt_loc; - page_number = 1; - - rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); - buf_size = page_size * page_number; - - buffer = rtw_zvmalloc(buf_size); - - if (NULL == buffer) { - RTW_ERR("%s buffer allocate failed size(%d)\n", - __func__, buf_size); - return; - } - - RTW_INFO("Get AOAC Report from rsvd page_offset:%d\n", page_offset); - - ret = rtw_hal_get_rsvd_page(adapter, page_offset, - page_number, buffer, buf_size); - - if (ret == _FALSE) { - RTW_ERR("%s get aoac report failed\n", __func__); - rtw_warn_on(1); - goto _exit; - } - - _rtw_memset(paoac_rpt, 0, sizeof(struct aoac_report)); - _rtw_memcpy(paoac_rpt, buffer, sizeof(struct aoac_report)); - - for (i = 0 ; i < 4 ; i++) { - tmp = paoac_rpt->replay_counter_eapol_key[i]; - paoac_rpt->replay_counter_eapol_key[i] = - paoac_rpt->replay_counter_eapol_key[7 - i]; - paoac_rpt->replay_counter_eapol_key[7 - i] = tmp; - } - - /* rtw_dump_aoac_rpt(adapter); */ - -_exit: - if (buffer) - rtw_vmfree(buffer, buf_size); -} - static void rtw_hal_update_gtk_offload_info(_adapter *adapter) { struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); @@ -3848,10 +5026,10 @@ static void rtw_hal_update_gtk_offload_info(_adapter *adapter) struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; _irqL irqL; u8 get_key[16]; - u8 gtk_id = 0, offset = 0; - u64 replay_count = 0; + u8 gtk_id = 0, offset = 0, i = 0, sz = 0, aoac_rpt_ver = 0, has_rekey = _FALSE; + u64 replay_count = 0, tmp_iv_hdr = 0, pkt_pn = 0; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (!MLME_IS_STA(adapter)) return; _rtw_memset(get_key, 0, sizeof(get_key)); @@ -3860,10 +5038,30 @@ static void rtw_hal_update_gtk_offload_info(_adapter *adapter) /*read gtk key index*/ gtk_id = paoac_rpt->key_index; + aoac_rpt_ver = paoac_rpt->version_info; + + if (aoac_rpt_ver == 0) { + /* initial verison */ + if (gtk_id == 5) + has_rekey = _FALSE; + else + has_rekey = _TRUE; + } else if (aoac_rpt_ver >= 1) { + /* Add krack patch */ + if (gtk_id == 5) + RTW_WARN("%s FW check iv fail\n", __func__); + + if (aoac_rpt_ver == 1) + RTW_WARN("%s aoac report version should be update to v2\n", __func__); + + /* Fix key id mismatch */ + if (aoac_rpt_ver == 2) + has_rekey = paoac_rpt->rekey_ok == 1 ? _TRUE : _FALSE; + } - if (gtk_id == 5 || gtk_id == 0) { + if (has_rekey == _FALSE) { RTW_INFO("%s no rekey event happened.\n", __func__); - } else if (gtk_id > 0 && gtk_id < 4) { + } else if (has_rekey == _TRUE) { RTW_INFO("%s update security key.\n", __func__); /*read key from sec-cam,for DK ,keyindex is equal to cam-id*/ rtw_sec_read_cam_ent(adapter, gtk_id, @@ -3902,11 +5100,21 @@ static void rtw_hal_update_gtk_offload_info(_adapter *adapter) &(paoac_rpt->group_key[offset]), RTW_TKIP_MIC_LEN); } - RTW_PRINT("GTK (%d) "KEY_FMT"\n", gtk_id, KEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_id].skey)); } + /* Update broadcast RX IV */ + if (psecuritypriv->dot118021XGrpPrivacy == _AES_) { + sz = sizeof(psecuritypriv->iv_seq[0]); + for (i = 0 ; i < 4 ; i++) { + _rtw_memcpy(&tmp_iv_hdr, paoac_rpt->rxgtk_iv[i], sz); + tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr); + pkt_pn = CCMPH_2_PN(tmp_iv_hdr); + _rtw_memcpy(psecuritypriv->iv_seq[i], &pkt_pn, sz); + } + } + rtw_clean_dk_section(adapter); rtw_write8(adapter, REG_SECCFG, 0x0c); @@ -3917,6 +5125,83 @@ static void rtw_hal_update_gtk_offload_info(_adapter *adapter) dump_sec_cam_cache(RTW_DBGDUMP, adapter); #endif } +#endif /*CONFIG_GTK_OL*/ + +static void rtw_dump_aoac_rpt(_adapter *adapter) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; + int i = 0; + + RTW_INFO_DUMP("[AOAC-RPT] IV -", paoac_rpt->iv, 8); + RTW_INFO_DUMP("[AOAC-RPT] Replay counter of EAPOL key - ", + paoac_rpt->replay_counter_eapol_key, 8); + RTW_INFO_DUMP("[AOAC-RPT] Group key - ", paoac_rpt->group_key, 32); + RTW_INFO("[AOAC-RPT] Key Index - %d\n", paoac_rpt->key_index); + RTW_INFO("[AOAC-RPT] Security Type - %d\n", paoac_rpt->security_type); + RTW_INFO("[AOAC-RPT] wow_pattern_idx - %d\n", + paoac_rpt->wow_pattern_idx); + RTW_INFO("[AOAC-RPT] version_info - %d\n", paoac_rpt->version_info); + RTW_INFO("[AOAC-RPT] rekey_ok - %d\n", paoac_rpt->rekey_ok); + RTW_INFO_DUMP("[AOAC-RPT] RX PTK IV-", paoac_rpt->rxptk_iv, 8); + RTW_INFO_DUMP("[AOAC-RPT] RX GTK[0] IV-", paoac_rpt->rxgtk_iv[0], 8); + RTW_INFO_DUMP("[AOAC-RPT] RX GTK[1] IV-", paoac_rpt->rxgtk_iv[1], 8); + RTW_INFO_DUMP("[AOAC-RPT] RX GTK[2] IV-", paoac_rpt->rxgtk_iv[2], 8); + RTW_INFO_DUMP("[AOAC-RPT] RX GTK[3] IV-", paoac_rpt->rxgtk_iv[3], 8); +} + +static void rtw_hal_get_aoac_rpt(_adapter *adapter) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt; + u32 page_offset = 0, page_number = 0; + u32 page_size = 0, buf_size = 0; + u8 *buffer = NULL; + u8 i = 0, tmp = 0; + int ret = -1; + + /* read aoac report from rsvd page */ + page_offset = pwrctl->wowlan_aoac_rpt_loc; + page_number = 1; + + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); + buf_size = page_size * page_number; + + buffer = rtw_zvmalloc(buf_size); + + if (buffer == NULL) { + RTW_ERR("%s buffer allocate failed size(%d)\n", + __func__, buf_size); + return; + } + + RTW_INFO("Get AOAC Report from rsvd page_offset:%d\n", page_offset); + + ret = rtw_hal_get_rsvd_page(adapter, page_offset, + page_number, buffer, buf_size); + + if (ret == _FALSE) { + RTW_ERR("%s get aoac report failed\n", __func__); + rtw_warn_on(1); + goto _exit; + } + + _rtw_memset(paoac_rpt, 0, sizeof(struct aoac_report)); + _rtw_memcpy(paoac_rpt, buffer, sizeof(struct aoac_report)); + + for (i = 0 ; i < 4 ; i++) { + tmp = paoac_rpt->replay_counter_eapol_key[i]; + paoac_rpt->replay_counter_eapol_key[i] = + paoac_rpt->replay_counter_eapol_key[7 - i]; + paoac_rpt->replay_counter_eapol_key[7 - i] = tmp; + } + + rtw_dump_aoac_rpt(adapter); + +_exit: + if (buffer) + rtw_vmfree(buffer, buf_size); +} static void rtw_hal_update_tx_iv(_adapter *adapter) { @@ -3963,10 +5248,18 @@ static void rtw_hal_update_tx_iv(_adapter *adapter) static void rtw_hal_update_sw_security_info(_adapter *adapter) { + struct security_priv *psecpriv = &adapter->securitypriv; + u8 sz = sizeof (psecpriv->iv_seq); + rtw_hal_update_tx_iv(adapter); - rtw_hal_update_gtk_offload_info(adapter); +#ifdef CONFIG_GTK_OL + if (psecpriv->binstallKCK_KEK == _TRUE && + psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) + rtw_hal_update_gtk_offload_info(adapter); +#else + _rtw_memset(psecpriv->iv_seq, 0, sz); +#endif } -#endif /*CONFIG_GTK_OL*/ static u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type) { @@ -3975,14 +5268,15 @@ static u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type) u8 u1H2CKeepAliveParm[H2C_KEEP_ALIVE_CTRL_LEN] = {0}; u8 adopt = 1, check_period = 5; u8 ret = _FAIL; + u8 hw_port = rtw_hal_get_port(adapter); SET_H2CCMD_KEEPALIVE_PARM_ENABLE(u1H2CKeepAliveParm, enable); SET_H2CCMD_KEEPALIVE_PARM_ADOPT(u1H2CKeepAliveParm, adopt); SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(u1H2CKeepAliveParm, pkt_type); SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(u1H2CKeepAliveParm, check_period); #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(u1H2CKeepAliveParm, adapter->hw_port); - RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, adapter->hw_port); + SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(u1H2CKeepAliveParm, hw_port); + RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, hw_port); #else RTW_INFO("%s(): enable = %d\n", __func__, enable); #endif @@ -3998,16 +5292,17 @@ static u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable) { struct hal_ops *pHalFunc = &adapter->hal_func; u8 u1H2CDisconDecisionParm[H2C_DISCON_DECISION_LEN] = {0}; - u8 adopt = 1, check_period = 10, trypkt_num = 0; + u8 adopt = 1, check_period = 30, trypkt_num = 5; u8 ret = _FAIL; + u8 hw_port = rtw_hal_get_port(adapter); SET_H2CCMD_DISCONDECISION_PARM_ENABLE(u1H2CDisconDecisionParm, enable); SET_H2CCMD_DISCONDECISION_PARM_ADOPT(u1H2CDisconDecisionParm, adopt); SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(u1H2CDisconDecisionParm, check_period); SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(u1H2CDisconDecisionParm, trypkt_num); #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - SET_H2CCMD_DISCONDECISION_PORT_NUM(u1H2CDisconDecisionParm, adapter->hw_port); - RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, adapter->hw_port); + SET_H2CCMD_DISCONDECISION_PORT_NUM(u1H2CDisconDecisionParm, hw_port); + RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, hw_port); #else RTW_INFO("%s(): enable = %d\n", __func__, enable); #endif @@ -4021,18 +5316,22 @@ static u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable) static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_unit) { + struct registry_priv *registry_par = &adapter->registrypriv; struct security_priv *psecpriv = &adapter->securitypriv; struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter); struct hal_ops *pHalFunc = &adapter->hal_func; u8 u1H2CWoWlanCtrlParm[H2C_WOWLAN_LEN] = {0}; - u8 discont_wake = 1, gpionum = 0, gpio_dur = 0; + u8 discont_wake = 0, gpionum = 0, gpio_dur = 0; u8 hw_unicast = 0, gpio_pulse_cnt = 0, gpio_pulse_en = 0; u8 sdio_wakeup_enable = 1; u8 gpio_high_active = 0; u8 magic_pkt = 0; u8 gpio_unit = 0; /*0: 64ns, 1: 8ms*/ u8 ret = _FAIL; +#ifdef CONFIG_DIS_UPHY + u8 dis_uphy = 0, dis_uphy_unit = 0, dis_uphy_time = 0; +#endif /* CONFIG_DIS_UPHY */ #ifdef CONFIG_GPIO_WAKEUP gpio_high_active = ppwrpriv->is_high_active; @@ -4040,15 +5339,17 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un sdio_wakeup_enable = 0; #endif /* CONFIG_GPIO_WAKEUP */ - if (!ppwrpriv->wowlan_pno_enable) + if (!ppwrpriv->wowlan_pno_enable && + registry_par->wakeup_event & BIT(0)) magic_pkt = enable; -#ifndef CONFIG_DEFAULT_PATTERNS_EN - if (psecpriv->dot11PrivacyAlgrthm == _WEP40_ || psecpriv->dot11PrivacyAlgrthm == _WEP104_) - hw_unicast = 1; - else - hw_unicast = 0; -#endif + if ((registry_par->wakeup_event & BIT(1)) && + (psecpriv->dot11PrivacyAlgrthm == _WEP40_ || + psecpriv->dot11PrivacyAlgrthm == _WEP104_)) + hw_unicast = 1; + + if (registry_par->wakeup_event & BIT(2)) + discont_wake = enable; RTW_INFO("%s(): enable=%d change_unit=%d\n", __func__, enable, change_unit); @@ -4075,8 +5376,8 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un SET_H2CCMD_WOWLAN_GPIO_ACTIVE(u1H2CWoWlanCtrlParm, gpio_high_active); #ifdef CONFIG_GTK_OL - /* GTK rekey only for AES, if GTK rekey is TKIP, then wake up*/ - if (psecpriv->binstallKCK_KEK == _TRUE) + if (psecpriv->binstallKCK_KEK == _TRUE && + psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 0); else SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 1); @@ -4097,6 +5398,30 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un if (enable) SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1); #endif + +#ifdef CONFIG_DIS_UPHY + if (enable) { + dis_uphy = 1; + /* time unit: 0 -> ms, 1 -> 256 ms*/ + dis_uphy_unit = 1; + dis_uphy_time = 0x4; + } + + SET_H2CCMD_WOWLAN_DISABLE_UPHY(u1H2CWoWlanCtrlParm, dis_uphy); + SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(u1H2CWoWlanCtrlParm, dis_uphy_unit); + SET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(u1H2CWoWlanCtrlParm, dis_uphy_time); + if (ppwrpriv->hst2dev_high_active == 1) + SET_H2CCMD_WOWLAN_RISE_HST2DEV(u1H2CWoWlanCtrlParm, 1); +#ifdef CONFIG_RTW_ONE_PIN_GPIO + SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1); + SET_H2CCMD_WOWLAN_DEV2HST_EN(u1H2CWoWlanCtrlParm, 1); + SET_H2CCMD_WOWLAN_HST2DEV_EN(u1H2CWoWlanCtrlParm, 0); +#else + SET_H2CCMD_WOWLAN_HST2DEV_EN(u1H2CWoWlanCtrlParm, 1); +#endif /* CONFIG_RTW_ONE_PIN_GPIO */ +#endif /* CONFIG_DIS_UPHY */ + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_WOWLAN, H2C_WOWLAN_LEN, @@ -4121,7 +5446,8 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable) SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN( u1H2CRemoteWakeCtrlParm, 1); #ifdef CONFIG_GTK_OL - if (psecuritypriv->binstallKCK_KEK == _TRUE) { + if (psecuritypriv->binstallKCK_KEK == _TRUE && + psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) { SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN( u1H2CRemoteWakeCtrlParm, 1); } else { @@ -4131,17 +5457,29 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable) } #endif /* CONFIG_GTK_OL */ - if (pregistrypriv->default_patterns_en == _FALSE) { - SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN( +#ifdef CONFIG_IPV6 + if (ppwrpriv->wowlan_ns_offload_en == _TRUE) { + RTW_INFO("enable NS offload\n"); + SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN( u1H2CRemoteWakeCtrlParm, enable); - /* - * filter NetBios name service pkt to avoid being waked-up - * by this kind of unicast pkt this exceptional modification - * is used for match competitor's behavior - */ - SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN( + } + + /* + * filter NetBios name service pkt to avoid being waked-up + * by this kind of unicast pkt this exceptional modification + * is used for match competitor's behavior + */ + + SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN( + u1H2CRemoteWakeCtrlParm, enable); +#endif /*CONFIG_IPV6*/ + +#ifdef CONFIG_RTL8192F + if (IS_HARDWARE_TYPE_8192F(adapter)){ + SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN( u1H2CRemoteWakeCtrlParm, enable); } +#endif /* CONFIG_RTL8192F */ if ((psecuritypriv->dot11PrivacyAlgrthm == _AES_) || (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) || @@ -4153,7 +5491,8 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable) u1H2CRemoteWakeCtrlParm, 1); } - if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) { + if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_ && + psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) { SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN( u1H2CRemoteWakeCtrlParm, enable); @@ -4254,6 +5593,7 @@ void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable) struct security_priv *psecpriv = &padapter->securitypriv; struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(padapter); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct registry_priv *pregistry = &padapter->registrypriv; struct sta_info *psta = NULL; u16 media_status_rpt; u8 pkt_type = 0; @@ -4269,7 +5609,9 @@ void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable) psecpriv->dot11PrivacyAlgrthm); if (!(ppwrpriv->wowlan_pno_enable)) { - rtw_hal_set_disconnect_decision_cmd(padapter, enable); + if (pregistry->wakeup_event & BIT(2)) + rtw_hal_set_disconnect_decision_cmd(padapter, + enable); #ifdef CONFIG_ARP_KEEP_ALIVE if ((psecpriv->dot11PrivacyAlgrthm == _WEP40_) || (psecpriv->dot11PrivacyAlgrthm == _WEP104_)) @@ -4498,7 +5840,8 @@ static void rtw_hal_ap_wow_enable(_adapter *padapter) #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) /* Invoid SE0 reset signal during suspending*/ rtw_write8(padapter, REG_RSV_CTRL, 0x20); - if (IS_8188F(pHalData->version_id) == FALSE) + if (IS_8188F(pHalData->version_id) == FALSE + && IS_8188GTV(pHalData->version_id) == FALSE) rtw_write8(padapter, REG_RSV_CTRL, 0x60); #endif } @@ -4541,6 +5884,9 @@ static void rtw_hal_ap_wow_disable(_adapter *padapter) rtw_hal_fw_dl(padapter, _FALSE); #ifdef CONFIG_GPIO_WAKEUP +#ifdef CONFIG_RTW_ONE_PIN_GPIO + rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX); +#else #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE if (pwrctl->is_high_active == 0) rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX); @@ -4553,6 +5899,7 @@ static void rtw_hal_ap_wow_disable(_adapter *padapter) rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _FALSE); #endif/*CONFIG_WAKEUP_GPIO_INPUT_MODE*/ +#endif /* CONFIG_RTW_ONE_PIN_GPIO */ #endif media_status_rpt = RT_MEDIA_CONNECT; @@ -4876,17 +6223,6 @@ static void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLe #endif } -static int get_reg_classes_full_count(struct p2p_channels channel_list) -{ - int cnt = 0; - int i; - - for (i = 0; i < channel_list.reg_classes; i++) - cnt += channel_list.reg_class[i].channels; - - return cnt; -} - static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength) { /* struct xmit_frame *pmgntframe; */ @@ -5210,6 +6546,7 @@ static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *p } static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pLength) { + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; u8 action = P2P_PUB_ACTION_ACTION; u32 p2poui = cpu_to_be32(P2POUI); @@ -5454,8 +6791,8 @@ static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pL /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)ch_list->reg_classes + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_buddy_check_fwstate(padapter, _FW_LINKED)) @@ -5501,37 +6838,22 @@ static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pL /* Channel List */ p2pie[p2pielen++] = union_ch; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ - /* Device Info */ /* Type: */ @@ -5727,6 +7049,8 @@ static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 * /* due to defult value is FAIL INFO UNAVAILABLE, so the following IE is not needed */ #if 0 if (status_code == P2P_STATUS_SUCCESS) { + struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list); + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { /* The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */ /* In this case, the P2P Invitation response frame should carry the two more P2P attributes. */ @@ -5781,8 +7105,8 @@ static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 * /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ /* + number of channels in all classes */ len_channellist_attr = 3 - + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes - + get_reg_classes_full_count(pmlmeext->channel_list); + + (1 + 1) * (u16)ch_list->reg_classes + + get_reg_classes_full_count(ch_list); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(padapter, MI_LINKED)) @@ -5828,36 +7152,22 @@ static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 * /* Channel List */ p2pie[p2pielen++] = union_ch; - } else { - int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { - /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; - - /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; - - /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; - } - } -#else /* CONFIG_CONCURRENT_MODE */ + } else +#endif /* CONFIG_CONCURRENT_MODE */ { int i, j; - for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + for (j = 0; j < ch_list->reg_classes; j++) { /* Operating Class */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + p2pie[p2pielen++] = ch_list->reg_class[j].reg_class; /* Number of Channels */ - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + p2pie[p2pielen++] = ch_list->reg_class[j].channels; /* Channel List */ - for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) - p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + for (i = 0; i < ch_list->reg_class[j].channels; i++) + p2pie[p2pielen++] = ch_list->reg_class[j].channel[i]; } } -#endif /* CONFIG_CONCURRENT_MODE */ } #endif @@ -6066,7 +7376,7 @@ u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter) } #endif /* CONFIG_P2P_WOWLAN */ -static void rtw_hal_construct_beacon(_adapter *padapter, +void rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength) { struct rtw_ieee80211_hdr *pwlanhdr; @@ -6106,6 +7416,7 @@ static void rtw_hal_construct_beacon(_adapter *padapter, pframe += 2; pktlen += 2; +#if 0 /* capability info: 2 bytes */ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); @@ -6148,13 +7459,15 @@ static void rtw_hal_construct_beacon(_adapter *padapter, if (rate_len > 8) pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); - /* todo:HT for adhoc */ +#endif _ConstructBeacon: - if ((pktlen + TXDESC_SIZE) > 512) { - RTW_INFO("beacon frame too large\n"); + if ((pktlen + TXDESC_SIZE) > MAX_BEACON_LEN) { + RTW_ERR("beacon frame too large ,len(%d,%d)\n", + (pktlen + TXDESC_SIZE), MAX_BEACON_LEN); + rtw_warn_on(1); return; } @@ -6195,11 +7508,48 @@ static void rtw_hal_construct_PSPoll(_adapter *padapter, *pLength = 16; } + +#ifdef DBG_FW_DEBUG_MSG_PKT +void rtw_hal_construct_fw_dbg_msg_pkt( + PADAPTER padapter, + u8 *pframe, + u32 *plength) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 pktlen; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + + /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, 0); + + set_frame_sub_type(pframe, WIFI_DATA); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + *plength = pktlen; +} +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + void rtw_hal_construct_NullFunctionData( PADAPTER padapter, u8 *pframe, u32 *pLength, - u8 *StaAddr, u8 bQoS, u8 AC, u8 bEosp, @@ -6212,7 +7562,8 @@ void rtw_hal_construct_NullFunctionData( struct wlan_network *cur_network = &pmlmepriv->cur_network; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - + u8 *sta_addr = NULL; + u8 bssid[ETH_ALEN] = {0}; /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */ @@ -6223,28 +7574,35 @@ void rtw_hal_construct_NullFunctionData( if (bForcePowerSave) SetPwrMgt(fctrl); + sta_addr = get_my_bssid(&pmlmeinfo->network); + if (NULL == sta_addr) { + _rtw_memcpy(bssid, adapter_mac_addr(padapter), ETH_ALEN); + sta_addr = bssid; + } + switch (cur_network->network.InfrastructureMode) { case Ndis802_11Infrastructure: SetToDs(fctrl); _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, sta_addr, ETH_ALEN); break; case Ndis802_11APMode: SetFrDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); break; case Ndis802_11IBSS: default: - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); break; } SetSeqNum(pwlanhdr, 0); + set_duration(pwlanhdr, 0); if (bQoS == _TRUE) { struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; @@ -6266,11 +7624,11 @@ void rtw_hal_construct_NullFunctionData( } void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, - u8 *StaAddr, BOOLEAN bHideSSID) + BOOLEAN bHideSSID) { struct rtw_ieee80211_hdr *pwlanhdr; u16 *fctrl; - u8 *mac, *bssid; + u8 *mac, *bssid, *sta_addr; u32 pktlen; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); @@ -6282,10 +7640,11 @@ void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, mac = adapter_mac_addr(padapter); bssid = cur_network->MacAddress; + sta_addr = get_my_bssid(&pmlmeinfo->network); fctrl = &(pwlanhdr->frame_ctl); *(fctrl) = 0; - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr1, sta_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); @@ -6448,23 +7807,23 @@ static void rtw_hal_construct_ARPRsp( /* ARP element */ pARPRspPkt += 8; - SET_ARP_PKT_HW(pARPRspPkt, 0x0100); - SET_ARP_PKT_PROTOCOL(pARPRspPkt, 0x0008); /* IP protocol */ - SET_ARP_PKT_HW_ADDR_LEN(pARPRspPkt, 6); - SET_ARP_PKT_PROTOCOL_ADDR_LEN(pARPRspPkt, 4); - SET_ARP_PKT_OPERATION(pARPRspPkt, 0x0200); /* ARP response */ - SET_ARP_PKT_SENDER_MAC_ADDR(pARPRspPkt, adapter_mac_addr(padapter)); - SET_ARP_PKT_SENDER_IP_ADDR(pARPRspPkt, pIPAddress); + SET_ARP_HTYPE(pARPRspPkt, 1); + SET_ARP_PTYPE(pARPRspPkt, ETH_P_IP); /* IP protocol */ + SET_ARP_HLEN(pARPRspPkt, ETH_ALEN); + SET_ARP_PLEN(pARPRspPkt, RTW_IP_ADDR_LEN); + SET_ARP_OPER(pARPRspPkt, 2); /* ARP response */ + SET_ARP_SENDER_MAC_ADDR(pARPRspPkt, adapter_mac_addr(padapter)); + SET_ARP_SENDER_IP_ADDR(pARPRspPkt, pIPAddress); #ifdef CONFIG_ARP_KEEP_ALIVE if (!is_zero_mac_addr(pmlmepriv->gw_mac_addr)) { - SET_ARP_PKT_TARGET_MAC_ADDR(pARPRspPkt, pmlmepriv->gw_mac_addr); - SET_ARP_PKT_TARGET_IP_ADDR(pARPRspPkt, pmlmepriv->gw_ip); + SET_ARP_TARGET_MAC_ADDR(pARPRspPkt, pmlmepriv->gw_mac_addr); + SET_ARP_TARGET_IP_ADDR(pARPRspPkt, pmlmepriv->gw_ip); } else #endif { - SET_ARP_PKT_TARGET_MAC_ADDR(pARPRspPkt, + SET_ARP_TARGET_MAC_ADDR(pARPRspPkt, get_my_bssid(&(pmlmeinfo->network))); - SET_ARP_PKT_TARGET_IP_ADDR(pARPRspPkt, + SET_ARP_TARGET_IP_ADDR(pARPRspPkt, pIPAddress); RTW_INFO("%s Target Mac Addr:" MAC_FMT "\n", __FUNCTION__, MAC_ARG(get_my_bssid(&(pmlmeinfo->network)))); @@ -6483,6 +7842,186 @@ static void rtw_hal_construct_ARPRsp( } } +#ifdef CONFIG_IPV6 +/* + * Description: Neighbor Discovery Offload. + */ +static void rtw_hal_construct_na_message(_adapter *padapter, + u8 *pframe, u32 *pLength) +{ + struct rtw_ieee80211_hdr *pwlanhdr = NULL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct security_priv *psecuritypriv = &padapter->securitypriv; + + u32 pktlen = 0; + u16 *fctrl = NULL; + + u8 ns_hdr[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x86, 0xDD}; + u8 ipv6_info[4] = {0x60, 0x00, 0x00, 0x00}; + u8 ipv6_contx[4] = {0x00, 0x20, 0x3a, 0xff}; + u8 icmpv6_hdr[8] = {0x88, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00}; + u8 val8 = 0; + + u8 *p_na_msg = pframe; + /* for TKIP Cal MIC */ + u8 *payload = pframe; + u8 EncryptionHeadOverhead = 0, na_msg_offset = 0; + /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + /* ------------------------------------------------------------------------- */ + /* MAC Header. */ + /* ------------------------------------------------------------------------- */ + SetFrameType(fctrl, WIFI_DATA); + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, + get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, + adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, + get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, 0); + set_duration(pwlanhdr, 0); + +#ifdef CONFIG_WAPI_SUPPORT + *pLength = sMacHdrLng; +#else + *pLength = 24; +#endif + switch (psecuritypriv->dot11PrivacyAlgrthm) { + case _WEP40_: + case _WEP104_: + EncryptionHeadOverhead = 4; + break; + case _TKIP_: + EncryptionHeadOverhead = 8; + break; + case _AES_: + EncryptionHeadOverhead = 8; + break; +#ifdef CONFIG_WAPI_SUPPORT + case _SMS4_: + EncryptionHeadOverhead = 18; + break; +#endif + default: + EncryptionHeadOverhead = 0; + } + + if (EncryptionHeadOverhead > 0) { + _rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead); + *pLength += EncryptionHeadOverhead; + /* SET_80211_HDR_WEP(pARPRspPkt, 1); */ /* Suggested by CCW. */ + SetPrivacy(fctrl); + } + + /* ------------------------------------------------------------------------- */ + /* Frame Body. */ + /* ------------------------------------------------------------------------- */ + na_msg_offset = *pLength; + p_na_msg = (u8 *)(pframe + na_msg_offset); + payload = p_na_msg; /* Get Payload pointer */ + + /* LLC header */ + val8 = sizeof(ns_hdr); + _rtw_memcpy(p_na_msg, ns_hdr, val8); + *pLength += val8; + p_na_msg += val8; + + /* IPv6 Header */ + /* 1 . Information (4 bytes): 0x60 0x00 0x00 0x00 */ + val8 = sizeof(ipv6_info); + _rtw_memcpy(p_na_msg, ipv6_info, val8); + *pLength += val8; + p_na_msg += val8; + + /* 2 . playload : 0x00 0x20 , NextProt : 0x3a (ICMPv6) HopLim : 0xff */ + val8 = sizeof(ipv6_contx); + _rtw_memcpy(p_na_msg, ipv6_contx, val8); + *pLength += val8; + p_na_msg += val8; + + /* 3 . SA : 16 bytes , DA : 16 bytes ( Fw will filled ) */ + _rtw_memset(&(p_na_msg[*pLength]), 0, 32); + *pLength += 32; + p_na_msg += 32; + + /* ICMPv6 */ + /* 1. Type : 0x88 (NA) + * 2. Code : 0x00 + * 3. ChechSum : 0x00 0x00 (RSvd) + * 4. NAFlag: 0x60 0x00 0x00 0x00 ( Solicited , Override) + */ + val8 = sizeof(icmpv6_hdr); + _rtw_memcpy(p_na_msg, icmpv6_hdr, val8); + *pLength += val8; + p_na_msg += val8; + + /* TA: 16 bytes*/ + _rtw_memset(&(p_na_msg[*pLength]), 0, 16); + *pLength += 16; + p_na_msg += 16; + + /* ICMPv6 Target Link Layer Address */ + p_na_msg[0] = 0x02; /* type */ + p_na_msg[1] = 0x01; /* len 1 unit of 8 octes */ + *pLength += 2; + p_na_msg += 2; + + _rtw_memset(&(p_na_msg[*pLength]), 0, 6); + *pLength += 6; + p_na_msg += 6; + + if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) { + if (IS_HARDWARE_TYPE_8188E(padapter) || + IS_HARDWARE_TYPE_8812(padapter)) { + rtw_hal_append_tkip_mic(padapter, pframe, + na_msg_offset); + } + *pLength += 8; + } +} +/* + * Description: Neighbor Discovery Protocol Information. + */ +static void rtw_hal_construct_ndp_info(_adapter *padapter, + u8 *pframe, u32 *pLength) +{ + struct mlme_ext_priv *pmlmeext = NULL; + struct mlme_ext_info *pmlmeinfo = NULL; + struct rtw_ndp_info ndp_info; + u8 *pndp_info = pframe; + u8 len = sizeof(struct rtw_ndp_info); + + RTW_INFO("%s: len: %d\n", __func__, len); + + pmlmeext = &padapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + _rtw_memset(pframe, 0, len); + _rtw_memset(&ndp_info, 0, len); + + ndp_info.enable = 1; + ndp_info.check_remote_ip = 0; + ndp_info.num_of_target_ip = 1; + + _rtw_memcpy(&ndp_info.target_link_addr, adapter_mac_addr(padapter), + ETH_ALEN); + _rtw_memcpy(&ndp_info.target_ipv6_addr, pmlmeinfo->ip6_addr, + RTW_IPv6_ADDR_LEN); + + _rtw_memcpy(pndp_info, &ndp_info, len); +} +#endif /* CONFIG_IPV6 */ + #ifdef CONFIG_PNO_SUPPORT static void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe, u32 *pLength, pno_ssid_t *ssid) @@ -6771,6 +8310,84 @@ static void rtw_hal_construct_GTKRsp( } #endif /* CONFIG_GTK_OL */ +#define PN_2_CCMPH(ch,key_id) ((ch) & 0x000000000000ffff) \ + | (((ch) & 0x0000ffffffff0000) << 16) \ + | (((key_id) << 30)) \ + | BIT(29) +static void rtw_hal_construct_remote_control_info(_adapter *adapter, + u8 *pframe, u32 *pLength) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct sta_priv *pstapriv = &adapter->stapriv; + struct security_priv *psecuritypriv = &adapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct sta_info *psta; + struct stainfo_rxcache *prxcache; + u8 cur_dot11rxiv[8], id = 0, tid_id = 0, i = 0; + size_t sz = 0, total = 0; + u64 ccmp_hdr = 0, tmp_key = 0; + + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + + if (psta == NULL) { + rtw_warn_on(1); + return; + } + + prxcache = &psta->sta_recvpriv.rxcache; + sz = sizeof(cur_dot11rxiv); + + /* 3 SEC IV * 1 page */ + rtw_get_sec_iv(adapter, cur_dot11rxiv, + get_my_bssid(&pmlmeinfo->network)); + + _rtw_memcpy(pframe, cur_dot11rxiv, sz); + *pLength += sz; + pframe += sz; + + _rtw_memset(&cur_dot11rxiv, 0, sz); + + if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) { + id = psecuritypriv->dot118021XGrpKeyid; + tid_id = prxcache->last_tid; + REMOTE_INFO_CTRL_SET_VALD_EN(cur_dot11rxiv, 0xdd); + REMOTE_INFO_CTRL_SET_PTK_EN(cur_dot11rxiv, 1); + REMOTE_INFO_CTRL_SET_GTK_EN(cur_dot11rxiv, 1); + REMOTE_INFO_CTRL_SET_GTK_IDX(cur_dot11rxiv, id); + _rtw_memcpy(pframe, cur_dot11rxiv, sz); + *pLength += sz; + pframe += sz; + + _rtw_memcpy(pframe, prxcache->iv[tid_id], sz); + *pLength += sz; + pframe += sz; + + total = sizeof(psecuritypriv->iv_seq); + total /= sizeof(psecuritypriv->iv_seq[0]); + + for (i = 0 ; i < total ; i ++) { + ccmp_hdr = + le64_to_cpu(*(u64*)psecuritypriv->iv_seq[i]); + _rtw_memset(&cur_dot11rxiv, 0, sz); + if (ccmp_hdr != 0) { + tmp_key = i; + ccmp_hdr = PN_2_CCMPH(ccmp_hdr, tmp_key); + *(u64*)cur_dot11rxiv = cpu_to_le64(ccmp_hdr); + _rtw_memcpy(pframe, cur_dot11rxiv, sz); + } + *pLength += sz; + pframe += sz; + } + } +} + +/*#define DBG_RSVD_PAGE_CFG*/ +#ifdef DBG_RSVD_PAGE_CFG +#define RSVD_PAGE_CFG(ops, v1, v2, v3) \ + RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n", \ + ops, v1, v2, v3) +#endif void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len, RSVDPAGE_LOC *rsvd_page_loc) @@ -6781,10 +8398,8 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, struct mlme_ext_priv *pmlmeext; struct mlme_ext_info *pmlmeinfo; u32 ARPLength = 0, GTKLength = 0, PNOLength = 0, ScanInfoLength = 0; - u32 SSIDLegnth = 0, ProbeReqLength = 0; + u32 SSIDLegnth = 0, ProbeReqLength = 0, ns_len = 0, rc_len = 0; u8 CurtPktPageNum = 0; - u8 currentip[4]; - u8 cur_dot11txpn[8]; #ifdef CONFIG_GTK_OL struct sta_priv *pstapriv = &adapter->stapriv; @@ -6803,14 +8418,13 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, if (pwrctl->wowlan_pno_enable == _FALSE) { /* ARP RSP * 1 page */ - rtw_get_current_ip_address(adapter, currentip); rsvd_page_loc->LocArpRsp = *page_num; RTW_INFO("LocArpRsp: %d\n", rsvd_page_loc->LocArpRsp); rtw_hal_construct_ARPRsp(adapter, &pframe[index], - &ARPLength, currentip); + &ARPLength, pmlmeinfo->ip_addr); rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc], @@ -6821,22 +8435,58 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-ARPRsp", CurtPktPageNum, *page_num, 0); + #endif + +#ifdef CONFIG_IPV6 + /* 2 NS offload and NDP Info*/ + if (pwrctl->wowlan_ns_offload_en == _TRUE) { + rsvd_page_loc->LocNbrAdv = *page_num; + RTW_INFO("LocNbrAdv: %d\n", rsvd_page_loc->LocNbrAdv); + rtw_hal_construct_na_message(adapter, + &pframe[index], &ns_len); + rtw_hal_fill_fake_txdesc(adapter, + &pframe[index - tx_desc], + ns_len, _FALSE, + _FALSE, _TRUE); + CurtPktPageNum = (u8)PageNum(tx_desc + ns_len, + page_size); + *page_num += CurtPktPageNum; + index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-NbrAdv", CurtPktPageNum, *page_num, 0); + #endif - /* 3 SEC IV * 1 page */ - rtw_get_sec_iv(adapter, cur_dot11txpn, - get_my_bssid(&pmlmeinfo->network)); + rsvd_page_loc->LocNDPInfo = *page_num; + RTW_INFO("LocNDPInfo: %d\n", + rsvd_page_loc->LocNDPInfo); - rsvd_page_loc->LocRemoteCtrlInfo = *page_num; + rtw_hal_construct_ndp_info(adapter, + &pframe[index - tx_desc], + &ns_len); + CurtPktPageNum = + (u8)PageNum(tx_desc + ns_len, page_size); + *page_num += CurtPktPageNum; + index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-NDPInfo", CurtPktPageNum, *page_num, 0); + #endif + } +#endif /*CONFIG_IPV6*/ + /* 3 Remote Control Info. * 1 page */ + rsvd_page_loc->LocRemoteCtrlInfo = *page_num; RTW_INFO("LocRemoteCtrlInfo: %d\n", rsvd_page_loc->LocRemoteCtrlInfo); - - _rtw_memcpy(pframe + index - tx_desc, cur_dot11txpn, _AES_IV_LEN_); - - CurtPktPageNum = (u8)PageNum(_AES_IV_LEN_, page_size); - + rtw_hal_construct_remote_control_info(adapter, + &pframe[index - tx_desc], + &rc_len); + CurtPktPageNum = (u8)PageNum(rc_len, page_size); *page_num += CurtPktPageNum; - - *total_pkt_len = index + _AES_IV_LEN_; + *total_pkt_len = index + rc_len; + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-RCI", CurtPktPageNum, *page_num, *total_pkt_len); + #endif #ifdef CONFIG_GTK_OL index += (CurtPktPageNum * page_size); @@ -6856,19 +8506,34 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, rsvd_page_loc->LocGTKInfo = *page_num; RTW_INFO("LocGTKInfo: %d\n", rsvd_page_loc->LocGTKInfo); - _rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN); - _rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN, - kek, RTW_KEK_LEN); - GTKLength = tx_desc + RTW_KCK_LEN + RTW_KEK_LEN; + if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8812(adapter)) { + struct security_priv *psecpriv = NULL; + + psecpriv = &adapter->securitypriv; + _rtw_memcpy(pframe + index - tx_desc, + &psecpriv->dot11PrivacyAlgrthm, 1); + _rtw_memcpy(pframe + index - tx_desc + 1, + &psecpriv->dot118021XGrpPrivacy, 1); + _rtw_memcpy(pframe + index - tx_desc + 2, + kck, RTW_KCK_LEN); + _rtw_memcpy(pframe + index - tx_desc + 2 + RTW_KCK_LEN, + kek, RTW_KEK_LEN); + CurtPktPageNum = (u8)PageNum(tx_desc + 2 + RTW_KCK_LEN + RTW_KEK_LEN, page_size); + } else { + + _rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN); + _rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN, + kek, RTW_KEK_LEN); + GTKLength = tx_desc + RTW_KCK_LEN + RTW_KEK_LEN; - if (psta != NULL && - psecuritypriv->dot118021XGrpPrivacy == _TKIP_) { - _rtw_memcpy(pframe + index - tx_desc + 56, - &psta->dot11tkiptxmickey, RTW_TKIP_MIC_LEN); - GTKLength += RTW_TKIP_MIC_LEN; + if (psta != NULL && + psecuritypriv->dot118021XGrpPrivacy == _TKIP_) { + _rtw_memcpy(pframe + index - tx_desc + 56, + &psta->dot11tkiptxmickey, RTW_TKIP_MIC_LEN); + GTKLength += RTW_TKIP_MIC_LEN; + } + CurtPktPageNum = (u8)PageNum(GTKLength, page_size); } - - CurtPktPageNum = (u8)PageNum(GTKLength, page_size); #if 0 { int i; @@ -6889,6 +8554,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-GTKInfo", CurtPktPageNum, *page_num, 0); + #endif /* 3 GTK Response */ rsvd_page_loc->LocGTKRsp = *page_num; @@ -6919,6 +8587,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-GTKRsp", CurtPktPageNum, *page_num, 0); + #endif /* below page is empty for GTK extension memory */ /* 3(11) GTK EXT MEM */ @@ -6932,6 +8603,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; /* extension memory for FW */ *total_pkt_len = index + (page_size * CurtPktPageNum); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-GTKEXTMEM", CurtPktPageNum, *page_num, *total_pkt_len); + #endif #endif /* CONFIG_GTK_OL */ index += (CurtPktPageNum * page_size); @@ -6941,6 +8615,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, RTW_INFO("LocAOACReport: %d\n", rsvd_page_loc->LocAOACReport); *page_num += 1; *total_pkt_len = index + (page_size * 1); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-AOAC", 1, *page_num, *total_pkt_len); + #endif } else { #ifdef CONFIG_PNO_SUPPORT if (pwrctl->wowlan_in_resume == _FALSE && @@ -6968,6 +8645,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0); + #endif /* Hidden SSID Probe Request */ ssid_num = pwrctl->pnlo_info->hidden_ssid_num; @@ -6992,6 +8672,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0); + #endif } /* PNO INFO Page */ @@ -7004,6 +8687,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, CurtPktPageNum = (u8)PageNum(PNOLength, page_size); *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-PNOInfo", CurtPktPageNum, *page_num, 0); + #endif /* Scan Info Page */ rsvd_page_loc->LocScanInfo = *page_num; @@ -7016,6 +8702,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; *total_pkt_len = index + ScanInfoLength; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-ScanInfo", CurtPktPageNum, *page_num, *total_pkt_len); + #endif } #endif /* CONFIG_PNO_SUPPORT */ } @@ -7024,10 +8713,25 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, static void rtw_hal_gate_bb(_adapter *adapter, bool stop) { struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); - u8 val8 = 0; + u8 i = 0, val8 = 0, empty = _FAIL; u16 val16 = 0; if (stop) { + /* checking TX queue status */ + for (i = 0 ; i < 5 ; i++) { + rtw_hal_get_hwreg(adapter, HW_VAR_CHK_MGQ_CPU_EMPTY, &empty); + if (empty) { + break; + } else { + RTW_WARN("%s: MGQ_CPU is busy(%d)!\n", + __func__, i); + rtw_mdelay_os(10); + } + } + + if (val8 == 5) + RTW_ERR("%s: Polling MGQ_CPU empty fail!\n", __func__); + /* Pause TX*/ pwrpriv->wowlan_txpause_status = rtw_read8(adapter, REG_TXPAUSE); rtw_write8(adapter, REG_TXPAUSE, 0xff); @@ -7076,7 +8780,7 @@ static u8 rtw_hal_wow_pattern_generate(_adapter *adapter, u8 idx, struct rtl_wow u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; u8 multicast_addr1[2] = {0x33, 0x33}; u8 multicast_addr2[3] = {0x01, 0x00, 0x5e}; - u8 mask_len = 0; + u8 mask_len = 0; u8 mac_addr[ETH_ALEN] = {0}; u16 count = 0; int i, j; @@ -7564,7 +9268,7 @@ static u32 _rtw_wow_pattern_read_cam(_adapter *adapter, u8 addr) u32 rdata = 0; u32 cnt = 0; - u32 start = 0; + systime start = 0; u8 timeout = 0; u8 rst = _FALSE; @@ -7634,7 +9338,7 @@ static void _rtw_wow_pattern_write_cam(_adapter *adapter, u8 addr, u32 wdata) struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex; u32 cnt = 0; - u32 start = 0, end = 0; + systime start = 0, end = 0; u8 timeout = 0; /*RTW_INFO("%s ==> addr:0x%02x , wdata:0x%08x\n", __func__, addr, wdata);*/ @@ -7703,7 +9407,7 @@ static u8 _rtw_wow_pattern_clean_cam(_adapter *adapter) struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex; u32 cnt = 0; - u32 start = 0; + systime start = 0; u8 timeout = 0; u8 rst = _FAIL; @@ -7830,7 +9534,7 @@ static void rtw_hal_wow_enable(_adapter *adapter) u16 media_status_rpt; - RTW_PRINT("%s, WOWLAN_ENABLE\n", __func__); + RTW_PRINT(FUNC_ADPT_FMT " WOWLAN_ENABLE\n", FUNC_ADPT_ARG(adapter)); rtw_hal_gate_bb(adapter, _TRUE); #ifdef CONFIG_GTK_OL if (psecuritypriv->binstallKCK_KEK == _TRUE) @@ -7839,6 +9543,11 @@ static void rtw_hal_wow_enable(_adapter *adapter) if (IS_HARDWARE_TYPE_8723B(adapter)) rtw_hal_backup_rate(adapter); + rtw_hal_fw_dl(adapter, _TRUE); + media_status_rpt = RT_MEDIA_CONNECT; + rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT, + (u8 *)&media_status_rpt); + /* RX DMA stop */ #if defined(CONFIG_RTL8188E) if (IS_HARDWARE_TYPE_8188E(adapter)) @@ -7857,17 +9566,14 @@ static void rtw_hal_wow_enable(_adapter *adapter) /* redownload wow pattern */ rtw_hal_dl_pattern(adapter, 1); - rtw_hal_fw_dl(adapter, _TRUE); - media_status_rpt = RT_MEDIA_CONNECT; - rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT, - (u8 *)&media_status_rpt); - if (!pwrctl->wowlan_pno_enable) { psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv)); if (psta != NULL) { #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id); + adapter_to_dvobj(adapter)->dft.port_id = 0xFF; + adapter_to_dvobj(adapter)->dft.mac_id = 0xFF; + rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id); #endif rtw_sta_media_status_rpt(adapter, psta, 1); @@ -7909,7 +9615,8 @@ static void rtw_hal_wow_enable(_adapter *adapter) #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) /* Invoid SE0 reset signal during suspending*/ rtw_write8(adapter, REG_RSV_CTRL, 0x20); - if (IS_8188F(pHalData->version_id) == FALSE) + if (IS_8188F(pHalData->version_id) == FALSE + && IS_8188GTV(pHalData->version_id) == FALSE) rtw_write8(adapter, REG_RSV_CTRL, 0x60); #endif @@ -8032,20 +9739,20 @@ static void rtw_hal_wow_disable(_adapter *adapter) rtw_hal_enable_tx_report(adapter); #endif -#ifdef CONFIG_GTK_OL - if (((pwrctl->wowlan_wake_reason != RX_DISASSOC) || - (pwrctl->wowlan_wake_reason != RX_DEAUTH) || - (pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT)) && - psecuritypriv->binstallKCK_KEK == _TRUE) { + if ((pwrctl->wowlan_wake_reason != RX_DISASSOC) && + (pwrctl->wowlan_wake_reason != RX_DEAUTH) && + (pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT)) { rtw_hal_get_aoac_rpt(adapter); rtw_hal_update_sw_security_info(adapter); } -#endif /*CONFIG_GTK_OL*/ rtw_hal_fw_dl(adapter, _FALSE); #ifdef CONFIG_GPIO_WAKEUP +#ifdef CONFIG_RTW_ONE_PIN_GPIO + rtw_hal_set_input_gpio(adapter, WAKEUP_GPIO_IDX); +#else #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE if (pwrctl->is_high_active == 0) rtw_hal_set_input_gpio(adapter, WAKEUP_GPIO_IDX); @@ -8058,7 +9765,7 @@ static void rtw_hal_wow_disable(_adapter *adapter) rtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, val8); rtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _FALSE); #endif - +#endif /* CONFIG_RTW_ONE_PIN_GPIO */ #endif if ((pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT) && (pwrctl->wowlan_wake_reason != RX_PAIRWISEKEY) && @@ -8071,7 +9778,9 @@ static void rtw_hal_wow_disable(_adapter *adapter) if (psta != NULL) { #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - rtw_hal_set_default_port_id_cmd(adapter, psta->mac_id); + adapter_to_dvobj(adapter)->dft.port_id = 0xFF; + adapter_to_dvobj(adapter)->dft.mac_id = 0xFF; + rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id); #endif rtw_sta_media_status_rpt(adapter, psta, 1); } @@ -8105,6 +9814,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-P2P-Beacon", CurtPktPageNum, *page_num, 0); + #endif /* P2P Probe rsp */ rsvd_page_loc->LocP2PProbeRsp = *page_num; @@ -8121,6 +9833,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-P2P-ProbeRsp", CurtPktPageNum, *page_num, 0); + #endif /* P2P nego rsp */ rsvd_page_loc->LocNegoRsp = *page_num; @@ -8137,6 +9852,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-P2P-NegoRsp", CurtPktPageNum, *page_num, 0); + #endif /* P2P invite rsp */ rsvd_page_loc->LocInviteRsp = *page_num; @@ -8153,6 +9871,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-P2P-InviteRsp", CurtPktPageNum, *page_num, 0); + #endif /* P2P provision discovery rsp */ rsvd_page_loc->LocPDRsp = *page_num; @@ -8170,6 +9891,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index, *page_num += CurtPktPageNum; *total_pkt_len = index + P2PPDRspLength; + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("WOW-P2P-PDR", CurtPktPageNum, *page_num, *total_pkt_len); + #endif index += (CurtPktPageNum * page_size); @@ -8197,6 +9921,7 @@ static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter) #endif u8 *psec_cam_id = lps_pg_info + 8; u8 sec_cam_num = 0; + u8 drv_rsvdpage_num = 0; if (!psta) { RTW_ERR("%s [ERROR] sta is NULL\n", __func__); @@ -8205,8 +9930,8 @@ static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter) } /*Byte 0 - used macid*/ - LPSPG_RSVD_PAGE_SET_MACID(lps_pg_info, psta->mac_id); - RTW_INFO("[LPSPG-INFO] mac_id:%d\n", psta->mac_id); + LPSPG_RSVD_PAGE_SET_MACID(lps_pg_info, psta->cmn.mac_id); + RTW_INFO("[LPSPG-INFO] mac_id:%d\n", psta->cmn.mac_id); #ifdef CONFIG_MBSSID_CAM /*Byte 1 - used BSSID CAM entry*/ @@ -8226,8 +9951,8 @@ static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter) #endif #ifdef CONFIG_BEAMFORMING /*&& MU BF*/ /*Btye 3 - Max MU rate table Group ID*/ - LPSPG_RSVD_PAGE_SET_MU_RAID_GID(lps_pg_info, _value); - RTW_INFO("[LPSPG-INFO] Max MU rate table Group ID :%d\n", _value); + LPSPG_RSVD_PAGE_SET_MU_RAID_GID(lps_pg_info, 0); + RTW_INFO("[LPSPG-INFO] Max MU rate table Group ID :%d\n", 0); #endif /*Btye 8 ~15 - used Security CAM entry */ @@ -8239,8 +9964,12 @@ static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter) RTW_INFO("[LPSPG-INFO] Security CAM entry number :%d\n", sec_cam_num); /*Btye 5 - Txbuf used page number for fw offload*/ - LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(lps_pg_info, phal_data->drv_rsvd_page_number); - RTW_INFO("[LPSPG-INFO] DRV's rsvd page numbers :%d\n", phal_data->drv_rsvd_page_number); + if (pwrpriv->wowlan_mode == _TRUE || pwrpriv->wowlan_ap_mode == _TRUE) + drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE); + else + drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE); + LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(lps_pg_info, drv_rsvdpage_num); + RTW_INFO("[LPSPG-INFO] DRV's rsvd page numbers :%d\n", drv_rsvdpage_num); #ifdef DBG_LPSPG_SEC_DUMP { @@ -8344,9 +10073,9 @@ u8 rtw_hal_set_lps_pg_info(_adapter *adapter) void rtw_hal_lps_pg_rssi_lv_decide(_adapter *adapter, struct sta_info *sta) { #if 0 - if (sta->rssi_level >= 4) + if (sta->cmn.ra_info.rssi_level >= 4) sta->lps_pg_rssi_lv = 3; /*RSSI High - 1SS_VHT_MCS7*/ - else if (sta->rssi_level >= 2) + else if (sta->cmn.ra_info.rssi_level >= 2) sta->lps_pg_rssi_lv = 2; /*RSSI Middle - 1SS_VHT_MCS3*/ else sta->lps_pg_rssi_lv = 1; /*RSSI Lower - Lowest_rate*/ @@ -8354,11 +10083,18 @@ void rtw_hal_lps_pg_rssi_lv_decide(_adapter *adapter, struct sta_info *sta) sta->lps_pg_rssi_lv = 0; #endif RTW_INFO("%s mac-id:%d, rssi:%d, rssi_level:%d, lps_pg_rssi_lv:%d\n", - __func__, sta->mac_id, sta->rssi_stat.undecorated_smoothed_pwdb, sta->rssi_level, sta->lps_pg_rssi_lv); + __func__, sta->cmn.mac_id, sta->cmn.rssi_stat.rssi, sta->cmn.ra_info.rssi_level, sta->lps_pg_rssi_lv); } void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id) { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *sta; + + sta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); + switch (hdl_id) { case LPS_PG_INFO_CFG: rtw_hal_set_lps_pg_info(adapter); @@ -8373,21 +10109,16 @@ void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id) rtw_clr_xmit_block(adapter, XMIT_BLOCK_REDLMEM); } break; - - case LPS_PG_RESEND_H2C: + case LPS_PG_PHYDM_DIS:/*Disable RA and PT by H2C*/ + if (sta) + rtw_phydm_lps_pg_hdl(adapter, sta, _TRUE); + break; + case LPS_PG_PHYDM_EN:/*Enable RA and PT by H2C*/ { - struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; - struct sta_info *sta; - PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); - int i; - - for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { - sta = macid_ctl->sta[i]; - if (sta && !is_broadcast_mac_addr(sta->hwaddr)) { - rtw_hal_lps_pg_rssi_lv_decide(adapter, sta); - set_sta_rate(adapter, sta); - sta->lps_pg_rssi_lv = 0; - } + if (sta) { + rtw_hal_lps_pg_rssi_lv_decide(adapter, sta); + rtw_phydm_lps_pg_hdl(adapter, sta, _FALSE); + sta->lps_pg_rssi_lv = 0; } } break; @@ -8399,31 +10130,91 @@ void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id) #endif /*CONFIG_LPS_PG*/ -/* - * Description: Fill the reserved packets that FW will use to RSVD page. - * Now we just send 4 types packet to rsvd page. - * (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. - * Input: - * finished - FALSE:At the first time we will send all the packets as a large packet to Hw, - * so we need to set the packet length to total lengh. - * TRUE: At the second time, we should send the first packet (default:beacon) - * to Hw again and set the lengh in descriptor to the real beacon lengh. - * 2009.10.15 by tynli. - * +static u8 _rtw_mi_assoc_if_num(_adapter *adapter) +{ + u8 mi_iface_num = 0; + + if (0) { + RTW_INFO("[IFS_ASSOC_STATUS] - STA :%d", DEV_STA_LD_NUM(adapter_to_dvobj(adapter))); + RTW_INFO("[IFS_ASSOC_STATUS] - AP:%d", DEV_AP_NUM(adapter_to_dvobj(adapter))); + RTW_INFO("[IFS_ASSOC_STATUS] - AP starting :%d", DEV_AP_STARTING_NUM(adapter_to_dvobj(adapter))); + RTW_INFO("[IFS_ASSOC_STATUS] - MESH :%d", DEV_MESH_NUM(adapter_to_dvobj(adapter))); + RTW_INFO("[IFS_ASSOC_STATUS] - ADHOC :%d", DEV_ADHOC_NUM(adapter_to_dvobj(adapter))); + /*RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GC :%d", DEV_P2P_GC_NUM(adapter_to_dvobj(adapter)));*/ + /*RTW_INFO("[IFS_ASSOC_STATUS] - P2P-GO :%d", DEV_P2P_GO_NUM(adapter_to_dvobj(adapter)));*/ + } + + mi_iface_num = (DEV_STA_LD_NUM(adapter_to_dvobj(adapter)) + + DEV_AP_NUM(adapter_to_dvobj(adapter)) + + DEV_AP_STARTING_NUM(adapter_to_dvobj(adapter))); + return mi_iface_num; +} + +static _adapter *_rtw_search_sta_iface(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface = NULL; + _adapter *sta_iface = NULL; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) { + if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) { + sta_iface = iface; + break; + } + } + } + return sta_iface; +} +#ifdef CONFIG_AP_MODE +static _adapter *_rtw_search_ap_iface(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface = NULL; + _adapter *ap_iface = NULL; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) { + ap_iface = iface; + break; + } + } + return ap_iface; +} +#endif + +/* + * Description: Fill the reserved packets that FW will use to RSVD page. + * Now we just send 4 types packet to rsvd page. + * (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. + * Input: + * finished - FALSE:At the first time we will send all the packets as a large packet to Hw, + * so we need to set the packet length to total lengh. + * TRUE: At the second time, we should send the first packet (default:beacon) + * to Hw again and set the lengh in descriptor to the real beacon lengh. + * page_num - The amount of reserved page which driver need. + * If this is not NULL, this function doesn't real download reserved + * page, but just count the number of reserved page. + * + * 2009.10.15 by tynli. + * 2017.06.20 modified by Lucas. + * * Page Size = 128: 8188e, 8723a/b, 8192c/d, * Page Size = 256: 8192e, 8821a * Page Size = 512: 8812a */ /*#define DBG_DUMP_SET_RSVD_PAGE*/ -void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) +static void _rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished, u8 *page_num) { PHAL_DATA_TYPE pHalData; - struct xmit_frame *pcmdframe; + struct xmit_frame *pcmdframe = NULL; struct pkt_attrib *pattrib; struct xmit_priv *pxmitpriv; - struct mlme_ext_priv *pmlmeext; - struct mlme_ext_info *pmlmeinfo; struct pwrctrl_priv *pwrctl; struct mlme_priv *pmlmepriv = &adapter->mlmepriv; struct hal_ops *pHalFunc = &adapter->hal_func; @@ -8437,6 +10228,10 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) u32 TotalPacketLen = 0, MaxRsvdPageBufSize = 0, PageSize = 0; RSVDPAGE_LOC RsvdPageLoc; +#ifdef DBG_FW_DEBUG_MSG_PKT + u32 fw_dbg_msg_pkt_len = 0; +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + #ifdef DBG_CONFIG_ERROR_DETECT struct sreset_priv *psrtpriv; #endif /* DBG_CONFIG_ERROR_DETECT */ @@ -8444,51 +10239,76 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) #ifdef CONFIG_MCC_MODE u8 dl_mcc_page = _FAIL; #endif /* CONFIG_MCC_MODE */ + u8 nr_assoc_if; + + _adapter *sta_iface = NULL; + _adapter *ap_iface = NULL; + + bool is_wow_mode = _FALSE; pHalData = GET_HAL_DATA(adapter); #ifdef DBG_CONFIG_ERROR_DETECT psrtpriv = &pHalData->srestpriv; #endif pxmitpriv = &adapter->xmitpriv; - pmlmeext = &adapter->mlmeextpriv; - pmlmeinfo = &pmlmeext->mlmext_info; pwrctl = adapter_to_pwrctl(adapter); rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize); if (PageSize == 0) { - RTW_INFO("[Error]: %s, PageSize is zero!!\n", __func__); + RTW_ERR("[Error]: %s, PageSize is zero!!\n", __func__); return; } + nr_assoc_if = _rtw_mi_assoc_if_num(adapter); - if (pwrctl->wowlan_mode == _TRUE || pwrctl->wowlan_ap_mode == _TRUE) - RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE); - else - RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE); + if ((pwrctl->wowlan_mode == _TRUE && pwrctl->wowlan_in_resume == _FALSE) || + pwrctl->wowlan_ap_mode == _TRUE || + pwrctl->wowlan_p2p_mode == _TRUE) + is_wow_mode = _TRUE; - RTW_INFO("%s PageSize: %d, RsvdPageNUm: %d\n", __func__, PageSize, RsvdPageNum); + /*page_num for init time to get rsvd page number*/ + /* Prepare ReservedPagePacket */ + if (page_num) { + ReservedPagePacket = rtw_zmalloc(MAX_CMDBUF_SZ); + if (!ReservedPagePacket) { + RTW_WARN("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); + *page_num = 0xFF; + return; + } + RTW_INFO(FUNC_ADPT_FMT" Get [ %s ] RsvdPageNUm ==>\n", + FUNC_ADPT_ARG(adapter), (is_wow_mode) ? "WOW" : "NOR"); - MaxRsvdPageBufSize = RsvdPageNum * PageSize; + } else { + if (is_wow_mode) + RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE); + else + RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE); - if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) { - RTW_INFO("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)", - __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ); - rtw_warn_on(1); - return; - } + RTW_INFO(FUNC_ADPT_FMT" PageSize: %d, [ %s ]-RsvdPageNUm: %d\n", + FUNC_ADPT_ARG(adapter), PageSize, (is_wow_mode) ? "WOW" : "NOR", RsvdPageNum); - pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv); + MaxRsvdPageBufSize = RsvdPageNum * PageSize; + if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) { + RTW_ERR("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)", + __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ); + rtw_warn_on(1); + return; + } - if (pcmdframe == NULL) { - RTW_INFO("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); - return; + pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv); + if (pcmdframe == NULL) { + RTW_ERR("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); + return; + } + + ReservedPagePacket = pcmdframe->buf_addr; } - ReservedPagePacket = pcmdframe->buf_addr; _rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC)); - /* beacon * 2 pages */ BufIndex = TxDescOffset; + + /*======== beacon content =======*/ rtw_hal_construct_beacon(adapter, &ReservedPagePacket[BufIndex], &BeaconLength); @@ -8496,22 +10316,32 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) * When we count the first page size, we need to reserve description size for the RSVD * packet, it will be filled in front of the packet in TXPKTBUF. */ + BeaconLength = MAX_BEACON_LEN - TxDescLen; CurtPktPageNum = (u8)PageNum((TxDescLen + BeaconLength), PageSize); - /* If we don't add 1 more page, ARP offload function will fail at 8723bs.*/ - if (CurtPktPageNum == 1) - CurtPktPageNum += 1; +#ifdef CONFIG_FW_HANDLE_TXBCN + CurtPktPageNum = CurtPktPageNum * CONFIG_LIMITED_AP_NUM; +#endif TotalPageNum += CurtPktPageNum; BufIndex += (CurtPktPageNum * PageSize); - if (pwrctl->wowlan_ap_mode == _TRUE) { + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("Beacon", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif + + /*======== probe response content ========*/ + if (pwrctl->wowlan_ap_mode == _TRUE) {/*WOW mode*/ + #ifdef CONFIG_CONCURRENT_MODE + if (nr_assoc_if >= 2) + RTW_ERR("Not support > 2 net-interface in WOW\n"); + #endif /* (4) probe response*/ RsvdPageLoc.LocProbeRsp = TotalPageNum; rtw_hal_construct_ProbeRsp( adapter, &ReservedPagePacket[BufIndex], &ProbeRspLength, - get_my_bssid(&pmlmeinfo->network), _FALSE); + _FALSE); rtw_hal_fill_fake_txdesc(adapter, &ReservedPagePacket[BufIndex - TxDescLen], ProbeRspLength, _FALSE, _FALSE, _FALSE); @@ -8520,102 +10350,168 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) TotalPageNum += CurtPktPageNum; TotalPacketLen = BufIndex + ProbeRspLength; BufIndex += (CurtPktPageNum * PageSize); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("ProbeRsp", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif goto download_page; } - /* ps-poll * 1 page */ - RsvdPageLoc.LocPsPoll = TotalPageNum; - RTW_INFO("LocPsPoll: %d\n", RsvdPageLoc.LocPsPoll); - rtw_hal_construct_PSPoll(adapter, - &ReservedPagePacket[BufIndex], &PSPollLength); - rtw_hal_fill_fake_txdesc(adapter, - &ReservedPagePacket[BufIndex - TxDescLen], - PSPollLength, _TRUE, _FALSE, _FALSE); - - CurtPktPageNum = (u8)PageNum((TxDescLen + PSPollLength), PageSize); + /*======== ps-poll content * 1 page ========*/ + sta_iface = adapter; + #ifdef CONFIG_CONCURRENT_MODE + if (!MLME_IS_STA(sta_iface) && DEV_STA_LD_NUM(adapter_to_dvobj(sta_iface))) { + sta_iface = _rtw_search_sta_iface(adapter); + RTW_INFO("get ("ADPT_FMT") to create PS-Poll/Null/QosNull\n", ADPT_ARG(sta_iface)); + } + #endif - TotalPageNum += CurtPktPageNum; + if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) { + RsvdPageLoc.LocPsPoll = TotalPageNum; + RTW_INFO("LocPsPoll: %d\n", RsvdPageLoc.LocPsPoll); + rtw_hal_construct_PSPoll(sta_iface, + &ReservedPagePacket[BufIndex], &PSPollLength); + rtw_hal_fill_fake_txdesc(sta_iface, + &ReservedPagePacket[BufIndex - TxDescLen], + PSPollLength, _TRUE, _FALSE, _FALSE); - BufIndex += (CurtPktPageNum * PageSize); + CurtPktPageNum = (u8)PageNum((TxDescLen + PSPollLength), PageSize); -#ifdef CONFIG_BT_COEXIST - /* BT Qos null data * 1 page */ - RsvdPageLoc.LocBTQosNull = TotalPageNum; - RTW_INFO("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull); - rtw_hal_construct_NullFunctionData( - adapter, - &ReservedPagePacket[BufIndex], - &BTQosNullLength, - get_my_bssid(&pmlmeinfo->network), - _TRUE, 0, 0, _FALSE); - rtw_hal_fill_fake_txdesc(adapter, - &ReservedPagePacket[BufIndex - TxDescLen], - BTQosNullLength, _FALSE, _TRUE, _FALSE); - - CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength, PageSize); - - TotalPageNum += CurtPktPageNum; + TotalPageNum += CurtPktPageNum; - BufIndex += (CurtPktPageNum * PageSize); -#endif /* CONFIG_BT_COEXIT */ + BufIndex += (CurtPktPageNum * PageSize); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("PSPoll", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif + } #ifdef CONFIG_MCC_MODE - if (MCC_EN(adapter)) { + /*======== MCC * n page ======== */ + if (MCC_EN(adapter)) {/*Normal mode*/ dl_mcc_page = rtw_hal_dl_mcc_fw_rsvd_page(adapter, ReservedPagePacket, - &BufIndex, TxDescLen, PageSize, - &TotalPageNum, &TotalPacketLen, &RsvdPageLoc); - } else + &BufIndex, TxDescLen, PageSize, &TotalPageNum, &RsvdPageLoc, page_num); + } else { dl_mcc_page = _FAIL; + } - if (dl_mcc_page == _FAIL) { + if (dl_mcc_page == _FAIL) #endif /* CONFIG_MCC_MODE */ - - /* null data * 1 page */ - RsvdPageLoc.LocNullData = TotalPageNum; - RTW_INFO("LocNullData: %d\n", RsvdPageLoc.LocNullData); - rtw_hal_construct_NullFunctionData( - adapter, - &ReservedPagePacket[BufIndex], - &NullDataLength, - get_my_bssid(&pmlmeinfo->network), - _FALSE, 0, 0, _FALSE); - rtw_hal_fill_fake_txdesc(adapter, + { /*======== null data * 1 page ======== */ + if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) { + RsvdPageLoc.LocNullData = TotalPageNum; + RTW_INFO("LocNullData: %d\n", RsvdPageLoc.LocNullData); + rtw_hal_construct_NullFunctionData( + sta_iface, + &ReservedPagePacket[BufIndex], + &NullDataLength, + _FALSE, 0, 0, _FALSE); + rtw_hal_fill_fake_txdesc(sta_iface, &ReservedPagePacket[BufIndex - TxDescLen], NullDataLength, _FALSE, _FALSE, _FALSE); - CurtPktPageNum = (u8)PageNum(TxDescLen + NullDataLength, PageSize); + CurtPktPageNum = (u8)PageNum(TxDescLen + NullDataLength, PageSize); - TotalPageNum += CurtPktPageNum; + TotalPageNum += CurtPktPageNum; - BufIndex += (CurtPktPageNum * PageSize); -#ifdef CONFIG_MCC_MODE + BufIndex += (CurtPktPageNum * PageSize); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("NullData", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif + } } -#endif /* CONFIG_MCC_MODE */ - /* Qos null data * 1 page */ - RsvdPageLoc.LocQosNull = TotalPageNum; - RTW_INFO("LocQosNull: %d\n", RsvdPageLoc.LocQosNull); - rtw_hal_construct_NullFunctionData( - adapter, - &ReservedPagePacket[BufIndex], - &QosNullLength, - get_my_bssid(&pmlmeinfo->network), - _TRUE, 0, 0, _FALSE); - rtw_hal_fill_fake_txdesc(adapter, - &ReservedPagePacket[BufIndex - TxDescLen], - QosNullLength, _FALSE, _FALSE, _FALSE); + /*======== Qos null data * 1 page ======== */ + if (pwrctl->wowlan_mode == _FALSE || + pwrctl->wowlan_in_resume == _TRUE) {/*Normal mode*/ + if (MLME_IS_STA(sta_iface) || (nr_assoc_if == 0)) { + RsvdPageLoc.LocQosNull = TotalPageNum; + RTW_INFO("LocQosNull: %d\n", RsvdPageLoc.LocQosNull); + rtw_hal_construct_NullFunctionData(sta_iface, + &ReservedPagePacket[BufIndex], + &QosNullLength, + _TRUE, 0, 0, _FALSE); + rtw_hal_fill_fake_txdesc(sta_iface, + &ReservedPagePacket[BufIndex - TxDescLen], + QosNullLength, _FALSE, _FALSE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength, + PageSize); + + TotalPageNum += CurtPktPageNum; + + BufIndex += (CurtPktPageNum * PageSize); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("QosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif + } + } - CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength, PageSize); +#ifdef CONFIG_BT_COEXIST + /*======== BT Qos null data * 1 page ======== */ + if (pwrctl->wowlan_mode == _FALSE || + pwrctl->wowlan_in_resume == _TRUE) {/*Normal mode*/ + + ap_iface = adapter; + #ifdef CONFIG_CONCURRENT_MODE + if (!MLME_IS_AP(ap_iface) && DEV_AP_NUM(adapter_to_dvobj(ap_iface))) { /*DEV_AP_STARTING_NUM*/ + ap_iface = _rtw_search_ap_iface(adapter); + RTW_INFO("get ("ADPT_FMT") to create BTQoSNull\n", ADPT_ARG(ap_iface)); + } + #endif - TotalPageNum += CurtPktPageNum; + if (MLME_IS_AP(ap_iface) || (nr_assoc_if == 0)) { + RsvdPageLoc.LocBTQosNull = TotalPageNum; - TotalPacketLen = BufIndex + QosNullLength; + RTW_INFO("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull); - BufIndex += (CurtPktPageNum * PageSize); + rtw_hal_construct_NullFunctionData(ap_iface, + &ReservedPagePacket[BufIndex], + &BTQosNullLength, + _TRUE, 0, 0, _FALSE); + + rtw_hal_fill_fake_txdesc(ap_iface, + &ReservedPagePacket[BufIndex - TxDescLen], + BTQosNullLength, _FALSE, _TRUE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength, + PageSize); + + TotalPageNum += CurtPktPageNum; + BufIndex += (CurtPktPageNum * PageSize); + + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("BTQosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen); + #endif + } + } +#endif /* CONFIG_BT_COEXIT */ + + TotalPacketLen = BufIndex; + +#ifdef DBG_FW_DEBUG_MSG_PKT + /*======== FW DEBUG MSG * n page ======== */ + RsvdPageLoc.loc_fw_dbg_msg_pkt = TotalPageNum; + RTW_INFO("loc_fw_dbg_msg_pkt: %d\n", RsvdPageLoc.loc_fw_dbg_msg_pkt); + rtw_hal_construct_fw_dbg_msg_pkt( + adapter, + &ReservedPagePacket[BufIndex], + &fw_dbg_msg_pkt_len); + + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex - TxDescLen], + fw_dbg_msg_pkt_len, _FALSE, _FALSE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + fw_dbg_msg_pkt_len, PageSize); + + TotalPageNum += CurtPktPageNum; + + TotalPacketLen = BufIndex + fw_dbg_msg_pkt_len; + BufIndex += (CurtPktPageNum * PageSize); +#endif /*DBG_FW_DEBUG_MSG_PKT*/ #ifdef CONFIG_WOWLAN + /*======== WOW * n page ======== */ if (pwrctl->wowlan_mode == _TRUE && - pwrctl->wowlan_in_resume == _FALSE) { + pwrctl->wowlan_in_resume == _FALSE) {/*WOW mode*/ rtw_hal_set_wow_fw_rsvd_page(adapter, ReservedPagePacket, BufIndex, TxDescLen, PageSize, &TotalPageNum, &TotalPacketLen, &RsvdPageLoc); @@ -8623,7 +10519,8 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) #endif /* CONFIG_WOWLAN */ #ifdef CONFIG_P2P_WOWLAN - if (_TRUE == pwrctl->wowlan_p2p_mode) { + /*======== P2P WOW * n page ======== */ + if (_TRUE == pwrctl->wowlan_p2p_mode) {/*WOW mode*/ rtw_hal_set_p2p_wow_fw_rsvd_page(adapter, ReservedPagePacket, BufIndex, TxDescLen, PageSize, &TotalPageNum, &TotalPacketLen, &RsvdPageLoc); @@ -8631,29 +10528,54 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) #endif /* CONFIG_P2P_WOWLAN */ #ifdef CONFIG_LPS_PG + /*======== LPS PG * 1 page ======== */ /* must reserved last 1 x page for LPS PG Info*/ pwrctl->lpspg_rsvd_page_locate = TotalPageNum; pwrctl->blpspg_info_up = _TRUE; + if (page_num) + TotalPageNum += LPS_PG_INFO_RSVD_PAGE_NUM; + + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("LPS_PG", LPS_PG_INFO_RSVD_PAGE_NUM, + (page_num) ? TotalPageNum : (TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM), + TotalPacketLen); + #endif + #endif + /*Note: BufIndex already add a TxDescOffset offset in first Beacon page + * The "TotalPacketLen" is calculate by BufIndex. + * We need to decrease TxDescOffset before doing length check. by yiwei + */ + TotalPacketLen = TotalPacketLen - TxDescOffset; + download_page: + if (page_num) { + *page_num = TotalPageNum; + rtw_mfree(ReservedPagePacket, MAX_CMDBUF_SZ); + ReservedPagePacket = NULL; + RTW_INFO(FUNC_ADPT_FMT" Get [ %s ] RsvdPageNUm <==\n", + FUNC_ADPT_ARG(adapter), (is_wow_mode) ? "WOW" : "NOR"); + return; + } + /* RTW_INFO("%s BufIndex(%d), TxDescLen(%d), PageSize(%d)\n",__func__, BufIndex, TxDescLen, PageSize);*/ RTW_INFO("%s PageNum(%d), pktlen(%d)\n", __func__, TotalPageNum, TotalPacketLen); #ifdef CONFIG_LPS_PG - if ((TotalPacketLen + (LPS_PG_INFO_RSVD_PAGE_NUM * PageSize)) > MaxRsvdPageBufSize) { + if ((TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM) > RsvdPageNum) { pwrctl->lpspg_rsvd_page_locate = 0; pwrctl->blpspg_info_up = _FALSE; - RTW_ERR("%s rsvd page size is not enough!!TotalPacketLen+LPS_PG_INFO_LEN %d, MaxRsvdPageBufSize %d\n", - __func__, (TotalPacketLen + (LPS_PG_INFO_RSVD_PAGE_NUM * PageSize)), MaxRsvdPageBufSize); + RTW_ERR("%s [LPS_PG] rsvd page %d is not enough! need %d pages\n", + __func__, RsvdPageNum, (TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM)); rtw_warn_on(1); } #endif if (TotalPacketLen > MaxRsvdPageBufSize) { - RTW_ERR("%s(ERROR): rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n", + RTW_ERR("%s : rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n", __FUNCTION__, TotalPacketLen, MaxRsvdPageBufSize); rtw_warn_on(1); goto error; @@ -8662,8 +10584,8 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) pattrib = &pcmdframe->attrib; update_mgntframe_attrib(adapter, pattrib); pattrib->qsel = QSLT_BEACON; - pattrib->pktlen = TotalPacketLen - TxDescOffset; - pattrib->last_txcmdsz = TotalPacketLen - TxDescOffset; + pattrib->pktlen = TotalPacketLen; + pattrib->last_txcmdsz = TotalPacketLen; #ifdef CONFIG_PCI_HCI dump_mgntframe(adapter, pcmdframe); #else @@ -8678,8 +10600,14 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) RTW_INFO_DUMP("\n", ReservedPagePacket, TotalPacketLen); RTW_INFO(" ==================================================\n"); #endif - if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + + + if (check_fwstate(pmlmepriv, _FW_LINKED) + || MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)){ rtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc); +#ifdef DBG_FW_DEBUG_MSG_PKT + rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(adapter, &RsvdPageLoc); +#endif /*DBG_FW_DEBUG_MSG_PKT*/ #ifdef CONFIG_WOWLAN if (pwrctl->wowlan_mode == _TRUE && pwrctl->wowlan_in_resume == _FALSE) @@ -8700,43 +10628,750 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) &RsvdPageLoc, 1); #endif /* CONFIG_PNO_SUPPORT */ } + #ifdef CONFIG_P2P_WOWLAN if (_TRUE == pwrctl->wowlan_p2p_mode) rtw_hal_set_FwP2PRsvdPage_cmd(adapter, &RsvdPageLoc); #endif /* CONFIG_P2P_WOWLAN */ + return; error: rtw_free_xmitframe(pxmitpriv, pcmdframe); } -static void rtw_hal_set_hw_update_tsf(PADAPTER padapter) + +void rtw_hal_set_fw_rsvd_page(struct _ADAPTER *adapter, bool finished) +{ + if (finished) + rtw_mi_tx_beacon_hdl(adapter); + else + _rtw_hal_set_fw_rsvd_page(adapter, finished, NULL); +} + +/** + * rtw_hal_get_rsvd_page_num() - Get needed reserved page number + * @adapter: struct _ADAPTER* + * + * Caculate needed reserved page number. + * In different state would get different number, for example normal mode and + * WOW mode would need different reserved page size. + * + * Return the number of reserved page which driver need. + */ +u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter) +{ + u8 num = 0; + + + _rtw_hal_set_fw_rsvd_page(adapter, _FALSE, &num); + + return num; +} + +static void hw_var_set_bcn_func(_adapter *adapter, u8 enable) +{ + u32 bcn_ctrl_reg; + +#ifdef CONFIG_CONCURRENT_MODE + if (adapter->hw_port == HW_PORT1) + bcn_ctrl_reg = REG_BCN_CTRL_1; + else +#endif + bcn_ctrl_reg = REG_BCN_CTRL; + + if (enable) + rtw_write8(adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT)); + else { + u8 val8; + + val8 = rtw_read8(adapter, bcn_ctrl_reg); + val8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT); + +#ifdef CONFIG_BT_COEXIST + if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == 1) { + /* Always enable port0 beacon function for PSTDMA */ + if (REG_BCN_CTRL == bcn_ctrl_reg) + val8 |= EN_BCN_FUNCTION; + } +#endif + + rtw_write8(adapter, bcn_ctrl_reg, val8); + } + +#ifdef CONFIG_RTL8192F + if (IS_HARDWARE_TYPE_8192F(adapter)) { + u16 val16, val16_ori; + + val16_ori = val16 = rtw_read16(adapter, REG_WLAN_ACT_MASK_CTRL_1); + + #ifdef CONFIG_CONCURRENT_MODE + if (adapter->hw_port == HW_PORT1) { + if (enable) + val16 |= EN_PORT_1_FUNCTION; + else + val16 &= ~EN_PORT_1_FUNCTION; + } else + #endif + { + if (enable) + val16 |= EN_PORT_0_FUNCTION; + else + val16 &= ~EN_PORT_0_FUNCTION; + + #ifdef CONFIG_BT_COEXIST + if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == 1) + val16 |= EN_PORT_0_FUNCTION; + #endif + } + + if (val16 != val16_ori) + rtw_write16(adapter, REG_WLAN_ACT_MASK_CTRL_1, val16); + } +#endif +} + +static void hw_var_set_mlme_disconnect(_adapter *adapter) +{ + u8 val8; + + /* reject all data frames */ +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE) +#endif + rtw_write16(adapter, REG_RXFLTMAP2, 0x0000); + +#ifdef CONFIG_CONCURRENT_MODE + if (adapter->hw_port == HW_PORT1) { + /* reset TSF1 */ + rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1)); + + /* disable update TSF1 */ + rtw_iface_disable_tsf_update(adapter); + + if (!IS_HARDWARE_TYPE_8723D(adapter) + && !IS_HARDWARE_TYPE_8192F(adapter) + && !IS_HARDWARE_TYPE_8710B(adapter) + ) { + /* disable Port1's beacon function */ + val8 = rtw_read8(adapter, REG_BCN_CTRL_1); + val8 &= ~EN_BCN_FUNCTION; + rtw_write8(adapter, REG_BCN_CTRL_1, val8); + } + } else +#endif + { + /* reset TSF */ + rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(0)); + + /* disable update TSF */ + rtw_iface_disable_tsf_update(adapter); + } +} + +static void hw_var_set_mlme_sitesurvey(_adapter *adapter, u8 enable) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u16 value_rxfltmap2; + int i; + _adapter *iface; + +#ifdef DBG_IFACE_STATUS + DBG_IFACE_STATUS_DUMP(adapter); +#endif + +#ifdef CONFIG_FIND_BEST_CHANNEL + /* Receive all data frames */ + value_rxfltmap2 = 0xFFFF; +#else + /* not to receive data frame */ + value_rxfltmap2 = 0; +#endif + + if (enable) { /* under sitesurvey */ + /* + * 1. configure REG_RXFLTMAP2 + * 2. disable TSF update & buddy TSF update to avoid updating wrong TSF due to clear RCR_CBSSID_BCN + * 3. config RCR to receive different BSSID BCN or probe rsp + */ + rtw_write16(adapter, REG_RXFLTMAP2, value_rxfltmap2); + + rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER); + + /* Save orignal RRSR setting. needed? */ + hal_data->RegRRSR = rtw_read16(adapter, REG_RRSR); + + #if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)) + if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) { + /* set 718[1:0]=2'b00 to avoid BF scan hang */ + hal_data->backup_snd_ptcl_ctrl = rtw_read8(adapter, REG_SND_PTCL_CTRL_8812A); + rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, (hal_data->backup_snd_ptcl_ctrl & 0xfc)); + } + #endif + + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) + StopTxBeacon(adapter); + } else { /* sitesurvey done */ + /* + * 1. enable rx data frame + * 2. config RCR not to receive different BSSID BCN or probe rsp + * 3. doesn't enable TSF update & buddy TSF right now to avoid HW conflict + * so, we enable TSF update when rx first BCN after sitesurvey done + */ + if (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE)) { + /* enable to rx data frame */ + rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF); + } + + rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE); + + /* Restore orignal RRSR setting. needed? */ + rtw_write16(adapter, REG_RRSR, hal_data->RegRRSR); + + #if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)) + if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) { + /* Restore orignal 0x718 setting*/ + rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, hal_data->backup_snd_ptcl_ctrl); + } + #endif + + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) { + ResumeTxBeacon(adapter); + rtw_mi_tx_beacon_hdl(adapter); + } + } +} + +static void hw_var_set_mlme_join(_adapter *adapter, u8 type) +{ + u8 val8; + u16 val16; + u32 val32; + u8 RetryLimit = RL_VAL_STA; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + +#ifdef CONFIG_CONCURRENT_MODE + if (type == 0) { + /* prepare to join */ + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) + StopTxBeacon(adapter); + + /* enable to rx data frame.Accept all data frame */ + rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF); + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + RetryLimit = (hal_data->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA; + else /* Ad-hoc Mode */ + RetryLimit = RL_VAL_AP; + + rtw_iface_enable_tsf_update(adapter); + + } else if (type == 1) { + /* joinbss_event call back when join res < 0 */ + if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE) + rtw_write16(adapter, REG_RXFLTMAP2, 0x00); + + rtw_iface_disable_tsf_update(adapter); + + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) { + ResumeTxBeacon(adapter); + + /* reset TSF 1/2 after ResumeTxBeacon */ + rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0)); + } + + } else if (type == 2) { + /* sta add event call back */ + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { + /* fixed beacon issue for 8191su........... */ + rtw_write8(adapter, 0x542 , 0x02); + RetryLimit = RL_VAL_AP; + } + + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) { + ResumeTxBeacon(adapter); + + /* reset TSF 1/2 after ResumeTxBeacon */ + rtw_write8(adapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0)); + } + } + + val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit); + rtw_write16(adapter, REG_RETRY_LIMIT, val16); +#else /* !CONFIG_CONCURRENT_MODE */ + if (type == 0) { /* prepare to join */ + /* enable to rx data frame.Accept all data frame */ + rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF); + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + RetryLimit = (hal_data->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA; + else /* Ad-hoc Mode */ + RetryLimit = RL_VAL_AP; + + rtw_iface_enable_tsf_update(adapter); + + } else if (type == 1) { /* joinbss_event call back when join res < 0 */ + rtw_write16(adapter, REG_RXFLTMAP2, 0x00); + + rtw_iface_disable_tsf_update(adapter); + + } else if (type == 2) { /* sta add event call back */ + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) + RetryLimit = RL_VAL_AP; + } + + val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit); + rtw_write16(adapter, REG_RETRY_LIMIT, val16); +#endif /* !CONFIG_CONCURRENT_MODE */ +} + +#ifdef CONFIG_TSF_RESET_OFFLOAD +static int rtw_hal_h2c_reset_tsf(_adapter *adapter, u8 reset_port) +{ + u8 buf[2]; + int ret; + + if (reset_port == HW_PORT0) { + buf[0] = 0x1; + buf[1] = 0; + } else { + buf[0] = 0x0; + buf[1] = 0x1; + } + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_RESET_TSF, 2, buf); + + return ret; +} + +int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port) +{ + u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0; + u32 reg_reset_tsf_cnt = (reset_port == HW_PORT0) ? + REG_FW_RESET_TSF_CNT_0 : REG_FW_RESET_TSF_CNT_1; + int ret; + + /* site survey will cause reset tsf fail */ + rtw_mi_buddy_scan_abort(adapter, _FALSE); + reset_cnt_after = reset_cnt_before = rtw_read8(adapter, reg_reset_tsf_cnt); + ret = rtw_hal_h2c_reset_tsf(adapter, reset_port); + if (ret != _SUCCESS) + return ret; + + while ((reset_cnt_after == reset_cnt_before) && (loop_cnt < 10)) { + rtw_msleep_os(100); + loop_cnt++; + reset_cnt_after = rtw_read8(adapter, reg_reset_tsf_cnt); + } + + return (loop_cnt >= 10) ? _FAIL : _SUCCESS; +} +#endif /* CONFIG_TSF_RESET_OFFLOAD */ + +#ifdef CONFIG_HW_P0_TSF_SYNC +#ifdef CONFIG_CONCURRENT_MODE +static void hw_port0_tsf_sync_sel(_adapter *adapter, u8 benable, u8 hw_port, u16 tr_offset) +{ + u8 val8; + u8 client_id = 0; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + +#ifdef CONFIG_MCC_MODE + if (MCC_EN(adapter) && (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))) { + RTW_INFO("[MCC] do not set HW TSF sync\n"); + return; + } +#endif + /* check if port0 is already synced */ + if (benable && dvobj->p0_tsf.sync_port != MAX_HW_PORT && dvobj->p0_tsf.sync_port == hw_port) { + RTW_WARN(FUNC_ADPT_FMT ": port0 already enable TSF sync(%d)\n", + FUNC_ADPT_ARG(adapter), dvobj->p0_tsf.sync_port); + return; + } + + /* check if port0 already disable sync */ + if (!benable && dvobj->p0_tsf.sync_port == MAX_HW_PORT) { + RTW_WARN(FUNC_ADPT_FMT ": port0 already disable TSF sync\n", FUNC_ADPT_ARG(adapter)); + return; + } + + /* check if port0 sync to port0 */ + if (benable && hw_port == HW_PORT0) { + RTW_ERR(FUNC_ADPT_FMT ": hw_port is port0 under enable\n", FUNC_ADPT_ARG(adapter)); + rtw_warn_on(1); + return; + } + + /*0x5B4 [6:4] :SYNC_CLI_SEL - The selector for the CLINT port of sync tsft source for port 0*/ + /* Bit[5:4] : 0 for clint0, 1 for clint1, 2 for clint2, 3 for clint3. + Bit6 : 1= enable sync to port 0. 0=disable sync to port 0.*/ + + val8 = rtw_read8(adapter, REG_TIMER0_SRC_SEL); + + if (benable) { + /*Disable Port0's beacon function*/ + rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL) & ~BIT_EN_BCN_FUNCTION); + + /*Reg 0x518[15:0]: TSFTR_SYN_OFFSET*/ + if (tr_offset) + rtw_write16(adapter, REG_TSFTR_SYN_OFFSET, tr_offset); + + /*reg 0x577[6]=1*/ /*auto sync by tbtt*/ + rtw_write8(adapter, REG_MISC_CTRL, rtw_read8(adapter, REG_MISC_CTRL) | BIT_AUTO_SYNC_BY_TBTT); + + if (HW_PORT1 == hw_port) + client_id = 0; + else if (HW_PORT2 == hw_port) + client_id = 1; + else if (HW_PORT3 == hw_port) + client_id = 2; + else if (HW_PORT4 == hw_port) + client_id = 3; + + val8 &= 0x8F; + val8 |= (BIT(6) | (client_id << 4)); + + dvobj->p0_tsf.sync_port = hw_port; + dvobj->p0_tsf.offset = tr_offset; + rtw_write8(adapter, REG_TIMER0_SRC_SEL, val8); + + /*Enable Port0's beacon function*/ + rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL) | BIT_EN_BCN_FUNCTION); + RTW_INFO("%s Port_%d TSF sync to P0, timer offset :%d\n", __func__, hw_port, tr_offset); + } else { + val8 &= ~BIT(6); + + dvobj->p0_tsf.sync_port = MAX_HW_PORT; + dvobj->p0_tsf.offset = 0; + rtw_write8(adapter, REG_TIMER0_SRC_SEL, val8); + RTW_INFO("%s P0 TSF sync disable\n", __func__); + } +} +static _adapter * _search_ld_sta(_adapter *adapter, u8 include_self) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 i; + _adapter *iface = NULL; + + if (rtw_mi_get_assoced_sta_num(adapter) == 0) { + RTW_ERR("STA_LD_NUM == 0\n"); + rtw_warn_on(1); + } + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + if (include_self == _FALSE && adapter == iface) + continue; + if (is_client_associated_to_ap(iface)) + break; + } + if (iface) + RTW_INFO("search STA iface -"ADPT_FMT"\n", ADPT_ARG(iface)); + return iface; +} +#endif /*CONFIG_CONCURRENT_MODE*/ +/*Correct port0's TSF*/ +/*#define DBG_P0_TSF_SYNC*/ +void hw_var_set_correct_tsf(PADAPTER adapter, u8 mlme_state) +{ +#ifdef CONFIG_CONCURRENT_MODE + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 p0_tsfsync = _FALSE; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + _adapter *sta_if = NULL; + u8 hw_port; + + RTW_INFO(FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(adapter)); + #ifdef DBG_P0_TSF_SYNC + RTW_INFO("[TSF_SYNC] AP_NUM = %d\n", rtw_mi_get_ap_num(adapter)); + RTW_INFO("[TSF_SYNC] MESH_NUM = %d\n", rtw_mi_get_mesh_num(adapter)); + RTW_INFO("[TSF_SYNC] LD_STA_NUM = %d\n", rtw_mi_get_assoced_sta_num(adapter)); + if (dvobj->p0_tsf.sync_port == MAX_HW_PORT) + RTW_INFO("[TSF_SYNC] org p0 sync port = N/A\n"); + else + RTW_INFO("[TSF_SYNC] org p0 sync port = %d\n", dvobj->p0_tsf.sync_port); + RTW_INFO("[TSF_SYNC] timer offset = %d\n", dvobj->p0_tsf.offset); + #endif + switch (mlme_state) { + case MLME_STA_CONNECTED : + { + hw_port = rtw_hal_get_port(adapter); + + if (!MLME_IS_STA(adapter)) { + RTW_ERR("STA CON state,but iface("ADPT_FMT") is not STA\n", ADPT_ARG(adapter)); + rtw_warn_on(1); + } + + if ((dvobj->p0_tsf.sync_port != MAX_HW_PORT) && (hw_port == HW_PORT0)) { + RTW_ERR(ADPT_FMT" is STA with P0 connected => DIS P0_TSF_SYNC\n", ADPT_ARG(adapter)); + rtw_warn_on(1); + hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0); + } + + if ((dvobj->p0_tsf.sync_port == MAX_HW_PORT) && + (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))) { + hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/ + #ifdef DBG_P0_TSF_SYNC + RTW_INFO("[TSF_SYNC] STA_LINKED => EN P0_TSF_SYNC\n"); + #endif + } + } + break; + case MLME_STA_DISCONNECTED : + { + hw_port = rtw_hal_get_port(adapter); + + if (!MLME_IS_STA(adapter)) { + RTW_ERR("STA DIS_CON state,but iface("ADPT_FMT") is not STA\n", ADPT_ARG(adapter)); + rtw_warn_on(1); + } + + if (dvobj->p0_tsf.sync_port == hw_port) { + if (rtw_mi_get_assoced_sta_num(adapter) >= 2) { + /* search next appropriate sta*/ + sta_if = _search_ld_sta(adapter, _FALSE); + if (sta_if) { + hw_port = rtw_hal_get_port(sta_if); + hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/ + #ifdef DBG_P0_TSF_SYNC + RTW_INFO("[TSF_SYNC] STA_DIS_CON => CHANGE P0_TSF_SYNC\n"); + #endif + } + } else if (rtw_mi_get_assoced_sta_num(adapter) == 1) { + hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0); + #ifdef DBG_P0_TSF_SYNC + RTW_INFO("[TSF_SYNC] STA_DIS_CON => DIS P0_TSF_SYNC\n"); + #endif + } + } + } + break; + case MLME_AP_STARTED : + case MLME_MESH_STARTED : + { + if (!(MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))) { + RTW_ERR("AP START state,but iface("ADPT_FMT") is not AP\n", ADPT_ARG(adapter)); + rtw_warn_on(1); + } + + if ((dvobj->p0_tsf.sync_port == MAX_HW_PORT) && + rtw_mi_get_assoced_sta_num(adapter)) { + /* get port of sta */ + sta_if = _search_ld_sta(adapter, _FALSE); + if (sta_if) { + hw_port = rtw_hal_get_port(sta_if); + hw_port0_tsf_sync_sel(adapter, _TRUE, hw_port, 50);/*timer offset 50ms*/ + #ifdef DBG_P0_TSF_SYNC + RTW_INFO("[TSF_SYNC] AP_START => EN P0_TSF_SYNC\n"); + #endif + } + } + } + break; + case MLME_AP_STOPPED : + case MLME_MESH_STOPPED : + { + if (!(MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))) { + RTW_ERR("AP START state,but iface("ADPT_FMT") is not AP\n", ADPT_ARG(adapter)); + rtw_warn_on(1); + } + /*stop ap mode*/ + if ((rtw_mi_get_ap_num(adapter) + rtw_mi_get_mesh_num(adapter) == 1) && + (dvobj->p0_tsf.sync_port != MAX_HW_PORT)) { + hw_port0_tsf_sync_sel(adapter, _FALSE, 0, 0); + #ifdef DBG_P0_TSF_SYNC + RTW_INFO("[TSF_SYNC] AP_STOP => DIS P0_TSF_SYNC\n"); + #endif + } + } + break; + default : + RTW_ERR(FUNC_ADPT_FMT" unknow state(0x%02x)\n", FUNC_ADPT_ARG(adapter), mlme_state); + break; + } + + /*#ifdef DBG_P0_TSF_SYNC*/ + #if 1 + if (dvobj->p0_tsf.sync_port == MAX_HW_PORT) + RTW_INFO("[TSF_SYNC] p0 sync port = N/A\n"); + else + RTW_INFO("[TSF_SYNC] p0 sync port = %d\n", dvobj->p0_tsf.sync_port); + RTW_INFO("[TSF_SYNC] timer offset = %d\n", dvobj->p0_tsf.offset); + #endif +#endif /*CONFIG_CONCURRENT_MODE*/ +} + +#else +static void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf) +{ + if (hw_port == HW_PORT0) { + /*disable related TSF function*/ + rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) & (~EN_BCN_FUNCTION)); +#if defined(CONFIG_RTL8192F) + rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter, + REG_WLAN_ACT_MASK_CTRL_1) & ~EN_PORT_0_FUNCTION); +#endif + + rtw_write32(padapter, REG_TSFTR, tsf); + rtw_write32(padapter, REG_TSFTR + 4, tsf >> 32); + + /*enable related TSF function*/ + rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | EN_BCN_FUNCTION); +#if defined(CONFIG_RTL8192F) + rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter, + REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_0_FUNCTION); +#endif + } else if (hw_port == HW_PORT1) { + /*disable related TSF function*/ + rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) & (~EN_BCN_FUNCTION)); +#if defined(CONFIG_RTL8192F) + rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter, + REG_WLAN_ACT_MASK_CTRL_1) & ~EN_PORT_1_FUNCTION); +#endif + + rtw_write32(padapter, REG_TSFTR1, tsf); + rtw_write32(padapter, REG_TSFTR1 + 4, tsf >> 32); + + /*enable related TSF function*/ + rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) | EN_BCN_FUNCTION); +#if defined(CONFIG_RTL8192F) + rtw_write16(padapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(padapter, + REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_1_FUNCTION); +#endif + } else + RTW_INFO("%s-[WARN] "ADPT_FMT" invalid hw_port:%d\n", __func__, ADPT_ARG(padapter), hw_port); +} + +static void hw_var_set_correct_tsf(_adapter *adapter, u8 mlme_state) +{ +#ifdef CONFIG_MI_WITH_MBSSID_CAM + /*do nothing*/ +#else + u64 tsf; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); + + tsf = mlmeext->TSFValue - rtw_modular64(mlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024)) - 1024; /*us*/ + + if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE + || (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) + StopTxBeacon(adapter); + + rtw_hal_correct_tsf(adapter, adapter->hw_port, tsf); + +#ifdef CONFIG_CONCURRENT_MODE + /* Update buddy port's TSF if it is SoftAP/Mesh for beacon TX issue! */ + if ((mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE + && (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) + ) { + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + int i; + _adapter *iface; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + if (iface == adapter) + continue; + + if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface)) + && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE + ) { + rtw_hal_correct_tsf(iface, iface->hw_port, tsf); + #ifdef CONFIG_TSF_RESET_OFFLOAD + if (rtw_hal_reset_tsf(iface, iface->hw_port) == _FAIL) + RTW_INFO("%s-[ERROR] "ADPT_FMT" Reset port%d TSF fail\n" + , __func__, ADPT_ARG(iface), iface->hw_port); + #endif /* CONFIG_TSF_RESET_OFFLOAD*/ + } + } + } +#endif /* CONFIG_CONCURRENT_MODE */ + + if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE + || (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) + ResumeTxBeacon(adapter); + +#endif /*CONFIG_MI_WITH_MBSSID_CAM*/ +} +#endif + +u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port) { - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u64 tsftr = 0; -#if defined(CONFIG_RTL8822B) || defined(CONFIG_MI_WITH_MBSSID_CAM) - RTW_INFO("[Warn] %s "ADPT_FMT" enter func\n", __func__, ADPT_ARG(padapter)); - rtw_warn_on(1); - return; + if (port >= hal_spec->port_num) { + RTW_ERR("%s invalid port(%d) \n", __func__, port); + goto exit; + } + + switch (rtw_get_chip_type(adapter)) { +#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) + case RTL8814A: + case RTL8822B: + case RTL8821C: + { + u8 val8; + + /* 0x554[30:28] - BIT_BCN_TIMER_SEL_FWRD */ + val8 = rtw_read8(adapter, REG_MBSSID_BCN_SPACE + 3); + val8 &= 0x8F; + val8 |= port << 4; + rtw_write8(adapter, REG_MBSSID_BCN_SPACE + 3, val8); + + tsftr = rtw_read32(adapter, REG_TSFTR + 4); + tsftr = tsftr << 32; + tsftr |= rtw_read32(adapter, REG_TSFTR); + + break; + } #endif +#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) \ + || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) \ + || defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D) \ + || defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) \ + || defined(CONFIG_RTL8710B) + case RTL8188E: + case RTL8188F: + case RTL8188GTV: + case RTL8192E: + case RTL8192F: + case RTL8723B: + case RTL8703B: + case RTL8723D: + case RTL8812: + case RTL8821: + case RTL8710B: + { + u32 addr; - if (!pmlmeext->en_hw_update_tsf) - return; + if (port == HW_PORT0) + addr = REG_TSFTR; + else if (port == HW_PORT1) + addr = REG_TSFTR1; + else { + RTW_ERR("%s unknown port(%d) \n", __func__, port); + goto exit; + } - /* check REG_RCR bit is set */ - if (!(rtw_read32(padapter, REG_RCR) & RCR_CBSSID_BCN)) - return; + tsftr = rtw_read32(adapter, addr + 4); + tsftr = tsftr << 32; + tsftr |= rtw_read32(adapter, addr); - /* enable hw update tsf function for non-AP */ - if (rtw_linked_check(padapter) && - check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) { -#ifdef CONFIG_CONCURRENT_MODE - if (padapter->hw_port == HW_PORT1) - rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) & (~DIS_TSF_UDT)); - else + break; + } #endif - rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) & (~DIS_TSF_UDT)); + default: + RTW_ERR("%s unknow chip type\n", __func__); } - pmlmeext->en_hw_update_tsf = _FALSE; + +exit: + return tsftr; } #ifdef CONFIG_TDLS @@ -8767,28 +11402,57 @@ s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset #endif #endif -#ifdef CONFIG_WMMPS +#ifdef CONFIG_WMMPS_STA void rtw_hal_update_uapsd_tid(_adapter *adapter) { - rtw_write8(adapter, REG_WMMPS_UAPSD_TID, 0xFF); + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + + /* write complement of pqospriv->uapsd_tid to mac register 0x693 because + it's designed for "0" represents "enable" and "1" represents "disable" */ + rtw_write8(adapter, REG_WMMPS_UAPSD_TID, (u8)(~pqospriv->uapsd_tid)); } -#endif +#endif /* CONFIG_WMMPS_STA */ #if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) /* For multi-port support, driver needs to inform the port ID to FW for btc operations */ -s32 rtw_hal_set_wifi_port_id_cmd(_adapter *adapter) +s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter) { - u8 port_id = 0; u8 h2c_buf[H2C_BTC_WL_PORT_ID_LEN] = {0}; + u8 hw_port = rtw_hal_get_port(adapter); - SET_H2CCMD_BTC_WL_PORT_ID(h2c_buf, adapter->hw_port); + SET_H2CCMD_BTC_WL_PORT_ID(h2c_buf, hw_port); + RTW_INFO("%s ("ADPT_FMT") - hw_port :%d\n", __func__, ADPT_ARG(adapter), hw_port); return rtw_hal_fill_h2c_cmd(adapter, H2C_BTC_WL_PORT_ID, H2C_BTC_WL_PORT_ID_LEN, h2c_buf); } #endif -void SetHwReg(_adapter *adapter, u8 variable, u8 *val) +#define LPS_ACTIVE_TIMEOUT 10 /*number of times*/ +void rtw_lps_state_chk(_adapter *adapter, u8 ps_mode) +{ + if (ps_mode == PS_MODE_ACTIVE) { + u8 ps_ready = _FALSE; + s8 leave_wait_count = LPS_ACTIVE_TIMEOUT; + + do { + if ((rtw_read8(adapter, REG_TCR) & BIT_PWRBIT_OW_EN) == 0) { + ps_ready = _TRUE; + break; + } + rtw_msleep_os(1); + } while (leave_wait_count--); + + if (ps_ready == _FALSE) { + RTW_ERR(FUNC_ADPT_FMT" PS_MODE_ACTIVE check failed\n", FUNC_ADPT_ARG(adapter)); + rtw_warn_on(1); + } + } +} + +u8 SetHwReg(_adapter *adapter, u8 variable, u8 *val) { HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 ret = _SUCCESS; switch (variable) { case HW_VAR_MEDIA_STATUS: { @@ -8797,6 +11461,12 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) rtw_hal_set_msr(adapter, net_type); } break; + case HW_VAR_DO_IQK: + if (*val) + hal_data->bNeedIQK = _TRUE; + else + hal_data->bNeedIQK = _FALSE; + break; case HW_VAR_MAC_ADDR: #ifdef CONFIG_MI_WITH_MBSSID_CAM rtw_hal_set_macaddr_mbid(adapter, val); @@ -8807,6 +11477,18 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) case HW_VAR_BSSID: rtw_hal_set_bssid(adapter, val); break; + case HW_VAR_RCR: + ret = hw_var_rcr_config(adapter, *((u32 *)val)); + break; + case HW_VAR_ON_RCR_AM: + hw_var_set_rcr_am(adapter, 1); + break; + case HW_VAR_OFF_RCR_AM: + hw_var_set_rcr_am(adapter, 0); + break; + case HW_VAR_BEACON_INTERVAL: + hw_var_set_bcn_interval(adapter, *(u16 *)val); + break; #ifdef CONFIG_MBSSID_CAM case HW_VAR_MBSSID_CAM_WRITE: { u32 cmd = 0; @@ -8829,14 +11511,9 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) break; case HW_VAR_RCR_MBSSID_EN: if (*((u8 *)val)) - rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR) | RCR_ENMBID); - else { - u32 val32; - - val32 = rtw_read32(adapter, REG_RCR); - val32 &= ~(RCR_ENMBID); - rtw_write32(adapter, REG_RCR, val32); - } + rtw_hal_rcr_add(adapter, RCR_ENMBID); + else + rtw_hal_rcr_clear(adapter, RCR_ENMBID); break; #endif case HW_VAR_PORT_SWITCH: @@ -8937,40 +11614,149 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val) break; #endif /*defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)*/ + case HW_VAR_BCN_FUNC: + hw_var_set_bcn_func(adapter, *val); + break; + + case HW_VAR_MLME_DISCONNECT: + hw_var_set_mlme_disconnect(adapter); + break; + + case HW_VAR_MLME_SITESURVEY: + hw_var_set_mlme_sitesurvey(adapter, *val); + #ifdef CONFIG_BT_COEXIST + if (hal_data->EEPROMBluetoothCoexist == 1) + rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE); + #endif + break; + + case HW_VAR_MLME_JOIN: + hw_var_set_mlme_join(adapter, *val); + #ifdef CONFIG_BT_COEXIST + if (hal_data->EEPROMBluetoothCoexist == 1) { + switch (*val) { + case 0: + /* Notify coex. mechanism before join */ + rtw_btcoex_ConnectNotify(adapter, _TRUE); + break; + case 1: + case 2: + /* Notify coex. mechanism after join, whether successful or failed */ + rtw_btcoex_ConnectNotify(adapter, _FALSE); + break; + } + } + #endif /* CONFIG_BT_COEXIST */ + break; + case HW_VAR_EN_HW_UPDATE_TSF: rtw_hal_set_hw_update_tsf(adapter); break; + case HW_VAR_CORRECT_TSF: + hw_var_set_correct_tsf(adapter, *val); + break; +#if defined(CONFIG_HW_P0_TSF_SYNC) && defined(CONFIG_CONCURRENT_MODE) + case HW_VAR_TSF_AUTO_SYNC: + if (*val == _TRUE) + hw_port0_tsf_sync_sel(adapter, _TRUE, adapter->hw_port, 50); + else + hw_port0_tsf_sync_sel(adapter, _FALSE, adapter->hw_port, 50); + break; +#endif case HW_VAR_APFM_ON_MAC: hal_data->bMacPwrCtrlOn = *val; RTW_INFO("%s: bMacPwrCtrlOn=%d\n", __func__, hal_data->bMacPwrCtrlOn); break; -#ifdef CONFIG_WMMPS +#ifdef CONFIG_WMMPS_STA case HW_VAR_UAPSD_TID: rtw_hal_update_uapsd_tid(adapter); break; -#endif +#endif /* CONFIG_WMMPS_STA */ #ifdef CONFIG_LPS_PG case HW_VAR_LPS_PG_HANDLE: rtw_hal_lps_pg_handler(adapter, *val); break; #endif +#ifdef CONFIG_LPS_LCLK_WD_TIMER + case HW_VAR_DM_IN_LPS_LCLK: + rtw_phydm_wd_lps_lclk_hdl(adapter); + break; +#endif + case HW_VAR_ENABLE_RX_BAR: + if (*val == _TRUE) { + /* enable RX BAR */ + u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1); + + val16 |= BIT(8); + rtw_write16(adapter, REG_RXFLTMAP1, val16); + } else { + /* disable RX BAR */ + u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1); + + val16 &= (~BIT(8)); + rtw_write16(adapter, REG_RXFLTMAP1, val16); + } + RTW_INFO("[HW_VAR_ENABLE_RX_BAR] 0x%02X=0x%02X\n", + REG_RXFLTMAP1, rtw_read16(adapter, REG_RXFLTMAP1)); + break; + case HW_VAR_HCI_SUS_STATE: + hal_data->hci_sus_state = *(u8 *)val; + RTW_INFO("%s: hci_sus_state=%u\n", __func__, hal_data->hci_sus_state); + break; +#if defined(CONFIG_AP_MODE) && defined(CONFIG_FW_HANDLE_TXBCN) && defined(CONFIG_SUPPORT_MULTI_BCN) + case HW_VAR_BCN_HEAD_SEL: + { + u8 vap_id = *(u8 *)val; + + if ((vap_id >= CONFIG_LIMITED_AP_NUM) && (vap_id != 0xFF)) { + RTW_ERR(ADPT_FMT " vap_id(%d:%d) is invalid\n", ADPT_ARG(adapter),vap_id, adapter->vap_id); + rtw_warn_on(1); + } + if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) { + u16 drv_pg_bndy = 0, bcn_addr = 0; + u32 page_size = 0; + + /*rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_BOUNDARY, &drv_pg_bndy);*/ + rtw_halmac_get_rsvd_drv_pg_bndy(adapter_to_dvobj(adapter), &drv_pg_bndy); + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&page_size); + if (vap_id != 0xFF) + bcn_addr = drv_pg_bndy + (vap_id * (MAX_BEACON_LEN / page_size)); + else + bcn_addr = drv_pg_bndy; + RTW_INFO(ADPT_FMT" vap_id(%d) change BCN HEAD to 0x%04x\n", + ADPT_ARG(adapter), vap_id, bcn_addr); + rtw_write16(adapter, REG_FIFOPAGE_CTRL_2, + (bcn_addr & BIT_MASK_BCN_HEAD_1_V1) | BIT_BCN_VALID_V1); + } + } + break; +#endif + case HW_VAR_LPS_STATE_CHK : + rtw_lps_state_chk(adapter, *(u8 *)val); + break; default: if (0) RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n", FUNC_ADPT_ARG(adapter), variable); + ret = _FAIL; break; } + return ret; } void GetHwReg(_adapter *adapter, u8 variable, u8 *val) { HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u64 val64; switch (variable) { + case HW_VAR_MAC_ADDR: + rtw_hal_get_macaddr_port(adapter, val); + break; case HW_VAR_BASIC_RATE: *((u16 *)val) = hal_data->BasicRateSet; break; @@ -8992,6 +11778,39 @@ void GetHwReg(_adapter *adapter, u8 variable, u8 *val) case HW_VAR_APFM_ON_MAC: *val = hal_data->bMacPwrCtrlOn; break; + case HW_VAR_RCR: + hw_var_rcr_get(adapter, (u32 *)val); + break; + case HW_VAR_FWLPS_RF_ON: + /* When we halt NIC, we should check if FW LPS is leave. */ + if (rtw_is_surprise_removed(adapter) + || (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off) + ) { + /* + * If it is in HW/SW Radio OFF or IPS state, + * we do not check Fw LPS Leave, + * because Fw is unload. + */ + *val = _TRUE; + } else { + u32 rcr = 0; + + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr); + if (rcr & (RCR_UC_MD_EN | RCR_BC_MD_EN | RCR_TIM_PARSER_EN)) + *val = _FALSE; + else + *val = _TRUE; + } + break; + + case HW_VAR_HCI_SUS_STATE: + *((u8 *)val) = hal_data->hci_sus_state; + break; + + case HW_VAR_BCN_CTRL_ADDR: + *((u32 *)val) = hw_bcn_ctrl_addr(adapter, adapter->hw_port); + break; + default: if (0) RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n", @@ -9001,6 +11820,27 @@ void GetHwReg(_adapter *adapter, u8 variable, u8 *val) } +static u32 _get_page_size(struct _ADAPTER *a) +{ +#ifdef RTW_HALMAC + struct dvobj_priv *d; + u32 size = 0; + int err = 0; + + + d = adapter_to_dvobj(a); + + err = rtw_halmac_get_page_size(d, &size); + if (!err) + return size; + + RTW_WARN(FUNC_ADPT_FMT ": Fail to get Page size!!(err=%d)\n", + FUNC_ADPT_ARG(a), err); +#endif /* RTW_HALMAC */ + + return PAGE_SIZE_128; +} + u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) { @@ -9018,9 +11858,6 @@ SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) case HAL_DEF_ANT_DETECT: hal_data->AntDetection = *((u8 *)value); break; - case HAL_DEF_DBG_DIS_PWT: - hal_data->bDisableTXPowerTraining = *((u8 *)value); - break; default: RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable); bResult = _FAIL; @@ -9075,6 +11912,35 @@ u8 rtw_hal_query_txbfee_rf_num(_adapter *adapter) return 1; } +#ifdef RTW_BEAMFORMING_VERSION_2 +void rtw_hal_beamforming_config_csirate(PADAPTER adapter) +{ + struct dm_struct *p_dm_odm; + struct beamforming_info *bf_info; + u8 fix_rate_enable = 0; + u8 new_csi_rate_idx; + + /* Acting as BFee */ + if (IS_BEAMFORMEE(adapter)) { + #if 0 + /* Do not enable now because it will affect MU performance and CTS/BA rate. 2016.07.19. by tynli. [PCIE-1660] */ + if (IS_HARDWARE_TYPE_8821C(Adapter)) + FixRateEnable = 1; /* Support after 8821C */ + #endif + + p_dm_odm = adapter_to_phydm(adapter); + bf_info = GET_BEAMFORM_INFO(adapter); + + rtw_halmac_bf_cfg_csi_rate(adapter_to_dvobj(adapter), + p_dm_odm->rssi_min, + bf_info->cur_csi_rpt_rate, + fix_rate_enable, &new_csi_rate_idx); + + if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate) + bf_info->cur_csi_rpt_rate = new_csi_rate_idx; + } +} +#endif #endif u8 @@ -9093,7 +11959,7 @@ GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) pstapriv = &adapter->stapriv; psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress); if (psta) - *((int *)value) = psta->rssi_stat.undecorated_smoothed_pwdb; + *((int *)value) = psta->cmn.rssi_stat.rssi; } break; case HAL_DEF_DBG_DUMP_RXPKT: @@ -9105,14 +11971,8 @@ GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) case HAL_DEF_ANT_DETECT: *((u8 *)value) = hal_data->AntDetection; break; - case HAL_DEF_MACID_SLEEP: - *(u8 *)value = _FALSE; - break; case HAL_DEF_TX_PAGE_SIZE: - *((u32 *)value) = PAGE_SIZE_128; - break; - case HAL_DEF_DBG_DIS_PWT: - *(u8 *)value = hal_data->bDisableTXPowerTraining; + *((u32 *)value) = _get_page_size(adapter); break; case HAL_DEF_EXPLICIT_BEAMFORMER: case HAL_DEF_EXPLICIT_BEAMFORMEE: @@ -9137,259 +11997,6 @@ GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) return bResult; } -void SetHalODMVar( - PADAPTER Adapter, - HAL_ODM_VARIABLE eVariable, - PVOID pValue1, - BOOLEAN bSet) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; - /* _irqL irqL; */ - switch (eVariable) { - case HAL_ODM_STA_INFO: { - struct sta_info *psta = (struct sta_info *)pValue1; - if (bSet) { - RTW_INFO("### Set STA_(%d) info ###\n", psta->mac_id); - odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta); - } else { - RTW_INFO("### Clean STA_(%d) info ###\n", psta->mac_id); - /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ - psta->rssi_level = 0; - odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL); - - /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ - } - } - break; - case HAL_ODM_P2P_STATE: - odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet); - break; - case HAL_ODM_WIFI_DISPLAY_STATE: - odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet); - break; - case HAL_ODM_REGULATION: - odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, pHalData->Regulation2_4G); - odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, pHalData->Regulation5G); - break; -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - case HAL_ODM_NOISE_MONITOR: { - struct noise_info *pinfo = (struct noise_info *)pValue1; - -#ifdef DBG_NOISE_MONITOR - RTW_INFO("### Noise monitor chan(%d)-bPauseDIG:%d,IGIValue:0x%02x,max_time:%d (ms) ###\n", - pinfo->chan, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time); -#endif - - pHalData->noise[pinfo->chan] = odm_inband_noise_monitor(podmpriv, pinfo->is_pause_dig, pinfo->igi_value, pinfo->max_time); - RTW_INFO("chan_%d, noise = %d (dBm)\n", pinfo->chan, pHalData->noise[pinfo->chan]); -#ifdef DBG_NOISE_MONITOR - RTW_INFO("noise_a = %d, noise_b = %d noise_all:%d\n", - podmpriv->noise_level.noise[ODM_RF_PATH_A], - podmpriv->noise_level.noise[ODM_RF_PATH_B], - podmpriv->noise_level.noise_all); -#endif - } - break; -#endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/ - - case HAL_ODM_INITIAL_GAIN: { - u8 rx_gain = *((u8 *)(pValue1)); - /*printk("rx_gain:%x\n",rx_gain);*/ - if (rx_gain == 0xff) {/*restore rx gain*/ - /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/ - odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain); - } else { - /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/ - /*odm_write_dig(podmpriv,rx_gain);*/ - odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain); - } - } - break; - case HAL_ODM_FA_CNT_DUMP: - if (*((u8 *)pValue1)) - podmpriv->debug_components |= (ODM_COMP_DIG | ODM_COMP_FA_CNT); - else - podmpriv->debug_components &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT); - break; - case HAL_ODM_DBG_FLAG: - odm_cmn_info_update(podmpriv, ODM_CMNINFO_DBG_COMP, *((u8Byte *)pValue1)); - break; - case HAL_ODM_DBG_LEVEL: - odm_cmn_info_update(podmpriv, ODM_CMNINFO_DBG_LEVEL, *((u4Byte *)pValue1)); - break; - case HAL_ODM_RX_INFO_DUMP: { - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(podmpriv , PHYDM_FALSEALMCNT); - struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &podmpriv->dm_dig_table; - void *sel; - - sel = pValue1; - - _RTW_PRINT_SEL(sel , "============ Rx Info dump ===================\n"); - _RTW_PRINT_SEL(sel , "is_linked = %d, rssi_min = %d(%%), current_igi = 0x%x\n", podmpriv->is_linked, podmpriv->rssi_min, pDM_DigTable->cur_ig_value); - _RTW_PRINT_SEL(sel , "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n", false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all); - - if (podmpriv->is_linked) { - _RTW_PRINT_SEL(sel , "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate)); - _RTW_PRINT_SEL(sel , " RSSI_A = %d(%%), RSSI_B = %d(%%)\n", podmpriv->RSSI_A, podmpriv->RSSI_B); -#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA - rtw_dump_raw_rssi_info(Adapter, sel); -#endif - } - } - break; - case HAL_ODM_RX_Dframe_INFO: { - void *sel; - - sel = pValue1; - - /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/ -#ifdef DBG_RX_DFRAME_RAW_DATA - rtw_dump_rx_dframe_info(Adapter, sel); -#endif - } - break; - -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - case HAL_ODM_AUTO_CHNL_SEL: { - ACS_OP acs_op = *(ACS_OP *)pValue1; - - rtw_phydm_func_set(Adapter, ODM_BB_NHM_CNT); - - if (ACS_INIT == acs_op) { -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_INIT\n", ADPT_ARG(Adapter)); -#endif - odm_AutoChannelSelectInit(podmpriv); - } else if (ACS_RESET == acs_op) { - /* Reset statistics for auto channel selection mechanism.*/ -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_RESET\n", ADPT_ARG(Adapter)); -#endif - odm_auto_channel_select_reset(podmpriv); - - } else if (ACS_SELECT == acs_op) { - /* Collect NHM measurement result after current channel */ -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_SELECT, CH(%d)\n", ADPT_ARG(Adapter), rtw_get_acs_channel(Adapter)); -#endif - odm_AutoChannelSelect(podmpriv, rtw_get_acs_channel(Adapter)); - } else - RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: Unexpected OP\n", ADPT_ARG(Adapter)); - - } - break; -#endif -#ifdef CONFIG_ANTENNA_DIVERSITY - case HAL_ODM_ANTDIV_SELECT: { - u8 antenna = (*(u8 *)pValue1); - - /*switch antenna*/ - odm_update_rx_idle_ant(&pHalData->odmpriv, antenna); - /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/ - - } - break; -#endif - - default: - break; - } -} - -void GetHalODMVar( - PADAPTER Adapter, - HAL_ODM_VARIABLE eVariable, - PVOID pValue1, - PVOID pValue2) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; - - switch (eVariable) { -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - case HAL_ODM_NOISE_MONITOR: { - u8 chan = *(u8 *)pValue1; - *(s16 *)pValue2 = pHalData->noise[chan]; -#ifdef DBG_NOISE_MONITOR - RTW_INFO("### Noise monitor chan(%d)-noise:%d (dBm) ###\n", - chan, pHalData->noise[chan]); -#endif - } - break; -#endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/ - case HAL_ODM_DBG_FLAG: - *((u8Byte *)pValue1) = podmpriv->debug_components; - break; - case HAL_ODM_DBG_LEVEL: - *((u4Byte *)pValue1) = podmpriv->debug_level; - break; - -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - case HAL_ODM_AUTO_CHNL_SEL: { -#ifdef DBG_AUTO_CHNL_SEL_NHM - RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: GET_BEST_CHAN\n", ADPT_ARG(Adapter)); -#endif - /* Retrieve better channel from NHM mechanism */ - if (IsSupported24G(Adapter->registrypriv.wireless_mode)) - *((u8 *)(pValue1)) = odm_get_auto_channel_select_result(podmpriv, BAND_ON_2_4G); - if (is_supported_5g(Adapter->registrypriv.wireless_mode)) - *((u8 *)(pValue2)) = odm_get_auto_channel_select_result(podmpriv, BAND_ON_5G); - } - break; -#endif -#ifdef CONFIG_ANTENNA_DIVERSITY - case HAL_ODM_ANTDIV_SELECT: { - struct _FAST_ANTENNA_TRAINNING_ *pDM_FatTable = &podmpriv->dm_fat_table; - *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant; - } - break; -#endif - case HAL_ODM_INITIAL_GAIN: { - struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &podmpriv->dm_dig_table; - *((u8 *)pValue1) = pDM_DigTable->cur_ig_value; - } - break; - default: - break; - } -} - - -u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; - u32 result = 0; - - switch (ops) { - case HAL_PHYDM_DIS_ALL_FUNC: - podmpriv->support_ability = DYNAMIC_FUNC_DISABLE; - break; - case HAL_PHYDM_FUNC_SET: - podmpriv->support_ability |= ability; - break; - case HAL_PHYDM_FUNC_CLR: - podmpriv->support_ability &= ~(ability); - break; - case HAL_PHYDM_ABILITY_BK: - /* dm flag backup*/ - podmpriv->bk_support_ability = podmpriv->support_ability; - break; - case HAL_PHYDM_ABILITY_RESTORE: - /* restore dm flag */ - podmpriv->support_ability = podmpriv->bk_support_ability; - break; - case HAL_PHYDM_ABILITY_SET: - podmpriv->support_ability = ability; - break; - case HAL_PHYDM_ABILITY_GET: - result = podmpriv->support_ability; - break; - } - return result; -} - BOOLEAN eqNByte( @@ -9503,6 +12110,9 @@ GetFractionValueFromString( ++(*pu4bMove); } + if (*szScan < '0' || *szScan > '9') + return _FALSE; + /* Parse each digit. */ do { (*pInteger) *= 10; @@ -9517,12 +12127,17 @@ GetFractionValueFromString( if (*szScan < '0' || *szScan > '9') return _FALSE; - else { - *pFraction = *szScan - '0'; + + *pFraction += (*szScan - '0') * 10; + ++szScan; + ++(*pu4bMove); + + if (*szScan >= '0' && *szScan <= '9') { + *pFraction += *szScan - '0'; ++szScan; ++(*pu4bMove); - return _TRUE; } + return _TRUE; } } while (*szScan >= '0' && *szScan <= '9'); @@ -9584,8 +12199,13 @@ ParseQualifiedString( return _FALSE; i = (*Start); - while ((c = In[(*Start)++]) != RightQualifier) - ; /* find ']' */ + c = In[(*Start)++]; + while (c != RightQualifier && c != '\0') + c = In[(*Start)++]; + + if (c == '\0') + return _FALSE; + j = (*Start) - 2; strncpy((char *)Out, (const char *)(In + i), j - i + 1); @@ -9623,12 +12243,14 @@ void rtw_hal_check_rxfifo_full(_adapter *adapter) /* switch counter to RX fifo */ if (IS_8188E(pHalData->version_id) || IS_8188F(pHalData->version_id) || + IS_8188GTV(pHalData->version_id) || IS_8812_SERIES(pHalData->version_id) || IS_8821_SERIES(pHalData->version_id) || IS_8723B_SERIES(pHalData->version_id) || IS_8192E(pHalData->version_id) || IS_8703B_SERIES(pHalData->version_id) || - IS_8723D_SERIES(pHalData->version_id)) { + IS_8723D_SERIES(pHalData->version_id) || + IS_8192F_SERIES(pHalData->version_id)) { rtw_write8(adapter, REG_RXERR_RPT + 3, rtw_read8(adapter, REG_RXERR_RPT + 3) | 0xa0); save_cnt = _TRUE; } else { @@ -9733,6 +12355,10 @@ void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel) #ifdef DBG_RX_DFRAME_RAW_DATA void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel) { +#define DBG_RX_DFRAME_RAW_DATA_UC 0 +#define DBG_RX_DFRAME_RAW_DATA_BMC 1 +#define DBG_RX_DFRAME_RAW_DATA_TYPES 2 + _irqL irqL; u8 isCCKrate, rf_path; struct recv_priv *precvpriv = &(padapter->recvpriv); @@ -9740,11 +12366,10 @@ void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel) struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *psta; struct sta_recv_dframe_info *psta_dframe_info; - int i; + int i, j; _list *plist, *phead; - char *BW; - u8 bc_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - u8 null_addr[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; if (precvpriv->store_law_data_flag) { @@ -9760,53 +12385,38 @@ void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel) plist = get_next(plist); if (psta) { - psta_dframe_info = &psta->sta_dframe_info; - if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), 6) != _TRUE)) { - - - isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE; - - switch (psta_dframe_info->sta_bw_mode) { - - case CHANNEL_WIDTH_20: - BW = "20M"; - break; - - case CHANNEL_WIDTH_40: - BW = "40M"; - break; - - case CHANNEL_WIDTH_80: - BW = "80M"; - break; - - case CHANNEL_WIDTH_160: - BW = "160M"; - break; - - default: - BW = ""; - break; - } + if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN) != _TRUE)) { RTW_PRINT_SEL(sel, "==============================\n"); - _RTW_PRINT_SEL(sel, "macaddr =" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); - _RTW_PRINT_SEL(sel, "BW=%s, sgi =%d\n", BW, psta_dframe_info->sta_sgi); - _RTW_PRINT_SEL(sel, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate)); - - for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) { - - if (!isCCKrate) { - - _RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]); - _RTW_PRINT_SEL(sel , ",rx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]); - - } else - - _RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100); + RTW_PRINT_SEL(sel, "macaddr =" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); + + for (j = 0; j < DBG_RX_DFRAME_RAW_DATA_TYPES; j++) { + if (j == DBG_RX_DFRAME_RAW_DATA_UC) { + psta_dframe_info = &psta->sta_dframe_info; + RTW_PRINT_SEL(sel, "\n"); + RTW_PRINT_SEL(sel, "Unicast:\n"); + } else if (j == DBG_RX_DFRAME_RAW_DATA_BMC) { + psta_dframe_info = &psta->sta_dframe_info_bmc; + RTW_PRINT_SEL(sel, "\n"); + RTW_PRINT_SEL(sel, "Broadcast/Multicast:\n"); + } + + isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE; + + RTW_PRINT_SEL(sel, "BW=%s, sgi =%d\n", ch_width_str(psta_dframe_info->sta_bw_mode), psta_dframe_info->sta_sgi); + RTW_PRINT_SEL(sel, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate)); + + for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) { + if (!isCCKrate) { + RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]); + _RTW_PRINT_SEL(sel , ",rx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]); + } else + RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100); + } } + } } } @@ -9827,7 +12437,7 @@ void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; struct sta_info *psta = prframe->u.hdr.psta; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)(&pattrib->phy_info); + struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info; struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info; psample_pkt_rssi->data_rate = pattrib->data_rate; ptr = prframe->u.hdr.rx_data; @@ -9854,9 +12464,13 @@ void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe) /*RTW_INFO("=>%s WIFI_DATA_TYPE or WIFI_QOS_DATA_TYPE\n", __FUNCTION__);*/ if (psta) { - psta_dframe_info = &psta->sta_dframe_info; - /*RTW_INFO("=>%s psta->hwaddr="MAC_FMT" !\n", __FUNCTION__, MAC_ARG(psta->hwaddr));*/ - if ((_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN) != _TRUE) || (padapter->registrypriv.mp_mode == 1)) { + if (IS_MCAST(get_ra(get_recvframe_data(prframe)))) + psta_dframe_info = &psta->sta_dframe_info_bmc; + else + psta_dframe_info = &psta->sta_dframe_info; + /*RTW_INFO("=>%s psta->cmn.mac_addr="MAC_FMT" !\n", + __FUNCTION__, MAC_ARG(psta->cmn.mac_addr));*/ + if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) || (padapter->registrypriv.mp_mode == 1)) { psta_dframe_info->sta_data_rate = pattrib->data_rate; psta_dframe_info->sta_sgi = pattrib->sgi; psta_dframe_info->sta_bw_mode = pattrib->bw; @@ -9877,61 +12491,6 @@ void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe) } - -int check_phy_efuse_tx_power_info_valid(PADAPTER padapter) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - u8 *pContent = pHalData->efuse_eeprom_data; - int index = 0; - u16 tx_index_offset = 0x0000; - - switch (rtw_get_chip_type(padapter)) { - case RTL8723B: - tx_index_offset = EEPROM_TX_PWR_INX_8723B; - break; - case RTL8703B: - tx_index_offset = EEPROM_TX_PWR_INX_8703B; - break; - case RTL8723D: - tx_index_offset = EEPROM_TX_PWR_INX_8723D; - break; - case RTL8188E: - tx_index_offset = EEPROM_TX_PWR_INX_88E; - break; - case RTL8188F: - tx_index_offset = EEPROM_TX_PWR_INX_8188F; - break; - case RTL8192E: - tx_index_offset = EEPROM_TX_PWR_INX_8192E; - break; - case RTL8821: - tx_index_offset = EEPROM_TX_PWR_INX_8821; - break; - case RTL8812: - tx_index_offset = EEPROM_TX_PWR_INX_8812; - break; - case RTL8814A: - tx_index_offset = EEPROM_TX_PWR_INX_8814; - break; - case RTL8822B: - tx_index_offset = EEPROM_TX_PWR_INX_8822B; - break; - case RTL8821C: - tx_index_offset = EEPROM_TX_PWR_INX_8821C; - break; - default: - tx_index_offset = 0x0010; - break; - } - - /* TODO: chacking length by ICs */ - for (index = 0 ; index < 11 ; index++) { - if (pContent[tx_index_offset + index] == 0xFF) - return _FALSE; - } - return _TRUE; -} - int hal_efuse_macaddr_offset(_adapter *adapter) { u8 interface_type = 0; @@ -9987,6 +12546,14 @@ int hal_efuse_macaddr_offset(_adapter *adapter) addr_offset = EEPROM_MAC_ADDR_8188FS; break; #endif +#ifdef CONFIG_RTL8188GTV + case RTL8188GTV: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_8188GTVU; + else if (interface_type == RTW_SDIO) + addr_offset = EEPROM_MAC_ADDR_8188GTVS; + break; +#endif #ifdef CONFIG_RTL8812A case RTL8812: if (interface_type == RTW_USB) @@ -10045,6 +12612,25 @@ int hal_efuse_macaddr_offset(_adapter *adapter) addr_offset = EEPROM_MAC_ADDR_8821CE; break; #endif /* CONFIG_RTL8821C */ + +#ifdef CONFIG_RTL8710B + case RTL8710B: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_8710B; + break; +#endif + +#ifdef CONFIG_RTL8192F + case RTL8192F: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_8192FU; + else if (interface_type == RTW_SDIO) + addr_offset = EEPROM_MAC_ADDR_8192FS; + else if (interface_type == RTW_PCIE) + addr_offset = EEPROM_MAC_ADDR_8192FE; + break; +#endif /* CONFIG_RTL8192F */ + } if (addr_offset == -1) { @@ -10083,22 +12669,11 @@ void rtw_dump_cur_efuse(PADAPTER padapter) return; } +#ifdef CONFIG_RTW_DEBUG if (hal_data->efuse_file_status == EFUSE_FILE_LOADED) - RTW_INFO("EFUSE FILE\n"); + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "EFUSE FILE", hal_data->efuse_eeprom_data, mapsize); else - RTW_INFO("HW EFUSE\n"); - -#ifdef CONFIG_RTW_DEBUG - for (i = 0; i < mapsize; i++) { - if (i % 16 == 0) - RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i); - - _RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s" - , hal_data->efuse_eeprom_data[i] - , ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ") - ); - } - _RTW_PRINT_SEL(RTW_DBGDUMP, "\n"); + RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "HW EFUSE", hal_data->efuse_eeprom_data, mapsize); #endif } @@ -10151,6 +12726,9 @@ int hal_config_macaddr(_adapter *adapter, bool autoload_fail) int addr_offset = hal_efuse_macaddr_offset(adapter); u8 *hw_addr = NULL; int ret = _SUCCESS; +#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI) + u8 ft_mac_addr[ETH_ALEN] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff}; /* FT USB2 for 8822B */ +#endif if (autoload_fail) goto bypass_hw_pg; @@ -10170,6 +12748,11 @@ int hal_config_macaddr(_adapter *adapter, bool autoload_fail) hw_addr = addr; } +#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI) + if (_rtw_memcmp(hw_addr, ft_mac_addr, ETH_ALEN)) + hw_addr[0] = 0xff; +#endif + /* check hw pg data */ if (hw_addr && rtw_check_invalid_mac_address(hw_addr, _TRUE) == _FALSE) { _rtw_memcpy(hal_data->EEPROMMACAddr, hw_addr, ETH_ALEN); @@ -10225,18 +12808,18 @@ void rtw_bb_rf_gain_offset(_adapter *padapter) } #if defined(CONFIG_RTL8723B) - if (value & BIT4 || (registry_par->RegPwrTrimEnable == 1)) { + if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) { RTW_INFO("Offset RF Gain.\n"); RTW_INFO("Offset RF Gain. pHalData->EEPROMRFGainVal=0x%x\n", pHalData->EEPROMRFGainVal); if (pHalData->EEPROMRFGainVal != 0xff) { - if (pHalData->ant_path == ODM_RF_PATH_A) + if (pHalData->ant_path == RF_PATH_A) GainValue = (pHalData->EEPROMRFGainVal & 0x0f); else GainValue = (pHalData->EEPROMRFGainVal & 0xf0) >> 4; - RTW_INFO("Ant PATH_%d GainValue Offset = 0x%x\n", (pHalData->ant_path == ODM_RF_PATH_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B), GainValue); + RTW_INFO("Ant PATH_%d GainValue Offset = 0x%x\n", (pHalData->ant_path == RF_PATH_A) ? (RF_PATH_A) : (RF_PATH_B), GainValue); for (i = 0; i < ArrayLen; i += 2) { /* RTW_INFO("ArrayLen in =%d ,Array 1 =0x%x ,Array2 =0x%x\n",i,Array[i],Array[i]+1); */ @@ -10264,7 +12847,7 @@ void rtw_bb_rf_gain_offset(_adapter *padapter) RTW_INFO("Using the default RF gain.\n"); #elif defined(CONFIG_RTL8188E) - if (value & BIT4 || (registry_par->RegPwrTrimEnable == 1)) { + if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) { RTW_INFO("8188ES Offset RF Gain.\n"); RTW_INFO("8188ES Offset RF Gain. EEPROMRFGainVal=0x%x\n", pHalData->EEPROMRFGainVal); @@ -10481,7 +13064,7 @@ inline u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qse struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); u8 chk_rst = _SUCCESS; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) return chk_rst; /* if((pre_qsel == 0xFF)||(next_qsel== 0xFF)) */ @@ -10546,7 +13129,9 @@ u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num) { u8 value = 0; u8 direction = 0; - u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2; + u32 gpio_pin_input_val = REG_GPIO_PIN_CTRL; + u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1; + u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2; u8 gpio_num_to_set = gpio_num; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); @@ -10559,18 +13144,20 @@ u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num) LeaveAllPowerSaveModeDirect(adapter); if (gpio_num > 7) { - gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2; + gpio_pin_input_val = REG_GPIO_PIN_CTRL_2; + gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1; + gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2; gpio_num_to_set = gpio_num - 8; } /* Read GPIO Direction */ - direction = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num; + direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set; /* According the direction to read register value */ if (direction) - value = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num; + value = (rtw_read8(adapter, gpio_pin_output_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set; else - value = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num; + value = (rtw_read8(adapter, gpio_pin_input_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set; rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); RTW_INFO("%s direction=%d value=%d\n", __FUNCTION__, direction, value); @@ -10582,7 +13169,8 @@ int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh) { u8 direction = 0; u8 res = -1; - u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2; + u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1; + u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2; u8 gpio_num_to_set = gpio_num; if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL) @@ -10593,19 +13181,20 @@ int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh) LeaveAllPowerSaveModeDirect(adapter); if (gpio_num > 7) { - gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2; + gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1; + gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2; gpio_num_to_set = gpio_num - 8; } /* Read GPIO direction */ - direction = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num; + direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set; /* If GPIO is output direction, setting value. */ if (direction) { if (isHigh) - rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) | BIT(gpio_num_to_set)); + rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) | BIT(gpio_num_to_set)); else - rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) & ~BIT(gpio_num_to_set)); + rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) & ~BIT(gpio_num_to_set)); RTW_INFO("%s Set gpio %x[%d]=%d\n", __FUNCTION__, REG_GPIO_PIN_CTRL + 1, gpio_num, isHigh); res = 0; @@ -10847,8 +13436,10 @@ void rtw_reset_mac_rx_counters(_adapter *padapter) /* If no packet rx, MaxRx clock be gating ,BIT_DISGCLK bit19 set 1 for fix*/ if (IS_HARDWARE_TYPE_8703B(padapter) || - IS_HARDWARE_TYPE_8723D(padapter) || - IS_HARDWARE_TYPE_8188F(padapter)) + IS_HARDWARE_TYPE_8723D(padapter) || + IS_HARDWARE_TYPE_8188F(padapter) || + IS_HARDWARE_TYPE_8188GTV(padapter) || + IS_HARDWARE_TYPE_8192F(padapter)) phy_set_mac_reg(padapter, REG_RCR, BIT19, 0x1); /* reset mac counter */ @@ -11002,61 +13593,54 @@ void rtw_dump_rx_counters(_adapter *padapter) } } #endif -void rtw_get_noise(_adapter *padapter) -{ -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct noise_info info; - if (rtw_linked_check(padapter)) { - info.bPauseDIG = _TRUE; - info.IGIValue = 0x1e; - info.max_time = 100;/* ms */ - info.chan = pmlmeext->cur_channel ;/* rtw_get_oper_ch(padapter); */ - rtw_ps_deny(padapter, PS_DENY_IOCTL); - LeaveAllPowerSaveModeDirect(padapter); - - rtw_hal_set_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &info, _FALSE); - /* odm_inband_noise_monitor(podmpriv,_TRUE,0x20,100); */ - rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); - rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(info.chan), &(padapter->recvpriv.noise)); -#ifdef DBG_NOISE_MONITOR - RTW_INFO("chan:%d,noise_level:%d\n", info.chan, padapter->recvpriv.noise); -#endif - } -#endif - -} -u8 rtw_get_current_tx_sgi(_adapter *padapter, u8 macid) +u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct _rate_adaptive_table_ *pRA_Table = &pDM_Odm->dm_ra_table; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); u8 curr_tx_sgi = 0; + struct ra_sta_info *ra_info; + if (!psta) + return curr_tx_sgi; + + if (padapter->fix_rate == 0xff) { #if defined(CONFIG_RTL8188E) - curr_tx_sgi = odm_ra_get_decision_rate_8188e(pDM_Odm, macid); +#if (RATE_ADAPTIVE_SUPPORT == 1) + curr_tx_sgi = hal_data->odmpriv.ra_info[psta->cmn.mac_id].rate_sgi; +#endif /* (RATE_ADAPTIVE_SUPPORT == 1)*/ #else - curr_tx_sgi = ((pRA_Table->link_tx_rate[macid]) & 0x80) >> 7; + ra_info = &psta->cmn.ra_info; + curr_tx_sgi = ((ra_info->curr_tx_rate) & 0x80) >> 7; #endif + } else { + curr_tx_sgi = ((padapter->fix_rate) & 0x80) >> 7; + } return curr_tx_sgi; - } -u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid) + +u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct _rate_adaptive_table_ *pRA_Table = &pDM_Odm->dm_ra_table; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); u8 rate_id = 0; + struct ra_sta_info *ra_info; + if (!psta) + return rate_id; + + if (padapter->fix_rate == 0xff) { +#if defined(CONFIG_RTL8188E) #if (RATE_ADAPTIVE_SUPPORT == 1) - rate_id = odm_ra_get_decision_rate_8188e(pDM_Odm, macid); + rate_id = hal_data->odmpriv.ra_info[psta->cmn.mac_id].decision_rate; +#endif /* (RATE_ADAPTIVE_SUPPORT == 1)*/ #else - rate_id = (pRA_Table->link_tx_rate[macid]) & 0x7f; + ra_info = &psta->cmn.ra_info; + rate_id = ra_info->curr_tx_rate & 0x7f; #endif + } else { + rate_id = padapter->fix_rate & 0x7f; + } return rate_id; - } void update_IOT_info(_adapter *padapter) @@ -11073,14 +13657,10 @@ void update_IOT_info(_adapter *padapter) case HT_IOT_PEER_RALINK: pmlmeinfo->turboMode_cts2self = 0; pmlmeinfo->turboMode_rtsen = 1; - /* disable high power */ - rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR); break; case HT_IOT_PEER_REALTEK: /* rtw_write16(padapter, 0x4cc, 0xffff); */ /* rtw_write16(padapter, 0x546, 0x01c0); */ - /* disable high power */ - rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR); break; default: pmlmeinfo->turboMode_cts2self = 0; @@ -11089,30 +13669,6 @@ void update_IOT_info(_adapter *padapter) } } -#ifdef CONFIG_AUTO_CHNL_SEL_NHM -void rtw_acs_start(_adapter *padapter, bool bStart) -{ - if (_TRUE == bStart) { - ACS_OP acs_op = ACS_INIT; - - rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE); - rtw_set_acs_channel(padapter, 0); - SET_ACS_STATE(padapter, ACS_ENABLE); - } else { - SET_ACS_STATE(padapter, ACS_DISABLE); -#ifdef DBG_AUTO_CHNL_SEL_NHM - if (1) { - u8 best_24g_ch = 0; - u8 best_5g_ch = 0; - - rtw_hal_get_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &(best_24g_ch), &(best_5g_ch)); - RTW_INFO("[ACS-"ADPT_FMT"] Best 2.4G CH:%u\n", ADPT_ARG(padapter), best_24g_ch); - RTW_INFO("[ACS-"ADPT_FMT"] Best 5G CH:%u\n", ADPT_ARG(padapter), best_5g_ch); - } -#endif - } -} -#endif /* TODO: merge with phydm, see odm_SetCrystalCap() */ void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap) @@ -11120,9 +13676,10 @@ void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap) crystal_cap = crystal_cap & 0x3F; switch (rtw_get_chip_type(adapter)) { -#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) +#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) case RTL8188E: case RTL8188F: + case RTL8188GTV: /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */ phy_set_bb_reg(adapter, REG_AFE_XTAL_CTRL, 0x007FF800, (crystal_cap | (crystal_cap << 6))); break; @@ -11135,7 +13692,7 @@ void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap) #endif #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \ defined(CONFIG_RTL8723D) || defined(CONFIG_RTL8821A) || \ - defined(CONFIG_RTL8192E) + defined(CONFIG_RTL8192E) case RTL8723B: case RTL8703B: case RTL8723D: @@ -11151,15 +13708,24 @@ void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap) phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6))); break; #endif -#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) +#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8192F) case RTL8822B: case RTL8821C: + case RTL8192F: /* write 0x28[6:1] = 0x24[30:25] = CrystalCap */ crystal_cap = crystal_cap & 0x3F; phy_set_bb_reg(adapter, REG_AFE_XTAL_CTRL, 0x7E000000, crystal_cap); phy_set_bb_reg(adapter, REG_AFE_PLL_CTRL, 0x7E, crystal_cap); break; +#endif +#if defined(CONFIG_RTL8710B) + case RTL8710B: + /*Change by ylb 20160728, Becase 0x2C[23:12] is removed to syson 0x60[29:18] */ + /* 0x2C[23:18] = 0x2C[29:24] = CrystalCap //Xo:[29:24], Xi:[23:18]*/ + crystal_cap = crystal_cap & 0x3F; + hal_set_syson_reg(adapter, REG_SYS_XTAL_CTRL0, 0x3FFC0000, (crystal_cap | (crystal_cap << 6))); + break; #endif default: rtw_warn_on(1); @@ -11199,6 +13765,11 @@ int hal_spec_init(_adapter *adapter) init_hal_spec_8188f(adapter); break; #endif +#ifdef CONFIG_RTL8188GTV + case RTL8188GTV: + init_hal_spec_8188gtv(adapter); + break; +#endif #ifdef CONFIG_RTL8812A case RTL8812: init_hal_spec_8812a(adapter); @@ -11229,6 +13800,17 @@ int hal_spec_init(_adapter *adapter) init_hal_spec_rtl8821c(adapter); break; #endif +#ifdef CONFIG_RTL8710B + case RTL8710B: + init_hal_spec_8710b(adapter); + break; +#endif +#ifdef CONFIG_RTL8192F + case RTL8192F: + init_hal_spec_8192f(adapter); + break; +#endif + default: RTW_ERR("%s: unknown chip_type:%u\n" , __func__, rtw_get_chip_type(adapter)); @@ -11278,6 +13860,8 @@ void dump_hal_spec(void *sel, _adapter *adapter) RTW_PRINT_SEL(sel, "sec_cam_ent_num:%u\n", hal_spec->sec_cam_ent_num); RTW_PRINT_SEL(sel, "rfpath_num_2g:%u\n", hal_spec->rfpath_num_2g); RTW_PRINT_SEL(sel, "rfpath_num_5g:%u\n", hal_spec->rfpath_num_5g); + RTW_PRINT_SEL(sel, "txgi_max:%u\n", hal_spec->txgi_max); + RTW_PRINT_SEL(sel, "txgi_pdbm:%u\n", hal_spec->txgi_pdbm); RTW_PRINT_SEL(sel, "max_tx_cnt:%u\n", hal_spec->max_tx_cnt); RTW_PRINT_SEL(sel, "tx_nss_num:%u\n", hal_spec->tx_nss_num); RTW_PRINT_SEL(sel, "rx_nss_num:%u\n", hal_spec->rx_nss_num); @@ -11309,6 +13893,11 @@ void dump_hal_spec(void *sel, _adapter *adapter) _RTW_PRINT_SEL(sel, "%s ", _wl_func_str[i]); } _RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "rx_tsf_filter:%u\n", hal_spec->rx_tsf_filter); + + RTW_PRINT_SEL(sel, "pg_txpwr_saddr:0x%X\n", hal_spec->pg_txpwr_saddr); + RTW_PRINT_SEL(sel, "pg_txgi_diff_factor:%u\n", hal_spec->pg_txgi_diff_factor); } inline bool hal_chk_band_cap(_adapter *adapter, u8 cap) @@ -11375,9 +13964,9 @@ inline bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode) /* * hal_largest_bw - starting from in_bw, get largest bw supported by HAL * @adapter: -* @in_bw: starting bw, value of CHANNEL_WIDTH +* @in_bw: starting bw, value of enum channel_width * -* Returns: value of CHANNEL_WIDTH +* Returns: value of enum channel_width */ u8 hal_largest_bw(_adapter *adapter, u8 in_bw) { @@ -11392,115 +13981,168 @@ u8 hal_largest_bw(_adapter *adapter, u8 in_bw) return in_bw; } -void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf) +void ResumeTxBeacon(_adapter *padapter) { - if (hw_port == HW_PORT0) { - /*disable related TSF function*/ - rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) & (~EN_BCN_FUNCTION)); - - rtw_write32(padapter, REG_TSFTR, tsf); - rtw_write32(padapter, REG_TSFTR + 4, tsf >> 32); - - /*enable related TSF function*/ - rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | EN_BCN_FUNCTION); - } else if (hw_port == HW_PORT1) { - /*disable related TSF function*/ - rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) & (~EN_BCN_FUNCTION)); + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, + rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) | BIT(6)); - rtw_write32(padapter, REG_TSFTR1, tsf); - rtw_write32(padapter, REG_TSFTR1 + 4, tsf >> 32); +#ifdef RTW_HALMAC + /* Add this for driver using HALMAC because driver doesn't have setup time init by self */ + /* TBTT setup time */ + rtw_write8(padapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME); +#endif - /*enable related TSF function*/ - rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) | EN_BCN_FUNCTION); - } else - RTW_INFO("%s-[WARN] "ADPT_FMT" invalid hw_port:%d\n", __func__, ADPT_ARG(padapter), hw_port); + /* TBTT hold time: 0x540[19:8] */ + rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, + (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8)); } -void ResumeTxBeacon(_adapter *padapter) +void StopTxBeacon(_adapter *padapter) { - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, + rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) & (~BIT6)); + /* TBTT hold time: 0x540[19:8] */ + rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, + (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8)); +} - /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ - /* which should be read from register to a global variable. */ +#ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/ +#ifdef CONFIG_CLIENT_PORT_CFG +const u8 _clt_port_id[MAX_CLIENT_PORT_NUM] = { + CLT_PORT0, + CLT_PORT1, + CLT_PORT2, + CLT_PORT3 +}; - pHalData->RegFwHwTxQCtrl |= BIT(6); - rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl); - rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff); - pHalData->RegReg542 |= BIT(0); - rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542); +void rtw_clt_port_init(struct clt_port_t *cltp) +{ + cltp->bmp = 0; + cltp->num = 0; + _rtw_spinlock_init(&cltp->lock); +} +void rtw_clt_port_deinit(struct clt_port_t *cltp) +{ + _rtw_spinlock_free(&cltp->lock); } +static void _hw_client_port_alloc(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct clt_port_t *cltp = &dvobj->clt_port; + _irqL irql; + int i; -void StopTxBeacon(_adapter *padapter) + #if 0 + if (cltp->num > MAX_CLIENT_PORT_NUM) { + RTW_ERR(ADPT_FMT" cann't alloc client (%d)\n", ADPT_ARG(adapter), cltp->num); + rtw_warn_on(1); + return; + } + #endif + + if (adapter->client_id != MAX_CLIENT_PORT_NUM) { + RTW_INFO(ADPT_FMT" client_id %d has allocated port:%d\n", + ADPT_ARG(adapter), adapter->client_id, adapter->client_port); + return; + } + _enter_critical_bh(&cltp->lock, &irql); + for (i = 0; i < MAX_CLIENT_PORT_NUM; i++) { + if (!(cltp->bmp & BIT(i))) + break; + } + + if (i < MAX_CLIENT_PORT_NUM) { + adapter->client_id = i; + cltp->bmp |= BIT(i); + adapter->client_port = _clt_port_id[i]; + } + cltp->num++; + _exit_critical_bh(&cltp->lock, &irql); + RTW_INFO("%s("ADPT_FMT")id:%d, port:%d clt_num:%d\n", + __func__, ADPT_ARG(adapter), adapter->client_id, adapter->client_port, cltp->num); +} +static void _hw_client_port_free(_adapter *adapter) { - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct clt_port_t *cltp = &dvobj->clt_port; + _irqL irql; + + #if 0 + if (adapter->client_id >= MAX_CLIENT_PORT_NUM) { + RTW_ERR(ADPT_FMT" client_id %d is invalid\n", ADPT_ARG(adapter), adapter->client_id); + /*rtw_warn_on(1);*/ + } + #endif + + RTW_INFO("%s ("ADPT_FMT") id:%d, port:%d clt_num:%d\n", + __func__, ADPT_ARG(adapter), adapter->client_id, adapter->client_port, cltp->num); + _enter_critical_bh(&cltp->lock, &irql); + if (adapter->client_id != MAX_CLIENT_PORT_NUM) { + cltp->bmp &= ~ BIT(adapter->client_id); + adapter->client_id = MAX_CLIENT_PORT_NUM; + adapter->client_port = CLT_PORT_INVALID; + } + cltp->num--; + if (cltp->num < 0) + cltp->num = 0; + _exit_critical_bh(&cltp->lock, &irql); +} +void rtw_hw_client_port_allocate(_adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ - /* which should be read from register to a global variable. */ + if (hal_spec->port_num != 5) + return; + _hw_client_port_alloc(adapter); +} +void rtw_hw_client_port_release(_adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - pHalData->RegFwHwTxQCtrl &= ~BIT(6); - rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl); - rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64); - pHalData->RegReg542 &= ~BIT(0); - rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542); + if (hal_spec->port_num != 5) + return; - /*CheckFwRsvdPageContent(padapter);*/ /* 2010.06.23. Added by tynli. */ + _hw_client_port_free(adapter); } +#endif /*CONFIG_CLIENT_PORT_CFG*/ -#ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/ void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode) { RTW_INFO("%s()-"ADPT_FMT" mode = %d\n", __func__, ADPT_ARG(Adapter), mode); - rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) & (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN))); - - /* disable Port0 TSF update*/ - rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) | DIS_TSF_UDT); + rtw_hal_rcr_set_chk_bssid(Adapter, MLME_ACTION_NONE); /* set net_type */ Set_MSR(Adapter, mode); if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) { - if (!rtw_mi_check_status(Adapter, MI_AP_MODE)) + if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter)) StopTxBeacon(Adapter); - - rtw_write8(Adapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM);/*disable atim wnd*/ - } else if (mode == _HW_STATE_ADHOC_) { - ResumeTxBeacon(Adapter); - rtw_write8(Adapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB); - - } else if (mode == _HW_STATE_AP_) { + } else if (mode == _HW_STATE_ADHOC_) ResumeTxBeacon(Adapter); + else if (mode == _HW_STATE_AP_) + /* enable rx ps-poll */ + rtw_write16(Adapter, REG_RXFLTMAP1, rtw_read16(Adapter, REG_RXFLTMAP1) | BIT_CTRLFLT10EN); - rtw_write8(Adapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB); - - /*enable to rx data frame*/ - rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF); - - /*Beacon Control related register for first time*/ - rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /* 2ms */ - - /*rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);*/ - rtw_write8(Adapter, REG_ATIMWND, 0x0a); /* 10ms */ - rtw_write16(Adapter, REG_BCNTCFG, 0x00); - rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04); - rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */ - - /*reset TSF*/ - rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0)); - - /*enable BCN0 Function for if1*/ - /*don't enable update TSF0 for if1 (due to TSF update when beacon,probe rsp are received)*/ - rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB)); - - if (IS_HARDWARE_TYPE_8821(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter))/* select BCN on port 0 for DualBeacon*/ - rtw_write8(Adapter, REG_CCK_CHECK, rtw_read8(Adapter, REG_CCK_CHECK) & (~BIT_BCN_PORT_SEL)); - - } + /* enable rx data frame */ + rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF); +#ifdef CONFIG_CLIENT_PORT_CFG + if (mode == _HW_STATE_STATION_) + rtw_hw_client_port_allocate(Adapter); + else + rtw_hw_client_port_release(Adapter); +#endif +#if defined(CONFIG_RTL8192F) + rtw_write16(Adapter, REG_WLAN_ACT_MASK_CTRL_1, rtw_read16(Adapter, + REG_WLAN_ACT_MASK_CTRL_1) | EN_PORT_0_FUNCTION); +#endif } #endif @@ -11642,3 +14284,147 @@ void rtw_dump_phy_cap(void *sel, _adapter *adapter) #endif } +inline s16 translate_dbm_to_percentage(s16 signal) +{ + if ((signal <= -100) || (signal >= 20)) + return 0; + else if (signal >= 0) + return 100; + else + return 100 + signal; +} + +#ifdef CONFIG_SWTIMER_BASED_TXBCN +#ifdef CONFIG_BCN_RECOVERY +#define REG_CPU_MGQ_INFO 0x041C +#define BIT_BCN_POLL BIT(28) +u8 rtw_ap_bcn_recovery(_adapter *padapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + + if (hal_data->issue_bcn_fail >= 2) { + RTW_ERR("%s ISSUE BCN Fail\n", __func__); + rtw_write8(padapter, REG_CPU_MGQ_INFO + 3, 0x10); + hal_data->issue_bcn_fail = 0; + } + return _SUCCESS; +} +#endif /*CONFIG_BCN_RECOVERY*/ + +#ifdef CONFIG_BCN_XMIT_PROTECT +u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms) +{ + u32 start_time = rtw_get_current_time(); + u8 bcn_queue_empty = _FALSE; + + do { + if (rtw_read16(padapter, REG_TXPKT_EMPTY) & BIT(11)) { + bcn_queue_empty = _TRUE; + break; + } + } while (rtw_get_passing_time_ms(start_time) <= (txbcn_timer_ms + 10)); + + if (bcn_queue_empty == _FALSE) + RTW_ERR("%s BCN queue not empty\n", __func__); + + return bcn_queue_empty; +} +#endif /*CONFIG_BCN_XMIT_PROTECT*/ +#endif /*CONFIG_SWTIMER_BASED_TXBCN*/ + +static void _rf_type_to_ant_path(enum rf_type rf, enum bb_path *tx, + enum bb_path *rx) +{ + if (tx) { + switch (rf) { + case RF_1T1R: + case RF_1T2R: + *tx = BB_PATH_A; + break; + case RF_2T2R: + case RF_2T3R: + case RF_2T4R: + *tx = BB_PATH_AB; + break; + case RF_3T3R: + case RF_3T4R: + *tx = BB_PATH_ABC; + break; + case RF_4T4R: + default: + *tx = BB_PATH_ABCD; + break; + } + } + + if (rx) { + switch (rf) { + case RF_1T1R: + *rx = BB_PATH_A; + break; + case RF_1T2R: + case RF_2T2R: + *rx = BB_PATH_AB; + break; + case RF_2T3R: + case RF_3T3R: + *rx = BB_PATH_ABC; + break; + case RF_2T4R: + case RF_3T4R: + case RF_4T4R: + default: + *rx = BB_PATH_ABCD; + break; + } + } +} + +/** + * rtw_hal_get_rf_path() - Get RF path related information + * @d: struct dvobj_priv* + * @type: RF type, nTnR + * @tx: Tx path + * @rx: Rx path + * + * Get RF type, TX path and RX path information. + */ +void rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type, + enum bb_path *tx, enum bb_path *rx) +{ + struct _ADAPTER *a; + u8 val8 = RF_1T1R; + enum rf_type rf; + + + a = dvobj_get_primary_adapter(d); + + rtw_hal_get_hwreg(a, HW_VAR_RF_TYPE, &val8); + rf = (enum rf_type)val8; + if (type) + *type = rf; + + if (tx || rx) + _rf_type_to_ant_path(rf, tx, rx); +} + +#ifdef RTW_CHANNEL_SWITCH_OFFLOAD +void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw) +{ + u8 h2c[H2C_SINGLE_CHANNELSWITCH_V2_LEN] = {0}; + PHAL_DATA_TYPE hal; + struct submit_ctx *chsw_sctx; + + hal = GET_HAL_DATA(adapter); + chsw_sctx = &hal->chsw_sctx; + + SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(h2c, central_ch); + SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(h2c, pri_ch_idx); + SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(h2c, bw); + + rtw_sctx_init(chsw_sctx, 10); + rtw_hal_fill_h2c_cmd(adapter, H2C_SINGLE_CHANNELSWITCH_V2, H2C_SINGLE_CHANNELSWITCH_V2_LEN, h2c); + rtw_sctx_wait(chsw_sctx, __func__); +} +#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ + diff --git a/hal/hal_com_c2h.h b/hal/hal_com_c2h.h index 6b7e987..1efabc9 100644 --- a/hal/hal_com_c2h.h +++ b/hal/hal_com_c2h.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __COMMON_C2H_H__ #define __COMMON_C2H_H__ @@ -75,6 +70,10 @@ typedef enum _C2H_EVT { C2H_DEFEATURE_DBG = 0x22, C2H_CUSTOMER_STR_RPT = 0x24, C2H_CUSTOMER_STR_RPT_2 = 0x25, + C2H_WLAN_INFO = 0x27, +#ifdef RTW_PER_CMD_SUPPORT_FW + C2H_PER_RATE_RPT = 0x2c, +#endif C2H_DEFEATURE_RSVD = 0xFD, C2H_EXTEND = 0xff, } C2H_EVT; @@ -116,4 +115,9 @@ int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len); int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len); #endif /* CONFIG_RTW_CUSTOMER_STR */ +#ifdef RTW_PER_CMD_SUPPORT_FW +/* C2H_PER_RATE_RPT, 0x2c */ +int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len); +#endif + #endif /* __COMMON_C2H_H__ */ diff --git a/hal/hal_com_phycfg.c b/hal/hal_com_phycfg.c index 40f733b..44de49e 100644 --- a/hal/hal_com_phycfg.c +++ b/hal/hal_com_phycfg.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,30 +11,27 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_COM_PHYCFG_C_ #include #include +#define PG_TXPWR_1PATH_BYTE_NUM_2G 18 +#define PG_TXPWR_BASE_BYTE_NUM_2G 11 + +#define PG_TXPWR_1PATH_BYTE_NUM_5G 24 +#define PG_TXPWR_BASE_BYTE_NUM_5G 14 + #define PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) (((_pg_v) & 0xf0) >> 4) #define PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) ((_pg_v) & 0x0f) #define PG_TXPWR_MSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_MSB_DIFF_S4BIT(_pg_v)) #define PG_TXPWR_LSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_LSB_DIFF_S4BIT(_pg_v)) -#define IS_PG_TXPWR_BASE_INVALID(_base) ((_base) > 63) +#define IS_PG_TXPWR_BASE_INVALID(hal_spec, _base) ((_base) > hal_spec->txgi_max) #define IS_PG_TXPWR_DIFF_INVALID(_diff) ((_diff) > 7 || (_diff) < -8) #define PG_TXPWR_INVALID_BASE 255 #define PG_TXPWR_INVALID_DIFF 8 -#if !IS_PG_TXPWR_BASE_INVALID(PG_TXPWR_INVALID_BASE) -#error "PG_TXPWR_BASE definition has problem" -#endif - #if !IS_PG_TXPWR_DIFF_INVALID(PG_TXPWR_INVALID_DIFF) #error "PG_TXPWR_DIFF definition has problem" #endif @@ -57,7 +54,8 @@ const char *const _pg_txpwr_src_str[] = { #define DBG_PG_TXPWR_READ 0 #endif -void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt) +#if DBG_PG_TXPWR_READ +static void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt) { int path, group, tx_idx; @@ -141,7 +139,7 @@ void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, RTW_PRINT_SEL(sel, "\n"); } -void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt) +static void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt) { int path, group, tx_idx; @@ -224,6 +222,7 @@ void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, } RTW_PRINT_SEL(sel, "\n"); } +#endif /* DBG_PG_TXPWR_READ */ const struct map_t pg_txpwr_def_info = MAP_ENT(0xB8, 1, 0xFF @@ -257,6 +256,14 @@ static const struct map_t rtl8188f_pg_txpwr_def_info = ); #endif +#ifdef CONFIG_RTL8188GTV +static const struct map_t rtl8188gtv_pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 12, + 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24) + ); +#endif + #ifdef CONFIG_RTL8723B static const struct map_t rtl8723b_pg_txpwr_def_info = MAP_ENT(0xB8, 2, 0xFF @@ -316,6 +323,14 @@ static const struct map_t rtl8821c_pg_txpwr_def_info = ); #endif +#ifdef CONFIG_RTL8710B +static const struct map_t rtl8710b_pg_txpwr_def_info = + MAP_ENT(0xC8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x20, 12, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x20) + ); +#endif + #ifdef CONFIG_RTL8812A static const struct map_t rtl8812a_pg_txpwr_def_info = MAP_ENT(0xB8, 1, 0xFF @@ -360,6 +375,16 @@ static const struct map_t rtl8814a_pg_txpwr_def_info = ); #endif +#ifdef CONFIG_RTL8192F/*use 8192F default,no document*/ +static const struct map_t rtl8192f_pg_txpwr_def_info = + MAP_ENT(0xB8, 2, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 14, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE) + , MAPSEG_ARRAY_ENT(0x3A, 14, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE) + ); +#endif + const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter) { u8 interface_type = 0; @@ -393,6 +418,11 @@ const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter) map = &rtl8188f_pg_txpwr_def_info; break; #endif +#ifdef CONFIG_RTL8188GTV + case RTL8188GTV: + map = &rtl8188gtv_pg_txpwr_def_info; + break; +#endif #ifdef CONFIG_RTL8812A case RTL8812: map = &rtl8812a_pg_txpwr_def_info; @@ -422,6 +452,16 @@ const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter) case RTL8821C: map = &rtl8821c_pg_txpwr_def_info; break; +#endif +#ifdef CONFIG_RTL8710B + case RTL8710B: + map = &rtl8710b_pg_txpwr_def_info; + break; +#endif +#ifdef CONFIG_RTL8192F + case RTL8192F: + map = &rtl8192f_pg_txpwr_def_info; + break; #endif } @@ -446,8 +486,8 @@ static u8 hal_chk_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info) if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) continue; for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { - if (IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexCCK_Base[path][group]) - || IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group])) + if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group]) + || IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])) return _FAIL; } for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { @@ -477,7 +517,7 @@ static u8 hal_chk_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info) if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) continue; for (group = 0; group < MAX_CHNL_GROUP_5G; group++) - if (IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group])) + if (IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group])) return _FAIL; for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { if (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) @@ -578,8 +618,6 @@ u16 hal_load_pg_txpwr_info_path_2g( const struct map_t *txpwr_map, u16 pg_offset) { -#define PG_TXPWR_1PATH_BYTE_NUM_2G 18 - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); u16 offset = pg_offset; u8 group, tx_idx; @@ -598,8 +636,8 @@ u16 hal_load_pg_txpwr_info_path_2g( for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) { tmp_base = map_read8(txpwr_map, offset); - if (!IS_PG_TXPWR_BASE_INVALID(tmp_base) - && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexCCK_Base[path][group]) + if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base) + && IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexCCK_Base[path][group]) ) { pwr_info->IndexCCK_Base[path][group] = tmp_base; if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) @@ -612,8 +650,8 @@ u16 hal_load_pg_txpwr_info_path_2g( for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) { if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) { tmp_base = map_read8(txpwr_map, offset); - if (!IS_PG_TXPWR_BASE_INVALID(tmp_base) - && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group]) + if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base) + && IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]) ) { pwr_info->IndexBW40_Base[path][group] = tmp_base; if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) @@ -708,8 +746,6 @@ u16 hal_load_pg_txpwr_info_path_5g( const struct map_t *txpwr_map, u16 pg_offset) { -#define PG_TXPWR_1PATH_BYTE_NUM_5G 24 - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); u16 offset = pg_offset; u8 group, tx_idx; @@ -732,8 +768,8 @@ u16 hal_load_pg_txpwr_info_path_5g( for (group = 0; group < MAX_CHNL_GROUP_5G; group++) { if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) { tmp_base = map_read8(txpwr_map, offset); - if (!IS_PG_TXPWR_BASE_INVALID(tmp_base) - && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group]) + if (!IS_PG_TXPWR_BASE_INVALID(hal_spec, tmp_base) + && IS_PG_TXPWR_BASE_INVALID(hal_spec, pwr_info->IndexBW40_Base[path][group]) ) { pwr_info->IndexBW40_Base[path][group] = tmp_base; if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) @@ -881,7 +917,7 @@ void hal_load_pg_txpwr_info( hal_init_pg_txpwr_info_5g(adapter, pwr_info_5g); select_src: - pg_offset = 0x10; + pg_offset = hal_spec->pg_txpwr_saddr; switch (txpwr_src) { case PG_TXPWR_SRC_PG_DATA: @@ -920,16 +956,89 @@ void hal_load_pg_txpwr_info( rtw_warn_on(1); exit: - if (DBG_PG_TXPWR_READ) { - if (pwr_info_2g) - dump_pg_txpwr_info_2g(RTW_DBGDUMP, pwr_info_2g, 4, 4); - if (pwr_info_5g) - dump_pg_txpwr_info_5g(RTW_DBGDUMP, pwr_info_5g, 4, 4); - } + #if DBG_PG_TXPWR_READ + if (pwr_info_2g) + dump_pg_txpwr_info_2g(RTW_DBGDUMP, pwr_info_2g, 4, 4); + if (pwr_info_5g) + dump_pg_txpwr_info_5g(RTW_DBGDUMP, pwr_info_5g, 4, 4); + #endif return; } +#ifdef CONFIG_EFUSE_CONFIG_FILE + +#define EFUSE_POWER_INDEX_INVALID 0xFF + +static u8 _check_phy_efuse_tx_power_info_valid(u8 *pg_data, int base_len, u16 pg_offset) +{ + int ff_cnt = 0; + int i; + + for (i = 0; i < base_len; i++) { + if (*(pg_data + pg_offset + i) == 0xFF) + ff_cnt++; + } + + if (ff_cnt == 0) + return _TRUE; + else if (ff_cnt == base_len) + return _FALSE; + else + return EFUSE_POWER_INDEX_INVALID; +} + +int check_phy_efuse_tx_power_info_valid(_adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 *pg_data = hal_data->efuse_eeprom_data; + u16 pg_offset = hal_spec->pg_txpwr_saddr; + u8 path; + u8 valid_2g_path_bmp = 0; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + u8 valid_5g_path_bmp = 0; +#endif + int result = _FALSE; + + for (path = 0; path < MAX_RF_PATH; path++) { + u8 ret = _FALSE; + + if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) + break; + + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) { + ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_2G, pg_offset); + if (ret == _TRUE) + valid_2g_path_bmp |= BIT(path); + else if (ret == EFUSE_POWER_INDEX_INVALID) + return _FALSE; + } + pg_offset += PG_TXPWR_1PATH_BYTE_NUM_2G; + + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) { + ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_5G, pg_offset); + if (ret == _TRUE) + valid_5g_path_bmp |= BIT(path); + else if (ret == EFUSE_POWER_INDEX_INVALID) + return _FALSE; + } + #endif + pg_offset += PG_TXPWR_1PATH_BYTE_NUM_5G; + } + + if ((hal_chk_band_cap(adapter, BAND_CAP_2G) && valid_2g_path_bmp) + #ifdef CONFIG_IEEE80211_BAND_5GHZ + || (hal_chk_band_cap(adapter, BAND_CAP_5G) && valid_5g_path_bmp) + #endif + ) + return _TRUE; + + return _FALSE; +} +#endif /* CONFIG_EFUSE_CONFIG_FILE */ + void hal_load_txpwr_info( _adapter *adapter, TxPowerInfo24G *pwr_info_2g, @@ -967,10 +1076,10 @@ void hal_load_txpwr_info( if (tx_idx >= max_tx_cnt) break; - hal_data->CCK_24G_Diff[rfpath][tx_idx] = pwr_info_2g->CCK_Diff[rfpath][tx_idx]; - hal_data->OFDM_24G_Diff[rfpath][tx_idx] = pwr_info_2g->OFDM_Diff[rfpath][tx_idx]; - hal_data->BW20_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW20_Diff[rfpath][tx_idx]; - hal_data->BW40_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW40_Diff[rfpath][tx_idx]; + hal_data->CCK_24G_Diff[rfpath][tx_idx] = pwr_info_2g->CCK_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor; + hal_data->OFDM_24G_Diff[rfpath][tx_idx] = pwr_info_2g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor; + hal_data->BW20_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor; + hal_data->BW40_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor; } bypass_2g: ; @@ -1002,10 +1111,10 @@ void hal_load_txpwr_info( if (tx_idx >= max_tx_cnt) break; - hal_data->OFDM_5G_Diff[rfpath][tx_idx] = pwr_info_5g->OFDM_Diff[rfpath][tx_idx]; - hal_data->BW20_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW20_Diff[rfpath][tx_idx]; - hal_data->BW40_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW40_Diff[rfpath][tx_idx]; - hal_data->BW80_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW80_Diff[rfpath][tx_idx]; + hal_data->OFDM_5G_Diff[rfpath][tx_idx] = pwr_info_5g->OFDM_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor; + hal_data->BW20_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW20_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor; + hal_data->BW40_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW40_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor; + hal_data->BW80_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW80_Diff[rfpath][tx_idx] * hal_spec->pg_txgi_diff_factor; } bypass_5g: ; @@ -1293,14 +1402,13 @@ bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter) /* * PHY_GetTxPowerByRateBase - * -* Return 2 times of dBm +* Return value in unit of TX Gain Index */ u8 PHY_GetTxPowerByRateBase( IN PADAPTER Adapter, IN u8 Band, IN u8 RfPath, - IN u8 TxNum, IN RATE_SECTION RateSection ) { @@ -1320,15 +1428,15 @@ PHY_GetTxPowerByRateBase( if (RateSection >= RATE_SECTION_NUM || (Band == BAND_ON_5G && RateSection == CCK) ) { - RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d, TxNum:%d\n", __func__ - , RateSection, Band, RfPath, TxNum); + RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__ + , RateSection, Band, RfPath); return 0; } if (Band == BAND_ON_2_4G) - value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][RateSection]; + value = pHalData->TxPwrByRateBase2_4G[RfPath][RateSection]; else /* BAND_ON_5G */ - value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][RateSection - 1]; + value = pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1]; return value; } @@ -1339,7 +1447,6 @@ phy_SetTxPowerByRateBase( IN u8 Band, IN u8 RfPath, IN RATE_SECTION RateSection, - IN u8 TxNum, IN u8 Value ) { @@ -1358,45 +1465,40 @@ phy_SetTxPowerByRateBase( if (RateSection >= RATE_SECTION_NUM || (Band == BAND_ON_5G && RateSection == CCK) ) { - RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d, TxNum:%d\n", __func__ - , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath, TxNum); + RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d\n", __func__ + , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath); return; } if (Band == BAND_ON_2_4G) - pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][RateSection] = Value; + pHalData->TxPwrByRateBase2_4G[RfPath][RateSection] = Value; else /* BAND_ON_5G */ - pHalData->TxPwrByRateBase5G[RfPath][TxNum][RateSection - 1] = Value; + pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1] = Value; } static inline BOOLEAN phy_is_txpwr_by_rate_undefined_of_band_path(_adapter *adapter, u8 band, u8 path) { struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - u8 tx_num = 0, rate_idx = 0; + u8 rate_idx = 0; - for (tx_num = 0; tx_num < TX_PWR_BY_RATE_NUM_RF; tx_num++) { - if (tx_num >= hal_spec->max_tx_cnt || tx_num >= hal_spec->tx_nss_num) + for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) { + if (hal_data->TxPwrByRateOffset[band][path][rate_idx] != 0) goto exit; - for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) { - if (hal_data->TxPwrByRateOffset[band][path][tx_num][rate_idx] != 0) - goto exit; - } } exit: - return (tx_num >= hal_spec->max_tx_cnt || tx_num >= hal_spec->tx_nss_num) ? _TRUE : _FALSE; + return rate_idx >= TX_PWR_BY_RATE_NUM_RATE ? _TRUE : _FALSE; } static inline void phy_txpwr_by_rate_duplicate_band_path(_adapter *adapter, u8 band, u8 s_path, u8 t_path) { struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - u8 tx_num = 0, rate_idx = 0; + u8 rate_idx = 0; - for (tx_num = 0; tx_num < TX_PWR_BY_RATE_NUM_RF; tx_num++) - for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) - hal_data->TxPwrByRateOffset[band][t_path][tx_num][rate_idx] = hal_data->TxPwrByRateOffset[band][s_path][tx_num][rate_idx]; + for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) + hal_data->TxPwrByRateOffset[band][t_path][rate_idx] = hal_data->TxPwrByRateOffset[band][s_path][rate_idx]; } static void phy_txpwr_by_rate_chk_for_path_dup(_adapter *adapter) @@ -1499,15 +1601,25 @@ phy_StoreTxPowerByRateBase( continue; if (regsty->target_tx_pwr_valid == _TRUE) - base = 2 * rtw_regsty_get_target_tx_power(pAdapter, band, path, rs); + base = hal_spec->txgi_pdbm * rtw_regsty_get_target_tx_power(pAdapter, band, path, rs); else - base = _PHY_GetTxPowerByRate(pAdapter, band, path, tx_num, rate_sec_base[rs]); - phy_SetTxPowerByRateBase(pAdapter, band, path, rs, tx_num, base); + base = _PHY_GetTxPowerByRate(pAdapter, band, path, rate_sec_base[rs]); + phy_SetTxPowerByRateBase(pAdapter, band, path, rs, base); } } } } +static u8 get_val_from_dhex(u32 dhex, u8 i) +{ + return (((dhex >> (i * 8 + 4)) & 0xF)) * 10 + ((dhex >> (i * 8)) & 0xF); +} + +static u8 get_val_from_hex(u32 hex, u8 i) +{ + return (hex >> (i * 8)) & 0xFF; +} + VOID PHY_GetRateValuesOfTxPowerByRate( IN PADAPTER pAdapter, @@ -1520,8 +1632,15 @@ PHY_GetRateValuesOfTxPowerByRate( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; u8 index = 0, i = 0; + u8 (*get_val)(u32, u8); + + if (hal_spec->txgi_pdbm == 2) + get_val = get_val_from_dhex; + else + get_val = get_val_from_hex; switch (RegAddr) { case rTxAGC_A_Rate18_06: @@ -1530,10 +1649,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_9M; Rate[2] = MGN_12M; Rate[3] = MGN_18M; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1543,17 +1660,14 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_36M; Rate[2] = MGN_48M; Rate[3] = MGN_54M; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; case rTxAGC_A_CCK1_Mcs32: Rate[0] = MGN_1M; - PwrByRateVal[0] = (s8)((((Value >> (8 + 4)) & 0xF)) * 10 + - ((Value >> 8) & 0xF)); + PwrByRateVal[0] = (s8)get_val(Value, 1); *RateNum = 1; break; @@ -1562,15 +1676,12 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[0] = MGN_2M; Rate[1] = MGN_5_5M; Rate[2] = MGN_11M; - for (i = 1; i < 4; ++i) { - PwrByRateVal[i - 1] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 1; i < 4; ++i) + PwrByRateVal[i - 1] = (s8)get_val(Value, i); *RateNum = 3; } else if (BitMask == 0x000000ff) { Rate[0] = MGN_11M; - PwrByRateVal[0] = (s8)((((Value >> 4) & 0xF)) * 10 + - (Value & 0xF)); + PwrByRateVal[0] = (s8)get_val(Value, 0); *RateNum = 1; } break; @@ -1581,10 +1692,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_MCS1; Rate[2] = MGN_MCS2; Rate[3] = MGN_MCS3; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1594,10 +1703,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_MCS5; Rate[2] = MGN_MCS6; Rate[3] = MGN_MCS7; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1607,10 +1714,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_MCS9; Rate[2] = MGN_MCS10; Rate[3] = MGN_MCS11; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1620,22 +1725,17 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_MCS13; Rate[2] = MGN_MCS14; Rate[3] = MGN_MCS15; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; - break; case rTxAGC_B_CCK1_55_Mcs32: Rate[0] = MGN_1M; Rate[1] = MGN_2M; Rate[2] = MGN_5_5M; - for (i = 1; i < 4; ++i) { - PwrByRateVal[i - 1] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 1; i < 4; ++i) + PwrByRateVal[i - 1] = (s8)get_val(Value, i); *RateNum = 3; break; @@ -1647,10 +1747,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_2M; Rate[2] = MGN_5_5M; Rate[3] = MGN_11M; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1662,10 +1760,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_9M; Rate[2] = MGN_12M; Rate[3] = MGN_18M; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1677,10 +1773,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_36M; Rate[2] = MGN_48M; Rate[3] = MGN_54M; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1692,10 +1786,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_MCS1; Rate[2] = MGN_MCS2; Rate[3] = MGN_MCS3; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1707,10 +1799,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_MCS5; Rate[2] = MGN_MCS6; Rate[3] = MGN_MCS7; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1722,10 +1812,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_MCS9; Rate[2] = MGN_MCS10; Rate[3] = MGN_MCS11; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1737,10 +1825,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_MCS13; Rate[2] = MGN_MCS14; Rate[3] = MGN_MCS15; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1752,10 +1838,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_VHT1SS_MCS1; Rate[2] = MGN_VHT1SS_MCS2; Rate[3] = MGN_VHT1SS_MCS3; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1767,10 +1851,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_VHT1SS_MCS5; Rate[2] = MGN_VHT1SS_MCS6; Rate[3] = MGN_VHT1SS_MCS7; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1782,10 +1864,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_VHT1SS_MCS9; Rate[2] = MGN_VHT2SS_MCS0; Rate[3] = MGN_VHT2SS_MCS1; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1797,10 +1877,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_VHT2SS_MCS3; Rate[2] = MGN_VHT2SS_MCS4; Rate[3] = MGN_VHT2SS_MCS5; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1812,10 +1890,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_VHT2SS_MCS7; Rate[2] = MGN_VHT2SS_MCS8; Rate[3] = MGN_VHT2SS_MCS9; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1827,10 +1903,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_MCS17; Rate[2] = MGN_MCS18; Rate[3] = MGN_MCS19; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1842,10 +1916,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_MCS21; Rate[2] = MGN_MCS22; Rate[3] = MGN_MCS23; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1857,10 +1929,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_VHT3SS_MCS1; Rate[2] = MGN_VHT3SS_MCS2; Rate[3] = MGN_VHT3SS_MCS3; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1872,10 +1942,8 @@ PHY_GetRateValuesOfTxPowerByRate( Rate[1] = MGN_VHT3SS_MCS5; Rate[2] = MGN_VHT3SS_MCS6; Rate[3] = MGN_VHT3SS_MCS7; - for (i = 0; i < 4; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 4; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 4; break; @@ -1885,10 +1953,8 @@ PHY_GetRateValuesOfTxPowerByRate( case 0x1aE8: Rate[0] = MGN_VHT3SS_MCS8; Rate[1] = MGN_VHT3SS_MCS9; - for (i = 0; i < 2; ++i) { - PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + - ((Value >> (i * 8)) & 0xF)); - } + for (i = 0; i < 2; ++i) + PwrByRateVal[i] = (s8)get_val(Value, i); *RateNum = 2; break; @@ -1903,7 +1969,6 @@ PHY_StoreTxPowerByRateNew( IN PADAPTER pAdapter, IN u32 Band, IN u32 RfPath, - IN u32 TxNum, IN u32 RegAddr, IN u32 BitMask, IN u32 Data @@ -1920,29 +1985,15 @@ PHY_StoreTxPowerByRateNew( return; } - if (RfPath > ODM_RF_PATH_D) { + if (RfPath > RF_PATH_D) { RTW_PRINT("Invalid RfPath %d\n", RfPath); return; } - if (TxNum > ODM_RF_PATH_D) { - RTW_PRINT("Invalid TxNum %d\n", TxNum); - return; - } - for (i = 0; i < rateNum; ++i) { u8 rate_idx = PHY_GetRateIndexOfTxPowerByRate(rates[i]); - if (IS_1T_RATE(rates[i])) - pHalData->TxPwrByRateOffset[Band][RfPath][RF_1TX][rate_idx] = PwrByRateVal[i]; - else if (IS_2T_RATE(rates[i])) - pHalData->TxPwrByRateOffset[Band][RfPath][RF_2TX][rate_idx] = PwrByRateVal[i]; - else if (IS_3T_RATE(rates[i])) - pHalData->TxPwrByRateOffset[Band][RfPath][RF_3TX][rate_idx] = PwrByRateVal[i]; - else if (IS_4T_RATE(rates[i])) - pHalData->TxPwrByRateOffset[Band][RfPath][RF_4TX][rate_idx] = PwrByRateVal[i]; - else - rtw_warn_on(1); + pHalData->TxPwrByRateOffset[Band][RfPath][rate_idx] = PwrByRateVal[i]; } } @@ -1952,13 +2003,12 @@ PHY_InitTxPowerByRate( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u8 band = 0, rfPath = 0, TxNum = 0, rate = 0, i = 0, j = 0; + u8 band = 0, rfPath = 0, rate = 0, i = 0, j = 0; for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath) - for (TxNum = 0; TxNum < TX_PWR_BY_RATE_NUM_RF; ++TxNum) for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate) - pHalData->TxPwrByRateOffset[band][rfPath][TxNum][rate] = 0; + pHalData->TxPwrByRateOffset[band][rfPath][rate] = 0; } VOID @@ -1973,10 +2023,10 @@ phy_store_tx_power_by_rate( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; if (pDM_Odm->phy_reg_pg_version > 0) - PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, TxNum, RegAddr, BitMask, Data); + PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, RegAddr, BitMask, Data); else RTW_INFO("Invalid PHY_REG_PG.txt version %d\n", pDM_Odm->phy_reg_pg_version); @@ -1989,7 +2039,7 @@ phy_ConvertTxPowerByRateInDbmToRelativeValues( { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); u8 base = 0, i = 0, value = 0, - band = 0, path = 0, txNum = 0, index = 0, + band = 0, path = 0, index = 0, startIndex = 0, endIndex = 0; u8 cckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}, ofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}, @@ -2006,65 +2056,63 @@ phy_ConvertTxPowerByRateInDbmToRelativeValues( /* RTW_INFO("===>PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */ for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) { - for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { - for (txNum = RF_1TX; txNum < RF_MAX_TX_NUM; ++txNum) { - /* CCK */ - if (band == BAND_ON_2_4G) { - base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, CCK); - for (i = 0; i < sizeof(cckRates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, cckRates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, cckRates[i], value - base); - } + for (path = RF_PATH_A; path <= RF_PATH_D; ++path) { + /* CCK */ + if (band == BAND_ON_2_4G) { + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, CCK); + for (i = 0; i < sizeof(cckRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, cckRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, cckRates[i], value - base); } + } - /* OFDM */ - base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, OFDM); - for (i = 0; i < sizeof(ofdmRates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, ofdmRates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, ofdmRates[i], value - base); - } + /* OFDM */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, OFDM); + for (i = 0; i < sizeof(ofdmRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, ofdmRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, ofdmRates[i], value - base); + } - /* HT MCS0~7 */ - base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, HT_1SS); - for (i = 0; i < sizeof(mcs0_7Rates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs0_7Rates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs0_7Rates[i], value - base); - } + /* HT MCS0~7 */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_1SS); + for (i = 0; i < sizeof(mcs0_7Rates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i], value - base); + } - /* HT MCS8~15 */ - base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, HT_2SS); - for (i = 0; i < sizeof(mcs8_15Rates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs8_15Rates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs8_15Rates[i], value - base); - } + /* HT MCS8~15 */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_2SS); + for (i = 0; i < sizeof(mcs8_15Rates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i], value - base); + } - /* HT MCS16~23 */ - base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, HT_3SS); - for (i = 0; i < sizeof(mcs16_23Rates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs16_23Rates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs16_23Rates[i], value - base); - } + /* HT MCS16~23 */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_3SS); + for (i = 0; i < sizeof(mcs16_23Rates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i], value - base); + } - /* VHT 1SS */ - base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, VHT_1SS); - for (i = 0; i < sizeof(vht1ssRates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht1ssRates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht1ssRates[i], value - base); - } + /* VHT 1SS */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_1SS); + for (i = 0; i < sizeof(vht1ssRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, vht1ssRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, vht1ssRates[i], value - base); + } - /* VHT 2SS */ - base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, VHT_2SS); - for (i = 0; i < sizeof(vht2ssRates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht2ssRates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht2ssRates[i], value - base); - } + /* VHT 2SS */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_2SS); + for (i = 0; i < sizeof(vht2ssRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, vht2ssRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, vht2ssRates[i], value - base); + } - /* VHT 3SS */ - base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, VHT_3SS); - for (i = 0; i < sizeof(vht3ssRates); ++i) { - value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht3ssRates[i]); - PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht3ssRates[i], value - base); - } + /* VHT 3SS */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_3SS); + for (i = 0; i < sizeof(vht3ssRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, vht3ssRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, vht3ssRates[i], value - base); } } } @@ -2091,7 +2139,7 @@ PHY_TxPowerByRateConfiguration( VOID phy_set_tx_power_index_by_rate_section( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Channel, IN u8 RateSection ) @@ -2143,15 +2191,16 @@ phy_GetChnlIndex( u8 PHY_GetTxPowerIndexBase( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, + u8 ntx_idx, + IN enum channel_width BandWidth, IN u8 Channel, OUT PBOOLEAN bIn24G ) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; u8 i = 0; /* default set to 1S */ u8 txPower = 0; u8 chnlIdx = (Channel - 1); @@ -2163,153 +2212,172 @@ PHY_GetTxPowerIndexBase( *bIn24G = phy_GetChnlIndex(Channel, &chnlIdx); - /* RTW_INFO("[%s] Channel Index: %d\n", (*bIn24G?"2.4G":"5G"), chnlIdx); */ + if (0) + RTW_INFO("[%s] Channel Index: %d\n", (*bIn24G ? "2.4G" : "5G"), chnlIdx); - if (*bIn24G) { /* 3 ============================== 2.4 G ============================== */ - if (IS_CCK_RATE(Rate)) + if (*bIn24G) { + if (IS_CCK_RATE(Rate)) { + /* CCK-nTX */ txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx]; - else if (MGN_6M <= Rate) - txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx]; - else - RTW_INFO("PHY_GetTxPowerIndexBase: INVALID Rate(0x%02x).\n", Rate); + txPower += pHalData->CCK_24G_Diff[RFPath][RF_1TX]; + if (ntx_idx >= RF_2TX) + txPower += pHalData->CCK_24G_Diff[RFPath][RF_2TX]; + if (ntx_idx >= RF_3TX) + txPower += pHalData->CCK_24G_Diff[RFPath][RF_3TX]; + if (ntx_idx >= RF_4TX) + txPower += pHalData->CCK_24G_Diff[RFPath][RF_4TX]; + goto exit; + } - /* RTW_INFO("Base Tx power(RF-%c, Rate #%d, Channel Index %d) = 0x%X\n", */ - /* ((RFPath==0)?'A':'B'), Rate, chnlIdx, txPower); */ + txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx]; - /* OFDM-1T */ + /* OFDM-nTX */ if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) { - txPower += pHalData->OFDM_24G_Diff[RFPath][TX_1S]; - /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (OFDM-1T) = (%d)\n", ((RFPath==0)?'A':'B'), pHalData->OFDM_24G_Diff[RFPath][TX_1S]); */ + txPower += pHalData->OFDM_24G_Diff[RFPath][RF_1TX]; + if (ntx_idx >= RF_2TX) + txPower += pHalData->OFDM_24G_Diff[RFPath][RF_2TX]; + if (ntx_idx >= RF_3TX) + txPower += pHalData->OFDM_24G_Diff[RFPath][RF_3TX]; + if (ntx_idx >= RF_4TX) + txPower += pHalData->OFDM_24G_Diff[RFPath][RF_4TX]; + goto exit; } - /* BW20-1S, BW20-2S */ + + /* BW20-nS */ if (BandWidth == CHANNEL_WIDTH_20) { if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_24G_Diff[RFPath][TX_1S]; + txPower += pHalData->BW20_24G_Diff[RFPath][RF_1TX]; if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_24G_Diff[RFPath][TX_2S]; + txPower += pHalData->BW20_24G_Diff[RFPath][RF_2TX]; if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_24G_Diff[RFPath][TX_3S]; + txPower += pHalData->BW20_24G_Diff[RFPath][RF_3TX]; if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_24G_Diff[RFPath][TX_4S]; - - /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW20-1S, BW20-2S, BW20-3S, BW20-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW20_24G_Diff[RFPath][TX_1S], pHalData->BW20_24G_Diff[RFPath][TX_2S], */ - /* pHalData->BW20_24G_Diff[RFPath][TX_3S], pHalData->BW20_24G_Diff[RFPath][TX_4S]); */ + txPower += pHalData->BW20_24G_Diff[RFPath][RF_4TX]; + goto exit; } - /* BW40-1S, BW40-2S */ - else if (BandWidth == CHANNEL_WIDTH_40) { + + /* BW40-nS */ + if (BandWidth == CHANNEL_WIDTH_40) { if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S]; + txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX]; if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S]; + txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX]; if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S]; + txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX]; if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S]; - - /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW40-1S, BW40-2S, BW40-3S, BW40-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW40_24G_Diff[RFPath][TX_1S], pHalData->BW40_24G_Diff[RFPath][TX_2S], */ - /* pHalData->BW40_24G_Diff[RFPath][TX_3S], pHalData->BW40_24G_Diff[RFPath][TX_4S]); */ + txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX]; + goto exit; } + /* Willis suggest adopt BW 40M power index while in BW 80 mode */ - else if (BandWidth == CHANNEL_WIDTH_80) { + if (BandWidth == CHANNEL_WIDTH_80) { if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S]; + txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX]; if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S]; + txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX]; if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S]; + txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX]; if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S]; - - /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW40-1S, BW40-2S, BW40-3S, BW40-4T) = (%d, %d, %d, %d) P.S. Current is in BW 80MHz\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW40_24G_Diff[RFPath][TX_1S], pHalData->BW40_24G_Diff[RFPath][TX_2S], */ - /* pHalData->BW40_24G_Diff[RFPath][TX_3S], pHalData->BW40_24G_Diff[RFPath][TX_4S]); */ + txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX]; + goto exit; } } #ifdef CONFIG_IEEE80211_BAND_5GHZ - else { /* 3 ============================== 5 G ============================== */ - if (MGN_6M <= Rate) + else { + if (Rate >= MGN_6M) txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx]; - else + else { RTW_INFO("===>PHY_GetTxPowerIndexBase: INVALID Rate(0x%02x).\n", Rate); + goto exit; + } - /* RTW_INFO("Base Tx power(RF-%c, Rate #%d, Channel Index %d) = 0x%X\n", */ - /* ((RFPath==0)?'A':'B'), Rate, chnlIdx, txPower); */ - - /* OFDM-1T */ + /* OFDM-nTX */ if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) { - txPower += pHalData->OFDM_5G_Diff[RFPath][TX_1S]; - /* RTW_INFO("+PowerDiff 5G (RF-%c): (OFDM-1T) = (%d)\n", ((RFPath==0)?'A':'B'), pHalData->OFDM_5G_Diff[RFPath][TX_1S]); */ + txPower += pHalData->OFDM_5G_Diff[RFPath][RF_1TX]; + if (ntx_idx >= RF_2TX) + txPower += pHalData->OFDM_5G_Diff[RFPath][RF_2TX]; + if (ntx_idx >= RF_3TX) + txPower += pHalData->OFDM_5G_Diff[RFPath][RF_3TX]; + if (ntx_idx >= RF_4TX) + txPower += pHalData->OFDM_5G_Diff[RFPath][RF_4TX]; + goto exit; } - /* BW20-1S, BW20-2S */ + /* BW20-nS */ if (BandWidth == CHANNEL_WIDTH_20) { if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_5G_Diff[RFPath][TX_1S]; + txPower += pHalData->BW20_5G_Diff[RFPath][RF_1TX]; if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_5G_Diff[RFPath][TX_2S]; + txPower += pHalData->BW20_5G_Diff[RFPath][RF_2TX]; if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_5G_Diff[RFPath][TX_3S]; + txPower += pHalData->BW20_5G_Diff[RFPath][RF_3TX]; if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW20_5G_Diff[RFPath][TX_4S]; - - /* RTW_INFO("+PowerDiff 5G (RF-%c): (BW20-1S, BW20-2S, BW20-3S, BW20-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW20_5G_Diff[RFPath][TX_1S], pHalData->BW20_5G_Diff[RFPath][TX_2S], */ - /* pHalData->BW20_5G_Diff[RFPath][TX_3S], pHalData->BW20_5G_Diff[RFPath][TX_4S]); */ + txPower += pHalData->BW20_5G_Diff[RFPath][RF_4TX]; + goto exit; } - /* BW40-1S, BW40-2S */ - else if (BandWidth == CHANNEL_WIDTH_40) { + + /* BW40-nS */ + if (BandWidth == CHANNEL_WIDTH_40) { if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_5G_Diff[RFPath][TX_1S]; + txPower += pHalData->BW40_5G_Diff[RFPath][RF_1TX]; if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_5G_Diff[RFPath][TX_2S]; + txPower += pHalData->BW40_5G_Diff[RFPath][RF_2TX]; if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_5G_Diff[RFPath][TX_3S]; + txPower += pHalData->BW40_5G_Diff[RFPath][RF_3TX]; if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW40_5G_Diff[RFPath][TX_4S]; - - /* RTW_INFO("+PowerDiff 5G(RF-%c): (BW40-1S, BW40-2S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW40_5G_Diff[RFPath][TX_1S], pHalData->BW40_5G_Diff[RFPath][TX_2S], */ - /* pHalData->BW40_5G_Diff[RFPath][TX_3S], pHalData->BW40_5G_Diff[RFPath][TX_4S]); */ + txPower += pHalData->BW40_5G_Diff[RFPath][RF_4TX]; + goto exit; } - /* BW80-1S, BW80-2S */ - else if (BandWidth == CHANNEL_WIDTH_80) { - /* <20121220, Kordan> Get the index of array "Index5G_BW80_Base". */ - for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) - if (center_ch_5g_80m[i] == Channel) + + /* BW80-nS */ + if (BandWidth == CHANNEL_WIDTH_80) { + /* get 80MHz cch index */ + for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) { + if (center_ch_5g_80m[i] == Channel) { chnlIdx = i; + break; + } + } + if (i >= CENTER_CH_5G_80M_NUM) { + #ifdef CONFIG_MP_INCLUDED + if (rtw_mp_mode_check(pAdapter) == _FALSE) + #endif + rtw_warn_on(1); + txPower = 0; + goto exit; + } txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx]; if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += + pHalData->BW80_5G_Diff[RFPath][TX_1S]; + txPower += + pHalData->BW80_5G_Diff[RFPath][RF_1TX]; if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW80_5G_Diff[RFPath][TX_2S]; + txPower += pHalData->BW80_5G_Diff[RFPath][RF_2TX]; if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW80_5G_Diff[RFPath][TX_3S]; + txPower += pHalData->BW80_5G_Diff[RFPath][RF_3TX]; if ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) - txPower += pHalData->BW80_5G_Diff[RFPath][TX_4S]; - - /* RTW_INFO("+PowerDiff 5G(RF-%c): (BW80-1S, BW80-2S, BW80-3S, BW80-4S) = (%d, %d, %d, %d)\n",((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ - /* pHalData->BW80_5G_Diff[RFPath][TX_1S], pHalData->BW80_5G_Diff[RFPath][TX_2S], */ - /* pHalData->BW80_5G_Diff[RFPath][TX_3S], pHalData->BW80_5G_Diff[RFPath][TX_4S]); */ + txPower += pHalData->BW80_5G_Diff[RFPath][RF_4TX]; + goto exit; } + + /* TODO: BW160-nS */ + rtw_warn_on(1); } #endif /* CONFIG_IEEE80211_BAND_5GHZ */ +exit: return txPower; } s8 PHY_GetTxPowerTrackingOffset( PADAPTER pAdapter, - u8 RFPath, + enum rf_path RFPath, u8 Rate ) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; s8 offset = 0; if (pDM_Odm->rf_calibrate_info.txpowertrack_control == _FALSE) @@ -2599,8 +2667,7 @@ s8 _PHY_GetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, + IN enum rf_path RFPath, IN u8 Rate ) { @@ -2612,20 +2679,16 @@ _PHY_GetTxPowerByRate( RTW_INFO("Invalid band %d in %s\n", Band, __func__); goto exit; } - if (RFPath > ODM_RF_PATH_D) { + if (RFPath > RF_PATH_D) { RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __func__); goto exit; } - if (TxNum >= RF_MAX_TX_NUM) { - RTW_INFO("Invalid TxNum %d in %s\n", TxNum, __func__); - goto exit; - } if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) { RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __func__); goto exit; } - value = pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex]; + value = pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex]; exit: return value; @@ -2636,66 +2699,21 @@ s8 PHY_GetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, + IN enum rf_path RFPath, IN u8 Rate ) { if (!phy_is_tx_power_by_rate_needed(pAdapter)) return 0; - return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, TxNum, Rate); -} - -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI -s8 -PHY_GetTxPowerByRateOriginal( - IN PADAPTER pAdapter, - IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, - IN u8 Rate -) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - s8 value = 0, limit = 0; - u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); - - if ((pAdapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory == 2) || - pAdapter->registrypriv.RegEnableTxPowerByRate == 0) - return 0; - - if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { - DBG_871X("Invalid band %d in %s\n", Band, __func__); - return value; - } - if (RFPath > ODM_RF_PATH_D) { - DBG_871X("Invalid RfPath %d in %s\n", RFPath, __func__); - return value; - } - if (TxNum >= RF_MAX_TX_NUM) { - DBG_871X("Invalid TxNum %d in %s\n", TxNum, __func__); - return value; - } - if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) { - DBG_871X("Invalid RateIndex %d in %s\n", rateIndex, __func__); - return value; - } - - value = pHalData->TxPwrByRate[Band][RFPath][TxNum][rateIndex]; - - return value; + return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, Rate); } -#endif - - VOID PHY_SetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, + IN enum rf_path RFPath, IN u8 Rate, IN s8 Value ) @@ -2707,20 +2725,44 @@ PHY_SetTxPowerByRate( RTW_INFO("Invalid band %d in %s\n", Band, __FUNCTION__); return; } - if (RFPath > ODM_RF_PATH_D) { + if (RFPath > RF_PATH_D) { RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __FUNCTION__); return; } - if (TxNum >= RF_MAX_TX_NUM) { - RTW_INFO("Invalid TxNum %d in %s\n", TxNum, __FUNCTION__); - return; - } if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) { RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __FUNCTION__); return; } - pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex] = Value; + pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex] = Value; +} + +u8 phy_check_under_survey_ch(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + struct mlme_ext_priv *mlmeext; + u8 ret = _FALSE; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + mlmeext = &iface->mlmeextpriv; + + /* check scan state */ + if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE + && mlmeext_scan_state(mlmeext) != SCAN_COMPLETE + && mlmeext_scan_state(mlmeext) != SCAN_BACKING_OP) { + ret = _TRUE; + } else if (mlmeext_scan_state(mlmeext) == SCAN_BACKING_OP + && !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)) { + ret = _TRUE; + } + } + + return ret; } VOID @@ -2732,6 +2774,8 @@ phy_set_tx_power_level_by_path( { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); BOOLEAN bIsIn24G = (pHalData->current_band_type == BAND_ON_2_4G); + u8 under_survey_ch = phy_check_under_survey_ch(Adapter); + /* if ( pMgntInfo->RegNByteAccess == 0 ) */ { @@ -2739,20 +2783,23 @@ phy_set_tx_power_level_by_path( phy_set_tx_power_index_by_rate_section(Adapter, path, channel, CCK); phy_set_tx_power_index_by_rate_section(Adapter, path, channel, OFDM); - phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS0_MCS7); - if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter)) - phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9); - - if (pHalData->NumTotalRFPath >= 2) { - phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS8_MCS15); + if (!under_survey_ch) { + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS0_MCS7); if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter)) - phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9); + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9); + + if (pHalData->NumTotalRFPath >= 2) { + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS8_MCS15); - if (IS_HARDWARE_TYPE_8814A(Adapter)) { - phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS16_MCS23); - phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9); + if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter)) + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9); + + if (IS_HARDWARE_TYPE_8814A(Adapter)) { + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS16_MCS23); + phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9); + } } } } @@ -2765,8 +2812,8 @@ phy_set_tx_power_level_by_path( VOID PHY_SetTxPowerIndexByRateArray( IN PADAPTER pAdapter, - IN u8 RFPath, - IN CHANNEL_WIDTH BandWidth, + IN enum rf_path RFPath, + IN enum channel_width BandWidth, IN u8 Channel, IN u8 *Rates, IN u8 RateArraySize @@ -2780,8 +2827,8 @@ PHY_SetTxPowerIndexByRateArray( struct txpwr_idx_comp tic; powerIndex = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel, &tic); - RTW_INFO("TXPWR: [%c][%s]ch:%u, %s, pwr_idx:%u = %u + (%d=%d:%d) + (%d) + (%d)\n" - , rf_path_char(RFPath), ch_width_str(BandWidth), Channel, MGN_RATE_STR(Rates[i]) + RTW_INFO("TXPWR: [%c][%s]ch:%u, %s %uT, pwr_idx:%u = %u + (%d=%d:%d) + (%d) + (%d)\n" + , rf_path_char(RFPath), ch_width_str(BandWidth), Channel, MGN_RATE_STR(Rates[i]), tic.ntx_idx + 1 , powerIndex, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias); #else powerIndex = phy_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel); @@ -2790,23 +2837,16 @@ PHY_SetTxPowerIndexByRateArray( } } -s8 -phy_GetWorldWideLimit( - s8 *LimitTable -) -{ - s8 min = LimitTable[0]; - u8 i = 0; - - for (i = 0; i < MAX_REGULATION_NUM; ++i) { - if (LimitTable[i] < min) - min = LimitTable[i]; - } - - return min; -} +#ifdef CONFIG_TXPWR_LIMIT +const char *const _txpwr_lmt_rs_str[] = { + "CCK", + "OFDM", + "HT", + "VHT", + "UNKNOWN", +}; -s8 +static s8 phy_GetChannelIndexOfTxPowerLimit( IN u8 Band, IN u8 Channel @@ -2831,536 +2871,428 @@ phy_GetChannelIndexOfTxPowerLimit( return channelIndex; } -static s8 _phy_get_txpwr_lmt( +static s8 phy_txpwr_ww_lmt_value(_adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + + if (hal_spec->txgi_max == 63) + return -63; + else if (hal_spec->txgi_max == 127) + return -128; + + rtw_warn_on(1); + return -128; +} + +/* +* return txpwr limit absolute value +* hsl_spec->txgi_max is returned when NO limit +*/ +s8 phy_get_txpwr_lmt_abs( IN PADAPTER Adapter, - IN u32 RegPwrTblSel, + IN const char *regd_name, IN BAND_TYPE Band, - IN CHANNEL_WIDTH Bandwidth, - IN u8 RfPath, - IN u8 DataRate, - IN u8 Channel, - BOOLEAN no_sc + IN enum channel_width bw, + u8 tlrs, + u8 ntx_idx, + u8 cch, + u8 lock ) { struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(Adapter); HAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter); - s8 regulation = -1, bw = -1, rs = -1; - u8 cch = 0; - u8 bw_bmp = 0; - s8 min_lmt = MAX_POWER_INDEX; - s8 tmp_lmt; - u8 final_bw = Bandwidth, final_cch = Channel; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter); + struct txpwr_lmt_ent *ent = NULL; + _irqL irqL; + _list *cur, *head; + s8 ch_idx; + u8 is_ww_regd = 0; + s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter); + s8 lmt = hal_spec->txgi_max; if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) || Adapter->registrypriv.RegEnableTxPowerLimit == 0) goto exit; - switch (RegPwrTblSel) { - case 1: - regulation = TXPWR_LMT_ETSI; - break; - case 2: - regulation = TXPWR_LMT_MKK; - break; - case 3: - regulation = TXPWR_LMT_FCC; - break; - case 4: - regulation = TXPWR_LMT_WW; - break; - default: - regulation = (Band == BAND_ON_2_4G) ? hal_data->Regulation2_4G : hal_data->Regulation5G; - break; - } - if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { RTW_ERR("%s invalid band:%u\n", __func__, Band); rtw_warn_on(1); goto exit; } - if (IS_CCK_RATE(DataRate)) - rs = CCK; - else if (IS_OFDM_RATE(DataRate)) - rs = OFDM; - else if (IS_HT1SS_RATE(DataRate)) - rs = HT_1SS; - else if (IS_HT2SS_RATE(DataRate)) - rs = HT_2SS; - else if (IS_HT3SS_RATE(DataRate)) - rs = HT_3SS; - else if (IS_HT4SS_RATE(DataRate)) - rs = HT_4SS; - else if (IS_VHT1SS_RATE(DataRate)) - rs = VHT_1SS; - else if (IS_VHT2SS_RATE(DataRate)) - rs = VHT_2SS; - else if (IS_VHT3SS_RATE(DataRate)) - rs = VHT_3SS; - else if (IS_VHT4SS_RATE(DataRate)) - rs = VHT_4SS; - else { - RTW_ERR("%s invalid rate 0x%x\n", __func__, DataRate); - rtw_warn_on(1); + if (Band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK) { + RTW_ERR("5G has no CCK\n"); goto exit; } - if (Band == BAND_ON_5G && rs == CCK) { - RTW_ERR("Wrong rate No CCK(0x%x) in 5G Band\n", DataRate); - goto exit; + if (lock) + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + + if (!regd_name) /* no regd_name specified, use currnet */ + regd_name = rfctl->regd_name; + + if (rfctl->txpwr_regd_num == 0 + || strcmp(regd_name, regd_str(TXPWR_LMT_NONE)) == 0) + goto release_lock; + + if (strcmp(regd_name, regd_str(TXPWR_LMT_WW)) == 0) + is_ww_regd = 1; + + if (!is_ww_regd) { + ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name); + if (!ent) + goto release_lock; } - if (no_sc == _TRUE) { - /* use the input center channel and bandwidth directly */ - cch = Channel; - bw_bmp = ch_width_to_bw_cap(Bandwidth); - } else { - /* - * find the possible tx bandwidth bmp for this rate, and then will get center channel for each bandwidth - * if no possible tx bandwidth bmp, select valid bandwidth up to current RF bandwidth into bmp - */ - if (rs == CCK || rs == OFDM) - bw_bmp = BW_CAP_20M; /* CCK, OFDM only BW 20M */ - else if (IS_HT_RATE_SECTION(rs)) { - bw_bmp = rtw_get_tx_bw_bmp_of_ht_rate(dvobj, DataRate, Bandwidth); - if (bw_bmp == 0) - bw_bmp = ch_width_to_bw_cap(Bandwidth > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 : Bandwidth); - } else if (IS_VHT_RATE_SECTION(rs)) { - bw_bmp = rtw_get_tx_bw_bmp_of_vht_rate(dvobj, DataRate, Bandwidth); - if (bw_bmp == 0) - bw_bmp = ch_width_to_bw_cap(Bandwidth > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 : Bandwidth); - } else - rtw_warn_on(1); - } - - if (bw_bmp == 0) - goto exit; - - /* loop for each possible tx bandwidth to find minimum limit */ - for (bw = CHANNEL_WIDTH_20; bw <= Bandwidth; bw++) { - s8 ch_idx; - - if (!(ch_width_to_bw_cap(bw) & bw_bmp)) - continue; + ch_idx = phy_GetChannelIndexOfTxPowerLimit(Band, cch); + if (ch_idx == -1) + goto release_lock; - if (no_sc == _FALSE) { - if (bw == CHANNEL_WIDTH_20) - cch = hal_data->cch_20; - else if (bw == CHANNEL_WIDTH_40) - cch = hal_data->cch_40; - else if (bw == CHANNEL_WIDTH_80) - cch = hal_data->cch_80; - else { - cch = 0; - rtw_warn_on(1); - } + if (Band == BAND_ON_2_4G) { + if (!is_ww_regd) { + lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]; + if (lmt != ww_lmt_val) + goto release_lock; } - ch_idx = phy_GetChannelIndexOfTxPowerLimit(Band, cch); - if (ch_idx == -1) - continue; - - if (Band == BAND_ON_2_4G) { - s8 limits[MAX_REGULATION_NUM] = {0}; - u8 i = 0; - - for (i = 0; i < MAX_REGULATION_NUM; ++i) - limits[i] = hal_data->TxPwrLimit_2_4G[i][bw][rs][ch_idx][RfPath]; - - tmp_lmt = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : - hal_data->TxPwrLimit_2_4G[regulation][bw][rs][ch_idx][RfPath]; - - } else if (Band == BAND_ON_5G) { - s8 limits[MAX_REGULATION_NUM] = {0}; - u8 i = 0; - - for (i = 0; i < MAX_REGULATION_NUM; ++i) - limits[i] = hal_data->TxPwrLimit_5G[i][bw][rs][ch_idx][RfPath]; - - tmp_lmt = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : - hal_data->TxPwrLimit_5G[regulation][bw][rs][ch_idx][RfPath]; - } else - continue; + /* search for min value for WW regd or WW limit */ + lmt = hal_spec->txgi_max; + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + if (ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] != ww_lmt_val) + lmt = rtw_min(lmt, ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]); + } + } + #ifdef CONFIG_IEEE80211_BAND_5GHZ + else if (Band == BAND_ON_5G) { + if (!is_ww_regd) { + lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]; + if (lmt != ww_lmt_val) + goto release_lock; + } - if (min_lmt >= tmp_lmt) { - min_lmt = tmp_lmt; - final_cch = cch; - final_bw = bw; + /* search for min value for WW regd or WW limit */ + lmt = hal_spec->txgi_max; + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + if (ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] != ww_lmt_val) + lmt = rtw_min(lmt, ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]); } } + #endif + +release_lock: + if (lock) + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); exit: - return min_lmt; + return lmt; } -inline s8 -PHY_GetTxPowerLimit( - IN PADAPTER Adapter, - IN u32 RegPwrTblSel, - IN BAND_TYPE Band, - IN CHANNEL_WIDTH Bandwidth, - IN u8 RfPath, - IN u8 DataRate, - IN u8 Channel +/* +* return txpwr limit diff value +* hal_spec->txgi_max is returned when NO limit +*/ +inline s8 phy_get_txpwr_lmt(_adapter *adapter + , const char *regd_name + , BAND_TYPE band, enum channel_width bw + , u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock ) { - BOOLEAN no_sc = _FALSE; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 tlrs; + s8 lmt = hal_spec->txgi_max; + + if (IS_CCK_RATE_SECTION(rs)) + tlrs = TXPWR_LMT_RS_CCK; + else if (IS_OFDM_RATE_SECTION(rs)) + tlrs = TXPWR_LMT_RS_OFDM; + else if (IS_HT_RATE_SECTION(rs)) + tlrs = TXPWR_LMT_RS_HT; + else if (IS_VHT_RATE_SECTION(rs)) + tlrs = TXPWR_LMT_RS_VHT; + else { + RTW_ERR("%s invalid rs %u\n", __func__, rs); + rtw_warn_on(1); + goto exit; + } - /* MP mode channel don't use secondary channel */ - if (rtw_mi_mp_mode_check(Adapter) == _TRUE) - no_sc = _TRUE; + lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock); - return _phy_get_txpwr_lmt(Adapter, RegPwrTblSel, Band, Bandwidth, RfPath, DataRate, Channel, no_sc); -} + if (lmt != hal_spec->txgi_max) { + /* return diff value */ + lmt = lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs); + } -inline s8 -PHY_GetTxPowerLimit_no_sc( - IN PADAPTER Adapter, - IN u32 RegPwrTblSel, - IN BAND_TYPE Band, - IN CHANNEL_WIDTH Bandwidth, - IN u8 RfPath, - IN u8 DataRate, - IN u8 Channel -) -{ - return _phy_get_txpwr_lmt(Adapter, RegPwrTblSel, Band, Bandwidth, RfPath, DataRate, Channel, _TRUE); +exit: + return lmt; } -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI +/* +* May search for secondary channels for min limit +* return txpwr limit diff value +*/ s8 -PHY_GetTxPowerLimitOriginal( - IN PADAPTER Adapter, - IN u32 RegPwrTblSel, - IN BAND_TYPE Band, - IN CHANNEL_WIDTH Bandwidth, - IN u8 RfPath, - IN u8 DataRate, - IN u8 Channel -) +PHY_GetTxPowerLimit(_adapter *adapter + , const char *regd_name + , BAND_TYPE band, enum channel_width bw + , u8 rfpath, u8 rate, u8 ntx_idx, u8 cch) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - s16 band = -1, regulation = -1, bandwidth = -1, - rateSection = -1, channel = -1; - s8 powerLimit = MAX_POWER_INDEX; - - if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory != 1) || - Adapter->registrypriv.RegEnableTxPowerLimit == 0) - return MAX_POWER_INDEX; - - switch (Adapter->registrypriv.RegPwrTblSel) { - case 1: - regulation = TXPWR_LMT_ETSI; - break; - - case 2: - regulation = TXPWR_LMT_MKK; - break; - - case 3: - regulation = TXPWR_LMT_FCC; - break; - - case 4: - regulation = TXPWR_LMT_WW; - break; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + BOOLEAN no_sc = _FALSE; + s8 tlrs = -1, rs = -1; + s8 lmt = hal_spec->txgi_max; + u8 tmp_cch = 0; + u8 tmp_bw; + u8 bw_bmp = 0; + s8 min_lmt = hal_spec->txgi_max; + u8 final_bw = bw, final_cch = cch; + _irqL irqL; - default: - regulation = (Band == BAND_ON_2_4G) ? pHalData->Regulation2_4G - : pHalData->Regulation5G; - break; +#ifdef CONFIG_MP_INCLUDED + /* MP mode channel don't use secondary channel */ + if (rtw_mp_mode_check(adapter) == _TRUE) + no_sc = _TRUE; +#endif + if (IS_CCK_RATE(rate)) { + tlrs = TXPWR_LMT_RS_CCK; + rs = CCK; + } else if (IS_OFDM_RATE(rate)) { + tlrs = TXPWR_LMT_RS_OFDM; + rs = OFDM; + } else if (IS_HT_RATE(rate)) { + tlrs = TXPWR_LMT_RS_HT; + rs = HT_1SS + (IS_HT1SS_RATE(rate) ? 0 : IS_HT2SS_RATE(rate) ? 1 : IS_HT3SS_RATE(rate) ? 2 : IS_HT4SS_RATE(rate) ? 3 : 0); + } else if (IS_VHT_RATE(rate)) { + tlrs = TXPWR_LMT_RS_VHT; + rs = VHT_1SS + (IS_VHT1SS_RATE(rate) ? 0 : IS_VHT2SS_RATE(rate) ? 1 : IS_VHT3SS_RATE(rate) ? 2 : IS_VHT4SS_RATE(rate) ? 3 : 0); + } else { + RTW_ERR("%s invalid rate 0x%x\n", __func__, rate); + rtw_warn_on(1); + goto exit; } - /*DBG_871X("pMgntInfo->RegPwrTblSel %d, final regulation %d\n", Adapter->registrypriv.RegPwrTblSel, regulation );*/ - - - if (Band == BAND_ON_2_4G) - band = 0; - else if (Band == BAND_ON_5G) - band = 1; - - if (Bandwidth == CHANNEL_WIDTH_20) - bandwidth = 0; - else if (Bandwidth == CHANNEL_WIDTH_40) - bandwidth = 1; - else if (Bandwidth == CHANNEL_WIDTH_80) - bandwidth = 2; - else if (Bandwidth == CHANNEL_WIDTH_160) - bandwidth = 3; - - switch (DataRate) { - case MGN_1M: - case MGN_2M: - case MGN_5_5M: - case MGN_11M: - rateSection = 0; - break; + if (no_sc == _TRUE) { + /* use the input center channel and bandwidth directly */ + tmp_cch = cch; + bw_bmp = ch_width_to_bw_cap(bw); + } else { + /* + * find the possible tx bandwidth bmp for this rate, and then will get center channel for each bandwidth + * if no possible tx bandwidth bmp, select valid bandwidth up to current RF bandwidth into bmp + */ + if (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM) + bw_bmp = BW_CAP_20M; /* CCK, OFDM only BW 20M */ + else if (tlrs == TXPWR_LMT_RS_HT) { + bw_bmp = rtw_get_tx_bw_bmp_of_ht_rate(dvobj, rate, bw); + if (bw_bmp == 0) + bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 : bw); + } else if (tlrs == TXPWR_LMT_RS_VHT) { + bw_bmp = rtw_get_tx_bw_bmp_of_vht_rate(dvobj, rate, bw); + if (bw_bmp == 0) + bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 : bw); + } else + rtw_warn_on(1); + } - case MGN_6M: - case MGN_9M: - case MGN_12M: - case MGN_18M: - case MGN_24M: - case MGN_36M: - case MGN_48M: - case MGN_54M: - rateSection = 1; - break; + if (bw_bmp == 0) + goto exit; - case MGN_MCS0: - case MGN_MCS1: - case MGN_MCS2: - case MGN_MCS3: - case MGN_MCS4: - case MGN_MCS5: - case MGN_MCS6: - case MGN_MCS7: - rateSection = 2; - break; + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - case MGN_MCS8: - case MGN_MCS9: - case MGN_MCS10: - case MGN_MCS11: - case MGN_MCS12: - case MGN_MCS13: - case MGN_MCS14: - case MGN_MCS15: - rateSection = 3; - break; + /* loop for each possible tx bandwidth to find minimum limit */ + for (tmp_bw = CHANNEL_WIDTH_20; tmp_bw <= bw; tmp_bw++) { + if (!(ch_width_to_bw_cap(tmp_bw) & bw_bmp)) + continue; - case MGN_MCS16: - case MGN_MCS17: - case MGN_MCS18: - case MGN_MCS19: - case MGN_MCS20: - case MGN_MCS21: - case MGN_MCS22: - case MGN_MCS23: - rateSection = 4; - break; + if (no_sc == _FALSE) { + if (tmp_bw == CHANNEL_WIDTH_20) + tmp_cch = hal_data->cch_20; + else if (tmp_bw == CHANNEL_WIDTH_40) + tmp_cch = hal_data->cch_40; + else if (tmp_bw == CHANNEL_WIDTH_80) + tmp_cch = hal_data->cch_80; + else { + tmp_cch = 0; + rtw_warn_on(1); + } + } - case MGN_MCS24: - case MGN_MCS25: - case MGN_MCS26: - case MGN_MCS27: - case MGN_MCS28: - case MGN_MCS29: - case MGN_MCS30: - case MGN_MCS31: - rateSection = 5; - break; + lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, tmp_bw, tlrs, ntx_idx, tmp_cch, 0); - case MGN_VHT1SS_MCS0: - case MGN_VHT1SS_MCS1: - case MGN_VHT1SS_MCS2: - case MGN_VHT1SS_MCS3: - case MGN_VHT1SS_MCS4: - case MGN_VHT1SS_MCS5: - case MGN_VHT1SS_MCS6: - case MGN_VHT1SS_MCS7: - case MGN_VHT1SS_MCS8: - case MGN_VHT1SS_MCS9: - rateSection = 6; - break; - - case MGN_VHT2SS_MCS0: - case MGN_VHT2SS_MCS1: - case MGN_VHT2SS_MCS2: - case MGN_VHT2SS_MCS3: - case MGN_VHT2SS_MCS4: - case MGN_VHT2SS_MCS5: - case MGN_VHT2SS_MCS6: - case MGN_VHT2SS_MCS7: - case MGN_VHT2SS_MCS8: - case MGN_VHT2SS_MCS9: - rateSection = 7; - break; + if (min_lmt >= lmt) { + min_lmt = lmt; + final_cch = tmp_cch; + final_bw = tmp_bw; + } - case MGN_VHT3SS_MCS0: - case MGN_VHT3SS_MCS1: - case MGN_VHT3SS_MCS2: - case MGN_VHT3SS_MCS3: - case MGN_VHT3SS_MCS4: - case MGN_VHT3SS_MCS5: - case MGN_VHT3SS_MCS6: - case MGN_VHT3SS_MCS7: - case MGN_VHT3SS_MCS8: - case MGN_VHT3SS_MCS9: - rateSection = 8; - break; + } - case MGN_VHT4SS_MCS0: - case MGN_VHT4SS_MCS1: - case MGN_VHT4SS_MCS2: - case MGN_VHT4SS_MCS3: - case MGN_VHT4SS_MCS4: - case MGN_VHT4SS_MCS5: - case MGN_VHT4SS_MCS6: - case MGN_VHT4SS_MCS7: - case MGN_VHT4SS_MCS8: - case MGN_VHT4SS_MCS9: - rateSection = 9; - break; + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); - default: - DBG_871X("Wrong rate 0x%x\n", DataRate); - break; + if (min_lmt != hal_spec->txgi_max) { + /* return diff value */ + min_lmt = min_lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs); } - if (Band == BAND_ON_5G && rateSection == 0) - DBG_871X("Wrong rate 0x%x: No CCK in 5G Band\n", DataRate); - - /*workaround for wrong index combination to obtain tx power limit,*/ - /*OFDM only exists in BW 20M*/ - if (rateSection == 1) - bandwidth = 0; +exit: - /*workaround for wrong index combination to obtain tx power limit,*/ - /*CCK table will only be given in BW 20M*/ - if (rateSection == 0) - bandwidth = 0; + if (0) { + if (final_bw != bw && (IS_HT_RATE(rate) || IS_VHT_RATE(rate))) + RTW_INFO("%s min_lmt: %s ch%u -> %s ch%u\n" + , MGN_RATE_STR(rate) + , ch_width_str(bw), cch + , ch_width_str(final_bw), final_cch); + } - /*workaround for wrong indxe combination to obtain tx power limit,*/ - /*HT on 80M will reference to HT on 40M*/ - if ((rateSection == 2 || rateSection == 3) && Band == BAND_ON_5G && bandwidth == 2) - bandwidth = 1; + return min_lmt; +} - if (Band == BAND_ON_2_4G) - channel = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, Channel); - else if (Band == BAND_ON_5G) - channel = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, Channel); - else if (Band == BAND_ON_BOTH) - /*BAND_ON_BOTH don't care temporarily*/ - - if (band == -1 || regulation == -1 || bandwidth == -1 || - rateSection == -1 || channel == -1) { - /*DBG_871X("Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnlGroup %d]\n",*/ - /* band, regulation, bandwidth, RfPath, rateSection, channelGroup );*/ - - return MAX_POWER_INDEX; - } +static void phy_txpwr_lmt_cck_ofdm_mt_chk(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + struct txpwr_lmt_ent *ent; + _list *cur, *head; + u8 channel, tlrs, ntx_idx; - if (Band == BAND_ON_2_4G) { - s8 limits[10] = {0}; - u8 i = 0; + rfctl->txpwr_lmt_2g_cck_ofdm_state = 0; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + rfctl->txpwr_lmt_5g_cck_ofdm_state = 0; +#endif - if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) - bandwidth = MAX_2_4G_BANDWIDTH_NUM - 1; + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); - for (i = 0; i < MAX_REGULATION_NUM; ++i) - limits[i] = pHalData->TxPwrLimit_2_4G_Original[i][bandwidth][rateSection][channel][RfPath]; + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); - powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : - pHalData->TxPwrLimit_2_4G_Original[regulation][bandwidth][rateSection][channel][RfPath]; + /* check 2G CCK, OFDM state*/ + for (tlrs = TXPWR_LMT_RS_CCK; tlrs <= TXPWR_LMT_RS_OFDM; tlrs++) { + for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) { + if (ent->lmt_2g[CHANNEL_WIDTH_20][tlrs][channel][ntx_idx] != hal_spec->txgi_max) { + if (tlrs == TXPWR_LMT_RS_CCK) + rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_CCK_1T << ntx_idx; + else + rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx; + break; + } + } + } + } - } else if (Band == BAND_ON_5G) { - s8 limits[10] = {0}; - u8 i = 0; + /* if 2G OFDM multi-TX is not defined, reference HT20 */ + for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) { + for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + if (rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)) + continue; + ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM][channel][ntx_idx] = + ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT][channel][ntx_idx]; + } + } - for (i = 0; i < MAX_REGULATION_NUM; ++i) - limits[i] = pHalData->TxPwrLimit_5G_Original[i][bandwidth][rateSection][channel][RfPath]; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + /* check 5G OFDM state*/ + for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { + if (ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] != hal_spec->txgi_max) { + rfctl->txpwr_lmt_5g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx; + break; + } + } + } - powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : - pHalData->TxPwrLimit_5G_Original[regulation][bandwidth][rateSection][channel][RfPath]; - } else - DBG_871X("No power limit table of the specified band\n"); - - /*combine 5G VHT & HT rate*/ - /*5G 20M and 40M HT and VHT can cross reference*/ - /* - if (Band == BAND_ON_5G && powerLimit == MAX_POWER_INDEX) { - if (bandwidth == 0 || bandwidth == 1) { - if (rateSection == 2) - powerLimit = pHalData->TxPwrLimit_5G_Original[regulation] - [bandwidth][4][channelGroup][RfPath]; - else if (rateSection == 4) - powerLimit = pHalData->TxPwrLimit_5G_Original[regulation] - [bandwidth][2][channelGroup][RfPath]; - else if (rateSection == 3) - powerLimit = pHalData->TxPwrLimit_5G_Original[regulation] - [bandwidth][5][channelGroup][RfPath]; - else if (rateSection == 5) - powerLimit = pHalData->TxPwrLimit_5G_Original[regulation] - [bandwidth][3][channelGroup][RfPath]; + for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { + for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + if (rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)) + continue; + /* if 5G OFDM multi-TX is not defined, reference HT20 */ + ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] = + ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT - 1][channel][ntx_idx]; + } } +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ } - */ - /*DBG_871X("TxPwrLmt[Regulation %d][Band %d][BW %d][RFPath %d][Rate 0x%x][Chnl %d] = %d\n",*/ - /* regulation, pHalData->current_band_type, Bandwidth, RfPath, DataRate, Channel, powerLimit);*/ - return powerLimit; } -#endif - -VOID -phy_CrossReferenceHTAndVHTTxPowerLimit( - IN PADAPTER pAdapter -) +#ifdef CONFIG_IEEE80211_BAND_5GHZ +static void phy_txpwr_lmt_cross_ref_ht_vht(_adapter *adapter) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u8 regulation, bw, channel, rs, ref_rs; + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + struct txpwr_lmt_ent *ent; + _list *cur, *head; + u8 bw, channel, tlrs, ref_tlrs, ntx_idx; int ht_ref_vht_5g_20_40 = 0; int vht_ref_ht_5g_20_40 = 0; int ht_has_ref_5g_20_40 = 0; int vht_has_ref_5g_20_40 = 0; - pHalData->tx_pwr_lmt_5g_20_40_ref = 0; + rfctl->txpwr_lmt_5g_20_40_ref = 0; + + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); - for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { - for (rs = 0; rs < MAX_RATE_SECTION_NUM; ++rs) { + for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; ++tlrs) { /* 5G 20M 40M VHT and HT can cross reference */ if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) { - if (rs == HT_1SS) - ref_rs = VHT_1SS; - else if (rs == HT_2SS) - ref_rs = VHT_2SS; - else if (rs == HT_3SS) - ref_rs = VHT_3SS; - else if (rs == HT_4SS) - ref_rs = VHT_4SS; - else if (rs == VHT_1SS) - ref_rs = HT_1SS; - else if (rs == VHT_2SS) - ref_rs = HT_2SS; - else if (rs == VHT_3SS) - ref_rs = HT_3SS; - else if (rs == VHT_4SS) - ref_rs = HT_4SS; + if (tlrs == TXPWR_LMT_RS_HT) + ref_tlrs = TXPWR_LMT_RS_VHT; + else if (tlrs == TXPWR_LMT_RS_VHT) + ref_tlrs = TXPWR_LMT_RS_HT; else continue; - if (pHalData->TxPwrLimit_5G[regulation][bw][ref_rs][channel][RF_PATH_A] == MAX_POWER_INDEX) - continue; + for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { - if (IS_HT_RATE_SECTION(rs)) - ht_has_ref_5g_20_40++; - else if (IS_VHT_RATE_SECTION(rs)) - vht_has_ref_5g_20_40++; - else - continue; + if (ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx] == hal_spec->txgi_max) + continue; - if (pHalData->TxPwrLimit_5G[regulation][bw][rs][channel][RF_PATH_A] != MAX_POWER_INDEX) - continue; + if (tlrs == TXPWR_LMT_RS_HT) + ht_has_ref_5g_20_40++; + else if (tlrs == TXPWR_LMT_RS_VHT) + vht_has_ref_5g_20_40++; + else + continue; - if (IS_HT_RATE_SECTION(rs) && IS_VHT_RATE_SECTION(ref_rs)) - ht_ref_vht_5g_20_40++; - else if (IS_VHT_RATE_SECTION(rs) && IS_HT_RATE_SECTION(ref_rs)) - vht_ref_ht_5g_20_40++; + if (ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] != hal_spec->txgi_max) + continue; - if (0) - RTW_INFO("reg:%u, bw:%u, ch:%u, %s ref %s\n" - , regulation, bw, channel - , rate_section_str(rs), rate_section_str(ref_rs)); + if (tlrs == TXPWR_LMT_RS_HT && ref_tlrs == TXPWR_LMT_RS_VHT) + ht_ref_vht_5g_20_40++; + else if (tlrs == TXPWR_LMT_RS_VHT && ref_tlrs == TXPWR_LMT_RS_HT) + vht_ref_ht_5g_20_40++; - pHalData->TxPwrLimit_5G[regulation][bw][rs][channel][RF_PATH_A] = - pHalData->TxPwrLimit_5G[regulation][bw][ref_rs][channel][RF_PATH_A]; + if (0) + RTW_INFO("reg:%s, bw:%u, ch:%u, %s-%uT ref %s-%uT\n" + , ent->regd_name, bw, channel + , txpwr_lmt_rs_str(tlrs), ntx_idx + 1 + , txpwr_lmt_rs_str(ref_tlrs), ntx_idx + 1); + + ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] = + ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx]; + } } } @@ -3370,178 +3302,326 @@ phy_CrossReferenceHTAndVHTTxPowerLimit( if (0) { RTW_INFO("ht_ref_vht_5g_20_40:%d, ht_has_ref_5g_20_40:%d\n", ht_ref_vht_5g_20_40, ht_has_ref_5g_20_40); - RTW_INFO("vht_ref_hht_5g_20_40:%d, vht_has_ref_5g_20_40:%d\n", vht_ref_ht_5g_20_40, vht_has_ref_5g_20_40); + RTW_INFO("vht_ref_ht_5g_20_40:%d, vht_has_ref_5g_20_40:%d\n", vht_ref_ht_5g_20_40, vht_has_ref_5g_20_40); } /* 5G 20M&40M HT all come from VHT*/ if (ht_ref_vht_5g_20_40 && ht_has_ref_5g_20_40 == ht_ref_vht_5g_20_40) - pHalData->tx_pwr_lmt_5g_20_40_ref |= TX_PWR_LMT_REF_HT_FROM_VHT; + rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_HT_FROM_VHT; /* 5G 20M&40M VHT all come from HT*/ if (vht_ref_ht_5g_20_40 && vht_has_ref_5g_20_40 == vht_ref_ht_5g_20_40) - pHalData->tx_pwr_lmt_5g_20_40_ref |= TX_PWR_LMT_REF_VHT_FROM_HT; + rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_VHT_FROM_HT; } +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ -VOID -PHY_ConvertTxPowerLimitToPowerIndex( - IN PADAPTER Adapter -) +#ifndef DBG_TXPWR_LMT_BAND_CHK +#define DBG_TXPWR_LMT_BAND_CHK 0 +#endif + +#if DBG_TXPWR_LMT_BAND_CHK +/* check if larger bandwidth limit is less than smaller bandwidth for HT & VHT rate */ +void phy_txpwr_limit_bandwidth_chk(_adapter *adapter) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 base; - u8 regulation, bw, channel, rateSection; - s8 tempValue = 0, tempPwrLmt = 0; - u8 rfPath = 0; + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 band, bw, path, tlrs, ntx_idx, cch, offset, scch; + u8 ch_num, n, i; - if (pHalData->odmpriv.phy_reg_pg_value_type != PHY_REG_PG_EXACT_VALUE) { - rtw_warn_on(1); - return; - } + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; - phy_CrossReferenceHTAndVHTTxPowerLimit(Adapter); + for (bw = CHANNEL_WIDTH_40; bw <= CHANNEL_WIDTH_80; bw++) { + if (bw >= CHANNEL_WIDTH_160) + continue; + if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80) + continue; - for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + if (band == BAND_ON_2_4G) + ch_num = center_chs_2g_num(bw); + else + ch_num = center_chs_5g_num(bw); - for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) { + if (ch_num == 0) { + rtw_warn_on(1); + break; + } - for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) { + for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; tlrs++) { - for (rateSection = CCK; rateSection <= HT_4SS; ++rateSection) { - tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][RF_PATH_A]; + if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT) + continue; + if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK) + continue; + if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)) + continue; + if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT) + continue; + if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + continue; - if (tempPwrLmt != MAX_POWER_INDEX) { + for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) { + struct txpwr_lmt_ent *ent; + _list *cur, *head; - for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH; ++rfPath) { - base = PHY_GetTxPowerByRateBase(Adapter, BAND_ON_2_4G, rfPath, rate_section_to_tx_num(rateSection), rateSection); - tempValue = tempPwrLmt - base; - pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue; - } + if (ntx_idx >= hal_spec->tx_nss_num) + continue; + + /* bypass CCK multi-TX is not defined */ + if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) { + if (band == BAND_ON_2_4G + && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx))) + continue; } - } - } - } - } - if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) { + /* bypass OFDM multi-TX is not defined */ + if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) { + if (band == BAND_ON_2_4G + && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))) + continue; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (band == BAND_ON_5G + && !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))) + continue; + #endif + } - for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + /* bypass 5G 20M, 40M pure reference */ + #ifdef CONFIG_IEEE80211_BAND_5GHZ + if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) { + if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) { + if (tlrs == TXPWR_LMT_RS_HT) + continue; + } else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) { + if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40) + continue; + } + } + #endif - for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { + for (n = 0; n < ch_num; n++) { + u8 cch_by_bw[3]; + u8 offset_by_bw; /* bitmap, 0 for lower, 1 for upper */ + u8 bw_pos; + s8 lmt[3]; - for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { + if (band == BAND_ON_2_4G) + cch = center_chs_2g(bw, n); + else + cch = center_chs_5g(bw, n); - for (rateSection = OFDM; rateSection <= VHT_4SS; ++rateSection) { - tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][RF_PATH_A]; + if (cch == 0) { + rtw_warn_on(1); + break; + } - if (tempPwrLmt != MAX_POWER_INDEX) { + _rtw_memset(cch_by_bw, 0, 3); + cch_by_bw[bw] = cch; + offset_by_bw = 0x01; + + do { + for (bw_pos = bw; bw_pos >= CHANNEL_WIDTH_40; bw_pos--) + cch_by_bw[bw_pos - 1] = rtw_get_scch_by_cch_offset(cch_by_bw[bw_pos], bw_pos, offset_by_bw & BIT(bw_pos) ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER); + + head = &rfctl->txpwr_lmt_list; + cur = get_next(head); + while ((rtw_end_of_queue_search(head, cur)) == _FALSE) { + ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list); + cur = get_next(cur); + + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) + lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0); + + for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--) + if (lmt[bw_pos] > lmt[bw_pos - 1]) + break; + if (bw_pos == CHANNEL_WIDTH_20) + continue; + + RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:" + , band_str(band) + , ch_width_str(bw) + , txpwr_lmt_rs_str(tlrs) + , ntx_idx + 1 + , ent->regd_name + ); + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) + _RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]); + _RTW_PRINT_SEL(RTW_DBGDUMP, "limit:"); + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) { + if (lmt[bw_pos] == hal_spec->txgi_max) + _RTW_PRINT_SEL(RTW_DBGDUMP, "N/A "); + else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */ + _RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm); + else if (lmt[bw_pos] % hal_spec->txgi_pdbm) + _RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm); + else + _RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm); + } + _RTW_PRINT_SEL(RTW_DBGDUMP, "\n"); + } + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) + lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0); - for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH; ++rfPath) { - base = PHY_GetTxPowerByRateBase(Adapter, BAND_ON_5G, rfPath, rate_section_to_tx_num(rateSection), rateSection); - tempValue = tempPwrLmt - base; - pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][rfPath] = tempValue; + for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--) + if (lmt[bw_pos] > lmt[bw_pos - 1]) + break; + if (bw_pos != CHANNEL_WIDTH_20) { + RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:" + , band_str(band) + , ch_width_str(bw) + , txpwr_lmt_rs_str(tlrs) + , ntx_idx + 1 + , regd_str(TXPWR_LMT_WW) + ); + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) + _RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]); + _RTW_PRINT_SEL(RTW_DBGDUMP, "limit:"); + for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) { + if (lmt[bw_pos] == hal_spec->txgi_max) + _RTW_PRINT_SEL(RTW_DBGDUMP, "N/A "); + else if (lmt[bw_pos] > -hal_spec->txgi_pdbm && lmt[bw_pos] < 0) /* -1 < value < 0 */ + _RTW_PRINT_SEL(RTW_DBGDUMP, "-0.%d", (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm); + else if (lmt[bw_pos] % hal_spec->txgi_pdbm) + _RTW_PRINT_SEL(RTW_DBGDUMP, "%2d.%d ", lmt[bw_pos] / hal_spec->txgi_pdbm, (rtw_abs(lmt[bw_pos]) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm); + else + _RTW_PRINT_SEL(RTW_DBGDUMP, "%2d ", lmt[bw_pos] / hal_spec->txgi_pdbm); + } + _RTW_PRINT_SEL(RTW_DBGDUMP, "\n"); } - } - } - } - } - } - } + + offset_by_bw += 2; + if (offset_by_bw & BIT(bw + 1)) + break; + } while (1); /* loop for all ch combinations */ + } /* loop for center channels */ + } /* loop fo each ntx_idx */ + } /* loop for tlrs */ + } /* loop for bandwidth */ + } /* loop for band */ +} +#endif /* DBG_TXPWR_LMT_BAND_CHK */ + +static void phy_txpwr_lmt_post_hdl(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + _irqL irqL; + + _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + phy_txpwr_lmt_cross_ref_ht_vht(adapter); +#endif + phy_txpwr_lmt_cck_ofdm_mt_chk(adapter); + +#if DBG_TXPWR_LMT_BAND_CHK + phy_txpwr_limit_bandwidth_chk(adapter); +#endif + + _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL); } -/* -* PHY_InitTxPowerLimit - Set all hal_data.TxPwrLimit_2_4G, TxPwrLimit_5G array to MAX_POWER_INDEX -*/ -VOID -PHY_InitTxPowerLimit( - IN PADAPTER Adapter +BOOLEAN +GetS1ByteIntegerFromStringInDecimal( + IN char *str, + IN OUT s8 *val ) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 i, j, k, l, m; - - for (i = 0; i < MAX_REGULATION_NUM; ++i) - for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) - for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) - for (m = 0; m < CENTER_CH_2G_NUM; ++m) - for (l = 0; l < MAX_RF_PATH; ++l) - pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX; - - for (i = 0; i < MAX_REGULATION_NUM; ++i) - for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j) - for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) - for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m) - for (l = 0; l < MAX_RF_PATH; ++l) - pHalData->TxPwrLimit_5G[i][j][k][m][l] = MAX_POWER_INDEX; + u8 negative = 0; + u16 i = 0; + + *val = 0; + + while (str[i] != '\0') { + if (i == 0 && (str[i] == '+' || str[i] == '-')) { + if (str[i] == '-') + negative = 1; + } else if (str[i] >= '0' && str[i] <= '9') { + *val *= 10; + *val += (str[i] - '0'); + } else + return _FALSE; + ++i; + } + + if (negative) + *val = -*val; + + return _TRUE; } +#endif /* CONFIG_TXPWR_LIMIT */ /* * phy_set_tx_power_limit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm */ VOID phy_set_tx_power_limit( - IN struct PHY_DM_STRUCT *pDM_Odm, + IN struct dm_struct *pDM_Odm, IN u8 *Regulation, IN u8 *Band, IN u8 *Bandwidth, IN u8 *RateSection, - IN u8 *RfPath, + IN u8 *ntx, IN u8 *Channel, IN u8 *PowerLimit ) { +#ifdef CONFIG_TXPWR_LIMIT PADAPTER Adapter = pDM_Odm->adapter; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 regulation = 0, bandwidth = 0, rateSection = 0, channel; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter); + u8 band = 0, bandwidth = 0, tlrs = 0, channel; + u8 ntx_idx; s8 powerLimit = 0, prevPowerLimit, channelIndex; + s8 ww_lmt_val = phy_txpwr_ww_lmt_value(Adapter); if (0) - RTW_INFO("Index of power limit table [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s][val %s]\n" - , Band, Regulation, Bandwidth, RateSection, RfPath, Channel, PowerLimit); + RTW_INFO("Index of power limit table [regulation %s][band %s][bw %s][rate section %s][ntx %s][chnl %s][val %s]\n" + , Regulation, Band, Bandwidth, RateSection, ntx, Channel, PowerLimit); - if (GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel) == _FALSE - || GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit) == _FALSE + if (GetU1ByteIntegerFromStringInDecimal((char *)Channel, &channel) == _FALSE + || GetS1ByteIntegerFromStringInDecimal((char *)PowerLimit, &powerLimit) == _FALSE ) { RTW_PRINT("Illegal index of power limit table [ch %s][val %s]\n", Channel, PowerLimit); return; } - powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit; + if (powerLimit != ww_lmt_val) { + if (powerLimit < -hal_spec->txgi_max || powerLimit > hal_spec->txgi_max) + RTW_PRINT("Illegal power limit value [ch %s][val %s]\n", Channel, PowerLimit); + + if (powerLimit > hal_spec->txgi_max) + powerLimit = hal_spec->txgi_max; + else if (powerLimit < -hal_spec->txgi_max) + powerLimit = ww_lmt_val + 1; + } - if (eqNByte(Regulation, (u8 *)("FCC"), 3)) - regulation = TXPWR_LMT_FCC; - else if (eqNByte(Regulation, (u8 *)("MKK"), 3)) - regulation = TXPWR_LMT_MKK; - else if (eqNByte(Regulation, (u8 *)("ETSI"), 4)) - regulation = TXPWR_LMT_ETSI; - else if (eqNByte(Regulation, (u8 *)("WW13"), 4)) - regulation = TXPWR_LMT_WW; + if (eqNByte(RateSection, (u8 *)("CCK"), 3)) + tlrs = TXPWR_LMT_RS_CCK; + else if (eqNByte(RateSection, (u8 *)("OFDM"), 4)) + tlrs = TXPWR_LMT_RS_OFDM; + else if (eqNByte(RateSection, (u8 *)("HT"), 2)) + tlrs = TXPWR_LMT_RS_HT; + else if (eqNByte(RateSection, (u8 *)("VHT"), 3)) + tlrs = TXPWR_LMT_RS_VHT; else { - RTW_PRINT("unknown regulation:%s", Regulation); + RTW_PRINT("Wrong rate section:%s\n", RateSection); return; } - if (eqNByte(RateSection, (u8 *)("CCK"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2)) - rateSection = CCK; - else if (eqNByte(RateSection, (u8 *)("OFDM"), 4) && eqNByte(RfPath, (u8 *)("1T"), 2)) - rateSection = OFDM; - else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("1T"), 2)) - rateSection = HT_1SS; - else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("2T"), 2)) - rateSection = HT_2SS; - else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("3T"), 2)) - rateSection = HT_3SS; - else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("4T"), 2)) - rateSection = HT_4SS; - else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2)) - rateSection = VHT_1SS; - else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("2T"), 2)) - rateSection = VHT_2SS; - else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("3T"), 2)) - rateSection = VHT_3SS; - else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("4T"), 2)) - rateSection = VHT_4SS; + if (eqNByte(ntx, (u8 *)("1T"), 2)) + ntx_idx = RF_1TX; + else if (eqNByte(ntx, (u8 *)("2T"), 2)) + ntx_idx = RF_2TX; + else if (eqNByte(ntx, (u8 *)("3T"), 2)) + ntx_idx = RF_3TX; + else if (eqNByte(ntx, (u8 *)("4T"), 2)) + ntx_idx = RF_4TX; else { - RTW_PRINT("Wrong rate section: (%s,%s)\n", RateSection, RfPath); + RTW_PRINT("Wrong tx num:%s\n", ntx); return; } @@ -3551,12 +3631,15 @@ phy_set_tx_power_limit( bandwidth = CHANNEL_WIDTH_40; else if (eqNByte(Bandwidth, (u8 *)("80M"), 3)) bandwidth = CHANNEL_WIDTH_80; + else if (eqNByte(Bandwidth, (u8 *)("160M"), 4)) + bandwidth = CHANNEL_WIDTH_160; else { RTW_PRINT("unknown bandwidth: %s\n", Bandwidth); return; } if (eqNByte(Band, (u8 *)("2.4G"), 4)) { + band = BAND_ON_2_4G; channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel); if (channelIndex == -1) { @@ -3569,20 +3652,11 @@ phy_set_tx_power_limit( return; } - prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]; - - if (prevPowerLimit != MAX_POWER_INDEX) - RTW_PRINT("duplicate tx power limit combination [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s]\n" - , Band, Regulation, Bandwidth, RateSection, RfPath, Channel); - - if (powerLimit < prevPowerLimit) - pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit; - - if (0) - RTW_INFO("2.4G Band value : [regulation %d][bw %d][rate_section %d][chnl %d][val %d]\n" - , regulation, bandwidth, rateSection, channelIndex, pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A]); - } else if (eqNByte(Band, (u8 *)("5G"), 2)) { - + rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit); + } +#ifdef CONFIG_IEEE80211_BAND_5GHZ + else if (eqNByte(Band, (u8 *)("5G"), 2)) { + band = BAND_ON_5G; channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel); if (channelIndex == -1) { @@ -3590,30 +3664,22 @@ phy_set_tx_power_limit( return; } - prevPowerLimit = pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]; - - if (prevPowerLimit != MAX_POWER_INDEX) - RTW_PRINT("duplicate tx power limit combination [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s]\n" - , Band, Regulation, Bandwidth, RateSection, RfPath, Channel); - - if (powerLimit < prevPowerLimit) - pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit; - - if (0) - RTW_INFO("5G Band value : [regulation %d][bw %d][rate_section %d][chnl %d][val %d]\n" - , regulation, bandwidth, rateSection, channel, pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]); - } else { - RTW_PRINT("Cannot recognize the band info in %s\n", Band); + rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit); + } +#endif + else { + RTW_PRINT("unknown/unsupported band:%s\n", Band); return; } +#endif } u8 phy_get_tx_power_index( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, + IN enum channel_width BandWidth, IN u8 Channel ) { @@ -3624,46 +3690,11 @@ VOID PHY_SetTxPowerIndex( IN PADAPTER pAdapter, IN u32 PowerIndex, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ) { - if (IS_HARDWARE_TYPE_8814A(pAdapter)) { -#if (RTL8814A_SUPPORT == 1) - PHY_SetTxPowerIndex_8814A(pAdapter, PowerIndex, RFPath, Rate); -#endif - } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) { -#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) - PHY_SetTxPowerIndex_8812A(pAdapter, PowerIndex, RFPath, Rate); -#endif - } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { -#if (RTL8723B_SUPPORT == 1) - PHY_SetTxPowerIndex_8723B(pAdapter, PowerIndex, RFPath, Rate); -#endif - } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { -#if (RTL8703B_SUPPORT == 1) - PHY_SetTxPowerIndex_8703B(pAdapter, PowerIndex, RFPath, Rate); -#endif - } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) { -#if (RTL8723D_SUPPORT == 1) - PHY_SetTxPowerIndex_8723D(pAdapter, PowerIndex, RFPath, Rate); -#endif - } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { -#if (RTL8192E_SUPPORT == 1) - PHY_SetTxPowerIndex_8192E(pAdapter, PowerIndex, RFPath, Rate); -#endif - } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) { -#if (RTL8188E_SUPPORT == 1) - PHY_SetTxPowerIndex_8188E(pAdapter, PowerIndex, RFPath, Rate); -#endif - } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { -#if (RTL8188F_SUPPORT == 1) - PHY_SetTxPowerIndex_8188F(pAdapter, PowerIndex, RFPath, Rate); -#endif - } else if (IS_HARDWARE_TYPE_8822B(pAdapter)) - rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate); - else if (IS_HARDWARE_TYPE_8821C(pAdapter)) - rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate); + rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate); } void dump_tx_power_idx_title(void *sel, _adapter *adapter) @@ -3678,8 +3709,8 @@ void dump_tx_power_idx_title(void *sel, _adapter *adapter) _RTW_PRINT_SEL(sel, ", cch40:%u", hal_data->cch_40); _RTW_PRINT_SEL(sel, ", cch20:%u\n", hal_data->cch_20); - RTW_PRINT_SEL(sel, "%-4s %-9s %-3s %-4s %-3s %-4s %-4s %-3s %-5s\n" - , "path", "rate", "pwr", "base", "", "(byr", "lmt)", "tpt", "ebias"); + RTW_PRINT_SEL(sel, "%-4s %-9s %2s %-3s %-4s %-3s %-4s %-4s %-3s %-5s\n" + , "path", "rate", "", "pwr", "base", "", "(byr", "lmt)", "tpt", "ebias"); } void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs) @@ -3712,8 +3743,8 @@ void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs for (i = 0; i < rates_by_sections[rs].rate_num; i++) { power_idx = rtw_hal_get_tx_power_index(adapter, rfpath, rates_by_sections[rs].rates[i], bw, cch, &tic); - RTW_PRINT_SEL(sel, "%4c %9s %3u %4u %3d (%3d %3d) %3d %5d\n" - , rf_path_char(rfpath), MGN_RATE_STR(rates_by_sections[rs].rates[i]) + RTW_PRINT_SEL(sel, "%4c %9s %uT %3u %4u %3d (%3d %3d) %3d %5d\n" + , rf_path_char(rfpath), MGN_RATE_STR(rates_by_sections[rs].rates[i]), tic.ntx_idx + 1 , power_idx, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias); } } @@ -3733,9 +3764,12 @@ bool phy_is_tx_power_limit_needed(_adapter *adapter) HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); +#ifdef CONFIG_TXPWR_LIMIT if (regsty->RegEnableTxPowerLimit == 1 || (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1)) return _TRUE; +#endif + return _FALSE; } @@ -3797,14 +3831,17 @@ int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file) return ret; } +#ifdef CONFIG_TXPWR_LIMIT int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file) { HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); int ret = _FAIL; hal_data->txpwr_limit_loaded = 0; - PHY_InitTxPowerLimit(adapter); + rtw_regd_exc_list_free(rfctl); + rtw_txpwr_lmt_list_free(rfctl); if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) { RTW_ERR("%s():Read Tx power limit before target tx power is specify\n", __func__); @@ -3821,7 +3858,7 @@ int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file) #endif #ifdef CONFIG_EMBEDDED_FWIMG - if (HAL_STATUS_SUCCESS == odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, (enum odm_rf_radio_path_e)0)) { + if (odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, RF_PATH_A) == HAL_STATUS_SUCCESS) { RTW_INFO("default power limit loaded\n"); hal_data->txpwr_limit_from_file = 0; goto post_hdl; @@ -3832,13 +3869,15 @@ int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file) goto exit; post_hdl: - PHY_ConvertTxPowerLimitToPowerIndex(adapter); + phy_txpwr_lmt_post_hdl(adapter); + rtw_txpwr_init_regd(rfctl); hal_data->txpwr_limit_loaded = 1; ret = _SUCCESS; exit: return ret; } +#endif /* CONFIG_TXPWR_LIMIT */ void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file) { @@ -3853,8 +3892,10 @@ void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file) ) phy_load_tx_power_by_rate(adapter, chk_file); +#ifdef CONFIG_TXPWR_LIMIT if (phy_is_tx_power_limit_needed(adapter)) phy_load_tx_power_limit(adapter, chk_file); +#endif } inline void phy_reload_tx_power_ext_info(_adapter *adapter) @@ -3922,12 +3963,15 @@ void dump_target_tx_power(void *sel, _adapter *adapter) if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) continue; - target = PHY_GetTxPowerByRateBase(adapter, band, path, rate_section_to_tx_num(rs), rs); + target = PHY_GetTxPowerByRateBase(adapter, band, path, rs); - if (target % 2) - _RTW_PRINT_SEL(sel, "%7s: %2d.5\n", rate_section_str(rs), target / 2); - else - _RTW_PRINT_SEL(sel, "%7s: %4d\n", rate_section_str(rs), target / 2); + if (target % hal_spec->txgi_pdbm) { + _RTW_PRINT_SEL(sel, "%7s: %2d.%d\n", rate_section_str(rs) + , target / hal_spec->txgi_pdbm, (target % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm); + } else { + _RTW_PRINT_SEL(sel, "%7s: %5d\n", rate_section_str(rs) + , target / hal_spec->txgi_pdbm); + } } } } @@ -3971,27 +4015,28 @@ void dump_tx_power_by_rate(void *sel, _adapter *adapter) else max_rate_num = 8; rate_num = rate_section_rate_num(rs); - base = PHY_GetTxPowerByRateBase(adapter, band, path, tx_num, rs); + base = PHY_GetTxPowerByRateBase(adapter, band, path, rs); RTW_PRINT_SEL(sel, "%7s: ", rate_section_str(rs)); /* dump power by rate in db */ for (n = rate_num - 1; n >= 0; n--) { - by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, tx_num, rates_by_sections[rs].rates[n]); + by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]); - if ((base + by_rate_offset) % 2) - _RTW_PRINT_SEL(sel, "%2d.5 ", (base + by_rate_offset) / 2); - else - _RTW_PRINT_SEL(sel, "%4d ", (base + by_rate_offset) / 2); + if ((base + by_rate_offset) % hal_spec->txgi_pdbm) { + _RTW_PRINT_SEL(sel, "%2d.%d ", (base + by_rate_offset) / hal_spec->txgi_pdbm + , ((base + by_rate_offset) % hal_spec->txgi_pdbm) * 100 / hal_spec->txgi_pdbm); + } else + _RTW_PRINT_SEL(sel, "%5d ", (base + by_rate_offset) / hal_spec->txgi_pdbm); } for (n = 0; n < max_rate_num - rate_num; n++) - _RTW_PRINT_SEL(sel, "%4s ", ""); + _RTW_PRINT_SEL(sel, "%5s ", ""); _RTW_PRINT_SEL(sel, "|"); /* dump power by rate in offset */ for (n = rate_num - 1; n >= 0; n--) { - by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, tx_num, rates_by_sections[rs].rates[n]); + by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]); _RTW_PRINT_SEL(sel, "%3d ", by_rate_offset); } RTW_PRINT_SEL(sel, "\n"); @@ -4001,181 +4046,6 @@ void dump_tx_power_by_rate(void *sel, _adapter *adapter) } } -void dump_tx_power_limit(void *sel, _adapter *adapter) -{ - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); - - int bw, band, ch_num, rs, i, path; - u8 ch, n, rd, rfpath_num; - - if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) - RTW_PRINT_SEL(sel, "tx_pwr_lmt_5g_20_40_ref:0x%02x\n", hal_data->tx_pwr_lmt_5g_20_40_ref); - - for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { - if (!hal_is_band_support(adapter, band)) - continue; - - rd = (band == BAND_ON_2_4G ? hal_data->Regulation2_4G : hal_data->Regulation5G); - rfpath_num = (band == BAND_ON_2_4G ? hal_spec->rfpath_num_2g : hal_spec->rfpath_num_5g); - - for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) { - - if (bw >= CHANNEL_WIDTH_160) - break; - if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80) - break; - - if (band == BAND_ON_2_4G) - ch_num = CENTER_CH_2G_NUM; - else - ch_num = center_chs_5g_num(bw); - - if (ch_num == 0) { - rtw_warn_on(1); - break; - } - - for (rs = 0; rs < RATE_SECTION_NUM; rs++) { - if (band == BAND_ON_2_4G && IS_VHT_RATE_SECTION(rs)) - continue; - if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) - continue; - if (bw > CHANNEL_WIDTH_20 && (IS_CCK_RATE_SECTION(rs) || IS_OFDM_RATE_SECTION(rs))) - continue; - if (bw > CHANNEL_WIDTH_40 && IS_HT_RATE_SECTION(rs)) - continue; - - if (rate_section_to_tx_num(rs) >= hal_spec->tx_nss_num) - continue; - - if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) - continue; - - /* by pass 5G 20M, 40M pure reference */ - if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) { - if (hal_data->tx_pwr_lmt_5g_20_40_ref == TX_PWR_LMT_REF_HT_FROM_VHT) { - if (IS_HT_RATE_SECTION(rs)) - continue; - } else if (hal_data->tx_pwr_lmt_5g_20_40_ref == TX_PWR_LMT_REF_VHT_FROM_HT) { - if (IS_VHT_RATE_SECTION(rs) && bw <= CHANNEL_WIDTH_40) - continue; - } - } - - RTW_PRINT_SEL(sel, "[%s][%s][%s]\n" - , band_str(band) - , ch_width_str(bw) - , rate_section_str(rs) - ); - - /* header for limit in db */ - RTW_PRINT_SEL(sel, "%3s %5s %5s %5s %5s " - , "ch" - , (rd == TXPWR_LMT_FCC ? "*FCC" : "FCC") - , (rd == TXPWR_LMT_ETSI ? "*ETSI" : "ETSI") - , (rd == TXPWR_LMT_MKK ? "*MKK" : "MKK") - , (rd == TXPWR_LMT_WW ? "*WW" : "WW") - ); - - /* header for limit offset */ - for (path = 0; path < RF_PATH_MAX; path++) { - if (path >= rfpath_num) - break; - _RTW_PRINT_SEL(sel, "|%3c %3c %3c %3c " - , (rd == TXPWR_LMT_FCC ? rf_path_char(path) : ' ') - , (rd == TXPWR_LMT_ETSI ? rf_path_char(path) : ' ') - , (rd == TXPWR_LMT_MKK ? rf_path_char(path) : ' ') - , (rd == TXPWR_LMT_WW ? rf_path_char(path) : ' ') - ); - } - _RTW_PRINT_SEL(sel, "\n"); - - for (n = 0; n < ch_num; n++) { - s8 limit_idx[RF_PATH_MAX][MAX_REGULATION_NUM]; - s8 limit_offset[MAX_REGULATION_NUM]; - u8 base; - - if (band == BAND_ON_2_4G) - ch = n + 1; - else - ch = center_chs_5g(bw, n); - - if (ch == 0) { - rtw_warn_on(1); - break; - } - - /* dump limit in db (calculate from path A) */ - limit_offset[0] = PHY_GetTxPowerLimit_no_sc(adapter, 3, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* FCC */ - limit_offset[1] = PHY_GetTxPowerLimit_no_sc(adapter, 1, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* ETSI */ - limit_offset[2] = PHY_GetTxPowerLimit_no_sc(adapter, 2, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* MKK */ - limit_offset[3] = PHY_GetTxPowerLimit_no_sc(adapter, 4, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* WW */ - - base = PHY_GetTxPowerByRateBase(adapter, band, RF_PATH_A, rate_section_to_tx_num(rs), rs); - - RTW_PRINT_SEL(sel, "%3u ", ch); - for (i = 0; i < MAX_REGULATION_NUM; i++) { - if (limit_offset[i] == MAX_POWER_INDEX) { - limit_idx[0][i] = MAX_POWER_INDEX; - _RTW_PRINT_SEL(sel, "%5s ", "NA"); - } else { - limit_idx[0][i] = limit_offset[i] + base; - if ((limit_offset[i] + base) % 2) - _RTW_PRINT_SEL(sel, "%3d.5 ", (limit_offset[i] + base) / 2); - else - _RTW_PRINT_SEL(sel, "%5d ", (limit_offset[i] + base) / 2); - } - } - - /* dump limit offset of each path */ - for (path = 0; path < RF_PATH_MAX; path++) { - if (path >= rfpath_num) - break; - limit_offset[0] = PHY_GetTxPowerLimit_no_sc(adapter, 3, band, bw, path, rates_by_sections[rs].rates[0], ch); /* FCC */ - limit_offset[1] = PHY_GetTxPowerLimit_no_sc(adapter, 1, band, bw, path, rates_by_sections[rs].rates[0], ch); /* ETSI */ - limit_offset[2] = PHY_GetTxPowerLimit_no_sc(adapter, 2, band, bw, path, rates_by_sections[rs].rates[0], ch); /* MKK */ - limit_offset[3] = PHY_GetTxPowerLimit_no_sc(adapter, 4, band, bw, path, rates_by_sections[rs].rates[0], ch); /* WW */ - - base = PHY_GetTxPowerByRateBase(adapter, band, path, rate_section_to_tx_num(rs), rs); - - _RTW_PRINT_SEL(sel, "|"); - for (i = 0; i < MAX_REGULATION_NUM; i++) { - if (limit_offset[i] == MAX_POWER_INDEX) { - limit_idx[path][i] = MAX_POWER_INDEX; - _RTW_PRINT_SEL(sel, "%3s ", "NA"); - } else { - limit_idx[path][i] = limit_offset[i] + base; - _RTW_PRINT_SEL(sel, "%3d ", limit_offset[i]); - } - } - } - - /* compare limit_idx of each path, print 'x' when mismatch */ - if (rfpath_num > 1) { - for (i = 0; i < MAX_REGULATION_NUM; i++) { - for (path = 0; path < RF_PATH_MAX; path++) { - if (path >= rfpath_num) - break; - if (limit_idx[path][i] != limit_idx[(path + 1) % rfpath_num][i]) - break; - } - if (path >= rfpath_num) - _RTW_PRINT_SEL(sel, " "); - else - _RTW_PRINT_SEL(sel, "x"); - } - } - _RTW_PRINT_SEL(sel, "\n"); - - } - RTW_PRINT_SEL(sel, "\n"); - } /* loop for rate sections */ - } /* loop for bandwidths */ - } /* loop for bands */ -} - /* * phy file path is stored in global char array rtw_phy_para_file_path * need to care about racing @@ -4411,14 +4281,19 @@ phy_DecryptBBPgParaFile( } } +#ifndef DBG_TXPWR_BY_RATE_FILE_PARSE +#define DBG_TXPWR_BY_RATE_FILE_PARSE 0 +#endif + int phy_ParseBBPgParaFile( PADAPTER Adapter, char *buffer ) { - int rtStatus = _SUCCESS; + int rtStatus = _FAIL; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter); char *szLine, *ptmp; u32 u4bRegOffset, u4bRegMask, u4bRegValue; u32 u4bMove; @@ -4426,8 +4301,6 @@ phy_ParseBBPgParaFile( u8 tx_num = 0; u8 band = 0, rf_path = 0; - /* RTW_INFO("=====>phy_ParseBBPgParaFile()\n"); */ - if (Adapter->registrypriv.RegDecryptCustomFile == 1) phy_DecryptBBPgParaFile(Adapter, buffer); @@ -4439,112 +4312,24 @@ phy_ParseBBPgParaFile( if (!IsCommentString(szLine)) { /* Get header info (relative value or exact value) */ if (firstLine) { - if (eqNByte(szLine, (u8 *)("#[v1]"), 5)) { - - pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0'; - /* RTW_INFO("This is a new format PHY_REG_PG.txt\n"); */ - } else if (eqNByte(szLine, (u8 *)("#[v0]"), 5)) { + if (eqNByte(szLine, (u8 *)("#[v1]"), 5)) pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0'; - /* RTW_INFO("This is a old format PHY_REG_PG.txt ok\n"); */ - } else { - RTW_INFO("The format in PHY_REG_PG are invalid %s\n", szLine); - return _FAIL; + else { + RTW_ERR("The format in PHY_REG_PG are invalid %s\n", szLine); + goto exit; } if (eqNByte(szLine + 5, (u8 *)("[Exact]#"), 8)) { pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; - /* RTW_INFO("The values in PHY_REG_PG are exact values ok\n"); */ - firstLine = _FALSE; - continue; - } else if (eqNByte(szLine + 5, (pu1Byte)("[Relative]#"), 11)) { - pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_RELATIVE_VALUE; - /* RTW_INFO("The values in PHY_REG_PG are relative values ok\n"); */ firstLine = _FALSE; continue; } else { - RTW_INFO("The values in PHY_REG_PG are invalid %s\n", szLine); - return _FAIL; + RTW_ERR("The values in PHY_REG_PG are invalid %s\n", szLine); + goto exit; } } - if (pHalData->odmpriv.phy_reg_pg_version == 0) { - /* Get 1st hex value as register offset. */ - if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) { - szLine += u4bMove; - if (u4bRegOffset == 0xffff) { - /* Ending. */ - break; - } - - /* Get 2nd hex value as register mask. */ - if (GetHexValueFromString(szLine, &u4bRegMask, &u4bMove)) - szLine += u4bMove; - else - return _FAIL; - - if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_RELATIVE_VALUE) { - /* Get 3rd hex value as register value. */ - if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) { - phy_store_tx_power_by_rate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, u4bRegValue); - /* RTW_INFO("[ADDR] %03X=%08X Mask=%08x\n", u4bRegOffset, u4bRegValue, u4bRegMask); */ - } else - return _FAIL; - } else if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) { - u32 combineValue = 0; - u8 integer = 0, fraction = 0; - - if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) - szLine += u4bMove; - else - return _FAIL; - - integer *= 2; - if (fraction == 5) - integer += 1; - combineValue |= (((integer / 10) << 4) + (integer % 10)); - /* RTW_INFO(" %d", integer ); */ - - if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) - szLine += u4bMove; - else - return _FAIL; - - integer *= 2; - if (fraction == 5) - integer += 1; - combineValue <<= 8; - combineValue |= (((integer / 10) << 4) + (integer % 10)); - /* RTW_INFO(" %d", integer ); */ - - if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) - szLine += u4bMove; - else - return _FAIL; - - integer *= 2; - if (fraction == 5) - integer += 1; - combineValue <<= 8; - combineValue |= (((integer / 10) << 4) + (integer % 10)); - /* RTW_INFO(" %d", integer ); */ - - if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) - szLine += u4bMove; - else - return _FAIL; - - integer *= 2; - if (fraction == 5) - integer += 1; - combineValue <<= 8; - combineValue |= (((integer / 10) << 4) + (integer % 10)); - /* RTW_INFO(" %d", integer ); */ - phy_store_tx_power_by_rate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, combineValue); - - /* RTW_INFO("[ADDR] 0x%3x = 0x%4x\n", u4bRegOffset, combineValue ); */ - } - } - } else if (pHalData->odmpriv.phy_reg_pg_version > 0) { + if (pHalData->odmpriv.phy_reg_pg_version > 0) { u32 index = 0, cnt = 0; if (eqNByte(szLine, "0xffff", 6)) @@ -4561,12 +4346,13 @@ phy_ParseBBPgParaFile( band = BAND_ON_5G; index += 6; } else { - RTW_INFO("Invalid band %s in PHY_REG_PG.txt\n", szLine); - return _FAIL; + RTW_ERR("Invalid band %s in PHY_REG_PG.txt\n", szLine); + goto exit; } rf_path = szLine[index] - 'A'; - /* RTW_INFO(" Table label Band %d, RfPath %d\n", band, rf_path ); */ + if (DBG_TXPWR_BY_RATE_FILE_PARSE) + RTW_INFO(" Table label Band %d, RfPath %d\n", band, rf_path ); } else { /* load rows of tables */ if (szLine[1] == '1') tx_num = RF_1TX; @@ -4577,8 +4363,8 @@ phy_ParseBBPgParaFile( else if (szLine[1] == '4') tx_num = RF_4TX; else { - RTW_INFO("Invalid row in PHY_REG_PG.txt '%c'(%d)\n", szLine[1], szLine[1]); - return _FAIL; + RTW_ERR("Invalid row in PHY_REG_PG.txt '%c'(%d)\n", szLine[1], szLine[1]); + goto exit; } while (szLine[index] != ']') @@ -4590,81 +4376,84 @@ phy_ParseBBPgParaFile( if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) szLine += u4bMove; else - return _FAIL; + goto exit; /* Get 2nd hex value as register mask. */ if (GetHexValueFromString(szLine, &u4bRegMask, &u4bMove)) szLine += u4bMove; else - return _FAIL; - - if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_RELATIVE_VALUE) { - /* Get 3rd hex value as register value. */ - if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) { - phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, u4bRegValue); - /* RTW_INFO("[ADDR] %03X (tx_num %d) =%08X Mask=%08x\n", u4bRegOffset, tx_num, u4bRegValue, u4bRegMask); */ - } else - return _FAIL; - } else if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) { + goto exit; + + if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) { u32 combineValue = 0; u8 integer = 0, fraction = 0; if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) szLine += u4bMove; else - return _FAIL; + goto exit; - integer *= 2; - if (fraction == 5) - integer += 1; - combineValue |= (((integer / 10) << 4) + (integer % 10)); - /* RTW_INFO(" %d", integer ); */ + integer *= hal_spec->txgi_pdbm; + integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100; + if (hal_spec->txgi_pdbm == 2) + combineValue |= (((integer / 10) << 4) + (integer % 10)); + else + combineValue |= integer; if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) szLine += u4bMove; else - return _FAIL; + goto exit; - integer *= 2; - if (fraction == 5) - integer += 1; + integer *= hal_spec->txgi_pdbm; + integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100; combineValue <<= 8; - combineValue |= (((integer / 10) << 4) + (integer % 10)); - /* RTW_INFO(" %d", integer ); */ + if (hal_spec->txgi_pdbm == 2) + combineValue |= (((integer / 10) << 4) + (integer % 10)); + else + combineValue |= integer; if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) szLine += u4bMove; else - return _FAIL; + goto exit; - integer *= 2; - if (fraction == 5) - integer += 1; + integer *= hal_spec->txgi_pdbm; + integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100; combineValue <<= 8; - combineValue |= (((integer / 10) << 4) + (integer % 10)); - /* RTW_INFO(" %d", integer ); */ + if (hal_spec->txgi_pdbm == 2) + combineValue |= (((integer / 10) << 4) + (integer % 10)); + else + combineValue |= integer; if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) szLine += u4bMove; else - return _FAIL; + goto exit; - integer *= 2; - if (fraction == 5) - integer += 1; + integer *= hal_spec->txgi_pdbm; + integer += ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100; combineValue <<= 8; - combineValue |= (((integer / 10) << 4) + (integer % 10)); - /* RTW_INFO(" %d", integer ); */ + if (hal_spec->txgi_pdbm == 2) + combineValue |= (((integer / 10) << 4) + (integer % 10)); + else + combineValue |= integer; + phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue); - /* RTW_INFO("[ADDR] 0x%3x (tx_num %d) = 0x%4x\n", u4bRegOffset, tx_num, combineValue ); */ + if (DBG_TXPWR_BY_RATE_FILE_PARSE) + RTW_INFO("addr:0x%3x mask:0x%08x %dTx = 0x%08x\n", u4bRegOffset, u4bRegMask, tx_num, combineValue); } } } } } } - /* RTW_INFO("<=====phy_ParseBBPgParaFile()\n"); */ + + rtStatus = _SUCCESS; + +exit: + RTW_INFO("%s return %d\n", __func__, rtStatus); return rtStatus; } @@ -4705,7 +4494,7 @@ phy_ConfigBBWithPgParaFile( if (rtStatus == _SUCCESS) { /* RTW_INFO("phy_ConfigBBWithPgParaFile(): read %s ok\n", pFileName); */ - phy_ParseBBPgParaFile(Adapter, pHalData->para_file_buf); + rtStatus = phy_ParseBBPgParaFile(Adapter, pHalData->para_file_buf); } else RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); @@ -4804,7 +4593,7 @@ int PHY_ConfigRFWithParaFile( IN PADAPTER Adapter, IN char *pFileName, - IN u8 eRFPath + IN enum rf_path eRFPath ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); @@ -4819,11 +4608,11 @@ PHY_ConfigRFWithParaFile( return rtStatus; switch (eRFPath) { - case ODM_RF_PATH_A: + case RF_PATH_A: pBuf = pHalData->rf_radio_a; pBufLen = &pHalData->rf_radio_a_len; break; - case ODM_RF_PATH_B: + case RF_PATH_B: pBuf = pHalData->rf_radio_b; pBufLen = &pHalData->rf_radio_b_len; break; @@ -4846,12 +4635,15 @@ PHY_ConfigRFWithParaFile( *pBufLen = rlen; switch (eRFPath) { - case ODM_RF_PATH_A: + case RF_PATH_A: pHalData->rf_radio_a = pBuf; break; - case ODM_RF_PATH_B: + case RF_PATH_B: pHalData->rf_radio_b = pBuf; break; + default: + RTW_INFO("Unknown RF path!! %d\r\n", eRFPath); + break; } } else RTW_INFO("%s(): eRFPath=%d alloc fail !\n", __FUNCTION__, eRFPath); @@ -4949,8 +4741,8 @@ initDeltaSwingIndexTables( } } while (0)\ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); u32 j = 0; char *token; char delim[] = ","; @@ -5018,8 +4810,8 @@ PHY_ConfigRFWithTxPwrTrackParaFile( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); int rlen = 0, rtStatus = _FAIL; char *szLine, *ptmp; u32 i = 0, j = 0; @@ -5109,24 +4901,143 @@ PHY_ConfigRFWithTxPwrTrackParaFile( return rtStatus; } -int +#ifdef CONFIG_TXPWR_LIMIT + +#ifndef DBG_TXPWR_LMT_FILE_PARSE +#define DBG_TXPWR_LMT_FILE_PARSE 0 +#endif + +#define PARSE_RET_NO_HDL 0 +#define PARSE_RET_SUCCESS 1 +#define PARSE_RET_FAIL 2 + +/* +* @@Ver=2.0 +* or +* @@DomainCode=0x28, Regulation=C6 +* or +* @@CountryCode=GB, Regulation=C7 +*/ +static u8 parse_reg_exc_config(_adapter *adapter, char *szLine) +{ +#define VER_PREFIX "Ver=" +#define DOMAIN_PREFIX "DomainCode=0x" +#define COUNTRY_PREFIX "CountryCode=" +#define REG_PREFIX "Regulation=" + + const u8 ver_prefix_len = strlen(VER_PREFIX); + const u8 domain_prefix_len = strlen(DOMAIN_PREFIX); + const u8 country_prefix_len = strlen(COUNTRY_PREFIX); + const u8 reg_prefix_len = strlen(REG_PREFIX); + u32 i, i_val_s, i_val_e; + u32 j; + u8 domain = 0xFF; + char *country = NULL; + u8 parse_reg = 0; + + if (szLine[0] != '@' || szLine[1] != '@') + return PARSE_RET_NO_HDL; + + i = 2; + if (strncmp(szLine + i, VER_PREFIX, ver_prefix_len) == 0) + ; /* nothing to do */ + else if (strncmp(szLine + i, DOMAIN_PREFIX, domain_prefix_len) == 0) { + /* get string after domain prefix to ',' */ + i += domain_prefix_len; + i_val_s = i; + while (szLine[i] != ',') { + if (szLine[i] == '\0') + return PARSE_RET_FAIL; + i++; + } + i_val_e = i; + + /* check if all hex */ + for (j = i_val_s; j < i_val_e; j++) + if (IsHexDigit(szLine[j]) == _FALSE) + return PARSE_RET_FAIL; + + /* get value from hex string */ + if (sscanf(szLine + i_val_s, "%hhx", &domain) != 1) + return PARSE_RET_FAIL; + + parse_reg = 1; + } else if (strncmp(szLine + i, COUNTRY_PREFIX, country_prefix_len) == 0) { + /* get string after country prefix to ',' */ + i += country_prefix_len; + i_val_s = i; + while (szLine[i] != ',') { + if (szLine[i] == '\0') + return PARSE_RET_FAIL; + i++; + } + i_val_e = i; + + if (i_val_e - i_val_s != 2) + return PARSE_RET_FAIL; + + /* check if all alpha */ + for (j = i_val_s; j < i_val_e; j++) + if (is_alpha(szLine[j]) == _FALSE) + return PARSE_RET_FAIL; + + country = szLine + i_val_s; + + parse_reg = 1; + + } else + return PARSE_RET_FAIL; + + if (parse_reg) { + /* move to 'R' */ + while (szLine[i] != 'R') { + if (szLine[i] == '\0') + return PARSE_RET_FAIL; + i++; + } + + /* check if matching regulation prefix */ + if (strncmp(szLine + i, REG_PREFIX, reg_prefix_len) != 0) + return PARSE_RET_FAIL; + + /* get string after regulation prefix ending with space */ + i += reg_prefix_len; + i_val_s = i; + while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0') + i++; + + if (i == i_val_s) + return PARSE_RET_FAIL; + + rtw_regd_exc_add_with_nlen(adapter_to_rfctl(adapter), country, domain, szLine + i_val_s, i - i_val_s); + } + + return PARSE_RET_SUCCESS; +} + +static int phy_ParsePowerLimitTableFile( PADAPTER Adapter, char *buffer ) { +#define LD_STAGE_EXC_MAPPING 0 +#define LD_STAGE_TAB_DEFINE 1 +#define LD_STAGE_TAB_START 2 +#define LD_STAGE_COLUMN_DEFINE 3 +#define LD_STAGE_CH_ROW 4 + + int rtStatus = _FAIL; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(Adapter); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); + u8 loadingStage = LD_STAGE_EXC_MAPPING; u32 i = 0, forCnt = 0; - u8 loadingStage = 0, limitValue = 0, fraction = 0; char *szLine, *ptmp; - int rtStatus = _SUCCESS; - char band[10], bandwidth[10], rateSection[10], - regulation[TXPWR_LMT_MAX_REGULATION_NUM][10], rfPath[10], colNumBuf[10]; + char band[10], bandwidth[10], rateSection[10], ntx[10], colNumBuf[10]; + char **regulation = NULL; u8 colNum = 0; - RTW_INFO("===>phy_ParsePowerLimitTableFile()\n"); - if (Adapter->registrypriv.RegDecryptCustomFile == 1) phy_DecryptBBPgParaFile(Adapter, buffer); @@ -5134,20 +5045,25 @@ phy_ParsePowerLimitTableFile( for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) { if (isAllSpaceOrTab(szLine, sizeof(*szLine))) continue; - - /* skip comment */ if (IsCommentString(szLine)) continue; - if (loadingStage == 0) { - for (forCnt = 0; forCnt < TXPWR_LMT_MAX_REGULATION_NUM; ++forCnt) - _rtw_memset((PVOID) regulation[forCnt], 0, 10); - _rtw_memset((PVOID) band, 0, 10); - _rtw_memset((PVOID) bandwidth, 0, 10); - _rtw_memset((PVOID) rateSection, 0, 10); - _rtw_memset((PVOID) rfPath, 0, 10); - _rtw_memset((PVOID) colNumBuf, 0, 10); + if (loadingStage == LD_STAGE_EXC_MAPPING) { + if (szLine[0] == '#' || szLine[1] == '#') { + loadingStage = LD_STAGE_TAB_DEFINE; + if (DBG_TXPWR_LMT_FILE_PARSE) + dump_regd_exc_list(RTW_DBGDUMP, adapter_to_rfctl(Adapter)); + } else { + if (parse_reg_exc_config(Adapter, szLine) == PARSE_RET_FAIL) { + RTW_ERR("Fail to parse regulation exception ruls!\n"); + goto exit; + } + continue; + } + } + if (loadingStage == LD_STAGE_TAB_DEFINE) { + /* read "## 2.4G, 20M, 1T, CCK" */ if (szLine[0] != '#' || szLine[1] != '#') continue; @@ -5159,25 +5075,30 @@ phy_ParsePowerLimitTableFile( szLine[--i] = ' '; /* return the space in front of the regulation info */ /* Parse the label of the table */ + _rtw_memset((PVOID) band, 0, 10); + _rtw_memset((PVOID) bandwidth, 0, 10); + _rtw_memset((PVOID) ntx, 0, 10); + _rtw_memset((PVOID) rateSection, 0, 10); if (!ParseQualifiedString(szLine, &i, band, ' ', ',')) { - RTW_INFO("Fail to parse band!\n"); - return _FAIL; + RTW_ERR("Fail to parse band!\n"); + goto exit; } if (!ParseQualifiedString(szLine, &i, bandwidth, ' ', ',')) { - RTW_INFO("Fail to parse bandwidth!\n"); - return _FAIL; + RTW_ERR("Fail to parse bandwidth!\n"); + goto exit; } - if (!ParseQualifiedString(szLine, &i, rfPath, ' ', ',')) { - RTW_INFO("Fail to parse rf path!\n"); - return _FAIL; + if (!ParseQualifiedString(szLine, &i, ntx, ' ', ',')) { + RTW_ERR("Fail to parse ntx!\n"); + goto exit; } if (!ParseQualifiedString(szLine, &i, rateSection, ' ', ',')) { - RTW_INFO("Fail to parse rate!\n"); - return _FAIL; + RTW_ERR("Fail to parse rate!\n"); + goto exit; } - loadingStage = 1; - } else if (loadingStage == 1) { + loadingStage = LD_STAGE_TAB_START; + } else if (loadingStage == LD_STAGE_TAB_START) { + /* read "## START" */ if (szLine[0] != '#' || szLine[1] != '#') continue; @@ -5187,12 +5108,13 @@ phy_ParsePowerLimitTableFile( ++i; if (!eqNByte((u8 *)(szLine + i), (u8 *)("START"), 5)) { - RTW_INFO("Lost \"## START\" label\n"); - return _FAIL; + RTW_ERR("Missing \"## START\" label\n"); + goto exit; } - loadingStage = 2; - } else if (loadingStage == 2) { + loadingStage = LD_STAGE_COLUMN_DEFINE; + } else if (loadingStage == LD_STAGE_COLUMN_DEFINE) { + /* read "## #5# FCC ETSI MKK IC KCC" */ if (szLine[0] != '#' || szLine[1] != '#') continue; @@ -5201,39 +5123,59 @@ phy_ParsePowerLimitTableFile( while (szLine[i] == ' ' || szLine[i] == '\t') ++i; + _rtw_memset((PVOID) colNumBuf, 0, 10); if (!ParseQualifiedString(szLine, &i, colNumBuf, '#', '#')) { - RTW_INFO("Fail to parse column number!\n"); - return _FAIL; + RTW_ERR("Fail to parse column number!\n"); + goto exit; + } + if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) { + RTW_ERR("Column number \"%s\" is not unsigned decimal\n", colNumBuf); + goto exit; + } + if (colNum == 0) { + RTW_ERR("Column number is 0\n"); + goto exit; } - if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) - return _FAIL; + if (DBG_TXPWR_LMT_FILE_PARSE) + RTW_PRINT("[%s][%s][%s][%s] column num:%d\n", band, bandwidth, rateSection, ntx, colNum); - if (colNum > TXPWR_LMT_MAX_REGULATION_NUM) { - RTW_INFO("unvalid col number %d (greater than max %d)\n", - colNum, TXPWR_LMT_MAX_REGULATION_NUM); - return _FAIL; + regulation = (char **)rtw_zmalloc(sizeof(char *) * colNum); + if (!regulation) { + RTW_ERR("Regulation alloc fail\n"); + goto exit; } for (forCnt = 0; forCnt < colNum; ++forCnt) { - u8 regulation_name_cnt = 0; + u32 i_ns; /* skip the space */ while (szLine[i] == ' ' || szLine[i] == '\t') - ++i; + i++; + i_ns = i; while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0') - regulation[forCnt][regulation_name_cnt++] = szLine[i++]; - /* RTW_INFO("regulation %s!\n", regulation[forCnt]); */ + i++; - if (regulation_name_cnt == 0) { - RTW_INFO("unvalid number of regulation!\n"); - return _FAIL; + regulation[forCnt] = (char *)rtw_malloc(i - i_ns + 1); + if (!regulation[forCnt]) { + RTW_ERR("Regulation alloc fail\n"); + goto exit; } + + _rtw_memcpy(regulation[forCnt], szLine + i_ns, i - i_ns); + regulation[forCnt][i - i_ns] = '\0'; + } + + if (DBG_TXPWR_LMT_FILE_PARSE) { + RTW_PRINT("column name:"); + for (forCnt = 0; forCnt < colNum; ++forCnt) + _RTW_PRINT(" %s", regulation[forCnt]); + _RTW_PRINT("\n"); } - loadingStage = 3; - } else if (loadingStage == 3) { + loadingStage = LD_STAGE_CH_ROW; + } else if (loadingStage == LD_STAGE_CH_ROW) { char channel[10] = {0}, powerLimit[10] = {0}; u8 cnt = 0; @@ -5244,18 +5186,29 @@ phy_ParsePowerLimitTableFile( ++i; if (eqNByte((u8 *)(szLine + i), (u8 *)("END"), 3)) { - loadingStage = 0; + loadingStage = LD_STAGE_TAB_DEFINE; + if (regulation) { + for (forCnt = 0; forCnt < colNum; ++forCnt) { + if (regulation[forCnt]) { + rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1); + regulation[forCnt] = NULL; + } + } + rtw_mfree((u8 *)regulation, sizeof(char *) * colNum); + regulation = NULL; + } + colNum = 0; continue; } else { - RTW_INFO("Wrong format\n"); - RTW_INFO("<===== phy_ParsePowerLimitTableFile()\n"); - return _FAIL; + RTW_ERR("Missing \"## END\" label\n"); + goto exit; } } if ((szLine[0] != 'c' && szLine[0] != 'C') || - (szLine[1] != 'h' && szLine[1] != 'H')) { - RTW_INFO("Meet wrong channel => power limt pair '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]); + (szLine[1] != 'h' && szLine[1] != 'H') + ) { + RTW_WARN("Wrong channel prefix: '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]); continue; } i = 2;/* move to the location behind 'h' */ @@ -5275,81 +5228,82 @@ phy_ParsePowerLimitTableFile( ++i; /* load the power limit value */ - cnt = 0; - fraction = 0; _rtw_memset((PVOID) powerLimit, 0, 10); - while ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.') { - if (szLine[i] == '.') { - if ((szLine[i + 1] >= '0' && szLine[i + 1] <= '9')) { - fraction = szLine[i + 1]; - i += 2; - } else { - RTW_INFO("Wrong fraction in TXPWR_LMT.txt\n"); - return _FAIL; - } - break; - } + if (szLine[i] == 'W' && szLine[i + 1] == 'W') { + /* + * case "WW" assign special ww value + * means to get minimal limit in other regulations at same channel + */ + s8 ww_value = phy_txpwr_ww_lmt_value(Adapter); - powerLimit[cnt] = szLine[i]; - ++cnt; - ++i; - } + sprintf(powerLimit, "%d", ww_value); + i += 2; - if (powerLimit[0] == '\0') { - powerLimit[0] = '6'; - powerLimit[1] = '3'; + } else if (szLine[i] == 'N' && szLine[i + 1] == 'A') { + /* + * case "NA" assign max txgi value + * means no limitation + */ + sprintf(powerLimit, "%d", hal_spec->txgi_max); i += 2; - } else { - if (!GetU1ByteIntegerFromStringInDecimal(powerLimit, &limitValue)) - return _FAIL; - - limitValue *= 2; - cnt = 0; - if (fraction == '5') - ++limitValue; - - /* the value is greater or equal to 100 */ - if (limitValue >= 100) { - powerLimit[cnt++] = limitValue / 100 + '0'; - limitValue %= 100; - - if (limitValue >= 10) { - powerLimit[cnt++] = limitValue / 10 + '0'; - limitValue %= 10; - } else - powerLimit[cnt++] = '0'; - - powerLimit[cnt++] = limitValue + '0'; + + } else if ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.' + || szLine[i] == '+' || szLine[i] == '-' + ){ + /* case of dBm value */ + u8 integer = 0, fraction = 0, negative = 0; + u32 u4bMove; + s8 lmt = 0; + + if (szLine[i] == '+' || szLine[i] == '-') { + if (szLine[i] == '-') + negative = 1; + i++; } - /* the value is greater or equal to 10 */ - else if (limitValue >= 10) { - powerLimit[cnt++] = limitValue / 10 + '0'; - limitValue %= 10; - powerLimit[cnt++] = limitValue + '0'; + + if (GetFractionValueFromString(&szLine[i], &integer, &fraction, &u4bMove)) + i += u4bMove; + else { + RTW_ERR("Limit \"%s\" is not valid decimal\n", &szLine[i]); + goto exit; } - /* the value is less than 10 */ - else - powerLimit[cnt++] = limitValue + '0'; - powerLimit[cnt] = '\0'; - } + /* transform to string of value in unit of txgi */ + lmt = integer * hal_spec->txgi_pdbm + ((u16)fraction * (u16)hal_spec->txgi_pdbm) / 100; + if (negative) + lmt = -lmt; + sprintf(powerLimit, "%d", lmt); - /* RTW_INFO("ch%s => %s\n", channel, powerLimit); */ + } else { + RTW_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n" + , szLine[i], szLine[i + 1], szLine[i], szLine[i + 1]); + goto exit; + } /* store the power limit value */ phy_set_tx_power_limit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band, - (u8 *)bandwidth, (u8 *)rateSection, (u8 *)rfPath, (u8 *)channel, (u8 *)powerLimit); + (u8 *)bandwidth, (u8 *)rateSection, (u8 *)ntx, (u8 *)channel, (u8 *)powerLimit); } - } else { - RTW_INFO("Abnormal loading stage in phy_ParsePowerLimitTableFile()!\n"); - rtStatus = _FAIL; - break; } } - RTW_INFO("<===phy_ParsePowerLimitTableFile()\n"); + rtStatus = _SUCCESS; + +exit: + if (regulation) { + for (forCnt = 0; forCnt < colNum; ++forCnt) { + if (regulation[forCnt]) { + rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1); + regulation[forCnt] = NULL; + } + } + rtw_mfree((u8 *)regulation, sizeof(char *) * colNum); + regulation = NULL; + } + + RTW_INFO("%s return %d\n", __func__, rtStatus); return rtStatus; } @@ -5397,6 +5351,7 @@ PHY_ConfigRFWithPowerLimitTableParaFile( return rtStatus; } +#endif /* CONFIG_TXPWR_LIMIT */ void phy_free_filebuf_mask(_adapter *padapter, u8 mask) { diff --git a/hal/hal_dm.c b/hal/hal_dm.c index 078e196..38a2f3a 100644 --- a/hal/hal_dm.c +++ b/hal/hal_dm.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2014 Realtek Corporation. All rights reserved. + * Copyright(c) 2014 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,20 +11,15 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #include /* A mapping from HalData to ODM. */ -enum odm_board_type_e boardType(u8 InterfaceSel) +enum odm_board_type boardType(u8 InterfaceSel) { - enum odm_board_type_e board = ODM_BOARD_DEFAULT; + enum odm_board_type board = ODM_BOARD_DEFAULT; #ifdef CONFIG_PCI_HCI INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel; @@ -70,22 +65,227 @@ enum odm_board_type_e boardType(u8 InterfaceSel) return board; } +void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + + if (hal->RegIQKFWOffload) { + rtw_sctx_init(&hal->iqk_sctx, 0); + phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD); + } else + phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD); + + RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable"); +} + +#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)) +void rtw_phydm_iqk_trigger(_adapter *adapter) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + u8 clear = _TRUE; + u8 segment = _FALSE; + u8 rfk_forbidden = _FALSE; + + /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/ + halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden); + halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment); + halrf_segment_iqk_trigger(p_dm_odm, clear, segment); +} +#endif + +void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + +#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)) + halrf_segment_iqk_trigger(p_dm_odm, clear, segment); +#else + halrf_iqk_trigger(p_dm_odm, recovery); +#endif +} +void rtw_phydm_lck_trigger(_adapter *adapter) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + + halrf_lck_trigger(p_dm_odm); +} +#ifdef CONFIG_DBG_RF_CAL +void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + + rtw_ps_deny(adapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(adapter); + + rtw_phydm_ability_backup(adapter); + rtw_phydm_func_disable_all(adapter); + + halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK); + + rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment); + rtw_phydm_ability_restore(adapter); + + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); +} + +void rtw_hal_lck_test(_adapter *adapter) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + + rtw_ps_deny(adapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(adapter); + + rtw_phydm_ability_backup(adapter); + rtw_phydm_func_disable_all(adapter); + + halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK); + + rtw_phydm_lck_trigger(adapter); + + rtw_phydm_ability_restore(adapter); + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); +} +#endif + +#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT +void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter) +{ + struct dm_struct *p_dm_odm = adapter_to_phydm(adapter); + + if (adapter->registrypriv.fw_param_init) + phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD); + else + phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD); + + RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable"); +} +#endif + +void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask) +{ + struct dm_struct *p_dm = (struct dm_struct *)p_dm_void; + _adapter *adapter = p_dm->adapter; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + if (p_sta) { + rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode); + rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable); + rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask); + rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32); + + rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter)); + } +} + +#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR +void rtw_phydm_fill_desc_dpt(void *dm, u8 *desc, u8 dpt_lv) +{ + struct dm_struct *p_dm = (struct dm_struct *)dm; + _adapter *adapter = p_dm->adapter; + + switch (rtw_get_chip_type(adapter)) { +/* + #ifdef CONFIG_RTL8188F + case RTL8188F: + break; + #endif + + #ifdef CONFIG_RTL8723B + case RTL8723B : + break; + #endif + + #ifdef CONFIG_RTL8703B + case RTL8703B : + break; + #endif + + #ifdef CONFIG_RTL8812A + case RTL8812 : + break; + #endif + + #ifdef CONFIG_RTL8821A + case RTL8821: + break; + #endif + + #ifdef CONFIG_RTL8814A + case RTL8814A : + break; + #endif + + #ifdef CONFIG_RTL8192F + case RTL8192F : + break; + #endif +*/ +/* + #ifdef CONFIG_RTL8192E + case RTL8192E : + SET_TX_DESC_TX_POWER_0_PSET_92E(desc, dpt_lv); + break; + #endif +*/ + + #ifdef CONFIG_RTL8821C + case RTL8821C : + SET_TX_DESC_TXPWR_OFSET_8821C(desc, dpt_lv); + break; + #endif + + default : + RTW_ERR("%s IC not support dynamic tx power\n", __func__); + break; + } +} +void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id) +{ + struct dm_struct *dm = adapter_to_phydm(adapter); + + odm_set_dyntxpwr(dm, desc, mac_id); +} +#endif + +#ifdef CONFIG_RTW_TX_2PATH_EN +void rtw_phydm_tx_2path_en(_adapter *adapter) +{ + struct dm_struct *dm = adapter_to_phydm(adapter); + + phydm_tx_2path(dm); +} +#endif + +void rtw_phydm_ops_func_init(struct dm_struct *p_phydm) +{ + struct ra_table *p_ra_t = &p_phydm->dm_ra_table; + + p_ra_t->record_ra_info = record_ra_info; + #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR + p_phydm->fill_desc_dyntxpwr = rtw_phydm_fill_desc_dpt; + #endif +} +void rtw_phydm_priv_init(_adapter *adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct dm_struct *phydm = &(hal->odmpriv); + + phydm->adapter = adapter; + odm_cmn_info_init(phydm, ODM_CMNINFO_PLATFORM, ODM_CE); +} + void Init_ODM_ComInfo(_adapter *adapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); int i; - _rtw_memset(pDM_Odm, 0, sizeof(*pDM_Odm)); - - pDM_Odm->adapter = adapter; - - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PLATFORM, ODM_CE); - + /*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/ + pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/ rtw_odm_init_ic_type(adapter); if (rtw_get_intf_type(adapter) == RTW_GSPI) @@ -99,28 +299,10 @@ void Init_ODM_ComInfo(_adapter *adapter) odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec); - - if (pHalData->rf_type == RF_1T1R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T1R); - else if (pHalData->rf_type == RF_1T2R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T2R); - else if (pHalData->rf_type == RF_2T2R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R); - else if (pHalData->rf_type == RF_2T2R_GREEN) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R_GREEN); - else if (pHalData->rf_type == RF_2T3R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T3R); - else if (pHalData->rf_type == RF_2T4R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T4R); - else if (pHalData->rf_type == RF_3T3R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T3R); - else if (pHalData->rf_type == RF_3T4R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T4R); - else if (pHalData->rf_type == RF_4T4R) - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_4T4R); - else - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_XTXR); - +#ifdef CONFIG_ADVANCE_OTA + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota); +#endif + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type); { /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */ @@ -149,12 +331,11 @@ void Init_ODM_ComInfo(_adapter *adapter) /* 1 ============== End of BoardType ============== */ } - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DOMAIN_CODE_2G, pHalData->Regulation2_4G); - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DOMAIN_CODE_5G, pHalData->Regulation5G); + rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE); #ifdef CONFIG_DFS_MASTER odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter->registrypriv.dfs_region_domain); - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->dfs_master_enabled)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->radar_detect_enabled)); #endif odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA); @@ -163,6 +344,7 @@ void Init_ODM_ComInfo(_adapter *adapter) odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_X_CAP_SETTING, pHalData->crystal_cap); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0); @@ -170,8 +352,6 @@ void Init_ODM_ComInfo(_adapter *adapter) odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable); - /*Antenna diversity relative parameters*/ - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg)); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch); @@ -183,45 +363,72 @@ void Init_ODM_ComInfo(_adapter *adapter) /*Add by YuChen for adaptivity init*/ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en)); phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE); - phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DCBACKOFF, adapter->registrypriv.adaptivity_dc_backoff); - phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, (adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE); phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini); phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff); + /*halrf info init*/ + halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter); + halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_PWT_TYPE, 0); + + if (rtw_odm_adaptivity_needed(adapter) == _TRUE) + rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter); + #ifdef CONFIG_IQK_PA_OFF odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1); #endif - odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKFWOFFLOAD, pHalData->RegIQKFWOffload); + rtw_hal_update_iqk_fw_offload_cap(adapter); + #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT + rtw_hal_update_param_init_fw_offload_cap(adapter); + #endif /* Pointer reference */ + /*Antenna diversity relative parameters*/ + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode)); + + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes)); - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_WM_MODE, &(pmlmeext->cur_wireless_mode)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate)); - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed)); - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb)); - odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pmlmepriv->bScanInProcess)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving)); /*Add by Yuchen for phydm beamforming*/ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp)); odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test)); +#ifdef CONFIG_RTL8723B + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path); +#endif /*CONFIG_RTL8723B*/ #ifdef CONFIG_USB_HCI odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed)); #endif + +#ifdef CONFIG_DYNAMIC_SOML + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en)); +#endif + + /*halrf info hook*/ +#ifdef CONFIG_MP_INCLUDED + halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx)); + halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone)); + halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression)); + halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index)); +#endif/*CONFIG_MP_INCLUDED*/ for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) odm_cmn_info_ptr_array_hook(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL); phydm_init_debug_setting(pDM_Odm); - + rtw_phydm_ops_func_init(pDM_Odm); /* TODO */ /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */ /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */ @@ -355,7 +562,7 @@ void rtw_hal_turbo_edca(_adapter *adapter) EDCA_BE_DL = edca_setting_DL[iot_peer]; } - if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E)) { /* add 8812AU/8812AE */ + if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E) || (ic_type == RTL8192F)) { /* add 8812AU/8812AE */ EDCA_BE_UL = 0x5ea42b; EDCA_BE_DL = 0x5ea42b; @@ -363,7 +570,8 @@ void rtw_hal_turbo_edca(_adapter *adapter) } if (interface_type == RTW_PCIE && - (ic_type == RTL8822B)) { + ((ic_type == RTL8822B) + || (ic_type == RTL8814A))) { EDCA_BE_UL = 0x6ea42b; EDCA_BE_DL = 0x6ea42b; } @@ -373,6 +581,59 @@ void rtw_hal_turbo_edca(_adapter *adapter) else edca_param = EDCA_BE_UL; +#ifdef CONFIG_EXTEND_LOWRATE_TXOP +#define TXOP_CCK1M 0x01A6 +#define TXOP_CCK2M 0x00E6 +#define TXOP_CCK5M 0x006B +#define TXOP_OFD6M 0x0066 +#define TXOP_MCS6M 0x0061 +{ + struct sta_info *psta; + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 mac_id, role, current_rate_id; + + /* search all used & connect2AP macid */ + for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) { + if (rtw_macid_is_used(macid_ctl, mac_id)) { + role = GET_H2CCMD_MSRRPT_PARM_ROLE(&(macid_ctl->h2c_msr[mac_id])); + if (role != H2C_MSR_ROLE_AP) + continue; + + psta = macid_ctl->sta[mac_id]; + current_rate_id = rtw_get_current_tx_rate(adapter, psta); + /* Check init tx_rate==1M and set 0x508[31:16]==0x019B(unit 32us) if it is */ + switch (current_rate_id) { + case DESC_RATE1M: + edca_param &= 0x0000FFFF; + edca_param |= (TXOP_CCK1M<<16); + break; + case DESC_RATE2M: + edca_param &= 0x0000FFFF; + edca_param |= (TXOP_CCK2M<<16); + break; + case DESC_RATE5_5M: + edca_param &= 0x0000FFFF; + edca_param |= (TXOP_CCK5M<<16); + break; + case DESC_RATE6M: + edca_param &= 0x0000FFFF; + edca_param |= (TXOP_OFD6M<<16); + break; + case DESC_RATEMCS0: + edca_param &= 0x0000FFFF; + edca_param |= (TXOP_MCS6M<<16); + break; + default: + break; + } + } + } +} +#endif + +#ifdef CONFIG_RTW_CUSTOMIZE_BEEDCA + edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA; +#endif rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param)); RTW_DBG("Turbo EDCA =0x%x\n", edca_param); @@ -395,4 +656,815 @@ void rtw_hal_turbo_edca(_adapter *adapter) } +s8 rtw_phydm_get_min_rssi(_adapter *adapter) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + s8 rssi_min = 0; + + rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN); + return rssi_min; +} + +u8 rtw_phydm_get_cur_igi(_adapter *adapter) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + u8 cur_igi = 0; + + cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI); + return cur_igi; +} + +u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + + if (cnt == FA_OFDM) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM); + else if (cnt == FA_CCK) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK); + else if (cnt == FA_TOTAL) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL); + else if (cnt == CCA_OFDM) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM); + else if (cnt == CCA_CCK) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK); + else if (cnt == CCA_ALL) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL); + else if (cnt == CRC32_OK_VHT) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT); + else if (cnt == CRC32_OK_HT) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT); + else if (cnt == CRC32_OK_LEGACY) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY); + else if (cnt == CRC32_OK_CCK) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK); + else if (cnt == CRC32_ERROR_VHT) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT); + else if (cnt == CRC32_ERROR_HT) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT); + else if (cnt == CRC32_ERROR_LEGACY) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY); + else if (cnt == CRC32_ERROR_CCK) + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK); + else + return 0; +} + +u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter) +{ + u8 rts = _FALSE; + struct dm_struct *podmpriv = adapter_to_phydm(adapter); + + odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK); + if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) { + RTW_ERR("IQK InProgress\n"); + rts = _TRUE; + } + odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK); + + return rts; +} + +void SetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + BOOLEAN bSet) +{ + struct dm_struct *podmpriv = adapter_to_phydm(Adapter); + /* _irqL irqL; */ + switch (eVariable) { + case HAL_ODM_STA_INFO: { + struct sta_info *psta = (struct sta_info *)pValue1; + + if (bSet) { + RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id); + odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, psta); + psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE; + phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn)); + } else { + RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id); + /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ + psta->cmn.dm_ctrl = 0; + odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, NULL); + phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL); + + /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ + } + } + break; + case HAL_ODM_P2P_STATE: + odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet); + break; + case HAL_ODM_WIFI_DISPLAY_STATE: + odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet); + break; + case HAL_ODM_REGULATION: + /* used to auto enable/disable adaptivity by SD7 */ + phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_2G, 0); + phydm_adaptivity_info_update(podmpriv, PHYDM_ADAPINFO_DOMAIN_CODE_5G, 0); + break; + case HAL_ODM_INITIAL_GAIN: { + u8 rx_gain = *((u8 *)(pValue1)); + /*printk("rx_gain:%x\n",rx_gain);*/ + if (rx_gain == 0xff) {/*restore rx gain*/ + /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/ + odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain); + } else { + /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/ + /*odm_write_dig(podmpriv,rx_gain);*/ + odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain); + } + } + break; + case HAL_ODM_RX_INFO_DUMP: { + u8 cur_igi = 0; + s8 rssi_min; + void *sel; + + sel = pValue1; + cur_igi = rtw_phydm_get_cur_igi(Adapter); + rssi_min = rtw_phydm_get_min_rssi(Adapter); + + _RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n"); + _RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%), current_igi = 0x%x\n", podmpriv->is_linked, rssi_min, cur_igi); + _RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n", + rtw_phydm_get_phy_cnt(Adapter, FA_CCK), + rtw_phydm_get_phy_cnt(Adapter, FA_OFDM), + rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL)); + + if (podmpriv->is_linked) { + _RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate)); + if (IS_HARDWARE_TYPE_8814A(Adapter)) + _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\n", + podmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d); + else + _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%)\n", podmpriv->rssi_a, podmpriv->rssi_b); +#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA + rtw_dump_raw_rssi_info(Adapter, sel); +#endif + } + } + break; + case HAL_ODM_RX_Dframe_INFO: { + void *sel; + + sel = pValue1; + + /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/ +#ifdef DBG_RX_DFRAME_RAW_DATA + rtw_dump_rx_dframe_info(Adapter, sel); +#endif + } + break; + +#ifdef CONFIG_ANTENNA_DIVERSITY + case HAL_ODM_ANTDIV_SELECT: { + u8 antenna = (*(u8 *)pValue1); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + /*switch antenna*/ + odm_update_rx_idle_ant(&pHalData->odmpriv, antenna); + /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/ + + } + break; +#endif + + default: + break; + } +} + +void GetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + PVOID pValue2) +{ + struct dm_struct *podmpriv = adapter_to_phydm(Adapter); + + switch (eVariable) { +#ifdef CONFIG_ANTENNA_DIVERSITY + case HAL_ODM_ANTDIV_SELECT: { + struct phydm_fat_struct *pDM_FatTable = &podmpriv->dm_fat_table; + *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant; + } + break; +#endif + case HAL_ODM_INITIAL_GAIN: + *((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter); + break; + default: + break; + } +} + +#ifdef RTW_HALMAC +#include "../hal_halmac.h" +#endif + +enum hal_status +rtw_phydm_fw_iqk( + struct dm_struct *p_dm_odm, + u8 clear, + u8 segment +) +{ + #ifdef RTW_HALMAC + struct _ADAPTER *adapter = p_dm_odm->adapter; + + if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0) + return HAL_STATUS_SUCCESS; + #endif + return HAL_STATUS_FAILURE; +} + +enum hal_status +rtw_phydm_cfg_phy_para( + struct dm_struct *p_dm_odm, + enum phydm_halmac_param config_type, + u32 offset, + u32 data, + u32 mask, + enum rf_path e_rf_path, + u32 delay_time) +{ + #ifdef RTW_HALMAC + struct _ADAPTER *adapter = p_dm_odm->adapter; + struct rtw_phy_parameter para; + + switch (config_type) { + case PHYDM_HALMAC_CMD_MAC_W8: + para.cmd = 0; /* MAC register */ + para.data.mac.offset = offset; + para.data.mac.value = data; + para.data.mac.msk = mask; + para.data.mac.msk_en = (mask) ? 1 : 0; + para.data.mac.size = 1; + break; + case PHYDM_HALMAC_CMD_MAC_W16: + para.cmd = 0; /* MAC register */ + para.data.mac.offset = offset; + para.data.mac.value = data; + para.data.mac.msk = mask; + para.data.mac.msk_en = (mask) ? 1 : 0; + para.data.mac.size = 2; + break; + case PHYDM_HALMAC_CMD_MAC_W32: + para.cmd = 0; /* MAC register */ + para.data.mac.offset = offset; + para.data.mac.value = data; + para.data.mac.msk = mask; + para.data.mac.msk_en = (mask) ? 1 : 0; + para.data.mac.size = 4; + break; + case PHYDM_HALMAC_CMD_BB_W8: + para.cmd = 1; /* BB register */ + para.data.bb.offset = offset; + para.data.bb.value = data; + para.data.bb.msk = mask; + para.data.bb.msk_en = (mask) ? 1 : 0; + para.data.bb.size = 1; + break; + case PHYDM_HALMAC_CMD_BB_W16: + para.cmd = 1; /* BB register */ + para.data.bb.offset = offset; + para.data.bb.value = data; + para.data.bb.msk = mask; + para.data.bb.msk_en = (mask) ? 1 : 0; + para.data.bb.size = 2; + break; + case PHYDM_HALMAC_CMD_BB_W32: + para.cmd = 1; /* BB register */ + para.data.bb.offset = offset; + para.data.bb.value = data; + para.data.bb.msk = mask; + para.data.bb.msk_en = (mask) ? 1 : 0; + para.data.bb.size = 4; + break; + case PHYDM_HALMAC_CMD_RF_W: + para.cmd = 2; /* RF register */ + para.data.rf.offset = offset; + para.data.rf.value = data; + para.data.rf.msk = mask; + para.data.rf.msk_en = (mask) ? 1 : 0; + if (e_rf_path == RF_PATH_A) + para.data.rf.path = 0; + else if (e_rf_path == RF_PATH_B) + para.data.rf.path = 1; + else if (e_rf_path == RF_PATH_C) + para.data.rf.path = 2; + else if (e_rf_path == RF_PATH_D) + para.data.rf.path = 3; + else + para.data.rf.path = 0; + break; + case PHYDM_HALMAC_CMD_DELAY_US: + para.cmd = 3; /* Delay */ + para.data.delay.unit = 0; /* microsecond */ + para.data.delay.value = delay_time; + break; + case PHYDM_HALMAC_CMD_DELAY_MS: + para.cmd = 3; /* Delay */ + para.data.delay.unit = 1; /* millisecond */ + para.data.delay.value = delay_time; + break; + case PHYDM_HALMAC_CMD_END: + para.cmd = 0xFF; /* End command */ + break; + default: + return HAL_STATUS_FAILURE; + } + + if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), ¶)) + return HAL_STATUS_FAILURE; + #endif /*RTW_HALMAC*/ + return HAL_STATUS_SUCCESS; +} + + +#ifdef CONFIG_LPS_LCLK_WD_TIMER +void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + struct dm_struct *podmpriv = &(pHalData->odmpriv); + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *psta = NULL; + u8 rssi_min = 0; + u32 rssi_rpt = 0; + bool is_linked = _FALSE; + + if (!rtw_is_hw_init_completed(adapter)) + return; + + if (rtw_mi_check_status(adapter, MI_ASSOC)) + is_linked = _TRUE; + + if (is_linked == _FALSE) + return; + + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta == NULL) + return; + + odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked); + + phydm_watchdog_lps_32k(&pHalData->odmpriv); +} + +void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *psta = NULL; + u8 cur_igi = 0; + s8 min_rssi = 0; + + if (!rtw_is_hw_init_completed(adapter)) + return; + + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta == NULL) + return; + + cur_igi = rtw_phydm_get_cur_igi(adapter); + min_rssi = rtw_phydm_get_min_rssi(adapter); + if (min_rssi <= 0) + min_rssi = psta->cmn.rssi_stat.rssi; + /*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__, ADPT_ARG(adapter), cur_igi, min_rssi);*/ + + if (min_rssi <= 0) + return; + + if ((cur_igi > min_rssi + 5) || + (cur_igi < min_rssi - 5)) { +#ifdef CONFIG_LPS + rtw_dm_in_lps_wk_cmd(adapter); +#endif + } +} +#endif /*CONFIG_LPS_LCLK_WD_TIMER*/ + +void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta) +{ + struct ra_sta_info *ra_info; + u8 curr_sgi = _FALSE; + u32 tx_tp_mbips, rx_tp_mbips, bi_tp_mbips; + + if (!psta) + return; + RTW_PRINT_SEL(sel, "\n"); + RTW_PRINT_SEL(sel, "====== mac_id : %d [" MAC_FMT "] ======\n", + psta->cmn.mac_id, MAC_ARG(psta->cmn.mac_addr)); + + if (is_client_associated_to_ap(psta->padapter)) + RTW_PRINT_SEL(sel, "BCN counts : %d (per-%d second), DTIM Period:%d\n", + rtw_get_bcn_cnt(psta->padapter) / 2, 1, adapter->mlmeextpriv.dtim); + + ra_info = &psta->cmn.ra_info; + curr_sgi = rtw_get_current_tx_sgi(adapter, psta); + RTW_PRINT_SEL(sel, "tx_rate : %s(%s) rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n" + , HDATA_RATE(rtw_get_current_tx_rate(adapter, psta)), (curr_sgi) ? "S" : "L" + , HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi + ); + + if (0) { + RTW_PRINT_SEL(sel, "tx_bytes:%llu(%llu - %llu)\n" + , psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes + , psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes + ); + RTW_PRINT_SEL(sel, "rx_uc_bytes:%llu(%llu - %llu)\n" + , sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta) + , sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta) + ); + RTW_PRINT_SEL(sel, "rx_mc_bytes:%llu(%llu - %llu)\n" + , psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes + , psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes + ); + RTW_PRINT_SEL(sel, "rx_bc_bytes:%llu(%llu - %llu)\n" + , psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes + , psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes + ); + } + + _RTW_PRINT_SEL(sel, "RTW: [TP] "); + tx_tp_mbips = psta->sta_stats.tx_tp_kbits >> 10; + rx_tp_mbips = psta->sta_stats.rx_tp_kbits >> 10; + bi_tp_mbips = tx_tp_mbips + rx_tp_mbips; + + if (tx_tp_mbips) + _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips); + else + _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.tx_tp_kbits); + + if (rx_tp_mbips) + _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips); + else + _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.rx_tp_kbits); + + if (bi_tp_mbips) + _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips); + else + _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.tx_tp_kbits + psta->sta_stats.rx_tp_kbits); + + + _RTW_PRINT_SEL(sel, "RTW: [Smooth TP] "); + tx_tp_mbips = psta->sta_stats.smooth_tx_tp_kbits >> 10; + rx_tp_mbips = psta->sta_stats.smooth_rx_tp_kbits >> 10; + bi_tp_mbips = tx_tp_mbips + rx_tp_mbips; + if (tx_tp_mbips) + _RTW_PRINT_SEL(sel, "Tx : %d(Mbps) ", tx_tp_mbips); + else + _RTW_PRINT_SEL(sel, "Tx : %d(Kbps) ", psta->sta_stats.smooth_tx_tp_kbits); + + if (rx_tp_mbips) + _RTW_PRINT_SEL(sel, "Rx : %d(Mbps) ", rx_tp_mbips); + else + _RTW_PRINT_SEL(sel, "Rx : %d(Kbps) ", psta->sta_stats.smooth_rx_tp_kbits); + + if (bi_tp_mbips) + _RTW_PRINT_SEL(sel, "Total : %d(Mbps)\n", bi_tp_mbips); + else + _RTW_PRINT_SEL(sel, "Total : %d(Kbps)\n", psta->sta_stats.smooth_tx_tp_kbits + psta->sta_stats.rx_tp_kbits); + + #if 0 + RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n", + (psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3), + (psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3); + #endif +} + +void dump_sta_info(void *sel, struct sta_info *psta) +{ + struct ra_sta_info *ra_info; + u8 curr_tx_sgi = _FALSE; + u8 curr_tx_rate = 0; + + if (!psta) + return; + + ra_info = &psta->cmn.ra_info; + + RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "] ===================\n", + MAC_ARG(psta->cmn.mac_addr)); + RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id); + RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode); + RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type); + RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n", + ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode)); + RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id); + RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level); + RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n", + (ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N"); + RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n", + (ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N"); + RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N"); + RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/ + + curr_tx_sgi = rtw_get_current_tx_sgi(psta->padapter, psta); + curr_tx_rate = rtw_get_current_tx_rate(psta->padapter, psta); + RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n", + HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L"); + RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw)); + RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio); + RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n\n", ra_info->ramask); +} + +void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + if (psta == NULL) { + RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter)); + rtw_warn_on(1); + return; + } + + phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi); + dump_sta_info(RTW_DBGDUMP, psta); +} + +static void init_phydm_info(_adapter *adapter) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + struct dm_struct *phydm = &(hal_data->odmpriv); + + odm_cmn_info_init(phydm, ODM_CMNINFO_FW_VER, hal_data->firmware_version); + odm_cmn_info_init(phydm, ODM_CMNINFO_FW_SUB_VER, hal_data->firmware_sub_version); +} +void rtw_phydm_init(_adapter *adapter) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + struct dm_struct *phydm = &(hal_data->odmpriv); + + init_phydm_info(adapter); + odm_dm_init(phydm); +} + +#ifdef CONFIG_LPS_PG +/* +static void _lps_pg_state_update(_adapter *adapter) +{ + u8 is_in_lpspg = _FALSE; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *psta = NULL; + + if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2)) + is_in_lpspg = _TRUE; + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + + if (psta) + psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE; +} +*/ +void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + /*u8 rate_id;*/ + + if(sta == NULL) { + RTW_ERR("%s sta is null\n", __func__); + rtw_warn_on(1); + return; + } + + if (in_lpspg) { + sta->cmn.ra_info.disable_ra = _TRUE; + sta->cmn.ra_info.disable_pt = _TRUE; + /*TODO : DRV fix tx rate*/ + /*rate_id = phydm_get_rate_from_rssi_lv(phydm, sta->cmn.mac_id);*/ + } else { + sta->cmn.ra_info.disable_ra = _FALSE; + sta->cmn.ra_info.disable_pt = _FALSE; + } + + rtw_phydm_ra_registed(adapter, sta); +} +#endif + +/*#define DBG_PHYDM_STATE_CHK*/ + + +static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter, u8 is_scaning, u8 ifs_linked) +{ + u8 rfk_allowed = _TRUE; + + #ifdef CONFIG_SKIP_RFK_IN_DM + rfk_allowed = _FALSE; + if (0) + RTW_ERR("[RFK-CHK] RF-K not allowed due to CONFIG_SKIP_RFK_IN_DM\n"); + return rfk_allowed; + #endif + + if (ifs_linked) { + if (is_scaning) { + rfk_allowed = _FALSE; + RTW_ERR("[RFK-CHK] RF-K not allowed due to ifaces under site-survey\n"); + } + else { + rfk_allowed = rtw_mi_stayin_union_ch_chk(adapter) ? _TRUE : _FALSE; + if (rfk_allowed == _FALSE) + RTW_ERR("[RFK-CHK] RF-K not allowed due to ld_iface not stayin union ch\n"); + } + } + + #ifdef CONFIG_MCC_MODE + /*not in MCC State*/ + if (MCC_EN(adapter)) { + if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) { + rfk_allowed = _FALSE; + if (0) + RTW_ERR("[RFK-CHK] RF-K not allowed due to doing MCC\n"); + } + } + #endif + + #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) + + #endif + + return rfk_allowed; +} +#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)) +static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter, u8 ifs_linked) +{ + u8 iqk_sgt = _FALSE; + +#if 0 + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + if (is_linked && (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2)) + rst = _TRUE; +#else + if (ifs_linked) + iqk_sgt = _TRUE; +#endif + return iqk_sgt; +} +#endif + +/*check the tx low rate while unlinked to any AP;for pwr tracking */ +static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter) +{ + int i; + _adapter *iface; + u8 if_tx_rate = 0xFF; + u8 tx_rate = 0xFF; + struct mlme_ext_priv *pmlmeext = NULL; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + pmlmeext = &(iface->mlmeextpriv); + if ((iface) && rtw_is_adapter_up(iface)) { +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE)) + if_tx_rate = IEEE80211_OFDM_RATE_6MB; + else +#endif + if_tx_rate = pmlmeext->tx_rate; + if(if_tx_rate < tx_rate) + tx_rate = if_tx_rate; + + RTW_DBG("%s i=%d tx_rate =0x%x\n", __func__, i, if_tx_rate); + } + } + RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate); + return tx_rate; +} + +#ifdef CONFIG_DYNAMIC_SOML +void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + + phydm_soml_bytes_acq(phydm, data_rate, size); +} + +void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl, + u8 period, u8 delay) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + + phydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay); + RTW_INFO("%s.\n", __func__); +} + +void rtw_dyn_soml_config(_adapter *adapter) +{ + RTW_INFO("%s.\n", __func__); + + if (adapter->registrypriv.dyn_soml_en == 1) { + /* Must after phydm_adaptive_soml_init() */ + rtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL); + RTW_INFO("dyn_soml_en = 1\n"); + } else { + if (adapter->registrypriv.dyn_soml_en == 2) { + rtw_dyn_soml_para_set(adapter, + adapter->registrypriv.dyn_soml_train_num, + adapter->registrypriv.dyn_soml_interval, + adapter->registrypriv.dyn_soml_period, + adapter->registrypriv.dyn_soml_delay); + RTW_INFO("dyn_soml_en = 2\n"); + RTW_INFO("dyn_soml_en, param = %d, %d, %d, %d\n", + adapter->registrypriv.dyn_soml_train_num, + adapter->registrypriv.dyn_soml_interval, + adapter->registrypriv.dyn_soml_period, + adapter->registrypriv.dyn_soml_delay); + } else if (adapter->registrypriv.dyn_soml_en == 0) { + RTW_INFO("dyn_soml_en = 0\n"); + } else + RTW_ERR("%s, wrong setting: dyn_soml_en = %d\n", __func__, + adapter->registrypriv.dyn_soml_en); + } +} +#endif + + +void rtw_phydm_read_efuse(_adapter *adapter) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + struct dm_struct *phydm = &(hal_data->odmpriv); + + /*PHYDM API - thermal trim*/ + phydm_get_thermal_trim_offset(phydm); + /*PHYDM API - power trim*/ + phydm_get_power_trim_offset(phydm); +} + +void rtw_phydm_watchdog(_adapter *adapter) +{ + u8 bLinked = _FALSE; + u8 bsta_state = _FALSE; + u8 bBtDisabled = _TRUE; + u8 rfk_forbidden = _FALSE; + #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)) + u8 segment_iqk = _FALSE; + #endif + u8 tx_unlinked_low_rate = 0xFF; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + + if (!rtw_is_hw_init_completed(adapter)) { + RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__); + return; + } + if (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY)) + pHalData->bScanInProcess = _TRUE; + else + pHalData->bScanInProcess = _FALSE; + + if (rtw_mi_check_status(adapter, MI_ASSOC)) { + bLinked = _TRUE; + if (rtw_mi_check_status(adapter, MI_STA_LINKED)) + bsta_state = _TRUE; + } + + odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked); + odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state); + + #ifdef CONFIG_BT_COEXIST + bBtDisabled = rtw_btcoex_IsBtDisabled(adapter); + #endif /* CONFIG_BT_COEXIST */ + odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, + (bBtDisabled == _TRUE) ? _FALSE : _TRUE); + + rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter, pHalData->bScanInProcess, bLinked) == _TRUE) ? _FALSE : _TRUE; + halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden); + + #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)) + segment_iqk = _rtw_phydm_iqk_segment_chk(adapter, bLinked); + halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk); + #endif + #ifdef DBG_PHYDM_STATE_CHK + RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n", + __func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N"); + #endif + + if (bLinked == _FALSE) { + tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter); + halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate); + } + + /*if (!rtw_mi_stayin_union_band_chk(adapter)) { + #ifdef DBG_PHYDM_STATE_CHK + RTW_ERR("Not stay in union band, skip phydm\n"); + #endif + goto _exit; + }*/ + if (pwrctl->bpower_saving) + phydm_watchdog_lps(&pHalData->odmpriv); + else + phydm_watchdog(&pHalData->odmpriv); + + #ifdef CONFIG_RTW_ACS + rtw_acs_update_current_info(adapter); + #endif + +_exit: + return; +} diff --git a/hal/hal_dm.h b/hal/hal_dm.h index 4e3dad0..af59d41 100644 --- a/hal/hal_dm.h +++ b/hal/hal_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,16 +11,90 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_DM_H__ #define __HAL_DM_H__ +#define adapter_to_phydm(adapter) (&(GET_HAL_DATA(adapter)->odmpriv)) +#define dvobj_to_phydm(dvobj) adapter_to_phydm(dvobj_get_primary_adapter(dvobj)) + +void rtw_phydm_priv_init(_adapter *adapter); void Init_ODM_ComInfo(_adapter *adapter); +void rtw_phydm_init(_adapter *adapter); + void rtw_hal_turbo_edca(_adapter *adapter); +u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter); + +void GetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + PVOID pValue2); +void SetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + BOOLEAN bSet); + +void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta); + +#ifdef CONFIG_DYNAMIC_SOML +void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size); +void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl, + u8 period, u8 delay); +void rtw_dyn_soml_config(_adapter *adapter); +#endif +void rtw_phydm_watchdog(_adapter *adapter); + +void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter); +void dump_sta_info(void *sel, struct sta_info *psta); +void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta); + +#ifdef CONFIG_DBG_RF_CAL +void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment); +void rtw_hal_lck_test(_adapter *adapter); +#endif + +s8 rtw_phydm_get_min_rssi(_adapter *adapter); +u8 rtw_phydm_get_cur_igi(_adapter *adapter); + + +#ifdef CONFIG_LPS_LCLK_WD_TIMER +extern void phydm_rssi_monitor_check(void *p_dm_void); + +void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter); +void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter); +#endif + +enum phy_cnt { + FA_OFDM, + FA_CCK, + FA_TOTAL, + CCA_OFDM, + CCA_CCK, + CCA_ALL, + CRC32_OK_VHT, + CRC32_OK_HT, + CRC32_OK_LEGACY, + CRC32_OK_CCK, + CRC32_ERROR_VHT, + CRC32_ERROR_HT, + CRC32_ERROR_LEGACY, + CRC32_ERROR_CCK, +}; +u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt); +#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1)) +void rtw_phydm_iqk_trigger(_adapter *adapter); +#endif +void rtw_phydm_read_efuse(_adapter *adapter); +#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR +void rtw_phydm_set_dyntxpwr(_adapter *adapter, u8 *desc, u8 mac_id); +#endif +#ifdef CONFIG_RTW_TX_2PATH_EN +void rtw_phydm_tx_2path_en(_adapter *adapter); +#endif +#ifdef CONFIG_LPS_PG +void rtw_phydm_lps_pg_hdl(_adapter *adapter, struct sta_info *sta, bool in_lpspg); +#endif #endif /* __HAL_DM_H__ */ diff --git a/hal/hal_dm_acs.c b/hal/hal_dm_acs.c new file mode 100644 index 0000000..5c19d99 --- /dev/null +++ b/hal/hal_dm_acs.c @@ -0,0 +1,554 @@ +/****************************************************************************** + * + * Copyright(c) 2014 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include +#include + + +#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR) +static void _rtw_bss_nums_count(_adapter *adapter, u8 *pbss_nums) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + _list *plist, *phead; + _irqL irqL; + int chan_idx = -1; + + if (pbss_nums == NULL) { + RTW_ERR("%s pbss_nums is null pointer\n", __func__); + return; + } + _rtw_memset(pbss_nums, 0, MAX_CHANNEL_NUM); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + phead = get_list_head(queue); + plist = get_next(phead); + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (!pnetwork) + break; + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), pnetwork->network.Configuration.DSConfig); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("%s can't get chan_idx(CH:%d)\n", + __func__, pnetwork->network.Configuration.DSConfig); + chan_idx = 0; + } + /*if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ)*/ + + pbss_nums[chan_idx]++; + + plist = get_next(plist); + } + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); +} + +u8 rtw_get_ch_num_by_idx(_adapter *adapter, u8 idx) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + RT_CHANNEL_INFO *pch_set = rfctl->channel_set; + u8 max_chan_nums = rfctl->max_chan_nums; + + if (idx >= max_chan_nums) + return 0; + return pch_set[idx].ChannelNum; +} +#endif /*defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)*/ + + +#ifdef CONFIG_RTW_ACS +void rtw_acs_version_dump(void *sel, _adapter *adapter) +{ + _RTW_PRINT_SEL(sel, "RTK_ACS VER_%d\n", RTK_ACS_VERSION); +} +u8 rtw_phydm_clm_ratio(_adapter *adapter) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CLM_RATIO); +} +u8 rtw_phydm_nhm_ratio(_adapter *adapter) +{ + struct dm_struct *phydm = adapter_to_phydm(adapter); + + return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_NHM_RATIO); +} +void rtw_acs_reset(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct auto_chan_sel *pacs = &hal_data->acs; + + _rtw_memset(pacs, 0, sizeof(struct auto_chan_sel)); + #ifdef CONFIG_RTW_ACS_DBG + rtw_acs_adv_reset(adapter); + #endif /*CONFIG_RTW_ACS_DBG*/ +} + +#ifdef CONFIG_RTW_ACS_DBG +u8 rtw_is_acs_igi_valid(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct auto_chan_sel *pacs = &hal_data->acs; + + if ((pacs->igi) && ((pacs->igi >= 0x1E) || (pacs->igi < 0x60))) + return _TRUE; + + return _FALSE; +} +void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct auto_chan_sel *pacs = &hal_data->acs; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + + pacs->scan_type = scan_type; + pacs->scan_time = scan_time; + pacs->igi = igi; + pacs->bw = bw; + RTW_INFO("[ACS] ADV setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n", + pacs->scan_type ? 'A' : 'P', pacs->scan_time, pacs->igi, pacs->bw); +} +void rtw_acs_adv_reset(_adapter *adapter) +{ + rtw_acs_adv_setting(adapter, SCAN_ACTIVE, 0, 0, 0); +} +#endif /*CONFIG_RTW_ACS_DBG*/ + +void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct dm_struct *phydm = adapter_to_phydm(adapter); +#if (RTK_ACS_VERSION == 3) + struct clm_para_info clm_para; + struct nhm_para_info nhm_para; + struct env_trig_rpt trig_rpt; + + scan_time_ms -= 10; + + init_acs_clm(clm_para, scan_time_ms); + + if (pid == NHM_PID_IEEE_11K_HIGH) + init_11K_high_nhm(nhm_para, scan_time_ms); + else if (pid == NHM_PID_IEEE_11K_LOW) + init_11K_low_nhm(nhm_para, scan_time_ms); + else + init_acs_nhm(nhm_para, scan_time_ms); + + hal_data->acs.trig_rst = phydm_env_mntr_trigger(phydm, &nhm_para, &clm_para, &trig_rpt); + if (hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS)) { + hal_data->acs.trig_rpt.clm_rpt_stamp = trig_rpt.clm_rpt_stamp; + hal_data->acs.trig_rpt.nhm_rpt_stamp = trig_rpt.nhm_rpt_stamp; + /*RTW_INFO("[ACS] trigger success (rst = 0x%02x, clm_stamp:%d, nhm_stamp:%d)\n", + hal_data->acs.trig_rst, hal_data->acs.trig_rpt.clm_rpt_stamp, hal_data->acs.trig_rpt.nhm_rpt_stamp);*/ + } else + RTW_ERR("[ACS] trigger failed (rst = 0x%02x)\n", hal_data->acs.trig_rst); +#else + phydm_ccx_monitor_trigger(phydm, scan_time_ms); +#endif + + hal_data->acs.trigger_ch = scan_chan; + hal_data->acs.triggered = _TRUE; + + #ifdef CONFIG_RTW_ACS_DBG + RTW_INFO("[ACS] Trigger CH:%d, Times:%d\n", hal_data->acs.trigger_ch, scan_time_ms); + #endif +} +void rtw_acs_get_rst(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct dm_struct *phydm = adapter_to_phydm(adapter); + int chan_idx = -1; + u8 cur_chan = hal_data->acs.trigger_ch; + + if (cur_chan == 0) + return; + + if (!hal_data->acs.triggered) + return; + + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), cur_chan); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("[ACS] %s can't get chan_idx(CH:%d)\n", __func__, cur_chan); + return; + } +#if (RTK_ACS_VERSION == 3) + if (!(hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS))) { + RTW_ERR("[ACS] get_rst return, due to acs trigger failed\n"); + return; + } + + { + struct env_mntr_rpt rpt = {0}; + u8 rst; + + rst = phydm_env_mntr_result(phydm, &rpt); + if ((rst == (NHM_SUCCESS | CLM_SUCCESS)) && + (rpt.clm_rpt_stamp == hal_data->acs.trig_rpt.clm_rpt_stamp) && + (rpt.nhm_rpt_stamp == hal_data->acs.trig_rpt.nhm_rpt_stamp)){ + hal_data->acs.clm_ratio[chan_idx] = rpt.clm_ratio; + hal_data->acs.nhm_ratio[chan_idx] = rpt.nhm_ratio; + _rtw_memcpy(&hal_data->acs.nhm[chan_idx][0], rpt.nhm_result, NHM_RPT_NUM); + + /*RTW_INFO("[ACS] get_rst success (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n", + rst, + hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp, + hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);*/ + } else { + RTW_ERR("[ACS] get_rst failed (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n", + rst, + hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp, + hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp); + } + } + +#else + phydm_ccx_monitor_result(phydm); + + hal_data->acs.clm_ratio[chan_idx] = rtw_phydm_clm_ratio(adapter); + hal_data->acs.nhm_ratio[chan_idx] = rtw_phydm_nhm_ratio(adapter); +#endif + hal_data->acs.triggered = _FALSE; + #ifdef CONFIG_RTW_ACS_DBG + RTW_INFO("[ACS] Result CH:%d, CLM:%d NHM:%d\n", + cur_chan, hal_data->acs.clm_ratio[chan_idx], hal_data->acs.nhm_ratio[chan_idx]); + #endif +} + +void _rtw_phydm_acs_select_best_chan(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + u8 ch_idx; + u8 ch_idx_24g = 0xFF, ch_idx_5g = 0xFF; + u8 min_itf_24g = 0xFF, min_itf_5g = 0xFF; + u8 *pbss_nums = hal_data->acs.bss_nums; + u8 *pclm_ratio = hal_data->acs.clm_ratio; + u8 *pnhm_ratio = hal_data->acs.nhm_ratio; + u8 *pinterference_time = hal_data->acs.interference_time; + u8 max_chan_nums = rfctl->max_chan_nums; + + for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) { + if (pbss_nums[ch_idx]) + pinterference_time[ch_idx] = (pclm_ratio[ch_idx] / 2) + pnhm_ratio[ch_idx]; + else + pinterference_time[ch_idx] = pclm_ratio[ch_idx] + pnhm_ratio[ch_idx]; + + if (rtw_get_ch_num_by_idx(adapter, ch_idx) < 14) { + if (pinterference_time[ch_idx] < min_itf_24g) { + min_itf_24g = pinterference_time[ch_idx]; + ch_idx_24g = ch_idx; + } + } else { + if (pinterference_time[ch_idx] < min_itf_5g) { + min_itf_5g = pinterference_time[ch_idx]; + ch_idx_5g = ch_idx; + } + } + } + if (ch_idx_24g != 0xFF) + hal_data->acs.best_chan_24g = rtw_get_ch_num_by_idx(adapter, ch_idx_24g); + + if (ch_idx_5g != 0xFF) + hal_data->acs.best_chan_5g = rtw_get_ch_num_by_idx(adapter, ch_idx_5g); + + hal_data->acs.trigger_ch = 0; +} + +void rtw_acs_info_dump(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + u8 max_chan_nums = rfctl->max_chan_nums; + u8 ch_idx, ch_num; + + _RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION); + _RTW_PRINT_SEL(sel, "Best 24G Channel:%d\n", hal_data->acs.best_chan_24g); + _RTW_PRINT_SEL(sel, "Best 5G Channel:%d\n\n", hal_data->acs.best_chan_5g); + + #ifdef CONFIG_RTW_ACS_DBG + _RTW_PRINT_SEL(sel, "Advanced setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n", + hal_data->acs.scan_type ? 'A' : 'P', hal_data->acs.scan_time, hal_data->acs.igi, hal_data->acs.bw); + + _RTW_PRINT_SEL(sel, "BW 20MHz\n"); + _RTW_PRINT_SEL(sel, "%5s %3s %3s %3s(%%) %3s(%%) %3s\n", + "Index", "CH", "BSS", "CLM", "NHM", "ITF"); + + for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) { + ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx); + _RTW_PRINT_SEL(sel, "%5d %3d %3d %6d %6d %3d\n", + ch_idx, ch_num, hal_data->acs.bss_nums[ch_idx], + hal_data->acs.clm_ratio[ch_idx], + hal_data->acs.nhm_ratio[ch_idx], + hal_data->acs.interference_time[ch_idx]); + } + #endif +} +void rtw_acs_select_best_chan(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + _rtw_bss_nums_count(adapter, hal_data->acs.bss_nums); + _rtw_phydm_acs_select_best_chan(adapter); + rtw_acs_info_dump(RTW_DBGDUMP, adapter); +} + +void rtw_acs_start(_adapter *adapter) +{ + rtw_acs_reset(adapter); + if (GET_ACS_STATE(adapter) != ACS_ENABLE) + SET_ACS_STATE(adapter, ACS_ENABLE); +} +void rtw_acs_stop(_adapter *adapter) +{ + SET_ACS_STATE(adapter, ACS_DISABLE); +} + + +u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int chan_idx = -1; + + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("[ACS] Get CLM fail, can't get chan_idx(CH:%d)\n", chan); + return 0; + } + + return hal_data->acs.clm_ratio[chan_idx]; +} +u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + if (ch_idx >= MAX_CHANNEL_NUM) { + RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx); + return 0; + } + + return hal_data->acs.clm_ratio[ch_idx]; +} +u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int chan_idx = -1; + + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("[ACS] Get NHM fail, can't get chan_idx(CH:%d)\n", chan); + return 0; + } + + return hal_data->acs.nhm_ratio[chan_idx]; +} +u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + if (ch_idx >= MAX_CHANNEL_NUM) { + RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx); + return 0; + } + + return hal_data->acs.nhm_ratio[ch_idx]; +} +void rtw_acs_chan_info_dump(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + u8 max_chan_nums = rfctl->max_chan_nums; + u8 ch_idx, ch_num; + u8 utilization; + + _RTW_PRINT_SEL(sel, "BW 20MHz\n"); + _RTW_PRINT_SEL(sel, "%5s %3s %7s(%%) %12s(%%) %11s(%%) %9s(%%) %8s(%%)\n", + "Index", "CH", "Quality", "Availability", "Utilization", + "WIFI Util", "Interference Util"); + + for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) { + ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx); + utilization = hal_data->acs.clm_ratio[ch_idx] + hal_data->acs.nhm_ratio[ch_idx]; + _RTW_PRINT_SEL(sel, "%5d %3d %7d %12d %12d %12d %12d\n", + ch_idx, ch_num, + (100-hal_data->acs.interference_time[ch_idx]), + (100-utilization), + utilization, + hal_data->acs.clm_ratio[ch_idx], + hal_data->acs.nhm_ratio[ch_idx]); + } +} +void rtw_acs_current_info_dump(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 ch, cen_ch, bw, offset; + + _RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION); + + ch = rtw_get_oper_ch(adapter); + bw = rtw_get_oper_bw(adapter); + offset = rtw_get_oper_choffset(adapter); + + _RTW_PRINT_SEL(sel, "Current Channel:%d\n", ch); + if ((bw == CHANNEL_WIDTH_80) ||(bw == CHANNEL_WIDTH_40)) { + cen_ch = rtw_get_center_ch(ch, bw, offset); + _RTW_PRINT_SEL(sel, "Center Channel:%d\n", cen_ch); + } + + _RTW_PRINT_SEL(sel, "Current BW %s\n", ch_width_str(bw)); + if (0) + _RTW_PRINT_SEL(sel, "Current IGI 0x%02x\n", rtw_phydm_get_cur_igi(adapter)); + _RTW_PRINT_SEL(sel, "CLM:%d, NHM:%d\n\n", + hal_data->acs.cur_ch_clm_ratio, hal_data->acs.cur_ch_nhm_ratio); +} + +void rtw_acs_update_current_info(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + hal_data->acs.cur_ch_clm_ratio = rtw_phydm_clm_ratio(adapter); + hal_data->acs.cur_ch_nhm_ratio = rtw_phydm_nhm_ratio(adapter); + + #ifdef CONFIG_RTW_ACS_DBG + rtw_acs_current_info_dump(RTW_DBGDUMP, adapter); + #endif +} +#endif /*CONFIG_RTW_ACS*/ + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +void rtw_noise_monitor_version_dump(void *sel, _adapter *adapter) +{ + _RTW_PRINT_SEL(sel, "RTK_NOISE_MONITOR VER_%d\n", RTK_NOISE_MONITOR_VERSION); +} +void rtw_nm_enable(_adapter *adapter) +{ + SET_NM_STATE(adapter, NM_ENABLE); +} +void rtw_nm_disable(_adapter *adapter) +{ + SET_NM_STATE(adapter, NM_DISABLE); +} +void rtw_noise_info_dump(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + u8 max_chan_nums = rfctl->max_chan_nums; + u8 ch_idx, ch_num; + + _RTW_PRINT_SEL(sel, "========== NM (VER-%d) ==========\n", RTK_NOISE_MONITOR_VERSION); + + _RTW_PRINT_SEL(sel, "%5s %3s %3s %10s", "Index", "CH", "BSS", "Noise(dBm)\n"); + + _rtw_bss_nums_count(adapter, hal_data->nm.bss_nums); + + for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) { + ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx); + _RTW_PRINT_SEL(sel, "%5d %3d %3d %10d\n", + ch_idx, ch_num, hal_data->nm.bss_nums[ch_idx], + hal_data->nm.noise[ch_idx]); + } +} + +void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct dm_struct *phydm = &hal_data->odmpriv; + int chan_idx = -1; + s16 noise = 0; + + #ifdef DBG_NOISE_MONITOR + RTW_INFO("[NM] chan(%d)-PauseDIG:%s, IGIValue:0x%02x, max_time:%d (ms)\n", + chan, (is_pause_dig) ? "Y" : "N", igi_value, max_time); + #endif + + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan); + return; + } + noise = odm_inband_noise_monitor(phydm, is_pause_dig, igi_value, max_time); /*dBm*/ + + hal_data->nm.noise[chan_idx] = noise; + + #ifdef DBG_NOISE_MONITOR + RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, hal_data->nm.noise[chan_idx]); + + RTW_INFO("[NM] noise_a = %d, noise_b = %d noise_all:%d\n", + phydm->noise_level.noise[RF_PATH_A], + phydm->noise_level.noise[RF_PATH_B], + phydm->noise_level.noise_all); + #endif /*DBG_NOISE_MONITOR*/ +} + +s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + s16 noise = 0; + int chan_idx = -1; + + chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan); + if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) { + RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan); + return noise; + } + noise = hal_data->nm.noise[chan_idx]; + + #ifdef DBG_NOISE_MONITOR + RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, noise); + #endif/*DBG_NOISE_MONITOR*/ + return noise; +} +s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + s16 noise = 0; + + if (ch_idx >= MAX_CHANNEL_NUM) { + RTW_ERR("[NM] %s ch_idx(%d) is invalid\n", __func__, ch_idx); + return noise; + } + noise = hal_data->nm.noise[ch_idx]; + + #ifdef DBG_NOISE_MONITOR + RTW_INFO("[NM] %s ch_idx %d, noise = %d (dBm)\n", __func__, ch_idx, noise); + #endif/*DBG_NOISE_MONITOR*/ + return noise; +} + +s16 rtw_noise_measure_curchan(_adapter *padapter) +{ + s16 noise = 0; + u8 igi_value = 0x1E; + u32 max_time = 100;/* ms */ + u8 is_pause_dig = _TRUE; + u8 cur_chan = rtw_get_oper_ch(padapter); + + if (rtw_linked_check(padapter) == _FALSE) + return noise; + + rtw_ps_deny(padapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(padapter); + rtw_noise_measure(padapter, cur_chan, is_pause_dig, igi_value, max_time); + noise = rtw_noise_query_by_chan_num(padapter, cur_chan); + rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); + + return noise; +} +#endif /*CONFIG_BACKGROUND_NOISE_MONITOR*/ + diff --git a/hal/hal_dm_acs.h b/hal/hal_dm_acs.h new file mode 100644 index 0000000..871c144 --- /dev/null +++ b/hal/hal_dm_acs.h @@ -0,0 +1,167 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __HAL_DM_ACS_H__ +#define __HAL_DM_ACS_H__ +#ifdef CONFIG_RTW_ACS +#define RTK_ACS_VERSION 3 + +#if (RTK_ACS_VERSION == 3) +enum NHM_PID { + NHM_PID_ACS, + NHM_PID_IEEE_11K_HIGH, + NHM_PID_IEEE_11K_LOW, +}; + +#define init_clm_param(clm, app, lv, time) \ + do {\ + clm.clm_app = app;\ + clm.clm_lv = lv;\ + clm.mntr_time = time;\ + } while (0) + +#define init_nhm_param(nhm, txon, cca, cnt_opt, app, lv, time) \ + do {\ + nhm.incld_txon = txon;\ + nhm.incld_cca = cca;\ + nhm.div_opt = cnt_opt;\ + nhm.nhm_app = app;\ + nhm.nhm_lv = lv;\ + nhm.mntr_time = time;\ + } while (0) + + +#define init_acs_clm(clm, time) \ + init_clm_param(clm, CLM_ACS, CLM_LV_2, time) + +#define init_acs_nhm(nhm, time) \ + init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, NHM_ACS, NHM_LV_2, time) + +#define init_11K_high_nhm(nhm, time) \ + init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_HIGH, NHM_LV_2, time) + +#define init_11K_low_nhm(nhm, time) \ + init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_LOW, NHM_LV_2, time) + + +#endif /*(RTK_ACS_VERSION == 3)*/ +void rtw_acs_version_dump(void *sel, _adapter *adapter); +extern void phydm_ccx_monitor_trigger(void *p_dm_void, u16 monitor_time); +extern void phydm_ccx_monitor_result(void *p_dm_void); + +#define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state)) +#define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state)) +#define IS_ACS_ENABLE(padapter) ((GET_ACS_STATE(padapter) == ACS_ENABLE) ? _TRUE : _FALSE) + +enum ACS_STATE { + ACS_DISABLE, + ACS_ENABLE, +}; + +#define ACS_BW_20M BIT(0) +#define ACS_BW_40M BIT(1) +#define ACS_BW_80M BIT(2) +#define ACS_BW_160M BIT(3) + +struct auto_chan_sel { + ATOMIC_T state; + u8 trigger_ch; + bool triggered; + u8 clm_ratio[MAX_CHANNEL_NUM]; + u8 nhm_ratio[MAX_CHANNEL_NUM]; + #if (RTK_ACS_VERSION == 3) + u8 nhm[MAX_CHANNEL_NUM][NHM_RPT_NUM]; + #endif + u8 bss_nums[MAX_CHANNEL_NUM]; + u8 interference_time[MAX_CHANNEL_NUM]; + u8 cur_ch_clm_ratio; + u8 cur_ch_nhm_ratio; + u8 best_chan_5g; + u8 best_chan_24g; + + #if (RTK_ACS_VERSION == 3) + u8 trig_rst; + struct env_trig_rpt trig_rpt; + #endif + + #ifdef CONFIG_RTW_ACS_DBG + RT_SCAN_TYPE scan_type; + u16 scan_time; + u8 igi; + u8 bw; + #endif +}; + +#define rtw_acs_get_best_chan_24g(adapter) (GET_HAL_DATA(adapter)->acs.best_chan_24g) +#define rtw_acs_get_best_chan_5g(adapter) (GET_HAL_DATA(adapter)->acs.best_chan_5g) + +#ifdef CONFIG_RTW_ACS_DBG +#define rtw_is_acs_passiv_scan(adapter) (((GET_HAL_DATA(adapter)->acs.scan_type) == SCAN_PASSIVE) ? _TRUE : _FALSE) + +#define rtw_acs_get_adv_st(adapter) (GET_HAL_DATA(adapter)->acs.scan_time) +#define rtw_is_acs_st_valid(adapter) ((GET_HAL_DATA(adapter)->acs.scan_time) ? _TRUE : _FALSE) + +#define rtw_acs_get_adv_igi(adapter) (GET_HAL_DATA(adapter)->acs.igi) +u8 rtw_is_acs_igi_valid(_adapter *adapter); + +#define rtw_acs_get_adv_bw(adapter) (GET_HAL_DATA(adapter)->acs.bw) + +void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw); +void rtw_acs_adv_reset(_adapter *adapter); +#endif + +u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan); +u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx); +u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan); +u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx); + +void rtw_acs_reset(_adapter *adapter); +void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid); +void rtw_acs_get_rst(_adapter *adapter); +void rtw_acs_select_best_chan(_adapter *adapter); +void rtw_acs_info_dump(void *sel, _adapter *adapter); +void rtw_acs_update_current_info(_adapter *adapter); +void rtw_acs_chan_info_dump(void *sel, _adapter *adapter); +void rtw_acs_current_info_dump(void *sel, _adapter *adapter); + +void rtw_acs_start(_adapter *adapter); +void rtw_acs_stop(_adapter *adapter); + +#endif /*CONFIG_RTW_ACS*/ + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +#define RTK_NOISE_MONITOR_VERSION 3 +#define GET_NM_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->nm.state)) +#define SET_NM_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->nm.state, set_state)) +#define IS_NM_ENABLE(padapter) ((GET_NM_STATE(padapter) == NM_ENABLE) ? _TRUE : _FALSE) + +enum NM_STATE { + NM_DISABLE, + NM_ENABLE, +}; + +struct noise_monitor { + ATOMIC_T state; + s16 noise[MAX_CHANNEL_NUM]; + u8 bss_nums[MAX_CHANNEL_NUM]; +}; +void rtw_nm_enable(_adapter *adapter); +void rtw_nm_disable(_adapter *adapter); +void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time); +s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan); +s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx); +s16 rtw_noise_measure_curchan(_adapter *padapter); +void rtw_noise_info_dump(void *sel, _adapter *adapter); +#endif +#endif /* __HAL_DM_ACS_H__ */ diff --git a/hal/hal_halmac.c b/hal/hal_halmac.c index f1142ce..58e0733 100644 --- a/hal/hal_halmac.c +++ b/hal/hal_halmac.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2018 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,23 +11,25 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_HALMAC_C_ #include /* PADAPTER, struct dvobj_priv, SDIO_ERR_VAL8 and etc. */ #include /* efuse, PHAL_DATA_TYPE and etc. */ -#include "halmac/halmac_api.h" /* HALMAC_FW_SIZE_MAX_88XX and etc. */ #include "hal_halmac.h" /* dvobj_to_halmac() and ect. */ +/* + * HALMAC take return value 0 for fail and 1 for success to replace + * _FALSE/_TRUE after V1_04_09 + */ +#define RTW_HALMAC_FAIL 0 +#define RTW_HALMAC_SUCCESS 1 + #define DEFAULT_INDICATOR_TIMELMT 1000 /* ms */ -#define FIRMWARE_MAX_SIZE HALMAC_FW_SIZE_MAX_88XX #define MSG_PREFIX "[HALMAC]" +#define RTW_HALMAC_DLFW_MEM_NO_STOP_TX + /* * Driver API for HALMAC operations */ @@ -101,7 +103,7 @@ static u8 _halmac_sdio_reg_read_8(void *p, u32 offset) struct dvobj_priv *d; u8 *pbuf; u8 val; - int err; + u8 ret; d = (struct dvobj_priv *)p; @@ -111,8 +113,8 @@ static u8 _halmac_sdio_reg_read_8(void *p, u32 offset) if (!pbuf) return val; - err = d->intf_ops->read(d, offset, pbuf, 1, 0); - if (err) { + ret = rtw_sdio_read_cmd53(d, offset, pbuf, 1); + if (ret == _FAIL) { RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); goto exit; } @@ -130,7 +132,7 @@ static u16 _halmac_sdio_reg_read_16(void *p, u32 offset) struct dvobj_priv *d; u8 *pbuf; u16 val; - int err; + u8 ret; d = (struct dvobj_priv *)p; @@ -140,8 +142,8 @@ static u16 _halmac_sdio_reg_read_16(void *p, u32 offset) if (!pbuf) return val; - err = d->intf_ops->read(d, offset, pbuf, 2, 0); - if (err) { + ret = rtw_sdio_read_cmd53(d, offset, pbuf, 2); + if (ret == _FAIL) { RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); goto exit; } @@ -159,7 +161,7 @@ static u32 _halmac_sdio_reg_read_32(void *p, u32 offset) struct dvobj_priv *d; u8 *pbuf; u32 val; - int err; + u8 ret; d = (struct dvobj_priv *)p; @@ -169,8 +171,8 @@ static u32 _halmac_sdio_reg_read_32(void *p, u32 offset) if (!pbuf) return val; - err = d->intf_ops->read(d, offset, pbuf, 4, 0); - if (err) { + ret = rtw_sdio_read_cmd53(d, offset, pbuf, 4); + if (ret == _FAIL) { RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); goto exit; } @@ -186,29 +188,27 @@ static u32 _halmac_sdio_reg_read_32(void *p, u32 offset) static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data) { struct dvobj_priv *d = (struct dvobj_priv *)p; - PSDIO_DATA psdio = &d->intf_data; - u8 *pbuf; - int err; - u8 rst = _FALSE; + u8 ret; + u8 rst = RTW_HALMAC_FAIL; u32 sdio_read_size; + sdio_read_size = RND4(size); - if (sdio_read_size > psdio->block_transfer_len) - sdio_read_size = _RND(sdio_read_size, psdio->block_transfer_len); + sdio_read_size = rtw_sdio_cmd53_align_size(d, sdio_read_size); pbuf = rtw_zmalloc(sdio_read_size); if ((!pbuf) || (!data)) return rst; - err = d->intf_ops->read(d, offset, pbuf, sdio_read_size, 0); - if (err) { - RTW_ERR("%s: [ERROR] I/O FAIL!\n", __func__); + ret = rtw_sdio_read_cmd53(d, offset, pbuf, sdio_read_size); + if (ret == _FAIL) { + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); goto exit; } _rtw_memcpy(data, pbuf, size); - rst = _TRUE; + rst = RTW_HALMAC_SUCCESS; exit: rtw_mfree(pbuf, sdio_read_size); @@ -219,7 +219,7 @@ static void _halmac_sdio_reg_write_8(void *p, u32 offset, u8 val) { struct dvobj_priv *d; u8 *pbuf; - int err; + u8 ret; d = (struct dvobj_priv *)p; @@ -229,8 +229,8 @@ static void _halmac_sdio_reg_write_8(void *p, u32 offset, u8 val) return; _rtw_memcpy(pbuf, &val, 1); - err = d->intf_ops->write(d, offset, pbuf, 1, 0); - if (err) + ret = rtw_sdio_write_cmd53(d, offset, pbuf, 1); + if (ret == _FAIL) RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); rtw_mfree(pbuf, 1); @@ -240,7 +240,7 @@ static void _halmac_sdio_reg_write_16(void *p, u32 offset, u16 val) { struct dvobj_priv *d; u8 *pbuf; - int err; + u8 ret; d = (struct dvobj_priv *)p; @@ -251,8 +251,8 @@ static void _halmac_sdio_reg_write_16(void *p, u32 offset, u16 val) return; _rtw_memcpy(pbuf, &val, 2); - err = d->intf_ops->write(d, offset, pbuf, 2, 0); - if (err) + ret = rtw_sdio_write_cmd53(d, offset, pbuf, 2); + if (ret == _FAIL) RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); rtw_mfree(pbuf, 2); @@ -262,7 +262,7 @@ static void _halmac_sdio_reg_write_32(void *p, u32 offset, u32 val) { struct dvobj_priv *d; u8 *pbuf; - int err; + u8 ret; d = (struct dvobj_priv *)p; @@ -273,13 +273,29 @@ static void _halmac_sdio_reg_write_32(void *p, u32 offset, u32 val) return; _rtw_memcpy(pbuf, &val, 4); - err = d->intf_ops->write(d, offset, pbuf, 4, 0); - if (err) + ret = rtw_sdio_write_cmd53(d, offset, pbuf, 4); + if (ret == _FAIL) RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); rtw_mfree(pbuf, 4); } +static u8 _halmac_sdio_read_cia(void *p, u32 offset) +{ + struct dvobj_priv *d; + u8 data = 0; + u8 ret; + + + d = (struct dvobj_priv *)p; + + ret = rtw_sdio_f0_read(d, offset, &data, 1); + if (ret == _FAIL) + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); + + return data; +} + #else /* !CONFIG_SDIO_HCI */ static u8 _halmac_reg_read_8(void *p, u32 offset) @@ -367,7 +383,7 @@ static void _halmac_reg_write_32(void *p, u32 offset, u32 val) static u8 _halmac_mfree(void *p, void *buffer, u32 size) { rtw_mfree(buffer, size); - return _TRUE; + return RTW_HALMAC_SUCCESS; } static void *_halmac_malloc(void *p, u32 size) @@ -378,30 +394,36 @@ static void *_halmac_malloc(void *p, u32 size) static u8 _halmac_memcpy(void *p, void *dest, void *src, u32 size) { _rtw_memcpy(dest, src, size); - return _TRUE; + return RTW_HALMAC_SUCCESS; } static u8 _halmac_memset(void *p, void *addr, u8 value, u32 size) { _rtw_memset(addr, value, size); - return _TRUE; + return RTW_HALMAC_SUCCESS; } static void _halmac_udelay(void *p, u32 us) { - rtw_udelay_os(us); + /* Most hardware polling wait time < 50us) */ + if (us <= 50) + rtw_udelay_os(us); + else if (us <= 1000) + rtw_usleep_os(us); + else + rtw_msleep_os(RTW_DIV_ROUND_UP(us, 1000)); } static u8 _halmac_mutex_init(void *p, HALMAC_MUTEX *pMutex) { _rtw_mutex_init(pMutex); - return _TRUE; + return RTW_HALMAC_SUCCESS; } static u8 _halmac_mutex_deinit(void *p, HALMAC_MUTEX *pMutex) { _rtw_mutex_free(pMutex); - return _TRUE; + return RTW_HALMAC_SUCCESS; } static u8 _halmac_mutex_lock(void *p, HALMAC_MUTEX *pMutex) @@ -410,15 +432,15 @@ static u8 _halmac_mutex_lock(void *p, HALMAC_MUTEX *pMutex) err = _enter_critical_mutex(pMutex, NULL); if (err) - return _FALSE; + return RTW_HALMAC_FAIL; - return _TRUE; + return RTW_HALMAC_SUCCESS; } static u8 _halmac_mutex_unlock(void *p, HALMAC_MUTEX *pMutex) { _exit_critical_mutex(pMutex, NULL); - return _TRUE; + return RTW_HALMAC_SUCCESS; } static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...) @@ -427,7 +449,7 @@ static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...) va_list args; u8 str[MSG_LEN] = {0}; int err; - u8 ret = _TRUE; + u8 ret = RTW_HALMAC_SUCCESS; str[0] = '\n'; @@ -437,10 +459,10 @@ static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...) /* An output error is encountered */ if (err < 0) - return _FALSE; + return RTW_HALMAC_FAIL; /* Output may be truncated due to size limit */ if ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\n')) - ret = _FALSE; + ret = RTW_HALMAC_FAIL; if (msg_level == HALMAC_DBG_ALWAYS) RTW_PRINT(MSG_PREFIX "%s", str); @@ -461,7 +483,7 @@ static u8 _halmac_buff_print(void *p, u32 msg_type, u8 msg_level, s8 *buf, u32 s else RTW_DBG_DUMP(MSG_PREFIX, buf, size); - return _TRUE; + return RTW_HALMAC_SUCCESS; } @@ -476,14 +498,15 @@ const char *const RTW_HALMAC_FEATURE_NAME[] = { "HALMAC_FEATURE_IQK", "HALMAC_FEATURE_POWER_TRACKING", "HALMAC_FEATURE_PSD", + "HALMAC_FEATURE_FW_SNDING", "HALMAC_FEATURE_ALL" }; -static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STATUS status) +static inline u8 is_valid_id_status(enum halmac_feature_id id, enum halmac_cmd_process_status status) { switch (id) { case HALMAC_FEATURE_CFG_PARA: - RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + RTW_DBG("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); break; case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); @@ -518,6 +541,9 @@ static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STA case HALMAC_FEATURE_PSD: RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); break; + case HALMAC_FEATURE_FW_SNDING: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + break; case HALMAC_FEATURE_ALL: RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); break; @@ -529,7 +555,7 @@ static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STA return _TRUE; } -static int init_halmac_event_with_waittime(struct dvobj_priv *d, HALMAC_FEATURE_ID id, u8 *buf, u32 size, u32 time) +static int init_halmac_event_with_waittime(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size, u32 time) { struct submit_ctx *sctx; @@ -555,12 +581,12 @@ static int init_halmac_event_with_waittime(struct dvobj_priv *d, HALMAC_FEATURE_ return 0; } -static inline int init_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id, u8 *buf, u32 size) +static inline int init_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size) { return init_halmac_event_with_waittime(d, id, buf, size, DEFAULT_INDICATOR_TIMELMT); } -static void free_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) +static void free_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id) { struct submit_ctx *sctx; @@ -573,10 +599,10 @@ static void free_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) rtw_mfree((u8 *)sctx, sizeof(*sctx)); } -static int wait_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) +static int wait_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; struct submit_ctx *sctx; int ret; @@ -602,9 +628,9 @@ static int wait_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) /* * Return: - * Always return _TRUE, HALMAC don't care the return value. + * Always return RTW_HALMAC_SUCCESS, HALMAC don't care the return value. */ -static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size) +static u8 _halmac_event_indication(void *p, enum halmac_feature_id feature_id, enum halmac_cmd_process_status process_status, u8 *buf, u32 size) { struct dvobj_priv *d; PADAPTER adapter; @@ -653,10 +679,10 @@ static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC rtw_sctx_done(&sctx); exit: - return _TRUE; + return RTW_HALMAC_SUCCESS; } -HALMAC_PLATFORM_API rtw_halmac_platform_api = { +struct halmac_platform_api rtw_halmac_platform_api = { /* R/W register */ #ifdef CONFIG_SDIO_HCI .SDIO_CMD52_READ = _halmac_sdio_cmd52_read, @@ -668,16 +694,16 @@ HALMAC_PLATFORM_API rtw_halmac_platform_api = { .SDIO_CMD53_WRITE_8 = _halmac_sdio_reg_write_8, .SDIO_CMD53_WRITE_16 = _halmac_sdio_reg_write_16, .SDIO_CMD53_WRITE_32 = _halmac_sdio_reg_write_32, - + .SDIO_CMD52_CIA_READ = _halmac_sdio_read_cia, #endif /* CONFIG_SDIO_HCI */ -#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCIE_HCI) +#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) .REG_READ_8 = _halmac_reg_read_8, .REG_READ_16 = _halmac_reg_read_16, .REG_READ_32 = _halmac_reg_read_32, .REG_WRITE_8 = _halmac_reg_write_8, .REG_WRITE_16 = _halmac_reg_write_16, .REG_WRITE_32 = _halmac_reg_write_32, -#endif /* CONFIG_USB_HCI || CONFIG_PCIE_HCI */ +#endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */ /* Write data */ #if 0 @@ -707,8 +733,8 @@ HALMAC_PLATFORM_API rtw_halmac_platform_api = { u8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; /* WARNING: pintf_dev should not be null! */ @@ -720,8 +746,8 @@ u8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr) u16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; /* WARNING: pintf_dev should not be null! */ @@ -733,8 +759,8 @@ u16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr) u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; /* WARNING: pintf_dev should not be null! */ @@ -744,29 +770,119 @@ u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr) return api->halmac_reg_read_32(mac, addr); } +static void _read_register(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf) +{ +#if 1 + struct _ADAPTER *a; + u32 i, n; + u16 val16; + u32 val32; + + + a = dvobj_get_primary_adapter(d); + + i = addr & 0x3; + /* Handle address not start from 4 bytes alignment case */ + if (i) { + val32 = cpu_to_le32(rtw_read32(a, addr & ~0x3)); + n = 4 - i; + _rtw_memcpy(buf, ((u8 *)&val32) + i, n); + i = n; + cnt -= n; + } + + while (cnt) { + if (cnt >= 4) + n = 4; + else if (cnt >= 2) + n = 2; + else + n = 1; + cnt -= n; + + switch (n) { + case 1: + buf[i] = rtw_read8(a, addr+i); + i++; + break; + case 2: + val16 = cpu_to_le16(rtw_read16(a, addr+i)); + _rtw_memcpy(&buf[i], &val16, 2); + i += 2; + break; + case 4: + val32 = cpu_to_le32(rtw_read32(a, addr+i)); + _rtw_memcpy(&buf[i], &val32, 4); + i += 4; + break; + } + } +#else + struct _ADAPTER *a; + u32 i; + + + a = dvobj_get_primary_adapter(d); + for (i = 0; i < cnt; i++) + buf[i] = rtw_read8(a, addr + i); +#endif +} + +#ifdef CONFIG_SDIO_HCI +static int _sdio_read_local(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + + + if (buf == NULL) + return -1; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, buf); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: addr=0x%08x cnt=%d err=%d\n", + __FUNCTION__, addr, cnt, status); + return -1; + } + + return 0; +} +#endif /* CONFIG_SDIO_HCI */ + void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem) { -#if defined(CONFIG_SDIO_HCI) - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct dvobj_priv *d; + if (pmem == NULL) { RTW_ERR("pmem is NULL\n"); return; } - /* WARNING: pintf_dev should not be null! */ - mac = dvobj_to_halmac(pintfhdl->pintf_dev); - api = HALMAC_GET_API(mac); - api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, pmem); -#endif + d = pintfhdl->pintf_dev; + +#ifdef CONFIG_SDIO_HCI + if (addr & 0xFFFF0000) { + int err = 0; + + err = _sdio_read_local(d, addr, cnt, pmem); + if (!err) + return; + } +#endif /* CONFIG_SDIO_HCI */ + + _read_register(d, addr, cnt, pmem); } #ifdef CONFIG_SDIO_INDIRECT_ACCESS u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; /* WARNING: pintf_dev should not be null! */ mac = dvobj_to_halmac(pintfhdl->pintf_dev); @@ -778,8 +894,8 @@ u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr) u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; u16 val16 = 0; /* WARNING: pintf_dev should not be null! */ @@ -792,8 +908,8 @@ u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr) u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; + struct halmac_adapter *mac; + struct halmac_api *api; /* WARNING: pintf_dev should not be null! */ @@ -802,13 +918,13 @@ u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr) return api->halmac_reg_read_indirect_32(mac, addr); } -#endif +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ int rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; /* WARNING: pintf_dev should not be null! */ @@ -825,9 +941,9 @@ int rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value) int rtw_halmac_write16(struct intf_hdl *pintfhdl, u32 addr, u16 value) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; /* WARNING: pintf_dev should not be null! */ @@ -844,9 +960,9 @@ int rtw_halmac_write16(struct intf_hdl *pintfhdl, u32 addr, u16 value) int rtw_halmac_write32(struct intf_hdl *pintfhdl, u32 addr, u32 value) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; /* WARNING: pintf_dev should not be null! */ @@ -861,15 +977,58 @@ int rtw_halmac_write32(struct intf_hdl *pintfhdl, u32 addr, u32 value) return -1; } +static int init_write_rsvd_page_size(struct dvobj_priv *d) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + u32 size = 0; + struct halmac_ofld_func_info ofld_info; + enum halmac_ret_status status; + int err = 0; + + +#ifdef CONFIG_USB_HCI + /* for USB do not exceed MAX_CMDBUF_SZ */ + size = 0x1000; +#elif defined(CONFIG_PCI_HCI) + size = MAX_CMDBUF_SZ - TXDESC_OFFSET; +#elif defined(CONFIG_SDIO_HCI) + size = 0x7000; /* 28KB */ +#endif + + /* If size==0, use HALMAC default setting and don't call any function */ + if (!size) + return 0; + + err = rtw_halmac_set_max_dl_fw_size(d, size); + if (err) { + RTW_ERR("%s: Fail to set max download fw size!\n", __FUNCTION__); + return -1; + } + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + _rtw_memset(&ofld_info, 0, sizeof(ofld_info)); + ofld_info.halmac_malloc_max_sz = 0xFFFFFFFF; + ofld_info.rsvd_pg_drv_buf_max_sz = size; + status = api->halmac_ofld_func_cfg(mac, &ofld_info); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: Fail to config offload parameters!\n", __FUNCTION__); + return -1; + } + + return 0; +} + static int init_priv(struct halmacpriv *priv) { struct halmac_indicator *indicator; u32 count, size; - size = sizeof(*priv); - _rtw_memset(priv, 0, size); - + if (priv->indicator) + RTW_WARN("%s: HALMAC private data is not CLEAR!\n", __FUNCTION__); count = HALMAC_FEATURE_ALL + 1; size = sizeof(*indicator) * count; indicator = (struct halmac_indicator *)rtw_zmalloc(size); @@ -914,10 +1073,10 @@ static void deinit_priv(struct halmacpriv *priv) } #ifdef CONFIG_SDIO_HCI -static enum _HALMAC_SDIO_SPEC_VER _sdio_ver_drv2halmac(struct dvobj_priv *d) +static enum halmac_sdio_spec_ver _sdio_ver_drv2halmac(struct dvobj_priv *d) { bool v3; - enum _HALMAC_SDIO_SPEC_VER ver; + enum halmac_sdio_spec_ver ver; v3 = rtw_is_sdio30(dvobj_get_primary_adapter(d)); @@ -930,45 +1089,47 @@ static enum _HALMAC_SDIO_SPEC_VER _sdio_ver_drv2halmac(struct dvobj_priv *d) } #endif /* CONFIG_SDIO_HCI */ -void rtw_dump_halmac_info(void *sel) +void rtw_halmac_get_version(char *str, u32 len) { - HALMAC_RET_STATUS status; - HALMAC_VER halmac_version; + enum halmac_ret_status status; + struct halmac_ver ver; + - status = halmac_get_version(&halmac_version); + status = halmac_get_version(&ver); if (status != HALMAC_RET_SUCCESS) return; - RTW_PRINT_SEL(sel, "HALMAC VER -%x.%x.%x\n", halmac_version.major_ver, halmac_version.prototype_ver, halmac_version.minor_ver); + rtw_sprintf(str, len, "V%d_%02d_%02d", + ver.major_ver, ver.prototype_ver, ver.minor_ver); } -int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api) +int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api) { - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_INTERFACE intf; - HALMAC_RET_STATUS status; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_interface intf; + enum halmac_ret_status status; int err = 0; #ifdef CONFIG_SDIO_HCI - HALMAC_SDIO_HW_INFO info; + struct halmac_sdio_hw_info info; #endif /* CONFIG_SDIO_HCI */ halmac = dvobj_to_halmac(d); if (halmac) { - err = 0; - goto out; + RTW_WARN("%s: initialize already completed!\n", __FUNCTION__); + goto error; } err = init_priv(&d->hmpriv); if (err) - goto out; + goto error; #ifdef CONFIG_SDIO_HCI intf = HALMAC_INTERFACE_SDIO; #elif defined(CONFIG_USB_HCI) intf = HALMAC_INTERFACE_USB; -#elif defined(CONFIG_PCIE_HCI) +#elif defined(CONFIG_PCI_HCI) intf = HALMAC_INTERFACE_PCIE; #else #warning "INTERFACE(CONFIG_XXX_HCI) not be defined!!" @@ -978,174 +1139,1481 @@ int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api) if (HALMAC_RET_SUCCESS != status) { RTW_ERR("%s: halmac_init_adapter fail!(status=%d)\n", __FUNCTION__, status); err = -1; - goto out; + if (halmac) + goto deinit; + goto free; } dvobj_set_halmac(d, halmac); + status = api->halmac_interface_integration_tuning(halmac); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: halmac_interface_integration_tuning fail!(status=%d)\n", __FUNCTION__, status); + err = -1; + goto deinit; + } + status = api->halmac_phy_cfg(halmac, HALMAC_INTF_PHY_PLATFORM_ALL); if (status != HALMAC_RET_SUCCESS) { RTW_ERR("%s: halmac_phy_cfg fail!(status=%d)\n", __FUNCTION__, status); err = -1; - goto out; + goto deinit; } + init_write_rsvd_page_size(d); + #ifdef CONFIG_SDIO_HCI + _rtw_memset(&info, 0, sizeof(info)); info.spec_ver = _sdio_ver_drv2halmac(d); - /* clock unit is MHz */ + /* Convert clock speed unit to MHz from Hz */ info.clock_speed = RTW_DIV_ROUND_UP(rtw_sdio_get_clock(d), 1000000); - RTW_DBG("%s: SDIO clock=%uMHz ver=%u\n", __FUNCTION__, info.clock_speed, info.spec_ver+2); + info.block_size = rtw_sdio_get_block_size(d); + RTW_DBG("%s: SDIO ver=%u clock=%uMHz blk_size=%u bytes\n", + __FUNCTION__, info.spec_ver+2, info.clock_speed, + info.block_size); status = api->halmac_sdio_hw_info(halmac, &info); if (status != HALMAC_RET_SUCCESS) { - RTW_ERR("%s: halmac_sdio_hw_info fail!(status=%d)\n", __FUNCTION__, status); + RTW_ERR("%s: halmac_sdio_hw_info fail!(status=%d)\n", + __FUNCTION__, status); err = -1; - goto out; + goto deinit; } #endif /* CONFIG_SDIO_HCI */ -out: - if (err) - rtw_halmac_deinit_adapter(d); + return 0; + +deinit: + status = halmac_deinit_adapter(halmac); + dvobj_set_halmac(d, NULL); + if (status != HALMAC_RET_SUCCESS) + RTW_ERR("%s: halmac_deinit_adapter fail!(status=%d)\n", + __FUNCTION__, status); + +free: + deinit_priv(&d->hmpriv); +error: return err; } int rtw_halmac_deinit_adapter(struct dvobj_priv *d) { - PHALMAC_ADAPTER halmac; - HALMAC_RET_STATUS status; + struct halmac_adapter *halmac; + enum halmac_ret_status status; int err = 0; halmac = dvobj_to_halmac(d); - if (!halmac) { - err = 0; - goto out; + if (halmac) { + status = halmac_deinit_adapter(halmac); + dvobj_set_halmac(d, NULL); + if (status != HALMAC_RET_SUCCESS) + err = -1; } deinit_priv(&d->hmpriv); - status = halmac_deinit_adapter(halmac); - dvobj_set_halmac(d, NULL); - if (status != HALMAC_RET_SUCCESS) { - err = -1; - goto out; - } - -out: return err; } -/* - * Description: - * Power on device hardware. - * [Notice!] If device's power state is on before, - * it would be power off first and turn on power again. - * - * Return: - * 0 power on success - * -1 power on fail - * -2 power state unchange - */ -int rtw_halmac_poweron(struct dvobj_priv *d) +static inline enum halmac_portid _hw_port_drv2halmac(enum _hw_port hwport) { - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - int err = -1; + enum halmac_portid port = HALMAC_PORTID_NUM; - halmac = dvobj_to_halmac(d); - if (!halmac) - goto out; - - api = HALMAC_GET_API(halmac); - - status = api->halmac_pre_init_system_cfg(halmac); - if (status != HALMAC_RET_SUCCESS) - goto out; - -#ifdef CONFIG_SDIO_HCI - status = api->halmac_sdio_cmd53_4byte(halmac, HALMAC_SDIO_CMD53_4BYTE_MODE_RW); - if (status != HALMAC_RET_SUCCESS) - goto out; -#endif /* CONFIG_SDIO_HCI */ - - status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON); - if (HALMAC_RET_PWR_UNCHANGE == status) { - /* - * Work around for warm reboot but device not power off, - * but it would also fall into this case when auto power on is enabled. - */ - api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF); - status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON); - RTW_WARN("%s: Power state abnormal, try to recover...%s\n", - __FUNCTION__, (HALMAC_RET_SUCCESS == status)?"OK":"FAIL!"); - } - if (HALMAC_RET_SUCCESS != status) { - if (HALMAC_RET_PWR_UNCHANGE == status) - err = -2; - goto out; + switch (hwport) { + case HW_PORT0: + port = HALMAC_PORTID0; + break; + case HW_PORT1: + port = HALMAC_PORTID1; + break; + case HW_PORT2: + port = HALMAC_PORTID2; + break; + case HW_PORT3: + port = HALMAC_PORTID3; + break; + case HW_PORT4: + port = HALMAC_PORTID4; + break; + default: + break; } - status = api->halmac_init_system_cfg(halmac); - if (status != HALMAC_RET_SUCCESS) - goto out; - - err = 0; -out: - return err; + return port; } -/* - * Description: - * Power off device hardware. - * - * Return: - * 0 Power off success - * -1 Power off fail - */ -int rtw_halmac_poweroff(struct dvobj_priv *d) +static enum halmac_network_type_select _network_type_drv2halmac(u8 type) { - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - int err = -1; + enum halmac_network_type_select network = HALMAC_NETWORK_UNDEFINE; - halmac = dvobj_to_halmac(d); - if (!halmac) - goto out; + switch (type) { + case _HW_STATE_NOLINK_: + case _HW_STATE_MONITOR_: + network = HALMAC_NETWORK_NO_LINK; + break; - api = HALMAC_GET_API(halmac); + case _HW_STATE_ADHOC_: + network = HALMAC_NETWORK_ADHOC; + break; - status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF); - if ((HALMAC_RET_SUCCESS != status) - && (HALMAC_RET_PWR_UNCHANGE != status)) - goto out; + case _HW_STATE_STATION_: + network = HALMAC_NETWORK_INFRASTRUCTURE; + break; - err = 0; -out: - return err; + case _HW_STATE_AP_: + network = HALMAC_NETWORK_AP; + break; + } + + return network; } -/* - * Note: - * When this function return, the register REG_RCR may be changed. - */ -int rtw_halmac_config_rx_info(struct dvobj_priv *d, HALMAC_DRV_INFO info) +static u8 _network_type_halmac2drv(enum halmac_network_type_select network) { - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - int err = -1; + u8 type = _HW_STATE_NOLINK_; + + + switch (network) { + case HALMAC_NETWORK_NO_LINK: + case HALMAC_NETWORK_UNDEFINE: + type = _HW_STATE_NOLINK_; + break; + + case HALMAC_NETWORK_ADHOC: + type = _HW_STATE_ADHOC_; + break; + + case HALMAC_NETWORK_INFRASTRUCTURE: + type = _HW_STATE_STATION_; + break; + + case HALMAC_NETWORK_AP: + type = _HW_STATE_AP_; + break; + } + + return type; +} + +static void _beacon_ctrl_halmac2drv(struct halmac_bcn_ctrl *ctrl, + struct rtw_halmac_bcn_ctrl *drv_ctrl) +{ + drv_ctrl->rx_bssid_fit = ctrl->dis_rx_bssid_fit ? 0 : 1; + drv_ctrl->txbcn_rpt = ctrl->en_txbcn_rpt ? 1 : 0; + drv_ctrl->tsf_update = ctrl->dis_tsf_udt ? 0 : 1; + drv_ctrl->enable_bcn = ctrl->en_bcn ? 1 : 0; + drv_ctrl->rxbcn_rpt = ctrl->en_rxbcn_rpt ? 1 : 0; + drv_ctrl->p2p_ctwin = ctrl->en_p2p_ctwin ? 1 : 0; + drv_ctrl->p2p_bcn_area = ctrl->en_p2p_bcn_area ? 1 : 0; +} + +static void _beacon_ctrl_drv2halmac(struct rtw_halmac_bcn_ctrl *drv_ctrl, + struct halmac_bcn_ctrl *ctrl) +{ + ctrl->dis_rx_bssid_fit = drv_ctrl->rx_bssid_fit ? 0 : 1; + ctrl->en_txbcn_rpt = drv_ctrl->txbcn_rpt ? 1 : 0; + ctrl->dis_tsf_udt = drv_ctrl->tsf_update ? 0 : 1; + ctrl->en_bcn = drv_ctrl->enable_bcn ? 1 : 0; + ctrl->en_rxbcn_rpt = drv_ctrl->rxbcn_rpt ? 1 : 0; + ctrl->en_p2p_ctwin = drv_ctrl->p2p_ctwin ? 1 : 0; + ctrl->en_p2p_bcn_area = drv_ctrl->p2p_bcn_area ? 1 : 0; +} + +int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_get_hw_value(mac, hw_id, pvalue); + if (HALMAC_RET_SUCCESS != status) + return -1; + + return 0; +} + +/** + * rtw_halmac_get_tx_fifo_size() - TX FIFO size + * @d: struct dvobj_priv* + * @size: TX FIFO size, unit is byte. + * + * Get TX FIFO size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFIFO_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/** + * rtw_halmac_get_rx_fifo_size() - RX FIFO size + * @d: struct dvobj_priv* + * @size: RX FIFO size, unit is byte + * + * Get RX FIFO size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_RXFIFO_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/** + * rtw_halmac_get_rsvd_drv_pg_bndy() - Reserve page boundary of driver + * @d: struct dvobj_priv* + * @size: Page size, unit is byte + * + * Get reserve page boundary of driver from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u16 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *bndy = val; + + return 0; +} + +/** + * rtw_halmac_get_page_size() - Page size + * @d: struct dvobj_priv* + * @size: Page size, unit is byte + * + * Get TX/RX page size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_PAGE_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/** + * rtw_halmac_get_tx_agg_align_size() - TX aggregation align size + * @d: struct dvobj_priv* + * @size: TX aggregation align size, unit is byte + * + * Get TX aggregation align size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u16 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_AGG_ALIGN_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/** + * rtw_halmac_get_rx_agg_align_size() - RX aggregation align size + * @d: struct dvobj_priv* + * @size: RX aggregation align size, unit is byte + * + * Get RX aggregation align size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u8 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_AGG_ALIGN_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/* + * Description: + * Get RX driver info size. RX driver info is a small memory space between + * scriptor and RX payload. + * + * +-------------------------+ + * | RX descriptor | + * | usually 24 bytes | + * +-------------------------+ + * | RX driver info | + * | depends on driver cfg | + * +-------------------------+ + * | RX paylad | + * | | + * +-------------------------+ + * + * Parameter: + * d pointer to struct dvobj_priv of driver + * sz rx driver info size in bytes. + * + * Rteurn: + * 0 Success + * other Fail + */ +int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *d, u8 *sz) +{ + enum halmac_ret_status status; + struct halmac_adapter *halmac = dvobj_to_halmac(d); + struct halmac_api *api = HALMAC_GET_API(halmac); + u8 dw = 0; + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *sz = dw * 8; + return 0; +} + +/** + * rtw_halmac_get_tx_desc_size() - TX descriptor size + * @d: struct dvobj_priv* + * @size: TX descriptor size, unit is byte. + * + * Get TX descriptor size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_DESC_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/** + * rtw_halmac_get_rx_desc_size() - RX descriptor size + * @d: struct dvobj_priv* + * @size: RX descriptor size, unit is byte. + * + * Get RX descriptor size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_DESC_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + + +/** + * rtw_halmac_get_fw_max_size() - Firmware MAX size + * @d: struct dvobj_priv* + * @size: MAX Firmware size, unit is byte. + * + * Get Firmware MAX size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +static int rtw_halmac_get_fw_max_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_FW_MAX_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +/** + * rtw_halmac_get_ori_h2c_size() - Original H2C MAX size + * @d: struct dvobj_priv* + * @size: H2C MAX size, unit is byte. + * + * Get original H2C MAX size(byte) from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_ORI_H2C_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + + return 0; +} + +int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size) +{ + enum halmac_ret_status status; + struct halmac_adapter *halmac; + struct halmac_api *api; + u8 val; + + + if (!size) + return -1; + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_OQT_SIZE, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *size = val; + return 0; +} + +int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num) +{ + enum halmac_ret_status status; + struct halmac_adapter *halmac; + struct halmac_api *api; + u8 val; + + + if (!num) + return -1; + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_QUEUE_NUM, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *num = val; + return 0; +} + +/** + * rtw_halmac_get_mac_address() - Get MAC address of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @addr: buffer for storing MAC address + * + * Get MAC address of specific port from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + union halmac_wlan_addr hwa; + enum halmac_ret_status status; + int err = -1; + + + if (!addr) + goto out; + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + _rtw_memset(&hwa, 0, sizeof(hwa)); + + status = api->halmac_get_mac_addr(halmac, port, &hwa); + if (status != HALMAC_RET_SUCCESS) + goto out; + + _rtw_memcpy(addr, hwa.addr, 6); + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_get_network_type() - Get network type of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @type: buffer to put network type (_HW_STATE_*) + * + * Get network type of specific port from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type) +{ +#if 0 + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + enum halmac_network_type_select network; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + network = HALMAC_NETWORK_UNDEFINE; + + status = api->halmac_get_net_type(halmac, port, &network); + if (status != HALMAC_RET_SUCCESS) + goto out; + + *type = _network_type_halmac2drv(network); + + err = 0; +out: + return err; +#else + struct _ADAPTER *a; + enum halmac_portid port; + enum halmac_network_type_select network; + u32 val; + int err = -1; + + + a = dvobj_get_primary_adapter(d); + port = _hw_port_drv2halmac(hwport); + network = HALMAC_NETWORK_UNDEFINE; + + switch (port) { + case HALMAC_PORTID0: + val = rtw_read32(a, REG_CR); + network = BIT_GET_NETYPE0(val); + break; + + case HALMAC_PORTID1: + val = rtw_read32(a, REG_CR); + network = BIT_GET_NETYPE1(val); + break; + + case HALMAC_PORTID2: + val = rtw_read32(a, REG_CR_EXT); + network = BIT_GET_NETYPE2(val); + break; + + case HALMAC_PORTID3: + val = rtw_read32(a, REG_CR_EXT); + network = BIT_GET_NETYPE3(val); + break; + + case HALMAC_PORTID4: + val = rtw_read32(a, REG_CR_EXT); + network = BIT_GET_NETYPE4(val); + break; + + default: + goto out; + } + + *type = _network_type_halmac2drv(network); + + err = 0; +out: + return err; +#endif +} + +/** + * rtw_halmac_get_bcn_ctrl() - Get beacon control setting of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @bcn_ctrl: setting of beacon control + * + * Get beacon control setting of specific port from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, + struct rtw_halmac_bcn_ctrl *bcn_ctrl) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + struct halmac_bcn_ctrl ctrl; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + _rtw_memset(&ctrl, 0, sizeof(ctrl)); + + status = api->halmac_rw_bcn_ctrl(halmac, port, 0, &ctrl); + if (status != HALMAC_RET_SUCCESS) + goto out; + _beacon_ctrl_halmac2drv(&ctrl, bcn_ctrl); + + err = 0; +out: + return err; +} + +/* + * Note: + * When this function return, the register REG_RCR may be changed. + */ +int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_cfg_drv_info(halmac, info); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_max_dl_fw_size() - Set the MAX download firmware size + * @d: struct dvobj_priv* + * @size: the max download firmware size in one I/O + * + * Set the max download firmware size in one I/O. + * Please also consider the max size of the callback function "SEND_RSVD_PAGE" + * could accept, because download firmware would call "SEND_RSVD_PAGE" to send + * firmware to IC. + * + * If the value of "size" is not even, it would be rounded down to nearest + * even, and 0 and 1 are both invalid value. + * + * Return 0 for setting OK, otherwise fail. + */ +int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + + + if (!size || (size == 1)) + return -1; + + mac = dvobj_to_halmac(d); + if (!mac) { + RTW_ERR("%s: HALMAC is not ready!!\n", __FUNCTION__); + return -1; + } + api = HALMAC_GET_API(mac); + + size &= ~1; /* round down to even */ + status = api->halmac_cfg_max_dl_size(mac, size); + if (status != HALMAC_RET_SUCCESS) { + RTW_WARN("%s: Fail to cfg_max_dl_size(%d), err=%d!!\n", + __FUNCTION__, size, status); + return -1; + } + + return 0; +} + +/** + * rtw_halmac_set_mac_address() - Set mac address of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @addr: mac address + * + * Set self mac address of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + union halmac_wlan_addr hwa; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + port = _hw_port_drv2halmac(hwport); + _rtw_memset(&hwa, 0, sizeof(hwa)); + _rtw_memcpy(hwa.addr, addr, 6); + + status = api->halmac_cfg_mac_addr(halmac, port, &hwa); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_bssid() - Set BSSID of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @addr: BSSID, mac address of AP + * + * Set BSSID of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + union halmac_wlan_addr hwa; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + + _rtw_memset(&hwa, 0, sizeof(hwa)); + _rtw_memcpy(hwa.addr, addr, 6); + status = api->halmac_cfg_bssid(halmac, port, &hwa); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_tx_address() - Set transmitter address of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @addr: transmitter address + * + * Set transmitter address of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + union halmac_wlan_addr hwa; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + _rtw_memset(&hwa, 0, sizeof(hwa)); + _rtw_memcpy(hwa.addr, addr, 6); + + status = api->halmac_cfg_transmitter_addr(halmac, port, &hwa); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_network_type() - Set network type of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @type: network type (_HW_STATE_*) + * + * Set network type of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + enum halmac_network_type_select network; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + network = _network_type_drv2halmac(type); + + status = api->halmac_cfg_net_type(halmac, port, network); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_reset_tsf() - Reset TSF timer of specific port + * @d: struct dvobj_priv* + * @hwport: port + * + * Notice HALMAC to reset timing synchronization function(TSF) timer of + * specific port. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + + status = api->halmac_cfg_tsf_rst(halmac, port); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_bcn_interval() - Set beacon interval of each port + * @d: struct dvobj_priv* + * @hwport: port + * @space: beacon interval, unit is ms + * + * Set beacon interval of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, + u32 interval) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + + status = api->halmac_cfg_bcn_space(halmac, port, interval); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_bcn_ctrl() - Set beacon control setting of each port + * @d: struct dvobj_priv* + * @hwport: port + * @bcn_ctrl: setting of beacon control + * + * Set beacon control setting of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, + struct rtw_halmac_bcn_ctrl *bcn_ctrl) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + struct halmac_bcn_ctrl ctrl; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + _rtw_memset(&ctrl, 0, sizeof(ctrl)); + _beacon_ctrl_drv2halmac(bcn_ctrl, &ctrl); + + status = api->halmac_rw_bcn_ctrl(halmac, port, 1, &ctrl); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/** + * rtw_halmac_set_aid() - Set association identifier(AID) of specific port + * @d: struct dvobj_priv* + * @hwport: port + * @aid: Association identifier + * + * Set association identifier(AID) of specific port to HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_portid port; + enum halmac_ret_status status; + int err = -1; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + +#if 0 + status = api->halmac_cfg_aid(halmac, port, aid); + if (status != HALMAC_RET_SUCCESS) + goto out; +#else +{ + struct _ADAPTER *a; + u32 addr; + u16 val; + + a = dvobj_get_primary_adapter(d); + + switch (port) { + case 0: + addr = REG_BCN_PSR_RPT; + val = rtw_read16(a, addr); + val = BIT_SET_PS_AID_0(val, aid); + rtw_write16(a, addr, val); + break; + + case 1: + addr = REG_BCN_PSR_RPT1; + val = rtw_read16(a, addr); + val = BIT_SET_PS_AID_1(val, aid); + rtw_write16(a, addr, val); + break; + + case 2: + addr = REG_BCN_PSR_RPT2; + val = rtw_read16(a, addr); + val = BIT_SET_PS_AID_2(val, aid); + rtw_write16(a, addr, val); + break; + + case 3: + addr = REG_BCN_PSR_RPT3; + val = rtw_read16(a, addr); + val = BIT_SET_PS_AID_3(val, aid); + rtw_write16(a, addr, val); + break; + + case 4: + addr = REG_BCN_PSR_RPT4; + val = rtw_read16(a, addr); + val = BIT_SET_PS_AID_4(val, aid); + rtw_write16(a, addr, val); + break; + + default: + goto out; + } +} +#endif + + err = 0; +out: + return err; +} + +int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw); + if (HALMAC_RET_SUCCESS != status) + return -1; + + return 0; +} + +/** + * rtw_halmac_set_edca() - config edca parameter + * @d: struct dvobj_priv* + * @queue: XMIT_[VO/VI/BE/BK]_QUEUE + * @aifs: Arbitration inter-frame space(AIFS) + * @cw: Contention window(CW) + * @txop: MAX Transmit Opportunity(TXOP) + * + * Return: 0 if process OK, otherwise -1. + */ +int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_acq_id ac; + struct halmac_edca_para edca; + enum halmac_ret_status status; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + switch (queue) { + case XMIT_VO_QUEUE: + ac = HALMAC_ACQ_ID_VO; + break; + case XMIT_VI_QUEUE: + ac = HALMAC_ACQ_ID_VI; + break; + case XMIT_BE_QUEUE: + ac = HALMAC_ACQ_ID_BE; + break; + case XMIT_BK_QUEUE: + ac = HALMAC_ACQ_ID_BK; + break; + default: + return -1; + } + + edca.aifs = aifs; + edca.cw = cw; + edca.txop_limit = txop; + + status = api->halmac_cfg_edca_para(mac, ac, &edca); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +/** + * rtw_halmac_set_rts_full_bw() - Send RTS to all covered channels + * @d: struct dvobj_priv* + * @enable: _TRUE(enable), _FALSE(disable) + * + * Hradware will duplicate RTS packet to all channels which are covered in used + * bandwidth. + * + * Return 0 if process OK, otherwise -1. + */ +int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + u8 full; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + full = (enable == _TRUE) ? 1 : 0; + + status = api->halmac_set_hw_value(mac, HALMAC_HW_RTS_FULL_BW, &full); + if (HALMAC_RET_SUCCESS != status) + return -1; + + return 0; +} + +#ifdef RTW_HALMAC_DBG_POWER_SWITCH +static void _dump_mac_reg(struct dvobj_priv *d, u32 start, u32 end) +{ + struct _ADAPTER *adapter; + int i, j = 1; + + + adapter = dvobj_get_primary_adapter(d); + for (i = start; i < end; i += 4) { + if (j % 4 == 1) + RTW_PRINT("0x%04x", i); + _RTW_PRINT(" 0x%08x ", rtw_read32(adapter, i)); + if ((j++) % 4 == 0) + _RTW_PRINT("\n"); + } +} + +void dump_dbg_val(struct _ADAPTER *a, u32 reg) +{ + u32 v32; + + + rtw_write8(a, 0x3A, reg); + v32 = rtw_read32(a, 0xC0); + RTW_PRINT("0x3A = %02x, 0xC0 = 0x%08x\n",reg, v32); +} + +#ifdef CONFIG_PCI_HCI +static void _dump_pcie_cfg_space(struct dvobj_priv *d) +{ + struct _ADAPTER *padapter = dvobj_get_primary_adapter(d); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + struct pci_dev *bridge_pdev = pdev->bus->self; + + u32 tmp[4] = { 0 }; + u32 i, j; + + RTW_PRINT("\n***** PCI Device Configuration Space *****\n\n"); + + for(i = 0; i < 0x100; i += 0x10) + { + for (j = 0 ; j < 4 ; j++) + pci_read_config_dword(pdev, i + j * 4, tmp+j); + + RTW_PRINT("%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF, + tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF, + tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF, + tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF); + } + + RTW_PRINT("\n***** PCI Host Device Configuration Space*****\n\n"); + + for(i = 0; i < 0x100; i += 0x10) + { + for (j = 0 ; j < 4 ; j++) + pci_read_config_dword(bridge_pdev, i + j * 4, tmp+j); + + RTW_PRINT("%03x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + i, tmp[0] & 0xFF, (tmp[0] >> 8) & 0xFF, (tmp[0] >> 16) & 0xFF, (tmp[0] >> 24) & 0xFF, + tmp[1] & 0xFF, (tmp[1] >> 8) & 0xFF, (tmp[1] >> 16) & 0xFF, (tmp[1] >> 24) & 0xFF, + tmp[2] & 0xFF, (tmp[2] >> 8) & 0xFF, (tmp[2] >> 16) & 0xFF, (tmp[2] >> 24) & 0xFF, + tmp[3] & 0xFF, (tmp[3] >> 8) & 0xFF, (tmp[3] >> 16) & 0xFF, (tmp[3] >> 24) & 0xFF); + } +} +#endif + +static void _dump_mac_reg_for_power_switch(struct dvobj_priv *d, + const char* caller, char* desc) +{ + struct _ADAPTER *a; + u8 v8; + + + RTW_PRINT("%s: %s\n", caller, desc); + RTW_PRINT("======= MAC REG =======\n"); + /* page 0/1 */ + _dump_mac_reg(d, 0x0, 0x200); + _dump_mac_reg(d, 0x300, 0x400); /* also dump page 3 */ + + /* dump debug register */ + a = dvobj_get_primary_adapter(d); + +#ifdef CONFIG_PCI_HCI + _dump_pcie_cfg_space(d); + + v8 = rtw_read8(a, 0xF6) | 0x01; + rtw_write8(a, 0xF6, v8); + RTW_PRINT("0xF6 = %02x\n", v8); + + dump_dbg_val(a, 0x63); + dump_dbg_val(a, 0x64); + dump_dbg_val(a, 0x68); + dump_dbg_val(a, 0x69); + dump_dbg_val(a, 0x6a); + dump_dbg_val(a, 0x6b); + dump_dbg_val(a, 0x71); + dump_dbg_val(a, 0x72); +#endif +} + +static enum halmac_ret_status _power_switch(struct halmac_adapter *halmac, + struct halmac_api *api, + enum halmac_mac_power pwr) +{ + enum halmac_ret_status status; + char desc[80] = {0}; + + + rtw_sprintf(desc, 80, "before calling power %s", + (pwr==HALMAC_MAC_POWER_ON)?"on":"off"); + _dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter, + __FUNCTION__, desc); + + status = api->halmac_mac_power_switch(halmac, pwr); + RTW_PRINT("%s: status=%d\n", __FUNCTION__, status); + + rtw_sprintf(desc, 80, "after calling power %s", + (pwr==HALMAC_MAC_POWER_ON)?"on":"off"); + _dump_mac_reg_for_power_switch((struct dvobj_priv *)halmac->drv_adapter, + __FUNCTION__, desc); + + return status; +} +#else /* !RTW_HALMAC_DBG_POWER_SWITCH */ +#define _power_switch(mac, api, pwr) (api)->halmac_mac_power_switch(mac, pwr) +#endif /* !RTW_HALMAC_DBG_POWER_SWITCH */ + +/* + * Description: + * Power on device hardware. + * [Notice!] If device's power state is on before, + * it would be power off first and turn on power again. + * + * Return: + * 0 power on success + * -1 power on fail + * -2 power state unchange + */ +int rtw_halmac_poweron(struct dvobj_priv *d) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + int err = -1; +#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B) + struct _ADAPTER *a; + u8 v8; + u32 addr; + + a = dvobj_get_primary_adapter(d); +#endif + + halmac = dvobj_to_halmac(d); + if (!halmac) + goto out; + + api = HALMAC_GET_API(halmac); + + status = api->halmac_pre_init_system_cfg(halmac); + if (status != HALMAC_RET_SUCCESS) + goto out; + +#ifdef CONFIG_SDIO_HCI + status = api->halmac_sdio_cmd53_4byte(halmac, HALMAC_SDIO_CMD53_4BYTE_MODE_RW); + if (status != HALMAC_RET_SUCCESS) + goto out; +#endif /* CONFIG_SDIO_HCI */ + +#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B) + addr = 0x3F3; + v8 = rtw_read8(a, addr); + RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8); + /* are we in pcie debug mode? */ + if (!(v8 & BIT(2))) { + RTW_PRINT("%s: Enable pcie debug mode\n", __FUNCTION__); + v8 |= BIT(2); + v8 = rtw_write8(a, addr, v8); + } +#endif + + status = _power_switch(halmac, api, HALMAC_MAC_POWER_ON); + if (HALMAC_RET_PWR_UNCHANGE == status) { + +#if defined(CONFIG_PCI_HCI) && defined(CONFIG_RTL8822B) + addr = 0x3F3; + v8 = rtw_read8(a, addr); + RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8); + + /* are we in pcie debug mode? */ + if (!(v8 & BIT(2))) { + RTW_PRINT("%s: Enable pcie debug mode\n", __FUNCTION__); + v8 |= BIT(2); + v8 = rtw_write8(a, addr, v8); + } else if (v8 & BIT(0)) { + /* DMA stuck */ + addr = 0x1350; + v8 = rtw_read8(a, addr); + RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8); + RTW_PRINT("%s: recover DMA stuck\n", __FUNCTION__); + v8 |= BIT(6); + v8 = rtw_write8(a, addr, v8); + RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v8); + } +#endif + /* + * Work around for warm reboot but device not power off, + * but it would also fall into this case when auto power on is enabled. + */ + _power_switch(halmac, api, HALMAC_MAC_POWER_OFF); + status = _power_switch(halmac, api, HALMAC_MAC_POWER_ON); + RTW_WARN("%s: Power state abnormal, try to recover...%s\n", + __FUNCTION__, (HALMAC_RET_SUCCESS == status)?"OK":"FAIL!"); + } + if (HALMAC_RET_SUCCESS != status) { + if (HALMAC_RET_PWR_UNCHANGE == status) + err = -2; + goto out; + } + + status = api->halmac_init_system_cfg(halmac); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/* + * Description: + * Power off device hardware. + * + * Return: + * 0 Power off success + * -1 Power off fail + */ +int rtw_halmac_poweroff(struct dvobj_priv *d) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + int err = -1; halmac = dvobj_to_halmac(d); + if (!halmac) + goto out; + api = HALMAC_GET_API(halmac); - status = api->halmac_cfg_drv_info(halmac, info); - if (status != HALMAC_RET_SUCCESS) + status = _power_switch(halmac, api, HALMAC_MAC_POWER_OFF); + if ((HALMAC_RET_SUCCESS != status) + && (HALMAC_RET_PWR_UNCHANGE != status)) goto out; err = 0; @@ -1154,7 +2622,7 @@ int rtw_halmac_config_rx_info(struct dvobj_priv *d, HALMAC_DRV_INFO info) } #ifdef CONFIG_SUPPORT_TRX_SHARED -static inline HALMAC_RX_FIFO_EXPANDING_MODE _trx_share_mode_drv2halmac(u8 trx_share_mode) +static inline enum halmac_rx_fifo_expanding_mode _trx_share_mode_drv2halmac(u8 trx_share_mode) { if (0 == trx_share_mode) return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE; @@ -1167,16 +2635,18 @@ static inline HALMAC_RX_FIFO_EXPANDING_MODE _trx_share_mode_drv2halmac(u8 trx_sh else return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE; } -static HALMAC_RX_FIFO_EXPANDING_MODE _rtw_get_trx_share_mode(_adapter *adapter) + +static enum halmac_rx_fifo_expanding_mode _rtw_get_trx_share_mode(struct _ADAPTER *adapter) { - struct registry_priv *registry_par = &adapter->registrypriv; + struct registry_priv *registry_par = &adapter->registrypriv; return _trx_share_mode_drv2halmac(registry_par->trx_share_mode); } -void dump_trx_share_mode(void *sel, _adapter *adapter) + +void dump_trx_share_mode(void *sel, struct _ADAPTER *adapter) { struct registry_priv *registry_par = &adapter->registrypriv; - u8 mode = _trx_share_mode_drv2halmac(registry_par->trx_share_mode); + u8 mode = _trx_share_mode_drv2halmac(registry_par->trx_share_mode); if (HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK == mode) RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_1"); @@ -1189,21 +2659,62 @@ void dump_trx_share_mode(void *sel, _adapter *adapter) } #endif -static u8 _get_drv_rsvd_page(HALMAC_DRV_RSVD_PG_NUM rsvd_page_number) +static enum halmac_drv_rsvd_pg_num _rsvd_page_num_drv2halmac(u8 num) { - if (HALMAC_RSVD_PG_NUM16 == rsvd_page_number) - return 16; - else if (HALMAC_RSVD_PG_NUM24 == rsvd_page_number) - return 24; - else if (HALMAC_RSVD_PG_NUM32 == rsvd_page_number) - return 32; + if (num <= 8) + return HALMAC_RSVD_PG_NUM8; + if (num <= 16) + return HALMAC_RSVD_PG_NUM16; + if (num <= 24) + return HALMAC_RSVD_PG_NUM24; + if (num <= 32) + return HALMAC_RSVD_PG_NUM32; + if (num <= 64) + return HALMAC_RSVD_PG_NUM64; + + if (num > 128) + RTW_WARN("%s: Fail to allocate RSVD page(%d)!!" + " The MAX RSVD page number is 128...\n", + __FUNCTION__, num); + + return HALMAC_RSVD_PG_NUM128; +} - RTW_ERR("%s unknown HALMAC_RSVD_PG type :%d\n", __func__, rsvd_page_number); - rtw_warn_on(1); - return 0; +static u8 _rsvd_page_num_halmac2drv(enum halmac_drv_rsvd_pg_num rsvd_page_number) +{ + u8 num = 0; + + + switch (rsvd_page_number) { + case HALMAC_RSVD_PG_NUM8: + num = 8; + break; + + case HALMAC_RSVD_PG_NUM16: + num = 16; + break; + + case HALMAC_RSVD_PG_NUM24: + num = 24; + break; + + case HALMAC_RSVD_PG_NUM32: + num = 32; + break; + + case HALMAC_RSVD_PG_NUM64: + num = 64; + break; + + case HALMAC_RSVD_PG_NUM128: + num = 128; + break; + } + + return num; } -static HALMAC_TRX_MODE _choose_trx_mode(struct dvobj_priv *d) +static enum halmac_trx_mode _choose_trx_mode(struct dvobj_priv *d) { PADAPTER p; @@ -1221,30 +2732,27 @@ static HALMAC_TRX_MODE _choose_trx_mode(struct dvobj_priv *d) return HALMAC_TRX_MODE_NORMAL; } -static inline HALMAC_RF_TYPE _rf_type_drv2halmac(RT_RF_TYPE_DEF_E rf_drv) +static inline enum halmac_rf_type _rf_type_drv2halmac(enum rf_type rf_drv) { - HALMAC_RF_TYPE rf_mac; + enum halmac_rf_type rf_mac; switch (rf_drv) { + case RF_1T1R: + rf_mac = HALMAC_RF_1T1R; + break; case RF_1T2R: rf_mac = HALMAC_RF_1T2R; break; - case RF_2T4R: - rf_mac = HALMAC_RF_2T4R; - break; case RF_2T2R: rf_mac = HALMAC_RF_2T2R; break; - case RF_1T1R: - rf_mac = HALMAC_RF_1T1R; - break; - case RF_2T2R_GREEN: - rf_mac = HALMAC_RF_2T2R_GREEN; - break; case RF_2T3R: rf_mac = HALMAC_RF_2T3R; break; + case RF_2T4R: + rf_mac = HALMAC_RF_2T4R; + break; case RF_3T3R: rf_mac = HALMAC_RF_3T3R; break; @@ -1255,22 +2763,120 @@ static inline HALMAC_RF_TYPE _rf_type_drv2halmac(RT_RF_TYPE_DEF_E rf_drv) rf_mac = HALMAC_RF_4T4R; break; default: - rf_mac = (HALMAC_RF_TYPE)rf_drv; + rf_mac = HALMAC_RF_MAX_TYPE; + RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_drv); break; } return rf_mac; } +static inline enum rf_type _rf_type_halmac2drv(enum halmac_rf_type rf_mac) +{ + enum rf_type rf_drv; + + + switch (rf_mac) { + case HALMAC_RF_1T2R: + rf_drv = RF_1T2R; + break; + case HALMAC_RF_2T4R: + rf_drv = RF_2T4R; + break; + case HALMAC_RF_2T2R: + case HALMAC_RF_2T2R_GREEN: + rf_drv = RF_2T2R; + break; + case HALMAC_RF_2T3R: + rf_drv = RF_2T3R; + break; + case HALMAC_RF_1T1R: + rf_drv = RF_1T1R; + break; + case HALMAC_RF_3T3R: + rf_drv = RF_3T3R; + break; + case HALMAC_RF_3T4R: + rf_drv = RF_3T4R; + break; + case HALMAC_RF_4T4R: + rf_drv = RF_4T4R; + break; + default: + rf_drv = RF_TYPE_MAX; + RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_mac); + break; + } + + return rf_drv; +} + +static enum odm_cut_version _cut_version_drv2phydm( + enum tag_HAL_Cut_Version_Definition cut_drv) +{ + enum odm_cut_version cut_phydm = ODM_CUT_A; + u32 diff; + + + if (cut_drv > K_CUT_VERSION) + RTW_WARN("%s: unknown cut_ver=%d !!\n", __FUNCTION__, cut_drv); + + diff = cut_drv - A_CUT_VERSION; + cut_phydm += diff; + + return cut_phydm; +} + +static int _send_general_info_by_reg(struct dvobj_priv *d, + struct halmac_general_info *info) +{ + struct _ADAPTER *a; + struct hal_com_data *hal; + enum tag_HAL_Cut_Version_Definition cut_drv; + enum rf_type rftype; + enum odm_cut_version cut_phydm; + u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; + + + a = dvobj_get_primary_adapter(d); + hal = GET_HAL_DATA(a); + rftype = _rf_type_halmac2drv(info->rf_type); + cut_drv = GET_CVID_CUT_VERSION(hal->version_id); + cut_phydm = _cut_version_drv2phydm(cut_drv); + +#define CLASS_GENERAL_INFO_REG 0x02 +#define CMD_ID_GENERAL_INFO_REG 0x0C +#define GENERAL_INFO_REG_SET_CMD_ID(buf, v) SET_BITS_TO_LE_4BYTE(buf, 0, 5, v) +#define GENERAL_INFO_REG_SET_CLASS(buf, v) SET_BITS_TO_LE_4BYTE(buf, 5, 3, v) +#define GENERAL_INFO_REG_SET_RFE_TYPE(buf, v) SET_BITS_TO_LE_4BYTE(buf, 8, 8, v) +#define GENERAL_INFO_REG_SET_RF_TYPE(buf, v) SET_BITS_TO_LE_4BYTE(buf, 16, 8, v) +#define GENERAL_INFO_REG_SET_CUT_VERSION(buf, v) SET_BITS_TO_LE_4BYTE(buf, 24, 8, v) +#define GENERAL_INFO_REG_SET_RX_ANT_STATUS(buf, v) SET_BITS_TO_LE_1BYTE(buf+4, 0, 4, v) +#define GENERAL_INFO_REG_SET_TX_ANT_STATUS(buf, v) SET_BITS_TO_LE_1BYTE(buf+4, 4, 4, v) + + GENERAL_INFO_REG_SET_CMD_ID(h2c, CMD_ID_GENERAL_INFO_REG); + GENERAL_INFO_REG_SET_CLASS(h2c, CLASS_GENERAL_INFO_REG); + GENERAL_INFO_REG_SET_RFE_TYPE(h2c, info->rfe_type); + GENERAL_INFO_REG_SET_RF_TYPE(h2c, rftype); + GENERAL_INFO_REG_SET_CUT_VERSION(h2c, cut_phydm); + GENERAL_INFO_REG_SET_RX_ANT_STATUS(h2c, info->rx_ant_status); + GENERAL_INFO_REG_SET_TX_ANT_STATUS(h2c, info->tx_ant_status); + + return rtw_halmac_send_h2c(d, h2c); +} + static int _send_general_info(struct dvobj_priv *d) { - PADAPTER adapter; - PHAL_DATA_TYPE hal; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_GENERAL_INFO info; - HALMAC_RET_STATUS status; - u8 val8; + struct _ADAPTER *adapter; + struct hal_com_data *hal; + struct halmac_adapter *halmac; + struct halmac_api *api; + struct halmac_general_info info; + enum halmac_ret_status status; + enum rf_type rf = RF_1T1R; + enum bb_path txpath = BB_PATH_A; + enum bb_path rxpath = BB_PATH_A; + int err; adapter = dvobj_get_primary_adapter(d); @@ -1282,8 +2888,10 @@ static int _send_general_info(struct dvobj_priv *d) _rtw_memset(&info, 0, sizeof(info)); info.rfe_type = (u8)hal->rfe_type; - rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &val8); - info.rf_type = _rf_type_drv2halmac(val8); + rtw_hal_get_rf_path(d, &rf, &txpath, &rxpath); + info.rf_type = _rf_type_drv2halmac(rf); + info.tx_ant_status = (u8)txpath; + info.rx_ant_status = (u8)rxpath; status = api->halmac_send_general_info(halmac, &info); switch (status) { @@ -1297,9 +2905,239 @@ static int _send_general_info(struct dvobj_priv *d) return -1; } + err = _send_general_info_by_reg(d, &info); + if (err) { + RTW_ERR("%s: Fail to send general info by register!\n", + __FUNCTION__); + return -1; + } + + return 0; +} + +static int _cfg_drv_rsvd_pg_num(struct dvobj_priv *d) +{ + struct _ADAPTER *a; + struct hal_com_data *hal; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_drv_rsvd_pg_num rsvd_page_number; + enum halmac_ret_status status; + u8 drv_rsvd_num; + + + a = dvobj_get_primary_adapter(d); + hal = GET_HAL_DATA(a); + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + drv_rsvd_num = rtw_hal_get_rsvd_page_num(a); + rsvd_page_number = _rsvd_page_num_drv2halmac(drv_rsvd_num); + status = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number); + if (status != HALMAC_RET_SUCCESS) + return -1; + hal->drv_rsvd_page_number = _rsvd_page_num_halmac2drv(rsvd_page_number); + + if (drv_rsvd_num != hal->drv_rsvd_page_number) + RTW_INFO("%s: request %d pages, but allocate %d pages\n", + __FUNCTION__, drv_rsvd_num, hal->drv_rsvd_page_number); + return 0; } +static void _debug_dlfw_fail(struct dvobj_priv *d) +{ + struct _ADAPTER *a; + u32 addr; + u32 v32, i, n; + u8 data[0x100] = {0}; + + + a = dvobj_get_primary_adapter(d); + + /* read 0x80[15:0], 0x10F8[31:0] once */ + addr = 0x80; + v32 = rtw_read16(a, addr); + RTW_PRINT("%s: 0x%X = 0x%04x\n", __FUNCTION__, addr, v32); + + addr = 0x10F8; + v32 = rtw_read32(a, addr); + RTW_PRINT("%s: 0x%X = 0x%08x\n", __FUNCTION__, addr, v32); + + /* read 0x10FC[31:0], 5 times */ + addr = 0x10FC; + n = 5; + for (i = 0; i < n; i++) { + v32 = rtw_read32(a, addr); + RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n", + __FUNCTION__, addr, v32, i, n); + } + + /* + * write 0x3A[7:0]=0x28 and 0xF6[7:0]=0x01 + * and then read 0xC0[31:0] 5 times + */ + addr = 0x3A; + v32 = 0x28; + rtw_write8(a, addr, (u8)v32); + v32 = rtw_read8(a, addr); + RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32); + + addr = 0xF6; + v32 = 0x1; + rtw_write8(a, addr, (u8)v32); + v32 = rtw_read8(a, addr); + RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32); + + addr = 0xC0; + n = 5; + for (i = 0; i < n; i++) { + v32 = rtw_read32(a, addr); + RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n", + __FUNCTION__, addr, v32, i, n); + } + + /* 0x00~0xFF, 0x1000~0x10FF */ + addr = 0; + n = 0x100; + for (i = 0; i < n; i+=4) + *(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i)); + for (i = 0; i < n; i++) { + if (i % 16 == 0) + RTW_PRINT("0x%04x\t", addr+i); + _RTW_PRINT("0x%02x", data[i]); + if (i % 16 == 15) + _RTW_PRINT("\n"); + else + _RTW_PRINT(" "); + } + + addr = 0x1000; + n = 0x100; + for (i = 0; i < n; i+=4) + *(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i)); + for (i = 0; i < n; i++) { + if (i % 16 == 0) + RTW_PRINT("0x%04x\t", addr+i); + _RTW_PRINT("0x%02x", data[i]); + if (i % 16 == 15) + _RTW_PRINT("\n"); + else + _RTW_PRINT(" "); + } + + /* read 0x80 after 10 secs */ + rtw_msleep_os(10000); + addr = 0x80; + v32 = rtw_read16(a, addr); + RTW_PRINT("%s: 0x%X = 0x%04x (after 10 secs)\n", + __FUNCTION__, addr, v32); +} + +static enum halmac_ret_status _enter_cpu_sleep_mode(struct dvobj_priv *d) +{ + struct hal_com_data *hal; + struct halmac_adapter *mac; + struct halmac_api *api; + + + hal = GET_HAL_DATA(dvobj_get_primary_adapter(d)); + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + +#ifdef CONFIG_RTL8822B + /* Support after firmware version 21 */ + if (hal->firmware_version < 21) + return HALMAC_RET_NOT_SUPPORT; +#elif defined(CONFIG_RTL8821C) + /* Support after firmware version 13.6 or 16 */ + if (hal->firmware_version == 13) { + if (hal->firmware_sub_version < 6) + return HALMAC_RET_NOT_SUPPORT; + } else if (hal->firmware_version < 16) { + return HALMAC_RET_NOT_SUPPORT; + } +#endif + + return api->halmac_enter_cpu_sleep_mode(mac); +} + +/* + * _cpu_sleep() - Let IC CPU enter sleep mode + * @d: struct dvobj_priv* + * @timeout: time limit of wait, unit is ms + * 0 for no limit + * + * Rteurn 0 for CPU in sleep mode, otherwise fail to enter sleep mode. + * Error codes definition are as follow: + * -1 HALMAC enter sleep return fail + * -2 HALMAC get CPU mode return fail + * -110 timeout + */ +static int _cpu_sleep(struct dvobj_priv *d, u32 timeout) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_wlcpu_mode mode = HALMAC_WLCPU_UNDEFINE; + systime start_t; + s32 period = 0; + u32 cnt = 0; + int err = 0; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + start_t = rtw_get_current_time(); + + status = _enter_cpu_sleep_mode(d); + if (status != HALMAC_RET_SUCCESS) { + if (status != HALMAC_RET_NOT_SUPPORT) + err = -1; + goto exit; + } + + do { + cnt++; + + mode = HALMAC_WLCPU_UNDEFINE; + status = api->halmac_get_cpu_mode(mac, &mode); + + period = rtw_get_passing_time_ms(start_t); + + if (status != HALMAC_RET_SUCCESS) { + err = -2; + break; + } + if (mode == HALMAC_WLCPU_SLEEP) + break; + if (period > timeout) { + err = -110; + break; + } + + rtw_msleep_os(1); + } while (1); + +exit: + if (err) + RTW_ERR("%s: Fail to enter sleep mode! (%d, %d)\n", + __FUNCTION__, status, mode); + + RTW_INFO("%s: Cost %dms to polling %u times. (err=%d)\n", + __FUNCTION__, period, cnt, err); + + return err; +} + +static void _init_trx_cfg_drv(struct dvobj_priv *d) +{ +#ifdef CONFIG_PCI_HCI + rtw_hal_irp_reset(dvobj_get_primary_adapter(d)); +#endif +} + /* * Description: * Downlaod Firmware Flow @@ -1318,17 +3156,17 @@ static int _send_general_info(struct dvobj_priv *d) */ static int download_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize, u8 re_dl) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - int err = 0; PHAL_DATA_TYPE hal; - HALMAC_FW_VERSION fw_vesion; + struct halmac_adapter *mac; + struct halmac_api *api; + struct halmac_fw_version fw_vesion; + enum halmac_ret_status status; + int err = 0; + hal = GET_HAL_DATA(dvobj_get_primary_adapter(d)); mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - hal = GET_HAL_DATA(dvobj_get_primary_adapter(d)); if ((!fw) || (!fwsize)) return -1; @@ -1337,71 +3175,101 @@ static int download_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize, u8 re_dl) /* ToDo */ /* 2. Driver Check Tx FIFO is empty */ - /* ToDo */ + err = rtw_halmac_txfifo_wait_empty(d, 2000); /* wait 2s */ + if (err) { + err = -1; + goto resume_tx; + } /* 3. Config MAX download size */ -#ifdef CONFIG_USB_HCI - /* for USB do not exceed MAX_CMDBUF_SZ */ - api->halmac_cfg_max_dl_size(mac, 0x1000); -#elif defined CONFIG_PCIE_HCI - /* required a even length from u32 */ - api->halmac_cfg_max_dl_size(mac, (MAX_CMDBUF_SZ - TXDESC_OFFSET) & 0xFFFFFFFE); -#endif + /* + * Already done in rtw_halmac_init_adapter() or + * somewhere calling rtw_halmac_set_max_dl_fw_size(). + */ + + if (re_dl) { + /* 4. Enter IC CPU sleep mode */ + err = _cpu_sleep(d, 2000); + if (err) { + RTW_ERR("%s: IC CPU fail to enter sleep mode!(%d)\n", + __FUNCTION__, err); + /* skip this error */ + err = 0; + } + } - /* 4. Download Firmware */ + /* 5. Download Firmware */ status = api->halmac_download_firmware(mac, fw, fwsize); - if (HALMAC_RET_SUCCESS != status) - return -1; + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: download firmware FAIL! status=0x%02x\n", + __FUNCTION__, status); + _debug_dlfw_fail(d); + err = -1; + goto resume_tx; + } + + /* 5.1. (Driver) Reset driver variables if needed */ + hal->LastHMEBoxNum = 0; + + /* 5.2. (Driver) Get FW version */ + status = api->halmac_get_fw_version(mac, &fw_vesion); + if (status == HALMAC_RET_SUCCESS) { + hal->firmware_version = fw_vesion.version; + hal->firmware_sub_version = fw_vesion.sub_version; + hal->firmware_size = fwsize; + } - /* 5. Driver resume TX if needed */ +resume_tx: + /* 6. Driver resume TX if needed */ /* ToDo */ + if (err) + goto exit; + if (re_dl) { - HALMAC_TRX_MODE mode; + enum halmac_trx_mode mode; + + /* 7. Change reserved page size */ + err = _cfg_drv_rsvd_pg_num(d); + if (err) + return -1; - /* 6. Init TRX Configuration */ + /* 8. Init TRX Configuration */ mode = _choose_trx_mode(d); status = api->halmac_init_trx_cfg(mac, mode); if (HALMAC_RET_SUCCESS != status) return -1; + _init_trx_cfg_drv(d); - /* 7. Config RX Aggregation */ + /* 9. Config RX Aggregation */ err = rtw_halmac_rx_agg_switch(d, _TRUE); if (err) return -1; - /* 8. Send General Info */ + /* 10. Send General Info */ err = _send_general_info(d); if (err) return -1; } - /* 9. Reset driver variables if needed */ - hal->LastHMEBoxNum = 0; - - /* 10. Get FW version */ - status = api->halmac_get_fw_version(mac, &fw_vesion); - if (status == HALMAC_RET_SUCCESS) { - hal->firmware_version = fw_vesion.version; - hal->firmware_sub_version = fw_vesion.sub_version; - hal->firmware_size = fwsize; - } - +exit: return err; } -static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) +static int init_mac_flow(struct dvobj_priv *d) { PADAPTER p; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_WLAN_ADDR hwa; - HALMAC_TRX_MODE trx_mode; - HALMAC_RET_STATUS status; + struct hal_com_data *hal; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_drv_rsvd_pg_num rsvd_page_number; + union halmac_wlan_addr hwa; + enum halmac_trx_mode trx_mode; + enum halmac_ret_status status; + u8 drv_rsvd_num; u8 nettype; - int err; - PHAL_DATA_TYPE hal; - HALMAC_DRV_RSVD_PG_NUM rsvd_page_number = HALMAC_RSVD_PG_NUM16;/*HALMAC_RSVD_PG_NUM24/HALMAC_RSVD_PG_NUM32*/ + int err, err_ret = -1; + p = dvobj_get_primary_adapter(d); hal = GET_HAL_DATA(p); @@ -1409,18 +3277,21 @@ static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) api = HALMAC_GET_API(halmac); #ifdef CONFIG_SUPPORT_TRX_SHARED - status = api->halmac_cfg_rx_fifo_expanding_mode(halmac, _rtw_get_trx_share_mode(p)); + status = api->halmac_cfg_rxff_expand_mode(halmac, + _rtw_get_trx_share_mode(p)); if (status != HALMAC_RET_SUCCESS) goto out; #endif -#ifdef CONFIG_PNO_SUPPORT - rsvd_page_number = HALMAC_RSVD_PG_NUM32; -#endif - status = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number); +#if 0 /* It is not necessary to call this in normal driver */ + status = api->halmac_cfg_la_mode(halmac, HALMAC_LA_MODE_DISABLE); if (status != HALMAC_RET_SUCCESS) goto out; - hal->drv_rsvd_page_number = _get_drv_rsvd_page(rsvd_page_number); +#endif + + err = _cfg_drv_rsvd_pg_num(d); + if (err) + goto out; #ifdef CONFIG_USB_HCI status = api->halmac_set_bulkout_num(halmac, d->RtNumOutPipes); @@ -1432,6 +3303,7 @@ static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) status = api->halmac_init_mac_cfg(halmac, trx_mode); if (status != HALMAC_RET_SUCCESS) goto out; + _init_trx_cfg_drv(d); err = rtw_halmac_rx_agg_switch(d, _TRUE); if (err) @@ -1449,8 +3321,33 @@ static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) if (status != HALMAC_RET_SUCCESS) goto out; + err_ret = 0; out: - return status; + return err_ret; +} + +static int _drv_enable_trx(struct dvobj_priv *d) +{ + struct _ADAPTER *adapter; + u32 status; + + + adapter = dvobj_get_primary_adapter(d); + if (adapter->bup == _FALSE) { +#ifdef CONFIG_NEW_NETDEV_HDL + status = rtw_mi_start_drv_threads(adapter); +#else + status = rtw_start_drv_threads(adapter); +#endif + if (status == _FAIL) { + RTW_ERR("%s: Start threads Failed!\n", __FUNCTION__); + return -1; + } + } + + rtw_intf_start(adapter); + + return 0; } /* @@ -1463,10 +3360,10 @@ static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize) { PADAPTER adapter; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - u32 ok = _TRUE; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 ok; u8 fw_ok = _FALSE; int err, err_ret = -1; @@ -1499,8 +3396,13 @@ static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize) } /* InitMACFlow */ - status = init_mac_flow(d); - if (status != HALMAC_RET_SUCCESS) + err = init_mac_flow(d); + if (err) + goto out; + + /* Driver insert flow: Enable TR/RX */ + err = _drv_enable_trx(d); + if (err) goto out; /* halmac_send_general_info */ @@ -1569,11 +3471,16 @@ int rtw_halmac_init_hal_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize) int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath) { u8 *fw = NULL; - u32 fwmaxsize, size = 0; + u32 fwmaxsize = 0, size = 0; int err = 0; - fwmaxsize = FIRMWARE_MAX_SIZE; + err = rtw_halmac_get_fw_max_size(d, &fwmaxsize); + if (err) { + RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err); + return -1; + } + fw = rtw_zmalloc(fwmaxsize); if (!fw) return -1; @@ -1588,7 +3495,7 @@ int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath) exit: rtw_mfree(fw, fwmaxsize); - fw = NULL; + /*fw = NULL;*/ return err; } @@ -1596,9 +3503,9 @@ int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath) int rtw_halmac_deinit_hal(struct dvobj_priv *d) { PADAPTER adapter; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; int err = -1; @@ -1621,9 +3528,9 @@ int rtw_halmac_deinit_hal(struct dvobj_priv *d) int rtw_halmac_self_verify(struct dvobj_priv *d) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; int err = -1; @@ -1643,41 +3550,121 @@ int rtw_halmac_self_verify(struct dvobj_priv *d) return err; } -u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d) +static u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - u8 rst = _TRUE; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + u32 chk_num = 10; + u8 rst = _FALSE; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - if (HALMAC_RET_TXFIFO_NO_EMPTY == api->halmac_txfifo_is_empty(mac, 10)) - rst = _FALSE; + + status = api->halmac_txfifo_is_empty(mac, chk_num); + if (status == HALMAC_RET_SUCCESS) + rst = _TRUE; return rst; } -static HALMAC_DLFW_MEM _get_halmac_fw_mem(enum fw_mem mem) +/** + * rtw_halmac_txfifo_wait_empty() - Wait TX FIFO to be emtpy + * @d: struct dvobj_priv* + * @timeout: time limit of wait, unit is ms + * 0 for no limit + * + * Wait TX FIFO to be emtpy. + * + * Rteurn 0 for TX FIFO is empty, otherwise not empty. + */ +int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout) { - if (FW_EMEM == mem) - return HALMAC_DLFW_MEM_EMEM; - else if (FW_IMEM == mem) - return HALMAC_DLFW_MEM_UNDEFINE; - else if (FW_DMEM == mem) - return HALMAC_DLFW_MEM_UNDEFINE; - else - return HALMAC_DLFW_MEM_UNDEFINE; + struct _ADAPTER *a; + u8 empty = _FALSE; + u32 cnt = 0; + systime start_time = 0; + u32 pass_time; /* ms */ + + + a = dvobj_get_primary_adapter(d); + start_time = rtw_get_current_time(); + + do { + cnt++; + empty = rtw_halmac_txfifo_is_empty(d); + if (empty == _TRUE) + break; + + if (timeout) { + pass_time = rtw_get_passing_time_ms(start_time); + if (pass_time > timeout) + break; + } + if (RTW_CANNOT_IO(a)) { + RTW_WARN("%s: Interrupted by I/O forbiden!\n", __FUNCTION__); + break; + } + + rtw_msleep_os(2); + } while (1); + + if (empty == _FALSE) { +#ifdef CONFIG_RTW_DEBUG + u16 dbg_reg[] = {0x210, 0x230, 0x234, 0x238, 0x23C, 0x240, + 0x41A, 0x10FC, 0x10F8, 0x11F4, 0x11F8}; + u8 i; + u32 val; + + if (!RTW_CANNOT_IO(a)) { + for (i = 0; i < ARRAY_SIZE(dbg_reg); i++) { + val = rtw_read32(a, dbg_reg[i]); + RTW_ERR("REG_%X:0x%08x\n", dbg_reg[i], val); + } + } +#endif /* CONFIG_RTW_DEBUG */ + + RTW_ERR("%s: Fail to wait txfifo empty!(cnt=%d)\n", + __FUNCTION__, cnt); + return -1; + } + + return 0; +} + +static enum halmac_dlfw_mem _fw_mem_drv2halmac(enum fw_mem mem, u8 tx_stop) +{ + enum halmac_dlfw_mem mem_halmac = HALMAC_DLFW_MEM_UNDEFINE; + + + switch (mem) { + case FW_EMEM: + if (tx_stop == _FALSE) + mem_halmac = HALMAC_DLFW_MEM_EMEM_RSVD_PG; + else + mem_halmac = HALMAC_DLFW_MEM_EMEM; + break; + + case FW_IMEM: + case FW_DMEM: + mem_halmac = HALMAC_DLFW_MEM_UNDEFINE; + break; + } + + return mem_halmac; } -#define DBG_DL_FW_MEM int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_dlfw_mem dlfw_mem; + u8 tx_stop = _FALSE; + u32 chk_timeout = 2000; /* unit: ms */ int err = 0; - u8 chk_cnt = 0; - bool txfifo_empty = _FALSE; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); @@ -1685,52 +3672,37 @@ int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem me if ((!fw) || (!fwsize)) return -1; +#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX /* 1. Driver Stop Tx */ /* ToDo */ /* 2. Driver Check Tx FIFO is empty */ - do { - txfifo_empty = rtw_halmac_txfifo_is_empty(d); - chk_cnt++; - #ifdef DBG_DL_FW_MEM - RTW_INFO("polling txfifo empty chk_cnt:%d\n", chk_cnt); - #endif - rtw_msleep_os(2); - } while ((!txfifo_empty) && (chk_cnt < 100)); - - if (_FALSE == txfifo_empty) { - #ifdef DBG_DL_FW_MEM - { - PADAPTER adapter = dvobj_get_primary_adapter(d); - - RTW_ERR("%s => polling txfifo empty failed\n", __func__); - RTW_ERR("REG_210:0x%08x\n", rtw_read32(adapter, 0x210)); - RTW_ERR("REG_230:0x%08x\n", rtw_read32(adapter, 0x230)); - RTW_ERR("REG_234:0x%08x\n", rtw_read32(adapter, 0x234)); - RTW_ERR("REG_238:0x%08x\n", rtw_read32(adapter, 0x238)); - RTW_ERR("REG_23C:0x%08x\n", rtw_read32(adapter, 0x23C)); - RTW_ERR("REG_240:0x%08x\n", rtw_read32(adapter, 0x240)); - RTW_ERR("REG_41A:0x%08x\n", rtw_read32(adapter, 0x41A)); - - RTW_ERR("REG_10FC:0x%08x\n", rtw_read32(adapter, 0x10FC)); - RTW_ERR("REG_10F8:0x%08x\n", rtw_read32(adapter, 0x10F8)); - RTW_ERR("REG_11F4:0x%08x\n", rtw_read32(adapter, 0x11F4)); - RTW_ERR("REG_11F8:0x%08x\n", rtw_read32(adapter, 0x11F8)); - } - #endif - return -1; - } + err = rtw_halmac_txfifo_wait_empty(d, chk_timeout); + if (err) + tx_stop = _FALSE; + else + tx_stop = _TRUE; +#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */ /* 3. Download Firmware MEM */ - status = api->halmac_free_download_firmware(mac, _get_halmac_fw_mem(mem), fw, fwsize); - if (HALMAC_RET_SUCCESS != status) { - #ifdef DBG_DL_FW_MEM - RTW_ERR("%s => halmac_free_download_firmware failed\n", __func__); - #endif - return -1; + dlfw_mem = _fw_mem_drv2halmac(mem, tx_stop); + if (dlfw_mem == HALMAC_DLFW_MEM_UNDEFINE) { + err = -1; + goto resume_tx; } + status = api->halmac_free_download_firmware(mac, dlfw_mem, fw, fwsize); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: halmac_free_download_firmware fail(err=0x%x)\n", + __FUNCTION__, status); + err = -1; + goto resume_tx; + } + +resume_tx: +#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX /* 4. Driver resume TX if needed */ /* ToDo */ +#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */ return err; } @@ -1738,10 +3710,16 @@ int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem me int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem) { u8 *fw = NULL; - u32 fwmaxsize, size = 0; + u32 fwmaxsize = 0, size = 0; int err = 0; - fwmaxsize = FIRMWARE_MAX_SIZE; + + err = rtw_halmac_get_fw_max_size(d, &fwmaxsize); + if (err) { + RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err); + return -1; + } + fw = rtw_zmalloc(fwmaxsize); if (!fw) return -1; @@ -1753,7 +3731,7 @@ int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem err = -1; rtw_mfree(fw, fwmaxsize); - fw = NULL; + /*fw = NULL;*/ return err; } @@ -1766,8 +3744,8 @@ int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize) { PADAPTER adapter; - HALMAC_RET_STATUS status; - u32 ok = _TRUE; + enum halmac_ret_status status; + u32 ok; int err, err_ret = -1; @@ -1792,8 +3770,8 @@ int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize) goto out; } - status = init_mac_flow(d); - if (status != HALMAC_RET_SUCCESS) + err = init_mac_flow(d); + if (err) goto out; err = _send_general_info(d); @@ -1809,11 +3787,16 @@ int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize) int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath) { u8 *fw = NULL; - u32 fwmaxsize, size = 0; + u32 fwmaxsize = 0, size = 0; int err = 0; - fwmaxsize = FIRMWARE_MAX_SIZE; + err = rtw_halmac_get_fw_max_size(d, &fwmaxsize); + if (err) { + RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err); + return -1; + } + fw = rtw_zmalloc(fwmaxsize); if (!fw) return -1; @@ -1825,7 +3808,7 @@ int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath) err = -1; rtw_mfree(fw, fwmaxsize); - fw = NULL; + /*fw = NULL;*/ return err; } @@ -1844,9 +3827,10 @@ int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath) int rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable) { PADAPTER adapter; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u8 on; adapter = dvobj_get_primary_adapter(d); @@ -1854,8 +3838,9 @@ int rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable) if (!halmac) return -1; api = HALMAC_GET_API(halmac); + on = (enable == _TRUE) ? 1 : 0; - status = api->halmac_set_hw_value(halmac, HALMAC_HW_EN_BB_RF, &enable); + status = api->halmac_set_hw_value(halmac, HALMAC_HW_EN_BB_RF, &on); if (status != HALMAC_RET_SUCCESS) return -1; @@ -1882,6 +3867,19 @@ static u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num) return read_down; } +/** + * rtw_halmac_send_h2c() - Send H2C to firmware + * @d: struct dvobj_priv* + * @h2c: H2C data buffer, suppose to be 8 bytes + * + * Send H2C to firmware by message box register(0x1D0~0x1D3 & 0x1F0~0x1F3). + * + * Assume firmware be ready to accept H2C here, please check + * (hal->bFWReady == _TRUE) before call this function or make sure firmware is + * ready. + * + * Return: 0 if process OK, otherwise fail to send this H2C. + */ int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c) { PADAPTER adapter = dvobj_get_primary_adapter(d); @@ -1891,40 +3889,40 @@ int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c) u32 msgbox_ex_addr = 0; u32 h2c_cmd = 0; u32 h2c_cmd_ex = 0; - s32 ret = _FAIL; + int err = -1; - if (adapter->bFWReady == _FALSE) { - RTW_WARN("%s: return H2C cmd because fw is not ready\n", __FUNCTION__); - return ret; - } if (!h2c) { RTW_WARN("%s: pbuf is NULL\n", __FUNCTION__); - return ret; + return err; } if (rtw_is_surprise_removed(adapter)) { RTW_WARN("%s: surprise removed\n", __FUNCTION__); - return ret; + return err; } _enter_critical_mutex(&d->h2c_fwcmd_mutex, NULL); - /* pay attention to if race condition happened in H2C cmd setting */ + /* pay attention to if race condition happened in H2C cmd setting */ h2c_box_num = hal->LastHMEBoxNum; if (!_is_fw_read_cmd_down(adapter, h2c_box_num)) { RTW_WARN(" fw read cmd failed...\n"); +#ifdef DBG_CONFIG_ERROR_DETECT + hal->srestpriv.self_dect_fw = _TRUE; + hal->srestpriv.self_dect_fw_cnt++; +#endif /* DBG_CONFIG_ERROR_DETECT */ goto exit; } - /* Write Ext command(byte 4 -7) */ + /* Write Ext command (byte 4~7) */ msgbox_ex_addr = REG_HMEBOX_E0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE); _rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, EX_MESSAGE_BOX_SIZE); h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex); rtw_write32(adapter, msgbox_ex_addr, h2c_cmd_ex); - /* Write command (byte 0 -3 ) */ + /* Write command (byte 0~3) */ msgbox_addr = REG_HMEBOX0 + (h2c_box_num * MESSAGE_BOX_SIZE); _rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4); h2c_cmd = le32_to_cpu(h2c_cmd); @@ -1932,21 +3930,36 @@ int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c) /* update last msg box number */ hal->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS; - ret = _SUCCESS; + err = 0; #ifdef DBG_H2C_CONTENT RTW_INFO_DUMP("[H2C] - ", h2c, RTW_HALMAC_H2C_MAX_SIZE); #endif exit: _exit_critical_mutex(&d->h2c_fwcmd_mutex, NULL); - return ret; + return err; } +/** + * rtw_halmac_c2h_handle() - Handle C2H for HALMAC + * @d: struct dvobj_priv* + * @c2h: Full C2H packet, including RX description and payload + * @size: Size(byte) of c2h + * + * Send C2H packet to HALMAC to process C2H packets, and the expected C2H ID is + * 0xFF. This function won't have any I/O, so caller doesn't have to call it in + * I/O safe place(ex. command thread). + * + * Please sure doesn't call this function in the same thread as someone is + * waiting HALMAC C2H ack, otherwise there is a deadlock happen. + * + * Return: 0 if process OK, otherwise no action for this C2H. + */ int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; mac = dvobj_to_halmac(d); @@ -1961,9 +3974,9 @@ int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size) int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 val; @@ -1980,9 +3993,9 @@ int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size) int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 val; @@ -1999,10 +4012,10 @@ int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size) int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - HALMAC_FEATURE_ID id; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_feature_id id; int ret; @@ -2014,7 +4027,7 @@ int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) if (ret) return -1; - status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_AUTO); + status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_DRV); if (HALMAC_RET_SUCCESS != status) { free_halmac_event(d, id); return -1; @@ -2029,9 +4042,9 @@ int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) int rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u8 v; u32 i; u8 *efuse = NULL; @@ -2072,9 +4085,9 @@ int rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 i; @@ -2095,9 +4108,9 @@ int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 val; @@ -2112,12 +4125,12 @@ int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size) return 0; } -int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) +int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - HALMAC_FEATURE_ID id; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_feature_id id; int ret; @@ -2139,23 +4152,36 @@ int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) if (ret) return -1; + if (maskmap && masksize) { + struct halmac_pg_efuse_info pginfo; + + pginfo.efuse_map = map; + pginfo.efuse_map_size = size; + pginfo.efuse_mask = maskmap; + pginfo.efuse_mask_size = masksize; + + status = api->halmac_mask_logical_efuse(mac, &pginfo); + if (status != HALMAC_RET_SUCCESS) + RTW_WARN("%s: mask logical efuse FAIL!\n", __FUNCTION__); + } + return 0; } int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_PG_EFUSE_INFO pginfo; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + struct halmac_pg_efuse_info pginfo; + enum halmac_ret_status status; mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); - pginfo.pEfuse_map = map; + pginfo.efuse_map = map; pginfo.efuse_map_size = size; - pginfo.pEfuse_mask = maskmap; + pginfo.efuse_mask = maskmap; pginfo.efuse_mask_size = masksize; status = api->halmac_pg_efuse_by_map(mac, &pginfo, HALMAC_EFUSE_R_AUTO); @@ -2167,9 +4193,9 @@ int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, int rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u8 v; u32 i; @@ -2189,9 +4215,9 @@ int rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 int rtw_halmac_write_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 i; @@ -2209,12 +4235,13 @@ int rtw_halmac_write_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 i; u8 bank = 1; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); @@ -2232,13 +4259,12 @@ int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - HALMAC_FEATURE_ID id; - int ret; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; int bank = 1; + mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); @@ -2253,147 +4279,38 @@ int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 siz return 0; } -static inline u8 _hw_port_drv2halmac(enum _hw_port hwport) -{ - u8 port = 0; - - - switch (hwport) { - case HW_PORT0: - port = 0; - break; - case HW_PORT1: - port = 1; - break; - case HW_PORT2: - port = 2; - break; - case HW_PORT3: - port = 3; - break; - case HW_PORT4: - port = 4; - break; - default: - port = hwport; - break; - } - - return port; -} - -int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) -{ - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - u8 port; - HALMAC_WLAN_ADDR hwa; - HALMAC_RET_STATUS status; - int err = -1; - - - halmac = dvobj_to_halmac(d); - api = HALMAC_GET_API(halmac); - - port = _hw_port_drv2halmac(hwport); - _rtw_memset(&hwa, 0, sizeof(hwa)); - _rtw_memcpy(hwa.Address, addr, 6); - - status = api->halmac_cfg_mac_addr(halmac, port, &hwa); - if (status != HALMAC_RET_SUCCESS) - goto out; - - err = 0; -out: - return err; -} - -int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) -{ - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - u8 port; - HALMAC_WLAN_ADDR hwa; - HALMAC_RET_STATUS status; - int err = -1; - - halmac = dvobj_to_halmac(d); - api = HALMAC_GET_API(halmac); - port = _hw_port_drv2halmac(hwport); - - _rtw_memset(&hwa, 0, sizeof(HALMAC_WLAN_ADDR)); - _rtw_memcpy(hwa.Address, addr, 6); - status = api->halmac_cfg_bssid(halmac, port, &hwa); - if (status != HALMAC_RET_SUCCESS) - goto out; - - err = 0; -out: - return err; -} - -int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw) -{ - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - - - mac = dvobj_to_halmac(d); - api = HALMAC_GET_API(mac); - - status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw); - if (HALMAC_RET_SUCCESS != status) - return -1; - - return 0; -} - -int rtw_halmac_get_hw_value(struct dvobj_priv *d, HALMAC_HW_ID hw_id, VOID *pvalue) -{ - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; - - - mac = dvobj_to_halmac(d); - api = HALMAC_GET_API(mac); - - status = api->halmac_get_hw_value(mac, hw_id, pvalue); - if (HALMAC_RET_SUCCESS != status) - return -1; - - return 0; -} - -static HAL_FIFO_SEL _fifo_sel_drv2halmac(u8 fifo_sel) +static enum hal_fifo_sel _fifo_sel_drv2halmac(u8 fifo_sel) { - if (0 == fifo_sel) + switch (fifo_sel) { + case 0: return HAL_FIFO_SEL_TX; - else if (1 == fifo_sel) + case 1: return HAL_FIFO_SEL_RX; - else if (2 == fifo_sel) + case 2: return HAL_FIFO_SEL_RSVD_PAGE; - else if (3 == fifo_sel) + case 3: return HAL_FIFO_SEL_REPORT; - else if (4 == fifo_sel) + case 4: return HAL_FIFO_SEL_LLT; - else - return HAL_FIFO_SEL_RSVD_PAGE; + case 5: + return HAL_FIFO_SEL_RXBUF_FW; + } + + return HAL_FIFO_SEL_RSVD_PAGE; } -#define CONFIG_HALMAC_FIFO_DUMP +/*#define CONFIG_HALMAC_FIFO_DUMP*/ int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum hal_fifo_sel halmac_fifo_sel; + enum halmac_ret_status status; u8 *pfifo_map = NULL; u32 fifo_size = 0; s8 ret = 0;/* 0:success, -1:error */ u8 mem_created = _FALSE; - HAL_FIFO_SEL halmac_fifo_sel; mac = dvobj_to_halmac(d); api = HALMAC_GET_API(mac); @@ -2425,31 +4342,52 @@ int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, #ifdef CONFIG_HALMAC_FIFO_DUMP { static const char * const fifo_sel_str[] = { - "TX", "RX", "RSVD_PAGE", "REPORT", "LLT" + "TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW" }; RTW_INFO("%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[halmac_fifo_sel], addr, fifo_size); RTW_INFO_DUMP("\n", pfifo_map, fifo_size); RTW_INFO(" ==================================================\n"); } -#endif +#endif /* CONFIG_HALMAC_FIFO_DUMP */ _exit: - if (mem_created && pfifo_map) + if ((mem_created == _TRUE) && pfifo_map) rtw_vmfree(pfifo_map, fifo_size); - return ret; + return ret; } +/* + * rtw_halmac_rx_agg_switch() - Switch RX aggregation function and setting + * @d struct dvobj_priv * + * @enable _FALSE/_TRUE for disable/enable RX aggregation function + * + * This function could help to on/off bus RX aggregation function, and is only + * useful for SDIO and USB interface. Although only "enable" flag is brough in, + * some setting would be taken from other places, and they are from: + * [DMA aggregation] + * struct hal_com_data.rxagg_dma_size + * struct hal_com_data.rxagg_dma_timeout + * [USB aggregation] (only use for USB interface) + * struct hal_com_data.rxagg_usb_size + * struct hal_com_data.rxagg_usb_timeout + * If above values of size and timeout are both 0 means driver would not + * control the threshold setting and leave it to HALMAC handle. + * + * From HALMAC V1_04_04, driver force the size threshold be hard limit, and the + * rx size can not exceed the setting. + * + * Return 0 for success, otherwise fail. + */ int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable) { - PADAPTER adapter; - PHAL_DATA_TYPE hal; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RXAGG_CFG rxaggcfg; - HALMAC_RET_STATUS status; - int err = -1; + struct _ADAPTER *adapter; + struct hal_com_data *hal; + struct halmac_adapter *halmac; + struct halmac_api *api; + struct halmac_rxagg_cfg rxaggcfg; + enum halmac_ret_status status; adapter = dvobj_get_primary_adapter(d); @@ -2457,94 +4395,58 @@ int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable) halmac = dvobj_to_halmac(d); api = HALMAC_GET_API(halmac); _rtw_memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg)); - + rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE; + /* + * Always enable size limit to avoid rx size exceed + * driver defined size. + */ + rxaggcfg.threshold.size_limit_en = 1; + +#ifdef RTW_RX_AGGREGATION if (_TRUE == enable) { #ifdef CONFIG_SDIO_HCI rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA; rxaggcfg.threshold.drv_define = 0; -#elif defined(CONFIG_USB_HCI) && defined(CONFIG_USB_RX_AGGREGATION) + if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) { + rxaggcfg.threshold.drv_define = 1; + rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout; + rxaggcfg.threshold.size = hal->rxagg_dma_size; + RTW_INFO("%s: RX aggregation threshold: " + "timeout=%u size=%u\n", + __FUNCTION__, + hal->rxagg_dma_timeout, + hal->rxagg_dma_size); + } +#elif defined(CONFIG_USB_HCI) switch (hal->rxagg_mode) { case RX_AGG_DISABLE: rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE; - break; - - case RX_AGG_DMA: - rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA; - if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) { - rxaggcfg.threshold.drv_define = 1; - rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout; - rxaggcfg.threshold.size = hal->rxagg_dma_size; - } - break; - - case RX_AGG_USB: - case RX_AGG_MIX: - rxaggcfg.mode = HALMAC_RX_AGG_MODE_USB; - if (hal->rxagg_usb_size || hal->rxagg_usb_timeout) { - rxaggcfg.threshold.drv_define = 1; - rxaggcfg.threshold.timeout = hal->rxagg_usb_timeout; - rxaggcfg.threshold.size = hal->rxagg_usb_size; - } - break; - } -#endif /* CONFIG_USB_HCI */ - } else - rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE; - - status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg); - if (status != HALMAC_RET_SUCCESS) - goto out; - - err = 0; -out: - return err; -} - -/* - * Description: - * Get RX driver info size. RX driver info is a small memory space between - * scriptor and RX payload. - * - * +-------------------------+ - * | RX descriptor | - * | usually 24 bytes | - * +-------------------------+ - * | RX driver info | - * | depends on driver cfg | - * +-------------------------+ - * | RX paylad | - * | | - * +-------------------------+ - * - * Parameter: - * d pointer to struct dvobj_priv of driver - * sz rx driver info size in bytes. - * - * Rteurn: - * 0 Success - * other Fail - */ -int rtw_halmac_get_drv_info_sz(struct dvobj_priv *d, u8 *sz) -{ - HALMAC_RET_STATUS status; - PHALMAC_ADAPTER halmac = dvobj_to_halmac(d); - PHALMAC_API api = HALMAC_GET_API(halmac); - u8 dw = 0; - - status = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw); - if (status != HALMAC_RET_SUCCESS) - return -1; + break; - *sz = dw * 8; - return 0; -} -int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg) -{ - HALMAC_RET_STATUS status; - PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj); - PHALMAC_API api = HALMAC_GET_API(halmac); + case RX_AGG_DMA: + rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA; + if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) { + rxaggcfg.threshold.drv_define = 1; + rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout; + rxaggcfg.threshold.size = hal->rxagg_dma_size; + } + break; + + case RX_AGG_USB: + case RX_AGG_MIX: + rxaggcfg.mode = HALMAC_RX_AGG_MODE_USB; + if (hal->rxagg_usb_size || hal->rxagg_usb_timeout) { + rxaggcfg.threshold.drv_define = 1; + rxaggcfg.threshold.timeout = hal->rxagg_usb_timeout; + rxaggcfg.threshold.size = hal->rxagg_usb_size; + } + break; + } +#endif /* CONFIG_USB_HCI */ + } +#endif /* RTW_RX_AGGREGATION */ - status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, drv_pg); + status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg); if (status != HALMAC_RET_SUCCESS) return -1; @@ -2553,16 +4455,15 @@ int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg) int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size) { - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj); - PHALMAC_API api = HALMAC_GET_API(halmac); + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_adapter *halmac = dvobj_to_halmac(dvobj); + struct halmac_api *api = HALMAC_GET_API(halmac); status = api->halmac_dl_drv_rsvd_page(halmac, pg_offset, pbuf, size); if (status != HALMAC_RET_SUCCESS) return -1; return 0; - } /* @@ -2576,9 +4477,9 @@ int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pb */ int rtw_halmac_fill_hal_spec(struct dvobj_priv *dvobj, struct hal_spec_t *spec) { - HALMAC_RET_STATUS status; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; + enum halmac_ret_status status; + struct halmac_adapter *halmac; + struct halmac_api *api; u8 cam = 0; /* Security Cam Entry Number */ @@ -2596,12 +4497,12 @@ int rtw_halmac_fill_hal_spec(struct dvobj_priv *dvobj, struct hal_spec_t *spec) return 0; } -int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para) +int rtw_halmac_p2pps(struct dvobj_priv *dvobj, struct hal_p2p_ps_para *pp2p_ps_para) { - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj); - PHALMAC_API api = HALMAC_GET_API(halmac); - HALMAC_P2PPS halmac_p2p_ps; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_adapter *halmac = dvobj_to_halmac(dvobj); + struct halmac_api *api = HALMAC_GET_API(halmac); + struct halmac_p2pps halmac_p2p_ps; (&halmac_p2p_ps)->offload_en = pp2p_ps_para->offload_en; (&halmac_p2p_ps)->role = pp2p_ps_para->role; @@ -2627,6 +4528,334 @@ int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para) } +/** + * rtw_halmac_iqk() - Run IQ Calibration + * @d: struct dvobj_priv* + * @clear: IQK parameters + * @segment: IQK parameters + * + * Process IQ Calibration(IQK). + * + * Rteurn: 0 for OK, otherwise fail. + */ +int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_feature_id id; + struct halmac_iqk_para para; + int ret; + u8 retry = 3; + u8 delay = 1; /* ms */ + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + id = HALMAC_FEATURE_IQK; + + ret = init_halmac_event(d, id, NULL, 0); + if (ret) + return -1; + + para.clear = clear; + para.segment_iqk = segment; + + do { + status = api->halmac_start_iqk(mac, ¶); + if (status != HALMAC_RET_BUSY_STATE) + break; + RTW_WARN("%s: Fail to start IQK, status is BUSY! retry=%d\n", __FUNCTION__, retry); + if (!retry) + break; + retry--; + rtw_msleep_os(delay); + } while (1); + if (status != HALMAC_RET_SUCCESS) { + free_halmac_event(d, id); + return -1; + } + + ret = wait_halmac_event(d, id); + if (ret) + return -1; + + return 0; +} + +static inline u32 _phy_parameter_val_drv2halmac(u32 val, u8 msk_en, u32 msk) +{ + if (!msk_en) + return val; + + return (val << bitshift(msk)); +} + +static int _phy_parameter_drv2halmac(struct rtw_phy_parameter *para, struct halmac_phy_parameter_info *info) +{ + if (!para || !info) + return -1; + + _rtw_memset(info, 0, sizeof(*info)); + + switch (para->cmd) { + case 0: + /* MAC register */ + switch (para->data.mac.size) { + case 1: + info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W8; + break; + case 2: + info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W16; + break; + default: + info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W32; + break; + } + info->content.MAC_REG_W.value = _phy_parameter_val_drv2halmac( + para->data.mac.value, + para->data.mac.msk_en, + para->data.mac.msk); + info->content.MAC_REG_W.msk = para->data.mac.msk; + info->content.MAC_REG_W.offset = para->data.mac.offset; + info->content.MAC_REG_W.msk_en = para->data.mac.msk_en; + break; + + case 1: + /* BB register */ + switch (para->data.bb.size) { + case 1: + info->cmd_id = HALMAC_PARAMETER_CMD_BB_W8; + break; + case 2: + info->cmd_id = HALMAC_PARAMETER_CMD_BB_W16; + break; + default: + info->cmd_id = HALMAC_PARAMETER_CMD_BB_W32; + break; + } + info->content.BB_REG_W.value = _phy_parameter_val_drv2halmac( + para->data.bb.value, + para->data.bb.msk_en, + para->data.bb.msk); + info->content.BB_REG_W.msk = para->data.bb.msk; + info->content.BB_REG_W.offset = para->data.bb.offset; + info->content.BB_REG_W.msk_en = para->data.bb.msk_en; + break; + + case 2: + /* RF register */ + info->cmd_id = HALMAC_PARAMETER_CMD_RF_W; + info->content.RF_REG_W.value = _phy_parameter_val_drv2halmac( + para->data.rf.value, + para->data.rf.msk_en, + para->data.rf.msk); + info->content.RF_REG_W.msk = para->data.rf.msk; + info->content.RF_REG_W.offset = para->data.rf.offset; + info->content.RF_REG_W.msk_en = para->data.rf.msk_en; + info->content.RF_REG_W.rf_path = para->data.rf.path; + break; + + case 3: + /* Delay register */ + if (para->data.delay.unit == 0) + info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_US; + else + info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_MS; + info->content.DELAY_TIME.delay_time = para->data.delay.value; + break; + + case 0xFF: + /* Latest(End) command */ + info->cmd_id = HALMAC_PARAMETER_CMD_END; + break; + + default: + return -1; + } + + return 0; +} + +/** + * rtw_halmac_cfg_phy_para() - Register(Phy parameter) configuration + * @d: struct dvobj_priv* + * @para: phy parameter + * + * Configure registers by firmware using H2C/C2H mechanism. + * The latest command should be para->cmd==0xFF(End command) to finish all + * processes. + * + * Return: 0 for OK, otherwise fail. + */ +int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_feature_id id; + struct halmac_phy_parameter_info info; + u8 full_fifo; + int err, ret; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + id = HALMAC_FEATURE_CFG_PARA; + full_fifo = 1; /* ToDo: How to deciede? */ + ret = 0; + + err = _phy_parameter_drv2halmac(para, &info); + if (err) + return -1; + + err = init_halmac_event(d, id, NULL, 0); + if (err) + return -1; + + status = api->halmac_cfg_parameter(mac, &info, full_fifo); + if (info.cmd_id == HALMAC_PARAMETER_CMD_END) { + if (status == HALMAC_RET_SUCCESS) { + err = wait_halmac_event(d, id); + if (err) + ret = -1; + } else { + free_halmac_event(d, id); + ret = -1; + RTW_ERR("%s: Fail to send END of cfg parameter, status is 0x%x!\n", __FUNCTION__, status); + } + } else { + if (status == HALMAC_RET_PARA_SENDING) { + err = wait_halmac_event(d, id); + if (err) + ret = -1; + } else { + free_halmac_event(d, id); + if (status != HALMAC_RET_SUCCESS) { + ret = -1; + RTW_ERR("%s: Fail to cfg parameter, status is 0x%x!\n", __FUNCTION__, status); + } + } + } + + return ret; +} + +static enum halmac_wlled_mode _led_mode_drv2halmac(u8 drv_mode) +{ + enum halmac_wlled_mode halmac_mode; + + + switch (drv_mode) { + case 1: + halmac_mode = HALMAC_WLLED_MODE_TX; + break; + case 2: + halmac_mode = HALMAC_WLLED_MODE_RX; + break; + case 3: + halmac_mode = HALMAC_WLLED_MODE_SW_CTRL; + break; + case 0: + default: + halmac_mode = HALMAC_WLLED_MODE_TRX; + break; + } + + return halmac_mode; +} + +/** + * rtw_halmac_led_cfg() - Configure Hardware LED Mode + * @d: struct dvobj_priv* + * @enable: enable or disable LED function + * 0: disable + * 1: enable + * @mode: WLan LED mode (valid when enable==1) + * 0: Blink when TX(transmit packet) and RX(receive packet) + * 1: Blink when TX only + * 2: Blink when RX only + * 3: Software control + * + * Configure hardware WLan LED mode. + * If want to change LED mode after enabled, need to disable LED first and + * enable again to set new mode. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_wlled_mode led_mode; + enum halmac_ret_status status; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + if (enable) { + status = api->halmac_pinmux_set_func(halmac, + HALMAC_GPIO_FUNC_WL_LED); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: pinmux set fail!(0x%x)\n", + __FUNCTION__, status); + return -1; + } + + led_mode = _led_mode_drv2halmac(mode); + status = api->halmac_pinmux_wl_led_mode(halmac, led_mode); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: mode set fail!(0x%x)\n", + __FUNCTION__, status); + return -1; + } + } else { + /* Change LED to software control and turn off */ + api->halmac_pinmux_wl_led_mode(halmac, + HALMAC_WLLED_MODE_SW_CTRL); + api->halmac_pinmux_wl_led_sw_ctrl(halmac, 0); + + status = api->halmac_pinmux_free_func(halmac, + HALMAC_GPIO_FUNC_WL_LED); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: pinmux free fail!(0x%x)\n", + __FUNCTION__, status); + return -1; + } + } + + return 0; +} + +/** + * rtw_halmac_led_switch() - Turn Hardware LED on/off + * @d: struct dvobj_priv* + * @on: LED light or not + * 0: Off + * 1: On(Light) + * + * Turn Hardware WLan LED On/Off. + * Before use this function, user should call rtw_halmac_led_ctrl() to switch + * mode to "software control(3)" first, otherwise control would fail. + * The interval between on and off must be longer than 1 ms, or the LED would + * keep light or dark only. + * Ex. Turn off LED at first, turn on after 0.5ms and turn off again after + * 0.5ms. The LED during this flow will only keep dark, and miss the turn on + * operation between two turn off operations. + */ +void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + api->halmac_pinmux_wl_led_sw_ctrl(halmac, on); +} + #ifdef CONFIG_SDIO_HCI /* @@ -2644,12 +4873,12 @@ int rtw_halmac_query_tx_page_num(struct dvobj_priv *d) { PADAPTER adapter; struct halmacpriv *hmpriv; - PHALMAC_ADAPTER halmac; - PHALMAC_API api; - HALMAC_RQPN_MAP rqpn; - HALMAC_DMA_MAPPING dmaqueue; - HALMAC_TXFF_ALLOCATION fifosize; - HALMAC_RET_STATUS status; + struct halmac_adapter *halmac; + struct halmac_api *api; + struct halmac_rqpn_map rqpn; + enum halmac_dma_mapping dmaqueue; + struct halmac_txff_allocation fifosize; + enum halmac_ret_status status; u8 i; @@ -2748,9 +4977,9 @@ int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *d, u8 queue, u32 *page) */ u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *d, u8 *desc, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u32 addr; @@ -2766,9 +4995,9 @@ u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *d, u8 *desc, u32 size) int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *d, u8 *buf, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; mac = dvobj_to_halmac(d); @@ -2797,9 +5026,9 @@ u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *d, u8 *seq) #ifdef CONFIG_USB_HCI u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; u8 bulkout_id; @@ -2813,9 +5042,38 @@ u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size) return bulkout_id; } -static inline HALMAC_USB_MODE _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode) +/** + * rtw_halmac_usb_get_txagg_desc_num() - MAX descriptor number in one bulk for TX + * @d: struct dvobj_priv* + * @size: TX FIFO size, unit is byte. + * + * Get MAX descriptor number in one bulk out from HALMAC. + * + * Rteurn 0 for OK, otherwise fail. + */ +int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num) +{ + struct halmac_adapter *halmac; + struct halmac_api *api; + enum halmac_ret_status status; + u8 val = 0; + + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_USB_TXAGG_DESC_NUM, &val); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *num = val; + + return 0; +} + +static inline enum halmac_usb_mode _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode) { - HALMAC_USB_MODE halmac_usb_mode = HALMAC_USB_MODE_U2; + enum halmac_usb_mode halmac_usb_mode = HALMAC_USB_MODE_U2; switch (usb_mode) { case RTW_USB_SPEED_2: @@ -2834,11 +5092,11 @@ static inline HALMAC_USB_MODE _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode) u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode) { - PHALMAC_ADAPTER mac; - PHALMAC_API api; - HALMAC_RET_STATUS status; PADAPTER adapter; - HALMAC_USB_MODE halmac_usb_mode; + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + enum halmac_usb_mode halmac_usb_mode; adapter = dvobj_get_primary_adapter(d); mac = dvobj_to_halmac(d); @@ -2852,3 +5110,143 @@ u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode) return _SUCCESS; } #endif /* CONFIG_USB_HCI */ + +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 +int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para, + u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + struct halmac_mu_bfer_init_para param; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + _rtw_memset(¶m, 0, sizeof(param)); + param.paid = paid; + param.csi_para = csi_para; + param.my_aid = my_aid; + param.csi_length_sel = sel; + _rtw_memcpy(param.bfer_address.addr, addr, 6); + + status = api->halmac_mu_bfer_entry_init(mac, ¶m); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_mu_bfer_entry_del(mac); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + + +int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, + enum halmac_snd_role role, enum halmac_data_rate rate) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_cfg_sounding(mac, role, rate); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, + enum halmac_snd_role role) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_del_sounding(mac, role); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, + u8 rssi, u8 current_rate, u8 fixrate_en, + u8 *new_rate) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_cfg_csi_rate(mac, + rssi, current_rate, fixrate_en, new_rate); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role, + u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en, + u32 *given_gid_tab, u32 *given_user_pos) +{ + struct halmac_adapter *mac; + struct halmac_api *api; + enum halmac_ret_status status; + struct halmac_cfg_mumimo_para param; + + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + _rtw_memset(¶m, 0, sizeof(param)); + + param.role = role; + param.grouping_bitmap = grouping_bitmap; + param.mu_tx_en = mu_tx_en; + + if (sounding_sts) + _rtw_memcpy(param.sounding_sts, sounding_sts, 6); + + if (given_gid_tab) + _rtw_memcpy(param.given_gid_tab, given_gid_tab, 8); + + if (given_user_pos) + _rtw_memcpy(param.given_user_pos, given_user_pos, 16); + + status = api->halmac_cfg_mumimo(mac, ¶m); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +#endif /* RTW_BEAMFORMING_VERSION_2 */ +#endif /* CONFIG_BEAMFORMING */ diff --git a/hal/hal_halmac.h b/hal/hal_halmac.h index e7d1068..46e988c 100644 --- a/hal/hal_halmac.h +++ b/hal/hal_halmac.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2018 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,25 +11,20 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _HAL_HALMAC_H_ #define _HAL_HALMAC_H_ #include /* adapter_to_dvobj(), struct intf_hdl and etc. */ #include /* struct hal_spec_t */ -#include "halmac/halmac_api.h" /* PHALMAC_ADAPTER and etc. */ +#include "halmac/halmac_api.h" /* struct halmac_adapter* and etc. */ /* HALMAC Definition for Driver */ -#define RTW_HALMAC_H2C_MAX_SIZE HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX +#define RTW_HALMAC_H2C_MAX_SIZE 8 #define RTW_HALMAC_BA_SSN_RPT_SIZE 4 #define dvobj_set_halmac(d, mac) ((d)->halmac = (mac)) -#define dvobj_to_halmac(d) ((PHALMAC_ADAPTER)((d)->halmac)) +#define dvobj_to_halmac(d) ((struct halmac_adapter *)((d)->halmac)) #define adapter_to_halmac(p) dvobj_to_halmac(adapter_to_dvobj(p)) /* for H2C cmd */ @@ -42,7 +37,67 @@ typedef enum _RTW_HALMAC_MODE { RTW_HALMAC_MODE_WIFI_TEST, } RTW_HALMAC_MODE; -extern HALMAC_PLATFORM_API rtw_halmac_platform_api; +union rtw_phy_para_data { + struct _mac { + u32 value; /* value to be set in bit mask(msk) */ + u32 msk; /* bit mask */ + u16 offset; /* address */ + u8 msk_en; /* 0/1 for msk invalid/valid */ + u8 size; /* Unit is bytes, and value should be 1/2/4 */ + } mac; + struct _bb { + u32 value; + u32 msk; + u16 offset; + u8 msk_en; + u8 size; + } bb; + struct _rf { + u32 value; + u32 msk; + u8 offset; + u8 msk_en; + /* + * 0: path A + * 1: path B + * 2: path C + * 3: path D + */ + u8 path; + } rf; + struct _delay { + /* + * 0: microsecond (us) + * 1: millisecond (ms) + */ + u8 unit; + u16 value; + } delay; +}; + +struct rtw_phy_parameter { + /* + * 0: MAC register + * 1: BB register + * 2: RF register + * 3: Delay + * 0xFF: Latest(End) command + */ + u8 cmd; + union rtw_phy_para_data data; +}; + +struct rtw_halmac_bcn_ctrl { + u8 rx_bssid_fit:1; /* 0:HW handle beacon, 1:ignore */ + u8 txbcn_rpt:1; /* Enable TXBCN report in ad hoc and AP mode */ + u8 tsf_update:1; /* Update TSF when beacon or probe response */ + u8 enable_bcn:1; /* Enable beacon related functions */ + u8 rxbcn_rpt:1; /* Enable RXBCNOK report */ + u8 p2p_ctwin:1; /* Enable P2P CTN WINDOWS function */ + u8 p2p_bcn_area:1; /* Enable P2P BCN area on function */ +}; + +extern struct halmac_platform_api rtw_halmac_platform_api; /* HALMAC API for Driver(HAL) */ u8 rtw_halmac_read8(struct intf_hdl *, u32 addr); @@ -53,14 +108,53 @@ void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem) u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr); u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr); u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr); -#endif +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value); int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value); int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value); -void rtw_dump_halmac_info(void *sel); -int rtw_halmac_init_adapter(struct dvobj_priv *, PHALMAC_PLATFORM_API); +/* Software Information */ +void rtw_halmac_get_version(char *str, u32 len); + +/* Software Initialization */ +int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api); int rtw_halmac_deinit_adapter(struct dvobj_priv *); + +/* Get operations */ +int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue); +int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy); +int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size); +int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size); +int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz); +int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size); +int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size); +int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num); +int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); +int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type); +int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl); +/*int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);*/ + +/* Set operations */ +int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info); +int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size); +int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); +int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); +int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr); +int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type); +int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport); +int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, u32 space); +int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl); +int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid); +int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw); +int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop); +int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable); + +/* Functions */ int rtw_halmac_poweron(struct dvobj_priv *); int rtw_halmac_poweroff(struct dvobj_priv *); int rtw_halmac_init_hal(struct dvobj_priv *); @@ -68,6 +162,7 @@ int rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize); int rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath); int rtw_halmac_deinit_hal(struct dvobj_priv *); int rtw_halmac_self_verify(struct dvobj_priv *); +int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout); int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize); int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath); int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem); @@ -75,14 +170,15 @@ int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable); int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c); int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size); -int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size); +/* eFuse */ +int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size); int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size); int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); int rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); int rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size); -int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); +int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize); int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize); int rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); @@ -90,20 +186,17 @@ int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); -int rtw_halmac_config_rx_info(struct dvobj_priv *, HALMAC_DRV_INFO); -int rtw_halmac_set_mac_address(struct dvobj_priv *, enum _hw_port, u8 *addr); -int rtw_halmac_set_bssid(struct dvobj_priv *, enum _hw_port hwport, u8 *addr); - -int rtw_halmac_set_bandwidth(struct dvobj_priv *, u8 channel, u8 pri_ch_idx, u8 bw); int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer); int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable); -int rtw_halmac_get_hw_value(struct dvobj_priv *, HALMAC_HW_ID hw_id, VOID *pvalue); -int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason); -int rtw_halmac_get_drv_info_sz(struct dvobj_priv *, u8 *sz); -int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg); + +/* Specific function APIs*/ int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size); int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *); int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para); +int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment); +int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para); +int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode); +void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on); #ifdef CONFIG_SDIO_HCI int rtw_halmac_query_tx_page_num(struct dvobj_priv *); @@ -115,10 +208,34 @@ u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq); #ifdef CONFIG_USB_HCI u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size); +int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num); u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode); #endif /* CONFIG_USB_HCI */ #ifdef CONFIG_SUPPORT_TRX_SHARED void dump_trx_share_mode(void *sel, _adapter *adapter); #endif + +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 +int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para, + u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr); +int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d); + +int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, enum halmac_snd_role role, + enum halmac_data_rate rate); +int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, enum halmac_snd_role role); + +int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate, + u8 fixrate_en, u8 *new_rate); + +int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role, + u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en, + u32 *given_gid_tab, u32 *given_user_pos); +#define rtw_halmac_bf_cfg_mu_bfee(d, gid_tab, user_pos) \ + rtw_halmac_bf_cfg_mu_mimo(d, HAL_BFEE, NULL, 0, 0, gid_tab, user_pos) + +#endif /* RTW_BEAMFORMING_VERSION_2 */ +#endif /* CONFIG_BEAMFORMING */ + #endif /* _HAL_HALMAC_H_ */ diff --git a/hal/hal_hci/hal_pci.c b/hal/hal_hci/hal_pci.c index 6b2e671..0fb6850 100644 --- a/hal/hal_hci/hal_pci.c +++ b/hal/hal_hci/hal_pci.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_PCI_C_ #include diff --git a/hal/hal_intf.c b/hal/hal_intf.c index 5a27a1f..f852abf 100644 --- a/hal/hal_intf.c +++ b/hal/hal_intf.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_INTF_C_ @@ -33,9 +28,12 @@ const u32 _chip_type_to_odm_ic_type[] = { ODM_RTL8814A, ODM_RTL8703B, ODM_RTL8188F, + ODM_RTL8188F, ODM_RTL8822B, ODM_RTL8723D, ODM_RTL8821C, + ODM_RTL8710B, + ODM_RTL8192F, 0, }; @@ -56,7 +54,7 @@ u8 rtw_hal_read_chip_info(_adapter *padapter) { u8 rtn = _SUCCESS; u8 hci_type = rtw_get_intf_type(padapter); - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); /* before access eFuse, make sure card enable has been called */ if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI) @@ -80,12 +78,56 @@ void rtw_hal_read_chip_version(_adapter *padapter) rtw_odm_init_ic_type(padapter); } +static void rtw_init_wireless_mode(_adapter *padapter) +{ + u8 proto_wireless_mode = 0; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + if(hal_spec->proto_cap & PROTO_CAP_11B) + proto_wireless_mode |= WIRELESS_11B; + + if(hal_spec->proto_cap & PROTO_CAP_11G) + proto_wireless_mode |= WIRELESS_11G; +#ifdef CONFIG_80211AC_VHT + if(hal_spec->band_cap & BAND_CAP_5G) + proto_wireless_mode |= WIRELESS_11A; +#endif + +#ifdef CONFIG_80211N_HT + if(hal_spec->proto_cap & PROTO_CAP_11N) { + + if(hal_spec->band_cap & BAND_CAP_2G) + proto_wireless_mode |= WIRELESS_11_24N; + if(hal_spec->band_cap & BAND_CAP_5G) + proto_wireless_mode |= WIRELESS_11_5N; + } +#endif + +#ifdef CONFIG_80211AC_VHT + if(hal_spec->proto_cap & PROTO_CAP_11AC) + proto_wireless_mode |= WIRELESS_11AC; +#endif + padapter->registrypriv.wireless_mode &= proto_wireless_mode; +} + void rtw_hal_def_value_init(_adapter *padapter) { if (is_primary_adapter(padapter)) { + /*init fw_psmode_iface_id*/ + adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff; + /*wireless_mode*/ + rtw_init_wireless_mode(padapter); padapter->hal_func.init_default_value(padapter); rtw_init_hal_com_default_value(padapter); + + #ifdef CONFIG_FW_MULTI_PORT_SUPPORT + adapter_to_dvobj(padapter)->dft.port_id = 0xFF; + adapter_to_dvobj(padapter)->dft.mac_id = 0xFF; + #endif + #ifdef CONFIG_HW_P0_TSF_SYNC + adapter_to_dvobj(padapter)->p0_tsf.sync_port = MAX_HW_PORT; + adapter_to_dvobj(padapter)->p0_tsf.offset = 0; + #endif { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); @@ -97,6 +139,7 @@ void rtw_hal_def_value_init(_adapter *padapter) dvobj->cam_ctl.sec_cap = hal_spec->sec_cap; dvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT); } + GET_HAL_DATA(padapter)->rx_tsf_addr_filter_config = 0; } } @@ -109,6 +152,7 @@ u8 rtw_hal_data_init(_adapter *padapter) RTW_INFO("cant not alloc memory for HAL DATA\n"); return _FAIL; } + rtw_phydm_priv_init(padapter); } return _SUCCESS; } @@ -154,26 +198,49 @@ void rtw_hal_dm_deinit(_adapter *padapter) _rtw_spinlock_free(&pHalData->IQKSpinLock); } } -void rtw_hal_sw_led_init(_adapter *padapter) + +#ifdef CONFIG_RTW_SW_LED +void rtw_hal_sw_led_init(_adapter *padapter) { - if (padapter->hal_func.InitSwLeds) + struct led_priv *ledpriv = adapter_to_led(padapter); + + if (ledpriv->bRegUseLed == _FALSE) + return; + + if (!is_primary_adapter(padapter)) + return; + + if (padapter->hal_func.InitSwLeds) { padapter->hal_func.InitSwLeds(padapter); + rtw_led_set_ctl_en_mask_primary(padapter); + rtw_led_set_iface_en(padapter, 1); + } } void rtw_hal_sw_led_deinit(_adapter *padapter) { + struct led_priv *ledpriv = adapter_to_led(padapter); + + if (ledpriv->bRegUseLed == _FALSE) + return; + + if (!is_primary_adapter(padapter)) + return; + if (padapter->hal_func.DeInitSwLeds) padapter->hal_func.DeInitSwLeds(padapter); } +#endif u32 rtw_hal_power_on(_adapter *padapter) { u32 ret = 0; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); ret = padapter->hal_func.hal_power_on(padapter); #ifdef CONFIG_BT_COEXIST - if (ret == _SUCCESS) + if ((ret == _SUCCESS) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) rtw_btcoex_PowerOnSetting(padapter); #endif @@ -205,27 +272,85 @@ void rtw_hal_init_opmode(_adapter *padapter) networkType = Ndis802_11IBSS; else if (fw_state & WIFI_STATION_STATE) networkType = Ndis802_11Infrastructure; +#ifdef CONFIG_AP_MODE else if (fw_state & WIFI_AP_STATE) networkType = Ndis802_11APMode; +#endif +#ifdef CONFIG_RTW_MESH + else if (fw_state & WIFI_MESH_STATE) + networkType = Ndis802_11_mesh; +#endif else return; - rtw_setopmode_cmd(padapter, networkType, _FALSE); + rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY); +} + +#ifdef CONFIG_NEW_NETDEV_HDL +uint rtw_hal_iface_init(_adapter *adapter) +{ + uint status = _SUCCESS; + + rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter)); + #ifdef RTW_HALMAC + rtw_hal_hw_port_enable(adapter); + #endif + rtw_sec_restore_wep_key(adapter); + rtw_hal_init_opmode(adapter); + rtw_hal_start_thread(adapter); + return status; } +uint rtw_hal_init(_adapter *padapter) +{ + uint status = _SUCCESS; + + status = padapter->hal_func.hal_init(padapter); + if (status == _SUCCESS) { + rtw_set_hw_init_completed(padapter, _TRUE); + if (padapter->registrypriv.notch_filter == 1) + rtw_hal_notch_filter(padapter, 1); + rtw_led_control(padapter, LED_CTL_POWER_ON); + init_hw_mlme_ext(padapter); + #ifdef CONFIG_RF_POWER_TRIM + rtw_bb_rf_gain_offset(padapter); + #endif /*CONFIG_RF_POWER_TRIM*/ + GET_PRIMARY_ADAPTER(padapter)->bup = _TRUE; /*temporary*/ + #ifdef CONFIG_MI_WITH_MBSSID_CAM + rtw_mi_set_mbid_cam(padapter); + #endif + #ifdef CONFIG_SUPPORT_MULTI_BCN + rtw_ap_multi_bcn_cfg(padapter); + #endif + #if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) + #ifdef CONFIG_DYNAMIC_SOML + rtw_dyn_soml_config(padapter); + #endif + #endif +#ifdef CONFIG_RTW_TX_2PATH_EN + rtw_phydm_tx_2path_en(padapter); +#endif + } else { + rtw_set_hw_init_completed(padapter, _FALSE); + RTW_ERR("%s: hal_init fail\n", __func__); + } + return status; +} +#else uint rtw_hal_init(_adapter *padapter) { uint status = _SUCCESS; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); int i; status = padapter->hal_func.hal_init(padapter); if (status == _SUCCESS) { - pHalData->hw_init_completed = _TRUE; - rtw_restore_mac_addr(padapter); - + rtw_set_hw_init_completed(padapter, _TRUE); + rtw_mi_set_mac_addr(padapter);/*set mac addr of all ifaces*/ + #ifdef RTW_HALMAC + rtw_restore_hw_port_cfg(padapter); + #endif if (padapter->registrypriv.notch_filter == 1) rtw_hal_notch_filter(padapter, 1); @@ -238,32 +363,45 @@ uint rtw_hal_init(_adapter *padapter) rtw_hal_init_opmode(padapter); -#ifdef CONFIG_RF_POWER_TRIM + #ifdef CONFIG_RF_POWER_TRIM rtw_bb_rf_gain_offset(padapter); -#endif /*CONFIG_RF_POWER_TRIM*/ + #endif /*CONFIG_RF_POWER_TRIM*/ + #ifdef CONFIG_SUPPORT_MULTI_BCN + rtw_ap_multi_bcn_cfg(padapter); + #endif + +#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) +#ifdef CONFIG_DYNAMIC_SOML + rtw_dyn_soml_config(padapter); +#endif +#endif + +#ifdef CONFIG_RTW_TX_2PATH_EN + rtw_phydm_tx_2path_en(padapter); +#endif } else { - pHalData->hw_init_completed = _FALSE; - RTW_INFO("rtw_hal_init: hal_init fail\n"); + rtw_set_hw_init_completed(padapter, _FALSE); + RTW_ERR("%s: fail\n", __func__); } return status; } +#endif uint rtw_hal_deinit(_adapter *padapter) { uint status = _SUCCESS; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); int i; status = padapter->hal_func.hal_deinit(padapter); if (status == _SUCCESS) { rtw_led_control(padapter, LED_CTL_POWER_OFF); - pHalData->hw_init_completed = _FALSE; + rtw_set_hw_init_completed(padapter, _FALSE); } else RTW_INFO("\n rtw_hal_deinit: hal_init fail\n"); @@ -271,9 +409,9 @@ uint rtw_hal_deinit(_adapter *padapter) return status; } -void rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val) +u8 rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val) { - padapter->hal_func.set_hw_reg_handler(padapter, variable, val); + return padapter->hal_func.set_hw_reg_handler(padapter, variable, val); } void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val) @@ -335,7 +473,7 @@ s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan) #ifdef RTW_HALMAC s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem) { - u32 dlfw_start_time = rtw_get_current_time(); + systime dlfw_start_time = rtw_get_current_time(); struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct debug_priv *pdbgpriv = &dvobj->drv_dbg; s32 rst = _FALSE; @@ -460,38 +598,18 @@ s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe) s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) { s32 ret = _FAIL; - u8 *pframe, subtype; - struct rtw_ieee80211_hdr *pwlanhdr; - struct sta_info *psta; - struct sta_priv *pstapriv = &padapter->stapriv; update_mgntframe_attrib_addr(padapter, pmgntframe); - pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; - subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ - - /* pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; */ - /* _rtw_memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN); */ - -#ifdef CONFIG_IEEE80211W - if (padapter->securitypriv.binstallBIPkey == _TRUE && (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || - subtype == WIFI_ACTION)) { - if (IS_MCAST(pmgntframe->attrib.ra) && pmgntframe->attrib.key_type != IEEE80211W_NO_KEY) { - pmgntframe->attrib.encrypt = _BIP_; - /* pmgntframe->attrib.bswenc = _TRUE; */ - } else if (pmgntframe->attrib.key_type != IEEE80211W_NO_KEY) { - psta = rtw_get_stainfo(pstapriv, pmgntframe->attrib.ra); - if (psta && psta->bpairwise_key_installed == _TRUE) { - pmgntframe->attrib.encrypt = _AES_; - pmgntframe->attrib.bswenc = _TRUE; - } else { - RTW_INFO("%s, %d, bpairwise_key_installed is FALSE\n", __func__, __LINE__); - goto no_mgmt_coalesce; - } - } - RTW_INFO("encrypt=%d, bswenc=%d\n", pmgntframe->attrib.encrypt, pmgntframe->attrib.bswenc); + +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) + if ((!MLME_IS_MESH(padapter) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) + #ifdef CONFIG_RTW_MESH + || (MLME_IS_MESH(padapter) && padapter->mesh_info.mesh_auth_id) + #endif + ) rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe); - } -#endif /* CONFIG_IEEE80211W */ +#endif + no_mgmt_coalesce: ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe); return ret; @@ -515,97 +633,44 @@ void rtw_hal_free_recv_priv(_adapter *padapter) padapter->hal_func.free_recv_priv(padapter); } -void rtw_update_ramask(_adapter *padapter, struct sta_info *psta, u32 mac_id, u8 rssi_level, u8 is_update_bw) +void rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta) { - struct macid_cfg h2c_macid_cfg; - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); - u8 disable_cck_rate = FALSE, MimoPs_enable = FALSE; - u32 ratr_bitmap_msb = 0, ratr_bitmap_lsb = 0; - u64 mask = 0, rate_bitmap = 0; - u8 bw, short_gi; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); if (psta == NULL) { - RTW_ERR(FUNC_ADPT_FMT" macid:%u, sta is NULL\n", FUNC_ADPT_ARG(padapter), mac_id); + RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(padapter)); rtw_warn_on(1); return; } - _rtw_memset(&h2c_macid_cfg, 0, sizeof(struct macid_cfg)); - - bw = rtw_get_tx_bw_mode(padapter, psta); - short_gi = query_ra_short_GI(psta, bw); - - ratr_bitmap_msb = (u32)(psta->ra_mask >> 32); - ratr_bitmap_lsb = (u32)(psta->ra_mask); - - phydm_update_hal_ra_mask(&hal_data->odmpriv, psta->wireless_mode, hal_data->rf_type, bw, MimoPs_enable, disable_cck_rate, &ratr_bitmap_msb, &ratr_bitmap_lsb, rssi_level); - mask = (((u64)ratr_bitmap_msb) << 32) | ((u64)ratr_bitmap_lsb); - -#ifdef CONFIG_BT_COEXIST - if (hal_data->EEPROMBluetoothCoexist == 1) { - rate_bitmap = rtw_btcoex_GetRaMask(padapter); - mask &= ~rate_bitmap; - } -#endif /* CONFIG_BT_COEXIST */ - -#ifdef CONFIG_CMCC_TEST -#ifdef CONFIG_BT_COEXIST - if (pmlmeext->cur_wireless_mode & WIRELESS_11G) { - if (mac_id == 0) { - RTW_INFO("CMCC_BT update raid entry, mask=0x%x\n", mask); - /*mask &=0xffffffc0; //disable CCK & <12M OFDM rate for 11G mode for CMCC */ - mask &= 0xffffff00; /*disable CCK & <24M OFDM rate for 11G mode for CMCC */ - RTW_INFO("CMCC_BT update raid entry, mask=0x%x\n", mask); +#ifdef CONFIG_AP_MODE + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { + if (psta->cmn.aid > padapter->stapriv.max_aid) { + RTW_ERR("station aid %d exceed the max number\n", psta->cmn.aid); + rtw_warn_on(1); + return; } + rtw_ap_update_sta_ra_info(padapter, psta); } -#endif #endif + psta->cmn.ra_info.ra_bw_mode = rtw_get_tx_bw_mode(padapter, psta); /*set correct initial date rate for each mac_id */ - hal_data->INIDATA_RATE[mac_id] = psta->init_rate; - - - RTW_INFO("%s => mac_id:%d, networkType:0x%02x, mask:0x%016llx\n\t ==> rssi_level:%d, rate_bitmap:0x%016llx, shortGIrate=%d\n\t ==> bw:%d, ignore_bw:0x%d\n", - __func__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap, short_gi, bw, (!is_update_bw)); - - rtw_macid_ctl_set_bw(macid_ctl, mac_id, bw); - rtw_macid_ctl_set_vht_en(macid_ctl, mac_id, is_supported_vht(psta->wireless_mode)); - rtw_macid_ctl_set_rate_bmp0(macid_ctl, mac_id, mask); - rtw_macid_ctl_set_rate_bmp1(macid_ctl, mac_id, mask >> 32); - rtw_update_tx_rate_bmp(adapter_to_dvobj(padapter)); - - h2c_macid_cfg.mac_id = mac_id; - h2c_macid_cfg.rate_id = psta->raid; - h2c_macid_cfg.bandwidth = bw; - h2c_macid_cfg.ignore_bw = (!is_update_bw); - h2c_macid_cfg.short_gi = short_gi; - h2c_macid_cfg.ra_mask = mask; + hal_data->INIDATA_RATE[psta->cmn.mac_id] = psta->init_rate; - padapter->hal_func.update_ra_mask_handler(padapter, psta, &h2c_macid_cfg); + rtw_phydm_ra_registed(padapter, psta); } -void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level, u8 is_update_bw) +void rtw_hal_update_ra_mask(struct sta_info *psta) { _adapter *padapter; - struct mlme_priv *pmlmepriv; if (!psta) return; padapter = psta->padapter; - - pmlmepriv = &(padapter->mlmepriv); - - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) - add_RATid(padapter, psta, rssi_level, is_update_bw); - else { - psta->raid = rtw_hal_networktype_to_raid(padapter, psta); - rtw_update_ramask(padapter, psta, psta->mac_id, rssi_level, is_update_bw); - } + rtw_sta_ra_registed(padapter, psta); } /* Start specifical interface thread */ @@ -642,30 +707,34 @@ void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data) padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data); } -u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask) +u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask) { u32 data = 0; if (padapter->hal_func.read_rfreg) { data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask); - if (match_rf_read_sniff_ranges(eRFPath, RegAddr, BitMask)) { + #ifdef DBG_IO + if (match_rf_read_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) { RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n" , eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data); } + #endif } return data; } -void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data) { if (padapter->hal_func.write_rfreg) { - if (match_rf_write_sniff_ranges(eRFPath, RegAddr, BitMask)) { + #ifdef DBG_IO + if (match_rf_write_sniff_ranges(padapter, eRFPath, RegAddr, BitMask)) { RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n" , eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data); } + #endif padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data); @@ -676,6 +745,23 @@ void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMa } } +#ifdef CONFIG_SYSON_INDIRECT_ACCESS +u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask) +{ + u32 data = 0; + if (padapter->hal_func.read_syson_reg) + data = padapter->hal_func.read_syson_reg(padapter, RegAddr, BitMask); + + return data; +} + +void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data) +{ + if (padapter->hal_func.write_syson_reg) + padapter->hal_func.write_syson_reg(padapter, RegAddr, BitMask, Data); +} +#endif + #if defined(CONFIG_PCI_HCI) s32 rtw_hal_interrupt_handler(_adapter *padapter) { @@ -691,22 +777,22 @@ void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf) } #endif -void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80) +void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0; u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0; u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0; u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0; - odm_acquire_spin_lock(pDM_Odm, RT_IQK_SPINLOCK); - if (pDM_Odm->rf_calibrate_info.is_iqk_in_progress == _TRUE) + if (rtw_phydm_is_iqk_in_progress(padapter)) RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__); - odm_release_spin_lock(pDM_Odm, RT_IQK_SPINLOCK); +#ifdef CONFIG_MP_INCLUDED /* MP mode channel don't use secondary channel */ - if (rtw_mi_mp_mode_check(padapter) == _FALSE) { + if (rtw_mp_mode_check(padapter) == _FALSE) +#endif + { #if 0 if (cch_160 != 0) cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80); @@ -743,15 +829,13 @@ void rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel) void rtw_hal_dm_watchdog(_adapter *padapter) { -#ifdef CONFIG_MCC_MODE - if (MCC_EN(padapter)) { - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) - return; - } -#endif /* CONFIG_MCC_MODE */ + rtw_hal_turbo_edca(padapter); padapter->hal_func.hal_dm_watchdog(padapter); +#ifdef CONFIG_PCI_DYNAMIC_ASPM + rtw_pci_aspm_config_dynamic_l1_ilde_time(padapter); +#endif } #ifdef CONFIG_LPS_LCLK_WD_TIMER @@ -764,11 +848,10 @@ void rtw_hal_dm_watchdog_in_lps(_adapter *padapter) #endif #endif - if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) { - padapter->hal_func.hal_dm_watchdog_in_lps(padapter);/* this function caller is in interrupt context */ - } + if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) + rtw_phydm_watchdog_in_lps_lclk(padapter);/* this function caller is in interrupt context */ } -#endif +#endif /*CONFIG_LPS_LCLK_WD_TIMER*/ void rtw_hal_bcn_related_reg_setting(_adapter *padapter) { @@ -914,8 +997,6 @@ bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 * #endif s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) { - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; u8 sub_id = 0; s32 ret = _SUCCESS; @@ -935,7 +1016,10 @@ s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) rtw_btcoex_BtMpRptNotify(adapter, plen, payload); break; case C2H_MAILBOX_STATUS: - RTW_INFO_DUMP("C2H_MAILBOX_STATUS: ", payload, plen); + RTW_DBG_DUMP("C2H_MAILBOX_STATUS: ", payload, plen); + break; + case C2H_WLAN_INFO: + rtw_btcoex_WlFwDbgInfoNotify(adapter, payload, plen); break; #endif /* CONFIG_BT_COEXIST */ @@ -979,13 +1063,17 @@ s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) c2h_customer_str_rpt_2_hdl(adapter, payload, plen); break; #endif - +#ifdef RTW_PER_CMD_SUPPORT_FW + case C2H_PER_RATE_RPT: + c2h_per_rate_rpt_hdl(adapter, payload, plen); + break; +#endif case C2H_EXTEND: sub_id = payload[0]; /* no handle, goto default */ default: - if (phydm_c2H_content_parsing(odm, id, plen, payload) != TRUE) + if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE) ret = _FAIL; break; } @@ -1036,55 +1124,164 @@ s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter) return GET_HAL_DATA(padapter)->bDisableSWChannelPlan; } -s32 rtw_hal_macid_sleep(PADAPTER padapter, u8 macid) +static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - u8 support; - - support = _FALSE; - rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support); - if (_FALSE == support) - return _FAIL; + struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); + u16 reg_sleep; + u8 bit_shift; + u32 val32; + s32 ret = _FAIL; if (macid >= macid_ctl->num) { - RTW_ERR(FUNC_ADPT_FMT": Invalid macid(%u)\n", - FUNC_ADPT_ARG(padapter), macid); - return _FAIL; + RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n" + , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid); + goto exit; } - rtw_hal_set_hwreg(padapter, HW_VAR_MACID_SLEEP, &macid); + if (macid < 32) { + reg_sleep = macid_ctl->reg_sleep_m0; + bit_shift = macid; + #if (MACID_NUM_SW_LIMIT > 32) + } else if (macid < 64) { + reg_sleep = macid_ctl->reg_sleep_m1; + bit_shift = macid - 32; + #endif + #if (MACID_NUM_SW_LIMIT > 64) + } else if (macid < 96) { + reg_sleep = macid_ctl->reg_sleep_m2; + bit_shift = macid - 64; + #endif + #if (MACID_NUM_SW_LIMIT > 96) + } else if (macid < 128) { + reg_sleep = macid_ctl->reg_sleep_m3; + bit_shift = macid - 96; + #endif + } else { + rtw_warn_on(1); + goto exit; + } - return _SUCCESS; + if (!reg_sleep) { + rtw_warn_on(1); + goto exit; + } + + val32 = rtw_read32(adapter, reg_sleep); + RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n" + , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" + , macid, reg_sleep, val32); + + ret = _SUCCESS; + + if (sleep) { + if (val32 & BIT(bit_shift)) + goto exit; + val32 |= BIT(bit_shift); + } else { + if (!(val32 & BIT(bit_shift))) + goto exit; + val32 &= ~BIT(bit_shift); + } + + rtw_write32(adapter, reg_sleep, val32); + +exit: + return ret; } -s32 rtw_hal_macid_wakeup(PADAPTER padapter, u8 macid) +inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid) { - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - u8 support; + return _rtw_hal_macid_sleep(adapter, macid, 1); +} - support = _FALSE; - rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support); - if (_FALSE == support) - return _FAIL; +inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid) +{ + return _rtw_hal_macid_sleep(adapter, macid, 0); +} - if (macid >= macid_ctl->num) { - RTW_ERR(FUNC_ADPT_FMT": Invalid macid(%u)\n", - FUNC_ADPT_ARG(padapter), macid); - return _FAIL; - } +static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep) +{ + struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); + u16 reg_sleep; + u32 m; + u8 mid = 0; + u32 val32; + + do { + if (mid == 0) { + m = bmp->m0; + reg_sleep = macid_ctl->reg_sleep_m0; + #if (MACID_NUM_SW_LIMIT > 32) + } else if (mid == 1) { + m = bmp->m1; + reg_sleep = macid_ctl->reg_sleep_m1; + #endif + #if (MACID_NUM_SW_LIMIT > 64) + } else if (mid == 2) { + m = bmp->m2; + reg_sleep = macid_ctl->reg_sleep_m2; + #endif + #if (MACID_NUM_SW_LIMIT > 96) + } else if (mid == 3) { + m = bmp->m3; + reg_sleep = macid_ctl->reg_sleep_m3; + #endif + } else { + rtw_warn_on(1); + break; + } + + if (m == 0) + goto move_next; + + if (!reg_sleep) { + rtw_warn_on(1); + break; + } + + val32 = rtw_read32(adapter, reg_sleep); + RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n" + , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" + , mid, m, reg_sleep, val32); + + if (sleep) { + if ((val32 & m) == m) + goto move_next; + val32 |= m; + } else { + if ((val32 & m) == 0) + goto move_next; + val32 &= ~m; + } + + rtw_write32(adapter, reg_sleep, val32); - rtw_hal_set_hwreg(padapter, HW_VAR_MACID_WAKEUP, &macid); +move_next: + mid++; + } while (mid * 32 < MACID_NUM_SW_LIMIT); return _SUCCESS; } +inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter) +{ + struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); + + return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 1); +} + +inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter) +{ + struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter); + + return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 0); +} + s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) { _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter); - if (pri_adapter->bFWReady == _TRUE) + if (GET_HAL_DATA(pri_adapter)->bFWReady == _TRUE) return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer); else if (padapter->registrypriv.mp_mode == 0) RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n" @@ -1098,9 +1295,21 @@ void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen, padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame); } + u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan) { - return adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan); + u8 num = 0; + + + if (adapter->hal_func.hal_get_tx_buff_rsvd_page_num) { + num = adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan); + } else { +#ifdef RTW_HALMAC + num = GET_HAL_DATA(adapter)->drv_rsvd_page_number; +#endif /* RTW_HALMAC */ + } + + return num; } #ifdef CONFIG_GPIO_API @@ -1127,18 +1336,20 @@ void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num) } #endif +#ifdef CONFIG_FW_CORRECT_BCN void rtw_hal_fw_correct_bcn(_adapter *padapter) { if (padapter->hal_func.fw_correct_bcn) padapter->hal_func.fw_correct_bcn(padapter); } +#endif -void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, u8 rfpath, u8 rate) +void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, enum rf_path rfpath, u8 rate) { return padapter->hal_func.set_tx_power_index_handler(padapter, powerindex, rfpath, rate); } -u8 rtw_hal_get_tx_power_index(PADAPTER padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) +u8 rtw_hal_get_tx_power_index(PADAPTER padapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) { return padapter->hal_func.get_tx_power_index_handler(padapter, rfpath, rate, bandwidth, channel, tic); } @@ -1171,6 +1382,21 @@ u8 rtw_hal_init_phy(PADAPTER adapter) } #endif /* RTW_HALMAC */ +#ifdef CONFIG_RFKILL_POLL +bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid) +{ + bool ret; + + if (adapter->hal_func.hal_radio_onoff_check) + ret = adapter->hal_func.hal_radio_onoff_check(adapter, valid); + else { + *valid = 0; + ret = _FALSE; + } + return ret; +} +#endif + #define rtw_hal_error_msg(ops_fun) \ RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun) @@ -1320,12 +1546,6 @@ u8 rtw_hal_ops_check(_adapter *padapter) rtw_hal_error_msg("hal_dm_watchdog"); ret = _FAIL; } -#ifdef CONFIG_LPS_LCLK_WD_TIMER - if (NULL == padapter->hal_func.hal_dm_watchdog_in_lps) { - rtw_hal_error_msg("hal_dm_watchdog_in_lps"); - ret = _FAIL; - } -#endif /*** xxx section ***/ if (NULL == padapter->hal_func.set_chnl_bw_handler) { @@ -1357,10 +1577,6 @@ u8 rtw_hal_ops_check(_adapter *padapter) rtw_hal_error_msg("SetHalODMVarHandler"); ret = _FAIL; } - if (NULL == padapter->hal_func.update_ra_mask_handler) { - rtw_hal_error_msg("update_ra_mask_handler"); - ret = _FAIL; - } if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) { rtw_hal_error_msg("SetBeaconRelatedRegistersHandler"); @@ -1390,10 +1606,13 @@ u8 rtw_hal_ops_check(_adapter *padapter) ret = _FAIL; } #endif + +#ifndef RTW_HALMAC if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) { rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num"); ret = _FAIL; } +#endif /* !RTW_HALMAC */ #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) @@ -1416,20 +1635,18 @@ u8 rtw_hal_ops_check(_adapter *padapter) } #endif - if ((IS_HARDWARE_TYPE_8814A(padapter) - || IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8822BS(padapter)) + #ifdef CONFIG_FW_CORRECT_BCN + if (IS_HARDWARE_TYPE_8814A(padapter) && NULL == padapter->hal_func.fw_correct_bcn) { rtw_hal_error_msg("fw_correct_bcn"); ret = _FAIL; } + #endif - if (IS_HARDWARE_TYPE_8822B(padapter) || IS_HARDWARE_TYPE_8821C(padapter)) { - if (!padapter->hal_func.set_tx_power_index_handler) { - rtw_hal_error_msg("set_tx_power_index_handler"); - ret = _FAIL; - } + if (!padapter->hal_func.set_tx_power_index_handler) { + rtw_hal_error_msg("set_tx_power_index_handler"); + ret = _FAIL; } - if (!padapter->hal_func.get_tx_power_index_handler) { rtw_hal_error_msg("get_tx_power_index_handler"); ret = _FAIL; @@ -1477,6 +1694,13 @@ u8 rtw_hal_ops_check(_adapter *padapter) ret = _FAIL; } #endif /* RTW_HALMAC */ + +#ifdef CONFIG_RFKILL_POLL + if (padapter->hal_func.hal_radio_onoff_check == NULL) { + rtw_hal_error_msg("hal_radio_onoff_check"); + ret = _FAIL; + } +#endif #endif return ret; } diff --git a/hal/hal_mcc.c b/hal/hal_mcc.c index 6d1a217..179d4d5 100644 --- a/hal/hal_mcc.c +++ b/hal/hal_mcc.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - ******************************************************************************/ + *****************************************************************************/ #ifdef CONFIG_MCC_MODE #define _HAL_MCC_C_ @@ -24,21 +20,24 @@ #include /* HAL_DATA */ #include /* power control */ -#define MCC_DURATION_IDX 0 +/* use for AP/GO + STA/GC case */ +#define MCC_DURATION_IDX 0 /* druration for station side */ #define MCC_TSF_SYNC_OFFSET_IDX 1 #define MCC_START_TIME_OFFSET_IDX 2 #define MCC_INTERVAL_IDX 3 #define MCC_GUARD_OFFSET0_IDX 4 #define MCC_GUARD_OFFSET1_IDX 5 +#define MCC_STOP_THRESHOLD 6 #define TU 1024 /* 1 TU equals 1024 microseconds */ -/* port 1 druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/ -u8 mcc_switch_channel_policy_table[][6]={ - {35, 50, 30, 100, 0, 0}, - {19, 50, 40, 100, 2, 2}, - {25, 50, 30, 100, 5, 5}, +/* druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/ +u8 mcc_switch_channel_policy_table[][7]={ + {20, 50, 40, 100, 0, 0, 30}, + {80, 50, 10, 100, 0, 0, 30}, + {36, 50, 32, 100, 0, 0, 30}, + {30, 50, 35, 100, 0, 0, 30}, }; -const int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /6; +const int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /7; static void dump_iqk_val_table(PADAPTER padapter) { @@ -49,6 +48,9 @@ static void dump_iqk_val_table(PADAPTER padapter) u8 backup_chan_idx = 0; u8 backup_reg_idx = 0; +#ifdef CONFIG_MCC_MODE_V2 +#else + RTW_INFO("=============dump IQK backup table================\n"); for (backup_chan_idx = 0; backup_chan_idx < MAX_IQK_INFO_BACKUP_CHNL_NUM; backup_chan_idx++) { for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx++) { @@ -64,6 +66,8 @@ static void dump_iqk_val_table(PADAPTER padapter) } } RTW_INFO("=============================================\n"); + +#endif } static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_len) @@ -76,14 +80,14 @@ static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_le u8 noa_desc_num = 1; u8 opp_ps = 0; /* Disable OppPS */ u8 noa_count = 255; - u32 noa_duration = 0x20; - u32 noa_interval = 0x64; + u32 noa_duration; + u32 noa_interval; u8 noa_index = 0; u8 mcc_policy_idx = 0; mcc_policy_idx = pmccobjpriv->policy_index; - noa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX]; - noa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX]; + noa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX] * TU; + noa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX] * TU; /* P2P OUI(4 bytes) */ _rtw_memcpy(p2p_noa_attr_ie, P2P_OUI, 4); @@ -94,7 +98,7 @@ static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_le p2p_noa_attr_len = p2p_noa_attr_len + 1; /* attrute length(2 bytes) length = noa_desc_num*13 + 2 */ - RTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num*13 + 2)); + RTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num * 13 + 2)); p2p_noa_attr_len = p2p_noa_attr_len + 2; /* Index (1 byte) */ @@ -110,11 +114,11 @@ static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_le p2p_noa_attr_len = p2p_noa_attr_len + 1; /* NoA Duration (4 bytes) unit: microseconds */ - RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_duration * TU)); + RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_duration); p2p_noa_attr_len = p2p_noa_attr_len + 4; /* NoA Interval (4 bytes) unit: microseconds */ - RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_interval * TU)); + RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_interval); p2p_noa_attr_len = p2p_noa_attr_len + 4; /* NoA Start Time (4 bytes) unit: microseconds */ @@ -139,6 +143,7 @@ static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_le static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter) { struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); u8 *pos = NULL; @@ -146,14 +151,22 @@ static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter) if (pmccadapriv->p2p_go_noa_ie_len == 0) rtw_hal_mcc_build_p2p_noa_attr(padapter, pmccadapriv->p2p_go_noa_ie, &pmccadapriv->p2p_go_noa_ie_len); else { - /* has noa attribut, modify it */ + /* has noa attribut, modify it */ + u32 noa_duration = 0; + /* update index */ pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 15; /* 0~255 */ (*pos) = ((*pos) + 1) % 256; - if (1) + if (0) RTW_INFO("indxe:%d\n", (*pos)); + + /* update duration */ + noa_duration = mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX] * TU; + pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 12; + RTW_PUT_LE32(pos, noa_duration); + /* update start time */ pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 4; RTW_PUT_LE32(pos, pmccadapriv->noa_start_time); @@ -167,16 +180,8 @@ static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter) } if (0) { - u8 i = 0; RTW_INFO("p2p_go_noa_ie_len:%d\n", pmccadapriv->p2p_go_noa_ie_len); - - for (i = 0;i < pmccadapriv->p2p_go_noa_ie_len; i++) { - if ((i+1)%8 != 0) - printk("0x%02x ", pmccadapriv->p2p_go_noa_ie[i]); - else - printk("0x%02x\n", pmccadapriv->p2p_go_noa_ie[i]); - } - printk("\n"); + RTW_INFO_DUMP("\n", pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len); } update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE); } @@ -204,6 +209,7 @@ void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter) u8 take_care_iqk = _FALSE; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); _adapter *iface = NULL; + struct mcc_adapter_priv *mccadapriv = NULL; u8 i = 0; rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk); @@ -213,6 +219,10 @@ void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter) if (iface == NULL) continue; + mccadapriv = &iface->mcc_adapterpriv; + if (mccadapriv->role == MCC_ROLE_MAX) + continue; + rtw_hal_ch_sw_iqk_info_restore(iface, CH_SW_USE_CASE_MCC); } } @@ -245,101 +255,74 @@ void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status) pmccobjpriv->mcc_status &= (~mcc_status); } -void rtw_hal_mcc_update_switch_channel_policy_table(PADAPTER padapter) +static void rtw_hal_mcc_update_policy_table(PADAPTER adapter) { - struct registry_priv *registry_par = &padapter->registrypriv; - u8 idx = 0; - - if (registry_par->rtw_mcc_policy_table_idx < 0) - return; - - if (registry_par->rtw_mcc_policy_table_idx >= mcc_max_policy_num) { - RTW_INFO("[MCC] mcc_policy_table_idx error, do not update policy table\n"); - return; - } - - idx = registry_par->rtw_mcc_policy_table_idx; - - if (registry_par->rtw_mcc_duration > 0) - mcc_switch_channel_policy_table[idx][MCC_DURATION_IDX] = registry_par->rtw_mcc_duration; - - if (registry_par->rtw_mcc_tsf_sync_offset > 0) - mcc_switch_channel_policy_table[idx][MCC_TSF_SYNC_OFFSET_IDX] = registry_par->rtw_mcc_tsf_sync_offset; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + u8 mcc_duration = mccobjpriv->duration; + s8 mcc_policy_idx = mccobjpriv->policy_index; + u8 interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX]; + u8 new_mcc_duration_time = 0; + u8 new_starttime_offset = 0; - if (registry_par->rtw_mcc_start_time_offset > 0) - mcc_switch_channel_policy_table[idx][MCC_START_TIME_OFFSET_IDX] = registry_par->rtw_mcc_start_time_offset; + /* convert % to ms */ + new_mcc_duration_time = mcc_duration * interval / 100; - if (registry_par->rtw_mcc_interval > 0) - mcc_switch_channel_policy_table[idx][MCC_INTERVAL_IDX] = registry_par->rtw_mcc_interval; + /* start time offset = (interval - duration time)/2 */ + new_starttime_offset = (interval - new_mcc_duration_time) >> 1; - if (registry_par->rtw_mcc_guard_offset0 >= 0) - mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET0_IDX] = registry_par->rtw_mcc_guard_offset0; + /* update modified parameters */ + mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX] + = new_mcc_duration_time; - if (registry_par->rtw_mcc_guard_offset1 >= 0) - mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET1_IDX] = registry_par->rtw_mcc_guard_offset1; + mcc_switch_channel_policy_table[mcc_policy_idx][MCC_START_TIME_OFFSET_IDX] + = new_starttime_offset; + } static void rtw_hal_config_mcc_switch_channel_setting(PADAPTER padapter) { - struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); struct registry_priv *registry_par = &padapter->registrypriv; - u8 interval = pmlmepriv->cur_network.network.Configuration.BeaconPeriod; - u8 i = 0; + u8 mcc_duration = 0; s8 mcc_policy_idx = 0; - rtw_hal_mcc_update_switch_channel_policy_table(padapter); mcc_policy_idx = registry_par->rtw_mcc_policy_table_idx; + mcc_duration = mccobjpriv->duration; if (mcc_policy_idx < 0 || mcc_policy_idx >= mcc_max_policy_num) { - pmccobjpriv->policy_index = 0; - RTW_INFO("[MCC] can't find table(%d,%d,%d), use default policy(%d)\n" - , pmccobjpriv->duration, interval, mcc_policy_idx, pmccobjpriv->policy_index); + mccobjpriv->policy_index = 0; + RTW_INFO("[MCC] can't find table(%d), use default policy(%d)\n", + mcc_policy_idx, mccobjpriv->policy_index); } else - pmccobjpriv->policy_index = mcc_policy_idx; + mccobjpriv->policy_index = mcc_policy_idx; + + /* convert % to time */ + if (mcc_duration != 0) + rtw_hal_mcc_update_policy_table(padapter); RTW_INFO("[MCC] policy(%d): %d,%d,%d,%d,%d,%d\n" - , pmccobjpriv->policy_index - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX] - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX] - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX] - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX] - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX] - , mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]); + , mccobjpriv->policy_index + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX] + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX] + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX] + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_INTERVAL_IDX] + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX] + , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]); } -static void rtw_hal_config_mcc_role_setting(PADAPTER padapter) +static void rtw_hal_mcc_assign_tx_threshold(PADAPTER padapter) { - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); - struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv); - struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct wlan_network *cur_network = &(pmlmepriv->cur_network); - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta = NULL; struct registry_priv *preg = &padapter->registrypriv; - u8 policy_index = 0; - u8 mcc_duration = 0; - u8 mcc_interval = 0; - - policy_index = pmccobjpriv->policy_index; - mcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX] - - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX] - - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]; - mcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX]; + struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - /* GO/AP is 1nd order GC/STA is 2nd order */ switch (pmccadapriv->role) { case MCC_ROLE_STA: case MCC_ROLE_GC: - pmccadapriv->order = 1; - pmccadapriv->mcc_duration = mcc_duration; - switch (pmlmeext->cur_bwmode) { case CHANNEL_WIDTH_20: /* @@ -363,26 +346,9 @@ static void rtw_hal_config_mcc_role_setting(PADAPTER padapter) , FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode); break; } - - /* assign used mac to avoid affecting RA */ - pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID; - - psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); - if (psta) { - /* combine AP/GO macid and mgmt queue macid to bitmap */ - pmccadapriv->mcc_macid_bitmap = BIT(psta->mac_id) | BIT(pmccadapriv->mgmt_queue_macid); - } else { - RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter)); - rtw_warn_on(1); - } break; case MCC_ROLE_AP: case MCC_ROLE_GO: - pmccadapriv->order = 0; - /* total druation value equals interval */ - pmccadapriv->mcc_duration = mcc_interval - mcc_duration; - pmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */ - switch (pmlmeext->cur_bwmode) { case CHANNEL_WIDTH_20: pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration; @@ -399,31 +365,154 @@ static void rtw_hal_config_mcc_role_setting(PADAPTER padapter) , FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode); break; } + break; + default: + RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n" + , FUNC_ADPT_ARG(padapter), pmccadapriv->role); + break; + } +} + +static void rtw_hal_config_mcc_role_setting(PADAPTER padapter, u8 order) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv); + struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; + struct registry_priv *preg = &padapter->registrypriv; + _irqL irqL; + _list *phead =NULL, *plist = NULL; + u8 policy_index = 0; + u8 mcc_duration = 0; + u8 mcc_interval = 0; + u8 starting_ap_num = DEV_AP_STARTING_NUM(pdvobjpriv); + u8 ap_num = DEV_AP_NUM(pdvobjpriv); + policy_index = pmccobjpriv->policy_index; + mcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX] + - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX] + - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]; + mcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX]; - psta = rtw_get_bcmc_stainfo(padapter); + if (starting_ap_num == 0 && ap_num == 0) { + pmccadapriv->order = order; - if (psta != NULL) - pmccadapriv->mgmt_queue_macid = psta->mac_id; - else { + if (pmccadapriv->order == 0) { + /* setting is smiliar to GO/AP */ + /* pmccadapriv->mcc_duration = mcc_interval - mcc_duration;*/ pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID; - RTW_INFO(FUNC_ADPT_FMT":bcmc station is NULL, use macid %d\n" - , FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid); + } else if (pmccadapriv->order == 1) { + /* pmccadapriv->mcc_duration = mcc_duration; */ + pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID; + } else { + RTW_INFO("[MCC] not support >= 3 interface\n"); + rtw_warn_on(1); + } + + rtw_hal_mcc_assign_tx_threshold(padapter); + + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if (psta) { + /* combine AP/GO macid and mgmt queue macid to bitmap */ + pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid); + } else { + RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter)); + rtw_warn_on(1); + } + } else { + /* GO/AP is 1nd order GC/STA is 2nd order */ + switch (pmccadapriv->role) { + case MCC_ROLE_STA: + case MCC_ROLE_GC: + pmccadapriv->order = 1; + pmccadapriv->mcc_duration = mcc_duration; + + rtw_hal_mcc_assign_tx_threshold(padapter); + /* assign used mac to avoid affecting RA */ + pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID; + + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if (psta) { + /* combine AP/GO macid and mgmt queue macid to bitmap */ + pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid); + } else { + RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter)); + rtw_warn_on(1); + } + break; + case MCC_ROLE_AP: + case MCC_ROLE_GO: + pmccadapriv->order = 0; + /* total druation value equals interval */ + pmccadapriv->mcc_duration = mcc_interval - mcc_duration; + pmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */ + + rtw_hal_mcc_assign_tx_threshold(padapter); + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + pmccadapriv->mcc_macid_bitmap = 0; + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + pmccadapriv->mcc_macid_bitmap |= BIT(psta->cmn.mac_id); + } + + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + psta = rtw_get_bcmc_stainfo(padapter); + + if (psta != NULL) + pmccadapriv->mgmt_queue_macid = psta->cmn.mac_id; + else { + pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID; + RTW_INFO(FUNC_ADPT_FMT":bcmc station is NULL, use macid %d\n" + , FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid); + } + + /* combine client macid and mgmt queue macid to bitmap */ + pmccadapriv->mcc_macid_bitmap |= BIT(pmccadapriv->mgmt_queue_macid); + break; + default: + RTW_INFO("Unknown role\n"); + rtw_warn_on(1); + break; } - /* combine client macid and mgmt queue macid to bitmap */ - pmccadapriv->mcc_macid_bitmap = (0xff << 8) | BIT(pmccadapriv->mgmt_queue_macid); - break; - default: - RTW_INFO("Unknown role\n"); - rtw_warn_on(1); - break; } + /* setting Null data parameters */ + if (pmccadapriv->role == MCC_ROLE_STA) { + pmccadapriv->null_early = 3; + pmccadapriv->null_rty_num= 5; + } else if (pmccadapriv->role == MCC_ROLE_GC) { + pmccadapriv->null_early = 2; + pmccadapriv->null_rty_num= 5; + } else { + pmccadapriv->null_early = 0; + pmccadapriv->null_rty_num= 0; + } + + RTW_INFO("********* "FUNC_ADPT_FMT" *********\n", FUNC_ADPT_ARG(padapter)); + RTW_INFO("order:%d\n", pmccadapriv->order); + RTW_INFO("role:%d\n", pmccadapriv->role); + RTW_INFO("mcc duration:%d\n", pmccadapriv->mcc_duration); + RTW_INFO("null_early:%d\n", pmccadapriv->null_early); + RTW_INFO("null_rty_num:%d\n", pmccadapriv->null_rty_num); + RTW_INFO("mgmt queue macid:%d\n", pmccadapriv->mgmt_queue_macid); + RTW_INFO("bitmap:0x%02x\n", pmccadapriv->mcc_macid_bitmap); + RTW_INFO("target tx bytes:%d\n", pmccadapriv->mcc_target_tx_bytes_to_port); + RTW_INFO("**********************************\n"); + pmccobjpriv->iface[pmccadapriv->order] = padapter; - RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d, mcc duration:%d, target tx bytes:%d, mgmt queue macid:%d, bitmap:0x%02x\n" - , FUNC_ADPT_ARG(padapter), pmccadapriv->order, pmccadapriv->role, pmccadapriv->mcc_duration - , pmccadapriv->mcc_target_tx_bytes_to_port, pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap); + } static void rtw_hal_clear_mcc_macid(PADAPTER padapter) @@ -445,6 +534,400 @@ static void rtw_hal_clear_mcc_macid(PADAPTER padapter) break; } } + +static void rtw_hal_mcc_rqt_tsf(PADAPTER padapter, u64 *out_tsf) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + PADAPTER order0_iface = NULL; + PADAPTER order1_iface = NULL; + struct submit_ctx *tsf_req_sctx = NULL; + enum _hw_port tsfx = MAX_HW_PORT; + enum _hw_port tsfy = MAX_HW_PORT; + u8 cmd[H2C_MCC_RQT_TSF_LEN] = {0}; + + _enter_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL); + + order0_iface = mccobjpriv->iface[0]; + order1_iface = mccobjpriv->iface[1]; + + tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx; + rtw_sctx_init(tsf_req_sctx, MCC_EXPIRE_TIME); + mccobjpriv->mcc_tsf_req_sctx_order = 0; + tsfx = rtw_hal_get_port(order0_iface); + tsfy = rtw_hal_get_port(order1_iface); + + SET_H2CCMD_MCC_RQT_TSFX(cmd, tsfx); + SET_H2CCMD_MCC_RQT_TSFY(cmd, tsfy); + + rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_RQT_TSF, H2C_MCC_RQT_TSF_LEN, cmd); + + if (!rtw_sctx_wait(tsf_req_sctx, __func__)) + RTW_INFO(FUNC_ADPT_FMT": wait for mcc tsf req C2H time out\n", FUNC_ADPT_ARG(padapter)); + + if (tsf_req_sctx->status == RTW_SCTX_DONE_SUCCESS && out_tsf != NULL) { + out_tsf[0] = order0_iface->mcc_adapterpriv.tsf; + out_tsf[1] = order1_iface->mcc_adapterpriv.tsf; + } + + + _exit_critical_mutex(&mccobjpriv->mcc_tsf_req_mutex, NULL); +} + +static u8 rtw_hal_mcc_check_start_time_is_valid(PADAPTER padapter, u8 case_num, + u32 tsfdiff, s8 *upper_bound_0, s8 *lower_bound_0, s8 *upper_bound_1, s8 *lower_bound_1) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + u8 duration_0 = 0, duration_1 = 0; + s8 final_upper_bound = 0, final_lower_bound = 0; + u8 intersection = _FALSE; + u8 min_start_time = 5; + u8 max_start_time = 95; + + duration_0 = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration; + duration_1 = mccobjpriv->iface[1]->mcc_adapterpriv.mcc_duration; + + switch(case_num) { + case 1: + *upper_bound_0 = tsfdiff; + *lower_bound_0 = tsfdiff - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + case 2: + *upper_bound_0 = tsfdiff + 100; + *lower_bound_0 = tsfdiff + 100 - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + case 3: + *upper_bound_0 = tsfdiff + 50; + *lower_bound_0 = tsfdiff + 50 - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + case 4: + *upper_bound_0 = tsfdiff; + *lower_bound_0 = tsfdiff - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + case 5: + *upper_bound_0 = 200 - tsfdiff; + *lower_bound_0 = 200 - tsfdiff - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + case 6: + *upper_bound_0 = tsfdiff - 50; + *lower_bound_0 = tsfdiff - 50 - duration_1; + *upper_bound_1 = 150 - duration_1; + *lower_bound_1= 0; + break; + default: + RTW_ERR("[MCC] %s: error case number(%d\n)", __func__, case_num); + } + + + /* check Intersection or not */ + if ((*lower_bound_1 >= *upper_bound_0) || + (*lower_bound_0 >= *upper_bound_1)) + intersection = _FALSE; + else + intersection = _TRUE; + + if (intersection) { + if (*upper_bound_0 > *upper_bound_1) + final_upper_bound = *upper_bound_1; + else + final_upper_bound = *upper_bound_0; + + if (*lower_bound_0 > *lower_bound_1) + final_lower_bound = *lower_bound_0; + else + final_lower_bound = *lower_bound_1; + + mccobjpriv->start_time = (final_lower_bound + final_upper_bound) / 2; + + /* check start time less than 5ms, request by Pablo@SD1 */ + if (mccobjpriv->start_time <= min_start_time) { + mccobjpriv->start_time = 6; + if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) { + intersection = _FALSE; + goto exit; + } + } + + /* check start time less than 95ms */ + if (mccobjpriv->start_time >= max_start_time) { + mccobjpriv->start_time = 90; + if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) { + intersection = _FALSE; + goto exit; + } + } + } + +exit: + return intersection; +} + +static void rtw_hal_mcc_decide_duration(PADAPTER padapter) +{ + struct registry_priv *registry_par = &padapter->registrypriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + struct mcc_adapter_priv *mccadapriv = NULL, *mccadapriv_order0 = NULL, *mccadapriv_order1 = NULL; + _adapter *iface = NULL, *iface_order0 = NULL, *iface_order1 = NULL; + u8 duration = 0, i = 0, duration_time; + u8 mcc_interval = 150; + + iface_order0 = mccobjpriv->iface[0]; + iface_order1 = mccobjpriv->iface[1]; + mccadapriv_order0 = &iface_order0->mcc_adapterpriv; + mccadapriv_order1 = &iface_order1->mcc_adapterpriv; + + if (mccobjpriv->duration == 0) { + /* default */ + duration = 30;/*(%)*/ + RTW_INFO("%s: mccobjpriv->duration=0, use default value(%d)\n", + __FUNCTION__, duration); + } else { + duration = mccobjpriv->duration;/*(%)*/ + RTW_INFO("%s: mccobjpriv->duration=%d\n", + __FUNCTION__, duration); + } + + mccobjpriv->interval = mcc_interval; + mccobjpriv->mcc_stop_threshold = 2000 * 4 / 300 - 6; + /* convert % to ms, for primary adapter */ + duration_time = mccobjpriv->interval * duration / 100; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + + if (!iface) + continue; + + mccadapriv = &iface->mcc_adapterpriv; + if (mccadapriv->role == MCC_ROLE_MAX) + continue; + + if (is_primary_adapter(iface)) + mccadapriv->mcc_duration = duration_time; + else + mccadapriv->mcc_duration = mccobjpriv->interval - duration_time; + } + + RTW_INFO("[MCC]" FUNC_ADPT_FMT " order 0 duration=%d\n", FUNC_ADPT_ARG(iface_order0), mccadapriv_order0->mcc_duration); + RTW_INFO("[MCC]" FUNC_ADPT_FMT " order 1 duration=%d\n", FUNC_ADPT_ARG(iface_order1), mccadapriv_order1->mcc_duration); +} + +static u8 rtw_hal_mcc_update_timing_parameters(PADAPTER padapter, u8 force_update) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u8 need_update = _FALSE; + u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj); + u8 ap_num = DEV_AP_NUM(dvobj); + + + /* for STA+STA, modify policy table */ + if (starting_ap_num == 0 && ap_num == 0) { + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + struct mcc_adapter_priv *pmccadapriv = NULL; + _adapter *iface = NULL; + u64 tsf[MAX_MCC_NUM] = {0}; + u64 tsf0 = 0, tsf1 = 0; + u32 beaconperiod_0 = 0, beaconperiod_1 = 0, tsfdiff = 0; + s8 upper_bound_0 = 0, lower_bound_0 = 0; + s8 upper_bound_1 = 0, lower_bound_1 = 0; + u8 valid = _FALSE; + u8 case_num = 1; + u8 i = 0; + + /* query TSF */ + rtw_hal_mcc_rqt_tsf(padapter, tsf); + + /* selecet policy table according TSF diff */ + tsf0 = tsf[0]; + beaconperiod_0 = pmccobjpriv->iface[0]->mlmepriv.cur_network.network.Configuration.BeaconPeriod; + tsf0 = rtw_modular64(tsf0, (beaconperiod_0 * TU)); + + tsf1 = tsf[1]; + beaconperiod_1 = pmccobjpriv->iface[1]->mlmepriv.cur_network.network.Configuration.BeaconPeriod; + tsf1 = rtw_modular64(tsf1, (beaconperiod_1 * TU)); + + if (tsf0 > tsf1) + tsfdiff = tsf0- tsf1; + else + tsfdiff = (tsf0 + beaconperiod_0 * TU) - tsf1; + + /* convert to ms */ + tsfdiff = (tsfdiff / TU); + + /* force update*/ + if (force_update) { + RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n", + pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf); + RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1); + RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n", + __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD); + pmccobjpriv->last_tsfdiff = tsfdiff; + need_update = _TRUE; + } else { + if (pmccobjpriv->last_tsfdiff > tsfdiff) { + /* last tsfdiff - current tsfdiff > THRESHOLD, update parameters */ + if (pmccobjpriv->last_tsfdiff > (tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) { + RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n", + pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf); + RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1); + RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n", + __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD); + + pmccobjpriv->last_tsfdiff = tsfdiff; + need_update = _TRUE; + } else { + need_update = _FALSE; + } + } else if (tsfdiff > pmccobjpriv->last_tsfdiff){ + /* current tsfdiff - last tsfdiff > THRESHOLD, update parameters */ + if (tsfdiff > (pmccobjpriv->last_tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) { + RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n", + pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf); + RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1); + RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n", + __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD); + + pmccobjpriv->last_tsfdiff = tsfdiff; + need_update = _TRUE; + } else { + need_update = _FALSE; + } + } else { + need_update = _FALSE; + } + } + + if (need_update == _FALSE) + goto exit; + + rtw_hal_mcc_decide_duration(padapter); + + if (tsfdiff <= 50) { + + /* RX TBTT 0 */ + case_num = 1; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + /* RX TBTT 1 */ + case_num = 2; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + /* RX TBTT 2 */ + case_num = 3; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + if (valid == _FALSE) { + RTW_INFO("[MCC] do not find fit start time\n"); + RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n", + tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval); + + } + + } else { + + /* RX TBTT 0 */ + case_num = 4; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + + /* RX TBTT 1 */ + case_num = 5; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + + /* RX TBTT 2 */ + case_num = 6; + valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff, + &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1); + + if (valid) + goto valid_result; + + if (valid == _FALSE) { + RTW_INFO("[MCC] do not find fit start time\n"); + RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n", + tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval); + } + } + + + + valid_result: + RTW_INFO("********************\n"); + RTW_INFO("%s: case_num:%d, start time:%d\n", + __func__, case_num, pmccobjpriv->start_time); + RTW_INFO("%s: upper_bound_0:%d, lower_bound_0:%d\n", + __func__, upper_bound_0, lower_bound_0); + RTW_INFO("%s: upper_bound_1:%d, lower_bound_1:%d\n", + __func__, upper_bound_1, lower_bound_1); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface == NULL) + continue; + + pmccadapriv = &iface->mcc_adapterpriv; + pmccadapriv = &iface->mcc_adapterpriv; + if (pmccadapriv->role == MCC_ROLE_MAX) + continue; +#if 0 + if (pmccadapriv->order == 0) { + pmccadapriv->mcc_duration = mcc_duration; + } else if (pmccadapriv->order == 1) { + pmccadapriv->mcc_duration = mcc_interval - mcc_duration; + } else { + RTW_INFO("[MCC] not support >= 3 interface\n"); + rtw_warn_on(1); + } +#endif + RTW_INFO("********************\n"); + RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d\n", + FUNC_ADPT_ARG(iface), pmccadapriv->order, pmccadapriv->role); + RTW_INFO(FUNC_ADPT_FMT": mcc duration:%d, target tx bytes:%d\n", + FUNC_ADPT_ARG(iface), pmccadapriv->mcc_duration, pmccadapriv->mcc_target_tx_bytes_to_port); + RTW_INFO(FUNC_ADPT_FMT": mgmt queue macid:%d, bitmap:0x%02x\n", + FUNC_ADPT_ARG(iface), pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap); + RTW_INFO("********************\n"); + } + + } +exit: + return need_update; +} + static u8 rtw_hal_decide_mcc_role(PADAPTER padapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); @@ -453,6 +936,7 @@ static u8 rtw_hal_decide_mcc_role(PADAPTER padapter) struct wifidirect_info *pwdinfo = NULL; struct mlme_priv *pmlmepriv = NULL; u8 ret = _SUCCESS, i = 0; + u8 order = 1; for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; @@ -460,6 +944,7 @@ static u8 rtw_hal_decide_mcc_role(PADAPTER padapter) continue; pmccadapriv = &iface->mcc_adapterpriv; + pwdinfo = &iface->wdinfo; if (MLME_IS_GO(iface)) pmccadapriv->role = MCC_ROLE_GO; @@ -467,32 +952,36 @@ static u8 rtw_hal_decide_mcc_role(PADAPTER padapter) pmccadapriv->role = MCC_ROLE_AP; else if (MLME_IS_GC(iface)) pmccadapriv->role = MCC_ROLE_GC; - else if (MLME_IS_STA(iface)) - pmccadapriv->role = MCC_ROLE_STA; - else { - pwdinfo = &iface->wdinfo; - pmlmepriv = &iface->mlmepriv; - - RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(iface)); - RTW_INFO("Unknown:P2P state:%d, mlme state:0x%2x, mlmext info state:0x%02x\n", - pwdinfo->role, pmlmepriv->fw_state, iface->mlmeextpriv.mlmext_info.state); - rtw_warn_on(1); - ret = _FAIL; - goto exit; + else if (MLME_IS_STA(iface)) { + if (MLME_IS_LINKING(iface) || MLME_IS_ASOC(iface)) + pmccadapriv->role = MCC_ROLE_STA; + else { + /* bypass non-linked/non-linking interface */ + RTW_INFO(FUNC_ADPT_FMT" mlme state:0x%2x\n", + FUNC_ADPT_ARG(iface), MLME_STATE(iface)); + continue; + } + } else { + /* bypass non-linked/non-linking interface */ + RTW_INFO(FUNC_ADPT_FMT" P2P Role:%d, mlme state:0x%2x\n", + FUNC_ADPT_ARG(iface), pwdinfo->role, MLME_STATE(iface)); + continue; } - if (ret == _SUCCESS) - rtw_hal_config_mcc_role_setting(iface); + if (padapter == iface) { + /* current adapter is order 0 */ + rtw_hal_config_mcc_role_setting(iface, 0); + } else { + rtw_hal_config_mcc_role_setting(iface, order); + order ++; + } } + rtw_hal_mcc_update_timing_parameters(padapter, _TRUE); exit: return ret; } -static void rtw_hal_init_mcc_parameter(PADAPTER padapter) -{ -} - static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength) { u8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; @@ -514,9 +1003,69 @@ static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength) *pLength = 22; } +/* avoid wrong information for power limit */ +void rtw_hal_mcc_upadate_chnl_bw(_adapter *padapter, u8 ch, u8 ch_offset, u8 bw, u8 print) +{ + + u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); + u8 cch_160, cch_80, cch_40, cch_20; + + center_ch = rtw_get_center_ch(ch, bw, ch_offset); + + if (bw == CHANNEL_WIDTH_80) { + if (center_ch > ch) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER; + else if (center_ch < ch) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER; + else + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + + /* set Channel */ + /* saved channel/bw info */ + rtw_set_oper_ch(padapter, ch); + rtw_set_oper_bw(padapter, bw); + rtw_set_oper_choffset(padapter, ch_offset); + + cch_80 = bw == CHANNEL_WIDTH_80 ? center_ch : 0; + cch_40 = bw == CHANNEL_WIDTH_40 ? center_ch : 0; + cch_20 = bw == CHANNEL_WIDTH_20 ? center_ch : 0; + + if (cch_80 != 0) + cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, chnl_offset80); + if (cch_40 != 0) + cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, ch_offset); + + + hal->cch_80 = cch_80; + hal->cch_40 = cch_40; + hal->cch_20 = cch_20; + hal->current_channel = center_ch; + hal->CurrentCenterFrequencyIndex1 = center_ch; + hal->current_channel_bw = bw; + hal->nCur40MhzPrimeSC = ch_offset; + hal->nCur80MhzPrimeSC = chnl_offset80; + hal->current_band_type = ch > 14 ? BAND_ON_5G:BAND_ON_2_4G; + + if (print) { + RTW_INFO(FUNC_ADPT_FMT" cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u), band:%s\n" + , FUNC_ADPT_ARG(padapter), center_ch, ch_width_str(bw) + , ch_offset, chnl_offset80 + , hal->cch_80, hal->cch_40, hal->cch_20 + , band_str(hal->current_band_type)); + } +} + +#ifdef DBG_RSVD_PAGE_CFG +#define RSVD_PAGE_CFG(ops, v1, v2, v3) \ + RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n", \ + ops, v1, v2, v3) +#endif + u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, - u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len, - RSVDPAGE_LOC *rsvd_page_loc) + u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num) { u32 len = 0; _adapter *iface = NULL; @@ -524,8 +1073,21 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); struct mlme_ext_info *pmlmeinfo = NULL; struct mlme_ext_priv *pmlmeext = NULL; - u8 ret = _SUCCESS, i = 0, order = 0, CurtPktPageNum = 0; - u8 bssid[ETH_ALEN] = {0}; + struct hal_com_data *hal = GET_HAL_DATA(adapter); + struct mcc_adapter_priv *mccadapriv = NULL; + u8 ret = _SUCCESS, i = 0, j =0, order = 0, CurtPktPageNum = 0; + u8 *start = NULL; + u8 path = RF_PATH_A; + + if (page_num) { +#ifdef CONFIG_MCC_MODE_V2 + if (!hal->RegIQKFWOffload) + RTW_WARN("[MCC] must enable FW IQK for New IC\n"); +#endif /* CONFIG_MCC_MODE_V2 */ + /* Null data(interface number) + power index(interface number) + 1 */ + *total_page_num += (2 * dvobj->iface_nums + 3); + goto exit; + } /* check proccess mcc start setting */ if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) { @@ -538,34 +1100,37 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, if (iface == NULL) continue; - order = iface->mcc_adapterpriv.order; - dvobj->mcc_objpriv.mcc_loc_rsvd_paga[order] = *page_num; + mccadapriv = &iface->mcc_adapterpriv; + if (mccadapriv->role == MCC_ROLE_MAX) + continue; + + order = mccadapriv->order; + pmccobjpriv->mcc_loc_rsvd_paga[order] = *total_page_num; - switch (iface->mcc_adapterpriv.role) { + switch (mccadapriv->role) { case MCC_ROLE_STA: case MCC_ROLE_GC: /* Build NULL DATA */ RTW_INFO("LocNull(order:%d): %d\n" - , order, dvobj->mcc_objpriv.mcc_loc_rsvd_paga[order]); + , order, pmccobjpriv->mcc_loc_rsvd_paga[order]); len = 0; - pmlmeext = &iface->mlmeextpriv; - pmlmeinfo = &pmlmeext->mlmext_info; - _rtw_memcpy(bssid, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); rtw_hal_construct_NullFunctionData(iface - , &pframe[*index], &len, bssid, _FALSE, 0, 0, _FALSE); + , &pframe[*index], &len, _FALSE, 0, 0, _FALSE); rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc], len, _FALSE, _FALSE, _FALSE); CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size); - *page_num += CurtPktPageNum; + *total_page_num += CurtPktPageNum; *index += (CurtPktPageNum * page_size); - *total_pkt_len = *index + len; + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("LocNull", CurtPktPageNum, *total_page_num, *index); + #endif break; case MCC_ROLE_AP: /* Bulid CTS */ RTW_INFO("LocCTS(order:%d): %d\n" - , order, dvobj->mcc_objpriv.mcc_loc_rsvd_paga[order]); + , order, pmccobjpriv->mcc_loc_rsvd_paga[order]); len = 0; rtw_hal_construct_CTS(iface, &pframe[*index], &len); @@ -573,15 +1138,315 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index, len, _FALSE, _FALSE, _FALSE); CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size); - *page_num += CurtPktPageNum; + *total_page_num += CurtPktPageNum; *index += (CurtPktPageNum * page_size); - *total_pkt_len = *index + len; + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("LocCTS", CurtPktPageNum, *total_page_num, *index); + #endif break; case MCC_ROLE_GO: /* To DO */ break; + default: + RTW_INFO(FUNC_ADPT_FMT": unknown role = %d\n" + , FUNC_ADPT_ARG(iface), mccadapriv->role); + break; } } + + for (i = 0; i < MAX_MCC_NUM; i++) { + u8 center_ch = 0, ch = 0, bw = 0, bw_offset = 0; + u8 power_index = 0; + u8 rate_array_sz = 0; + u8 *rates = NULL; + u8 rate = 0; + u8 shift = 0; + u32 power_index_4bytes = 0; + u8 total_rate = 0; + u8 *total_rate_offset = NULL; + + iface = pmccobjpriv->iface[i]; + pmlmeext = &iface->mlmeextpriv; + ch = pmlmeext->cur_channel; + bw = pmlmeext->cur_bwmode; + bw_offset = pmlmeext->cur_ch_offset; + center_ch = rtw_get_center_ch(ch, bw, bw_offset); + rtw_hal_mcc_upadate_chnl_bw(iface, ch, bw_offset, bw, _TRUE); + + start = &pframe[*index - tx_desc]; + _rtw_memset(start, 0, page_size); + pmccobjpriv->mcc_pwr_idx_rsvd_page[i] = *total_page_num; + RTW_INFO(ADPT_FMT" order:%d, pwr_idx_rsvd_page location[%d]: %d\n", + ADPT_ARG(iface), mccadapriv->order, + i, pmccobjpriv->mcc_pwr_idx_rsvd_page[i]); + + total_rate_offset = start; + + for (path = RF_PATH_A; path < hal->NumTotalRFPath; ++path) { + total_rate = 0; + /* PATH A for 0~63 byte, PATH B for 64~127 byte*/ + if (path == RF_PATH_A) + start = total_rate_offset + 1; + else if (path == RF_PATH_B) + start = total_rate_offset + 64; + else { + RTW_INFO("[MCC] %s: unknow RF PATH(%d)\n", __func__, path); + break; + } + + /* CCK */ + if (ch <= 14) { + rate_array_sz = rates_by_sections[CCK].rate_num; + rates = rates_by_sections[CCK].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + } + + *start = power_index; + start++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + + } + } + + /* OFDM */ + rate_array_sz = rates_by_sections[OFDM].rate_num; + rates = rates_by_sections[OFDM].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + + } + + *start = power_index; + start++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + } + + /* HT_MCS0_MCS7 */ + rate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num; + rates = rates_by_sections[HT_MCS0_MCS7].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + + } + + *start = power_index; + start++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + } + + /* HT_MCS8_MCS15 */ + rate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num; + rates = rates_by_sections[HT_MCS8_MCS15].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + } + + *start = power_index; + start++; + + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + } + + /* VHT_1SSMCS0_1SSMCS9 */ + rate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num; + rates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:0x%02x\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + } + *start = power_index; + start++; + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + } + + /* VHT_2SSMCS0_2SSMCS9 */ + rate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num; + rates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates; + for (j = 0; j < rate_array_sz; ++j) { + power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL); + rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]); + + shift = rate % 4; + if (shift == 0) { + *start = rate; + start++; + total_rate++; + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + #endif + } + *start = power_index; + start++; + #ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n", + ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw), + center_ch, MGN_RATE_STR(rates[j]), power_index); + + shift = rate % 4; + power_index_4bytes |= ((power_index & 0xff) << (shift * 8)); + if (shift == 3) { + rate = rate - 3; + RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate); + power_index_4bytes = 0; + total_rate++; + } + #endif + } + + } + /* total rate store in offset 0 */ + *total_rate_offset = total_rate; + +#ifdef DBG_PWR_IDX_RSVD_PAGE + RTW_INFO("total_rate=%d\n", total_rate); + RTW_INFO(" ======================="ADPT_FMT"===========================\n", ADPT_ARG(iface)); + RTW_INFO_DUMP("\n", total_rate_offset, 128); + RTW_INFO(" ==================================================\n"); +#endif + + CurtPktPageNum = 1; + *total_page_num += CurtPktPageNum; + *index += (CurtPktPageNum * page_size); + #ifdef DBG_RSVD_PAGE_CFG + RSVD_PAGE_CFG("mcc_pwr_idx_rsvd_page", CurtPktPageNum, *total_page_num, *index); + #endif + } + exit: return ret; } @@ -605,12 +1470,17 @@ static void rtw_hal_set_fw_mcc_rsvd_page(PADAPTER padapter) rtw_hal_set_hwreg(port0_iface, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus)); /* Re-Download beacon */ - for (i = 0; i < dvobj->iface_nums; i++) { + for (i = 0; i < MAX_MCC_NUM; i++) { iface = pmccobjpriv->iface[i]; + if (iface == NULL) + continue; + pmccadapriv = &iface->mcc_adapterpriv; + if (pmccadapriv->role == MCC_ROLE_AP - || pmccadapriv->role == MCC_ROLE_GO) + || pmccadapriv->role == MCC_ROLE_GO) { tx_beacon_hdl(iface, NULL); + } } } @@ -618,23 +1488,17 @@ static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter) { u8 cmd[H2C_MCC_LOCATION_LEN] = {0}, i = 0, order = 0; _adapter *iface = NULL; + PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter); struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(cmd, _TRUE); + SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(cmd, hal->NumTotalRFPath); + for (order = 0; order < MAX_MCC_NUM; order++) { + iface = pmccobjpriv->iface[i]; - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (iface == NULL) - continue; - - order = iface->mcc_adapterpriv.order; - if (order >= H2C_MCC_LOCATION_LEN) { - RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n" - , FUNC_ADPT_ARG(padapter), order); - continue; - } - - SET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), (pmccobjpriv->mcc_loc_rsvd_paga[order])); + SET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), pmccobjpriv->mcc_loc_rsvd_paga[order]); + SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC ((cmd + order), pmccobjpriv->mcc_pwr_idx_rsvd_page[order]); } #ifdef CONFIG_MCC_MODE_DEBUG @@ -649,44 +1513,78 @@ static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter) rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_LOCATION, H2C_MCC_LOCATION_LEN, cmd); } -static void rtw_hal_set_mcc_noa_cmd(PADAPTER padapter) +static void rtw_hal_set_mcc_time_setting_cmd(PADAPTER padapter) { struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); - u8 cmd[H2C_MCC_NOA_PARAM_LEN] = {0}; - u8 policy_idx = pmccobjpriv->policy_index; - u8 noa_fw_eable = 1; - u8 noa_tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX]; - u8 noa_start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX]; - u8 noa_interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX]; - u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX]; - u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX]; + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0}; + u8 fw_eable = 1; u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME; - u8 i = 0; + u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj); + u8 ap_num = DEV_AP_NUM(dvobj); - /* FW set NOA enable */ - SET_H2CCMD_MCC_NOA_FW_EN(cmd, noa_fw_eable); - /* TSF Sync offset */ - SET_H2CCMD_MCC_NOA_TSF_SYNC_OFFSET(cmd, noa_tsf_sync_offset); - /* NoA start time offset */ - SET_H2CCMD_MCC_NOA_START_TIME(cmd, (noa_start_time_offset + guard_offset0)); - /* NoA interval */ - SET_H2CCMD_MCC_NOA_INTERVAL(cmd, noa_interval); - /* Early time to inform driver by C2H before switch channel */ - SET_H2CCMD_MCC_EARLY_TIME(cmd, swchannel_early_time); + if (starting_ap_num == 0 && ap_num == 0) + /* For STA+GC/STA+STA, TSF of GC/STA does not need to sync from TSF of other STA/GC */ + fw_eable = 0; + else + /* Only for STA+GO/STA+AP, TSF of AP/GO need to sync from TSF of STA */ + fw_eable = 1; + + if (fw_eable == 1) { + PADAPTER order0_iface = NULL; + PADAPTER order1_iface = NULL; + u8 policy_idx = mccobjpriv->policy_index; + u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX]; + u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX]; + u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX]; + u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX]; + u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX]; + enum _hw_port tsf_bsae_port = MAX_HW_PORT; + enum _hw_port tsf_sync_port = MAX_HW_PORT; + order0_iface = mccobjpriv->iface[0]; + order1_iface = mccobjpriv->iface[1]; + + tsf_bsae_port = rtw_hal_get_port(order1_iface); + tsf_sync_port = rtw_hal_get_port(order0_iface); + + /* FW set enable */ + SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, fw_eable); + /* TSF Sync offset */ + SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset); + /* start time offset */ + SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0)); + /* interval */ + SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval); + /* Early time to inform driver by C2H before switch channel */ + SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time); + /* Port0 sync from Port1, not support multi-port */ + SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port); + SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port); + } else { + /* start time offset */ + SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, mccobjpriv->start_time); + /* interval */ + SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, mccobjpriv->interval); + /* Early time to inform driver by C2H before switch channel */ + SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time); + } #ifdef CONFIG_MCC_MODE_DEBUG - RTW_INFO("=========================\n"); - RTW_INFO("NoA:\n"); - for (i = 0; i < H2C_MCC_NOA_PARAM_LEN; i++) - pr_dbg("0x%x ", cmd[i]); - pr_dbg("\n"); - RTW_INFO("=========================\n"); + { + u8 i = 0; + + RTW_INFO("=========================\n"); + RTW_INFO("NoA:\n"); + for (i = 0; i < H2C_MCC_TIME_SETTING_LEN; i++) + pr_dbg("0x%x ", cmd[i]); + pr_dbg("\n"); + RTW_INFO("=========================\n"); + } #endif /* CONFIG_MCC_MODE_DEBUG */ - rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_NOA_PARAM, H2C_MCC_NOA_PARAM_LEN, cmd); + rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd); } static void rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter) @@ -701,7 +1599,7 @@ static void rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter) u8 rf_path_idx = 0, last_order = MAX_MCC_NUM - 1, last_rf_path_index = total_rf_path - 1; /* by order, last order & last_rf_path_index must set ready bit = 1 */ - for (i = 0; i < dvobj->iface_nums; i++) { + for (i = 0; i < MAX_MCC_NUM; i++) { iface = pmccobjpriv->iface[i]; if (iface == NULL) continue; @@ -783,6 +1681,9 @@ static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter) continue; pmccadapriv = &iface->mcc_adapterpriv; + if (pmccadapriv->role == MCC_ROLE_MAX) + continue; + order = pmccadapriv->order; bitmap = pmccadapriv->mcc_macid_bitmap; @@ -799,20 +1700,168 @@ static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter) RTW_INFO("=========================\n"); RTW_INFO("MACID BITMAP: "); for (i = 0; i < H2C_MCC_MACID_BITMAP_LEN; i++) - pr_dbg("0x%x ", cmd[i]); - pr_dbg("\n"); + printk("0x%x ", cmd[i]); + printk("\n"); RTW_INFO("=========================\n"); #endif /* CONFIG_MCC_MODE_DEBUG */ rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_MACID_BITMAP, H2C_MCC_MACID_BITMAP_LEN, cmd); } -static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop) +#ifdef CONFIG_MCC_MODE_V2 +static u8 get_pri_ch_idx_by_adapter(u8 center_ch, u8 channel, u8 bw, u8 ch_offset40) +{ + u8 pri_ch_idx = 0, chnl_offset80 = 0; + + if (bw == CHANNEL_WIDTH_80) { + if (center_ch > channel) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER; + else if (center_ch < channel) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER; + else + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + + if (bw == CHANNEL_WIDTH_80) { + /* primary channel is at lower subband of 80MHz & 40MHz */ + if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER)) + pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ; + /* primary channel is at lower subband of 80MHz & upper subband of 40MHz */ + else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER)) + pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ; + /* primary channel is at upper subband of 80MHz & lower subband of 40MHz */ + else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER)) + pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ; + /* primary channel is at upper subband of 80MHz & upper subband of 40MHz */ + else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER)) + pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ; + else { + if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER) + pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ; + else if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER) + pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ; + else + RTW_INFO("SCMapping: DONOT CARE Mode Setting\n"); + } + } else if (bw == CHANNEL_WIDTH_40) { + /* primary channel is at upper subband of 40MHz */ + if (ch_offset40== HAL_PRIME_CHNL_OFFSET_UPPER) + pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ; + /* primary channel is at lower subband of 40MHz */ + else if (ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) + pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ; + else + RTW_INFO("SCMapping: DONOT CARE Mode Setting\n"); + } + + return pri_ch_idx; +} + +static void rtw_hal_set_mcc_ctrl_cmd_v2(PADAPTER padapter, u8 stop) +{ + u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0; + u8 order = 0, totalnum = 0; + u8 center_ch = 0, pri_ch_idx = 0, bw = 0; + u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0; + u8 dis_sw_retry = 0, null_early_time=2, tsfx = 0, update_parm = 0; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + struct mcc_adapter_priv *mccadapriv = NULL; + struct mlme_ext_priv *pmlmeext = NULL; + struct mlme_ext_info *pmlmeinfo = NULL; + _adapter *iface = NULL; + + RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop); + + for (i = 0; i < MAX_MCC_NUM; i++) { + iface = pmccobjpriv->iface[i]; + if (iface == NULL) + continue; + + if (stop) { + if (iface != padapter) + continue; + } + + mccadapriv = &iface->mcc_adapterpriv; + order = mccadapriv->order; + + if (!stop) + totalnum = MAX_MCC_NUM; + else + totalnum = 0xff; /* 0xff means stop */ + + pmlmeext = &iface->mlmeextpriv; + center_ch = rtw_get_center_ch(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); + pri_ch_idx = get_pri_ch_idx_by_adapter(center_ch, pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); + bw = pmlmeext->cur_bwmode; + duration = mccadapriv->mcc_duration; + role = mccadapriv->role; + + incurch = _FALSE; + dis_sw_retry = _TRUE; + + /* STA/GC TX NULL data to inform AP/GC for ps mode */ + switch (role) { + case MCC_ROLE_GO: + case MCC_ROLE_AP: + distxnull = MCC_DISABLE_TX_NULL; + break; + case MCC_ROLE_GC: + set_channel_bwmode(iface, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + distxnull = MCC_ENABLE_TX_NULL; + break; + case MCC_ROLE_STA: + distxnull = MCC_ENABLE_TX_NULL; + break; + } + + null_early_time = mccadapriv->null_early; + + c2hrpt = MCC_C2H_REPORT_ALL_STATUS; + tsfx = rtw_hal_get_port(iface); + update_parm = 0; + + SET_H2CCMD_MCC_CTRL_V2_ORDER(cmd, order); + SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(cmd, totalnum); + SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(cmd, center_ch); + SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(cmd, pri_ch_idx); + SET_H2CCMD_MCC_CTRL_V2_BW(cmd, bw); + SET_H2CCMD_MCC_CTRL_V2_DURATION(cmd, duration); + SET_H2CCMD_MCC_CTRL_V2_ROLE(cmd, role); + SET_H2CCMD_MCC_CTRL_V2_INCURCH(cmd, incurch); + SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(cmd, dis_sw_retry); + SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(cmd, distxnull); + SET_H2CCMD_MCC_CTRL_V2_C2HRPT(cmd, c2hrpt); + SET_H2CCMD_MCC_CTRL_V2_TSFX(cmd, tsfx); + SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(cmd, null_early_time); + SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(cmd, update_parm); + +#ifdef CONFIG_MCC_MODE_DEBUG + RTW_INFO("=========================\n"); + RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface)); + RTW_INFO("cmd[0]:0x%02x\n", cmd[0]); + RTW_INFO("cmd[1]:0x%02x\n", cmd[1]); + RTW_INFO("cmd[2]:0x%02x\n", cmd[2]); + RTW_INFO("cmd[3]:0x%02x\n", cmd[3]); + RTW_INFO("cmd[4]:0x%02x\n", cmd[4]); + RTW_INFO("cmd[5]:0x%02x\n", cmd[5]); + RTW_INFO("cmd[6]:0x%02x\n", cmd[6]); + RTW_INFO("=========================\n"); +#endif /* CONFIG_MCC_MODE_DEBUG */ + + rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL_V2, H2C_MCC_CTRL_LEN, cmd); + } +} + +#else +static void rtw_hal_set_mcc_ctrl_cmd_v1(PADAPTER padapter, u8 stop) { u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0; u8 order = 0, totalnum = 0, chidx = 0, bw = 0, bw40sc = 0, bw80sc = 0; u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0, chscan = 0; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + struct mcc_adapter_priv *mccadapriv = NULL; struct mlme_ext_priv *pmlmeext = NULL; struct mlme_ext_info *pmlmeinfo = NULL; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); @@ -820,7 +1869,7 @@ static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop) RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop); - for (i = 0; i < dvobj->iface_nums; i++) { + for (i = 0; i < MAX_MCC_NUM; i++) { iface = pmccobjpriv->iface[i]; if (iface == NULL) continue; @@ -830,10 +1879,11 @@ static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop) continue; } + mccadapriv = &iface->mcc_adapterpriv; + order = mccadapriv->order; - order = iface->mcc_adapterpriv.order; if (!stop) - totalnum = dvobj->iface_nums; + totalnum = MAX_MCC_NUM; else totalnum = 0xff; /* 0xff means stop */ @@ -855,8 +1905,8 @@ static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop) } else bw80sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - duration = iface->mcc_adapterpriv.mcc_duration; - role = iface->mcc_adapterpriv.role; + duration = mccadapriv->mcc_duration; + role = mccadapriv->role; incurch = _FALSE; @@ -910,10 +1960,76 @@ static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop) rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL, H2C_MCC_CTRL_LEN, cmd); } } +#endif -static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status) +static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop) { + #ifdef CONFIG_MCC_MODE_V2 + /* new cmd 0x17 */ + rtw_hal_set_mcc_ctrl_cmd_v2(padapter, stop); + #else + /* old cmd 0x18 */ + rtw_hal_set_mcc_ctrl_cmd_v1(padapter, stop); + #endif +} + +static u8 check_mcc_support(PADAPTER adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 sta_linking_num = DEV_STA_LG_NUM(dvobj); + u8 sta_linked_num = DEV_STA_LD_NUM(dvobj); + u8 starting_ap_num = DEV_AP_STARTING_NUM(dvobj); + u8 ap_num = DEV_AP_NUM(dvobj); u8 ret = _SUCCESS; + + /* case for linking sta + linked sta */ + if ((sta_linking_num + sta_linked_num) != MAX_MCC_NUM) { + ret = _FAIL; + goto exit; + } + + /* case for starting AP + linked sta */ + if ((starting_ap_num + sta_linked_num) != MAX_MCC_NUM) { + ret = _FAIL; + goto exit; + } + + /* case for linking sta + started AP */ + if ((sta_linking_num + ap_num) != MAX_MCC_NUM) { + ret = _FAIL; + goto exit; + } + + /* case for starting AP + started AP */ + if ((starting_ap_num + ap_num) != MAX_MCC_NUM) { + ret = _FAIL; + goto exit; + } + +exit: + return ret; +} + +static void rtw_hal_mcc_start_prehdl(PADAPTER padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + _adapter *iface = NULL; + struct mcc_adapter_priv *mccadapriv = NULL; + u8 i = 1; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface == NULL) + continue; + + mccadapriv = &iface->mcc_adapterpriv; + mccadapriv->role = MCC_ROLE_MAX; + } +} + +static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status) +{ + u8 ret = _SUCCESS, enable_tsf_auto_sync = _FALSE; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); @@ -923,12 +2039,15 @@ static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status) LeaveAllPowerSaveModeDirect(padapter); } - if (dvobj->iface_nums > MAX_MCC_NUM) { - RTW_INFO("%s: current iface num(%d) > MAX_MCC_NUM(%d)\n", __func__, dvobj->iface_nums, MAX_MCC_NUM); + if (check_mcc_support(padapter)) { + RTW_INFO("%s: check_mcc_support fail\n", __func__); + dump_dvobj_mi_status(RTW_DBGDUMP, __func__, padapter); ret = _FAIL; goto exit; } + rtw_hal_mcc_start_prehdl(padapter); + /* configure mcc switch channel setting */ rtw_hal_config_mcc_switch_channel_setting(padapter); @@ -947,15 +2066,25 @@ static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status) rtw_hal_set_mcc_rsvdpage_cmd(padapter); } - /* configure NoA setting */ - rtw_hal_set_mcc_noa_cmd(padapter); + /* configure time setting */ + rtw_hal_set_mcc_time_setting_cmd(padapter); +#ifndef CONFIG_MCC_MODE_V2 /* IQK value offload */ rtw_hal_set_mcc_IQK_offload_cmd(padapter); +#endif /* set mac id to fw */ rtw_hal_set_mcc_macid_cmd(padapter); + if (dvobj->p0_tsf.sync_port != MAX_HW_PORT ) { + /* disable tsf auto sync */ + RTW_INFO("[MCC] disable HW TSF sync\n"); + rtw_hal_set_hwreg(padapter, HW_VAR_TSF_AUTO_SYNC, &enable_tsf_auto_sync); + } else { + RTW_INFO("[MCC] already disable HW TSF sync\n"); + } + /* set mcc parameter */ rtw_hal_set_mcc_ctrl_cmd(padapter, _FALSE); @@ -966,7 +2095,9 @@ static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status) static void rtw_hal_set_mcc_stop_setting(PADAPTER padapter, u8 status) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &dvobj->mcc_objpriv; _adapter *iface = NULL; + struct mcc_adapter_priv *mccadapriv = NULL; u8 i = 0; /* * when adapter disconnect, stop mcc mod @@ -976,10 +2107,13 @@ static void rtw_hal_set_mcc_stop_setting(PADAPTER padapter, u8 status) switch (status) { default: /* let fw switch to other interface channel */ - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; + for (i = 0; i < MAX_MCC_NUM; i++) { + iface = mccobjpriv->iface[i]; if (iface == NULL) continue; + + mccadapriv = &iface->mcc_adapterpriv; + /* use other interface to set cmd */ if (iface != padapter) { rtw_hal_set_mcc_ctrl_cmd(iface, _TRUE); @@ -1014,38 +2148,94 @@ static void rtw_hal_mcc_status_hdl(PADAPTER padapter, u8 status) static void rtw_hal_mcc_stop_posthdl(PADAPTER padapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); + struct mcc_adapter_priv *mccadapriv = NULL; _adapter *iface = NULL; + PHAL_DATA_TYPE hal; + struct dm_struct *p_dm_odm; u8 i = 0; + u8 enable_rx_bar = _FALSE; - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; + for (i = 0; i < MAX_MCC_NUM; i++) { + iface = mccobjpriv->iface[i]; if (iface == NULL) continue; + /* release network queue */ rtw_netif_wake_queue(iface->pnetdev); - iface->mcc_adapterpriv.mcc_tx_bytes_from_kernel = 0; - iface->mcc_adapterpriv.mcc_last_tx_bytes_from_kernel = 0; - iface->mcc_adapterpriv.mcc_tx_bytes_to_port = 0; + mccadapriv = &iface->mcc_adapterpriv; + mccadapriv->mcc_tx_bytes_from_kernel = 0; + mccadapriv->mcc_last_tx_bytes_from_kernel = 0; + mccadapriv->mcc_tx_bytes_to_port = 0; - if (iface->mcc_adapterpriv.role == MCC_ROLE_GO) + if (mccadapriv->role == MCC_ROLE_GO) rtw_hal_mcc_remove_go_p2p_ie(iface); + +#ifdef CONFIG_TDLS + if (MLME_IS_STA(iface)) { + if (mccadapriv->backup_tdls_en) { + rtw_enable_tdls_func(iface); + RTW_INFO("%s: Disable MCC, Enable TDLS\n", __func__); + mccadapriv->backup_tdls_en = _FALSE; + } + } +#endif /* CONFIG_TDLS */ + + mccadapriv->role = MCC_ROLE_MAX; + mccobjpriv->iface[i] = NULL; } + + hal = GET_HAL_DATA(padapter); + p_dm_odm = &hal->odmpriv; + phydm_dm_early_init(p_dm_odm); + + /* force switch channel */ + hal->current_channel = 0; + hal->current_channel_bw = CHANNEL_WIDTH_MAX; } static void rtw_hal_mcc_start_posthdl(PADAPTER padapter) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); + struct mcc_adapter_priv *mccadapriv = NULL; _adapter *iface = NULL; + PHAL_DATA_TYPE hal; + struct dm_struct *p_dm_odm; + struct _hal_rf_ *p_rf; + u32 support_ability = 0; u8 i = 0; + u8 enable_rx_bar = _TRUE; for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (iface == NULL) continue; - iface->mcc_adapterpriv.mcc_tx_bytes_from_kernel = 0; - iface->mcc_adapterpriv.mcc_last_tx_bytes_from_kernel = 0; - iface->mcc_adapterpriv.mcc_tx_bytes_to_port = 0; + + mccadapriv = &iface->mcc_adapterpriv; + if (mccadapriv->role == MCC_ROLE_MAX) + continue; + + mccadapriv->mcc_tx_bytes_from_kernel = 0; + mccadapriv->mcc_last_tx_bytes_from_kernel = 0; + mccadapriv->mcc_tx_bytes_to_port = 0; + +#ifdef CONFIG_TDLS + if (MLME_IS_STA(iface)) { + if (rtw_is_tdls_enabled(iface)) { + mccadapriv->backup_tdls_en = _TRUE; + rtw_disable_tdls_func(iface, _TRUE); + RTW_INFO("%s: Enable MCC, Disable TDLS\n", __func__); + } + } +#endif /* CONFIG_TDLS */ } + + hal = GET_HAL_DATA(padapter); + p_dm_odm = &hal->odmpriv; + p_rf = &(p_dm_odm->rf_table); + mccobjpriv->backup_phydm_ability = p_rf->rf_supportability; + p_rf->rf_supportability = p_rf->rf_supportability & (~HAL_RF_TX_PWR_TRACK) & (~HAL_RF_IQK); } /* @@ -1079,6 +2269,7 @@ static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status) if (ret == _SUCCESS) { RTW_INFO(FUNC_ADPT_FMT": mcc start sucecssfully\n", FUNC_ADPT_ARG(padapter)); + rtw_hal_mcc_status_hdl(padapter, status); rtw_hal_mcc_start_posthdl(padapter); } } else { @@ -1094,13 +2285,12 @@ static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status) RTW_INFO(FUNC_ADPT_FMT": wait for mcc stop C2H time out\n", FUNC_ADPT_ARG(padapter)); else { ret = _SUCCESS; + rtw_hal_mcc_status_hdl(padapter, status); rtw_hal_mcc_stop_posthdl(padapter); } } exit: - - rtw_hal_mcc_status_hdl(padapter, status); /* clear mcc status */ rtw_hal_clear_mcc_status(padapter , MCC_STATUS_PROCESS_MCC_START_SETTING | MCC_STATUS_PROCESS_MCC_STOP_SETTING); @@ -1145,6 +2335,9 @@ static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter) for (i = 0; i < iface_num; i++) { iface = pdvobjpriv->padapters[i]; + if (iface == NULL) + continue; + if (cur_op_ch == iface->mlmeextpriv.cur_channel) { cur_iface = iface; cur_mccadapriv = &cur_iface->mcc_adapterpriv; @@ -1156,6 +2349,12 @@ static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter) } } + if (cur_iface == NULL || next_iface == NULL) { + RTW_ERR("cur_iface=%p,next_iface=%p\n", cur_iface, next_iface); + rtw_warn_on(1); + return; + } + /* check other interface tx busy traffic or not under every 2 switch channel notify(Mbits/100ms) */ if (cnt == 2) { cur_mccadapriv->mcc_tp = (cur_mccadapriv->mcc_tx_bytes_from_kernel @@ -1234,6 +2433,9 @@ static void rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter, u8 buflen, continue; pmccadapriv = &iface->mcc_adapterpriv; + if (pmccadapriv->role == MCC_ROLE_MAX) + continue; + /* GO & channel match */ if (pmccadapriv->role == MCC_ROLE_GO) { /* convert GO TBTT from FW to noa_start_time(TU convert to mircosecond) */ @@ -1259,6 +2461,31 @@ static void rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter, u8 buflen, } +static void rtw_hal_mcc_rpt_tsf_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf) +{ + struct dvobj_priv *dvobjpriv = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); + struct submit_ctx *mcc_tsf_req_sctx = &mccobjpriv->mcc_tsf_req_sctx; + struct mcc_adapter_priv *mccadapriv = NULL; + _adapter *iface = NULL; + u8 order = 0; + + order = mccobjpriv->mcc_tsf_req_sctx_order; + iface = mccobjpriv->iface[order]; + mccadapriv = &iface->mcc_adapterpriv; + mccadapriv->tsf = RTW_GET_LE64(tmpBuf + 2); + + + if (0) + RTW_INFO(FUNC_ADPT_FMT" TSF(order:%d):0x%02llx\n", FUNC_ADPT_ARG(iface), mccadapriv->order, mccadapriv->tsf); + + if (mccadapriv->order == (MAX_MCC_NUM - 1)) + rtw_sctx_done(&mcc_tsf_req_sctx); + else + mccobjpriv->mcc_tsf_req_sctx_order ++; + +} + /** * rtw_hal_mcc_c2h_handler - mcc c2h handler */ @@ -1268,6 +2495,8 @@ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf) struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; struct submit_ctx *mcc_sctx = &pmccobjpriv->mcc_sctx; + _adapter *cur_adapter = NULL; + u8 cur_ch = 0, cur_bw = 0, cur_ch_offset = 0; _irqL irqL; /* RTW_INFO("[length]=%d, [C2H data]="MAC_FMT"\n", buflen, MAC_ARG(tmpBuf)); */ @@ -1278,19 +2507,32 @@ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf) } pmccobjpriv->mcc_c2h_status = tmpBuf[0]; + pmccobjpriv->current_order = tmpBuf[1]; + cur_adapter = pmccobjpriv->iface[pmccobjpriv->current_order]; + cur_ch = cur_adapter->mlmeextpriv.cur_channel; + cur_bw = cur_adapter->mlmeextpriv.cur_bwmode; + cur_ch_offset = cur_adapter->mlmeextpriv.cur_ch_offset; + rtw_set_oper_ch(cur_adapter, cur_ch); + rtw_set_oper_bw(cur_adapter, cur_bw); + rtw_set_oper_choffset(cur_adapter, cur_ch_offset); + + if (0) + RTW_INFO("%d,order:%d,TSF:0x%llx\n", tmpBuf[0], tmpBuf[1], RTW_GET_LE64(tmpBuf + 2)); + switch (pmccobjpriv->mcc_c2h_status) { case MCC_RPT_SUCCESS: - pdvobjpriv->oper_channel = tmpBuf[1]; _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL); pmccobjpriv->cur_mcc_success_cnt++; + rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _FALSE); _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL); break; case MCC_RPT_TXNULL_FAIL: RTW_INFO("[MCC] TXNULL FAIL\n"); break; case MCC_RPT_STOPMCC: - RTW_INFO("[MCC] MCC stop (time:%d)\n", rtw_get_current_time()); + RTW_INFO("[MCC] MCC stop\n"); pmccobjpriv->mcc_c2h_status = MCC_RPT_STOPMCC; + rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _TRUE); rtw_sctx_done(&mcc_sctx); break; case MCC_RPT_READY: @@ -1303,22 +2545,116 @@ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf) pmccobjpriv->mcc_tolerance_time = MCC_TOLERANCE_TIME; _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL); - RTW_INFO("[MCC] MCC ready (time:%d)\n", pmccobjpriv->mcc_launch_time); + RTW_INFO("[MCC] MCC ready\n"); rtw_sctx_done(&mcc_sctx); break; case MCC_RPT_SWICH_CHANNEL_NOTIFY: - pdvobjpriv->oper_channel = tmpBuf[1]; rtw_hal_mcc_sw_ch_fw_notify_hdl(padapter); break; case MCC_RPT_UPDATE_NOA_START_TIME: rtw_hal_mcc_update_noa_start_time_hdl(padapter, buflen, tmpBuf); break; + case MCC_RPT_TSF: + _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL); + rtw_hal_mcc_rpt_tsf_hdl(padapter, buflen, tmpBuf); + _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL); + break; default: /* RTW_INFO("[MCC] Other MCC status(%d)\n", pmccobjpriv->mcc_c2h_status); */ break; } } +void rtw_hal_mcc_update_parameter(PADAPTER padapter, u8 force_update) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0}; + u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME; + u8 ap_num = DEV_AP_NUM(dvobj); + + if (ap_num == 0) { + u8 need_update = _FALSE; + u8 start_time_offset = 0, interval = 0, duration = 0; + + need_update = rtw_hal_mcc_update_timing_parameters(padapter, force_update); + + if (need_update == _FALSE) + return; + + start_time_offset = mccobjpriv->start_time; + interval = mccobjpriv->interval; + duration = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration; + + SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, start_time_offset); + SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval); + SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time); + SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE); + SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, duration); + } else { + PADAPTER order0_iface = NULL; + PADAPTER order1_iface = NULL; + u8 policy_idx = mccobjpriv->policy_index; + u8 duration = mcc_switch_channel_policy_table[policy_idx][MCC_DURATION_IDX]; + u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX]; + u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX]; + u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX]; + u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX]; + u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX]; + u8 order0_duration = 0; + u8 i = 0; + enum _hw_port tsf_bsae_port = MAX_HW_PORT; + enum _hw_port tsf_sync_port = MAX_HW_PORT; + + RTW_INFO("%s: policy_idx=%d\n", __func__, policy_idx); + + order0_iface = mccobjpriv->iface[0]; + order1_iface = mccobjpriv->iface[1]; + + /* GO/AP is order 0, GC/STA is order 1 */ + order0_duration = order0_iface->mcc_adapterpriv.mcc_duration = interval - duration; + order0_iface->mcc_adapterpriv.mcc_duration = duration; + + tsf_bsae_port = rtw_hal_get_port(order1_iface); + tsf_sync_port = rtw_hal_get_port(order0_iface); + + /* update IE */ + for (i = 0; i < dvobj->iface_nums; i++) { + PADAPTER iface = NULL; + struct mcc_adapter_priv *mccadapriv = NULL; + + iface = dvobj->padapters[i]; + if (iface == NULL) + continue; + + mccadapriv = &iface->mcc_adapterpriv; + if (mccadapriv->role == MCC_ROLE_MAX) + continue; + + if (mccadapriv->role == MCC_ROLE_GO) + rtw_hal_mcc_update_go_p2p_ie(iface); + } + + /* update H2C cmd */ + /* FW set enable */ + SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, _TRUE); + /* TSF Sync offset */ + SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset); + /* start time offset */ + SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0)); + /* interval */ + SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval); + /* Early time to inform driver by C2H before switch channel */ + SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time); + /* Port0 sync from Port1, not support multi-port */ + SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, tsf_bsae_port); + SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, tsf_sync_port); + SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE); + SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, order0_duration); + } + + rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd); +} /** * rtw_hal_mcc_sw_status_check - check mcc swich channel status @@ -1329,8 +2665,14 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter) struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); - u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL; + struct mcc_adapter_priv *mccadapriv = NULL; + _adapter *iface = NULL; + u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL, threshold = 0; + u8 policy_idx = pmccobjpriv->policy_index; + u8 noa_enable = _FALSE; + u8 i = 0; _irqL irqL; + u8 ap_num = DEV_AP_NUM(dvobj); /* #define MCC_RESTART 1 */ @@ -1341,6 +2683,27 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter) if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { + /* check noa enable or not */ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface == NULL) + continue; + + mccadapriv = &iface->mcc_adapterpriv; + if (mccadapriv->role == MCC_ROLE_MAX) + continue; + + if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) { + noa_enable = _TRUE; + break; + } + } + + if (!noa_enable && ap_num == 0) + rtw_hal_mcc_update_parameter(padapter, _FALSE); + + threshold = pmccobjpriv->mcc_stop_threshold; + if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) { rtw_warn_on(1); RTW_INFO("PS mode is not active under mcc, force exit ps mode\n"); @@ -1357,7 +2720,7 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter) else diff_cnt = cur_cnt - prev_cnt; - if (diff_cnt < 30) { + if (diff_cnt < threshold) { pmccobjpriv->mcc_tolerance_time--; RTW_INFO("%s: diff_cnt:%d, tolerance_time:%d\n", __func__, diff_cnt, pmccobjpriv->mcc_tolerance_time); @@ -1402,10 +2765,11 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter) */ u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset) { - u8 need_ch_setting_union = _TRUE, i = 0, flags = 0, role = 0; + u8 need_ch_setting_union = _TRUE, i = 0, flags = 0, back_op = _FALSE; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); - struct mcc_adapter_priv *pmccadapriv = NULL; - struct mlme_ext_priv *pmlmeext = NULL; + struct mcc_adapter_priv *mccadapriv = NULL; + struct mlme_ext_priv *mlmeext = NULL; + _adapter *iface = NULL; if (!MCC_EN(padapter)) goto exit; @@ -1413,41 +2777,45 @@ u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset) if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) goto exit; - for (i = 0; i < dvobj->iface_nums; i++) { - if (!dvobj->padapters[i]) - continue; - - pmlmeext = &dvobj->padapters[i]->mlmeextpriv; - pmccadapriv = &dvobj->padapters[i]->mcc_adapterpriv; - role = pmccadapriv->role; + /* disable PS_ANNC & TX_RESUME for all interface */ + /* ToDo: TX_RESUME by interface in SCAN_BACKING_OP */ + mlmeext = &padapter->mlmeextpriv; + + flags = mlmeext_scan_backop_flags(mlmeext); + if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_PS_ANNC)) + flags &= ~SS_BACKOP_PS_ANNC; - switch (role) { - case MCC_ROLE_AP: - case MCC_ROLE_GO: - *ch = pmlmeext->cur_channel; - *bw = pmlmeext->cur_bwmode; - *offset = pmlmeext->cur_ch_offset; - need_ch_setting_union = _FALSE; - break; - case MCC_ROLE_STA: - case MCC_ROLE_GC: - break; - default: - RTW_INFO("unknown role\n"); - rtw_warn_on(1); - break; - } + if (mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)) + flags &= ~SS_BACKOP_TX_RESUME; - /* check other scan flag */ - flags = mlmeext_scan_backop_flags(pmlmeext); - if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) - flags &= ~SS_BACKOP_PS_ANNC; + mlmeext_assign_scan_backop_flags(mlmeext, flags); - if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_TX_RESUME)) - flags &= ~SS_BACKOP_TX_RESUME; + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; - mlmeext_assign_scan_backop_flags(pmlmeext, flags); + mlmeext = &iface->mlmeextpriv; + if (MLME_IS_GO(iface) || MLME_IS_AP(iface)) + back_op = _TRUE; + else if (MLME_IS_GC(iface) && (iface != padapter)) + /* switch to another linked interface(GO) to receive beacon to avoid no beacon disconnect */ + back_op = _TRUE; + else if (MLME_IS_STA(iface) && MLME_IS_ASOC(iface) && (iface != padapter)) + /* switch to another linked interface(STA) to receive beacon to avoid no beacon disconnect */ + back_op = _TRUE; + else { + /* bypass non-linked/non-linking interface/scan interface */ + continue; + } + + if (back_op) { + *ch = mlmeext->cur_channel; + *bw = mlmeext->cur_bwmode; + *offset = mlmeext->cur_ch_offset; + need_ch_setting_union = _FALSE; + } } exit: return need_ch_setting_union; @@ -1483,13 +2851,14 @@ inline void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len) struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv); struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { pmccadapriv->mcc_tx_bytes_to_port += len; if (0) RTW_INFO("%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\n" , __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port , pmccadapriv->mcc_target_tx_bytes_to_port); } + } } /** @@ -1516,6 +2885,45 @@ inline u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter) return _FALSE; } +static void rtw_hal_mcc_assign_scan_flag(PADAPTER padapter, u8 scan_done) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_adapter_priv *mccadapriv = NULL; + _adapter *iface = NULL; + struct mlme_ext_priv *pmlmeext = NULL; + u8 i = 0, flags; + + if (!MCC_EN(padapter)) + return; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface == NULL) + continue; + + mccadapriv = &iface->mcc_adapterpriv; + if (mccadapriv->role == MCC_ROLE_MAX) + continue; + + pmlmeext = &iface->mlmeextpriv; + if (is_client_associated_to_ap(iface)) { + flags = mlmeext_scan_backop_flags_sta(pmlmeext); + if (scan_done) { + if (mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) { + flags &= ~SS_BACKOP_EN; + mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags); + } + } else { + if (!mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) { + flags |= SS_BACKOP_EN; + mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags); + } + } + + } + } +} + /** * rtw_hal_set_mcc_setting_scan_start - setting mcc under scan start * @padapter: the adapter to be setted @@ -1532,8 +2940,7 @@ u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter) if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) { if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) { ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_SCAN_START); - /* issue null data to all station connected to AP before scan */ - rtw_hal_mcc_issue_null_data(padapter, 0, 1); + rtw_hal_mcc_assign_scan_flag(padapter, 0); } } _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); @@ -1556,9 +2963,10 @@ u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter) _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); - if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) - ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_SCAN_DONE); - + if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) { + rtw_hal_mcc_assign_scan_flag(padapter, 1); + ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_SCAN_DONE); + } _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); } @@ -1655,9 +3063,9 @@ u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter) _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT); _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL); - } } } + } return ret; } @@ -1680,12 +3088,15 @@ u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw if (chbw_allow == _FALSE) { struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + /* issue null data to other interface connected to AP */ + rtw_hal_mcc_issue_null_data(padapter, chbw_allow, _TRUE); + *ch = pmlmeext->cur_channel; *bw = pmlmeext->cur_bwmode; *offset = pmlmeext->cur_ch_offset; RTW_INFO(FUNC_ADPT_FMT" en_mcc:%d(%d,%d,%d,)\n" - , FUNC_ADPT_ARG(padapter), padapter->registrypriv.en_mcc + , FUNC_ADPT_ARG(padapter), MCC_EN(padapter) , *ch, *bw, *offset); ret = _SUCCESS; } @@ -1713,34 +3124,47 @@ static void rtw_hal_mcc_dump_noa_content(void *sel, PADAPTER padapter) void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj) { - struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); - struct mcc_adapter_priv *pmccadapriv = NULL; + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + struct mcc_adapter_priv *mccadapriv = NULL; _adapter *iface = NULL, *adapter = NULL; struct registry_priv *regpriv = NULL; + u64 tsf[MAX_MCC_NUM] = {0}; u8 i = 0; /* regpriv is common for all adapter */ - adapter = dvobj->padapters[IFACE_ID0]; + adapter = dvobj_get_primary_adapter(dvobj); RTW_PRINT_SEL(sel, "**********************************************\n"); + RTW_PRINT_SEL(sel, "en_mcc:%d\n", MCC_EN(adapter)); + RTW_PRINT_SEL(sel, "primary adapter("ADPT_FMT") duration:%d%c\n", + ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mccobjpriv->duration, 37); + RTW_PRINT_SEL(sel, "runtime duration:%s\n", mccobjpriv->enable_runtime_duration ? "enable":"disable"); + + rtw_hal_mcc_rqt_tsf(dvobj_get_primary_adapter(dvobj), tsf); + for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if (!iface) continue; regpriv = &iface->registrypriv; - pmccadapriv = &iface->mcc_adapterpriv; - if (pmccadapriv) { + mccadapriv = &iface->mcc_adapterpriv; + if (mccadapriv->role == MCC_ROLE_MAX) + continue; + + if (mccadapriv) { + u8 p2p_ps_mode = iface->wdinfo.p2p_ps_mode; + RTW_PRINT_SEL(sel, "adapter mcc info:\n"); RTW_PRINT_SEL(sel, "ifname:%s\n", ADPT_ARG(iface)); - RTW_PRINT_SEL(sel, "order:%d\n", pmccadapriv->order); - RTW_PRINT_SEL(sel, "duration:%d\n", pmccadapriv->mcc_duration); - RTW_PRINT_SEL(sel, "target tx bytes:%d\n", pmccadapriv->mcc_target_tx_bytes_to_port); - RTW_PRINT_SEL(sel, "current TP:%d\n", pmccadapriv->mcc_tp); - RTW_PRINT_SEL(sel, "mgmt queue macid:%d\n", pmccadapriv->mgmt_queue_macid); - RTW_PRINT_SEL(sel, "macid bitmap:0x%02x\n\n", pmccadapriv->mcc_macid_bitmap); + RTW_PRINT_SEL(sel, "order:%d\n", mccadapriv->order); + RTW_PRINT_SEL(sel, "duration:%d\n", mccadapriv->mcc_duration); + RTW_PRINT_SEL(sel, "target tx bytes:%d\n", mccadapriv->mcc_target_tx_bytes_to_port); + RTW_PRINT_SEL(sel, "current TP:%d\n", mccadapriv->mcc_tp); + RTW_PRINT_SEL(sel, "mgmt queue macid:%d\n", mccadapriv->mgmt_queue_macid); + RTW_PRINT_SEL(sel, "macid bitmap:0x%02x\n", mccadapriv->mcc_macid_bitmap); + RTW_PRINT_SEL(sel, "P2P NoA:%s\n\n", p2p_ps_mode == P2P_PS_NOA ? "enable":"disable"); RTW_PRINT_SEL(sel, "registry data:\n"); - RTW_PRINT_SEL(sel, "en_mcc:%d\n", regpriv->en_mcc); RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_ap_bw20_target_tx_tp); RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", regpriv->rtw_mcc_ap_bw40_target_tx_tp); RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_ap_bw80_target_tx_tp); @@ -1748,13 +3172,14 @@ void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj) RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M ):%d Mbps\n", regpriv->rtw_mcc_sta_bw40_target_tx_tp); RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_sta_bw80_target_tx_tp); RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", regpriv->rtw_mcc_single_tx_cri); + RTW_PRINT_SEL(sel, "HW TSF=0x%llx\n", tsf[mccadapriv->order]); if (MLME_IS_GO(iface)) rtw_hal_mcc_dump_noa_content(sel, iface); RTW_PRINT_SEL(sel, "**********************************************\n"); } } RTW_PRINT_SEL(sel, "------------------------------------------\n"); - RTW_PRINT_SEL(sel, "policy index:%d\n", pmccobjpriv->policy_index); + RTW_PRINT_SEL(sel, "policy index:%d\n", mccobjpriv->policy_index); RTW_PRINT_SEL(sel, "------------------------------------------\n"); RTW_PRINT_SEL(sel, "define data:\n"); RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", MCC_AP_BW20_TARGET_TX_TP); @@ -1811,7 +3236,7 @@ void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode) { struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); _adapter *iface = NULL; - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); u8 i = 0; if (!MCC_EN(padapter)) @@ -1828,11 +3253,22 @@ void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode) /* issue null data to inform ap station will leave */ if (is_client_associated_to_ap(iface)) { struct mlme_ext_priv *mlmeext = &iface->mlmeextpriv; + struct mlme_ext_info *mlmeextinfo = &mlmeext->mlmext_info; u8 ch = mlmeext->cur_channel; u8 bw = mlmeext->cur_bwmode; u8 offset = mlmeext->cur_ch_offset; + struct sta_info *sta = rtw_get_stainfo(&iface->stapriv, get_my_bssid(&(mlmeextinfo->network))); + + if (!sta) + continue; + + set_channel_bwmode(iface, ch, offset, bw); + + if (ps_mode) + rtw_hal_macid_sleep(iface, sta->cmn.mac_id); + else + rtw_hal_macid_wakeup(iface, sta->cmn.mac_id); - set_channel_bwmode(iface, ch, bw, offset); issue_nulldata(iface, NULL, ps_mode, 3, 50); } } @@ -1874,4 +3310,179 @@ void rtw_hal_dump_mcc_policy_table(void *sel) } } +void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add) +{ + struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv; + + if (!MCC_EN(padapter)) + return; + + if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + return; + + if (pmccadapriv->role == MCC_ROLE_GC || pmccadapriv->role == MCC_ROLE_STA) + return; + + if (mac_id < 0) { + RTW_WARN("%s: mac_id < 0(%d)\n", __func__, mac_id); + return; + } + + RTW_INFO(ADPT_FMT" %s macid=%d, ori mcc_macid_bitmap=0x%08x\n" + , ADPT_ARG(padapter), add ? "add" : "clear" + , mac_id, pmccadapriv->mcc_macid_bitmap); + + if (add) + pmccadapriv->mcc_macid_bitmap |= BIT(mac_id); + else + pmccadapriv->mcc_macid_bitmap &= ~(BIT(mac_id)); + + rtw_hal_set_mcc_macid_cmd(padapter); +} + +void rtw_hal_mcc_process_noa(PADAPTER padapter) +{ + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv); + + if (!MCC_EN(padapter)) + return; + + if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) + return; + + if (!MLME_IS_GC(padapter)) + return; + + switch(pwdinfo->p2p_ps_mode) { + case P2P_PS_NONE: + RTW_INFO("[MCC] Disable NoA under MCC\n"); + rtw_hal_mcc_update_parameter(padapter, _TRUE); + break; + case P2P_PS_NOA: + RTW_INFO("[MCC] Enable NoA under MCC\n"); + break; + default: + break; + + } +} + +void rtw_hal_mcc_parameter_init(PADAPTER padapter) +{ + if (!padapter->registrypriv.en_mcc) + return; + + if (is_primary_adapter(padapter)) { + SET_MCC_EN_FLAG(padapter, padapter->registrypriv.en_mcc); + SET_MCC_DURATION(padapter, padapter->registrypriv.rtw_mcc_duration); + SET_MCC_RUNTIME_DURATION(padapter, padapter->registrypriv.rtw_mcc_enable_runtime_duration); + } +} + + +u8 rtw_set_mcc_duration_hdl(PADAPTER adapter, u8 type, const u8 *val) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv); + _adapter *iface = NULL; + u8 duration = 50; + u8 ret = _SUCCESS, noa_enable = _FALSE, i = 0; + + if (!mccobjpriv->enable_runtime_duration) + goto exit; + +#ifdef CONFIG_P2P_PS + /* check noa enable or not */ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) { + noa_enable = _TRUE; + break; + } + } +#endif /* CONFIG_P2P_PS */ + + + + if (type == MCC_DURATION_MAPPING) { + switch (*val) { + /* 0 = fair scheduling */ + case 0: + mccobjpriv->duration= 40; + mccobjpriv->policy_index = 2; + mccobjpriv->mchan_sched_mode = MCC_FAIR_SCHEDULE; + break; + /* 1 = favor STA */ + case 1: + mccobjpriv->duration= 70; + mccobjpriv->policy_index = 1; + mccobjpriv->mchan_sched_mode = MCC_FAVOE_STA; + break; + /* 2 = favor P2P*/ + case 2: + default: + mccobjpriv->duration= 30; + mccobjpriv->policy_index = 0; + mccobjpriv->mchan_sched_mode = MCC_FAVOE_P2P; + break; + } + } else { + mccobjpriv->duration = *val; + rtw_hal_mcc_update_policy_table(adapter); + } + + /* only update sw parameter under MCC + it will be force update during */ + if (noa_enable) + goto exit; + + if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) + rtw_hal_mcc_update_parameter(adapter, _TRUE); +exit: + return ret; +} + +u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + u8 *mcc_duration = NULL; + u8 res = _FAIL; + + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) + goto exit; + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + goto exit; + } + + mcc_duration = rtw_zmalloc(sizeof(u8)); + if (mcc_duration == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = MCC_SET_DURATION_WK_CID; + pdrvextra_cmd_parm->type = type; + pdrvextra_cmd_parm->size = 1; + pdrvextra_cmd_parm->pbuf = mcc_duration; + + _rtw_memcpy(mcc_duration, &val, 1); + + init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + +exit: + return res; +} + #endif /* CONFIG_MCC_MODE */ diff --git a/hal/hal_mp.c b/hal/hal_mp.c index df69134..1af9de3 100644 --- a/hal/hal_mp.c +++ b/hal/hal_mp.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_MP_C_ #include @@ -47,9 +42,18 @@ #ifdef CONFIG_RTL8723D #include #endif + #ifdef CONFIG_RTL8710B + #include + #endif #ifdef CONFIG_RTL8188F #include #endif + #ifdef CONFIG_RTL8188GTV + #include + #endif + #ifdef CONFIG_RTL8192F + #include + #endif #endif /* !RTW_HALMAC */ @@ -83,34 +87,34 @@ void hal_mpt_SwitchRfSetting(PADAPTER pAdapter) /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/ if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) && (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) { - pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0); - pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0); if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); } else { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD); + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD); } } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/ if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ } else { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ } } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A); + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B); } } s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); if (!netif_running(padapter->pnetdev)) { @@ -131,7 +135,7 @@ s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable) void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control; @@ -150,7 +154,8 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) u1Byte DataRate = 0xFF; /* Do not modify CCK TX filter parameters for 8822B*/ - if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter)) + if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) || + IS_HARDWARE_TYPE_8723D(Adapter) || IS_HARDWARE_TYPE_8192F(Adapter)) return; DataRate = mpt_to_mgnt_rate(ulRateIdx); @@ -188,7 +193,7 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) pHalData->RegForRecover[i].value); } } - } else if (IS_HARDWARE_TYPE_8188F(Adapter)) { + } else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) { /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/ CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord); CCKSwingIndex = 20; /* default index */ @@ -313,9 +318,9 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) void hal_mpt_SetChannel(PADAPTER pAdapter) { - u8 eRFPath; + enum rf_path eRFPath; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct dm_struct *pDM_Odm = &(pHalData->odmpriv); struct mp_priv *pmp = &pAdapter->mppriv; u8 channel = pmp->channel; u8 bandwidth = pmp->bandwidth; @@ -324,9 +329,18 @@ void hal_mpt_SetChannel(PADAPTER pAdapter) pHalData->bSwChnl = _TRUE; pHalData->bSetChnlBW = _TRUE; - rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); + +#ifdef CONFIG_RTL8822B + if (bandwidth == 2) { + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER); + } else if (bandwidth == 1) { + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0); + } else +#endif + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0); hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14); + rtw_btcoex_wifionly_scan_notify(pAdapter); } @@ -344,9 +358,19 @@ void hal_mpt_SetBandwidth(PADAPTER pAdapter) pHalData->bSwChnl = _TRUE; pHalData->bSetChnlBW = _TRUE; - rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); + +#ifdef CONFIG_RTL8822B + if (bandwidth == 2) { + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_LOWER, HAL_PRIME_CHNL_OFFSET_UPPER); + } else if (bandwidth == 1) { + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, HAL_PRIME_CHNL_OFFSET_UPPER, 0); + } else +#endif + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, 0); hal_mpt_SwitchRfSetting(pAdapter); + rtw_btcoex_wifionly_scan_notify(pAdapter); + } void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower) @@ -356,16 +380,16 @@ void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower) u4Byte TxAGC = 0, pwr = 0; u1Byte rf; - pwr = pTxPower[ODM_RF_PATH_A]; + pwr = pTxPower[RF_PATH_A]; if (pwr < 0x3f) { TxAGC = (pwr << 16) | (pwr << 8) | (pwr); - phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]); + phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]); phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); } - pwr = pTxPower[ODM_RF_PATH_B]; + pwr = pTxPower[RF_PATH_B]; if (pwr < 0x3f) { TxAGC = (pwr << 16) | (pwr << 8) | (pwr); - phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]); + phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]); phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC); } } @@ -417,12 +441,13 @@ mpt_SetTxPower( HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); u1Byte path = 0 , i = 0, MaxRate = MGN_6M; - u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B; + u1Byte StartPath = RF_PATH_A, EndPath = RF_PATH_B; if (IS_HARDWARE_TYPE_8814A(pAdapter)) - EndPath = ODM_RF_PATH_D; - else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) - EndPath = ODM_RF_PATH_A; + EndPath = RF_PATH_D; + else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter) + || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) + EndPath = RF_PATH_A; switch (Rate) { case MPT_CCK: { @@ -506,15 +531,17 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct dm_struct *pDM_Odm = &pHalData->odmpriv; - if (pHalData->rf_chip < RF_TYPE_MAX) { + if (pHalData->rf_chip < RF_CHIP_MAX) { if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8192E(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter) || - IS_HARDWARE_TYPE_8188F(pAdapter)) { - u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B); + IS_HARDWARE_TYPE_8188F(pAdapter) || + IS_HARDWARE_TYPE_8188GTV(pAdapter) + ) { + u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (RF_PATH_A) : (RF_PATH_B); RTW_INFO("===> MPT_ProSetTxPower: Old\n"); @@ -522,15 +549,17 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter) mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel); } else { - RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n"); + mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel); mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel); mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel); - mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel); - + if(IS_HARDWARE_TYPE_JAGUAR(pAdapter)||IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) { + RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n"); + mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel); + } } } else - RTW_INFO("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip); + RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip); odm_clear_txpowertracking_state(pDM_Odm); } @@ -547,26 +576,26 @@ void hal_mpt_SetDataRate(PADAPTER pAdapter) hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14); #ifdef CONFIG_RTL8723B - if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) { + if (IS_HARDWARE_TYPE_8723B(pAdapter)) { if (IS_CCK_RATE(DataRate)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6); + if (pMptCtx->mpt_rf_path == RF_PATH_A) + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6); else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6); } else { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); + if (pMptCtx->mpt_rf_path == RF_PATH_A) + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE); else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE); } } if ((IS_HARDWARE_TYPE_8723BS(pAdapter) && ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); + if (pMptCtx->mpt_rf_path == RF_PATH_A) + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE); else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE); } #endif } @@ -579,15 +608,15 @@ VOID mpt_ToggleIG_8814A(PADAPTER pAdapter) u1Byte Path = 0; u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0; - for (Path; Path <= ODM_RF_PATH_D; Path++) { + for (Path; Path <= RF_PATH_D; Path++) { switch (Path) { - case ODM_RF_PATH_B: + case RF_PATH_B: IGReg = rB_IGI_Jaguar; break; - case ODM_RF_PATH_C: + case RF_PATH_C: IGReg = rC_IGI_Jaguar2; break; - case ODM_RF_PATH_D: + case RF_PATH_D: IGReg = rD_IGI_Jaguar2; break; default: @@ -609,7 +638,6 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */ R_ANTENNA_SELECT_CCK *p_cck_txrx; u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index); - u8 HtStbcCap = pAdapter->registrypriv.stbc_cap; /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/ /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/ @@ -617,52 +645,29 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) u32 ulAntennaRx = pHalData->AntennaRxPath; u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate); - if ((NssforRate == RF_2TX) || ((NssforRate == RF_1TX) && IS_HT_RATE(ForcedDataRate)) || ((NssforRate == RF_1TX) && IS_VHT_RATE(ForcedDataRate))) { - RTW_INFO("===> SetAntenna 2T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); - - switch (ulAntennaTx) { - case ANTENNA_BC: - pMptCtx->mpt_rf_path = ODM_RF_PATH_BC; - /*pHalData->ValidTxPath = 0x06; linux no use */ - phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106); /*/ 0x940[15:4]=12'b0000_0100_0011*/ - break; - - case ANTENNA_CD: - pMptCtx->mpt_rf_path = ODM_RF_PATH_CD; - /*pHalData->ValidTxPath = 0x0C;*/ - phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c); /*/ 0x940[15:4]=12'b0000_0100_0011*/ - break; - case ANTENNA_AB: - default: - pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; - /*pHalData->ValidTxPath = 0x03;*/ - phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043); /*/ 0x940[15:4]=12'b0000_0100_0011*/ - break; - } - - } else if (NssforRate == RF_3TX) { - RTW_INFO("===> SetAntenna 3T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); + if (NssforRate == RF_3TX) { + RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); switch (ulAntennaTx) { case ANTENNA_BCD: - pMptCtx->mpt_rf_path = ODM_RF_PATH_BCD; + pMptCtx->mpt_rf_path = RF_PATH_BCD; /*pHalData->ValidTxPath = 0x0e;*/ phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/ break; case ANTENNA_ABC: default: - pMptCtx->mpt_rf_path = ODM_RF_PATH_ABC; + pMptCtx->mpt_rf_path = RF_PATH_ABC; /*pHalData->ValidTxPath = 0x0d;*/ phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/ break; } } else { /*/if(NssforRate == RF_1TX)*/ - RTW_INFO("===> SetAntenna 1T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); + RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); switch (ulAntennaTx) { case ANTENNA_BCD: - pMptCtx->mpt_rf_path = ODM_RF_PATH_BCD; + pMptCtx->mpt_rf_path = RF_PATH_BCD; /*pHalData->ValidTxPath = 0x0e;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7); phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe); @@ -670,14 +675,14 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) break; case ANTENNA_BC: - pMptCtx->mpt_rf_path = ODM_RF_PATH_BC; + pMptCtx->mpt_rf_path = RF_PATH_BC; /*pHalData->ValidTxPath = 0x06;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6); phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6); phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6); break; case ANTENNA_B: - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; /*pHalData->ValidTxPath = 0x02;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/ @@ -685,7 +690,7 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) break; case ANTENNA_C: - pMptCtx->mpt_rf_path = ODM_RF_PATH_C; + pMptCtx->mpt_rf_path = RF_PATH_C; /*pHalData->ValidTxPath = 0x04;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/ @@ -693,7 +698,7 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) break; case ANTENNA_D: - pMptCtx->mpt_rf_path = ODM_RF_PATH_D; + pMptCtx->mpt_rf_path = RF_PATH_D; /*pHalData->ValidTxPath = 0x08;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/ @@ -702,7 +707,7 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_A: default: - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; /*pHalData->ValidTxPath = 0x01;*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/ @@ -714,14 +719,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) switch (ulAntennaRx) { case ANTENNA_A: /*pHalData->ValidRxPath = 0x01;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -729,14 +736,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_B: /*pHalData->ValidRxPath = 0x02;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -744,14 +753,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_C: /*pHalData->ValidRxPath = 0x04;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -759,14 +770,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_D: /*pHalData->ValidRxPath = 0x08;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -774,14 +787,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_BC: /*pHalData->ValidRxPath = 0x06;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -789,14 +804,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_CD: /*pHalData->ValidRxPath = 0x0C;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); @@ -804,14 +821,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_BCD: /*pHalData->ValidRxPath = 0x0e;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8); @@ -819,14 +838,16 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) case ANTENNA_ABCD: /*pHalData->ValidRxPath = 0x0f;*/ + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2); phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff); phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3); + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ /*/ CCA related PD_delay_th*/ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3); phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8); @@ -850,7 +871,7 @@ mpt_SetSingleTone_8814A( { PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); - u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_A; + u1Byte StartPath = RF_PATH_A, EndPath = RF_PATH_A; static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0; if (bSingleTone) { @@ -860,29 +881,29 @@ mpt_SetSingleTone_8814A( regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/ switch (pMptCtx->mpt_rf_path) { - case ODM_RF_PATH_A: - case ODM_RF_PATH_B: - case ODM_RF_PATH_C: - case ODM_RF_PATH_D: + case RF_PATH_A: + case RF_PATH_B: + case RF_PATH_C: + case RF_PATH_D: StartPath = pMptCtx->mpt_rf_path; EndPath = pMptCtx->mpt_rf_path; break; - case ODM_RF_PATH_AB: - EndPath = ODM_RF_PATH_B; + case RF_PATH_AB: + EndPath = RF_PATH_B; break; - case ODM_RF_PATH_BC: - StartPath = ODM_RF_PATH_B; - EndPath = ODM_RF_PATH_C; + case RF_PATH_BC: + StartPath = RF_PATH_B; + EndPath = RF_PATH_C; break; - case ODM_RF_PATH_ABC: - EndPath = ODM_RF_PATH_C; + case RF_PATH_ABC: + EndPath = RF_PATH_C; break; - case ODM_RF_PATH_BCD: - StartPath = ODM_RF_PATH_B; - EndPath = ODM_RF_PATH_D; + case RF_PATH_BCD: + StartPath = RF_PATH_B; + EndPath = RF_PATH_D; break; - case ODM_RF_PATH_ABCD: - EndPath = ODM_RF_PATH_D; + case RF_PATH_ABCD: + EndPath = RF_PATH_D; break; } @@ -906,29 +927,29 @@ mpt_SetSingleTone_8814A( phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/ } else { switch (pMptCtx->mpt_rf_path) { - case ODM_RF_PATH_A: - case ODM_RF_PATH_B: - case ODM_RF_PATH_C: - case ODM_RF_PATH_D: + case RF_PATH_A: + case RF_PATH_B: + case RF_PATH_C: + case RF_PATH_D: StartPath = pMptCtx->mpt_rf_path; EndPath = pMptCtx->mpt_rf_path; break; - case ODM_RF_PATH_AB: - EndPath = ODM_RF_PATH_B; + case RF_PATH_AB: + EndPath = RF_PATH_B; break; - case ODM_RF_PATH_BC: - StartPath = ODM_RF_PATH_B; - EndPath = ODM_RF_PATH_C; + case RF_PATH_BC: + StartPath = RF_PATH_B; + EndPath = RF_PATH_C; break; - case ODM_RF_PATH_ABC: - EndPath = ODM_RF_PATH_C; + case RF_PATH_ABC: + EndPath = RF_PATH_C; break; - case ODM_RF_PATH_BCD: - StartPath = ODM_RF_PATH_B; - EndPath = ODM_RF_PATH_D; + case RF_PATH_BCD: + StartPath = RF_PATH_B; + EndPath = RF_PATH_D; break; - case ODM_RF_PATH_ABCD: - EndPath = ODM_RF_PATH_D; + case RF_PATH_ABCD: + EndPath = RF_PATH_D; break; } for (StartPath; StartPath <= EndPath; StartPath++) @@ -964,25 +985,25 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) switch (ulAntennaTx) { case ANTENNA_A: - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111); if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0); break; case ANTENNA_B: - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222); if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1); break; case ANTENNA_AB: - pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; + pMptCtx->mpt_rf_path = RF_PATH_AB; phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333); if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0); break; default: - pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; + pMptCtx->mpt_rf_path = RF_PATH_AB; RTW_INFO("Unknown Tx antenna.\n"); break; } @@ -991,9 +1012,9 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) u32 reg0xC50 = 0; case ANTENNA_A: phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/ reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0); @@ -1017,9 +1038,9 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) break; case ANTENNA_B: phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3); /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/ reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0); @@ -1043,7 +1064,7 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) break; case ANTENNA_AB: phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); /* set PWED_TH for BB Yn user guide R29 */ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04); @@ -1052,6 +1073,18 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter) RTW_INFO("Unknown Rx antenna.\n"); break; } + + if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) { + if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) { + /* WiFi */ + phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2); + phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3); + } else { + /* BT */ + phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1); + phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3); + } + } } #endif @@ -1061,13 +1094,13 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter) HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); u32 ulAntennaTx, ulAntennaRx; PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); ulAntennaTx = pHalData->antenna_tx_path; ulAntennaRx = pHalData->AntennaRxPath; - if (pHalData->rf_chip >= RF_TYPE_MAX) { + if (pHalData->rf_chip >= RF_CHIP_MAX) { RTW_INFO("This RF chip ID is not supported\n"); return; } @@ -1075,19 +1108,13 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter) switch (pAdapter->mppriv.antenna_tx) { u8 p = 0, i = 0; case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/ - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0); phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/ - /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/ - if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); - else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); - for (i = 0; i < 3; ++i) { - u4Byte offset = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][0]; - u4Byte data = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][1]; + u4Byte offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0]; + u4Byte data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1]; if (offset != 0) { phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); @@ -1095,8 +1122,8 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter) } } for (i = 0; i < 2; ++i) { - u4Byte offset = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][0]; - u4Byte data = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][1]; + u4Byte offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0]; + u4Byte data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1]; if (offset != 0) { phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); @@ -1109,29 +1136,24 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter) u4Byte offset; u4Byte data; - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5); phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/ - /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/ - if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); - else - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); for (i = 0; i < 3; ++i) { /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/ - offset = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_A][i][0]; - data = pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_B][i][1]; - if (pRFCalibrateInfo->tx_iqc_8723b[ODM_RF_PATH_B][i][0] != 0) { + offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0]; + data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1]; + if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) { phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); } } /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/ for (i = 0; i < 2; ++i) { - offset = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_A][i][0]; - data = pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_B][i][1]; - if (pRFCalibrateInfo->rx_iqc_8723b[ODM_RF_PATH_B][i][0] != 0) { + offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0]; + data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1]; + if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) { phy_set_bb_reg(pAdapter, offset, bMaskDWord, data); RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); } @@ -1151,13 +1173,13 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter) HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); u4Byte ulAntennaTx, ulAntennaRx; PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); ulAntennaTx = pHalData->antenna_tx_path; ulAntennaRx = pHalData->AntennaRxPath; - if (pHalData->rf_chip >= RF_TYPE_MAX) { + if (pHalData->rf_chip >= RF_CHIP_MAX) { RTW_INFO("This RF chip ID is not supported\n"); return; } @@ -1166,7 +1188,7 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter) u1Byte p = 0, i = 0; case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */ - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0); phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/ @@ -1192,7 +1214,7 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter) } break; case ANTENNA_B: { /* Actually path S0 (BT)*/ - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5); phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */ @@ -1231,13 +1253,13 @@ void mpt_SetRFPath_8723D(PADAPTER pAdapter) u1Byte p = 0, i = 0; u4Byte ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0; PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); ulAntennaTx = pHalData->antenna_tx_path; ulAntennaRx = pHalData->AntennaRxPath; - if (pHalData->rf_chip >= RF_TYPE_MAX) { + if (pHalData->rf_chip >= RF_CHIP_MAX) { RTW_INFO("This RF chip ID is not supported\n"); return; } @@ -1245,13 +1267,13 @@ void mpt_SetRFPath_8723D(PADAPTER pAdapter) switch (pAdapter->mppriv.antenna_tx) { /* Actually path S1 (Wi-Fi) */ case ANTENNA_A: { - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0); } break; /* Actually path S0 (BT) */ case ANTENNA_B: { - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA); } @@ -1310,7 +1332,7 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0); } } - pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + pMptCtx->mpt_rf_path = RF_PATH_A; break; case ANTENNA_B: p_ofdm_tx->r_tx_antenna = 0x2; @@ -1337,7 +1359,7 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); } } - pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + pMptCtx->mpt_rf_path = RF_PATH_B; break; case ANTENNA_AB:/*/ For 8192S*/ p_ofdm_tx->r_tx_antenna = 0x3; @@ -1364,7 +1386,7 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); } } - pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; + pMptCtx->mpt_rf_path = RF_PATH_AB; break; default: break; @@ -1422,6 +1444,65 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter) } } /* MPT_ProSetRFPath */ +#ifdef CONFIG_RTL8192F + +void mpt_set_rfpath_8192f(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + + u16 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index); + u8 NssforRate, odmNssforRate; + u32 ulAntennaTx, ulAntennaRx; + u8 RxAntToPhyDm; + u8 TxAntToPhyDm; + + ulAntennaTx = pHalData->antenna_tx_path; + ulAntennaRx = pHalData->AntennaRxPath; + NssforRate = MgntQuery_NssTxRate(ForcedDataRate); + + if (pHalData->rf_chip >= RF_TYPE_MAX) + RTW_INFO("This RF chip ID is not supported\n"); + + switch (ulAntennaTx) { + case ANTENNA_A: + pMptCtx->mpt_rf_path = RF_PATH_A; + TxAntToPhyDm = BB_PATH_A; + break; + case ANTENNA_B: + pMptCtx->mpt_rf_path = RF_PATH_B; + TxAntToPhyDm = BB_PATH_B; + break; + case ANTENNA_AB: + pMptCtx->mpt_rf_path = RF_PATH_AB; + TxAntToPhyDm = (BB_PATH_A|BB_PATH_B); + break; + default: + pMptCtx->mpt_rf_path = RF_PATH_AB; + TxAntToPhyDm = (BB_PATH_A|BB_PATH_B); + break; + } + + switch (ulAntennaRx) { + case ANTENNA_A: + RxAntToPhyDm = BB_PATH_A; + break; + case ANTENNA_B: + RxAntToPhyDm = BB_PATH_B; + break; + case ANTENNA_AB: + RxAntToPhyDm = (BB_PATH_A|BB_PATH_B); + break; + default: + RxAntToPhyDm = (BB_PATH_A|BB_PATH_B); + break; + } + + config_phydm_trx_mode_8192f(GET_PDM_ODM(pAdapter), TxAntToPhyDm, RxAntToPhyDm, FALSE); + +} + +#endif void hal_mpt_SetAntenna(PADAPTER pAdapter) @@ -1471,6 +1552,14 @@ void hal_mpt_SetAntenna(PADAPTER pAdapter) return; } #endif + +#ifdef CONFIG_RTL8192F + if (IS_HARDWARE_TYPE_8192F(pAdapter)) { + mpt_set_rfpath_8192f(pAdapter); + return; + } +#endif + /* else if (IS_HARDWARE_TYPE_8821B(pAdapter)) mpt_SetRFPath_8821B(pAdapter); Prepare for 8822B @@ -1509,7 +1598,7 @@ s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther) void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03); } @@ -1517,13 +1606,12 @@ void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter) u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter) { - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(pAdapter); - struct PHY_DM_STRUCT *p_dm_odm = &hal_data->odmpriv; + struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter); u32 ThermalValue = 0; s32 thermal_value_temp = 0; s8 thermal_offset = 0; - ThermalValue = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/ + ThermalValue = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/ thermal_offset = phydm_get_thermal_offset(p_dm_odm); thermal_value_temp = ThermalValue + thermal_offset; @@ -1604,23 +1692,24 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; u4Byte ulAntennaTx = pHalData->antenna_tx_path; static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0; u8 rfPath; switch (ulAntennaTx) { case ANTENNA_B: - rfPath = ODM_RF_PATH_B; + rfPath = RF_PATH_B; break; case ANTENNA_C: - rfPath = ODM_RF_PATH_C; + rfPath = RF_PATH_C; break; case ANTENNA_D: - rfPath = ODM_RF_PATH_D; + rfPath = RF_PATH_D; break; case ANTENNA_A: default: - rfPath = ODM_RF_PATH_A; + rfPath = RF_PATH_A; break; } @@ -1630,7 +1719,7 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/ if (IS_HARDWARE_TYPE_8188E(pAdapter)) { regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0); phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0); } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/ @@ -1638,41 +1727,53 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF); phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + } else if (IS_HARDWARE_TYPE_8192F(pAdapter)) { /* USB need to do RF LO disable first, PCIE isn't required to follow this order.*/ + #ifdef CONFIG_RTL8192F + phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x1); + phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x1); + phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x1); + phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x1); + phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x1); + phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x1); + phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0xF); + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x1); /* RF LO disabled*/ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /* Tx mode*/ +#endif } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/ + if (pMptCtx->mpt_rf_path == RF_PATH_A) { + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/ } else { /*/ S0/S1 both use PATH A to configure*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/ } } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */ + if (pMptCtx->mpt_rf_path == RF_PATH_A) { + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */ } - } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { + } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) { /*Set BB REG 88C: Prevent SingleTone Fail*/ phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF); phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + if (pMptCtx->mpt_rf_path == RF_PATH_A) { phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x1); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1); } else {/* S0/S1 both use PATH A to configure */ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x1); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1); } - } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) { -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) - u1Byte p = ODM_RF_PATH_A; + } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) { +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) + u1Byte p = RF_PATH_A; - regRF = phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask); + regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask); regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord); regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord); regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord); @@ -1680,8 +1781,8 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/ - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_AB) { - for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) { + if (pMptCtx->mpt_rf_path == RF_PATH_AB) { + for (p = RF_PATH_A; p <= RF_PATH_B; ++p) { phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ @@ -1689,26 +1790,49 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) } else { phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ - phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ +#ifdef CONFIG_RTL8821C + if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG) + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */ + else +#endif + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ } - - phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ - phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ - - if (pHalData->external_pa_5g) { - phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/ - phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/ - } else if (pHalData->ExternalPA_2G) { - phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/ - phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/ + if (IS_HARDWARE_TYPE_8822B(pAdapter)) { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xCB0=0x77777777*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xEB0=0x77777777*/ + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xCB4[15:0] = 0x7777*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xEB4[15:0] = 0x7777*/ + phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/ + phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/ + } else if (IS_HARDWARE_TYPE_8821C(pAdapter)) { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707); /* 0xCB0[[15:12, 7:4] = 0x707*/ + + if (pHalData->external_pa_5g) + { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/ + } + else if (pHalData->ExternalPA_2G) + { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/ + } + } else { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ + + if (pHalData->external_pa_5g) { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/ + } else if (pHalData->ExternalPA_2G) { + phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/ + phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/ + } } #endif } -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821C) - else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) +#if defined(CONFIG_RTL8814A) + else if (IS_HARDWARE_TYPE_8814A(pAdapter)) mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE); #endif - else /*/ Turn On SingleTone and turn off the other test modes.*/ phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone); @@ -1718,7 +1842,7 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) } else {/*/ Stop Single Ton e.*/ if (IS_HARDWARE_TYPE_8188E(pAdapter)) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF); + phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF); phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1); phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1); } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { @@ -1726,48 +1850,65 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */ /*/ RESTORE MAC REG 88C: Enable RF Functions*/ phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0); + } else if (IS_HARDWARE_TYPE_8192F(pAdapter)){ +#ifdef CONFIG_RTL8192F + phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT23, 0x0); + phy_set_mac_reg(pAdapter, REG_LEDCFG0_8192F, BIT26, 0x0); + phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT7, 0x0); + phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT1, 0x0); + phy_set_mac_reg(pAdapter, REG_PAD_CTRL1_8192F, BIT0, 0x0); + phy_set_mac_reg(pAdapter, REG_AFE_CTRL_4_8192F, BIT16, 0x0); + phy_set_bb_reg(pAdapter, 0x88C, 0xF00000, 0x0); + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x57, BIT1, 0x0); /* RF LO disabled*/ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /* Rx mode*/ +#endif } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/ + if (pMptCtx->mpt_rf_path == RF_PATH_A) { + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/ } else { /*/ S0/S1 both use PATH A to configure*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/ } } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */ - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */ + if (pMptCtx->mpt_rf_path == RF_PATH_A) { + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */ + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */ } - } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { + } else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8188GTV(pAdapter)) { phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/ /*Set BB REG 88C: Prevent SingleTone Fail*/ phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc); } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) { - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + if (pMptCtx->mpt_rf_path == RF_PATH_A) { phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x0); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0); } else { /* S0/S1 both use PATH A to configure */ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1); - phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x0); + phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1); + phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0); } - } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) { -#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) - u1Byte p = ODM_RF_PATH_A; + } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) { +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) + u1Byte p = RF_PATH_A; phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/ - if (pMptCtx->mpt_rf_path == ODM_RF_PATH_AB) { - for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) { + if (pMptCtx->mpt_rf_path == RF_PATH_AB) { + for (p = RF_PATH_A; p <= RF_PATH_B; ++p) { phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF); phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/ } } else { + p = pMptCtx->mpt_rf_path; phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF); + + if (IS_HARDWARE_TYPE_8821C(pAdapter)) + phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */ + phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/ } @@ -1775,10 +1916,16 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1); phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2); phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3); + + if (IS_HARDWARE_TYPE_8822B(pAdapter)) { + RTW_INFO("Restore RFE control Pin cbc\n"); + phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0); + phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0); + } #endif } -#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) - else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) +#if defined(CONFIG_RTL8814A) + else if (IS_HARDWARE_TYPE_8814A(pAdapter)) mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE); else/*/ Turn off all test modes.*/ @@ -2007,12 +2154,10 @@ static VOID mpt_StartOfdmContTx( void mpt_ProSetPMacTx(PADAPTER Adapter) { PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); + struct mp_priv *pmppriv = &Adapter->mppriv; RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; u32 u4bTmp; - dbg_print("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound); - dbg_print("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount, - PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern); #if 0 PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3); PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6); @@ -2021,46 +2166,61 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC); PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4); - PRINT_DATA("Src Address", Adapter->mac_addr, 6); - PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, 6); + PRINT_DATA("Src Address", Adapter->mac_addr, ETH_ALEN); + PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, ETH_ALEN); #endif + if (pmppriv->pktInterval != 0) + PMacTxInfo.PacketPeriod = pmppriv->pktInterval; + + if (pmppriv->tx.count != 0) + PMacTxInfo.PacketCount = pmppriv->tx.count; + + RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound); + RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount, + PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern); if (PMacTxInfo.bEnPMacTx == FALSE) { - if (PMacTxInfo.Mode == CONTINUOUS_TX) { + if (pMptCtx->HWTxmode == CONTINUOUS_TX) { phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/ - if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) mpt_StopCckContTx(Adapter); else mpt_StopOfdmContTx(Adapter); - } else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) { + } else if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) { u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord); phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50); phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/ } else phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/ - if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) { + if (pMptCtx->HWTxmode == OFDM_Single_Tone_TX) { /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/ - if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + if (IS_MPT_CCK_RATE(pMptCtx->mpt_rate_index)) mpt_StopCckContTx(Adapter); else mpt_StopOfdmContTx(Adapter); mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE); } - + pMptCtx->HWTxmode = TEST_NONE; return; } + pMptCtx->mpt_rate_index = PMacTxInfo.TX_RATE; + if (PMacTxInfo.Mode == CONTINUOUS_TX) { + pMptCtx->HWTxmode = CONTINUOUS_TX; PMacTxInfo.PacketCount = 1; + hal_mpt_SetTxPower(Adapter); + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) mpt_StartCckContTx(Adapter); else mpt_StartOfdmContTx(Adapter); } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) { /* Continuous TX -> HW TX -> RF Setting */ + pMptCtx->HWTxmode = OFDM_Single_Tone_TX; PMacTxInfo.PacketCount = 1; if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) @@ -2068,6 +2228,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) else mpt_StartOfdmContTx(Adapter); } else if (PMacTxInfo.Mode == PACKETS_TX) { + pMptCtx->HWTxmode = PACKETS_TX; if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0) PMacTxInfo.PacketCount = 0xffff; } @@ -2174,7 +2335,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8); phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp); - if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) { + if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) { u4Byte offset = 0xb44; if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE)) @@ -2183,6 +2344,16 @@ void mpt_ProSetPMacTx(PADAPTER Adapter) phy_set_bb_reg(Adapter, offset, 0xc0000000, 1); else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) phy_set_bb_reg(Adapter, offset, 0xc0000000, 2); + + } else if(IS_HARDWARE_TYPE_JAGUAR(Adapter)) { + u4Byte offset = 0xb4c; + + if(IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE)) + phy_set_bb_reg(Adapter, offset, 0xc0000000, 0); + else if(IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) + phy_set_bb_reg(Adapter, offset, 0xc0000000, 1); + else if(IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) + phy_set_bb_reg(Adapter, offset, 0xc0000000, 2); } phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/ @@ -2204,8 +2375,7 @@ void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart) { u8 Rate; - RT_TRACE(_module_mp_, _drv_info_, - ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx)); + RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx); Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx); pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart; diff --git a/hal/hal_phy.c b/hal/hal_phy.c index 5c87dbb..1504a73 100644 --- a/hal/hal_phy.c +++ b/hal/hal_phy.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,22 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HAL_PHY_C_ #include -/* ******************************************************************************** - * Constant. - * ******************************************************************************** - * 2008/11/20 MH For Debug only, RF */ -static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; - /** * Function: PHY_CalculateBitShift * @@ -54,6 +43,13 @@ PHY_CalculateBitShift( } +#ifdef CONFIG_RF_SHADOW_RW +/* ******************************************************************************** + * Constant. + * ******************************************************************************** + * 2008/11/20 MH For Debug only, RF */ +static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; + /* * ==> RF shadow Operation API Code Section!!! * @@ -85,7 +81,7 @@ PHY_CalculateBitShift( u32 PHY_RFShadowRead( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset) { return RF_Shadow[eRFPath][Offset].Value; @@ -96,7 +92,7 @@ PHY_RFShadowRead( VOID PHY_RFShadowWrite( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u32 Data) { @@ -109,7 +105,7 @@ PHY_RFShadowWrite( BOOLEAN PHY_RFShadowCompare( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset) { u32 reg; @@ -130,7 +126,7 @@ PHY_RFShadowCompare( VOID PHY_RFShadowRecorver( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset) { /* Check if the address is error */ @@ -149,7 +145,7 @@ VOID PHY_RFShadowCompareAll( IN PADAPTER Adapter) { - u8 eRFPath = 0 ; + enum rf_path eRFPath = RF_PATH_A; u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter); for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) { @@ -164,7 +160,7 @@ VOID PHY_RFShadowRecorverAll( IN PADAPTER Adapter) { - u8 eRFPath = 0; + enum rf_path eRFPath = RF_PATH_A; u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter); for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) { @@ -178,7 +174,7 @@ PHY_RFShadowRecorverAll( VOID PHY_RFShadowCompareFlagSet( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u8 Type) { @@ -191,7 +187,7 @@ PHY_RFShadowCompareFlagSet( VOID PHY_RFShadowRecorverFlagSet( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u8 Type) { @@ -205,7 +201,7 @@ VOID PHY_RFShadowCompareFlagSetAll( IN PADAPTER Adapter) { - u8 eRFPath = 0; + enum rf_path eRFPath = RF_PATH_A; u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter); for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) { @@ -225,7 +221,7 @@ VOID PHY_RFShadowRecorverFlagSetAll( IN PADAPTER Adapter) { - u8 eRFPath = 0; + enum rf_path eRFPath = RF_PATH_A; u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter); for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) { @@ -244,7 +240,7 @@ VOID PHY_RFShadowRefresh( IN PADAPTER Adapter) { - u8 eRFPath = 0; + enum rf_path eRFPath = RF_PATH_A; u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter); for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) { @@ -258,3 +254,4 @@ PHY_RFShadowRefresh( } } /* PHY_RFShadowRead */ +#endif /*CONFIG_RF_SHADOW_RW*/ diff --git a/hal/halmac/halmac_2_platform.h b/hal/halmac/halmac_2_platform.h index 8efe01d..ef57868 100644 --- a/hal/halmac/halmac_2_platform.h +++ b/hal/halmac/halmac_2_platform.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2018 Realtek Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * ******************************************************************************/ + #ifndef _HALMAC_2_PLATFORM_H_ #define _HALMAC_2_PLATFORM_H_ @@ -32,20 +28,18 @@ #include /* __BIG_ENDIAN, __LITTLE_ENDIAN, _sema, _mutex */ #endif -/*[Driver] provide the define of _TRUE, _FALSE, NULL, u8, u16, u32*/ +/*[Driver] provide the define of NULL, u8, u16, u32*/ #ifndef NULL #define NULL ((void *)0) #endif #define HALMAC_INLINE inline -typedef u8 *pu8; -typedef u16 *pu16; -typedef u32 *pu32; -typedef s8 *ps8; -typedef s16 *ps16; -typedef s32 *ps32; - +/* + * Ignore following typedef because Linux already have these + * u8, u16, u32, s8, s16, s32 + * __le16, __le32, __be16, __be32 + */ #define HALMAC_PLATFORM_LITTLE_ENDIAN 1 #define HALMAC_PLATFORM_BIG_ENDIAN 0 @@ -70,9 +64,20 @@ typedef s32 *ps32; /*[Driver] config if enable the dbg msg or notl*/ #define HALMAC_DBG_MSG_ENABLE 1 +#define HALMAC_MSG_LEVEL_TRACE 3 +#define HALMAC_MSG_LEVEL_WARNING 2 +#define HALMAC_MSG_LEVEL_ERR 1 +#define HALMAC_MSG_LEVEL_NO_LOG 0 +/*[Driver] config halmac msg level + * Use HALMAC_MSG_LEVEL_XXXX + */ +#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE + /*[Driver] define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */ /*Should be 8 Byte alignment*/ -#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 48 /*Bytes*/ +#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 80 /*Bytes*/ + +#define HALMAC_USE_TYPEDEF 0 /*[Driver] provide the type mutex*/ /* Mutex type */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h index 7ad613c..7506209 100644 --- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h @@ -1,85 +1,65 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_8821C_CFG_H_ #define _HALMAC_8821C_CFG_H_ -#include "halmac_8821c_pwr_seq.h" -#include "halmac_api_8821c.h" -#include "halmac_api_8821c_usb.h" -#include "halmac_api_8821c_pcie.h" -#include "halmac_api_8821c_sdio.h" -#include "../../halmac_bit2.h" -#include "../../halmac_reg2.h" -#include "../../halmac_api.h" - -#if HALMAC_PLATFORM_TESTPROGRAM -#include "halmisc_api_8821c.h" -#include "halmisc_api_8821c_usb.h" -#include "halmisc_api_8821c_sdio.h" -#include "halmisc_api_8821c_pcie.h" -#endif - -#define HALMAC_TX_FIFO_SIZE_8821C 65536 /* 64k */ -#define HALMAC_TX_FIFO_SIZE_LA_8821C 32768 /* 32k */ -#define HALMAC_RX_FIFO_SIZE_8821C 16384 /* 16k */ -#define HALMAC_TX_PAGE_SIZE_8821C 128 /* PageSize 128Byte */ -#define HALMAC_TX_ALIGN_SIZE_8821C 8 -#define HALMAC_TX_PAGE_SIZE_2_POWER_8821C 7 /* 128 = 2^7 */ -#define HALMAC_SECURITY_CAM_ENTRY_NUM_8821C 64 /* CAM Entry Size */ -#define HALMAC_TX_DESC_SIZE_8821C 48 -#define HALMAC_RX_DESC_SIZE_8821C 24 -#define HALMAC_C2H_PKT_BUF_8821C 256 +#include "../../halmac_hw_cfg.h" +#include "../halmac_88xx_cfg.h" -#define HALMAC_RX_FIFO_EXPANDING_UNIT_8821C (HALMAC_RX_DESC_SIZE_8821C + HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE) /* should be 8 Byte alignment*/ -#define HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8821C (HALMAC_RX_DESC_SIZE_8821C + HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_88XX) /* should be 8 Byte alignment*/ -#define HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C 32768 /* 32k */ -#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C ((((HALMAC_RX_FIFO_EXPANDING_UNIT_8821C << 8) - 1) >> 10) << 10) /* < 48k*/ -#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8821C ((((HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8821C << 8) - 1) >> 10) << 10) /* 45k < 48k*/ +#if HALMAC_8821C_SUPPORT -#define HALMAC_EFUSE_SIZE_8821C 512 /* 0x2000 */ -#define HALMAC_EEPROM_SIZE_8821C 0x200 -#define HALMAC_BT_EFUSE_SIZE_8821C 128 +#define TX_FIFO_SIZE_8821C 65536 +#define RX_FIFO_SIZE_8821C 16384 +#define TRX_SHARE_SIZE_8821C 32768 -#define HALMAC_CR_TRX_ENABLE_8821C (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ - BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ - BIT_MACTXEN | BIT_MACRXEN) +#define RX_DESC_DUMMY_SIZE_8821C 72 /* 8 * 9 Bytes */ +#define RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8821C 80 /* 8 Byte alignment*/ -#define HALMAC_BLK_DESC_NUM_8821C 0x3 /* Only for USB */ - -/* AMPDU max time (unit : 32us) */ -#define HALMAC_AMPDU_MAX_TIME_8821C 0x70 - -/* Protect mode control */ -#define HALMAC_PROT_RTS_LEN_TH_8821C 0xFF -#define HALMAC_PROT_RTS_TX_TIME_TH_8821C 0x08 -#define HALMAC_PROT_MAX_AGG_PKT_LIMIT_8821C 0x10 -#define HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8821C 0x10 -#define HALMAC_PROT_MAX_AGG_PKT_LIMIT_8821C_SDIO 0x2B -#define HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8821C_SDIO 0x2B +/* should be 8 Byte alignment*/ +#if (HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE <= \ + RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8821C) +#define RX_FIFO_EXPANDING_UNIT_8821C (RX_DESC_SIZE_88XX + \ + RX_DESC_DUMMY_SIZE_8821C + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE) +#else +#define RX_FIFO_EXPANDING_UNIT_8821C (RX_DESC_SIZE_88XX + \ + RX_DESC_DUMMY_SIZE_8821C + RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8821C) +#endif -/* Fast EDCA setting */ -#define HALMAC_FAST_EDCA_VO_TH_8821C 0x06 -#define HALMAC_FAST_EDCA_VI_TH_8821C 0x06 -#define HALMAC_FAST_EDCA_BE_TH_8821C 0x06 -#define HALMAC_FAST_EDCA_BK_TH_8821C 0x06 +#define TX_FIFO_SIZE_LA_8821C (TX_FIFO_SIZE_8821C >> 1) +#define TX_FIFO_SIZE_RX_EXPAND_1BLK_8821C \ + (TX_FIFO_SIZE_8821C - TRX_SHARE_SIZE_8821C) +#define RX_FIFO_SIZE_RX_EXPAND_1BLK_8821C \ + ((((RX_FIFO_EXPANDING_UNIT_8821C << 8) - 1) >> 10) << 10) -/* BAR setting */ -#define HALMAC_BAR_RETRY_LIMIT_8821C 0x01 -#define HALMAC_RA_TRY_RATE_AGG_LIMIT_8821C 0x08 +#define EFUSE_SIZE_8821C 512 +#define EEPROM_SIZE_8821C 512 +#define BT_EFUSE_SIZE_8821C 128 -typedef enum _HALMAC_NORMAL_RXAGG_TH_TO_8821C { - HALMAC_NORMAL_RXAGG_THRESHOLD_8821C = 0xFF, - HALMAC_NORMAL_RXAGG_TIMEOUT_8821C = 0x01, -} HALMAC_NORMAL_RXAGG_TH_TO_8821C; +#define SEC_CAM_NUM_8821C 64 -typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO_8821C { - HALMAC_LOOPBACK_RXAGG_THRESHOLD_8821C = 0xFF, - HALMAC_LOOPBACK_RXAGG_TIMEOUT_8821C = 0x01, -} HALMAC_LOOPBACK_RXAGG_TH_TO_8821C; +#define OQT_ENTRY_AC_8821C 32 +#define OQT_ENTRY_NOAC_8821C 32 +#define MACID_MAX_8821C 128 -#define HALMAC_RSVD_DRV_PGNUM_8821C 16 /*2048*/ -#define HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8821C 32 /*4096*/ -#define HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C 8 /*1024*/ -#define HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8821C 0 /*0*/ -#define HALMAC_RSVD_FW_TXBUFF_PGNUM_8821C 4 /*512*/ +#define WLAN_FW_IRAM_MAX_SIZE_8821C 65536 +#define WLAN_FW_DRAM_MAX_SIZE_8821C 49152 +#define WLAN_FW_ERAM_MAX_SIZE_8821C 49152 +#define WLAN_FW_MAX_SIZE_8821C (WLAN_FW_IRAM_MAX_SIZE_8821C + \ + WLAN_FW_DRAM_MAX_SIZE_8821C + WLAN_FW_ERAM_MAX_SIZE_8821C) +#endif /* HALMAC_8821C_SUPPORT */ #endif diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.c b/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.c new file mode 100644 index 0000000..dcfd796 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.c @@ -0,0 +1,145 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_cfg_wmac_8821c.h" +#include "halmac_8821c_cfg.h" + +#if HALMAC_8821C_SUPPORT + +/** + * cfg_drv_info_8821c() - config driver info + * @adapter : the adapter of halmac + * @drv_info : driver information selection + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_drv_info_8821c(struct halmac_adapter *adapter, + enum halmac_drv_info drv_info) +{ + u8 drv_info_size = 0; + u8 phy_status_en = 0; + u8 sniffer_en = 0; + u8 plcp_hdr_en = 0; + u8 value8; + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]drv info = %d\n", drv_info); + + switch (drv_info) { + case HALMAC_DRV_INFO_NONE: + drv_info_size = 0; + phy_status_en = 0; + sniffer_en = 0; + plcp_hdr_en = 0; + break; + case HALMAC_DRV_INFO_PHY_STATUS: + drv_info_size = 4; + phy_status_en = 1; + sniffer_en = 0; + plcp_hdr_en = 0; + break; + case HALMAC_DRV_INFO_PHY_SNIFFER: + drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */ + phy_status_en = 1; + sniffer_en = 1; + plcp_hdr_en = 0; + break; + case HALMAC_DRV_INFO_PHY_PLCP: + drv_info_size = 6; /* phy status 4byte, plcp header 2byte */ + phy_status_en = 1; + sniffer_en = 0; + plcp_hdr_en = 1; + break; + default: + return HALMAC_RET_SW_CASE_NOT_SUPPORT; + } + + if (adapter->txff_alloc.rx_fifo_exp_mode != + HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) + drv_info_size = RX_DESC_DUMMY_SIZE_8821C >> 3; + + HALMAC_REG_W8(REG_RX_DRVINFO_SZ, drv_info_size); + + value8 = HALMAC_REG_R8(REG_TRXFF_BNDY + 1); + value8 &= 0xF0; + /* For rxdesc len = 0 issue */ + value8 |= 0xF; + HALMAC_REG_W8(REG_TRXFF_BNDY + 1, value8); + + adapter->drv_info_size = drv_info_size; + + value32 = HALMAC_REG_R32(REG_RCR); + value32 = (value32 & (~BIT_APP_PHYSTS)); + if (phy_status_en == 1) + value32 = value32 | BIT_APP_PHYSTS; + HALMAC_REG_W32(REG_RCR, value32); + + value32 = HALMAC_REG_R32(REG_WMAC_OPTION_FUNCTION + 4); + value32 = (value32 & (~(BIT(8) | BIT(9)))); + if (sniffer_en == 1) + value32 = value32 | BIT(9); + if (plcp_hdr_en == 1) + value32 = value32 | BIT(8); + HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 4, value32); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_low_pwr_8821c() - config WMAC register + * @adapter + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_low_pwr_8821c(struct halmac_adapter *adapter) +{ + return HALMAC_RET_SUCCESS; +} + +void +cfg_rx_ignore_8821c(struct halmac_adapter *adapter, + struct halmac_mac_rx_ignore_cfg *cfg) +{ +} + +enum halmac_ret_status +cfg_ampdu_8821c(struct halmac_adapter *adapter, + struct halmac_ampdu_config *cfg) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (cfg->ht_max_len != cfg->vht_max_len) { + PLTFM_MSG_ERR("[ERR]max len ht != vht!!\n"); + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + HALMAC_REG_W8(REG_PROT_MODE_CTRL + 2, cfg->max_agg_num); + HALMAC_REG_W8(REG_PROT_MODE_CTRL + 3, cfg->max_agg_num); + + if (cfg->max_len_en == 1) + HALMAC_REG_W32(REG_AMPDU_MAX_LENGTH, cfg->ht_max_len); + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_8821C_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.h new file mode 100644 index 0000000..093fd29 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_cfg_wmac_8821c.h @@ -0,0 +1,40 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_CFG_WMAC_8821C_H_ +#define _HALMAC_CFG_WMAC_8821C_H_ + +#include "../../halmac_api.h" + +#if HALMAC_8821C_SUPPORT + +enum halmac_ret_status +cfg_drv_info_8821c(struct halmac_adapter *adapter, + enum halmac_drv_info drv_info); + +enum halmac_ret_status +init_low_pwr_8821c(struct halmac_adapter *adapter); + +void +cfg_rx_ignore_8821c(struct halmac_adapter *adapter, + struct halmac_mac_rx_ignore_cfg *cfg); + +enum halmac_ret_status +cfg_ampdu_8821c(struct halmac_adapter *adapter, + struct halmac_ampdu_config *cfg); + +#endif/* HALMAC_8821C_SUPPORT */ + +#endif/* _HALMAC_CFG_WMAC_8821C_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.c b/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.c new file mode 100644 index 0000000..43ae23e --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.c @@ -0,0 +1,182 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_8821c_cfg.h" +#include "halmac_common_8821c.h" +#include "../halmac_common_88xx.h" +#include "halmac_cfg_wmac_8821c.h" +#if HALMAC_PCIE_SUPPORT +#include "halmac_pcie_8821c.h" +#endif + +#if HALMAC_8821C_SUPPORT + +static void +cfg_ldo25_8821c(struct halmac_adapter *adapter, u8 enable); + +/** + * get_hw_value_8821c() -get hw config value + * @adapter : the adapter of halmac + * @hw_id : hw id for driver to query + * @value : hw value, reference table to get data type + * Author : KaiYuan Chang / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_hw_value_8821c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!value) { + PLTFM_MSG_ERR("[ERR]null pointer\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (get_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS) + return HALMAC_RET_SUCCESS; + + switch (hw_id) { + case HALMAC_HW_FW_MAX_SIZE: + *(u32 *)value = WLAN_FW_MAX_SIZE_8821C; + break; + case HALMAC_HW_SDIO_INT_LAT: + break; + case HALMAC_HW_SDIO_CLK_CNT: + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * set_hw_value_8821c() -set hw config value + * @adapter : the adapter of halmac + * @hw_id : hw id for driver to config + * @value : hw value, reference table to get data type + * Author : KaiYuan Chang / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +set_hw_value_8821c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!value) { + PLTFM_MSG_ERR("[ERR]null pointer\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (set_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS) + return HALMAC_RET_SUCCESS; + + switch (hw_id) { + case HALMAC_HW_AMPDU_CONFIG: + status = cfg_ampdu_8821c(adapter, + (struct halmac_ampdu_config *)value); + break; + case HALMAC_HW_SDIO_TX_FORMAT: + break; + case HALMAC_HW_RXGCK_FIFO: + break; + case HALMAC_HW_RX_IGNORE: + break; + case HALMAC_HW_LDO25_EN: + cfg_ldo25_8821c(adapter, *(u8 *)value); + break; +#if HALMAC_PCIE_SUPPORT + case HALMAC_HW_PCIE_REF_AUTOK: + if (adapter->intf != HALMAC_INTERFACE_PCIE) + return HALMAC_RET_WRONG_INTF; + status = auto_refclk_cal_8821c_pcie(adapter); + if (status != HALMAC_RET_SUCCESS) + return status; + break; +#endif + case HALMAC_HW_SDIO_WT_EN: + break; + case HALMAC_HW_SDIO_CLK_MONITOR: + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +/** + * halmac_fill_txdesc_check_sum_88xx() - fill in tx desc check sum + * @adapter : the adapter of halmac + * @txdesc : tx desc packet + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +fill_txdesc_check_sum_8821c(struct halmac_adapter *adapter, u8 *txdesc) +{ + __le16 chksum = 0; + __le16 *data; + u32 i; + + if (!txdesc) { + PLTFM_MSG_ERR("[ERR]null pointer\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (adapter->tx_desc_checksum != 1) + PLTFM_MSG_TRACE("[TRACE]chksum disable\n"); + + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000); + + data = (__le16 *)(txdesc); + + /* HW clculates only 32byte */ + for (i = 0; i < 8; i++) + chksum ^= (*(data + 2 * i) ^ *(data + (2 * i + 1))); + + /* *(data + 2 * i) & *(data + (2 * i + 1) have endain issue*/ + /* Process eniadn issue after checksum calculation */ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, rtk_le16_to_cpu(chksum)); + + return HALMAC_RET_SUCCESS; +} + +static void +cfg_ldo25_8821c(struct halmac_adapter *adapter, u8 enable) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 3); + + if (enable == 1) + HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 | BIT(7))); + else + HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 & ~BIT(7))); +} + +#endif /* HALMAC_8821C_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.h new file mode 100644 index 0000000..eb1f8f8 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_common_8821c.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_COMMON_8821C_H_ +#define _HALMAC_COMMON_8821C_H_ + +#include "../../halmac_api.h" + +#if HALMAC_8821C_SUPPORT + +enum halmac_ret_status +get_hw_value_8821c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value); + +enum halmac_ret_status +set_hw_value_8821c(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value); + +enum halmac_ret_status +fill_txdesc_check_sum_8821c(struct halmac_adapter *adapter, u8 *txdesc); + +#endif/* HALMAC_8821C_SUPPORT */ + +#endif/* _HALMAC_COMMON_8821C_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.c b/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.c new file mode 100644 index 0000000..8a153fd --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.c @@ -0,0 +1,846 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_gpio_8821c.h" +#include "../halmac_gpio_88xx.h" + +#if HALMAC_8821C_SUPPORT + +/* P_LED0 definition */ +#define GPIO0_BT_GPIO0_8821C \ + {HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(2), BIT(2)} +#define GPIO0_BT_GPIO0_8821C \ + {HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(2), BIT(2)} +#define GPIO0_BT_ACT_8821C \ + {HALMAC_BT_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \ + 0x41, BIT(1), 0} +#define GPIO0_WL_ACT_8821C \ + {HALMAC_WL_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO0_WLMAC_DBG_GPIO0_8821C \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO0_WLPHY_DBG_GPIO0_8821C \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO0_BT_DBG_GPIO0_8821C \ + {HALMAC_BT_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO0_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO1 definition */ +#define GPIO1_BT_GPIO1_8821C \ + {HALMAC_BT_GPIO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(2), BIT(2)} +#define GPIO1_BT_3DD_SYNC_A_8821C \ + {HALMAC_BT_3DDLS_A, HALMAC_GPIO1, HALMAC_GPIO_IN, \ + 0x66, BIT(2), BIT(2)} +#define GPIO1_WL_CK_8821C \ + {HALMAC_BT_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \ + 0x41, BIT(1), 0} +#define GPIO1_BT_CK_8821C \ + {HALMAC_WL_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO1_WLMAC_DBG_GPIO1_8821C \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO1_WLPHY_DBG_GPIO1_8821C \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO1_BT_DBG_GPIO1_8821C \ + {HALMAC_BT_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO1_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO2 definition */ +#define GPIO2_BT_GPIO2_8821C \ + {HALMAC_BT_GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(2), BIT(2)} +#define GPIO2_WL_STATE_8821C \ + {HALMAC_BT_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \ + 0x41, BIT(1), 0} +#define GPIO2_BT_STATE_8821C \ + {HALMAC_WL_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO2_WLMAC_DBG_GPIO2_8821C \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO2_WLPHY_DBG_GPIO2_8821C \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO2_BT_DBG_GPIO2_8821C \ + {HALMAC_BT_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO2_RFE_CTRL_5_8821C \ + {HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(2), BIT(2)} +#define GPIO2_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO3 definition */ +#define GPIO3_BT_GPIO3_8821C \ + {HALMAC_BT_GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(2), BIT(2)} +#define GPIO3_WL_PRI_8821C \ + {HALMAC_BT_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \ + 0x41, BIT(1), 0} +#define GPIO3_BT_PRI_8821C \ + {HALMAC_WL_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \ + 0x41, BIT(2), BIT(2)} +#define GPIO3_WLMAC_DBG_GPIO3_8821C \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO3_WLPHY_DBG_GPIO3_8821C \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO3_BT_DBG_GPIO3_8821C \ + {HALMAC_BT_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO3_RFE_CTRL_4_8821C \ + {HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(2), BIT(2)} +#define GPIO3_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO4 definition */ +#define GPIO4_BT_SPI_D0_8821C \ + {HALMAC_BT_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO4_WL_SPI_D0_8821C \ + {HALMAC_WL_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO4_SDIO_INT_8821C \ + {HALMAC_SDIO_INT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \ + 0x72, BIT(2), BIT(2)} +#define GPIO4_JTAG_TRST_8821C \ + {HALMAC_JTAG, HALMAC_GPIO4, HALMAC_GPIO_IN, \ + 0x67, BIT(0), BIT(0)} +#define GPIO4_DBG_GNT_WL_8821C \ + {HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \ + 0x73, BIT(3), BIT(3)} +#define GPIO4_WLMAC_DBG_GPIO4_8821C \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO4_WLPHY_DBG_GPIO4_8821C \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO4_BT_DBG_GPIO4_8821C \ + {HALMAC_BT_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO4_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO5 definition */ +#define GPIO5_BT_SPI_D1_8821C \ + {HALMAC_BT_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO5_WL_SPI_D1_8821C \ + {HALMAC_WL_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO5_JTAG_TDI_8821C \ + {HALMAC_JTAG, HALMAC_GPIO5, HALMAC_GPIO_IN, \ + 0x67, BIT(0), BIT(0)} +#define GPIO5_DBG_GNT_BT_8821C \ + {HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO5, HALMAC_GPIO_OUT, \ + 0x73, BIT(3), BIT(3)} +#define GPIO5_WLMAC_DBG_GPIO5_8821C \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO5_WLPHY_DBG_GPIO5_8821C \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO5_BT_DBG_GPIO5_8821C \ + {HALMAC_BT_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO5_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO6 definition */ +#define GPIO6_BT_SPI_D2_8821C \ + {HALMAC_BT_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO6_WL_SPI_D2_8821C \ + {HALMAC_WL_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO6_EEDO_8821C \ + {HALMAC_EEPROM, HALMAC_GPIO6, HALMAC_GPIO_IN, \ + 0x40, BIT(4), BIT(4)} +#define GPIO6_JTAG_TDO_8821C \ + {HALMAC_JTAG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \ + 0x67, BIT(0), BIT(0)} +#define GPIO6_BT_3DD_SYNC_B_8821C \ + {HALMAC_BT_3DDLS_B, HALMAC_GPIO6, HALMAC_GPIO_IN, \ + 0x67, BIT(1), BIT(1)} +#define GPIO6_BT_GPIO18_8821C \ + {HALMAC_BT_GPIO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \ + 0x67, BIT(1), BIT(1)} +#define GPIO6_SIN_8821C \ + {HALMAC_WL_UART, HALMAC_GPIO6, HALMAC_GPIO_IN, \ + 0x41, BIT(0), BIT(0)} +#define GPIO6_WLMAC_DBG_GPIO6_8821C \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO6_WLPHY_DBG_GPIO6_8821C \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO6_BT_DBG_GPIO6_8821C \ + {HALMAC_BT_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO6_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO7 definition */ +#define GPIO7_BT_SPI_D3_8821C \ + {HALMAC_BT_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \ + 0x66, BIT(4), BIT(4)} +#define GPIO7_WL_SPI_D3_8821C \ + {HALMAC_WL_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \ + 0x42, BIT(3), BIT(3)} +#define GPIO7_EEDI_8821C \ + {HALMAC_EEPROM, HALMAC_GPIO7, HALMAC_GPIO_OUT, \ + 0x40, BIT(4), BIT(4)} +#define GPIO7_JTAG_TMS_8821C \ + {HALMAC_JTAG, HALMAC_GPIO7, HALMAC_GPIO_IN, \ + 0x67, BIT(0), BIT(0)} +#define GPIO7_BT_GPIO16_8821C \ + {HALMAC_BT_GPIO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \ + 0x67, BIT(2), BIT(2)} +#define GPIO7_SOUT_8821C \ + {HALMAC_WL_UART, HALMAC_GPIO7, HALMAC_GPIO_OUT, \ + 0x41, BIT(0), BIT(0)} +#define GPIO7_WLMAC_DBG_GPIO7_8821C \ + {HALMAC_WLMAC_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0)} +#define GPIO7_WLPHY_DBG_GPIO7_8821C \ + {HALMAC_WLPHY_DBG, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(1)} +#define GPIO7_BT_DBG_GPIO7_8821C \ + {HALMAC_BT_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \ + 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)} +#define GPIO7_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO8 definition */ +#define GPIO8_WL_EXT_WOL_8821C \ + {HALMAC_WL_HW_EXTWOL, HALMAC_GPIO8, HALMAC_GPIO_IN, \ + 0x4a, BIT(0) | BIT(1), BIT(0) | BIT(1)} +#define GPIO8_WL_LED_8821C \ + {HALMAC_WL_LED, HALMAC_GPIO8, HALMAC_GPIO_OUT, \ + 0x4e, BIT(5), BIT(5)} +#define GPIO8_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO8, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO9 definition */ +#define GPIO9_DIS_WL_N_8821C \ + {HALMAC_WL_HWPDN, HALMAC_GPIO9, HALMAC_GPIO_IN, \ + 0x68, BIT(3) | BIT(0), BIT(3) | BIT(0)} +#define GPIO9_WL_EXT_WOL_8821C \ + {HALMAC_WL_HW_EXTWOL, HALMAC_GPIO9, HALMAC_GPIO_IN, \ + 0x4a, BIT(0) | BIT(1), BIT(0)} +#define GPIO9_USCTS0_8821C \ + {HALMAC_UART0, HALMAC_GPIO9, HALMAC_GPIO_IN, \ + 0x66, BIT(6), BIT(6)} +#define GPIO9_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO9, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO10 definition */ +#define GPIO10_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO10, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO11 definition */ +#define GPIO11_DIS_BT_N_8821C \ + {HALMAC_BT_HWPDN, HALMAC_GPIO11, HALMAC_GPIO_IN, \ + 0x6a, BIT(0), BIT(0)} +#define GPIO11_USOUT0_8821C \ + {HALMAC_UART0, HALMAC_GPIO11, HALMAC_GPIO_OUT, \ + 0x66, BIT(6), BIT(6)} +#define GPIO11_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO11, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO12 definition */ +#define GPIO12_USIN0_8821C \ + {HALMAC_UART0, HALMAC_GPIO12, HALMAC_GPIO_IN, \ + 0x66, BIT(6), BIT(6)} +#define GPIO12_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO12, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO13 definition */ +#define GPIO13_BT_WAKE_8821C \ + {HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO13, HALMAC_GPIO_IN, \ + 0x4e, BIT(6), BIT(6)} +#define GPIO13_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO14 definition */ +#define GPIO14_UART_WAKE_8821C \ + {HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO14, HALMAC_GPIO_OUT, \ + 0x4e, BIT(6), BIT(6)} +#define GPIO14_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO14, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +/* GPIO15 definition */ +#define GPIO15_EXT_XTAL_8821C \ + {HALMAC_EXT_XTAL, HALMAC_GPIO15, HALMAC_GPIO_OUT, \ + 0x66, BIT(7), BIT(7)} +#define GPIO15_SW_IO_8821C \ + {HALMAC_SW_IO, HALMAC_GPIO15, HALMAC_GPIO_IN_OUT, \ + 0x40, BIT(1) | BIT(0), 0} + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO0_8821C[] = { + GPIO0_BT_GPIO0_8821C, + GPIO0_BT_ACT_8821C, + GPIO0_WL_ACT_8821C, + GPIO0_WLMAC_DBG_GPIO0_8821C, + GPIO0_WLPHY_DBG_GPIO0_8821C, + GPIO0_BT_DBG_GPIO0_8821C, + GPIO0_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO1_8821C[] = { + GPIO1_BT_GPIO1_8821C, + GPIO1_BT_3DD_SYNC_A_8821C, + GPIO1_WL_CK_8821C, + GPIO1_BT_CK_8821C, + GPIO1_WLMAC_DBG_GPIO1_8821C, + GPIO1_WLPHY_DBG_GPIO1_8821C, + GPIO1_BT_DBG_GPIO1_8821C, + GPIO1_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO2_8821C[] = { + GPIO2_BT_GPIO2_8821C, + GPIO2_WL_STATE_8821C, + GPIO2_BT_STATE_8821C, + GPIO2_WLMAC_DBG_GPIO2_8821C, + GPIO2_WLPHY_DBG_GPIO2_8821C, + GPIO2_BT_DBG_GPIO2_8821C, + GPIO2_RFE_CTRL_5_8821C, + GPIO2_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO3_8821C[] = { + GPIO3_BT_GPIO3_8821C, + GPIO3_WL_PRI_8821C, + GPIO3_BT_PRI_8821C, + GPIO3_WLMAC_DBG_GPIO3_8821C, + GPIO3_WLPHY_DBG_GPIO3_8821C, + GPIO3_BT_DBG_GPIO3_8821C, + GPIO3_RFE_CTRL_4_8821C, + GPIO3_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO4_8821C[] = { + GPIO4_BT_SPI_D0_8821C, + GPIO4_WL_SPI_D0_8821C, + GPIO4_SDIO_INT_8821C, + GPIO4_JTAG_TRST_8821C, + GPIO4_DBG_GNT_WL_8821C, + GPIO4_WLMAC_DBG_GPIO4_8821C, + GPIO4_WLPHY_DBG_GPIO4_8821C, + GPIO4_BT_DBG_GPIO4_8821C, + GPIO4_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO5_8821C[] = { + GPIO5_BT_SPI_D1_8821C, + GPIO5_WL_SPI_D1_8821C, + GPIO5_JTAG_TDI_8821C, + GPIO5_DBG_GNT_BT_8821C, + GPIO5_WLMAC_DBG_GPIO5_8821C, + GPIO5_WLPHY_DBG_GPIO5_8821C, + GPIO5_BT_DBG_GPIO5_8821C, + GPIO5_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO6_8821C[] = { + GPIO6_BT_SPI_D2_8821C, + GPIO6_WL_SPI_D2_8821C, + GPIO6_EEDO_8821C, + GPIO6_JTAG_TDO_8821C, + GPIO6_BT_3DD_SYNC_B_8821C, + GPIO6_BT_GPIO18_8821C, + GPIO6_SIN_8821C, + GPIO6_WLMAC_DBG_GPIO6_8821C, + GPIO6_WLPHY_DBG_GPIO6_8821C, + GPIO6_BT_DBG_GPIO6_8821C, + GPIO6_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO7_8821C[] = { + GPIO7_BT_SPI_D3_8821C, + GPIO7_WL_SPI_D3_8821C, + GPIO7_EEDI_8821C, + GPIO7_JTAG_TMS_8821C, + GPIO7_BT_GPIO16_8821C, + GPIO7_SOUT_8821C, + GPIO7_WLMAC_DBG_GPIO7_8821C, + GPIO7_WLPHY_DBG_GPIO7_8821C, + GPIO7_BT_DBG_GPIO7_8821C, + GPIO7_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO8_8821C[] = { + GPIO8_WL_EXT_WOL_8821C, + GPIO8_WL_LED_8821C, + GPIO8_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO9_8821C[] = { + GPIO9_DIS_WL_N_8821C, + GPIO9_WL_EXT_WOL_8821C, + GPIO9_USCTS0_8821C, + GPIO9_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO10_8821C[] = { + GPIO10_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO11_8821C[] = { + GPIO11_DIS_BT_N_8821C, + GPIO11_USOUT0_8821C, + GPIO11_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO12_8821C[] = { + GPIO12_USIN0_8821C, + GPIO12_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO13_8821C[] = { + GPIO13_BT_WAKE_8821C, + GPIO13_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO14_8821C[] = { + GPIO14_UART_WAKE_8821C, + GPIO14_SW_IO_8821C +}; + +static const struct halmac_gpio_pimux_list PINMUX_LIST_GPIO15_8821C[] = { + GPIO15_EXT_XTAL_8821C, + GPIO15_SW_IO_8821C +}; + +static enum halmac_ret_status +get_pinmux_list_8821c(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, + const struct halmac_gpio_pimux_list **list, + u32 *list_size, u32 *gpio_id); + +static enum halmac_ret_status +chk_pinmux_valid_8821c(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func); + +/** + * pinmux_get_func_8821c() -get current gpio status + * @adapter : the adapter of halmac + * @gpio_func : gpio function + * @enable : function is enable(1) or disable(0) + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pinmux_get_func_8821c(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, u8 *enable) +{ + u32 list_size; + u32 cur_func; + u32 gpio_id; + enum halmac_ret_status status; + const struct halmac_gpio_pimux_list *list = NULL; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = get_pinmux_list_8821c(adapter, gpio_func, &list, &list_size, + &gpio_id); + if (status != HALMAC_RET_SUCCESS) + return status; + + status = pinmux_parser_88xx(adapter, list, list_size, gpio_id, + &cur_func); + if (status != HALMAC_RET_SUCCESS) + return status; + + switch (gpio_func) { + case HALMAC_GPIO_FUNC_WL_LED: + *enable = (cur_func == HALMAC_WL_LED) ? 1 : 0; + break; + case HALMAC_GPIO_FUNC_SDIO_INT: + *enable = (cur_func == HALMAC_SDIO_INT) ? 1 : 0; + break; + case HALMAC_GPIO_FUNC_BT_HOST_WAKE1: + case HALMAC_GPIO_FUNC_BT_DEV_WAKE1: + *enable = (cur_func == HALMAC_GPIO13_14_WL_CTRL_EN) ? 1 : 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_0: + case HALMAC_GPIO_FUNC_SW_IO_1: + case HALMAC_GPIO_FUNC_SW_IO_2: + case HALMAC_GPIO_FUNC_SW_IO_3: + case HALMAC_GPIO_FUNC_SW_IO_4: + case HALMAC_GPIO_FUNC_SW_IO_5: + case HALMAC_GPIO_FUNC_SW_IO_6: + case HALMAC_GPIO_FUNC_SW_IO_7: + case HALMAC_GPIO_FUNC_SW_IO_8: + case HALMAC_GPIO_FUNC_SW_IO_9: + case HALMAC_GPIO_FUNC_SW_IO_10: + case HALMAC_GPIO_FUNC_SW_IO_11: + case HALMAC_GPIO_FUNC_SW_IO_12: + case HALMAC_GPIO_FUNC_SW_IO_13: + case HALMAC_GPIO_FUNC_SW_IO_14: + case HALMAC_GPIO_FUNC_SW_IO_15: + *enable = (cur_func == HALMAC_SW_IO) ? 1 : 0; + break; + default: + *enable = 0; + return HALMAC_RET_GET_PINMUX_ERR; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * pinmux_set_func_8821c() -set gpio function + * @adapter : the adapter of halmac + * @gpio_func : gpio function + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pinmux_set_func_8821c(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func) +{ + u32 list_size; + u32 gpio_id; + enum halmac_ret_status status; + const struct halmac_gpio_pimux_list *list = NULL; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]func name : %d\n", gpio_func); + + status = chk_pinmux_valid_8821c(adapter, gpio_func); + if (status != HALMAC_RET_SUCCESS) + return status; + + status = get_pinmux_list_8821c(adapter, gpio_func, &list, &list_size, + &gpio_id); + if (status != HALMAC_RET_SUCCESS) + return status; + + status = pinmux_switch_88xx(adapter, list, list_size, gpio_id, + gpio_func); + if (status != HALMAC_RET_SUCCESS) + return status; + + status = pinmux_record_88xx(adapter, gpio_func, 1); + if (status != HALMAC_RET_SUCCESS) + return status; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * pinmux_free_func_8821c() -free locked gpio function + * @adapter : the adapter of halmac + * @gpio_func : gpio function + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pinmux_free_func_8821c(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func) +{ + struct halmac_pinmux_info *info = &adapter->pinmux_info; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (gpio_func) { + case HALMAC_GPIO_FUNC_SW_IO_0: + info->sw_io_0 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_1: + info->sw_io_1 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_2: + info->sw_io_2 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_3: + info->sw_io_3 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_4: + case HALMAC_GPIO_FUNC_SDIO_INT: + info->sw_io_4 = 0; + info->sdio_int = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_5: + info->sw_io_5 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_6: + info->sw_io_6 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_7: + info->sw_io_7 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_8: + case HALMAC_GPIO_FUNC_WL_LED: + info->sw_io_8 = 0; + info->wl_led = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_9: + info->sw_io_9 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_10: + info->sw_io_10 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_11: + info->sw_io_11 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_12: + info->sw_io_12 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_13: + case HALMAC_GPIO_FUNC_BT_DEV_WAKE1: + info->bt_dev_wake = 0; + info->sw_io_13 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_14: + case HALMAC_GPIO_FUNC_BT_HOST_WAKE1: + info->bt_host_wake = 0; + info->sw_io_14 = 0; + break; + case HALMAC_GPIO_FUNC_SW_IO_15: + info->sw_io_15 = 0; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + PLTFM_MSG_TRACE("[TRACE]func : %X\n", gpio_func); + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_pinmux_list_8821c(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, + const struct halmac_gpio_pimux_list **list, + u32 *list_size, u32 *gpio_id) +{ + switch (gpio_func) { + case HALMAC_GPIO_FUNC_SW_IO_0: + *list = PINMUX_LIST_GPIO0_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO0_8821C); + *gpio_id = HALMAC_GPIO0; + break; + case HALMAC_GPIO_FUNC_SW_IO_1: + *list = PINMUX_LIST_GPIO1_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO1_8821C); + *gpio_id = HALMAC_GPIO1; + break; + case HALMAC_GPIO_FUNC_SW_IO_2: + *list = PINMUX_LIST_GPIO2_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO2_8821C); + *gpio_id = HALMAC_GPIO2; + break; + case HALMAC_GPIO_FUNC_SW_IO_3: + *list = PINMUX_LIST_GPIO3_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO3_8821C); + *gpio_id = HALMAC_GPIO3; + break; + case HALMAC_GPIO_FUNC_SW_IO_4: + case HALMAC_GPIO_FUNC_SDIO_INT: + *list = PINMUX_LIST_GPIO4_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO4_8821C); + *gpio_id = HALMAC_GPIO4; + break; + case HALMAC_GPIO_FUNC_SW_IO_5: + *list = PINMUX_LIST_GPIO5_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO5_8821C); + *gpio_id = HALMAC_GPIO5; + break; + case HALMAC_GPIO_FUNC_SW_IO_6: + *list = PINMUX_LIST_GPIO6_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO6_8821C); + *gpio_id = HALMAC_GPIO6; + break; + case HALMAC_GPIO_FUNC_SW_IO_7: + *list = PINMUX_LIST_GPIO7_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO7_8821C); + *gpio_id = HALMAC_GPIO7; + break; + case HALMAC_GPIO_FUNC_SW_IO_8: + case HALMAC_GPIO_FUNC_WL_LED: + *list = PINMUX_LIST_GPIO8_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO8_8821C); + *gpio_id = HALMAC_GPIO8; + break; + case HALMAC_GPIO_FUNC_SW_IO_9: + *list = PINMUX_LIST_GPIO9_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO9_8821C); + *gpio_id = HALMAC_GPIO9; + break; + case HALMAC_GPIO_FUNC_SW_IO_10: + *list = PINMUX_LIST_GPIO10_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO10_8821C); + *gpio_id = HALMAC_GPIO10; + break; + case HALMAC_GPIO_FUNC_SW_IO_11: + *list = PINMUX_LIST_GPIO11_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO11_8821C); + *gpio_id = HALMAC_GPIO11; + break; + case HALMAC_GPIO_FUNC_SW_IO_12: + *list = PINMUX_LIST_GPIO12_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO12_8821C); + *gpio_id = HALMAC_GPIO12; + break; + case HALMAC_GPIO_FUNC_SW_IO_13: + case HALMAC_GPIO_FUNC_BT_DEV_WAKE1: + *list = PINMUX_LIST_GPIO13_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO13_8821C); + *gpio_id = HALMAC_GPIO13; + break; + case HALMAC_GPIO_FUNC_SW_IO_14: + case HALMAC_GPIO_FUNC_BT_HOST_WAKE1: + *list = PINMUX_LIST_GPIO14_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO14_8821C); + *gpio_id = HALMAC_GPIO14; + break; + case HALMAC_GPIO_FUNC_SW_IO_15: + *list = PINMUX_LIST_GPIO15_8821C; + *list_size = ARRAY_SIZE(PINMUX_LIST_GPIO15_8821C); + *gpio_id = HALMAC_GPIO15; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +chk_pinmux_valid_8821c(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func) +{ + struct halmac_pinmux_info *info = &adapter->pinmux_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + switch (gpio_func) { + case HALMAC_GPIO_FUNC_SW_IO_0: + if (info->sw_io_0 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_1: + if (info->sw_io_1 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_2: + if (info->sw_io_2 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_3: + if (info->sw_io_3 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_4: + case HALMAC_GPIO_FUNC_SDIO_INT: + if (info->sw_io_4 == 1 || info->sdio_int == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_5: + if (info->sw_io_5 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_6: + if (info->sw_io_6 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_7: + if (info->sw_io_7 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_8: + case HALMAC_GPIO_FUNC_WL_LED: + if (info->sw_io_8 == 1 || info->wl_led == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_9: + if (info->sw_io_9 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_10: + if (info->sw_io_10 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_11: + if (info->sw_io_11 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_12: + if (info->sw_io_12 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_13: + case HALMAC_GPIO_FUNC_BT_DEV_WAKE1: + if (info->sw_io_13 == 1 || info->bt_dev_wake == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_14: + case HALMAC_GPIO_FUNC_BT_HOST_WAKE1: + if (info->sw_io_14 == 1 || info->bt_host_wake == 1) + status = HALMAC_RET_PINMUX_USED; + break; + case HALMAC_GPIO_FUNC_SW_IO_15: + if (info->sw_io_15 == 1) + status = HALMAC_RET_PINMUX_USED; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + PLTFM_MSG_TRACE("[TRACE]chk_pinmux_valid func : %X status : %X\n", + gpio_func, status); + + return status; +} +#endif /* HALMAC_8821C_SUPPORT */ + diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.h new file mode 100644 index 0000000..6a605db --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_gpio_8821c.h @@ -0,0 +1,37 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_GPIO_8821C_H_ +#define _HALMAC_GPIO_8821C_H_ + +#include "../../halmac_api.h" + +#if HALMAC_8821C_SUPPORT + +enum halmac_ret_status +pinmux_get_func_8821c(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, u8 *enable); + +enum halmac_ret_status +pinmux_set_func_8821c(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func); + +enum halmac_ret_status +pinmux_free_func_8821c(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func); + +#endif /* HALMAC_8821C_SUPPORT */ + +#endif/* _HALMAC_GPIO_8821C_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.c b/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.c new file mode 100644 index 0000000..6bd1d45 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.c @@ -0,0 +1,890 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_init_8821c.h" +#include "halmac_8821c_cfg.h" +#if HALMAC_PCIE_SUPPORT +#include "halmac_pcie_8821c.h" +#endif +#if HALMAC_SDIO_SUPPORT +#include "halmac_sdio_8821c.h" +#endif +#if HALMAC_USB_SUPPORT +#include "halmac_usb_8821c.h" +#endif +#include "halmac_gpio_8821c.h" +#include "halmac_common_8821c.h" +#include "halmac_cfg_wmac_8821c.h" +#include "../halmac_common_88xx.h" +#include "../halmac_init_88xx.h" + +#if HALMAC_8821C_SUPPORT + +#define RSVD_PG_DRV_NUM 16 +#define RSVD_PG_H2C_EXTRAINFO_NUM 24 +#define RSVD_PG_H2C_STATICINFO_NUM 8 +#define RSVD_PG_H2CQ_NUM 8 +#define RSVD_PG_CPU_INSTRUCTION_NUM 0 +#define RSVD_PG_FW_TXBUF_NUM 4 +#define RSVD_PG_CSIBUF_NUM 0 +#define RSVD_PG_DLLB_NUM (TX_FIFO_SIZE_8821C / 3 >> \ + TX_PAGE_SIZE_SHIFT_88XX) + +#define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ + BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ + BIT_MACTXEN | BIT_MACRXEN) + +#define BLK_DESC_NUM 0x3 + +#define WLAN_SLOT_TIME 0x05 +#define WLAN_PIFS_TIME 0x19 +#define WLAN_SIFS_CCK_CONT_TX 0xA +#define WLAN_SIFS_OFDM_CONT_TX 0xA +#define WLAN_SIFS_CCK_TRX 0x10 +#define WLAN_SIFS_OFDM_TRX 0x10 +#define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */ +#define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */ +#define WLAN_RDG_NAV 0x05 +#define WLAN_TXOP_NAV 0x1B +#define WLAN_CCK_RX_TSF 0x30 +#define WLAN_OFDM_RX_TSF 0x30 +#define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ +#define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ +#define WLAN_DRV_EARLY_INT 0x04 +#define WLAN_BCN_DMA_TIME 0x02 +#define WLAN_ACK_TO_CCK 0x40 + +#define WLAN_RX_FILTER0 0x0FFFFFFF +#define WLAN_RX_FILTER2 0xFFFF +#define WLAN_RCR_CFG 0xE400220E +#define WLAN_RXPKT_MAX_SZ 12288 +#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) + +#define WLAN_AMPDU_MAX_TIME 0x70 +#define WLAN_RTS_LEN_TH 0xFF +#define WLAN_RTS_TX_TIME_TH 0x08 +#define WLAN_MAX_AGG_PKT_LIMIT 0x10 +#define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x10 +#define WLAN_MAX_AGG_PKT_LIMIT_SDIO 0x2B +#define WLAN_RTS_MAX_AGG_PKT_LIMIT_SDIO 0x2B +#define WLAN_PRE_TXCNT_TIME_TH 0x1E4 +#define WALN_FAST_EDCA_VO_TH 0x06 +#define WLAN_FAST_EDCA_VI_TH 0x06 +#define WLAN_FAST_EDCA_BE_TH 0x06 +#define WLAN_FAST_EDCA_BK_TH 0x06 +#define WLAN_BAR_RETRY_LIMIT 0x01 +#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 + +#define WLAN_TX_FUNC_CFG1 0x30 +#define WLAN_TX_FUNC_CFG2 0x30 +#define WLAN_MAC_OPT_NORM_FUNC1 0x98 +#define WLAN_MAC_OPT_LB_FUNC1 0x80 +#define WLAN_MAC_OPT_FUNC2 0x30810041 + +#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ + (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ + (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ + (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) + +#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ + (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) + +#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) +#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) + +#if HALMAC_PLATFORM_WINDOWS +/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/ +static struct halmac_rqpn HALMAC_RQPN_SDIO_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; +#else +/*SDIO RQPN Mapping*/ +static struct halmac_rqpn HALMAC_RQPN_SDIO_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; +#endif + +/*PCIE RQPN Mapping*/ +static struct halmac_rqpn HALMAC_RQPN_PCIE_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; + +/*USB 2 Bulkout RQPN Mapping*/ +static struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; + +/*USB 3 Bulkout RQPN Mapping*/ +static struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; + +/*USB 4 Bulkout RQPN Mapping*/ +static struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, + HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, + HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, + HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; + +#if HALMAC_PLATFORM_WINDOWS +/*SDIO Page Number*/ +static struct halmac_pg_num HALMAC_PG_NUM_SDIO_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 8, 8, 8, 0, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 0, 1}, +}; +#else +/*SDIO Page Number*/ +static struct halmac_pg_num HALMAC_PG_NUM_SDIO_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 8, 8, 8, 8, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 1}, +}; +#endif + +/*PCIE Page Number*/ +static struct halmac_pg_num HALMAC_PG_NUM_PCIE_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 1}, +}; + +/*USB 2 Bulkout Page Number*/ +static struct halmac_pg_num HALMAC_PG_NUM_2BULKOUT_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 0, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 16, 16, 0, 0, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 0, 0, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 0, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 0, 0, 1}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 0, 0, 1}, +}; + +/*USB 3 Bulkout Page Number*/ +static struct halmac_pg_num HALMAC_PG_NUM_3BULKOUT_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 0, 1}, +}; + +/*USB 4 Bulkout Page Number*/ +static struct halmac_pg_num HALMAC_PG_NUM_4BULKOUT_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 1}, +}; + +static enum halmac_ret_status +txdma_queue_mapping_8821c(struct halmac_adapter *adapter, + enum halmac_trx_mode mode); + +static enum halmac_ret_status +priority_queue_cfg_8821c(struct halmac_adapter *adapter, + enum halmac_trx_mode mode); + +static enum halmac_ret_status +set_trx_fifo_info_8821c(struct halmac_adapter *adapter, + enum halmac_trx_mode mode); + +enum halmac_ret_status +mount_api_8821c(struct halmac_adapter *adapter) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + adapter->chip_id = HALMAC_CHIP_ID_8821C; + adapter->hw_cfg_info.efuse_size = EFUSE_SIZE_8821C; + adapter->hw_cfg_info.eeprom_size = EEPROM_SIZE_8821C; + adapter->hw_cfg_info.bt_efuse_size = BT_EFUSE_SIZE_8821C; + adapter->hw_cfg_info.cam_entry_num = SEC_CAM_NUM_8821C; + adapter->hw_cfg_info.tx_fifo_size = TX_FIFO_SIZE_8821C; + adapter->hw_cfg_info.rx_fifo_size = RX_FIFO_SIZE_8821C; + adapter->hw_cfg_info.ac_oqt_size = OQT_ENTRY_AC_8821C; + adapter->hw_cfg_info.non_ac_oqt_size = OQT_ENTRY_NOAC_8821C; + adapter->hw_cfg_info.usb_txagg_num = BLK_DESC_NUM; + adapter->txff_alloc.rsvd_drv_pg_num = RSVD_PG_DRV_NUM; + + api->halmac_init_trx_cfg = init_trx_cfg_8821c; + api->halmac_init_protocol_cfg = init_protocol_cfg_8821c; + api->halmac_init_h2c = init_h2c_8821c; + api->halmac_pinmux_get_func = pinmux_get_func_8821c; + api->halmac_pinmux_set_func = pinmux_set_func_8821c; + api->halmac_pinmux_free_func = pinmux_free_func_8821c; + api->halmac_get_hw_value = get_hw_value_8821c; + api->halmac_set_hw_value = set_hw_value_8821c; + api->halmac_cfg_drv_info = cfg_drv_info_8821c; + api->halmac_fill_txdesc_checksum = fill_txdesc_check_sum_8821c; + api->halmac_init_low_pwr = init_low_pwr_8821c; + + api->halmac_init_wmac_cfg = init_wmac_cfg_8821c; + api->halmac_init_edca_cfg = init_edca_cfg_8821c; + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { +#if HALMAC_SDIO_SUPPORT + api->halmac_mac_power_switch = mac_pwr_switch_sdio_8821c; + api->halmac_phy_cfg = phy_cfg_sdio_8821c; + api->halmac_pcie_switch = pcie_switch_sdio_8821c; + api->halmac_interface_integration_tuning = intf_tun_sdio_8821c; + api->halmac_tx_allowed_sdio = tx_allowed_sdio_8821c; + api->halmac_get_sdio_tx_addr = get_sdio_tx_addr_8821c; + api->halmac_reg_read_8 = reg_r8_sdio_8821c; + api->halmac_reg_write_8 = reg_w8_sdio_8821c; + api->halmac_reg_read_16 = reg_r16_sdio_8821c; + api->halmac_reg_write_16 = reg_w16_sdio_8821c; + api->halmac_reg_read_32 = reg_r32_sdio_8821c; + api->halmac_reg_write_32 = reg_w32_sdio_8821c; + + adapter->sdio_fs.macid_map_size = MACID_MAX_8821C * 2; + if (!adapter->sdio_fs.macid_map) { + adapter->sdio_fs.macid_map = + (u8 *)PLTFM_MALLOC(adapter->sdio_fs.macid_map_size); + if (!adapter->sdio_fs.macid_map) + PLTFM_MSG_ERR("[ERR]mac id map malloc!!\n"); + } +#endif + } else if (adapter->intf == HALMAC_INTERFACE_USB) { +#if HALMAC_USB_SUPPORT + api->halmac_mac_power_switch = mac_pwr_switch_usb_8821c; + api->halmac_phy_cfg = phy_cfg_usb_8821c; + api->halmac_pcie_switch = pcie_switch_usb_8821c; + api->halmac_interface_integration_tuning = intf_tun_usb_8821c; +#endif + } else if (adapter->intf == HALMAC_INTERFACE_PCIE) { +#if HALMAC_PCIE_SUPPORT + api->halmac_mac_power_switch = mac_pwr_switch_pcie_8821c; + api->halmac_phy_cfg = phy_cfg_pcie_8821c; + api->halmac_pcie_switch = pcie_switch_8821c; + api->halmac_interface_integration_tuning = intf_tun_pcie_8821c; +#endif + } else { + PLTFM_MSG_ERR("[ERR]Undefined IC\n"); + return HALMAC_RET_CHIP_NOT_SUPPORT; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * init_trx_cfg_8821c() - config trx dma register + * @adapter : the adapter of halmac + * @mode : trx mode selection + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_trx_cfg_8821c(struct halmac_adapter *adapter, enum halmac_trx_mode mode) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + adapter->trx_mode = mode; + + status = txdma_queue_mapping_8821c(adapter, mode); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]queue mapping\n"); + return status; + } + + value8 = 0; + HALMAC_REG_W8(REG_CR, value8); + value8 = MAC_TRX_ENABLE; + HALMAC_REG_W8(REG_CR, value8); + HALMAC_REG_W32(REG_H2CQ_CSR, BIT(31)); + + status = priority_queue_cfg_8821c(adapter, mode); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]priority queue cfg\n"); + return status; + } + + if (adapter->txff_alloc.rx_fifo_exp_mode != + HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE) + HALMAC_REG_W8(REG_RX_DRVINFO_SZ, RX_DESC_DUMMY_SIZE_8821C >> 3); + + status = init_h2c_8821c(adapter); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]init h2cq!\n"); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +txdma_queue_mapping_8821c(struct halmac_adapter *adapter, + enum halmac_trx_mode mode) +{ + u16 value16; + struct halmac_rqpn *cur_rqpn_sel = NULL; + enum halmac_ret_status status; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + cur_rqpn_sel = HALMAC_RQPN_SDIO_8821C; + } else if (adapter->intf == HALMAC_INTERFACE_PCIE) { + cur_rqpn_sel = HALMAC_RQPN_PCIE_8821C; + } else if (adapter->intf == HALMAC_INTERFACE_USB) { + if (adapter->bulkout_num == 2) { + cur_rqpn_sel = HALMAC_RQPN_2BULKOUT_8821C; + } else if (adapter->bulkout_num == 3) { + cur_rqpn_sel = HALMAC_RQPN_3BULKOUT_8821C; + } else if (adapter->bulkout_num == 4) { + cur_rqpn_sel = HALMAC_RQPN_4BULKOUT_8821C; + } else { + PLTFM_MSG_ERR("[ERR]invalid intf\n"); + return HALMAC_RET_NOT_SUPPORT; + } + } else { + return HALMAC_RET_NOT_SUPPORT; + } + + status = rqpn_parser_88xx(adapter, mode, cur_rqpn_sel); + if (status != HALMAC_RET_SUCCESS) + return status; + + value16 = 0; + value16 |= BIT_TXDMA_HIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_HI]); + value16 |= BIT_TXDMA_MGQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_MG]); + value16 |= BIT_TXDMA_BKQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BK]); + value16 |= BIT_TXDMA_BEQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BE]); + value16 |= BIT_TXDMA_VIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VI]); + value16 |= BIT_TXDMA_VOQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VO]); + HALMAC_REG_W16(REG_TXDMA_PQ_MAP, value16); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +priority_queue_cfg_8821c(struct halmac_adapter *adapter, + enum halmac_trx_mode mode) +{ + u8 transfer_mode = 0; + u8 value8; + u32 cnt; + struct halmac_txff_allocation *txff_info = &adapter->txff_alloc; + enum halmac_ret_status status; + struct halmac_pg_num *cur_pg_num = NULL; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + status = set_trx_fifo_info_8821c(adapter, mode); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]set trx fifo!!\n"); + return status; + } + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + cur_pg_num = HALMAC_PG_NUM_SDIO_8821C; + } else if (adapter->intf == HALMAC_INTERFACE_PCIE) { + cur_pg_num = HALMAC_PG_NUM_PCIE_8821C; + } else if (adapter->intf == HALMAC_INTERFACE_USB) { + if (adapter->bulkout_num == 2) { + cur_pg_num = HALMAC_PG_NUM_2BULKOUT_8821C; + } else if (adapter->bulkout_num == 3) { + cur_pg_num = HALMAC_PG_NUM_3BULKOUT_8821C; + } else if (adapter->bulkout_num == 4) { + cur_pg_num = HALMAC_PG_NUM_4BULKOUT_8821C; + } else { + PLTFM_MSG_ERR("[ERR]invalid intf\n"); + return HALMAC_RET_NOT_SUPPORT; + } + } else { + return HALMAC_RET_NOT_SUPPORT; + } + + status = pg_num_parser_88xx(adapter, mode, cur_pg_num); + if (status != HALMAC_RET_SUCCESS) + return status; + + PLTFM_MSG_TRACE("[TRACE]Set FIFO page\n"); + + HALMAC_REG_W16(REG_FIFOPAGE_INFO_1, txff_info->high_queue_pg_num); + HALMAC_REG_W16(REG_FIFOPAGE_INFO_2, txff_info->low_queue_pg_num); + HALMAC_REG_W16(REG_FIFOPAGE_INFO_3, txff_info->normal_queue_pg_num); + HALMAC_REG_W16(REG_FIFOPAGE_INFO_4, txff_info->extra_queue_pg_num); + HALMAC_REG_W16(REG_FIFOPAGE_INFO_5, txff_info->pub_queue_pg_num); + HALMAC_REG_W32_SET(REG_RQPN_CTRL_2, BIT(31)); + + adapter->sdio_fs.hiq_pg_num = txff_info->high_queue_pg_num; + adapter->sdio_fs.miq_pg_num = txff_info->normal_queue_pg_num; + adapter->sdio_fs.lowq_pg_num = txff_info->low_queue_pg_num; + adapter->sdio_fs.pubq_pg_num = txff_info->pub_queue_pg_num; + adapter->sdio_fs.exq_pg_num = txff_info->extra_queue_pg_num; + + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, txff_info->rsvd_boundary); + HALMAC_REG_W8_SET(REG_FWHW_TXQ_CTRL + 2, BIT(4)); + + /*20170411 Soar*/ + /* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */ + /* and may cause a mismatch between HW status and Reg value. */ + /* A patch is to write high byte first, suggested by Argis */ + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + value8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF); + HALMAC_REG_W8(REG_BCNQ_BDNY_V1 + 1, value8); + value8 = (u8)(txff_info->rsvd_boundary & 0xFF); + HALMAC_REG_W8(REG_BCNQ_BDNY_V1, value8); + } else { + HALMAC_REG_W16(REG_BCNQ_BDNY_V1, txff_info->rsvd_boundary); + } + + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2 + 2, txff_info->rsvd_boundary); + + /*20170411 Soar*/ + /* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */ + /* and may cause a mismatch between HW status and Reg value. */ + /* A patch is to write high byte first, suggested by Argis */ + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + value8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF); + HALMAC_REG_W8(REG_BCNQ1_BDNY_V1 + 1, value8); + value8 = (u8)(txff_info->rsvd_boundary & 0xFF); + HALMAC_REG_W8(REG_BCNQ1_BDNY_V1, value8); + } else { + HALMAC_REG_W16(REG_BCNQ1_BDNY_V1, txff_info->rsvd_boundary); + } + + HALMAC_REG_W32(REG_RXFF_BNDY, + adapter->hw_cfg_info.rx_fifo_size - + C2H_PKT_BUF_88XX - 1); + + if (adapter->intf == HALMAC_INTERFACE_USB) { + value8 = HALMAC_REG_R8(REG_AUTO_LLT_V1); + value8 &= ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM); + value8 |= (BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM); + HALMAC_REG_W8(REG_AUTO_LLT_V1, value8); + + HALMAC_REG_W8(REG_AUTO_LLT_V1 + 3, BLK_DESC_NUM); + HALMAC_REG_W8_SET(REG_TXDMA_OFFSET_CHK + 1, BIT(1)); + } + + HALMAC_REG_W8_SET(REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1); + cnt = 1000; + while (HALMAC_REG_R8(REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) { + cnt--; + if (cnt == 0) + return HALMAC_RET_INIT_LLT_FAIL; + } + + if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) { + transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY; + HALMAC_REG_W16(REG_WMAC_LBK_BUF_HD_V1, + adapter->txff_alloc.rsvd_boundary); + } else if (mode == HALMAC_TRX_MODE_LOOPBACK) { + transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT; + } else { + transfer_mode = HALMAC_TRNSFER_NORMAL; + } + + adapter->hw_cfg_info.trx_mode = transfer_mode; + HALMAC_REG_W8(REG_CR + 3, (u8)transfer_mode); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +set_trx_fifo_info_8821c(struct halmac_adapter *adapter, + enum halmac_trx_mode mode) +{ + u16 cur_pg_addr; + u32 txff_size = TX_FIFO_SIZE_8821C; + u32 rxff_size = RX_FIFO_SIZE_8821C; + struct halmac_txff_allocation *info = &adapter->txff_alloc; + + if (info->rx_fifo_exp_mode == HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK) { + txff_size = TX_FIFO_SIZE_RX_EXPAND_1BLK_8821C; + rxff_size = RX_FIFO_SIZE_RX_EXPAND_1BLK_8821C; + } + + if (info->la_mode != HALMAC_LA_MODE_DISABLE) { + txff_size = TX_FIFO_SIZE_LA_8821C; + rxff_size = RX_FIFO_SIZE_8821C; + } + + adapter->hw_cfg_info.tx_fifo_size = txff_size; + adapter->hw_cfg_info.rx_fifo_size = rxff_size; + info->tx_fifo_pg_num = (u16)(txff_size >> TX_PAGE_SIZE_SHIFT_88XX); + + info->rsvd_pg_num = info->rsvd_drv_pg_num + + RSVD_PG_H2C_EXTRAINFO_NUM + + RSVD_PG_H2C_STATICINFO_NUM + + RSVD_PG_H2CQ_NUM + + RSVD_PG_CPU_INSTRUCTION_NUM + + RSVD_PG_FW_TXBUF_NUM + + RSVD_PG_CSIBUF_NUM; + + if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) + info->rsvd_pg_num += RSVD_PG_DLLB_NUM; + + if (info->rsvd_pg_num > info->tx_fifo_pg_num) + return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; + + info->acq_pg_num = info->tx_fifo_pg_num - info->rsvd_pg_num; + info->rsvd_boundary = info->tx_fifo_pg_num - info->rsvd_pg_num; + + cur_pg_addr = info->tx_fifo_pg_num; + cur_pg_addr -= RSVD_PG_CSIBUF_NUM; + info->rsvd_csibuf_addr = cur_pg_addr; + cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM; + info->rsvd_fw_txbuf_addr = cur_pg_addr; + cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM; + info->rsvd_cpu_instr_addr = cur_pg_addr; + cur_pg_addr -= RSVD_PG_H2CQ_NUM; + info->rsvd_h2cq_addr = cur_pg_addr; + cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM; + info->rsvd_h2c_sta_info_addr = cur_pg_addr; + cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM; + info->rsvd_h2c_info_addr = cur_pg_addr; + cur_pg_addr -= info->rsvd_drv_pg_num; + info->rsvd_drv_addr = cur_pg_addr; + + if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) + info->rsvd_drv_addr -= RSVD_PG_DLLB_NUM; + + if (info->rsvd_boundary != info->rsvd_drv_addr) + return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; + + return HALMAC_RET_SUCCESS; +} + +/** + * init_protocol_cfg_8821c() - config protocol register + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_protocol_cfg_8821c(struct halmac_adapter *adapter) +{ + u16 pre_txcnt; + u32 max_agg_num; + u32 max_rts_agg_num; + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + HALMAC_REG_W8(REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); + HALMAC_REG_W8_SET(REG_TX_HANG_CTRL, BIT_EN_EOF_V1); + + pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; + HALMAC_REG_W8(REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); + HALMAC_REG_W8(REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); + + max_agg_num = WLAN_MAX_AGG_PKT_LIMIT; + max_rts_agg_num = WLAN_RTS_MAX_AGG_PKT_LIMIT; + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + max_agg_num = WLAN_MAX_AGG_PKT_LIMIT_SDIO; + max_rts_agg_num = WLAN_RTS_MAX_AGG_PKT_LIMIT_SDIO; + } + + value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | + (max_agg_num << 16) | (max_rts_agg_num << 24); + HALMAC_REG_W32(REG_PROT_MODE_CTRL, value32); + + HALMAC_REG_W16(REG_BAR_MODE_CTRL + 2, + WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); + + HALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING, WALN_FAST_EDCA_VO_TH); + HALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING + 2, WLAN_FAST_EDCA_VI_TH); + HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING, WLAN_FAST_EDCA_BE_TH); + HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING + 2, WLAN_FAST_EDCA_BK_TH); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_h2c_8821c() - config h2c packet buffer + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_h2c_8821c(struct halmac_adapter *adapter) +{ + u8 value8; + u32 value32; + u32 h2cq_addr; + u32 h2cq_size; + struct halmac_txff_allocation *txff_info = &adapter->txff_alloc; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + h2cq_addr = txff_info->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT_88XX; + h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT_88XX; + + value32 = HALMAC_REG_R32(REG_H2C_HEAD); + value32 = (value32 & 0xFFFC0000) | h2cq_addr; + HALMAC_REG_W32(REG_H2C_HEAD, value32); + + value32 = HALMAC_REG_R32(REG_H2C_READ_ADDR); + value32 = (value32 & 0xFFFC0000) | h2cq_addr; + HALMAC_REG_W32(REG_H2C_READ_ADDR, value32); + + value32 = HALMAC_REG_R32(REG_H2C_TAIL); + value32 &= 0xFFFC0000; + value32 |= (h2cq_addr + h2cq_size); + HALMAC_REG_W32(REG_H2C_TAIL, value32); + + value8 = HALMAC_REG_R8(REG_H2C_INFO); + value8 = (u8)((value8 & 0xFC) | 0x01); + HALMAC_REG_W8(REG_H2C_INFO, value8); + + value8 = HALMAC_REG_R8(REG_H2C_INFO); + value8 = (u8)((value8 & 0xFB) | 0x04); + HALMAC_REG_W8(REG_H2C_INFO, value8); + + value8 = HALMAC_REG_R8(REG_TXDMA_OFFSET_CHK + 1); + value8 = (u8)((value8 & 0x7f) | 0x80); + HALMAC_REG_W8(REG_TXDMA_OFFSET_CHK + 1, value8); + + adapter->h2c_info.buf_size = h2cq_size; + get_h2c_buf_free_space_88xx(adapter); + + if (adapter->h2c_info.buf_size != adapter->h2c_info.buf_fs) { + PLTFM_MSG_ERR("[ERR]get h2c free space error!\n"); + return HALMAC_RET_GET_H2C_SPACE_ERR; + } + + PLTFM_MSG_TRACE("[TRACE]h2c fs : %d\n", adapter->h2c_info.buf_fs); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_edca_cfg_8821c() - init EDCA config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_edca_cfg_8821c(struct halmac_adapter *adapter) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + /* Init SYNC_CLI_SEL : reg 0x5B4[6:4] = 0 */ + HALMAC_REG_W8_CLR(REG_TIMER0_SRC_SEL, BIT(4) | BIT(5) | BIT(6)); + + /* Clear TX pause */ + HALMAC_REG_W16(REG_TXPAUSE, 0x0000); + + HALMAC_REG_W8(REG_SLOT, WLAN_SLOT_TIME); + HALMAC_REG_W8(REG_PIFS, WLAN_PIFS_TIME); + HALMAC_REG_W32(REG_SIFS, WLAN_SIFS_CFG); + + HALMAC_REG_W16(REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); + HALMAC_REG_W16(REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); + + HALMAC_REG_W32(REG_RD_NAV_NXT, WLAN_NAV_CFG); + HALMAC_REG_W16(REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); + + /* Set beacon cotnrol - enable TSF and other related functions */ + HALMAC_REG_W8(REG_BCN_CTRL, (u8)(HALMAC_REG_R8(REG_BCN_CTRL) | + BIT_EN_BCN_FUNCTION)); + + /* Set send beacon related registers */ + HALMAC_REG_W32(REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); + HALMAC_REG_W8(REG_DRVERLYINT, WLAN_DRV_EARLY_INT); + HALMAC_REG_W8(REG_BCNDMATIM, WLAN_BCN_DMA_TIME); + + HALMAC_REG_W8_CLR(REG_TX_PTCL_CTRL + 1, BIT(4)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_wmac_cfg_8821c() - init wmac config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_wmac_cfg_8821c(struct halmac_adapter *adapter) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + HALMAC_REG_W32(REG_RXFLTMAP0, WLAN_RX_FILTER0); + HALMAC_REG_W16(REG_RXFLTMAP2, WLAN_RX_FILTER2); + + HALMAC_REG_W32(REG_RCR, WLAN_RCR_CFG); + + HALMAC_REG_W8(REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); + + HALMAC_REG_W8(REG_TCR + 2, WLAN_TX_FUNC_CFG2); + HALMAC_REG_W8(REG_TCR + 1, WLAN_TX_FUNC_CFG1); + + HALMAC_REG_W8(REG_ACKTO_CCK, WLAN_ACK_TO_CCK); + + HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); + + if (adapter->hw_cfg_info.trx_mode == HALMAC_TRNSFER_NORMAL) + value8 = WLAN_MAC_OPT_NORM_FUNC1; + else + value8 = WLAN_MAC_OPT_LB_FUNC1; + + HALMAC_REG_W8(REG_WMAC_OPTION_FUNCTION + 4, value8); + + status = api->halmac_init_low_pwr(adapter); + if (status != HALMAC_RET_SUCCESS) + return status; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_8821C_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.h new file mode 100644 index 0000000..7b4667a --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_init_8821c.h @@ -0,0 +1,43 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_INIT_8821C_H_ +#define _HALMAC_INIT_8821C_H_ + +#include "../../halmac_api.h" + +#if HALMAC_8821C_SUPPORT + +enum halmac_ret_status +mount_api_8821c(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_trx_cfg_8821c(struct halmac_adapter *adapter, enum halmac_trx_mode mode); + +enum halmac_ret_status +init_protocol_cfg_8821c(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_h2c_8821c(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_edca_cfg_8821c(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_wmac_cfg_8821c(struct halmac_adapter *adapter); + +#endif /* HALMAC_8821C_SUPPORT */ + +#endif/* _HALMAC_INIT_8821C_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.c b/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.c new file mode 100644 index 0000000..9c87c7d --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.c @@ -0,0 +1,356 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_pcie_8821c.h" +#include "halmac_pwr_seq_8821c.h" +#include "../halmac_init_88xx.h" +#include "../halmac_common_88xx.h" +#include "../halmac_pcie_88xx.h" +#include "halmac_8821c_cfg.h" + +#if (HALMAC_8821C_SUPPORT && HALMAC_PCIE_SUPPORT) + +#define INTF_INTGRA_MINREF 90 +#define INTF_INTGRA_HOSTREF 100 + +static u16 +get_target(struct halmac_adapter *adapter); + +static enum halmac_ret_status +freerun_delay_us(struct halmac_adapter *adapter, u16 delay); + +/** + * mac_pwr_switch_pcie_8821c() - switch mac power + * @adapter : the adapter of halmac + * @pwr : power state + * Author : KaiYuan Chang / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mac_pwr_switch_pcie_8821c(struct halmac_adapter *adapter, + enum halmac_mac_power pwr) +{ + u8 value8; + u8 rpwm; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]pwr = %x\n", pwr); + PLTFM_MSG_TRACE("[TRACE]8821C pwr seq ver = %s\n", + HALMAC_8821C_PWR_SEQ_VER); + + adapter->rpwm = HALMAC_REG_R8(REG_PCIE_HRPWM1_V1); + + /* Check FW still exist or not */ + if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) { + /* Leave 32K */ + rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80); + HALMAC_REG_W8(REG_PCIE_HRPWM1_V1, rpwm); + } + + value8 = HALMAC_REG_R8(REG_CR); + if (value8 == 0xEA) + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF; + else + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON; + + /* Check if power switch is needed */ + if (pwr == HALMAC_MAC_POWER_ON && + adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) { + PLTFM_MSG_WARN("[WARN]power state unchange!!\n"); + return HALMAC_RET_PWR_UNCHANGE; + } + + if (pwr == HALMAC_MAC_POWER_OFF) { + status = trxdma_check_idle_88xx(adapter); + if (status != HALMAC_RET_SUCCESS) + return status; + if (pwr_seq_parser_88xx(adapter, card_dis_flow_8821c) != + HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n"); + return HALMAC_RET_POWER_OFF_FAIL; + } + + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF; + adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + init_adapter_dynamic_param_88xx(adapter); + } else { + if (pwr_seq_parser_88xx(adapter, card_en_flow_8821c) != + HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n"); + return HALMAC_RET_POWER_ON_FAIL; + } + + adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pcie_switch_8821c() - pcie gen1/gen2 switch + * @adapter : the adapter of halmac + * @cfg : gen1/gen2 selection + * Author : KaiYuan Chang / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pcie_switch_8821c(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * phy_cfg_pcie_8821c() - phy config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +phy_cfg_pcie_8821c(struct halmac_adapter *adapter, + enum halmac_intf_phy_platform pltfm) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = parse_intf_phy_88xx(adapter, pcie_gen1_phy_param_8821c, pltfm, + HAL_INTF_PHY_PCIE_GEN1); + + if (status != HALMAC_RET_SUCCESS) + return status; + + status = parse_intf_phy_88xx(adapter, pcie_gen2_phy_param_8821c, pltfm, + HAL_INTF_PHY_PCIE_GEN2); + + if (status != HALMAC_RET_SUCCESS) + return status; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * intf_tun_pcie_8821c() - pcie interface fine tuning + * @adapter : the adapter of halmac + * Author : Rick Liu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +intf_tun_pcie_8821c(struct halmac_adapter *adapter) +{ + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +auto_refclk_cal_8821c_pcie(struct halmac_adapter *adapter) +{ + u8 bdr_ori; + u16 tmp_u16; + u16 div_set; + u16 mgn_tmp; + u16 mgn_set; + u16 tar; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + u8 l1_flag = 0; + +#if (INTF_INTGRA_HOSTREF <= INTF_INTGRA_MINREF || 0 >= INTF_INTGRA_MINREF) + return status; +#endif + /* Disable L1BD */ + bdr_ori = dbi_r8_88xx(adapter, PCIE_L1_BACKDOOR); + if (bdr_ori & (BIT(4) | BIT(3))) { + status = dbi_w8_88xx(adapter, PCIE_L1_BACKDOOR, + bdr_ori & ~(BIT(4) | BIT(3))); + if (status != HALMAC_RET_SUCCESS) + return status; + l1_flag = 1; + } + + /* Disable function */ + tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR, + HAL_INTF_PHY_PCIE_GEN1); + if (tmp_u16 & BIT(9)) { + status = mdio_write_88xx(adapter, RAC_CTRL_PPR, + tmp_u16 & ~(BIT(9)), + HAL_INTF_PHY_PCIE_GEN1); + if (status != HALMAC_RET_SUCCESS) + return status; + } + if (adapter->pcie_refautok_en == 0) { + if (l1_flag == 1) + status = dbi_w8_88xx(adapter, PCIE_L1_BACKDOOR, + bdr_ori); + return status; + } + + /* Set div */ + tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR, HAL_INTF_PHY_PCIE_GEN1); + status = mdio_write_88xx(adapter, RAC_CTRL_PPR, + tmp_u16 & ~(BIT(7) | BIT(6)), + HAL_INTF_PHY_PCIE_GEN1); + if (status != HALMAC_RET_SUCCESS) + return status; + + /* Obtain div and margin */ + tar = get_target(adapter); + if (tar == 0xFFFF) + return HALMAC_RET_FAIL; + mgn_tmp = tar * INTF_INTGRA_HOSTREF / INTF_INTGRA_MINREF - tar; + + if (mgn_tmp >= 128) { + div_set = 0x0003; + mgn_set = 0x000F; + } else if (mgn_tmp >= 64) { + div_set = 0x0003; + mgn_set = mgn_tmp >> 3; + } else if (mgn_tmp >= 32) { + div_set = 0x0002; + mgn_set = mgn_tmp >> 2; + } else if (mgn_tmp >= 16) { + div_set = 0x0001; + mgn_set = mgn_tmp >> 1; + } else if (mgn_tmp == 0) { + div_set = 0x0000; + mgn_set = 0x0001; + } else { + div_set = 0x0000; + mgn_set = mgn_tmp; + } + + /* Set div, margin, target*/ + tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR, HAL_INTF_PHY_PCIE_GEN1); + tmp_u16 = (tmp_u16 & ~(BIT(7) | BIT(6))) | (div_set << 6); + status = mdio_write_88xx(adapter, RAC_CTRL_PPR, + tmp_u16, HAL_INTF_PHY_PCIE_GEN1); + if (status != HALMAC_RET_SUCCESS) + return status; + tar = get_target(adapter); + if (tar == 0xFFFF) + return HALMAC_RET_FAIL; + PLTFM_MSG_TRACE("[TRACE]target = 0x%X, div = 0x%X, margin = 0x%X\n", + tar, div_set, mgn_set); + status = mdio_write_88xx(adapter, RAC_SET_PPR, + (tar & 0x0FFF) | (mgn_set << 12), + HAL_INTF_PHY_PCIE_GEN1); + if (status != HALMAC_RET_SUCCESS) + return status; + + /* Enable function */ + tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR, HAL_INTF_PHY_PCIE_GEN1); + status = mdio_write_88xx(adapter, RAC_CTRL_PPR, tmp_u16 | BIT(9), + HAL_INTF_PHY_PCIE_GEN1); + if (status != HALMAC_RET_SUCCESS) + return status; + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + /* Set L1BD to ori */ + if (l1_flag == 1) + status = dbi_w8_88xx(adapter, PCIE_L1_BACKDOOR, bdr_ori); + + return status; +} + +static u16 +get_target(struct halmac_adapter *adapter) +{ + u16 tmp_u16; + u16 tar; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + /* Enable counter */ + tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR, HAL_INTF_PHY_PCIE_GEN1); + status = mdio_write_88xx(adapter, RAC_CTRL_PPR, + tmp_u16 | BIT(11), HAL_INTF_PHY_PCIE_GEN1); + if (status != HALMAC_RET_SUCCESS) + return 0xFFFF; + + /* Obtain target */ + status = freerun_delay_us(adapter, 300); + if (status != HALMAC_RET_SUCCESS) + return 0xFFFF; + tar = mdio_read_88xx(adapter, RAC_TRG_PPR, HAL_INTF_PHY_PCIE_GEN1); + if (tar == 0) { + PLTFM_MSG_ERR("[ERR]Get target failed.\n"); + return 0xFFFF; + } + + /* Disable counter */ + tmp_u16 = mdio_read_88xx(adapter, RAC_CTRL_PPR, HAL_INTF_PHY_PCIE_GEN1); + status = mdio_write_88xx(adapter, RAC_CTRL_PPR, + tmp_u16 & ~(BIT(11)), HAL_INTF_PHY_PCIE_GEN1); + if (status != HALMAC_RET_SUCCESS) + return 0xFFFF; + return tar; +} + +static enum halmac_ret_status +freerun_delay_us(struct halmac_adapter *adapter, u16 delay) +{ + u16 count; + u8 mc_ori; + u32 frcnt_ori; + u32 frcnt_cmp; + u8 frcnt_onflg = 0; + u32 cmp_val; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + /* Enable free-run counter */ + mc_ori = HALMAC_REG_R8(REG_MISC_CTRL); + if ((mc_ori & BIT(3)) == 0) { + status = HALMAC_REG_W8(REG_MISC_CTRL, mc_ori | BIT(3)); + if (status != HALMAC_RET_SUCCESS) + return status; + frcnt_onflg = 1; + } + + /* counting delay */ + count = 20; + frcnt_ori = HALMAC_REG_R32(REG_FREERUN_CNT); + PLTFM_MSG_TRACE("[TRACE]free_ori = 0x%X\n", frcnt_ori); + do { + PLTFM_DELAY_US(100); + count--; + frcnt_cmp = HALMAC_REG_R32(REG_FREERUN_CNT); + PLTFM_MSG_TRACE("[TRACE]Count=0x%X, free_cmp=0x%X\n" + , count, frcnt_cmp); + if (frcnt_cmp >= frcnt_ori) + cmp_val = frcnt_cmp - frcnt_ori; + else + cmp_val = 0xFFFFFFFF - frcnt_ori + frcnt_cmp; + } while ((count > 0) && (cmp_val < delay)); + + /* Reset freerun counter */ + if (frcnt_onflg != 1) + return status; + + status = HALMAC_REG_W8(REG_MISC_CTRL, mc_ori); + if (status != HALMAC_RET_SUCCESS) + return status; + status = HALMAC_REG_W8(REG_DUAL_TSF_RST, + HALMAC_REG_R8(REG_DUAL_TSF_RST) | BIT(5)); + return status; +} + +#endif /* HALMAC_8821C_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.h new file mode 100644 index 0000000..72928cf --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_pcie_8821c.h @@ -0,0 +1,45 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_PCIE_8821C_H_ +#define _HALMAC_PCIE_8821C_H_ + +#include "../../halmac_api.h" + +#if (HALMAC_8821C_SUPPORT && HALMAC_PCIE_SUPPORT) + +extern struct halmac_intf_phy_para pcie_gen1_phy_param_8821c[]; +extern struct halmac_intf_phy_para pcie_gen2_phy_param_8821c[]; + +enum halmac_ret_status +mac_pwr_switch_pcie_8821c(struct halmac_adapter *adapter, + enum halmac_mac_power pwr); + +enum halmac_ret_status +pcie_switch_8821c(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg); + +enum halmac_ret_status +phy_cfg_pcie_8821c(struct halmac_adapter *adapter, + enum halmac_intf_phy_platform pltfm); + +enum halmac_ret_status +intf_tun_pcie_8821c(struct halmac_adapter *adapter); + +enum halmac_ret_status +auto_refclk_cal_8821c_pcie(struct halmac_adapter *adapter); + +#endif /* HALMAC_8821C_SUPPORT */ + +#endif/* _HALMAC_PCIE_8821C_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_phy_8821c.c b/hal/halmac/halmac_88xx/halmac_8821c/halmac_phy_8821c.c new file mode 100644 index 0000000..69acb12 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_phy_8821c.c @@ -0,0 +1,76 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "../../halmac_type.h" +#if HALMAC_USB_SUPPORT +#include "halmac_usb_8821c.h" +#endif +#if HALMAC_PCIE_SUPPORT +#include "halmac_pcie_8821c.h" +#endif + +/** + * ============ip sel item list============ + * HALMAC_IP_INTF_PHY + * USB2 : usb2 phy, 1byte value + * USB3 : usb3 phy, 2byte value + * PCIE1 : pcie gen1 mdio, 2byte value + * PCIE2 : pcie gen2 mdio, 2byte value + * HALMAC_IP_SEL_MAC + * USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value + * HALMAC_IP_PCIE_DBI + * USB2 USB3 : none + * PCIE1, PCIE2 : pcie dbi, 1byte value + */ + +#if HALMAC_8821C_SUPPORT + +struct halmac_intf_phy_para usb2_phy_param_8821c[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0xFFFF, 0x00, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_ALL, + HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +struct halmac_intf_phy_para usb3_phy_param_8821c[] = { + /* {offset, value, cut mask, platform mask} */ + {0xFFFF, 0x0000, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_ALL, + HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +struct halmac_intf_phy_para pcie_gen1_phy_param_8821c[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0x0009, 0x6380, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_ALL, + HALMAC_INTF_PHY_PLATFORM_ALL}, + {0xFFFF, 0x0000, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_ALL, + HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +struct halmac_intf_phy_para pcie_gen2_phy_param_8821c[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0xFFFF, 0x0000, + HALMAC_IP_INTF_PHY, + HALMAC_INTF_PHY_CUT_ALL, + HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +#endif /* HALMAC_8821C_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.c b/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.c new file mode 100644 index 0000000..658ac03 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.c @@ -0,0 +1,905 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_pwr_seq_8821c.h" + +#if HALMAC_8821C_SUPPORT + +static struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8821C[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, + {0x004A, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, + {0x0300, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x0301, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8821C[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0020, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0001, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWR_DELAY_MS}, + {0x0000, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), 0}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, + {0x0075, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0006, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, + {0x0075, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, + {0x0006, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, + {0x10C3, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(0), 0}, + {0x0020, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, + {0x0074, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, + {0x0022, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0062, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), + (BIT(7) | BIT(6) | BIT(5))}, + {0x0061, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, + {0x007C, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8821C[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0093, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3), 0}, + {0x001F, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x0049, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0006, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x10C3, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(1), 0}, + {0x0020, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3), 0}, + {0x0000, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8821C[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0007, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0067, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), 0}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, + {0x004A, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0067, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, + {0x0067, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, + {0x004F, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, + {0x0067, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, + {0x0046, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6) }, + {0x0067, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), 0 }, + {0x0046, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, + {0x0062, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, + {0x0081, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_POLLING, BIT(1), 0}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0044, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x0040, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x90}, + {0x0041, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x00}, + {0x0042, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x04}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +/* Card Enable Array */ +struct halmac_wlan_pwr_cfg *card_en_flow_8821c[] = { + TRANS_CARDDIS_TO_CARDEMU_8821C, + TRANS_CARDEMU_TO_ACT_8821C, + NULL +}; + +/* Card Disable Array */ +struct halmac_wlan_pwr_cfg *card_dis_flow_8821c[] = { + TRANS_ACT_TO_CARDEMU_8821C, + TRANS_CARDEMU_TO_CARDDIS_8821C, + NULL +}; + +#if HALMAC_PLATFORM_TESTPROGRAM + +static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8821C[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, + {0x0007, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_POLLING, BIT(1), 0}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +static struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8821C[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0086, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8821C[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0007, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0006, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +static struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8821C[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0005, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), 0}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8821C[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, + {0x0199, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, + {0x019B, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x1138, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, + {0x0194, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0093, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xD6}, + {0x0092, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x60}, + {0x0093, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x93}, + {0x0092, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x60}, + {0x0093, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x2}, + {0x0092, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x60}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x0301, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0522, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x05F8, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05F9, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05FA, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05FB, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0100, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0553, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, + {0x0008, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, + {0x0109, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8821C[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, + {0x0199, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, + {0x019B, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x1138, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, + {0x0194, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0x0093, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xD4}, + {0x0092, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0093, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x91}, + {0x0092, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0093, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x0}, + {0x0092, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x0301, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0522, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x05F8, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05F9, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05FA, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x05FB, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, 0xFF, 0}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), 0}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0100, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0553, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, + {0x0008, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, + {0x0109, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +static struct halmac_wlan_pwr_cfg TRANS_LPS_TO_ACT_8821C[] = { + /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */ + {0x0080, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS}, + {0x0080, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_SDIO_MSK, + HALMAC_PWR_ADDR_SDIO, + HALMAC_PWR_CMD_WRITE, BIT(7), 0}, + {0xFE58, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, + {0xFE58, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_USB_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x04}, + {0x03D9, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS}, + {0x03D9, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_PCI_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(7), 0}, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS}, + {0x0008, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(4), 0}, + {0x0109, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_POLLING, BIT(7), 0}, + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x0100, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, + {0x0002, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, + {0x0522, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x113C, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0x03}, + {0x0124, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0125, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0126, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0127, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, + {0x0090, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(1), 0}, + {0x0101, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + HALMAC_PWR_ADDR_MAC, + HALMAC_PWR_CMD_WRITE, BIT(2), 0}, + {0xFFFF, + HALMAC_PWR_CUT_ALL_MSK, + HALMAC_PWR_INTF_ALL_MSK, + 0, + HALMAC_PWR_CMD_END, 0, 0}, +}; + +/* Suspend Array */ +struct halmac_wlan_pwr_cfg *suspend_flow_8821c[] = { + TRANS_ACT_TO_CARDEMU_8821C, + TRANS_CARDEMU_TO_SUS_8821C, + NULL +}; + +/* Resume Array */ +struct halmac_wlan_pwr_cfg *resume_flow_8821c[] = { + TRANS_SUS_TO_CARDEMU_8821C, + TRANS_CARDEMU_TO_ACT_8821C, + NULL +}; + +/* HWPDN Array - HW behavior */ +struct halmac_wlan_pwr_cfg *hwpdn_flow_8821c[] = { + NULL +}; + +/* Enter LPS - FW behavior */ +struct halmac_wlan_pwr_cfg *enter_lps_flow_8821c[] = { + TRANS_ACT_TO_LPS_8821C, + NULL +}; + +/* Enter Deep LPS - FW behavior */ +struct halmac_wlan_pwr_cfg *enter_dlps_flow_8821c[] = { + TRANS_ACT_TO_DEEP_LPS_8821C, + NULL +}; + +/* Leave LPS -FW behavior */ +struct halmac_wlan_pwr_cfg *leave_lps_flow_8821c[] = { + TRANS_LPS_TO_ACT_8821C, + NULL +}; + +#endif + +#endif /* HALMAC_8821C_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.h new file mode 100644 index 0000000..cf6ee46 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_8821c/halmac_pwr_seq_8821c.h @@ -0,0 +1,37 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef HALMAC_POWER_SEQUENCE_8821C +#define HALMAC_POWER_SEQUENCE_8821C + +#include "../../halmac_pwr_seq_cmd.h" +#include "../../halmac_hw_cfg.h" + +#if HALMAC_8821C_SUPPORT + +#define HALMAC_8821C_PWR_SEQ_VER "V19" + +extern struct halmac_wlan_pwr_cfg *card_dis_flow_8821c[]; +extern struct halmac_wlan_pwr_cfg *card_en_flow_8821c[]; +extern struct halmac_wlan_pwr_cfg *suspend_flow_8821c[]; +extern struct halmac_wlan_pwr_cfg *resume_flow_8821c[]; +extern struct halmac_wlan_pwr_cfg *hwpdn_flow_8821c[]; +extern struct halmac_wlan_pwr_cfg *enter_lps_flow_8821c[]; +extern struct halmac_wlan_pwr_cfg *enter_dlps_flow_8821c[]; +extern struct halmac_wlan_pwr_cfg *leave_lps_flow_8821c[]; + +#endif /* HALMAC_8821C_SUPPORT */ + +#endif diff --git a/hal/halmac/halmac_88xx/halmac_88xx_cfg.h b/hal/halmac/halmac_88xx/halmac_88xx_cfg.h index 87030bd..bad894c 100644 --- a/hal/halmac/halmac_88xx/halmac_88xx_cfg.h +++ b/hal/halmac/halmac_88xx/halmac_88xx_cfg.h @@ -1,163 +1,44 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_88XX_CFG_H_ #define _HALMAC_88XX_CFG_H_ -#include "../halmac_2_platform.h" -#include "../halmac_type.h" -#include "../halmac_hw_cfg.h" #include "../halmac_api.h" -#include "../halmac_bit2.h" -#include "../halmac_reg2.h" -#include "../halmac_pwr_seq_cmd.h" -#include "halmac_func_88xx.h" -#include "halmac_api_88xx.h" -#include "halmac_api_88xx_usb.h" -#include "halmac_api_88xx_pcie.h" -#include "halmac_api_88xx_sdio.h" -#if HALMAC_PLATFORM_TESTPROGRAM -#include "halmisc_api_88xx.h" -#include "halmisc_api_88xx_usb.h" -#include "halmisc_api_88xx_pcie.h" -#include "halmisc_api_88xx_sdio.h" -#endif - -#define HALMAC_SVN_VER_88XX "13359M" - -#define HALMAC_MAJOR_VER_88XX 0x0001 /* major version, ver_1 for async_api */ -#define HALMAC_PROTOTYPE_VER_88XX 0x0003 /* For halmac_api num change or prototype change, increment prototype version */ -#define HALMAC_MINOR_VER_88XX 0x0006 /* else increment minor version */ -#define HALMAC_PATCH_VER_88XX 0x0002 /* patch version */ - -#define HALMAC_C2H_DATA_OFFSET_88XX 10 -#define HALMAC_RX_AGG_ALIGNMENT_SIZE_88XX 8 -#define HALMAC_TX_AGG_ALIGNMENT_SIZE_88XX 8 -#define HALMAC_TX_AGG_BUFF_SIZE_88XX 32768 -#define HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX 80 /*8*10 Bytes*/ -#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_88XX 80 /* should be 8 Byte alignment*/ - -#define HALMAC_TX_PAGE_SIZE_88XX 128 /* PageSize 128Byte */ -#define HALMAC_TX_PAGE_SIZE_2_POWER_88XX 7 /* 128 = 2^7 */ - -#define HALMAC_EXTRA_INFO_BUFF_SIZE_88XX 4096 /*4K*/ -#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX 16384 /*16K*/ -#define HALMAC_FW_OFFLOAD_CMD_SIZE_88XX 12 /*Fw config parameter cmd size, each 12 byte*/ -#define HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX 8 -#define HALMAC_H2C_CMD_SIZE_UNIT_88XX 32 /* Only support 32 byte packet now */ +#if HALMAC_88XX_SUPPORT -#define HALMAC_NLO_INFO_SIZE_88XX 1024 +#define TX_PAGE_SIZE_88XX 128 +#define TX_PAGE_SIZE_SHIFT_88XX 7 /* 128 = 2^7 */ +#define TX_ALIGN_SIZE_88XX 8 +#define SDIO_TX_MAX_SIZE_88XX 31744 +#define RX_BUF_FW_88XX 12288 -/* Download FW */ -#define HALMAC_FW_SIZE_MAX_88XX 0x40000 -#define HALMAC_FWHDR_SIZE_88XX 64 -#define HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX 8 -#define HALMAC_FW_MAX_DL_SIZE_88XX 0x2000 /* need power of 2 */ -/* Max dlfw size can not over 31K, because SDIO HW restriction */ -#define HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX 0x7C00 +#define TX_DESC_SIZE_88XX 48 +#define RX_DESC_SIZE_88XX 24 -#define DLFW_RESTORE_REG_NUM_88XX 9 -#define ID_INFORM_DLEMEM_RDY 0x80 - -/* FW header information */ -#define HALMAC_FWHDR_OFFSET_VERSION_88XX 4 -#define HALMAC_FWHDR_OFFSET_SUBVERSION_88XX 6 -#define HALMAC_FWHDR_OFFSET_SUBINDEX_88XX 7 -#define HALMAC_FWHDR_OFFSET_MONTH_88XX 16 -#define HALMAC_FWHDR_OFFSET_DATE_88XX 17 -#define HALMAC_FWHDR_OFFSET_HOUR_88XX 18 -#define HALMAC_FWHDR_OFFSET_MIN_88XX 19 -#define HALMAC_FWHDR_OFFSET_YEAR_88XX 20 -#define HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX 24 -#define HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX 28 -#define HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX 32 -#define HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX 36 -#define HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX 48 -#define HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX 52 -#define HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX 56 -#define HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX 60 +#define H2C_PKT_SIZE_88XX 32 /* Only support 32 byte packet now */ +#define H2C_PKT_HDR_SIZE_88XX 8 +#define C2H_DATA_OFFSET_88XX 10 +#define C2H_PKT_BUF_88XX 256 /* HW memory address */ -#define HALMAC_OCPBASE_TXBUF_88XX 0x18780000 -#define HALMAC_OCPBASE_DMEM_88XX 0x00200000 -#define HALMAC_OCPBASE_IMEM_88XX 0x00000000 - -/* define the SDIO Bus CLK threshold, for avoiding CMD53 fails that result from SDIO CLK sync to ana_clk fail */ -#define HALMAC_SDIO_CLK_THRESHOLD_88XX 150 /* 150MHz */ -#define HALMAC_SDIO_CLOCK_SPEED_MAX_88XX 208 /* 208MHz */ - -/* MAC clock */ -#define HALMAC_MAC_CLOCK_88XX 80 /* 80M */ - -/* H2C/C2H*/ -#define HALMAC_H2C_CMD_SIZE_88XX 32 -#define HALMAC_H2C_CMD_HDR_SIZE_88XX 8 - -#define HALMAC_PROTECTED_EFUSE_SIZE_88XX 0x60 - -/* Function enable */ -#define HALMAC_FUNCTION_ENABLE_88XX 0xDC - -/* FIFO size & packet size */ -/* #define HALMAC_WOWLAN_PATTERN_SIZE 256 */ - -/* CFEND rate */ -#define HALMAC_BASIC_CFEND_RATE_88XX 0x5 -#define HALMAC_STBC_CFEND_RATE_88XX 0xF - -/* Response rate */ -#define HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX 0xFFFFF -#define HALMAC_RESPONSE_RATE_88XX HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX - -/* Spec SIFS */ -#define HALMAC_SIFS_CCK_PTCL_88XX 16 -#define HALMAC_SIFS_OFDM_PTCL_88XX 16 - -/* Retry limit */ -#define HALMAC_LONG_RETRY_LIMIT_88XX 8 -#define HALMAC_SHORT_RETRY_LIMIT_88XX 7 - -/* Slot, SIFS, PIFS time */ -#define HALMAC_SLOT_TIME_88XX 0x05 -#define HALMAC_PIFS_TIME_88XX 0x19 -#define HALMAC_SIFS_CCK_CTX_88XX 0xA -#define HALMAC_SIFS_OFDM_CTX_88XX 0xA -#define HALMAC_SIFS_CCK_TRX_88XX 0x10 -#define HALMAC_SIFS_OFDM_TRX_88XX 0x10 - -/* TXOP limit */ -#define HALMAC_VO_TXOP_LIMIT_88XX 0x186 -#define HALMAC_VI_TXOP_LIMIT_88XX 0x3BC - -/* NAV */ -#define HALMAC_RDG_NAV_88XX 0x05 -#define HALMAC_TXOP_NAV_88XX 0x1B - -/* TSF */ -#define HALMAC_CCK_RX_TSF_88XX 0x30 -#define HALMAC_OFDM_RX_TSF_88XX 0x30 - -/* Send beacon related */ -#define HALMAC_TBTT_PROHIBIT_88XX 0x04 -#define HALMAC_TBTT_HOLD_TIME_88XX 0x064 -#define HALMAC_DRIVER_EARLY_INT_88XX 0x04 -#define HALMAC_BEACON_DMA_TIM_88XX 0x02 - -/* RX filter */ -#define HALMAC_RX_FILTER0_RECIVE_ALL_88XX 0xFFFFFFF -#define HALMAC_RX_FILTER0_88XX HALMAC_RX_FILTER0_RECIVE_ALL_88XX -#define HALMAC_RX_FILTER_RECIVE_ALL_88XX 0xFFFF -#define HALMAC_RX_FILTER_88XX HALMAC_RX_FILTER_RECIVE_ALL_88XX - -/* RCR */ -#define HALMAC_RCR_CONFIG_88XX 0xE400631E - -/* Security config */ -#define HALMAC_SECURITY_CONFIG_88XX 0x01CC - -/* CCK rate ACK timeout */ -#define HALMAC_ACK_TO_CCK_88XX 0x40 +#define OCPBASE_TXBUF_88XX 0x18780000 +#define OCPBASE_DMEM_88XX 0x00200000 +#define OCPBASE_EMEM_88XX 0x00100000 -/* RX pkt max size */ -#define HALMAC_RXPKT_MAX_SIZE 12288 /* 12K */ -#define HALMAC_RXPKT_MAX_SIZE_BASE512 (HALMAC_RXPKT_MAX_SIZE >> 9) +#endif /* HALMAC_88XX_SUPPORT */ #endif diff --git a/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c new file mode 100644 index 0000000..414b4c9 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c @@ -0,0 +1,395 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_bb_rf_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_common_88xx.h" +#include "halmac_init_88xx.h" + +#if HALMAC_88XX_SUPPORT + +/** + * start_iqk_88xx() -trigger FW IQK + * @adapter : the adapter of halmac + * @param : IQK parameter + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_h2c_header_info hdr_info; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.iqk_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(iqk)\n"); + return HALMAC_RET_BUSY_STATE; + } + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + IQK_SET_CLEAR(h2c_buf, param->clear); + IQK_SET_SEGMENT_IQK(h2c_buf, param->segment_iqk); + + hdr_info.sub_cmd_id = SUB_CMD_ID_IQK; + hdr_info.content_size = 1; + hdr_info.ack = 1; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + adapter->halmac_state.iqk_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_IQK); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * ctrl_pwr_tracking_88xx() -trigger FW power tracking + * @adapter : the adapter of halmac + * @opt : power tracking option + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter, + struct halmac_pwr_tracking_option *opt) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_h2c_header_info hdr_info; + struct halmac_pwr_tracking_para *param; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.pwr_trk_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(pwr tracking)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + PWR_TRK_SET_TYPE(h2c_buf, opt->type); + PWR_TRK_SET_BBSWING_INDEX(h2c_buf, opt->bbswing_index); + + param = &opt->pwr_tracking_para[HALMAC_RF_PATH_A]; + PWR_TRK_SET_ENABLE_A(h2c_buf, param->enable); + PWR_TRK_SET_TX_PWR_INDEX_A(h2c_buf, param->tx_pwr_index); + PWR_TRK_SET_TSSI_VALUE_A(h2c_buf, param->tssi_value); + PWR_TRK_SET_OFFSET_VALUE_A(h2c_buf, param->pwr_tracking_offset_value); + + param = &opt->pwr_tracking_para[HALMAC_RF_PATH_B]; + PWR_TRK_SET_ENABLE_B(h2c_buf, param->enable); + PWR_TRK_SET_TX_PWR_INDEX_B(h2c_buf, param->tx_pwr_index); + PWR_TRK_SET_TSSI_VALUE_B(h2c_buf, param->tssi_value); + PWR_TRK_SET_OFFSET_VALUE_B(h2c_buf, param->pwr_tracking_offset_value); + + param = &opt->pwr_tracking_para[HALMAC_RF_PATH_C]; + PWR_TRK_SET_ENABLE_C(h2c_buf, param->enable); + PWR_TRK_SET_TX_PWR_INDEX_C(h2c_buf, param->tx_pwr_index); + PWR_TRK_SET_TSSI_VALUE_C(h2c_buf, param->tssi_value); + PWR_TRK_SET_OFFSET_VALUE_C(h2c_buf, param->pwr_tracking_offset_value); + + param = &opt->pwr_tracking_para[HALMAC_RF_PATH_D]; + PWR_TRK_SET_ENABLE_D(h2c_buf, param->enable); + PWR_TRK_SET_TX_PWR_INDEX_D(h2c_buf, param->tx_pwr_index); + PWR_TRK_SET_TSSI_VALUE_D(h2c_buf, param->tssi_value); + PWR_TRK_SET_OFFSET_VALUE_D(h2c_buf, param->pwr_tracking_offset_value); + + hdr_info.sub_cmd_id = SUB_CMD_ID_PWR_TRK; + hdr_info.content_size = 20; + hdr_info.ack = 1; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + adapter->halmac_state.pwr_trk_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_POWER_TRACKING); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_iqk_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.iqk_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_pwr_trk_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.pwr_trk_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_psd_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, u8 *data, + u32 *size) +{ + struct halmac_psd_state *state = &adapter->halmac_state.psd_state; + + *proc_status = state->proc_status; + + if (!data) + return HALMAC_RET_NULL_POINTER; + + if (!size) + return HALMAC_RET_NULL_POINTER; + + if (*proc_status == HALMAC_CMD_PROCESS_DONE) { + if (*size < state->data_size) { + *size = state->data_size; + return HALMAC_RET_BUFFER_TOO_SMALL; + } + + *size = state->data_size; + PLTFM_MEMCPY(data, state->data, *size); + } + + return HALMAC_RET_SUCCESS; +} + +/** + * psd_88xx() - trigger fw psd + * @adapter : the adapter of halmac + * @start_psd : start PSD + * @end_psd : end PSD + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_h2c_header_info hdr_info; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.psd_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(psd)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (adapter->halmac_state.psd_state.data) { + PLTFM_FREE(adapter->halmac_state.psd_state.data, + adapter->halmac_state.psd_state.data_size); + adapter->halmac_state.psd_state.data = (u8 *)NULL; + } + + adapter->halmac_state.psd_state.data_size = 0; + adapter->halmac_state.psd_state.seg_size = 0; + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + PSD_SET_START_PSD(h2c_buf, start_psd); + PSD_SET_END_PSD(h2c_buf, end_psd); + + hdr_info.sub_cmd_id = SUB_CMD_ID_PSD; + hdr_info.content_size = 4; + hdr_info.ack = 1; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_PSD); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num; + u8 fw_rc; + struct halmac_iqk_state *state = &adapter->halmac_state.iqk_state; + enum halmac_cmd_process_status proc_status; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, &fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num; + u8 fw_rc; + struct halmac_pwr_tracking_state *state; + enum halmac_cmd_process_status proc_status; + + state = &adapter->halmac_state.pwr_trk_state; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status, + NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status, + &fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seg_id; + u8 seg_size; + u8 seq_num; + u16 total_size; + enum halmac_cmd_process_status proc_status; + struct halmac_psd_state *state = &adapter->halmac_state.psd_state; + + seq_num = (u8)PSD_DATA_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + total_size = (u16)PSD_DATA_GET_TOTAL_SIZE(buf); + seg_id = (u8)PSD_DATA_GET_SEGMENT_ID(buf); + seg_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(buf); + state->data_size = total_size; + + if (!state->data) + state->data = (u8 *)PLTFM_MALLOC(state->data_size); + + if (seg_id == 0) + state->seg_size = seg_size; + + PLTFM_MEMCPY(state->data + seg_id * state->seg_size, + buf + C2H_DATA_OFFSET_88XX, seg_size); + + if (PSD_DATA_GET_END_SEGMENT(buf) == 0) + return HALMAC_RET_SUCCESS; + + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + + PLTFM_EVENT_SIG(HALMAC_FEATURE_PSD, proc_status, state->data, + state->data_size); + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h new file mode 100644 index 0000000..bd107e6 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_BB_RF_88XX_H_ +#define _HALMAC_BB_RF_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param); + +enum halmac_ret_status +ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter, + struct halmac_pwr_tracking_option *opt); + +enum halmac_ret_status +get_iqk_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +enum halmac_ret_status +get_pwr_trk_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +enum halmac_ret_status +get_psd_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, u8 *data, + u32 *size); + +enum halmac_ret_status +psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd); + +enum halmac_ret_status +get_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_BB_RF_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c new file mode 100644 index 0000000..eeb2d85 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c @@ -0,0 +1,1133 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_cfg_wmac_88xx.h" +#include "halmac_88xx_cfg.h" + +#if HALMAC_88XX_SUPPORT + +#define MAC_CLK_SPEED 80 /* 80M */ + +enum mac_clock_hw_def { + MAC_CLK_HW_DEF_80M = 0, + MAC_CLK_HW_DEF_40M = 1, + MAC_CLK_HW_DEF_20M = 2, +}; + +/** + * cfg_mac_addr_88xx() - config mac address + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @addr : mac address + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr) +{ + u32 offset; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (port >= HALMAC_PORTID_NUM) { + PLTFM_MSG_ERR("[ERR]port index >= 5\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + switch (port) { + case HALMAC_PORTID0: + offset = REG_MACID; + break; + case HALMAC_PORTID1: + offset = REG_MACID1; + break; + case HALMAC_PORTID2: + offset = REG_MACID2; + break; + case HALMAC_PORTID3: + offset = REG_MACID3; + break; + case HALMAC_PORTID4: + offset = REG_MACID4; + break; + default: + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low)); + HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_bssid_88xx() - config BSSID + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @addr : bssid + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr) +{ + u32 offset; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (port >= HALMAC_PORTID_NUM) { + PLTFM_MSG_ERR("[ERR]port index > 5\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + switch (port) { + case HALMAC_PORTID0: + offset = REG_BSSID; + break; + case HALMAC_PORTID1: + offset = REG_BSSID1; + break; + case HALMAC_PORTID2: + offset = REG_BSSID2; + break; + case HALMAC_PORTID3: + offset = REG_BSSID3; + break; + case HALMAC_PORTID4: + offset = REG_BSSID4; + break; + default: + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low)); + HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_transmitter_addr_88xx() - config transmitter address + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @addr : + * Author : Alan + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr) +{ + u32 offset; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (port >= HALMAC_PORTID_NUM) { + PLTFM_MSG_ERR("[ERR]port index > 5\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + switch (port) { + case HALMAC_PORTID0: + offset = REG_TRANSMIT_ADDRSS_0; + break; + case HALMAC_PORTID1: + offset = REG_TRANSMIT_ADDRSS_1; + break; + case HALMAC_PORTID2: + offset = REG_TRANSMIT_ADDRSS_2; + break; + case HALMAC_PORTID3: + offset = REG_TRANSMIT_ADDRSS_3; + break; + case HALMAC_PORTID4: + offset = REG_TRANSMIT_ADDRSS_4; + break; + default: + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + HALMAC_REG_W32(offset, rtk_le32_to_cpu(addr->addr_l_h.low)); + HALMAC_REG_W16(offset + 4, rtk_le16_to_cpu(addr->addr_l_h.high)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_net_type_88xx() - config network type + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @addr : mac address + * Author : Alan + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +cfg_net_type_88xx(struct halmac_adapter *adapter, u8 port, + enum halmac_network_type_select net_type) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 value8 = 0; + u8 net_type_tmp = 0; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (net_type == HALMAC_NETWORK_AP) { + if (port >= HALMAC_PORTID1) { + PLTFM_MSG_ERR("[ERR]AP port > 1\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + } + + switch (port) { + case HALMAC_PORTID0: + net_type_tmp = net_type; + value8 = ((HALMAC_REG_R8(REG_CR + 2) & 0xFC) | net_type_tmp); + HALMAC_REG_W8(REG_CR + 2, value8); + break; + case HALMAC_PORTID1: + net_type_tmp = (net_type << 2); + value8 = ((HALMAC_REG_R8(REG_CR + 2) & 0xF3) | net_type_tmp); + HALMAC_REG_W8(REG_CR + 2, value8); + break; + case HALMAC_PORTID2: + net_type_tmp = net_type; + value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xFC) | net_type_tmp); + HALMAC_REG_W8(REG_CR_EXT, value8); + break; + case HALMAC_PORTID3: + net_type_tmp = (net_type << 2); + value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xF3) | net_type_tmp); + HALMAC_REG_W8(REG_CR_EXT, value8); + break; + case HALMAC_PORTID4: + net_type_tmp = (net_type << 4); + value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xCF) | net_type_tmp); + HALMAC_REG_W8(REG_CR_EXT, value8); + break; + default: + break; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_tsf_rst_88xx() - tsf reset + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * Author : Alan + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +cfg_tsf_rst_88xx(struct halmac_adapter *adapter, u8 port) +{ + u8 tsf_rst = 0; + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (port) { + case HALMAC_PORTID0: + tsf_rst = BIT_TSFTR_RST; + break; + case HALMAC_PORTID1: + tsf_rst = BIT_TSFTR_CLI0_RST; + break; + case HALMAC_PORTID2: + tsf_rst = BIT_TSFTR_CLI1_RST; + break; + case HALMAC_PORTID3: + tsf_rst = BIT_TSFTR_CLI2_RST; + break; + case HALMAC_PORTID4: + tsf_rst = BIT_TSFTR_CLI3_RST; + break; + default: + break; + } + + value8 = HALMAC_REG_R8(REG_DUAL_TSF_RST); + HALMAC_REG_W8(REG_DUAL_TSF_RST, value8 | tsf_rst); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_bcn_space_88xx() - config beacon space + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @bcn_space : beacon space + * Author : Alan + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +cfg_bcn_space_88xx(struct halmac_adapter *adapter, u8 port, u32 bcn_space) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u16 bcn_space_real = 0; + u16 value16 = 0; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + bcn_space_real = ((u16)bcn_space); + + switch (port) { + case HALMAC_PORTID0: + HALMAC_REG_W16(REG_MBSSID_BCN_SPACE, bcn_space_real); + break; + case HALMAC_PORTID1: + value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE + 2) & 0xF000; + value16 |= bcn_space_real; + HALMAC_REG_W16(REG_MBSSID_BCN_SPACE + 2, value16); + break; + case HALMAC_PORTID2: + value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE2) & 0xF000; + value16 |= bcn_space_real; + HALMAC_REG_W16(REG_MBSSID_BCN_SPACE2, value16); + break; + case HALMAC_PORTID3: + value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE2 + 2) & 0xF000; + value16 |= bcn_space_real; + HALMAC_REG_W16(REG_MBSSID_BCN_SPACE2 + 2, value16); + break; + case HALMAC_PORTID4: + value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE3) & 0xF000; + value16 |= bcn_space_real; + HALMAC_REG_W16(REG_MBSSID_BCN_SPACE3, value16); + break; + default: + break; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * rw_bcn_ctrl_88xx() - r/w beacon control + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @write_en : 1->write beacon function 0->read beacon function + * @pBcn_ctrl : beacon control info + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en, + struct halmac_bcn_ctrl *ctrl) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 ctrl_value = 0; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (write_en) { + if (ctrl->dis_rx_bssid_fit == 1) + ctrl_value |= BIT_DIS_RX_BSSID_FIT; + + if (ctrl->en_txbcn_rpt == 1) + ctrl_value |= BIT_P0_EN_TXBCN_RPT; + + if (ctrl->dis_tsf_udt == 1) + ctrl_value |= BIT_DIS_TSF_UDT; + + if (ctrl->en_bcn == 1) + ctrl_value |= BIT_EN_BCN_FUNCTION; + + if (ctrl->en_rxbcn_rpt == 1) + ctrl_value |= BIT_P0_EN_RXBCN_RPT; + + if (ctrl->en_p2p_ctwin == 1) + ctrl_value |= BIT_EN_P2P_CTWINDOW; + + if (ctrl->en_p2p_bcn_area == 1) + ctrl_value |= BIT_EN_P2P_BCNQ_AREA; + + switch (port) { + case HALMAC_PORTID0: + HALMAC_REG_W8(REG_BCN_CTRL, ctrl_value); + break; + case HALMAC_PORTID1: + HALMAC_REG_W8(REG_BCN_CTRL_CLINT0, ctrl_value); + break; + case HALMAC_PORTID2: + HALMAC_REG_W8(REG_BCN_CTRL_CLINT1, ctrl_value); + break; + case HALMAC_PORTID3: + HALMAC_REG_W8(REG_BCN_CTRL_CLINT2, ctrl_value); + break; + case HALMAC_PORTID4: + HALMAC_REG_W8(REG_BCN_CTRL_CLINT3, ctrl_value); + break; + default: + break; + } + + } else { + switch (port) { + case HALMAC_PORTID0: + ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL); + break; + case HALMAC_PORTID1: + ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT0); + break; + case HALMAC_PORTID2: + ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT1); + break; + case HALMAC_PORTID3: + ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT2); + break; + case HALMAC_PORTID4: + ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT3); + break; + default: + break; + } + + if (ctrl_value & BIT_EN_P2P_BCNQ_AREA) + ctrl->en_p2p_bcn_area = 1; + else + ctrl->en_p2p_bcn_area = 0; + + if (ctrl_value & BIT_EN_P2P_CTWINDOW) + ctrl->en_p2p_ctwin = 1; + else + ctrl->en_p2p_ctwin = 0; + + if (ctrl_value & BIT_P0_EN_RXBCN_RPT) + ctrl->en_rxbcn_rpt = 1; + else + ctrl->en_rxbcn_rpt = 0; + + if (ctrl_value & BIT_EN_BCN_FUNCTION) + ctrl->en_bcn = 1; + else + ctrl->en_bcn = 0; + + if (ctrl_value & BIT_DIS_TSF_UDT) + ctrl->dis_tsf_udt = 1; + else + ctrl->dis_tsf_udt = 0; + + if (ctrl_value & BIT_P0_EN_TXBCN_RPT) + ctrl->en_txbcn_rpt = 1; + else + ctrl->en_txbcn_rpt = 0; + + if (ctrl_value & BIT_DIS_RX_BSSID_FIT) + ctrl->dis_rx_bssid_fit = 1; + else + ctrl->dis_rx_bssid_fit = 0; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_multicast_addr_88xx() - config multicast address + * @adapter : the adapter of halmac + * @addr : multicast address + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_multicast_addr_88xx(struct halmac_adapter *adapter, + union halmac_wlan_addr *addr) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + HALMAC_REG_W32(REG_MAR, rtk_le32_to_cpu(addr->addr_l_h.low)); + HALMAC_REG_W16(REG_MAR + 4, rtk_le16_to_cpu(addr->addr_l_h.high)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_operation_mode_88xx() - config operation mode + * @adapter : the adapter of halmac + * @mode : 802.11 standard(b/g/n/ac) + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_operation_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wireless_mode mode) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_ch_bw_88xx() - config channel & bandwidth + * @adapter : the adapter of halmac + * @ch : WLAN channel, support 2.4G & 5G + * @idx : primary channel index, idx1, idx2, idx3, idx4 + * @bw : band width, 20, 40, 80, 160, 5 ,10 + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_ch_bw_88xx(struct halmac_adapter *adapter, u8 ch, + enum halmac_pri_ch_idx idx, enum halmac_bw bw) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + cfg_pri_ch_idx_88xx(adapter, idx); + cfg_bw_88xx(adapter, bw); + cfg_ch_88xx(adapter, ch); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +cfg_ch_88xx(struct halmac_adapter *adapter, u8 ch) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + value8 = HALMAC_REG_R8(REG_CCK_CHECK); + value8 = value8 & (~(BIT(7))); + + if (ch > 35) + value8 = value8 | BIT(7); + + HALMAC_REG_W8(REG_CCK_CHECK, value8); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +cfg_pri_ch_idx_88xx(struct halmac_adapter *adapter, enum halmac_pri_ch_idx idx) +{ + u8 txsc40 = 0, txsc20 = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + txsc20 = idx; + if (txsc20 == HALMAC_CH_IDX_1 || txsc20 == HALMAC_CH_IDX_3) + txsc40 = 9; + else + txsc40 = 10; + + HALMAC_REG_W8(REG_DATA_SC, BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_bw_88xx() - config bandwidth + * @adapter : the adapter of halmac + * @bw : band width, 20, 40, 80, 160, 5 ,10 + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw) +{ + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + value32 = HALMAC_REG_R32(REG_WMAC_TRXPTCL_CTL); + value32 = value32 & (~(BIT(7) | BIT(8))); + + switch (bw) { + case HALMAC_BW_80: + value32 = value32 | BIT(8); + break; + case HALMAC_BW_40: + value32 = value32 | BIT(7); + break; + case HALMAC_BW_20: + case HALMAC_BW_10: + case HALMAC_BW_5: + break; + default: + break; + } + + HALMAC_REG_W32(REG_WMAC_TRXPTCL_CTL, value32); + + /* TODO:Move to change mac clk api later... */ + value32 = HALMAC_REG_R32(REG_AFE_CTRL1) & ~(BIT(20) | BIT(21)); + value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL); + HALMAC_REG_W32(REG_AFE_CTRL1, value32); + + HALMAC_REG_W8(REG_USTIME_TSF, MAC_CLK_SPEED); + HALMAC_REG_W8(REG_USTIME_EDCA, MAC_CLK_SPEED); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +void +enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable) +{ + u8 value8; + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (enable == 1) { + value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN); + value8 = value8 | BIT(0) | BIT(1); + HALMAC_REG_W8(REG_SYS_FUNC_EN, value8); + + value8 = HALMAC_REG_R8(REG_RF_CTRL); + value8 = value8 | BIT(0) | BIT(1) | BIT(2); + HALMAC_REG_W8(REG_RF_CTRL, value8); + + value32 = HALMAC_REG_R32(REG_WLRF1); + value32 = value32 | BIT(24) | BIT(25) | BIT(26); + HALMAC_REG_W32(REG_WLRF1, value32); + } else { + value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN); + value8 = value8 & (~(BIT(0) | BIT(1))); + HALMAC_REG_W8(REG_SYS_FUNC_EN, value8); + + value8 = HALMAC_REG_R8(REG_RF_CTRL); + value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2))); + HALMAC_REG_W8(REG_RF_CTRL, value8); + + value32 = HALMAC_REG_R32(REG_WLRF1); + value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26))); + HALMAC_REG_W32(REG_WLRF1, value32); + } +} + +/** + * cfg_la_mode_88xx() - config la mode + * @adapter : the adapter of halmac + * @mode : + * disable : no TXFF space reserved for LA debug + * partial : partial TXFF space is reserved for LA debug + * full : all TXFF space is reserved for LA debug + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_la_mode_88xx(struct halmac_adapter *adapter, enum halmac_la_mode mode) +{ + if (adapter->api_registry.la_mode_en == 0) + return HALMAC_RET_NOT_SUPPORT; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + adapter->txff_alloc.la_mode = mode; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_rxfifo_expand_mode_88xx() - rx fifo expanding + * @adapter : the adapter of halmac + * @mode : + * disable : normal mode + * 1 block : Rx FIFO + 1 FIFO block; Tx fifo - 1 FIFO block + * 2 block : Rx FIFO + 2 FIFO block; Tx fifo - 2 FIFO block + * 3 block : Rx FIFO + 3 FIFO block; Tx fifo - 3 FIFO block + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_rxfifo_expand_mode_88xx(struct halmac_adapter *adapter, + enum halmac_rx_fifo_expanding_mode mode) +{ + if (adapter->api_registry.rx_exp_en == 0) + return HALMAC_RET_NOT_SUPPORT; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + adapter->txff_alloc.rx_fifo_exp_mode = mode; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +config_security_88xx(struct halmac_adapter *adapter, + struct halmac_security_setting *setting) +{ + u8 sec_cfg; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + HALMAC_REG_W16_SET(REG_CR, BIT_MAC_SEC_EN); + + if (setting->compare_keyid == 1) { + HALMAC_REG_W8_SET(REG_SECCFG + 1, BIT(0)); + adapter->hw_cfg_info.chk_security_keyid = 1; + } else { + adapter->hw_cfg_info.chk_security_keyid = 0; + } + + sec_cfg = HALMAC_REG_R8(REG_SECCFG); + + /* BC/MC uses default key */ + /* cam entry 0~3, kei id = 0 -> entry0, kei id = 1 -> entry1... */ + sec_cfg |= (BIT_TXBCUSEDK | BIT_RXBCUSEDK); + + if (setting->tx_encryption == 1) + sec_cfg |= BIT_TXENC; + else + sec_cfg &= ~BIT_TXENC; + + if (setting->rx_decryption == 1) + sec_cfg |= BIT_RXDEC; + else + sec_cfg &= ~BIT_RXDEC; + + HALMAC_REG_W8(REG_SECCFG, sec_cfg); + + if (setting->bip_enable == 1) { + if (adapter->chip_id == HALMAC_CHIP_ID_8822B) + return HALMAC_RET_BIP_NO_SUPPORT; +#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + sec_cfg = HALMAC_REG_R8(REG_WSEC_OPTION + 2); + + if (setting->tx_encryption == 1) + sec_cfg |= (BIT(3) | BIT(5)); + else + sec_cfg &= ~(BIT(3) | BIT(5)); + + if (setting->rx_decryption == 1) + sec_cfg |= (BIT(4) | BIT(6)); + else + sec_cfg &= ~(BIT(4) | BIT(6)); + + HALMAC_REG_W8(REG_WSEC_OPTION + 2, sec_cfg); +#endif + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +u8 +get_used_cam_entry_num_88xx(struct halmac_adapter *adapter, + enum hal_security_type sec_type) +{ + u8 entry_num; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (sec_type) { + case HAL_SECURITY_TYPE_WEP40: + case HAL_SECURITY_TYPE_WEP104: + case HAL_SECURITY_TYPE_TKIP: + case HAL_SECURITY_TYPE_AES128: + case HAL_SECURITY_TYPE_GCMP128: + case HAL_SECURITY_TYPE_GCMSMS4: + case HAL_SECURITY_TYPE_BIP: + entry_num = 1; + break; + case HAL_SECURITY_TYPE_WAPI: + case HAL_SECURITY_TYPE_AES256: + case HAL_SECURITY_TYPE_GCMP256: + entry_num = 2; + break; + default: + entry_num = 0; + break; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return entry_num; +} + +enum halmac_ret_status +write_cam_88xx(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_info *info) +{ + u32 i; + u32 cmd = 0x80010000; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + struct halmac_cam_entry_format *fmt = NULL; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (idx >= adapter->hw_cfg_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; + + if (info->key_id > 3) + return HALMAC_RET_FAIL; + + fmt = (struct halmac_cam_entry_format *)PLTFM_MALLOC(sizeof(*fmt)); + if (!fmt) + return HALMAC_RET_NULL_POINTER; + PLTFM_MEMSET(fmt, 0x00, sizeof(*fmt)); + + if (adapter->hw_cfg_info.chk_security_keyid == 1) + fmt->key_id = info->key_id; + fmt->valid = info->valid; + PLTFM_MEMCPY(fmt->mac_address, info->mac_address, 6); + PLTFM_MEMCPY(fmt->key, info->key, 16); + + switch (info->security_type) { + case HAL_SECURITY_TYPE_NONE: + fmt->type = 0; + break; + case HAL_SECURITY_TYPE_WEP40: + fmt->type = 1; + break; + case HAL_SECURITY_TYPE_WEP104: + fmt->type = 5; + break; + case HAL_SECURITY_TYPE_TKIP: + fmt->type = 2; + break; + case HAL_SECURITY_TYPE_AES128: + fmt->type = 4; + break; + case HAL_SECURITY_TYPE_WAPI: + fmt->type = 6; + break; + case HAL_SECURITY_TYPE_AES256: + fmt->type = 4; + fmt->ext_sectype = 1; + break; + case HAL_SECURITY_TYPE_GCMP128: + fmt->type = 7; + break; + case HAL_SECURITY_TYPE_GCMP256: + case HAL_SECURITY_TYPE_GCMSMS4: + fmt->type = 7; + fmt->ext_sectype = 1; + break; + case HAL_SECURITY_TYPE_BIP: + fmt->type = (info->unicast == 1) ? 4 : 0; + fmt->mgnt = 1; + fmt->grp = (info->unicast == 1) ? 0 : 1; + break; + default: + PLTFM_FREE(fmt, sizeof(*fmt)); + return HALMAC_RET_FAIL; + } + + for (i = 0; i < 8; i++) { + HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i)); + HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i)); + } + + if (info->security_type == HAL_SECURITY_TYPE_WAPI || + info->security_type == HAL_SECURITY_TYPE_AES256 || + info->security_type == HAL_SECURITY_TYPE_GCMP256 || + info->security_type == HAL_SECURITY_TYPE_GCMSMS4) { + fmt->mic = 1; + PLTFM_MEMCPY(fmt->key, info->key_ext, 16); + idx++; + for (i = 0; i < 8; i++) { + HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i)); + HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i)); + } + } + + PLTFM_FREE(fmt, sizeof(*fmt)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +read_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_format *content) +{ + u32 i; + u32 cmd = 0x80000000; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (idx >= adapter->hw_cfg_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; + + for (i = 0; i < 8; i++) { + HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i)); + *((u32 *)content + i) = HALMAC_REG_R32(REG_CAMREAD); + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +clear_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx) +{ + u32 i; + u32 cmd = 0x80010000; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + struct halmac_cam_entry_format *fmt = NULL; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (idx >= adapter->hw_cfg_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; + + fmt = (struct halmac_cam_entry_format *)PLTFM_MALLOC(sizeof(*fmt)); + if (!fmt) + return HALMAC_RET_NULL_POINTER; + PLTFM_MEMSET(fmt, 0x00, sizeof(*fmt)); + + for (i = 0; i < 8; i++) { + HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i)); + HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i)); + } + + PLTFM_FREE(fmt, sizeof(*fmt)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +void +rx_shift_88xx(struct halmac_adapter *adapter, u8 enable) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_TXDMA_PQ_MAP); + + if (enable == 1) + HALMAC_REG_W8(REG_TXDMA_PQ_MAP, value8 | BIT(1)); + else + HALMAC_REG_W8(REG_TXDMA_PQ_MAP, value8 & ~(BIT(1))); +} + +/** + * cfg_edca_para_88xx() - config edca parameter + * @adapter : the adapter of halmac + * @acq_id : VO/VI/BE/BK + * @param : aifs, cw, txop limit + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_edca_para_88xx(struct halmac_adapter *adapter, enum halmac_acq_id acq_id, + struct halmac_edca_para *param) +{ + u32 offset; + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (acq_id) { + case HALMAC_ACQ_ID_VO: + offset = REG_EDCA_VO_PARAM; + break; + case HALMAC_ACQ_ID_VI: + offset = REG_EDCA_VI_PARAM; + break; + case HALMAC_ACQ_ID_BE: + offset = REG_EDCA_BE_PARAM; + break; + case HALMAC_ACQ_ID_BK: + offset = REG_EDCA_BK_PARAM; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + param->txop_limit &= 0x7FF; + value32 = (param->aifs) | (param->cw << 8) | (param->txop_limit << 16); + + HALMAC_REG_W32(offset, value32); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +void +rx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_RCR + 2); + + if (enable == 1) + HALMAC_REG_W8(REG_RCR + 2, value8 & ~(BIT(3))); + else + HALMAC_REG_W8(REG_RCR + 2, value8 | BIT(3)); +} + +enum halmac_ret_status +rx_cut_amsdu_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_cut_amsdu_cfg *cfg) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +enum halmac_ret_status +fast_edca_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_fast_edca_cfg *cfg) +{ + u16 value16; + u32 offset; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (cfg->acq_id) { + case HALMAC_ACQ_ID_VO: + offset = REG_FAST_EDCA_VOVI_SETTING; + break; + case HALMAC_ACQ_ID_VI: + offset = REG_FAST_EDCA_VOVI_SETTING + 2; + break; + case HALMAC_ACQ_ID_BE: + offset = REG_FAST_EDCA_BEBK_SETTING; + break; + case HALMAC_ACQ_ID_BK: + offset = REG_FAST_EDCA_BEBK_SETTING + 2; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + value16 = HALMAC_REG_R16(offset); + value16 &= 0xFF; + value16 = value16 | (cfg->queue_to << 8); + + HALMAC_REG_W16(offset, value16); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * get_mac_addr_88xx() - get mac address + * @adapter : the adapter of halmac + * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @addr : mac address + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr) +{ + u16 mac_addr_h; + u32 mac_addr_l; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (port >= HALMAC_PORTID_NUM) { + PLTFM_MSG_ERR("[ERR]port index >= 5\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + switch (port) { + case HALMAC_PORTID0: + mac_addr_l = HALMAC_REG_R32(REG_MACID); + mac_addr_h = HALMAC_REG_R16(REG_MACID + 4); + break; + case HALMAC_PORTID1: + mac_addr_l = HALMAC_REG_R32(REG_MACID1); + mac_addr_h = HALMAC_REG_R16(REG_MACID1 + 4); + break; + case HALMAC_PORTID2: + mac_addr_l = HALMAC_REG_R32(REG_MACID2); + mac_addr_h = HALMAC_REG_R16(REG_MACID2 + 4); + break; + case HALMAC_PORTID3: + mac_addr_l = HALMAC_REG_R32(REG_MACID3); + mac_addr_h = HALMAC_REG_R16(REG_MACID3 + 4); + break; + case HALMAC_PORTID4: + mac_addr_l = HALMAC_REG_R32(REG_MACID4); + mac_addr_h = HALMAC_REG_R16(REG_MACID4 + 4); + break; + default: + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + addr->addr_l_h.low = rtk_cpu_to_le32(mac_addr_l); + addr->addr_l_h.high = rtk_cpu_to_le16(mac_addr_h); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +void +rts_full_bw_88xx(struct halmac_adapter *adapter, u8 enable) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_INIRTS_RATE_SEL); + + if (enable == 1) + HALMAC_REG_W8(REG_INIRTS_RATE_SEL, value8 | BIT(5)); + else + HALMAC_REG_W8(REG_INIRTS_RATE_SEL, value8 & ~(BIT(5))); +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h new file mode 100644 index 0000000..e5f26b1 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h @@ -0,0 +1,126 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_CFG_WMAC_88XX_H_ +#define _HALMAC_CFG_WMAC_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + +enum halmac_ret_status +cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + +enum halmac_ret_status +cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + +enum halmac_ret_status +cfg_net_type_88xx(struct halmac_adapter *adapter, u8 port, + enum halmac_network_type_select net_type); + +enum halmac_ret_status +cfg_tsf_rst_88xx(struct halmac_adapter *adapter, u8 port); + +enum halmac_ret_status +cfg_bcn_space_88xx(struct halmac_adapter *adapter, u8 port, u32 bcn_space); + +enum halmac_ret_status +rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en, + struct halmac_bcn_ctrl *ctrl); + +enum halmac_ret_status +cfg_multicast_addr_88xx(struct halmac_adapter *adapter, + union halmac_wlan_addr *addr); + +enum halmac_ret_status +cfg_operation_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wireless_mode mode); + +enum halmac_ret_status +cfg_ch_bw_88xx(struct halmac_adapter *adapter, u8 ch, + enum halmac_pri_ch_idx idx, enum halmac_bw bw); + +enum halmac_ret_status +cfg_ch_88xx(struct halmac_adapter *adapter, u8 ch); + +enum halmac_ret_status +cfg_pri_ch_idx_88xx(struct halmac_adapter *adapter, enum halmac_pri_ch_idx idx); + +enum halmac_ret_status +cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw); + +void +enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable); + +enum halmac_ret_status +cfg_la_mode_88xx(struct halmac_adapter *adapter, enum halmac_la_mode mode); + +enum halmac_ret_status +cfg_rxfifo_expand_mode_88xx(struct halmac_adapter *adapter, + enum halmac_rx_fifo_expanding_mode mode); + +enum halmac_ret_status +config_security_88xx(struct halmac_adapter *adapter, + struct halmac_security_setting *setting); + +u8 +get_used_cam_entry_num_88xx(struct halmac_adapter *adapter, + enum hal_security_type sec_type); + +enum halmac_ret_status +write_cam_88xx(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_info *info); + +enum halmac_ret_status +read_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_format *content); + +enum halmac_ret_status +clear_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx); + +void +rx_shift_88xx(struct halmac_adapter *adapter, u8 enable); + +enum halmac_ret_status +cfg_edca_para_88xx(struct halmac_adapter *adapter, enum halmac_acq_id acq_id, + struct halmac_edca_para *param); + +void +rx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable); + +enum halmac_ret_status +rx_cut_amsdu_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_cut_amsdu_cfg *cfg); + +enum halmac_ret_status +fast_edca_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_fast_edca_cfg *cfg); + +enum halmac_ret_status +get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + +void +rts_full_bw_88xx(struct halmac_adapter *adapter, u8 enable); + +#endif/* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_CFG_WMAC_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_common_88xx.c b/hal/halmac/halmac_88xx/halmac_common_88xx.c new file mode 100644 index 0000000..2119c34 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_common_88xx.c @@ -0,0 +1,2895 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_common_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_init_88xx.h" +#include "halmac_cfg_wmac_88xx.h" +#include "halmac_efuse_88xx.h" +#include "halmac_bb_rf_88xx.h" +#if HALMAC_USB_SUPPORT +#include "halmac_usb_88xx.h" +#endif +#if HALMAC_SDIO_SUPPORT +#include "halmac_sdio_88xx.h" +#endif +#if HALMAC_PCIE_SUPPORT +#include "halmac_pcie_88xx.h" +#endif +#include "halmac_mimo_88xx.h" + +#if HALMAC_88XX_SUPPORT + +#define CFG_PARAM_H2C_INFO_SIZE 12 +#define ORIGINAL_H2C_CMD_SIZE 8 + +#define WLHDR_PROT_VER 0 + +#define WLHDR_TYPE_MGMT 0 +#define WLHDR_TYPE_CTRL 1 +#define WLHDR_TYPE_DATA 2 + +/* mgmt frame */ +#define WLHDR_SUB_TYPE_ASSOC_REQ 0 +#define WLHDR_SUB_TYPE_ASSOC_RSPNS 1 +#define WLHDR_SUB_TYPE_REASSOC_REQ 2 +#define WLHDR_SUB_TYPE_REASSOC_RSPNS 3 +#define WLHDR_SUB_TYPE_PROBE_REQ 4 +#define WLHDR_SUB_TYPE_PROBE_RSPNS 5 +#define WLHDR_SUB_TYPE_BCN 8 +#define WLHDR_SUB_TYPE_DISASSOC 10 +#define WLHDR_SUB_TYPE_AUTH 11 +#define WLHDR_SUB_TYPE_DEAUTH 12 +#define WLHDR_SUB_TYPE_ACTION 13 +#define WLHDR_SUB_TYPE_ACTION_NOACK 14 + +/* ctrl frame */ +#define WLHDR_SUB_TYPE_BF_RPT_POLL 4 +#define WLHDR_SUB_TYPE_NDPA 5 + +/* data frame */ +#define WLHDR_SUB_TYPE_DATA 0 +#define WLHDR_SUB_TYPE_NULL 4 +#define WLHDR_SUB_TYPE_QOS_DATA 8 +#define WLHDR_SUB_TYPE_QOS_NULL 12 + +#define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 + +struct wlhdr_frame_ctrl { + u16 protocol:2; + u16 type:2; + u16 sub_type:4; + u16 to_ds:1; + u16 from_ds:1; + u16 more_frag:1; + u16 retry:1; + u16 pwr_mgmt:1; + u16 more_data:1; + u16 protect_frame:1; + u16 order:1; +}; + +static enum halmac_ret_status +parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_c2h_dbg_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_h2c_ack_cfg_param_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, + u32 size); + +static enum halmac_ret_status +get_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +static enum halmac_ret_status +malloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo); + +static enum halmac_cmd_construct_state +cfg_param_cmd_cnstr_state_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +proc_cfg_param_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *param, u8 full_fifo); + +static enum halmac_ret_status +send_cfg_param_h2c_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +cnv_cfg_param_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state); + +static enum halmac_ret_status +add_param_buf_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *param, u8 *buf, + u8 *end_cmd); + +static enum halmac_ret_status +gen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff); + +static enum halmac_ret_status +send_h2c_update_packet_88xx(struct halmac_adapter *adapter, + enum halmac_packet_id pkt_id, u8 *pkt, u32 size); + +static enum halmac_ret_status +send_bt_coex_cmd_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 ack); + +static enum halmac_ret_status +read_buf_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + enum hal_fifo_sel sel, u8 *data); + +static enum halmac_cmd_construct_state +scan_cmd_cnstr_state_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +cnv_scan_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state); + +static enum halmac_ret_status +proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter, + struct halmac_ch_switch_option *opt); + +static enum halmac_ret_status +proc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info); + +static enum halmac_ret_status +get_cfg_param_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +static enum halmac_ret_status +get_ch_switch_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +static enum halmac_ret_status +get_update_packet_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +static enum halmac_ret_status +pwr_sub_seq_parser_88xx(struct halmac_adapter *adapter, u8 cut, u8 intf, + struct halmac_wlan_pwr_cfg *cmd); + +static void +pwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state); + +static enum halmac_ret_status +pwr_cmd_polling_88xx(struct halmac_adapter *adapter, + struct halmac_wlan_pwr_cfg *cmd); + +static void +get_pq_mapping_88xx(struct halmac_adapter *adapter, + struct halmac_rqpn_map *mapping); + +static void +dump_reg_sdio_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +wlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf); + +static u8 +wlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr); + +static u8 +wlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr); + +static u8 +wlhdr_data_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr); + +static void +dump_reg_88xx(struct halmac_adapter *adapter); + +/** + * ofld_func_cfg_88xx() - config offload function + * @adapter : the adapter of halmac + * @info : offload function information + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +ofld_func_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_ofld_func_info *info) +{ + if (adapter->intf == HALMAC_INTERFACE_SDIO && + info->rsvd_pg_drv_buf_max_sz > SDIO_TX_MAX_SIZE_88XX) + return HALMAC_RET_FAIL; + + adapter->pltfm_info.malloc_size = info->halmac_malloc_max_sz; + adapter->pltfm_info.rsvd_pg_size = info->rsvd_pg_drv_buf_max_sz; + + return HALMAC_RET_SUCCESS; +} + +/** + * dl_drv_rsvd_page_88xx() - download packet to rsvd page + * @adapter : the adapter of halmac + * @pg_offset : page offset of driver's rsvd page + * @halmac_buf : data to be downloaded, tx_desc is not included + * @halmac_size : data size to be downloaded + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +dl_drv_rsvd_page_88xx(struct halmac_adapter *adapter, u8 pg_offset, u8 *buf, + u32 size) +{ + enum halmac_ret_status status; + u32 pg_size; + u32 pg_num = 0; + u16 pg_addr = 0; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + pg_size = adapter->hw_cfg_info.page_size; + pg_num = size / pg_size + ((size & (pg_size - 1)) ? 1 : 0); + if (pg_offset + pg_num > adapter->txff_alloc.rsvd_drv_pg_num) { + PLTFM_MSG_ERR("[ERR] pkt overflow!!\n"); + return HALMAC_RET_DRV_DL_ERR; + } + + pg_addr = adapter->txff_alloc.rsvd_drv_addr + pg_offset; + + status = dl_rsvd_page_88xx(adapter, pg_addr, buf, size); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd page fail!!\n"); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +dl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf, + u32 size) +{ + u8 restore[2]; + u8 value8; + u16 rsvd_pg_head; + u32 cnt; + enum halmac_rsvd_pg_state *state = &adapter->halmac_state.rsvd_pg_state; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (size == 0) { + PLTFM_MSG_TRACE("[TRACE]pkt size = 0\n"); + return HALMAC_RET_ZERO_LEN_RSVD_PACKET; + } + + if (*state == HALMAC_RSVD_PG_STATE_BUSY) + return HALMAC_RET_BUSY_STATE; + + *state = HALMAC_RSVD_PG_STATE_BUSY; + + pg_addr &= BIT_MASK_BCN_HEAD_1_V1; + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, (u16)(pg_addr | BIT(15))); + + value8 = HALMAC_REG_R8(REG_CR + 1); + restore[0] = value8; + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_W8(REG_CR + 1, value8); + + value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2); + restore[1] = value8; + value8 = (u8)(value8 & ~(BIT(6))); + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8); + + if (PLTFM_SEND_RSVD_PAGE(buf, size) == 0) { + PLTFM_MSG_ERR("[ERR]send rvsd pg(pltfm)!!\n"); + status = HALMAC_RET_DL_RSVD_PAGE_FAIL; + goto DL_RSVD_PG_END; + } + + cnt = 1000; + while (!(HALMAC_REG_R8(REG_FIFOPAGE_CTRL_2 + 1) & BIT(7))) { + PLTFM_DELAY_US(10); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]bcn valid!!\n"); + status = HALMAC_RET_POLLING_BCN_VALID_FAIL; + break; + } + } +DL_RSVD_PG_END: + rsvd_pg_head = adapter->txff_alloc.rsvd_boundary; + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_head | BIT(15)); + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[1]); + HALMAC_REG_W8(REG_CR + 1, restore[0]); + + *state = HALMAC_RSVD_PG_STATE_IDLE; + + return status; +} + +enum halmac_ret_status +get_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (hw_id) { + case HALMAC_HW_RQPN_MAPPING: + get_pq_mapping_88xx(adapter, (struct halmac_rqpn_map *)value); + break; + case HALMAC_HW_EFUSE_SIZE: + *(u32 *)value = adapter->hw_cfg_info.efuse_size; + break; + case HALMAC_HW_EEPROM_SIZE: + *(u32 *)value = adapter->hw_cfg_info.eeprom_size; + break; + case HALMAC_HW_BT_BANK_EFUSE_SIZE: + *(u32 *)value = adapter->hw_cfg_info.bt_efuse_size; + break; + case HALMAC_HW_BT_BANK1_EFUSE_SIZE: + case HALMAC_HW_BT_BANK2_EFUSE_SIZE: + *(u32 *)value = 0; + break; + case HALMAC_HW_TXFIFO_SIZE: + *(u32 *)value = adapter->hw_cfg_info.tx_fifo_size; + break; + case HALMAC_HW_RXFIFO_SIZE: + *(u32 *)value = adapter->hw_cfg_info.rx_fifo_size; + break; + case HALMAC_HW_RSVD_PG_BNDY: + *(u16 *)value = adapter->txff_alloc.rsvd_drv_addr; + break; + case HALMAC_HW_CAM_ENTRY_NUM: + *(u8 *)value = adapter->hw_cfg_info.cam_entry_num; + break; + case HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE: + get_efuse_available_size_88xx(adapter, (u32 *)value); + break; + case HALMAC_HW_IC_VERSION: + *(u8 *)value = adapter->chip_ver; + break; + case HALMAC_HW_PAGE_SIZE: + *(u32 *)value = adapter->hw_cfg_info.page_size; + break; + case HALMAC_HW_TX_AGG_ALIGN_SIZE: + *(u16 *)value = adapter->hw_cfg_info.tx_align_size; + break; + case HALMAC_HW_RX_AGG_ALIGN_SIZE: + *(u8 *)value = 8; + break; + case HALMAC_HW_DRV_INFO_SIZE: + *(u8 *)value = adapter->drv_info_size; + break; + case HALMAC_HW_TXFF_ALLOCATION: + PLTFM_MEMCPY(value, &adapter->txff_alloc, + sizeof(struct halmac_txff_allocation)); + break; + case HALMAC_HW_RSVD_EFUSE_SIZE: + *(u32 *)value = get_rsvd_efuse_size_88xx(adapter); + break; + case HALMAC_HW_FW_HDR_SIZE: + *(u32 *)value = WLAN_FW_HDR_SIZE; + break; + case HALMAC_HW_TX_DESC_SIZE: + *(u32 *)value = adapter->hw_cfg_info.txdesc_size; + break; + case HALMAC_HW_RX_DESC_SIZE: + *(u32 *)value = adapter->hw_cfg_info.rxdesc_size; + break; + case HALMAC_HW_ORI_H2C_SIZE: + *(u32 *)value = ORIGINAL_H2C_CMD_SIZE; + break; + case HALMAC_HW_RSVD_DRV_PGNUM: + *(u16 *)value = adapter->txff_alloc.rsvd_drv_pg_num; + break; + case HALMAC_HW_TX_PAGE_SIZE: + *(u16 *)value = TX_PAGE_SIZE_88XX; + break; + case HALMAC_HW_USB_TXAGG_DESC_NUM: + *(u8 *)value = adapter->hw_cfg_info.usb_txagg_num; + break; + case HALMAC_HW_AC_OQT_SIZE: + *(u8 *)value = adapter->hw_cfg_info.ac_oqt_size; + break; + case HALMAC_HW_NON_AC_OQT_SIZE: + *(u8 *)value = adapter->hw_cfg_info.non_ac_oqt_size; + break; + case HALMAC_HW_AC_QUEUE_NUM: + *(u8 *)value = adapter->hw_cfg_info.acq_num; + break; + case HALMAC_HW_PWR_STATE: + pwr_state_88xx(adapter, (enum halmac_mac_power *)value); + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static void +get_pq_mapping_88xx(struct halmac_adapter *adapter, + struct halmac_rqpn_map *mapping) +{ + mapping->dma_map_vo = adapter->pq_map[HALMAC_PQ_MAP_VO]; + mapping->dma_map_vi = adapter->pq_map[HALMAC_PQ_MAP_VI]; + mapping->dma_map_be = adapter->pq_map[HALMAC_PQ_MAP_BE]; + mapping->dma_map_bk = adapter->pq_map[HALMAC_PQ_MAP_BK]; + mapping->dma_map_mg = adapter->pq_map[HALMAC_PQ_MAP_MG]; + mapping->dma_map_hi = adapter->pq_map[HALMAC_PQ_MAP_HI]; +} + +/** + * set_hw_value_88xx() -set hw config value + * @adapter : the adapter of halmac + * @hw_id : hw id for driver to config + * @value : hw value, reference table to get data type + * Author : KaiYuan Chang / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_tx_page_threshold_info *th_info = NULL; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!value) { + PLTFM_MSG_ERR("[ERR]null ptr-set hw value\n"); + return HALMAC_RET_NULL_POINTER; + } + + switch (hw_id) { +#if HALMAC_USB_SUPPORT + case HALMAC_HW_USB_MODE: + status = set_usb_mode_88xx(adapter, + *(enum halmac_usb_mode *)value); + if (status != HALMAC_RET_SUCCESS) + return status; + break; +#endif + case HALMAC_HW_BANDWIDTH: + cfg_bw_88xx(adapter, *(enum halmac_bw *)value); + break; + case HALMAC_HW_CHANNEL: + cfg_ch_88xx(adapter, *(u8 *)value); + break; + case HALMAC_HW_PRI_CHANNEL_IDX: + cfg_pri_ch_idx_88xx(adapter, *(enum halmac_pri_ch_idx *)value); + break; + case HALMAC_HW_EN_BB_RF: + enable_bb_rf_88xx(adapter, *(u8 *)value); + break; +#if HALMAC_SDIO_SUPPORT + case HALMAC_HW_SDIO_TX_PAGE_THRESHOLD: + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + th_info = (struct halmac_tx_page_threshold_info *)value; + cfg_sdio_tx_page_threshold_88xx(adapter, th_info); + } else { + return HALMAC_RET_FAIL; + } + break; +#endif + case HALMAC_HW_RX_SHIFT: + rx_shift_88xx(adapter, *(u8 *)value); + break; + case HALMAC_HW_TXDESC_CHECKSUM: + tx_desc_chksum_88xx(adapter, *(u8 *)value); + break; + case HALMAC_HW_RX_CLK_GATE: + rx_clk_gate_88xx(adapter, *(u8 *)value); + break; + case HALMAC_HW_FAST_EDCA: + fast_edca_cfg_88xx(adapter, + (struct halmac_fast_edca_cfg *)value); + break; + case HALMAC_HW_RTS_FULL_BW: + rts_full_bw_88xx(adapter, *(u8 *)value); + break; + case HALMAC_HW_FREE_CNT_EN: + HALMAC_REG_W8_SET(REG_MISC_CTRL, BIT_EN_FREECNT); + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr, + struct halmac_h2c_header_info *info, u16 *seq_num) +{ + u16 total_size; + + PLTFM_MSG_TRACE("[TRACE]%s!!\n", __func__); + + total_size = H2C_PKT_HDR_SIZE_88XX + info->content_size; + FW_OFFLOAD_H2C_SET_TOTAL_LEN(hdr, total_size); + FW_OFFLOAD_H2C_SET_SUB_CMD_ID(hdr, info->sub_cmd_id); + + FW_OFFLOAD_H2C_SET_CATEGORY(hdr, 0x01); + FW_OFFLOAD_H2C_SET_CMD_ID(hdr, 0xFF); + + PLTFM_MUTEX_LOCK(&adapter->h2c_seq_mutex); + FW_OFFLOAD_H2C_SET_SEQ_NUM(hdr, adapter->h2c_info.seq_num); + *seq_num = adapter->h2c_info.seq_num; + (adapter->h2c_info.seq_num)++; + PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex); + + if (info->ack == 1) + FW_OFFLOAD_H2C_SET_ACK(hdr, 1); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +send_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt) +{ + u32 cnt = 100; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + while (adapter->h2c_info.buf_fs <= H2C_PKT_SIZE_88XX) { + get_h2c_buf_free_space_88xx(adapter); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]h2c free space!!\n"); + return HALMAC_RET_H2C_SPACE_FULL; + } + } + + cnt = 100; + do { + if (PLTFM_SEND_H2C_PKT(pkt, H2C_PKT_SIZE_88XX) == 1) + break; + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]pltfm - sned h2c pkt!!\n"); + return HALMAC_RET_SEND_H2C_FAIL; + } + PLTFM_DELAY_US(5); + + } while (1); + + adapter->h2c_info.buf_fs -= H2C_PKT_SIZE_88XX; + + return status; +} + +enum halmac_ret_status +get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter) +{ + u32 hw_wptr; + u32 fw_rptr; + struct halmac_h2c_info *info = &adapter->h2c_info; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + hw_wptr = HALMAC_REG_R32(REG_H2C_PKT_WRITEADDR) & 0x3FFFF; + fw_rptr = HALMAC_REG_R32(REG_H2C_PKT_READADDR) & 0x3FFFF; + + if (hw_wptr >= fw_rptr) + info->buf_fs = info->buf_size - (hw_wptr - fw_rptr); + else + info->buf_fs = fw_rptr - hw_wptr; + + return HALMAC_RET_SUCCESS; +} + +/** + * get_c2h_info_88xx() - process halmac C2H packet + * @adapter : the adapter of halmac + * @buf : RX Packet pointer + * @size : RX Packet size + * + * Note : Don't use any IO or DELAY in this API + * + * Author : KaiYuan Chang/Ivan Lin + * + * Used to process c2h packet info from RX path. After receiving the packet, + * user need to call this api and pass the packet pointer. + * + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (GET_RX_DESC_C2H(buf) == 1) { + PLTFM_MSG_TRACE("[TRACE]Parse c2h pkt\n"); + + status = parse_c2h_pkt_88xx(adapter, buf, size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]Parse c2h pkt\n"); + return status; + } + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 cmd_id; + u8 sub_cmd_id; + u8 *c2h_pkt = buf + adapter->hw_cfg_info.rxdesc_size; + u32 c2h_size = size - adapter->hw_cfg_info.rxdesc_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + cmd_id = (u8)C2H_HDR_GET_CMD_ID(c2h_pkt); + + if (cmd_id != 0xFF) { + PLTFM_MSG_TRACE("[TRACE]Not 0xFF cmd!!\n"); + return HALMAC_RET_C2H_NOT_HANDLED; + } + + sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt); + + switch (sub_cmd_id) { + case C2H_SUB_CMD_ID_C2H_DBG: + status = get_c2h_dbg_88xx(adapter, c2h_pkt, c2h_size); + break; + case C2H_SUB_CMD_ID_H2C_ACK_HDR: + status = get_h2c_ack_88xx(adapter, c2h_pkt, c2h_size); + break; + case C2H_SUB_CMD_ID_BT_COEX_INFO: + status = HALMAC_RET_C2H_NOT_HANDLED; + break; + case C2H_SUB_CMD_ID_SCAN_STATUS_RPT: + status = get_scan_rpt_88xx(adapter, c2h_pkt, c2h_size); + break; + case C2H_SUB_CMD_ID_PSD_DATA: + status = get_psd_data_88xx(adapter, c2h_pkt, c2h_size); + break; + case C2H_SUB_CMD_ID_EFUSE_DATA: + status = get_efuse_data_88xx(adapter, c2h_pkt, c2h_size); + break; + default: + PLTFM_MSG_WARN("[WARN]Sub cmd id!!\n"); + status = HALMAC_RET_C2H_NOT_HANDLED; + break; + } + + return status; +} + +static enum halmac_ret_status +get_c2h_dbg_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 i; + u8 next_msg = 0; + u8 cur_msg = 0; + u8 msg_len = 0; + char *c2h_buf = (char *)NULL; + u8 content_len = 0; + u8 seq_num = 0; + + content_len = (u8)C2H_HDR_GET_LEN((u8 *)buf); + + if (content_len > C2H_DBG_CONTENT_MAX_LENGTH) { + PLTFM_MSG_ERR("[ERR]c2h size > max len!\n"); + return HALMAC_RET_C2H_NOT_HANDLED; + } + + for (i = 0; i < content_len; i++) { + if (*(buf + C2H_DBG_HDR_LEN + i) == '\n') { + if ((*(buf + C2H_DBG_HDR_LEN + i + 1) == '\0') || + (*(buf + C2H_DBG_HDR_LEN + i + 1) == 0xff)) { + next_msg = C2H_DBG_HDR_LEN + i + 1; + goto _ENDFOUND; + } + } + } + +_ENDFOUND: + msg_len = next_msg - C2H_DBG_HDR_LEN; + + c2h_buf = (char *)PLTFM_MALLOC(msg_len); + if (!c2h_buf) + return HALMAC_RET_MALLOC_FAIL; + + PLTFM_MEMCPY(c2h_buf, buf + C2H_DBG_HDR_LEN, msg_len); + + seq_num = (u8)(*(c2h_buf)); + *(c2h_buf + msg_len - 1) = '\0'; + PLTFM_MSG_ALWAYS("[RTKFW, SEQ=%d]: %s\n", + seq_num, (char *)(c2h_buf + 1)); + PLTFM_FREE(c2h_buf, msg_len); + + while (*(buf + next_msg) != '\0') { + cur_msg = next_msg; + + msg_len = (u8)(*(buf + cur_msg + 3)) - 1; + next_msg += C2H_DBG_HDR_LEN + msg_len; + + c2h_buf = (char *)PLTFM_MALLOC(msg_len); + if (!c2h_buf) + return HALMAC_RET_MALLOC_FAIL; + + PLTFM_MEMCPY(c2h_buf, buf + cur_msg + C2H_DBG_HDR_LEN, msg_len); + *(c2h_buf + msg_len - 1) = '\0'; + seq_num = (u8)(*(c2h_buf)); + PLTFM_MSG_ALWAYS("[RTKFW, SEQ=%d]: %s\n", + seq_num, (char *)(c2h_buf + 1)); + PLTFM_FREE(c2h_buf, msg_len); + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 cmd_id; + u8 sub_cmd_id; + u8 fw_rc; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]Ack for C2H!!\n"); + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + if (HALMAC_H2C_RETURN_SUCCESS != (enum halmac_h2c_return_code)fw_rc) + PLTFM_MSG_TRACE("[TRACE]fw rc = %d\n", fw_rc); + + cmd_id = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(buf); + + if (cmd_id != 0xFF) { + PLTFM_MSG_ERR("[ERR]h2c ack cmd id!!\n"); + return HALMAC_RET_C2H_NOT_HANDLED; + } + + sub_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(buf); + + switch (sub_cmd_id) { + case H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK: + status = get_h2c_ack_phy_efuse_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_CFG_PARAM_ACK: + status = get_h2c_ack_cfg_param_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_UPDATE_PKT_ACK: + status = get_h2c_ack_update_pkt_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK: + status = get_h2c_ack_update_datapkt_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_RUN_DATAPACK_ACK: + status = get_h2c_ack_run_datapkt_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_CH_SWITCH_ACK: + status = get_h2c_ack_ch_switch_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_IQK_ACK: + status = get_h2c_ack_iqk_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_PWR_TRK_ACK: + status = get_h2c_ack_pwr_trk_88xx(adapter, buf, size); + break; + case H2C_SUB_CMD_ID_PSD_ACK: + break; + case H2C_SUB_CMD_ID_FW_SNDING_ACK: + status = get_h2c_ack_fw_snding_88xx(adapter, buf, size); + break; + default: + status = HALMAC_RET_C2H_NOT_HANDLED; + break; + } + + return status; +} + +static enum halmac_ret_status +get_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 fw_rc; + enum halmac_cmd_process_status proc_status; + + fw_rc = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(buf); + proc_status = (HALMAC_H2C_RETURN_SUCCESS == + (enum halmac_h2c_return_code)fw_rc) ? + HALMAC_CMD_PROCESS_DONE : HALMAC_CMD_PROCESS_ERROR; + + PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status, NULL, 0); + + adapter->halmac_state.scan_state.proc_status = proc_status; + + PLTFM_MSG_TRACE("[TRACE]scan : %X\n", proc_status); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_h2c_ack_cfg_param_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num; + u8 fw_rc; + u32 offset_accum; + u32 value_accum; + struct halmac_cfg_param_state *state = + &adapter->halmac_state.cfg_param_state; + enum halmac_cmd_process_status proc_status = + HALMAC_CMD_PROCESS_UNDEFINE; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + offset_accum = CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(buf); + value_accum = CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(buf); + + if (offset_accum != adapter->cfg_param_info.offset_accum || + value_accum != adapter->cfg_param_info.value_accum) { + PLTFM_MSG_ERR("[ERR][C2H]offset_accu : %x, value_accu : %xn", + offset_accum, value_accum); + PLTFM_MSG_ERR("[ERR][Ada]offset_accu : %x, value_accu : %x\n", + adapter->cfg_param_info.offset_accum, + adapter->cfg_param_info.value_accum); + proc_status = HALMAC_CMD_PROCESS_ERROR; + } + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS && + proc_status != HALMAC_CMD_PROCESS_ERROR) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, proc_status, NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, proc_status, + &fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num; + u8 fw_rc; + struct halmac_update_pkt_state *state = + &adapter->halmac_state.update_pkt_state; + enum halmac_cmd_process_status proc_status; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + if (HALMAC_H2C_RETURN_SUCCESS == (enum halmac_h2c_return_code)fw_rc) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_UPDATE_PACKET, proc_status, + NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_UPDATE_PACKET, proc_status, + &state->fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, + u32 size) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +static enum halmac_ret_status +get_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +static enum halmac_ret_status +get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num; + u8 fw_rc; + struct halmac_scan_state *state = &adapter->halmac_state.scan_state; + enum halmac_cmd_process_status proc_status; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) { + proc_status = HALMAC_CMD_PROCESS_RCVD; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status, + NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status, + &fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +/** + * mac_debug_88xx_v1() - read some registers for debug + * @adapter + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +mac_debug_88xx(struct halmac_adapter *adapter) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->intf == HALMAC_INTERFACE_SDIO) + dump_reg_sdio_88xx(adapter); + else + dump_reg_88xx(adapter); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static void +dump_reg_sdio_88xx(struct halmac_adapter *adapter) +{ + u8 tmp8; + u32 i; + + /* Dump CCCR, it needs new platform api */ + + /*Dump SDIO Local Register, use CMD52*/ + for (i = 0x10250000; i < 0x102500ff; i++) { + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-sdio[%x]=%x\n", i, tmp8); + } + + /*Dump MAC Register*/ + for (i = 0x0000; i < 0x17ff; i++) { + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8); + } + + tmp8 = PLTFM_SDIO_CMD52_R(REG_SDIO_CRC_ERR_IDX); + if (tmp8) + PLTFM_MSG_ERR("[ERR]sdio crc=%x\n", tmp8); + + /*Check RX Fifo status*/ + i = REG_RXFF_PTR_V1; + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8); + i = REG_RXFF_WTR_V1; + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8); + i = REG_RXFF_PTR_V1; + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8); + i = REG_RXFF_WTR_V1; + tmp8 = PLTFM_SDIO_CMD52_R(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8); +} + +static void +dump_reg_88xx(struct halmac_adapter *adapter) +{ + u32 tmp32; + u32 i; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + /*Dump MAC Register*/ + for (i = 0x0000; i < 0x17fc; i += 4) { + tmp32 = HALMAC_REG_R32(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32); + } + + /*Check RX Fifo status*/ + i = REG_RXFF_PTR_V1; + tmp32 = HALMAC_REG_R32(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32); + i = REG_RXFF_WTR_V1; + tmp32 = HALMAC_REG_R32(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32); + i = REG_RXFF_PTR_V1; + tmp32 = HALMAC_REG_R32(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32); + i = REG_RXFF_WTR_V1; + tmp32 = HALMAC_REG_R32(i); + PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32); +} + +/** + * cfg_parameter_88xx() - config parameter by FW + * @adapter : the adapter of halmac + * @info : cmd id, content + * @full_fifo : parameter information + * + * If msk_en = 1, the format of array is {reg_info, mask, value}. + * If msk_en =_FAUSE, the format of array is {reg_info, value} + * The format of reg_info is + * reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg + * reg_info[27:24]=rf_path, 0: path_A, 1: path_B + * if rf_reg=0(MAC_BB reg), rf_path is meaningless. + * ref_info[15:0]=offset + * + * Example: msk_en = 0 + * {0x8100000a, 0x00001122} + * =>Set RF register, path_B, offset 0xA to 0x00001122 + * {0x00000824, 0x11224433} + * =>Set MAC_BB register, offset 0x800 to 0x11224433 + * + * Note : full fifo mode only for init flow + * + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_parameter_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *info, u8 full_fifo) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + enum halmac_cmd_construct_state cmd_state; + + proc_status = &adapter->halmac_state.cfg_param_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(para)\n"); + return HALMAC_RET_BUSY_STATE; + } + + cmd_state = cfg_param_cmd_cnstr_state_88xx(adapter); + if (cmd_state != HALMAC_CMD_CNSTR_IDLE && + cmd_state != HALMAC_CMD_CNSTR_CNSTR) { + PLTFM_MSG_TRACE("[TRACE]Not idle(para)\n"); + return HALMAC_RET_BUSY_STATE; + } + + *proc_status = HALMAC_CMD_PROCESS_IDLE; + + status = proc_cfg_param_88xx(adapter, info, full_fifo); + + if (status != HALMAC_RET_SUCCESS && status != HALMAC_RET_PARA_SENDING) { + PLTFM_MSG_ERR("[ERR]send param h2c\n"); + return status; + } + + return status; +} + +static enum halmac_cmd_construct_state +cfg_param_cmd_cnstr_state_88xx(struct halmac_adapter *adapter) +{ + return adapter->halmac_state.cfg_param_state.cmd_cnstr_state; +} + +static enum halmac_ret_status +proc_cfg_param_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *param, u8 full_fifo) +{ + u8 end_cmd = 0; + u32 rsvd_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_cfg_param_info *info = &adapter->cfg_param_info; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.cfg_param_state.proc_status; + + status = malloc_cfg_param_buf_88xx(adapter, full_fifo); + if (status != HALMAC_RET_SUCCESS) + return status; + + if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) != + HALMAC_RET_SUCCESS) { + PLTFM_FREE(info->buf, info->buf_size); + info->buf = NULL; + info->buf_wptr = NULL; + return HALMAC_RET_ERROR_STATE; + } + + add_param_buf_88xx(adapter, param, info->buf_wptr, &end_cmd); + if (param->cmd_id != HALMAC_PARAMETER_CMD_END) { + info->num++; + info->buf_wptr += CFG_PARAM_H2C_INFO_SIZE; + info->avl_buf_size -= CFG_PARAM_H2C_INFO_SIZE; + } + + rsvd_size = info->avl_buf_size - adapter->hw_cfg_info.txdesc_size; + if (rsvd_size > CFG_PARAM_H2C_INFO_SIZE && end_cmd == 0) + return HALMAC_RET_SUCCESS; + + if (info->num == 0) { + PLTFM_FREE(info->buf, info->buf_size); + info->buf = NULL; + info->buf_wptr = NULL; + PLTFM_MSG_TRACE("[TRACE]param num = 0!!\n"); + + *proc_status = HALMAC_CMD_PROCESS_DONE; + PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, *proc_status, NULL, 0); + + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CFG_PARA); + + return HALMAC_RET_SUCCESS; + } + + status = send_cfg_param_h2c_88xx(adapter); + if (status != HALMAC_RET_SUCCESS) { + if (info->buf) { + PLTFM_FREE(info->buf, info->buf_size); + info->buf = NULL; + info->buf_wptr = NULL; + } + return status; + } + + if (end_cmd == 0) { + PLTFM_MSG_TRACE("[TRACE]send h2c-buf full\n"); + return HALMAC_RET_PARA_SENDING; + } + + return status; +} + +static enum halmac_ret_status +send_cfg_param_h2c_88xx(struct halmac_adapter *adapter) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 pg_addr; + u16 seq_num = 0; + u32 info_size; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_cfg_param_info *info = &adapter->cfg_param_info; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.cfg_param_state.proc_status; + + if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + if (info->full_fifo_mode == 1) + pg_addr = 0; + else + pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + + info_size = info->num * CFG_PARAM_H2C_INFO_SIZE; + + status = dl_rsvd_page_88xx(adapter, pg_addr, info->buf, info_size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n"); + goto CFG_PARAM_H2C_FAIL; + } + + gen_cfg_param_h2c_88xx(adapter, h2c_buf); + + hdr_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAM; + hdr_info.content_size = 4; + hdr_info.ack = 1; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + adapter->halmac_state.cfg_param_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CFG_PARA); + } + +CFG_PARAM_H2C_FAIL: + PLTFM_FREE(info->buf, info->buf_size); + info->buf = NULL; + info->buf_wptr = NULL; + + if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + return status; +} + +static enum halmac_ret_status +cnv_cfg_param_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state) +{ + enum halmac_cmd_construct_state *state; + + state = &adapter->halmac_state.cfg_param_state.cmd_cnstr_state; + + if ((*state != HALMAC_CMD_CNSTR_IDLE) && + (*state != HALMAC_CMD_CNSTR_CNSTR) && + (*state != HALMAC_CMD_CNSTR_H2C_SENT)) + return HALMAC_RET_ERROR_STATE; + + if (dest_state == HALMAC_CMD_CNSTR_IDLE) { + if (*state == HALMAC_CMD_CNSTR_CNSTR) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_CNSTR) { + if (*state == HALMAC_CMD_CNSTR_H2C_SENT) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) { + if ((*state == HALMAC_CMD_CNSTR_IDLE) || + (*state == HALMAC_CMD_CNSTR_H2C_SENT)) + return HALMAC_RET_ERROR_STATE; + } + + *state = dest_state; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +add_param_buf_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *param, u8 *buf, + u8 *end_cmd) +{ + struct halmac_cfg_param_info *info = &adapter->cfg_param_info; + union halmac_parameter_content *content = ¶m->content; + + *end_cmd = 0; + + PARAM_INFO_SET_LEN(buf, CFG_PARAM_H2C_INFO_SIZE); + PARAM_INFO_SET_IO_CMD(buf, param->cmd_id); + + switch (param->cmd_id) { + case HALMAC_PARAMETER_CMD_BB_W8: + case HALMAC_PARAMETER_CMD_BB_W16: + case HALMAC_PARAMETER_CMD_BB_W32: + case HALMAC_PARAMETER_CMD_MAC_W8: + case HALMAC_PARAMETER_CMD_MAC_W16: + case HALMAC_PARAMETER_CMD_MAC_W32: + PARAM_INFO_SET_IO_ADDR(buf, content->MAC_REG_W.offset); + PARAM_INFO_SET_DATA(buf, content->MAC_REG_W.value); + PARAM_INFO_SET_MASK(buf, content->MAC_REG_W.msk); + PARAM_INFO_SET_MSK_EN(buf, content->MAC_REG_W.msk_en); + info->value_accum += content->MAC_REG_W.value; + info->offset_accum += content->MAC_REG_W.offset; + break; + case HALMAC_PARAMETER_CMD_RF_W: + /*In rf register, the address is only 1 byte*/ + PARAM_INFO_SET_RF_ADDR(buf, content->RF_REG_W.offset); + PARAM_INFO_SET_RF_PATH(buf, content->RF_REG_W.rf_path); + PARAM_INFO_SET_DATA(buf, content->RF_REG_W.value); + PARAM_INFO_SET_MASK(buf, content->RF_REG_W.msk); + PARAM_INFO_SET_MSK_EN(buf, content->RF_REG_W.msk_en); + info->value_accum += content->RF_REG_W.value; + info->offset_accum += (content->RF_REG_W.offset + + (content->RF_REG_W.rf_path << 8)); + break; + case HALMAC_PARAMETER_CMD_DELAY_US: + case HALMAC_PARAMETER_CMD_DELAY_MS: + PARAM_INFO_SET_DELAY_VAL(buf, content->DELAY_TIME.delay_time); + break; + case HALMAC_PARAMETER_CMD_END: + *end_cmd = 1; + break; + default: + PLTFM_MSG_ERR("[ERR]cmd id!!\n"); + break; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +gen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff) +{ + struct halmac_cfg_param_info *info = &adapter->cfg_param_info; + u16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + u16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary; + + CFG_PARAM_SET_NUM(buff, info->num); + + if (info->full_fifo_mode == 1) { + CFG_PARAM_SET_INIT_CASE(buff, 0x1); + CFG_PARAM_SET_LOC(buff, 0); + } else { + CFG_PARAM_SET_INIT_CASE(buff, 0x0); + CFG_PARAM_SET_LOC(buff, h2c_info_addr - rsvd_pg_addr); + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +malloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo) +{ + struct halmac_cfg_param_info *info = &adapter->cfg_param_info; + struct halmac_pltfm_cfg_info *pltfm_info = &adapter->pltfm_info; + + if (info->buf) + return HALMAC_RET_SUCCESS; + + if (full_fifo == 1) + info->buf_size = pltfm_info->malloc_size; + else + info->buf_size = CFG_PARAM_RSVDPG_SIZE; + + if (info->buf_size > pltfm_info->rsvd_pg_size) + info->buf_size = pltfm_info->rsvd_pg_size; + + info->buf = smart_malloc_88xx(adapter, info->buf_size, &info->buf_size); + if (info->buf) { + PLTFM_MEMSET(info->buf, 0x00, info->buf_size); + info->full_fifo_mode = full_fifo; + info->buf_wptr = info->buf; + info->num = 0; + info->avl_buf_size = info->buf_size; + info->value_accum = 0; + info->offset_accum = 0; + } else { + return HALMAC_RET_MALLOC_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * update_packet_88xx() - send specific packet to FW + * @adapter : the adapter of halmac + * @pkt_id : packet id, to know the purpose of this packet + * @pkt : packet + * @size : packet size + * + * Note : TX_DESC is not included in the pkt + * + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id, + u8 *pkt, u32 size) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status = + &adapter->halmac_state.update_pkt_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + if (size > UPDATE_PKT_RSVDPG_SIZE) + return HALMAC_RET_RSVD_PG_OVERFLOW_FAIL; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(upd)\n"); + return HALMAC_RET_BUSY_STATE; + } + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + status = send_h2c_update_packet_88xx(adapter, pkt_id, pkt, size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + PLTFM_MSG_ERR("[ERR]pkt id : %X!!\n", pkt_id); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +send_h2c_update_packet_88xx(struct halmac_adapter *adapter, + enum halmac_packet_id pkt_id, u8 *pkt, u32 size) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + u16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + u16 pg_offset; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + status = dl_rsvd_page_88xx(adapter, pg_addr, pkt, size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n"); + return status; + } + + pg_offset = pg_addr - adapter->txff_alloc.rsvd_boundary; + UPDATE_PKT_SET_SIZE(h2c_buf, size + adapter->hw_cfg_info.txdesc_size); + UPDATE_PKT_SET_ID(h2c_buf, pkt_id); + UPDATE_PKT_SET_LOC(h2c_buf, pg_offset); + + hdr_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PKT; + hdr_info.content_size = 8; + hdr_info.ack = 1; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + adapter->halmac_state.update_pkt_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_UPDATE_PACKET); + return status; + } + + return status; +} + +enum halmac_ret_status +bcn_ie_filter_88xx(struct halmac_adapter *adapter, + struct halmac_bcn_ie_info *info) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +enum halmac_ret_status +update_datapack_88xx(struct halmac_adapter *adapter, + enum halmac_data_type data_type, + struct halmac_phy_parameter_info *info) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +enum halmac_ret_status +run_datapack_88xx(struct halmac_adapter *adapter, + enum halmac_data_type data_type) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +enum halmac_ret_status +send_bt_coex_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, u8 ack) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = send_bt_coex_cmd_88xx(adapter, buf, size, ack); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]bt coex cmd!!\n"); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +send_bt_coex_cmd_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 ack) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + PLTFM_MEMCPY(h2c_buf + 8, buf, size); + + hdr_info.sub_cmd_id = SUB_CMD_ID_BT_COEX; + hdr_info.content_size = (u16)size; + hdr_info.ack = ack; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + return status; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * dump_fifo_88xx() - dump fifo data + * @adapter : the adapter of halmac + * @sel : FIFO selection + * @start_addr : start address of selected FIFO + * @size : dump size of selected FIFO + * @data : FIFO data + * + * Note : before dump fifo, user need to call halmac_get_fifo_size to + * get fifo size. Then input this size to halmac_dump_fifo. + * + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +dump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel, + u32 start_addr, u32 size, u8 *data) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + u8 tmp8; + u8 enable; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (sel == HAL_FIFO_SEL_TX && + (start_addr + size) > adapter->hw_cfg_info.tx_fifo_size) { + PLTFM_MSG_ERR("[ERR]size overflow!!\n"); + return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; + } + + if (sel == HAL_FIFO_SEL_RX && + (start_addr + size) > adapter->hw_cfg_info.rx_fifo_size) { + PLTFM_MSG_ERR("[ERR]size overflow!!\n"); + return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; + } + + if ((size & (4 - 1)) != 0) { + PLTFM_MSG_ERR("[ERR]not 4byte alignment!!\n"); + return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; + } + + if (!data) + return HALMAC_RET_NULL_POINTER; + + tmp8 = HALMAC_REG_R8(REG_RCR + 2); + enable = 0; + status = api->halmac_set_hw_value(adapter, HALMAC_HW_RX_CLK_GATE, + &enable); + if (status != HALMAC_RET_SUCCESS) + return status; + status = read_buf_88xx(adapter, start_addr, size, sel, data); + + HALMAC_REG_W8(REG_RCR + 2, tmp8); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read buf!!\n"); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +read_buf_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + enum hal_fifo_sel sel, u8 *data) +{ + u32 start_pg; + u32 value32; + u32 i; + u32 residue; + u32 cnt = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (sel == HAL_FIFO_SEL_RSVD_PAGE) + offset += (adapter->txff_alloc.rsvd_boundary << + TX_PAGE_SIZE_SHIFT_88XX); + + start_pg = offset >> 12; + residue = offset & (4096 - 1); + + if (sel == HAL_FIFO_SEL_TX || sel == HAL_FIFO_SEL_RSVD_PAGE) + start_pg += 0x780; + else if (sel == HAL_FIFO_SEL_RX) + start_pg += 0x700; + else if (sel == HAL_FIFO_SEL_REPORT) + start_pg += 0x660; + else if (sel == HAL_FIFO_SEL_LLT) + start_pg += 0x650; + else if (sel == HAL_FIFO_SEL_RXBUF_FW) + start_pg += 0x680; + else + return HALMAC_RET_NOT_SUPPORT; + + value32 = HALMAC_REG_R16(REG_PKTBUF_DBG_CTRL) & 0xF000; + + do { + HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)(start_pg | value32)); + + for (i = 0x8000 + residue; i <= 0x8FFF; i += 4) { + *(u32 *)(data + cnt) = HALMAC_REG_R32(i); + *(u32 *)(data + cnt) = + rtk_le32_to_cpu(*(u32 *)(data + cnt)); + cnt += 4; + if (size == cnt) + goto HALMAC_BUF_READ_OK; + } + + residue = 0; + start_pg++; + } while (1); + +HALMAC_BUF_READ_OK: + HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)value32); + + return HALMAC_RET_SUCCESS; +} + +/** + * get_fifo_size_88xx() - get fifo size + * @adapter : the adapter of halmac + * @sel : FIFO selection + * Author : Ivan Lin/KaiYuan Chang + * Return : u32 + * More details of status code can be found in prototype document + */ +u32 +get_fifo_size_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel) +{ + u32 size = 0; + + if (sel == HAL_FIFO_SEL_TX) + size = adapter->hw_cfg_info.tx_fifo_size; + else if (sel == HAL_FIFO_SEL_RX) + size = adapter->hw_cfg_info.rx_fifo_size; + else if (sel == HAL_FIFO_SEL_RSVD_PAGE) + size = adapter->hw_cfg_info.tx_fifo_size - + (adapter->txff_alloc.rsvd_boundary << + TX_PAGE_SIZE_SHIFT_88XX); + else if (sel == HAL_FIFO_SEL_REPORT) + size = 65536; + else if (sel == HAL_FIFO_SEL_LLT) + size = 65536; + else if (sel == HAL_FIFO_SEL_RXBUF_FW) + size = RX_BUF_FW_88XX; + + return size; +} + +enum halmac_ret_status +set_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack) +{ + PLTFM_MSG_TRACE("[TRACE]%s!!\n", __func__); + + H2C_CMD_HEADER_SET_CATEGORY(hdr, 0x00); + H2C_CMD_HEADER_SET_TOTAL_LEN(hdr, 16); + + PLTFM_MUTEX_LOCK(&adapter->h2c_seq_mutex); + H2C_CMD_HEADER_SET_SEQ_NUM(hdr, adapter->h2c_info.seq_num); + *seq = adapter->h2c_info.seq_num; + (adapter->h2c_info.seq_num)++; + PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex); + + if (ack == 1) + H2C_CMD_HEADER_SET_ACK(hdr, 1); + + return HALMAC_RET_SUCCESS; +} + +/** + * add_ch_info_88xx() -add channel information + * @adapter : the adapter of halmac + * @info : channel information + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +add_ch_info_88xx(struct halmac_adapter *adapter, struct halmac_ch_info *info) +{ + struct halmac_ch_sw_info *ch_sw_info = &adapter->ch_sw_info; + enum halmac_cmd_construct_state state; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) { + PLTFM_MSG_ERR("[ERR]gen info\n"); + return HALMAC_RET_GEN_INFO_NOT_SENT; + } + + state = scan_cmd_cnstr_state_88xx(adapter); + if (state != HALMAC_CMD_CNSTR_BUF_CLR && + state != HALMAC_CMD_CNSTR_CNSTR) { + PLTFM_MSG_WARN("[WARN]cmd state (scan)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (!ch_sw_info->buf) { + ch_sw_info->buf = (u8 *)PLTFM_MALLOC(SCAN_INFO_RSVDPG_SIZE); + if (!ch_sw_info->buf) + return HALMAC_RET_NULL_POINTER; + ch_sw_info->buf_wptr = ch_sw_info->buf; + ch_sw_info->buf_size = SCAN_INFO_RSVDPG_SIZE; + ch_sw_info->avl_buf_size = SCAN_INFO_RSVDPG_SIZE; + ch_sw_info->total_size = 0; + ch_sw_info->extra_info_en = 0; + ch_sw_info->ch_num = 0; + } + + if (ch_sw_info->extra_info_en == 1) { + PLTFM_MSG_ERR("[ERR]extra info = 1!!\n"); + return HALMAC_RET_CH_SW_SEQ_WRONG; + } + + if (ch_sw_info->avl_buf_size < 4) { + PLTFM_MSG_ERR("[ERR]buf full!!\n"); + return HALMAC_RET_CH_SW_NO_BUF; + } + + if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + CH_INFO_SET_CH(ch_sw_info->buf_wptr, info->channel); + CH_INFO_SET_PRI_CH_IDX(ch_sw_info->buf_wptr, info->pri_ch_idx); + CH_INFO_SET_BW(ch_sw_info->buf_wptr, info->bw); + CH_INFO_SET_TIMEOUT(ch_sw_info->buf_wptr, info->timeout); + CH_INFO_SET_ACTION_ID(ch_sw_info->buf_wptr, info->action_id); + CH_INFO_SET_EXTRA_INFO(ch_sw_info->buf_wptr, info->extra_info); + + ch_sw_info->avl_buf_size = ch_sw_info->avl_buf_size - 4; + ch_sw_info->total_size = ch_sw_info->total_size + 4; + ch_sw_info->ch_num++; + ch_sw_info->extra_info_en = info->extra_info; + ch_sw_info->buf_wptr = ch_sw_info->buf_wptr + 4; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_cmd_construct_state +scan_cmd_cnstr_state_88xx(struct halmac_adapter *adapter) +{ + return adapter->halmac_state.scan_state.cmd_cnstr_state; +} + +static enum halmac_ret_status +cnv_scan_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state) +{ + enum halmac_cmd_construct_state *state; + + state = &adapter->halmac_state.scan_state.cmd_cnstr_state; + + if (dest_state == HALMAC_CMD_CNSTR_IDLE) { + if ((*state == HALMAC_CMD_CNSTR_BUF_CLR) || + (*state == HALMAC_CMD_CNSTR_CNSTR)) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_BUF_CLR) { + if (*state == HALMAC_CMD_CNSTR_H2C_SENT) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_CNSTR) { + if ((*state == HALMAC_CMD_CNSTR_IDLE) || + (*state == HALMAC_CMD_CNSTR_H2C_SENT)) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) { + if ((*state != HALMAC_CMD_CNSTR_CNSTR) && + (*state != HALMAC_CMD_CNSTR_BUF_CLR)) + return HALMAC_RET_ERROR_STATE; + } + + *state = dest_state; + + return HALMAC_RET_SUCCESS; +} + +/** + * add_extra_ch_info_88xx() -add extra channel information + * @adapter : the adapter of halmac + * @info : extra channel information + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +add_extra_ch_info_88xx(struct halmac_adapter *adapter, + struct halmac_ch_extra_info *info) +{ + struct halmac_ch_sw_info *ch_sw_info = &adapter->ch_sw_info; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!ch_sw_info->buf) { + PLTFM_MSG_ERR("[ERR]buf = null!!\n"); + return HALMAC_RET_CH_SW_SEQ_WRONG; + } + + if (ch_sw_info->extra_info_en == 0) { + PLTFM_MSG_ERR("[ERR]extra info = 0!!\n"); + return HALMAC_RET_CH_SW_SEQ_WRONG; + } + + if (ch_sw_info->avl_buf_size < (u32)(info->extra_info_size + 2)) { + PLTFM_MSG_ERR("[ERR]no available buffer!!\n"); + return HALMAC_RET_CH_SW_NO_BUF; + } + + if (scan_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_CNSTR) { + PLTFM_MSG_WARN("[WARN]cmd state (ex scan)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + CH_EXTRA_INFO_SET_ID(ch_sw_info->buf_wptr, info->extra_action_id); + CH_EXTRA_INFO_SET_INFO(ch_sw_info->buf_wptr, info->extra_info); + CH_EXTRA_INFO_SET_SIZE(ch_sw_info->buf_wptr, info->extra_info_size); + PLTFM_MEMCPY(ch_sw_info->buf_wptr + 2, info->extra_info_data, + info->extra_info_size); + + ch_sw_info->avl_buf_size -= (2 + info->extra_info_size); + ch_sw_info->total_size += (2 + info->extra_info_size); + ch_sw_info->extra_info_en = info->extra_info; + ch_sw_info->buf_wptr += (2 + info->extra_info_size); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * ctrl_ch_switch_88xx() -send channel switch cmd + * @adapter : the adapter of halmac + * @opt : channel switch config + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +ctrl_ch_switch_88xx(struct halmac_adapter *adapter, + struct halmac_ch_switch_option *opt) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_construct_state state; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.scan_state.proc_status; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (opt->switch_en == 0) + *proc_status = HALMAC_CMD_PROCESS_IDLE; + + if ((*proc_status == HALMAC_CMD_PROCESS_SENDING) || + (*proc_status == HALMAC_CMD_PROCESS_RCVD)) { + PLTFM_MSG_TRACE("[TRACE]Wait event(scan)\n"); + return HALMAC_RET_BUSY_STATE; + } + + state = scan_cmd_cnstr_state_88xx(adapter); + if (opt->switch_en == 1) { + if (state != HALMAC_CMD_CNSTR_CNSTR) { + PLTFM_MSG_ERR("[ERR]state(en = 1)\n"); + return HALMAC_RET_ERROR_STATE; + } + } else { + if (state != HALMAC_CMD_CNSTR_BUF_CLR) { + PLTFM_MSG_ERR("[ERR]state(en = 0)\n"); + return HALMAC_RET_ERROR_STATE; + } + } + + status = proc_ctrl_ch_switch_88xx(adapter, opt); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]ctrl ch sw!!\n"); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter, + struct halmac_ch_switch_option *opt) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + u16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.scan_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + if (opt->switch_en != 0) { + status = dl_rsvd_page_88xx(adapter, pg_addr, + adapter->ch_sw_info.buf, + adapter->ch_sw_info.total_size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n"); + return status; + } + } + + CH_SWITCH_SET_START(h2c_buf, opt->switch_en); + CH_SWITCH_SET_CH_NUM(h2c_buf, adapter->ch_sw_info.ch_num); + CH_SWITCH_SET_INFO_LOC(h2c_buf, + pg_addr - adapter->txff_alloc.rsvd_boundary); + CH_SWITCH_SET_DEST_CH_EN(h2c_buf, opt->dest_ch_en); + CH_SWITCH_SET_DEST_CH(h2c_buf, opt->dest_ch); + CH_SWITCH_SET_PRI_CH_IDX(h2c_buf, opt->dest_pri_ch_idx); + CH_SWITCH_SET_ABSOLUTE_TIME(h2c_buf, opt->absolute_time_en); + CH_SWITCH_SET_TSF_LOW(h2c_buf, opt->tsf_low); + CH_SWITCH_SET_PERIODIC_OPT(h2c_buf, opt->periodic_option); + CH_SWITCH_SET_NORMAL_CYCLE(h2c_buf, opt->normal_cycle); + CH_SWITCH_SET_NORMAL_PERIOD(h2c_buf, opt->normal_period); + CH_SWITCH_SET_SLOW_PERIOD(h2c_buf, opt->phase_2_period); + CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_buf, opt->normal_period_sel); + CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_buf, opt->phase_2_period_sel); + CH_SWITCH_SET_INFO_SIZE(h2c_buf, adapter->ch_sw_info.total_size); + + hdr_info.sub_cmd_id = SUB_CMD_ID_CH_SWITCH; + hdr_info.content_size = 20; + hdr_info.ack = 1; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + adapter->halmac_state.scan_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CHANNEL_SWITCH); + } + PLTFM_FREE(adapter->ch_sw_info.buf, adapter->ch_sw_info.buf_size); + adapter->ch_sw_info.buf = NULL; + adapter->ch_sw_info.buf_wptr = NULL; + adapter->ch_sw_info.extra_info_en = 0; + adapter->ch_sw_info.buf_size = 0; + adapter->ch_sw_info.avl_buf_size = 0; + adapter->ch_sw_info.total_size = 0; + adapter->ch_sw_info.ch_num = 0; + + if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + return status; +} + +/** + * clear_ch_info_88xx() -clear channel information + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +clear_ch_info_88xx(struct halmac_adapter *adapter) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (scan_cmd_cnstr_state_88xx(adapter) == HALMAC_CMD_CNSTR_H2C_SENT) { + PLTFM_MSG_WARN("[WARN]state(clear)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_BUF_CLR) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_FREE(adapter->ch_sw_info.buf, adapter->ch_sw_info.buf_size); + adapter->ch_sw_info.buf = NULL; + adapter->ch_sw_info.buf_wptr = NULL; + adapter->ch_sw_info.extra_info_en = 0; + adapter->ch_sw_info.buf_size = 0; + adapter->ch_sw_info.avl_buf_size = 0; + adapter->ch_sw_info.total_size = 0; + adapter->ch_sw_info.ch_num = 0; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * chk_txdesc_88xx() -check if the tx packet format is incorrect + * @adapter : the adapter of halmac + * @buf : tx Packet buffer, tx desc is included + * @size : tx packet size + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u32 mac_clk = 0; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (GET_TX_DESC_BMC(buf) == 1 && GET_TX_DESC_AGG_EN(buf) == 1) + PLTFM_MSG_ERR("[ERR]txdesc - agg + bmc\n"); + + if (size < (GET_TX_DESC_TXPKTSIZE(buf) + + adapter->hw_cfg_info.txdesc_size + + (GET_TX_DESC_PKT_OFFSET(buf) << 3))) { + PLTFM_MSG_ERR("[ERR]txdesc - total size\n"); + status = HALMAC_RET_TXDESC_SET_FAIL; + } + + if (wlhdr_valid_88xx(adapter, buf) != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]wlhdr\n"); + status = HALMAC_RET_WLHDR_FAIL; + } + + if (GET_TX_DESC_AMSDU_PAD_EN(buf) != 0) { + PLTFM_MSG_ERR("[ERR]txdesc - amsdu_pad\n"); + status = HALMAC_RET_TXDESC_SET_FAIL; + } + + switch (BIT_GET_MAC_CLK_SEL(HALMAC_REG_R32(REG_AFE_CTRL1))) { + case 0x0: + mac_clk = 80; + break; + case 0x1: + mac_clk = 40; + break; + case 0x2: + mac_clk = 20; + break; + case 0x3: + mac_clk = 10; + break; + } + + PLTFM_MSG_ALWAYS("MAC clock : 0x%XM\n", mac_clk); + PLTFM_MSG_ALWAYS("mac agg en : 0x%X\n", GET_TX_DESC_AGG_EN(buf)); + PLTFM_MSG_ALWAYS("mac agg num : 0x%X\n", GET_TX_DESC_MAX_AGG_NUM(buf)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +static enum halmac_ret_status +wlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf) +{ + u32 txdesc_size = adapter->hw_cfg_info.txdesc_size + + GET_TX_DESC_PKT_OFFSET(buf); + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct wlhdr_frame_ctrl *wlhdr; + + wlhdr = (struct wlhdr_frame_ctrl *)(buf + txdesc_size); + + if (wlhdr->protocol != WLHDR_PROT_VER) { + PLTFM_MSG_ERR("[ERR]prot ver!!\n"); + return HALMAC_RET_WLHDR_FAIL; + } + + switch (wlhdr->type) { + case WLHDR_TYPE_MGMT: + if (wlhdr_mgmt_valid_88xx(adapter, wlhdr) != 1) + status = HALMAC_RET_WLHDR_FAIL; + break; + case WLHDR_TYPE_CTRL: + if (wlhdr_ctrl_valid_88xx(adapter, wlhdr) != 1) + status = HALMAC_RET_WLHDR_FAIL; + break; + case WLHDR_TYPE_DATA: + if (wlhdr_data_valid_88xx(adapter, wlhdr) != 1) + status = HALMAC_RET_WLHDR_FAIL; + break; + default: + PLTFM_MSG_ERR("[ERR]undefined type!!\n"); + status = HALMAC_RET_WLHDR_FAIL; + break; + } + + return status; +} + +static u8 +wlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr) +{ + u8 state; + + switch (wlhdr->sub_type) { + case WLHDR_SUB_TYPE_ASSOC_REQ: + case WLHDR_SUB_TYPE_ASSOC_RSPNS: + case WLHDR_SUB_TYPE_REASSOC_REQ: + case WLHDR_SUB_TYPE_REASSOC_RSPNS: + case WLHDR_SUB_TYPE_PROBE_REQ: + case WLHDR_SUB_TYPE_PROBE_RSPNS: + case WLHDR_SUB_TYPE_BCN: + case WLHDR_SUB_TYPE_DISASSOC: + case WLHDR_SUB_TYPE_AUTH: + case WLHDR_SUB_TYPE_DEAUTH: + case WLHDR_SUB_TYPE_ACTION: + case WLHDR_SUB_TYPE_ACTION_NOACK: + state = 1; + break; + default: + PLTFM_MSG_ERR("[ERR]mgmt invalid!!\n"); + state = 0; + break; + } + + return state; +} + +static u8 +wlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr) +{ + u8 state; + + switch (wlhdr->sub_type) { + case WLHDR_SUB_TYPE_BF_RPT_POLL: + case WLHDR_SUB_TYPE_NDPA: + state = 1; + break; + default: + PLTFM_MSG_ERR("[ERR]ctrl invalid!!\n"); + state = 0; + break; + } + + return state; +} + +static u8 +wlhdr_data_valid_88xx(struct halmac_adapter *adapter, + struct wlhdr_frame_ctrl *wlhdr) +{ + u8 state; + + switch (wlhdr->sub_type) { + case WLHDR_SUB_TYPE_DATA: + case WLHDR_SUB_TYPE_NULL: + case WLHDR_SUB_TYPE_QOS_DATA: + case WLHDR_SUB_TYPE_QOS_NULL: + state = 1; + break; + default: + PLTFM_MSG_ERR("[ERR]data invalid!!\n"); + state = 0; + break; + } + + return state; +} + +/** + * get_version_88xx() - get HALMAC version + * @ver : return version of major, prototype and minor information + * Author : KaiYuan Chang / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_version_88xx(struct halmac_adapter *adapter, struct halmac_ver *ver) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + ver->major_ver = (u8)HALMAC_MAJOR_VER; + ver->prototype_ver = (u8)HALMAC_PROTOTYPE_VER; + ver->minor_ver = (u8)HALMAC_MINOR_VER; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 6) + return HALMAC_RET_FW_NO_SUPPORT; + + status = proc_p2pps_88xx(adapter, info); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]p2pps!!\n"); + return status; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +proc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + P2PPS_SET_OFFLOAD_EN(h2c_buf, info->offload_en); + P2PPS_SET_ROLE(h2c_buf, info->role); + P2PPS_SET_CTWINDOW_EN(h2c_buf, info->ctwindow_en); + P2PPS_SET_NOA_EN(h2c_buf, info->noa_en); + P2PPS_SET_NOA_SEL(h2c_buf, info->noa_sel); + P2PPS_SET_ALLSTASLEEP(h2c_buf, info->all_sta_sleep); + P2PPS_SET_DISCOVERY(h2c_buf, info->discovery); + P2PPS_SET_DISABLE_CLOSERF(h2c_buf, info->disable_close_rf); + P2PPS_SET_P2P_PORT_ID(h2c_buf, info->p2p_port_id); + P2PPS_SET_P2P_GROUP(h2c_buf, info->p2p_group); + P2PPS_SET_P2P_MACID(h2c_buf, info->p2p_macid); + + P2PPS_SET_CTWINDOW_LENGTH(h2c_buf, info->ctwindow_length); + + P2PPS_SET_NOA_DURATION_PARA(h2c_buf, info->noa_duration_para); + P2PPS_SET_NOA_INTERVAL_PARA(h2c_buf, info->noa_interval_para); + P2PPS_SET_NOA_START_TIME_PARA(h2c_buf, info->noa_start_time_para); + P2PPS_SET_NOA_COUNT_PARA(h2c_buf, info->noa_count_para); + + hdr_info.sub_cmd_id = SUB_CMD_ID_P2PPS; + hdr_info.content_size = 24; + hdr_info.ack = 0; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + + return status; +} + +/** + * query_status_88xx() -query the offload feature status + * @adapter : the adapter of halmac + * @feature_id : feature_id + * @proc_status : feature_status + * @data : data buffer + * @size : data size + * + * Note : + * If user wants to know the data size, user can allocate zero + * size buffer first. If this size less than the data size, halmac + * will return HALMAC_RET_BUFFER_TOO_SMALL. User need to + * re-allocate data buffer with correct data size. + * + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +query_status_88xx(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id, + enum halmac_cmd_process_status *proc_status, u8 *data, + u32 *size) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (!proc_status) + return HALMAC_RET_NULL_POINTER; + + switch (feature_id) { + case HALMAC_FEATURE_CFG_PARA: + status = get_cfg_param_status_88xx(adapter, proc_status); + break; + case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: + status = get_dump_phy_efuse_status_88xx(adapter, proc_status, + data, size); + break; + case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE: + status = get_dump_log_efuse_status_88xx(adapter, proc_status, + data, size); + break; + case HALMAC_FEATURE_CHANNEL_SWITCH: + status = get_ch_switch_status_88xx(adapter, proc_status); + break; + case HALMAC_FEATURE_UPDATE_PACKET: + status = get_update_packet_status_88xx(adapter, proc_status); + break; + case HALMAC_FEATURE_IQK: + status = get_iqk_status_88xx(adapter, proc_status); + break; + case HALMAC_FEATURE_POWER_TRACKING: + status = get_pwr_trk_status_88xx(adapter, proc_status); + break; + case HALMAC_FEATURE_PSD: + status = get_psd_status_88xx(adapter, proc_status, data, size); + break; + case HALMAC_FEATURE_FW_SNDING: + status = get_fw_snding_status_88xx(adapter, proc_status); + break; + default: + return HALMAC_RET_INVALID_FEATURE_ID; + } + + return status; +} + +static enum halmac_ret_status +get_cfg_param_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.cfg_param_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_ch_switch_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.scan_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +get_update_packet_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.update_pkt_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_drv_rsvd_pg_num_88xx() -config reserved page number for driver + * @adapter : the adapter of halmac + * @pg_num : page number + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter, + enum halmac_drv_rsvd_pg_num pg_num) +{ + if (adapter->api_registry.cfg_drv_rsvd_pg_en == 0) + return HALMAC_RET_NOT_SUPPORT; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]pg_num = %d\n", pg_num); + + switch (pg_num) { + case HALMAC_RSVD_PG_NUM8: + adapter->txff_alloc.rsvd_drv_pg_num = 8; + break; + case HALMAC_RSVD_PG_NUM16: + adapter->txff_alloc.rsvd_drv_pg_num = 16; + break; + case HALMAC_RSVD_PG_NUM24: + adapter->txff_alloc.rsvd_drv_pg_num = 24; + break; + case HALMAC_RSVD_PG_NUM32: + adapter->txff_alloc.rsvd_drv_pg_num = 32; + break; + case HALMAC_RSVD_PG_NUM64: + adapter->txff_alloc.rsvd_drv_pg_num = 64; + break; + case HALMAC_RSVD_PG_NUM128: + adapter->txff_alloc.rsvd_drv_pg_num = 128; + break; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * (debug API)h2c_lb_88xx() - send h2c loopback packet + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +h2c_lb_88xx(struct halmac_adapter *adapter) +{ + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +pwr_seq_parser_88xx(struct halmac_adapter *adapter, + struct halmac_wlan_pwr_cfg **cmd_seq) +{ + u8 cut; + u8 intf; + u32 idx = 0; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_wlan_pwr_cfg *cmd; + + switch (adapter->chip_ver) { + case HALMAC_CHIP_VER_A_CUT: + cut = HALMAC_PWR_CUT_A_MSK; + break; + case HALMAC_CHIP_VER_B_CUT: + cut = HALMAC_PWR_CUT_B_MSK; + break; + case HALMAC_CHIP_VER_C_CUT: + cut = HALMAC_PWR_CUT_C_MSK; + break; + case HALMAC_CHIP_VER_D_CUT: + cut = HALMAC_PWR_CUT_D_MSK; + break; + case HALMAC_CHIP_VER_E_CUT: + cut = HALMAC_PWR_CUT_E_MSK; + break; + case HALMAC_CHIP_VER_F_CUT: + cut = HALMAC_PWR_CUT_F_MSK; + break; + case HALMAC_CHIP_VER_TEST: + cut = HALMAC_PWR_CUT_TESTCHIP_MSK; + break; + default: + PLTFM_MSG_ERR("[ERR]cut version!!\n"); + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + switch (adapter->intf) { + case HALMAC_INTERFACE_PCIE: + case HALMAC_INTERFACE_AXI: + intf = HALMAC_PWR_INTF_PCI_MSK; + break; + case HALMAC_INTERFACE_USB: + intf = HALMAC_PWR_INTF_USB_MSK; + break; + case HALMAC_INTERFACE_SDIO: + intf = HALMAC_PWR_INTF_SDIO_MSK; + break; + default: + PLTFM_MSG_ERR("[ERR]interface!!\n"); + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + do { + cmd = cmd_seq[idx]; + + if (!cmd) + break; + + status = pwr_sub_seq_parser_88xx(adapter, cut, intf, cmd); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]pwr sub seq!!\n"); + return status; + } + + idx++; + } while (1); + + return status; +} + +static enum halmac_ret_status +pwr_sub_seq_parser_88xx(struct halmac_adapter *adapter, u8 cut, u8 intf, + struct halmac_wlan_pwr_cfg *cmd) +{ + u8 value; + u32 offset; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + do { + if ((cmd->interface_msk & intf) && (cmd->cut_msk & cut)) { + switch (cmd->cmd) { + case HALMAC_PWR_CMD_WRITE: + offset = cmd->offset; + + if (cmd->base == HALMAC_PWR_ADDR_SDIO) + offset |= SDIO_LOCAL_OFFSET; + + value = HALMAC_REG_R8(offset); + value = (u8)(value & (u8)(~(cmd->msk))); + value = (u8)(value | (cmd->value & cmd->msk)); + + HALMAC_REG_W8(offset, value); + break; + case HALMAC_PWR_CMD_POLLING: + if (pwr_cmd_polling_88xx(adapter, cmd) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_PWRSEQ_POLLING_FAIL; + break; + case HALMAC_PWR_CMD_DELAY: + if (cmd->value == HALMAC_PWR_DELAY_US) + PLTFM_DELAY_US(cmd->offset); + else + PLTFM_DELAY_US(1000 * cmd->offset); + break; + case HALMAC_PWR_CMD_READ: + break; + case HALMAC_PWR_CMD_END: + return HALMAC_RET_SUCCESS; + default: + return HALMAC_RET_PWRSEQ_CMD_INCORRECT; + } + } + cmd++; + } while (1); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +pwr_cmd_polling_88xx(struct halmac_adapter *adapter, + struct halmac_wlan_pwr_cfg *cmd) +{ + u8 value; + u8 flg; + u8 poll_bit; + u32 offset; + u32 cnt; + static u32 stats; + enum halmac_interface intf; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + poll_bit = 0; + cnt = HALMAC_PWR_POLLING_CNT; + flg = 0; + intf = adapter->intf; + + if (cmd->base == HALMAC_PWR_ADDR_SDIO) + offset = cmd->offset | SDIO_LOCAL_OFFSET; + else + offset = cmd->offset; + + do { + cnt--; + value = HALMAC_REG_R8(offset); + value = (u8)(value & cmd->msk); + + if (value == (cmd->value & cmd->msk)) { + poll_bit = 1; + } else { + if (cnt == 0) { + if (intf == HALMAC_INTERFACE_PCIE && flg == 0) { + /* PCIE + USB package */ + /* power bit polling timeout issue */ + stats++; + PLTFM_MSG_WARN("[WARN]PCIE stats:%d\n", + stats); + value = HALMAC_REG_R8(REG_SYS_PW_CTRL); + value |= BIT(3); + HALMAC_REG_W8(REG_SYS_PW_CTRL, value); + value &= ~BIT(3); + HALMAC_REG_W8(REG_SYS_PW_CTRL, value); + poll_bit = 0; + cnt = HALMAC_PWR_POLLING_CNT; + flg = 1; + } else { + PLTFM_MSG_ERR("[ERR]polling to!!\n"); + PLTFM_MSG_ERR("[ERR]cmd offset:%X\n", + cmd->offset); + PLTFM_MSG_ERR("[ERR]cmd value:%X\n", + cmd->value); + PLTFM_MSG_ERR("[ERR]cmd msk:%X\n", + cmd->msk); + PLTFM_MSG_ERR("[ERR]offset = %X\n", + offset); + PLTFM_MSG_ERR("[ERR]value = %X\n", + value); + return HALMAC_RET_PWRSEQ_POLLING_FAIL; + } + } else { + PLTFM_DELAY_US(50); + } + } + } while (!poll_bit); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +parse_intf_phy_88xx(struct halmac_adapter *adapter, + struct halmac_intf_phy_para *param, + enum halmac_intf_phy_platform pltfm, + enum hal_intf_phy intf_phy) +{ + u16 value; + u16 cur_cut; + u16 offset; + u16 ip_sel; + struct halmac_intf_phy_para *cur_param; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 result = HALMAC_RET_SUCCESS; + + switch (adapter->chip_ver) { + case HALMAC_CHIP_VER_A_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_A; + break; + case HALMAC_CHIP_VER_B_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_B; + break; + case HALMAC_CHIP_VER_C_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_C; + break; + case HALMAC_CHIP_VER_D_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_D; + break; + case HALMAC_CHIP_VER_E_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_E; + break; + case HALMAC_CHIP_VER_F_CUT: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_F; + break; + case HALMAC_CHIP_VER_TEST: + cur_cut = (u16)HALMAC_INTF_PHY_CUT_TESTCHIP; + break; + default: + return HALMAC_RET_FAIL; + } + + cur_param = param; + + do { + if ((cur_param->cut & cur_cut) && + (cur_param->plaform & (u16)pltfm)) { + offset = cur_param->offset; + value = cur_param->value; + ip_sel = cur_param->ip_sel; + + if (offset == 0xFFFF) + break; + + if (ip_sel == HALMAC_IP_SEL_MAC) { + HALMAC_REG_W8((u32)offset, (u8)value); + } else if (intf_phy == HAL_INTF_PHY_USB2 || + intf_phy == HAL_INTF_PHY_USB3) { +#if HALMAC_USB_SUPPORT + result = usbphy_write_88xx(adapter, (u8)offset, + value, intf_phy); + if (result != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]usb phy!!\n"); +#endif + } else if (intf_phy == HAL_INTF_PHY_PCIE_GEN1 || + intf_phy == HAL_INTF_PHY_PCIE_GEN2) { +#if HALMAC_PCIE_SUPPORT + if (ip_sel == HALMAC_IP_INTF_PHY) + result = mdio_write_88xx(adapter, + (u8)offset, + value, + intf_phy); + else + result = dbi_w8_88xx(adapter, offset, + (u8)value); + if (result != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]mdio/dbi!!\n"); +#endif + } else { + PLTFM_MSG_ERR("[ERR]intf phy sel!!\n"); + } + } + cur_param++; + } while (1); + + return HALMAC_RET_SUCCESS; +} + +/** + * txfifo_is_empty_88xx() -check if txfifo is empty + * @adapter : the adapter of halmac + * @chk_num : check number + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +txfifo_is_empty_88xx(struct halmac_adapter *adapter, u32 chk_num) +{ + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + cnt = (chk_num <= 10) ? 10 : chk_num; + do { + if (HALMAC_REG_R8(REG_TXPKT_EMPTY) != 0xFF) + return HALMAC_RET_TXFIFO_NO_EMPTY; + + if ((HALMAC_REG_R8(REG_TXPKT_EMPTY + 1) & 0x06) != 0x06) + return HALMAC_RET_TXFIFO_NO_EMPTY; + cnt--; + + } while (cnt != 0); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * (internal use) + * smart_malloc_88xx() - adapt malloc size + * @adapter : the adapter of halmac + * @size : expected malloc size + * @pNew_size : real malloc size + * Author : Ivan Lin + * Return : address pointer + */ +u8* +smart_malloc_88xx(struct halmac_adapter *adapter, u32 size, u32 *new_size) +{ + u8 retry_num; + u8 *malloc_buf = NULL; + + for (retry_num = 0; retry_num < 5; retry_num++) { + malloc_buf = (u8 *)PLTFM_MALLOC(size); + + if (malloc_buf) { + *new_size = size; + return malloc_buf; + } + + size = size >> 1; + + if (size == 0) + break; + } + + PLTFM_MSG_ERR("[ERR]adptive malloc!!\n"); + + return NULL; +} + +/** + * (internal use) + * ltecoex_reg_read_88xx() - read ltecoex register + * @adapter : the adapter of halmac + * @offset : offset + * @pValue : value + * Author : Ivan Lin + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +ltecoex_reg_read_88xx(struct halmac_adapter *adapter, u16 offset, u32 *value) +{ + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + cnt = 10000; + while ((HALMAC_REG_R8(LTECOEX_ACCESS_CTRL + 3) & BIT(5)) == 0) { + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]lte ready(R)\n"); + return HALMAC_RET_LTECOEX_READY_FAIL; + } + cnt--; + PLTFM_DELAY_US(50); + } + + HALMAC_REG_W32(LTECOEX_ACCESS_CTRL, 0x800F0000 | offset); + *value = HALMAC_REG_R32(REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1); + + return HALMAC_RET_SUCCESS; +} + +/** + * (internal use) + * ltecoex_reg_write_88xx() - write ltecoex register + * @adapter : the adapter of halmac + * @offset : offset + * @value : value + * Author : Ivan Lin + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +ltecoex_reg_write_88xx(struct halmac_adapter *adapter, u16 offset, u32 value) +{ + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + cnt = 10000; + while ((HALMAC_REG_R8(LTECOEX_ACCESS_CTRL + 3) & BIT(5)) == 0) { + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]lte ready(W)\n"); + return HALMAC_RET_LTECOEX_READY_FAIL; + } + cnt--; + PLTFM_DELAY_US(50); + } + + HALMAC_REG_W32(REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1, value); + HALMAC_REG_W32(LTECOEX_ACCESS_CTRL, 0xC00F0000 | offset); + + return HALMAC_RET_SUCCESS; +} + +static void +pwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if ((HALMAC_REG_R8(REG_SYS_FUNC_EN + 1) & BIT(3)) == 0) + *state = HALMAC_MAC_POWER_OFF; + else + *state = HALMAC_MAC_POWER_ON; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_common_88xx.h b/hal/halmac/halmac_88xx/halmac_common_88xx.h new file mode 100644 index 0000000..8b77a5d --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_common_88xx.h @@ -0,0 +1,155 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_COMMON_88XX_H_ +#define _HALMAC_COMMON_88XX_H_ + +#include "../halmac_api.h" +#include "../halmac_pwr_seq_cmd.h" +#include "../halmac_gpio_cmd.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +ofld_func_cfg_88xx(struct halmac_adapter *adapter, + struct halmac_ofld_func_info *info); + +enum halmac_ret_status +dl_drv_rsvd_page_88xx(struct halmac_adapter *adapter, u8 pg_offset, u8 *buf, + u32 size); + +enum halmac_ret_status +dl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf, + u32 size); + +enum halmac_ret_status +get_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value); + +enum halmac_ret_status +set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id, + void *value); + +enum halmac_ret_status +set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr, + struct halmac_h2c_header_info *info, u16 *seq_num); + +enum halmac_ret_status +send_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt); + +enum halmac_ret_status +get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +mac_debug_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +cfg_parameter_88xx(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *info, u8 full_fifo); + +enum halmac_ret_status +update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id, + u8 *pkt, u32 size); + +enum halmac_ret_status +bcn_ie_filter_88xx(struct halmac_adapter *adapter, + struct halmac_bcn_ie_info *info); + +enum halmac_ret_status +update_datapack_88xx(struct halmac_adapter *adapter, + enum halmac_data_type data_type, + struct halmac_phy_parameter_info *info); + +enum halmac_ret_status +run_datapack_88xx(struct halmac_adapter *adapter, + enum halmac_data_type data_type); + +enum halmac_ret_status +send_bt_coex_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, u8 ack); + +enum halmac_ret_status +dump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel, + u32 start_addr, u32 size, u8 *data); + +u32 +get_fifo_size_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel); + +enum halmac_ret_status +set_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack); + +enum halmac_ret_status +add_ch_info_88xx(struct halmac_adapter *adapter, struct halmac_ch_info *info); + +enum halmac_ret_status +add_extra_ch_info_88xx(struct halmac_adapter *adapter, + struct halmac_ch_extra_info *info); + +enum halmac_ret_status +ctrl_ch_switch_88xx(struct halmac_adapter *adapter, + struct halmac_ch_switch_option *opt); + +enum halmac_ret_status +clear_ch_info_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +get_version_88xx(struct halmac_adapter *adapter, struct halmac_ver *ver); + +enum halmac_ret_status +p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info); + +enum halmac_ret_status +query_status_88xx(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id, + enum halmac_cmd_process_status *proc_status, u8 *data, + u32 *size); + +enum halmac_ret_status +cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter, + enum halmac_drv_rsvd_pg_num pg_num); + +enum halmac_ret_status +h2c_lb_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +pwr_seq_parser_88xx(struct halmac_adapter *adapter, + struct halmac_wlan_pwr_cfg **cmd_seq); + +enum halmac_ret_status +parse_intf_phy_88xx(struct halmac_adapter *adapter, + struct halmac_intf_phy_para *param, + enum halmac_intf_phy_platform pltfm, + enum hal_intf_phy intf_phy); + +enum halmac_ret_status +txfifo_is_empty_88xx(struct halmac_adapter *adapter, u32 chk_num); + +u8* +smart_malloc_88xx(struct halmac_adapter *adapter, u32 size, u32 *new_size); + +enum halmac_ret_status +ltecoex_reg_read_88xx(struct halmac_adapter *adapter, u16 offset, u32 *value); + +enum halmac_ret_status +ltecoex_reg_write_88xx(struct halmac_adapter *adapter, u16 offset, u32 value); + +#endif/* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_COMMON_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_efuse_88xx.c b/hal/halmac/halmac_88xx/halmac_efuse_88xx.c new file mode 100644 index 0000000..49d6daf --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_efuse_88xx.c @@ -0,0 +1,1905 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_efuse_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_common_88xx.h" +#include "halmac_init_88xx.h" + +#if HALMAC_88XX_SUPPORT + +#define RSVD_EFUSE_SIZE 16 +#define RSVD_CS_EFUSE_SIZE 24 +#define PROTECT_EFUSE_SIZE 96 +#define FEATURE_DUMP_PHY_EFUSE HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE +#define FEATURE_DUMP_LOG_EFUSE HALMAC_FEATURE_DUMP_LOGICAL_EFUSE + +static enum halmac_cmd_construct_state +efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +proc_dump_efuse_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg); + +static enum halmac_ret_status +read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *map); + +static enum halmac_ret_status +eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map); + +static enum halmac_ret_status +read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map); + +static enum halmac_ret_status +proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, + enum halmac_efuse_read_cfg cfg); + +static enum halmac_ret_status +dump_efuse_fw_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +dump_efuse_drv_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value); + +static enum halmac_ret_status +update_eeprom_mask_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask); + +static enum halmac_ret_status +check_efuse_enough_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask); + +static enum halmac_ret_status +pg_extend_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 word_en, + u8 pre_word_en, u32 eeprom_offset); + +static enum halmac_ret_status +proc_pg_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 word_en, + u8 pre_word_en, u32 eeprom_offset); + +static enum halmac_ret_status +program_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask); + +static void +mask_eeprom_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info); + +/** + * dump_efuse_map_88xx() - dump "physical" efuse map + * @adapter : the adapter of halmac + * @cfg : dump efuse method + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +dump_efuse_map_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg) +{ + u8 *map = NULL; + u8 *efuse_map; + u32 efuse_size = adapter->hw_cfg_info.efuse_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + if (cfg == HALMAC_EFUSE_R_FW && + halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) + PLTFM_MSG_ERR("[ERR]Dump efuse in suspend\n"); + + *proc_status = HALMAC_CMD_PROCESS_IDLE; + adapter->evnt.phy_efuse_map = 1; + + status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + return status; + } + + status = proc_dump_efuse_88xx(adapter, cfg); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dump efuse!!\n"); + return status; + } + + if (adapter->efuse_map_valid == 1) { + *proc_status = HALMAC_CMD_PROCESS_DONE; + efuse_map = adapter->efuse_map; + + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, efuse_size); + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + PLTFM_MEMCPY(map, efuse_map, efuse_size - PROTECT_EFUSE_SIZE); + PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE + + RSVD_CS_EFUSE_SIZE, + efuse_map + efuse_size - PROTECT_EFUSE_SIZE + + RSVD_CS_EFUSE_SIZE, + PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE - + RSVD_CS_EFUSE_SIZE); + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, + *proc_status, map, efuse_size); + adapter->evnt.phy_efuse_map = 0; + + PLTFM_FREE(map, efuse_size); + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * dump_efuse_map_bt_88xx() - dump "BT physical" efuse map + * @adapter : the adapter of halmac + * @bank : bt efuse bank + * @size : bt efuse map size. get from halmac_get_efuse_size API + * @map : bt efuse map + * Author : Soar / Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +dump_efuse_map_bt_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_bank bank, u32 size, u8 *map) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->hw_cfg_info.bt_efuse_size != size) + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + + if (bank >= HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) { + PLTFM_MSG_ERR("[ERR]Undefined BT bank\n"); + return HALMAC_RET_EFUSE_BANK_INCORRECT; + } + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = switch_efuse_bank_88xx(adapter, bank); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + return status; + } + + status = read_hw_efuse_88xx(adapter, 0, size, map); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read hw efuse\n"); + return status; + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * write_efuse_bt_88xx() - write "BT physical" efuse offset + * @adapter : the adapter of halmac + * @offset : offset + * @value : Write value + * @map : bt efuse map + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +write_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value, + enum halmac_efuse_bank bank) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (offset >= adapter->hw_cfg_info.efuse_size) { + PLTFM_MSG_ERR("[ERR]Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) { + PLTFM_MSG_ERR("[ERR]Undefined BT bank\n"); + return HALMAC_RET_EFUSE_BANK_INCORRECT; + } + + status = switch_efuse_bank_88xx(adapter, bank); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n"); + return status; + } + + status = write_hw_efuse_88xx(adapter, offset, value); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse\n"); + return status; + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * read_efuse_bt_88xx() - read "BT physical" efuse offset + * @adapter : the adapter of halmac + * @offset : offset + * @value : 1 byte efuse value + * @bank : efuse bank + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value, + enum halmac_efuse_bank bank) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (offset >= adapter->hw_cfg_info.efuse_size) { + PLTFM_MSG_ERR("[ERR]Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) { + PLTFM_MSG_ERR("[ERR]Undefined BT bank\n"); + return HALMAC_RET_EFUSE_BANK_INCORRECT; + } + + status = switch_efuse_bank_88xx(adapter, bank); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + return status; + } + + status = read_efuse_88xx(adapter, offset, 1, value); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read efuse\n"); + return status; + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_efuse_auto_check_88xx() - check efuse after writing it + * @adapter : the adapter of halmac + * @enable : 1, enable efuse auto check. others, disable + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + adapter->efuse_auto_check_en = enable; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * get_efuse_available_size_88xx() - get efuse available size + * @adapter : the adapter of halmac + * @size : physical efuse available size + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size) +{ + enum halmac_ret_status status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = dump_log_efuse_map_88xx(adapter, HALMAC_EFUSE_R_DRV); + + if (status != HALMAC_RET_SUCCESS) + return status; + + *size = adapter->hw_cfg_info.efuse_size - PROTECT_EFUSE_SIZE - + adapter->efuse_end; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * get_efuse_size_88xx() - get "physical" efuse size + * @adapter : the adapter of halmac + * @size : physical efuse size + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + *size = adapter->hw_cfg_info.efuse_size; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * get_log_efuse_size_88xx() - get "logical" efuse size + * @adapter : the adapter of halmac + * @size : logical efuse size + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + *size = adapter->hw_cfg_info.eeprom_size; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * dump_log_efuse_map_88xx() - dump "logical" efuse map + * @adapter : the adapter of halmac + * @cfg : dump efuse method + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +dump_log_efuse_map_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg) +{ + u8 *map = NULL; + u32 size = adapter->hw_cfg_info.eeprom_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + if (cfg == HALMAC_EFUSE_R_FW && + halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg); + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) + PLTFM_MSG_ERR("[ERR]Dump efuse in suspend\n"); + + *proc_status = HALMAC_CMD_PROCESS_IDLE; + adapter->evnt.log_efuse_map = 1; + + status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + return status; + } + + status = proc_dump_efuse_88xx(adapter, cfg); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dump efuse\n"); + return status; + } + + if (adapter->efuse_map_valid == 1) { + *proc_status = HALMAC_CMD_PROCESS_DONE; + + map = (u8 *)PLTFM_MALLOC(size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, size); + + if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) != + HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, size); + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + + PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, + *proc_status, map, size); + adapter->evnt.log_efuse_map = 0; + + PLTFM_FREE(map, size); + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * read_logical_efuse_88xx() - read logical efuse map 1 byte + * @adapter : the adapter of halmac + * @offset : offset + * @value : 1 byte efuse value + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value) +{ + u8 *map = NULL; + u32 size = adapter->hw_cfg_info.eeprom_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (offset >= size) { + PLTFM_MSG_ERR("[ERR]Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + return status; + } + + map = (u8 *)PLTFM_MALLOC(size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, size); + + status = read_log_efuse_map_88xx(adapter, map); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read logical efuse\n"); + PLTFM_FREE(map, size); + return status; + } + + *value = *(map + offset); + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, size); + return HALMAC_RET_ERROR_STATE; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + PLTFM_FREE(map, size); + + return HALMAC_RET_SUCCESS; +} + +/** + * write_log_efuse_88xx() - write "logical" efuse offset + * @adapter : the adapter of halmac + * @offset : offset + * @value : value + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (offset >= adapter->hw_cfg_info.eeprom_size) { + PLTFM_MSG_ERR("[ERR]Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + return status; + } + + status = proc_write_log_efuse_88xx(adapter, offset, value); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write logical efuse\n"); + return status; + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * pg_efuse_by_map_88xx() - pg logical efuse by map + * @adapter : the adapter of halmac + * @info : efuse map information + * @cfg : dump efuse method + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pg_efuse_by_map_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, + enum halmac_efuse_read_cfg cfg) +{ + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) { + PLTFM_MSG_ERR("[ERR]map size error\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if ((info->efuse_map_size & 0xF) > 0) { + PLTFM_MSG_ERR("[ERR]not multiple of 16\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (info->efuse_mask_size != info->efuse_map_size >> 4) { + PLTFM_MSG_ERR("[ERR]mask size error\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (!info->efuse_map) { + PLTFM_MSG_ERR("[ERR]map is NULL\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (!info->efuse_mask) { + PLTFM_MSG_ERR("[ERR]mask is NULL\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]switch efuse bank\n"); + return status; + } + + status = proc_pg_efuse_by_map_88xx(adapter, info, cfg); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]pg efuse\n"); + return status; + } + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * mask_log_efuse_88xx() - mask logical efuse + * @adapter : the adapter of halmac + * @info : efuse map information + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mask_log_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) { + PLTFM_MSG_ERR("[ERR]map size error\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if ((info->efuse_map_size & 0xF) > 0) { + PLTFM_MSG_ERR("[ERR]not multiple of 16\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (info->efuse_mask_size != info->efuse_map_size >> 4) { + PLTFM_MSG_ERR("[ERR]mask size error\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (!info->efuse_map) { + PLTFM_MSG_ERR("[ERR]map is NULL\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (!info->efuse_mask) { + PLTFM_MSG_ERR("[ERR]mask is NULL\n"); + return HALMAC_RET_NULL_POINTER; + } + + mask_eeprom_88xx(adapter, info); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_cmd_construct_state +efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter) +{ + return adapter->halmac_state.efuse_state.cmd_cnstr_state; +} + +enum halmac_ret_status +switch_efuse_bank_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_bank bank) +{ + u8 reg_value; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_BUSY) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + reg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1); + + if (bank == (reg_value & (BIT(0) | BIT(1)))) + return HALMAC_RET_SUCCESS; + + reg_value &= ~(BIT(0) | BIT(1)); + reg_value |= bank; + HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 1, reg_value); + + reg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1); + if ((reg_value & (BIT(0) | BIT(1))) != bank) + return HALMAC_RET_SWITCH_EFUSE_BANK_FAIL; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +proc_dump_efuse_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg) +{ + u32 h2c_init; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + enum halmac_cmd_process_status *proc_status; + + proc_status = &adapter->halmac_state.efuse_state.proc_status; + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + if (cfg == HALMAC_EFUSE_R_AUTO) { + h2c_init = HALMAC_REG_R32(REG_H2C_PKT_READADDR); + if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE || + h2c_init == 0) + status = dump_efuse_drv_88xx(adapter); + else + status = dump_efuse_fw_88xx(adapter); + } else if (cfg == HALMAC_EFUSE_R_FW) { + status = dump_efuse_fw_88xx(adapter); + } else { + status = dump_efuse_drv_88xx(adapter); + } + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dump efsue drv/fw\n"); + return status; + } + + return status; +} + +enum halmac_ret_status +cnv_efuse_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state) +{ + struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state; + + if (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE && + state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY && + state->cmd_cnstr_state != HALMAC_CMD_CNSTR_H2C_SENT) + return HALMAC_RET_ERROR_STATE; + + if (state->cmd_cnstr_state == dest_state) + return HALMAC_RET_ERROR_STATE; + + if (dest_state == HALMAC_CMD_CNSTR_BUSY) { + if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_H2C_SENT) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) { + if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE) + return HALMAC_RET_ERROR_STATE; + } + + state->cmd_cnstr_state = dest_state; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *map) +{ + u8 enable; + u32 value32; + u32 addr; + u32 tmp32; + u32 cnt; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + /* Read efuse no need 2.5V LDO */ + enable = 0; + status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dis ldo25\n"); + return status; + } + value32 = HALMAC_REG_R32(REG_EFUSE_CTRL); + + for (addr = offset; addr < offset + size; addr++) { + value32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR); + value32 |= ((addr & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR); + HALMAC_REG_W32(REG_EFUSE_CTRL, value32 & (~BIT_EF_FLAG)); + + cnt = 1000000; + do { + PLTFM_DELAY_US(1); + tmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]read\n"); + return HALMAC_RET_EFUSE_R_FAIL; + } + } while ((tmp32 & BIT_EF_FLAG) == 0); + + *(map + addr - offset) = (u8)(tmp32 & BIT_MASK_EF_DATA); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value) +{ + const u8 unlock_code = 0x69; + u8 value_read = 0; + u8 enable; + u32 value32; + u32 tmp32; + u32 cnt; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + adapter->efuse_map_valid = 0; + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, unlock_code); + + /* Enable 2.5V LDO */ + enable = 1; + status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]en ldo25\n"); + return status; + } + + value32 = HALMAC_REG_R32(REG_EFUSE_CTRL); + value32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR); + value32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) | + (value & BIT_MASK_EF_DATA); + HALMAC_REG_W32(REG_EFUSE_CTRL, value32 | BIT_EF_FLAG); + + cnt = 1000000; + do { + PLTFM_DELAY_US(1); + tmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]write!!\n"); + return HALMAC_RET_EFUSE_W_FAIL; + } + } while (BIT_EF_FLAG == (tmp32 & BIT_EF_FLAG)); + + HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, 0x00); + + /* Disable 2.5V LDO */ + enable = 0; + status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dis ldo25\n"); + return status; + } + + if (adapter->efuse_auto_check_en == 1) { + if (read_hw_efuse_88xx(adapter, offset, 1, &value_read) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_EFUSE_R_FAIL; + if (value_read != value) { + PLTFM_MSG_ERR("[ERR]efuse compare\n"); + return HALMAC_RET_EFUSE_W_FAIL; + } + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map) +{ + u8 i; + u8 value8; + u8 blk_idx; + u8 word_en; + u8 valid; + u8 hdr; + u8 hdr2 = 0; + u32 eeprom_idx; + u32 efuse_idx = 0; + struct halmac_hw_cfg_info *hw_info = &adapter->hw_cfg_info; + + PLTFM_MEMSET(log_map, 0xFF, hw_info->eeprom_size); + + do { + value8 = *(phy_map + efuse_idx); + hdr = value8; + + if ((hdr & 0x1f) == 0x0f) { + efuse_idx++; + value8 = *(phy_map + efuse_idx); + hdr2 = value8; + if (hdr2 == 0xff) + break; + blk_idx = ((hdr2 & 0xF0) >> 1) | ((hdr >> 5) & 0x07); + word_en = hdr2 & 0x0F; + } else { + blk_idx = (hdr & 0xF0) >> 4; + word_en = hdr & 0x0F; + } + + if (hdr == 0xff) + break; + + efuse_idx++; + + if (efuse_idx >= hw_info->efuse_size - PROTECT_EFUSE_SIZE - 1) + return HALMAC_RET_EEPROM_PARSING_FAIL; + + for (i = 0; i < 4; i++) { + valid = (u8)((~(word_en >> i)) & BIT(0)); + if (valid == 1) { + eeprom_idx = (blk_idx << 3) + (i << 1); + + if ((eeprom_idx + 1) > hw_info->eeprom_size) { + PLTFM_MSG_ERR("[ERR]efuse idx:0x%X\n", + efuse_idx - 1); + + PLTFM_MSG_ERR("[ERR]read hdr:0x%X\n", + hdr); + + PLTFM_MSG_ERR("[ERR]rad hdr2:0x%X\n", + hdr2); + + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + + value8 = *(phy_map + efuse_idx); + *(log_map + eeprom_idx) = value8; + + eeprom_idx++; + efuse_idx++; + + if (efuse_idx > hw_info->efuse_size - + PROTECT_EFUSE_SIZE - 1) + return HALMAC_RET_EEPROM_PARSING_FAIL; + + value8 = *(phy_map + efuse_idx); + *(log_map + eeprom_idx) = value8; + + efuse_idx++; + + if (efuse_idx > hw_info->efuse_size - + PROTECT_EFUSE_SIZE) + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + } + } while (1); + + adapter->efuse_end = efuse_idx; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map) +{ + u8 *local_map = NULL; + u32 efuse_size; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (adapter->efuse_map_valid == 0) { + efuse_size = adapter->hw_cfg_info.efuse_size; + + local_map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!local_map) { + PLTFM_MSG_ERR("[ERR]local map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + + status = read_efuse_88xx(adapter, 0, efuse_size, local_map); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read efuse\n"); + PLTFM_FREE(local_map, efuse_size); + return status; + } + + if (!adapter->efuse_map) { + adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!adapter->efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc adapter map\n"); + PLTFM_FREE(local_map, efuse_size); + return HALMAC_RET_MALLOC_FAIL; + } + } + + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + PLTFM_MEMCPY(adapter->efuse_map, local_map, efuse_size); + adapter->efuse_map_valid = 1; + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + PLTFM_FREE(local_map, efuse_size); + } + + if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_EEPROM_PARSING_FAIL; + + return status; +} + +static enum halmac_ret_status +proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, + enum halmac_efuse_read_cfg cfg) +{ + u8 *updated_mask = NULL; + u32 mask_size = adapter->hw_cfg_info.eeprom_size >> 4; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + updated_mask = (u8 *)PLTFM_MALLOC(mask_size); + if (!updated_mask) { + PLTFM_MSG_ERR("[ERR]malloc updated mask\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(updated_mask, 0x00, mask_size); + + status = update_eeprom_mask_88xx(adapter, info, updated_mask); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]update eeprom mask\n"); + PLTFM_FREE(updated_mask, mask_size); + return status; + } + + status = check_efuse_enough_88xx(adapter, info, updated_mask); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]chk efuse enough\n"); + PLTFM_FREE(updated_mask, mask_size); + return status; + } + + status = program_efuse_88xx(adapter, info, updated_mask); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]pg efuse\n"); + PLTFM_FREE(updated_mask, mask_size); + return status; + } + + PLTFM_FREE(updated_mask, mask_size); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +dump_efuse_drv_88xx(struct halmac_adapter *adapter) +{ + u8 *map = NULL; + u32 efuse_size = adapter->hw_cfg_info.efuse_size; + + if (!adapter->efuse_map) { + adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!adapter->efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc adapter map!!\n"); + reset_ofld_feature_88xx(adapter, + FEATURE_DUMP_PHY_EFUSE); + return HALMAC_RET_MALLOC_FAIL; + } + } + + if (adapter->efuse_map_valid == 0) { + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + + if (read_hw_efuse_88xx(adapter, 0, efuse_size, map) != + HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, efuse_size); + return HALMAC_RET_EFUSE_R_FAIL; + } + + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + PLTFM_MEMCPY(adapter->efuse_map, map, efuse_size); + adapter->efuse_map_valid = 1; + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + PLTFM_FREE(map, efuse_size); + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +dump_efuse_fw_88xx(struct halmac_adapter *adapter) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + u32 efuse_size = adapter->hw_cfg_info.efuse_size; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + hdr_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE; + hdr_info.content_size = 0; + hdr_info.ack = 1; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + adapter->halmac_state.efuse_state.seq_num = seq_num; + + if (!adapter->efuse_map) { + adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!adapter->efuse_map) { + PLTFM_MSG_ERR("[ERR]malloc adapter map\n"); + reset_ofld_feature_88xx(adapter, + FEATURE_DUMP_PHY_EFUSE); + return HALMAC_RET_MALLOC_FAIL; + } + } + + if (adapter->efuse_map_valid == 0) { + status = send_h2c_pkt_88xx(adapter, h2c_buf); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c pkt\n"); + reset_ofld_feature_88xx(adapter, + FEATURE_DUMP_PHY_EFUSE); + return status; + } + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value) +{ + u8 byte1; + u8 byte2; + u8 blk; + u8 blk_idx; + u8 hdr; + u8 hdr2; + u8 *map = NULL; + u32 eeprom_size = adapter->hw_cfg_info.eeprom_size; + u32 end; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + map = (u8 *)PLTFM_MALLOC(eeprom_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, eeprom_size); + + status = read_log_efuse_map_88xx(adapter, map); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]read logical efuse\n"); + PLTFM_FREE(map, eeprom_size); + return status; + } + + if (*(map + offset) != value) { + end = adapter->efuse_end; + blk = (u8)(offset >> 3); + blk_idx = (u8)((offset & (8 - 1)) >> 1); + + if (offset > 0x7f) { + hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F; + hdr2 = (u8)(((blk & 0x78) << 1) + + ((0x1 << blk_idx) ^ 0x0F)); + } else { + hdr = (u8)((blk << 4) + ((0x01 << blk_idx) ^ 0x0F)); + } + + if ((offset & 1) == 0) { + byte1 = value; + byte2 = *(map + offset + 1); + } else { + byte1 = *(map + offset - 1); + byte2 = value; + } + + if (offset > 0x7f) { + if (adapter->hw_cfg_info.efuse_size <= + 4 + PROTECT_EFUSE_SIZE + end) { + PLTFM_FREE(map, eeprom_size); + return HALMAC_RET_EFUSE_NOT_ENOUGH; + } + + status = write_hw_efuse_88xx(adapter, end, hdr); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + status = write_hw_efuse_88xx(adapter, end + 1, hdr2); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + status = write_hw_efuse_88xx(adapter, end + 2, byte1); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + status = write_hw_efuse_88xx(adapter, end + 3, byte2); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + } else { + if (adapter->hw_cfg_info.efuse_size <= + 3 + PROTECT_EFUSE_SIZE + end) { + PLTFM_FREE(map, eeprom_size); + return HALMAC_RET_EFUSE_NOT_ENOUGH; + } + + status = write_hw_efuse_88xx(adapter, end, hdr); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + status = write_hw_efuse_88xx(adapter, end + 1, byte1); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + status = write_hw_efuse_88xx(adapter, end + 2, byte2); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + } + } + + PLTFM_FREE(map, eeprom_size); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map) +{ + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (adapter->efuse_map_valid == 1) { + PLTFM_MEMCPY(map, adapter->efuse_map + offset, size); + } else { + if (read_hw_efuse_88xx(adapter, offset, size, map) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_EFUSE_R_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +update_eeprom_mask_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask) +{ + u8 *map = NULL; + u8 clr_bit = 0; + u32 eeprom_size = adapter->hw_cfg_info.eeprom_size; + u8 *map_pg; + u8 *efuse_mask; + u16 i; + u16 j; + u16 map_offset; + u16 mask_offset; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + map = (u8 *)PLTFM_MALLOC(eeprom_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, eeprom_size); + + PLTFM_MEMSET(updated_mask, 0x00, info->efuse_mask_size); + + status = read_log_efuse_map_88xx(adapter, map); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return status; + } + + map_pg = info->efuse_map; + efuse_mask = info->efuse_mask; + + for (i = 0; i < info->efuse_mask_size; i++) + *(updated_mask + i) = *(efuse_mask + i); + + for (i = 0; i < info->efuse_map_size; i += 16) { + for (j = 0; j < 16; j += 2) { + map_offset = i + j; + mask_offset = i >> 4; + if (*(u16 *)(map_pg + map_offset) == + *(u16 *)(map + map_offset)) { + switch (j) { + case 0: + clr_bit = BIT(4); + break; + case 2: + clr_bit = BIT(5); + break; + case 4: + clr_bit = BIT(6); + break; + case 6: + clr_bit = BIT(7); + break; + case 8: + clr_bit = BIT(0); + break; + case 10: + clr_bit = BIT(1); + break; + case 12: + clr_bit = BIT(2); + break; + case 14: + clr_bit = BIT(3); + break; + default: + break; + } + *(updated_mask + mask_offset) &= ~clr_bit; + } + } + } + + PLTFM_FREE(map, eeprom_size); + + return status; +} + +static enum halmac_ret_status +check_efuse_enough_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask) +{ + u8 pre_word_en; + u16 i; + u16 j; + u32 eeprom_offset; + u32 pg_num = 0; + + for (i = 0; i < info->efuse_map_size; i = i + 8) { + eeprom_offset = i; + + if ((eeprom_offset & 7) > 0) + pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F); + else + pre_word_en = (*(updated_mask + (i >> 4)) >> 4); + + if (pre_word_en > 0) { + if (eeprom_offset > 0x7f) { + pg_num += 2; + for (j = 0; j < 4; j++) { + if (((pre_word_en >> j) & 0x1) > 0) + pg_num += 2; + } + } else { + pg_num++; + for (j = 0; j < 4; j++) { + if (((pre_word_en >> j) & 0x1) > 0) + pg_num += 2; + } + } + } + } + + if (adapter->hw_cfg_info.efuse_size <= + (pg_num + PROTECT_EFUSE_SIZE + adapter->efuse_end)) + return HALMAC_RET_EFUSE_NOT_ENOUGH; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +pg_extend_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 word_en, + u8 pre_word_en, u32 eeprom_offset) +{ + u8 blk; + u8 hdr; + u8 hdr2; + u16 i; + u32 efuse_end; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + efuse_end = adapter->efuse_end; + + blk = (u8)(eeprom_offset >> 3); + hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F; + hdr2 = (u8)(((blk & 0x78) << 1) + word_en); + + status = write_hw_efuse_88xx(adapter, efuse_end, hdr); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse\n"); + return status; + } + + status = write_hw_efuse_88xx(adapter, efuse_end + 1, hdr2); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse(+1)\n"); + return status; + } + + efuse_end = efuse_end + 2; + for (i = 0; i < 4; i++) { + if (((pre_word_en >> i) & 0x1) > 0) { + status = write_hw_efuse_88xx(adapter, efuse_end, + *(info->efuse_map + + eeprom_offset + + (i << 1))); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse(<<1)\n"); + return status; + } + + status = write_hw_efuse_88xx(adapter, efuse_end + 1, + *(info->efuse_map + + eeprom_offset + (i << 1) + + 1)); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse(<<1)+1\n"); + return status; + } + efuse_end = efuse_end + 2; + } + } + adapter->efuse_end = efuse_end; + return status; +} + +static enum halmac_ret_status +proc_pg_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 word_en, + u8 pre_word_en, u32 eeprom_offset) +{ + u8 blk; + u8 hdr; + u16 i; + u32 efuse_end; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + efuse_end = adapter->efuse_end; + + blk = (u8)(eeprom_offset >> 3); + hdr = (u8)((blk << 4) + word_en); + + status = write_hw_efuse_88xx(adapter, efuse_end, hdr); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse\n"); + return status; + } + efuse_end = efuse_end + 1; + for (i = 0; i < 4; i++) { + if (((pre_word_en >> i) & 0x1) > 0) { + status = write_hw_efuse_88xx(adapter, efuse_end, + *(info->efuse_map + + eeprom_offset + + (i << 1))); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse(<<1)\n"); + return status; + } + status = write_hw_efuse_88xx(adapter, efuse_end + 1, + *(info->efuse_map + + eeprom_offset + (i << 1) + + 1)); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]write efuse(<<1)+1\n"); + return status; + } + efuse_end = efuse_end + 2; + } + } + adapter->efuse_end = efuse_end; + return status; +} + +static enum halmac_ret_status +program_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, u8 *updated_mask) +{ + u8 pre_word_en; + u8 word_en; + u16 i; + u32 eeprom_offset; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + for (i = 0; i < info->efuse_map_size; i = i + 8) { + eeprom_offset = i; + + if (((eeprom_offset >> 3) & 1) > 0) { + pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F); + word_en = pre_word_en ^ 0x0F; + } else { + pre_word_en = (*(updated_mask + (i >> 4)) >> 4); + word_en = pre_word_en ^ 0x0F; + } + + if (pre_word_en > 0) { + if (eeprom_offset > 0x7f) { + status = pg_extend_efuse_88xx(adapter, info, + word_en, + pre_word_en, + eeprom_offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]extend efuse\n"); + return status; + } + } else { + status = proc_pg_efuse_88xx(adapter, info, + word_en, + pre_word_en, + eeprom_offset); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]extend efuse"); + return status; + } + } + } + } + + return status; +} + +static void +mask_eeprom_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info) +{ + u8 pre_word_en; + u8 *updated_mask; + u8 *efuse_map; + u16 i; + u16 j; + u32 offset; + + updated_mask = info->efuse_mask; + efuse_map = info->efuse_map; + + for (i = 0; i < info->efuse_map_size; i = i + 8) { + offset = i; + + if (((offset >> 3) & 1) > 0) + pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F); + else + pre_word_en = (*(updated_mask + (i >> 4)) >> 4); + + for (j = 0; j < 4; j++) { + if (((pre_word_en >> j) & 0x1) == 0) { + *(efuse_map + offset + (j << 1)) = 0xFF; + *(efuse_map + offset + (j << 1) + 1) = 0xFF; + } + } + } +} + +enum halmac_ret_status +get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seg_id; + u8 seg_size; + u8 seq_num; + u8 fw_rc; + u8 *map = NULL; + u32 eeprom_size = adapter->hw_cfg_info.eeprom_size; + struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state; + enum halmac_cmd_process_status proc_status; + + seq_num = (u8)EFUSE_DATA_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + seg_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(buf); + seg_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(buf); + if (seg_id == 0) + adapter->efuse_seg_size = seg_size; + + map = (u8 *)PLTFM_MALLOC(eeprom_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, eeprom_size); + + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + PLTFM_MEMCPY(adapter->efuse_map + seg_id * adapter->efuse_seg_size, + buf + C2H_DATA_OFFSET_88XX, seg_size); + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + if (EFUSE_DATA_GET_END_SEGMENT(buf) == 0) { + PLTFM_FREE(map, eeprom_size); + return HALMAC_RET_SUCCESS; + } + + fw_rc = state->fw_rc; + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + adapter->efuse_map_valid = 1; + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + if (adapter->evnt.phy_efuse_map == 1) { + PLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE, + proc_status, adapter->efuse_map, + adapter->hw_cfg_info.efuse_size); + adapter->evnt.phy_efuse_map = 0; + } + + if (adapter->evnt.log_efuse_map == 1) { + if (eeprom_parser_88xx(adapter, adapter->efuse_map, + map) != HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status, + map, eeprom_size); + adapter->evnt.log_efuse_map = 0; + } + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + + if (adapter->evnt.phy_efuse_map == 1) { + PLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE, proc_status, + &state->fw_rc, 1); + adapter->evnt.phy_efuse_map = 0; + } + + if (adapter->evnt.log_efuse_map == 1) { + PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status, + &state->fw_rc, 1); + adapter->evnt.log_efuse_map = 0; + } + } + + PLTFM_FREE(map, eeprom_size); + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, + u8 *data, u32 *size) +{ + u8 *map = NULL; + u32 efuse_size = adapter->hw_cfg_info.efuse_size; + struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state; + + *proc_status = state->proc_status; + + if (!data) + return HALMAC_RET_NULL_POINTER; + + if (!size) + return HALMAC_RET_NULL_POINTER; + + if (*proc_status == HALMAC_CMD_PROCESS_DONE) { + if (*size < efuse_size) { + *size = efuse_size; + return HALMAC_RET_BUFFER_TOO_SMALL; + } + + *size = efuse_size; + + map = (u8 *)PLTFM_MALLOC(efuse_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, efuse_size); + PLTFM_MUTEX_LOCK(&adapter->efuse_mutex); + PLTFM_MEMCPY(map, adapter->efuse_map, + efuse_size - PROTECT_EFUSE_SIZE); + PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE + + RSVD_CS_EFUSE_SIZE, + adapter->efuse_map + efuse_size - + PROTECT_EFUSE_SIZE + RSVD_CS_EFUSE_SIZE, + PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE - + RSVD_CS_EFUSE_SIZE); + PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex); + + PLTFM_MEMCPY(data, map, *size); + + PLTFM_FREE(map, efuse_size); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, + u8 *data, u32 *size) +{ + u8 *map = NULL; + u32 eeprom_size = adapter->hw_cfg_info.eeprom_size; + struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state; + + *proc_status = state->proc_status; + + if (!data) + return HALMAC_RET_NULL_POINTER; + + if (!size) + return HALMAC_RET_NULL_POINTER; + + if (*proc_status == HALMAC_CMD_PROCESS_DONE) { + if (*size < eeprom_size) { + *size = eeprom_size; + return HALMAC_RET_BUFFER_TOO_SMALL; + } + + *size = eeprom_size; + + map = (u8 *)PLTFM_MALLOC(eeprom_size); + if (!map) { + PLTFM_MSG_ERR("[ERR]malloc map\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLTFM_MEMSET(map, 0xFF, eeprom_size); + + if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) != + HALMAC_RET_SUCCESS) { + PLTFM_FREE(map, eeprom_size); + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + + PLTFM_MEMCPY(data, map, *size); + + PLTFM_FREE(map, eeprom_size); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num = 0; + u8 fw_rc; + struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not cmd sending\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + return HALMAC_RET_SUCCESS; +} + +u32 +get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter) +{ + return PROTECT_EFUSE_SIZE; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_efuse_88xx.h b/hal/halmac/halmac_88xx/halmac_efuse_88xx.h new file mode 100644 index 0000000..5bf97fa --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_efuse_88xx.h @@ -0,0 +1,105 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_EFUSE_88XX_H_ +#define _HALMAC_EFUSE_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +dump_efuse_map_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg); + +enum halmac_ret_status +dump_efuse_map_bt_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_bank bank, u32 size, u8 *map); + +enum halmac_ret_status +write_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value, + enum halmac_efuse_bank bank); + +enum halmac_ret_status +read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value, + enum halmac_efuse_bank bank); + +enum halmac_ret_status +cfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable); + +enum halmac_ret_status +get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size); + +enum halmac_ret_status +get_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size); + +enum halmac_ret_status +get_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size); + +enum halmac_ret_status +dump_log_efuse_map_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg); + +enum halmac_ret_status +read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value); + +enum halmac_ret_status +write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value); + +enum halmac_ret_status +pg_efuse_by_map_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, + enum halmac_efuse_read_cfg cfg); + +enum halmac_ret_status +mask_log_efuse_88xx(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info); + +enum halmac_ret_status +read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map); + +enum halmac_ret_status +write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value); + +enum halmac_ret_status +switch_efuse_bank_88xx(struct halmac_adapter *adapter, + enum halmac_efuse_bank bank); + +enum halmac_ret_status +get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +cnv_efuse_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state); + +enum halmac_ret_status +get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, + u8 *data, u32 *size); + +enum halmac_ret_status +get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status, + u8 *data, u32 *size); + +enum halmac_ret_status +get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +u32 +get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_EFUSE_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_flash_88xx.c b/hal/halmac/halmac_88xx/halmac_flash_88xx.c new file mode 100644 index 0000000..24bc5b6 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_flash_88xx.c @@ -0,0 +1,316 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_flash_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_common_88xx.h" + +#if HALMAC_88XX_SUPPORT + +/** + * download_flash_88xx() -download firmware to flash + * @adapter : the adapter of halmac + * @fw_bin : pointer to fw + * @size : fw size + * @rom_addr : flash start address where fw should be download + * Author : Pablo Chiu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 rom_addr) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status rc; + struct halmac_h2c_header_info hdr_info; + u8 value8; + u8 restore[3]; + u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0}; + u16 seq_num = 0; + u16 h2c_info_offset; + u32 pkt_size; + u32 mem_offset; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + value8 = HALMAC_REG_R8(REG_CR + 1); + restore[0] = value8; + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_W8(REG_CR + 1, value8); + + value8 = HALMAC_REG_R8(REG_BCN_CTRL); + restore[1] = value8; + value8 = (u8)((value8 & ~(BIT(3))) | BIT(4)); + HALMAC_REG_W8(REG_BCN_CTRL, value8); + + value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2); + restore[2] = value8; + value8 = (u8)(value8 & ~(BIT(6))); + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8); + + /* Download FW to Flash flow */ + h2c_info_offset = adapter->txff_alloc.rsvd_h2c_info_addr - + adapter->txff_alloc.rsvd_boundary; + mem_offset = 0; + + while (size != 0) { + if (size >= (DL_FLASH_RSVDPG_SIZE - 48)) + pkt_size = DL_FLASH_RSVDPG_SIZE - 48; + else + pkt_size = size; + + rc = dl_rsvd_page_88xx(adapter, + adapter->txff_alloc.rsvd_h2c_info_addr, + fw_bin + mem_offset, pkt_size); + if (rc != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n"); + return rc; + } + + DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x02); + DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_offset); + DOWNLOAD_FLASH_SET_SIZE(h2c_buf, pkt_size); + DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, rom_addr); + + hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; + hdr_info.content_size = 20; + hdr_info.ack = 1; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + rc = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (rc != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + return rc; + } + + value8 = HALMAC_REG_R8(REG_MCUTST_I); + value8 |= BIT(0); + HALMAC_REG_W8(REG_MCUTST_I, value8); + + rom_addr += pkt_size; + mem_offset += pkt_size; + size -= pkt_size; + + while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) + PLTFM_DELAY_US(1000); + + if (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) { + PLTFM_MSG_ERR("[ERR]dl flash!!\n"); + return HALMAC_RET_DLFW_FAIL; + } + } + + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]); + HALMAC_REG_W8(REG_BCN_CTRL, restore[1]); + HALMAC_REG_W8(REG_CR + 1, restore[0]); + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * read_flash_88xx() -read data from flash + * @adapter : the adapter of halmac + * @addr : flash start address where fw should be read + * Author : Pablo Chiu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status; + struct halmac_h2c_header_info hdr_info; + u8 value8; + u8 restore[3]; + u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0}; + u16 seq_num = 0; + u16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + u16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + value8 = HALMAC_REG_R8(REG_CR + 1); + restore[0] = value8; + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_W8(REG_CR + 1, value8); + + value8 = HALMAC_REG_R8(REG_BCN_CTRL); + restore[1] = value8; + value8 = (u8)((value8 & ~(BIT(3))) | BIT(4)); + HALMAC_REG_W8(REG_BCN_CTRL, value8); + + value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2); + restore[2] = value8; + value8 = (u8)(value8 & ~(BIT(6))); + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8); + + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, h2c_info_addr); + value8 = HALMAC_REG_R8(REG_MCUTST_I); + value8 |= BIT(0); + HALMAC_REG_W8(REG_MCUTST_I, value8); + + /* Construct H2C Content */ + DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x03); + DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_addr - rsvd_pg_addr); + DOWNLOAD_FLASH_SET_SIZE(h2c_buf, length); + DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr); + + /* Fill in H2C Header */ + hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; + hdr_info.content_size = 16; + hdr_info.ack = 1; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + /* Send H2C Cmd Packet */ + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + return status; + } + + while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) + PLTFM_DELAY_US(1000); + + HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_addr); + HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]); + HALMAC_REG_W8(REG_BCN_CTRL, restore[1]); + HALMAC_REG_W8(REG_CR + 1, restore[0]); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * erase_flash_88xx() -erase flash data + * @adapter : the adapter of halmac + * @erase_cmd : erase command + * @addr : flash start address where fw should be erased + * Author : Pablo Chiu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr) +{ + enum halmac_ret_status status; + struct halmac_h2c_header_info hdr_info; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 value8; + u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0}; + u16 seq_num = 0; + u32 cnt; + + /* Construct H2C Content */ + DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, erase_cmd); + DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, 0); + DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr); + DOWNLOAD_FLASH_SET_SIZE(h2c_buf, 0); + + value8 = HALMAC_REG_R8(REG_MCUTST_I); + value8 |= BIT(0); + HALMAC_REG_W8(REG_MCUTST_I, value8); + + /* Fill in H2C Header */ + hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH; + hdr_info.content_size = 16; + hdr_info.ack = 1; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + /* Send H2C Cmd Packet */ + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + + cnt = 5000; + while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0 && cnt != 0) { + PLTFM_DELAY_US(1000); + cnt--; + } + + if (cnt == 0) + return HALMAC_RET_FAIL; + else + return HALMAC_RET_SUCCESS; +} + +/** + * check_flash_88xx() -check flash data + * @adapter : the adapter of halmac + * @fw_bin : pointer to fw + * @size : fw size + * @addr : flash start address where fw should be checked + * Author : Pablo Chiu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 addr) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 value8; + u16 i; + u16 residue; + u16 pg_addr; + u32 pkt_size; + u32 start_page; + u32 cnt; + + pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + + while (size != 0) { + start_page = ((pg_addr << 7) >> 12) + 0x780; + residue = (pg_addr << 7) & (4096 - 1); + + if (size >= DL_FLASH_RSVDPG_SIZE) + pkt_size = DL_FLASH_RSVDPG_SIZE; + else + pkt_size = size; + + read_flash_88xx(adapter, addr, 4096); + + cnt = 0; + while (cnt < pkt_size) { + HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)(start_page)); + for (i = 0x8000 + residue; i <= 0x8FFF; i++) { + value8 = HALMAC_REG_R8(i); + if (*fw_bin != value8) { + PLTFM_MSG_ERR("[ERR]check flash!!\n"); + return HALMAC_RET_FAIL; + } + + fw_bin++; + cnt++; + if (cnt == pkt_size) + break; + } + residue = 0; + start_page++; + } + addr += pkt_size; + size -= pkt_size; + } + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_flash_88xx.h b/hal/halmac/halmac_88xx/halmac_flash_88xx.h new file mode 100644 index 0000000..41429df --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_flash_88xx.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_FLASH_88XX_H_ +#define _HALMAC_FLASH_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 rom_addr); + +enum halmac_ret_status +read_flash_88xx(struct halmac_adapter *adapter, u32 addr, u32 length); + +enum halmac_ret_status +erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr); + +enum halmac_ret_status +check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 addr); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_FLASH_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_fw_88xx.c b/hal/halmac/halmac_88xx/halmac_fw_88xx.c new file mode 100644 index 0000000..1a960dc --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_fw_88xx.c @@ -0,0 +1,1167 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_fw_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_common_88xx.h" +#include "halmac_init_88xx.h" + +#if HALMAC_88XX_SUPPORT + +#define DLFW_RESTORE_REG_NUM 6 +#define ILLEGAL_KEY_GROUP 0xFAAAAA00 + +/* Max dlfw size can not over 31K, due to SDIO HW limitation */ +#define DLFW_PKT_SIZE_LIMIT 31744 + +#define ID_INFORM_DLEMEM_RDY 0x80 +#define ID_INFORM_ENETR_CPU_SLEEP 0x20 +#define ID_CHECK_DLEMEM_RDY 0x80 +#define ID_CHECK_ENETR_CPU_SLEEP 0x05 + +#define FW_STATUS_CHK_FATAL (BIT(1) | BIT(20)) +#define FW_STATUS_CHK_ERR (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | \ + BIT(9) | BIT(12) | BIT(14) | BIT(15) | \ + BIT(16) | BIT(17) | BIT(18) | BIT(19) | \ + BIT(21) | BIT(22) | BIT(25)) +#define FW_STATUS_CHK_WARN ~(FW_STATUS_CHK_FATAL | FW_STATUS_CHK_ERR) + +struct halmac_backup_info { + u32 mac_register; + u32 value; + u8 length; +}; + +static enum halmac_ret_status +update_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin); + +static void +restore_mac_reg_88xx(struct halmac_adapter *adapter, + struct halmac_backup_info *info, u32 num); + +static enum halmac_ret_status +dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest, + u32 size); + +static enum halmac_ret_status +dlfw_end_flow_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +free_dl_fw_end_flow_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +send_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin, + u32 size); + +static enum halmac_ret_status +iddma_dlfw_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 len, + u8 first); + +static enum halmac_ret_status +iddma_en_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 ctrl); + +static enum halmac_ret_status +check_fw_chksum_88xx(struct halmac_adapter *adapter, u32 mem_addr); + +static void +fw_fatal_status_debug_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 dl_addr, u8 emem_only); + +static enum halmac_ret_status +chk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size); + +static void +chk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin); + +static void +wlan_cpu_en_88xx(struct halmac_adapter *adapter, u8 enable); + +static void +pltfm_reset_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +proc_send_general_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info); + +static enum halmac_ret_status +proc_send_phydm_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info); + +/** + * download_firmware_88xx() - download Firmware + * @adapter : the adapter of halmac + * @fw_bin : firmware bin + * @size : firmware size + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +download_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size) +{ + u8 value8; + u32 bckp_idx = 0; + u32 lte_coex_backup = 0; + struct halmac_backup_info bckp[DLFW_RESTORE_REG_NUM]; + enum halmac_ret_status status; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) + return HALMAC_RET_POWER_STATE_INVALID; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = chk_fw_size_88xx(adapter, fw_bin, size); + if (status != HALMAC_RET_SUCCESS) + return status; + + chk_h2c_ver_88xx(adapter, fw_bin); + + if (adapter->halmac_state.wlcpu_mode == HALMAC_WLCPU_ENTER_SLEEP) + PLTFM_MSG_WARN("[WARN]Enter Sleep..zZZ\n"); + + adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + + status = ltecoex_reg_read_88xx(adapter, 0x38, <e_coex_backup); + if (status != HALMAC_RET_SUCCESS) + return status; + + wlan_cpu_en_88xx(adapter, 0); + + /* set HIQ to hi priority */ + bckp[bckp_idx].length = 1; + bckp[bckp_idx].mac_register = REG_TXDMA_PQ_MAP + 1; + bckp[bckp_idx].value = HALMAC_REG_R8(REG_TXDMA_PQ_MAP + 1); + bckp_idx++; + value8 = HALMAC_DMA_MAPPING_HIGH << 6; + HALMAC_REG_W8(REG_TXDMA_PQ_MAP + 1, value8); + + /* DLFW only use HIQ, map HIQ to hi priority */ + adapter->pq_map[HALMAC_PQ_MAP_HI] = HALMAC_DMA_MAPPING_HIGH; + bckp[bckp_idx].length = 1; + bckp[bckp_idx].mac_register = REG_CR; + bckp[bckp_idx].value = HALMAC_REG_R8(REG_CR); + bckp_idx++; + bckp[bckp_idx].length = 4; + bckp[bckp_idx].mac_register = REG_H2CQ_CSR; + bckp[bckp_idx].value = BIT(31); + bckp_idx++; + value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; + HALMAC_REG_W8(REG_CR, value8); + HALMAC_REG_W32(REG_H2CQ_CSR, BIT(31)); + + /* Config hi priority queue and public priority queue page number */ + bckp[bckp_idx].length = 2; + bckp[bckp_idx].mac_register = REG_FIFOPAGE_INFO_1; + bckp[bckp_idx].value = HALMAC_REG_R16(REG_FIFOPAGE_INFO_1); + bckp_idx++; + bckp[bckp_idx].length = 4; + bckp[bckp_idx].mac_register = REG_RQPN_CTRL_2; + bckp[bckp_idx].value = HALMAC_REG_R32(REG_RQPN_CTRL_2) | BIT(31); + bckp_idx++; + HALMAC_REG_W16(REG_FIFOPAGE_INFO_1, 0x200); + HALMAC_REG_W32(REG_RQPN_CTRL_2, bckp[bckp_idx - 1].value); + + /* Disable beacon related functions */ + value8 = HALMAC_REG_R8(REG_BCN_CTRL); + bckp[bckp_idx].length = 1; + bckp[bckp_idx].mac_register = REG_BCN_CTRL; + bckp[bckp_idx].value = value8; + bckp_idx++; + value8 = (u8)((value8 & (~BIT(3))) | BIT(4)); + HALMAC_REG_W8(REG_BCN_CTRL, value8); + + if (adapter->intf == HALMAC_INTERFACE_SDIO) + HALMAC_REG_R32(REG_SDIO_FREE_TXPG); + + pltfm_reset_88xx(adapter); + + status = start_dlfw_88xx(adapter, fw_bin, size, 0, 0); + + restore_mac_reg_88xx(adapter, bckp, DLFW_RESTORE_REG_NUM); + + if (status != HALMAC_RET_SUCCESS) + goto DLFW_FAIL; + + status = dlfw_end_flow_88xx(adapter); + if (status != HALMAC_RET_SUCCESS) + goto DLFW_FAIL; + + status = ltecoex_reg_write_88xx(adapter, 0x38, lte_coex_backup); + if (status != HALMAC_RET_SUCCESS) + return status; + + adapter->halmac_state.dlfw_state = HALMAC_DLFW_DONE; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; + +DLFW_FAIL: + + /* Disable FWDL_EN */ + value8 = HALMAC_REG_R8(REG_MCUFW_CTRL); + value8 &= ~BIT(0); + HALMAC_REG_W8(REG_MCUFW_CTRL, value8); + + value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1); + value8 |= BIT(2); + HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8); + + if (ltecoex_reg_write_88xx(adapter, 0x38, lte_coex_backup) != + HALMAC_RET_SUCCESS) + return HALMAC_RET_LTECOEX_READY_FAIL; + + return status; +} + +static enum halmac_ret_status +start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size, + u32 dl_addr, u8 emem_only) +{ + u8 *cur_fw; + u16 value16; + u32 imem_size; + u32 dmem_size; + u32 emem_size = 0; + u32 addr; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status; + + dmem_size = + rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE))); + imem_size = + rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE))); + if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4))) + emem_size = + rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE))); + + dmem_size += WLAN_FW_HDR_CHKSUM_SIZE; + imem_size += WLAN_FW_HDR_CHKSUM_SIZE; + if (emem_size != 0) + emem_size += WLAN_FW_HDR_CHKSUM_SIZE; + + if (emem_only == 1) { + if (!emem_size) + return HALMAC_RET_SUCCESS; + goto DLFW_EMEM; + } + + value16 = (u16)(HALMAC_REG_R16(REG_MCUFW_CTRL) & 0x3800); + value16 |= BIT(0); + HALMAC_REG_W16(REG_MCUFW_CTRL, value16); + + cur_fw = fw_bin + WLAN_FW_HDR_SIZE; + addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_ADDR))); + addr &= ~BIT(31); + status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, dmem_size); + if (status != HALMAC_RET_SUCCESS) + return status; + + cur_fw = fw_bin + WLAN_FW_HDR_SIZE + dmem_size; + addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_ADDR))); + addr &= ~BIT(31); + status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, imem_size); + if (status != HALMAC_RET_SUCCESS) + return status; + +DLFW_EMEM: + if (emem_size) { + cur_fw = fw_bin + WLAN_FW_HDR_SIZE + + dmem_size + imem_size; + addr = rtk_le32_to_cpu(*((__le32 *)(fw_bin + + WLAN_FW_HDR_EMEM_ADDR))); + addr &= ~BIT(31); + status = dlfw_to_mem_88xx(adapter, cur_fw, dl_addr << 7, addr, + emem_size); + if (status != HALMAC_RET_SUCCESS) + return status; + + if (emem_only == 1) + return HALMAC_RET_SUCCESS; + } + + update_fw_info_88xx(adapter, fw_bin); + init_ofld_feature_state_machine_88xx(adapter); + + return HALMAC_RET_SUCCESS; +} + +static void +chk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin) +{ + u16 halmac_h2c_ver; + u16 fw_h2c_ver; + + fw_h2c_ver = rtk_le16_to_cpu(*((__le16 *)(fw_bin + + WLAN_FW_HDR_H2C_FMT_VER))); + halmac_h2c_ver = H2C_FORMAT_VERSION; + + PLTFM_MSG_TRACE("[TRACE]halmac h2c ver = %x, fw h2c ver = %x!!\n", + halmac_h2c_ver, fw_h2c_ver); +} + +static enum halmac_ret_status +chk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size) +{ + u32 imem_size; + u32 dmem_size; + u32 emem_size = 0; + u32 real_size; + + if (size < WLAN_FW_HDR_SIZE) { + PLTFM_MSG_ERR("[ERR]FW size error!\n"); + return HALMAC_RET_FW_SIZE_ERR; + } + + dmem_size = + rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE))); + imem_size = + rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE))); + if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4))) + emem_size = + rtk_le32_to_cpu(*((__le32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE))); + + dmem_size += WLAN_FW_HDR_CHKSUM_SIZE; + imem_size += WLAN_FW_HDR_CHKSUM_SIZE; + if (emem_size != 0) + emem_size += WLAN_FW_HDR_CHKSUM_SIZE; + + real_size = WLAN_FW_HDR_SIZE + dmem_size + imem_size + emem_size; + if (size != real_size) { + PLTFM_MSG_ERR("[ERR]size != real size!\n"); + return HALMAC_RET_FW_SIZE_ERR; + } + + return HALMAC_RET_SUCCESS; +} + +static void +wlan_cpu_en_88xx(struct halmac_adapter *adapter, u8 enable) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (enable == 1) { + /* cpu io interface enable or disable */ + value8 = HALMAC_REG_R8(REG_RSV_CTRL + 1); + value8 |= BIT(0); + HALMAC_REG_W8(REG_RSV_CTRL + 1, value8); + + /* cpu enable or disable */ + value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1); + value8 |= BIT(2); + HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8); + + } else { + /* cpu enable or disable */ + value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1); + value8 &= ~BIT(2); + HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8); + + /* cpu io interface enable or disable */ + value8 = HALMAC_REG_R8(REG_RSV_CTRL + 1); + value8 &= ~BIT(0); + HALMAC_REG_W8(REG_RSV_CTRL + 1, value8); + } +} + +static void +pltfm_reset_88xx(struct halmac_adapter *adapter) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_CPU_DMEM_CON + 2) & ~BIT(0); + HALMAC_REG_W8(REG_CPU_DMEM_CON + 2, value8); + + /* For 8822B & 8821C clock sync issue */ + if (adapter->chip_id == HALMAC_CHIP_ID_8821C || + adapter->chip_id == HALMAC_CHIP_ID_8822B) { + value8 = HALMAC_REG_R8(REG_SYS_CLK_CTRL + 1) & ~BIT(6); + HALMAC_REG_W8(REG_SYS_CLK_CTRL + 1, value8); + } + + value8 = HALMAC_REG_R8(REG_CPU_DMEM_CON + 2) | BIT(0); + HALMAC_REG_W8(REG_CPU_DMEM_CON + 2, value8); + + if (adapter->chip_id == HALMAC_CHIP_ID_8821C || + adapter->chip_id == HALMAC_CHIP_ID_8822B) { + value8 = HALMAC_REG_R8(REG_SYS_CLK_CTRL + 1) | BIT(6); + HALMAC_REG_W8(REG_SYS_CLK_CTRL + 1, value8); + } +} + +/** + * free_download_firmware_88xx() - download specific memory firmware + * @adapter + * @mem_sel : memory selection + * @fw_bin : firmware bin + * @size : firmware size + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + */ +enum halmac_ret_status +free_download_firmware_88xx(struct halmac_adapter *adapter, + enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size) +{ + u8 tx_pause_bckp; + u32 dl_addr; + u32 dlfw_size_bckp; + enum halmac_ret_status status; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = chk_fw_size_88xx(adapter, fw_bin, size); + if (status != HALMAC_RET_SUCCESS) + return status; + + if (((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)) == 0) + return HALMAC_RET_SUCCESS; + + dlfw_size_bckp = adapter->dlfw_pkt_size; + if (mem_sel == HALMAC_DLFW_MEM_EMEM) { + dl_addr = 0; + } else { + dl_addr = adapter->txff_alloc.rsvd_h2c_info_addr; + adapter->dlfw_pkt_size = (dlfw_size_bckp > DLFW_RSVDPG_SIZE) ? + DLFW_RSVDPG_SIZE : dlfw_size_bckp; + } + + tx_pause_bckp = HALMAC_REG_R8(REG_TXPAUSE); + HALMAC_REG_W8(REG_TXPAUSE, tx_pause_bckp | BIT(7)); + + status = start_dlfw_88xx(adapter, fw_bin, size, dl_addr, 1); + if (status != HALMAC_RET_SUCCESS) + goto DL_FREE_FW_END; + + status = free_dl_fw_end_flow_88xx(adapter); + +DL_FREE_FW_END: + HALMAC_REG_W8(REG_TXPAUSE, tx_pause_bckp); + adapter->dlfw_pkt_size = dlfw_size_bckp; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +/** + * get_fw_version_88xx() - get FW version + * @adapter : the adapter of halmac + * @ver : fw version info + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_fw_version_88xx(struct halmac_adapter *adapter, + struct halmac_fw_version *ver) +{ + struct halmac_fw_version *info = &adapter->fw_ver; + + if (!ver) + return HALMAC_RET_NULL_POINTER; + + if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) + return HALMAC_RET_NO_DLFW; + + ver->version = info->version; + ver->sub_version = info->sub_version; + ver->sub_index = info->sub_index; + ver->h2c_version = info->h2c_version; + ver->build_time.month = info->build_time.month; + ver->build_time.date = info->build_time.date; + ver->build_time.hour = info->build_time.hour; + ver->build_time.min = info->build_time.min; + ver->build_time.year = info->build_time.year; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +update_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin) +{ + struct halmac_fw_version *info = &adapter->fw_ver; + + info->version = + rtk_le16_to_cpu(*((__le16 *)(fw_bin + WLAN_FW_HDR_VERSION))); + info->sub_version = *(fw_bin + WLAN_FW_HDR_SUBVERSION); + info->sub_index = *(fw_bin + WLAN_FW_HDR_SUBINDEX); + info->h2c_version = rtk_le16_to_cpu(*((__le16 *)(fw_bin + + WLAN_FW_HDR_H2C_FMT_VER))); + info->build_time.month = *(fw_bin + WLAN_FW_HDR_MONTH); + info->build_time.date = *(fw_bin + WLAN_FW_HDR_DATE); + info->build_time.hour = *(fw_bin + WLAN_FW_HDR_HOUR); + info->build_time.min = *(fw_bin + WLAN_FW_HDR_MIN); + info->build_time.year = + rtk_le16_to_cpu(*((__le16 *)(fw_bin + WLAN_FW_HDR_YEAR))); + + PLTFM_MSG_TRACE("[TRACE]=== FW info ===\n"); + PLTFM_MSG_TRACE("[TRACE]ver : %X\n", info->version); + PLTFM_MSG_TRACE("[TRACE]sub-ver : %X\n", + info->sub_version); + PLTFM_MSG_TRACE("[TRACE]sub-idx : %X\n", + info->sub_index); + PLTFM_MSG_TRACE("[TRACE]build : %d/%d/%d %d:%d\n", + info->build_time.year, info->build_time.month, + info->build_time.date, info->build_time.hour, + info->build_time.min); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest, + u32 size) +{ + u8 first_part; + u32 mem_offset; + u32 residue_size; + u32 pkt_size; + enum halmac_ret_status status; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + mem_offset = 0; + first_part = 1; + residue_size = size; + + HALMAC_REG_W32_SET(REG_DDMA_CH0CTRL, BIT_DDMACH0_RESET_CHKSUM_STS); + + while (residue_size != 0) { + if (residue_size >= adapter->dlfw_pkt_size) + pkt_size = adapter->dlfw_pkt_size; + else + pkt_size = residue_size; + + status = send_fwpkt_88xx(adapter, (u16)(src >> 7), + fw_bin + mem_offset, pkt_size); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send fw pkt!!\n"); + return status; + } + + status = iddma_dlfw_88xx(adapter, + OCPBASE_TXBUF_88XX + + src + adapter->hw_cfg_info.txdesc_size, + dest + mem_offset, pkt_size, + first_part); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]iddma dlfw!!\n"); + return status; + } + + first_part = 0; + mem_offset += pkt_size; + residue_size -= pkt_size; + } + + status = check_fw_chksum_88xx(adapter, dest); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]chk fw chksum!!\n"); + return status; + } + + return HALMAC_RET_SUCCESS; +} + +static void +restore_mac_reg_88xx(struct halmac_adapter *adapter, + struct halmac_backup_info *info, u32 num) +{ + u8 len; + u32 i; + u32 reg; + u32 value; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + struct halmac_backup_info *curr_info = info; + + for (i = 0; i < num; i++) { + reg = curr_info->mac_register; + value = curr_info->value; + len = curr_info->length; + + if (len == 1) + HALMAC_REG_W8(reg, (u8)value); + else if (len == 2) + HALMAC_REG_W16(reg, (u16)value); + else if (len == 4) + HALMAC_REG_W32(reg, value); + + curr_info++; + } +} + +static enum halmac_ret_status +dlfw_end_flow_88xx(struct halmac_adapter *adapter) +{ + u16 fw_ctrl; + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W32(REG_TXDMA_STATUS, BIT(2)); + + /* Check IMEM & DMEM checksum is OK or not */ + fw_ctrl = HALMAC_REG_R16(REG_MCUFW_CTRL); + if ((fw_ctrl & 0x50) != 0x50) + return HALMAC_RET_IDMEM_CHKSUM_FAIL; + + HALMAC_REG_W16(REG_MCUFW_CTRL, (fw_ctrl | BIT_FW_DW_RDY) & ~BIT(0)); + + wlan_cpu_en_88xx(adapter, 1); + PLTFM_MSG_TRACE("[TRACE]Dlfw OK, enable CPU\n"); + + cnt = 5000; + while (HALMAC_REG_R16(REG_MCUFW_CTRL) != 0xC078) { + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]Check 0x80 = 0xC078 fail\n"); + if ((HALMAC_REG_R32(REG_FW_DBG7) & 0xFFFFFF00) == + ILLEGAL_KEY_GROUP) { + PLTFM_MSG_ERR("[ERR]Key!!\n"); + return HALMAC_RET_ILLEGAL_KEY_FAIL; + } + return HALMAC_RET_FW_READY_CHK_FAIL; + } + cnt--; + PLTFM_DELAY_US(50); + } + + PLTFM_MSG_TRACE("[TRACE]0x80=0xC078, cnt=%d\n", cnt); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +free_dl_fw_end_flow_88xx(struct halmac_adapter *adapter) +{ + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + cnt = 100; + while (HALMAC_REG_R8(REG_HMETFR + 3) != 0) { + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]0x1CF != 0\n"); + return HALMAC_RET_DLFW_FAIL; + } + PLTFM_DELAY_US(50); + } + + HALMAC_REG_W8(REG_HMETFR + 3, ID_INFORM_DLEMEM_RDY); + + cnt = 10000; + while (HALMAC_REG_R8(REG_MCU_TST_CFG) != ID_CHECK_DLEMEM_RDY) { + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]0x84 != 0x80\n"); + return HALMAC_RET_DLFW_FAIL; + } + PLTFM_DELAY_US(50); + } + + HALMAC_REG_W8(REG_MCU_TST_CFG, 0); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +send_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin, + u32 size) +{ + u8 *fw_add_dum = NULL; + enum halmac_ret_status status; + + if (adapter->intf == HALMAC_INTERFACE_USB && + !((size + TX_DESC_SIZE_88XX) & (512 - 1))) { + fw_add_dum = (u8 *)PLTFM_MALLOC(size + 1); + if (!fw_add_dum) { + PLTFM_MSG_ERR("[ERR]fw bin malloc!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + + PLTFM_MEMCPY(fw_add_dum, fw_bin, size); + + status = dl_rsvd_page_88xx(adapter, pg_addr, + fw_add_dum, size + 1); + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]dl rsvd page - dum!!\n"); + + PLTFM_FREE(fw_add_dum, size + 1); + + return status; + } + + status = dl_rsvd_page_88xx(adapter, pg_addr, fw_bin, size); + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]dl rsvd page!!\n"); + + return status; +} + +static enum halmac_ret_status +iddma_dlfw_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 len, + u8 first) +{ + u32 cnt; + u32 ch0_ctrl = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN); + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + cnt = HALMC_DDMA_POLLING_COUNT; + while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]ch0 ready!!\n"); + return HALMAC_RET_DDMA_FAIL; + } + } + + ch0_ctrl |= (len & BIT_MASK_DDMACH0_DLEN); + if (first == 0) + ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT; + + if (iddma_en_88xx(adapter, src, dest, ch0_ctrl) != + HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]iddma en!!\n"); + return HALMAC_RET_DDMA_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +iddma_en_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 ctrl) +{ + u32 cnt = HALMC_DDMA_POLLING_COUNT; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W32(REG_DDMA_CH0SA, src); + HALMAC_REG_W32(REG_DDMA_CH0DA, dest); + HALMAC_REG_W32(REG_DDMA_CH0CTRL, ctrl); + + while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { + cnt--; + if (cnt == 0) + return HALMAC_RET_DDMA_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +check_fw_chksum_88xx(struct halmac_adapter *adapter, u32 mem_addr) +{ + u8 fw_ctrl; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + fw_ctrl = HALMAC_REG_R8(REG_MCUFW_CTRL); + + if (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) { + if (mem_addr < OCPBASE_DMEM_88XX) { + fw_ctrl |= BIT_IMEM_DW_OK; + fw_ctrl &= ~BIT_IMEM_CHKSUM_OK; + HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl); + } else { + fw_ctrl |= BIT_DMEM_DW_OK; + fw_ctrl &= ~BIT_DMEM_CHKSUM_OK; + HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl); + } + + PLTFM_MSG_ERR("[ERR]fw chksum!!\n"); + + return HALMAC_RET_FW_CHECKSUM_FAIL; + } + + if (mem_addr < OCPBASE_DMEM_88XX) { + fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK); + HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl); + } else { + fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK); + HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl); + } + + return HALMAC_RET_SUCCESS; +} + +/** + * check_fw_status_88xx() -check fw status + * @adapter : the adapter of halmac + * @status : fw status + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status) +{ + u32 cnt; + u32 fw_dbg6; + u32 fw_pc; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + *fw_status = 1; + + fw_dbg6 = HALMAC_REG_R32(REG_FW_DBG6); + + if (fw_dbg6 != 0) { + PLTFM_MSG_ERR("[ERR]REG_FW_DBG6 !=0\n"); + if ((fw_dbg6 & FW_STATUS_CHK_WARN) != 0) + PLTFM_MSG_WARN("[WARN]fw status(warn):%X\n", fw_dbg6); + + if ((fw_dbg6 & FW_STATUS_CHK_ERR) != 0) + PLTFM_MSG_ERR("[ERR]fw status(err):%X\n", fw_dbg6); + + if ((fw_dbg6 & FW_STATUS_CHK_FATAL) != 0) { + PLTFM_MSG_ERR("[ERR]fw status(fatal):%X\n", fw_dbg6); + fw_fatal_status_debug_88xx(adapter); + *fw_status = 0; + return status; + } + } + + fw_pc = HALMAC_REG_R32(REG_FW_DBG7); + cnt = 10; + while (HALMAC_REG_R32(REG_FW_DBG7) == fw_pc) { + cnt--; + if (cnt == 0) + break; + } + + if (cnt == 0) { + cnt = 200; + while (HALMAC_REG_R32(REG_FW_DBG7) == fw_pc) { + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]fw pc\n"); + *fw_status = 0; + return status; + } + PLTFM_DELAY_US(50); + } + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +static void +fw_fatal_status_debug_88xx(struct halmac_adapter *adapter) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_ERR("[ERR]0x%X = %X\n", + REG_FW_DBG6, HALMAC_REG_R32(REG_FW_DBG6)); + + PLTFM_MSG_ERR("[ERR]0x%X = %X\n", + REG_ARFR5, HALMAC_REG_R32(REG_ARFR5)); + + PLTFM_MSG_ERR("[ERR]0x%X = %X\n", + REG_MCUTST_I, HALMAC_REG_R32(REG_MCUTST_I)); +} + +enum halmac_ret_status +dump_fw_dmem_88xx(struct halmac_adapter *adapter, u8 *dmem, u32 *size) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_max_dl_size_88xx() - config max download FW size + * @adapter : the adapter of halmac + * @size : max download fw size + * + * Halmac uses this setting to set max packet size for + * download FW. + * If user has not called this API, halmac use default + * setting for download FW + * Note1 : size need multiple of 2 + * Note2 : max size is 31K + * + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_max_dl_size_88xx(struct halmac_adapter *adapter, u32 size) +{ + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (size > DLFW_PKT_SIZE_LIMIT) { + PLTFM_MSG_ERR("[ERR]size > max dl size!\n"); + return HALMAC_RET_CFG_DLFW_SIZE_FAIL; + } + + if ((size & (2 - 1)) != 0) { + PLTFM_MSG_ERR("[ERR]not multiple of 2!\n"); + return HALMAC_RET_CFG_DLFW_SIZE_FAIL; + } + + adapter->dlfw_pkt_size = size; + + PLTFM_MSG_TRACE("[TRACE]Cfg max size:%X\n", size); + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * enter_cpu_sleep_mode_88xx() -wlan cpu enter sleep mode + * @adapter : the adapter of halmac + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +enter_cpu_sleep_mode_88xx(struct halmac_adapter *adapter) +{ + u32 cnt; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_wlcpu_mode *cur_mode = &adapter->halmac_state.wlcpu_mode; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (*cur_mode != HALMAC_WLCPU_ACTIVE) + return HALMAC_RET_ERROR_STATE; + + cnt = 100; + while (HALMAC_REG_R8(REG_HMETFR + 3) != 0) { + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]0x1CF != 0\n"); + return HALMAC_RET_STATE_INCORRECT; + } + PLTFM_DELAY_US(50); + } + + HALMAC_REG_W8(REG_HMETFR + 3, ID_INFORM_ENETR_CPU_SLEEP); + + *cur_mode = HALMAC_WLCPU_ENTER_SLEEP; + + return HALMAC_RET_SUCCESS; +} + +/** + * get_cpu_mode_88xx() -get wlcpu mode + * @adapter : the adapter of halmac + * @mode : cpu mode + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_cpu_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wlcpu_mode *mode) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_wlcpu_mode *cur_mode = &adapter->halmac_state.wlcpu_mode; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (*cur_mode == HALMAC_WLCPU_ACTIVE) { + *mode = HALMAC_WLCPU_ACTIVE; + return HALMAC_RET_SUCCESS; + } + + if (*cur_mode == HALMAC_WLCPU_SLEEP) { + *mode = HALMAC_WLCPU_SLEEP; + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_REG_R8(REG_MCU_TST_CFG) == ID_CHECK_ENETR_CPU_SLEEP) { + *mode = HALMAC_WLCPU_SLEEP; + HALMAC_REG_W8(REG_MCU_TST_CFG, 0); + } else { + *mode = HALMAC_WLCPU_ENTER_SLEEP; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * send_general_info_88xx() -send general information to FW + * @adapter : the adapter of halmac + * @info : general information + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +send_general_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info) +{ + u8 h2cq_ele[4] = {0}; + u32 h2cq_addr; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) { + PLTFM_MSG_ERR("[ERR]no dl fw!!\n"); + return HALMAC_RET_NO_DLFW; + } + + status = proc_send_general_info_88xx(adapter, info); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send gen info!!\n"); + return status; + } + + status = proc_send_phydm_info_88xx(adapter, info); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send phydm info\n"); + return status; + } + + h2cq_addr = adapter->txff_alloc.rsvd_h2cq_addr; + h2cq_addr <<= TX_PAGE_SIZE_SHIFT_88XX; + status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_TX, + h2cq_addr, 4, h2cq_ele); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dump h2cq!!\n"); + return status; + } + + if ((h2cq_ele[0] & 0x7F) != 0x01 || h2cq_ele[1] != 0xFF) { + PLTFM_MSG_ERR("[ERR]h2cq compare!!\n"); + return HALMAC_RET_SEND_H2C_FAIL; + } + + if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_DONE) + adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +proc_send_general_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s\n", __func__); + + GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_buf, + adapter->txff_alloc.rsvd_fw_txbuf_addr - + adapter->txff_alloc.rsvd_boundary); + + hdr_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO; + hdr_info.content_size = 4; + hdr_info.ack = 0; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + + return status; +} + +static enum halmac_ret_status +proc_send_phydm_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s\n", __func__); + + PHYDM_INFO_SET_REF_TYPE(h2c_buf, info->rfe_type); + PHYDM_INFO_SET_RF_TYPE(h2c_buf, info->rf_type); + PHYDM_INFO_SET_CUT_VER(h2c_buf, adapter->chip_ver); + PHYDM_INFO_SET_RX_ANT_STATUS(h2c_buf, info->rx_ant_status); + PHYDM_INFO_SET_TX_ANT_STATUS(h2c_buf, info->tx_ant_status); + + hdr_info.sub_cmd_id = SUB_CMD_ID_PHYDM_INFO; + hdr_info.content_size = 8; + hdr_info.ack = 0; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + + return status; +} + +/** + * drv_fwctrl_88xx() - send drv-defined h2c pkt + * @adapter : the adapter of halmac + * @payload : no include offload pkt h2c header + * @size : no include offload pkt h2c header + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +drv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num = 0; + struct halmac_h2c_header_info hdr_info; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (!payload) + return HALMAC_RET_DATA_BUF_NULL; + + if (size > H2C_PKT_SIZE_88XX - H2C_PKT_HDR_SIZE_88XX) + return HALMAC_RET_DATA_SIZE_INCORRECT; + + PLTFM_MEMCPY(h2c_buf + H2C_PKT_HDR_SIZE_88XX, payload, size); + + hdr_info.sub_cmd_id = SUB_CMD_ID_FW_FWCTRL; + hdr_info.content_size = (u16)size; + hdr_info.ack = ack; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + + if (status != HALMAC_RET_SUCCESS) + PLTFM_MSG_ERR("[ERR]send h2c!!\n"); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_fw_88xx.h b/hal/halmac/halmac_88xx/halmac_fw_88xx.h new file mode 100644 index 0000000..d575a32 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_fw_88xx.h @@ -0,0 +1,61 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_FW_88XX_H_ +#define _HALMAC_FW_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +#define HALMC_DDMA_POLLING_COUNT 1000 + +enum halmac_ret_status +download_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size); + +enum halmac_ret_status +free_download_firmware_88xx(struct halmac_adapter *adapter, + enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size); + +enum halmac_ret_status +get_fw_version_88xx(struct halmac_adapter *adapter, + struct halmac_fw_version *ver); + +enum halmac_ret_status +check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status); + +enum halmac_ret_status +dump_fw_dmem_88xx(struct halmac_adapter *adapter, u8 *dmem, u32 *size); + +enum halmac_ret_status +cfg_max_dl_size_88xx(struct halmac_adapter *adapter, u32 size); + +enum halmac_ret_status +enter_cpu_sleep_mode_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +get_cpu_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wlcpu_mode *mode); + +enum halmac_ret_status +send_general_info_88xx(struct halmac_adapter *adapter, + struct halmac_general_info *info); + +enum halmac_ret_status +drv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_FW_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_gpio_88xx.c b/hal/halmac/halmac_88xx/halmac_gpio_88xx.c new file mode 100644 index 0000000..cb0ebde --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_gpio_88xx.c @@ -0,0 +1,421 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_gpio_88xx.h" + +#if HALMAC_88XX_SUPPORT + +/** + * pinmux_wl_led_mode_88xx() -control wlan led gpio function + * @adapter : the adapter of halmac + * @mode : wlan led mode + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pinmux_wl_led_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wlled_mode mode) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + value8 = HALMAC_REG_R8(REG_LED_CFG + 2); + value8 &= ~(BIT(6)); + value8 |= BIT(3); + value8 &= ~(BIT(0) | BIT(1) | BIT(2)); + + switch (mode) { + case HALMAC_WLLED_MODE_TRX: + value8 |= 2; + break; + case HALMAC_WLLED_MODE_TX: + value8 |= 4; + break; + case HALMAC_WLLED_MODE_RX: + value8 |= 6; + break; + case HALMAC_WLLED_MODE_SW_CTRL: + value8 |= 0; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + HALMAC_REG_W8(REG_LED_CFG + 2, value8); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * pinmux_wl_led_sw_ctrl_88xx() -control wlan led on/off + * @adapter : the adapter of halmac + * @on : on(1), off(0) + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +void +pinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_LED_CFG + 2); + value8 = (on == 0) ? value8 | BIT(3) : value8 & ~(BIT(3)); + + HALMAC_REG_W8(REG_LED_CFG + 2, value8); +} + +/** + * pinmux_sdio_int_polarity_88xx() -control sdio int polarity + * @adapter : the adapter of halmac + * @low_active : low active(1), high active(0) + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +void +pinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active) +{ + u8 value8; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + value8 = HALMAC_REG_R8(REG_SYS_SDIO_CTRL + 2); + value8 = (low_active == 0) ? value8 | BIT(3) : value8 & ~(BIT(3)); + + HALMAC_REG_W8(REG_SYS_SDIO_CTRL + 2, value8); +} + +/** + * pinmux_gpio_mode_88xx() -control gpio io mode + * @adapter : the adapter of halmac + * @gpio_id : gpio0~15(0~15) + * @output : output(1), input(0) + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output) +{ + u16 value16; + u8 in_out; + u32 offset; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (gpio_id <= 7) + offset = REG_GPIO_PIN_CTRL + 2; + else if (gpio_id >= 8 && gpio_id <= 15) + offset = REG_GPIO_EXT_CTRL + 2; + else + return HALMAC_RET_WRONG_GPIO; + + in_out = (output == 0) ? 0 : 1; + gpio_id &= (8 - 1); + + value16 = HALMAC_REG_R16(offset); + value16 &= ~((1 << gpio_id) | (1 << gpio_id << 8)); + value16 |= (in_out << gpio_id); + HALMAC_REG_W16(offset, value16); + + return HALMAC_RET_SUCCESS; +} + +/** + * pinmux_gpio_output_88xx() -control gpio output high/low + * @adapter : the adapter of halmac + * @gpio_id : gpio0~15(0~15) + * @high : high(1), low(0) + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high) +{ + u8 value8; + u8 hi_low; + u32 offset; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (gpio_id <= 7) + offset = REG_GPIO_PIN_CTRL + 1; + else if (gpio_id >= 8 && gpio_id <= 15) + offset = REG_GPIO_EXT_CTRL + 1; + else + return HALMAC_RET_WRONG_GPIO; + + hi_low = (high == 0) ? 0 : 1; + gpio_id &= (8 - 1); + + value8 = HALMAC_REG_R8(offset); + value8 &= ~(1 << gpio_id); + value8 |= (hi_low << gpio_id); + HALMAC_REG_W8(offset, value8); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pinmux_status_88xx() -get current gpio status(high/low) + * @adapter : the adapter of halmac + * @pin_id : 0~15(0~15) + * @phigh : high(1), low(0) + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high) +{ + u8 value8; + u32 offset; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (pin_id <= 7) + offset = REG_GPIO_PIN_CTRL; + else if (pin_id >= 8 && pin_id <= 15) + offset = REG_GPIO_EXT_CTRL; + else + return HALMAC_RET_WRONG_GPIO; + + pin_id &= (8 - 1); + + value8 = HALMAC_REG_R8(offset); + *high = (value8 & (1 << pin_id)) >> pin_id; + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +pinmux_parser_88xx(struct halmac_adapter *adapter, + const struct halmac_gpio_pimux_list *list, u32 size, + u32 gpio_id, u32 *cur_func) +{ + u32 i; + u8 value8; + const struct halmac_gpio_pimux_list *cur_list = list; + enum halmac_gpio_cfg_state *state; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + state = &adapter->halmac_state.gpio_cfg_state; + + if (*state == HALMAC_GPIO_CFG_STATE_BUSY) + return HALMAC_RET_BUSY_STATE; + + *state = HALMAC_GPIO_CFG_STATE_BUSY; + + for (i = 0; i < size; i++) { + if (gpio_id != cur_list->id) { + PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n", + cur_list->offset, cur_list->value, + cur_list->func); + PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n", + gpio_id, cur_list->id); + *state = HALMAC_GPIO_CFG_STATE_IDLE; + return HALMAC_RET_GET_PINMUX_ERR; + } + value8 = HALMAC_REG_R8(cur_list->offset); + value8 &= cur_list->msk; + if (value8 == cur_list->value) { + *cur_func = cur_list->func; + break; + } + cur_list++; + } + + *state = HALMAC_GPIO_CFG_STATE_IDLE; + + if (i == size) + return HALMAC_RET_GET_PINMUX_ERR; + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +pinmux_switch_88xx(struct halmac_adapter *adapter, + const struct halmac_gpio_pimux_list *list, u32 size, + u32 gpio_id, enum halmac_gpio_func gpio_func) +{ + u32 i; + u8 value8; + u16 switch_func; + const struct halmac_gpio_pimux_list *cur_list = list; + enum halmac_gpio_cfg_state *state; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + state = &adapter->halmac_state.gpio_cfg_state; + + if (*state == HALMAC_GPIO_CFG_STATE_BUSY) + return HALMAC_RET_BUSY_STATE; + + switch (gpio_func) { + case HALMAC_GPIO_FUNC_WL_LED: + switch_func = HALMAC_WL_LED; + break; + case HALMAC_GPIO_FUNC_SDIO_INT: + switch_func = HALMAC_SDIO_INT; + break; + case HALMAC_GPIO_FUNC_BT_HOST_WAKE1: + case HALMAC_GPIO_FUNC_BT_DEV_WAKE1: + switch_func = HALMAC_GPIO13_14_WL_CTRL_EN; + break; + case HALMAC_GPIO_FUNC_SW_IO_0: + case HALMAC_GPIO_FUNC_SW_IO_1: + case HALMAC_GPIO_FUNC_SW_IO_2: + case HALMAC_GPIO_FUNC_SW_IO_3: + case HALMAC_GPIO_FUNC_SW_IO_4: + case HALMAC_GPIO_FUNC_SW_IO_5: + case HALMAC_GPIO_FUNC_SW_IO_6: + case HALMAC_GPIO_FUNC_SW_IO_7: + case HALMAC_GPIO_FUNC_SW_IO_8: + case HALMAC_GPIO_FUNC_SW_IO_9: + case HALMAC_GPIO_FUNC_SW_IO_10: + case HALMAC_GPIO_FUNC_SW_IO_11: + case HALMAC_GPIO_FUNC_SW_IO_12: + case HALMAC_GPIO_FUNC_SW_IO_13: + case HALMAC_GPIO_FUNC_SW_IO_14: + case HALMAC_GPIO_FUNC_SW_IO_15: + switch_func = HALMAC_SW_IO; + break; + default: + return HALMAC_RET_SWITCH_CASE_ERROR; + } + + for (i = 0; i < size; i++) { + if (gpio_id != cur_list->id) { + PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n", + cur_list->offset, cur_list->value, + cur_list->func); + PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n", + gpio_id, cur_list->id); + return HALMAC_RET_GET_PINMUX_ERR; + } + + if (switch_func == cur_list->func) + break; + + cur_list++; + } + + if (i == size) { + PLTFM_MSG_ERR("[ERR]gpio func error:%X %X\n", + gpio_id, cur_list->id); + return HALMAC_RET_GET_PINMUX_ERR; + } + + *state = HALMAC_GPIO_CFG_STATE_BUSY; + + cur_list = list; + for (i = 0; i < size; i++) { + value8 = HALMAC_REG_R8(cur_list->offset); + value8 &= ~(cur_list->msk); + + if (switch_func == cur_list->func) { + value8 |= (cur_list->value & cur_list->msk); + HALMAC_REG_W8(cur_list->offset, value8); + break; + } + + value8 |= (~cur_list->value & cur_list->msk); + HALMAC_REG_W8(cur_list->offset, value8); + + cur_list++; + } + + *state = HALMAC_GPIO_CFG_STATE_IDLE; + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +pinmux_record_88xx(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, u8 val) +{ + switch (gpio_func) { + case HALMAC_GPIO_FUNC_WL_LED: + adapter->pinmux_info.wl_led = val; + break; + case HALMAC_GPIO_FUNC_SDIO_INT: + adapter->pinmux_info.sdio_int = val; + break; + case HALMAC_GPIO_FUNC_BT_HOST_WAKE1: + adapter->pinmux_info.bt_host_wake = val; + break; + case HALMAC_GPIO_FUNC_BT_DEV_WAKE1: + adapter->pinmux_info.bt_dev_wake = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_0: + adapter->pinmux_info.sw_io_0 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_1: + adapter->pinmux_info.sw_io_1 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_2: + adapter->pinmux_info.sw_io_2 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_3: + adapter->pinmux_info.sw_io_3 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_4: + adapter->pinmux_info.sw_io_4 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_5: + adapter->pinmux_info.sw_io_5 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_6: + adapter->pinmux_info.sw_io_6 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_7: + adapter->pinmux_info.sw_io_7 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_8: + adapter->pinmux_info.sw_io_8 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_9: + adapter->pinmux_info.sw_io_9 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_10: + adapter->pinmux_info.sw_io_10 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_11: + adapter->pinmux_info.sw_io_11 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_12: + adapter->pinmux_info.sw_io_12 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_13: + adapter->pinmux_info.sw_io_13 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_14: + adapter->pinmux_info.sw_io_14 = val; + break; + case HALMAC_GPIO_FUNC_SW_IO_15: + adapter->pinmux_info.sw_io_15 = val; + break; + default: + return HALMAC_RET_GET_PINMUX_ERR; + } + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_88XX_SUPPORT */ + diff --git a/hal/halmac/halmac_88xx/halmac_gpio_88xx.h b/hal/halmac/halmac_88xx/halmac_gpio_88xx.h new file mode 100644 index 0000000..63ffac4 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_gpio_88xx.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_GPIO_88XX_H_ +#define _HALMAC_GPIO_88XX_H_ + +#include "../halmac_api.h" +#include "../halmac_gpio_cmd.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +pinmux_wl_led_mode_88xx(struct halmac_adapter *adapter, + enum halmac_wlled_mode mode); + +void +pinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on); + +void +pinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active); + +enum halmac_ret_status +pinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output); + +enum halmac_ret_status +pinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high); + +enum halmac_ret_status +pinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high); + +enum halmac_ret_status +pinmux_parser_88xx(struct halmac_adapter *adapter, + const struct halmac_gpio_pimux_list *list, u32 size, + u32 gpio_id, u32 *cur_func); + +enum halmac_ret_status +pinmux_switch_88xx(struct halmac_adapter *adapter, + const struct halmac_gpio_pimux_list *list, u32 size, + u32 gpio_id, enum halmac_gpio_func gpio_func); + +enum halmac_ret_status +pinmux_record_88xx(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, u8 val); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_GPIO_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_init_88xx.c b/hal/halmac/halmac_88xx/halmac_init_88xx.c new file mode 100644 index 0000000..e85b4d8 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_init_88xx.c @@ -0,0 +1,992 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_init_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_fw_88xx.h" +#include "halmac_common_88xx.h" +#include "halmac_cfg_wmac_88xx.h" +#include "halmac_efuse_88xx.h" +#include "halmac_mimo_88xx.h" +#include "halmac_bb_rf_88xx.h" +#if HALMAC_SDIO_SUPPORT +#include "halmac_sdio_88xx.h" +#endif +#if HALMAC_USB_SUPPORT +#include "halmac_usb_88xx.h" +#endif +#if HALMAC_PCIE_SUPPORT +#include "halmac_pcie_88xx.h" +#endif +#include "halmac_gpio_88xx.h" +#include "halmac_flash_88xx.h" + +#if HALMAC_8822B_SUPPORT +#include "halmac_8822b/halmac_init_8822b.h" +#endif + +#if HALMAC_8821C_SUPPORT +#include "halmac_8821c/halmac_init_8821c.h" +#endif + +#if HALMAC_8822C_SUPPORT +#include "halmac_8822c/halmac_init_8822c.h" +#endif + +#if HALMAC_8812F_SUPPORT +#include "halmac_8812f/halmac_init_8812f.h" +#endif + +#if HALMAC_PLATFORM_TESTPROGRAM +#include "halmisc_api_88xx.h" +#endif + +#if HALMAC_88XX_SUPPORT + +#define PLTFM_INFO_MALLOC_MAX_SIZE 16384 +#define PLTFM_INFO_RSVD_PG_SIZE 16384 +#define DLFW_PKT_MAX_SIZE 8192 /* need multiple of 2 */ + +#define SYS_FUNC_EN 0xD8 + +static void +init_state_machine_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +verify_io_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +verify_send_rsvd_page_88xx(struct halmac_adapter *adapter); + +void +init_adapter_param_88xx(struct halmac_adapter *adapter) +{ + adapter->api_registry.rx_exp_en = 1; + adapter->api_registry.la_mode_en = 1; + adapter->api_registry.cfg_drv_rsvd_pg_en = 1; + adapter->api_registry.sdio_cmd53_4byte_en = 1; + + adapter->efuse_map = (u8 *)NULL; + adapter->efuse_map_valid = 0; + adapter->efuse_end = 0; + + adapter->dlfw_pkt_size = DLFW_PKT_MAX_SIZE; + adapter->pltfm_info.malloc_size = PLTFM_INFO_MALLOC_MAX_SIZE; + adapter->pltfm_info.rsvd_pg_size = PLTFM_INFO_RSVD_PG_SIZE; + + adapter->cfg_param_info.buf = NULL; + adapter->cfg_param_info.buf_wptr = NULL; + adapter->cfg_param_info.num = 0; + adapter->cfg_param_info.full_fifo_mode = 0; + adapter->cfg_param_info.buf_size = 0; + adapter->cfg_param_info.avl_buf_size = 0; + adapter->cfg_param_info.offset_accum = 0; + adapter->cfg_param_info.value_accum = 0; + + adapter->ch_sw_info.buf = NULL; + adapter->ch_sw_info.buf_wptr = NULL; + adapter->ch_sw_info.extra_info_en = 0; + adapter->ch_sw_info.buf_size = 0; + adapter->ch_sw_info.avl_buf_size = 0; + adapter->ch_sw_info.total_size = 0; + adapter->ch_sw_info.ch_num = 0; + + adapter->drv_info_size = 0; + adapter->tx_desc_transfer = 0; + + adapter->txff_alloc.tx_fifo_pg_num = 0; + adapter->txff_alloc.acq_pg_num = 0; + adapter->txff_alloc.rsvd_boundary = 0; + adapter->txff_alloc.rsvd_drv_addr = 0; + adapter->txff_alloc.rsvd_h2c_info_addr = 0; + adapter->txff_alloc.rsvd_h2cq_addr = 0; + adapter->txff_alloc.rsvd_cpu_instr_addr = 0; + adapter->txff_alloc.rsvd_fw_txbuf_addr = 0; + adapter->txff_alloc.pub_queue_pg_num = 0; + adapter->txff_alloc.high_queue_pg_num = 0; + adapter->txff_alloc.low_queue_pg_num = 0; + adapter->txff_alloc.normal_queue_pg_num = 0; + adapter->txff_alloc.extra_queue_pg_num = 0; + + adapter->txff_alloc.la_mode = HALMAC_LA_MODE_DISABLE; + adapter->txff_alloc.rx_fifo_exp_mode = + HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE; + + adapter->hw_cfg_info.chk_security_keyid = 0; + adapter->hw_cfg_info.acq_num = 8; + adapter->hw_cfg_info.page_size = TX_PAGE_SIZE_88XX; + adapter->hw_cfg_info.tx_align_size = TX_ALIGN_SIZE_88XX; + adapter->hw_cfg_info.txdesc_size = TX_DESC_SIZE_88XX; + adapter->hw_cfg_info.rxdesc_size = RX_DESC_SIZE_88XX; + adapter->hw_cfg_info.rx_desc_fifo_size = 0; + + adapter->sdio_cmd53_4byte = HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE; + adapter->sdio_hw_info.io_hi_speed_flag = 0; + adapter->sdio_hw_info.io_indir_flag = 0; + adapter->sdio_hw_info.spec_ver = HALMAC_SDIO_SPEC_VER_2_00; + adapter->sdio_hw_info.clock_speed = 50; + adapter->sdio_hw_info.block_size = 512; + adapter->sdio_hw_info.tx_seq = 1; + adapter->sdio_fs.macid_map = (u8 *)NULL; + + adapter->pinmux_info.wl_led = 0; + adapter->pinmux_info.sdio_int = 0; + adapter->pinmux_info.sw_io_0 = 0; + adapter->pinmux_info.sw_io_1 = 0; + adapter->pinmux_info.sw_io_2 = 0; + adapter->pinmux_info.sw_io_3 = 0; + adapter->pinmux_info.sw_io_4 = 0; + adapter->pinmux_info.sw_io_5 = 0; + adapter->pinmux_info.sw_io_6 = 0; + adapter->pinmux_info.sw_io_7 = 0; + adapter->pinmux_info.sw_io_8 = 0; + adapter->pinmux_info.sw_io_9 = 0; + adapter->pinmux_info.sw_io_10 = 0; + adapter->pinmux_info.sw_io_11 = 0; + adapter->pinmux_info.sw_io_12 = 0; + adapter->pinmux_info.sw_io_13 = 0; + adapter->pinmux_info.sw_io_14 = 0; + adapter->pinmux_info.sw_io_15 = 0; + + adapter->pcie_refautok_en = 1; + adapter->pwr_off_flow_flag = 0; + + adapter->rx_ignore_info.hdr_chk_mask = 1; + adapter->rx_ignore_info.fcs_chk_mask = 1; + adapter->rx_ignore_info.hdr_chk_en = 0; + adapter->rx_ignore_info.fcs_chk_en = 0; + adapter->rx_ignore_info.cck_rst_en = 0; + adapter->rx_ignore_info.fcs_chk_thr = HALMAC_PSF_FCS_CHK_THR_28; + + init_adapter_dynamic_param_88xx(adapter); + init_state_machine_88xx(adapter); +} + +void +init_adapter_dynamic_param_88xx(struct halmac_adapter *adapter) +{ + adapter->h2c_info.seq_num = 0; + adapter->h2c_info.buf_fs = 0; +} + +enum halmac_ret_status +mount_api_88xx(struct halmac_adapter *adapter) +{ + struct halmac_api *api = NULL; + + adapter->halmac_api = + (struct halmac_api *)PLTFM_MALLOC(sizeof(struct halmac_api)); + if (!adapter->halmac_api) + return HALMAC_RET_MALLOC_FAIL; + + api = (struct halmac_api *)adapter->halmac_api; + + api->halmac_read_efuse = NULL; + api->halmac_write_efuse = NULL; + + /* Mount function pointer */ + api->halmac_register_api = register_api_88xx; + api->halmac_download_firmware = download_firmware_88xx; + api->halmac_free_download_firmware = free_download_firmware_88xx; + api->halmac_get_fw_version = get_fw_version_88xx; + api->halmac_cfg_mac_addr = cfg_mac_addr_88xx; + api->halmac_cfg_bssid = cfg_bssid_88xx; + api->halmac_cfg_transmitter_addr = cfg_transmitter_addr_88xx; + api->halmac_cfg_net_type = cfg_net_type_88xx; + api->halmac_cfg_tsf_rst = cfg_tsf_rst_88xx; + api->halmac_cfg_bcn_space = cfg_bcn_space_88xx; + api->halmac_rw_bcn_ctrl = rw_bcn_ctrl_88xx; + api->halmac_cfg_multicast_addr = cfg_multicast_addr_88xx; + api->halmac_pre_init_system_cfg = pre_init_system_cfg_88xx; + api->halmac_init_system_cfg = init_system_cfg_88xx; + api->halmac_cfg_operation_mode = cfg_operation_mode_88xx; + api->halmac_cfg_ch_bw = cfg_ch_bw_88xx; + api->halmac_cfg_bw = cfg_bw_88xx; + api->halmac_init_mac_cfg = init_mac_cfg_88xx; + api->halmac_dump_efuse_map = dump_efuse_map_88xx; + api->halmac_dump_efuse_map_bt = dump_efuse_map_bt_88xx; + api->halmac_write_efuse_bt = write_efuse_bt_88xx; + api->halmac_read_efuse_bt = read_efuse_bt_88xx; + api->halmac_cfg_efuse_auto_check = cfg_efuse_auto_check_88xx; + api->halmac_dump_logical_efuse_map = dump_log_efuse_map_88xx; + api->halmac_pg_efuse_by_map = pg_efuse_by_map_88xx; + api->halmac_mask_logical_efuse = mask_log_efuse_88xx; + api->halmac_get_efuse_size = get_efuse_size_88xx; + api->halmac_get_efuse_available_size = get_efuse_available_size_88xx; + api->halmac_get_c2h_info = get_c2h_info_88xx; + + api->halmac_get_logical_efuse_size = get_log_efuse_size_88xx; + + api->halmac_write_logical_efuse = write_log_efuse_88xx; + api->halmac_read_logical_efuse = read_logical_efuse_88xx; + + api->halmac_ofld_func_cfg = ofld_func_cfg_88xx; + api->halmac_h2c_lb = h2c_lb_88xx; + api->halmac_debug = mac_debug_88xx; + api->halmac_cfg_parameter = cfg_parameter_88xx; + api->halmac_update_datapack = update_datapack_88xx; + api->halmac_run_datapack = run_datapack_88xx; + api->halmac_send_bt_coex = send_bt_coex_88xx; + api->halmac_verify_platform_api = verify_platform_api_88xx; + api->halmac_update_packet = update_packet_88xx; + api->halmac_bcn_ie_filter = bcn_ie_filter_88xx; + api->halmac_cfg_txbf = cfg_txbf_88xx; + api->halmac_cfg_mumimo = cfg_mumimo_88xx; + api->halmac_cfg_sounding = cfg_sounding_88xx; + api->halmac_del_sounding = del_sounding_88xx; + api->halmac_su_bfer_entry_init = su_bfer_entry_init_88xx; + api->halmac_su_bfee_entry_init = su_bfee_entry_init_88xx; + api->halmac_mu_bfer_entry_init = mu_bfer_entry_init_88xx; + api->halmac_mu_bfee_entry_init = mu_bfee_entry_init_88xx; + api->halmac_su_bfer_entry_del = su_bfer_entry_del_88xx; + api->halmac_su_bfee_entry_del = su_bfee_entry_del_88xx; + api->halmac_mu_bfer_entry_del = mu_bfer_entry_del_88xx; + api->halmac_mu_bfee_entry_del = mu_bfee_entry_del_88xx; + + api->halmac_add_ch_info = add_ch_info_88xx; + api->halmac_add_extra_ch_info = add_extra_ch_info_88xx; + api->halmac_ctrl_ch_switch = ctrl_ch_switch_88xx; + api->halmac_p2pps = p2pps_88xx; + api->halmac_clear_ch_info = clear_ch_info_88xx; + api->halmac_send_general_info = send_general_info_88xx; + + api->halmac_start_iqk = start_iqk_88xx; + api->halmac_ctrl_pwr_tracking = ctrl_pwr_tracking_88xx; + api->halmac_psd = psd_88xx; + api->halmac_cfg_la_mode = cfg_la_mode_88xx; + api->halmac_cfg_rxff_expand_mode = cfg_rxfifo_expand_mode_88xx; + + api->halmac_config_security = config_security_88xx; + api->halmac_get_used_cam_entry_num = get_used_cam_entry_num_88xx; + api->halmac_read_cam_entry = read_cam_entry_88xx; + api->halmac_write_cam = write_cam_88xx; + api->halmac_clear_cam_entry = clear_cam_entry_88xx; + + api->halmac_cfg_drv_rsvd_pg_num = cfg_drv_rsvd_pg_num_88xx; + api->halmac_get_chip_version = get_version_88xx; + + api->halmac_query_status = query_status_88xx; + api->halmac_reset_feature = reset_ofld_feature_88xx; + api->halmac_check_fw_status = check_fw_status_88xx; + api->halmac_dump_fw_dmem = dump_fw_dmem_88xx; + api->halmac_cfg_max_dl_size = cfg_max_dl_size_88xx; + + api->halmac_dump_fifo = dump_fifo_88xx; + api->halmac_get_fifo_size = get_fifo_size_88xx; + + api->halmac_chk_txdesc = chk_txdesc_88xx; + api->halmac_dl_drv_rsvd_page = dl_drv_rsvd_page_88xx; + api->halmac_cfg_csi_rate = cfg_csi_rate_88xx; + + api->halmac_txfifo_is_empty = txfifo_is_empty_88xx; + api->halmac_download_flash = download_flash_88xx; + api->halmac_read_flash = read_flash_88xx; + api->halmac_erase_flash = erase_flash_88xx; + api->halmac_check_flash = check_flash_88xx; + api->halmac_cfg_edca_para = cfg_edca_para_88xx; + api->halmac_pinmux_wl_led_mode = pinmux_wl_led_mode_88xx; + api->halmac_pinmux_wl_led_sw_ctrl = pinmux_wl_led_sw_ctrl_88xx; + api->halmac_pinmux_sdio_int_polarity = pinmux_sdio_int_polarity_88xx; + api->halmac_pinmux_gpio_mode = pinmux_gpio_mode_88xx; + api->halmac_pinmux_gpio_output = pinmux_gpio_output_88xx; + api->halmac_pinmux_pin_status = pinmux_pin_status_88xx; + + api->halmac_rx_cut_amsdu_cfg = rx_cut_amsdu_cfg_88xx; + api->halmac_fw_snding = fw_snding_88xx; + api->halmac_get_mac_addr = get_mac_addr_88xx; + + api->halmac_enter_cpu_sleep_mode = enter_cpu_sleep_mode_88xx; + api->halmac_get_cpu_mode = get_cpu_mode_88xx; + api->halmac_drv_fwctrl = drv_fwctrl_88xx; + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { +#if HALMAC_SDIO_SUPPORT + api->halmac_init_sdio_cfg = init_sdio_cfg_88xx; + api->halmac_deinit_sdio_cfg = deinit_sdio_cfg_88xx; + api->halmac_cfg_rx_aggregation = cfg_sdio_rx_agg_88xx; + api->halmac_init_interface_cfg = init_sdio_cfg_88xx; + api->halmac_deinit_interface_cfg = deinit_sdio_cfg_88xx; + api->halmac_cfg_tx_agg_align = cfg_txagg_sdio_align_88xx; + api->halmac_set_bulkout_num = set_sdio_bulkout_num_88xx; + api->halmac_get_usb_bulkout_id = get_sdio_bulkout_id_88xx; + api->halmac_reg_read_indirect_32 = sdio_indirect_reg_r32_88xx; + api->halmac_reg_sdio_cmd53_read_n = sdio_reg_rn_88xx; + api->halmac_sdio_cmd53_4byte = sdio_cmd53_4byte_88xx; + api->halmac_sdio_hw_info = sdio_hw_info_88xx; + +#endif + } else if (adapter->intf == HALMAC_INTERFACE_USB) { +#if HALMAC_USB_SUPPORT + api->halmac_init_usb_cfg = init_usb_cfg_88xx; + api->halmac_deinit_usb_cfg = deinit_usb_cfg_88xx; + api->halmac_cfg_rx_aggregation = cfg_usb_rx_agg_88xx; + api->halmac_init_interface_cfg = init_usb_cfg_88xx; + api->halmac_deinit_interface_cfg = deinit_usb_cfg_88xx; + api->halmac_cfg_tx_agg_align = cfg_txagg_usb_align_88xx; + api->halmac_tx_allowed_sdio = tx_allowed_usb_88xx; + api->halmac_set_bulkout_num = set_usb_bulkout_num_88xx; + api->halmac_get_sdio_tx_addr = get_usb_tx_addr_88xx; + api->halmac_get_usb_bulkout_id = get_usb_bulkout_id_88xx; + api->halmac_reg_read_8 = reg_r8_usb_88xx; + api->halmac_reg_write_8 = reg_w8_usb_88xx; + api->halmac_reg_read_16 = reg_r16_usb_88xx; + api->halmac_reg_write_16 = reg_w16_usb_88xx; + api->halmac_reg_read_32 = reg_r32_usb_88xx; + api->halmac_reg_write_32 = reg_w32_usb_88xx; + api->halmac_reg_read_indirect_32 = usb_indirect_reg_r32_88xx; + api->halmac_reg_sdio_cmd53_read_n = usb_reg_rn_88xx; +#endif + } else if (adapter->intf == HALMAC_INTERFACE_PCIE) { +#if HALMAC_PCIE_SUPPORT + api->halmac_init_pcie_cfg = init_pcie_cfg_88xx; + api->halmac_deinit_pcie_cfg = deinit_pcie_cfg_88xx; + api->halmac_cfg_rx_aggregation = cfg_pcie_rx_agg_88xx; + api->halmac_init_interface_cfg = init_pcie_cfg_88xx; + api->halmac_deinit_interface_cfg = deinit_pcie_cfg_88xx; + api->halmac_cfg_tx_agg_align = cfg_txagg_pcie_align_88xx; + api->halmac_tx_allowed_sdio = tx_allowed_pcie_88xx; + api->halmac_set_bulkout_num = set_pcie_bulkout_num_88xx; + api->halmac_get_sdio_tx_addr = get_pcie_tx_addr_88xx; + api->halmac_get_usb_bulkout_id = get_pcie_bulkout_id_88xx; + api->halmac_reg_read_8 = reg_r8_pcie_88xx; + api->halmac_reg_write_8 = reg_w8_pcie_88xx; + api->halmac_reg_read_16 = reg_r16_pcie_88xx; + api->halmac_reg_write_16 = reg_w16_pcie_88xx; + api->halmac_reg_read_32 = reg_r32_pcie_88xx; + api->halmac_reg_write_32 = reg_w32_pcie_88xx; + api->halmac_reg_read_indirect_32 = pcie_indirect_reg_r32_88xx; + api->halmac_reg_sdio_cmd53_read_n = pcie_reg_rn_88xx; + api->halmac_en_ref_autok_pcie = en_ref_autok_88xx; +#endif + } else { + PLTFM_MSG_ERR("[ERR]Set halmac io function Error!!\n"); + } + + if (adapter->chip_id == HALMAC_CHIP_ID_8822B) { +#if HALMAC_8822B_SUPPORT + mount_api_8822b(adapter); +#endif + } else if (adapter->chip_id == HALMAC_CHIP_ID_8821C) { +#if HALMAC_8821C_SUPPORT + mount_api_8821c(adapter); +#endif + } else if (adapter->chip_id == HALMAC_CHIP_ID_8822C) { +#if HALMAC_8822C_SUPPORT + mount_api_8822c(adapter); +#endif + } else if (adapter->chip_id == HALMAC_CHIP_ID_8812F) { +#if HALMAC_8812F_SUPPORT + mount_api_8812f(adapter); +#endif + } else { + PLTFM_MSG_ERR("[ERR]Chip ID undefine!!\n"); + return HALMAC_RET_CHIP_NOT_SUPPORT; + } + +#if HALMAC_PLATFORM_TESTPROGRAM + halmac_mount_misc_api_88xx(adapter); +#endif + + return HALMAC_RET_SUCCESS; +} + +static void +init_state_machine_88xx(struct halmac_adapter *adapter) +{ + struct halmac_state *state = &adapter->halmac_state; + + init_ofld_feature_state_machine_88xx(adapter); + + state->api_state = HALMAC_API_STATE_INIT; + + state->dlfw_state = HALMAC_DLFW_NONE; + state->mac_pwr = HALMAC_MAC_POWER_OFF; + state->gpio_cfg_state = HALMAC_GPIO_CFG_STATE_IDLE; + state->rsvd_pg_state = HALMAC_RSVD_PG_STATE_IDLE; +} + +void +init_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter) +{ + struct halmac_state *state = &adapter->halmac_state; + + state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->efuse_state.seq_num = adapter->h2c_info.seq_num; + + state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->cfg_param_state.seq_num = adapter->h2c_info.seq_num; + + state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->scan_state.seq_num = adapter->h2c_info.seq_num; + + state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->update_pkt_state.seq_num = adapter->h2c_info.seq_num; + + state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->iqk_state.seq_num = adapter->h2c_info.seq_num; + + state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->pwr_trk_state.seq_num = adapter->h2c_info.seq_num; + + state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->psd_state.seq_num = adapter->h2c_info.seq_num; + state->psd_state.data_size = 0; + state->psd_state.seg_size = 0; + state->psd_state.data = NULL; + + state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->fw_snding_state.seq_num = adapter->h2c_info.seq_num; + + state->wlcpu_mode = HALMAC_WLCPU_ACTIVE; +} + +/** + * register_api_88xx() - register feature list + * @adapter + * @registry : feature list, 1->enable 0->disable + * Author : Ivan Lin + * + * Default is enable all api registry + * + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +register_api_88xx(struct halmac_adapter *adapter, + struct halmac_api_registry *registry) +{ + if (!registry) + return HALMAC_RET_NULL_POINTER; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + PLTFM_MEMCPY(&adapter->api_registry, registry, sizeof(*registry)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * pre_init_system_cfg_88xx() - pre-init system config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pre_init_system_cfg_88xx(struct halmac_adapter *adapter) +{ + u32 value32; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 enable_bb; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + HALMAC_REG_W8(REG_RSV_CTRL, 0); + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { +#if HALMAC_SDIO_SUPPORT + if (leave_sdio_suspend_88xx(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL; +#endif + } else if (adapter->intf == HALMAC_INTERFACE_USB) { +#if HALMAC_USB_SUPPORT + if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) + HALMAC_REG_W8(0xFE5B, HALMAC_REG_R8(0xFE5B) | BIT(4)); +#endif + } else if (adapter->intf == HALMAC_INTERFACE_PCIE) { +#if HALMAC_PCIE_SUPPORT + /* For PCIE power on fail issue */ + HALMAC_REG_W8(REG_HCI_OPT_CTRL + 1, + HALMAC_REG_R8(REG_HCI_OPT_CTRL + 1) | BIT(0)); +#endif + } + + /* Config PIN Mux */ + value32 = HALMAC_REG_R32(REG_PAD_CTRL1); + value32 = value32 & (~(BIT(28) | BIT(29))); + value32 = value32 | BIT(28) | BIT(29); + HALMAC_REG_W32(REG_PAD_CTRL1, value32); + + value32 = HALMAC_REG_R32(REG_LED_CFG); + value32 = value32 & (~(BIT(25) | BIT(26))); + HALMAC_REG_W32(REG_LED_CFG, value32); + + value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG); + value32 = value32 & (~(BIT(2))); + value32 = value32 | BIT(2); + HALMAC_REG_W32(REG_GPIO_MUXCFG, value32); + + enable_bb = 0; + set_hw_value_88xx(adapter, HALMAC_HW_EN_BB_RF, &enable_bb); + + if (HALMAC_REG_R8(REG_SYS_CFG1 + 2) & BIT(4)) { + PLTFM_MSG_ERR("[ERR]test mode!!\n"); + return HALMAC_RET_WLAN_MODE_FAIL; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_system_cfg_88xx() - init system config + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_system_cfg_88xx(struct halmac_adapter *adapter) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u32 tmp = 0; + u32 value32; + enum halmac_ret_status status; + u8 hwval; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + if (adapter->intf == HALMAC_INTERFACE_PCIE) { + hwval = 1; + status = api->halmac_set_hw_value(adapter, + HALMAC_HW_PCIE_REF_AUTOK, + &hwval); + if (status != HALMAC_RET_SUCCESS) + return status; + } + + value32 = HALMAC_REG_R32(REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST; +#if HALMAC_8822C_SUPPORT + if (adapter->chip_id != HALMAC_CHIP_ID_8822B && + adapter->chip_id != HALMAC_CHIP_ID_8821C) + value32 |= BIT_DDMA_EN; +#endif + HALMAC_REG_W32(REG_CPU_DMEM_CON, value32); + + HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, SYS_FUNC_EN); +#if HALMAC_8822B_SUPPORT + /* cpu_en is related to wlan tx in 8822B hw design */ + /* 8822B should enable cpu_en in init flow */ + if (adapter->chip_id == HALMAC_CHIP_ID_8822B) + HALMAC_REG_W8_SET(REG_SYS_FUNC_EN + 1, BIT(2)); +#endif + /*disable boot-from-flash for driver's DL FW*/ + tmp = HALMAC_REG_R32(REG_MCUFW_CTRL); + if (tmp & BIT_BOOT_FSPI_EN) { + HALMAC_REG_W32(REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN)); + value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG) & (~BIT_FSPI_EN); + HALMAC_REG_W32(REG_GPIO_MUXCFG, value32); + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * init_mac_cfg_88xx() - config page1~page7 register + * @adapter : the adapter of halmac + * @mode : trx mode + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + status = api->halmac_init_trx_cfg(adapter, mode); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]init trx %x\n", status); + return status; + } + + status = api->halmac_init_protocol_cfg(adapter); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]init ptcl %x\n", status); + return status; + } + + status = api->halmac_init_edca_cfg(adapter); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]init edca %x\n", status); + return status; + } + + status = api->halmac_init_wmac_cfg(adapter); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]init wmac %x\n", status); + return status; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return status; +} + +/** + * reset_ofld_feature_88xx() -reset async api cmd status + * @adapter : the adapter of halmac + * @feature_id : feature_id + * Author : Ivan Lin/KaiYuan Chang + * Return : enum halmac_ret_status. + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reset_ofld_feature_88xx(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id) +{ + struct halmac_state *state = &adapter->halmac_state; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + switch (feature_id) { + case HALMAC_FEATURE_CFG_PARA: + state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + break; + case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: + case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE: + state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + break; + case HALMAC_FEATURE_CHANNEL_SWITCH: + state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + break; + case HALMAC_FEATURE_UPDATE_PACKET: + state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + break; + case HALMAC_FEATURE_IQK: + state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + break; + case HALMAC_FEATURE_POWER_TRACKING: + state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + break; + case HALMAC_FEATURE_PSD: + state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + break; + case HALMAC_FEATURE_FW_SNDING: + state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + break; + case HALMAC_FEATURE_ALL: + state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE; + state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE; + break; + default: + PLTFM_MSG_ERR("[ERR]invalid feature id\n"); + return HALMAC_RET_INVALID_FEATURE_ID; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * (debug API)verify_platform_api_88xx() - verify platform api + * @adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +verify_platform_api_88xx(struct halmac_adapter *adapter) +{ + enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + ret_status = verify_io_88xx(adapter); + + if (ret_status != HALMAC_RET_SUCCESS) + return ret_status; + + if (adapter->txff_alloc.la_mode != HALMAC_LA_MODE_FULL) + ret_status = verify_send_rsvd_page_88xx(adapter); + + if (ret_status != HALMAC_RET_SUCCESS) + return ret_status; + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return ret_status; +} + +void +tx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable) +{ + u16 value16; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + + adapter->tx_desc_checksum = enable; + + value16 = HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK); + if (enable == 1) + HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 | BIT(13)); + else + HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 & ~BIT(13)); +} + +static enum halmac_ret_status +verify_io_88xx(struct halmac_adapter *adapter) +{ + u8 value8; + u8 wvalue8; + u32 value32; + u32 value32_2; + u32 wvalue32; + u32 offset; + enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS; + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + offset = REG_PAGE5_DUMMY; + if (0 == (offset & 0xFFFF0000)) + offset |= WLAN_IOREG_OFFSET; +#if HALMAC_SDIO_SUPPORT + ret_status = cnv_to_sdio_bus_offset_88xx(adapter, &offset); +#else + return HALMAC_RET_WRONG_INTF; +#endif + /* Verify CMD52 R/W */ + wvalue8 = 0xab; + PLTFM_SDIO_CMD52_W(offset, wvalue8); + + value8 = PLTFM_SDIO_CMD52_R(offset); + + if (value8 != wvalue8) { + PLTFM_MSG_ERR("[ERR]cmd52 r/w\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + + /* Verify CMD53 R/W */ + PLTFM_SDIO_CMD52_W(offset, 0xaa); + PLTFM_SDIO_CMD52_W(offset + 1, 0xbb); + PLTFM_SDIO_CMD52_W(offset + 2, 0xcc); + PLTFM_SDIO_CMD52_W(offset + 3, 0xdd); + + value32 = PLTFM_SDIO_CMD53_R32(offset); + + if (value32 != 0xddccbbaa) { + PLTFM_MSG_ERR("[ERR]cmd53 r\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + + wvalue32 = 0x11223344; + PLTFM_SDIO_CMD53_W32(offset, wvalue32); + + value32 = PLTFM_SDIO_CMD53_R32(offset); + + if (value32 != wvalue32) { + PLTFM_MSG_ERR("[ERR]cmd53 w\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + + /* value32 should be 0x33441122 */ + value32 = PLTFM_SDIO_CMD53_R32(offset + 2); + + wvalue32 = 0x11225566; + PLTFM_SDIO_CMD53_W32(offset, wvalue32); + + /* value32 should be 0x55661122 */ + value32_2 = PLTFM_SDIO_CMD53_R32(offset + 2); + if (value32_2 == value32) { + PLTFM_MSG_ERR("[ERR]cmd52 is used\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + } else { + wvalue32 = 0x77665511; + PLTFM_REG_W32(REG_PAGE5_DUMMY, wvalue32); + + value32 = PLTFM_REG_R32(REG_PAGE5_DUMMY); + if (value32 != wvalue32) { + PLTFM_MSG_ERR("[ERR]reg rw\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + } + + return ret_status; +} + +static enum halmac_ret_status +verify_send_rsvd_page_88xx(struct halmac_adapter *adapter) +{ + u8 txdesc_size = adapter->hw_cfg_info.txdesc_size; + u8 *rsvd_buf = NULL; + u8 *rsvd_page = NULL; + u32 i; + u32 pkt_size = 64; + u32 payload = 0xab; + enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS; + + rsvd_buf = (u8 *)PLTFM_MALLOC(pkt_size); + + if (!rsvd_buf) { + PLTFM_MSG_ERR("[ERR]rsvd buf malloc!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + + PLTFM_MEMSET(rsvd_buf, (u8)payload, pkt_size); + + ret_status = dl_rsvd_page_88xx(adapter, + adapter->txff_alloc.rsvd_boundary, + rsvd_buf, pkt_size); + if (ret_status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(rsvd_buf, pkt_size); + return ret_status; + } + + rsvd_page = (u8 *)PLTFM_MALLOC(pkt_size + txdesc_size); + + if (!rsvd_page) { + PLTFM_MSG_ERR("[ERR]rsvd page malloc!!\n"); + PLTFM_FREE(rsvd_buf, pkt_size); + return HALMAC_RET_MALLOC_FAIL; + } + + PLTFM_MEMSET(rsvd_page, 0x00, pkt_size + txdesc_size); + + ret_status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_RSVD_PAGE, 0, + pkt_size + txdesc_size, rsvd_page); + + if (ret_status != HALMAC_RET_SUCCESS) { + PLTFM_FREE(rsvd_buf, pkt_size); + PLTFM_FREE(rsvd_page, pkt_size + txdesc_size); + return ret_status; + } + + for (i = 0; i < pkt_size; i++) { + if (*(rsvd_buf + i) != *(rsvd_page + (i + txdesc_size))) { + PLTFM_MSG_ERR("[ERR]Compare RSVD page Fail\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + } + + PLTFM_FREE(rsvd_buf, pkt_size); + PLTFM_FREE(rsvd_page, pkt_size + txdesc_size); + + return ret_status; +} + +enum halmac_ret_status +pg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode, + struct halmac_pg_num *tbl) +{ + u8 flag; + u16 hpq_num = 0; + u16 lpq_num = 0; + u16 npq_num = 0; + u16 gapq_num = 0; + u16 expq_num = 0; + u16 pubq_num = 0; + u32 i = 0; + + flag = 0; + for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) { + if (mode == tbl[i].mode) { + hpq_num = tbl[i].hq_num; + lpq_num = tbl[i].lq_num; + npq_num = tbl[i].nq_num; + expq_num = tbl[i].exq_num; + gapq_num = tbl[i].gap_num; + pubq_num = adapter->txff_alloc.acq_pg_num - hpq_num - + lpq_num - npq_num - expq_num - gapq_num; + flag = 1; + PLTFM_MSG_TRACE("[TRACE]%s done\n", __func__); + break; + } + } + + if (flag == 0) { + PLTFM_MSG_ERR("[ERR]trx mode!!\n"); + return HALMAC_RET_TRX_MODE_NOT_SUPPORT; + } + + if (adapter->txff_alloc.acq_pg_num < + hpq_num + lpq_num + npq_num + expq_num + gapq_num) { + PLTFM_MSG_ERR("[ERR]acqnum = %d\n", + adapter->txff_alloc.acq_pg_num); + PLTFM_MSG_ERR("[ERR]hpq_num = %d\n", hpq_num); + PLTFM_MSG_ERR("[ERR]LPQ_num = %d\n", lpq_num); + PLTFM_MSG_ERR("[ERR]npq_num = %d\n", npq_num); + PLTFM_MSG_ERR("[ERR]EPQ_num = %d\n", expq_num); + PLTFM_MSG_ERR("[ERR]gapq_num = %d\n", gapq_num); + return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; + } + + adapter->txff_alloc.high_queue_pg_num = hpq_num; + adapter->txff_alloc.low_queue_pg_num = lpq_num; + adapter->txff_alloc.normal_queue_pg_num = npq_num; + adapter->txff_alloc.extra_queue_pg_num = expq_num; + adapter->txff_alloc.pub_queue_pg_num = pubq_num; + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +rqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode, + struct halmac_rqpn *tbl) +{ + u8 flag; + u32 i; + + flag = 0; + for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) { + if (mode == tbl[i].mode) { + adapter->pq_map[HALMAC_PQ_MAP_VO] = tbl[i].dma_map_vo; + adapter->pq_map[HALMAC_PQ_MAP_VI] = tbl[i].dma_map_vi; + adapter->pq_map[HALMAC_PQ_MAP_BE] = tbl[i].dma_map_be; + adapter->pq_map[HALMAC_PQ_MAP_BK] = tbl[i].dma_map_bk; + adapter->pq_map[HALMAC_PQ_MAP_MG] = tbl[i].dma_map_mg; + adapter->pq_map[HALMAC_PQ_MAP_HI] = tbl[i].dma_map_hi; + flag = 1; + PLTFM_MSG_TRACE("[TRACE]%s done\n", __func__); + break; + } + } + + if (flag == 0) { + PLTFM_MSG_ERR("[ERR]trx mdoe!!\n"); + return HALMAC_RET_TRX_MODE_NOT_SUPPORT; + } + + return HALMAC_RET_SUCCESS; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_init_88xx.h b/hal/halmac/halmac_88xx/halmac_init_88xx.h new file mode 100644 index 0000000..83ff9fb --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_init_88xx.h @@ -0,0 +1,68 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_INIT_88XX_H_ +#define _HALMAC_INIT_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +register_api_88xx(struct halmac_adapter *adapter, + struct halmac_api_registry *registry); + +void +init_adapter_param_88xx(struct halmac_adapter *adapter); + +void +init_adapter_dynamic_param_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +mount_api_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +pre_init_system_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_system_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode); + +enum halmac_ret_status +reset_ofld_feature_88xx(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id); + +enum halmac_ret_status +verify_platform_api_88xx(struct halmac_adapter *adapter); + +void +tx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable); + +enum halmac_ret_status +pg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode, + struct halmac_pg_num *tbl); + +enum halmac_ret_status +rqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode, + struct halmac_rqpn *tbl); + +void +init_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_INIT_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_mimo_88xx.c b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c new file mode 100644 index 0000000..b961b24 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c @@ -0,0 +1,876 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_mimo_88xx.h" +#include "halmac_88xx_cfg.h" +#include "halmac_common_88xx.h" +#include "halmac_init_88xx.h" + +#if HALMAC_88XX_SUPPORT + +#define TXBF_CTRL_CFG (BIT_R_ENABLE_NDPA | BIT_USE_NDPA_PARAMETER | \ + BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN) + +static void +cfg_mu_bfee_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param); + +static void +cfg_mu_bfer_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param); + +static enum halmac_cmd_construct_state +fw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter); + +static enum halmac_ret_status +cnv_fw_snding_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state); + +static u8 +snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt); + +/** + * cfg_txbf_88xx() - enable/disable specific user's txbf + * @adapter : the adapter of halmac + * @userid : su bfee userid = 0 or 1 to apply TXBF + * @bw : the sounding bandwidth + * @txbf_en : 0: disable TXBF, 1: enable TXBF + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw, + u8 txbf_en) +{ + u16 tmp42c = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (txbf_en) { + switch (bw) { + case HALMAC_BW_80: + tmp42c |= BIT_R_TXBF0_80M; + case HALMAC_BW_40: + tmp42c |= BIT_R_TXBF0_40M; + case HALMAC_BW_20: + tmp42c |= BIT_R_TXBF0_20M; + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + } + + switch (userid) { + case 0: + tmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL) & + ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL, tmp42c); + break; + case 1: + tmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL + 2) & + ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_mumimo_88xx() -config mumimo + * @adapter : the adapter of halmac + * @param : parameters to configure MU PPDU Tx/Rx + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_mumimo_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param) +{ + if (param->role == HAL_BFEE) + cfg_mu_bfee_88xx(adapter, param); + else + cfg_mu_bfer_88xx(adapter, param); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +static void +cfg_mu_bfee_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param) +{ + u8 mu_tbl_sel; + u8 tmp14c0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + tmp14c0 = HALMAC_REG_R8(REG_MU_TX_CTL) & ~BIT_MASK_R_MU_TABLE_VALID; + HALMAC_REG_W8(REG_MU_TX_CTL, (tmp14c0 | BIT(0) | BIT(1)) & ~(BIT(7))); + + /*config GID valid table and user position table*/ + mu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8; + + HALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel); + HALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[0]); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[1]); + + HALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel | 1); + HALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[1]); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[3]); +} + +static void +cfg_mu_bfer_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param) +{ + u8 i; + u8 idx; + u8 id0; + u8 id1; + u8 gid; + u8 mu_tbl_sel; + u8 mu_tbl_valid = 0; + u32 gid_valid[6] = {0}; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + if (param->mu_tx_en == 0) { + HALMAC_REG_W8(REG_MU_TX_CTL, + HALMAC_REG_R8(REG_MU_TX_CTL) & ~(BIT(7))); + return; + } + + for (idx = 0; idx < 15; idx++) { + if (idx < 5) { + /*grouping_bitmap bit0~4, MU_STA0 with MUSTA1~5*/ + id0 = 0; + id1 = (u8)(idx + 1); + } else if (idx < 9) { + /*grouping_bitmap bit5~8, MU_STA1 with MUSTA2~5*/ + id0 = 1; + id1 = (u8)(idx - 3); + } else if (idx < 12) { + /*grouping_bitmap bit9~11, MU_STA2 with MUSTA3~5*/ + id0 = 2; + id1 = (u8)(idx - 6); + } else if (idx < 14) { + /*grouping_bitmap bit12~13, MU_STA3 with MUSTA4~5*/ + id0 = 3; + id1 = (u8)(idx - 8); + } else { + /*grouping_bitmap bit14, MU_STA4 with MUSTA5*/ + id0 = 4; + id1 = (u8)(idx - 9); + } + if (param->grouping_bitmap & BIT(idx)) { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + } else { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + } + } + + /*set MU STA GID valid TABLE*/ + mu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8; + for (idx = 0; idx < 6; idx++) { + HALMAC_REG_W8(REG_MU_TX_CTL + 1, idx | mu_tbl_sel); + HALMAC_REG_W32(REG_MU_STA_GID_VLD, gid_valid[idx]); + } + + /*To validate the sounding successful MU STA and enable MU TX*/ + for (i = 0; i < 6; i++) { + if (param->sounding_sts[i] == 1) + mu_tbl_valid |= BIT(i); + } + HALMAC_REG_W8(REG_MU_TX_CTL, mu_tbl_valid | BIT(7)); +} + +/** + * cfg_sounding_88xx() - configure general sounding + * @adapter : the adapter of halmac + * @role : driver's role, BFer or BFee + * @rate : set ndpa tx rate if driver is BFer, + * or set csi response rate if driver is BFee + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role, + enum halmac_data_rate rate) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u32 tmp6dc = 0; + u8 csi_rsc = 0x1; + + /*use ndpa rx rate to decide csi rate*/ + tmp6dc = HALMAC_REG_R32(REG_BBPSF_CTRL) | BIT_WMAC_USE_NDPARATE + | (csi_rsc << 13); + + switch (role) { + case HAL_BFER: + HALMAC_REG_W32_SET(REG_TXBF_CTRL, TXBF_CTRL_CFG); + HALMAC_REG_W8(REG_NDPA_RATE, rate); + HALMAC_REG_W8_CLR(REG_NDPA_OPT_CTRL, BIT(0) | BIT(1)); + HALMAC_REG_W8(REG_SND_PTCL_CTRL + 1, 0x2 | BIT(7)); + HALMAC_REG_W8(REG_SND_PTCL_CTRL + 2, 0x2); + break; + case HAL_BFEE: + HALMAC_REG_W8(REG_SND_PTCL_CTRL, 0xDB); + HALMAC_REG_W8(REG_SND_PTCL_CTRL + 3, 0x26); + HALMAC_REG_W8_CLR(REG_RXFLTMAP1, BIT(4)); + HALMAC_REG_W8_CLR(REG_RXFLTMAP4, BIT(4)); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + /*AP mode set tx gid to 63*/ + /*STA mode set tx gid to 0*/ + if (BIT_GET_NETYPE0(HALMAC_REG_R32(REG_CR)) == 0x3) + HALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc | BIT(12)); + else + HALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc & ~(BIT(12))); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * del_sounding_88xx() - reset general sounding + * @adapter : the adapter of halmac + * @role : driver's role, BFer or BFee + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +del_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + switch (role) { + case HAL_BFER: + HALMAC_REG_W8(REG_TXBF_CTRL + 3, 0); + break; + case HAL_BFEE: + HALMAC_REG_W8(REG_SND_PTCL_CTRL, 0); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * su_bfee_entry_init_88xx() - config SU beamformee's registers + * @adapter : the adapter of halmac + * @userid : SU bfee userid = 0 or 1 to be added + * @paid : partial AID of this bfee + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +su_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid) +{ + u16 tmp42c = 0; + u16 tmp168x = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + switch (userid) { + case 0: + tmp42c = HALMAC_REG_R16(REG_TXBF_CTRL) & + ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | + BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL, tmp42c | paid); + HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid); + #if HALMAC_8822C_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8822C) + HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid | BIT(9)); + #endif + break; + case 1: + tmp42c = HALMAC_REG_R16(REG_TXBF_CTRL + 2) & + ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | + BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c | paid); + HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9)); + break; + case 2: + tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE2); + tmp168x = BIT_CLEAR_WMAC_MU_BFEE2_AID(tmp168x); + tmp168x |= (paid | BIT(9)); + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, tmp168x); + break; + case 3: + tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE3); + tmp168x = BIT_CLEAR_WMAC_MU_BFEE3_AID(tmp168x); + tmp168x |= (paid | BIT(9)); + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, tmp168x); + break; + case 4: + tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE4); + tmp168x = BIT_CLEAR_WMAC_MU_BFEE4_AID(tmp168x); + tmp168x |= (paid | BIT(9)); + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, tmp168x); + break; + case 5: + tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE5); + tmp168x = BIT_CLEAR_WMAC_MU_BFEE5_AID(tmp168x); + tmp168x |= (paid | BIT(9)); + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, tmp168x); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * su_bfee_entry_init_88xx() - config SU beamformer's registers + * @adapter : the adapter of halmac + * @param : parameters to configure SU BFER entry + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +su_bfer_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_su_bfer_init_para *param) +{ + u16 mac_addr_h; + u32 mac_addr_l; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + mac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low); + mac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high); + + switch (param->userid) { + case 0: + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid); + HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para); + break; + case 1: + HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, mac_addr_l); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 4, mac_addr_h); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 6, param->paid); + HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20 + 2, param->csi_para); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * mu_bfee_entry_init_88xx() - config MU beamformee's registers + * @adapter : the adapter of halmac + * @param : parameters to configure MU BFEE entry + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mu_bfee_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_mu_bfee_init_para *param) +{ + u16 tmp168x = 0; + u16 tmp14c0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + tmp168x |= param->paid | BIT(9); + HALMAC_REG_W16((0x1680 + param->userid * 2), tmp168x); + + tmp14c0 = HALMAC_REG_R16(REG_MU_TX_CTL) & ~(BIT(8) | BIT(9) | BIT(10)); + HALMAC_REG_W16(REG_MU_TX_CTL, tmp14c0 | ((param->userid - 2) << 8)); + HALMAC_REG_W32(REG_MU_STA_GID_VLD, 0); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->user_position_l); + HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->user_position_h); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * mu_bfer_entry_init_88xx() - config MU beamformer's registers + * @adapter : the adapter of halmac + * @param : parameters to configure MU BFER entry + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mu_bfer_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_mu_bfer_init_para *param) +{ + u16 tmp1680 = 0; + u16 mac_addr_h; + u32 mac_addr_l; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + mac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low); + mac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high); + + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h); + HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid); + HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para); + + tmp1680 = HALMAC_REG_R16(0x1680) & 0xC000; + tmp1680 |= param->my_aid | (param->csi_length_sel << 12); + HALMAC_REG_W16(0x1680, tmp1680); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * su_bfee_entry_del_88xx() - reset SU beamformee's registers + * @adapter : the adapter of halmac + * @userid : the SU BFee userid to be deleted + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +su_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid) +{ + u16 value16; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + switch (userid) { + case 0: + value16 = HALMAC_REG_R16(REG_TXBF_CTRL); + value16 &= ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | + BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL, value16); + HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, 0); + break; + case 1: + value16 = HALMAC_REG_R16(REG_TXBF_CTRL + 2); + value16 &= ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | + BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_W16(REG_TXBF_CTRL + 2, value16); + HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, 0); + break; + case 2: + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, 0); + break; + case 3: + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, 0); + break; + case 4: + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, 0); + break; + case 5: + HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, 0); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * su_bfee_entry_del_88xx() - reset SU beamformer's registers + * @adapter : the adapter of halmac + * @userid : the SU BFer userid to be deleted + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +su_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + switch (userid) { + case 0: + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0); + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0); + break; + case 1: + HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, 0); + HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO + 4, 0); + break; + default: + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * mu_bfee_entry_del_88xx() - reset MU beamformee's registers + * @adapter : the adapter of halmac + * @userid : the MU STA userid to be deleted + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W16(0x1680 + userid * 2, 0); + HALMAC_REG_W8_CLR(REG_MU_TX_CTL, BIT(userid - 2)); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * mu_bfer_entry_del_88xx() -reset MU beamformer's registers + * @adapter : the adapter of halmac + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +mu_bfer_entry_del_88xx(struct halmac_adapter *adapter) +{ + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0); + HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0); + HALMAC_REG_W16(0x1680, 0); + HALMAC_REG_W8(REG_MU_TX_CTL, 0); + + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_csi_rate_88xx() - config CSI frame Tx rate + * @adapter : the adapter of halmac + * @rssi : rssi in decimal value + * @cur_rate : current CSI frame rate + * @fixrate_en : enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate + * @new_rate : API returns the final CSI frame rate + * Author : chunchu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate, + u8 fixrate_en, u8 *new_rate) +{ + u32 csi_cfg; + u16 cur_rrsr; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); + +#if HALMAC_8821C_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8821C && fixrate_en) { + csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE; + HALMAC_REG_W32(REG_BBPSF_CTRL, + csi_cfg | BIT_CSI_FORCE_RATE_EN | + BIT_CSI_RSC(1) | + BIT_WMAC_CSI_RATE(HALMAC_VHT_NSS1_MCS3)); + *new_rate = HALMAC_VHT_NSS1_MCS3; + return HALMAC_RET_SUCCESS; + } + csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE & + ~BIT_CSI_FORCE_RATE_EN; +#else + csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE; +#endif + + cur_rrsr = HALMAC_REG_R16(REG_RRSR); + + if (rssi >= 40) { + if (cur_rate != HALMAC_OFDM54) { + cur_rrsr |= BIT(HALMAC_OFDM54); + csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM54); + HALMAC_REG_W16(REG_RRSR, cur_rrsr); + HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg); + } + *new_rate = HALMAC_OFDM54; + } else { + if (cur_rate != HALMAC_OFDM24) { + cur_rrsr &= ~(BIT(HALMAC_OFDM54)); + csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM24); + HALMAC_REG_W16(REG_RRSR, cur_rrsr); + HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg); + } + *new_rate = HALMAC_OFDM24; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * fw_snding_88xx() - fw sounding control + * @adapter : the adapter of halmac + * @su_info : + * su0_en : enable/disable fw sounding + * su0_ndpa_pkt : ndpa pkt, shall include txdesc + * su0_pkt_sz : ndpa pkt size, shall include txdesc + * @mu_info : currently not in use, input NULL is acceptable + * @period : sounding period, unit is 5ms + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +fw_snding_88xx(struct halmac_adapter *adapter, + struct halmac_su_snding_info *su_info, + struct halmac_mu_snding_info *mu_info, u8 period) +{ + u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 }; + u16 seq_num; + u16 snding_info_addr; + struct halmac_h2c_header_info hdr_info; + enum halmac_cmd_process_status *proc_status; + enum halmac_ret_status status; + + proc_status = &adapter->halmac_state.fw_snding_state.proc_status; + + if (adapter->chip_id == HALMAC_CHIP_ID_8821C) + return HALMAC_RET_NOT_SUPPORT; + + if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS) + return HALMAC_RET_NO_DLFW; + + if (adapter->fw_ver.h2c_version < 9) + return HALMAC_RET_FW_NO_SUPPORT; + + if (*proc_status == HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_TRACE("[TRACE]Wait event(snd)\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (su_info->su0_en == 1) { + if (!su_info->su0_ndpa_pkt) + return HALMAC_RET_NULL_POINTER; + + if (su_info->su0_pkt_sz > (u32)SU0_SNDING_PKT_RSVDPG_SIZE - + adapter->hw_cfg_info.txdesc_size) + return HALMAC_RET_DATA_SIZE_INCORRECT; + + if (!snding_pkt_chk_88xx(adapter, su_info->su0_ndpa_pkt)) + return HALMAC_RET_TXDESC_SET_FAIL; + + if (fw_snding_cmd_cnstr_state_88xx(adapter) != + HALMAC_CMD_CNSTR_IDLE) { + PLTFM_MSG_ERR("[ERR]Not idle(snd)\n"); + return HALMAC_RET_ERROR_STATE; + } + + snding_info_addr = adapter->txff_alloc.rsvd_h2c_sta_info_addr + + SU0_SNDING_PKT_OFFSET; + status = dl_rsvd_page_88xx(adapter, snding_info_addr, + su_info->su0_ndpa_pkt, + su_info->su0_pkt_sz); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]dl rsvd page\n"); + return status; + } + + FW_SNDING_SET_SU0(h2c_buf, 1); + FW_SNDING_SET_PERIOD(h2c_buf, period); + FW_SNDING_SET_NDPA0_HEAD_PG(h2c_buf, snding_info_addr - + adapter->txff_alloc.rsvd_boundary); + } else { + if (fw_snding_cmd_cnstr_state_88xx(adapter) != + HALMAC_CMD_CNSTR_BUSY) { + PLTFM_MSG_ERR("[ERR]Not snd(snd)\n"); + return HALMAC_RET_ERROR_STATE; + } + FW_SNDING_SET_SU0(h2c_buf, 0); + } + + *proc_status = HALMAC_CMD_PROCESS_SENDING; + + hdr_info.sub_cmd_id = SUB_CMD_ID_FW_SNDING; + hdr_info.content_size = 8; + hdr_info.ack = 1; + set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num); + adapter->halmac_state.fw_snding_state.seq_num = seq_num; + + status = send_h2c_pkt_88xx(adapter, h2c_buf); + if (status != HALMAC_RET_SUCCESS) { + PLTFM_MSG_ERR("[ERR]send h2c\n"); + reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_FW_SNDING); + return status; + } + + if (cnv_fw_snding_state_88xx(adapter, su_info->su0_en == 1 ? + HALMAC_CMD_CNSTR_BUSY : + HALMAC_CMD_CNSTR_IDLE) + != HALMAC_RET_SUCCESS) + return HALMAC_RET_ERROR_STATE; + + return HALMAC_RET_SUCCESS; +} + +static u8 +snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt) +{ + u8 data_rate; + + if (GET_TX_DESC_NDPA(pkt) == 0) { + PLTFM_MSG_ERR("[ERR]txdesc ndpa = 0\n"); + return 0; + } + + data_rate = (u8)GET_TX_DESC_DATARATE(pkt); + if (!(data_rate >= HALMAC_VHT_NSS2_MCS0 && + data_rate <= HALMAC_VHT_NSS2_MCS9)) { + if (!(data_rate >= HALMAC_MCS8 && data_rate <= HALMAC_MCS15)) { + PLTFM_MSG_ERR("[ERR]txdesc rate\n"); + return 0; + } + } + + if (GET_TX_DESC_NAVUSEHDR(pkt) == 0) { + PLTFM_MSG_ERR("[ERR]txdesc navusehdr = 0\n"); + return 0; + } + + if (GET_TX_DESC_USE_RATE(pkt) == 0) { + PLTFM_MSG_ERR("[ERR]txdesc userate = 0\n"); + return 0; + } + + return 1; +} + +static enum halmac_cmd_construct_state +fw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter) +{ + return adapter->halmac_state.fw_snding_state.cmd_cnstr_state; +} + +enum halmac_ret_status +get_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + u8 seq_num = 0; + u8 fw_rc; + struct halmac_fw_snding_state *state; + enum halmac_cmd_process_status proc_status; + + state = &adapter->halmac_state.fw_snding_state; + + seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf); + PLTFM_MSG_TRACE("[TRACE]Seq num:h2c->%d c2h->%d\n", + state->seq_num, seq_num); + if (seq_num != state->seq_num) { + PLTFM_MSG_ERR("[ERR]Seq num mismatch:h2c->%d c2h->%d\n", + state->seq_num, seq_num); + return HALMAC_RET_SUCCESS; + } + + if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) { + PLTFM_MSG_ERR("[ERR]not sending(snd)\n"); + return HALMAC_RET_SUCCESS; + } + + fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf); + state->fw_rc = fw_rc; + + if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) { + proc_status = HALMAC_CMD_PROCESS_DONE; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status, + NULL, 0); + } else { + proc_status = HALMAC_CMD_PROCESS_ERROR; + state->proc_status = proc_status; + PLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status, + &fw_rc, 1); + } + + return HALMAC_RET_SUCCESS; +} + +enum halmac_ret_status +get_fw_snding_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status) +{ + *proc_status = adapter->halmac_state.fw_snding_state.proc_status; + + return HALMAC_RET_SUCCESS; +} + +static enum halmac_ret_status +cnv_fw_snding_state_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_construct_state dest_state) +{ + struct halmac_fw_snding_state *state; + + state = &adapter->halmac_state.fw_snding_state; + + if (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE && + state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY) + return HALMAC_RET_ERROR_STATE; + + if (dest_state == HALMAC_CMD_CNSTR_IDLE) { + if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE) + return HALMAC_RET_ERROR_STATE; + } else if (dest_state == HALMAC_CMD_CNSTR_BUSY) { + if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_BUSY) + return HALMAC_RET_ERROR_STATE; + } + + state->cmd_cnstr_state = dest_state; + + return HALMAC_RET_SUCCESS; +} +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_mimo_88xx.h b/hal/halmac/halmac_88xx/halmac_mimo_88xx.h new file mode 100644 index 0000000..95d0372 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_mimo_88xx.h @@ -0,0 +1,83 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_MIMO_88XX_H_ +#define _HALMAC_MIMO_88XX_H_ + +#include "../halmac_api.h" + +#if HALMAC_88XX_SUPPORT + +enum halmac_ret_status +cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw, + u8 txbf_en); + +enum halmac_ret_status +cfg_mumimo_88xx(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param); + +enum halmac_ret_status +cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role, + enum halmac_data_rate rate); + +enum halmac_ret_status +del_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role); + +enum halmac_ret_status +su_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid); + +enum halmac_ret_status +su_bfer_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_su_bfer_init_para *param); + +enum halmac_ret_status +mu_bfee_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_mu_bfee_init_para *param); + +enum halmac_ret_status +mu_bfer_entry_init_88xx(struct halmac_adapter *adapter, + struct halmac_mu_bfer_init_para *param); + +enum halmac_ret_status +su_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid); + +enum halmac_ret_status +su_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid); + +enum halmac_ret_status +mu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid); + +enum halmac_ret_status +mu_bfer_entry_del_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate, + u8 fixrate_en, u8 *new_rate); + +enum halmac_ret_status +fw_snding_88xx(struct halmac_adapter *adapter, + struct halmac_su_snding_info *su_info, + struct halmac_mu_snding_info *mu_info, u8 period); + +enum halmac_ret_status +get_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +enum halmac_ret_status +get_fw_snding_status_88xx(struct halmac_adapter *adapter, + enum halmac_cmd_process_status *proc_status); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_MIMO_88XX_H_ */ diff --git a/hal/halmac/halmac_88xx/halmac_pcie_88xx.c b/hal/halmac/halmac_88xx/halmac_pcie_88xx.c new file mode 100644 index 0000000..574174f --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_pcie_88xx.c @@ -0,0 +1,537 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#include "halmac_pcie_88xx.h" + +#if (HALMAC_88XX_SUPPORT && HALMAC_PCIE_SUPPORT) + +/** + * init_pcie_cfg_88xx() - init PCIe + * @adapter : the adapter of halmac + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +init_pcie_cfg_88xx(struct halmac_adapter *adapter) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * deinit_pcie_cfg_88xx() - deinit PCIE + * @adapter : the adapter of halmac + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +deinit_pcie_cfg_88xx(struct halmac_adapter *adapter) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_pcie_rx_agg_88xx() - config rx aggregation + * @adapter : the adapter of halmac + * @halmac_rx_agg_mode + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter, + struct halmac_rxagg_cfg *cfg) +{ + return HALMAC_RET_SUCCESS; +} + +/** + * reg_r8_pcie_88xx() - read 1byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u8 +reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset) +{ + return PLTFM_REG_R8(offset); +} + +/** + * reg_w8_pcie_88xx() - write 1byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value) +{ + PLTFM_REG_W8(offset, value); + + return HALMAC_RET_SUCCESS; +} + +/** + * reg_r16_pcie_88xx() - read 2byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u16 +reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset) +{ + return PLTFM_REG_R16(offset); +} + +/** + * reg_w16_pcie_88xx() - write 2byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value) +{ + PLTFM_REG_W16(offset, value); + + return HALMAC_RET_SUCCESS; +} + +/** + * reg_r32_pcie_88xx() - read 4byte register + * @adapter : the adapter of halmac + * @offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u32 +reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset) +{ + return PLTFM_REG_R32(offset); +} + +/** + * reg_w32_pcie_88xx() - write 4byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @value : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value) +{ + PLTFM_REG_W32(offset, value); + + return HALMAC_RET_SUCCESS; +} + +/** + * cfg_txagg_pcie_align_88xx() -config sdio bus tx agg alignment + * @adapter : the adapter of halmac + * @enable : function enable(1)/disable(0) + * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11) + * Author : Soar Tu + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable, + u16 align_size) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * tx_allowed_pcie_88xx() - check tx status + * @adapter : the adapter of halmac + * @buf : tx packet, include txdesc + * @size : tx packet size, include txdesc + * Author : Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * pcie_indirect_reg_r32_88xx() - read MAC reg by SDIO reg + * @adapter : the adapter of halmac + * @offset : register offset + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +u32 +pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset) +{ + return 0xFFFFFFFF; +} + +/** + * pcie_reg_rn_88xx() - read n byte register + * @adapter : the adapter of halmac + * @offset : register offset + * @size : register value size + * @value : register value + * Author : Soar + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *value) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * set_pcie_bulkout_num_88xx() - inform bulk-out num + * @adapter : the adapter of halmac + * @num : usb bulk-out number + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * get_pcie_tx_addr_88xx() - get CMD53 addr for the TX packet + * @adapter : the adapter of halmac + * @buf : tx packet, include txdesc + * @size : tx packet size + * @cmd53_addr : cmd53 addr value + * Author : KaiYuan Chang/Ivan Lin + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u32 *cmd53_addr) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +/** + * get_pcie_bulkout_id_88xx() - get bulk out id for the TX packet + * @adapter : the adapter of halmac + * @buf : tx packet, include txdesc + * @size : tx packet size + * @id : usb bulk-out id + * Author : KaiYuan Chang + * Return : enum halmac_ret_status + * More details of status code can be found in prototype document + */ +enum halmac_ret_status +get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 *id) +{ + return HALMAC_RET_NOT_SUPPORT; +} + +enum halmac_ret_status +mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed) +{ + u8 tmp_u1b = 0; + u32 cnt = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 real_addr = 0; + + HALMAC_REG_W16(REG_MDIO_V1, data); + + real_addr = (addr & 0x1F); + HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr); + + if (speed == HAL_INTF_PHY_PCIE_GEN1) { + if (addr < 0x20) + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00); + else + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01); + } else if (speed == HAL_INTF_PHY_PCIE_GEN2) { + if (addr < 0x20) + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02); + else + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03); + } else { + PLTFM_MSG_ERR("[ERR]Error Speed !\n"); + } + + HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1); + + tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1; + cnt = 20; + + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1; + cnt--; + } + + if (tmp_u1b) { + PLTFM_MSG_ERR("[ERR]MDIO write fail!\n"); + return HALMAC_RET_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +u16 +mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed) +{ + u16 ret = 0; + u8 tmp_u1b = 0; + u32 cnt = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + u8 real_addr = 0; + + real_addr = (addr & 0x1F); + HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr); + + if (speed == HAL_INTF_PHY_PCIE_GEN1) { + if (addr < 0x20) + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00); + else + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01); + } else if (speed == HAL_INTF_PHY_PCIE_GEN2) { + if (addr < 0x20) + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02); + else + HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03); + } else { + PLTFM_MSG_ERR("[ERR]Error Speed !\n"); + } + + HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_RFLAG_V1); + + tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1; + cnt = 20; + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1; + cnt--; + } + + if (tmp_u1b) { + ret = 0xFFFF; + PLTFM_MSG_ERR("[ERR]MDIO read fail!\n"); + } else { + ret = HALMAC_REG_R16(REG_MDIO_V1 + 2); + PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret); + } + + return ret; +} + +enum halmac_ret_status +dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data) +{ + u8 tmp_u1b = 0; + u32 cnt = 0; + u16 write_addr = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W32(REG_DBI_WDATA_V1, data); + + write_addr = ((addr & 0x0ffc) | (0x000F << 12)); + HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr); + + PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr); + + HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + + cnt = 20; + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + cnt--; + } + + if (tmp_u1b) { + PLTFM_MSG_ERR("[ERR]DBI write fail!\n"); + return HALMAC_RET_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +u32 +dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr) +{ + u16 read_addr = addr & 0x0ffc; + u8 tmp_u1b = 0; + u32 cnt = 0; + u32 ret = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr); + + HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + + cnt = 20; + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + cnt--; + } + + if (tmp_u1b) { + ret = 0xFFFF; + PLTFM_MSG_ERR("[ERR]DBI read fail!\n"); + } else { + ret = HALMAC_REG_R32(REG_DBI_RDATA_V1); + PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret); + } + + return ret; +} + +enum halmac_ret_status +dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data) +{ + u8 tmp_u1b = 0; + u32 cnt = 0; + u16 write_addr = 0; + u16 remainder = addr & (4 - 1); + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W8(REG_DBI_WDATA_V1 + remainder, data); + + write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12))); + + HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr); + + PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr); + + HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01); + + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + + cnt = 20; + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + cnt--; + } + + if (tmp_u1b) { + PLTFM_MSG_ERR("[ERR]DBI write fail!\n"); + return HALMAC_RET_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +u8 +dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr) +{ + u16 read_addr = addr & 0x0ffc; + u8 tmp_u1b = 0; + u32 cnt = 0; + u8 ret = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr); + HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2); + + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + + cnt = 20; + while (tmp_u1b && (cnt != 0)) { + PLTFM_DELAY_US(10); + tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2); + cnt--; + } + + if (tmp_u1b) { + ret = 0xFF; + PLTFM_MSG_ERR("[ERR]DBI read fail!\n"); + } else { + ret = HALMAC_REG_R8(REG_DBI_RDATA_V1 + (addr & (4 - 1))); + PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret); + } + + return ret; +} + +enum halmac_ret_status +trxdma_check_idle_88xx(struct halmac_adapter *adapter) +{ + u32 cnt = 0; + struct halmac_api *api = (struct halmac_api *)adapter->halmac_api; + + /* Stop Tx & Rx DMA */ + HALMAC_REG_W32_SET(REG_RXPKT_NUM, BIT(18)); + HALMAC_REG_W16_SET(REG_PCIE_CTRL, ~(BIT(15) | BIT(8))); + + /* Stop FW */ + HALMAC_REG_W16_CLR(REG_SYS_FUNC_EN, BIT(10)); + + /* Check Tx DMA is idle */ + cnt = 20; + while ((HALMAC_REG_R8(REG_SYS_CFG5) & BIT(2)) == BIT(2)) { + PLTFM_DELAY_US(10); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]Chk tx idle\n"); + return HALMAC_RET_POWER_OFF_FAIL; + } + } + + /* Check Rx DMA is idle */ + cnt = 20; + while ((HALMAC_REG_R32(REG_RXPKT_NUM) & BIT(17)) != BIT(17)) { + PLTFM_DELAY_US(10); + cnt--; + if (cnt == 0) { + PLTFM_MSG_ERR("[ERR]Chk rx idle\n"); + return HALMAC_RET_POWER_OFF_FAIL; + } + } + + return HALMAC_RET_SUCCESS; +} + +void +en_ref_autok_88xx(struct halmac_adapter *adapter, u8 en) +{ + if (en == 1) + adapter->pcie_refautok_en = 1; + else + adapter->pcie_refautok_en = 0; +} + +#endif /* HALMAC_88XX_SUPPORT */ diff --git a/hal/halmac/halmac_88xx/halmac_pcie_88xx.h b/hal/halmac/halmac_88xx/halmac_pcie_88xx.h new file mode 100644 index 0000000..0da6632 --- /dev/null +++ b/hal/halmac/halmac_88xx/halmac_pcie_88xx.h @@ -0,0 +1,102 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_PCIE_88XX_H_ +#define _HALMAC_PCIE_88XX_H_ + +#include "../halmac_api.h" + +#if (HALMAC_88XX_SUPPORT && HALMAC_PCIE_SUPPORT) + +enum halmac_ret_status +init_pcie_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +deinit_pcie_cfg_88xx(struct halmac_adapter *adapter); + +enum halmac_ret_status +cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter, + struct halmac_rxagg_cfg *cfg); + +u8 +reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value); + +u16 +reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value); + +u32 +reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value); + +enum halmac_ret_status +cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable, + u16 align_size); + +enum halmac_ret_status +tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size); + +u32 +pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset); + +enum halmac_ret_status +pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, + u8 *value); + +enum halmac_ret_status +set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num); + +enum halmac_ret_status +get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u32 *cmd53_addr); + +enum halmac_ret_status +get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, + u8 *id); + +enum halmac_ret_status +mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed); + +u16 +mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed); + +enum halmac_ret_status +dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data); + +u32 +dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr); + +enum halmac_ret_status +dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data); + +u8 +dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr); + +enum halmac_ret_status +trxdma_check_idle_88xx(struct halmac_adapter *adapter); + +void +en_ref_autok_88xx(struct halmac_adapter *dapter, u8 en); + +#endif /* HALMAC_88XX_SUPPORT */ + +#endif/* _HALMAC_PCIE_88XX_H_ */ diff --git a/hal/halmac/halmac_api.c b/hal/halmac/halmac_api.c index a585d0c..d9e3645 100644 --- a/hal/halmac/halmac_api.c +++ b/hal/halmac/halmac_api.c @@ -1,367 +1,455 @@ -#include "halmac_2_platform.h" +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #include "halmac_type.h" -#if HALMAC_PLATFORM_WINDOWS == 1 +#include "halmac_api.h" + +#if (HALMAC_PLATFORM_WINDOWS) + #if HALMAC_8822B_SUPPORT -#include "halmac_88xx/halmac_api_win8822b.h" -#include "halmac_88xx/halmac_win8822b_cfg.h" +#include "halmac_88xx/halmac_init_win8822b.h" #endif + #if HALMAC_8821C_SUPPORT -#include "halmac_88xx/halmac_api_win8821c.h" -#include "halmac_88xx/halmac_win8821c_cfg.h" +#include "halmac_88xx/halmac_init_win8821c.h" #endif -#else -#include "halmac_88xx/halmac_api_88xx.h" -#include "halmac_88xx/halmac_88xx_cfg.h" +#if HALMAC_8814B_SUPPORT +#include "halmac_88xx_v1/halmac_init_win8814b_v1.h" #endif -#if HALMAC_8822B_SUPPORT -#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h" +#if HALMAC_8822C_SUPPORT +#include "halmac_88xx/halmac_init_win8822c.h" +#endif + +#else + +#if HALMAC_88XX_SUPPORT +#include "halmac_88xx/halmac_init_88xx.h" +#endif +#if HALMAC_88XX_V1_SUPPORT +#include "halmac_88xx_v1/halmac_init_88xx_v1.h" +#if defined(HALMAC_DATA_CPU_EN) +#include "halmac_88xxd_v1/halmac_init_88xxd_v1.h" #endif -#if HALMAC_8821C_SUPPORT -#include "halmac_88xx/halmac_8821c/halmac_8821c_cfg.h" #endif -HALMAC_RET_STATUS -halmac_check_platform_api( - IN VOID *pDriver_adapter, - IN HALMAC_INTERFACE halmac_interface, - IN PHALMAC_PLATFORM_API pHalmac_platform_api -); - -HALMAC_RET_STATUS -halmac_get_chip_info( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN HALMAC_INTERFACE halmac_interface, - IN PHALMAC_ADAPTER pHalmac_adapter -); - -u8 -platform_reg_read_8_sdio( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN u32 offset -); - -HALMAC_RET_STATUS -plarform_reg_write_8_sdio( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN u32 offset, - IN u8 data -); - -HALMAC_RET_STATUS -halmac_convert_to_sdio_bus_offset( - INOUT u32 *halmac_offset -); +#endif + +enum chip_id_hw_def { + CHIP_ID_HW_DEF_8723A = 0x01, + CHIP_ID_HW_DEF_8188E = 0x02, + CHIP_ID_HW_DEF_8881A = 0x03, + CHIP_ID_HW_DEF_8812A = 0x04, + CHIP_ID_HW_DEF_8821A = 0x05, + CHIP_ID_HW_DEF_8723B = 0x06, + CHIP_ID_HW_DEF_8192E = 0x07, + CHIP_ID_HW_DEF_8814A = 0x08, + CHIP_ID_HW_DEF_8821C = 0x09, + CHIP_ID_HW_DEF_8822B = 0x0A, + CHIP_ID_HW_DEF_8703B = 0x0B, + CHIP_ID_HW_DEF_8188F = 0x0C, + CHIP_ID_HW_DEF_8192F = 0x0D, + CHIP_ID_HW_DEF_8197F = 0x0E, + CHIP_ID_HW_DEF_8723D = 0x0F, + CHIP_ID_HW_DEF_8814B = 0x11, + CHIP_ID_HW_DEF_8822C = 0x13, + CHIP_ID_HW_DEF_8812F = 0x14, + CHIP_ID_HW_DEF_UNDEFINE = 0x7F, + CHIP_ID_HW_DEF_PS = 0xEA, +}; + +static enum halmac_ret_status +chk_pltfm_api(void *drv_adapter, enum halmac_interface intf, + struct halmac_platform_api *pltfm_api); + +static enum halmac_ret_status +get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api, + enum halmac_interface intf, struct halmac_adapter *adapter); + +static u8 +pltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset); + +static enum halmac_ret_status +pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset, u8 data); + +static u8 +pltfm_reg_r_indir_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset); + +static enum halmac_ret_status +cnv_to_sdio_bus_offset(u32 *offset); /** * halmac_init_adapter() - init halmac_adapter - * @pDriver_adapter : the adapter of caller - * @pHalmac_platform_api : the platform APIs which is used in halmac APIs - * @halmac_interface : bus interface - * @ppHalmac_adapter : the adapter of halmac - * @ppHalmac_api : the function pointer of APIs, caller shall call APIs by function pointer + * @drv_adapter : the adapter of caller + * @pltfm_api : the platform APIs which is used in halmac + * @intf : bus interface + * @halmac_adapter : the adapter of halmac + * @halmac_api : the function pointer of APIs * Author : KaiYuan Chang / Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_init_adapter( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN HALMAC_INTERFACE halmac_interface, - OUT PHALMAC_ADAPTER *ppHalmac_adapter, - OUT PHALMAC_API *ppHalmac_api -) +enum halmac_ret_status +halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api, + enum halmac_interface intf, + struct halmac_adapter **halmac_adapter, + struct halmac_api **halmac_api) { - PHALMAC_ADAPTER pHalmac_adapter = (PHALMAC_ADAPTER)NULL; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - u8 *pBuf = NULL; + struct halmac_adapter *adapter = NULL; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + u8 *buf = NULL; -#if HALMAC_PLATFORM_WINDOWS == 1 - u8 chip_id = 0; -#endif union { - u32 i; - u8 x[4]; + u32 i; + u8 x[4]; } ENDIAN_CHECK = { 0x01000000 }; - status = halmac_check_platform_api(pDriver_adapter, halmac_interface, pHalmac_platform_api); - if (HALMAC_RET_SUCCESS != status) + status = chk_pltfm_api(drv_adapter, intf, pltfm_api); + if (status != HALMAC_RET_SUCCESS) return status; - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, HALMAC_SVN_VER "\n"); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MAJOR_VER = %x\n", HALMAC_MAJOR_VER); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PROTOTYPE_VER = %x\n", HALMAC_PROTOTYPE_VER); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MINOR_VER = %x\n", HALMAC_MINOR_VER); - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PATCH_VER = %x\n", HALMAC_PATCH_VER); - - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_adapter_88xx ==========>\n"); - /* Check endian setting - Little endian : 1, Big endian : 0*/ - if (HALMAC_SYSTEM_ENDIAN == ENDIAN_CHECK.x[0]) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Endian setting Err!!\n"); + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, + HALMAC_SVN_VER "\n" + "HALMAC_MAJOR_VER = %x\n" + "HALMAC_PROTOTYPE_VER = %x\n" + "HALMAC_MINOR_VER = %x\n" + "HALMAC_PATCH_VER = %x\n", + HALMAC_MAJOR_VER, HALMAC_PROTOTYPE_VER, + HALMAC_MINOR_VER, HALMAC_PATCH_VER); + + if (ENDIAN_CHECK.x[0] == HALMAC_SYSTEM_ENDIAN) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, + "[ERR]Endian setting err!!\n"); return HALMAC_RET_ENDIAN_ERR; } - pBuf = (u8 *)pHalmac_platform_api->RTL_MALLOC(pDriver_adapter, sizeof(HALMAC_ADAPTER)); + buf = (u8 *)pltfm_api->RTL_MALLOC(drv_adapter, sizeof(*adapter)); - if (pBuf == NULL) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Malloc HAL Adapter Err!!\n"); + if (!buf) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, + "[ERR]Malloc HAL adapter err!!\n"); return HALMAC_RET_MALLOC_FAIL; } - pHalmac_platform_api->RTL_MEMSET(pDriver_adapter, pBuf, 0x00, sizeof(HALMAC_ADAPTER)); - pHalmac_adapter = (PHALMAC_ADAPTER)pBuf; + pltfm_api->RTL_MEMSET(drv_adapter, buf, 0x00, sizeof(*adapter)); + adapter = (struct halmac_adapter *)buf; - /* return halmac adapter address to caller */ - *ppHalmac_adapter = pHalmac_adapter; + *halmac_adapter = adapter; - /* Record caller info */ - pHalmac_adapter->pHalmac_platform_api = pHalmac_platform_api; - pHalmac_adapter->pDriver_adapter = pDriver_adapter; - halmac_interface = (HALMAC_INTERFACE_AXI == halmac_interface) ? HALMAC_INTERFACE_PCIE : halmac_interface; - pHalmac_adapter->halmac_interface = halmac_interface; + adapter->pltfm_api = pltfm_api; + adapter->drv_adapter = drv_adapter; + intf = (intf == HALMAC_INTERFACE_AXI) ? HALMAC_INTERFACE_PCIE : intf; + adapter->intf = intf; - PLATFORM_MUTEX_INIT(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); - PLATFORM_MUTEX_INIT(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); - - /*Get Chip*/ - if (HALMAC_RET_SUCCESS != halmac_get_chip_info(pDriver_adapter, pHalmac_platform_api, halmac_interface, pHalmac_adapter)) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_CHIP_NOT_SUPPORT\n"); + if (get_chip_info(drv_adapter, pltfm_api, intf, adapter) + != HALMAC_RET_SUCCESS) { + PLTFM_FREE(*halmac_adapter, sizeof(**halmac_adapter)); + *halmac_adapter = NULL; return HALMAC_RET_CHIP_NOT_SUPPORT; } - /* Assign function pointer to halmac API */ -#if HALMAC_PLATFORM_WINDOWS == 0 - halmac_init_adapter_para_88xx(pHalmac_adapter); - status = halmac_mount_api_88xx(pHalmac_adapter); + PLTFM_MUTEX_INIT(&adapter->efuse_mutex); + PLTFM_MUTEX_INIT(&adapter->h2c_seq_mutex); + PLTFM_MUTEX_INIT(&adapter->sdio_indir_mutex); + +#if (HALMAC_PLATFORM_WINDOWS == 0) + +#if HALMAC_88XX_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8822B || + adapter->chip_id == HALMAC_CHIP_ID_8821C || + adapter->chip_id == HALMAC_CHIP_ID_8822C || + adapter->chip_id == HALMAC_CHIP_ID_8812F) { + init_adapter_param_88xx(adapter); + status = mount_api_88xx(adapter); + } +#endif + +#if HALMAC_88XX_V1_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8814B) { + init_adapter_param_88xx_v1(adapter); + status = mount_api_88xx_v1(adapter); + } +#if defined(HALMAC_DATA_CPU_EN) + if (adapter->chip_id == HALMAC_CHIP_ID_8814B) { + init_adapter_param_88xxd_v1(adapter); + status = mount_api_88xxd_v1(adapter); + } +#endif +#endif + #else #if HALMAC_8822B_SUPPORT - if (HALMAC_CHIP_ID_8822B == pHalmac_adapter->chip_id) { - halmac_init_adapter_para_win8822b(pHalmac_adapter); - status = halmac_mount_api_win8822b(pHalmac_adapter); + if (adapter->chip_id == HALMAC_CHIP_ID_8822B) { + init_adapter_param_win8822b(adapter); + status = mount_api_win8822b(adapter); } #endif + #if HALMAC_8821C_SUPPORT - if (HALMAC_CHIP_ID_8821C == pHalmac_adapter->chip_id) { - halmac_init_adapter_para_win8821c(pHalmac_adapter); - status = halmac_mount_api_win8821c(pHalmac_adapter); + if (adapter->chip_id == HALMAC_CHIP_ID_8821C) { + init_adapter_param_win8821c(adapter); + status = mount_api_win8821c(adapter); + } +#endif + +#if HALMAC_8814B_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8814B) { + init_adapter_param_win8814b_v1(adapter); + status = mount_api_win8814b_v1(adapter); + } +#endif + +#if HALMAC_8822C_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8822C) { + init_adapter_param_win8822c(adapter); + status = mount_api_win8822c(adapter); } #endif +#if HALMAC_8812F_SUPPORT + if (adapter->chip_id == HALMAC_CHIP_ID_8812F) { + init_adapter_param_win8812f(adapter); + status = mount_api_win8812f(adapter); + } #endif - /* Return halmac API function pointer */ - *ppHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; +#endif + *halmac_api = (struct halmac_api *)adapter->halmac_api; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_adapter_88xx <==========\n"); + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); return status; } /** * halmac_halt_api() - stop halmac_api action - * @pHalmac_adapter : the adapter of halmac + * @adapter : the adapter of halmac * Author : Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_halt_api( - IN PHALMAC_ADAPTER pHalmac_adapter -) +enum halmac_ret_status +halmac_halt_api(struct halmac_adapter *adapter) { - VOID *pDriver_adapter = NULL; - PHALMAC_PLATFORM_API pHalmac_platform_api = (PHALMAC_PLATFORM_API)NULL; + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; + adapter->halmac_state.api_state = HALMAC_API_STATE_HALT; - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - pHalmac_platform_api = pHalmac_adapter->pHalmac_platform_api; + PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_halt_api ==========>\n"); - pHalmac_adapter->halmac_state.api_state = HALMAC_API_STATE_HALT; - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_halt_api ==========>\n"); return HALMAC_RET_SUCCESS; } /** * halmac_deinit_adapter() - deinit halmac adapter - * @pHalmac_adapter : the adapter of halmac + * @adapter : the adapter of halmac * Author : KaiYuan Chang / Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_deinit_adapter( - IN PHALMAC_ADAPTER pHalmac_adapter -) +enum halmac_ret_status +halmac_deinit_adapter(struct halmac_adapter *adapter) { - VOID *pDriver_adapter = NULL; + PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__); - if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; + PLTFM_MUTEX_DEINIT(&adapter->efuse_mutex); + PLTFM_MUTEX_DEINIT(&adapter->h2c_seq_mutex); + PLTFM_MUTEX_DEINIT(&adapter->sdio_indir_mutex); - pDriver_adapter = pHalmac_adapter->pDriver_adapter; - - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_deinit_adapter_88xx ==========>\n"); - - PLATFORM_MUTEX_DEINIT(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); - PLATFORM_MUTEX_DEINIT(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + if (adapter->efuse_map) { + PLTFM_FREE(adapter->efuse_map, adapter->hw_cfg_info.efuse_size); + adapter->efuse_map = (u8 *)NULL; + } - if (NULL != pHalmac_adapter->pHalEfuse_map) { - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size); - pHalmac_adapter->pHalEfuse_map = (u8 *)NULL; + if (adapter->sdio_fs.macid_map) { + PLTFM_FREE(adapter->sdio_fs.macid_map, + adapter->sdio_fs.macid_map_size); + adapter->sdio_fs.macid_map = (u8 *)NULL; } - if (NULL != pHalmac_adapter->halmac_state.psd_set.pData) { - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->halmac_state.psd_set.pData, pHalmac_adapter->halmac_state.psd_set.data_size); - pHalmac_adapter->halmac_state.psd_set.pData = (u8 *)NULL; + if (adapter->halmac_state.psd_state.data) { + PLTFM_FREE(adapter->halmac_state.psd_state.data, + adapter->halmac_state.psd_state.data_size); + adapter->halmac_state.psd_state.data = (u8 *)NULL; } - if (NULL != pHalmac_adapter->pHalmac_api) { - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->pHalmac_api, sizeof(HALMAC_API)); - pHalmac_adapter->pHalmac_api = NULL; + if (adapter->halmac_api) { + PLTFM_FREE(adapter->halmac_api, sizeof(struct halmac_api)); + adapter->halmac_api = NULL; } - pHalmac_adapter->pHalAdapter_backup = NULL; - PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter, sizeof(HALMAC_ADAPTER)); + PLTFM_FREE(adapter, sizeof(*adapter)); return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS -halmac_check_platform_api( - IN VOID *pDriver_adapter, - IN HALMAC_INTERFACE halmac_interface, - IN PHALMAC_PLATFORM_API pHalmac_platform_api -) +static enum halmac_ret_status +chk_pltfm_api(void *drv_adapter, enum halmac_interface intf, + struct halmac_platform_api *pltfm_api) { - VOID *pAdapter_Local = NULL; - - pAdapter_Local = pDriver_adapter; - - if (NULL == pHalmac_platform_api) + if (!pltfm_api) return HALMAC_RET_PLATFORM_API_NULL; - if (NULL == pHalmac_platform_api->MSG_PRINT) + if (!pltfm_api->MSG_PRINT) return HALMAC_RET_PLATFORM_API_NULL; - if (HALMAC_INTERFACE_SDIO == halmac_interface) { - if (NULL == pHalmac_platform_api->SDIO_CMD52_READ) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD52_READ)\n"); + if (intf == HALMAC_INTERFACE_SDIO) { + if (!pltfm_api->SDIO_CMD52_READ) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-r\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (!pltfm_api->SDIO_CMD53_READ_8) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-r8\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_8) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_8)\n"); + if (!pltfm_api->SDIO_CMD53_READ_16) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-r16\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_16) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_16)\n"); + if (!pltfm_api->SDIO_CMD53_READ_32) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-r32\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_32) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_32)\n"); + if (!pltfm_api->SDIO_CMD53_READ_N) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-rn\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_N) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_N)\n"); + if (!pltfm_api->SDIO_CMD52_WRITE) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-w\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD52_WRITE) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD52_WRITE)\n"); + if (!pltfm_api->SDIO_CMD53_WRITE_8) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-w8\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_8) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_8)\n"); + if (!pltfm_api->SDIO_CMD53_WRITE_16) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-w16\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_16) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_16)\n"); + if (!pltfm_api->SDIO_CMD53_WRITE_32) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-w32\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_32) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_32)\n"); + if (!pltfm_api->SDIO_CMD52_CIA_READ) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio-cia\n"); return HALMAC_RET_PLATFORM_API_NULL; } } - if ((HALMAC_INTERFACE_USB == halmac_interface) || (HALMAC_INTERFACE_PCIE == halmac_interface)) { - if (NULL == pHalmac_platform_api->REG_READ_8) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_8)\n"); + if (intf == HALMAC_INTERFACE_USB || intf == HALMAC_INTERFACE_PCIE) { + if (!pltfm_api->REG_READ_8) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-r8\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->REG_READ_16) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_16)\n"); + if (!pltfm_api->REG_READ_16) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-r16\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->REG_READ_32) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_32)\n"); + if (!pltfm_api->REG_READ_32) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-r32\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->REG_WRITE_8) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_8)\n"); + if (!pltfm_api->REG_WRITE_8) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-w8\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->REG_WRITE_16) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_16)\n"); + if (!pltfm_api->REG_WRITE_16) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-w16\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->REG_WRITE_32) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_32)\n"); + if (!pltfm_api->REG_WRITE_32) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]reg-w32\n"); return HALMAC_RET_PLATFORM_API_NULL; } } - if (NULL == pHalmac_platform_api->RTL_FREE) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_FREE)\n"); + if (!pltfm_api->RTL_FREE) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mem-free\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->RTL_MALLOC) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MALLOC)\n"); + if (!pltfm_api->RTL_MALLOC) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mem-malloc\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->RTL_MEMCPY) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MEMCPY)\n"); + if (!pltfm_api->RTL_MEMCPY) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mem-cpy\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->RTL_MEMSET) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MEMSET)\n"); + if (!pltfm_api->RTL_MEMSET) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mem-set\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->RTL_DELAY_US) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_DELAY_US)\n"); + if (!pltfm_api->RTL_DELAY_US) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]time-delay\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->MUTEX_INIT) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_INIT)\n"); + if (!pltfm_api->MUTEX_INIT) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mutex-init\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->MUTEX_DEINIT) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_DEINIT)\n"); + if (!pltfm_api->MUTEX_DEINIT) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mutex-deinit\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->MUTEX_LOCK) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_LOCK)\n"); + if (!pltfm_api->MUTEX_LOCK) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mutex-lock\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->MUTEX_UNLOCK) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_UNLOCK)\n"); + if (!pltfm_api->MUTEX_UNLOCK) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]mutex-unlock\n"); return HALMAC_RET_PLATFORM_API_NULL; } - if (NULL == pHalmac_platform_api->EVENT_INDICATION) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->EVENT_INDICATION)\n"); + if (!pltfm_api->EVENT_INDICATION) { + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]event-indication\n"); return HALMAC_RET_PLATFORM_API_NULL; } - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_check_platform_api ==========>\n"); - return HALMAC_RET_SUCCESS; } @@ -369,13 +457,11 @@ halmac_check_platform_api( * halmac_get_version() - get HALMAC version * @version : return version of major, prototype and minor information * Author : KaiYuan Chang / Ivan Lin - * Return : HALMAC_RET_STATUS + * Return : enum halmac_ret_status * More details of status code can be found in prototype document */ -HALMAC_RET_STATUS -halmac_get_version( - OUT HALMAC_VER *version -) +enum halmac_ret_status +halmac_get_version(struct halmac_ver *version) { version->major_ver = (u8)HALMAC_MAJOR_VER; version->prototype_ver = (u8)HALMAC_PROTOTYPE_VER; @@ -384,127 +470,153 @@ halmac_get_version( return HALMAC_RET_SUCCESS; } -HALMAC_RET_STATUS -halmac_get_chip_info( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN HALMAC_INTERFACE halmac_interface, - IN PHALMAC_ADAPTER pHalmac_adapter -) +static enum halmac_ret_status +get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api, + enum halmac_interface intf, struct halmac_adapter *adapter) { - PHALMAC_API pHalmac_api = (PHALMAC_API)NULL; - u8 chip_id, chip_version; - u32 polling_count; - - pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; - - /* Get Chip_id and Chip_version */ - if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { - plarform_reg_write_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SDIO_HSUS_CTRL, platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SDIO_HSUS_CTRL) & ~(BIT(0))); - - polling_count = 10000; - while (!(platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SDIO_HSUS_CTRL) & 0x02)) { - polling_count--; - if (polling_count == 0) + u8 chip_id; + u8 chip_ver; + u32 cnt; + + if (adapter->intf == HALMAC_INTERFACE_SDIO) { + pltfm_reg_w8_sdio(drv_adapter, pltfm_api, REG_SDIO_HSUS_CTRL, + pltfm_reg_r8_sdio(drv_adapter, pltfm_api, + REG_SDIO_HSUS_CTRL) & + ~(BIT(0))); + + cnt = 10000; + while (!(pltfm_reg_r8_sdio(drv_adapter, pltfm_api, + REG_SDIO_HSUS_CTRL) & BIT(1))) { + cnt--; + if (cnt == 0) return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL; } - chip_id = platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SYS_CFG2); - chip_version = platform_reg_read_8_sdio(pDriver_adapter, pHalmac_platform_api, REG_SYS_CFG1 + 1) >> 4; + chip_id = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api, + REG_SYS_CFG2); + chip_ver = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api, + REG_SYS_CFG1 + 1) >> 4; } else { - chip_id = pHalmac_platform_api->REG_READ_8(pDriver_adapter, REG_SYS_CFG2); - chip_version = pHalmac_platform_api->REG_READ_8(pDriver_adapter, REG_SYS_CFG1 + 1) >> 4; + chip_id = pltfm_api->REG_READ_8(drv_adapter, REG_SYS_CFG2); + chip_ver = pltfm_api->REG_READ_8(drv_adapter, + REG_SYS_CFG1 + 1) >> 4; } - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]Chip id : 0x%X\n", chip_id); - PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]Chip version : 0x%X\n", chip_version); - - pHalmac_adapter->chip_version = (HALMAC_CHIP_VER)chip_version; - - if (HALMAC_CHIP_ID_HW_DEF_8822B == chip_id) - pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8822B; - else if (HALMAC_CHIP_ID_HW_DEF_8821C == chip_id) - pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8821C; - else if (HALMAC_CHIP_ID_HW_DEF_8814B == chip_id) - pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8814B; - else if (HALMAC_CHIP_ID_HW_DEF_8197F == chip_id) - pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8197F; - else { - pHalmac_adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE; + adapter->chip_ver = (enum halmac_chip_ver)chip_ver; + + if (chip_id == CHIP_ID_HW_DEF_8822B) { + adapter->chip_id = HALMAC_CHIP_ID_8822B; + } else if (chip_id == CHIP_ID_HW_DEF_8821C) { + adapter->chip_id = HALMAC_CHIP_ID_8821C; + } else if (chip_id == CHIP_ID_HW_DEF_8814B) { + adapter->chip_id = HALMAC_CHIP_ID_8814B; + } else if (chip_id == CHIP_ID_HW_DEF_8197F) { + adapter->chip_id = HALMAC_CHIP_ID_8197F; + } else if (chip_id == CHIP_ID_HW_DEF_8822C) { + adapter->chip_id = HALMAC_CHIP_ID_8822C; + } else if (chip_id == CHIP_ID_HW_DEF_8812F) { + adapter->chip_id = HALMAC_CHIP_ID_8812F; + } else { + adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE; + PLTFM_MSG_ERR("[ERR]Chip id is undefined\n"); return HALMAC_RET_CHIP_NOT_SUPPORT; } return HALMAC_RET_SUCCESS; } -u8 -platform_reg_read_8_sdio( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN u32 offset -) +static u8 +pltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset) { u8 value8; - u32 halmac_offset = offset; - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; - if (0 == (halmac_offset & 0xFFFF0000)) - halmac_offset |= WLAN_IOREG_OFFSET; + if (0 == (offset & 0xFFFF0000)) + offset |= WLAN_IOREG_OFFSET; - status = halmac_convert_to_sdio_bus_offset(&halmac_offset); - if (HALMAC_RET_SUCCESS != status) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "platform_reg_read_8_sdio error = %x\n", status); + status = cnv_to_sdio_bus_offset(&offset); + if (status != HALMAC_RET_SUCCESS) return status; - } - value8 = pHalmac_platform_api->SDIO_CMD52_READ(pDriver_adapter, halmac_offset); + value8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, offset); return value8; } -HALMAC_RET_STATUS -plarform_reg_write_8_sdio( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN u32 offset, - IN u8 data -) +static enum halmac_ret_status +pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset, u8 data) { - HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; - u32 halmac_offset = offset; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; - if (0 == (halmac_offset & 0xFFFF0000)) - halmac_offset |= WLAN_IOREG_OFFSET; + if (0 == (offset & 0xFFFF0000)) + offset |= WLAN_IOREG_OFFSET; - status = halmac_convert_to_sdio_bus_offset(&halmac_offset); + status = cnv_to_sdio_bus_offset(&offset); - if (HALMAC_RET_SUCCESS != status) { - pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_8_sdio_88xx error = %x\n", status); + if (status != HALMAC_RET_SUCCESS) return status; - } - pHalmac_platform_api->SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, data); + + pltfm_api->SDIO_CMD52_WRITE(drv_adapter, offset, data); return HALMAC_RET_SUCCESS; } - -HALMAC_RET_STATUS -halmac_convert_to_sdio_bus_offset( - INOUT u32 *halmac_offset -) +static u8 +pltfm_reg_r_indir_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api, + u32 offset) { + u8 value8, tmp, cnt = 50; + u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG; + u32 reg_data = REG_SDIO_INDIRECT_REG_DATA; + enum halmac_ret_status status = HALMAC_RET_SUCCESS; + + status = cnv_to_sdio_bus_offset(®_cfg); + if (status != HALMAC_RET_SUCCESS) + return status; + status = cnv_to_sdio_bus_offset(®_data); + if (status != HALMAC_RET_SUCCESS) + return status; + + pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg, (u8)offset); + pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 1, + (u8)(offset >> 8)); + pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 2, + (u8)(BIT(3) | BIT(4))); - switch ((*halmac_offset) & 0xFFFF0000) { + do { + tmp = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_cfg + 2); + cnt--; + } while (((tmp & BIT(4)) == 0) && (cnt > 0)); + + if (((cnt & BIT(4)) == 0) && cnt == 0) + pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, + HALMAC_DBG_ERR, "[ERR]sdio indir read\n"); + + value8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_data); + + return value8; +} + +/*Note: copy from cnv_to_sdio_bus_offset_88xx*/ +static enum halmac_ret_status +cnv_to_sdio_bus_offset(u32 *offset) +{ + switch ((*offset) & 0xFFFF0000) { case WLAN_IOREG_OFFSET: - *halmac_offset = (HALMAC_SDIO_CMD_ADDR_MAC_REG << 13) | (*halmac_offset & HALMAC_WLAN_MAC_REG_MSK); + *offset &= HALMAC_WLAN_MAC_REG_MSK; + *offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13; break; case SDIO_LOCAL_OFFSET: - *halmac_offset = (HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13) | (*halmac_offset & HALMAC_SDIO_LOCAL_MSK); + *offset &= HALMAC_SDIO_LOCAL_MSK; + *offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13; break; default: - *halmac_offset = 0xFFFFFFFF; + *offset = 0xFFFFFFFF; return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL; } return HALMAC_RET_SUCCESS; } + diff --git a/hal/halmac/halmac_api.h b/hal/halmac/halmac_api.h index 03781a7..11a9e8c 100644 --- a/hal/halmac/halmac_api.h +++ b/hal/halmac/halmac_api.h @@ -1,26 +1,80 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_API_H_ #define _HALMAC_API_H_ -#define HALMAC_SVN_VER "13348M" +#define HALMAC_SVN_VER "11692M" + +#define HALMAC_MAJOR_VER 0x0001 +#define HALMAC_PROTOTYPE_VER 0x0005 +#define HALMAC_MINOR_VER 0x0000 +#define HALMAC_PATCH_VER 0x0002 + +#define HALMAC_88XX_SUPPORT (HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define HALMAC_MAJOR_VER 0x0001 /* major version, ver_1 for async_api */ -#define HALMAC_PROTOTYPE_VER 0x0003 /* For halmac_api num change or prototype change, increment prototype version */ -#define HALMAC_MINOR_VER 0x0006 /* else increment minor version */ -#define HALMAC_PATCH_VER 0x0002 /* patch version */ +#define HALMAC_88XX_V1_SUPPORT HALMAC_8814B_SUPPORT #include "halmac_2_platform.h" -#include "halmac_hw_cfg.h" #include "halmac_type.h" - +#include "halmac_hw_cfg.h" #include "halmac_usb_reg.h" #include "halmac_sdio_reg.h" #include "halmac_pcie_reg.h" - #include "halmac_bit2.h" #include "halmac_reg2.h" +#if HALMAC_PLATFORM_TESTPROGRAM +#include "halmac_type_testprogram.h" +#endif + +#ifndef HALMAC_USE_TYPEDEF +#define HALMAC_USE_TYPEDEF 1 +#endif + +#if HALMAC_USE_TYPEDEF +#include "halmac_typedef.h" +#endif + +#if HALMAC_8822B_SUPPORT +#include "halmac_reg_8822b.h" +#include "halmac_bit_8822b.h" +#endif + +#if HALMAC_8821C_SUPPORT +#include "halmac_reg_8821c.h" +#include "halmac_bit_8821c.h" +#endif + +#if HALMAC_8814B_SUPPORT +#include "halmac_reg_8814b.h" +#include "halmac_bit_8814b.h" +#endif + +#if HALMAC_8822C_SUPPORT +#include "halmac_reg_8822c.h" +#include "halmac_bit_8822c.h" +#endif + #if (HALMAC_PLATFORM_WINDOWS || HALMAC_PLATFORM_LINUX) #include "halmac_tx_desc_nic.h" +#include "halmac_tx_desc_buffer_nic.h" +#include "halmac_tx_desc_ie_nic.h" #include "halmac_rx_desc_nic.h" #include "halmac_tx_bd_nic.h" #include "halmac_rx_bd_nic.h" @@ -34,8 +88,8 @@ #if (HALMAC_PLATFORM_AP) #include "halmac_rx_desc_ap.h" #include "halmac_tx_desc_ap.h" -#include "halmac_rx_bd_ap.h" -#include "halmac_tx_bd_ap.h" +#include "halmac_tx_desc_buffer_ap.h" +#include "halmac_tx_desc_ie_ap.h" #include "halmac_fw_offload_c2h_ap.h" #include "halmac_fw_offload_h2c_ap.h" #include "halmac_h2c_extra_info_ap.h" @@ -45,55 +99,22 @@ #include "halmac_tx_desc_chip.h" #include "halmac_rx_desc_chip.h" -#include "halmac_tx_bd_chip.h" -#include "halmac_rx_bd_chip.h" -#if HALMAC_PLATFORM_WINDOWS == 1 - -#if HALMAC_8822B_SUPPORT -#include "halmac_88xx/halmac_win8822b_cfg.h" -#endif -#if HALMAC_8821C_SUPPORT -#include "halmac_88xx/halmac_win8821c_cfg.h" -#endif +#include "halmac_tx_desc_buffer_chip.h" +#include "halmac_tx_desc_ie_chip.h" -#else -#include "halmac_88xx/halmac_88xx_cfg.h" -#endif +enum halmac_ret_status +halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api, + enum halmac_interface intf, + struct halmac_adapter **halmac_adapter, + struct halmac_api **halmac_api); -#if HALMAC_8822B_SUPPORT -#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h" -#include "halmac_reg_8822b.h" -#include "halmac_bit_8822b.h" -#endif +enum halmac_ret_status +halmac_deinit_adapter(struct halmac_adapter *adapter); -#if HALMAC_8821C_SUPPORT -#include "halmac_88xx/halmac_8821c/halmac_8821c_cfg.h" -#include "halmac_reg_8821c.h" -#include "halmac_bit_8821c.h" -#endif +enum halmac_ret_status +halmac_halt_api(struct halmac_adapter *adapter); -HALMAC_RET_STATUS -halmac_init_adapter( - IN VOID *pDriver_adapter, - IN PHALMAC_PLATFORM_API pHalmac_platform_api, - IN HALMAC_INTERFACE halmac_interface, - OUT PHALMAC_ADAPTER *ppHalmac_adapter, - OUT PHALMAC_API *ppHalmac_api -); - -HALMAC_RET_STATUS -halmac_deinit_adapter( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_halt_api( - IN PHALMAC_ADAPTER pHalmac_adapter -); - -HALMAC_RET_STATUS -halmac_get_version( - OUT HALMAC_VER *version -); +enum halmac_ret_status +halmac_get_version(struct halmac_ver *version); #endif diff --git a/hal/halmac/halmac_bit2.h b/hal/halmac/halmac_bit2.h index a29d9a7..3ffd6cc 100644 --- a/hal/halmac/halmac_bit2.h +++ b/hal/halmac/halmac_bit2.h @@ -1,34880 +1,73023 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __RTL_WLAN_BITDEF_H__ #define __RTL_WLAN_BITDEF_H__ -/*-------------------------Modification Log----------------------------------- - Base on MAC_Register.doc SVN391 --------------------------Modification Log-----------------------------------*/ - -/*--------------------------Include File--------------------------------------*/ #include "halmac_hw_cfg.h" -/*--------------------------Include File--------------------------------------*/ -/* 3 ============Programming guide Start===================== */ -/* - 1. For all bit define, it should be prefixed by "BIT_" - 2. For all bit mask, it should be prefixed by "BIT_MASK_" - 3. For all bit shift, it should be prefixed by "BIT_SHIFT_" - 4. For other case, prefix is not needed +#define CPU_OPT_WIDTH 0x1F -Example: -#define BIT_SHIFT_MAX_TXDMA 16 -#define BIT_MASK_MAX_TXDMA 0x7 -#define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA)<> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA) +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) +#define BIT_WRITE_ENABLE BIT(31) -*/ -/* 3 ============Programming guide End===================== */ +#endif -#define CPU_OPT_WIDTH 0x1F +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#define BIT_MEM_RMV_SIGN BIT(31) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31) +#endif -#define BIT_SHIFT_WATCH_DOG_RECORD_V1 10 -#define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff -#define BIT_WATCH_DOG_RECORD_V1(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1) -#define BIT_GET_WATCH_DOG_RECORD_V1(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9) +#define BIT_SHIFT_LLTE_RWM 30 +#define BIT_MASK_LLTE_RWM 0x3 +#define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM) +#define BITS_LLTE_RWM (BIT_MASK_LLTE_RWM << BIT_SHIFT_LLTE_RWM) +#define BIT_CLEAR_LLTE_RWM(x) ((x) & (~BITS_LLTE_RWM)) +#define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM) +#define BIT_SET_LLTE_RWM(x, v) (BIT_CLEAR_LLTE_RWM(x) | BIT_LLTE_RWM(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - -#define BIT_EN_WATCH_DOG_V1 BIT(8) +#define BIT_MEM_RMV_2PRF1 BIT(29) +#define BIT_MEM_RMV_2PRF0 BIT(28) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define BIT_AFE_MBIAS BIT(1) +#define BIT_SHIFT_GTAB_ID 28 +#define BIT_MASK_GTAB_ID 0x7 +#define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID) +#define BITS_GTAB_ID (BIT_MASK_GTAB_ID << BIT_SHIFT_GTAB_ID) +#define BIT_CLEAR_GTAB_ID(x) ((x) & (~BITS_GTAB_ID)) +#define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID) +#define BIT_SET_GTAB_ID(x, v) (BIT_CLEAR_GTAB_ID(x) | BIT_GTAB_ID(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +#define BIT_MULRW BIT(27) + +#endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_ISO_MD2PP BIT(0) +#define BIT_MEM_RMV_1PRF1 BIT(27) +#define BIT_MEM_RMV_1PRF0 BIT(26) +#define BIT_MEM_RMV_1PSR BIT(25) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_MBIDCAM_ADDR 24 +#define BIT_MASK_MBIDCAM_ADDR 0x1f +#define BIT_MBIDCAM_ADDR(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR) +#define BITS_MBIDCAM_ADDR (BIT_MASK_MBIDCAM_ADDR << BIT_SHIFT_MBIDCAM_ADDR) +#define BIT_CLEAR_MBIDCAM_ADDR(x) ((x) & (~BITS_MBIDCAM_ADDR)) +#define BIT_GET_MBIDCAM_ADDR(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR) +#define BIT_SET_MBIDCAM_ADDR(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR(x) | BIT_MBIDCAM_ADDR(v)) +#endif -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) -#define BIT_GET_R_WMAC_IPV6_MYIPAD(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD) +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#define BIT_MEM_RMV_ROM BIT(24) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) + +#define BIT_CPRST BIT(23) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#define BIT_CTS_EN BIT(16) +#endif -#define BIT_SHIFT_SDIO_INT_TIMEOUT 16 -#define BIT_MASK_SDIO_INT_TIMEOUT 0xffff -#define BIT_SDIO_INT_TIMEOUT(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT) -#define BIT_GET_SDIO_INT_TIMEOUT(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT) +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) +#define BIT_SHIFT_R_OFDM_LEN_V1 16 +#define BIT_MASK_R_OFDM_LEN_V1 0xffff +#define BIT_R_OFDM_LEN_V1(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_V1) << BIT_SHIFT_R_OFDM_LEN_V1) +#define BITS_R_OFDM_LEN_V1 (BIT_MASK_R_OFDM_LEN_V1 << BIT_SHIFT_R_OFDM_LEN_V1) +#define BIT_CLEAR_R_OFDM_LEN_V1(x) ((x) & (~BITS_R_OFDM_LEN_V1)) +#define BIT_GET_R_OFDM_LEN_V1(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_V1) & BIT_MASK_R_OFDM_LEN_V1) +#define BIT_SET_R_OFDM_LEN_V1(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_V1(x) | BIT_R_OFDM_LEN_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_COUNTER_BASE 16 +#define BIT_MASK_COUNTER_BASE 0x1fff +#define BIT_COUNTER_BASE(x) \ + (((x) & BIT_MASK_COUNTER_BASE) << BIT_SHIFT_COUNTER_BASE) +#define BITS_COUNTER_BASE (BIT_MASK_COUNTER_BASE << BIT_SHIFT_COUNTER_BASE) +#define BIT_CLEAR_COUNTER_BASE(x) ((x) & (~BITS_COUNTER_BASE)) +#define BIT_GET_COUNTER_BASE(x) \ + (((x) >> BIT_SHIFT_COUNTER_BASE) & BIT_MASK_COUNTER_BASE) +#define BIT_SET_COUNTER_BASE(x, v) \ + (BIT_CLEAR_COUNTER_BASE(x) | BIT_COUNTER_BASE(v)) +#define BIT_SHIFT_AGG_VALUE2 16 +#define BIT_MASK_AGG_VALUE2 0x7f +#define BIT_AGG_VALUE2(x) (((x) & BIT_MASK_AGG_VALUE2) << BIT_SHIFT_AGG_VALUE2) +#define BITS_AGG_VALUE2 (BIT_MASK_AGG_VALUE2 << BIT_SHIFT_AGG_VALUE2) +#define BIT_CLEAR_AGG_VALUE2(x) ((x) & (~BITS_AGG_VALUE2)) +#define BIT_GET_AGG_VALUE2(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE2) & BIT_MASK_AGG_VALUE2) +#define BIT_SET_AGG_VALUE2(x, v) (BIT_CLEAR_AGG_VALUE2(x) | BIT_AGG_VALUE2(v)) -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_PWC_EV12V BIT(15) +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#define BIT_SHIFT_XTAL_DRV_RF1 13 +#define BIT_MASK_XTAL_DRV_RF1 0x3 +#define BIT_XTAL_DRV_RF1(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1) +#define BITS_XTAL_DRV_RF1 (BIT_MASK_XTAL_DRV_RF1 << BIT_SHIFT_XTAL_DRV_RF1) +#define BIT_CLEAR_XTAL_DRV_RF1(x) ((x) & (~BITS_XTAL_DRV_RF1)) +#define BIT_GET_XTAL_DRV_RF1(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1) +#define BIT_SET_XTAL_DRV_RF1(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF1(x) | BIT_XTAL_DRV_RF1(v)) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_PWC_EBCOEB BIT(15) +#define BIT_DISABLE_B0 BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_ATIMEND BIT(12) +#endif -/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_IO_ERR_STATUS BIT(15) +#define BIT_SHIFT_GTAB_ID_V1 12 +#define BIT_MASK_GTAB_ID_V1 0x7 +#define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1) +#define BITS_GTAB_ID_V1 (BIT_MASK_GTAB_ID_V1 << BIT_SHIFT_GTAB_ID_V1) +#define BIT_CLEAR_GTAB_ID_V1(x) ((x) & (~BITS_GTAB_ID_V1)) +#define BIT_GET_GTAB_ID_V1(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1) +#define BIT_SET_GTAB_ID_V1(x, v) (BIT_CLEAR_GTAB_ID_V1(x) | BIT_GTAB_ID_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_WATCH_DOG_RECORD_V1 10 +#define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff +#define BIT_WATCH_DOG_RECORD_V1(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1) +#define BITS_WATCH_DOG_RECORD_V1 \ + (BIT_MASK_WATCH_DOG_RECORD_V1 << BIT_SHIFT_WATCH_DOG_RECORD_V1) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1(x) ((x) & (~BITS_WATCH_DOG_RECORD_V1)) +#define BIT_GET_WATCH_DOG_RECORD_V1(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1) +#define BIT_SET_WATCH_DOG_RECORD_V1(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1(x) | BIT_WATCH_DOG_RECORD_V1(v)) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_PWC_EV25V BIT(14) +#define BIT_R_8051_SPD BIT(9) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_PA33V_EN BIT(13) -#define BIT_PA12V_EN BIT(12) +#define BIT_EN_RTS_REQ BIT(9) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#define BIT_EN_WATCH_DOG_V1 BIT(8) + +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_EN_EDCA_REQ BIT(8) -#define BIT_PC_A15V BIT(12) +#define BIT_SHIFT_AGG_VALUE1 8 +#define BIT_MASK_AGG_VALUE1 0x7f +#define BIT_AGG_VALUE1(x) (((x) & BIT_MASK_AGG_VALUE1) << BIT_SHIFT_AGG_VALUE1) +#define BITS_AGG_VALUE1 (BIT_MASK_AGG_VALUE1 << BIT_SHIFT_AGG_VALUE1) +#define BIT_CLEAR_AGG_VALUE1(x) ((x) & (~BITS_AGG_VALUE1)) +#define BIT_GET_AGG_VALUE1(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE1) & BIT_MASK_AGG_VALUE1) +#define BIT_SET_AGG_VALUE1(x, v) (BIT_CLEAR_AGG_VALUE1(x) | BIT_AGG_VALUE1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_DIS_TXDMA_PRE BIT(7) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_UA33V_EN BIT(11) -#define BIT_UA12V_EN BIT(10) +#define BIT_RAM_DL_SEL BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#define BIT_EN_PTCL_REQ BIT(7) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_ISO_AFE_OUTPUT_SIGNAL BIT(10) +#define BIT_DIS_RXDMA_PRE BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_WINTINI_RDY BIT(6) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_ISO_RFDIO BIT(9) +#define BIT_EN_SCH_REQ BIT(6) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_CLR_HGQ_REQ_BLOCK BIT(5) +#endif -/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_REPLY_ERRCRC_IN_DATA BIT(9) +#define BIT_TXFLAG_EXIT_L1_EN BIT(2) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_DATA_FW_STS_FILTER BIT(2) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_ISO_EB2CORE BIT(8) +#define BIT_EN_RXDMA_ALIGN_V1 BIT(1) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_CTRL_FW_STS_FILTER BIT(1) +#endif -/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#if (HALMAC_8881A_SUPPORT) -#define BIT_EN_CMD53_OVERLAP BIT(8) +#define BIT_AFE_MBIAS BIT(1) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_MDIO_REG_ADDR 0 +#define BIT_MASK_MDIO_REG_ADDR 0x1f +#define BIT_MDIO_REG_ADDR(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR) << BIT_SHIFT_MDIO_REG_ADDR) +#define BITS_MDIO_REG_ADDR (BIT_MASK_MDIO_REG_ADDR << BIT_SHIFT_MDIO_REG_ADDR) +#define BIT_CLEAR_MDIO_REG_ADDR(x) ((x) & (~BITS_MDIO_REG_ADDR)) +#define BIT_GET_MDIO_REG_ADDR(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR) & BIT_MASK_MDIO_REG_ADDR) +#define BIT_SET_MDIO_REG_ADDR(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR(x) | BIT_MDIO_REG_ADDR(v)) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_ISO_DIOE BIT(7) +#define BIT_EN_TXDMA_ALIGN_V1 BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_AGG_VALUE0 0 +#define BIT_MASK_AGG_VALUE0 0x7f +#define BIT_AGG_VALUE0(x) (((x) & BIT_MASK_AGG_VALUE0) << BIT_SHIFT_AGG_VALUE0) +#define BITS_AGG_VALUE0 (BIT_MASK_AGG_VALUE0 << BIT_SHIFT_AGG_VALUE0) +#define BIT_CLEAR_AGG_VALUE0(x) ((x) & (~BITS_AGG_VALUE0)) +#define BIT_GET_AGG_VALUE0(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE0) & BIT_MASK_AGG_VALUE0) +#define BIT_SET_AGG_VALUE0(x, v) (BIT_CLEAR_AGG_VALUE0(x) | BIT_AGG_VALUE0(v)) +#endif -/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_REPLY_ERR_IN_R5 BIT(7) +#define BIT_SHIFT_BW_CFG 0 +#define BIT_MASK_BW_CFG 0x3 +#define BIT_BW_CFG(x) (((x) & BIT_MASK_BW_CFG) << BIT_SHIFT_BW_CFG) +#define BITS_BW_CFG (BIT_MASK_BW_CFG << BIT_SHIFT_BW_CFG) +#define BIT_CLEAR_BW_CFG(x) ((x) & (~BITS_BW_CFG)) +#define BIT_GET_BW_CFG(x) (((x) >> BIT_SHIFT_BW_CFG) & BIT_MASK_BW_CFG) +#define BIT_SET_BW_CFG(x, v) (BIT_CLEAR_BW_CFG(x) | BIT_BW_CFG(v)) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_MGNT_FW_STS_FILTER BIT(0) +#endif -/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_ISO_DIOP BIT(6) +#define BIT_ISO_MD2PP BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ + +#define BIT_SHIFT_SDIO_INT_TIMEOUT 16 +#define BIT_MASK_SDIO_INT_TIMEOUT 0xffff +#define BIT_SDIO_INT_TIMEOUT(x) \ + (((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT) +#define BITS_SDIO_INT_TIMEOUT \ + (BIT_MASK_SDIO_INT_TIMEOUT << BIT_SHIFT_SDIO_INT_TIMEOUT) +#define BIT_CLEAR_SDIO_INT_TIMEOUT(x) ((x) & (~BITS_SDIO_INT_TIMEOUT)) +#define BIT_GET_SDIO_INT_TIMEOUT(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT) +#define BIT_SET_SDIO_INT_TIMEOUT(x, v) \ + (BIT_CLEAR_SDIO_INT_TIMEOUT(x) | BIT_SDIO_INT_TIMEOUT(v)) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_WLPON2PP BIT(6) +#define BIT_PWC_EV12V BIT(15) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ + +#define BIT_PWC_ON2EF BIT(15) + +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_R18A_EN BIT(6) +#define BIT_IO_ERR_STATUS BIT(15) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ + +#define BIT_PWC_EBCOEB BIT(15) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_IP2MAC_WA2PP BIT(5) +#define BIT_PWC_EV25V BIT(14) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_PWC_EV2EF BIT(14) -/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#endif -#define BIT_INIT_CMD_EN BIT(5) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#define BIT_CMD53_W_MIX BIT(14) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_PD2CORE BIT(4) +#define BIT_PA33V_EN BIT(13) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ + +#define BIT_CMD53_TX_FORMAT BIT(13) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_PA2PCIE BIT(3) +#define BIT_PA12V_EN BIT(12) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_EN_32K_TRANS BIT(3) +#define BIT_CMD53_R_TIMEOUT_MASK BIT(12) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_UD2CORE BIT(2) +#define BIT_PC_A15V BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ + +#define BIT_UA33V_EN BIT(11) +#define BIT_UA12V_EN BIT(10) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_EN_RXDMA_MASK_INT BIT(2) +#define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT 10 +#define BIT_MASK_CMD53_R_TIMEOUT_UNIT 0x3 +#define BIT_CMD53_R_TIMEOUT_UNIT(x) \ + (((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT) \ + << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) +#define BITS_CMD53_R_TIMEOUT_UNIT \ + (BIT_MASK_CMD53_R_TIMEOUT_UNIT << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) +#define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) ((x) & (~BITS_CMD53_R_TIMEOUT_UNIT)) +#define BIT_GET_CMD53_R_TIMEOUT_UNIT(x) \ + (((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) & \ + BIT_MASK_CMD53_R_TIMEOUT_UNIT) +#define BIT_SET_CMD53_R_TIMEOUT_UNIT(x, v) \ + (BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) | BIT_CMD53_R_TIMEOUT_UNIT(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ + +#define BIT_ISO_AFE_OUTPUT_SIGNAL BIT(10) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_HD2CORE BIT(2) +#define BIT_ISO_RFDIO BIT(9) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ + +#define BIT_REPLY_ERRCRC_IN_DATA BIT(9) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_UA2USB BIT(1) +#define BIT_ISO_EB2CORE BIT(8) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ + +#define BIT_ISO_EF2PP BIT(8) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_EN_MASK_TIMER BIT(1) +#define BIT_EN_CMD53_OVERLAP BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ISO_WD2PP BIT(0) +#define BIT_ISO_DIOE BIT(7) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ + +#define BIT_ISO_EXTIO BIT(7) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_CMD_ERR_STOP_INT_EN BIT(0) +#define BIT_REPLY_ERR_IN_R5 BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_DIOP BIT(6) -/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#endif -#define BIT_FEN_MREGEN BIT(15) -#define BIT_FEN_HWPDN BIT(14) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_WLPON2PP BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_EN_25_1 BIT(13) +#define BIT_R18A_EN BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_IP2MAC_WA2PP BIT(5) -/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_FEN_ELDR BIT(12) -#define BIT_FEN_DCORE BIT(11) -#define BIT_FEN_CPUEN BIT(10) -#define BIT_FEN_DIOE BIT(9) -#define BIT_FEN_PCIED BIT(8) -#define BIT_FEN_PPLL BIT(7) -#define BIT_FEN_PCIEA BIT(6) -#define BIT_FEN_DIO_PCIE BIT(5) -#define BIT_FEN_USBD BIT(4) -#define BIT_FEN_UPLL BIT(3) -#define BIT_FEN_USBA BIT(2) +#define BIT_ISO_WA2PP BIT(5) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#define BIT_SDIO_CMD_FORCE_VLD BIT(5) -/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#endif -#define BIT_FEN_BB_GLB_RSTN BIT(1) -#define BIT_FEN_BBRSTB BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_SOP_EABM BIT(31) +#define BIT_ISO_PD2CORE BIT(4) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_PD2PP BIT(4) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#endif -#define BIT_SKP_ALD BIT(31) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#define BIT_INIT_CMD_EN BIT(4) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_SOP_ACKF BIT(30) -#define BIT_SOP_ERCK BIT(29) +#define BIT_ISO_PA2PCIE BIT(3) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_PA2PD BIT(3) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#endif -#define BIT_SOP_ESWR BIT(28) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#define BIT_RXINT_READ_MASK_DIS BIT(3) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_SOP_AFEP BIT(28) +#define BIT_EN_32K_TRANS BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_UD2CORE BIT(2) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#endif -#define BIT_SOP_PWMM BIT(27) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_UD2PP BIT(2) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ -#define BIT_SOP_EPWM BIT(27) +#define BIT_EN_RXDMA_MASK_INT BIT(2) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_HD2CORE BIT(2) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#endif -#define BIT_SOP_EECK BIT(26) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_UA2USB BIT(1) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_ROP_ENXT BIT(25) +#define BIT_ISO_UA2UD BIT(1) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#define BIT_EN_MASK_TIMER BIT(1) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#endif -#define BIT_SOP_EXTL BIT(24) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ +#define BIT_ISO_WD2PP BIT(0) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ -#define BIT_CHIPOFF_EN BIT(23) +#define BIT_ISO_WL2PP BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ +#define BIT_CMD_ERR_STOP_INT_EN BIT(0) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#endif -#define BIT_SYM_OP_RING_12M BIT(22) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#define BIT_FEN_MREGEN BIT(15) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ -#define BIT_DIS_USB3_SUS_ALD BIT(22) +#define BIT_FEN_WLMACPON BIT(15) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#define BIT_FEN_HWPDN BIT(14) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#endif -#define BIT_ROP_SWPR BIT(21) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#define BIT_AIP_PD12_N BIT(14) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ -#define BIT_DIS_HW_LPLDM BIT(20) +#define BIT_EN_25_1 BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#define BIT_FEN_ELDR BIT(12) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#endif -#define BIT_SOP_ALD BIT(20) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#define BIT_FEN_DCORE BIT(11) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ -#define BIT_OPT_SWRST_WLMCU BIT(19) -#define BIT_RDY_SYSPWR BIT(17) +#define BIT_FEN_WLMACPOF BIT(11) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#define BIT_FEN_CPUEN BIT(10) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#endif -#define BIT_EN_WLON BIT(16) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#define BIT_FEN_DIOE BIT(9) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ -#define BIT_APDM_HPDN BIT(15) +#define BIT_FEN_EXTIO BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#define BIT_FEN_PCIED BIT(8) +#define BIT_FEN_PPLL BIT(7) +#define BIT_FEN_PCIEA BIT(6) +#define BIT_FEN_DIO_PCIE BIT(5) +#define BIT_FEN_USBD BIT(4) +#define BIT_FEN_UPLL BIT(3) +#define BIT_FEN_USBA BIT(2) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#endif -#define BIT_HSUS BIT(14) -#define BIT_PDN_SEL BIT(13) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#define BIT_FEN_BB_GLB_RSTN BIT(1) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ -#define BIT_AFSM_PCIE_SUS_EN BIT(12) +#define BIT_FEN_WLPHYGLB BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#define BIT_FEN_BBRSTB BIT(0) -/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#endif -#define BIT_AFSM_WLSUS_EN BIT(11) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ +#define BIT_FEN_WLPHYFUN BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_APFM_SWLPS BIT(10) +#define BIT_SOP_EABM BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_APFM_SWLPS_EN BIT(10) +#define BIT_SKP_ALD BIT(31) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_APFM_OFFMAC BIT(9) -#define BIT_APFN_ONMAC BIT(8) +#define BIT_SOP_ACKF BIT(30) +#define BIT_SOP_ERCK BIT(29) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_CHIP_PDN_EN BIT(7) +#define BIT_SOP_ESWR BIT(28) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_BT_SUSEN BIT(7) +#define BIT_SOP_AFEP BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_RDY_MACDIS BIT(6) +#define BIT_SOP_PWMM BIT(27) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_PD_RF BIT(5) +#define BIT_SOP_EPWM BIT(27) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_RING_CLK_12M_EN BIT(4) +#define BIT_SOP_EECK BIT(26) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_ENPDN BIT(4) +#define BIT_PMC_RATIO_BIT2 BIT(25) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_PFM_WOWL BIT(3) +#define BIT_SOP_ANA_CLK_DIVISION_2 BIT(25) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SW_WAKE BIT(3) +#define BIT_ROP_ENXT BIT(25) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_PFM_LDKP BIT(2) +#define BIT_SOP_EXTL BIT(24) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_WL_HCI_ALD BIT(1) +#define BIT_PMC_RATIO_BIT1 BIT(23) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_PFM_ALDN BIT(1) +#define BIT_CHIPOFF_EN BIT(23) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_PFM_LDALL BIT(0) +#define BIT_SYM_OP_RING_12M BIT(22) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_LDO_DUMMY BIT(15) +#define BIT_DIS_USB3_SUS_ALD BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_ANA_CLK_EN BIT(15) +#define BIT_ROP_SWPR BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_DIS_HW_LPLDM BIT(20) -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#endif -#define BIT_CPU_CLK_EN BIT(14) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_SOP_ALD BIT(20) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SYMREG_CLK_EN BIT(13) +#define BIT_OPT_SWRST_WLMCU BIT(19) +#define BIT_RDY_SYSPWR BIT(17) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_EN_WLON BIT(16) -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#endif -#define BIT_RING_CLK_EN BIT(13) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_APDM_HPDN BIT(15) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_HCI_CLK_EN BIT(12) +#define BIT_PMC_RATIO_BIT0 BIT(14) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ - -#define BIT_SYS_CLK_EN BIT(12) +#define BIT_HSUS BIT(14) +#define BIT_PDN_SEL BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_AFSM_PCIE_SUS_EN BIT(12) -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#endif -#define BIT_MAC_CLK_EN BIT(11) -#define BIT_SEC_CLK_EN BIT(10) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_AFSM_WLSUS_EN BIT(11) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_PHY_SSC_RSTB BIT(9) -#define BIT_EXT_32K_EN BIT(8) +#define BIT_APFM_SWLPS BIT(10) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ - -#define BIT_EXT32K_EN BIT(8) +#define BIT_APFM_SWLPS_EN BIT(10) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_WL_CLK_TEST BIT(7) -#define BIT_OP_SPS_PWM_EN BIT(6) +#define BIT_APFM_OFFMAC BIT(9) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_HW_AUTO_CTRL_EXT_SWR BIT(9) -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MAC_CLK_SEL_V1 6 -#define BIT_MASK_MAC_CLK_SEL_V1 0x3 -#define BIT_MAC_CLK_SEL_V1(x) (((x) & BIT_MASK_MAC_CLK_SEL_V1) << BIT_SHIFT_MAC_CLK_SEL_V1) -#define BIT_GET_MAC_CLK_SEL_V1(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_V1) & BIT_MASK_MAC_CLK_SEL_V1) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_APFN_ONMAC BIT(8) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_LOADER_CLK_EN BIT(5) -#define BIT_MACSLP BIT(4) -#define BIT_WAKEPAD_EN BIT(3) -#define BIT_ROMD16V_EN BIT(2) +#define BIT_USE_INTERNAL_SWR_AND_LDO BIT(8) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_CHIP_PDN_EN BIT(7) -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#endif -#define BIT_CKANA8M_EN BIT(1) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_BT_SUSEN BIT(7) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_CKANA12M_EN BIT(1) +#define BIT_RDY_MACDIS BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ - -#define BIT_ANA8M_EN BIT(1) +#define BIT_PD_RF BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_RING_CLK_12M_EN BIT(4) -/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#endif -#define BIT_CNTD16V_EN BIT(0) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +/* 2 REG_SDIO_CMD11_VOL_SWITCH (Offset 0x10250004) */ +#define BIT_SHIFT_CMD11_SEQ_END_DELAY 4 +#define BIT_MASK_CMD11_SEQ_END_DELAY 0xf +#define BIT_CMD11_SEQ_END_DELAY(x) \ + (((x) & BIT_MASK_CMD11_SEQ_END_DELAY) << BIT_SHIFT_CMD11_SEQ_END_DELAY) +#define BITS_CMD11_SEQ_END_DELAY \ + (BIT_MASK_CMD11_SEQ_END_DELAY << BIT_SHIFT_CMD11_SEQ_END_DELAY) +#define BIT_CLEAR_CMD11_SEQ_END_DELAY(x) ((x) & (~BITS_CMD11_SEQ_END_DELAY)) +#define BIT_GET_CMD11_SEQ_END_DELAY(x) \ + (((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY) & BIT_MASK_CMD11_SEQ_END_DELAY) +#define BIT_SET_CMD11_SEQ_END_DELAY(x, v) \ + (BIT_CLEAR_CMD11_SEQ_END_DELAY(x) | BIT_CMD11_SEQ_END_DELAY(v)) -#define BIT_SHIFT_VPDIDX 8 -#define BIT_MASK_VPDIDX 0xff -#define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX) -#define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_EEM1_0 6 -#define BIT_MASK_EEM1_0 0x3 -#define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0) -#define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_AUTOLOAD_SUS BIT(5) +#define BIT_ENPDN BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_EERPOMSEL BIT(4) +#define BIT_PFM_WOWL BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ - -#define BIT_EEPROMSEL BIT(4) +#define BIT_SW_WAKE BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_EECS_V1 BIT(3) -#define BIT_EESK_V1 BIT(2) -#define BIT_EEDI_V1 BIT(1) -#define BIT_EEDO_V1 BIT(0) +#define BIT_PFM_LDKP BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_WL_HCI_ALD BIT(1) -/* 2 REG_EE_VPD (Offset 0x000C) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -#define BIT_SHIFT_VPD_DATA 0 -#define BIT_MASK_VPD_DATA 0xffffffffL -#define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA) -#define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA) +#define BIT_ANA_CLK_DIVISION_2 BIT(1) +#define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL 1 +#define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL 0x7 +#define BIT_CMD11_SEQ_SAMPLE_INTERVAL(x) \ + (((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL) \ + << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) +#define BITS_CMD11_SEQ_SAMPLE_INTERVAL \ + (BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL \ + << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) +#define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x) \ + ((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL)) +#define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL(x) \ + (((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) & \ + BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL) +#define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL(x, v) \ + (BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x) | \ + BIT_CMD11_SEQ_SAMPLE_INTERVAL(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ -/* 2 REG_EE_VPD (Offset 0x000C) */ +#define BIT_PFM_ALDN BIT(1) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VDP_DATA 0 -#define BIT_MASK_VDP_DATA 0xffffffffL -#define BIT_VDP_DATA(x) (((x) & BIT_MASK_VDP_DATA) << BIT_SHIFT_VDP_DATA) -#define BIT_GET_VDP_DATA(x) (((x) >> BIT_SHIFT_VDP_DATA) & BIT_MASK_VDP_DATA) +/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ +#define BIT_PFM_LDALL BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_SDIO_CMD11_VOL_SWITCH (Offset 0x10250004) */ -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_CMD11_SEQ_EN BIT(0) -#define BIT_SW18_C2_BIT0 BIT(31) +/* 2 REG_SDIO_CTRL (Offset 0x10250005) */ -#endif +#define BIT_SIG_OUT_PH BIT(0) +/* 2 REG_SDIO_DRIVING (Offset 0x10250006) */ -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_SDIO_DRV_TYPE_D 12 +#define BIT_MASK_SDIO_DRV_TYPE_D 0xf +#define BIT_SDIO_DRV_TYPE_D(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_D) << BIT_SHIFT_SDIO_DRV_TYPE_D) +#define BITS_SDIO_DRV_TYPE_D \ + (BIT_MASK_SDIO_DRV_TYPE_D << BIT_SHIFT_SDIO_DRV_TYPE_D) +#define BIT_CLEAR_SDIO_DRV_TYPE_D(x) ((x) & (~BITS_SDIO_DRV_TYPE_D)) +#define BIT_GET_SDIO_DRV_TYPE_D(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D) & BIT_MASK_SDIO_DRV_TYPE_D) +#define BIT_SET_SDIO_DRV_TYPE_D(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_D(x) | BIT_SDIO_DRV_TYPE_D(v)) +#define BIT_SHIFT_SDIO_DRV_TYPE_C 8 +#define BIT_MASK_SDIO_DRV_TYPE_C 0xf +#define BIT_SDIO_DRV_TYPE_C(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_C) << BIT_SHIFT_SDIO_DRV_TYPE_C) +#define BITS_SDIO_DRV_TYPE_C \ + (BIT_MASK_SDIO_DRV_TYPE_C << BIT_SHIFT_SDIO_DRV_TYPE_C) +#define BIT_CLEAR_SDIO_DRV_TYPE_C(x) ((x) & (~BITS_SDIO_DRV_TYPE_C)) +#define BIT_GET_SDIO_DRV_TYPE_C(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C) & BIT_MASK_SDIO_DRV_TYPE_C) +#define BIT_SET_SDIO_DRV_TYPE_C(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_C(x) | BIT_SDIO_DRV_TYPE_C(v)) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_SDIO_DRV_TYPE_B 4 +#define BIT_MASK_SDIO_DRV_TYPE_B 0xf +#define BIT_SDIO_DRV_TYPE_B(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_B) << BIT_SHIFT_SDIO_DRV_TYPE_B) +#define BITS_SDIO_DRV_TYPE_B \ + (BIT_MASK_SDIO_DRV_TYPE_B << BIT_SHIFT_SDIO_DRV_TYPE_B) +#define BIT_CLEAR_SDIO_DRV_TYPE_B(x) ((x) & (~BITS_SDIO_DRV_TYPE_B)) +#define BIT_GET_SDIO_DRV_TYPE_B(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B) & BIT_MASK_SDIO_DRV_TYPE_B) +#define BIT_SET_SDIO_DRV_TYPE_B(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_B(x) | BIT_SDIO_DRV_TYPE_B(v)) -#define BIT_C2_L_BIT0 BIT(31) +#define BIT_SHIFT_SDIO_DRV_TYPE_A 0 +#define BIT_MASK_SDIO_DRV_TYPE_A 0xf +#define BIT_SDIO_DRV_TYPE_A(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_A) << BIT_SHIFT_SDIO_DRV_TYPE_A) +#define BITS_SDIO_DRV_TYPE_A \ + (BIT_MASK_SDIO_DRV_TYPE_A << BIT_SHIFT_SDIO_DRV_TYPE_A) +#define BIT_CLEAR_SDIO_DRV_TYPE_A(x) ((x) & (~BITS_SDIO_DRV_TYPE_A)) +#define BIT_GET_SDIO_DRV_TYPE_A(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A) & BIT_MASK_SDIO_DRV_TYPE_A) +#define BIT_SET_SDIO_DRV_TYPE_A(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_A(x) | BIT_SDIO_DRV_TYPE_A(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_CPHY_LDO_CL_EN BIT(19) +#define BIT_CPHY_LDO_OK BIT(18) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R1_L1_V1 30 -#define BIT_MASK_R1_L1_V1 0x3 -#define BIT_R1_L1_V1(x) (((x) & BIT_MASK_R1_L1_V1) << BIT_SHIFT_R1_L1_V1) -#define BIT_GET_R1_L1_V1(x) (((x) >> BIT_SHIFT_R1_L1_V1) & BIT_MASK_R1_L1_V1) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_LDO_DUMMY BIT(15) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_ANA_CLK_EN BIT(15) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_SW18_C1 29 -#define BIT_MASK_SW18_C1 0x3 -#define BIT_SW18_C1(x) (((x) & BIT_MASK_SW18_C1) << BIT_SHIFT_SW18_C1) -#define BIT_GET_SW18_C1(x) (((x) >> BIT_SHIFT_SW18_C1) & BIT_MASK_SW18_C1) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_DATA_CPU_CLK_EN BIT(15) +#define BIT_DATA_CPU_PWC BIT(15) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_CPU_CLK_EN BIT(14) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_C1_L 29 -#define BIT_MASK_C1_L 0x3 -#define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L) -#define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_SYMREG_CLK_EN BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ - +#define BIT_RING_CLK_EN BIT(13) -#define BIT_SHIFT_C3_L1_V1 28 -#define BIT_MASK_C3_L1_V1 0x3 -#define BIT_C3_L1_V1(x) (((x) & BIT_MASK_C3_L1_V1) << BIT_SHIFT_C3_L1_V1) -#define BIT_GET_C3_L1_V1(x) (((x) >> BIT_SHIFT_C3_L1_V1) & BIT_MASK_C3_L1_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_C2_L1_V1 26 -#define BIT_MASK_C2_L1_V1 0x3 -#define BIT_C2_L1_V1(x) (((x) & BIT_MASK_C2_L1_V1) << BIT_SHIFT_C2_L1_V1) -#define BIT_GET_C2_L1_V1(x) (((x) >> BIT_SHIFT_C2_L1_V1) & BIT_MASK_C2_L1_V1) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_HCI_CLK_EN BIT(12) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_SYS_CLK_EN BIT(12) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_REG_FREQ_L 25 -#define BIT_MASK_REG_FREQ_L 0x7 -#define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L) -#define BIT_GET_REG_FREQ_L(x) (((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_REG_EN_DUTY BIT(24) +#define BIT_MAC_CLK_EN BIT(11) +#define BIT_SEC_CLK_EN BIT(10) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_CTRL_SPS_PWM_FREQ BIT(10) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_C1_L1_V1 24 -#define BIT_MASK_C1_L1_V1 0x3 -#define BIT_C1_L1_V1(x) (((x) & BIT_MASK_C1_L1_V1) << BIT_SHIFT_C1_L1_V1) -#define BIT_GET_C1_L1_V1(x) (((x) >> BIT_SHIFT_C1_L1_V1) & BIT_MASK_C1_L1_V1) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_REG_TYPE_L_V3 BIT(23) +#define BIT_PHY_SSC_RSTB BIT(9) +#define BIT_EXT_32K_EN BIT(8) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_EXT32K_EN BIT(8) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_REG_MODE 22 -#define BIT_MASK_REG_MODE 0x3 -#define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE) -#define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_DISABLE_OPEN_SPS_LDO BIT(8) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_FPWM_L1_V1 BIT(22) +#define BIT_WL_CLK_TEST BIT(7) +#define BIT_OP_SPS_PWM_EN BIT(6) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_SHIFT_MAC_CLK_SEL_V1 6 +#define BIT_MASK_MAC_CLK_SEL_V1 0x3 +#define BIT_MAC_CLK_SEL_V1(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_V1) << BIT_SHIFT_MAC_CLK_SEL_V1) +#define BITS_MAC_CLK_SEL_V1 \ + (BIT_MASK_MAC_CLK_SEL_V1 << BIT_SHIFT_MAC_CLK_SEL_V1) +#define BIT_CLEAR_MAC_CLK_SEL_V1(x) ((x) & (~BITS_MAC_CLK_SEL_V1)) +#define BIT_GET_MAC_CLK_SEL_V1(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_V1) & BIT_MASK_MAC_CLK_SEL_V1) +#define BIT_SET_MAC_CLK_SEL_V1(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_V1(x) | BIT_MAC_CLK_SEL_V1(v)) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif -#define BIT_REG_EN_SP BIT(21) -#define BIT_REG_AUTO_L BIT(20) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_LOADER_CLK_EN BIT(5) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_SW18_SELD_BIT0 BIT(19) +#define BIT_POW_PC_LDO3 BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_MACSLP BIT(4) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_V15ADJ_L1 19 -#define BIT_MASK_V15ADJ_L1 0x7 -#define BIT_V15ADJ_L1(x) (((x) & BIT_MASK_V15ADJ_L1) << BIT_SHIFT_V15ADJ_L1) -#define BIT_GET_V15ADJ_L1(x) (((x) >> BIT_SHIFT_V15ADJ_L1) & BIT_MASK_V15ADJ_L1) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_POW_PC_LDO2 BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ + +#define BIT_WAKEPAD_EN BIT(3) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ -#define BIT_SW18_POWOCP BIT(18) +#define BIT_ENB_LDO_DIODE_L BIT(3) +#define BIT_POW_PC_LDO1 BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_ROMD16V_EN BIT(2) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_IN_L1 16 -#define BIT_MASK_IN_L1 0x7 -#define BIT_IN_L1(x) (((x) & BIT_MASK_IN_L1) << BIT_SHIFT_IN_L1) -#define BIT_GET_IN_L1(x) (((x) >> BIT_SHIFT_IN_L1) & BIT_MASK_IN_L1) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_AFE_BGEN_PCIE_OP BIT(2) +#define BIT_POW_PC_LDO0 BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_CKANA8M_EN BIT(1) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_SW18_OCP 15 -#define BIT_MASK_SW18_OCP 0x7 -#define BIT_SW18_OCP(x) (((x) & BIT_MASK_SW18_OCP) << BIT_SHIFT_SW18_OCP) -#define BIT_GET_SW18_OCP(x) (((x) >> BIT_SHIFT_SW18_OCP) & BIT_MASK_SW18_OCP) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_CKANA12M_EN BIT(1) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_ANA8M_EN BIT(1) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_OCP_L1 15 -#define BIT_MASK_OCP_L1 0x7 -#define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1) -#define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_CNTD16V_EN BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_MONITOR (Offset 0x10250008) */ +#define BIT_SHIFT_SDIO_INT_START 0 +#define BIT_MASK_SDIO_INT_START 0xffffffffL +#define BIT_SDIO_INT_START(x) \ + (((x) & BIT_MASK_SDIO_INT_START) << BIT_SHIFT_SDIO_INT_START) +#define BITS_SDIO_INT_START \ + (BIT_MASK_SDIO_INT_START << BIT_SHIFT_SDIO_INT_START) +#define BIT_CLEAR_SDIO_INT_START(x) ((x) & (~BITS_SDIO_INT_START)) +#define BIT_GET_SDIO_INT_START(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_START) & BIT_MASK_SDIO_INT_START) +#define BIT_SET_SDIO_INT_START(x, v) \ + (BIT_CLEAR_SDIO_INT_START(x) | BIT_SDIO_INT_START(v)) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_STD_L1 14 -#define BIT_MASK_STD_L1 0x3 -#define BIT_STD_L1(x) (((x) & BIT_MASK_STD_L1) << BIT_SHIFT_STD_L1) -#define BIT_GET_STD_L1(x) (((x) >> BIT_SHIFT_STD_L1) & BIT_MASK_STD_L1) +/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ +#define BIT_POW_POWER_CUT BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_VPDIDX 8 +#define BIT_MASK_VPDIDX 0xff +#define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX) +#define BITS_VPDIDX (BIT_MASK_VPDIDX << BIT_SHIFT_VPDIDX) +#define BIT_CLEAR_VPDIDX(x) ((x) & (~BITS_VPDIDX)) +#define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX) +#define BIT_SET_VPDIDX(x, v) (BIT_CLEAR_VPDIDX(x) | BIT_VPDIDX(v)) +#define BIT_SHIFT_EEM1_0 6 +#define BIT_MASK_EEM1_0 0x3 +#define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0) +#define BITS_EEM1_0 (BIT_MASK_EEM1_0 << BIT_SHIFT_EEM1_0) +#define BIT_CLEAR_EEM1_0(x) ((x) & (~BITS_EEM1_0)) +#define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0) +#define BIT_SET_EEM1_0(x, v) (BIT_CLEAR_EEM1_0(x) | BIT_EEM1_0(v)) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_AUTOLOAD_SUS BIT(5) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CF_L_BIT0_TO_1 13 -#define BIT_MASK_CF_L_BIT0_TO_1 0x3 -#define BIT_CF_L_BIT0_TO_1(x) (((x) & BIT_MASK_CF_L_BIT0_TO_1) << BIT_SHIFT_CF_L_BIT0_TO_1) -#define BIT_GET_CF_L_BIT0_TO_1(x) (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1) & BIT_MASK_CF_L_BIT0_TO_1) +/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +#define BIT_EERPOMSEL BIT(4) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +#define BIT_EEPROMSEL BIT(4) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CF_L 13 -#define BIT_MASK_CF_L 0x3 -#define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L) -#define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L) +/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ +#define BIT_EECS_V1 BIT(3) +#define BIT_EESK_V1 BIT(2) +#define BIT_EEDI_V1 BIT(1) +#define BIT_EEDO_V1 BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_SDIO_MONITOR_2 (Offset 0x1025000C) */ -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_CMD53_WT_EN BIT(23) -#define BIT_SW18_FPWM BIT(11) +#define BIT_SHIFT_SDIO_CLK_MONITOR 21 +#define BIT_MASK_SDIO_CLK_MONITOR 0x3 +#define BIT_SDIO_CLK_MONITOR(x) \ + (((x) & BIT_MASK_SDIO_CLK_MONITOR) << BIT_SHIFT_SDIO_CLK_MONITOR) +#define BITS_SDIO_CLK_MONITOR \ + (BIT_MASK_SDIO_CLK_MONITOR << BIT_SHIFT_SDIO_CLK_MONITOR) +#define BIT_CLEAR_SDIO_CLK_MONITOR(x) ((x) & (~BITS_SDIO_CLK_MONITOR)) +#define BIT_GET_SDIO_CLK_MONITOR(x) \ + (((x) >> BIT_SHIFT_SDIO_CLK_MONITOR) & BIT_MASK_SDIO_CLK_MONITOR) +#define BIT_SET_SDIO_CLK_MONITOR(x, v) \ + (BIT_CLEAR_SDIO_CLK_MONITOR(x) | BIT_SDIO_CLK_MONITOR(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_EE_VPD (Offset 0x000C) */ +#define BIT_SHIFT_VPD_DATA 0 +#define BIT_MASK_VPD_DATA 0xffffffffL +#define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA) +#define BITS_VPD_DATA (BIT_MASK_VPD_DATA << BIT_SHIFT_VPD_DATA) +#define BIT_CLEAR_VPD_DATA(x) ((x) & (~BITS_VPD_DATA)) +#define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA) +#define BIT_SET_VPD_DATA(x, v) (BIT_CLEAR_VPD_DATA(x) | BIT_VPD_DATA(v)) -/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_VOL_L1 10 -#define BIT_MASK_VOL_L1 0xf -#define BIT_VOL_L1(x) (((x) & BIT_MASK_VOL_L1) << BIT_SHIFT_VOL_L1) -#define BIT_GET_VOL_L1(x) (((x) >> BIT_SHIFT_VOL_L1) & BIT_MASK_VOL_L1) +/* 2 REG_SDIO_MONITOR_2 (Offset 0x1025000C) */ +#define BIT_SHIFT_SDIO_CLK_CNT 0 +#define BIT_MASK_SDIO_CLK_CNT 0x1fffff +#define BIT_SDIO_CLK_CNT(x) \ + (((x) & BIT_MASK_SDIO_CLK_CNT) << BIT_SHIFT_SDIO_CLK_CNT) +#define BITS_SDIO_CLK_CNT (BIT_MASK_SDIO_CLK_CNT << BIT_SHIFT_SDIO_CLK_CNT) +#define BIT_CLEAR_SDIO_CLK_CNT(x) ((x) & (~BITS_SDIO_CLK_CNT)) +#define BIT_GET_SDIO_CLK_CNT(x) \ + (((x) >> BIT_SHIFT_SDIO_CLK_CNT) & BIT_MASK_SDIO_CLK_CNT) +#define BIT_SET_SDIO_CLK_CNT(x, v) \ + (BIT_CLEAR_SDIO_CLK_CNT(x) | BIT_SDIO_CLK_CNT(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_EE_VPD (Offset 0x000C) */ + +#define BIT_SHIFT_VDP_DATA 0 +#define BIT_MASK_VDP_DATA 0xffffffffL +#define BIT_VDP_DATA(x) (((x) & BIT_MASK_VDP_DATA) << BIT_SHIFT_VDP_DATA) +#define BITS_VDP_DATA (BIT_MASK_VDP_DATA << BIT_SHIFT_VDP_DATA) +#define BIT_CLEAR_VDP_DATA(x) ((x) & (~BITS_VDP_DATA)) +#define BIT_GET_VDP_DATA(x) (((x) >> BIT_SHIFT_VDP_DATA) & BIT_MASK_VDP_DATA) +#define BIT_SET_VDP_DATA(x, v) (BIT_CLEAR_VDP_DATA(x) | BIT_VDP_DATA(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_SW18_SWEN BIT(9) -#define BIT_SW18_LDEN BIT(8) -#define BIT_MAC_ID_EN BIT(7) +#define BIT_SW18_C2_BIT0 BIT(31) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_WL_CTRL_XTAL_CADJ BIT(6) +#define BIT_C2_L_BIT0 BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_LDO11_EN BIT(6) -#define BIT_AFE_P3_PC BIT(5) -#define BIT_AFE_P2_PC BIT(4) -#define BIT_AFE_P1_PC BIT(3) -#define BIT_AFE_P0_PC BIT(2) +#define BIT_SHIFT_R1_L1_V1 30 +#define BIT_MASK_R1_L1_V1 0x3 +#define BIT_R1_L1_V1(x) (((x) & BIT_MASK_R1_L1_V1) << BIT_SHIFT_R1_L1_V1) +#define BITS_R1_L1_V1 (BIT_MASK_R1_L1_V1 << BIT_SHIFT_R1_L1_V1) +#define BIT_CLEAR_R1_L1_V1(x) ((x) & (~BITS_R1_L1_V1)) +#define BIT_GET_R1_L1_V1(x) (((x) >> BIT_SHIFT_R1_L1_V1) & BIT_MASK_R1_L1_V1) +#define BIT_SET_R1_L1_V1(x, v) (BIT_CLEAR_R1_L1_V1(x) | BIT_R1_L1_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_AFE_BGEN BIT(0) +#define BIT_SHIFT_SW18_C1 29 +#define BIT_MASK_SW18_C1 0x3 +#define BIT_SW18_C1(x) (((x) & BIT_MASK_SW18_C1) << BIT_SHIFT_SW18_C1) +#define BITS_SW18_C1 (BIT_MASK_SW18_C1 << BIT_SHIFT_SW18_C1) +#define BIT_CLEAR_SW18_C1(x) ((x) & (~BITS_SW18_C1)) +#define BIT_GET_SW18_C1(x) (((x) >> BIT_SHIFT_SW18_C1) & BIT_MASK_SW18_C1) +#define BIT_SET_SW18_C1(x, v) (BIT_CLEAR_SW18_C1(x) | BIT_SW18_C1(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_POW_ZCD_L BIT(31) +#define BIT_SHIFT_C1_L 29 +#define BIT_MASK_C1_L 0x3 +#define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L) +#define BITS_C1_L (BIT_MASK_C1_L << BIT_SHIFT_C1_L) +#define BIT_CLEAR_C1_L(x) ((x) & (~BITS_C1_L)) +#define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L) +#define BIT_SET_C1_L(x, v) (BIT_CLEAR_C1_L(x) | BIT_C1_L(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SHIFT_C3_L1_V1 28 +#define BIT_MASK_C3_L1_V1 0x3 +#define BIT_C3_L1_V1(x) (((x) & BIT_MASK_C3_L1_V1) << BIT_SHIFT_C3_L1_V1) +#define BITS_C3_L1_V1 (BIT_MASK_C3_L1_V1 << BIT_SHIFT_C3_L1_V1) +#define BIT_CLEAR_C3_L1_V1(x) ((x) & (~BITS_C3_L1_V1)) +#define BIT_GET_C3_L1_V1(x) (((x) >> BIT_SHIFT_C3_L1_V1) & BIT_MASK_C3_L1_V1) +#define BIT_SET_C3_L1_V1(x, v) (BIT_CLEAR_C3_L1_V1(x) | BIT_C3_L1_V1(v)) -#define BIT_IO_READY_SIGNAL_ERR_MSK BIT(31) +#define BIT_SHIFT_C2_L1_V1 26 +#define BIT_MASK_C2_L1_V1 0x3 +#define BIT_C2_L1_V1(x) (((x) & BIT_MASK_C2_L1_V1) << BIT_SHIFT_C2_L1_V1) +#define BITS_C2_L1_V1 (BIT_MASK_C2_L1_V1 << BIT_SHIFT_C2_L1_V1) +#define BIT_CLEAR_C2_L1_V1(x) ((x) & (~BITS_C2_L1_V1)) +#define BIT_GET_C2_L1_V1(x) (((x) >> BIT_SHIFT_C2_L1_V1) & BIT_MASK_C2_L1_V1) +#define BIT_SET_C2_L1_V1(x, v) (BIT_CLEAR_C2_L1_V1(x) | BIT_C2_L1_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SHIFT_REG_FREQ_L 25 +#define BIT_MASK_REG_FREQ_L 0x7 +#define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L) +#define BITS_REG_FREQ_L (BIT_MASK_REG_FREQ_L << BIT_SHIFT_REG_FREQ_L) +#define BIT_CLEAR_REG_FREQ_L(x) ((x) & (~BITS_REG_FREQ_L)) +#define BIT_GET_REG_FREQ_L(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L) +#define BIT_SET_REG_FREQ_L(x, v) (BIT_CLEAR_REG_FREQ_L(x) | BIT_REG_FREQ_L(v)) -#define BIT_SDIO_CRCERR_MSK BIT(31) +#define BIT_REG_EN_DUTY BIT(24) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_C1_L1_V1 24 +#define BIT_MASK_C1_L1_V1 0x3 +#define BIT_C1_L1_V1(x) (((x) & BIT_MASK_C1_L1_V1) << BIT_SHIFT_C1_L1_V1) +#define BITS_C1_L1_V1 (BIT_MASK_C1_L1_V1 << BIT_SHIFT_C1_L1_V1) +#define BIT_CLEAR_C1_L1_V1(x) ((x) & (~BITS_C1_L1_V1)) +#define BIT_GET_C1_L1_V1(x) (((x) >> BIT_SHIFT_C1_L1_V1) & BIT_MASK_C1_L1_V1) +#define BIT_SET_C1_L1_V1(x, v) (BIT_CLEAR_C1_L1_V1(x) | BIT_C1_L1_V1(v)) -#define BIT_ENABLE_ZCDOUT_L BIT(30) +#define BIT_REG_TYPE_L_V3 BIT(23) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_REG_MODE 22 +#define BIT_MASK_REG_MODE 0x3 +#define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE) +#define BITS_REG_MODE (BIT_MASK_REG_MODE << BIT_SHIFT_REG_MODE) +#define BIT_CLEAR_REG_MODE(x) ((x) & (~BITS_REG_MODE)) +#define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE) +#define BIT_SET_REG_MODE(x, v) (BIT_CLEAR_REG_MODE(x) | BIT_REG_MODE(v)) -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#endif -#define BIT_SDIO_TX_CRC__MSK BIT(30) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_FPWM_L1_V1 BIT(22) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_AUTOZCD_L BIT(30) -#define BIT_SDIO_HSISR3_IND_MSK BIT(30) -#define BIT_SDIO_HSISR2_IND_MSK BIT(29) +#define BIT_REG_EN_SP BIT(21) +#define BIT_REG_AUTO_L BIT(20) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SW18_SELD_BIT0 BIT(19) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_REG_DELAY 28 -#define BIT_MASK_REG_DELAY 0x3 -#define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY) -#define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_V15ADJ_L1 19 +#define BIT_MASK_V15ADJ_L1 0x7 +#define BIT_V15ADJ_L1(x) (((x) & BIT_MASK_V15ADJ_L1) << BIT_SHIFT_V15ADJ_L1) +#define BITS_V15ADJ_L1 (BIT_MASK_V15ADJ_L1 << BIT_SHIFT_V15ADJ_L1) +#define BIT_CLEAR_V15ADJ_L1(x) ((x) & (~BITS_V15ADJ_L1)) +#define BIT_GET_V15ADJ_L1(x) (((x) >> BIT_SHIFT_V15ADJ_L1) & BIT_MASK_V15ADJ_L1) +#define BIT_SET_V15ADJ_L1(x, v) (BIT_CLEAR_V15ADJ_L1(x) | BIT_V15ADJ_L1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_SDIO_HEISR_IND_MSK BIT(28) +#define BIT_SW18_POWOCP BIT(18) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_IN_L1 16 +#define BIT_MASK_IN_L1 0x7 +#define BIT_IN_L1(x) (((x) & BIT_MASK_IN_L1) << BIT_SHIFT_IN_L1) +#define BITS_IN_L1 (BIT_MASK_IN_L1 << BIT_SHIFT_IN_L1) +#define BIT_CLEAR_IN_L1(x) ((x) & (~BITS_IN_L1)) +#define BIT_GET_IN_L1(x) (((x) >> BIT_SHIFT_IN_L1) & BIT_MASK_IN_L1) +#define BIT_SET_IN_L1(x, v) (BIT_CLEAR_IN_L1(x) | BIT_IN_L1(v)) -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#endif -#define BIT_SDIO_CTWEND_MSK BIT(27) -#define BIT_SDIO_ATIMEND_E_MSK BIT(26) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_SW18_OCP 15 +#define BIT_MASK_SW18_OCP 0x7 +#define BIT_SW18_OCP(x) (((x) & BIT_MASK_SW18_OCP) << BIT_SHIFT_SW18_OCP) +#define BITS_SW18_OCP (BIT_MASK_SW18_OCP << BIT_SHIFT_SW18_OCP) +#define BIT_CLEAR_SW18_OCP(x) ((x) & (~BITS_SW18_OCP)) +#define BIT_GET_SW18_OCP(x) (((x) >> BIT_SHIFT_SW18_OCP) & BIT_MASK_SW18_OCP) +#define BIT_SET_SW18_OCP(x, v) (BIT_CLEAR_SW18_OCP(x) | BIT_SW18_OCP(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_SDIO_ATIMEND_MSK BIT(25) +#define BIT_SHIFT_OCP_L1 15 +#define BIT_MASK_OCP_L1 0x7 +#define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1) +#define BITS_OCP_L1 (BIT_MASK_OCP_L1 << BIT_SHIFT_OCP_L1) +#define BIT_CLEAR_OCP_L1(x) ((x) & (~BITS_OCP_L1)) +#define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1) +#define BIT_SET_OCP_L1(x, v) (BIT_CLEAR_OCP_L1(x) | BIT_OCP_L1(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_STD_L1 14 +#define BIT_MASK_STD_L1 0x3 +#define BIT_STD_L1(x) (((x) & BIT_MASK_STD_L1) << BIT_SHIFT_STD_L1) +#define BITS_STD_L1 (BIT_MASK_STD_L1 << BIT_SHIFT_STD_L1) +#define BIT_CLEAR_STD_L1(x) ((x) & (~BITS_STD_L1)) +#define BIT_GET_STD_L1(x) (((x) >> BIT_SHIFT_STD_L1) & BIT_MASK_STD_L1) +#define BIT_SET_STD_L1(x, v) (BIT_CLEAR_STD_L1(x) | BIT_STD_L1(v)) -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SDIIO_ATIMEND_MSK BIT(25) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ + +#define BIT_SHIFT_CF_L_BIT0_TO_1 13 +#define BIT_MASK_CF_L_BIT0_TO_1 0x3 +#define BIT_CF_L_BIT0_TO_1(x) \ + (((x) & BIT_MASK_CF_L_BIT0_TO_1) << BIT_SHIFT_CF_L_BIT0_TO_1) +#define BITS_CF_L_BIT0_TO_1 \ + (BIT_MASK_CF_L_BIT0_TO_1 << BIT_SHIFT_CF_L_BIT0_TO_1) +#define BIT_CLEAR_CF_L_BIT0_TO_1(x) ((x) & (~BITS_CF_L_BIT0_TO_1)) +#define BIT_GET_CF_L_BIT0_TO_1(x) \ + (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1) & BIT_MASK_CF_L_BIT0_TO_1) +#define BIT_SET_CF_L_BIT0_TO_1(x, v) \ + (BIT_CLEAR_CF_L_BIT0_TO_1(x) | BIT_CF_L_BIT0_TO_1(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_CF_L 13 +#define BIT_MASK_CF_L 0x3 +#define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L) +#define BITS_CF_L (BIT_MASK_CF_L << BIT_SHIFT_CF_L) +#define BIT_CLEAR_CF_L(x) ((x) & (~BITS_CF_L)) +#define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L) +#define BIT_SET_CF_L(x, v) (BIT_CLEAR_CF_L(x) | BIT_CF_L(v)) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SW18_V15ADJ 24 -#define BIT_MASK_SW18_V15ADJ 0x7 -#define BIT_SW18_V15ADJ(x) (((x) & BIT_MASK_SW18_V15ADJ) << BIT_SHIFT_SW18_V15ADJ) -#define BIT_GET_SW18_V15ADJ(x) (((x) >> BIT_SHIFT_SW18_V15ADJ) & BIT_MASK_SW18_V15ADJ) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SW18_FPWM BIT(11) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SPS_FPWM BIT(11) +#define BIT_WL_CTRL_SPS_PWMFREQ BIT(10) -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#endif -#define BIT_SDIO_OCPINT_MSK BIT(24) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SHIFT_VOL_L1 10 +#define BIT_MASK_VOL_L1 0xf +#define BIT_VOL_L1(x) (((x) & BIT_MASK_VOL_L1) << BIT_SHIFT_VOL_L1) +#define BITS_VOL_L1 (BIT_MASK_VOL_L1 << BIT_SHIFT_VOL_L1) +#define BIT_CLEAR_VOL_L1(x) ((x) & (~BITS_VOL_L1)) +#define BIT_GET_VOL_L1(x) (((x) >> BIT_SHIFT_VOL_L1) & BIT_MASK_VOL_L1) +#define BIT_SET_VOL_L1(x, v) (BIT_CLEAR_VOL_L1(x) | BIT_VOL_L1(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_OCPSL BIT(24) +#define BIT_SW18_SWEN BIT(9) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SPS_SWEN BIT(9) +#define BIT_HALF_L BIT(9) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_V15ADJ_L1_V1 24 -#define BIT_MASK_V15ADJ_L1_V1 0x7 -#define BIT_V15ADJ_L1_V1(x) (((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1) -#define BIT_GET_V15ADJ_L1_V1(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SW18_LDEN BIT(8) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_SPS_LDEN BIT(8) -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_SDIO_PSTIMEOUT_MSK BIT(23) +#define BIT_MAC_ID_EN BIT(7) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_WL_CTRL_XTAL_CADJ BIT(6) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif -#define BIT_REG_LDOF_L_V1 BIT(23) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ + +#define BIT_LDO11_EN BIT(6) +#define BIT_AFE_P3_PC BIT(5) +#define BIT_AFE_P2_PC BIT(4) +#define BIT_AFE_P1_PC BIT(3) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_AFE_MBEN_PCIE_OPT BIT(2) -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ -#define BIT_SDIO_GTINT4_MSK BIT(22) +#define BIT_AFE_P0_PC BIT(2) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ +#define BIT_AFE_MBEN BIT(1) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_PARSW_DUMMY BIT(22) +/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ + +#define BIT_AFE_BGEN BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ + +#define BIT_POW_ZCD_L BIT(31) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_GTINT3_MSK BIT(21) +#define BIT_SDIO_CRCERR_MSK BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_CLAMP_MAX_DUTY BIT(21) +#define BIT_IO_READY_SIGNAL_ERR_MSK BIT(31) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_ENABLE_ZCDOUT_L BIT(30) -#define BIT_SHIFT_SW18_VOL 20 -#define BIT_MASK_SW18_VOL 0xf -#define BIT_SW18_VOL(x) (((x) & BIT_MASK_SW18_VOL) << BIT_SHIFT_SW18_VOL) -#define BIT_GET_SW18_VOL(x) (((x) >> BIT_SHIFT_SW18_VOL) & BIT_MASK_SW18_VOL) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_AUTOZCD_L BIT(30) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_HSISR_IND_MSK BIT(20) +#define BIT_SDIO_HSISR3_IND_MSK BIT(30) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIO_TX_CRC__MSK BIT(30) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_VOL_L1_V1 20 -#define BIT_MASK_VOL_L1_V1 0xf -#define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1) -#define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIO_HSISR2_IND_MSK BIT(29) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ + +#define BIT_SHIFT_REG_DELAY 28 +#define BIT_MASK_REG_DELAY 0x3 +#define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY) +#define BITS_REG_DELAY (BIT_MASK_REG_DELAY << BIT_SHIFT_REG_DELAY) +#define BIT_CLEAR_REG_DELAY(x) ((x) & (~BITS_REG_DELAY)) +#define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY) +#define BIT_SET_REG_DELAY(x, v) (BIT_CLEAR_REG_DELAY(x) | BIT_REG_DELAY(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_CPWM2_MSK BIT(19) +#define BIT_SDIO_HEISR_IND_MSK BIT(28) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIO_CTWEND_MSK BIT(27) +#define BIT_SDIO_ATIMEND_E_MSK BIT(26) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TBOX_L1_V1 19 -#define BIT_MASK_TBOX_L1_V1 0x3 -#define BIT_TBOX_L1_V1(x) (((x) & BIT_MASK_TBOX_L1_V1) << BIT_SHIFT_TBOX_L1_V1) -#define BIT_GET_TBOX_L1_V1(x) (((x) >> BIT_SHIFT_TBOX_L1_V1) & BIT_MASK_TBOX_L1_V1) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIIO_ATIMEND_MSK BIT(25) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_CPWM1_MSK BIT(18) +#define BIT_SDIO_ATIMEND_MSK BIT(25) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_SW18_V15ADJ 24 +#define BIT_MASK_SW18_V15ADJ 0x7 +#define BIT_SW18_V15ADJ(x) \ + (((x) & BIT_MASK_SW18_V15ADJ) << BIT_SHIFT_SW18_V15ADJ) +#define BITS_SW18_V15ADJ (BIT_MASK_SW18_V15ADJ << BIT_SHIFT_SW18_V15ADJ) +#define BIT_CLEAR_SW18_V15ADJ(x) ((x) & (~BITS_SW18_V15ADJ)) +#define BIT_GET_SW18_V15ADJ(x) \ + (((x) >> BIT_SHIFT_SW18_V15ADJ) & BIT_MASK_SW18_V15ADJ) +#define BIT_SET_SW18_V15ADJ(x, v) \ + (BIT_CLEAR_SW18_V15ADJ(x) | BIT_SW18_V15ADJ(v)) -#define BIT_SHIFT_SW18_IN 17 -#define BIT_MASK_SW18_IN 0x7 -#define BIT_SW18_IN(x) (((x) & BIT_MASK_SW18_IN) << BIT_SHIFT_SW18_IN) -#define BIT_GET_SW18_IN(x) (((x) >> BIT_SHIFT_SW18_IN) & BIT_MASK_SW18_IN) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_V15ADJ_L1_V1 24 +#define BIT_MASK_V15ADJ_L1_V1 0x7 +#define BIT_V15ADJ_L1_V1(x) \ + (((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1) +#define BITS_V15ADJ_L1_V1 (BIT_MASK_V15ADJ_L1_V1 << BIT_SHIFT_V15ADJ_L1_V1) +#define BIT_CLEAR_V15ADJ_L1_V1(x) ((x) & (~BITS_V15ADJ_L1_V1)) +#define BIT_GET_V15ADJ_L1_V1(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1) +#define BIT_SET_V15ADJ_L1_V1(x, v) \ + (BIT_CLEAR_V15ADJ_L1_V1(x) | BIT_V15ADJ_L1_V1(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_C2HCMD_INT_MSK BIT(17) +#define BIT_SDIO_OCPINT_MSK BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_REG_DELAY_V3 17 -#define BIT_MASK_REG_DELAY_V3 0x3 -#define BIT_REG_DELAY_V3(x) (((x) & BIT_MASK_REG_DELAY_V3) << BIT_SHIFT_REG_DELAY_V3) -#define BIT_GET_REG_DELAY_V3(x) (((x) >> BIT_SHIFT_REG_DELAY_V3) & BIT_MASK_REG_DELAY_V3) - +#define BIT_OCPSL BIT(24) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIO_PSTIMEOUT_MSK BIT(23) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_IN_L1_V1 17 -#define BIT_MASK_IN_L1_V1 0x7 -#define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1) -#define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1) +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_REG_LDOF_L_V1 BIT(23) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_BCNERLY_INT_MSK BIT(16) +#define BIT_SDIO_GTINT4_MSK BIT(22) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_REG_CLAMP_D_L_V2 BIT(16) +#define BIT_PARSW_DUMMY BIT(22) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIO_GTINT3_MSK BIT(21) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_SW18_TBOX 15 -#define BIT_MASK_SW18_TBOX 0x3 -#define BIT_SW18_TBOX(x) (((x) & BIT_MASK_SW18_TBOX) << BIT_SHIFT_SW18_TBOX) -#define BIT_GET_SW18_TBOX(x) (((x) >> BIT_SHIFT_SW18_TBOX) & BIT_MASK_SW18_TBOX) +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_CLAMP_MAX_DUTY BIT(21) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_REG_BYPASS_L_V3 BIT(15) +#define BIT_SHIFT_SW18_VOL 20 +#define BIT_MASK_SW18_VOL 0xf +#define BIT_SW18_VOL(x) (((x) & BIT_MASK_SW18_VOL) << BIT_SHIFT_SW18_VOL) +#define BITS_SW18_VOL (BIT_MASK_SW18_VOL << BIT_SHIFT_SW18_VOL) +#define BIT_CLEAR_SW18_VOL(x) ((x) & (~BITS_SW18_VOL)) +#define BIT_GET_SW18_VOL(x) (((x) >> BIT_SHIFT_SW18_VOL) & BIT_MASK_SW18_VOL) +#define BIT_SET_SW18_VOL(x, v) (BIT_CLEAR_SW18_VOL(x) | BIT_SW18_VOL(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_VOL_L1_V1 20 +#define BIT_MASK_VOL_L1_V1 0xf +#define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1) +#define BITS_VOL_L1_V1 (BIT_MASK_VOL_L1_V1 << BIT_SHIFT_VOL_L1_V1) +#define BIT_CLEAR_VOL_L1_V1(x) ((x) & (~BITS_VOL_L1_V1)) +#define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1) +#define BIT_SET_VOL_L1_V1(x, v) (BIT_CLEAR_VOL_L1_V1(x) | BIT_VOL_L1_V1(v)) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TBOX_L1 15 -#define BIT_MASK_TBOX_L1 0x3 -#define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1) -#define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIO_HSISR_IND_MSK BIT(20) +#define BIT_SDIO_CPWM2_MSK BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_ENABLE_ZCDOUT_L_V3 BIT(14) +#define BIT_SHIFT_TBOX_L1_V1 19 +#define BIT_MASK_TBOX_L1_V1 0x3 +#define BIT_TBOX_L1_V1(x) (((x) & BIT_MASK_TBOX_L1_V1) << BIT_SHIFT_TBOX_L1_V1) +#define BITS_TBOX_L1_V1 (BIT_MASK_TBOX_L1_V1 << BIT_SHIFT_TBOX_L1_V1) +#define BIT_CLEAR_TBOX_L1_V1(x) ((x) & (~BITS_TBOX_L1_V1)) +#define BIT_GET_TBOX_L1_V1(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_V1) & BIT_MASK_TBOX_L1_V1) +#define BIT_SET_TBOX_L1_V1(x, v) (BIT_CLEAR_TBOX_L1_V1(x) | BIT_TBOX_L1_V1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ + +#define BIT_SDIO_CPWM1_MSK BIT(18) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_SW18_SEL BIT(13) +#define BIT_SHIFT_SW18_IN 17 +#define BIT_MASK_SW18_IN 0x7 +#define BIT_SW18_IN(x) (((x) & BIT_MASK_SW18_IN) << BIT_SHIFT_SW18_IN) +#define BITS_SW18_IN (BIT_MASK_SW18_IN << BIT_SHIFT_SW18_IN) +#define BIT_CLEAR_SW18_IN(x) ((x) & (~BITS_SW18_IN)) +#define BIT_GET_SW18_IN(x) (((x) >> BIT_SHIFT_SW18_IN) & BIT_MASK_SW18_IN) +#define BIT_SET_SW18_IN(x, v) (BIT_CLEAR_SW18_IN(x) | BIT_SW18_IN(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_POW_ZCD_L_V3 BIT(13) -#define BIT_AREN_L1_V1 BIT(12) +#define BIT_SHIFT_IN_L1_V1 17 +#define BIT_MASK_IN_L1_V1 0x7 +#define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1) +#define BITS_IN_L1_V1 (BIT_MASK_IN_L1_V1 << BIT_SHIFT_IN_L1_V1) +#define BIT_CLEAR_IN_L1_V1(x) ((x) & (~BITS_IN_L1_V1)) +#define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1) +#define BIT_SET_IN_L1_V1(x, v) (BIT_CLEAR_IN_L1_V1(x) | BIT_IN_L1_V1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIO_C2HCMD_INT_MSK BIT(17) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_SW18_STD 11 -#define BIT_MASK_SW18_STD 0x3 -#define BIT_SW18_STD(x) (((x) & BIT_MASK_SW18_STD) << BIT_SHIFT_SW18_STD) -#define BIT_GET_SW18_STD(x) (((x) >> BIT_SHIFT_SW18_STD) & BIT_MASK_SW18_STD) +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_REG_DELAY_V3 17 +#define BIT_MASK_REG_DELAY_V3 0x3 +#define BIT_REG_DELAY_V3(x) \ + (((x) & BIT_MASK_REG_DELAY_V3) << BIT_SHIFT_REG_DELAY_V3) +#define BITS_REG_DELAY_V3 (BIT_MASK_REG_DELAY_V3 << BIT_SHIFT_REG_DELAY_V3) +#define BIT_CLEAR_REG_DELAY_V3(x) ((x) & (~BITS_REG_DELAY_V3)) +#define BIT_GET_REG_DELAY_V3(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_V3) & BIT_MASK_REG_DELAY_V3) +#define BIT_SET_REG_DELAY_V3(x, v) \ + (BIT_CLEAR_REG_DELAY_V3(x) | BIT_REG_DELAY_V3(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIO_BCNERLY_INT_MSK BIT(16) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif -#define BIT_SW18_SD BIT(10) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_REG_CLAMP_D_L_V2 BIT(16) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_SW18_AREN BIT(9) +#define BIT_SHIFT_SW18_TBOX 15 +#define BIT_MASK_SW18_TBOX 0x3 +#define BIT_SW18_TBOX(x) (((x) & BIT_MASK_SW18_TBOX) << BIT_SHIFT_SW18_TBOX) +#define BITS_SW18_TBOX (BIT_MASK_SW18_TBOX << BIT_SHIFT_SW18_TBOX) +#define BIT_CLEAR_SW18_TBOX(x) ((x) & (~BITS_SW18_TBOX)) +#define BIT_GET_SW18_TBOX(x) (((x) >> BIT_SHIFT_SW18_TBOX) & BIT_MASK_SW18_TBOX) +#define BIT_SET_SW18_TBOX(x, v) (BIT_CLEAR_SW18_TBOX(x) | BIT_SW18_TBOX(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_OCP_V3 9 -#define BIT_MASK_OCP_V3 0x7 -#define BIT_OCP_V3(x) (((x) & BIT_MASK_OCP_V3) << BIT_SHIFT_OCP_V3) -#define BIT_GET_OCP_V3(x) (((x) >> BIT_SHIFT_OCP_V3) & BIT_MASK_OCP_V3) - -#define BIT_POWOCP_V3 BIT(8) +#define BIT_REG_BYPASS_L_V3 BIT(15) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_TBOX_L1 15 +#define BIT_MASK_TBOX_L1 0x3 +#define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1) +#define BITS_TBOX_L1 (BIT_MASK_TBOX_L1 << BIT_SHIFT_TBOX_L1) +#define BIT_CLEAR_TBOX_L1(x) ((x) & (~BITS_TBOX_L1)) +#define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1) +#define BIT_SET_TBOX_L1(x, v) (BIT_CLEAR_TBOX_L1(x) | BIT_TBOX_L1(v)) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_SW18_R3 7 -#define BIT_MASK_SW18_R3 0x3 -#define BIT_SW18_R3(x) (((x) & BIT_MASK_SW18_R3) << BIT_SHIFT_SW18_R3) -#define BIT_GET_SW18_R3(x) (((x) >> BIT_SHIFT_SW18_R3) & BIT_MASK_SW18_R3) +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_ENABLE_ZCDOUT_L_V3 BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SW18_SEL BIT(13) -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#endif -#define BIT_SDIO_TXBCNERR_MSK BIT(7) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_POW_ZCD_L_V3 BIT(13) +#define BIT_AREN_L1_V1 BIT(12) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_SW18_STD 11 +#define BIT_MASK_SW18_STD 0x3 +#define BIT_SW18_STD(x) (((x) & BIT_MASK_SW18_STD) << BIT_SHIFT_SW18_STD) +#define BITS_SW18_STD (BIT_MASK_SW18_STD << BIT_SHIFT_SW18_STD) +#define BIT_CLEAR_SW18_STD(x) ((x) & (~BITS_SW18_STD)) +#define BIT_GET_SW18_STD(x) (((x) >> BIT_SHIFT_SW18_STD) & BIT_MASK_SW18_STD) +#define BIT_SET_SW18_STD(x, v) (BIT_CLEAR_SW18_STD(x) | BIT_SW18_STD(v)) -#define BIT_SHIFT_R3_L 7 -#define BIT_MASK_R3_L 0x3 -#define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L) -#define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SW18_SD BIT(10) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_SDIO_TXBCNOK_MSK BIT(6) +#define BIT_SW18_AREN BIT(9) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_OCP_V3 9 +#define BIT_MASK_OCP_V3 0x7 +#define BIT_OCP_V3(x) (((x) & BIT_MASK_OCP_V3) << BIT_SHIFT_OCP_V3) +#define BITS_OCP_V3 (BIT_MASK_OCP_V3 << BIT_SHIFT_OCP_V3) +#define BIT_CLEAR_OCP_V3(x) ((x) & (~BITS_OCP_V3)) +#define BIT_GET_OCP_V3(x) (((x) >> BIT_SHIFT_OCP_V3) & BIT_MASK_OCP_V3) +#define BIT_SET_OCP_V3(x, v) (BIT_CLEAR_OCP_V3(x) | BIT_OCP_V3(v)) -#define BIT_SHIFT_CF_L_V3 6 -#define BIT_MASK_CF_L_V3 0x3 -#define BIT_CF_L_V3(x) (((x) & BIT_MASK_CF_L_V3) << BIT_SHIFT_CF_L_V3) -#define BIT_GET_CF_L_V3(x) (((x) >> BIT_SHIFT_CF_L_V3) & BIT_MASK_CF_L_V3) - +#define BIT_POWOCP_V3 BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_SW18_R2 5 -#define BIT_MASK_SW18_R2 0x3 -#define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2) -#define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2) - +#define BIT_SHIFT_SW18_R3 7 +#define BIT_MASK_SW18_R3 0x3 +#define BIT_SW18_R3(x) (((x) & BIT_MASK_SW18_R3) << BIT_SHIFT_SW18_R3) +#define BITS_SW18_R3 (BIT_MASK_SW18_R3 << BIT_SHIFT_SW18_R3) +#define BIT_CLEAR_SW18_R3(x) ((x) & (~BITS_SW18_R3)) +#define BIT_GET_SW18_R3(x) (((x) >> BIT_SHIFT_SW18_R3) & BIT_MASK_SW18_R3) +#define BIT_SET_SW18_R3(x, v) (BIT_CLEAR_SW18_R3(x) | BIT_SW18_R3(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_RXFOVW_MSK BIT(5) -#define BIT_SDIO_TXFOVW_MSK BIT(4) +#define BIT_SDIO_TXBCNERR_MSK BIT(7) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_R3_L 7 +#define BIT_MASK_R3_L 0x3 +#define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L) +#define BITS_R3_L (BIT_MASK_R3_L << BIT_SHIFT_R3_L) +#define BIT_CLEAR_R3_L(x) ((x) & (~BITS_R3_L)) +#define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L) +#define BIT_SET_R3_L(x, v) (BIT_CLEAR_R3_L(x) | BIT_R3_L(v)) -#define BIT_SHIFT_CFC_L_BIT0_TO_1_V1 4 -#define BIT_MASK_CFC_L_BIT0_TO_1_V1 0x3 -#define BIT_CFC_L_BIT0_TO_1_V1(x) (((x) & BIT_MASK_CFC_L_BIT0_TO_1_V1) << BIT_SHIFT_CFC_L_BIT0_TO_1_V1) -#define BIT_GET_CFC_L_BIT0_TO_1_V1(x) (((x) >> BIT_SHIFT_CFC_L_BIT0_TO_1_V1) & BIT_MASK_CFC_L_BIT0_TO_1_V1) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ +#define BIT_SDIO_TXBCNOK_MSK BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_CF_L_V3 6 +#define BIT_MASK_CF_L_V3 0x3 +#define BIT_CF_L_V3(x) (((x) & BIT_MASK_CF_L_V3) << BIT_SHIFT_CF_L_V3) +#define BITS_CF_L_V3 (BIT_MASK_CF_L_V3 << BIT_SHIFT_CF_L_V3) +#define BIT_CLEAR_CF_L_V3(x) ((x) & (~BITS_CF_L_V3)) +#define BIT_GET_CF_L_V3(x) (((x) >> BIT_SHIFT_CF_L_V3) & BIT_MASK_CF_L_V3) +#define BIT_SET_CF_L_V3(x, v) (BIT_CLEAR_CF_L_V3(x) | BIT_CF_L_V3(v)) -#define BIT_SHIFT_SW18_R1 3 -#define BIT_MASK_SW18_R1 0x3 -#define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1) -#define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_SW18_R2 5 +#define BIT_MASK_SW18_R2 0x3 +#define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2) +#define BITS_SW18_R2 (BIT_MASK_SW18_R2 << BIT_SHIFT_SW18_R2) +#define BIT_CLEAR_SW18_R2(x) ((x) & (~BITS_SW18_R2)) +#define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2) +#define BIT_SET_SW18_R2(x, v) (BIT_CLEAR_SW18_R2(x) | BIT_SW18_R2(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_RXERR_MSK BIT(3) -#define BIT_SDIO_TXERR_MSK BIT(2) +#define BIT_SDIO_RXFOVW_MSK BIT(5) +#define BIT_SDIO_TXFOVW_MSK BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_R3_L1_V1 2 -#define BIT_MASK_R3_L1_V1 0x3 -#define BIT_R3_L1_V1(x) (((x) & BIT_MASK_R3_L1_V1) << BIT_SHIFT_R3_L1_V1) -#define BIT_GET_R3_L1_V1(x) (((x) >> BIT_SHIFT_R3_L1_V1) & BIT_MASK_R3_L1_V1) - +#define BIT_SHIFT_CFC_L_BIT0_TO_1_V1 4 +#define BIT_MASK_CFC_L_BIT0_TO_1_V1 0x3 +#define BIT_CFC_L_BIT0_TO_1_V1(x) \ + (((x) & BIT_MASK_CFC_L_BIT0_TO_1_V1) << BIT_SHIFT_CFC_L_BIT0_TO_1_V1) +#define BITS_CFC_L_BIT0_TO_1_V1 \ + (BIT_MASK_CFC_L_BIT0_TO_1_V1 << BIT_SHIFT_CFC_L_BIT0_TO_1_V1) +#define BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) ((x) & (~BITS_CFC_L_BIT0_TO_1_V1)) +#define BIT_GET_CFC_L_BIT0_TO_1_V1(x) \ + (((x) >> BIT_SHIFT_CFC_L_BIT0_TO_1_V1) & BIT_MASK_CFC_L_BIT0_TO_1_V1) +#define BIT_SET_CFC_L_BIT0_TO_1_V1(x, v) \ + (BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) | BIT_CFC_L_BIT0_TO_1_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_SW18_C3 1 -#define BIT_MASK_SW18_C3 0x3 -#define BIT_SW18_C3(x) (((x) & BIT_MASK_SW18_C3) << BIT_SHIFT_SW18_C3) -#define BIT_GET_SW18_C3(x) (((x) >> BIT_SHIFT_SW18_C3) & BIT_MASK_SW18_C3) - +#define BIT_SHIFT_SW18_R1 3 +#define BIT_MASK_SW18_R1 0x3 +#define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1) +#define BITS_SW18_R1 (BIT_MASK_SW18_R1 << BIT_SHIFT_SW18_R1) +#define BIT_CLEAR_SW18_R1(x) ((x) & (~BITS_SW18_R1)) +#define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1) +#define BIT_SET_SW18_R1(x, v) (BIT_CLEAR_SW18_R1(x) | BIT_SW18_R1(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_SDIO_AVAL_MSK BIT(1) +#define BIT_SDIO_RXERR_MSK BIT(3) +#define BIT_SDIO_TXERR_MSK BIT(2) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_R3_L1_V1 2 +#define BIT_MASK_R3_L1_V1 0x3 +#define BIT_R3_L1_V1(x) (((x) & BIT_MASK_R3_L1_V1) << BIT_SHIFT_R3_L1_V1) +#define BITS_R3_L1_V1 (BIT_MASK_R3_L1_V1 << BIT_SHIFT_R3_L1_V1) +#define BIT_CLEAR_R3_L1_V1(x) ((x) & (~BITS_R3_L1_V1)) +#define BIT_GET_R3_L1_V1(x) (((x) >> BIT_SHIFT_R3_L1_V1) & BIT_MASK_R3_L1_V1) +#define BIT_SET_R3_L1_V1(x, v) (BIT_CLEAR_R3_L1_V1(x) | BIT_R3_L1_V1(v)) -/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_C3_L_C3 1 -#define BIT_MASK_C3_L_C3 0x3 -#define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3) -#define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3) +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ +#define BIT_SHIFT_SW18_C3 1 +#define BIT_MASK_SW18_C3 0x3 +#define BIT_SW18_C3(x) (((x) & BIT_MASK_SW18_C3) << BIT_SHIFT_SW18_C3) +#define BITS_SW18_C3 (BIT_MASK_SW18_C3 << BIT_SHIFT_SW18_C3) +#define BIT_CLEAR_SW18_C3(x) ((x) & (~BITS_SW18_C3)) +#define BIT_GET_SW18_C3(x) (((x) >> BIT_SHIFT_SW18_C3) & BIT_MASK_SW18_C3) +#define BIT_SET_SW18_C3(x, v) (BIT_CLEAR_SW18_C3(x) | BIT_SW18_C3(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_HIMR (Offset 0x10250014) */ + +#define BIT_SDIO_AVAL_MSK BIT(1) +#endif + +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_SW18_C2_BIT1 BIT(0) +#define BIT_SHIFT_C3_L_C3 1 +#define BIT_MASK_C3_L_C3 0x3 +#define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3) +#define BITS_C3_L_C3 (BIT_MASK_C3_L_C3 << BIT_SHIFT_C3_L_C3) +#define BIT_CLEAR_C3_L_C3(x) ((x) & (~BITS_C3_L_C3)) +#define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3) +#define BIT_SET_C3_L_C3(x, v) (BIT_CLEAR_C3_L_C3(x) | BIT_C3_L_C3(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ + +#define BIT_SW18_C2_BIT1 BIT(0) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ -#define BIT_RX_REQUEST_MSK BIT(0) +#define BIT_RX_REQUEST_MSK BIT(0) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ - -#define BIT_SHIFT_R2_L1_V1 0 -#define BIT_MASK_R2_L1_V1 0x3 -#define BIT_R2_L1_V1(x) (((x) & BIT_MASK_R2_L1_V1) << BIT_SHIFT_R2_L1_V1) -#define BIT_GET_R2_L1_V1(x) (((x) >> BIT_SHIFT_R2_L1_V1) & BIT_MASK_R2_L1_V1) - +#define BIT_SHIFT_R2_L1_V1 0 +#define BIT_MASK_R2_L1_V1 0x3 +#define BIT_R2_L1_V1(x) (((x) & BIT_MASK_R2_L1_V1) << BIT_SHIFT_R2_L1_V1) +#define BITS_R2_L1_V1 (BIT_MASK_R2_L1_V1 << BIT_SHIFT_R2_L1_V1) +#define BIT_CLEAR_R2_L1_V1(x) ((x) & (~BITS_R2_L1_V1)) +#define BIT_GET_R2_L1_V1(x) (((x) >> BIT_SHIFT_R2_L1_V1) & BIT_MASK_R2_L1_V1) +#define BIT_SET_R2_L1_V1(x, v) (BIT_CLEAR_R2_L1_V1(x) | BIT_R2_L1_V1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ -#define BIT_C2_L_BIT1 BIT(0) +#define BIT_C2_L_BIT1 BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ -#define BIT_SPS18_OCP_DIS BIT(31) +#define BIT_SPS18_OCP_DIS BIT(31) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_IO_READY_SIGNAL_ERR BIT(31) +#define BIT_SDIO_CRCERR BIT(31) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_HISR (Offset 0x10250018) */ + +#define BIT_IO_READY_SIGNAL_ERR BIT(31) + +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_SDIO_CRCERR BIT(31) +#define BIT_SDIO_HSISR3_IND BIT(30) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_TX_CRC BIT(30) +#define BIT_TX_CRC BIT(30) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_SDIO_HSISR3_IND BIT(30) -#define BIT_SDIO_HSISR2_IND BIT(29) -#define BIT_SDIO_HEISR_IND BIT(28) +#define BIT_SDIO_HSISR2_IND BIT(29) +#define BIT_SDIO_HEISR_IND BIT(28) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_SDIO_CTWEND BIT(27) -#define BIT_SDIO_ATIMEND_E BIT(26) -#define BIT_SDIO_ATIMEND BIT(25) -#define BIT_SDIO_OCPINT BIT(24) -#define BIT_SDIO_PSTIMEOUT BIT(23) -#define BIT_SDIO_GTINT4 BIT(22) -#define BIT_SDIO_GTINT3 BIT(21) -#define BIT_SDIO_HSISR_IND BIT(20) -#define BIT_SDIO_CPWM2 BIT(19) -#define BIT_SDIO_CPWM1 BIT(18) -#define BIT_SDIO_C2HCMD_INT BIT(17) +#define BIT_SDIO_CTWEND BIT(27) +#define BIT_SDIO_ATIMEND_E BIT(26) +#define BIT_SDIO_ATIMEND BIT(25) +#define BIT_SDIO_OCPINT BIT(24) +#define BIT_SDIO_PSTIMEOUT BIT(23) +#define BIT_SDIO_GTINT4 BIT(22) +#define BIT_SDIO_GTINT3 BIT(21) +#define BIT_SDIO_HSISR_IND BIT(20) +#define BIT_SDIO_CPWM2 BIT(19) +#define BIT_SDIO_CPWM1 BIT(18) +#define BIT_SDIO_C2HCMD_INT BIT(17) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ - - -#define BIT_SHIFT_SPS18_OCP_TH 16 -#define BIT_MASK_SPS18_OCP_TH 0x7fff -#define BIT_SPS18_OCP_TH(x) (((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH) -#define BIT_GET_SPS18_OCP_TH(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH) +/* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ +#define BIT_SHIFT_SPS18_OCP_TH 16 +#define BIT_MASK_SPS18_OCP_TH 0x7fff +#define BIT_SPS18_OCP_TH(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH) +#define BITS_SPS18_OCP_TH (BIT_MASK_SPS18_OCP_TH << BIT_SHIFT_SPS18_OCP_TH) +#define BIT_CLEAR_SPS18_OCP_TH(x) ((x) & (~BITS_SPS18_OCP_TH)) +#define BIT_GET_SPS18_OCP_TH(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH) +#define BIT_SET_SPS18_OCP_TH(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH(x) | BIT_SPS18_OCP_TH(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_SDIO_BCNERLY_INT BIT(16) -#define BIT_SDIO_TXBCNERR BIT(7) -#define BIT_SDIO_TXBCNOK BIT(6) -#define BIT_SDIO_RXFOVW BIT(5) -#define BIT_SDIO_TXFOVW BIT(4) -#define BIT_SDIO_RXERR BIT(3) -#define BIT_SDIO_TXERR BIT(2) -#define BIT_SDIO_AVAL BIT(1) +#define BIT_SDIO_BCNERLY_INT BIT(16) +#define BIT_SDIO_TXBCNERR BIT(7) +#define BIT_SDIO_TXBCNOK BIT(6) +#define BIT_SDIO_RXFOVW BIT(5) +#define BIT_SDIO_TXFOVW BIT(4) +#define BIT_SDIO_RXERR BIT(3) +#define BIT_SDIO_TXERR BIT(2) +#define BIT_SDIO_AVAL BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ - -#define BIT_SHIFT_OCP_WINDOW 0 -#define BIT_MASK_OCP_WINDOW 0xffff -#define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW) -#define BIT_GET_OCP_WINDOW(x) (((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW) - +#define BIT_SHIFT_OCP_WINDOW 0 +#define BIT_MASK_OCP_WINDOW 0xffff +#define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW) +#define BITS_OCP_WINDOW (BIT_MASK_OCP_WINDOW << BIT_SHIFT_OCP_WINDOW) +#define BIT_CLEAR_OCP_WINDOW(x) ((x) & (~BITS_OCP_WINDOW)) +#define BIT_GET_OCP_WINDOW(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW) +#define BIT_SET_OCP_WINDOW(x, v) (BIT_CLEAR_OCP_WINDOW(x) | BIT_OCP_WINDOW(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_HISR (Offset 0x10250018) */ -#define BIT_RX_REQUEST BIT(0) +#define BIT_RX_REQUEST BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_HREG_DBG BIT(23) +#define BIT_HREG_DBG BIT(23) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ +#define BIT_SHIFT_HREG_DBG_V1 12 +#define BIT_MASK_HREG_DBG_V1 0xfff +#define BIT_HREG_DBG_V1(x) \ + (((x) & BIT_MASK_HREG_DBG_V1) << BIT_SHIFT_HREG_DBG_V1) +#define BITS_HREG_DBG_V1 (BIT_MASK_HREG_DBG_V1 << BIT_SHIFT_HREG_DBG_V1) +#define BIT_CLEAR_HREG_DBG_V1(x) ((x) & (~BITS_HREG_DBG_V1)) +#define BIT_GET_HREG_DBG_V1(x) \ + (((x) >> BIT_SHIFT_HREG_DBG_V1) & BIT_MASK_HREG_DBG_V1) +#define BIT_SET_HREG_DBG_V1(x, v) \ + (BIT_CLEAR_HREG_DBG_V1(x) | BIT_HREG_DBG_V1(v)) -#define BIT_SHIFT_HREG_DBG_V1 12 -#define BIT_MASK_HREG_DBG_V1 0xfff -#define BIT_HREG_DBG_V1(x) (((x) & BIT_MASK_HREG_DBG_V1) << BIT_SHIFT_HREG_DBG_V1) -#define BIT_GET_HREG_DBG_V1(x) (((x) >> BIT_SHIFT_HREG_DBG_V1) & BIT_MASK_HREG_DBG_V1) +#endif -#define BIT_MCU_RST BIT(11) -#define BIT_WLOCK_90 BIT(10) -#define BIT_WLOCK_70 BIT(9) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_RSV_CTRL (Offset 0x001C) */ +#define BIT_MCU_RST BIT(11) +#define BIT_WLOCK_90 BIT(10) +#define BIT_WLOCK_70 BIT(9) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_WLMCUIOIF BIT(8) +#define BIT_WLMCUIOIF BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_WLOCK_78 BIT(8) +#define BIT_WLOCK_78 BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_LOCK_ALL_EN BIT(7) +#define BIT_LOCK_ALL_EN BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_R_DIS_PRST BIT(6) +#define BIT_R_DIS_PRST BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_R_DIS_PRST_1 BIT(6) +#define BIT_R_DIS_PRST_1 BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_WLOCK_1C_B6 BIT(5) +#define BIT_WLOCK_1C_B6 BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_R_DIS_PRST_0 BIT(5) +#define BIT_R_DIS_PRST_0 BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_RSV_CTRL (Offset 0x001C) */ -#define BIT_WLOCK_40 BIT(4) -#define BIT_WLOCK_08 BIT(3) -#define BIT_WLOCK_04 BIT(2) -#define BIT_WLOCK_00 BIT(1) -#define BIT_WLOCK_ALL BIT(0) +#define BIT_WLOCK_40 BIT(4) +#define BIT_WLOCK_08 BIT(3) +#define BIT_WLOCK_04 BIT(2) +#define BIT_WLOCK_00 BIT(1) +#define BIT_WLOCK_ALL BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_RX_REQ_LEN (Offset 0x1025001C) */ - -#define BIT_SHIFT_RX_REQ_LEN_V1 0 -#define BIT_MASK_RX_REQ_LEN_V1 0x3ffff -#define BIT_RX_REQ_LEN_V1(x) (((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1) -#define BIT_GET_RX_REQ_LEN_V1(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1) - +#define BIT_SHIFT_RX_REQ_LEN_V1 0 +#define BIT_MASK_RX_REQ_LEN_V1 0x3ffff +#define BIT_RX_REQ_LEN_V1(x) \ + (((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1) +#define BITS_RX_REQ_LEN_V1 (BIT_MASK_RX_REQ_LEN_V1 << BIT_SHIFT_RX_REQ_LEN_V1) +#define BIT_CLEAR_RX_REQ_LEN_V1(x) ((x) & (~BITS_RX_REQ_LEN_V1)) +#define BIT_GET_RX_REQ_LEN_V1(x) \ + (((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1) +#define BIT_SET_RX_REQ_LEN_V1(x, v) \ + (BIT_CLEAR_RX_REQ_LEN_V1(x) | BIT_RX_REQ_LEN_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ -#define BIT_RF_SDMRSTB BIT(2) +#define BIT_RF_SDMRSTB BIT(2) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RF0_CTRL (Offset 0x001F) */ -#define BIT_RF0_SDMRSTB BIT(2) +#define BIT_RF0_SDMRSTB BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ -#define BIT_RF_RSTB BIT(1) +#define BIT_RF_RSTB BIT(1) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RF0_CTRL (Offset 0x001F) */ -#define BIT_RF0_RSTB BIT(1) +#define BIT_RF0_RSTB BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_RF_CTRL (Offset 0x001F) */ -#define BIT_RF_EN BIT(0) +#define BIT_RF_EN BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_RF0_CTRL (Offset 0x001F) */ -#define BIT_RF0_EN BIT(0) +#define BIT_RF0_EN BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_FREE_TXPG_SEQ_V1 (Offset 0x1025001F) */ +#define BIT_SHIFT_FREE_TXPG_SEQ 0 +#define BIT_MASK_FREE_TXPG_SEQ 0xff +#define BIT_FREE_TXPG_SEQ(x) \ + (((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ) +#define BITS_FREE_TXPG_SEQ (BIT_MASK_FREE_TXPG_SEQ << BIT_SHIFT_FREE_TXPG_SEQ) +#define BIT_CLEAR_FREE_TXPG_SEQ(x) ((x) & (~BITS_FREE_TXPG_SEQ)) +#define BIT_GET_FREE_TXPG_SEQ(x) \ + (((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ) +#define BIT_SET_FREE_TXPG_SEQ(x, v) \ + (BIT_CLEAR_FREE_TXPG_SEQ(x) | BIT_FREE_TXPG_SEQ(v)) -/* 2 REG_SDIO_FREE_TXPG_SEQ_V1 (Offset 0x1025001F) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FREE_TXPG_SEQ 0 -#define BIT_MASK_FREE_TXPG_SEQ 0xff -#define BIT_FREE_TXPG_SEQ(x) (((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ) -#define BIT_GET_FREE_TXPG_SEQ(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLPON_EMEM1_EN BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_LPLDH12_RSV1 BIT(31) -#define BIT_LPLDH12_RSV0 BIT(30) +#define BIT_LPLDH12_RSV1 BIT(31) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ - -#define BIT_SHIFT_LPLDH12_RSV 29 -#define BIT_MASK_LPLDH12_RSV 0x7 -#define BIT_LPLDH12_RSV(x) (((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV) -#define BIT_GET_LPLDH12_RSV(x) (((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV) - +#define BIT_R_SYM_WLPON_EMEM0_EN BIT(30) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_LPLDH12_SLP BIT(28) - -#define BIT_SHIFT_LPLDH12_VADJ 24 -#define BIT_MASK_LPLDH12_VADJ 0xf -#define BIT_LPLDH12_VADJ(x) (((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ) -#define BIT_GET_LPLDH12_VADJ(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ) - +#define BIT_LPLDH12_RSV0 BIT(30) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_PCIE_CALIB_EN BIT(17) +#define BIT_SHIFT_LPLDH12_RSV 29 +#define BIT_MASK_LPLDH12_RSV 0x7 +#define BIT_LPLDH12_RSV(x) \ + (((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV) +#define BITS_LPLDH12_RSV (BIT_MASK_LPLDH12_RSV << BIT_SHIFT_LPLDH12_RSV) +#define BIT_CLEAR_LPLDH12_RSV(x) ((x) & (~BITS_LPLDH12_RSV)) +#define BIT_GET_LPLDH12_RSV(x) \ + (((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV) +#define BIT_SET_LPLDH12_RSV(x, v) \ + (BIT_CLEAR_LPLDH12_RSV(x) | BIT_LPLDH12_RSV(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_LDH12_EN BIT(16) +#define BIT_LPLDH12_SLP BIT(28) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLPOFF_P4EN BIT(28) +#define BIT_R_SYM_WLPOFF_P3EN BIT(27) +#define BIT_R_SYM_WLPOFF_P2EN BIT(26) +#define BIT_R_SYM_WLPOFF_P1EN BIT(25) -/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MID_FREEPG_V1 16 -#define BIT_MASK_MID_FREEPG_V1 0xfff -#define BIT_MID_FREEPG_V1(x) (((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1) -#define BIT_GET_MID_FREEPG_V1(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_SHIFT_LPLDH12_VADJ 24 +#define BIT_MASK_LPLDH12_VADJ 0xf +#define BIT_LPLDH12_VADJ(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ) +#define BITS_LPLDH12_VADJ (BIT_MASK_LPLDH12_VADJ << BIT_SHIFT_LPLDH12_VADJ) +#define BIT_CLEAR_LPLDH12_VADJ(x) ((x) & (~BITS_LPLDH12_VADJ)) +#define BIT_GET_LPLDH12_VADJ(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ) +#define BIT_SET_LPLDH12_VADJ(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ(x) | BIT_LPLDH12_VADJ(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_WLBBOFF_BIG_PWC_EN BIT(14) -#define BIT_WLBBOFF_SMALL_PWC_EN BIT(13) -#define BIT_WLMACOFF_BIG_PWC_EN BIT(12) -#define BIT_WLPON_PWC_EN BIT(11) +#define BIT_R_SYM_WLPOFF_EN BIT(24) +#define BIT_R_SYM_WLPON_P3EN BIT(21) +#define BIT_R_SYM_WLPON_P2EN BIT(20) +#define BIT_R_SYM_WLPON_P1EN BIT(19) +#define BIT_R_SYM_WLPON_EN BIT(18) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_POW_REGU_P1 BIT(10) +#define BIT_PCIE_CALIB_EN BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_LDOV12W_EN BIT(8) +#define BIT_LDH12_EN BIT(16) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ +#define BIT_SHIFT_MID_FREEPG_V1 16 +#define BIT_MASK_MID_FREEPG_V1 0xfff +#define BIT_MID_FREEPG_V1(x) \ + (((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1) +#define BITS_MID_FREEPG_V1 (BIT_MASK_MID_FREEPG_V1 << BIT_SHIFT_MID_FREEPG_V1) +#define BIT_CLEAR_MID_FREEPG_V1(x) ((x) & (~BITS_MID_FREEPG_V1)) +#define BIT_GET_MID_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1) +#define BIT_SET_MID_FREEPG_V1(x, v) \ + (BIT_CLEAR_MID_FREEPG_V1(x) | BIT_MID_FREEPG_V1(v)) -/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_ANAPAR_RFC2 8 -#define BIT_MASK_ANAPAR_RFC2 0xff -#define BIT_ANAPAR_RFC2(x) (((x) & BIT_MASK_ANAPAR_RFC2) << BIT_SHIFT_ANAPAR_RFC2) -#define BIT_GET_ANAPAR_RFC2(x) (((x) >> BIT_SHIFT_ANAPAR_RFC2) & BIT_MASK_ANAPAR_RFC2) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_LDOV12D_STBY BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_EX_XTAL_DRV_DIGI BIT(7) -#define BIT_EX_XTAL_DRV_USB BIT(6) -#define BIT_EX_XTAL_DRV_AFE BIT(5) +#define BIT_BB_POWER_CUT_CTRL_BY_BB BIT(15) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ - -#define BIT_SHIFT_LDA12_VOADJ 4 -#define BIT_MASK_LDA12_VOADJ 0xf -#define BIT_LDA12_VOADJ(x) (((x) & BIT_MASK_LDA12_VOADJ) << BIT_SHIFT_LDA12_VOADJ) -#define BIT_GET_LDA12_VOADJ(x) (((x) >> BIT_SHIFT_LDA12_VOADJ) & BIT_MASK_LDA12_VOADJ) - +#define BIT_WLBBOFF_BIG_PWC_EN BIT(14) +#define BIT_WLBBOFF_SMALL_PWC_EN BIT(13) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_EX_XTAL_DRV_RF2 BIT(4) +#define BIT_POW_REGU_P3 BIT(12) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_REG_VOS BIT(3) +#define BIT_WLMACOFF_BIG_PWC_EN BIT(12) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_EX_XTAL_DRV_RF1 BIT(3) -#define BIT_POW_REGU_P0 BIT(2) +#define BIT_POW_REGU_P2 BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_LDA12_EN BIT(0) +#define BIT_WLPON_PWC_EN BIT(11) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_POW_PLL_LDO BIT(0) +#define BIT_POW_REGU_P1 BIT(10) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_MEM_DS_EN BIT(9) -/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HIQ_FREEPG_V1 0 -#define BIT_MASK_HIQ_FREEPG_V1 0xfff -#define BIT_HIQ_FREEPG_V1(x) (((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1) -#define BIT_GET_HIQ_FREEPG_V1(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLBBOFF1_P4_EN BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_LDOV12W_EN BIT(8) -/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_ANAPAR_RFC1 0 -#define BIT_MASK_ANAPAR_RFC1 0xff -#define BIT_ANAPAR_RFC1(x) (((x) & BIT_MASK_ANAPAR_RFC1) << BIT_SHIFT_ANAPAR_RFC1) -#define BIT_GET_ANAPAR_RFC1(x) (((x) >> BIT_SHIFT_ANAPAR_RFC1) & BIT_MASK_ANAPAR_RFC1) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLBBOFF1_P3_EN BIT(8) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_SHIFT_ANAPAR_RFC2 8 +#define BIT_MASK_ANAPAR_RFC2 0xff +#define BIT_ANAPAR_RFC2(x) \ + (((x) & BIT_MASK_ANAPAR_RFC2) << BIT_SHIFT_ANAPAR_RFC2) +#define BITS_ANAPAR_RFC2 (BIT_MASK_ANAPAR_RFC2 << BIT_SHIFT_ANAPAR_RFC2) +#define BIT_CLEAR_ANAPAR_RFC2(x) ((x) & (~BITS_ANAPAR_RFC2)) +#define BIT_GET_ANAPAR_RFC2(x) \ + (((x) >> BIT_SHIFT_ANAPAR_RFC2) & BIT_MASK_ANAPAR_RFC2) +#define BIT_SET_ANAPAR_RFC2(x, v) \ + (BIT_CLEAR_ANAPAR_RFC2(x) | BIT_ANAPAR_RFC2(v)) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif -#define BIT_AGPIO_GPE BIT(31) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_EX_XTAL_DRV_DIGI BIT(7) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_XQSEL_V3 BIT(31) +#define BIT_R_SYM_WLBBOFF1_P2_EN BIT(7) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_EX_XTAL_DRV_USB BIT(6) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_REG_CC 30 -#define BIT_MASK_REG_CC 0x3 -#define BIT_REG_CC(x) (((x) & BIT_MASK_REG_CC) << BIT_SHIFT_REG_CC) -#define BIT_GET_REG_CC(x) (((x) >> BIT_SHIFT_REG_CC) & BIT_MASK_REG_CC) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLBBOFF1_P1_EN BIT(6) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_CKDELAY_AFE_V1 BIT(30) +#define BIT_EX_XTAL_DRV_AFE BIT(5) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_CKDLY_DIG BIT(28) -#define BIT_CKDLY_USB BIT(27) +#define BIT_SHIFT_LDA12_VOADJ 4 +#define BIT_MASK_LDA12_VOADJ 0xf +#define BIT_LDA12_VOADJ(x) \ + (((x) & BIT_MASK_LDA12_VOADJ) << BIT_SHIFT_LDA12_VOADJ) +#define BITS_LDA12_VOADJ (BIT_MASK_LDA12_VOADJ << BIT_SHIFT_LDA12_VOADJ) +#define BIT_CLEAR_LDA12_VOADJ(x) ((x) & (~BITS_LDA12_VOADJ)) +#define BIT_GET_LDA12_VOADJ(x) \ + (((x) >> BIT_SHIFT_LDA12_VOADJ) & BIT_MASK_LDA12_VOADJ) +#define BIT_SET_LDA12_VOADJ(x, v) \ + (BIT_CLEAR_LDA12_VOADJ(x) | BIT_LDA12_VOADJ(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_EX_XTAL_DRV_RF2 BIT(4) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_XTAL_GPIO_V1 27 -#define BIT_MASK_XTAL_GPIO_V1 0x7 -#define BIT_XTAL_GPIO_V1(x) (((x) & BIT_MASK_XTAL_GPIO_V1) << BIT_SHIFT_XTAL_GPIO_V1) -#define BIT_GET_XTAL_GPIO_V1(x) (((x) >> BIT_SHIFT_XTAL_GPIO_V1) & BIT_MASK_XTAL_GPIO_V1) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLBBOFF_P4_EN BIT(4) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_CKDLY_AFE BIT(26) +#define BIT_REG_VOS BIT(3) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_EX_XTAL_DRV_RF1 BIT(3) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_XTAL_CAP_XI 25 -#define BIT_MASK_XTAL_CAP_XI 0x3f -#define BIT_XTAL_CAP_XI(x) (((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI) -#define BIT_GET_XTAL_CAP_XI(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_R_SYM_WLBBOFF_P3_EN BIT(3) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_POW_REGU_P0 BIT(2) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_XTAL_DIG_DRV_1_TO_0 25 -#define BIT_MASK_XTAL_DIG_DRV_1_TO_0 0x3 -#define BIT_XTAL_DIG_DRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) -#define BIT_GET_XTAL_DIG_DRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_XTAL_GDIG BIT(24) +#define BIT_R_SYM_WLBBOFF_P2_EN BIT(2) +#define BIT_R_SYM_WLBBOFF_P1_EN BIT(1) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ + +#define BIT_LDA12_EN BIT(0) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_XTAL_GPIO 23 -#define BIT_MASK_XTAL_GPIO 0x7 -#define BIT_XTAL_GPIO(x) (((x) & BIT_MASK_XTAL_GPIO) << BIT_SHIFT_XTAL_GPIO) -#define BIT_GET_XTAL_GPIO(x) (((x) >> BIT_SHIFT_XTAL_GPIO) & BIT_MASK_XTAL_GPIO) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_POW_PLL_LDO BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ +#define BIT_SHIFT_HIQ_FREEPG_V1 0 +#define BIT_MASK_HIQ_FREEPG_V1 0xfff +#define BIT_HIQ_FREEPG_V1(x) \ + (((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1) +#define BITS_HIQ_FREEPG_V1 (BIT_MASK_HIQ_FREEPG_V1 << BIT_SHIFT_HIQ_FREEPG_V1) +#define BIT_CLEAR_HIQ_FREEPG_V1(x) ((x) & (~BITS_HIQ_FREEPG_V1)) +#define BIT_GET_HIQ_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1) +#define BIT_SET_HIQ_FREEPG_V1(x, v) \ + (BIT_CLEAR_HIQ_FREEPG_V1(x) | BIT_HIQ_FREEPG_V1(v)) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_XTAL_DRV_DIGI 23 -#define BIT_MASK_XTAL_DRV_DIGI 0x3 -#define BIT_XTAL_DRV_DIGI(x) (((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI) -#define BIT_GET_XTAL_DRV_DIGI(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ -#define BIT_XTAL_DRV_USB_BIT1 BIT(22) +#define BIT_R_SYM_WLBBOFF_EN BIT(0) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ +#define BIT_SHIFT_ANAPAR_RFC1 0 +#define BIT_MASK_ANAPAR_RFC1 0xff +#define BIT_ANAPAR_RFC1(x) \ + (((x) & BIT_MASK_ANAPAR_RFC1) << BIT_SHIFT_ANAPAR_RFC1) +#define BITS_ANAPAR_RFC1 (BIT_MASK_ANAPAR_RFC1 << BIT_SHIFT_ANAPAR_RFC1) +#define BIT_CLEAR_ANAPAR_RFC1(x) ((x) & (~BITS_ANAPAR_RFC1)) +#define BIT_GET_ANAPAR_RFC1(x) \ + (((x) >> BIT_SHIFT_ANAPAR_RFC1) & BIT_MASK_ANAPAR_RFC1) +#define BIT_SET_ANAPAR_RFC1(x, v) \ + (BIT_CLEAR_ANAPAR_RFC1(x) | BIT_ANAPAR_RFC1(v)) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0 22 -#define BIT_MASK_XTAL_RDRV_RF2_1_TO_0 0x3 -#define BIT_XTAL_RDRV_RF2_1_TO_0(x) (((x) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0) << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) -#define BIT_GET_XTAL_RDRV_RF2_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_AGPIO_GPE BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GMN_4 BIT(21) +#define BIT_XQSEL_V3 BIT(31) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_REG_CC 30 +#define BIT_MASK_REG_CC 0x3 +#define BIT_REG_CC(x) (((x) & BIT_MASK_REG_CC) << BIT_SHIFT_REG_CC) +#define BITS_REG_CC (BIT_MASK_REG_CC << BIT_SHIFT_REG_CC) +#define BIT_CLEAR_REG_CC(x) ((x) & (~BITS_REG_CC)) +#define BIT_GET_REG_CC(x) (((x) >> BIT_SHIFT_REG_CC) & BIT_MASK_REG_CC) +#define BIT_SET_REG_CC(x, v) (BIT_CLEAR_REG_CC(x) | BIT_REG_CC(v)) -#define BIT_SHIFT_MAC_CLK_SEL 20 -#define BIT_MASK_MAC_CLK_SEL 0x3 -#define BIT_MAC_CLK_SEL(x) (((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL) -#define BIT_GET_MAC_CLK_SEL(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_CKDELAY_AFE_V1 BIT(30) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_DRV_USB_BIT0 BIT(19) +#define BIT_CKDLY_DIG BIT(28) +#define BIT_CKDLY_USB BIT(27) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_RDRV_1_TO_0 19 -#define BIT_MASK_XTAL_RDRV_1_TO_0 0x3 -#define BIT_XTAL_RDRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_RDRV_1_TO_0) << BIT_SHIFT_XTAL_RDRV_1_TO_0) -#define BIT_GET_XTAL_RDRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_RDRV_1_TO_0) & BIT_MASK_XTAL_RDRV_1_TO_0) - +#define BIT_SHIFT_XTAL_GPIO_V1 27 +#define BIT_MASK_XTAL_GPIO_V1 0x7 +#define BIT_XTAL_GPIO_V1(x) \ + (((x) & BIT_MASK_XTAL_GPIO_V1) << BIT_SHIFT_XTAL_GPIO_V1) +#define BITS_XTAL_GPIO_V1 (BIT_MASK_XTAL_GPIO_V1 << BIT_SHIFT_XTAL_GPIO_V1) +#define BIT_CLEAR_XTAL_GPIO_V1(x) ((x) & (~BITS_XTAL_GPIO_V1)) +#define BIT_GET_XTAL_GPIO_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_GPIO_V1) & BIT_MASK_XTAL_GPIO_V1) +#define BIT_SET_XTAL_GPIO_V1(x, v) \ + (BIT_CLEAR_XTAL_GPIO_V1(x) | BIT_XTAL_GPIO_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_CKDLY_AFE BIT(26) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_XTAL_DIG_DRV 18 -#define BIT_MASK_XTAL_DIG_DRV 0x3 -#define BIT_XTAL_DIG_DRV(x) (((x) & BIT_MASK_XTAL_DIG_DRV) << BIT_SHIFT_XTAL_DIG_DRV) -#define BIT_GET_XTAL_DIG_DRV(x) (((x) >> BIT_SHIFT_XTAL_DIG_DRV) & BIT_MASK_XTAL_DIG_DRV) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_CAP_XI 25 +#define BIT_MASK_XTAL_CAP_XI 0x3f +#define BIT_XTAL_CAP_XI(x) \ + (((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI) +#define BITS_XTAL_CAP_XI (BIT_MASK_XTAL_CAP_XI << BIT_SHIFT_XTAL_CAP_XI) +#define BIT_CLEAR_XTAL_CAP_XI(x) ((x) & (~BITS_XTAL_CAP_XI)) +#define BIT_GET_XTAL_CAP_XI(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI) +#define BIT_SET_XTAL_CAP_XI(x, v) \ + (BIT_CLEAR_XTAL_CAP_XI(x) | BIT_XTAL_CAP_XI(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GMP_4 BIT(18) +#define BIT_SHIFT_XTAL_DIG_DRV_1_TO_0 25 +#define BIT_MASK_XTAL_DIG_DRV_1_TO_0 0x3 +#define BIT_XTAL_DIG_DRV_1_TO_0(x) \ + (((x) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) +#define BITS_XTAL_DIG_DRV_1_TO_0 \ + (BIT_MASK_XTAL_DIG_DRV_1_TO_0 << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) +#define BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) ((x) & (~BITS_XTAL_DIG_DRV_1_TO_0)) +#define BIT_GET_XTAL_DIG_DRV_1_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) +#define BIT_SET_XTAL_DIG_DRV_1_TO_0(x, v) \ + (BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) | BIT_XTAL_DIG_DRV_1_TO_0(v)) -#endif +#define BIT_XTAL_GDIG BIT(24) +#endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GATE_DIG BIT(17) +#define BIT_SHIFT_XTAL_GPIO 23 +#define BIT_MASK_XTAL_GPIO 0x7 +#define BIT_XTAL_GPIO(x) (((x) & BIT_MASK_XTAL_GPIO) << BIT_SHIFT_XTAL_GPIO) +#define BITS_XTAL_GPIO (BIT_MASK_XTAL_GPIO << BIT_SHIFT_XTAL_GPIO) +#define BIT_CLEAR_XTAL_GPIO(x) ((x) & (~BITS_XTAL_GPIO)) +#define BIT_GET_XTAL_GPIO(x) (((x) >> BIT_SHIFT_XTAL_GPIO) & BIT_MASK_XTAL_GPIO) +#define BIT_SET_XTAL_GPIO(x, v) (BIT_CLEAR_XTAL_GPIO(x) | BIT_XTAL_GPIO(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_DRV_DIGI 23 +#define BIT_MASK_XTAL_DRV_DIGI 0x3 +#define BIT_XTAL_DRV_DIGI(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI) +#define BITS_XTAL_DRV_DIGI (BIT_MASK_XTAL_DRV_DIGI << BIT_SHIFT_XTAL_DRV_DIGI) +#define BIT_CLEAR_XTAL_DRV_DIGI(x) ((x) & (~BITS_XTAL_DRV_DIGI)) +#define BIT_GET_XTAL_DRV_DIGI(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI) +#define BIT_SET_XTAL_DRV_DIGI(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI(x) | BIT_XTAL_DRV_DIGI(v)) -#define BIT_SHIFT_XTAL_DRV_AFE 17 -#define BIT_MASK_XTAL_DRV_AFE 0x3 -#define BIT_XTAL_DRV_AFE(x) (((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE) -#define BIT_GET_XTAL_DRV_AFE(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE) - +#define BIT_XTAL_DRV_USB_BIT1 BIT(22) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_XTAL_DRV_RF_LATCH_V2 BIT(22) -/* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ +#endif +#if (HALMAC_8814A_SUPPORT) -#define BIT_SHIFT_PUB_FREEPG_V1 16 -#define BIT_MASK_PUB_FREEPG_V1 0xfff -#define BIT_PUB_FREEPG_V1(x) (((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1) -#define BIT_GET_PUB_FREEPG_V1(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0 22 +#define BIT_MASK_XTAL_RDRV_RF2_1_TO_0 0x3 +#define BIT_XTAL_RDRV_RF2_1_TO_0(x) \ + (((x) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0) \ + << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) +#define BITS_XTAL_RDRV_RF2_1_TO_0 \ + (BIT_MASK_XTAL_RDRV_RF2_1_TO_0 << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) +#define BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_RF2_1_TO_0)) +#define BIT_GET_XTAL_RDRV_RF2_1_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) & \ + BIT_MASK_XTAL_RDRV_RF2_1_TO_0) +#define BIT_SET_XTAL_RDRV_RF2_1_TO_0(x, v) \ + (BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) | BIT_XTAL_RDRV_RF2_1_TO_0(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_ADRV_1_TO_0 16 -#define BIT_MASK_XTAL_ADRV_1_TO_0 0x3 -#define BIT_XTAL_ADRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_ADRV_1_TO_0) << BIT_SHIFT_XTAL_ADRV_1_TO_0) -#define BIT_GET_XTAL_ADRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_ADRV_1_TO_0) & BIT_MASK_XTAL_ADRV_1_TO_0) - +#define BIT_XTAL_GMN_4 BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_MAC_CLK_SEL 20 +#define BIT_MASK_MAC_CLK_SEL 0x3 +#define BIT_MAC_CLK_SEL(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL) +#define BITS_MAC_CLK_SEL (BIT_MASK_MAC_CLK_SEL << BIT_SHIFT_MAC_CLK_SEL) +#define BIT_CLEAR_MAC_CLK_SEL(x) ((x) & (~BITS_MAC_CLK_SEL)) +#define BIT_GET_MAC_CLK_SEL(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL) +#define BIT_SET_MAC_CLK_SEL(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL(x) | BIT_MAC_CLK_SEL(v)) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_XTAL_RF_DRV 15 -#define BIT_MASK_XTAL_RF_DRV 0x3 -#define BIT_XTAL_RF_DRV(x) (((x) & BIT_MASK_XTAL_RF_DRV) << BIT_SHIFT_XTAL_RF_DRV) -#define BIT_GET_XTAL_RF_DRV(x) (((x) >> BIT_SHIFT_XTAL_RF_DRV) & BIT_MASK_XTAL_RF_DRV) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_XTAL_DRV_USB_BIT0 BIT(19) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_RDRV_1_TO_0 19 +#define BIT_MASK_XTAL_RDRV_1_TO_0 0x3 +#define BIT_XTAL_RDRV_1_TO_0(x) \ + (((x) & BIT_MASK_XTAL_RDRV_1_TO_0) << BIT_SHIFT_XTAL_RDRV_1_TO_0) +#define BITS_XTAL_RDRV_1_TO_0 \ + (BIT_MASK_XTAL_RDRV_1_TO_0 << BIT_SHIFT_XTAL_RDRV_1_TO_0) +#define BIT_CLEAR_XTAL_RDRV_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_1_TO_0)) +#define BIT_GET_XTAL_RDRV_1_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_RDRV_1_TO_0) & BIT_MASK_XTAL_RDRV_1_TO_0) +#define BIT_SET_XTAL_RDRV_1_TO_0(x, v) \ + (BIT_CLEAR_XTAL_RDRV_1_TO_0(x) | BIT_XTAL_RDRV_1_TO_0(v)) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_XTAL_DRV_RF2 15 -#define BIT_MASK_XTAL_DRV_RF2 0x3 -#define BIT_XTAL_DRV_RF2(x) (((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2) -#define BIT_GET_XTAL_DRV_RF2(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_DIG_DRV 18 +#define BIT_MASK_XTAL_DIG_DRV 0x3 +#define BIT_XTAL_DIG_DRV(x) \ + (((x) & BIT_MASK_XTAL_DIG_DRV) << BIT_SHIFT_XTAL_DIG_DRV) +#define BITS_XTAL_DIG_DRV (BIT_MASK_XTAL_DIG_DRV << BIT_SHIFT_XTAL_DIG_DRV) +#define BIT_CLEAR_XTAL_DIG_DRV(x) ((x) & (~BITS_XTAL_DIG_DRV)) +#define BIT_GET_XTAL_DIG_DRV(x) \ + (((x) >> BIT_SHIFT_XTAL_DIG_DRV) & BIT_MASK_XTAL_DIG_DRV) +#define BIT_SET_XTAL_DIG_DRV(x, v) \ + (BIT_CLEAR_XTAL_DIG_DRV(x) | BIT_XTAL_DIG_DRV(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GAFE BIT(15) +#define BIT_XTAL_GMP_4 BIT(18) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_RF_GATE BIT(14) +#define BIT_XTAL_GATE_DIG BIT(17) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_DRV_AFE 17 +#define BIT_MASK_XTAL_DRV_AFE 0x3 +#define BIT_XTAL_DRV_AFE(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE) +#define BITS_XTAL_DRV_AFE (BIT_MASK_XTAL_DRV_AFE << BIT_SHIFT_XTAL_DRV_AFE) +#define BIT_CLEAR_XTAL_DRV_AFE(x) ((x) & (~BITS_XTAL_DRV_AFE)) +#define BIT_GET_XTAL_DRV_AFE(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE) +#define BIT_SET_XTAL_DRV_AFE(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE(x) | BIT_XTAL_DRV_AFE(v)) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_XTAL_DRV_RF1 13 -#define BIT_MASK_XTAL_DRV_RF1 0x3 -#define BIT_XTAL_DRV_RF1(x) (((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1) -#define BIT_GET_XTAL_DRV_RF1(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1) +/* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ +#define BIT_SHIFT_PUB_FREEPG_V1 16 +#define BIT_MASK_PUB_FREEPG_V1 0xfff +#define BIT_PUB_FREEPG_V1(x) \ + (((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1) +#define BITS_PUB_FREEPG_V1 (BIT_MASK_PUB_FREEPG_V1 << BIT_SHIFT_PUB_FREEPG_V1) +#define BIT_CLEAR_PUB_FREEPG_V1(x) ((x) & (~BITS_PUB_FREEPG_V1)) +#define BIT_GET_PUB_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1) +#define BIT_SET_PUB_FREEPG_V1(x, v) \ + (BIT_CLEAR_PUB_FREEPG_V1(x) | BIT_PUB_FREEPG_V1(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_DDRV_1_TO_0 13 -#define BIT_MASK_XTAL_DDRV_1_TO_0 0x3 -#define BIT_XTAL_DDRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_DDRV_1_TO_0) << BIT_SHIFT_XTAL_DDRV_1_TO_0) -#define BIT_GET_XTAL_DDRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_DDRV_1_TO_0) & BIT_MASK_XTAL_DDRV_1_TO_0) - +#define BIT_SHIFT_XTAL_ADRV_1_TO_0 16 +#define BIT_MASK_XTAL_ADRV_1_TO_0 0x3 +#define BIT_XTAL_ADRV_1_TO_0(x) \ + (((x) & BIT_MASK_XTAL_ADRV_1_TO_0) << BIT_SHIFT_XTAL_ADRV_1_TO_0) +#define BITS_XTAL_ADRV_1_TO_0 \ + (BIT_MASK_XTAL_ADRV_1_TO_0 << BIT_SHIFT_XTAL_ADRV_1_TO_0) +#define BIT_CLEAR_XTAL_ADRV_1_TO_0(x) ((x) & (~BITS_XTAL_ADRV_1_TO_0)) +#define BIT_GET_XTAL_ADRV_1_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_ADRV_1_TO_0) & BIT_MASK_XTAL_ADRV_1_TO_0) +#define BIT_SET_XTAL_ADRV_1_TO_0(x, v) \ + (BIT_CLEAR_XTAL_ADRV_1_TO_0(x) | BIT_XTAL_ADRV_1_TO_0(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_AFE_DRV 12 -#define BIT_MASK_XTAL_AFE_DRV 0x3 -#define BIT_XTAL_AFE_DRV(x) (((x) & BIT_MASK_XTAL_AFE_DRV) << BIT_SHIFT_XTAL_AFE_DRV) -#define BIT_GET_XTAL_AFE_DRV(x) (((x) >> BIT_SHIFT_XTAL_AFE_DRV) & BIT_MASK_XTAL_AFE_DRV) - +#define BIT_SHIFT_XTAL_RF_DRV 15 +#define BIT_MASK_XTAL_RF_DRV 0x3 +#define BIT_XTAL_RF_DRV(x) \ + (((x) & BIT_MASK_XTAL_RF_DRV) << BIT_SHIFT_XTAL_RF_DRV) +#define BITS_XTAL_RF_DRV (BIT_MASK_XTAL_RF_DRV << BIT_SHIFT_XTAL_RF_DRV) +#define BIT_CLEAR_XTAL_RF_DRV(x) ((x) & (~BITS_XTAL_RF_DRV)) +#define BIT_GET_XTAL_RF_DRV(x) \ + (((x) >> BIT_SHIFT_XTAL_RF_DRV) & BIT_MASK_XTAL_RF_DRV) +#define BIT_SET_XTAL_RF_DRV(x, v) \ + (BIT_CLEAR_XTAL_RF_DRV(x) | BIT_XTAL_RF_DRV(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_DELAY_DIGI BIT(12) +#define BIT_SHIFT_XTAL_DRV_RF2 15 +#define BIT_MASK_XTAL_DRV_RF2 0x3 +#define BIT_XTAL_DRV_RF2(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2) +#define BITS_XTAL_DRV_RF2 (BIT_MASK_XTAL_DRV_RF2 << BIT_SHIFT_XTAL_DRV_RF2) +#define BIT_CLEAR_XTAL_DRV_RF2(x) ((x) & (~BITS_XTAL_DRV_RF2)) +#define BIT_GET_XTAL_DRV_RF2(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2) +#define BIT_SET_XTAL_DRV_RF2(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2(x) | BIT_XTAL_DRV_RF2(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GUSB BIT(12) +#define BIT_XTAL_GAFE BIT(15) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GATE_AFE BIT(11) +#define BIT_XTAL_RF_GATE BIT(14) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_DELAY_USB BIT(11) -#define BIT_XTAL_DELAY_AFE BIT(10) +#define BIT_SHIFT_XTAL_DDRV_1_TO_0 13 +#define BIT_MASK_XTAL_DDRV_1_TO_0 0x3 +#define BIT_XTAL_DDRV_1_TO_0(x) \ + (((x) & BIT_MASK_XTAL_DDRV_1_TO_0) << BIT_SHIFT_XTAL_DDRV_1_TO_0) +#define BITS_XTAL_DDRV_1_TO_0 \ + (BIT_MASK_XTAL_DDRV_1_TO_0 << BIT_SHIFT_XTAL_DDRV_1_TO_0) +#define BIT_CLEAR_XTAL_DDRV_1_TO_0(x) ((x) & (~BITS_XTAL_DDRV_1_TO_0)) +#define BIT_GET_XTAL_DDRV_1_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DDRV_1_TO_0) & BIT_MASK_XTAL_DDRV_1_TO_0) +#define BIT_SET_XTAL_DDRV_1_TO_0(x, v) \ + (BIT_CLEAR_XTAL_DDRV_1_TO_0(x) | BIT_XTAL_DDRV_1_TO_0(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_AFE_DRV 12 +#define BIT_MASK_XTAL_AFE_DRV 0x3 +#define BIT_XTAL_AFE_DRV(x) \ + (((x) & BIT_MASK_XTAL_AFE_DRV) << BIT_SHIFT_XTAL_AFE_DRV) +#define BITS_XTAL_AFE_DRV (BIT_MASK_XTAL_AFE_DRV << BIT_SHIFT_XTAL_AFE_DRV) +#define BIT_CLEAR_XTAL_AFE_DRV(x) ((x) & (~BITS_XTAL_AFE_DRV)) +#define BIT_GET_XTAL_AFE_DRV(x) \ + (((x) >> BIT_SHIFT_XTAL_AFE_DRV) & BIT_MASK_XTAL_AFE_DRV) +#define BIT_SET_XTAL_AFE_DRV(x, v) \ + (BIT_CLEAR_XTAL_AFE_DRV(x) | BIT_XTAL_AFE_DRV(v)) -#define BIT_SHIFT_XTAL_USB_DRV 9 -#define BIT_MASK_XTAL_USB_DRV 0x3 -#define BIT_XTAL_USB_DRV(x) (((x) & BIT_MASK_XTAL_USB_DRV) << BIT_SHIFT_XTAL_USB_DRV) -#define BIT_GET_XTAL_USB_DRV(x) (((x) >> BIT_SHIFT_XTAL_USB_DRV) & BIT_MASK_XTAL_USB_DRV) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_XTAL_DELAY_DIGI BIT(12) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_LP_V1 BIT(9) +#define BIT_XTAL_GUSB BIT(12) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GATE_USB BIT(8) +#define BIT_XTAL_GATE_AFE BIT(11) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_GM_SEP_V1 BIT(8) +#define BIT_XTAL_DELAY_USB BIT(11) +#define BIT_XTAL_DELAY_AFE BIT(10) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_GMN_3_TO_0 8 -#define BIT_MASK_XTAL_GMN_3_TO_0 0xf -#define BIT_XTAL_GMN_3_TO_0(x) (((x) & BIT_MASK_XTAL_GMN_3_TO_0) << BIT_SHIFT_XTAL_GMN_3_TO_0) -#define BIT_GET_XTAL_GMN_3_TO_0(x) (((x) >> BIT_SHIFT_XTAL_GMN_3_TO_0) & BIT_MASK_XTAL_GMN_3_TO_0) - +#define BIT_SHIFT_XTAL_USB_DRV 9 +#define BIT_MASK_XTAL_USB_DRV 0x3 +#define BIT_XTAL_USB_DRV(x) \ + (((x) & BIT_MASK_XTAL_USB_DRV) << BIT_SHIFT_XTAL_USB_DRV) +#define BITS_XTAL_USB_DRV (BIT_MASK_XTAL_USB_DRV << BIT_SHIFT_XTAL_USB_DRV) +#define BIT_CLEAR_XTAL_USB_DRV(x) ((x) & (~BITS_XTAL_USB_DRV)) +#define BIT_GET_XTAL_USB_DRV(x) \ + (((x) >> BIT_SHIFT_XTAL_USB_DRV) & BIT_MASK_XTAL_USB_DRV) +#define BIT_SET_XTAL_USB_DRV(x, v) \ + (BIT_CLEAR_XTAL_USB_DRV(x) | BIT_XTAL_USB_DRV(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_LDO_VREF_V1 BIT(7) +#define BIT_XTAL_LP_V1 BIT(9) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_LDO_VREF 7 -#define BIT_MASK_XTAL_LDO_VREF 0x7 -#define BIT_XTAL_LDO_VREF(x) (((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF) -#define BIT_GET_XTAL_LDO_VREF(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF) - +#define BIT_XTAL_GATE_USB BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_XQSEL_RF BIT(6) -#define BIT_XTAL_XQSEL BIT(5) +#define BIT_XTAL_GM_SEP_V1 BIT(8) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_GMN_3_TO_0 8 +#define BIT_MASK_XTAL_GMN_3_TO_0 0xf +#define BIT_XTAL_GMN_3_TO_0(x) \ + (((x) & BIT_MASK_XTAL_GMN_3_TO_0) << BIT_SHIFT_XTAL_GMN_3_TO_0) +#define BITS_XTAL_GMN_3_TO_0 \ + (BIT_MASK_XTAL_GMN_3_TO_0 << BIT_SHIFT_XTAL_GMN_3_TO_0) +#define BIT_CLEAR_XTAL_GMN_3_TO_0(x) ((x) & (~BITS_XTAL_GMN_3_TO_0)) +#define BIT_GET_XTAL_GMN_3_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_3_TO_0) & BIT_MASK_XTAL_GMN_3_TO_0) +#define BIT_SET_XTAL_GMN_3_TO_0(x, v) \ + (BIT_CLEAR_XTAL_GMN_3_TO_0(x) | BIT_XTAL_GMN_3_TO_0(v)) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_XTAL_GMP 4 -#define BIT_MASK_XTAL_GMP 0xf -#define BIT_XTAL_GMP(x) (((x) & BIT_MASK_XTAL_GMP) << BIT_SHIFT_XTAL_GMP) -#define BIT_GET_XTAL_GMP(x) (((x) >> BIT_SHIFT_XTAL_GMP) & BIT_MASK_XTAL_GMP) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_XTAL_LDO_VREF_V1 BIT(7) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_LDO_VREF 7 +#define BIT_MASK_XTAL_LDO_VREF 0x7 +#define BIT_XTAL_LDO_VREF(x) \ + (((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF) +#define BITS_XTAL_LDO_VREF (BIT_MASK_XTAL_LDO_VREF << BIT_SHIFT_XTAL_LDO_VREF) +#define BIT_CLEAR_XTAL_LDO_VREF(x) ((x) & (~BITS_XTAL_LDO_VREF)) +#define BIT_GET_XTAL_LDO_VREF(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF) +#define BIT_SET_XTAL_LDO_VREF(x, v) \ + (BIT_CLEAR_XTAL_LDO_VREF(x) | BIT_XTAL_LDO_VREF(v)) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_XTAL_GMP_3_TO_0 4 -#define BIT_MASK_XTAL_GMP_3_TO_0 0xf -#define BIT_XTAL_GMP_3_TO_0(x) (((x) & BIT_MASK_XTAL_GMP_3_TO_0) << BIT_SHIFT_XTAL_GMP_3_TO_0) -#define BIT_GET_XTAL_GMP_3_TO_0(x) (((x) >> BIT_SHIFT_XTAL_GMP_3_TO_0) & BIT_MASK_XTAL_GMP_3_TO_0) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_XTAL_XQSEL_RF BIT(6) +#define BIT_XTAL_XQSEL BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_GMP 4 +#define BIT_MASK_XTAL_GMP 0xf +#define BIT_XTAL_GMP(x) (((x) & BIT_MASK_XTAL_GMP) << BIT_SHIFT_XTAL_GMP) +#define BITS_XTAL_GMP (BIT_MASK_XTAL_GMP << BIT_SHIFT_XTAL_GMP) +#define BIT_CLEAR_XTAL_GMP(x) ((x) & (~BITS_XTAL_GMP)) +#define BIT_GET_XTAL_GMP(x) (((x) >> BIT_SHIFT_XTAL_GMP) & BIT_MASK_XTAL_GMP) +#define BIT_SET_XTAL_GMP(x, v) (BIT_CLEAR_XTAL_GMP(x) | BIT_XTAL_GMP(v)) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_XTAL_GMN_V1 3 -#define BIT_MASK_XTAL_GMN_V1 0x3 -#define BIT_XTAL_GMN_V1(x) (((x) & BIT_MASK_XTAL_GMN_V1) << BIT_SHIFT_XTAL_GMN_V1) -#define BIT_GET_XTAL_GMN_V1(x) (((x) >> BIT_SHIFT_XTAL_GMN_V1) & BIT_MASK_XTAL_GMN_V1) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_GMP_3_TO_0 4 +#define BIT_MASK_XTAL_GMP_3_TO_0 0xf +#define BIT_XTAL_GMP_3_TO_0(x) \ + (((x) & BIT_MASK_XTAL_GMP_3_TO_0) << BIT_SHIFT_XTAL_GMP_3_TO_0) +#define BITS_XTAL_GMP_3_TO_0 \ + (BIT_MASK_XTAL_GMP_3_TO_0 << BIT_SHIFT_XTAL_GMP_3_TO_0) +#define BIT_CLEAR_XTAL_GMP_3_TO_0(x) ((x) & (~BITS_XTAL_GMP_3_TO_0)) +#define BIT_GET_XTAL_GMP_3_TO_0(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_3_TO_0) & BIT_MASK_XTAL_GMP_3_TO_0) +#define BIT_SET_XTAL_GMP_3_TO_0(x, v) \ + (BIT_CLEAR_XTAL_GMP_3_TO_0(x) | BIT_XTAL_GMP_3_TO_0(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_GMN_V2 3 +#define BIT_MASK_XTAL_GMN_V2 0x3 +#define BIT_XTAL_GMN_V2(x) \ + (((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2) +#define BITS_XTAL_GMN_V2 (BIT_MASK_XTAL_GMN_V2 << BIT_SHIFT_XTAL_GMN_V2) +#define BIT_CLEAR_XTAL_GMN_V2(x) ((x) & (~BITS_XTAL_GMN_V2)) +#define BIT_GET_XTAL_GMN_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2) +#define BIT_SET_XTAL_GMN_V2(x, v) \ + (BIT_CLEAR_XTAL_GMN_V2(x) | BIT_XTAL_GMN_V2(v)) -/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_XTAL_GMN_V2 3 -#define BIT_MASK_XTAL_GMN_V2 0x3 -#define BIT_XTAL_GMN_V2(x) (((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2) -#define BIT_GET_XTAL_GMN_V2(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2) +/* 2 REG_AFE_CTRL1 (Offset 0x0024) */ +#define BIT_SHIFT_XTAL_GMN_V1 3 +#define BIT_MASK_XTAL_GMN_V1 0x3 +#define BIT_XTAL_GMN_V1(x) \ + (((x) & BIT_MASK_XTAL_GMN_V1) << BIT_SHIFT_XTAL_GMN_V1) +#define BITS_XTAL_GMN_V1 (BIT_MASK_XTAL_GMN_V1 << BIT_SHIFT_XTAL_GMN_V1) +#define BIT_CLEAR_XTAL_GMN_V1(x) ((x) & (~BITS_XTAL_GMN_V1)) +#define BIT_GET_XTAL_GMN_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V1) & BIT_MASK_XTAL_GMN_V1) +#define BIT_SET_XTAL_GMN_V1(x, v) \ + (BIT_CLEAR_XTAL_GMN_V1(x) | BIT_XTAL_GMN_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_LDO_VCM 2 -#define BIT_MASK_XTAL_LDO_VCM 0x3 -#define BIT_XTAL_LDO_VCM(x) (((x) & BIT_MASK_XTAL_LDO_VCM) << BIT_SHIFT_XTAL_LDO_VCM) -#define BIT_GET_XTAL_LDO_VCM(x) (((x) >> BIT_SHIFT_XTAL_LDO_VCM) & BIT_MASK_XTAL_LDO_VCM) - +#define BIT_SHIFT_XTAL_LDO_VCM 2 +#define BIT_MASK_XTAL_LDO_VCM 0x3 +#define BIT_XTAL_LDO_VCM(x) \ + (((x) & BIT_MASK_XTAL_LDO_VCM) << BIT_SHIFT_XTAL_LDO_VCM) +#define BITS_XTAL_LDO_VCM (BIT_MASK_XTAL_LDO_VCM << BIT_SHIFT_XTAL_LDO_VCM) +#define BIT_CLEAR_XTAL_LDO_VCM(x) ((x) & (~BITS_XTAL_LDO_VCM)) +#define BIT_GET_XTAL_LDO_VCM(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VCM) & BIT_MASK_XTAL_LDO_VCM) +#define BIT_SET_XTAL_LDO_VCM(x, v) \ + (BIT_CLEAR_XTAL_LDO_VCM(x) | BIT_XTAL_LDO_VCM(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_DRV_LDO_VCM_1_TO_0 2 -#define BIT_MASK_DRV_LDO_VCM_1_TO_0 0x3 -#define BIT_DRV_LDO_VCM_1_TO_0(x) (((x) & BIT_MASK_DRV_LDO_VCM_1_TO_0) << BIT_SHIFT_DRV_LDO_VCM_1_TO_0) -#define BIT_GET_DRV_LDO_VCM_1_TO_0(x) (((x) >> BIT_SHIFT_DRV_LDO_VCM_1_TO_0) & BIT_MASK_DRV_LDO_VCM_1_TO_0) - +#define BIT_SHIFT_DRV_LDO_VCM_1_TO_0 2 +#define BIT_MASK_DRV_LDO_VCM_1_TO_0 0x3 +#define BIT_DRV_LDO_VCM_1_TO_0(x) \ + (((x) & BIT_MASK_DRV_LDO_VCM_1_TO_0) << BIT_SHIFT_DRV_LDO_VCM_1_TO_0) +#define BITS_DRV_LDO_VCM_1_TO_0 \ + (BIT_MASK_DRV_LDO_VCM_1_TO_0 << BIT_SHIFT_DRV_LDO_VCM_1_TO_0) +#define BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) ((x) & (~BITS_DRV_LDO_VCM_1_TO_0)) +#define BIT_GET_DRV_LDO_VCM_1_TO_0(x) \ + (((x) >> BIT_SHIFT_DRV_LDO_VCM_1_TO_0) & BIT_MASK_DRV_LDO_VCM_1_TO_0) +#define BIT_SET_DRV_LDO_VCM_1_TO_0(x, v) \ + (BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) | BIT_DRV_LDO_VCM_1_TO_0(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_DUMMY BIT(1) +#define BIT_XTAL_DUMMY BIT(1) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_GMP_V1 1 -#define BIT_MASK_XTAL_GMP_V1 0x3 -#define BIT_XTAL_GMP_V1(x) (((x) & BIT_MASK_XTAL_GMP_V1) << BIT_SHIFT_XTAL_GMP_V1) -#define BIT_GET_XTAL_GMP_V1(x) (((x) >> BIT_SHIFT_XTAL_GMP_V1) & BIT_MASK_XTAL_GMP_V1) - +#define BIT_SHIFT_XTAL_GMP_V2 1 +#define BIT_MASK_XTAL_GMP_V2 0x3 +#define BIT_XTAL_GMP_V2(x) \ + (((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2) +#define BITS_XTAL_GMP_V2 (BIT_MASK_XTAL_GMP_V2 << BIT_SHIFT_XTAL_GMP_V2) +#define BIT_CLEAR_XTAL_GMP_V2(x) ((x) & (~BITS_XTAL_GMP_V2)) +#define BIT_GET_XTAL_GMP_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2) +#define BIT_SET_XTAL_GMP_V2(x, v) \ + (BIT_CLEAR_XTAL_GMP_V2(x) | BIT_XTAL_GMP_V2(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XQSEL_RF_INITIAL_V1 BIT(1) +#define BIT_SHIFT_XTAL_GMP_V1 1 +#define BIT_MASK_XTAL_GMP_V1 0x3 +#define BIT_XTAL_GMP_V1(x) \ + (((x) & BIT_MASK_XTAL_GMP_V1) << BIT_SHIFT_XTAL_GMP_V1) +#define BITS_XTAL_GMP_V1 (BIT_MASK_XTAL_GMP_V1 << BIT_SHIFT_XTAL_GMP_V1) +#define BIT_CLEAR_XTAL_GMP_V1(x) ((x) & (~BITS_XTAL_GMP_V1)) +#define BIT_GET_XTAL_GMP_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V1) & BIT_MASK_XTAL_GMP_V1) +#define BIT_SET_XTAL_GMP_V1(x, v) \ + (BIT_CLEAR_XTAL_GMP_V1(x) | BIT_XTAL_GMP_V1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ - -#define BIT_SHIFT_XTAL_GMP_V2 1 -#define BIT_MASK_XTAL_GMP_V2 0x3 -#define BIT_XTAL_GMP_V2(x) (((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2) -#define BIT_GET_XTAL_GMP_V2(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2) - +#define BIT_XQSEL_RF_INITIAL_V1 BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ -#define BIT_XTAL_EN BIT(0) +#define BIT_XTAL_EN BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ - -#define BIT_SHIFT_LOW_FREEPG_V1 0 -#define BIT_MASK_LOW_FREEPG_V1 0xfff -#define BIT_LOW_FREEPG_V1(x) (((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1) -#define BIT_GET_LOW_FREEPG_V1(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1) - +#define BIT_SHIFT_LOW_FREEPG_V1 0 +#define BIT_MASK_LOW_FREEPG_V1 0xfff +#define BIT_LOW_FREEPG_V1(x) \ + (((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1) +#define BITS_LOW_FREEPG_V1 (BIT_MASK_LOW_FREEPG_V1 << BIT_SHIFT_LOW_FREEPG_V1) +#define BIT_CLEAR_LOW_FREEPG_V1(x) ((x) & (~BITS_LOW_FREEPG_V1)) +#define BIT_GET_LOW_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1) +#define BIT_SET_LOW_FREEPG_V1(x, v) \ + (BIT_CLEAR_LOW_FREEPG_V1(x) | BIT_LOW_FREEPG_V1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_SHIFT_REG_C3_V4 30 +#define BIT_MASK_REG_C3_V4 0x3 +#define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4) +#define BITS_REG_C3_V4 (BIT_MASK_REG_C3_V4 << BIT_SHIFT_REG_C3_V4) +#define BIT_CLEAR_REG_C3_V4(x) ((x) & (~BITS_REG_C3_V4)) +#define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4) +#define BIT_SET_REG_C3_V4(x, v) (BIT_CLEAR_REG_C3_V4(x) | BIT_REG_C3_V4(v)) -#define BIT_SHIFT_REG_C3_V4 30 -#define BIT_MASK_REG_C3_V4 0x3 -#define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4) -#define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4) - -#define BIT_REG_CP_BIT1 BIT(29) +#define BIT_REG_CP_BIT1 BIT(29) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_XTAL_GMN 28 -#define BIT_MASK_XTAL_GMN 0xf -#define BIT_XTAL_GMN(x) (((x) & BIT_MASK_XTAL_GMN) << BIT_SHIFT_XTAL_GMN) -#define BIT_GET_XTAL_GMN(x) (((x) >> BIT_SHIFT_XTAL_GMN) & BIT_MASK_XTAL_GMN) - +#define BIT_SHIFT_XTAL_GMN 28 +#define BIT_MASK_XTAL_GMN 0xf +#define BIT_XTAL_GMN(x) (((x) & BIT_MASK_XTAL_GMN) << BIT_SHIFT_XTAL_GMN) +#define BITS_XTAL_GMN (BIT_MASK_XTAL_GMN << BIT_SHIFT_XTAL_GMN) +#define BIT_CLEAR_XTAL_GMN(x) ((x) & (~BITS_XTAL_GMN)) +#define BIT_GET_XTAL_GMN(x) (((x) >> BIT_SHIFT_XTAL_GMN) & BIT_MASK_XTAL_GMN) +#define BIT_SET_XTAL_GMN(x, v) (BIT_CLEAR_XTAL_GMN(x) | BIT_XTAL_GMN(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_SHIFT_IOOFFSET_3_TO_0 28 +#define BIT_MASK_IOOFFSET_3_TO_0 0xf +#define BIT_IOOFFSET_3_TO_0(x) \ + (((x) & BIT_MASK_IOOFFSET_3_TO_0) << BIT_SHIFT_IOOFFSET_3_TO_0) +#define BITS_IOOFFSET_3_TO_0 \ + (BIT_MASK_IOOFFSET_3_TO_0 << BIT_SHIFT_IOOFFSET_3_TO_0) +#define BIT_CLEAR_IOOFFSET_3_TO_0(x) ((x) & (~BITS_IOOFFSET_3_TO_0)) +#define BIT_GET_IOOFFSET_3_TO_0(x) \ + (((x) >> BIT_SHIFT_IOOFFSET_3_TO_0) & BIT_MASK_IOOFFSET_3_TO_0) +#define BIT_SET_IOOFFSET_3_TO_0(x, v) \ + (BIT_CLEAR_IOOFFSET_3_TO_0(x) | BIT_IOOFFSET_3_TO_0(v)) -#define BIT_SHIFT_IOOFFSET_3_TO_0 28 -#define BIT_MASK_IOOFFSET_3_TO_0 0xf -#define BIT_IOOFFSET_3_TO_0(x) (((x) & BIT_MASK_IOOFFSET_3_TO_0) << BIT_SHIFT_IOOFFSET_3_TO_0) -#define BIT_GET_IOOFFSET_3_TO_0(x) (((x) >> BIT_SHIFT_IOOFFSET_3_TO_0) & BIT_MASK_IOOFFSET_3_TO_0) - -#define BIT_REG_FREF_SEL_BIT3_V1 BIT(27) +#define BIT_REG_FREF_SEL_BIT3_V1 BIT(27) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG_VO_AD 26 -#define BIT_MASK_REG_VO_AD 0x3 -#define BIT_REG_VO_AD(x) (((x) & BIT_MASK_REG_VO_AD) << BIT_SHIFT_REG_VO_AD) -#define BIT_GET_REG_VO_AD(x) (((x) >> BIT_SHIFT_REG_VO_AD) & BIT_MASK_REG_VO_AD) - +#define BIT_SHIFT_REG_VO_AD 26 +#define BIT_MASK_REG_VO_AD 0x3 +#define BIT_REG_VO_AD(x) (((x) & BIT_MASK_REG_VO_AD) << BIT_SHIFT_REG_VO_AD) +#define BITS_REG_VO_AD (BIT_MASK_REG_VO_AD << BIT_SHIFT_REG_VO_AD) +#define BIT_CLEAR_REG_VO_AD(x) ((x) & (~BITS_REG_VO_AD)) +#define BIT_GET_REG_VO_AD(x) (((x) >> BIT_SHIFT_REG_VO_AD) & BIT_MASK_REG_VO_AD) +#define BIT_SET_REG_VO_AD(x, v) (BIT_CLEAR_REG_VO_AD(x) | BIT_REG_VO_AD(v)) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_RS_SET_V2 26 -#define BIT_MASK_RS_SET_V2 0x7 -#define BIT_RS_SET_V2(x) (((x) & BIT_MASK_RS_SET_V2) << BIT_SHIFT_RS_SET_V2) -#define BIT_GET_RS_SET_V2(x) (((x) >> BIT_SHIFT_RS_SET_V2) & BIT_MASK_RS_SET_V2) - +#define BIT_SHIFT_RS_SET 26 +#define BIT_MASK_RS_SET 0x7 +#define BIT_RS_SET(x) (((x) & BIT_MASK_RS_SET) << BIT_SHIFT_RS_SET) +#define BITS_RS_SET (BIT_MASK_RS_SET << BIT_SHIFT_RS_SET) +#define BIT_CLEAR_RS_SET(x) ((x) & (~BITS_RS_SET)) +#define BIT_GET_RS_SET(x) (((x) >> BIT_SHIFT_RS_SET) & BIT_MASK_RS_SET) +#define BIT_SET_RS_SET(x, v) (BIT_CLEAR_RS_SET(x) | BIT_RS_SET(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_SHIFT_RS_SET_V2 26 +#define BIT_MASK_RS_SET_V2 0x7 +#define BIT_RS_SET_V2(x) (((x) & BIT_MASK_RS_SET_V2) << BIT_SHIFT_RS_SET_V2) +#define BITS_RS_SET_V2 (BIT_MASK_RS_SET_V2 << BIT_SHIFT_RS_SET_V2) +#define BIT_CLEAR_RS_SET_V2(x) ((x) & (~BITS_RS_SET_V2)) +#define BIT_GET_RS_SET_V2(x) (((x) >> BIT_SHIFT_RS_SET_V2) & BIT_MASK_RS_SET_V2) +#define BIT_SET_RS_SET_V2(x, v) (BIT_CLEAR_RS_SET_V2(x) | BIT_RS_SET_V2(v)) -/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_REG_RS_V4 26 -#define BIT_MASK_REG_RS_V4 0x7 -#define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4) -#define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4) +/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_SHIFT_REG_RS_V4 26 +#define BIT_MASK_REG_RS_V4 0x7 +#define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4) +#define BITS_REG_RS_V4 (BIT_MASK_REG_RS_V4 << BIT_SHIFT_REG_RS_V4) +#define BIT_CLEAR_REG_RS_V4(x) ((x) & (~BITS_REG_RS_V4)) +#define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4) +#define BIT_SET_REG_RS_V4(x, v) (BIT_CLEAR_REG_RS_V4(x) | BIT_REG_RS_V4(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_V12ADJ_V1 25 -#define BIT_MASK_V12ADJ_V1 0x3 -#define BIT_V12ADJ_V1(x) (((x) & BIT_MASK_V12ADJ_V1) << BIT_SHIFT_V12ADJ_V1) -#define BIT_GET_V12ADJ_V1(x) (((x) >> BIT_SHIFT_V12ADJ_V1) & BIT_MASK_V12ADJ_V1) - +#define BIT_SHIFT_V12ADJ_V1 25 +#define BIT_MASK_V12ADJ_V1 0x3 +#define BIT_V12ADJ_V1(x) (((x) & BIT_MASK_V12ADJ_V1) << BIT_SHIFT_V12ADJ_V1) +#define BITS_V12ADJ_V1 (BIT_MASK_V12ADJ_V1 << BIT_SHIFT_V12ADJ_V1) +#define BIT_CLEAR_V12ADJ_V1(x) ((x) & (~BITS_V12ADJ_V1)) +#define BIT_GET_V12ADJ_V1(x) (((x) >> BIT_SHIFT_V12ADJ_V1) & BIT_MASK_V12ADJ_V1) +#define BIT_SET_V12ADJ_V1(x, v) (BIT_CLEAR_V12ADJ_V1(x) | BIT_V12ADJ_V1(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ - -#define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24 -#define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff -#define BIT_NOAC_OQT_FREEPG_V1(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1) -#define BIT_GET_NOAC_OQT_FREEPG_V1(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1) - +#define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24 +#define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff +#define BIT_NOAC_OQT_FREEPG_V1(x) \ + (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1) +#define BITS_NOAC_OQT_FREEPG_V1 \ + (BIT_MASK_NOAC_OQT_FREEPG_V1 << BIT_SHIFT_NOAC_OQT_FREEPG_V1) +#define BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) ((x) & (~BITS_NOAC_OQT_FREEPG_V1)) +#define BIT_GET_NOAC_OQT_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1) +#define BIT_SET_NOAC_OQT_FREEPG_V1(x, v) \ + (BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) | BIT_NOAC_OQT_FREEPG_V1(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_PS_EN BIT(24) +#define BIT_PS_EN BIT(24) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG__CS 24 -#define BIT_MASK_REG__CS 0x3 -#define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS) -#define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS) - +#define BIT_SHIFT_REG__CS 24 +#define BIT_MASK_REG__CS 0x3 +#define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS) +#define BITS_REG__CS (BIT_MASK_REG__CS << BIT_SHIFT_REG__CS) +#define BIT_CLEAR_REG__CS(x) ((x) & (~BITS_REG__CS)) +#define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS) +#define BIT_SET_REG__CS(x, v) (BIT_CLEAR_REG__CS(x) | BIT_REG__CS(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_EN_CK320M_V1 BIT(23) -#define BIT_AGPIO BIT(22) -#define BIT_REG_EDGE_SEL_V1 BIT(21) +#define BIT_EN_CK320M_V1 BIT(23) +#define BIT_AGPIO BIT(22) +#define BIT_REG_EDGE_SEL_V1 BIT(21) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG_CP_OFFSET 21 -#define BIT_MASK_REG_CP_OFFSET 0x7 -#define BIT_REG_CP_OFFSET(x) (((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET) -#define BIT_GET_REG_CP_OFFSET(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET) - +#define BIT_SHIFT_REG_CP_OFFSET 21 +#define BIT_MASK_REG_CP_OFFSET 0x7 +#define BIT_REG_CP_OFFSET(x) \ + (((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET) +#define BITS_REG_CP_OFFSET (BIT_MASK_REG_CP_OFFSET << BIT_SHIFT_REG_CP_OFFSET) +#define BIT_CLEAR_REG_CP_OFFSET(x) ((x) & (~BITS_REG_CP_OFFSET)) +#define BIT_GET_REG_CP_OFFSET(x) \ + (((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET) +#define BIT_SET_REG_CP_OFFSET(x, v) \ + (BIT_CLEAR_REG_CP_OFFSET(x) | BIT_REG_CP_OFFSET(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_VCO_BIAS_0 BIT(20) +#define BIT_REG_VCO_BIAS_0 BIT(20) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_CP_BIAS_V2 18 -#define BIT_MASK_CP_BIAS_V2 0x7 -#define BIT_CP_BIAS_V2(x) (((x) & BIT_MASK_CP_BIAS_V2) << BIT_SHIFT_CP_BIAS_V2) -#define BIT_GET_CP_BIAS_V2(x) (((x) >> BIT_SHIFT_CP_BIAS_V2) & BIT_MASK_CP_BIAS_V2) - +#define BIT_SHIFT_CP_BIAS 18 +#define BIT_MASK_CP_BIAS 0x7 +#define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS) +#define BITS_CP_BIAS (BIT_MASK_CP_BIAS << BIT_SHIFT_CP_BIAS) +#define BIT_CLEAR_CP_BIAS(x) ((x) & (~BITS_CP_BIAS)) +#define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS) +#define BIT_SET_CP_BIAS(x, v) (BIT_CLEAR_CP_BIAS(x) | BIT_CP_BIAS(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_CP_BIAS 18 -#define BIT_MASK_CP_BIAS 0x7 -#define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS) -#define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS) - +#define BIT_SHIFT_CP_BIAS_V2 18 +#define BIT_MASK_CP_BIAS_V2 0x7 +#define BIT_CP_BIAS_V2(x) (((x) & BIT_MASK_CP_BIAS_V2) << BIT_SHIFT_CP_BIAS_V2) +#define BITS_CP_BIAS_V2 (BIT_MASK_CP_BIAS_V2 << BIT_SHIFT_CP_BIAS_V2) +#define BIT_CLEAR_CP_BIAS_V2(x) ((x) & (~BITS_CP_BIAS_V2)) +#define BIT_GET_CP_BIAS_V2(x) \ + (((x) >> BIT_SHIFT_CP_BIAS_V2) & BIT_MASK_CP_BIAS_V2) +#define BIT_SET_CP_BIAS_V2(x, v) (BIT_CLEAR_CP_BIAS_V2(x) | BIT_CP_BIAS_V2(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1 17 -#define BIT_MASK_REG_PLLBIAS_2_TO_0_V1 0x7 -#define BIT_REG_PLLBIAS_2_TO_0_V1(x) (((x) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1) << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) -#define BIT_GET_REG_PLLBIAS_2_TO_0_V1(x) (((x) >> BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1) - +#define BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1 17 +#define BIT_MASK_REG_PLLBIAS_2_TO_0_V1 0x7 +#define BIT_REG_PLLBIAS_2_TO_0_V1(x) \ + (((x) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1) \ + << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) +#define BITS_REG_PLLBIAS_2_TO_0_V1 \ + (BIT_MASK_REG_PLLBIAS_2_TO_0_V1 << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) +#define BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) ((x) & (~BITS_REG_PLLBIAS_2_TO_0_V1)) +#define BIT_GET_REG_PLLBIAS_2_TO_0_V1(x) \ + (((x) >> BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) & \ + BIT_MASK_REG_PLLBIAS_2_TO_0_V1) +#define BIT_SET_REG_PLLBIAS_2_TO_0_V1(x, v) \ + (BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) | BIT_REG_PLLBIAS_2_TO_0_V1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_IDOUBLE_V2 BIT(17) +#define BIT_REG_IDOUBLE_V2 BIT(17) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_FREF_SEL BIT(16) +#define BIT_FREF_SEL BIT(16) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_REG_IDOUBLE_V1 BIT(16) - -#define BIT_SHIFT_AC_OQT__FREEPG_V1 16 -#define BIT_MASK_AC_OQT__FREEPG_V1 0xff -#define BIT_AC_OQT__FREEPG_V1(x) (((x) & BIT_MASK_AC_OQT__FREEPG_V1) << BIT_SHIFT_AC_OQT__FREEPG_V1) -#define BIT_GET_AC_OQT__FREEPG_V1(x) (((x) >> BIT_SHIFT_AC_OQT__FREEPG_V1) & BIT_MASK_AC_OQT__FREEPG_V1) +/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ +#define BIT_SHIFT_AC_OQT_FREEPG_V1 16 +#define BIT_MASK_AC_OQT_FREEPG_V1 0xff +#define BIT_AC_OQT_FREEPG_V1(x) \ + (((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1) +#define BITS_AC_OQT_FREEPG_V1 \ + (BIT_MASK_AC_OQT_FREEPG_V1 << BIT_SHIFT_AC_OQT_FREEPG_V1) +#define BIT_CLEAR_AC_OQT_FREEPG_V1(x) ((x) & (~BITS_AC_OQT_FREEPG_V1)) +#define BIT_GET_AC_OQT_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1) +#define BIT_SET_AC_OQT_FREEPG_V1(x, v) \ + (BIT_CLEAR_AC_OQT_FREEPG_V1(x) | BIT_AC_OQT_FREEPG_V1(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_EN_SYN BIT(16) - -#define BIT_SHIFT_AC_OQT_FREEPG_V1 16 -#define BIT_MASK_AC_OQT_FREEPG_V1 0xff -#define BIT_AC_OQT_FREEPG_V1(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1) -#define BIT_GET_AC_OQT_FREEPG_V1(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1) +#define BIT_REG_IDOUBLE_V1 BIT(16) +#define BIT_SHIFT_AC_OQT__FREEPG_V1 16 +#define BIT_MASK_AC_OQT__FREEPG_V1 0xff +#define BIT_AC_OQT__FREEPG_V1(x) \ + (((x) & BIT_MASK_AC_OQT__FREEPG_V1) << BIT_SHIFT_AC_OQT__FREEPG_V1) +#define BITS_AC_OQT__FREEPG_V1 \ + (BIT_MASK_AC_OQT__FREEPG_V1 << BIT_SHIFT_AC_OQT__FREEPG_V1) +#define BIT_CLEAR_AC_OQT__FREEPG_V1(x) ((x) & (~BITS_AC_OQT__FREEPG_V1)) +#define BIT_GET_AC_OQT__FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_AC_OQT__FREEPG_V1) & BIT_MASK_AC_OQT__FREEPG_V1) +#define BIT_SET_AC_OQT__FREEPG_V1(x, v) \ + (BIT_CLEAR_AC_OQT__FREEPG_V1(x) | BIT_AC_OQT__FREEPG_V1(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_KVCO_V1 BIT(15) +#define BIT_EN_SYN BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_APLL_320_GATEB BIT(14) +#define BIT_REG_KVCO_V1 BIT(15) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_MCCO_V2 14 -#define BIT_MASK_MCCO_V2 0x3 -#define BIT_MCCO_V2(x) (((x) & BIT_MASK_MCCO_V2) << BIT_SHIFT_MCCO_V2) -#define BIT_GET_MCCO_V2(x) (((x) >> BIT_SHIFT_MCCO_V2) & BIT_MASK_MCCO_V2) - +#define BIT_APLL_320_GATEB BIT(14) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_VCO_BIAS_1_V1 BIT(14) +#define BIT_SHIFT_MCCO 14 +#define BIT_MASK_MCCO 0x3 +#define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO) +#define BITS_MCCO (BIT_MASK_MCCO << BIT_SHIFT_MCCO) +#define BIT_CLEAR_MCCO(x) ((x) & (~BITS_MCCO)) +#define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO) +#define BIT_SET_MCCO(x, v) (BIT_CLEAR_MCCO(x) | BIT_MCCO(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_MCCO 14 -#define BIT_MASK_MCCO 0x3 -#define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO) -#define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO) - +#define BIT_SHIFT_MCCO_V2 14 +#define BIT_MASK_MCCO_V2 0x3 +#define BIT_MCCO_V2(x) (((x) & BIT_MASK_MCCO_V2) << BIT_SHIFT_MCCO_V2) +#define BITS_MCCO_V2 (BIT_MASK_MCCO_V2 << BIT_SHIFT_MCCO_V2) +#define BIT_CLEAR_MCCO_V2(x) ((x) & (~BITS_MCCO_V2)) +#define BIT_GET_MCCO_V2(x) (((x) >> BIT_SHIFT_MCCO_V2) & BIT_MASK_MCCO_V2) +#define BIT_SET_MCCO_V2(x, v) (BIT_CLEAR_MCCO_V2(x) | BIT_MCCO_V2(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_DOGB_V1 BIT(13) +#define BIT_REG_VCO_BIAS_1_V1 BIT(14) +#define BIT_REG_DOGB_V1 BIT(13) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_CK320_EN 12 -#define BIT_MASK_CK320_EN 0x3 -#define BIT_CK320_EN(x) (((x) & BIT_MASK_CK320_EN) << BIT_SHIFT_CK320_EN) -#define BIT_GET_CK320_EN(x) (((x) >> BIT_SHIFT_CK320_EN) & BIT_MASK_CK320_EN) - +#define BIT_SHIFT_CK320_EN 12 +#define BIT_MASK_CK320_EN 0x3 +#define BIT_CK320_EN(x) (((x) & BIT_MASK_CK320_EN) << BIT_SHIFT_CK320_EN) +#define BITS_CK320_EN (BIT_MASK_CK320_EN << BIT_SHIFT_CK320_EN) +#define BIT_CLEAR_CK320_EN(x) ((x) & (~BITS_CK320_EN)) +#define BIT_GET_CK320_EN(x) (((x) >> BIT_SHIFT_CK320_EN) & BIT_MASK_CK320_EN) +#define BIT_SET_CK320_EN(x, v) (BIT_CLEAR_CK320_EN(x) | BIT_CK320_EN(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_SHIFT_REG_LDO_SEL 12 +#define BIT_MASK_REG_LDO_SEL 0x3 +#define BIT_REG_LDO_SEL(x) \ + (((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL) +#define BITS_REG_LDO_SEL (BIT_MASK_REG_LDO_SEL << BIT_SHIFT_REG_LDO_SEL) +#define BIT_CLEAR_REG_LDO_SEL(x) ((x) & (~BITS_REG_LDO_SEL)) +#define BIT_GET_REG_LDO_SEL(x) \ + (((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL) +#define BIT_SET_REG_LDO_SEL(x, v) \ + (BIT_CLEAR_REG_LDO_SEL(x) | BIT_REG_LDO_SEL(v)) -#define BIT_SHIFT_REG_LDO_SEL 12 -#define BIT_MASK_REG_LDO_SEL 0x3 -#define BIT_REG_LDO_SEL(x) (((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL) -#define BIT_GET_REG_LDO_SEL(x) (((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL) - -#define BIT_REG_KVCO_V2 BIT(10) +#define BIT_REG_KVCO_V2 BIT(10) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_AGPIO_GPO BIT(9) +#define BIT_AGPIO_GPO BIT(9) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_APLL_BIAS 8 -#define BIT_MASK_APLL_BIAS 0x7 -#define BIT_APLL_BIAS(x) (((x) & BIT_MASK_APLL_BIAS) << BIT_SHIFT_APLL_BIAS) -#define BIT_GET_APLL_BIAS(x) (((x) >> BIT_SHIFT_APLL_BIAS) & BIT_MASK_APLL_BIAS) - +#define BIT_SHIFT_APLL_BIAS 8 +#define BIT_MASK_APLL_BIAS 0x7 +#define BIT_APLL_BIAS(x) (((x) & BIT_MASK_APLL_BIAS) << BIT_SHIFT_APLL_BIAS) +#define BITS_APLL_BIAS (BIT_MASK_APLL_BIAS << BIT_SHIFT_APLL_BIAS) +#define BIT_CLEAR_APLL_BIAS(x) ((x) & (~BITS_APLL_BIAS)) +#define BIT_GET_APLL_BIAS(x) (((x) >> BIT_SHIFT_APLL_BIAS) & BIT_MASK_APLL_BIAS) +#define BIT_SET_APLL_BIAS(x, v) (BIT_CLEAR_APLL_BIAS(x) | BIT_APLL_BIAS(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_AGPIO_DRV 7 -#define BIT_MASK_AGPIO_DRV 0x3 -#define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV) -#define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV) - +#define BIT_SHIFT_AGPIO_DRV 7 +#define BIT_MASK_AGPIO_DRV 0x3 +#define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV) +#define BITS_AGPIO_DRV (BIT_MASK_AGPIO_DRV << BIT_SHIFT_AGPIO_DRV) +#define BIT_CLEAR_AGPIO_DRV(x) ((x) & (~BITS_AGPIO_DRV)) +#define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV) +#define BIT_SET_AGPIO_DRV(x, v) (BIT_CLEAR_AGPIO_DRV(x) | BIT_AGPIO_DRV(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG_V15_3_TO_0_V1 7 -#define BIT_MASK_REG_V15_3_TO_0_V1 0xf -#define BIT_REG_V15_3_TO_0_V1(x) (((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_V1) -#define BIT_GET_REG_V15_3_TO_0_V1(x) (((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1) - +#define BIT_SHIFT_REG_V15_3_TO_0_V1 7 +#define BIT_MASK_REG_V15_3_TO_0_V1 0xf +#define BIT_REG_V15_3_TO_0_V1(x) \ + (((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_V1) +#define BITS_REG_V15_3_TO_0_V1 \ + (BIT_MASK_REG_V15_3_TO_0_V1 << BIT_SHIFT_REG_V15_3_TO_0_V1) +#define BIT_CLEAR_REG_V15_3_TO_0_V1(x) ((x) & (~BITS_REG_V15_3_TO_0_V1)) +#define BIT_GET_REG_V15_3_TO_0_V1(x) \ + (((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1) +#define BIT_SET_REG_V15_3_TO_0_V1(x, v) \ + (BIT_CLEAR_REG_V15_3_TO_0_V1(x) | BIT_REG_V15_3_TO_0_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_APLL_KVCO BIT(6) +#define BIT_APLL_KVCO BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_REG_SEL_LDO_PC BIT(6) +#define BIT_REG_SEL_LDO_PC BIT(6) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_APLL_WDOGB BIT(4) +#define BIT_APLL_WDOGB BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ - -#define BIT_SHIFT_REG_CC_1_TO_0_V1 4 -#define BIT_MASK_REG_CC_1_TO_0_V1 0x3 -#define BIT_REG_CC_1_TO_0_V1(x) (((x) & BIT_MASK_REG_CC_1_TO_0_V1) << BIT_SHIFT_REG_CC_1_TO_0_V1) -#define BIT_GET_REG_CC_1_TO_0_V1(x) (((x) >> BIT_SHIFT_REG_CC_1_TO_0_V1) & BIT_MASK_REG_CC_1_TO_0_V1) - +#define BIT_SHIFT_REG_CC_1_TO_0_V1 4 +#define BIT_MASK_REG_CC_1_TO_0_V1 0x3 +#define BIT_REG_CC_1_TO_0_V1(x) \ + (((x) & BIT_MASK_REG_CC_1_TO_0_V1) << BIT_SHIFT_REG_CC_1_TO_0_V1) +#define BITS_REG_CC_1_TO_0_V1 \ + (BIT_MASK_REG_CC_1_TO_0_V1 << BIT_SHIFT_REG_CC_1_TO_0_V1) +#define BIT_CLEAR_REG_CC_1_TO_0_V1(x) ((x) & (~BITS_REG_CC_1_TO_0_V1)) +#define BIT_GET_REG_CC_1_TO_0_V1(x) \ + (((x) >> BIT_SHIFT_REG_CC_1_TO_0_V1) & BIT_MASK_REG_CC_1_TO_0_V1) +#define BIT_SET_REG_CC_1_TO_0_V1(x, v) \ + (BIT_CLEAR_REG_CC_1_TO_0_V1(x) | BIT_REG_CC_1_TO_0_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_APLL_EDGE_SEL BIT(3) +#define BIT_APLL_EDGE_SEL BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_CKDELAY_USB_V1 BIT(3) +#define BIT_CKDELAY_USB_V1 BIT(3) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_APLL_FREF_SEL_BIT0 BIT(2) +#define BIT_APLL_FREF_SEL_BIT0 BIT(2) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */ + +#define BIT_POW_LDO15 BIT(2) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_CKDELAY_DIG_V1 BIT(2) +#define BIT_CKDELAY_DIG_V1 BIT(2) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#define BIT_SHIFT_XTAL_CAP_XO 1 +#define BIT_MASK_XTAL_CAP_XO 0x3f +#define BIT_XTAL_CAP_XO(x) \ + (((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO) +#define BITS_XTAL_CAP_XO (BIT_MASK_XTAL_CAP_XO << BIT_SHIFT_XTAL_CAP_XO) +#define BIT_CLEAR_XTAL_CAP_XO(x) ((x) & (~BITS_XTAL_CAP_XO)) +#define BIT_GET_XTAL_CAP_XO(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO) +#define BIT_SET_XTAL_CAP_XO(x, v) \ + (BIT_CLEAR_XTAL_CAP_XO(x) | BIT_XTAL_CAP_XO(v)) -/* 2 REG_AFE_CTRL2 (Offset 0x0028) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_XTAL_CAP_XO 1 -#define BIT_MASK_XTAL_CAP_XO 0x3f -#define BIT_XTAL_CAP_XO(x) (((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO) -#define BIT_GET_XTAL_CAP_XO(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO) +/* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */ +#define BIT_POW_SW BIT(1) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_MPLL_EN BIT(1) +#define BIT_MPLL_EN BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_APLL_EN BIT(0) +#define BIT_APLL_EN BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ -#define BIT_POW_PLL BIT(0) +#define BIT_POW_PLL BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ +#define BIT_SHIFT_EXQ_FREEPG_V1 0 +#define BIT_MASK_EXQ_FREEPG_V1 0xfff +#define BIT_EXQ_FREEPG_V1(x) \ + (((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1) +#define BITS_EXQ_FREEPG_V1 (BIT_MASK_EXQ_FREEPG_V1 << BIT_SHIFT_EXQ_FREEPG_V1) +#define BIT_CLEAR_EXQ_FREEPG_V1(x) ((x) & (~BITS_EXQ_FREEPG_V1)) +#define BIT_GET_EXQ_FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1) +#define BIT_SET_EXQ_FREEPG_V1(x, v) \ + (BIT_CLEAR_EXQ_FREEPG_V1(x) | BIT_EXQ_FREEPG_V1(v)) -/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_EXQ__FREEPG_V1 0 -#define BIT_MASK_EXQ__FREEPG_V1 0xfff -#define BIT_EXQ__FREEPG_V1(x) (((x) & BIT_MASK_EXQ__FREEPG_V1) << BIT_SHIFT_EXQ__FREEPG_V1) -#define BIT_GET_EXQ__FREEPG_V1(x) (((x) >> BIT_SHIFT_EXQ__FREEPG_V1) & BIT_MASK_EXQ__FREEPG_V1) +/* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */ +#define BIT_POW_LDO14 BIT(0) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ +#define BIT_SHIFT_EXQ__FREEPG_V1 0 +#define BIT_MASK_EXQ__FREEPG_V1 0xfff +#define BIT_EXQ__FREEPG_V1(x) \ + (((x) & BIT_MASK_EXQ__FREEPG_V1) << BIT_SHIFT_EXQ__FREEPG_V1) +#define BITS_EXQ__FREEPG_V1 \ + (BIT_MASK_EXQ__FREEPG_V1 << BIT_SHIFT_EXQ__FREEPG_V1) +#define BIT_CLEAR_EXQ__FREEPG_V1(x) ((x) & (~BITS_EXQ__FREEPG_V1)) +#define BIT_GET_EXQ__FREEPG_V1(x) \ + (((x) >> BIT_SHIFT_EXQ__FREEPG_V1) & BIT_MASK_EXQ__FREEPG_V1) +#define BIT_SET_EXQ__FREEPG_V1(x, v) \ + (BIT_CLEAR_EXQ__FREEPG_V1(x) | BIT_EXQ__FREEPG_V1(v)) -/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_EXQ_FREEPG_V1 0 -#define BIT_MASK_EXQ_FREEPG_V1 0xfff -#define BIT_EXQ_FREEPG_V1(x) (((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1) -#define BIT_GET_EXQ_FREEPG_V1(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1) +/* 2 REG_ANAPARLDO_POW_MAC (Offset 0x0029) */ +#define BIT_LDOE25_POW_L BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */ +#define BIT_REG_STANDBY_L BIT(19) +#define BIT_PD_REGU_L BIT(18) +#define BIT_EN_PC_BT_L BIT(17) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_REG_LDOADJ_L 13 +#define BIT_MASK_REG_LDOADJ_L 0xf +#define BIT_REG_LDOADJ_L(x) \ + (((x) & BIT_MASK_REG_LDOADJ_L) << BIT_SHIFT_REG_LDOADJ_L) +#define BITS_REG_LDOADJ_L (BIT_MASK_REG_LDOADJ_L << BIT_SHIFT_REG_LDOADJ_L) +#define BIT_CLEAR_REG_LDOADJ_L(x) ((x) & (~BITS_REG_LDOADJ_L)) +#define BIT_GET_REG_LDOADJ_L(x) \ + (((x) >> BIT_SHIFT_REG_LDOADJ_L) & BIT_MASK_REG_LDOADJ_L) +#define BIT_SET_REG_LDOADJ_L(x, v) \ + (BIT_CLEAR_REG_LDOADJ_L(x) | BIT_REG_LDOADJ_L(v)) +#define BIT_CK12M_EN BIT(11) +#define BIT_CK12M_SEL BIT(10) +#define BIT_EN_25_L BIT(9) +#define BIT_EN_SLEEP BIT(8) +#define BIT_DUMMY_V4 BIT(7) +#define BIT_DUMMY_V3 BIT(6) +#define BIT_DUMMY_V2 BIT(5) +#define BIT_DUMMY_V1 BIT(4) -#define BIT_SHIFT_XTAL_RF2_DRV 30 -#define BIT_MASK_XTAL_RF2_DRV 0x3 -#define BIT_XTAL_RF2_DRV(x) (((x) & BIT_MASK_XTAL_RF2_DRV) << BIT_SHIFT_XTAL_RF2_DRV) -#define BIT_GET_XTAL_RF2_DRV(x) (((x) >> BIT_SHIFT_XTAL_RF2_DRV) & BIT_MASK_XTAL_RF2_DRV) +#define BIT_SHIFT_LDOH12_V12ADJ_L 4 +#define BIT_MASK_LDOH12_V12ADJ_L 0xf +#define BIT_LDOH12_V12ADJ_L(x) \ + (((x) & BIT_MASK_LDOH12_V12ADJ_L) << BIT_SHIFT_LDOH12_V12ADJ_L) +#define BITS_LDOH12_V12ADJ_L \ + (BIT_MASK_LDOH12_V12ADJ_L << BIT_SHIFT_LDOH12_V12ADJ_L) +#define BIT_CLEAR_LDOH12_V12ADJ_L(x) ((x) & (~BITS_LDOH12_V12ADJ_L)) +#define BIT_GET_LDOH12_V12ADJ_L(x) \ + (((x) >> BIT_SHIFT_LDOH12_V12ADJ_L) & BIT_MASK_LDOH12_V12ADJ_L) +#define BIT_SET_LDOH12_V12ADJ_L(x, v) \ + (BIT_CLEAR_LDOH12_V12ADJ_L(x) | BIT_LDOH12_V12ADJ_L(v)) +#define BIT_POW_PC_LDO_PORT1 BIT(3) +#define BIT_POW_PC_LDO_PORT0 BIT(2) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +/* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */ -#define BIT_REG_REF_SEL_V3 BIT(30) +#define BIT_POW_PLL_V1 BIT(1) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */ +#define BIT_POW_POWER_CUT_POW_LDO BIT(0) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_XTAL_GMN_BIT4 BIT(29) -#define BIT_XTAL_GMP_BIT4 BIT(28) +#define BIT_SHIFT_LDOE25_V12ADJ_L_V1 0 +#define BIT_MASK_LDOE25_V12ADJ_L_V1 0xf +#define BIT_LDOE25_V12ADJ_L_V1(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L_V1) << BIT_SHIFT_LDOE25_V12ADJ_L_V1) +#define BITS_LDOE25_V12ADJ_L_V1 \ + (BIT_MASK_LDOE25_V12ADJ_L_V1 << BIT_SHIFT_LDOE25_V12ADJ_L_V1) +#define BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) ((x) & (~BITS_LDOE25_V12ADJ_L_V1)) +#define BIT_GET_LDOE25_V12ADJ_L_V1(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_V1) & BIT_MASK_LDOE25_V12ADJ_L_V1) +#define BIT_SET_LDOE25_V12ADJ_L_V1(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) | BIT_LDOE25_V12ADJ_L_V1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_ANAPAR_POW_XTAL (Offset 0x002B) */ + +#define BIT_PSTIMER_2 BIT(31) +#define BIT_PSTIMER_1 BIT(30) +#define BIT_PSTIMER_0 BIT(29) +#define BIT_TXDMA_START_INT BIT(23) +#define BIT_TXDMA_STOP_INT BIT(22) +#define BIT_HISR7_IND BIT(21) +#define BIT_HISR6_IND BIT(19) +#define BIT_HISR5_IND BIT(18) +#define BIT_HISR4_IND BIT(17) +#define BIT_HISR3_IND BIT(14) +#define BIT_HISR2_IND BIT(13) +#define BIT_POW_XTAL BIT(1) +#define BIT_POW_BG BIT(0) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_XQSEL BIT(27) +#define BIT_SHIFT_XTAL_RF2_DRV 30 +#define BIT_MASK_XTAL_RF2_DRV 0x3 +#define BIT_XTAL_RF2_DRV(x) \ + (((x) & BIT_MASK_XTAL_RF2_DRV) << BIT_SHIFT_XTAL_RF2_DRV) +#define BITS_XTAL_RF2_DRV (BIT_MASK_XTAL_RF2_DRV << BIT_SHIFT_XTAL_RF2_DRV) +#define BIT_CLEAR_XTAL_RF2_DRV(x) ((x) & (~BITS_XTAL_RF2_DRV)) +#define BIT_GET_XTAL_RF2_DRV(x) \ + (((x) >> BIT_SHIFT_XTAL_RF2_DRV) & BIT_MASK_XTAL_RF2_DRV) +#define BIT_SET_XTAL_RF2_DRV(x, v) \ + (BIT_CLEAR_XTAL_RF2_DRV(x) | BIT_XTAL_RF2_DRV(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_REG_FREF_SEL_2_TO_0 27 -#define BIT_MASK_REG_FREF_SEL_2_TO_0 0x7 -#define BIT_REG_FREF_SEL_2_TO_0(x) (((x) & BIT_MASK_REG_FREF_SEL_2_TO_0) << BIT_SHIFT_REG_FREF_SEL_2_TO_0) -#define BIT_GET_REG_FREF_SEL_2_TO_0(x) (((x) >> BIT_SHIFT_REG_FREF_SEL_2_TO_0) & BIT_MASK_REG_FREF_SEL_2_TO_0) - +#define BIT_REG_REF_SEL_V3 BIT(30) #endif - -#if (HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_XQSEL_BIT0 BIT(27) +#define BIT_XTAL_GMN_BIT4 BIT(29) +#define BIT_XTAL_GMP_BIT4 BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_APLL_DUMMY BIT(26) +#define BIT_XQSEL BIT(27) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1 21 -#define BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 0x3f -#define BIT_XTAL_CADJ_XOUT_5_TO_0_V1(x) (((x) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) -#define BIT_GET_XTAL_CADJ_XOUT_5_TO_0_V1(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) - +#define BIT_SHIFT_REG_FREF_SEL_2_TO_0 27 +#define BIT_MASK_REG_FREF_SEL_2_TO_0 0x7 +#define BIT_REG_FREF_SEL_2_TO_0(x) \ + (((x) & BIT_MASK_REG_FREF_SEL_2_TO_0) << BIT_SHIFT_REG_FREF_SEL_2_TO_0) +#define BITS_REG_FREF_SEL_2_TO_0 \ + (BIT_MASK_REG_FREF_SEL_2_TO_0 << BIT_SHIFT_REG_FREF_SEL_2_TO_0) +#define BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) ((x) & (~BITS_REG_FREF_SEL_2_TO_0)) +#define BIT_GET_REG_FREF_SEL_2_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_FREF_SEL_2_TO_0) & BIT_MASK_REG_FREF_SEL_2_TO_0) +#define BIT_SET_REG_FREF_SEL_2_TO_0(x, v) \ + (BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) | BIT_REG_FREF_SEL_2_TO_0(v)) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_XQSEL_BIT0 BIT(27) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_XTAL_CADJ_XOUT 18 -#define BIT_MASK_XTAL_CADJ_XOUT 0x3f -#define BIT_XTAL_CADJ_XOUT(x) (((x) & BIT_MASK_XTAL_CADJ_XOUT) << BIT_SHIFT_XTAL_CADJ_XOUT) -#define BIT_GET_XTAL_CADJ_XOUT(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT) & BIT_MASK_XTAL_CADJ_XOUT) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_APLL_DUMMY BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_XTAL_CADJ_XIN_V2 15 -#define BIT_MASK_XTAL_CADJ_XIN_V2 0x3f -#define BIT_XTAL_CADJ_XIN_V2(x) (((x) & BIT_MASK_XTAL_CADJ_XIN_V2) << BIT_SHIFT_XTAL_CADJ_XIN_V2) -#define BIT_GET_XTAL_CADJ_XIN_V2(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XIN_V2) & BIT_MASK_XTAL_CADJ_XIN_V2) - +#define BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1 21 +#define BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 0x3f +#define BIT_XTAL_CADJ_XOUT_5_TO_0_V1(x) \ + (((x) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) \ + << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) +#define BITS_XTAL_CADJ_XOUT_5_TO_0_V1 \ + (BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 \ + << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) +#define BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x) \ + ((x) & (~BITS_XTAL_CADJ_XOUT_5_TO_0_V1)) +#define BIT_GET_XTAL_CADJ_XOUT_5_TO_0_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) & \ + BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) +#define BIT_SET_XTAL_CADJ_XOUT_5_TO_0_V1(x, v) \ + (BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x) | \ + BIT_XTAL_CADJ_XOUT_5_TO_0_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_XTAL_CADJ_XIN 12 -#define BIT_MASK_XTAL_CADJ_XIN 0x3f -#define BIT_XTAL_CADJ_XIN(x) (((x) & BIT_MASK_XTAL_CADJ_XIN) << BIT_SHIFT_XTAL_CADJ_XIN) -#define BIT_GET_XTAL_CADJ_XIN(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XIN) & BIT_MASK_XTAL_CADJ_XIN) - +#define BIT_SHIFT_XTAL_CADJ_XOUT 18 +#define BIT_MASK_XTAL_CADJ_XOUT 0x3f +#define BIT_XTAL_CADJ_XOUT(x) \ + (((x) & BIT_MASK_XTAL_CADJ_XOUT) << BIT_SHIFT_XTAL_CADJ_XOUT) +#define BITS_XTAL_CADJ_XOUT \ + (BIT_MASK_XTAL_CADJ_XOUT << BIT_SHIFT_XTAL_CADJ_XOUT) +#define BIT_CLEAR_XTAL_CADJ_XOUT(x) ((x) & (~BITS_XTAL_CADJ_XOUT)) +#define BIT_GET_XTAL_CADJ_XOUT(x) \ + (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT) & BIT_MASK_XTAL_CADJ_XOUT) +#define BIT_SET_XTAL_CADJ_XOUT(x, v) \ + (BIT_CLEAR_XTAL_CADJ_XOUT(x) | BIT_XTAL_CADJ_XOUT(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_REG_RS_V3 12 -#define BIT_MASK_REG_RS_V3 0x7 -#define BIT_REG_RS_V3(x) (((x) & BIT_MASK_REG_RS_V3) << BIT_SHIFT_REG_RS_V3) -#define BIT_GET_REG_RS_V3(x) (((x) >> BIT_SHIFT_REG_RS_V3) & BIT_MASK_REG_RS_V3) - +#define BIT_SHIFT_XTAL_CADJ_XIN_V2 15 +#define BIT_MASK_XTAL_CADJ_XIN_V2 0x3f +#define BIT_XTAL_CADJ_XIN_V2(x) \ + (((x) & BIT_MASK_XTAL_CADJ_XIN_V2) << BIT_SHIFT_XTAL_CADJ_XIN_V2) +#define BITS_XTAL_CADJ_XIN_V2 \ + (BIT_MASK_XTAL_CADJ_XIN_V2 << BIT_SHIFT_XTAL_CADJ_XIN_V2) +#define BIT_CLEAR_XTAL_CADJ_XIN_V2(x) ((x) & (~BITS_XTAL_CADJ_XIN_V2)) +#define BIT_GET_XTAL_CADJ_XIN_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_CADJ_XIN_V2) & BIT_MASK_XTAL_CADJ_XIN_V2) +#define BIT_SET_XTAL_CADJ_XIN_V2(x, v) \ + (BIT_CLEAR_XTAL_CADJ_XIN_V2(x) | BIT_XTAL_CADJ_XIN_V2(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ - -#define BIT_SHIFT_REG_RS 9 -#define BIT_MASK_REG_RS 0x7 -#define BIT_REG_RS(x) (((x) & BIT_MASK_REG_RS) << BIT_SHIFT_REG_RS) -#define BIT_GET_REG_RS(x) (((x) >> BIT_SHIFT_REG_RS) & BIT_MASK_REG_RS) - +#define BIT_SHIFT_XTAL_CADJ_XIN 12 +#define BIT_MASK_XTAL_CADJ_XIN 0x3f +#define BIT_XTAL_CADJ_XIN(x) \ + (((x) & BIT_MASK_XTAL_CADJ_XIN) << BIT_SHIFT_XTAL_CADJ_XIN) +#define BITS_XTAL_CADJ_XIN (BIT_MASK_XTAL_CADJ_XIN << BIT_SHIFT_XTAL_CADJ_XIN) +#define BIT_CLEAR_XTAL_CADJ_XIN(x) ((x) & (~BITS_XTAL_CADJ_XIN)) +#define BIT_GET_XTAL_CADJ_XIN(x) \ + (((x) >> BIT_SHIFT_XTAL_CADJ_XIN) & BIT_MASK_XTAL_CADJ_XIN) +#define BIT_SET_XTAL_CADJ_XIN(x, v) \ + (BIT_CLEAR_XTAL_CADJ_XIN(x) | BIT_XTAL_CADJ_XIN(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_REG_RS_V3 12 +#define BIT_MASK_REG_RS_V3 0x7 +#define BIT_REG_RS_V3(x) (((x) & BIT_MASK_REG_RS_V3) << BIT_SHIFT_REG_RS_V3) +#define BITS_REG_RS_V3 (BIT_MASK_REG_RS_V3 << BIT_SHIFT_REG_RS_V3) +#define BIT_CLEAR_REG_RS_V3(x) ((x) & (~BITS_REG_RS_V3)) +#define BIT_GET_REG_RS_V3(x) (((x) >> BIT_SHIFT_REG_RS_V3) & BIT_MASK_REG_RS_V3) +#define BIT_SET_REG_RS_V3(x, v) (BIT_CLEAR_REG_RS_V3(x) | BIT_REG_RS_V3(v)) -#define BIT_SHIFT_REG_R3_V3 9 -#define BIT_MASK_REG_R3_V3 0x7 -#define BIT_REG_R3_V3(x) (((x) & BIT_MASK_REG_R3_V3) << BIT_SHIFT_REG_R3_V3) -#define BIT_GET_REG_R3_V3(x) (((x) >> BIT_SHIFT_REG_R3_V3) & BIT_MASK_REG_R3_V3) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_BCNQ_EMPTY BIT(11) +#define BIT_SDIO_HQQ_EMPTY BIT(10) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_REG_RS 9 +#define BIT_MASK_REG_RS 0x7 +#define BIT_REG_RS(x) (((x) & BIT_MASK_REG_RS) << BIT_SHIFT_REG_RS) +#define BITS_REG_RS (BIT_MASK_REG_RS << BIT_SHIFT_REG_RS) +#define BIT_CLEAR_REG_RS(x) ((x) & (~BITS_REG_RS)) +#define BIT_GET_REG_RS(x) (((x) >> BIT_SHIFT_REG_RS) & BIT_MASK_REG_RS) +#define BIT_SET_REG_RS(x, v) (BIT_CLEAR_REG_RS(x) | BIT_REG_RS(v)) -#define BIT_SHIFT_PS_V2 7 -#define BIT_MASK_PS_V2 0x7 -#define BIT_PS_V2(x) (((x) & BIT_MASK_PS_V2) << BIT_SHIFT_PS_V2) -#define BIT_GET_PS_V2(x) (((x) >> BIT_SHIFT_PS_V2) & BIT_MASK_PS_V2) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_MQQ_EMPTY BIT(9) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_REG_R3_V3 9 +#define BIT_MASK_REG_R3_V3 0x7 +#define BIT_REG_R3_V3(x) (((x) & BIT_MASK_REG_R3_V3) << BIT_SHIFT_REG_R3_V3) +#define BITS_REG_R3_V3 (BIT_MASK_REG_R3_V3 << BIT_SHIFT_REG_R3_V3) +#define BIT_CLEAR_REG_R3_V3(x) ((x) & (~BITS_REG_R3_V3)) +#define BIT_GET_REG_R3_V3(x) (((x) >> BIT_SHIFT_REG_R3_V3) & BIT_MASK_REG_R3_V3) +#define BIT_SET_REG_R3_V3(x, v) (BIT_CLEAR_REG_R3_V3(x) | BIT_REG_R3_V3(v)) -#define BIT_SHIFT_REG_CS_V3 7 -#define BIT_MASK_REG_CS_V3 0x3 -#define BIT_REG_CS_V3(x) (((x) & BIT_MASK_REG_CS_V3) << BIT_SHIFT_REG_CS_V3) -#define BIT_GET_REG_CS_V3(x) (((x) >> BIT_SHIFT_REG_CS_V3) & BIT_MASK_REG_CS_V3) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_MGQ_CPU_EMPTY BIT(8) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_PS_V2 7 +#define BIT_MASK_PS_V2 0x7 +#define BIT_PS_V2(x) (((x) & BIT_MASK_PS_V2) << BIT_SHIFT_PS_V2) +#define BITS_PS_V2 (BIT_MASK_PS_V2 << BIT_SHIFT_PS_V2) +#define BIT_CLEAR_PS_V2(x) ((x) & (~BITS_PS_V2)) +#define BIT_GET_PS_V2(x) (((x) >> BIT_SHIFT_PS_V2) & BIT_MASK_PS_V2) +#define BIT_SET_PS_V2(x, v) (BIT_CLEAR_PS_V2(x) | BIT_PS_V2(v)) -#define BIT_SHIFT_PS 7 -#define BIT_MASK_PS 0x7 -#define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS) -#define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC7Q_EMPTY BIT(7) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_REG_CS_V3 7 +#define BIT_MASK_REG_CS_V3 0x3 +#define BIT_REG_CS_V3(x) (((x) & BIT_MASK_REG_CS_V3) << BIT_SHIFT_REG_CS_V3) +#define BITS_REG_CS_V3 (BIT_MASK_REG_CS_V3 << BIT_SHIFT_REG_CS_V3) +#define BIT_CLEAR_REG_CS_V3(x) ((x) & (~BITS_REG_CS_V3)) +#define BIT_GET_REG_CS_V3(x) (((x) >> BIT_SHIFT_REG_CS_V3) & BIT_MASK_REG_CS_V3) +#define BIT_SET_REG_CS_V3(x, v) (BIT_CLEAR_REG_CS_V3(x) | BIT_REG_CS_V3(v)) -#define BIT_SHIFT_REG_R3 6 -#define BIT_MASK_REG_R3 0x7 -#define BIT_REG_R3(x) (((x) & BIT_MASK_REG_R3) << BIT_SHIFT_REG_R3) -#define BIT_GET_REG_R3(x) (((x) >> BIT_SHIFT_REG_R3) & BIT_MASK_REG_R3) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_PS 7 +#define BIT_MASK_PS 0x7 +#define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS) +#define BITS_PS (BIT_MASK_PS << BIT_SHIFT_PS) +#define BIT_CLEAR_PS(x) ((x) & (~BITS_PS)) +#define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS) +#define BIT_SET_PS(x, v) (BIT_CLEAR_PS(x) | BIT_PS(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_PSEN BIT(6) -#define BIT_DOGENB BIT(5) +#define BIT_SHIFT_REG_R3 6 +#define BIT_MASK_REG_R3 0x7 +#define BIT_REG_R3(x) (((x) & BIT_MASK_REG_R3) << BIT_SHIFT_REG_R3) +#define BITS_REG_R3 (BIT_MASK_REG_R3 << BIT_SHIFT_REG_R3) +#define BIT_CLEAR_REG_R3(x) ((x) & (~BITS_REG_R3)) +#define BIT_GET_REG_R3(x) (((x) >> BIT_SHIFT_REG_R3) & BIT_MASK_REG_R3) +#define BIT_SET_REG_R3(x, v) (BIT_CLEAR_REG_R3(x) | BIT_REG_R3(v)) #endif - -#if (HALMAC_8814A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_PSEN BIT(6) -#define BIT_SHIFT_REG_CP_V3 5 -#define BIT_MASK_REG_CP_V3 0x3 -#define BIT_REG_CP_V3(x) (((x) & BIT_MASK_REG_CP_V3) << BIT_SHIFT_REG_CP_V3) -#define BIT_GET_REG_CP_V3(x) (((x) >> BIT_SHIFT_REG_CP_V3) & BIT_MASK_REG_CP_V3) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC6Q_EMPTY BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_DOGENB BIT(5) -#define BIT_SHIFT_REG_CS 4 -#define BIT_MASK_REG_CS 0x3 -#define BIT_REG_CS(x) (((x) & BIT_MASK_REG_CS) << BIT_SHIFT_REG_CS) -#define BIT_GET_REG_CS(x) (((x) >> BIT_SHIFT_REG_CS) & BIT_MASK_REG_CS) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC5Q_EMPTY BIT(5) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_REG_MBIAS BIT(4) +#define BIT_SHIFT_REG_CP_V3 5 +#define BIT_MASK_REG_CP_V3 0x3 +#define BIT_REG_CP_V3(x) (((x) & BIT_MASK_REG_CP_V3) << BIT_SHIFT_REG_CP_V3) +#define BITS_REG_CP_V3 (BIT_MASK_REG_CP_V3 << BIT_SHIFT_REG_CP_V3) +#define BIT_CLEAR_REG_CP_V3(x) ((x) & (~BITS_REG_CP_V3)) +#define BIT_GET_REG_CP_V3(x) (((x) >> BIT_SHIFT_REG_CP_V3) & BIT_MASK_REG_CP_V3) +#define BIT_SET_REG_CP_V3(x, v) (BIT_CLEAR_REG_CP_V3(x) | BIT_REG_CP_V3(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_SHIFT_REG_CS 4 +#define BIT_MASK_REG_CS 0x3 +#define BIT_REG_CS(x) (((x) & BIT_MASK_REG_CS) << BIT_SHIFT_REG_CS) +#define BITS_REG_CS (BIT_MASK_REG_CS << BIT_SHIFT_REG_CS) +#define BIT_CLEAR_REG_CS(x) ((x) & (~BITS_REG_CS)) +#define BIT_GET_REG_CS(x) (((x) >> BIT_SHIFT_REG_CS) & BIT_MASK_REG_CS) +#define BIT_SET_REG_CS(x, v) (BIT_CLEAR_REG_CS(x) | BIT_REG_CS(v)) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_REG_C3_V3 3 -#define BIT_MASK_REG_C3_V3 0x3 -#define BIT_REG_C3_V3(x) (((x) & BIT_MASK_REG_C3_V3) << BIT_SHIFT_REG_C3_V3) -#define BIT_GET_REG_C3_V3(x) (((x) >> BIT_SHIFT_REG_C3_V3) & BIT_MASK_REG_C3_V3) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC4Q_EMPTY BIT(4) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_REG_MBIAS BIT(4) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_REG_CP 2 -#define BIT_MASK_REG_CP 0x3 -#define BIT_REG_CP(x) (((x) & BIT_MASK_REG_CP) << BIT_SHIFT_REG_CP) -#define BIT_GET_REG_CP(x) (((x) >> BIT_SHIFT_REG_CP) & BIT_MASK_REG_CP) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC3Q_EMPTY BIT(3) #endif - #if (HALMAC_8814A_SUPPORT) - /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_REG_320_SEL_V3 BIT(2) +#define BIT_SHIFT_REG_C3_V3 3 +#define BIT_MASK_REG_C3_V3 0x3 +#define BIT_REG_C3_V3(x) (((x) & BIT_MASK_REG_C3_V3) << BIT_SHIFT_REG_C3_V3) +#define BITS_REG_C3_V3 (BIT_MASK_REG_C3_V3 << BIT_SHIFT_REG_C3_V3) +#define BIT_CLEAR_REG_C3_V3(x) ((x) & (~BITS_REG_C3_V3)) +#define BIT_GET_REG_C3_V3(x) (((x) >> BIT_SHIFT_REG_C3_V3) & BIT_MASK_REG_C3_V3) +#define BIT_SET_REG_C3_V3(x, v) (BIT_CLEAR_REG_C3_V3(x) | BIT_REG_C3_V3(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_EN_SYN_V1 BIT(1) +#define BIT_SHIFT_REG_CP 2 +#define BIT_MASK_REG_CP 0x3 +#define BIT_REG_CP(x) (((x) & BIT_MASK_REG_CP) << BIT_SHIFT_REG_CP) +#define BITS_REG_CP (BIT_MASK_REG_CP << BIT_SHIFT_REG_CP) +#define BIT_CLEAR_REG_CP(x) ((x) & (~BITS_REG_CP)) +#define BIT_GET_REG_CP(x) (((x) >> BIT_SHIFT_REG_CP) & BIT_MASK_REG_CP) +#define BIT_SET_REG_CP(x, v) (BIT_CLEAR_REG_CP(x) | BIT_REG_CP(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC2Q_EMPTY BIT(2) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8814A_SUPPORT) -#define BIT_SHIFT_REG_R3_V4 1 -#define BIT_MASK_REG_R3_V4 0x7 -#define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4) -#define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_REG_320_SEL_V3 BIT(2) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC1Q_EMPTY BIT(1) -/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_REG_C3 0 -#define BIT_MASK_REG_C3 0x3 -#define BIT_REG_C3(x) (((x) & BIT_MASK_REG_C3) << BIT_SHIFT_REG_C3) -#define BIT_GET_REG_C3(x) (((x) >> BIT_SHIFT_REG_C3) & BIT_MASK_REG_C3) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_EN_SYN_V1 BIT(1) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_IOOFFSET_BIT4 BIT(0) +#define BIT_SHIFT_REG_R3_V4 1 +#define BIT_MASK_REG_R3_V4 0x7 +#define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4) +#define BITS_REG_R3_V4 (BIT_MASK_REG_R3_V4 << BIT_SHIFT_REG_R3_V4) +#define BIT_CLEAR_REG_R3_V4(x) ((x) & (~BITS_REG_R3_V4)) +#define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4) +#define BIT_SET_REG_R3_V4(x, v) (BIT_CLEAR_REG_R3_V4(x) | BIT_REG_R3_V4(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ -#define BIT_REG_CP_BIT0 BIT(0) +#define BIT_SHIFT_REG_C3 0 +#define BIT_MASK_REG_C3 0x3 +#define BIT_REG_C3(x) (((x) & BIT_MASK_REG_C3) << BIT_SHIFT_REG_C3) +#define BITS_REG_C3 (BIT_MASK_REG_C3 << BIT_SHIFT_REG_C3) +#define BIT_CLEAR_REG_C3(x) ((x) & (~BITS_REG_C3)) +#define BIT_GET_REG_C3(x) (((x) >> BIT_SHIFT_REG_C3) & BIT_MASK_REG_C3) +#define BIT_SET_REG_C3(x, v) (BIT_CLEAR_REG_C3(x) | BIT_REG_C3(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */ +#define BIT_SDIO_AC0Q_EMPTY BIT(0) -/* 2 REG_EFUSE_CTRL (Offset 0x0030) */ +#endif -#define BIT_EF_FLAG BIT(31) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_EF_PGPD 28 -#define BIT_MASK_EF_PGPD 0x7 -#define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD) -#define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_IOOFFSET_BIT4 BIT(0) -#define BIT_SHIFT_EF_RDT 24 -#define BIT_MASK_EF_RDT 0xf -#define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT) -#define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT) +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_EF_PGTS 20 -#define BIT_MASK_EF_PGTS 0xf -#define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS) -#define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS) +/* 2 REG_AFE_CTRL3 (Offset 0x002C) */ +#define BIT_REG_CP_BIT0 BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ -#define BIT_EF_PDWN BIT(19) +#define BIT_EF_FLAG BIT(31) -#endif +#define BIT_SHIFT_EF_PGPD 28 +#define BIT_MASK_EF_PGPD 0x7 +#define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD) +#define BITS_EF_PGPD (BIT_MASK_EF_PGPD << BIT_SHIFT_EF_PGPD) +#define BIT_CLEAR_EF_PGPD(x) ((x) & (~BITS_EF_PGPD)) +#define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD) +#define BIT_SET_EF_PGPD(x, v) (BIT_CLEAR_EF_PGPD(x) | BIT_EF_PGPD(v)) + +#define BIT_SHIFT_EF_RDT 24 +#define BIT_MASK_EF_RDT 0xf +#define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT) +#define BITS_EF_RDT (BIT_MASK_EF_RDT << BIT_SHIFT_EF_RDT) +#define BIT_CLEAR_EF_RDT(x) ((x) & (~BITS_EF_RDT)) +#define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT) +#define BIT_SET_EF_RDT(x, v) (BIT_CLEAR_EF_RDT(x) | BIT_EF_RDT(v)) +#define BIT_SHIFT_EF_PGTS 20 +#define BIT_MASK_EF_PGTS 0xf +#define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS) +#define BITS_EF_PGTS (BIT_MASK_EF_PGTS << BIT_SHIFT_EF_PGTS) +#define BIT_CLEAR_EF_PGTS(x) ((x) & (~BITS_EF_PGTS)) +#define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS) +#define BIT_SET_EF_PGTS(x, v) (BIT_CLEAR_EF_PGTS(x) | BIT_EF_PGTS(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ -#define BIT_EF_ALDEN BIT(18) +#define BIT_EF_PDWN BIT(19) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_EFUSE_CTRL (Offset 0x0030) */ +#define BIT_EF_ALDEN BIT(18) -/* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HTSFR1 16 -#define BIT_MASK_HTSFR1 0xffff -#define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1) -#define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1) +/* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ +#define BIT_SHIFT_HTSFR1 16 +#define BIT_MASK_HTSFR1 0xffff +#define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1) +#define BITS_HTSFR1 (BIT_MASK_HTSFR1 << BIT_SHIFT_HTSFR1) +#define BIT_CLEAR_HTSFR1(x) ((x) & (~BITS_HTSFR1)) +#define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1) +#define BIT_SET_HTSFR1(x, v) (BIT_CLEAR_HTSFR1(x) | BIT_HTSFR1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ +#define BIT_SHIFT_EF_ADDR 8 +#define BIT_MASK_EF_ADDR 0x3ff +#define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) +#define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR) +#define BIT_CLEAR_EF_ADDR(x) ((x) & (~BITS_EF_ADDR)) +#define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR) +#define BIT_SET_EF_ADDR(x, v) (BIT_CLEAR_EF_ADDR(x) | BIT_EF_ADDR(v)) + +#define BIT_SHIFT_EF_DATA 0 +#define BIT_MASK_EF_DATA 0xff +#define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA) +#define BITS_EF_DATA (BIT_MASK_EF_DATA << BIT_SHIFT_EF_DATA) +#define BIT_CLEAR_EF_DATA(x) ((x) & (~BITS_EF_DATA)) +#define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA) +#define BIT_SET_EF_DATA(x, v) (BIT_CLEAR_EF_DATA(x) | BIT_EF_DATA(v)) -#define BIT_SHIFT_EF_ADDR 8 -#define BIT_MASK_EF_ADDR 0x3ff -#define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) -#define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_EF_DATA 0 -#define BIT_MASK_EF_DATA 0xff -#define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA) -#define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA) +/* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ +#define BIT_SHIFT_HTSFR0 0 +#define BIT_MASK_HTSFR0 0xffff +#define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0) +#define BITS_HTSFR0 (BIT_MASK_HTSFR0 << BIT_SHIFT_HTSFR0) +#define BIT_CLEAR_HTSFR0(x) ((x) & (~BITS_HTSFR0)) +#define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0) +#define BIT_SET_HTSFR0(x, v) (BIT_CLEAR_HTSFR0(x) | BIT_HTSFR0(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ +#define BIT_LDOE25_EN BIT(31) -/* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HTSFR0 0 -#define BIT_MASK_HTSFR0 0xffff -#define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0) -#define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0) +/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ +#define BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2 28 +#define BIT_MASK_LDOE25_VADJ_BIT0_TO_2 0x7 +#define BIT_LDOE25_VADJ_BIT0_TO_2(x) \ + (((x) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2) \ + << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) +#define BITS_LDOE25_VADJ_BIT0_TO_2 \ + (BIT_MASK_LDOE25_VADJ_BIT0_TO_2 << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) +#define BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) ((x) & (~BITS_LDOE25_VADJ_BIT0_TO_2)) +#define BIT_GET_LDOE25_VADJ_BIT0_TO_2(x) \ + (((x) >> BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) & \ + BIT_MASK_LDOE25_VADJ_BIT0_TO_2) +#define BIT_SET_LDOE25_VADJ_BIT0_TO_2(x, v) \ + (BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) | BIT_LDOE25_VADJ_BIT0_TO_2(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_LDOE25_EN BIT(31) +#define BIT_SHIFT_LDOE25_V12ADJ_L_LOW 28 +#define BIT_MASK_LDOE25_V12ADJ_L_LOW 0x7 +#define BIT_LDOE25_V12ADJ_L_LOW(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L_LOW) << BIT_SHIFT_LDOE25_V12ADJ_L_LOW) +#define BITS_LDOE25_V12ADJ_L_LOW \ + (BIT_MASK_LDOE25_V12ADJ_L_LOW << BIT_SHIFT_LDOE25_V12ADJ_L_LOW) +#define BIT_CLEAR_LDOE25_V12ADJ_L_LOW(x) ((x) & (~BITS_LDOE25_V12ADJ_L_LOW)) +#define BIT_GET_LDOE25_V12ADJ_L_LOW(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_LOW) & BIT_MASK_LDOE25_V12ADJ_L_LOW) +#define BIT_SET_LDOE25_V12ADJ_L_LOW(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L_LOW(x) | BIT_LDOE25_V12ADJ_L_LOW(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2 28 -#define BIT_MASK_LDOE25_VADJ_BIT0_TO_2 0x7 -#define BIT_LDOE25_VADJ_BIT0_TO_2(x) (((x) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2) << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) -#define BIT_GET_LDOE25_VADJ_BIT0_TO_2(x) (((x) >> BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2) - -#define BIT_LDOE25_VADJ_BIT3 BIT(27) +#define BIT_LDOE25_VADJ_BIT3 BIT(27) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ +#define BIT_LDOE25_V12ADJ_L_HIGH BIT(27) -/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_LDOE25_V12ADJ_L 27 -#define BIT_MASK_LDOE25_V12ADJ_L 0xf -#define BIT_LDOE25_V12ADJ_L(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L) -#define BIT_GET_LDOE25_V12ADJ_L(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L) +/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ +#define BIT_SHIFT_LDOE25_V12ADJ_L 27 +#define BIT_MASK_LDOE25_V12ADJ_L 0xf +#define BIT_LDOE25_V12ADJ_L(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L) +#define BITS_LDOE25_V12ADJ_L \ + (BIT_MASK_LDOE25_V12ADJ_L << BIT_SHIFT_LDOE25_V12ADJ_L) +#define BIT_CLEAR_LDOE25_V12ADJ_L(x) ((x) & (~BITS_LDOE25_V12ADJ_L)) +#define BIT_GET_LDOE25_V12ADJ_L(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L) +#define BIT_SET_LDOE25_V12ADJ_L(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L(x) | BIT_LDOE25_V12ADJ_L(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_SHIFT_LDOE25_VADJ_3_TO_0 27 -#define BIT_MASK_LDOE25_VADJ_3_TO_0 0xf -#define BIT_LDOE25_VADJ_3_TO_0(x) (((x) & BIT_MASK_LDOE25_VADJ_3_TO_0) << BIT_SHIFT_LDOE25_VADJ_3_TO_0) -#define BIT_GET_LDOE25_VADJ_3_TO_0(x) (((x) >> BIT_SHIFT_LDOE25_VADJ_3_TO_0) & BIT_MASK_LDOE25_VADJ_3_TO_0) - +#define BIT_SHIFT_LDOE25_VADJ_3_TO_0 27 +#define BIT_MASK_LDOE25_VADJ_3_TO_0 0xf +#define BIT_LDOE25_VADJ_3_TO_0(x) \ + (((x) & BIT_MASK_LDOE25_VADJ_3_TO_0) << BIT_SHIFT_LDOE25_VADJ_3_TO_0) +#define BITS_LDOE25_VADJ_3_TO_0 \ + (BIT_MASK_LDOE25_VADJ_3_TO_0 << BIT_SHIFT_LDOE25_VADJ_3_TO_0) +#define BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) ((x) & (~BITS_LDOE25_VADJ_3_TO_0)) +#define BIT_GET_LDOE25_VADJ_3_TO_0(x) \ + (((x) >> BIT_SHIFT_LDOE25_VADJ_3_TO_0) & BIT_MASK_LDOE25_VADJ_3_TO_0) +#define BIT_SET_LDOE25_VADJ_3_TO_0(x, v) \ + (BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) | BIT_LDOE25_VADJ_3_TO_0(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_EFCRES_SEL BIT(26) +#define BIT_EFCRES_SEL BIT(26) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_EF_CSER BIT(26) +#define BIT_EF_CRES_SEL BIT(26) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_EF_CRES_SEL BIT(26) +#define BIT_EF_CSER BIT(26) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_SHIFT_EF_SCAN_START 16 -#define BIT_MASK_EF_SCAN_START 0x1ff -#define BIT_EF_SCAN_START(x) (((x) & BIT_MASK_EF_SCAN_START) << BIT_SHIFT_EF_SCAN_START) -#define BIT_GET_EF_SCAN_START(x) (((x) >> BIT_SHIFT_EF_SCAN_START) & BIT_MASK_EF_SCAN_START) - +#define BIT_SHIFT_EF_SCAN_START 16 +#define BIT_MASK_EF_SCAN_START 0x1ff +#define BIT_EF_SCAN_START(x) \ + (((x) & BIT_MASK_EF_SCAN_START) << BIT_SHIFT_EF_SCAN_START) +#define BITS_EF_SCAN_START (BIT_MASK_EF_SCAN_START << BIT_SHIFT_EF_SCAN_START) +#define BIT_CLEAR_EF_SCAN_START(x) ((x) & (~BITS_EF_SCAN_START)) +#define BIT_GET_EF_SCAN_START(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START) & BIT_MASK_EF_SCAN_START) +#define BIT_SET_EF_SCAN_START(x, v) \ + (BIT_CLEAR_EF_SCAN_START(x) | BIT_EF_SCAN_START(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_SHIFT_EF_SCAN_START_V1 16 -#define BIT_MASK_EF_SCAN_START_V1 0x3ff -#define BIT_EF_SCAN_START_V1(x) (((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1) -#define BIT_GET_EF_SCAN_START_V1(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1) - +#define BIT_SHIFT_EF_SCAN_START_V1 16 +#define BIT_MASK_EF_SCAN_START_V1 0x3ff +#define BIT_EF_SCAN_START_V1(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1) +#define BITS_EF_SCAN_START_V1 \ + (BIT_MASK_EF_SCAN_START_V1 << BIT_SHIFT_EF_SCAN_START_V1) +#define BIT_CLEAR_EF_SCAN_START_V1(x) ((x) & (~BITS_EF_SCAN_START_V1)) +#define BIT_GET_EF_SCAN_START_V1(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1) +#define BIT_SET_EF_SCAN_START_V1(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1(x) | BIT_EF_SCAN_START_V1(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_SHIFT_EF_SCAN_END 12 -#define BIT_MASK_EF_SCAN_END 0xf -#define BIT_EF_SCAN_END(x) (((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END) -#define BIT_GET_EF_SCAN_END(x) (((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END) - +#define BIT_SHIFT_EF_SCAN_END 12 +#define BIT_MASK_EF_SCAN_END 0xf +#define BIT_EF_SCAN_END(x) \ + (((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END) +#define BITS_EF_SCAN_END (BIT_MASK_EF_SCAN_END << BIT_SHIFT_EF_SCAN_END) +#define BIT_CLEAR_EF_SCAN_END(x) ((x) & (~BITS_EF_SCAN_END)) +#define BIT_GET_EF_SCAN_END(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END) +#define BIT_SET_EF_SCAN_END(x, v) \ + (BIT_CLEAR_EF_SCAN_END(x) | BIT_EF_SCAN_END(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_EF_FORCE_PGMEN BIT(11) +#define BIT_EF_FORCE_PGMEN BIT(11) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_SCAN_EN BIT(11) +#define BIT_EF_PD_DIS BIT(11) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_EF_PD_DIS BIT(11) +#define BIT_SCAN_EN BIT(11) +#define BIT_SW_PG_EN BIT(10) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ -#define BIT_SW_PG_EN BIT(10) +#define BIT_SHIFT_EF_CELL_SEL 8 +#define BIT_MASK_EF_CELL_SEL 0x3 +#define BIT_EF_CELL_SEL(x) \ + (((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL) +#define BITS_EF_CELL_SEL (BIT_MASK_EF_CELL_SEL << BIT_SHIFT_EF_CELL_SEL) +#define BIT_CLEAR_EF_CELL_SEL(x) ((x) & (~BITS_EF_CELL_SEL)) +#define BIT_GET_EF_CELL_SEL(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL) +#define BIT_SET_EF_CELL_SEL(x, v) \ + (BIT_CLEAR_EF_CELL_SEL(x) | BIT_EF_CELL_SEL(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ +#define BIT_EF_TRPT BIT(7) -#define BIT_SHIFT_EF_CELL_SEL 8 -#define BIT_MASK_EF_CELL_SEL 0x3 -#define BIT_EF_CELL_SEL(x) (((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL) -#define BIT_GET_EF_CELL_SEL(x) (((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL) - +#define BIT_SHIFT_EF_TTHD 0 +#define BIT_MASK_EF_TTHD 0x7f +#define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD) +#define BITS_EF_TTHD (BIT_MASK_EF_TTHD << BIT_SHIFT_EF_TTHD) +#define BIT_CLEAR_EF_TTHD(x) ((x) & (~BITS_EF_TTHD)) +#define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD) +#define BIT_SET_EF_TTHD(x, v) (BIT_CLEAR_EF_TTHD(x) | BIT_EF_TTHD(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ - -#define BIT_EF_TRPT BIT(7) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SHIFT_EF_TTHD 0 -#define BIT_MASK_EF_TTHD 0x7f -#define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD) -#define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD) +#define BIT_SHIFT_UPHY_BG_ON_OPT 30 +#define BIT_MASK_UPHY_BG_ON_OPT 0x3 +#define BIT_UPHY_BG_ON_OPT(x) \ + (((x) & BIT_MASK_UPHY_BG_ON_OPT) << BIT_SHIFT_UPHY_BG_ON_OPT) +#define BITS_UPHY_BG_ON_OPT \ + (BIT_MASK_UPHY_BG_ON_OPT << BIT_SHIFT_UPHY_BG_ON_OPT) +#define BIT_CLEAR_UPHY_BG_ON_OPT(x) ((x) & (~BITS_UPHY_BG_ON_OPT)) +#define BIT_GET_UPHY_BG_ON_OPT(x) \ + (((x) >> BIT_SHIFT_UPHY_BG_ON_OPT) & BIT_MASK_UPHY_BG_ON_OPT) +#define BIT_SET_UPHY_BG_ON_OPT(x, v) \ + (BIT_CLEAR_UPHY_BG_ON_OPT(x) | BIT_UPHY_BG_ON_OPT(v)) +#define BIT_UPHY_BG_ON_USB2 BIT(29) +#define BIT_UPHY_BG_ON_PCIE BIT(28) +#define BIT_VD33IO_LEFT_SHD_N_ BIT(27) +#define BIT_VDIO_RIGHT1_SHD_N_ BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_AFE_USB_CURRENT_SEL 26 +#define BIT_MASK_AFE_USB_CURRENT_SEL 0x7 +#define BIT_AFE_USB_CURRENT_SEL(x) \ + (((x) & BIT_MASK_AFE_USB_CURRENT_SEL) << BIT_SHIFT_AFE_USB_CURRENT_SEL) +#define BITS_AFE_USB_CURRENT_SEL \ + (BIT_MASK_AFE_USB_CURRENT_SEL << BIT_SHIFT_AFE_USB_CURRENT_SEL) +#define BIT_CLEAR_AFE_USB_CURRENT_SEL(x) ((x) & (~BITS_AFE_USB_CURRENT_SEL)) +#define BIT_GET_AFE_USB_CURRENT_SEL(x) \ + (((x) >> BIT_SHIFT_AFE_USB_CURRENT_SEL) & BIT_MASK_AFE_USB_CURRENT_SEL) +#define BIT_SET_AFE_USB_CURRENT_SEL(x, v) \ + (BIT_CLEAR_AFE_USB_CURRENT_SEL(x) | BIT_AFE_USB_CURRENT_SEL(v)) -#define BIT_SHIFT_AFE_USB_CURRENT_SEL 26 -#define BIT_MASK_AFE_USB_CURRENT_SEL 0x7 -#define BIT_AFE_USB_CURRENT_SEL(x) (((x) & BIT_MASK_AFE_USB_CURRENT_SEL) << BIT_SHIFT_AFE_USB_CURRENT_SEL) -#define BIT_GET_AFE_USB_CURRENT_SEL(x) (((x) >> BIT_SHIFT_AFE_USB_CURRENT_SEL) & BIT_MASK_AFE_USB_CURRENT_SEL) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_AFE_USB_PATH_SEL 24 -#define BIT_MASK_AFE_USB_PATH_SEL 0x3 -#define BIT_AFE_USB_PATH_SEL(x) (((x) & BIT_MASK_AFE_USB_PATH_SEL) << BIT_SHIFT_AFE_USB_PATH_SEL) -#define BIT_GET_AFE_USB_PATH_SEL(x) (((x) >> BIT_SHIFT_AFE_USB_PATH_SEL) & BIT_MASK_AFE_USB_PATH_SEL) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_VDIO_RIGHT0_SHD_N_ BIT(25) +#define BIT_DIS_LPS_WT_PDNSUS BIT(24) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_AFE_USB_PATH_SEL 24 +#define BIT_MASK_AFE_USB_PATH_SEL 0x3 +#define BIT_AFE_USB_PATH_SEL(x) \ + (((x) & BIT_MASK_AFE_USB_PATH_SEL) << BIT_SHIFT_AFE_USB_PATH_SEL) +#define BITS_AFE_USB_PATH_SEL \ + (BIT_MASK_AFE_USB_PATH_SEL << BIT_SHIFT_AFE_USB_PATH_SEL) +#define BIT_CLEAR_AFE_USB_PATH_SEL(x) ((x) & (~BITS_AFE_USB_PATH_SEL)) +#define BIT_GET_AFE_USB_PATH_SEL(x) \ + (((x) >> BIT_SHIFT_AFE_USB_PATH_SEL) & BIT_MASK_AFE_USB_PATH_SEL) +#define BIT_SET_AFE_USB_PATH_SEL(x, v) \ + (BIT_CLEAR_AFE_USB_PATH_SEL(x) | BIT_AFE_USB_PATH_SEL(v)) -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DBG_SEL_V1 16 -#define BIT_MASK_DBG_SEL_V1 0xff -#define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1) -#define BIT_GET_DBG_SEL_V1(x) (((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_DBG_SEL_V1 16 +#define BIT_MASK_DBG_SEL_V1 0xff +#define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1) +#define BITS_DBG_SEL_V1 (BIT_MASK_DBG_SEL_V1 << BIT_SHIFT_DBG_SEL_V1) +#define BIT_CLEAR_DBG_SEL_V1(x) ((x) & (~BITS_DBG_SEL_V1)) +#define BIT_GET_DBG_SEL_V1(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1) +#define BIT_SET_DBG_SEL_V1(x, v) (BIT_CLEAR_DBG_SEL_V1(x) | BIT_DBG_SEL_V1(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_CLK_REQ_INPUT BIT(15) -#define BIT_USB_XTAL_CLK_SEL BIT(14) +#define BIT_CLK_REQ_INPUT BIT(15) +#define BIT_USB_XTAL_CLK_SEL BIT(14) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ - -#define BIT_SHIFT_DBG_SEL_BYTE 14 -#define BIT_MASK_DBG_SEL_BYTE 0x3 -#define BIT_DBG_SEL_BYTE(x) (((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE) -#define BIT_GET_DBG_SEL_BYTE(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE) - +#define BIT_SHIFT_DBG_SEL_BYTE 14 +#define BIT_MASK_DBG_SEL_BYTE 0x3 +#define BIT_DBG_SEL_BYTE(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE) +#define BITS_DBG_SEL_BYTE (BIT_MASK_DBG_SEL_BYTE << BIT_SHIFT_DBG_SEL_BYTE) +#define BIT_CLEAR_DBG_SEL_BYTE(x) ((x) & (~BITS_DBG_SEL_BYTE)) +#define BIT_GET_DBG_SEL_BYTE(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE) +#define BIT_SET_DBG_SEL_BYTE(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE(x) | BIT_DBG_SEL_BYTE(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_USB_REG_XTAL_SEL BIT(14) -#define BIT_SYSON_BTIO1POW_PAD_E2 BIT(13) +#define BIT_USB_REG_XTAL_SEL BIT(14) +#define BIT_SYSON_BTIO1POW_PAD_E2 BIT(13) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ - -#define BIT_SHIFT_SYSON_SPS0_STD_L1 12 -#define BIT_MASK_SYSON_SPS0_STD_L1 0x3 -#define BIT_SYSON_SPS0_STD_L1(x) (((x) & BIT_MASK_SYSON_SPS0_STD_L1) << BIT_SHIFT_SYSON_SPS0_STD_L1) -#define BIT_GET_SYSON_SPS0_STD_L1(x) (((x) >> BIT_SHIFT_SYSON_SPS0_STD_L1) & BIT_MASK_SYSON_SPS0_STD_L1) - +#define BIT_SHIFT_SYSON_SPS0_STD_L1 12 +#define BIT_MASK_SYSON_SPS0_STD_L1 0x3 +#define BIT_SYSON_SPS0_STD_L1(x) \ + (((x) & BIT_MASK_SYSON_SPS0_STD_L1) << BIT_SHIFT_SYSON_SPS0_STD_L1) +#define BITS_SYSON_SPS0_STD_L1 \ + (BIT_MASK_SYSON_SPS0_STD_L1 << BIT_SHIFT_SYSON_SPS0_STD_L1) +#define BIT_CLEAR_SYSON_SPS0_STD_L1(x) ((x) & (~BITS_SYSON_SPS0_STD_L1)) +#define BIT_GET_SYSON_SPS0_STD_L1(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0_STD_L1) & BIT_MASK_SYSON_SPS0_STD_L1) +#define BIT_SET_SYSON_SPS0_STD_L1(x, v) \ + (BIT_CLEAR_SYSON_SPS0_STD_L1(x) | BIT_SYSON_SPS0_STD_L1(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ - -#define BIT_SHIFT_STD_L1_V1 12 -#define BIT_MASK_STD_L1_V1 0x3 -#define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1) -#define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1) - +#define BIT_SHIFT_STD_L1_V1 12 +#define BIT_MASK_STD_L1_V1 0x3 +#define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1) +#define BITS_STD_L1_V1 (BIT_MASK_STD_L1_V1 << BIT_SHIFT_STD_L1_V1) +#define BIT_CLEAR_STD_L1_V1(x) ((x) & (~BITS_STD_L1_V1)) +#define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1) +#define BIT_SET_STD_L1_V1(x, v) (BIT_CLEAR_STD_L1_V1(x) | BIT_STD_L1_V1(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_BTIOPOW_PAD_E2 BIT(12) +#define BIT_SYSON_BTIOPOW_PAD_E2 BIT(12) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ - -#define BIT_SHIFT_SYSON_LDOA12V_WT 12 -#define BIT_MASK_SYSON_LDOA12V_WT 0x3 -#define BIT_SYSON_LDOA12V_WT(x) (((x) & BIT_MASK_SYSON_LDOA12V_WT) << BIT_SHIFT_SYSON_LDOA12V_WT) -#define BIT_GET_SYSON_LDOA12V_WT(x) (((x) >> BIT_SHIFT_SYSON_LDOA12V_WT) & BIT_MASK_SYSON_LDOA12V_WT) - +#define BIT_SHIFT_SYSON_LDOA12V_WT 12 +#define BIT_MASK_SYSON_LDOA12V_WT 0x3 +#define BIT_SYSON_LDOA12V_WT(x) \ + (((x) & BIT_MASK_SYSON_LDOA12V_WT) << BIT_SHIFT_SYSON_LDOA12V_WT) +#define BITS_SYSON_LDOA12V_WT \ + (BIT_MASK_SYSON_LDOA12V_WT << BIT_SHIFT_SYSON_LDOA12V_WT) +#define BIT_CLEAR_SYSON_LDOA12V_WT(x) ((x) & (~BITS_SYSON_LDOA12V_WT)) +#define BIT_GET_SYSON_LDOA12V_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_LDOA12V_WT) & BIT_MASK_SYSON_LDOA12V_WT) +#define BIT_SET_SYSON_LDOA12V_WT(x, v) \ + (BIT_CLEAR_SYSON_LDOA12V_WT(x) | BIT_SYSON_LDOA12V_WT(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_DBG_PAD_E2 BIT(11) +#define BIT_SYSON_DBG_PAD_E2 BIT(11) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_SDIOPOW_PAD_E2 BIT(11) +#define BIT_SYSON_SDIOPOW_PAD_E2 BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_LED_PAD_E2 BIT(10) +#define BIT_SYSON_LED_PAD_E2 BIT(10) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_GPEE_PAD_E2 BIT(9) +#define BIT_SYSON_GPEE_PAD_E2 BIT(9) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_GPEE_PAD_E2_V33 BIT(9) +#define BIT_SYSON_GPEE_PAD_E2_V33 BIT(9) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_SYSON_PCI_PAD_E2 BIT(8) - -#define BIT_SHIFT_MATCH_CNT 8 -#define BIT_MASK_MATCH_CNT 0xff -#define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT) -#define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT) +#define BIT_SYSON_PCI_PAD_E2 BIT(8) +#define BIT_SHIFT_MATCH_CNT 8 +#define BIT_MASK_MATCH_CNT 0xff +#define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT) +#define BITS_MATCH_CNT (BIT_MASK_MATCH_CNT << BIT_SHIFT_MATCH_CNT) +#define BIT_CLEAR_MATCH_CNT(x) ((x) & (~BITS_MATCH_CNT)) +#define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT) +#define BIT_SET_MATCH_CNT(x, v) (BIT_CLEAR_MATCH_CNT(x) | BIT_MATCH_CNT(v)) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_AUTO_SW_LDO_VOL_EN BIT(7) +#define BIT_AUTO_SW_LDO_VOL_EN BIT(7) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_AUTO_SW_LDO_VOL_EN_V1 BIT(6) +#define BIT_AUTO_SW_LDO_VOL_EN_V1 BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ -#define BIT_ADJ_LDO_VOLT BIT(6) +#define BIT_ADJ_LDO_VOLT BIT(6) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ - -#define BIT_SHIFT_SYSON_LDOHCI12_WT 6 -#define BIT_MASK_SYSON_LDOHCI12_WT 0x3 -#define BIT_SYSON_LDOHCI12_WT(x) (((x) & BIT_MASK_SYSON_LDOHCI12_WT) << BIT_SHIFT_SYSON_LDOHCI12_WT) -#define BIT_GET_SYSON_LDOHCI12_WT(x) (((x) >> BIT_SHIFT_SYSON_LDOHCI12_WT) & BIT_MASK_SYSON_LDOHCI12_WT) - +#define BIT_SHIFT_SYSON_LDOHCI12_WT 6 +#define BIT_MASK_SYSON_LDOHCI12_WT 0x3 +#define BIT_SYSON_LDOHCI12_WT(x) \ + (((x) & BIT_MASK_SYSON_LDOHCI12_WT) << BIT_SHIFT_SYSON_LDOHCI12_WT) +#define BITS_SYSON_LDOHCI12_WT \ + (BIT_MASK_SYSON_LDOHCI12_WT << BIT_SHIFT_SYSON_LDOHCI12_WT) +#define BIT_CLEAR_SYSON_LDOHCI12_WT(x) ((x) & (~BITS_SYSON_LDOHCI12_WT)) +#define BIT_GET_SYSON_LDOHCI12_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_LDOHCI12_WT) & BIT_MASK_SYSON_LDOHCI12_WT) +#define BIT_SET_SYSON_LDOHCI12_WT(x, v) \ + (BIT_CLEAR_SYSON_LDOHCI12_WT(x) | BIT_SYSON_LDOHCI12_WT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_SYSON_SPS0WWV_WT 4 +#define BIT_MASK_SYSON_SPS0WWV_WT 0x3 +#define BIT_SYSON_SPS0WWV_WT(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT) +#define BITS_SYSON_SPS0WWV_WT \ + (BIT_MASK_SYSON_SPS0WWV_WT << BIT_SHIFT_SYSON_SPS0WWV_WT) +#define BIT_CLEAR_SYSON_SPS0WWV_WT(x) ((x) & (~BITS_SYSON_SPS0WWV_WT)) +#define BIT_GET_SYSON_SPS0WWV_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT) +#define BIT_SET_SYSON_SPS0WWV_WT(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT(x) | BIT_SYSON_SPS0WWV_WT(v)) -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_SYSON_SPS0WWV_WT 4 -#define BIT_MASK_SYSON_SPS0WWV_WT 0x3 -#define BIT_SYSON_SPS0WWV_WT(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT) -#define BIT_GET_SYSON_SPS0WWV_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_SYSON_SPS0SPS_WT 4 +#define BIT_MASK_SYSON_SPS0SPS_WT 0x3 +#define BIT_SYSON_SPS0SPS_WT(x) \ + (((x) & BIT_MASK_SYSON_SPS0SPS_WT) << BIT_SHIFT_SYSON_SPS0SPS_WT) +#define BITS_SYSON_SPS0SPS_WT \ + (BIT_MASK_SYSON_SPS0SPS_WT << BIT_SHIFT_SYSON_SPS0SPS_WT) +#define BIT_CLEAR_SYSON_SPS0SPS_WT(x) ((x) & (~BITS_SYSON_SPS0SPS_WT)) +#define BIT_GET_SYSON_SPS0SPS_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0SPS_WT) & BIT_MASK_SYSON_SPS0SPS_WT) +#define BIT_SET_SYSON_SPS0SPS_WT(x, v) \ + (BIT_CLEAR_SYSON_SPS0SPS_WT(x) | BIT_SYSON_SPS0SPS_WT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_SYSON_SPS0LDO_WT 2 +#define BIT_MASK_SYSON_SPS0LDO_WT 0x3 +#define BIT_SYSON_SPS0LDO_WT(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT) +#define BITS_SYSON_SPS0LDO_WT \ + (BIT_MASK_SYSON_SPS0LDO_WT << BIT_SHIFT_SYSON_SPS0LDO_WT) +#define BIT_CLEAR_SYSON_SPS0LDO_WT(x) ((x) & (~BITS_SYSON_SPS0LDO_WT)) +#define BIT_GET_SYSON_SPS0LDO_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT) +#define BIT_SET_SYSON_SPS0LDO_WT(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT(x) | BIT_SYSON_SPS0LDO_WT(v)) -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_SYSON_SPS0SPS_WT 4 -#define BIT_MASK_SYSON_SPS0SPS_WT 0x3 -#define BIT_SYSON_SPS0SPS_WT(x) (((x) & BIT_MASK_SYSON_SPS0SPS_WT) << BIT_SHIFT_SYSON_SPS0SPS_WT) -#define BIT_GET_SYSON_SPS0SPS_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS0SPS_WT) & BIT_MASK_SYSON_SPS0SPS_WT) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_SYSON_SPS11VLDO_WT 2 +#define BIT_MASK_SYSON_SPS11VLDO_WT 0x3 +#define BIT_SYSON_SPS11VLDO_WT(x) \ + (((x) & BIT_MASK_SYSON_SPS11VLDO_WT) << BIT_SHIFT_SYSON_SPS11VLDO_WT) +#define BITS_SYSON_SPS11VLDO_WT \ + (BIT_MASK_SYSON_SPS11VLDO_WT << BIT_SHIFT_SYSON_SPS11VLDO_WT) +#define BIT_CLEAR_SYSON_SPS11VLDO_WT(x) ((x) & (~BITS_SYSON_SPS11VLDO_WT)) +#define BIT_GET_SYSON_SPS11VLDO_WT(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS11VLDO_WT) & BIT_MASK_SYSON_SPS11VLDO_WT) +#define BIT_SET_SYSON_SPS11VLDO_WT(x, v) \ + (BIT_CLEAR_SYSON_SPS11VLDO_WT(x) | BIT_SYSON_SPS11VLDO_WT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#define BIT_SHIFT_SYSON_RCLK_SCALE 0 +#define BIT_MASK_SYSON_RCLK_SCALE 0x3 +#define BIT_SYSON_RCLK_SCALE(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE) +#define BITS_SYSON_RCLK_SCALE \ + (BIT_MASK_SYSON_RCLK_SCALE << BIT_SHIFT_SYSON_RCLK_SCALE) +#define BIT_CLEAR_SYSON_RCLK_SCALE(x) ((x) & (~BITS_SYSON_RCLK_SCALE)) +#define BIT_GET_SYSON_RCLK_SCALE(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE) +#define BIT_SET_SYSON_RCLK_SCALE(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE(x) | BIT_SYSON_RCLK_SCALE(v)) -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SYSON_SPS0LDO_WT 2 -#define BIT_MASK_SYSON_SPS0LDO_WT 0x3 -#define BIT_SYSON_SPS0LDO_WT(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT) -#define BIT_GET_SYSON_SPS0LDO_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT) +/* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */ +#define BIT_CUR_PS BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_CAL_TIMER (Offset 0x003C) */ +#define BIT_SHIFT_CAL_SCAL 0 +#define BIT_MASK_CAL_SCAL 0xff +#define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL) +#define BITS_CAL_SCAL (BIT_MASK_CAL_SCAL << BIT_SHIFT_CAL_SCAL) +#define BIT_CLEAR_CAL_SCAL(x) ((x) & (~BITS_CAL_SCAL)) +#define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL) +#define BIT_SET_CAL_SCAL(x, v) (BIT_CLEAR_CAL_SCAL(x) | BIT_CAL_SCAL(v)) -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +/* 2 REG_ACLK_MON (Offset 0x003E) */ +#define BIT_SHIFT_RCLK_MON 5 +#define BIT_MASK_RCLK_MON 0x7ff +#define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON) +#define BITS_RCLK_MON (BIT_MASK_RCLK_MON << BIT_SHIFT_RCLK_MON) +#define BIT_CLEAR_RCLK_MON(x) ((x) & (~BITS_RCLK_MON)) +#define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON) +#define BIT_SET_RCLK_MON(x, v) (BIT_CLEAR_RCLK_MON(x) | BIT_RCLK_MON(v)) -#define BIT_SHIFT_SYSON_SPS11VLDO_WT 2 -#define BIT_MASK_SYSON_SPS11VLDO_WT 0x3 -#define BIT_SYSON_SPS11VLDO_WT(x) (((x) & BIT_MASK_SYSON_SPS11VLDO_WT) << BIT_SHIFT_SYSON_SPS11VLDO_WT) -#define BIT_GET_SYSON_SPS11VLDO_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS11VLDO_WT) & BIT_MASK_SYSON_SPS11VLDO_WT) +#define BIT_CAL_EN BIT(4) +#define BIT_SHIFT_DPSTU 2 +#define BIT_MASK_DPSTU 0x3 +#define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU) +#define BITS_DPSTU (BIT_MASK_DPSTU << BIT_SHIFT_DPSTU) +#define BIT_CLEAR_DPSTU(x) ((x) & (~BITS_DPSTU)) +#define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU) +#define BIT_SET_DPSTU(x, v) (BIT_CLEAR_DPSTU(x) | BIT_DPSTU(v)) + +#define BIT_SUS_16X BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACLK_MON (Offset 0x003E) */ +#define BIT_RSM_EN BIT(0) -/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SYSON_RCLK_SCALE 0 -#define BIT_MASK_SYSON_RCLK_SCALE 0x3 -#define BIT_SYSON_RCLK_SCALE(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE) -#define BIT_GET_SYSON_RCLK_SCALE(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE) +/* 2 REG_GPIO_MUXCFG_2 (Offset 0x003F) */ +#define BIT_SOUT_GPIO8 BIT(7) +#define BIT_SOUT_GPIO5 BIT(6) +#define BIT_RFE_CTRL_5_GPIO14_V1 BIT(5) +#define BIT_RFE_CTRL_10_GPIO13_V1 BIT(4) +#define BIT_RFE_CTRL_11_GPIO4_V1 BIT(3) +#define BIT_RFE_CTRL_5_GPIO14 BIT(2) +#define BIT_RFE_CTRL_10_GPIO13 BIT(1) +#define BIT_RFE_CTRL_11_GPIO4 BIT(0) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_RFE_CTRL_3_GPIO12 BIT(31) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */ +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_SYS_CLK BIT(0) +#define BIT_PAD_D_PAPE_2G_E BIT(31) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_CAL_TIMER (Offset 0x003C) */ +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_BT_RFE_CTRL_5_GPIO12 BIT(30) -#define BIT_SHIFT_CAL_SCAL 0 -#define BIT_MASK_CAL_SCAL 0xff -#define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL) -#define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_ACLK_MON (Offset 0x003E) */ +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_PAD_D_PAPE_5G_E BIT(30) -#define BIT_SHIFT_RCLK_MON 5 -#define BIT_MASK_RCLK_MON 0x7ff -#define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON) -#define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON) +#endif -#define BIT_CAL_EN BIT(4) +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_DPSTU 2 -#define BIT_MASK_DPSTU 0x3 -#define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU) -#define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_SUS_16X BIT(1) +#define BIT_SIC_LOWEST_PRIORITY_V1 BIT(29) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_S0_TRSW_GPIO12 BIT(29) -/* 2 REG_ACLK_MON (Offset 0x003E) */ +#endif -#define BIT_RSM_EN BIT(0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_PAD_D_TRSW_E BIT(29) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_PAD_D_PAPE_2G_E BIT(31) -#define BIT_PAD_D_PAPE_5G_E BIT(30) -#define BIT_PAD_D_TRSW_E BIT(29) +#define BIT_SIC_PRI_LOWEST BIT(28) #endif - #if (HALMAC_8197F_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_SIC_LOWEST_PRIORITY BIT(28) +#define BIT_SIC_LOWEST_PRIORITY BIT(28) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_RFE_CTRL_9_GPIO13 BIT(28) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_PAD_D_TRSWB_E BIT(28) -#define BIT_PAD_D_PAPE_2G_O BIT(27) -#define BIT_PAD_D_PAPE_5G_O BIT(26) -#define BIT_PAD_D_TRSW_O BIT(25) +#define BIT_PAD_D_TRSWB_E BIT(28) #endif - #if (HALMAC_8197F_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_WL_DSS_RSTN BIT(27) -#define BIT_SHIFT_PIN_USECASE 24 -#define BIT_MASK_PIN_USECASE 0xf -#define BIT_PIN_USECASE(x) (((x) & BIT_MASK_PIN_USECASE) << BIT_SHIFT_PIN_USECASE) -#define BIT_GET_PIN_USECASE(x) (((x) >> BIT_SHIFT_PIN_USECASE) & BIT_MASK_PIN_USECASE) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_RFE_CTRL_9_GPIO12 BIT(27) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_PAD_D_TRSWB_O BIT(24) -#define BIT_EN_A_ANTSEL BIT(23) -#define BIT_EN_A_ANTSELB BIT(22) -#define BIT_EN_D_PAPE_2G BIT(21) +#define BIT_PAD_D_PAPE_2G_O BIT(27) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_WL_DSS_EN_CLK BIT(26) -/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#endif -#define BIT_INDIRECT_REG_RDY BIT(20) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_RFE_CTRL_8_GPIO4 BIT(26) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_EN_D_PAPE_5G BIT(20) +#define BIT_PAD_D_PAPE_5G_O BIT(26) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ + +#define BIT_BT_RFE_CTRL_1_GPIO13 BIT(25) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_FSPI_EN BIT(19) +#define BIT_PAD_D_TRSW_O BIT(25) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_SHIFT_PIN_USECASE 24 +#define BIT_MASK_PIN_USECASE 0xf +#define BIT_PIN_USECASE(x) \ + (((x) & BIT_MASK_PIN_USECASE) << BIT_SHIFT_PIN_USECASE) +#define BITS_PIN_USECASE (BIT_MASK_PIN_USECASE << BIT_SHIFT_PIN_USECASE) +#define BIT_CLEAR_PIN_USECASE(x) ((x) & (~BITS_PIN_USECASE)) +#define BIT_GET_PIN_USECASE(x) \ + (((x) >> BIT_SHIFT_PIN_USECASE) & BIT_MASK_PIN_USECASE) +#define BIT_SET_PIN_USECASE(x, v) \ + (BIT_CLEAR_PIN_USECASE(x) | BIT_PIN_USECASE(v)) -/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#endif -#define BIT_INDIRECT_REG_R BIT(19) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_SHIFT_PIN_USECASE_V1 24 +#define BIT_MASK_PIN_USECASE_V1 0x1f +#define BIT_PIN_USECASE_V1(x) \ + (((x) & BIT_MASK_PIN_USECASE_V1) << BIT_SHIFT_PIN_USECASE_V1) +#define BITS_PIN_USECASE_V1 \ + (BIT_MASK_PIN_USECASE_V1 << BIT_SHIFT_PIN_USECASE_V1) +#define BIT_CLEAR_PIN_USECASE_V1(x) ((x) & (~BITS_PIN_USECASE_V1)) +#define BIT_GET_PIN_USECASE_V1(x) \ + (((x) >> BIT_SHIFT_PIN_USECASE_V1) & BIT_MASK_PIN_USECASE_V1) +#define BIT_SET_PIN_USECASE_V1(x, v) \ + (BIT_CLEAR_PIN_USECASE_V1(x) | BIT_PIN_USECASE_V1(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_WL_RTS_EXT_32K_SEL BIT(18) +#define BIT_BT_RFE_CTRL_1_GPIO12 BIT(24) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_PAD_D_TRSWB_O BIT(24) -/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#endif -#define BIT_INDIRECT_REG_W BIT(18) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_EN_DATACPU_GPIO2 BIT(24) -#if (HALMAC_8192E_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_CKOUT33_EN BIT(17) +#define BIT_BT_RFE_CTRL_0_GPIO4 BIT(23) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_XTAL_OUT_EN BIT(17) +#define BIT_EN_A_ANTSEL BIT(23) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_WLGP_SPI_EN BIT(16) +#define BIT_EN_DATACPU_GPIO BIT(23) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_ANTSW_GPIO13 BIT(22) -/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_INDIRECT_REG_SIZE 16 -#define BIT_MASK_INDIRECT_REG_SIZE 0x3 -#define BIT_INDIRECT_REG_SIZE(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE) -#define BIT_GET_INDIRECT_REG_SIZE(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_EN_A_ANTSELB BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_SIC_LBK BIT(15) -#define BIT_ENHTP BIT(14) +#define BIT_EN_DATACPU_UART BIT(22) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_WLPHY_DBG_EN BIT(13) +#define BIT_ANTSW_GPIO12 BIT(21) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_SIC_23 BIT(13) +#define BIT_EN_D_PAPE_2G BIT(21) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_ENSIC BIT(12) -#define BIT_SIC_SWRST BIT(11) +#define BIT_DATACPU_FSPI_EN BIT(21) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ + +#define BIT_INDIRECT_REG_RDY BIT(20) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_PO_WIFI_PTA_PINS BIT(10) +#define BIT_ANTSWB_GPIO4 BIT(20) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_ENPMAC BIT(10) +#define BIT_EN_D_PAPE_5G BIT(20) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_ENBTCMD BIT(9) +#define BIT_EN_GPIO8_UART_OUT BIT(20) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_BTCOEX_MBOX_EN BIT(9) +#define BIT_FSPI_EN BIT(19) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_BTCMD_OUT_EN BIT(9) +#define BIT_SW_IO_EN BIT(19) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#define BIT_INDIRECT_REG_R BIT(19) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_PO_BT_PTA_PINS BIT(9) +#define BIT_WL_RTS_EXT_32K_SEL BIT(18) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#define BIT_INDIRECT_REG_W BIT(18) -/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#endif -#define BIT_ENUART BIT(8) +#if (HALMAC_8192E_SUPPORT) -#define BIT_SHIFT_BTMODE 6 -#define BIT_MASK_BTMODE 0x3 -#define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE) -#define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_ENBT BIT(5) -#define BIT_EROM_EN BIT(4) +#define BIT_CKOUT33_EN BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_WLRFE_6_7_EN BIT(3) +#define BIT_WLBT_DPDT_SEL_EN BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_EN_D_TRSW BIT(3) +#define BIT_XTAL_OUT_EN BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_WLRFE_4_5_EN BIT(2) +#define BIT_WLGP_SPI_EN BIT(16) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_EN_D_TRSWB BIT(2) +#define BIT_WLGP_CKOUT BIT(16) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#define BIT_SHIFT_INDIRECT_REG_SIZE 16 +#define BIT_MASK_INDIRECT_REG_SIZE 0x3 +#define BIT_INDIRECT_REG_SIZE(x) \ + (((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE) +#define BITS_INDIRECT_REG_SIZE \ + (BIT_MASK_INDIRECT_REG_SIZE << BIT_SHIFT_INDIRECT_REG_SIZE) +#define BIT_CLEAR_INDIRECT_REG_SIZE(x) ((x) & (~BITS_INDIRECT_REG_SIZE)) +#define BIT_GET_INDIRECT_REG_SIZE(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE) +#define BIT_SET_INDIRECT_REG_SIZE(x, v) \ + (BIT_CLEAR_INDIRECT_REG_SIZE(x) | BIT_INDIRECT_REG_SIZE(v)) -/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_GPIOSEL 0 -#define BIT_MASK_GPIOSEL 0x3 -#define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL) -#define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_WLBT_LNAON_SEL_EN BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_SIC_LBK BIT(15) +#define BIT_ENHTP BIT(14) -/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_INDIRECT_REG_ADDR 0 -#define BIT_MASK_INDIRECT_REG_ADDR 0xffff -#define BIT_INDIRECT_REG_ADDR(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR) -#define BIT_GET_INDIRECT_REG_ADDR(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_PHY_TEST_EN BIT(13) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_WLPHY_DBG_EN BIT(13) -/* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_GPIO_MOD_7_TO_0 24 -#define BIT_MASK_GPIO_MOD_7_TO_0 0xff -#define BIT_GPIO_MOD_7_TO_0(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0) -#define BIT_GET_GPIO_MOD_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ + +#define BIT_BT_AOD_GPIO3 BIT(13) + +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16 -#define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff -#define BIT_GPIO_IO_SEL_7_TO_0(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0) -#define BIT_GET_GPIO_IO_SEL_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_SIC_23 BIT(13) -#define BIT_SHIFT_GPIO_OUT_7_TO_0 8 -#define BIT_MASK_GPIO_OUT_7_TO_0 0xff -#define BIT_GPIO_OUT_7_TO_0(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0) -#define BIT_GET_GPIO_OUT_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_GPIO_IN_7_TO_0 0 -#define BIT_MASK_GPIO_IN_7_TO_0 0xff -#define BIT_GPIO_IN_7_TO_0(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0) -#define BIT_GET_GPIO_IN_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_ENSIC BIT(12) +#define BIT_SIC_SWRST BIT(11) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_PO_WIFI_PTA_PINS BIT(10) -/* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_INDIRECT_REG_DATA 0 -#define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL -#define BIT_INDIRECT_REG_DATA(x) (((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA) -#define BIT_GET_INDIRECT_REG_DATA(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_ENPMAC BIT(10) #endif +#if (HALMAC_8192E_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_ENBTCMD BIT(9) -/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_MUXDBG_SEL 30 -#define BIT_MASK_MUXDBG_SEL 0x3 -#define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL) -#define BIT_GET_MUXDBG_SEL(x) (((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_COEX_MBOX BIT(9) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_BTCOEX_MBOX_EN BIT(9) -/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MUXDBG_SEL2 28 -#define BIT_MASK_MUXDBG_SEL2 0x3 -#define BIT_MUXDBG_SEL2(x) (((x) & BIT_MASK_MUXDBG_SEL2) << BIT_SHIFT_MUXDBG_SEL2) -#define BIT_GET_MUXDBG_SEL2(x) (((x) >> BIT_SHIFT_MUXDBG_SEL2) & BIT_MASK_MUXDBG_SEL2) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_PO_BT_PTA_PINS BIT(9) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -/* 2 REG_GPIO_INTM (Offset 0x0048) */ - -#define BIT_GPIO_EXT_EN BIT(20) +#define BIT_BTCMD_OUT_EN BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_ENUART BIT(8) -/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#define BIT_SHIFT_BTMODE 6 +#define BIT_MASK_BTMODE 0x3 +#define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE) +#define BITS_BTMODE (BIT_MASK_BTMODE << BIT_SHIFT_BTMODE) +#define BIT_CLEAR_BTMODE(x) ((x) & (~BITS_BTMODE)) +#define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE) +#define BIT_SET_BTMODE(x, v) (BIT_CLEAR_BTMODE(x) | BIT_BTMODE(v)) -#define BIT_EXTWOL1_SEL BIT(19) -#define BIT_EXTWOL1_EN BIT(18) +#define BIT_ENBT BIT(5) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_GEN1GEN2_SWITCH BIT(5) -/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#endif -#define BIT_EXTWOL0_SEL BIT(17) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_EROM_EN BIT(4) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_GPIO_INTM (Offset 0x0048) */ +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_EXTWOL_SEL BIT(17) +#define BIT_ENUARTTX BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_WLRFE_6_7_EN BIT(3) -/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#endif -#define BIT_EXTWOL0_EN BIT(16) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_WLRFE_12_EN BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_GPIO_INTM (Offset 0x0048) */ +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_EXTWOL_EN BIT(16) +#define BIT_EN_D_TRSW BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_WLRFE_4_5_EN BIT(2) -/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_GPIO_EXT_WOL_V1 16 -#define BIT_MASK_GPIO_EXT_WOL_V1 0xf -#define BIT_GPIO_EXT_WOL_V1(x) (((x) & BIT_MASK_GPIO_EXT_WOL_V1) << BIT_SHIFT_GPIO_EXT_WOL_V1) -#define BIT_GET_GPIO_EXT_WOL_V1(x) (((x) >> BIT_SHIFT_GPIO_EXT_WOL_V1) & BIT_MASK_GPIO_EXT_WOL_V1) +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ +#define BIT_SPDT_SEL BIT(2) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ + +#define BIT_EN_D_TRSWB BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_GPIO_INTM (Offset 0x0048) */ +/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ -#define BIT_GPIOF_INT_MD BIT(15) -#define BIT_GPIOE_INT_MD BIT(14) -#define BIT_GPIOD_INT_MD BIT(13) -#define BIT_GPIOC_INT_MD BIT(12) -#define BIT_GPIOB_INT_MD BIT(11) -#define BIT_GPIOA_INT_MD BIT(10) -#define BIT_GPIO9_INT_MD BIT(9) -#define BIT_GPIO8_INT_MD BIT(8) -#define BIT_GPIO7_INT_MD BIT(7) -#define BIT_GPIO6_INT_MD BIT(6) -#define BIT_GPIO5_INT_MD BIT(5) -#define BIT_GPIO4_INT_MD BIT(4) -#define BIT_GPIO3_INT_MD BIT(3) -#define BIT_GPIO2_INT_MD BIT(2) -#define BIT_GPIO1_INT_MD BIT(1) -#define BIT_GPIO0_INT_MD BIT(0) +#define BIT_SHIFT_GPIOSEL 0 +#define BIT_MASK_GPIOSEL 0x3 +#define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL) +#define BITS_GPIOSEL (BIT_MASK_GPIOSEL << BIT_SHIFT_GPIOSEL) +#define BIT_CLEAR_GPIOSEL(x) ((x) & (~BITS_GPIOSEL)) +#define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL) +#define BIT_SET_GPIOSEL(x, v) (BIT_CLEAR_GPIOSEL(x) | BIT_GPIOSEL(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ +#define BIT_SHIFT_INDIRECT_REG_ADDR 0 +#define BIT_MASK_INDIRECT_REG_ADDR 0xffff +#define BIT_INDIRECT_REG_ADDR(x) \ + (((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR) +#define BITS_INDIRECT_REG_ADDR \ + (BIT_MASK_INDIRECT_REG_ADDR << BIT_SHIFT_INDIRECT_REG_ADDR) +#define BIT_CLEAR_INDIRECT_REG_ADDR(x) ((x) & (~BITS_INDIRECT_REG_ADDR)) +#define BIT_GET_INDIRECT_REG_ADDR(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR) +#define BIT_SET_INDIRECT_REG_ADDR(x, v) \ + (BIT_CLEAR_INDIRECT_REG_ADDR(x) | BIT_INDIRECT_REG_ADDR(v)) -/* 2 REG_LED_CFG (Offset 0x004C) */ +#endif -#define BIT_PAD_ANTSEL_I BIT(31) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ +#define BIT_SHIFT_GPIO_MOD_7_TO_0 24 +#define BIT_MASK_GPIO_MOD_7_TO_0 0xff +#define BIT_GPIO_MOD_7_TO_0(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0) +#define BITS_GPIO_MOD_7_TO_0 \ + (BIT_MASK_GPIO_MOD_7_TO_0 << BIT_SHIFT_GPIO_MOD_7_TO_0) +#define BIT_CLEAR_GPIO_MOD_7_TO_0(x) ((x) & (~BITS_GPIO_MOD_7_TO_0)) +#define BIT_GET_GPIO_MOD_7_TO_0(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0) +#define BIT_SET_GPIO_MOD_7_TO_0(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0(x) | BIT_GPIO_MOD_7_TO_0(v)) -#if (HALMAC_8192E_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_LED_CFG (Offset 0x004C) */ +/* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ -#define BIT_ANT_SEL7_EN BIT(30) +#define BIT_SHIFT_WLGP1_SWIOMOD 24 +#define BIT_MASK_WLGP1_SWIOMOD 0xff +#define BIT_WLGP1_SWIOMOD(x) \ + (((x) & BIT_MASK_WLGP1_SWIOMOD) << BIT_SHIFT_WLGP1_SWIOMOD) +#define BITS_WLGP1_SWIOMOD (BIT_MASK_WLGP1_SWIOMOD << BIT_SHIFT_WLGP1_SWIOMOD) +#define BIT_CLEAR_WLGP1_SWIOMOD(x) ((x) & (~BITS_WLGP1_SWIOMOD)) +#define BIT_GET_WLGP1_SWIOMOD(x) \ + (((x) >> BIT_SHIFT_WLGP1_SWIOMOD) & BIT_MASK_WLGP1_SWIOMOD) +#define BIT_SET_WLGP1_SWIOMOD(x, v) \ + (BIT_CLEAR_WLGP1_SWIOMOD(x) | BIT_WLGP1_SWIOMOD(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ +#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16 +#define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff +#define BIT_GPIO_IO_SEL_7_TO_0(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0) +#define BITS_GPIO_IO_SEL_7_TO_0 \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) ((x) & (~BITS_GPIO_IO_SEL_7_TO_0)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0) +#define BIT_SET_GPIO_IO_SEL_7_TO_0(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) | BIT_GPIO_IO_SEL_7_TO_0(v)) + +#define BIT_SHIFT_GPIO_OUT_7_TO_0 8 +#define BIT_MASK_GPIO_OUT_7_TO_0 0xff +#define BIT_GPIO_OUT_7_TO_0(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0) +#define BITS_GPIO_OUT_7_TO_0 \ + (BIT_MASK_GPIO_OUT_7_TO_0 << BIT_SHIFT_GPIO_OUT_7_TO_0) +#define BIT_CLEAR_GPIO_OUT_7_TO_0(x) ((x) & (~BITS_GPIO_OUT_7_TO_0)) +#define BIT_GET_GPIO_OUT_7_TO_0(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0) +#define BIT_SET_GPIO_OUT_7_TO_0(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0(x) | BIT_GPIO_OUT_7_TO_0(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_LED_CFG (Offset 0x004C) */ +/* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ -#define BIT_PAD_ANTSELB_I BIT(30) +#define BIT_SHIFT_GPIO_IN_7_TO_0 0 +#define BIT_MASK_GPIO_IN_7_TO_0 0xff +#define BIT_GPIO_IN_7_TO_0(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0) +#define BITS_GPIO_IN_7_TO_0 \ + (BIT_MASK_GPIO_IN_7_TO_0 << BIT_SHIFT_GPIO_IN_7_TO_0) +#define BIT_CLEAR_GPIO_IN_7_TO_0(x) ((x) & (~BITS_GPIO_IN_7_TO_0)) +#define BIT_GET_GPIO_IN_7_TO_0(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0) +#define BIT_SET_GPIO_IN_7_TO_0(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0(x) | BIT_GPIO_IN_7_TO_0(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */ +#define BIT_SHIFT_INDIRECT_REG_DATA 0 +#define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL +#define BIT_INDIRECT_REG_DATA(x) \ + (((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA) +#define BITS_INDIRECT_REG_DATA \ + (BIT_MASK_INDIRECT_REG_DATA << BIT_SHIFT_INDIRECT_REG_DATA) +#define BIT_CLEAR_INDIRECT_REG_DATA(x) ((x) & (~BITS_INDIRECT_REG_DATA)) +#define BIT_GET_INDIRECT_REG_DATA(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA) +#define BIT_SET_INDIRECT_REG_DATA(x, v) \ + (BIT_CLEAR_INDIRECT_REG_DATA(x) | BIT_INDIRECT_REG_DATA(v)) -/* 2 REG_LED_CFG (Offset 0x004C) */ +#endif -#define BIT_ANT_SEL46_EN BIT(29) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#define BIT_SHIFT_MUXDBG_SEL 30 +#define BIT_MASK_MUXDBG_SEL 0x3 +#define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL) +#define BITS_MUXDBG_SEL (BIT_MASK_MUXDBG_SEL << BIT_SHIFT_MUXDBG_SEL) +#define BIT_CLEAR_MUXDBG_SEL(x) ((x) & (~BITS_MUXDBG_SEL)) +#define BIT_GET_MUXDBG_SEL(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL) +#define BIT_SET_MUXDBG_SEL(x, v) (BIT_CLEAR_MUXDBG_SEL(x) | BIT_MUXDBG_SEL(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_LED_CFG (Offset 0x004C) */ +/* 2 REG_GPIO_INTM (Offset 0x0048) */ -#define BIT_PAD_D_PAPE_2G_I BIT(29) +#define BIT_PCI_LPS_LDACT BIT(29) #endif - #if (HALMAC_8192E_SUPPORT) +/* 2 REG_GPIO_INTM (Offset 0x0048) */ -/* 2 REG_LED_CFG (Offset 0x004C) */ - -#define BIT_ANT_SEL3_EN BIT(28) +#define BIT_SHIFT_MUXDBG_SEL2 28 +#define BIT_MASK_MUXDBG_SEL2 0x3 +#define BIT_MUXDBG_SEL2(x) \ + (((x) & BIT_MASK_MUXDBG_SEL2) << BIT_SHIFT_MUXDBG_SEL2) +#define BITS_MUXDBG_SEL2 (BIT_MASK_MUXDBG_SEL2 << BIT_SHIFT_MUXDBG_SEL2) +#define BIT_CLEAR_MUXDBG_SEL2(x) ((x) & (~BITS_MUXDBG_SEL2)) +#define BIT_GET_MUXDBG_SEL2(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL2) & BIT_MASK_MUXDBG_SEL2) +#define BIT_SET_MUXDBG_SEL2(x, v) \ + (BIT_CLEAR_MUXDBG_SEL2(x) | BIT_MUXDBG_SEL2(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_GPIO_INTM (Offset 0x0048) */ -/* 2 REG_LED_CFG (Offset 0x004C) */ - -#define BIT_PAD_D_PAPE_5G_I BIT(28) +#define BIT_GPIO_EXT_EN BIT(20) #endif - #if (HALMAC_8192E_SUPPORT) +/* 2 REG_GPIO_INTM (Offset 0x0048) */ -/* 2 REG_LED_CFG (Offset 0x004C) */ - -#define BIT_TRSW_SEL_EN BIT(27) +#define BIT_EXTWOL1_SEL BIT(19) +#define BIT_EXTWOL1_EN BIT(18) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#define BIT_EXTWOL0_SEL BIT(17) -/* 2 REG_LED_CFG (Offset 0x004C) */ +#endif -#define BIT_PAD_D_TRSW_I BIT(27) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#define BIT_BT_EXTWOL_DIS BIT(17) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_LED_CFG (Offset 0x004C) */ +/* 2 REG_GPIO_INTM (Offset 0x0048) */ -#define BIT_GPIO3_WL_CTRL_EN BIT(27) +#define BIT_EXTWOL_SEL BIT(17) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#define BIT_EXTWOL0_EN BIT(16) -/* 2 REG_LED_CFG (Offset 0x004C) */ +#endif -#define BIT_PAPE1_SEL_EN BIT(26) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#define BIT_EXTWOL_EN BIT(16) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_LED_CFG (Offset 0x004C) */ +/* 2 REG_GPIO_INTM (Offset 0x0048) */ -#define BIT_LNAON_SEL_EN BIT(26) +#define BIT_SHIFT_GPIO_EXT_WOL_V1 16 +#define BIT_MASK_GPIO_EXT_WOL_V1 0xf +#define BIT_GPIO_EXT_WOL_V1(x) \ + (((x) & BIT_MASK_GPIO_EXT_WOL_V1) << BIT_SHIFT_GPIO_EXT_WOL_V1) +#define BITS_GPIO_EXT_WOL_V1 \ + (BIT_MASK_GPIO_EXT_WOL_V1 << BIT_SHIFT_GPIO_EXT_WOL_V1) +#define BIT_CLEAR_GPIO_EXT_WOL_V1(x) ((x) & (~BITS_GPIO_EXT_WOL_V1)) +#define BIT_GET_GPIO_EXT_WOL_V1(x) \ + (((x) >> BIT_SHIFT_GPIO_EXT_WOL_V1) & BIT_MASK_GPIO_EXT_WOL_V1) +#define BIT_SET_GPIO_EXT_WOL_V1(x, v) \ + (BIT_CLEAR_GPIO_EXT_WOL_V1(x) | BIT_GPIO_EXT_WOL_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_GPIO_INTM (Offset 0x0048) */ +#define BIT_GPIOF_INT_MD BIT(15) +#define BIT_GPIOE_INT_MD BIT(14) +#define BIT_GPIOD_INT_MD BIT(13) +#define BIT_GPIOC_INT_MD BIT(12) +#define BIT_GPIOB_INT_MD BIT(11) +#define BIT_GPIOA_INT_MD BIT(10) +#define BIT_GPIO9_INT_MD BIT(9) +#define BIT_GPIO8_INT_MD BIT(8) +#define BIT_GPIO7_INT_MD BIT(7) +#define BIT_GPIO6_INT_MD BIT(6) +#define BIT_GPIO5_INT_MD BIT(5) +#define BIT_GPIO4_INT_MD BIT(4) +#define BIT_GPIO3_INT_MD BIT(3) +#define BIT_GPIO2_INT_MD BIT(2) +#define BIT_GPIO1_INT_MD BIT(1) +#define BIT_GPIO0_INT_MD BIT(0) -/* 2 REG_LED_CFG (Offset 0x004C) */ +#endif -#define BIT_PAD_D_TRSWB_I BIT(26) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_LED_CFG (Offset 0x004C) */ +#define BIT_MAILBOX_1WIRE_GPIO_CFG BIT(31) -#if (HALMAC_8192E_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_PAPE0_SEL_EN BIT(25) +#define BIT_PAD_ANTSEL_I BIT(31) #endif +#if (HALMAC_8192E_SUPPORT) + +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_ANT_SEL7_EN BIT(30) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_PAPE_SEL_EN BIT(25) +#define BIT_BT_RF_GPIO_CFG BIT(30) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_DWH_EN BIT(25) +#define BIT_PAD_ANTSELB_I BIT(30) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_ANTSEL2_EN BIT(24) +#define BIT_ANT_SEL46_EN BIT(29) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_DPDT_WLBT_SEL BIT(24) +#define BIT_BT_SDIO_INT_GPIO_CFG BIT(29) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_DHW_EN BIT(24) +#define BIT_PAD_D_PAPE_2G_I BIT(29) #endif +#if (HALMAC_8192E_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_LED_CFG (Offset 0x004C) */ +#define BIT_ANT_SEL3_EN BIT(28) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_RFE_ANT_EXT_SEL BIT(24) +#define BIT_MAILBOX_3WIRE_GPIO_CFG BIT(28) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_PAD_D_PAPE_5G_I BIT(28) -#if (HALMAC_8192E_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_ANTSEL_EN BIT(23) +#define BIT_TRSW_SEL_EN BIT(27) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_WLBT_PAPE_SEL_EN BIT(27) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_DPDT_SEL_EN BIT(23) +#define BIT_PAD_D_TRSW_I BIT(27) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_GPIO3_WL_CTRL_EN BIT(27) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_GPIO13_14_WL_CTRL_EN BIT(22) +#define BIT_PAPE1_SEL_EN BIT(26) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_LNAON_SEL_EN BIT(26) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LED2DIS_V1 BIT(22) +#define BIT_PAD_D_TRSWB_I BIT(26) #endif +#if (HALMAC_8192E_SUPPORT) + +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_PAPE0_SEL_EN BIT(25) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_TRXIQ_DBG_EN BIT(22) +#define BIT_PAPE_SEL_EN BIT(25) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_DWH_EN BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LED2DIS BIT(21) +#define BIT_ANTSEL2_EN BIT(24) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_ANT01_EN BIT(24) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LED2EN BIT(21) +#define BIT_DPDT_WLBT_SEL BIT(24) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_DHW_EN BIT(24) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8881A_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LED2PL BIT(20) -#define BIT_LED2SV BIT(19) +#define BIT_RFE_ANT_EXT_SEL BIT(24) -#define BIT_SHIFT_LED2CM 16 -#define BIT_MASK_LED2CM 0x7 -#define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM) -#define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM) +#endif -#define BIT_LED1DIS BIT(15) -#define BIT_LED1PL BIT(12) -#define BIT_LED1SV BIT(11) +#if (HALMAC_8192E_SUPPORT) -#define BIT_SHIFT_LED1CM 8 -#define BIT_MASK_LED1CM 0x7 -#define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM) -#define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM) +/* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LED0DIS BIT(7) +#define BIT_ANTSEL_EN BIT(23) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_LED_CFG (Offset 0x004C) */ +#define BIT_DPDT_SEL_EN BIT(23) -/* 2 REG_LED_CFG (Offset 0x004C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AFE_LDO_SWR_CHECK 5 -#define BIT_MASK_AFE_LDO_SWR_CHECK 0x3 -#define BIT_AFE_LDO_SWR_CHECK(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK) -#define BIT_GET_AFE_LDO_SWR_CHECK(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK) +/* 2 REG_LED_CFG (Offset 0x004C) */ +#define BIT_GPIO13_14_WL_CTRL_EN BIT(22) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_LED_CFG (Offset 0x004C) */ + +#define BIT_SW_SPDT_SEL BIT(22) + +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_LED0PL BIT(4) -#define BIT_LED0SV BIT(3) +#define BIT_LED2DIS_V1 BIT(22) -#define BIT_SHIFT_LED0CM 0 -#define BIT_MASK_LED0CM 0x7 -#define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM) -#define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM) +#endif +#if (HALMAC_8881A_SUPPORT) -/* 2 REG_FSIMR (Offset 0x0050) */ +/* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_FS_PDNINT_EN BIT(31) +#define BIT_TRXIQ_DBG_EN BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LED_CFG (Offset 0x004C) */ +#define BIT_LED2DIS BIT(21) -/* 2 REG_FSIMR (Offset 0x0050) */ +#endif -#define BIT_NFC_INT_PAD_EN BIT(30) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_LED_CFG (Offset 0x004C) */ +#define BIT_LED0_GPIO_EN BIT(21) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -/* 2 REG_FSIMR (Offset 0x0050) */ +/* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_FS_SPS_OCP_INT_EN BIT(29) +#define BIT_LED2EN BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_LED_CFG (Offset 0x004C) */ +#define BIT_LED2PL BIT(20) +#define BIT_LED2SV BIT(19) -/* 2 REG_FSIMR (Offset 0x0050) */ +#define BIT_SHIFT_LED2CM 16 +#define BIT_MASK_LED2CM 0x7 +#define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM) +#define BITS_LED2CM (BIT_MASK_LED2CM << BIT_SHIFT_LED2CM) +#define BIT_CLEAR_LED2CM(x) ((x) & (~BITS_LED2CM)) +#define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM) +#define BIT_SET_LED2CM(x, v) (BIT_CLEAR_LED2CM(x) | BIT_LED2CM(v)) -#define BIT_SW_SPS_OCP_INT_EN BIT(29) +#define BIT_LED1DIS BIT(15) +#define BIT_LED1PL BIT(12) +#define BIT_LED1SV BIT(11) -#endif +#define BIT_SHIFT_LED1CM 8 +#define BIT_MASK_LED1CM 0x7 +#define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM) +#define BITS_LED1CM (BIT_MASK_LED1CM << BIT_SHIFT_LED1CM) +#define BIT_CLEAR_LED1CM(x) ((x) & (~BITS_LED1CM)) +#define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM) +#define BIT_SET_LED1CM(x, v) (BIT_CLEAR_LED1CM(x) | BIT_LED1CM(v)) +#define BIT_LED0DIS BIT(7) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_FSIMR (Offset 0x0050) */ +/* 2 REG_LED_CFG (Offset 0x004C) */ -#define BIT_FS_PWMERR_INT_EN BIT(28) +#define BIT_SHIFT_AFE_LDO_SWR_CHECK 5 +#define BIT_MASK_AFE_LDO_SWR_CHECK 0x3 +#define BIT_AFE_LDO_SWR_CHECK(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK) +#define BITS_AFE_LDO_SWR_CHECK \ + (BIT_MASK_AFE_LDO_SWR_CHECK << BIT_SHIFT_AFE_LDO_SWR_CHECK) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK(x) ((x) & (~BITS_AFE_LDO_SWR_CHECK)) +#define BIT_GET_AFE_LDO_SWR_CHECK(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK) +#define BIT_SET_AFE_LDO_SWR_CHECK(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK(x) | BIT_AFE_LDO_SWR_CHECK(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_LED_CFG (Offset 0x004C) */ +#define BIT_LED0PL BIT(4) +#define BIT_LED0SV BIT(3) + +#define BIT_SHIFT_LED0CM 0 +#define BIT_MASK_LED0CM 0x7 +#define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM) +#define BITS_LED0CM (BIT_MASK_LED0CM << BIT_SHIFT_LED0CM) +#define BIT_CLEAR_LED0CM(x) ((x) & (~BITS_LED0CM)) +#define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM) +#define BIT_SET_LED0CM(x, v) (BIT_CLEAR_LED0CM(x) | BIT_LED0CM(v)) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_PWM_HW_ERR_EN BIT(28) +#define BIT_FS_PDNINT_EN BIT(31) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +/* 2 REG_FSIMR (Offset 0x0050) */ + +#define BIT_NFC_INT_PAD_EN BIT(30) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOF_INT_EN BIT(27) -#define BIT_FS_GPIOE_INT_EN BIT(26) -#define BIT_FS_GPIOD_INT_EN BIT(25) -#define BIT_FS_GPIOC_INT_EN BIT(24) +#define BIT_FS_SPS_OCP_INT_EN BIT(29) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_ACT2RECOVERY_INT_EN BIT(24) +#define BIT_SW_SPS_OCP_INT_EN BIT(29) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOB_INT_EN BIT(23) +#define BIT_FS_PWMERR_INT_EN BIT(28) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_PCIE_GEN12_SWITH_EN BIT(23) +#define BIT_FS_PWM_HW_ERR_EN BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOA_INT_EN BIT(22) +#define BIT_FS_GPIOF_INT_EN BIT(27) +#define BIT_FS_GPIOE_INT_EN BIT(26) +#define BIT_FS_GPIOD_INT_EN BIT(25) +#define BIT_FS_GPIOC_INT_EN BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_SUS_EN_V1 BIT(22) +#define BIT_ACT2RECOVERY_INT_EN BIT(24) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO9_INT_EN BIT(21) +#define BIT_FS_GPIOB_INT_EN BIT(23) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_RES_EN_V1 BIT(21) +#define BIT_PCIE_GEN12_SWITCH_EN BIT(23) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO8_INT_EN BIT(20) +#define BIT_FS_GPIOA_INT_EN BIT(22) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_RESET_EN_V1 BIT(20) +#define BIT_FS_HCI_SUS_EN_V1 BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO7_INT_EN BIT(19) +#define BIT_FS_GPIO9_INT_EN BIT(21) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_32K_LEAVE_SETTING_EN BIT(19) +#define BIT_FS_HCI_RES_EN_V1 BIT(21) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO6_INT_EN BIT(18) +#define BIT_FS_GPIO8_INT_EN BIT(20) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_32K_ENTER_SETTING_EN BIT(18) +#define BIT_FS_HCI_RESET_EN_V1 BIT(20) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO5_INT_EN BIT(17) +#define BIT_FS_GPIO7_INT_EN BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_SIE_LPM_RSM_EN_V1 BIT(17) +#define BIT_FS_32K_LEAVE_SETTING_EN BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO4_INT_EN BIT(16) +#define BIT_FS_GPIO6_INT_EN BIT(18) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_SIE_LPM_ACT_EN_V1 BIT(16) +#define BIT_FS_32K_ENTER_SETTING_EN BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO3_INT_EN BIT(15) +#define BIT_FS_GPIO5_INT_EN BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOF_INT_EN_V1 BIT(15) +#define BIT_FS_SIE_LPM_RSM_EN_V1 BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO2_INT_EN BIT(14) +#define BIT_FS_GPIO4_INT_EN BIT(16) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOE_INT_EN_V1 BIT(14) +#define BIT_FS_SIE_LPM_ACT_EN_V1 BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO1_INT_EN BIT(13) +#define BIT_FS_GPIO3_INT_EN BIT(15) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOD_INT_EN_V1 BIT(13) +#define BIT_FS_GPIOF_INT_EN_V1 BIT(15) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO0_INT_EN BIT(12) +#define BIT_FS_GPIO2_INT_EN BIT(14) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOC_INT_EN_V1 BIT(12) +#define BIT_FS_GPIOE_INT_EN_V1 BIT(14) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_SUS_EN BIT(11) +#define BIT_FS_GPIO1_INT_EN BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOB_INT_EN_V1 BIT(11) +#define BIT_FS_GPIOD_INT_EN_V1 BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_RES_EN BIT(10) +#define BIT_FS_GPIO0_INT_EN BIT(12) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIOA_INT_EN_V1 BIT(10) +#define BIT_FS_GPIOC_INT_EN_V1 BIT(12) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_HCI_RESET_EN BIT(9) +#define BIT_FS_HCI_SUS_EN BIT(11) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO9_INT_EN_V1 BIT(9) +#define BIT_FS_GPIOB_INT_EN_V1 BIT(11) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_AXI_EXCEPT_FINT_EN BIT(8) +#define BIT_FS_HCI_RES_EN BIT(10) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO8_INT_EN_V1 BIT(8) +#define BIT_FS_GPIOA_INT_EN_V1 BIT(10) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_USB_SCSI_CMD_EN BIT(8) +#define BIT_FS_HCI_RESET_EN BIT(9) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7) +#define BIT_FS_GPIO9_INT_EN_V1 BIT(9) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO7_INT_EN_V1 BIT(7) +#define BIT_AXI_EXCEPT_FINT_EN BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6) +#define BIT_USB_SCSI_CMD_EN BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO6_INT_EN_V1 BIT(6) +#define BIT_FS_GPIO8_INT_EN_V1 BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_TRPC_TO_INT_EN BIT(5) +#define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO5_INT_EN_V1 BIT(5) +#define BIT_FS_GPIO7_INT_EN_V1 BIT(7) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_GEN1GEN2_SWITCH BIT(5) +#define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_FSIMR (Offset 0x0050) */ + +#define BIT_FS_GPIO6_INT_EN_V1 BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_RPC_O_T_INT_EN BIT(4) +#define BIT_FS_TRPC_TO_INT_EN BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO4_INT_EN_V1 BIT(4) +#define BIT_FS_GPIO5_INT_EN_V1 BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FSIMR (Offset 0x0050) */ +#define BIT_FS_RPC_O_T_INT_EN BIT(4) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_HCI_TXDMA_REQ_HIMR BIT(4) +#define BIT_HCI_TXDMA_REQ_HIMR BIT(4) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_FSIMR (Offset 0x0050) */ + +#define BIT_FS_GPIO4_INT_EN_V1 BIT(4) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3) +#define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO3_INT_EN_V1 BIT(3) +#define BIT_FS_GPIO3_INT_EN_V1 BIT(3) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_32K_ENTER_SETTING_MAK BIT(2) +#define BIT_FS_32K_ENTER_SETTING_MAK BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO2_INT_EN_V1 BIT(2) +#define BIT_FS_GPIO2_INT_EN_V1 BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_USB_LPMRSM_MSK BIT(1) +#define BIT_FS_USB_LPMRSM_MSK BIT(1) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO1_INT_EN_V1 BIT(1) +#define BIT_FS_GPIO1_INT_EN_V1 BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_USB_LPMINT_MSK BIT(0) +#define BIT_FS_USB_LPMINT_MSK BIT(0) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSIMR (Offset 0x0050) */ -#define BIT_FS_GPIO0_INT_EN_V1 BIT(0) +#define BIT_FS_GPIO0_INT_EN_V1 BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_PDNINT BIT(31) +#define BIT_FS_PDNINT BIT(31) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_SPS_OCP_INT BIT(29) +#define BIT_FS_SPS_OCP_INT BIT(29) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_SW_SPS_OCP_INT BIT(29) +#define BIT_SW_SPS_OCP_INT BIT(29) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_PWMERR_INT BIT(28) +#define BIT_FS_PWMERR_INT BIT(28) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_PWM_HW_ERR BIT(28) +#define BIT_FS_PWM_HW_ERR BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOF_INT BIT(27) -#define BIT_FS_GPIOE_INT BIT(26) -#define BIT_FS_GPIOD_INT BIT(25) -#define BIT_FS_GPIOC_INT BIT(24) +#define BIT_FS_GPIOF_INT BIT(27) +#define BIT_FS_GPIOE_INT BIT(26) +#define BIT_FS_GPIOD_INT BIT(25) +#define BIT_FS_GPIOC_INT BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_ACT2RECOVERY_INT BIT(24) +#define BIT_ACT2RECOVERY_INT BIT(24) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOB_INT BIT(23) +#define BIT_FS_GPIOB_INT BIT(23) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_PCIE_GEN12_SWITH BIT(23) +#define BIT_PCIE_GEN12_SWITCH BIT(23) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOA_INT BIT(22) +#define BIT_FS_GPIOA_INT BIT(22) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_SUS_V1 BIT(22) +#define BIT_FS_HCI_SUS_V1 BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO9_INT BIT(21) +#define BIT_FS_GPIO9_INT BIT(21) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_RES_V1 BIT(21) +#define BIT_FS_HCI_RES_V1 BIT(21) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO8_INT BIT(20) +#define BIT_FS_GPIO8_INT BIT(20) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_RESET_V1 BIT(20) +#define BIT_FS_HCI_RESET_V1 BIT(20) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO7_INT BIT(19) +#define BIT_FS_GPIO7_INT BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_32K_LEAVE_SETTING BIT(19) +#define BIT_FS_32K_LEAVE_SETTING BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO6_INT BIT(18) +#define BIT_FS_GPIO6_INT BIT(18) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_32K_ENTER_SETTING BIT(18) +#define BIT_FS_32K_ENTER_SETTING BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO5_INT BIT(17) +#define BIT_FS_GPIO5_INT BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_SIE_LPM_RSM_V1 BIT(17) +#define BIT_FS_SIE_LPM_RSM_V1 BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO4_INT BIT(16) +#define BIT_FS_GPIO4_INT BIT(16) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_SIE_LPM_ACT_V1 BIT(16) +#define BIT_FS_SIE_LPM_ACT_V1 BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO3_INT BIT(15) +#define BIT_FS_GPIO3_INT BIT(15) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOF_INT_V1 BIT(15) +#define BIT_FS_GPIOF_INT_V1 BIT(15) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO2_INT BIT(14) +#define BIT_FS_GPIO2_INT BIT(14) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOE_INT_V1 BIT(14) +#define BIT_FS_GPIOE_INT_V1 BIT(14) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO1_INT BIT(13) +#define BIT_FS_GPIO1_INT BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOD_INT_V1 BIT(13) +#define BIT_FS_GPIOD_INT_V1 BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO0_INT BIT(12) +#define BIT_FS_GPIO0_INT BIT(12) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOC_INT_V1 BIT(12) +#define BIT_FS_GPIOC_INT_V1 BIT(12) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_SUS_INT BIT(11) +#define BIT_FS_HCI_SUS_INT BIT(11) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIOB_INT_V1 BIT(11) +#define BIT_FS_GPIOB_INT_V1 BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_RES_INT BIT(10) +#define BIT_FS_HCI_RES_INT BIT(10) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -/* 2 REG_FSISR (Offset 0x0054) */ - -#define BIT_FS_GPIOA_INT_V1 BIT(10) - -#endif - - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_HCI_RESET_INT BIT(9) +#define BIT_FS_GPIOA_INT_V1 BIT(10) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_R_8051_SPD BIT(9) +#define BIT_FS_HCI_RESET_INT BIT(9) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -/* 2 REG_FSISR (Offset 0x0054) */ - -#define BIT_FS_GPIO9_INT_V1 BIT(9) - -#endif - - -#if (HALMAC_8197F_SUPPORT) - - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_AXI_EXCEPT_FINT BIT(8) +#define BIT_FS_GPIO9_INT_V1 BIT(9) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO8_INT_V1 BIT(8) +#define BIT_AXI_EXCEPT_FINT BIT(8) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_USB_SCSI_CMD_INT BIT(8) +#define BIT_USB_SCSI_CMD_INT BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_RAM_DL_SEL BIT(7) +#define BIT_FS_GPIO8_INT_V1 BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_BTON_STS_UPDATE_INT BIT(7) +#define BIT_FS_BTON_STS_UPDATE_INT BIT(7) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO7_INT_V1 BIT(7) +#define BIT_FS_GPIO7_INT_V1 BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_WINTINI_RDY BIT(6) +#define BIT_ACT2RECOVERY_INT_V1 BIT(6) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_ACT2RECOVERY_INT_V1 BIT(6) +#define BIT_ACT2RECOVERY BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -/* 2 REG_FSISR (Offset 0x0054) */ - -#define BIT_FS_GPIO6_INT_V1 BIT(6) - -#endif - - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_ACT2RECOVERY BIT(6) +#define BIT_FS_GPIO6_INT_V1 BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_TRPC_TO_INT_INT BIT(5) +#define BIT_FS_TRPC_TO_INT_INT BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO5_INT_V1 BIT(5) +#define BIT_FS_GPIO5_INT_V1 BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_RPC_O_T_INT_INT BIT(4) +#define BIT_FS_RPC_O_T_INT_INT BIT(4) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO4_INT_V1 BIT(4) +#define BIT_HCI_TXDMA_REQ_HISR BIT(4) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_HCI_TXDMA_REQ_HISR BIT(4) +#define BIT_FS_GPIO4_INT_V1 BIT(4) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_32K_LEAVE_SETTING_INT BIT(3) +#define BIT_FS_32K_LEAVE_SETTING_INT BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO3_INT_V1 BIT(3) +#define BIT_FS_GPIO3_INT_V1 BIT(3) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_32K_ENTER_SETTING_INT BIT(2) +#define BIT_FS_32K_ENTER_SETTING_INT BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO2_INT_V1 BIT(2) +#define BIT_FS_GPIO2_INT_V1 BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_USB_LPMRSM_INT BIT(1) +#define BIT_FS_USB_LPMRSM_INT BIT(1) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO1_INT_V1 BIT(1) +#define BIT_FS_GPIO1_INT_V1 BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_USB_LPMINT_INT BIT(0) +#define BIT_FS_USB_LPMINT_INT BIT(0) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_FSISR (Offset 0x0054) */ -#define BIT_FS_GPIO0_INT_V1 BIT(0) +#define BIT_FS_GPIO0_INT_V1 BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIOF_INT_EN BIT(31) -#define BIT_GPIOE_INT_EN BIT(30) -#define BIT_GPIOD_INT_EN BIT(29) -#define BIT_GPIOC_INT_EN BIT(28) -#define BIT_GPIOB_INT_EN BIT(27) -#define BIT_GPIOA_INT_EN BIT(26) -#define BIT_GPIO9_INT_EN BIT(25) -#define BIT_GPIO8_INT_EN BIT(24) -#define BIT_GPIO7_INT_EN BIT(23) -#define BIT_GPIO6_INT_EN BIT(22) -#define BIT_GPIO5_INT_EN BIT(21) -#define BIT_GPIO4_INT_EN BIT(20) -#define BIT_GPIO3_INT_EN BIT(19) +#define BIT_GPIOF_INT_EN BIT(31) +#define BIT_GPIOE_INT_EN BIT(30) +#define BIT_GPIOD_INT_EN BIT(29) +#define BIT_GPIOC_INT_EN BIT(28) +#define BIT_GPIOB_INT_EN BIT(27) +#define BIT_GPIOA_INT_EN BIT(26) +#define BIT_GPIO9_INT_EN BIT(25) +#define BIT_GPIO8_INT_EN BIT(24) +#define BIT_GPIO7_INT_EN BIT(23) +#define BIT_GPIO6_INT_EN BIT(22) +#define BIT_GPIO5_INT_EN BIT(21) +#define BIT_GPIO4_INT_EN BIT(20) +#define BIT_GPIO3_INT_EN BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIO2_INT_EN BIT(18) +#define BIT_GPIO2_INT_EN BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIO1_INT_EN BIT(17) -#define BIT_GPIO0_INT_EN BIT(16) +#define BIT_GPIO2_INT_EN_V1 BIT(18) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIO2_INT_EN_V1 BIT(16) +#define BIT_GPIO1_INT_EN BIT(17) +#define BIT_GPIO0_INT_EN BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_AXI_EXCEPT_HINT_EN BIT(9) -#define BIT_PDNINT_EN_V2 BIT(8) +#define BIT_AXI_EXCEPT_HINT_EN BIT(9) +#define BIT_PDNINT_EN_V2 BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_PDNINT_EN BIT(7) +#define BIT_PDNINT_EN BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_PDNINT_EN_V1 BIT(7) +#define BIT_PDNINT_EN_V1 BIT(7) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_PDN_INT_EN BIT(7) +#define BIT_PDN_INT_EN BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_RON_INT_EN BIT(6) +#define BIT_RON_INT_EN BIT(6) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_RON_INT_EN_V1 BIT(6) +#define BIT_RON_INT_EN_V1 BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_SPS_OCP_INT_EN BIT(5) +#define BIT_SPS_OCP_INT_EN BIT(5) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_SPS_OCP_INT_EN_V1 BIT(5) +#define BIT_SPS_OCP_INT_EN_V1 BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIO15_0_INT_EN BIT(0) +#define BIT_GPIO15_0_INT_EN BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSIMR (Offset 0x0058) */ -#define BIT_GPIO15_0_INT_EN_V1 BIT(0) +#define BIT_GPIO15_0_INT_EN_V1 BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_GPIOF_INT BIT(31) -#define BIT_GPIOE_INT BIT(30) -#define BIT_GPIOD_INT BIT(29) -#define BIT_GPIOC_INT BIT(28) -#define BIT_GPIOB_INT BIT(27) -#define BIT_GPIOA_INT BIT(26) -#define BIT_GPIO9_INT BIT(25) -#define BIT_GPIO8_INT BIT(24) -#define BIT_GPIO7_INT BIT(23) +#define BIT_GPIOF_INT BIT(31) +#define BIT_GPIOE_INT BIT(30) +#define BIT_GPIOD_INT BIT(29) +#define BIT_GPIOC_INT BIT(28) +#define BIT_GPIOB_INT BIT(27) +#define BIT_GPIOA_INT BIT(26) +#define BIT_GPIO9_INT BIT(25) +#define BIT_GPIO8_INT BIT(24) +#define BIT_GPIO7_INT BIT(23) +#define BIT_GPIO6_INT BIT(22) +#define BIT_GPIO5_INT BIT(21) +#define BIT_GPIO4_INT BIT(20) +#define BIT_GPIO3_INT BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_CPRST BIT(23) +#define BIT_GPIO2_INT BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_GPIO6_INT BIT(22) -#define BIT_GPIO5_INT BIT(21) -#define BIT_GPIO4_INT BIT(20) -#define BIT_GPIO3_INT BIT(19) +#define BIT_GPIO2_INT_V1 BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_GPIO2_INT BIT(18) +#define BIT_GPIO1_INT BIT(17) +#define BIT_GPIO0_INT BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_GPIO1_INT BIT(17) -#define BIT_GPIO0_INT BIT(16) +#define BIT_AXI_EXCEPT_HINT BIT(8) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_GPIO2_INT_V1 BIT(16) +#define BIT_PDNINT BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ - -#define BIT_SHIFT_NPQ_AVAL_PG 8 -#define BIT_MASK_NPQ_AVAL_PG 0xff -#define BIT_NPQ_AVAL_PG(x) (((x) & BIT_MASK_NPQ_AVAL_PG) << BIT_SHIFT_NPQ_AVAL_PG) -#define BIT_GET_NPQ_AVAL_PG(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG) & BIT_MASK_NPQ_AVAL_PG) - +#define BIT_PDNINT_V1 BIT(7) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_AXI_EXCEPT_HINT BIT(8) +#define BIT_PDN_INT BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_PDNINT BIT(7) +#define BIT_RON_INT BIT(6) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_PDNINT_V1 BIT(7) +#define BIT_RON_INT_V1 BIT(6) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_PDN_INT BIT(7) +#define BIT_SPS_OCP_INT BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_RON_INT BIT(6) +#define BIT_SPS_OCP_INT_V1 BIT(5) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_RON_INT_V1 BIT(6) +#define BIT_GPIO15_0_INT BIT(0) +#define BIT_MCUFWDL_EN BIT(0) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HSISR (Offset 0x005C) */ -#define BIT_SPS_OCP_INT BIT(5) +#define BIT_GPIO15_0_INT_V1 BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_HSISR (Offset 0x005C) */ +/* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */ -#define BIT_SPS_OCP_INT_V1 BIT(5) +#define BIT_SHIFT_GPIO_MOD_15_TO_8 24 +#define BIT_MASK_GPIO_MOD_15_TO_8 0xff +#define BIT_GPIO_MOD_15_TO_8(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8) +#define BITS_GPIO_MOD_15_TO_8 \ + (BIT_MASK_GPIO_MOD_15_TO_8 << BIT_SHIFT_GPIO_MOD_15_TO_8) +#define BIT_CLEAR_GPIO_MOD_15_TO_8(x) ((x) & (~BITS_GPIO_MOD_15_TO_8)) +#define BIT_GET_GPIO_MOD_15_TO_8(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8) +#define BIT_SET_GPIO_MOD_15_TO_8(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8(x) | BIT_GPIO_MOD_15_TO_8(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */ +#define BIT_ROM_DLEN BIT(19) + +#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16 +#define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff +#define BIT_GPIO_IO_SEL_15_TO_8(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8) +#define BITS_GPIO_IO_SEL_15_TO_8 \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) ((x) & (~BITS_GPIO_IO_SEL_15_TO_8)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8) +#define BIT_SET_GPIO_IO_SEL_15_TO_8(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) | BIT_GPIO_IO_SEL_15_TO_8(v)) + +#define BIT_SHIFT_ROM_PGE 16 +#define BIT_MASK_ROM_PGE 0x7 +#define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE) +#define BITS_ROM_PGE (BIT_MASK_ROM_PGE << BIT_SHIFT_ROM_PGE) +#define BIT_CLEAR_ROM_PGE(x) ((x) & (~BITS_ROM_PGE)) +#define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE) +#define BIT_SET_ROM_PGE(x, v) (BIT_CLEAR_ROM_PGE(x) | BIT_ROM_PGE(v)) + +#define BIT_SHIFT_GPIO_OUT_15_TO_8 8 +#define BIT_MASK_GPIO_OUT_15_TO_8 0xff +#define BIT_GPIO_OUT_15_TO_8(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8) +#define BITS_GPIO_OUT_15_TO_8 \ + (BIT_MASK_GPIO_OUT_15_TO_8 << BIT_SHIFT_GPIO_OUT_15_TO_8) +#define BIT_CLEAR_GPIO_OUT_15_TO_8(x) ((x) & (~BITS_GPIO_OUT_15_TO_8)) +#define BIT_GET_GPIO_OUT_15_TO_8(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8) +#define BIT_SET_GPIO_OUT_15_TO_8(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8(x) | BIT_GPIO_OUT_15_TO_8(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_HSISR (Offset 0x005C) */ +/* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */ -#define BIT_GPIO15_0_INT BIT(0) -#define BIT_MCUFWDL_EN BIT(0) +#define BIT_SHIFT_GPIO_IN_15_TO_8 0 +#define BIT_MASK_GPIO_IN_15_TO_8 0xff +#define BIT_GPIO_IN_15_TO_8(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8) +#define BITS_GPIO_IN_15_TO_8 \ + (BIT_MASK_GPIO_IN_15_TO_8 << BIT_SHIFT_GPIO_IN_15_TO_8) +#define BIT_CLEAR_GPIO_IN_15_TO_8(x) ((x) & (~BITS_GPIO_IN_15_TO_8)) +#define BIT_GET_GPIO_IN_15_TO_8(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8) +#define BIT_SET_GPIO_IN_15_TO_8(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8(x) | BIT_GPIO_IN_15_TO_8(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_HSISR (Offset 0x005C) */ +/* 2 REG_SDIO_H2C (Offset 0x10250060) */ -#define BIT_GPIO15_0_INT_V1 BIT(0) +#define BIT_SHIFT_SDIO_H2C_MSG 0 +#define BIT_MASK_SDIO_H2C_MSG 0xffffffffL +#define BIT_SDIO_H2C_MSG(x) \ + (((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG) +#define BITS_SDIO_H2C_MSG (BIT_MASK_SDIO_H2C_MSG << BIT_SHIFT_SDIO_H2C_MSG) +#define BIT_CLEAR_SDIO_H2C_MSG(x) ((x) & (~BITS_SDIO_H2C_MSG)) +#define BIT_GET_SDIO_H2C_MSG(x) \ + (((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG) +#define BIT_SET_SDIO_H2C_MSG(x, v) \ + (BIT_CLEAR_SDIO_H2C_MSG(x) | BIT_SDIO_H2C_MSG(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */ +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_DATA_CPU_JTAG BIT(30) -#define BIT_SHIFT_GPIO_MOD_15_TO_8 24 -#define BIT_MASK_GPIO_MOD_15_TO_8 0xff -#define BIT_GPIO_MOD_15_TO_8(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8) -#define BIT_GET_GPIO_MOD_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16 -#define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff -#define BIT_GPIO_IO_SEL_15_TO_8(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8) -#define BIT_GET_GPIO_IO_SEL_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_PAPE_WLBT_SEL BIT(29) +#define BIT_LNAON_WLBT_SEL BIT(28) -#define BIT_SHIFT_GPIO_OUT_15_TO_8 8 -#define BIT_MASK_GPIO_OUT_15_TO_8 0xff -#define BIT_GPIO_OUT_15_TO_8(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8) -#define BIT_GET_GPIO_OUT_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_GPIO_IN_15_TO_8 0 -#define BIT_MASK_GPIO_IN_15_TO_8 0xff -#define BIT_GPIO_IN_15_TO_8(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8) -#define BIT_GET_GPIO_IN_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_BDEN BIT(28) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_BT_BQB_GPIO_SEL BIT(27) -/* 2 REG_SDIO_H2C (Offset 0x10250060) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SDIO_H2C_MSG 0 -#define BIT_MASK_SDIO_H2C_MSG 0xffffffffL -#define BIT_SDIO_H2C_MSG(x) (((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG) -#define BIT_GET_SDIO_H2C_MSG(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_BTGP_GPG3_FEN BIT(26) +#define BIT_BTGP_GPG2_FEN BIT(25) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAPE_WLBT_SEL BIT(29) -#define BIT_LNAON_WLBT_SEL BIT(28) +#define BIT_BTGP_JTAG_EN BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BDEN BIT(28) +#define BIT_BB2PP_ISO BIT(24) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_GPG3_FEN BIT(26) -#define BIT_BTGP_GPG2_FEN BIT(25) +#define BIT_XTAL_CLK_EXTARNAL_EN BIT(23) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_JTAG_EN BIT(24) +#define BIT_BTBRI_UART_EN BIT(22) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BB2PP_ISO BIT(24) +#define BIT_BTGP_UART0_EN BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_XTAL_CLK_EXTARNAL_EN BIT(23) +#define BIT_BTGP_UART1_EN BIT(21) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTBRI_UART_EN BIT(22) +#define BIT_BTCOEX_PU BIT(21) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_BTGP_SPI_EN BIT(20) -/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#endif -#define BIT_BTGP_UART0_EN BIT(22) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_EEPROM_SEL_PD BIT(20) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_UART1_EN BIT(21) +#define BIT_BTGP_GPIO_E2 BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTCOEX_PU BIT(21) +#define BIT_TST_MOD_PD BIT(19) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_SPI_EN BIT(20) +#define BIT_BTGP_GPIO_EN BIT(18) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_EEPROM_SEL_PD BIT(20) +#define BIT_BOOT_FLUSH_PD BIT(18) +#define BIT_USB_XTAL_SEL1_PD BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_GPIO_E2 BIT(19) +#define BIT_SHIFT_BTGP_GPIO_SL 16 +#define BIT_MASK_BTGP_GPIO_SL 0x3 +#define BIT_BTGP_GPIO_SL(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL) +#define BITS_BTGP_GPIO_SL (BIT_MASK_BTGP_GPIO_SL << BIT_SHIFT_BTGP_GPIO_SL) +#define BIT_CLEAR_BTGP_GPIO_SL(x) ((x) & (~BITS_BTGP_GPIO_SL)) +#define BIT_GET_BTGP_GPIO_SL(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL) +#define BIT_SET_BTGP_GPIO_SL(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL(x) | BIT_BTGP_GPIO_SL(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_TST_MOD_PD BIT(19) +#define BIT_USB_XTAL_SEL0_PD BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTGP_GPIO_EN BIT(18) +#define BIT_HST_WKE_DEV_SL BIT(15) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BOOT_FLUSH_PD BIT(18) -#define BIT_USB_XTAL_SEL1_PD BIT(17) +#define BIT_BTSUSB_PL BIT(15) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ - -#define BIT_SHIFT_BTGP_GPIO_SL 16 -#define BIT_MASK_BTGP_GPIO_SL 0x3 -#define BIT_BTGP_GPIO_SL(x) (((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL) -#define BIT_GET_BTGP_GPIO_SL(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL) - +#define BIT_WL_JTAG BIT(15) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_USB_XTAL_SEL0_PD BIT(16) +#define BIT_PAD_SDIO_SR BIT(14) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_HST_WKE_DEV_SL BIT(15) +#define BIT_GPIO14_OUTPUT_PL BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_BTSUSB_PL BIT(15) +#define BIT_SW_DEVWHOST_POLARITY BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_SDIO_SR BIT(14) +#define BIT_GPIO15_OUTPUT_PL BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_GPIO14_OUTPUT_PL BIT(13) +#define BIT_HOST_WAKE_PAD_PULL_EN BIT(12) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_DEVWHOST_POLARITY BIT(13) +#define BIT_HOST_WAKE_DEV_PLL_EN BIT(12) #endif - -#if (HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_GPIO15_OUTPUT_PL BIT(13) +#define BIT_HOST_WAKE_PAD_SL BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_HOST_WAKE_PAD_PULL_EN BIT(12) +#define BIT_SW_TRSW_3 BIT(11) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_HOST_WAKE_DEV_PLL_EN BIT(12) +#define BIT_HOST_WAKE_DEV_POLARITY BIT(11) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_HOST_WAKE_PAD_SL BIT(11) +#define BIT_PAD_TRSW_SR BIT(10) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_HOST_WAKE_DEV_POLARITY BIT(11) +#define BIT_PAD_LNAON_SR BIT(10) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_TRSW_SR BIT(10) +#define BIT_SW_TRSW_2 BIT(10) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_LNAON_SR BIT(10) +#define BIT_PAD_TRSW_E2 BIT(9) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_TRSW_E2 BIT(9) +#define BIT_PAD_LNAON_E2 BIT(9) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_LNAON_E2 BIT(9) +#define BIT_SW_TRSW_1 BIT(9) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_A_ANTSEL_SR BIT(9) +#define BIT_A_ANTSEL_SR BIT(9) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_TRSW_P_SEL_DATA BIT(8) +#define BIT_SW_TRSW_P_SEL_DATA BIT(8) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ + +#define BIT_SW_LNAON_G_SEL_DATA BIT(8) + +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_LNAON_G_SEL_DATA BIT(8) +#define BIT_SW_TRSW_0 BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_A_ANTSEL_E2 BIT(8) +#define BIT_A_ANTSEL_E2 BIT(8) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_TRSW_N_SEL_DATA BIT(7) +#define BIT_SW_TRSW_N_SEL_DATA BIT(7) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ + +#define BIT_SW_LNAON_A_SEL_DATA BIT(7) + +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_LNAON_A_SEL_DATA BIT(7) +#define BIT_SW_PAPE_3 BIT(7) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_PAPE_2G_SR BIT(7) +#define BIT_D_PAPE_2G_SR BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ + +#define BIT_PAD_PAPE_SR BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_PAPE_SR BIT(6) +#define BIT_SW_PAPE_2 BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_PAPE_5G_SR BIT(6) +#define BIT_D_PAPE_5G_SR BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ + +#define BIT_PAD_PAPE_E2 BIT(5) + +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_PAPE_E2 BIT(5) +#define BIT_SW_PAPE_1 BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_TRSW_SR BIT(5) +#define BIT_D_TRSW_SR BIT(5) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_PAPE_1_SEL_DATA BIT(4) +#define BIT_SW_PAPE_1_SEL_DATA BIT(4) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ + +#define BIT_SW_PAPE_G_SEL_DATA BIT(4) + +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_PAPE_G_SEL_DATA BIT(4) +#define BIT_SW_PAPE_0 BIT(4) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_TRSWB_SR BIT(4) +#define BIT_D_TRSWB_SR BIT(4) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_PAPE_0_SEL_DATA BIT(3) +#define BIT_SW_PAPE_0_SEL_DATA BIT(3) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ + +#define BIT_SW_PAPE_A_SEL_DATA BIT(3) + +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_PAPE_A_SEL_DATA BIT(3) +#define BIT_SW_ANTSEL_3 BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_PAPE_2G_E2 BIT(3) +#define BIT_D_PAPE_2G_E2 BIT(3) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_ANTSEL_2_SEL_DATA BIT(2) +#define BIT_SW_ANTSEL_2_SEL_DATA BIT(2) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ + +#define BIT_PAD_DPDT_SR BIT(2) + +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_DPDT_SR BIT(2) +#define BIT_SW_ANTSEL_2 BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_PAPE_5G_E2 BIT(2) +#define BIT_D_PAPE_5G_E2 BIT(2) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_ANTSEL_N_SEL_DATA BIT(1) +#define BIT_SW_ANTSEL_N_SEL_DATA BIT(1) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ + +#define BIT_PAD_DPDT_PAD_E2 BIT(1) + +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_DPDT_PAD_E2 BIT(1) +#define BIT_SW_ANTSEL_1 BIT(1) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_TRSW_E2 BIT(1) +#define BIT_D_TRSW_E2 BIT(1) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_PAD_DPDT_E2 BIT(1) +#define BIT_PAD_DPDT_E2 BIT(1) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_ANTSEL_P_SEL_DATA BIT(0) +#define BIT_SW_ANTSEL_P_SEL_DATA BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_SW_DPDT_SEL_DATA BIT(0) +#define BIT_SW_DPDT_SEL_DATA BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ -#define BIT_D_TRSWB_E2 BIT(0) +#define BIT_SW_ANTSEL_0 BIT(0) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_C2H (Offset 0x10250064) */ +#define BIT_SHIFT_SDIO_C2H_MSG 0 +#define BIT_MASK_SDIO_C2H_MSG 0xffffffffL +#define BIT_SDIO_C2H_MSG(x) \ + (((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG) +#define BITS_SDIO_C2H_MSG (BIT_MASK_SDIO_C2H_MSG << BIT_SHIFT_SDIO_C2H_MSG) +#define BIT_CLEAR_SDIO_C2H_MSG(x) ((x) & (~BITS_SDIO_C2H_MSG)) +#define BIT_GET_SDIO_C2H_MSG(x) \ + (((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG) +#define BIT_SET_SDIO_C2H_MSG(x, v) \ + (BIT_CLEAR_SDIO_C2H_MSG(x) | BIT_SDIO_C2H_MSG(v)) -#define BIT_SHIFT_SDIO_C2H_MSG 0 -#define BIT_MASK_SDIO_C2H_MSG 0xffffffffL -#define BIT_SDIO_C2H_MSG(x) (((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG) -#define BIT_GET_SDIO_C2H_MSG(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_PAD_CTRL1 (Offset 0x0064) */ +#define BIT_D_TRSWB_E2 BIT(0) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_ISO_BD2PP BIT(31) -#define BIT_LDOV12B_EN BIT(30) -#define BIT_CKEN_BTGPS BIT(29) -#define BIT_FEN_BTGPS BIT(28) +#define BIT_ISO_BD2PP BIT(31) +#define BIT_LDOV12B_EN BIT(30) +#define BIT_CKEN_BTGPS BIT(29) +#define BIT_FEN_BTGPS BIT(28) +#define BIT_BTCPU_BOOTSEL BIT(27) +#define BIT_SPI_SPEEDUP BIT(26) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ + +#define BIT_BT_LPS_EN BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_MULRW BIT(27) +#define BIT_BT_LDO_MODE BIT(25) #endif +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ + +#define BIT_BT_SUS BIT(25) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BTCPU_BOOTSEL BIT(27) -#define BIT_SPI_SPEEDUP BIT(26) +#define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ + +#define BIT_CLKREQ_PAD_PL BIT(23) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24) -#define BIT_CLKREQ_PAD_TYPE_SEL BIT(23) +#define BIT_CLKREQ_PAD_TYPE_SEL BIT(23) #endif - #if (HALMAC_8881A_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_CKSL_BZSLP BIT(23) +#define BIT_CKSL_BZSLP BIT(23) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_EN_CPL_TIMEOUT_PS BIT(22) +#define BIT_EN_CPL_TIMEOUT_PS BIT(22) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_WAKE_HST_EN BIT(22) +#define BIT_BT_WAKE_HST_EN BIT(22) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_ISO_BTPON2PP BIT(22) +#define BIT_BTGP_WAKE_HST_EN BIT(22) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ + +#define BIT_ISO_BTPON2PP BIT(22) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_REG_TXDMA_FAIL_PS BIT(21) +#define BIT_REG_TXDMA_FAIL_PS BIT(21) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WAKE_BT_EN BIT(21) -#define BIT_EN_BT BIT(20) +#define BIT_WAKE_BT_EN BIT(21) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ + +#define BIT_BTGP_WAKE_BT_EN BIT(21) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_EN_HWENTR_L1 BIT(19) +#define BIT_BTCOEX_CMD BIT(21) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_SUSN_EN BIT(19) +#define BIT_EN_BT BIT(20) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_HWROF_EN BIT(19) +#define BIT_BTGP_EN BIT(20) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_S3_RF_HW_EN BIT(19) +#define BIT_BT_UART_INTF BIT(20) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_EN_ADV_CLKGATE BIT(18) +#define BIT_EN_HWENTR_L1 BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_FUNC_EN BIT(18) +#define BIT_BT_SUSN_EN BIT(19) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_S2_RF_HW_EN BIT(18) +#define BIT_BTGP_SUS_EN BIT(19) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_HWPDN_SL BIT(17) +#define BIT_BT_HWROF_EN BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_S1_RF_HW_EN BIT(17) +#define BIT_S3_RF_HW_EN BIT(19) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ + +#define BIT_EN_ADV_CLKGATE BIT(18) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_DISN_EN BIT(16) +#define BIT_BT_FUNC_EN BIT(18) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_S0_RF_HW_EN BIT(16) +#define BIT_S2_RF_HW_EN BIT(18) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_PDN_PULL_EN BIT(15) +#define BIT_BT_HWPDN_SL BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WL_PDN_PULL_EN BIT(14) -#define BIT_EXTERNAL_REQUEST_PL BIT(13) +#define BIT_S1_RF_HW_EN BIT(17) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12) +#define BIT_BT_DISN_EN BIT(16) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_ISO_BA2PP BIT(11) -#define BIT_BT_AFE_LDO_EN BIT(10) +#define BIT_BT_HWPDEN BIT(16) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_PDN_PIN_SEL BIT(10) +#define BIT_S0_RF_HW_EN BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_GPIO11_PULL_LOW_EN BIT(9) +#define BIT_BT_PDN_PULL_EN BIT(15) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_AFE_PLL_EN BIT(9) +#define BIT_WL_PDN_PULL_EN BIT(14) +#define BIT_EXTERNAL_REQUEST_PL BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_GPIO4_PULL_LOW_EN BIT(8) +#define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ + +#define BIT_ISO_BA2PP BIT(11) +#define BIT_BT_AFE_LDO_EN BIT(10) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_DIG_CLK_EN BIT(8) +#define BIT_PDN_PIN_SEL BIT(10) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BT_WAKE_HST_SL BIT(7) +#define BIT_GPIO11_PULL_LOW_EN BIT(9) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_ASSERT_SPS_EN BIT(7) +#define BIT_BT_AFE_PLL_EN BIT(9) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WAKE_BT_SL BIT(6) +#define BIT_GPIO4_PULL_LOW_EN BIT(8) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_MASK_CHIPEN BIT(6) +#define BIT_BT_DIG_CLK_EN BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WL_DRV_EXIST_IDX BIT(5) +#define BIT_BT_WAKE_HST_SL BIT(7) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_ASSERT_RF_EN BIT(5) +#define BIT_BT_WAKE_HST_PL BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_DOP_EHPAD BIT(4) +#define BIT_ASSERT_SPS_EN BIT(7) #endif - -#if (HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_BIT_DOP_EHPAD BIT(4) +#define BIT_UART_BRIDGE BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WL_HWROF_EN BIT(3) +#define BIT_WAKE_BT_SL BIT(6) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_SDIO_PAD_SHUTDOWNB BIT(3) +#define BIT_WAKE_BT_PL BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WL_FUNC_EN BIT(2) +#define BIT_WLAN_32K_SEL BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_SDIO_CLK_SMT BIT(2) +#define BIT_MASK_CHIPEN BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8814B_SUPPORT) /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ -#define BIT_WL_HWPDN_SL BIT(1) -#define BIT_WL_HWPDN_EN BIT(0) +#define BIT_OSC32K_CTRL_SEL BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ +#define BIT_WL_DRV_EXIST_IDX BIT(5) -/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_F0N 23 -#define BIT_MASK_F0N 0x7 -#define BIT_F0N(x) (((x) & BIT_MASK_F0N) << BIT_SHIFT_F0N) -#define BIT_GET_F0N(x) (((x) >> BIT_SHIFT_F0N) & BIT_MASK_F0N) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ +#define BIT_ASSERT_RF_EN BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ +#define BIT_DOP_EHPAD BIT(4) -/* 2 REG_GSSR (Offset 0x006C) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_GPIO_15_TO_0_VAL 16 -#define BIT_MASK_GPIO_15_TO_0_VAL 0xffff -#define BIT_GPIO_15_TO_0_VAL(x) (((x) & BIT_MASK_GPIO_15_TO_0_VAL) << BIT_SHIFT_GPIO_15_TO_0_VAL) -#define BIT_GET_GPIO_15_TO_0_VAL(x) (((x) >> BIT_SHIFT_GPIO_15_TO_0_VAL) & BIT_MASK_GPIO_15_TO_0_VAL) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ +#define BIT_BIT_DOP_EHPAD BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ +#define BIT_WL_HWROF_EN BIT(3) -/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_F0F 10 -#define BIT_MASK_F0F 0x1fff -#define BIT_F0F(x) (((x) & BIT_MASK_F0F) << BIT_SHIFT_F0F) -#define BIT_GET_F0F(x) (((x) >> BIT_SHIFT_F0F) & BIT_MASK_F0F) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ +#define BIT_SDIO_PAD_SHUTDOWNB BIT(3) -#define BIT_SHIFT_DIVN 4 -#define BIT_MASK_DIVN 0x3f -#define BIT_DIVN(x) (((x) & BIT_MASK_DIVN) << BIT_SHIFT_DIVN) -#define BIT_GET_DIVN(x) (((x) >> BIT_SHIFT_DIVN) & BIT_MASK_DIVN) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM 0 -#define BIT_MASK_BB_DBG_SEL_AFE_SDM 0xf -#define BIT_BB_DBG_SEL_AFE_SDM(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM) -#define BIT_GET_BB_DBG_SEL_AFE_SDM(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM) & BIT_MASK_BB_DBG_SEL_AFE_SDM) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ +#define BIT_WL_FUNC_EN BIT(2) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ +#define BIT_SDIO_CLK_SMT BIT(2) -/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WLCLK_PHASE 0 -#define BIT_MASK_WLCLK_PHASE 0x1f -#define BIT_WLCLK_PHASE(x) (((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE) -#define BIT_GET_WLCLK_PHASE(x) (((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE) +/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ +#define BIT_WL_HWPDN_SL BIT(1) +#define BIT_WL_HWPDN_EN BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#define BIT_SHIFT_F0N 23 +#define BIT_MASK_F0N 0x7 +#define BIT_F0N(x) (((x) & BIT_MASK_F0N) << BIT_SHIFT_F0N) +#define BITS_F0N (BIT_MASK_F0N << BIT_SHIFT_F0N) +#define BIT_CLEAR_F0N(x) ((x) & (~BITS_F0N)) +#define BIT_GET_F0N(x) (((x) >> BIT_SHIFT_F0N) & BIT_MASK_F0N) +#define BIT_SET_F0N(x, v) (BIT_CLEAR_F0N(x) | BIT_F0N(v)) -/* 2 REG_GSSR (Offset 0x006C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_GPIO_15_TO_0_EN 0 -#define BIT_MASK_GPIO_15_TO_0_EN 0xffff -#define BIT_GPIO_15_TO_0_EN(x) (((x) & BIT_MASK_GPIO_15_TO_0_EN) << BIT_SHIFT_GPIO_15_TO_0_EN) -#define BIT_GET_GPIO_15_TO_0_EN(x) (((x) >> BIT_SHIFT_GPIO_15_TO_0_EN) & BIT_MASK_GPIO_15_TO_0_EN) +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#define BIT_BT_WAKE_DEV_EN_V1 BIT(19) +#define BIT_BT_WAKE_HST_EN_V1 BIT(18) +#define BIT_BT_WAKE_HST_PL_V1 BIT(17) -/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#endif -#define BIT_BBRSTB_STANDBY_V1 BIT(28) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_GSSR (Offset 0x006C) */ +#define BIT_SHIFT_GPIO_15_TO_0_VAL 16 +#define BIT_MASK_GPIO_15_TO_0_VAL 0xffff +#define BIT_GPIO_15_TO_0_VAL(x) \ + (((x) & BIT_MASK_GPIO_15_TO_0_VAL) << BIT_SHIFT_GPIO_15_TO_0_VAL) +#define BITS_GPIO_15_TO_0_VAL \ + (BIT_MASK_GPIO_15_TO_0_VAL << BIT_SHIFT_GPIO_15_TO_0_VAL) +#define BIT_CLEAR_GPIO_15_TO_0_VAL(x) ((x) & (~BITS_GPIO_15_TO_0_VAL)) +#define BIT_GET_GPIO_15_TO_0_VAL(x) \ + (((x) >> BIT_SHIFT_GPIO_15_TO_0_VAL) & BIT_MASK_GPIO_15_TO_0_VAL) +#define BIT_SET_GPIO_15_TO_0_VAL(x, v) \ + (BIT_CLEAR_GPIO_15_TO_0_VAL(x) | BIT_GPIO_15_TO_0_VAL(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ -#define BIT_DBG_GNT_WL_BT BIT(27) +#define BIT_BT_CLKREQ_EN_V1 BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ + +#define BIT_SHIFT_F0F 10 +#define BIT_MASK_F0F 0x1fff +#define BIT_F0F(x) (((x) & BIT_MASK_F0F) << BIT_SHIFT_F0F) +#define BITS_F0F (BIT_MASK_F0F << BIT_SHIFT_F0F) +#define BIT_CLEAR_F0F(x) ((x) & (~BITS_F0F)) +#define BIT_GET_F0F(x) (((x) >> BIT_SHIFT_F0F) & BIT_MASK_F0F) +#define BIT_SET_F0F(x, v) (BIT_CLEAR_F0F(x) | BIT_F0F(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_SYS_CLKR (Offset 0x0070) */ +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ -#define BIT_AFE_PORT3_ISO BIT(27) +#define BIT_GPIO_IE_V18 BIT(10) +#define BIT_PCIE_IE_V18 BIT(9) +#define BIT_UART_IE_V18 BIT(8) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ -/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_SHIFT_DIVN 4 +#define BIT_MASK_DIVN 0x3f +#define BIT_DIVN(x) (((x) & BIT_MASK_DIVN) << BIT_SHIFT_DIVN) +#define BITS_DIVN (BIT_MASK_DIVN << BIT_SHIFT_DIVN) +#define BIT_CLEAR_DIVN(x) ((x) & (~BITS_DIVN)) +#define BIT_GET_DIVN(x) (((x) >> BIT_SHIFT_DIVN) & BIT_MASK_DIVN) +#define BIT_SET_DIVN(x, v) (BIT_CLEAR_DIVN(x) | BIT_DIVN(v)) -#define BIT_LTE_MUX_CTRL_PATH BIT(26) +#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM 0 +#define BIT_MASK_BB_DBG_SEL_AFE_SDM 0xf +#define BIT_BB_DBG_SEL_AFE_SDM(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM) +#define BITS_BB_DBG_SEL_AFE_SDM \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM << BIT_SHIFT_BB_DBG_SEL_AFE_SDM) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM) & BIT_MASK_BB_DBG_SEL_AFE_SDM) +#define BIT_SET_BB_DBG_SEL_AFE_SDM(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) | BIT_BB_DBG_SEL_AFE_SDM(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDM_DEBUG (Offset 0x006C) */ +#define BIT_SHIFT_WLCLK_PHASE 0 +#define BIT_MASK_WLCLK_PHASE 0x1f +#define BIT_WLCLK_PHASE(x) \ + (((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE) +#define BITS_WLCLK_PHASE (BIT_MASK_WLCLK_PHASE << BIT_SHIFT_WLCLK_PHASE) +#define BIT_CLEAR_WLCLK_PHASE(x) ((x) & (~BITS_WLCLK_PHASE)) +#define BIT_GET_WLCLK_PHASE(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE) +#define BIT_SET_WLCLK_PHASE(x, v) \ + (BIT_CLEAR_WLCLK_PHASE(x) | BIT_WLCLK_PHASE(v)) -/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#endif -#define BIT_AFE_PORT2_ISO BIT(26) -#define BIT_AFE_PORT1_ISO BIT(25) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_GSSR (Offset 0x006C) */ +#define BIT_SHIFT_GPIO_15_TO_0_EN 0 +#define BIT_MASK_GPIO_15_TO_0_EN 0xffff +#define BIT_GPIO_15_TO_0_EN(x) \ + (((x) & BIT_MASK_GPIO_15_TO_0_EN) << BIT_SHIFT_GPIO_15_TO_0_EN) +#define BITS_GPIO_15_TO_0_EN \ + (BIT_MASK_GPIO_15_TO_0_EN << BIT_SHIFT_GPIO_15_TO_0_EN) +#define BIT_CLEAR_GPIO_15_TO_0_EN(x) ((x) & (~BITS_GPIO_15_TO_0_EN)) +#define BIT_GET_GPIO_15_TO_0_EN(x) \ + (((x) >> BIT_SHIFT_GPIO_15_TO_0_EN) & BIT_MASK_GPIO_15_TO_0_EN) +#define BIT_SET_GPIO_15_TO_0_EN(x, v) \ + (BIT_CLEAR_GPIO_15_TO_0_EN(x) | BIT_GPIO_15_TO_0_EN(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_LTE_COEX_UART BIT(25) +#define BIT_FORCE_RST_PCIE_APHY BIT(30) +#define BIT_FORCE_OFF_EPC BIT(29) +#define BIT_PTA_3W_MODE BIT(28) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_AFE_PORT0_ISO BIT(24) +#define BIT_BBRSTB_STANDBY_V1 BIT(28) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_3W_LTE_WL_GPIO BIT(24) +#define BIT_DBG_GNT_WL_BT BIT(27) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_USB_PWR_OFF_SEL BIT(23) -#define BIT_USB_HOST_PWR_OFF_EN_V1 BIT(22) -#define BIT_SYM_LPS_BLOCK_EN_V1 BIT(21) -#define BIT_USB_LPM_ACT_EN_V1 BIT(20) +#define BIT_AFE_PORT3_ISO BIT(27) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_SDIO_INT_POLARITY BIT(19) -#define BIT_SDIO_INT BIT(18) +#define BIT_LTE_MUX_CTRL_PATH BIT(26) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SYS_CLKR (Offset 0x0070) */ + +#define BIT_AFE_PORT2_ISO BIT(26) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_SDIO_OFF_EN BIT(17) +#define BIT_LTE_COEX_EN BIT(25) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_LTE_COEX_UART BIT(25) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_SDIO_OFF_EN_V1 BIT(17) +#define BIT_AFE_PORT1_ISO BIT(25) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ + +#define BIT_3W_LTE_GPIO_EN BIT(24) + +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_SDIO_ON_EN BIT(16) +#define BIT_3W_LTE_WL_GPIO BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_SDIO_ON_EN_V1 BIT(16) -#define BIT_DIS_U3MB_INU2 BIT(13) -#define BIT_USB3_MDIO_EN BIT(12) -#define BIT_USB3_BG_EN BIT(11) -#define BIT_USB3_MB_EN BIT(10) +#define BIT_AFE_PORT0_ISO BIT(24) +#define BIT_USB_PWR_OFF_SEL BIT(23) +#define BIT_USB_HOST_PWR_OFF_EN_V1 BIT(22) +#define BIT_SYM_LPS_BLOCK_EN_V1 BIT(21) +#define BIT_USB_LPM_ACT_EN_V1 BIT(20) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_SDIO_INT_POLARITY BIT(19) +#define BIT_SDIO_INT BIT(18) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10) -#define BIT_PCIE_WAIT_TIME BIT(9) +#define BIT_SDIO_OFF_EN BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_SDIO_OFF_EN_V1 BIT(17) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_USB3_CK_MD 8 -#define BIT_MASK_USB3_CK_MD 0x3 -#define BIT_USB3_CK_MD(x) (((x) & BIT_MASK_USB3_CK_MD) << BIT_SHIFT_USB3_CK_MD) -#define BIT_GET_USB3_CK_MD(x) (((x) >> BIT_SHIFT_USB3_CK_MD) & BIT_MASK_USB3_CK_MD) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_SDIO_ON_EN BIT(16) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_SDIO_ON_EN_V1 BIT(16) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8) +#define BIT_PCIE_FORCE_PWR_NGAT BIT(13) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_USB3_CKBUF BIT(7) -#define BIT_USB3_IBX_EN BIT(6) -#define BIT_U3_MB_MASK BIT(5) -#define BIT_U3_BG_MASK BIT(4) -#define BIT_DIS_USB3_MB_POLLING BIT(3) -#define BIT_PDN_MASK BIT(2) -#define BIT_NO_PDN_CHIPOFF BIT(1) +#define BIT_DIS_U3MB_INU2 BIT(13) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_RES_USB_MASS_STORAGE_DESC BIT(1) +#define BIT_PCIE_CALIB_EN_V1 BIT(12) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CLKR (Offset 0x0070) */ -#define BIT_PDN_HCOUNT BIT(0) +#define BIT_USB3_MDIO_EN BIT(12) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_USB_WAIT_TIME BIT(0) +#define BIT_PAGE3_AUXCLK_GATE BIT(11) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_USB3_BG_EN BIT(11) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TSFT_SEL 29 -#define BIT_MASK_TSFT_SEL 0x7 -#define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL) -#define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_USB3_MB_EN BIT(10) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_XTAL_SEL_0_V1 28 -#define BIT_MASK_XTAL_SEL_0_V1 0xf -#define BIT_XTAL_SEL_0_V1(x) (((x) & BIT_MASK_XTAL_SEL_0_V1) << BIT_SHIFT_XTAL_SEL_0_V1) -#define BIT_GET_XTAL_SEL_0_V1(x) (((x) >> BIT_SHIFT_XTAL_SEL_0_V1) & BIT_MASK_XTAL_SEL_0_V1) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_ISO_RFC2RF_3 BIT(27) -#define BIT_ISO_RFC2RF_2 BIT(26) +#define BIT_PCIE_WAIT_TIME BIT(9) +#define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_SYS_CLKR (Offset 0x0070) */ -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_SHIFT_USB3_CK_MD 8 +#define BIT_MASK_USB3_CK_MD 0x3 +#define BIT_USB3_CK_MD(x) (((x) & BIT_MASK_USB3_CK_MD) << BIT_SHIFT_USB3_CK_MD) +#define BITS_USB3_CK_MD (BIT_MASK_USB3_CK_MD << BIT_SHIFT_USB3_CK_MD) +#define BIT_CLEAR_USB3_CK_MD(x) ((x) & (~BITS_USB3_CK_MD)) +#define BIT_GET_USB3_CK_MD(x) \ + (((x) >> BIT_SHIFT_USB3_CK_MD) & BIT_MASK_USB3_CK_MD) +#define BIT_SET_USB3_CK_MD(x, v) (BIT_CLEAR_USB3_CK_MD(x) | BIT_USB3_CK_MD(v)) +#define BIT_USB3_CKBUF BIT(7) +#define BIT_USB3_IBX_EN BIT(6) -#define BIT_SHIFT_RPWM 24 -#define BIT_MASK_RPWM 0xff -#define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM) -#define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM) +#endif -#define BIT_ROM_DLEN BIT(19) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_ROM_PGE 16 -#define BIT_MASK_ROM_PGE 0x7 -#define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE) -#define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_BT_CLKREQ_EN BIT(6) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_BT_CTRL_USB_PWR_BACKDOOR BIT(5) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#endif -#define BIT_R_FORCE_CLK_U3 BIT(13) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_U3_MB_MASK BIT(5) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_USB_HOST_PWR_OFF_EN BIT(12) +#define BIT_USB_D_STATE_HOLD BIT(4) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_U3_BG_MASK BIT(4) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#endif -#define BIT_R_USB2_AUTOLOAD BIT(12) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_SHIFT_USB_CKREF_CML_R 4 +#define BIT_MASK_USB_CKREF_CML_R 0x3 +#define BIT_USB_CKREF_CML_R(x) \ + (((x) & BIT_MASK_USB_CKREF_CML_R) << BIT_SHIFT_USB_CKREF_CML_R) +#define BITS_USB_CKREF_CML_R \ + (BIT_MASK_USB_CKREF_CML_R << BIT_SHIFT_USB_CKREF_CML_R) +#define BIT_CLEAR_USB_CKREF_CML_R(x) ((x) & (~BITS_USB_CKREF_CML_R)) +#define BIT_GET_USB_CKREF_CML_R(x) \ + (((x) >> BIT_SHIFT_USB_CKREF_CML_R) & BIT_MASK_USB_CKREF_CML_R) +#define BIT_SET_USB_CKREF_CML_R(x, v) \ + (BIT_CLEAR_USB_CKREF_CML_R(x) | BIT_USB_CKREF_CML_R(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_SYM_LPS_BLOCK_EN BIT(11) +#define BIT_REG_FORCE_DP BIT(3) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_DIS_USB3_MB_POLLING BIT(3) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#endif -#define BIT_FORCE_U2CK BIT(11) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_BTGP_CLKREQ_EN BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_USB_LPM_ACT_EN BIT(10) +#define BIT_REG_DP_MODE BIT(2) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ - -#define BIT_FORCE_CLK BIT(10) +#define BIT_PDN_MASK BIT(2) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_SHIFT_USB_CKREF_D2S_I 2 +#define BIT_MASK_USB_CKREF_D2S_I 0x3 +#define BIT_USB_CKREF_D2S_I(x) \ + (((x) & BIT_MASK_USB_CKREF_D2S_I) << BIT_SHIFT_USB_CKREF_D2S_I) +#define BITS_USB_CKREF_D2S_I \ + (BIT_MASK_USB_CKREF_D2S_I << BIT_SHIFT_USB_CKREF_D2S_I) +#define BIT_CLEAR_USB_CKREF_D2S_I(x) ((x) & (~BITS_USB_CKREF_D2S_I)) +#define BIT_GET_USB_CKREF_D2S_I(x) \ + (((x) >> BIT_SHIFT_USB_CKREF_D2S_I) & BIT_MASK_USB_CKREF_D2S_I) +#define BIT_SET_USB_CKREF_D2S_I(x, v) \ + (BIT_CLEAR_USB_CKREF_D2S_I(x) | BIT_USB_CKREF_D2S_I(v)) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#endif -#define BIT_USB_LPM_NY BIT(9) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_USB_INSTALL_EN BIT(1) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_U2_FORCE BIT(9) +#define BIT_RES_USB_MASS_STORAGE_DESC BIT(1) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_NO_PDN_CHIPOFF BIT(1) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#endif -#define BIT_USB_SUS_DIS BIT(8) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_USB_BT_CLKSEL BIT(0) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ -#define BIT_U3_FORCE BIT(8) +#define BIT_USB_WAIT_TIME BIT(0) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CLKR (Offset 0x0070) */ +#define BIT_PDN_HCOUNT BIT(0) -/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#endif +#if (HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_SDIO_PAD_E 5 -#define BIT_MASK_SDIO_PAD_E 0x7 -#define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E) -#define BIT_GET_SDIO_PAD_E(x) (((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E) +/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ +#define BIT_SHIFT_SI_AUTHORIZATION 0 +#define BIT_MASK_SI_AUTHORIZATION 0xff +#define BIT_SI_AUTHORIZATION(x) \ + (((x) & BIT_MASK_SI_AUTHORIZATION) << BIT_SHIFT_SI_AUTHORIZATION) +#define BITS_SI_AUTHORIZATION \ + (BIT_MASK_SI_AUTHORIZATION << BIT_SHIFT_SI_AUTHORIZATION) +#define BIT_CLEAR_SI_AUTHORIZATION(x) ((x) & (~BITS_SI_AUTHORIZATION)) +#define BIT_GET_SI_AUTHORIZATION(x) \ + (((x) >> BIT_SHIFT_SI_AUTHORIZATION) & BIT_MASK_SI_AUTHORIZATION) +#define BIT_SET_SI_AUTHORIZATION(x, v) \ + (BIT_CLEAR_SI_AUTHORIZATION(x) | BIT_SI_AUTHORIZATION(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_USB_LPPLL_EN BIT(4) +#define BIT_SHIFT_HCI_RATIO 30 +#define BIT_MASK_HCI_RATIO 0x3 +#define BIT_HCI_RATIO(x) (((x) & BIT_MASK_HCI_RATIO) << BIT_SHIFT_HCI_RATIO) +#define BITS_HCI_RATIO (BIT_MASK_HCI_RATIO << BIT_SHIFT_HCI_RATIO) +#define BIT_CLEAR_HCI_RATIO(x) ((x) & (~BITS_HCI_RATIO)) +#define BIT_GET_HCI_RATIO(x) (((x) >> BIT_SHIFT_HCI_RATIO) & BIT_MASK_HCI_RATIO) +#define BIT_SET_HCI_RATIO(x, v) (BIT_CLEAR_HCI_RATIO(x) | BIT_HCI_RATIO(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_SDIO_H3L1 BIT(4) +#define BIT_SHIFT_TSFT_SEL 29 +#define BIT_MASK_TSFT_SEL 0x7 +#define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL) +#define BITS_TSFT_SEL (BIT_MASK_TSFT_SEL << BIT_SHIFT_TSFT_SEL) +#define BIT_CLEAR_TSFT_SEL(x) ((x) & (~BITS_TSFT_SEL)) +#define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL) +#define BIT_SET_TSFT_SEL(x, v) (BIT_CLEAR_TSFT_SEL(x) | BIT_TSFT_SEL(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_ROP_SW15 BIT(2) +#define BIT_SHIFT_WAIT_HPOW_TIME 28 +#define BIT_MASK_WAIT_HPOW_TIME 0x3 +#define BIT_WAIT_HPOW_TIME(x) \ + (((x) & BIT_MASK_WAIT_HPOW_TIME) << BIT_SHIFT_WAIT_HPOW_TIME) +#define BITS_WAIT_HPOW_TIME \ + (BIT_MASK_WAIT_HPOW_TIME << BIT_SHIFT_WAIT_HPOW_TIME) +#define BIT_CLEAR_WAIT_HPOW_TIME(x) ((x) & (~BITS_WAIT_HPOW_TIME)) +#define BIT_GET_WAIT_HPOW_TIME(x) \ + (((x) >> BIT_SHIFT_WAIT_HPOW_TIME) & BIT_MASK_WAIT_HPOW_TIME) +#define BIT_SET_WAIT_HPOW_TIME(x, v) \ + (BIT_CLEAR_WAIT_HPOW_TIME(x) | BIT_WAIT_HPOW_TIME(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_SHIFT_XTAL_SEL_0_V1 28 +#define BIT_MASK_XTAL_SEL_0_V1 0xf +#define BIT_XTAL_SEL_0_V1(x) \ + (((x) & BIT_MASK_XTAL_SEL_0_V1) << BIT_SHIFT_XTAL_SEL_0_V1) +#define BITS_XTAL_SEL_0_V1 (BIT_MASK_XTAL_SEL_0_V1 << BIT_SHIFT_XTAL_SEL_0_V1) +#define BIT_CLEAR_XTAL_SEL_0_V1(x) ((x) & (~BITS_XTAL_SEL_0_V1)) +#define BIT_GET_XTAL_SEL_0_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_0_V1) & BIT_MASK_XTAL_SEL_0_V1) +#define BIT_SET_XTAL_SEL_0_V1(x, v) \ + (BIT_CLEAR_XTAL_SEL_0_V1(x) | BIT_XTAL_SEL_0_V1(v)) -#define BIT_SHIFT_USB23_SW_MODE 2 -#define BIT_MASK_USB23_SW_MODE 0x3 -#define BIT_USB23_SW_MODE(x) (((x) & BIT_MASK_USB23_SW_MODE) << BIT_SHIFT_USB23_SW_MODE) -#define BIT_GET_USB23_SW_MODE(x) (((x) >> BIT_SHIFT_USB23_SW_MODE) & BIT_MASK_USB23_SW_MODE) +#endif +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_TSFT_BAND_SEL BIT(28) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_PCI_CKRDY_OPT BIT(1) +#define BIT_PCIE_HPOW_OPT2 BIT(27) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_PCLK_VLD_SEL BIT(1) +#define BIT_ISO_RFC2RF_3 BIT(27) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_PCI_VAUX_EN BIT(0) +#define BIT_PCIE_HPOW_OPT1 BIT(26) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8814AMP_SUPPORT) /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_VAUX_EN BIT(0) +#define BIT_ISO_RFC2RF_2 BIT(26) -/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#endif -#define BIT_SDM_ORDER BIT(30) -#define BIT_XTAL_DRV_RF_LATCH_V1 BIT(29) -#define BIT_XTAL_VDD_SEL_V1 BIT(28) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_PCIE_HPOW_OPT0 BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_XTAL_DRV_RF_LATCH BIT(27) +#define BIT_SHIFT_RPWM 24 +#define BIT_MASK_RPWM 0xff +#define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM) +#define BITS_RPWM (BIT_MASK_RPWM << BIT_SHIFT_RPWM) +#define BIT_CLEAR_RPWM(x) ((x) & (~BITS_RPWM)) +#define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM) +#define BIT_SET_RPWM(x, v) (BIT_CLEAR_RPWM(x) | BIT_RPWM(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_PCIE_EPC_ISO BIT(24) +#define BIT_PCIE_EPC_OPT BIT(23) +#define BIT_PCIE_SUS_OPT BIT(22) +#define BIT_PCIE_L1OF_OPT BIT(21) +#define BIT_PCIE_L1OF_LDOA BIT(20) +#define BIT_USB_SUS_LDOA BIT(19) -/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#endif -#define BIT_XQSEL_RF_AWAKE_V1 BIT(27) +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_SDIO_PAD_E5 BIT(18) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_XTAL_VDD_SEL BIT(26) +#define BIT_USB_HOST_PWR_OFF_SEL BIT(13) #endif +#if (HALMAC_8814A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_R_FORCE_CLK_U3 BIT(13) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#endif -#define BIT_RF1_SDMRSTB BIT(26) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_USB_HOST_PWR_OFF_EN BIT(12) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT) -/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_GATED_XTAL_OK0_V1 BIT(26) +#define BIT_R_USB2_AUTOLOAD BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_SYM_LPS_BLOCK_EN BIT(11) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#endif -#define BIT_XQSEL_RF BIT(25) +#if (HALMAC_8814A_SUPPORT) -#endif +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_FORCE_U2CK BIT(11) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_RF1_RSTB BIT(25) +#define BIT_USB_LPM_ACT_EN BIT(10) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - - -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_XQSEL_RF_AWAKE BIT(25) +#define BIT_FORCE_CLK BIT(10) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_USB_LPM_NY BIT(9) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#endif -#define BIT_XQSEL_RF_INITIAL BIT(24) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_IBX_EN_VALUE BIT(9) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_RF1_EN BIT(24) +#define BIT_U2_FORCE BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_USB_SUS_DIS BIT(8) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#endif -#define BIT_XQSEL_BIT1 BIT(24) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_IB_EN_VALUE BIT(8) -#if (HALMAC_8192E_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_REG_VREF_SEL BIT(23) +#define BIT_U3_FORCE BIT(8) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_EN_LW_PWR BIT(6) -/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_F0N_2_TO_0 23 -#define BIT_MASK_F0N_2_TO_0 0x7 -#define BIT_F0N_2_TO_0(x) (((x) & BIT_MASK_F0N_2_TO_0) << BIT_SHIFT_F0N_2_TO_0) -#define BIT_GET_F0N_2_TO_0(x) (((x) >> BIT_SHIFT_F0N_2_TO_0) & BIT_MASK_F0N_2_TO_0) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_SHIFT_SDIO_PAD_E 5 +#define BIT_MASK_SDIO_PAD_E 0x7 +#define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E) +#define BITS_SDIO_PAD_E (BIT_MASK_SDIO_PAD_E << BIT_SHIFT_SDIO_PAD_E) +#define BIT_CLEAR_SDIO_PAD_E(x) ((x) & (~BITS_SDIO_PAD_E)) +#define BIT_GET_SDIO_PAD_E(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E) +#define BIT_SET_SDIO_PAD_E(x, v) (BIT_CLEAR_SDIO_PAD_E(x) | BIT_SDIO_PAD_E(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_EN_REGU BIT(5) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_REG_LPFEN BIT(22) -#define BIT_REG_KVCO BIT(21) -#define BIT_XTAL_DRV_AGPIO_BIT1 BIT(20) +#define BIT_USB_LPPLL_EN BIT(4) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_FORCED_IB_EN BIT(4) +#define BIT_EN_PC BIT(4) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_XTAL_LDO 20 -#define BIT_MASK_XTAL_LDO 0x7 -#define BIT_XTAL_LDO(x) (((x) & BIT_MASK_XTAL_LDO) << BIT_SHIFT_XTAL_LDO) -#define BIT_GET_XTAL_LDO(x) (((x) >> BIT_SHIFT_XTAL_LDO) & BIT_MASK_XTAL_LDO) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_SDIO_H3L1 BIT(4) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_PERST_SYNC_EN BIT(3) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#endif -#define BIT_XTAL_DRV_AGPIO_BIT0 BIT(19) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_USB1_1_USB2_0_DECISION BIT(3) +#define BIT_EN_REGBG BIT(3) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_XTAL_GRF2 BIT(18) -#define BIT_REG_REF_SEL BIT(17) -#define BIT_REG_320_SEL BIT(16) +#define BIT_ROP_SW15 BIT(2) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_REG_BG_LPF BIT(2) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_ADC_CK_SYNC_EN BIT(16) +#define BIT_SHIFT_USB23_SW_MODE 2 +#define BIT_MASK_USB23_SW_MODE 0x3 +#define BIT_USB23_SW_MODE(x) \ + (((x) & BIT_MASK_USB23_SW_MODE) << BIT_SHIFT_USB23_SW_MODE) +#define BITS_USB23_SW_MODE (BIT_MASK_USB23_SW_MODE << BIT_SHIFT_USB23_SW_MODE) +#define BIT_CLEAR_USB23_SW_MODE(x) ((x) & (~BITS_USB23_SW_MODE)) +#define BIT_GET_USB23_SW_MODE(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE) & BIT_MASK_USB23_SW_MODE) +#define BIT_SET_USB23_SW_MODE(x, v) \ + (BIT_CLEAR_USB23_SW_MODE(x) | BIT_USB23_SW_MODE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_PCI_CKRDY_OPT BIT(1) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#endif -#define BIT_EN_SYM BIT(15) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_IOFFSET 10 -#define BIT_MASK_IOFFSET 0x1f -#define BIT_IOFFSET(x) (((x) & BIT_MASK_IOFFSET) << BIT_SHIFT_IOFFSET) -#define BIT_GET_IOFFSET(x) (((x) >> BIT_SHIFT_IOFFSET) & BIT_MASK_IOFFSET) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_PCLK_VLD_SEL BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_PCI_VAUX_EN BIT(0) -/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ -#define BIT_SHIFT_F0F_12_TO_0 10 -#define BIT_MASK_F0F_12_TO_0 0x1fff -#define BIT_F0F_12_TO_0(x) (((x) & BIT_MASK_F0F_12_TO_0) << BIT_SHIFT_F0F_12_TO_0) -#define BIT_GET_F0F_12_TO_0(x) (((x) >> BIT_SHIFT_F0F_12_TO_0) & BIT_MASK_F0F_12_TO_0) +#define BIT_SHIFT_REG_BG 0 +#define BIT_MASK_REG_BG 0x3 +#define BIT_REG_BG(x) (((x) & BIT_MASK_REG_BG) << BIT_SHIFT_REG_BG) +#define BITS_REG_BG (BIT_MASK_REG_BG << BIT_SHIFT_REG_BG) +#define BIT_CLEAR_REG_BG(x) ((x) & (~BITS_REG_BG)) +#define BIT_GET_REG_BG(x) (((x) >> BIT_SHIFT_REG_BG) & BIT_MASK_REG_BG) +#define BIT_SET_REG_BG(x, v) (BIT_CLEAR_REG_BG(x) | BIT_REG_BG(v)) +#define BIT_SHIFT_REG_VADJ 0 +#define BIT_MASK_REG_VADJ 0xf +#define BIT_REG_VADJ(x) (((x) & BIT_MASK_REG_VADJ) << BIT_SHIFT_REG_VADJ) +#define BITS_REG_VADJ (BIT_MASK_REG_VADJ << BIT_SHIFT_REG_VADJ) +#define BIT_CLEAR_REG_VADJ(x) ((x) & (~BITS_REG_VADJ)) +#define BIT_GET_REG_VADJ(x) (((x) >> BIT_SHIFT_REG_VADJ) & BIT_MASK_REG_VADJ) +#define BIT_SET_REG_VADJ(x, v) (BIT_CLEAR_REG_VADJ(x) | BIT_REG_VADJ(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ +#define BIT_VAUX_EN BIT(0) -/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#define BIT_SDM_ORDER BIT(30) +#define BIT_XTAL_DRV_RF_LATCH_V1 BIT(29) +#define BIT_XTAL_VDD_SEL_V1 BIT(28) -#define BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1 8 -#define BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 0x3 -#define BIT_APLL_FREF_SEL_BIT_2_TO_1(x) (((x) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) -#define BIT_GET_APLL_FREF_SEL_BIT_2_TO_1(x) (((x) >> BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) +#endif -#define BIT_APLL_FREF_SEL_BIT3 BIT(7) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_APLL_LDO_V12ADJ 5 -#define BIT_MASK_APLL_LDO_V12ADJ 0x3 -#define BIT_APLL_LDO_V12ADJ(x) (((x) & BIT_MASK_APLL_LDO_V12ADJ) << BIT_SHIFT_APLL_LDO_V12ADJ) -#define BIT_GET_APLL_LDO_V12ADJ(x) (((x) >> BIT_SHIFT_APLL_LDO_V12ADJ) & BIT_MASK_APLL_LDO_V12ADJ) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_APLL_160_GATEB BIT(4) +#define BIT_XTAL_DRV_RF_LATCH BIT(27) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#define BIT_XQSEL_RF_AWAKE_V1 BIT(27) -#define BIT_SHIFT_DIVN_5_TO_0 4 -#define BIT_MASK_DIVN_5_TO_0 0x3f -#define BIT_DIVN_5_TO_0(x) (((x) & BIT_MASK_DIVN_5_TO_0) << BIT_SHIFT_DIVN_5_TO_0) -#define BIT_GET_DIVN_5_TO_0(x) (((x) >> BIT_SHIFT_DIVN_5_TO_0) & BIT_MASK_DIVN_5_TO_0) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_XTAL_VDD_SEL BIT(26) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_AFE_DUMMY BIT(3) -#define BIT_REG_IDOUBLE BIT(2) -#define BIT_REG_VCO_BIAS_BIT0 BIT(1) -#define BIT_REG_VCO_BIAS_BIT1 BIT(0) +#define BIT_RF1_SDMRSTB BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#define BIT_GATED_XTAL_OK0_V1 BIT(26) -#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0 0 -#define BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 0xf -#define BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_3_TO_0(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) +#endif +#if (HALMAC_8192E_SUPPORT) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_REF_FREF_EDGE BIT(29) -#define BIT_REG_VREF_SEL_V1 BIT(28) +#define BIT_XQSEL_RF BIT(25) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_ZCD_HW_AUTO_EN BIT(27) -#define BIT_ZCD_REGSEL BIT(26) +#define BIT_RF1_RSTB BIT(25) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_XQSEL_RF_AWAKE BIT(25) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8192E_SUPPORT) -#define BIT_SHIFT_REG_CP_OFFSET_4_TO_0 23 -#define BIT_MASK_REG_CP_OFFSET_4_TO_0 0x1f -#define BIT_REG_CP_OFFSET_4_TO_0(x) (((x) & BIT_MASK_REG_CP_OFFSET_4_TO_0) << BIT_SHIFT_REG_CP_OFFSET_4_TO_0) -#define BIT_GET_REG_CP_OFFSET_4_TO_0(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_4_TO_0) & BIT_MASK_REG_CP_OFFSET_4_TO_0) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_XQSEL_RF_INITIAL BIT(24) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF1_EN BIT(24) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_AUTO_ZCD_IN_CODE 21 -#define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f -#define BIT_AUTO_ZCD_IN_CODE(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE) -#define BIT_GET_AUTO_ZCD_IN_CODE(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_XQSEL_BIT1 BIT(24) #endif +#if (HALMAC_8192E_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_REG_VREF_SEL BIT(23) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_REG_RS_SET_2_TO_0 20 -#define BIT_MASK_REG_RS_SET_2_TO_0 0x7 -#define BIT_REG_RS_SET_2_TO_0(x) (((x) & BIT_MASK_REG_RS_SET_2_TO_0) << BIT_SHIFT_REG_RS_SET_2_TO_0) -#define BIT_GET_REG_RS_SET_2_TO_0(x) (((x) >> BIT_SHIFT_REG_RS_SET_2_TO_0) & BIT_MASK_REG_RS_SET_2_TO_0) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_DITHER_SDM_BIT3 BIT(23) -#define BIT_SHIFT_REG_CS_SET_1_TO_0 18 -#define BIT_MASK_REG_CS_SET_1_TO_0 0x3 -#define BIT_REG_CS_SET_1_TO_0(x) (((x) & BIT_MASK_REG_CS_SET_1_TO_0) << BIT_SHIFT_REG_CS_SET_1_TO_0) -#define BIT_GET_REG_CS_SET_1_TO_0(x) (((x) >> BIT_SHIFT_REG_CS_SET_1_TO_0) & BIT_MASK_REG_CS_SET_1_TO_0) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_REG_CP_SET_1_TO_0 16 -#define BIT_MASK_REG_CP_SET_1_TO_0 0x3 -#define BIT_REG_CP_SET_1_TO_0(x) (((x) & BIT_MASK_REG_CP_SET_1_TO_0) << BIT_SHIFT_REG_CP_SET_1_TO_0) -#define BIT_GET_REG_CP_SET_1_TO_0(x) (((x) >> BIT_SHIFT_REG_CP_SET_1_TO_0) & BIT_MASK_REG_CP_SET_1_TO_0) +/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#define BIT_SHIFT_F0N_2_TO_0 23 +#define BIT_MASK_F0N_2_TO_0 0x7 +#define BIT_F0N_2_TO_0(x) (((x) & BIT_MASK_F0N_2_TO_0) << BIT_SHIFT_F0N_2_TO_0) +#define BITS_F0N_2_TO_0 (BIT_MASK_F0N_2_TO_0 << BIT_SHIFT_F0N_2_TO_0) +#define BIT_CLEAR_F0N_2_TO_0(x) ((x) & (~BITS_F0N_2_TO_0)) +#define BIT_GET_F0N_2_TO_0(x) \ + (((x) >> BIT_SHIFT_F0N_2_TO_0) & BIT_MASK_F0N_2_TO_0) +#define BIT_SET_F0N_2_TO_0(x, v) (BIT_CLEAR_F0N_2_TO_0(x) | BIT_F0N_2_TO_0(v)) #endif +#if (HALMAC_8192E_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_REG_LPFEN BIT(22) +#define BIT_REG_KVCO BIT(21) +#define BIT_XTAL_DRV_AGPIO_BIT1 BIT(20) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_ZCD_CODE_IN_L 16 -#define BIT_MASK_ZCD_CODE_IN_L 0x1f -#define BIT_ZCD_CODE_IN_L(x) (((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L) -#define BIT_GET_ZCD_CODE_IN_L(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_SHIFT_XTAL_LDO 20 +#define BIT_MASK_XTAL_LDO 0x7 +#define BIT_XTAL_LDO(x) (((x) & BIT_MASK_XTAL_LDO) << BIT_SHIFT_XTAL_LDO) +#define BITS_XTAL_LDO (BIT_MASK_XTAL_LDO << BIT_SHIFT_XTAL_LDO) +#define BIT_CLEAR_XTAL_LDO(x) ((x) & (~BITS_XTAL_LDO)) +#define BIT_GET_XTAL_LDO(x) (((x) >> BIT_SHIFT_XTAL_LDO) & BIT_MASK_XTAL_LDO) +#define BIT_SET_XTAL_LDO(x, v) (BIT_CLEAR_XTAL_LDO(x) | BIT_XTAL_LDO(v)) #endif +#if (HALMAC_8192E_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -#define BIT_LPFEN BIT(15) +#define BIT_XTAL_DRV_AGPIO_BIT0 BIT(19) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_XTAL_GRF2 BIT(18) +#define BIT_REG_REF_SEL BIT(17) +#define BIT_REG_320_SEL BIT(16) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_LDO_HV5_DUMMY 14 -#define BIT_MASK_LDO_HV5_DUMMY 0x3 -#define BIT_LDO_HV5_DUMMY(x) (((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY) -#define BIT_GET_LDO_HV5_DUMMY(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_ADC_CK_SYNC_EN BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_EN_SYM BIT(15) -#define BIT_REG_DOGENB BIT(14) -#define BIT_REG_TEST_EN BIT(13) +#define BIT_SHIFT_IOFFSET 10 +#define BIT_MASK_IOFFSET 0x1f +#define BIT_IOFFSET(x) (((x) & BIT_MASK_IOFFSET) << BIT_SHIFT_IOFFSET) +#define BITS_IOFFSET (BIT_MASK_IOFFSET << BIT_SHIFT_IOFFSET) +#define BIT_CLEAR_IOFFSET(x) ((x) & (~BITS_IOFFSET)) +#define BIT_GET_IOFFSET(x) (((x) >> BIT_SHIFT_IOFFSET) & BIT_MASK_IOFFSET) +#define BIT_SET_IOFFSET(x, v) (BIT_CLEAR_IOFFSET(x) | BIT_IOFFSET(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF2_SDMRSTB BIT(10) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_REG_VTUNE33 12 -#define BIT_MASK_REG_VTUNE33 0x3 -#define BIT_REG_VTUNE33(x) (((x) & BIT_MASK_REG_VTUNE33) << BIT_SHIFT_REG_VTUNE33) -#define BIT_GET_REG_VTUNE33(x) (((x) >> BIT_SHIFT_REG_VTUNE33) & BIT_MASK_REG_VTUNE33) +/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#define BIT_SHIFT_F0F_12_TO_0 10 +#define BIT_MASK_F0F_12_TO_0 0x1fff +#define BIT_F0F_12_TO_0(x) \ + (((x) & BIT_MASK_F0F_12_TO_0) << BIT_SHIFT_F0F_12_TO_0) +#define BITS_F0F_12_TO_0 (BIT_MASK_F0F_12_TO_0 << BIT_SHIFT_F0F_12_TO_0) +#define BIT_CLEAR_F0F_12_TO_0(x) ((x) & (~BITS_F0F_12_TO_0)) +#define BIT_GET_F0F_12_TO_0(x) \ + (((x) >> BIT_SHIFT_F0F_12_TO_0) & BIT_MASK_F0F_12_TO_0) +#define BIT_SET_F0F_12_TO_0(x, v) \ + (BIT_CLEAR_F0F_12_TO_0(x) | BIT_F0F_12_TO_0(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF2_RSTB BIT(9) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12 -#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3 -#define BIT_REG_VTUNE33_BIT0_TO_BIT1(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) -#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1 8 +#define BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 0x3 +#define BIT_APLL_FREF_SEL_BIT_2_TO_1(x) \ + (((x) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) \ + << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) +#define BITS_APLL_FREF_SEL_BIT_2_TO_1 \ + (BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 \ + << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) +#define BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x) \ + ((x) & (~BITS_APLL_FREF_SEL_BIT_2_TO_1)) +#define BIT_GET_APLL_FREF_SEL_BIT_2_TO_1(x) \ + (((x) >> BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) & \ + BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) +#define BIT_SET_APLL_FREF_SEL_BIT_2_TO_1(x, v) \ + (BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x) | \ + BIT_APLL_FREF_SEL_BIT_2_TO_1(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF2_EN BIT(8) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_APLL_FREF_SEL_BIT3 BIT(7) -#define BIT_SHIFT_REG_STANDBY33 10 -#define BIT_MASK_REG_STANDBY33 0x3 -#define BIT_REG_STANDBY33(x) (((x) & BIT_MASK_REG_STANDBY33) << BIT_SHIFT_REG_STANDBY33) -#define BIT_GET_REG_STANDBY33(x) (((x) >> BIT_SHIFT_REG_STANDBY33) & BIT_MASK_REG_STANDBY33) +#define BIT_SHIFT_APLL_LDO_V12ADJ 5 +#define BIT_MASK_APLL_LDO_V12ADJ 0x3 +#define BIT_APLL_LDO_V12ADJ(x) \ + (((x) & BIT_MASK_APLL_LDO_V12ADJ) << BIT_SHIFT_APLL_LDO_V12ADJ) +#define BITS_APLL_LDO_V12ADJ \ + (BIT_MASK_APLL_LDO_V12ADJ << BIT_SHIFT_APLL_LDO_V12ADJ) +#define BIT_CLEAR_APLL_LDO_V12ADJ(x) ((x) & (~BITS_APLL_LDO_V12ADJ)) +#define BIT_GET_APLL_LDO_V12ADJ(x) \ + (((x) >> BIT_SHIFT_APLL_LDO_V12ADJ) & BIT_MASK_APLL_LDO_V12ADJ) +#define BIT_SET_APLL_LDO_V12ADJ(x, v) \ + (BIT_CLEAR_APLL_LDO_V12ADJ(x) | BIT_APLL_LDO_V12ADJ(v)) +#define BIT_APLL_160_GATEB BIT(4) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#define BIT_SHIFT_DIVN_5_TO_0 4 +#define BIT_MASK_DIVN_5_TO_0 0x3f +#define BIT_DIVN_5_TO_0(x) \ + (((x) & BIT_MASK_DIVN_5_TO_0) << BIT_SHIFT_DIVN_5_TO_0) +#define BITS_DIVN_5_TO_0 (BIT_MASK_DIVN_5_TO_0 << BIT_SHIFT_DIVN_5_TO_0) +#define BIT_CLEAR_DIVN_5_TO_0(x) ((x) & (~BITS_DIVN_5_TO_0)) +#define BIT_GET_DIVN_5_TO_0(x) \ + (((x) >> BIT_SHIFT_DIVN_5_TO_0) & BIT_MASK_DIVN_5_TO_0) +#define BIT_SET_DIVN_5_TO_0(x, v) \ + (BIT_CLEAR_DIVN_5_TO_0(x) | BIT_DIVN_5_TO_0(v)) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10 -#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3 -#define BIT_REG_STANDBY33_BIT0_TO_BIT1(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) -#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_AFE_DUMMY BIT(3) +#define BIT_REG_IDOUBLE BIT(2) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF3_SDMRSTB BIT(2) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_REG_LOAD33 8 -#define BIT_MASK_REG_LOAD33 0x3 -#define BIT_REG_LOAD33(x) (((x) & BIT_MASK_REG_LOAD33) << BIT_SHIFT_REG_LOAD33) -#define BIT_GET_REG_LOAD33(x) (((x) >> BIT_SHIFT_REG_LOAD33) & BIT_MASK_REG_LOAD33) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_REG_VCO_BIAS_BIT0 BIT(1) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF3_RSTB BIT(1) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_REG_DIV_SEL 8 -#define BIT_MASK_REG_DIV_SEL 0x1f -#define BIT_REG_DIV_SEL(x) (((x) & BIT_MASK_REG_DIV_SEL) << BIT_SHIFT_REG_DIV_SEL) -#define BIT_GET_REG_DIV_SEL(x) (((x) >> BIT_SHIFT_REG_DIV_SEL) & BIT_MASK_REG_DIV_SEL) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_REG_VCO_BIAS_BIT1 BIT(0) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL4 (Offset 0x0078) */ +#define BIT_RF3_EN BIT(0) -/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8 -#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3 -#define BIT_REG_LOAD33_BIT0_TO_BIT1(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) -#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) +/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */ +#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0 0 +#define BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 0xf +#define BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) +#define BITS_BB_DBG_SEL_AFE_SDM_3_TO_0 \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \ + ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_3_TO_0)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_3_TO_0(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x) | \ + BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ + +#define BIT_SPS_EN_DIODE BIT(31) + +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_BYPASS_L BIT(7) +#define BIT_EXT_SWR_CTRL_EN BIT(31) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_EN_CK200M BIT(7) +#define BIT_REF_FREF_EDGE BIT(29) +#define BIT_REG_VREF_SEL_V1 BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_LDOF_L BIT(6) +#define BIT_ZCD_HW_AUTO_EN BIT(27) +#define BIT_ZCD_REGSEL BIT(26) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ + +#define BIT_SHIFT_REG_CP_OFFSET_4_TO_0 23 +#define BIT_MASK_REG_CP_OFFSET_4_TO_0 0x1f +#define BIT_REG_CP_OFFSET_4_TO_0(x) \ + (((x) & BIT_MASK_REG_CP_OFFSET_4_TO_0) \ + << BIT_SHIFT_REG_CP_OFFSET_4_TO_0) +#define BITS_REG_CP_OFFSET_4_TO_0 \ + (BIT_MASK_REG_CP_OFFSET_4_TO_0 << BIT_SHIFT_REG_CP_OFFSET_4_TO_0) +#define BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) ((x) & (~BITS_REG_CP_OFFSET_4_TO_0)) +#define BIT_GET_REG_CP_OFFSET_4_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_CP_OFFSET_4_TO_0) & \ + BIT_MASK_REG_CP_OFFSET_4_TO_0) +#define BIT_SET_REG_CP_OFFSET_4_TO_0(x, v) \ + (BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) | BIT_REG_CP_OFFSET_4_TO_0(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_OCPS_L BIT(5) +#define BIT_SHIFT_AUTO_ZCD_IN_CODE 21 +#define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f +#define BIT_AUTO_ZCD_IN_CODE(x) \ + (((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE) +#define BITS_AUTO_ZCD_IN_CODE \ + (BIT_MASK_AUTO_ZCD_IN_CODE << BIT_SHIFT_AUTO_ZCD_IN_CODE) +#define BIT_CLEAR_AUTO_ZCD_IN_CODE(x) ((x) & (~BITS_AUTO_ZCD_IN_CODE)) +#define BIT_GET_AUTO_ZCD_IN_CODE(x) \ + (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE) +#define BIT_SET_AUTO_ZCD_IN_CODE(x, v) \ + (BIT_CLEAR_AUTO_ZCD_IN_CODE(x) | BIT_AUTO_ZCD_IN_CODE(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_REG_RS_SET_2_TO_0 20 +#define BIT_MASK_REG_RS_SET_2_TO_0 0x7 +#define BIT_REG_RS_SET_2_TO_0(x) \ + (((x) & BIT_MASK_REG_RS_SET_2_TO_0) << BIT_SHIFT_REG_RS_SET_2_TO_0) +#define BITS_REG_RS_SET_2_TO_0 \ + (BIT_MASK_REG_RS_SET_2_TO_0 << BIT_SHIFT_REG_RS_SET_2_TO_0) +#define BIT_CLEAR_REG_RS_SET_2_TO_0(x) ((x) & (~BITS_REG_RS_SET_2_TO_0)) +#define BIT_GET_REG_RS_SET_2_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_RS_SET_2_TO_0) & BIT_MASK_REG_RS_SET_2_TO_0) +#define BIT_SET_REG_RS_SET_2_TO_0(x, v) \ + (BIT_CLEAR_REG_RS_SET_2_TO_0(x) | BIT_REG_RS_SET_2_TO_0(v)) + +#define BIT_SHIFT_REG_CS_SET_1_TO_0 18 +#define BIT_MASK_REG_CS_SET_1_TO_0 0x3 +#define BIT_REG_CS_SET_1_TO_0(x) \ + (((x) & BIT_MASK_REG_CS_SET_1_TO_0) << BIT_SHIFT_REG_CS_SET_1_TO_0) +#define BITS_REG_CS_SET_1_TO_0 \ + (BIT_MASK_REG_CS_SET_1_TO_0 << BIT_SHIFT_REG_CS_SET_1_TO_0) +#define BIT_CLEAR_REG_CS_SET_1_TO_0(x) ((x) & (~BITS_REG_CS_SET_1_TO_0)) +#define BIT_GET_REG_CS_SET_1_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_CS_SET_1_TO_0) & BIT_MASK_REG_CS_SET_1_TO_0) +#define BIT_SET_REG_CS_SET_1_TO_0(x, v) \ + (BIT_CLEAR_REG_CS_SET_1_TO_0(x) | BIT_REG_CS_SET_1_TO_0(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_REG_KVCO_200M_1_TO_0 5 -#define BIT_MASK_REG_KVCO_200M_1_TO_0 0x3 -#define BIT_REG_KVCO_200M_1_TO_0(x) (((x) & BIT_MASK_REG_KVCO_200M_1_TO_0) << BIT_SHIFT_REG_KVCO_200M_1_TO_0) -#define BIT_GET_REG_KVCO_200M_1_TO_0(x) (((x) >> BIT_SHIFT_REG_KVCO_200M_1_TO_0) & BIT_MASK_REG_KVCO_200M_1_TO_0) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_ZCD_CODE_IN_L 16 +#define BIT_MASK_ZCD_CODE_IN_L 0x1f +#define BIT_ZCD_CODE_IN_L(x) \ + (((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L) +#define BITS_ZCD_CODE_IN_L (BIT_MASK_ZCD_CODE_IN_L << BIT_SHIFT_ZCD_CODE_IN_L) +#define BIT_CLEAR_ZCD_CODE_IN_L(x) ((x) & (~BITS_ZCD_CODE_IN_L)) +#define BIT_GET_ZCD_CODE_IN_L(x) \ + (((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L) +#define BIT_SET_ZCD_CODE_IN_L(x, v) \ + (BIT_CLEAR_ZCD_CODE_IN_L(x) | BIT_ZCD_CODE_IN_L(v)) #endif - -#if (HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_TYPE_L_V1 BIT(5) - -#endif +#define BIT_SHIFT_REG_CP_SET_1_TO_0 16 +#define BIT_MASK_REG_CP_SET_1_TO_0 0x3 +#define BIT_REG_CP_SET_1_TO_0(x) \ + (((x) & BIT_MASK_REG_CP_SET_1_TO_0) << BIT_SHIFT_REG_CP_SET_1_TO_0) +#define BITS_REG_CP_SET_1_TO_0 \ + (BIT_MASK_REG_CP_SET_1_TO_0 << BIT_SHIFT_REG_CP_SET_1_TO_0) +#define BIT_CLEAR_REG_CP_SET_1_TO_0(x) ((x) & (~BITS_REG_CP_SET_1_TO_0)) +#define BIT_GET_REG_CP_SET_1_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_CP_SET_1_TO_0) & BIT_MASK_REG_CP_SET_1_TO_0) +#define BIT_SET_REG_CP_SET_1_TO_0(x, v) \ + (BIT_CLEAR_REG_CP_SET_1_TO_0(x) | BIT_REG_CP_SET_1_TO_0(v)) +#define BIT_LPFEN BIT(15) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_ARENB_L BIT(3) +#define BIT_SHIFT_LDO_HV5_DUMMY 14 +#define BIT_MASK_LDO_HV5_DUMMY 0x3 +#define BIT_LDO_HV5_DUMMY(x) \ + (((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY) +#define BITS_LDO_HV5_DUMMY (BIT_MASK_LDO_HV5_DUMMY << BIT_SHIFT_LDO_HV5_DUMMY) +#define BIT_CLEAR_LDO_HV5_DUMMY(x) ((x) & (~BITS_LDO_HV5_DUMMY)) +#define BIT_GET_LDO_HV5_DUMMY(x) \ + (((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY) +#define BIT_SET_LDO_HV5_DUMMY(x, v) \ + (BIT_CLEAR_LDO_HV5_DUMMY(x) | BIT_LDO_HV5_DUMMY(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_REG_DOGENB BIT(14) +#define BIT_REG_TEST_EN BIT(13) -#define BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0 2 -#define BIT_MASK_REG_CP_BIAS_200M_2_TO_0 0x7 -#define BIT_REG_CP_BIAS_200M_2_TO_0(x) (((x) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0) << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) -#define BIT_GET_REG_CP_BIAS_200M_2_TO_0(x) (((x) >> BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0) +#endif +#if (HALMAC_8192E_SUPPORT) -#endif +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_REG_VTUNE33 12 +#define BIT_MASK_REG_VTUNE33 0x3 +#define BIT_REG_VTUNE33(x) \ + (((x) & BIT_MASK_REG_VTUNE33) << BIT_SHIFT_REG_VTUNE33) +#define BITS_REG_VTUNE33 (BIT_MASK_REG_VTUNE33 << BIT_SHIFT_REG_VTUNE33) +#define BIT_CLEAR_REG_VTUNE33(x) ((x) & (~BITS_REG_VTUNE33)) +#define BIT_GET_REG_VTUNE33(x) \ + (((x) >> BIT_SHIFT_REG_VTUNE33) & BIT_MASK_REG_VTUNE33) +#define BIT_SET_REG_VTUNE33(x, v) \ + (BIT_CLEAR_REG_VTUNE33(x) | BIT_REG_VTUNE33(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12 +#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3 +#define BIT_REG_VTUNE33_BIT0_TO_BIT1(x) \ + (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) +#define BITS_REG_VTUNE33_BIT0_TO_BIT1 \ + (BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) +#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x) \ + ((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1)) +#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x) \ + (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) & \ + BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) +#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1(x, v) \ + (BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x) | \ + BIT_REG_VTUNE33_BIT0_TO_BIT1(v)) -#define BIT_SHIFT_CFC_L_BIT_1_TO_0 1 -#define BIT_MASK_CFC_L_BIT_1_TO_0 0x3 -#define BIT_CFC_L_BIT_1_TO_0(x) (((x) & BIT_MASK_CFC_L_BIT_1_TO_0) << BIT_SHIFT_CFC_L_BIT_1_TO_0) -#define BIT_GET_CFC_L_BIT_1_TO_0(x) (((x) >> BIT_SHIFT_CFC_L_BIT_1_TO_0) & BIT_MASK_CFC_L_BIT_1_TO_0) +#endif +#if (HALMAC_8192E_SUPPORT) -#endif +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_REG_STANDBY33 10 +#define BIT_MASK_REG_STANDBY33 0x3 +#define BIT_REG_STANDBY33(x) \ + (((x) & BIT_MASK_REG_STANDBY33) << BIT_SHIFT_REG_STANDBY33) +#define BITS_REG_STANDBY33 (BIT_MASK_REG_STANDBY33 << BIT_SHIFT_REG_STANDBY33) +#define BIT_CLEAR_REG_STANDBY33(x) ((x) & (~BITS_REG_STANDBY33)) +#define BIT_GET_REG_STANDBY33(x) \ + (((x) >> BIT_SHIFT_REG_STANDBY33) & BIT_MASK_REG_STANDBY33) +#define BIT_SET_REG_STANDBY33(x, v) \ + (BIT_CLEAR_REG_STANDBY33(x) | BIT_REG_STANDBY33(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10 +#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3 +#define BIT_REG_STANDBY33_BIT0_TO_BIT1(x) \ + (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) +#define BITS_REG_STANDBY33_BIT0_TO_BIT1 \ + (BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) +#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x) \ + ((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1)) +#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x) \ + (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) & \ + BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) +#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1(x, v) \ + (BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x) | \ + BIT_REG_STANDBY33_BIT0_TO_BIT1(v)) -#define BIT_SHIFT_CFC_L 1 -#define BIT_MASK_CFC_L 0x3 -#define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L) -#define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L) +#endif +#if (HALMAC_8192E_SUPPORT) -#endif +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_REG_LOAD33 8 +#define BIT_MASK_REG_LOAD33 0x3 +#define BIT_REG_LOAD33(x) (((x) & BIT_MASK_REG_LOAD33) << BIT_SHIFT_REG_LOAD33) +#define BITS_REG_LOAD33 (BIT_MASK_REG_LOAD33 << BIT_SHIFT_REG_LOAD33) +#define BIT_CLEAR_REG_LOAD33(x) ((x) & (~BITS_REG_LOAD33)) +#define BIT_GET_REG_LOAD33(x) \ + (((x) >> BIT_SHIFT_REG_LOAD33) & BIT_MASK_REG_LOAD33) +#define BIT_SET_REG_LOAD33(x, v) (BIT_CLEAR_REG_LOAD33(x) | BIT_REG_LOAD33(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_TYPE_L BIT(0) +#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8 +#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3 +#define BIT_REG_LOAD33_BIT0_TO_BIT1(x) \ + (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) \ + << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) +#define BITS_REG_LOAD33_BIT0_TO_BIT1 \ + (BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) +#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x) \ + ((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1)) +#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x) \ + (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) & \ + BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) +#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1(x, v) \ + (BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x) | BIT_REG_LOAD33_BIT0_TO_BIT1(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_XCK_OUT_EN BIT(0) +#define BIT_SHIFT_REG_DIV_SEL 8 +#define BIT_MASK_REG_DIV_SEL 0x1f +#define BIT_REG_DIV_SEL(x) \ + (((x) & BIT_MASK_REG_DIV_SEL) << BIT_SHIFT_REG_DIV_SEL) +#define BITS_REG_DIV_SEL (BIT_MASK_REG_DIV_SEL << BIT_SHIFT_REG_DIV_SEL) +#define BIT_CLEAR_REG_DIV_SEL(x) ((x) & (~BITS_REG_DIV_SEL)) +#define BIT_GET_REG_DIV_SEL(x) \ + (((x) >> BIT_SHIFT_REG_DIV_SEL) & BIT_MASK_REG_DIV_SEL) +#define BIT_SET_REG_DIV_SEL(x, v) \ + (BIT_CLEAR_REG_DIV_SEL(x) | BIT_REG_DIV_SEL(v)) #endif - -#if (HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_REG_OCPS_L_V1 BIT(0) +#define BIT_REG_BYPASS_L BIT(7) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_EN_CK200M BIT(7) -/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#endif -#define BIT_ANA_PORT_EN BIT(22) -#define BIT_MAC_PORT_EN BIT(21) -#define BIT_BOOT_FSPI_EN BIT(20) -#define BIT_FW_INIT_RDY BIT(15) -#define BIT_FW_DW_RDY BIT(14) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_REG_LDOF_L BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_8051FW_CTRL (Offset 0x0080) */ +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_FWDL_RSVDPAGE_RDY BIT(12) +#define BIT_REG_OCPS_L BIT(5) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_REG_KVCO_200M_1_TO_0 5 +#define BIT_MASK_REG_KVCO_200M_1_TO_0 0x3 +#define BIT_REG_KVCO_200M_1_TO_0(x) \ + (((x) & BIT_MASK_REG_KVCO_200M_1_TO_0) \ + << BIT_SHIFT_REG_KVCO_200M_1_TO_0) +#define BITS_REG_KVCO_200M_1_TO_0 \ + (BIT_MASK_REG_KVCO_200M_1_TO_0 << BIT_SHIFT_REG_KVCO_200M_1_TO_0) +#define BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) ((x) & (~BITS_REG_KVCO_200M_1_TO_0)) +#define BIT_GET_REG_KVCO_200M_1_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_KVCO_200M_1_TO_0) & \ + BIT_MASK_REG_KVCO_200M_1_TO_0) +#define BIT_SET_REG_KVCO_200M_1_TO_0(x, v) \ + (BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) | BIT_REG_KVCO_200M_1_TO_0(v)) -/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#endif +#if (HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_CPU_CLK_SEL 12 -#define BIT_MASK_CPU_CLK_SEL 0x3 -#define BIT_CPU_CLK_SEL(x) (((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL) -#define BIT_GET_CPU_CLK_SEL(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_REG_TYPE_L_V1 BIT(5) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_ARENB_L BIT(3) -/* 2 REG_8051FW_CTRL (Offset 0x0080) */ +#endif -#define BIT_R_8051_ROMDLFW_EN BIT(11) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0 2 +#define BIT_MASK_REG_CP_BIAS_200M_2_TO_0 0x7 +#define BIT_REG_CP_BIAS_200M_2_TO_0(x) \ + (((x) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0) \ + << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) +#define BITS_REG_CP_BIAS_200M_2_TO_0 \ + (BIT_MASK_REG_CP_BIAS_200M_2_TO_0 << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) +#define BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x) \ + ((x) & (~BITS_REG_CP_BIAS_200M_2_TO_0)) +#define BIT_GET_REG_CP_BIAS_200M_2_TO_0(x) \ + (((x) >> BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) & \ + BIT_MASK_REG_CP_BIAS_200M_2_TO_0) +#define BIT_SET_REG_CP_BIAS_200M_2_TO_0(x, v) \ + (BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x) | BIT_REG_CP_BIAS_200M_2_TO_0(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_CCLK_CHG_MASK BIT(11) +#define BIT_SHIFT_CFC_L_BIT_1_TO_0 1 +#define BIT_MASK_CFC_L_BIT_1_TO_0 0x3 +#define BIT_CFC_L_BIT_1_TO_0(x) \ + (((x) & BIT_MASK_CFC_L_BIT_1_TO_0) << BIT_SHIFT_CFC_L_BIT_1_TO_0) +#define BITS_CFC_L_BIT_1_TO_0 \ + (BIT_MASK_CFC_L_BIT_1_TO_0 << BIT_SHIFT_CFC_L_BIT_1_TO_0) +#define BIT_CLEAR_CFC_L_BIT_1_TO_0(x) ((x) & (~BITS_CFC_L_BIT_1_TO_0)) +#define BIT_GET_CFC_L_BIT_1_TO_0(x) \ + (((x) >> BIT_SHIFT_CFC_L_BIT_1_TO_0) & BIT_MASK_CFC_L_BIT_1_TO_0) +#define BIT_SET_CFC_L_BIT_1_TO_0(x, v) \ + (BIT_CLEAR_CFC_L_BIT_1_TO_0(x) | BIT_CFC_L_BIT_1_TO_0(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_SHIFT_CFC_L 1 +#define BIT_MASK_CFC_L 0x3 +#define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L) +#define BITS_CFC_L (BIT_MASK_CFC_L << BIT_SHIFT_CFC_L) +#define BIT_CLEAR_CFC_L(x) ((x) & (~BITS_CFC_L)) +#define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L) +#define BIT_SET_CFC_L(x, v) (BIT_CLEAR_CFC_L(x) | BIT_CFC_L(v)) -/* 2 REG_8051FW_CTRL (Offset 0x0080) */ +#endif -#define BIT_R_8051_INIT_RDY BIT(10) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_REG_TYPE_L BIT(0) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ -#define BIT_FW_INIT_RDY_V1 BIT(10) +#define BIT_XCK_OUT_EN BIT(0) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ +#define BIT_REG_OCPS_L_V1 BIT(0) -/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#endif -#define BIT_EMEM_TXBUF_CHKSUM_OK BIT(10) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#define BIT_MCUSUS_EN BIT(23) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10) +#define BIT_ANA_PORT_EN BIT(22) +#define BIT_MAC_PORT_EN BIT(21) +#define BIT_BOOT_FSPI_EN BIT(20) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ + +#define BIT_SHIFT_MCUROM_DL 16 +#define BIT_MASK_MCUROM_DL 0xf +#define BIT_MCUROM_DL(x) (((x) & BIT_MASK_MCUROM_DL) << BIT_SHIFT_MCUROM_DL) +#define BITS_MCUROM_DL (BIT_MASK_MCUROM_DL << BIT_SHIFT_MCUROM_DL) +#define BIT_CLEAR_MCUROM_DL(x) ((x) & (~BITS_MCUROM_DL)) +#define BIT_GET_MCUROM_DL(x) (((x) >> BIT_SHIFT_MCUROM_DL) & BIT_MASK_MCUROM_DL) +#define BIT_SET_MCUROM_DL(x, v) (BIT_CLEAR_MCUROM_DL(x) | BIT_MCUROM_DL(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_EMEM_TXBUF_DW_RDY BIT(9) +#define BIT_WMAC_SRCH_FIFOFULL BIT(15) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#define BIT_FW_INIT_RDY BIT(15) -/* 2 REG_8051FW_CTRL (Offset 0x0080) */ +#endif -#define BIT_R_8051_GAT BIT(8) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#define BIT_SHIFT_MCUFWDL_DMA_2KB_SEL 14 +#define BIT_MASK_MCUFWDL_DMA_2KB_SEL 0x3 +#define BIT_MCUFWDL_DMA_2KB_SEL(x) \ + (((x) & BIT_MASK_MCUFWDL_DMA_2KB_SEL) << BIT_SHIFT_MCUFWDL_DMA_2KB_SEL) +#define BITS_MCUFWDL_DMA_2KB_SEL \ + (BIT_MASK_MCUFWDL_DMA_2KB_SEL << BIT_SHIFT_MCUFWDL_DMA_2KB_SEL) +#define BIT_CLEAR_MCUFWDL_DMA_2KB_SEL(x) ((x) & (~BITS_MCUFWDL_DMA_2KB_SEL)) +#define BIT_GET_MCUFWDL_DMA_2KB_SEL(x) \ + (((x) >> BIT_SHIFT_MCUFWDL_DMA_2KB_SEL) & BIT_MASK_MCUFWDL_DMA_2KB_SEL) +#define BIT_SET_MCUFWDL_DMA_2KB_SEL(x, v) \ + (BIT_CLEAR_MCUFWDL_DMA_2KB_SEL(x) | BIT_MCUFWDL_DMA_2KB_SEL(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_MCU_CLK_EN BIT(8) +#define BIT_FW_DW_RDY BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_8051FW_CTRL (Offset 0x0080) */ + +#define BIT_FWDL_RSVDPAGE_RDY BIT(12) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_EMEM_CHKSUM_OK BIT(8) -#define BIT_EMEM_DW_OK BIT(7) -#define BIT_TOGGLING BIT(7) -#define BIT_DMEM_CHKSUM_OK BIT(6) -#define BIT_ACK BIT(6) +#define BIT_SHIFT_CPU_CLK_SEL 12 +#define BIT_MASK_CPU_CLK_SEL 0x3 +#define BIT_CPU_CLK_SEL(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL) +#define BITS_CPU_CLK_SEL (BIT_MASK_CPU_CLK_SEL << BIT_SHIFT_CPU_CLK_SEL) +#define BIT_CLEAR_CPU_CLK_SEL(x) ((x) & (~BITS_CPU_CLK_SEL)) +#define BIT_GET_CPU_CLK_SEL(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL) +#define BIT_SET_CPU_CLK_SEL(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL(x) | BIT_CPU_CLK_SEL(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_RFINI_RDY BIT(5) +#define BIT_R_8051_ROMDLFW_EN BIT(11) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ + +#define BIT_MCUFWDL_DMA_EN BIT(11) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_RF_INIT_RDY BIT(5) +#define BIT_CCLK_CHG_MASK BIT(11) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_8051FW_CTRL (Offset 0x0080) */ + +#define BIT_R_8051_INIT_RDY BIT(10) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_DMEM_DW_OK BIT(5) +#define BIT_MCUINI_WROMRDY BIT(10) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#define BIT_FW_INIT_RDY_V1 BIT(10) -/* 2 REG_8051FW_CTRL (Offset 0x0080) */ +#endif -#define BIT_BBINI_RDY BIT(4) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_BB_INIT_RDY BIT(4) +#define BIT_EMEM_TXBUF_CHKSUM_OK BIT(10) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ + +#define BIT_MCUTXA_SPD BIT(9) + +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_IMEM_CHKSUM_OK BIT(4) +#define BIT_EMEM_TXBUF_DW_RDY BIT(9) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_MACINI_RDY BIT(3) +#define BIT_R_8051_GAT BIT(8) #endif - -#if (HALMAC_8197F_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_MAC_INIT_RDY BIT(3) +#define BIT_MCUCLK_TEN BIT(8) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ + +#define BIT_MCU_CLK_EN BIT(8) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_IMEM_DW_OK BIT(3) +#define BIT_EMEM_CHKSUM_OK BIT(8) +#define BIT_EMEM_DW_OK BIT(7) +#define BIT_TOGGLE BIT(7) +#define BIT_DMEM_CHKSUM_OK BIT(6) +#define BIT_ACK BIT(6) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_FWDL_CHK_RPT BIT(2) +#define BIT_RFINI_RDY BIT(5) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ + +#define BIT_MCUINI_WRFCRDY BIT(5) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2) +#define BIT_RF_INIT_RDY BIT(5) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#define BIT_DMEM_DW_OK BIT(5) -/* 2 REG_8051FW_CTRL (Offset 0x0080) */ +#endif -#define BIT_MCUFWDL_RDY BIT(1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_8051FW_CTRL (Offset 0x0080) */ +#define BIT_BBINI_RDY BIT(4) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_MCU_FWDL_RDY BIT(1) +#define BIT_MCUINI_WPHYRDY BIT(4) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ + +#define BIT_BB_INIT_RDY BIT(4) + +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1) +#define BIT_IMEM_CHKSUM_OK BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_8051FW_CTRL (Offset 0x0080) */ +#define BIT_MACINI_RDY BIT(3) -/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#endif -#define BIT_MCU_FWDL_EN BIT(0) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#define BIT_MCUINI_WMACRDY BIT(3) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */ +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ -#define BIT_32K_PERMISSION BIT(0) +#define BIT_MAC_INIT_RDY BIT(3) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#define BIT_IMEM_DW_OK BIT(3) -/* 2 REG_MCU_TST_CFG (Offset 0x0084) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LBKTST 0 -#define BIT_MASK_LBKTST 0xffff -#define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST) -#define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST) +/* 2 REG_8051FW_CTRL (Offset 0x0080) */ +#define BIT_FWDL_CHK_RPT BIT(2) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2) -/* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ +#endif -#define BIT_PAD_CLK_XHGE_EN BIT(3) -#define BIT_INTER_CLK_EN BIT(2) -#define BIT_EN_RPT_TXCRC BIT(1) -#define BIT_DIS_RXDMA_STS BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ +/* 2 REG_8051FW_CTRL (Offset 0x0080) */ -#define BIT_INTR_CTRL BIT(4) -#define BIT_SDIO_VOLTAGE BIT(3) -#define BIT_BYPASS_INIT BIT(2) +#define BIT_MCUFWDL_RDY BIT(1) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1) -/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ +#endif -#define BIT_HCI_RESUME_RDY BIT(1) -#define BIT_HCI_SUS_REQ BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_MCUFW_CTRL (Offset 0x0080) */ +#define BIT_MCU_FWDL_RDY BIT(1) +#define BIT_MCU_FWDL_EN BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */ +/* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */ +#define BIT_REQ_PS BIT(0) -#define BIT_SHIFT_HOST_MSG_E1 16 -#define BIT_MASK_HOST_MSG_E1 0xffff -#define BIT_HOST_MSG_E1(x) (((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1) -#define BIT_GET_HOST_MSG_E1(x) (((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_HOST_MSG_E0 0 -#define BIT_MASK_HOST_MSG_E0 0xffff -#define BIT_HOST_MSG_E0(x) (((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0) -#define BIT_GET_HOST_MSG_E0(x) (((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0) +/* 2 REG_MCU_TST_CFG (Offset 0x0084) */ +#define BIT_SHIFT_8051CODE_OFS 16 +#define BIT_MASK_8051CODE_OFS 0xffff +#define BIT_8051CODE_OFS(x) \ + (((x) & BIT_MASK_8051CODE_OFS) << BIT_SHIFT_8051CODE_OFS) +#define BITS_8051CODE_OFS (BIT_MASK_8051CODE_OFS << BIT_SHIFT_8051CODE_OFS) +#define BIT_CLEAR_8051CODE_OFS(x) ((x) & (~BITS_8051CODE_OFS)) +#define BIT_GET_8051CODE_OFS(x) \ + (((x) >> BIT_SHIFT_8051CODE_OFS) & BIT_MASK_8051CODE_OFS) +#define BIT_SET_8051CODE_OFS(x, v) \ + (BIT_CLEAR_8051CODE_OFS(x) | BIT_8051CODE_OFS(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MCU_TST_CFG (Offset 0x0084) */ +#define BIT_SHIFT_LBKTST 0 +#define BIT_MASK_LBKTST 0xffff +#define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST) +#define BITS_LBKTST (BIT_MASK_LBKTST << BIT_SHIFT_LBKTST) +#define BIT_CLEAR_LBKTST(x) ((x) & (~BITS_LBKTST)) +#define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST) +#define BIT_SET_LBKTST(x, v) (BIT_CLEAR_LBKTST(x) | BIT_LBKTST(v)) -/* 2 REG_SDIO_RESPONSE_TIMER (Offset 0x10250088) */ +#endif +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_CMDIN_2RESP_TIMER 0 -#define BIT_MASK_CMDIN_2RESP_TIMER 0xffff -#define BIT_CMDIN_2RESP_TIMER(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER) -#define BIT_GET_CMDIN_2RESP_TIMER(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER) +/* 2 REG_MCU_TST_CFG (Offset 0x0084) */ +#define BIT_SHIFT_C2H_MSG 0 +#define BIT_MASK_C2H_MSG 0xffff +#define BIT_C2H_MSG(x) (((x) & BIT_MASK_C2H_MSG) << BIT_SHIFT_C2H_MSG) +#define BITS_C2H_MSG (BIT_MASK_C2H_MSG << BIT_SHIFT_C2H_MSG) +#define BIT_CLEAR_C2H_MSG(x) ((x) & (~BITS_C2H_MSG)) +#define BIT_GET_C2H_MSG(x) (((x) >> BIT_SHIFT_C2H_MSG) & BIT_MASK_C2H_MSG) +#define BIT_SET_C2H_MSG(x, v) (BIT_CLEAR_C2H_MSG(x) | BIT_C2H_MSG(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ +#define BIT_INT_MASK_DIS BIT(4) -/* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SDIO_CMD_CRC 1 -#define BIT_MASK_SDIO_CMD_CRC 0x7f -#define BIT_SDIO_CMD_CRC(x) (((x) & BIT_MASK_SDIO_CMD_CRC) << BIT_SHIFT_SDIO_CMD_CRC) -#define BIT_GET_SDIO_CMD_CRC(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC) & BIT_MASK_SDIO_CMD_CRC) +/* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ -#define BIT_SDIO_CMD_E_BIT BIT(0) +#define BIT_PAD_CLK_XHGE_EN BIT(3) +#define BIT_INTER_CLK_EN BIT(2) +#define BIT_EN_RPT_TXCRC BIT(1) +#define BIT_DIS_RXDMA_STS BIT(0) #endif +#if (HALMAC_8812F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ +#define BIT_SPI_PHASE BIT(5) -/* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SDIO_CMD_CRC_V1 0 -#define BIT_MASK_SDIO_CMD_CRC_V1 0xff -#define BIT_SDIO_CMD_CRC_V1(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1) -#define BIT_GET_SDIO_CMD_CRC_V1(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1) +/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ +#define BIT_INTR_CTRL BIT(4) +#define BIT_SDIO_VOLTAGE BIT(3) +#define BIT_BYPASS_INIT BIT(2) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ +#define BIT_HCI_RESUME_RDY BIT(1) +#define BIT_HCI_SUS_REQ BIT(0) -/* 2 REG_HMEBOX_E2_E3 (Offset 0x008C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HOST_MSG_E3 16 -#define BIT_MASK_HOST_MSG_E3 0xffff -#define BIT_HOST_MSG_E3(x) (((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3) -#define BIT_GET_HOST_MSG_E3(x) (((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3) +/* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */ +#define BIT_SHIFT_HOST_MSG_E1 16 +#define BIT_MASK_HOST_MSG_E1 0xffff +#define BIT_HOST_MSG_E1(x) \ + (((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1) +#define BITS_HOST_MSG_E1 (BIT_MASK_HOST_MSG_E1 << BIT_SHIFT_HOST_MSG_E1) +#define BIT_CLEAR_HOST_MSG_E1(x) ((x) & (~BITS_HOST_MSG_E1)) +#define BIT_GET_HOST_MSG_E1(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1) +#define BIT_SET_HOST_MSG_E1(x, v) \ + (BIT_CLEAR_HOST_MSG_E1(x) | BIT_HOST_MSG_E1(v)) + +#define BIT_SHIFT_HOST_MSG_E0 0 +#define BIT_MASK_HOST_MSG_E0 0xffff +#define BIT_HOST_MSG_E0(x) \ + (((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0) +#define BITS_HOST_MSG_E0 (BIT_MASK_HOST_MSG_E0 << BIT_SHIFT_HOST_MSG_E0) +#define BIT_CLEAR_HOST_MSG_E0(x) ((x) & (~BITS_HOST_MSG_E0)) +#define BIT_GET_HOST_MSG_E0(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0) +#define BIT_SET_HOST_MSG_E0(x, v) \ + (BIT_CLEAR_HOST_MSG_E0(x) | BIT_HOST_MSG_E0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HOST_MSG_E2 0 -#define BIT_MASK_HOST_MSG_E2 0xffff -#define BIT_HOST_MSG_E2(x) (((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2) -#define BIT_GET_HOST_MSG_E2(x) (((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2) +/* 2 REG_SDIO_RESPONSE_TIMER (Offset 0x10250088) */ +#define BIT_SHIFT_CMDIN_2RESP_TIMER 0 +#define BIT_MASK_CMDIN_2RESP_TIMER 0xffff +#define BIT_CMDIN_2RESP_TIMER(x) \ + (((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER) +#define BITS_CMDIN_2RESP_TIMER \ + (BIT_MASK_CMDIN_2RESP_TIMER << BIT_SHIFT_CMDIN_2RESP_TIMER) +#define BIT_CLEAR_CMDIN_2RESP_TIMER(x) ((x) & (~BITS_CMDIN_2RESP_TIMER)) +#define BIT_GET_CMDIN_2RESP_TIMER(x) \ + (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER) +#define BIT_SET_CMDIN_2RESP_TIMER(x, v) \ + (BIT_CLEAR_CMDIN_2RESP_TIMER(x) | BIT_CMDIN_2RESP_TIMER(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ +#define BIT_SHIFT_SDIO_CMD_CRC 1 +#define BIT_MASK_SDIO_CMD_CRC 0x7f +#define BIT_SDIO_CMD_CRC(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC) << BIT_SHIFT_SDIO_CMD_CRC) +#define BITS_SDIO_CMD_CRC (BIT_MASK_SDIO_CMD_CRC << BIT_SHIFT_SDIO_CMD_CRC) +#define BIT_CLEAR_SDIO_CMD_CRC(x) ((x) & (~BITS_SDIO_CMD_CRC)) +#define BIT_GET_SDIO_CMD_CRC(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC) & BIT_MASK_SDIO_CMD_CRC) +#define BIT_SET_SDIO_CMD_CRC(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC(x) | BIT_SDIO_CMD_CRC(v)) -/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#endif -#define BIT_WLLPSOP_EABM BIT(31) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ +#define BIT_SHIFT_SDIO_CMD_CRC_V1 0 +#define BIT_MASK_SDIO_CMD_CRC_V1 0xff +#define BIT_SDIO_CMD_CRC_V1(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1) +#define BITS_SDIO_CMD_CRC_V1 \ + (BIT_MASK_SDIO_CMD_CRC_V1 << BIT_SHIFT_SDIO_CMD_CRC_V1) +#define BIT_CLEAR_SDIO_CMD_CRC_V1(x) ((x) & (~BITS_SDIO_CMD_CRC_V1)) +#define BIT_GET_SDIO_CMD_CRC_V1(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1) +#define BIT_SET_SDIO_CMD_CRC_V1(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC_V1(x) | BIT_SDIO_CMD_CRC_V1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +/* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ -#define BIT_WLLPSOP_ACKF BIT(30) +#define BIT_SDIO_CMD_E_BIT BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HMEBOX_E2_E3 (Offset 0x008C) */ +#define BIT_SHIFT_HOST_MSG_E3 16 +#define BIT_MASK_HOST_MSG_E3 0xffff +#define BIT_HOST_MSG_E3(x) \ + (((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3) +#define BITS_HOST_MSG_E3 (BIT_MASK_HOST_MSG_E3 << BIT_SHIFT_HOST_MSG_E3) +#define BIT_CLEAR_HOST_MSG_E3(x) ((x) & (~BITS_HOST_MSG_E3)) +#define BIT_GET_HOST_MSG_E3(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3) +#define BIT_SET_HOST_MSG_E3(x, v) \ + (BIT_CLEAR_HOST_MSG_E3(x) | BIT_HOST_MSG_E3(v)) + +#define BIT_SHIFT_HOST_MSG_E2 0 +#define BIT_MASK_HOST_MSG_E2 0xffff +#define BIT_HOST_MSG_E2(x) \ + (((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2) +#define BITS_HOST_MSG_E2 (BIT_MASK_HOST_MSG_E2 << BIT_SHIFT_HOST_MSG_E2) +#define BIT_CLEAR_HOST_MSG_E2(x) ((x) & (~BITS_HOST_MSG_E2)) +#define BIT_GET_HOST_MSG_E2(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2) +#define BIT_SET_HOST_MSG_E2(x, v) \ + (BIT_CLEAR_HOST_MSG_E2(x) | BIT_HOST_MSG_E2(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_DLDM BIT(29) +#define BIT_WLLPSOP_EABM BIT(31) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ + +#define BIT_WLLPSOP_ACKF BIT(30) + +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_AFEP BIT(29) +#define BIT_TXFIFO_TH_INT BIT(30) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ + +#define BIT_WLLPSOP_DLDM BIT(29) + +#endif +#if (HALMAC_8192F_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_ESWR BIT(28) +#define BIT_WLLPSOP_NODS BIT(29) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_LPS_DIS_SW BIT(28) +#define BIT_WLLPSOP_AFEP BIT(29) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_PWMM BIT(27) -#define BIT_WLLPSOP_EECK BIT(26) +#define BIT_WLLPSOP_ESWR BIT(28) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_ELDO BIT(25) +#define BIT_LPS_DIS_SW BIT(28) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_WLMACOFF BIT(25) +#define BIT_WLLPSOP_PWMM BIT(27) +#define BIT_WLLPSOP_EECK BIT(26) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ + +#define BIT_WLLPSOP_WLPON BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_EXTAL BIT(24) +#define BIT_WLLPSOP_WLMACOFF BIT(25) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_LPS_BB_REG_EN BIT(23) +#define BIT_WLLPSOP_ELDO BIT(25) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ + +#define BIT_WLLPSOP_EXTAL BIT(24) + +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WL_SYNPON_VOLTSPDN BIT(23) +#define BIT_WL_SYNPON_VOLTSPDN BIT(23) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_LPS_BB_PWR_EN BIT(22) +#define BIT_LPS_BB_REG_EN BIT(23) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_LOP_SKIP BIT(22) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_WLBBOFF BIT(22) +#define BIT_WLLPSOP_WLBBOFF BIT(22) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_LPS_BB_GLB_EN BIT(21) +#define BIT_LPS_BB_PWR_EN BIT(22) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WLLPSOP_WLMEM_DS BIT(21) +#define BIT_LOP_MEMDS BIT(21) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_SUS_DIS_SW BIT(15) -#define BIT_SUS_SKP_PAGE0_ALD BIT(14) -#define BIT_SUS_LDO_SLEEP BIT(13) -#define BIT_PFM_EN_ZCD BIT(12) +#define BIT_WLLPSOP_WLMEM_DS BIT(21) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_LPS_BB_GLB_EN BIT(21) -/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12 -#define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf -#define BIT_LPLDH12_VADJ_STEP_DN(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN) -#define BIT_GET_LPLDH12_VADJ_STEP_DN(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) & BIT_MASK_LPLDH12_VADJ_STEP_DN) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_WLLPSOP_LDO_WAIT_TIME BIT(20) +#define BIT_WLLPSOP_ANA_CLK_DIVISION_2 BIT(19) +#define BIT_AFE_BCN BIT(18) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_KEEP_RFC_EN BIT(11) -#define BIT_MACON_NO_RFCISO_RELEASE BIT(10) -#define BIT_MACON_NO_AFEPORT_PWR BIT(9) -#define BIT_MACON_NO_CPU_EN BIT(8) +#define BIT_SUS_DIS_SW BIT(15) +#define BIT_SUS_SKP_PAGE0_ALD BIT(14) +#define BIT_SUS_LDO_SLEEP BIT(13) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12 +#define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf +#define BIT_LPLDH12_VADJ_STEP_DN(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN) \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN) +#define BITS_LPLDH12_VADJ_STEP_DN \ + (BIT_MASK_LPLDH12_VADJ_STEP_DN << BIT_SHIFT_LPLDH12_VADJ_STEP_DN) +#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) ((x) & (~BITS_LPLDH12_VADJ_STEP_DN)) +#define BIT_GET_LPLDH12_VADJ_STEP_DN(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) & \ + BIT_MASK_LPLDH12_VADJ_STEP_DN) +#define BIT_SET_LPLDH12_VADJ_STEP_DN(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) | BIT_LPLDH12_VADJ_STEP_DN(v)) -#define BIT_SHIFT_V15ADJ_L1_STEP_DN 8 -#define BIT_MASK_V15ADJ_L1_STEP_DN 0x7 -#define BIT_V15ADJ_L1_STEP_DN(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN) -#define BIT_GET_V15ADJ_L1_STEP_DN(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN) +#endif -#define BIT_REGU_32K_CLK_EN BIT(1) -#define BIT_DRV_WLAN_INT_CLR BIT(1) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_PFM_EN_ZCD BIT(12) +#define BIT_KEEP_RFC_EN BIT(11) +#define BIT_MACON_NO_RFCISO_RELEASE BIT(10) +#define BIT_MACON_NO_AFEPORT_PWR BIT(9) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_WL_LPS_EN BIT(0) +#define BIT_SHIFT_V15ADJ_L1_STEP_DN 8 +#define BIT_MASK_V15ADJ_L1_STEP_DN 0x7 +#define BIT_V15ADJ_L1_STEP_DN(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN) +#define BITS_V15ADJ_L1_STEP_DN \ + (BIT_MASK_V15ADJ_L1_STEP_DN << BIT_SHIFT_V15ADJ_L1_STEP_DN) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN)) +#define BIT_GET_V15ADJ_L1_STEP_DN(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN) +#define BIT_SET_V15ADJ_L1_STEP_DN(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN(x) | BIT_V15ADJ_L1_STEP_DN(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_SHIFT_V15ADJ_L1_STEP_DN_V1 8 +#define BIT_MASK_V15ADJ_L1_STEP_DN_V1 0xf +#define BIT_V15ADJ_L1_STEP_DN_V1(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_V1) \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) +#define BITS_V15ADJ_L1_STEP_DN_V1 \ + (BIT_MASK_V15ADJ_L1_STEP_DN_V1 << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN_V1)) +#define BIT_GET_V15ADJ_L1_STEP_DN_V1(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) & \ + BIT_MASK_V15ADJ_L1_STEP_DN_V1) +#define BIT_SET_V15ADJ_L1_STEP_DN_V1(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) | BIT_V15ADJ_L1_STEP_DN_V1(v)) -/* 2 REG_SDIO_HSISR (Offset 0x10250090) */ +#endif -#define BIT_DRV_WLAN_INT BIT(0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_SDIO_HSIMR (Offset 0x10250091) */ +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_HISR_MASK BIT(0) +#define BIT_MACON_NO_CPU_EN BIT(8) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_LD_B15V_EN BIT(7) +#define BIT_LPRX_BCN_EN BIT(5) +#define BIT_LBN BIT(4) +#define BIT_LXSPS_UNUSED BIT(3) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif -#define BIT_BB_DBG_SEL_AFE_SDM_V3 BIT(31) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_FORCE_LEAVE_LPS BIT(3) +#define BIT_SW_AFE_MODE BIT(2) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ -#define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31) +#define BIT_REGU_32K_CLK_EN BIT(1) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SDIO_HSISR (Offset 0x10250090) */ +#define BIT_DRV_WLAN_INT_CLR BIT(1) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif -#define BIT_ORDER_SDM BIT(30) -#define BIT_RFE_SEL_SDM BIT(29) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_REF_SEL 25 -#define BIT_MASK_REF_SEL 0xf -#define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL) -#define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL) +/* 2 REG_WLLPS_CTRL (Offset 0x0090) */ +#define BIT_WL_LPS_EN BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SDIO_HSISR (Offset 0x10250090) */ +#define BIT_DRV_WLAN_INT BIT(0) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_F0F_SDM_V2 12 -#define BIT_MASK_F0F_SDM_V2 0x1fff -#define BIT_F0F_SDM_V2(x) (((x) & BIT_MASK_F0F_SDM_V2) << BIT_SHIFT_F0F_SDM_V2) -#define BIT_GET_F0F_SDM_V2(x) (((x) >> BIT_SHIFT_F0F_SDM_V2) & BIT_MASK_F0F_SDM_V2) +/* 2 REG_SDIO_HSIMR (Offset 0x10250091) */ +#define BIT_HISR_MASK BIT(0) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_BB_DBG_SEL_AFE_SDM_V3 BIT(31) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_F0F_SDM 12 -#define BIT_MASK_F0F_SDM 0x1fff -#define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM) -#define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_ORDER_SDM BIT(30) +#define BIT_RFE_SEL_SDM BIT(29) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_REF_SEL 25 +#define BIT_MASK_REF_SEL 0xf +#define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL) +#define BITS_REF_SEL (BIT_MASK_REF_SEL << BIT_SHIFT_REF_SEL) +#define BIT_CLEAR_REF_SEL(x) ((x) & (~BITS_REF_SEL)) +#define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL) +#define BIT_SET_REF_SEL(x, v) (BIT_CLEAR_REF_SEL(x) | BIT_REF_SEL(v)) + +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_F0N_SDM_V2 9 -#define BIT_MASK_F0N_SDM_V2 0x7 -#define BIT_F0N_SDM_V2(x) (((x) & BIT_MASK_F0N_SDM_V2) << BIT_SHIFT_F0N_SDM_V2) -#define BIT_GET_F0N_SDM_V2(x) (((x) >> BIT_SHIFT_F0N_SDM_V2) & BIT_MASK_F0N_SDM_V2) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_F0F_SDM_V2 12 +#define BIT_MASK_F0F_SDM_V2 0x1fff +#define BIT_F0F_SDM_V2(x) (((x) & BIT_MASK_F0F_SDM_V2) << BIT_SHIFT_F0F_SDM_V2) +#define BITS_F0F_SDM_V2 (BIT_MASK_F0F_SDM_V2 << BIT_SHIFT_F0F_SDM_V2) +#define BIT_CLEAR_F0F_SDM_V2(x) ((x) & (~BITS_F0F_SDM_V2)) +#define BIT_GET_F0F_SDM_V2(x) \ + (((x) >> BIT_SHIFT_F0F_SDM_V2) & BIT_MASK_F0F_SDM_V2) +#define BIT_SET_F0F_SDM_V2(x, v) (BIT_CLEAR_F0F_SDM_V2(x) | BIT_F0F_SDM_V2(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_F0F_SDM 12 +#define BIT_MASK_F0F_SDM 0x1fff +#define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM) +#define BITS_F0F_SDM (BIT_MASK_F0F_SDM << BIT_SHIFT_F0F_SDM) +#define BIT_CLEAR_F0F_SDM(x) ((x) & (~BITS_F0F_SDM)) +#define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM) +#define BIT_SET_F0F_SDM(x, v) (BIT_CLEAR_F0F_SDM(x) | BIT_F0F_SDM(v)) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_F0N_SDM 9 -#define BIT_MASK_F0N_SDM 0x7 -#define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM) -#define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_F0N_SDM_V2 9 +#define BIT_MASK_F0N_SDM_V2 0x7 +#define BIT_F0N_SDM_V2(x) (((x) & BIT_MASK_F0N_SDM_V2) << BIT_SHIFT_F0N_SDM_V2) +#define BITS_F0N_SDM_V2 (BIT_MASK_F0N_SDM_V2 << BIT_SHIFT_F0N_SDM_V2) +#define BIT_CLEAR_F0N_SDM_V2(x) ((x) & (~BITS_F0N_SDM_V2)) +#define BIT_GET_F0N_SDM_V2(x) \ + (((x) >> BIT_SHIFT_F0N_SDM_V2) & BIT_MASK_F0N_SDM_V2) +#define BIT_SET_F0N_SDM_V2(x, v) (BIT_CLEAR_F0N_SDM_V2(x) | BIT_F0N_SDM_V2(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_F0N_SDM 9 +#define BIT_MASK_F0N_SDM 0x7 +#define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM) +#define BITS_F0N_SDM (BIT_MASK_F0N_SDM << BIT_SHIFT_F0N_SDM) +#define BIT_CLEAR_F0N_SDM(x) ((x) & (~BITS_F0N_SDM)) +#define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM) +#define BIT_SET_F0N_SDM(x, v) (BIT_CLEAR_F0N_SDM(x) | BIT_F0N_SDM(v)) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_DIVN_SDM_V2 3 -#define BIT_MASK_DIVN_SDM_V2 0x3f -#define BIT_DIVN_SDM_V2(x) (((x) & BIT_MASK_DIVN_SDM_V2) << BIT_SHIFT_DIVN_SDM_V2) -#define BIT_GET_DIVN_SDM_V2(x) (((x) >> BIT_SHIFT_DIVN_SDM_V2) & BIT_MASK_DIVN_SDM_V2) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_DIVN_SDM_V2 3 +#define BIT_MASK_DIVN_SDM_V2 0x3f +#define BIT_DIVN_SDM_V2(x) \ + (((x) & BIT_MASK_DIVN_SDM_V2) << BIT_SHIFT_DIVN_SDM_V2) +#define BITS_DIVN_SDM_V2 (BIT_MASK_DIVN_SDM_V2 << BIT_SHIFT_DIVN_SDM_V2) +#define BIT_CLEAR_DIVN_SDM_V2(x) ((x) & (~BITS_DIVN_SDM_V2)) +#define BIT_GET_DIVN_SDM_V2(x) \ + (((x) >> BIT_SHIFT_DIVN_SDM_V2) & BIT_MASK_DIVN_SDM_V2) +#define BIT_SET_DIVN_SDM_V2(x, v) \ + (BIT_CLEAR_DIVN_SDM_V2(x) | BIT_DIVN_SDM_V2(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_DIVN_SDM 3 +#define BIT_MASK_DIVN_SDM 0x3f +#define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM) +#define BITS_DIVN_SDM (BIT_MASK_DIVN_SDM << BIT_SHIFT_DIVN_SDM) +#define BIT_CLEAR_DIVN_SDM(x) ((x) & (~BITS_DIVN_SDM)) +#define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM) +#define BIT_SET_DIVN_SDM(x, v) (BIT_CLEAR_DIVN_SDM(x) | BIT_DIVN_SDM(v)) -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_DIVN_SDM 3 -#define BIT_MASK_DIVN_SDM 0x3f -#define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM) -#define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM) +/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_SHIFT_DITHER_SDM_V2 0 +#define BIT_MASK_DITHER_SDM_V2 0x7 +#define BIT_DITHER_SDM_V2(x) \ + (((x) & BIT_MASK_DITHER_SDM_V2) << BIT_SHIFT_DITHER_SDM_V2) +#define BITS_DITHER_SDM_V2 (BIT_MASK_DITHER_SDM_V2 << BIT_SHIFT_DITHER_SDM_V2) +#define BIT_CLEAR_DITHER_SDM_V2(x) ((x) & (~BITS_DITHER_SDM_V2)) +#define BIT_GET_DITHER_SDM_V2(x) \ + (((x) >> BIT_SHIFT_DITHER_SDM_V2) & BIT_MASK_DITHER_SDM_V2) +#define BIT_SET_DITHER_SDM_V2(x, v) \ + (BIT_CLEAR_DITHER_SDM_V2(x) | BIT_DITHER_SDM_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */ -/* 2 REG_AFE_CTRL5 (Offset 0x0094) */ +#define BIT_WLGP_DBC1EN BIT(15) +#define BIT_SHIFT_WLGP_DBC1 8 +#define BIT_MASK_WLGP_DBC1 0xf +#define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1) +#define BITS_WLGP_DBC1 (BIT_MASK_WLGP_DBC1 << BIT_SHIFT_WLGP_DBC1) +#define BIT_CLEAR_WLGP_DBC1(x) ((x) & (~BITS_WLGP_DBC1)) +#define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1) +#define BIT_SET_WLGP_DBC1(x, v) (BIT_CLEAR_WLGP_DBC1(x) | BIT_WLGP_DBC1(v)) -#define BIT_SHIFT_DITHER_SDM_V2 0 -#define BIT_MASK_DITHER_SDM_V2 0x7 -#define BIT_DITHER_SDM_V2(x) (((x) & BIT_MASK_DITHER_SDM_V2) << BIT_SHIFT_DITHER_SDM_V2) -#define BIT_GET_DITHER_SDM_V2(x) (((x) >> BIT_SHIFT_DITHER_SDM_V2) & BIT_MASK_DITHER_SDM_V2) +#define BIT_WLGP_DBC0EN BIT(7) +#define BIT_SHIFT_WLGP_DBC0 0 +#define BIT_MASK_WLGP_DBC0 0xf +#define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0) +#define BITS_WLGP_DBC0 (BIT_MASK_WLGP_DBC0 << BIT_SHIFT_WLGP_DBC0) +#define BIT_CLEAR_WLGP_DBC0(x) ((x) & (~BITS_WLGP_DBC0)) +#define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0) +#define BIT_SET_WLGP_DBC0(x, v) (BIT_CLEAR_WLGP_DBC0(x) | BIT_WLGP_DBC0(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RPWM2 (Offset 0x009C) */ +#define BIT_SHIFT_RPWM2 16 +#define BIT_MASK_RPWM2 0xffff +#define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2) +#define BITS_RPWM2 (BIT_MASK_RPWM2 << BIT_SHIFT_RPWM2) +#define BIT_CLEAR_RPWM2(x) ((x) & (~BITS_RPWM2)) +#define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2) +#define BIT_SET_RPWM2(x, v) (BIT_CLEAR_RPWM2(x) | BIT_RPWM2(v)) -/* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */ +#endif -#define BIT_WLGP_DBC1EN BIT(15) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WLGP_DBC1 8 -#define BIT_MASK_WLGP_DBC1 0xf -#define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1) -#define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1) +/* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */ -#define BIT_WLGP_DBC0EN BIT(7) +#define BIT_SHIFT_FSM_MON_SEL 24 +#define BIT_MASK_FSM_MON_SEL 0x7 +#define BIT_FSM_MON_SEL(x) \ + (((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL) +#define BITS_FSM_MON_SEL (BIT_MASK_FSM_MON_SEL << BIT_SHIFT_FSM_MON_SEL) +#define BIT_CLEAR_FSM_MON_SEL(x) ((x) & (~BITS_FSM_MON_SEL)) +#define BIT_GET_FSM_MON_SEL(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL) +#define BIT_SET_FSM_MON_SEL(x, v) \ + (BIT_CLEAR_FSM_MON_SEL(x) | BIT_FSM_MON_SEL(v)) -#define BIT_SHIFT_WLGP_DBC0 0 -#define BIT_MASK_WLGP_DBC0 0xf -#define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0) -#define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0) +#define BIT_DOP_ELDO BIT(23) +#define BIT_FSM_MON_UPD BIT(15) +#define BIT_SHIFT_FSM_PAR 0 +#define BIT_MASK_FSM_PAR 0x7fff +#define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR) +#define BITS_FSM_PAR (BIT_MASK_FSM_PAR << BIT_SHIFT_FSM_PAR) +#define BIT_CLEAR_FSM_PAR(x) ((x) & (~BITS_FSM_PAR)) +#define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR) +#define BIT_SET_FSM_PAR(x, v) (BIT_CLEAR_FSM_PAR(x) | BIT_FSM_PAR(v)) -/* 2 REG_RPWM2 (Offset 0x009C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RPWM2 16 -#define BIT_MASK_RPWM2 0xffff -#define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2) -#define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2) +/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ +#define BIT_SHIFT_TSFT_SEL_V1 0 +#define BIT_MASK_TSFT_SEL_V1 0x7 +#define BIT_TSFT_SEL_V1(x) \ + (((x) & BIT_MASK_TSFT_SEL_V1) << BIT_SHIFT_TSFT_SEL_V1) +#define BITS_TSFT_SEL_V1 (BIT_MASK_TSFT_SEL_V1 << BIT_SHIFT_TSFT_SEL_V1) +#define BIT_CLEAR_TSFT_SEL_V1(x) ((x) & (~BITS_TSFT_SEL_V1)) +#define BIT_GET_TSFT_SEL_V1(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_V1) & BIT_MASK_TSFT_SEL_V1) +#define BIT_SET_TSFT_SEL_V1(x, v) \ + (BIT_CLEAR_TSFT_SEL_V1(x) | BIT_TSFT_SEL_V1(v)) #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ +#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0 +#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7 +#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) +#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1 \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ + ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x) | \ + BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */ +/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ + +#define BIT_BT_INT_EN BIT(31) +#define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16 +#define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff +#define BIT_RD_WR_WIFI_BT_INFO(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO) +#define BITS_RD_WR_WIFI_BT_INFO \ + (BIT_MASK_RD_WR_WIFI_BT_INFO << BIT_SHIFT_RD_WR_WIFI_BT_INFO) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) ((x) & (~BITS_RD_WR_WIFI_BT_INFO)) +#define BIT_GET_RD_WR_WIFI_BT_INFO(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO) +#define BIT_SET_RD_WR_WIFI_BT_INFO(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) | BIT_RD_WR_WIFI_BT_INFO(v)) + +#endif -#define BIT_SHIFT_FSM_MON_SEL 24 -#define BIT_MASK_FSM_MON_SEL 0x7 -#define BIT_FSM_MON_SEL(x) (((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL) -#define BIT_GET_FSM_MON_SEL(x) (((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_DOP_ELDO BIT(23) -#define BIT_FSM_MON_UPD BIT(15) +/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ -#define BIT_SHIFT_FSM_PAR 0 -#define BIT_MASK_FSM_PAR 0x7fff -#define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR) -#define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR) +#define BIT_PMC_WR_OVF BIT(8) +#define BIT_SHIFT_WLPMC_ERRINT 0 +#define BIT_MASK_WLPMC_ERRINT 0xff +#define BIT_WLPMC_ERRINT(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT) +#define BITS_WLPMC_ERRINT (BIT_MASK_WLPMC_ERRINT << BIT_SHIFT_WLPMC_ERRINT) +#define BIT_CLEAR_WLPMC_ERRINT(x) ((x) & (~BITS_WLPMC_ERRINT)) +#define BIT_GET_WLPMC_ERRINT(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT) +#define BIT_SET_WLPMC_ERRINT(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT(x) | BIT_WLPMC_ERRINT(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#define BIT_SHIFT_SEL_V 30 +#define BIT_MASK_SEL_V 0x3 +#define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V) +#define BITS_SEL_V (BIT_MASK_SEL_V << BIT_SHIFT_SEL_V) +#define BIT_CLEAR_SEL_V(x) ((x) & (~BITS_SEL_V)) +#define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V) +#define BIT_SET_SEL_V(x, v) (BIT_CLEAR_SEL_V(x) | BIT_SEL_V(v)) -/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ +#define BIT_SEL_LDO_PC BIT(29) +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_TSFT_SEL_V1 0 -#define BIT_MASK_TSFT_SEL_V1 0x7 -#define BIT_TSFT_SEL_V1(x) (((x) & BIT_MASK_TSFT_SEL_V1) << BIT_SHIFT_TSFT_SEL_V1) -#define BIT_GET_TSFT_SEL_V1(x) (((x) >> BIT_SHIFT_TSFT_SEL_V1) & BIT_MASK_TSFT_SEL_V1) +/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#define BIT_SHIFT_CK_MON_SEL 26 +#define BIT_MASK_CK_MON_SEL 0x7 +#define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL) +#define BITS_CK_MON_SEL (BIT_MASK_CK_MON_SEL << BIT_SHIFT_CK_MON_SEL) +#define BIT_CLEAR_CK_MON_SEL(x) ((x) & (~BITS_CK_MON_SEL)) +#define BIT_GET_CK_MON_SEL(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL) +#define BIT_SET_CK_MON_SEL(x, v) (BIT_CLEAR_CK_MON_SEL(x) | BIT_CK_MON_SEL(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#define BIT_SHIFT_CK_MON_SEL_V2 26 +#define BIT_MASK_CK_MON_SEL_V2 0x7 +#define BIT_CK_MON_SEL_V2(x) \ + (((x) & BIT_MASK_CK_MON_SEL_V2) << BIT_SHIFT_CK_MON_SEL_V2) +#define BITS_CK_MON_SEL_V2 (BIT_MASK_CK_MON_SEL_V2 << BIT_SHIFT_CK_MON_SEL_V2) +#define BIT_CLEAR_CK_MON_SEL_V2(x) ((x) & (~BITS_CK_MON_SEL_V2)) +#define BIT_GET_CK_MON_SEL_V2(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_V2) & BIT_MASK_CK_MON_SEL_V2) +#define BIT_SET_CK_MON_SEL_V2(x, v) \ + (BIT_CLEAR_CK_MON_SEL_V2(x) | BIT_CK_MON_SEL_V2(v)) -/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0 -#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) +/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#define BIT_CK_MON_EN BIT(25) +#define BIT_FREF_EDGE BIT(24) +#define BIT_CK320M_EN BIT(23) +#define BIT_CK_5M_EN BIT(22) +#define BIT_TESTEN BIT(21) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#define BIT_LD_B12V_EN_V1 BIT(7) -/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ +#endif -#define BIT_BT_INT_EN BIT(31) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16 -#define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff -#define BIT_RD_WR_WIFI_BT_INFO(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO) -#define BIT_GET_RD_WR_WIFI_BT_INFO(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_PSTIMER_2_MSK BIT(31) -/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ +#endif -#define BIT_PMC_WR_OVF BIT(8) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WLPMC_ERRINT 0 -#define BIT_MASK_WLPMC_ERRINT 0xff -#define BIT_WLPMC_ERRINT(x) (((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT) -#define BIT_GET_WLPMC_ERRINT(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_PSTIMER_1_MSK BIT(30) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SEL_V 30 -#define BIT_MASK_SEL_V 0x3 -#define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V) -#define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_PSTIMEOUT_MSK BIT(29) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_PSTIMER_0_MSK BIT(29) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#endif -#define BIT_TXFIFO_TH_INT BIT(30) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_GTINT4_MSK BIT(28) +#define BIT_GTINT4 BIT(28) +#define BIT_GTINT3_MSK BIT(27) +#define BIT_GTINT3 BIT(27) +#define BIT_TXBCN0ERR_MSK BIT(26) +#define BIT_TXBCN0ERR BIT(26) +#define BIT_TXBCN0OK_MSK BIT(25) +#define BIT_TXBCN0OK BIT(25) +#define BIT_TSF_BIT32_TOGGLE_MSK BIT(24) +#define BIT_TSF_BIT32_TOGGLE BIT(24) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +/* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_SEL_LDO_PC BIT(29) +#define BIT_TXDMA_START_INT_MSK BIT(23) +#define BIT_TXDMA_STOP_INT_MSK BIT(22) +#define BIT_HISR7_IND_MSK BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_BCNDMAINT0_MSK BIT(20) +#define BIT_BCNDMAINT0 BIT(20) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_CK_MON_SEL_V2 26 -#define BIT_MASK_CK_MON_SEL_V2 0x7 -#define BIT_CK_MON_SEL_V2(x) (((x) & BIT_MASK_CK_MON_SEL_V2) << BIT_SHIFT_CK_MON_SEL_V2) -#define BIT_GET_CK_MON_SEL_V2(x) (((x) >> BIT_SHIFT_CK_MON_SEL_V2) & BIT_MASK_CK_MON_SEL_V2) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR6_IND_MSK BIT(19) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR5_MSK BIT(18) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_CK_MON_SEL 26 -#define BIT_MASK_CK_MON_SEL 0x7 -#define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL) -#define BIT_GET_CK_MON_SEL(x) (((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR5_IND_MSK BIT(18) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR4_MSK BIT(17) -/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ +#endif -#define BIT_CK_MON_EN BIT(25) -#define BIT_FREF_EDGE BIT(24) -#define BIT_CK320M_EN BIT(23) -#define BIT_CK_5M_EN BIT(22) -#define BIT_TESTEN BIT(21) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR4_IND_MSK BIT(17) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30) -#define BIT_PSTIMEOUT_MSK BIT(29) -#define BIT_GTINT4_MSK BIT(28) -#define BIT_GTINT3_MSK BIT(27) -#define BIT_TXBCN0ERR_MSK BIT(26) -#define BIT_TXBCN0OK_MSK BIT(25) -#define BIT_TSF_BIT32_TOGGLE_MSK BIT(24) -#define BIT_BCNDMAINT0_MSK BIT(20) -#define BIT_BCNDERR0_MSK BIT(16) -#define BIT_HSISR_IND_ON_INT_MSK BIT(15) +#define BIT_BCNDERR0_MSK BIT(16) +#define BIT_BCNDERR0 BIT(16) +#define BIT_HSISR_IND_ON_INT_MSK BIT(15) +#define BIT_HSISR_IND_ON_INT BIT(15) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_HIMR0 (Offset 0x00B0) */ + +#define BIT_BCNDMAINT_E_MSK BIT(14) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_BCNDMAINT_E_MSK BIT(14) +#define BIT_HISR3_IND_INT_MSK BIT(14) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ + +#define BIT_HISR3_IND_MSK BIT(14) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_HISR3_IND_INT_MSK BIT(14) -#define BIT_HISR2_IND_INT_MSK BIT(13) +#define BIT_HISR2_IND_INT_MSK BIT(13) #endif +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR0 (Offset 0x00B0) */ + +#define BIT_HISR2_IND_MSK BIT(13) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_CTWEND_MSK BIT(12) -#define BIT_HISR1_IND_MSK BIT(11) +#define BIT_CTWEND_MSK BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_HISR1_IND_MSK BIT(11) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_HISR1_IND_INT_MSK BIT(11) +#define BIT_HISR1_IND_INT_MSK BIT(11) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ + +#define BIT_C2HCMD_MSK BIT(10) +#define BIT_C2HCMD BIT(10) +#define BIT_CPWM2_MSK BIT(9) +#define BIT_CPWM2 BIT(9) +#define BIT_CPWM_MSK BIT(8) +#define BIT_CPWM BIT(8) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_C2HCMD_MSK BIT(10) -#define BIT_CPWM2_MSK BIT(9) -#define BIT_CPWM_MSK BIT(8) -#define BIT_HIGHDOK_MSK BIT(7) -#define BIT_MGTDOK_MSK BIT(6) -#define BIT_BKDOK_MSK BIT(5) -#define BIT_BEDOK_MSK BIT(4) -#define BIT_VIDOK_MSK BIT(3) -#define BIT_VODOK_MSK BIT(2) -#define BIT_RDU_MSK BIT(1) -#define BIT_RXOK_MSK BIT(0) +#define BIT_HIGHDOK_MSK BIT(7) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_TXDMAOK_CHANNEL15_MSK BIT(7) -/* 2 REG_HISR0 (Offset 0x00B4) */ +#endif -#define BIT_PSTIMEOUT2 BIT(31) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_MGTDOK_MSK BIT(6) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_HISR0 (Offset 0x00B4) */ +/* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_TIMEOUT_INTERRUPT2 BIT(31) +#define BIT_TXDMAOK_CHANNEL14_MSK BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_BKDOK_MSK BIT(5) -/* 2 REG_HISR0 (Offset 0x00B4) */ +#endif -#define BIT_PSTIMEOUT1 BIT(30) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_TXDMAOK_CHANNEL3_MSK BIT(5) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_HISR0 (Offset 0x00B4) */ +/* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_TIMEOUT_INTERRUTP1 BIT(30) +#define BIT_BEDOK_MSK BIT(4) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_TXDMAOK_CHANNEL2_MSK BIT(4) -/* 2 REG_HISR0 (Offset 0x00B4) */ +#endif -#define BIT_PSTIMEOUT BIT(29) -#define BIT_GTINT4 BIT(28) -#define BIT_GTINT3 BIT(27) -#define BIT_TXBCN0ERR BIT(26) -#define BIT_TXBCN0OK BIT(25) -#define BIT_TSF_BIT32_TOGGLE BIT(24) -#define BIT_BCNDMAINT0 BIT(20) -#define BIT_BCNDERR0 BIT(16) -#define BIT_HSISR_IND_ON_INT BIT(15) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_VIDOK_MSK BIT(3) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_HISR0 (Offset 0x00B4) */ +/* 2 REG_HIMR0 (Offset 0x00B0) */ -#define BIT_BCNDMAINT_E BIT(14) +#define BIT_TXDMAOK_CHANNEL1_MSK BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HIMR0 (Offset 0x00B0) */ +#define BIT_VODOK_MSK BIT(2) -/* 2 REG_HISR0 (Offset 0x00B4) */ +#endif -#define BIT_HISR3_IND_INT BIT(14) -#define BIT_HISR2_IND_INT BIT(13) +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR0 (Offset 0x00B0) */ + +#define BIT_TXDMAOK_CHANNEL0_MSK BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_HIMR0 (Offset 0x00B0) */ + +#define BIT_RDU_MSK BIT(1) +#define BIT_RDU BIT(1) +#define BIT_RXOK_MSK BIT(0) +#define BIT_RXOK BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ -#define BIT_CTWEND BIT(12) +#define BIT_PSTIMEOUT2 BIT(31) +#define BIT_PSTIMEOUT1 BIT(30) +#define BIT_PSTIMEOUT BIT(29) #endif +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HISR0 (Offset 0x00B4) */ + +#define BIT_HISR5_IND_INT BIT(18) +#define BIT_HISR4_IND_INT BIT(17) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR0 (Offset 0x00B4) */ -#define BIT_HISR1_IND_INT BIT(11) -#define BIT_C2HCMD BIT(10) -#define BIT_CPWM2 BIT(9) -#define BIT_CPWM BIT(8) -#define BIT_HIGHDOK BIT(7) -#define BIT_MGTDOK BIT(6) -#define BIT_BKDOK BIT(5) -#define BIT_BEDOK BIT(4) -#define BIT_VIDOK BIT(3) -#define BIT_VODOK BIT(2) -#define BIT_RDU BIT(1) -#define BIT_RXOK BIT(0) +#define BIT_BCNDMAINT_E BIT(14) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HISR0 (Offset 0x00B4) */ +#define BIT_HISR3_IND_INT BIT(14) +#define BIT_HISR2_IND_INT BIT(13) -/* 2 REG_HIMR1 (Offset 0x00B8) */ +#endif -#define BIT_BTON_STS_UPDATE_MSK BIT(29) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HISR0 (Offset 0x00B4) */ +#define BIT_CTWEND BIT(12) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_HIMR1 (Offset 0x00B8) */ +/* 2 REG_HISR0 (Offset 0x00B4) */ -#define BIT_BTON_STS_UPDATE_MASK BIT(29) +#define BIT_HISR1_IND_INT BIT(11) +#define BIT_HIGHDOK BIT(7) +#define BIT_MGTDOK BIT(6) +#define BIT_BKDOK BIT(5) +#define BIT_BEDOK BIT(4) +#define BIT_VIDOK BIT(3) +#define BIT_VODOK BIT(2) #endif +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_PRETXERR_HANDLE_MSK BIT(31) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_MCU_ERR_MASK BIT(28) +#define BIT_PRE_TX_ERR_INT_MSK BIT(31) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_BTON_STS_UPDATE_INT BIT(29) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT7_MSK BIT(27) +#define BIT_BTON_STS_UPDATE_MSK BIT(29) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_BTON_STS_UPDATE_MASK BIT(29) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT7__MSK BIT(27) +#define BIT_MCU_ERR_MASK BIT(28) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_BCNDMAINT7 BIT(27) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT6_MSK BIT(26) +#define BIT_BCNDMAINT7_MSK BIT(27) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_BCNDMAINT7__MSK BIT(27) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT6__MSK BIT(26) +#define BIT_BCNDMAINT6 BIT(26) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_BCNDMAINT6_MSK BIT(26) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT5_MSK BIT(25) +#define BIT_BCNDMAINT6__MSK BIT(26) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_BCNDMAINT5 BIT(25) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT5__MSK BIT(25) +#define BIT_BCNDMAINT5_MSK BIT(25) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_BCNDMAINT5__MSK BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT4_MSK BIT(24) +#define BIT_BCNDMAINT4 BIT(24) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_BCNDMAINT4_MSK BIT(24) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT4__MSK BIT(24) +#define BIT_BCNDMAINT4__MSK BIT(24) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_BCNDMAINT3_MSK BIT(23) +#define BIT_BCNDMAINT3 BIT(23) +#define BIT_BCNDMAINT2_MSK BIT(22) +#define BIT_BCNDMAINT2 BIT(22) +#define BIT_BCNDMAINT1_MSK BIT(21) +#define BIT_BCNDMAINT1 BIT(21) +#define BIT_BCNDERR7_MSK BIT(20) +#define BIT_BCNDERR7 BIT(20) +#define BIT_BCNDERR6_MSK BIT(19) +#define BIT_BCNDERR6 BIT(19) +#define BIT_BCNDERR5_MSK BIT(18) +#define BIT_BCNDERR5 BIT(18) +#define BIT_BCNDERR4_MSK BIT(17) +#define BIT_BCNDERR4 BIT(17) +#define BIT_BCNDERR3_MSK BIT(16) +#define BIT_BCNDERR3 BIT(16) +#define BIT_BCNDERR2_MSK BIT(15) +#define BIT_BCNDERR2 BIT(15) +#define BIT_BCNDERR1_MSK BIT(14) +#define BIT_BCNDERR1 BIT(14) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_BCNDMAINT3_MSK BIT(23) -#define BIT_BCNDMAINT2_MSK BIT(22) -#define BIT_BCNDMAINT1_MSK BIT(21) -#define BIT_BCNDERR7_MSK BIT(20) -#define BIT_BCNDERR6_MSK BIT(19) -#define BIT_BCNDERR5_MSK BIT(18) -#define BIT_BCNDERR4_MSK BIT(17) -#define BIT_BCNDERR3_MSK BIT(16) -#define BIT_BCNDERR2_MSK BIT(15) -#define BIT_BCNDERR1_MSK BIT(14) +#define BIT_ATIMEND_E_MSK BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_ATIMEND_MSK BIT(12) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_ATIMEND_E_MSK BIT(13) +#define BIT_ATIMEND__MSK BIT(12) #endif +#if (HALMAC_8822B_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_ATIMEND_E_V1_MSK BIT(12) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_ATIMEND_MSK BIT(12) +#define BIT_TXERR_MSK BIT(11) +#define BIT_TXERR_INT BIT(11) +#define BIT_RXERR_MSK BIT(10) +#define BIT_RXERR_INT BIT(10) +#define BIT_TXFOVW_MSK BIT(9) +#define BIT_TXFOVW BIT(9) +#define BIT_FOVW_MSK BIT(8) +#define BIT_FOVW BIT(8) #endif +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_CPU_MGQ_EARLY_INT_MSK BIT(6) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_ATIMEND__MSK BIT(12) +#define BIT_CPU_MGQ_TXDONE_MSK BIT(5) +#define BIT_CPU_MGQ_TXDONE BIT(5) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_PS_TIMER_C_MSK BIT(4) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_TXERR_MSK BIT(11) -#define BIT_RXERR_MSK BIT(10) -#define BIT_TXFOVW_MSK BIT(9) -#define BIT_FOVW_MSK BIT(8) +#define BIT_PSTIMER_5_MSK BIT(4) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_PS_TIMER_B_MSK BIT(3) + +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_LD_B12V_EN_V1 BIT(7) +#define BIT_PSTIMER_4_MSK BIT(3) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ + +#define BIT_PS_TIMER_A_MSK BIT(2) + +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_HIMR1 (Offset 0x00B8) */ -#define BIT_CPU_MGQ_TXDONE_MSK BIT(5) -#define BIT_PS_TIMER_C_MSK BIT(4) -#define BIT_PS_TIMER_B_MSK BIT(3) -#define BIT_PS_TIMER_A_MSK BIT(2) -#define BIT_CPUMGQ_TX_TIMER_MSK BIT(1) +#define BIT_PSTIMER_3_MSK BIT(2) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_CPUMGQ_TX_TIMER_MSK BIT(1) +#define BIT_CPUMGQ_TX_TIMER BIT(1) -/* 2 REG_HISR1 (Offset 0x00BC) */ +#endif -#define BIT_BTON_STS_UPDATE_INT BIT(29) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_HIMR1 (Offset 0x00B8) */ +#define BIT_BB_STOPRX_INT_MSK BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ -#define BIT_MCU_ERR BIT(28) +#define BIT_PRETXERR_HANDLE_INT BIT(31) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ -#define BIT_BCNDMAINT7 BIT(27) -#define BIT_BCNDMAINT6 BIT(26) -#define BIT_BCNDMAINT5 BIT(25) -#define BIT_BCNDMAINT4 BIT(24) -#define BIT_BCNDMAINT3 BIT(23) -#define BIT_BCNDMAINT2 BIT(22) -#define BIT_BCNDMAINT1 BIT(21) -#define BIT_BCNDERR7 BIT(20) -#define BIT_BCNDERR6 BIT(19) -#define BIT_BCNDERR5 BIT(18) -#define BIT_BCNDERR4 BIT(17) -#define BIT_BCNDERR3 BIT(16) -#define BIT_BCNDERR2 BIT(15) -#define BIT_BCNDERR1 BIT(14) +#define BIT_MCU_ERR BIT(28) +#define BIT_ATIMEND_E BIT(13) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8822B_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ -#define BIT_ATIMEND_E BIT(13) +#define BIT_ATIMEND_E_V1_INT BIT(12) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ -#define BIT_ATIMEND BIT(12) -#define BIT_TXERR_INT BIT(11) -#define BIT_RXERR_INT BIT(10) -#define BIT_TXFOVW BIT(9) -#define BIT_FOVW BIT(8) +#define BIT_PS_TIMER_C BIT(4) +#define BIT_PS_TIMER_B BIT(3) +#define BIT_PS_TIMER_A BIT(2) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8198F_SUPPORT) /* 2 REG_HISR1 (Offset 0x00BC) */ -#define BIT_CPU_MGQ_TXDONE BIT(5) -#define BIT_PS_TIMER_C BIT(4) -#define BIT_PS_TIMER_B BIT(3) -#define BIT_PS_TIMER_A BIT(2) -#define BIT_CPUMGQ_TX_TIMER BIT(1) +#define BIT_SHIFT_SYS_PINMUX_EN 0 +#define BIT_MASK_SYS_PINMUX_EN 0xfffffff +#define BIT_SYS_PINMUX_EN(x) \ + (((x) & BIT_MASK_SYS_PINMUX_EN) << BIT_SHIFT_SYS_PINMUX_EN) +#define BITS_SYS_PINMUX_EN (BIT_MASK_SYS_PINMUX_EN << BIT_SHIFT_SYS_PINMUX_EN) +#define BIT_CLEAR_SYS_PINMUX_EN(x) ((x) & (~BITS_SYS_PINMUX_EN)) +#define BIT_GET_SYS_PINMUX_EN(x) \ + (((x) >> BIT_SHIFT_SYS_PINMUX_EN) & BIT_MASK_SYS_PINMUX_EN) +#define BIT_SET_SYS_PINMUX_EN(x, v) \ + (BIT_CLEAR_SYS_PINMUX_EN(x) | BIT_SYS_PINMUX_EN(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ -#define BIT_HR_FF_OVF BIT(6) -#define BIT_HR_FF_UDN BIT(5) -#define BIT_TXDMA_BUSY_ERR BIT(4) -#define BIT_TXDMA_VLD_ERR BIT(3) -#define BIT_QSEL_UNKNOWN_ERR BIT(2) -#define BIT_QSEL_MIS_ERR BIT(1) +#define BIT_HR_FF_OVF BIT(6) +#define BIT_HR_FF_UDN BIT(5) +#define BIT_TXDMA_BUSY_ERR BIT(4) +#define BIT_TXDMA_VLD_ERR BIT(3) +#define BIT_QSEL_UNKNOWN_ERR BIT(2) +#define BIT_QSEL_MIS_ERR BIT(1) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_DBG_PORT_SEL (Offset 0x00C0) */ +#define BIT_SHIFT_DEBUG_ST 0 +#define BIT_MASK_DEBUG_ST 0xffffffffL +#define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST) +#define BITS_DEBUG_ST (BIT_MASK_DEBUG_ST << BIT_SHIFT_DEBUG_ST) +#define BIT_CLEAR_DEBUG_ST(x) ((x) & (~BITS_DEBUG_ST)) +#define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST) +#define BIT_SET_DEBUG_ST(x, v) (BIT_CLEAR_DEBUG_ST(x) | BIT_DEBUG_ST(v)) -#define BIT_SHIFT_DEBUG_ST 0 -#define BIT_MASK_DEBUG_ST 0xffffffffL -#define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST) -#define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SDIO_DIOERR_RPT (Offset 0x102500C0) */ +#define BIT_SDIO_PAGE_ERR BIT(0) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ -#define BIT_SDIO_OVERRD_ERR BIT(0) +#define BIT_SDIO_OVERRD_ERR BIT(0) + +#define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0 +#define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7 +#define BIT_SDIO_DATA_REPLY_TIME(x) \ + (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME) \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME) +#define BITS_SDIO_DATA_REPLY_TIME \ + (BIT_MASK_SDIO_DATA_REPLY_TIME << BIT_SHIFT_SDIO_DATA_REPLY_TIME) +#define BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) ((x) & (~BITS_SDIO_DATA_REPLY_TIME)) +#define BIT_GET_SDIO_DATA_REPLY_TIME(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) & \ + BIT_MASK_SDIO_DATA_REPLY_TIME) +#define BIT_SET_SDIO_DATA_REPLY_TIME(x, v) \ + (BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) | BIT_SDIO_DATA_REPLY_TIME(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_SDIO_CMD_ERRCNT (Offset 0x102500C2) */ + +#define BIT_SHIFT_CMD_CRC_ERR_CNT 0 +#define BIT_MASK_CMD_CRC_ERR_CNT 0xff +#define BIT_CMD_CRC_ERR_CNT(x) \ + (((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT) +#define BITS_CMD_CRC_ERR_CNT \ + (BIT_MASK_CMD_CRC_ERR_CNT << BIT_SHIFT_CMD_CRC_ERR_CNT) +#define BIT_CLEAR_CMD_CRC_ERR_CNT(x) ((x) & (~BITS_CMD_CRC_ERR_CNT)) +#define BIT_GET_CMD_CRC_ERR_CNT(x) \ + (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT) +#define BIT_SET_CMD_CRC_ERR_CNT(x, v) \ + (BIT_CLEAR_CMD_CRC_ERR_CNT(x) | BIT_CMD_CRC_ERR_CNT(v)) + +/* 2 REG_SDIO_DATA_ERRCNT (Offset 0x102500C3) */ + +#define BIT_SHIFT_DATA_CRC_ERR_CNT 0 +#define BIT_MASK_DATA_CRC_ERR_CNT 0xff +#define BIT_DATA_CRC_ERR_CNT(x) \ + (((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT) +#define BITS_DATA_CRC_ERR_CNT \ + (BIT_MASK_DATA_CRC_ERR_CNT << BIT_SHIFT_DATA_CRC_ERR_CNT) +#define BIT_CLEAR_DATA_CRC_ERR_CNT(x) ((x) & (~BITS_DATA_CRC_ERR_CNT)) +#define BIT_GET_DATA_CRC_ERR_CNT(x) \ + (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT) +#define BIT_SET_DATA_CRC_ERR_CNT(x, v) \ + (BIT_CLEAR_DATA_CRC_ERR_CNT(x) | BIT_DATA_CRC_ERR_CNT(v)) -/* 2 REG_SDIO_CMD_ERRCNT (Offset 0x102500C1) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_CMD_CRC_ERR_CNT 0 -#define BIT_MASK_CMD_CRC_ERR_CNT 0xff -#define BIT_CMD_CRC_ERR_CNT(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT) -#define BIT_GET_CMD_CRC_ERR_CNT(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT) +/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ +#define BIT_MAC_SOP BIT(25) +#define BIT_LDO11_ST_EXT BIT(24) +#define BIT_ANTSELB_S2 BIT(23) +#define BIT_ANTSELB_S1 BIT(22) +#define BIT_ANTSEL_S3 BIT(21) -/* 2 REG_SDIO_DATA_ERRCNT (Offset 0x102500C2) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DATA_CRC_ERR_CNT 0 -#define BIT_MASK_DATA_CRC_ERR_CNT 0xff -#define BIT_DATA_CRC_ERR_CNT(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT) -#define BIT_GET_DATA_CRC_ERR_CNT(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT) +/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ +#define BIT_USB3_USB2_TRANSITION BIT(20) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_MAC_SOP BIT(25) -#define BIT_LDO11_ST_EXT BIT(24) -#define BIT_ANTSELB_S2 BIT(23) -#define BIT_ANTSELB_S1 BIT(22) -#define BIT_ANTSEL_S3 BIT(21) -#define BIT_ANTSEL_S2 BIT(20) +#define BIT_ANTSEL_S2 BIT(20) +#define BIT_ANTSEL_S1 BIT(19) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_USB3_USB2_TRANSITION BIT(20) +#define BIT_SHIFT_USB23_SW_MODE_V1 18 +#define BIT_MASK_USB23_SW_MODE_V1 0x3 +#define BIT_USB23_SW_MODE_V1(x) \ + (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1) +#define BITS_USB23_SW_MODE_V1 \ + (BIT_MASK_USB23_SW_MODE_V1 << BIT_SHIFT_USB23_SW_MODE_V1) +#define BIT_CLEAR_USB23_SW_MODE_V1(x) ((x) & (~BITS_USB23_SW_MODE_V1)) +#define BIT_GET_USB23_SW_MODE_V1(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1) +#define BIT_SET_USB23_SW_MODE_V1(x, v) \ + (BIT_CLEAR_USB23_SW_MODE_V1(x) | BIT_USB23_SW_MODE_V1(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_ANTSEL_S1 BIT(19) -#define BIT_FCSN_PU BIT(18) +#define BIT_FCSN_PU BIT(18) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ - - -#define BIT_SHIFT_USB23_SW_MODE_V1 18 -#define BIT_MASK_USB23_SW_MODE_V1 0x3 -#define BIT_USB23_SW_MODE_V1(x) (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1) -#define BIT_GET_USB23_SW_MODE_V1(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1) - - -#endif - - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ - -#define BIT_KEEP_PAD BIT(17) - -#endif - - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_NO_PDN_CHIPOFF_V1 BIT(17) +#define BIT_NO_PDN_CHIPOFF_V1 BIT(17) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_PAD_ALD_SKP BIT(16) +#define BIT_KEEP_PAD BIT(17) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_RSM_EN_V1 BIT(16) +#define BIT_RSM_EN_V1 BIT(16) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_PAD_A_ANTSEL_E BIT(11) -#define BIT_PAD_A_ANTSELB_E BIT(10) -#define BIT_PAD_A_ANTSEL_O BIT(9) -#define BIT_PAD_A_ANTSELB_O BIT(8) +#define BIT_PAD_ALD_SKP BIT(16) +#define BIT_PAD_A_ANTSEL_E BIT(11) +#define BIT_PAD_A_ANTSELB_E BIT(10) +#define BIT_PAD_A_ANTSEL_O BIT(9) +#define BIT_PAD_A_ANTSELB_O BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_LD_B12V_EN BIT(7) +#define BIT_LD_B12V_EN BIT(7) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_B15V_EN BIT(7) +#define BIT_B15V_EN BIT(7) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_IOSEL BIT(6) +#define BIT_EESK_IOSEL BIT(6) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_IOSEL_V1 BIT(6) +#define BIT_EECS_IOSEL_V1 BIT(6) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_DATA_O BIT(5) +#define BIT_EESK_DATA_O BIT(5) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_DATA_O_V1 BIT(5) +#define BIT_EECS_DATA_O_V1 BIT(5) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_DATA_I BIT(4) +#define BIT_EESK_DATA_I BIT(4) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_DATA_I_V1 BIT(4) +#define BIT_EECS_DATA_I_V1 BIT(4) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_IOSEL BIT(2) +#define BIT_EECS_IOSEL BIT(2) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_IOSEL_V1 BIT(2) +#define BIT_EESK_IOSEL_V1 BIT(2) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_DATA_O BIT(1) +#define BIT_EECS_DATA_O BIT(1) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_DATA_O_V1 BIT(1) +#define BIT_EESK_DATA_O_V1 BIT(1) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EECS_DATA_I BIT(0) +#define BIT_EECS_DATA_I BIT(0) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ -#define BIT_EESK_DATA_I_V1 BIT(0) +#define BIT_EESK_DATA_I_V1 BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_CMD_ERR_CONTENT (Offset 0x102500C4) */ - -#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0 -#define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL -#define BIT_SDIO_CMD_ERR_CONTENT(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT) -#define BIT_GET_SDIO_CMD_ERR_CONTENT(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & BIT_MASK_SDIO_CMD_ERR_CONTENT) - +#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0 +#define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL +#define BIT_SDIO_CMD_ERR_CONTENT(x) \ + (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT) +#define BITS_SDIO_CMD_ERR_CONTENT \ + (BIT_MASK_SDIO_CMD_ERR_CONTENT << BIT_SHIFT_SDIO_CMD_ERR_CONTENT) +#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) ((x) & (~BITS_SDIO_CMD_ERR_CONTENT)) +#define BIT_GET_SDIO_CMD_ERR_CONTENT(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & \ + BIT_MASK_SDIO_CMD_ERR_CONTENT) +#define BIT_SET_SDIO_CMD_ERR_CONTENT(x, v) \ + (BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) | BIT_SDIO_CMD_ERR_CONTENT(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_MEM_RMC (Offset 0x00C8) */ -#define BIT_MEM_RMV_SIGN BIT(31) -#define BIT_MEM_RMV_2PRF1 BIT(29) -#define BIT_MEM_RMV_2PRF0 BIT(28) -#define BIT_MEM_RMV_1PRF1 BIT(27) -#define BIT_MEM_RMV_1PRF0 BIT(26) -#define BIT_MEM_RMV_1PSR BIT(25) -#define BIT_MEM_RMV_ROM BIT(24) +#define BIT_SHIFT_MEM_RME_WL_V2 4 +#define BIT_MASK_MEM_RME_WL_V2 0x3f +#define BIT_MEM_RME_WL_V2(x) \ + (((x) & BIT_MASK_MEM_RME_WL_V2) << BIT_SHIFT_MEM_RME_WL_V2) +#define BITS_MEM_RME_WL_V2 (BIT_MASK_MEM_RME_WL_V2 << BIT_SHIFT_MEM_RME_WL_V2) +#define BIT_CLEAR_MEM_RME_WL_V2(x) ((x) & (~BITS_MEM_RME_WL_V2)) +#define BIT_GET_MEM_RME_WL_V2(x) \ + (((x) >> BIT_SHIFT_MEM_RME_WL_V2) & BIT_MASK_MEM_RME_WL_V2) +#define BIT_SET_MEM_RME_WL_V2(x, v) \ + (BIT_CLEAR_MEM_RME_WL_V2(x) | BIT_MEM_RME_WL_V2(v)) + +#define BIT_SHIFT_MEM_RME_HCI_V2 0 +#define BIT_MASK_MEM_RME_HCI_V2 0x1f +#define BIT_MEM_RME_HCI_V2(x) \ + (((x) & BIT_MASK_MEM_RME_HCI_V2) << BIT_SHIFT_MEM_RME_HCI_V2) +#define BITS_MEM_RME_HCI_V2 \ + (BIT_MASK_MEM_RME_HCI_V2 << BIT_SHIFT_MEM_RME_HCI_V2) +#define BIT_CLEAR_MEM_RME_HCI_V2(x) ((x) & (~BITS_MEM_RME_HCI_V2)) +#define BIT_GET_MEM_RME_HCI_V2(x) \ + (((x) >> BIT_SHIFT_MEM_RME_HCI_V2) & BIT_MASK_MEM_RME_HCI_V2) +#define BIT_SET_MEM_RME_HCI_V2(x, v) \ + (BIT_CLEAR_MEM_RME_HCI_V2(x) | BIT_MEM_RME_HCI_V2(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MEM_RME_WL_V2 4 -#define BIT_MASK_MEM_RME_WL_V2 0x3f -#define BIT_MEM_RME_WL_V2(x) (((x) & BIT_MASK_MEM_RME_WL_V2) << BIT_SHIFT_MEM_RME_WL_V2) -#define BIT_GET_MEM_RME_WL_V2(x) (((x) >> BIT_SHIFT_MEM_RME_WL_V2) & BIT_MASK_MEM_RME_WL_V2) - - -#define BIT_SHIFT_MEM_RME_HCI_V2 0 -#define BIT_MASK_MEM_RME_HCI_V2 0x1f -#define BIT_MEM_RME_HCI_V2(x) (((x) & BIT_MASK_MEM_RME_HCI_V2) << BIT_SHIFT_MEM_RME_HCI_V2) -#define BIT_GET_MEM_RME_HCI_V2(x) (((x) >> BIT_SHIFT_MEM_RME_HCI_V2) & BIT_MASK_MEM_RME_HCI_V2) +/* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */ +#define BIT_D3_CRC_ERR BIT(4) +#define BIT_D2_CRC_ERR BIT(3) +#define BIT_D1_CRC_ERR BIT(2) +#define BIT_D0_CRC_ERR BIT(1) +#define BIT_CMD_CRC_ERR BIT(0) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */ - -#define BIT_D3_CRC_ERR BIT(4) -#define BIT_D2_CRC_ERR BIT(3) -#define BIT_D1_CRC_ERR BIT(2) -#define BIT_D0_CRC_ERR BIT(1) -#define BIT_CMD_CRC_ERR BIT(0) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SDIO_DATA_CRC (Offset 0x102500CA) */ - -#define BIT_SHIFT_SDIO_DATA_CRC 0 -#define BIT_MASK_SDIO_DATA_CRC 0xff -#define BIT_SDIO_DATA_CRC(x) (((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC) -#define BIT_GET_SDIO_DATA_CRC(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC) - - -/* 2 REG_SDIO_DATA_REPLY_TIME (Offset 0x102500CB) */ - - -#define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0 -#define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7 -#define BIT_SDIO_DATA_REPLY_TIME(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME) << BIT_SHIFT_SDIO_DATA_REPLY_TIME) -#define BIT_GET_SDIO_DATA_REPLY_TIME(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) & BIT_MASK_SDIO_DATA_REPLY_TIME) - +#define BIT_SHIFT_SDIO_DATA_CRC 0 +#define BIT_MASK_SDIO_DATA_CRC 0xffff +#define BIT_SDIO_DATA_CRC(x) \ + (((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC) +#define BITS_SDIO_DATA_CRC (BIT_MASK_SDIO_DATA_CRC << BIT_SHIFT_SDIO_DATA_CRC) +#define BIT_CLEAR_SDIO_DATA_CRC(x) ((x) & (~BITS_SDIO_DATA_CRC)) +#define BIT_GET_SDIO_DATA_CRC(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC) +#define BIT_SET_SDIO_DATA_CRC(x, v) \ + (BIT_CLEAR_SDIO_DATA_CRC(x) | BIT_SDIO_DATA_CRC(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ - -#define BIT_SHIFT_EFUSE_BURN_GNT 24 -#define BIT_MASK_EFUSE_BURN_GNT 0xff -#define BIT_EFUSE_BURN_GNT(x) (((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT) -#define BIT_GET_EFUSE_BURN_GNT(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT) - +#define BIT_SHIFT_EFUSE_BURN_GNT 24 +#define BIT_MASK_EFUSE_BURN_GNT 0xff +#define BIT_EFUSE_BURN_GNT(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT) +#define BITS_EFUSE_BURN_GNT \ + (BIT_MASK_EFUSE_BURN_GNT << BIT_SHIFT_EFUSE_BURN_GNT) +#define BIT_CLEAR_EFUSE_BURN_GNT(x) ((x) & (~BITS_EFUSE_BURN_GNT)) +#define BIT_GET_EFUSE_BURN_GNT(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT) +#define BIT_SET_EFUSE_BURN_GNT(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT(x) | BIT_EFUSE_BURN_GNT(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#define BIT_SHIFT_EFUSE_PG_PWD 24 +#define BIT_MASK_EFUSE_PG_PWD 0xff +#define BIT_EFUSE_PG_PWD(x) \ + (((x) & BIT_MASK_EFUSE_PG_PWD) << BIT_SHIFT_EFUSE_PG_PWD) +#define BITS_EFUSE_PG_PWD (BIT_MASK_EFUSE_PG_PWD << BIT_SHIFT_EFUSE_PG_PWD) +#define BIT_CLEAR_EFUSE_PG_PWD(x) ((x) & (~BITS_EFUSE_PG_PWD)) +#define BIT_GET_EFUSE_PG_PWD(x) \ + (((x) >> BIT_SHIFT_EFUSE_PG_PWD) & BIT_MASK_EFUSE_PG_PWD) +#define BIT_SET_EFUSE_PG_PWD(x, v) \ + (BIT_CLEAR_EFUSE_PG_PWD(x) | BIT_EFUSE_PG_PWD(v)) -#define BIT_SHIFT_EFUSE_PG_PWD 24 -#define BIT_MASK_EFUSE_PG_PWD 0xff -#define BIT_EFUSE_PG_PWD(x) (((x) & BIT_MASK_EFUSE_PG_PWD) << BIT_SHIFT_EFUSE_PG_PWD) -#define BIT_GET_EFUSE_PG_PWD(x) (((x) >> BIT_SHIFT_EFUSE_PG_PWD) & BIT_MASK_EFUSE_PG_PWD) - -#define BIT_DBG_READ_EN BIT(16) +#define BIT_DBG_READ_EN BIT(16) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ -#define BIT_STOP_WL_PMC BIT(9) -#define BIT_STOP_SYM_PMC BIT(8) +#define BIT_STOP_WL_PMC BIT(9) +#define BIT_STOP_SYM_PMC BIT(8) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#define BIT_SHIFT_EDATA1_V1 8 +#define BIT_MASK_EDATA1_V1 0xff +#define BIT_EDATA1_V1(x) (((x) & BIT_MASK_EDATA1_V1) << BIT_SHIFT_EDATA1_V1) +#define BITS_EDATA1_V1 (BIT_MASK_EDATA1_V1 << BIT_SHIFT_EDATA1_V1) +#define BIT_CLEAR_EDATA1_V1(x) ((x) & (~BITS_EDATA1_V1)) +#define BIT_GET_EDATA1_V1(x) (((x) >> BIT_SHIFT_EDATA1_V1) & BIT_MASK_EDATA1_V1) +#define BIT_SET_EDATA1_V1(x, v) (BIT_CLEAR_EDATA1_V1(x) | BIT_EDATA1_V1(v)) -#define BIT_SHIFT_EDATA1_V1 8 -#define BIT_MASK_EDATA1_V1 0xff -#define BIT_EDATA1_V1(x) (((x) & BIT_MASK_EDATA1_V1) << BIT_SHIFT_EDATA1_V1) -#define BIT_GET_EDATA1_V1(x) (((x) >> BIT_SHIFT_EDATA1_V1) & BIT_MASK_EDATA1_V1) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#define BIT_BT_ACCESS_WL_PAGE0 BIT(6) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ -#define BIT_BT_ACCESS_WL_PAGE0 BIT(6) +#define BIT_REG_RST_WLPMC BIT(5) +#define BIT_REG_RST_PD12N BIT(4) +#define BIT_SYSON_DIS_WLREG_WRMSK BIT(3) +#define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SDIO_TRANS_FIFO_STATUS (Offset 0x102500CC) */ +#define BIT_TRANS_FIFO_UNDERFLOW BIT(1) -/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#endif -#define BIT_REG_RST_WLPMC BIT(5) -#define BIT_REG_RST_PD12N BIT(4) -#define BIT_SYSON_DIS_WLREG_WRMSK BIT(3) -#define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SYSON_REG_ARB 0 -#define BIT_MASK_SYSON_REG_ARB 0x3 -#define BIT_SYSON_REG_ARB(x) (((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB) -#define BIT_GET_SYSON_REG_ARB(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB) +/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#define BIT_SHIFT_SYSON_REG_ARB 0 +#define BIT_MASK_SYSON_REG_ARB 0x3 +#define BIT_SYSON_REG_ARB(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB) +#define BITS_SYSON_REG_ARB (BIT_MASK_SYSON_REG_ARB << BIT_SHIFT_SYSON_REG_ARB) +#define BIT_CLEAR_SYSON_REG_ARB(x) ((x) & (~BITS_SYSON_REG_ARB)) +#define BIT_GET_SYSON_REG_ARB(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB) +#define BIT_SET_SYSON_REG_ARB(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB(x) | BIT_SYSON_REG_ARB(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SDIO_TRANS_FIFO_STATUS (Offset 0x102500CC) */ +#define BIT_TRANS_FIFO_OVERFLOW BIT(0) -/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_EDATA0_V1 0 -#define BIT_MASK_EDATA0_V1 0xff -#define BIT_EDATA0_V1(x) (((x) & BIT_MASK_EDATA0_V1) << BIT_SHIFT_EDATA0_V1) -#define BIT_GET_EDATA0_V1(x) (((x) >> BIT_SHIFT_EDATA0_V1) & BIT_MASK_EDATA0_V1) +/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ +#define BIT_SHIFT_EDATA0_V1 0 +#define BIT_MASK_EDATA0_V1 0xff +#define BIT_EDATA0_V1(x) (((x) & BIT_MASK_EDATA0_V1) << BIT_SHIFT_EDATA0_V1) +#define BITS_EDATA0_V1 (BIT_MASK_EDATA0_V1 << BIT_SHIFT_EDATA0_V1) +#define BIT_CLEAR_EDATA0_V1(x) ((x) & (~BITS_EDATA0_V1)) +#define BIT_GET_EDATA0_V1(x) (((x) >> BIT_SHIFT_EDATA0_V1) & BIT_MASK_EDATA0_V1) +#define BIT_SET_EDATA0_V1(x, v) (BIT_CLEAR_EDATA0_V1(x) | BIT_EDATA0_V1(v)) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_SCAN_PLL_BYPASS BIT(30) -#define BIT_DRF_BIST_FAIL_V1 BIT(28) +#define BIT_SCAN_PLL_BYPASS BIT(30) +#define BIT_DRF_BIST_FAIL_V1 BIT(28) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_USB_DIS BIT(27) +#define BIT_BIST_USB_DIS BIT(27) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_DRF_BIST_READY_V1 BIT(27) +#define BIT_DRF_BIST_READY_V1 BIT(27) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_PCI_DIS BIT(26) +#define BIT_BIST_PCI_DIS BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_FAIL_V1 BIT(26) +#define BIT_BIST_FAIL_V1 BIT(26) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_BT_DIS BIT(25) +#define BIT_BIST_BT_DIS BIT(25) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_READY_V1 BIT(25) +#define BIT_BIST_READY_V1 BIT(25) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_WL_DIS BIT(24) +#define BIT_BIST_WL_DIS BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_START_PAUSE_V1 BIT(24) +#define BIT_BIST_START_PAUSE_V1 BIT(24) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#define BIT_SHIFT_BIST_RPT_SEL_V1 20 +#define BIT_MASK_BIST_RPT_SEL_V1 0xf +#define BIT_BIST_RPT_SEL_V1(x) \ + (((x) & BIT_MASK_BIST_RPT_SEL_V1) << BIT_SHIFT_BIST_RPT_SEL_V1) +#define BITS_BIST_RPT_SEL_V1 \ + (BIT_MASK_BIST_RPT_SEL_V1 << BIT_SHIFT_BIST_RPT_SEL_V1) +#define BIT_CLEAR_BIST_RPT_SEL_V1(x) ((x) & (~BITS_BIST_RPT_SEL_V1)) +#define BIT_GET_BIST_RPT_SEL_V1(x) \ + (((x) >> BIT_SHIFT_BIST_RPT_SEL_V1) & BIT_MASK_BIST_RPT_SEL_V1) +#define BIT_SET_BIST_RPT_SEL_V1(x, v) \ + (BIT_CLEAR_BIST_RPT_SEL_V1(x) | BIT_BIST_RPT_SEL_V1(v)) -/* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BIST_RPT_SEL 16 -#define BIT_MASK_BIST_RPT_SEL 0xf -#define BIT_BIST_RPT_SEL(x) (((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL) -#define BIT_GET_BIST_RPT_SEL(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL) +/* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#define BIT_SHIFT_BIST_RPT_SEL 16 +#define BIT_MASK_BIST_RPT_SEL 0xf +#define BIT_BIST_RPT_SEL(x) \ + (((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL) +#define BITS_BIST_RPT_SEL (BIT_MASK_BIST_RPT_SEL << BIT_SHIFT_BIST_RPT_SEL) +#define BIT_CLEAR_BIST_RPT_SEL(x) ((x) & (~BITS_BIST_RPT_SEL)) +#define BIT_GET_BIST_RPT_SEL(x) \ + (((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL) +#define BIT_SET_BIST_RPT_SEL(x, v) \ + (BIT_CLEAR_BIST_RPT_SEL(x) | BIT_BIST_RPT_SEL(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#define BIT_SHIFT_MBIST_RSTNI 8 +#define BIT_MASK_MBIST_RSTNI 0x3ff +#define BIT_MBIST_RSTNI(x) \ + (((x) & BIT_MASK_MBIST_RSTNI) << BIT_SHIFT_MBIST_RSTNI) +#define BITS_MBIST_RSTNI (BIT_MASK_MBIST_RSTNI << BIT_SHIFT_MBIST_RSTNI) +#define BIT_CLEAR_MBIST_RSTNI(x) ((x) & (~BITS_MBIST_RSTNI)) +#define BIT_GET_MBIST_RSTNI(x) \ + (((x) >> BIT_SHIFT_MBIST_RSTNI) & BIT_MASK_MBIST_RSTNI) +#define BIT_SET_MBIST_RSTNI(x, v) \ + (BIT_CLEAR_MBIST_RSTNI(x) | BIT_MBIST_RSTNI(v)) -#define BIT_SHIFT_MBIST_RSTNI 8 -#define BIT_MASK_MBIST_RSTNI 0x3ff -#define BIT_MBIST_RSTNI(x) (((x) & BIT_MASK_MBIST_RSTNI) << BIT_SHIFT_MBIST_RSTNI) -#define BIT_GET_MBIST_RSTNI(x) (((x) >> BIT_SHIFT_MBIST_RSTNI) & BIT_MASK_MBIST_RSTNI) +#endif -#define BIT_BIST_RESUME_PS_V1 BIT(5) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#define BIT_BISD_MODE BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_RESUME_PS BIT(4) +#define BIT_BIST_RESUME_PS_V1 BIT(5) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_RESUME_V1 BIT(4) +#define BIT_BIST_RESUME_PS BIT(4) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_RESUME BIT(3) -#define BIT_BIST_NORMAL BIT(2) +#define BIT_BIST_RESUME_V1 BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#define BIT_BIST_RESUME BIT(3) -/* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_BIST_MODE 2 -#define BIT_MASK_BIST_MODE 0x3 -#define BIT_BIST_MODE(x) (((x) & BIT_MASK_BIST_MODE) << BIT_SHIFT_BIST_MODE) -#define BIT_GET_BIST_MODE(x) (((x) >> BIT_SHIFT_BIST_MODE) & BIT_MASK_BIST_MODE) +/* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#define BIT_BIST_DRF BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_BIST_CTRL (Offset 0x00D0) */ + +#define BIT_BIST_NORMAL BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_BIST_CTRL (Offset 0x00D0) */ -#define BIT_BIST_RSTN BIT(1) -#define BIT_BIST_CLK_EN BIT(0) +#define BIT_SHIFT_BIST_MODE 2 +#define BIT_MASK_BIST_MODE 0x3 +#define BIT_BIST_MODE(x) (((x) & BIT_MASK_BIST_MODE) << BIT_SHIFT_BIST_MODE) +#define BITS_BIST_MODE (BIT_MASK_BIST_MODE << BIT_SHIFT_BIST_MODE) +#define BIT_CLEAR_BIST_MODE(x) ((x) & (~BITS_BIST_MODE)) +#define BIT_GET_BIST_MODE(x) (((x) >> BIT_SHIFT_BIST_MODE) & BIT_MASK_BIST_MODE) +#define BIT_SET_BIST_MODE(x, v) (BIT_CLEAR_BIST_MODE(x) | BIT_BIST_MODE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BIST_CTRL (Offset 0x00D0) */ +#define BIT_BIST_RSTN BIT(1) +#define BIT_BIST_CLK_EN BIT(0) -/* 2 REG_BIST_RPT (Offset 0x00D4) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MBIST_REPORT 0 -#define BIT_MASK_MBIST_REPORT 0xffffffffL -#define BIT_MBIST_REPORT(x) (((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT) -#define BIT_GET_MBIST_REPORT(x) (((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT) +/* 2 REG_BIST_RPT (Offset 0x00D4) */ +#define BIT_SHIFT_MBIST_REPORT 0 +#define BIT_MASK_MBIST_REPORT 0xffffffffL +#define BIT_MBIST_REPORT(x) \ + (((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT) +#define BITS_MBIST_REPORT (BIT_MASK_MBIST_REPORT << BIT_SHIFT_MBIST_REPORT) +#define BIT_CLEAR_MBIST_REPORT(x) ((x) & (~BITS_MBIST_REPORT)) +#define BIT_GET_MBIST_REPORT(x) \ + (((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT) +#define BIT_SET_MBIST_REPORT(x, v) \ + (BIT_CLEAR_MBIST_REPORT(x) | BIT_MBIST_REPORT(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_MEM_CTRL (Offset 0x00D8) */ -#define BIT_RMV_SIGN BIT(31) +#define BIT_RMV_SIGN BIT(31) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ -#define BIT_UMEM_RME BIT(31) +#define BIT_UMEM_RME BIT(31) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_MEM_CTRL (Offset 0x00D8) */ -#define BIT_RMV_2PRF1 BIT(29) -#define BIT_RMV_2PRF0 BIT(28) +#define BIT_RMV_2PRF1 BIT(29) +#define BIT_RMV_2PRF0 BIT(28) #endif - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ - -#define BIT_SHIFT_BT_SPRAM 28 -#define BIT_MASK_BT_SPRAM 0x3 -#define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM) -#define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM) - +#define BIT_SHIFT_BT_SPRAM 28 +#define BIT_MASK_BT_SPRAM 0x3 +#define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM) +#define BITS_BT_SPRAM (BIT_MASK_BT_SPRAM << BIT_SHIFT_BT_SPRAM) +#define BIT_CLEAR_BT_SPRAM(x) ((x) & (~BITS_BT_SPRAM)) +#define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM) +#define BIT_SET_BT_SPRAM(x, v) (BIT_CLEAR_BT_SPRAM(x) | BIT_BT_SPRAM(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_MEM_CTRL (Offset 0x00D8) */ -#define BIT_RMV_1PRF1 BIT(27) -#define BIT_RMV_1PRF0 BIT(26) -#define BIT_RMV_1PSR BIT(25) -#define BIT_RMV_ROM BIT(24) +#define BIT_RMV_1PRF1 BIT(27) +#define BIT_RMV_1PRF0 BIT(26) +#define BIT_RMV_1PSR BIT(25) +#define BIT_RMV_ROM BIT(24) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_MEM_CTRL (Offset 0x00D8) */ + +#define BIT_SHIFT_BT_ROM 24 +#define BIT_MASK_BT_ROM 0xf +#define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM) +#define BITS_BT_ROM (BIT_MASK_BT_ROM << BIT_SHIFT_BT_ROM) +#define BIT_CLEAR_BT_ROM(x) ((x) & (~BITS_BT_ROM)) +#define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM) +#define BIT_SET_BT_ROM(x, v) (BIT_CLEAR_BT_ROM(x) | BIT_BT_ROM(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_MEM_RMV1_2PRF1 BIT(19) +#define BIT_MEM_RMV1_2PRF0 BIT(18) +#define BIT_MEM_RMV1_1PRF1 BIT(17) +#define BIT_MEM_RMV1_1PRF0 BIT(16) +#define BIT_MEM_RMV1_1PSR BIT(15) +#define BIT_MEM_RMV1_ROM BIT(14) -#define BIT_SHIFT_BT_ROM 24 -#define BIT_MASK_BT_ROM 0xf -#define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM) -#define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PCI_DPRAM 10 -#define BIT_MASK_PCI_DPRAM 0x3 -#define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM) -#define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM) +/* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_SHIFT_PCI_DPRAM 10 +#define BIT_MASK_PCI_DPRAM 0x3 +#define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM) +#define BITS_PCI_DPRAM (BIT_MASK_PCI_DPRAM << BIT_SHIFT_PCI_DPRAM) +#define BIT_CLEAR_PCI_DPRAM(x) ((x) & (~BITS_PCI_DPRAM)) +#define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM) +#define BIT_SET_PCI_DPRAM(x, v) (BIT_CLEAR_PCI_DPRAM(x) | BIT_PCI_DPRAM(v)) #endif - #if (HALMAC_8192E_SUPPORT) - /* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_SHIFT_MEM_RME_BT 8 +#define BIT_MASK_MEM_RME_BT 0xf +#define BIT_MEM_RME_BT(x) (((x) & BIT_MASK_MEM_RME_BT) << BIT_SHIFT_MEM_RME_BT) +#define BITS_MEM_RME_BT (BIT_MASK_MEM_RME_BT << BIT_SHIFT_MEM_RME_BT) +#define BIT_CLEAR_MEM_RME_BT(x) ((x) & (~BITS_MEM_RME_BT)) +#define BIT_GET_MEM_RME_BT(x) \ + (((x) >> BIT_SHIFT_MEM_RME_BT) & BIT_MASK_MEM_RME_BT) +#define BIT_SET_MEM_RME_BT(x, v) (BIT_CLEAR_MEM_RME_BT(x) | BIT_MEM_RME_BT(v)) + +#endif -#define BIT_SHIFT_MEM_RME_BT 8 -#define BIT_MASK_MEM_RME_BT 0xf -#define BIT_MEM_RME_BT(x) (((x) & BIT_MASK_MEM_RME_BT) << BIT_SHIFT_MEM_RME_BT) -#define BIT_GET_MEM_RME_BT(x) (((x) >> BIT_SHIFT_MEM_RME_BT) & BIT_MASK_MEM_RME_BT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MEM_CTRL (Offset 0x00D8) */ -#endif +#define BIT_SHIFT_PCI_SPRAM 8 +#define BIT_MASK_PCI_SPRAM 0x3 +#define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM) +#define BITS_PCI_SPRAM (BIT_MASK_PCI_SPRAM << BIT_SHIFT_PCI_SPRAM) +#define BIT_CLEAR_PCI_SPRAM(x) ((x) & (~BITS_PCI_SPRAM)) +#define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM) +#define BIT_SET_PCI_SPRAM(x, v) (BIT_CLEAR_PCI_SPRAM(x) | BIT_PCI_SPRAM(v)) +#define BIT_SHIFT_USB_SPRAM 6 +#define BIT_MASK_USB_SPRAM 0x3 +#define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM) +#define BITS_USB_SPRAM (BIT_MASK_USB_SPRAM << BIT_SHIFT_USB_SPRAM) +#define BIT_CLEAR_USB_SPRAM(x) ((x) & (~BITS_USB_SPRAM)) +#define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM) +#define BIT_SET_USB_SPRAM(x, v) (BIT_CLEAR_USB_SPRAM(x) | BIT_USB_SPRAM(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT) /* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_SHIFT_MEM_RME_WL 4 +#define BIT_MASK_MEM_RME_WL 0xf +#define BIT_MEM_RME_WL(x) (((x) & BIT_MASK_MEM_RME_WL) << BIT_SHIFT_MEM_RME_WL) +#define BITS_MEM_RME_WL (BIT_MASK_MEM_RME_WL << BIT_SHIFT_MEM_RME_WL) +#define BIT_CLEAR_MEM_RME_WL(x) ((x) & (~BITS_MEM_RME_WL)) +#define BIT_GET_MEM_RME_WL(x) \ + (((x) >> BIT_SHIFT_MEM_RME_WL) & BIT_MASK_MEM_RME_WL) +#define BIT_SET_MEM_RME_WL(x, v) (BIT_CLEAR_MEM_RME_WL(x) | BIT_MEM_RME_WL(v)) -#define BIT_SHIFT_PCI_SPRAM 8 -#define BIT_MASK_PCI_SPRAM 0x3 -#define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM) -#define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_USB_SPRAM 6 -#define BIT_MASK_USB_SPRAM 0x3 -#define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM) -#define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM) +/* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_SHIFT_USB_SPRF 4 +#define BIT_MASK_USB_SPRF 0x3 +#define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF) +#define BITS_USB_SPRF (BIT_MASK_USB_SPRF << BIT_SHIFT_USB_SPRF) +#define BIT_CLEAR_USB_SPRF(x) ((x) & (~BITS_USB_SPRF)) +#define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF) +#define BIT_SET_USB_SPRF(x, v) (BIT_CLEAR_USB_SPRF(x) | BIT_USB_SPRF(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_SHIFT_MEM_RME_HCI 0 +#define BIT_MASK_MEM_RME_HCI 0xf +#define BIT_MEM_RME_HCI(x) \ + (((x) & BIT_MASK_MEM_RME_HCI) << BIT_SHIFT_MEM_RME_HCI) +#define BITS_MEM_RME_HCI (BIT_MASK_MEM_RME_HCI << BIT_SHIFT_MEM_RME_HCI) +#define BIT_CLEAR_MEM_RME_HCI(x) ((x) & (~BITS_MEM_RME_HCI)) +#define BIT_GET_MEM_RME_HCI(x) \ + (((x) >> BIT_SHIFT_MEM_RME_HCI) & BIT_MASK_MEM_RME_HCI) +#define BIT_SET_MEM_RME_HCI(x, v) \ + (BIT_CLEAR_MEM_RME_HCI(x) | BIT_MEM_RME_HCI(v)) -/* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MEM_RME_WL 4 -#define BIT_MASK_MEM_RME_WL 0xf -#define BIT_MEM_RME_WL(x) (((x) & BIT_MASK_MEM_RME_WL) << BIT_SHIFT_MEM_RME_WL) -#define BIT_GET_MEM_RME_WL(x) (((x) >> BIT_SHIFT_MEM_RME_WL) & BIT_MASK_MEM_RME_WL) +/* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_SHIFT_MCU_ROM 0 +#define BIT_MASK_MCU_ROM 0xf +#define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM) +#define BITS_MCU_ROM (BIT_MASK_MCU_ROM << BIT_SHIFT_MCU_ROM) +#define BIT_CLEAR_MCU_ROM(x) ((x) & (~BITS_MCU_ROM)) +#define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM) +#define BIT_SET_MCU_ROM(x, v) (BIT_CLEAR_MCU_ROM(x) | BIT_MCU_ROM(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_SHIFT_BIST_ROM 0 +#define BIT_MASK_BIST_ROM 0xffffffffL +#define BIT_BIST_ROM(x) (((x) & BIT_MASK_BIST_ROM) << BIT_SHIFT_BIST_ROM) +#define BITS_BIST_ROM (BIT_MASK_BIST_ROM << BIT_SHIFT_BIST_ROM) +#define BIT_CLEAR_BIST_ROM(x) ((x) & (~BITS_BIST_ROM)) +#define BIT_GET_BIST_ROM(x) (((x) >> BIT_SHIFT_BIST_ROM) & BIT_MASK_BIST_ROM) +#define BIT_SET_BIST_ROM(x, v) (BIT_CLEAR_BIST_ROM(x) | BIT_BIST_ROM(v)) -/* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_USB_SPRF 4 -#define BIT_MASK_USB_SPRF 0x3 -#define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF) -#define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF) +/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4 26 +#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 0x7 +#define BIT_BB_DBG_SEL_AFE_SDM_V4(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) +#define BITS_BB_DBG_SEL_AFE_SDM_V4 \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) | BIT_BB_DBG_SEL_AFE_SDM_V4(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#define BIT_SYN_AGPIO BIT(20) -/* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MEM_RME_HCI 0 -#define BIT_MASK_MEM_RME_HCI 0xf -#define BIT_MEM_RME_HCI(x) (((x) & BIT_MASK_MEM_RME_HCI) << BIT_SHIFT_MEM_RME_HCI) -#define BIT_GET_MEM_RME_HCI(x) (((x) >> BIT_SHIFT_MEM_RME_HCI) & BIT_MASK_MEM_RME_HCI) +/* 2 REG_SYN_RFC_CTRL (Offset 0x00DC) */ +#define BIT_SHIFT_SYN_RF1_CTRL 8 +#define BIT_MASK_SYN_RF1_CTRL 0xff +#define BIT_SYN_RF1_CTRL(x) \ + (((x) & BIT_MASK_SYN_RF1_CTRL) << BIT_SHIFT_SYN_RF1_CTRL) +#define BITS_SYN_RF1_CTRL (BIT_MASK_SYN_RF1_CTRL << BIT_SHIFT_SYN_RF1_CTRL) +#define BIT_CLEAR_SYN_RF1_CTRL(x) ((x) & (~BITS_SYN_RF1_CTRL)) +#define BIT_GET_SYN_RF1_CTRL(x) \ + (((x) >> BIT_SHIFT_SYN_RF1_CTRL) & BIT_MASK_SYN_RF1_CTRL) +#define BIT_SET_SYN_RF1_CTRL(x, v) \ + (BIT_CLEAR_SYN_RF1_CTRL(x) | BIT_SYN_RF1_CTRL(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#define BIT_SHIFT_XTAL_GM_REP 6 +#define BIT_MASK_XTAL_GM_REP 0x3 +#define BIT_XTAL_GM_REP(x) \ + (((x) & BIT_MASK_XTAL_GM_REP) << BIT_SHIFT_XTAL_GM_REP) +#define BITS_XTAL_GM_REP (BIT_MASK_XTAL_GM_REP << BIT_SHIFT_XTAL_GM_REP) +#define BIT_CLEAR_XTAL_GM_REP(x) ((x) & (~BITS_XTAL_GM_REP)) +#define BIT_GET_XTAL_GM_REP(x) \ + (((x) >> BIT_SHIFT_XTAL_GM_REP) & BIT_MASK_XTAL_GM_REP) +#define BIT_SET_XTAL_GM_REP(x, v) \ + (BIT_CLEAR_XTAL_GM_REP(x) | BIT_XTAL_GM_REP(v)) -/* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#define BIT_XTAL_DRV_RF_LATCH_V5 BIT(5) + +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_MCU_ROM 0 -#define BIT_MASK_MCU_ROM 0xf -#define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM) -#define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM) +/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#define BIT_XTAL_LP BIT(4) +#define BIT_XTAL_GM_SEP BIT(3) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#define BIT_SHIFT_XTAL_SEL_TOK_V2 0 +#define BIT_MASK_XTAL_SEL_TOK_V2 0x7 +#define BIT_XTAL_SEL_TOK_V2(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_V2) << BIT_SHIFT_XTAL_SEL_TOK_V2) +#define BITS_XTAL_SEL_TOK_V2 \ + (BIT_MASK_XTAL_SEL_TOK_V2 << BIT_SHIFT_XTAL_SEL_TOK_V2) +#define BIT_CLEAR_XTAL_SEL_TOK_V2(x) ((x) & (~BITS_XTAL_SEL_TOK_V2)) +#define BIT_GET_XTAL_SEL_TOK_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2) & BIT_MASK_XTAL_SEL_TOK_V2) +#define BIT_SET_XTAL_SEL_TOK_V2(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_V2(x) | BIT_XTAL_SEL_TOK_V2(v)) -/* 2 REG_MEM_CTRL (Offset 0x00D8) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_BIST_ROM 0 -#define BIT_MASK_BIST_ROM 0xffffffffL -#define BIT_BIST_ROM(x) (((x) & BIT_MASK_BIST_ROM) << BIT_SHIFT_BIST_ROM) -#define BIT_GET_BIST_ROM(x) (((x) >> BIT_SHIFT_BIST_ROM) & BIT_MASK_BIST_ROM) +/* 2 REG_WLAN_DBG (Offset 0x00DC) */ +#define BIT_SHIFT_WLAN_DBG 0 +#define BIT_MASK_WLAN_DBG 0xffffffffL +#define BIT_WLAN_DBG(x) (((x) & BIT_MASK_WLAN_DBG) << BIT_SHIFT_WLAN_DBG) +#define BITS_WLAN_DBG (BIT_MASK_WLAN_DBG << BIT_SHIFT_WLAN_DBG) +#define BIT_CLEAR_WLAN_DBG(x) ((x) & (~BITS_WLAN_DBG)) +#define BIT_GET_WLAN_DBG(x) (((x) >> BIT_SHIFT_WLAN_DBG) & BIT_MASK_WLAN_DBG) +#define BIT_SET_WLAN_DBG(x, v) (BIT_CLEAR_WLAN_DBG(x) | BIT_WLAN_DBG(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SYN_RFC_CTRL (Offset 0x00DC) */ +#define BIT_SHIFT_SYN_RF0_CTRL 0 +#define BIT_MASK_SYN_RF0_CTRL 0xff +#define BIT_SYN_RF0_CTRL(x) \ + (((x) & BIT_MASK_SYN_RF0_CTRL) << BIT_SHIFT_SYN_RF0_CTRL) +#define BITS_SYN_RF0_CTRL (BIT_MASK_SYN_RF0_CTRL << BIT_SHIFT_SYN_RF0_CTRL) +#define BIT_CLEAR_SYN_RF0_CTRL(x) ((x) & (~BITS_SYN_RF0_CTRL)) +#define BIT_GET_SYN_RF0_CTRL(x) \ + (((x) >> BIT_SHIFT_SYN_RF0_CTRL) & BIT_MASK_SYN_RF0_CTRL) +#define BIT_SET_SYN_RF0_CTRL(x, v) \ + (BIT_CLEAR_SYN_RF0_CTRL(x) | BIT_SYN_RF0_CTRL(v)) -/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4 26 -#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_V4(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) +/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#define BIT_SHIFT_XTAL_SEL_TOK 0 +#define BIT_MASK_XTAL_SEL_TOK 0x7 +#define BIT_XTAL_SEL_TOK(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK) +#define BITS_XTAL_SEL_TOK (BIT_MASK_XTAL_SEL_TOK << BIT_SHIFT_XTAL_SEL_TOK) +#define BIT_CLEAR_XTAL_SEL_TOK(x) ((x) & (~BITS_XTAL_SEL_TOK)) +#define BIT_GET_XTAL_SEL_TOK(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK) +#define BIT_SET_XTAL_SEL_TOK(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK(x) | BIT_XTAL_SEL_TOK(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#define BIT_RD_SEL BIT(31) -/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#endif -#define BIT_SYN_AGPIO BIT(20) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#define BIT_CPU_REG_SEL BIT(31) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ -#define BIT_XTAL_LP BIT(4) -#define BIT_XTAL_GM_SEP BIT(3) +#define BIT_USB_SIE_INTF_WE_V1 BIT(30) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#define BIT_USB3_REG_SEL BIT(30) -/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_XTAL_SEL_TOK_V2 0 -#define BIT_MASK_XTAL_SEL_TOK_V2 0x7 -#define BIT_XTAL_SEL_TOK_V2(x) (((x) & BIT_MASK_XTAL_SEL_TOK_V2) << BIT_SHIFT_XTAL_SEL_TOK_V2) -#define BIT_GET_XTAL_SEL_TOK_V2(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2) & BIT_MASK_XTAL_SEL_TOK_V2) +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#define BIT_SHIFT_USB_SIE_EN 28 +#define BIT_MASK_USB_SIE_EN 0x3 +#define BIT_USB_SIE_EN(x) (((x) & BIT_MASK_USB_SIE_EN) << BIT_SHIFT_USB_SIE_EN) +#define BITS_USB_SIE_EN (BIT_MASK_USB_SIE_EN << BIT_SHIFT_USB_SIE_EN) +#define BIT_CLEAR_USB_SIE_EN(x) ((x) & (~BITS_USB_SIE_EN)) +#define BIT_GET_USB_SIE_EN(x) \ + (((x) >> BIT_SHIFT_USB_SIE_EN) & BIT_MASK_USB_SIE_EN) +#define BIT_SET_USB_SIE_EN(x, v) (BIT_CLEAR_USB_SIE_EN(x) | BIT_USB_SIE_EN(v)) -/* 2 REG_WLAN_DBG (Offset 0x00DC) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WLAN_DBG 0 -#define BIT_MASK_WLAN_DBG 0xffffffffL -#define BIT_WLAN_DBG(x) (((x) & BIT_MASK_WLAN_DBG) << BIT_SHIFT_WLAN_DBG) -#define BIT_GET_WLAN_DBG(x) (((x) >> BIT_SHIFT_WLAN_DBG) & BIT_MASK_WLAN_DBG) +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#define BIT_USB_SIE_SELECT BIT(28) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ -/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ +#define BIT_USB_SIE_INTF_WE BIT(25) +#endif -#define BIT_SHIFT_XTAL_SEL_TOK 0 -#define BIT_MASK_XTAL_SEL_TOK 0x7 -#define BIT_XTAL_SEL_TOK(x) (((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK) -#define BIT_GET_XTAL_SEL_TOK(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ -#endif +#define BIT_USB_SIE_INTF_BYIOREG BIT(24) +#define BIT_SHIFT_USB_SIE_INTF_ADDR 16 +#define BIT_MASK_USB_SIE_INTF_ADDR 0xff +#define BIT_USB_SIE_INTF_ADDR(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR) << BIT_SHIFT_USB_SIE_INTF_ADDR) +#define BITS_USB_SIE_INTF_ADDR \ + (BIT_MASK_USB_SIE_INTF_ADDR << BIT_SHIFT_USB_SIE_INTF_ADDR) +#define BIT_CLEAR_USB_SIE_INTF_ADDR(x) ((x) & (~BITS_USB_SIE_INTF_ADDR)) +#define BIT_GET_USB_SIE_INTF_ADDR(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR) & BIT_MASK_USB_SIE_INTF_ADDR) +#define BIT_SET_USB_SIE_INTF_ADDR(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR(x) | BIT_USB_SIE_INTF_ADDR(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ -#define BIT_RD_SEL BIT(31) +#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16 +#define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff +#define BIT_USB_SIE_INTF_ADDR_V1(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1) \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1) +#define BITS_USB_SIE_INTF_ADDR_V1 \ + (BIT_MASK_USB_SIE_INTF_ADDR_V1 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1) +#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) ((x) & (~BITS_USB_SIE_INTF_ADDR_V1)) +#define BIT_GET_USB_SIE_INTF_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) & \ + BIT_MASK_USB_SIE_INTF_ADDR_V1) +#define BIT_SET_USB_SIE_INTF_ADDR_V1(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) | BIT_USB_SIE_INTF_ADDR_V1(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ -#define BIT_CPU_REG_SEL BIT(31) -#define BIT_USB3_REG_SEL BIT(30) +#define BIT_SHIFT_USB_SIE_INTF_RD 8 +#define BIT_MASK_USB_SIE_INTF_RD 0xff +#define BIT_USB_SIE_INTF_RD(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD) +#define BITS_USB_SIE_INTF_RD \ + (BIT_MASK_USB_SIE_INTF_RD << BIT_SHIFT_USB_SIE_INTF_RD) +#define BIT_CLEAR_USB_SIE_INTF_RD(x) ((x) & (~BITS_USB_SIE_INTF_RD)) +#define BIT_GET_USB_SIE_INTF_RD(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD) +#define BIT_SET_USB_SIE_INTF_RD(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_RD(x) | BIT_USB_SIE_INTF_RD(v)) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ -#define BIT_USB_SIE_INTF_WE_V1 BIT(30) -#define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29) -#define BIT_USB_SIE_SELECT BIT(28) +#define BIT_SHIFT_NPQ_AVAL_PG 8 +#define BIT_MASK_NPQ_AVAL_PG 0xff +#define BIT_NPQ_AVAL_PG(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG) << BIT_SHIFT_NPQ_AVAL_PG) +#define BITS_NPQ_AVAL_PG (BIT_MASK_NPQ_AVAL_PG << BIT_SHIFT_NPQ_AVAL_PG) +#define BIT_CLEAR_NPQ_AVAL_PG(x) ((x) & (~BITS_NPQ_AVAL_PG)) +#define BIT_GET_NPQ_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG) & BIT_MASK_NPQ_AVAL_PG) +#define BIT_SET_NPQ_AVAL_PG(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG(x) | BIT_NPQ_AVAL_PG(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#define BIT_SHIFT_USB_SIE_INTF_WD 0 +#define BIT_MASK_USB_SIE_INTF_WD 0xff +#define BIT_USB_SIE_INTF_WD(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD) +#define BITS_USB_SIE_INTF_WD \ + (BIT_MASK_USB_SIE_INTF_WD << BIT_SHIFT_USB_SIE_INTF_WD) +#define BIT_CLEAR_USB_SIE_INTF_WD(x) ((x) & (~BITS_USB_SIE_INTF_WD)) +#define BIT_GET_USB_SIE_INTF_WD(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD) +#define BIT_SET_USB_SIE_INTF_WD(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_WD(x) | BIT_USB_SIE_INTF_WD(v)) -/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#endif -#define BIT_USB_SIE_INTF_WE BIT(25) -#define BIT_USB_SIE_INTF_BYIOREG BIT(24) +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_USB_SIE_INTF_ADDR 16 -#define BIT_MASK_USB_SIE_INTF_ADDR 0xff -#define BIT_USB_SIE_INTF_ADDR(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR) << BIT_SHIFT_USB_SIE_INTF_ADDR) -#define BIT_GET_USB_SIE_INTF_ADDR(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR) & BIT_MASK_USB_SIE_INTF_ADDR) +/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +#define BIT_PCIE_MIO_EXIT_L1 BIT(19) +#define BIT_PCIE_MIO_EXT BIT(18) +#define BIT_PCIE_MIO_ACK BIT(17) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +#define BIT_PCIE_MIO_RIO BIT(16) -/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16 -#define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff -#define BIT_USB_SIE_INTF_ADDR_V1(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1) -#define BIT_GET_USB_SIE_INTF_ADDR_V1(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) & BIT_MASK_USB_SIE_INTF_ADDR_V1) +/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE 16 +#define BIT_MASK_PCIE_MIO_ADDR_PAGE 0x3 +#define BIT_PCIE_MIO_ADDR_PAGE(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE) << BIT_SHIFT_PCIE_MIO_ADDR_PAGE) +#define BITS_PCIE_MIO_ADDR_PAGE \ + (BIT_MASK_PCIE_MIO_ADDR_PAGE << BIT_SHIFT_PCIE_MIO_ADDR_PAGE) +#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) ((x) & (~BITS_PCIE_MIO_ADDR_PAGE)) +#define BIT_GET_PCIE_MIO_ADDR_PAGE(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE) & BIT_MASK_PCIE_MIO_ADDR_PAGE) +#define BIT_SET_PCIE_MIO_ADDR_PAGE(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) | BIT_PCIE_MIO_ADDR_PAGE(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +#define BIT_PCIE_MIO_IOREG BIT(16) -/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_USB_SIE_INTF_RD 8 -#define BIT_MASK_USB_SIE_INTF_RD 0xff -#define BIT_USB_SIE_INTF_RD(x) (((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD) -#define BIT_GET_USB_SIE_INTF_RD(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD) +/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +#define BIT_PCIE_MIO_BYIOREG BIT(13) +#define BIT_PCIE_MIO_RE BIT(12) + +#define BIT_SHIFT_PCIE_MIO_WE 8 +#define BIT_MASK_PCIE_MIO_WE 0xf +#define BIT_PCIE_MIO_WE(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE) +#define BITS_PCIE_MIO_WE (BIT_MASK_PCIE_MIO_WE << BIT_SHIFT_PCIE_MIO_WE) +#define BIT_CLEAR_PCIE_MIO_WE(x) ((x) & (~BITS_PCIE_MIO_WE)) +#define BIT_GET_PCIE_MIO_WE(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE) +#define BIT_SET_PCIE_MIO_WE(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE(x) | BIT_PCIE_MIO_WE(v)) + +#define BIT_SHIFT_PCIE_MIO_ADDR 0 +#define BIT_MASK_PCIE_MIO_ADDR 0xff +#define BIT_PCIE_MIO_ADDR(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR) +#define BITS_PCIE_MIO_ADDR (BIT_MASK_PCIE_MIO_ADDR << BIT_SHIFT_PCIE_MIO_ADDR) +#define BIT_CLEAR_PCIE_MIO_ADDR(x) ((x) & (~BITS_PCIE_MIO_ADDR)) +#define BIT_GET_PCIE_MIO_ADDR(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR) +#define BIT_SET_PCIE_MIO_ADDR(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR(x) | BIT_PCIE_MIO_ADDR(v)) -#define BIT_SHIFT_USB_SIE_INTF_WD 0 -#define BIT_MASK_USB_SIE_INTF_WD 0xff -#define BIT_USB_SIE_INTF_WD(x) (((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD) -#define BIT_GET_USB_SIE_INTF_WD(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD) +/* 2 REG_PCIE_MIO_INTD (Offset 0x00E8) */ +#define BIT_SHIFT_PCIE_MIO_DATA 0 +#define BIT_MASK_PCIE_MIO_DATA 0xffffffffL +#define BIT_PCIE_MIO_DATA(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA) +#define BITS_PCIE_MIO_DATA (BIT_MASK_PCIE_MIO_DATA << BIT_SHIFT_PCIE_MIO_DATA) +#define BIT_CLEAR_PCIE_MIO_DATA(x) ((x) & (~BITS_PCIE_MIO_DATA)) +#define BIT_GET_PCIE_MIO_DATA(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA) +#define BIT_SET_PCIE_MIO_DATA(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA(x) | BIT_PCIE_MIO_DATA(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_HPON_FSM (Offset 0x00EC) */ -/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +#define BIT_SUSPEND_V1 BIT(31) +#define BIT_FSM_RESUME_V1 BIT(30) +#define BIT_HOST_RESUME_SYNC_V1 BIT(29) +#define BIT_CHIP_PDNB_V1 BIT(28) -#define BIT_PCIE_MIO_EXIT_L1 BIT(19) -#define BIT_PCIE_MIO_EXT BIT(18) -#define BIT_PCIE_MIO_ACK BIT(17) -#define BIT_PCIE_MIO_IOREG BIT(16) +#define BIT_SHIFT_FSM_SUSPEND_V1 25 +#define BIT_MASK_FSM_SUSPEND_V1 0x7 +#define BIT_FSM_SUSPEND_V1(x) \ + (((x) & BIT_MASK_FSM_SUSPEND_V1) << BIT_SHIFT_FSM_SUSPEND_V1) +#define BITS_FSM_SUSPEND_V1 \ + (BIT_MASK_FSM_SUSPEND_V1 << BIT_SHIFT_FSM_SUSPEND_V1) +#define BIT_CLEAR_FSM_SUSPEND_V1(x) ((x) & (~BITS_FSM_SUSPEND_V1)) +#define BIT_GET_FSM_SUSPEND_V1(x) \ + (((x) >> BIT_SHIFT_FSM_SUSPEND_V1) & BIT_MASK_FSM_SUSPEND_V1) +#define BIT_SET_FSM_SUSPEND_V1(x, v) \ + (BIT_CLEAR_FSM_SUSPEND_V1(x) | BIT_FSM_SUSPEND_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_WLRF1 (Offset 0x00EC) */ +#define BIT_SHIFT_XTAL_SEL 25 +#define BIT_MASK_XTAL_SEL 0x3 +#define BIT_XTAL_SEL(x) (((x) & BIT_MASK_XTAL_SEL) << BIT_SHIFT_XTAL_SEL) +#define BITS_XTAL_SEL (BIT_MASK_XTAL_SEL << BIT_SHIFT_XTAL_SEL) +#define BIT_CLEAR_XTAL_SEL(x) ((x) & (~BITS_XTAL_SEL)) +#define BIT_GET_XTAL_SEL(x) (((x) >> BIT_SHIFT_XTAL_SEL) & BIT_MASK_XTAL_SEL) +#define BIT_SET_XTAL_SEL(x, v) (BIT_CLEAR_XTAL_SEL(x) | BIT_XTAL_SEL(v)) -/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ +#endif -#define BIT_PCIE_MIO_BYIOREG BIT(13) -#define BIT_PCIE_MIO_RE BIT(12) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PCIE_MIO_WE 8 -#define BIT_MASK_PCIE_MIO_WE 0xf -#define BIT_PCIE_MIO_WE(x) (((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE) -#define BIT_GET_PCIE_MIO_WE(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE) +/* 2 REG_WLRF1 (Offset 0x00EC) */ +#define BIT_SHIFT_WLRF1_CTRL 24 +#define BIT_MASK_WLRF1_CTRL 0xff +#define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL) +#define BITS_WLRF1_CTRL (BIT_MASK_WLRF1_CTRL << BIT_SHIFT_WLRF1_CTRL) +#define BIT_CLEAR_WLRF1_CTRL(x) ((x) & (~BITS_WLRF1_CTRL)) +#define BIT_GET_WLRF1_CTRL(x) \ + (((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL) +#define BIT_SET_WLRF1_CTRL(x, v) (BIT_CLEAR_WLRF1_CTRL(x) | BIT_WLRF1_CTRL(v)) -#define BIT_SHIFT_PCIE_MIO_ADDR 0 -#define BIT_MASK_PCIE_MIO_ADDR 0xff -#define BIT_PCIE_MIO_ADDR(x) (((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR) -#define BIT_GET_PCIE_MIO_ADDR(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_PCIE_MIO_INTD (Offset 0x00E8) */ +/* 2 REG_HPON_FSM (Offset 0x00EC) */ +#define BIT_PMC_ALD_V1 BIT(24) -#define BIT_SHIFT_PCIE_MIO_DATA 0 -#define BIT_MASK_PCIE_MIO_DATA 0xffffffffL -#define BIT_PCIE_MIO_DATA(x) (((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA) -#define BIT_GET_PCIE_MIO_DATA(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA) +#define BIT_SHIFT_HCI_SEL_1 22 +#define BIT_MASK_HCI_SEL_1 0x3 +#define BIT_HCI_SEL_1(x) (((x) & BIT_MASK_HCI_SEL_1) << BIT_SHIFT_HCI_SEL_1) +#define BITS_HCI_SEL_1 (BIT_MASK_HCI_SEL_1 << BIT_SHIFT_HCI_SEL_1) +#define BIT_CLEAR_HCI_SEL_1(x) ((x) & (~BITS_HCI_SEL_1)) +#define BIT_GET_HCI_SEL_1(x) (((x) >> BIT_SHIFT_HCI_SEL_1) & BIT_MASK_HCI_SEL_1) +#define BIT_SET_HCI_SEL_1(x, v) (BIT_CLEAR_HCI_SEL_1(x) | BIT_HCI_SEL_1(v)) +#define BIT_LOAD_DONE_V1 BIT(21) +#define BIT_CNT_MATCH BIT(20) +#define BIT_TIMEUP_V1 BIT(19) +#define BIT_SPS_12V_VLD BIT(18) +#define BIT_PCIERST_V1 BIT(17) +#define BIT_HOST_CLK_VLD BIT(16) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +/* 2 REG_WLRF1 (Offset 0x00EC) */ -/* 2 REG_HPON_FSM (Offset 0x00EC) */ +#define BIT_SHIFT_WLRF2_CTRL 16 +#define BIT_MASK_WLRF2_CTRL 0xff +#define BIT_WLRF2_CTRL(x) (((x) & BIT_MASK_WLRF2_CTRL) << BIT_SHIFT_WLRF2_CTRL) +#define BITS_WLRF2_CTRL (BIT_MASK_WLRF2_CTRL << BIT_SHIFT_WLRF2_CTRL) +#define BIT_CLEAR_WLRF2_CTRL(x) ((x) & (~BITS_WLRF2_CTRL)) +#define BIT_GET_WLRF2_CTRL(x) \ + (((x) >> BIT_SHIFT_WLRF2_CTRL) & BIT_MASK_WLRF2_CTRL) +#define BIT_SET_WLRF2_CTRL(x, v) (BIT_CLEAR_WLRF2_CTRL(x) | BIT_WLRF2_CTRL(v)) -#define BIT_SUSPEND_V1 BIT(31) -#define BIT_FSM_RESUME_V1 BIT(30) -#define BIT_HOST_RESUME_SYNC_V1 BIT(29) -#define BIT_CHIP_PDNB_V1 BIT(28) +#endif -#define BIT_SHIFT_FSM_SUSPEND_V1 25 -#define BIT_MASK_FSM_SUSPEND_V1 0x7 -#define BIT_FSM_SUSPEND_V1(x) (((x) & BIT_MASK_FSM_SUSPEND_V1) << BIT_SHIFT_FSM_SUSPEND_V1) -#define BIT_GET_FSM_SUSPEND_V1(x) (((x) >> BIT_SHIFT_FSM_SUSPEND_V1) & BIT_MASK_FSM_SUSPEND_V1) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_PMC_ALD_V1 BIT(24) +/* 2 REG_HPON_FSM (Offset 0x00EC) */ -#endif +#define BIT_PMC_WR_V1 BIT(15) +#define BIT_PMC_DATA_V1 BIT(14) +#define BIT_SHIFT_PMC_ADDR_V1 8 +#define BIT_MASK_PMC_ADDR_V1 0x3f +#define BIT_PMC_ADDR_V1(x) \ + (((x) & BIT_MASK_PMC_ADDR_V1) << BIT_SHIFT_PMC_ADDR_V1) +#define BITS_PMC_ADDR_V1 (BIT_MASK_PMC_ADDR_V1 << BIT_SHIFT_PMC_ADDR_V1) +#define BIT_CLEAR_PMC_ADDR_V1(x) ((x) & (~BITS_PMC_ADDR_V1)) +#define BIT_GET_PMC_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_PMC_ADDR_V1) & BIT_MASK_PMC_ADDR_V1) +#define BIT_SET_PMC_ADDR_V1(x, v) \ + (BIT_CLEAR_PMC_ADDR_V1(x) | BIT_PMC_ADDR_V1(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) /* 2 REG_WLRF1 (Offset 0x00EC) */ - -#define BIT_SHIFT_WLRF1_CTRL 24 -#define BIT_MASK_WLRF1_CTRL 0xff -#define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL) -#define BIT_GET_WLRF1_CTRL(x) (((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL) - +#define BIT_SHIFT_WLRF3_CTRL 8 +#define BIT_MASK_WLRF3_CTRL 0xff +#define BIT_WLRF3_CTRL(x) (((x) & BIT_MASK_WLRF3_CTRL) << BIT_SHIFT_WLRF3_CTRL) +#define BITS_WLRF3_CTRL (BIT_MASK_WLRF3_CTRL << BIT_SHIFT_WLRF3_CTRL) +#define BIT_CLEAR_WLRF3_CTRL(x) ((x) & (~BITS_WLRF3_CTRL)) +#define BIT_GET_WLRF3_CTRL(x) \ + (((x) >> BIT_SHIFT_WLRF3_CTRL) & BIT_MASK_WLRF3_CTRL) +#define BIT_SET_WLRF3_CTRL(x, v) (BIT_CLEAR_WLRF3_CTRL(x) | BIT_WLRF3_CTRL(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_HPON_FSM (Offset 0x00EC) */ +#define BIT_PMC_COUNT_EN_V1 BIT(7) -#define BIT_SHIFT_HCI_SEL_1 22 -#define BIT_MASK_HCI_SEL_1 0x3 -#define BIT_HCI_SEL_1(x) (((x) & BIT_MASK_HCI_SEL_1) << BIT_SHIFT_HCI_SEL_1) -#define BIT_GET_HCI_SEL_1(x) (((x) >> BIT_SHIFT_HCI_SEL_1) & BIT_MASK_HCI_SEL_1) +#define BIT_SHIFT_FSM_STATE_V1 0 +#define BIT_MASK_FSM_STATE_V1 0x7f +#define BIT_FSM_STATE_V1(x) \ + (((x) & BIT_MASK_FSM_STATE_V1) << BIT_SHIFT_FSM_STATE_V1) +#define BITS_FSM_STATE_V1 (BIT_MASK_FSM_STATE_V1 << BIT_SHIFT_FSM_STATE_V1) +#define BIT_CLEAR_FSM_STATE_V1(x) ((x) & (~BITS_FSM_STATE_V1)) +#define BIT_GET_FSM_STATE_V1(x) \ + (((x) >> BIT_SHIFT_FSM_STATE_V1) & BIT_MASK_FSM_STATE_V1) +#define BIT_SET_FSM_STATE_V1(x, v) \ + (BIT_CLEAR_FSM_STATE_V1(x) | BIT_FSM_STATE_V1(v)) -#define BIT_LOAD_DONE_V1 BIT(21) -#define BIT_CNT_MATCH BIT(20) -#define BIT_TIMEUP_V1 BIT(19) -#define BIT_SPS_12V_VLD BIT(18) -#define BIT_PCIERST_V1 BIT(17) -#define BIT_HOST_CLK_VLD BIT(16) -#define BIT_PMC_WR_V1 BIT(15) -#define BIT_PMC_DATA_V1 BIT(14) - -#define BIT_SHIFT_PMC_ADDR_V1 8 -#define BIT_MASK_PMC_ADDR_V1 0x3f -#define BIT_PMC_ADDR_V1(x) (((x) & BIT_MASK_PMC_ADDR_V1) << BIT_SHIFT_PMC_ADDR_V1) -#define BIT_GET_PMC_ADDR_V1(x) (((x) >> BIT_SHIFT_PMC_ADDR_V1) & BIT_MASK_PMC_ADDR_V1) +#endif -#define BIT_PMC_COUNT_EN_V1 BIT(7) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FSM_STATE_V1 0 -#define BIT_MASK_FSM_STATE_V1 0x7f -#define BIT_FSM_STATE_V1(x) (((x) & BIT_MASK_FSM_STATE_V1) << BIT_SHIFT_FSM_STATE_V1) -#define BIT_GET_FSM_STATE_V1(x) (((x) >> BIT_SHIFT_FSM_STATE_V1) & BIT_MASK_FSM_STATE_V1) +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_SHIFT_TRP_ICFG 28 +#define BIT_MASK_TRP_ICFG 0xf +#define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG) +#define BITS_TRP_ICFG (BIT_MASK_TRP_ICFG << BIT_SHIFT_TRP_ICFG) +#define BIT_CLEAR_TRP_ICFG(x) ((x) & (~BITS_TRP_ICFG)) +#define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG) +#define BIT_SET_TRP_ICFG(x, v) (BIT_CLEAR_TRP_ICFG(x) | BIT_TRP_ICFG(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_RF_TYPE_ID BIT(27) -#define BIT_SHIFT_TRP_ICFG 28 -#define BIT_MASK_TRP_ICFG 0xf -#define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG) -#define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_BD_HCI_SEL BIT(26) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_RF_TYPE_ID BIT(27) -#define BIT_BD_HCI_SEL BIT(26) +#define BIT_LDO_VLD BIT(26) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_SHIFT_BD_HCI_SEL_V1 26 +#define BIT_MASK_BD_HCI_SEL_V1 0x3 +#define BIT_BD_HCI_SEL_V1(x) \ + (((x) & BIT_MASK_BD_HCI_SEL_V1) << BIT_SHIFT_BD_HCI_SEL_V1) +#define BITS_BD_HCI_SEL_V1 (BIT_MASK_BD_HCI_SEL_V1 << BIT_SHIFT_BD_HCI_SEL_V1) +#define BIT_CLEAR_BD_HCI_SEL_V1(x) ((x) & (~BITS_BD_HCI_SEL_V1)) +#define BIT_GET_BD_HCI_SEL_V1(x) \ + (((x) >> BIT_SHIFT_BD_HCI_SEL_V1) & BIT_MASK_BD_HCI_SEL_V1) +#define BIT_SET_BD_HCI_SEL_V1(x, v) \ + (BIT_CLEAR_BD_HCI_SEL_V1(x) | BIT_BD_HCI_SEL_V1(v)) -#define BIT_SHIFT_BD_HCI_SEL 26 -#define BIT_MASK_BD_HCI_SEL 0x3 -#define BIT_BD_HCI_SEL(x) (((x) & BIT_MASK_BD_HCI_SEL) << BIT_SHIFT_BD_HCI_SEL) -#define BIT_GET_BD_HCI_SEL(x) (((x) >> BIT_SHIFT_BD_HCI_SEL) & BIT_MASK_BD_HCI_SEL) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_BD_PKG_SEL BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_BD_PKG_SEL BIT(25) +#define BIT_SPSLDO_SEL BIT(24) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_SPSLDO_SEL BIT(24) +#define BIT_INTERNAL_EXTERNAL_SWR BIT(24) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_LDO_SPS_SEL BIT(24) +#define BIT_LDO_SPS_SEL BIT(24) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_RTL_ID BIT(23) -#define BIT_PAD_HWPD_IDN BIT(22) +#define BIT_RTL_ID BIT(23) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_TESTMODE BIT(20) +#define BIT_PAD_HWPD_IDN BIT(22) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_DIS_WL BIT(22) -/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PSC_TESTCFG 20 -#define BIT_MASK_PSC_TESTCFG 0x3 -#define BIT_PSC_TESTCFG(x) (((x) & BIT_MASK_PSC_TESTCFG) << BIT_SHIFT_PSC_TESTCFG) -#define BIT_GET_PSC_TESTCFG(x) (((x) >> BIT_SHIFT_PSC_TESTCFG) & BIT_MASK_PSC_TESTCFG) +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_TESTMODE BIT(20) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_SHIFT_PSC_TESTCFG 20 +#define BIT_MASK_PSC_TESTCFG 0x3 +#define BIT_PSC_TESTCFG(x) \ + (((x) & BIT_MASK_PSC_TESTCFG) << BIT_SHIFT_PSC_TESTCFG) +#define BITS_PSC_TESTCFG (BIT_MASK_PSC_TESTCFG << BIT_SHIFT_PSC_TESTCFG) +#define BIT_CLEAR_PSC_TESTCFG(x) ((x) & (~BITS_PSC_TESTCFG)) +#define BIT_GET_PSC_TESTCFG(x) \ + (((x) >> BIT_SHIFT_PSC_TESTCFG) & BIT_MASK_PSC_TESTCFG) +#define BIT_SET_PSC_TESTCFG(x, v) \ + (BIT_CLEAR_PSC_TESTCFG(x) | BIT_PSC_TESTCFG(v)) -/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VENDOR_ID 16 -#define BIT_MASK_VENDOR_ID 0xf -#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) -#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_SHIFT_VENDOR_ID 16 +#define BIT_MASK_VENDOR_ID 0xf +#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) +#define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID) +#define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID)) +#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) +#define BIT_SET_VENDOR_ID(x, v) (BIT_CLEAR_VENDOR_ID(x) | BIT_VENDOR_ID(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_SHIFT_CHIP_VER_V2 16 +#define BIT_MASK_CHIP_VER_V2 0xf +#define BIT_CHIP_VER_V2(x) \ + (((x) & BIT_MASK_CHIP_VER_V2) << BIT_SHIFT_CHIP_VER_V2) +#define BITS_CHIP_VER_V2 (BIT_MASK_CHIP_VER_V2 << BIT_SHIFT_CHIP_VER_V2) +#define BIT_CLEAR_CHIP_VER_V2(x) ((x) & (~BITS_CHIP_VER_V2)) +#define BIT_GET_CHIP_VER_V2(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_V2) & BIT_MASK_CHIP_VER_V2) +#define BIT_SET_CHIP_VER_V2(x, v) \ + (BIT_CLEAR_CHIP_VER_V2(x) | BIT_CHIP_VER_V2(v)) -#define BIT_SHIFT_CHIP_VER_V2 16 -#define BIT_MASK_CHIP_VER_V2 0xf -#define BIT_CHIP_VER_V2(x) (((x) & BIT_MASK_CHIP_VER_V2) << BIT_SHIFT_CHIP_VER_V2) -#define BIT_GET_CHIP_VER_V2(x) (((x) >> BIT_SHIFT_CHIP_VER_V2) & BIT_MASK_CHIP_VER_V2) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_SHIFT_CHIP_VER 12 +#define BIT_MASK_CHIP_VER 0xf +#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) +#define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER) +#define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER)) +#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) +#define BIT_SET_CHIP_VER(x, v) (BIT_CLEAR_CHIP_VER(x) | BIT_CHIP_VER(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_TST_MODE_SEL BIT(11) -#define BIT_SHIFT_CHIP_VER 12 -#define BIT_MASK_CHIP_VER 0xf -#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) -#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_BD_MAC3 BIT(11) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_IC_MACPHY_MODE BIT(11) +#define BIT_IC_MACPHY_MODE BIT(11) #endif - -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_BD_MAC3 BIT(11) +#define BIT_BD_MAC1 BIT(10) +#define BIT_BD_MAC2 BIT(9) +#define BIT_SIC_IDLE BIT(8) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_BD_MAC1 BIT(10) -#define BIT_BD_MAC2 BIT(9) -#define BIT_SIC_IDLE BIT(8) -#define BIT_SW_OFFLOAD_EN BIT(7) +#define BIT_SW_OFFLOAD_EN BIT(7) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_OCP_SHUTDN BIT(6) +#define BIT_OCP_SHUTDN BIT(6) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_OCP_SHUTDN_1 BIT(6) +#define BIT_OCP_SHUTDN_1 BIT(6) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_V15_VLD BIT(5) +#define BIT_V15_VLD BIT(5) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_V12_VLD BIT(5) +#define BIT_V12_VLD BIT(5) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_PCIRSTB BIT(4) +#define BIT_PCIRSTB BIT(4) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_PCLK_VLD BIT(3) +#define BIT_PCLK_VLD BIT(3) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_PCLK_VLD_1 BIT(3) +#define BIT_PCLK_VLD_1 BIT(3) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_UCLK_VLD BIT(2) +#define BIT_UCLK_VLD BIT(2) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_ACLK_VLD BIT(1) +#define BIT_ACLK_VLD BIT(1) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ -#define BIT_M200CLK_VLD_V1 BIT(1) +#define BIT_M200CLK_VLD_V1 BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#define BIT_XCLK_VLD BIT(0) -/* 2 REG_SYS_CFG1 (Offset 0x00F0) */ +#endif -#define BIT_XCLK_VLD BIT(0) +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SYM_OSC32K_OUTSEL BIT(31) +#define BIT_BTGP_WAKE_BT_LOC_BIT0 BIT(31) + +#define BIT_SHIFT_SYM_SEC_CLKSEL 30 +#define BIT_MASK_SYM_SEC_CLKSEL 0x3 +#define BIT_SYM_SEC_CLKSEL(x) \ + (((x) & BIT_MASK_SYM_SEC_CLKSEL) << BIT_SHIFT_SYM_SEC_CLKSEL) +#define BITS_SYM_SEC_CLKSEL \ + (BIT_MASK_SYM_SEC_CLKSEL << BIT_SHIFT_SYM_SEC_CLKSEL) +#define BIT_CLEAR_SYM_SEC_CLKSEL(x) ((x) & (~BITS_SYM_SEC_CLKSEL)) +#define BIT_GET_SYM_SEC_CLKSEL(x) \ + (((x) >> BIT_SHIFT_SYM_SEC_CLKSEL) & BIT_MASK_SYM_SEC_CLKSEL) +#define BIT_SET_SYM_SEC_CLKSEL(x, v) \ + (BIT_CLEAR_SYM_SEC_CLKSEL(x) | BIT_SYM_SEC_CLKSEL(v)) + +#define BIT_SHIFT_WL_GPIO_SEL 30 +#define BIT_MASK_WL_GPIO_SEL 0x3 +#define BIT_WL_GPIO_SEL(x) \ + (((x) & BIT_MASK_WL_GPIO_SEL) << BIT_SHIFT_WL_GPIO_SEL) +#define BITS_WL_GPIO_SEL (BIT_MASK_WL_GPIO_SEL << BIT_SHIFT_WL_GPIO_SEL) +#define BIT_CLEAR_WL_GPIO_SEL(x) ((x) & (~BITS_WL_GPIO_SEL)) +#define BIT_GET_WL_GPIO_SEL(x) \ + (((x) >> BIT_SHIFT_WL_GPIO_SEL) & BIT_MASK_WL_GPIO_SEL) +#define BIT_SET_WL_GPIO_SEL(x, v) \ + (BIT_CLEAR_WL_GPIO_SEL(x) | BIT_WL_GPIO_SEL(v)) + +#define BIT_SHIFT_BT_MCM_CTRL_LOC 29 +#define BIT_MASK_BT_MCM_CTRL_LOC 0x3 +#define BIT_BT_MCM_CTRL_LOC(x) \ + (((x) & BIT_MASK_BT_MCM_CTRL_LOC) << BIT_SHIFT_BT_MCM_CTRL_LOC) +#define BITS_BT_MCM_CTRL_LOC \ + (BIT_MASK_BT_MCM_CTRL_LOC << BIT_SHIFT_BT_MCM_CTRL_LOC) +#define BIT_CLEAR_BT_MCM_CTRL_LOC(x) ((x) & (~BITS_BT_MCM_CTRL_LOC)) +#define BIT_GET_BT_MCM_CTRL_LOC(x) \ + (((x) >> BIT_SHIFT_BT_MCM_CTRL_LOC) & BIT_MASK_BT_MCM_CTRL_LOC) +#define BIT_SET_BT_MCM_CTRL_LOC(x, v) \ + (BIT_CLEAR_BT_MCM_CTRL_LOC(x) | BIT_BT_MCM_CTRL_LOC(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RF_RL_ID 28 -#define BIT_MASK_RF_RL_ID 0xf -#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) -#define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_RF_RL_ID 28 +#define BIT_MASK_RF_RL_ID 0xf +#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) +#define BITS_RF_RL_ID (BIT_MASK_RF_RL_ID << BIT_SHIFT_RF_RL_ID) +#define BIT_CLEAR_RF_RL_ID(x) ((x) & (~BITS_RF_RL_ID)) +#define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID) +#define BIT_SET_RF_RL_ID(x, v) (BIT_CLEAR_RF_RL_ID(x) | BIT_RF_RL_ID(v)) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_U3_CLK_VLD BIT(27) -#define BIT_PRST_VLD_V1 BIT(26) -#define BIT_PDN BIT(25) -#define BIT_OCP_SHUTDN_V1 BIT(24) -#define BIT_PCLK_VLD_V1 BIT(23) -#define BIT_U2_CLK_VLD BIT(22) -#define BIT_PLL_CLK_VLD BIT(21) -#define BIT_XCK_VLD BIT(20) +#define BIT_SHIFT_SYM_MAC_CLKSEL 28 +#define BIT_MASK_SYM_MAC_CLKSEL 0x3 +#define BIT_SYM_MAC_CLKSEL(x) \ + (((x) & BIT_MASK_SYM_MAC_CLKSEL) << BIT_SHIFT_SYM_MAC_CLKSEL) +#define BITS_SYM_MAC_CLKSEL \ + (BIT_MASK_SYM_MAC_CLKSEL << BIT_SHIFT_SYM_MAC_CLKSEL) +#define BIT_CLEAR_SYM_MAC_CLKSEL(x) ((x) & (~BITS_SYM_MAC_CLKSEL)) +#define BIT_GET_SYM_MAC_CLKSEL(x) \ + (((x) >> BIT_SHIFT_SYM_MAC_CLKSEL) & BIT_MASK_SYM_MAC_CLKSEL) +#define BIT_SET_SYM_MAC_CLKSEL(x, v) \ + (BIT_CLEAR_SYM_MAC_CLKSEL(x) | BIT_SYM_MAC_CLKSEL(v)) + +#define BIT_SHIFT_SW_DPDT_LOC 27 +#define BIT_MASK_SW_DPDT_LOC 0x3 +#define BIT_SW_DPDT_LOC(x) \ + (((x) & BIT_MASK_SW_DPDT_LOC) << BIT_SHIFT_SW_DPDT_LOC) +#define BITS_SW_DPDT_LOC (BIT_MASK_SW_DPDT_LOC << BIT_SHIFT_SW_DPDT_LOC) +#define BIT_CLEAR_SW_DPDT_LOC(x) ((x) & (~BITS_SW_DPDT_LOC)) +#define BIT_GET_SW_DPDT_LOC(x) \ + (((x) >> BIT_SHIFT_SW_DPDT_LOC) & BIT_MASK_SW_DPDT_LOC) +#define BIT_SET_SW_DPDT_LOC(x, v) \ + (BIT_CLEAR_SW_DPDT_LOC(x) | BIT_SW_DPDT_LOC(v)) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_HPHY_ICFG BIT(19) +#define BIT_U3_CLK_VLD BIT(27) #endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_CK200M_VLD BIT(19) -#define BIT_BTEN_TRAP BIT(18) -#define BIT_PKG_EN_V1 BIT(17) +#define BIT_WLGP_HW_DIS_LOC_BIT0 BIT(26) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_PRST_VLD_V1 BIT(26) +#define BIT_PDN BIT(25) -/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_SEL_0XC0 16 -#define BIT_MASK_SEL_0XC0 0x3 -#define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0) -#define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_PKG_SEL 24 +#define BIT_MASK_PKG_SEL 0x3 +#define BIT_PKG_SEL(x) (((x) & BIT_MASK_PKG_SEL) << BIT_SHIFT_PKG_SEL) +#define BITS_PKG_SEL (BIT_MASK_PKG_SEL << BIT_SHIFT_PKG_SEL) +#define BIT_CLEAR_PKG_SEL(x) ((x) & (~BITS_PKG_SEL)) +#define BIT_GET_PKG_SEL(x) (((x) >> BIT_SHIFT_PKG_SEL) & BIT_MASK_PKG_SEL) +#define BIT_SET_PKG_SEL(x, v) (BIT_CLEAR_PKG_SEL(x) | BIT_PKG_SEL(v)) + +#define BIT_SHIFT_SYM_OSC32K_RCAL 24 +#define BIT_MASK_SYM_OSC32K_RCAL 0x3f +#define BIT_SYM_OSC32K_RCAL(x) \ + (((x) & BIT_MASK_SYM_OSC32K_RCAL) << BIT_SHIFT_SYM_OSC32K_RCAL) +#define BITS_SYM_OSC32K_RCAL \ + (BIT_MASK_SYM_OSC32K_RCAL << BIT_SHIFT_SYM_OSC32K_RCAL) +#define BIT_CLEAR_SYM_OSC32K_RCAL(x) ((x) & (~BITS_SYM_OSC32K_RCAL)) +#define BIT_GET_SYM_OSC32K_RCAL(x) \ + (((x) >> BIT_SHIFT_SYM_OSC32K_RCAL) & BIT_MASK_SYM_OSC32K_RCAL) +#define BIT_SET_SYM_OSC32K_RCAL(x, v) \ + (BIT_CLEAR_SYM_OSC32K_RCAL(x) | BIT_SYM_OSC32K_RCAL(v)) + +#define BIT_SHIFT_SW_GPIO_B_PD 24 +#define BIT_MASK_SW_GPIO_B_PD 0xff +#define BIT_SW_GPIO_B_PD(x) \ + (((x) & BIT_MASK_SW_GPIO_B_PD) << BIT_SHIFT_SW_GPIO_B_PD) +#define BITS_SW_GPIO_B_PD (BIT_MASK_SW_GPIO_B_PD << BIT_SHIFT_SW_GPIO_B_PD) +#define BIT_CLEAR_SW_GPIO_B_PD(x) ((x) & (~BITS_SW_GPIO_B_PD)) +#define BIT_GET_SW_GPIO_B_PD(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_B_PD) & BIT_MASK_SW_GPIO_B_PD) +#define BIT_SET_SW_GPIO_B_PD(x, v) \ + (BIT_CLEAR_SW_GPIO_B_PD(x) | BIT_SW_GPIO_B_PD(v)) + +#define BIT_SHIFT_SW_GPIO_B_IN 24 +#define BIT_MASK_SW_GPIO_B_IN 0xff +#define BIT_SW_GPIO_B_IN(x) \ + (((x) & BIT_MASK_SW_GPIO_B_IN) << BIT_SHIFT_SW_GPIO_B_IN) +#define BITS_SW_GPIO_B_IN (BIT_MASK_SW_GPIO_B_IN << BIT_SHIFT_SW_GPIO_B_IN) +#define BIT_CLEAR_SW_GPIO_B_IN(x) ((x) & (~BITS_SW_GPIO_B_IN)) +#define BIT_GET_SW_GPIO_B_IN(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_B_IN) & BIT_MASK_SW_GPIO_B_IN) +#define BIT_SET_SW_GPIO_B_IN(x, v) \ + (BIT_CLEAR_SW_GPIO_B_IN(x) | BIT_SW_GPIO_B_IN(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_TRAP_LDO_SPS_V1 BIT(16) -#define BIT_MACRDY BIT(15) -#define BIT_12V_VLD BIT(14) -#define BIT_U3PHY_RST BIT(13) -#define BIT_USB2_SEL_V1 BIT(12) +#define BIT_OCP_SHUTDN_V1 BIT(24) #endif - -#if (HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_ANT_SEL_01_LOC 23 +#define BIT_MASK_ANT_SEL_01_LOC 0x7 +#define BIT_ANT_SEL_01_LOC(x) \ + (((x) & BIT_MASK_ANT_SEL_01_LOC) << BIT_SHIFT_ANT_SEL_01_LOC) +#define BITS_ANT_SEL_01_LOC \ + (BIT_MASK_ANT_SEL_01_LOC << BIT_SHIFT_ANT_SEL_01_LOC) +#define BIT_CLEAR_ANT_SEL_01_LOC(x) ((x) & (~BITS_ANT_SEL_01_LOC)) +#define BIT_GET_ANT_SEL_01_LOC(x) \ + (((x) >> BIT_SHIFT_ANT_SEL_01_LOC) & BIT_MASK_ANT_SEL_01_LOC) +#define BIT_SET_ANT_SEL_01_LOC(x, v) \ + (BIT_CLEAR_ANT_SEL_01_LOC(x) | BIT_ANT_SEL_01_LOC(v)) + +#define BIT_SHIFT_AUTOLOADABLE_AT_1FC 23 +#define BIT_MASK_AUTOLOADABLE_AT_1FC 0x3f +#define BIT_AUTOLOADABLE_AT_1FC(x) \ + (((x) & BIT_MASK_AUTOLOADABLE_AT_1FC) << BIT_SHIFT_AUTOLOADABLE_AT_1FC) +#define BITS_AUTOLOADABLE_AT_1FC \ + (BIT_MASK_AUTOLOADABLE_AT_1FC << BIT_SHIFT_AUTOLOADABLE_AT_1FC) +#define BIT_CLEAR_AUTOLOADABLE_AT_1FC(x) ((x) & (~BITS_AUTOLOADABLE_AT_1FC)) +#define BIT_GET_AUTOLOADABLE_AT_1FC(x) \ + (((x) >> BIT_SHIFT_AUTOLOADABLE_AT_1FC) & BIT_MASK_AUTOLOADABLE_AT_1FC) +#define BIT_SET_AUTOLOADABLE_AT_1FC(x, v) \ + (BIT_CLEAR_AUTOLOADABLE_AT_1FC(x) | BIT_AUTOLOADABLE_AT_1FC(v)) -#define BIT_SHIFT_HCI_SEL_V3 12 -#define BIT_MASK_HCI_SEL_V3 0x7 -#define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3) -#define BIT_GET_HCI_SEL_V3(x) (((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_PCLK_VLD_V1 BIT(23) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_USB_OPERATION_MODE BIT(10) -#define BIT_BT_PDN BIT(9) -#define BIT_AUTO_WLPON BIT(8) +#define BIT_BT_DISN_EN_V1 BIT(22) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ - -#define BIT_SHIFT_TRAP_ICFG 8 -#define BIT_MASK_TRAP_ICFG 0xf -#define BIT_TRAP_ICFG(x) (((x) & BIT_MASK_TRAP_ICFG) << BIT_SHIFT_TRAP_ICFG) -#define BIT_GET_TRAP_ICFG(x) (((x) >> BIT_SHIFT_TRAP_ICFG) & BIT_MASK_TRAP_ICFG) - +#define BIT_U2_CLK_VLD BIT(22) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_WL_MODE BIT(7) +#define BIT_SHIFT_ANT_SEL_23_LOC 21 +#define BIT_MASK_ANT_SEL_23_LOC 0x3 +#define BIT_ANT_SEL_23_LOC(x) \ + (((x) & BIT_MASK_ANT_SEL_23_LOC) << BIT_SHIFT_ANT_SEL_23_LOC) +#define BITS_ANT_SEL_23_LOC \ + (BIT_MASK_ANT_SEL_23_LOC << BIT_SHIFT_ANT_SEL_23_LOC) +#define BIT_CLEAR_ANT_SEL_23_LOC(x) ((x) & (~BITS_ANT_SEL_23_LOC)) +#define BIT_GET_ANT_SEL_23_LOC(x) \ + (((x) >> BIT_SHIFT_ANT_SEL_23_LOC) & BIT_MASK_ANT_SEL_23_LOC) +#define BIT_SET_ANT_SEL_23_LOC(x, v) \ + (BIT_CLEAR_ANT_SEL_23_LOC(x) | BIT_ANT_SEL_23_LOC(v)) -#endif +#define BIT_BT_SUSN_LOC BIT(21) +#endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_WLAN_ID BIT(7) +#define BIT_PLL_CLK_VLD BIT(21) #endif - -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_PKG_SEL_HCI BIT(6) +#define BIT_SHIFT_SW_ICFG 20 +#define BIT_MASK_SW_ICFG 0xf +#define BIT_SW_ICFG(x) (((x) & BIT_MASK_SW_ICFG) << BIT_SHIFT_SW_ICFG) +#define BITS_SW_ICFG (BIT_MASK_SW_ICFG << BIT_SHIFT_SW_ICFG) +#define BIT_CLEAR_SW_ICFG(x) ((x) & (~BITS_SW_ICFG)) +#define BIT_GET_SW_ICFG(x) (((x) >> BIT_SHIFT_SW_ICFG) & BIT_MASK_SW_ICFG) +#define BIT_SET_SW_ICFG(x, v) (BIT_CLEAR_SW_ICFG(x) | BIT_SW_ICFG(v)) -#endif +#define BIT_SYM_CONF_BYTE_ENB BIT(20) +#define BIT_WLBB_RFE_LED1 BIT(20) +#endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_ALDN BIT(6) -#define BIT_BTCOEX_CMDEN BIT(5) +#define BIT_XCK_VLD BIT(20) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_HPHY_ICFG BIT(19) -/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#endif + +#if (HALMAC_8192F_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_SHIFT_HCI_SEL 4 -#define BIT_MASK_HCI_SEL 0x3 -#define BIT_HCI_SEL(x) (((x) & BIT_MASK_HCI_SEL) << BIT_SHIFT_HCI_SEL) -#define BIT_GET_HCI_SEL(x) (((x) >> BIT_SHIFT_HCI_SEL) & BIT_MASK_HCI_SEL) +#define BIT_SHIFT_EXTCK32K_LOC 19 +#define BIT_MASK_EXTCK32K_LOC 0x3 +#define BIT_EXTCK32K_LOC(x) \ + (((x) & BIT_MASK_EXTCK32K_LOC) << BIT_SHIFT_EXTCK32K_LOC) +#define BITS_EXTCK32K_LOC (BIT_MASK_EXTCK32K_LOC << BIT_SHIFT_EXTCK32K_LOC) +#define BIT_CLEAR_EXTCK32K_LOC(x) ((x) & (~BITS_EXTCK32K_LOC)) +#define BIT_GET_EXTCK32K_LOC(x) \ + (((x) >> BIT_SHIFT_EXTCK32K_LOC) & BIT_MASK_EXTCK32K_LOC) +#define BIT_SET_EXTCK32K_LOC(x, v) \ + (BIT_CLEAR_EXTCK32K_LOC(x) | BIT_EXTCK32K_LOC(v)) +#define BIT_WLGP_LED1_EN BIT(19) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_BT_EN BIT(4) +#define BIT_CK200M_VLD BIT(19) #endif - -#if (HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ - -#define BIT_SHIFT_PAD_HCI_SEL_V1 3 -#define BIT_MASK_PAD_HCI_SEL_V1 0x7 -#define BIT_PAD_HCI_SEL_V1(x) (((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1) -#define BIT_GET_PAD_HCI_SEL_V1(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1) - +#define BIT_BT_COEX_MBOX_LOC BIT(18) +#define BIT_WLGP_ANT23_EN BIT(18) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_HCI_SEL_EMBEDDED BIT(18) -/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_PAD_HCI_SEL 2 -#define BIT_MASK_PAD_HCI_SEL 0x3 -#define BIT_PAD_HCI_SEL(x) (((x) & BIT_MASK_PAD_HCI_SEL) << BIT_SHIFT_PAD_HCI_SEL) -#define BIT_GET_PAD_HCI_SEL(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL) & BIT_MASK_PAD_HCI_SEL) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_BTEN_TRAP BIT(18) +#define BIT_PKG_EN_V1 BIT(17) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_SEL_0XC0 16 +#define BIT_MASK_SEL_0XC0 0x3 +#define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0) +#define BITS_SEL_0XC0 (BIT_MASK_SEL_0XC0 << BIT_SHIFT_SEL_0XC0) +#define BIT_CLEAR_SEL_0XC0(x) ((x) & (~BITS_SEL_0XC0)) +#define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0) +#define BIT_SET_SEL_0XC0(x, v) (BIT_CLEAR_SEL_0XC0(x) | BIT_SEL_0XC0(v)) -/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_HCI_SEL_V2 2 -#define BIT_MASK_HCI_SEL_V2 0x3 -#define BIT_HCI_SEL_V2(x) (((x) & BIT_MASK_HCI_SEL_V2) << BIT_SHIFT_HCI_SEL_V2) -#define BIT_GET_HCI_SEL_V2(x) (((x) >> BIT_SHIFT_HCI_SEL_V2) & BIT_MASK_HCI_SEL_V2) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_TST_MOD_SEL BIT(1) +#define BIT_SYM_MCUFWDL_DDMA_EN BIT(16) +#define BIT_SYM_SPIC_BOOT_ADDR_CMP BIT(16) + +#define BIT_SHIFT_SYM_OSC32K_CLKGEN0 16 +#define BIT_MASK_SYM_OSC32K_CLKGEN0 0xff +#define BIT_SYM_OSC32K_CLKGEN0(x) \ + (((x) & BIT_MASK_SYM_OSC32K_CLKGEN0) << BIT_SHIFT_SYM_OSC32K_CLKGEN0) +#define BITS_SYM_OSC32K_CLKGEN0 \ + (BIT_MASK_SYM_OSC32K_CLKGEN0 << BIT_SHIFT_SYM_OSC32K_CLKGEN0) +#define BIT_CLEAR_SYM_OSC32K_CLKGEN0(x) ((x) & (~BITS_SYM_OSC32K_CLKGEN0)) +#define BIT_GET_SYM_OSC32K_CLKGEN0(x) \ + (((x) >> BIT_SHIFT_SYM_OSC32K_CLKGEN0) & BIT_MASK_SYM_OSC32K_CLKGEN0) +#define BIT_SET_SYM_OSC32K_CLKGEN0(x, v) \ + (BIT_CLEAR_SYM_OSC32K_CLKGEN0(x) | BIT_SYM_OSC32K_CLKGEN0(v)) + +#define BIT_SHIFT_CRC16_RESULT 16 +#define BIT_MASK_CRC16_RESULT 0xffff +#define BIT_CRC16_RESULT(x) \ + (((x) & BIT_MASK_CRC16_RESULT) << BIT_SHIFT_CRC16_RESULT) +#define BITS_CRC16_RESULT (BIT_MASK_CRC16_RESULT << BIT_SHIFT_CRC16_RESULT) +#define BIT_CLEAR_CRC16_RESULT(x) ((x) & (~BITS_CRC16_RESULT)) +#define BIT_GET_CRC16_RESULT(x) \ + (((x) >> BIT_SHIFT_CRC16_RESULT) & BIT_MASK_CRC16_RESULT) +#define BIT_SET_CRC16_RESULT(x, v) \ + (BIT_CLEAR_CRC16_RESULT(x) | BIT_CRC16_RESULT(v)) + +#define BIT_SHIFT_BTGP_LEDIO_LOC 16 +#define BIT_MASK_BTGP_LEDIO_LOC 0x3 +#define BIT_BTGP_LEDIO_LOC(x) \ + (((x) & BIT_MASK_BTGP_LEDIO_LOC) << BIT_SHIFT_BTGP_LEDIO_LOC) +#define BITS_BTGP_LEDIO_LOC \ + (BIT_MASK_BTGP_LEDIO_LOC << BIT_SHIFT_BTGP_LEDIO_LOC) +#define BIT_CLEAR_BTGP_LEDIO_LOC(x) ((x) & (~BITS_BTGP_LEDIO_LOC)) +#define BIT_GET_BTGP_LEDIO_LOC(x) \ + (((x) >> BIT_SHIFT_BTGP_LEDIO_LOC) & BIT_MASK_BTGP_LEDIO_LOC) +#define BIT_SET_BTGP_LEDIO_LOC(x, v) \ + (BIT_CLEAR_BTGP_LEDIO_LOC(x) | BIT_BTGP_LEDIO_LOC(v)) + +#define BIT_SHIFT_FEM_EN 16 +#define BIT_MASK_FEM_EN 0x3 +#define BIT_FEM_EN(x) (((x) & BIT_MASK_FEM_EN) << BIT_SHIFT_FEM_EN) +#define BITS_FEM_EN (BIT_MASK_FEM_EN << BIT_SHIFT_FEM_EN) +#define BIT_CLEAR_FEM_EN(x) ((x) & (~BITS_FEM_EN)) +#define BIT_GET_FEM_EN(x) (((x) >> BIT_SHIFT_FEM_EN) & BIT_MASK_FEM_EN) +#define BIT_SET_FEM_EN(x, v) (BIT_CLEAR_FEM_EN(x) | BIT_FEM_EN(v)) + +#define BIT_SHIFT_SW_GPIO_B_PU 16 +#define BIT_MASK_SW_GPIO_B_PU 0xff +#define BIT_SW_GPIO_B_PU(x) \ + (((x) & BIT_MASK_SW_GPIO_B_PU) << BIT_SHIFT_SW_GPIO_B_PU) +#define BITS_SW_GPIO_B_PU (BIT_MASK_SW_GPIO_B_PU << BIT_SHIFT_SW_GPIO_B_PU) +#define BIT_CLEAR_SW_GPIO_B_PU(x) ((x) & (~BITS_SW_GPIO_B_PU)) +#define BIT_GET_SW_GPIO_B_PU(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_B_PU) & BIT_MASK_SW_GPIO_B_PU) +#define BIT_SET_SW_GPIO_B_PU(x, v) \ + (BIT_CLEAR_SW_GPIO_B_PU(x) | BIT_SW_GPIO_B_PU(v)) + +#define BIT_SHIFT_SYM_INT_PERIODIC 16 +#define BIT_MASK_SYM_INT_PERIODIC 0x3ff +#define BIT_SYM_INT_PERIODIC(x) \ + (((x) & BIT_MASK_SYM_INT_PERIODIC) << BIT_SHIFT_SYM_INT_PERIODIC) +#define BITS_SYM_INT_PERIODIC \ + (BIT_MASK_SYM_INT_PERIODIC << BIT_SHIFT_SYM_INT_PERIODIC) +#define BIT_CLEAR_SYM_INT_PERIODIC(x) ((x) & (~BITS_SYM_INT_PERIODIC)) +#define BIT_GET_SYM_INT_PERIODIC(x) \ + (((x) >> BIT_SHIFT_SYM_INT_PERIODIC) & BIT_MASK_SYM_INT_PERIODIC) +#define BIT_SET_SYM_INT_PERIODIC(x, v) \ + (BIT_CLEAR_SYM_INT_PERIODIC(x) | BIT_SYM_INT_PERIODIC(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_TRAP_LDO_SPS_V1 BIT(16) -/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_EFS_HCI_SEL 0 -#define BIT_MASK_EFS_HCI_SEL 0x3 -#define BIT_EFS_HCI_SEL(x) (((x) & BIT_MASK_EFS_HCI_SEL) << BIT_SHIFT_EFS_HCI_SEL) -#define BIT_GET_EFS_HCI_SEL(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL) & BIT_MASK_EFS_HCI_SEL) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_IDV_DPDTSEL_P BIT(15) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_PAD_HWPDB BIT(0) +#define BIT_MACRDY BIT(15) #endif - -#if (HALMAC_8822B_SUPPORT) - +#if (HALMAC_8192F_SUPPORT) /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_LTE_COEX_UART_LOC 14 +#define BIT_MASK_LTE_COEX_UART_LOC 0x3 +#define BIT_LTE_COEX_UART_LOC(x) \ + (((x) & BIT_MASK_LTE_COEX_UART_LOC) << BIT_SHIFT_LTE_COEX_UART_LOC) +#define BITS_LTE_COEX_UART_LOC \ + (BIT_MASK_LTE_COEX_UART_LOC << BIT_SHIFT_LTE_COEX_UART_LOC) +#define BIT_CLEAR_LTE_COEX_UART_LOC(x) ((x) & (~BITS_LTE_COEX_UART_LOC)) +#define BIT_GET_LTE_COEX_UART_LOC(x) \ + (((x) >> BIT_SHIFT_LTE_COEX_UART_LOC) & BIT_MASK_LTE_COEX_UART_LOC) +#define BIT_SET_LTE_COEX_UART_LOC(x, v) \ + (BIT_CLEAR_LTE_COEX_UART_LOC(x) | BIT_LTE_COEX_UART_LOC(v)) -#define BIT_SHIFT_EFS_HCI_SEL_V1 0 -#define BIT_MASK_EFS_HCI_SEL_V1 0x7 -#define BIT_EFS_HCI_SEL_V1(x) (((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1) -#define BIT_GET_EFS_HCI_SEL_V1(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1) - +#define BIT_IDV_DPDTSEL_N BIT(14) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_12V_VLD BIT(14) +#define BIT_U3PHY_RST BIT(13) -/* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ +#endif -#define BIT_SIO_ALDN BIT(19) -#define BIT_USB_ALDN BIT(18) -#define BIT_PCI_ALDN BIT(17) -#define BIT_SYS_ALDN BIT(16) +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_EPVID1 8 -#define BIT_MASK_EPVID1 0xff -#define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1) -#define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_SYM_LDOA12V_WT 12 +#define BIT_MASK_SYM_LDOA12V_WT 0x3 +#define BIT_SYM_LDOA12V_WT(x) \ + (((x) & BIT_MASK_SYM_LDOA12V_WT) << BIT_SHIFT_SYM_LDOA12V_WT) +#define BITS_SYM_LDOA12V_WT \ + (BIT_MASK_SYM_LDOA12V_WT << BIT_SHIFT_SYM_LDOA12V_WT) +#define BIT_CLEAR_SYM_LDOA12V_WT(x) ((x) & (~BITS_SYM_LDOA12V_WT)) +#define BIT_GET_SYM_LDOA12V_WT(x) \ + (((x) >> BIT_SHIFT_SYM_LDOA12V_WT) & BIT_MASK_SYM_LDOA12V_WT) +#define BIT_SET_SYM_LDOA12V_WT(x, v) \ + (BIT_CLEAR_SYM_LDOA12V_WT(x) | BIT_SYM_LDOA12V_WT(v)) + +#define BIT_SHIFT_SYM_OSC32K_TEMP_COMP 12 +#define BIT_MASK_SYM_OSC32K_TEMP_COMP 0xf +#define BIT_SYM_OSC32K_TEMP_COMP(x) \ + (((x) & BIT_MASK_SYM_OSC32K_TEMP_COMP) \ + << BIT_SHIFT_SYM_OSC32K_TEMP_COMP) +#define BITS_SYM_OSC32K_TEMP_COMP \ + (BIT_MASK_SYM_OSC32K_TEMP_COMP << BIT_SHIFT_SYM_OSC32K_TEMP_COMP) +#define BIT_CLEAR_SYM_OSC32K_TEMP_COMP(x) ((x) & (~BITS_SYM_OSC32K_TEMP_COMP)) +#define BIT_GET_SYM_OSC32K_TEMP_COMP(x) \ + (((x) >> BIT_SHIFT_SYM_OSC32K_TEMP_COMP) & \ + BIT_MASK_SYM_OSC32K_TEMP_COMP) +#define BIT_SET_SYM_OSC32K_TEMP_COMP(x, v) \ + (BIT_CLEAR_SYM_OSC32K_TEMP_COMP(x) | BIT_SYM_OSC32K_TEMP_COMP(v)) + +#define BIT_SHIFT_LTE_3W_LOC 12 +#define BIT_MASK_LTE_3W_LOC 0x3 +#define BIT_LTE_3W_LOC(x) (((x) & BIT_MASK_LTE_3W_LOC) << BIT_SHIFT_LTE_3W_LOC) +#define BITS_LTE_3W_LOC (BIT_MASK_LTE_3W_LOC << BIT_SHIFT_LTE_3W_LOC) +#define BIT_CLEAR_LTE_3W_LOC(x) ((x) & (~BITS_LTE_3W_LOC)) +#define BIT_GET_LTE_3W_LOC(x) \ + (((x) >> BIT_SHIFT_LTE_3W_LOC) & BIT_MASK_LTE_3W_LOC) +#define BIT_SET_LTE_3W_LOC(x, v) (BIT_CLEAR_LTE_3W_LOC(x) | BIT_LTE_3W_LOC(v)) + +#define BIT_SHIFT_HW_EXTWOL_LOC 12 +#define BIT_MASK_HW_EXTWOL_LOC 0x3 +#define BIT_HW_EXTWOL_LOC(x) \ + (((x) & BIT_MASK_HW_EXTWOL_LOC) << BIT_SHIFT_HW_EXTWOL_LOC) +#define BITS_HW_EXTWOL_LOC (BIT_MASK_HW_EXTWOL_LOC << BIT_SHIFT_HW_EXTWOL_LOC) +#define BIT_CLEAR_HW_EXTWOL_LOC(x) ((x) & (~BITS_HW_EXTWOL_LOC)) +#define BIT_GET_HW_EXTWOL_LOC(x) \ + (((x) >> BIT_SHIFT_HW_EXTWOL_LOC) & BIT_MASK_HW_EXTWOL_LOC) +#define BIT_SET_HW_EXTWOL_LOC(x, v) \ + (BIT_CLEAR_HW_EXTWOL_LOC(x) | BIT_HW_EXTWOL_LOC(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_EPVID0 0 -#define BIT_MASK_EPVID0 0xff -#define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0) -#define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_HCI_SEL_V4 12 +#define BIT_MASK_HCI_SEL_V4 0x3 +#define BIT_HCI_SEL_V4(x) (((x) & BIT_MASK_HCI_SEL_V4) << BIT_SHIFT_HCI_SEL_V4) +#define BITS_HCI_SEL_V4 (BIT_MASK_HCI_SEL_V4 << BIT_SHIFT_HCI_SEL_V4) +#define BIT_CLEAR_HCI_SEL_V4(x) ((x) & (~BITS_HCI_SEL_V4)) +#define BIT_GET_HCI_SEL_V4(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V4) & BIT_MASK_HCI_SEL_V4) +#define BIT_SET_HCI_SEL_V4(x, v) (BIT_CLEAR_HCI_SEL_V4(x) | BIT_HCI_SEL_V4(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ - -#define BIT_USB2_SEL_1 BIT(31) -#define BIT_USB3PHY_RST BIT(30) -#define BIT_U3_TERM_DET BIT(29) -#define BIT_USB23_DBG_SEL BIT(24) +#define BIT_USB2_SEL_V1 BIT(12) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_HCI_SEL_EMBEDED BIT(8) +#define BIT_SHIFT_HCI_SEL_V3 12 +#define BIT_MASK_HCI_SEL_V3 0x7 +#define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3) +#define BITS_HCI_SEL_V3 (BIT_MASK_HCI_SEL_V3 << BIT_SHIFT_HCI_SEL_V3) +#define BIT_CLEAR_HCI_SEL_V3(x) ((x) & (~BITS_HCI_SEL_V3)) +#define BIT_GET_HCI_SEL_V3(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3) +#define BIT_SET_HCI_SEL_V3(x, v) (BIT_CLEAR_HCI_SEL_V3(x) | BIT_HCI_SEL_V3(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SIC_LOC BIT(11) -/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HW_ID 0 -#define BIT_MASK_HW_ID 0xff -#define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID) -#define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_USB_OPERATION_MODE BIT(10) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_BTGP_WAKE_LOC 10 +#define BIT_MASK_BTGP_WAKE_LOC 0x3 +#define BIT_BTGP_WAKE_LOC(x) \ + (((x) & BIT_MASK_BTGP_WAKE_LOC) << BIT_SHIFT_BTGP_WAKE_LOC) +#define BITS_BTGP_WAKE_LOC (BIT_MASK_BTGP_WAKE_LOC << BIT_SHIFT_BTGP_WAKE_LOC) +#define BIT_CLEAR_BTGP_WAKE_LOC(x) ((x) & (~BITS_BTGP_WAKE_LOC)) +#define BIT_GET_BTGP_WAKE_LOC(x) \ + (((x) >> BIT_SHIFT_BTGP_WAKE_LOC) & BIT_MASK_BTGP_WAKE_LOC) +#define BIT_SET_BTGP_WAKE_LOC(x, v) \ + (BIT_CLEAR_BTGP_WAKE_LOC(x) | BIT_BTGP_WAKE_LOC(v)) -/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CHIPID 0 -#define BIT_MASK_CHIPID 0xff -#define BIT_CHIPID(x) (((x) & BIT_MASK_CHIPID) << BIT_SHIFT_CHIPID) -#define BIT_GET_CHIPID(x) (((x) >> BIT_SHIFT_CHIPID) & BIT_MASK_CHIPID) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_BT_PDN BIT(9) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_CR (Offset 0x0100) */ +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_MACIO_TIMEOUT_EN BIT(29) +#define BIT_SHIFT_WLMAC_DBG_LOC 9 +#define BIT_MASK_WLMAC_DBG_LOC 0x3 +#define BIT_WLMAC_DBG_LOC(x) \ + (((x) & BIT_MASK_WLMAC_DBG_LOC) << BIT_SHIFT_WLMAC_DBG_LOC) +#define BITS_WLMAC_DBG_LOC (BIT_MASK_WLMAC_DBG_LOC << BIT_SHIFT_WLMAC_DBG_LOC) +#define BIT_CLEAR_WLMAC_DBG_LOC(x) ((x) & (~BITS_WLMAC_DBG_LOC)) +#define BIT_GET_WLMAC_DBG_LOC(x) \ + (((x) >> BIT_SHIFT_WLMAC_DBG_LOC) & BIT_MASK_WLMAC_DBG_LOC) +#define BIT_SET_WLMAC_DBG_LOC(x, v) \ + (BIT_CLEAR_WLMAC_DBG_LOC(x) | BIT_WLMAC_DBG_LOC(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_AUTO_WLPON BIT(8) -/* 2 REG_CR (Offset 0x0100) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_LBMODE 24 -#define BIT_MASK_LBMODE 0x1f -#define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE) -#define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SYM_MCU_CLK_DIV2 BIT(8) + +#define BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ 8 +#define BIT_MASK_SYM_OSC32K_LDO_V18ADJ 0xf +#define BIT_SYM_OSC32K_LDO_V18ADJ(x) \ + (((x) & BIT_MASK_SYM_OSC32K_LDO_V18ADJ) \ + << BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ) +#define BITS_SYM_OSC32K_LDO_V18ADJ \ + (BIT_MASK_SYM_OSC32K_LDO_V18ADJ << BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ) +#define BIT_CLEAR_SYM_OSC32K_LDO_V18ADJ(x) ((x) & (~BITS_SYM_OSC32K_LDO_V18ADJ)) +#define BIT_GET_SYM_OSC32K_LDO_V18ADJ(x) \ + (((x) >> BIT_SHIFT_SYM_OSC32K_LDO_V18ADJ) & \ + BIT_MASK_SYM_OSC32K_LDO_V18ADJ) +#define BIT_SET_SYM_OSC32K_LDO_V18ADJ(x, v) \ + (BIT_CLEAR_SYM_OSC32K_LDO_V18ADJ(x) | BIT_SYM_OSC32K_LDO_V18ADJ(v)) + +#define BIT_SHIFT_HOST_WAKE_WL_LOC 8 +#define BIT_MASK_HOST_WAKE_WL_LOC 0x3 +#define BIT_HOST_WAKE_WL_LOC(x) \ + (((x) & BIT_MASK_HOST_WAKE_WL_LOC) << BIT_SHIFT_HOST_WAKE_WL_LOC) +#define BITS_HOST_WAKE_WL_LOC \ + (BIT_MASK_HOST_WAKE_WL_LOC << BIT_SHIFT_HOST_WAKE_WL_LOC) +#define BIT_CLEAR_HOST_WAKE_WL_LOC(x) ((x) & (~BITS_HOST_WAKE_WL_LOC)) +#define BIT_GET_HOST_WAKE_WL_LOC(x) \ + (((x) >> BIT_SHIFT_HOST_WAKE_WL_LOC) & BIT_MASK_HOST_WAKE_WL_LOC) +#define BIT_SET_HOST_WAKE_WL_LOC(x, v) \ + (BIT_CLEAR_HOST_WAKE_WL_LOC(x) | BIT_HOST_WAKE_WL_LOC(v)) + +#define BIT_SHIFT_SW_GPIO_B_OE2 8 +#define BIT_MASK_SW_GPIO_B_OE2 0xff +#define BIT_SW_GPIO_B_OE2(x) \ + (((x) & BIT_MASK_SW_GPIO_B_OE2) << BIT_SHIFT_SW_GPIO_B_OE2) +#define BITS_SW_GPIO_B_OE2 (BIT_MASK_SW_GPIO_B_OE2 << BIT_SHIFT_SW_GPIO_B_OE2) +#define BIT_CLEAR_SW_GPIO_B_OE2(x) ((x) & (~BITS_SW_GPIO_B_OE2)) +#define BIT_GET_SW_GPIO_B_OE2(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_B_OE2) & BIT_MASK_SW_GPIO_B_OE2) +#define BIT_SET_SW_GPIO_B_OE2(x, v) \ + (BIT_CLEAR_SW_GPIO_B_OE2(x) | BIT_SW_GPIO_B_OE2(v)) -#define BIT_SHIFT_NETYPE1 18 -#define BIT_MASK_NETYPE1 0x3 -#define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1) -#define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_NETYPE0 16 -#define BIT_MASK_NETYPE0 0x3 -#define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0) -#define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_TRAP_ICFG 8 +#define BIT_MASK_TRAP_ICFG 0xf +#define BIT_TRAP_ICFG(x) (((x) & BIT_MASK_TRAP_ICFG) << BIT_SHIFT_TRAP_ICFG) +#define BITS_TRAP_ICFG (BIT_MASK_TRAP_ICFG << BIT_SHIFT_TRAP_ICFG) +#define BIT_CLEAR_TRAP_ICFG(x) ((x) & (~BITS_TRAP_ICFG)) +#define BIT_GET_TRAP_ICFG(x) (((x) >> BIT_SHIFT_TRAP_ICFG) & BIT_MASK_TRAP_ICFG) +#define BIT_SET_TRAP_ICFG(x, v) (BIT_CLEAR_TRAP_ICFG(x) | BIT_TRAP_ICFG(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_CR (Offset 0x0100) */ +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_STAT_FUNC_RST BIT(13) +#define BIT_WL_MODE BIT(7) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -/* 2 REG_CR (Offset 0x0100) */ +#define BIT_SPI_FLASH_LOC BIT(7) -#define BIT_PTA_I2C_MBOX_EN BIT(12) +#define BIT_SHIFT_WLPHY_DBG_LOC 7 +#define BIT_MASK_WLPHY_DBG_LOC 0x3 +#define BIT_WLPHY_DBG_LOC(x) \ + (((x) & BIT_MASK_WLPHY_DBG_LOC) << BIT_SHIFT_WLPHY_DBG_LOC) +#define BITS_WLPHY_DBG_LOC (BIT_MASK_WLPHY_DBG_LOC << BIT_SHIFT_WLPHY_DBG_LOC) +#define BIT_CLEAR_WLPHY_DBG_LOC(x) ((x) & (~BITS_WLPHY_DBG_LOC)) +#define BIT_GET_WLPHY_DBG_LOC(x) \ + (((x) >> BIT_SHIFT_WLPHY_DBG_LOC) & BIT_MASK_WLPHY_DBG_LOC) +#define BIT_SET_WLPHY_DBG_LOC(x, v) \ + (BIT_CLEAR_WLPHY_DBG_LOC(x) | BIT_WLPHY_DBG_LOC(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_WLAN_ID BIT(7) -/* 2 REG_CR (Offset 0x0100) */ +#endif -#define BIT_I2C_MAILBOX_EN BIT(12) -#define BIT_SHCUT_EN BIT(11) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ + +#define BIT_PKG_SEL_HCI BIT(6) +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192F_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -/* 2 REG_CR (Offset 0x0100) */ +#define BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR 6 +#define BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR 0x3 +#define BIT_SYM_OSC32K_COMP_LOAD_CUR(x) \ + (((x) & BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR) \ + << BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR) +#define BITS_SYM_OSC32K_COMP_LOAD_CUR \ + (BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR \ + << BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR) +#define BIT_CLEAR_SYM_OSC32K_COMP_LOAD_CUR(x) \ + ((x) & (~BITS_SYM_OSC32K_COMP_LOAD_CUR)) +#define BIT_GET_SYM_OSC32K_COMP_LOAD_CUR(x) \ + (((x) >> BIT_SHIFT_SYM_OSC32K_COMP_LOAD_CUR) & \ + BIT_MASK_SYM_OSC32K_COMP_LOAD_CUR) +#define BIT_SET_SYM_OSC32K_COMP_LOAD_CUR(x, v) \ + (BIT_CLEAR_SYM_OSC32K_COMP_LOAD_CUR(x) | \ + BIT_SYM_OSC32K_COMP_LOAD_CUR(v)) -#define BIT_32K_CAL_TMR_EN BIT(10) -#define BIT_MAC_SEC_EN BIT(9) -#define BIT_ENSWBCN BIT(8) -#define BIT_MACRXEN BIT(7) -#define BIT_MACTXEN BIT(6) -#define BIT_SCHEDULE_EN BIT(5) -#define BIT_PROTOCOL_EN BIT(4) -#define BIT_RXDMA_EN BIT(3) -#define BIT_TXDMA_EN BIT(2) -#define BIT_HCI_RXDMA_EN BIT(1) -#define BIT_HCI_TXDMA_EN BIT(0) +#define BIT_WLGP_HW_DIS_LOC_BIT1 BIT(6) +#define BIT_XTAL_CKOUT_LOC BIT(6) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_ALDN BIT(6) -/* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0 -#define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff -#define BIT_PKT_BUFF_ACCESS_CTRL(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) -#define BIT_GET_PKT_BUFF_ACCESS_CTRL(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_XTAL_CLKREQ_EN BIT(5) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_BTCOEX_CMDEN BIT(5) -/* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ +#endif -#define BIT_TSF_CLK_IDX BIT(15) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_HCI_SEL 4 +#define BIT_MASK_HCI_SEL 0x3 +#define BIT_HCI_SEL(x) (((x) & BIT_MASK_HCI_SEL) << BIT_SHIFT_HCI_SEL) +#define BITS_HCI_SEL (BIT_MASK_HCI_SEL << BIT_SHIFT_HCI_SEL) +#define BIT_CLEAR_HCI_SEL(x) ((x) & (~BITS_HCI_SEL)) +#define BIT_GET_HCI_SEL(x) (((x) >> BIT_SHIFT_HCI_SEL) & BIT_MASK_HCI_SEL) +#define BIT_SET_HCI_SEL(x, v) (BIT_CLEAR_HCI_SEL(x) | BIT_HCI_SEL(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_TSF_CLK_STABLE BIT(15) +#define BIT_SYM_BOOT_SEL BIT(4) + +#define BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR 4 +#define BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR 0x3 +#define BIT_SYM_OSC32K_COMP_LATCH_CUR(x) \ + (((x) & BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR) \ + << BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR) +#define BITS_SYM_OSC32K_COMP_LATCH_CUR \ + (BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR \ + << BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR) +#define BIT_CLEAR_SYM_OSC32K_COMP_LATCH_CUR(x) \ + ((x) & (~BITS_SYM_OSC32K_COMP_LATCH_CUR)) +#define BIT_GET_SYM_OSC32K_COMP_LATCH_CUR(x) \ + (((x) >> BIT_SHIFT_SYM_OSC32K_COMP_LATCH_CUR) & \ + BIT_MASK_SYM_OSC32K_COMP_LATCH_CUR) +#define BIT_SET_SYM_OSC32K_COMP_LATCH_CUR(x, v) \ + (BIT_CLEAR_SYM_OSC32K_COMP_LATCH_CUR(x) | \ + BIT_SYM_OSC32K_COMP_LATCH_CUR(v)) + +#define BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY 4 +#define BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY 0x3ff +#define BIT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x) \ + (((x) & BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY) \ + << BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY) +#define BITS_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY \ + (BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY \ + << BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY) +#define BIT_CLEAR_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x) \ + ((x) & (~BITS_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY)) +#define BIT_GET_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x) \ + (((x) >> BIT_SHIFT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY) & \ + BIT_MASK_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY) +#define BIT_SET_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x, v) \ + (BIT_CLEAR_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(x) | \ + BIT_CRC16_CHECK_MAXIMUM_ADDRESS_BOUNDARY(v)) + +#define BIT_HOST_WAKE_WL_EN BIT(4) + +#define BIT_SHIFT_XTAL_CLKREQ_LOC 4 +#define BIT_MASK_XTAL_CLKREQ_LOC 0x3 +#define BIT_XTAL_CLKREQ_LOC(x) \ + (((x) & BIT_MASK_XTAL_CLKREQ_LOC) << BIT_SHIFT_XTAL_CLKREQ_LOC) +#define BITS_XTAL_CLKREQ_LOC \ + (BIT_MASK_XTAL_CLKREQ_LOC << BIT_SHIFT_XTAL_CLKREQ_LOC) +#define BIT_CLEAR_XTAL_CLKREQ_LOC(x) ((x) & (~BITS_XTAL_CLKREQ_LOC)) +#define BIT_GET_XTAL_CLKREQ_LOC(x) \ + (((x) >> BIT_SHIFT_XTAL_CLKREQ_LOC) & BIT_MASK_XTAL_CLKREQ_LOC) +#define BIT_SET_XTAL_CLKREQ_LOC(x, v) \ + (BIT_CLEAR_XTAL_CLKREQ_LOC(x) | BIT_XTAL_CLKREQ_LOC(v)) -#define BIT_SHIFT_I2C_M_BUS_GNT_FW 4 -#define BIT_MASK_I2C_M_BUS_GNT_FW 0x7 -#define BIT_I2C_M_BUS_GNT_FW(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW) -#define BIT_GET_I2C_M_BUS_GNT_FW(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW) +#endif -#define BIT_I2C_M_GNT_FW BIT(3) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_I2C_M_SPEED 1 -#define BIT_MASK_I2C_M_SPEED 0x3 -#define BIT_I2C_M_SPEED(x) (((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED) -#define BIT_GET_I2C_M_SPEED(x) (((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_I2C_M_UNLOCK BIT(0) +#define BIT_BT_EN BIT(4) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_BTGP_MCM_UART_EN BIT(3) +#define BIT_WLGP_UART_LOC BIT(3) -/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TXDMA_CMQ_MAP 16 -#define BIT_MASK_TXDMA_CMQ_MAP 0x3 -#define BIT_TXDMA_CMQ_MAP(x) (((x) & BIT_MASK_TXDMA_CMQ_MAP) << BIT_SHIFT_TXDMA_CMQ_MAP) -#define BIT_GET_TXDMA_CMQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_CMQ_MAP) & BIT_MASK_TXDMA_CMQ_MAP) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_PAD_HCI_SEL_V2 3 +#define BIT_MASK_PAD_HCI_SEL_V2 0x3 +#define BIT_PAD_HCI_SEL_V2(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V2) << BIT_SHIFT_PAD_HCI_SEL_V2) +#define BITS_PAD_HCI_SEL_V2 \ + (BIT_MASK_PAD_HCI_SEL_V2 << BIT_SHIFT_PAD_HCI_SEL_V2) +#define BIT_CLEAR_PAD_HCI_SEL_V2(x) ((x) & (~BITS_PAD_HCI_SEL_V2)) +#define BIT_GET_PAD_HCI_SEL_V2(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2) & BIT_MASK_PAD_HCI_SEL_V2) +#define BIT_SET_PAD_HCI_SEL_V2(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V2(x) | BIT_PAD_HCI_SEL_V2(v)) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_PAD_HCI_SEL_V1 3 +#define BIT_MASK_PAD_HCI_SEL_V1 0x7 +#define BIT_PAD_HCI_SEL_V1(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1) +#define BITS_PAD_HCI_SEL_V1 \ + (BIT_MASK_PAD_HCI_SEL_V1 << BIT_SHIFT_PAD_HCI_SEL_V1) +#define BIT_CLEAR_PAD_HCI_SEL_V1(x) ((x) & (~BITS_PAD_HCI_SEL_V1)) +#define BIT_GET_PAD_HCI_SEL_V1(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1) +#define BIT_SET_PAD_HCI_SEL_V1(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V1(x) | BIT_PAD_HCI_SEL_V1(v)) -/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TXDMA_HIQ_MAP 14 -#define BIT_MASK_TXDMA_HIQ_MAP 0x3 -#define BIT_TXDMA_HIQ_MAP(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) -#define BIT_GET_TXDMA_HIQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_PAD_HCI_SEL 2 +#define BIT_MASK_PAD_HCI_SEL 0x3 +#define BIT_PAD_HCI_SEL(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL) << BIT_SHIFT_PAD_HCI_SEL) +#define BITS_PAD_HCI_SEL (BIT_MASK_PAD_HCI_SEL << BIT_SHIFT_PAD_HCI_SEL) +#define BIT_CLEAR_PAD_HCI_SEL(x) ((x) & (~BITS_PAD_HCI_SEL)) +#define BIT_GET_PAD_HCI_SEL(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL) & BIT_MASK_PAD_HCI_SEL) +#define BIT_SET_PAD_HCI_SEL(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL(x) | BIT_PAD_HCI_SEL(v)) -#define BIT_SHIFT_TXDMA_MGQ_MAP 12 -#define BIT_MASK_TXDMA_MGQ_MAP 0x3 -#define BIT_TXDMA_MGQ_MAP(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) -#define BIT_GET_TXDMA_MGQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_TXDMA_BKQ_MAP 10 -#define BIT_MASK_TXDMA_BKQ_MAP 0x3 -#define BIT_TXDMA_BKQ_MAP(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) -#define BIT_GET_TXDMA_BKQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR 2 +#define BIT_MASK_SYM_OSC32K_COMP_GM_CUR 0x3 +#define BIT_SYM_OSC32K_COMP_GM_CUR(x) \ + (((x) & BIT_MASK_SYM_OSC32K_COMP_GM_CUR) \ + << BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR) +#define BITS_SYM_OSC32K_COMP_GM_CUR \ + (BIT_MASK_SYM_OSC32K_COMP_GM_CUR << BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR) +#define BIT_CLEAR_SYM_OSC32K_COMP_GM_CUR(x) \ + ((x) & (~BITS_SYM_OSC32K_COMP_GM_CUR)) +#define BIT_GET_SYM_OSC32K_COMP_GM_CUR(x) \ + (((x) >> BIT_SHIFT_SYM_OSC32K_COMP_GM_CUR) & \ + BIT_MASK_SYM_OSC32K_COMP_GM_CUR) +#define BIT_SET_SYM_OSC32K_COMP_GM_CUR(x, v) \ + (BIT_CLEAR_SYM_OSC32K_COMP_GM_CUR(x) | BIT_SYM_OSC32K_COMP_GM_CUR(v)) -#define BIT_SHIFT_TXDMA_BEQ_MAP 8 -#define BIT_MASK_TXDMA_BEQ_MAP 0x3 -#define BIT_TXDMA_BEQ_MAP(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) -#define BIT_GET_TXDMA_BEQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP) +#define BIT_WLGP_MCM_COEXFEN BIT(2) +#endif -#define BIT_SHIFT_TXDMA_VIQ_MAP 6 -#define BIT_MASK_TXDMA_VIQ_MAP 0x3 -#define BIT_TXDMA_VIQ_MAP(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) -#define BIT_GET_TXDMA_VIQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ -#define BIT_SHIFT_TXDMA_VOQ_MAP 4 -#define BIT_MASK_TXDMA_VOQ_MAP 0x3 -#define BIT_TXDMA_VOQ_MAP(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) -#define BIT_GET_TXDMA_VOQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP) - -#define BIT_RXDMA_AGG_EN BIT(2) -#define BIT_RXSHFT_EN BIT(1) -#define BIT_RXDMA_ARBBW_EN BIT(0) +#define BIT_SHIFT_HCI_SEL_V2 2 +#define BIT_MASK_HCI_SEL_V2 0x3 +#define BIT_HCI_SEL_V2(x) (((x) & BIT_MASK_HCI_SEL_V2) << BIT_SHIFT_HCI_SEL_V2) +#define BITS_HCI_SEL_V2 (BIT_MASK_HCI_SEL_V2 << BIT_SHIFT_HCI_SEL_V2) +#define BIT_CLEAR_HCI_SEL_V2(x) ((x) & (~BITS_HCI_SEL_V2)) +#define BIT_GET_HCI_SEL_V2(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V2) & BIT_MASK_HCI_SEL_V2) +#define BIT_SET_HCI_SEL_V2(x, v) (BIT_CLEAR_HCI_SEL_V2(x) | BIT_HCI_SEL_V2(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_BT_COEX_MCM_MBOX BIT(1) -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_BTGP_WAKE_HST_LOC 1 +#define BIT_MASK_BTGP_WAKE_HST_LOC 0x3 +#define BIT_BTGP_WAKE_HST_LOC(x) \ + (((x) & BIT_MASK_BTGP_WAKE_HST_LOC) << BIT_SHIFT_BTGP_WAKE_HST_LOC) +#define BITS_BTGP_WAKE_HST_LOC \ + (BIT_MASK_BTGP_WAKE_HST_LOC << BIT_SHIFT_BTGP_WAKE_HST_LOC) +#define BIT_CLEAR_BTGP_WAKE_HST_LOC(x) ((x) & (~BITS_BTGP_WAKE_HST_LOC)) +#define BIT_GET_BTGP_WAKE_HST_LOC(x) \ + (((x) >> BIT_SHIFT_BTGP_WAKE_HST_LOC) & BIT_MASK_BTGP_WAKE_HST_LOC) +#define BIT_SET_BTGP_WAKE_HST_LOC(x, v) \ + (BIT_CLEAR_BTGP_WAKE_HST_LOC(x) | BIT_BTGP_WAKE_HST_LOC(v)) +#define BIT_SYM_HCI_TADMA_ALLOW BIT(1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_RXFFOVFL_RSV_V1 28 -#define BIT_MASK_RXFFOVFL_RSV_V1 0xf -#define BIT_RXFFOVFL_RSV_V1(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V1) << BIT_SHIFT_RXFFOVFL_RSV_V1) -#define BIT_GET_RXFFOVFL_RSV_V1(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V1) & BIT_MASK_RXFFOVFL_RSV_V1) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_TST_MOD_SEL BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_EFS_HCI_SEL 0 +#define BIT_MASK_EFS_HCI_SEL 0x3 +#define BIT_EFS_HCI_SEL(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL) << BIT_SHIFT_EFS_HCI_SEL) +#define BITS_EFS_HCI_SEL (BIT_MASK_EFS_HCI_SEL << BIT_SHIFT_EFS_HCI_SEL) +#define BIT_CLEAR_EFS_HCI_SEL(x) ((x) & (~BITS_EFS_HCI_SEL)) +#define BIT_GET_EFS_HCI_SEL(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL) & BIT_MASK_EFS_HCI_SEL) +#define BIT_SET_EFS_HCI_SEL(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL(x) | BIT_EFS_HCI_SEL(v)) -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_RXFF0_BNDY 16 -#define BIT_MASK_RXFF0_BNDY 0xffff -#define BIT_RXFF0_BNDY(x) (((x) & BIT_MASK_RXFF0_BNDY) << BIT_SHIFT_RXFF0_BNDY) -#define BIT_GET_RXFF0_BNDY(x) (((x) >> BIT_SHIFT_RXFF0_BNDY) & BIT_MASK_RXFF0_BNDY) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SYM_BOOT_CFG BIT(0) + +#define BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR 0 +#define BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR 0xffff +#define BIT_SYM_SPIC_BOOT_EXT_ADDR(x) \ + (((x) & BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR) \ + << BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR) +#define BITS_SYM_SPIC_BOOT_EXT_ADDR \ + (BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR << BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR) +#define BIT_CLEAR_SYM_SPIC_BOOT_EXT_ADDR(x) \ + ((x) & (~BITS_SYM_SPIC_BOOT_EXT_ADDR)) +#define BIT_GET_SYM_SPIC_BOOT_EXT_ADDR(x) \ + (((x) >> BIT_SHIFT_SYM_SPIC_BOOT_EXT_ADDR) & \ + BIT_MASK_SYM_SPIC_BOOT_EXT_ADDR) +#define BIT_SET_SYM_SPIC_BOOT_EXT_ADDR(x, v) \ + (BIT_CLEAR_SYM_SPIC_BOOT_EXT_ADDR(x) | BIT_SYM_SPIC_BOOT_EXT_ADDR(v)) + +#define BIT_SHIFT_SYM_OSC32K_FREQSEL 0 +#define BIT_MASK_SYM_OSC32K_FREQSEL 0x3 +#define BIT_SYM_OSC32K_FREQSEL(x) \ + (((x) & BIT_MASK_SYM_OSC32K_FREQSEL) << BIT_SHIFT_SYM_OSC32K_FREQSEL) +#define BITS_SYM_OSC32K_FREQSEL \ + (BIT_MASK_SYM_OSC32K_FREQSEL << BIT_SHIFT_SYM_OSC32K_FREQSEL) +#define BIT_CLEAR_SYM_OSC32K_FREQSEL(x) ((x) & (~BITS_SYM_OSC32K_FREQSEL)) +#define BIT_GET_SYM_OSC32K_FREQSEL(x) \ + (((x) >> BIT_SHIFT_SYM_OSC32K_FREQSEL) & BIT_MASK_SYM_OSC32K_FREQSEL) +#define BIT_SET_SYM_OSC32K_FREQSEL(x, v) \ + (BIT_CLEAR_SYM_OSC32K_FREQSEL(x) | BIT_SYM_OSC32K_FREQSEL(v)) + +#define BIT_CRC16_CHECK_ENABLE BIT(0) +#define BIT_SW_GPIO_FUNC BIT(0) +#define BIT_BTGP_WAKE_BT_LOC BIT(0) + +#define BIT_SHIFT_SW_GPIO_A_OUT 0 +#define BIT_MASK_SW_GPIO_A_OUT 0xffffffffL +#define BIT_SW_GPIO_A_OUT(x) \ + (((x) & BIT_MASK_SW_GPIO_A_OUT) << BIT_SHIFT_SW_GPIO_A_OUT) +#define BITS_SW_GPIO_A_OUT (BIT_MASK_SW_GPIO_A_OUT << BIT_SHIFT_SW_GPIO_A_OUT) +#define BIT_CLEAR_SW_GPIO_A_OUT(x) ((x) & (~BITS_SW_GPIO_A_OUT)) +#define BIT_GET_SW_GPIO_A_OUT(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_A_OUT) & BIT_MASK_SW_GPIO_A_OUT) +#define BIT_SET_SW_GPIO_A_OUT(x, v) \ + (BIT_CLEAR_SW_GPIO_A_OUT(x) | BIT_SW_GPIO_A_OUT(v)) + +#define BIT_SHIFT_SW_GPIO_A_OEN 0 +#define BIT_MASK_SW_GPIO_A_OEN 0xffffffffL +#define BIT_SW_GPIO_A_OEN(x) \ + (((x) & BIT_MASK_SW_GPIO_A_OEN) << BIT_SHIFT_SW_GPIO_A_OEN) +#define BITS_SW_GPIO_A_OEN (BIT_MASK_SW_GPIO_A_OEN << BIT_SHIFT_SW_GPIO_A_OEN) +#define BIT_CLEAR_SW_GPIO_A_OEN(x) ((x) & (~BITS_SW_GPIO_A_OEN)) +#define BIT_GET_SW_GPIO_A_OEN(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_A_OEN) & BIT_MASK_SW_GPIO_A_OEN) +#define BIT_SET_SW_GPIO_A_OEN(x, v) \ + (BIT_CLEAR_SW_GPIO_A_OEN(x) | BIT_SW_GPIO_A_OEN(v)) + +#define BIT_SHIFT_SW_GPIO_A_OE2 0 +#define BIT_MASK_SW_GPIO_A_OE2 0xffffffffL +#define BIT_SW_GPIO_A_OE2(x) \ + (((x) & BIT_MASK_SW_GPIO_A_OE2) << BIT_SHIFT_SW_GPIO_A_OE2) +#define BITS_SW_GPIO_A_OE2 (BIT_MASK_SW_GPIO_A_OE2 << BIT_SHIFT_SW_GPIO_A_OE2) +#define BIT_CLEAR_SW_GPIO_A_OE2(x) ((x) & (~BITS_SW_GPIO_A_OE2)) +#define BIT_GET_SW_GPIO_A_OE2(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_A_OE2) & BIT_MASK_SW_GPIO_A_OE2) +#define BIT_SET_SW_GPIO_A_OE2(x, v) \ + (BIT_CLEAR_SW_GPIO_A_OE2(x) | BIT_SW_GPIO_A_OE2(v)) + +#define BIT_SHIFT_SW_GPIO_A_PU 0 +#define BIT_MASK_SW_GPIO_A_PU 0xffffffffL +#define BIT_SW_GPIO_A_PU(x) \ + (((x) & BIT_MASK_SW_GPIO_A_PU) << BIT_SHIFT_SW_GPIO_A_PU) +#define BITS_SW_GPIO_A_PU (BIT_MASK_SW_GPIO_A_PU << BIT_SHIFT_SW_GPIO_A_PU) +#define BIT_CLEAR_SW_GPIO_A_PU(x) ((x) & (~BITS_SW_GPIO_A_PU)) +#define BIT_GET_SW_GPIO_A_PU(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_A_PU) & BIT_MASK_SW_GPIO_A_PU) +#define BIT_SET_SW_GPIO_A_PU(x, v) \ + (BIT_CLEAR_SW_GPIO_A_PU(x) | BIT_SW_GPIO_A_PU(v)) + +#define BIT_SHIFT_SW_GPIO_A_PD 0 +#define BIT_MASK_SW_GPIO_A_PD 0xffffffffL +#define BIT_SW_GPIO_A_PD(x) \ + (((x) & BIT_MASK_SW_GPIO_A_PD) << BIT_SHIFT_SW_GPIO_A_PD) +#define BITS_SW_GPIO_A_PD (BIT_MASK_SW_GPIO_A_PD << BIT_SHIFT_SW_GPIO_A_PD) +#define BIT_CLEAR_SW_GPIO_A_PD(x) ((x) & (~BITS_SW_GPIO_A_PD)) +#define BIT_GET_SW_GPIO_A_PD(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_A_PD) & BIT_MASK_SW_GPIO_A_PD) +#define BIT_SET_SW_GPIO_A_PD(x, v) \ + (BIT_CLEAR_SW_GPIO_A_PD(x) | BIT_SW_GPIO_A_PD(v)) + +#define BIT_SHIFT_SW_GPIO_A_IN 0 +#define BIT_MASK_SW_GPIO_A_IN 0xffffffffL +#define BIT_SW_GPIO_A_IN(x) \ + (((x) & BIT_MASK_SW_GPIO_A_IN) << BIT_SHIFT_SW_GPIO_A_IN) +#define BITS_SW_GPIO_A_IN (BIT_MASK_SW_GPIO_A_IN << BIT_SHIFT_SW_GPIO_A_IN) +#define BIT_CLEAR_SW_GPIO_A_IN(x) ((x) & (~BITS_SW_GPIO_A_IN)) +#define BIT_GET_SW_GPIO_A_IN(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_A_IN) & BIT_MASK_SW_GPIO_A_IN) +#define BIT_SET_SW_GPIO_A_IN(x, v) \ + (BIT_CLEAR_SW_GPIO_A_IN(x) | BIT_SW_GPIO_A_IN(v)) + +#define BIT_SHIFT_SW_GPIO_B_OEN 0 +#define BIT_MASK_SW_GPIO_B_OEN 0xff +#define BIT_SW_GPIO_B_OEN(x) \ + (((x) & BIT_MASK_SW_GPIO_B_OEN) << BIT_SHIFT_SW_GPIO_B_OEN) +#define BITS_SW_GPIO_B_OEN (BIT_MASK_SW_GPIO_B_OEN << BIT_SHIFT_SW_GPIO_B_OEN) +#define BIT_CLEAR_SW_GPIO_B_OEN(x) ((x) & (~BITS_SW_GPIO_B_OEN)) +#define BIT_GET_SW_GPIO_B_OEN(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_B_OEN) & BIT_MASK_SW_GPIO_B_OEN) +#define BIT_SET_SW_GPIO_B_OEN(x, v) \ + (BIT_CLEAR_SW_GPIO_B_OEN(x) | BIT_SW_GPIO_B_OEN(v)) + +#define BIT_SHIFT_SW_GPIO_B_OUT 0 +#define BIT_MASK_SW_GPIO_B_OUT 0xff +#define BIT_SW_GPIO_B_OUT(x) \ + (((x) & BIT_MASK_SW_GPIO_B_OUT) << BIT_SHIFT_SW_GPIO_B_OUT) +#define BITS_SW_GPIO_B_OUT (BIT_MASK_SW_GPIO_B_OUT << BIT_SHIFT_SW_GPIO_B_OUT) +#define BIT_CLEAR_SW_GPIO_B_OUT(x) ((x) & (~BITS_SW_GPIO_B_OUT)) +#define BIT_GET_SW_GPIO_B_OUT(x) \ + (((x) >> BIT_SHIFT_SW_GPIO_B_OUT) & BIT_MASK_SW_GPIO_B_OUT) +#define BIT_SET_SW_GPIO_B_OUT(x, v) \ + (BIT_CLEAR_SW_GPIO_B_OUT(x) | BIT_SW_GPIO_B_OUT(v)) + +#define BIT_SYM_FW_CTL_HCI_TXDMA_EN BIT(0) + +#define BIT_SHIFT_TDE_H2C_RD_ADDR 0 +#define BIT_MASK_TDE_H2C_RD_ADDR 0x3ffff +#define BIT_TDE_H2C_RD_ADDR(x) \ + (((x) & BIT_MASK_TDE_H2C_RD_ADDR) << BIT_SHIFT_TDE_H2C_RD_ADDR) +#define BITS_TDE_H2C_RD_ADDR \ + (BIT_MASK_TDE_H2C_RD_ADDR << BIT_SHIFT_TDE_H2C_RD_ADDR) +#define BIT_CLEAR_TDE_H2C_RD_ADDR(x) ((x) & (~BITS_TDE_H2C_RD_ADDR)) +#define BIT_GET_TDE_H2C_RD_ADDR(x) \ + (((x) >> BIT_SHIFT_TDE_H2C_RD_ADDR) & BIT_MASK_TDE_H2C_RD_ADDR) +#define BIT_SET_TDE_H2C_RD_ADDR(x, v) \ + (BIT_CLEAR_TDE_H2C_RD_ADDR(x) | BIT_TDE_H2C_RD_ADDR(v)) + +#define BIT_SHIFT_TDE_H2C_WR_ADDR 0 +#define BIT_MASK_TDE_H2C_WR_ADDR 0x3ffff +#define BIT_TDE_H2C_WR_ADDR(x) \ + (((x) & BIT_MASK_TDE_H2C_WR_ADDR) << BIT_SHIFT_TDE_H2C_WR_ADDR) +#define BITS_TDE_H2C_WR_ADDR \ + (BIT_MASK_TDE_H2C_WR_ADDR << BIT_SHIFT_TDE_H2C_WR_ADDR) +#define BIT_CLEAR_TDE_H2C_WR_ADDR(x) ((x) & (~BITS_TDE_H2C_WR_ADDR)) +#define BIT_GET_TDE_H2C_WR_ADDR(x) \ + (((x) >> BIT_SHIFT_TDE_H2C_WR_ADDR) & BIT_MASK_TDE_H2C_WR_ADDR) +#define BIT_SET_TDE_H2C_WR_ADDR(x, v) \ + (BIT_CLEAR_TDE_H2C_WR_ADDR(x) | BIT_TDE_H2C_WR_ADDR(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXFFOVFL_RSV 8 -#define BIT_MASK_RXFFOVFL_RSV 0xf -#define BIT_RXFFOVFL_RSV(x) (((x) & BIT_MASK_RXFFOVFL_RSV) << BIT_SHIFT_RXFFOVFL_RSV) -#define BIT_GET_RXFFOVFL_RSV(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV) & BIT_MASK_RXFFOVFL_RSV) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_SHIFT_EFS_HCI_SEL_V1 0 +#define BIT_MASK_EFS_HCI_SEL_V1 0x7 +#define BIT_EFS_HCI_SEL_V1(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1) +#define BITS_EFS_HCI_SEL_V1 \ + (BIT_MASK_EFS_HCI_SEL_V1 << BIT_SHIFT_EFS_HCI_SEL_V1) +#define BIT_CLEAR_EFS_HCI_SEL_V1(x) ((x) & (~BITS_EFS_HCI_SEL_V1)) +#define BIT_GET_EFS_HCI_SEL_V1(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1) +#define BIT_SET_EFS_HCI_SEL_V1(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_V1(x) | BIT_EFS_HCI_SEL_V1(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ +#define BIT_PAD_HWPDB BIT(0) -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXFFOVFL_RSV_V2 8 -#define BIT_MASK_RXFFOVFL_RSV_V2 0xf -#define BIT_RXFFOVFL_RSV_V2(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2) -#define BIT_GET_RXFFOVFL_RSV_V2(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2) +/* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ +#define BIT_HIOE_ON_TIMEOUT BIT(23) +#define BIT_SIC_ON_TIMEOUT BIT(22) +#define BIT_CPU_ON_TIMEOUT BIT(21) +#define BIT_HCI_ON_TIMEOUT BIT(20) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT) - - -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +/* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ +#define BIT_SIO_ALDN BIT(19) +#define BIT_USB_ALDN BIT(18) +#define BIT_PCI_ALDN BIT(17) +#define BIT_SYS_ALDN BIT(16) -#define BIT_SHIFT_RXFF0_BNDY_V1 8 -#define BIT_MASK_RXFF0_BNDY_V1 0x3ffff -#define BIT_RXFF0_BNDY_V1(x) (((x) & BIT_MASK_RXFF0_BNDY_V1) << BIT_SHIFT_RXFF0_BNDY_V1) -#define BIT_GET_RXFF0_BNDY_V1(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V1) & BIT_MASK_RXFF0_BNDY_V1) +#define BIT_SHIFT_EPVID1 8 +#define BIT_MASK_EPVID1 0xff +#define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1) +#define BITS_EPVID1 (BIT_MASK_EPVID1 << BIT_SHIFT_EPVID1) +#define BIT_CLEAR_EPVID1(x) ((x) & (~BITS_EPVID1)) +#define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1) +#define BIT_SET_EPVID1(x, v) (BIT_CLEAR_EPVID1(x) | BIT_EPVID1(v)) +#define BIT_SHIFT_EPVID0 0 +#define BIT_MASK_EPVID0 0xff +#define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0) +#define BITS_EPVID0 (BIT_MASK_EPVID0 << BIT_SHIFT_EPVID0) +#define BIT_CLEAR_EPVID0(x) ((x) & (~BITS_EPVID0)) +#define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0) +#define BIT_SET_EPVID0(x, v) (BIT_CLEAR_EPVID0(x) | BIT_EPVID0(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_USB2_SEL_1 BIT(31) -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TXPKTBUF_PGBNDY 0 -#define BIT_MASK_TXPKTBUF_PGBNDY 0xff -#define BIT_TXPKTBUF_PGBNDY(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY) -#define BIT_GET_TXPKTBUF_PGBNDY(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_USB2_SEL BIT(31) +#define BIT_FEN_WLMAC_OFF BIT(31) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_USB3PHY_RST BIT(30) -/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RXFF0_BNDY_V2 0 -#define BIT_MASK_RXFF0_BNDY_V2 0x3ffff -#define BIT_RXFF0_BNDY_V2(x) (((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2) -#define BIT_GET_RXFF0_BNDY_V2(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_U3PHY_RST_V1 BIT(30) -#define BIT_SHIFT_RXFF0_RDPTR_V2 0 -#define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff -#define BIT_RXFF0_RDPTR_V2(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2) -#define BIT_GET_RXFF0_RDPTR_V2(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_RXFF0_WTPTR_V2 0 -#define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff -#define BIT_RXFF0_WTPTR_V2(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2) -#define BIT_GET_RXFF0_WTPTR_V2(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_U3_TERM_DET BIT(29) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_U3_TERM_DETECT BIT(29) -/* 2 REG_FF_STATUS (Offset 0x0118) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_RXFF0_RDPTR_V1 13 -#define BIT_MASK_RXFF0_RDPTR_V1 0x3ffff -#define BIT_RXFF0_RDPTR_V1(x) (((x) & BIT_MASK_RXFF0_RDPTR_V1) << BIT_SHIFT_RXFF0_RDPTR_V1) -#define BIT_GET_RXFF0_RDPTR_V1(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V1) & BIT_MASK_RXFF0_RDPTR_V1) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_USB23_DBG_SEL BIT(24) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_HCI_SEL_EMBEDDED BIT(8) -/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_I2C_M_STATUS 8 -#define BIT_MASK_I2C_M_STATUS 0xf -#define BIT_I2C_M_STATUS(x) (((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS) -#define BIT_GET_I2C_M_STATUS(x) (((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_ISO_BB2PP BIT(7) +#define BIT_ISO_DENG2PP BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ +#define BIT_SHIFT_HW_ID 0 +#define BIT_MASK_HW_ID 0xff +#define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID) +#define BITS_HW_ID (BIT_MASK_HW_ID << BIT_SHIFT_HW_ID) +#define BIT_CLEAR_HW_ID(x) ((x) & (~BITS_HW_ID)) +#define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID) +#define BIT_SET_HW_ID(x, v) (BIT_CLEAR_HW_ID(x) | BIT_HW_ID(v)) -#define BIT_SHIFT_I2C_M_BUS_GNT 4 -#define BIT_MASK_I2C_M_BUS_GNT 0x7 -#define BIT_I2C_M_BUS_GNT(x) (((x) & BIT_MASK_I2C_M_BUS_GNT) << BIT_SHIFT_I2C_M_BUS_GNT) -#define BIT_GET_I2C_M_BUS_GNT(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT) & BIT_MASK_I2C_M_BUS_GNT) +#endif -#define BIT_I2C_GNT_FW BIT(3) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_I2C_DATA_RATE 1 -#define BIT_MASK_I2C_DATA_RATE 0x3 -#define BIT_I2C_DATA_RATE(x) (((x) & BIT_MASK_I2C_DATA_RATE) << BIT_SHIFT_I2C_DATA_RATE) -#define BIT_GET_I2C_DATA_RATE(x) (((x) >> BIT_SHIFT_I2C_DATA_RATE) & BIT_MASK_I2C_DATA_RATE) +/* 2 REG_SYS_CFG2 (Offset 0x00FC) */ -#define BIT_I2C_SW_CONTROL_UNLOCK BIT(0) +#define BIT_SHIFT_CHIPID 0 +#define BIT_MASK_CHIPID 0xff +#define BIT_CHIPID(x) (((x) & BIT_MASK_CHIPID) << BIT_SHIFT_CHIPID) +#define BITS_CHIPID (BIT_MASK_CHIPID << BIT_SHIFT_CHIPID) +#define BIT_CLEAR_CHIPID(x) ((x) & (~BITS_CHIPID)) +#define BIT_GET_CHIPID(x) (((x) >> BIT_SHIFT_CHIPID) & BIT_MASK_CHIPID) +#define BIT_SET_CHIPID(x, v) (BIT_CLEAR_CHIPID(x) | BIT_CHIPID(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT) +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_BIST_H32BIT_SEL BIT(29) -/* 2 REG_FF_STATUS (Offset 0x0118) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RXFF0_WTPTR_V1 0 -#define BIT_MASK_RXFF0_WTPTR_V1 0x3ffff -#define BIT_RXFF0_WTPTR_V1(x) (((x) & BIT_MASK_RXFF0_WTPTR_V1) << BIT_SHIFT_RXFF0_WTPTR_V1) -#define BIT_GET_RXFF0_WTPTR_V1(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V1) & BIT_MASK_RXFF0_WTPTR_V1) +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_MACIO_TIMEOUT_EN BIT(29) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_SHIFT_LBMODE 24 +#define BIT_MASK_LBMODE 0x1f +#define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE) +#define BITS_LBMODE (BIT_MASK_LBMODE << BIT_SHIFT_LBMODE) +#define BIT_CLEAR_LBMODE(x) ((x) & (~BITS_LBMODE)) +#define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE) +#define BIT_SET_LBMODE(x, v) (BIT_CLEAR_LBMODE(x) | BIT_LBMODE(v)) -/* 2 REG_RXFF_PTR (Offset 0x011C) */ +#define BIT_SHIFT_NETYPE1 18 +#define BIT_MASK_NETYPE1 0x3 +#define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1) +#define BITS_NETYPE1 (BIT_MASK_NETYPE1 << BIT_SHIFT_NETYPE1) +#define BIT_CLEAR_NETYPE1(x) ((x) & (~BITS_NETYPE1)) +#define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1) +#define BIT_SET_NETYPE1(x, v) (BIT_CLEAR_NETYPE1(x) | BIT_NETYPE1(v)) +#define BIT_SHIFT_NETYPE0 16 +#define BIT_MASK_NETYPE0 0x3 +#define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0) +#define BITS_NETYPE0 (BIT_MASK_NETYPE0 << BIT_SHIFT_NETYPE0) +#define BIT_CLEAR_NETYPE0(x) ((x) & (~BITS_NETYPE0)) +#define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0) +#define BIT_SET_NETYPE0(x, v) (BIT_CLEAR_NETYPE0(x) | BIT_NETYPE0(v)) -#define BIT_SHIFT_RXFF0_RDPTR 16 -#define BIT_MASK_RXFF0_RDPTR 0xffff -#define BIT_RXFF0_RDPTR(x) (((x) & BIT_MASK_RXFF0_RDPTR) << BIT_SHIFT_RXFF0_RDPTR) -#define BIT_GET_RXFF0_RDPTR(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR) & BIT_MASK_RXFF0_RDPTR) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_RXFF0_WTPTR 0 -#define BIT_MASK_RXFF0_WTPTR 0xffff -#define BIT_RXFF0_WTPTR(x) (((x) & BIT_MASK_RXFF0_WTPTR) << BIT_SHIFT_RXFF0_WTPTR) -#define BIT_GET_RXFF0_WTPTR(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR) & BIT_MASK_RXFF0_WTPTR) +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_STAT_FUNC_RST BIT(13) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_COUNTER_STS_EN BIT(13) -/* 2 REG_FE1IMR (Offset 0x0120) */ +#endif -#define BIT_BB_STOP_RX_INT_EN BIT(29) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_PTA_I2C_MBOX_EN BIT(12) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE1IMR (Offset 0x0120) */ +/* 2 REG_CR (Offset 0x0100) */ -#define BIT_FS_RXDMA2_DONE_INT_EN BIT(28) -#define BIT_FS_RXDONE3_INT_EN BIT(27) -#define BIT_FS_RXDONE2_INT_EN BIT(26) -#define BIT_FS_RX_BCN_P4_INT_EN BIT(25) -#define BIT_FS_RX_BCN_P3_INT_EN BIT(24) -#define BIT_FS_RX_BCN_P2_INT_EN BIT(23) -#define BIT_FS_RX_BCN_P1_INT_EN BIT(22) -#define BIT_FS_RX_BCN_P0_INT_EN BIT(21) -#define BIT_FS_RX_UMD0_INT_EN BIT(20) -#define BIT_FS_RX_UMD1_INT_EN BIT(19) -#define BIT_FS_RX_BMD0_INT_EN BIT(18) -#define BIT_FS_RX_BMD1_INT_EN BIT(17) -#define BIT_FS_RXDONE_INT_EN BIT(16) -#define BIT_FS_WWLAN_INT_EN BIT(15) -#define BIT_FS_SOUND_DONE_INT_EN BIT(14) -#define BIT_FS_LP_STBY_INT_EN BIT(13) -#define BIT_FS_TRL_MTR_INT_EN BIT(12) -#define BIT_FS_BF1_PRETO_INT_EN BIT(11) -#define BIT_FS_BF0_PRETO_INT_EN BIT(10) -#define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9) +#define BIT_I2C_MAILBOX_EN BIT(12) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_SHCUT_EN BIT(11) -/* 2 REG_FE1IMR (Offset 0x0120) */ +#endif -#define BIT_FS_LTE_COEX_EN BIT(6) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_32K_CAL_TMR_EN BIT(10) +#define BIT_MAC_SEC_EN BIT(9) +#define BIT_ENSWBCN BIT(8) +#define BIT_MACRXEN BIT(7) +#define BIT_MACTXEN BIT(6) +#define BIT_SCHEDULE_EN BIT(5) +#define BIT_PROTOCOL_EN BIT(4) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE1IMR (Offset 0x0120) */ +/* 2 REG_CR (Offset 0x0100) */ -#define BIT_FS_WLACTOFF_INT_EN BIT(5) -#define BIT_FS_WLACTON_INT_EN BIT(4) -#define BIT_FS_BTCMD_INT_EN BIT(3) +#define BIT_SHIFT_I2C_M_BUS_GNT_FW 4 +#define BIT_MASK_I2C_M_BUS_GNT_FW 0x7 +#define BIT_I2C_M_BUS_GNT_FW(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW) +#define BITS_I2C_M_BUS_GNT_FW \ + (BIT_MASK_I2C_M_BUS_GNT_FW << BIT_SHIFT_I2C_M_BUS_GNT_FW) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW(x) ((x) & (~BITS_I2C_M_BUS_GNT_FW)) +#define BIT_GET_I2C_M_BUS_GNT_FW(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW) +#define BIT_SET_I2C_M_BUS_GNT_FW(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW(x) | BIT_I2C_M_BUS_GNT_FW(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_RXDMA_EN BIT(3) -/* 2 REG_FEIMR (Offset 0x0120) */ +#endif -#define BIT_REG_MAILBOX_TO_I2C_INT BIT(2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_I2C_M_GNT_FW BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FE1IMR (Offset 0x0120) */ +/* 2 REG_CR (Offset 0x0100) */ -#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2) +#define BIT_TXDMA_EN BIT(2) +#define BIT_HCI_RXDMA_EN BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_SHIFT_I2C_M_SPEED 1 +#define BIT_MASK_I2C_M_SPEED 0x3 +#define BIT_I2C_M_SPEED(x) \ + (((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED) +#define BITS_I2C_M_SPEED (BIT_MASK_I2C_M_SPEED << BIT_SHIFT_I2C_M_SPEED) +#define BIT_CLEAR_I2C_M_SPEED(x) ((x) & (~BITS_I2C_M_SPEED)) +#define BIT_GET_I2C_M_SPEED(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED) +#define BIT_SET_I2C_M_SPEED(x, v) \ + (BIT_CLEAR_I2C_M_SPEED(x) | BIT_I2C_M_SPEED(v)) -/* 2 REG_FEIMR (Offset 0x0120) */ +#endif -#define BIT_TRPC_TO_INT_EN BIT(1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_CR (Offset 0x0100) */ +#define BIT_HCI_TXDMA_EN BIT(0) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE1IMR (Offset 0x0120) */ +/* 2 REG_CR (Offset 0x0100) */ -#define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1) +#define BIT_I2C_M_UNLOCK BIT(0) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PG_SIZE (Offset 0x0104) */ +#define BIT_SHIFT_DBG_FIFO_SEL 16 +#define BIT_MASK_DBG_FIFO_SEL 0xff +#define BIT_DBG_FIFO_SEL(x) \ + (((x) & BIT_MASK_DBG_FIFO_SEL) << BIT_SHIFT_DBG_FIFO_SEL) +#define BITS_DBG_FIFO_SEL (BIT_MASK_DBG_FIFO_SEL << BIT_SHIFT_DBG_FIFO_SEL) +#define BIT_CLEAR_DBG_FIFO_SEL(x) ((x) & (~BITS_DBG_FIFO_SEL)) +#define BIT_GET_DBG_FIFO_SEL(x) \ + (((x) >> BIT_SHIFT_DBG_FIFO_SEL) & BIT_MASK_DBG_FIFO_SEL) +#define BIT_SET_DBG_FIFO_SEL(x, v) \ + (BIT_CLEAR_DBG_FIFO_SEL(x) | BIT_DBG_FIFO_SEL(v)) -/* 2 REG_FEIMR (Offset 0x0120) */ +#endif -#define BIT_BIT_RPC_O_T_INT_EN BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */ +#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0 +#define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff +#define BIT_PKT_BUFF_ACCESS_CTRL(x) \ + (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) +#define BITS_PKT_BUFF_ACCESS_CTRL \ + (BIT_MASK_PKT_BUFF_ACCESS_CTRL << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) +#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL)) +#define BIT_GET_PKT_BUFF_ACCESS_CTRL(x) \ + (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & \ + BIT_MASK_PKT_BUFF_ACCESS_CTRL) +#define BIT_SET_PKT_BUFF_ACCESS_CTRL(x, v) \ + (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) | BIT_PKT_BUFF_ACCESS_CTRL(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE1IMR (Offset 0x0120) */ +/* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ -#define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0) +#define BIT_RXPKTBUF_DBG BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ +#define BIT_TSF_CLK_IDX BIT(15) -/* 2 REG_FE1ISR (Offset 0x0124) */ +#endif -#define BIT_BB_STOP_RX_INT BIT(29) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ + +#define BIT_TSF_CLK_STABLE BIT(15) +#define BIT_SHIFT_PKTBUF_DBG_ADDR 0 +#define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff +#define BIT_PKTBUF_DBG_ADDR(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR) +#define BITS_PKTBUF_DBG_ADDR \ + (BIT_MASK_PKTBUF_DBG_ADDR << BIT_SHIFT_PKTBUF_DBG_ADDR) +#define BIT_CLEAR_PKTBUF_DBG_ADDR(x) ((x) & (~BITS_PKTBUF_DBG_ADDR)) +#define BIT_GET_PKTBUF_DBG_ADDR(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR) +#define BIT_SET_PKTBUF_DBG_ADDR(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR(x) | BIT_PKTBUF_DBG_ADDR(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE1ISR (Offset 0x0124) */ +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ -#define BIT_FS_RXDMA2_DONE_INT BIT(28) -#define BIT_FS_RXDONE3_INT BIT(27) -#define BIT_FS_RXDONE2_INT BIT(26) -#define BIT_FS_RX_BCN_P4_INT BIT(25) -#define BIT_FS_RX_BCN_P3_INT BIT(24) -#define BIT_FS_RX_BCN_P2_INT BIT(23) -#define BIT_FS_RX_BCN_P1_INT BIT(22) -#define BIT_FS_RX_BCN_P0_INT BIT(21) -#define BIT_FS_RX_UMD0_INT BIT(20) -#define BIT_FS_RX_UMD1_INT BIT(19) -#define BIT_FS_RX_BMD0_INT BIT(18) -#define BIT_FS_RX_BMD1_INT BIT(17) -#define BIT_FS_RXDONE_INT BIT(16) -#define BIT_FS_WWLAN_INT BIT(15) -#define BIT_FS_SOUND_DONE_INT BIT(14) -#define BIT_FS_LP_STBY_INT BIT(13) -#define BIT_FS_TRL_MTR_INT BIT(12) -#define BIT_FS_BF1_PRETO_INT BIT(11) -#define BIT_FS_BF0_PRETO_INT BIT(10) -#define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9) +#define BIT_CSI_BW_EN BIT(31) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_HIQ_MAP_V1 19 +#define BIT_MASK_TXDMA_HIQ_MAP_V1 0x7 +#define BIT_TXDMA_HIQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_V1) << BIT_SHIFT_TXDMA_HIQ_MAP_V1) +#define BITS_TXDMA_HIQ_MAP_V1 \ + (BIT_MASK_TXDMA_HIQ_MAP_V1 << BIT_SHIFT_TXDMA_HIQ_MAP_V1) +#define BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_HIQ_MAP_V1)) +#define BIT_GET_TXDMA_HIQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_V1) & BIT_MASK_TXDMA_HIQ_MAP_V1) +#define BIT_SET_TXDMA_HIQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) | BIT_TXDMA_HIQ_MAP_V1(v)) -/* 2 REG_FE1ISR (Offset 0x0124) */ +#endif -#define BIT_FS_LTE_COEX_INT BIT(6) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_CMQ_MAP 16 +#define BIT_MASK_TXDMA_CMQ_MAP 0x3 +#define BIT_TXDMA_CMQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_CMQ_MAP) << BIT_SHIFT_TXDMA_CMQ_MAP) +#define BITS_TXDMA_CMQ_MAP (BIT_MASK_TXDMA_CMQ_MAP << BIT_SHIFT_TXDMA_CMQ_MAP) +#define BIT_CLEAR_TXDMA_CMQ_MAP(x) ((x) & (~BITS_TXDMA_CMQ_MAP)) +#define BIT_GET_TXDMA_CMQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_CMQ_MAP) & BIT_MASK_TXDMA_CMQ_MAP) +#define BIT_SET_TXDMA_CMQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_CMQ_MAP(x) | BIT_TXDMA_CMQ_MAP(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FE1ISR (Offset 0x0124) */ +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ -#define BIT_FS_WLACTOFF_INT BIT(5) -#define BIT_FS_WLACTON_INT BIT(4) -#define BIT_FS_BCN_RX_INT_INT BIT(3) +#define BIT_SHIFT_TXDMA_MGQ_MAP_V1 16 +#define BIT_MASK_TXDMA_MGQ_MAP_V1 0x7 +#define BIT_TXDMA_MGQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_V1) << BIT_SHIFT_TXDMA_MGQ_MAP_V1) +#define BITS_TXDMA_MGQ_MAP_V1 \ + (BIT_MASK_TXDMA_MGQ_MAP_V1 << BIT_SHIFT_TXDMA_MGQ_MAP_V1) +#define BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) ((x) & (~BITS_TXDMA_MGQ_MAP_V1)) +#define BIT_GET_TXDMA_MGQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_V1) & BIT_MASK_TXDMA_MGQ_MAP_V1) +#define BIT_SET_TXDMA_MGQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) | BIT_TXDMA_MGQ_MAP_V1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_H2C_MAP 16 +#define BIT_MASK_TXDMA_H2C_MAP 0x3 +#define BIT_TXDMA_H2C_MAP(x) \ + (((x) & BIT_MASK_TXDMA_H2C_MAP) << BIT_SHIFT_TXDMA_H2C_MAP) +#define BITS_TXDMA_H2C_MAP (BIT_MASK_TXDMA_H2C_MAP << BIT_SHIFT_TXDMA_H2C_MAP) +#define BIT_CLEAR_TXDMA_H2C_MAP(x) ((x) & (~BITS_TXDMA_H2C_MAP)) +#define BIT_GET_TXDMA_H2C_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_H2C_MAP) & BIT_MASK_TXDMA_H2C_MAP) +#define BIT_SET_TXDMA_H2C_MAP(x, v) \ + (BIT_CLEAR_TXDMA_H2C_MAP(x) | BIT_TXDMA_H2C_MAP(v)) -/* 2 REG_FEISR (Offset 0x0124) */ +#endif -#define BIT_MAILBOX_TO_I2C BIT(2) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_HIQ_MAP 14 +#define BIT_MASK_TXDMA_HIQ_MAP 0x3 +#define BIT_TXDMA_HIQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) +#define BITS_TXDMA_HIQ_MAP (BIT_MASK_TXDMA_HIQ_MAP << BIT_SHIFT_TXDMA_HIQ_MAP) +#define BIT_CLEAR_TXDMA_HIQ_MAP(x) ((x) & (~BITS_TXDMA_HIQ_MAP)) +#define BIT_GET_TXDMA_HIQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP) +#define BIT_SET_TXDMA_HIQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP(x) | BIT_TXDMA_HIQ_MAP(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FE1ISR (Offset 0x0124) */ +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ -#define BIT_FS_MAILBOX_TO_I2C_INT BIT(2) +#define BIT_SHIFT_TXDMA_BKQ_MAP_V1 13 +#define BIT_MASK_TXDMA_BKQ_MAP_V1 0x7 +#define BIT_TXDMA_BKQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_V1) << BIT_SHIFT_TXDMA_BKQ_MAP_V1) +#define BITS_TXDMA_BKQ_MAP_V1 \ + (BIT_MASK_TXDMA_BKQ_MAP_V1 << BIT_SHIFT_TXDMA_BKQ_MAP_V1) +#define BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BKQ_MAP_V1)) +#define BIT_GET_TXDMA_BKQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_V1) & BIT_MASK_TXDMA_BKQ_MAP_V1) +#define BIT_SET_TXDMA_BKQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) | BIT_TXDMA_BKQ_MAP_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ -/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_SHIFT_TXDMA_MGQ_MAP 12 +#define BIT_MASK_TXDMA_MGQ_MAP 0x3 +#define BIT_TXDMA_MGQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) +#define BITS_TXDMA_MGQ_MAP (BIT_MASK_TXDMA_MGQ_MAP << BIT_SHIFT_TXDMA_MGQ_MAP) +#define BIT_CLEAR_TXDMA_MGQ_MAP(x) ((x) & (~BITS_TXDMA_MGQ_MAP)) +#define BIT_GET_TXDMA_MGQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP) +#define BIT_SET_TXDMA_MGQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP(x) | BIT_TXDMA_MGQ_MAP(v)) -#define BIT_TRPC_TO_INT BIT(1) +#define BIT_SHIFT_TXDMA_BKQ_MAP 10 +#define BIT_MASK_TXDMA_BKQ_MAP 0x3 +#define BIT_TXDMA_BKQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) +#define BITS_TXDMA_BKQ_MAP (BIT_MASK_TXDMA_BKQ_MAP << BIT_SHIFT_TXDMA_BKQ_MAP) +#define BIT_CLEAR_TXDMA_BKQ_MAP(x) ((x) & (~BITS_TXDMA_BKQ_MAP)) +#define BIT_GET_TXDMA_BKQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP) +#define BIT_SET_TXDMA_BKQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP(x) | BIT_TXDMA_BKQ_MAP(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_BEQ_MAP_V1 10 +#define BIT_MASK_TXDMA_BEQ_MAP_V1 0x7 +#define BIT_TXDMA_BEQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_V1) << BIT_SHIFT_TXDMA_BEQ_MAP_V1) +#define BITS_TXDMA_BEQ_MAP_V1 \ + (BIT_MASK_TXDMA_BEQ_MAP_V1 << BIT_SHIFT_TXDMA_BEQ_MAP_V1) +#define BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BEQ_MAP_V1)) +#define BIT_GET_TXDMA_BEQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_V1) & BIT_MASK_TXDMA_BEQ_MAP_V1) +#define BIT_SET_TXDMA_BEQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) | BIT_TXDMA_BEQ_MAP_V1(v)) -/* 2 REG_FE1ISR (Offset 0x0124) */ +#endif -#define BIT_FS_TRPC_TO_INT BIT(1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_BEQ_MAP 8 +#define BIT_MASK_TXDMA_BEQ_MAP 0x3 +#define BIT_TXDMA_BEQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) +#define BITS_TXDMA_BEQ_MAP (BIT_MASK_TXDMA_BEQ_MAP << BIT_SHIFT_TXDMA_BEQ_MAP) +#define BIT_CLEAR_TXDMA_BEQ_MAP(x) ((x) & (~BITS_TXDMA_BEQ_MAP)) +#define BIT_GET_TXDMA_BEQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP) +#define BIT_SET_TXDMA_BEQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP(x) | BIT_TXDMA_BEQ_MAP(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FEISR (Offset 0x0124) */ +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ -#define BIT_RPC_O_T_INT BIT(0) +#define BIT_SHIFT_TXDMA_VIQ_MAP_V1 7 +#define BIT_MASK_TXDMA_VIQ_MAP_V1 0x7 +#define BIT_TXDMA_VIQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_V1) << BIT_SHIFT_TXDMA_VIQ_MAP_V1) +#define BITS_TXDMA_VIQ_MAP_V1 \ + (BIT_MASK_TXDMA_VIQ_MAP_V1 << BIT_SHIFT_TXDMA_VIQ_MAP_V1) +#define BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VIQ_MAP_V1)) +#define BIT_GET_TXDMA_VIQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_V1) & BIT_MASK_TXDMA_VIQ_MAP_V1) +#define BIT_SET_TXDMA_VIQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) | BIT_TXDMA_VIQ_MAP_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ -/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_SHIFT_TXDMA_VIQ_MAP 6 +#define BIT_MASK_TXDMA_VIQ_MAP 0x3 +#define BIT_TXDMA_VIQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) +#define BITS_TXDMA_VIQ_MAP (BIT_MASK_TXDMA_VIQ_MAP << BIT_SHIFT_TXDMA_VIQ_MAP) +#define BIT_CLEAR_TXDMA_VIQ_MAP(x) ((x) & (~BITS_TXDMA_VIQ_MAP)) +#define BIT_GET_TXDMA_VIQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP) +#define BIT_SET_TXDMA_VIQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP(x) | BIT_TXDMA_VIQ_MAP(v)) -#define BIT_FS_RPC_O_T_INT BIT(0) +#define BIT_SHIFT_TXDMA_VOQ_MAP 4 +#define BIT_MASK_TXDMA_VOQ_MAP 0x3 +#define BIT_TXDMA_VOQ_MAP(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) +#define BITS_TXDMA_VOQ_MAP (BIT_MASK_TXDMA_VOQ_MAP << BIT_SHIFT_TXDMA_VOQ_MAP) +#define BIT_CLEAR_TXDMA_VOQ_MAP(x) ((x) & (~BITS_TXDMA_VOQ_MAP)) +#define BIT_GET_TXDMA_VOQ_MAP(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP) +#define BIT_SET_TXDMA_VOQ_MAP(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP(x) | BIT_TXDMA_VOQ_MAP(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_SHIFT_TXDMA_VOQ_MAP_V1 4 +#define BIT_MASK_TXDMA_VOQ_MAP_V1 0x7 +#define BIT_TXDMA_VOQ_MAP_V1(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_V1) << BIT_SHIFT_TXDMA_VOQ_MAP_V1) +#define BITS_TXDMA_VOQ_MAP_V1 \ + (BIT_MASK_TXDMA_VOQ_MAP_V1 << BIT_SHIFT_TXDMA_VOQ_MAP_V1) +#define BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VOQ_MAP_V1)) +#define BIT_GET_TXDMA_VOQ_MAP_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_V1) & BIT_MASK_TXDMA_VOQ_MAP_V1) +#define BIT_SET_TXDMA_VOQ_MAP_V1(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) | BIT_TXDMA_VOQ_MAP_V1(v)) -/* 2 REG_CPWM (Offset 0x012C) */ +#endif -#define BIT_CPWM_TOGGLING BIT(31) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_CPWM_MOD 24 -#define BIT_MASK_CPWM_MOD 0x7f -#define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD) -#define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_TXDMA_BW_EN BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ +#define BIT_RXDMA_AGG_EN BIT(2) +#define BIT_RXSHFT_EN BIT(1) +#define BIT_RXDMA_ARBBW_EN BIT(0) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31) +#if (HALMAC_8814A_SUPPORT) -#endif +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_RXFFOVFL_RSV_V1 28 +#define BIT_MASK_RXFFOVFL_RSV_V1 0xf +#define BIT_RXFFOVFL_RSV_V1(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V1) << BIT_SHIFT_RXFFOVFL_RSV_V1) +#define BITS_RXFFOVFL_RSV_V1 \ + (BIT_MASK_RXFFOVFL_RSV_V1 << BIT_SHIFT_RXFFOVFL_RSV_V1) +#define BIT_CLEAR_RXFFOVFL_RSV_V1(x) ((x) & (~BITS_RXFFOVFL_RSV_V1)) +#define BIT_GET_RXFFOVFL_RSV_V1(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V1) & BIT_MASK_RXFFOVFL_RSV_V1) +#define BIT_SET_RXFFOVFL_RSV_V1(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V1(x) | BIT_RXFFOVFL_RSV_V1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ -#define BIT_SOUND_DONE_MSK BIT(30) +#define BIT_SHIFT_RXFF0_BNDY 16 +#define BIT_MASK_RXFF0_BNDY 0xffff +#define BIT_RXFF0_BNDY(x) (((x) & BIT_MASK_RXFF0_BNDY) << BIT_SHIFT_RXFF0_BNDY) +#define BITS_RXFF0_BNDY (BIT_MASK_RXFF0_BNDY << BIT_SHIFT_RXFF0_BNDY) +#define BIT_CLEAR_RXFF0_BNDY(x) ((x) & (~BITS_RXFF0_BNDY)) +#define BIT_GET_RXFF0_BNDY(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY) & BIT_MASK_RXFF0_BNDY) +#define BIT_SET_RXFF0_BNDY(x, v) (BIT_CLEAR_RXFF0_BNDY(x) | BIT_RXFF0_BNDY(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_FWFFOVFL_RSV 16 +#define BIT_MASK_FWFFOVFL_RSV 0xf +#define BIT_FWFFOVFL_RSV(x) \ + (((x) & BIT_MASK_FWFFOVFL_RSV) << BIT_SHIFT_FWFFOVFL_RSV) +#define BITS_FWFFOVFL_RSV (BIT_MASK_FWFFOVFL_RSV << BIT_SHIFT_FWFFOVFL_RSV) +#define BIT_CLEAR_FWFFOVFL_RSV(x) ((x) & (~BITS_FWFFOVFL_RSV)) +#define BIT_GET_FWFFOVFL_RSV(x) \ + (((x) >> BIT_SHIFT_FWFFOVFL_RSV) & BIT_MASK_FWFFOVFL_RSV) +#define BIT_SET_FWFFOVFL_RSV(x, v) \ + (BIT_CLEAR_FWFFOVFL_RSV(x) | BIT_FWFFOVFL_RSV(v)) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_RXFFOVFL_RSV 8 +#define BIT_MASK_RXFFOVFL_RSV 0xf +#define BIT_RXFFOVFL_RSV(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV) << BIT_SHIFT_RXFFOVFL_RSV) +#define BITS_RXFFOVFL_RSV (BIT_MASK_RXFFOVFL_RSV << BIT_SHIFT_RXFFOVFL_RSV) +#define BIT_CLEAR_RXFFOVFL_RSV(x) ((x) & (~BITS_RXFFOVFL_RSV)) +#define BIT_GET_RXFFOVFL_RSV(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV) & BIT_MASK_RXFFOVFL_RSV) +#define BIT_SET_RXFFOVFL_RSV(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV(x) | BIT_RXFFOVFL_RSV(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ -#define BIT_TRY_DONE_MSK BIT(29) +#define BIT_SHIFT_RXFFOVFL_RSV_V2 8 +#define BIT_MASK_RXFFOVFL_RSV_V2 0xf +#define BIT_RXFFOVFL_RSV_V2(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2) +#define BITS_RXFFOVFL_RSV_V2 \ + (BIT_MASK_RXFFOVFL_RSV_V2 << BIT_SHIFT_RXFFOVFL_RSV_V2) +#define BIT_CLEAR_RXFFOVFL_RSV_V2(x) ((x) & (~BITS_RXFFOVFL_RSV_V2)) +#define BIT_GET_RXFFOVFL_RSV_V2(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2) +#define BIT_SET_RXFFOVFL_RSV_V2(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2(x) | BIT_RXFFOVFL_RSV_V2(v)) #endif +#if (HALMAC_8814A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_RXFF0_BNDY_V1 8 +#define BIT_MASK_RXFF0_BNDY_V1 0x3ffff +#define BIT_RXFF0_BNDY_V1(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V1) << BIT_SHIFT_RXFF0_BNDY_V1) +#define BITS_RXFF0_BNDY_V1 (BIT_MASK_RXFF0_BNDY_V1 << BIT_SHIFT_RXFF0_BNDY_V1) +#define BIT_CLEAR_RXFF0_BNDY_V1(x) ((x) & (~BITS_RXFF0_BNDY_V1)) +#define BIT_GET_RXFF0_BNDY_V1(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V1) & BIT_MASK_RXFF0_BNDY_V1) +#define BIT_SET_RXFF0_BNDY_V1(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V1(x) | BIT_RXFF0_BNDY_V1(v)) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ +#define BIT_SHIFT_TXPKTBUF_PGBNDY 0 +#define BIT_MASK_TXPKTBUF_PGBNDY 0xff +#define BIT_TXPKTBUF_PGBNDY(x) \ + (((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY) +#define BITS_TXPKTBUF_PGBNDY \ + (BIT_MASK_TXPKTBUF_PGBNDY << BIT_SHIFT_TXPKTBUF_PGBNDY) +#define BIT_CLEAR_TXPKTBUF_PGBNDY(x) ((x) & (~BITS_TXPKTBUF_PGBNDY)) +#define BIT_GET_TXPKTBUF_PGBNDY(x) \ + (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY) +#define BIT_SET_TXPKTBUF_PGBNDY(x, v) \ + (BIT_CLEAR_TXPKTBUF_PGBNDY(x) | BIT_TXPKTBUF_PGBNDY(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_TRXFF_BNDY (Offset 0x0114) */ -#define BIT_TXRPT_CNT_FULL_MSK BIT(28) +#define BIT_SHIFT_RXFF0_BNDY_V2 0 +#define BIT_MASK_RXFF0_BNDY_V2 0x3ffff +#define BIT_RXFF0_BNDY_V2(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2) +#define BITS_RXFF0_BNDY_V2 (BIT_MASK_RXFF0_BNDY_V2 << BIT_SHIFT_RXFF0_BNDY_V2) +#define BIT_CLEAR_RXFF0_BNDY_V2(x) ((x) & (~BITS_RXFF0_BNDY_V2)) +#define BIT_GET_RXFF0_BNDY_V2(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2) +#define BIT_SET_RXFF0_BNDY_V2(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2(x) | BIT_RXFF0_BNDY_V2(v)) + +#define BIT_SHIFT_RXFF0_RDPTR_V2 0 +#define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff +#define BIT_RXFF0_RDPTR_V2(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2) +#define BITS_RXFF0_RDPTR_V2 \ + (BIT_MASK_RXFF0_RDPTR_V2 << BIT_SHIFT_RXFF0_RDPTR_V2) +#define BIT_CLEAR_RXFF0_RDPTR_V2(x) ((x) & (~BITS_RXFF0_RDPTR_V2)) +#define BIT_GET_RXFF0_RDPTR_V2(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2) +#define BIT_SET_RXFF0_RDPTR_V2(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2(x) | BIT_RXFF0_RDPTR_V2(v)) + +#define BIT_SHIFT_RXFF0_WTPTR_V2 0 +#define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff +#define BIT_RXFF0_WTPTR_V2(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2) +#define BITS_RXFF0_WTPTR_V2 \ + (BIT_MASK_RXFF0_WTPTR_V2 << BIT_SHIFT_RXFF0_WTPTR_V2) +#define BIT_CLEAR_RXFF0_WTPTR_V2(x) ((x) & (~BITS_RXFF0_WTPTR_V2)) +#define BIT_GET_RXFF0_WTPTR_V2(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2) +#define BIT_SET_RXFF0_WTPTR_V2(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2(x) | BIT_RXFF0_WTPTR_V2(v)) #endif +#if (HALMAC_8814A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FF_STATUS (Offset 0x0118) */ +#define BIT_SHIFT_RXFF0_RDPTR_V1 13 +#define BIT_MASK_RXFF0_RDPTR_V1 0x3ffff +#define BIT_RXFF0_RDPTR_V1(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V1) << BIT_SHIFT_RXFF0_RDPTR_V1) +#define BITS_RXFF0_RDPTR_V1 \ + (BIT_MASK_RXFF0_RDPTR_V1 << BIT_SHIFT_RXFF0_RDPTR_V1) +#define BIT_CLEAR_RXFF0_RDPTR_V1(x) ((x) & (~BITS_RXFF0_RDPTR_V1)) +#define BIT_GET_RXFF0_RDPTR_V1(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V1) & BIT_MASK_RXFF0_RDPTR_V1) +#define BIT_SET_RXFF0_RDPTR_V1(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V1(x) | BIT_RXFF0_RDPTR_V1(v)) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ +#define BIT_SHIFT_I2C_M_STATUS 8 +#define BIT_MASK_I2C_M_STATUS 0xf +#define BIT_I2C_M_STATUS(x) \ + (((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS) +#define BITS_I2C_M_STATUS (BIT_MASK_I2C_M_STATUS << BIT_SHIFT_I2C_M_STATUS) +#define BIT_CLEAR_I2C_M_STATUS(x) ((x) & (~BITS_I2C_M_STATUS)) +#define BIT_GET_I2C_M_STATUS(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS) +#define BIT_SET_I2C_M_STATUS(x, v) \ + (BIT_CLEAR_I2C_M_STATUS(x) | BIT_I2C_M_STATUS(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ -#define BIT_WLACTOFF_INT_EN BIT(27) +#define BIT_SHIFT_I2C_M_BUS_GNT 4 +#define BIT_MASK_I2C_M_BUS_GNT 0x7 +#define BIT_I2C_M_BUS_GNT(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT) << BIT_SHIFT_I2C_M_BUS_GNT) +#define BITS_I2C_M_BUS_GNT (BIT_MASK_I2C_M_BUS_GNT << BIT_SHIFT_I2C_M_BUS_GNT) +#define BIT_CLEAR_I2C_M_BUS_GNT(x) ((x) & (~BITS_I2C_M_BUS_GNT)) +#define BIT_GET_I2C_M_BUS_GNT(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT) & BIT_MASK_I2C_M_BUS_GNT) +#define BIT_SET_I2C_M_BUS_GNT(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT(x) | BIT_I2C_M_BUS_GNT(v)) -#endif +#define BIT_I2C_GNT_FW BIT(3) + +#define BIT_SHIFT_I2C_DATA_RATE 1 +#define BIT_MASK_I2C_DATA_RATE 0x3 +#define BIT_I2C_DATA_RATE(x) \ + (((x) & BIT_MASK_I2C_DATA_RATE) << BIT_SHIFT_I2C_DATA_RATE) +#define BITS_I2C_DATA_RATE (BIT_MASK_I2C_DATA_RATE << BIT_SHIFT_I2C_DATA_RATE) +#define BIT_CLEAR_I2C_DATA_RATE(x) ((x) & (~BITS_I2C_DATA_RATE)) +#define BIT_GET_I2C_DATA_RATE(x) \ + (((x) >> BIT_SHIFT_I2C_DATA_RATE) & BIT_MASK_I2C_DATA_RATE) +#define BIT_SET_I2C_DATA_RATE(x, v) \ + (BIT_CLEAR_I2C_DATA_RATE(x) | BIT_I2C_DATA_RATE(v)) +#define BIT_I2C_SW_CONTROL_UNLOCK BIT(0) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FF_STATUS (Offset 0x0118) */ -#define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27) +#define BIT_SHIFT_RXFF0_WTPTR_V1 0 +#define BIT_MASK_RXFF0_WTPTR_V1 0x3ffff +#define BIT_RXFF0_WTPTR_V1(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V1) << BIT_SHIFT_RXFF0_WTPTR_V1) +#define BITS_RXFF0_WTPTR_V1 \ + (BIT_MASK_RXFF0_WTPTR_V1 << BIT_SHIFT_RXFF0_WTPTR_V1) +#define BIT_CLEAR_RXFF0_WTPTR_V1(x) ((x) & (~BITS_RXFF0_WTPTR_V1)) +#define BIT_GET_RXFF0_WTPTR_V1(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V1) & BIT_MASK_RXFF0_WTPTR_V1) +#define BIT_SET_RXFF0_WTPTR_V1(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V1(x) | BIT_RXFF0_WTPTR_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_RXFF_PTR (Offset 0x011C) */ -/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_SHIFT_RXFF0_RDPTR 16 +#define BIT_MASK_RXFF0_RDPTR 0xffff +#define BIT_RXFF0_RDPTR(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR) << BIT_SHIFT_RXFF0_RDPTR) +#define BITS_RXFF0_RDPTR (BIT_MASK_RXFF0_RDPTR << BIT_SHIFT_RXFF0_RDPTR) +#define BIT_CLEAR_RXFF0_RDPTR(x) ((x) & (~BITS_RXFF0_RDPTR)) +#define BIT_GET_RXFF0_RDPTR(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR) & BIT_MASK_RXFF0_RDPTR) +#define BIT_SET_RXFF0_RDPTR(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR(x) | BIT_RXFF0_RDPTR(v)) -#define BIT_WLACTON_INT_EN BIT(26) +#define BIT_SHIFT_RXFF0_WTPTR 0 +#define BIT_MASK_RXFF0_WTPTR 0xffff +#define BIT_RXFF0_WTPTR(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR) << BIT_SHIFT_RXFF0_WTPTR) +#define BITS_RXFF0_WTPTR (BIT_MASK_RXFF0_WTPTR << BIT_SHIFT_RXFF0_WTPTR) +#define BIT_CLEAR_RXFF0_WTPTR(x) ((x) & (~BITS_RXFF0_WTPTR)) +#define BIT_GET_RXFF0_WTPTR(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR) & BIT_MASK_RXFF0_WTPTR) +#define BIT_SET_RXFF0_WTPTR(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR(x) | BIT_RXFF0_WTPTR(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_H2C_OK_INT_MSK BIT(31) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_SW_PLL_LEAVE_32K_INT_EN BIT(31) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_TXPKTIN_INT_EN BIT(25) +#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_EN BIT(31) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_H2C_CMD_FULL_INT_MSK BIT(30) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_FWFF_FULL_INT_EN BIT(30) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_TXBCNOK_MSK BIT(24) +#define BIT_FWFF_FULL_INT_EN BIT(30) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_PWR_INT_127_MSK_V1 BIT(29) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_BB_STOP_RX_INT_EN BIT(29) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_TXBCNERR_MSK BIT(23) +#define BIT_FS_BB_STOP_RX_INT_EN BIT(29) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_PWR_INT_126_MSK BIT(28) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RXDMA2_DONE_INT_EN BIT(28) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEIMR (Offset 0x0120) */ -#define BIT_RX_UMD0_EN BIT(22) +#define BIT_PWR_INT_125TO96_MSK BIT(27) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RXDONE3_INT_EN BIT(27) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_PWR_INT_95TO64_MSK_V1 BIT(26) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_RX_UMD1_EN BIT(21) +#define BIT_FS_RXDONE2_INT_EN BIT(26) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_PWR_INT_63TO32_MSK_V1 BIT(25) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RX_BCN_P4_INT_EN BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEIMR (Offset 0x0120) */ -#define BIT_RX_BMD0_EN BIT(20) +#define BIT_PWR_INT_31TO0_MSK_V1 BIT(24) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RX_BCN_P3_INT_EN BIT(24) +#define BIT_FS_RX_BCN_P2_INT_EN BIT(23) +#define BIT_FS_RX_BCN_P1_INT_EN BIT(22) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_BF0_TIMEOUT_INT_MSK BIT(21) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_RX_BMD1_EN BIT(19) +#define BIT_FS_RX_BCN_P0_INT_EN BIT(21) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_BF1_TIMEOUT_INT_MSK BIT(20) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RX_UMD0_INT_EN BIT(20) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEIMR (Offset 0x0120) */ -#define BIT_BCN_RX_INT_EN BIT(18) +#define BIT_EVTQ_TXDONE_INT_MSK BIT(19) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RX_UMD1_INT_EN BIT(19) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_EVTQ_START_INT_MSK BIT(18) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_TBTTINT_MSK BIT(17) +#define BIT_FS_RX_BMD0_INT_EN BIT(18) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_TXBCN2_OK_INT_MSK BIT(17) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RX_BMD1_INT_EN BIT(17) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEIMR (Offset 0x0120) */ -#define BIT_BCNERLY_MSK BIT(16) +#define BIT_TXBCN2_ERR_INT_MSK BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RXDONE_INT_EN BIT(16) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_DWWIN_END_INT_MSK BIT(15) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_BCNDMA7_MSK BIT(15) +#define BIT_FS_WWLAN_INT_EN BIT(15) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_BCN2_EARLY_INT_MSK BIT(14) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN BIT(15) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_SOUND_DONE_INT_EN BIT(14) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEIMR (Offset 0x0120) */ -#define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15) +#define BIT_TBTT1_INT_MSK BIT(13) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_LP_STBY_INT_EN BIT(13) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_BCNDMA6_MSK BIT(14) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_PSTIMERB_INT_MSK BIT(12) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_SIFS_OVERSPEC_INT_EN BIT(14) +#define BIT_FS_TRL_MTR_INT_EN BIT(12) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_PSTIMERA_INT_MSK BIT(11) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_BCNDMA5_MSK BIT(13) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_BF1_PRETO_INT_EN BIT(11) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEIMR (Offset 0x0120) */ -#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13) +#define BIT_P2P_RFOFF_EARLY_INT_MSK BIT(10) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_BF0_PRETO_INT_EN BIT(10) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_BCNDMA4_MSK BIT(12) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_MACID_RELEASE_INT_MSK BIT(9) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_FS_MGNTQFF_TO_INT_EN BIT(12) +#define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_NANRPT_DONE_INT_MSK BIT(8) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_BCNDMA3_MSK BIT(11) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_PRETXERR_HANDLE_FSIMR BIT(8) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN BIT(11) +#define BIT_FS_PRETX_ERRHLD_INT_EN BIT(8) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_PRETX_ERRHLD_INT_EN BIT(8) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_DDMA1_LP_INT_EN BIT(11) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_FTM_PTT_INT_MSK_V1 BIT(7) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_BCNDMA2_MSK BIT(10) +#define BIT_FS_GTRD_INT_EN BIT(7) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_RXFTMREQ_OK_INT_MSK BIT(6) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_DDMA1_HP_INT_EN BIT(10) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_LTE_COEX_EN BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEIMR (Offset 0x0120) */ -#define BIT_BCNDMA1_MSK BIT(9) +#define BIT_RXFTM_INT_MSK_V1 BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_WLACTOFF_INT_EN BIT(5) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_DDMA0_LP_INT_EN BIT(9) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_TXFTM_INT_MSK_V1 BIT(4) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1IMR (Offset 0x0120) */ -#define BIT_BCNDMA0_MSK BIT(8) +#define BIT_FS_WLACTON_INT_EN BIT(4) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_LTECOEX_INT_MSK BIT(3) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_DDMA0_HP_INT_EN BIT(8) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_BTCMD_INT_EN BIT(3) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEIMR (Offset 0x0120) */ -#define BIT_LP_STBY_MSK BIT(7) +#define BIT_REG_MAILBOX_TO_I2C_INT BIT(2) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_MAILBOX_INT_MSK BIT(2) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TRXRPT_INT_EN BIT(7) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEIMR (Offset 0x0120) */ -#define BIT_CTWENDINT_MSK BIT(6) +#define BIT_TRPC_TO_INT_EN BIT(1) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_FLC_DRUTO_INT_MSK BIT(1) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_C2H_W_READY_INT_EN BIT(6) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEIMR (Offset 0x0120) */ -#define BIT_HRCV_MSK BIT(5) +#define BIT_BIT_RPC_O_T_INT_EN BIT(0) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEIMR (Offset 0x0120) */ +#define BIT_FLC_PKTTH_INT_MSK BIT(0) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_HRCV_INT_EN BIT(5) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1IMR (Offset 0x0120) */ +#define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_H2CCMD_MSK BIT(4) +#define BIT_H2C_OK_INT BIT(31) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_SW_PLL_LEAVE_32K_INT BIT(31) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_H2CCMD_INT_EN BIT(4) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT BIT(31) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_RXDONE_MSK BIT(3) +#define BIT_H2C_CMD_FULL_INT BIT(30) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_FS_FWFF_FULL_INT BIT(30) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXPKTIN_INT_EN BIT(3) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FWFF_FULL_INT BIT(30) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_ERRORHDL_MSK BIT(2) +#define BIT_PWR_INT_127_V2 BIT(29) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_BB_STOP_RX_INT BIT(29) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_ERRORHDL_INT_EN BIT(2) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_BB_STOP_RX_INT BIT(29) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_TXCCX_MSK_FW BIT(1) +#define BIT_PWR_INT_126 BIT(28) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_RXDMA2_DONE_INT BIT(28) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXCCX_INT_EN BIT(1) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_PWR_INT_125TO96 BIT(27) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_FWIMR (Offset 0x0130) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_TXCLOSE_MSK BIT(0) +#define BIT_FS_RXDONE3_INT BIT(27) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_RXDONE3_INT_INT BIT(27) -/* 2 REG_FWIMR (Offset 0x0130) */ +#endif -#define BIT_FS_TXCLOSE_INT_EN BIT(0) +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_FS_TXBCNOK_MB7_INT BIT(31) +#define BIT_PWR_INT_95TO64_V1 BIT(26) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_SOUND_DONE_INT BIT(30) +#define BIT_FS_RXDONE2_INT BIT(26) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_PWR_INT_63TO32_V1 BIT(25) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNOK_MB6_INT BIT(30) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_RX_BCN_P4_INT BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_TRY_DONE_INT BIT(29) +#define BIT_PWR_INT_31TO0_V1 BIT(24) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_RX_BCN_P3_INT BIT(24) +#define BIT_FS_RX_BCN_P2_INT BIT(23) +#define BIT_FS_RX_BCN_P1_INT BIT(22) +#define BIT_FS_RX_BCN_P0_INT BIT(21) +#define BIT_FS_RX_UMD0_INT BIT(20) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNOK_MB5_INT BIT(29) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_EVTQ_TXDONE_INT BIT(19) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_TXRPT_CNT_FULL_INT BIT(28) +#define BIT_FS_RX_UMD1_INT BIT(19) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_EVTQ_START_INT BIT(18) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNOK_MB4_INT BIT(28) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_RX_BMD0_INT BIT(18) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_WLACTOFF_INT BIT(27) +#define BIT_TXBCN2_OK_INT BIT(17) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_RX_BMD1_INT BIT(17) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNOK_MB3_INT BIT(27) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_TXBCN2_ERR_INT BIT(16) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_WLACTON_INT BIT(26) +#define BIT_FS_RXDONE_INT BIT(16) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_DWWIN_END_INT BIT(15) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNOK_MB2_INT BIT(26) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_WWLAN_INT BIT(15) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_TXPKTIN_INT BIT(25) +#define BIT_BCN2_EARLY_INT BIT(14) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_SOUND_DONE_INT BIT(14) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNOK_MB1_INT BIT(25) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_TBTT1_INT BIT(13) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_TXBCNOK_INT BIT(24) +#define BIT_FS_LP_STBY_INT BIT(13) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_PSTIMERB_INT BIT(12) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNOK_MB0_INT BIT(24) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_TRL_MTR_INT BIT(12) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_TXBCNERR_INT BIT(23) +#define BIT_PSTIMERA_INT BIT(11) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_BF1_PRETO_INT BIT(11) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNERR_MB7_INT BIT(23) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_P2P_RFOFF_EARLY_INT BIT(10) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_RX_UMD0_INT BIT(22) +#define BIT_FS_BF0_PRETO_INT BIT(10) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_MACID_RELEASE_INT BIT(9) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNERR_MB6_INT BIT(22) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_RX_UMD1_INT BIT(21) +#define BIT_NANRPT_DONE_INT BIT(8) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_PRETXERR_HANDLE_FSISR BIT(8) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNERR_MB5_INT BIT(21) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_PRETX_ERRHLD_INT BIT(8) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_RX_BMD0_INT BIT(20) +#define BIT_PRETX_ERRHLD_INT BIT(8) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_FTM_PTT_INT_V1 BIT(7) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNERR_MB4_INT BIT(20) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_SND_RDY_INT BIT(7) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_RX_BMD1_INT BIT(19) +#define BIT_RXFTMREQ_OK_INT BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_LTE_COEX_INT BIT(6) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXBCNERR_MB3_INT BIT(19) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_RXFTM_INT_V1 BIT(5) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_BCN_RX_INT_INT BIT(18) +#define BIT_FS_WLACTOFF_INT BIT(5) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_FEISR (Offset 0x0124) */ + +#define BIT_TXFTM_INT_V1 BIT(4) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_FS_TXBCNERR_MB2_INT BIT(18) +#define BIT_FS_WLACTON_INT BIT(4) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_LTECOEX_INT BIT(3) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_TBTTINT_INT BIT(17) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_BCN_RX_INT_INT BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_FS_TXBCNERR_MB1_INT BIT(17) +#define BIT_BT_CMD_INT BIT(3) #endif +#if (HALMAC_8192E_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_MAILBOX_TO_I2C BIT(2) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_BCNERLY_INT BIT(16) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_MAILBOX_INT BIT(2) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FE1ISR (Offset 0x0124) */ -#define BIT_FS_TXBCNERR_MB0_INT BIT(16) +#define BIT_FS_MAILBOX_TO_I2C_INT BIT(2) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ -/* 2 REG_FWISR (Offset 0x0134) */ - -#define BIT_BCNDMA7_INT BIT(15) +#define BIT_TRPC_TO_INT BIT(1) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_FLC_DRUTO_INT BIT(1) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_CPUMGN_POLLED_PKT_DONE_INT BIT(15) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_TRPC_TO_INT BIT(1) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FEISR (Offset 0x0124) */ -#define BIT_CPU_MGQ_TXDONE_INT BIT(15) +#define BIT_RPC_O_T_INT BIT(0) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FEISR (Offset 0x0124) */ +#define BIT_FLC_PKTTH_INT BIT(0) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_BCNDMA6_INT BIT(14) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FE1ISR (Offset 0x0124) */ +#define BIT_FS_RPC_O_T_INT BIT(0) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_CPWM (Offset 0x012C) */ + +#define BIT_CPWM_TOGGLING BIT(31) -#define BIT_SIFS_OVERSPEC_INT BIT(14) +#define BIT_SHIFT_CPWM_MOD 24 +#define BIT_MASK_CPWM_MOD 0x7f +#define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD) +#define BITS_CPWM_MOD (BIT_MASK_CPWM_MOD << BIT_SHIFT_CPWM_MOD) +#define BIT_CLEAR_CPWM_MOD(x) ((x) & (~BITS_CPWM_MOD)) +#define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD) +#define BIT_SET_CPWM_MOD(x, v) (BIT_CLEAR_CPWM_MOD(x) | BIT_CPWM_MOD(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_PCIE_BCNDMAERR_INT_MSK BIT(31) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_BCNDMA5_INT BIT(13) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13) +#define BIT_SOUND_DONE_MSK BIT(30) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_SOUND_DONE_INT_MSK BIT(30) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_BCNDMA4_INT BIT(12) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_MGNTQFF_TO_INT BIT(12) +#define BIT_TRY_DONE_MSK BIT(29) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_TRY_DONE_INT_MSK BIT(29) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_BCNDMA3_INT BIT(11) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT BIT(11) +#define BIT_TXRPT_CNT_FULL_MSK BIT(28) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_TXRPT_CNT_FULL_INT_MSK BIT(28) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_DDMA1_LP_INT BIT(11) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMA2_INT BIT(10) +#define BIT_WLACTOFF_INT_EN BIT(27) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_WLACTOFF_INT_MSK BIT(27) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_DDMA1_HP_INT BIT(10) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMA1_INT BIT(9) +#define BIT_WLACTON_INT_EN BIT(26) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_WLACTON_INT_MSK BIT(26) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_DDMA0_LP_INT BIT(9) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMA0_INT BIT(8) +#define BIT_TXPKTIN_INT_EN BIT(25) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_FWIMR (Offset 0x0130) */ + +#define BIT_TXPKTIN_INT_MSK BIT(25) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_DDMA0_HP_INT BIT(8) +#define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ -/* 2 REG_FWISR (Offset 0x0134) */ - -#define BIT_LP_STBY_INT BIT(7) +#define BIT_TXBCNOK_MSK BIT(24) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_TXBCNOK_INT_MSK BIT(24) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TRXRPT_INT BIT(7) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_CTWENDINT_INT BIT(6) +#define BIT_TXBCNERR_MSK BIT(23) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_TXBCNERR_INT_MSK BIT(23) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_C2H_W_READY_INT BIT(6) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_HRCV_INT BIT(5) +#define BIT_RX_UMD0_EN BIT(22) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_RX_UMD0_INT_MSK BIT(22) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_HRCV_INT BIT(5) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_H2CCMD_INT BIT(4) +#define BIT_RX_UMD1_EN BIT(21) #endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_FWIMR (Offset 0x0130) */ + +#define BIT_RX_UMD1_INT_MSK BIT(21) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FS_H2CCMD_INT BIT(4) +#define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ -/* 2 REG_FWISR (Offset 0x0134) */ - -#define BIT_RXDONE_INT BIT(3) +#define BIT_RX_BMD0_EN BIT(20) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_RX_BMD0_INT_MSK BIT(20) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXPKTIN_INT BIT(3) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_ERRORHDL_INT BIT(2) +#define BIT_RX_BMD1_EN BIT(19) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_RX_BMD1_INT_MSK BIT(19) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_ERRORHDL_INT BIT(2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_TXCCX_INT BIT(1) +#define BIT_BCN_RX_INT_EN BIT(18) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_BCN_RX_INT_INT_MSK BIT(18) -/* 2 REG_FWISR (Offset 0x0134) */ +#endif -#define BIT_FS_TXCCX_INT BIT(1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWISR (Offset 0x0134) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_TXCLOSE_INT BIT(0) +#define BIT_TBTTINT_MSK BIT(17) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ - -/* 2 REG_FWISR (Offset 0x0134) */ - -#define BIT_FS_TXCLOSE_INT BIT(0) +#define BIT_TBTTINT_INT_MSK BIT(17) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_GTINT6_MSK BIT(31) -#define BIT_TX_NULL1_INT_MSK BIT(30) -#define BIT_TX_NULL0_INT_MSK BIT(29) -#define BIT_MTI_BCNIVLEAR_INT_MSK BIT(28) -#define BIT_ATIMINT_MSK BIT(27) -#define BIT_WWLAN_INT_EN BIT(26) -#define BIT_C2H_W_READY_EN BIT(25) -#define BIT_TRL_MTR_EN BIT(24) -#define BIT_CLR_PS_STATUS_MSK BIT(23) +#define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23) +#define BIT_BCNERLY_MSK BIT(16) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_BCNERLY_INT_MSK BIT(16) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_RETRIEVE_BUFFERED_MSK BIT(22) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22) +#define BIT_BCNDMA7_MSK BIT(15) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_BCNDMA7_INT_MSK BIT(15) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_RPWMINT2_MSK BIT(21) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN BIT(15) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21) +#define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ -/* 2 REG_FTIMR (Offset 0x0138) */ - -#define BIT_TSF_BIT32_TOGGLE_MSK_V1 BIT(20) +#define BIT_BCNDMA6_MSK BIT(14) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20) +#define BIT_BCNDMA6_INT_MSK BIT(14) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_SIFS_OVERSPEC_INT_EN BIT(14) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_TRIGGER_PKT_MSK BIT(19) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_BCNDMA5_MSK BIT(13) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_PS_TIMER_C_INT_EN BIT(19) +#define BIT_BCNDMA5_INT_MSK BIT(13) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FW_BTCMD_INTMSK BIT(18) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_BCNDMA4_MSK BIT(12) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_PS_TIMER_B_INT_EN BIT(18) +#define BIT_BCNDMA4_INT_MSK BIT(12) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_MGNTQFF_TO_INT_EN BIT(12) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_P2P_RFOFF_INTMSK BIT(17) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_BCNDMA3_MSK BIT(11) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_PS_TIMER_A_INT_EN BIT(17) +#define BIT_BCNDMA3_INT_MSK BIT(11) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN BIT(11) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_P2P_RFON_INTMSK BIT(16) +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_CPUMGQ_ERR_INT_EN BIT(11) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16) +#define BIT_FS_DDMA1_LP_INT_EN BIT(11) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ -/* 2 REG_FTIMR (Offset 0x0138) */ - -#define BIT_TXBCN1ERR_MSK BIT(15) +#define BIT_BCNDMA2_MSK BIT(10) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_BCNDMA2_INT_MSK BIT(10) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_PS_TIMEOUT2_EN BIT(15) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_DDMA1_HP_INT_EN BIT(10) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_TXBCN1OK_MSK BIT(14) +#define BIT_BCNDMA1_MSK BIT(9) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_BCNDMA1_INT_MSK BIT(9) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_PS_TIMEOUT1_EN BIT(14) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_DDMA0_LP_INT_EN BIT(9) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FT_ATIMEND_EMSK BIT(13) +#define BIT_BCNDMA0_MSK BIT(8) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_BCNDMA0_INT_MSK BIT(8) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_PS_TIMEOUT0_EN BIT(13) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_DDMA0_HP_INT_EN BIT(8) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_BCNDMAINT_EMSK BIT(12) -#define BIT_GTINT5_MSK BIT(11) -#define BIT_EOSP_INT_MSK BIT(10) -#define BIT_RX_BCN_E_MSK BIT(9) -#define BIT_RPWM_INT_EN BIT(8) +#define BIT_LP_STBY_MSK BIT(7) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_LP_STBY_INT_MSK BIT(7) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_GTINT8_EN BIT(8) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TRXRPT_INT_EN BIT(7) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_PSTIMER_MSK BIT(7) +#define BIT_CTWENDINT_MSK BIT(6) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_CTWENDINT_INT_MSK BIT(6) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_GTINT7_EN BIT(7) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_C2H_W_READY_INT_EN BIT(6) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_TIMEOUT1_MSK BIT(6) +#define BIT_HRCV_MSK BIT(5) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_HRCV_INT_MSK BIT(5) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_GTINT6_EN BIT(6) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_HRCV_INT_EN BIT(5) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_TIMEOUT0_MSK BIT(5) +#define BIT_H2CCMD_MSK BIT(4) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_H2CCMD_INT_MSK BIT(4) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_GTINT5_EN BIT(5) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_H2CCMD_INT_EN BIT(4) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FT_GTINT4_MSK BIT(4) +#define BIT_RXDONE_MSK BIT(3) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_RXDONE_INT_MSK BIT(3) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_GTINT4_EN BIT(4) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXPKTIN_INT_EN BIT(3) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_FT_GTINT3_MSK BIT(3) +#define BIT_ERRORHDL_MSK BIT(2) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_ERRORHDL_INT_MSK BIT(2) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_GTINT3_EN BIT(3) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_ERRORHDL_INT_EN BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_GTINT2_MSK BIT(2) +#define BIT_TXCCX_MSK_FW BIT(1) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_TXCCX_INT_MSK BIT(1) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_GTINT2_EN BIT(2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXCCX_INT_EN BIT(1) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWIMR (Offset 0x0130) */ -#define BIT_GTINT1_MSK BIT(1) +#define BIT_TXCLOSE_MSK BIT(0) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_TXCLOSE_INT_MSK BIT(0) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_GTINT1_EN BIT(1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWIMR (Offset 0x0130) */ +#define BIT_FS_TXCLOSE_INT_EN BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FTIMR (Offset 0x0138) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_GTINT0_MSK BIT(0) +#define BIT_PCIE_BCNDMAERR_INT BIT(31) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXBCNOK_MB7_INT BIT(31) -/* 2 REG_FTIMR (Offset 0x0138) */ +#endif -#define BIT_FS_GTINT0_EN BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_SOUND_DONE_INT BIT(30) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_GT6INT BIT(31) -#define BIT_TX_NULL1_INT BIT(30) -#define BIT_TX_NULL0_INT BIT(29) -#define BIT_MTI_BCNIVLEAR_INT BIT(28) -#define BIT_ATIM_INT BIT(27) -#define BIT_WWLAN_INT BIT(26) -#define BIT_C2H_W_READY BIT(25) -#define BIT_TRL_MTR_INT BIT(24) -#define BIT_CLR_PS_STATUS BIT(23) +#define BIT_FS_TXBCNOK_MB6_INT BIT(30) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_TRY_DONE_INT BIT(29) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_PS_TIMER_C_EARLY__INT BIT(23) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXBCNOK_MB5_INT BIT(29) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_RETRIEVE_BUFFERED_INT BIT(22) +#define BIT_TXRPT_CNT_FULL_INT BIT(28) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXBCNOK_MB4_INT BIT(28) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_PS_TIMER_B_EARLY__INT BIT(22) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_WLACTOFF_INT BIT(27) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_RPWM2INT BIT(21) +#define BIT_FS_TXBCNOK_MB3_INT BIT(27) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_WLACTON_INT BIT(26) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_PS_TIMER_A_EARLY__INT BIT(21) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXBCNOK_MB2_INT BIT(26) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_TSF_BIT32_TOGGLE_INT_V1 BIT(20) +#define BIT_TXPKTIN_INT BIT(25) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXBCNOK_MB1_INT BIT(25) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_TXBCNOK_INT BIT(24) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_TRIGGER_PKT BIT(19) +#define BIT_FS_TXBCNOK_MB0_INT BIT(24) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_TXBCNERR_INT BIT(23) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_PS_TIMER_C_INT BIT(19) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXBCNERR_MB7_INT BIT(23) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FW_BTCMD_INT BIT(18) +#define BIT_RX_UMD0_INT BIT(22) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXBCNERR_MB6_INT BIT(22) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_PS_TIMER_B_INT BIT(18) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_RX_UMD1_INT BIT(21) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_P2P_RFOFF_INT BIT(17) +#define BIT_FS_TXBCNERR_MB5_INT BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_PS_TIMER_A_INT BIT(17) +#define BIT_RX_BMD0_INT BIT(20) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXBCNERR_MB4_INT BIT(20) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_P2P_RFON_INT BIT(16) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_RX_BMD1_INT BIT(19) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_CPUMGQ_TX_TIMER_INT BIT(16) +#define BIT_FS_TXBCNERR_MB3_INT BIT(19) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_BCN_RX_INT_INT BIT(18) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_TX_BCN1ERR_INT BIT(15) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXBCNERR_MB2_INT BIT(18) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_PS_TIMEOUT2_INT BIT(15) +#define BIT_TBTTINT_INT BIT(17) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXBCNERR_MB1_INT BIT(17) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_TX_BCN1OK_INT BIT(14) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_BCNERLY_INT BIT(16) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_PS_TIMEOUT1_INT BIT(14) +#define BIT_FS_TXBCNERR_MB0_INT BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_BCNDMA7_INT BIT(15) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_FT_ATIMEND_E BIT(13) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_CPUMGN_POLLED_PKT_DONE_INT BIT(15) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_PS_TIMEOUT0_INT BIT(13) +#define BIT_CPU_MGQ_TXDONE_INT BIT(15) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_BCNDMA6_INT BIT(14) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_BCNDMAINT_E_V1 BIT(12) -#define BIT_GT5INT BIT(11) -#define BIT_EOSP_INT BIT(10) -#define BIT_RX_BCN_E_INT BIT(9) -#define BIT_RPWMINT BIT(8) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_SIFS_OVERSPEC_INT BIT(14) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_GTINT8_INT BIT(8) +#define BIT_BCNDMA5_INT BIT(13) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_PSTIMER_INT BIT(7) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_BCNDMA4_INT BIT(12) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_GTINT7_INT BIT(7) +#define BIT_FS_MGNTQFF_TO_INT BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_BCNDMA3_INT BIT(11) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_TIMEOUT1_INT BIT(6) +#if (HALMAC_8197F_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT BIT(11) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_GTINT6_INT BIT(6) +#define BIT_FS_CPUMGQ_ERR_INT BIT(11) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_DDMA1_LP_INT BIT(11) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_TIMEOUT0_INT BIT(5) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_BCNDMA2_INT BIT(10) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_GTINT5_INT BIT(5) +#define BIT_FS_DDMA1_HP_INT BIT(10) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FWCMD_PKTIN_INT BIT(10) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_FT_GT4INT BIT(4) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_BCNDMA1_INT BIT(9) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_GTINT4_INT BIT(4) +#define BIT_FS_DDMA0_LP_INT BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_BCNDMA0_INT BIT(8) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_FT_GT3INT BIT(3) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_DDMA0_HP_INT BIT(8) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_GTINT3_INT BIT(3) +#define BIT_LP_STBY_INT BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TRXRPT_INT BIT(7) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_GT2INT BIT(2) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_CTWENDINT_INT BIT(6) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_GTINT2_INT BIT(2) +#define BIT_FS_C2H_W_READY_INT BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_HRCV_INT BIT(5) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_GT1INT BIT(1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_HRCV_INT BIT(5) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_GTINT1_INT BIT(1) +#define BIT_H2CCMD_INT BIT(4) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_H2CCMD_INT BIT(4) -/* 2 REG_FTISR (Offset 0x013C) */ +#endif -#define BIT_GT0INT BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_RXDONE_INT BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FTISR (Offset 0x013C) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_FS_GTINT0_INT BIT(0) +#define BIT_FS_TXPKTIN_INT BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_ERRORHDL_INT BIT(2) -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PKTBUF_WRITE_EN 24 -#define BIT_MASK_PKTBUF_WRITE_EN 0xff -#define BIT_PKTBUF_WRITE_EN(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN) -#define BIT_GET_PKTBUF_WRITE_EN(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_ERRORHDL_INT BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_TXCCX_INT BIT(1) -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#endif -#define BIT_TXPKT_BUF_READ_EN BIT(23) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXCCX_INT BIT(1) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +/* 2 REG_FWISR (Offset 0x0134) */ -#define BIT_TXRPTBUF_DBG BIT(23) +#define BIT_TXCLOSE_INT BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWISR (Offset 0x0134) */ +#define BIT_FS_TXCLOSE_INT BIT(0) -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#endif -#define BIT_TXRPT_BUF_READ_EN BIT(20) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_GTINT6_MSK BIT(31) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +/* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_TXPKTBUF_DBG_V2 BIT(20) +#define BIT_GT6INT_MSK BIT(31) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TX_NULL1_INT_MSK BIT(30) +#define BIT_TX_NULL0_INT_MSK BIT(29) +#define BIT_MTI_BCNIVLEAR_INT_MSK BIT(28) -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#endif -#define BIT_RXPKT_BUF_READ_EN BIT(16) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_ATIMINT_MSK BIT(27) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +/* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_RXPKTBUF_DBG BIT(16) +#define BIT_ATIM_INT_MSK BIT(27) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_WWLAN_INT_EN BIT(26) + +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_PKTBUF_ADDR 0 -#define BIT_MASK_PKTBUF_ADDR 0x1fff -#define BIT_PKTBUF_ADDR(x) (((x) & BIT_MASK_PKTBUF_ADDR) << BIT_SHIFT_PKTBUF_ADDR) -#define BIT_GET_PKTBUF_ADDR(x) (((x) >> BIT_SHIFT_PKTBUF_ADDR) & BIT_MASK_PKTBUF_ADDR) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_WWLAN_INT_MSK BIT(26) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_C2H_W_READY_EN BIT(25) -/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_PKTBUF_DBG_ADDR 0 -#define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff -#define BIT_PKTBUF_DBG_ADDR(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR) -#define BIT_GET_PKTBUF_DBG_ADDR(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_C2H_W_READY_MSK BIT(25) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_PKTBUF_DBG_DATA_L (Offset 0x0144) */ +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TRL_MTR_EN BIT(24) -#define BIT_SHIFT_PKTBUF_DBG_DATA_L 0 -#define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_L(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L) -#define BIT_GET_PKTBUF_DBG_DATA_L(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_PKTBUF_DBG_DATA_H (Offset 0x0148) */ +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TRL_MTR_INT_MSK BIT(24) -#define BIT_SHIFT_PKTBUF_DBG_DATA_H 0 -#define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_H(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H) -#define BIT_GET_PKTBUF_DBG_DATA_H(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_CPWM2 (Offset 0x014C) */ +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_CLR_PS_STATUS_MSK BIT(23) -#define BIT_SHIFT_L0S_TO_RCVY_NUM 16 -#define BIT_MASK_L0S_TO_RCVY_NUM 0xff -#define BIT_L0S_TO_RCVY_NUM(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM) -#define BIT_GET_L0S_TO_RCVY_NUM(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM) +#endif -#define BIT_CPWM2_TOGGLING BIT(15) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_CPWM2_MOD 0 -#define BIT_MASK_CPWM2_MOD 0x7fff -#define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD) -#define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23) -/* 2 REG_TC0_CTRL (Offset 0x0150) */ +#endif -#define BIT_TC0INT_EN BIT(26) -#define BIT_TC0MODE BIT(25) -#define BIT_TC0EN BIT(24) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TC0DATA 0 -#define BIT_MASK_TC0DATA 0xffffff -#define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA) -#define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_RETRIEVE_BUFFERED_MSK BIT(22) -/* 2 REG_TC1_CTRL (Offset 0x0154) */ +#endif -#define BIT_TC1INT_EN BIT(26) -#define BIT_TC1MODE BIT(25) -#define BIT_TC1EN BIT(24) +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_TC1DATA 0 -#define BIT_MASK_TC1DATA 0xffffff -#define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA) -#define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_RETRIEVE_BUFFERED_INT_MSK BIT(22) -/* 2 REG_TC2_CTRL (Offset 0x0158) */ +#endif -#define BIT_TC2INT_EN BIT(26) -#define BIT_TC2MODE BIT(25) -#define BIT_TC2EN BIT(24) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TC2DATA 0 -#define BIT_MASK_TC2DATA 0xffffff -#define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA) -#define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22) -/* 2 REG_TC3_CTRL (Offset 0x015C) */ +#endif -#define BIT_TC3INT_EN BIT(26) -#define BIT_TC3MODE BIT(25) -#define BIT_TC3EN BIT(24) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TC3DATA 0 -#define BIT_MASK_TC3DATA 0xffffff -#define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA) -#define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_RPWMINT2_MSK BIT(21) -/* 2 REG_TC4_CTRL (Offset 0x0160) */ +#endif -#define BIT_TC4INT_EN BIT(26) -#define BIT_TC4MODE BIT(25) -#define BIT_TC4EN BIT(24) +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_TC4DATA 0 -#define BIT_MASK_TC4DATA 0xffffff -#define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA) -#define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_RPWM2INT_MSK BIT(21) -/* 2 REG_TCUNIT_BASE (Offset 0x0164) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TCUNIT_BASE 0 -#define BIT_MASK_TCUNIT_BASE 0x3fff -#define BIT_TCUNIT_BASE(x) (((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE) -#define BIT_GET_TCUNIT_BASE(x) (((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ -/* 2 REG_TC5_CTRL (Offset 0x0168) */ - -#define BIT_TC50INT_EN BIT(26) +#define BIT_TSF_BIT32_TOGGLE_MSK_V1 BIT(20) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_TC5_CTRL (Offset 0x0168) */ +/* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_TC5INT_EN BIT(26) +#define BIT_TSF_BIT32_TOGGLE_INT_MSK BIT(20) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20) -/* 2 REG_TC5_CTRL (Offset 0x0168) */ +#endif -#define BIT_TC5MODE BIT(25) -#define BIT_TC5EN BIT(24) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TC5DATA 0 -#define BIT_MASK_TC5DATA 0xffffff -#define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA) -#define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TRIGGER_PKT_MSK BIT(19) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_PS_TIMER_C_INT_EN BIT(19) -/* 2 REG_TC6_CTRL (Offset 0x016C) */ +#endif -#define BIT_TC60INT_EN BIT(26) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FW_BTCMD_INTMSK BIT(18) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_TC6_CTRL (Offset 0x016C) */ +/* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_TC6INT_EN BIT(26) +#define BIT_FW_BTCMD_INT_MSK BIT(18) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_PS_TIMER_B_INT_EN BIT(18) -/* 2 REG_TC6_CTRL (Offset 0x016C) */ +#endif -#define BIT_TC6MODE BIT(25) -#define BIT_TC6EN BIT(24) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TC6DATA 0 -#define BIT_MASK_TC6DATA 0xffffff -#define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA) -#define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_P2P_RFOFF_INTMSK BIT(17) -/* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_8051_MBIST_FAIL 26 -#define BIT_MASK_8051_MBIST_FAIL 0x7 -#define BIT_8051_MBIST_FAIL(x) (((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL) -#define BIT_GET_8051_MBIST_FAIL(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_P2P_RFOFF_INT_MSK BIT(17) -#define BIT_SHIFT_USB_MBIST_FAIL 24 -#define BIT_MASK_USB_MBIST_FAIL 0x3 -#define BIT_USB_MBIST_FAIL(x) (((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL) -#define BIT_GET_USB_MBIST_FAIL(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PCIE_MBIST_FAIL 16 -#define BIT_MASK_PCIE_MBIST_FAIL 0x3f -#define BIT_PCIE_MBIST_FAIL(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL) -#define BIT_GET_PCIE_MBIST_FAIL(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_PS_TIMER_A_INT_EN BIT(17) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_P2P_RFON_INTMSK BIT(16) -/* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_MAC_MBIST_FAIL 0 -#define BIT_MASK_MAC_MBIST_FAIL 0xfff -#define BIT_MAC_MBIST_FAIL(x) (((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL) -#define BIT_GET_MAC_MBIST_FAIL(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_P2P_RFON_INT_MSK BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16) -/* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MAC_MBIST_FAIL_DRF 0 -#define BIT_MASK_MAC_MBIST_FAIL_DRF 0x3ffff -#define BIT_MAC_MBIST_FAIL_DRF(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF) << BIT_SHIFT_MAC_MBIST_FAIL_DRF) -#define BIT_GET_MAC_MBIST_FAIL_DRF(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF) & BIT_MASK_MAC_MBIST_FAIL_DRF) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TXBCN1ERR_MSK BIT(15) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TX_BCN1ERR_INT_MSK BIT(15) -/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_8051_MBIST_START_PAUSE 26 -#define BIT_MASK_8051_MBIST_START_PAUSE 0x7 -#define BIT_8051_MBIST_START_PAUSE(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE) << BIT_SHIFT_8051_MBIST_START_PAUSE) -#define BIT_GET_8051_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) & BIT_MASK_8051_MBIST_START_PAUSE) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_PS_TIMEOUT2_EN BIT(15) -#define BIT_SHIFT_USB_MBIST_START_PAUSE 24 -#define BIT_MASK_USB_MBIST_START_PAUSE 0x3 -#define BIT_USB_MBIST_START_PAUSE(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE) << BIT_SHIFT_USB_MBIST_START_PAUSE) -#define BIT_GET_USB_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) & BIT_MASK_USB_MBIST_START_PAUSE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16 -#define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f -#define BIT_PCIE_MBIST_START_PAUSE(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE) << BIT_SHIFT_PCIE_MBIST_START_PAUSE) -#define BIT_GET_PCIE_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) & BIT_MASK_PCIE_MBIST_START_PAUSE) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TXBCN1OK_MSK BIT(14) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TX_BCN1OK_INT_MSK BIT(14) -/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MAC_MBIST_START_PAUSE 0 -#define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff -#define BIT_MAC_MBIST_START_PAUSE(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE) << BIT_SHIFT_MAC_MBIST_START_PAUSE) -#define BIT_GET_MAC_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) & BIT_MASK_MAC_MBIST_START_PAUSE) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_PS_TIMEOUT1_EN BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FT_ATIMEND_EMSK BIT(13) -/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1 0 -#define BIT_MASK_MAC_MBIST_START_PAUSE_V1 0x3ffff -#define BIT_MAC_MBIST_START_PAUSE_V1(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1) << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) -#define BIT_GET_MAC_MBIST_START_PAUSE_V1(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) & BIT_MASK_MAC_MBIST_START_PAUSE_V1) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FT_ATIMEND_E_MSK BIT(13) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_PS_TIMEOUT0_EN BIT(13) -/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_8051_MBIST_DONE 26 -#define BIT_MASK_8051_MBIST_DONE 0x7 -#define BIT_8051_MBIST_DONE(x) (((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE) -#define BIT_GET_8051_MBIST_DONE(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_BCNDMAINT_EMSK BIT(12) -#define BIT_SHIFT_USB_MBIST_DONE 24 -#define BIT_MASK_USB_MBIST_DONE 0x3 -#define BIT_USB_MBIST_DONE(x) (((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE) -#define BIT_GET_USB_MBIST_DONE(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_PCIE_MBIST_DONE 16 -#define BIT_MASK_PCIE_MBIST_DONE 0x3f -#define BIT_PCIE_MBIST_DONE(x) (((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE) -#define BIT_GET_PCIE_MBIST_DONE(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_BCNDMAINT_E_MSK_V1 BIT(12) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT12_EN BIT(12) -/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MAC_MBIST_DONE 0 -#define BIT_MASK_MAC_MBIST_DONE 0xfff -#define BIT_MAC_MBIST_DONE(x) (((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE) -#define BIT_GET_MAC_MBIST_DONE(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_GTINT5_MSK BIT(11) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_GT5INT_MSK BIT(11) -/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MAC_MBIST_DONE_V1 0 -#define BIT_MASK_MAC_MBIST_DONE_V1 0x3ffff -#define BIT_MAC_MBIST_DONE_V1(x) (((x) & BIT_MASK_MAC_MBIST_DONE_V1) << BIT_SHIFT_MAC_MBIST_DONE_V1) -#define BIT_GET_MAC_MBIST_DONE_V1(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1) & BIT_MASK_MAC_MBIST_DONE_V1) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT11_EN BIT(11) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_EOSP_INT_MSK BIT(10) -/* 2 REG_MBIST_ROM_CRC_DATA (Offset 0x017C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MBIST_ROM_CRC_DATA 0 -#define BIT_MASK_MBIST_ROM_CRC_DATA 0xffffffffL -#define BIT_MBIST_ROM_CRC_DATA(x) (((x) & BIT_MASK_MBIST_ROM_CRC_DATA) << BIT_SHIFT_MBIST_ROM_CRC_DATA) -#define BIT_GET_MBIST_ROM_CRC_DATA(x) (((x) >> BIT_SHIFT_MBIST_ROM_CRC_DATA) & BIT_MASK_MBIST_ROM_CRC_DATA) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT10_EN BIT(10) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_RX_BCN_E_MSK BIT(9) -/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_MBIST_FAIL_NRML_V1 0 -#define BIT_MASK_MBIST_FAIL_NRML_V1 0x3ffff -#define BIT_MBIST_FAIL_NRML_V1(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_V1) << BIT_SHIFT_MBIST_FAIL_NRML_V1) -#define BIT_GET_MBIST_FAIL_NRML_V1(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1) & BIT_MASK_MBIST_FAIL_NRML_V1) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_RX_BCN_E_INT_MSK BIT(9) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT9_EN BIT(9) -/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MBIST_FAIL_NRML 0 -#define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL -#define BIT_MBIST_FAIL_NRML(x) (((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML) -#define BIT_GET_MBIST_FAIL_NRML(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_RPWM_INT_EN BIT(8) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_RPWMINT_MSK BIT(8) -/* 2 REG_AES_DECRPT_DATA (Offset 0x0180) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_IPS_CFG_ADDR 0 -#define BIT_MASK_IPS_CFG_ADDR 0xff -#define BIT_IPS_CFG_ADDR(x) (((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR) -#define BIT_GET_IPS_CFG_ADDR(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT8_EN BIT(8) -/* 2 REG_AES_DECRPT_CFG (Offset 0x0184) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_IPS_CFG_DATA 0 -#define BIT_MASK_IPS_CFG_DATA 0xffffffffL -#define BIT_IPS_CFG_DATA(x) (((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA) -#define BIT_GET_IPS_CFG_DATA(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_PSTIMER_MSK BIT(7) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_PSTIMER_INT_MSK BIT(7) -/* 2 REG_MACCLKFRQ (Offset 0x018C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MACCLK_FREQ_LOW32 0 -#define BIT_MASK_MACCLK_FREQ_LOW32 0xffffffffL -#define BIT_MACCLK_FREQ_LOW32(x) (((x) & BIT_MASK_MACCLK_FREQ_LOW32) << BIT_SHIFT_MACCLK_FREQ_LOW32) -#define BIT_GET_MACCLK_FREQ_LOW32(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32) & BIT_MASK_MACCLK_FREQ_LOW32) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT7_EN BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TIMEOUT1_MSK BIT(6) -/* 2 REG_TMETER (Offset 0x0190) */ +#endif -#define BIT_TEMP_VALID BIT(31) +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_TEMP_VALUE 24 -#define BIT_MASK_TEMP_VALUE 0x3f -#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE) -#define BIT_GET_TEMP_VALUE(x) (((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TIMEOUT1_INT_MSK BIT(6) -#define BIT_SHIFT_REG_TMETER_TIMER 8 -#define BIT_MASK_REG_TMETER_TIMER 0xfff -#define BIT_REG_TMETER_TIMER(x) (((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER) -#define BIT_GET_REG_TMETER_TIMER(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_REG_TEMP_DELTA 2 -#define BIT_MASK_REG_TEMP_DELTA 0x3f -#define BIT_REG_TEMP_DELTA(x) (((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA) -#define BIT_GET_REG_TEMP_DELTA(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA) +/* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_REG_TMETER_EN BIT(0) +#define BIT_FS_GTINT6_EN BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TIMEOUT0_MSK BIT(5) -/* 2 REG_TMETER (Offset 0x0190) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_MACCLK_FREQ_HIGH10 0 -#define BIT_MASK_MACCLK_FREQ_HIGH10 0x3ff -#define BIT_MACCLK_FREQ_HIGH10(x) (((x) & BIT_MASK_MACCLK_FREQ_HIGH10) << BIT_SHIFT_MACCLK_FREQ_HIGH10) -#define BIT_GET_MACCLK_FREQ_HIGH10(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10) & BIT_MASK_MACCLK_FREQ_HIGH10) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_TIMEOUT0_INT_MSK BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT5_EN BIT(5) -/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_OSC_32K_CLKGEN_0 16 -#define BIT_MASK_OSC_32K_CLKGEN_0 0xffff -#define BIT_OSC_32K_CLKGEN_0(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0) -#define BIT_GET_OSC_32K_CLKGEN_0(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FT_GTINT4_MSK BIT(4) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FT_GT4INT_MSK BIT(4) -/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#endif -#define BIT_32K_CLK_OUT_RDY BIT(12) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MONITOR_CYCLE_LOG2 8 -#define BIT_MASK_MONITOR_CYCLE_LOG2 0xf -#define BIT_MONITOR_CYCLE_LOG2(x) (((x) & BIT_MASK_MONITOR_CYCLE_LOG2) << BIT_SHIFT_MONITOR_CYCLE_LOG2) -#define BIT_GET_MONITOR_CYCLE_LOG2(x) (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2) & BIT_MASK_MONITOR_CYCLE_LOG2) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT4_EN BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FT_GTINT3_MSK BIT(3) -/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_OSC_32K_RES_COMP 4 -#define BIT_MASK_OSC_32K_RES_COMP 0x3 -#define BIT_OSC_32K_RES_COMP(x) (((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP) -#define BIT_GET_OSC_32K_RES_COMP(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP) +/* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_OSC_32K_OUT_SEL BIT(3) +#define BIT_FT_GT3INT_MSK BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +/* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_ISO_WL_2_OSC_32K BIT(1) +#define BIT_FS_GTINT3_EN BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +/* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_POW_CKGEN BIT(0) +#define BIT_GTINT2_MSK BIT(2) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_GT2INT_MSK BIT(2) -/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ +#endif -#define BIT_CAL_32K_REG_WR BIT(31) -#define BIT_CAL_32K_DBG_SEL BIT(22) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_CAL_32K_REG_ADDR 16 -#define BIT_MASK_CAL_32K_REG_ADDR 0x3f -#define BIT_CAL_32K_REG_ADDR(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR) -#define BIT_GET_CAL_32K_REG_ADDR(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT2_EN BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_GTINT1_MSK BIT(1) -/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_FREQVALUE_UNREGCLK 8 -#define BIT_MASK_FREQVALUE_UNREGCLK 0xffffff -#define BIT_FREQVALUE_UNREGCLK(x) (((x) & BIT_MASK_FREQVALUE_UNREGCLK) << BIT_SHIFT_FREQVALUE_UNREGCLK) -#define BIT_GET_FREQVALUE_UNREGCLK(x) (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK) & BIT_MASK_FREQVALUE_UNREGCLK) +/* 2 REG_FTIMR (Offset 0x0138) */ -#define BIT_CAL32K_DBGMOD BIT(7) +#define BIT_GT1INT_MSK BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT1_EN BIT(1) -/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CAL_32K_REG_DATA 0 -#define BIT_MASK_CAL_32K_REG_DATA 0xffff -#define BIT_CAL_32K_REG_DATA(x) (((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA) -#define BIT_GET_CAL_32K_REG_DATA(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_GTINT0_MSK BIT(0) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_GT0INT_MSK BIT(0) -/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NCO_THRS 0 -#define BIT_MASK_NCO_THRS 0x7f -#define BIT_NCO_THRS(x) (((x) & BIT_MASK_NCO_THRS) << BIT_SHIFT_NCO_THRS) -#define BIT_GET_NCO_THRS(x) (((x) >> BIT_SHIFT_NCO_THRS) & BIT_MASK_NCO_THRS) +/* 2 REG_FTIMR (Offset 0x0138) */ +#define BIT_FS_GTINT0_EN BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_GT6INT BIT(31) +#define BIT_TX_NULL1_INT BIT(30) +#define BIT_TX_NULL0_INT BIT(29) +#define BIT_MTI_BCNIVLEAR_INT BIT(28) +#define BIT_ATIM_INT BIT(27) +#define BIT_WWLAN_INT BIT(26) -/* 2 REG_C2HEVT (Offset 0x01A0) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_C2HEVT_MSG 0 -#define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL -#define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG) -#define BIT_GET_C2HEVT_MSG(x) (((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_5_EARLY__INT BIT(26) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_C2H_W_READY BIT(25) -/* 2 REG_C2HEVT (Offset 0x01A0) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_C2HEVT_MSG_V1 0 -#define BIT_MASK_C2HEVT_MSG_V1 0xffffffffL -#define BIT_C2HEVT_MSG_V1(x) (((x) & BIT_MASK_C2HEVT_MSG_V1) << BIT_SHIFT_C2HEVT_MSG_V1) -#define BIT_GET_C2HEVT_MSG_V1(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_V1) & BIT_MASK_C2HEVT_MSG_V1) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_4_EARLY__INT BIT(25) -/* 2 REG_C2HEVT_1 (Offset 0x01A4) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_C2HEVT_MSG_1 0 -#define BIT_MASK_C2HEVT_MSG_1 0xffffffffL -#define BIT_C2HEVT_MSG_1(x) (((x) & BIT_MASK_C2HEVT_MSG_1) << BIT_SHIFT_C2HEVT_MSG_1) -#define BIT_GET_C2HEVT_MSG_1(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_1) & BIT_MASK_C2HEVT_MSG_1) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_TRL_MTR_INT BIT(24) -/* 2 REG_C2HEVT_2 (Offset 0x01A8) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_C2HEVT_MSG_2 0 -#define BIT_MASK_C2HEVT_MSG_2 0xffffffffL -#define BIT_C2HEVT_MSG_2(x) (((x) & BIT_MASK_C2HEVT_MSG_2) << BIT_SHIFT_C2HEVT_MSG_2) -#define BIT_GET_C2HEVT_MSG_2(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_2) & BIT_MASK_C2HEVT_MSG_2) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_3_EARLY__INT BIT(24) -/* 2 REG_C2HEVT_3 (Offset 0x01AC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_C2HEVT_MSG_3 0 -#define BIT_MASK_C2HEVT_MSG_3 0xffffffffL -#define BIT_C2HEVT_MSG_3(x) (((x) & BIT_MASK_C2HEVT_MSG_3) << BIT_SHIFT_C2HEVT_MSG_3) -#define BIT_GET_C2HEVT_MSG_3(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_3) & BIT_MASK_C2HEVT_MSG_3) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_CLR_PS_STATUS BIT(23) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_C_EARLY__INT BIT(23) -/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_SW_DEFINED_PAGE1 0 -#define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL -#define BIT_SW_DEFINED_PAGE1(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1) -#define BIT_GET_SW_DEFINED_PAGE1(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_2_EARLY__INT BIT(23) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_RETRIEVE_BUFFERED_INT BIT(22) -/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SW_DEFINED_PAGE1_V1 0 -#define BIT_MASK_SW_DEFINED_PAGE1_V1 0xffffffffL -#define BIT_SW_DEFINED_PAGE1_V1(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1) << BIT_SHIFT_SW_DEFINED_PAGE1_V1) -#define BIT_GET_SW_DEFINED_PAGE1_V1(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1) & BIT_MASK_SW_DEFINED_PAGE1_V1) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_B_EARLY__INT BIT(22) -/* 2 REG_SW_DEFINED_PAGE2 (Offset 0x01BC) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_SW_DEFINED_PAGE2 0 -#define BIT_MASK_SW_DEFINED_PAGE2 0xffffffffL -#define BIT_SW_DEFINED_PAGE2(x) (((x) & BIT_MASK_SW_DEFINED_PAGE2) << BIT_SHIFT_SW_DEFINED_PAGE2) -#define BIT_GET_SW_DEFINED_PAGE2(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2) & BIT_MASK_SW_DEFINED_PAGE2) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_1_EARLY__INT BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_RPWM2INT BIT(21) -/* 2 REG_MCUTST_I (Offset 0x01C0) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MCUDMSG_I 0 -#define BIT_MASK_MCUDMSG_I 0xffffffffL -#define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I) -#define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_A_EARLY__INT BIT(21) -/* 2 REG_MCUTST_II (Offset 0x01C4) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MCUDMSG_II 0 -#define BIT_MASK_MCUDMSG_II 0xffffffffL -#define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II) -#define BIT_GET_MCUDMSG_II(x) (((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_0_EARLY__INT BIT(21) -/* 2 REG_FMETHR (Offset 0x01C8) */ +#endif -#define BIT_FMSG_INT BIT(31) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FW_MSG 0 -#define BIT_MASK_FW_MSG 0xffffffffL -#define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG) -#define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_TSF_BIT32_TOGGLE_INT_V1 BIT(20) -/* 2 REG_HMETFR (Offset 0x01CC) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HRCV_MSG 24 -#define BIT_MASK_HRCV_MSG 0xff -#define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG) -#define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG) +/* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_INT_BOX3 BIT(3) -#define BIT_INT_BOX2 BIT(2) -#define BIT_INT_BOX1 BIT(1) -#define BIT_INT_BOX0 BIT(0) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20) -/* 2 REG_HMEBOX0 (Offset 0x01D0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HOST_MSG_0 0 -#define BIT_MASK_HOST_MSG_0 0xffffffffL -#define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0) -#define BIT_GET_HOST_MSG_0(x) (((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_TRIGGER_PKT BIT(19) -/* 2 REG_HMEBOX1 (Offset 0x01D4) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HOST_MSG_1 0 -#define BIT_MASK_HOST_MSG_1 0xffffffffL -#define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1) -#define BIT_GET_HOST_MSG_1(x) (((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_C_INT BIT(19) -/* 2 REG_HMEBOX2 (Offset 0x01D8) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HOST_MSG_2 0 -#define BIT_MASK_HOST_MSG_2 0xffffffffL -#define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2) -#define BIT_GET_HOST_MSG_2(x) (((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_5_INT BIT(19) -/* 2 REG_HMEBOX3 (Offset 0x01DC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HOST_MSG_3 0 -#define BIT_MASK_HOST_MSG_3 0xffffffffL -#define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3) -#define BIT_GET_HOST_MSG_3(x) (((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FW_BTCMD_INT BIT(18) -/* 2 REG_LLT_INIT (Offset 0x01E0) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LLTE_RWM 30 -#define BIT_MASK_LLTE_RWM 0x3 -#define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM) -#define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_B_INT BIT(18) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_4_INT BIT(18) -/* 2 REG_LLT_INIT (Offset 0x01E0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LLTINI_PDATA 16 -#define BIT_MASK_LLTINI_PDATA 0xff -#define BIT_LLTINI_PDATA(x) (((x) & BIT_MASK_LLTINI_PDATA) << BIT_SHIFT_LLTINI_PDATA) -#define BIT_GET_LLTINI_PDATA(x) (((x) >> BIT_SHIFT_LLTINI_PDATA) & BIT_MASK_LLTINI_PDATA) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_P2P_RFOFF_INT BIT(17) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_A_INT BIT(17) -/* 2 REG_LLT_INIT (Offset 0x01E0) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_LLTINI_PDATA_V1 16 -#define BIT_MASK_LLTINI_PDATA_V1 0xfff -#define BIT_LLTINI_PDATA_V1(x) (((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1) -#define BIT_GET_LLTINI_PDATA_V1(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_3_INT BIT(17) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_FTISR (Offset 0x013C) */ -/* 2 REG_LLT_INIT (Offset 0x01E0) */ +#define BIT_P2P_RFON_INT BIT(16) +#define BIT_SHIFT_LLTINI_PDATA 16 +#define BIT_MASK_LLTINI_PDATA 0xff +#define BIT_LLTINI_PDATA(x) \ + (((x) & BIT_MASK_LLTINI_PDATA) << BIT_SHIFT_LLTINI_PDATA) +#define BITS_LLTINI_PDATA (BIT_MASK_LLTINI_PDATA << BIT_SHIFT_LLTINI_PDATA) +#define BIT_CLEAR_LLTINI_PDATA(x) ((x) & (~BITS_LLTINI_PDATA)) +#define BIT_GET_LLTINI_PDATA(x) \ + (((x) >> BIT_SHIFT_LLTINI_PDATA) & BIT_MASK_LLTINI_PDATA) +#define BIT_SET_LLTINI_PDATA(x, v) \ + (BIT_CLEAR_LLTINI_PDATA(x) | BIT_LLTINI_PDATA(v)) -#define BIT_SHIFT_LLTINI_ADDR 8 -#define BIT_MASK_LLTINI_ADDR 0xff -#define BIT_LLTINI_ADDR(x) (((x) & BIT_MASK_LLTINI_ADDR) << BIT_SHIFT_LLTINI_ADDR) -#define BIT_GET_LLTINI_ADDR(x) (((x) >> BIT_SHIFT_LLTINI_ADDR) & BIT_MASK_LLTINI_ADDR) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LLTINI_HDATA 0 -#define BIT_MASK_LLTINI_HDATA 0xff -#define BIT_LLTINI_HDATA(x) (((x) & BIT_MASK_LLTINI_HDATA) << BIT_SHIFT_LLTINI_HDATA) -#define BIT_GET_LLTINI_HDATA(x) (((x) >> BIT_SHIFT_LLTINI_HDATA) & BIT_MASK_LLTINI_HDATA) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_CPUMGQ_TX_TIMER_INT BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_TX_BCN1ERR_INT BIT(15) -/* 2 REG_LLT_INIT (Offset 0x01E0) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LLTINI_HDATA_V1 0 -#define BIT_MASK_LLTINI_HDATA_V1 0xfff -#define BIT_LLTINI_HDATA_V1(x) (((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1) -#define BIT_GET_LLTINI_HDATA_V1(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_PS_TIMEOUT2_INT BIT(15) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_2_INT BIT(15) -/* 2 REG_GENTST (Offset 0x01E4) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_GENTST 0 -#define BIT_MASK_GENTST 0xffffffffL -#define BIT_GENTST(x) (((x) & BIT_MASK_GENTST) << BIT_SHIFT_GENTST) -#define BIT_GET_GENTST(x) (((x) >> BIT_SHIFT_GENTST) & BIT_MASK_GENTST) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_TX_BCN1OK_INT BIT(14) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_PS_TIMEOUT1_INT BIT(14) -/* 2 REG_LLT_INIT_ADDR (Offset 0x01E4) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_LLTINI_ADDR_V1 0 -#define BIT_MASK_LLTINI_ADDR_V1 0xfff -#define BIT_LLTINI_ADDR_V1(x) (((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1) -#define BIT_GET_LLTINI_ADDR_V1(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_1_INT BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FT_ATIMEND_E BIT(13) -/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BB_WRITE_READ 30 -#define BIT_MASK_BB_WRITE_READ 0x3 -#define BIT_BB_WRITE_READ(x) (((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ) -#define BIT_GET_BB_WRITE_READ(x) (((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_PS_TIMEOUT0_INT BIT(13) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PS_TIMER_0_INT BIT(13) -/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BB_WRITE_EN_V1 16 -#define BIT_MASK_BB_WRITE_EN_V1 0xf -#define BIT_BB_WRITE_EN_V1(x) (((x) & BIT_MASK_BB_WRITE_EN_V1) << BIT_SHIFT_BB_WRITE_EN_V1) -#define BIT_GET_BB_WRITE_EN_V1(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_V1) & BIT_MASK_BB_WRITE_EN_V1) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_BCNDMAINT_E_V1 BIT(12) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_GTINT12_INT BIT(12) -#define BIT_SHIFT_BB_WRITE_EN 12 -#define BIT_MASK_BB_WRITE_EN 0xf -#define BIT_BB_WRITE_EN(x) (((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN) -#define BIT_GET_BB_WRITE_EN(x) (((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BB_ADDR 2 -#define BIT_MASK_BB_ADDR 0x1ff -#define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR) -#define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_GT5INT BIT(11) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_GTINT11_INT BIT(11) -/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BB_ADDR_V1 2 -#define BIT_MASK_BB_ADDR_V1 0xfff -#define BIT_BB_ADDR_V1(x) (((x) & BIT_MASK_BB_ADDR_V1) << BIT_SHIFT_BB_ADDR_V1) -#define BIT_GET_BB_ADDR_V1(x) (((x) >> BIT_SHIFT_BB_ADDR_V1) & BIT_MASK_BB_ADDR_V1) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_EOSP_INT BIT(10) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_FTISR (Offset 0x013C) */ -/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ +#define BIT_FS_GTINT10_INT BIT(10) -#define BIT_BB_ERRACC BIT(0) +#endif -/* 2 REG_BB_ACCESS_DATA (Offset 0x01EC) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_SHIFT_BB_DATA 0 -#define BIT_MASK_BB_DATA 0xffffffffL -#define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA) -#define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA) +#define BIT_RX_BCN_E_INT BIT(9) +#endif -/* 2 REG_HMEBOX_E0 (Offset 0x01F0) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_SHIFT_HMEBOX_E0 0 -#define BIT_MASK_HMEBOX_E0 0xffffffffL -#define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0) -#define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0) +#define BIT_FS_GTINT9_INT BIT(9) +#endif -/* 2 REG_HMEBOX_E1 (Offset 0x01F4) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_SHIFT_HMEBOX_E1 0 -#define BIT_MASK_HMEBOX_E1 0xffffffffL -#define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1) -#define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1) +#define BIT_RPWMINT BIT(8) +#define BIT_SHIFT_LLTINI_ADDR 8 +#define BIT_MASK_LLTINI_ADDR 0xff +#define BIT_LLTINI_ADDR(x) \ + (((x) & BIT_MASK_LLTINI_ADDR) << BIT_SHIFT_LLTINI_ADDR) +#define BITS_LLTINI_ADDR (BIT_MASK_LLTINI_ADDR << BIT_SHIFT_LLTINI_ADDR) +#define BIT_CLEAR_LLTINI_ADDR(x) ((x) & (~BITS_LLTINI_ADDR)) +#define BIT_GET_LLTINI_ADDR(x) \ + (((x) >> BIT_SHIFT_LLTINI_ADDR) & BIT_MASK_LLTINI_ADDR) +#define BIT_SET_LLTINI_ADDR(x, v) \ + (BIT_CLEAR_LLTINI_ADDR(x) | BIT_LLTINI_ADDR(v)) -/* 2 REG_HMEBOX_E2 (Offset 0x01F8) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HMEBOX_E2 0 -#define BIT_MASK_HMEBOX_E2 0xffffffffL -#define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2) -#define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_GTINT8_INT BIT(8) -/* 2 REG_HMEBOX_E3 (Offset 0x01FC) */ +#endif -#define BIT_LD_RQPN BIT(31) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HMEBOX_E3 0 -#define BIT_MASK_HMEBOX_E3 0xffffffffL -#define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3) -#define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_PSTIMER_INT BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_GTINT7_INT BIT(7) -/* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */ +#endif -#define BIT_EPQ_PUBLIC_DIS BIT(27) -#define BIT_NPQ_PUBLIC_DIS BIT(26) -#define BIT_LPQ_PUBLIC_DIS BIT(25) -#define BIT_HPQ_PUBLIC_DIS BIT(24) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PUBQ 16 -#define BIT_MASK_PUBQ 0xff -#define BIT_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ) -#define BIT_GET_PUBQ(x) (((x) >> BIT_SHIFT_PUBQ) & BIT_MASK_PUBQ) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_TIMEOUT1_INT BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_GTINT6_INT BIT(6) -/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16 -#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff -#define BIT_TX_OQT_HE_FREE_SPACE_V1(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) -#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_TIMEOUT0_INT BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_GTINT5_INT BIT(5) -/* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LPQ 8 -#define BIT_MASK_LPQ 0xff -#define BIT_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ) -#define BIT_GET_LPQ(x) (((x) >> BIT_SHIFT_LPQ) & BIT_MASK_LPQ) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FT_GT4INT BIT(4) -#define BIT_SHIFT_HPQ 0 -#define BIT_MASK_HPQ 0xff -#define BIT_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ) -#define BIT_GET_HPQ(x) (((x) >> BIT_SHIFT_HPQ) & BIT_MASK_HPQ) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_GTINT4_INT BIT(4) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FT_GT3INT BIT(3) -#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0 -#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff -#define BIT_TX_OQT_NL_FREE_SPACE_V1(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) -#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +/* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_BCN_VALID_1_V1 BIT(31) +#define BIT_FS_GTINT3_INT BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_GT2INT BIT(2) -/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ - - -#define BIT_SHIFT_TXPKTNUM 24 -#define BIT_MASK_TXPKTNUM 0xff -#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM) -#define BIT_GET_TXPKTNUM(x) (((x) >> BIT_SHIFT_TXPKTNUM) & BIT_MASK_TXPKTNUM) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PUBQ_AVAL_PG 16 -#define BIT_MASK_PUBQ_AVAL_PG 0xff -#define BIT_PUBQ_AVAL_PG(x) (((x) & BIT_MASK_PUBQ_AVAL_PG) << BIT_SHIFT_PUBQ_AVAL_PG) -#define BIT_GET_PUBQ_AVAL_PG(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG) & BIT_MASK_PUBQ_AVAL_PG) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_GTINT2_INT BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_GT1INT BIT(1) -/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BCN_HEAD_1_V1 16 -#define BIT_MASK_BCN_HEAD_1_V1 0xfff -#define BIT_BCN_HEAD_1_V1(x) (((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1) -#define BIT_GET_BCN_HEAD_1_V1(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1) +/* 2 REG_FTISR (Offset 0x013C) */ -#define BIT_BCN_VALID_V1 BIT(15) +#define BIT_FS_GTINT1_INT BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_FTISR (Offset 0x013C) */ -/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ +#define BIT_GT0INT BIT(0) +#define BIT_SHIFT_LLTINI_HDATA 0 +#define BIT_MASK_LLTINI_HDATA 0xff +#define BIT_LLTINI_HDATA(x) \ + (((x) & BIT_MASK_LLTINI_HDATA) << BIT_SHIFT_LLTINI_HDATA) +#define BITS_LLTINI_HDATA (BIT_MASK_LLTINI_HDATA << BIT_SHIFT_LLTINI_HDATA) +#define BIT_CLEAR_LLTINI_HDATA(x) ((x) & (~BITS_LLTINI_HDATA)) +#define BIT_GET_LLTINI_HDATA(x) \ + (((x) >> BIT_SHIFT_LLTINI_HDATA) & BIT_MASK_LLTINI_HDATA) +#define BIT_SET_LLTINI_HDATA(x, v) \ + (BIT_CLEAR_LLTINI_HDATA(x) | BIT_LLTINI_HDATA(v)) -#define BIT_SHIFT_LPQ_AVAL_PG 8 -#define BIT_MASK_LPQ_AVAL_PG 0xff -#define BIT_LPQ_AVAL_PG(x) (((x) & BIT_MASK_LPQ_AVAL_PG) << BIT_SHIFT_LPQ_AVAL_PG) -#define BIT_GET_LPQ_AVAL_PG(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG) & BIT_MASK_LPQ_AVAL_PG) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HPQ_AVAL_PG 0 -#define BIT_MASK_HPQ_AVAL_PG 0xff -#define BIT_HPQ_AVAL_PG(x) (((x) & BIT_MASK_HPQ_AVAL_PG) << BIT_SHIFT_HPQ_AVAL_PG) -#define BIT_GET_HPQ_AVAL_PG(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG) & BIT_MASK_HPQ_AVAL_PG) +/* 2 REG_FTISR (Offset 0x013C) */ +#define BIT_FS_GTINT0_INT BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_SHIFT_PKTBUF_WRITE_EN 24 +#define BIT_MASK_PKTBUF_WRITE_EN 0xff +#define BIT_PKTBUF_WRITE_EN(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN) +#define BITS_PKTBUF_WRITE_EN \ + (BIT_MASK_PKTBUF_WRITE_EN << BIT_SHIFT_PKTBUF_WRITE_EN) +#define BIT_CLEAR_PKTBUF_WRITE_EN(x) ((x) & (~BITS_PKTBUF_WRITE_EN)) +#define BIT_GET_PKTBUF_WRITE_EN(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN) +#define BIT_SET_PKTBUF_WRITE_EN(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN(x) | BIT_PKTBUF_WRITE_EN(v)) -/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCN_HEAD_V1 0 -#define BIT_MASK_BCN_HEAD_V1 0xfff -#define BIT_BCN_HEAD_V1(x) (((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1) -#define BIT_GET_BCN_HEAD_V1(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1) +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_TXPKT_BUF_READ_EN BIT(23) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_TXPKTBUF_DBG BIT(23) -/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LLT_FREE_PAGE 24 -#define BIT_MASK_LLT_FREE_PAGE 0xff -#define BIT_LLT_FREE_PAGE(x) (((x) & BIT_MASK_LLT_FREE_PAGE) << BIT_SHIFT_LLT_FREE_PAGE) -#define BIT_GET_LLT_FREE_PAGE(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE) & BIT_MASK_LLT_FREE_PAGE) +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_TXRPTBUF_DBG BIT(23) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_TXRPT_BUF_READ_EN BIT(20) -/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24 -#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_TXRPTBUF_DBG_V2 BIT(20) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ +#define BIT_TXPKTBUF_DBG_V2 BIT(20) -/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_BCN_VALID BIT(16) +/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ -#define BIT_SHIFT_BCN_HEAD 8 -#define BIT_MASK_BCN_HEAD 0xff -#define BIT_BCN_HEAD(x) (((x) & BIT_MASK_BCN_HEAD) << BIT_SHIFT_BCN_HEAD) -#define BIT_GET_BCN_HEAD(x) (((x) >> BIT_SHIFT_BCN_HEAD) & BIT_MASK_BCN_HEAD) +#define BIT_RXPKT_BUF_READ_EN BIT(16) +#define BIT_SHIFT_PKTBUF_ADDR 0 +#define BIT_MASK_PKTBUF_ADDR 0x1fff +#define BIT_PKTBUF_ADDR(x) \ + (((x) & BIT_MASK_PKTBUF_ADDR) << BIT_SHIFT_PKTBUF_ADDR) +#define BITS_PKTBUF_ADDR (BIT_MASK_PKTBUF_ADDR << BIT_SHIFT_PKTBUF_ADDR) +#define BIT_CLEAR_PKTBUF_ADDR(x) ((x) & (~BITS_PKTBUF_ADDR)) +#define BIT_GET_PKTBUF_ADDR(x) \ + (((x) >> BIT_SHIFT_PKTBUF_ADDR) & BIT_MASK_PKTBUF_ADDR) +#define BIT_SET_PKTBUF_ADDR(x, v) \ + (BIT_CLEAR_PKTBUF_ADDR(x) | BIT_PKTBUF_ADDR(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_PKTBUF_DBG_DATA_L (Offset 0x0144) */ -/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_SHIFT_PKTBUF_DBG_DATA_L 0 +#define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_L(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L) +#define BITS_PKTBUF_DBG_DATA_L \ + (BIT_MASK_PKTBUF_DBG_DATA_L << BIT_SHIFT_PKTBUF_DBG_DATA_L) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L(x) ((x) & (~BITS_PKTBUF_DBG_DATA_L)) +#define BIT_GET_PKTBUF_DBG_DATA_L(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L) +#define BIT_SET_PKTBUF_DBG_DATA_L(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L(x) | BIT_PKTBUF_DBG_DATA_L(v)) +/* 2 REG_PKTBUF_DBG_DATA_H (Offset 0x0148) */ -#define BIT_SHIFT_LLT_FREE_PAGE_V1 8 -#define BIT_MASK_LLT_FREE_PAGE_V1 0xffff -#define BIT_LLT_FREE_PAGE_V1(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1) -#define BIT_GET_LLT_FREE_PAGE_V1(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1) +#define BIT_SHIFT_PKTBUF_DBG_DATA_H 0 +#define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_H(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H) +#define BITS_PKTBUF_DBG_DATA_H \ + (BIT_MASK_PKTBUF_DBG_DATA_H << BIT_SHIFT_PKTBUF_DBG_DATA_H) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H(x) ((x) & (~BITS_PKTBUF_DBG_DATA_H)) +#define BIT_GET_PKTBUF_DBG_DATA_H(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H) +#define BIT_SET_PKTBUF_DBG_DATA_H(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H(x) | BIT_PKTBUF_DBG_DATA_H(v)) +/* 2 REG_CPWM2 (Offset 0x014C) */ -#endif +#define BIT_SHIFT_L0S_TO_RCVY_NUM 16 +#define BIT_MASK_L0S_TO_RCVY_NUM 0xff +#define BIT_L0S_TO_RCVY_NUM(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM) +#define BITS_L0S_TO_RCVY_NUM \ + (BIT_MASK_L0S_TO_RCVY_NUM << BIT_SHIFT_L0S_TO_RCVY_NUM) +#define BIT_CLEAR_L0S_TO_RCVY_NUM(x) ((x) & (~BITS_L0S_TO_RCVY_NUM)) +#define BIT_GET_L0S_TO_RCVY_NUM(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM) +#define BIT_SET_L0S_TO_RCVY_NUM(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM(x) | BIT_L0S_TO_RCVY_NUM(v)) + +#define BIT_CPWM2_TOGGLING BIT(15) + +#define BIT_SHIFT_CPWM2_MOD 0 +#define BIT_MASK_CPWM2_MOD 0x7fff +#define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD) +#define BITS_CPWM2_MOD (BIT_MASK_CPWM2_MOD << BIT_SHIFT_CPWM2_MOD) +#define BIT_CLEAR_CPWM2_MOD(x) ((x) & (~BITS_CPWM2_MOD)) +#define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD) +#define BIT_SET_CPWM2_MOD(x, v) (BIT_CLEAR_CPWM2_MOD(x) | BIT_CPWM2_MOD(v)) +/* 2 REG_TC0_CTRL (Offset 0x0150) */ -#if (HALMAC_8814AMP_SUPPORT) +#define BIT_TC0INT_EN BIT(26) +#define BIT_TC0MODE BIT(25) +#define BIT_TC0EN BIT(24) +#define BIT_SHIFT_TC0DATA 0 +#define BIT_MASK_TC0DATA 0xffffff +#define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA) +#define BITS_TC0DATA (BIT_MASK_TC0DATA << BIT_SHIFT_TC0DATA) +#define BIT_CLEAR_TC0DATA(x) ((x) & (~BITS_TC0DATA)) +#define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA) +#define BIT_SET_TC0DATA(x, v) (BIT_CLEAR_TC0DATA(x) | BIT_TC0DATA(v)) -/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +/* 2 REG_TC1_CTRL (Offset 0x0154) */ +#define BIT_TC1INT_EN BIT(26) +#define BIT_TC1MODE BIT(25) +#define BIT_TC1EN BIT(24) -#define BIT_SHIFT_LLT_FREE_PAGE_V2 8 -#define BIT_MASK_LLT_FREE_PAGE_V2 0xfff -#define BIT_LLT_FREE_PAGE_V2(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V2) << BIT_SHIFT_LLT_FREE_PAGE_V2) -#define BIT_GET_LLT_FREE_PAGE_V2(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2) & BIT_MASK_LLT_FREE_PAGE_V2) +#define BIT_SHIFT_TC1DATA 0 +#define BIT_MASK_TC1DATA 0xffffff +#define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA) +#define BITS_TC1DATA (BIT_MASK_TC1DATA << BIT_SHIFT_TC1DATA) +#define BIT_CLEAR_TC1DATA(x) ((x) & (~BITS_TC1DATA)) +#define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA) +#define BIT_SET_TC1DATA(x, v) (BIT_CLEAR_TC1DATA(x) | BIT_TC1DATA(v)) +/* 2 REG_TC2_CTRL (Offset 0x0158) */ -#endif +#define BIT_TC2INT_EN BIT(26) +#define BIT_TC2MODE BIT(25) +#define BIT_TC2EN BIT(24) +#define BIT_SHIFT_TC2DATA 0 +#define BIT_MASK_TC2DATA 0xffffff +#define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA) +#define BITS_TC2DATA (BIT_MASK_TC2DATA << BIT_SHIFT_TC2DATA) +#define BIT_CLEAR_TC2DATA(x) ((x) & (~BITS_TC2DATA)) +#define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA) +#define BIT_SET_TC2DATA(x, v) (BIT_CLEAR_TC2DATA(x) | BIT_TC2DATA(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TC3_CTRL (Offset 0x015C) */ +#define BIT_TC3INT_EN BIT(26) +#define BIT_TC3MODE BIT(25) +#define BIT_TC3EN BIT(24) -/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ +#define BIT_SHIFT_TC3DATA 0 +#define BIT_MASK_TC3DATA 0xffffff +#define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA) +#define BITS_TC3DATA (BIT_MASK_TC3DATA << BIT_SHIFT_TC3DATA) +#define BIT_CLEAR_TC3DATA(x) ((x) & (~BITS_TC3DATA)) +#define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA) +#define BIT_SET_TC3DATA(x, v) (BIT_CLEAR_TC3DATA(x) | BIT_TC3DATA(v)) +/* 2 REG_TC4_CTRL (Offset 0x0160) */ -#define BIT_SHIFT_BLK_DESC_NUM 4 -#define BIT_MASK_BLK_DESC_NUM 0xf -#define BIT_BLK_DESC_NUM(x) (((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM) -#define BIT_GET_BLK_DESC_NUM(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM) +#define BIT_TC4INT_EN BIT(26) +#define BIT_TC4MODE BIT(25) +#define BIT_TC4EN BIT(24) +#define BIT_SHIFT_TC4DATA 0 +#define BIT_MASK_TC4DATA 0xffffff +#define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA) +#define BITS_TC4DATA (BIT_MASK_TC4DATA << BIT_SHIFT_TC4DATA) +#define BIT_CLEAR_TC4DATA(x) ((x) & (~BITS_TC4DATA)) +#define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA) +#define BIT_SET_TC4DATA(x, v) (BIT_CLEAR_TC4DATA(x) | BIT_TC4DATA(v)) -#endif +/* 2 REG_TCUNIT_BASE (Offset 0x0164) */ +#define BIT_SHIFT_TCUNIT_BASE 0 +#define BIT_MASK_TCUNIT_BASE 0x3fff +#define BIT_TCUNIT_BASE(x) \ + (((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE) +#define BITS_TCUNIT_BASE (BIT_MASK_TCUNIT_BASE << BIT_SHIFT_TCUNIT_BASE) +#define BIT_CLEAR_TCUNIT_BASE(x) ((x) & (~BITS_TCUNIT_BASE)) +#define BIT_GET_TCUNIT_BASE(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE) +#define BIT_SET_TCUNIT_BASE(x, v) \ + (BIT_CLEAR_TCUNIT_BASE(x) | BIT_TCUNIT_BASE(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +/* 2 REG_TC5_CTRL (Offset 0x0168) */ -#define BIT_R_BCN_HEAD_SEL BIT(3) -#define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2) -#define BIT_LLT_DBG_SEL BIT(1) -#define BIT_AUTO_INIT_LLT_V1 BIT(0) +#define BIT_TC50INT_EN BIT(26) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +/* 2 REG_TC5_CTRL (Offset 0x0168) */ -#define BIT_EM_CHKSUM_FIN BIT(31) -#define BIT_EMN_PCIE_DMA_MOD BIT(30) +#define BIT_TC5INT_EN BIT(26) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_TC5_CTRL (Offset 0x0168) */ -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_TC5MODE BIT(25) +#define BIT_TC5EN BIT(24) -#define BIT_EN_TXQUE_CLR BIT(29) -#define BIT_EN_PCIE_FIFO_MODE BIT(28) +#define BIT_SHIFT_TC5DATA 0 +#define BIT_MASK_TC5DATA 0xffffff +#define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA) +#define BITS_TC5DATA (BIT_MASK_TC5DATA << BIT_SHIFT_TC5DATA) +#define BIT_CLEAR_TC5DATA(x) ((x) & (~BITS_TC5DATA)) +#define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA) +#define BIT_SET_TC5DATA(x, v) (BIT_CLEAR_TC5DATA(x) | BIT_TC5DATA(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TC6_CTRL (Offset 0x016C) */ -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_TC60INT_EN BIT(26) +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PG_UNDER_TH 16 -#define BIT_MASK_PG_UNDER_TH 0xff -#define BIT_PG_UNDER_TH(x) (((x) & BIT_MASK_PG_UNDER_TH) << BIT_SHIFT_PG_UNDER_TH) -#define BIT_GET_PG_UNDER_TH(x) (((x) >> BIT_SHIFT_PG_UNDER_TH) & BIT_MASK_PG_UNDER_TH) +/* 2 REG_TC6_CTRL (Offset 0x016C) */ +#define BIT_TC6INT_EN BIT(26) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TC6_CTRL (Offset 0x016C) */ +#define BIT_TC6MODE BIT(25) +#define BIT_TC6EN BIT(24) -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PG_UNDER_TH_V1 16 -#define BIT_MASK_PG_UNDER_TH_V1 0xfff -#define BIT_PG_UNDER_TH_V1(x) (((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1) -#define BIT_GET_PG_UNDER_TH_V1(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1) +/* 2 REG_TC6_CTRL (Offset 0x016C) */ +#define BIT_SHIFT_SEQNUM_MID 16 +#define BIT_MASK_SEQNUM_MID 0xffff +#define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID) +#define BITS_SEQNUM_MID (BIT_MASK_SEQNUM_MID << BIT_SHIFT_SEQNUM_MID) +#define BIT_CLEAR_SEQNUM_MID(x) ((x) & (~BITS_SEQNUM_MID)) +#define BIT_GET_SEQNUM_MID(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID) +#define BIT_SET_SEQNUM_MID(x, v) (BIT_CLEAR_SEQNUM_MID(x) | BIT_SEQNUM_MID(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +/* 2 REG_TC6_CTRL (Offset 0x016C) */ -#define BIT_EN_RESET_RESTORE_H2C BIT(15) +#define BIT_SHIFT_TC6DATA 0 +#define BIT_MASK_TC6DATA 0xffffff +#define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA) +#define BITS_TC6DATA (BIT_MASK_TC6DATA << BIT_SHIFT_TC6DATA) +#define BIT_CLEAR_TC6DATA(x) ((x) & (~BITS_TC6DATA)) +#define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA) +#define BIT_SET_TC6DATA(x, v) (BIT_CLEAR_TC6DATA(x) | BIT_TC6DATA(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_WLON_MBIST_DRF_FAIL 30 +#define BIT_MASK_WLON_MBIST_DRF_FAIL 0x3 +#define BIT_WLON_MBIST_DRF_FAIL(x) \ + (((x) & BIT_MASK_WLON_MBIST_DRF_FAIL) << BIT_SHIFT_WLON_MBIST_DRF_FAIL) +#define BITS_WLON_MBIST_DRF_FAIL \ + (BIT_MASK_WLON_MBIST_DRF_FAIL << BIT_SHIFT_WLON_MBIST_DRF_FAIL) +#define BIT_CLEAR_WLON_MBIST_DRF_FAIL(x) ((x) & (~BITS_WLON_MBIST_DRF_FAIL)) +#define BIT_GET_WLON_MBIST_DRF_FAIL(x) \ + (((x) >> BIT_SHIFT_WLON_MBIST_DRF_FAIL) & BIT_MASK_WLON_MBIST_DRF_FAIL) +#define BIT_SET_WLON_MBIST_DRF_FAIL(x, v) \ + (BIT_CLEAR_WLON_MBIST_DRF_FAIL(x) | BIT_WLON_MBIST_DRF_FAIL(v)) -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#endif -#define BIT_RESTORE_H2C_ADDRESS BIT(15) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_8051_MBIST_FAIL 26 +#define BIT_MASK_8051_MBIST_FAIL 0x7 +#define BIT_8051_MBIST_FAIL(x) \ + (((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL) +#define BITS_8051_MBIST_FAIL \ + (BIT_MASK_8051_MBIST_FAIL << BIT_SHIFT_8051_MBIST_FAIL) +#define BIT_CLEAR_8051_MBIST_FAIL(x) ((x) & (~BITS_8051_MBIST_FAIL)) +#define BIT_GET_8051_MBIST_FAIL(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL) +#define BIT_SET_8051_MBIST_FAIL(x, v) \ + (BIT_CLEAR_8051_MBIST_FAIL(x) | BIT_8051_MBIST_FAIL(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ -#define BIT_SDIO_TDE_FINISH BIT(14) +#define BIT_SHIFT_8051_MBIST_DRF_FAIL 26 +#define BIT_MASK_8051_MBIST_DRF_FAIL 0x3f +#define BIT_8051_MBIST_DRF_FAIL(x) \ + (((x) & BIT_MASK_8051_MBIST_DRF_FAIL) << BIT_SHIFT_8051_MBIST_DRF_FAIL) +#define BITS_8051_MBIST_DRF_FAIL \ + (BIT_MASK_8051_MBIST_DRF_FAIL << BIT_SHIFT_8051_MBIST_DRF_FAIL) +#define BIT_CLEAR_8051_MBIST_DRF_FAIL(x) ((x) & (~BITS_8051_MBIST_DRF_FAIL)) +#define BIT_GET_8051_MBIST_DRF_FAIL(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL) & BIT_MASK_8051_MBIST_DRF_FAIL) +#define BIT_SET_8051_MBIST_DRF_FAIL(x, v) \ + (BIT_CLEAR_8051_MBIST_DRF_FAIL(x) | BIT_8051_MBIST_DRF_FAIL(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_USB_MBIST_FAIL 24 +#define BIT_MASK_USB_MBIST_FAIL 0x3 +#define BIT_USB_MBIST_FAIL(x) \ + (((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL) +#define BITS_USB_MBIST_FAIL \ + (BIT_MASK_USB_MBIST_FAIL << BIT_SHIFT_USB_MBIST_FAIL) +#define BIT_CLEAR_USB_MBIST_FAIL(x) ((x) & (~BITS_USB_MBIST_FAIL)) +#define BIT_GET_USB_MBIST_FAIL(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL) +#define BIT_SET_USB_MBIST_FAIL(x, v) \ + (BIT_CLEAR_USB_MBIST_FAIL(x) | BIT_USB_MBIST_FAIL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ + +#define BIT_SHIFT_USB_MBIST_DRF_FAIL 24 +#define BIT_MASK_USB_MBIST_DRF_FAIL 0x3 +#define BIT_USB_MBIST_DRF_FAIL(x) \ + (((x) & BIT_MASK_USB_MBIST_DRF_FAIL) << BIT_SHIFT_USB_MBIST_DRF_FAIL) +#define BITS_USB_MBIST_DRF_FAIL \ + (BIT_MASK_USB_MBIST_DRF_FAIL << BIT_SHIFT_USB_MBIST_DRF_FAIL) +#define BIT_CLEAR_USB_MBIST_DRF_FAIL(x) ((x) & (~BITS_USB_MBIST_DRF_FAIL)) +#define BIT_GET_USB_MBIST_DRF_FAIL(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL) & BIT_MASK_USB_MBIST_DRF_FAIL) +#define BIT_SET_USB_MBIST_DRF_FAIL(x, v) \ + (BIT_CLEAR_USB_MBIST_DRF_FAIL(x) | BIT_USB_MBIST_DRF_FAIL(v)) + +#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL 18 +#define BIT_MASK_PCIE_MBIST_DRF_FAIL 0x3f +#define BIT_PCIE_MBIST_DRF_FAIL(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL) << BIT_SHIFT_PCIE_MBIST_DRF_FAIL) +#define BITS_PCIE_MBIST_DRF_FAIL \ + (BIT_MASK_PCIE_MBIST_DRF_FAIL << BIT_SHIFT_PCIE_MBIST_DRF_FAIL) +#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) ((x) & (~BITS_PCIE_MBIST_DRF_FAIL)) +#define BIT_GET_PCIE_MBIST_DRF_FAIL(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL) & BIT_MASK_PCIE_MBIST_DRF_FAIL) +#define BIT_SET_PCIE_MBIST_DRF_FAIL(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) | BIT_PCIE_MBIST_DRF_FAIL(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +/* 2 REG_MBIST_FAIL (Offset 0x0170) */ -#define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13) -#define BIT_RST_RDPTR BIT(12) -#define BIT_RST_WRPTR BIT(11) -#define BIT_CHK_PG_TH_EN BIT(10) -#define BIT_DROP_DATA_EN BIT(9) -#define BIT_CHECK_OFFSET_EN BIT(8) +#define BIT_SHIFT_PCIE_MBIST_FAIL 16 +#define BIT_MASK_PCIE_MBIST_FAIL 0x3f +#define BIT_PCIE_MBIST_FAIL(x) \ + (((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL) +#define BITS_PCIE_MBIST_FAIL \ + (BIT_MASK_PCIE_MBIST_FAIL << BIT_SHIFT_PCIE_MBIST_FAIL) +#define BIT_CLEAR_PCIE_MBIST_FAIL(x) ((x) & (~BITS_PCIE_MBIST_FAIL)) +#define BIT_GET_PCIE_MBIST_FAIL(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL) +#define BIT_SET_PCIE_MBIST_FAIL(x, v) \ + (BIT_CLEAR_PCIE_MBIST_FAIL(x) | BIT_PCIE_MBIST_FAIL(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ + +#define BIT_SHIFT_WLOFF_MBIST_DRF_FAIL 16 +#define BIT_MASK_WLOFF_MBIST_DRF_FAIL 0x3fff +#define BIT_WLOFF_MBIST_DRF_FAIL(x) \ + (((x) & BIT_MASK_WLOFF_MBIST_DRF_FAIL) \ + << BIT_SHIFT_WLOFF_MBIST_DRF_FAIL) +#define BITS_WLOFF_MBIST_DRF_FAIL \ + (BIT_MASK_WLOFF_MBIST_DRF_FAIL << BIT_SHIFT_WLOFF_MBIST_DRF_FAIL) +#define BIT_CLEAR_WLOFF_MBIST_DRF_FAIL(x) ((x) & (~BITS_WLOFF_MBIST_DRF_FAIL)) +#define BIT_GET_WLOFF_MBIST_DRF_FAIL(x) \ + (((x) >> BIT_SHIFT_WLOFF_MBIST_DRF_FAIL) & \ + BIT_MASK_WLOFF_MBIST_DRF_FAIL) +#define BIT_SET_WLOFF_MBIST_DRF_FAIL(x, v) \ + (BIT_CLEAR_WLOFF_MBIST_DRF_FAIL(x) | BIT_WLOFF_MBIST_DRF_FAIL(v)) + +#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1 11 +#define BIT_MASK_PCIE_MBIST_DRF_FAIL_V1 0x1f +#define BIT_PCIE_MBIST_DRF_FAIL_V1(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_V1) \ + << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1) +#define BITS_PCIE_MBIST_DRF_FAIL_V1 \ + (BIT_MASK_PCIE_MBIST_DRF_FAIL_V1 << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1) +#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_V1(x) \ + ((x) & (~BITS_PCIE_MBIST_DRF_FAIL_V1)) +#define BIT_GET_PCIE_MBIST_DRF_FAIL_V1(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_V1) & \ + BIT_MASK_PCIE_MBIST_DRF_FAIL_V1) +#define BIT_SET_PCIE_MBIST_DRF_FAIL_V1(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DRF_FAIL_V1(x) | BIT_PCIE_MBIST_DRF_FAIL_V1(v)) + +#define BIT_SHIFT_USB_MBIST_DRF_FAIL_V1 4 +#define BIT_MASK_USB_MBIST_DRF_FAIL_V1 0x7f +#define BIT_USB_MBIST_DRF_FAIL_V1(x) \ + (((x) & BIT_MASK_USB_MBIST_DRF_FAIL_V1) \ + << BIT_SHIFT_USB_MBIST_DRF_FAIL_V1) +#define BITS_USB_MBIST_DRF_FAIL_V1 \ + (BIT_MASK_USB_MBIST_DRF_FAIL_V1 << BIT_SHIFT_USB_MBIST_DRF_FAIL_V1) +#define BIT_CLEAR_USB_MBIST_DRF_FAIL_V1(x) ((x) & (~BITS_USB_MBIST_DRF_FAIL_V1)) +#define BIT_GET_USB_MBIST_DRF_FAIL_V1(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_V1) & \ + BIT_MASK_USB_MBIST_DRF_FAIL_V1) +#define BIT_SET_USB_MBIST_DRF_FAIL_V1(x, v) \ + (BIT_CLEAR_USB_MBIST_DRF_FAIL_V1(x) | BIT_USB_MBIST_DRF_FAIL_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CHECK_OFFSET 0 -#define BIT_MASK_CHECK_OFFSET 0xff -#define BIT_CHECK_OFFSET(x) (((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET) -#define BIT_GET_CHECK_OFFSET(x) (((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET) +/* 2 REG_MBIST_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_MAC_MBIST_FAIL 0 +#define BIT_MASK_MAC_MBIST_FAIL 0xfff +#define BIT_MAC_MBIST_FAIL(x) \ + (((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL) +#define BITS_MAC_MBIST_FAIL \ + (BIT_MASK_MAC_MBIST_FAIL << BIT_SHIFT_MAC_MBIST_FAIL) +#define BIT_CLEAR_MAC_MBIST_FAIL(x) ((x) & (~BITS_MAC_MBIST_FAIL)) +#define BIT_GET_MAC_MBIST_FAIL(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL) +#define BIT_SET_MAC_MBIST_FAIL(x, v) \ + (BIT_CLEAR_MAC_MBIST_FAIL(x) | BIT_MAC_MBIST_FAIL(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - - -/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ -#define BIT_TXPKTBUF_REQ_ERR BIT(18) +#define BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL 0 +#define BIT_MASK_USB_WLON_MBIST_DRF_FAIL 0xf +#define BIT_USB_WLON_MBIST_DRF_FAIL(x) \ + (((x) & BIT_MASK_USB_WLON_MBIST_DRF_FAIL) \ + << BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL) +#define BITS_USB_WLON_MBIST_DRF_FAIL \ + (BIT_MASK_USB_WLON_MBIST_DRF_FAIL << BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL) +#define BIT_CLEAR_USB_WLON_MBIST_DRF_FAIL(x) \ + ((x) & (~BITS_USB_WLON_MBIST_DRF_FAIL)) +#define BIT_GET_USB_WLON_MBIST_DRF_FAIL(x) \ + (((x) >> BIT_SHIFT_USB_WLON_MBIST_DRF_FAIL) & \ + BIT_MASK_USB_WLON_MBIST_DRF_FAIL) +#define BIT_SET_USB_WLON_MBIST_DRF_FAIL(x, v) \ + (BIT_CLEAR_USB_WLON_MBIST_DRF_FAIL(x) | BIT_USB_WLON_MBIST_DRF_FAIL(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +/* 2 REG_MBIST_FAIL (Offset 0x0170) */ -#define BIT_HI_OQT_UDN BIT(17) -#define BIT_HI_OQT_OVF BIT(16) -#define BIT_PAYLOAD_CHKSUM_ERR BIT(15) -#define BIT_PAYLOAD_UDN BIT(14) -#define BIT_PAYLOAD_OVF BIT(13) -#define BIT_DSC_CHKSUM_FAIL BIT(12) -#define BIT_UNKNOWN_QSEL BIT(11) -#define BIT_EP_QSEL_DIFF BIT(10) -#define BIT_TX_OFFS_UNMATCH BIT(9) -#define BIT_TXOQT_UDN BIT(8) -#define BIT_TXOQT_OVF BIT(7) -#define BIT_TXDMA_SFF_UDN BIT(6) -#define BIT_TXDMA_SFF_OVF BIT(5) -#define BIT_LLT_NULL_PG BIT(4) -#define BIT_PAGE_UDN BIT(3) -#define BIT_PAGE_OVF BIT(2) -#define BIT_TXFF_PG_UDN BIT(1) -#define BIT_TXFF_PG_OVF BIT(0) +#define BIT_SHIFT_MAC_MBIST_FAIL_DRF 0 +#define BIT_MASK_MAC_MBIST_FAIL_DRF 0x3ffff +#define BIT_MAC_MBIST_FAIL_DRF(x) \ + (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF) << BIT_SHIFT_MAC_MBIST_FAIL_DRF) +#define BITS_MAC_MBIST_FAIL_DRF \ + (BIT_MASK_MAC_MBIST_FAIL_DRF << BIT_SHIFT_MAC_MBIST_FAIL_DRF) +#define BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) ((x) & (~BITS_MAC_MBIST_FAIL_DRF)) +#define BIT_GET_MAC_MBIST_FAIL_DRF(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF) & BIT_MASK_MAC_MBIST_FAIL_DRF) +#define BIT_SET_MAC_MBIST_FAIL_DRF(x, v) \ + (BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) | BIT_MAC_MBIST_FAIL_DRF(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */ +#define BIT_SHIFT_MAC_MBIST_DRF_FAIL 0 +#define BIT_MASK_MAC_MBIST_DRF_FAIL 0x3ffff +#define BIT_MAC_MBIST_DRF_FAIL(x) \ + (((x) & BIT_MASK_MAC_MBIST_DRF_FAIL) << BIT_SHIFT_MAC_MBIST_DRF_FAIL) +#define BITS_MAC_MBIST_DRF_FAIL \ + (BIT_MASK_MAC_MBIST_DRF_FAIL << BIT_SHIFT_MAC_MBIST_DRF_FAIL) +#define BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) ((x) & (~BITS_MAC_MBIST_DRF_FAIL)) +#define BIT_GET_MAC_MBIST_DRF_FAIL(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL) & BIT_MASK_MAC_MBIST_DRF_FAIL) +#define BIT_SET_MAC_MBIST_DRF_FAIL(x, v) \ + (BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) | BIT_MAC_MBIST_DRF_FAIL(v)) -/* 2 REG_RQPN_NPQ (Offset 0x0214) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_EXQ_AVAL_PG 24 -#define BIT_MASK_EXQ_AVAL_PG 0xff -#define BIT_EXQ_AVAL_PG(x) (((x) & BIT_MASK_EXQ_AVAL_PG) << BIT_SHIFT_EXQ_AVAL_PG) -#define BIT_GET_EXQ_AVAL_PG(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG) & BIT_MASK_EXQ_AVAL_PG) +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_8051_MBIST_START_PAUSE 26 +#define BIT_MASK_8051_MBIST_START_PAUSE 0x7 +#define BIT_8051_MBIST_START_PAUSE(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE) +#define BITS_8051_MBIST_START_PAUSE \ + (BIT_MASK_8051_MBIST_START_PAUSE << BIT_SHIFT_8051_MBIST_START_PAUSE) +#define BIT_CLEAR_8051_MBIST_START_PAUSE(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE)) +#define BIT_GET_8051_MBIST_START_PAUSE(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) & \ + BIT_MASK_8051_MBIST_START_PAUSE) +#define BIT_SET_8051_MBIST_START_PAUSE(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE(x) | BIT_8051_MBIST_START_PAUSE(v)) -#define BIT_SHIFT_EXQ 16 -#define BIT_MASK_EXQ 0xff -#define BIT_EXQ(x) (((x) & BIT_MASK_EXQ) << BIT_SHIFT_EXQ) -#define BIT_GET_EXQ(x) (((x) >> BIT_SHIFT_EXQ) & BIT_MASK_EXQ) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NPQ 0 -#define BIT_MASK_NPQ 0xff -#define BIT_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ) -#define BIT_GET_NPQ(x) (((x) >> BIT_SHIFT_NPQ) & BIT_MASK_NPQ) +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1 26 +#define BIT_MASK_8051_MBIST_START_PAUSE_V1 0x3f +#define BIT_8051_MBIST_START_PAUSE_V1(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1) +#define BITS_8051_MBIST_START_PAUSE_V1 \ + (BIT_MASK_8051_MBIST_START_PAUSE_V1 \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1) +#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE_V1)) +#define BIT_GET_8051_MBIST_START_PAUSE_V1(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1) & \ + BIT_MASK_8051_MBIST_START_PAUSE_V1) +#define BIT_SET_8051_MBIST_START_PAUSE_V1(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x) | \ + BIT_8051_MBIST_START_PAUSE_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_TQPNT1 (Offset 0x0218) */ +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_USB_MBIST_START_PAUSE 24 +#define BIT_MASK_USB_MBIST_START_PAUSE 0x3 +#define BIT_USB_MBIST_START_PAUSE(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE) +#define BITS_USB_MBIST_START_PAUSE \ + (BIT_MASK_USB_MBIST_START_PAUSE << BIT_SHIFT_USB_MBIST_START_PAUSE) +#define BIT_CLEAR_USB_MBIST_START_PAUSE(x) ((x) & (~BITS_USB_MBIST_START_PAUSE)) +#define BIT_GET_USB_MBIST_START_PAUSE(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) & \ + BIT_MASK_USB_MBIST_START_PAUSE) +#define BIT_SET_USB_MBIST_START_PAUSE(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE(x) | BIT_USB_MBIST_START_PAUSE(v)) -#define BIT_SHIFT_NPQ_HIGH_TH 24 -#define BIT_MASK_NPQ_HIGH_TH 0xff -#define BIT_NPQ_HIGH_TH(x) (((x) & BIT_MASK_NPQ_HIGH_TH) << BIT_SHIFT_NPQ_HIGH_TH) -#define BIT_GET_NPQ_HIGH_TH(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH) & BIT_MASK_NPQ_HIGH_TH) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NPQ_LOW_TH 16 -#define BIT_MASK_NPQ_LOW_TH 0xff -#define BIT_NPQ_LOW_TH(x) (((x) & BIT_MASK_NPQ_LOW_TH) << BIT_SHIFT_NPQ_LOW_TH) -#define BIT_GET_NPQ_LOW_TH(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH) & BIT_MASK_NPQ_LOW_TH) +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1 24 +#define BIT_MASK_USB_MBIST_START_PAUSE_V1 0x3 +#define BIT_USB_MBIST_START_PAUSE_V1(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1) +#define BITS_USB_MBIST_START_PAUSE_V1 \ + (BIT_MASK_USB_MBIST_START_PAUSE_V1 \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x) \ + ((x) & (~BITS_USB_MBIST_START_PAUSE_V1)) +#define BIT_GET_USB_MBIST_START_PAUSE_V1(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1) & \ + BIT_MASK_USB_MBIST_START_PAUSE_V1) +#define BIT_SET_USB_MBIST_START_PAUSE_V1(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x) | \ + BIT_USB_MBIST_START_PAUSE_V1(v)) + +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1 18 +#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1 0x3f +#define BIT_PCIE_MBIST_START_PAUSE_V1(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) +#define BITS_PCIE_MBIST_START_PAUSE_V1 \ + (BIT_MASK_PCIE_MBIST_START_PAUSE_V1 \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_V1(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE_V1) +#define BIT_SET_PCIE_MBIST_START_PAUSE_V1(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x) | \ + BIT_PCIE_MBIST_START_PAUSE_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16 +#define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f +#define BIT_PCIE_MBIST_START_PAUSE(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE) +#define BITS_PCIE_MBIST_START_PAUSE \ + (BIT_MASK_PCIE_MBIST_START_PAUSE << BIT_SHIFT_PCIE_MBIST_START_PAUSE) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE)) +#define BIT_GET_PCIE_MBIST_START_PAUSE(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE) +#define BIT_SET_PCIE_MBIST_START_PAUSE(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE(x) | BIT_PCIE_MBIST_START_PAUSE(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_TQPNT1 (Offset 0x0218) */ +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_WLON_MBIST_START_PAUSE_V1 9 +#define BIT_MASK_WLON_MBIST_START_PAUSE_V1 0x3 +#define BIT_WLON_MBIST_START_PAUSE_V1(x) \ + (((x) & BIT_MASK_WLON_MBIST_START_PAUSE_V1) \ + << BIT_SHIFT_WLON_MBIST_START_PAUSE_V1) +#define BITS_WLON_MBIST_START_PAUSE_V1 \ + (BIT_MASK_WLON_MBIST_START_PAUSE_V1 \ + << BIT_SHIFT_WLON_MBIST_START_PAUSE_V1) +#define BIT_CLEAR_WLON_MBIST_START_PAUSE_V1(x) \ + ((x) & (~BITS_WLON_MBIST_START_PAUSE_V1)) +#define BIT_GET_WLON_MBIST_START_PAUSE_V1(x) \ + (((x) >> BIT_SHIFT_WLON_MBIST_START_PAUSE_V1) & \ + BIT_MASK_WLON_MBIST_START_PAUSE_V1) +#define BIT_SET_WLON_MBIST_START_PAUSE_V1(x, v) \ + (BIT_CLEAR_WLON_MBIST_START_PAUSE_V1(x) | \ + BIT_WLON_MBIST_START_PAUSE_V1(v)) + +#define BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1 4 +#define BIT_MASK_WLOFF_MBIST_START_PAUSE_V1 0x1f +#define BIT_WLOFF_MBIST_START_PAUSE_V1(x) \ + (((x) & BIT_MASK_WLOFF_MBIST_START_PAUSE_V1) \ + << BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1) +#define BITS_WLOFF_MBIST_START_PAUSE_V1 \ + (BIT_MASK_WLOFF_MBIST_START_PAUSE_V1 \ + << BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1) +#define BIT_CLEAR_WLOFF_MBIST_START_PAUSE_V1(x) \ + ((x) & (~BITS_WLOFF_MBIST_START_PAUSE_V1)) +#define BIT_GET_WLOFF_MBIST_START_PAUSE_V1(x) \ + (((x) >> BIT_SHIFT_WLOFF_MBIST_START_PAUSE_V1) & \ + BIT_MASK_WLOFF_MBIST_START_PAUSE_V1) +#define BIT_SET_WLOFF_MBIST_START_PAUSE_V1(x, v) \ + (BIT_CLEAR_WLOFF_MBIST_START_PAUSE_V1(x) | \ + BIT_WLOFF_MBIST_START_PAUSE_V1(v)) + +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2 2 +#define BIT_MASK_PCIE_MBIST_START_PAUSE_V2 0x3 +#define BIT_PCIE_MBIST_START_PAUSE_V2(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V2) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2) +#define BITS_PCIE_MBIST_START_PAUSE_V2 \ + (BIT_MASK_PCIE_MBIST_START_PAUSE_V2 \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V2(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE_V2)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_V2(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V2) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE_V2) +#define BIT_SET_PCIE_MBIST_START_PAUSE_V2(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE_V2(x) | \ + BIT_PCIE_MBIST_START_PAUSE_V2(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HPQ_HIGH_TH_V1 16 -#define BIT_MASK_HPQ_HIGH_TH_V1 0xfff -#define BIT_HPQ_HIGH_TH_V1(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1) -#define BIT_GET_HPQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1) +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_MAC_MBIST_START_PAUSE 0 +#define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff +#define BIT_MAC_MBIST_START_PAUSE(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE) +#define BITS_MAC_MBIST_START_PAUSE \ + (BIT_MASK_MAC_MBIST_START_PAUSE << BIT_SHIFT_MAC_MBIST_START_PAUSE) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE(x) ((x) & (~BITS_MAC_MBIST_START_PAUSE)) +#define BIT_GET_MAC_MBIST_START_PAUSE(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) & \ + BIT_MASK_MAC_MBIST_START_PAUSE) +#define BIT_SET_MAC_MBIST_START_PAUSE(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE(x) | BIT_MAC_MBIST_START_PAUSE(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_USB_MBIST_START_PAUSE_V2 0 +#define BIT_MASK_USB_MBIST_START_PAUSE_V2 0x3 +#define BIT_USB_MBIST_START_PAUSE_V2(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE_V2) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V2) +#define BITS_USB_MBIST_START_PAUSE_V2 \ + (BIT_MASK_USB_MBIST_START_PAUSE_V2 \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V2) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_V2(x) \ + ((x) & (~BITS_USB_MBIST_START_PAUSE_V2)) +#define BIT_GET_USB_MBIST_START_PAUSE_V2(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V2) & \ + BIT_MASK_USB_MBIST_START_PAUSE_V2) +#define BIT_SET_USB_MBIST_START_PAUSE_V2(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE_V2(x) | \ + BIT_USB_MBIST_START_PAUSE_V2(v)) -/* 2 REG_TQPNT1 (Offset 0x0218) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HPQ_HIGH_TH 8 -#define BIT_MASK_HPQ_HIGH_TH 0xff -#define BIT_HPQ_HIGH_TH(x) (((x) & BIT_MASK_HPQ_HIGH_TH) << BIT_SHIFT_HPQ_HIGH_TH) -#define BIT_GET_HPQ_HIGH_TH(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH) & BIT_MASK_HPQ_HIGH_TH) +/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ +#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1 0 +#define BIT_MASK_MAC_MBIST_START_PAUSE_V1 0x3ffff +#define BIT_MAC_MBIST_START_PAUSE_V1(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) +#define BITS_MAC_MBIST_START_PAUSE_V1 \ + (BIT_MASK_MAC_MBIST_START_PAUSE_V1 \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x) \ + ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1)) +#define BIT_GET_MAC_MBIST_START_PAUSE_V1(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) & \ + BIT_MASK_MAC_MBIST_START_PAUSE_V1) +#define BIT_SET_MAC_MBIST_START_PAUSE_V1(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x) | \ + BIT_MAC_MBIST_START_PAUSE_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HPQ_LOW_TH 0 -#define BIT_MASK_HPQ_LOW_TH 0xff -#define BIT_HPQ_LOW_TH(x) (((x) & BIT_MASK_HPQ_LOW_TH) << BIT_SHIFT_HPQ_LOW_TH) -#define BIT_GET_HPQ_LOW_TH(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH) & BIT_MASK_HPQ_LOW_TH) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_8051_MBIST_DONE 26 +#define BIT_MASK_8051_MBIST_DONE 0x7 +#define BIT_8051_MBIST_DONE(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE) +#define BITS_8051_MBIST_DONE \ + (BIT_MASK_8051_MBIST_DONE << BIT_SHIFT_8051_MBIST_DONE) +#define BIT_CLEAR_8051_MBIST_DONE(x) ((x) & (~BITS_8051_MBIST_DONE)) +#define BIT_GET_8051_MBIST_DONE(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE) +#define BIT_SET_8051_MBIST_DONE(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE(x) | BIT_8051_MBIST_DONE(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_8051_MBIST_DONE_V1 26 +#define BIT_MASK_8051_MBIST_DONE_V1 0x3f +#define BIT_8051_MBIST_DONE_V1(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE_V1) << BIT_SHIFT_8051_MBIST_DONE_V1) +#define BITS_8051_MBIST_DONE_V1 \ + (BIT_MASK_8051_MBIST_DONE_V1 << BIT_SHIFT_8051_MBIST_DONE_V1) +#define BIT_CLEAR_8051_MBIST_DONE_V1(x) ((x) & (~BITS_8051_MBIST_DONE_V1)) +#define BIT_GET_8051_MBIST_DONE_V1(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE_V1) & BIT_MASK_8051_MBIST_DONE_V1) +#define BIT_SET_8051_MBIST_DONE_V1(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE_V1(x) | BIT_8051_MBIST_DONE_V1(v)) -/* 2 REG_TQPNT1 (Offset 0x0218) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HPQ_LOW_TH_V1 0 -#define BIT_MASK_HPQ_LOW_TH_V1 0xfff -#define BIT_HPQ_LOW_TH_V1(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1) -#define BIT_GET_HPQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_USB_MBIST_DONE 24 +#define BIT_MASK_USB_MBIST_DONE 0x3 +#define BIT_USB_MBIST_DONE(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE) +#define BITS_USB_MBIST_DONE \ + (BIT_MASK_USB_MBIST_DONE << BIT_SHIFT_USB_MBIST_DONE) +#define BIT_CLEAR_USB_MBIST_DONE(x) ((x) & (~BITS_USB_MBIST_DONE)) +#define BIT_GET_USB_MBIST_DONE(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE) +#define BIT_SET_USB_MBIST_DONE(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE(x) | BIT_USB_MBIST_DONE(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_USB_MBIST_DONE_V1 24 +#define BIT_MASK_USB_MBIST_DONE_V1 0x3 +#define BIT_USB_MBIST_DONE_V1(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE_V1) << BIT_SHIFT_USB_MBIST_DONE_V1) +#define BITS_USB_MBIST_DONE_V1 \ + (BIT_MASK_USB_MBIST_DONE_V1 << BIT_SHIFT_USB_MBIST_DONE_V1) +#define BIT_CLEAR_USB_MBIST_DONE_V1(x) ((x) & (~BITS_USB_MBIST_DONE_V1)) +#define BIT_GET_USB_MBIST_DONE_V1(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE_V1) & BIT_MASK_USB_MBIST_DONE_V1) +#define BIT_SET_USB_MBIST_DONE_V1(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE_V1(x) | BIT_USB_MBIST_DONE_V1(v)) + +#define BIT_SHIFT_PCIE_MBIST_DONE_V1 18 +#define BIT_MASK_PCIE_MBIST_DONE_V1 0x3f +#define BIT_PCIE_MBIST_DONE_V1(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE_V1) << BIT_SHIFT_PCIE_MBIST_DONE_V1) +#define BITS_PCIE_MBIST_DONE_V1 \ + (BIT_MASK_PCIE_MBIST_DONE_V1 << BIT_SHIFT_PCIE_MBIST_DONE_V1) +#define BIT_CLEAR_PCIE_MBIST_DONE_V1(x) ((x) & (~BITS_PCIE_MBIST_DONE_V1)) +#define BIT_GET_PCIE_MBIST_DONE_V1(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1) & BIT_MASK_PCIE_MBIST_DONE_V1) +#define BIT_SET_PCIE_MBIST_DONE_V1(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE_V1(x) | BIT_PCIE_MBIST_DONE_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_TQPNT2 (Offset 0x021C) */ +/* 2 REG_MBIST_DONE (Offset 0x0178) */ + +#define BIT_SHIFT_PCIE_MBIST_DONE 16 +#define BIT_MASK_PCIE_MBIST_DONE 0x3f +#define BIT_PCIE_MBIST_DONE(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE) +#define BITS_PCIE_MBIST_DONE \ + (BIT_MASK_PCIE_MBIST_DONE << BIT_SHIFT_PCIE_MBIST_DONE) +#define BIT_CLEAR_PCIE_MBIST_DONE(x) ((x) & (~BITS_PCIE_MBIST_DONE)) +#define BIT_GET_PCIE_MBIST_DONE(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE) +#define BIT_SET_PCIE_MBIST_DONE(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE(x) | BIT_PCIE_MBIST_DONE(v)) + +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_EXQ_HIGH_TH 24 -#define BIT_MASK_EXQ_HIGH_TH 0xff -#define BIT_EXQ_HIGH_TH(x) (((x) & BIT_MASK_EXQ_HIGH_TH) << BIT_SHIFT_EXQ_HIGH_TH) -#define BIT_GET_EXQ_HIGH_TH(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH) & BIT_MASK_EXQ_HIGH_TH) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_WLON_MBIST_DONE_V1 9 +#define BIT_MASK_WLON_MBIST_DONE_V1 0x3 +#define BIT_WLON_MBIST_DONE_V1(x) \ + (((x) & BIT_MASK_WLON_MBIST_DONE_V1) << BIT_SHIFT_WLON_MBIST_DONE_V1) +#define BITS_WLON_MBIST_DONE_V1 \ + (BIT_MASK_WLON_MBIST_DONE_V1 << BIT_SHIFT_WLON_MBIST_DONE_V1) +#define BIT_CLEAR_WLON_MBIST_DONE_V1(x) ((x) & (~BITS_WLON_MBIST_DONE_V1)) +#define BIT_GET_WLON_MBIST_DONE_V1(x) \ + (((x) >> BIT_SHIFT_WLON_MBIST_DONE_V1) & BIT_MASK_WLON_MBIST_DONE_V1) +#define BIT_SET_WLON_MBIST_DONE_V1(x, v) \ + (BIT_CLEAR_WLON_MBIST_DONE_V1(x) | BIT_WLON_MBIST_DONE_V1(v)) + +#define BIT_SHIFT_WLOFF_MBIST_DONE_V1 4 +#define BIT_MASK_WLOFF_MBIST_DONE_V1 0x1f +#define BIT_WLOFF_MBIST_DONE_V1(x) \ + (((x) & BIT_MASK_WLOFF_MBIST_DONE_V1) << BIT_SHIFT_WLOFF_MBIST_DONE_V1) +#define BITS_WLOFF_MBIST_DONE_V1 \ + (BIT_MASK_WLOFF_MBIST_DONE_V1 << BIT_SHIFT_WLOFF_MBIST_DONE_V1) +#define BIT_CLEAR_WLOFF_MBIST_DONE_V1(x) ((x) & (~BITS_WLOFF_MBIST_DONE_V1)) +#define BIT_GET_WLOFF_MBIST_DONE_V1(x) \ + (((x) >> BIT_SHIFT_WLOFF_MBIST_DONE_V1) & BIT_MASK_WLOFF_MBIST_DONE_V1) +#define BIT_SET_WLOFF_MBIST_DONE_V1(x, v) \ + (BIT_CLEAR_WLOFF_MBIST_DONE_V1(x) | BIT_WLOFF_MBIST_DONE_V1(v)) + +#define BIT_SHIFT_PCIE_MBIST_DONE_V2 2 +#define BIT_MASK_PCIE_MBIST_DONE_V2 0x3 +#define BIT_PCIE_MBIST_DONE_V2(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE_V2) << BIT_SHIFT_PCIE_MBIST_DONE_V2) +#define BITS_PCIE_MBIST_DONE_V2 \ + (BIT_MASK_PCIE_MBIST_DONE_V2 << BIT_SHIFT_PCIE_MBIST_DONE_V2) +#define BIT_CLEAR_PCIE_MBIST_DONE_V2(x) ((x) & (~BITS_PCIE_MBIST_DONE_V2)) +#define BIT_GET_PCIE_MBIST_DONE_V2(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V2) & BIT_MASK_PCIE_MBIST_DONE_V2) +#define BIT_SET_PCIE_MBIST_DONE_V2(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE_V2(x) | BIT_PCIE_MBIST_DONE_V2(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_EXQ_LOW_TH 16 -#define BIT_MASK_EXQ_LOW_TH 0xff -#define BIT_EXQ_LOW_TH(x) (((x) & BIT_MASK_EXQ_LOW_TH) << BIT_SHIFT_EXQ_LOW_TH) -#define BIT_GET_EXQ_LOW_TH(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH) & BIT_MASK_EXQ_LOW_TH) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_MAC_MBIST_DONE 0 +#define BIT_MASK_MAC_MBIST_DONE 0xfff +#define BIT_MAC_MBIST_DONE(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE) +#define BITS_MAC_MBIST_DONE \ + (BIT_MASK_MAC_MBIST_DONE << BIT_SHIFT_MAC_MBIST_DONE) +#define BIT_CLEAR_MAC_MBIST_DONE(x) ((x) & (~BITS_MAC_MBIST_DONE)) +#define BIT_GET_MAC_MBIST_DONE(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE) +#define BIT_SET_MAC_MBIST_DONE(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE(x) | BIT_MAC_MBIST_DONE(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_USB_MBIST_DONE_V2 0 +#define BIT_MASK_USB_MBIST_DONE_V2 0x3 +#define BIT_USB_MBIST_DONE_V2(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE_V2) << BIT_SHIFT_USB_MBIST_DONE_V2) +#define BITS_USB_MBIST_DONE_V2 \ + (BIT_MASK_USB_MBIST_DONE_V2 << BIT_SHIFT_USB_MBIST_DONE_V2) +#define BIT_CLEAR_USB_MBIST_DONE_V2(x) ((x) & (~BITS_USB_MBIST_DONE_V2)) +#define BIT_GET_USB_MBIST_DONE_V2(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE_V2) & BIT_MASK_USB_MBIST_DONE_V2) +#define BIT_SET_USB_MBIST_DONE_V2(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE_V2(x) | BIT_USB_MBIST_DONE_V2(v)) -/* 2 REG_TQPNT2 (Offset 0x021C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NPQ_HIGH_TH_V1 16 -#define BIT_MASK_NPQ_HIGH_TH_V1 0xfff -#define BIT_NPQ_HIGH_TH_V1(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1) -#define BIT_GET_NPQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1) +/* 2 REG_MBIST_DONE (Offset 0x0178) */ +#define BIT_SHIFT_MAC_MBIST_DONE_V1 0 +#define BIT_MASK_MAC_MBIST_DONE_V1 0x3ffff +#define BIT_MAC_MBIST_DONE_V1(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE_V1) << BIT_SHIFT_MAC_MBIST_DONE_V1) +#define BITS_MAC_MBIST_DONE_V1 \ + (BIT_MASK_MAC_MBIST_DONE_V1 << BIT_SHIFT_MAC_MBIST_DONE_V1) +#define BIT_CLEAR_MAC_MBIST_DONE_V1(x) ((x) & (~BITS_MAC_MBIST_DONE_V1)) +#define BIT_GET_MAC_MBIST_DONE_V1(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1) & BIT_MASK_MAC_MBIST_DONE_V1) +#define BIT_SET_MAC_MBIST_DONE_V1(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE_V1(x) | BIT_MAC_MBIST_DONE_V1(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_MBIST_NRML_FAIL (Offset 0x017C) */ + +#define BIT_SHIFT_WLON_MBIST_NRML_FAIL 30 +#define BIT_MASK_WLON_MBIST_NRML_FAIL 0x3 +#define BIT_WLON_MBIST_NRML_FAIL(x) \ + (((x) & BIT_MASK_WLON_MBIST_NRML_FAIL) \ + << BIT_SHIFT_WLON_MBIST_NRML_FAIL) +#define BITS_WLON_MBIST_NRML_FAIL \ + (BIT_MASK_WLON_MBIST_NRML_FAIL << BIT_SHIFT_WLON_MBIST_NRML_FAIL) +#define BIT_CLEAR_WLON_MBIST_NRML_FAIL(x) ((x) & (~BITS_WLON_MBIST_NRML_FAIL)) +#define BIT_GET_WLON_MBIST_NRML_FAIL(x) \ + (((x) >> BIT_SHIFT_WLON_MBIST_NRML_FAIL) & \ + BIT_MASK_WLON_MBIST_NRML_FAIL) +#define BIT_SET_WLON_MBIST_NRML_FAIL(x, v) \ + (BIT_CLEAR_WLON_MBIST_NRML_FAIL(x) | BIT_WLON_MBIST_NRML_FAIL(v)) + +#define BIT_SHIFT_WLOFF_MBIST_NRML_FAIL 16 +#define BIT_MASK_WLOFF_MBIST_NRML_FAIL 0x3fff +#define BIT_WLOFF_MBIST_NRML_FAIL(x) \ + (((x) & BIT_MASK_WLOFF_MBIST_NRML_FAIL) \ + << BIT_SHIFT_WLOFF_MBIST_NRML_FAIL) +#define BITS_WLOFF_MBIST_NRML_FAIL \ + (BIT_MASK_WLOFF_MBIST_NRML_FAIL << BIT_SHIFT_WLOFF_MBIST_NRML_FAIL) +#define BIT_CLEAR_WLOFF_MBIST_NRML_FAIL(x) ((x) & (~BITS_WLOFF_MBIST_NRML_FAIL)) +#define BIT_GET_WLOFF_MBIST_NRML_FAIL(x) \ + (((x) >> BIT_SHIFT_WLOFF_MBIST_NRML_FAIL) & \ + BIT_MASK_WLOFF_MBIST_NRML_FAIL) +#define BIT_SET_WLOFF_MBIST_NRML_FAIL(x, v) \ + (BIT_CLEAR_WLOFF_MBIST_NRML_FAIL(x) | BIT_WLOFF_MBIST_NRML_FAIL(v)) + +#define BIT_SHIFT_PCIE_MBIST_NRML_FAIL 11 +#define BIT_MASK_PCIE_MBIST_NRML_FAIL 0x1f +#define BIT_PCIE_MBIST_NRML_FAIL(x) \ + (((x) & BIT_MASK_PCIE_MBIST_NRML_FAIL) \ + << BIT_SHIFT_PCIE_MBIST_NRML_FAIL) +#define BITS_PCIE_MBIST_NRML_FAIL \ + (BIT_MASK_PCIE_MBIST_NRML_FAIL << BIT_SHIFT_PCIE_MBIST_NRML_FAIL) +#define BIT_CLEAR_PCIE_MBIST_NRML_FAIL(x) ((x) & (~BITS_PCIE_MBIST_NRML_FAIL)) +#define BIT_GET_PCIE_MBIST_NRML_FAIL(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_NRML_FAIL) & \ + BIT_MASK_PCIE_MBIST_NRML_FAIL) +#define BIT_SET_PCIE_MBIST_NRML_FAIL(x, v) \ + (BIT_CLEAR_PCIE_MBIST_NRML_FAIL(x) | BIT_PCIE_MBIST_NRML_FAIL(v)) + +#define BIT_SHIFT_USB_MBIST_NRML_FAIL 4 +#define BIT_MASK_USB_MBIST_NRML_FAIL 0x7f +#define BIT_USB_MBIST_NRML_FAIL(x) \ + (((x) & BIT_MASK_USB_MBIST_NRML_FAIL) << BIT_SHIFT_USB_MBIST_NRML_FAIL) +#define BITS_USB_MBIST_NRML_FAIL \ + (BIT_MASK_USB_MBIST_NRML_FAIL << BIT_SHIFT_USB_MBIST_NRML_FAIL) +#define BIT_CLEAR_USB_MBIST_NRML_FAIL(x) ((x) & (~BITS_USB_MBIST_NRML_FAIL)) +#define BIT_GET_USB_MBIST_NRML_FAIL(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_NRML_FAIL) & BIT_MASK_USB_MBIST_NRML_FAIL) +#define BIT_SET_USB_MBIST_NRML_FAIL(x, v) \ + (BIT_CLEAR_USB_MBIST_NRML_FAIL(x) | BIT_USB_MBIST_NRML_FAIL(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBIST_ROM_CRC_DATA (Offset 0x017C) */ -/* 2 REG_TQPNT2 (Offset 0x021C) */ - +#define BIT_SHIFT_MBIST_ROM_CRC_DATA 0 +#define BIT_MASK_MBIST_ROM_CRC_DATA 0xffffffffL +#define BIT_MBIST_ROM_CRC_DATA(x) \ + (((x) & BIT_MASK_MBIST_ROM_CRC_DATA) << BIT_SHIFT_MBIST_ROM_CRC_DATA) +#define BITS_MBIST_ROM_CRC_DATA \ + (BIT_MASK_MBIST_ROM_CRC_DATA << BIT_SHIFT_MBIST_ROM_CRC_DATA) +#define BIT_CLEAR_MBIST_ROM_CRC_DATA(x) ((x) & (~BITS_MBIST_ROM_CRC_DATA)) +#define BIT_GET_MBIST_ROM_CRC_DATA(x) \ + (((x) >> BIT_SHIFT_MBIST_ROM_CRC_DATA) & BIT_MASK_MBIST_ROM_CRC_DATA) +#define BIT_SET_MBIST_ROM_CRC_DATA(x, v) \ + (BIT_CLEAR_MBIST_ROM_CRC_DATA(x) | BIT_MBIST_ROM_CRC_DATA(v)) -#define BIT_SHIFT_LPQ_HIGH_TH 8 -#define BIT_MASK_LPQ_HIGH_TH 0xff -#define BIT_LPQ_HIGH_TH(x) (((x) & BIT_MASK_LPQ_HIGH_TH) << BIT_SHIFT_LPQ_HIGH_TH) -#define BIT_GET_LPQ_HIGH_TH(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH) & BIT_MASK_LPQ_HIGH_TH) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_LPQ_LOW_TH 0 -#define BIT_MASK_LPQ_LOW_TH 0xff -#define BIT_LPQ_LOW_TH(x) (((x) & BIT_MASK_LPQ_LOW_TH) << BIT_SHIFT_LPQ_LOW_TH) -#define BIT_GET_LPQ_LOW_TH(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH) & BIT_MASK_LPQ_LOW_TH) +/* 2 REG_MBIST_NRML_FAIL (Offset 0x017C) */ +#define BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL 0 +#define BIT_MASK_USB_WLON_MBIST_NRML_FAIL 0xf +#define BIT_USB_WLON_MBIST_NRML_FAIL(x) \ + (((x) & BIT_MASK_USB_WLON_MBIST_NRML_FAIL) \ + << BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL) +#define BITS_USB_WLON_MBIST_NRML_FAIL \ + (BIT_MASK_USB_WLON_MBIST_NRML_FAIL \ + << BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL) +#define BIT_CLEAR_USB_WLON_MBIST_NRML_FAIL(x) \ + ((x) & (~BITS_USB_WLON_MBIST_NRML_FAIL)) +#define BIT_GET_USB_WLON_MBIST_NRML_FAIL(x) \ + (((x) >> BIT_SHIFT_USB_WLON_MBIST_NRML_FAIL) & \ + BIT_MASK_USB_WLON_MBIST_NRML_FAIL) +#define BIT_SET_USB_WLON_MBIST_NRML_FAIL(x, v) \ + (BIT_CLEAR_USB_WLON_MBIST_NRML_FAIL(x) | \ + BIT_USB_WLON_MBIST_NRML_FAIL(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ +#define BIT_SHIFT_MBIST_FAIL_NRML_V1 0 +#define BIT_MASK_MBIST_FAIL_NRML_V1 0x3ffff +#define BIT_MBIST_FAIL_NRML_V1(x) \ + (((x) & BIT_MASK_MBIST_FAIL_NRML_V1) << BIT_SHIFT_MBIST_FAIL_NRML_V1) +#define BITS_MBIST_FAIL_NRML_V1 \ + (BIT_MASK_MBIST_FAIL_NRML_V1 << BIT_SHIFT_MBIST_FAIL_NRML_V1) +#define BIT_CLEAR_MBIST_FAIL_NRML_V1(x) ((x) & (~BITS_MBIST_FAIL_NRML_V1)) +#define BIT_GET_MBIST_FAIL_NRML_V1(x) \ + (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1) & BIT_MASK_MBIST_FAIL_NRML_V1) +#define BIT_SET_MBIST_FAIL_NRML_V1(x, v) \ + (BIT_CLEAR_MBIST_FAIL_NRML_V1(x) | BIT_MBIST_FAIL_NRML_V1(v)) -/* 2 REG_TQPNT2 (Offset 0x021C) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_NPQ_LOW_TH_V1 0 -#define BIT_MASK_NPQ_LOW_TH_V1 0xfff -#define BIT_NPQ_LOW_TH_V1(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1) -#define BIT_GET_NPQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1) +/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ +#define BIT_SHIFT_MBIST_FAIL_NRML 0 +#define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL +#define BIT_MBIST_FAIL_NRML(x) \ + (((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML) +#define BITS_MBIST_FAIL_NRML \ + (BIT_MASK_MBIST_FAIL_NRML << BIT_SHIFT_MBIST_FAIL_NRML) +#define BIT_CLEAR_MBIST_FAIL_NRML(x) ((x) & (~BITS_MBIST_FAIL_NRML)) +#define BIT_GET_MBIST_FAIL_NRML(x) \ + (((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML) +#define BIT_SET_MBIST_FAIL_NRML(x, v) \ + (BIT_CLEAR_MBIST_FAIL_NRML(x) | BIT_MBIST_FAIL_NRML(v)) + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) +#define BITS_R_WMAC_IPV6_MYIPAD \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD) +#define BIT_SET_R_WMAC_IPV6_MYIPAD(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) | BIT_R_WMAC_IPV6_MYIPAD(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_TQPNT3 (Offset 0x0220) */ +/* 2 REG_AES_DECRPT_DATA (Offset 0x0180) */ +#define BIT_SHIFT_IPS_CFG_ADDR 0 +#define BIT_MASK_IPS_CFG_ADDR 0xff +#define BIT_IPS_CFG_ADDR(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR) +#define BITS_IPS_CFG_ADDR (BIT_MASK_IPS_CFG_ADDR << BIT_SHIFT_IPS_CFG_ADDR) +#define BIT_CLEAR_IPS_CFG_ADDR(x) ((x) & (~BITS_IPS_CFG_ADDR)) +#define BIT_GET_IPS_CFG_ADDR(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR) +#define BIT_SET_IPS_CFG_ADDR(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR(x) | BIT_IPS_CFG_ADDR(v)) -#define BIT_SHIFT_LPQ_HIGH_TH_V1 16 -#define BIT_MASK_LPQ_HIGH_TH_V1 0xfff -#define BIT_LPQ_HIGH_TH_V1(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1) -#define BIT_GET_LPQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1) +/* 2 REG_AES_DECRPT_CFG (Offset 0x0184) */ +#define BIT_SHIFT_IPS_CFG_DATA 0 +#define BIT_MASK_IPS_CFG_DATA 0xffffffffL +#define BIT_IPS_CFG_DATA(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA) +#define BITS_IPS_CFG_DATA (BIT_MASK_IPS_CFG_DATA << BIT_SHIFT_IPS_CFG_DATA) +#define BIT_CLEAR_IPS_CFG_DATA(x) ((x) & (~BITS_IPS_CFG_DATA)) +#define BIT_GET_IPS_CFG_DATA(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA) +#define BIT_SET_IPS_CFG_DATA(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA(x) | BIT_IPS_CFG_DATA(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_HIOE_CTRL (Offset 0x0188) */ -/* 2 REG_TDE_DEBUG (Offset 0x0220) */ +#define BIT_HIOE_CFG_FILE_LOC_SEL BIT(31) +#endif -#define BIT_SHIFT_TDE_DEBUG 0 -#define BIT_MASK_TDE_DEBUG 0xffffffffL -#define BIT_TDE_DEBUG(x) (((x) & BIT_MASK_TDE_DEBUG) << BIT_SHIFT_TDE_DEBUG) -#define BIT_GET_TDE_DEBUG(x) (((x) >> BIT_SHIFT_TDE_DEBUG) & BIT_MASK_TDE_DEBUG) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_HIOE_CTRL (Offset 0x0188) */ -#endif +#define BIT_HIOE_WRITE_REQ BIT(30) +#define BIT_HIOE_READ_REQ BIT(29) +#define BIT_INST_FORMAT_ERR BIT(25) +#define BIT_OP_TIMEOUT_ERR BIT(24) +#define BIT_SHIFT_HIOE_OP_TIMEOUT 16 +#define BIT_MASK_HIOE_OP_TIMEOUT 0xff +#define BIT_HIOE_OP_TIMEOUT(x) \ + (((x) & BIT_MASK_HIOE_OP_TIMEOUT) << BIT_SHIFT_HIOE_OP_TIMEOUT) +#define BITS_HIOE_OP_TIMEOUT \ + (BIT_MASK_HIOE_OP_TIMEOUT << BIT_SHIFT_HIOE_OP_TIMEOUT) +#define BIT_CLEAR_HIOE_OP_TIMEOUT(x) ((x) & (~BITS_HIOE_OP_TIMEOUT)) +#define BIT_GET_HIOE_OP_TIMEOUT(x) \ + (((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT) & BIT_MASK_HIOE_OP_TIMEOUT) +#define BIT_SET_HIOE_OP_TIMEOUT(x, v) \ + (BIT_CLEAR_HIOE_OP_TIMEOUT(x) | BIT_HIOE_OP_TIMEOUT(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_TQPNT3 (Offset 0x0220) */ +/* 2 REG_MBIST_READ_BIST_RPT_V1 (Offset 0x0188) */ +#define BIT_SHIFT_MBIST_READ_BIST_RPT 0 +#define BIT_MASK_MBIST_READ_BIST_RPT 0xffffffffL +#define BIT_MBIST_READ_BIST_RPT(x) \ + (((x) & BIT_MASK_MBIST_READ_BIST_RPT) << BIT_SHIFT_MBIST_READ_BIST_RPT) +#define BITS_MBIST_READ_BIST_RPT \ + (BIT_MASK_MBIST_READ_BIST_RPT << BIT_SHIFT_MBIST_READ_BIST_RPT) +#define BIT_CLEAR_MBIST_READ_BIST_RPT(x) ((x) & (~BITS_MBIST_READ_BIST_RPT)) +#define BIT_GET_MBIST_READ_BIST_RPT(x) \ + (((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT) & BIT_MASK_MBIST_READ_BIST_RPT) +#define BIT_SET_MBIST_READ_BIST_RPT(x, v) \ + (BIT_CLEAR_MBIST_READ_BIST_RPT(x) | BIT_MBIST_READ_BIST_RPT(v)) -#define BIT_SHIFT_LPQ_LOW_TH_V1 0 -#define BIT_MASK_LPQ_LOW_TH_V1 0xfff -#define BIT_LPQ_LOW_TH_V1(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1) -#define BIT_GET_LPQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_HIOE_CTRL (Offset 0x0188) */ +#define BIT_SHIFT_BITDATA_CHECKSUM 0 +#define BIT_MASK_BITDATA_CHECKSUM 0xffff +#define BIT_BITDATA_CHECKSUM(x) \ + (((x) & BIT_MASK_BITDATA_CHECKSUM) << BIT_SHIFT_BITDATA_CHECKSUM) +#define BITS_BITDATA_CHECKSUM \ + (BIT_MASK_BITDATA_CHECKSUM << BIT_SHIFT_BITDATA_CHECKSUM) +#define BIT_CLEAR_BITDATA_CHECKSUM(x) ((x) & (~BITS_BITDATA_CHECKSUM)) +#define BIT_GET_BITDATA_CHECKSUM(x) \ + (((x) >> BIT_SHIFT_BITDATA_CHECKSUM) & BIT_MASK_BITDATA_CHECKSUM) +#define BIT_SET_BITDATA_CHECKSUM(x, v) \ + (BIT_CLEAR_BITDATA_CHECKSUM(x) | BIT_BITDATA_CHECKSUM(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIOE_CFG_FILE (Offset 0x018C) */ +#define BIT_SHIFT_TXBF_END_ADDR 16 +#define BIT_MASK_TXBF_END_ADDR 0xffff +#define BIT_TXBF_END_ADDR(x) \ + (((x) & BIT_MASK_TXBF_END_ADDR) << BIT_SHIFT_TXBF_END_ADDR) +#define BITS_TXBF_END_ADDR (BIT_MASK_TXBF_END_ADDR << BIT_SHIFT_TXBF_END_ADDR) +#define BIT_CLEAR_TXBF_END_ADDR(x) ((x) & (~BITS_TXBF_END_ADDR)) +#define BIT_GET_TXBF_END_ADDR(x) \ + (((x) >> BIT_SHIFT_TXBF_END_ADDR) & BIT_MASK_TXBF_END_ADDR) +#define BIT_SET_TXBF_END_ADDR(x, v) \ + (BIT_CLEAR_TXBF_END_ADDR(x) | BIT_TXBF_END_ADDR(v)) -/* 2 REG_AUTO_LLT (Offset 0x0224) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_TXPKTNUM_V1 24 -#define BIT_MASK_TXPKTNUM_V1 0xff -#define BIT_TXPKTNUM_V1(x) (((x) & BIT_MASK_TXPKTNUM_V1) << BIT_SHIFT_TXPKTNUM_V1) -#define BIT_GET_TXPKTNUM_V1(x) (((x) >> BIT_SHIFT_TXPKTNUM_V1) & BIT_MASK_TXPKTNUM_V1) +/* 2 REG_MACCLKFRQ (Offset 0x018C) */ -#define BIT_TDE_DBG_SEL BIT(23) -#define BIT_AUTO_INIT_LLT BIT(16) +#define BIT_SHIFT_MACCLK_FREQ_LOW32 0 +#define BIT_MASK_MACCLK_FREQ_LOW32 0xffffffffL +#define BIT_MACCLK_FREQ_LOW32(x) \ + (((x) & BIT_MASK_MACCLK_FREQ_LOW32) << BIT_SHIFT_MACCLK_FREQ_LOW32) +#define BITS_MACCLK_FREQ_LOW32 \ + (BIT_MASK_MACCLK_FREQ_LOW32 << BIT_SHIFT_MACCLK_FREQ_LOW32) +#define BIT_CLEAR_MACCLK_FREQ_LOW32(x) ((x) & (~BITS_MACCLK_FREQ_LOW32)) +#define BIT_GET_MACCLK_FREQ_LOW32(x) \ + (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32) & BIT_MASK_MACCLK_FREQ_LOW32) +#define BIT_SET_MACCLK_FREQ_LOW32(x, v) \ + (BIT_CLEAR_MACCLK_FREQ_LOW32(x) | BIT_MACCLK_FREQ_LOW32(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIOE_CFG_FILE (Offset 0x018C) */ +#define BIT_SHIFT_TXBF_STR_ADDR 0 +#define BIT_MASK_TXBF_STR_ADDR 0xffff +#define BIT_TXBF_STR_ADDR(x) \ + (((x) & BIT_MASK_TXBF_STR_ADDR) << BIT_SHIFT_TXBF_STR_ADDR) +#define BITS_TXBF_STR_ADDR (BIT_MASK_TXBF_STR_ADDR << BIT_SHIFT_TXBF_STR_ADDR) +#define BIT_CLEAR_TXBF_STR_ADDR(x) ((x) & (~BITS_TXBF_STR_ADDR)) +#define BIT_GET_TXBF_STR_ADDR(x) \ + (((x) >> BIT_SHIFT_TXBF_STR_ADDR) & BIT_MASK_TXBF_STR_ADDR) +#define BIT_SET_TXBF_STR_ADDR(x, v) \ + (BIT_CLEAR_TXBF_STR_ADDR(x) | BIT_TXBF_STR_ADDR(v)) -/* 2 REG_TQPNT4 (Offset 0x0224) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TMETER (Offset 0x0190) */ -#define BIT_SHIFT_EXQ_HIGH_TH_V1 16 -#define BIT_MASK_EXQ_HIGH_TH_V1 0xfff -#define BIT_EXQ_HIGH_TH_V1(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1) -#define BIT_GET_EXQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1) +#define BIT_TEMP_VALID BIT(31) +#define BIT_SHIFT_TEMP_VALUE 24 +#define BIT_MASK_TEMP_VALUE 0x3f +#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE) +#define BITS_TEMP_VALUE (BIT_MASK_TEMP_VALUE << BIT_SHIFT_TEMP_VALUE) +#define BIT_CLEAR_TEMP_VALUE(x) ((x) & (~BITS_TEMP_VALUE)) +#define BIT_GET_TEMP_VALUE(x) \ + (((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE) +#define BIT_SET_TEMP_VALUE(x, v) (BIT_CLEAR_TEMP_VALUE(x) | BIT_TEMP_VALUE(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TMETER (Offset 0x0190) */ +#define BIT_SHIFT_NCO_OUTCLK_FREQ 12 +#define BIT_MASK_NCO_OUTCLK_FREQ 0xfffff +#define BIT_NCO_OUTCLK_FREQ(x) \ + (((x) & BIT_MASK_NCO_OUTCLK_FREQ) << BIT_SHIFT_NCO_OUTCLK_FREQ) +#define BITS_NCO_OUTCLK_FREQ \ + (BIT_MASK_NCO_OUTCLK_FREQ << BIT_SHIFT_NCO_OUTCLK_FREQ) +#define BIT_CLEAR_NCO_OUTCLK_FREQ(x) ((x) & (~BITS_NCO_OUTCLK_FREQ)) +#define BIT_GET_NCO_OUTCLK_FREQ(x) \ + (((x) >> BIT_SHIFT_NCO_OUTCLK_FREQ) & BIT_MASK_NCO_OUTCLK_FREQ) +#define BIT_SET_NCO_OUTCLK_FREQ(x, v) \ + (BIT_CLEAR_NCO_OUTCLK_FREQ(x) | BIT_NCO_OUTCLK_FREQ(v)) -/* 2 REG_AUTO_LLT (Offset 0x0224) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE 8 -#define BIT_MASK_TX_OQT_HE_FREE_SPACE 0xff -#define BIT_TX_OQT_HE_FREE_SPACE(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE) -#define BIT_GET_TX_OQT_HE_FREE_SPACE(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE) & BIT_MASK_TX_OQT_HE_FREE_SPACE) +/* 2 REG_TMETER (Offset 0x0190) */ +#define BIT_SHIFT_REG_TMETER_TIMER 8 +#define BIT_MASK_REG_TMETER_TIMER 0xfff +#define BIT_REG_TMETER_TIMER(x) \ + (((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER) +#define BITS_REG_TMETER_TIMER \ + (BIT_MASK_REG_TMETER_TIMER << BIT_SHIFT_REG_TMETER_TIMER) +#define BIT_CLEAR_REG_TMETER_TIMER(x) ((x) & (~BITS_REG_TMETER_TIMER)) +#define BIT_GET_REG_TMETER_TIMER(x) \ + (((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER) +#define BIT_SET_REG_TMETER_TIMER(x, v) \ + (BIT_CLEAR_REG_TMETER_TIMER(x) | BIT_REG_TMETER_TIMER(v)) -#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE 0 -#define BIT_MASK_TX_OQT_NL_FREE_SPACE 0xff -#define BIT_TX_OQT_NL_FREE_SPACE(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE) -#define BIT_GET_TX_OQT_NL_FREE_SPACE(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE) & BIT_MASK_TX_OQT_NL_FREE_SPACE) +#define BIT_SHIFT_REG_TEMP_DELTA 2 +#define BIT_MASK_REG_TEMP_DELTA 0x3f +#define BIT_REG_TEMP_DELTA(x) \ + (((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA) +#define BITS_REG_TEMP_DELTA \ + (BIT_MASK_REG_TEMP_DELTA << BIT_SHIFT_REG_TEMP_DELTA) +#define BIT_CLEAR_REG_TEMP_DELTA(x) ((x) & (~BITS_REG_TEMP_DELTA)) +#define BIT_GET_REG_TEMP_DELTA(x) \ + (((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA) +#define BIT_SET_REG_TEMP_DELTA(x, v) \ + (BIT_CLEAR_REG_TEMP_DELTA(x) | BIT_REG_TEMP_DELTA(v)) +#define BIT_REG_TMETER_EN BIT(0) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TMETER (Offset 0x0190) */ +#define BIT_SHIFT_MACCLK_FREQ_HIGH10 0 +#define BIT_MASK_MACCLK_FREQ_HIGH10 0x3ff +#define BIT_MACCLK_FREQ_HIGH10(x) \ + (((x) & BIT_MASK_MACCLK_FREQ_HIGH10) << BIT_SHIFT_MACCLK_FREQ_HIGH10) +#define BITS_MACCLK_FREQ_HIGH10 \ + (BIT_MASK_MACCLK_FREQ_HIGH10 << BIT_SHIFT_MACCLK_FREQ_HIGH10) +#define BIT_CLEAR_MACCLK_FREQ_HIGH10(x) ((x) & (~BITS_MACCLK_FREQ_HIGH10)) +#define BIT_GET_MACCLK_FREQ_HIGH10(x) \ + (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10) & BIT_MASK_MACCLK_FREQ_HIGH10) +#define BIT_SET_MACCLK_FREQ_HIGH10(x, v) \ + (BIT_CLEAR_MACCLK_FREQ_HIGH10(x) | BIT_MACCLK_FREQ_HIGH10(v)) -/* 2 REG_TQPNT4 (Offset 0x0224) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_EXQ_LOW_TH_V1 0 -#define BIT_MASK_EXQ_LOW_TH_V1 0xfff -#define BIT_EXQ_LOW_TH_V1(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1) -#define BIT_GET_EXQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1) +/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#define BIT_SHIFT_OSC_32K_CLKGEN_0 16 +#define BIT_MASK_OSC_32K_CLKGEN_0 0xffff +#define BIT_OSC_32K_CLKGEN_0(x) \ + (((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0) +#define BITS_OSC_32K_CLKGEN_0 \ + (BIT_MASK_OSC_32K_CLKGEN_0 << BIT_SHIFT_OSC_32K_CLKGEN_0) +#define BIT_CLEAR_OSC_32K_CLKGEN_0(x) ((x) & (~BITS_OSC_32K_CLKGEN_0)) +#define BIT_GET_OSC_32K_CLKGEN_0(x) \ + (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0) +#define BIT_SET_OSC_32K_CLKGEN_0(x, v) \ + (BIT_CLEAR_OSC_32K_CLKGEN_0(x) | BIT_OSC_32K_CLKGEN_0(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#define BIT_32K_CLK_OUT_RDY BIT(12) -/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ +#define BIT_SHIFT_MONITOR_CYCLE_LOG2 8 +#define BIT_MASK_MONITOR_CYCLE_LOG2 0xf +#define BIT_MONITOR_CYCLE_LOG2(x) \ + (((x) & BIT_MASK_MONITOR_CYCLE_LOG2) << BIT_SHIFT_MONITOR_CYCLE_LOG2) +#define BITS_MONITOR_CYCLE_LOG2 \ + (BIT_MASK_MONITOR_CYCLE_LOG2 << BIT_SHIFT_MONITOR_CYCLE_LOG2) +#define BIT_CLEAR_MONITOR_CYCLE_LOG2(x) ((x) & (~BITS_MONITOR_CYCLE_LOG2)) +#define BIT_GET_MONITOR_CYCLE_LOG2(x) \ + (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2) & BIT_MASK_MONITOR_CYCLE_LOG2) +#define BIT_SET_MONITOR_CYCLE_LOG2(x, v) \ + (BIT_CLEAR_MONITOR_CYCLE_LOG2(x) | BIT_MONITOR_CYCLE_LOG2(v)) + +#define BIT_SHIFT_FREQVALUE_UNREGCLK 8 +#define BIT_MASK_FREQVALUE_UNREGCLK 0xffffff +#define BIT_FREQVALUE_UNREGCLK(x) \ + (((x) & BIT_MASK_FREQVALUE_UNREGCLK) << BIT_SHIFT_FREQVALUE_UNREGCLK) +#define BITS_FREQVALUE_UNREGCLK \ + (BIT_MASK_FREQVALUE_UNREGCLK << BIT_SHIFT_FREQVALUE_UNREGCLK) +#define BIT_CLEAR_FREQVALUE_UNREGCLK(x) ((x) & (~BITS_FREQVALUE_UNREGCLK)) +#define BIT_GET_FREQVALUE_UNREGCLK(x) \ + (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK) & BIT_MASK_FREQVALUE_UNREGCLK) +#define BIT_SET_FREQVALUE_UNREGCLK(x, v) \ + (BIT_CLEAR_FREQVALUE_UNREGCLK(x) | BIT_FREQVALUE_UNREGCLK(v)) -#define BIT_SW_BCN_SEL BIT(20) -#define BIT_SW_BCN_SEL_EN BIT(17) -#define BIT_BCN_VALID_1 BIT(16) +#define BIT_CAL32K_DBGMOD BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#define BIT_SHIFT_OSC_32K_RES_COMP 4 +#define BIT_MASK_OSC_32K_RES_COMP 0x3 +#define BIT_OSC_32K_RES_COMP(x) \ + (((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP) +#define BITS_OSC_32K_RES_COMP \ + (BIT_MASK_OSC_32K_RES_COMP << BIT_SHIFT_OSC_32K_RES_COMP) +#define BIT_CLEAR_OSC_32K_RES_COMP(x) ((x) & (~BITS_OSC_32K_RES_COMP)) +#define BIT_GET_OSC_32K_RES_COMP(x) \ + (((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP) +#define BIT_SET_OSC_32K_RES_COMP(x, v) \ + (BIT_CLEAR_OSC_32K_RES_COMP(x) | BIT_OSC_32K_RES_COMP(v)) -/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +#define BIT_OSC_32K_OUT_SEL BIT(3) +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TXPKTNUM_H 16 -#define BIT_MASK_TXPKTNUM_H 0xffff -#define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H) -#define BIT_GET_TXPKTNUM_H(x) (((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H) +/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#define BIT_ISO_WL_2_OSC_32K BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#define BIT_POW_CKGEN BIT(0) -/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_BCN_HEAD_1 8 -#define BIT_MASK_BCN_HEAD_1 0xff -#define BIT_BCN_HEAD_1(x) (((x) & BIT_MASK_BCN_HEAD_1) << BIT_SHIFT_BCN_HEAD_1) -#define BIT_GET_BCN_HEAD_1(x) (((x) >> BIT_SHIFT_BCN_HEAD_1) & BIT_MASK_BCN_HEAD_1) +/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ +#define BIT_SHIFT_NCO_THRS 0 +#define BIT_MASK_NCO_THRS 0x7f +#define BIT_NCO_THRS(x) (((x) & BIT_MASK_NCO_THRS) << BIT_SHIFT_NCO_THRS) +#define BITS_NCO_THRS (BIT_MASK_NCO_THRS << BIT_SHIFT_NCO_THRS) +#define BIT_CLEAR_NCO_THRS(x) ((x) & (~BITS_NCO_THRS)) +#define BIT_GET_NCO_THRS(x) (((x) >> BIT_SHIFT_NCO_THRS) & BIT_MASK_NCO_THRS) +#define BIT_SET_NCO_THRS(x, v) (BIT_CLEAR_NCO_THRS(x) | BIT_NCO_THRS(v)) -#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO 0 -#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ +#define BIT_CAL_32K_REG_WR BIT(31) +#define BIT_CAL_32K_DBG_SEL BIT(22) + +#define BIT_SHIFT_CAL_32K_REG_ADDR 16 +#define BIT_MASK_CAL_32K_REG_ADDR 0x3f +#define BIT_CAL_32K_REG_ADDR(x) \ + (((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR) +#define BITS_CAL_32K_REG_ADDR \ + (BIT_MASK_CAL_32K_REG_ADDR << BIT_SHIFT_CAL_32K_REG_ADDR) +#define BIT_CLEAR_CAL_32K_REG_ADDR(x) ((x) & (~BITS_CAL_32K_REG_ADDR)) +#define BIT_GET_CAL_32K_REG_ADDR(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR) +#define BIT_SET_CAL_32K_REG_ADDR(x, v) \ + (BIT_CLEAR_CAL_32K_REG_ADDR(x) | BIT_CAL_32K_REG_ADDR(v)) + +#define BIT_SHIFT_CAL_32K_REG_DATA 0 +#define BIT_MASK_CAL_32K_REG_DATA 0xffff +#define BIT_CAL_32K_REG_DATA(x) \ + (((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA) +#define BITS_CAL_32K_REG_DATA \ + (BIT_MASK_CAL_32K_REG_DATA << BIT_SHIFT_CAL_32K_REG_DATA) +#define BIT_CLEAR_CAL_32K_REG_DATA(x) ((x) & (~BITS_CAL_32K_REG_DATA)) +#define BIT_GET_CAL_32K_REG_DATA(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA) +#define BIT_SET_CAL_32K_REG_DATA(x, v) \ + (BIT_CLEAR_CAL_32K_REG_DATA(x) | BIT_CAL_32K_REG_DATA(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_C2HEVT (Offset 0x01A0) */ +#define BIT_SHIFT_C2HEVT_MSG 0 +#define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL +#define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG) +#define BITS_C2HEVT_MSG (BIT_MASK_C2HEVT_MSG << BIT_SHIFT_C2HEVT_MSG) +#define BIT_CLEAR_C2HEVT_MSG(x) ((x) & (~BITS_C2HEVT_MSG)) +#define BIT_GET_C2HEVT_MSG(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG) +#define BIT_SET_C2HEVT_MSG(x, v) (BIT_CLEAR_C2HEVT_MSG(x) | BIT_C2HEVT_MSG(v)) -/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TXPKTNUM_H_V1 0 -#define BIT_MASK_TXPKTNUM_H_V1 0xffff -#define BIT_TXPKTNUM_H_V1(x) (((x) & BIT_MASK_TXPKTNUM_H_V1) << BIT_SHIFT_TXPKTNUM_H_V1) -#define BIT_GET_TXPKTNUM_H_V1(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_V1) & BIT_MASK_TXPKTNUM_H_V1) +/* 2 REG_C2HEVT (Offset 0x01A0) */ +#define BIT_SHIFT_C2HEVT_MSG_V1 0 +#define BIT_MASK_C2HEVT_MSG_V1 0xffffffffL +#define BIT_C2HEVT_MSG_V1(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_V1) << BIT_SHIFT_C2HEVT_MSG_V1) +#define BITS_C2HEVT_MSG_V1 (BIT_MASK_C2HEVT_MSG_V1 << BIT_SHIFT_C2HEVT_MSG_V1) +#define BIT_CLEAR_C2HEVT_MSG_V1(x) ((x) & (~BITS_C2HEVT_MSG_V1)) +#define BIT_GET_C2HEVT_MSG_V1(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_V1) & BIT_MASK_C2HEVT_MSG_V1) +#define BIT_SET_C2HEVT_MSG_V1(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_V1(x) | BIT_C2HEVT_MSG_V1(v)) -#endif +/* 2 REG_C2HEVT_1 (Offset 0x01A4) */ +#define BIT_SHIFT_C2HEVT_MSG_1 0 +#define BIT_MASK_C2HEVT_MSG_1 0xffffffffL +#define BIT_C2HEVT_MSG_1(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_1) << BIT_SHIFT_C2HEVT_MSG_1) +#define BITS_C2HEVT_MSG_1 (BIT_MASK_C2HEVT_MSG_1 << BIT_SHIFT_C2HEVT_MSG_1) +#define BIT_CLEAR_C2HEVT_MSG_1(x) ((x) & (~BITS_C2HEVT_MSG_1)) +#define BIT_GET_C2HEVT_MSG_1(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_1) & BIT_MASK_C2HEVT_MSG_1) +#define BIT_SET_C2HEVT_MSG_1(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_1(x) | BIT_C2HEVT_MSG_1(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_C2HEVT_2 (Offset 0x01A8) */ +#define BIT_SHIFT_C2HEVT_MSG_2 0 +#define BIT_MASK_C2HEVT_MSG_2 0xffffffffL +#define BIT_C2HEVT_MSG_2(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_2) << BIT_SHIFT_C2HEVT_MSG_2) +#define BITS_C2HEVT_MSG_2 (BIT_MASK_C2HEVT_MSG_2 << BIT_SHIFT_C2HEVT_MSG_2) +#define BIT_CLEAR_C2HEVT_MSG_2(x) ((x) & (~BITS_C2HEVT_MSG_2)) +#define BIT_GET_C2HEVT_MSG_2(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_2) & BIT_MASK_C2HEVT_MSG_2) +#define BIT_SET_C2HEVT_MSG_2(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_2(x) | BIT_C2HEVT_MSG_2(v)) -/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +/* 2 REG_C2HEVT_3 (Offset 0x01AC) */ +#define BIT_SHIFT_C2HEVT_MSG_3 0 +#define BIT_MASK_C2HEVT_MSG_3 0xffffffffL +#define BIT_C2HEVT_MSG_3(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_3) << BIT_SHIFT_C2HEVT_MSG_3) +#define BITS_C2HEVT_MSG_3 (BIT_MASK_C2HEVT_MSG_3 << BIT_SHIFT_C2HEVT_MSG_3) +#define BIT_CLEAR_C2HEVT_MSG_3(x) ((x) & (~BITS_C2HEVT_MSG_3)) +#define BIT_GET_C2HEVT_MSG_3(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_3) & BIT_MASK_C2HEVT_MSG_3) +#define BIT_SET_C2HEVT_MSG_3(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_3(x) | BIT_C2HEVT_MSG_3(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_MISC_CTRL_V1 (Offset 0x01B0) */ + +#define BIT_SHIFT_PHYWR_SETUP_CNT 28 +#define BIT_MASK_PHYWR_SETUP_CNT 0xf +#define BIT_PHYWR_SETUP_CNT(x) \ + (((x) & BIT_MASK_PHYWR_SETUP_CNT) << BIT_SHIFT_PHYWR_SETUP_CNT) +#define BITS_PHYWR_SETUP_CNT \ + (BIT_MASK_PHYWR_SETUP_CNT << BIT_SHIFT_PHYWR_SETUP_CNT) +#define BIT_CLEAR_PHYWR_SETUP_CNT(x) ((x) & (~BITS_PHYWR_SETUP_CNT)) +#define BIT_GET_PHYWR_SETUP_CNT(x) \ + (((x) >> BIT_SHIFT_PHYWR_SETUP_CNT) & BIT_MASK_PHYWR_SETUP_CNT) +#define BIT_SET_PHYWR_SETUP_CNT(x, v) \ + (BIT_CLEAR_PHYWR_SETUP_CNT(x) | BIT_PHYWR_SETUP_CNT(v)) + +#define BIT_SHIFT_PHYWR_HOLD_CNT 24 +#define BIT_MASK_PHYWR_HOLD_CNT 0xf +#define BIT_PHYWR_HOLD_CNT(x) \ + (((x) & BIT_MASK_PHYWR_HOLD_CNT) << BIT_SHIFT_PHYWR_HOLD_CNT) +#define BITS_PHYWR_HOLD_CNT \ + (BIT_MASK_PHYWR_HOLD_CNT << BIT_SHIFT_PHYWR_HOLD_CNT) +#define BIT_CLEAR_PHYWR_HOLD_CNT(x) ((x) & (~BITS_PHYWR_HOLD_CNT)) +#define BIT_GET_PHYWR_HOLD_CNT(x) \ + (((x) >> BIT_SHIFT_PHYWR_HOLD_CNT) & BIT_MASK_PHYWR_HOLD_CNT) +#define BIT_SET_PHYWR_HOLD_CNT(x, v) \ + (BIT_CLEAR_PHYWR_HOLD_CNT(x) | BIT_PHYWR_HOLD_CNT(v)) + +#define BIT_SHIFT_TXBUF_WKCAM_OFFSET 8 +#define BIT_MASK_TXBUF_WKCAM_OFFSET 0x1fff +#define BIT_TXBUF_WKCAM_OFFSET(x) \ + (((x) & BIT_MASK_TXBUF_WKCAM_OFFSET) << BIT_SHIFT_TXBUF_WKCAM_OFFSET) +#define BITS_TXBUF_WKCAM_OFFSET \ + (BIT_MASK_TXBUF_WKCAM_OFFSET << BIT_SHIFT_TXBUF_WKCAM_OFFSET) +#define BIT_CLEAR_TXBUF_WKCAM_OFFSET(x) ((x) & (~BITS_TXBUF_WKCAM_OFFSET)) +#define BIT_GET_TXBUF_WKCAM_OFFSET(x) \ + (((x) >> BIT_SHIFT_TXBUF_WKCAM_OFFSET) & BIT_MASK_TXBUF_WKCAM_OFFSET) +#define BIT_SET_TXBUF_WKCAM_OFFSET(x, v) \ + (BIT_CLEAR_TXBUF_WKCAM_OFFSET(x) | BIT_TXBUF_WKCAM_OFFSET(v)) + +#define BIT_SHIFT_PHYRD_WAIT_CNT 4 +#define BIT_MASK_PHYRD_WAIT_CNT 0xf +#define BIT_PHYRD_WAIT_CNT(x) \ + (((x) & BIT_MASK_PHYRD_WAIT_CNT) << BIT_SHIFT_PHYRD_WAIT_CNT) +#define BITS_PHYRD_WAIT_CNT \ + (BIT_MASK_PHYRD_WAIT_CNT << BIT_SHIFT_PHYRD_WAIT_CNT) +#define BIT_CLEAR_PHYRD_WAIT_CNT(x) ((x) & (~BITS_PHYRD_WAIT_CNT)) +#define BIT_GET_PHYRD_WAIT_CNT(x) \ + (((x) >> BIT_SHIFT_PHYRD_WAIT_CNT) & BIT_MASK_PHYRD_WAIT_CNT) +#define BIT_SET_PHYRD_WAIT_CNT(x, v) \ + (BIT_CLEAR_PHYRD_WAIT_CNT(x) | BIT_PHYRD_WAIT_CNT(v)) + +#define BIT_SHIFT_H2CQ_PRI 0 +#define BIT_MASK_H2CQ_PRI 0x3 +#define BIT_H2CQ_PRI(x) (((x) & BIT_MASK_H2CQ_PRI) << BIT_SHIFT_H2CQ_PRI) +#define BITS_H2CQ_PRI (BIT_MASK_H2CQ_PRI << BIT_SHIFT_H2CQ_PRI) +#define BIT_CLEAR_H2CQ_PRI(x) ((x) & (~BITS_H2CQ_PRI)) +#define BIT_GET_H2CQ_PRI(x) (((x) >> BIT_SHIFT_H2CQ_PRI) & BIT_MASK_H2CQ_PRI) +#define BIT_SET_H2CQ_PRI(x, v) (BIT_CLEAR_H2CQ_PRI(x) | BIT_H2CQ_PRI(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_RXDESC_BUFF_RPTR (Offset 0x01B0) */ + +#define BIT_SHIFT_RXDESC_BUFF_RPTR 0 +#define BIT_MASK_RXDESC_BUFF_RPTR 0xffffffffL +#define BIT_RXDESC_BUFF_RPTR(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_RPTR) << BIT_SHIFT_RXDESC_BUFF_RPTR) +#define BITS_RXDESC_BUFF_RPTR \ + (BIT_MASK_RXDESC_BUFF_RPTR << BIT_SHIFT_RXDESC_BUFF_RPTR) +#define BIT_CLEAR_RXDESC_BUFF_RPTR(x) ((x) & (~BITS_RXDESC_BUFF_RPTR)) +#define BIT_GET_RXDESC_BUFF_RPTR(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_RPTR) & BIT_MASK_RXDESC_BUFF_RPTR) +#define BIT_SET_RXDESC_BUFF_RPTR(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_RPTR(x) | BIT_RXDESC_BUFF_RPTR(v)) + +/* 2 REG_RXDESC_BUFF_WPTR (Offset 0x01B4) */ + +#define BIT_SHIFT_RXDESC_BUFF_WPTR 0 +#define BIT_MASK_RXDESC_BUFF_WPTR 0xffffffffL +#define BIT_RXDESC_BUFF_WPTR(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_WPTR) << BIT_SHIFT_RXDESC_BUFF_WPTR) +#define BITS_RXDESC_BUFF_WPTR \ + (BIT_MASK_RXDESC_BUFF_WPTR << BIT_SHIFT_RXDESC_BUFF_WPTR) +#define BIT_CLEAR_RXDESC_BUFF_WPTR(x) ((x) & (~BITS_RXDESC_BUFF_WPTR)) +#define BIT_GET_RXDESC_BUFF_WPTR(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_WPTR) & BIT_MASK_RXDESC_BUFF_WPTR) +#define BIT_SET_RXDESC_BUFF_WPTR(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_WPTR(x) | BIT_RXDESC_BUFF_WPTR(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TXPKTNUM_V2 0 -#define BIT_MASK_TXPKTNUM_V2 0xffff -#define BIT_TXPKTNUM_V2(x) (((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2) -#define BIT_GET_TXPKTNUM_V2(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2) +/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ +#define BIT_SHIFT_SW_DEFINED_PAGE1 0 +#define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL +#define BIT_SW_DEFINED_PAGE1(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1) +#define BITS_SW_DEFINED_PAGE1 \ + (BIT_MASK_SW_DEFINED_PAGE1 << BIT_SHIFT_SW_DEFINED_PAGE1) +#define BIT_CLEAR_SW_DEFINED_PAGE1(x) ((x) & (~BITS_SW_DEFINED_PAGE1)) +#define BIT_GET_SW_DEFINED_PAGE1(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1) +#define BIT_SET_SW_DEFINED_PAGE1(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1(x) | BIT_SW_DEFINED_PAGE1(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ +#define BIT_SHIFT_SW_DEFINED_PAGE1_V1 0 +#define BIT_MASK_SW_DEFINED_PAGE1_V1 0xffffffffL +#define BIT_SW_DEFINED_PAGE1_V1(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1) << BIT_SHIFT_SW_DEFINED_PAGE1_V1) +#define BITS_SW_DEFINED_PAGE1_V1 \ + (BIT_MASK_SW_DEFINED_PAGE1_V1 << BIT_SHIFT_SW_DEFINED_PAGE1_V1) +#define BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) ((x) & (~BITS_SW_DEFINED_PAGE1_V1)) +#define BIT_GET_SW_DEFINED_PAGE1_V1(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1) & BIT_MASK_SW_DEFINED_PAGE1_V1) +#define BIT_SET_SW_DEFINED_PAGE1_V1(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) | BIT_SW_DEFINED_PAGE1_V1(v)) -/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ +/* 2 REG_SW_DEFINED_PAGE2 (Offset 0x01BC) */ -#define BIT_EXQ_PUBLIC_DIS_V1 BIT(19) -#define BIT_NPQ_PUBLIC_DIS_V1 BIT(18) -#define BIT_LPQ_PUBLIC_DIS_V1 BIT(17) -#define BIT_HPQ_PUBLIC_DIS_V1 BIT(16) +#define BIT_SHIFT_SW_DEFINED_PAGE2 0 +#define BIT_MASK_SW_DEFINED_PAGE2 0xffffffffL +#define BIT_SW_DEFINED_PAGE2(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE2) << BIT_SHIFT_SW_DEFINED_PAGE2) +#define BITS_SW_DEFINED_PAGE2 \ + (BIT_MASK_SW_DEFINED_PAGE2 << BIT_SHIFT_SW_DEFINED_PAGE2) +#define BIT_CLEAR_SW_DEFINED_PAGE2(x) ((x) & (~BITS_SW_DEFINED_PAGE2)) +#define BIT_GET_SW_DEFINED_PAGE2(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2) & BIT_MASK_SW_DEFINED_PAGE2) +#define BIT_SET_SW_DEFINED_PAGE2(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE2(x) | BIT_SW_DEFINED_PAGE2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_MCUTST_I (Offset 0x01C0) */ +#define BIT_SHIFT_MCUDMSG_I 0 +#define BIT_MASK_MCUDMSG_I 0xffffffffL +#define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I) +#define BITS_MCUDMSG_I (BIT_MASK_MCUDMSG_I << BIT_SHIFT_MCUDMSG_I) +#define BIT_CLEAR_MCUDMSG_I(x) ((x) & (~BITS_MCUDMSG_I)) +#define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I) +#define BIT_SET_MCUDMSG_I(x, v) (BIT_CLEAR_MCUDMSG_I(x) | BIT_MCUDMSG_I(v)) -/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ +/* 2 REG_MCUTST_II (Offset 0x01C4) */ -#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN BIT(15) +#define BIT_SHIFT_MCUDMSG_II 0 +#define BIT_MASK_MCUDMSG_II 0xffffffffL +#define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II) +#define BITS_MCUDMSG_II (BIT_MASK_MCUDMSG_II << BIT_SHIFT_MCUDMSG_II) +#define BIT_CLEAR_MCUDMSG_II(x) ((x) & (~BITS_MCUDMSG_II)) +#define BIT_GET_MCUDMSG_II(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II) +#define BIT_SET_MCUDMSG_II(x, v) (BIT_CLEAR_MCUDMSG_II(x) | BIT_MCUDMSG_II(v)) -#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE 0 -#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE 0xfff -#define BIT_SDIO_TXAGG_ALIGN_SIZE(x) (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) -#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE(x) (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) +/* 2 REG_FMETHR (Offset 0x01C8) */ +#define BIT_FMSG_INT BIT(31) -#endif +#define BIT_SHIFT_FW_MSG 0 +#define BIT_MASK_FW_MSG 0xffffffffL +#define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG) +#define BITS_FW_MSG (BIT_MASK_FW_MSG << BIT_SHIFT_FW_MSG) +#define BIT_CLEAR_FW_MSG(x) ((x) & (~BITS_FW_MSG)) +#define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG) +#define BIT_SET_FW_MSG(x, v) (BIT_CLEAR_FW_MSG(x) | BIT_FW_MSG(v)) +/* 2 REG_HMETFR (Offset 0x01CC) */ -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_HRCV_MSG 24 +#define BIT_MASK_HRCV_MSG 0xff +#define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG) +#define BITS_HRCV_MSG (BIT_MASK_HRCV_MSG << BIT_SHIFT_HRCV_MSG) +#define BIT_CLEAR_HRCV_MSG(x) ((x) & (~BITS_HRCV_MSG)) +#define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG) +#define BIT_SET_HRCV_MSG(x, v) (BIT_CLEAR_HRCV_MSG(x) | BIT_HRCV_MSG(v)) +#define BIT_INT_BOX3 BIT(3) +#define BIT_INT_BOX2 BIT(2) +#define BIT_INT_BOX1 BIT(1) +#define BIT_INT_BOX0 BIT(0) -/* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */ +/* 2 REG_HMEBOX0 (Offset 0x01D0) */ +#define BIT_SHIFT_HOST_MSG_0 0 +#define BIT_MASK_HOST_MSG_0 0xffffffffL +#define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0) +#define BITS_HOST_MSG_0 (BIT_MASK_HOST_MSG_0 << BIT_SHIFT_HOST_MSG_0) +#define BIT_CLEAR_HOST_MSG_0(x) ((x) & (~BITS_HOST_MSG_0)) +#define BIT_GET_HOST_MSG_0(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0) +#define BIT_SET_HOST_MSG_0(x, v) (BIT_CLEAR_HOST_MSG_0(x) | BIT_HOST_MSG_0(v)) -#define BIT_SHIFT_HPQ_AVAL_PG_V1 16 -#define BIT_MASK_HPQ_AVAL_PG_V1 0xfff -#define BIT_HPQ_AVAL_PG_V1(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1) -#define BIT_GET_HPQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1) +/* 2 REG_HMEBOX1 (Offset 0x01D4) */ +#define BIT_SHIFT_HOST_MSG_1 0 +#define BIT_MASK_HOST_MSG_1 0xffffffffL +#define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1) +#define BITS_HOST_MSG_1 (BIT_MASK_HOST_MSG_1 << BIT_SHIFT_HOST_MSG_1) +#define BIT_CLEAR_HOST_MSG_1(x) ((x) & (~BITS_HOST_MSG_1)) +#define BIT_GET_HOST_MSG_1(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1) +#define BIT_SET_HOST_MSG_1(x, v) (BIT_CLEAR_HOST_MSG_1(x) | BIT_HOST_MSG_1(v)) -#define BIT_SHIFT_HPQ_V1 0 -#define BIT_MASK_HPQ_V1 0xfff -#define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1) -#define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1) +/* 2 REG_HMEBOX2 (Offset 0x01D8) */ +#define BIT_SHIFT_HOST_MSG_2 0 +#define BIT_MASK_HOST_MSG_2 0xffffffffL +#define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2) +#define BITS_HOST_MSG_2 (BIT_MASK_HOST_MSG_2 << BIT_SHIFT_HOST_MSG_2) +#define BIT_CLEAR_HOST_MSG_2(x) ((x) & (~BITS_HOST_MSG_2)) +#define BIT_GET_HOST_MSG_2(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2) +#define BIT_SET_HOST_MSG_2(x, v) (BIT_CLEAR_HOST_MSG_2(x) | BIT_HOST_MSG_2(v)) -/* 2 REG_FIFOPAGE_INFO_2 (Offset 0x0234) */ +/* 2 REG_HMEBOX3 (Offset 0x01DC) */ +#define BIT_SHIFT_HOST_MSG_3 0 +#define BIT_MASK_HOST_MSG_3 0xffffffffL +#define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3) +#define BITS_HOST_MSG_3 (BIT_MASK_HOST_MSG_3 << BIT_SHIFT_HOST_MSG_3) +#define BIT_CLEAR_HOST_MSG_3(x) ((x) & (~BITS_HOST_MSG_3)) +#define BIT_GET_HOST_MSG_3(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3) +#define BIT_SET_HOST_MSG_3(x, v) (BIT_CLEAR_HOST_MSG_3(x) | BIT_HOST_MSG_3(v)) -#define BIT_SHIFT_LPQ_AVAL_PG_V1 16 -#define BIT_MASK_LPQ_AVAL_PG_V1 0xfff -#define BIT_LPQ_AVAL_PG_V1(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1) -#define BIT_GET_LPQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_LPQ_V1 0 -#define BIT_MASK_LPQ_V1 0xfff -#define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1) -#define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1) +/* 2 REG_RXDESC_BUFF_BNDY (Offset 0x01E0) */ +#define BIT_FW_FIFO_PTR_RST BIT(18) +#define BIT_PHY_FIFO_PTR_RST BIT(17) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LLT_INIT (Offset 0x01E0) */ +#define BIT_SHIFT_LLTINI_PDATA_V1 16 +#define BIT_MASK_LLTINI_PDATA_V1 0xfff +#define BIT_LLTINI_PDATA_V1(x) \ + (((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1) +#define BITS_LLTINI_PDATA_V1 \ + (BIT_MASK_LLTINI_PDATA_V1 << BIT_SHIFT_LLTINI_PDATA_V1) +#define BIT_CLEAR_LLTINI_PDATA_V1(x) ((x) & (~BITS_LLTINI_PDATA_V1)) +#define BIT_GET_LLTINI_PDATA_V1(x) \ + (((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1) +#define BIT_SET_LLTINI_PDATA_V1(x, v) \ + (BIT_CLEAR_LLTINI_PDATA_V1(x) | BIT_LLTINI_PDATA_V1(v)) -/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ +#define BIT_SHIFT_LLTINI_HDATA_V1 0 +#define BIT_MASK_LLTINI_HDATA_V1 0xfff +#define BIT_LLTINI_HDATA_V1(x) \ + (((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1) +#define BITS_LLTINI_HDATA_V1 \ + (BIT_MASK_LLTINI_HDATA_V1 << BIT_SHIFT_LLTINI_HDATA_V1) +#define BIT_CLEAR_LLTINI_HDATA_V1(x) ((x) & (~BITS_LLTINI_HDATA_V1)) +#define BIT_GET_LLTINI_HDATA_V1(x) \ + (((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1) +#define BIT_SET_LLTINI_HDATA_V1(x, v) \ + (BIT_CLEAR_LLTINI_HDATA_V1(x) | BIT_LLTINI_HDATA_V1(v)) +#endif -#define BIT_SHIFT_NPQ_AVAL_PG_V1 16 -#define BIT_MASK_NPQ_AVAL_PG_V1 0xfff -#define BIT_NPQ_AVAL_PG_V1(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1) -#define BIT_GET_NPQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_RXDESC_BUFF_BNDY (Offset 0x01E0) */ -#endif +#define BIT_SHIFT_RXDESC_BUFF_BNDY 0 +#define BIT_MASK_RXDESC_BUFF_BNDY 0xffffffffL +#define BIT_RXDESC_BUFF_BNDY(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_BNDY) << BIT_SHIFT_RXDESC_BUFF_BNDY) +#define BITS_RXDESC_BUFF_BNDY \ + (BIT_MASK_RXDESC_BUFF_BNDY << BIT_SHIFT_RXDESC_BUFF_BNDY) +#define BIT_CLEAR_RXDESC_BUFF_BNDY(x) ((x) & (~BITS_RXDESC_BUFF_BNDY)) +#define BIT_GET_RXDESC_BUFF_BNDY(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_BNDY) & BIT_MASK_RXDESC_BUFF_BNDY) +#define BIT_SET_RXDESC_BUFF_BNDY(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_BNDY(x) | BIT_RXDESC_BUFF_BNDY(v)) +#endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_GENTST (Offset 0x01E4) */ -/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ +#define BIT_SHIFT_GENTST 0 +#define BIT_MASK_GENTST 0xffffffffL +#define BIT_GENTST(x) (((x) & BIT_MASK_GENTST) << BIT_SHIFT_GENTST) +#define BITS_GENTST (BIT_MASK_GENTST << BIT_SHIFT_GENTST) +#define BIT_CLEAR_GENTST(x) ((x) & (~BITS_GENTST)) +#define BIT_GET_GENTST(x) (((x) >> BIT_SHIFT_GENTST) & BIT_MASK_GENTST) +#define BIT_SET_GENTST(x, v) (BIT_CLEAR_GENTST(x) | BIT_GENTST(v)) +#endif -#define BIT_SHIFT_NPQ_V1 0 -#define BIT_MASK_NPQ_V1 0xfff -#define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1) -#define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LLT_INIT_ADDR (Offset 0x01E4) */ -/* 2 REG_FIFOPAGE_INFO_4 (Offset 0x023C) */ +#define BIT_SHIFT_LLTINI_ADDR_V1 0 +#define BIT_MASK_LLTINI_ADDR_V1 0xfff +#define BIT_LLTINI_ADDR_V1(x) \ + (((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1) +#define BITS_LLTINI_ADDR_V1 \ + (BIT_MASK_LLTINI_ADDR_V1 << BIT_SHIFT_LLTINI_ADDR_V1) +#define BIT_CLEAR_LLTINI_ADDR_V1(x) ((x) & (~BITS_LLTINI_ADDR_V1)) +#define BIT_GET_LLTINI_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1) +#define BIT_SET_LLTINI_ADDR_V1(x, v) \ + (BIT_CLEAR_LLTINI_ADDR_V1(x) | BIT_LLTINI_ADDR_V1(v)) +#endif -#define BIT_SHIFT_EXQ_AVAL_PG_V1 16 -#define BIT_MASK_EXQ_AVAL_PG_V1 0xfff -#define BIT_EXQ_AVAL_PG_V1(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1) -#define BIT_GET_EXQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ -#define BIT_SHIFT_EXQ_V1 0 -#define BIT_MASK_EXQ_V1 0xfff -#define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1) -#define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1) +#define BIT_SHIFT_BB_WRITE_READ 30 +#define BIT_MASK_BB_WRITE_READ 0x3 +#define BIT_BB_WRITE_READ(x) \ + (((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ) +#define BITS_BB_WRITE_READ (BIT_MASK_BB_WRITE_READ << BIT_SHIFT_BB_WRITE_READ) +#define BIT_CLEAR_BB_WRITE_READ(x) ((x) & (~BITS_BB_WRITE_READ)) +#define BIT_GET_BB_WRITE_READ(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ) +#define BIT_SET_BB_WRITE_READ(x, v) \ + (BIT_CLEAR_BB_WRITE_READ(x) | BIT_BB_WRITE_READ(v)) +#endif -/* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */ +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) +/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ -#define BIT_SHIFT_PUBQ_AVAL_PG_V1 16 -#define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff -#define BIT_PUBQ_AVAL_PG_V1(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1) -#define BIT_GET_PUBQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1) +#define BIT_SHIFT_BB_WRITE_EN_V1 16 +#define BIT_MASK_BB_WRITE_EN_V1 0xf +#define BIT_BB_WRITE_EN_V1(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_V1) << BIT_SHIFT_BB_WRITE_EN_V1) +#define BITS_BB_WRITE_EN_V1 \ + (BIT_MASK_BB_WRITE_EN_V1 << BIT_SHIFT_BB_WRITE_EN_V1) +#define BIT_CLEAR_BB_WRITE_EN_V1(x) ((x) & (~BITS_BB_WRITE_EN_V1)) +#define BIT_GET_BB_WRITE_EN_V1(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_V1) & BIT_MASK_BB_WRITE_EN_V1) +#define BIT_SET_BB_WRITE_EN_V1(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_V1(x) | BIT_BB_WRITE_EN_V1(v)) +#endif -#define BIT_SHIFT_PUBQ_V1 0 -#define BIT_MASK_PUBQ_V1 0xfff -#define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1) -#define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ -#endif +#define BIT_SHIFT_BB_WRITE_EN 12 +#define BIT_MASK_BB_WRITE_EN 0xf +#define BIT_BB_WRITE_EN(x) \ + (((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN) +#define BITS_BB_WRITE_EN (BIT_MASK_BB_WRITE_EN << BIT_SHIFT_BB_WRITE_EN) +#define BIT_CLEAR_BB_WRITE_EN(x) ((x) & (~BITS_BB_WRITE_EN)) +#define BIT_GET_BB_WRITE_EN(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN) +#define BIT_SET_BB_WRITE_EN(x, v) \ + (BIT_CLEAR_BB_WRITE_EN(x) | BIT_BB_WRITE_EN(v)) +#define BIT_SHIFT_BB_ADDR 2 +#define BIT_MASK_BB_ADDR 0x1ff +#define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR) +#define BITS_BB_ADDR (BIT_MASK_BB_ADDR << BIT_SHIFT_BB_ADDR) +#define BIT_CLEAR_BB_ADDR(x) ((x) & (~BITS_BB_ADDR)) +#define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR) +#define BIT_SET_BB_ADDR(x, v) (BIT_CLEAR_BB_ADDR(x) | BIT_BB_ADDR(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_H2C_HEAD (Offset 0x0244) */ +/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ +#define BIT_SHIFT_BB_ADDR_V1 2 +#define BIT_MASK_BB_ADDR_V1 0xfff +#define BIT_BB_ADDR_V1(x) (((x) & BIT_MASK_BB_ADDR_V1) << BIT_SHIFT_BB_ADDR_V1) +#define BITS_BB_ADDR_V1 (BIT_MASK_BB_ADDR_V1 << BIT_SHIFT_BB_ADDR_V1) +#define BIT_CLEAR_BB_ADDR_V1(x) ((x) & (~BITS_BB_ADDR_V1)) +#define BIT_GET_BB_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_V1) & BIT_MASK_BB_ADDR_V1) +#define BIT_SET_BB_ADDR_V1(x, v) (BIT_CLEAR_BB_ADDR_V1(x) | BIT_BB_ADDR_V1(v)) -#define BIT_SHIFT_H2C_HEAD 0 -#define BIT_MASK_H2C_HEAD 0x3ffff -#define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD) -#define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_H2C_TAIL (Offset 0x0248) */ +/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ +#define BIT_BB_ERRACC BIT(0) -#define BIT_SHIFT_H2C_TAIL 0 -#define BIT_MASK_H2C_TAIL 0x3ffff -#define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL) -#define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL) +/* 2 REG_BB_ACCESS_DATA (Offset 0x01EC) */ +#define BIT_SHIFT_BB_DATA 0 +#define BIT_MASK_BB_DATA 0xffffffffL +#define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA) +#define BITS_BB_DATA (BIT_MASK_BB_DATA << BIT_SHIFT_BB_DATA) +#define BIT_CLEAR_BB_DATA(x) ((x) & (~BITS_BB_DATA)) +#define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA) +#define BIT_SET_BB_DATA(x, v) (BIT_CLEAR_BB_DATA(x) | BIT_BB_DATA(v)) -/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */ +/* 2 REG_HMEBOX_E0 (Offset 0x01F0) */ +#define BIT_SHIFT_HMEBOX_E0 0 +#define BIT_MASK_HMEBOX_E0 0xffffffffL +#define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0) +#define BITS_HMEBOX_E0 (BIT_MASK_HMEBOX_E0 << BIT_SHIFT_HMEBOX_E0) +#define BIT_CLEAR_HMEBOX_E0(x) ((x) & (~BITS_HMEBOX_E0)) +#define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0) +#define BIT_SET_HMEBOX_E0(x, v) (BIT_CLEAR_HMEBOX_E0(x) | BIT_HMEBOX_E0(v)) -#define BIT_SHIFT_H2C_READ_ADDR 0 -#define BIT_MASK_H2C_READ_ADDR 0x3ffff -#define BIT_H2C_READ_ADDR(x) (((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR) -#define BIT_GET_H2C_READ_ADDR(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR) +/* 2 REG_HMEBOX_E1 (Offset 0x01F4) */ +#define BIT_SHIFT_HMEBOX_E1 0 +#define BIT_MASK_HMEBOX_E1 0xffffffffL +#define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1) +#define BITS_HMEBOX_E1 (BIT_MASK_HMEBOX_E1 << BIT_SHIFT_HMEBOX_E1) +#define BIT_CLEAR_HMEBOX_E1(x) ((x) & (~BITS_HMEBOX_E1)) +#define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1) +#define BIT_SET_HMEBOX_E1(x, v) (BIT_CLEAR_HMEBOX_E1(x) | BIT_HMEBOX_E1(v)) -/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */ +/* 2 REG_HMEBOX_E2 (Offset 0x01F8) */ +#define BIT_SHIFT_HMEBOX_E2 0 +#define BIT_MASK_HMEBOX_E2 0xffffffffL +#define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2) +#define BITS_HMEBOX_E2 (BIT_MASK_HMEBOX_E2 << BIT_SHIFT_HMEBOX_E2) +#define BIT_CLEAR_HMEBOX_E2(x) ((x) & (~BITS_HMEBOX_E2)) +#define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2) +#define BIT_SET_HMEBOX_E2(x, v) (BIT_CLEAR_HMEBOX_E2(x) | BIT_HMEBOX_E2(v)) -#define BIT_SHIFT_H2C_WR_ADDR 0 -#define BIT_MASK_H2C_WR_ADDR 0x3ffff -#define BIT_H2C_WR_ADDR(x) (((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR) -#define BIT_GET_H2C_WR_ADDR(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR) +/* 2 REG_HMEBOX_E3 (Offset 0x01FC) */ +#define BIT_SHIFT_HMEBOX_E3 0 +#define BIT_MASK_HMEBOX_E3 0xffffffffL +#define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3) +#define BITS_HMEBOX_E3 (BIT_MASK_HMEBOX_E3 << BIT_SHIFT_HMEBOX_E3) +#define BIT_CLEAR_HMEBOX_E3(x) ((x) & (~BITS_HMEBOX_E3)) +#define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3) +#define BIT_SET_HMEBOX_E3(x, v) (BIT_CLEAR_HMEBOX_E3(x) | BIT_HMEBOX_E3(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BCN_CTRL_0 (Offset 0x0200) */ +#define BIT_BCN1_VALID BIT(31) -/* 2 REG_H2C_INFO (Offset 0x0254) */ - - -#define BIT_SHIFT_VI_PUB_LIMIT 16 -#define BIT_MASK_VI_PUB_LIMIT 0xfff -#define BIT_VI_PUB_LIMIT(x) (((x) & BIT_MASK_VI_PUB_LIMIT) << BIT_SHIFT_VI_PUB_LIMIT) -#define BIT_GET_VI_PUB_LIMIT(x) (((x) >> BIT_SHIFT_VI_PUB_LIMIT) & BIT_MASK_VI_PUB_LIMIT) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_BK_PUB_LIMIT 16 -#define BIT_MASK_BK_PUB_LIMIT 0xfff -#define BIT_BK_PUB_LIMIT(x) (((x) & BIT_MASK_BK_PUB_LIMIT) << BIT_SHIFT_BK_PUB_LIMIT) -#define BIT_GET_BK_PUB_LIMIT(x) (((x) >> BIT_SHIFT_BK_PUB_LIMIT) & BIT_MASK_BK_PUB_LIMIT) +/* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */ -#define BIT_EXQ_EN_PUBLIC_LIMIT BIT(11) -#define BIT_NPQ_EN_PUBLIC_LIMIT BIT(10) -#define BIT_LPQ_EN_PUBLIC_LIMIT BIT(9) -#define BIT_HPQ_EN_PUBLIC_LIMIT BIT(8) +#define BIT_EP2Q_PUBLIC_DIS BIT(29) +#define BIT_EP1Q_PUBLIC_DIS BIT(28) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */ -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_EPQ_PUBLIC_DIS BIT(27) +#define BIT_NPQ_PUBLIC_DIS BIT(26) +#define BIT_LPQ_PUBLIC_DIS BIT(25) +#define BIT_HPQ_PUBLIC_DIS BIT(24) +#define BIT_SHIFT_PUBQ 16 +#define BIT_MASK_PUBQ 0xff +#define BIT_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ) +#define BITS_PUBQ (BIT_MASK_PUBQ << BIT_SHIFT_PUBQ) +#define BIT_CLEAR_PUBQ(x) ((x) & (~BITS_PUBQ)) +#define BIT_GET_PUBQ(x) (((x) >> BIT_SHIFT_PUBQ) & BIT_MASK_PUBQ) +#define BIT_SET_PUBQ(x, v) (BIT_CLEAR_PUBQ(x) | BIT_PUBQ(v)) -/* 2 REG_H2C_INFO (Offset 0x0254) */ +#endif -#define BIT_H2C_SPACE_VLD BIT(3) -#define BIT_H2C_WR_ADDR_RST BIT(2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_H2C_LEN_SEL 0 -#define BIT_MASK_H2C_LEN_SEL 0x3 -#define BIT_H2C_LEN_SEL(x) (((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL) -#define BIT_GET_H2C_LEN_SEL(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL) +/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ +#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16 +#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff +#define BIT_TX_OQT_HE_FREE_SPACE_V1(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) +#define BITS_TX_OQT_HE_FREE_SPACE_V1 \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x) \ + ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) +#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x) | BIT_TX_OQT_HE_FREE_SPACE_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BCN_CTRL_0 (Offset 0x0200) */ +#define BIT_SHIFT_BCN1_HEAD 16 +#define BIT_MASK_BCN1_HEAD 0xfff +#define BIT_BCN1_HEAD(x) (((x) & BIT_MASK_BCN1_HEAD) << BIT_SHIFT_BCN1_HEAD) +#define BITS_BCN1_HEAD (BIT_MASK_BCN1_HEAD << BIT_SHIFT_BCN1_HEAD) +#define BIT_CLEAR_BCN1_HEAD(x) ((x) & (~BITS_BCN1_HEAD)) +#define BIT_GET_BCN1_HEAD(x) (((x) >> BIT_SHIFT_BCN1_HEAD) & BIT_MASK_BCN1_HEAD) +#define BIT_SET_BCN1_HEAD(x, v) (BIT_CLEAR_BCN1_HEAD(x) | BIT_BCN1_HEAD(v)) -/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_BCN0_VALID BIT(15) +#endif -#define BIT_SHIFT_VO_PUB_LIMIT 0 -#define BIT_MASK_VO_PUB_LIMIT 0xfff -#define BIT_VO_PUB_LIMIT(x) (((x) & BIT_MASK_VO_PUB_LIMIT) << BIT_SHIFT_VO_PUB_LIMIT) -#define BIT_GET_VO_PUB_LIMIT(x) (((x) >> BIT_SHIFT_VO_PUB_LIMIT) & BIT_MASK_VO_PUB_LIMIT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */ -#define BIT_SHIFT_BE_PUB_LIMIT 0 -#define BIT_MASK_BE_PUB_LIMIT 0xfff -#define BIT_BE_PUB_LIMIT(x) (((x) & BIT_MASK_BE_PUB_LIMIT) << BIT_SHIFT_BE_PUB_LIMIT) -#define BIT_GET_BE_PUB_LIMIT(x) (((x) >> BIT_SHIFT_BE_PUB_LIMIT) & BIT_MASK_BE_PUB_LIMIT) +#define BIT_SHIFT_LPQ 8 +#define BIT_MASK_LPQ 0xff +#define BIT_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ) +#define BITS_LPQ (BIT_MASK_LPQ << BIT_SHIFT_LPQ) +#define BIT_CLEAR_LPQ(x) ((x) & (~BITS_LPQ)) +#define BIT_GET_LPQ(x) (((x) >> BIT_SHIFT_LPQ) & BIT_MASK_LPQ) +#define BIT_SET_LPQ(x, v) (BIT_CLEAR_LPQ(x) | BIT_LPQ(v)) +#define BIT_SHIFT_HPQ 0 +#define BIT_MASK_HPQ 0xff +#define BIT_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ) +#define BITS_HPQ (BIT_MASK_HPQ << BIT_SHIFT_HPQ) +#define BIT_CLEAR_HPQ(x) ((x) & (~BITS_HPQ)) +#define BIT_GET_HPQ(x) (((x) >> BIT_SHIFT_HPQ) & BIT_MASK_HPQ) +#define BIT_SET_HPQ(x, v) (BIT_CLEAR_HPQ(x) | BIT_HPQ(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ +#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0 +#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff +#define BIT_TX_OQT_NL_FREE_SPACE_V1(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) +#define BITS_TX_OQT_NL_FREE_SPACE_V1 \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x) \ + ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) +#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x) | BIT_TX_OQT_NL_FREE_SPACE_V1(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif -#define BIT_USB_RXDMA_AGG_EN BIT(31) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_BCN_CTRL_0 (Offset 0x0200) */ +#define BIT_SHIFT_BCN0_HEAD 0 +#define BIT_MASK_BCN0_HEAD 0xfff +#define BIT_BCN0_HEAD(x) (((x) & BIT_MASK_BCN0_HEAD) << BIT_SHIFT_BCN0_HEAD) +#define BITS_BCN0_HEAD (BIT_MASK_BCN0_HEAD << BIT_SHIFT_BCN0_HEAD) +#define BIT_CLEAR_BCN0_HEAD(x) ((x) & (~BITS_BCN0_HEAD)) +#define BIT_GET_BCN0_HEAD(x) (((x) >> BIT_SHIFT_BCN0_HEAD) & BIT_MASK_BCN0_HEAD) +#define BIT_SET_BCN0_HEAD(x, v) (BIT_CLEAR_BCN0_HEAD(x) | BIT_BCN0_HEAD(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ -#define BIT_DMA_STORE_MODE BIT(31) -#define BIT_EN_FW_ADD BIT(30) -#define BIT_EN_PRE_CALC BIT(29) -#define BIT_RXAGG_SW_EN BIT(28) +#define BIT_BCN_VALID_1_V1 BIT(31) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ +#define BIT_BCN3_VALID BIT(31) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24 -#define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff -#define BIT_RXDMA_AGG_OLD_MOD(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD) -#define BIT_GET_RXDMA_AGG_OLD_MOD(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD) +/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ +#define BIT_SHIFT_TXPKTNUM 24 +#define BIT_MASK_TXPKTNUM 0xff +#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM) +#define BITS_TXPKTNUM (BIT_MASK_TXPKTNUM << BIT_SHIFT_TXPKTNUM) +#define BIT_CLEAR_TXPKTNUM(x) ((x) & (~BITS_TXPKTNUM)) +#define BIT_GET_TXPKTNUM(x) (((x) >> BIT_SHIFT_TXPKTNUM) & BIT_MASK_TXPKTNUM) +#define BIT_SET_TXPKTNUM(x, v) (BIT_CLEAR_TXPKTNUM(x) | BIT_TXPKTNUM(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ +#define BIT_SHIFT_R_BCN_HEAD_SEL_V1 20 +#define BIT_MASK_R_BCN_HEAD_SEL_V1 0x7 +#define BIT_R_BCN_HEAD_SEL_V1(x) \ + (((x) & BIT_MASK_R_BCN_HEAD_SEL_V1) << BIT_SHIFT_R_BCN_HEAD_SEL_V1) +#define BITS_R_BCN_HEAD_SEL_V1 \ + (BIT_MASK_R_BCN_HEAD_SEL_V1 << BIT_SHIFT_R_BCN_HEAD_SEL_V1) +#define BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) ((x) & (~BITS_R_BCN_HEAD_SEL_V1)) +#define BIT_GET_R_BCN_HEAD_SEL_V1(x) \ + (((x) >> BIT_SHIFT_R_BCN_HEAD_SEL_V1) & BIT_MASK_R_BCN_HEAD_SEL_V1) +#define BIT_SET_R_BCN_HEAD_SEL_V1(x, v) \ + (BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) | BIT_R_BCN_HEAD_SEL_V1(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKT_NUM_WOL 16 -#define BIT_MASK_PKT_NUM_WOL 0xff -#define BIT_PKT_NUM_WOL(x) (((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL) -#define BIT_GET_PKT_NUM_WOL(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL) +/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ +#define BIT_SHIFT_PUBQ_AVAL_PG 16 +#define BIT_MASK_PUBQ_AVAL_PG 0xff +#define BIT_PUBQ_AVAL_PG(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG) << BIT_SHIFT_PUBQ_AVAL_PG) +#define BITS_PUBQ_AVAL_PG (BIT_MASK_PUBQ_AVAL_PG << BIT_SHIFT_PUBQ_AVAL_PG) +#define BIT_CLEAR_PUBQ_AVAL_PG(x) ((x) & (~BITS_PUBQ_AVAL_PG)) +#define BIT_GET_PUBQ_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG) & BIT_MASK_PUBQ_AVAL_PG) +#define BIT_SET_PUBQ_AVAL_PG(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG(x) | BIT_PUBQ_AVAL_PG(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +#define BIT_SHIFT_BCN_HEAD_1_V1 16 +#define BIT_MASK_BCN_HEAD_1_V1 0xfff +#define BIT_BCN_HEAD_1_V1(x) \ + (((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1) +#define BITS_BCN_HEAD_1_V1 (BIT_MASK_BCN_HEAD_1_V1 << BIT_SHIFT_BCN_HEAD_1_V1) +#define BIT_CLEAR_BCN_HEAD_1_V1(x) ((x) & (~BITS_BCN_HEAD_1_V1)) +#define BIT_GET_BCN_HEAD_1_V1(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1) +#define BIT_SET_BCN_HEAD_1_V1(x, v) \ + (BIT_CLEAR_BCN_HEAD_1_V1(x) | BIT_BCN_HEAD_1_V1(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_DMA_AGG_TO_V1 8 -#define BIT_MASK_DMA_AGG_TO_V1 0xff -#define BIT_DMA_AGG_TO_V1(x) (((x) & BIT_MASK_DMA_AGG_TO_V1) << BIT_SHIFT_DMA_AGG_TO_V1) -#define BIT_GET_DMA_AGG_TO_V1(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_V1) & BIT_MASK_DMA_AGG_TO_V1) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ +#define BIT_SHIFT_BCN3_HEAD 16 +#define BIT_MASK_BCN3_HEAD 0xfff +#define BIT_BCN3_HEAD(x) (((x) & BIT_MASK_BCN3_HEAD) << BIT_SHIFT_BCN3_HEAD) +#define BITS_BCN3_HEAD (BIT_MASK_BCN3_HEAD << BIT_SHIFT_BCN3_HEAD) +#define BIT_CLEAR_BCN3_HEAD(x) ((x) & (~BITS_BCN3_HEAD)) +#define BIT_GET_BCN3_HEAD(x) (((x) >> BIT_SHIFT_BCN3_HEAD) & BIT_MASK_BCN3_HEAD) +#define BIT_SET_BCN3_HEAD(x, v) (BIT_CLEAR_BCN3_HEAD(x) | BIT_BCN3_HEAD(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +#define BIT_BCN_VALID_V1 BIT(15) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH 8 -#define BIT_MASK_RXDMA_AGG_TIMEOUT_TH 0xff -#define BIT_RXDMA_AGG_TIMEOUT_TH(x) (((x) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH) << BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH) -#define BIT_GET_RXDMA_AGG_TIMEOUT_TH(x) (((x) >> BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ +#define BIT_BCN2_VALID BIT(15) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ +#define BIT_SHIFT_LPQ_AVAL_PG 8 +#define BIT_MASK_LPQ_AVAL_PG 0xff +#define BIT_LPQ_AVAL_PG(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG) << BIT_SHIFT_LPQ_AVAL_PG) +#define BITS_LPQ_AVAL_PG (BIT_MASK_LPQ_AVAL_PG << BIT_SHIFT_LPQ_AVAL_PG) +#define BIT_CLEAR_LPQ_AVAL_PG(x) ((x) & (~BITS_LPQ_AVAL_PG)) +#define BIT_GET_LPQ_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG) & BIT_MASK_LPQ_AVAL_PG) +#define BIT_SET_LPQ_AVAL_PG(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG(x) | BIT_LPQ_AVAL_PG(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_DMA_AGG_TO 8 -#define BIT_MASK_DMA_AGG_TO 0xf -#define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO) -#define BIT_GET_DMA_AGG_TO(x) (((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ +#define BIT_TDE_ERROR_STOP BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */ +#define BIT_SHIFT_HPQ_AVAL_PG 0 +#define BIT_MASK_HPQ_AVAL_PG 0xff +#define BIT_HPQ_AVAL_PG(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG) << BIT_SHIFT_HPQ_AVAL_PG) +#define BITS_HPQ_AVAL_PG (BIT_MASK_HPQ_AVAL_PG << BIT_SHIFT_HPQ_AVAL_PG) +#define BIT_CLEAR_HPQ_AVAL_PG(x) ((x) & (~BITS_HPQ_AVAL_PG)) +#define BIT_GET_HPQ_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG) & BIT_MASK_HPQ_AVAL_PG) +#define BIT_SET_HPQ_AVAL_PG(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG(x) | BIT_HPQ_AVAL_PG(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0 -#define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf -#define BIT_RXDMA_AGG_PG_TH_V1(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1) -#define BIT_GET_RXDMA_AGG_PG_TH_V1(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1) +/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ +#define BIT_SHIFT_BCN_HEAD_V1 0 +#define BIT_MASK_BCN_HEAD_V1 0xfff +#define BIT_BCN_HEAD_V1(x) \ + (((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1) +#define BITS_BCN_HEAD_V1 (BIT_MASK_BCN_HEAD_V1 << BIT_SHIFT_BCN_HEAD_V1) +#define BIT_CLEAR_BCN_HEAD_V1(x) ((x) & (~BITS_BCN_HEAD_V1)) +#define BIT_GET_BCN_HEAD_V1(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1) +#define BIT_SET_BCN_HEAD_V1(x, v) \ + (BIT_CLEAR_BCN_HEAD_V1(x) | BIT_BCN_HEAD_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */ +#define BIT_SHIFT_BCN2_HEAD 0 +#define BIT_MASK_BCN2_HEAD 0xfff +#define BIT_BCN2_HEAD(x) (((x) & BIT_MASK_BCN2_HEAD) << BIT_SHIFT_BCN2_HEAD) +#define BITS_BCN2_HEAD (BIT_MASK_BCN2_HEAD << BIT_SHIFT_BCN2_HEAD) +#define BIT_CLEAR_BCN2_HEAD(x) ((x) & (~BITS_BCN2_HEAD)) +#define BIT_GET_BCN2_HEAD(x) (((x) >> BIT_SHIFT_BCN2_HEAD) & BIT_MASK_BCN2_HEAD) +#define BIT_SET_BCN2_HEAD(x, v) (BIT_CLEAR_BCN2_HEAD(x) | BIT_BCN2_HEAD(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RXDMA_AGG_PG_TH 0 -#define BIT_MASK_RXDMA_AGG_PG_TH 0xff -#define BIT_RXDMA_AGG_PG_TH(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH) << BIT_SHIFT_RXDMA_AGG_PG_TH) -#define BIT_GET_RXDMA_AGG_PG_TH(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH) & BIT_MASK_RXDMA_AGG_PG_TH) +/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ +#define BIT_SHIFT_LLT_FREE_PAGE 24 +#define BIT_MASK_LLT_FREE_PAGE 0xff +#define BIT_LLT_FREE_PAGE(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE) << BIT_SHIFT_LLT_FREE_PAGE) +#define BITS_LLT_FREE_PAGE (BIT_MASK_LLT_FREE_PAGE << BIT_SHIFT_LLT_FREE_PAGE) +#define BIT_CLEAR_LLT_FREE_PAGE(x) ((x) & (~BITS_LLT_FREE_PAGE)) +#define BIT_GET_LLT_FREE_PAGE(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE) & BIT_MASK_LLT_FREE_PAGE) +#define BIT_SET_LLT_FREE_PAGE(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE(x) | BIT_LLT_FREE_PAGE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24 +#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) +#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 \ + (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) +#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ + ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) & \ + BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) +#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) | \ + BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(v)) -/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXDMA_AGG_PG_TH_V2 0 -#define BIT_MASK_RXDMA_AGG_PG_TH_V2 0xff -#define BIT_RXDMA_AGG_PG_TH_V2(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V2) << BIT_SHIFT_RXDMA_AGG_PG_TH_V2) -#define BIT_GET_RXDMA_AGG_PG_TH_V2(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V2) & BIT_MASK_RXDMA_AGG_PG_TH_V2) +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_SHIFT_MAX_TX_PKT_V1 24 +#define BIT_MASK_MAX_TX_PKT_V1 0xff +#define BIT_MAX_TX_PKT_V1(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_V1) << BIT_SHIFT_MAX_TX_PKT_V1) +#define BITS_MAX_TX_PKT_V1 (BIT_MASK_MAX_TX_PKT_V1 << BIT_SHIFT_MAX_TX_PKT_V1) +#define BIT_CLEAR_MAX_TX_PKT_V1(x) ((x) & (~BITS_MAX_TX_PKT_V1)) +#define BIT_GET_MAX_TX_PKT_V1(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_V1) & BIT_MASK_MAX_TX_PKT_V1) +#define BIT_SET_MAX_TX_PKT_V1(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_V1(x) | BIT_MAX_TX_PKT_V1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_TDE_ERROR_STOP_V1 BIT(23) -/* 2 REG_RXPKT_NUM (Offset 0x0284) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RXPKT_NUM 24 -#define BIT_MASK_RXPKT_NUM 0xff -#define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM) -#define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM) +/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ + +#define BIT_BCN_VALID BIT(16) +#define BIT_SHIFT_BCN_HEAD 8 +#define BIT_MASK_BCN_HEAD 0xff +#define BIT_BCN_HEAD(x) (((x) & BIT_MASK_BCN_HEAD) << BIT_SHIFT_BCN_HEAD) +#define BITS_BCN_HEAD (BIT_MASK_BCN_HEAD << BIT_SHIFT_BCN_HEAD) +#define BIT_CLEAR_BCN_HEAD(x) ((x) & (~BITS_BCN_HEAD)) +#define BIT_GET_BCN_HEAD(x) (((x) >> BIT_SHIFT_BCN_HEAD) & BIT_MASK_BCN_HEAD) +#define BIT_SET_BCN_HEAD(x, v) (BIT_CLEAR_BCN_HEAD(x) | BIT_BCN_HEAD(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_SHIFT_LLT_FREE_PAGE_V1 8 +#define BIT_MASK_LLT_FREE_PAGE_V1 0xffff +#define BIT_LLT_FREE_PAGE_V1(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1) +#define BITS_LLT_FREE_PAGE_V1 \ + (BIT_MASK_LLT_FREE_PAGE_V1 << BIT_SHIFT_LLT_FREE_PAGE_V1) +#define BIT_CLEAR_LLT_FREE_PAGE_V1(x) ((x) & (~BITS_LLT_FREE_PAGE_V1)) +#define BIT_GET_LLT_FREE_PAGE_V1(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1) +#define BIT_SET_LLT_FREE_PAGE_V1(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V1(x) | BIT_LLT_FREE_PAGE_V1(v)) -/* 2 REG_RXPKT_NUM (Offset 0x0284) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20 -#define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf -#define BIT_FW_UPD_RDPTR19_TO_16(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16) -#define BIT_GET_FW_UPD_RDPTR19_TO_16(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) & BIT_MASK_FW_UPD_RDPTR19_TO_16) +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_SHIFT_LLT_FREE_PAGE_V2 8 +#define BIT_MASK_LLT_FREE_PAGE_V2 0xfff +#define BIT_LLT_FREE_PAGE_V2(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V2) << BIT_SHIFT_LLT_FREE_PAGE_V2) +#define BITS_LLT_FREE_PAGE_V2 \ + (BIT_MASK_LLT_FREE_PAGE_V2 << BIT_SHIFT_LLT_FREE_PAGE_V2) +#define BIT_CLEAR_LLT_FREE_PAGE_V2(x) ((x) & (~BITS_LLT_FREE_PAGE_V2)) +#define BIT_GET_LLT_FREE_PAGE_V2(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2) & BIT_MASK_LLT_FREE_PAGE_V2) +#define BIT_SET_LLT_FREE_PAGE_V2(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V2(x) | BIT_LLT_FREE_PAGE_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_SHIFT_BLK_DESC_NUM 4 +#define BIT_MASK_BLK_DESC_NUM 0xf +#define BIT_BLK_DESC_NUM(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM) +#define BITS_BLK_DESC_NUM (BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM) +#define BIT_CLEAR_BLK_DESC_NUM(x) ((x) & (~BITS_BLK_DESC_NUM)) +#define BIT_GET_BLK_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM) +#define BIT_SET_BLK_DESC_NUM(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM(x) | BIT_BLK_DESC_NUM(v)) -/* 2 REG_RXPKT_NUM (Offset 0x0284) */ +#endif -#define BIT_RXDMA_REQ BIT(19) -#define BIT_RW_RELEASE_EN BIT(18) -#define BIT_RXDMA_IDLE BIT(17) -#define BIT_RXPKT_RELEASE_POLL BIT(16) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FW_UPD_RDPTR 0 -#define BIT_MASK_FW_UPD_RDPTR 0xffff -#define BIT_FW_UPD_RDPTR(x) (((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR) -#define BIT_GET_FW_UPD_RDPTR(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR) +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_R_BCN_HEAD_SEL BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ -#define BIT_FC2H_PKT_OVERFLOW BIT(8) +#define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2) +#define BIT_LLT_DBG_SEL BIT(1) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ +#define BIT_BLK_DESC_OPT BIT(0) -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#endif -#define BIT_C2H_PKT_OVF BIT(7) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ +#define BIT_AUTO_INIT_LLT_V1 BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -#define BIT_AGG_CFG_ISSUE BIT(6) +#define BIT_EM_CHKSUM_FIN BIT(31) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_EN_CHKSUM_ERR_FIN BIT(31) -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#endif -#define BIT_AGG_CONFGI_ISSUE BIT(6) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_EMN_PCIE_DMA_MOD BIT(30) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -#define BIT_FW_POLL_ISSUE BIT(5) -#define BIT_RX_DATA_UDN BIT(4) -#define BIT_RX_SFF_UDN BIT(3) -#define BIT_RX_SFF_OVF BIT(2) +#define BIT_EN_PCIE_DMA_MOD BIT(30) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_EN_TXQUE_CLR BIT(29) +#define BIT_EN_PCIE_FIFO_MODE BIT(28) -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#endif -#define BIT_USB_REQ_LEN_OVF BIT(1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_SHIFT_PG_UNDER_TH 16 +#define BIT_MASK_PG_UNDER_TH 0xff +#define BIT_PG_UNDER_TH(x) \ + (((x) & BIT_MASK_PG_UNDER_TH) << BIT_SHIFT_PG_UNDER_TH) +#define BITS_PG_UNDER_TH (BIT_MASK_PG_UNDER_TH << BIT_SHIFT_PG_UNDER_TH) +#define BIT_CLEAR_PG_UNDER_TH(x) ((x) & (~BITS_PG_UNDER_TH)) +#define BIT_GET_PG_UNDER_TH(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH) & BIT_MASK_PG_UNDER_TH) +#define BIT_SET_PG_UNDER_TH(x, v) \ + (BIT_CLEAR_PG_UNDER_TH(x) | BIT_PG_UNDER_TH(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -#define BIT_RXPKT_OVF BIT(0) +#define BIT_SHIFT_PG_UNDER_TH_V2 16 +#define BIT_MASK_PG_UNDER_TH_V2 0xff +#define BIT_PG_UNDER_TH_V2(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V2) << BIT_SHIFT_PG_UNDER_TH_V2) +#define BITS_PG_UNDER_TH_V2 \ + (BIT_MASK_PG_UNDER_TH_V2 << BIT_SHIFT_PG_UNDER_TH_V2) +#define BIT_CLEAR_PG_UNDER_TH_V2(x) ((x) & (~BITS_PG_UNDER_TH_V2)) +#define BIT_GET_PG_UNDER_TH_V2(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V2) & BIT_MASK_PG_UNDER_TH_V2) +#define BIT_SET_PG_UNDER_TH_V2(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V2(x) | BIT_PG_UNDER_TH_V2(v)) -/* 2 REG_RXDMA_DPR (Offset 0x028C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RDE_DEBUG 0 -#define BIT_MASK_RDE_DEBUG 0xffffffffL -#define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG) -#define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG) +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_SHIFT_PG_UNDER_TH_V1 16 +#define BIT_MASK_PG_UNDER_TH_V1 0xfff +#define BIT_PG_UNDER_TH_V1(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1) +#define BITS_PG_UNDER_TH_V1 \ + (BIT_MASK_PG_UNDER_TH_V1 << BIT_SHIFT_PG_UNDER_TH_V1) +#define BIT_CLEAR_PG_UNDER_TH_V1(x) ((x) & (~BITS_PG_UNDER_TH_V1)) +#define BIT_GET_PG_UNDER_TH_V1(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1) +#define BIT_SET_PG_UNDER_TH_V1(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1(x) | BIT_PG_UNDER_TH_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_EN_RESTORE_H2C_BY_RST BIT(15) -/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#endif +#if (HALMAC_8197F_SUPPORT) -#define BIT_SHIFT_PKTNUM_TH_V2 24 -#define BIT_MASK_PKTNUM_TH_V2 0x1f -#define BIT_PKTNUM_TH_V2(x) (((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2) -#define BIT_GET_PKTNUM_TH_V2(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2) +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -#define BIT_TXBA_BREAK_USBAGG BIT(23) +#define BIT_EN_RESET_RESTORE_H2C BIT(15) -#define BIT_SHIFT_PKTLEN_PARA 16 -#define BIT_MASK_PKTLEN_PARA 0x7 -#define BIT_PKTLEN_PARA(x) (((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA) -#define BIT_GET_PKTLEN_PARA(x) (((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ +#define BIT_R_EN_RESET_RESTORE_H2C BIT(15) -#if (HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8822B_SUPPORT) -/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -#define BIT_GRAYCODE_SYNC_WITH_BIN BIT(8) +#define BIT_RESTORE_H2C_ADDRESS BIT(15) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_SDIO_TDE_FINISH BIT(14) +#endif -#define BIT_SHIFT_BURST_SIZE 4 -#define BIT_MASK_BURST_SIZE 0x3 -#define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE) -#define BIT_GET_BURST_SIZE(x) (((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ -#define BIT_SHIFT_BURST_CNT 2 -#define BIT_MASK_BURST_CNT 0x3 -#define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT) -#define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT) +#define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13) +#define BIT_RST_RDPTR BIT(12) +#define BIT_RST_WRPTR BIT(11) +#define BIT_CHK_PG_TH_EN BIT(10) +#define BIT_DROP_DATA_EN BIT(9) +#define BIT_CHECK_OFFSET_EN BIT(8) +#define BIT_SHIFT_CHECK_OFFSET 0 +#define BIT_MASK_CHECK_OFFSET 0xff +#define BIT_CHECK_OFFSET(x) \ + (((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET) +#define BITS_CHECK_OFFSET (BIT_MASK_CHECK_OFFSET << BIT_SHIFT_CHECK_OFFSET) +#define BIT_CLEAR_CHECK_OFFSET(x) ((x) & (~BITS_CHECK_OFFSET)) +#define BIT_GET_CHECK_OFFSET(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET) +#define BIT_SET_CHECK_OFFSET(x, v) \ + (BIT_CLEAR_CHECK_OFFSET(x) | BIT_CHECK_OFFSET(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ -#define BIT_DAM_MODE BIT(1) +#define BIT_LD_RQPN BIT(31) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_AMSDU_PKT_SIZE_ERR BIT(31) +#define BIT_AMSDU_EN_ERR BIT(30) +#define BIT_CHKSUM_AMSDU_EN_ERR BIT(29) +#define BIT_TXPKTBF_REQ_ERR BIT(28) +#define BIT_OQT_UDN_16 BIT(27) +#define BIT_OQT_OVF_16 BIT(26) +#define BIT_OQT_UDN_14_15 BIT(25) +#define BIT_OQT_OVF_14_15 BIT(24) +#define BIT_OQT_UDN_13 BIT(23) +#define BIT_OQT_OVF_13 BIT(22) +#define BIT_OQT_UDN_12 BIT(21) +#define BIT_OQT_OVF_12 BIT(20) +#define BIT_OQT_UDN_8_11 BIT(19) -/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#endif -#define BIT_DMA_MODE BIT(1) +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXPKTBUF_REQ_ERR BIT(18) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_C2H_PKT (Offset 0x0294) */ +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_OQT_OVF_8_11 BIT(18) -#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24 -#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf -#define BIT_R_C2H_STR_ADDR_16_TO_19(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) -#define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MDIO_PHY_ADDR 24 -#define BIT_MASK_MDIO_PHY_ADDR 0x1f -#define BIT_MDIO_PHY_ADDR(x) (((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR) -#define BIT_GET_MDIO_PHY_ADDR(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_HI_OQT_UDN BIT(17) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_OQT_UDN_4_7 BIT(17) -/* 2 REG_C2H_PKT (Offset 0x0294) */ +#endif -#define BIT_R_C2H_PKT_REQ BIT(16) -#define BIT_RX_CLOSE_EN BIT(15) -#define BIT_STOP_BCNQ BIT(14) -#define BIT_STOP_MGQ BIT(13) -#define BIT_STOP_VOQ BIT(12) -#define BIT_STOP_VIQ BIT(11) -#define BIT_STOP_BEQ BIT(10) -#define BIT_STOP_BKQ BIT(9) -#define BIT_STOP_RXQ BIT(8) -#define BIT_STOP_HI7Q BIT(7) -#define BIT_STOP_HI6Q BIT(6) -#define BIT_STOP_HI5Q BIT(5) -#define BIT_STOP_HI4Q BIT(4) -#define BIT_STOP_HI3Q BIT(3) -#define BIT_STOP_HI2Q BIT(2) -#define BIT_STOP_HI1Q BIT(1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_C2H_STR_ADDR 0 -#define BIT_MASK_R_C2H_STR_ADDR 0xffff -#define BIT_R_C2H_STR_ADDR(x) (((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR) -#define BIT_GET_R_C2H_STR_ADDR(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ -#define BIT_STOP_HI0Q BIT(0) +#define BIT_HI_OQT_OVF BIT(16) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FWFF_C2H (Offset 0x0298) */ +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_OQT_OVF_4_7 BIT(16) -#define BIT_SHIFT_C2H_DMA_ADDR 0 -#define BIT_MASK_C2H_DMA_ADDR 0x3ffff -#define BIT_C2H_DMA_ADDR(x) (((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR) -#define BIT_GET_C2H_DMA_ADDR(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWFF_CTRL (Offset 0x029C) */ +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ -#define BIT_FWFF_DMAPKT_REQ BIT(31) +#define BIT_PAYLOAD_CHKSUM_ERR BIT(15) -#define BIT_SHIFT_FWFF_DMA_PKT_NUM 16 -#define BIT_MASK_FWFF_DMA_PKT_NUM 0xff -#define BIT_FWFF_DMA_PKT_NUM(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM) -#define BIT_GET_FWFF_DMA_PKT_NUM(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FWFF_STR_ADDR 0 -#define BIT_MASK_FWFF_STR_ADDR 0xffff -#define BIT_FWFF_STR_ADDR(x) (((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR) -#define BIT_GET_FWFF_STR_ADDR(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_RX_CLOSE_EN BIT(15) -/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FWFF_PKT_QUEUED 16 -#define BIT_MASK_FWFF_PKT_QUEUED 0xff -#define BIT_FWFF_PKT_QUEUED(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED) -#define BIT_GET_FWFF_PKT_QUEUED(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_PAYLOAD_UDN BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_BCNQ BIT(14) -/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FWFF_PKT_STR_ADDR 0 -#define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff -#define BIT_FWFF_PKT_STR_ADDR(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR) -#define BIT_GET_FWFF_PKT_STR_ADDR(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_PAYLOAD_OVF BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_MGQ BIT(13) -/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V1 0 -#define BIT_MASK_FWFF_PKT_STR_ADDR_V1 0x7ff -#define BIT_FWFF_PKT_STR_ADDR_V1(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V1) << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) -#define BIT_GET_FWFF_PKT_STR_ADDR_V1(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) & BIT_MASK_FWFF_PKT_STR_ADDR_V1) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_DSC_CHKSUM_FAIL BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_VOQ BIT(12) +#define BIT_UNKNOWN_QSEL BIT(11) +#define BIT_STOP_VIQ BIT(11) -/* 2 REG_FC2H_INFO (Offset 0x02A6) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FC2H_STR_ADDR 17 -#define BIT_MASK_FC2H_STR_ADDR 0x7fff -#define BIT_FC2H_STR_ADDR(x) (((x) & BIT_MASK_FC2H_STR_ADDR) << BIT_SHIFT_FC2H_STR_ADDR) -#define BIT_GET_FC2H_STR_ADDR(x) (((x) >> BIT_SHIFT_FC2H_STR_ADDR) & BIT_MASK_FC2H_STR_ADDR) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ -#define BIT_FC2H_PKT_REQ BIT(16) +#define BIT_EP_QSEL_DIFF BIT(10) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_BEQ BIT(10) -/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#endif -#define BIT_PCIEIO_PERSTB_SEL BIT(31) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TX_OFFS_UNMATCH BIT(9) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_HCI_CTRL (Offset 0x0300) */ +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ -#define BIT_HCIIO_PERSTB_SEL BIT(31) +#define BIT_STOP_BKQ BIT(9) +#define BIT_TXOQT_UDN BIT(8) +#define BIT_STOP_RXQ BIT(8) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXOQT_UDN_0_3 BIT(8) -/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PCIE_MAX_RXDMA 28 -#define BIT_MASK_PCIE_MAX_RXDMA 0x7 -#define BIT_PCIE_MAX_RXDMA(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA) -#define BIT_GET_PCIE_MAX_RXDMA(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXOQT_OVF BIT(7) +#define BIT_STOP_HI7Q BIT(7) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXOQT_OVF_0_3 BIT(7) -/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HCI_MAX_RXDMA 28 -#define BIT_MASK_HCI_MAX_RXDMA 0x7 -#define BIT_HCI_MAX_RXDMA(x) (((x) & BIT_MASK_HCI_MAX_RXDMA) << BIT_SHIFT_HCI_MAX_RXDMA) -#define BIT_GET_HCI_MAX_RXDMA(x) (((x) >> BIT_SHIFT_HCI_MAX_RXDMA) & BIT_MASK_HCI_MAX_RXDMA) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXDMA_SFF_UDN BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI6Q BIT(6) -/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ -#define BIT_RX_LIT_EDN_SEL BIT(27) -#define BIT_TX_LIT_EDN_SEL BIT(26) -#define BIT_WT_LIT_EDN BIT(25) +#define BIT_TXDMA_SFF_OVF BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI5Q BIT(5) -/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PCIE_MAX_TXDMA 24 -#define BIT_MASK_PCIE_MAX_TXDMA 0x7 -#define BIT_PCIE_MAX_TXDMA(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA) -#define BIT_GET_PCIE_MAX_TXDMA(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_LLT_NULL_PG BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI4Q BIT(4) -/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HCI_MAX_TXDMA 24 -#define BIT_MASK_HCI_MAX_TXDMA 0x7 -#define BIT_HCI_MAX_TXDMA(x) (((x) & BIT_MASK_HCI_MAX_TXDMA) << BIT_SHIFT_HCI_MAX_TXDMA) -#define BIT_GET_HCI_MAX_TXDMA(x) (((x) >> BIT_SHIFT_HCI_MAX_TXDMA) & BIT_MASK_HCI_MAX_TXDMA) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_PAGE_UDN BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI3Q BIT(3) -/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#endif -#define BIT_RD_LITT_EDN BIT(24) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_PAGE_OVF BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ -#define BIT_PCIE_RST_TRXDMA_INTF BIT(20) +#define BIT_STOP_HI2Q BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXFF_PG_UDN BIT(1) -/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_HCI_RST_TRXDMA_INTF BIT(20) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ + +#define BIT_STOP_HI1Q BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_TXFF_PG_OVF BIT(0) -/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MAX_RXDMA 20 -#define BIT_MASK_MAX_RXDMA 0x7 -#define BIT_MAX_RXDMA(x) (((x) & BIT_MASK_MAX_RXDMA) << BIT_SHIFT_MAX_RXDMA) -#define BIT_GET_MAX_RXDMA(x) (((x) >> BIT_SHIFT_MAX_RXDMA) & BIT_MASK_MAX_RXDMA) +/* 2 REG_TXDMA_STATUS (Offset 0x0210) */ +#define BIT_STOP_HI0Q BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RQPN_NPQ (Offset 0x0214) */ +#define BIT_SHIFT_EXQ_AVAL_PG 24 +#define BIT_MASK_EXQ_AVAL_PG 0xff +#define BIT_EXQ_AVAL_PG(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG) << BIT_SHIFT_EXQ_AVAL_PG) +#define BITS_EXQ_AVAL_PG (BIT_MASK_EXQ_AVAL_PG << BIT_SHIFT_EXQ_AVAL_PG) +#define BIT_CLEAR_EXQ_AVAL_PG(x) ((x) & (~BITS_EXQ_AVAL_PG)) +#define BIT_GET_EXQ_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG) & BIT_MASK_EXQ_AVAL_PG) +#define BIT_SET_EXQ_AVAL_PG(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG(x) | BIT_EXQ_AVAL_PG(v)) + +#define BIT_SHIFT_EXQ 16 +#define BIT_MASK_EXQ 0xff +#define BIT_EXQ(x) (((x) & BIT_MASK_EXQ) << BIT_SHIFT_EXQ) +#define BITS_EXQ (BIT_MASK_EXQ << BIT_SHIFT_EXQ) +#define BIT_CLEAR_EXQ(x) ((x) & (~BITS_EXQ)) +#define BIT_GET_EXQ(x) (((x) >> BIT_SHIFT_EXQ) & BIT_MASK_EXQ) +#define BIT_SET_EXQ(x, v) (BIT_CLEAR_EXQ(x) | BIT_EXQ(v)) + +#define BIT_SHIFT_NPQ 0 +#define BIT_MASK_NPQ 0xff +#define BIT_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ) +#define BITS_NPQ (BIT_MASK_NPQ << BIT_SHIFT_NPQ) +#define BIT_CLEAR_NPQ(x) ((x) & (~BITS_NPQ)) +#define BIT_GET_NPQ(x) (((x) >> BIT_SHIFT_NPQ) & BIT_MASK_NPQ) +#define BIT_SET_NPQ(x, v) (BIT_CLEAR_NPQ(x) | BIT_NPQ(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +/* 2 REG_TQPNT1 (Offset 0x0218) */ -#define BIT_PCIE_EN_SWENT_L23 BIT(17) +#define BIT_HPQ_INT_EN BIT(31) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_TQPNT1 (Offset 0x0218) */ -/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_SHIFT_NPQ_HIGH_TH 24 +#define BIT_MASK_NPQ_HIGH_TH 0xff +#define BIT_NPQ_HIGH_TH(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH) << BIT_SHIFT_NPQ_HIGH_TH) +#define BITS_NPQ_HIGH_TH (BIT_MASK_NPQ_HIGH_TH << BIT_SHIFT_NPQ_HIGH_TH) +#define BIT_CLEAR_NPQ_HIGH_TH(x) ((x) & (~BITS_NPQ_HIGH_TH)) +#define BIT_GET_NPQ_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH) & BIT_MASK_NPQ_HIGH_TH) +#define BIT_SET_NPQ_HIGH_TH(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH(x) | BIT_NPQ_HIGH_TH(v)) -#define BIT_HCI_EN_SWENT_L23 BIT(17) +#define BIT_SHIFT_NPQ_LOW_TH 16 +#define BIT_MASK_NPQ_LOW_TH 0xff +#define BIT_NPQ_LOW_TH(x) (((x) & BIT_MASK_NPQ_LOW_TH) << BIT_SHIFT_NPQ_LOW_TH) +#define BITS_NPQ_LOW_TH (BIT_MASK_NPQ_LOW_TH << BIT_SHIFT_NPQ_LOW_TH) +#define BIT_CLEAR_NPQ_LOW_TH(x) ((x) & (~BITS_NPQ_LOW_TH)) +#define BIT_GET_NPQ_LOW_TH(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH) & BIT_MASK_NPQ_LOW_TH) +#define BIT_SET_NPQ_LOW_TH(x, v) (BIT_CLEAR_NPQ_LOW_TH(x) | BIT_NPQ_LOW_TH(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TQPNT1 (Offset 0x0218) */ +#define BIT_SHIFT_HPQ_HIGH_TH_V1 16 +#define BIT_MASK_HPQ_HIGH_TH_V1 0xfff +#define BIT_HPQ_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1) +#define BITS_HPQ_HIGH_TH_V1 \ + (BIT_MASK_HPQ_HIGH_TH_V1 << BIT_SHIFT_HPQ_HIGH_TH_V1) +#define BIT_CLEAR_HPQ_HIGH_TH_V1(x) ((x) & (~BITS_HPQ_HIGH_TH_V1)) +#define BIT_GET_HPQ_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1) +#define BIT_SET_HPQ_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH_V1(x) | BIT_HPQ_HIGH_TH_V1(v)) -/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#endif -#define BIT_PCIE_EN_HWEXT_L1 BIT(16) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_DMA_RQPN_INFO_PUB (Offset 0x0218) */ +#define BIT_SHIFT_PUB_AVAL_PG 16 +#define BIT_MASK_PUB_AVAL_PG 0xfff +#define BIT_PUB_AVAL_PG(x) \ + (((x) & BIT_MASK_PUB_AVAL_PG) << BIT_SHIFT_PUB_AVAL_PG) +#define BITS_PUB_AVAL_PG (BIT_MASK_PUB_AVAL_PG << BIT_SHIFT_PUB_AVAL_PG) +#define BIT_CLEAR_PUB_AVAL_PG(x) ((x) & (~BITS_PUB_AVAL_PG)) +#define BIT_GET_PUB_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_PUB_AVAL_PG) & BIT_MASK_PUB_AVAL_PG) +#define BIT_SET_PUB_AVAL_PG(x, v) \ + (BIT_CLEAR_PUB_AVAL_PG(x) | BIT_PUB_AVAL_PG(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_HCI_CTRL (Offset 0x0300) */ +/* 2 REG_TQPNT1 (Offset 0x0218) */ -#define BIT_HCI_EN_HWEXT_L1 BIT(16) +#define BIT_SHIFT_HPQ_HIGH_TH 8 +#define BIT_MASK_HPQ_HIGH_TH 0xff +#define BIT_HPQ_HIGH_TH(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH) << BIT_SHIFT_HPQ_HIGH_TH) +#define BITS_HPQ_HIGH_TH (BIT_MASK_HPQ_HIGH_TH << BIT_SHIFT_HPQ_HIGH_TH) +#define BIT_CLEAR_HPQ_HIGH_TH(x) ((x) & (~BITS_HPQ_HIGH_TH)) +#define BIT_GET_HPQ_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH) & BIT_MASK_HPQ_HIGH_TH) +#define BIT_SET_HPQ_HIGH_TH(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH(x) | BIT_HPQ_HIGH_TH(v)) + +#define BIT_SHIFT_HPQ_LOW_TH 0 +#define BIT_MASK_HPQ_LOW_TH 0xff +#define BIT_HPQ_LOW_TH(x) (((x) & BIT_MASK_HPQ_LOW_TH) << BIT_SHIFT_HPQ_LOW_TH) +#define BITS_HPQ_LOW_TH (BIT_MASK_HPQ_LOW_TH << BIT_SHIFT_HPQ_LOW_TH) +#define BIT_CLEAR_HPQ_LOW_TH(x) ((x) & (~BITS_HPQ_LOW_TH)) +#define BIT_GET_HPQ_LOW_TH(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH) & BIT_MASK_HPQ_LOW_TH) +#define BIT_SET_HPQ_LOW_TH(x, v) (BIT_CLEAR_HPQ_LOW_TH(x) | BIT_HPQ_LOW_TH(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_TQPNT1 (Offset 0x0218) */ +#define BIT_SHIFT_HPQ_LOW_TH_V1 0 +#define BIT_MASK_HPQ_LOW_TH_V1 0xfff +#define BIT_HPQ_LOW_TH_V1(x) \ + (((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1) +#define BITS_HPQ_LOW_TH_V1 (BIT_MASK_HPQ_LOW_TH_V1 << BIT_SHIFT_HPQ_LOW_TH_V1) +#define BIT_CLEAR_HPQ_LOW_TH_V1(x) ((x) & (~BITS_HPQ_LOW_TH_V1)) +#define BIT_GET_HPQ_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1) +#define BIT_SET_HPQ_LOW_TH_V1(x, v) \ + (BIT_CLEAR_HPQ_LOW_TH_V1(x) | BIT_HPQ_LOW_TH_V1(v)) -/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MAX_TXDMA 16 -#define BIT_MASK_MAX_TXDMA 0x7 -#define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA) -#define BIT_GET_MAX_TXDMA(x) (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA) +/* 2 REG_DMA_RQPN_INFO_PUB (Offset 0x0218) */ +#define BIT_SHIFT_PUB_RSVD_PG 0 +#define BIT_MASK_PUB_RSVD_PG 0xfff +#define BIT_PUB_RSVD_PG(x) \ + (((x) & BIT_MASK_PUB_RSVD_PG) << BIT_SHIFT_PUB_RSVD_PG) +#define BITS_PUB_RSVD_PG (BIT_MASK_PUB_RSVD_PG << BIT_SHIFT_PUB_RSVD_PG) +#define BIT_CLEAR_PUB_RSVD_PG(x) ((x) & (~BITS_PUB_RSVD_PG)) +#define BIT_GET_PUB_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_PUB_RSVD_PG) & BIT_MASK_PUB_RSVD_PG) +#define BIT_SET_PUB_RSVD_PG(x, v) \ + (BIT_CLEAR_PUB_RSVD_PG(x) | BIT_PUB_RSVD_PG(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TQPNT2 (Offset 0x021C) */ +#define BIT_NPQ_INT_EN BIT(31) -/* 2 REG_INT_MIG (Offset 0x0304) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TXTTIMER_MATCH_NUM 28 -#define BIT_MASK_TXTTIMER_MATCH_NUM 0xf -#define BIT_TXTTIMER_MATCH_NUM(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM) -#define BIT_GET_TXTTIMER_MATCH_NUM(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM) +/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ +#define BIT_LD_RQPN_V1 BIT(31) -#define BIT_SHIFT_TXPKT_NUM_MATCH 24 -#define BIT_MASK_TXPKT_NUM_MATCH 0xf -#define BIT_TXPKT_NUM_MATCH(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH) -#define BIT_GET_TXPKT_NUM_MATCH(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RXTTIMER_MATCH_NUM 20 -#define BIT_MASK_RXTTIMER_MATCH_NUM 0xf -#define BIT_RXTTIMER_MATCH_NUM(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM) -#define BIT_GET_RXTTIMER_MATCH_NUM(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM) +/* 2 REG_TQPNT2 (Offset 0x021C) */ +#define BIT_SHIFT_EXQ_HIGH_TH 24 +#define BIT_MASK_EXQ_HIGH_TH 0xff +#define BIT_EXQ_HIGH_TH(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH) << BIT_SHIFT_EXQ_HIGH_TH) +#define BITS_EXQ_HIGH_TH (BIT_MASK_EXQ_HIGH_TH << BIT_SHIFT_EXQ_HIGH_TH) +#define BIT_CLEAR_EXQ_HIGH_TH(x) ((x) & (~BITS_EXQ_HIGH_TH)) +#define BIT_GET_EXQ_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH) & BIT_MASK_EXQ_HIGH_TH) +#define BIT_SET_EXQ_HIGH_TH(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH(x) | BIT_EXQ_HIGH_TH(v)) -#define BIT_SHIFT_RXPKT_NUM_MATCH 16 -#define BIT_MASK_RXPKT_NUM_MATCH 0xf -#define BIT_RXPKT_NUM_MATCH(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH) -#define BIT_GET_RXPKT_NUM_MATCH(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH) +#define BIT_SHIFT_EXQ_LOW_TH 16 +#define BIT_MASK_EXQ_LOW_TH 0xff +#define BIT_EXQ_LOW_TH(x) (((x) & BIT_MASK_EXQ_LOW_TH) << BIT_SHIFT_EXQ_LOW_TH) +#define BITS_EXQ_LOW_TH (BIT_MASK_EXQ_LOW_TH << BIT_SHIFT_EXQ_LOW_TH) +#define BIT_CLEAR_EXQ_LOW_TH(x) ((x) & (~BITS_EXQ_LOW_TH)) +#define BIT_GET_EXQ_LOW_TH(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH) & BIT_MASK_EXQ_LOW_TH) +#define BIT_SET_EXQ_LOW_TH(x, v) (BIT_CLEAR_EXQ_LOW_TH(x) | BIT_EXQ_LOW_TH(v)) +#endif -#define BIT_SHIFT_MIGRATE_TIMER 0 -#define BIT_MASK_MIGRATE_TIMER 0xffff -#define BIT_MIGRATE_TIMER(x) (((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER) -#define BIT_GET_MIGRATE_TIMER(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TQPNT2 (Offset 0x021C) */ -/* 2 REG_BCNQ_TXBD_DESA (Offset 0x0308) */ +#define BIT_SHIFT_NPQ_HIGH_TH_V1 16 +#define BIT_MASK_NPQ_HIGH_TH_V1 0xfff +#define BIT_NPQ_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1) +#define BITS_NPQ_HIGH_TH_V1 \ + (BIT_MASK_NPQ_HIGH_TH_V1 << BIT_SHIFT_NPQ_HIGH_TH_V1) +#define BIT_CLEAR_NPQ_HIGH_TH_V1(x) ((x) & (~BITS_NPQ_HIGH_TH_V1)) +#define BIT_GET_NPQ_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1) +#define BIT_SET_NPQ_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH_V1(x) | BIT_NPQ_HIGH_TH_V1(v)) +#endif -#define BIT_SHIFT_BCNQ_TXBD_DESA 0 -#define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_BCNQ_TXBD_DESA(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA) -#define BIT_GET_BCNQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ -/* 2 REG_MGQ_TXBD_DESA (Offset 0x0310) */ +#define BIT_CH16_PUBLIC_DIS BIT(16) +#define BIT_CH15_PUBLIC_DIS BIT(15) +#define BIT_CH14_PUBLIC_DIS BIT(14) +#define BIT_CH13_PUBLIC_DIS BIT(13) +#define BIT_CH12_PUBLIC_DIS BIT(12) +#define BIT_CH11_PUBLIC_DIS BIT(11) +#define BIT_CH10_PUBLIC_DIS BIT(10) +#define BIT_CH9_PUBLIC_DIS BIT(9) +#endif -#define BIT_SHIFT_MGQ_TXBD_DESA 0 -#define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_MGQ_TXBD_DESA(x) (((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA) -#define BIT_GET_MGQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TQPNT2 (Offset 0x021C) */ -/* 2 REG_VOQ_TXBD_DESA (Offset 0x0318) */ +#define BIT_SHIFT_LPQ_HIGH_TH 8 +#define BIT_MASK_LPQ_HIGH_TH 0xff +#define BIT_LPQ_HIGH_TH(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH) << BIT_SHIFT_LPQ_HIGH_TH) +#define BITS_LPQ_HIGH_TH (BIT_MASK_LPQ_HIGH_TH << BIT_SHIFT_LPQ_HIGH_TH) +#define BIT_CLEAR_LPQ_HIGH_TH(x) ((x) & (~BITS_LPQ_HIGH_TH)) +#define BIT_GET_LPQ_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH) & BIT_MASK_LPQ_HIGH_TH) +#define BIT_SET_LPQ_HIGH_TH(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH(x) | BIT_LPQ_HIGH_TH(v)) +#endif -#define BIT_SHIFT_VOQ_TXBD_DESA 0 -#define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_VOQ_TXBD_DESA(x) (((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA) -#define BIT_GET_VOQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ -/* 2 REG_VIQ_TXBD_DESA (Offset 0x0320) */ +#define BIT_CH8_PUBLIC_DIS BIT(8) +#define BIT_CH7_PUBLIC_DIS BIT(7) +#define BIT_CH6_PUBLIC_DIS BIT(6) +#define BIT_CH5_PUBLIC_DIS BIT(5) +#define BIT_CH4_PUBLIC_DIS BIT(4) +#define BIT_CH3_PUBLIC_DIS BIT(3) +#define BIT_CH2_PUBLIC_DIS BIT(2) +#define BIT_CH1_PUBLIC_DIS BIT(1) +#endif -#define BIT_SHIFT_VIQ_TXBD_DESA 0 -#define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_VIQ_TXBD_DESA(x) (((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA) -#define BIT_GET_VIQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TQPNT2 (Offset 0x021C) */ -/* 2 REG_BEQ_TXBD_DESA (Offset 0x0328) */ - - -#define BIT_SHIFT_BEQ_TXBD_DESA 0 -#define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_BEQ_TXBD_DESA(x) (((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA) -#define BIT_GET_BEQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA) +#define BIT_SHIFT_LPQ_LOW_TH 0 +#define BIT_MASK_LPQ_LOW_TH 0xff +#define BIT_LPQ_LOW_TH(x) (((x) & BIT_MASK_LPQ_LOW_TH) << BIT_SHIFT_LPQ_LOW_TH) +#define BITS_LPQ_LOW_TH (BIT_MASK_LPQ_LOW_TH << BIT_SHIFT_LPQ_LOW_TH) +#define BIT_CLEAR_LPQ_LOW_TH(x) ((x) & (~BITS_LPQ_LOW_TH)) +#define BIT_GET_LPQ_LOW_TH(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH) & BIT_MASK_LPQ_LOW_TH) +#define BIT_SET_LPQ_LOW_TH(x, v) (BIT_CLEAR_LPQ_LOW_TH(x) | BIT_LPQ_LOW_TH(v)) +#endif -/* 2 REG_BKQ_TXBD_DESA (Offset 0x0330) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TQPNT2 (Offset 0x021C) */ -#define BIT_SHIFT_BKQ_TXBD_DESA 0 -#define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_BKQ_TXBD_DESA(x) (((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA) -#define BIT_GET_BKQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA) +#define BIT_SHIFT_NPQ_LOW_TH_V1 0 +#define BIT_MASK_NPQ_LOW_TH_V1 0xfff +#define BIT_NPQ_LOW_TH_V1(x) \ + (((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1) +#define BITS_NPQ_LOW_TH_V1 (BIT_MASK_NPQ_LOW_TH_V1 << BIT_SHIFT_NPQ_LOW_TH_V1) +#define BIT_CLEAR_NPQ_LOW_TH_V1(x) ((x) & (~BITS_NPQ_LOW_TH_V1)) +#define BIT_GET_NPQ_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1) +#define BIT_SET_NPQ_LOW_TH_V1(x, v) \ + (BIT_CLEAR_NPQ_LOW_TH_V1(x) | BIT_NPQ_LOW_TH_V1(v)) +#endif -/* 2 REG_RXQ_RXBD_DESA (Offset 0x0338) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */ -#define BIT_SHIFT_RXQ_RXBD_DESA 0 -#define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL -#define BIT_RXQ_RXBD_DESA(x) (((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA) -#define BIT_GET_RXQ_RXBD_DESA(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA) +#define BIT_CH0_PUBLIC_DIS BIT(0) +#endif -/* 2 REG_HI0Q_TXBD_DESA (Offset 0x0340) */ +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TQPNT3 (Offset 0x0220) */ -#define BIT_SHIFT_HI0Q_TXBD_DESA 0 -#define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI0Q_TXBD_DESA(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA) -#define BIT_GET_HI0Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA) +#define BIT_LPQ_INT_EN BIT(31) +#endif -/* 2 REG_HI1Q_TXBD_DESA (Offset 0x0348) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_BCN_CTRL_2 (Offset 0x0220) */ -#define BIT_SHIFT_HI1Q_TXBD_DESA 0 -#define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI1Q_TXBD_DESA(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA) -#define BIT_GET_HI1Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA) +#define BIT_BCN0_EXT_VALID BIT(31) +#endif -/* 2 REG_HI2Q_TXBD_DESA (Offset 0x0350) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TQPNT3 (Offset 0x0220) */ -#define BIT_SHIFT_HI2Q_TXBD_DESA 0 -#define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI2Q_TXBD_DESA(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA) -#define BIT_GET_HI2Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA) +#define BIT_SHIFT_LPQ_HIGH_TH_V1 16 +#define BIT_MASK_LPQ_HIGH_TH_V1 0xfff +#define BIT_LPQ_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1) +#define BITS_LPQ_HIGH_TH_V1 \ + (BIT_MASK_LPQ_HIGH_TH_V1 << BIT_SHIFT_LPQ_HIGH_TH_V1) +#define BIT_CLEAR_LPQ_HIGH_TH_V1(x) ((x) & (~BITS_LPQ_HIGH_TH_V1)) +#define BIT_GET_LPQ_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1) +#define BIT_SET_LPQ_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH_V1(x) | BIT_LPQ_HIGH_TH_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_BCN_CTRL_2 (Offset 0x0220) */ + +#define BIT_SHIFT_BCN0_EXT_HEAD 16 +#define BIT_MASK_BCN0_EXT_HEAD 0xfff +#define BIT_BCN0_EXT_HEAD(x) \ + (((x) & BIT_MASK_BCN0_EXT_HEAD) << BIT_SHIFT_BCN0_EXT_HEAD) +#define BITS_BCN0_EXT_HEAD (BIT_MASK_BCN0_EXT_HEAD << BIT_SHIFT_BCN0_EXT_HEAD) +#define BIT_CLEAR_BCN0_EXT_HEAD(x) ((x) & (~BITS_BCN0_EXT_HEAD)) +#define BIT_GET_BCN0_EXT_HEAD(x) \ + (((x) >> BIT_SHIFT_BCN0_EXT_HEAD) & BIT_MASK_BCN0_EXT_HEAD) +#define BIT_SET_BCN0_EXT_HEAD(x, v) \ + (BIT_CLEAR_BCN0_EXT_HEAD(x) | BIT_BCN0_EXT_HEAD(v)) + +#define BIT_SHIFT_TXPKTNUM_CH4_7 16 +#define BIT_MASK_TXPKTNUM_CH4_7 0xfff +#define BIT_TXPKTNUM_CH4_7(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH4_7) << BIT_SHIFT_TXPKTNUM_CH4_7) +#define BITS_TXPKTNUM_CH4_7 \ + (BIT_MASK_TXPKTNUM_CH4_7 << BIT_SHIFT_TXPKTNUM_CH4_7) +#define BIT_CLEAR_TXPKTNUM_CH4_7(x) ((x) & (~BITS_TXPKTNUM_CH4_7)) +#define BIT_GET_TXPKTNUM_CH4_7(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH4_7) & BIT_MASK_TXPKTNUM_CH4_7) +#define BIT_SET_TXPKTNUM_CH4_7(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH4_7(x) | BIT_TXPKTNUM_CH4_7(v)) + +#define BIT_SHIFT_TXPKTNUM_CH12 16 +#define BIT_MASK_TXPKTNUM_CH12 0xfff +#define BIT_TXPKTNUM_CH12(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH12) << BIT_SHIFT_TXPKTNUM_CH12) +#define BITS_TXPKTNUM_CH12 (BIT_MASK_TXPKTNUM_CH12 << BIT_SHIFT_TXPKTNUM_CH12) +#define BIT_CLEAR_TXPKTNUM_CH12(x) ((x) & (~BITS_TXPKTNUM_CH12)) +#define BIT_GET_TXPKTNUM_CH12(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH12) & BIT_MASK_TXPKTNUM_CH12) +#define BIT_SET_TXPKTNUM_CH12(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH12(x) | BIT_TXPKTNUM_CH12(v)) + +#define BIT_SHIFT_TXPKTNUM_CH14_15 16 +#define BIT_MASK_TXPKTNUM_CH14_15 0xfff +#define BIT_TXPKTNUM_CH14_15(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH14_15) << BIT_SHIFT_TXPKTNUM_CH14_15) +#define BITS_TXPKTNUM_CH14_15 \ + (BIT_MASK_TXPKTNUM_CH14_15 << BIT_SHIFT_TXPKTNUM_CH14_15) +#define BIT_CLEAR_TXPKTNUM_CH14_15(x) ((x) & (~BITS_TXPKTNUM_CH14_15)) +#define BIT_GET_TXPKTNUM_CH14_15(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH14_15) & BIT_MASK_TXPKTNUM_CH14_15) +#define BIT_SET_TXPKTNUM_CH14_15(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH14_15(x) | BIT_TXPKTNUM_CH14_15(v)) + +#define BIT_BCN4_VALID BIT(15) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TDE_DEBUG (Offset 0x0220) */ -/* 2 REG_HI3Q_TXBD_DESA (Offset 0x0358) */ +#define BIT_SHIFT_TDE_DEBUG 0 +#define BIT_MASK_TDE_DEBUG 0xffffffffL +#define BIT_TDE_DEBUG(x) (((x) & BIT_MASK_TDE_DEBUG) << BIT_SHIFT_TDE_DEBUG) +#define BITS_TDE_DEBUG (BIT_MASK_TDE_DEBUG << BIT_SHIFT_TDE_DEBUG) +#define BIT_CLEAR_TDE_DEBUG(x) ((x) & (~BITS_TDE_DEBUG)) +#define BIT_GET_TDE_DEBUG(x) (((x) >> BIT_SHIFT_TDE_DEBUG) & BIT_MASK_TDE_DEBUG) +#define BIT_SET_TDE_DEBUG(x, v) (BIT_CLEAR_TDE_DEBUG(x) | BIT_TDE_DEBUG(v)) +#endif -#define BIT_SHIFT_HI3Q_TXBD_DESA 0 -#define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI3Q_TXBD_DESA(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA) -#define BIT_GET_HI3Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TQPNT3 (Offset 0x0220) */ -/* 2 REG_HI4Q_TXBD_DESA (Offset 0x0360) */ +#define BIT_SHIFT_LPQ_LOW_TH_V1 0 +#define BIT_MASK_LPQ_LOW_TH_V1 0xfff +#define BIT_LPQ_LOW_TH_V1(x) \ + (((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1) +#define BITS_LPQ_LOW_TH_V1 (BIT_MASK_LPQ_LOW_TH_V1 << BIT_SHIFT_LPQ_LOW_TH_V1) +#define BIT_CLEAR_LPQ_LOW_TH_V1(x) ((x) & (~BITS_LPQ_LOW_TH_V1)) +#define BIT_GET_LPQ_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1) +#define BIT_SET_LPQ_LOW_TH_V1(x, v) \ + (BIT_CLEAR_LPQ_LOW_TH_V1(x) | BIT_LPQ_LOW_TH_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_BCN_CTRL_2 (Offset 0x0220) */ + +#define BIT_SHIFT_BCN4_HEAD 0 +#define BIT_MASK_BCN4_HEAD 0xfff +#define BIT_BCN4_HEAD(x) (((x) & BIT_MASK_BCN4_HEAD) << BIT_SHIFT_BCN4_HEAD) +#define BITS_BCN4_HEAD (BIT_MASK_BCN4_HEAD << BIT_SHIFT_BCN4_HEAD) +#define BIT_CLEAR_BCN4_HEAD(x) ((x) & (~BITS_BCN4_HEAD)) +#define BIT_GET_BCN4_HEAD(x) (((x) >> BIT_SHIFT_BCN4_HEAD) & BIT_MASK_BCN4_HEAD) +#define BIT_SET_BCN4_HEAD(x, v) (BIT_CLEAR_BCN4_HEAD(x) | BIT_BCN4_HEAD(v)) + +#define BIT_SHIFT_TXPKTNUM_CH0_3 0 +#define BIT_MASK_TXPKTNUM_CH0_3 0xfff +#define BIT_TXPKTNUM_CH0_3(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH0_3) << BIT_SHIFT_TXPKTNUM_CH0_3) +#define BITS_TXPKTNUM_CH0_3 \ + (BIT_MASK_TXPKTNUM_CH0_3 << BIT_SHIFT_TXPKTNUM_CH0_3) +#define BIT_CLEAR_TXPKTNUM_CH0_3(x) ((x) & (~BITS_TXPKTNUM_CH0_3)) +#define BIT_GET_TXPKTNUM_CH0_3(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH0_3) & BIT_MASK_TXPKTNUM_CH0_3) +#define BIT_SET_TXPKTNUM_CH0_3(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH0_3(x) | BIT_TXPKTNUM_CH0_3(v)) + +#define BIT_SHIFT_TXPKTNUM_CH8_11 0 +#define BIT_MASK_TXPKTNUM_CH8_11 0xfff +#define BIT_TXPKTNUM_CH8_11(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH8_11) << BIT_SHIFT_TXPKTNUM_CH8_11) +#define BITS_TXPKTNUM_CH8_11 \ + (BIT_MASK_TXPKTNUM_CH8_11 << BIT_SHIFT_TXPKTNUM_CH8_11) +#define BIT_CLEAR_TXPKTNUM_CH8_11(x) ((x) & (~BITS_TXPKTNUM_CH8_11)) +#define BIT_GET_TXPKTNUM_CH8_11(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH8_11) & BIT_MASK_TXPKTNUM_CH8_11) +#define BIT_SET_TXPKTNUM_CH8_11(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH8_11(x) | BIT_TXPKTNUM_CH8_11(v)) + +#define BIT_SHIFT_TXPKTNUM_CH13 0 +#define BIT_MASK_TXPKTNUM_CH13 0xfff +#define BIT_TXPKTNUM_CH13(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH13) << BIT_SHIFT_TXPKTNUM_CH13) +#define BITS_TXPKTNUM_CH13 (BIT_MASK_TXPKTNUM_CH13 << BIT_SHIFT_TXPKTNUM_CH13) +#define BIT_CLEAR_TXPKTNUM_CH13(x) ((x) & (~BITS_TXPKTNUM_CH13)) +#define BIT_GET_TXPKTNUM_CH13(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH13) & BIT_MASK_TXPKTNUM_CH13) +#define BIT_SET_TXPKTNUM_CH13(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH13(x) | BIT_TXPKTNUM_CH13(v)) + +#define BIT_SHIFT_TXPKTNUM_CH16 0 +#define BIT_MASK_TXPKTNUM_CH16 0xfff +#define BIT_TXPKTNUM_CH16(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH16) << BIT_SHIFT_TXPKTNUM_CH16) +#define BITS_TXPKTNUM_CH16 (BIT_MASK_TXPKTNUM_CH16 << BIT_SHIFT_TXPKTNUM_CH16) +#define BIT_CLEAR_TXPKTNUM_CH16(x) ((x) & (~BITS_TXPKTNUM_CH16)) +#define BIT_GET_TXPKTNUM_CH16(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH16) & BIT_MASK_TXPKTNUM_CH16) +#define BIT_SET_TXPKTNUM_CH16(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH16(x) | BIT_TXPKTNUM_CH16(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TQPNT4 (Offset 0x0224) */ -#define BIT_SHIFT_HI4Q_TXBD_DESA 0 -#define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI4Q_TXBD_DESA(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA) -#define BIT_GET_HI4Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA) +#define BIT_EXQ_INT_EN BIT(31) +#endif -/* 2 REG_HI5Q_TXBD_DESA (Offset 0x0368) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AUTO_LLT (Offset 0x0224) */ -#define BIT_SHIFT_HI5Q_TXBD_DESA 0 -#define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI5Q_TXBD_DESA(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA) -#define BIT_GET_HI5Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA) +#define BIT_SHIFT_TXPKTNUM_V1 24 +#define BIT_MASK_TXPKTNUM_V1 0xff +#define BIT_TXPKTNUM_V1(x) \ + (((x) & BIT_MASK_TXPKTNUM_V1) << BIT_SHIFT_TXPKTNUM_V1) +#define BITS_TXPKTNUM_V1 (BIT_MASK_TXPKTNUM_V1 << BIT_SHIFT_TXPKTNUM_V1) +#define BIT_CLEAR_TXPKTNUM_V1(x) ((x) & (~BITS_TXPKTNUM_V1)) +#define BIT_GET_TXPKTNUM_V1(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V1) & BIT_MASK_TXPKTNUM_V1) +#define BIT_SET_TXPKTNUM_V1(x, v) \ + (BIT_CLEAR_TXPKTNUM_V1(x) | BIT_TXPKTNUM_V1(v)) +#define BIT_TDE_DBG_SEL BIT(23) -/* 2 REG_HI6Q_TXBD_DESA (Offset 0x0370) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_HI6Q_TXBD_DESA 0 -#define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI6Q_TXBD_DESA(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA) -#define BIT_GET_HI6Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA) +/* 2 REG_AUTO_LLT (Offset 0x0224) */ +#define BIT_MASK_QSEL_DIFF BIT(22) -/* 2 REG_HI7Q_TXBD_DESA (Offset 0x0378) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI7Q_TXBD_DESA 0 -#define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL -#define BIT_HI7Q_TXBD_DESA(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA) -#define BIT_GET_HI7Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA) +/* 2 REG_AUTO_LLT (Offset 0x0224) */ +#define BIT_AUTO_INIT_LLT BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ +/* 2 REG_TQPNT4 (Offset 0x0224) */ -#define BIT_PCIE_MGQ_FLAG BIT(14) +#define BIT_SHIFT_EXQ_HIGH_TH_V1 16 +#define BIT_MASK_EXQ_HIGH_TH_V1 0xfff +#define BIT_EXQ_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1) +#define BITS_EXQ_HIGH_TH_V1 \ + (BIT_MASK_EXQ_HIGH_TH_V1 << BIT_SHIFT_EXQ_HIGH_TH_V1) +#define BIT_CLEAR_EXQ_HIGH_TH_V1(x) ((x) & (~BITS_EXQ_HIGH_TH_V1)) +#define BIT_GET_EXQ_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1) +#define BIT_SET_EXQ_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH_V1(x) | BIT_EXQ_HIGH_TH_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_AUTO_LLT (Offset 0x0224) */ +#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE 8 +#define BIT_MASK_TX_OQT_HE_FREE_SPACE 0xff +#define BIT_TX_OQT_HE_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE) +#define BITS_TX_OQT_HE_FREE_SPACE \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE << BIT_SHIFT_TX_OQT_HE_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_HE_FREE_SPACE)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE) +#define BIT_SET_TX_OQT_HE_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) | BIT_TX_OQT_HE_FREE_SPACE(v)) + +#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE 0 +#define BIT_MASK_TX_OQT_NL_FREE_SPACE 0xff +#define BIT_TX_OQT_NL_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE) +#define BITS_TX_OQT_NL_FREE_SPACE \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE << BIT_SHIFT_TX_OQT_NL_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_NL_FREE_SPACE)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE) +#define BIT_SET_TX_OQT_NL_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) | BIT_TX_OQT_NL_FREE_SPACE(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ +/* 2 REG_TQPNT4 (Offset 0x0224) */ -#define BIT_HCI_MGQ_FLAG BIT(14) +#define BIT_SHIFT_EXQ_LOW_TH_V1 0 +#define BIT_MASK_EXQ_LOW_TH_V1 0xfff +#define BIT_EXQ_LOW_TH_V1(x) \ + (((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1) +#define BITS_EXQ_LOW_TH_V1 (BIT_MASK_EXQ_LOW_TH_V1 << BIT_SHIFT_EXQ_LOW_TH_V1) +#define BIT_CLEAR_EXQ_LOW_TH_V1(x) ((x) & (~BITS_EXQ_LOW_TH_V1)) +#define BIT_GET_EXQ_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1) +#define BIT_SET_EXQ_LOW_TH_V1(x, v) \ + (BIT_CLEAR_EXQ_LOW_TH_V1(x) | BIT_EXQ_LOW_TH_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ -/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ +#define BIT_SHIFT_BCN_HEAD_2 24 +#define BIT_MASK_BCN_HEAD_2 0xff +#define BIT_BCN_HEAD_2(x) (((x) & BIT_MASK_BCN_HEAD_2) << BIT_SHIFT_BCN_HEAD_2) +#define BITS_BCN_HEAD_2 (BIT_MASK_BCN_HEAD_2 << BIT_SHIFT_BCN_HEAD_2) +#define BIT_CLEAR_BCN_HEAD_2(x) ((x) & (~BITS_BCN_HEAD_2)) +#define BIT_GET_BCN_HEAD_2(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_2) & BIT_MASK_BCN_HEAD_2) +#define BIT_SET_BCN_HEAD_2(x, v) (BIT_CLEAR_BCN_HEAD_2(x) | BIT_BCN_HEAD_2(v)) +#endif -#define BIT_SHIFT_MGQ_DESC_MODE 12 -#define BIT_MASK_MGQ_DESC_MODE 0x3 -#define BIT_MGQ_DESC_MODE(x) (((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE) -#define BIT_GET_MGQ_DESC_MODE(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ -#define BIT_SHIFT_MGQ_DESC_NUM 0 -#define BIT_MASK_MGQ_DESC_NUM 0xfff -#define BIT_MGQ_DESC_NUM(x) (((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM) -#define BIT_GET_MGQ_DESC_NUM(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM) +#define BIT_SW_BCN_SEL BIT(20) +#endif -/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +#if (HALMAC_8192F_SUPPORT) -#define BIT_SYS_32_64 BIT(15) +/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ -#define BIT_SHIFT_BCNQ_DESC_MODE 13 -#define BIT_MASK_BCNQ_DESC_MODE 0x3 -#define BIT_BCNQ_DESC_MODE(x) (((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE) -#define BIT_GET_BCNQ_DESC_MODE(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE) +#define BIT_SHIFT_SW_BCN_SEL_V1 20 +#define BIT_MASK_SW_BCN_SEL_V1 0x3 +#define BIT_SW_BCN_SEL_V1(x) \ + (((x) & BIT_MASK_SW_BCN_SEL_V1) << BIT_SHIFT_SW_BCN_SEL_V1) +#define BITS_SW_BCN_SEL_V1 (BIT_MASK_SW_BCN_SEL_V1 << BIT_SHIFT_SW_BCN_SEL_V1) +#define BIT_CLEAR_SW_BCN_SEL_V1(x) ((x) & (~BITS_SW_BCN_SEL_V1)) +#define BIT_GET_SW_BCN_SEL_V1(x) \ + (((x) >> BIT_SHIFT_SW_BCN_SEL_V1) & BIT_MASK_SW_BCN_SEL_V1) +#define BIT_SET_SW_BCN_SEL_V1(x, v) \ + (BIT_CLEAR_SW_BCN_SEL_V1(x) | BIT_SW_BCN_SEL_V1(v)) +#define BIT_BCN_VALID_2 BIT(18) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ +#define BIT_SW_BCN_SEL_EN BIT(17) +#define BIT_BCN_VALID_1 BIT(16) -/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +#endif -#define BIT_PCIE_BCNQ_FLAG BIT(12) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +#define BIT_SHIFT_TXPKTNUM_H 16 +#define BIT_MASK_TXPKTNUM_H 0xffff +#define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H) +#define BITS_TXPKTNUM_H (BIT_MASK_TXPKTNUM_H << BIT_SHIFT_TXPKTNUM_H) +#define BIT_CLEAR_TXPKTNUM_H(x) ((x) & (~BITS_TXPKTNUM_H)) +#define BIT_GET_TXPKTNUM_H(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H) +#define BIT_SET_TXPKTNUM_H(x, v) (BIT_CLEAR_TXPKTNUM_H(x) | BIT_TXPKTNUM_H(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ -#define BIT_HCI_BCNQ_FLAG BIT(12) +#define BIT_SHIFT_TXPKTNUM_H_V2 16 +#define BIT_MASK_TXPKTNUM_H_V2 0xfff +#define BIT_TXPKTNUM_H_V2(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_V2) << BIT_SHIFT_TXPKTNUM_H_V2) +#define BITS_TXPKTNUM_H_V2 (BIT_MASK_TXPKTNUM_H_V2 << BIT_SHIFT_TXPKTNUM_H_V2) +#define BIT_CLEAR_TXPKTNUM_H_V2(x) ((x) & (~BITS_TXPKTNUM_H_V2)) +#define BIT_GET_TXPKTNUM_H_V2(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_V2) & BIT_MASK_TXPKTNUM_H_V2) +#define BIT_SET_TXPKTNUM_H_V2(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_V2(x) | BIT_TXPKTNUM_H_V2(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ +#define BIT_ADJUSTABLE_SIZE_EN BIT(15) -/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RXQ_DESC_NUM 0 -#define BIT_MASK_RXQ_DESC_NUM 0xfff -#define BIT_RXQ_DESC_NUM(x) (((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM) -#define BIT_GET_RXQ_DESC_NUM(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM) +/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ +#define BIT_SHIFT_BCN_HEAD_1 8 +#define BIT_MASK_BCN_HEAD_1 0xff +#define BIT_BCN_HEAD_1(x) (((x) & BIT_MASK_BCN_HEAD_1) << BIT_SHIFT_BCN_HEAD_1) +#define BITS_BCN_HEAD_1 (BIT_MASK_BCN_HEAD_1 << BIT_SHIFT_BCN_HEAD_1) +#define BIT_CLEAR_BCN_HEAD_1(x) ((x) & (~BITS_BCN_HEAD_1)) +#define BIT_GET_BCN_HEAD_1(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1) & BIT_MASK_BCN_HEAD_1) +#define BIT_SET_BCN_HEAD_1(x, v) (BIT_CLEAR_BCN_HEAD_1(x) | BIT_BCN_HEAD_1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ +#define BIT_RST_PGSUB_CNT BIT(1) -/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +#endif -#define BIT_PCIE_VOQ_FLAG BIT(14) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ +#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO 0 +#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO 0xff +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) +#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO \ + (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) +#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \ + ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO)) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) & \ + BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) +#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x) | \ + BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */ -#define BIT_HCI_VOQ_FLAG BIT(14) +#define BIT_SHIFT_ALIGNMENT_SIZE 0 +#define BIT_MASK_ALIGNMENT_SIZE 0xfff +#define BIT_ALIGNMENT_SIZE(x) \ + (((x) & BIT_MASK_ALIGNMENT_SIZE) << BIT_SHIFT_ALIGNMENT_SIZE) +#define BITS_ALIGNMENT_SIZE \ + (BIT_MASK_ALIGNMENT_SIZE << BIT_SHIFT_ALIGNMENT_SIZE) +#define BIT_CLEAR_ALIGNMENT_SIZE(x) ((x) & (~BITS_ALIGNMENT_SIZE)) +#define BIT_GET_ALIGNMENT_SIZE(x) \ + (((x) >> BIT_SHIFT_ALIGNMENT_SIZE) & BIT_MASK_ALIGNMENT_SIZE) +#define BIT_SET_ALIGNMENT_SIZE(x, v) \ + (BIT_CLEAR_ALIGNMENT_SIZE(x) | BIT_ALIGNMENT_SIZE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ -/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +#define BIT_SHIFT_TXPKTNUM_H_V1 0 +#define BIT_MASK_TXPKTNUM_H_V1 0xffff +#define BIT_TXPKTNUM_H_V1(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_V1) << BIT_SHIFT_TXPKTNUM_H_V1) +#define BITS_TXPKTNUM_H_V1 (BIT_MASK_TXPKTNUM_H_V1 << BIT_SHIFT_TXPKTNUM_H_V1) +#define BIT_CLEAR_TXPKTNUM_H_V1(x) ((x) & (~BITS_TXPKTNUM_H_V1)) +#define BIT_GET_TXPKTNUM_H_V1(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_V1) & BIT_MASK_TXPKTNUM_H_V1) +#define BIT_SET_TXPKTNUM_H_V1(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_V1(x) | BIT_TXPKTNUM_H_V1(v)) +#endif -#define BIT_SHIFT_VOQ_DESC_MODE 12 -#define BIT_MASK_VOQ_DESC_MODE 0x3 -#define BIT_VOQ_DESC_MODE(x) (((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE) -#define BIT_GET_VOQ_DESC_MODE(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ -#define BIT_SHIFT_VOQ_DESC_NUM 0 -#define BIT_MASK_VOQ_DESC_NUM 0xfff -#define BIT_VOQ_DESC_NUM(x) (((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM) -#define BIT_GET_VOQ_DESC_NUM(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM) +#define BIT_SHIFT_TXPKTNUM_V3 0 +#define BIT_MASK_TXPKTNUM_V3 0xfff +#define BIT_TXPKTNUM_V3(x) \ + (((x) & BIT_MASK_TXPKTNUM_V3) << BIT_SHIFT_TXPKTNUM_V3) +#define BITS_TXPKTNUM_V3 (BIT_MASK_TXPKTNUM_V3 << BIT_SHIFT_TXPKTNUM_V3) +#define BIT_CLEAR_TXPKTNUM_V3(x) ((x) & (~BITS_TXPKTNUM_V3)) +#define BIT_GET_TXPKTNUM_V3(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V3) & BIT_MASK_TXPKTNUM_V3) +#define BIT_SET_TXPKTNUM_V3(x, v) \ + (BIT_CLEAR_TXPKTNUM_V3(x) | BIT_TXPKTNUM_V3(v)) +#define BIT_PGSUB_CNT_EN BIT(0) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ +/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ -#define BIT_PCIE_VIQ_FLAG BIT(14) +#define BIT_SHIFT_TXPKTNUM_V2 0 +#define BIT_MASK_TXPKTNUM_V2 0xffff +#define BIT_TXPKTNUM_V2(x) \ + (((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2) +#define BITS_TXPKTNUM_V2 (BIT_MASK_TXPKTNUM_V2 << BIT_SHIFT_TXPKTNUM_V2) +#define BIT_CLEAR_TXPKTNUM_V2(x) ((x) & (~BITS_TXPKTNUM_V2)) +#define BIT_GET_TXPKTNUM_V2(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2) +#define BIT_SET_TXPKTNUM_V2(x, v) \ + (BIT_CLEAR_TXPKTNUM_V2(x) | BIT_TXPKTNUM_V2(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ +/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ -#define BIT_HCI_VIQ_FLAG BIT(14) +#define BIT_EX2Q_PUBLIC_DIS_V1 BIT(21) +#define BIT_EX1Q_PUBLIC_DIS_V1 BIT(20) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ -/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ +#define BIT_EXQ_PUBLIC_DIS_V1 BIT(19) +#define BIT_NPQ_PUBLIC_DIS_V1 BIT(18) +#define BIT_LPQ_PUBLIC_DIS_V1 BIT(17) +#define BIT_HPQ_PUBLIC_DIS_V1 BIT(16) +#endif -#define BIT_SHIFT_VIQ_DESC_MODE 12 -#define BIT_MASK_VIQ_DESC_MODE 0x3 -#define BIT_VIQ_DESC_MODE(x) (((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE) -#define BIT_GET_VIQ_DESC_MODE(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE) +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ -#define BIT_SHIFT_VIQ_DESC_NUM 0 -#define BIT_MASK_VIQ_DESC_NUM 0xfff -#define BIT_VIQ_DESC_NUM(x) (((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM) -#define BIT_GET_VIQ_DESC_NUM(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM) +#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN BIT(15) +#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE 0 +#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE 0xfff +#define BIT_SDIO_TXAGG_ALIGN_SIZE(x) \ + (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) +#define BITS_SDIO_TXAGG_ALIGN_SIZE \ + (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) +#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE)) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE(x) \ + (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) & \ + BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) +#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE(x, v) \ + (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) | BIT_SDIO_TXAGG_ALIGN_SIZE(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_RQPN_EXQ1_EXQ2 (Offset 0x0230) */ -/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ +#define BIT_SHIFT_EXQ2_AVAL_PG 24 +#define BIT_MASK_EXQ2_AVAL_PG 0xff +#define BIT_EXQ2_AVAL_PG(x) \ + (((x) & BIT_MASK_EXQ2_AVAL_PG) << BIT_SHIFT_EXQ2_AVAL_PG) +#define BITS_EXQ2_AVAL_PG (BIT_MASK_EXQ2_AVAL_PG << BIT_SHIFT_EXQ2_AVAL_PG) +#define BIT_CLEAR_EXQ2_AVAL_PG(x) ((x) & (~BITS_EXQ2_AVAL_PG)) +#define BIT_GET_EXQ2_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_EXQ2_AVAL_PG) & BIT_MASK_EXQ2_AVAL_PG) +#define BIT_SET_EXQ2_AVAL_PG(x, v) \ + (BIT_CLEAR_EXQ2_AVAL_PG(x) | BIT_EXQ2_AVAL_PG(v)) -#define BIT_PCIE_BEQ_FLAG BIT(14) +#define BIT_SHIFT_EXQ2 16 +#define BIT_MASK_EXQ2 0xff +#define BIT_EXQ2(x) (((x) & BIT_MASK_EXQ2) << BIT_SHIFT_EXQ2) +#define BITS_EXQ2 (BIT_MASK_EXQ2 << BIT_SHIFT_EXQ2) +#define BIT_CLEAR_EXQ2(x) ((x) & (~BITS_EXQ2)) +#define BIT_GET_EXQ2(x) (((x) >> BIT_SHIFT_EXQ2) & BIT_MASK_EXQ2) +#define BIT_SET_EXQ2(x, v) (BIT_CLEAR_EXQ2(x) | BIT_EXQ2(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ +/* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */ -#define BIT_HCI_BEQ_FLAG BIT(14) +#define BIT_SHIFT_HPQ_AVAL_PG_V1 16 +#define BIT_MASK_HPQ_AVAL_PG_V1 0xfff +#define BIT_HPQ_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1) +#define BITS_HPQ_AVAL_PG_V1 \ + (BIT_MASK_HPQ_AVAL_PG_V1 << BIT_SHIFT_HPQ_AVAL_PG_V1) +#define BIT_CLEAR_HPQ_AVAL_PG_V1(x) ((x) & (~BITS_HPQ_AVAL_PG_V1)) +#define BIT_GET_HPQ_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1) +#define BIT_SET_HPQ_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG_V1(x) | BIT_HPQ_AVAL_PG_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RQPN_EXQ1_EXQ2 (Offset 0x0230) */ +#define BIT_SHIFT_EXQ1_AVAL_PG 8 +#define BIT_MASK_EXQ1_AVAL_PG 0xff +#define BIT_EXQ1_AVAL_PG(x) \ + (((x) & BIT_MASK_EXQ1_AVAL_PG) << BIT_SHIFT_EXQ1_AVAL_PG) +#define BITS_EXQ1_AVAL_PG (BIT_MASK_EXQ1_AVAL_PG << BIT_SHIFT_EXQ1_AVAL_PG) +#define BIT_CLEAR_EXQ1_AVAL_PG(x) ((x) & (~BITS_EXQ1_AVAL_PG)) +#define BIT_GET_EXQ1_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_EXQ1_AVAL_PG) & BIT_MASK_EXQ1_AVAL_PG) +#define BIT_SET_EXQ1_AVAL_PG(x, v) \ + (BIT_CLEAR_EXQ1_AVAL_PG(x) | BIT_EXQ1_AVAL_PG(v)) -/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ - +#define BIT_SHIFT_EXQ1 0 +#define BIT_MASK_EXQ1 0xff +#define BIT_EXQ1(x) (((x) & BIT_MASK_EXQ1) << BIT_SHIFT_EXQ1) +#define BITS_EXQ1 (BIT_MASK_EXQ1 << BIT_SHIFT_EXQ1) +#define BIT_CLEAR_EXQ1(x) ((x) & (~BITS_EXQ1)) +#define BIT_GET_EXQ1(x) (((x) >> BIT_SHIFT_EXQ1) & BIT_MASK_EXQ1) +#define BIT_SET_EXQ1(x, v) (BIT_CLEAR_EXQ1(x) | BIT_EXQ1(v)) -#define BIT_SHIFT_BEQ_DESC_MODE 12 -#define BIT_MASK_BEQ_DESC_MODE 0x3 -#define BIT_BEQ_DESC_MODE(x) (((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE) -#define BIT_GET_BEQ_DESC_MODE(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BEQ_DESC_NUM 0 -#define BIT_MASK_BEQ_DESC_NUM 0xfff -#define BIT_BEQ_DESC_NUM(x) (((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM) -#define BIT_GET_BEQ_DESC_NUM(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM) +/* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */ +#define BIT_SHIFT_HPQ_V1 0 +#define BIT_MASK_HPQ_V1 0xfff +#define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1) +#define BITS_HPQ_V1 (BIT_MASK_HPQ_V1 << BIT_SHIFT_HPQ_V1) +#define BIT_CLEAR_HPQ_V1(x) ((x) & (~BITS_HPQ_V1)) +#define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1) +#define BIT_SET_HPQ_V1(x, v) (BIT_CLEAR_HPQ_V1(x) | BIT_HPQ_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TQPNT3_V1 (Offset 0x0234) */ +#define BIT_SHIFT_EXQ2_HIGH_TH 24 +#define BIT_MASK_EXQ2_HIGH_TH 0xff +#define BIT_EXQ2_HIGH_TH(x) \ + (((x) & BIT_MASK_EXQ2_HIGH_TH) << BIT_SHIFT_EXQ2_HIGH_TH) +#define BITS_EXQ2_HIGH_TH (BIT_MASK_EXQ2_HIGH_TH << BIT_SHIFT_EXQ2_HIGH_TH) +#define BIT_CLEAR_EXQ2_HIGH_TH(x) ((x) & (~BITS_EXQ2_HIGH_TH)) +#define BIT_GET_EXQ2_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_EXQ2_HIGH_TH) & BIT_MASK_EXQ2_HIGH_TH) +#define BIT_SET_EXQ2_HIGH_TH(x, v) \ + (BIT_CLEAR_EXQ2_HIGH_TH(x) | BIT_EXQ2_HIGH_TH(v)) -/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ - -#define BIT_PCIE_BKQ_FLAG BIT(14) +#define BIT_SHIFT_EXQ2_LOW_TH 16 +#define BIT_MASK_EXQ2_LOW_TH 0xff +#define BIT_EXQ2_LOW_TH(x) \ + (((x) & BIT_MASK_EXQ2_LOW_TH) << BIT_SHIFT_EXQ2_LOW_TH) +#define BITS_EXQ2_LOW_TH (BIT_MASK_EXQ2_LOW_TH << BIT_SHIFT_EXQ2_LOW_TH) +#define BIT_CLEAR_EXQ2_LOW_TH(x) ((x) & (~BITS_EXQ2_LOW_TH)) +#define BIT_GET_EXQ2_LOW_TH(x) \ + (((x) >> BIT_SHIFT_EXQ2_LOW_TH) & BIT_MASK_EXQ2_LOW_TH) +#define BIT_SET_EXQ2_LOW_TH(x, v) \ + (BIT_CLEAR_EXQ2_LOW_TH(x) | BIT_EXQ2_LOW_TH(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_FIFOPAGE_INFO_2 (Offset 0x0234) */ +#define BIT_SHIFT_LPQ_AVAL_PG_V1 16 +#define BIT_MASK_LPQ_AVAL_PG_V1 0xfff +#define BIT_LPQ_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1) +#define BITS_LPQ_AVAL_PG_V1 \ + (BIT_MASK_LPQ_AVAL_PG_V1 << BIT_SHIFT_LPQ_AVAL_PG_V1) +#define BIT_CLEAR_LPQ_AVAL_PG_V1(x) ((x) & (~BITS_LPQ_AVAL_PG_V1)) +#define BIT_GET_LPQ_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1) +#define BIT_SET_LPQ_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG_V1(x) | BIT_LPQ_AVAL_PG_V1(v)) -/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ +#endif -#define BIT_HCI_BKQ_FLAG BIT(14) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_TQPNT3_V1 (Offset 0x0234) */ +#define BIT_SHIFT_EXQ1_HIGH_TH 8 +#define BIT_MASK_EXQ1_HIGH_TH 0xff +#define BIT_EXQ1_HIGH_TH(x) \ + (((x) & BIT_MASK_EXQ1_HIGH_TH) << BIT_SHIFT_EXQ1_HIGH_TH) +#define BITS_EXQ1_HIGH_TH (BIT_MASK_EXQ1_HIGH_TH << BIT_SHIFT_EXQ1_HIGH_TH) +#define BIT_CLEAR_EXQ1_HIGH_TH(x) ((x) & (~BITS_EXQ1_HIGH_TH)) +#define BIT_GET_EXQ1_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_EXQ1_HIGH_TH) & BIT_MASK_EXQ1_HIGH_TH) +#define BIT_SET_EXQ1_HIGH_TH(x, v) \ + (BIT_CLEAR_EXQ1_HIGH_TH(x) | BIT_EXQ1_HIGH_TH(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_EXQ1_LOW_TH 0 +#define BIT_MASK_EXQ1_LOW_TH 0xff +#define BIT_EXQ1_LOW_TH(x) \ + (((x) & BIT_MASK_EXQ1_LOW_TH) << BIT_SHIFT_EXQ1_LOW_TH) +#define BITS_EXQ1_LOW_TH (BIT_MASK_EXQ1_LOW_TH << BIT_SHIFT_EXQ1_LOW_TH) +#define BIT_CLEAR_EXQ1_LOW_TH(x) ((x) & (~BITS_EXQ1_LOW_TH)) +#define BIT_GET_EXQ1_LOW_TH(x) \ + (((x) >> BIT_SHIFT_EXQ1_LOW_TH) & BIT_MASK_EXQ1_LOW_TH) +#define BIT_SET_EXQ1_LOW_TH(x, v) \ + (BIT_CLEAR_EXQ1_LOW_TH(x) | BIT_EXQ1_LOW_TH(v)) +#endif -/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_FIFOPAGE_INFO_2 (Offset 0x0234) */ -#define BIT_SHIFT_BKQ_DESC_MODE 12 -#define BIT_MASK_BKQ_DESC_MODE 0x3 -#define BIT_BKQ_DESC_MODE(x) (((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE) -#define BIT_GET_BKQ_DESC_MODE(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE) +#define BIT_SHIFT_LPQ_V1 0 +#define BIT_MASK_LPQ_V1 0xfff +#define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1) +#define BITS_LPQ_V1 (BIT_MASK_LPQ_V1 << BIT_SHIFT_LPQ_V1) +#define BIT_CLEAR_LPQ_V1(x) ((x) & (~BITS_LPQ_V1)) +#define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1) +#define BIT_SET_LPQ_V1(x, v) (BIT_CLEAR_LPQ_V1(x) | BIT_LPQ_V1(v)) +#endif -#define BIT_SHIFT_BKQ_DESC_NUM 0 -#define BIT_MASK_BKQ_DESC_NUM 0xfff -#define BIT_BKQ_DESC_NUM(x) (((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM) -#define BIT_GET_BKQ_DESC_NUM(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ -/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ +#define BIT_SHIFT_NPQ_AVAL_PG_V1 16 +#define BIT_MASK_NPQ_AVAL_PG_V1 0xfff +#define BIT_NPQ_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1) +#define BITS_NPQ_AVAL_PG_V1 \ + (BIT_MASK_NPQ_AVAL_PG_V1 << BIT_SHIFT_NPQ_AVAL_PG_V1) +#define BIT_CLEAR_NPQ_AVAL_PG_V1(x) ((x) & (~BITS_NPQ_AVAL_PG_V1)) +#define BIT_GET_NPQ_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1) +#define BIT_SET_NPQ_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG_V1(x) | BIT_NPQ_AVAL_PG_V1(v)) -#define BIT_HI0Q_FLAG BIT(14) +#endif -#define BIT_SHIFT_HI0Q_DESC_MODE 12 -#define BIT_MASK_HI0Q_DESC_MODE 0x3 -#define BIT_HI0Q_DESC_MODE(x) (((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE) -#define BIT_GET_HI0Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ -#define BIT_SHIFT_HI0Q_DESC_NUM 0 -#define BIT_MASK_HI0Q_DESC_NUM 0xfff -#define BIT_HI0Q_DESC_NUM(x) (((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM) -#define BIT_GET_HI0Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM) +#define BIT_SHIFT_NPQ_V1 0 +#define BIT_MASK_NPQ_V1 0xfff +#define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1) +#define BITS_NPQ_V1 (BIT_MASK_NPQ_V1 << BIT_SHIFT_NPQ_V1) +#define BIT_CLEAR_NPQ_V1(x) ((x) & (~BITS_NPQ_V1)) +#define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1) +#define BIT_SET_NPQ_V1(x, v) (BIT_CLEAR_NPQ_V1(x) | BIT_NPQ_V1(v)) +/* 2 REG_FIFOPAGE_INFO_4 (Offset 0x023C) */ -/* 2 REG_HI1Q_TXBD_NUM (Offset 0x038E) */ +#define BIT_SHIFT_EXQ_AVAL_PG_V1 16 +#define BIT_MASK_EXQ_AVAL_PG_V1 0xfff +#define BIT_EXQ_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1) +#define BITS_EXQ_AVAL_PG_V1 \ + (BIT_MASK_EXQ_AVAL_PG_V1 << BIT_SHIFT_EXQ_AVAL_PG_V1) +#define BIT_CLEAR_EXQ_AVAL_PG_V1(x) ((x) & (~BITS_EXQ_AVAL_PG_V1)) +#define BIT_GET_EXQ_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1) +#define BIT_SET_EXQ_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG_V1(x) | BIT_EXQ_AVAL_PG_V1(v)) + +#define BIT_SHIFT_EXQ_V1 0 +#define BIT_MASK_EXQ_V1 0xfff +#define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1) +#define BITS_EXQ_V1 (BIT_MASK_EXQ_V1 << BIT_SHIFT_EXQ_V1) +#define BIT_CLEAR_EXQ_V1(x) ((x) & (~BITS_EXQ_V1)) +#define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1) +#define BIT_SET_EXQ_V1(x, v) (BIT_CLEAR_EXQ_V1(x) | BIT_EXQ_V1(v)) -#define BIT_HI1Q_FLAG BIT(14) +/* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */ -#define BIT_SHIFT_HI1Q_DESC_MODE 12 -#define BIT_MASK_HI1Q_DESC_MODE 0x3 -#define BIT_HI1Q_DESC_MODE(x) (((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE) -#define BIT_GET_HI1Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE) +#define BIT_SHIFT_PUBQ_AVAL_PG_V1 16 +#define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff +#define BIT_PUBQ_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1) +#define BITS_PUBQ_AVAL_PG_V1 \ + (BIT_MASK_PUBQ_AVAL_PG_V1 << BIT_SHIFT_PUBQ_AVAL_PG_V1) +#define BIT_CLEAR_PUBQ_AVAL_PG_V1(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1)) +#define BIT_GET_PUBQ_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1) +#define BIT_SET_PUBQ_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG_V1(x) | BIT_PUBQ_AVAL_PG_V1(v)) +#endif -#define BIT_SHIFT_HI1Q_DESC_NUM 0 -#define BIT_MASK_HI1Q_DESC_NUM 0xfff -#define BIT_HI1Q_DESC_NUM(x) (((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM) -#define BIT_GET_HI1Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_TX_AGG_ALIGN (Offset 0x0240) */ -/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ +#define BIT_SHIFT_HW_FLOW_CTL_EN 16 +#define BIT_MASK_HW_FLOW_CTL_EN 0xffff +#define BIT_HW_FLOW_CTL_EN(x) \ + (((x) & BIT_MASK_HW_FLOW_CTL_EN) << BIT_SHIFT_HW_FLOW_CTL_EN) +#define BITS_HW_FLOW_CTL_EN \ + (BIT_MASK_HW_FLOW_CTL_EN << BIT_SHIFT_HW_FLOW_CTL_EN) +#define BIT_CLEAR_HW_FLOW_CTL_EN(x) ((x) & (~BITS_HW_FLOW_CTL_EN)) +#define BIT_GET_HW_FLOW_CTL_EN(x) \ + (((x) >> BIT_SHIFT_HW_FLOW_CTL_EN) & BIT_MASK_HW_FLOW_CTL_EN) +#define BIT_SET_HW_FLOW_CTL_EN(x, v) \ + (BIT_CLEAR_HW_FLOW_CTL_EN(x) | BIT_HW_FLOW_CTL_EN(v)) -#define BIT_HI2Q_FLAG BIT(14) +#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_V1 BIT(15) -#define BIT_SHIFT_HI2Q_DESC_MODE 12 -#define BIT_MASK_HI2Q_DESC_MODE 0x3 -#define BIT_HI2Q_DESC_MODE(x) (((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE) -#define BIT_GET_HI2Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HI2Q_DESC_NUM 0 -#define BIT_MASK_HI2Q_DESC_NUM 0xfff -#define BIT_HI2Q_DESC_NUM(x) (((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM) -#define BIT_GET_HI2Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM) +/* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */ +#define BIT_SHIFT_PUBQ_V1 0 +#define BIT_MASK_PUBQ_V1 0xfff +#define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1) +#define BITS_PUBQ_V1 (BIT_MASK_PUBQ_V1 << BIT_SHIFT_PUBQ_V1) +#define BIT_CLEAR_PUBQ_V1(x) ((x) & (~BITS_PUBQ_V1)) +#define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1) +#define BIT_SET_PUBQ_V1(x, v) (BIT_CLEAR_PUBQ_V1(x) | BIT_PUBQ_V1(v)) -/* 2 REG_HI3Q_TXBD_NUM (Offset 0x0392) */ +#endif -#define BIT_HI3Q_FLAG BIT(14) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HI3Q_DESC_MODE 12 -#define BIT_MASK_HI3Q_DESC_MODE 0x3 -#define BIT_HI3Q_DESC_MODE(x) (((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE) -#define BIT_GET_HI3Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE) +/* 2 REG_TX_AGG_ALIGN (Offset 0x0240) */ +#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1 0 +#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1 0xfff +#define BIT_SDIO_TXAGG_ALIGN_SIZE_V1(x) \ + (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1) \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) +#define BITS_SDIO_TXAGG_ALIGN_SIZE_V1 \ + (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1 \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) +#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x) \ + ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_V1)) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_V1(x) \ + (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) & \ + BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1) +#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_V1(x, v) \ + (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x) | \ + BIT_SDIO_TXAGG_ALIGN_SIZE_V1(v)) -#define BIT_SHIFT_HI3Q_DESC_NUM 0 -#define BIT_MASK_HI3Q_DESC_NUM 0xfff -#define BIT_HI3Q_DESC_NUM(x) (((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM) -#define BIT_GET_HI3Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ +/* 2 REG_H2C_HEAD (Offset 0x0244) */ -#define BIT_HI4Q_FLAG BIT(14) +#define BIT_SHIFT_H2C_HEAD_V2 0 +#define BIT_MASK_H2C_HEAD_V2 0xffff +#define BIT_H2C_HEAD_V2(x) \ + (((x) & BIT_MASK_H2C_HEAD_V2) << BIT_SHIFT_H2C_HEAD_V2) +#define BITS_H2C_HEAD_V2 (BIT_MASK_H2C_HEAD_V2 << BIT_SHIFT_H2C_HEAD_V2) +#define BIT_CLEAR_H2C_HEAD_V2(x) ((x) & (~BITS_H2C_HEAD_V2)) +#define BIT_GET_H2C_HEAD_V2(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_V2) & BIT_MASK_H2C_HEAD_V2) +#define BIT_SET_H2C_HEAD_V2(x, v) \ + (BIT_CLEAR_H2C_HEAD_V2(x) | BIT_H2C_HEAD_V2(v)) -#define BIT_SHIFT_HI4Q_DESC_MODE 12 -#define BIT_MASK_HI4Q_DESC_MODE 0x3 -#define BIT_HI4Q_DESC_MODE(x) (((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE) -#define BIT_GET_HI4Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HI4Q_DESC_NUM 0 -#define BIT_MASK_HI4Q_DESC_NUM 0xfff -#define BIT_HI4Q_DESC_NUM(x) (((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM) -#define BIT_GET_HI4Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM) +/* 2 REG_H2C_HEAD (Offset 0x0244) */ +#define BIT_SHIFT_H2C_HEAD 0 +#define BIT_MASK_H2C_HEAD 0x3ffff +#define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD) +#define BITS_H2C_HEAD (BIT_MASK_H2C_HEAD << BIT_SHIFT_H2C_HEAD) +#define BIT_CLEAR_H2C_HEAD(x) ((x) & (~BITS_H2C_HEAD)) +#define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD) +#define BIT_SET_H2C_HEAD(x, v) (BIT_CLEAR_H2C_HEAD(x) | BIT_H2C_HEAD(v)) -/* 2 REG_HI5Q_TXBD_NUM (Offset 0x0396) */ +#endif -#define BIT_HI5Q_FLAG BIT(14) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HI5Q_DESC_MODE 12 -#define BIT_MASK_HI5Q_DESC_MODE 0x3 -#define BIT_HI5Q_DESC_MODE(x) (((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE) -#define BIT_GET_HI5Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE) +/* 2 REG_H2C_HEAD (Offset 0x0244) */ +#define BIT_SHIFT_H2C_HEAD_V1 0 +#define BIT_MASK_H2C_HEAD_V1 0x7ffff +#define BIT_H2C_HEAD_V1(x) \ + (((x) & BIT_MASK_H2C_HEAD_V1) << BIT_SHIFT_H2C_HEAD_V1) +#define BITS_H2C_HEAD_V1 (BIT_MASK_H2C_HEAD_V1 << BIT_SHIFT_H2C_HEAD_V1) +#define BIT_CLEAR_H2C_HEAD_V1(x) ((x) & (~BITS_H2C_HEAD_V1)) +#define BIT_GET_H2C_HEAD_V1(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_V1) & BIT_MASK_H2C_HEAD_V1) +#define BIT_SET_H2C_HEAD_V1(x, v) \ + (BIT_CLEAR_H2C_HEAD_V1(x) | BIT_H2C_HEAD_V1(v)) -#define BIT_SHIFT_HI5Q_DESC_NUM 0 -#define BIT_MASK_HI5Q_DESC_NUM 0xfff -#define BIT_HI5Q_DESC_NUM(x) (((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM) -#define BIT_GET_HI5Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ +/* 2 REG_H2C_TAIL (Offset 0x0248) */ -#define BIT_HI6Q_FLAG BIT(14) +#define BIT_SHIFT_H2C_TAIL_V2 0 +#define BIT_MASK_H2C_TAIL_V2 0xffff +#define BIT_H2C_TAIL_V2(x) \ + (((x) & BIT_MASK_H2C_TAIL_V2) << BIT_SHIFT_H2C_TAIL_V2) +#define BITS_H2C_TAIL_V2 (BIT_MASK_H2C_TAIL_V2 << BIT_SHIFT_H2C_TAIL_V2) +#define BIT_CLEAR_H2C_TAIL_V2(x) ((x) & (~BITS_H2C_TAIL_V2)) +#define BIT_GET_H2C_TAIL_V2(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_V2) & BIT_MASK_H2C_TAIL_V2) +#define BIT_SET_H2C_TAIL_V2(x, v) \ + (BIT_CLEAR_H2C_TAIL_V2(x) | BIT_H2C_TAIL_V2(v)) -#define BIT_SHIFT_HI6Q_DESC_MODE 12 -#define BIT_MASK_HI6Q_DESC_MODE 0x3 -#define BIT_HI6Q_DESC_MODE(x) (((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE) -#define BIT_GET_HI6Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HI6Q_DESC_NUM 0 -#define BIT_MASK_HI6Q_DESC_NUM 0xfff -#define BIT_HI6Q_DESC_NUM(x) (((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM) -#define BIT_GET_HI6Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM) +/* 2 REG_H2C_TAIL (Offset 0x0248) */ +#define BIT_SHIFT_H2C_TAIL 0 +#define BIT_MASK_H2C_TAIL 0x3ffff +#define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL) +#define BITS_H2C_TAIL (BIT_MASK_H2C_TAIL << BIT_SHIFT_H2C_TAIL) +#define BIT_CLEAR_H2C_TAIL(x) ((x) & (~BITS_H2C_TAIL)) +#define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL) +#define BIT_SET_H2C_TAIL(x, v) (BIT_CLEAR_H2C_TAIL(x) | BIT_H2C_TAIL(v)) -/* 2 REG_HI7Q_TXBD_NUM (Offset 0x039A) */ +#endif -#define BIT_HI7Q_FLAG BIT(14) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HI7Q_DESC_MODE 12 -#define BIT_MASK_HI7Q_DESC_MODE 0x3 -#define BIT_HI7Q_DESC_MODE(x) (((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE) -#define BIT_GET_HI7Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE) +/* 2 REG_H2C_TAIL (Offset 0x0248) */ +#define BIT_SHIFT_H2C_TAIL_V1 0 +#define BIT_MASK_H2C_TAIL_V1 0x7ffff +#define BIT_H2C_TAIL_V1(x) \ + (((x) & BIT_MASK_H2C_TAIL_V1) << BIT_SHIFT_H2C_TAIL_V1) +#define BITS_H2C_TAIL_V1 (BIT_MASK_H2C_TAIL_V1 << BIT_SHIFT_H2C_TAIL_V1) +#define BIT_CLEAR_H2C_TAIL_V1(x) ((x) & (~BITS_H2C_TAIL_V1)) +#define BIT_GET_H2C_TAIL_V1(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_V1) & BIT_MASK_H2C_TAIL_V1) +#define BIT_SET_H2C_TAIL_V1(x, v) \ + (BIT_CLEAR_H2C_TAIL_V1(x) | BIT_H2C_TAIL_V1(v)) -#define BIT_SHIFT_HI7Q_DESC_NUM 0 -#define BIT_MASK_HI7Q_DESC_NUM 0xfff -#define BIT_HI7Q_DESC_NUM(x) (((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM) -#define BIT_GET_HI7Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */ -#define BIT_CLR_HI7Q_HW_IDX BIT(29) -#define BIT_CLR_HI6Q_HW_IDX BIT(28) -#define BIT_CLR_HI5Q_HW_IDX BIT(27) -#define BIT_CLR_HI4Q_HW_IDX BIT(26) -#define BIT_CLR_HI3Q_HW_IDX BIT(25) -#define BIT_CLR_HI2Q_HW_IDX BIT(24) -#define BIT_CLR_HI1Q_HW_IDX BIT(23) +#define BIT_SHIFT_H2C_READ_ADDR_V2 0 +#define BIT_MASK_H2C_READ_ADDR_V2 0xffff +#define BIT_H2C_READ_ADDR_V2(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_V2) << BIT_SHIFT_H2C_READ_ADDR_V2) +#define BITS_H2C_READ_ADDR_V2 \ + (BIT_MASK_H2C_READ_ADDR_V2 << BIT_SHIFT_H2C_READ_ADDR_V2) +#define BIT_CLEAR_H2C_READ_ADDR_V2(x) ((x) & (~BITS_H2C_READ_ADDR_V2)) +#define BIT_GET_H2C_READ_ADDR_V2(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_V2) & BIT_MASK_H2C_READ_ADDR_V2) +#define BIT_SET_H2C_READ_ADDR_V2(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_V2(x) | BIT_H2C_READ_ADDR_V2(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */ +#define BIT_SHIFT_H2C_READ_ADDR 0 +#define BIT_MASK_H2C_READ_ADDR 0x3ffff +#define BIT_H2C_READ_ADDR(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR) +#define BITS_H2C_READ_ADDR (BIT_MASK_H2C_READ_ADDR << BIT_SHIFT_H2C_READ_ADDR) +#define BIT_CLEAR_H2C_READ_ADDR(x) ((x) & (~BITS_H2C_READ_ADDR)) +#define BIT_GET_H2C_READ_ADDR(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR) +#define BIT_SET_H2C_READ_ADDR(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR(x) | BIT_H2C_READ_ADDR(v)) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_BCN7DOK BIT(23) -#define BIT_BCN7DOKM BIT(23) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */ +#define BIT_SHIFT_H2C_READ_ADDR_V1 0 +#define BIT_MASK_H2C_READ_ADDR_V1 0x7ffff +#define BIT_H2C_READ_ADDR_V1(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_V1) << BIT_SHIFT_H2C_READ_ADDR_V1) +#define BITS_H2C_READ_ADDR_V1 \ + (BIT_MASK_H2C_READ_ADDR_V1 << BIT_SHIFT_H2C_READ_ADDR_V1) +#define BIT_CLEAR_H2C_READ_ADDR_V1(x) ((x) & (~BITS_H2C_READ_ADDR_V1)) +#define BIT_GET_H2C_READ_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_V1) & BIT_MASK_H2C_READ_ADDR_V1) +#define BIT_SET_H2C_READ_ADDR_V1(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_V1(x) | BIT_H2C_READ_ADDR_V1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */ -#define BIT_CLR_HI0Q_HW_IDX BIT(22) +#define BIT_SHIFT_H2C_WR_ADDR_V2 0 +#define BIT_MASK_H2C_WR_ADDR_V2 0xffff +#define BIT_H2C_WR_ADDR_V2(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_V2) << BIT_SHIFT_H2C_WR_ADDR_V2) +#define BITS_H2C_WR_ADDR_V2 \ + (BIT_MASK_H2C_WR_ADDR_V2 << BIT_SHIFT_H2C_WR_ADDR_V2) +#define BIT_CLEAR_H2C_WR_ADDR_V2(x) ((x) & (~BITS_H2C_WR_ADDR_V2)) +#define BIT_GET_H2C_WR_ADDR_V2(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_V2) & BIT_MASK_H2C_WR_ADDR_V2) +#define BIT_SET_H2C_WR_ADDR_V2(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_V2(x) | BIT_H2C_WR_ADDR_V2(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */ +#define BIT_SHIFT_H2C_WR_ADDR 0 +#define BIT_MASK_H2C_WR_ADDR 0x3ffff +#define BIT_H2C_WR_ADDR(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR) +#define BITS_H2C_WR_ADDR (BIT_MASK_H2C_WR_ADDR << BIT_SHIFT_H2C_WR_ADDR) +#define BIT_CLEAR_H2C_WR_ADDR(x) ((x) & (~BITS_H2C_WR_ADDR)) +#define BIT_GET_H2C_WR_ADDR(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR) +#define BIT_SET_H2C_WR_ADDR(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR(x) | BIT_H2C_WR_ADDR(v)) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_BCN6DOK BIT(22) -#define BIT_BCN6DOKM BIT(22) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */ +#define BIT_SHIFT_H2C_WR_ADDR_V1 0 +#define BIT_MASK_H2C_WR_ADDR_V1 0x7ffff +#define BIT_H2C_WR_ADDR_V1(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_V1) << BIT_SHIFT_H2C_WR_ADDR_V1) +#define BITS_H2C_WR_ADDR_V1 \ + (BIT_MASK_H2C_WR_ADDR_V1 << BIT_SHIFT_H2C_WR_ADDR_V1) +#define BIT_CLEAR_H2C_WR_ADDR_V1(x) ((x) & (~BITS_H2C_WR_ADDR_V1)) +#define BIT_GET_H2C_WR_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_V1) & BIT_MASK_H2C_WR_ADDR_V1) +#define BIT_SET_H2C_WR_ADDR_V1(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_V1(x) | BIT_H2C_WR_ADDR_V1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_H2C_INFO (Offset 0x0254) */ -#define BIT_CLR_BKQ_HW_IDX BIT(21) +#define BIT_SHIFT_MDIO_PHY_ADDR 24 +#define BIT_MASK_MDIO_PHY_ADDR 0x1f +#define BIT_MDIO_PHY_ADDR(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR) +#define BITS_MDIO_PHY_ADDR (BIT_MASK_MDIO_PHY_ADDR << BIT_SHIFT_MDIO_PHY_ADDR) +#define BIT_CLEAR_MDIO_PHY_ADDR(x) ((x) & (~BITS_MDIO_PHY_ADDR)) +#define BIT_GET_MDIO_PHY_ADDR(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR) +#define BIT_SET_MDIO_PHY_ADDR(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR(x) | BIT_MDIO_PHY_ADDR(v)) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - +/* 2 REG_H2C_INFO (Offset 0x0254) */ -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_SHIFT_VI_PUB_LIMIT 16 +#define BIT_MASK_VI_PUB_LIMIT 0xfff +#define BIT_VI_PUB_LIMIT(x) \ + (((x) & BIT_MASK_VI_PUB_LIMIT) << BIT_SHIFT_VI_PUB_LIMIT) +#define BITS_VI_PUB_LIMIT (BIT_MASK_VI_PUB_LIMIT << BIT_SHIFT_VI_PUB_LIMIT) +#define BIT_CLEAR_VI_PUB_LIMIT(x) ((x) & (~BITS_VI_PUB_LIMIT)) +#define BIT_GET_VI_PUB_LIMIT(x) \ + (((x) >> BIT_SHIFT_VI_PUB_LIMIT) & BIT_MASK_VI_PUB_LIMIT) +#define BIT_SET_VI_PUB_LIMIT(x, v) \ + (BIT_CLEAR_VI_PUB_LIMIT(x) | BIT_VI_PUB_LIMIT(v)) -#define BIT_BCN5DOK BIT(21) -#define BIT_BCN5DOKM BIT(21) +#define BIT_SHIFT_BK_PUB_LIMIT 16 +#define BIT_MASK_BK_PUB_LIMIT 0xfff +#define BIT_BK_PUB_LIMIT(x) \ + (((x) & BIT_MASK_BK_PUB_LIMIT) << BIT_SHIFT_BK_PUB_LIMIT) +#define BITS_BK_PUB_LIMIT (BIT_MASK_BK_PUB_LIMIT << BIT_SHIFT_BK_PUB_LIMIT) +#define BIT_CLEAR_BK_PUB_LIMIT(x) ((x) & (~BITS_BK_PUB_LIMIT)) +#define BIT_GET_BK_PUB_LIMIT(x) \ + (((x) >> BIT_SHIFT_BK_PUB_LIMIT) & BIT_MASK_BK_PUB_LIMIT) +#define BIT_SET_BK_PUB_LIMIT(x, v) \ + (BIT_CLEAR_BK_PUB_LIMIT(x) | BIT_BK_PUB_LIMIT(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_EX2Q_EN_PUBLIC_LIMIT BIT(13) +#define BIT_EX1Q_EN_PUBLIC_LIMIT BIT(12) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_BEQ_HW_IDX BIT(20) +#if (HALMAC_8197F_SUPPORT) -#endif +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_EXQ_EN_PUBLIC_LIMIT BIT(11) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_H2C_INFO (Offset 0x0254) */ -#define BIT_BCN4DOK BIT(20) -#define BIT_BCN4DOKM BIT(20) -#define BIT_RX_OVER_RD_ERR BIT(20) +#define BIT_EQ_EN_PUBLIC_LIMIT BIT(11) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_NPQ_EN_PUBLIC_LIMIT BIT(10) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_VIQ_HW_IDX BIT(19) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_NQ_EN_PUBLIC_LIMIT BIT(10) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_H2C_INFO (Offset 0x0254) */ -#define BIT_BCN3DOK BIT(19) -#define BIT_BCN3DOKM BIT(19) -#define BIT_RXDMA_STUCK BIT(19) +#define BIT_LPQ_EN_PUBLIC_LIMIT BIT(9) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_LQ_EN_PUBLIC_LIMIT BIT(9) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_VOQ_HW_IDX BIT(18) +#if (HALMAC_8197F_SUPPORT) -#endif +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_HPQ_EN_PUBLIC_LIMIT BIT(8) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_H2C_INFO (Offset 0x0254) */ -#define BIT_BCN2DOK BIT(18) -#define BIT_BCN2DOKM BIT(18) +#define BIT_HQ_EN_PUBLIC_LIMIT BIT(8) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_H2C_INFO (Offset 0x0254) */ -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_H2C_SPACE_VLD BIT(3) +#define BIT_H2C_WR_ADDR_RST BIT(2) -#define BIT_CLR_MGQ_HW_IDX BIT(17) +#define BIT_SHIFT_H2C_LEN_SEL 0 +#define BIT_MASK_H2C_LEN_SEL 0x3 +#define BIT_H2C_LEN_SEL(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL) +#define BITS_H2C_LEN_SEL (BIT_MASK_H2C_LEN_SEL << BIT_SHIFT_H2C_LEN_SEL) +#define BIT_CLEAR_H2C_LEN_SEL(x) ((x) & (~BITS_H2C_LEN_SEL)) +#define BIT_GET_H2C_LEN_SEL(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL) +#define BIT_SET_H2C_LEN_SEL(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL(x) | BIT_H2C_LEN_SEL(v)) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_H2C_INFO (Offset 0x0254) */ +#define BIT_SHIFT_VO_PUB_LIMIT 0 +#define BIT_MASK_VO_PUB_LIMIT 0xfff +#define BIT_VO_PUB_LIMIT(x) \ + (((x) & BIT_MASK_VO_PUB_LIMIT) << BIT_SHIFT_VO_PUB_LIMIT) +#define BITS_VO_PUB_LIMIT (BIT_MASK_VO_PUB_LIMIT << BIT_SHIFT_VO_PUB_LIMIT) +#define BIT_CLEAR_VO_PUB_LIMIT(x) ((x) & (~BITS_VO_PUB_LIMIT)) +#define BIT_GET_VO_PUB_LIMIT(x) \ + (((x) >> BIT_SHIFT_VO_PUB_LIMIT) & BIT_MASK_VO_PUB_LIMIT) +#define BIT_SET_VO_PUB_LIMIT(x, v) \ + (BIT_CLEAR_VO_PUB_LIMIT(x) | BIT_VO_PUB_LIMIT(v)) + +#define BIT_SHIFT_BE_PUB_LIMIT 0 +#define BIT_MASK_BE_PUB_LIMIT 0xfff +#define BIT_BE_PUB_LIMIT(x) \ + (((x) & BIT_MASK_BE_PUB_LIMIT) << BIT_SHIFT_BE_PUB_LIMIT) +#define BITS_BE_PUB_LIMIT (BIT_MASK_BE_PUB_LIMIT << BIT_SHIFT_BE_PUB_LIMIT) +#define BIT_CLEAR_BE_PUB_LIMIT(x) ((x) & (~BITS_BE_PUB_LIMIT)) +#define BIT_GET_BE_PUB_LIMIT(x) \ + (((x) >> BIT_SHIFT_BE_PUB_LIMIT) & BIT_MASK_BE_PUB_LIMIT) +#define BIT_SET_BE_PUB_LIMIT(x, v) \ + (BIT_CLEAR_BE_PUB_LIMIT(x) | BIT_BE_PUB_LIMIT(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DMA_OQT_0 (Offset 0x0260) */ + +#define BIT_SHIFT_TX_OQT_12_FREE_SPACE 24 +#define BIT_MASK_TX_OQT_12_FREE_SPACE 0xff +#define BIT_TX_OQT_12_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_12_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_12_FREE_SPACE) +#define BITS_TX_OQT_12_FREE_SPACE \ + (BIT_MASK_TX_OQT_12_FREE_SPACE << BIT_SHIFT_TX_OQT_12_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_12_FREE_SPACE)) +#define BIT_GET_TX_OQT_12_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_12_FREE_SPACE) & \ + BIT_MASK_TX_OQT_12_FREE_SPACE) +#define BIT_SET_TX_OQT_12_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) | BIT_TX_OQT_12_FREE_SPACE(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_TQPNT5 (Offset 0x0260) */ + +#define BIT_SHIFT_EX1Q_HIGH_TH_V1 16 +#define BIT_MASK_EX1Q_HIGH_TH_V1 0xfff +#define BIT_EX1Q_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_EX1Q_HIGH_TH_V1) << BIT_SHIFT_EX1Q_HIGH_TH_V1) +#define BITS_EX1Q_HIGH_TH_V1 \ + (BIT_MASK_EX1Q_HIGH_TH_V1 << BIT_SHIFT_EX1Q_HIGH_TH_V1) +#define BIT_CLEAR_EX1Q_HIGH_TH_V1(x) ((x) & (~BITS_EX1Q_HIGH_TH_V1)) +#define BIT_GET_EX1Q_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_EX1Q_HIGH_TH_V1) & BIT_MASK_EX1Q_HIGH_TH_V1) +#define BIT_SET_EX1Q_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_EX1Q_HIGH_TH_V1(x) | BIT_EX1Q_HIGH_TH_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DMA_OQT_0 (Offset 0x0260) */ + +#define BIT_SHIFT_TX_OQT_8_11_FREE_SPACE 16 +#define BIT_MASK_TX_OQT_8_11_FREE_SPACE 0xff +#define BIT_TX_OQT_8_11_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_8_11_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) +#define BITS_TX_OQT_8_11_FREE_SPACE \ + (BIT_MASK_TX_OQT_8_11_FREE_SPACE << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x) \ + ((x) & (~BITS_TX_OQT_8_11_FREE_SPACE)) +#define BIT_GET_TX_OQT_8_11_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) & \ + BIT_MASK_TX_OQT_8_11_FREE_SPACE) +#define BIT_SET_TX_OQT_8_11_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x) | BIT_TX_OQT_8_11_FREE_SPACE(v)) + +#define BIT_SHIFT_TX_OQT_16_FREE_SPACE 16 +#define BIT_MASK_TX_OQT_16_FREE_SPACE 0xff +#define BIT_TX_OQT_16_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_16_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_16_FREE_SPACE) +#define BITS_TX_OQT_16_FREE_SPACE \ + (BIT_MASK_TX_OQT_16_FREE_SPACE << BIT_SHIFT_TX_OQT_16_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_16_FREE_SPACE)) +#define BIT_GET_TX_OQT_16_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_16_FREE_SPACE) & \ + BIT_MASK_TX_OQT_16_FREE_SPACE) +#define BIT_SET_TX_OQT_16_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) | BIT_TX_OQT_16_FREE_SPACE(v)) + +#define BIT_SHIFT_TX_OQT_4_7_FREE_SPACE 8 +#define BIT_MASK_TX_OQT_4_7_FREE_SPACE 0xff +#define BIT_TX_OQT_4_7_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_4_7_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) +#define BITS_TX_OQT_4_7_FREE_SPACE \ + (BIT_MASK_TX_OQT_4_7_FREE_SPACE << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_4_7_FREE_SPACE)) +#define BIT_GET_TX_OQT_4_7_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) & \ + BIT_MASK_TX_OQT_4_7_FREE_SPACE) +#define BIT_SET_TX_OQT_4_7_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) | BIT_TX_OQT_4_7_FREE_SPACE(v)) + +#define BIT_SHIFT_TX_OQT_14_15_FREE_SPACE 8 +#define BIT_MASK_TX_OQT_14_15_FREE_SPACE 0xff +#define BIT_TX_OQT_14_15_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_14_15_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) +#define BITS_TX_OQT_14_15_FREE_SPACE \ + (BIT_MASK_TX_OQT_14_15_FREE_SPACE << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x) \ + ((x) & (~BITS_TX_OQT_14_15_FREE_SPACE)) +#define BIT_GET_TX_OQT_14_15_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) & \ + BIT_MASK_TX_OQT_14_15_FREE_SPACE) +#define BIT_SET_TX_OQT_14_15_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x) | BIT_TX_OQT_14_15_FREE_SPACE(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_TQPNT5 (Offset 0x0260) */ + +#define BIT_SHIFT_EX1Q_LOW_TH_V1 0 +#define BIT_MASK_EX1Q_LOW_TH_V1 0xfff +#define BIT_EX1Q_LOW_TH_V1(x) \ + (((x) & BIT_MASK_EX1Q_LOW_TH_V1) << BIT_SHIFT_EX1Q_LOW_TH_V1) +#define BITS_EX1Q_LOW_TH_V1 \ + (BIT_MASK_EX1Q_LOW_TH_V1 << BIT_SHIFT_EX1Q_LOW_TH_V1) +#define BIT_CLEAR_EX1Q_LOW_TH_V1(x) ((x) & (~BITS_EX1Q_LOW_TH_V1)) +#define BIT_GET_EX1Q_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_EX1Q_LOW_TH_V1) & BIT_MASK_EX1Q_LOW_TH_V1) +#define BIT_SET_EX1Q_LOW_TH_V1(x, v) \ + (BIT_CLEAR_EX1Q_LOW_TH_V1(x) | BIT_EX1Q_LOW_TH_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DMA_OQT_0 (Offset 0x0260) */ + +#define BIT_SHIFT_TX_OQT_0_3_FREE_SPACE 0 +#define BIT_MASK_TX_OQT_0_3_FREE_SPACE 0xff +#define BIT_TX_OQT_0_3_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_0_3_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) +#define BITS_TX_OQT_0_3_FREE_SPACE \ + (BIT_MASK_TX_OQT_0_3_FREE_SPACE << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_0_3_FREE_SPACE)) +#define BIT_GET_TX_OQT_0_3_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) & \ + BIT_MASK_TX_OQT_0_3_FREE_SPACE) +#define BIT_SET_TX_OQT_0_3_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) | BIT_TX_OQT_0_3_FREE_SPACE(v)) + +#define BIT_SHIFT_TX_OQT_13_FREE_SPACE 0 +#define BIT_MASK_TX_OQT_13_FREE_SPACE 0xff +#define BIT_TX_OQT_13_FREE_SPACE(x) \ + (((x) & BIT_MASK_TX_OQT_13_FREE_SPACE) \ + << BIT_SHIFT_TX_OQT_13_FREE_SPACE) +#define BITS_TX_OQT_13_FREE_SPACE \ + (BIT_MASK_TX_OQT_13_FREE_SPACE << BIT_SHIFT_TX_OQT_13_FREE_SPACE) +#define BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_13_FREE_SPACE)) +#define BIT_GET_TX_OQT_13_FREE_SPACE(x) \ + (((x) >> BIT_SHIFT_TX_OQT_13_FREE_SPACE) & \ + BIT_MASK_TX_OQT_13_FREE_SPACE) +#define BIT_SET_TX_OQT_13_FREE_SPACE(x, v) \ + (BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) | BIT_TX_OQT_13_FREE_SPACE(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_TQPNT6 (Offset 0x0264) */ + +#define BIT_SHIFT_EX2Q_HIGH_TH_V1 16 +#define BIT_MASK_EX2Q_HIGH_TH_V1 0xfff +#define BIT_EX2Q_HIGH_TH_V1(x) \ + (((x) & BIT_MASK_EX2Q_HIGH_TH_V1) << BIT_SHIFT_EX2Q_HIGH_TH_V1) +#define BITS_EX2Q_HIGH_TH_V1 \ + (BIT_MASK_EX2Q_HIGH_TH_V1 << BIT_SHIFT_EX2Q_HIGH_TH_V1) +#define BIT_CLEAR_EX2Q_HIGH_TH_V1(x) ((x) & (~BITS_EX2Q_HIGH_TH_V1)) +#define BIT_GET_EX2Q_HIGH_TH_V1(x) \ + (((x) >> BIT_SHIFT_EX2Q_HIGH_TH_V1) & BIT_MASK_EX2Q_HIGH_TH_V1) +#define BIT_SET_EX2Q_HIGH_TH_V1(x, v) \ + (BIT_CLEAR_EX2Q_HIGH_TH_V1(x) | BIT_EX2Q_HIGH_TH_V1(v)) + +#define BIT_SHIFT_EX2Q_LOW_TH_V1 0 +#define BIT_MASK_EX2Q_LOW_TH_V1 0xfff +#define BIT_EX2Q_LOW_TH_V1(x) \ + (((x) & BIT_MASK_EX2Q_LOW_TH_V1) << BIT_SHIFT_EX2Q_LOW_TH_V1) +#define BITS_EX2Q_LOW_TH_V1 \ + (BIT_MASK_EX2Q_LOW_TH_V1 << BIT_SHIFT_EX2Q_LOW_TH_V1) +#define BIT_CLEAR_EX2Q_LOW_TH_V1(x) ((x) & (~BITS_EX2Q_LOW_TH_V1)) +#define BIT_GET_EX2Q_LOW_TH_V1(x) \ + (((x) >> BIT_SHIFT_EX2Q_LOW_TH_V1) & BIT_MASK_EX2Q_LOW_TH_V1) +#define BIT_SET_EX2Q_LOW_TH_V1(x, v) \ + (BIT_CLEAR_EX2Q_LOW_TH_V1(x) | BIT_EX2Q_LOW_TH_V1(v)) + +/* 2 REG_FIFOPAGE_INFO_6 (Offset 0x0268) */ + +#define BIT_SHIFT_EX1Q_AVAL_PG_V1 16 +#define BIT_MASK_EX1Q_AVAL_PG_V1 0xfff +#define BIT_EX1Q_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_EX1Q_AVAL_PG_V1) << BIT_SHIFT_EX1Q_AVAL_PG_V1) +#define BITS_EX1Q_AVAL_PG_V1 \ + (BIT_MASK_EX1Q_AVAL_PG_V1 << BIT_SHIFT_EX1Q_AVAL_PG_V1) +#define BIT_CLEAR_EX1Q_AVAL_PG_V1(x) ((x) & (~BITS_EX1Q_AVAL_PG_V1)) +#define BIT_GET_EX1Q_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_EX1Q_AVAL_PG_V1) & BIT_MASK_EX1Q_AVAL_PG_V1) +#define BIT_SET_EX1Q_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_EX1Q_AVAL_PG_V1(x) | BIT_EX1Q_AVAL_PG_V1(v)) + +#define BIT_SHIFT_EX1Q_V1 0 +#define BIT_MASK_EX1Q_V1 0xfff +#define BIT_EX1Q_V1(x) (((x) & BIT_MASK_EX1Q_V1) << BIT_SHIFT_EX1Q_V1) +#define BITS_EX1Q_V1 (BIT_MASK_EX1Q_V1 << BIT_SHIFT_EX1Q_V1) +#define BIT_CLEAR_EX1Q_V1(x) ((x) & (~BITS_EX1Q_V1)) +#define BIT_GET_EX1Q_V1(x) (((x) >> BIT_SHIFT_EX1Q_V1) & BIT_MASK_EX1Q_V1) +#define BIT_SET_EX1Q_V1(x, v) (BIT_CLEAR_EX1Q_V1(x) | BIT_EX1Q_V1(v)) + +/* 2 REG_FIFOPAGE_INFO_7 (Offset 0x026C) */ + +#define BIT_SHIFT_EX2Q_AVAL_PG_V1 16 +#define BIT_MASK_EX2Q_AVAL_PG_V1 0xfff +#define BIT_EX2Q_AVAL_PG_V1(x) \ + (((x) & BIT_MASK_EX2Q_AVAL_PG_V1) << BIT_SHIFT_EX2Q_AVAL_PG_V1) +#define BITS_EX2Q_AVAL_PG_V1 \ + (BIT_MASK_EX2Q_AVAL_PG_V1 << BIT_SHIFT_EX2Q_AVAL_PG_V1) +#define BIT_CLEAR_EX2Q_AVAL_PG_V1(x) ((x) & (~BITS_EX2Q_AVAL_PG_V1)) +#define BIT_GET_EX2Q_AVAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_EX2Q_AVAL_PG_V1) & BIT_MASK_EX2Q_AVAL_PG_V1) +#define BIT_SET_EX2Q_AVAL_PG_V1(x, v) \ + (BIT_CLEAR_EX2Q_AVAL_PG_V1(x) | BIT_EX2Q_AVAL_PG_V1(v)) + +#define BIT_SHIFT_EX2Q_V1 0 +#define BIT_MASK_EX2Q_V1 0xfff +#define BIT_EX2Q_V1(x) (((x) & BIT_MASK_EX2Q_V1) << BIT_SHIFT_EX2Q_V1) +#define BITS_EX2Q_V1 (BIT_MASK_EX2Q_V1 << BIT_SHIFT_EX2Q_V1) +#define BIT_CLEAR_EX2Q_V1(x) ((x) & (~BITS_EX2Q_V1)) +#define BIT_GET_EX2Q_V1(x) (((x) >> BIT_SHIFT_EX2Q_V1) & BIT_MASK_EX2Q_V1) +#define BIT_SET_EX2Q_V1(x, v) (BIT_CLEAR_EX2Q_V1(x) | BIT_EX2Q_V1(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_PGSUB_H (Offset 0x0270) */ + +#define BIT_SHIFT_HPQ_PGSUB_CNT 0 +#define BIT_MASK_HPQ_PGSUB_CNT 0xffffffffL +#define BIT_HPQ_PGSUB_CNT(x) \ + (((x) & BIT_MASK_HPQ_PGSUB_CNT) << BIT_SHIFT_HPQ_PGSUB_CNT) +#define BITS_HPQ_PGSUB_CNT (BIT_MASK_HPQ_PGSUB_CNT << BIT_SHIFT_HPQ_PGSUB_CNT) +#define BIT_CLEAR_HPQ_PGSUB_CNT(x) ((x) & (~BITS_HPQ_PGSUB_CNT)) +#define BIT_GET_HPQ_PGSUB_CNT(x) \ + (((x) >> BIT_SHIFT_HPQ_PGSUB_CNT) & BIT_MASK_HPQ_PGSUB_CNT) +#define BIT_SET_HPQ_PGSUB_CNT(x, v) \ + (BIT_CLEAR_HPQ_PGSUB_CNT(x) | BIT_HPQ_PGSUB_CNT(v)) + +/* 2 REG_PGSUB_N (Offset 0x0274) */ + +#define BIT_SHIFT_NPQ_PGSUB_CNT 0 +#define BIT_MASK_NPQ_PGSUB_CNT 0xffffffffL +#define BIT_NPQ_PGSUB_CNT(x) \ + (((x) & BIT_MASK_NPQ_PGSUB_CNT) << BIT_SHIFT_NPQ_PGSUB_CNT) +#define BITS_NPQ_PGSUB_CNT (BIT_MASK_NPQ_PGSUB_CNT << BIT_SHIFT_NPQ_PGSUB_CNT) +#define BIT_CLEAR_NPQ_PGSUB_CNT(x) ((x) & (~BITS_NPQ_PGSUB_CNT)) +#define BIT_GET_NPQ_PGSUB_CNT(x) \ + (((x) >> BIT_SHIFT_NPQ_PGSUB_CNT) & BIT_MASK_NPQ_PGSUB_CNT) +#define BIT_SET_NPQ_PGSUB_CNT(x, v) \ + (BIT_CLEAR_NPQ_PGSUB_CNT(x) | BIT_NPQ_PGSUB_CNT(v)) + +/* 2 REG_PGSUB_L (Offset 0x0278) */ + +#define BIT_SHIFT_LPQ_PGSUB_CNT 0 +#define BIT_MASK_LPQ_PGSUB_CNT 0xffffffffL +#define BIT_LPQ_PGSUB_CNT(x) \ + (((x) & BIT_MASK_LPQ_PGSUB_CNT) << BIT_SHIFT_LPQ_PGSUB_CNT) +#define BITS_LPQ_PGSUB_CNT (BIT_MASK_LPQ_PGSUB_CNT << BIT_SHIFT_LPQ_PGSUB_CNT) +#define BIT_CLEAR_LPQ_PGSUB_CNT(x) ((x) & (~BITS_LPQ_PGSUB_CNT)) +#define BIT_GET_LPQ_PGSUB_CNT(x) \ + (((x) >> BIT_SHIFT_LPQ_PGSUB_CNT) & BIT_MASK_LPQ_PGSUB_CNT) +#define BIT_SET_LPQ_PGSUB_CNT(x, v) \ + (BIT_CLEAR_LPQ_PGSUB_CNT(x) | BIT_LPQ_PGSUB_CNT(v)) + +/* 2 REG_PGSUB_E (Offset 0x027C) */ + +#define BIT_SHIFT_EPQ_PGSUB_CNT 0 +#define BIT_MASK_EPQ_PGSUB_CNT 0xffffffffL +#define BIT_EPQ_PGSUB_CNT(x) \ + (((x) & BIT_MASK_EPQ_PGSUB_CNT) << BIT_SHIFT_EPQ_PGSUB_CNT) +#define BITS_EPQ_PGSUB_CNT (BIT_MASK_EPQ_PGSUB_CNT << BIT_SHIFT_EPQ_PGSUB_CNT) +#define BIT_CLEAR_EPQ_PGSUB_CNT(x) ((x) & (~BITS_EPQ_PGSUB_CNT)) +#define BIT_GET_EPQ_PGSUB_CNT(x) \ + (((x) >> BIT_SHIFT_EPQ_PGSUB_CNT) & BIT_MASK_EPQ_PGSUB_CNT) +#define BIT_SET_EPQ_PGSUB_CNT(x, v) \ + (BIT_CLEAR_EPQ_PGSUB_CNT(x) | BIT_EPQ_PGSUB_CNT(v)) + +#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V2 0 +#define BIT_MASK_FWFF_PKT_STR_ADDR_V2 0x3fff +#define BIT_FWFF_PKT_STR_ADDR_V2(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V2) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) +#define BITS_FWFF_PKT_STR_ADDR_V2 \ + (BIT_MASK_FWFF_PKT_STR_ADDR_V2 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V2)) +#define BIT_GET_FWFF_PKT_STR_ADDR_V2(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_V2) +#define BIT_SET_FWFF_PKT_STR_ADDR_V2(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) | BIT_FWFF_PKT_STR_ADDR_V2(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ -#define BIT_BCN1DOK BIT(17) -#define BIT_BCN1DOKM BIT(17) +#define BIT_USB_RXDMA_AGG_EN BIT(31) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_RXDMA_AGG_OLD_MOD_V1 BIT(31) -/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ +#endif +#if (HALMAC_8197F_SUPPORT) -#define BIT_SHIFT_TSFT2_HCI 16 -#define BIT_MASK_TSFT2_HCI 0xffff -#define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI) -#define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ -#define BIT_CLR_RXQ_HW_IDX BIT(16) +#define BIT_DMA_STORE_MODE BIT(31) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_DMA_STORE BIT(31) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_BCN0DOK BIT(16) -#define BIT_BCN0DOKM BIT(16) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RX_STATE 16 -#define BIT_MASK_RX_STATE 0x7 -#define BIT_RX_STATE(x) (((x) & BIT_MASK_RX_STATE) << BIT_SHIFT_RX_STATE) -#define BIT_GET_RX_STATE(x) (((x) >> BIT_SHIFT_RX_STATE) & BIT_MASK_RX_STATE) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ -#define BIT_SRST_TX BIT(15) -#define BIT_M7DOK BIT(15) -#define BIT_M7DOKM BIT(15) -#define BIT_TDE_NO_IDLE BIT(15) -#define BIT_SRST_RX BIT(14) -#define BIT_M6DOK BIT(14) -#define BIT_M6DOKM BIT(14) -#define BIT_TXDMA_STUCK BIT(14) +#define BIT_EN_FW_ADD BIT(30) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_RXAGG_TH_MODE BIT(29) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_HI7Q_HOST_IDX BIT(13) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_EN_PRE_CALC BIT(29) +#define BIT_RXAGG_SW_EN BIT(28) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ -#define BIT_M5DOK BIT(13) -#define BIT_M5DOKM BIT(13) -#define BIT_TDE_FULL_ERR BIT(13) +#define BIT_RXAGG_SW_TRIG BIT(27) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24 +#define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff +#define BIT_RXDMA_AGG_OLD_MOD(x) \ + (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD) +#define BITS_RXDMA_AGG_OLD_MOD \ + (BIT_MASK_RXDMA_AGG_OLD_MOD << BIT_SHIFT_RXDMA_AGG_OLD_MOD) +#define BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) ((x) & (~BITS_RXDMA_AGG_OLD_MOD)) +#define BIT_GET_RXDMA_AGG_OLD_MOD(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD) +#define BIT_SET_RXDMA_AGG_OLD_MOD(x, v) \ + (BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) | BIT_RXDMA_AGG_OLD_MOD(v)) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_HI6Q_HOST_IDX BIT(12) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SHIFT_PKT_NUM_WOL 16 +#define BIT_MASK_PKT_NUM_WOL 0xff +#define BIT_PKT_NUM_WOL(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL) +#define BITS_PKT_NUM_WOL (BIT_MASK_PKT_NUM_WOL << BIT_SHIFT_PKT_NUM_WOL) +#define BIT_CLEAR_PKT_NUM_WOL(x) ((x) & (~BITS_PKT_NUM_WOL)) +#define BIT_GET_PKT_NUM_WOL(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL) +#define BIT_SET_PKT_NUM_WOL(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL(x) | BIT_PKT_NUM_WOL(v)) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ -#define BIT_M4DOK BIT(12) -#define BIT_M4DOKM BIT(12) -#define BIT_HD_SIZE_ERR BIT(12) +#define BIT_SHIFT_DMA_AGG_TO_V1 8 +#define BIT_MASK_DMA_AGG_TO_V1 0xff +#define BIT_DMA_AGG_TO_V1(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1) << BIT_SHIFT_DMA_AGG_TO_V1) +#define BITS_DMA_AGG_TO_V1 (BIT_MASK_DMA_AGG_TO_V1 << BIT_SHIFT_DMA_AGG_TO_V1) +#define BIT_CLEAR_DMA_AGG_TO_V1(x) ((x) & (~BITS_DMA_AGG_TO_V1)) +#define BIT_GET_DMA_AGG_TO_V1(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1) & BIT_MASK_DMA_AGG_TO_V1) +#define BIT_SET_DMA_AGG_TO_V1(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1(x) | BIT_DMA_AGG_TO_V1(v)) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SHIFT_DMA_AGG_TO 8 +#define BIT_MASK_DMA_AGG_TO 0xf +#define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO) +#define BITS_DMA_AGG_TO (BIT_MASK_DMA_AGG_TO << BIT_SHIFT_DMA_AGG_TO) +#define BIT_CLEAR_DMA_AGG_TO(x) ((x) & (~BITS_DMA_AGG_TO)) +#define BIT_GET_DMA_AGG_TO(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO) +#define BIT_SET_DMA_AGG_TO(x, v) (BIT_CLEAR_DMA_AGG_TO(x) | BIT_DMA_AGG_TO(v)) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_HI5Q_HOST_IDX BIT(11) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf +#define BIT_RXDMA_AGG_PG_TH_V1(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1) +#define BITS_RXDMA_AGG_PG_TH_V1 \ + (BIT_MASK_RXDMA_AGG_PG_TH_V1 << BIT_SHIFT_RXDMA_AGG_PG_TH_V1) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V1)) +#define BIT_GET_RXDMA_AGG_PG_TH_V1(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1) +#define BIT_SET_RXDMA_AGG_PG_TH_V1(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) | BIT_RXDMA_AGG_PG_TH_V1(v)) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ -#define BIT_M3DOK BIT(11) -#define BIT_M3DOKM BIT(11) +#define BIT_SHIFT_RXDMA_AGG_PG_TH 0 +#define BIT_MASK_RXDMA_AGG_PG_TH 0xff +#define BIT_RXDMA_AGG_PG_TH(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH) << BIT_SHIFT_RXDMA_AGG_PG_TH) +#define BITS_RXDMA_AGG_PG_TH \ + (BIT_MASK_RXDMA_AGG_PG_TH << BIT_SHIFT_RXDMA_AGG_PG_TH) +#define BIT_CLEAR_RXDMA_AGG_PG_TH(x) ((x) & (~BITS_RXDMA_AGG_PG_TH)) +#define BIT_GET_RXDMA_AGG_PG_TH(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH) & BIT_MASK_RXDMA_AGG_PG_TH) +#define BIT_SET_RXDMA_AGG_PG_TH(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH(x) | BIT_RXDMA_AGG_PG_TH(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SHIFT_QINFO_INDEX 0 +#define BIT_MASK_QINFO_INDEX 0x1f +#define BIT_QINFO_INDEX(x) \ + (((x) & BIT_MASK_QINFO_INDEX) << BIT_SHIFT_QINFO_INDEX) +#define BITS_QINFO_INDEX (BIT_MASK_QINFO_INDEX << BIT_SHIFT_QINFO_INDEX) +#define BIT_CLEAR_QINFO_INDEX(x) ((x) & (~BITS_QINFO_INDEX)) +#define BIT_GET_QINFO_INDEX(x) \ + (((x) >> BIT_SHIFT_QINFO_INDEX) & BIT_MASK_QINFO_INDEX) +#define BIT_SET_QINFO_INDEX(x, v) \ + (BIT_CLEAR_QINFO_INDEX(x) | BIT_QINFO_INDEX(v)) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_HI4Q_HOST_IDX BIT(10) +#if (HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ +#define BIT_SHIFT_RXDMA_AGG_PG_TH_V2 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_V2 0xff +#define BIT_RXDMA_AGG_PG_TH_V2(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V2) << BIT_SHIFT_RXDMA_AGG_PG_TH_V2) +#define BITS_RXDMA_AGG_PG_TH_V2 \ + (BIT_MASK_RXDMA_AGG_PG_TH_V2 << BIT_SHIFT_RXDMA_AGG_PG_TH_V2) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V2)) +#define BIT_GET_RXDMA_AGG_PG_TH_V2(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V2) & BIT_MASK_RXDMA_AGG_PG_TH_V2) +#define BIT_SET_RXDMA_AGG_PG_TH_V2(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) | BIT_RXDMA_AGG_PG_TH_V2(v)) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_RXPKT_NUM (Offset 0x0284) */ -#define BIT_M2DOK BIT(10) -#define BIT_M2DOKM BIT(10) +#define BIT_SHIFT_RXPKT_NUM 24 +#define BIT_MASK_RXPKT_NUM 0xff +#define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM) +#define BITS_RXPKT_NUM (BIT_MASK_RXPKT_NUM << BIT_SHIFT_RXPKT_NUM) +#define BIT_CLEAR_RXPKT_NUM(x) ((x) & (~BITS_RXPKT_NUM)) +#define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM) +#define BIT_SET_RXPKT_NUM(x, v) (BIT_CLEAR_RXPKT_NUM(x) | BIT_RXPKT_NUM(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXPKT_NUM (Offset 0x0284) */ - -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ - -#define BIT_CLR_HI3Q_HOST_IDX BIT(9) +#define BIT_STOP_RXDMA BIT(20) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - - -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_RXPKT_NUM (Offset 0x0284) */ -#define BIT_M1DOK BIT(9) -#define BIT_M1DOKM BIT(9) +#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20 +#define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf +#define BIT_FW_UPD_RDPTR19_TO_16(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16) +#define BITS_FW_UPD_RDPTR19_TO_16 \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) ((x) & (~BITS_FW_UPD_RDPTR19_TO_16)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16) +#define BIT_SET_FW_UPD_RDPTR19_TO_16(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) | BIT_FW_UPD_RDPTR19_TO_16(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_RXPKT_NUM (Offset 0x0284) */ -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_RXDMA_REQ BIT(19) +#define BIT_RW_RELEASE_EN BIT(18) +#define BIT_RXDMA_IDLE BIT(17) +#define BIT_RXPKT_RELEASE_POLL BIT(16) -#define BIT_CLR_HI2Q_HOST_IDX BIT(8) +#define BIT_SHIFT_FW_UPD_RDPTR 0 +#define BIT_MASK_FW_UPD_RDPTR 0xffff +#define BIT_FW_UPD_RDPTR(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR) +#define BITS_FW_UPD_RDPTR (BIT_MASK_FW_UPD_RDPTR << BIT_SHIFT_FW_UPD_RDPTR) +#define BIT_CLEAR_FW_UPD_RDPTR(x) ((x) & (~BITS_FW_UPD_RDPTR)) +#define BIT_GET_FW_UPD_RDPTR(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR) +#define BIT_SET_FW_UPD_RDPTR(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR(x) | BIT_FW_UPD_RDPTR(v)) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#define BIT_FC2H_PKT_OVERFLOW BIT(8) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_M0DOK BIT(8) -#define BIT_M0DOKM BIT(8) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TX_STATE 8 -#define BIT_MASK_TX_STATE 0xf -#define BIT_TX_STATE(x) (((x) & BIT_MASK_TX_STATE) << BIT_SHIFT_TX_STATE) -#define BIT_GET_TX_STATE(x) (((x) >> BIT_SHIFT_TX_STATE) & BIT_MASK_TX_STATE) +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#define BIT_C2H_PKT_OVF BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ -#define BIT_CLR_HI1Q_HOST_IDX BIT(7) -#define BIT_CLR_HI0Q_HOST_IDX BIT(6) +#define BIT_AGG_CFG_ISSUE BIT(6) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#define BIT_AGG_CONFGI_ISSUE BIT(6) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_MGQDOK BIT(6) -#define BIT_MGQDOKM BIT(6) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#define BIT_FW_POLL_ISSUE BIT(5) +#define BIT_RX_DATA_UDN BIT(4) +#define BIT_RX_SFF_UDN BIT(3) +#define BIT_RX_SFF_OVF BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ -#define BIT_CLR_BKQ_HOST_IDX BIT(5) +#define BIT_USB_REQ_LEN_OVF BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_STATUS (Offset 0x0288) */ +#define BIT_RXPKT_OVF BIT(0) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_RXDMA_DPR (Offset 0x028C) */ -#define BIT_BKQDOK BIT(5) -#define BIT_BKQDOKM BIT(5) +#define BIT_SHIFT_RDE_DEBUG 0 +#define BIT_MASK_RDE_DEBUG 0xffffffffL +#define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG) +#define BITS_RDE_DEBUG (BIT_MASK_RDE_DEBUG << BIT_SHIFT_RDE_DEBUG) +#define BIT_CLEAR_RDE_DEBUG(x) ((x) & (~BITS_RDE_DEBUG)) +#define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG) +#define BIT_SET_RDE_DEBUG(x, v) (BIT_CLEAR_RDE_DEBUG(x) | BIT_RDE_DEBUG(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_SHIFT_PKTNUM_TH_V2 24 +#define BIT_MASK_PKTNUM_TH_V2 0x1f +#define BIT_PKTNUM_TH_V2(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2) +#define BITS_PKTNUM_TH_V2 (BIT_MASK_PKTNUM_TH_V2 << BIT_SHIFT_PKTNUM_TH_V2) +#define BIT_CLEAR_PKTNUM_TH_V2(x) ((x) & (~BITS_PKTNUM_TH_V2)) +#define BIT_GET_PKTNUM_TH_V2(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2) +#define BIT_SET_PKTNUM_TH_V2(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V2(x) | BIT_PKTNUM_TH_V2(v)) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_TXBA_BREAK_USBAGG BIT(23) -#define BIT_CLR_BEQ_HOST_IDX BIT(4) +#define BIT_SHIFT_PKTLEN_PARA 16 +#define BIT_MASK_PKTLEN_PARA 0x7 +#define BIT_PKTLEN_PARA(x) \ + (((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA) +#define BITS_PKTLEN_PARA (BIT_MASK_PKTLEN_PARA << BIT_SHIFT_PKTLEN_PARA) +#define BIT_CLEAR_PKTLEN_PARA(x) ((x) & (~BITS_PKTLEN_PARA)) +#define BIT_GET_PKTLEN_PARA(x) \ + (((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA) +#define BIT_SET_PKTLEN_PARA(x, v) \ + (BIT_CLEAR_PKTLEN_PARA(x) | BIT_PKTLEN_PARA(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_EN_SDIO_FAIL BIT(9) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_HPS_CLKR 4 -#define BIT_MASK_HPS_CLKR 0x3 -#define BIT_HPS_CLKR(x) (((x) & BIT_MASK_HPS_CLKR) << BIT_SHIFT_HPS_CLKR) -#define BIT_GET_HPS_CLKR(x) (((x) >> BIT_SHIFT_HPS_CLKR) & BIT_MASK_HPS_CLKR) +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ -#define BIT_BEQDOK BIT(4) -#define BIT_BEQDOKM BIT(4) +#define BIT_GRAYCODE_SYNC_WITH_BIN BIT(8) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_RXDMA_DBD_SEL BIT(7) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_CLR_VIQ_HOST_IDX BIT(3) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_RX_DBG_SEL BIT(7) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ -#define BIT_LX_INT BIT(3) -#define BIT_VIQDOK BIT(3) -#define BIT_VIQDOKM BIT(3) -#define BIT_MST_BUSY BIT(3) +#define BIT_EN_SPD BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_SHIFT_BURST_SIZE 4 +#define BIT_MASK_BURST_SIZE 0x3 +#define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE) +#define BITS_BURST_SIZE (BIT_MASK_BURST_SIZE << BIT_SHIFT_BURST_SIZE) +#define BIT_CLEAR_BURST_SIZE(x) ((x) & (~BITS_BURST_SIZE)) +#define BIT_GET_BURST_SIZE(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE) +#define BIT_SET_BURST_SIZE(x, v) (BIT_CLEAR_BURST_SIZE(x) | BIT_BURST_SIZE(v)) -#define BIT_CLR_VOQ_HOST_IDX BIT(2) +#define BIT_SHIFT_BURST_CNT 2 +#define BIT_MASK_BURST_CNT 0x3 +#define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT) +#define BITS_BURST_CNT (BIT_MASK_BURST_CNT << BIT_SHIFT_BURST_CNT) +#define BIT_CLEAR_BURST_CNT(x) ((x) & (~BITS_BURST_CNT)) +#define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT) +#define BIT_SET_BURST_CNT(x, v) (BIT_CLEAR_BURST_CNT(x) | BIT_BURST_CNT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_DAM_MODE BIT(1) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#endif -#define BIT_VOQDOK BIT(2) -#define BIT_VOQDOKM BIT(2) -#define BIT_SLV_BUSY BIT(2) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_RXDMA_MODE (Offset 0x0290) */ +#define BIT_DMA_MODE BIT(1) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_C2H_PKT (Offset 0x0294) */ -#define BIT_CLR_MGQ_HOST_IDX BIT(1) +#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24 +#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf +#define BIT_R_C2H_STR_ADDR_16_TO_19(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) +#define BITS_R_C2H_STR_ADDR_16_TO_19 \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x) | BIT_R_C2H_STR_ADDR_16_TO_19(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - +/* 2 REG_C2H_PKT (Offset 0x0294) */ -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_R_C2H_PKT_REQ BIT(16) -#define BIT_RDUM BIT(1) -#define BIT_RXDES_UNAVAIL BIT(1) +#define BIT_SHIFT_R_C2H_STR_ADDR 0 +#define BIT_MASK_R_C2H_STR_ADDR 0xffff +#define BIT_R_C2H_STR_ADDR(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR) +#define BITS_R_C2H_STR_ADDR \ + (BIT_MASK_R_C2H_STR_ADDR << BIT_SHIFT_R_C2H_STR_ADDR) +#define BIT_CLEAR_R_C2H_STR_ADDR(x) ((x) & (~BITS_R_C2H_STR_ADDR)) +#define BIT_GET_R_C2H_STR_ADDR(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR) +#define BIT_SET_R_C2H_STR_ADDR(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR(x) | BIT_R_C2H_STR_ADDR(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWFF_C2H (Offset 0x0298) */ +#define BIT_SHIFT_C2H_DMA_ADDR 0 +#define BIT_MASK_C2H_DMA_ADDR 0x3ffff +#define BIT_C2H_DMA_ADDR(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR) +#define BITS_C2H_DMA_ADDR (BIT_MASK_C2H_DMA_ADDR << BIT_SHIFT_C2H_DMA_ADDR) +#define BIT_CLEAR_C2H_DMA_ADDR(x) ((x) & (~BITS_C2H_DMA_ADDR)) +#define BIT_GET_C2H_DMA_ADDR(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR) +#define BIT_SET_C2H_DMA_ADDR(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR(x) | BIT_C2H_DMA_ADDR(v)) -/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ +/* 2 REG_FWFF_CTRL (Offset 0x029C) */ +#define BIT_FWFF_DMAPKT_REQ BIT(31) -#define BIT_SHIFT_TSFT1_HCI 0 -#define BIT_MASK_TSFT1_HCI 0xffff -#define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI) -#define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI) +#endif -#define BIT_CLR_RXQ_HOST_IDX BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FWFF_CTRL (Offset 0x029C) */ +#define BIT_SHIFT_FWFF_DMA_PKT_NUM 16 +#define BIT_MASK_FWFF_DMA_PKT_NUM 0xff +#define BIT_FWFF_DMA_PKT_NUM(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM) +#define BITS_FWFF_DMA_PKT_NUM \ + (BIT_MASK_FWFF_DMA_PKT_NUM << BIT_SHIFT_FWFF_DMA_PKT_NUM) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM)) +#define BIT_GET_FWFF_DMA_PKT_NUM(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM) +#define BIT_SET_FWFF_DMA_PKT_NUM(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM(x) | BIT_FWFF_DMA_PKT_NUM(v)) -#if (HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +/* 2 REG_FWFF_CTRL (Offset 0x029C) */ -#define BIT_RXDOK BIT(0) -#define BIT_RXDOKM BIT(0) -#define BIT_EN_DBG_STUCK BIT(0) +#define BIT_SHIFT_FWFF_DMA_PKT_NUM_V1 16 +#define BIT_MASK_FWFF_DMA_PKT_NUM_V1 0x7fff +#define BIT_FWFF_DMA_PKT_NUM_V1(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_V1) << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) +#define BITS_FWFF_DMA_PKT_NUM_V1 \ + (BIT_MASK_FWFF_DMA_PKT_NUM_V1 << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM_V1)) +#define BIT_GET_FWFF_DMA_PKT_NUM_V1(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) & BIT_MASK_FWFF_DMA_PKT_NUM_V1) +#define BIT_SET_FWFF_DMA_PKT_NUM_V1(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) | BIT_FWFF_DMA_PKT_NUM_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWFF_CTRL (Offset 0x029C) */ +#define BIT_SHIFT_FWFF_STR_ADDR 0 +#define BIT_MASK_FWFF_STR_ADDR 0xffff +#define BIT_FWFF_STR_ADDR(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR) +#define BITS_FWFF_STR_ADDR (BIT_MASK_FWFF_STR_ADDR << BIT_SHIFT_FWFF_STR_ADDR) +#define BIT_CLEAR_FWFF_STR_ADDR(x) ((x) & (~BITS_FWFF_STR_ADDR)) +#define BIT_GET_FWFF_STR_ADDR(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR) +#define BIT_SET_FWFF_STR_ADDR(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR(x) | BIT_FWFF_STR_ADDR(v)) -/* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_VOQ_HW_IDX 16 -#define BIT_MASK_VOQ_HW_IDX 0xfff -#define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX) -#define BIT_GET_VOQ_HW_IDX(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX) +/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#define BIT_SHIFT_FWFF_PKT_QUEUED 16 +#define BIT_MASK_FWFF_PKT_QUEUED 0xff +#define BIT_FWFF_PKT_QUEUED(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED) +#define BITS_FWFF_PKT_QUEUED \ + (BIT_MASK_FWFF_PKT_QUEUED << BIT_SHIFT_FWFF_PKT_QUEUED) +#define BIT_CLEAR_FWFF_PKT_QUEUED(x) ((x) & (~BITS_FWFF_PKT_QUEUED)) +#define BIT_GET_FWFF_PKT_QUEUED(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED) +#define BIT_SET_FWFF_PKT_QUEUED(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED(x) | BIT_FWFF_PKT_QUEUED(v)) -#define BIT_SHIFT_VOQ_HOST_IDX 0 -#define BIT_MASK_VOQ_HOST_IDX 0xfff -#define BIT_VOQ_HOST_IDX(x) (((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX) -#define BIT_GET_VOQ_HOST_IDX(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */ +/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#define BIT_SHIFT_FWFF_PKT_READ_ADDR 16 +#define BIT_MASK_FWFF_PKT_READ_ADDR 0xffff +#define BIT_FWFF_PKT_READ_ADDR(x) \ + (((x) & BIT_MASK_FWFF_PKT_READ_ADDR) << BIT_SHIFT_FWFF_PKT_READ_ADDR) +#define BITS_FWFF_PKT_READ_ADDR \ + (BIT_MASK_FWFF_PKT_READ_ADDR << BIT_SHIFT_FWFF_PKT_READ_ADDR) +#define BIT_CLEAR_FWFF_PKT_READ_ADDR(x) ((x) & (~BITS_FWFF_PKT_READ_ADDR)) +#define BIT_GET_FWFF_PKT_READ_ADDR(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_READ_ADDR) & BIT_MASK_FWFF_PKT_READ_ADDR) +#define BIT_SET_FWFF_PKT_READ_ADDR(x, v) \ + (BIT_CLEAR_FWFF_PKT_READ_ADDR(x) | BIT_FWFF_PKT_READ_ADDR(v)) -#define BIT_SHIFT_VIQ_HW_IDX 16 -#define BIT_MASK_VIQ_HW_IDX 0xfff -#define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX) -#define BIT_GET_VIQ_HW_IDX(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_VIQ_HOST_IDX 0 -#define BIT_MASK_VIQ_HOST_IDX 0xfff -#define BIT_VIQ_HOST_IDX(x) (((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX) -#define BIT_GET_VIQ_HOST_IDX(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX) +/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#define BIT_SHIFT_FWFF_PKT_STR_ADDR 0 +#define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff +#define BIT_FWFF_PKT_STR_ADDR(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR) +#define BITS_FWFF_PKT_STR_ADDR \ + (BIT_MASK_FWFF_PKT_STR_ADDR << BIT_SHIFT_FWFF_PKT_STR_ADDR) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR)) +#define BIT_GET_FWFF_PKT_STR_ADDR(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR) +#define BIT_SET_FWFF_PKT_STR_ADDR(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR(x) | BIT_FWFF_PKT_STR_ADDR(v)) -/* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */ +#endif +#if (HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_BEQ_HW_IDX 16 -#define BIT_MASK_BEQ_HW_IDX 0xfff -#define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX) -#define BIT_GET_BEQ_HW_IDX(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX) +/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V1 0 +#define BIT_MASK_FWFF_PKT_STR_ADDR_V1 0x7ff +#define BIT_FWFF_PKT_STR_ADDR_V1(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V1) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) +#define BITS_FWFF_PKT_STR_ADDR_V1 \ + (BIT_MASK_FWFF_PKT_STR_ADDR_V1 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V1)) +#define BIT_GET_FWFF_PKT_STR_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_V1) +#define BIT_SET_FWFF_PKT_STR_ADDR_V1(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) | BIT_FWFF_PKT_STR_ADDR_V1(v)) -#define BIT_SHIFT_BEQ_HOST_IDX 0 -#define BIT_MASK_BEQ_HOST_IDX 0xfff -#define BIT_BEQ_HOST_IDX(x) (((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX) -#define BIT_GET_BEQ_HOST_IDX(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */ +/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ +#define BIT_SHIFT_FWFF_PKT_WRITE_ADDR 0 +#define BIT_MASK_FWFF_PKT_WRITE_ADDR 0xffff +#define BIT_FWFF_PKT_WRITE_ADDR(x) \ + (((x) & BIT_MASK_FWFF_PKT_WRITE_ADDR) << BIT_SHIFT_FWFF_PKT_WRITE_ADDR) +#define BITS_FWFF_PKT_WRITE_ADDR \ + (BIT_MASK_FWFF_PKT_WRITE_ADDR << BIT_SHIFT_FWFF_PKT_WRITE_ADDR) +#define BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) ((x) & (~BITS_FWFF_PKT_WRITE_ADDR)) +#define BIT_GET_FWFF_PKT_WRITE_ADDR(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_WRITE_ADDR) & BIT_MASK_FWFF_PKT_WRITE_ADDR) +#define BIT_SET_FWFF_PKT_WRITE_ADDR(x, v) \ + (BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) | BIT_FWFF_PKT_WRITE_ADDR(v)) -#define BIT_SHIFT_BKQ_HW_IDX 16 -#define BIT_MASK_BKQ_HW_IDX 0xfff -#define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX) -#define BIT_GET_BKQ_HW_IDX(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX) +#endif +#if (HALMAC_8197F_SUPPORT) -#define BIT_SHIFT_BKQ_HOST_IDX 0 -#define BIT_MASK_BKQ_HOST_IDX 0xfff -#define BIT_BKQ_HOST_IDX(x) (((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX) -#define BIT_GET_BKQ_HOST_IDX(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX) +/* 2 REG_FC2H_INFO (Offset 0x02A4) */ +#define BIT_FC2H_PKT_REQ BIT(16) -/* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_MGQ_HW_IDX 16 -#define BIT_MASK_MGQ_HW_IDX 0xfff -#define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX) -#define BIT_GET_MGQ_HW_IDX(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX) +/* 2 REG_FC2H_INFO (Offset 0x02A4) */ +#define BIT_FC2H_DMAPKT_REQ BIT(16) -#define BIT_SHIFT_MGQ_HOST_IDX 0 -#define BIT_MASK_MGQ_HOST_IDX 0xfff -#define BIT_MGQ_HOST_IDX(x) (((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX) -#define BIT_GET_MGQ_HOST_IDX(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */ +/* 2 REG_FC2H_INFO (Offset 0x02A4) */ +#define BIT_SHIFT_FC2H_STR_ADDR 0 +#define BIT_MASK_FC2H_STR_ADDR 0xffff +#define BIT_FC2H_STR_ADDR(x) \ + (((x) & BIT_MASK_FC2H_STR_ADDR) << BIT_SHIFT_FC2H_STR_ADDR) +#define BITS_FC2H_STR_ADDR (BIT_MASK_FC2H_STR_ADDR << BIT_SHIFT_FC2H_STR_ADDR) +#define BIT_CLEAR_FC2H_STR_ADDR(x) ((x) & (~BITS_FC2H_STR_ADDR)) +#define BIT_GET_FC2H_STR_ADDR(x) \ + (((x) >> BIT_SHIFT_FC2H_STR_ADDR) & BIT_MASK_FC2H_STR_ADDR) +#define BIT_SET_FC2H_STR_ADDR(x, v) \ + (BIT_CLEAR_FC2H_STR_ADDR(x) | BIT_FC2H_STR_ADDR(v)) -#define BIT_SHIFT_RXQ_HW_IDX 16 -#define BIT_MASK_RXQ_HW_IDX 0xfff -#define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX) -#define BIT_GET_RXQ_HW_IDX(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RXQ_HOST_IDX 0 -#define BIT_MASK_RXQ_HOST_IDX 0xfff -#define BIT_RXQ_HOST_IDX(x) (((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX) -#define BIT_GET_RXQ_HOST_IDX(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX) +/* 2 REG_FWFF_PKT_INFO2 (Offset 0x02A4) */ +#define BIT_SHIFT_FWFF_PKT_QUEUED_V1 0 +#define BIT_MASK_FWFF_PKT_QUEUED_V1 0xffff +#define BIT_FWFF_PKT_QUEUED_V1(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_V1) << BIT_SHIFT_FWFF_PKT_QUEUED_V1) +#define BITS_FWFF_PKT_QUEUED_V1 \ + (BIT_MASK_FWFF_PKT_QUEUED_V1 << BIT_SHIFT_FWFF_PKT_QUEUED_V1) +#define BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) ((x) & (~BITS_FWFF_PKT_QUEUED_V1)) +#define BIT_GET_FWFF_PKT_QUEUED_V1(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_V1) & BIT_MASK_FWFF_PKT_QUEUED_V1) +#define BIT_SET_FWFF_PKT_QUEUED_V1(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) | BIT_FWFF_PKT_QUEUED_V1(v)) + +#define BIT_SHIFT_FW_UPD_RXDES_RD_PTR 0 +#define BIT_MASK_FW_UPD_RXDES_RD_PTR 0x3ffff +#define BIT_FW_UPD_RXDES_RD_PTR(x) \ + (((x) & BIT_MASK_FW_UPD_RXDES_RD_PTR) << BIT_SHIFT_FW_UPD_RXDES_RD_PTR) +#define BITS_FW_UPD_RXDES_RD_PTR \ + (BIT_MASK_FW_UPD_RXDES_RD_PTR << BIT_SHIFT_FW_UPD_RXDES_RD_PTR) +#define BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) ((x) & (~BITS_FW_UPD_RXDES_RD_PTR)) +#define BIT_GET_FW_UPD_RXDES_RD_PTR(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RXDES_RD_PTR) & BIT_MASK_FW_UPD_RXDES_RD_PTR) +#define BIT_SET_FW_UPD_RXDES_RD_PTR(x, v) \ + (BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) | BIT_FW_UPD_RXDES_RD_PTR(v)) + +#endif -/* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */ +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_RXPKTNUM (Offset 0x02B0) */ -#define BIT_SHIFT_HI0Q_HW_IDX 16 -#define BIT_MASK_HI0Q_HW_IDX 0xfff -#define BIT_HI0Q_HW_IDX(x) (((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX) -#define BIT_GET_HI0Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX) +#define BIT_SHIFT_PKT_NUM_WOL_V1 16 +#define BIT_MASK_PKT_NUM_WOL_V1 0xffff +#define BIT_PKT_NUM_WOL_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_V1) << BIT_SHIFT_PKT_NUM_WOL_V1) +#define BITS_PKT_NUM_WOL_V1 \ + (BIT_MASK_PKT_NUM_WOL_V1 << BIT_SHIFT_PKT_NUM_WOL_V1) +#define BIT_CLEAR_PKT_NUM_WOL_V1(x) ((x) & (~BITS_PKT_NUM_WOL_V1)) +#define BIT_GET_PKT_NUM_WOL_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_V1) & BIT_MASK_PKT_NUM_WOL_V1) +#define BIT_SET_PKT_NUM_WOL_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_V1(x) | BIT_PKT_NUM_WOL_V1(v)) +#define BIT_SHIFT_RXPKT_NUM_V1 0 +#define BIT_MASK_RXPKT_NUM_V1 0xffff +#define BIT_RXPKT_NUM_V1(x) \ + (((x) & BIT_MASK_RXPKT_NUM_V1) << BIT_SHIFT_RXPKT_NUM_V1) +#define BITS_RXPKT_NUM_V1 (BIT_MASK_RXPKT_NUM_V1 << BIT_SHIFT_RXPKT_NUM_V1) +#define BIT_CLEAR_RXPKT_NUM_V1(x) ((x) & (~BITS_RXPKT_NUM_V1)) +#define BIT_GET_RXPKT_NUM_V1(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_V1) & BIT_MASK_RXPKT_NUM_V1) +#define BIT_SET_RXPKT_NUM_V1(x, v) \ + (BIT_CLEAR_RXPKT_NUM_V1(x) | BIT_RXPKT_NUM_V1(v)) -#define BIT_SHIFT_HI0Q_HOST_IDX 0 -#define BIT_MASK_HI0Q_HOST_IDX 0xfff -#define BIT_HI0Q_HOST_IDX(x) (((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX) -#define BIT_GET_HI0Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX) +#define BIT_SHIFT_RXPKT_NUM_TH 0 +#define BIT_MASK_RXPKT_NUM_TH 0xff +#define BIT_RXPKT_NUM_TH(x) \ + (((x) & BIT_MASK_RXPKT_NUM_TH) << BIT_SHIFT_RXPKT_NUM_TH) +#define BITS_RXPKT_NUM_TH (BIT_MASK_RXPKT_NUM_TH << BIT_SHIFT_RXPKT_NUM_TH) +#define BIT_CLEAR_RXPKT_NUM_TH(x) ((x) & (~BITS_RXPKT_NUM_TH)) +#define BIT_GET_RXPKT_NUM_TH(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_TH) & BIT_MASK_RXPKT_NUM_TH) +#define BIT_SET_RXPKT_NUM_TH(x, v) \ + (BIT_CLEAR_RXPKT_NUM_TH(x) | BIT_RXPKT_NUM_TH(v)) +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FW_MSG1 (Offset 0x02E0) */ + +#define BIT_SHIFT_FW_MSG_REG1 0 +#define BIT_MASK_FW_MSG_REG1 0xffffffffL +#define BIT_FW_MSG_REG1(x) \ + (((x) & BIT_MASK_FW_MSG_REG1) << BIT_SHIFT_FW_MSG_REG1) +#define BITS_FW_MSG_REG1 (BIT_MASK_FW_MSG_REG1 << BIT_SHIFT_FW_MSG_REG1) +#define BIT_CLEAR_FW_MSG_REG1(x) ((x) & (~BITS_FW_MSG_REG1)) +#define BIT_GET_FW_MSG_REG1(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG1) & BIT_MASK_FW_MSG_REG1) +#define BIT_SET_FW_MSG_REG1(x, v) \ + (BIT_CLEAR_FW_MSG_REG1(x) | BIT_FW_MSG_REG1(v)) + +/* 2 REG_FW_MSG2 (Offset 0x02E4) */ + +#define BIT_SHIFT_FW_MSG_REG2 0 +#define BIT_MASK_FW_MSG_REG2 0xffffffffL +#define BIT_FW_MSG_REG2(x) \ + (((x) & BIT_MASK_FW_MSG_REG2) << BIT_SHIFT_FW_MSG_REG2) +#define BITS_FW_MSG_REG2 (BIT_MASK_FW_MSG_REG2 << BIT_SHIFT_FW_MSG_REG2) +#define BIT_CLEAR_FW_MSG_REG2(x) ((x) & (~BITS_FW_MSG_REG2)) +#define BIT_GET_FW_MSG_REG2(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG2) & BIT_MASK_FW_MSG_REG2) +#define BIT_SET_FW_MSG_REG2(x, v) \ + (BIT_CLEAR_FW_MSG_REG2(x) | BIT_FW_MSG_REG2(v)) + +/* 2 REG_FW_MSG3 (Offset 0x02E8) */ + +#define BIT_SHIFT_FW_MSG_REG3 0 +#define BIT_MASK_FW_MSG_REG3 0xffffffffL +#define BIT_FW_MSG_REG3(x) \ + (((x) & BIT_MASK_FW_MSG_REG3) << BIT_SHIFT_FW_MSG_REG3) +#define BITS_FW_MSG_REG3 (BIT_MASK_FW_MSG_REG3 << BIT_SHIFT_FW_MSG_REG3) +#define BIT_CLEAR_FW_MSG_REG3(x) ((x) & (~BITS_FW_MSG_REG3)) +#define BIT_GET_FW_MSG_REG3(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG3) & BIT_MASK_FW_MSG_REG3) +#define BIT_SET_FW_MSG_REG3(x, v) \ + (BIT_CLEAR_FW_MSG_REG3(x) | BIT_FW_MSG_REG3(v)) + +/* 2 REG_FW_MSG4 (Offset 0x02EC) */ + +#define BIT_SHIFT_FW_MSG_REG4 0 +#define BIT_MASK_FW_MSG_REG4 0xffffffffL +#define BIT_FW_MSG_REG4(x) \ + (((x) & BIT_MASK_FW_MSG_REG4) << BIT_SHIFT_FW_MSG_REG4) +#define BITS_FW_MSG_REG4 (BIT_MASK_FW_MSG_REG4 << BIT_SHIFT_FW_MSG_REG4) +#define BIT_CLEAR_FW_MSG_REG4(x) ((x) & (~BITS_FW_MSG_REG4)) +#define BIT_GET_FW_MSG_REG4(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG4) & BIT_MASK_FW_MSG_REG4) +#define BIT_SET_FW_MSG_REG4(x, v) \ + (BIT_CLEAR_FW_MSG_REG4(x) | BIT_FW_MSG_REG4(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */ +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_PCIEIO_PERSTB_SEL BIT(31) -#define BIT_SHIFT_HI1Q_HW_IDX 16 -#define BIT_MASK_HI1Q_HW_IDX 0xfff -#define BIT_HI1Q_HW_IDX(x) (((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX) -#define BIT_GET_HI1Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_HI1Q_HOST_IDX 0 -#define BIT_MASK_HI1Q_HOST_IDX 0xfff -#define BIT_HI1Q_HOST_IDX(x) (((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX) -#define BIT_GET_HI1Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX) +/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_HCIIO_PERSTB_SEL BIT(31) -/* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HI2Q_HW_IDX 16 -#define BIT_MASK_HI2Q_HW_IDX 0xfff -#define BIT_HI2Q_HW_IDX(x) (((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX) -#define BIT_GET_HI2Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_SHIFT_PCIE_MAX_RXDMA 28 +#define BIT_MASK_PCIE_MAX_RXDMA 0x7 +#define BIT_PCIE_MAX_RXDMA(x) \ + (((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA) +#define BITS_PCIE_MAX_RXDMA \ + (BIT_MASK_PCIE_MAX_RXDMA << BIT_SHIFT_PCIE_MAX_RXDMA) +#define BIT_CLEAR_PCIE_MAX_RXDMA(x) ((x) & (~BITS_PCIE_MAX_RXDMA)) +#define BIT_GET_PCIE_MAX_RXDMA(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA) +#define BIT_SET_PCIE_MAX_RXDMA(x, v) \ + (BIT_CLEAR_PCIE_MAX_RXDMA(x) | BIT_PCIE_MAX_RXDMA(v)) -#define BIT_SHIFT_HI2Q_HOST_IDX 0 -#define BIT_MASK_HI2Q_HOST_IDX 0xfff -#define BIT_HI2Q_HOST_IDX(x) (((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX) -#define BIT_GET_HI2Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */ +/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_SHIFT_HCI_MAX_RXDMA 28 +#define BIT_MASK_HCI_MAX_RXDMA 0x7 +#define BIT_HCI_MAX_RXDMA(x) \ + (((x) & BIT_MASK_HCI_MAX_RXDMA) << BIT_SHIFT_HCI_MAX_RXDMA) +#define BITS_HCI_MAX_RXDMA (BIT_MASK_HCI_MAX_RXDMA << BIT_SHIFT_HCI_MAX_RXDMA) +#define BIT_CLEAR_HCI_MAX_RXDMA(x) ((x) & (~BITS_HCI_MAX_RXDMA)) +#define BIT_GET_HCI_MAX_RXDMA(x) \ + (((x) >> BIT_SHIFT_HCI_MAX_RXDMA) & BIT_MASK_HCI_MAX_RXDMA) +#define BIT_SET_HCI_MAX_RXDMA(x, v) \ + (BIT_CLEAR_HCI_MAX_RXDMA(x) | BIT_HCI_MAX_RXDMA(v)) -#define BIT_SHIFT_HI3Q_HW_IDX 16 -#define BIT_MASK_HI3Q_HW_IDX 0xfff -#define BIT_HI3Q_HW_IDX(x) (((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX) -#define BIT_GET_HI3Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX) +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI3Q_HOST_IDX 0 -#define BIT_MASK_HI3Q_HOST_IDX 0xfff -#define BIT_HI3Q_HOST_IDX(x) (((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX) -#define BIT_GET_HI3Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX) +/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#define BIT_RX_LIT_EDN_SEL BIT(27) +#define BIT_TX_LIT_EDN_SEL BIT(26) +#define BIT_WT_LIT_EDN BIT(25) -/* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HI4Q_HW_IDX 16 -#define BIT_MASK_HI4Q_HW_IDX 0xfff -#define BIT_HI4Q_HW_IDX(x) (((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX) -#define BIT_GET_HI4Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_SHIFT_PCIE_MAX_TXDMA 24 +#define BIT_MASK_PCIE_MAX_TXDMA 0x7 +#define BIT_PCIE_MAX_TXDMA(x) \ + (((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA) +#define BITS_PCIE_MAX_TXDMA \ + (BIT_MASK_PCIE_MAX_TXDMA << BIT_SHIFT_PCIE_MAX_TXDMA) +#define BIT_CLEAR_PCIE_MAX_TXDMA(x) ((x) & (~BITS_PCIE_MAX_TXDMA)) +#define BIT_GET_PCIE_MAX_TXDMA(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA) +#define BIT_SET_PCIE_MAX_TXDMA(x, v) \ + (BIT_CLEAR_PCIE_MAX_TXDMA(x) | BIT_PCIE_MAX_TXDMA(v)) -#define BIT_SHIFT_HI4Q_HOST_IDX 0 -#define BIT_MASK_HI4Q_HOST_IDX 0xfff -#define BIT_HI4Q_HOST_IDX(x) (((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX) -#define BIT_GET_HI4Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */ +/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_SHIFT_HCI_MAX_TXDMA 24 +#define BIT_MASK_HCI_MAX_TXDMA 0x7 +#define BIT_HCI_MAX_TXDMA(x) \ + (((x) & BIT_MASK_HCI_MAX_TXDMA) << BIT_SHIFT_HCI_MAX_TXDMA) +#define BITS_HCI_MAX_TXDMA (BIT_MASK_HCI_MAX_TXDMA << BIT_SHIFT_HCI_MAX_TXDMA) +#define BIT_CLEAR_HCI_MAX_TXDMA(x) ((x) & (~BITS_HCI_MAX_TXDMA)) +#define BIT_GET_HCI_MAX_TXDMA(x) \ + (((x) >> BIT_SHIFT_HCI_MAX_TXDMA) & BIT_MASK_HCI_MAX_TXDMA) +#define BIT_SET_HCI_MAX_TXDMA(x, v) \ + (BIT_CLEAR_HCI_MAX_TXDMA(x) | BIT_HCI_MAX_TXDMA(v)) -#define BIT_SHIFT_HI5Q_HW_IDX 16 -#define BIT_MASK_HI5Q_HW_IDX 0xfff -#define BIT_HI5Q_HW_IDX(x) (((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX) -#define BIT_GET_HI5Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX) +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HI5Q_HOST_IDX 0 -#define BIT_MASK_HI5Q_HOST_IDX 0xfff -#define BIT_HI5Q_HOST_IDX(x) (((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX) -#define BIT_GET_HI5Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX) +/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#define BIT_RD_LITT_EDN BIT(24) -/* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HI6Q_HW_IDX 16 -#define BIT_MASK_HI6Q_HW_IDX 0xfff -#define BIT_HI6Q_HW_IDX(x) (((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX) -#define BIT_GET_HI6Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_PWR_SCALE_START_PS BIT(23) -#define BIT_SHIFT_HI6Q_HOST_IDX 0 -#define BIT_MASK_HI6Q_HOST_IDX 0xfff -#define BIT_HI6Q_HOST_IDX(x) (((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX) -#define BIT_GET_HI6Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */ +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_PCIE_RST_TRXDMA_INTF BIT(20) -#define BIT_SHIFT_HI7Q_HW_IDX 16 -#define BIT_MASK_HI7Q_HW_IDX 0xfff -#define BIT_HI7Q_HW_IDX(x) (((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX) -#define BIT_GET_HI7Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_HI7Q_HOST_IDX 0 -#define BIT_MASK_HI7Q_HOST_IDX 0xfff -#define BIT_HI7Q_HOST_IDX(x) (((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX) -#define BIT_GET_HI7Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX) +/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_HCI_RST_TRXDMA_INTF BIT(20) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#define BIT_SHIFT_MAX_RXDMA 20 +#define BIT_MASK_MAX_RXDMA 0x7 +#define BIT_MAX_RXDMA(x) (((x) & BIT_MASK_MAX_RXDMA) << BIT_SHIFT_MAX_RXDMA) +#define BITS_MAX_RXDMA (BIT_MASK_MAX_RXDMA << BIT_SHIFT_MAX_RXDMA) +#define BIT_CLEAR_MAX_RXDMA(x) ((x) & (~BITS_MAX_RXDMA)) +#define BIT_GET_MAX_RXDMA(x) (((x) >> BIT_SHIFT_MAX_RXDMA) & BIT_MASK_MAX_RXDMA) +#define BIT_SET_MAX_RXDMA(x, v) (BIT_CLEAR_MAX_RXDMA(x) | BIT_MAX_RXDMA(v)) -/* 2 REG_DBG_SEL_V1 (Offset 0x03D8) */ +#endif -#define BIT_DIS_TXDMA_PRE BIT(7) -#define BIT_DIS_RXDMA_PRE BIT(6) -#define BIT_TXFLAG_EXIT_L1_EN BIT(2) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DBG_SEL 0 -#define BIT_MASK_DBG_SEL 0xff -#define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL) -#define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_PCIE_EN_SWENT_L23 BIT(17) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_HCI_EN_SWENT_L23 BIT(17) -/* 2 REG_PCIE_HRPWM1_V1 (Offset 0x03D9) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PCIE_HRPWM 0 -#define BIT_MASK_PCIE_HRPWM 0xff -#define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM) -#define BIT_GET_PCIE_HRPWM(x) (((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_PCIE_EN_HWEXT_L1 BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HCI_CTRL (Offset 0x0300) */ +#define BIT_HCI_EN_HWEXT_L1 BIT(16) -/* 2 REG_HCI_HRPWM1_V1 (Offset 0x03D9) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HCI_HRPWM 0 -#define BIT_MASK_HCI_HRPWM 0xff -#define BIT_HCI_HRPWM(x) (((x) & BIT_MASK_HCI_HRPWM) << BIT_SHIFT_HCI_HRPWM) -#define BIT_GET_HCI_HRPWM(x) (((x) >> BIT_SHIFT_HCI_HRPWM) & BIT_MASK_HCI_HRPWM) +/* 2 REG_LX_CTRL1 (Offset 0x0300) */ +#define BIT_SHIFT_MAX_TXDMA 16 +#define BIT_MASK_MAX_TXDMA 0x7 +#define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA) +#define BITS_MAX_TXDMA (BIT_MASK_MAX_TXDMA << BIT_SHIFT_MAX_TXDMA) +#define BIT_CLEAR_MAX_TXDMA(x) ((x) & (~BITS_MAX_TXDMA)) +#define BIT_GET_MAX_TXDMA(x) (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA) +#define BIT_SET_MAX_TXDMA(x, v) (BIT_CLEAR_MAX_TXDMA(x) | BIT_MAX_TXDMA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PCIE_CTRL (Offset 0x0300) */ +#define BIT_STOP_P0_MPRT_BCNQ4 BIT(6) +#define BIT_STOP_P0_MPRT_BCNQ3 BIT(4) +#define BIT_STOP_P0_MPRT_BCNQ2 BIT(2) +#define BIT_STOP_P0_MPRT_BCNQ1 BIT(0) -/* 2 REG_PCIE_HCPWM1_V1 (Offset 0x03DA) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PCIE_HCPWM 0 -#define BIT_MASK_PCIE_HCPWM 0xff -#define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM) -#define BIT_GET_PCIE_HCPWM(x) (((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_TXTTIMER_MATCH_NUM 28 +#define BIT_MASK_TXTTIMER_MATCH_NUM 0xf +#define BIT_TXTTIMER_MATCH_NUM(x) \ + (((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM) +#define BITS_TXTTIMER_MATCH_NUM \ + (BIT_MASK_TXTTIMER_MATCH_NUM << BIT_SHIFT_TXTTIMER_MATCH_NUM) +#define BIT_CLEAR_TXTTIMER_MATCH_NUM(x) ((x) & (~BITS_TXTTIMER_MATCH_NUM)) +#define BIT_GET_TXTTIMER_MATCH_NUM(x) \ + (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM) +#define BIT_SET_TXTTIMER_MATCH_NUM(x, v) \ + (BIT_CLEAR_TXTTIMER_MATCH_NUM(x) | BIT_TXTTIMER_MATCH_NUM(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ACH_CTRL (Offset 0x0304) */ +#define BIT_STOP_P0HIQ19 BIT(27) +#define BIT_STOP_P0HIQ18 BIT(26) +#define BIT_STOP_P0HIQ17 BIT(25) -/* 2 REG_HCI_HCPWM1_V1 (Offset 0x03DA) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HCI_HCPWM 0 -#define BIT_MASK_HCI_HCPWM 0xff -#define BIT_HCI_HCPWM(x) (((x) & BIT_MASK_HCI_HCPWM) << BIT_SHIFT_HCI_HCPWM) -#define BIT_GET_HCI_HCPWM(x) (((x) >> BIT_SHIFT_HCI_HCPWM) & BIT_MASK_HCI_HCPWM) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_TXPKT_NUM_MATCH 24 +#define BIT_MASK_TXPKT_NUM_MATCH 0xf +#define BIT_TXPKT_NUM_MATCH(x) \ + (((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH) +#define BITS_TXPKT_NUM_MATCH \ + (BIT_MASK_TXPKT_NUM_MATCH << BIT_SHIFT_TXPKT_NUM_MATCH) +#define BIT_CLEAR_TXPKT_NUM_MATCH(x) ((x) & (~BITS_TXPKT_NUM_MATCH)) +#define BIT_GET_TXPKT_NUM_MATCH(x) \ + (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH) +#define BIT_SET_TXPKT_NUM_MATCH(x, v) \ + (BIT_CLEAR_TXPKT_NUM_MATCH(x) | BIT_TXPKT_NUM_MATCH(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_TRXCOUNTER_MATCH 24 +#define BIT_MASK_TRXCOUNTER_MATCH 0xff +#define BIT_TRXCOUNTER_MATCH(x) \ + (((x) & BIT_MASK_TRXCOUNTER_MATCH) << BIT_SHIFT_TRXCOUNTER_MATCH) +#define BITS_TRXCOUNTER_MATCH \ + (BIT_MASK_TRXCOUNTER_MATCH << BIT_SHIFT_TRXCOUNTER_MATCH) +#define BIT_CLEAR_TRXCOUNTER_MATCH(x) ((x) & (~BITS_TRXCOUNTER_MATCH)) +#define BIT_GET_TRXCOUNTER_MATCH(x) \ + (((x) >> BIT_SHIFT_TRXCOUNTER_MATCH) & BIT_MASK_TRXCOUNTER_MATCH) +#define BIT_SET_TRXCOUNTER_MATCH(x, v) \ + (BIT_CLEAR_TRXCOUNTER_MATCH(x) | BIT_TRXCOUNTER_MATCH(v)) -/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HPS_CLKR_PCIE 4 -#define BIT_MASK_HPS_CLKR_PCIE 0x3 -#define BIT_HPS_CLKR_PCIE(x) (((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE) -#define BIT_GET_HPS_CLKR_PCIE(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE) +/* 2 REG_ACH_CTRL (Offset 0x0304) */ +#define BIT_STOP_P0HIQ16 BIT(24) +#define BIT_RX_CLOSE_EN_V1 BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_RXTTIMER_MATCH_NUM 20 +#define BIT_MASK_RXTTIMER_MATCH_NUM 0xf +#define BIT_RXTTIMER_MATCH_NUM(x) \ + (((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM) +#define BITS_RXTTIMER_MATCH_NUM \ + (BIT_MASK_RXTTIMER_MATCH_NUM << BIT_SHIFT_RXTTIMER_MATCH_NUM) +#define BIT_CLEAR_RXTTIMER_MATCH_NUM(x) ((x) & (~BITS_RXTTIMER_MATCH_NUM)) +#define BIT_GET_RXTTIMER_MATCH_NUM(x) \ + (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM) +#define BIT_SET_RXTTIMER_MATCH_NUM(x, v) \ + (BIT_CLEAR_RXTTIMER_MATCH_NUM(x) | BIT_RXTTIMER_MATCH_NUM(v)) -/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HPS_CLKR_HCI 4 -#define BIT_MASK_HPS_CLKR_HCI 0x3 -#define BIT_HPS_CLKR_HCI(x) (((x) & BIT_MASK_HPS_CLKR_HCI) << BIT_SHIFT_HPS_CLKR_HCI) -#define BIT_GET_HPS_CLKR_HCI(x) (((x) >> BIT_SHIFT_HPS_CLKR_HCI) & BIT_MASK_HPS_CLKR_HCI) +/* 2 REG_ACH_CTRL (Offset 0x0304) */ +#define BIT_STOP_FWCMDQ BIT(20) +#define BIT_STOP_P0BCNQ BIT(18) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_RXPKT_NUM_MATCH 16 +#define BIT_MASK_RXPKT_NUM_MATCH 0xf +#define BIT_RXPKT_NUM_MATCH(x) \ + (((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH) +#define BITS_RXPKT_NUM_MATCH \ + (BIT_MASK_RXPKT_NUM_MATCH << BIT_SHIFT_RXPKT_NUM_MATCH) +#define BIT_CLEAR_RXPKT_NUM_MATCH(x) ((x) & (~BITS_RXPKT_NUM_MATCH)) +#define BIT_GET_RXPKT_NUM_MATCH(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH) +#define BIT_SET_RXPKT_NUM_MATCH(x, v) \ + (BIT_CLEAR_RXPKT_NUM_MATCH(x) | BIT_RXPKT_NUM_MATCH(v)) -/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ +#endif -#define BIT_PCIE_INT BIT(3) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_TRXTIMER_MATCH 16 +#define BIT_MASK_TRXTIMER_MATCH 0xff +#define BIT_TRXTIMER_MATCH(x) \ + (((x) & BIT_MASK_TRXTIMER_MATCH) << BIT_SHIFT_TRXTIMER_MATCH) +#define BITS_TRXTIMER_MATCH \ + (BIT_MASK_TRXTIMER_MATCH << BIT_SHIFT_TRXTIMER_MATCH) +#define BIT_CLEAR_TRXTIMER_MATCH(x) ((x) & (~BITS_TRXTIMER_MATCH)) +#define BIT_GET_TRXTIMER_MATCH(x) \ + (((x) >> BIT_SHIFT_TRXTIMER_MATCH) & BIT_MASK_TRXTIMER_MATCH) +#define BIT_SET_TRXTIMER_MATCH(x, v) \ + (BIT_CLEAR_TRXTIMER_MATCH(x) | BIT_TRXTIMER_MATCH(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */ +/* 2 REG_ACH_CTRL (Offset 0x0304) */ -#define BIT_HCI_INT BIT(3) +#define BIT_STOP_P0MGQ BIT(16) +#define BIT_STOP_ACH13 BIT(15) +#define BIT_STOP_ACH12 BIT(14) +#define BIT_STOP_ACH11 BIT(13) +#define BIT_STOP_ACH10 BIT(12) +#define BIT_STOP_ACH9 BIT(11) +#define BIT_STOP_ACH8 BIT(10) +#define BIT_STOP_ACH7 BIT(9) +#define BIT_STOP_ACH6 BIT(8) +#define BIT_STOP_ACH5 BIT(7) +#define BIT_STOP_ACH4 BIT(6) +#define BIT_STOP_ACH3 BIT(5) +#define BIT_STOP_ACH2 BIT(4) +#define BIT_STOP_ACH1 BIT(3) +#define BIT_STOP_ACH0 BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_MIGRATE_TIMER 0 +#define BIT_MASK_MIGRATE_TIMER 0xffff +#define BIT_MIGRATE_TIMER(x) \ + (((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER) +#define BITS_MIGRATE_TIMER (BIT_MASK_MIGRATE_TIMER << BIT_SHIFT_MIGRATE_TIMER) +#define BIT_CLEAR_MIGRATE_TIMER(x) ((x) & (~BITS_MIGRATE_TIMER)) +#define BIT_GET_MIGRATE_TIMER(x) \ + (((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER) +#define BIT_SET_MIGRATE_TIMER(x, v) \ + (BIT_CLEAR_MIGRATE_TIMER(x) | BIT_MIGRATE_TIMER(v)) -/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ +#endif -#define BIT_EN_RXDMA_ALIGN BIT(1) -#define BIT_EN_TXDMA_ALIGN BIT(0) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_INT_MIG (Offset 0x0304) */ +#define BIT_SHIFT_TRXTIMER_UNIT 0 +#define BIT_MASK_TRXTIMER_UNIT 0x3 +#define BIT_TRXTIMER_UNIT(x) \ + (((x) & BIT_MASK_TRXTIMER_UNIT) << BIT_SHIFT_TRXTIMER_UNIT) +#define BITS_TRXTIMER_UNIT (BIT_MASK_TRXTIMER_UNIT << BIT_SHIFT_TRXTIMER_UNIT) +#define BIT_CLEAR_TRXTIMER_UNIT(x) ((x) & (~BITS_TRXTIMER_UNIT)) +#define BIT_GET_TRXTIMER_UNIT(x) \ + (((x) >> BIT_SHIFT_TRXTIMER_UNIT) & BIT_MASK_TRXTIMER_UNIT) +#define BIT_SET_TRXTIMER_UNIT(x, v) \ + (BIT_CLEAR_TRXTIMER_UNIT(x) | BIT_TRXTIMER_UNIT(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_PCIE_HRPWM2_V1 (Offset 0x03DC) */ +/* 2 REG_ACH_CTRL (Offset 0x0304) */ +#define BIT_STOP_P0RX BIT(0) -#define BIT_SHIFT_PCIE_HRPWM2 0 -#define BIT_MASK_PCIE_HRPWM2 0xffff -#define BIT_PCIE_HRPWM2(x) (((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2) -#define BIT_GET_PCIE_HRPWM2(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2) +/* 2 REG_HIQ_CTRL (Offset 0x0308) */ +#define BIT_STOP_P0HIQ15 BIT(15) +#define BIT_STOP_P0HIQ14 BIT(14) +#define BIT_STOP_P0HIQ13 BIT(13) +#define BIT_STOP_P0HIQ12 BIT(12) +#define BIT_STOP_P0HIQ11 BIT(11) +#define BIT_STOP_P0HIQ10 BIT(10) +#define BIT_STOP_P0HIQ9 BIT(9) +#define BIT_STOP_P0HIQ8 BIT(8) +#define BIT_STOP_P0HIQ7 BIT(7) +#define BIT_STOP_P0HIQ6 BIT(6) +#define BIT_STOP_P0HIQ5 BIT(5) +#define BIT_STOP_P0HIQ4 BIT(4) +#define BIT_STOP_P0HIQ3 BIT(3) +#define BIT_STOP_P0HIQ2 BIT(2) +#define BIT_STOP_P0HIQ1 BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BCNQ_TXBD_DESA (Offset 0x0308) */ +#define BIT_SHIFT_BCNQ_TXBD_DESA 0 +#define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_BCNQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA) +#define BITS_BCNQ_TXBD_DESA \ + (BIT_MASK_BCNQ_TXBD_DESA << BIT_SHIFT_BCNQ_TXBD_DESA) +#define BIT_CLEAR_BCNQ_TXBD_DESA(x) ((x) & (~BITS_BCNQ_TXBD_DESA)) +#define BIT_GET_BCNQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA) +#define BIT_SET_BCNQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_BCNQ_TXBD_DESA(x) | BIT_BCNQ_TXBD_DESA(v)) -/* 2 REG_HCI_HRPWM2_V1 (Offset 0x03DC) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HCI_HRPWM2 0 -#define BIT_MASK_HCI_HRPWM2 0xffff -#define BIT_HCI_HRPWM2(x) (((x) & BIT_MASK_HCI_HRPWM2) << BIT_SHIFT_HCI_HRPWM2) -#define BIT_GET_HCI_HRPWM2(x) (((x) >> BIT_SHIFT_HCI_HRPWM2) & BIT_MASK_HCI_HRPWM2) +/* 2 REG_HIQ_CTRL (Offset 0x0308) */ +#define BIT_STOP_P0HIQ0 BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MGQ_TXBD_DESA (Offset 0x0310) */ +#define BIT_SHIFT_MGQ_TXBD_DESA 0 +#define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_MGQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA) +#define BITS_MGQ_TXBD_DESA (BIT_MASK_MGQ_TXBD_DESA << BIT_SHIFT_MGQ_TXBD_DESA) +#define BIT_CLEAR_MGQ_TXBD_DESA(x) ((x) & (~BITS_MGQ_TXBD_DESA)) +#define BIT_GET_MGQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA) +#define BIT_SET_MGQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_MGQ_TXBD_DESA(x) | BIT_MGQ_TXBD_DESA(v)) -/* 2 REG_PCIE_HCPWM2_V1 (Offset 0x03DE) */ +/* 2 REG_VOQ_TXBD_DESA (Offset 0x0318) */ +#define BIT_SHIFT_VOQ_TXBD_DESA 0 +#define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_VOQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA) +#define BITS_VOQ_TXBD_DESA (BIT_MASK_VOQ_TXBD_DESA << BIT_SHIFT_VOQ_TXBD_DESA) +#define BIT_CLEAR_VOQ_TXBD_DESA(x) ((x) & (~BITS_VOQ_TXBD_DESA)) +#define BIT_GET_VOQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA) +#define BIT_SET_VOQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_VOQ_TXBD_DESA(x) | BIT_VOQ_TXBD_DESA(v)) -#define BIT_SHIFT_PCIE_HCPWM2 0 -#define BIT_MASK_PCIE_HCPWM2 0xffff -#define BIT_PCIE_HCPWM2(x) (((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2) -#define BIT_GET_PCIE_HCPWM2(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2) +#endif +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ACH0_TXBD_DESA_L (Offset 0x0318) */ +#define BIT_SHIFT_ACH0_TXBD_DESA_L 0 +#define BIT_MASK_ACH0_TXBD_DESA_L 0xffffffffL +#define BIT_ACH0_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH0_TXBD_DESA_L) << BIT_SHIFT_ACH0_TXBD_DESA_L) +#define BITS_ACH0_TXBD_DESA_L \ + (BIT_MASK_ACH0_TXBD_DESA_L << BIT_SHIFT_ACH0_TXBD_DESA_L) +#define BIT_CLEAR_ACH0_TXBD_DESA_L(x) ((x) & (~BITS_ACH0_TXBD_DESA_L)) +#define BIT_GET_ACH0_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_L) & BIT_MASK_ACH0_TXBD_DESA_L) +#define BIT_SET_ACH0_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH0_TXBD_DESA_L(x) | BIT_ACH0_TXBD_DESA_L(v)) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ACH0_TXBD_DESA_H (Offset 0x031C) */ +#define BIT_SHIFT_ACH0_TXBD_DESA_H 0 +#define BIT_MASK_ACH0_TXBD_DESA_H 0xffffffffL +#define BIT_ACH0_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH0_TXBD_DESA_H) << BIT_SHIFT_ACH0_TXBD_DESA_H) +#define BITS_ACH0_TXBD_DESA_H \ + (BIT_MASK_ACH0_TXBD_DESA_H << BIT_SHIFT_ACH0_TXBD_DESA_H) +#define BIT_CLEAR_ACH0_TXBD_DESA_H(x) ((x) & (~BITS_ACH0_TXBD_DESA_H)) +#define BIT_GET_ACH0_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_H) & BIT_MASK_ACH0_TXBD_DESA_H) +#define BIT_SET_ACH0_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH0_TXBD_DESA_H(x) | BIT_ACH0_TXBD_DESA_H(v)) -/* 2 REG_HCI_HCPWM2_V1 (Offset 0x03DE) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HCI_HCPWM2 0 -#define BIT_MASK_HCI_HCPWM2 0xffff -#define BIT_HCI_HCPWM2(x) (((x) & BIT_MASK_HCI_HCPWM2) << BIT_SHIFT_HCI_HCPWM2) -#define BIT_GET_HCI_HCPWM2(x) (((x) >> BIT_SHIFT_HCI_HCPWM2) & BIT_MASK_HCI_HCPWM2) +/* 2 REG_VIQ_TXBD_DESA (Offset 0x0320) */ +#define BIT_SHIFT_VIQ_TXBD_DESA 0 +#define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_VIQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA) +#define BITS_VIQ_TXBD_DESA (BIT_MASK_VIQ_TXBD_DESA << BIT_SHIFT_VIQ_TXBD_DESA) +#define BIT_CLEAR_VIQ_TXBD_DESA(x) ((x) & (~BITS_VIQ_TXBD_DESA)) +#define BIT_GET_VIQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA) +#define BIT_SET_VIQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_VIQ_TXBD_DESA(x) | BIT_VIQ_TXBD_DESA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH1_TXBD_DESA_L (Offset 0x0320) */ +#define BIT_SHIFT_ACH1_TXBD_DESA_L 0 +#define BIT_MASK_ACH1_TXBD_DESA_L 0xffffffffL +#define BIT_ACH1_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH1_TXBD_DESA_L) << BIT_SHIFT_ACH1_TXBD_DESA_L) +#define BITS_ACH1_TXBD_DESA_L \ + (BIT_MASK_ACH1_TXBD_DESA_L << BIT_SHIFT_ACH1_TXBD_DESA_L) +#define BIT_CLEAR_ACH1_TXBD_DESA_L(x) ((x) & (~BITS_ACH1_TXBD_DESA_L)) +#define BIT_GET_ACH1_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_L) & BIT_MASK_ACH1_TXBD_DESA_L) +#define BIT_SET_ACH1_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH1_TXBD_DESA_L(x) | BIT_ACH1_TXBD_DESA_L(v)) -/* 2 REG_PCIE_H2C_MSG_V1 (Offset 0x03E0) */ +/* 2 REG_ACH1_TXBD_DESA_H (Offset 0x0324) */ +#define BIT_SHIFT_ACH1_TXBD_DESA_H 0 +#define BIT_MASK_ACH1_TXBD_DESA_H 0xffffffffL +#define BIT_ACH1_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH1_TXBD_DESA_H) << BIT_SHIFT_ACH1_TXBD_DESA_H) +#define BITS_ACH1_TXBD_DESA_H \ + (BIT_MASK_ACH1_TXBD_DESA_H << BIT_SHIFT_ACH1_TXBD_DESA_H) +#define BIT_CLEAR_ACH1_TXBD_DESA_H(x) ((x) & (~BITS_ACH1_TXBD_DESA_H)) +#define BIT_GET_ACH1_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_H) & BIT_MASK_ACH1_TXBD_DESA_H) +#define BIT_SET_ACH1_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH1_TXBD_DESA_H(x) | BIT_ACH1_TXBD_DESA_H(v)) -#define BIT_SHIFT_DRV2FW_INFO 0 -#define BIT_MASK_DRV2FW_INFO 0xffffffffL -#define BIT_DRV2FW_INFO(x) (((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO) -#define BIT_GET_DRV2FW_INFO(x) (((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_BEQ_TXBD_DESA (Offset 0x0328) */ +#define BIT_SHIFT_BEQ_TXBD_DESA 0 +#define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_BEQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA) +#define BITS_BEQ_TXBD_DESA (BIT_MASK_BEQ_TXBD_DESA << BIT_SHIFT_BEQ_TXBD_DESA) +#define BIT_CLEAR_BEQ_TXBD_DESA(x) ((x) & (~BITS_BEQ_TXBD_DESA)) +#define BIT_GET_BEQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA) +#define BIT_SET_BEQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_BEQ_TXBD_DESA(x) | BIT_BEQ_TXBD_DESA(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_PCIE_C2H_MSG_V1 (Offset 0x03E4) */ +/* 2 REG_ACH2_TXBD_DESA_L (Offset 0x0328) */ +#define BIT_SHIFT_ACH2_TXBD_DESA_L 0 +#define BIT_MASK_ACH2_TXBD_DESA_L 0xffffffffL +#define BIT_ACH2_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH2_TXBD_DESA_L) << BIT_SHIFT_ACH2_TXBD_DESA_L) +#define BITS_ACH2_TXBD_DESA_L \ + (BIT_MASK_ACH2_TXBD_DESA_L << BIT_SHIFT_ACH2_TXBD_DESA_L) +#define BIT_CLEAR_ACH2_TXBD_DESA_L(x) ((x) & (~BITS_ACH2_TXBD_DESA_L)) +#define BIT_GET_ACH2_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_L) & BIT_MASK_ACH2_TXBD_DESA_L) +#define BIT_SET_ACH2_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH2_TXBD_DESA_L(x) | BIT_ACH2_TXBD_DESA_L(v)) -#define BIT_SHIFT_HCI_PCIE_C2H_MSG 0 -#define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL -#define BIT_HCI_PCIE_C2H_MSG(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG) -#define BIT_GET_HCI_PCIE_C2H_MSG(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG) +/* 2 REG_ACH2_TXBD_DESA_H (Offset 0x032C) */ +#define BIT_SHIFT_ACH2_TXBD_DESA_H 0 +#define BIT_MASK_ACH2_TXBD_DESA_H 0xffffffffL +#define BIT_ACH2_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH2_TXBD_DESA_H) << BIT_SHIFT_ACH2_TXBD_DESA_H) +#define BITS_ACH2_TXBD_DESA_H \ + (BIT_MASK_ACH2_TXBD_DESA_H << BIT_SHIFT_ACH2_TXBD_DESA_H) +#define BIT_CLEAR_ACH2_TXBD_DESA_H(x) ((x) & (~BITS_ACH2_TXBD_DESA_H)) +#define BIT_GET_ACH2_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_H) & BIT_MASK_ACH2_TXBD_DESA_H) +#define BIT_SET_ACH2_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH2_TXBD_DESA_H(x) | BIT_ACH2_TXBD_DESA_H(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BKQ_TXBD_DESA (Offset 0x0330) */ +#define BIT_SHIFT_BKQ_TXBD_DESA 0 +#define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_BKQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA) +#define BITS_BKQ_TXBD_DESA (BIT_MASK_BKQ_TXBD_DESA << BIT_SHIFT_BKQ_TXBD_DESA) +#define BIT_CLEAR_BKQ_TXBD_DESA(x) ((x) & (~BITS_BKQ_TXBD_DESA)) +#define BIT_GET_BKQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA) +#define BIT_SET_BKQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_BKQ_TXBD_DESA(x) | BIT_BKQ_TXBD_DESA(v)) -/* 2 REG_HCI_C2H_MSG_V1 (Offset 0x03E4) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HCI_C2H_MSG 0 -#define BIT_MASK_HCI_C2H_MSG 0xffffffffL -#define BIT_HCI_C2H_MSG(x) (((x) & BIT_MASK_HCI_C2H_MSG) << BIT_SHIFT_HCI_C2H_MSG) -#define BIT_GET_HCI_C2H_MSG(x) (((x) >> BIT_SHIFT_HCI_C2H_MSG) & BIT_MASK_HCI_C2H_MSG) +/* 2 REG_ACH3_TXBD_DESA_L (Offset 0x0330) */ +#define BIT_SHIFT_ACH3_TXBD_DESA_L 0 +#define BIT_MASK_ACH3_TXBD_DESA_L 0xffffffffL +#define BIT_ACH3_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH3_TXBD_DESA_L) << BIT_SHIFT_ACH3_TXBD_DESA_L) +#define BITS_ACH3_TXBD_DESA_L \ + (BIT_MASK_ACH3_TXBD_DESA_L << BIT_SHIFT_ACH3_TXBD_DESA_L) +#define BIT_CLEAR_ACH3_TXBD_DESA_L(x) ((x) & (~BITS_ACH3_TXBD_DESA_L)) +#define BIT_GET_ACH3_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_L) & BIT_MASK_ACH3_TXBD_DESA_L) +#define BIT_SET_ACH3_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH3_TXBD_DESA_L(x) | BIT_ACH3_TXBD_DESA_L(v)) -#endif +/* 2 REG_ACH3_TXBD_DESA_H (Offset 0x0334) */ +#define BIT_SHIFT_ACH3_TXBD_DESA_H 0 +#define BIT_MASK_ACH3_TXBD_DESA_H 0xffffffffL +#define BIT_ACH3_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH3_TXBD_DESA_H) << BIT_SHIFT_ACH3_TXBD_DESA_H) +#define BITS_ACH3_TXBD_DESA_H \ + (BIT_MASK_ACH3_TXBD_DESA_H << BIT_SHIFT_ACH3_TXBD_DESA_H) +#define BIT_CLEAR_ACH3_TXBD_DESA_H(x) ((x) & (~BITS_ACH3_TXBD_DESA_H)) +#define BIT_GET_ACH3_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_H) & BIT_MASK_ACH3_TXBD_DESA_H) +#define BIT_SET_ACH3_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH3_TXBD_DESA_H(x) | BIT_ACH3_TXBD_DESA_H(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DBI_WDATA_V1 (Offset 0x03E8) */ +/* 2 REG_RXQ_RXBD_DESA (Offset 0x0338) */ +#define BIT_SHIFT_RXQ_RXBD_DESA 0 +#define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL +#define BIT_RXQ_RXBD_DESA(x) \ + (((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA) +#define BITS_RXQ_RXBD_DESA (BIT_MASK_RXQ_RXBD_DESA << BIT_SHIFT_RXQ_RXBD_DESA) +#define BIT_CLEAR_RXQ_RXBD_DESA(x) ((x) & (~BITS_RXQ_RXBD_DESA)) +#define BIT_GET_RXQ_RXBD_DESA(x) \ + (((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA) +#define BIT_SET_RXQ_RXBD_DESA(x, v) \ + (BIT_CLEAR_RXQ_RXBD_DESA(x) | BIT_RXQ_RXBD_DESA(v)) -#define BIT_SHIFT_DBI_WDATA 0 -#define BIT_MASK_DBI_WDATA 0xffffffffL -#define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA) -#define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_DBI_RDATA_V1 (Offset 0x03EC) */ +/* 2 REG_P0RXQ_RXBD_DESA_L (Offset 0x0338) */ +#define BIT_SHIFT_P0RXQ_RXBD_DESA_L 0 +#define BIT_MASK_P0RXQ_RXBD_DESA_L 0xffffffffL +#define BIT_P0RXQ_RXBD_DESA_L(x) \ + (((x) & BIT_MASK_P0RXQ_RXBD_DESA_L) << BIT_SHIFT_P0RXQ_RXBD_DESA_L) +#define BITS_P0RXQ_RXBD_DESA_L \ + (BIT_MASK_P0RXQ_RXBD_DESA_L << BIT_SHIFT_P0RXQ_RXBD_DESA_L) +#define BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_L)) +#define BIT_GET_P0RXQ_RXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_L) & BIT_MASK_P0RXQ_RXBD_DESA_L) +#define BIT_SET_P0RXQ_RXBD_DESA_L(x, v) \ + (BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) | BIT_P0RXQ_RXBD_DESA_L(v)) -#define BIT_SHIFT_DBI_RDATA 0 -#define BIT_MASK_DBI_RDATA 0xffffffffL -#define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA) -#define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA) +/* 2 REG_P0RXQ_RXBD_DESA_H (Offset 0x033C) */ +#define BIT_SHIFT_P0RXQ_RXBD_DESA_H 0 +#define BIT_MASK_P0RXQ_RXBD_DESA_H 0xffffffffL +#define BIT_P0RXQ_RXBD_DESA_H(x) \ + (((x) & BIT_MASK_P0RXQ_RXBD_DESA_H) << BIT_SHIFT_P0RXQ_RXBD_DESA_H) +#define BITS_P0RXQ_RXBD_DESA_H \ + (BIT_MASK_P0RXQ_RXBD_DESA_H << BIT_SHIFT_P0RXQ_RXBD_DESA_H) +#define BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_H)) +#define BIT_GET_P0RXQ_RXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_H) & BIT_MASK_P0RXQ_RXBD_DESA_H) +#define BIT_SET_P0RXQ_RXBD_DESA_H(x, v) \ + (BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) | BIT_P0RXQ_RXBD_DESA_H(v)) -/* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */ +#endif -#define BIT_EN_STUCK_DBG BIT(26) -#define BIT_RX_STUCK BIT(25) -#define BIT_TX_STUCK BIT(24) -#define BIT_DBI_RFLAG BIT(17) -#define BIT_DBI_WFLAG BIT(16) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DBI_WREN 12 -#define BIT_MASK_DBI_WREN 0xf -#define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN) -#define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN) +/* 2 REG_HI0Q_TXBD_DESA (Offset 0x0340) */ +#define BIT_SHIFT_HI0Q_TXBD_DESA 0 +#define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI0Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA) +#define BITS_HI0Q_TXBD_DESA \ + (BIT_MASK_HI0Q_TXBD_DESA << BIT_SHIFT_HI0Q_TXBD_DESA) +#define BIT_CLEAR_HI0Q_TXBD_DESA(x) ((x) & (~BITS_HI0Q_TXBD_DESA)) +#define BIT_GET_HI0Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA) +#define BIT_SET_HI0Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA(x) | BIT_HI0Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0BCNQ_TXBD_DESA_L (Offset 0x0340) */ + +#define BIT_SHIFT_P0BCNQ_TXBD_DESA_L 0 +#define BIT_MASK_P0BCNQ_TXBD_DESA_L 0xffffffffL +#define BIT_P0BCNQ_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_L) << BIT_SHIFT_P0BCNQ_TXBD_DESA_L) +#define BITS_P0BCNQ_TXBD_DESA_L \ + (BIT_MASK_P0BCNQ_TXBD_DESA_L << BIT_SHIFT_P0BCNQ_TXBD_DESA_L) +#define BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_L)) +#define BIT_GET_P0BCNQ_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_L) & BIT_MASK_P0BCNQ_TXBD_DESA_L) +#define BIT_SET_P0BCNQ_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) | BIT_P0BCNQ_TXBD_DESA_L(v)) + +/* 2 REG_P0BCNQ_TXBD_DESA_H (Offset 0x0344) */ + +#define BIT_SHIFT_P0BCNQ_TXBD_DESA_H 0 +#define BIT_MASK_P0BCNQ_TXBD_DESA_H 0xffffffffL +#define BIT_P0BCNQ_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_H) << BIT_SHIFT_P0BCNQ_TXBD_DESA_H) +#define BITS_P0BCNQ_TXBD_DESA_H \ + (BIT_MASK_P0BCNQ_TXBD_DESA_H << BIT_SHIFT_P0BCNQ_TXBD_DESA_H) +#define BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_H)) +#define BIT_GET_P0BCNQ_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_H) & BIT_MASK_P0BCNQ_TXBD_DESA_H) +#define BIT_SET_P0BCNQ_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) | BIT_P0BCNQ_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DBI_ADDR 0 -#define BIT_MASK_DBI_ADDR 0xfff -#define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR) -#define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR) +/* 2 REG_HI1Q_TXBD_DESA (Offset 0x0348) */ +#define BIT_SHIFT_HI1Q_TXBD_DESA 0 +#define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI1Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA) +#define BITS_HI1Q_TXBD_DESA \ + (BIT_MASK_HI1Q_TXBD_DESA << BIT_SHIFT_HI1Q_TXBD_DESA) +#define BIT_CLEAR_HI1Q_TXBD_DESA(x) ((x) & (~BITS_HI1Q_TXBD_DESA)) +#define BIT_GET_HI1Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA) +#define BIT_SET_HI1Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA(x) | BIT_HI1Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FWCMDQ_TXBD_DESA_L (Offset 0x0348) */ + +#define BIT_SHIFT_FWCMDQ_TXBD_DESA_L 0 +#define BIT_MASK_FWCMDQ_TXBD_DESA_L 0xffffffffL +#define BIT_FWCMDQ_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_L) << BIT_SHIFT_FWCMDQ_TXBD_DESA_L) +#define BITS_FWCMDQ_TXBD_DESA_L \ + (BIT_MASK_FWCMDQ_TXBD_DESA_L << BIT_SHIFT_FWCMDQ_TXBD_DESA_L) +#define BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_L)) +#define BIT_GET_FWCMDQ_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_L) & BIT_MASK_FWCMDQ_TXBD_DESA_L) +#define BIT_SET_FWCMDQ_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) | BIT_FWCMDQ_TXBD_DESA_L(v)) + +/* 2 REG_FWCMDQ_TXBD_DESA_H (Offset 0x034C) */ + +#define BIT_SHIFT_FWCMDQ_TXBD_DESA_H 0 +#define BIT_MASK_FWCMDQ_TXBD_DESA_H 0xffffffffL +#define BIT_FWCMDQ_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_H) << BIT_SHIFT_FWCMDQ_TXBD_DESA_H) +#define BITS_FWCMDQ_TXBD_DESA_H \ + (BIT_MASK_FWCMDQ_TXBD_DESA_H << BIT_SHIFT_FWCMDQ_TXBD_DESA_H) +#define BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_H)) +#define BIT_GET_FWCMDQ_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_H) & BIT_MASK_FWCMDQ_TXBD_DESA_H) +#define BIT_SET_FWCMDQ_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) | BIT_FWCMDQ_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_MDIO_V1 (Offset 0x03F4) */ +/* 2 REG_HI2Q_TXBD_DESA (Offset 0x0350) */ +#define BIT_SHIFT_HI2Q_TXBD_DESA 0 +#define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI2Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA) +#define BITS_HI2Q_TXBD_DESA \ + (BIT_MASK_HI2Q_TXBD_DESA << BIT_SHIFT_HI2Q_TXBD_DESA) +#define BIT_CLEAR_HI2Q_TXBD_DESA(x) ((x) & (~BITS_HI2Q_TXBD_DESA)) +#define BIT_GET_HI2Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA) +#define BIT_SET_HI2Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA(x) | BIT_HI2Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_PCIE_HRPWM1_HCPWM1_DCPU (Offset 0x0354) */ + +#define BIT_SHIFT_PCIE_HCPWM1_DCPU 16 +#define BIT_MASK_PCIE_HCPWM1_DCPU 0xff +#define BIT_PCIE_HCPWM1_DCPU(x) \ + (((x) & BIT_MASK_PCIE_HCPWM1_DCPU) << BIT_SHIFT_PCIE_HCPWM1_DCPU) +#define BITS_PCIE_HCPWM1_DCPU \ + (BIT_MASK_PCIE_HCPWM1_DCPU << BIT_SHIFT_PCIE_HCPWM1_DCPU) +#define BIT_CLEAR_PCIE_HCPWM1_DCPU(x) ((x) & (~BITS_PCIE_HCPWM1_DCPU)) +#define BIT_GET_PCIE_HCPWM1_DCPU(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM1_DCPU) & BIT_MASK_PCIE_HCPWM1_DCPU) +#define BIT_SET_PCIE_HCPWM1_DCPU(x, v) \ + (BIT_CLEAR_PCIE_HCPWM1_DCPU(x) | BIT_PCIE_HCPWM1_DCPU(v)) + +#define BIT_SHIFT_PCIE_HRPWM1_DCPU 8 +#define BIT_MASK_PCIE_HRPWM1_DCPU 0xff +#define BIT_PCIE_HRPWM1_DCPU(x) \ + (((x) & BIT_MASK_PCIE_HRPWM1_DCPU) << BIT_SHIFT_PCIE_HRPWM1_DCPU) +#define BITS_PCIE_HRPWM1_DCPU \ + (BIT_MASK_PCIE_HRPWM1_DCPU << BIT_SHIFT_PCIE_HRPWM1_DCPU) +#define BIT_CLEAR_PCIE_HRPWM1_DCPU(x) ((x) & (~BITS_PCIE_HRPWM1_DCPU)) +#define BIT_GET_PCIE_HRPWM1_DCPU(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM1_DCPU) & BIT_MASK_PCIE_HRPWM1_DCPU) +#define BIT_SET_PCIE_HRPWM1_DCPU(x, v) \ + (BIT_CLEAR_PCIE_HRPWM1_DCPU(x) | BIT_PCIE_HRPWM1_DCPU(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MDIO_RDATA 16 -#define BIT_MASK_MDIO_RDATA 0xffff -#define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA) -#define BIT_GET_MDIO_RDATA(x) (((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA) +/* 2 REG_HI3Q_TXBD_DESA (Offset 0x0358) */ +#define BIT_SHIFT_HI3Q_TXBD_DESA 0 +#define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI3Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA) +#define BITS_HI3Q_TXBD_DESA \ + (BIT_MASK_HI3Q_TXBD_DESA << BIT_SHIFT_HI3Q_TXBD_DESA) +#define BIT_CLEAR_HI3Q_TXBD_DESA(x) ((x) & (~BITS_HI3Q_TXBD_DESA)) +#define BIT_GET_HI3Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA) +#define BIT_SET_HI3Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA(x) | BIT_HI3Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_L (Offset 0x0358) */ + +#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L 0 +#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L 0xffffffffL +#define BIT_P0_MPRT_BCNQ_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L) \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) +#define BITS_P0_MPRT_BCNQ_TXBD_DESA_L \ + (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) +#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_L)) +#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) & \ + BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L) +#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x) | \ + BIT_P0_MPRT_BCNQ_TXBD_DESA_L(v)) + +/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_H (Offset 0x035C) */ + +#define BIT_CLR_P0HI15Q_HW_IDX BIT(29) +#define BIT_CLR_P0HI14Q_HW_IDX BIT(28) +#define BIT_CLR_P0HI13Q_HW_IDX BIT(27) +#define BIT_CLR_P0HI12Q_HW_IDX BIT(26) +#define BIT_CLR_P0HI11Q_HW_IDX BIT(25) +#define BIT_CLR_P0HI10Q_HW_IDX BIT(24) +#define BIT_CLR_P0HI9Q_HW_IDX BIT(23) +#define BIT_CLR_P0HI8Q_HW_IDX BIT(22) +#define BIT_CLR_ACH7_HW_IDX BIT(21) +#define BIT_CLR_ACH13_HW_IDX BIT(21) +#define BIT_CLR_ACH6_HW_IDX BIT(20) +#define BIT_CLR_ACH12_HW_IDX BIT(20) +#define BIT_CLR_ACH5_HW_IDX BIT(19) +#define BIT_CLR_ACH11_HW_IDX BIT(19) +#define BIT_CLR_ACH4_HW_IDX BIT(18) +#define BIT_CLR_ACH10_HW_IDX BIT(18) +#define BIT_CLR_ACH9_HW_IDX BIT(17) +#define BIT_CLR_ACH8_HW_IDX BIT(16) + +#define BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE 13 +#define BIT_MASK_P0_MPRT_BCNQ_DESC_MODE 0x3 +#define BIT_P0_MPRT_BCNQ_DESC_MODE(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_DESC_MODE) \ + << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) +#define BITS_P0_MPRT_BCNQ_DESC_MODE \ + (BIT_MASK_P0_MPRT_BCNQ_DESC_MODE << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) +#define BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_DESC_MODE)) +#define BIT_GET_P0_MPRT_BCNQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) & \ + BIT_MASK_P0_MPRT_BCNQ_DESC_MODE) +#define BIT_SET_P0_MPRT_BCNQ_DESC_MODE(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x) | BIT_P0_MPRT_BCNQ_DESC_MODE(v)) + +#define BIT_CLR_P0HI15Q_HOST_IDX BIT(13) +#define BIT_CLR_P0HI14Q_HOST_IDX BIT(12) +#define BIT_PCIE_P0MPRT_BCNQ4_FLAG BIT(11) +#define BIT_CLR_P0HI13Q_HOST_IDX BIT(11) +#define BIT_PCIE_P0MPRT_BCNQ3_FLAG BIT(10) +#define BIT_CLR_P0HI12Q_HOST_IDX BIT(10) +#define BIT_PCIE_P0MPRT_BCNQ2_FLAG BIT(9) +#define BIT_CLR_P0HI11Q_HOST_IDX BIT(9) +#define BIT_PCIE_P0MPRT_BCNQ1_FLAG BIT(8) +#define BIT_CLR_P0HI10Q_HOST_IDX BIT(8) +#define BIT_CLR_P0HI9Q_HOST_IDX BIT(7) +#define BIT_CLR_P0HI8Q_HOST_IDX BIT(6) +#define BIT_CLR_ACH7_HOST_IDX BIT(5) +#define BIT_CLR_ACH13_HOST_IDX BIT(5) +#define BIT_CLR_ACH6_HOST_IDX BIT(4) +#define BIT_CLR_ACH12_HOST_IDX BIT(4) +#define BIT_CLR_ACH5_HOST_IDX BIT(3) +#define BIT_CLR_ACH11_HOST_IDX BIT(3) +#define BIT_CLR_ACH4_HOST_IDX BIT(2) +#define BIT_CLR_ACH10_HOST_IDX BIT(2) +#define BIT_EPHY_CAL_DONE BIT(1) +#define BIT_CLR_ACH9_HOST_IDX BIT(1) + +#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H 0 +#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H 0xffffffffL +#define BIT_P0_MPRT_BCNQ_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H) \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) +#define BITS_P0_MPRT_BCNQ_TXBD_DESA_H \ + (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) +#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_H)) +#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) & \ + BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H) +#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x) | \ + BIT_P0_MPRT_BCNQ_TXBD_DESA_H(v)) + +#define BIT_RESET_APHY BIT(0) +#define BIT_CLR_ACH8_HOST_IDX BIT(0) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MDIO_WDATA 0 -#define BIT_MASK_MDIO_WDATA 0xffff -#define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA) -#define BIT_GET_MDIO_WDATA(x) (((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA) +/* 2 REG_HI4Q_TXBD_DESA (Offset 0x0360) */ +#define BIT_SHIFT_HI4Q_TXBD_DESA 0 +#define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI4Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA) +#define BITS_HI4Q_TXBD_DESA \ + (BIT_MASK_HI4Q_TXBD_DESA << BIT_SHIFT_HI4Q_TXBD_DESA) +#define BIT_CLEAR_HI4Q_TXBD_DESA(x) ((x) & (~BITS_HI4Q_TXBD_DESA)) +#define BIT_GET_HI4Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA) +#define BIT_SET_HI4Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA(x) | BIT_HI4Q_TXBD_DESA(v)) -#endif +/* 2 REG_HI5Q_TXBD_DESA (Offset 0x0368) */ +#define BIT_SHIFT_HI5Q_TXBD_DESA 0 +#define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI5Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA) +#define BITS_HI5Q_TXBD_DESA \ + (BIT_MASK_HI5Q_TXBD_DESA << BIT_SHIFT_HI5Q_TXBD_DESA) +#define BIT_CLEAR_HI5Q_TXBD_DESA(x) ((x) & (~BITS_HI5Q_TXBD_DESA)) +#define BIT_GET_HI5Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA) +#define BIT_SET_HI5Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA(x) | BIT_HI5Q_TXBD_DESA(v)) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_HI6Q_TXBD_DESA (Offset 0x0370) */ +#define BIT_SHIFT_HI6Q_TXBD_DESA 0 +#define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI6Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA) +#define BITS_HI6Q_TXBD_DESA \ + (BIT_MASK_HI6Q_TXBD_DESA << BIT_SHIFT_HI6Q_TXBD_DESA) +#define BIT_CLEAR_HI6Q_TXBD_DESA(x) ((x) & (~BITS_HI6Q_TXBD_DESA)) +#define BIT_GET_HI6Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA) +#define BIT_SET_HI6Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA(x) | BIT_HI6Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM (Offset 0x0378) */ + +#define BIT_SYS_32_64_V1 BIT(31) + +#define BIT_SHIFT_P0BCNQ_DESC_MODE 29 +#define BIT_MASK_P0BCNQ_DESC_MODE 0x3 +#define BIT_P0BCNQ_DESC_MODE(x) \ + (((x) & BIT_MASK_P0BCNQ_DESC_MODE) << BIT_SHIFT_P0BCNQ_DESC_MODE) +#define BITS_P0BCNQ_DESC_MODE \ + (BIT_MASK_P0BCNQ_DESC_MODE << BIT_SHIFT_P0BCNQ_DESC_MODE) +#define BIT_CLEAR_P0BCNQ_DESC_MODE(x) ((x) & (~BITS_P0BCNQ_DESC_MODE)) +#define BIT_GET_P0BCNQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_DESC_MODE) & BIT_MASK_P0BCNQ_DESC_MODE) +#define BIT_SET_P0BCNQ_DESC_MODE(x, v) \ + (BIT_CLEAR_P0BCNQ_DESC_MODE(x) | BIT_P0BCNQ_DESC_MODE(v)) + +#define BIT_PCIE_P0BCNQ_FLAG BIT(28) + +#define BIT_SHIFT_P0RXQ_DESC_NUM 16 +#define BIT_MASK_P0RXQ_DESC_NUM 0xfff +#define BIT_P0RXQ_DESC_NUM(x) \ + (((x) & BIT_MASK_P0RXQ_DESC_NUM) << BIT_SHIFT_P0RXQ_DESC_NUM) +#define BITS_P0RXQ_DESC_NUM \ + (BIT_MASK_P0RXQ_DESC_NUM << BIT_SHIFT_P0RXQ_DESC_NUM) +#define BIT_CLEAR_P0RXQ_DESC_NUM(x) ((x) & (~BITS_P0RXQ_DESC_NUM)) +#define BIT_GET_P0RXQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0RXQ_DESC_NUM) & BIT_MASK_P0RXQ_DESC_NUM) +#define BIT_SET_P0RXQ_DESC_NUM(x, v) \ + (BIT_CLEAR_P0RXQ_DESC_NUM(x) | BIT_P0RXQ_DESC_NUM(v)) + +#define BIT_PCIE_P0MGQ_FLAG BIT(14) + +#define BIT_SHIFT_P0MGQ_DESC_MODE 12 +#define BIT_MASK_P0MGQ_DESC_MODE 0x3 +#define BIT_P0MGQ_DESC_MODE(x) \ + (((x) & BIT_MASK_P0MGQ_DESC_MODE) << BIT_SHIFT_P0MGQ_DESC_MODE) +#define BITS_P0MGQ_DESC_MODE \ + (BIT_MASK_P0MGQ_DESC_MODE << BIT_SHIFT_P0MGQ_DESC_MODE) +#define BIT_CLEAR_P0MGQ_DESC_MODE(x) ((x) & (~BITS_P0MGQ_DESC_MODE)) +#define BIT_GET_P0MGQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0MGQ_DESC_MODE) & BIT_MASK_P0MGQ_DESC_MODE) +#define BIT_SET_P0MGQ_DESC_MODE(x, v) \ + (BIT_CLEAR_P0MGQ_DESC_MODE(x) | BIT_P0MGQ_DESC_MODE(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BUS_MIX_CFG (Offset 0x03F8) */ +/* 2 REG_HI7Q_TXBD_DESA (Offset 0x0378) */ +#define BIT_SHIFT_HI7Q_TXBD_DESA 0 +#define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI7Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA) +#define BITS_HI7Q_TXBD_DESA \ + (BIT_MASK_HI7Q_TXBD_DESA << BIT_SHIFT_HI7Q_TXBD_DESA) +#define BIT_CLEAR_HI7Q_TXBD_DESA(x) ((x) & (~BITS_HI7Q_TXBD_DESA)) +#define BIT_GET_HI7Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA) +#define BIT_SET_HI7Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA(x) | BIT_HI7Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM (Offset 0x0378) */ + +#define BIT_SHIFT_P0MGQ_DESC_NUM 0 +#define BIT_MASK_P0MGQ_DESC_NUM 0xfff +#define BIT_P0MGQ_DESC_NUM(x) \ + (((x) & BIT_MASK_P0MGQ_DESC_NUM) << BIT_SHIFT_P0MGQ_DESC_NUM) +#define BITS_P0MGQ_DESC_NUM \ + (BIT_MASK_P0MGQ_DESC_NUM << BIT_SHIFT_P0MGQ_DESC_NUM) +#define BIT_CLEAR_P0MGQ_DESC_NUM(x) ((x) & (~BITS_P0MGQ_DESC_NUM)) +#define BIT_GET_P0MGQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0MGQ_DESC_NUM) & BIT_MASK_P0MGQ_DESC_NUM) +#define BIT_SET_P0MGQ_DESC_NUM(x, v) \ + (BIT_CLEAR_P0MGQ_DESC_NUM(x) | BIT_P0MGQ_DESC_NUM(v)) + +/* 2 REG_CHNL_DMA_CFG (Offset 0x037C) */ + +#define BIT_TXHCI_EN BIT(26) +#define BIT_TXHCI_IDLE BIT(25) +#define BIT_DMA_PRI_EN BIT(24) +#define BIT_PCIE_FWCMDQ_FLAG BIT(14) + +#define BIT_SHIFT_FWCMDQ_DESC_MODE 12 +#define BIT_MASK_FWCMDQ_DESC_MODE 0x3 +#define BIT_FWCMDQ_DESC_MODE(x) \ + (((x) & BIT_MASK_FWCMDQ_DESC_MODE) << BIT_SHIFT_FWCMDQ_DESC_MODE) +#define BITS_FWCMDQ_DESC_MODE \ + (BIT_MASK_FWCMDQ_DESC_MODE << BIT_SHIFT_FWCMDQ_DESC_MODE) +#define BIT_CLEAR_FWCMDQ_DESC_MODE(x) ((x) & (~BITS_FWCMDQ_DESC_MODE)) +#define BIT_GET_FWCMDQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_DESC_MODE) & BIT_MASK_FWCMDQ_DESC_MODE) +#define BIT_SET_FWCMDQ_DESC_MODE(x, v) \ + (BIT_CLEAR_FWCMDQ_DESC_MODE(x) | BIT_FWCMDQ_DESC_MODE(v)) + +#define BIT_SHIFT_FWCMDQ_DESC_NUM 0 +#define BIT_MASK_FWCMDQ_DESC_NUM 0xfff +#define BIT_FWCMDQ_DESC_NUM(x) \ + (((x) & BIT_MASK_FWCMDQ_DESC_NUM) << BIT_SHIFT_FWCMDQ_DESC_NUM) +#define BITS_FWCMDQ_DESC_NUM \ + (BIT_MASK_FWCMDQ_DESC_NUM << BIT_SHIFT_FWCMDQ_DESC_NUM) +#define BIT_CLEAR_FWCMDQ_DESC_NUM(x) ((x) & (~BITS_FWCMDQ_DESC_NUM)) +#define BIT_GET_FWCMDQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_DESC_NUM) & BIT_MASK_FWCMDQ_DESC_NUM) +#define BIT_SET_FWCMDQ_DESC_NUM(x, v) \ + (BIT_CLEAR_FWCMDQ_DESC_NUM(x) | BIT_FWCMDQ_DESC_NUM(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DELAY_TIME 24 -#define BIT_MASK_DELAY_TIME 0xff -#define BIT_DELAY_TIME(x) (((x) & BIT_MASK_DELAY_TIME) << BIT_SHIFT_DELAY_TIME) -#define BIT_GET_DELAY_TIME(x) (((x) >> BIT_SHIFT_DELAY_TIME) & BIT_MASK_DELAY_TIME) +/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ -#define BIT_RX_TIMER_DELAY_EN BIT(17) +#define BIT_PCIE_MGQ_FLAG BIT(14) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ +/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ -#define BIT_EN_WATCH_DOG BIT(8) +#define BIT_HCI_MGQ_FLAG BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT) - +/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ -/* 2 REG_MDIO2_V1 (Offset 0x03F8) */ +#define BIT_SHIFT_MGQ_DESC_MODE 12 +#define BIT_MASK_MGQ_DESC_MODE 0x3 +#define BIT_MGQ_DESC_MODE(x) \ + (((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE) +#define BITS_MGQ_DESC_MODE (BIT_MASK_MGQ_DESC_MODE << BIT_SHIFT_MGQ_DESC_MODE) +#define BIT_CLEAR_MGQ_DESC_MODE(x) ((x) & (~BITS_MGQ_DESC_MODE)) +#define BIT_GET_MGQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE) +#define BIT_SET_MGQ_DESC_MODE(x, v) \ + (BIT_CLEAR_MGQ_DESC_MODE(x) | BIT_MGQ_DESC_MODE(v)) + +#define BIT_SHIFT_MGQ_DESC_NUM 0 +#define BIT_MASK_MGQ_DESC_NUM 0xfff +#define BIT_MGQ_DESC_NUM(x) \ + (((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM) +#define BITS_MGQ_DESC_NUM (BIT_MASK_MGQ_DESC_NUM << BIT_SHIFT_MGQ_DESC_NUM) +#define BIT_CLEAR_MGQ_DESC_NUM(x) ((x) & (~BITS_MGQ_DESC_NUM)) +#define BIT_GET_MGQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM) +#define BIT_SET_MGQ_DESC_NUM(x, v) \ + (BIT_CLEAR_MGQ_DESC_NUM(x) | BIT_MGQ_DESC_NUM(v)) -#define BIT_ECRC_EN BIT(7) -#define BIT_MDIO_RFLAG BIT(6) -#define BIT_MDIO_WFLAG BIT(5) +/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ -#define BIT_SHIFT_MDIO_ADDR 0 -#define BIT_MASK_MDIO_ADDR 0x1f -#define BIT_MDIO_ADDR(x) (((x) & BIT_MASK_MDIO_ADDR) << BIT_SHIFT_MDIO_ADDR) -#define BIT_GET_MDIO_ADDR(x) (((x) >> BIT_SHIFT_MDIO_ADDR) & BIT_MASK_MDIO_ADDR) +#define BIT_SYS_32_64 BIT(15) +#define BIT_SHIFT_BCNQ_DESC_MODE 13 +#define BIT_MASK_BCNQ_DESC_MODE 0x3 +#define BIT_BCNQ_DESC_MODE(x) \ + (((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE) +#define BITS_BCNQ_DESC_MODE \ + (BIT_MASK_BCNQ_DESC_MODE << BIT_SHIFT_BCNQ_DESC_MODE) +#define BIT_CLEAR_BCNQ_DESC_MODE(x) ((x) & (~BITS_BCNQ_DESC_MODE)) +#define BIT_GET_BCNQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE) +#define BIT_SET_BCNQ_DESC_MODE(x, v) \ + (BIT_CLEAR_BCNQ_DESC_MODE(x) | BIT_BCNQ_DESC_MODE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +#define BIT_PCIE_BCNQ_FLAG BIT(12) -/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_MDIO_REG_ADDR_V1 0 -#define BIT_MASK_MDIO_REG_ADDR_V1 0x1f -#define BIT_MDIO_REG_ADDR_V1(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1) -#define BIT_GET_MDIO_REG_ADDR_V1(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1) +/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ +#define BIT_HCI_BCNQ_FLAG BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ -#define BIT_RXRST_BACKDOOR BIT(31) -#define BIT_TXRST_BACKDOOR BIT(30) -#define BIT_RXIDX_RSTB BIT(29) -#define BIT_TXIDX_RSTB BIT(28) -#define BIT_DROP_NEXT_RXPKT BIT(27) -#define BIT_SHORT_CORE_RST_SEL BIT(26) +#define BIT_SHIFT_RXQ_DESC_NUM 0 +#define BIT_MASK_RXQ_DESC_NUM 0xfff +#define BIT_RXQ_DESC_NUM(x) \ + (((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM) +#define BITS_RXQ_DESC_NUM (BIT_MASK_RXQ_DESC_NUM << BIT_SHIFT_RXQ_DESC_NUM) +#define BIT_CLEAR_RXQ_DESC_NUM(x) ((x) & (~BITS_RXQ_DESC_NUM)) +#define BIT_GET_RXQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM) +#define BIT_SET_RXQ_DESC_NUM(x, v) \ + (BIT_CLEAR_RXQ_DESC_NUM(x) | BIT_RXQ_DESC_NUM(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ +#define BIT_PCIE_ACH1_FLAG_V1 BIT(30) -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_ACH1_DESC_MODE_V1 28 +#define BIT_MASK_ACH1_DESC_MODE_V1 0x3 +#define BIT_ACH1_DESC_MODE_V1(x) \ + (((x) & BIT_MASK_ACH1_DESC_MODE_V1) << BIT_SHIFT_ACH1_DESC_MODE_V1) +#define BITS_ACH1_DESC_MODE_V1 \ + (BIT_MASK_ACH1_DESC_MODE_V1 << BIT_SHIFT_ACH1_DESC_MODE_V1) +#define BIT_CLEAR_ACH1_DESC_MODE_V1(x) ((x) & (~BITS_ACH1_DESC_MODE_V1)) +#define BIT_GET_ACH1_DESC_MODE_V1(x) \ + (((x) >> BIT_SHIFT_ACH1_DESC_MODE_V1) & BIT_MASK_ACH1_DESC_MODE_V1) +#define BIT_SET_ACH1_DESC_MODE_V1(x, v) \ + (BIT_CLEAR_ACH1_DESC_MODE_V1(x) | BIT_ACH1_DESC_MODE_V1(v)) -#define BIT_EXCEPT_RESUME_EN BIT(25) -#define BIT_EXCEPT_RESUME_FLAG BIT(24) +#define BIT_SHIFT_ACH1_DESC_NUM_V1 16 +#define BIT_MASK_ACH1_DESC_NUM_V1 0xfff +#define BIT_ACH1_DESC_NUM_V1(x) \ + (((x) & BIT_MASK_ACH1_DESC_NUM_V1) << BIT_SHIFT_ACH1_DESC_NUM_V1) +#define BITS_ACH1_DESC_NUM_V1 \ + (BIT_MASK_ACH1_DESC_NUM_V1 << BIT_SHIFT_ACH1_DESC_NUM_V1) +#define BIT_CLEAR_ACH1_DESC_NUM_V1(x) ((x) & (~BITS_ACH1_DESC_NUM_V1)) +#define BIT_GET_ACH1_DESC_NUM_V1(x) \ + (((x) >> BIT_SHIFT_ACH1_DESC_NUM_V1) & BIT_MASK_ACH1_DESC_NUM_V1) +#define BIT_SET_ACH1_DESC_NUM_V1(x, v) \ + (BIT_CLEAR_ACH1_DESC_NUM_V1(x) | BIT_ACH1_DESC_NUM_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +#define BIT_PCIE_VOQ_FLAG BIT(14) -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#endif -#define BIT_ALIGN_MTU BIT(23) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +#define BIT_HCI_VOQ_FLAG BIT(14) -#if (HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ -#define BIT_EARLY_TAG_RETURN BIT(22) +#define BIT_PCIE_ACH0_FLAG BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ +#define BIT_SHIFT_VOQ_DESC_MODE 12 +#define BIT_MASK_VOQ_DESC_MODE 0x3 +#define BIT_VOQ_DESC_MODE(x) \ + (((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE) +#define BITS_VOQ_DESC_MODE (BIT_MASK_VOQ_DESC_MODE << BIT_SHIFT_VOQ_DESC_MODE) +#define BIT_CLEAR_VOQ_DESC_MODE(x) ((x) & (~BITS_VOQ_DESC_MODE)) +#define BIT_GET_VOQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE) +#define BIT_SET_VOQ_DESC_MODE(x, v) \ + (BIT_CLEAR_VOQ_DESC_MODE(x) | BIT_VOQ_DESC_MODE(v)) -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#endif -#define BIT_HOST_GEN2_SUPPORT BIT(20) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TXDMA_ERR_FLAG 16 -#define BIT_MASK_TXDMA_ERR_FLAG 0xf -#define BIT_TXDMA_ERR_FLAG(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG) -#define BIT_GET_TXDMA_ERR_FLAG(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG) +/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ +#define BIT_SHIFT_ACH0_DESC_MODE 12 +#define BIT_MASK_ACH0_DESC_MODE 0x3 +#define BIT_ACH0_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH0_DESC_MODE) << BIT_SHIFT_ACH0_DESC_MODE) +#define BITS_ACH0_DESC_MODE \ + (BIT_MASK_ACH0_DESC_MODE << BIT_SHIFT_ACH0_DESC_MODE) +#define BIT_CLEAR_ACH0_DESC_MODE(x) ((x) & (~BITS_ACH0_DESC_MODE)) +#define BIT_GET_ACH0_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH0_DESC_MODE) & BIT_MASK_ACH0_DESC_MODE) +#define BIT_SET_ACH0_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH0_DESC_MODE(x) | BIT_ACH0_DESC_MODE(v)) -#define BIT_SHIFT_EARLY_MODE_SEL 12 -#define BIT_MASK_EARLY_MODE_SEL 0xf -#define BIT_EARLY_MODE_SEL(x) (((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL) -#define BIT_GET_EARLY_MODE_SEL(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL) +#endif -#define BIT_EPHY_RX50_EN BIT(11) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8 -#define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7 -#define BIT_MSI_TIMEOUT_ID_V1(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1) -#define BIT_GET_MSI_TIMEOUT_ID_V1(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1) +/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ -#define BIT_RADDR_RD BIT(7) -#define BIT_EN_MUL_TAG BIT(6) -#define BIT_EN_EARLY_MODE BIT(5) -#define BIT_L0S_LINK_OFF BIT(4) -#define BIT_ACT_LINK_OFF BIT(3) +#define BIT_SHIFT_VOQ_DESC_NUM 0 +#define BIT_MASK_VOQ_DESC_NUM 0xfff +#define BIT_VOQ_DESC_NUM(x) \ + (((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM) +#define BITS_VOQ_DESC_NUM (BIT_MASK_VOQ_DESC_NUM << BIT_SHIFT_VOQ_DESC_NUM) +#define BIT_CLEAR_VOQ_DESC_NUM(x) ((x) & (~BITS_VOQ_DESC_NUM)) +#define BIT_GET_VOQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM) +#define BIT_SET_VOQ_DESC_NUM(x, v) \ + (BIT_CLEAR_VOQ_DESC_NUM(x) | BIT_VOQ_DESC_NUM(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */ -#define BIT_EN_SLOW_MAC_TX BIT(2) -#define BIT_EN_SLOW_MAC_RX BIT(1) +#define BIT_SHIFT_ACH0_DESC_NUM 0 +#define BIT_MASK_ACH0_DESC_NUM 0xfff +#define BIT_ACH0_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH0_DESC_NUM) << BIT_SHIFT_ACH0_DESC_NUM) +#define BITS_ACH0_DESC_NUM (BIT_MASK_ACH0_DESC_NUM << BIT_SHIFT_ACH0_DESC_NUM) +#define BIT_CLEAR_ACH0_DESC_NUM(x) ((x) & (~BITS_ACH0_DESC_NUM)) +#define BIT_GET_ACH0_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH0_DESC_NUM) & BIT_MASK_ACH0_DESC_NUM) +#define BIT_SET_ACH0_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH0_DESC_NUM(x) | BIT_ACH0_DESC_NUM(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_Q0_INFO (Offset 0x0400) */ +/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ +#define BIT_PCIE_VIQ_FLAG BIT(14) -#define BIT_SHIFT_QUEUEMACID_Q0_V1 25 -#define BIT_MASK_QUEUEMACID_Q0_V1 0x7f -#define BIT_QUEUEMACID_Q0_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1) -#define BIT_GET_QUEUEMACID_Q0_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_QUEUEAC_Q0_V1 23 -#define BIT_MASK_QUEUEAC_Q0_V1 0x3 -#define BIT_QUEUEAC_Q0_V1(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1) -#define BIT_GET_QUEUEAC_Q0_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1) +/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ +#define BIT_HCI_VIQ_FLAG BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ +#define BIT_SHIFT_VIQ_DESC_MODE 12 +#define BIT_MASK_VIQ_DESC_MODE 0x3 +#define BIT_VIQ_DESC_MODE(x) \ + (((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE) +#define BITS_VIQ_DESC_MODE (BIT_MASK_VIQ_DESC_MODE << BIT_SHIFT_VIQ_DESC_MODE) +#define BIT_CLEAR_VIQ_DESC_MODE(x) ((x) & (~BITS_VIQ_DESC_MODE)) +#define BIT_GET_VIQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE) +#define BIT_SET_VIQ_DESC_MODE(x, v) \ + (BIT_CLEAR_VIQ_DESC_MODE(x) | BIT_VIQ_DESC_MODE(v)) + +#define BIT_SHIFT_VIQ_DESC_NUM 0 +#define BIT_MASK_VIQ_DESC_NUM 0xfff +#define BIT_VIQ_DESC_NUM(x) \ + (((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM) +#define BITS_VIQ_DESC_NUM (BIT_MASK_VIQ_DESC_NUM << BIT_SHIFT_VIQ_DESC_NUM) +#define BIT_CLEAR_VIQ_DESC_NUM(x) ((x) & (~BITS_VIQ_DESC_NUM)) +#define BIT_GET_VIQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM) +#define BIT_SET_VIQ_DESC_NUM(x, v) \ + (BIT_CLEAR_VIQ_DESC_NUM(x) | BIT_VIQ_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ + +#define BIT_PCIE_ACH3_FLAG_V1 BIT(30) + +#define BIT_SHIFT_ACH3_DESC_MODE_V1 28 +#define BIT_MASK_ACH3_DESC_MODE_V1 0x3 +#define BIT_ACH3_DESC_MODE_V1(x) \ + (((x) & BIT_MASK_ACH3_DESC_MODE_V1) << BIT_SHIFT_ACH3_DESC_MODE_V1) +#define BITS_ACH3_DESC_MODE_V1 \ + (BIT_MASK_ACH3_DESC_MODE_V1 << BIT_SHIFT_ACH3_DESC_MODE_V1) +#define BIT_CLEAR_ACH3_DESC_MODE_V1(x) ((x) & (~BITS_ACH3_DESC_MODE_V1)) +#define BIT_GET_ACH3_DESC_MODE_V1(x) \ + (((x) >> BIT_SHIFT_ACH3_DESC_MODE_V1) & BIT_MASK_ACH3_DESC_MODE_V1) +#define BIT_SET_ACH3_DESC_MODE_V1(x, v) \ + (BIT_CLEAR_ACH3_DESC_MODE_V1(x) | BIT_ACH3_DESC_MODE_V1(v)) + +#define BIT_SHIFT_ACH3_DESC_NUM_V1 16 +#define BIT_MASK_ACH3_DESC_NUM_V1 0xfff +#define BIT_ACH3_DESC_NUM_V1(x) \ + (((x) & BIT_MASK_ACH3_DESC_NUM_V1) << BIT_SHIFT_ACH3_DESC_NUM_V1) +#define BITS_ACH3_DESC_NUM_V1 \ + (BIT_MASK_ACH3_DESC_NUM_V1 << BIT_SHIFT_ACH3_DESC_NUM_V1) +#define BIT_CLEAR_ACH3_DESC_NUM_V1(x) ((x) & (~BITS_ACH3_DESC_NUM_V1)) +#define BIT_GET_ACH3_DESC_NUM_V1(x) \ + (((x) >> BIT_SHIFT_ACH3_DESC_NUM_V1) & BIT_MASK_ACH3_DESC_NUM_V1) +#define BIT_SET_ACH3_DESC_NUM_V1(x, v) \ + (BIT_CLEAR_ACH3_DESC_NUM_V1(x) | BIT_ACH3_DESC_NUM_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_Q0_INFO (Offset 0x0400) */ +/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ -#define BIT_TIDEMPTY_Q0_V1 BIT(22) +#define BIT_PCIE_BEQ_FLAG BIT(14) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ +#define BIT_HCI_BEQ_FLAG BIT(14) -/* 2 REG_Q0_INFO (Offset 0x0400) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q0_V1 15 -#define BIT_MASK_TAIL_PKT_Q0_V1 0xff -#define BIT_TAIL_PKT_Q0_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V1) << BIT_SHIFT_TAIL_PKT_Q0_V1) -#define BIT_GET_TAIL_PKT_Q0_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V1) & BIT_MASK_TAIL_PKT_Q0_V1) +/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ +#define BIT_PCIE_ACH2_FLAG BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ +#define BIT_SHIFT_BEQ_DESC_MODE 12 +#define BIT_MASK_BEQ_DESC_MODE 0x3 +#define BIT_BEQ_DESC_MODE(x) \ + (((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE) +#define BITS_BEQ_DESC_MODE (BIT_MASK_BEQ_DESC_MODE << BIT_SHIFT_BEQ_DESC_MODE) +#define BIT_CLEAR_BEQ_DESC_MODE(x) ((x) & (~BITS_BEQ_DESC_MODE)) +#define BIT_GET_BEQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE) +#define BIT_SET_BEQ_DESC_MODE(x, v) \ + (BIT_CLEAR_BEQ_DESC_MODE(x) | BIT_BEQ_DESC_MODE(v)) -/* 2 REG_Q0_INFO (Offset 0x0400) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q0_V2 11 -#define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff -#define BIT_TAIL_PKT_Q0_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2) -#define BIT_GET_TAIL_PKT_Q0_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2) +/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ +#define BIT_SHIFT_ACH2_DESC_MODE 12 +#define BIT_MASK_ACH2_DESC_MODE 0x3 +#define BIT_ACH2_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH2_DESC_MODE) << BIT_SHIFT_ACH2_DESC_MODE) +#define BITS_ACH2_DESC_MODE \ + (BIT_MASK_ACH2_DESC_MODE << BIT_SHIFT_ACH2_DESC_MODE) +#define BIT_CLEAR_ACH2_DESC_MODE(x) ((x) & (~BITS_ACH2_DESC_MODE)) +#define BIT_GET_ACH2_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH2_DESC_MODE) & BIT_MASK_ACH2_DESC_MODE) +#define BIT_SET_ACH2_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH2_DESC_MODE(x) | BIT_ACH2_DESC_MODE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_Q0_INFO (Offset 0x0400) */ +/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ +#define BIT_SHIFT_BEQ_DESC_NUM 0 +#define BIT_MASK_BEQ_DESC_NUM 0xfff +#define BIT_BEQ_DESC_NUM(x) \ + (((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM) +#define BITS_BEQ_DESC_NUM (BIT_MASK_BEQ_DESC_NUM << BIT_SHIFT_BEQ_DESC_NUM) +#define BIT_CLEAR_BEQ_DESC_NUM(x) ((x) & (~BITS_BEQ_DESC_NUM)) +#define BIT_GET_BEQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM) +#define BIT_SET_BEQ_DESC_NUM(x, v) \ + (BIT_CLEAR_BEQ_DESC_NUM(x) | BIT_BEQ_DESC_NUM(v)) -#define BIT_SHIFT_PKT_NUM_Q0_V1 8 -#define BIT_MASK_PKT_NUM_Q0_V1 0x7f -#define BIT_PKT_NUM_Q0_V1(x) (((x) & BIT_MASK_PKT_NUM_Q0_V1) << BIT_SHIFT_PKT_NUM_Q0_V1) -#define BIT_GET_PKT_NUM_Q0_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q0_V1) & BIT_MASK_PKT_NUM_Q0_V1) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q0 0 -#define BIT_MASK_HEAD_PKT_Q0 0xff -#define BIT_HEAD_PKT_Q0(x) (((x) & BIT_MASK_HEAD_PKT_Q0) << BIT_SHIFT_HEAD_PKT_Q0) -#define BIT_GET_HEAD_PKT_Q0(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0) & BIT_MASK_HEAD_PKT_Q0) +/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */ +#define BIT_SHIFT_ACH2_DESC_NUM 0 +#define BIT_MASK_ACH2_DESC_NUM 0xfff +#define BIT_ACH2_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH2_DESC_NUM) << BIT_SHIFT_ACH2_DESC_NUM) +#define BITS_ACH2_DESC_NUM (BIT_MASK_ACH2_DESC_NUM << BIT_SHIFT_ACH2_DESC_NUM) +#define BIT_CLEAR_ACH2_DESC_NUM(x) ((x) & (~BITS_ACH2_DESC_NUM)) +#define BIT_GET_ACH2_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH2_DESC_NUM) & BIT_MASK_ACH2_DESC_NUM) +#define BIT_SET_ACH2_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH2_DESC_NUM(x) | BIT_ACH2_DESC_NUM(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ +#define BIT_PCIE_BKQ_FLAG BIT(14) -/* 2 REG_Q0_INFO (Offset 0x0400) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q0_V1 0 -#define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff -#define BIT_HEAD_PKT_Q0_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1) -#define BIT_GET_HEAD_PKT_Q0_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1) +/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ +#define BIT_HCI_BKQ_FLAG BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ +#define BIT_SHIFT_BKQ_DESC_MODE 12 +#define BIT_MASK_BKQ_DESC_MODE 0x3 +#define BIT_BKQ_DESC_MODE(x) \ + (((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE) +#define BITS_BKQ_DESC_MODE (BIT_MASK_BKQ_DESC_MODE << BIT_SHIFT_BKQ_DESC_MODE) +#define BIT_CLEAR_BKQ_DESC_MODE(x) ((x) & (~BITS_BKQ_DESC_MODE)) +#define BIT_GET_BKQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE) +#define BIT_SET_BKQ_DESC_MODE(x, v) \ + (BIT_CLEAR_BKQ_DESC_MODE(x) | BIT_BKQ_DESC_MODE(v)) + +#define BIT_SHIFT_BKQ_DESC_NUM 0 +#define BIT_MASK_BKQ_DESC_NUM 0xfff +#define BIT_BKQ_DESC_NUM(x) \ + (((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM) +#define BITS_BKQ_DESC_NUM (BIT_MASK_BKQ_DESC_NUM << BIT_SHIFT_BKQ_DESC_NUM) +#define BIT_CLEAR_BKQ_DESC_NUM(x) ((x) & (~BITS_BKQ_DESC_NUM)) +#define BIT_GET_BKQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM) +#define BIT_SET_BKQ_DESC_NUM(x, v) \ + (BIT_CLEAR_BKQ_DESC_NUM(x) | BIT_BKQ_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ + +#define BIT_P0HI1Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI1Q_DESC_MODE 28 +#define BIT_MASK_P0HI1Q_DESC_MODE 0x3 +#define BIT_P0HI1Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI1Q_DESC_MODE) << BIT_SHIFT_P0HI1Q_DESC_MODE) +#define BITS_P0HI1Q_DESC_MODE \ + (BIT_MASK_P0HI1Q_DESC_MODE << BIT_SHIFT_P0HI1Q_DESC_MODE) +#define BIT_CLEAR_P0HI1Q_DESC_MODE(x) ((x) & (~BITS_P0HI1Q_DESC_MODE)) +#define BIT_GET_P0HI1Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_DESC_MODE) & BIT_MASK_P0HI1Q_DESC_MODE) +#define BIT_SET_P0HI1Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI1Q_DESC_MODE(x) | BIT_P0HI1Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI1Q_DESC_NUM 16 +#define BIT_MASK_P0HI1Q_DESC_NUM 0xfff +#define BIT_P0HI1Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI1Q_DESC_NUM) << BIT_SHIFT_P0HI1Q_DESC_NUM) +#define BITS_P0HI1Q_DESC_NUM \ + (BIT_MASK_P0HI1Q_DESC_NUM << BIT_SHIFT_P0HI1Q_DESC_NUM) +#define BIT_CLEAR_P0HI1Q_DESC_NUM(x) ((x) & (~BITS_P0HI1Q_DESC_NUM)) +#define BIT_GET_P0HI1Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_DESC_NUM) & BIT_MASK_P0HI1Q_DESC_NUM) +#define BIT_SET_P0HI1Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI1Q_DESC_NUM(x) | BIT_P0HI1Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_Q1_INFO (Offset 0x0404) */ +/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ +#define BIT_HI0Q_FLAG BIT(14) -#define BIT_SHIFT_QUEUEMACID_Q1_V1 25 -#define BIT_MASK_QUEUEMACID_Q1_V1 0x7f -#define BIT_QUEUEMACID_Q1_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1) -#define BIT_GET_QUEUEMACID_Q1_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_QUEUEAC_Q1_V1 23 -#define BIT_MASK_QUEUEAC_Q1_V1 0x3 -#define BIT_QUEUEAC_Q1_V1(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1) -#define BIT_GET_QUEUEAC_Q1_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1) +/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ +#define BIT_P0HI0Q_FLAG BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_Q1_INFO (Offset 0x0404) */ +/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ -#define BIT_TIDEMPTY_Q1_V1 BIT(22) +#define BIT_SHIFT_HI0Q_DESC_MODE 12 +#define BIT_MASK_HI0Q_DESC_MODE 0x3 +#define BIT_HI0Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE) +#define BITS_HI0Q_DESC_MODE \ + (BIT_MASK_HI0Q_DESC_MODE << BIT_SHIFT_HI0Q_DESC_MODE) +#define BIT_CLEAR_HI0Q_DESC_MODE(x) ((x) & (~BITS_HI0Q_DESC_MODE)) +#define BIT_GET_HI0Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE) +#define BIT_SET_HI0Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI0Q_DESC_MODE(x) | BIT_HI0Q_DESC_MODE(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ +#define BIT_SHIFT_P0HI0Q_DESC_MODE 12 +#define BIT_MASK_P0HI0Q_DESC_MODE 0x3 +#define BIT_P0HI0Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI0Q_DESC_MODE) << BIT_SHIFT_P0HI0Q_DESC_MODE) +#define BITS_P0HI0Q_DESC_MODE \ + (BIT_MASK_P0HI0Q_DESC_MODE << BIT_SHIFT_P0HI0Q_DESC_MODE) +#define BIT_CLEAR_P0HI0Q_DESC_MODE(x) ((x) & (~BITS_P0HI0Q_DESC_MODE)) +#define BIT_GET_P0HI0Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_DESC_MODE) & BIT_MASK_P0HI0Q_DESC_MODE) +#define BIT_SET_P0HI0Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI0Q_DESC_MODE(x) | BIT_P0HI0Q_DESC_MODE(v)) -/* 2 REG_Q1_INFO (Offset 0x0404) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q1_V1 15 -#define BIT_MASK_TAIL_PKT_Q1_V1 0xff -#define BIT_TAIL_PKT_Q1_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V1) << BIT_SHIFT_TAIL_PKT_Q1_V1) -#define BIT_GET_TAIL_PKT_Q1_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V1) & BIT_MASK_TAIL_PKT_Q1_V1) +/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ +#define BIT_SHIFT_HI0Q_DESC_NUM 0 +#define BIT_MASK_HI0Q_DESC_NUM 0xfff +#define BIT_HI0Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM) +#define BITS_HI0Q_DESC_NUM (BIT_MASK_HI0Q_DESC_NUM << BIT_SHIFT_HI0Q_DESC_NUM) +#define BIT_CLEAR_HI0Q_DESC_NUM(x) ((x) & (~BITS_HI0Q_DESC_NUM)) +#define BIT_GET_HI0Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM) +#define BIT_SET_HI0Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI0Q_DESC_NUM(x) | BIT_HI0Q_DESC_NUM(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */ +#define BIT_SHIFT_P0HI0Q_DESC_NUM 0 +#define BIT_MASK_P0HI0Q_DESC_NUM 0xfff +#define BIT_P0HI0Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI0Q_DESC_NUM) << BIT_SHIFT_P0HI0Q_DESC_NUM) +#define BITS_P0HI0Q_DESC_NUM \ + (BIT_MASK_P0HI0Q_DESC_NUM << BIT_SHIFT_P0HI0Q_DESC_NUM) +#define BIT_CLEAR_P0HI0Q_DESC_NUM(x) ((x) & (~BITS_P0HI0Q_DESC_NUM)) +#define BIT_GET_P0HI0Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_DESC_NUM) & BIT_MASK_P0HI0Q_DESC_NUM) +#define BIT_SET_P0HI0Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI0Q_DESC_NUM(x) | BIT_P0HI0Q_DESC_NUM(v)) -/* 2 REG_Q1_INFO (Offset 0x0404) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q1_V2 11 -#define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff -#define BIT_TAIL_PKT_Q1_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2) -#define BIT_GET_TAIL_PKT_Q1_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2) +/* 2 REG_HI1Q_TXBD_NUM (Offset 0x038E) */ +#define BIT_HI1Q_FLAG BIT(14) + +#define BIT_SHIFT_HI1Q_DESC_MODE 12 +#define BIT_MASK_HI1Q_DESC_MODE 0x3 +#define BIT_HI1Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE) +#define BITS_HI1Q_DESC_MODE \ + (BIT_MASK_HI1Q_DESC_MODE << BIT_SHIFT_HI1Q_DESC_MODE) +#define BIT_CLEAR_HI1Q_DESC_MODE(x) ((x) & (~BITS_HI1Q_DESC_MODE)) +#define BIT_GET_HI1Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE) +#define BIT_SET_HI1Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI1Q_DESC_MODE(x) | BIT_HI1Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI1Q_DESC_NUM 0 +#define BIT_MASK_HI1Q_DESC_NUM 0xfff +#define BIT_HI1Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM) +#define BITS_HI1Q_DESC_NUM (BIT_MASK_HI1Q_DESC_NUM << BIT_SHIFT_HI1Q_DESC_NUM) +#define BIT_CLEAR_HI1Q_DESC_NUM(x) ((x) & (~BITS_HI1Q_DESC_NUM)) +#define BIT_GET_HI1Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM) +#define BIT_SET_HI1Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI1Q_DESC_NUM(x) | BIT_HI1Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ + +#define BIT_P0HI3Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI3Q_DESC_MODE 28 +#define BIT_MASK_P0HI3Q_DESC_MODE 0x3 +#define BIT_P0HI3Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI3Q_DESC_MODE) << BIT_SHIFT_P0HI3Q_DESC_MODE) +#define BITS_P0HI3Q_DESC_MODE \ + (BIT_MASK_P0HI3Q_DESC_MODE << BIT_SHIFT_P0HI3Q_DESC_MODE) +#define BIT_CLEAR_P0HI3Q_DESC_MODE(x) ((x) & (~BITS_P0HI3Q_DESC_MODE)) +#define BIT_GET_P0HI3Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_DESC_MODE) & BIT_MASK_P0HI3Q_DESC_MODE) +#define BIT_SET_P0HI3Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI3Q_DESC_MODE(x) | BIT_P0HI3Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI3Q_DESC_NUM 16 +#define BIT_MASK_P0HI3Q_DESC_NUM 0xfff +#define BIT_P0HI3Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI3Q_DESC_NUM) << BIT_SHIFT_P0HI3Q_DESC_NUM) +#define BITS_P0HI3Q_DESC_NUM \ + (BIT_MASK_P0HI3Q_DESC_NUM << BIT_SHIFT_P0HI3Q_DESC_NUM) +#define BIT_CLEAR_P0HI3Q_DESC_NUM(x) ((x) & (~BITS_P0HI3Q_DESC_NUM)) +#define BIT_GET_P0HI3Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_DESC_NUM) & BIT_MASK_P0HI3Q_DESC_NUM) +#define BIT_SET_P0HI3Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI3Q_DESC_NUM(x) | BIT_P0HI3Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ +#define BIT_HI2Q_FLAG BIT(14) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_Q1_INFO (Offset 0x0404) */ +/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ +#define BIT_P0HI2Q_FLAG BIT(14) -#define BIT_SHIFT_PKT_NUM_Q1_V1 8 -#define BIT_MASK_PKT_NUM_Q1_V1 0x7f -#define BIT_PKT_NUM_Q1_V1(x) (((x) & BIT_MASK_PKT_NUM_Q1_V1) << BIT_SHIFT_PKT_NUM_Q1_V1) -#define BIT_GET_PKT_NUM_Q1_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q1_V1) & BIT_MASK_PKT_NUM_Q1_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q1 0 -#define BIT_MASK_HEAD_PKT_Q1 0xff -#define BIT_HEAD_PKT_Q1(x) (((x) & BIT_MASK_HEAD_PKT_Q1) << BIT_SHIFT_HEAD_PKT_Q1) -#define BIT_GET_HEAD_PKT_Q1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1) & BIT_MASK_HEAD_PKT_Q1) +/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ +#define BIT_SHIFT_HI2Q_DESC_MODE 12 +#define BIT_MASK_HI2Q_DESC_MODE 0x3 +#define BIT_HI2Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE) +#define BITS_HI2Q_DESC_MODE \ + (BIT_MASK_HI2Q_DESC_MODE << BIT_SHIFT_HI2Q_DESC_MODE) +#define BIT_CLEAR_HI2Q_DESC_MODE(x) ((x) & (~BITS_HI2Q_DESC_MODE)) +#define BIT_GET_HI2Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE) +#define BIT_SET_HI2Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI2Q_DESC_MODE(x) | BIT_HI2Q_DESC_MODE(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ +#define BIT_SHIFT_P0HI2Q_DESC_MODE 12 +#define BIT_MASK_P0HI2Q_DESC_MODE 0x3 +#define BIT_P0HI2Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI2Q_DESC_MODE) << BIT_SHIFT_P0HI2Q_DESC_MODE) +#define BITS_P0HI2Q_DESC_MODE \ + (BIT_MASK_P0HI2Q_DESC_MODE << BIT_SHIFT_P0HI2Q_DESC_MODE) +#define BIT_CLEAR_P0HI2Q_DESC_MODE(x) ((x) & (~BITS_P0HI2Q_DESC_MODE)) +#define BIT_GET_P0HI2Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_DESC_MODE) & BIT_MASK_P0HI2Q_DESC_MODE) +#define BIT_SET_P0HI2Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI2Q_DESC_MODE(x) | BIT_P0HI2Q_DESC_MODE(v)) -/* 2 REG_Q1_INFO (Offset 0x0404) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q1_V1 0 -#define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff -#define BIT_HEAD_PKT_Q1_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1) -#define BIT_GET_HEAD_PKT_Q1_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1) +/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ +#define BIT_SHIFT_HI2Q_DESC_NUM 0 +#define BIT_MASK_HI2Q_DESC_NUM 0xfff +#define BIT_HI2Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM) +#define BITS_HI2Q_DESC_NUM (BIT_MASK_HI2Q_DESC_NUM << BIT_SHIFT_HI2Q_DESC_NUM) +#define BIT_CLEAR_HI2Q_DESC_NUM(x) ((x) & (~BITS_HI2Q_DESC_NUM)) +#define BIT_GET_HI2Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM) +#define BIT_SET_HI2Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI2Q_DESC_NUM(x) | BIT_HI2Q_DESC_NUM(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */ +#define BIT_SHIFT_P0HI2Q_DESC_NUM 0 +#define BIT_MASK_P0HI2Q_DESC_NUM 0xfff +#define BIT_P0HI2Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI2Q_DESC_NUM) << BIT_SHIFT_P0HI2Q_DESC_NUM) +#define BITS_P0HI2Q_DESC_NUM \ + (BIT_MASK_P0HI2Q_DESC_NUM << BIT_SHIFT_P0HI2Q_DESC_NUM) +#define BIT_CLEAR_P0HI2Q_DESC_NUM(x) ((x) & (~BITS_P0HI2Q_DESC_NUM)) +#define BIT_GET_P0HI2Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_DESC_NUM) & BIT_MASK_P0HI2Q_DESC_NUM) +#define BIT_SET_P0HI2Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI2Q_DESC_NUM(x) | BIT_P0HI2Q_DESC_NUM(v)) -/* 2 REG_Q2_INFO (Offset 0x0408) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_QUEUEMACID_Q2_V1 25 -#define BIT_MASK_QUEUEMACID_Q2_V1 0x7f -#define BIT_QUEUEMACID_Q2_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1) -#define BIT_GET_QUEUEMACID_Q2_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1) +/* 2 REG_HI3Q_TXBD_NUM (Offset 0x0392) */ +#define BIT_HI3Q_FLAG BIT(14) + +#define BIT_SHIFT_HI3Q_DESC_MODE 12 +#define BIT_MASK_HI3Q_DESC_MODE 0x3 +#define BIT_HI3Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE) +#define BITS_HI3Q_DESC_MODE \ + (BIT_MASK_HI3Q_DESC_MODE << BIT_SHIFT_HI3Q_DESC_MODE) +#define BIT_CLEAR_HI3Q_DESC_MODE(x) ((x) & (~BITS_HI3Q_DESC_MODE)) +#define BIT_GET_HI3Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE) +#define BIT_SET_HI3Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI3Q_DESC_MODE(x) | BIT_HI3Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI3Q_DESC_NUM 0 +#define BIT_MASK_HI3Q_DESC_NUM 0xfff +#define BIT_HI3Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM) +#define BITS_HI3Q_DESC_NUM (BIT_MASK_HI3Q_DESC_NUM << BIT_SHIFT_HI3Q_DESC_NUM) +#define BIT_CLEAR_HI3Q_DESC_NUM(x) ((x) & (~BITS_HI3Q_DESC_NUM)) +#define BIT_GET_HI3Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM) +#define BIT_SET_HI3Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI3Q_DESC_NUM(x) | BIT_HI3Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ + +#define BIT_P0HI5Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI5Q_DESC_MODE 28 +#define BIT_MASK_P0HI5Q_DESC_MODE 0x3 +#define BIT_P0HI5Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI5Q_DESC_MODE) << BIT_SHIFT_P0HI5Q_DESC_MODE) +#define BITS_P0HI5Q_DESC_MODE \ + (BIT_MASK_P0HI5Q_DESC_MODE << BIT_SHIFT_P0HI5Q_DESC_MODE) +#define BIT_CLEAR_P0HI5Q_DESC_MODE(x) ((x) & (~BITS_P0HI5Q_DESC_MODE)) +#define BIT_GET_P0HI5Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_DESC_MODE) & BIT_MASK_P0HI5Q_DESC_MODE) +#define BIT_SET_P0HI5Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI5Q_DESC_MODE(x) | BIT_P0HI5Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI5Q_DESC_NUM 16 +#define BIT_MASK_P0HI5Q_DESC_NUM 0xfff +#define BIT_P0HI5Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI5Q_DESC_NUM) << BIT_SHIFT_P0HI5Q_DESC_NUM) +#define BITS_P0HI5Q_DESC_NUM \ + (BIT_MASK_P0HI5Q_DESC_NUM << BIT_SHIFT_P0HI5Q_DESC_NUM) +#define BIT_CLEAR_P0HI5Q_DESC_NUM(x) ((x) & (~BITS_P0HI5Q_DESC_NUM)) +#define BIT_GET_P0HI5Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_DESC_NUM) & BIT_MASK_P0HI5Q_DESC_NUM) +#define BIT_SET_P0HI5Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI5Q_DESC_NUM(x) | BIT_P0HI5Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_QUEUEAC_Q2_V1 23 -#define BIT_MASK_QUEUEAC_Q2_V1 0x3 -#define BIT_QUEUEAC_Q2_V1(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1) -#define BIT_GET_QUEUEAC_Q2_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1) +/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ +#define BIT_HI4Q_FLAG BIT(14) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_Q2_INFO (Offset 0x0408) */ +/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ -#define BIT_TIDEMPTY_Q2_V1 BIT(22) +#define BIT_P0HI4Q_FLAG BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ +#define BIT_SHIFT_HI4Q_DESC_MODE 12 +#define BIT_MASK_HI4Q_DESC_MODE 0x3 +#define BIT_HI4Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE) +#define BITS_HI4Q_DESC_MODE \ + (BIT_MASK_HI4Q_DESC_MODE << BIT_SHIFT_HI4Q_DESC_MODE) +#define BIT_CLEAR_HI4Q_DESC_MODE(x) ((x) & (~BITS_HI4Q_DESC_MODE)) +#define BIT_GET_HI4Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE) +#define BIT_SET_HI4Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI4Q_DESC_MODE(x) | BIT_HI4Q_DESC_MODE(v)) -/* 2 REG_Q2_INFO (Offset 0x0408) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q2_V1 15 -#define BIT_MASK_TAIL_PKT_Q2_V1 0xff -#define BIT_TAIL_PKT_Q2_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V1) << BIT_SHIFT_TAIL_PKT_Q2_V1) -#define BIT_GET_TAIL_PKT_Q2_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V1) & BIT_MASK_TAIL_PKT_Q2_V1) +/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ +#define BIT_SHIFT_P0HI4Q_DESC_MODE 12 +#define BIT_MASK_P0HI4Q_DESC_MODE 0x3 +#define BIT_P0HI4Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI4Q_DESC_MODE) << BIT_SHIFT_P0HI4Q_DESC_MODE) +#define BITS_P0HI4Q_DESC_MODE \ + (BIT_MASK_P0HI4Q_DESC_MODE << BIT_SHIFT_P0HI4Q_DESC_MODE) +#define BIT_CLEAR_P0HI4Q_DESC_MODE(x) ((x) & (~BITS_P0HI4Q_DESC_MODE)) +#define BIT_GET_P0HI4Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_DESC_MODE) & BIT_MASK_P0HI4Q_DESC_MODE) +#define BIT_SET_P0HI4Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI4Q_DESC_MODE(x) | BIT_P0HI4Q_DESC_MODE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ +#define BIT_SHIFT_HI4Q_DESC_NUM 0 +#define BIT_MASK_HI4Q_DESC_NUM 0xfff +#define BIT_HI4Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM) +#define BITS_HI4Q_DESC_NUM (BIT_MASK_HI4Q_DESC_NUM << BIT_SHIFT_HI4Q_DESC_NUM) +#define BIT_CLEAR_HI4Q_DESC_NUM(x) ((x) & (~BITS_HI4Q_DESC_NUM)) +#define BIT_GET_HI4Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM) +#define BIT_SET_HI4Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI4Q_DESC_NUM(x) | BIT_HI4Q_DESC_NUM(v)) -/* 2 REG_Q2_INFO (Offset 0x0408) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q2_V2 11 -#define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff -#define BIT_TAIL_PKT_Q2_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2) -#define BIT_GET_TAIL_PKT_Q2_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2) +/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */ +#define BIT_SHIFT_P0HI4Q_DESC_NUM 0 +#define BIT_MASK_P0HI4Q_DESC_NUM 0xfff +#define BIT_P0HI4Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI4Q_DESC_NUM) << BIT_SHIFT_P0HI4Q_DESC_NUM) +#define BITS_P0HI4Q_DESC_NUM \ + (BIT_MASK_P0HI4Q_DESC_NUM << BIT_SHIFT_P0HI4Q_DESC_NUM) +#define BIT_CLEAR_P0HI4Q_DESC_NUM(x) ((x) & (~BITS_P0HI4Q_DESC_NUM)) +#define BIT_GET_P0HI4Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_DESC_NUM) & BIT_MASK_P0HI4Q_DESC_NUM) +#define BIT_SET_P0HI4Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI4Q_DESC_NUM(x) | BIT_P0HI4Q_DESC_NUM(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI5Q_TXBD_NUM (Offset 0x0396) */ +#define BIT_HI5Q_FLAG BIT(14) + +#define BIT_SHIFT_HI5Q_DESC_MODE 12 +#define BIT_MASK_HI5Q_DESC_MODE 0x3 +#define BIT_HI5Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE) +#define BITS_HI5Q_DESC_MODE \ + (BIT_MASK_HI5Q_DESC_MODE << BIT_SHIFT_HI5Q_DESC_MODE) +#define BIT_CLEAR_HI5Q_DESC_MODE(x) ((x) & (~BITS_HI5Q_DESC_MODE)) +#define BIT_GET_HI5Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE) +#define BIT_SET_HI5Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI5Q_DESC_MODE(x) | BIT_HI5Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI5Q_DESC_NUM 0 +#define BIT_MASK_HI5Q_DESC_NUM 0xfff +#define BIT_HI5Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM) +#define BITS_HI5Q_DESC_NUM (BIT_MASK_HI5Q_DESC_NUM << BIT_SHIFT_HI5Q_DESC_NUM) +#define BIT_CLEAR_HI5Q_DESC_NUM(x) ((x) & (~BITS_HI5Q_DESC_NUM)) +#define BIT_GET_HI5Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM) +#define BIT_SET_HI5Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI5Q_DESC_NUM(x) | BIT_HI5Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ + +#define BIT_P0HI7Q_FLAG BIT(30) +#define BIT_CLR_FWCMDQ_HW_IDX BIT(30) +#define BIT_CLR_P0HI7Q_HW_IDX BIT(29) + +#define BIT_SHIFT_P0HI7Q_DESC_MODE 28 +#define BIT_MASK_P0HI7Q_DESC_MODE 0x3 +#define BIT_P0HI7Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI7Q_DESC_MODE) << BIT_SHIFT_P0HI7Q_DESC_MODE) +#define BITS_P0HI7Q_DESC_MODE \ + (BIT_MASK_P0HI7Q_DESC_MODE << BIT_SHIFT_P0HI7Q_DESC_MODE) +#define BIT_CLEAR_P0HI7Q_DESC_MODE(x) ((x) & (~BITS_P0HI7Q_DESC_MODE)) +#define BIT_GET_P0HI7Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_DESC_MODE) & BIT_MASK_P0HI7Q_DESC_MODE) +#define BIT_SET_P0HI7Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI7Q_DESC_MODE(x) | BIT_P0HI7Q_DESC_MODE(v)) + +#define BIT_CLR_P0HI6Q_HW_IDX BIT(28) +#define BIT_CLR_P0HI5Q_HW_IDX BIT(27) +#define BIT_CLR_P0HI4Q_HW_IDX BIT(26) +#define BIT_CLR_P0HI3Q_HW_IDX BIT(25) +#define BIT_CLR_P0HI2Q_HW_IDX BIT(24) +#define BIT_CLR_P0HI1Q_HW_IDX BIT(23) +#define BIT_CLR_P0HI0Q_HW_IDX BIT(22) +#define BIT_CLR_ACH3_HW_IDX BIT(21) +#define BIT_CLR_ACH2_HW_IDX BIT(20) +#define BIT_CLR_ACH1_HW_IDX BIT(19) +#define BIT_CLR_ACH0_HW_IDX BIT(18) +#define BIT_CLR_P0MGQ_HW_IDX BIT(17) + +#define BIT_SHIFT_P0HI7Q_DESC_NUM 16 +#define BIT_MASK_P0HI7Q_DESC_NUM 0xfff +#define BIT_P0HI7Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI7Q_DESC_NUM) << BIT_SHIFT_P0HI7Q_DESC_NUM) +#define BITS_P0HI7Q_DESC_NUM \ + (BIT_MASK_P0HI7Q_DESC_NUM << BIT_SHIFT_P0HI7Q_DESC_NUM) +#define BIT_CLEAR_P0HI7Q_DESC_NUM(x) ((x) & (~BITS_P0HI7Q_DESC_NUM)) +#define BIT_GET_P0HI7Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_DESC_NUM) & BIT_MASK_P0HI7Q_DESC_NUM) +#define BIT_SET_P0HI7Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI7Q_DESC_NUM(x) | BIT_P0HI7Q_DESC_NUM(v)) + +#define BIT_CLR_P0RXQ_HW_IDX BIT(16) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_Q2_INFO (Offset 0x0408) */ +/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ +#define BIT_HI6Q_FLAG BIT(14) -#define BIT_SHIFT_PKT_NUM_Q2_V1 8 -#define BIT_MASK_PKT_NUM_Q2_V1 0x7f -#define BIT_PKT_NUM_Q2_V1(x) (((x) & BIT_MASK_PKT_NUM_Q2_V1) << BIT_SHIFT_PKT_NUM_Q2_V1) -#define BIT_GET_PKT_NUM_Q2_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q2_V1) & BIT_MASK_PKT_NUM_Q2_V1) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q2 0 -#define BIT_MASK_HEAD_PKT_Q2 0xff -#define BIT_HEAD_PKT_Q2(x) (((x) & BIT_MASK_HEAD_PKT_Q2) << BIT_SHIFT_HEAD_PKT_Q2) -#define BIT_GET_HEAD_PKT_Q2(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2) & BIT_MASK_HEAD_PKT_Q2) +/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ +#define BIT_P0HI6Q_FLAG BIT(14) +#define BIT_CLR_PFWCMDQ_HOST_IDX BIT(14) +#define BIT_CLR_P0HI7Q_HOST_IDX BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ +#define BIT_SHIFT_HI6Q_DESC_MODE 12 +#define BIT_MASK_HI6Q_DESC_MODE 0x3 +#define BIT_HI6Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE) +#define BITS_HI6Q_DESC_MODE \ + (BIT_MASK_HI6Q_DESC_MODE << BIT_SHIFT_HI6Q_DESC_MODE) +#define BIT_CLEAR_HI6Q_DESC_MODE(x) ((x) & (~BITS_HI6Q_DESC_MODE)) +#define BIT_GET_HI6Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE) +#define BIT_SET_HI6Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI6Q_DESC_MODE(x) | BIT_HI6Q_DESC_MODE(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ + +#define BIT_SHIFT_P0HI6Q_DESC_MODE 12 +#define BIT_MASK_P0HI6Q_DESC_MODE 0x3 +#define BIT_P0HI6Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI6Q_DESC_MODE) << BIT_SHIFT_P0HI6Q_DESC_MODE) +#define BITS_P0HI6Q_DESC_MODE \ + (BIT_MASK_P0HI6Q_DESC_MODE << BIT_SHIFT_P0HI6Q_DESC_MODE) +#define BIT_CLEAR_P0HI6Q_DESC_MODE(x) ((x) & (~BITS_P0HI6Q_DESC_MODE)) +#define BIT_GET_P0HI6Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_DESC_MODE) & BIT_MASK_P0HI6Q_DESC_MODE) +#define BIT_SET_P0HI6Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI6Q_DESC_MODE(x) | BIT_P0HI6Q_DESC_MODE(v)) + +#define BIT_CLR_P0HI6Q_HOST_IDX BIT(12) +#define BIT_CLR_P0HI5Q_HOST_IDX BIT(11) +#define BIT_CLR_P0HI4Q_HOST_IDX BIT(10) +#define BIT_CLR_P0HI3Q_HOST_IDX BIT(9) +#define BIT_CLR_P0HI2Q_HOST_IDX BIT(8) +#define BIT_CLR_P0HI1Q_HOST_IDX BIT(7) +#define BIT_CLR_P0HI0Q_HOST_IDX BIT(6) +#define BIT_CLR_ACH3_HOST_IDX BIT(5) +#define BIT_CLR_ACH2_HOST_IDX BIT(4) +#define BIT_CLR_ACH1_HOST_IDX BIT(3) +#define BIT_CLR_ACH0_HOST_IDX BIT(2) +#define BIT_CLR_P0MGQ_HOST_IDX BIT(1) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_Q2_INFO (Offset 0x0408) */ +/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ + +#define BIT_SHIFT_HI6Q_DESC_NUM 0 +#define BIT_MASK_HI6Q_DESC_NUM 0xfff +#define BIT_HI6Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM) +#define BITS_HI6Q_DESC_NUM (BIT_MASK_HI6Q_DESC_NUM << BIT_SHIFT_HI6Q_DESC_NUM) +#define BIT_CLEAR_HI6Q_DESC_NUM(x) ((x) & (~BITS_HI6Q_DESC_NUM)) +#define BIT_GET_HI6Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM) +#define BIT_SET_HI6Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI6Q_DESC_NUM(x) | BIT_HI6Q_DESC_NUM(v)) +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q2_V1 0 -#define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff -#define BIT_HEAD_PKT_Q2_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1) -#define BIT_GET_HEAD_PKT_Q2_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1) +/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */ +#define BIT_SHIFT_P0HI6Q_DESC_NUM 0 +#define BIT_MASK_P0HI6Q_DESC_NUM 0xfff +#define BIT_P0HI6Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI6Q_DESC_NUM) << BIT_SHIFT_P0HI6Q_DESC_NUM) +#define BITS_P0HI6Q_DESC_NUM \ + (BIT_MASK_P0HI6Q_DESC_NUM << BIT_SHIFT_P0HI6Q_DESC_NUM) +#define BIT_CLEAR_P0HI6Q_DESC_NUM(x) ((x) & (~BITS_P0HI6Q_DESC_NUM)) +#define BIT_GET_P0HI6Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_DESC_NUM) & BIT_MASK_P0HI6Q_DESC_NUM) +#define BIT_SET_P0HI6Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI6Q_DESC_NUM(x) | BIT_P0HI6Q_DESC_NUM(v)) + +#define BIT_CLR_P0RXQ_HOST_IDX BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI7Q_TXBD_NUM (Offset 0x039A) */ +#define BIT_HI7Q_FLAG BIT(14) + +#define BIT_SHIFT_HI7Q_DESC_MODE 12 +#define BIT_MASK_HI7Q_DESC_MODE 0x3 +#define BIT_HI7Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE) +#define BITS_HI7Q_DESC_MODE \ + (BIT_MASK_HI7Q_DESC_MODE << BIT_SHIFT_HI7Q_DESC_MODE) +#define BIT_CLEAR_HI7Q_DESC_MODE(x) ((x) & (~BITS_HI7Q_DESC_MODE)) +#define BIT_GET_HI7Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE) +#define BIT_SET_HI7Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI7Q_DESC_MODE(x) | BIT_HI7Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI7Q_DESC_NUM 0 +#define BIT_MASK_HI7Q_DESC_NUM 0xfff +#define BIT_HI7Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM) +#define BITS_HI7Q_DESC_NUM (BIT_MASK_HI7Q_DESC_NUM << BIT_SHIFT_HI7Q_DESC_NUM) +#define BIT_CLEAR_HI7Q_DESC_NUM(x) ((x) & (~BITS_HI7Q_DESC_NUM)) +#define BIT_GET_HI7Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM) +#define BIT_SET_HI7Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI7Q_DESC_NUM(x) | BIT_HI7Q_DESC_NUM(v)) -/* 2 REG_Q3_INFO (Offset 0x040C) */ +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI7Q_HW_IDX BIT(29) +#define BIT_CLR_HI6Q_HW_IDX BIT(28) +#define BIT_CLR_HI5Q_HW_IDX BIT(27) +#define BIT_CLR_HI4Q_HW_IDX BIT(26) +#define BIT_CLR_HI3Q_HW_IDX BIT(25) +#define BIT_CLR_HI2Q_HW_IDX BIT(24) +#define BIT_CLR_HI1Q_HW_IDX BIT(23) -#define BIT_SHIFT_QUEUEMACID_Q3_V1 25 -#define BIT_MASK_QUEUEMACID_Q3_V1 0x7f -#define BIT_QUEUEMACID_Q3_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1) -#define BIT_GET_QUEUEMACID_Q3_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1) +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_QUEUEAC_Q3_V1 23 -#define BIT_MASK_QUEUEAC_Q3_V1 0x3 -#define BIT_QUEUEAC_Q3_V1(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1) -#define BIT_GET_QUEUEAC_Q3_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_BCN7DOK BIT(23) +#define BIT_BCN7DOKM BIT(23) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI0Q_HW_IDX BIT(22) -/* 2 REG_Q3_INFO (Offset 0x040C) */ +#endif + +#if (HALMAC_8881A_SUPPORT) + +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_TIDEMPTY_Q3_V1 BIT(22) +#define BIT_BCN6DOK BIT(22) +#define BIT_BCN6DOKM BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_BKQ_HW_IDX BIT(21) -/* 2 REG_Q3_INFO (Offset 0x040C) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q3_V1 15 -#define BIT_MASK_TAIL_PKT_Q3_V1 0xff -#define BIT_TAIL_PKT_Q3_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V1) << BIT_SHIFT_TAIL_PKT_Q3_V1) -#define BIT_GET_TAIL_PKT_Q3_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V1) & BIT_MASK_TAIL_PKT_Q3_V1) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_BCN5DOK BIT(21) +#define BIT_BCN5DOKM BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_BEQ_HW_IDX BIT(20) -/* 2 REG_Q3_INFO (Offset 0x040C) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q3_V2 11 -#define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff -#define BIT_TAIL_PKT_Q3_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2) -#define BIT_GET_TAIL_PKT_Q3_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_BCN4DOK BIT(20) +#define BIT_BCN4DOKM BIT(20) +#define BIT_RX_OVER_RD_ERR BIT(20) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_VIQ_HW_IDX BIT(19) -/* 2 REG_Q3_INFO (Offset 0x040C) */ +#endif + +#if (HALMAC_8881A_SUPPORT) + +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_BCN3DOK BIT(19) +#define BIT_BCN3DOKM BIT(19) +#define BIT_RXDMA_STUCK BIT(19) -#define BIT_SHIFT_PKT_NUM_Q3_V1 8 -#define BIT_MASK_PKT_NUM_Q3_V1 0x7f -#define BIT_PKT_NUM_Q3_V1(x) (((x) & BIT_MASK_PKT_NUM_Q3_V1) << BIT_SHIFT_PKT_NUM_Q3_V1) -#define BIT_GET_PKT_NUM_Q3_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q3_V1) & BIT_MASK_PKT_NUM_Q3_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q3 0 -#define BIT_MASK_HEAD_PKT_Q3 0xff -#define BIT_HEAD_PKT_Q3(x) (((x) & BIT_MASK_HEAD_PKT_Q3) << BIT_SHIFT_HEAD_PKT_Q3) -#define BIT_GET_HEAD_PKT_Q3(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3) & BIT_MASK_HEAD_PKT_Q3) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_VOQ_HW_IDX BIT(18) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_BCN2DOK BIT(18) +#define BIT_BCN2DOKM BIT(18) -/* 2 REG_Q3_INFO (Offset 0x040C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q3_V1 0 -#define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff -#define BIT_HEAD_PKT_Q3_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1) -#define BIT_GET_HEAD_PKT_Q3_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_MGQ_HW_IDX BIT(17) #endif +#if (HALMAC_8881A_SUPPORT) + +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ + +#define BIT_BCN1DOK BIT(17) +#define BIT_BCN1DOKM BIT(17) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ +#define BIT_SHIFT_TSFT2_HCI 16 +#define BIT_MASK_TSFT2_HCI 0xffff +#define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI) +#define BITS_TSFT2_HCI (BIT_MASK_TSFT2_HCI << BIT_SHIFT_TSFT2_HCI) +#define BIT_CLEAR_TSFT2_HCI(x) ((x) & (~BITS_TSFT2_HCI)) +#define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI) +#define BIT_SET_TSFT2_HCI(x, v) (BIT_CLEAR_TSFT2_HCI(x) | BIT_TSFT2_HCI(v)) -#define BIT_SHIFT_QUEUEMACID_MGQ_V1 25 -#define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f -#define BIT_QUEUEMACID_MGQ_V1(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1) -#define BIT_GET_QUEUEMACID_MGQ_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_QUEUEAC_MGQ_V1 23 -#define BIT_MASK_QUEUEAC_MGQ_V1 0x3 -#define BIT_QUEUEAC_MGQ_V1(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1) -#define BIT_GET_QUEUEAC_MGQ_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_RXQ_HW_IDX BIT(16) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_BCN0DOK BIT(16) +#define BIT_BCN0DOKM BIT(16) -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_RX_STATE 16 +#define BIT_MASK_RX_STATE 0x7 +#define BIT_RX_STATE(x) (((x) & BIT_MASK_RX_STATE) << BIT_SHIFT_RX_STATE) +#define BITS_RX_STATE (BIT_MASK_RX_STATE << BIT_SHIFT_RX_STATE) +#define BIT_CLEAR_RX_STATE(x) ((x) & (~BITS_RX_STATE)) +#define BIT_GET_RX_STATE(x) (((x) >> BIT_SHIFT_RX_STATE) & BIT_MASK_RX_STATE) +#define BIT_SET_RX_STATE(x, v) (BIT_CLEAR_RX_STATE(x) | BIT_RX_STATE(v)) -#define BIT_TIDEMPTY_MGQ_V1 BIT(22) +#define BIT_SRST_TX BIT(15) +#define BIT_M7DOK BIT(15) +#define BIT_M7DOKM BIT(15) +#define BIT_TDE_NO_IDLE BIT(15) +#define BIT_SRST_RX BIT(14) +#define BIT_M6DOK BIT(14) +#define BIT_M6DOKM BIT(14) +#define BIT_TXDMA_STUCK BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI7Q_HOST_IDX BIT(13) -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_MGQ_V1 15 -#define BIT_MASK_TAIL_PKT_MGQ_V1 0xff -#define BIT_TAIL_PKT_MGQ_V1(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V1) << BIT_SHIFT_TAIL_PKT_MGQ_V1) -#define BIT_GET_TAIL_PKT_MGQ_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V1) & BIT_MASK_TAIL_PKT_MGQ_V1) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_M5DOK BIT(13) +#define BIT_M5DOKM BIT(13) +#define BIT_TDE_FULL_ERR BIT(13) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI6Q_HOST_IDX BIT(12) -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_MGQ_V2 11 -#define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff -#define BIT_TAIL_PKT_MGQ_V2(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2) -#define BIT_GET_TAIL_PKT_MGQ_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_M4DOK BIT(12) +#define BIT_M4DOKM BIT(12) +#define BIT_HD_SIZE_ERR BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI5Q_HOST_IDX BIT(11) -#define BIT_SHIFT_PKT_NUM_MGQ_V1 8 -#define BIT_MASK_PKT_NUM_MGQ_V1 0x7f -#define BIT_PKT_NUM_MGQ_V1(x) (((x) & BIT_MASK_PKT_NUM_MGQ_V1) << BIT_SHIFT_PKT_NUM_MGQ_V1) -#define BIT_GET_PKT_NUM_MGQ_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_MGQ_V1) & BIT_MASK_PKT_NUM_MGQ_V1) +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_MGQ 0 -#define BIT_MASK_HEAD_PKT_MGQ 0xff -#define BIT_HEAD_PKT_MGQ(x) (((x) & BIT_MASK_HEAD_PKT_MGQ) << BIT_SHIFT_HEAD_PKT_MGQ) -#define BIT_GET_HEAD_PKT_MGQ(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ) & BIT_MASK_HEAD_PKT_MGQ) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_M3DOK BIT(11) +#define BIT_M3DOKM BIT(11) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI4Q_HOST_IDX BIT(10) -/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_MGQ_V1 0 -#define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff -#define BIT_HEAD_PKT_MGQ_V1(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1) -#define BIT_GET_HEAD_PKT_MGQ_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_M2DOK BIT(10) +#define BIT_M2DOKM BIT(10) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI3Q_HOST_IDX BIT(9) -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#endif + +#if (HALMAC_8881A_SUPPORT) + +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_M1DOK BIT(9) +#define BIT_M1DOKM BIT(9) -#define BIT_SHIFT_QUEUEMACID_HIQ_V1 25 -#define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f -#define BIT_QUEUEMACID_HIQ_V1(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1) -#define BIT_GET_QUEUEMACID_HIQ_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_QUEUEAC_HIQ_V1 23 -#define BIT_MASK_QUEUEAC_HIQ_V1 0x3 -#define BIT_QUEUEAC_HIQ_V1(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1) -#define BIT_GET_QUEUEAC_HIQ_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI2Q_HOST_IDX BIT(8) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_M0DOK BIT(8) +#define BIT_M0DOKM BIT(8) -#define BIT_TIDEMPTY_HIQ_V1 BIT(22) +#define BIT_SHIFT_TX_STATE 8 +#define BIT_MASK_TX_STATE 0xf +#define BIT_TX_STATE(x) (((x) & BIT_MASK_TX_STATE) << BIT_SHIFT_TX_STATE) +#define BITS_TX_STATE (BIT_MASK_TX_STATE << BIT_SHIFT_TX_STATE) +#define BIT_CLEAR_TX_STATE(x) ((x) & (~BITS_TX_STATE)) +#define BIT_GET_TX_STATE(x) (((x) >> BIT_SHIFT_TX_STATE) & BIT_MASK_TX_STATE) +#define BIT_SET_TX_STATE(x, v) (BIT_CLEAR_TX_STATE(x) | BIT_TX_STATE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_HI1Q_HOST_IDX BIT(7) +#define BIT_CLR_HI0Q_HOST_IDX BIT(6) -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_HIQ_V1 15 -#define BIT_MASK_TAIL_PKT_HIQ_V1 0xff -#define BIT_TAIL_PKT_HIQ_V1(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V1) << BIT_SHIFT_TAIL_PKT_HIQ_V1) -#define BIT_GET_TAIL_PKT_HIQ_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V1) & BIT_MASK_TAIL_PKT_HIQ_V1) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_MGQDOK BIT(6) +#define BIT_MGQDOKM BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_BKQ_HOST_IDX BIT(5) -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_HIQ_V2 11 -#define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff -#define BIT_TAIL_PKT_HIQ_V2(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2) -#define BIT_GET_TAIL_PKT_HIQ_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_BKQDOK BIT(5) +#define BIT_BKQDOKM BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_CLR_BEQ_HOST_IDX BIT(4) +#endif -#define BIT_SHIFT_PKT_NUM_HIQ_V1 8 -#define BIT_MASK_PKT_NUM_HIQ_V1 0x7f -#define BIT_PKT_NUM_HIQ_V1(x) (((x) & BIT_MASK_PKT_NUM_HIQ_V1) << BIT_SHIFT_PKT_NUM_HIQ_V1) -#define BIT_GET_PKT_NUM_HIQ_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_HIQ_V1) & BIT_MASK_PKT_NUM_HIQ_V1) +#if (HALMAC_8881A_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_SHIFT_HEAD_PKT_HIQ 0 -#define BIT_MASK_HEAD_PKT_HIQ 0xff -#define BIT_HEAD_PKT_HIQ(x) (((x) & BIT_MASK_HEAD_PKT_HIQ) << BIT_SHIFT_HEAD_PKT_HIQ) -#define BIT_GET_HEAD_PKT_HIQ(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ) & BIT_MASK_HEAD_PKT_HIQ) +#define BIT_SHIFT_HPS_CLKR 4 +#define BIT_MASK_HPS_CLKR 0x3 +#define BIT_HPS_CLKR(x) (((x) & BIT_MASK_HPS_CLKR) << BIT_SHIFT_HPS_CLKR) +#define BITS_HPS_CLKR (BIT_MASK_HPS_CLKR << BIT_SHIFT_HPS_CLKR) +#define BIT_CLEAR_HPS_CLKR(x) ((x) & (~BITS_HPS_CLKR)) +#define BIT_GET_HPS_CLKR(x) (((x) >> BIT_SHIFT_HPS_CLKR) & BIT_MASK_HPS_CLKR) +#define BIT_SET_HPS_CLKR(x, v) (BIT_CLEAR_HPS_CLKR(x) | BIT_HPS_CLKR(v)) +#define BIT_BEQDOK BIT(4) +#define BIT_BEQDOKM BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_VIQ_HOST_IDX BIT(3) -/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_HIQ_V1 0 -#define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff -#define BIT_HEAD_PKT_HIQ_V1(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1) -#define BIT_GET_HEAD_PKT_HIQ_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_LX_INT BIT(3) +#define BIT_VIQDOK BIT(3) +#define BIT_VIQDOKM BIT(3) +#define BIT_MST_BUSY BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_BCNQ_INFO (Offset 0x0418) */ +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_VOQ_HOST_IDX BIT(2) -#define BIT_SHIFT_PKT_NUM_BCNQ 8 -#define BIT_MASK_PKT_NUM_BCNQ 0xff -#define BIT_PKT_NUM_BCNQ(x) (((x) & BIT_MASK_PKT_NUM_BCNQ) << BIT_SHIFT_PKT_NUM_BCNQ) -#define BIT_GET_PKT_NUM_BCNQ(x) (((x) >> BIT_SHIFT_PKT_NUM_BCNQ) & BIT_MASK_PKT_NUM_BCNQ) +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCNQ_HEAD_PG 0 -#define BIT_MASK_BCNQ_HEAD_PG 0xff -#define BIT_BCNQ_HEAD_PG(x) (((x) & BIT_MASK_BCNQ_HEAD_PG) << BIT_SHIFT_BCNQ_HEAD_PG) -#define BIT_GET_BCNQ_HEAD_PG(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG) & BIT_MASK_BCNQ_HEAD_PG) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_VOQDOK BIT(2) +#define BIT_VOQDOKM BIT(2) +#define BIT_SLV_BUSY BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_MGQ_HOST_IDX BIT(1) -/* 2 REG_BCNQ_INFO (Offset 0x0418) */ +#endif +#if (HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCNQ_HEAD_PG_V1 0 -#define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff -#define BIT_BCNQ_HEAD_PG_V1(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1) -#define BIT_GET_BCNQ_HEAD_PG_V1(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1) +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_RDUM BIT(1) +#define BIT_RXDES_UNAVAIL BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ +#define BIT_SHIFT_TSFT1_HCI 0 +#define BIT_MASK_TSFT1_HCI 0xffff +#define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI) +#define BITS_TSFT1_HCI (BIT_MASK_TSFT1_HCI << BIT_SHIFT_TSFT1_HCI) +#define BIT_CLEAR_TSFT1_HCI(x) ((x) & (~BITS_TSFT1_HCI)) +#define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI) +#define BIT_SET_TSFT1_HCI(x, v) (BIT_CLEAR_TSFT1_HCI(x) | BIT_TSFT1_HCI(v)) -/* 2 REG_TXPKT_EMPTY (Offset 0x041A) */ +#endif -#define BIT_BCNQ_EMPTY BIT(11) -#define BIT_HQQ_EMPTY BIT(10) -#define BIT_MQQ_EMPTY BIT(9) -#define BIT_MGQ_CPU_EMPTY BIT(8) -#define BIT_AC7Q_EMPTY BIT(7) -#define BIT_AC6Q_EMPTY BIT(6) -#define BIT_AC5Q_EMPTY BIT(5) -#define BIT_AC4Q_EMPTY BIT(4) -#define BIT_AC3Q_EMPTY BIT(3) -#define BIT_AC2Q_EMPTY BIT(2) -#define BIT_AC1Q_EMPTY BIT(1) -#define BIT_AC0Q_EMPTY BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ +#define BIT_CLR_RXQ_HOST_IDX BIT(0) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8881A_SUPPORT) -/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ -#define BIT_BCN1_POLL BIT(30) +#define BIT_RXDOK BIT(0) +#define BIT_RXDOKM BIT(0) +#define BIT_EN_DBG_STUCK BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */ +#define BIT_SHIFT_VOQ_HW_IDX 16 +#define BIT_MASK_VOQ_HW_IDX 0xfff +#define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX) +#define BITS_VOQ_HW_IDX (BIT_MASK_VOQ_HW_IDX << BIT_SHIFT_VOQ_HW_IDX) +#define BIT_CLEAR_VOQ_HW_IDX(x) ((x) & (~BITS_VOQ_HW_IDX)) +#define BIT_GET_VOQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX) +#define BIT_SET_VOQ_HW_IDX(x, v) (BIT_CLEAR_VOQ_HW_IDX(x) | BIT_VOQ_HW_IDX(v)) -/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#endif -#define BIT_CPUMGT_POLL BIT(29) -#define BIT_BCN_POLL BIT(28) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ACH0_TXBD_IDX (Offset 0x03A0) */ +#define BIT_SHIFT_ACH0_HW_IDX 16 +#define BIT_MASK_ACH0_HW_IDX 0xfff +#define BIT_ACH0_HW_IDX(x) \ + (((x) & BIT_MASK_ACH0_HW_IDX) << BIT_SHIFT_ACH0_HW_IDX) +#define BITS_ACH0_HW_IDX (BIT_MASK_ACH0_HW_IDX << BIT_SHIFT_ACH0_HW_IDX) +#define BIT_CLEAR_ACH0_HW_IDX(x) ((x) & (~BITS_ACH0_HW_IDX)) +#define BIT_GET_ACH0_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH0_HW_IDX) & BIT_MASK_ACH0_HW_IDX) +#define BIT_SET_ACH0_HW_IDX(x, v) \ + (BIT_CLEAR_ACH0_HW_IDX(x) | BIT_ACH0_HW_IDX(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +/* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */ -#define BIT_CPUMGQ_FW_NUM_V1 BIT(12) +#define BIT_SHIFT_VOQ_HOST_IDX 0 +#define BIT_MASK_VOQ_HOST_IDX 0xfff +#define BIT_VOQ_HOST_IDX(x) \ + (((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX) +#define BITS_VOQ_HOST_IDX (BIT_MASK_VOQ_HOST_IDX << BIT_SHIFT_VOQ_HOST_IDX) +#define BIT_CLEAR_VOQ_HOST_IDX(x) ((x) & (~BITS_VOQ_HOST_IDX)) +#define BIT_GET_VOQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX) +#define BIT_SET_VOQ_HOST_IDX(x, v) \ + (BIT_CLEAR_VOQ_HOST_IDX(x) | BIT_VOQ_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH0_TXBD_IDX (Offset 0x03A0) */ +#define BIT_SHIFT_ACH0_HOST_IDX 0 +#define BIT_MASK_ACH0_HOST_IDX 0xfff +#define BIT_ACH0_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH0_HOST_IDX) << BIT_SHIFT_ACH0_HOST_IDX) +#define BITS_ACH0_HOST_IDX (BIT_MASK_ACH0_HOST_IDX << BIT_SHIFT_ACH0_HOST_IDX) +#define BIT_CLEAR_ACH0_HOST_IDX(x) ((x) & (~BITS_ACH0_HOST_IDX)) +#define BIT_GET_ACH0_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH0_HOST_IDX) & BIT_MASK_ACH0_HOST_IDX) +#define BIT_SET_ACH0_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH0_HOST_IDX(x) | BIT_ACH0_HOST_IDX(v)) -/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#endif -#define BIT_CPUMGQ_FW_NUM BIT(8) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CPUMGQ_HEAD_PG 0 -#define BIT_MASK_CPUMGQ_HEAD_PG 0xff -#define BIT_CPUMGQ_HEAD_PG(x) (((x) & BIT_MASK_CPUMGQ_HEAD_PG) << BIT_SHIFT_CPUMGQ_HEAD_PG) -#define BIT_GET_CPUMGQ_HEAD_PG(x) (((x) >> BIT_SHIFT_CPUMGQ_HEAD_PG) & BIT_MASK_CPUMGQ_HEAD_PG) +/* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */ +#define BIT_SHIFT_VIQ_HW_IDX 16 +#define BIT_MASK_VIQ_HW_IDX 0xfff +#define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX) +#define BITS_VIQ_HW_IDX (BIT_MASK_VIQ_HW_IDX << BIT_SHIFT_VIQ_HW_IDX) +#define BIT_CLEAR_VIQ_HW_IDX(x) ((x) & (~BITS_VIQ_HW_IDX)) +#define BIT_GET_VIQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX) +#define BIT_SET_VIQ_HW_IDX(x, v) (BIT_CLEAR_VIQ_HW_IDX(x) | BIT_VIQ_HW_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ACH1_TXBD_IDX (Offset 0x03A4) */ +#define BIT_SHIFT_ACH1_HW_IDX 16 +#define BIT_MASK_ACH1_HW_IDX 0xfff +#define BIT_ACH1_HW_IDX(x) \ + (((x) & BIT_MASK_ACH1_HW_IDX) << BIT_SHIFT_ACH1_HW_IDX) +#define BITS_ACH1_HW_IDX (BIT_MASK_ACH1_HW_IDX << BIT_SHIFT_ACH1_HW_IDX) +#define BIT_CLEAR_ACH1_HW_IDX(x) ((x) & (~BITS_ACH1_HW_IDX)) +#define BIT_GET_ACH1_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH1_HW_IDX) & BIT_MASK_ACH1_HW_IDX) +#define BIT_SET_ACH1_HW_IDX(x, v) \ + (BIT_CLEAR_ACH1_HW_IDX(x) | BIT_ACH1_HW_IDX(v)) -/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FW_FREE_TAIL_V1 0 -#define BIT_MASK_FW_FREE_TAIL_V1 0xfff -#define BIT_FW_FREE_TAIL_V1(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1) -#define BIT_GET_FW_FREE_TAIL_V1(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1) +/* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */ +#define BIT_SHIFT_VIQ_HOST_IDX 0 +#define BIT_MASK_VIQ_HOST_IDX 0xfff +#define BIT_VIQ_HOST_IDX(x) \ + (((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX) +#define BITS_VIQ_HOST_IDX (BIT_MASK_VIQ_HOST_IDX << BIT_SHIFT_VIQ_HOST_IDX) +#define BIT_CLEAR_VIQ_HOST_IDX(x) ((x) & (~BITS_VIQ_HOST_IDX)) +#define BIT_GET_VIQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX) +#define BIT_SET_VIQ_HOST_IDX(x, v) \ + (BIT_CLEAR_VIQ_HOST_IDX(x) | BIT_VIQ_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ACH1_TXBD_IDX (Offset 0x03A4) */ +#define BIT_SHIFT_ACH1_HOST_IDX 0 +#define BIT_MASK_ACH1_HOST_IDX 0xfff +#define BIT_ACH1_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH1_HOST_IDX) << BIT_SHIFT_ACH1_HOST_IDX) +#define BITS_ACH1_HOST_IDX (BIT_MASK_ACH1_HOST_IDX << BIT_SHIFT_ACH1_HOST_IDX) +#define BIT_CLEAR_ACH1_HOST_IDX(x) ((x) & (~BITS_ACH1_HOST_IDX)) +#define BIT_GET_ACH1_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH1_HOST_IDX) & BIT_MASK_ACH1_HOST_IDX) +#define BIT_SET_ACH1_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH1_HOST_IDX(x) | BIT_ACH1_HOST_IDX(v)) -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#endif -#define BIT_RTS_LIMIT_IN_OFDM BIT(23) -#define BIT_EN_BCNQ_DL BIT(22) -#define BIT_EN_RD_RESP_NAV_BK BIT(21) -#define BIT_EN_WR_FREE_TAIL BIT(20) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_EN_QUEUE_RPT 8 -#define BIT_MASK_EN_QUEUE_RPT 0xff -#define BIT_EN_QUEUE_RPT(x) (((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT) -#define BIT_GET_EN_QUEUE_RPT(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT) +/* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */ -#define BIT_EN_RTY_BK BIT(7) -#define BIT_EN_USE_INI_RAT BIT(6) -#define BIT_EN_RTS_NAV_BK BIT(5) -#define BIT_DIS_SSN_CHECK BIT(4) -#define BIT_MACID_MATCH_RTS BIT(3) +#define BIT_SHIFT_BEQ_HW_IDX 16 +#define BIT_MASK_BEQ_HW_IDX 0xfff +#define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX) +#define BITS_BEQ_HW_IDX (BIT_MASK_BEQ_HW_IDX << BIT_SHIFT_BEQ_HW_IDX) +#define BIT_CLEAR_BEQ_HW_IDX(x) ((x) & (~BITS_BEQ_HW_IDX)) +#define BIT_GET_BEQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX) +#define BIT_SET_BEQ_HW_IDX(x, v) (BIT_CLEAR_BEQ_HW_IDX(x) | BIT_BEQ_HW_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ACH2_TXBD_IDX (Offset 0x03A8) */ +#define BIT_SHIFT_ACH2_HW_IDX 16 +#define BIT_MASK_ACH2_HW_IDX 0xfff +#define BIT_ACH2_HW_IDX(x) \ + (((x) & BIT_MASK_ACH2_HW_IDX) << BIT_SHIFT_ACH2_HW_IDX) +#define BITS_ACH2_HW_IDX (BIT_MASK_ACH2_HW_IDX << BIT_SHIFT_ACH2_HW_IDX) +#define BIT_CLEAR_ACH2_HW_IDX(x) ((x) & (~BITS_ACH2_HW_IDX)) +#define BIT_GET_ACH2_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH2_HW_IDX) & BIT_MASK_ACH2_HW_IDX) +#define BIT_SET_ACH2_HW_IDX(x, v) \ + (BIT_CLEAR_ACH2_HW_IDX(x) | BIT_ACH2_HW_IDX(v)) -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#endif -#define BIT_EN_BCN_TRXRPT_V1 BIT(2) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */ +#define BIT_SHIFT_BEQ_HOST_IDX 0 +#define BIT_MASK_BEQ_HOST_IDX 0xfff +#define BIT_BEQ_HOST_IDX(x) \ + (((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX) +#define BITS_BEQ_HOST_IDX (BIT_MASK_BEQ_HOST_IDX << BIT_SHIFT_BEQ_HOST_IDX) +#define BIT_CLEAR_BEQ_HOST_IDX(x) ((x) & (~BITS_BEQ_HOST_IDX)) +#define BIT_GET_BEQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX) +#define BIT_SET_BEQ_HOST_IDX(x, v) \ + (BIT_CLEAR_BEQ_HOST_IDX(x) | BIT_BEQ_HOST_IDX(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +/* 2 REG_ACH2_TXBD_IDX (Offset 0x03A8) */ -#define BIT_R_EN_FTMRPT BIT(1) +#define BIT_SHIFT_ACH2_HOST_IDX 0 +#define BIT_MASK_ACH2_HOST_IDX 0xfff +#define BIT_ACH2_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH2_HOST_IDX) << BIT_SHIFT_ACH2_HOST_IDX) +#define BITS_ACH2_HOST_IDX (BIT_MASK_ACH2_HOST_IDX << BIT_SHIFT_ACH2_HOST_IDX) +#define BIT_CLEAR_ACH2_HOST_IDX(x) ((x) & (~BITS_ACH2_HOST_IDX)) +#define BIT_GET_ACH2_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH2_HOST_IDX) & BIT_MASK_ACH2_HOST_IDX) +#define BIT_SET_ACH2_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH2_HOST_IDX(x) | BIT_ACH2_HOST_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */ +#define BIT_SHIFT_BKQ_HW_IDX 16 +#define BIT_MASK_BKQ_HW_IDX 0xfff +#define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX) +#define BITS_BKQ_HW_IDX (BIT_MASK_BKQ_HW_IDX << BIT_SHIFT_BKQ_HW_IDX) +#define BIT_CLEAR_BKQ_HW_IDX(x) ((x) & (~BITS_BKQ_HW_IDX)) +#define BIT_GET_BKQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX) +#define BIT_SET_BKQ_HW_IDX(x, v) (BIT_CLEAR_BKQ_HW_IDX(x) | BIT_BKQ_HW_IDX(v)) -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#endif -#define BIT_EN_FTMACKRPT BIT(1) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ACH3_TXBD_IDX (Offset 0x03AC) */ +#define BIT_SHIFT_ACH3_HW_IDX 16 +#define BIT_MASK_ACH3_HW_IDX 0xfff +#define BIT_ACH3_HW_IDX(x) \ + (((x) & BIT_MASK_ACH3_HW_IDX) << BIT_SHIFT_ACH3_HW_IDX) +#define BITS_ACH3_HW_IDX (BIT_MASK_ACH3_HW_IDX << BIT_SHIFT_ACH3_HW_IDX) +#define BIT_CLEAR_ACH3_HW_IDX(x) ((x) & (~BITS_ACH3_HW_IDX)) +#define BIT_GET_ACH3_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH3_HW_IDX) & BIT_MASK_ACH3_HW_IDX) +#define BIT_SET_ACH3_HW_IDX(x, v) \ + (BIT_CLEAR_ACH3_HW_IDX(x) | BIT_ACH3_HW_IDX(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +/* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */ -#define BIT_R_BMC_NAV_PROTECT BIT(0) +#define BIT_SHIFT_BKQ_HOST_IDX 0 +#define BIT_MASK_BKQ_HOST_IDX 0xfff +#define BIT_BKQ_HOST_IDX(x) \ + (((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX) +#define BITS_BKQ_HOST_IDX (BIT_MASK_BKQ_HOST_IDX << BIT_SHIFT_BKQ_HOST_IDX) +#define BIT_CLEAR_BKQ_HOST_IDX(x) ((x) & (~BITS_BKQ_HOST_IDX)) +#define BIT_GET_BKQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX) +#define BIT_SET_BKQ_HOST_IDX(x, v) \ + (BIT_CLEAR_BKQ_HOST_IDX(x) | BIT_BKQ_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_ACH3_TXBD_IDX (Offset 0x03AC) */ +#define BIT_SHIFT_ACH3_HOST_IDX 0 +#define BIT_MASK_ACH3_HOST_IDX 0xfff +#define BIT_ACH3_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH3_HOST_IDX) << BIT_SHIFT_ACH3_HOST_IDX) +#define BITS_ACH3_HOST_IDX (BIT_MASK_ACH3_HOST_IDX << BIT_SHIFT_ACH3_HOST_IDX) +#define BIT_CLEAR_ACH3_HOST_IDX(x) ((x) & (~BITS_ACH3_HOST_IDX)) +#define BIT_GET_ACH3_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH3_HOST_IDX) & BIT_MASK_ACH3_HOST_IDX) +#define BIT_SET_ACH3_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH3_HOST_IDX(x) | BIT_ACH3_HOST_IDX(v)) -/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#endif -#define BIT_EN_FTMRPT BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */ +#define BIT_SHIFT_MGQ_HW_IDX 16 +#define BIT_MASK_MGQ_HW_IDX 0xfff +#define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX) +#define BITS_MGQ_HW_IDX (BIT_MASK_MGQ_HW_IDX << BIT_SHIFT_MGQ_HW_IDX) +#define BIT_CLEAR_MGQ_HW_IDX(x) ((x) & (~BITS_MGQ_HW_IDX)) +#define BIT_GET_MGQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX) +#define BIT_SET_MGQ_HW_IDX(x, v) (BIT_CLEAR_MGQ_HW_IDX(x) | BIT_MGQ_HW_IDX(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ +/* 2 REG_P0MGQ_TXBD_IDX (Offset 0x03B0) */ -#define BIT_HWSEQ_CPUM_EN BIT(7) -#define BIT_HWSEQ_BCN_EN BIT(6) -#define BIT_HWSEQ_HI_EN BIT(5) -#define BIT_HWSEQ_MGT_EN BIT(4) -#define BIT_HWSEQ_BK_EN BIT(3) -#define BIT_HWSEQ_BE_EN BIT(2) +#define BIT_SHIFT_P0MGQ_HW_IDX 16 +#define BIT_MASK_P0MGQ_HW_IDX 0xfff +#define BIT_P0MGQ_HW_IDX(x) \ + (((x) & BIT_MASK_P0MGQ_HW_IDX) << BIT_SHIFT_P0MGQ_HW_IDX) +#define BITS_P0MGQ_HW_IDX (BIT_MASK_P0MGQ_HW_IDX << BIT_SHIFT_P0MGQ_HW_IDX) +#define BIT_CLEAR_P0MGQ_HW_IDX(x) ((x) & (~BITS_P0MGQ_HW_IDX)) +#define BIT_GET_P0MGQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0MGQ_HW_IDX) & BIT_MASK_P0MGQ_HW_IDX) +#define BIT_SET_P0MGQ_HW_IDX(x, v) \ + (BIT_CLEAR_P0MGQ_HW_IDX(x) | BIT_P0MGQ_HW_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */ - -/* 2 REG_DATAFB_SEL (Offset 0x0423) */ - -#define BIT__R_EN_RTY_BK_COD BIT(2) +#define BIT_SHIFT_MGQ_HOST_IDX 0 +#define BIT_MASK_MGQ_HOST_IDX 0xfff +#define BIT_MGQ_HOST_IDX(x) \ + (((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX) +#define BITS_MGQ_HOST_IDX (BIT_MASK_MGQ_HOST_IDX << BIT_SHIFT_MGQ_HOST_IDX) +#define BIT_CLEAR_MGQ_HOST_IDX(x) ((x) & (~BITS_MGQ_HOST_IDX)) +#define BIT_GET_MGQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX) +#define BIT_SET_MGQ_HOST_IDX(x, v) \ + (BIT_CLEAR_MGQ_HOST_IDX(x) | BIT_MGQ_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ +/* 2 REG_P0MGQ_TXBD_IDX (Offset 0x03B0) */ -#define BIT_HWSEQ_VI_EN BIT(1) -#define BIT_HWSEQ_VO_EN BIT(0) +#define BIT_SHIFT_P0MGQ_HOST_IDX 0 +#define BIT_MASK_P0MGQ_HOST_IDX 0xfff +#define BIT_P0MGQ_HOST_IDX(x) \ + (((x) & BIT_MASK_P0MGQ_HOST_IDX) << BIT_SHIFT_P0MGQ_HOST_IDX) +#define BITS_P0MGQ_HOST_IDX \ + (BIT_MASK_P0MGQ_HOST_IDX << BIT_SHIFT_P0MGQ_HOST_IDX) +#define BIT_CLEAR_P0MGQ_HOST_IDX(x) ((x) & (~BITS_P0MGQ_HOST_IDX)) +#define BIT_GET_P0MGQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0MGQ_HOST_IDX) & BIT_MASK_P0MGQ_HOST_IDX) +#define BIT_SET_P0MGQ_HOST_IDX(x, v) \ + (BIT_CLEAR_P0MGQ_HOST_IDX(x) | BIT_P0MGQ_HOST_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */ +#define BIT_SHIFT_RXQ_HW_IDX 16 +#define BIT_MASK_RXQ_HW_IDX 0xfff +#define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX) +#define BITS_RXQ_HW_IDX (BIT_MASK_RXQ_HW_IDX << BIT_SHIFT_RXQ_HW_IDX) +#define BIT_CLEAR_RXQ_HW_IDX(x) ((x) & (~BITS_RXQ_HW_IDX)) +#define BIT_GET_RXQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX) +#define BIT_SET_RXQ_HW_IDX(x, v) (BIT_CLEAR_RXQ_HW_IDX(x) | BIT_RXQ_HW_IDX(v)) -/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT__R_DATA_FALLBACK_SEL 0 -#define BIT_MASK__R_DATA_FALLBACK_SEL 0x3 -#define BIT__R_DATA_FALLBACK_SEL(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL) << BIT_SHIFT__R_DATA_FALLBACK_SEL) -#define BIT_GET__R_DATA_FALLBACK_SEL(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) & BIT_MASK__R_DATA_FALLBACK_SEL) +/* 2 REG_P0RXQ_RXBD_IDX (Offset 0x03B4) */ +#define BIT_SHIFT_P0RXQ_HW_IDX 16 +#define BIT_MASK_P0RXQ_HW_IDX 0xfff +#define BIT_P0RXQ_HW_IDX(x) \ + (((x) & BIT_MASK_P0RXQ_HW_IDX) << BIT_SHIFT_P0RXQ_HW_IDX) +#define BITS_P0RXQ_HW_IDX (BIT_MASK_P0RXQ_HW_IDX << BIT_SHIFT_P0RXQ_HW_IDX) +#define BIT_CLEAR_P0RXQ_HW_IDX(x) ((x) & (~BITS_P0RXQ_HW_IDX)) +#define BIT_GET_P0RXQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0RXQ_HW_IDX) & BIT_MASK_P0RXQ_HW_IDX) +#define BIT_SET_P0RXQ_HW_IDX(x, v) \ + (BIT_CLEAR_P0RXQ_HW_IDX(x) | BIT_P0RXQ_HW_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */ +#define BIT_SHIFT_RXQ_HOST_IDX 0 +#define BIT_MASK_RXQ_HOST_IDX 0xfff +#define BIT_RXQ_HOST_IDX(x) \ + (((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX) +#define BITS_RXQ_HOST_IDX (BIT_MASK_RXQ_HOST_IDX << BIT_SHIFT_RXQ_HOST_IDX) +#define BIT_CLEAR_RXQ_HOST_IDX(x) ((x) & (~BITS_RXQ_HOST_IDX)) +#define BIT_GET_RXQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX) +#define BIT_SET_RXQ_HOST_IDX(x, v) \ + (BIT_CLEAR_RXQ_HOST_IDX(x) | BIT_RXQ_HOST_IDX(v)) -/* 2 REG_BCNQ_BDNY (Offset 0x0424) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCNQ_PGBNDY 0 -#define BIT_MASK_BCNQ_PGBNDY 0xff -#define BIT_BCNQ_PGBNDY(x) (((x) & BIT_MASK_BCNQ_PGBNDY) << BIT_SHIFT_BCNQ_PGBNDY) -#define BIT_GET_BCNQ_PGBNDY(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY) & BIT_MASK_BCNQ_PGBNDY) +/* 2 REG_P0RXQ_RXBD_IDX (Offset 0x03B4) */ +#define BIT_SHIFT_P0RXQ_HOST_IDX 0 +#define BIT_MASK_P0RXQ_HOST_IDX 0xfff +#define BIT_P0RXQ_HOST_IDX(x) \ + (((x) & BIT_MASK_P0RXQ_HOST_IDX) << BIT_SHIFT_P0RXQ_HOST_IDX) +#define BITS_P0RXQ_HOST_IDX \ + (BIT_MASK_P0RXQ_HOST_IDX << BIT_SHIFT_P0RXQ_HOST_IDX) +#define BIT_CLEAR_P0RXQ_HOST_IDX(x) ((x) & (~BITS_P0RXQ_HOST_IDX)) +#define BIT_GET_P0RXQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0RXQ_HOST_IDX) & BIT_MASK_P0RXQ_HOST_IDX) +#define BIT_SET_P0RXQ_HOST_IDX(x, v) \ + (BIT_CLEAR_P0RXQ_HOST_IDX(x) | BIT_P0RXQ_HOST_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */ +#define BIT_SHIFT_HI0Q_HW_IDX 16 +#define BIT_MASK_HI0Q_HW_IDX 0xfff +#define BIT_HI0Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX) +#define BITS_HI0Q_HW_IDX (BIT_MASK_HI0Q_HW_IDX << BIT_SHIFT_HI0Q_HW_IDX) +#define BIT_CLEAR_HI0Q_HW_IDX(x) ((x) & (~BITS_HI0Q_HW_IDX)) +#define BIT_GET_HI0Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX) +#define BIT_SET_HI0Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI0Q_HW_IDX(x) | BIT_HI0Q_HW_IDX(v)) -/* 2 REG_BCNQ_BDNY_V1 (Offset 0x0424) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCNQ_PGBNDY_V1 0 -#define BIT_MASK_BCNQ_PGBNDY_V1 0xfff -#define BIT_BCNQ_PGBNDY_V1(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1) -#define BIT_GET_BCNQ_PGBNDY_V1(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1) +/* 2 REG_P0HI0Q_TXBD_IDX (Offset 0x03B8) */ +#define BIT_SHIFT_P0HI0Q_HW_IDX 16 +#define BIT_MASK_P0HI0Q_HW_IDX 0xfff +#define BIT_P0HI0Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI0Q_HW_IDX) << BIT_SHIFT_P0HI0Q_HW_IDX) +#define BITS_P0HI0Q_HW_IDX (BIT_MASK_P0HI0Q_HW_IDX << BIT_SHIFT_P0HI0Q_HW_IDX) +#define BIT_CLEAR_P0HI0Q_HW_IDX(x) ((x) & (~BITS_P0HI0Q_HW_IDX)) +#define BIT_GET_P0HI0Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_HW_IDX) & BIT_MASK_P0HI0Q_HW_IDX) +#define BIT_SET_P0HI0Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI0Q_HW_IDX(x) | BIT_P0HI0Q_HW_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */ +#define BIT_SHIFT_HI0Q_HOST_IDX 0 +#define BIT_MASK_HI0Q_HOST_IDX 0xfff +#define BIT_HI0Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX) +#define BITS_HI0Q_HOST_IDX (BIT_MASK_HI0Q_HOST_IDX << BIT_SHIFT_HI0Q_HOST_IDX) +#define BIT_CLEAR_HI0Q_HOST_IDX(x) ((x) & (~BITS_HI0Q_HOST_IDX)) +#define BIT_GET_HI0Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX) +#define BIT_SET_HI0Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI0Q_HOST_IDX(x) | BIT_HI0Q_HOST_IDX(v)) -/* 2 REG_MGQ_BDNY (Offset 0x0425) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MGQ_PGBNDY 0 -#define BIT_MASK_MGQ_PGBNDY 0xff -#define BIT_MGQ_PGBNDY(x) (((x) & BIT_MASK_MGQ_PGBNDY) << BIT_SHIFT_MGQ_PGBNDY) -#define BIT_GET_MGQ_PGBNDY(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY) & BIT_MASK_MGQ_PGBNDY) +/* 2 REG_P0HI0Q_TXBD_IDX (Offset 0x03B8) */ +#define BIT_SHIFT_P0HI0Q_HOST_IDX 0 +#define BIT_MASK_P0HI0Q_HOST_IDX 0xfff +#define BIT_P0HI0Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI0Q_HOST_IDX) << BIT_SHIFT_P0HI0Q_HOST_IDX) +#define BITS_P0HI0Q_HOST_IDX \ + (BIT_MASK_P0HI0Q_HOST_IDX << BIT_SHIFT_P0HI0Q_HOST_IDX) +#define BIT_CLEAR_P0HI0Q_HOST_IDX(x) ((x) & (~BITS_P0HI0Q_HOST_IDX)) +#define BIT_GET_P0HI0Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_HOST_IDX) & BIT_MASK_P0HI0Q_HOST_IDX) +#define BIT_SET_P0HI0Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI0Q_HOST_IDX(x) | BIT_P0HI0Q_HOST_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +/* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */ -#define BIT_BT_INT_CPU BIT(7) -#define BIT_BT_INT_PTA BIT(6) +#define BIT_SHIFT_HI1Q_HW_IDX 16 +#define BIT_MASK_HI1Q_HW_IDX 0xfff +#define BIT_HI1Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX) +#define BITS_HI1Q_HW_IDX (BIT_MASK_HI1Q_HW_IDX << BIT_SHIFT_HI1Q_HW_IDX) +#define BIT_CLEAR_HI1Q_HW_IDX(x) ((x) & (~BITS_HI1Q_HW_IDX)) +#define BIT_GET_HI1Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX) +#define BIT_SET_HI1Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI1Q_HW_IDX(x) | BIT_HI1Q_HW_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +/* 2 REG_P0HI1Q_TXBD_IDX (Offset 0x03BC) */ -#define BIT_SPERPT_ENTRY BIT(5) -#define BIT_RTYCNT_FB BIT(4) +#define BIT_SHIFT_P0HI1Q_HW_IDX 16 +#define BIT_MASK_P0HI1Q_HW_IDX 0xfff +#define BIT_P0HI1Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI1Q_HW_IDX) << BIT_SHIFT_P0HI1Q_HW_IDX) +#define BITS_P0HI1Q_HW_IDX (BIT_MASK_P0HI1Q_HW_IDX << BIT_SHIFT_P0HI1Q_HW_IDX) +#define BIT_CLEAR_P0HI1Q_HW_IDX(x) ((x) & (~BITS_P0HI1Q_HW_IDX)) +#define BIT_GET_P0HI1Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_HW_IDX) & BIT_MASK_P0HI1Q_HW_IDX) +#define BIT_SET_P0HI1Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI1Q_HW_IDX(x) | BIT_P0HI1Q_HW_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */ +#define BIT_SHIFT_HI1Q_HOST_IDX 0 +#define BIT_MASK_HI1Q_HOST_IDX 0xfff +#define BIT_HI1Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX) +#define BITS_HI1Q_HOST_IDX (BIT_MASK_HI1Q_HOST_IDX << BIT_SHIFT_HI1Q_HOST_IDX) +#define BIT_CLEAR_HI1Q_HOST_IDX(x) ((x) & (~BITS_HI1Q_HOST_IDX)) +#define BIT_GET_HI1Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX) +#define BIT_SET_HI1Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI1Q_HOST_IDX(x) | BIT_HI1Q_HOST_IDX(v)) -/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +#endif -#define BIT_EN_CTRL_RTYBIT BIT(4) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_P0HI1Q_TXBD_IDX (Offset 0x03BC) */ +#define BIT_SHIFT_P0HI1Q_HOST_IDX 0 +#define BIT_MASK_P0HI1Q_HOST_IDX 0xfff +#define BIT_P0HI1Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI1Q_HOST_IDX) << BIT_SHIFT_P0HI1Q_HOST_IDX) +#define BITS_P0HI1Q_HOST_IDX \ + (BIT_MASK_P0HI1Q_HOST_IDX << BIT_SHIFT_P0HI1Q_HOST_IDX) +#define BIT_CLEAR_P0HI1Q_HOST_IDX(x) ((x) & (~BITS_P0HI1Q_HOST_IDX)) +#define BIT_GET_P0HI1Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_HOST_IDX) & BIT_MASK_P0HI1Q_HOST_IDX) +#define BIT_SET_P0HI1Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI1Q_HOST_IDX(x) | BIT_P0HI1Q_HOST_IDX(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +/* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */ -#define BIT_LIFETIME_BK_EN BIT(3) -#define BIT_LIFETIME_BE_EN BIT(2) -#define BIT_LIFETIME_VI_EN BIT(1) -#define BIT_LIFETIME_VO_EN BIT(0) +#define BIT_SHIFT_HI2Q_HW_IDX 16 +#define BIT_MASK_HI2Q_HW_IDX 0xfff +#define BIT_HI2Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX) +#define BITS_HI2Q_HW_IDX (BIT_MASK_HI2Q_HW_IDX << BIT_SHIFT_HI2Q_HW_IDX) +#define BIT_CLEAR_HI2Q_HW_IDX(x) ((x) & (~BITS_HI2Q_HW_IDX)) +#define BIT_GET_HI2Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX) +#define BIT_SET_HI2Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI2Q_HW_IDX(x) | BIT_HI2Q_HW_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P0HI2Q_TXBD_IDX (Offset 0x03C0) */ +#define BIT_SHIFT_P0HI2Q_HW_IDX 16 +#define BIT_MASK_P0HI2Q_HW_IDX 0xfff +#define BIT_P0HI2Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI2Q_HW_IDX) << BIT_SHIFT_P0HI2Q_HW_IDX) +#define BITS_P0HI2Q_HW_IDX (BIT_MASK_P0HI2Q_HW_IDX << BIT_SHIFT_P0HI2Q_HW_IDX) +#define BIT_CLEAR_P0HI2Q_HW_IDX(x) ((x) & (~BITS_P0HI2Q_HW_IDX)) +#define BIT_GET_P0HI2Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_HW_IDX) & BIT_MASK_P0HI2Q_HW_IDX) +#define BIT_SET_P0HI2Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI2Q_HW_IDX(x) | BIT_P0HI2Q_HW_IDX(v)) -/* 2 REG_FW_FREE_TAIL (Offset 0x0427) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FW_FREE_TAIL 0 -#define BIT_MASK_FW_FREE_TAIL 0xff -#define BIT_FW_FREE_TAIL(x) (((x) & BIT_MASK_FW_FREE_TAIL) << BIT_SHIFT_FW_FREE_TAIL) -#define BIT_GET_FW_FREE_TAIL(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL) & BIT_MASK_FW_FREE_TAIL) +/* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */ +#define BIT_SHIFT_HI2Q_HOST_IDX 0 +#define BIT_MASK_HI2Q_HOST_IDX 0xfff +#define BIT_HI2Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX) +#define BITS_HI2Q_HOST_IDX (BIT_MASK_HI2Q_HOST_IDX << BIT_SHIFT_HI2Q_HOST_IDX) +#define BIT_CLEAR_HI2Q_HOST_IDX(x) ((x) & (~BITS_HI2Q_HOST_IDX)) +#define BIT_GET_HI2Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX) +#define BIT_SET_HI2Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI2Q_HOST_IDX(x) | BIT_HI2Q_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P0HI2Q_TXBD_IDX (Offset 0x03C0) */ +#define BIT_SHIFT_P0HI2Q_HOST_IDX 0 +#define BIT_MASK_P0HI2Q_HOST_IDX 0xfff +#define BIT_P0HI2Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI2Q_HOST_IDX) << BIT_SHIFT_P0HI2Q_HOST_IDX) +#define BITS_P0HI2Q_HOST_IDX \ + (BIT_MASK_P0HI2Q_HOST_IDX << BIT_SHIFT_P0HI2Q_HOST_IDX) +#define BIT_CLEAR_P0HI2Q_HOST_IDX(x) ((x) & (~BITS_P0HI2Q_HOST_IDX)) +#define BIT_GET_P0HI2Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_HOST_IDX) & BIT_MASK_P0HI2Q_HOST_IDX) +#define BIT_SET_P0HI2Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI2Q_HOST_IDX(x) | BIT_P0HI2Q_HOST_IDX(v)) -/* 2 REG_SPEC_SIFS (Offset 0x0428) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8 -#define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff -#define BIT_SPEC_SIFS_OFDM_PTCL(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) -#define BIT_GET_SPEC_SIFS_OFDM_PTCL(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) +/* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */ +#define BIT_SHIFT_HI3Q_HW_IDX 16 +#define BIT_MASK_HI3Q_HW_IDX 0xfff +#define BIT_HI3Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX) +#define BITS_HI3Q_HW_IDX (BIT_MASK_HI3Q_HW_IDX << BIT_SHIFT_HI3Q_HW_IDX) +#define BIT_CLEAR_HI3Q_HW_IDX(x) ((x) & (~BITS_HI3Q_HW_IDX)) +#define BIT_GET_HI3Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX) +#define BIT_SET_HI3Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI3Q_HW_IDX(x) | BIT_HI3Q_HW_IDX(v)) -#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0 -#define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff -#define BIT_SPEC_SIFS_CCK_PTCL(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL) -#define BIT_GET_SPEC_SIFS_CCK_PTCL(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_RETRY_LIMIT (Offset 0x042A) */ +/* 2 REG_P0HI3Q_TXBD_IDX (Offset 0x03C4) */ +#define BIT_SHIFT_P0HI3Q_HW_IDX 16 +#define BIT_MASK_P0HI3Q_HW_IDX 0xfff +#define BIT_P0HI3Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI3Q_HW_IDX) << BIT_SHIFT_P0HI3Q_HW_IDX) +#define BITS_P0HI3Q_HW_IDX (BIT_MASK_P0HI3Q_HW_IDX << BIT_SHIFT_P0HI3Q_HW_IDX) +#define BIT_CLEAR_P0HI3Q_HW_IDX(x) ((x) & (~BITS_P0HI3Q_HW_IDX)) +#define BIT_GET_P0HI3Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_HW_IDX) & BIT_MASK_P0HI3Q_HW_IDX) +#define BIT_SET_P0HI3Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI3Q_HW_IDX(x) | BIT_P0HI3Q_HW_IDX(v)) -#define BIT_SHIFT_SRL 8 -#define BIT_MASK_SRL 0x3f -#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL) -#define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LRL 0 -#define BIT_MASK_LRL 0x3f -#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL) -#define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL) +/* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */ +#define BIT_SHIFT_HI3Q_HOST_IDX 0 +#define BIT_MASK_HI3Q_HOST_IDX 0xfff +#define BIT_HI3Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX) +#define BITS_HI3Q_HOST_IDX (BIT_MASK_HI3Q_HOST_IDX << BIT_SHIFT_HI3Q_HOST_IDX) +#define BIT_CLEAR_HI3Q_HOST_IDX(x) ((x) & (~BITS_HI3Q_HOST_IDX)) +#define BIT_GET_HI3Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX) +#define BIT_SET_HI3Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI3Q_HOST_IDX(x) | BIT_HI3Q_HOST_IDX(v)) -/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#endif -#define BIT_R_ENABLE_NDPA BIT(31) -#define BIT_USE_NDPA_PARAMETER BIT(30) -#define BIT_R_PROP_TXBF BIT(29) -#define BIT_R_EN_NDPA_INT BIT(28) -#define BIT_R_TXBF1_80M BIT(27) -#define BIT_R_TXBF1_40M BIT(26) -#define BIT_R_TXBF1_20M BIT(25) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_R_TXBF1_AID 16 -#define BIT_MASK_R_TXBF1_AID 0x1ff -#define BIT_R_TXBF1_AID(x) (((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID) -#define BIT_GET_R_TXBF1_AID(x) (((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID) +/* 2 REG_P0HI3Q_TXBD_IDX (Offset 0x03C4) */ +#define BIT_SHIFT_P0HI3Q_HOST_IDX 0 +#define BIT_MASK_P0HI3Q_HOST_IDX 0xfff +#define BIT_P0HI3Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI3Q_HOST_IDX) << BIT_SHIFT_P0HI3Q_HOST_IDX) +#define BITS_P0HI3Q_HOST_IDX \ + (BIT_MASK_P0HI3Q_HOST_IDX << BIT_SHIFT_P0HI3Q_HOST_IDX) +#define BIT_CLEAR_P0HI3Q_HOST_IDX(x) ((x) & (~BITS_P0HI3Q_HOST_IDX)) +#define BIT_GET_P0HI3Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_HOST_IDX) & BIT_MASK_P0HI3Q_HOST_IDX) +#define BIT_SET_P0HI3Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI3Q_HOST_IDX(x) | BIT_P0HI3Q_HOST_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */ +#define BIT_SHIFT_HI4Q_HW_IDX 16 +#define BIT_MASK_HI4Q_HW_IDX 0xfff +#define BIT_HI4Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX) +#define BITS_HI4Q_HW_IDX (BIT_MASK_HI4Q_HW_IDX << BIT_SHIFT_HI4Q_HW_IDX) +#define BIT_CLEAR_HI4Q_HW_IDX(x) ((x) & (~BITS_HI4Q_HW_IDX)) +#define BIT_GET_HI4Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX) +#define BIT_SET_HI4Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI4Q_HW_IDX(x) | BIT_HI4Q_HW_IDX(v)) -/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#endif -#define BIT_DIS_NDP_BFEN BIT(15) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_P0HI4Q_TXBD_IDX (Offset 0x03C8) */ +#define BIT_SHIFT_P0HI4Q_HW_IDX 16 +#define BIT_MASK_P0HI4Q_HW_IDX 0xfff +#define BIT_P0HI4Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI4Q_HW_IDX) << BIT_SHIFT_P0HI4Q_HW_IDX) +#define BITS_P0HI4Q_HW_IDX (BIT_MASK_P0HI4Q_HW_IDX << BIT_SHIFT_P0HI4Q_HW_IDX) +#define BIT_CLEAR_P0HI4Q_HW_IDX(x) ((x) & (~BITS_P0HI4Q_HW_IDX)) +#define BIT_GET_P0HI4Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_HW_IDX) & BIT_MASK_P0HI4Q_HW_IDX) +#define BIT_SET_P0HI4Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI4Q_HW_IDX(x) | BIT_P0HI4Q_HW_IDX(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +/* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */ -#define BIT_R_TXBCN_NOBLOCK_NDP BIT(14) +#define BIT_SHIFT_HI4Q_HOST_IDX 0 +#define BIT_MASK_HI4Q_HOST_IDX 0xfff +#define BIT_HI4Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX) +#define BITS_HI4Q_HOST_IDX (BIT_MASK_HI4Q_HOST_IDX << BIT_SHIFT_HI4Q_HOST_IDX) +#define BIT_CLEAR_HI4Q_HOST_IDX(x) ((x) & (~BITS_HI4Q_HOST_IDX)) +#define BIT_GET_HI4Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX) +#define BIT_SET_HI4Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI4Q_HOST_IDX(x) | BIT_HI4Q_HOST_IDX(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P0HI4Q_TXBD_IDX (Offset 0x03C8) */ +#define BIT_SHIFT_P0HI4Q_HOST_IDX 0 +#define BIT_MASK_P0HI4Q_HOST_IDX 0xfff +#define BIT_P0HI4Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI4Q_HOST_IDX) << BIT_SHIFT_P0HI4Q_HOST_IDX) +#define BITS_P0HI4Q_HOST_IDX \ + (BIT_MASK_P0HI4Q_HOST_IDX << BIT_SHIFT_P0HI4Q_HOST_IDX) +#define BIT_CLEAR_P0HI4Q_HOST_IDX(x) ((x) & (~BITS_P0HI4Q_HOST_IDX)) +#define BIT_GET_P0HI4Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_HOST_IDX) & BIT_MASK_P0HI4Q_HOST_IDX) +#define BIT_SET_P0HI4Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI4Q_HOST_IDX(x) | BIT_P0HI4Q_HOST_IDX(v)) -/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#endif -#define BIT_R_TXBF0_80M BIT(11) -#define BIT_R_TXBF0_40M BIT(10) -#define BIT_R_TXBF0_20M BIT(9) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_TXBF0_AID 0 -#define BIT_MASK_R_TXBF0_AID 0x1ff -#define BIT_R_TXBF0_AID(x) (((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID) -#define BIT_GET_R_TXBF0_AID(x) (((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID) +/* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */ +#define BIT_SHIFT_HI5Q_HW_IDX 16 +#define BIT_MASK_HI5Q_HW_IDX 0xfff +#define BIT_HI5Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX) +#define BITS_HI5Q_HW_IDX (BIT_MASK_HI5Q_HW_IDX << BIT_SHIFT_HI5Q_HW_IDX) +#define BIT_CLEAR_HI5Q_HW_IDX(x) ((x) & (~BITS_HI5Q_HW_IDX)) +#define BIT_GET_HI5Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX) +#define BIT_SET_HI5Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI5Q_HW_IDX(x) | BIT_HI5Q_HW_IDX(v)) -/* 2 REG_DARFRC (Offset 0x0430) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC8 0x1f -#define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8) -#define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8) +/* 2 REG_P0HI5Q_TXBD_IDX (Offset 0x03CC) */ +#define BIT_SHIFT_P0HI5Q_HW_IDX 16 +#define BIT_MASK_P0HI5Q_HW_IDX 0xfff +#define BIT_P0HI5Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI5Q_HW_IDX) << BIT_SHIFT_P0HI5Q_HW_IDX) +#define BITS_P0HI5Q_HW_IDX (BIT_MASK_P0HI5Q_HW_IDX << BIT_SHIFT_P0HI5Q_HW_IDX) +#define BIT_CLEAR_P0HI5Q_HW_IDX(x) ((x) & (~BITS_P0HI5Q_HW_IDX)) +#define BIT_GET_P0HI5Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_HW_IDX) & BIT_MASK_P0HI5Q_HW_IDX) +#define BIT_SET_P0HI5Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI5Q_HW_IDX(x) | BIT_P0HI5Q_HW_IDX(v)) -#define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC7 0x1f -#define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7) -#define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC6 0x1f -#define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6) -#define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6) +/* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */ +#define BIT_SHIFT_HI5Q_HOST_IDX 0 +#define BIT_MASK_HI5Q_HOST_IDX 0xfff +#define BIT_HI5Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX) +#define BITS_HI5Q_HOST_IDX (BIT_MASK_HI5Q_HOST_IDX << BIT_SHIFT_HI5Q_HOST_IDX) +#define BIT_CLEAR_HI5Q_HOST_IDX(x) ((x) & (~BITS_HI5Q_HOST_IDX)) +#define BIT_GET_HI5Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX) +#define BIT_SET_HI5Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI5Q_HOST_IDX(x) | BIT_HI5Q_HOST_IDX(v)) -#define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC5 0x1f -#define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5) -#define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_DARF_RC4 24 -#define BIT_MASK_DARF_RC4 0x1f -#define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4) -#define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4) +/* 2 REG_P0HI5Q_TXBD_IDX (Offset 0x03CC) */ +#define BIT_SHIFT_P0HI5Q_HOST_IDX 0 +#define BIT_MASK_P0HI5Q_HOST_IDX 0xfff +#define BIT_P0HI5Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI5Q_HOST_IDX) << BIT_SHIFT_P0HI5Q_HOST_IDX) +#define BITS_P0HI5Q_HOST_IDX \ + (BIT_MASK_P0HI5Q_HOST_IDX << BIT_SHIFT_P0HI5Q_HOST_IDX) +#define BIT_CLEAR_P0HI5Q_HOST_IDX(x) ((x) & (~BITS_P0HI5Q_HOST_IDX)) +#define BIT_GET_P0HI5Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_HOST_IDX) & BIT_MASK_P0HI5Q_HOST_IDX) +#define BIT_SET_P0HI5Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI5Q_HOST_IDX(x) | BIT_P0HI5Q_HOST_IDX(v)) -#define BIT_SHIFT_DARF_RC3 16 -#define BIT_MASK_DARF_RC3 0x1f -#define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3) -#define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DARF_RC2 8 -#define BIT_MASK_DARF_RC2 0x1f -#define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2) -#define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2) +/* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */ +#define BIT_SHIFT_HI6Q_HW_IDX 16 +#define BIT_MASK_HI6Q_HW_IDX 0xfff +#define BIT_HI6Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX) +#define BITS_HI6Q_HW_IDX (BIT_MASK_HI6Q_HW_IDX << BIT_SHIFT_HI6Q_HW_IDX) +#define BIT_CLEAR_HI6Q_HW_IDX(x) ((x) & (~BITS_HI6Q_HW_IDX)) +#define BIT_GET_HI6Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX) +#define BIT_SET_HI6Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI6Q_HW_IDX(x) | BIT_HI6Q_HW_IDX(v)) -#define BIT_SHIFT_DARF_RC1 0 -#define BIT_MASK_DARF_RC1 0x1f -#define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1) -#define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_RARFRC (Offset 0x0438) */ +/* 2 REG_P0HI6Q_TXBD_IDX (Offset 0x03D0) */ +#define BIT_SHIFT_P0HI6Q_HW_IDX 16 +#define BIT_MASK_P0HI6Q_HW_IDX 0xfff +#define BIT_P0HI6Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI6Q_HW_IDX) << BIT_SHIFT_P0HI6Q_HW_IDX) +#define BITS_P0HI6Q_HW_IDX (BIT_MASK_P0HI6Q_HW_IDX << BIT_SHIFT_P0HI6Q_HW_IDX) +#define BIT_CLEAR_P0HI6Q_HW_IDX(x) ((x) & (~BITS_P0HI6Q_HW_IDX)) +#define BIT_GET_P0HI6Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_HW_IDX) & BIT_MASK_P0HI6Q_HW_IDX) +#define BIT_SET_P0HI6Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI6Q_HW_IDX(x) | BIT_P0HI6Q_HW_IDX(v)) -#define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC8 0x1f -#define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8) -#define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC7 0x1f -#define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7) -#define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7) +/* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */ +#define BIT_SHIFT_HI6Q_HOST_IDX 0 +#define BIT_MASK_HI6Q_HOST_IDX 0xfff +#define BIT_HI6Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX) +#define BITS_HI6Q_HOST_IDX (BIT_MASK_HI6Q_HOST_IDX << BIT_SHIFT_HI6Q_HOST_IDX) +#define BIT_CLEAR_HI6Q_HOST_IDX(x) ((x) & (~BITS_HI6Q_HOST_IDX)) +#define BIT_GET_HI6Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX) +#define BIT_SET_HI6Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI6Q_HOST_IDX(x) | BIT_HI6Q_HOST_IDX(v)) -#define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC6 0x1f -#define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6) -#define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC5 0x1f -#define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5) -#define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5) +/* 2 REG_P0HI6Q_TXBD_IDX (Offset 0x03D0) */ +#define BIT_SHIFT_P0HI6Q_HOST_IDX 0 +#define BIT_MASK_P0HI6Q_HOST_IDX 0xfff +#define BIT_P0HI6Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI6Q_HOST_IDX) << BIT_SHIFT_P0HI6Q_HOST_IDX) +#define BITS_P0HI6Q_HOST_IDX \ + (BIT_MASK_P0HI6Q_HOST_IDX << BIT_SHIFT_P0HI6Q_HOST_IDX) +#define BIT_CLEAR_P0HI6Q_HOST_IDX(x) ((x) & (~BITS_P0HI6Q_HOST_IDX)) +#define BIT_GET_P0HI6Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_HOST_IDX) & BIT_MASK_P0HI6Q_HOST_IDX) +#define BIT_SET_P0HI6Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI6Q_HOST_IDX(x) | BIT_P0HI6Q_HOST_IDX(v)) -#define BIT_SHIFT_RARF_RC4 24 -#define BIT_MASK_RARF_RC4 0x1f -#define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4) -#define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RARF_RC3 16 -#define BIT_MASK_RARF_RC3 0x1f -#define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3) -#define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3) +/* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */ +#define BIT_SHIFT_HI7Q_HW_IDX 16 +#define BIT_MASK_HI7Q_HW_IDX 0xfff +#define BIT_HI7Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX) +#define BITS_HI7Q_HW_IDX (BIT_MASK_HI7Q_HW_IDX << BIT_SHIFT_HI7Q_HW_IDX) +#define BIT_CLEAR_HI7Q_HW_IDX(x) ((x) & (~BITS_HI7Q_HW_IDX)) +#define BIT_GET_HI7Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX) +#define BIT_SET_HI7Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI7Q_HW_IDX(x) | BIT_HI7Q_HW_IDX(v)) -#define BIT_SHIFT_RARF_RC2 8 -#define BIT_MASK_RARF_RC2 0x1f -#define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2) -#define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RARF_RC1 0 -#define BIT_MASK_RARF_RC1 0x1f -#define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1) -#define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1) +/* 2 REG_P0HI7Q_TXBD_IDX (Offset 0x03D4) */ +#define BIT_SHIFT_P0HI7Q_HW_IDX 16 +#define BIT_MASK_P0HI7Q_HW_IDX 0xfff +#define BIT_P0HI7Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI7Q_HW_IDX) << BIT_SHIFT_P0HI7Q_HW_IDX) +#define BITS_P0HI7Q_HW_IDX (BIT_MASK_P0HI7Q_HW_IDX << BIT_SHIFT_P0HI7Q_HW_IDX) +#define BIT_CLEAR_P0HI7Q_HW_IDX(x) ((x) & (~BITS_P0HI7Q_HW_IDX)) +#define BIT_GET_P0HI7Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_HW_IDX) & BIT_MASK_P0HI7Q_HW_IDX) +#define BIT_SET_P0HI7Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI7Q_HW_IDX(x) | BIT_P0HI7Q_HW_IDX(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */ +#define BIT_SHIFT_HI7Q_HOST_IDX 0 +#define BIT_MASK_HI7Q_HOST_IDX 0xfff +#define BIT_HI7Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX) +#define BITS_HI7Q_HOST_IDX (BIT_MASK_HI7Q_HOST_IDX << BIT_SHIFT_HI7Q_HOST_IDX) +#define BIT_CLEAR_HI7Q_HOST_IDX(x) ((x) & (~BITS_HI7Q_HOST_IDX)) +#define BIT_GET_HI7Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX) +#define BIT_SET_HI7Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI7Q_HOST_IDX(x) | BIT_HI7Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI7Q_TXBD_IDX (Offset 0x03D4) */ + +#define BIT_SHIFT_P0HI7Q_HOST_IDX 0 +#define BIT_MASK_P0HI7Q_HOST_IDX 0xfff +#define BIT_P0HI7Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI7Q_HOST_IDX) << BIT_SHIFT_P0HI7Q_HOST_IDX) +#define BITS_P0HI7Q_HOST_IDX \ + (BIT_MASK_P0HI7Q_HOST_IDX << BIT_SHIFT_P0HI7Q_HOST_IDX) +#define BIT_CLEAR_P0HI7Q_HOST_IDX(x) ((x) & (~BITS_P0HI7Q_HOST_IDX)) +#define BIT_GET_P0HI7Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_HOST_IDX) & BIT_MASK_P0HI7Q_HOST_IDX) +#define BIT_SET_P0HI7Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI7Q_HOST_IDX(x) | BIT_P0HI7Q_HOST_IDX(v)) + +/* 2 REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1 (Offset 0x03D8) */ + +#define BIT_DIS_TXDMA_PRE_V1 BIT(31) +#define BIT_DIS_RXDMA_PRE_V1 BIT(30) + +#define BIT_SHIFT_HPS_CLKR_PCIE_V1 28 +#define BIT_MASK_HPS_CLKR_PCIE_V1 0x3 +#define BIT_HPS_CLKR_PCIE_V1(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE_V1) << BIT_SHIFT_HPS_CLKR_PCIE_V1) +#define BITS_HPS_CLKR_PCIE_V1 \ + (BIT_MASK_HPS_CLKR_PCIE_V1 << BIT_SHIFT_HPS_CLKR_PCIE_V1) +#define BIT_CLEAR_HPS_CLKR_PCIE_V1(x) ((x) & (~BITS_HPS_CLKR_PCIE_V1)) +#define BIT_GET_HPS_CLKR_PCIE_V1(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_V1) & BIT_MASK_HPS_CLKR_PCIE_V1) +#define BIT_SET_HPS_CLKR_PCIE_V1(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE_V1(x) | BIT_HPS_CLKR_PCIE_V1(v)) + +#define BIT_PCIE_INT_V1 BIT(27) +#define BIT_TXFLAG_EXIT_L1_EN_V1 BIT(26) +#define BIT_EN_RXDMA_ALIGN_V2 BIT(25) +#define BIT_EN_TXDMA_ALIGN_V2 BIT(24) + +#define BIT_SHIFT_PCIE_HCPWM_V1 16 +#define BIT_MASK_PCIE_HCPWM_V1 0xff +#define BIT_PCIE_HCPWM_V1(x) \ + (((x) & BIT_MASK_PCIE_HCPWM_V1) << BIT_SHIFT_PCIE_HCPWM_V1) +#define BITS_PCIE_HCPWM_V1 (BIT_MASK_PCIE_HCPWM_V1 << BIT_SHIFT_PCIE_HCPWM_V1) +#define BIT_CLEAR_PCIE_HCPWM_V1(x) ((x) & (~BITS_PCIE_HCPWM_V1)) +#define BIT_GET_PCIE_HCPWM_V1(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM_V1) & BIT_MASK_PCIE_HCPWM_V1) +#define BIT_SET_PCIE_HCPWM_V1(x, v) \ + (BIT_CLEAR_PCIE_HCPWM_V1(x) | BIT_PCIE_HCPWM_V1(v)) + +#define BIT_SHIFT_PCIE_HRPWM_V1 8 +#define BIT_MASK_PCIE_HRPWM_V1 0xff +#define BIT_PCIE_HRPWM_V1(x) \ + (((x) & BIT_MASK_PCIE_HRPWM_V1) << BIT_SHIFT_PCIE_HRPWM_V1) +#define BITS_PCIE_HRPWM_V1 (BIT_MASK_PCIE_HRPWM_V1 << BIT_SHIFT_PCIE_HRPWM_V1) +#define BIT_CLEAR_PCIE_HRPWM_V1(x) ((x) & (~BITS_PCIE_HRPWM_V1)) +#define BIT_GET_PCIE_HRPWM_V1(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM_V1) & BIT_MASK_PCIE_HRPWM_V1) +#define BIT_SET_PCIE_HRPWM_V1(x, v) \ + (BIT_CLEAR_PCIE_HRPWM_V1(x) | BIT_PCIE_HRPWM_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RRSR (Offset 0x0440) */ +/* 2 REG_DBG_SEL_V1 (Offset 0x03D8) */ -#define BIT_EN_VHTBW_FALL BIT(31) -#define BIT_EN_HTBW_FALL BIT(30) +#define BIT_SHIFT_DBG_SEL 0 +#define BIT_MASK_DBG_SEL 0xff +#define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL) +#define BITS_DBG_SEL (BIT_MASK_DBG_SEL << BIT_SHIFT_DBG_SEL) +#define BIT_CLEAR_DBG_SEL(x) ((x) & (~BITS_DBG_SEL)) +#define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL) +#define BIT_SET_DBG_SEL(x, v) (BIT_CLEAR_DBG_SEL(x) | BIT_DBG_SEL(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PCIE_HRPWM1_V1 (Offset 0x03D9) */ +#define BIT_SHIFT_PCIE_HRPWM 0 +#define BIT_MASK_PCIE_HRPWM 0xff +#define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM) +#define BITS_PCIE_HRPWM (BIT_MASK_PCIE_HRPWM << BIT_SHIFT_PCIE_HRPWM) +#define BIT_CLEAR_PCIE_HRPWM(x) ((x) & (~BITS_PCIE_HRPWM)) +#define BIT_GET_PCIE_HRPWM(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM) +#define BIT_SET_PCIE_HRPWM(x, v) (BIT_CLEAR_PCIE_HRPWM(x) | BIT_PCIE_HRPWM(v)) -/* 2 REG_RRSR (Offset 0x0440) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RRSR_RSC 21 -#define BIT_MASK_RRSR_RSC 0x3 -#define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC) -#define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC) +/* 2 REG_HCI_HRPWM1_V1 (Offset 0x03D9) */ -#define BIT_RRSR_BW BIT(20) +#define BIT_SHIFT_HCI_HRPWM 0 +#define BIT_MASK_HCI_HRPWM 0xff +#define BIT_HCI_HRPWM(x) (((x) & BIT_MASK_HCI_HRPWM) << BIT_SHIFT_HCI_HRPWM) +#define BITS_HCI_HRPWM (BIT_MASK_HCI_HRPWM << BIT_SHIFT_HCI_HRPWM) +#define BIT_CLEAR_HCI_HRPWM(x) ((x) & (~BITS_HCI_HRPWM)) +#define BIT_GET_HCI_HRPWM(x) (((x) >> BIT_SHIFT_HCI_HRPWM) & BIT_MASK_HCI_HRPWM) +#define BIT_SET_HCI_HRPWM(x, v) (BIT_CLEAR_HCI_HRPWM(x) | BIT_HCI_HRPWM(v)) -#define BIT_SHIFT_RRSC_BITMAP 0 -#define BIT_MASK_RRSC_BITMAP 0xfffff -#define BIT_RRSC_BITMAP(x) (((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP) -#define BIT_GET_RRSC_BITMAP(x) (((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_ARFR0 (Offset 0x0444) */ +/* 2 REG_PCIE_HCPWM1_V1 (Offset 0x03DA) */ +#define BIT_SHIFT_PCIE_HCPWM 0 +#define BIT_MASK_PCIE_HCPWM 0xff +#define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM) +#define BITS_PCIE_HCPWM (BIT_MASK_PCIE_HCPWM << BIT_SHIFT_PCIE_HCPWM) +#define BIT_CLEAR_PCIE_HCPWM(x) ((x) & (~BITS_PCIE_HCPWM)) +#define BIT_GET_PCIE_HCPWM(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM) +#define BIT_SET_PCIE_HCPWM(x, v) (BIT_CLEAR_PCIE_HCPWM(x) | BIT_PCIE_HCPWM(v)) -#define BIT_SHIFT_ARFR0_V1 0 -#define BIT_MASK_ARFR0_V1 0xffffffffffffffffL -#define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1) -#define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_ARFR1_V1 (Offset 0x044C) */ +/* 2 REG_HCI_HCPWM1_V1 (Offset 0x03DA) */ +#define BIT_SHIFT_HCI_HCPWM 0 +#define BIT_MASK_HCI_HCPWM 0xff +#define BIT_HCI_HCPWM(x) (((x) & BIT_MASK_HCI_HCPWM) << BIT_SHIFT_HCI_HCPWM) +#define BITS_HCI_HCPWM (BIT_MASK_HCI_HCPWM << BIT_SHIFT_HCI_HCPWM) +#define BIT_CLEAR_HCI_HCPWM(x) ((x) & (~BITS_HCI_HCPWM)) +#define BIT_GET_HCI_HCPWM(x) (((x) >> BIT_SHIFT_HCI_HCPWM) & BIT_MASK_HCI_HCPWM) +#define BIT_SET_HCI_HCPWM(x, v) (BIT_CLEAR_HCI_HCPWM(x) | BIT_HCI_HCPWM(v)) -#define BIT_SHIFT_ARFR1_V1 0 -#define BIT_MASK_ARFR1_V1 0xffffffffffffffffL -#define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1) -#define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_CCK_CHECK (Offset 0x0454) */ +/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ -#define BIT_CHECK_CCK_EN BIT(7) -#define BIT_EN_BCN_PKT_REL BIT(6) -#define BIT_BCN_PORT_SEL BIT(5) -#define BIT_MOREDATA_BYPASS BIT(4) -#define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3) +#define BIT_SHIFT_HPS_CLKR_PCIE 4 +#define BIT_MASK_HPS_CLKR_PCIE 0x3 +#define BIT_HPS_CLKR_PCIE(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE) +#define BITS_HPS_CLKR_PCIE (BIT_MASK_HPS_CLKR_PCIE << BIT_SHIFT_HPS_CLKR_PCIE) +#define BIT_CLEAR_HPS_CLKR_PCIE(x) ((x) & (~BITS_HPS_CLKR_PCIE)) +#define BIT_GET_HPS_CLKR_PCIE(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE) +#define BIT_SET_HPS_CLKR_PCIE(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE(x) | BIT_HPS_CLKR_PCIE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_CCK_CHECK (Offset 0x0454) */ +/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */ -#define BIT_R_EN_SET_MOREDATA BIT(2) -#define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1) -#define BIT__R_MACID_RELEASE_EN BIT(0) +#define BIT_SHIFT_HPS_CLKR_HCI 4 +#define BIT_MASK_HPS_CLKR_HCI 0x3 +#define BIT_HPS_CLKR_HCI(x) \ + (((x) & BIT_MASK_HPS_CLKR_HCI) << BIT_SHIFT_HPS_CLKR_HCI) +#define BITS_HPS_CLKR_HCI (BIT_MASK_HPS_CLKR_HCI << BIT_SHIFT_HPS_CLKR_HCI) +#define BIT_CLEAR_HPS_CLKR_HCI(x) ((x) & (~BITS_HPS_CLKR_HCI)) +#define BIT_GET_HPS_CLKR_HCI(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_HCI) & BIT_MASK_HPS_CLKR_HCI) +#define BIT_SET_HPS_CLKR_HCI(x, v) \ + (BIT_CLEAR_HPS_CLKR_HCI(x) | BIT_HPS_CLKR_HCI(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_AMPDU_BURST_CTRL (Offset 0x0455) */ +/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ -#define BIT_AMPDU_BURST_GLOBAL_EN BIT(0) +#define BIT_PCIE_INT BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */ +#define BIT_HCI_INT BIT(3) -/* 2 REG_AMPDU_MAX_TIME (Offset 0x0456) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AMPDU_MAX_TIME 0 -#define BIT_MASK_AMPDU_MAX_TIME 0xff -#define BIT_AMPDU_MAX_TIME(x) (((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME) -#define BIT_GET_AMPDU_MAX_TIME(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME) +/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ +#define BIT_EN_RXDMA_ALIGN BIT(1) +#define BIT_EN_TXDMA_ALIGN BIT(0) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PCIE_HRPWM2_HCPWM2_V1 (Offset 0x03DC) */ +#define BIT_SHIFT_PCIE_HCPWM2_V1 16 +#define BIT_MASK_PCIE_HCPWM2_V1 0xffff +#define BIT_PCIE_HCPWM2_V1(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2_V1) << BIT_SHIFT_PCIE_HCPWM2_V1) +#define BITS_PCIE_HCPWM2_V1 \ + (BIT_MASK_PCIE_HCPWM2_V1 << BIT_SHIFT_PCIE_HCPWM2_V1) +#define BIT_CLEAR_PCIE_HCPWM2_V1(x) ((x) & (~BITS_PCIE_HCPWM2_V1)) +#define BIT_GET_PCIE_HCPWM2_V1(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2_V1) & BIT_MASK_PCIE_HCPWM2_V1) +#define BIT_SET_PCIE_HCPWM2_V1(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2_V1(x) | BIT_PCIE_HCPWM2_V1(v)) -/* 2 REG_BCNQ1_BDNY_V1 (Offset 0x0456) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCNQ1_PGBNDY_V1 0 -#define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff -#define BIT_BCNQ1_PGBNDY_V1(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1) -#define BIT_GET_BCNQ1_PGBNDY_V1(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1) +/* 2 REG_PCIE_HRPWM2_V1 (Offset 0x03DC) */ +#define BIT_SHIFT_PCIE_HRPWM2 0 +#define BIT_MASK_PCIE_HRPWM2 0xffff +#define BIT_PCIE_HRPWM2(x) \ + (((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2) +#define BITS_PCIE_HRPWM2 (BIT_MASK_PCIE_HRPWM2 << BIT_SHIFT_PCIE_HRPWM2) +#define BIT_CLEAR_PCIE_HRPWM2(x) ((x) & (~BITS_PCIE_HRPWM2)) +#define BIT_GET_PCIE_HRPWM2(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2) +#define BIT_SET_PCIE_HRPWM2(x, v) \ + (BIT_CLEAR_PCIE_HRPWM2(x) | BIT_PCIE_HRPWM2(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_HRPWM2_V1 (Offset 0x03DC) */ +#define BIT_SHIFT_HCI_HRPWM2 0 +#define BIT_MASK_HCI_HRPWM2 0xffff +#define BIT_HCI_HRPWM2(x) (((x) & BIT_MASK_HCI_HRPWM2) << BIT_SHIFT_HCI_HRPWM2) +#define BITS_HCI_HRPWM2 (BIT_MASK_HCI_HRPWM2 << BIT_SHIFT_HCI_HRPWM2) +#define BIT_CLEAR_HCI_HRPWM2(x) ((x) & (~BITS_HCI_HRPWM2)) +#define BIT_GET_HCI_HRPWM2(x) \ + (((x) >> BIT_SHIFT_HCI_HRPWM2) & BIT_MASK_HCI_HRPWM2) +#define BIT_SET_HCI_HRPWM2(x, v) (BIT_CLEAR_HCI_HRPWM2(x) | BIT_HCI_HRPWM2(v)) -/* 2 REG_BCNQ1_BDNY (Offset 0x0457) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCNQ1_PGBNDY 0 -#define BIT_MASK_BCNQ1_PGBNDY 0xff -#define BIT_BCNQ1_PGBNDY(x) (((x) & BIT_MASK_BCNQ1_PGBNDY) << BIT_SHIFT_BCNQ1_PGBNDY) -#define BIT_GET_BCNQ1_PGBNDY(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY) & BIT_MASK_BCNQ1_PGBNDY) +/* 2 REG_PCIE_HCPWM2_V1 (Offset 0x03DE) */ +#define BIT_SHIFT_PCIE_HCPWM2 0 +#define BIT_MASK_PCIE_HCPWM2 0xffff +#define BIT_PCIE_HCPWM2(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2) +#define BITS_PCIE_HCPWM2 (BIT_MASK_PCIE_HCPWM2 << BIT_SHIFT_PCIE_HCPWM2) +#define BIT_CLEAR_PCIE_HCPWM2(x) ((x) & (~BITS_PCIE_HCPWM2)) +#define BIT_GET_PCIE_HCPWM2(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2) +#define BIT_SET_PCIE_HCPWM2(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2(x) | BIT_PCIE_HCPWM2(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_HCPWM2_V1 (Offset 0x03DE) */ +#define BIT_SHIFT_HCI_HCPWM2 0 +#define BIT_MASK_HCI_HCPWM2 0xffff +#define BIT_HCI_HCPWM2(x) (((x) & BIT_MASK_HCI_HCPWM2) << BIT_SHIFT_HCI_HCPWM2) +#define BITS_HCI_HCPWM2 (BIT_MASK_HCI_HCPWM2 << BIT_SHIFT_HCI_HCPWM2) +#define BIT_CLEAR_HCI_HCPWM2(x) ((x) & (~BITS_HCI_HCPWM2)) +#define BIT_GET_HCI_HCPWM2(x) \ + (((x) >> BIT_SHIFT_HCI_HCPWM2) & BIT_MASK_HCI_HCPWM2) +#define BIT_SET_HCI_HCPWM2(x, v) (BIT_CLEAR_HCI_HCPWM2(x) | BIT_HCI_HCPWM2(v)) -/* 2 REG_AMPDU_MAX_LENGTH (Offset 0x0458) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_AMPDU_MAX_LENGTH 0 -#define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL -#define BIT_AMPDU_MAX_LENGTH(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH) -#define BIT_GET_AMPDU_MAX_LENGTH(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH) +/* 2 REG_PCIE_H2C_MSG_V1 (Offset 0x03E0) */ +#define BIT_AC7Q_EMPTY BIT(7) +#define BIT_AC6Q_EMPTY BIT(6) +#define BIT_AC5Q_EMPTY BIT(5) +#define BIT_AC4Q_EMPTY BIT(4) +#define BIT_AC3Q_EMPTY BIT(3) +#define BIT_AC2Q_EMPTY BIT(2) +#define BIT_AC1Q_EMPTY BIT(1) -/* 2 REG_ACQ_STOP (Offset 0x045C) */ +#define BIT_SHIFT_DRV2FW_INFO 0 +#define BIT_MASK_DRV2FW_INFO 0xffffffffL +#define BIT_DRV2FW_INFO(x) \ + (((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO) +#define BITS_DRV2FW_INFO (BIT_MASK_DRV2FW_INFO << BIT_SHIFT_DRV2FW_INFO) +#define BIT_CLEAR_DRV2FW_INFO(x) ((x) & (~BITS_DRV2FW_INFO)) +#define BIT_GET_DRV2FW_INFO(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO) +#define BIT_SET_DRV2FW_INFO(x, v) \ + (BIT_CLEAR_DRV2FW_INFO(x) | BIT_DRV2FW_INFO(v)) -#define BIT_AC7Q_STOP BIT(7) -#define BIT_AC6Q_STOP BIT(6) -#define BIT_AC5Q_STOP BIT(5) -#define BIT_AC4Q_STOP BIT(4) -#define BIT_AC3Q_STOP BIT(3) -#define BIT_AC2Q_STOP BIT(2) -#define BIT_AC1Q_STOP BIT(1) -#define BIT_AC0Q_STOP BIT(0) +#define BIT_AC0Q_EMPTY BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PCIE_C2H_MSG_V1 (Offset 0x03E4) */ +#define BIT_SHIFT_HCI_PCIE_C2H_MSG 0 +#define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL +#define BIT_HCI_PCIE_C2H_MSG(x) \ + (((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG) +#define BITS_HCI_PCIE_C2H_MSG \ + (BIT_MASK_HCI_PCIE_C2H_MSG << BIT_SHIFT_HCI_PCIE_C2H_MSG) +#define BIT_CLEAR_HCI_PCIE_C2H_MSG(x) ((x) & (~BITS_HCI_PCIE_C2H_MSG)) +#define BIT_GET_HCI_PCIE_C2H_MSG(x) \ + (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG) +#define BIT_SET_HCI_PCIE_C2H_MSG(x, v) \ + (BIT_CLEAR_HCI_PCIE_C2H_MSG(x) | BIT_HCI_PCIE_C2H_MSG(v)) -/* 2 REG_WMAC_LBK_BUF_HD (Offset 0x045D) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_WMAC_LBK_BUF_HEAD 0 -#define BIT_MASK_WMAC_LBK_BUF_HEAD 0xff -#define BIT_WMAC_LBK_BUF_HEAD(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD) << BIT_SHIFT_WMAC_LBK_BUF_HEAD) -#define BIT_GET_WMAC_LBK_BUF_HEAD(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD) & BIT_MASK_WMAC_LBK_BUF_HEAD) +/* 2 REG_HCI_C2H_MSG_V1 (Offset 0x03E4) */ +#define BIT_SHIFT_HCI_C2H_MSG 0 +#define BIT_MASK_HCI_C2H_MSG 0xffffffffL +#define BIT_HCI_C2H_MSG(x) \ + (((x) & BIT_MASK_HCI_C2H_MSG) << BIT_SHIFT_HCI_C2H_MSG) +#define BITS_HCI_C2H_MSG (BIT_MASK_HCI_C2H_MSG << BIT_SHIFT_HCI_C2H_MSG) +#define BIT_CLEAR_HCI_C2H_MSG(x) ((x) & (~BITS_HCI_C2H_MSG)) +#define BIT_GET_HCI_C2H_MSG(x) \ + (((x) >> BIT_SHIFT_HCI_C2H_MSG) & BIT_MASK_HCI_C2H_MSG) +#define BIT_SET_HCI_C2H_MSG(x, v) \ + (BIT_CLEAR_HCI_C2H_MSG(x) | BIT_HCI_C2H_MSG(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DBI_WDATA_V1 (Offset 0x03E8) */ +#define BIT_SHIFT_DBI_WDATA 0 +#define BIT_MASK_DBI_WDATA 0xffffffffL +#define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA) +#define BITS_DBI_WDATA (BIT_MASK_DBI_WDATA << BIT_SHIFT_DBI_WDATA) +#define BIT_CLEAR_DBI_WDATA(x) ((x) & (~BITS_DBI_WDATA)) +#define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA) +#define BIT_SET_DBI_WDATA(x, v) (BIT_CLEAR_DBI_WDATA(x) | BIT_DBI_WDATA(v)) -/* 2 REG_NDPA_RATE (Offset 0x045D) */ +/* 2 REG_DBI_RDATA_V1 (Offset 0x03EC) */ +#define BIT_SHIFT_DBI_RDATA 0 +#define BIT_MASK_DBI_RDATA 0xffffffffL +#define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA) +#define BITS_DBI_RDATA (BIT_MASK_DBI_RDATA << BIT_SHIFT_DBI_RDATA) +#define BIT_CLEAR_DBI_RDATA(x) ((x) & (~BITS_DBI_RDATA)) +#define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA) +#define BIT_SET_DBI_RDATA(x, v) (BIT_CLEAR_DBI_RDATA(x) | BIT_DBI_RDATA(v)) -#define BIT_SHIFT_R_NDPA_RATE_V1 0 -#define BIT_MASK_R_NDPA_RATE_V1 0xff -#define BIT_R_NDPA_RATE_V1(x) (((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1) -#define BIT_GET_R_NDPA_RATE_V1(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1) +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */ +#define BIT_SHIFT_LOOPBACK_DBG_SEL 28 +#define BIT_MASK_LOOPBACK_DBG_SEL 0xf +#define BIT_LOOPBACK_DBG_SEL(x) \ + (((x) & BIT_MASK_LOOPBACK_DBG_SEL) << BIT_SHIFT_LOOPBACK_DBG_SEL) +#define BITS_LOOPBACK_DBG_SEL \ + (BIT_MASK_LOOPBACK_DBG_SEL << BIT_SHIFT_LOOPBACK_DBG_SEL) +#define BIT_CLEAR_LOOPBACK_DBG_SEL(x) ((x) & (~BITS_LOOPBACK_DBG_SEL)) +#define BIT_GET_LOOPBACK_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_LOOPBACK_DBG_SEL) & BIT_MASK_LOOPBACK_DBG_SEL) +#define BIT_SET_LOOPBACK_DBG_SEL(x, v) \ + (BIT_CLEAR_LOOPBACK_DBG_SEL(x) | BIT_LOOPBACK_DBG_SEL(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */ +#define BIT_EN_STUCK_DBG BIT(26) +#define BIT_RX_STUCK BIT(25) +#define BIT_TX_STUCK BIT(24) +#define BIT_DBI_RFLAG BIT(17) +#define BIT_DBI_WFLAG BIT(16) + +#define BIT_SHIFT_DBI_WREN 12 +#define BIT_MASK_DBI_WREN 0xf +#define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN) +#define BITS_DBI_WREN (BIT_MASK_DBI_WREN << BIT_SHIFT_DBI_WREN) +#define BIT_CLEAR_DBI_WREN(x) ((x) & (~BITS_DBI_WREN)) +#define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN) +#define BIT_SET_DBI_WREN(x, v) (BIT_CLEAR_DBI_WREN(x) | BIT_DBI_WREN(v)) + +#define BIT_SHIFT_DBI_ADDR 0 +#define BIT_MASK_DBI_ADDR 0xfff +#define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR) +#define BITS_DBI_ADDR (BIT_MASK_DBI_ADDR << BIT_SHIFT_DBI_ADDR) +#define BIT_CLEAR_DBI_ADDR(x) ((x) & (~BITS_DBI_ADDR)) +#define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR) +#define BIT_SET_DBI_ADDR(x, v) (BIT_CLEAR_DBI_ADDR(x) | BIT_DBI_ADDR(v)) -/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +/* 2 REG_MDIO_V1 (Offset 0x03F4) */ -#define BIT_R_EN_GNT_BT_AWAKE BIT(3) +#define BIT_SHIFT_MDIO_RDATA 16 +#define BIT_MASK_MDIO_RDATA 0xffff +#define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA) +#define BITS_MDIO_RDATA (BIT_MASK_MDIO_RDATA << BIT_SHIFT_MDIO_RDATA) +#define BIT_CLEAR_MDIO_RDATA(x) ((x) & (~BITS_MDIO_RDATA)) +#define BIT_GET_MDIO_RDATA(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA) +#define BIT_SET_MDIO_RDATA(x, v) (BIT_CLEAR_MDIO_RDATA(x) | BIT_MDIO_RDATA(v)) -#endif +#define BIT_SHIFT_MDIO_WDATA 0 +#define BIT_MASK_MDIO_WDATA 0xffff +#define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA) +#define BITS_MDIO_WDATA (BIT_MASK_MDIO_WDATA << BIT_SHIFT_MDIO_WDATA) +#define BIT_CLEAR_MDIO_WDATA(x) ((x) & (~BITS_MDIO_WDATA)) +#define BIT_GET_MDIO_WDATA(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA) +#define BIT_SET_MDIO_WDATA(x, v) (BIT_CLEAR_MDIO_WDATA(x) | BIT_MDIO_WDATA(v)) +#endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8881A_SUPPORT) +/* 2 REG_BUS_MIX_CFG (Offset 0x03F8) */ -/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +#define BIT_SHIFT_DELAY_TIME 24 +#define BIT_MASK_DELAY_TIME 0xff +#define BIT_DELAY_TIME(x) (((x) & BIT_MASK_DELAY_TIME) << BIT_SHIFT_DELAY_TIME) +#define BITS_DELAY_TIME (BIT_MASK_DELAY_TIME << BIT_SHIFT_DELAY_TIME) +#define BIT_CLEAR_DELAY_TIME(x) ((x) & (~BITS_DELAY_TIME)) +#define BIT_GET_DELAY_TIME(x) \ + (((x) >> BIT_SHIFT_DELAY_TIME) & BIT_MASK_DELAY_TIME) +#define BIT_SET_DELAY_TIME(x, v) (BIT_CLEAR_DELAY_TIME(x) | BIT_DELAY_TIME(v)) -#define BIT_EN_EOF_V1 BIT(2) +#define BIT_RX_TIMER_DELAY_EN BIT(17) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ +#define BIT_EN_WATCH_DOG BIT(8) -/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +#endif -#define BIT_DIS_OQT_BLOCK BIT(1) -#define BIT_SEARCH_QUEUE_EN BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_MDIO2_V1 (Offset 0x03F8) */ +#define BIT_ECRC_EN BIT(7) +#define BIT_MDIO_RFLAG BIT(6) +#define BIT_MDIO_WFLAG BIT(5) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT) -/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +/* 2 REG_MDIO2_V1 (Offset 0x03F8) */ + +#define BIT_SHIFT_MDIO_ADDR 0 +#define BIT_MASK_MDIO_ADDR 0x1f +#define BIT_MDIO_ADDR(x) (((x) & BIT_MASK_MDIO_ADDR) << BIT_SHIFT_MDIO_ADDR) +#define BITS_MDIO_ADDR (BIT_MASK_MDIO_ADDR << BIT_SHIFT_MDIO_ADDR) +#define BIT_CLEAR_MDIO_ADDR(x) ((x) & (~BITS_MDIO_ADDR)) +#define BIT_GET_MDIO_ADDR(x) (((x) >> BIT_SHIFT_MDIO_ADDR) & BIT_MASK_MDIO_ADDR) +#define BIT_SET_MDIO_ADDR(x, v) (BIT_CLEAR_MDIO_ADDR(x) | BIT_MDIO_ADDR(v)) -#define BIT_R_DIS_MACID_RELEASE_RTY BIT(5) +#define BIT_SHIFT_TXFAIL_DROPCNT 0 +#define BIT_MASK_TXFAIL_DROPCNT 0xffff +#define BIT_TXFAIL_DROPCNT(x) \ + (((x) & BIT_MASK_TXFAIL_DROPCNT) << BIT_SHIFT_TXFAIL_DROPCNT) +#define BITS_TXFAIL_DROPCNT \ + (BIT_MASK_TXFAIL_DROPCNT << BIT_SHIFT_TXFAIL_DROPCNT) +#define BIT_CLEAR_TXFAIL_DROPCNT(x) ((x) & (~BITS_TXFAIL_DROPCNT)) +#define BIT_GET_TXFAIL_DROPCNT(x) \ + (((x) >> BIT_SHIFT_TXFAIL_DROPCNT) & BIT_MASK_TXFAIL_DROPCNT) +#define BIT_SET_TXFAIL_DROPCNT(x, v) \ + (BIT_CLEAR_TXFAIL_DROPCNT(x) | BIT_TXFAIL_DROPCNT(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ +#define BIT_SHIFT_MDIO_REG_ADDR_V1 0 +#define BIT_MASK_MDIO_REG_ADDR_V1 0x1f +#define BIT_MDIO_REG_ADDR_V1(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1) +#define BITS_MDIO_REG_ADDR_V1 \ + (BIT_MASK_MDIO_REG_ADDR_V1 << BIT_SHIFT_MDIO_REG_ADDR_V1) +#define BIT_CLEAR_MDIO_REG_ADDR_V1(x) ((x) & (~BITS_MDIO_REG_ADDR_V1)) +#define BIT_GET_MDIO_REG_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1) +#define BIT_SET_MDIO_REG_ADDR_V1(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_V1(x) | BIT_MDIO_REG_ADDR_V1(v)) -/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_BW_SIGTA 3 -#define BIT_MASK_BW_SIGTA 0x3 -#define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA) -#define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_RXRST_BACKDOOR BIT(31) +#define BIT_TXRST_BACKDOOR BIT(30) +#define BIT_RXIDX_RSTB BIT(29) +#define BIT_TXIDX_RSTB BIT(28) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_WATCH_DOG_TIMER 28 +#define BIT_MASK_WATCH_DOG_TIMER 0xf +#define BIT_WATCH_DOG_TIMER(x) \ + (((x) & BIT_MASK_WATCH_DOG_TIMER) << BIT_SHIFT_WATCH_DOG_TIMER) +#define BITS_WATCH_DOG_TIMER \ + (BIT_MASK_WATCH_DOG_TIMER << BIT_SHIFT_WATCH_DOG_TIMER) +#define BIT_CLEAR_WATCH_DOG_TIMER(x) ((x) & (~BITS_WATCH_DOG_TIMER)) +#define BIT_GET_WATCH_DOG_TIMER(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_TIMER) & BIT_MASK_WATCH_DOG_TIMER) +#define BIT_SET_WATCH_DOG_TIMER(x, v) \ + (BIT_CLEAR_WATCH_DOG_TIMER(x) | BIT_WATCH_DOG_TIMER(v)) -/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_R_NDPA_RATE 2 -#define BIT_MASK_R_NDPA_RATE 0x3f -#define BIT_R_NDPA_RATE(x) (((x) & BIT_MASK_R_NDPA_RATE) << BIT_SHIFT_R_NDPA_RATE) -#define BIT_GET_R_NDPA_RATE(x) (((x) >> BIT_SHIFT_R_NDPA_RATE) & BIT_MASK_R_NDPA_RATE) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_DROP_NEXT_RXPKT BIT(27) +#define BIT_SHORT_CORE_RST_SEL BIT(26) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ -#define BIT_EN_BAR_SIGTA BIT(2) +#define BIT_EXCEPT_RESUME_EN BIT(25) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EXCEPT_FLAG BIT(24) -/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_R_NDPA_BW 0 -#define BIT_MASK_R_NDPA_BW 0x3 -#define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW) -#define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EXCEPT_RESUME_FLAG BIT(24) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_ALIGN_MTU BIT(23) -/* 2 REG_FAST_EDCA_CTRL (Offset 0x0460) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FAST_EDCA_TO_V1 16 -#define BIT_MASK_FAST_EDCA_TO_V1 0xff -#define BIT_FAST_EDCA_TO_V1(x) (((x) & BIT_MASK_FAST_EDCA_TO_V1) << BIT_SHIFT_FAST_EDCA_TO_V1) -#define BIT_GET_FAST_EDCA_TO_V1(x) (((x) >> BIT_SHIFT_FAST_EDCA_TO_V1) & BIT_MASK_FAST_EDCA_TO_V1) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_ALIGN_MTU BIT(23) -#define BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH 12 -#define BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH 0xf -#define BIT_AC3_AC7_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) -#define BIT_GET_AC3_AC7_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) +#endif +#if (HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_AC2_FAST_EDCA_PKT_TH 8 -#define BIT_MASK_AC2_FAST_EDCA_PKT_TH 0xf -#define BIT_AC2_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC2_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) -#define BIT_GET_AC2_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) & BIT_MASK_AC2_FAST_EDCA_PKT_TH) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EARLY_TAG_RETURN BIT(22) -#define BIT_SHIFT_AC1_FAST_EDCA_PKT_TH 4 -#define BIT_MASK_AC1_FAST_EDCA_PKT_TH 0xf -#define BIT_AC1_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC1_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) -#define BIT_GET_AC1_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) & BIT_MASK_AC1_FAST_EDCA_PKT_TH) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AC0_FAST_EDCA_PKT_TH 0 -#define BIT_MASK_AC0_FAST_EDCA_PKT_TH 0xf -#define BIT_AC0_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC0_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) -#define BIT_GET_AC0_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) & BIT_MASK_AC0_FAST_EDCA_PKT_TH) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_LATENCY_CONTROL 21 +#define BIT_MASK_LATENCY_CONTROL 0x3 +#define BIT_LATENCY_CONTROL(x) \ + (((x) & BIT_MASK_LATENCY_CONTROL) << BIT_SHIFT_LATENCY_CONTROL) +#define BITS_LATENCY_CONTROL \ + (BIT_MASK_LATENCY_CONTROL << BIT_SHIFT_LATENCY_CONTROL) +#define BIT_CLEAR_LATENCY_CONTROL(x) ((x) & (~BITS_LATENCY_CONTROL)) +#define BIT_GET_LATENCY_CONTROL(x) \ + (((x) >> BIT_SHIFT_LATENCY_CONTROL) & BIT_MASK_LATENCY_CONTROL) +#define BIT_SET_LATENCY_CONTROL(x, v) \ + (BIT_CLEAR_LATENCY_CONTROL(x) | BIT_LATENCY_CONTROL(v)) -/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RD_RESP_PKT_TH 0 -#define BIT_MASK_RD_RESP_PKT_TH 0x1f -#define BIT_RD_RESP_PKT_TH(x) (((x) & BIT_MASK_RD_RESP_PKT_TH) << BIT_SHIFT_RD_RESP_PKT_TH) -#define BIT_GET_RD_RESP_PKT_TH(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH) & BIT_MASK_RD_RESP_PKT_TH) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_HOST_GEN2_SUPPORT BIT(20) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_TXDMA_ERR_FLAG 16 +#define BIT_MASK_TXDMA_ERR_FLAG 0xf +#define BIT_TXDMA_ERR_FLAG(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG) +#define BITS_TXDMA_ERR_FLAG \ + (BIT_MASK_TXDMA_ERR_FLAG << BIT_SHIFT_TXDMA_ERR_FLAG) +#define BIT_CLEAR_TXDMA_ERR_FLAG(x) ((x) & (~BITS_TXDMA_ERR_FLAG)) +#define BIT_GET_TXDMA_ERR_FLAG(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG) +#define BIT_SET_TXDMA_ERR_FLAG(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG(x) | BIT_TXDMA_ERR_FLAG(v)) -/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RD_RESP_PKT_TH_V1 0 -#define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f -#define BIT_RD_RESP_PKT_TH_V1(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1) -#define BIT_GET_RD_RESP_PKT_TH_V1(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_TXDMA_ERR_FLAG_V1 15 +#define BIT_MASK_TXDMA_ERR_FLAG_V1 0x1f +#define BIT_TXDMA_ERR_FLAG_V1(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_V1) << BIT_SHIFT_TXDMA_ERR_FLAG_V1) +#define BITS_TXDMA_ERR_FLAG_V1 \ + (BIT_MASK_TXDMA_ERR_FLAG_V1 << BIT_SHIFT_TXDMA_ERR_FLAG_V1) +#define BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) ((x) & (~BITS_TXDMA_ERR_FLAG_V1)) +#define BIT_GET_TXDMA_ERR_FLAG_V1(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1) & BIT_MASK_TXDMA_ERR_FLAG_V1) +#define BIT_SET_TXDMA_ERR_FLAG_V1(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) | BIT_TXDMA_ERR_FLAG_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_EARLY_MODE_SEL 12 +#define BIT_MASK_EARLY_MODE_SEL 0xf +#define BIT_EARLY_MODE_SEL(x) \ + (((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL) +#define BITS_EARLY_MODE_SEL \ + (BIT_MASK_EARLY_MODE_SEL << BIT_SHIFT_EARLY_MODE_SEL) +#define BIT_CLEAR_EARLY_MODE_SEL(x) ((x) & (~BITS_EARLY_MODE_SEL)) +#define BIT_GET_EARLY_MODE_SEL(x) \ + (((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL) +#define BIT_SET_EARLY_MODE_SEL(x, v) \ + (BIT_CLEAR_EARLY_MODE_SEL(x) | BIT_EARLY_MODE_SEL(v)) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ -#define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25 -#define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f -#define BIT_QUEUEMACID_CMDQ_V1(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1) -#define BIT_GET_QUEUEMACID_CMDQ_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1) +#define BIT_EPHY_RX50_EN BIT(11) +#define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8 +#define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7 +#define BIT_MSI_TIMEOUT_ID_V1(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1) +#define BITS_MSI_TIMEOUT_ID_V1 \ + (BIT_MASK_MSI_TIMEOUT_ID_V1 << BIT_SHIFT_MSI_TIMEOUT_ID_V1) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) ((x) & (~BITS_MSI_TIMEOUT_ID_V1)) +#define BIT_GET_MSI_TIMEOUT_ID_V1(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1) +#define BIT_SET_MSI_TIMEOUT_ID_V1(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) | BIT_MSI_TIMEOUT_ID_V1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_SHIFT_RXDMA_ERR_CNT 8 +#define BIT_MASK_RXDMA_ERR_CNT 0xff +#define BIT_RXDMA_ERR_CNT(x) \ + (((x) & BIT_MASK_RXDMA_ERR_CNT) << BIT_SHIFT_RXDMA_ERR_CNT) +#define BITS_RXDMA_ERR_CNT (BIT_MASK_RXDMA_ERR_CNT << BIT_SHIFT_RXDMA_ERR_CNT) +#define BIT_CLEAR_RXDMA_ERR_CNT(x) ((x) & (~BITS_RXDMA_ERR_CNT)) +#define BIT_GET_RXDMA_ERR_CNT(x) \ + (((x) >> BIT_SHIFT_RXDMA_ERR_CNT) & BIT_MASK_RXDMA_ERR_CNT) +#define BIT_SET_RXDMA_ERR_CNT(x, v) \ + (BIT_CLEAR_RXDMA_ERR_CNT(x) | BIT_RXDMA_ERR_CNT(v)) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PKT_NUM_CMDQ_V2 24 -#define BIT_MASK_PKT_NUM_CMDQ_V2 0xff -#define BIT_PKT_NUM_CMDQ_V2(x) (((x) & BIT_MASK_PKT_NUM_CMDQ_V2) << BIT_SHIFT_PKT_NUM_CMDQ_V2) -#define BIT_GET_PKT_NUM_CMDQ_V2(x) (((x) >> BIT_SHIFT_PKT_NUM_CMDQ_V2) & BIT_MASK_PKT_NUM_CMDQ_V2) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_RADDR_RD BIT(7) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_TXDMA_ERR_HANDLE_REQ BIT(7) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_PKT_NUM 23 -#define BIT_MASK_PKT_NUM 0x1ff -#define BIT_PKT_NUM(x) (((x) & BIT_MASK_PKT_NUM) << BIT_SHIFT_PKT_NUM) -#define BIT_GET_PKT_NUM(x) (((x) >> BIT_SHIFT_PKT_NUM) & BIT_MASK_PKT_NUM) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_MUL_TAG BIT(6) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_TXDMA_ERROR_PS BIT(6) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_QUEUEAC_CMDQ_V1 23 -#define BIT_MASK_QUEUEAC_CMDQ_V1 0x3 -#define BIT_QUEUEAC_CMDQ_V1(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1) -#define BIT_GET_QUEUEAC_CMDQ_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_L1OFF_PWR_OFF_EN BIT(6) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ -#define BIT_TIDEMPTY_CMDQ_V1 BIT(22) +#define BIT_EN_EARLY_MODE BIT(5) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_TXDMA_STUCK_ERR_HANDLE BIT(5) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_CMDQ 16 -#define BIT_MASK_TAIL_PKT_CMDQ 0xff -#define BIT_TAIL_PKT_CMDQ(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ) << BIT_SHIFT_TAIL_PKT_CMDQ) -#define BIT_GET_TAIL_PKT_CMDQ(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ) & BIT_MASK_TAIL_PKT_CMDQ) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_L0S_LINK_OFF BIT(4) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_TXDMA_RTN_ERR_HANDLE BIT(4) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11 -#define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff -#define BIT_TAIL_PKT_CMDQ_V2(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2) -#define BIT_GET_TAIL_PKT_CMDQ_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_ACT_LINK_OFF BIT(3) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_RXDMA_ERR_HANDLE_REQ BIT(3) -#define BIT_SHIFT_PKT_NUM_CMDQ 8 -#define BIT_MASK_PKT_NUM_CMDQ 0xff -#define BIT_PKT_NUM_CMDQ(x) (((x) & BIT_MASK_PKT_NUM_CMDQ) << BIT_SHIFT_PKT_NUM_CMDQ) -#define BIT_GET_PKT_NUM_CMDQ(x) (((x) >> BIT_SHIFT_PKT_NUM_CMDQ) & BIT_MASK_PKT_NUM_CMDQ) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_CMDQ 0 -#define BIT_MASK_HEAD_PKT_CMDQ 0xff -#define BIT_HEAD_PKT_CMDQ(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ) << BIT_SHIFT_HEAD_PKT_CMDQ) -#define BIT_GET_HEAD_PKT_CMDQ(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ) & BIT_MASK_HEAD_PKT_CMDQ) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_SLOW_MAC_TX BIT(2) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_RXDMA_ERROR_PS BIT(2) -/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0 -#define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff -#define BIT_HEAD_PKT_CMDQ_V1(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1) -#define BIT_GET_HEAD_PKT_CMDQ_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1) +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ +#define BIT_EN_SLOW_MAC_RX BIT(1) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_EN_RXDMA_STUCK_ERR_HANDLE BIT(1) +#define BIT_EN_SLOW_MAC_HW BIT(0) +#define BIT_EN_RXDMA_RTN_ERR_HANDLE BIT(0) +#endif -/* 2 REG_Q4_INFO (Offset 0x0468) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q0_INFO (Offset 0x0400) */ -#define BIT_SHIFT_QUEUEMACID_Q4_V1 25 -#define BIT_MASK_QUEUEMACID_Q4_V1 0x7f -#define BIT_QUEUEMACID_Q4_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1) -#define BIT_GET_QUEUEMACID_Q4_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1) +#define BIT_SHIFT_QUEUEMACID_Q0_V1 25 +#define BIT_MASK_QUEUEMACID_Q0_V1 0x7f +#define BIT_QUEUEMACID_Q0_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1) +#define BITS_QUEUEMACID_Q0_V1 \ + (BIT_MASK_QUEUEMACID_Q0_V1 << BIT_SHIFT_QUEUEMACID_Q0_V1) +#define BIT_CLEAR_QUEUEMACID_Q0_V1(x) ((x) & (~BITS_QUEUEMACID_Q0_V1)) +#define BIT_GET_QUEUEMACID_Q0_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1) +#define BIT_SET_QUEUEMACID_Q0_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q0_V1(x) | BIT_QUEUEMACID_Q0_V1(v)) +#endif -#define BIT_SHIFT_QUEUEAC_Q4_V1 23 -#define BIT_MASK_QUEUEAC_Q4_V1 0x3 -#define BIT_QUEUEAC_Q4_V1(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1) -#define BIT_GET_QUEUEAC_Q4_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1) +#if (HALMAC_8198F_SUPPORT) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ -#endif +#define BIT_SHIFT_QUEUEMACID 25 +#define BIT_MASK_QUEUEMACID 0x7f +#define BIT_QUEUEMACID(x) (((x) & BIT_MASK_QUEUEMACID) << BIT_SHIFT_QUEUEMACID) +#define BITS_QUEUEMACID (BIT_MASK_QUEUEMACID << BIT_SHIFT_QUEUEMACID) +#define BIT_CLEAR_QUEUEMACID(x) ((x) & (~BITS_QUEUEMACID)) +#define BIT_GET_QUEUEMACID(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID) & BIT_MASK_QUEUEMACID) +#define BIT_SET_QUEUEMACID(x, v) (BIT_CLEAR_QUEUEMACID(x) | BIT_QUEUEMACID(v)) +#define BIT_DONE BIT(24) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_Q4_INFO (Offset 0x0468) */ +/* 2 REG_Q0_INFO (Offset 0x0400) */ -#define BIT_TIDEMPTY_Q4_V1 BIT(22) +#define BIT_SHIFT_QUEUEAC_Q0_V1 23 +#define BIT_MASK_QUEUEAC_Q0_V1 0x3 +#define BIT_QUEUEAC_Q0_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1) +#define BITS_QUEUEAC_Q0_V1 (BIT_MASK_QUEUEAC_Q0_V1 << BIT_SHIFT_QUEUEAC_Q0_V1) +#define BIT_CLEAR_QUEUEAC_Q0_V1(x) ((x) & (~BITS_QUEUEAC_Q0_V1)) +#define BIT_GET_QUEUEAC_Q0_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1) +#define BIT_SET_QUEUEAC_Q0_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q0_V1(x) | BIT_QUEUEAC_Q0_V1(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ +#define BIT_SHIFT_QUEUEAC 23 +#define BIT_MASK_QUEUEAC 0x3 +#define BIT_QUEUEAC(x) (((x) & BIT_MASK_QUEUEAC) << BIT_SHIFT_QUEUEAC) +#define BITS_QUEUEAC (BIT_MASK_QUEUEAC << BIT_SHIFT_QUEUEAC) +#define BIT_CLEAR_QUEUEAC(x) ((x) & (~BITS_QUEUEAC)) +#define BIT_GET_QUEUEAC(x) (((x) >> BIT_SHIFT_QUEUEAC) & BIT_MASK_QUEUEAC) +#define BIT_SET_QUEUEAC(x, v) (BIT_CLEAR_QUEUEAC(x) | BIT_QUEUEAC(v)) -/* 2 REG_Q4_INFO (Offset 0x0468) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q4_V1 15 -#define BIT_MASK_TAIL_PKT_Q4_V1 0xff -#define BIT_TAIL_PKT_Q4_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V1) << BIT_SHIFT_TAIL_PKT_Q4_V1) -#define BIT_GET_TAIL_PKT_Q4_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V1) & BIT_MASK_TAIL_PKT_Q4_V1) +/* 2 REG_Q0_INFO (Offset 0x0400) */ +#define BIT_TIDEMPTY_Q0_V1 BIT(22) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ +#define BIT_TIDEMPTY BIT(22) -/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_ACCWBITEN 20 +#define BIT_MASK_ACCWBITEN 0xf +#define BIT_ACCWBITEN(x) (((x) & BIT_MASK_ACCWBITEN) << BIT_SHIFT_ACCWBITEN) +#define BITS_ACCWBITEN (BIT_MASK_ACCWBITEN << BIT_SHIFT_ACCWBITEN) +#define BIT_CLEAR_ACCWBITEN(x) ((x) & (~BITS_ACCWBITEN)) +#define BIT_GET_ACCWBITEN(x) (((x) >> BIT_SHIFT_ACCWBITEN) & BIT_MASK_ACCWBITEN) +#define BIT_SET_ACCWBITEN(x, v) (BIT_CLEAR_ACCWBITEN(x) | BIT_ACCWBITEN(v)) +#define BIT_BCNQ_EMPTY_V1 BIT(19) +#define BIT_HIQ_EMPTY_V1 BIT(18) +#define BIT_MQQ_EMPTY_V1 BIT(17) -#define BIT_SHIFT_TAIL_PKT_Q4_V2 11 -#define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff -#define BIT_TAIL_PKT_Q4_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2) -#define BIT_GET_TAIL_PKT_Q4_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2) +#define BIT_SHIFT_COL_CNT 16 +#define BIT_MASK_COL_CNT 0xf +#define BIT_COL_CNT(x) (((x) & BIT_MASK_COL_CNT) << BIT_SHIFT_COL_CNT) +#define BITS_COL_CNT (BIT_MASK_COL_CNT << BIT_SHIFT_COL_CNT) +#define BIT_CLEAR_COL_CNT(x) ((x) & (~BITS_COL_CNT)) +#define BIT_GET_COL_CNT(x) (((x) >> BIT_SHIFT_COL_CNT) & BIT_MASK_COL_CNT) +#define BIT_SET_COL_CNT(x, v) (BIT_CLEAR_COL_CNT(x) | BIT_COL_CNT(v)) +#define BIT_CPU_MGT_EMPTY BIT(16) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q0_INFO (Offset 0x0400) */ -/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_TAIL_PKT_Q0_V1 15 +#define BIT_MASK_TAIL_PKT_Q0_V1 0xff +#define BIT_TAIL_PKT_Q0_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V1) << BIT_SHIFT_TAIL_PKT_Q0_V1) +#define BITS_TAIL_PKT_Q0_V1 \ + (BIT_MASK_TAIL_PKT_Q0_V1 << BIT_SHIFT_TAIL_PKT_Q0_V1) +#define BIT_CLEAR_TAIL_PKT_Q0_V1(x) ((x) & (~BITS_TAIL_PKT_Q0_V1)) +#define BIT_GET_TAIL_PKT_Q0_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V1) & BIT_MASK_TAIL_PKT_Q0_V1) +#define BIT_SET_TAIL_PKT_Q0_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V1(x) | BIT_TAIL_PKT_Q0_V1(v)) +#endif -#define BIT_SHIFT_PKT_NUM_Q4_V1 8 -#define BIT_MASK_PKT_NUM_Q4_V1 0x7f -#define BIT_PKT_NUM_Q4_V1(x) (((x) & BIT_MASK_PKT_NUM_Q4_V1) << BIT_SHIFT_PKT_NUM_Q4_V1) -#define BIT_GET_PKT_NUM_Q4_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q4_V1) & BIT_MASK_PKT_NUM_Q4_V1) +#if (HALMAC_8198F_SUPPORT) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ -#define BIT_SHIFT_HEAD_PKT_Q4 0 -#define BIT_MASK_HEAD_PKT_Q4 0xff -#define BIT_HEAD_PKT_Q4(x) (((x) & BIT_MASK_HEAD_PKT_Q4) << BIT_SHIFT_HEAD_PKT_Q4) -#define BIT_GET_HEAD_PKT_Q4(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4) & BIT_MASK_HEAD_PKT_Q4) +#define BIT_AC_MACID_NOT_SAME BIT(15) +#define BIT_SHIFT_GROUP_TABLE_ID 12 +#define BIT_MASK_GROUP_TABLE_ID 0x7 +#define BIT_GROUP_TABLE_ID(x) \ + (((x) & BIT_MASK_GROUP_TABLE_ID) << BIT_SHIFT_GROUP_TABLE_ID) +#define BITS_GROUP_TABLE_ID \ + (BIT_MASK_GROUP_TABLE_ID << BIT_SHIFT_GROUP_TABLE_ID) +#define BIT_CLEAR_GROUP_TABLE_ID(x) ((x) & (~BITS_GROUP_TABLE_ID)) +#define BIT_GET_GROUP_TABLE_ID(x) \ + (((x) >> BIT_SHIFT_GROUP_TABLE_ID) & BIT_MASK_GROUP_TABLE_ID) +#define BIT_SET_GROUP_TABLE_ID(x, v) \ + (BIT_CLEAR_GROUP_TABLE_ID(x) | BIT_GROUP_TABLE_ID(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q0_INFO (Offset 0x0400) */ +#define BIT_SHIFT_TAIL_PKT_Q0_V2 11 +#define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff +#define BIT_TAIL_PKT_Q0_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2) +#define BITS_TAIL_PKT_Q0_V2 \ + (BIT_MASK_TAIL_PKT_Q0_V2 << BIT_SHIFT_TAIL_PKT_Q0_V2) +#define BIT_CLEAR_TAIL_PKT_Q0_V2(x) ((x) & (~BITS_TAIL_PKT_Q0_V2)) +#define BIT_GET_TAIL_PKT_Q0_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2) +#define BIT_SET_TAIL_PKT_Q0_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V2(x) | BIT_TAIL_PKT_Q0_V2(v)) -/* 2 REG_Q4_INFO (Offset 0x0468) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q4_V1 0 -#define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff -#define BIT_HEAD_PKT_Q4_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1) -#define BIT_GET_HEAD_PKT_Q4_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ +#define BIT_SHIFT_TAIL_PKT 11 +#define BIT_MASK_TAIL_PKT 0x7ff +#define BIT_TAIL_PKT(x) (((x) & BIT_MASK_TAIL_PKT) << BIT_SHIFT_TAIL_PKT) +#define BITS_TAIL_PKT (BIT_MASK_TAIL_PKT << BIT_SHIFT_TAIL_PKT) +#define BIT_CLEAR_TAIL_PKT(x) ((x) & (~BITS_TAIL_PKT)) +#define BIT_GET_TAIL_PKT(x) (((x) >> BIT_SHIFT_TAIL_PKT) & BIT_MASK_TAIL_PKT) +#define BIT_SET_TAIL_PKT(x, v) (BIT_CLEAR_TAIL_PKT(x) | BIT_TAIL_PKT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q0_INFO (Offset 0x0400) */ +#define BIT_SHIFT_PKT_NUM_Q0_V1 8 +#define BIT_MASK_PKT_NUM_Q0_V1 0x7f +#define BIT_PKT_NUM_Q0_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q0_V1) << BIT_SHIFT_PKT_NUM_Q0_V1) +#define BITS_PKT_NUM_Q0_V1 (BIT_MASK_PKT_NUM_Q0_V1 << BIT_SHIFT_PKT_NUM_Q0_V1) +#define BIT_CLEAR_PKT_NUM_Q0_V1(x) ((x) & (~BITS_PKT_NUM_Q0_V1)) +#define BIT_GET_PKT_NUM_Q0_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q0_V1) & BIT_MASK_PKT_NUM_Q0_V1) +#define BIT_SET_PKT_NUM_Q0_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q0_V1(x) | BIT_PKT_NUM_Q0_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q0 0 +#define BIT_MASK_HEAD_PKT_Q0 0xff +#define BIT_HEAD_PKT_Q0(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0) << BIT_SHIFT_HEAD_PKT_Q0) +#define BITS_HEAD_PKT_Q0 (BIT_MASK_HEAD_PKT_Q0 << BIT_SHIFT_HEAD_PKT_Q0) +#define BIT_CLEAR_HEAD_PKT_Q0(x) ((x) & (~BITS_HEAD_PKT_Q0)) +#define BIT_GET_HEAD_PKT_Q0(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0) & BIT_MASK_HEAD_PKT_Q0) +#define BIT_SET_HEAD_PKT_Q0(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0(x) | BIT_HEAD_PKT_Q0(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +/* 2 REG_Q0_INFO (Offset 0x0400) */ +#define BIT_SHIFT_HEAD_PKT_Q0_V1 0 +#define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff +#define BIT_HEAD_PKT_Q0_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1) +#define BITS_HEAD_PKT_Q0_V1 \ + (BIT_MASK_HEAD_PKT_Q0_V1 << BIT_SHIFT_HEAD_PKT_Q0_V1) +#define BIT_CLEAR_HEAD_PKT_Q0_V1(x) ((x) & (~BITS_HEAD_PKT_Q0_V1)) +#define BIT_GET_HEAD_PKT_Q0_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1) +#define BIT_SET_HEAD_PKT_Q0_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0_V1(x) | BIT_HEAD_PKT_Q0_V1(v)) -#define BIT_SHIFT_QUEUEMACID_Q5_V1 25 -#define BIT_MASK_QUEUEMACID_Q5_V1 0x7f -#define BIT_QUEUEMACID_Q5_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1) -#define BIT_GET_QUEUEMACID_Q5_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_QUEUEAC_Q5_V1 23 -#define BIT_MASK_QUEUEAC_Q5_V1 0x3 -#define BIT_QUEUEAC_Q5_V1(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1) -#define BIT_GET_QUEUEAC_Q5_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1) +/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */ +#define BIT_SHIFT_HEAD_PKT 0 +#define BIT_MASK_HEAD_PKT 0x7ff +#define BIT_HEAD_PKT(x) (((x) & BIT_MASK_HEAD_PKT) << BIT_SHIFT_HEAD_PKT) +#define BITS_HEAD_PKT (BIT_MASK_HEAD_PKT << BIT_SHIFT_HEAD_PKT) +#define BIT_CLEAR_HEAD_PKT(x) ((x) & (~BITS_HEAD_PKT)) +#define BIT_GET_HEAD_PKT(x) (((x) >> BIT_SHIFT_HEAD_PKT) & BIT_MASK_HEAD_PKT) +#define BIT_SET_HEAD_PKT(x, v) (BIT_CLEAR_HEAD_PKT(x) | BIT_HEAD_PKT(v)) -#endif +#define BIT_SHIFT_PKT_NUMBER 0 +#define BIT_MASK_PKT_NUMBER 0xfff +#define BIT_PKT_NUMBER(x) (((x) & BIT_MASK_PKT_NUMBER) << BIT_SHIFT_PKT_NUMBER) +#define BITS_PKT_NUMBER (BIT_MASK_PKT_NUMBER << BIT_SHIFT_PKT_NUMBER) +#define BIT_CLEAR_PKT_NUMBER(x) ((x) & (~BITS_PKT_NUMBER)) +#define BIT_GET_PKT_NUMBER(x) \ + (((x) >> BIT_SHIFT_PKT_NUMBER) & BIT_MASK_PKT_NUMBER) +#define BIT_SET_PKT_NUMBER(x, v) (BIT_CLEAR_PKT_NUMBER(x) | BIT_PKT_NUMBER(v)) +#define BIT_SHIFT_ACCW 0 +#define BIT_MASK_ACCW 0x3ff +#define BIT_ACCW(x) (((x) & BIT_MASK_ACCW) << BIT_SHIFT_ACCW) +#define BITS_ACCW (BIT_MASK_ACCW << BIT_SHIFT_ACCW) +#define BIT_CLEAR_ACCW(x) ((x) & (~BITS_ACCW)) +#define BIT_GET_ACCW(x) (((x) >> BIT_SHIFT_ACCW) & BIT_MASK_ACCW) +#define BIT_SET_ACCW(x, v) (BIT_CLEAR_ACCW(x) | BIT_ACCW(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +/* 2 REG_QUEUELIST_INFO0 (Offset 0x0400) */ -#define BIT_TIDEMPTY_Q5_V1 BIT(22) +#define BIT_SHIFT_QINFO0 0 +#define BIT_MASK_QINFO0 0xffffffffL +#define BIT_QINFO0(x) (((x) & BIT_MASK_QINFO0) << BIT_SHIFT_QINFO0) +#define BITS_QINFO0 (BIT_MASK_QINFO0 << BIT_SHIFT_QINFO0) +#define BIT_CLEAR_QINFO0(x) ((x) & (~BITS_QINFO0)) +#define BIT_GET_QINFO0(x) (((x) >> BIT_SHIFT_QINFO0) & BIT_MASK_QINFO0) +#define BIT_SET_QINFO0(x, v) (BIT_CLEAR_QINFO0(x) | BIT_QINFO0(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q1_INFO (Offset 0x0404) */ +#define BIT_SHIFT_QUEUEMACID_Q1_V1 25 +#define BIT_MASK_QUEUEMACID_Q1_V1 0x7f +#define BIT_QUEUEMACID_Q1_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1) +#define BITS_QUEUEMACID_Q1_V1 \ + (BIT_MASK_QUEUEMACID_Q1_V1 << BIT_SHIFT_QUEUEMACID_Q1_V1) +#define BIT_CLEAR_QUEUEMACID_Q1_V1(x) ((x) & (~BITS_QUEUEMACID_Q1_V1)) +#define BIT_GET_QUEUEMACID_Q1_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1) +#define BIT_SET_QUEUEMACID_Q1_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q1_V1(x) | BIT_QUEUEMACID_Q1_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q1_V1 23 +#define BIT_MASK_QUEUEAC_Q1_V1 0x3 +#define BIT_QUEUEAC_Q1_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1) +#define BITS_QUEUEAC_Q1_V1 (BIT_MASK_QUEUEAC_Q1_V1 << BIT_SHIFT_QUEUEAC_Q1_V1) +#define BIT_CLEAR_QUEUEAC_Q1_V1(x) ((x) & (~BITS_QUEUEAC_Q1_V1)) +#define BIT_GET_QUEUEAC_Q1_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1) +#define BIT_SET_QUEUEAC_Q1_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q1_V1(x) | BIT_QUEUEAC_Q1_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +/* 2 REG_Q1_INFO (Offset 0x0404) */ + +#define BIT_TIDEMPTY_Q1_V1 BIT(22) + +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q5_V1 15 -#define BIT_MASK_TAIL_PKT_Q5_V1 0xff -#define BIT_TAIL_PKT_Q5_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V1) << BIT_SHIFT_TAIL_PKT_Q5_V1) -#define BIT_GET_TAIL_PKT_Q5_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V1) & BIT_MASK_TAIL_PKT_Q5_V1) +/* 2 REG_Q1_INFO (Offset 0x0404) */ +#define BIT_SHIFT_TAIL_PKT_Q1_V1 15 +#define BIT_MASK_TAIL_PKT_Q1_V1 0xff +#define BIT_TAIL_PKT_Q1_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V1) << BIT_SHIFT_TAIL_PKT_Q1_V1) +#define BITS_TAIL_PKT_Q1_V1 \ + (BIT_MASK_TAIL_PKT_Q1_V1 << BIT_SHIFT_TAIL_PKT_Q1_V1) +#define BIT_CLEAR_TAIL_PKT_Q1_V1(x) ((x) & (~BITS_TAIL_PKT_Q1_V1)) +#define BIT_GET_TAIL_PKT_Q1_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V1) & BIT_MASK_TAIL_PKT_Q1_V1) +#define BIT_SET_TAIL_PKT_Q1_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V1(x) | BIT_TAIL_PKT_Q1_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q1_INFO (Offset 0x0404) */ +#define BIT_SHIFT_TAIL_PKT_Q1_V2 11 +#define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff +#define BIT_TAIL_PKT_Q1_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2) +#define BITS_TAIL_PKT_Q1_V2 \ + (BIT_MASK_TAIL_PKT_Q1_V2 << BIT_SHIFT_TAIL_PKT_Q1_V2) +#define BIT_CLEAR_TAIL_PKT_Q1_V2(x) ((x) & (~BITS_TAIL_PKT_Q1_V2)) +#define BIT_GET_TAIL_PKT_Q1_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2) +#define BIT_SET_TAIL_PKT_Q1_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V2(x) | BIT_TAIL_PKT_Q1_V2(v)) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_Q1_INFO (Offset 0x0404) */ +#define BIT_SHIFT_PKT_NUM_Q1_V1 8 +#define BIT_MASK_PKT_NUM_Q1_V1 0x7f +#define BIT_PKT_NUM_Q1_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q1_V1) << BIT_SHIFT_PKT_NUM_Q1_V1) +#define BITS_PKT_NUM_Q1_V1 (BIT_MASK_PKT_NUM_Q1_V1 << BIT_SHIFT_PKT_NUM_Q1_V1) +#define BIT_CLEAR_PKT_NUM_Q1_V1(x) ((x) & (~BITS_PKT_NUM_Q1_V1)) +#define BIT_GET_PKT_NUM_Q1_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q1_V1) & BIT_MASK_PKT_NUM_Q1_V1) +#define BIT_SET_PKT_NUM_Q1_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q1_V1(x) | BIT_PKT_NUM_Q1_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q1 0 +#define BIT_MASK_HEAD_PKT_Q1 0xff +#define BIT_HEAD_PKT_Q1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1) << BIT_SHIFT_HEAD_PKT_Q1) +#define BITS_HEAD_PKT_Q1 (BIT_MASK_HEAD_PKT_Q1 << BIT_SHIFT_HEAD_PKT_Q1) +#define BIT_CLEAR_HEAD_PKT_Q1(x) ((x) & (~BITS_HEAD_PKT_Q1)) +#define BIT_GET_HEAD_PKT_Q1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1) & BIT_MASK_HEAD_PKT_Q1) +#define BIT_SET_HEAD_PKT_Q1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1(x) | BIT_HEAD_PKT_Q1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q5_V2 11 -#define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff -#define BIT_TAIL_PKT_Q5_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2) -#define BIT_GET_TAIL_PKT_Q5_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2) +/* 2 REG_Q1_INFO (Offset 0x0404) */ +#define BIT_SHIFT_HEAD_PKT_Q1_V1 0 +#define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff +#define BIT_HEAD_PKT_Q1_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1) +#define BITS_HEAD_PKT_Q1_V1 \ + (BIT_MASK_HEAD_PKT_Q1_V1 << BIT_SHIFT_HEAD_PKT_Q1_V1) +#define BIT_CLEAR_HEAD_PKT_Q1_V1(x) ((x) & (~BITS_HEAD_PKT_Q1_V1)) +#define BIT_GET_HEAD_PKT_Q1_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1) +#define BIT_SET_HEAD_PKT_Q1_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1_V1(x) | BIT_HEAD_PKT_Q1_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUELIST_INFO1 (Offset 0x0404) */ +#define BIT_SHIFT_QINFO1 0 +#define BIT_MASK_QINFO1 0xffffffffL +#define BIT_QINFO1(x) (((x) & BIT_MASK_QINFO1) << BIT_SHIFT_QINFO1) +#define BITS_QINFO1 (BIT_MASK_QINFO1 << BIT_SHIFT_QINFO1) +#define BIT_CLEAR_QINFO1(x) ((x) & (~BITS_QINFO1)) +#define BIT_GET_QINFO1(x) (((x) >> BIT_SHIFT_QINFO1) & BIT_MASK_QINFO1) +#define BIT_SET_QINFO1(x, v) (BIT_CLEAR_QINFO1(x) | BIT_QINFO1(v)) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKT_NUM_Q5_V1 8 -#define BIT_MASK_PKT_NUM_Q5_V1 0x7f -#define BIT_PKT_NUM_Q5_V1(x) (((x) & BIT_MASK_PKT_NUM_Q5_V1) << BIT_SHIFT_PKT_NUM_Q5_V1) -#define BIT_GET_PKT_NUM_Q5_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q5_V1) & BIT_MASK_PKT_NUM_Q5_V1) +/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_SHIFT_QUEUEMACID_Q2_V1 25 +#define BIT_MASK_QUEUEMACID_Q2_V1 0x7f +#define BIT_QUEUEMACID_Q2_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1) +#define BITS_QUEUEMACID_Q2_V1 \ + (BIT_MASK_QUEUEMACID_Q2_V1 << BIT_SHIFT_QUEUEMACID_Q2_V1) +#define BIT_CLEAR_QUEUEMACID_Q2_V1(x) ((x) & (~BITS_QUEUEMACID_Q2_V1)) +#define BIT_GET_QUEUEMACID_Q2_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1) +#define BIT_SET_QUEUEMACID_Q2_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q2_V1(x) | BIT_QUEUEMACID_Q2_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q2_V1 23 +#define BIT_MASK_QUEUEAC_Q2_V1 0x3 +#define BIT_QUEUEAC_Q2_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1) +#define BITS_QUEUEAC_Q2_V1 (BIT_MASK_QUEUEAC_Q2_V1 << BIT_SHIFT_QUEUEAC_Q2_V1) +#define BIT_CLEAR_QUEUEAC_Q2_V1(x) ((x) & (~BITS_QUEUEAC_Q2_V1)) +#define BIT_GET_QUEUEAC_Q2_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1) +#define BIT_SET_QUEUEAC_Q2_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q2_V1(x) | BIT_QUEUEAC_Q2_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q5 0 -#define BIT_MASK_HEAD_PKT_Q5 0xff -#define BIT_HEAD_PKT_Q5(x) (((x) & BIT_MASK_HEAD_PKT_Q5) << BIT_SHIFT_HEAD_PKT_Q5) -#define BIT_GET_HEAD_PKT_Q5(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5) & BIT_MASK_HEAD_PKT_Q5) +/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_TIDEMPTY_Q2_V1 BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_SHIFT_TAIL_PKT_Q2_V1 15 +#define BIT_MASK_TAIL_PKT_Q2_V1 0xff +#define BIT_TAIL_PKT_Q2_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V1) << BIT_SHIFT_TAIL_PKT_Q2_V1) +#define BITS_TAIL_PKT_Q2_V1 \ + (BIT_MASK_TAIL_PKT_Q2_V1 << BIT_SHIFT_TAIL_PKT_Q2_V1) +#define BIT_CLEAR_TAIL_PKT_Q2_V1(x) ((x) & (~BITS_TAIL_PKT_Q2_V1)) +#define BIT_GET_TAIL_PKT_Q2_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V1) & BIT_MASK_TAIL_PKT_Q2_V1) +#define BIT_SET_TAIL_PKT_Q2_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V1(x) | BIT_TAIL_PKT_Q2_V1(v)) -/* 2 REG_Q5_INFO (Offset 0x046C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q5_V1 0 -#define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff -#define BIT_HEAD_PKT_Q5_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1) -#define BIT_GET_HEAD_PKT_Q5_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1) +/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_SHIFT_TAIL_PKT_Q2_V2 11 +#define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff +#define BIT_TAIL_PKT_Q2_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2) +#define BITS_TAIL_PKT_Q2_V2 \ + (BIT_MASK_TAIL_PKT_Q2_V2 << BIT_SHIFT_TAIL_PKT_Q2_V2) +#define BIT_CLEAR_TAIL_PKT_Q2_V2(x) ((x) & (~BITS_TAIL_PKT_Q2_V2)) +#define BIT_GET_TAIL_PKT_Q2_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2) +#define BIT_SET_TAIL_PKT_Q2_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V2(x) | BIT_TAIL_PKT_Q2_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_SHIFT_PKT_NUM_Q2_V1 8 +#define BIT_MASK_PKT_NUM_Q2_V1 0x7f +#define BIT_PKT_NUM_Q2_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q2_V1) << BIT_SHIFT_PKT_NUM_Q2_V1) +#define BITS_PKT_NUM_Q2_V1 (BIT_MASK_PKT_NUM_Q2_V1 << BIT_SHIFT_PKT_NUM_Q2_V1) +#define BIT_CLEAR_PKT_NUM_Q2_V1(x) ((x) & (~BITS_PKT_NUM_Q2_V1)) +#define BIT_GET_PKT_NUM_Q2_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q2_V1) & BIT_MASK_PKT_NUM_Q2_V1) +#define BIT_SET_PKT_NUM_Q2_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q2_V1(x) | BIT_PKT_NUM_Q2_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q2 0 +#define BIT_MASK_HEAD_PKT_Q2 0xff +#define BIT_HEAD_PKT_Q2(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2) << BIT_SHIFT_HEAD_PKT_Q2) +#define BITS_HEAD_PKT_Q2 (BIT_MASK_HEAD_PKT_Q2 << BIT_SHIFT_HEAD_PKT_Q2) +#define BIT_CLEAR_HEAD_PKT_Q2(x) ((x) & (~BITS_HEAD_PKT_Q2)) +#define BIT_GET_HEAD_PKT_Q2(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2) & BIT_MASK_HEAD_PKT_Q2) +#define BIT_SET_HEAD_PKT_Q2(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2(x) | BIT_HEAD_PKT_Q2(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_Q6_INFO (Offset 0x0470) */ +/* 2 REG_Q2_INFO (Offset 0x0408) */ +#define BIT_SHIFT_HEAD_PKT_Q2_V1 0 +#define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff +#define BIT_HEAD_PKT_Q2_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1) +#define BITS_HEAD_PKT_Q2_V1 \ + (BIT_MASK_HEAD_PKT_Q2_V1 << BIT_SHIFT_HEAD_PKT_Q2_V1) +#define BIT_CLEAR_HEAD_PKT_Q2_V1(x) ((x) & (~BITS_HEAD_PKT_Q2_V1)) +#define BIT_GET_HEAD_PKT_Q2_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1) +#define BIT_SET_HEAD_PKT_Q2_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2_V1(x) | BIT_HEAD_PKT_Q2_V1(v)) -#define BIT_SHIFT_QUEUEMACID_Q6_V1 25 -#define BIT_MASK_QUEUEMACID_Q6_V1 0x7f -#define BIT_QUEUEMACID_Q6_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1) -#define BIT_GET_QUEUEMACID_Q6_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_QUEUEAC_Q6_V1 23 -#define BIT_MASK_QUEUEAC_Q6_V1 0x3 -#define BIT_QUEUEAC_Q6_V1(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1) -#define BIT_GET_QUEUEAC_Q6_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1) +/* 2 REG_QUEUELIST_INFO2 (Offset 0x0408) */ +#define BIT_SHIFT_QINFO2 0 +#define BIT_MASK_QINFO2 0xffffffffL +#define BIT_QINFO2(x) (((x) & BIT_MASK_QINFO2) << BIT_SHIFT_QINFO2) +#define BITS_QINFO2 (BIT_MASK_QINFO2 << BIT_SHIFT_QINFO2) +#define BIT_CLEAR_QINFO2(x) ((x) & (~BITS_QINFO2)) +#define BIT_GET_QINFO2(x) (((x) >> BIT_SHIFT_QINFO2) & BIT_MASK_QINFO2) +#define BIT_SET_QINFO2(x, v) (BIT_CLEAR_QINFO2(x) | BIT_QINFO2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q3_INFO (Offset 0x040C) */ +#define BIT_SHIFT_QUEUEMACID_Q3_V1 25 +#define BIT_MASK_QUEUEMACID_Q3_V1 0x7f +#define BIT_QUEUEMACID_Q3_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1) +#define BITS_QUEUEMACID_Q3_V1 \ + (BIT_MASK_QUEUEMACID_Q3_V1 << BIT_SHIFT_QUEUEMACID_Q3_V1) +#define BIT_CLEAR_QUEUEMACID_Q3_V1(x) ((x) & (~BITS_QUEUEMACID_Q3_V1)) +#define BIT_GET_QUEUEMACID_Q3_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1) +#define BIT_SET_QUEUEMACID_Q3_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q3_V1(x) | BIT_QUEUEMACID_Q3_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q3_V1 23 +#define BIT_MASK_QUEUEAC_Q3_V1 0x3 +#define BIT_QUEUEAC_Q3_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1) +#define BITS_QUEUEAC_Q3_V1 (BIT_MASK_QUEUEAC_Q3_V1 << BIT_SHIFT_QUEUEAC_Q3_V1) +#define BIT_CLEAR_QUEUEAC_Q3_V1(x) ((x) & (~BITS_QUEUEAC_Q3_V1)) +#define BIT_GET_QUEUEAC_Q3_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1) +#define BIT_SET_QUEUEAC_Q3_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q3_V1(x) | BIT_QUEUEAC_Q3_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_Q6_INFO (Offset 0x0470) */ +/* 2 REG_Q3_INFO (Offset 0x040C) */ -#define BIT_TIDEMPTY_Q6_V1 BIT(22) +#define BIT_TIDEMPTY_Q3_V1 BIT(22) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q3_INFO (Offset 0x040C) */ -/* 2 REG_Q6_INFO (Offset 0x0470) */ - +#define BIT_SHIFT_TAIL_PKT_Q3_V1 15 +#define BIT_MASK_TAIL_PKT_Q3_V1 0xff +#define BIT_TAIL_PKT_Q3_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V1) << BIT_SHIFT_TAIL_PKT_Q3_V1) +#define BITS_TAIL_PKT_Q3_V1 \ + (BIT_MASK_TAIL_PKT_Q3_V1 << BIT_SHIFT_TAIL_PKT_Q3_V1) +#define BIT_CLEAR_TAIL_PKT_Q3_V1(x) ((x) & (~BITS_TAIL_PKT_Q3_V1)) +#define BIT_GET_TAIL_PKT_Q3_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V1) & BIT_MASK_TAIL_PKT_Q3_V1) +#define BIT_SET_TAIL_PKT_Q3_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V1(x) | BIT_TAIL_PKT_Q3_V1(v)) -#define BIT_SHIFT_TAIL_PKT_Q6_V1 15 -#define BIT_MASK_TAIL_PKT_Q6_V1 0xff -#define BIT_TAIL_PKT_Q6_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V1) << BIT_SHIFT_TAIL_PKT_Q6_V1) -#define BIT_GET_TAIL_PKT_Q6_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V1) & BIT_MASK_TAIL_PKT_Q6_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_Q3_INFO (Offset 0x040C) */ +#define BIT_SHIFT_TAIL_PKT_Q3_V2 11 +#define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff +#define BIT_TAIL_PKT_Q3_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2) +#define BITS_TAIL_PKT_Q3_V2 \ + (BIT_MASK_TAIL_PKT_Q3_V2 << BIT_SHIFT_TAIL_PKT_Q3_V2) +#define BIT_CLEAR_TAIL_PKT_Q3_V2(x) ((x) & (~BITS_TAIL_PKT_Q3_V2)) +#define BIT_GET_TAIL_PKT_Q3_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2) +#define BIT_SET_TAIL_PKT_Q3_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V2(x) | BIT_TAIL_PKT_Q3_V2(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_Q6_INFO (Offset 0x0470) */ +/* 2 REG_Q3_INFO (Offset 0x040C) */ +#define BIT_SHIFT_PKT_NUM_Q3_V1 8 +#define BIT_MASK_PKT_NUM_Q3_V1 0x7f +#define BIT_PKT_NUM_Q3_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q3_V1) << BIT_SHIFT_PKT_NUM_Q3_V1) +#define BITS_PKT_NUM_Q3_V1 (BIT_MASK_PKT_NUM_Q3_V1 << BIT_SHIFT_PKT_NUM_Q3_V1) +#define BIT_CLEAR_PKT_NUM_Q3_V1(x) ((x) & (~BITS_PKT_NUM_Q3_V1)) +#define BIT_GET_PKT_NUM_Q3_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q3_V1) & BIT_MASK_PKT_NUM_Q3_V1) +#define BIT_SET_PKT_NUM_Q3_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q3_V1(x) | BIT_PKT_NUM_Q3_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q3 0 +#define BIT_MASK_HEAD_PKT_Q3 0xff +#define BIT_HEAD_PKT_Q3(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3) << BIT_SHIFT_HEAD_PKT_Q3) +#define BITS_HEAD_PKT_Q3 (BIT_MASK_HEAD_PKT_Q3 << BIT_SHIFT_HEAD_PKT_Q3) +#define BIT_CLEAR_HEAD_PKT_Q3(x) ((x) & (~BITS_HEAD_PKT_Q3)) +#define BIT_GET_HEAD_PKT_Q3(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3) & BIT_MASK_HEAD_PKT_Q3) +#define BIT_SET_HEAD_PKT_Q3(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3(x) | BIT_HEAD_PKT_Q3(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q6_V2 11 -#define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff -#define BIT_TAIL_PKT_Q6_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2) -#define BIT_GET_TAIL_PKT_Q6_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2) +/* 2 REG_Q3_INFO (Offset 0x040C) */ +#define BIT_SHIFT_HEAD_PKT_Q3_V1 0 +#define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff +#define BIT_HEAD_PKT_Q3_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1) +#define BITS_HEAD_PKT_Q3_V1 \ + (BIT_MASK_HEAD_PKT_Q3_V1 << BIT_SHIFT_HEAD_PKT_Q3_V1) +#define BIT_CLEAR_HEAD_PKT_Q3_V1(x) ((x) & (~BITS_HEAD_PKT_Q3_V1)) +#define BIT_GET_HEAD_PKT_Q3_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1) +#define BIT_SET_HEAD_PKT_Q3_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3_V1(x) | BIT_HEAD_PKT_Q3_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUELIST_INFO3 (Offset 0x040C) */ +#define BIT_SHIFT_QINFO3 0 +#define BIT_MASK_QINFO3 0xffffffffL +#define BIT_QINFO3(x) (((x) & BIT_MASK_QINFO3) << BIT_SHIFT_QINFO3) +#define BITS_QINFO3 (BIT_MASK_QINFO3 << BIT_SHIFT_QINFO3) +#define BIT_CLEAR_QINFO3(x) ((x) & (~BITS_QINFO3)) +#define BIT_GET_QINFO3(x) (((x) >> BIT_SHIFT_QINFO3) & BIT_MASK_QINFO3) +#define BIT_SET_QINFO3(x, v) (BIT_CLEAR_QINFO3(x) | BIT_QINFO3(v)) -/* 2 REG_Q6_INFO (Offset 0x0470) */ +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_FWCMDQ_EMPTY BIT(31) +#define BIT_MGQ_CPU_EMPTY_V1 BIT(30) +#define BIT_BCNQ_EMPTY_EXTP0 BIT(29) +#define BIT_BCNQ_EMPTY_PORT4 BIT(28) +#define BIT_BCNQ_EMPTY_PORT3 BIT(27) +#define BIT_BCNQ_EMPTY_PORT2 BIT(26) -#define BIT_SHIFT_PKT_NUM_Q6_V1 8 -#define BIT_MASK_PKT_NUM_Q6_V1 0x7f -#define BIT_PKT_NUM_Q6_V1(x) (((x) & BIT_MASK_PKT_NUM_Q6_V1) << BIT_SHIFT_PKT_NUM_Q6_V1) -#define BIT_GET_PKT_NUM_Q6_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q6_V1) & BIT_MASK_PKT_NUM_Q6_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q6 0 -#define BIT_MASK_HEAD_PKT_Q6 0xff -#define BIT_HEAD_PKT_Q6(x) (((x) & BIT_MASK_HEAD_PKT_Q6) << BIT_SHIFT_HEAD_PKT_Q6) -#define BIT_GET_HEAD_PKT_Q6(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6) & BIT_MASK_HEAD_PKT_Q6) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_QUEUEMACID_MGQ_V1 25 +#define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f +#define BIT_QUEUEMACID_MGQ_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1) +#define BITS_QUEUEMACID_MGQ_V1 \ + (BIT_MASK_QUEUEMACID_MGQ_V1 << BIT_SHIFT_QUEUEMACID_MGQ_V1) +#define BIT_CLEAR_QUEUEMACID_MGQ_V1(x) ((x) & (~BITS_QUEUEMACID_MGQ_V1)) +#define BIT_GET_QUEUEMACID_MGQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1) +#define BIT_SET_QUEUEMACID_MGQ_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_MGQ_V1(x) | BIT_QUEUEMACID_MGQ_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_BCNQ_EMPTY_PORT1 BIT(25) +#define BIT_BCNQ_EMPTY_PORT0 BIT(24) -/* 2 REG_Q6_INFO (Offset 0x0470) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q6_V1 0 -#define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff -#define BIT_HEAD_PKT_Q6_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1) -#define BIT_GET_HEAD_PKT_Q6_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_QUEUEAC_MGQ_V1 23 +#define BIT_MASK_QUEUEAC_MGQ_V1 0x3 +#define BIT_QUEUEAC_MGQ_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1) +#define BITS_QUEUEAC_MGQ_V1 \ + (BIT_MASK_QUEUEAC_MGQ_V1 << BIT_SHIFT_QUEUEAC_MGQ_V1) +#define BIT_CLEAR_QUEUEAC_MGQ_V1(x) ((x) & (~BITS_QUEUEAC_MGQ_V1)) +#define BIT_GET_QUEUEAC_MGQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1) +#define BIT_SET_QUEUEAC_MGQ_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_MGQ_V1(x) | BIT_QUEUEAC_MGQ_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_HQQ_EMPTY_V1 BIT(23) -/* 2 REG_Q7_INFO (Offset 0x0474) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_QUEUEMACID_Q7_V1 25 -#define BIT_MASK_QUEUEMACID_Q7_V1 0x7f -#define BIT_QUEUEMACID_Q7_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1) -#define BIT_GET_QUEUEMACID_Q7_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_TIDEMPTY_MGQ_V1 BIT(22) -#define BIT_SHIFT_QUEUEAC_Q7_V1 23 -#define BIT_MASK_QUEUEAC_Q7_V1 0x3 -#define BIT_QUEUEAC_Q7_V1(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1) -#define BIT_GET_QUEUEAC_Q7_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1) +#endif +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_MQQ_EMPTY_V2 BIT(22) +#define BIT_S1_EMPTY BIT(21) +#define BIT_S0_EMPTY BIT(20) +#define BIT_AC19Q_EMPTY BIT(19) +#define BIT_AC18Q_EMPTY BIT(18) +#define BIT_AC17Q_EMPTY BIT(17) +#define BIT_AC16Q_EMPTY BIT(16) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_Q7_INFO (Offset 0x0474) */ +/* 2 REG_MGQ_INFO (Offset 0x0410) */ -#define BIT_TIDEMPTY_Q7_V1 BIT(22) +#define BIT_SHIFT_TAIL_PKT_MGQ_V1 15 +#define BIT_MASK_TAIL_PKT_MGQ_V1 0xff +#define BIT_TAIL_PKT_MGQ_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V1) << BIT_SHIFT_TAIL_PKT_MGQ_V1) +#define BITS_TAIL_PKT_MGQ_V1 \ + (BIT_MASK_TAIL_PKT_MGQ_V1 << BIT_SHIFT_TAIL_PKT_MGQ_V1) +#define BIT_CLEAR_TAIL_PKT_MGQ_V1(x) ((x) & (~BITS_TAIL_PKT_MGQ_V1)) +#define BIT_GET_TAIL_PKT_MGQ_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V1) & BIT_MASK_TAIL_PKT_MGQ_V1) +#define BIT_SET_TAIL_PKT_MGQ_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V1(x) | BIT_TAIL_PKT_MGQ_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_AC15Q_EMPTY BIT(15) +#define BIT_AC14Q_EMPTY BIT(14) +#define BIT_AC13Q_EMPTY BIT(13) +#define BIT_AC12Q_EMPTY BIT(12) +#define BIT_AC11Q_EMPTY BIT(11) -/* 2 REG_Q7_INFO (Offset 0x0474) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q7_V1 15 -#define BIT_MASK_TAIL_PKT_Q7_V1 0xff -#define BIT_TAIL_PKT_Q7_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V1) << BIT_SHIFT_TAIL_PKT_Q7_V1) -#define BIT_GET_TAIL_PKT_Q7_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V1) & BIT_MASK_TAIL_PKT_Q7_V1) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_TAIL_PKT_MGQ_V2 11 +#define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff +#define BIT_TAIL_PKT_MGQ_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2) +#define BITS_TAIL_PKT_MGQ_V2 \ + (BIT_MASK_TAIL_PKT_MGQ_V2 << BIT_SHIFT_TAIL_PKT_MGQ_V2) +#define BIT_CLEAR_TAIL_PKT_MGQ_V2(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2)) +#define BIT_GET_TAIL_PKT_MGQ_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2) +#define BIT_SET_TAIL_PKT_MGQ_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V2(x) | BIT_TAIL_PKT_MGQ_V2(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_AC10Q_EMPTY BIT(10) +#define BIT_AC9Q_EMPTY BIT(9) -/* 2 REG_Q7_INFO (Offset 0x0474) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TAIL_PKT_Q7_V2 11 -#define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff -#define BIT_TAIL_PKT_Q7_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2) -#define BIT_GET_TAIL_PKT_Q7_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_PKT_NUM_MGQ_V1 8 +#define BIT_MASK_PKT_NUM_MGQ_V1 0x7f +#define BIT_PKT_NUM_MGQ_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_MGQ_V1) << BIT_SHIFT_PKT_NUM_MGQ_V1) +#define BITS_PKT_NUM_MGQ_V1 \ + (BIT_MASK_PKT_NUM_MGQ_V1 << BIT_SHIFT_PKT_NUM_MGQ_V1) +#define BIT_CLEAR_PKT_NUM_MGQ_V1(x) ((x) & (~BITS_PKT_NUM_MGQ_V1)) +#define BIT_GET_PKT_NUM_MGQ_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_MGQ_V1) & BIT_MASK_PKT_NUM_MGQ_V1) +#define BIT_SET_PKT_NUM_MGQ_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_MGQ_V1(x) | BIT_PKT_NUM_MGQ_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_Q7_INFO (Offset 0x0474) */ +/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */ +#define BIT_AC8Q_EMPTY BIT(8) -#define BIT_SHIFT_PKT_NUM_Q7_V1 8 -#define BIT_MASK_PKT_NUM_Q7_V1 0x7f -#define BIT_PKT_NUM_Q7_V1(x) (((x) & BIT_MASK_PKT_NUM_Q7_V1) << BIT_SHIFT_PKT_NUM_Q7_V1) -#define BIT_GET_PKT_NUM_Q7_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q7_V1) & BIT_MASK_PKT_NUM_Q7_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q7 0 -#define BIT_MASK_HEAD_PKT_Q7 0xff -#define BIT_HEAD_PKT_Q7(x) (((x) & BIT_MASK_HEAD_PKT_Q7) << BIT_SHIFT_HEAD_PKT_Q7) -#define BIT_GET_HEAD_PKT_Q7(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7) & BIT_MASK_HEAD_PKT_Q7) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_HEAD_PKT_MGQ 0 +#define BIT_MASK_HEAD_PKT_MGQ 0xff +#define BIT_HEAD_PKT_MGQ(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ) << BIT_SHIFT_HEAD_PKT_MGQ) +#define BITS_HEAD_PKT_MGQ (BIT_MASK_HEAD_PKT_MGQ << BIT_SHIFT_HEAD_PKT_MGQ) +#define BIT_CLEAR_HEAD_PKT_MGQ(x) ((x) & (~BITS_HEAD_PKT_MGQ)) +#define BIT_GET_HEAD_PKT_MGQ(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ) & BIT_MASK_HEAD_PKT_MGQ) +#define BIT_SET_HEAD_PKT_MGQ(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ(x) | BIT_HEAD_PKT_MGQ(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MGQ_INFO (Offset 0x0410) */ +#define BIT_SHIFT_HEAD_PKT_MGQ_V1 0 +#define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff +#define BIT_HEAD_PKT_MGQ_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1) +#define BITS_HEAD_PKT_MGQ_V1 \ + (BIT_MASK_HEAD_PKT_MGQ_V1 << BIT_SHIFT_HEAD_PKT_MGQ_V1) +#define BIT_CLEAR_HEAD_PKT_MGQ_V1(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1)) +#define BIT_GET_HEAD_PKT_MGQ_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1) +#define BIT_SET_HEAD_PKT_MGQ_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ_V1(x) | BIT_HEAD_PKT_MGQ_V1(v)) -/* 2 REG_Q7_INFO (Offset 0x0474) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HEAD_PKT_Q7_V1 0 -#define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff -#define BIT_HEAD_PKT_Q7_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1) -#define BIT_GET_HEAD_PKT_Q7_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_QUEUEMACID_HIQ_V1 25 +#define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f +#define BIT_QUEUEMACID_HIQ_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1) +#define BITS_QUEUEMACID_HIQ_V1 \ + (BIT_MASK_QUEUEMACID_HIQ_V1 << BIT_SHIFT_QUEUEMACID_HIQ_V1) +#define BIT_CLEAR_QUEUEMACID_HIQ_V1(x) ((x) & (~BITS_QUEUEMACID_HIQ_V1)) +#define BIT_GET_QUEUEMACID_HIQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1) +#define BIT_SET_QUEUEMACID_HIQ_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_HIQ_V1(x) | BIT_QUEUEMACID_HIQ_V1(v)) -/* 2 REG_WMAC_LBK_BUF_HD_V1 (Offset 0x0478) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0 -#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff -#define BIT_WMAC_LBK_BUF_HEAD_V1(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) -#define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ +#define BIT_SHIFT_QINFO_CTRL 24 +#define BIT_MASK_QINFO_CTRL 0x3f +#define BIT_QINFO_CTRL(x) (((x) & BIT_MASK_QINFO_CTRL) << BIT_SHIFT_QINFO_CTRL) +#define BITS_QINFO_CTRL (BIT_MASK_QINFO_CTRL << BIT_SHIFT_QINFO_CTRL) +#define BIT_CLEAR_QINFO_CTRL(x) ((x) & (~BITS_QINFO_CTRL)) +#define BIT_GET_QINFO_CTRL(x) \ + (((x) >> BIT_SHIFT_QINFO_CTRL) & BIT_MASK_QINFO_CTRL) +#define BIT_SET_QINFO_CTRL(x, v) (BIT_CLEAR_QINFO_CTRL(x) | BIT_QINFO_CTRL(v)) -/* 2 REG_MGQ_BDNY_V1 (Offset 0x047A) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MGQ_PGBNDY_V1 0 -#define BIT_MASK_MGQ_PGBNDY_V1 0xfff -#define BIT_MGQ_PGBNDY_V1(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1) -#define BIT_GET_MGQ_PGBNDY_V1(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_QUEUEAC_HIQ_V1 23 +#define BIT_MASK_QUEUEAC_HIQ_V1 0x3 +#define BIT_QUEUEAC_HIQ_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1) +#define BITS_QUEUEAC_HIQ_V1 \ + (BIT_MASK_QUEUEAC_HIQ_V1 << BIT_SHIFT_QUEUEAC_HIQ_V1) +#define BIT_CLEAR_QUEUEAC_HIQ_V1(x) ((x) & (~BITS_QUEUEAC_HIQ_V1)) +#define BIT_GET_QUEUEAC_HIQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1) +#define BIT_SET_QUEUEAC_HIQ_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_HIQ_V1(x) | BIT_QUEUEAC_HIQ_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_TIDEMPTY_HIQ_V1 BIT(22) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_SPC_READ_PTR 24 -#define BIT_MASK_SPC_READ_PTR 0xf -#define BIT_SPC_READ_PTR(x) (((x) & BIT_MASK_SPC_READ_PTR) << BIT_SHIFT_SPC_READ_PTR) -#define BIT_GET_SPC_READ_PTR(x) (((x) >> BIT_SHIFT_SPC_READ_PTR) & BIT_MASK_SPC_READ_PTR) +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ +#define BIT_SHIFT_QINFO_MODE_BAND 20 +#define BIT_MASK_QINFO_MODE_BAND 0x7 +#define BIT_QINFO_MODE_BAND(x) \ + (((x) & BIT_MASK_QINFO_MODE_BAND) << BIT_SHIFT_QINFO_MODE_BAND) +#define BITS_QINFO_MODE_BAND \ + (BIT_MASK_QINFO_MODE_BAND << BIT_SHIFT_QINFO_MODE_BAND) +#define BIT_CLEAR_QINFO_MODE_BAND(x) ((x) & (~BITS_QINFO_MODE_BAND)) +#define BIT_GET_QINFO_MODE_BAND(x) \ + (((x) >> BIT_SHIFT_QINFO_MODE_BAND) & BIT_MASK_QINFO_MODE_BAND) +#define BIT_SET_QINFO_MODE_BAND(x, v) \ + (BIT_CLEAR_QINFO_MODE_BAND(x) | BIT_QINFO_MODE_BAND(v)) + +#define BIT_ACQ19_ENABLE BIT(19) +#define BIT_ACQ18_ENABLE BIT(18) +#define BIT_ACQ17_ENABLE BIT(17) +#define BIT_ACQ16_ENABLE BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_TAIL_PKT_HIQ_V1 15 +#define BIT_MASK_TAIL_PKT_HIQ_V1 0xff +#define BIT_TAIL_PKT_HIQ_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V1) << BIT_SHIFT_TAIL_PKT_HIQ_V1) +#define BITS_TAIL_PKT_HIQ_V1 \ + (BIT_MASK_TAIL_PKT_HIQ_V1 << BIT_SHIFT_TAIL_PKT_HIQ_V1) +#define BIT_CLEAR_TAIL_PKT_HIQ_V1(x) ((x) & (~BITS_TAIL_PKT_HIQ_V1)) +#define BIT_GET_TAIL_PKT_HIQ_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V1) & BIT_MASK_TAIL_PKT_HIQ_V1) +#define BIT_SET_TAIL_PKT_HIQ_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V1(x) | BIT_TAIL_PKT_HIQ_V1(v)) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TRXRPT_TIMER_TH 24 -#define BIT_MASK_TRXRPT_TIMER_TH 0xff -#define BIT_TRXRPT_TIMER_TH(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH) -#define BIT_GET_TRXRPT_TIMER_TH(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH) +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ +#define BIT_ACQ15_ENABLE BIT(15) +#define BIT_ACQ14_ENABLE BIT(14) +#define BIT_ACQ13_ENABLE BIT(13) +#define BIT_ACQ12_ENABLE BIT(12) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_TAIL_PKT_HIQ_V2 11 +#define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff +#define BIT_TAIL_PKT_HIQ_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2) +#define BITS_TAIL_PKT_HIQ_V2 \ + (BIT_MASK_TAIL_PKT_HIQ_V2 << BIT_SHIFT_TAIL_PKT_HIQ_V2) +#define BIT_CLEAR_TAIL_PKT_HIQ_V2(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2)) +#define BIT_GET_TAIL_PKT_HIQ_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2) +#define BIT_SET_TAIL_PKT_HIQ_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V2(x) | BIT_TAIL_PKT_HIQ_V2(v)) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_SPC_WRITE_PTR 16 -#define BIT_MASK_SPC_WRITE_PTR 0xf -#define BIT_SPC_WRITE_PTR(x) (((x) & BIT_MASK_SPC_WRITE_PTR) << BIT_SHIFT_SPC_WRITE_PTR) -#define BIT_GET_SPC_WRITE_PTR(x) (((x) >> BIT_SHIFT_SPC_WRITE_PTR) & BIT_MASK_SPC_WRITE_PTR) +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ +#define BIT_ACQ11_ENABLE BIT(11) +#define BIT_ACQ10_ENABLE BIT(10) +#define BIT_ACQ9_ENABLE BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_PKT_NUM_HIQ_V1 8 +#define BIT_MASK_PKT_NUM_HIQ_V1 0x7f +#define BIT_PKT_NUM_HIQ_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_HIQ_V1) << BIT_SHIFT_PKT_NUM_HIQ_V1) +#define BITS_PKT_NUM_HIQ_V1 \ + (BIT_MASK_PKT_NUM_HIQ_V1 << BIT_SHIFT_PKT_NUM_HIQ_V1) +#define BIT_CLEAR_PKT_NUM_HIQ_V1(x) ((x) & (~BITS_PKT_NUM_HIQ_V1)) +#define BIT_GET_PKT_NUM_HIQ_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_HIQ_V1) & BIT_MASK_PKT_NUM_HIQ_V1) +#define BIT_SET_PKT_NUM_HIQ_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_HIQ_V1(x) | BIT_PKT_NUM_HIQ_V1(v)) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TRXRPT_LEN_TH 16 -#define BIT_MASK_TRXRPT_LEN_TH 0xff -#define BIT_TRXRPT_LEN_TH(x) (((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH) -#define BIT_GET_TRXRPT_LEN_TH(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH) +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ +#define BIT_ACQ8_ENABLE BIT(8) +#define BIT_ACQ7_ENABLE BIT(7) +#define BIT_ACQ6_ENABLE BIT(6) +#define BIT_ACQ5_ENABLE BIT(5) +#define BIT_ACQ4_ENABLE BIT(4) +#define BIT_ACQ3_ENABLE BIT(3) +#define BIT_ACQ2_ENABLE BIT(2) +#define BIT_ACQ1_ENABLE BIT(1) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_HEAD_PKT_HIQ 0 +#define BIT_MASK_HEAD_PKT_HIQ 0xff +#define BIT_HEAD_PKT_HIQ(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ) << BIT_SHIFT_HEAD_PKT_HIQ) +#define BITS_HEAD_PKT_HIQ (BIT_MASK_HEAD_PKT_HIQ << BIT_SHIFT_HEAD_PKT_HIQ) +#define BIT_CLEAR_HEAD_PKT_HIQ(x) ((x) & (~BITS_HEAD_PKT_HIQ)) +#define BIT_GET_HEAD_PKT_HIQ(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ) & BIT_MASK_HEAD_PKT_HIQ) +#define BIT_SET_HEAD_PKT_HIQ(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ(x) | BIT_HEAD_PKT_HIQ(v)) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AC_READ_PTR 8 -#define BIT_MASK_AC_READ_PTR 0xf -#define BIT_AC_READ_PTR(x) (((x) & BIT_MASK_AC_READ_PTR) << BIT_SHIFT_AC_READ_PTR) -#define BIT_GET_AC_READ_PTR(x) (((x) >> BIT_SHIFT_AC_READ_PTR) & BIT_MASK_AC_READ_PTR) +/* 2 REG_HIQ_INFO (Offset 0x0414) */ +#define BIT_SHIFT_HEAD_PKT_HIQ_V1 0 +#define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff +#define BIT_HEAD_PKT_HIQ_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1) +#define BITS_HEAD_PKT_HIQ_V1 \ + (BIT_MASK_HEAD_PKT_HIQ_V1 << BIT_SHIFT_HEAD_PKT_HIQ_V1) +#define BIT_CLEAR_HEAD_PKT_HIQ_V1(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1)) +#define BIT_GET_HEAD_PKT_HIQ_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1) +#define BIT_SET_HEAD_PKT_HIQ_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ_V1(x) | BIT_HEAD_PKT_HIQ_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */ -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_ACQ0_ENABLE BIT(0) +/* 2 REG_BCNQ_BDNY_V2 (Offset 0x0418) */ -#define BIT_SHIFT_TRXRPT_READ_PTR 8 -#define BIT_MASK_TRXRPT_READ_PTR 0xff -#define BIT_TRXRPT_READ_PTR(x) (((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR) -#define BIT_GET_TRXRPT_READ_PTR(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR) +#define BIT_SHIFT_BCNQ_PGBNDY_WSEL 28 +#define BIT_MASK_BCNQ_PGBNDY_WSEL 0x7 +#define BIT_BCNQ_PGBNDY_WSEL(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_WSEL) << BIT_SHIFT_BCNQ_PGBNDY_WSEL) +#define BITS_BCNQ_PGBNDY_WSEL \ + (BIT_MASK_BCNQ_PGBNDY_WSEL << BIT_SHIFT_BCNQ_PGBNDY_WSEL) +#define BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_WSEL)) +#define BIT_GET_BCNQ_PGBNDY_WSEL(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WSEL) & BIT_MASK_BCNQ_PGBNDY_WSEL) +#define BIT_SET_BCNQ_PGBNDY_WSEL(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) | BIT_BCNQ_PGBNDY_WSEL(v)) +#define BIT_SHIFT_BCNQ_PGBNDY_RCONTENT 12 +#define BIT_MASK_BCNQ_PGBNDY_RCONTENT 0xfff +#define BIT_BCNQ_PGBNDY_RCONTENT(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_RCONTENT) \ + << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) +#define BITS_BCNQ_PGBNDY_RCONTENT \ + (BIT_MASK_BCNQ_PGBNDY_RCONTENT << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) +#define BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_RCONTENT)) +#define BIT_GET_BCNQ_PGBNDY_RCONTENT(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) & \ + BIT_MASK_BCNQ_PGBNDY_RCONTENT) +#define BIT_SET_BCNQ_PGBNDY_RCONTENT(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) | BIT_BCNQ_PGBNDY_RCONTENT(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCNQ_INFO (Offset 0x0418) */ -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ - +#define BIT_SHIFT_PKT_NUM_BCNQ 8 +#define BIT_MASK_PKT_NUM_BCNQ 0xff +#define BIT_PKT_NUM_BCNQ(x) \ + (((x) & BIT_MASK_PKT_NUM_BCNQ) << BIT_SHIFT_PKT_NUM_BCNQ) +#define BITS_PKT_NUM_BCNQ (BIT_MASK_PKT_NUM_BCNQ << BIT_SHIFT_PKT_NUM_BCNQ) +#define BIT_CLEAR_PKT_NUM_BCNQ(x) ((x) & (~BITS_PKT_NUM_BCNQ)) +#define BIT_GET_PKT_NUM_BCNQ(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_BCNQ) & BIT_MASK_PKT_NUM_BCNQ) +#define BIT_SET_PKT_NUM_BCNQ(x, v) \ + (BIT_CLEAR_PKT_NUM_BCNQ(x) | BIT_PKT_NUM_BCNQ(v)) + +#define BIT_SHIFT_BCNQ_HEAD_PG 0 +#define BIT_MASK_BCNQ_HEAD_PG 0xff +#define BIT_BCNQ_HEAD_PG(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG) << BIT_SHIFT_BCNQ_HEAD_PG) +#define BITS_BCNQ_HEAD_PG (BIT_MASK_BCNQ_HEAD_PG << BIT_SHIFT_BCNQ_HEAD_PG) +#define BIT_CLEAR_BCNQ_HEAD_PG(x) ((x) & (~BITS_BCNQ_HEAD_PG)) +#define BIT_GET_BCNQ_HEAD_PG(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG) & BIT_MASK_BCNQ_HEAD_PG) +#define BIT_SET_BCNQ_HEAD_PG(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG(x) | BIT_BCNQ_HEAD_PG(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AC_WRITE_PTR 0 -#define BIT_MASK_AC_WRITE_PTR 0xf -#define BIT_AC_WRITE_PTR(x) (((x) & BIT_MASK_AC_WRITE_PTR) << BIT_SHIFT_AC_WRITE_PTR) -#define BIT_GET_AC_WRITE_PTR(x) (((x) >> BIT_SHIFT_AC_WRITE_PTR) & BIT_MASK_AC_WRITE_PTR) +/* 2 REG_BCNQ_INFO (Offset 0x0418) */ +#define BIT_SHIFT_BCNQ_HEAD_PG_V1 0 +#define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff +#define BIT_BCNQ_HEAD_PG_V1(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1) +#define BITS_BCNQ_HEAD_PG_V1 \ + (BIT_MASK_BCNQ_HEAD_PG_V1 << BIT_SHIFT_BCNQ_HEAD_PG_V1) +#define BIT_CLEAR_BCNQ_HEAD_PG_V1(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1)) +#define BIT_GET_BCNQ_HEAD_PG_V1(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1) +#define BIT_SET_BCNQ_HEAD_PG_V1(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG_V1(x) | BIT_BCNQ_HEAD_PG_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCNQ_BDNY_V2 (Offset 0x0418) */ +#define BIT_SHIFT_BCNQ_PGBNDY_WCONTENT 0 +#define BIT_MASK_BCNQ_PGBNDY_WCONTENT 0xfff +#define BIT_BCNQ_PGBNDY_WCONTENT(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_WCONTENT) \ + << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) +#define BITS_BCNQ_PGBNDY_WCONTENT \ + (BIT_MASK_BCNQ_PGBNDY_WCONTENT << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) +#define BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_WCONTENT)) +#define BIT_GET_BCNQ_PGBNDY_WCONTENT(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) & \ + BIT_MASK_BCNQ_PGBNDY_WCONTENT) +#define BIT_SET_BCNQ_PGBNDY_WCONTENT(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) | BIT_BCNQ_PGBNDY_WCONTENT(v)) -/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TRXRPT_WRITE_PTR 0 -#define BIT_MASK_TRXRPT_WRITE_PTR 0xff -#define BIT_TRXRPT_WRITE_PTR(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR) -#define BIT_GET_TRXRPT_WRITE_PTR(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR) +/* 2 REG_TXPKT_EMPTY (Offset 0x041A) */ +#define BIT_BCNQ_EMPTY BIT(11) +#define BIT_HQQ_EMPTY BIT(10) +#define BIT_MQQ_EMPTY BIT(9) +#define BIT_MGQ_CPU_EMPTY BIT(8) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_BCN_POLL2 BIT(31) +#define BIT_BCN_POLL1 BIT(30) -/* 2 REG_INIRTS_RATE_SEL (Offset 0x0480) */ +#endif -#define BIT_LEAG_RTS_BW_DUP BIT(5) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BASIC_CFEND_RATE (Offset 0x0481) */ +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_BCN1_POLL BIT(30) -#define BIT_SHIFT_BASIC_CFEND_RATE 0 -#define BIT_MASK_BASIC_CFEND_RATE 0x1f -#define BIT_BASIC_CFEND_RATE(x) (((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE) -#define BIT_GET_BASIC_CFEND_RATE(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_STBC_CFEND_RATE (Offset 0x0482) */ +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGT_CLR_V1 BIT(30) -#define BIT_SHIFT_STBC_CFEND_RATE 0 -#define BIT_MASK_STBC_CFEND_RATE 0x1f -#define BIT_STBC_CFEND_RATE(x) (((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE) -#define BIT_GET_STBC_CFEND_RATE(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DATA_SC (Offset 0x0483) */ +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGT_POLL BIT(29) -#define BIT_SHIFT_TXSC_40M 4 -#define BIT_MASK_TXSC_40M 0xf -#define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) -#define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_TXSC_20M 0 -#define BIT_MASK_TXSC_20M 0xf -#define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) -#define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGT_POLL_SET BIT(29) -/* 2 REG_MACID_SLEEP3 (Offset 0x0484) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MACID127_96_PKTSLEEP 0 -#define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL -#define BIT_MACID127_96_PKTSLEEP(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP) << BIT_SHIFT_MACID127_96_PKTSLEEP) -#define BIT_GET_MACID127_96_PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) & BIT_MASK_MACID127_96_PKTSLEEP) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_BCN_POLL BIT(28) -/* 2 REG_MACID_SLEEP1 (Offset 0x0488) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_MACID63_32_PKTSLEEP 0 -#define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL -#define BIT_MACID63_32_PKTSLEEP(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP) -#define BIT_GET_MACID63_32_PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGT_POLL_CLR BIT(27) -/* 2 REG_ARFR2_V1 (Offset 0x048C) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_ARFR2_V1 0 -#define BIT_MASK_ARFR2_V1 0xffffffffffffffffL -#define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1) -#define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGT_CLR BIT(27) -/* 2 REG_ARFR3_V1 (Offset 0x0494) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_ARFR3_V1 0 -#define BIT_MASK_ARFR3_V1 0xffffffffffffffffL -#define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1) -#define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_EVTQ_VALID BIT(26) -/* 2 REG_ARFR4 (Offset 0x049C) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_ARFR4 0 -#define BIT_MASK_ARFR4 0xffffffffffffffffL -#define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4) -#define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_BCN_EXT_POLL BIT(21) +#define BIT_BCN4_POLL BIT(20) +#define BIT_BCN3_POLL BIT(19) +#define BIT_BCN2_POLL BIT(18) +#define BIT_BCN1_POLL_V1 BIT(17) -/* 2 REG_ARFR5 (Offset 0x04A4) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_ARFR5 0 -#define BIT_MASK_ARFR5 0xffffffffffffffffL -#define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5) -#define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_EN_RTY_BK_COND BIT(16) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ -#define BIT_SHCUT_PARSE_DASA BIT(25) +#define BIT_BCN_POLL_V1 BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGQ_FW_NUM_V1 BIT(12) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LOC_AMPDU_BURST_CTRL 24 -#define BIT_MASK_LOC_AMPDU_BURST_CTRL 0xff -#define BIT_LOC_AMPDU_BURST_CTRL(x) (((x) & BIT_MASK_LOC_AMPDU_BURST_CTRL) << BIT_SHIFT_LOC_AMPDU_BURST_CTRL) -#define BIT_GET_LOC_AMPDU_BURST_CTRL(x) (((x) >> BIT_SHIFT_LOC_AMPDU_BURST_CTRL) & BIT_MASK_LOC_AMPDU_BURST_CTRL) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_CPUMGQ_FW_NUM BIT(8) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ -#define BIT_SHCUT_BYPASS BIT(24) +#define BIT_EN_EVTQ_RPT BIT(2) +#define BIT_HWSEQ_EVTQ_EN BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_SHIFT_CPUMGQ_HEAD_PG 0 +#define BIT_MASK_CPUMGQ_HEAD_PG 0xff +#define BIT_CPUMGQ_HEAD_PG(x) \ + (((x) & BIT_MASK_CPUMGQ_HEAD_PG) << BIT_SHIFT_CPUMGQ_HEAD_PG) +#define BITS_CPUMGQ_HEAD_PG \ + (BIT_MASK_CPUMGQ_HEAD_PG << BIT_SHIFT_CPUMGQ_HEAD_PG) +#define BIT_CLEAR_CPUMGQ_HEAD_PG(x) ((x) & (~BITS_CPUMGQ_HEAD_PG)) +#define BIT_GET_CPUMGQ_HEAD_PG(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_HEAD_PG) & BIT_MASK_CPUMGQ_HEAD_PG) +#define BIT_SET_CPUMGQ_HEAD_PG(x, v) \ + (BIT_CLEAR_CPUMGQ_HEAD_PG(x) | BIT_CPUMGQ_HEAD_PG(v)) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET 24 -#define BIT_MASK_R_MUTAB_TXRPT_OFFSET 0xff -#define BIT_R_MUTAB_TXRPT_OFFSET(x) (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET) << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) -#define BIT_GET_R_MUTAB_TXRPT_OFFSET(x) (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) & BIT_MASK_R_MUTAB_TXRPT_OFFSET) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_SHIFT_FW_FREE_TAIL_V1 0 +#define BIT_MASK_FW_FREE_TAIL_V1 0xfff +#define BIT_FW_FREE_TAIL_V1(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1) +#define BITS_FW_FREE_TAIL_V1 \ + (BIT_MASK_FW_FREE_TAIL_V1 << BIT_SHIFT_FW_FREE_TAIL_V1) +#define BIT_CLEAR_FW_FREE_TAIL_V1(x) ((x) & (~BITS_FW_FREE_TAIL_V1)) +#define BIT_GET_FW_FREE_TAIL_V1(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1) +#define BIT_SET_FW_FREE_TAIL_V1(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL_V1(x) | BIT_FW_FREE_TAIL_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ +#define BIT_SHIFT_FREE_TAIL_PAGE 0 +#define BIT_MASK_FREE_TAIL_PAGE 0xfff +#define BIT_FREE_TAIL_PAGE(x) \ + (((x) & BIT_MASK_FREE_TAIL_PAGE) << BIT_SHIFT_FREE_TAIL_PAGE) +#define BITS_FREE_TAIL_PAGE \ + (BIT_MASK_FREE_TAIL_PAGE << BIT_SHIFT_FREE_TAIL_PAGE) +#define BIT_CLEAR_FREE_TAIL_PAGE(x) ((x) & (~BITS_FREE_TAIL_PAGE)) +#define BIT_GET_FREE_TAIL_PAGE(x) \ + (((x) >> BIT_SHIFT_FREE_TAIL_PAGE) & BIT_MASK_FREE_TAIL_PAGE) +#define BIT_SET_FREE_TAIL_PAGE(x, v) \ + (BIT_CLEAR_FREE_TAIL_PAGE(x) | BIT_FREE_TAIL_PAGE(v)) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MACID_MURATE_OFFSET 24 -#define BIT_MASK_MACID_MURATE_OFFSET 0xff -#define BIT_MACID_MURATE_OFFSET(x) (((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET) -#define BIT_GET_MACID_MURATE_OFFSET(x) (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_RTS_LIMIT_IN_OFDM BIT(23) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_BCNQ_DL BIT(22) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LOC_BCN_RPT 16 -#define BIT_MASK_LOC_BCN_RPT 0xff -#define BIT_LOC_BCN_RPT(x) (((x) & BIT_MASK_LOC_BCN_RPT) << BIT_SHIFT_LOC_BCN_RPT) -#define BIT_GET_LOC_BCN_RPT(x) (((x) >> BIT_SHIFT_LOC_BCN_RPT) & BIT_MASK_LOC_BCN_RPT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_RD_RESP_NAV_BK BIT(21) +#define BIT_EN_WR_FREE_TAIL BIT(20) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - - -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ -#define BIT__R_RPTFIFO_1K BIT(16) +#define BIT_TXRPT_DIS BIT(19) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_NOTXRPT_USERATE_EN BIT(19) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MACID_SHCUT_OFFSET 16 -#define BIT_MASK_MACID_SHCUT_OFFSET 0xff -#define BIT_MACID_SHCUT_OFFSET(x) (((x) & BIT_MASK_MACID_SHCUT_OFFSET) << BIT_SHIFT_MACID_SHCUT_OFFSET) -#define BIT_GET_MACID_SHCUT_OFFSET(x) (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET) & BIT_MASK_MACID_SHCUT_OFFSET) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_DIS_TXFAIL_RPT BIT(18) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) - - -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ -#define BIT_RPTFIFO_SIZE_OPT BIT(16) +#define BIT_FTM_TIMEOUT_BYPASS BIT(16) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_BCNQ_DL5 BIT(13) +#define BIT_EN_BCNQ_DL4 BIT(12) +#define BIT_EN_BCNQ_DL3 BIT(11) +#define BIT_EN_BCNQ_DL2 BIT(10) +#define BIT_EN_BCNQ_DL1 BIT(9) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BFRPT_PARA_USERID_SEL 12 -#define BIT_MASK_BFRPT_PARA_USERID_SEL 0x7 -#define BIT_BFRPT_PARA_USERID_SEL(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL) << BIT_SHIFT_BFRPT_PARA_USERID_SEL) -#define BIT_GET_BFRPT_PARA_USERID_SEL(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL) & BIT_MASK_BFRPT_PARA_USERID_SEL) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_SHIFT_EN_QUEUE_RPT 8 +#define BIT_MASK_EN_QUEUE_RPT 0xff +#define BIT_EN_QUEUE_RPT(x) \ + (((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT) +#define BITS_EN_QUEUE_RPT (BIT_MASK_EN_QUEUE_RPT << BIT_SHIFT_EN_QUEUE_RPT) +#define BIT_CLEAR_EN_QUEUE_RPT(x) ((x) & (~BITS_EN_QUEUE_RPT)) +#define BIT_GET_EN_QUEUE_RPT(x) \ + (((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT) +#define BIT_SET_EN_QUEUE_RPT(x, v) \ + (BIT_CLEAR_EN_QUEUE_RPT(x) | BIT_EN_QUEUE_RPT(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_BCNQ_DL0 BIT(8) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_LOC_TXRPT 8 -#define BIT_MASK_LOC_TXRPT 0xff -#define BIT_LOC_TXRPT(x) (((x) & BIT_MASK_LOC_TXRPT) << BIT_SHIFT_LOC_TXRPT) -#define BIT_GET_LOC_TXRPT(x) (((x) >> BIT_SHIFT_LOC_TXRPT) & BIT_MASK_LOC_TXRPT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_RTY_BK BIT(7) +#define BIT_EN_USE_INI_RAT BIT(6) +#define BIT_EN_RTS_NAV_BK BIT(5) +#define BIT_DIS_SSN_CHECK BIT(4) +#define BIT_MACID_MATCH_RTS BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_BCN_TRXRPT_V1 BIT(2) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_MACID_CTRL_OFFSET 8 -#define BIT_MASK_MACID_CTRL_OFFSET 0xff -#define BIT_MACID_CTRL_OFFSET(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET) -#define BIT_GET_MACID_CTRL_OFFSET(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_R_EN_FTMRPT BIT(1) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_R_EN_FTMRPT_V1 BIT(1) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_LOC_SRFF 0 -#define BIT_MASK_LOC_SRFF 0xff -#define BIT_LOC_SRFF(x) (((x) & BIT_MASK_LOC_SRFF) << BIT_SHIFT_LOC_SRFF) -#define BIT_GET_LOC_SRFF(x) (((x) >> BIT_SHIFT_LOC_SRFF) & BIT_MASK_LOC_SRFF) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_FTMRPT_V1 BIT(1) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_FTMACKRPT BIT(1) -/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0 -#define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff -#define BIT_AMPDU_TXRPT_OFFSET(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET) -#define BIT_GET_AMPDU_TXRPT_OFFSET(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_R_BMC_NAV_PROTECT BIT(0) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_BMC_NAV_PROTECT BIT(0) -/* 2 REG_TRYING_CNT_TH (Offset 0x04B0) */ +#endif +#if (HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_INDEX_15 24 -#define BIT_MASK_INDEX_15 0xff -#define BIT_INDEX_15(x) (((x) & BIT_MASK_INDEX_15) << BIT_SHIFT_INDEX_15) -#define BIT_GET_INDEX_15(x) (((x) >> BIT_SHIFT_INDEX_15) & BIT_MASK_INDEX_15) +/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ +#define BIT_EN_FTMRPT BIT(0) -#define BIT_SHIFT_INDEX_14 16 -#define BIT_MASK_INDEX_14 0xff -#define BIT_INDEX_14(x) (((x) & BIT_MASK_INDEX_14) << BIT_SHIFT_INDEX_14) -#define BIT_GET_INDEX_14(x) (((x) >> BIT_SHIFT_INDEX_14) & BIT_MASK_INDEX_14) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_INDEX_13 8 -#define BIT_MASK_INDEX_13 0xff -#define BIT_INDEX_13(x) (((x) & BIT_MASK_INDEX_13) << BIT_SHIFT_INDEX_13) -#define BIT_GET_INDEX_13(x) (((x) >> BIT_SHIFT_INDEX_13) & BIT_MASK_INDEX_13) +/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ +#define BIT_HWSEQ_CPUM_EN BIT(7) +#define BIT_HWSEQ_BCN_EN BIT(6) +#define BIT_HWSEQ_HI_EN BIT(5) +#define BIT_HWSEQ_MGT_EN BIT(4) +#define BIT_HWSEQ_BK_EN BIT(3) -#define BIT_SHIFT_INDEX_12 0 -#define BIT_MASK_INDEX_12 0xff -#define BIT_INDEX_12(x) (((x) & BIT_MASK_INDEX_12) << BIT_SHIFT_INDEX_12) -#define BIT_GET_INDEX_12(x) (((x) >> BIT_SHIFT_INDEX_12) & BIT_MASK_INDEX_12) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT 0 -#define BIT_MASK_RA_TRY_RATE_AGG_LMT 0x1f -#define BIT_RA_TRY_RATE_AGG_LMT(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT) -#define BIT_GET_RA_TRY_RATE_AGG_LMT(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT) & BIT_MASK_RA_TRY_RATE_AGG_LMT) +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#define BIT_R_BROADCAST_RETRY_EN BIT(3) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ -#define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31) -#define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30) -#define BIT_PTA_WL_PRI_MASK_HIQ BIT(29) -#define BIT_PTA_WL_PRI_MASK_MGQ BIT(28) -#define BIT_PTA_WL_PRI_MASK_BK BIT(27) -#define BIT_PTA_WL_PRI_MASK_BE BIT(26) -#define BIT_PTA_WL_PRI_MASK_VI BIT(25) -#define BIT_PTA_WL_PRI_MASK_VO BIT(24) +#define BIT_BROADCAST_RTY_EN BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ +#define BIT_HWSEQ_BE_EN BIT(2) -/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_POWER_STAGE1 0 -#define BIT_MASK_POWER_STAGE1 0xffffff -#define BIT_POWER_STAGE1(x) (((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1) -#define BIT_GET_POWER_STAGE1(x) (((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1) +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#define BIT__R_EN_RTY_BK_COD BIT(2) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ -#define BIT__R_CTRL_PKT_POW_ADJ BIT(24) +#define BIT_EN_RTY_BK_COD BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */ +#define BIT_HWSEQ_VI_EN BIT(1) +#define BIT_HWSEQ_VO_EN BIT(0) -/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_POWER_STAGE2 0 -#define BIT_MASK_POWER_STAGE2 0xffffff -#define BIT_POWER_STAGE2(x) (((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2) -#define BIT_GET_POWER_STAGE2(x) (((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2) +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#define BIT_SHIFT__R_DATA_FALLBACK_SEL 0 +#define BIT_MASK__R_DATA_FALLBACK_SEL 0x3 +#define BIT__R_DATA_FALLBACK_SEL(x) \ + (((x) & BIT_MASK__R_DATA_FALLBACK_SEL) \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL) +#define BITS__R_DATA_FALLBACK_SEL \ + (BIT_MASK__R_DATA_FALLBACK_SEL << BIT_SHIFT__R_DATA_FALLBACK_SEL) +#define BIT_CLEAR__R_DATA_FALLBACK_SEL(x) ((x) & (~BITS__R_DATA_FALLBACK_SEL)) +#define BIT_GET__R_DATA_FALLBACK_SEL(x) \ + (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) & \ + BIT_MASK__R_DATA_FALLBACK_SEL) +#define BIT_SET__R_DATA_FALLBACK_SEL(x, v) \ + (BIT_CLEAR__R_DATA_FALLBACK_SEL(x) | BIT__R_DATA_FALLBACK_SEL(v)) -/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PAD_NUM_THRES 24 -#define BIT_MASK_PAD_NUM_THRES 0x3f -#define BIT_PAD_NUM_THRES(x) (((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES) -#define BIT_GET_PAD_NUM_THRES(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES) +/* 2 REG_DATAFB_SEL (Offset 0x0423) */ +#define BIT_SHIFT__DATA_FALLBACK_SEL 0 +#define BIT_MASK__DATA_FALLBACK_SEL 0x3 +#define BIT__DATA_FALLBACK_SEL(x) \ + (((x) & BIT_MASK__DATA_FALLBACK_SEL) << BIT_SHIFT__DATA_FALLBACK_SEL) +#define BITS__DATA_FALLBACK_SEL \ + (BIT_MASK__DATA_FALLBACK_SEL << BIT_SHIFT__DATA_FALLBACK_SEL) +#define BIT_CLEAR__DATA_FALLBACK_SEL(x) ((x) & (~BITS__DATA_FALLBACK_SEL)) +#define BIT_GET__DATA_FALLBACK_SEL(x) \ + (((x) >> BIT_SHIFT__DATA_FALLBACK_SEL) & BIT_MASK__DATA_FALLBACK_SEL) +#define BIT_SET__DATA_FALLBACK_SEL(x, v) \ + (BIT_CLEAR__DATA_FALLBACK_SEL(x) | BIT__DATA_FALLBACK_SEL(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCNQ_BDNY (Offset 0x0424) */ +#define BIT_SHIFT_MGQ_PGBNDY_V2 8 +#define BIT_MASK_MGQ_PGBNDY_V2 0xff +#define BIT_MGQ_PGBNDY_V2(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V2) << BIT_SHIFT_MGQ_PGBNDY_V2) +#define BITS_MGQ_PGBNDY_V2 (BIT_MASK_MGQ_PGBNDY_V2 << BIT_SHIFT_MGQ_PGBNDY_V2) +#define BIT_CLEAR_MGQ_PGBNDY_V2(x) ((x) & (~BITS_MGQ_PGBNDY_V2)) +#define BIT_GET_MGQ_PGBNDY_V2(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V2) & BIT_MASK_MGQ_PGBNDY_V2) +#define BIT_SET_MGQ_PGBNDY_V2(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V2(x) | BIT_MGQ_PGBNDY_V2(v)) -/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#endif -#define BIT_R_DMA_THIS_QUEUE_BK BIT(23) -#define BIT_R_DMA_THIS_QUEUE_BE BIT(22) -#define BIT_R_DMA_THIS_QUEUE_VI BIT(21) -#define BIT_R_DMA_THIS_QUEUE_VO BIT(20) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_TOTAL_LEN_TH 8 -#define BIT_MASK_R_TOTAL_LEN_TH 0xfff -#define BIT_R_TOTAL_LEN_TH(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH) -#define BIT_GET_R_TOTAL_LEN_TH(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH) +/* 2 REG_BCNQ_BDNY (Offset 0x0424) */ +#define BIT_SHIFT_BCNQ_PGBNDY 0 +#define BIT_MASK_BCNQ_PGBNDY 0xff +#define BIT_BCNQ_PGBNDY(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY) << BIT_SHIFT_BCNQ_PGBNDY) +#define BITS_BCNQ_PGBNDY (BIT_MASK_BCNQ_PGBNDY << BIT_SHIFT_BCNQ_PGBNDY) +#define BIT_CLEAR_BCNQ_PGBNDY(x) ((x) & (~BITS_BCNQ_PGBNDY)) +#define BIT_GET_BCNQ_PGBNDY(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY) & BIT_MASK_BCNQ_PGBNDY) +#define BIT_SET_BCNQ_PGBNDY(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY(x) | BIT_BCNQ_PGBNDY(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +/* 2 REG_BCNQ_BDNY_V1 (Offset 0x0424) */ -#define BIT_EN_NEW_EARLY BIT(7) +#define BIT_SHIFT_BCNQ_PGBNDY_V1 0 +#define BIT_MASK_BCNQ_PGBNDY_V1 0xfff +#define BIT_BCNQ_PGBNDY_V1(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1) +#define BITS_BCNQ_PGBNDY_V1 \ + (BIT_MASK_BCNQ_PGBNDY_V1 << BIT_SHIFT_BCNQ_PGBNDY_V1) +#define BIT_CLEAR_BCNQ_PGBNDY_V1(x) ((x) & (~BITS_BCNQ_PGBNDY_V1)) +#define BIT_GET_BCNQ_PGBNDY_V1(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1) +#define BIT_SET_BCNQ_PGBNDY_V1(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_V1(x) | BIT_BCNQ_PGBNDY_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXBDNY (Offset 0x0424) */ +#define BIT_SHIFT_TXBNDY 0 +#define BIT_MASK_TXBNDY 0xfff +#define BIT_TXBNDY(x) (((x) & BIT_MASK_TXBNDY) << BIT_SHIFT_TXBNDY) +#define BITS_TXBNDY (BIT_MASK_TXBNDY << BIT_SHIFT_TXBNDY) +#define BIT_CLEAR_TXBNDY(x) ((x) & (~BITS_TXBNDY)) +#define BIT_GET_TXBNDY(x) (((x) >> BIT_SHIFT_TXBNDY) & BIT_MASK_TXBNDY) +#define BIT_SET_TXBNDY(x, v) (BIT_CLEAR_TXBNDY(x) | BIT_TXBNDY(v)) -/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#endif -#define BIT_PRE_TX_CMD BIT(6) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NUM_SCL_EN 4 -#define BIT_MASK_NUM_SCL_EN 0x3 -#define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN) -#define BIT_GET_NUM_SCL_EN(x) (((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN) +/* 2 REG_MGQ_BDNY (Offset 0x0425) */ -#define BIT_BK_EN BIT(3) -#define BIT_BE_EN BIT(2) -#define BIT_VI_EN BIT(1) -#define BIT_VO_EN BIT(0) +#define BIT_SHIFT_MGQ_PGBNDY 0 +#define BIT_MASK_MGQ_PGBNDY 0xff +#define BIT_MGQ_PGBNDY(x) (((x) & BIT_MASK_MGQ_PGBNDY) << BIT_SHIFT_MGQ_PGBNDY) +#define BITS_MGQ_PGBNDY (BIT_MASK_MGQ_PGBNDY << BIT_SHIFT_MGQ_PGBNDY) +#define BIT_CLEAR_MGQ_PGBNDY(x) ((x) & (~BITS_MGQ_PGBNDY)) +#define BIT_GET_MGQ_PGBNDY(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY) & BIT_MASK_MGQ_PGBNDY) +#define BIT_SET_MGQ_PGBNDY(x, v) (BIT_CLEAR_MGQ_PGBNDY(x) | BIT_MGQ_PGBNDY(v)) -/* 2 REG_PKT_LIFE_TIME (Offset 0x04C0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKT_LIFTIME_BEBK 16 -#define BIT_MASK_PKT_LIFTIME_BEBK 0xffff -#define BIT_PKT_LIFTIME_BEBK(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK) -#define BIT_GET_PKT_LIFTIME_BEBK(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK) +/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +#define BIT_BT_INT_CPU BIT(7) +#define BIT_BT_INT_PTA BIT(6) -#define BIT_SHIFT_PKT_LIFTIME_VOVI 0 -#define BIT_MASK_PKT_LIFTIME_VOVI 0xffff -#define BIT_PKT_LIFTIME_VOVI(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI) -#define BIT_GET_PKT_LIFTIME_VOVI(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_STBC_SETTING (Offset 0x04C4) */ +/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +#define BIT_SPERPT_ENTRY BIT(5) -#define BIT_SHIFT_CDEND_TXTIME_L 4 -#define BIT_MASK_CDEND_TXTIME_L 0xf -#define BIT_CDEND_TXTIME_L(x) (((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L) -#define BIT_GET_CDEND_TXTIME_L(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NESS 2 -#define BIT_MASK_NESS 0x3 -#define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS) -#define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS) +/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +#define BIT_RTYCNT_FB BIT(4) -#define BIT_SHIFT_STBC_CFEND 0 -#define BIT_MASK_STBC_CFEND 0x3 -#define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND) -#define BIT_GET_STBC_CFEND(x) (((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_STBC_SETTING2 (Offset 0x04C5) */ +/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +#define BIT_EN_CTRL_RTYBIT BIT(4) -#define BIT_SHIFT_CDEND_TXTIME_H 0 -#define BIT_MASK_CDEND_TXTIME_H 0x1f -#define BIT_CDEND_TXTIME_H(x) (((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H) -#define BIT_GET_CDEND_TXTIME_H(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_LIFETIME_EN (Offset 0x0426) */ +#define BIT_LIFETIME_BK_EN BIT(3) +#define BIT_LIFETIME_BE_EN BIT(2) +#define BIT_LIFETIME_VI_EN BIT(1) +#define BIT_LIFETIME_VO_EN BIT(0) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ +/* 2 REG_FW_FREE_TAIL (Offset 0x0427) */ -#define BIT_PTA_EDCCA_EN BIT(5) -#define BIT_PTA_WL_TX_EN BIT(4) +#define BIT_SHIFT_FW_FREE_TAIL 0 +#define BIT_MASK_FW_FREE_TAIL 0xff +#define BIT_FW_FREE_TAIL(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL) << BIT_SHIFT_FW_FREE_TAIL) +#define BITS_FW_FREE_TAIL (BIT_MASK_FW_FREE_TAIL << BIT_SHIFT_FW_FREE_TAIL) +#define BIT_CLEAR_FW_FREE_TAIL(x) ((x) & (~BITS_FW_FREE_TAIL)) +#define BIT_GET_FW_FREE_TAIL(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL) & BIT_MASK_FW_FREE_TAIL) +#define BIT_SET_FW_FREE_TAIL(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL(x) | BIT_FW_FREE_TAIL(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SPEC_SIFS (Offset 0x0428) */ +#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8 +#define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff +#define BIT_SPEC_SIFS_OFDM_PTCL(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) +#define BITS_SPEC_SIFS_OFDM_PTCL \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) | BIT_SPEC_SIFS_OFDM_PTCL(v)) + +#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0 +#define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff +#define BIT_SPEC_SIFS_CCK_PTCL(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL) +#define BITS_SPEC_SIFS_CCK_PTCL \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL << BIT_SHIFT_SPEC_SIFS_CCK_PTCL) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) ((x) & (~BITS_SPEC_SIFS_CCK_PTCL)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL) +#define BIT_SET_SPEC_SIFS_CCK_PTCL(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) | BIT_SPEC_SIFS_CCK_PTCL(v)) -/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ +/* 2 REG_RETRY_LIMIT (Offset 0x042A) */ -#define BIT_R_USE_DATA_BW BIT(3) -#define BIT_TRI_PKT_INT_MODE1 BIT(2) -#define BIT_TRI_PKT_INT_MODE0 BIT(1) -#define BIT_ACQ_MODE_SEL BIT(0) +#define BIT_SHIFT_SRL 8 +#define BIT_MASK_SRL 0x3f +#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL) +#define BITS_SRL (BIT_MASK_SRL << BIT_SHIFT_SRL) +#define BIT_CLEAR_SRL(x) ((x) & (~BITS_SRL)) +#define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL) +#define BIT_SET_SRL(x, v) (BIT_CLEAR_SRL(x) | BIT_SRL(v)) -/* 2 REG_SINGLE_AMPDU_CTRL (Offset 0x04C7) */ +#define BIT_SHIFT_LRL 0 +#define BIT_MASK_LRL 0x3f +#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL) +#define BITS_LRL (BIT_MASK_LRL << BIT_SHIFT_LRL) +#define BIT_CLEAR_LRL(x) ((x) & (~BITS_LRL)) +#define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL) +#define BIT_SET_LRL(x, v) (BIT_CLEAR_LRL(x) | BIT_LRL(v)) -#define BIT_EN_SINGLE_APMDU BIT(7) +#endif -/* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_ENABLE_NDPA BIT(31) -#define BIT_SHIFT_RTS_MAX_AGG_NUM 24 -#define BIT_MASK_RTS_MAX_AGG_NUM 0x3f -#define BIT_RTS_MAX_AGG_NUM(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM) -#define BIT_GET_RTS_MAX_AGG_NUM(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_MAX_AGG_NUM 16 -#define BIT_MASK_MAX_AGG_NUM 0x3f -#define BIT_MAX_AGG_NUM(x) (((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM) -#define BIT_GET_MAX_AGG_NUM(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_ENABLE_NDPA BIT(31) -#define BIT_SHIFT_RTS_TXTIME_TH 8 -#define BIT_MASK_RTS_TXTIME_TH 0xff -#define BIT_RTS_TXTIME_TH(x) (((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH) -#define BIT_GET_RTS_TXTIME_TH(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RTS_LEN_TH 0 -#define BIT_MASK_RTS_LEN_TH 0xff -#define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH) -#define BIT_GET_RTS_LEN_TH(x) (((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_USE_NDPA_PARAMETER BIT(30) -/* 2 REG_BAR_MODE_CTRL (Offset 0x04CC) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BAR_RTY_LMT 16 -#define BIT_MASK_BAR_RTY_LMT 0x3 -#define BIT_BAR_RTY_LMT(x) (((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT) -#define BIT_GET_BAR_RTY_LMT(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_NDPA_PARA BIT(30) -#define BIT_SHIFT_BAR_PKT_TXTIME_TH 8 -#define BIT_MASK_BAR_PKT_TXTIME_TH 0xff -#define BIT_BAR_PKT_TXTIME_TH(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH) -#define BIT_GET_BAR_PKT_TXTIME_TH(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH) +#endif -#define BIT_BAR_EN_V1 BIT(6) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BAR_PKTNUM_TH_V1 0 -#define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f -#define BIT_BAR_PKTNUM_TH_V1(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1) -#define BIT_GET_BAR_PKTNUM_TH_V1(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_PROP_TXBF BIT(29) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_PROP_TXBF BIT(29) -/* 2 REG_RA_TRY_RATE_AGG_LMT (Offset 0x04CF) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0 -#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f -#define BIT_RA_TRY_RATE_AGG_LMT_V1(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) -#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_EN_NDPA_INT BIT(28) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_EN_NDPA_INT BIT(28) -/* 2 REG_MACID_SLEEP2 (Offset 0x04D0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MACID95_64PKTSLEEP 0 -#define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL -#define BIT_MACID95_64PKTSLEEP(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP) -#define BIT_GET_MACID95_64PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBF1_80M BIT(27) -/* 2 REG_MACID_SLEEP (Offset 0x04D4) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_MACID31_0_PKTSLEEP 0 -#define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL -#define BIT_MACID31_0_PKTSLEEP(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP) -#define BIT_GET_MACID31_0_PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF1_80M BIT(27) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF1_80M_160M BIT(27) -/* 2 REG_HW_SEQ0 (Offset 0x04D8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HW_SSN_SEQ0 0 -#define BIT_MASK_HW_SSN_SEQ0 0xfff -#define BIT_HW_SSN_SEQ0(x) (((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0) -#define BIT_GET_HW_SSN_SEQ0(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBF1_40M BIT(26) -/* 2 REG_HW_SEQ1 (Offset 0x04DA) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HW_SSN_SEQ1 0 -#define BIT_MASK_HW_SSN_SEQ1 0xfff -#define BIT_HW_SSN_SEQ1(x) (((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1) -#define BIT_GET_HW_SSN_SEQ1(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF1_40M BIT(26) -/* 2 REG_HW_SEQ2 (Offset 0x04DC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_HW_SSN_SEQ2 0 -#define BIT_MASK_HW_SSN_SEQ2 0xfff -#define BIT_HW_SSN_SEQ2(x) (((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2) -#define BIT_GET_HW_SSN_SEQ2(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBF1_20M BIT(25) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF1_20M BIT(25) -/* 2 REG_HW_SEQ3 (Offset 0x04DE) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CSI_HWSSN_SEL 12 -#define BIT_MASK_CSI_HWSSN_SEL 0x3 -#define BIT_CSI_HWSSN_SEL(x) (((x) & BIT_MASK_CSI_HWSSN_SEL) << BIT_SHIFT_CSI_HWSSN_SEL) -#define BIT_GET_CSI_HWSSN_SEL(x) (((x) >> BIT_SHIFT_CSI_HWSSN_SEL) & BIT_MASK_CSI_HWSSN_SEL) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_SHIFT_R_TXBF1_AID 16 +#define BIT_MASK_R_TXBF1_AID 0x1ff +#define BIT_R_TXBF1_AID(x) \ + (((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID) +#define BITS_R_TXBF1_AID (BIT_MASK_R_TXBF1_AID << BIT_SHIFT_R_TXBF1_AID) +#define BIT_CLEAR_R_TXBF1_AID(x) ((x) & (~BITS_R_TXBF1_AID)) +#define BIT_GET_R_TXBF1_AID(x) \ + (((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID) +#define BIT_SET_R_TXBF1_AID(x, v) \ + (BIT_CLEAR_R_TXBF1_AID(x) | BIT_R_TXBF1_AID(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_SHIFT_TXBF1_AID 16 +#define BIT_MASK_TXBF1_AID 0x1ff +#define BIT_TXBF1_AID(x) (((x) & BIT_MASK_TXBF1_AID) << BIT_SHIFT_TXBF1_AID) +#define BITS_TXBF1_AID (BIT_MASK_TXBF1_AID << BIT_SHIFT_TXBF1_AID) +#define BIT_CLEAR_TXBF1_AID(x) ((x) & (~BITS_TXBF1_AID)) +#define BIT_GET_TXBF1_AID(x) (((x) >> BIT_SHIFT_TXBF1_AID) & BIT_MASK_TXBF1_AID) +#define BIT_SET_TXBF1_AID(x, v) (BIT_CLEAR_TXBF1_AID(x) | BIT_TXBF1_AID(v)) -/* 2 REG_HW_SEQ3 (Offset 0x04DE) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HW_SSN_SEQ3 0 -#define BIT_MASK_HW_SSN_SEQ3 0xfff -#define BIT_HW_SSN_SEQ3(x) (((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3) -#define BIT_GET_HW_SSN_SEQ3(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_DIS_NDP_BFEN BIT(15) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBCN_NOBLOCK_NDP BIT(14) -/* 2 REG_CSI_SEQ (Offset 0x04DE) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_HW_CSI_SEQ 0 -#define BIT_MASK_HW_CSI_SEQ 0xfff -#define BIT_HW_CSI_SEQ(x) (((x) & BIT_MASK_HW_CSI_SEQ) << BIT_SHIFT_HW_CSI_SEQ) -#define BIT_GET_HW_CSI_SEQ(x) (((x) >> BIT_SHIFT_HW_CSI_SEQ) & BIT_MASK_HW_CSI_SEQ) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBCN_NOBLOCK_NDP BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBF0_80M BIT(11) -/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_PTCL_TOTAL_PG_V1 2 -#define BIT_MASK_PTCL_TOTAL_PG_V1 0x1fff -#define BIT_PTCL_TOTAL_PG_V1(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V1) << BIT_SHIFT_PTCL_TOTAL_PG_V1) -#define BIT_GET_PTCL_TOTAL_PG_V1(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1) & BIT_MASK_PTCL_TOTAL_PG_V1) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF0_80M BIT(11) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF0_80M_160M BIT(11) -/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PTCL_TOTAL_PG_V2 2 -#define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff -#define BIT_PTCL_TOTAL_PG_V2(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2) -#define BIT_GET_PTCL_TOTAL_PG_V2(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBF0_40M BIT(10) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_TXBF0_40M BIT(10) -/* 2 REG_NULL_PKT_STATUS (Offset 0x04E0) */ +#endif -#define BIT_TX_NULL_1 BIT(1) -#define BIT_TX_NULL_0 BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_R_TXBF0_20M BIT(9) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ -#define BIT_PTCL_RATE_TABLE_INVALID BIT(7) -#define BIT_FTM_T2R_ERROR BIT(6) +#define BIT_TXBF0_20M BIT(9) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ +#define BIT_SHIFT_R_TXBF0_AID 0 +#define BIT_MASK_R_TXBF0_AID 0x1ff +#define BIT_R_TXBF0_AID(x) \ + (((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID) +#define BITS_R_TXBF0_AID (BIT_MASK_R_TXBF0_AID << BIT_SHIFT_R_TXBF0_AID) +#define BIT_CLEAR_R_TXBF0_AID(x) ((x) & (~BITS_R_TXBF0_AID)) +#define BIT_GET_R_TXBF0_AID(x) \ + (((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID) +#define BIT_SET_R_TXBF0_AID(x, v) \ + (BIT_CLEAR_R_TXBF0_AID(x) | BIT_R_TXBF0_AID(v)) -/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#endif -#define BIT_PTCL_ERR0 BIT(5) -#define BIT_PTCL_ERR1 BIT(4) -#define BIT_PTCL_ERR2 BIT(3) -#define BIT_PTCL_ERR3 BIT(2) -#define BIT_PTCL_ERR4 BIT(1) -#define BIT_PTCL_ERR5 BIT(0) +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) + +/* 2 REG_TXBF_CTRL (Offset 0x042C) */ + +#define BIT_SHIFT_TXBF0_AID 0 +#define BIT_MASK_TXBF0_AID 0x1ff +#define BIT_TXBF0_AID(x) (((x) & BIT_MASK_TXBF0_AID) << BIT_SHIFT_TXBF0_AID) +#define BITS_TXBF0_AID (BIT_MASK_TXBF0_AID << BIT_SHIFT_TXBF0_AID) +#define BIT_CLEAR_TXBF0_AID(x) ((x) & (~BITS_TXBF0_AID)) +#define BIT_GET_TXBF0_AID(x) (((x) >> BIT_SHIFT_TXBF0_AID) & BIT_MASK_TXBF0_AID) +#define BIT_SET_TXBF0_AID(x, v) (BIT_CLEAR_TXBF0_AID(x) | BIT_TXBF0_AID(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC8 0x1f +#define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8) +#define BITS_DARF_RC8 (BIT_MASK_DARF_RC8 << BIT_SHIFT_DARF_RC8) +#define BIT_CLEAR_DARF_RC8(x) ((x) & (~BITS_DARF_RC8)) +#define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8) +#define BIT_SET_DARF_RC8(x, v) (BIT_CLEAR_DARF_RC8(x) | BIT_DARF_RC8(v)) + +#define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC7 0x1f +#define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7) +#define BITS_DARF_RC7 (BIT_MASK_DARF_RC7 << BIT_SHIFT_DARF_RC7) +#define BIT_CLEAR_DARF_RC7(x) ((x) & (~BITS_DARF_RC7)) +#define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7) +#define BIT_SET_DARF_RC7(x, v) (BIT_CLEAR_DARF_RC7(x) | BIT_DARF_RC7(v)) + +#define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC6 0x1f +#define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6) +#define BITS_DARF_RC6 (BIT_MASK_DARF_RC6 << BIT_SHIFT_DARF_RC6) +#define BIT_CLEAR_DARF_RC6(x) ((x) & (~BITS_DARF_RC6)) +#define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6) +#define BIT_SET_DARF_RC6(x, v) (BIT_CLEAR_DARF_RC6(x) | BIT_DARF_RC6(v)) + +#define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC5 0x1f +#define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5) +#define BITS_DARF_RC5 (BIT_MASK_DARF_RC5 << BIT_SHIFT_DARF_RC5) +#define BIT_CLEAR_DARF_RC5(x) ((x) & (~BITS_DARF_RC5)) +#define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5) +#define BIT_SET_DARF_RC5(x, v) (BIT_CLEAR_DARF_RC5(x) | BIT_DARF_RC5(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ +/* 2 REG_DARFRC (Offset 0x0430) */ -#define BIT_CLI3_TX_NULL_1 BIT(7) -#define BIT_CLI3_TX_NULL_0 BIT(6) -#define BIT_CLI2_TX_NULL_1 BIT(5) -#define BIT_CLI2_TX_NULL_0 BIT(4) -#define BIT_CLI1_TX_NULL_1 BIT(3) -#define BIT_CLI1_TX_NULL_0 BIT(2) -#define BIT_CLI0_TX_NULL_1 BIT(1) +#define BIT_SHIFT_DARF_RC4 24 +#define BIT_MASK_DARF_RC4 0x1f +#define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4) +#define BITS_DARF_RC4 (BIT_MASK_DARF_RC4 << BIT_SHIFT_DARF_RC4) +#define BIT_CLEAR_DARF_RC4(x) ((x) & (~BITS_DARF_RC4)) +#define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4) +#define BIT_SET_DARF_RC4(x, v) (BIT_CLEAR_DARF_RC4(x) | BIT_DARF_RC4(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC4_V2 24 +#define BIT_MASK_DARF_RC4_V2 0x1f +#define BIT_DARF_RC4_V2(x) \ + (((x) & BIT_MASK_DARF_RC4_V2) << BIT_SHIFT_DARF_RC4_V2) +#define BITS_DARF_RC4_V2 (BIT_MASK_DARF_RC4_V2 << BIT_SHIFT_DARF_RC4_V2) +#define BIT_CLEAR_DARF_RC4_V2(x) ((x) & (~BITS_DARF_RC4_V2)) +#define BIT_GET_DARF_RC4_V2(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_V2) & BIT_MASK_DARF_RC4_V2) +#define BIT_SET_DARF_RC4_V2(x, v) \ + (BIT_CLEAR_DARF_RC4_V2(x) | BIT_DARF_RC4_V2(v)) -/* 2 REG_PTCL_PKT_NUM (Offset 0x04E3) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PTCL_TOTAL_PG 0 -#define BIT_MASK_PTCL_TOTAL_PG 0xff -#define BIT_PTCL_TOTAL_PG(x) (((x) & BIT_MASK_PTCL_TOTAL_PG) << BIT_SHIFT_PTCL_TOTAL_PG) -#define BIT_GET_PTCL_TOTAL_PG(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG) & BIT_MASK_PTCL_TOTAL_PG) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC4_V1 24 +#define BIT_MASK_DARF_RC4_V1 0x3f +#define BIT_DARF_RC4_V1(x) \ + (((x) & BIT_MASK_DARF_RC4_V1) << BIT_SHIFT_DARF_RC4_V1) +#define BITS_DARF_RC4_V1 (BIT_MASK_DARF_RC4_V1 << BIT_SHIFT_DARF_RC4_V1) +#define BIT_CLEAR_DARF_RC4_V1(x) ((x) & (~BITS_DARF_RC4_V1)) +#define BIT_GET_DARF_RC4_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_V1) & BIT_MASK_DARF_RC4_V1) +#define BIT_SET_DARF_RC4_V1(x, v) \ + (BIT_CLEAR_DARF_RC4_V1(x) | BIT_DARF_RC4_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ +/* 2 REG_DARFRC (Offset 0x0430) */ -#define BIT_CLI0_TX_NULL_0 BIT(0) +#define BIT_SHIFT_DARF_RC3 16 +#define BIT_MASK_DARF_RC3 0x1f +#define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3) +#define BITS_DARF_RC3 (BIT_MASK_DARF_RC3 << BIT_SHIFT_DARF_RC3) +#define BIT_CLEAR_DARF_RC3(x) ((x) & (~BITS_DARF_RC3)) +#define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3) +#define BIT_SET_DARF_RC3(x, v) (BIT_CLEAR_DARF_RC3(x) | BIT_DARF_RC3(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC3_V2 16 +#define BIT_MASK_DARF_RC3_V2 0x1f +#define BIT_DARF_RC3_V2(x) \ + (((x) & BIT_MASK_DARF_RC3_V2) << BIT_SHIFT_DARF_RC3_V2) +#define BITS_DARF_RC3_V2 (BIT_MASK_DARF_RC3_V2 << BIT_SHIFT_DARF_RC3_V2) +#define BIT_CLEAR_DARF_RC3_V2(x) ((x) & (~BITS_DARF_RC3_V2)) +#define BIT_GET_DARF_RC3_V2(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_V2) & BIT_MASK_DARF_RC3_V2) +#define BIT_SET_DARF_RC3_V2(x, v) \ + (BIT_CLEAR_DARF_RC3_V2(x) | BIT_DARF_RC3_V2(v)) -/* 2 REG_TRXRPT_MISS_CNT (Offset 0x04E3) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TRXRPT_MISS_CNT 0 -#define BIT_MASK_TRXRPT_MISS_CNT 0x7 -#define BIT_TRXRPT_MISS_CNT(x) (((x) & BIT_MASK_TRXRPT_MISS_CNT) << BIT_SHIFT_TRXRPT_MISS_CNT) -#define BIT_GET_TRXRPT_MISS_CNT(x) (((x) >> BIT_SHIFT_TRXRPT_MISS_CNT) & BIT_MASK_TRXRPT_MISS_CNT) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC3_V1 16 +#define BIT_MASK_DARF_RC3_V1 0x3f +#define BIT_DARF_RC3_V1(x) \ + (((x) & BIT_MASK_DARF_RC3_V1) << BIT_SHIFT_DARF_RC3_V1) +#define BITS_DARF_RC3_V1 (BIT_MASK_DARF_RC3_V1 << BIT_SHIFT_DARF_RC3_V1) +#define BIT_CLEAR_DARF_RC3_V1(x) ((x) & (~BITS_DARF_RC3_V1)) +#define BIT_GET_DARF_RC3_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_V1) & BIT_MASK_DARF_RC3_V1) +#define BIT_SET_DARF_RC3_V1(x, v) \ + (BIT_CLEAR_DARF_RC3_V1(x) | BIT_DARF_RC3_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ +/* 2 REG_DARFRC (Offset 0x0430) */ -#define BIT_VIDEO_JUST_DROP BIT(1) -#define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0) +#define BIT_SHIFT_DARF_RC2 8 +#define BIT_MASK_DARF_RC2 0x1f +#define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2) +#define BITS_DARF_RC2 (BIT_MASK_DARF_RC2 << BIT_SHIFT_DARF_RC2) +#define BIT_CLEAR_DARF_RC2(x) ((x) & (~BITS_DARF_RC2)) +#define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2) +#define BIT_SET_DARF_RC2(x, v) (BIT_CLEAR_DARF_RC2(x) | BIT_DARF_RC2(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC2_V2 8 +#define BIT_MASK_DARF_RC2_V2 0x1f +#define BIT_DARF_RC2_V2(x) \ + (((x) & BIT_MASK_DARF_RC2_V2) << BIT_SHIFT_DARF_RC2_V2) +#define BITS_DARF_RC2_V2 (BIT_MASK_DARF_RC2_V2 << BIT_SHIFT_DARF_RC2_V2) +#define BIT_CLEAR_DARF_RC2_V2(x) ((x) & (~BITS_DARF_RC2_V2)) +#define BIT_GET_DARF_RC2_V2(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_V2) & BIT_MASK_DARF_RC2_V2) +#define BIT_SET_DARF_RC2_V2(x, v) \ + (BIT_CLEAR_DARF_RC2_V2(x) | BIT_DARF_RC2_V2(v)) -/* 2 REG_BT_POLLUTE_PKT_CNT (Offset 0x04E8) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0 -#define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff -#define BIT_BT_POLLUTE_PKT_CNT(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT) -#define BIT_GET_BT_POLLUTE_PKT_CNT(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC2_V1 8 +#define BIT_MASK_DARF_RC2_V1 0x3f +#define BIT_DARF_RC2_V1(x) \ + (((x) & BIT_MASK_DARF_RC2_V1) << BIT_SHIFT_DARF_RC2_V1) +#define BITS_DARF_RC2_V1 (BIT_MASK_DARF_RC2_V1 << BIT_SHIFT_DARF_RC2_V1) +#define BIT_CLEAR_DARF_RC2_V1(x) ((x) & (~BITS_DARF_RC2_V1)) +#define BIT_GET_DARF_RC2_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_V1) & BIT_MASK_DARF_RC2_V1) +#define BIT_SET_DARF_RC2_V1(x, v) \ + (BIT_CLEAR_DARF_RC2_V1(x) | BIT_DARF_RC2_V1(v)) -/* 2 REG_PTCL_DBG (Offset 0x04EC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PTCL_DBG 0 -#define BIT_MASK_PTCL_DBG 0xffffffffL -#define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG) -#define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC1 0 +#define BIT_MASK_DARF_RC1 0x1f +#define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1) +#define BITS_DARF_RC1 (BIT_MASK_DARF_RC1 << BIT_SHIFT_DARF_RC1) +#define BIT_CLEAR_DARF_RC1(x) ((x) & (~BITS_DARF_RC1)) +#define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1) +#define BIT_SET_DARF_RC1(x, v) (BIT_CLEAR_DARF_RC1(x) | BIT_DARF_RC1(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC1_V2 0 +#define BIT_MASK_DARF_RC1_V2 0x1f +#define BIT_DARF_RC1_V2(x) \ + (((x) & BIT_MASK_DARF_RC1_V2) << BIT_SHIFT_DARF_RC1_V2) +#define BITS_DARF_RC1_V2 (BIT_MASK_DARF_RC1_V2 << BIT_SHIFT_DARF_RC1_V2) +#define BIT_CLEAR_DARF_RC1_V2(x) ((x) & (~BITS_DARF_RC1_V2)) +#define BIT_GET_DARF_RC1_V2(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_V2) & BIT_MASK_DARF_RC1_V2) +#define BIT_SET_DARF_RC1_V2(x, v) \ + (BIT_CLEAR_DARF_RC1_V2(x) | BIT_DARF_RC1_V2(v)) -/* 2 REG_PTCL_TX_RPT (Offset 0x04F0) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_AC_TX_RPT_INFO 0 -#define BIT_MASK_AC_TX_RPT_INFO 0xffffffffffffffffL -#define BIT_AC_TX_RPT_INFO(x) (((x) & BIT_MASK_AC_TX_RPT_INFO) << BIT_SHIFT_AC_TX_RPT_INFO) -#define BIT_GET_AC_TX_RPT_INFO(x) (((x) >> BIT_SHIFT_AC_TX_RPT_INFO) & BIT_MASK_AC_TX_RPT_INFO) +/* 2 REG_DARFRC (Offset 0x0430) */ +#define BIT_SHIFT_DARF_RC1_V1 0 +#define BIT_MASK_DARF_RC1_V1 0x3f +#define BIT_DARF_RC1_V1(x) \ + (((x) & BIT_MASK_DARF_RC1_V1) << BIT_SHIFT_DARF_RC1_V1) +#define BITS_DARF_RC1_V1 (BIT_MASK_DARF_RC1_V1 << BIT_SHIFT_DARF_RC1_V1) +#define BIT_CLEAR_DARF_RC1_V1(x) ((x) & (~BITS_DARF_RC1_V1)) +#define BIT_GET_DARF_RC1_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_V1) & BIT_MASK_DARF_RC1_V1) +#define BIT_SET_DARF_RC1_V1(x, v) \ + (BIT_CLEAR_DARF_RC1_V1(x) | BIT_DARF_RC1_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DARFRCH (Offset 0x0434) */ +#define BIT_SHIFT_DARF_RC8_V3 24 +#define BIT_MASK_DARF_RC8_V3 0x1f +#define BIT_DARF_RC8_V3(x) \ + (((x) & BIT_MASK_DARF_RC8_V3) << BIT_SHIFT_DARF_RC8_V3) +#define BITS_DARF_RC8_V3 (BIT_MASK_DARF_RC8_V3 << BIT_SHIFT_DARF_RC8_V3) +#define BIT_CLEAR_DARF_RC8_V3(x) ((x) & (~BITS_DARF_RC8_V3)) +#define BIT_GET_DARF_RC8_V3(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_V3) & BIT_MASK_DARF_RC8_V3) +#define BIT_SET_DARF_RC8_V3(x, v) \ + (BIT_CLEAR_DARF_RC8_V3(x) | BIT_DARF_RC8_V3(v)) -/* 2 REG_TXOP_EXTRA_CTRL (Offset 0x04F0) */ +#endif -#define BIT_TXOP_EFFICIENCY_EN BIT(0) +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_DARFRCH (Offset 0x0434) */ +#define BIT_SHIFT_DARF_RC8_V1 24 +#define BIT_MASK_DARF_RC8_V1 0x1f +#define BIT_DARF_RC8_V1(x) \ + (((x) & BIT_MASK_DARF_RC8_V1) << BIT_SHIFT_DARF_RC8_V1) +#define BITS_DARF_RC8_V1 (BIT_MASK_DARF_RC8_V1 << BIT_SHIFT_DARF_RC8_V1) +#define BIT_CLEAR_DARF_RC8_V1(x) ((x) & (~BITS_DARF_RC8_V1)) +#define BIT_GET_DARF_RC8_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_V1) & BIT_MASK_DARF_RC8_V1) +#define BIT_SET_DARF_RC8_V1(x, v) \ + (BIT_CLEAR_DARF_RC8_V1(x) | BIT_DARF_RC8_V1(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */ +/* 2 REG_DARFRCH (Offset 0x0434) */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31) +#define BIT_SHIFT_DARF_RC7_V3 16 +#define BIT_MASK_DARF_RC7_V3 0x1f +#define BIT_DARF_RC7_V3(x) \ + (((x) & BIT_MASK_DARF_RC7_V3) << BIT_SHIFT_DARF_RC7_V3) +#define BITS_DARF_RC7_V3 (BIT_MASK_DARF_RC7_V3 << BIT_SHIFT_DARF_RC7_V3) +#define BIT_CLEAR_DARF_RC7_V3(x) ((x) & (~BITS_DARF_RC7_V3)) +#define BIT_GET_DARF_RC7_V3(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_V3) & BIT_MASK_DARF_RC7_V3) +#define BIT_SET_DARF_RC7_V3(x, v) \ + (BIT_CLEAR_DARF_RC7_V3(x) | BIT_DARF_RC7_V3(v)) -#define BIT_SHIFT_GTAB_ID 28 -#define BIT_MASK_GTAB_ID 0x7 -#define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID) -#define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TRI_HEAD_ADDR 16 -#define BIT_MASK_TRI_HEAD_ADDR 0xfff -#define BIT_TRI_HEAD_ADDR(x) (((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR) -#define BIT_GET_TRI_HEAD_ADDR(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR) +/* 2 REG_DARFRCH (Offset 0x0434) */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15) +#define BIT_SHIFT_DARF_RC7_V1 16 +#define BIT_MASK_DARF_RC7_V1 0x1f +#define BIT_DARF_RC7_V1(x) \ + (((x) & BIT_MASK_DARF_RC7_V1) << BIT_SHIFT_DARF_RC7_V1) +#define BITS_DARF_RC7_V1 (BIT_MASK_DARF_RC7_V1 << BIT_SHIFT_DARF_RC7_V1) +#define BIT_CLEAR_DARF_RC7_V1(x) ((x) & (~BITS_DARF_RC7_V1)) +#define BIT_GET_DARF_RC7_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_V1) & BIT_MASK_DARF_RC7_V1) +#define BIT_SET_DARF_RC7_V1(x, v) \ + (BIT_CLEAR_DARF_RC7_V1(x) | BIT_DARF_RC7_V1(v)) -#define BIT_SHIFT_GTAB_ID_V1 12 -#define BIT_MASK_GTAB_ID_V1 0x7 -#define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1) -#define BIT_GET_GTAB_ID_V1(x) (((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1) +#endif -#define BIT_DROP_TH_EN BIT(8) +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_DROP_TH 0 -#define BIT_MASK_DROP_TH 0xff -#define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH) -#define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH) +/* 2 REG_DARFRCH (Offset 0x0434) */ +#define BIT_SHIFT_DARF_RC6_V3 8 +#define BIT_MASK_DARF_RC6_V3 0x1f +#define BIT_DARF_RC6_V3(x) \ + (((x) & BIT_MASK_DARF_RC6_V3) << BIT_SHIFT_DARF_RC6_V3) +#define BITS_DARF_RC6_V3 (BIT_MASK_DARF_RC6_V3 << BIT_SHIFT_DARF_RC6_V3) +#define BIT_CLEAR_DARF_RC6_V3(x) ((x) & (~BITS_DARF_RC6_V3)) +#define BIT_GET_DARF_RC6_V3(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_V3) & BIT_MASK_DARF_RC6_V3) +#define BIT_SET_DARF_RC6_V3(x, v) \ + (BIT_CLEAR_DARF_RC6_V3(x) | BIT_DARF_RC6_V3(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_DARFRCH (Offset 0x0434) */ +#define BIT_SHIFT_DARF_RC6_V1 8 +#define BIT_MASK_DARF_RC6_V1 0x1f +#define BIT_DARF_RC6_V1(x) \ + (((x) & BIT_MASK_DARF_RC6_V1) << BIT_SHIFT_DARF_RC6_V1) +#define BITS_DARF_RC6_V1 (BIT_MASK_DARF_RC6_V1 << BIT_SHIFT_DARF_RC6_V1) +#define BIT_CLEAR_DARF_RC6_V1(x) ((x) & (~BITS_DARF_RC6_V1)) +#define BIT_GET_DARF_RC6_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_V1) & BIT_MASK_DARF_RC6_V1) +#define BIT_SET_DARF_RC6_V1(x, v) \ + (BIT_CLEAR_DARF_RC6_V1(x) | BIT_DARF_RC6_V1(v)) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#endif -#define BIT_MOREDATA_CTRL2_EN BIT(19) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_DARFRCH (Offset 0x0434) */ +#define BIT_SHIFT_DARF_RC5_V3 0 +#define BIT_MASK_DARF_RC5_V3 0x1f +#define BIT_DARF_RC5_V3(x) \ + (((x) & BIT_MASK_DARF_RC5_V3) << BIT_SHIFT_DARF_RC5_V3) +#define BITS_DARF_RC5_V3 (BIT_MASK_DARF_RC5_V3 << BIT_SHIFT_DARF_RC5_V3) +#define BIT_CLEAR_DARF_RC5_V3(x) ((x) & (~BITS_DARF_RC5_V3)) +#define BIT_GET_DARF_RC5_V3(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_V3) & BIT_MASK_DARF_RC5_V3) +#define BIT_SET_DARF_RC5_V3(x, v) \ + (BIT_CLEAR_DARF_RC5_V3(x) | BIT_DARF_RC5_V3(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +/* 2 REG_DARFRCH (Offset 0x0434) */ -#define BIT_MOREDATA_CTRL2_EN_V2 BIT(19) +#define BIT_SHIFT_DARF_RC5_V1 0 +#define BIT_MASK_DARF_RC5_V1 0x1f +#define BIT_DARF_RC5_V1(x) \ + (((x) & BIT_MASK_DARF_RC5_V1) << BIT_SHIFT_DARF_RC5_V1) +#define BITS_DARF_RC5_V1 (BIT_MASK_DARF_RC5_V1 << BIT_SHIFT_DARF_RC5_V1) +#define BIT_CLEAR_DARF_RC5_V1(x) ((x) & (~BITS_DARF_RC5_V1)) +#define BIT_GET_DARF_RC5_V1(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_V1) & BIT_MASK_DARF_RC5_V1) +#define BIT_SET_DARF_RC5_V1(x, v) \ + (BIT_CLEAR_DARF_RC5_V1(x) | BIT_DARF_RC5_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_RARFRC (Offset 0x0438) */ +#define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC8 0x1f +#define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8) +#define BITS_RARF_RC8 (BIT_MASK_RARF_RC8 << BIT_SHIFT_RARF_RC8) +#define BIT_CLEAR_RARF_RC8(x) ((x) & (~BITS_RARF_RC8)) +#define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8) +#define BIT_SET_RARF_RC8(x, v) (BIT_CLEAR_RARF_RC8(x) | BIT_RARF_RC8(v)) + +#define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC7 0x1f +#define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7) +#define BITS_RARF_RC7 (BIT_MASK_RARF_RC7 << BIT_SHIFT_RARF_RC7) +#define BIT_CLEAR_RARF_RC7(x) ((x) & (~BITS_RARF_RC7)) +#define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7) +#define BIT_SET_RARF_RC7(x, v) (BIT_CLEAR_RARF_RC7(x) | BIT_RARF_RC7(v)) + +#define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC6 0x1f +#define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6) +#define BITS_RARF_RC6 (BIT_MASK_RARF_RC6 << BIT_SHIFT_RARF_RC6) +#define BIT_CLEAR_RARF_RC6(x) ((x) & (~BITS_RARF_RC6)) +#define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6) +#define BIT_SET_RARF_RC6(x, v) (BIT_CLEAR_RARF_RC6(x) | BIT_RARF_RC6(v)) + +#define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC5 0x1f +#define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5) +#define BITS_RARF_RC5 (BIT_MASK_RARF_RC5 << BIT_SHIFT_RARF_RC5) +#define BIT_CLEAR_RARF_RC5(x) ((x) & (~BITS_RARF_RC5)) +#define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5) +#define BIT_SET_RARF_RC5(x, v) (BIT_CLEAR_RARF_RC5(x) | BIT_RARF_RC5(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +/* 2 REG_RARFRC (Offset 0x0438) */ -#define BIT_MOREDATA_CTRL1_EN BIT(18) +#define BIT_SHIFT_RARF_RC4 24 +#define BIT_MASK_RARF_RC4 0x1f +#define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4) +#define BITS_RARF_RC4 (BIT_MASK_RARF_RC4 << BIT_SHIFT_RARF_RC4) +#define BIT_CLEAR_RARF_RC4(x) ((x) & (~BITS_RARF_RC4)) +#define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4) +#define BIT_SET_RARF_RC4(x, v) (BIT_CLEAR_RARF_RC4(x) | BIT_RARF_RC4(v)) + +#define BIT_SHIFT_RARF_RC3 16 +#define BIT_MASK_RARF_RC3 0x1f +#define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3) +#define BITS_RARF_RC3 (BIT_MASK_RARF_RC3 << BIT_SHIFT_RARF_RC3) +#define BIT_CLEAR_RARF_RC3(x) ((x) & (~BITS_RARF_RC3)) +#define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3) +#define BIT_SET_RARF_RC3(x, v) (BIT_CLEAR_RARF_RC3(x) | BIT_RARF_RC3(v)) + +#define BIT_SHIFT_RARF_RC2 8 +#define BIT_MASK_RARF_RC2 0x1f +#define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2) +#define BITS_RARF_RC2 (BIT_MASK_RARF_RC2 << BIT_SHIFT_RARF_RC2) +#define BIT_CLEAR_RARF_RC2(x) ((x) & (~BITS_RARF_RC2)) +#define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2) +#define BIT_SET_RARF_RC2(x, v) (BIT_CLEAR_RARF_RC2(x) | BIT_RARF_RC2(v)) + +#define BIT_SHIFT_RARF_RC1 0 +#define BIT_MASK_RARF_RC1 0x1f +#define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1) +#define BITS_RARF_RC1 (BIT_MASK_RARF_RC1 << BIT_SHIFT_RARF_RC1) +#define BIT_CLEAR_RARF_RC1(x) ((x) & (~BITS_RARF_RC1)) +#define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1) +#define BIT_SET_RARF_RC1(x, v) (BIT_CLEAR_RARF_RC1(x) | BIT_RARF_RC1(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_RARFRCH (Offset 0x043C) */ + +#define BIT_SHIFT_RARF_RC8_V1 24 +#define BIT_MASK_RARF_RC8_V1 0x1f +#define BIT_RARF_RC8_V1(x) \ + (((x) & BIT_MASK_RARF_RC8_V1) << BIT_SHIFT_RARF_RC8_V1) +#define BITS_RARF_RC8_V1 (BIT_MASK_RARF_RC8_V1 << BIT_SHIFT_RARF_RC8_V1) +#define BIT_CLEAR_RARF_RC8_V1(x) ((x) & (~BITS_RARF_RC8_V1)) +#define BIT_GET_RARF_RC8_V1(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_V1) & BIT_MASK_RARF_RC8_V1) +#define BIT_SET_RARF_RC8_V1(x, v) \ + (BIT_CLEAR_RARF_RC8_V1(x) | BIT_RARF_RC8_V1(v)) + +#define BIT_SHIFT_RARF_RC7_V1 16 +#define BIT_MASK_RARF_RC7_V1 0x1f +#define BIT_RARF_RC7_V1(x) \ + (((x) & BIT_MASK_RARF_RC7_V1) << BIT_SHIFT_RARF_RC7_V1) +#define BITS_RARF_RC7_V1 (BIT_MASK_RARF_RC7_V1 << BIT_SHIFT_RARF_RC7_V1) +#define BIT_CLEAR_RARF_RC7_V1(x) ((x) & (~BITS_RARF_RC7_V1)) +#define BIT_GET_RARF_RC7_V1(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_V1) & BIT_MASK_RARF_RC7_V1) +#define BIT_SET_RARF_RC7_V1(x, v) \ + (BIT_CLEAR_RARF_RC7_V1(x) | BIT_RARF_RC7_V1(v)) + +#define BIT_SHIFT_RARF_RC6_V1 8 +#define BIT_MASK_RARF_RC6_V1 0x1f +#define BIT_RARF_RC6_V1(x) \ + (((x) & BIT_MASK_RARF_RC6_V1) << BIT_SHIFT_RARF_RC6_V1) +#define BITS_RARF_RC6_V1 (BIT_MASK_RARF_RC6_V1 << BIT_SHIFT_RARF_RC6_V1) +#define BIT_CLEAR_RARF_RC6_V1(x) ((x) & (~BITS_RARF_RC6_V1)) +#define BIT_GET_RARF_RC6_V1(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_V1) & BIT_MASK_RARF_RC6_V1) +#define BIT_SET_RARF_RC6_V1(x, v) \ + (BIT_CLEAR_RARF_RC6_V1(x) | BIT_RARF_RC6_V1(v)) + +#define BIT_SHIFT_RARF_RC5_V1 0 +#define BIT_MASK_RARF_RC5_V1 0x1f +#define BIT_RARF_RC5_V1(x) \ + (((x) & BIT_MASK_RARF_RC5_V1) << BIT_SHIFT_RARF_RC5_V1) +#define BITS_RARF_RC5_V1 (BIT_MASK_RARF_RC5_V1 << BIT_SHIFT_RARF_RC5_V1) +#define BIT_CLEAR_RARF_RC5_V1(x) ((x) & (~BITS_RARF_RC5_V1)) +#define BIT_GET_RARF_RC5_V1(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_V1) & BIT_MASK_RARF_RC5_V1) +#define BIT_SET_RARF_RC5_V1(x, v) \ + (BIT_CLEAR_RARF_RC5_V1(x) | BIT_RARF_RC5_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_RRSR (Offset 0x0440) */ +#define BIT_EN_VHTBW_FALL BIT(31) +#define BIT_EN_HTBW_FALL BIT(30) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +/* 2 REG_RRSR (Offset 0x0440) */ -#define BIT_MOREDATA_CTRL1_EN_V2 BIT(18) +#define BIT_SHIFT_RRSR_RSC 21 +#define BIT_MASK_RRSR_RSC 0x3 +#define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC) +#define BITS_RRSR_RSC (BIT_MASK_RRSR_RSC << BIT_SHIFT_RRSR_RSC) +#define BIT_CLEAR_RRSR_RSC(x) ((x) & (~BITS_RRSR_RSC)) +#define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC) +#define BIT_SET_RRSR_RSC(x, v) (BIT_CLEAR_RRSR_RSC(x) | BIT_RRSR_RSC(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RRSR (Offset 0x0440) */ +#define BIT_RRSR_BW BIT(20) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#endif -#define BIT_EN_BCN_TRXRPT BIT(17) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_RRSR (Offset 0x0440) */ +#define BIT_SHIFT_RRSC_BITMAP 0 +#define BIT_MASK_RRSC_BITMAP 0xfffff +#define BIT_RRSC_BITMAP(x) \ + (((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP) +#define BITS_RRSC_BITMAP (BIT_MASK_RRSC_BITMAP << BIT_SHIFT_RRSC_BITMAP) +#define BIT_CLEAR_RRSC_BITMAP(x) ((x) & (~BITS_RRSC_BITMAP)) +#define BIT_GET_RRSC_BITMAP(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP) +#define BIT_SET_RRSC_BITMAP(x, v) \ + (BIT_CLEAR_RRSC_BITMAP(x) | BIT_RRSC_BITMAP(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +/* 2 REG_ARFR0 (Offset 0x0444) */ -#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE BIT(16) +#define BIT_SHIFT_ARFR0_V1 0 +#define BIT_MASK_ARFR0_V1 0xffffffffffffffffL +#define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1) +#define BITS_ARFR0_V1 (BIT_MASK_ARFR0_V1 << BIT_SHIFT_ARFR0_V1) +#define BIT_CLEAR_ARFR0_V1(x) ((x) & (~BITS_ARFR0_V1)) +#define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1) +#define BIT_SET_ARFR0_V1(x, v) (BIT_CLEAR_ARFR0_V1(x) | BIT_ARFR0_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_ARFR0 (Offset 0x0444) */ +#define BIT_SHIFT_ARFRL0 0 +#define BIT_MASK_ARFRL0 0xffffffffL +#define BIT_ARFRL0(x) (((x) & BIT_MASK_ARFRL0) << BIT_SHIFT_ARFRL0) +#define BITS_ARFRL0 (BIT_MASK_ARFRL0 << BIT_SHIFT_ARFRL0) +#define BIT_CLEAR_ARFRL0(x) ((x) & (~BITS_ARFRL0)) +#define BIT_GET_ARFRL0(x) (((x) >> BIT_SHIFT_ARFRL0) & BIT_MASK_ARFRL0) +#define BIT_SET_ARFRL0(x, v) (BIT_CLEAR_ARFRL0(x) | BIT_ARFRL0(v)) + +/* 2 REG_ARFRH0 (Offset 0x0448) */ + +#define BIT_SHIFT_ARFRH0 0 +#define BIT_MASK_ARFRH0 0xffffffffL +#define BIT_ARFRH0(x) (((x) & BIT_MASK_ARFRH0) << BIT_SHIFT_ARFRH0) +#define BITS_ARFRH0 (BIT_MASK_ARFRH0 << BIT_SHIFT_ARFRH0) +#define BIT_CLEAR_ARFRH0(x) ((x) & (~BITS_ARFRH0)) +#define BIT_GET_ARFRH0(x) (((x) >> BIT_SHIFT_ARFRH0) & BIT_MASK_ARFRH0) +#define BIT_SET_ARFRH0(x, v) (BIT_CLEAR_ARFRH0(x) | BIT_ARFRH0(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_REG_ARFR_WT0 (Offset 0x044C) */ + +#define BIT_SHIFT_RATE7_WEIGHTING 28 +#define BIT_MASK_RATE7_WEIGHTING 0xf +#define BIT_RATE7_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE7_WEIGHTING) << BIT_SHIFT_RATE7_WEIGHTING) +#define BITS_RATE7_WEIGHTING \ + (BIT_MASK_RATE7_WEIGHTING << BIT_SHIFT_RATE7_WEIGHTING) +#define BIT_CLEAR_RATE7_WEIGHTING(x) ((x) & (~BITS_RATE7_WEIGHTING)) +#define BIT_GET_RATE7_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE7_WEIGHTING) & BIT_MASK_RATE7_WEIGHTING) +#define BIT_SET_RATE7_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE7_WEIGHTING(x) | BIT_RATE7_WEIGHTING(v)) + +#define BIT_SHIFT_RATE6_WEIGHTING 24 +#define BIT_MASK_RATE6_WEIGHTING 0xf +#define BIT_RATE6_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE6_WEIGHTING) << BIT_SHIFT_RATE6_WEIGHTING) +#define BITS_RATE6_WEIGHTING \ + (BIT_MASK_RATE6_WEIGHTING << BIT_SHIFT_RATE6_WEIGHTING) +#define BIT_CLEAR_RATE6_WEIGHTING(x) ((x) & (~BITS_RATE6_WEIGHTING)) +#define BIT_GET_RATE6_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE6_WEIGHTING) & BIT_MASK_RATE6_WEIGHTING) +#define BIT_SET_RATE6_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE6_WEIGHTING(x) | BIT_RATE6_WEIGHTING(v)) + +#define BIT_SHIFT_RATE5_WEIGHTING 20 +#define BIT_MASK_RATE5_WEIGHTING 0xf +#define BIT_RATE5_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE5_WEIGHTING) << BIT_SHIFT_RATE5_WEIGHTING) +#define BITS_RATE5_WEIGHTING \ + (BIT_MASK_RATE5_WEIGHTING << BIT_SHIFT_RATE5_WEIGHTING) +#define BIT_CLEAR_RATE5_WEIGHTING(x) ((x) & (~BITS_RATE5_WEIGHTING)) +#define BIT_GET_RATE5_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE5_WEIGHTING) & BIT_MASK_RATE5_WEIGHTING) +#define BIT_SET_RATE5_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE5_WEIGHTING(x) | BIT_RATE5_WEIGHTING(v)) + +#define BIT_SHIFT_RATE4_WEIGHTING 16 +#define BIT_MASK_RATE4_WEIGHTING 0xf +#define BIT_RATE4_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE4_WEIGHTING) << BIT_SHIFT_RATE4_WEIGHTING) +#define BITS_RATE4_WEIGHTING \ + (BIT_MASK_RATE4_WEIGHTING << BIT_SHIFT_RATE4_WEIGHTING) +#define BIT_CLEAR_RATE4_WEIGHTING(x) ((x) & (~BITS_RATE4_WEIGHTING)) +#define BIT_GET_RATE4_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE4_WEIGHTING) & BIT_MASK_RATE4_WEIGHTING) +#define BIT_SET_RATE4_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE4_WEIGHTING(x) | BIT_RATE4_WEIGHTING(v)) + +#define BIT_SHIFT_RATE3_WEIGHTING 12 +#define BIT_MASK_RATE3_WEIGHTING 0xf +#define BIT_RATE3_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE3_WEIGHTING) << BIT_SHIFT_RATE3_WEIGHTING) +#define BITS_RATE3_WEIGHTING \ + (BIT_MASK_RATE3_WEIGHTING << BIT_SHIFT_RATE3_WEIGHTING) +#define BIT_CLEAR_RATE3_WEIGHTING(x) ((x) & (~BITS_RATE3_WEIGHTING)) +#define BIT_GET_RATE3_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE3_WEIGHTING) & BIT_MASK_RATE3_WEIGHTING) +#define BIT_SET_RATE3_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE3_WEIGHTING(x) | BIT_RATE3_WEIGHTING(v)) + +#define BIT_SHIFT_RATE2_WEIGHTING 8 +#define BIT_MASK_RATE2_WEIGHTING 0xf +#define BIT_RATE2_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE2_WEIGHTING) << BIT_SHIFT_RATE2_WEIGHTING) +#define BITS_RATE2_WEIGHTING \ + (BIT_MASK_RATE2_WEIGHTING << BIT_SHIFT_RATE2_WEIGHTING) +#define BIT_CLEAR_RATE2_WEIGHTING(x) ((x) & (~BITS_RATE2_WEIGHTING)) +#define BIT_GET_RATE2_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE2_WEIGHTING) & BIT_MASK_RATE2_WEIGHTING) +#define BIT_SET_RATE2_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE2_WEIGHTING(x) | BIT_RATE2_WEIGHTING(v)) + +#define BIT_SHIFT_RATE1_WEIGHTING 4 +#define BIT_MASK_RATE1_WEIGHTING 0xf +#define BIT_RATE1_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE1_WEIGHTING) << BIT_SHIFT_RATE1_WEIGHTING) +#define BITS_RATE1_WEIGHTING \ + (BIT_MASK_RATE1_WEIGHTING << BIT_SHIFT_RATE1_WEIGHTING) +#define BIT_CLEAR_RATE1_WEIGHTING(x) ((x) & (~BITS_RATE1_WEIGHTING)) +#define BIT_GET_RATE1_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE1_WEIGHTING) & BIT_MASK_RATE1_WEIGHTING) +#define BIT_SET_RATE1_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE1_WEIGHTING(x) | BIT_RATE1_WEIGHTING(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_DUMMY_PAGE4_V1 (Offset 0x04FC) */ +/* 2 REG_ARFR1_V1 (Offset 0x044C) */ -#define BIT_BCN_EN_EXTHWSEQ BIT(1) -#define BIT_BCN_EN_HWSEQ BIT(0) +#define BIT_SHIFT_ARFR1_V1 0 +#define BIT_MASK_ARFR1_V1 0xffffffffffffffffL +#define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1) +#define BITS_ARFR1_V1 (BIT_MASK_ARFR1_V1 << BIT_SHIFT_ARFR1_V1) +#define BIT_CLEAR_ARFR1_V1(x) ((x) & (~BITS_ARFR1_V1)) +#define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1) +#define BIT_SET_ARFR1_V1(x, v) (BIT_CLEAR_ARFR1_V1(x) | BIT_ARFR1_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ARFR1_V1 (Offset 0x044C) */ +#define BIT_SHIFT_ARFRL1 0 +#define BIT_MASK_ARFRL1 0xffffffffL +#define BIT_ARFRL1(x) (((x) & BIT_MASK_ARFRL1) << BIT_SHIFT_ARFRL1) +#define BITS_ARFRL1 (BIT_MASK_ARFRL1 << BIT_SHIFT_ARFRL1) +#define BIT_CLEAR_ARFRL1(x) ((x) & (~BITS_ARFRL1)) +#define BIT_GET_ARFRL1(x) (((x) >> BIT_SHIFT_ARFRL1) & BIT_MASK_ARFRL1) +#define BIT_SET_ARFRL1(x, v) (BIT_CLEAR_ARFRL1(x) | BIT_ARFRL1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_REG_ARFR_WT0 (Offset 0x044C) */ + +#define BIT_SHIFT_RATE0_WEIGHTING 0 +#define BIT_MASK_RATE0_WEIGHTING 0xf +#define BIT_RATE0_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE0_WEIGHTING) << BIT_SHIFT_RATE0_WEIGHTING) +#define BITS_RATE0_WEIGHTING \ + (BIT_MASK_RATE0_WEIGHTING << BIT_SHIFT_RATE0_WEIGHTING) +#define BIT_CLEAR_RATE0_WEIGHTING(x) ((x) & (~BITS_RATE0_WEIGHTING)) +#define BIT_GET_RATE0_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE0_WEIGHTING) & BIT_MASK_RATE0_WEIGHTING) +#define BIT_SET_RATE0_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE0_WEIGHTING(x) | BIT_RATE0_WEIGHTING(v)) + +/* 2 REG_REG_ARFR_WT1 (Offset 0x0450) */ + +#define BIT_SHIFT_RATE15_WEIGHTING 28 +#define BIT_MASK_RATE15_WEIGHTING 0xf +#define BIT_RATE15_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE15_WEIGHTING) << BIT_SHIFT_RATE15_WEIGHTING) +#define BITS_RATE15_WEIGHTING \ + (BIT_MASK_RATE15_WEIGHTING << BIT_SHIFT_RATE15_WEIGHTING) +#define BIT_CLEAR_RATE15_WEIGHTING(x) ((x) & (~BITS_RATE15_WEIGHTING)) +#define BIT_GET_RATE15_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE15_WEIGHTING) & BIT_MASK_RATE15_WEIGHTING) +#define BIT_SET_RATE15_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE15_WEIGHTING(x) | BIT_RATE15_WEIGHTING(v)) + +#define BIT_SHIFT_RATE14_WEIGHTING 24 +#define BIT_MASK_RATE14_WEIGHTING 0xf +#define BIT_RATE14_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE14_WEIGHTING) << BIT_SHIFT_RATE14_WEIGHTING) +#define BITS_RATE14_WEIGHTING \ + (BIT_MASK_RATE14_WEIGHTING << BIT_SHIFT_RATE14_WEIGHTING) +#define BIT_CLEAR_RATE14_WEIGHTING(x) ((x) & (~BITS_RATE14_WEIGHTING)) +#define BIT_GET_RATE14_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE14_WEIGHTING) & BIT_MASK_RATE14_WEIGHTING) +#define BIT_SET_RATE14_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE14_WEIGHTING(x) | BIT_RATE14_WEIGHTING(v)) + +#define BIT_SHIFT_RATE13_WEIGHTING 20 +#define BIT_MASK_RATE13_WEIGHTING 0xf +#define BIT_RATE13_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE13_WEIGHTING) << BIT_SHIFT_RATE13_WEIGHTING) +#define BITS_RATE13_WEIGHTING \ + (BIT_MASK_RATE13_WEIGHTING << BIT_SHIFT_RATE13_WEIGHTING) +#define BIT_CLEAR_RATE13_WEIGHTING(x) ((x) & (~BITS_RATE13_WEIGHTING)) +#define BIT_GET_RATE13_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE13_WEIGHTING) & BIT_MASK_RATE13_WEIGHTING) +#define BIT_SET_RATE13_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE13_WEIGHTING(x) | BIT_RATE13_WEIGHTING(v)) + +#define BIT_SHIFT_RATE12_WEIGHTING 16 +#define BIT_MASK_RATE12_WEIGHTING 0xf +#define BIT_RATE12_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE12_WEIGHTING) << BIT_SHIFT_RATE12_WEIGHTING) +#define BITS_RATE12_WEIGHTING \ + (BIT_MASK_RATE12_WEIGHTING << BIT_SHIFT_RATE12_WEIGHTING) +#define BIT_CLEAR_RATE12_WEIGHTING(x) ((x) & (~BITS_RATE12_WEIGHTING)) +#define BIT_GET_RATE12_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE12_WEIGHTING) & BIT_MASK_RATE12_WEIGHTING) +#define BIT_SET_RATE12_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE12_WEIGHTING(x) | BIT_RATE12_WEIGHTING(v)) + +#define BIT_SHIFT_RATE11_WEIGHTING 12 +#define BIT_MASK_RATE11_WEIGHTING 0xf +#define BIT_RATE11_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE11_WEIGHTING) << BIT_SHIFT_RATE11_WEIGHTING) +#define BITS_RATE11_WEIGHTING \ + (BIT_MASK_RATE11_WEIGHTING << BIT_SHIFT_RATE11_WEIGHTING) +#define BIT_CLEAR_RATE11_WEIGHTING(x) ((x) & (~BITS_RATE11_WEIGHTING)) +#define BIT_GET_RATE11_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE11_WEIGHTING) & BIT_MASK_RATE11_WEIGHTING) +#define BIT_SET_RATE11_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE11_WEIGHTING(x) | BIT_RATE11_WEIGHTING(v)) + +#define BIT_SHIFT_RATE10_WEIGHTING 8 +#define BIT_MASK_RATE10_WEIGHTING 0xf +#define BIT_RATE10_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE10_WEIGHTING) << BIT_SHIFT_RATE10_WEIGHTING) +#define BITS_RATE10_WEIGHTING \ + (BIT_MASK_RATE10_WEIGHTING << BIT_SHIFT_RATE10_WEIGHTING) +#define BIT_CLEAR_RATE10_WEIGHTING(x) ((x) & (~BITS_RATE10_WEIGHTING)) +#define BIT_GET_RATE10_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE10_WEIGHTING) & BIT_MASK_RATE10_WEIGHTING) +#define BIT_SET_RATE10_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE10_WEIGHTING(x) | BIT_RATE10_WEIGHTING(v)) + +#define BIT_SHIFT_RATE9_WEIGHTING 4 +#define BIT_MASK_RATE9_WEIGHTING 0xf +#define BIT_RATE9_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE9_WEIGHTING) << BIT_SHIFT_RATE9_WEIGHTING) +#define BITS_RATE9_WEIGHTING \ + (BIT_MASK_RATE9_WEIGHTING << BIT_SHIFT_RATE9_WEIGHTING) +#define BIT_CLEAR_RATE9_WEIGHTING(x) ((x) & (~BITS_RATE9_WEIGHTING)) +#define BIT_GET_RATE9_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE9_WEIGHTING) & BIT_MASK_RATE9_WEIGHTING) +#define BIT_SET_RATE9_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE9_WEIGHTING(x) | BIT_RATE9_WEIGHTING(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_ARFRH1 (Offset 0x0450) */ + +#define BIT_SHIFT_ARFRH1 0 +#define BIT_MASK_ARFRH1 0xffffffffL +#define BIT_ARFRH1(x) (((x) & BIT_MASK_ARFRH1) << BIT_SHIFT_ARFRH1) +#define BITS_ARFRH1 (BIT_MASK_ARFRH1 << BIT_SHIFT_ARFRH1) +#define BIT_CLEAR_ARFRH1(x) ((x) & (~BITS_ARFRH1)) +#define BIT_GET_ARFRH1(x) (((x) >> BIT_SHIFT_ARFRH1) & BIT_MASK_ARFRH1) +#define BIT_SET_ARFRH1(x, v) (BIT_CLEAR_ARFRH1(x) | BIT_ARFRH1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_REG_ARFR_WT1 (Offset 0x0450) */ + +#define BIT_SHIFT_RATE8_WEIGHTING 0 +#define BIT_MASK_RATE8_WEIGHTING 0xf +#define BIT_RATE8_WEIGHTING(x) \ + (((x) & BIT_MASK_RATE8_WEIGHTING) << BIT_SHIFT_RATE8_WEIGHTING) +#define BITS_RATE8_WEIGHTING \ + (BIT_MASK_RATE8_WEIGHTING << BIT_SHIFT_RATE8_WEIGHTING) +#define BIT_CLEAR_RATE8_WEIGHTING(x) ((x) & (~BITS_RATE8_WEIGHTING)) +#define BIT_GET_RATE8_WEIGHTING(x) \ + (((x) >> BIT_SHIFT_RATE8_WEIGHTING) & BIT_MASK_RATE8_WEIGHTING) +#define BIT_SET_RATE8_WEIGHTING(x, v) \ + (BIT_CLEAR_RATE8_WEIGHTING(x) | BIT_RATE8_WEIGHTING(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_MOREDATA (Offset 0x04FE) */ +/* 2 REG_CCK_CHECK (Offset 0x0454) */ -#define BIT_MOREDATA_CTRL2_EN_V1 BIT(3) -#define BIT_MOREDATA_CTRL1_EN_V1 BIT(2) -#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0) +#define BIT_CHECK_CCK_EN BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_EN_BCN_PKT_REL BIT(6) -/* 2 REG_EDCA_VO_PARAM (Offset 0x0500) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TXOPLIMIT 16 -#define BIT_MASK_TXOPLIMIT 0x7ff -#define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT) -#define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_EN_BCN_PKT_REL_P0 BIT(6) -#define BIT_SHIFT_CW 8 -#define BIT_MASK_CW 0xff -#define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW) -#define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_AIFS 0 -#define BIT_MASK_AIFS 0xff -#define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS) -#define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_BCN_PORT_SEL BIT(5) +#define BIT_MOREDATA_BYPASS BIT(4) -/* 2 REG_BCNTCFG (Offset 0x0510) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCNCW_MAX 12 -#define BIT_MASK_BCNCW_MAX 0xf -#define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX) -#define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3) -#define BIT_SHIFT_BCNCW_MIN 8 -#define BIT_MASK_BCNCW_MIN 0xf -#define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN) -#define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCNIFS 0 -#define BIT_MASK_BCNIFS 0xff -#define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS) -#define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P0 BIT(3) -/* 2 REG_PIFS (Offset 0x0512) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PIFS 0 -#define BIT_MASK_PIFS 0xff -#define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS) -#define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_EN_SET_MOREDATA BIT(2) -/* 2 REG_RDG_PIFS (Offset 0x0513) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RDG_PIFS 0 -#define BIT_MASK_RDG_PIFS 0xff -#define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS) -#define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT_R_EN_SET_MOREDATA BIT(2) -/* 2 REG_SIFS (Offset 0x0514) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SIFS_OFDM_TRX 24 -#define BIT_MASK_SIFS_OFDM_TRX 0xff -#define BIT_SIFS_OFDM_TRX(x) (((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX) -#define BIT_GET_SIFS_OFDM_TRX(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX) +/* 2 REG_CCK_CHECK (Offset 0x0454) */ +#define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1) +#define BIT__R_MACID_RELEASE_EN BIT(0) -#define BIT_SHIFT_SIFS_CCK_TRX 16 -#define BIT_MASK_SIFS_CCK_TRX 0xff -#define BIT_SIFS_CCK_TRX(x) (((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX) -#define BIT_GET_SIFS_CCK_TRX(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SIFS_OFDM_CTX 8 -#define BIT_MASK_SIFS_OFDM_CTX 0xff -#define BIT_SIFS_OFDM_CTX(x) (((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX) -#define BIT_GET_SIFS_OFDM_CTX(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX) +/* 2 REG_AMPDU_MAX_TIME_V1 (Offset 0x0455) */ +#define BIT_SHIFT_AMPDU_MAX_TIME 0 +#define BIT_MASK_AMPDU_MAX_TIME 0xff +#define BIT_AMPDU_MAX_TIME(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME) +#define BITS_AMPDU_MAX_TIME \ + (BIT_MASK_AMPDU_MAX_TIME << BIT_SHIFT_AMPDU_MAX_TIME) +#define BIT_CLEAR_AMPDU_MAX_TIME(x) ((x) & (~BITS_AMPDU_MAX_TIME)) +#define BIT_GET_AMPDU_MAX_TIME(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME) +#define BIT_SET_AMPDU_MAX_TIME(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME(x) | BIT_AMPDU_MAX_TIME(v)) -#define BIT_SHIFT_SIFS_CCK_CTX 0 -#define BIT_MASK_SIFS_CCK_CTX 0xff -#define BIT_SIFS_CCK_CTX(x) (((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX) -#define BIT_GET_SIFS_CCK_CTX(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_TSFTR_SYN_OFFSET (Offset 0x0518) */ +/* 2 REG_AMPDU_BURST_CTRL (Offset 0x0455) */ +#define BIT_AMPDU_BURST_GLOBAL_EN BIT(0) -#define BIT_SHIFT_TSFTR_SNC_OFFSET 0 -#define BIT_MASK_TSFTR_SNC_OFFSET 0xffff -#define BIT_TSFTR_SNC_OFFSET(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET) -#define BIT_GET_TSFTR_SNC_OFFSET(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_AGGR_BREAK_TIME (Offset 0x051A) */ +/* 2 REG_BCNQ2_HEAD (Offset 0x0455) */ +#define BIT_SHIFT_BCNQ2_HEAD 0 +#define BIT_MASK_BCNQ2_HEAD 0xff +#define BIT_BCNQ2_HEAD(x) (((x) & BIT_MASK_BCNQ2_HEAD) << BIT_SHIFT_BCNQ2_HEAD) +#define BITS_BCNQ2_HEAD (BIT_MASK_BCNQ2_HEAD << BIT_SHIFT_BCNQ2_HEAD) +#define BIT_CLEAR_BCNQ2_HEAD(x) ((x) & (~BITS_BCNQ2_HEAD)) +#define BIT_GET_BCNQ2_HEAD(x) \ + (((x) >> BIT_SHIFT_BCNQ2_HEAD) & BIT_MASK_BCNQ2_HEAD) +#define BIT_SET_BCNQ2_HEAD(x, v) (BIT_CLEAR_BCNQ2_HEAD(x) | BIT_BCNQ2_HEAD(v)) -#define BIT_SHIFT_AGGR_BK_TIME 0 -#define BIT_MASK_AGGR_BK_TIME 0xff -#define BIT_AGGR_BK_TIME(x) (((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME) -#define BIT_GET_AGGR_BK_TIME(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_SLOT (Offset 0x051B) */ +/* 2 REG_BCNQ1_BDNY_V1 (Offset 0x0456) */ +#define BIT_SHIFT_BCNQ1_PGBNDY_V1 0 +#define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff +#define BIT_BCNQ1_PGBNDY_V1(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1) +#define BITS_BCNQ1_PGBNDY_V1 \ + (BIT_MASK_BCNQ1_PGBNDY_V1 << BIT_SHIFT_BCNQ1_PGBNDY_V1) +#define BIT_CLEAR_BCNQ1_PGBNDY_V1(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1)) +#define BIT_GET_BCNQ1_PGBNDY_V1(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1) +#define BIT_SET_BCNQ1_PGBNDY_V1(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY_V1(x) | BIT_BCNQ1_PGBNDY_V1(v)) -#define BIT_SHIFT_SLOT 0 -#define BIT_MASK_SLOT 0xff -#define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT) -#define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */ +/* 2 REG_TAB_SEL (Offset 0x0456) */ -#define BIT_DIS_EDCCA BIT(15) -#define BIT_DIS_CCA BIT(14) -#define BIT_LSIG_TXOP_TXCMD_NAV BIT(13) -#define BIT_SIFS_BK_EN BIT(12) - -#define BIT_SHIFT_TXQ_NAV_MSK 8 -#define BIT_MASK_TXQ_NAV_MSK 0xf -#define BIT_TXQ_NAV_MSK(x) (((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK) -#define BIT_GET_TXQ_NAV_MSK(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK) - -#define BIT_DIS_CW BIT(7) -#define BIT_NAV_END_TXOP BIT(6) -#define BIT_RDG_END_TXOP BIT(5) -#define BIT_AC_INBCN_HOLD BIT(4) -#define BIT_MGTQ_TXOP_EN BIT(3) -#define BIT_MGTQ_RTSMF_EN BIT(2) -#define BIT_HIQ_RTSMF_EN BIT(1) -#define BIT_BCN_RTSMF_EN BIT(0) +#define BIT_SHIFT_RATE_SEL 0 +#define BIT_MASK_RATE_SEL 0xf +#define BIT_RATE_SEL(x) (((x) & BIT_MASK_RATE_SEL) << BIT_SHIFT_RATE_SEL) +#define BITS_RATE_SEL (BIT_MASK_RATE_SEL << BIT_SHIFT_RATE_SEL) +#define BIT_CLEAR_RATE_SEL(x) ((x) & (~BITS_RATE_SEL)) +#define BIT_GET_RATE_SEL(x) (((x) >> BIT_SHIFT_RATE_SEL) & BIT_MASK_RATE_SEL) +#define BIT_SET_RATE_SEL(x, v) (BIT_CLEAR_RATE_SEL(x) | BIT_RATE_SEL(v)) -/* 2 REG_TXPAUSE (Offset 0x0522) */ +/* 2 REG_BCN_INVALID_CTRL (Offset 0x0457) */ -#define BIT_STOP_BCN_HI_MGT BIT(7) -#define BIT_MAC_STOPBCNQ BIT(6) -#define BIT_MAC_STOPHIQ BIT(5) -#define BIT_MAC_STOPMGQ BIT(4) -#define BIT_MAC_STOPBK BIT(3) -#define BIT_MAC_STOPBE BIT(2) -#define BIT_MAC_STOPVI BIT(1) -#define BIT_MAC_STOPVO BIT(0) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P4 BIT(7) +#define BIT_EN_BCN_PKT_REL_P4 BIT(6) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P3 BIT(5) +#define BIT_EN_BCN_PKT_REL_P3 BIT(4) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P2 BIT(3) +#define BIT_EN_BCN_PKT_REL_P2 BIT(2) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P1 BIT(1) -/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +#endif -#define BIT_DIS_BT_CCA BIT(7) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_BCNQ1_BDNY (Offset 0x0457) */ +#define BIT_SHIFT_BCNQ1_PGBNDY 0 +#define BIT_MASK_BCNQ1_PGBNDY 0xff +#define BIT_BCNQ1_PGBNDY(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY) << BIT_SHIFT_BCNQ1_PGBNDY) +#define BITS_BCNQ1_PGBNDY (BIT_MASK_BCNQ1_PGBNDY << BIT_SHIFT_BCNQ1_PGBNDY) +#define BIT_CLEAR_BCNQ1_PGBNDY(x) ((x) & (~BITS_BCNQ1_PGBNDY)) +#define BIT_GET_BCNQ1_PGBNDY(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY) & BIT_MASK_BCNQ1_PGBNDY) +#define BIT_SET_BCNQ1_PGBNDY(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY(x) | BIT_BCNQ1_PGBNDY(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +/* 2 REG_BCNQ1_BDNY (Offset 0x0457) */ -#define BIT_DIS_TXREQ_CLR_CPUMGQ BIT(6) +#define BIT_SHIFT_BCNQ1_HEAD 0 +#define BIT_MASK_BCNQ1_HEAD 0xff +#define BIT_BCNQ1_HEAD(x) (((x) & BIT_MASK_BCNQ1_HEAD) << BIT_SHIFT_BCNQ1_HEAD) +#define BITS_BCNQ1_HEAD (BIT_MASK_BCNQ1_HEAD << BIT_SHIFT_BCNQ1_HEAD) +#define BIT_CLEAR_BCNQ1_HEAD(x) ((x) & (~BITS_BCNQ1_HEAD)) +#define BIT_GET_BCNQ1_HEAD(x) \ + (((x) >> BIT_SHIFT_BCNQ1_HEAD) & BIT_MASK_BCNQ1_HEAD) +#define BIT_SET_BCNQ1_HEAD(x, v) (BIT_CLEAR_BCNQ1_HEAD(x) | BIT_BCNQ1_HEAD(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCN_INVALID_CTRL (Offset 0x0457) */ +#define BIT_EN_BCN_PKT_REL_P1 BIT(0) -/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +#endif -#define BIT_DIS_TXREQ_CLR_HI BIT(5) -#define BIT_DIS_TXREQ_CLR_MGQ BIT(4) -#define BIT_DIS_TXREQ_CLR_VO BIT(3) -#define BIT_DIS_TXREQ_CLR_VI BIT(2) -#define BIT_DIS_TXREQ_CLR_BE BIT(1) -#define BIT_DIS_TXREQ_CLR_BK BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_RD_CTRL (Offset 0x0524) */ +/* 2 REG_AMPDU_MAX_LENGTH (Offset 0x0458) */ -#define BIT_EN_CLR_TXREQ_INCCA BIT(15) -#define BIT_DIS_TX_OVER_BCNQ BIT(14) +#define BIT_SHIFT_AMPDU_MAX_LENGTH 0 +#define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL +#define BIT_AMPDU_MAX_LENGTH(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH) +#define BITS_AMPDU_MAX_LENGTH \ + (BIT_MASK_AMPDU_MAX_LENGTH << BIT_SHIFT_AMPDU_MAX_LENGTH) +#define BIT_CLEAR_AMPDU_MAX_LENGTH(x) ((x) & (~BITS_AMPDU_MAX_LENGTH)) +#define BIT_GET_AMPDU_MAX_LENGTH(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH) +#define BIT_SET_AMPDU_MAX_LENGTH(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH(x) | BIT_AMPDU_MAX_LENGTH(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AMPDU_MAX_LENGTH_HT (Offset 0x0458) */ +#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_HT 0xffff +#define BIT_AMPDU_MAX_LENGTH_HT(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT) << BIT_SHIFT_AMPDU_MAX_LENGTH_HT) +#define BITS_AMPDU_MAX_LENGTH_HT \ + (BIT_MASK_AMPDU_MAX_LENGTH_HT << BIT_SHIFT_AMPDU_MAX_LENGTH_HT) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_HT)) +#define BIT_GET_AMPDU_MAX_LENGTH_HT(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT) & BIT_MASK_AMPDU_MAX_LENGTH_HT) +#define BIT_SET_AMPDU_MAX_LENGTH_HT(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) | BIT_AMPDU_MAX_LENGTH_HT(v)) -/* 2 REG_RD_CTRL (Offset 0x0524) */ +#endif -#define BIT_EN_BCNERR_INCCCA BIT(13) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_ACQ_STOP (Offset 0x045C) */ +#define BIT_AC7Q_STOP BIT(7) +#define BIT_AC6Q_STOP BIT(6) +#define BIT_AC5Q_STOP BIT(5) +#define BIT_AC4Q_STOP BIT(4) +#define BIT_AC3Q_STOP BIT(3) +#define BIT_AC2Q_STOP BIT(2) +#define BIT_AC1Q_STOP BIT(1) +#define BIT_AC0Q_STOP BIT(0) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_RD_CTRL (Offset 0x0524) */ +/* 2 REG_WMAC_LBK_BUF_HD (Offset 0x045D) */ -#define BIT_EN_BCNERR_INCCA BIT(13) -#define BIT_EN_BCNERR_INEDCCA BIT(12) +#define BIT_SHIFT_WMAC_LBK_BUF_HEAD 0 +#define BIT_MASK_WMAC_LBK_BUF_HEAD 0xff +#define BIT_WMAC_LBK_BUF_HEAD(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD) << BIT_SHIFT_WMAC_LBK_BUF_HEAD) +#define BITS_WMAC_LBK_BUF_HEAD \ + (BIT_MASK_WMAC_LBK_BUF_HEAD << BIT_SHIFT_WMAC_LBK_BUF_HEAD) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD)) +#define BIT_GET_WMAC_LBK_BUF_HEAD(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD) & BIT_MASK_WMAC_LBK_BUF_HEAD) +#define BIT_SET_WMAC_LBK_BUF_HEAD(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) | BIT_WMAC_LBK_BUF_HEAD(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NDPA_RATE (Offset 0x045D) */ +#define BIT_SHIFT_R_NDPA_RATE_V1 0 +#define BIT_MASK_R_NDPA_RATE_V1 0xff +#define BIT_R_NDPA_RATE_V1(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1) +#define BITS_R_NDPA_RATE_V1 \ + (BIT_MASK_R_NDPA_RATE_V1 << BIT_SHIFT_R_NDPA_RATE_V1) +#define BIT_CLEAR_R_NDPA_RATE_V1(x) ((x) & (~BITS_R_NDPA_RATE_V1)) +#define BIT_GET_R_NDPA_RATE_V1(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1) +#define BIT_SET_R_NDPA_RATE_V1(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1(x) | BIT_R_NDPA_RATE_V1(v)) -/* 2 REG_RD_CTRL (Offset 0x0524) */ +#endif -#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11) -#define BIT_DIS_TXOP_CFE BIT(10) -#define BIT_DIS_LSIG_CFE BIT(9) -#define BIT_DIS_STBC_CFE BIT(8) -#define BIT_BKQ_RD_INIT_EN BIT(7) -#define BIT_BEQ_RD_INIT_EN BIT(6) -#define BIT_VIQ_RD_INIT_EN BIT(5) -#define BIT_VOQ_RD_INIT_EN BIT(4) -#define BIT_BKQ_RD_RESP_EN BIT(3) -#define BIT_BEQ_RD_RESP_EN BIT(2) -#define BIT_VIQ_RD_RESP_EN BIT(1) -#define BIT_VOQ_RD_RESP_EN BIT(0) +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -/* 2 REG_MBSSID_CTRL (Offset 0x0526) */ +/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ -#define BIT_MBID_BCNQ7_EN BIT(7) -#define BIT_MBID_BCNQ6_EN BIT(6) -#define BIT_MBID_BCNQ5_EN BIT(5) -#define BIT_MBID_BCNQ4_EN BIT(4) -#define BIT_MBID_BCNQ3_EN BIT(3) -#define BIT_MBID_BCNQ2_EN BIT(2) -#define BIT_MBID_BCNQ1_EN BIT(1) -#define BIT_MBID_BCNQ0_EN BIT(0) +#define BIT_EN_GNT_BT_AWAKE BIT(3) -/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +#endif -#define BIT_P2P_CTW_ALLSTASLEEP BIT(7) -#define BIT_P2P_OFF_DISTX_EN BIT(6) -#define BIT_PWR_MGT_EN BIT(5) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +#define BIT_R_EN_GNT_BT_AWAKE BIT(3) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ -#define BIT_P2P_BCN_AREA_EN BIT(4) -#define BIT_P2P_CTWND_EN BIT(3) +#define BIT_DIS_RELEASE_RETRY BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +#define BIT_EN_EOF_V1 BIT(2) -/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +#endif -#define BIT_P2P_NOA1_EN BIT(2) -#define BIT_P2P_NOA0_EN BIT(1) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ +#define BIT_DIS_OQT_BLOCK BIT(1) +#define BIT_SEARCH_QUEUE_EN BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ -#define BIT_P2P_BCN_SEL BIT(0) +#define BIT_R_DIS_MACID_RELEASE_RTY BIT(5) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#define BIT_DIS_MACID_RELEASE_RTY BIT(5) -/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#endif -#define BIT_EN_P2P_CTWND1 BIT(23) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#define BIT_SHIFT_BW_SIGTA 3 +#define BIT_MASK_BW_SIGTA 0x3 +#define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA) +#define BITS_BW_SIGTA (BIT_MASK_BW_SIGTA << BIT_SHIFT_BW_SIGTA) +#define BIT_CLEAR_BW_SIGTA(x) ((x) & (~BITS_BW_SIGTA)) +#define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA) +#define BIT_SET_BW_SIGTA(x, v) (BIT_CLEAR_BW_SIGTA(x) | BIT_BW_SIGTA(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ -#define BIT_EN_TBTT_AREA_FOR_BB BIT(23) +#define BIT_SHIFT_R_NDPA_RATE 2 +#define BIT_MASK_R_NDPA_RATE 0x3f +#define BIT_R_NDPA_RATE(x) \ + (((x) & BIT_MASK_R_NDPA_RATE) << BIT_SHIFT_R_NDPA_RATE) +#define BITS_R_NDPA_RATE (BIT_MASK_R_NDPA_RATE << BIT_SHIFT_R_NDPA_RATE) +#define BIT_CLEAR_R_NDPA_RATE(x) ((x) & (~BITS_R_NDPA_RATE)) +#define BIT_GET_R_NDPA_RATE(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE) & BIT_MASK_R_NDPA_RATE) +#define BIT_SET_R_NDPA_RATE(x, v) \ + (BIT_CLEAR_R_NDPA_RATE(x) | BIT_R_NDPA_RATE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#define BIT_EN_BAR_SIGTA BIT(2) -/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#endif -#define BIT_EN_BKF_CLR_TXREQ BIT(22) -#define BIT_EN_TSFBIT32_RST_P2P BIT(21) -#define BIT_EN_BCN_TX_BTCCA BIT(20) -#define BIT_DIS_PKT_TX_ATIM BIT(19) -#define BIT_DIS_BCN_DIS_CTN BIT(18) -#define BIT_EN_NAVEND_RST_TXOP BIT(17) -#define BIT_EN_FILTER_CCA BIT(16) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CCA_FILTER_THRS 8 -#define BIT_MASK_CCA_FILTER_THRS 0xff -#define BIT_CCA_FILTER_THRS(x) (((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS) -#define BIT_GET_CCA_FILTER_THRS(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS) +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ +#define BIT_SHIFT_R_NDPA_BW 0 +#define BIT_MASK_R_NDPA_BW 0x3 +#define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW) +#define BITS_R_NDPA_BW (BIT_MASK_R_NDPA_BW << BIT_SHIFT_R_NDPA_BW) +#define BIT_CLEAR_R_NDPA_BW(x) ((x) & (~BITS_R_NDPA_BW)) +#define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW) +#define BIT_SET_R_NDPA_BW(x, v) (BIT_CLEAR_R_NDPA_BW(x) | BIT_R_NDPA_BW(v)) -#define BIT_SHIFT_EDCCA_THRS 0 -#define BIT_MASK_EDCCA_THRS 0xff -#define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS) -#define BIT_GET_EDCCA_THRS(x) (((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -/* 2 REG_P2PPS_SPEC_STATE (Offset 0x052B) */ +/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ -#define BIT_SPEC_POWER_STATE BIT(7) -#define BIT_SPEC_CTWINDOW_ON BIT(6) -#define BIT_SPEC_BEACON_AREA_ON BIT(5) -#define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4) -#define BIT_SPEC_NOA1_OFF_PERIOD BIT(3) -#define BIT_SPEC_FORCE_DOZE1 BIT(2) -#define BIT_SPEC_NOA0_OFF_PERIOD BIT(1) -#define BIT_SPEC_FORCE_DOZE0 BIT(0) +#define BIT_SHIFT_NDPA_BW 0 +#define BIT_MASK_NDPA_BW 0x3 +#define BIT_NDPA_BW(x) (((x) & BIT_MASK_NDPA_BW) << BIT_SHIFT_NDPA_BW) +#define BITS_NDPA_BW (BIT_MASK_NDPA_BW << BIT_SHIFT_NDPA_BW) +#define BIT_CLEAR_NDPA_BW(x) ((x) & (~BITS_NDPA_BW)) +#define BIT_GET_NDPA_BW(x) (((x) >> BIT_SHIFT_NDPA_BW) & BIT_MASK_NDPA_BW) +#define BIT_SET_NDPA_BW(x, v) (BIT_CLEAR_NDPA_BW(x) | BIT_NDPA_BW(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FAST_EDCA_CTRL (Offset 0x0460) */ +#define BIT_SHIFT_FAST_EDCA_TO_V1 16 +#define BIT_MASK_FAST_EDCA_TO_V1 0xff +#define BIT_FAST_EDCA_TO_V1(x) \ + (((x) & BIT_MASK_FAST_EDCA_TO_V1) << BIT_SHIFT_FAST_EDCA_TO_V1) +#define BITS_FAST_EDCA_TO_V1 \ + (BIT_MASK_FAST_EDCA_TO_V1 << BIT_SHIFT_FAST_EDCA_TO_V1) +#define BIT_CLEAR_FAST_EDCA_TO_V1(x) ((x) & (~BITS_FAST_EDCA_TO_V1)) +#define BIT_GET_FAST_EDCA_TO_V1(x) \ + (((x) >> BIT_SHIFT_FAST_EDCA_TO_V1) & BIT_MASK_FAST_EDCA_TO_V1) +#define BIT_SET_FAST_EDCA_TO_V1(x, v) \ + (BIT_CLEAR_FAST_EDCA_TO_V1(x) | BIT_FAST_EDCA_TO_V1(v)) + +#define BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH 12 +#define BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH 0xf +#define BIT_AC3_AC7_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) \ + << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) +#define BITS_AC3_AC7_FAST_EDCA_PKT_TH \ + (BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH \ + << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x) \ + ((x) & (~BITS_AC3_AC7_FAST_EDCA_PKT_TH)) +#define BIT_GET_AC3_AC7_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) & \ + BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) +#define BIT_SET_AC3_AC7_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x) | \ + BIT_AC3_AC7_FAST_EDCA_PKT_TH(v)) + +#define BIT_SHIFT_AC2_FAST_EDCA_PKT_TH 8 +#define BIT_MASK_AC2_FAST_EDCA_PKT_TH 0xf +#define BIT_AC2_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_AC2_FAST_EDCA_PKT_TH) \ + << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) +#define BITS_AC2_FAST_EDCA_PKT_TH \ + (BIT_MASK_AC2_FAST_EDCA_PKT_TH << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC2_FAST_EDCA_PKT_TH)) +#define BIT_GET_AC2_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) & \ + BIT_MASK_AC2_FAST_EDCA_PKT_TH) +#define BIT_SET_AC2_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) | BIT_AC2_FAST_EDCA_PKT_TH(v)) + +#define BIT_SHIFT_AC1_FAST_EDCA_PKT_TH 4 +#define BIT_MASK_AC1_FAST_EDCA_PKT_TH 0xf +#define BIT_AC1_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_AC1_FAST_EDCA_PKT_TH) \ + << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) +#define BITS_AC1_FAST_EDCA_PKT_TH \ + (BIT_MASK_AC1_FAST_EDCA_PKT_TH << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC1_FAST_EDCA_PKT_TH)) +#define BIT_GET_AC1_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) & \ + BIT_MASK_AC1_FAST_EDCA_PKT_TH) +#define BIT_SET_AC1_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) | BIT_AC1_FAST_EDCA_PKT_TH(v)) + +#define BIT_SHIFT_AC0_FAST_EDCA_PKT_TH 0 +#define BIT_MASK_AC0_FAST_EDCA_PKT_TH 0xf +#define BIT_AC0_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_AC0_FAST_EDCA_PKT_TH) \ + << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) +#define BITS_AC0_FAST_EDCA_PKT_TH \ + (BIT_MASK_AC0_FAST_EDCA_PKT_TH << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC0_FAST_EDCA_PKT_TH)) +#define BIT_GET_AC0_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) & \ + BIT_MASK_AC0_FAST_EDCA_PKT_TH) +#define BIT_SET_AC0_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) | BIT_AC0_FAST_EDCA_PKT_TH(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_AMPDU_MAX_LENGTH_VHT (Offset 0x0460) */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 0xfffff +#define BIT_AMPDU_MAX_LENGTH_VHT_V1(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) +#define BITS_AMPDU_MAX_LENGTH_VHT_V1 \ + (BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_V1)) +#define BIT_GET_AMPDU_MAX_LENGTH_VHT_V1(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) & \ + BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1) +#define BIT_SET_AMPDU_MAX_LENGTH_VHT_V1(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x) | BIT_AMPDU_MAX_LENGTH_VHT_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_AMPDU_MAX_LENGTH_VHT (Offset 0x0460) */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_VHT 0x3ffff +#define BIT_AMPDU_MAX_LENGTH_VHT(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) +#define BITS_AMPDU_MAX_LENGTH_VHT \ + (BIT_MASK_AMPDU_MAX_LENGTH_VHT << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT)) +#define BIT_GET_AMPDU_MAX_LENGTH_VHT(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) & \ + BIT_MASK_AMPDU_MAX_LENGTH_VHT) +#define BIT_SET_AMPDU_MAX_LENGTH_VHT(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) | BIT_AMPDU_MAX_LENGTH_VHT(v)) -/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BK_QUEUE_THR 24 -#define BIT_MASK_BK_QUEUE_THR 0xff -#define BIT_BK_QUEUE_THR(x) (((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR) -#define BIT_GET_BK_QUEUE_THR(x) (((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR) +/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ +#define BIT_SHIFT_RD_RESP_PKT_TH 0 +#define BIT_MASK_RD_RESP_PKT_TH 0x1f +#define BIT_RD_RESP_PKT_TH(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH) << BIT_SHIFT_RD_RESP_PKT_TH) +#define BITS_RD_RESP_PKT_TH \ + (BIT_MASK_RD_RESP_PKT_TH << BIT_SHIFT_RD_RESP_PKT_TH) +#define BIT_CLEAR_RD_RESP_PKT_TH(x) ((x) & (~BITS_RD_RESP_PKT_TH)) +#define BIT_GET_RD_RESP_PKT_TH(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH) & BIT_MASK_RD_RESP_PKT_TH) +#define BIT_SET_RD_RESP_PKT_TH(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH(x) | BIT_RD_RESP_PKT_TH(v)) -#define BIT_SHIFT_BE_QUEUE_THR 16 -#define BIT_MASK_BE_QUEUE_THR 0xff -#define BIT_BE_QUEUE_THR(x) (((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR) -#define BIT_GET_BE_QUEUE_THR(x) (((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_VI_QUEUE_THR 8 -#define BIT_MASK_VI_QUEUE_THR 0xff -#define BIT_VI_QUEUE_THR(x) (((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR) -#define BIT_GET_VI_QUEUE_THR(x) (((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR) +/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ +#define BIT_SHIFT_RD_RESP_PKT_TH_V1 0 +#define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f +#define BIT_RD_RESP_PKT_TH_V1(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1) +#define BITS_RD_RESP_PKT_TH_V1 \ + (BIT_MASK_RD_RESP_PKT_TH_V1 << BIT_SHIFT_RD_RESP_PKT_TH_V1) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1(x) ((x) & (~BITS_RD_RESP_PKT_TH_V1)) +#define BIT_GET_RD_RESP_PKT_TH_V1(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1) +#define BIT_SET_RD_RESP_PKT_TH_V1(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1(x) | BIT_RD_RESP_PKT_TH_V1(v)) -#define BIT_SHIFT_VO_QUEUE_THR 0 -#define BIT_MASK_VO_QUEUE_THR 0xff -#define BIT_VO_QUEUE_THR(x) (((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR) -#define BIT_GET_VO_QUEUE_THR(x) (((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ -#define BIT_QUEUE_INCOL_EN BIT(16) +#define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25 +#define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f +#define BIT_QUEUEMACID_CMDQ_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1) +#define BITS_QUEUEMACID_CMDQ_V1 \ + (BIT_MASK_QUEUEMACID_CMDQ_V1 << BIT_SHIFT_QUEUEMACID_CMDQ_V1) +#define BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) ((x) & (~BITS_QUEUEMACID_CMDQ_V1)) +#define BIT_GET_QUEUEMACID_CMDQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1) +#define BIT_SET_QUEUEMACID_CMDQ_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) | BIT_QUEUEMACID_CMDQ_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_PKT_NUM_CMDQ_V2 24 +#define BIT_MASK_PKT_NUM_CMDQ_V2 0xff +#define BIT_PKT_NUM_CMDQ_V2(x) \ + (((x) & BIT_MASK_PKT_NUM_CMDQ_V2) << BIT_SHIFT_PKT_NUM_CMDQ_V2) +#define BITS_PKT_NUM_CMDQ_V2 \ + (BIT_MASK_PKT_NUM_CMDQ_V2 << BIT_SHIFT_PKT_NUM_CMDQ_V2) +#define BIT_CLEAR_PKT_NUM_CMDQ_V2(x) ((x) & (~BITS_PKT_NUM_CMDQ_V2)) +#define BIT_GET_PKT_NUM_CMDQ_V2(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_CMDQ_V2) & BIT_MASK_PKT_NUM_CMDQ_V2) +#define BIT_SET_PKT_NUM_CMDQ_V2(x, v) \ + (BIT_CLEAR_PKT_NUM_CMDQ_V2(x) | BIT_PKT_NUM_CMDQ_V2(v)) -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#endif +#if (HALMAC_8197F_SUPPORT) -#define BIT_SHIFT_BK_TRIGGER_NUM_V1 12 -#define BIT_MASK_BK_TRIGGER_NUM_V1 0xf -#define BIT_BK_TRIGGER_NUM_V1(x) (((x) & BIT_MASK_BK_TRIGGER_NUM_V1) << BIT_SHIFT_BK_TRIGGER_NUM_V1) -#define BIT_GET_BK_TRIGGER_NUM_V1(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1) & BIT_MASK_BK_TRIGGER_NUM_V1) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_PKT_NUM 23 +#define BIT_MASK_PKT_NUM 0x1ff +#define BIT_PKT_NUM(x) (((x) & BIT_MASK_PKT_NUM) << BIT_SHIFT_PKT_NUM) +#define BITS_PKT_NUM (BIT_MASK_PKT_NUM << BIT_SHIFT_PKT_NUM) +#define BIT_CLEAR_PKT_NUM(x) ((x) & (~BITS_PKT_NUM)) +#define BIT_GET_PKT_NUM(x) (((x) >> BIT_SHIFT_PKT_NUM) & BIT_MASK_PKT_NUM) +#define BIT_SET_PKT_NUM(x, v) (BIT_CLEAR_PKT_NUM(x) | BIT_PKT_NUM(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_QUEUEAC_CMDQ_V1 23 +#define BIT_MASK_QUEUEAC_CMDQ_V1 0x3 +#define BIT_QUEUEAC_CMDQ_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1) +#define BITS_QUEUEAC_CMDQ_V1 \ + (BIT_MASK_QUEUEAC_CMDQ_V1 << BIT_SHIFT_QUEUEAC_CMDQ_V1) +#define BIT_CLEAR_QUEUEAC_CMDQ_V1(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1)) +#define BIT_GET_QUEUEAC_CMDQ_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1) +#define BIT_SET_QUEUEAC_CMDQ_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_CMDQ_V1(x) | BIT_QUEUEAC_CMDQ_V1(v)) -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BE_TRIGGER_NUM 12 -#define BIT_MASK_BE_TRIGGER_NUM 0xf -#define BIT_BE_TRIGGER_NUM(x) (((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM) -#define BIT_GET_BE_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_TIDEMPTY_CMDQ_V1 BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_TAIL_PKT_CMDQ 16 +#define BIT_MASK_TAIL_PKT_CMDQ 0xff +#define BIT_TAIL_PKT_CMDQ(x) \ + (((x) & BIT_MASK_TAIL_PKT_CMDQ) << BIT_SHIFT_TAIL_PKT_CMDQ) +#define BITS_TAIL_PKT_CMDQ (BIT_MASK_TAIL_PKT_CMDQ << BIT_SHIFT_TAIL_PKT_CMDQ) +#define BIT_CLEAR_TAIL_PKT_CMDQ(x) ((x) & (~BITS_TAIL_PKT_CMDQ)) +#define BIT_GET_TAIL_PKT_CMDQ(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ) & BIT_MASK_TAIL_PKT_CMDQ) +#define BIT_SET_TAIL_PKT_CMDQ(x, v) \ + (BIT_CLEAR_TAIL_PKT_CMDQ(x) | BIT_TAIL_PKT_CMDQ(v)) -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_BE_TRIGGER_NUM_V1 8 -#define BIT_MASK_BE_TRIGGER_NUM_V1 0xf -#define BIT_BE_TRIGGER_NUM_V1(x) (((x) & BIT_MASK_BE_TRIGGER_NUM_V1) << BIT_SHIFT_BE_TRIGGER_NUM_V1) -#define BIT_GET_BE_TRIGGER_NUM_V1(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1) & BIT_MASK_BE_TRIGGER_NUM_V1) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11 +#define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff +#define BIT_TAIL_PKT_CMDQ_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2) +#define BITS_TAIL_PKT_CMDQ_V2 \ + (BIT_MASK_TAIL_PKT_CMDQ_V2 << BIT_SHIFT_TAIL_PKT_CMDQ_V2) +#define BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) ((x) & (~BITS_TAIL_PKT_CMDQ_V2)) +#define BIT_GET_TAIL_PKT_CMDQ_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2) +#define BIT_SET_TAIL_PKT_CMDQ_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) | BIT_TAIL_PKT_CMDQ_V2(v)) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */ +#define BIT_SHIFT_RANDOM_VALUE_SHIFT 9 +#define BIT_MASK_RANDOM_VALUE_SHIFT 0x7 +#define BIT_RANDOM_VALUE_SHIFT(x) \ + (((x) & BIT_MASK_RANDOM_VALUE_SHIFT) << BIT_SHIFT_RANDOM_VALUE_SHIFT) +#define BITS_RANDOM_VALUE_SHIFT \ + (BIT_MASK_RANDOM_VALUE_SHIFT << BIT_SHIFT_RANDOM_VALUE_SHIFT) +#define BIT_CLEAR_RANDOM_VALUE_SHIFT(x) ((x) & (~BITS_RANDOM_VALUE_SHIFT)) +#define BIT_GET_RANDOM_VALUE_SHIFT(x) \ + (((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT) & BIT_MASK_RANDOM_VALUE_SHIFT) +#define BIT_SET_RANDOM_VALUE_SHIFT(x, v) \ + (BIT_CLEAR_RANDOM_VALUE_SHIFT(x) | BIT_RANDOM_VALUE_SHIFT(v)) -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BK_TRIGGER_NUM 8 -#define BIT_MASK_BK_TRIGGER_NUM 0xf -#define BIT_BK_TRIGGER_NUM(x) (((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM) -#define BIT_GET_BK_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_PKT_NUM_CMDQ 8 +#define BIT_MASK_PKT_NUM_CMDQ 0xff +#define BIT_PKT_NUM_CMDQ(x) \ + (((x) & BIT_MASK_PKT_NUM_CMDQ) << BIT_SHIFT_PKT_NUM_CMDQ) +#define BITS_PKT_NUM_CMDQ (BIT_MASK_PKT_NUM_CMDQ << BIT_SHIFT_PKT_NUM_CMDQ) +#define BIT_CLEAR_PKT_NUM_CMDQ(x) ((x) & (~BITS_PKT_NUM_CMDQ)) +#define BIT_GET_PKT_NUM_CMDQ(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_CMDQ) & BIT_MASK_PKT_NUM_CMDQ) +#define BIT_SET_PKT_NUM_CMDQ(x, v) \ + (BIT_CLEAR_PKT_NUM_CMDQ(x) | BIT_PKT_NUM_CMDQ(v)) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +/* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */ +#define BIT_ENABLE_NEW_EDCA BIT(8) -#define BIT_SHIFT_VI_TRIGGER_NUM 4 -#define BIT_MASK_VI_TRIGGER_NUM 0xf -#define BIT_VI_TRIGGER_NUM(x) (((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM) -#define BIT_GET_VI_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VO_TRIGGER_NUM 0 -#define BIT_MASK_VO_TRIGGER_NUM 0xf -#define BIT_VO_TRIGGER_NUM(x) (((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM) -#define BIT_GET_VO_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_HEAD_PKT_CMDQ 0 +#define BIT_MASK_HEAD_PKT_CMDQ 0xff +#define BIT_HEAD_PKT_CMDQ(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ) << BIT_SHIFT_HEAD_PKT_CMDQ) +#define BITS_HEAD_PKT_CMDQ (BIT_MASK_HEAD_PKT_CMDQ << BIT_SHIFT_HEAD_PKT_CMDQ) +#define BIT_CLEAR_HEAD_PKT_CMDQ(x) ((x) & (~BITS_HEAD_PKT_CMDQ)) +#define BIT_GET_HEAD_PKT_CMDQ(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ) & BIT_MASK_HEAD_PKT_CMDQ) +#define BIT_SET_HEAD_PKT_CMDQ(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ(x) | BIT_HEAD_PKT_CMDQ(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CMDQ_INFO (Offset 0x0464) */ +#define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0 +#define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff +#define BIT_HEAD_PKT_CMDQ_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1) +#define BITS_HEAD_PKT_CMDQ_V1 \ + (BIT_MASK_HEAD_PKT_CMDQ_V1 << BIT_SHIFT_HEAD_PKT_CMDQ_V1) +#define BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) ((x) & (~BITS_HEAD_PKT_CMDQ_V1)) +#define BIT_GET_HEAD_PKT_CMDQ_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1) +#define BIT_SET_HEAD_PKT_CMDQ_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) | BIT_HEAD_PKT_CMDQ_V1(v)) -/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 -#define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff -#define BIT_TBTT_HOLD_TIME_AP(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP) -#define BIT_GET_TBTT_HOLD_TIME_AP(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP) +/* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */ +#define BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER 0 +#define BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER 0xff +#define BIT_MEDIUM_HAS_IDKE_TRIGGER(x) \ + (((x) & BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER) \ + << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) +#define BITS_MEDIUM_HAS_IDKE_TRIGGER \ + (BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) +#define BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x) \ + ((x) & (~BITS_MEDIUM_HAS_IDKE_TRIGGER)) +#define BIT_GET_MEDIUM_HAS_IDKE_TRIGGER(x) \ + (((x) >> BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) & \ + BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER) +#define BIT_SET_MEDIUM_HAS_IDKE_TRIGGER(x, v) \ + (BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x) | BIT_MEDIUM_HAS_IDKE_TRIGGER(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_QUEUEMACID_Q4_V1 25 +#define BIT_MASK_QUEUEMACID_Q4_V1 0x7f +#define BIT_QUEUEMACID_Q4_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1) +#define BITS_QUEUEMACID_Q4_V1 \ + (BIT_MASK_QUEUEMACID_Q4_V1 << BIT_SHIFT_QUEUEMACID_Q4_V1) +#define BIT_CLEAR_QUEUEMACID_Q4_V1(x) ((x) & (~BITS_QUEUEMACID_Q4_V1)) +#define BIT_GET_QUEUEMACID_Q4_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1) +#define BIT_SET_QUEUEMACID_Q4_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q4_V1(x) | BIT_QUEUEMACID_Q4_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q4_V1 23 +#define BIT_MASK_QUEUEAC_Q4_V1 0x3 +#define BIT_QUEUEAC_Q4_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1) +#define BITS_QUEUEAC_Q4_V1 (BIT_MASK_QUEUEAC_Q4_V1 << BIT_SHIFT_QUEUEAC_Q4_V1) +#define BIT_CLEAR_QUEUEAC_Q4_V1(x) ((x) & (~BITS_QUEUEAC_Q4_V1)) +#define BIT_GET_QUEUEAC_Q4_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1) +#define BIT_SET_QUEUEAC_Q4_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q4_V1(x) | BIT_QUEUEAC_Q4_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TBTT_HOLD_TIME_INFRA 4 -#define BIT_MASK_TBTT_HOLD_TIME_INFRA 0xf -#define BIT_TBTT_HOLD_TIME_INFRA(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_INFRA) << BIT_SHIFT_TBTT_HOLD_TIME_INFRA) -#define BIT_GET_TBTT_HOLD_TIME_INFRA(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_INFRA) & BIT_MASK_TBTT_HOLD_TIME_INFRA) +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_TIDEMPTY_Q4_V1 BIT(22) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ +/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ +#define BIT_AC19Q_STOP BIT(19) +#define BIT_AC18Q_STOP BIT(18) +#define BIT_AC17Q_STOP BIT(17) +#define BIT_AC16Q_STOP BIT(16) -#define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0 -#define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf -#define BIT_TBTT_PROHIBIT_SETUP(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP) -#define BIT_GET_TBTT_PROHIBIT_SETUP(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_P2PPS_STATE (Offset 0x0543) */ +/* 2 REG_Q4_INFO (Offset 0x0468) */ -#define BIT_POWER_STATE BIT(7) -#define BIT_CTWINDOW_ON BIT(6) -#define BIT_BEACON_AREA_ON BIT(5) -#define BIT_CTWIN_EARLY_DISTX BIT(4) -#define BIT_NOA1_OFF_PERIOD BIT(3) -#define BIT_FORCE_DOZE1 BIT(2) -#define BIT_NOA0_OFF_PERIOD BIT(1) -#define BIT_FORCE_DOZE0 BIT(0) +#define BIT_SHIFT_TAIL_PKT_Q4_V1 15 +#define BIT_MASK_TAIL_PKT_Q4_V1 0xff +#define BIT_TAIL_PKT_Q4_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V1) << BIT_SHIFT_TAIL_PKT_Q4_V1) +#define BITS_TAIL_PKT_Q4_V1 \ + (BIT_MASK_TAIL_PKT_Q4_V1 << BIT_SHIFT_TAIL_PKT_Q4_V1) +#define BIT_CLEAR_TAIL_PKT_Q4_V1(x) ((x) & (~BITS_TAIL_PKT_Q4_V1)) +#define BIT_GET_TAIL_PKT_Q4_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V1) & BIT_MASK_TAIL_PKT_Q4_V1) +#define BIT_SET_TAIL_PKT_Q4_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V1(x) | BIT_TAIL_PKT_Q4_V1(v)) -/* 2 REG_RD_NAV_NXT (Offset 0x0544) */ +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RD_NAV_PROT_NXT 0 -#define BIT_MASK_RD_NAV_PROT_NXT 0xffff -#define BIT_RD_NAV_PROT_NXT(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT) -#define BIT_GET_RD_NAV_PROT_NXT(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT) +/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ +#define BIT_AC15Q_STOP BIT(15) +#define BIT_AC14Q_STOP BIT(14) +#define BIT_AC13Q_STOP BIT(13) +#define BIT_AC12Q_STOP BIT(12) -/* 2 REG_NAV_PROT_LEN (Offset 0x0546) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NAV_PROT_LEN 0 -#define BIT_MASK_NAV_PROT_LEN 0xffff -#define BIT_NAV_PROT_LEN(x) (((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN) -#define BIT_GET_NAV_PROT_LEN(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN) +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_TAIL_PKT_Q4_V2 11 +#define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff +#define BIT_TAIL_PKT_Q4_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2) +#define BITS_TAIL_PKT_Q4_V2 \ + (BIT_MASK_TAIL_PKT_Q4_V2 << BIT_SHIFT_TAIL_PKT_Q4_V2) +#define BIT_CLEAR_TAIL_PKT_Q4_V2(x) ((x) & (~BITS_TAIL_PKT_Q4_V2)) +#define BIT_GET_TAIL_PKT_Q4_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2) +#define BIT_SET_TAIL_PKT_Q4_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2(x) | BIT_TAIL_PKT_Q4_V2(v)) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ +#define BIT_AC11Q_STOP BIT(11) +#define BIT_AC10Q_STOP BIT(10) +#define BIT_AC9Q_STOP BIT(9) -/* 2 REG_FTM_CTRL (Offset 0x0548) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FTM_TSF_R2T_PORT 22 -#define BIT_MASK_FTM_TSF_R2T_PORT 0x7 -#define BIT_FTM_TSF_R2T_PORT(x) (((x) & BIT_MASK_FTM_TSF_R2T_PORT) << BIT_SHIFT_FTM_TSF_R2T_PORT) -#define BIT_GET_FTM_TSF_R2T_PORT(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT) & BIT_MASK_FTM_TSF_R2T_PORT) +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_PKT_NUM_Q4_V1 8 +#define BIT_MASK_PKT_NUM_Q4_V1 0x7f +#define BIT_PKT_NUM_Q4_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q4_V1) << BIT_SHIFT_PKT_NUM_Q4_V1) +#define BITS_PKT_NUM_Q4_V1 (BIT_MASK_PKT_NUM_Q4_V1 << BIT_SHIFT_PKT_NUM_Q4_V1) +#define BIT_CLEAR_PKT_NUM_Q4_V1(x) ((x) & (~BITS_PKT_NUM_Q4_V1)) +#define BIT_GET_PKT_NUM_Q4_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q4_V1) & BIT_MASK_PKT_NUM_Q4_V1) +#define BIT_SET_PKT_NUM_Q4_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q4_V1(x) | BIT_PKT_NUM_Q4_V1(v)) -#define BIT_SHIFT_FTM_TSF_T2R_PORT 19 -#define BIT_MASK_FTM_TSF_T2R_PORT 0x7 -#define BIT_FTM_TSF_T2R_PORT(x) (((x) & BIT_MASK_FTM_TSF_T2R_PORT) << BIT_SHIFT_FTM_TSF_T2R_PORT) -#define BIT_GET_FTM_TSF_T2R_PORT(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT) & BIT_MASK_FTM_TSF_T2R_PORT) +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_FTM_PTT_PORT 16 -#define BIT_MASK_FTM_PTT_PORT 0x7 -#define BIT_FTM_PTT_PORT(x) (((x) & BIT_MASK_FTM_PTT_PORT) << BIT_SHIFT_FTM_PTT_PORT) -#define BIT_GET_FTM_PTT_PORT(x) (((x) >> BIT_SHIFT_FTM_PTT_PORT) & BIT_MASK_FTM_PTT_PORT) +/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */ +#define BIT_AC8Q_STOP BIT(8) -#define BIT_SHIFT_FTM_PTT 0 -#define BIT_MASK_FTM_PTT 0xffff -#define BIT_FTM_PTT(x) (((x) & BIT_MASK_FTM_PTT) << BIT_SHIFT_FTM_PTT) -#define BIT_GET_FTM_PTT(x) (((x) >> BIT_SHIFT_FTM_PTT) & BIT_MASK_FTM_PTT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FTM_TSF_CNT (Offset 0x054C) */ +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_HEAD_PKT_Q4 0 +#define BIT_MASK_HEAD_PKT_Q4 0xff +#define BIT_HEAD_PKT_Q4(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4) << BIT_SHIFT_HEAD_PKT_Q4) +#define BITS_HEAD_PKT_Q4 (BIT_MASK_HEAD_PKT_Q4 << BIT_SHIFT_HEAD_PKT_Q4) +#define BIT_CLEAR_HEAD_PKT_Q4(x) ((x) & (~BITS_HEAD_PKT_Q4)) +#define BIT_GET_HEAD_PKT_Q4(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4) & BIT_MASK_HEAD_PKT_Q4) +#define BIT_SET_HEAD_PKT_Q4(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4(x) | BIT_HEAD_PKT_Q4(v)) -#define BIT_SHIFT_FTM_TSF_R2T 16 -#define BIT_MASK_FTM_TSF_R2T 0xffff -#define BIT_FTM_TSF_R2T(x) (((x) & BIT_MASK_FTM_TSF_R2T) << BIT_SHIFT_FTM_TSF_R2T) -#define BIT_GET_FTM_TSF_R2T(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T) & BIT_MASK_FTM_TSF_R2T) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FTM_TSF_T2R 0 -#define BIT_MASK_FTM_TSF_T2R 0xffff -#define BIT_FTM_TSF_T2R(x) (((x) & BIT_MASK_FTM_TSF_T2R) << BIT_SHIFT_FTM_TSF_T2R) -#define BIT_GET_FTM_TSF_T2R(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R) & BIT_MASK_FTM_TSF_T2R) +/* 2 REG_Q4_INFO (Offset 0x0468) */ +#define BIT_SHIFT_HEAD_PKT_Q4_V1 0 +#define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff +#define BIT_HEAD_PKT_Q4_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1) +#define BITS_HEAD_PKT_Q4_V1 \ + (BIT_MASK_HEAD_PKT_Q4_V1 << BIT_SHIFT_HEAD_PKT_Q4_V1) +#define BIT_CLEAR_HEAD_PKT_Q4_V1(x) ((x) & (~BITS_HEAD_PKT_Q4_V1)) +#define BIT_GET_HEAD_PKT_Q4_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1) +#define BIT_SET_HEAD_PKT_Q4_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4_V1(x) | BIT_HEAD_PKT_Q4_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q5_INFO (Offset 0x046C) */ +#define BIT_SHIFT_QUEUEMACID_Q5_V1 25 +#define BIT_MASK_QUEUEMACID_Q5_V1 0x7f +#define BIT_QUEUEMACID_Q5_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1) +#define BITS_QUEUEMACID_Q5_V1 \ + (BIT_MASK_QUEUEMACID_Q5_V1 << BIT_SHIFT_QUEUEMACID_Q5_V1) +#define BIT_CLEAR_QUEUEMACID_Q5_V1(x) ((x) & (~BITS_QUEUEMACID_Q5_V1)) +#define BIT_GET_QUEUEMACID_Q5_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1) +#define BIT_SET_QUEUEMACID_Q5_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q5_V1(x) | BIT_QUEUEMACID_Q5_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q5_V1 23 +#define BIT_MASK_QUEUEAC_Q5_V1 0x3 +#define BIT_QUEUEAC_Q5_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1) +#define BITS_QUEUEAC_Q5_V1 (BIT_MASK_QUEUEAC_Q5_V1 << BIT_SHIFT_QUEUEAC_Q5_V1) +#define BIT_CLEAR_QUEUEAC_Q5_V1(x) ((x) & (~BITS_QUEUEAC_Q5_V1)) +#define BIT_GET_QUEUEAC_Q5_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1) +#define BIT_SET_QUEUEAC_Q5_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q5_V1(x) | BIT_QUEUEAC_Q5_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +/* 2 REG_Q5_INFO (Offset 0x046C) */ -#define BIT_DIS_RX_BSSID_FIT BIT(6) +#define BIT_TIDEMPTY_Q5_V1 BIT(22) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +/* 2 REG_Q5_INFO (Offset 0x046C) */ -#define BIT_P0_EN_TXBCN_RPT BIT(5) +#define BIT_SHIFT_TAIL_PKT_Q5_V1 15 +#define BIT_MASK_TAIL_PKT_Q5_V1 0xff +#define BIT_TAIL_PKT_Q5_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V1) << BIT_SHIFT_TAIL_PKT_Q5_V1) +#define BITS_TAIL_PKT_Q5_V1 \ + (BIT_MASK_TAIL_PKT_Q5_V1 << BIT_SHIFT_TAIL_PKT_Q5_V1) +#define BIT_CLEAR_TAIL_PKT_Q5_V1(x) ((x) & (~BITS_TAIL_PKT_Q5_V1)) +#define BIT_GET_TAIL_PKT_Q5_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V1) & BIT_MASK_TAIL_PKT_Q5_V1) +#define BIT_SET_TAIL_PKT_Q5_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V1(x) | BIT_TAIL_PKT_Q5_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +/* 2 REG_Q5_INFO (Offset 0x046C) */ -#define BIT_DIS_TSF_UDT BIT(4) -#define BIT_EN_BCN_FUNCTION BIT(3) +#define BIT_SHIFT_TAIL_PKT_Q5_V2 11 +#define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff +#define BIT_TAIL_PKT_Q5_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2) +#define BITS_TAIL_PKT_Q5_V2 \ + (BIT_MASK_TAIL_PKT_Q5_V2 << BIT_SHIFT_TAIL_PKT_Q5_V2) +#define BIT_CLEAR_TAIL_PKT_Q5_V2(x) ((x) & (~BITS_TAIL_PKT_Q5_V2)) +#define BIT_GET_TAIL_PKT_Q5_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2) +#define BIT_SET_TAIL_PKT_Q5_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V2(x) | BIT_TAIL_PKT_Q5_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q5_INFO (Offset 0x046C) */ +#define BIT_SHIFT_PKT_NUM_Q5_V1 8 +#define BIT_MASK_PKT_NUM_Q5_V1 0x7f +#define BIT_PKT_NUM_Q5_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q5_V1) << BIT_SHIFT_PKT_NUM_Q5_V1) +#define BITS_PKT_NUM_Q5_V1 (BIT_MASK_PKT_NUM_Q5_V1 << BIT_SHIFT_PKT_NUM_Q5_V1) +#define BIT_CLEAR_PKT_NUM_Q5_V1(x) ((x) & (~BITS_PKT_NUM_Q5_V1)) +#define BIT_GET_PKT_NUM_Q5_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q5_V1) & BIT_MASK_PKT_NUM_Q5_V1) +#define BIT_SET_PKT_NUM_Q5_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q5_V1(x) | BIT_PKT_NUM_Q5_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q5 0 +#define BIT_MASK_HEAD_PKT_Q5 0xff +#define BIT_HEAD_PKT_Q5(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5) << BIT_SHIFT_HEAD_PKT_Q5) +#define BITS_HEAD_PKT_Q5 (BIT_MASK_HEAD_PKT_Q5 << BIT_SHIFT_HEAD_PKT_Q5) +#define BIT_CLEAR_HEAD_PKT_Q5(x) ((x) & (~BITS_HEAD_PKT_Q5)) +#define BIT_GET_HEAD_PKT_Q5(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5) & BIT_MASK_HEAD_PKT_Q5) +#define BIT_SET_HEAD_PKT_Q5(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5(x) | BIT_HEAD_PKT_Q5(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +/* 2 REG_Q5_INFO (Offset 0x046C) */ -#define BIT_EN_TXBCN_RPT BIT(2) +#define BIT_SHIFT_HEAD_PKT_Q5_V1 0 +#define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff +#define BIT_HEAD_PKT_Q5_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1) +#define BITS_HEAD_PKT_Q5_V1 \ + (BIT_MASK_HEAD_PKT_Q5_V1 << BIT_SHIFT_HEAD_PKT_Q5_V1) +#define BIT_CLEAR_HEAD_PKT_Q5_V1(x) ((x) & (~BITS_HEAD_PKT_Q5_V1)) +#define BIT_GET_HEAD_PKT_Q5_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1) +#define BIT_SET_HEAD_PKT_Q5_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5_V1(x) | BIT_HEAD_PKT_Q5_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q6_INFO (Offset 0x0470) */ +#define BIT_SHIFT_QUEUEMACID_Q6_V1 25 +#define BIT_MASK_QUEUEMACID_Q6_V1 0x7f +#define BIT_QUEUEMACID_Q6_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1) +#define BITS_QUEUEMACID_Q6_V1 \ + (BIT_MASK_QUEUEMACID_Q6_V1 << BIT_SHIFT_QUEUEMACID_Q6_V1) +#define BIT_CLEAR_QUEUEMACID_Q6_V1(x) ((x) & (~BITS_QUEUEMACID_Q6_V1)) +#define BIT_GET_QUEUEMACID_Q6_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1) +#define BIT_SET_QUEUEMACID_Q6_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q6_V1(x) | BIT_QUEUEMACID_Q6_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q6_V1 23 +#define BIT_MASK_QUEUEAC_Q6_V1 0x3 +#define BIT_QUEUEAC_Q6_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1) +#define BITS_QUEUEAC_Q6_V1 (BIT_MASK_QUEUEAC_Q6_V1 << BIT_SHIFT_QUEUEAC_Q6_V1) +#define BIT_CLEAR_QUEUEAC_Q6_V1(x) ((x) & (~BITS_QUEUEAC_Q6_V1)) +#define BIT_GET_QUEUEAC_Q6_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1) +#define BIT_SET_QUEUEAC_Q6_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q6_V1(x) | BIT_QUEUEAC_Q6_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +/* 2 REG_Q6_INFO (Offset 0x0470) */ -#define BIT_P0_EN_RXBCN_RPT BIT(2) +#define BIT_TIDEMPTY_Q6_V1 BIT(22) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q6_INFO (Offset 0x0470) */ -/* 2 REG_BCN_CTRL (Offset 0x0550) */ - -#define BIT_DIS_BCNQ_SUB BIT(1) +#define BIT_SHIFT_TAIL_PKT_Q6_V1 15 +#define BIT_MASK_TAIL_PKT_Q6_V1 0xff +#define BIT_TAIL_PKT_Q6_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V1) << BIT_SHIFT_TAIL_PKT_Q6_V1) +#define BITS_TAIL_PKT_Q6_V1 \ + (BIT_MASK_TAIL_PKT_Q6_V1 << BIT_SHIFT_TAIL_PKT_Q6_V1) +#define BIT_CLEAR_TAIL_PKT_Q6_V1(x) ((x) & (~BITS_TAIL_PKT_Q6_V1)) +#define BIT_GET_TAIL_PKT_Q6_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V1) & BIT_MASK_TAIL_PKT_Q6_V1) +#define BIT_SET_TAIL_PKT_Q6_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V1(x) | BIT_TAIL_PKT_Q6_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_BCN_CTRL (Offset 0x0550) */ +/* 2 REG_Q6_INFO (Offset 0x0470) */ -#define BIT_EN_P2P_CTWINDOW BIT(1) -#define BIT_EN_P2P_BCNQ_AREA BIT(0) +#define BIT_SHIFT_TAIL_PKT_Q6_V2 11 +#define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff +#define BIT_TAIL_PKT_Q6_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2) +#define BITS_TAIL_PKT_Q6_V2 \ + (BIT_MASK_TAIL_PKT_Q6_V2 << BIT_SHIFT_TAIL_PKT_Q6_V2) +#define BIT_CLEAR_TAIL_PKT_Q6_V2(x) ((x) & (~BITS_TAIL_PKT_Q6_V2)) +#define BIT_GET_TAIL_PKT_Q6_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2) +#define BIT_SET_TAIL_PKT_Q6_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V2(x) | BIT_TAIL_PKT_Q6_V2(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q6_INFO (Offset 0x0470) */ + +#define BIT_SHIFT_PKT_NUM_Q6_V1 8 +#define BIT_MASK_PKT_NUM_Q6_V1 0x7f +#define BIT_PKT_NUM_Q6_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q6_V1) << BIT_SHIFT_PKT_NUM_Q6_V1) +#define BITS_PKT_NUM_Q6_V1 (BIT_MASK_PKT_NUM_Q6_V1 << BIT_SHIFT_PKT_NUM_Q6_V1) +#define BIT_CLEAR_PKT_NUM_Q6_V1(x) ((x) & (~BITS_PKT_NUM_Q6_V1)) +#define BIT_GET_PKT_NUM_Q6_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q6_V1) & BIT_MASK_PKT_NUM_Q6_V1) +#define BIT_SET_PKT_NUM_Q6_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q6_V1(x) | BIT_PKT_NUM_Q6_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q6 0 +#define BIT_MASK_HEAD_PKT_Q6 0xff +#define BIT_HEAD_PKT_Q6(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6) << BIT_SHIFT_HEAD_PKT_Q6) +#define BITS_HEAD_PKT_Q6 (BIT_MASK_HEAD_PKT_Q6 << BIT_SHIFT_HEAD_PKT_Q6) +#define BIT_CLEAR_HEAD_PKT_Q6(x) ((x) & (~BITS_HEAD_PKT_Q6)) +#define BIT_GET_HEAD_PKT_Q6(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6) & BIT_MASK_HEAD_PKT_Q6) +#define BIT_SET_HEAD_PKT_Q6(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6(x) | BIT_HEAD_PKT_Q6(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +/* 2 REG_Q6_INFO (Offset 0x0470) */ -#define BIT_DIS_RX_BSSID_FIT1 BIT(6) +#define BIT_SHIFT_HEAD_PKT_Q6_V1 0 +#define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff +#define BIT_HEAD_PKT_Q6_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1) +#define BITS_HEAD_PKT_Q6_V1 \ + (BIT_MASK_HEAD_PKT_Q6_V1 << BIT_SHIFT_HEAD_PKT_Q6_V1) +#define BIT_CLEAR_HEAD_PKT_Q6_V1(x) ((x) & (~BITS_HEAD_PKT_Q6_V1)) +#define BIT_GET_HEAD_PKT_Q6_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1) +#define BIT_SET_HEAD_PKT_Q6_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6_V1(x) | BIT_HEAD_PKT_Q6_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q7_INFO (Offset 0x0474) */ +#define BIT_SHIFT_QUEUEMACID_Q7_V1 25 +#define BIT_MASK_QUEUEMACID_Q7_V1 0x7f +#define BIT_QUEUEMACID_Q7_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1) +#define BITS_QUEUEMACID_Q7_V1 \ + (BIT_MASK_QUEUEMACID_Q7_V1 << BIT_SHIFT_QUEUEMACID_Q7_V1) +#define BIT_CLEAR_QUEUEMACID_Q7_V1(x) ((x) & (~BITS_QUEUEMACID_Q7_V1)) +#define BIT_GET_QUEUEMACID_Q7_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1) +#define BIT_SET_QUEUEMACID_Q7_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q7_V1(x) | BIT_QUEUEMACID_Q7_V1(v)) + +#define BIT_SHIFT_QUEUEAC_Q7_V1 23 +#define BIT_MASK_QUEUEAC_Q7_V1 0x3 +#define BIT_QUEUEAC_Q7_V1(x) \ + (((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1) +#define BITS_QUEUEAC_Q7_V1 (BIT_MASK_QUEUEAC_Q7_V1 << BIT_SHIFT_QUEUEAC_Q7_V1) +#define BIT_CLEAR_QUEUEAC_Q7_V1(x) ((x) & (~BITS_QUEUEAC_Q7_V1)) +#define BIT_GET_QUEUEAC_Q7_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1) +#define BIT_SET_QUEUEAC_Q7_V1(x, v) \ + (BIT_CLEAR_QUEUEAC_Q7_V1(x) | BIT_QUEUEAC_Q7_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +/* 2 REG_Q7_INFO (Offset 0x0474) */ -#define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6) +#define BIT_TIDEMPTY_Q7_V1 BIT(22) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q7_INFO (Offset 0x0474) */ -/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ - -#define BIT_DIS_TSF1_UDT BIT(4) +#define BIT_SHIFT_TAIL_PKT_Q7_V1 15 +#define BIT_MASK_TAIL_PKT_Q7_V1 0xff +#define BIT_TAIL_PKT_Q7_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V1) << BIT_SHIFT_TAIL_PKT_Q7_V1) +#define BITS_TAIL_PKT_Q7_V1 \ + (BIT_MASK_TAIL_PKT_Q7_V1 << BIT_SHIFT_TAIL_PKT_Q7_V1) +#define BIT_CLEAR_TAIL_PKT_Q7_V1(x) ((x) & (~BITS_TAIL_PKT_Q7_V1)) +#define BIT_GET_TAIL_PKT_Q7_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V1) & BIT_MASK_TAIL_PKT_Q7_V1) +#define BIT_SET_TAIL_PKT_Q7_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V1(x) | BIT_TAIL_PKT_Q7_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +/* 2 REG_Q7_INFO (Offset 0x0474) */ -#define BIT_CLI0_DIS_TSF_UDT BIT(4) +#define BIT_SHIFT_TAIL_PKT_Q7_V2 11 +#define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff +#define BIT_TAIL_PKT_Q7_V2(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2) +#define BITS_TAIL_PKT_Q7_V2 \ + (BIT_MASK_TAIL_PKT_Q7_V2 << BIT_SHIFT_TAIL_PKT_Q7_V2) +#define BIT_CLEAR_TAIL_PKT_Q7_V2(x) ((x) & (~BITS_TAIL_PKT_Q7_V2)) +#define BIT_GET_TAIL_PKT_Q7_V2(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2) +#define BIT_SET_TAIL_PKT_Q7_V2(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V2(x) | BIT_TAIL_PKT_Q7_V2(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_Q7_INFO (Offset 0x0474) */ + +#define BIT_SHIFT_PKT_NUM_Q7_V1 8 +#define BIT_MASK_PKT_NUM_Q7_V1 0x7f +#define BIT_PKT_NUM_Q7_V1(x) \ + (((x) & BIT_MASK_PKT_NUM_Q7_V1) << BIT_SHIFT_PKT_NUM_Q7_V1) +#define BITS_PKT_NUM_Q7_V1 (BIT_MASK_PKT_NUM_Q7_V1 << BIT_SHIFT_PKT_NUM_Q7_V1) +#define BIT_CLEAR_PKT_NUM_Q7_V1(x) ((x) & (~BITS_PKT_NUM_Q7_V1)) +#define BIT_GET_PKT_NUM_Q7_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_Q7_V1) & BIT_MASK_PKT_NUM_Q7_V1) +#define BIT_SET_PKT_NUM_Q7_V1(x, v) \ + (BIT_CLEAR_PKT_NUM_Q7_V1(x) | BIT_PKT_NUM_Q7_V1(v)) + +#define BIT_SHIFT_HEAD_PKT_Q7 0 +#define BIT_MASK_HEAD_PKT_Q7 0xff +#define BIT_HEAD_PKT_Q7(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7) << BIT_SHIFT_HEAD_PKT_Q7) +#define BITS_HEAD_PKT_Q7 (BIT_MASK_HEAD_PKT_Q7 << BIT_SHIFT_HEAD_PKT_Q7) +#define BIT_CLEAR_HEAD_PKT_Q7(x) ((x) & (~BITS_HEAD_PKT_Q7)) +#define BIT_GET_HEAD_PKT_Q7(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7) & BIT_MASK_HEAD_PKT_Q7) +#define BIT_SET_HEAD_PKT_Q7(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7(x) | BIT_HEAD_PKT_Q7(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +/* 2 REG_Q7_INFO (Offset 0x0474) */ -#define BIT_EN_BCN1_FUNCTION BIT(3) +#define BIT_SHIFT_HEAD_PKT_Q7_V1 0 +#define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff +#define BIT_HEAD_PKT_Q7_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1) +#define BITS_HEAD_PKT_Q7_V1 \ + (BIT_MASK_HEAD_PKT_Q7_V1 << BIT_SHIFT_HEAD_PKT_Q7_V1) +#define BIT_CLEAR_HEAD_PKT_Q7_V1(x) ((x) & (~BITS_HEAD_PKT_Q7_V1)) +#define BIT_GET_HEAD_PKT_Q7_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1) +#define BIT_SET_HEAD_PKT_Q7_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7_V1(x) | BIT_HEAD_PKT_Q7_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_LBK_BUF_HD_V1 (Offset 0x0478) */ +#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0 +#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff +#define BIT_WMAC_LBK_BUF_HEAD_V1(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) +#define BITS_WMAC_LBK_BUF_HEAD_V1 \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) | BIT_WMAC_LBK_BUF_HEAD_V1(v)) -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +/* 2 REG_MGQ_BDNY_V1 (Offset 0x047A) */ -#define BIT_CLI0_EN_BCN_FUNCTION BIT(3) +#define BIT_SHIFT_MGQ_PGBNDY_V1 0 +#define BIT_MASK_MGQ_PGBNDY_V1 0xfff +#define BIT_MGQ_PGBNDY_V1(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1) +#define BITS_MGQ_PGBNDY_V1 (BIT_MASK_MGQ_PGBNDY_V1 << BIT_SHIFT_MGQ_PGBNDY_V1) +#define BIT_CLEAR_MGQ_PGBNDY_V1(x) ((x) & (~BITS_MGQ_PGBNDY_V1)) +#define BIT_GET_MGQ_PGBNDY_V1(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1) +#define BIT_SET_MGQ_PGBNDY_V1(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1(x) | BIT_MGQ_PGBNDY_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_SPC_READ_PTR 24 +#define BIT_MASK_SPC_READ_PTR 0xf +#define BIT_SPC_READ_PTR(x) \ + (((x) & BIT_MASK_SPC_READ_PTR) << BIT_SHIFT_SPC_READ_PTR) +#define BITS_SPC_READ_PTR (BIT_MASK_SPC_READ_PTR << BIT_SHIFT_SPC_READ_PTR) +#define BIT_CLEAR_SPC_READ_PTR(x) ((x) & (~BITS_SPC_READ_PTR)) +#define BIT_GET_SPC_READ_PTR(x) \ + (((x) >> BIT_SHIFT_SPC_READ_PTR) & BIT_MASK_SPC_READ_PTR) +#define BIT_SET_SPC_READ_PTR(x, v) \ + (BIT_CLEAR_SPC_READ_PTR(x) | BIT_SPC_READ_PTR(v)) -/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +#endif -#define BIT_EN_TXBCN1_RPT BIT(2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_TRXRPT_TIMER_TH 24 +#define BIT_MASK_TRXRPT_TIMER_TH 0xff +#define BIT_TRXRPT_TIMER_TH(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH) +#define BITS_TRXRPT_TIMER_TH \ + (BIT_MASK_TRXRPT_TIMER_TH << BIT_SHIFT_TRXRPT_TIMER_TH) +#define BIT_CLEAR_TRXRPT_TIMER_TH(x) ((x) & (~BITS_TRXRPT_TIMER_TH)) +#define BIT_GET_TRXRPT_TIMER_TH(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH) +#define BIT_SET_TRXRPT_TIMER_TH(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH(x) | BIT_TRXRPT_TIMER_TH(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ -#define BIT_CLI0_EN_RXBCN_RPT BIT(2) +#define BIT_SHIFT_SPC_WRITE_PTR 16 +#define BIT_MASK_SPC_WRITE_PTR 0xf +#define BIT_SPC_WRITE_PTR(x) \ + (((x) & BIT_MASK_SPC_WRITE_PTR) << BIT_SHIFT_SPC_WRITE_PTR) +#define BITS_SPC_WRITE_PTR (BIT_MASK_SPC_WRITE_PTR << BIT_SHIFT_SPC_WRITE_PTR) +#define BIT_CLEAR_SPC_WRITE_PTR(x) ((x) & (~BITS_SPC_WRITE_PTR)) +#define BIT_GET_SPC_WRITE_PTR(x) \ + (((x) >> BIT_SHIFT_SPC_WRITE_PTR) & BIT_MASK_SPC_WRITE_PTR) +#define BIT_SET_SPC_WRITE_PTR(x, v) \ + (BIT_CLEAR_SPC_WRITE_PTR(x) | BIT_SPC_WRITE_PTR(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_TRXRPT_LEN_TH 16 +#define BIT_MASK_TRXRPT_LEN_TH 0xff +#define BIT_TRXRPT_LEN_TH(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH) +#define BITS_TRXRPT_LEN_TH (BIT_MASK_TRXRPT_LEN_TH << BIT_SHIFT_TRXRPT_LEN_TH) +#define BIT_CLEAR_TRXRPT_LEN_TH(x) ((x) & (~BITS_TRXRPT_LEN_TH)) +#define BIT_GET_TRXRPT_LEN_TH(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH) +#define BIT_SET_TRXRPT_LEN_TH(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH(x) | BIT_TRXRPT_LEN_TH(v)) -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#endif -#define BIT_CLI0_EN_BCN_RPT BIT(2) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ +#define BIT_SHIFT_AC_READ_PTR 8 +#define BIT_MASK_AC_READ_PTR 0xf +#define BIT_AC_READ_PTR(x) \ + (((x) & BIT_MASK_AC_READ_PTR) << BIT_SHIFT_AC_READ_PTR) +#define BITS_AC_READ_PTR (BIT_MASK_AC_READ_PTR << BIT_SHIFT_AC_READ_PTR) +#define BIT_CLEAR_AC_READ_PTR(x) ((x) & (~BITS_AC_READ_PTR)) +#define BIT_GET_AC_READ_PTR(x) \ + (((x) >> BIT_SHIFT_AC_READ_PTR) & BIT_MASK_AC_READ_PTR) +#define BIT_SET_AC_READ_PTR(x, v) \ + (BIT_CLEAR_AC_READ_PTR(x) | BIT_AC_READ_PTR(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ -#define BIT_DIS_BCNQ1_SUB BIT(1) +#define BIT_SHIFT_TRXRPT_READ_PTR 8 +#define BIT_MASK_TRXRPT_READ_PTR 0xff +#define BIT_TRXRPT_READ_PTR(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR) +#define BITS_TRXRPT_READ_PTR \ + (BIT_MASK_TRXRPT_READ_PTR << BIT_SHIFT_TRXRPT_READ_PTR) +#define BIT_CLEAR_TRXRPT_READ_PTR(x) ((x) & (~BITS_TRXRPT_READ_PTR)) +#define BIT_GET_TRXRPT_READ_PTR(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR) +#define BIT_SET_TRXRPT_READ_PTR(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR(x) | BIT_TRXRPT_READ_PTR(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ + +#define BIT_SHIFT_AC_WRITE_PTR 0 +#define BIT_MASK_AC_WRITE_PTR 0xf +#define BIT_AC_WRITE_PTR(x) \ + (((x) & BIT_MASK_AC_WRITE_PTR) << BIT_SHIFT_AC_WRITE_PTR) +#define BITS_AC_WRITE_PTR (BIT_MASK_AC_WRITE_PTR << BIT_SHIFT_AC_WRITE_PTR) +#define BIT_CLEAR_AC_WRITE_PTR(x) ((x) & (~BITS_AC_WRITE_PTR)) +#define BIT_GET_AC_WRITE_PTR(x) \ + (((x) >> BIT_SHIFT_AC_WRITE_PTR) & BIT_MASK_AC_WRITE_PTR) +#define BIT_SET_AC_WRITE_PTR(x, v) \ + (BIT_CLEAR_AC_WRITE_PTR(x) | BIT_AC_WRITE_PTR(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +/* 2 REG_TXRPT_CTRL (Offset 0x047C) */ -#define BIT_CLI0_ENP2P_CTWINDOW BIT(1) -#define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0) +#define BIT_SHIFT_TRXRPT_WRITE_PTR 0 +#define BIT_MASK_TRXRPT_WRITE_PTR 0xff +#define BIT_TRXRPT_WRITE_PTR(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR) +#define BITS_TRXRPT_WRITE_PTR \ + (BIT_MASK_TRXRPT_WRITE_PTR << BIT_SHIFT_TRXRPT_WRITE_PTR) +#define BIT_CLEAR_TRXRPT_WRITE_PTR(x) ((x) & (~BITS_TRXRPT_WRITE_PTR)) +#define BIT_GET_TRXRPT_WRITE_PTR(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR) +#define BIT_SET_TRXRPT_WRITE_PTR(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR(x) | BIT_TRXRPT_WRITE_PTR(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_INIRTS_RATE_SEL (Offset 0x0480) */ +#define BIT_LEAG_RTS_BW_DUP BIT(5) -/* 2 REG_MBID_NUM (Offset 0x0552) */ +/* 2 REG_BASIC_CFEND_RATE (Offset 0x0481) */ -#define BIT_EN_PRE_DL_BEACON BIT(3) +#define BIT_SHIFT_BASIC_CFEND_RATE 0 +#define BIT_MASK_BASIC_CFEND_RATE 0x1f +#define BIT_BASIC_CFEND_RATE(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE) +#define BITS_BASIC_CFEND_RATE \ + (BIT_MASK_BASIC_CFEND_RATE << BIT_SHIFT_BASIC_CFEND_RATE) +#define BIT_CLEAR_BASIC_CFEND_RATE(x) ((x) & (~BITS_BASIC_CFEND_RATE)) +#define BIT_GET_BASIC_CFEND_RATE(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE) +#define BIT_SET_BASIC_CFEND_RATE(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE(x) | BIT_BASIC_CFEND_RATE(v)) -#define BIT_SHIFT_MBID_BCN_NUM 0 -#define BIT_MASK_MBID_BCN_NUM 0x7 -#define BIT_MBID_BCN_NUM(x) (((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM) -#define BIT_GET_MBID_BCN_NUM(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM) +/* 2 REG_STBC_CFEND_RATE (Offset 0x0482) */ +#define BIT_SHIFT_STBC_CFEND_RATE 0 +#define BIT_MASK_STBC_CFEND_RATE 0x1f +#define BIT_STBC_CFEND_RATE(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE) +#define BITS_STBC_CFEND_RATE \ + (BIT_MASK_STBC_CFEND_RATE << BIT_SHIFT_STBC_CFEND_RATE) +#define BIT_CLEAR_STBC_CFEND_RATE(x) ((x) & (~BITS_STBC_CFEND_RATE)) +#define BIT_GET_STBC_CFEND_RATE(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE) +#define BIT_SET_STBC_CFEND_RATE(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE(x) | BIT_STBC_CFEND_RATE(v)) -#endif +/* 2 REG_DATA_SC (Offset 0x0483) */ +#define BIT_SHIFT_TXSC_40M 4 +#define BIT_MASK_TXSC_40M 0xf +#define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) +#define BITS_TXSC_40M (BIT_MASK_TXSC_40M << BIT_SHIFT_TXSC_40M) +#define BIT_CLEAR_TXSC_40M(x) ((x) & (~BITS_TXSC_40M)) +#define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M) +#define BIT_SET_TXSC_40M(x, v) (BIT_CLEAR_TXSC_40M(x) | BIT_TXSC_40M(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#define BIT_SHIFT_TXSC_20M 0 +#define BIT_MASK_TXSC_20M 0xf +#define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) +#define BITS_TXSC_20M (BIT_MASK_TXSC_20M << BIT_SHIFT_TXSC_20M) +#define BIT_CLEAR_TXSC_20M(x) ((x) & (~BITS_TXSC_20M)) +#define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M) +#define BIT_SET_TXSC_20M(x, v) (BIT_CLEAR_TXSC_20M(x) | BIT_TXSC_20M(v)) +#endif -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_MACID_SLEEP3 (Offset 0x0484) */ -#define BIT_P2P_PWR_RST1 BIT(6) -#define BIT_SCHEDULER_RST BIT(5) +#define BIT_SHIFT_MACID127_96_PKTSLEEP 0 +#define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL +#define BIT_MACID127_96_PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID127_96_PKTSLEEP) \ + << BIT_SHIFT_MACID127_96_PKTSLEEP) +#define BITS_MACID127_96_PKTSLEEP \ + (BIT_MASK_MACID127_96_PKTSLEEP << BIT_SHIFT_MACID127_96_PKTSLEEP) +#define BIT_CLEAR_MACID127_96_PKTSLEEP(x) ((x) & (~BITS_MACID127_96_PKTSLEEP)) +#define BIT_GET_MACID127_96_PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) & \ + BIT_MASK_MACID127_96_PKTSLEEP) +#define BIT_SET_MACID127_96_PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID127_96_PKTSLEEP(x) | BIT_MACID127_96_PKTSLEEP(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MACID_SLEEP3 (Offset 0x0484) */ +#define BIT_SHIFT_MACID103_96_PKTSLEEP 0 +#define BIT_MASK_MACID103_96_PKTSLEEP 0xff +#define BIT_MACID103_96_PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID103_96_PKTSLEEP) \ + << BIT_SHIFT_MACID103_96_PKTSLEEP) +#define BITS_MACID103_96_PKTSLEEP \ + (BIT_MASK_MACID103_96_PKTSLEEP << BIT_SHIFT_MACID103_96_PKTSLEEP) +#define BIT_CLEAR_MACID103_96_PKTSLEEP(x) ((x) & (~BITS_MACID103_96_PKTSLEEP)) +#define BIT_GET_MACID103_96_PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID103_96_PKTSLEEP) & \ + BIT_MASK_MACID103_96_PKTSLEEP) +#define BIT_SET_MACID103_96_PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID103_96_PKTSLEEP(x) | BIT_MACID103_96_PKTSLEEP(v)) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_MACID_SLEEP4 (Offset 0x0485) */ -#define BIT_FREECNT_RST BIT(5) +#define BIT_SHIFT_MACID119_104_PKTSLEEP 0 +#define BIT_MASK_MACID119_104_PKTSLEEP 0xffff +#define BIT_MACID119_104_PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID119_104_PKTSLEEP) \ + << BIT_SHIFT_MACID119_104_PKTSLEEP) +#define BITS_MACID119_104_PKTSLEEP \ + (BIT_MASK_MACID119_104_PKTSLEEP << BIT_SHIFT_MACID119_104_PKTSLEEP) +#define BIT_CLEAR_MACID119_104_PKTSLEEP(x) ((x) & (~BITS_MACID119_104_PKTSLEEP)) +#define BIT_GET_MACID119_104_PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID119_104_PKTSLEEP) & \ + BIT_MASK_MACID119_104_PKTSLEEP) +#define BIT_SET_MACID119_104_PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID119_104_PKTSLEEP(x) | BIT_MACID119_104_PKTSLEEP(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DATA_SC1 (Offset 0x0487) */ +#define BIT_SHIFT_TXSC_160M 4 +#define BIT_MASK_TXSC_160M 0xf +#define BIT_TXSC_160M(x) (((x) & BIT_MASK_TXSC_160M) << BIT_SHIFT_TXSC_160M) +#define BITS_TXSC_160M (BIT_MASK_TXSC_160M << BIT_SHIFT_TXSC_160M) +#define BIT_CLEAR_TXSC_160M(x) ((x) & (~BITS_TXSC_160M)) +#define BIT_GET_TXSC_160M(x) (((x) >> BIT_SHIFT_TXSC_160M) & BIT_MASK_TXSC_160M) +#define BIT_SET_TXSC_160M(x, v) (BIT_CLEAR_TXSC_160M(x) | BIT_TXSC_160M(v)) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#endif -#define BIT_P2P_PWR_RST0 BIT(4) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_MACID_SLEEP5 (Offset 0x0487) */ +#define BIT_SHIFT_MACID127_120_PKTSLEEP 0 +#define BIT_MASK_MACID127_120_PKTSLEEP 0xff +#define BIT_MACID127_120_PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID127_120_PKTSLEEP) \ + << BIT_SHIFT_MACID127_120_PKTSLEEP) +#define BITS_MACID127_120_PKTSLEEP \ + (BIT_MASK_MACID127_120_PKTSLEEP << BIT_SHIFT_MACID127_120_PKTSLEEP) +#define BIT_CLEAR_MACID127_120_PKTSLEEP(x) ((x) & (~BITS_MACID127_120_PKTSLEEP)) +#define BIT_GET_MACID127_120_PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID127_120_PKTSLEEP) & \ + BIT_MASK_MACID127_120_PKTSLEEP) +#define BIT_SET_MACID127_120_PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID127_120_PKTSLEEP(x) | BIT_MACID127_120_PKTSLEEP(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_DATA_SC1 (Offset 0x0487) */ -#define BIT_TSFTR_CLI3_RST BIT(4) +#define BIT_SHIFT_TXSC_80M 0 +#define BIT_MASK_TXSC_80M 0xf +#define BIT_TXSC_80M(x) (((x) & BIT_MASK_TXSC_80M) << BIT_SHIFT_TXSC_80M) +#define BITS_TXSC_80M (BIT_MASK_TXSC_80M << BIT_SHIFT_TXSC_80M) +#define BIT_CLEAR_TXSC_80M(x) ((x) & (~BITS_TXSC_80M)) +#define BIT_GET_TXSC_80M(x) (((x) >> BIT_SHIFT_TXSC_80M) & BIT_MASK_TXSC_80M) +#define BIT_SET_TXSC_80M(x, v) (BIT_CLEAR_TXSC_80M(x) | BIT_TXSC_80M(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MACID_SLEEP1 (Offset 0x0488) */ +#define BIT_SHIFT_MACID63_32_PKTSLEEP 0 +#define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL +#define BIT_MACID63_32_PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP) +#define BITS_MACID63_32_PKTSLEEP \ + (BIT_MASK_MACID63_32_PKTSLEEP << BIT_SHIFT_MACID63_32_PKTSLEEP) +#define BIT_CLEAR_MACID63_32_PKTSLEEP(x) ((x) & (~BITS_MACID63_32_PKTSLEEP)) +#define BIT_GET_MACID63_32_PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP) +#define BIT_SET_MACID63_32_PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID63_32_PKTSLEEP(x) | BIT_MACID63_32_PKTSLEEP(v)) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#endif -#define BIT_TSFTR1_SYNC_EN BIT(3) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_ARFR2_V1 (Offset 0x048C) */ +#define BIT_SHIFT_ARFR2_V1 0 +#define BIT_MASK_ARFR2_V1 0xffffffffffffffffL +#define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1) +#define BITS_ARFR2_V1 (BIT_MASK_ARFR2_V1 << BIT_SHIFT_ARFR2_V1) +#define BIT_CLEAR_ARFR2_V1(x) ((x) & (~BITS_ARFR2_V1)) +#define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1) +#define BIT_SET_ARFR2_V1(x, v) (BIT_CLEAR_ARFR2_V1(x) | BIT_ARFR2_V1(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_ARFR2 (Offset 0x048C) */ -#define BIT_TSFTR_CLI2_RST BIT(3) +#define BIT_SHIFT_ARFRL2 0 +#define BIT_MASK_ARFRL2 0xffffffffL +#define BIT_ARFRL2(x) (((x) & BIT_MASK_ARFRL2) << BIT_SHIFT_ARFRL2) +#define BITS_ARFRL2 (BIT_MASK_ARFRL2 << BIT_SHIFT_ARFRL2) +#define BIT_CLEAR_ARFRL2(x) ((x) & (~BITS_ARFRL2)) +#define BIT_GET_ARFRL2(x) (((x) >> BIT_SHIFT_ARFRL2) & BIT_MASK_ARFRL2) +#define BIT_SET_ARFRL2(x, v) (BIT_CLEAR_ARFRL2(x) | BIT_ARFRL2(v)) -#endif +/* 2 REG_ARFRH2 (Offset 0x0490) */ +#define BIT_SHIFT_ARFRH2 0 +#define BIT_MASK_ARFRH2 0xffffffffL +#define BIT_ARFRH2(x) (((x) & BIT_MASK_ARFRH2) << BIT_SHIFT_ARFRH2) +#define BITS_ARFRH2 (BIT_MASK_ARFRH2 << BIT_SHIFT_ARFRH2) +#define BIT_CLEAR_ARFRH2(x) ((x) & (~BITS_ARFRH2)) +#define BIT_GET_ARFRH2(x) (((x) >> BIT_SHIFT_ARFRH2) & BIT_MASK_ARFRH2) +#define BIT_SET_ARFRH2(x, v) (BIT_CLEAR_ARFRH2(x) | BIT_ARFRH2(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_ARFR3_V1 (Offset 0x0494) */ -#define BIT_TSFTR_SYNC_EN BIT(2) +#define BIT_SHIFT_ARFR3_V1 0 +#define BIT_MASK_ARFR3_V1 0xffffffffffffffffL +#define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1) +#define BITS_ARFR3_V1 (BIT_MASK_ARFR3_V1 << BIT_SHIFT_ARFR3_V1) +#define BIT_CLEAR_ARFR3_V1(x) ((x) & (~BITS_ARFR3_V1)) +#define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1) +#define BIT_SET_ARFR3_V1(x, v) (BIT_CLEAR_ARFR3_V1(x) | BIT_ARFR3_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ARFR3 (Offset 0x0494) */ +#define BIT_SHIFT_ARFRL3 0 +#define BIT_MASK_ARFRL3 0xffffffffL +#define BIT_ARFRL3(x) (((x) & BIT_MASK_ARFRL3) << BIT_SHIFT_ARFRL3) +#define BITS_ARFRL3 (BIT_MASK_ARFRL3 << BIT_SHIFT_ARFRL3) +#define BIT_CLEAR_ARFRL3(x) ((x) & (~BITS_ARFRL3)) +#define BIT_GET_ARFRL3(x) (((x) >> BIT_SHIFT_ARFRL3) & BIT_MASK_ARFRL3) +#define BIT_SET_ARFRL3(x, v) (BIT_CLEAR_ARFRL3(x) | BIT_ARFRL3(v)) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_ARFRH3_V1 (Offset 0x0498) */ -#define BIT_TSFTR_CLI1_RST BIT(2) +#define BIT_SHIFT_ARFRH3 0 +#define BIT_MASK_ARFRH3 0xffffffffL +#define BIT_ARFRH3(x) (((x) & BIT_MASK_ARFRH3) << BIT_SHIFT_ARFRH3) +#define BITS_ARFRH3 (BIT_MASK_ARFRH3 << BIT_SHIFT_ARFRH3) +#define BIT_CLEAR_ARFRH3(x) ((x) & (~BITS_ARFRH3)) +#define BIT_GET_ARFRH3(x) (((x) >> BIT_SHIFT_ARFRH3) & BIT_MASK_ARFRH3) +#define BIT_SET_ARFRH3(x, v) (BIT_CLEAR_ARFRH3(x) | BIT_ARFRH3(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_ARFR4 (Offset 0x049C) */ -#define BIT_TSFTR1_RST BIT(1) +#define BIT_SHIFT_ARFR4 0 +#define BIT_MASK_ARFR4 0xffffffffffffffffL +#define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4) +#define BITS_ARFR4 (BIT_MASK_ARFR4 << BIT_SHIFT_ARFR4) +#define BIT_CLEAR_ARFR4(x) ((x) & (~BITS_ARFR4)) +#define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4) +#define BIT_SET_ARFR4(x, v) (BIT_CLEAR_ARFR4(x) | BIT_ARFR4(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ARFR4 (Offset 0x049C) */ +#define BIT_SHIFT_ARFRL4 0 +#define BIT_MASK_ARFRL4 0xffffffffL +#define BIT_ARFRL4(x) (((x) & BIT_MASK_ARFRL4) << BIT_SHIFT_ARFRL4) +#define BITS_ARFRL4 (BIT_MASK_ARFRL4 << BIT_SHIFT_ARFRL4) +#define BIT_CLEAR_ARFRL4(x) ((x) & (~BITS_ARFRL4)) +#define BIT_GET_ARFRL4(x) (((x) >> BIT_SHIFT_ARFRL4) & BIT_MASK_ARFRL4) +#define BIT_SET_ARFRL4(x, v) (BIT_CLEAR_ARFRL4(x) | BIT_ARFRL4(v)) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +/* 2 REG_ARFRH4 (Offset 0x04A0) */ -#define BIT_TSFTR_CLI0_RST BIT(1) +#define BIT_SHIFT_ARFRH4 0 +#define BIT_MASK_ARFRH4 0xffffffffL +#define BIT_ARFRH4(x) (((x) & BIT_MASK_ARFRH4) << BIT_SHIFT_ARFRH4) +#define BITS_ARFRH4 (BIT_MASK_ARFRH4 << BIT_SHIFT_ARFRH4) +#define BIT_CLEAR_ARFRH4(x) ((x) & (~BITS_ARFRH4)) +#define BIT_GET_ARFRH4(x) (((x) >> BIT_SHIFT_ARFRH4) & BIT_MASK_ARFRH4) +#define BIT_SET_ARFRH4(x, v) (BIT_CLEAR_ARFRH4(x) | BIT_ARFRH4(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ARFR5 (Offset 0x04A4) */ +#define BIT_SHIFT_ARFR5 0 +#define BIT_MASK_ARFR5 0xffffffffffffffffL +#define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5) +#define BITS_ARFR5 (BIT_MASK_ARFR5 << BIT_SHIFT_ARFR5) +#define BIT_CLEAR_ARFR5(x) ((x) & (~BITS_ARFR5)) +#define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5) +#define BIT_SET_ARFR5(x, v) (BIT_CLEAR_ARFR5(x) | BIT_ARFR5(v)) -/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#endif -#define BIT_TSFTR_RST BIT(0) +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ARFR5 (Offset 0x04A4) */ +#define BIT_SHIFT_ARFRL5 0 +#define BIT_MASK_ARFRL5 0xffffffffL +#define BIT_ARFRL5(x) (((x) & BIT_MASK_ARFRL5) << BIT_SHIFT_ARFRL5) +#define BITS_ARFRL5 (BIT_MASK_ARFRL5 << BIT_SHIFT_ARFRL5) +#define BIT_CLEAR_ARFRL5(x) ((x) & (~BITS_ARFRL5)) +#define BIT_GET_ARFRL5(x) (((x) >> BIT_SHIFT_ARFRL5) & BIT_MASK_ARFRL5) +#define BIT_SET_ARFRL5(x, v) (BIT_CLEAR_ARFRL5(x) | BIT_ARFRL5(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ARFRH5 (Offset 0x04A8) */ +#define BIT_SHIFT_ARFRH5 0 +#define BIT_MASK_ARFRH5 0xffffffffL +#define BIT_ARFRH5(x) (((x) & BIT_MASK_ARFRH5) << BIT_SHIFT_ARFRH5) +#define BITS_ARFRH5 (BIT_MASK_ARFRH5 << BIT_SHIFT_ARFRH5) +#define BIT_CLEAR_ARFRH5(x) ((x) & (~BITS_ARFRH5)) +#define BIT_GET_ARFRH5(x) (((x) >> BIT_SHIFT_ARFRH5) & BIT_MASK_ARFRH5) +#define BIT_SET_ARFRH5(x, v) (BIT_CLEAR_ARFRH5(x) | BIT_ARFRH5(v)) -/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28 -#define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7 -#define BIT_BCN_TIMER_SEL_FWRD(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD) -#define BIT_GET_BCN_TIMER_SEL_FWRD(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ + +#define BIT_RPTFIFO_RPTNUM_OPT BIT(31) +#define BIT_SHIFT_MISSED_RPT_NUM 28 +#define BIT_MASK_MISSED_RPT_NUM 0x7 +#define BIT_MISSED_RPT_NUM(x) \ + (((x) & BIT_MASK_MISSED_RPT_NUM) << BIT_SHIFT_MISSED_RPT_NUM) +#define BITS_MISSED_RPT_NUM \ + (BIT_MASK_MISSED_RPT_NUM << BIT_SHIFT_MISSED_RPT_NUM) +#define BIT_CLEAR_MISSED_RPT_NUM(x) ((x) & (~BITS_MISSED_RPT_NUM)) +#define BIT_GET_MISSED_RPT_NUM(x) \ + (((x) >> BIT_SHIFT_MISSED_RPT_NUM) & BIT_MASK_MISSED_RPT_NUM) +#define BIT_SET_MISSED_RPT_NUM(x, v) \ + (BIT_CLEAR_MISSED_RPT_NUM(x) | BIT_MISSED_RPT_NUM(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHCUT_PARSE_DASA BIT(25) -/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BCN_SPACE1 16 -#define BIT_MASK_BCN_SPACE1 0xffff -#define BIT_BCN_SPACE1(x) (((x) & BIT_MASK_BCN_SPACE1) << BIT_SHIFT_BCN_SPACE1) -#define BIT_GET_BCN_SPACE1(x) (((x) >> BIT_SHIFT_BCN_SPACE1) & BIT_MASK_BCN_SPACE1) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_INDEX_15 24 +#define BIT_MASK_INDEX_15 0xff +#define BIT_INDEX_15(x) (((x) & BIT_MASK_INDEX_15) << BIT_SHIFT_INDEX_15) +#define BITS_INDEX_15 (BIT_MASK_INDEX_15 << BIT_SHIFT_INDEX_15) +#define BIT_CLEAR_INDEX_15(x) ((x) & (~BITS_INDEX_15)) +#define BIT_GET_INDEX_15(x) (((x) >> BIT_SHIFT_INDEX_15) & BIT_MASK_INDEX_15) +#define BIT_SET_INDEX_15(x, v) (BIT_CLEAR_INDEX_15(x) | BIT_INDEX_15(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_LOC_AMPDU_BURST_CTRL 24 +#define BIT_MASK_LOC_AMPDU_BURST_CTRL 0xff +#define BIT_LOC_AMPDU_BURST_CTRL(x) \ + (((x) & BIT_MASK_LOC_AMPDU_BURST_CTRL) \ + << BIT_SHIFT_LOC_AMPDU_BURST_CTRL) +#define BITS_LOC_AMPDU_BURST_CTRL \ + (BIT_MASK_LOC_AMPDU_BURST_CTRL << BIT_SHIFT_LOC_AMPDU_BURST_CTRL) +#define BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) ((x) & (~BITS_LOC_AMPDU_BURST_CTRL)) +#define BIT_GET_LOC_AMPDU_BURST_CTRL(x) \ + (((x) >> BIT_SHIFT_LOC_AMPDU_BURST_CTRL) & \ + BIT_MASK_LOC_AMPDU_BURST_CTRL) +#define BIT_SET_LOC_AMPDU_BURST_CTRL(x, v) \ + (BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) | BIT_LOC_AMPDU_BURST_CTRL(v)) -/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_BCN_SPACE_CLINT0 16 -#define BIT_MASK_BCN_SPACE_CLINT0 0xfff -#define BIT_BCN_SPACE_CLINT0(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0) -#define BIT_GET_BCN_SPACE_CLINT0(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_LOC_SWPS_RPT_CTRL 24 +#define BIT_MASK_LOC_SWPS_RPT_CTRL 0xff +#define BIT_LOC_SWPS_RPT_CTRL(x) \ + (((x) & BIT_MASK_LOC_SWPS_RPT_CTRL) << BIT_SHIFT_LOC_SWPS_RPT_CTRL) +#define BITS_LOC_SWPS_RPT_CTRL \ + (BIT_MASK_LOC_SWPS_RPT_CTRL << BIT_SHIFT_LOC_SWPS_RPT_CTRL) +#define BIT_CLEAR_LOC_SWPS_RPT_CTRL(x) ((x) & (~BITS_LOC_SWPS_RPT_CTRL)) +#define BIT_GET_LOC_SWPS_RPT_CTRL(x) \ + (((x) >> BIT_SHIFT_LOC_SWPS_RPT_CTRL) & BIT_MASK_LOC_SWPS_RPT_CTRL) +#define BIT_SET_LOC_SWPS_RPT_CTRL(x, v) \ + (BIT_CLEAR_LOC_SWPS_RPT_CTRL(x) | BIT_LOC_SWPS_RPT_CTRL(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHCUT_BYPASS BIT(24) -/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BCN_SPACE0 0 -#define BIT_MASK_BCN_SPACE0 0xffff -#define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0) -#define BIT_GET_BCN_SPACE0(x) (((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_MACID_MURATE_OFFSET 24 +#define BIT_MASK_MACID_MURATE_OFFSET 0xff +#define BIT_MACID_MURATE_OFFSET(x) \ + (((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET) +#define BITS_MACID_MURATE_OFFSET \ + (BIT_MASK_MACID_MURATE_OFFSET << BIT_SHIFT_MACID_MURATE_OFFSET) +#define BIT_CLEAR_MACID_MURATE_OFFSET(x) ((x) & (~BITS_MACID_MURATE_OFFSET)) +#define BIT_GET_MACID_MURATE_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET) +#define BIT_SET_MACID_MURATE_OFFSET(x, v) \ + (BIT_CLEAR_MACID_MURATE_OFFSET(x) | BIT_MACID_MURATE_OFFSET(v)) -/* 2 REG_DRVERLYINT (Offset 0x0558) */ +#endif +#if (HALMAC_8821C_SUPPORT) -#define BIT_SHIFT_DRVERLYITV 0 -#define BIT_MASK_DRVERLYITV 0xff -#define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV) -#define BIT_GET_DRVERLYITV(x) (((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET 24 +#define BIT_MASK_R_MUTAB_TXRPT_OFFSET 0xff +#define BIT_R_MUTAB_TXRPT_OFFSET(x) \ + (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET) \ + << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) +#define BITS_R_MUTAB_TXRPT_OFFSET \ + (BIT_MASK_R_MUTAB_TXRPT_OFFSET << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) +#define BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) ((x) & (~BITS_R_MUTAB_TXRPT_OFFSET)) +#define BIT_GET_R_MUTAB_TXRPT_OFFSET(x) \ + (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) & \ + BIT_MASK_R_MUTAB_TXRPT_OFFSET) +#define BIT_SET_R_MUTAB_TXRPT_OFFSET(x, v) \ + (BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) | BIT_R_MUTAB_TXRPT_OFFSET(v)) -/* 2 REG_BCNDMATIM (Offset 0x0559) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BCNDMATIM 0 -#define BIT_MASK_BCNDMATIM 0xff -#define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM) -#define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_TXRPT_MISS_COUNT 17 +#define BIT_MASK_TXRPT_MISS_COUNT 0x7 +#define BIT_TXRPT_MISS_COUNT(x) \ + (((x) & BIT_MASK_TXRPT_MISS_COUNT) << BIT_SHIFT_TXRPT_MISS_COUNT) +#define BITS_TXRPT_MISS_COUNT \ + (BIT_MASK_TXRPT_MISS_COUNT << BIT_SHIFT_TXRPT_MISS_COUNT) +#define BIT_CLEAR_TXRPT_MISS_COUNT(x) ((x) & (~BITS_TXRPT_MISS_COUNT)) +#define BIT_GET_TXRPT_MISS_COUNT(x) \ + (((x) >> BIT_SHIFT_TXRPT_MISS_COUNT) & BIT_MASK_TXRPT_MISS_COUNT) +#define BIT_SET_TXRPT_MISS_COUNT(x, v) \ + (BIT_CLEAR_TXRPT_MISS_COUNT(x) | BIT_TXRPT_MISS_COUNT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_LOC_BCN_RPT 16 +#define BIT_MASK_LOC_BCN_RPT 0xff +#define BIT_LOC_BCN_RPT(x) \ + (((x) & BIT_MASK_LOC_BCN_RPT) << BIT_SHIFT_LOC_BCN_RPT) +#define BITS_LOC_BCN_RPT (BIT_MASK_LOC_BCN_RPT << BIT_SHIFT_LOC_BCN_RPT) +#define BIT_CLEAR_LOC_BCN_RPT(x) ((x) & (~BITS_LOC_BCN_RPT)) +#define BIT_GET_LOC_BCN_RPT(x) \ + (((x) >> BIT_SHIFT_LOC_BCN_RPT) & BIT_MASK_LOC_BCN_RPT) +#define BIT_SET_LOC_BCN_RPT(x, v) \ + (BIT_CLEAR_LOC_BCN_RPT(x) | BIT_LOC_BCN_RPT(v)) -/* 2 REG_ATIMWND (Offset 0x055A) */ +#define BIT_SHIFT_INDEX_14 16 +#define BIT_MASK_INDEX_14 0xff +#define BIT_INDEX_14(x) (((x) & BIT_MASK_INDEX_14) << BIT_SHIFT_INDEX_14) +#define BITS_INDEX_14 (BIT_MASK_INDEX_14 << BIT_SHIFT_INDEX_14) +#define BIT_CLEAR_INDEX_14(x) ((x) & (~BITS_INDEX_14)) +#define BIT_GET_INDEX_14(x) (((x) >> BIT_SHIFT_INDEX_14) & BIT_MASK_INDEX_14) +#define BIT_SET_INDEX_14(x, v) (BIT_CLEAR_INDEX_14(x) | BIT_INDEX_14(v)) + +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT) -#define BIT_SHIFT_ATIMWND 0 -#define BIT_MASK_ATIMWND 0xffff -#define BIT_ATIMWND(x) (((x) & BIT_MASK_ATIMWND) << BIT_SHIFT_ATIMWND) -#define BIT_GET_ATIMWND(x) (((x) >> BIT_SHIFT_ATIMWND) & BIT_MASK_ATIMWND) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT__R_RPTFIFO_1K BIT(16) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_RPTFIFO_SIZE_OPT BIT(16) -/* 2 REG_ATIMWND (Offset 0x055A) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_ATIMWND0 0 -#define BIT_MASK_ATIMWND0 0xffff -#define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0) -#define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_MACID_SHCUT_OFFSET 16 +#define BIT_MASK_MACID_SHCUT_OFFSET 0xff +#define BIT_MACID_SHCUT_OFFSET(x) \ + (((x) & BIT_MASK_MACID_SHCUT_OFFSET) << BIT_SHIFT_MACID_SHCUT_OFFSET) +#define BITS_MACID_SHCUT_OFFSET \ + (BIT_MASK_MACID_SHCUT_OFFSET << BIT_SHIFT_MACID_SHCUT_OFFSET) +#define BIT_CLEAR_MACID_SHCUT_OFFSET(x) ((x) & (~BITS_MACID_SHCUT_OFFSET)) +#define BIT_GET_MACID_SHCUT_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET) & BIT_MASK_MACID_SHCUT_OFFSET) +#define BIT_SET_MACID_SHCUT_OFFSET(x, v) \ + (BIT_CLEAR_MACID_SHCUT_OFFSET(x) | BIT_MACID_SHCUT_OFFSET(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_USTIME_TSF (Offset 0x055C) */ +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_MACID_CTRL_OFFSET_V1 16 +#define BIT_MASK_MACID_CTRL_OFFSET_V1 0x1ff +#define BIT_MACID_CTRL_OFFSET_V1(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_V1) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_V1) +#define BITS_MACID_CTRL_OFFSET_V1 \ + (BIT_MASK_MACID_CTRL_OFFSET_V1 << BIT_SHIFT_MACID_CTRL_OFFSET_V1) +#define BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) ((x) & (~BITS_MACID_CTRL_OFFSET_V1)) +#define BIT_GET_MACID_CTRL_OFFSET_V1(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_V1) & \ + BIT_MASK_MACID_CTRL_OFFSET_V1) +#define BIT_SET_MACID_CTRL_OFFSET_V1(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) | BIT_MACID_CTRL_OFFSET_V1(v)) -#define BIT_SHIFT_USTIME_TSF_V1 0 -#define BIT_MASK_USTIME_TSF_V1 0xff -#define BIT_USTIME_TSF_V1(x) (((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1) -#define BIT_GET_USTIME_TSF_V1(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BCN_MAX_ERR (Offset 0x055D) */ +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_LOC_TXRPT 8 +#define BIT_MASK_LOC_TXRPT 0xff +#define BIT_LOC_TXRPT(x) (((x) & BIT_MASK_LOC_TXRPT) << BIT_SHIFT_LOC_TXRPT) +#define BITS_LOC_TXRPT (BIT_MASK_LOC_TXRPT << BIT_SHIFT_LOC_TXRPT) +#define BIT_CLEAR_LOC_TXRPT(x) ((x) & (~BITS_LOC_TXRPT)) +#define BIT_GET_LOC_TXRPT(x) (((x) >> BIT_SHIFT_LOC_TXRPT) & BIT_MASK_LOC_TXRPT) +#define BIT_SET_LOC_TXRPT(x, v) (BIT_CLEAR_LOC_TXRPT(x) | BIT_LOC_TXRPT(v)) -#define BIT_SHIFT_BCN_MAX_ERR 0 -#define BIT_MASK_BCN_MAX_ERR 0xff -#define BIT_BCN_MAX_ERR(x) (((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR) -#define BIT_GET_BCN_MAX_ERR(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR) +#define BIT_SHIFT_INDEX_13 8 +#define BIT_MASK_INDEX_13 0xff +#define BIT_INDEX_13(x) (((x) & BIT_MASK_INDEX_13) << BIT_SHIFT_INDEX_13) +#define BITS_INDEX_13 (BIT_MASK_INDEX_13 << BIT_SHIFT_INDEX_13) +#define BIT_CLEAR_INDEX_13(x) ((x) & (~BITS_INDEX_13)) +#define BIT_GET_INDEX_13(x) (((x) >> BIT_SHIFT_INDEX_13) & BIT_MASK_INDEX_13) +#define BIT_SET_INDEX_13(x, v) (BIT_CLEAR_INDEX_13(x) | BIT_INDEX_13(v)) +#endif -/* 2 REG_RXTSF_OFFSET_CCK (Offset 0x055E) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ -#define BIT_SHIFT_CCK_RXTSF_OFFSET 0 -#define BIT_MASK_CCK_RXTSF_OFFSET 0xff -#define BIT_CCK_RXTSF_OFFSET(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET) -#define BIT_GET_CCK_RXTSF_OFFSET(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET) +#define BIT_SHIFT_MACID_CTRL_OFFSET 8 +#define BIT_MASK_MACID_CTRL_OFFSET 0xff +#define BIT_MACID_CTRL_OFFSET(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET) +#define BITS_MACID_CTRL_OFFSET \ + (BIT_MASK_MACID_CTRL_OFFSET << BIT_SHIFT_MACID_CTRL_OFFSET) +#define BIT_CLEAR_MACID_CTRL_OFFSET(x) ((x) & (~BITS_MACID_CTRL_OFFSET)) +#define BIT_GET_MACID_CTRL_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET) +#define BIT_SET_MACID_CTRL_OFFSET(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET(x) | BIT_MACID_CTRL_OFFSET(v)) +#endif -/* 2 REG_RXTSF_OFFSET_OFDM (Offset 0x055F) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ -#define BIT_SHIFT_OFDM_RXTSF_OFFSET 0 -#define BIT_MASK_OFDM_RXTSF_OFFSET 0xff -#define BIT_OFDM_RXTSF_OFFSET(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET) -#define BIT_GET_OFDM_RXTSF_OFFSET(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET) +#define BIT_SHIFT_LOC_SRFF 0 +#define BIT_MASK_LOC_SRFF 0xff +#define BIT_LOC_SRFF(x) (((x) & BIT_MASK_LOC_SRFF) << BIT_SHIFT_LOC_SRFF) +#define BITS_LOC_SRFF (BIT_MASK_LOC_SRFF << BIT_SHIFT_LOC_SRFF) +#define BIT_CLEAR_LOC_SRFF(x) ((x) & (~BITS_LOC_SRFF)) +#define BIT_GET_LOC_SRFF(x) (((x) >> BIT_SHIFT_LOC_SRFF) & BIT_MASK_LOC_SRFF) +#define BIT_SET_LOC_SRFF(x, v) (BIT_CLEAR_LOC_SRFF(x) | BIT_LOC_SRFF(v)) +#define BIT_SHIFT_INDEX_12 0 +#define BIT_MASK_INDEX_12 0xff +#define BIT_INDEX_12(x) (((x) & BIT_MASK_INDEX_12) << BIT_SHIFT_INDEX_12) +#define BITS_INDEX_12 (BIT_MASK_INDEX_12 << BIT_SHIFT_INDEX_12) +#define BIT_CLEAR_INDEX_12(x) ((x) & (~BITS_INDEX_12)) +#define BIT_GET_INDEX_12(x) (((x) >> BIT_SHIFT_INDEX_12) & BIT_MASK_INDEX_12) +#define BIT_SET_INDEX_12(x, v) (BIT_CLEAR_INDEX_12(x) | BIT_INDEX_12(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT 0 +#define BIT_MASK_RA_TRY_RATE_AGG_LMT 0x1f +#define BIT_RA_TRY_RATE_AGG_LMT(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT) +#define BITS_RA_TRY_RATE_AGG_LMT \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT << BIT_SHIFT_RA_TRY_RATE_AGG_LMT) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) ((x) & (~BITS_RA_TRY_RATE_AGG_LMT)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT) & BIT_MASK_RA_TRY_RATE_AGG_LMT) +#define BIT_SET_RA_TRY_RATE_AGG_LMT(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) | BIT_RA_TRY_RATE_AGG_LMT(v)) -/* 2 REG_TSFTR (Offset 0x0560) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TSF_TIMER 0 -#define BIT_MASK_TSF_TIMER 0xffffffffffffffffL -#define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER) -#define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER) +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0 +#define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff +#define BIT_AMPDU_TXRPT_OFFSET(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET) +#define BITS_AMPDU_TXRPT_OFFSET \ + (BIT_MASK_AMPDU_TXRPT_OFFSET << BIT_SHIFT_AMPDU_TXRPT_OFFSET) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET)) +#define BIT_GET_AMPDU_TXRPT_OFFSET(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET) +#define BIT_SET_AMPDU_TXRPT_OFFSET(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) | BIT_AMPDU_TXRPT_OFFSET(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - - -/* 2 REG_TSFTR (Offset 0x0560) */ +/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ +#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1 0 +#define BIT_MASK_AMPDU_TXRPT_OFFSET_V1 0x1ff +#define BIT_AMPDU_TXRPT_OFFSET_V1(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_V1) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) +#define BITS_AMPDU_TXRPT_OFFSET_V1 \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_V1 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET_V1)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_V1(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_V1) +#define BIT_SET_AMPDU_TXRPT_OFFSET_V1(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) | BIT_AMPDU_TXRPT_OFFSET_V1(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT) + +/* 2 REG_RRSR_CTS (Offset 0x04B0) */ + +#define BIT_SHIFT_RRCTSSR_RSC 21 +#define BIT_MASK_RRCTSSR_RSC 0x3 +#define BIT_RRCTSSR_RSC(x) \ + (((x) & BIT_MASK_RRCTSSR_RSC) << BIT_SHIFT_RRCTSSR_RSC) +#define BITS_RRCTSSR_RSC (BIT_MASK_RRCTSSR_RSC << BIT_SHIFT_RRCTSSR_RSC) +#define BIT_CLEAR_RRCTSSR_RSC(x) ((x) & (~BITS_RRCTSSR_RSC)) +#define BIT_GET_RRCTSSR_RSC(x) \ + (((x) >> BIT_SHIFT_RRCTSSR_RSC) & BIT_MASK_RRCTSSR_RSC) +#define BIT_SET_RRCTSSR_RSC(x, v) \ + (BIT_CLEAR_RRCTSSR_RSC(x) | BIT_RRCTSSR_RSC(v)) + +#define BIT_SHIFT_RRCTSSC_BITMAP 0 +#define BIT_MASK_RRCTSSC_BITMAP 0xfffff +#define BIT_RRCTSSC_BITMAP(x) \ + (((x) & BIT_MASK_RRCTSSC_BITMAP) << BIT_SHIFT_RRCTSSC_BITMAP) +#define BITS_RRCTSSC_BITMAP \ + (BIT_MASK_RRCTSSC_BITMAP << BIT_SHIFT_RRCTSSC_BITMAP) +#define BIT_CLEAR_RRCTSSC_BITMAP(x) ((x) & (~BITS_RRCTSSC_BITMAP)) +#define BIT_GET_RRCTSSC_BITMAP(x) \ + (((x) >> BIT_SHIFT_RRCTSSC_BITMAP) & BIT_MASK_RRCTSSC_BITMAP) +#define BIT_SET_RRCTSSC_BITMAP(x, v) \ + (BIT_CLEAR_RRCTSSC_BITMAP(x) | BIT_RRCTSSC_BITMAP(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TSF_TIMER_V1 0 -#define BIT_MASK_TSF_TIMER_V1 0xffffffffL -#define BIT_TSF_TIMER_V1(x) (((x) & BIT_MASK_TSF_TIMER_V1) << BIT_SHIFT_TSF_TIMER_V1) -#define BIT_GET_TSF_TIMER_V1(x) (((x) >> BIT_SHIFT_TSF_TIMER_V1) & BIT_MASK_TSF_TIMER_V1) +/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ +#define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31) +#define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30) +#define BIT_PTA_WL_PRI_MASK_HIQ BIT(29) +#define BIT_PTA_WL_PRI_MASK_MGQ BIT(28) +#define BIT_PTA_WL_PRI_MASK_BK BIT(27) +#define BIT_PTA_WL_PRI_MASK_BE BIT(26) +#define BIT_PTA_WL_PRI_MASK_VI BIT(25) +#define BIT_PTA_WL_PRI_MASK_VO BIT(24) -/* 2 REG_TSFTR_1 (Offset 0x0564) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TSF_TIMER_V2 0 -#define BIT_MASK_TSF_TIMER_V2 0xffffffffL -#define BIT_TSF_TIMER_V2(x) (((x) & BIT_MASK_TSF_TIMER_V2) << BIT_SHIFT_TSF_TIMER_V2) -#define BIT_GET_TSF_TIMER_V2(x) (((x) >> BIT_SHIFT_TSF_TIMER_V2) & BIT_MASK_TSF_TIMER_V2) +/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ +#define BIT_SHIFT_POWER_STAGE1 0 +#define BIT_MASK_POWER_STAGE1 0xffffff +#define BIT_POWER_STAGE1(x) \ + (((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1) +#define BITS_POWER_STAGE1 (BIT_MASK_POWER_STAGE1 << BIT_SHIFT_POWER_STAGE1) +#define BIT_CLEAR_POWER_STAGE1(x) ((x) & (~BITS_POWER_STAGE1)) +#define BIT_GET_POWER_STAGE1(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1) +#define BIT_SET_POWER_STAGE1(x, v) \ + (BIT_CLEAR_POWER_STAGE1(x) | BIT_POWER_STAGE1(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ +#define BIT_SHIFT_EVTQ_TXRPT 27 +#define BIT_MASK_EVTQ_TXRPT 0x7 +#define BIT_EVTQ_TXRPT(x) (((x) & BIT_MASK_EVTQ_TXRPT) << BIT_SHIFT_EVTQ_TXRPT) +#define BITS_EVTQ_TXRPT (BIT_MASK_EVTQ_TXRPT << BIT_SHIFT_EVTQ_TXRPT) +#define BIT_CLEAR_EVTQ_TXRPT(x) ((x) & (~BITS_EVTQ_TXRPT)) +#define BIT_GET_EVTQ_TXRPT(x) \ + (((x) >> BIT_SHIFT_EVTQ_TXRPT) & BIT_MASK_EVTQ_TXRPT) +#define BIT_SET_EVTQ_TXRPT(x, v) (BIT_CLEAR_EVTQ_TXRPT(x) | BIT_EVTQ_TXRPT(v)) -/* 2 REG_TSFTR1 (Offset 0x0568) */ +#define BIT_PTA_WL_PRI_MASK_EVT BIT(25) + +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_TSF_TIMER1 0 -#define BIT_MASK_TSF_TIMER1 0xffffffffffffffffL -#define BIT_TSF_TIMER1(x) (((x) & BIT_MASK_TSF_TIMER1) << BIT_SHIFT_TSF_TIMER1) -#define BIT_GET_TSF_TIMER1(x) (((x) >> BIT_SHIFT_TSF_TIMER1) & BIT_MASK_TSF_TIMER1) +/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ +#define BIT__CTRL_PKT_POW_ADJ BIT(24) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FREERUN_CNT (Offset 0x0568) */ - - -#define BIT_SHIFT_FREERUN_CNT 0 -#define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL -#define BIT_FREERUN_CNT(x) (((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT) -#define BIT_GET_FREERUN_CNT(x) (((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT) +/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ +#define BIT__R_CTRL_PKT_POW_ADJ BIT(24) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ +#define BIT_SHIFT_POWER_STAGE2 0 +#define BIT_MASK_POWER_STAGE2 0xffffff +#define BIT_POWER_STAGE2(x) \ + (((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2) +#define BITS_POWER_STAGE2 (BIT_MASK_POWER_STAGE2 << BIT_SHIFT_POWER_STAGE2) +#define BIT_CLEAR_POWER_STAGE2(x) ((x) & (~BITS_POWER_STAGE2)) +#define BIT_GET_POWER_STAGE2(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2) +#define BIT_SET_POWER_STAGE2(x, v) \ + (BIT_CLEAR_POWER_STAGE2(x) | BIT_POWER_STAGE2(v)) -/* 2 REG_FREERUN_CNT (Offset 0x0568) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_FREERUN_CNT_V1 0 -#define BIT_MASK_FREERUN_CNT_V1 0xffffffffL -#define BIT_FREERUN_CNT_V1(x) (((x) & BIT_MASK_FREERUN_CNT_V1) << BIT_SHIFT_FREERUN_CNT_V1) -#define BIT_GET_FREERUN_CNT_V1(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V1) & BIT_MASK_FREERUN_CNT_V1) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_SHIFT_EVTQ_HEAD 24 +#define BIT_MASK_EVTQ_HEAD 0xff +#define BIT_EVTQ_HEAD(x) (((x) & BIT_MASK_EVTQ_HEAD) << BIT_SHIFT_EVTQ_HEAD) +#define BITS_EVTQ_HEAD (BIT_MASK_EVTQ_HEAD << BIT_SHIFT_EVTQ_HEAD) +#define BIT_CLEAR_EVTQ_HEAD(x) ((x) & (~BITS_EVTQ_HEAD)) +#define BIT_GET_EVTQ_HEAD(x) (((x) >> BIT_SHIFT_EVTQ_HEAD) & BIT_MASK_EVTQ_HEAD) +#define BIT_SET_EVTQ_HEAD(x, v) (BIT_CLEAR_EVTQ_HEAD(x) | BIT_EVTQ_HEAD(v)) -/* 2 REG_FREERUN_CNT_1 (Offset 0x056C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FREERUN_CNT_V2 0 -#define BIT_MASK_FREERUN_CNT_V2 0xffffffffL -#define BIT_FREERUN_CNT_V2(x) (((x) & BIT_MASK_FREERUN_CNT_V2) << BIT_SHIFT_FREERUN_CNT_V2) -#define BIT_GET_FREERUN_CNT_V2(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V2) & BIT_MASK_FREERUN_CNT_V2) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_SHIFT_PAD_NUM_THRES 24 +#define BIT_MASK_PAD_NUM_THRES 0x3f +#define BIT_PAD_NUM_THRES(x) \ + (((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES) +#define BITS_PAD_NUM_THRES (BIT_MASK_PAD_NUM_THRES << BIT_SHIFT_PAD_NUM_THRES) +#define BIT_CLEAR_PAD_NUM_THRES(x) ((x) & (~BITS_PAD_NUM_THRES)) +#define BIT_GET_PAD_NUM_THRES(x) \ + (((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES) +#define BIT_SET_PAD_NUM_THRES(x, v) \ + (BIT_CLEAR_PAD_NUM_THRES(x) | BIT_PAD_NUM_THRES(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_R_DMA_THIS_QUEUE_BK BIT(23) -/* 2 REG_ATIMWND1 (Offset 0x0570) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_ATIMWND1 0 -#define BIT_MASK_ATIMWND1 0xffff -#define BIT_ATIMWND1(x) (((x) & BIT_MASK_ATIMWND1) << BIT_SHIFT_ATIMWND1) -#define BIT_GET_ATIMWND1(x) (((x) >> BIT_SHIFT_ATIMWND1) & BIT_MASK_ATIMWND1) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_DMA_THIS_QUEUE_BK BIT(23) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_R_DMA_THIS_QUEUE_BE BIT(22) -/* 2 REG_ATIMWND1_V1 (Offset 0x0570) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_ATIMWND1_V1 0 -#define BIT_MASK_ATIMWND1_V1 0xff -#define BIT_ATIMWND1_V1(x) (((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1) -#define BIT_GET_ATIMWND1_V1(x) (((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_DMA_THIS_QUEUE_BE BIT(22) -/* 2 REG_TBTT_PROHIBIT_INFRA (Offset 0x0571) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0 -#define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff -#define BIT_TBTT_PROHIBIT_INFRA(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA) -#define BIT_GET_TBTT_PROHIBIT_INFRA(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_R_DMA_THIS_QUEUE_VI BIT(21) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_DMA_THIS_QUEUE_VI BIT(21) -/* 2 REG_CTWND (Offset 0x0572) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CTWND 0 -#define BIT_MASK_CTWND 0xff -#define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND) -#define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_R_DMA_THIS_QUEUE_VO BIT(20) -/* 2 REG_BCNIVLCUNT (Offset 0x0573) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BCNIVLCUNT 0 -#define BIT_MASK_BCNIVLCUNT 0x7f -#define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT) -#define BIT_GET_BCNIVLCUNT(x) (((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_DMA_THIS_QUEUE_VO BIT(20) -/* 2 REG_BCNDROPCTRL (Offset 0x0574) */ +#endif -#define BIT_BEACON_DROP_EN BIT(7) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BEACON_DROP_IVL 0 -#define BIT_MASK_BEACON_DROP_IVL 0x7f -#define BIT_BEACON_DROP_IVL(x) (((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL) -#define BIT_GET_BEACON_DROP_IVL(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_SHIFT_R_TOTAL_LEN_TH 8 +#define BIT_MASK_R_TOTAL_LEN_TH 0xfff +#define BIT_R_TOTAL_LEN_TH(x) \ + (((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH) +#define BITS_R_TOTAL_LEN_TH \ + (BIT_MASK_R_TOTAL_LEN_TH << BIT_SHIFT_R_TOTAL_LEN_TH) +#define BIT_CLEAR_R_TOTAL_LEN_TH(x) ((x) & (~BITS_R_TOTAL_LEN_TH)) +#define BIT_GET_R_TOTAL_LEN_TH(x) \ + (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH) +#define BIT_SET_R_TOTAL_LEN_TH(x, v) \ + (BIT_CLEAR_R_TOTAL_LEN_TH(x) | BIT_R_TOTAL_LEN_TH(v)) -/* 2 REG_HGQ_TIMEOUT_PERIOD (Offset 0x0575) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0 -#define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff -#define BIT_HGQ_TIMEOUT_PERIOD(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD) -#define BIT_GET_HGQ_TIMEOUT_PERIOD(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_SHIFT_TOTAL_LEN_TH 8 +#define BIT_MASK_TOTAL_LEN_TH 0xfff +#define BIT_TOTAL_LEN_TH(x) \ + (((x) & BIT_MASK_TOTAL_LEN_TH) << BIT_SHIFT_TOTAL_LEN_TH) +#define BITS_TOTAL_LEN_TH (BIT_MASK_TOTAL_LEN_TH << BIT_SHIFT_TOTAL_LEN_TH) +#define BIT_CLEAR_TOTAL_LEN_TH(x) ((x) & (~BITS_TOTAL_LEN_TH)) +#define BIT_GET_TOTAL_LEN_TH(x) \ + (((x) >> BIT_SHIFT_TOTAL_LEN_TH) & BIT_MASK_TOTAL_LEN_TH) +#define BIT_SET_TOTAL_LEN_TH(x, v) \ + (BIT_CLEAR_TOTAL_LEN_TH(x) | BIT_TOTAL_LEN_TH(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_WEP_PRETX_EN BIT(7) -/* 2 REG_TXCMD_TIMEOUT_PERIOD (Offset 0x0576) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0 -#define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff -#define BIT_TXCMD_TIMEOUT_PERIOD(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) -#define BIT_GET_TXCMD_TIMEOUT_PERIOD(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_EN_NEW_EARLY BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ +#define BIT_PRE_TX_CMD BIT(6) -/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_SHIFT_NUM_SCL_EN 4 +#define BIT_MASK_NUM_SCL_EN 0x3 +#define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN) +#define BITS_NUM_SCL_EN (BIT_MASK_NUM_SCL_EN << BIT_SHIFT_NUM_SCL_EN) +#define BIT_CLEAR_NUM_SCL_EN(x) ((x) & (~BITS_NUM_SCL_EN)) +#define BIT_GET_NUM_SCL_EN(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN) +#define BIT_SET_NUM_SCL_EN(x, v) (BIT_CLEAR_NUM_SCL_EN(x) | BIT_NUM_SCL_EN(v)) -#define BIT_DIS_MARK_TSF_US BIT(7) -#define BIT_EN_TSFAUTO_SYNC BIT(6) +#define BIT_BK_EN BIT(3) +#define BIT_BE_EN BIT(2) +#define BIT_VI_EN BIT(1) +#define BIT_VO_EN BIT(0) -#endif +/* 2 REG_PKT_LIFE_TIME (Offset 0x04C0) */ +#define BIT_SHIFT_PKT_LIFTIME_BEBK 16 +#define BIT_MASK_PKT_LIFTIME_BEBK 0xffff +#define BIT_PKT_LIFTIME_BEBK(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK) +#define BITS_PKT_LIFTIME_BEBK \ + (BIT_MASK_PKT_LIFTIME_BEBK << BIT_SHIFT_PKT_LIFTIME_BEBK) +#define BIT_CLEAR_PKT_LIFTIME_BEBK(x) ((x) & (~BITS_PKT_LIFTIME_BEBK)) +#define BIT_GET_PKT_LIFTIME_BEBK(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK) +#define BIT_SET_PKT_LIFTIME_BEBK(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK(x) | BIT_PKT_LIFTIME_BEBK(v)) + +#define BIT_SHIFT_PKT_LIFTIME_VOVI 0 +#define BIT_MASK_PKT_LIFTIME_VOVI 0xffff +#define BIT_PKT_LIFTIME_VOVI(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI) +#define BITS_PKT_LIFTIME_VOVI \ + (BIT_MASK_PKT_LIFTIME_VOVI << BIT_SHIFT_PKT_LIFTIME_VOVI) +#define BIT_CLEAR_PKT_LIFTIME_VOVI(x) ((x) & (~BITS_PKT_LIFTIME_VOVI)) +#define BIT_GET_PKT_LIFTIME_VOVI(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI) +#define BIT_SET_PKT_LIFTIME_VOVI(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI(x) | BIT_PKT_LIFTIME_VOVI(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_STBC_SETTING (Offset 0x04C4) */ +#define BIT_SHIFT_CDEND_TXTIME_L 4 +#define BIT_MASK_CDEND_TXTIME_L 0xf +#define BIT_CDEND_TXTIME_L(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L) +#define BITS_CDEND_TXTIME_L \ + (BIT_MASK_CDEND_TXTIME_L << BIT_SHIFT_CDEND_TXTIME_L) +#define BIT_CLEAR_CDEND_TXTIME_L(x) ((x) & (~BITS_CDEND_TXTIME_L)) +#define BIT_GET_CDEND_TXTIME_L(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L) +#define BIT_SET_CDEND_TXTIME_L(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L(x) | BIT_CDEND_TXTIME_L(v)) + +#define BIT_SHIFT_NESS 2 +#define BIT_MASK_NESS 0x3 +#define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS) +#define BITS_NESS (BIT_MASK_NESS << BIT_SHIFT_NESS) +#define BIT_CLEAR_NESS(x) ((x) & (~BITS_NESS)) +#define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS) +#define BIT_SET_NESS(x, v) (BIT_CLEAR_NESS(x) | BIT_NESS(v)) + +#define BIT_SHIFT_STBC_CFEND 0 +#define BIT_MASK_STBC_CFEND 0x3 +#define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND) +#define BITS_STBC_CFEND (BIT_MASK_STBC_CFEND << BIT_SHIFT_STBC_CFEND) +#define BIT_CLEAR_STBC_CFEND(x) ((x) & (~BITS_STBC_CFEND)) +#define BIT_GET_STBC_CFEND(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND) +#define BIT_SET_STBC_CFEND(x, v) (BIT_CLEAR_STBC_CFEND(x) | BIT_STBC_CFEND(v)) -/* 2 REG_MISC_CTRL (Offset 0x0577) */ +/* 2 REG_STBC_SETTING2 (Offset 0x04C5) */ -#define BIT_DIS_TRX_CAL_BCN BIT(5) -#define BIT_DIS_TX_CAL_TBTT BIT(4) -#define BIT_EN_FREECNT BIT(3) -#define BIT_BCN_AGGRESSION BIT(2) +#define BIT_SHIFT_CDEND_TXTIME_H 0 +#define BIT_MASK_CDEND_TXTIME_H 0x1f +#define BIT_CDEND_TXTIME_H(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H) +#define BITS_CDEND_TXTIME_H \ + (BIT_MASK_CDEND_TXTIME_H << BIT_SHIFT_CDEND_TXTIME_H) +#define BIT_CLEAR_CDEND_TXTIME_H(x) ((x) & (~BITS_CDEND_TXTIME_H)) +#define BIT_GET_CDEND_TXTIME_H(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H) +#define BIT_SET_CDEND_TXTIME_H(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H(x) | BIT_CDEND_TXTIME_H(v)) -#define BIT_SHIFT_DIS_SECONDARY_CCA 0 -#define BIT_MASK_DIS_SECONDARY_CCA 0x3 -#define BIT_DIS_SECONDARY_CCA(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA) -#define BIT_GET_DIS_SECONDARY_CCA(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ -#define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6) -#define BIT_CLI1_DIS_TSF_UDT BIT(4) -#define BIT_CLI1_EN_BCN_FUNCTION BIT(3) +#define BIT_FORCE_RND_PRI BIT(6) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ -#define BIT_CLI1_EN_RXBCN_RPT BIT(2) +#define BIT_R_FORCE_RND_PRI BIT(6) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ -#define BIT_CLI1_EN_BCN_RPT BIT(2) +#define BIT_PTA_EDCCA_EN BIT(5) +#define BIT_PTA_WL_TX_EN BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ +#define BIT_R_USE_DATA_BW BIT(3) -/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +#endif -#define BIT_CLI1_ENP2P_CTWINDOW BIT(1) -#define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0) +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ -#define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6) -#define BIT_CLI2_DIS_TSF_UDT BIT(4) -#define BIT_CLI2_EN_BCN_FUNCTION BIT(3) +#define BIT_USE_DATA_BW BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ +#define BIT_TRI_PKT_INT_MODE1 BIT(2) +#define BIT_TRI_PKT_INT_MODE0 BIT(1) +#define BIT_ACQ_MODE_SEL BIT(0) -/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +/* 2 REG_SINGLE_AMPDU_CTRL (Offset 0x04C7) */ -#define BIT_CLI2_EN_RXBCN_RPT BIT(2) +#define BIT_EN_SINGLE_APMDU BIT(7) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_SINGLE_AMPDU_CTRL (Offset 0x04C7) */ +#define BIT_SHIFT_SNDTX_MAXTIME 0 +#define BIT_MASK_SNDTX_MAXTIME 0x7f +#define BIT_SNDTX_MAXTIME(x) \ + (((x) & BIT_MASK_SNDTX_MAXTIME) << BIT_SHIFT_SNDTX_MAXTIME) +#define BITS_SNDTX_MAXTIME (BIT_MASK_SNDTX_MAXTIME << BIT_SHIFT_SNDTX_MAXTIME) +#define BIT_CLEAR_SNDTX_MAXTIME(x) ((x) & (~BITS_SNDTX_MAXTIME)) +#define BIT_GET_SNDTX_MAXTIME(x) \ + (((x) >> BIT_SHIFT_SNDTX_MAXTIME) & BIT_MASK_SNDTX_MAXTIME) +#define BIT_SET_SNDTX_MAXTIME(x, v) \ + (BIT_CLEAR_SNDTX_MAXTIME(x) | BIT_SNDTX_MAXTIME(v)) -/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +/* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */ -#define BIT_CLI2_EN_BCN_RPT BIT(2) +#define BIT_SND_SIFS_TXDATA BIT(31) +#define BIT_TX_SND_MATCH_MACID BIT(30) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */ +#define BIT_SHIFT_RTS_MAX_AGG_NUM 24 +#define BIT_MASK_RTS_MAX_AGG_NUM 0x3f +#define BIT_RTS_MAX_AGG_NUM(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM) +#define BITS_RTS_MAX_AGG_NUM \ + (BIT_MASK_RTS_MAX_AGG_NUM << BIT_SHIFT_RTS_MAX_AGG_NUM) +#define BIT_CLEAR_RTS_MAX_AGG_NUM(x) ((x) & (~BITS_RTS_MAX_AGG_NUM)) +#define BIT_GET_RTS_MAX_AGG_NUM(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM) +#define BIT_SET_RTS_MAX_AGG_NUM(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM(x) | BIT_RTS_MAX_AGG_NUM(v)) + +#define BIT_SHIFT_MAX_AGG_NUM 16 +#define BIT_MASK_MAX_AGG_NUM 0x3f +#define BIT_MAX_AGG_NUM(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM) +#define BITS_MAX_AGG_NUM (BIT_MASK_MAX_AGG_NUM << BIT_SHIFT_MAX_AGG_NUM) +#define BIT_CLEAR_MAX_AGG_NUM(x) ((x) & (~BITS_MAX_AGG_NUM)) +#define BIT_GET_MAX_AGG_NUM(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM) +#define BIT_SET_MAX_AGG_NUM(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM(x) | BIT_MAX_AGG_NUM(v)) + +#define BIT_SHIFT_RTS_TXTIME_TH 8 +#define BIT_MASK_RTS_TXTIME_TH 0xff +#define BIT_RTS_TXTIME_TH(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH) +#define BITS_RTS_TXTIME_TH (BIT_MASK_RTS_TXTIME_TH << BIT_SHIFT_RTS_TXTIME_TH) +#define BIT_CLEAR_RTS_TXTIME_TH(x) ((x) & (~BITS_RTS_TXTIME_TH)) +#define BIT_GET_RTS_TXTIME_TH(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH) +#define BIT_SET_RTS_TXTIME_TH(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH(x) | BIT_RTS_TXTIME_TH(v)) + +#define BIT_SHIFT_RTS_LEN_TH 0 +#define BIT_MASK_RTS_LEN_TH 0xff +#define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH) +#define BITS_RTS_LEN_TH (BIT_MASK_RTS_LEN_TH << BIT_SHIFT_RTS_LEN_TH) +#define BIT_CLEAR_RTS_LEN_TH(x) ((x) & (~BITS_RTS_LEN_TH)) +#define BIT_GET_RTS_LEN_TH(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH) +#define BIT_SET_RTS_LEN_TH(x, v) (BIT_CLEAR_RTS_LEN_TH(x) | BIT_RTS_LEN_TH(v)) -/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +/* 2 REG_BAR_MODE_CTRL (Offset 0x04CC) */ -#define BIT_CLI2_ENP2P_CTWINDOW BIT(1) -#define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0) +#define BIT_SHIFT_BAR_RTY_LMT 16 +#define BIT_MASK_BAR_RTY_LMT 0x3 +#define BIT_BAR_RTY_LMT(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT) +#define BITS_BAR_RTY_LMT (BIT_MASK_BAR_RTY_LMT << BIT_SHIFT_BAR_RTY_LMT) +#define BIT_CLEAR_BAR_RTY_LMT(x) ((x) & (~BITS_BAR_RTY_LMT)) +#define BIT_GET_BAR_RTY_LMT(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT) +#define BIT_SET_BAR_RTY_LMT(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT(x) | BIT_BAR_RTY_LMT(v)) + +#define BIT_SHIFT_BAR_PKT_TXTIME_TH 8 +#define BIT_MASK_BAR_PKT_TXTIME_TH 0xff +#define BIT_BAR_PKT_TXTIME_TH(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH) +#define BITS_BAR_PKT_TXTIME_TH \ + (BIT_MASK_BAR_PKT_TXTIME_TH << BIT_SHIFT_BAR_PKT_TXTIME_TH) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH(x) ((x) & (~BITS_BAR_PKT_TXTIME_TH)) +#define BIT_GET_BAR_PKT_TXTIME_TH(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH) +#define BIT_SET_BAR_PKT_TXTIME_TH(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH(x) | BIT_BAR_PKT_TXTIME_TH(v)) + +#define BIT_BAR_EN_V1 BIT(6) + +#define BIT_SHIFT_BAR_PKTNUM_TH_V1 0 +#define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f +#define BIT_BAR_PKTNUM_TH_V1(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1) +#define BITS_BAR_PKTNUM_TH_V1 \ + (BIT_MASK_BAR_PKTNUM_TH_V1 << BIT_SHIFT_BAR_PKTNUM_TH_V1) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1(x) ((x) & (~BITS_BAR_PKTNUM_TH_V1)) +#define BIT_GET_BAR_PKTNUM_TH_V1(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1) +#define BIT_SET_BAR_PKTNUM_TH_V1(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1(x) | BIT_BAR_PKTNUM_TH_V1(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +/* 2 REG_RA_TRY_RATE_AGG_LMT (Offset 0x04CF) */ -#define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6) -#define BIT_CLI3_DIS_TSF_UDT BIT(4) -#define BIT_CLI3_EN_BCN_FUNCTION BIT(3) +#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0 +#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f +#define BIT_RA_TRY_RATE_AGG_LMT_V1(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) +#define BITS_RA_TRY_RATE_AGG_LMT_V1 \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x) | BIT_RA_TRY_RATE_AGG_LMT_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_MACID_SLEEP_CTRL (Offset 0x04D0) */ + +#define BIT_SHIFT_DEBUG_PROTOCOL 24 +#define BIT_MASK_DEBUG_PROTOCOL 0xff +#define BIT_DEBUG_PROTOCOL(x) \ + (((x) & BIT_MASK_DEBUG_PROTOCOL) << BIT_SHIFT_DEBUG_PROTOCOL) +#define BITS_DEBUG_PROTOCOL \ + (BIT_MASK_DEBUG_PROTOCOL << BIT_SHIFT_DEBUG_PROTOCOL) +#define BIT_CLEAR_DEBUG_PROTOCOL(x) ((x) & (~BITS_DEBUG_PROTOCOL)) +#define BIT_GET_DEBUG_PROTOCOL(x) \ + (((x) >> BIT_SHIFT_DEBUG_PROTOCOL) & BIT_MASK_DEBUG_PROTOCOL) +#define BIT_SET_DEBUG_PROTOCOL(x, v) \ + (BIT_CLEAR_DEBUG_PROTOCOL(x) | BIT_DEBUG_PROTOCOL(v)) + +#define BIT_SHIFT_BCNQ_PGBNDY_RSEL 16 +#define BIT_MASK_BCNQ_PGBNDY_RSEL 0x7 +#define BIT_BCNQ_PGBNDY_RSEL(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_RSEL) << BIT_SHIFT_BCNQ_PGBNDY_RSEL) +#define BITS_BCNQ_PGBNDY_RSEL \ + (BIT_MASK_BCNQ_PGBNDY_RSEL << BIT_SHIFT_BCNQ_PGBNDY_RSEL) +#define BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_RSEL)) +#define BIT_GET_BCNQ_PGBNDY_RSEL(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RSEL) & BIT_MASK_BCNQ_PGBNDY_RSEL) +#define BIT_SET_BCNQ_PGBNDY_RSEL(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) | BIT_BCNQ_PGBNDY_RSEL(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_MACID_SLEEP2 (Offset 0x04D0) */ +#define BIT_SHIFT_MACID95_64PKTSLEEP 0 +#define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL +#define BIT_MACID95_64PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP) +#define BITS_MACID95_64PKTSLEEP \ + (BIT_MASK_MACID95_64PKTSLEEP << BIT_SHIFT_MACID95_64PKTSLEEP) +#define BIT_CLEAR_MACID95_64PKTSLEEP(x) ((x) & (~BITS_MACID95_64PKTSLEEP)) +#define BIT_GET_MACID95_64PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP) +#define BIT_SET_MACID95_64PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID95_64PKTSLEEP(x) | BIT_MACID95_64PKTSLEEP(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +/* 2 REG_MACID_SLEEP_CTRL (Offset 0x04D0) */ -#define BIT_CLI3_EN_RXBCN_RPT BIT(2) +#define BIT_SHIFT_MACID_SLEEP_SEL 0 +#define BIT_MASK_MACID_SLEEP_SEL 0x7 +#define BIT_MACID_SLEEP_SEL(x) \ + (((x) & BIT_MASK_MACID_SLEEP_SEL) << BIT_SHIFT_MACID_SLEEP_SEL) +#define BITS_MACID_SLEEP_SEL \ + (BIT_MASK_MACID_SLEEP_SEL << BIT_SHIFT_MACID_SLEEP_SEL) +#define BIT_CLEAR_MACID_SLEEP_SEL(x) ((x) & (~BITS_MACID_SLEEP_SEL)) +#define BIT_GET_MACID_SLEEP_SEL(x) \ + (((x) >> BIT_SHIFT_MACID_SLEEP_SEL) & BIT_MASK_MACID_SLEEP_SEL) +#define BIT_SET_MACID_SLEEP_SEL(x, v) \ + (BIT_CLEAR_MACID_SLEEP_SEL(x) | BIT_MACID_SLEEP_SEL(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - - -/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +/* 2 REG_MACID_SLEEP (Offset 0x04D4) */ -#define BIT_CLI3_EN_BCN_RPT BIT(2) +#define BIT_SHIFT_MACID31_0_PKTSLEEP 0 +#define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL +#define BIT_MACID31_0_PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP) +#define BITS_MACID31_0_PKTSLEEP \ + (BIT_MASK_MACID31_0_PKTSLEEP << BIT_SHIFT_MACID31_0_PKTSLEEP) +#define BIT_CLEAR_MACID31_0_PKTSLEEP(x) ((x) & (~BITS_MACID31_0_PKTSLEEP)) +#define BIT_GET_MACID31_0_PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP) +#define BIT_SET_MACID31_0_PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID31_0_PKTSLEEP(x) | BIT_MACID31_0_PKTSLEEP(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MACID_SLEEP (Offset 0x04D4) */ +#define BIT_SHIFT_MACID31_0PKTSLEEP 0 +#define BIT_MASK_MACID31_0PKTSLEEP 0xffffffffL +#define BIT_MACID31_0PKTSLEEP(x) \ + (((x) & BIT_MASK_MACID31_0PKTSLEEP) << BIT_SHIFT_MACID31_0PKTSLEEP) +#define BITS_MACID31_0PKTSLEEP \ + (BIT_MASK_MACID31_0PKTSLEEP << BIT_SHIFT_MACID31_0PKTSLEEP) +#define BIT_CLEAR_MACID31_0PKTSLEEP(x) ((x) & (~BITS_MACID31_0PKTSLEEP)) +#define BIT_GET_MACID31_0PKTSLEEP(x) \ + (((x) >> BIT_SHIFT_MACID31_0PKTSLEEP) & BIT_MASK_MACID31_0PKTSLEEP) +#define BIT_SET_MACID31_0PKTSLEEP(x, v) \ + (BIT_CLEAR_MACID31_0PKTSLEEP(x) | BIT_MACID31_0PKTSLEEP(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_MACID_SLEEP_INFO (Offset 0x04D4) */ + +#define BIT_SHIFT_MACID_SLEEP_INFO 0 +#define BIT_MASK_MACID_SLEEP_INFO 0xffffffffL +#define BIT_MACID_SLEEP_INFO(x) \ + (((x) & BIT_MASK_MACID_SLEEP_INFO) << BIT_SHIFT_MACID_SLEEP_INFO) +#define BITS_MACID_SLEEP_INFO \ + (BIT_MASK_MACID_SLEEP_INFO << BIT_SHIFT_MACID_SLEEP_INFO) +#define BIT_CLEAR_MACID_SLEEP_INFO(x) ((x) & (~BITS_MACID_SLEEP_INFO)) +#define BIT_GET_MACID_SLEEP_INFO(x) \ + (((x) >> BIT_SHIFT_MACID_SLEEP_INFO) & BIT_MASK_MACID_SLEEP_INFO) +#define BIT_SET_MACID_SLEEP_INFO(x, v) \ + (BIT_CLEAR_MACID_SLEEP_INFO(x) | BIT_MACID_SLEEP_INFO(v)) + +#define BIT_SHIFT_PTCL_TOTAL_PG_V3 0 +#define BIT_MASK_PTCL_TOTAL_PG_V3 0x1fff +#define BIT_PTCL_TOTAL_PG_V3(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V3) << BIT_SHIFT_PTCL_TOTAL_PG_V3) +#define BITS_PTCL_TOTAL_PG_V3 \ + (BIT_MASK_PTCL_TOTAL_PG_V3 << BIT_SHIFT_PTCL_TOTAL_PG_V3) +#define BIT_CLEAR_PTCL_TOTAL_PG_V3(x) ((x) & (~BITS_PTCL_TOTAL_PG_V3)) +#define BIT_GET_PTCL_TOTAL_PG_V3(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V3) & BIT_MASK_PTCL_TOTAL_PG_V3) +#define BIT_SET_PTCL_TOTAL_PG_V3(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V3(x) | BIT_PTCL_TOTAL_PG_V3(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +/* 2 REG_HW_SEQ0 (Offset 0x04D8) */ -#define BIT_CLI3_ENP2P_CTWINDOW BIT(1) -#define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0) +#define BIT_SHIFT_HW_SSN_SEQ0 0 +#define BIT_MASK_HW_SSN_SEQ0 0xfff +#define BIT_HW_SSN_SEQ0(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0) +#define BITS_HW_SSN_SEQ0 (BIT_MASK_HW_SSN_SEQ0 << BIT_SHIFT_HW_SSN_SEQ0) +#define BIT_CLEAR_HW_SSN_SEQ0(x) ((x) & (~BITS_HW_SSN_SEQ0)) +#define BIT_GET_HW_SSN_SEQ0(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0) +#define BIT_SET_HW_SSN_SEQ0(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0(x) | BIT_HW_SSN_SEQ0(v)) -#endif +/* 2 REG_HW_SEQ1 (Offset 0x04DA) */ +#define BIT_SHIFT_HW_SSN_SEQ1 0 +#define BIT_MASK_HW_SSN_SEQ1 0xfff +#define BIT_HW_SSN_SEQ1(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1) +#define BITS_HW_SSN_SEQ1 (BIT_MASK_HW_SSN_SEQ1 << BIT_SHIFT_HW_SSN_SEQ1) +#define BIT_CLEAR_HW_SSN_SEQ1(x) ((x) & (~BITS_HW_SSN_SEQ1)) +#define BIT_GET_HW_SSN_SEQ1(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1) +#define BIT_SET_HW_SSN_SEQ1(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1(x) | BIT_HW_SSN_SEQ1(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HW_SEQ2 (Offset 0x04DC) */ +#define BIT_SHIFT_HW_SSN_SEQ2 0 +#define BIT_MASK_HW_SSN_SEQ2 0xfff +#define BIT_HW_SSN_SEQ2(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2) +#define BITS_HW_SSN_SEQ2 (BIT_MASK_HW_SSN_SEQ2 << BIT_SHIFT_HW_SSN_SEQ2) +#define BIT_CLEAR_HW_SSN_SEQ2(x) ((x) & (~BITS_HW_SSN_SEQ2)) +#define BIT_GET_HW_SSN_SEQ2(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2) +#define BIT_SET_HW_SSN_SEQ2(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2(x) | BIT_HW_SSN_SEQ2(v)) -/* 2 REG_EXTEND_CTRL (Offset 0x057B) */ +#endif -#define BIT_EN_TSFBIT32_RST_P2P2 BIT(5) -#define BIT_EN_TSFBIT32_RST_P2P1 BIT(4) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_PORT_SEL 0 -#define BIT_MASK_PORT_SEL 0x7 -#define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL) -#define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL) +/* 2 REG_HW_SEQ3 (Offset 0x04DE) */ +#define BIT_SHIFT_CSI_HWSSN_SEL 12 +#define BIT_MASK_CSI_HWSSN_SEL 0x3 +#define BIT_CSI_HWSSN_SEL(x) \ + (((x) & BIT_MASK_CSI_HWSSN_SEL) << BIT_SHIFT_CSI_HWSSN_SEL) +#define BITS_CSI_HWSSN_SEL (BIT_MASK_CSI_HWSSN_SEL << BIT_SHIFT_CSI_HWSSN_SEL) +#define BIT_CLEAR_CSI_HWSSN_SEL(x) ((x) & (~BITS_CSI_HWSSN_SEL)) +#define BIT_GET_CSI_HWSSN_SEL(x) \ + (((x) >> BIT_SHIFT_CSI_HWSSN_SEL) & BIT_MASK_CSI_HWSSN_SEL) +#define BIT_SET_CSI_HWSSN_SEL(x, v) \ + (BIT_CLEAR_CSI_HWSSN_SEL(x) | BIT_CSI_HWSSN_SEL(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HW_SEQ3 (Offset 0x04DE) */ +#define BIT_SHIFT_CSI_HWSEQ_SEL 12 +#define BIT_MASK_CSI_HWSEQ_SEL 0x3 +#define BIT_CSI_HWSEQ_SEL(x) \ + (((x) & BIT_MASK_CSI_HWSEQ_SEL) << BIT_SHIFT_CSI_HWSEQ_SEL) +#define BITS_CSI_HWSEQ_SEL (BIT_MASK_CSI_HWSEQ_SEL << BIT_SHIFT_CSI_HWSEQ_SEL) +#define BIT_CLEAR_CSI_HWSEQ_SEL(x) ((x) & (~BITS_CSI_HWSEQ_SEL)) +#define BIT_GET_CSI_HWSEQ_SEL(x) \ + (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL) & BIT_MASK_CSI_HWSEQ_SEL) +#define BIT_SET_CSI_HWSEQ_SEL(x, v) \ + (BIT_CLEAR_CSI_HWSEQ_SEL(x) | BIT_CSI_HWSEQ_SEL(v)) -/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ +#endif -#define BIT_P2P1_SPEC_POWER_STATE BIT(7) -#define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6) -#define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5) -#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4) -#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3) -#define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2) -#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1) -#define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_P2PPS1_STATE (Offset 0x057D) */ +/* 2 REG_HW_SEQ3 (Offset 0x04DE) */ -#define BIT_P2P1_POWER_STATE BIT(7) -#define BIT_P2P1_CTWINDOW_ON BIT(6) -#define BIT_P2P1_BEACON_AREA_ON BIT(5) -#define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4) -#define BIT_P2P1_NOA1_OFF_PERIOD BIT(3) -#define BIT_P2P1_FORCE_DOZE1 BIT(2) -#define BIT_P2P1_NOA0_OFF_PERIOD BIT(1) -#define BIT_P2P1_FORCE_DOZE0 BIT(0) +#define BIT_SHIFT_HW_SSN_SEQ3 0 +#define BIT_MASK_HW_SSN_SEQ3 0xfff +#define BIT_HW_SSN_SEQ3(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3) +#define BITS_HW_SSN_SEQ3 (BIT_MASK_HW_SSN_SEQ3 << BIT_SHIFT_HW_SSN_SEQ3) +#define BIT_CLEAR_HW_SSN_SEQ3(x) ((x) & (~BITS_HW_SSN_SEQ3)) +#define BIT_GET_HW_SSN_SEQ3(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3) +#define BIT_SET_HW_SSN_SEQ3(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3(x) | BIT_HW_SSN_SEQ3(v)) -/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ +#endif -#define BIT_P2P2_SPEC_POWER_STATE BIT(7) -#define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6) -#define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5) -#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4) -#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3) -#define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2) -#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1) -#define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_P2PPS2_STATE (Offset 0x057F) */ +/* 2 REG_CSI_SEQ (Offset 0x04DE) */ -#define BIT_P2P2_POWER_STATE BIT(7) -#define BIT_P2P2_CTWINDOW_ON BIT(6) -#define BIT_P2P2_BEACON_AREA_ON BIT(5) -#define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4) -#define BIT_P2P2_NOA1_OFF_PERIOD BIT(3) -#define BIT_P2P2_FORCE_DOZE1 BIT(2) -#define BIT_P2P2_NOA0_OFF_PERIOD BIT(1) -#define BIT_P2P2_FORCE_DOZE0 BIT(0) +#define BIT_SHIFT_HW_CSI_SEQ 0 +#define BIT_MASK_HW_CSI_SEQ 0xfff +#define BIT_HW_CSI_SEQ(x) (((x) & BIT_MASK_HW_CSI_SEQ) << BIT_SHIFT_HW_CSI_SEQ) +#define BITS_HW_CSI_SEQ (BIT_MASK_HW_CSI_SEQ << BIT_SHIFT_HW_CSI_SEQ) +#define BIT_CLEAR_HW_CSI_SEQ(x) ((x) & (~BITS_HW_CSI_SEQ)) +#define BIT_GET_HW_CSI_SEQ(x) \ + (((x) >> BIT_SHIFT_HW_CSI_SEQ) & BIT_MASK_HW_CSI_SEQ) +#define BIT_SET_HW_CSI_SEQ(x, v) (BIT_CLEAR_HW_CSI_SEQ(x) | BIT_HW_CSI_SEQ(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ +#define BIT_SHIFT_PTCL_TOTAL_PG_V1 2 +#define BIT_MASK_PTCL_TOTAL_PG_V1 0x1fff +#define BIT_PTCL_TOTAL_PG_V1(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V1) << BIT_SHIFT_PTCL_TOTAL_PG_V1) +#define BITS_PTCL_TOTAL_PG_V1 \ + (BIT_MASK_PTCL_TOTAL_PG_V1 << BIT_SHIFT_PTCL_TOTAL_PG_V1) +#define BIT_CLEAR_PTCL_TOTAL_PG_V1(x) ((x) & (~BITS_PTCL_TOTAL_PG_V1)) +#define BIT_GET_PTCL_TOTAL_PG_V1(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1) & BIT_MASK_PTCL_TOTAL_PG_V1) +#define BIT_SET_PTCL_TOTAL_PG_V1(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V1(x) | BIT_PTCL_TOTAL_PG_V1(v)) -/* 2 REG_PS_TIMER (Offset 0x0580) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PSTIMER_INT 5 -#define BIT_MASK_PSTIMER_INT 0x7ffffff -#define BIT_PSTIMER_INT(x) (((x) & BIT_MASK_PSTIMER_INT) << BIT_SHIFT_PSTIMER_INT) -#define BIT_GET_PSTIMER_INT(x) (((x) >> BIT_SHIFT_PSTIMER_INT) & BIT_MASK_PSTIMER_INT) +/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ +#define BIT_SHIFT_PTCL_TOTAL_PG_V2 2 +#define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff +#define BIT_PTCL_TOTAL_PG_V2(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2) +#define BITS_PTCL_TOTAL_PG_V2 \ + (BIT_MASK_PTCL_TOTAL_PG_V2 << BIT_SHIFT_PTCL_TOTAL_PG_V2) +#define BIT_CLEAR_PTCL_TOTAL_PG_V2(x) ((x) & (~BITS_PTCL_TOTAL_PG_V2)) +#define BIT_GET_PTCL_TOTAL_PG_V2(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2) +#define BIT_SET_PTCL_TOTAL_PG_V2(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V2(x) | BIT_PTCL_TOTAL_PG_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_NULL_PKT_STATUS (Offset 0x04E0) */ +#define BIT_TX_NULL_1 BIT(1) +#define BIT_TX_NULL_0 BIT(0) -/* 2 REG_PS_TIMER0 (Offset 0x0580) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PSTIMER0_INT 5 -#define BIT_MASK_PSTIMER0_INT 0x7ffffff -#define BIT_PSTIMER0_INT(x) (((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT) -#define BIT_GET_PSTIMER0_INT(x) (((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_MUARB_SEARCH_ERR BIT(14) +#define BIT_MU_BFEN_ERR BIT(12) +#define BIT_NDPA_DROPNULL_ERR BIT(11) +#define BIT_NDPA_DROPPKT_ERR BIT(10) +#define BIT_PTCL_PKYIN_ERR BIT(9) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_SHIFT_PTCL_TOTAL_PG_V4 8 +#define BIT_MASK_PTCL_TOTAL_PG_V4 0xff +#define BIT_PTCL_TOTAL_PG_V4(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V4) << BIT_SHIFT_PTCL_TOTAL_PG_V4) +#define BITS_PTCL_TOTAL_PG_V4 \ + (BIT_MASK_PTCL_TOTAL_PG_V4 << BIT_SHIFT_PTCL_TOTAL_PG_V4) +#define BIT_CLEAR_PTCL_TOTAL_PG_V4(x) ((x) & (~BITS_PTCL_TOTAL_PG_V4)) +#define BIT_GET_PTCL_TOTAL_PG_V4(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V4) & BIT_MASK_PTCL_TOTAL_PG_V4) +#define BIT_SET_PTCL_TOTAL_PG_V4(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V4(x) | BIT_PTCL_TOTAL_PG_V4(v)) -/* 2 REG_PS_TIMER (Offset 0x0580) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PSTIMER_INT_V1 5 -#define BIT_MASK_PSTIMER_INT_V1 0x7ffffff -#define BIT_PSTIMER_INT_V1(x) (((x) & BIT_MASK_PSTIMER_INT_V1) << BIT_SHIFT_PSTIMER_INT_V1) -#define BIT_GET_PSTIMER_INT_V1(x) (((x) >> BIT_SHIFT_PSTIMER_INT_V1) & BIT_MASK_PSTIMER_INT_V1) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_PTCL_QSELCNL_ERR BIT(8) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_PTCL_TOTAL_PG_8 BIT(7) -/* 2 REG_TIMER0 (Offset 0x0584) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TIMER0_INT 5 -#define BIT_MASK_TIMER0_INT 0x7ffffff -#define BIT_TIMER0_INT(x) (((x) & BIT_MASK_TIMER0_INT) << BIT_SHIFT_TIMER0_INT) -#define BIT_GET_TIMER0_INT(x) (((x) >> BIT_SHIFT_TIMER0_INT) & BIT_MASK_TIMER0_INT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_PTCL_RATE_TABLE_INVALID BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#define BIT_P2P_OFF_DISTX_EN BIT(6) -/* 2 REG_PS_TIMER1 (Offset 0x0584) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_PSTIMER1_INT 5 -#define BIT_MASK_PSTIMER1_INT 0x7ffffff -#define BIT_PSTIMER1_INT(x) (((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT) -#define BIT_GET_PSTIMER1_INT(x) (((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_PTCL_RATE_TABLE_INVALID_V1 BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_FTM_T2R_ERROR BIT(6) -/* 2 REG_TIMER1 (Offset 0x0588) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TIMER1_INT 5 -#define BIT_MASK_TIMER1_INT 0x7ffffff -#define BIT_TIMER1_INT(x) (((x) & BIT_MASK_TIMER1_INT) << BIT_SHIFT_TIMER1_INT) -#define BIT_GET_TIMER1_INT(x) (((x) >> BIT_SHIFT_TIMER1_INT) & BIT_MASK_TIMER1_INT) +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#define BIT_PTCL_ERR0 BIT(5) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_TXTIMEOUT_ERR BIT(5) -/* 2 REG_PS_TIMER2 (Offset 0x0588) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PSTIMER2_INT 5 -#define BIT_MASK_PSTIMER2_INT 0x7ffffff -#define BIT_PSTIMER2_INT(x) (((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT) -#define BIT_GET_PSTIMER2_INT(x) (((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT) +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#define BIT_PTCL_ERR1 BIT(4) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_NULLPAGE_ERR BIT(4) -/* 2 REG_TBTT_CTN_AREA (Offset 0x058C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TBTT_CTN_AREA 0 -#define BIT_MASK_TBTT_CTN_AREA 0xff -#define BIT_TBTT_CTN_AREA(x) (((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA) -#define BIT_GET_TBTT_CTN_AREA(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA) +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#define BIT_PTCL_ERR2 BIT(3) -/* 2 REG_FORCE_BCN_IFS (Offset 0x058E) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_FORCE_BCN_IFS 0 -#define BIT_MASK_FORCE_BCN_IFS 0xff -#define BIT_FORCE_BCN_IFS(x) (((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS) -#define BIT_GET_FORCE_BCN_IFS(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_CONTENTION_ERR BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_TXOP_MIN (Offset 0x0590) */ +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ -#define BIT_NAV_BLK_HGQ BIT(15) -#define BIT_NAV_BLK_MGQ BIT(14) +#define BIT_PTCL_ERR3 BIT(2) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_HEADNULL_ERR BIT(2) -/* 2 REG_TXOP_MIN (Offset 0x0590) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_TXOP_MIN 0 -#define BIT_MASK_TXOP_MIN 0x3fff -#define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN) -#define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN) +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ +#define BIT_PTCL_ERR4 BIT(1) -/* 2 REG_PRE_BKF_TIME (Offset 0x0592) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PRE_BKF_TIME 0 -#define BIT_MASK_PRE_BKF_TIME 0xff -#define BIT_PRE_BKF_TIME(x) (((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME) -#define BIT_GET_PRE_BKF_TIME(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME) +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ +#define BIT_OVERFLOW_ERR BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - - -/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ +/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ -#define BIT_TXFAIL_BREACK_TXOP_EN BIT(3) +#define BIT_PTCL_ERR5 BIT(0) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */ -/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ - -#define BIT_DTIM_BYPASS BIT(2) -#define BIT_RTS_NAV_TXOP BIT(1) -#define BIT_NOT_CROSS_TXOP BIT(0) +#define BIT_QUEUE_INDEX_ERR BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ -/* 2 REG_TBTT_INT_SHIFT_CLI0 (Offset 0x0594) */ +#define BIT_CLI3_TX_NULL_1 BIT(7) +#define BIT_CLI3_TX_NULL_0 BIT(6) +#define BIT_CLI2_TX_NULL_1 BIT(5) +#define BIT_CLI2_TX_NULL_0 BIT(4) +#define BIT_CLI1_TX_NULL_1 BIT(3) +#define BIT_CLI1_TX_NULL_0 BIT(2) +#define BIT_CLI0_TX_NULL_1 BIT(1) -#define BIT_TBTT_INT_SHIFT_DIR_CLI0 BIT(7) +#endif -#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0 0 -#define BIT_MASK_TBTT_INT_SHIFT_CLI0 0x7f -#define BIT_TBTT_INT_SHIFT_CLI0(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0) -#define BIT_GET_TBTT_INT_SHIFT_CLI0(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0) & BIT_MASK_TBTT_INT_SHIFT_CLI0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PTCL_PKT_NUM (Offset 0x04E3) */ -/* 2 REG_TBTT_INT_SHIFT_CLI1 (Offset 0x0595) */ +#define BIT_SHIFT_PTCL_TOTAL_PG 0 +#define BIT_MASK_PTCL_TOTAL_PG 0xff +#define BIT_PTCL_TOTAL_PG(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG) << BIT_SHIFT_PTCL_TOTAL_PG) +#define BITS_PTCL_TOTAL_PG (BIT_MASK_PTCL_TOTAL_PG << BIT_SHIFT_PTCL_TOTAL_PG) +#define BIT_CLEAR_PTCL_TOTAL_PG(x) ((x) & (~BITS_PTCL_TOTAL_PG)) +#define BIT_GET_PTCL_TOTAL_PG(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG) & BIT_MASK_PTCL_TOTAL_PG) +#define BIT_SET_PTCL_TOTAL_PG(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG(x) | BIT_PTCL_TOTAL_PG(v)) -#define BIT_TBTT_INT_SHIFT_DIR_CLI1 BIT(7) +#endif -#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1 0 -#define BIT_MASK_TBTT_INT_SHIFT_CLI1 0x7f -#define BIT_TBTT_INT_SHIFT_CLI1(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1) -#define BIT_GET_TBTT_INT_SHIFT_CLI1(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1) & BIT_MASK_TBTT_INT_SHIFT_CLI1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ -/* 2 REG_TBTT_INT_SHIFT_CLI2 (Offset 0x0596) */ +#define BIT_CLI0_TX_NULL_0 BIT(0) -#define BIT_TBTT_INT_SHIFT_DIR_CLI2 BIT(7) +#endif -#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2 0 -#define BIT_MASK_TBTT_INT_SHIFT_CLI2 0x7f -#define BIT_TBTT_INT_SHIFT_CLI2(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2) -#define BIT_GET_TBTT_INT_SHIFT_CLI2(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2) & BIT_MASK_TBTT_INT_SHIFT_CLI2) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_TRXRPT_MISS_CNT (Offset 0x04E3) */ -/* 2 REG_TBTT_INT_SHIFT_CLI3 (Offset 0x0597) */ +#define BIT_SHIFT_TRXRPT_MISS_CNT 0 +#define BIT_MASK_TRXRPT_MISS_CNT 0x7 +#define BIT_TRXRPT_MISS_CNT(x) \ + (((x) & BIT_MASK_TRXRPT_MISS_CNT) << BIT_SHIFT_TRXRPT_MISS_CNT) +#define BITS_TRXRPT_MISS_CNT \ + (BIT_MASK_TRXRPT_MISS_CNT << BIT_SHIFT_TRXRPT_MISS_CNT) +#define BIT_CLEAR_TRXRPT_MISS_CNT(x) ((x) & (~BITS_TRXRPT_MISS_CNT)) +#define BIT_GET_TRXRPT_MISS_CNT(x) \ + (((x) >> BIT_SHIFT_TRXRPT_MISS_CNT) & BIT_MASK_TRXRPT_MISS_CNT) +#define BIT_SET_TRXRPT_MISS_CNT(x, v) \ + (BIT_CLEAR_TRXRPT_MISS_CNT(x) | BIT_TRXRPT_MISS_CNT(v)) -#define BIT_TBTT_INT_SHIFT_DIR_CLI3 BIT(7) +#endif -#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3 0 -#define BIT_MASK_TBTT_INT_SHIFT_CLI3 0x7f -#define BIT_TBTT_INT_SHIFT_CLI3(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3) -#define BIT_GET_TBTT_INT_SHIFT_CLI3(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3) & BIT_MASK_TBTT_INT_SHIFT_CLI3) +#if (HALMAC_8198F_SUPPORT) +/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ -/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ +#define BIT_MAX_PRETX_AGGR_EN BIT(19) -#define BIT_EN_TBTT_RTY BIT(1) -#define BIT_TBTT_INT_SHIFT_ENABLE BIT(0) +#define BIT_SHIFT_MAX_PRETX_AGGR_TIME 8 +#define BIT_MASK_MAX_PRETX_AGGR_TIME 0x7ff +#define BIT_MAX_PRETX_AGGR_TIME(x) \ + (((x) & BIT_MASK_MAX_PRETX_AGGR_TIME) << BIT_SHIFT_MAX_PRETX_AGGR_TIME) +#define BITS_MAX_PRETX_AGGR_TIME \ + (BIT_MASK_MAX_PRETX_AGGR_TIME << BIT_SHIFT_MAX_PRETX_AGGR_TIME) +#define BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) ((x) & (~BITS_MAX_PRETX_AGGR_TIME)) +#define BIT_GET_MAX_PRETX_AGGR_TIME(x) \ + (((x) >> BIT_SHIFT_MAX_PRETX_AGGR_TIME) & BIT_MASK_MAX_PRETX_AGGR_TIME) +#define BIT_SET_MAX_PRETX_AGGR_TIME(x, v) \ + (BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) | BIT_MAX_PRETX_AGGR_TIME(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NULL_PKT_STATUS_V2 (Offset 0x04E4) */ +#define BIT_HIQ_DROP BIT(7) -/* 2 REG_ATIMWND2 (Offset 0x05A0) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_ATIMWND2 0 -#define BIT_MASK_ATIMWND2 0xff -#define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2) -#define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2) +/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ +#define BIT_HGQ_DEL_EN BIT(7) -/* 2 REG_ATIMWND3 (Offset 0x05A1) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_ATIMWND3 0 -#define BIT_MASK_ATIMWND3 0xff -#define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3) -#define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3) +/* 2 REG_NULL_PKT_STATUS_V2 (Offset 0x04E4) */ +#define BIT_MGQ_DROP BIT(6) -/* 2 REG_ATIMWND4 (Offset 0x05A2) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_ATIMWND4 0 -#define BIT_MASK_ATIMWND4 0xff -#define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4) -#define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4) +/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ +#define BIT_MGQ_DEL_EN BIT(6) -/* 2 REG_ATIMWND5 (Offset 0x05A3) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_ATIMWND5 0 -#define BIT_MASK_ATIMWND5 0xff -#define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5) -#define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5) +/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ +#define BIT_VIDEO_JUST_DROP BIT(1) -/* 2 REG_ATIMWND6 (Offset 0x05A4) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_ATIMWND6 0 -#define BIT_MASK_ATIMWND6 0xff -#define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6) -#define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6) +/* 2 REG_NULL_PKT_STATUS_V2 (Offset 0x04E4) */ +#define BIT_TX_NULL_1_V1 BIT(1) -/* 2 REG_ATIMWND7 (Offset 0x05A5) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_ATIMWND7 0 -#define BIT_MASK_ATIMWND7 0xff -#define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7) -#define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7) +/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ +#define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0) -/* 2 REG_ATIMUGT (Offset 0x05A6) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_ATIM_URGENT 0 -#define BIT_MASK_ATIM_URGENT 0xff -#define BIT_ATIM_URGENT(x) (((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT) -#define BIT_GET_ATIM_URGENT(x) (((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT) +/* 2 REG_NULL_PKT_STATUS_V2 (Offset 0x04E4) */ +#define BIT_TX_NULL_0_V1 BIT(0) -/* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */ +#endif -#define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7) -#define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6) -#define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5) -#define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4) -#define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3) -#define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2) -#define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1) -#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0) +#if (HALMAC_8812F_SUPPORT) -/* 2 REG_DTIM_COUNTER_ROOT (Offset 0x05A8) */ +/* 2 REG_PRECNT_CTRL (Offset 0x04E5) */ +#define BIT_SHIFT_COLLISION_DETECT_TIME 12 +#define BIT_MASK_COLLISION_DETECT_TIME 0xf +#define BIT_COLLISION_DETECT_TIME(x) \ + (((x) & BIT_MASK_COLLISION_DETECT_TIME) \ + << BIT_SHIFT_COLLISION_DETECT_TIME) +#define BITS_COLLISION_DETECT_TIME \ + (BIT_MASK_COLLISION_DETECT_TIME << BIT_SHIFT_COLLISION_DETECT_TIME) +#define BIT_CLEAR_COLLISION_DETECT_TIME(x) ((x) & (~BITS_COLLISION_DETECT_TIME)) +#define BIT_GET_COLLISION_DETECT_TIME(x) \ + (((x) >> BIT_SHIFT_COLLISION_DETECT_TIME) & \ + BIT_MASK_COLLISION_DETECT_TIME) +#define BIT_SET_COLLISION_DETECT_TIME(x, v) \ + (BIT_CLEAR_COLLISION_DETECT_TIME(x) | BIT_COLLISION_DETECT_TIME(v)) -#define BIT_SHIFT_DTIM_COUNT_ROOT 0 -#define BIT_MASK_DTIM_COUNT_ROOT 0xff -#define BIT_DTIM_COUNT_ROOT(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT) -#define BIT_GET_DTIM_COUNT_ROOT(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP1 (Offset 0x05A9) */ +/* 2 REG_PRECNT_CTRL (Offset 0x04E5) */ +#define BIT_EN_PRECNT BIT(11) -#define BIT_SHIFT_DTIM_COUNT_VAP1 0 -#define BIT_MASK_DTIM_COUNT_VAP1 0xff -#define BIT_DTIM_COUNT_VAP1(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1) -#define BIT_GET_DTIM_COUNT_VAP1(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1) +#define BIT_SHIFT_PRECNT_TH 0 +#define BIT_MASK_PRECNT_TH 0x7ff +#define BIT_PRECNT_TH(x) (((x) & BIT_MASK_PRECNT_TH) << BIT_SHIFT_PRECNT_TH) +#define BITS_PRECNT_TH (BIT_MASK_PRECNT_TH << BIT_SHIFT_PRECNT_TH) +#define BIT_CLEAR_PRECNT_TH(x) ((x) & (~BITS_PRECNT_TH)) +#define BIT_GET_PRECNT_TH(x) (((x) >> BIT_SHIFT_PRECNT_TH) & BIT_MASK_PRECNT_TH) +#define BIT_SET_PRECNT_TH(x, v) (BIT_CLEAR_PRECNT_TH(x) | BIT_PRECNT_TH(v)) +#endif -/* 2 REG_DTIM_COUNTER_VAP2 (Offset 0x05AA) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_NULL_PKT_STATUS_EXTEND_V1 (Offset 0x04E7) */ -#define BIT_SHIFT_DTIM_COUNT_VAP2 0 -#define BIT_MASK_DTIM_COUNT_VAP2 0xff -#define BIT_DTIM_COUNT_VAP2(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2) -#define BIT_GET_DTIM_COUNT_VAP2(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2) +#define BIT_CLI3_TX_NULL_1_V1 BIT(7) +#define BIT_CLI3_TX_NULL_0_V1 BIT(6) +#define BIT_CLI2_TX_NULL_1_V1 BIT(5) +#define BIT_CLI2_TX_NULL_0_V1 BIT(4) +#define BIT_CLI1_TX_NULL_1_V1 BIT(3) +#define BIT_CLI1_TX_NULL_0_V1 BIT(2) +#define BIT_CLI0_TX_NULL_1_V1 BIT(1) +#define BIT_CLI0_TX_NULL_0_V1 BIT(0) +#endif -/* 2 REG_DTIM_COUNTER_VAP3 (Offset 0x05AB) */ +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_BT_POLLUTE_PKT_CNT (Offset 0x04E8) */ +#define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0 +#define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff +#define BIT_BT_POLLUTE_PKT_CNT(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT) +#define BITS_BT_POLLUTE_PKT_CNT \ + (BIT_MASK_BT_POLLUTE_PKT_CNT << BIT_SHIFT_BT_POLLUTE_PKT_CNT) +#define BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) ((x) & (~BITS_BT_POLLUTE_PKT_CNT)) +#define BIT_GET_BT_POLLUTE_PKT_CNT(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT) +#define BIT_SET_BT_POLLUTE_PKT_CNT(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) | BIT_BT_POLLUTE_PKT_CNT(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP3 0 -#define BIT_MASK_DTIM_COUNT_VAP3 0xff -#define BIT_DTIM_COUNT_VAP3(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3) -#define BIT_GET_DTIM_COUNT_VAP3(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP4 (Offset 0x05AC) */ +/* 2 REG_DROP_NUM (Offset 0x04EC) */ +#define BIT_SHIFT_DROP_PKT_NUM 0 +#define BIT_MASK_DROP_PKT_NUM 0xffff +#define BIT_DROP_PKT_NUM(x) \ + (((x) & BIT_MASK_DROP_PKT_NUM) << BIT_SHIFT_DROP_PKT_NUM) +#define BITS_DROP_PKT_NUM (BIT_MASK_DROP_PKT_NUM << BIT_SHIFT_DROP_PKT_NUM) +#define BIT_CLEAR_DROP_PKT_NUM(x) ((x) & (~BITS_DROP_PKT_NUM)) +#define BIT_GET_DROP_PKT_NUM(x) \ + (((x) >> BIT_SHIFT_DROP_PKT_NUM) & BIT_MASK_DROP_PKT_NUM) +#define BIT_SET_DROP_PKT_NUM(x, v) \ + (BIT_CLEAR_DROP_PKT_NUM(x) | BIT_DROP_PKT_NUM(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP4 0 -#define BIT_MASK_DTIM_COUNT_VAP4 0xff -#define BIT_DTIM_COUNT_VAP4(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4) -#define BIT_GET_DTIM_COUNT_VAP4(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP5 (Offset 0x05AD) */ +/* 2 REG_PTCL_DBG_V1 (Offset 0x04EC) */ +#define BIT_SHIFT_PTCL_DBG 0 +#define BIT_MASK_PTCL_DBG 0xffffffffL +#define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG) +#define BITS_PTCL_DBG (BIT_MASK_PTCL_DBG << BIT_SHIFT_PTCL_DBG) +#define BIT_CLEAR_PTCL_DBG(x) ((x) & (~BITS_PTCL_DBG)) +#define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG) +#define BIT_SET_PTCL_DBG(x, v) (BIT_CLEAR_PTCL_DBG(x) | BIT_PTCL_DBG(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP5 0 -#define BIT_MASK_DTIM_COUNT_VAP5 0xff -#define BIT_DTIM_COUNT_VAP5(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5) -#define BIT_GET_DTIM_COUNT_VAP5(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP6 (Offset 0x05AE) */ +/* 2 REG_PTCL_TX_RPT (Offset 0x04F0) */ +#define BIT_SHIFT_AC_TX_RPT_INFO 0 +#define BIT_MASK_AC_TX_RPT_INFO 0xffffffffffffffffL +#define BIT_AC_TX_RPT_INFO(x) \ + (((x) & BIT_MASK_AC_TX_RPT_INFO) << BIT_SHIFT_AC_TX_RPT_INFO) +#define BITS_AC_TX_RPT_INFO \ + (BIT_MASK_AC_TX_RPT_INFO << BIT_SHIFT_AC_TX_RPT_INFO) +#define BIT_CLEAR_AC_TX_RPT_INFO(x) ((x) & (~BITS_AC_TX_RPT_INFO)) +#define BIT_GET_AC_TX_RPT_INFO(x) \ + (((x) >> BIT_SHIFT_AC_TX_RPT_INFO) & BIT_MASK_AC_TX_RPT_INFO) +#define BIT_SET_AC_TX_RPT_INFO(x, v) \ + (BIT_CLEAR_AC_TX_RPT_INFO(x) | BIT_AC_TX_RPT_INFO(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP6 0 -#define BIT_MASK_DTIM_COUNT_VAP6 0xff -#define BIT_DTIM_COUNT_VAP6(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6) -#define BIT_GET_DTIM_COUNT_VAP6(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_DTIM_COUNTER_VAP7 (Offset 0x05AF) */ +/* 2 REG_TX_RPT_INFO_L32 (Offset 0x04F0) */ +#define BIT_SHIFT_AC_TX_RPT_INFO_L32 0 +#define BIT_MASK_AC_TX_RPT_INFO_L32 0xffffffffL +#define BIT_AC_TX_RPT_INFO_L32(x) \ + (((x) & BIT_MASK_AC_TX_RPT_INFO_L32) << BIT_SHIFT_AC_TX_RPT_INFO_L32) +#define BITS_AC_TX_RPT_INFO_L32 \ + (BIT_MASK_AC_TX_RPT_INFO_L32 << BIT_SHIFT_AC_TX_RPT_INFO_L32) +#define BIT_CLEAR_AC_TX_RPT_INFO_L32(x) ((x) & (~BITS_AC_TX_RPT_INFO_L32)) +#define BIT_GET_AC_TX_RPT_INFO_L32(x) \ + (((x) >> BIT_SHIFT_AC_TX_RPT_INFO_L32) & BIT_MASK_AC_TX_RPT_INFO_L32) +#define BIT_SET_AC_TX_RPT_INFO_L32(x, v) \ + (BIT_CLEAR_AC_TX_RPT_INFO_L32(x) | BIT_AC_TX_RPT_INFO_L32(v)) -#define BIT_SHIFT_DTIM_COUNT_VAP7 0 -#define BIT_MASK_DTIM_COUNT_VAP7 0xff -#define BIT_DTIM_COUNT_VAP7(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7) -#define BIT_GET_DTIM_COUNT_VAP7(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_DIS_ATIM (Offset 0x05B0) */ +/* 2 REG_TXOP_EXTRA_CTRL (Offset 0x04F0) */ -#define BIT_DIS_ATIM_VAP7 BIT(7) -#define BIT_DIS_ATIM_VAP6 BIT(6) -#define BIT_DIS_ATIM_VAP5 BIT(5) -#define BIT_DIS_ATIM_VAP4 BIT(4) -#define BIT_DIS_ATIM_VAP3 BIT(3) -#define BIT_DIS_ATIM_VAP2 BIT(2) -#define BIT_DIS_ATIM_VAP1 BIT(1) -#define BIT_DIS_ATIM_ROOT BIT(0) +#define BIT_TXOP_EFFICIENCY_EN BIT(0) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_BT_POLLUTE_PKTCNT (Offset 0x04F0) */ -/* 2 REG_EARLY_128US (Offset 0x05B1) */ +#define BIT_SHIFT_BT_POLLUTE_PKTCNT 0 +#define BIT_MASK_BT_POLLUTE_PKTCNT 0xffff +#define BIT_BT_POLLUTE_PKTCNT(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKTCNT) << BIT_SHIFT_BT_POLLUTE_PKTCNT) +#define BITS_BT_POLLUTE_PKTCNT \ + (BIT_MASK_BT_POLLUTE_PKTCNT << BIT_SHIFT_BT_POLLUTE_PKTCNT) +#define BIT_CLEAR_BT_POLLUTE_PKTCNT(x) ((x) & (~BITS_BT_POLLUTE_PKTCNT)) +#define BIT_GET_BT_POLLUTE_PKTCNT(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKTCNT) & BIT_MASK_BT_POLLUTE_PKTCNT) +#define BIT_SET_BT_POLLUTE_PKTCNT(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKTCNT(x) | BIT_BT_POLLUTE_PKTCNT(v)) +#endif -#define BIT_SHIFT_TSFT_SEL_TIMER1 3 -#define BIT_MASK_TSFT_SEL_TIMER1 0x7 -#define BIT_TSFT_SEL_TIMER1(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1) -#define BIT_GET_TSFT_SEL_TIMER1(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */ -#define BIT_SHIFT_EARLY_128US 0 -#define BIT_MASK_EARLY_128US 0x7 -#define BIT_EARLY_128US(x) (((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US) -#define BIT_GET_EARLY_128US(x) (((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US) +#define BIT_SHIFT_TRI_HEAD_ADDR 16 +#define BIT_MASK_TRI_HEAD_ADDR 0xfff +#define BIT_TRI_HEAD_ADDR(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR) +#define BITS_TRI_HEAD_ADDR (BIT_MASK_TRI_HEAD_ADDR << BIT_SHIFT_TRI_HEAD_ADDR) +#define BIT_CLEAR_TRI_HEAD_ADDR(x) ((x) & (~BITS_TRI_HEAD_ADDR)) +#define BIT_GET_TRI_HEAD_ADDR(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR) +#define BIT_SET_TRI_HEAD_ADDR(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR(x) | BIT_TRI_HEAD_ADDR(v)) +#define BIT_DROP_TH_EN BIT(8) -/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ +#endif -#define BIT_P2P1_CTW_ALLSTASLEEP BIT(7) -#define BIT_P2P1_OFF_DISTX_EN BIT(6) -#define BIT_P2P1_PWR_MGT_EN BIT(5) -#define BIT_P2P1_NOA1_EN BIT(2) -#define BIT_P2P1_NOA0_EN BIT(1) +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ +/* 2 REG_TX_RPT_INFO_H32 (Offset 0x04F4) */ -#define BIT_P2P2_CTW_ALLSTASLEEP BIT(7) -#define BIT_P2P2_OFF_DISTX_EN BIT(6) -#define BIT_P2P2_PWR_MGT_EN BIT(5) -#define BIT_P2P2_NOA1_EN BIT(2) -#define BIT_P2P2_NOA0_EN BIT(1) +#define BIT_SHIFT_AC_TX_RPT_INFO_H32 0 +#define BIT_MASK_AC_TX_RPT_INFO_H32 0xffffffffL +#define BIT_AC_TX_RPT_INFO_H32(x) \ + (((x) & BIT_MASK_AC_TX_RPT_INFO_H32) << BIT_SHIFT_AC_TX_RPT_INFO_H32) +#define BITS_AC_TX_RPT_INFO_H32 \ + (BIT_MASK_AC_TX_RPT_INFO_H32 << BIT_SHIFT_AC_TX_RPT_INFO_H32) +#define BIT_CLEAR_AC_TX_RPT_INFO_H32(x) ((x) & (~BITS_AC_TX_RPT_INFO_H32)) +#define BIT_GET_AC_TX_RPT_INFO_H32(x) \ + (((x) >> BIT_SHIFT_AC_TX_RPT_INFO_H32) & BIT_MASK_AC_TX_RPT_INFO_H32) +#define BIT_SET_AC_TX_RPT_INFO_H32(x, v) \ + (BIT_CLEAR_AC_TX_RPT_INFO_H32(x) | BIT_AC_TX_RPT_INFO_H32(v)) -/* 2 REG_TIMER0_SRC_SEL (Offset 0x05B4) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SYNC_CLI_SEL 4 -#define BIT_MASK_SYNC_CLI_SEL 0x7 -#define BIT_SYNC_CLI_SEL(x) (((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL) -#define BIT_GET_SYNC_CLI_SEL(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL) +/* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */ +#define BIT_SHIFT_DROP_TH 0 +#define BIT_MASK_DROP_TH 0xff +#define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH) +#define BITS_DROP_TH (BIT_MASK_DROP_TH << BIT_SHIFT_DROP_TH) +#define BIT_CLEAR_DROP_TH(x) ((x) & (~BITS_DROP_TH)) +#define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH) +#define BIT_SET_DROP_TH(x, v) (BIT_CLEAR_DROP_TH(x) | BIT_DROP_TH(v)) -#define BIT_SHIFT_TSFT_SEL_TIMER0 0 -#define BIT_MASK_TSFT_SEL_TIMER0 0x7 -#define BIT_TSFT_SEL_TIMER0(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0) -#define BIT_GET_TSFT_SEL_TIMER0(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_NOA_UNIT_SEL (Offset 0x05B5) */ +/* 2 REG_PTCL_DBG_OUT (Offset 0x04F8) */ +#define BIT_SHIFT_PTCL_DBG_OUT 0 +#define BIT_MASK_PTCL_DBG_OUT 0xffffffffL +#define BIT_PTCL_DBG_OUT(x) \ + (((x) & BIT_MASK_PTCL_DBG_OUT) << BIT_SHIFT_PTCL_DBG_OUT) +#define BITS_PTCL_DBG_OUT (BIT_MASK_PTCL_DBG_OUT << BIT_SHIFT_PTCL_DBG_OUT) +#define BIT_CLEAR_PTCL_DBG_OUT(x) ((x) & (~BITS_PTCL_DBG_OUT)) +#define BIT_GET_PTCL_DBG_OUT(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_OUT) & BIT_MASK_PTCL_DBG_OUT) +#define BIT_SET_PTCL_DBG_OUT(x, v) \ + (BIT_CLEAR_PTCL_DBG_OUT(x) | BIT_PTCL_DBG_OUT(v)) -#define BIT_SHIFT_NOA_UNIT2_SEL 8 -#define BIT_MASK_NOA_UNIT2_SEL 0x7 -#define BIT_NOA_UNIT2_SEL(x) (((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL) -#define BIT_GET_NOA_UNIT2_SEL(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL) +#endif +#if (HALMAC_8192E_SUPPORT) -#define BIT_SHIFT_NOA_UNIT1_SEL 4 -#define BIT_MASK_NOA_UNIT1_SEL 0x7 -#define BIT_NOA_UNIT1_SEL(x) (((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL) -#define BIT_GET_NOA_UNIT1_SEL(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL) +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#define BIT_MOREDATA_CTRL2_EN BIT(19) -#define BIT_SHIFT_NOA_UNIT0_SEL 0 -#define BIT_MASK_NOA_UNIT0_SEL 0x7 -#define BIT_NOA_UNIT0_SEL(x) (((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL) -#define BIT_GET_NOA_UNIT0_SEL(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_P2POFF_DIS_TXTIME (Offset 0x05B7) */ +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#define BIT_MOREDATA_CTRL2_EN_V2 BIT(19) -#define BIT_SHIFT_P2POFF_DIS_TXTIME 0 -#define BIT_MASK_P2POFF_DIS_TXTIME 0xff -#define BIT_P2POFF_DIS_TXTIME(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME) -#define BIT_GET_P2POFF_DIS_TXTIME(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME) +#endif +#if (HALMAC_8192E_SUPPORT) -/* 2 REG_MBSSID_BCN_SPACE2 (Offset 0x05B8) */ +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#define BIT_MOREDATA_CTRL1_EN BIT(18) -#define BIT_SHIFT_BCN_SPACE_CLINT2 16 -#define BIT_MASK_BCN_SPACE_CLINT2 0xfff -#define BIT_BCN_SPACE_CLINT2(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2) -#define BIT_GET_BCN_SPACE_CLINT2(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_BCN_SPACE_CLINT1 0 -#define BIT_MASK_BCN_SPACE_CLINT1 0xfff -#define BIT_BCN_SPACE_CLINT1(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1) -#define BIT_GET_BCN_SPACE_CLINT1(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1) +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#define BIT_MOREDATA_CTRL1_EN_V2 BIT(18) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ +#define BIT_EN_BCN_TRXRPT BIT(17) -/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */ -#define BIT_SHIFT_BCNERR_CNT_OTHERS 24 -#define BIT_MASK_BCNERR_CNT_OTHERS 0xff -#define BIT_BCNERR_CNT_OTHERS(x) (((x) & BIT_MASK_BCNERR_CNT_OTHERS) << BIT_SHIFT_BCNERR_CNT_OTHERS) -#define BIT_GET_BCNERR_CNT_OTHERS(x) (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS) & BIT_MASK_BCNERR_CNT_OTHERS) +#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE BIT(16) -#define BIT_BCNERR_CNT_EN BIT(20) +#endif -#define BIT_SHIFT_SUB_BCN_SPACE_V1 16 -#define BIT_MASK_SUB_BCN_SPACE_V1 0xfff -#define BIT_SUB_BCN_SPACE_V1(x) (((x) & BIT_MASK_SUB_BCN_SPACE_V1) << BIT_SHIFT_SUB_BCN_SPACE_V1) -#define BIT_GET_SUB_BCN_SPACE_V1(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V1) & BIT_MASK_SUB_BCN_SPACE_V1) +#if (HALMAC_8822B_SUPPORT) +/* 2 REG_DUMMY_PAGE4_V1 (Offset 0x04FC) */ -#define BIT_SHIFT_BCNERR_PORT_SEL 16 -#define BIT_MASK_BCNERR_PORT_SEL 0x7 -#define BIT_BCNERR_PORT_SEL(x) (((x) & BIT_MASK_BCNERR_PORT_SEL) << BIT_SHIFT_BCNERR_PORT_SEL) -#define BIT_GET_BCNERR_PORT_SEL(x) (((x) >> BIT_SHIFT_BCNERR_PORT_SEL) & BIT_MASK_BCNERR_PORT_SEL) +#define BIT_BCN_EN_EXTHWSEQ BIT(1) +#define BIT_BCN_EN_HWSEQ BIT(0) +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL +#define BIT_R_MU_STA_GTAB_POSITION(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION) +#define BITS_R_MU_STA_GTAB_POSITION \ + (BIT_MASK_R_MU_STA_GTAB_POSITION << BIT_SHIFT_R_MU_STA_GTAB_POSITION) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION)) +#define BIT_GET_R_MU_STA_GTAB_POSITION(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION) +#define BIT_SET_R_MU_STA_GTAB_POSITION(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION(x) | BIT_R_MU_STA_GTAB_POSITION(v)) -#define BIT_SHIFT_RXBCN_TIMER 16 -#define BIT_MASK_RXBCN_TIMER 0xffff -#define BIT_RXBCN_TIMER(x) (((x) & BIT_MASK_RXBCN_TIMER) << BIT_SHIFT_RXBCN_TIMER) -#define BIT_GET_RXBCN_TIMER(x) (((x) >> BIT_SHIFT_RXBCN_TIMER) & BIT_MASK_RXBCN_TIMER) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BCNERR_CNT_INVALID 16 -#define BIT_MASK_BCNERR_CNT_INVALID 0xff -#define BIT_BCNERR_CNT_INVALID(x) (((x) & BIT_MASK_BCNERR_CNT_INVALID) << BIT_SHIFT_BCNERR_CNT_INVALID) -#define BIT_GET_BCNERR_CNT_INVALID(x) (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID) & BIT_MASK_BCNERR_CNT_INVALID) +/* 2 REG_MOREDATA (Offset 0x04FE) */ +#define BIT_MOREDATA_CTRL2_EN_V1 BIT(3) +#define BIT_MOREDATA_CTRL1_EN_V1 BIT(2) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DUMMY_PAGE4_1 (Offset 0x04FE) */ +#define BIT_EN_BCN_TRXRPT_V2 BIT(1) -/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SUB_BCN_SPACE 16 -#define BIT_MASK_SUB_BCN_SPACE 0xff -#define BIT_SUB_BCN_SPACE(x) (((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE) -#define BIT_GET_SUB_BCN_SPACE(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE) +/* 2 REG_MOREDATA (Offset 0x04FE) */ +#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_EDCA_VO_PARAM (Offset 0x0500) */ +#define BIT_SHIFT_TXOPLIMIT 16 +#define BIT_MASK_TXOPLIMIT 0x7ff +#define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT) +#define BITS_TXOPLIMIT (BIT_MASK_TXOPLIMIT << BIT_SHIFT_TXOPLIMIT) +#define BIT_CLEAR_TXOPLIMIT(x) ((x) & (~BITS_TXOPLIMIT)) +#define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT) +#define BIT_SET_TXOPLIMIT(x, v) (BIT_CLEAR_TXOPLIMIT(x) | BIT_TXOPLIMIT(v)) + +#define BIT_SHIFT_CW 8 +#define BIT_MASK_CW 0xff +#define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW) +#define BITS_CW (BIT_MASK_CW << BIT_SHIFT_CW) +#define BIT_CLEAR_CW(x) ((x) & (~BITS_CW)) +#define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW) +#define BIT_SET_CW(x, v) (BIT_CLEAR_CW(x) | BIT_CW(v)) + +#define BIT_SHIFT_AIFS 0 +#define BIT_MASK_AIFS 0xff +#define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS) +#define BITS_AIFS (BIT_MASK_AIFS << BIT_SHIFT_AIFS) +#define BIT_CLEAR_AIFS(x) ((x) & (~BITS_AIFS)) +#define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS) +#define BIT_SET_AIFS(x, v) (BIT_CLEAR_AIFS(x) | BIT_AIFS(v)) -/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ +/* 2 REG_BCNTCFG (Offset 0x0510) */ +#define BIT_SHIFT_BCNCW_MAX 12 +#define BIT_MASK_BCNCW_MAX 0xf +#define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX) +#define BITS_BCNCW_MAX (BIT_MASK_BCNCW_MAX << BIT_SHIFT_BCNCW_MAX) +#define BIT_CLEAR_BCNCW_MAX(x) ((x) & (~BITS_BCNCW_MAX)) +#define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX) +#define BIT_SET_BCNCW_MAX(x, v) (BIT_CLEAR_BCNCW_MAX(x) | BIT_BCNCW_MAX(v)) + +#define BIT_SHIFT_BCNCW_MIN 8 +#define BIT_MASK_BCNCW_MIN 0xf +#define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN) +#define BITS_BCNCW_MIN (BIT_MASK_BCNCW_MIN << BIT_SHIFT_BCNCW_MIN) +#define BIT_CLEAR_BCNCW_MIN(x) ((x) & (~BITS_BCNCW_MIN)) +#define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN) +#define BIT_SET_BCNCW_MIN(x, v) (BIT_CLEAR_BCNCW_MIN(x) | BIT_BCNCW_MIN(v)) + +#define BIT_SHIFT_BCNIFS 0 +#define BIT_MASK_BCNIFS 0xff +#define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS) +#define BITS_BCNIFS (BIT_MASK_BCNIFS << BIT_SHIFT_BCNIFS) +#define BIT_CLEAR_BCNIFS(x) ((x) & (~BITS_BCNIFS)) +#define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS) +#define BIT_SET_BCNIFS(x, v) (BIT_CLEAR_BCNIFS(x) | BIT_BCNIFS(v)) -#define BIT_SHIFT_TXPAUSE1 8 -#define BIT_MASK_TXPAUSE1 0xff -#define BIT_TXPAUSE1(x) (((x) & BIT_MASK_TXPAUSE1) << BIT_SHIFT_TXPAUSE1) -#define BIT_GET_TXPAUSE1(x) (((x) >> BIT_SHIFT_TXPAUSE1) & BIT_MASK_TXPAUSE1) - +/* 2 REG_PIFS (Offset 0x0512) */ -#define BIT_SHIFT_BCNERR_CNT_MAC 8 -#define BIT_MASK_BCNERR_CNT_MAC 0xff -#define BIT_BCNERR_CNT_MAC(x) (((x) & BIT_MASK_BCNERR_CNT_MAC) << BIT_SHIFT_BCNERR_CNT_MAC) -#define BIT_GET_BCNERR_CNT_MAC(x) (((x) >> BIT_SHIFT_BCNERR_CNT_MAC) & BIT_MASK_BCNERR_CNT_MAC) +#define BIT_SHIFT_PIFS 0 +#define BIT_MASK_PIFS 0xff +#define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS) +#define BITS_PIFS (BIT_MASK_PIFS << BIT_SHIFT_PIFS) +#define BIT_CLEAR_PIFS(x) ((x) & (~BITS_PIFS)) +#define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS) +#define BIT_SET_PIFS(x, v) (BIT_CLEAR_PIFS(x) | BIT_PIFS(v)) -#define BIT_CHANGE_POW_BCN_AREA BIT(1) +/* 2 REG_RDG_PIFS (Offset 0x0513) */ -#endif +#define BIT_SHIFT_RDG_PIFS 0 +#define BIT_MASK_RDG_PIFS 0xff +#define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS) +#define BITS_RDG_PIFS (BIT_MASK_RDG_PIFS << BIT_SHIFT_RDG_PIFS) +#define BIT_CLEAR_RDG_PIFS(x) ((x) & (~BITS_RDG_PIFS)) +#define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS) +#define BIT_SET_RDG_PIFS(x, v) (BIT_CLEAR_RDG_PIFS(x) | BIT_RDG_PIFS(v)) +/* 2 REG_SIFS (Offset 0x0514) */ -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_SIFS_OFDM_TRX 24 +#define BIT_MASK_SIFS_OFDM_TRX 0xff +#define BIT_SIFS_OFDM_TRX(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX) +#define BITS_SIFS_OFDM_TRX (BIT_MASK_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX) +#define BIT_CLEAR_SIFS_OFDM_TRX(x) ((x) & (~BITS_SIFS_OFDM_TRX)) +#define BIT_GET_SIFS_OFDM_TRX(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX) +#define BIT_SET_SIFS_OFDM_TRX(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX(x) | BIT_SIFS_OFDM_TRX(v)) + +#define BIT_SHIFT_SIFS_CCK_TRX 16 +#define BIT_MASK_SIFS_CCK_TRX 0xff +#define BIT_SIFS_CCK_TRX(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX) +#define BITS_SIFS_CCK_TRX (BIT_MASK_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) +#define BIT_CLEAR_SIFS_CCK_TRX(x) ((x) & (~BITS_SIFS_CCK_TRX)) +#define BIT_GET_SIFS_CCK_TRX(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX) +#define BIT_SET_SIFS_CCK_TRX(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX(x) | BIT_SIFS_CCK_TRX(v)) + +#define BIT_SHIFT_SIFS_OFDM_CTX 8 +#define BIT_MASK_SIFS_OFDM_CTX 0xff +#define BIT_SIFS_OFDM_CTX(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX) +#define BITS_SIFS_OFDM_CTX (BIT_MASK_SIFS_OFDM_CTX << BIT_SHIFT_SIFS_OFDM_CTX) +#define BIT_CLEAR_SIFS_OFDM_CTX(x) ((x) & (~BITS_SIFS_OFDM_CTX)) +#define BIT_GET_SIFS_OFDM_CTX(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX) +#define BIT_SET_SIFS_OFDM_CTX(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX(x) | BIT_SIFS_OFDM_CTX(v)) + +#define BIT_SHIFT_SIFS_CCK_CTX 0 +#define BIT_MASK_SIFS_CCK_CTX 0xff +#define BIT_SIFS_CCK_CTX(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX) +#define BITS_SIFS_CCK_CTX (BIT_MASK_SIFS_CCK_CTX << BIT_SHIFT_SIFS_CCK_CTX) +#define BIT_CLEAR_SIFS_CCK_CTX(x) ((x) & (~BITS_SIFS_CCK_CTX)) +#define BIT_GET_SIFS_CCK_CTX(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX) +#define BIT_SET_SIFS_CCK_CTX(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX(x) | BIT_SIFS_CCK_CTX(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TSFTR_SYN_OFFSET (Offset 0x0518) */ -/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ +#define BIT_SHIFT_TSFTR_SNC_OFFSET 0 +#define BIT_MASK_TSFTR_SNC_OFFSET 0xffff +#define BIT_TSFTR_SNC_OFFSET(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET) +#define BITS_TSFTR_SNC_OFFSET \ + (BIT_MASK_TSFTR_SNC_OFFSET << BIT_SHIFT_TSFTR_SNC_OFFSET) +#define BIT_CLEAR_TSFTR_SNC_OFFSET(x) ((x) & (~BITS_TSFTR_SNC_OFFSET)) +#define BIT_GET_TSFTR_SNC_OFFSET(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET) +#define BIT_SET_TSFTR_SNC_OFFSET(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET(x) | BIT_TSFTR_SNC_OFFSET(v)) +#endif -#define BIT_SHIFT_BCN_SPACE_CLINT3 0 -#define BIT_MASK_BCN_SPACE_CLINT3 0xfff -#define BIT_BCN_SPACE_CLINT3(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3) -#define BIT_GET_BCN_SPACE_CLINT3(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_AGGR_BREAK_TIME (Offset 0x051A) */ -#endif +#define BIT_SHIFT_AGGR_BK_TIME 0 +#define BIT_MASK_AGGR_BK_TIME 0xff +#define BIT_AGGR_BK_TIME(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME) +#define BITS_AGGR_BK_TIME (BIT_MASK_AGGR_BK_TIME << BIT_SHIFT_AGGR_BK_TIME) +#define BIT_CLEAR_AGGR_BK_TIME(x) ((x) & (~BITS_AGGR_BK_TIME)) +#define BIT_GET_AGGR_BK_TIME(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME) +#define BIT_SET_AGGR_BK_TIME(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME(x) | BIT_AGGR_BK_TIME(v)) +/* 2 REG_SLOT (Offset 0x051B) */ -#if (HALMAC_8197F_SUPPORT) +#define BIT_SHIFT_SLOT 0 +#define BIT_MASK_SLOT 0xff +#define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT) +#define BITS_SLOT (BIT_MASK_SLOT << BIT_SHIFT_SLOT) +#define BIT_CLEAR_SLOT(x) ((x) & (~BITS_SLOT)) +#define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT) +#define BIT_SET_SLOT(x, v) (BIT_CLEAR_SLOT(x) | BIT_SLOT(v)) +#endif -/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_EDCA_CPUMGQ_PARAM (Offset 0x051C) */ -#define BIT_SHIFT_BW_CFG 0 -#define BIT_MASK_BW_CFG 0x3 -#define BIT_BW_CFG(x) (((x) & BIT_MASK_BW_CFG) << BIT_SHIFT_BW_CFG) -#define BIT_GET_BW_CFG(x) (((x) >> BIT_SHIFT_BW_CFG) & BIT_MASK_BW_CFG) +#define BIT_SHIFT_CW_V1 8 +#define BIT_MASK_CW_V1 0xff +#define BIT_CW_V1(x) (((x) & BIT_MASK_CW_V1) << BIT_SHIFT_CW_V1) +#define BITS_CW_V1 (BIT_MASK_CW_V1 << BIT_SHIFT_CW_V1) +#define BIT_CLEAR_CW_V1(x) ((x) & (~BITS_CW_V1)) +#define BIT_GET_CW_V1(x) (((x) >> BIT_SHIFT_CW_V1) & BIT_MASK_CW_V1) +#define BIT_SET_CW_V1(x, v) (BIT_CLEAR_CW_V1(x) | BIT_CW_V1(v)) +#define BIT_SHIFT_AIFS_V1 0 +#define BIT_MASK_AIFS_V1 0xff +#define BIT_AIFS_V1(x) (((x) & BIT_MASK_AIFS_V1) << BIT_SHIFT_AIFS_V1) +#define BITS_AIFS_V1 (BIT_MASK_AIFS_V1 << BIT_SHIFT_AIFS_V1) +#define BIT_CLEAR_AIFS_V1(x) ((x) & (~BITS_AIFS_V1)) +#define BIT_GET_AIFS_V1(x) (((x) >> BIT_SHIFT_AIFS_V1) & BIT_MASK_AIFS_V1) +#define BIT_SET_AIFS_V1(x, v) (BIT_CLEAR_AIFS_V1(x) | BIT_AIFS_V1(v)) -#define BIT_SHIFT_BCN_ELY_ADJ 0 -#define BIT_MASK_BCN_ELY_ADJ 0xffff -#define BIT_BCN_ELY_ADJ(x) (((x) & BIT_MASK_BCN_ELY_ADJ) << BIT_SHIFT_BCN_ELY_ADJ) -#define BIT_GET_BCN_ELY_ADJ(x) (((x) >> BIT_SHIFT_BCN_ELY_ADJ) & BIT_MASK_BCN_ELY_ADJ) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BCNERR_CNT_CCA 0 -#define BIT_MASK_BCNERR_CNT_CCA 0xff -#define BIT_BCNERR_CNT_CCA(x) (((x) & BIT_MASK_BCNERR_CNT_CCA) << BIT_SHIFT_BCNERR_CNT_CCA) -#define BIT_GET_BCNERR_CNT_CCA(x) (((x) >> BIT_SHIFT_BCNERR_CNT_CCA) & BIT_MASK_BCNERR_CNT_CCA) +/* 2 REG_NOA_OFF_ERLY_TIME (Offset 0x051D) */ +#define BIT_SHIFT__NOA_OFF_ERLY_TIME 0 +#define BIT_MASK__NOA_OFF_ERLY_TIME 0xff +#define BIT__NOA_OFF_ERLY_TIME(x) \ + (((x) & BIT_MASK__NOA_OFF_ERLY_TIME) << BIT_SHIFT__NOA_OFF_ERLY_TIME) +#define BITS__NOA_OFF_ERLY_TIME \ + (BIT_MASK__NOA_OFF_ERLY_TIME << BIT_SHIFT__NOA_OFF_ERLY_TIME) +#define BIT_CLEAR__NOA_OFF_ERLY_TIME(x) ((x) & (~BITS__NOA_OFF_ERLY_TIME)) +#define BIT_GET__NOA_OFF_ERLY_TIME(x) \ + (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME) & BIT_MASK__NOA_OFF_ERLY_TIME) +#define BIT_SET__NOA_OFF_ERLY_TIME(x, v) \ + (BIT_CLEAR__NOA_OFF_ERLY_TIME(x) | BIT__NOA_OFF_ERLY_TIME(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CPUMGQ_PAUSE (Offset 0x051E) */ +#define BIT_MAC_STOP_CPUMGQ_V1 BIT(0) -/* 2 REG_ACMHWCTRL (Offset 0x05C0) */ +#endif -#define BIT_BEQ_ACM_STATUS BIT(7) -#define BIT_VIQ_ACM_STATUS BIT(6) -#define BIT_VOQ_ACM_STATUS BIT(5) -#define BIT_BEQ_ACM_EN BIT(3) -#define BIT_VIQ_ACM_EN BIT(2) -#define BIT_VOQ_ACM_EN BIT(1) -#define BIT_ACMHWEN BIT(0) +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_ACMRSTCTRL (Offset 0x05C1) */ +/* 2 REG_PS_TIMER_CTRL (Offset 0x051F) */ -#define BIT_BE_ACM_RESET_USED_TIME BIT(2) -#define BIT_VI_ACM_RESET_USED_TIME BIT(1) -#define BIT_VO_ACM_RESET_USED_TIME BIT(0) +#define BIT_PS_TIMER_B_EN_V1 BIT(7) -/* 2 REG_ACMAVG (Offset 0x05C2) */ +#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1 4 +#define BIT_MASK_PS_TIMER_B_TSF_SEL_V1 0x3 +#define BIT_PS_TIMER_B_TSF_SEL_V1(x) \ + (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_V1) \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1) +#define BITS_PS_TIMER_B_TSF_SEL_V1 \ + (BIT_MASK_PS_TIMER_B_TSF_SEL_V1 << BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_V1(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL_V1)) +#define BIT_GET_PS_TIMER_B_TSF_SEL_V1(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_V1) & \ + BIT_MASK_PS_TIMER_B_TSF_SEL_V1) +#define BIT_SET_PS_TIMER_B_TSF_SEL_V1(x, v) \ + (BIT_CLEAR_PS_TIMER_B_TSF_SEL_V1(x) | BIT_PS_TIMER_B_TSF_SEL_V1(v)) + +#define BIT_PS_TIMER_A_EN_V1 BIT(3) +#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1 0 +#define BIT_MASK_PS_TIMER_A_TSF_SEL_V1 0x3 +#define BIT_PS_TIMER_A_TSF_SEL_V1(x) \ + (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_V1) \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1) +#define BITS_PS_TIMER_A_TSF_SEL_V1 \ + (BIT_MASK_PS_TIMER_A_TSF_SEL_V1 << BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_V1(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL_V1)) +#define BIT_GET_PS_TIMER_A_TSF_SEL_V1(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_V1) & \ + BIT_MASK_PS_TIMER_A_TSF_SEL_V1) +#define BIT_SET_PS_TIMER_A_TSF_SEL_V1(x, v) \ + (BIT_CLEAR_PS_TIMER_A_TSF_SEL_V1(x) | BIT_PS_TIMER_A_TSF_SEL_V1(v)) -#define BIT_SHIFT_AVGPERIOD 0 -#define BIT_MASK_AVGPERIOD 0xffff -#define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD) -#define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_VO_ADMTIME (Offset 0x05C4) */ +/* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */ +#define BIT_DIS_EDCCA BIT(15) +#define BIT_DIS_CCA BIT(14) +#define BIT_LSIG_TXOP_TXCMD_NAV BIT(13) +#define BIT_SIFS_BK_EN BIT(12) -#define BIT_SHIFT_VO_ADMITTED_TIME 0 -#define BIT_MASK_VO_ADMITTED_TIME 0xffff -#define BIT_VO_ADMITTED_TIME(x) (((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME) -#define BIT_GET_VO_ADMITTED_TIME(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME) +#define BIT_SHIFT_TXQ_NAV_MSK 8 +#define BIT_MASK_TXQ_NAV_MSK 0xf +#define BIT_TXQ_NAV_MSK(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK) +#define BITS_TXQ_NAV_MSK (BIT_MASK_TXQ_NAV_MSK << BIT_SHIFT_TXQ_NAV_MSK) +#define BIT_CLEAR_TXQ_NAV_MSK(x) ((x) & (~BITS_TXQ_NAV_MSK)) +#define BIT_GET_TXQ_NAV_MSK(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK) +#define BIT_SET_TXQ_NAV_MSK(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK(x) | BIT_TXQ_NAV_MSK(v)) +#define BIT_DIS_CW BIT(7) +#define BIT_NAV_END_TXOP BIT(6) +#define BIT_RDG_END_TXOP BIT(5) -/* 2 REG_VI_ADMTIME (Offset 0x05C6) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_VI_ADMITTED_TIME 0 -#define BIT_MASK_VI_ADMITTED_TIME 0xffff -#define BIT_VI_ADMITTED_TIME(x) (((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME) -#define BIT_GET_VI_ADMITTED_TIME(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME) +/* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */ +#define BIT_AC_INBCN_HOLD BIT(4) -/* 2 REG_BE_ADMTIME (Offset 0x05C8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BE_ADMITTED_TIME 0 -#define BIT_MASK_BE_ADMITTED_TIME 0xffff -#define BIT_BE_ADMITTED_TIME(x) (((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME) -#define BIT_GET_BE_ADMITTED_TIME(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME) +/* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */ +#define BIT_MGTQ_TXOP_EN BIT(3) +#define BIT_MGTQ_RTSMF_EN BIT(2) +#define BIT_HIQ_RTSMF_EN BIT(1) +#define BIT_BCN_RTSMF_EN BIT(0) -/* 2 REG_EDCA_RANDOM_GEN (Offset 0x05CC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RANDOM_GEN 0 -#define BIT_MASK_RANDOM_GEN 0xffffff -#define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN) -#define BIT_GET_RANDOM_GEN(x) (((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN) +/* 2 REG_TXPAUSE (Offset 0x0522) */ +#define BIT_STOP_BCN_HI_MGT BIT(7) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT) +/* 2 REG_TXPAUSE (Offset 0x0522) */ +#define BIT_MAC_STOPCPUMGQ BIT(7) -/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ +#endif -#define BIT_NOA_SEL BIT(4) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_TXPAUSE (Offset 0x0522) */ +#define BIT_MAC_STOPBCNQ BIT(6) +#define BIT_MAC_STOPHIQ BIT(5) +#define BIT_MAC_STOPMGQ BIT(4) +#define BIT_MAC_STOPBK BIT(3) +#define BIT_MAC_STOPBE BIT(2) +#define BIT_MAC_STOPVI BIT(1) +#define BIT_MAC_STOPVO BIT(0) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +#define BIT_DIS_BT_CCA BIT(7) -/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_NOA_SEL 4 -#define BIT_MASK_NOA_SEL 0x7 -#define BIT_NOA_SEL(x) (((x) & BIT_MASK_NOA_SEL) << BIT_SHIFT_NOA_SEL) -#define BIT_GET_NOA_SEL(x) (((x) >> BIT_SHIFT_NOA_SEL) & BIT_MASK_NOA_SEL) +/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +#define BIT_DIS_TXREQ_CLR_CPUMGQ BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ +#define BIT_DIS_TXREQ_CLR_HI BIT(5) +#define BIT_DIS_TXREQ_CLR_MGQ BIT(4) +#define BIT_DIS_TXREQ_CLR_VO BIT(3) +#define BIT_DIS_TXREQ_CLR_VI BIT(2) +#define BIT_DIS_TXREQ_CLR_BE BIT(1) +#define BIT_DIS_TXREQ_CLR_BK BIT(0) -/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ +/* 2 REG_RD_CTRL (Offset 0x0524) */ -#define BIT_NOA_SEL_V1 BIT(4) +#define BIT_EN_CLR_TXREQ_INCCA BIT(15) +#define BIT_DIS_TX_OVER_BCNQ BIT(14) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RD_CTRL (Offset 0x0524) */ +#define BIT_EN_BCNERR_INCCCA BIT(13) -/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_TXCMD_SEG_SEL 0 -#define BIT_MASK_TXCMD_SEG_SEL 0xf -#define BIT_TXCMD_SEG_SEL(x) (((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL) -#define BIT_GET_TXCMD_SEG_SEL(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL) +/* 2 REG_RD_CTRL (Offset 0x0524) */ +#define BIT_EN_BCNERR_INCCA BIT(13) +#define BIT_EN_BCNERR_INEDCCA BIT(12) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RD_CTRL (Offset 0x0524) */ +#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11) +#define BIT_DIS_TXOP_CFE BIT(10) +#define BIT_DIS_LSIG_CFE BIT(9) -/* 2 REG_NOA_PARAM (Offset 0x05E0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH) -#define BIT_MASK_NOA_COUNT 0xff -#define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT) -#define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT) +/* 2 REG_RD_CTRL (Offset 0x0524) */ +#define BIT_DIS_STBC_CFE BIT(8) -#define BIT_SHIFT_NOA_START_TIME (64 & CPU_OPT_WIDTH) -#define BIT_MASK_NOA_START_TIME 0xffffffffL -#define BIT_NOA_START_TIME(x) (((x) & BIT_MASK_NOA_START_TIME) << BIT_SHIFT_NOA_START_TIME) -#define BIT_GET_NOA_START_TIME(x) (((x) >> BIT_SHIFT_NOA_START_TIME) & BIT_MASK_NOA_START_TIME) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NOA_INTERVAL (32 & CPU_OPT_WIDTH) -#define BIT_MASK_NOA_INTERVAL 0xffffffffL -#define BIT_NOA_INTERVAL(x) (((x) & BIT_MASK_NOA_INTERVAL) << BIT_SHIFT_NOA_INTERVAL) -#define BIT_GET_NOA_INTERVAL(x) (((x) >> BIT_SHIFT_NOA_INTERVAL) & BIT_MASK_NOA_INTERVAL) +/* 2 REG_RD_CTRL (Offset 0x0524) */ +#define BIT_BKQ_RD_INIT_EN BIT(7) +#define BIT_BEQ_RD_INIT_EN BIT(6) +#define BIT_VIQ_RD_INIT_EN BIT(5) +#define BIT_VOQ_RD_INIT_EN BIT(4) +#define BIT_BKQ_RD_RESP_EN BIT(3) +#define BIT_BEQ_RD_RESP_EN BIT(2) +#define BIT_VIQ_RD_RESP_EN BIT(1) +#define BIT_VOQ_RD_RESP_EN BIT(0) -#define BIT_SHIFT_NOA_DURATION 0 -#define BIT_MASK_NOA_DURATION 0xffffffffL -#define BIT_NOA_DURATION(x) (((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION) -#define BIT_GET_NOA_DURATION(x) (((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION) +/* 2 REG_MBSSID_CTRL (Offset 0x0526) */ +#define BIT_MBID_BCNQ7_EN BIT(7) +#define BIT_MBID_BCNQ6_EN BIT(6) +#define BIT_MBID_BCNQ5_EN BIT(5) +#define BIT_MBID_BCNQ4_EN BIT(4) +#define BIT_MBID_BCNQ3_EN BIT(3) +#define BIT_MBID_BCNQ2_EN BIT(2) +#define BIT_MBID_BCNQ1_EN BIT(1) +#define BIT_MBID_BCNQ0_EN BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +#define BIT_P2P_CTW_ALLSTASLEEP BIT(7) -/* 2 REG_NOA_PARAM (Offset 0x05E0) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_NOA_DURATION_V1 0 -#define BIT_MASK_NOA_DURATION_V1 0xffffffffL -#define BIT_NOA_DURATION_V1(x) (((x) & BIT_MASK_NOA_DURATION_V1) << BIT_SHIFT_NOA_DURATION_V1) -#define BIT_GET_NOA_DURATION_V1(x) (((x) >> BIT_SHIFT_NOA_DURATION_V1) & BIT_MASK_NOA_DURATION_V1) +/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +#define BIT_P2P_DISTX_SEL BIT(6) -/* 2 REG_NOA_PARAM_1 (Offset 0x05E4) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NOA_INTERVAL_V1 0 -#define BIT_MASK_NOA_INTERVAL_V1 0xffffffffL -#define BIT_NOA_INTERVAL_V1(x) (((x) & BIT_MASK_NOA_INTERVAL_V1) << BIT_SHIFT_NOA_INTERVAL_V1) -#define BIT_GET_NOA_INTERVAL_V1(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_V1) & BIT_MASK_NOA_INTERVAL_V1) +/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +#define BIT_PWR_MGT_EN BIT(5) -/* 2 REG_NOA_PARAM_2 (Offset 0x05E8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NOA_START_TIME_V1 0 -#define BIT_MASK_NOA_START_TIME_V1 0xffffffffL -#define BIT_NOA_START_TIME_V1(x) (((x) & BIT_MASK_NOA_START_TIME_V1) << BIT_SHIFT_NOA_START_TIME_V1) -#define BIT_GET_NOA_START_TIME_V1(x) (((x) >> BIT_SHIFT_NOA_START_TIME_V1) & BIT_MASK_NOA_START_TIME_V1) +/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +#define BIT_P2P_BCN_AREA_EN BIT(4) +#define BIT_P2P_CTWND_EN BIT(3) -/* 2 REG_NOA_PARAM_3 (Offset 0x05EC) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NOA_COUNT_V1 0 -#define BIT_MASK_NOA_COUNT_V1 0xffffffffL -#define BIT_NOA_COUNT_V1(x) (((x) & BIT_MASK_NOA_COUNT_V1) << BIT_SHIFT_NOA_COUNT_V1) -#define BIT_GET_NOA_COUNT_V1(x) (((x) >> BIT_SHIFT_NOA_COUNT_V1) & BIT_MASK_NOA_COUNT_V1) +/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ +#define BIT_P2P_NOA1_EN BIT(2) +#define BIT_P2P_NOA0_EN BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_NOA_SUBIE (Offset 0x05ED) */ +/* 2 REG_P2PPS_CTRL (Offset 0x0527) */ -#define BIT_MORE_NOA_DESC BIT(19) -#define BIT_NOA_DESC1_VALID BIT(18) -#define BIT_NOA_DESC0_VALID BIT(17) -#define BIT_NOA_HEAD_VALID BIT(16) -#define BIT_NOA_OPP_PS BIT(15) +#define BIT_P2P_BCN_SEL BIT(0) -#define BIT_SHIFT_NOA_CTW 8 -#define BIT_MASK_NOA_CTW 0x7f -#define BIT_NOA_CTW(x) (((x) & BIT_MASK_NOA_CTW) << BIT_SHIFT_NOA_CTW) -#define BIT_GET_NOA_CTW(x) (((x) >> BIT_SHIFT_NOA_CTW) & BIT_MASK_NOA_CTW) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_NOA_INDEX 0 -#define BIT_MASK_NOA_INDEX 0xff -#define BIT_NOA_INDEX(x) (((x) & BIT_MASK_NOA_INDEX) << BIT_SHIFT_NOA_INDEX) -#define BIT_GET_NOA_INDEX(x) (((x) >> BIT_SHIFT_NOA_INDEX) & BIT_MASK_NOA_INDEX) +/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#define BIT_EN_P2P_CTWND1 BIT(23) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#define BIT_EN_TBTT_AREA_FOR_BB BIT(23) -/* 2 REG_P2P_RST (Offset 0x05F0) */ +#endif -#define BIT_P2P2_PWR_RST1 BIT(5) -#define BIT_P2P2_PWR_RST0 BIT(4) -#define BIT_P2P1_PWR_RST1 BIT(3) -#define BIT_P2P1_PWR_RST0 BIT(2) -#define BIT_P2P_PWR_RST1_V1 BIT(1) -#define BIT_P2P_PWR_RST0_V1 BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#define BIT_EN_BKF_CLR_TXREQ BIT(22) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ -#define BIT_STOP_CPUMGQ BIT(16) -#define BIT_SYNC_TSF_NOW BIT(2) +#define BIT_EN_TSFBIT32_RST_P2P BIT(21) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ +#define BIT_EN_BCN_TX_BTCCA BIT(20) +#define BIT_DIS_PKT_TX_ATIM BIT(19) +#define BIT_DIS_BCN_DIS_CTN BIT(18) +#define BIT_EN_NAVEND_RST_TXOP BIT(17) +#define BIT_EN_FILTER_CCA BIT(16) + +#define BIT_SHIFT_CCA_FILTER_THRS 8 +#define BIT_MASK_CCA_FILTER_THRS 0xff +#define BIT_CCA_FILTER_THRS(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS) +#define BITS_CCA_FILTER_THRS \ + (BIT_MASK_CCA_FILTER_THRS << BIT_SHIFT_CCA_FILTER_THRS) +#define BIT_CLEAR_CCA_FILTER_THRS(x) ((x) & (~BITS_CCA_FILTER_THRS)) +#define BIT_GET_CCA_FILTER_THRS(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS) +#define BIT_SET_CCA_FILTER_THRS(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS(x) | BIT_CCA_FILTER_THRS(v)) + +#define BIT_SHIFT_EDCCA_THRS 0 +#define BIT_MASK_EDCCA_THRS 0xff +#define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS) +#define BITS_EDCCA_THRS (BIT_MASK_EDCCA_THRS << BIT_SHIFT_EDCCA_THRS) +#define BIT_CLEAR_EDCCA_THRS(x) ((x) & (~BITS_EDCCA_THRS)) +#define BIT_GET_EDCCA_THRS(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS) +#define BIT_SET_EDCCA_THRS(x, v) (BIT_CLEAR_EDCCA_THRS(x) | BIT_EDCCA_THRS(v)) -/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +/* 2 REG_P2PPS_SPEC_STATE (Offset 0x052B) */ -#define BIT_SYNC_CLI BIT(1) -#define BIT_SCHEDULER_RST_V1 BIT(0) +#define BIT_SPEC_POWER_STATE BIT(7) +#define BIT_SPEC_CTWINDOW_ON BIT(6) +#define BIT_SPEC_BEACON_AREA_ON BIT(5) +#define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4) +#define BIT_SPEC_NOA1_OFF_PERIOD BIT(3) +#define BIT_SPEC_FORCE_DOZE1 BIT(2) +#define BIT_SPEC_NOA0_OFF_PERIOD BIT(1) +#define BIT_SPEC_FORCE_DOZE0 BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TXOP_LIMIT_CTRL (Offset 0x052C) */ +#define BIT_SHIFT_TXOP_TBTT_CNT 24 +#define BIT_MASK_TXOP_TBTT_CNT 0xff +#define BIT_TXOP_TBTT_CNT(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT) << BIT_SHIFT_TXOP_TBTT_CNT) +#define BITS_TXOP_TBTT_CNT (BIT_MASK_TXOP_TBTT_CNT << BIT_SHIFT_TXOP_TBTT_CNT) +#define BIT_CLEAR_TXOP_TBTT_CNT(x) ((x) & (~BITS_TXOP_TBTT_CNT)) +#define BIT_GET_TXOP_TBTT_CNT(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT) & BIT_MASK_TXOP_TBTT_CNT) +#define BIT_SET_TXOP_TBTT_CNT(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT(x) | BIT_TXOP_TBTT_CNT(v)) -/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_SHIFT_TXOP_TBTT_CNT_SEL 20 +#define BIT_MASK_TXOP_TBTT_CNT_SEL 0xf +#define BIT_TXOP_TBTT_CNT_SEL(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL) << BIT_SHIFT_TXOP_TBTT_CNT_SEL) +#define BITS_TXOP_TBTT_CNT_SEL \ + (BIT_MASK_TXOP_TBTT_CNT_SEL << BIT_SHIFT_TXOP_TBTT_CNT_SEL) +#define BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) ((x) & (~BITS_TXOP_TBTT_CNT_SEL)) +#define BIT_GET_TXOP_TBTT_CNT_SEL(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL) & BIT_MASK_TXOP_TBTT_CNT_SEL) +#define BIT_SET_TXOP_TBTT_CNT_SEL(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) | BIT_TXOP_TBTT_CNT_SEL(v)) +#define BIT_SHIFT_TXOP_LMT_EN 16 +#define BIT_MASK_TXOP_LMT_EN 0xf +#define BIT_TXOP_LMT_EN(x) \ + (((x) & BIT_MASK_TXOP_LMT_EN) << BIT_SHIFT_TXOP_LMT_EN) +#define BITS_TXOP_LMT_EN (BIT_MASK_TXOP_LMT_EN << BIT_SHIFT_TXOP_LMT_EN) +#define BIT_CLEAR_TXOP_LMT_EN(x) ((x) & (~BITS_TXOP_LMT_EN)) +#define BIT_GET_TXOP_LMT_EN(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_EN) & BIT_MASK_TXOP_LMT_EN) +#define BIT_SET_TXOP_LMT_EN(x, v) \ + (BIT_CLEAR_TXOP_LMT_EN(x) | BIT_TXOP_LMT_EN(v)) -#define BIT_SHIFT_CPUMGQ_PARAMETER 0 -#define BIT_MASK_CPUMGQ_PARAMETER 0xffff -#define BIT_CPUMGQ_PARAMETER(x) (((x) & BIT_MASK_CPUMGQ_PARAMETER) << BIT_SHIFT_CPUMGQ_PARAMETER) -#define BIT_GET_CPUMGQ_PARAMETER(x) (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER) & BIT_MASK_CPUMGQ_PARAMETER) +#define BIT_SHIFT_TXOP_LMT_TX_TIME 8 +#define BIT_MASK_TXOP_LMT_TX_TIME 0xff +#define BIT_TXOP_LMT_TX_TIME(x) \ + (((x) & BIT_MASK_TXOP_LMT_TX_TIME) << BIT_SHIFT_TXOP_LMT_TX_TIME) +#define BITS_TXOP_LMT_TX_TIME \ + (BIT_MASK_TXOP_LMT_TX_TIME << BIT_SHIFT_TXOP_LMT_TX_TIME) +#define BIT_CLEAR_TXOP_LMT_TX_TIME(x) ((x) & (~BITS_TXOP_LMT_TX_TIME)) +#define BIT_GET_TXOP_LMT_TX_TIME(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME) & BIT_MASK_TXOP_LMT_TX_TIME) +#define BIT_SET_TXOP_LMT_TX_TIME(x, v) \ + (BIT_CLEAR_TXOP_LMT_TX_TIME(x) | BIT_TXOP_LMT_TX_TIME(v)) +#define BIT_TXOP_CNT_TRIGGER_RESET BIT(7) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_PS_TIMER_A_V2 (Offset 0x052C) */ +#define BIT_SHIFT_PS_TIMER_A_V2 0 +#define BIT_MASK_PS_TIMER_A_V2 0xffffffffL +#define BIT_PS_TIMER_A_V2(x) \ + (((x) & BIT_MASK_PS_TIMER_A_V2) << BIT_SHIFT_PS_TIMER_A_V2) +#define BITS_PS_TIMER_A_V2 (BIT_MASK_PS_TIMER_A_V2 << BIT_SHIFT_PS_TIMER_A_V2) +#define BIT_CLEAR_PS_TIMER_A_V2(x) ((x) & (~BITS_PS_TIMER_A_V2)) +#define BIT_GET_PS_TIMER_A_V2(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_V2) & BIT_MASK_PS_TIMER_A_V2) +#define BIT_SET_PS_TIMER_A_V2(x, v) \ + (BIT_CLEAR_PS_TIMER_A_V2(x) | BIT_PS_TIMER_A_V2(v)) -/* 2 REG_SCH_TXCMD (Offset 0x05F8) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_SCH_TXCMD 0 -#define BIT_MASK_SCH_TXCMD 0xffffffffL -#define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD) -#define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD) +/* 2 REG_TXOP_LIMIT_CTRL (Offset 0x052C) */ +#define BIT_SHIFT_TXOP_LMT_PKT_NUM 0 +#define BIT_MASK_TXOP_LMT_PKT_NUM 0x3f +#define BIT_TXOP_LMT_PKT_NUM(x) \ + (((x) & BIT_MASK_TXOP_LMT_PKT_NUM) << BIT_SHIFT_TXOP_LMT_PKT_NUM) +#define BITS_TXOP_LMT_PKT_NUM \ + (BIT_MASK_TXOP_LMT_PKT_NUM << BIT_SHIFT_TXOP_LMT_PKT_NUM) +#define BIT_CLEAR_TXOP_LMT_PKT_NUM(x) ((x) & (~BITS_TXOP_LMT_PKT_NUM)) +#define BIT_GET_TXOP_LMT_PKT_NUM(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM) & BIT_MASK_TXOP_LMT_PKT_NUM) +#define BIT_SET_TXOP_LMT_PKT_NUM(x, v) \ + (BIT_CLEAR_TXOP_LMT_PKT_NUM(x) | BIT_TXOP_LMT_PKT_NUM(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_PS_TIMER_B_V2 (Offset 0x0534) */ +#define BIT_FTM_PTT_TSF_R2T_SEL_V1 BIT(24) -/* 2 REG_WMAC_CR (Offset 0x0600) */ +#endif -#define BIT_APSDOFF_STATUS BIT(7) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_CCA_TXEN_CNT (Offset 0x0534) */ +#define BIT_ENABLE_STOP_UPDATE_NAV BIT(21) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_WMAC_CR (Offset 0x0600) */ +/* 2 REG_PS_TIMER_B_V2 (Offset 0x0534) */ -#define BIT_APSDOFF BIT(6) +#define BIT_TBTT_DIG BIT(20) +#define BIT_FTM_PTT_TSF_T2R_SEL_V1 BIT(20) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_CCA_TXEN_CNT (Offset 0x0534) */ +#define BIT_ENABLE_GEN_RANDON_SLOT_TX BIT(20) +#define BIT_ENABLE_RANDOM_SHIFT_TX BIT(19) +#define BIT_ENABLE_EDCA_REF_FUNCTION BIT(18) -/* 2 REG_WMAC_CR (Offset 0x0600) */ +#endif -#define BIT_STANDBY_STATUS BIT(5) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_CCA_TXEN_CNT (Offset 0x0534) */ +#define BIT_CCA_TXEN_CNT_SWITCH BIT(17) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_WMAC_CR (Offset 0x0600) */ +/* 2 REG_PS_TIMER_B_V2 (Offset 0x0534) */ -#define BIT_IC_MACPHY_M BIT(0) +#define BIT_FTM_PTT_TSF_SEL_V1 BIT(16) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CCA_TXEN_CNT (Offset 0x0534) */ +#define BIT_CCA_TXEN_CNT_EN BIT(16) -/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ - -#define BIT_FWEN BIT(7) +#define BIT_SHIFT_CCA_TXEN_BIG_CNT 8 +#define BIT_MASK_CCA_TXEN_BIG_CNT 0xff +#define BIT_CCA_TXEN_BIG_CNT(x) \ + (((x) & BIT_MASK_CCA_TXEN_BIG_CNT) << BIT_SHIFT_CCA_TXEN_BIG_CNT) +#define BITS_CCA_TXEN_BIG_CNT \ + (BIT_MASK_CCA_TXEN_BIG_CNT << BIT_SHIFT_CCA_TXEN_BIG_CNT) +#define BIT_CLEAR_CCA_TXEN_BIG_CNT(x) ((x) & (~BITS_CCA_TXEN_BIG_CNT)) +#define BIT_GET_CCA_TXEN_BIG_CNT(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT) & BIT_MASK_CCA_TXEN_BIG_CNT) +#define BIT_SET_CCA_TXEN_BIG_CNT(x, v) \ + (BIT_CLEAR_CCA_TXEN_BIG_CNT(x) | BIT_CCA_TXEN_BIG_CNT(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PS_TIMER_B_V2 (Offset 0x0534) */ - -/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ - -#define BIT_PHYSTS_PKT_CTRL BIT(6) +#define BIT_SHIFT_PS_TIMER_B_V2 0 +#define BIT_MASK_PS_TIMER_B_V2 0xffffffffL +#define BIT_PS_TIMER_B_V2(x) \ + (((x) & BIT_MASK_PS_TIMER_B_V2) << BIT_SHIFT_PS_TIMER_B_V2) +#define BITS_PS_TIMER_B_V2 (BIT_MASK_PS_TIMER_B_V2 << BIT_SHIFT_PS_TIMER_B_V2) +#define BIT_CLEAR_PS_TIMER_B_V2(x) ((x) & (~BITS_PS_TIMER_B_V2)) +#define BIT_GET_PS_TIMER_B_V2(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_V2) & BIT_MASK_PS_TIMER_B_V2) +#define BIT_SET_PS_TIMER_B_V2(x, v) \ + (BIT_CLEAR_PS_TIMER_B_V2(x) | BIT_PS_TIMER_B_V2(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CCA_TXEN_CNT (Offset 0x0534) */ +#define BIT_SHIFT_CCA_TXEN_SMALL_CNT 0 +#define BIT_MASK_CCA_TXEN_SMALL_CNT 0xff +#define BIT_CCA_TXEN_SMALL_CNT(x) \ + (((x) & BIT_MASK_CCA_TXEN_SMALL_CNT) << BIT_SHIFT_CCA_TXEN_SMALL_CNT) +#define BITS_CCA_TXEN_SMALL_CNT \ + (BIT_MASK_CCA_TXEN_SMALL_CNT << BIT_SHIFT_CCA_TXEN_SMALL_CNT) +#define BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) ((x) & (~BITS_CCA_TXEN_SMALL_CNT)) +#define BIT_GET_CCA_TXEN_SMALL_CNT(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT) & BIT_MASK_CCA_TXEN_SMALL_CNT) +#define BIT_SET_CCA_TXEN_SMALL_CNT(x, v) \ + (BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) | BIT_CCA_TXEN_SMALL_CNT(v)) -/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ +#endif -#define BIT_APPHDR_MIDSRCH_FAIL BIT(4) -#define BIT_FWPARSING_EN BIT(3) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_APPEND_MHDR_LEN 0 -#define BIT_MASK_APPEND_MHDR_LEN 0x7 -#define BIT_APPEND_MHDR_LEN(x) (((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN) -#define BIT_GET_APPEND_MHDR_LEN(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN) +/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ +#define BIT_SHIFT_BK_QUEUE_THR 24 +#define BIT_MASK_BK_QUEUE_THR 0xff +#define BIT_BK_QUEUE_THR(x) \ + (((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR) +#define BITS_BK_QUEUE_THR (BIT_MASK_BK_QUEUE_THR << BIT_SHIFT_BK_QUEUE_THR) +#define BIT_CLEAR_BK_QUEUE_THR(x) ((x) & (~BITS_BK_QUEUE_THR)) +#define BIT_GET_BK_QUEUE_THR(x) \ + (((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR) +#define BIT_SET_BK_QUEUE_THR(x, v) \ + (BIT_CLEAR_BK_QUEUE_THR(x) | BIT_BK_QUEUE_THR(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_BK 24 +#define BIT_MASK_MAX_INTER_COLLISION_BK 0xff +#define BIT_MAX_INTER_COLLISION_BK(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BK) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BK) +#define BITS_MAX_INTER_COLLISION_BK \ + (BIT_MASK_MAX_INTER_COLLISION_BK << BIT_SHIFT_MAX_INTER_COLLISION_BK) +#define BIT_CLEAR_MAX_INTER_COLLISION_BK(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BK)) +#define BIT_GET_MAX_INTER_COLLISION_BK(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK) & \ + BIT_MASK_MAX_INTER_COLLISION_BK) +#define BIT_SET_MAX_INTER_COLLISION_BK(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BK(x) | BIT_MAX_INTER_COLLISION_BK(v)) -/* 2 REG_FW_STS_FILTER (Offset 0x0602) */ +#endif -#define BIT_DATA_FW_STS_FILTER BIT(2) -#define BIT_CTRL_FW_STS_FILTER BIT(1) -#define BIT_MGNT_FW_STS_FILTER BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ +#define BIT_SHIFT_BE_QUEUE_THR 16 +#define BIT_MASK_BE_QUEUE_THR 0xff +#define BIT_BE_QUEUE_THR(x) \ + (((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR) +#define BITS_BE_QUEUE_THR (BIT_MASK_BE_QUEUE_THR << BIT_SHIFT_BE_QUEUE_THR) +#define BIT_CLEAR_BE_QUEUE_THR(x) ((x) & (~BITS_BE_QUEUE_THR)) +#define BIT_GET_BE_QUEUE_THR(x) \ + (((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR) +#define BIT_SET_BE_QUEUE_THR(x, v) \ + (BIT_CLEAR_BE_QUEUE_THR(x) | BIT_BE_QUEUE_THR(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TCR (Offset 0x0604) */ +/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ -#define BIT_WMAC_EN_RTS_ADDR BIT(31) -#define BIT_WMAC_DISABLE_CCK BIT(30) -#define BIT_WMAC_RAW_LEN BIT(29) -#define BIT_WMAC_NOTX_IN_RXNDP BIT(28) -#define BIT_WMAC_EN_EOF BIT(27) -#define BIT_WMAC_BF_SEL BIT(26) -#define BIT_WMAC_ANTMODE_SEL BIT(25) +#define BIT_SHIFT_MAX_INTER_COLLISION_BE 16 +#define BIT_MASK_MAX_INTER_COLLISION_BE 0xff +#define BIT_MAX_INTER_COLLISION_BE(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BE) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BE) +#define BITS_MAX_INTER_COLLISION_BE \ + (BIT_MASK_MAX_INTER_COLLISION_BE << BIT_SHIFT_MAX_INTER_COLLISION_BE) +#define BIT_CLEAR_MAX_INTER_COLLISION_BE(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BE)) +#define BIT_GET_MAX_INTER_COLLISION_BE(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE) & \ + BIT_MASK_MAX_INTER_COLLISION_BE) +#define BIT_SET_MAX_INTER_COLLISION_BE(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BE(x) | BIT_MAX_INTER_COLLISION_BE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ +#define BIT_SHIFT_VI_QUEUE_THR 8 +#define BIT_MASK_VI_QUEUE_THR 0xff +#define BIT_VI_QUEUE_THR(x) \ + (((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR) +#define BITS_VI_QUEUE_THR (BIT_MASK_VI_QUEUE_THR << BIT_SHIFT_VI_QUEUE_THR) +#define BIT_CLEAR_VI_QUEUE_THR(x) ((x) & (~BITS_VI_QUEUE_THR)) +#define BIT_GET_VI_QUEUE_THR(x) \ + (((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR) +#define BIT_SET_VI_QUEUE_THR(x, v) \ + (BIT_CLEAR_VI_QUEUE_THR(x) | BIT_VI_QUEUE_THR(v)) -/* 2 REG_TCR (Offset 0x0604) */ +#endif -#define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_VI 8 +#define BIT_MASK_MAX_INTER_COLLISION_VI 0xff +#define BIT_MAX_INTER_COLLISION_VI(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VI) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VI) +#define BITS_MAX_INTER_COLLISION_VI \ + (BIT_MASK_MAX_INTER_COLLISION_VI << BIT_SHIFT_MAX_INTER_COLLISION_VI) +#define BIT_CLEAR_MAX_INTER_COLLISION_VI(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VI)) +#define BIT_GET_MAX_INTER_COLLISION_VI(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI) & \ + BIT_MASK_MAX_INTER_COLLISION_VI) +#define BIT_SET_MAX_INTER_COLLISION_VI(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VI(x) | BIT_MAX_INTER_COLLISION_VI(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_TCR (Offset 0x0604) */ +/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ -#define BIT_RXLEN_SEL BIT(24) +#define BIT_SHIFT_VO_QUEUE_THR 0 +#define BIT_MASK_VO_QUEUE_THR 0xff +#define BIT_VO_QUEUE_THR(x) \ + (((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR) +#define BITS_VO_QUEUE_THR (BIT_MASK_VO_QUEUE_THR << BIT_SHIFT_VO_QUEUE_THR) +#define BIT_CLEAR_VO_QUEUE_THR(x) ((x) & (~BITS_VO_QUEUE_THR)) +#define BIT_GET_VO_QUEUE_THR(x) \ + (((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR) +#define BIT_SET_VO_QUEUE_THR(x, v) \ + (BIT_CLEAR_VO_QUEUE_THR(x) | BIT_VO_QUEUE_THR(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_VO 0 +#define BIT_MASK_MAX_INTER_COLLISION_VO 0xff +#define BIT_MAX_INTER_COLLISION_VO(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VO) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VO) +#define BITS_MAX_INTER_COLLISION_VO \ + (BIT_MASK_MAX_INTER_COLLISION_VO << BIT_SHIFT_MAX_INTER_COLLISION_VO) +#define BIT_CLEAR_MAX_INTER_COLLISION_VO(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VO)) +#define BIT_GET_MAX_INTER_COLLISION_VO(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO) & \ + BIT_MASK_MAX_INTER_COLLISION_VO) +#define BIT_SET_MAX_INTER_COLLISION_VO(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VO(x) | BIT_MAX_INTER_COLLISION_VO(v)) -/* 2 REG_TCR (Offset 0x0604) */ +#endif -#define BIT_WMAC_SMOOTH_VAL BIT(23) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_QUEUE_INCOL_EN BIT(16) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TCR (Offset 0x0604) */ +/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ -#define BIT_UNDERFLOWEN_CMPLEN_SEL BIT(21) +#define BIT_MAX_INTER_COLLISION_EN BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_SHIFT_BK_TRIGGER_NUM_V1 12 +#define BIT_MASK_BK_TRIGGER_NUM_V1 0xf +#define BIT_BK_TRIGGER_NUM_V1(x) \ + (((x) & BIT_MASK_BK_TRIGGER_NUM_V1) << BIT_SHIFT_BK_TRIGGER_NUM_V1) +#define BITS_BK_TRIGGER_NUM_V1 \ + (BIT_MASK_BK_TRIGGER_NUM_V1 << BIT_SHIFT_BK_TRIGGER_NUM_V1) +#define BIT_CLEAR_BK_TRIGGER_NUM_V1(x) ((x) & (~BITS_BK_TRIGGER_NUM_V1)) +#define BIT_GET_BK_TRIGGER_NUM_V1(x) \ + (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1) & BIT_MASK_BK_TRIGGER_NUM_V1) +#define BIT_SET_BK_TRIGGER_NUM_V1(x, v) \ + (BIT_CLEAR_BK_TRIGGER_NUM_V1(x) | BIT_BK_TRIGGER_NUM_V1(v)) -/* 2 REG_TCR (Offset 0x0604) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TSFT_CMP 20 -#define BIT_MASK_TSFT_CMP 0xf -#define BIT_TSFT_CMP(x) (((x) & BIT_MASK_TSFT_CMP) << BIT_SHIFT_TSFT_CMP) -#define BIT_GET_TSFT_CMP(x) (((x) >> BIT_SHIFT_TSFT_CMP) & BIT_MASK_TSFT_CMP) +/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK 12 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BK(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) +#define BITS_MAX_INTER_COLLISION_CNT_BK \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BK \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BK(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BK) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BK(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BK(v)) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_SHIFT_BE_TRIGGER_NUM 12 +#define BIT_MASK_BE_TRIGGER_NUM 0xf +#define BIT_BE_TRIGGER_NUM(x) \ + (((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM) +#define BITS_BE_TRIGGER_NUM \ + (BIT_MASK_BE_TRIGGER_NUM << BIT_SHIFT_BE_TRIGGER_NUM) +#define BIT_CLEAR_BE_TRIGGER_NUM(x) ((x) & (~BITS_BE_TRIGGER_NUM)) +#define BIT_GET_BE_TRIGGER_NUM(x) \ + (((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM) +#define BIT_SET_BE_TRIGGER_NUM(x, v) \ + (BIT_CLEAR_BE_TRIGGER_NUM(x) | BIT_BE_TRIGGER_NUM(v)) -/* 2 REG_TCR (Offset 0x0604) */ +#endif -#define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_SHIFT_BE_TRIGGER_NUM_V1 8 +#define BIT_MASK_BE_TRIGGER_NUM_V1 0xf +#define BIT_BE_TRIGGER_NUM_V1(x) \ + (((x) & BIT_MASK_BE_TRIGGER_NUM_V1) << BIT_SHIFT_BE_TRIGGER_NUM_V1) +#define BITS_BE_TRIGGER_NUM_V1 \ + (BIT_MASK_BE_TRIGGER_NUM_V1 << BIT_SHIFT_BE_TRIGGER_NUM_V1) +#define BIT_CLEAR_BE_TRIGGER_NUM_V1(x) ((x) & (~BITS_BE_TRIGGER_NUM_V1)) +#define BIT_GET_BE_TRIGGER_NUM_V1(x) \ + (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1) & BIT_MASK_BE_TRIGGER_NUM_V1) +#define BIT_SET_BE_TRIGGER_NUM_V1(x, v) \ + (BIT_CLEAR_BE_TRIGGER_NUM_V1(x) | BIT_BE_TRIGGER_NUM_V1(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TCR (Offset 0x0604) */ +/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ -#define BIT_WMAC_TCR_EN_20MST BIT(19) -#define BIT_WMAC_DIS_SIGTA BIT(18) -#define BIT_WMAC_DIS_A2B0 BIT(17) -#define BIT_WMAC_MSK_SIGBCRC BIT(16) +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE 8 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BE(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) +#define BITS_MAX_INTER_COLLISION_CNT_BE \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BE \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BE(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BE) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BE(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BE(v)) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_SHIFT_BK_TRIGGER_NUM 8 +#define BIT_MASK_BK_TRIGGER_NUM 0xf +#define BIT_BK_TRIGGER_NUM(x) \ + (((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM) +#define BITS_BK_TRIGGER_NUM \ + (BIT_MASK_BK_TRIGGER_NUM << BIT_SHIFT_BK_TRIGGER_NUM) +#define BIT_CLEAR_BK_TRIGGER_NUM(x) ((x) & (~BITS_BK_TRIGGER_NUM)) +#define BIT_GET_BK_TRIGGER_NUM(x) \ + (((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM) +#define BIT_SET_BK_TRIGGER_NUM(x, v) \ + (BIT_CLEAR_BK_TRIGGER_NUM(x) | BIT_BK_TRIGGER_NUM(v)) -/* 2 REG_TCR (Offset 0x0604) */ +#endif -#define BIT_WMAC_TCR_ERRSTEN_3 BIT(15) -#define BIT_WMAC_TCR_ERRSTEN_2 BIT(14) -#define BIT_WMAC_TCR_ERRSTEN_1 BIT(13) -#define BIT_WMAC_TCR_ERRSTEN_0 BIT(12) -#define BIT_WMAC_TCR_TXSK_PERPKT BIT(11) -#define BIT_ICV BIT(10) -#define BIT_CFEND_FORMAT BIT(9) -#define BIT_CRC BIT(8) -#define BIT_PWRBIT_OW_EN BIT(7) -#define BIT_PWR_ST BIT(6) -#define BIT_WMAC_TCR_UPD_TIMIE BIT(5) -#define BIT_WMAC_TCR_UPD_HGQMD BIT(4) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_SHIFT_VI_TRIGGER_NUM 4 +#define BIT_MASK_VI_TRIGGER_NUM 0xf +#define BIT_VI_TRIGGER_NUM(x) \ + (((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM) +#define BITS_VI_TRIGGER_NUM \ + (BIT_MASK_VI_TRIGGER_NUM << BIT_SHIFT_VI_TRIGGER_NUM) +#define BIT_CLEAR_VI_TRIGGER_NUM(x) ((x) & (~BITS_VI_TRIGGER_NUM)) +#define BIT_GET_VI_TRIGGER_NUM(x) \ + (((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM) +#define BIT_SET_VI_TRIGGER_NUM(x, v) \ + (BIT_CLEAR_VI_TRIGGER_NUM(x) | BIT_VI_TRIGGER_NUM(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_TCR (Offset 0x0604) */ +/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ -#define BIT_VHTSIGA1_TXPS BIT(3) +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI 4 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VI(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) +#define BITS_MAX_INTER_COLLISION_CNT_VI \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VI \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VI(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VI) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VI(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VI(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ +#define BIT_SHIFT_VO_TRIGGER_NUM 0 +#define BIT_MASK_VO_TRIGGER_NUM 0xf +#define BIT_VO_TRIGGER_NUM(x) \ + (((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM) +#define BITS_VO_TRIGGER_NUM \ + (BIT_MASK_VO_TRIGGER_NUM << BIT_SHIFT_VO_TRIGGER_NUM) +#define BIT_CLEAR_VO_TRIGGER_NUM(x) ((x) & (~BITS_VO_TRIGGER_NUM)) +#define BIT_GET_VO_TRIGGER_NUM(x) \ + (((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM) +#define BIT_SET_VO_TRIGGER_NUM(x, v) \ + (BIT_CLEAR_VO_TRIGGER_NUM(x) | BIT_VO_TRIGGER_NUM(v)) -/* 2 REG_TCR (Offset 0x0604) */ +#endif -#define BIT_PAD_SEL BIT(2) -#define BIT_DIS_GCLK BIT(1) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */ +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO 0 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VO(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) +#define BITS_MAX_INTER_COLLISION_CNT_VO \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VO \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VO(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VO) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VO(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VO(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_TCR (Offset 0x0604) */ +/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ -#define BIT_TSFRST BIT(0) +#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 +#define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff +#define BIT_TBTT_HOLD_TIME_AP(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP) +#define BITS_TBTT_HOLD_TIME_AP \ + (BIT_MASK_TBTT_HOLD_TIME_AP << BIT_SHIFT_TBTT_HOLD_TIME_AP) +#define BIT_CLEAR_TBTT_HOLD_TIME_AP(x) ((x) & (~BITS_TBTT_HOLD_TIME_AP)) +#define BIT_GET_TBTT_HOLD_TIME_AP(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP) +#define BIT_SET_TBTT_HOLD_TIME_AP(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_AP(x) | BIT_TBTT_HOLD_TIME_AP(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ +#define BIT_SHIFT_TBTT_HOLD_TIME_INFRA 4 +#define BIT_MASK_TBTT_HOLD_TIME_INFRA 0xf +#define BIT_TBTT_HOLD_TIME_INFRA(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_INFRA) \ + << BIT_SHIFT_TBTT_HOLD_TIME_INFRA) +#define BITS_TBTT_HOLD_TIME_INFRA \ + (BIT_MASK_TBTT_HOLD_TIME_INFRA << BIT_SHIFT_TBTT_HOLD_TIME_INFRA) +#define BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) ((x) & (~BITS_TBTT_HOLD_TIME_INFRA)) +#define BIT_GET_TBTT_HOLD_TIME_INFRA(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_INFRA) & \ + BIT_MASK_TBTT_HOLD_TIME_INFRA) +#define BIT_SET_TBTT_HOLD_TIME_INFRA(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) | BIT_TBTT_HOLD_TIME_INFRA(v)) -/* 2 REG_TCR (Offset 0x0604) */ +#endif -#define BIT_R_WMAC_TCR_LSIG BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_P2PPS_STATE (Offset 0x0543) */ +#define BIT_POWER_STATE BIT(7) +#define BIT_CTWINDOW_ON BIT(6) +#define BIT_BEACON_AREA_ON BIT(5) +#define BIT_CTWIN_EARLY_DISTX BIT(4) +#define BIT_NOA1_OFF_PERIOD BIT(3) +#define BIT_FORCE_DOZE1 BIT(2) +#define BIT_NOA0_OFF_PERIOD BIT(1) +#define BIT_FORCE_DOZE0 BIT(0) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_RD_NAV_NXT (Offset 0x0544) */ +#define BIT_SHIFT_RD_NAV_PROT_NXT 0 +#define BIT_MASK_RD_NAV_PROT_NXT 0xffff +#define BIT_RD_NAV_PROT_NXT(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT) +#define BITS_RD_NAV_PROT_NXT \ + (BIT_MASK_RD_NAV_PROT_NXT << BIT_SHIFT_RD_NAV_PROT_NXT) +#define BIT_CLEAR_RD_NAV_PROT_NXT(x) ((x) & (~BITS_RD_NAV_PROT_NXT)) +#define BIT_GET_RD_NAV_PROT_NXT(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT) +#define BIT_SET_RD_NAV_PROT_NXT(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT(x) | BIT_RD_NAV_PROT_NXT(v)) -/* 2 REG_RCR (Offset 0x0608) */ +/* 2 REG_NAV_PROT_LEN (Offset 0x0546) */ -#define BIT_APP_FCS BIT(31) -#define BIT_APP_MIC BIT(30) -#define BIT_APP_ICV BIT(29) -#define BIT_APP_PHYSTS BIT(28) -#define BIT_APP_BASSN BIT(27) +#define BIT_SHIFT_NAV_PROT_LEN 0 +#define BIT_MASK_NAV_PROT_LEN 0xffff +#define BIT_NAV_PROT_LEN(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN) +#define BITS_NAV_PROT_LEN (BIT_MASK_NAV_PROT_LEN << BIT_SHIFT_NAV_PROT_LEN) +#define BIT_CLEAR_NAV_PROT_LEN(x) ((x) & (~BITS_NAV_PROT_LEN)) +#define BIT_GET_NAV_PROT_LEN(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN) +#define BIT_SET_NAV_PROT_LEN(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN(x) | BIT_NAV_PROT_LEN(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FTM_CTRL (Offset 0x0548) */ +#define BIT_SHIFT_FTM_TSF_R2T_PORT 22 +#define BIT_MASK_FTM_TSF_R2T_PORT 0x7 +#define BIT_FTM_TSF_R2T_PORT(x) \ + (((x) & BIT_MASK_FTM_TSF_R2T_PORT) << BIT_SHIFT_FTM_TSF_R2T_PORT) +#define BITS_FTM_TSF_R2T_PORT \ + (BIT_MASK_FTM_TSF_R2T_PORT << BIT_SHIFT_FTM_TSF_R2T_PORT) +#define BIT_CLEAR_FTM_TSF_R2T_PORT(x) ((x) & (~BITS_FTM_TSF_R2T_PORT)) +#define BIT_GET_FTM_TSF_R2T_PORT(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT) & BIT_MASK_FTM_TSF_R2T_PORT) +#define BIT_SET_FTM_TSF_R2T_PORT(x, v) \ + (BIT_CLEAR_FTM_TSF_R2T_PORT(x) | BIT_FTM_TSF_R2T_PORT(v)) -/* 2 REG_RCR (Offset 0x0608) */ +#endif -#define BIT_VHT_DACK BIT(26) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FTM_PTT (Offset 0x0548) */ +#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL 22 +#define BIT_MASK_FTM_PTT_TSF_R2T_SEL 0x7 +#define BIT_FTM_PTT_TSF_R2T_SEL(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL) << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) +#define BITS_FTM_PTT_TSF_R2T_SEL \ + (BIT_MASK_FTM_PTT_TSF_R2T_SEL << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) +#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL)) +#define BIT_GET_FTM_PTT_TSF_R2T_SEL(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) & BIT_MASK_FTM_PTT_TSF_R2T_SEL) +#define BIT_SET_FTM_PTT_TSF_R2T_SEL(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) | BIT_FTM_PTT_TSF_R2T_SEL(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_RCR (Offset 0x0608) */ +/* 2 REG_FTM_CTRL (Offset 0x0548) */ -#define BIT_TCPOFLD_EN BIT(25) -#define BIT_ENMBID BIT(24) -#define BIT_LSIGEN BIT(23) -#define BIT_MFBEN BIT(22) -#define BIT_DISCHKPPDLLEN BIT(21) -#define BIT_PKTCTL_DLEN BIT(20) -#define BIT_TIM_PARSER_EN BIT(18) -#define BIT_BC_MD_EN BIT(17) -#define BIT_UC_MD_EN BIT(16) -#define BIT_RXSK_PERPKT BIT(15) -#define BIT_HTC_LOC_CTRL BIT(14) +#define BIT_SHIFT_FTM_TSF_T2R_PORT 19 +#define BIT_MASK_FTM_TSF_T2R_PORT 0x7 +#define BIT_FTM_TSF_T2R_PORT(x) \ + (((x) & BIT_MASK_FTM_TSF_T2R_PORT) << BIT_SHIFT_FTM_TSF_T2R_PORT) +#define BITS_FTM_TSF_T2R_PORT \ + (BIT_MASK_FTM_TSF_T2R_PORT << BIT_SHIFT_FTM_TSF_T2R_PORT) +#define BIT_CLEAR_FTM_TSF_T2R_PORT(x) ((x) & (~BITS_FTM_TSF_T2R_PORT)) +#define BIT_GET_FTM_TSF_T2R_PORT(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT) & BIT_MASK_FTM_TSF_T2R_PORT) +#define BIT_SET_FTM_TSF_T2R_PORT(x, v) \ + (BIT_CLEAR_FTM_TSF_T2R_PORT(x) | BIT_FTM_TSF_T2R_PORT(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTM_PTT (Offset 0x0548) */ +#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL 19 +#define BIT_MASK_FTM_PTT_TSF_T2R_SEL 0x7 +#define BIT_FTM_PTT_TSF_T2R_SEL(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL) << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) +#define BITS_FTM_PTT_TSF_T2R_SEL \ + (BIT_MASK_FTM_PTT_TSF_T2R_SEL << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) +#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL)) +#define BIT_GET_FTM_PTT_TSF_T2R_SEL(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) & BIT_MASK_FTM_PTT_TSF_T2R_SEL) +#define BIT_SET_FTM_PTT_TSF_T2R_SEL(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) | BIT_FTM_PTT_TSF_T2R_SEL(v)) -/* 2 REG_RCR (Offset 0x0608) */ +#endif -#define BIT_AMF BIT(13) -#define BIT_ACF BIT(12) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_FTM_CTRL (Offset 0x0548) */ +#define BIT_SHIFT_FTM_PTT_PORT 16 +#define BIT_MASK_FTM_PTT_PORT 0x7 +#define BIT_FTM_PTT_PORT(x) \ + (((x) & BIT_MASK_FTM_PTT_PORT) << BIT_SHIFT_FTM_PTT_PORT) +#define BITS_FTM_PTT_PORT (BIT_MASK_FTM_PTT_PORT << BIT_SHIFT_FTM_PTT_PORT) +#define BIT_CLEAR_FTM_PTT_PORT(x) ((x) & (~BITS_FTM_PTT_PORT)) +#define BIT_GET_FTM_PTT_PORT(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_PORT) & BIT_MASK_FTM_PTT_PORT) +#define BIT_SET_FTM_PTT_PORT(x, v) \ + (BIT_CLEAR_FTM_PTT_PORT(x) | BIT_FTM_PTT_PORT(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RCR (Offset 0x0608) */ +/* 2 REG_FTM_PTT (Offset 0x0548) */ -#define BIT_RPFM_CAM_ENABLE BIT(12) +#define BIT_SHIFT_FTM_PTT_TSF_SEL 16 +#define BIT_MASK_FTM_PTT_TSF_SEL 0x7 +#define BIT_FTM_PTT_TSF_SEL(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_SEL) << BIT_SHIFT_FTM_PTT_TSF_SEL) +#define BITS_FTM_PTT_TSF_SEL \ + (BIT_MASK_FTM_PTT_TSF_SEL << BIT_SHIFT_FTM_PTT_TSF_SEL) +#define BIT_CLEAR_FTM_PTT_TSF_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_SEL)) +#define BIT_GET_FTM_PTT_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL) & BIT_MASK_FTM_PTT_TSF_SEL) +#define BIT_SET_FTM_PTT_TSF_SEL(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_SEL(x) | BIT_FTM_PTT_TSF_SEL(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTM_CTRL (Offset 0x0548) */ +#define BIT_SHIFT_FTM_PTT 0 +#define BIT_MASK_FTM_PTT 0xffff +#define BIT_FTM_PTT(x) (((x) & BIT_MASK_FTM_PTT) << BIT_SHIFT_FTM_PTT) +#define BITS_FTM_PTT (BIT_MASK_FTM_PTT << BIT_SHIFT_FTM_PTT) +#define BIT_CLEAR_FTM_PTT(x) ((x) & (~BITS_FTM_PTT)) +#define BIT_GET_FTM_PTT(x) (((x) >> BIT_SHIFT_FTM_PTT) & BIT_MASK_FTM_PTT) +#define BIT_SET_FTM_PTT(x, v) (BIT_CLEAR_FTM_PTT(x) | BIT_FTM_PTT(v)) -/* 2 REG_RCR (Offset 0x0608) */ +#endif -#define BIT_ADF BIT(11) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_FTM_PTT (Offset 0x0548) */ +#define BIT_SHIFT_FTM_PTT_VALUE 0 +#define BIT_MASK_FTM_PTT_VALUE 0xffff +#define BIT_FTM_PTT_VALUE(x) \ + (((x) & BIT_MASK_FTM_PTT_VALUE) << BIT_SHIFT_FTM_PTT_VALUE) +#define BITS_FTM_PTT_VALUE (BIT_MASK_FTM_PTT_VALUE << BIT_SHIFT_FTM_PTT_VALUE) +#define BIT_CLEAR_FTM_PTT_VALUE(x) ((x) & (~BITS_FTM_PTT_VALUE)) +#define BIT_GET_FTM_PTT_VALUE(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_VALUE) & BIT_MASK_FTM_PTT_VALUE) +#define BIT_SET_FTM_PTT_VALUE(x, v) \ + (BIT_CLEAR_FTM_PTT_VALUE(x) | BIT_FTM_PTT_VALUE(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_RCR (Offset 0x0608) */ +/* 2 REG_FTM_TSF_CNT (Offset 0x054C) */ -#define BIT_TA_BCN BIT(11) +#define BIT_SHIFT_FTM_TSF_R2T 16 +#define BIT_MASK_FTM_TSF_R2T 0xffff +#define BIT_FTM_TSF_R2T(x) \ + (((x) & BIT_MASK_FTM_TSF_R2T) << BIT_SHIFT_FTM_TSF_R2T) +#define BITS_FTM_TSF_R2T (BIT_MASK_FTM_TSF_R2T << BIT_SHIFT_FTM_TSF_R2T) +#define BIT_CLEAR_FTM_TSF_R2T(x) ((x) & (~BITS_FTM_TSF_R2T)) +#define BIT_GET_FTM_TSF_R2T(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_R2T) & BIT_MASK_FTM_TSF_R2T) +#define BIT_SET_FTM_TSF_R2T(x, v) \ + (BIT_CLEAR_FTM_TSF_R2T(x) | BIT_FTM_TSF_R2T(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FTM_TSF (Offset 0x054C) */ +#define BIT_SHIFT_FTM_T2_TSF 16 +#define BIT_MASK_FTM_T2_TSF 0xffff +#define BIT_FTM_T2_TSF(x) (((x) & BIT_MASK_FTM_T2_TSF) << BIT_SHIFT_FTM_T2_TSF) +#define BITS_FTM_T2_TSF (BIT_MASK_FTM_T2_TSF << BIT_SHIFT_FTM_T2_TSF) +#define BIT_CLEAR_FTM_T2_TSF(x) ((x) & (~BITS_FTM_T2_TSF)) +#define BIT_GET_FTM_T2_TSF(x) \ + (((x) >> BIT_SHIFT_FTM_T2_TSF) & BIT_MASK_FTM_T2_TSF) +#define BIT_SET_FTM_T2_TSF(x, v) (BIT_CLEAR_FTM_T2_TSF(x) | BIT_FTM_T2_TSF(v)) -/* 2 REG_RCR (Offset 0x0608) */ +#endif -#define BIT_DISDECMYPKT BIT(10) -#define BIT_AICV BIT(9) -#define BIT_ACRC32 BIT(8) -#define BIT_CBSSID_BCN BIT(7) -#define BIT_CBSSID_DATA BIT(6) -#define BIT_APWRMGT BIT(5) -#define BIT_ADD3 BIT(4) -#define BIT_AB BIT(3) -#define BIT_AM BIT(2) -#define BIT_APM BIT(1) -#define BIT_AAP BIT(0) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_RX_PKT_LIMIT (Offset 0x060C) */ +/* 2 REG_FTM_TSF_CNT (Offset 0x054C) */ +#define BIT_SHIFT_FTM_TSF_T2R 0 +#define BIT_MASK_FTM_TSF_T2R 0xffff +#define BIT_FTM_TSF_T2R(x) \ + (((x) & BIT_MASK_FTM_TSF_T2R) << BIT_SHIFT_FTM_TSF_T2R) +#define BITS_FTM_TSF_T2R (BIT_MASK_FTM_TSF_T2R << BIT_SHIFT_FTM_TSF_T2R) +#define BIT_CLEAR_FTM_TSF_T2R(x) ((x) & (~BITS_FTM_TSF_T2R)) +#define BIT_GET_FTM_TSF_T2R(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_T2R) & BIT_MASK_FTM_TSF_T2R) +#define BIT_SET_FTM_TSF_T2R(x, v) \ + (BIT_CLEAR_FTM_TSF_T2R(x) | BIT_FTM_TSF_T2R(v)) -#define BIT_SHIFT_RXPKTLMT 0 -#define BIT_MASK_RXPKTLMT 0x3f -#define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT) -#define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RX_DLK_TIME (Offset 0x060D) */ +/* 2 REG_FTM_TSF (Offset 0x054C) */ +#define BIT_SHIFT_FTM_T1_TSF 0 +#define BIT_MASK_FTM_T1_TSF 0xffff +#define BIT_FTM_T1_TSF(x) (((x) & BIT_MASK_FTM_T1_TSF) << BIT_SHIFT_FTM_T1_TSF) +#define BITS_FTM_T1_TSF (BIT_MASK_FTM_T1_TSF << BIT_SHIFT_FTM_T1_TSF) +#define BIT_CLEAR_FTM_T1_TSF(x) ((x) & (~BITS_FTM_T1_TSF)) +#define BIT_GET_FTM_T1_TSF(x) \ + (((x) >> BIT_SHIFT_FTM_T1_TSF) & BIT_MASK_FTM_T1_TSF) +#define BIT_SET_FTM_T1_TSF(x, v) (BIT_CLEAR_FTM_T1_TSF(x) | BIT_FTM_T1_TSF(v)) -#define BIT_SHIFT_RX_DLK_TIME 0 -#define BIT_MASK_RX_DLK_TIME 0xff -#define BIT_RX_DLK_TIME(x) (((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME) -#define BIT_GET_RX_DLK_TIME(x) (((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BCN_CTRL (Offset 0x0550) */ +#define BIT_P0_EN_TXBCN_RPT BIT(5) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +/* 2 REG_BCN_CTRL (Offset 0x0550) */ -#define BIT_DATA_RPFM15EN BIT(15) -#define BIT_DATA_RPFM14EN BIT(14) -#define BIT_DATA_RPFM13EN BIT(13) -#define BIT_DATA_RPFM12EN BIT(12) -#define BIT_DATA_RPFM11EN BIT(11) -#define BIT_DATA_RPFM10EN BIT(10) -#define BIT_DATA_RPFM9EN BIT(9) -#define BIT_DATA_RPFM8EN BIT(8) +#define BIT_EN_BCN_FUNCTION BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BCN_CTRL (Offset 0x0550) */ +#define BIT_EN_TXBCN_RPT BIT(2) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_APP_PHYSTS_PER_SUBMPDU BIT(7) +/* 2 REG_BCN_CTRL (Offset 0x0550) */ + +#define BIT_P0_EN_RXBCN_RPT BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL (Offset 0x0550) */ +#define BIT_DIS_BCNQ_SUB BIT(1) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ -#define BIT_PHYSTS_PER_PKT_MODE BIT(7) -#define BIT_DATA_RPFM7EN BIT(7) +#define BIT_DIS_RX_BSSID_FIT1 BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#endif -#define BIT_APP_MH_SHIFT_VAL BIT(6) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +#define BIT_DIS_TSF1_UDT BIT(4) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ -#define BIT_DATA_RPFM6EN BIT(6) +#define BIT_CLI0_DIS_TSF_UDT BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +#define BIT_EN_BCN1_FUNCTION BIT(3) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#endif -#define BIT_WMAC_ENSHIFT BIT(5) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#define BIT_CLI0_EN_BCN_FUNCTION BIT(3) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ -#define BIT_DATA_RPFM5EN BIT(5) -#define BIT_DATA_RPFM4EN BIT(4) -#define BIT_DATA_RPFM3EN BIT(3) -#define BIT_DATA_RPFM2EN BIT(2) -#define BIT_DATA_RPFM1EN BIT(1) +#define BIT_EN_TXBCN1_RPT BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#define BIT_CLI0_EN_RXBCN_RPT BIT(2) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_DRVINFO_SZ 0 -#define BIT_MASK_DRVINFO_SZ 0xff -#define BIT_DRVINFO_SZ(x) (((x) & BIT_MASK_DRVINFO_SZ) << BIT_SHIFT_DRVINFO_SZ) -#define BIT_GET_DRVINFO_SZ(x) (((x) >> BIT_SHIFT_DRVINFO_SZ) & BIT_MASK_DRVINFO_SZ) +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#define BIT_CLI0_EN_BCN_RPT BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL1 (Offset 0x0551) */ +#define BIT_DIS_BCNQ1_SUB BIT(1) -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DRVINFO_SZ_V1 0 -#define BIT_MASK_DRVINFO_SZ_V1 0xf -#define BIT_DRVINFO_SZ_V1(x) (((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1) -#define BIT_GET_DRVINFO_SZ_V1(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1) +/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ +#define BIT_CLI0_ENP2P_CTWINDOW BIT(1) +#define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +/* 2 REG_MBID_NUM (Offset 0x0552) */ -#define BIT_DATA_RPFM0EN BIT(0) +#define BIT_SHIFT_MBID_BCN_NUM_V2 4 +#define BIT_MASK_MBID_BCN_NUM_V2 0xf +#define BIT_MBID_BCN_NUM_V2(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_V2) << BIT_SHIFT_MBID_BCN_NUM_V2) +#define BITS_MBID_BCN_NUM_V2 \ + (BIT_MASK_MBID_BCN_NUM_V2 << BIT_SHIFT_MBID_BCN_NUM_V2) +#define BIT_CLEAR_MBID_BCN_NUM_V2(x) ((x) & (~BITS_MBID_BCN_NUM_V2)) +#define BIT_GET_MBID_BCN_NUM_V2(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_V2) & BIT_MASK_MBID_BCN_NUM_V2) +#define BIT_SET_MBID_BCN_NUM_V2(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_V2(x) | BIT_MBID_BCN_NUM_V2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MBID_NUM (Offset 0x0552) */ +#define BIT_EN_PRE_DL_BEACON BIT(3) -/* 2 REG_MACID (Offset 0x0610) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MACID 0 -#define BIT_MASK_MACID 0xffffffffffffL -#define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID) -#define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID) +/* 2 REG_MBID_NUM (Offset 0x0552) */ +#define BIT_SHIFT_MBID_BCN_NUM 0 +#define BIT_MASK_MBID_BCN_NUM 0x7 +#define BIT_MBID_BCN_NUM(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM) +#define BITS_MBID_BCN_NUM (BIT_MASK_MBID_BCN_NUM << BIT_SHIFT_MBID_BCN_NUM) +#define BIT_CLEAR_MBID_BCN_NUM(x) ((x) & (~BITS_MBID_BCN_NUM)) +#define BIT_GET_MBID_BCN_NUM(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM) +#define BIT_SET_MBID_BCN_NUM(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM(x) | BIT_MBID_BCN_NUM(v)) -/* 2 REG_BSSID (Offset 0x0618) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BSSID 0 -#define BIT_MASK_BSSID 0xffffffffffffL -#define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID) -#define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_P2P_PWR_RST1 BIT(6) +#define BIT_SCHEDULER_RST BIT(5) -/* 2 REG_MAR (Offset 0x0620) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MAR 0 -#define BIT_MASK_MAR 0xffffffffffffffffL -#define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR) -#define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_FREECNT_RST BIT(5) -/* 2 REG_MBIDCAMCFG_1 (Offset 0x0628) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MBIDCAM_RWDATA_L 0 -#define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL -#define BIT_MBIDCAM_RWDATA_L(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L) -#define BIT_GET_MBIDCAM_RWDATA_L(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_P2P_PWR_RST0 BIT(4) -/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ +#endif -#define BIT_MBIDCAM_POLL BIT(31) -#define BIT_MBIDCAM_WT_EN BIT(30) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MBIDCAM_ADDR 24 -#define BIT_MASK_MBIDCAM_ADDR 0x1f -#define BIT_MBIDCAM_ADDR(x) (((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR) -#define BIT_GET_MBIDCAM_ADDR(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ -#define BIT_MBIDCAM_VALID BIT(23) -#define BIT_LSIC_TXOP_EN BIT(17) +#define BIT_TSFTR_CLI3_RST BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR1_SYNC_EN BIT(3) -/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ +#endif -#define BIT_CTS_EN BIT(16) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR_CLI2_RST BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ -#define BIT_REPEAT_MODE_EN BIT(16) +#define BIT_TSFTR_SYNC_EN BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR_CLI1_RST BIT(2) -/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MBIDCAM_RWDATA_H 0 -#define BIT_MASK_MBIDCAM_RWDATA_H 0xffff -#define BIT_MBIDCAM_RWDATA_H(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H) -#define BIT_GET_MBIDCAM_RWDATA_H(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR1_RST BIT(1) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR_CLI0_RST BIT(1) -/* 2 REG_MCU_TEST_1 (Offset 0x0630) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MCU_RSVD 0 -#define BIT_MASK_MCU_RSVD 0xffffffffL -#define BIT_MCU_RSVD(x) (((x) & BIT_MASK_MCU_RSVD) << BIT_SHIFT_MCU_RSVD) -#define BIT_GET_MCU_RSVD(x) (((x) >> BIT_SHIFT_MCU_RSVD) & BIT_MASK_MCU_RSVD) +/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ +#define BIT_TSFTR_RST BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28 +#define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7 +#define BIT_BCN_TIMER_SEL_FWRD(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD) +#define BITS_BCN_TIMER_SEL_FWRD \ + (BIT_MASK_BCN_TIMER_SEL_FWRD << BIT_SHIFT_BCN_TIMER_SEL_FWRD) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD)) +#define BIT_GET_BCN_TIMER_SEL_FWRD(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD) +#define BIT_SET_BCN_TIMER_SEL_FWRD(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) | BIT_BCN_TIMER_SEL_FWRD(v)) -/* 2 REG_WMAC_TCR_TSFT_OFS (Offset 0x0630) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0 -#define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff -#define BIT_WMAC_TCR_TSFT_OFS(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS) -#define BIT_GET_WMAC_TCR_TSFT_OFS(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS) +/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#define BIT_SHIFT_BCN_SPACE1 16 +#define BIT_MASK_BCN_SPACE1 0xffff +#define BIT_BCN_SPACE1(x) (((x) & BIT_MASK_BCN_SPACE1) << BIT_SHIFT_BCN_SPACE1) +#define BITS_BCN_SPACE1 (BIT_MASK_BCN_SPACE1 << BIT_SHIFT_BCN_SPACE1) +#define BIT_CLEAR_BCN_SPACE1(x) ((x) & (~BITS_BCN_SPACE1)) +#define BIT_GET_BCN_SPACE1(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE1) & BIT_MASK_BCN_SPACE1) +#define BIT_SET_BCN_SPACE1(x, v) (BIT_CLEAR_BCN_SPACE1(x) | BIT_BCN_SPACE1(v)) -/* 2 REG_UDF_THSD (Offset 0x0632) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_UDF_THSD 0 -#define BIT_MASK_UDF_THSD 0xff -#define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD) -#define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD) +/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#define BIT_SHIFT_BCN_SPACE_CLINT0 16 +#define BIT_MASK_BCN_SPACE_CLINT0 0xfff +#define BIT_BCN_SPACE_CLINT0(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0) +#define BITS_BCN_SPACE_CLINT0 \ + (BIT_MASK_BCN_SPACE_CLINT0 << BIT_SHIFT_BCN_SPACE_CLINT0) +#define BIT_CLEAR_BCN_SPACE_CLINT0(x) ((x) & (~BITS_BCN_SPACE_CLINT0)) +#define BIT_GET_BCN_SPACE_CLINT0(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0) +#define BIT_SET_BCN_SPACE_CLINT0(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT0(x) | BIT_BCN_SPACE_CLINT0(v)) -/* 2 REG_ZLD_NUM (Offset 0x0633) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_ZLD_NUM 0 -#define BIT_MASK_ZLD_NUM 0xff -#define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM) -#define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM) +/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ +#define BIT_SHIFT_BCN_SPACE0 0 +#define BIT_MASK_BCN_SPACE0 0xffff +#define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0) +#define BITS_BCN_SPACE0 (BIT_MASK_BCN_SPACE0 << BIT_SHIFT_BCN_SPACE0) +#define BIT_CLEAR_BCN_SPACE0(x) ((x) & (~BITS_BCN_SPACE0)) +#define BIT_GET_BCN_SPACE0(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0) +#define BIT_SET_BCN_SPACE0(x, v) (BIT_CLEAR_BCN_SPACE0(x) | BIT_BCN_SPACE0(v)) #endif - #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ATIMWND (Offset 0x055A) */ + +#define BIT_SHIFT_ATIMWND 0 +#define BIT_MASK_ATIMWND 0xffff +#define BIT_ATIMWND(x) (((x) & BIT_MASK_ATIMWND) << BIT_SHIFT_ATIMWND) +#define BITS_ATIMWND (BIT_MASK_ATIMWND << BIT_SHIFT_ATIMWND) +#define BIT_CLEAR_ATIMWND(x) ((x) & (~BITS_ATIMWND)) +#define BIT_GET_ATIMWND(x) (((x) >> BIT_SHIFT_ATIMWND) & BIT_MASK_ATIMWND) +#define BIT_SET_ATIMWND(x, v) (BIT_CLEAR_ATIMWND(x) | BIT_ATIMWND(v)) -/* 2 REG_MCU_TEST_2 (Offset 0x0634) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MCU_RSVD_2 0 -#define BIT_MASK_MCU_RSVD_2 0xffffffffL -#define BIT_MCU_RSVD_2(x) (((x) & BIT_MASK_MCU_RSVD_2) << BIT_SHIFT_MCU_RSVD_2) -#define BIT_GET_MCU_RSVD_2(x) (((x) >> BIT_SHIFT_MCU_RSVD_2) & BIT_MASK_MCU_RSVD_2) +/* 2 REG_ATIMWND (Offset 0x055A) */ +#define BIT_SHIFT_ATIMWND0 0 +#define BIT_MASK_ATIMWND0 0xffff +#define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0) +#define BITS_ATIMWND0 (BIT_MASK_ATIMWND0 << BIT_SHIFT_ATIMWND0) +#define BIT_CLEAR_ATIMWND0(x) ((x) & (~BITS_ATIMWND0)) +#define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0) +#define BIT_SET_ATIMWND0(x, v) (BIT_CLEAR_ATIMWND0(x) | BIT_ATIMWND0(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_USTIME_TSF (Offset 0x055C) */ +#define BIT_SHIFT_USTIME_TSF_V1 0 +#define BIT_MASK_USTIME_TSF_V1 0xff +#define BIT_USTIME_TSF_V1(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1) +#define BITS_USTIME_TSF_V1 (BIT_MASK_USTIME_TSF_V1 << BIT_SHIFT_USTIME_TSF_V1) +#define BIT_CLEAR_USTIME_TSF_V1(x) ((x) & (~BITS_USTIME_TSF_V1)) +#define BIT_GET_USTIME_TSF_V1(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1) +#define BIT_SET_USTIME_TSF_V1(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1(x) | BIT_USTIME_TSF_V1(v)) -/* 2 REG_STMP_THSD (Offset 0x0634) */ +/* 2 REG_BCN_MAX_ERR (Offset 0x055D) */ +#define BIT_SHIFT_BCN_MAX_ERR 0 +#define BIT_MASK_BCN_MAX_ERR 0xff +#define BIT_BCN_MAX_ERR(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR) +#define BITS_BCN_MAX_ERR (BIT_MASK_BCN_MAX_ERR << BIT_SHIFT_BCN_MAX_ERR) +#define BIT_CLEAR_BCN_MAX_ERR(x) ((x) & (~BITS_BCN_MAX_ERR)) +#define BIT_GET_BCN_MAX_ERR(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR) +#define BIT_SET_BCN_MAX_ERR(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR(x) | BIT_BCN_MAX_ERR(v)) -#define BIT_SHIFT_STMP_THSD 0 -#define BIT_MASK_STMP_THSD 0xff -#define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD) -#define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD) +/* 2 REG_RXTSF_OFFSET_CCK (Offset 0x055E) */ +#define BIT_SHIFT_CCK_RXTSF_OFFSET 0 +#define BIT_MASK_CCK_RXTSF_OFFSET 0xff +#define BIT_CCK_RXTSF_OFFSET(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET) +#define BITS_CCK_RXTSF_OFFSET \ + (BIT_MASK_CCK_RXTSF_OFFSET << BIT_SHIFT_CCK_RXTSF_OFFSET) +#define BIT_CLEAR_CCK_RXTSF_OFFSET(x) ((x) & (~BITS_CCK_RXTSF_OFFSET)) +#define BIT_GET_CCK_RXTSF_OFFSET(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET) +#define BIT_SET_CCK_RXTSF_OFFSET(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET(x) | BIT_CCK_RXTSF_OFFSET(v)) -/* 2 REG_WMAC_TXTIMEOUT (Offset 0x0635) */ +/* 2 REG_RXTSF_OFFSET_OFDM (Offset 0x055F) */ +#define BIT_SHIFT_OFDM_RXTSF_OFFSET 0 +#define BIT_MASK_OFDM_RXTSF_OFFSET 0xff +#define BIT_OFDM_RXTSF_OFFSET(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET) +#define BITS_OFDM_RXTSF_OFFSET \ + (BIT_MASK_OFDM_RXTSF_OFFSET << BIT_SHIFT_OFDM_RXTSF_OFFSET) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET(x) ((x) & (~BITS_OFDM_RXTSF_OFFSET)) +#define BIT_GET_OFDM_RXTSF_OFFSET(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET) +#define BIT_SET_OFDM_RXTSF_OFFSET(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET(x) | BIT_OFDM_RXTSF_OFFSET(v)) -#define BIT_SHIFT_WMAC_TXTIMEOUT 0 -#define BIT_MASK_WMAC_TXTIMEOUT 0xff -#define BIT_WMAC_TXTIMEOUT(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT) -#define BIT_GET_WMAC_TXTIMEOUT(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_MCU_TEST_2_V1 (Offset 0x0636) */ +/* 2 REG_TSFTR (Offset 0x0560) */ + +#define BIT_SHIFT_TSF_TIMER 0 +#define BIT_MASK_TSF_TIMER 0xffffffffffffffffL +#define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER) +#define BITS_TSF_TIMER (BIT_MASK_TSF_TIMER << BIT_SHIFT_TSF_TIMER) +#define BIT_CLEAR_TSF_TIMER(x) ((x) & (~BITS_TSF_TIMER)) +#define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER) +#define BIT_SET_TSF_TIMER(x, v) (BIT_CLEAR_TSF_TIMER(x) | BIT_TSF_TIMER(v)) +#endif + +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_MCU_RSVD_2_V1 0 -#define BIT_MASK_MCU_RSVD_2_V1 0xffff -#define BIT_MCU_RSVD_2_V1(x) (((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1) -#define BIT_GET_MCU_RSVD_2_V1(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1) +/* 2 REG_TSFTR0_L (Offset 0x0560) */ +#define BIT_SHIFT_TSF0_TIMER_L 0 +#define BIT_MASK_TSF0_TIMER_L 0xffffffffL +#define BIT_TSF0_TIMER_L(x) \ + (((x) & BIT_MASK_TSF0_TIMER_L) << BIT_SHIFT_TSF0_TIMER_L) +#define BITS_TSF0_TIMER_L (BIT_MASK_TSF0_TIMER_L << BIT_SHIFT_TSF0_TIMER_L) +#define BIT_CLEAR_TSF0_TIMER_L(x) ((x) & (~BITS_TSF0_TIMER_L)) +#define BIT_GET_TSF0_TIMER_L(x) \ + (((x) >> BIT_SHIFT_TSF0_TIMER_L) & BIT_MASK_TSF0_TIMER_L) +#define BIT_SET_TSF0_TIMER_L(x, v) \ + (BIT_CLEAR_TSF0_TIMER_L(x) | BIT_TSF0_TIMER_L(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TSFTR (Offset 0x0560) */ +#define BIT_SHIFT_TSF_TIMER_V1 0 +#define BIT_MASK_TSF_TIMER_V1 0xffffffffL +#define BIT_TSF_TIMER_V1(x) \ + (((x) & BIT_MASK_TSF_TIMER_V1) << BIT_SHIFT_TSF_TIMER_V1) +#define BITS_TSF_TIMER_V1 (BIT_MASK_TSF_TIMER_V1 << BIT_SHIFT_TSF_TIMER_V1) +#define BIT_CLEAR_TSF_TIMER_V1(x) ((x) & (~BITS_TSF_TIMER_V1)) +#define BIT_GET_TSF_TIMER_V1(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V1) & BIT_MASK_TSF_TIMER_V1) +#define BIT_SET_TSF_TIMER_V1(x, v) \ + (BIT_CLEAR_TSF_TIMER_V1(x) | BIT_TSF_TIMER_V1(v)) -/* 2 REG_USTIME_EDCA (Offset 0x0638) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_USTIME_EDCA 0 -#define BIT_MASK_USTIME_EDCA 0xff -#define BIT_USTIME_EDCA(x) (((x) & BIT_MASK_USTIME_EDCA) << BIT_SHIFT_USTIME_EDCA) -#define BIT_GET_USTIME_EDCA(x) (((x) >> BIT_SHIFT_USTIME_EDCA) & BIT_MASK_USTIME_EDCA) +/* 2 REG_TSFTR0_H (Offset 0x0564) */ +#define BIT_SHIFT_TSF0_TIMER_H 0 +#define BIT_MASK_TSF0_TIMER_H 0xffffffffL +#define BIT_TSF0_TIMER_H(x) \ + (((x) & BIT_MASK_TSF0_TIMER_H) << BIT_SHIFT_TSF0_TIMER_H) +#define BITS_TSF0_TIMER_H (BIT_MASK_TSF0_TIMER_H << BIT_SHIFT_TSF0_TIMER_H) +#define BIT_CLEAR_TSF0_TIMER_H(x) ((x) & (~BITS_TSF0_TIMER_H)) +#define BIT_GET_TSF0_TIMER_H(x) \ + (((x) >> BIT_SHIFT_TSF0_TIMER_H) & BIT_MASK_TSF0_TIMER_H) +#define BIT_SET_TSF0_TIMER_H(x, v) \ + (BIT_CLEAR_TSF0_TIMER_H(x) | BIT_TSF0_TIMER_H(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TSFTR_1 (Offset 0x0564) */ +#define BIT_SHIFT_TSF_TIMER_V2 0 +#define BIT_MASK_TSF_TIMER_V2 0xffffffffL +#define BIT_TSF_TIMER_V2(x) \ + (((x) & BIT_MASK_TSF_TIMER_V2) << BIT_SHIFT_TSF_TIMER_V2) +#define BITS_TSF_TIMER_V2 (BIT_MASK_TSF_TIMER_V2 << BIT_SHIFT_TSF_TIMER_V2) +#define BIT_CLEAR_TSF_TIMER_V2(x) ((x) & (~BITS_TSF_TIMER_V2)) +#define BIT_GET_TSF_TIMER_V2(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V2) & BIT_MASK_TSF_TIMER_V2) +#define BIT_SET_TSF_TIMER_V2(x, v) \ + (BIT_CLEAR_TSF_TIMER_V2(x) | BIT_TSF_TIMER_V2(v)) -/* 2 REG_USTIME_EDCA (Offset 0x0638) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_USTIME_EDCA_V1 0 -#define BIT_MASK_USTIME_EDCA_V1 0x1ff -#define BIT_USTIME_EDCA_V1(x) (((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1) -#define BIT_GET_USTIME_EDCA_V1(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1) +/* 2 REG_TSFTR1 (Offset 0x0568) */ +#define BIT_SHIFT_TSF_TIMER1 0 +#define BIT_MASK_TSF_TIMER1 0xffffffffffffffffL +#define BIT_TSF_TIMER1(x) (((x) & BIT_MASK_TSF_TIMER1) << BIT_SHIFT_TSF_TIMER1) +#define BITS_TSF_TIMER1 (BIT_MASK_TSF_TIMER1 << BIT_SHIFT_TSF_TIMER1) +#define BIT_CLEAR_TSF_TIMER1(x) ((x) & (~BITS_TSF_TIMER1)) +#define BIT_GET_TSF_TIMER1(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER1) & BIT_MASK_TSF_TIMER1) +#define BIT_SET_TSF_TIMER1(x, v) (BIT_CLEAR_TSF_TIMER1(x) | BIT_TSF_TIMER1(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_TSFTR1_L (Offset 0x0568) */ +#define BIT_SHIFT_TSF1_TIMER_L 0 +#define BIT_MASK_TSF1_TIMER_L 0xffffffffL +#define BIT_TSF1_TIMER_L(x) \ + (((x) & BIT_MASK_TSF1_TIMER_L) << BIT_SHIFT_TSF1_TIMER_L) +#define BITS_TSF1_TIMER_L (BIT_MASK_TSF1_TIMER_L << BIT_SHIFT_TSF1_TIMER_L) +#define BIT_CLEAR_TSF1_TIMER_L(x) ((x) & (~BITS_TSF1_TIMER_L)) +#define BIT_GET_TSF1_TIMER_L(x) \ + (((x) >> BIT_SHIFT_TSF1_TIMER_L) & BIT_MASK_TSF1_TIMER_L) +#define BIT_SET_TSF1_TIMER_L(x, v) \ + (BIT_CLEAR_TSF1_TIMER_L(x) | BIT_TSF1_TIMER_L(v)) -/* 2 REG_ACKTO_CCK (Offset 0x0639) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_ACKTO_CCK 0 -#define BIT_MASK_ACKTO_CCK 0xff -#define BIT_ACKTO_CCK(x) (((x) & BIT_MASK_ACKTO_CCK) << BIT_SHIFT_ACKTO_CCK) -#define BIT_GET_ACKTO_CCK(x) (((x) >> BIT_SHIFT_ACKTO_CCK) & BIT_MASK_ACKTO_CCK) +/* 2 REG_FREERUN_CNT (Offset 0x0568) */ +#define BIT_SHIFT_FREERUN_CNT 0 +#define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL +#define BIT_FREERUN_CNT(x) \ + (((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT) +#define BITS_FREERUN_CNT (BIT_MASK_FREERUN_CNT << BIT_SHIFT_FREERUN_CNT) +#define BIT_CLEAR_FREERUN_CNT(x) ((x) & (~BITS_FREERUN_CNT)) +#define BIT_GET_FREERUN_CNT(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT) +#define BIT_SET_FREERUN_CNT(x, v) \ + (BIT_CLEAR_FREERUN_CNT(x) | BIT_FREERUN_CNT(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_FREERUN_CNT (Offset 0x0568) */ +#define BIT_SHIFT_FREERUN_CNT_V1 0 +#define BIT_MASK_FREERUN_CNT_V1 0xffffffffL +#define BIT_FREERUN_CNT_V1(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V1) << BIT_SHIFT_FREERUN_CNT_V1) +#define BITS_FREERUN_CNT_V1 \ + (BIT_MASK_FREERUN_CNT_V1 << BIT_SHIFT_FREERUN_CNT_V1) +#define BIT_CLEAR_FREERUN_CNT_V1(x) ((x) & (~BITS_FREERUN_CNT_V1)) +#define BIT_GET_FREERUN_CNT_V1(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V1) & BIT_MASK_FREERUN_CNT_V1) +#define BIT_SET_FREERUN_CNT_V1(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V1(x) | BIT_FREERUN_CNT_V1(v)) -/* 2 REG_MAC_SPEC_SIFS (Offset 0x063A) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_SPEC_SIFS_OFDM 8 -#define BIT_MASK_SPEC_SIFS_OFDM 0xff -#define BIT_SPEC_SIFS_OFDM(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM) -#define BIT_GET_SPEC_SIFS_OFDM(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM) +/* 2 REG_TSFTR1_H (Offset 0x056C) */ +#define BIT_SHIFT_TSF1_TIMER_H 0 +#define BIT_MASK_TSF1_TIMER_H 0xffffffffL +#define BIT_TSF1_TIMER_H(x) \ + (((x) & BIT_MASK_TSF1_TIMER_H) << BIT_SHIFT_TSF1_TIMER_H) +#define BITS_TSF1_TIMER_H (BIT_MASK_TSF1_TIMER_H << BIT_SHIFT_TSF1_TIMER_H) +#define BIT_CLEAR_TSF1_TIMER_H(x) ((x) & (~BITS_TSF1_TIMER_H)) +#define BIT_GET_TSF1_TIMER_H(x) \ + (((x) >> BIT_SHIFT_TSF1_TIMER_H) & BIT_MASK_TSF1_TIMER_H) +#define BIT_SET_TSF1_TIMER_H(x, v) \ + (BIT_CLEAR_TSF1_TIMER_H(x) | BIT_TSF1_TIMER_H(v)) -#define BIT_SHIFT_SPEC_SIFS_CCK 0 -#define BIT_MASK_SPEC_SIFS_CCK 0xff -#define BIT_SPEC_SIFS_CCK(x) (((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK) -#define BIT_GET_SPEC_SIFS_CCK(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */ +/* 2 REG_FREERUN_CNT_1 (Offset 0x056C) */ +#define BIT_SHIFT_FREERUN_CNT_V2 0 +#define BIT_MASK_FREERUN_CNT_V2 0xffffffffL +#define BIT_FREERUN_CNT_V2(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V2) << BIT_SHIFT_FREERUN_CNT_V2) +#define BITS_FREERUN_CNT_V2 \ + (BIT_MASK_FREERUN_CNT_V2 << BIT_SHIFT_FREERUN_CNT_V2) +#define BIT_CLEAR_FREERUN_CNT_V2(x) ((x) & (~BITS_FREERUN_CNT_V2)) +#define BIT_GET_FREERUN_CNT_V2(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V2) & BIT_MASK_FREERUN_CNT_V2) +#define BIT_SET_FREERUN_CNT_V2(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V2(x) | BIT_FREERUN_CNT_V2(v)) -#define BIT_SHIFT_SIFS_R2T_CCK 8 -#define BIT_MASK_SIFS_R2T_CCK 0xff -#define BIT_SIFS_R2T_CCK(x) (((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK) -#define BIT_GET_SIFS_R2T_CCK(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_SIFS_T2T_CCK 0 -#define BIT_MASK_SIFS_T2T_CCK 0xff -#define BIT_SIFS_T2T_CCK(x) (((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK) -#define BIT_GET_SIFS_T2T_CCK(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK) +/* 2 REG_ATIMWND1 (Offset 0x0570) */ +#define BIT_SHIFT_ATIMWND1 0 +#define BIT_MASK_ATIMWND1 0xffff +#define BIT_ATIMWND1(x) (((x) & BIT_MASK_ATIMWND1) << BIT_SHIFT_ATIMWND1) +#define BITS_ATIMWND1 (BIT_MASK_ATIMWND1 << BIT_SHIFT_ATIMWND1) +#define BIT_CLEAR_ATIMWND1(x) ((x) & (~BITS_ATIMWND1)) +#define BIT_GET_ATIMWND1(x) (((x) >> BIT_SHIFT_ATIMWND1) & BIT_MASK_ATIMWND1) +#define BIT_SET_ATIMWND1(x, v) (BIT_CLEAR_ATIMWND1(x) | BIT_ATIMWND1(v)) -/* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_SIFS_R2T_OFDM 8 -#define BIT_MASK_SIFS_R2T_OFDM 0xff -#define BIT_SIFS_R2T_OFDM(x) (((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM) -#define BIT_GET_SIFS_R2T_OFDM(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM) +/* 2 REG_ATIMWND1_V1 (Offset 0x0570) */ +#define BIT_SHIFT_ATIMWND1_V2 0 +#define BIT_MASK_ATIMWND1_V2 0xffff +#define BIT_ATIMWND1_V2(x) \ + (((x) & BIT_MASK_ATIMWND1_V2) << BIT_SHIFT_ATIMWND1_V2) +#define BITS_ATIMWND1_V2 (BIT_MASK_ATIMWND1_V2 << BIT_SHIFT_ATIMWND1_V2) +#define BIT_CLEAR_ATIMWND1_V2(x) ((x) & (~BITS_ATIMWND1_V2)) +#define BIT_GET_ATIMWND1_V2(x) \ + (((x) >> BIT_SHIFT_ATIMWND1_V2) & BIT_MASK_ATIMWND1_V2) +#define BIT_SET_ATIMWND1_V2(x, v) \ + (BIT_CLEAR_ATIMWND1_V2(x) | BIT_ATIMWND1_V2(v)) -#define BIT_SHIFT_SIFS_T2T_OFDM 0 -#define BIT_MASK_SIFS_T2T_OFDM 0xff -#define BIT_SIFS_T2T_OFDM(x) (((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM) -#define BIT_GET_SIFS_T2T_OFDM(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_ACKTO (Offset 0x0640) */ +/* 2 REG_ATIMWND1_V1 (Offset 0x0570) */ +#define BIT_SHIFT_ATIMWND1_V1 0 +#define BIT_MASK_ATIMWND1_V1 0xff +#define BIT_ATIMWND1_V1(x) \ + (((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1) +#define BITS_ATIMWND1_V1 (BIT_MASK_ATIMWND1_V1 << BIT_SHIFT_ATIMWND1_V1) +#define BIT_CLEAR_ATIMWND1_V1(x) ((x) & (~BITS_ATIMWND1_V1)) +#define BIT_GET_ATIMWND1_V1(x) \ + (((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1) +#define BIT_SET_ATIMWND1_V1(x, v) \ + (BIT_CLEAR_ATIMWND1_V1(x) | BIT_ATIMWND1_V1(v)) -#define BIT_SHIFT_ACKTO 0 -#define BIT_MASK_ACKTO 0xff -#define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO) -#define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO) +/* 2 REG_TBTT_PROHIBIT_INFRA (Offset 0x0571) */ +#define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0 +#define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff +#define BIT_TBTT_PROHIBIT_INFRA(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA) +#define BITS_TBTT_PROHIBIT_INFRA \ + (BIT_MASK_TBTT_PROHIBIT_INFRA << BIT_SHIFT_TBTT_PROHIBIT_INFRA) +#define BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) ((x) & (~BITS_TBTT_PROHIBIT_INFRA)) +#define BIT_GET_TBTT_PROHIBIT_INFRA(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA) +#define BIT_SET_TBTT_PROHIBIT_INFRA(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) | BIT_TBTT_PROHIBIT_INFRA(v)) -/* 2 REG_CTS2TO (Offset 0x0641) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CTS2TO 0 -#define BIT_MASK_CTS2TO 0xff -#define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO) -#define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO) +/* 2 REG_BCNIVLCUNT (Offset 0x0573) */ +#define BIT_SHIFT_BCNIVLCUNT 0 +#define BIT_MASK_BCNIVLCUNT 0x7f +#define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT) +#define BITS_BCNIVLCUNT (BIT_MASK_BCNIVLCUNT << BIT_SHIFT_BCNIVLCUNT) +#define BIT_CLEAR_BCNIVLCUNT(x) ((x) & (~BITS_BCNIVLCUNT)) +#define BIT_GET_BCNIVLCUNT(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT) +#define BIT_SET_BCNIVLCUNT(x, v) (BIT_CLEAR_BCNIVLCUNT(x) | BIT_BCNIVLCUNT(v)) -/* 2 REG_EIFS (Offset 0x0642) */ +/* 2 REG_BCNDROPCTRL (Offset 0x0574) */ + +#define BIT_BEACON_DROP_EN BIT(7) +#define BIT_SHIFT_BEACON_DROP_IVL 0 +#define BIT_MASK_BEACON_DROP_IVL 0x7f +#define BIT_BEACON_DROP_IVL(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL) +#define BITS_BEACON_DROP_IVL \ + (BIT_MASK_BEACON_DROP_IVL << BIT_SHIFT_BEACON_DROP_IVL) +#define BIT_CLEAR_BEACON_DROP_IVL(x) ((x) & (~BITS_BEACON_DROP_IVL)) +#define BIT_GET_BEACON_DROP_IVL(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL) +#define BIT_SET_BEACON_DROP_IVL(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL(x) | BIT_BEACON_DROP_IVL(v)) -#define BIT_SHIFT_EIFS 0 -#define BIT_MASK_EIFS 0xffff -#define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS) -#define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS) +/* 2 REG_HGQ_TIMEOUT_PERIOD (Offset 0x0575) */ +#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0 +#define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff +#define BIT_HGQ_TIMEOUT_PERIOD(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD) +#define BITS_HGQ_TIMEOUT_PERIOD \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD << BIT_SHIFT_HGQ_TIMEOUT_PERIOD) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) ((x) & (~BITS_HGQ_TIMEOUT_PERIOD)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD) +#define BIT_SET_HGQ_TIMEOUT_PERIOD(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) | BIT_HGQ_TIMEOUT_PERIOD(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_TXCMD_TIMEOUT_PERIOD (Offset 0x0576) */ +#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0 +#define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff +#define BIT_TXCMD_TIMEOUT_PERIOD(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) +#define BITS_TXCMD_TIMEOUT_PERIOD \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) | BIT_TXCMD_TIMEOUT_PERIOD(v)) + +#define BIT_SHIFT_EARLY_128US 0 +#define BIT_MASK_EARLY_128US 0x7 +#define BIT_EARLY_128US(x) \ + (((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US) +#define BITS_EARLY_128US (BIT_MASK_EARLY_128US << BIT_SHIFT_EARLY_128US) +#define BIT_CLEAR_EARLY_128US(x) ((x) & (~BITS_EARLY_128US)) +#define BIT_GET_EARLY_128US(x) \ + (((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US) +#define BIT_SET_EARLY_128US(x, v) \ + (BIT_CLEAR_EARLY_128US(x) | BIT_EARLY_128US(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_RPFM_MAP0 (Offset 0x0644) */ +/* 2 REG_MISC_CTRL (Offset 0x0577) */ -#define BIT_MGT_RPFM15EN BIT(15) -#define BIT_MGT_RPFM14EN BIT(14) -#define BIT_MGT_RPFM13EN BIT(13) -#define BIT_MGT_RPFM12EN BIT(12) -#define BIT_MGT_RPFM11EN BIT(11) -#define BIT_MGT_RPFM10EN BIT(10) -#define BIT_MGT_RPFM9EN BIT(9) -#define BIT_MGT_RPFM8EN BIT(8) -#define BIT_MGT_RPFM7EN BIT(7) -#define BIT_MGT_RPFM6EN BIT(6) -#define BIT_MGT_RPFM5EN BIT(5) -#define BIT_MGT_RPFM4EN BIT(4) -#define BIT_MGT_RPFM3EN BIT(3) -#define BIT_MGT_RPFM2EN BIT(2) -#define BIT_MGT_RPFM1EN BIT(1) -#define BIT_MGT_RPFM0EN BIT(0) +#define BIT_DIS_MARK_TSF_US BIT(7) -/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ +#endif -#define BIT_RPFM_CAM_POLLING BIT(31) -#define BIT_RPFM_CAM_CLR BIT(30) -#define BIT_RPFM_CAM_WE BIT(16) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RPFM_CAM_ADDR 0 -#define BIT_MASK_RPFM_CAM_ADDR 0x7f -#define BIT_RPFM_CAM_ADDR(x) (((x) & BIT_MASK_RPFM_CAM_ADDR) << BIT_SHIFT_RPFM_CAM_ADDR) -#define BIT_GET_RPFM_CAM_ADDR(x) (((x) >> BIT_SHIFT_RPFM_CAM_ADDR) & BIT_MASK_RPFM_CAM_ADDR) +/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_DIS_MARK_TSF_US_V2 BIT(7) -/* 2 REG_RPFM_CAM_RWD (Offset 0x064C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RPFM_CAM_RWD 0 -#define BIT_MASK_RPFM_CAM_RWD 0xffffffffL -#define BIT_RPFM_CAM_RWD(x) (((x) & BIT_MASK_RPFM_CAM_RWD) << BIT_SHIFT_RPFM_CAM_RWD) -#define BIT_GET_RPFM_CAM_RWD(x) (((x) >> BIT_SHIFT_RPFM_CAM_RWD) & BIT_MASK_RPFM_CAM_RWD) +/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_EN_TSFAUTO_SYNC BIT(6) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_AUTO_SYNC_BY_TBTT BIT(6) -/* 2 REG_NAV_CTRL (Offset 0x0650) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NAV_UPPER 16 -#define BIT_MASK_NAV_UPPER 0xff -#define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER) -#define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER) +/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_DIS_TRX_CAL_BCN BIT(5) +#define BIT_DIS_TX_CAL_TBTT BIT(4) +#define BIT_EN_FREECNT BIT(3) +#define BIT_BCN_AGGRESSION BIT(2) -#define BIT_SHIFT_RXMYRTS_NAV 8 -#define BIT_MASK_RXMYRTS_NAV 0xf -#define BIT_RXMYRTS_NAV(x) (((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV) -#define BIT_GET_RXMYRTS_NAV(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RTSRST 0 -#define BIT_MASK_RTSRST 0xff -#define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST) -#define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST) +/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_DIS_SECONDARY_CCA_80M BIT(2) +#define BIT_DIS_SECONDARY_CCA_40M BIT(1) -/* 2 REG_BACAMCMD (Offset 0x0654) */ +#endif -#define BIT_BACAM_POLL BIT(31) -#define BIT_BACAM_RST BIT(17) -#define BIT_BACAM_RW BIT(16) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TXSBM 14 -#define BIT_MASK_TXSBM 0x3 -#define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM) -#define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM) +/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_SHIFT_DIS_SECONDARY_CCA 0 +#define BIT_MASK_DIS_SECONDARY_CCA 0x3 +#define BIT_DIS_SECONDARY_CCA(x) \ + (((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA) +#define BITS_DIS_SECONDARY_CCA \ + (BIT_MASK_DIS_SECONDARY_CCA << BIT_SHIFT_DIS_SECONDARY_CCA) +#define BIT_CLEAR_DIS_SECONDARY_CCA(x) ((x) & (~BITS_DIS_SECONDARY_CCA)) +#define BIT_GET_DIS_SECONDARY_CCA(x) \ + (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA) +#define BIT_SET_DIS_SECONDARY_CCA(x, v) \ + (BIT_CLEAR_DIS_SECONDARY_CCA(x) | BIT_DIS_SECONDARY_CCA(v)) -#define BIT_SHIFT_BACAM_ADDR 0 -#define BIT_MASK_BACAM_ADDR 0x3f -#define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR) -#define BIT_GET_BACAM_ADDR(x) (((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_BACAMCONTENT (Offset 0x0658) */ +/* 2 REG_MISC_CTRL (Offset 0x0577) */ +#define BIT_DIS_SECONDARY_CCA_20M BIT(0) -#define BIT_SHIFT_BA_CONTENT_H (32 & CPU_OPT_WIDTH) -#define BIT_MASK_BA_CONTENT_H 0xffffffffL -#define BIT_BA_CONTENT_H(x) (((x) & BIT_MASK_BA_CONTENT_H) << BIT_SHIFT_BA_CONTENT_H) -#define BIT_GET_BA_CONTENT_H(x) (((x) >> BIT_SHIFT_BA_CONTENT_H) & BIT_MASK_BA_CONTENT_H) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BA_CONTENT_L 0 -#define BIT_MASK_BA_CONTENT_L 0xffffffffL -#define BIT_BA_CONTENT_L(x) (((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L) -#define BIT_GET_BA_CONTENT_L(x) (((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L) +/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +#define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6) +#define BIT_CLI1_DIS_TSF_UDT BIT(4) +#define BIT_CLI1_EN_BCN_FUNCTION BIT(3) -/* 2 REG_LBDLY (Offset 0x0660) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LBDLY 0 -#define BIT_MASK_LBDLY 0x1f -#define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY) -#define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY) +/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +#define BIT_CLI1_EN_RXBCN_RPT BIT(2) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +#define BIT_CLI1_EN_BCN_RPT BIT(2) -/* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2 -#define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f -#define BIT_BITMAP_SSNBK_COUNTER(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER) << BIT_SHIFT_BITMAP_SSNBK_COUNTER) -#define BIT_GET_BITMAP_SSNBK_COUNTER(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) & BIT_MASK_BITMAP_SSNBK_COUNTER) +/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ -#define BIT_BITMAP_EN BIT(1) +#define BIT_CLI1_ENP2P_CTWINDOW BIT(1) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_TSFTR2_L (Offset 0x0578) */ -/* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ - -#define BIT_WMAC_BACAM_RPMEN BIT(0) +#define BIT_SHIFT_TSF2_TIMER_L 0 +#define BIT_MASK_TSF2_TIMER_L 0xffffffffL +#define BIT_TSF2_TIMER_L(x) \ + (((x) & BIT_MASK_TSF2_TIMER_L) << BIT_SHIFT_TSF2_TIMER_L) +#define BITS_TSF2_TIMER_L (BIT_MASK_TSF2_TIMER_L << BIT_SHIFT_TSF2_TIMER_L) +#define BIT_CLEAR_TSF2_TIMER_L(x) ((x) & (~BITS_TSF2_TIMER_L)) +#define BIT_GET_TSF2_TIMER_L(x) \ + (((x) >> BIT_SHIFT_TSF2_TIMER_L) & BIT_MASK_TSF2_TIMER_L) +#define BIT_SET_TSF2_TIMER_L(x, v) \ + (BIT_CLEAR_TSF2_TIMER_L(x) | BIT_TSF2_TIMER_L(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ +#define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0) -/* 2 REG_TX_RX (Offset 0x0662) */ +/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +#define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6) +#define BIT_CLI2_DIS_TSF_UDT BIT(4) +#define BIT_CLI2_EN_BCN_FUNCTION BIT(3) -#define BIT_SHIFT_RXPKT_TYPE 2 -#define BIT_MASK_RXPKT_TYPE 0x3f -#define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE) -#define BIT_GET_RXPKT_TYPE(x) (((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE) +#endif -#define BIT_TXACT_IND BIT(1) -#define BIT_RXACT_IND BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_WMAC_BITMAP_CTL (Offset 0x0663) */ +/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ -#define BIT_BITMAP_VO BIT(7) -#define BIT_BITMAP_VI BIT(6) -#define BIT_BITMAP_BE BIT(5) -#define BIT_BITMAP_BK BIT(4) +#define BIT_CLI2_EN_RXBCN_RPT BIT(2) -#define BIT_SHIFT_BITMAP_CONDITION 2 -#define BIT_MASK_BITMAP_CONDITION 0x3 -#define BIT_BITMAP_CONDITION(x) (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION) -#define BIT_GET_BITMAP_CONDITION(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION) +#endif -#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1) -#define BIT_BITMAP_FORCE BIT(0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +#define BIT_CLI2_EN_BCN_RPT BIT(2) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RXERR_RPT (Offset 0x0664) */ +/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ +#define BIT_CLI2_ENP2P_CTWINDOW BIT(1) +#define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0) -#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28 -#define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf -#define BIT_RXERR_RPT_SEL_V1_3_0(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) -#define BIT_GET_RXERR_RPT_SEL_V1_3_0(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) +/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +#define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6) +#define BIT_CLI3_DIS_TSF_UDT BIT(4) +#define BIT_CLI3_EN_BCN_FUNCTION BIT(3) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +#define BIT_CLI3_EN_RXBCN_RPT BIT(2) -/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_RXERR_RPT_SEL 28 -#define BIT_MASK_RXERR_RPT_SEL 0xf -#define BIT_RXERR_RPT_SEL(x) (((x) & BIT_MASK_RXERR_RPT_SEL) << BIT_SHIFT_RXERR_RPT_SEL) -#define BIT_GET_RXERR_RPT_SEL(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL) & BIT_MASK_RXERR_RPT_SEL) +/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +#define BIT_CLI3_EN_BCN_RPT BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ +#define BIT_CLI3_ENP2P_CTWINDOW BIT(1) +#define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0) -/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#endif -#define BIT_RXERR_RPT_RST BIT(27) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_EXTEND_CTRL (Offset 0x057B) */ + +#define BIT_EN_TSFBIT32_RST_P2P2 BIT(5) +#define BIT_EN_TSFBIT32_RST_P2P1 BIT(4) +#define BIT_SHIFT_PORT_SEL 0 +#define BIT_MASK_PORT_SEL 0x7 +#define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL) +#define BITS_PORT_SEL (BIT_MASK_PORT_SEL << BIT_SHIFT_PORT_SEL) +#define BIT_CLEAR_PORT_SEL(x) ((x) & (~BITS_PORT_SEL)) +#define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL) +#define BIT_SET_PORT_SEL(x, v) (BIT_CLEAR_PORT_SEL(x) | BIT_PORT_SEL(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RXERR_RPT (Offset 0x0664) */ +/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ -#define BIT_RXERR_RPT_SEL_V1_4 BIT(26) +#define BIT_P2P1_SPEC_POWER_STATE BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ +#define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6) -/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_UD_SELECT_BSSID_2_1 24 -#define BIT_MASK_UD_SELECT_BSSID_2_1 0x3 -#define BIT_UD_SELECT_BSSID_2_1(x) (((x) & BIT_MASK_UD_SELECT_BSSID_2_1) << BIT_SHIFT_UD_SELECT_BSSID_2_1) -#define BIT_GET_UD_SELECT_BSSID_2_1(x) (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1) & BIT_MASK_UD_SELECT_BSSID_2_1) +/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ +#define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ +#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4) +#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3) +#define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2) +#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1) -/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#endif + +#if (HALMAC_8192F_SUPPORT) -#define BIT_W1S BIT(23) +/* 2 REG_TSFTR2_H (Offset 0x057C) */ + +#define BIT_SHIFT_TSF2_TIMER_H 0 +#define BIT_MASK_TSF2_TIMER_H 0xffffffffL +#define BIT_TSF2_TIMER_H(x) \ + (((x) & BIT_MASK_TSF2_TIMER_H) << BIT_SHIFT_TSF2_TIMER_H) +#define BITS_TSF2_TIMER_H (BIT_MASK_TSF2_TIMER_H << BIT_SHIFT_TSF2_TIMER_H) +#define BIT_CLEAR_TSF2_TIMER_H(x) ((x) & (~BITS_TSF2_TIMER_H)) +#define BIT_GET_TSF2_TIMER_H(x) \ + (((x) >> BIT_SHIFT_TSF2_TIMER_H) & BIT_MASK_TSF2_TIMER_H) +#define BIT_SET_TSF2_TIMER_H(x, v) \ + (BIT_CLEAR_TSF2_TIMER_H(x) | BIT_TSF2_TIMER_H(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ +#define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0) -/* 2 REG_RXERR_RPT (Offset 0x0664) */ +/* 2 REG_P2PPS1_STATE (Offset 0x057D) */ -#define BIT_UD_SELECT_BSSID BIT(22) +#define BIT_P2P1_POWER_STATE BIT(7) +#define BIT_P2P1_CTWINDOW_ON BIT(6) +#define BIT_P2P1_BEACON_AREA_ON BIT(5) +#define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4) +#define BIT_P2P1_NOA1_OFF_PERIOD BIT(3) +#define BIT_P2P1_FORCE_DOZE1 BIT(2) +#define BIT_P2P1_NOA0_OFF_PERIOD BIT(1) +#define BIT_P2P1_FORCE_DOZE0 BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ +#define BIT_P2P2_SPEC_POWER_STATE BIT(7) -/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#endif -#define BIT_UD_SELECT_BSSID_0 BIT(22) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ + +#define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ +#define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5) -/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_UD_SUB_TYPE 18 -#define BIT_MASK_UD_SUB_TYPE 0xf -#define BIT_UD_SUB_TYPE(x) (((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE) -#define BIT_GET_UD_SUB_TYPE(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE) +/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ +#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4) +#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3) +#define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2) +#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1) +#define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0) -#define BIT_SHIFT_UD_TYPE 16 -#define BIT_MASK_UD_TYPE 0x3 -#define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE) -#define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE) +/* 2 REG_P2PPS2_STATE (Offset 0x057F) */ +#define BIT_P2P2_POWER_STATE BIT(7) +#define BIT_P2P2_CTWINDOW_ON BIT(6) +#define BIT_P2P2_BEACON_AREA_ON BIT(5) +#define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4) +#define BIT_P2P2_NOA1_OFF_PERIOD BIT(3) +#define BIT_P2P2_FORCE_DOZE1 BIT(2) +#define BIT_P2P2_NOA0_OFF_PERIOD BIT(1) +#define BIT_P2P2_FORCE_DOZE0 BIT(0) -#define BIT_SHIFT_RPT_COUNTER 0 -#define BIT_MASK_RPT_COUNTER 0xffff -#define BIT_RPT_COUNTER(x) (((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER) -#define BIT_GET_RPT_COUNTER(x) (((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +/* 2 REG_PS_TIMER (Offset 0x0580) */ +#define BIT_SHIFT_PSTIMER 5 +#define BIT_MASK_PSTIMER 0x7ffffff +#define BIT_PSTIMER(x) (((x) & BIT_MASK_PSTIMER) << BIT_SHIFT_PSTIMER) +#define BITS_PSTIMER (BIT_MASK_PSTIMER << BIT_SHIFT_PSTIMER) +#define BIT_CLEAR_PSTIMER(x) ((x) & (~BITS_PSTIMER)) +#define BIT_GET_PSTIMER(x) (((x) >> BIT_SHIFT_PSTIMER) & BIT_MASK_PSTIMER) +#define BIT_SET_PSTIMER(x, v) (BIT_CLEAR_PSTIMER(x) | BIT_PSTIMER(v)) -#define BIT_SHIFT_ACKBA_TYPSEL (60 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_TYPSEL 0xf -#define BIT_ACKBA_TYPSEL(x) (((x) & BIT_MASK_ACKBA_TYPSEL) << BIT_SHIFT_ACKBA_TYPSEL) -#define BIT_GET_ACKBA_TYPSEL(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL) & BIT_MASK_ACKBA_TYPSEL) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_ACKBA_ACKPCHK (56 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_ACKPCHK 0xf -#define BIT_ACKBA_ACKPCHK(x) (((x) & BIT_MASK_ACKBA_ACKPCHK) << BIT_SHIFT_ACKBA_ACKPCHK) -#define BIT_GET_ACKBA_ACKPCHK(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK) & BIT_MASK_ACKBA_ACKPCHK) +/* 2 REG_PS_TIMER0 (Offset 0x0580) */ +#define BIT_SHIFT_PSTIMER0_INT 5 +#define BIT_MASK_PSTIMER0_INT 0x7ffffff +#define BIT_PSTIMER0_INT(x) \ + (((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT) +#define BITS_PSTIMER0_INT (BIT_MASK_PSTIMER0_INT << BIT_SHIFT_PSTIMER0_INT) +#define BIT_CLEAR_PSTIMER0_INT(x) ((x) & (~BITS_PSTIMER0_INT)) +#define BIT_GET_PSTIMER0_INT(x) \ + (((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT) +#define BIT_SET_PSTIMER0_INT(x, v) \ + (BIT_CLEAR_PSTIMER0_INT(x) | BIT_PSTIMER0_INT(v)) -#define BIT_SHIFT_ACKBAR_TYPESEL (48 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_TYPESEL 0xff -#define BIT_ACKBAR_TYPESEL(x) (((x) & BIT_MASK_ACKBAR_TYPESEL) << BIT_SHIFT_ACKBAR_TYPESEL) -#define BIT_GET_ACKBAR_TYPESEL(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL) & BIT_MASK_ACKBAR_TYPESEL) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_ACKBAR_ACKPCHK (44 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_ACKPCHK 0xf -#define BIT_ACKBAR_ACKPCHK(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK) << BIT_SHIFT_ACKBAR_ACKPCHK) -#define BIT_GET_ACKBAR_ACKPCHK(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK) & BIT_MASK_ACKBAR_ACKPCHK) +/* 2 REG_TIMER0 (Offset 0x0584) */ +#define BIT_SHIFT_TIMER0_INT 5 +#define BIT_MASK_TIMER0_INT 0x7ffffff +#define BIT_TIMER0_INT(x) (((x) & BIT_MASK_TIMER0_INT) << BIT_SHIFT_TIMER0_INT) +#define BITS_TIMER0_INT (BIT_MASK_TIMER0_INT << BIT_SHIFT_TIMER0_INT) +#define BIT_CLEAR_TIMER0_INT(x) ((x) & (~BITS_TIMER0_INT)) +#define BIT_GET_TIMER0_INT(x) \ + (((x) >> BIT_SHIFT_TIMER0_INT) & BIT_MASK_TIMER0_INT) +#define BIT_SET_TIMER0_INT(x, v) (BIT_CLEAR_TIMER0_INT(x) | BIT_TIMER0_INT(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PS_TIMER1 (Offset 0x0584) */ +#define BIT_SHIFT_PSTIMER1_INT 5 +#define BIT_MASK_PSTIMER1_INT 0x7ffffff +#define BIT_PSTIMER1_INT(x) \ + (((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT) +#define BITS_PSTIMER1_INT (BIT_MASK_PSTIMER1_INT << BIT_SHIFT_PSTIMER1_INT) +#define BIT_CLEAR_PSTIMER1_INT(x) ((x) & (~BITS_PSTIMER1_INT)) +#define BIT_GET_PSTIMER1_INT(x) \ + (((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT) +#define BIT_SET_PSTIMER1_INT(x, v) \ + (BIT_CLEAR_PSTIMER1_INT(x) | BIT_PSTIMER1_INT(v)) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +/* 2 REG_PS_TIMER2 (Offset 0x0588) */ -#define BIT_RXBA_IGNOREA2 BIT(42) -#define BIT_EN_SAVE_ALL_TXOPADDR BIT(41) -#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40) +#define BIT_SHIFT_INFO_INDEX_OFFSET 16 +#define BIT_MASK_INFO_INDEX_OFFSET 0x1fff +#define BIT_INFO_INDEX_OFFSET(x) \ + (((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET) +#define BITS_INFO_INDEX_OFFSET \ + (BIT_MASK_INFO_INDEX_OFFSET << BIT_SHIFT_INFO_INDEX_OFFSET) +#define BIT_CLEAR_INFO_INDEX_OFFSET(x) ((x) & (~BITS_INFO_INDEX_OFFSET)) +#define BIT_GET_INFO_INDEX_OFFSET(x) \ + (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET) +#define BIT_SET_INFO_INDEX_OFFSET(x, v) \ + (BIT_CLEAR_INFO_INDEX_OFFSET(x) | BIT_INFO_INDEX_OFFSET(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TIMER1 (Offset 0x0588) */ +#define BIT_SHIFT_TIMER1_INT 5 +#define BIT_MASK_TIMER1_INT 0x7ffffff +#define BIT_TIMER1_INT(x) (((x) & BIT_MASK_TIMER1_INT) << BIT_SHIFT_TIMER1_INT) +#define BITS_TIMER1_INT (BIT_MASK_TIMER1_INT << BIT_SHIFT_TIMER1_INT) +#define BIT_CLEAR_TIMER1_INT(x) ((x) & (~BITS_TIMER1_INT)) +#define BIT_GET_TIMER1_INT(x) \ + (((x) >> BIT_SHIFT_TIMER1_INT) & BIT_MASK_TIMER1_INT) +#define BIT_SET_TIMER1_INT(x, v) (BIT_CLEAR_TIMER1_INT(x) | BIT_TIMER1_INT(v)) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#endif -#define BIT_DIS_TXBA_AMPDUFCSERR BIT(39) -#define BIT_DIS_TXBA_RXBARINFULL BIT(38) -#define BIT_DIS_TXCFE_INFULL BIT(37) -#define BIT_DIS_TXCTS_INFULL BIT(36) -#define BIT_EN_TXACKBA_IN_TX_RDG BIT(35) -#define BIT_EN_TXACKBA_IN_TXOP BIT(34) -#define BIT_EN_TXCTS_IN_RXNAV BIT(33) -#define BIT_EN_TXCTS_INTXOP BIT(32) -#define BIT_BLK_EDCA_BBSLP BIT(31) -#define BIT_BLK_EDCA_BBSBY BIT(30) -#define BIT_ACKTO_BLOCK_SCH_EN BIT(27) -#define BIT_EIFS_BLOCK_SCH_EN BIT(26) -#define BIT_PLCPCHK_RST_EIFS BIT(25) -#define BIT_CCA_RST_EIFS BIT(24) -#define BIT_DIS_UPD_MYRXPKTNAV BIT(23) -#define BIT_EARLY_TXBA BIT(22) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RESP_CHNBUSY 20 -#define BIT_MASK_RESP_CHNBUSY 0x3 -#define BIT_RESP_CHNBUSY(x) (((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY) -#define BIT_GET_RESP_CHNBUSY(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY) +/* 2 REG_PS_TIMER2 (Offset 0x0588) */ -#define BIT_RESP_DCTS_EN BIT(19) -#define BIT_RESP_DCFE_EN BIT(18) -#define BIT_RESP_SPLCPEN BIT(17) -#define BIT_RESP_SGIEN BIT(16) +#define BIT_SHIFT_PSTIMER2_INT 5 +#define BIT_MASK_PSTIMER2_INT 0x7ffffff +#define BIT_PSTIMER2_INT(x) \ + (((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT) +#define BITS_PSTIMER2_INT (BIT_MASK_PSTIMER2_INT << BIT_SHIFT_PSTIMER2_INT) +#define BIT_CLEAR_PSTIMER2_INT(x) ((x) & (~BITS_PSTIMER2_INT)) +#define BIT_GET_PSTIMER2_INT(x) \ + (((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT) +#define BIT_SET_PSTIMER2_INT(x, v) \ + (BIT_CLEAR_PSTIMER2_INT(x) | BIT_PSTIMER2_INT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TBTT_CTN_AREA (Offset 0x058C) */ +#define BIT_SHIFT_TBTT_CTN_AREA 0 +#define BIT_MASK_TBTT_CTN_AREA 0xff +#define BIT_TBTT_CTN_AREA(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA) +#define BITS_TBTT_CTN_AREA (BIT_MASK_TBTT_CTN_AREA << BIT_SHIFT_TBTT_CTN_AREA) +#define BIT_CLEAR_TBTT_CTN_AREA(x) ((x) & (~BITS_TBTT_CTN_AREA)) +#define BIT_GET_TBTT_CTN_AREA(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA) +#define BIT_SET_TBTT_CTN_AREA(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA(x) | BIT_TBTT_CTN_AREA(v)) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +/* 2 REG_FORCE_BCN_IFS (Offset 0x058E) */ -#define BIT_RESP_LDPC_EN BIT(15) -#define BIT_DIS_RESP_ACKINCCA BIT(14) -#define BIT_DIS_RESP_CTSINCCA BIT(13) +#define BIT_SHIFT_FORCE_BCN_IFS 0 +#define BIT_MASK_FORCE_BCN_IFS 0xff +#define BIT_FORCE_BCN_IFS(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS) +#define BITS_FORCE_BCN_IFS (BIT_MASK_FORCE_BCN_IFS << BIT_SHIFT_FORCE_BCN_IFS) +#define BIT_CLEAR_FORCE_BCN_IFS(x) ((x) & (~BITS_FORCE_BCN_IFS)) +#define BIT_GET_FORCE_BCN_IFS(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS) +#define BIT_SET_FORCE_BCN_IFS(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS(x) | BIT_FORCE_BCN_IFS(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DRVERLYINT_V1 (Offset 0x058F) */ +#define BIT_SHIFT_PRE_BCN_DMATIM 0 +#define BIT_MASK_PRE_BCN_DMATIM 0xff +#define BIT_PRE_BCN_DMATIM(x) \ + (((x) & BIT_MASK_PRE_BCN_DMATIM) << BIT_SHIFT_PRE_BCN_DMATIM) +#define BITS_PRE_BCN_DMATIM \ + (BIT_MASK_PRE_BCN_DMATIM << BIT_SHIFT_PRE_BCN_DMATIM) +#define BIT_CLEAR_PRE_BCN_DMATIM(x) ((x) & (~BITS_PRE_BCN_DMATIM)) +#define BIT_GET_PRE_BCN_DMATIM(x) \ + (((x) >> BIT_SHIFT_PRE_BCN_DMATIM) & BIT_MASK_PRE_BCN_DMATIM) +#define BIT_SET_PRE_BCN_DMATIM(x, v) \ + (BIT_CLEAR_PRE_BCN_DMATIM(x) | BIT_PRE_BCN_DMATIM(v)) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10 -#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7 -#define BIT_R_WMAC_SECOND_CCA_TIMER(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) -#define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) +/* 2 REG_TXOP_MIN (Offset 0x0590) */ +#define BIT_NAV_BLK_HGQ BIT(15) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_TXOP_MIN (Offset 0x0590) */ +#define BIT_HIQ_NAV_BREAK_EN BIT(15) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_SECOND_CCA_CNT 10 -#define BIT_MASK_SECOND_CCA_CNT 0x7 -#define BIT_SECOND_CCA_CNT(x) (((x) & BIT_MASK_SECOND_CCA_CNT) << BIT_SHIFT_SECOND_CCA_CNT) -#define BIT_GET_SECOND_CCA_CNT(x) (((x) >> BIT_SHIFT_SECOND_CCA_CNT) & BIT_MASK_SECOND_CCA_CNT) +/* 2 REG_TXOP_MIN (Offset 0x0590) */ +#define BIT_NAV_BLK_MGQ BIT(14) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXOP_MIN (Offset 0x0590) */ +#define BIT_MGQ_NAV_BREAK_EN BIT(14) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXOP_MIN (Offset 0x0590) */ + +#define BIT_SHIFT_TXOP_MIN 0 +#define BIT_MASK_TXOP_MIN 0x3fff +#define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN) +#define BITS_TXOP_MIN (BIT_MASK_TXOP_MIN << BIT_SHIFT_TXOP_MIN) +#define BIT_CLEAR_TXOP_MIN(x) ((x) & (~BITS_TXOP_MIN)) +#define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN) +#define BIT_SET_TXOP_MIN(x, v) (BIT_CLEAR_TXOP_MIN(x) | BIT_TXOP_MIN(v)) -#define BIT_SHIFT_RFMOD 7 -#define BIT_MASK_RFMOD 0x3 -#define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD) -#define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD) +/* 2 REG_PRE_BKF_TIME (Offset 0x0592) */ +#define BIT_SHIFT_PRE_BKF_TIME 0 +#define BIT_MASK_PRE_BKF_TIME 0xff +#define BIT_PRE_BKF_TIME(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME) +#define BITS_PRE_BKF_TIME (BIT_MASK_PRE_BKF_TIME << BIT_SHIFT_PRE_BKF_TIME) +#define BIT_CLEAR_PRE_BKF_TIME(x) ((x) & (~BITS_PRE_BKF_TIME)) +#define BIT_GET_PRE_BKF_TIME(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME) +#define BIT_SET_PRE_BKF_TIME(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME(x) | BIT_PRE_BKF_TIME(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ +#define BIT_NOPKT_END_RTSMF BIT(7) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_RF_MOD 7 -#define BIT_MASK_RF_MOD 0x3 -#define BIT_RF_MOD(x) (((x) & BIT_MASK_RF_MOD) << BIT_SHIFT_RF_MOD) -#define BIT_GET_RF_MOD(x) (((x) >> BIT_SHIFT_RF_MOD) & BIT_MASK_RF_MOD) +/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ +#define BIT_TBTT_RETRY BIT(4) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ +#define BIT_SHIFT_PRETX_US 3 +#define BIT_MASK_PRETX_US 0xf +#define BIT_PRETX_US(x) (((x) & BIT_MASK_PRETX_US) << BIT_SHIFT_PRETX_US) +#define BITS_PRETX_US (BIT_MASK_PRETX_US << BIT_SHIFT_PRETX_US) +#define BIT_CLEAR_PRETX_US(x) ((x) & (~BITS_PRETX_US)) +#define BIT_GET_PRETX_US(x) (((x) >> BIT_SHIFT_PRETX_US) & BIT_MASK_PRETX_US) +#define BIT_SET_PRETX_US(x, v) (BIT_CLEAR_PRETX_US(x) | BIT_PRETX_US(v)) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5 -#define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3 -#define BIT_RESP_CTS_DYNBW_SEL(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL) -#define BIT_GET_RESP_CTS_DYNBW_SEL(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL) +/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ +#define BIT_TXOP_FAIL_BREAK BIT(3) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ +#define BIT_TXFAIL_BREACK_TXOP_EN BIT(3) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL 5 -#define BIT_MASK_RESP_CTS_BW_DYNBW_SEL 0x3 -#define BIT_RESP_CTS_BW_DYNBW_SEL(x) (((x) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) -#define BIT_GET_RESP_CTS_BW_DYNBW_SEL(x) (((x) >> BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL) +/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ +#define BIT_DTIM_BYPASS BIT(2) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ +#define BIT_RTS_NAV_TXOP BIT(1) +#define BIT_NOT_CROSS_TXOP BIT(0) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#endif -#define BIT_DLY_TX_WAIT_RXANTSEL BIT(4) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_TBTT_INT_SHIFT_CLI0 (Offset 0x0594) */ +#define BIT_TBTT_INT_SHIFT_DIR_CLI0 BIT(7) -#if (HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +/* 2 REG_FREERUN_CNT_L (Offset 0x0594) */ -#define BIT_DELAY_TX_USE_RX_ANTSEL BIT(4) +#define BIT_SHIFT_FREERUN_CNT_L 0 +#define BIT_MASK_FREERUN_CNT_L 0xffffffffL +#define BIT_FREERUN_CNT_L(x) \ + (((x) & BIT_MASK_FREERUN_CNT_L) << BIT_SHIFT_FREERUN_CNT_L) +#define BITS_FREERUN_CNT_L (BIT_MASK_FREERUN_CNT_L << BIT_SHIFT_FREERUN_CNT_L) +#define BIT_CLEAR_FREERUN_CNT_L(x) ((x) & (~BITS_FREERUN_CNT_L)) +#define BIT_GET_FREERUN_CNT_L(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_L) & BIT_MASK_FREERUN_CNT_L) +#define BIT_SET_FREERUN_CNT_L(x, v) \ + (BIT_CLEAR_FREERUN_CNT_L(x) | BIT_FREERUN_CNT_L(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_TBTT_INT_SHIFT_CLI0 (Offset 0x0594) */ -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI0 0x7f +#define BIT_TBTT_INT_SHIFT_CLI0(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0) +#define BITS_TBTT_INT_SHIFT_CLI0 \ + (BIT_MASK_TBTT_INT_SHIFT_CLI0 << BIT_SHIFT_TBTT_INT_SHIFT_CLI0) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI0)) +#define BIT_GET_TBTT_INT_SHIFT_CLI0(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0) & BIT_MASK_TBTT_INT_SHIFT_CLI0) +#define BIT_SET_TBTT_INT_SHIFT_CLI0(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) | BIT_TBTT_INT_SHIFT_CLI0(v)) -#define BIT_TXRESP_BY_RXANTSEL BIT(3) +/* 2 REG_TBTT_INT_SHIFT_CLI1 (Offset 0x0595) */ -#endif +#define BIT_TBTT_INT_SHIFT_DIR_CLI1 BIT(7) +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI1 0x7f +#define BIT_TBTT_INT_SHIFT_CLI1(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1) +#define BITS_TBTT_INT_SHIFT_CLI1 \ + (BIT_MASK_TBTT_INT_SHIFT_CLI1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI1) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI1)) +#define BIT_GET_TBTT_INT_SHIFT_CLI1(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1) & BIT_MASK_TBTT_INT_SHIFT_CLI1) +#define BIT_SET_TBTT_INT_SHIFT_CLI1(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) | BIT_TBTT_INT_SHIFT_CLI1(v)) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_TBTT_INT_SHIFT_CLI2 (Offset 0x0596) */ +#define BIT_TBTT_INT_SHIFT_DIR_CLI2 BIT(7) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI2 0x7f +#define BIT_TBTT_INT_SHIFT_CLI2(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2) +#define BITS_TBTT_INT_SHIFT_CLI2 \ + (BIT_MASK_TBTT_INT_SHIFT_CLI2 << BIT_SHIFT_TBTT_INT_SHIFT_CLI2) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI2)) +#define BIT_GET_TBTT_INT_SHIFT_CLI2(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2) & BIT_MASK_TBTT_INT_SHIFT_CLI2) +#define BIT_SET_TBTT_INT_SHIFT_CLI2(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) | BIT_TBTT_INT_SHIFT_CLI2(v)) -#define BIT_TX_USE_RX_ANTSEL BIT(3) +/* 2 REG_TBTT_INT_SHIFT_CLI3 (Offset 0x0597) */ -#endif +#define BIT_TBTT_INT_SHIFT_DIR_CLI3 BIT(7) +#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3 0 +#define BIT_MASK_TBTT_INT_SHIFT_CLI3 0x7f +#define BIT_TBTT_INT_SHIFT_CLI3(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3) +#define BITS_TBTT_INT_SHIFT_CLI3 \ + (BIT_MASK_TBTT_INT_SHIFT_CLI3 << BIT_SHIFT_TBTT_INT_SHIFT_CLI3) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI3)) +#define BIT_GET_TBTT_INT_SHIFT_CLI3(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3) & BIT_MASK_TBTT_INT_SHIFT_CLI3) +#define BIT_SET_TBTT_INT_SHIFT_CLI3(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) | BIT_TBTT_INT_SHIFT_CLI3(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +/* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */ -#define BIT_RESP_EARLY_TXACK_RWEPTKIP BIT(2) +#define BIT_RX_TBTT_SHIFT_RW_FLAG_V1 BIT(31) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ +#define BIT_BCNERR_CNT_EN BIT(20) -/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_ORIG_DCTS_CHK 0 -#define BIT_MASK_ORIG_DCTS_CHK 0x3 -#define BIT_ORIG_DCTS_CHK(x) (((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK) -#define BIT_GET_ORIG_DCTS_CHK(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK) +/* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */ +#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1 16 +#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 0xfff +#define BIT_RX_TBTT_SHIFT_OFFSET_V1(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1) \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) +#define BITS_RX_TBTT_SHIFT_OFFSET_V1 \ + (BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) +#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x) \ + ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_V1)) +#define BIT_GET_RX_TBTT_SHIFT_OFFSET_V1(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) & \ + BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1) +#define BIT_SET_RX_TBTT_SHIFT_OFFSET_V1(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x) | BIT_RX_TBTT_SHIFT_OFFSET_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ +#define BIT_CHANGE_POW_BCN_AREA BIT(9) -/* 2 REG_CAMCMD (Offset 0x0670) */ +#endif -#define BIT_SECCAM_POLLING BIT(31) -#define BIT_SECCAM_CLR BIT(30) -#define BIT_MFBCAM_CLR BIT(29) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */ +#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1 8 +#define BIT_MASK_RX_TBTT_SHIFT_SEL_V1 0x7 +#define BIT_RX_TBTT_SHIFT_SEL_V1(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_V1) \ + << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) +#define BITS_RX_TBTT_SHIFT_SEL_V1 \ + (BIT_MASK_RX_TBTT_SHIFT_SEL_V1 << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) +#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL_V1)) +#define BIT_GET_RX_TBTT_SHIFT_SEL_V1(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) & \ + BIT_MASK_RX_TBTT_SHIFT_SEL_V1) +#define BIT_SET_RX_TBTT_SHIFT_SEL_V1(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) | BIT_RX_TBTT_SHIFT_SEL_V1(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_CAMCMD (Offset 0x0670) */ +/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ -#define BIT_SECCAM_WE BIT(16) +#define BIT_EN_TBTT_RTY BIT(1) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_FREERUN_CNT_H (Offset 0x0598) */ -/* 2 REG_CAMCMD (Offset 0x0670) */ +#define BIT_SHIFT_FREERUN_CNT_H 0 +#define BIT_MASK_FREERUN_CNT_H 0xffffffffL +#define BIT_FREERUN_CNT_H(x) \ + (((x) & BIT_MASK_FREERUN_CNT_H) << BIT_SHIFT_FREERUN_CNT_H) +#define BITS_FREERUN_CNT_H (BIT_MASK_FREERUN_CNT_H << BIT_SHIFT_FREERUN_CNT_H) +#define BIT_CLEAR_FREERUN_CNT_H(x) ((x) & (~BITS_FREERUN_CNT_H)) +#define BIT_GET_FREERUN_CNT_H(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_H) & BIT_MASK_FREERUN_CNT_H) +#define BIT_SET_FREERUN_CNT_H(x, v) \ + (BIT_CLEAR_FREERUN_CNT_H(x) | BIT_FREERUN_CNT_H(v)) +#endif -#define BIT_SHIFT_SECCAM_ADDR_V1 0 -#define BIT_MASK_SECCAM_ADDR_V1 0xff -#define BIT_SECCAM_ADDR_V1(x) (((x) & BIT_MASK_SECCAM_ADDR_V1) << BIT_SHIFT_SECCAM_ADDR_V1) -#define BIT_GET_SECCAM_ADDR_V1(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V1) & BIT_MASK_SECCAM_ADDR_V1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) +/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */ -#define BIT_SHIFT_WKFCAM_NUM 0 -#define BIT_MASK_WKFCAM_NUM 0x7f -#define BIT_WKFCAM_NUM(x) (((x) & BIT_MASK_WKFCAM_NUM) << BIT_SHIFT_WKFCAM_NUM) -#define BIT_GET_WKFCAM_NUM(x) (((x) >> BIT_SHIFT_WKFCAM_NUM) & BIT_MASK_WKFCAM_NUM) +#define BIT_TBTT_INT_SHIFT_ENABLE BIT(0) +#define BIT_SHIFT_BCN_ELY_ADJ 0 +#define BIT_MASK_BCN_ELY_ADJ 0xffff +#define BIT_BCN_ELY_ADJ(x) \ + (((x) & BIT_MASK_BCN_ELY_ADJ) << BIT_SHIFT_BCN_ELY_ADJ) +#define BITS_BCN_ELY_ADJ (BIT_MASK_BCN_ELY_ADJ << BIT_SHIFT_BCN_ELY_ADJ) +#define BIT_CLEAR_BCN_ELY_ADJ(x) ((x) & (~BITS_BCN_ELY_ADJ)) +#define BIT_GET_BCN_ELY_ADJ(x) \ + (((x) >> BIT_SHIFT_BCN_ELY_ADJ) & BIT_MASK_BCN_ELY_ADJ) +#define BIT_SET_BCN_ELY_ADJ(x, v) \ + (BIT_CLEAR_BCN_ELY_ADJ(x) | BIT_BCN_ELY_ADJ(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ATIMWND2 (Offset 0x05A0) */ +#define BIT_SHIFT_ATIMWND2 0 +#define BIT_MASK_ATIMWND2 0xff +#define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2) +#define BITS_ATIMWND2 (BIT_MASK_ATIMWND2 << BIT_SHIFT_ATIMWND2) +#define BIT_CLEAR_ATIMWND2(x) ((x) & (~BITS_ATIMWND2)) +#define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2) +#define BIT_SET_ATIMWND2(x, v) (BIT_CLEAR_ATIMWND2(x) | BIT_ATIMWND2(v)) -/* 2 REG_CAMCMD (Offset 0x0670) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_SECCAM_ADDR_V2 0 -#define BIT_MASK_SECCAM_ADDR_V2 0x3ff -#define BIT_SECCAM_ADDR_V2(x) (((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2) -#define BIT_GET_SECCAM_ADDR_V2(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2) +/* 2 REG_ATIMWND_GROUP1 (Offset 0x05A0) */ +#define BIT_SHIFT_ATIMWND_GROUP1 0 +#define BIT_MASK_ATIMWND_GROUP1 0xff +#define BIT_ATIMWND_GROUP1(x) \ + (((x) & BIT_MASK_ATIMWND_GROUP1) << BIT_SHIFT_ATIMWND_GROUP1) +#define BITS_ATIMWND_GROUP1 \ + (BIT_MASK_ATIMWND_GROUP1 << BIT_SHIFT_ATIMWND_GROUP1) +#define BIT_CLEAR_ATIMWND_GROUP1(x) ((x) & (~BITS_ATIMWND_GROUP1)) +#define BIT_GET_ATIMWND_GROUP1(x) \ + (((x) >> BIT_SHIFT_ATIMWND_GROUP1) & BIT_MASK_ATIMWND_GROUP1) +#define BIT_SET_ATIMWND_GROUP1(x, v) \ + (BIT_CLEAR_ATIMWND_GROUP1(x) | BIT_ATIMWND_GROUP1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_ATIMWND3 (Offset 0x05A1) */ +#define BIT_SHIFT_ATIMWND3 0 +#define BIT_MASK_ATIMWND3 0xff +#define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3) +#define BITS_ATIMWND3 (BIT_MASK_ATIMWND3 << BIT_SHIFT_ATIMWND3) +#define BIT_CLEAR_ATIMWND3(x) ((x) & (~BITS_ATIMWND3)) +#define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3) +#define BIT_SET_ATIMWND3(x, v) (BIT_CLEAR_ATIMWND3(x) | BIT_ATIMWND3(v)) -/* 2 REG_CAMCMD (Offset 0x0670) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_SECCAM_ADDR 0 -#define BIT_MASK_SECCAM_ADDR 0xff -#define BIT_SECCAM_ADDR(x) (((x) & BIT_MASK_SECCAM_ADDR) << BIT_SHIFT_SECCAM_ADDR) -#define BIT_GET_SECCAM_ADDR(x) (((x) >> BIT_SHIFT_SECCAM_ADDR) & BIT_MASK_SECCAM_ADDR) +/* 2 REG_ATIMWND_GROUP2 (Offset 0x05A1) */ +#define BIT_SHIFT_ATIMWND_GROUP2 0 +#define BIT_MASK_ATIMWND_GROUP2 0xff +#define BIT_ATIMWND_GROUP2(x) \ + (((x) & BIT_MASK_ATIMWND_GROUP2) << BIT_SHIFT_ATIMWND_GROUP2) +#define BITS_ATIMWND_GROUP2 \ + (BIT_MASK_ATIMWND_GROUP2 << BIT_SHIFT_ATIMWND_GROUP2) +#define BIT_CLEAR_ATIMWND_GROUP2(x) ((x) & (~BITS_ATIMWND_GROUP2)) +#define BIT_GET_ATIMWND_GROUP2(x) \ + (((x) >> BIT_SHIFT_ATIMWND_GROUP2) & BIT_MASK_ATIMWND_GROUP2) +#define BIT_SET_ATIMWND_GROUP2(x, v) \ + (BIT_CLEAR_ATIMWND_GROUP2(x) | BIT_ATIMWND_GROUP2(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_ATIMWND4 (Offset 0x05A2) */ +#define BIT_SHIFT_ATIMWND4 0 +#define BIT_MASK_ATIMWND4 0xff +#define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4) +#define BITS_ATIMWND4 (BIT_MASK_ATIMWND4 << BIT_SHIFT_ATIMWND4) +#define BIT_CLEAR_ATIMWND4(x) ((x) & (~BITS_ATIMWND4)) +#define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4) +#define BIT_SET_ATIMWND4(x, v) (BIT_CLEAR_ATIMWND4(x) | BIT_ATIMWND4(v)) -/* 2 REG_CAMWRITE (Offset 0x0674) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_CAMW_DATA 0 -#define BIT_MASK_CAMW_DATA 0xffffffffL -#define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA) -#define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA) +/* 2 REG_ATIMWND_GROUP3 (Offset 0x05A2) */ +#define BIT_SHIFT_ATIMWND_GROUP3 0 +#define BIT_MASK_ATIMWND_GROUP3 0xff +#define BIT_ATIMWND_GROUP3(x) \ + (((x) & BIT_MASK_ATIMWND_GROUP3) << BIT_SHIFT_ATIMWND_GROUP3) +#define BITS_ATIMWND_GROUP3 \ + (BIT_MASK_ATIMWND_GROUP3 << BIT_SHIFT_ATIMWND_GROUP3) +#define BIT_CLEAR_ATIMWND_GROUP3(x) ((x) & (~BITS_ATIMWND_GROUP3)) +#define BIT_GET_ATIMWND_GROUP3(x) \ + (((x) >> BIT_SHIFT_ATIMWND_GROUP3) & BIT_MASK_ATIMWND_GROUP3) +#define BIT_SET_ATIMWND_GROUP3(x, v) \ + (BIT_CLEAR_ATIMWND_GROUP3(x) | BIT_ATIMWND_GROUP3(v)) -/* 2 REG_CAMREAD (Offset 0x0678) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CAMR_DATA 0 -#define BIT_MASK_CAMR_DATA 0xffffffffL -#define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA) -#define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA) +/* 2 REG_ATIMWND5 (Offset 0x05A3) */ +#define BIT_SHIFT_ATIMWND5 0 +#define BIT_MASK_ATIMWND5 0xff +#define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5) +#define BITS_ATIMWND5 (BIT_MASK_ATIMWND5 << BIT_SHIFT_ATIMWND5) +#define BIT_CLEAR_ATIMWND5(x) ((x) & (~BITS_ATIMWND5)) +#define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5) +#define BIT_SET_ATIMWND5(x, v) (BIT_CLEAR_ATIMWND5(x) | BIT_ATIMWND5(v)) -/* 2 REG_CAMDBG (Offset 0x067C) */ +#endif -#define BIT_SECCAM_INFO BIT(31) -#define BIT_SEC_KEYFOUND BIT(15) +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_CAMDBG_SEC_TYPE 12 -#define BIT_MASK_CAMDBG_SEC_TYPE 0x7 -#define BIT_CAMDBG_SEC_TYPE(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE) -#define BIT_GET_CAMDBG_SEC_TYPE(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE) +/* 2 REG_ATIMWND_GROUP4 (Offset 0x05A3) */ +#define BIT_SHIFT_ATIMWND_GROUP4 0 +#define BIT_MASK_ATIMWND_GROUP4 0xff +#define BIT_ATIMWND_GROUP4(x) \ + (((x) & BIT_MASK_ATIMWND_GROUP4) << BIT_SHIFT_ATIMWND_GROUP4) +#define BITS_ATIMWND_GROUP4 \ + (BIT_MASK_ATIMWND_GROUP4 << BIT_SHIFT_ATIMWND_GROUP4) +#define BIT_CLEAR_ATIMWND_GROUP4(x) ((x) & (~BITS_ATIMWND_GROUP4)) +#define BIT_GET_ATIMWND_GROUP4(x) \ + (((x) >> BIT_SHIFT_ATIMWND_GROUP4) & BIT_MASK_ATIMWND_GROUP4) +#define BIT_SET_ATIMWND_GROUP4(x, v) \ + (BIT_CLEAR_ATIMWND_GROUP4(x) | BIT_ATIMWND_GROUP4(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_CAMDBG (Offset 0x067C) */ +/* 2 REG_ATIMWND6 (Offset 0x05A4) */ -#define BIT_CAMDBG_EXT_SEC_TYPE BIT(11) +#define BIT_SHIFT_ATIMWND6 0 +#define BIT_MASK_ATIMWND6 0xff +#define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6) +#define BITS_ATIMWND6 (BIT_MASK_ATIMWND6 << BIT_SHIFT_ATIMWND6) +#define BIT_CLEAR_ATIMWND6(x) ((x) & (~BITS_ATIMWND6)) +#define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6) +#define BIT_SET_ATIMWND6(x, v) (BIT_CLEAR_ATIMWND6(x) | BIT_ATIMWND6(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_CAMDBG (Offset 0x067C) */ +/* 2 REG_DTIM_COUNT_GROUP1 (Offset 0x05A4) */ -#define BIT_CAMDBG_EXT_SECTYPE BIT(11) +#define BIT_SHIFT_DTIM_COUNT_GROUP1 0 +#define BIT_MASK_DTIM_COUNT_GROUP1 0xff +#define BIT_DTIM_COUNT_GROUP1(x) \ + (((x) & BIT_MASK_DTIM_COUNT_GROUP1) << BIT_SHIFT_DTIM_COUNT_GROUP1) +#define BITS_DTIM_COUNT_GROUP1 \ + (BIT_MASK_DTIM_COUNT_GROUP1 << BIT_SHIFT_DTIM_COUNT_GROUP1) +#define BIT_CLEAR_DTIM_COUNT_GROUP1(x) ((x) & (~BITS_DTIM_COUNT_GROUP1)) +#define BIT_GET_DTIM_COUNT_GROUP1(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP1) & BIT_MASK_DTIM_COUNT_GROUP1) +#define BIT_SET_DTIM_COUNT_GROUP1(x, v) \ + (BIT_CLEAR_DTIM_COUNT_GROUP1(x) | BIT_DTIM_COUNT_GROUP1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_CAMDBG (Offset 0x067C) */ +/* 2 REG_ATIMWND7 (Offset 0x05A5) */ +#define BIT_SHIFT_ATIMWND7 0 +#define BIT_MASK_ATIMWND7 0xff +#define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7) +#define BITS_ATIMWND7 (BIT_MASK_ATIMWND7 << BIT_SHIFT_ATIMWND7) +#define BIT_CLEAR_ATIMWND7(x) ((x) & (~BITS_ATIMWND7)) +#define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7) +#define BIT_SET_ATIMWND7(x, v) (BIT_CLEAR_ATIMWND7(x) | BIT_ATIMWND7(v)) -#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5 -#define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f -#define BIT_CAMDBG_MIC_KEY_IDX(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX) -#define BIT_GET_CAMDBG_MIC_KEY_IDX(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0 -#define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f -#define BIT_CAMDBG_SEC_KEY_IDX(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX) -#define BIT_GET_CAMDBG_SEC_KEY_IDX(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX) +/* 2 REG_DTIM_COUNT_GROUP2 (Offset 0x05A5) */ +#define BIT_SHIFT_DTIM_COUNT_GROUP2 0 +#define BIT_MASK_DTIM_COUNT_GROUP2 0xff +#define BIT_DTIM_COUNT_GROUP2(x) \ + (((x) & BIT_MASK_DTIM_COUNT_GROUP2) << BIT_SHIFT_DTIM_COUNT_GROUP2) +#define BITS_DTIM_COUNT_GROUP2 \ + (BIT_MASK_DTIM_COUNT_GROUP2 << BIT_SHIFT_DTIM_COUNT_GROUP2) +#define BIT_CLEAR_DTIM_COUNT_GROUP2(x) ((x) & (~BITS_DTIM_COUNT_GROUP2)) +#define BIT_GET_DTIM_COUNT_GROUP2(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP2) & BIT_MASK_DTIM_COUNT_GROUP2) +#define BIT_SET_DTIM_COUNT_GROUP2(x, v) \ + (BIT_CLEAR_DTIM_COUNT_GROUP2(x) | BIT_DTIM_COUNT_GROUP2(v)) -/* 2 REG_SECCFG (Offset 0x0680) */ +/* 2 REG_DTIM_COUNT_GROUP3 (Offset 0x05A6) */ -#define BIT_DIS_GCLK_WAPI BIT(15) -#define BIT_DIS_GCLK_AES BIT(14) -#define BIT_DIS_GCLK_TKIP BIT(13) +#define BIT_SHIFT_DTIM_COUNT_GROUP3 0 +#define BIT_MASK_DTIM_COUNT_GROUP3 0xff +#define BIT_DTIM_COUNT_GROUP3(x) \ + (((x) & BIT_MASK_DTIM_COUNT_GROUP3) << BIT_SHIFT_DTIM_COUNT_GROUP3) +#define BITS_DTIM_COUNT_GROUP3 \ + (BIT_MASK_DTIM_COUNT_GROUP3 << BIT_SHIFT_DTIM_COUNT_GROUP3) +#define BIT_CLEAR_DTIM_COUNT_GROUP3(x) ((x) & (~BITS_DTIM_COUNT_GROUP3)) +#define BIT_GET_DTIM_COUNT_GROUP3(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP3) & BIT_MASK_DTIM_COUNT_GROUP3) +#define BIT_SET_DTIM_COUNT_GROUP3(x, v) \ + (BIT_CLEAR_DTIM_COUNT_GROUP3(x) | BIT_DTIM_COUNT_GROUP3(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_SECCFG (Offset 0x0680) */ +/* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */ -#define BIT_AES_SEL_QC_1 BIT(12) -#define BIT_AES_SEL_QC_0 BIT(11) +#define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7) +#define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6) +#define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5) +#define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4) +#define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3) +#define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2) +#define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */ +#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_DTIM_COUNT_GROUP4 (Offset 0x05A7) */ + +#define BIT_SHIFT_DTIM_COUNT_GROUP4 0 +#define BIT_MASK_DTIM_COUNT_GROUP4 0xff +#define BIT_DTIM_COUNT_GROUP4(x) \ + (((x) & BIT_MASK_DTIM_COUNT_GROUP4) << BIT_SHIFT_DTIM_COUNT_GROUP4) +#define BITS_DTIM_COUNT_GROUP4 \ + (BIT_MASK_DTIM_COUNT_GROUP4 << BIT_SHIFT_DTIM_COUNT_GROUP4) +#define BIT_CLEAR_DTIM_COUNT_GROUP4(x) ((x) & (~BITS_DTIM_COUNT_GROUP4)) +#define BIT_GET_DTIM_COUNT_GROUP4(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP4) & BIT_MASK_DTIM_COUNT_GROUP4) +#define BIT_SET_DTIM_COUNT_GROUP4(x, v) \ + (BIT_CLEAR_DTIM_COUNT_GROUP4(x) | BIT_DTIM_COUNT_GROUP4(v)) + +/* 2 REG_HIQ_NO_LMT_EN_V2 (Offset 0x05A8) */ + +#define BIT_SHIFT_ATIM_CFG_SEL 24 +#define BIT_MASK_ATIM_CFG_SEL 0x3 +#define BIT_ATIM_CFG_SEL(x) \ + (((x) & BIT_MASK_ATIM_CFG_SEL) << BIT_SHIFT_ATIM_CFG_SEL) +#define BITS_ATIM_CFG_SEL (BIT_MASK_ATIM_CFG_SEL << BIT_SHIFT_ATIM_CFG_SEL) +#define BIT_CLEAR_ATIM_CFG_SEL(x) ((x) & (~BITS_ATIM_CFG_SEL)) +#define BIT_GET_ATIM_CFG_SEL(x) \ + (((x) >> BIT_SHIFT_ATIM_CFG_SEL) & BIT_MASK_ATIM_CFG_SEL) +#define BIT_SET_ATIM_CFG_SEL(x, v) \ + (BIT_CLEAR_ATIM_CFG_SEL(x) | BIT_ATIM_CFG_SEL(v)) + +#define BIT_SHIFT_DIS_ATIM 16 +#define BIT_MASK_DIS_ATIM 0xffff +#define BIT_DIS_ATIM(x) (((x) & BIT_MASK_DIS_ATIM) << BIT_SHIFT_DIS_ATIM) +#define BITS_DIS_ATIM (BIT_MASK_DIS_ATIM << BIT_SHIFT_DIS_ATIM) +#define BIT_CLEAR_DIS_ATIM(x) ((x) & (~BITS_DIS_ATIM)) +#define BIT_GET_DIS_ATIM(x) (((x) >> BIT_SHIFT_DIS_ATIM) & BIT_MASK_DIS_ATIM) +#define BIT_SET_DIS_ATIM(x, v) (BIT_CLEAR_DIS_ATIM(x) | BIT_DIS_ATIM(v)) + +#define BIT_SHIFT_ATIM_URGENT_V1 16 +#define BIT_MASK_ATIM_URGENT_V1 0xff +#define BIT_ATIM_URGENT_V1(x) \ + (((x) & BIT_MASK_ATIM_URGENT_V1) << BIT_SHIFT_ATIM_URGENT_V1) +#define BITS_ATIM_URGENT_V1 \ + (BIT_MASK_ATIM_URGENT_V1 << BIT_SHIFT_ATIM_URGENT_V1) +#define BIT_CLEAR_ATIM_URGENT_V1(x) ((x) & (~BITS_ATIM_URGENT_V1)) +#define BIT_GET_ATIM_URGENT_V1(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_V1) & BIT_MASK_ATIM_URGENT_V1) +#define BIT_SET_ATIM_URGENT_V1(x, v) \ + (BIT_CLEAR_ATIM_URGENT_V1(x) | BIT_ATIM_URGENT_V1(v)) + +#define BIT_SHIFT_BCNERR_PORT_SEL_V1 16 +#define BIT_MASK_BCNERR_PORT_SEL_V1 0xf +#define BIT_BCNERR_PORT_SEL_V1(x) \ + (((x) & BIT_MASK_BCNERR_PORT_SEL_V1) << BIT_SHIFT_BCNERR_PORT_SEL_V1) +#define BITS_BCNERR_PORT_SEL_V1 \ + (BIT_MASK_BCNERR_PORT_SEL_V1 << BIT_SHIFT_BCNERR_PORT_SEL_V1) +#define BIT_CLEAR_BCNERR_PORT_SEL_V1(x) ((x) & (~BITS_BCNERR_PORT_SEL_V1)) +#define BIT_GET_BCNERR_PORT_SEL_V1(x) \ + (((x) >> BIT_SHIFT_BCNERR_PORT_SEL_V1) & BIT_MASK_BCNERR_PORT_SEL_V1) +#define BIT_SET_BCNERR_PORT_SEL_V1(x, v) \ + (BIT_CLEAR_BCNERR_PORT_SEL_V1(x) | BIT_BCNERR_PORT_SEL_V1(v)) + +#define BIT_DIS_NDPA_NAV_CHK BIT(8) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_SECCFG (Offset 0x0680) */ +/* 2 REG_DTIM_COUNTER_ROOT (Offset 0x05A8) */ -#define BIT_WMAC_CKECK_BMC BIT(9) +#define BIT_SHIFT_DTIM_COUNT_ROOT 0 +#define BIT_MASK_DTIM_COUNT_ROOT 0xff +#define BIT_DTIM_COUNT_ROOT(x) \ + (((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT) +#define BITS_DTIM_COUNT_ROOT \ + (BIT_MASK_DTIM_COUNT_ROOT << BIT_SHIFT_DTIM_COUNT_ROOT) +#define BIT_CLEAR_DTIM_COUNT_ROOT(x) ((x) & (~BITS_DTIM_COUNT_ROOT)) +#define BIT_GET_DTIM_COUNT_ROOT(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT) +#define BIT_SET_DTIM_COUNT_ROOT(x, v) \ + (BIT_CLEAR_DTIM_COUNT_ROOT(x) | BIT_DTIM_COUNT_ROOT(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_HIQ_NO_LMT_EN_V2 (Offset 0x05A8) */ -/* 2 REG_SECCFG (Offset 0x0680) */ - -#define BIT_CHK_BMC BIT(9) +#define BIT_SHIFT_MBID_BCNQ_EN 0 +#define BIT_MASK_MBID_BCNQ_EN 0xffff +#define BIT_MBID_BCNQ_EN(x) \ + (((x) & BIT_MASK_MBID_BCNQ_EN) << BIT_SHIFT_MBID_BCNQ_EN) +#define BITS_MBID_BCNQ_EN (BIT_MASK_MBID_BCNQ_EN << BIT_SHIFT_MBID_BCNQ_EN) +#define BIT_CLEAR_MBID_BCNQ_EN(x) ((x) & (~BITS_MBID_BCNQ_EN)) +#define BIT_GET_MBID_BCNQ_EN(x) \ + (((x) >> BIT_SHIFT_MBID_BCNQ_EN) & BIT_MASK_MBID_BCNQ_EN) +#define BIT_SET_MBID_BCNQ_EN(x, v) \ + (BIT_CLEAR_MBID_BCNQ_EN(x) | BIT_MBID_BCNQ_EN(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_DTIM_COUNTER_VAP1 (Offset 0x05A9) */ +#define BIT_SHIFT_DTIM_COUNT_VAP1 0 +#define BIT_MASK_DTIM_COUNT_VAP1 0xff +#define BIT_DTIM_COUNT_VAP1(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1) +#define BITS_DTIM_COUNT_VAP1 \ + (BIT_MASK_DTIM_COUNT_VAP1 << BIT_SHIFT_DTIM_COUNT_VAP1) +#define BIT_CLEAR_DTIM_COUNT_VAP1(x) ((x) & (~BITS_DTIM_COUNT_VAP1)) +#define BIT_GET_DTIM_COUNT_VAP1(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1) +#define BIT_SET_DTIM_COUNT_VAP1(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP1(x) | BIT_DTIM_COUNT_VAP1(v)) -/* 2 REG_SECCFG (Offset 0x0680) */ +/* 2 REG_DTIM_COUNTER_VAP2 (Offset 0x05AA) */ -#define BIT_CHK_KEYID BIT(8) -#define BIT_RXBCUSEDK BIT(7) -#define BIT_TXBCUSEDK BIT(6) -#define BIT_NOSKMC BIT(5) -#define BIT_SKBYA2 BIT(4) -#define BIT_RXDEC BIT(3) -#define BIT_TXENC BIT(2) -#define BIT_RXUHUSEDK BIT(1) -#define BIT_TXUHUSEDK BIT(0) +#define BIT_SHIFT_DTIM_COUNT_VAP2 0 +#define BIT_MASK_DTIM_COUNT_VAP2 0xff +#define BIT_DTIM_COUNT_VAP2(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2) +#define BITS_DTIM_COUNT_VAP2 \ + (BIT_MASK_DTIM_COUNT_VAP2 << BIT_SHIFT_DTIM_COUNT_VAP2) +#define BIT_CLEAR_DTIM_COUNT_VAP2(x) ((x) & (~BITS_DTIM_COUNT_VAP2)) +#define BIT_GET_DTIM_COUNT_VAP2(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2) +#define BIT_SET_DTIM_COUNT_VAP2(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP2(x) | BIT_DTIM_COUNT_VAP2(v)) -#endif +/* 2 REG_DTIM_COUNTER_VAP3 (Offset 0x05AB) */ +#define BIT_SHIFT_DTIM_COUNT_VAP3 0 +#define BIT_MASK_DTIM_COUNT_VAP3 0xff +#define BIT_DTIM_COUNT_VAP3(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3) +#define BITS_DTIM_COUNT_VAP3 \ + (BIT_MASK_DTIM_COUNT_VAP3 << BIT_SHIFT_DTIM_COUNT_VAP3) +#define BIT_CLEAR_DTIM_COUNT_VAP3(x) ((x) & (~BITS_DTIM_COUNT_VAP3)) +#define BIT_GET_DTIM_COUNT_VAP3(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3) +#define BIT_SET_DTIM_COUNT_VAP3(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP3(x) | BIT_DTIM_COUNT_VAP3(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_DTIM_COUNTER_VAP4 (Offset 0x05AC) */ +#define BIT_SHIFT_DTIM_COUNT_VAP4 0 +#define BIT_MASK_DTIM_COUNT_VAP4 0xff +#define BIT_DTIM_COUNT_VAP4(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4) +#define BITS_DTIM_COUNT_VAP4 \ + (BIT_MASK_DTIM_COUNT_VAP4 << BIT_SHIFT_DTIM_COUNT_VAP4) +#define BIT_CLEAR_DTIM_COUNT_VAP4(x) ((x) & (~BITS_DTIM_COUNT_VAP4)) +#define BIT_GET_DTIM_COUNT_VAP4(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4) +#define BIT_SET_DTIM_COUNT_VAP4(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP4(x) | BIT_DTIM_COUNT_VAP4(v)) -/* 2 REG_RXFILTER_CATEGORY_1 (Offset 0x0682) */ +/* 2 REG_DTIM_COUNTER_VAP5 (Offset 0x05AD) */ +#define BIT_SHIFT_DTIM_COUNT_VAP5 0 +#define BIT_MASK_DTIM_COUNT_VAP5 0xff +#define BIT_DTIM_COUNT_VAP5(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5) +#define BITS_DTIM_COUNT_VAP5 \ + (BIT_MASK_DTIM_COUNT_VAP5 << BIT_SHIFT_DTIM_COUNT_VAP5) +#define BIT_CLEAR_DTIM_COUNT_VAP5(x) ((x) & (~BITS_DTIM_COUNT_VAP5)) +#define BIT_GET_DTIM_COUNT_VAP5(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5) +#define BIT_SET_DTIM_COUNT_VAP5(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP5(x) | BIT_DTIM_COUNT_VAP5(v)) -#define BIT_SHIFT_RXFILTER_CATEGORY_1 0 -#define BIT_MASK_RXFILTER_CATEGORY_1 0xff -#define BIT_RXFILTER_CATEGORY_1(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1) -#define BIT_GET_RXFILTER_CATEGORY_1(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1) +/* 2 REG_DTIM_COUNTER_VAP6 (Offset 0x05AE) */ +#define BIT_SHIFT_DTIM_COUNT_VAP6 0 +#define BIT_MASK_DTIM_COUNT_VAP6 0xff +#define BIT_DTIM_COUNT_VAP6(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6) +#define BITS_DTIM_COUNT_VAP6 \ + (BIT_MASK_DTIM_COUNT_VAP6 << BIT_SHIFT_DTIM_COUNT_VAP6) +#define BIT_CLEAR_DTIM_COUNT_VAP6(x) ((x) & (~BITS_DTIM_COUNT_VAP6)) +#define BIT_GET_DTIM_COUNT_VAP6(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6) +#define BIT_SET_DTIM_COUNT_VAP6(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP6(x) | BIT_DTIM_COUNT_VAP6(v)) -/* 2 REG_RXFILTER_ACTION_1 (Offset 0x0683) */ +/* 2 REG_DTIM_COUNTER_VAP7 (Offset 0x05AF) */ +#define BIT_SHIFT_DTIM_COUNT_VAP7 0 +#define BIT_MASK_DTIM_COUNT_VAP7 0xff +#define BIT_DTIM_COUNT_VAP7(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7) +#define BITS_DTIM_COUNT_VAP7 \ + (BIT_MASK_DTIM_COUNT_VAP7 << BIT_SHIFT_DTIM_COUNT_VAP7) +#define BIT_CLEAR_DTIM_COUNT_VAP7(x) ((x) & (~BITS_DTIM_COUNT_VAP7)) +#define BIT_GET_DTIM_COUNT_VAP7(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7) +#define BIT_SET_DTIM_COUNT_VAP7(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP7(x) | BIT_DTIM_COUNT_VAP7(v)) -#define BIT_SHIFT_RXFILTER_ACTION_1 0 -#define BIT_MASK_RXFILTER_ACTION_1 0xff -#define BIT_RXFILTER_ACTION_1(x) (((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1) -#define BIT_GET_RXFILTER_ACTION_1(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1) +/* 2 REG_DIS_ATIM (Offset 0x05B0) */ +#define BIT_MBIDCAM_VALID BIT(23) -/* 2 REG_RXFILTER_CATEGORY_2 (Offset 0x0684) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RXFILTER_CATEGORY_2 0 -#define BIT_MASK_RXFILTER_CATEGORY_2 0xff -#define BIT_RXFILTER_CATEGORY_2(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2) -#define BIT_GET_RXFILTER_CATEGORY_2(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2) +/* 2 REG_DIS_ATIM (Offset 0x05B0) */ +#define BIT_DIS_ATIM_VAP7 BIT(7) +#define BIT_DIS_ATIM_VAP6 BIT(6) +#define BIT_DIS_ATIM_VAP5 BIT(5) +#define BIT_DIS_ATIM_VAP4 BIT(4) +#define BIT_DIS_ATIM_VAP3 BIT(3) +#define BIT_DIS_ATIM_VAP2 BIT(2) +#define BIT_DIS_ATIM_VAP1 BIT(1) -/* 2 REG_RXFILTER_ACTION_2 (Offset 0x0685) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RXFILTER_ACTION_2 0 -#define BIT_MASK_RXFILTER_ACTION_2 0xff -#define BIT_RXFILTER_ACTION_2(x) (((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2) -#define BIT_GET_RXFILTER_ACTION_2(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2) +/* 2 REG_DIS_ATIM (Offset 0x05B0) */ +#define BIT_DIS_ATIM_ROOT BIT(0) -/* 2 REG_RXFILTER_CATEGORY_3 (Offset 0x0686) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_RXFILTER_CATEGORY_3 0 -#define BIT_MASK_RXFILTER_CATEGORY_3 0xff -#define BIT_RXFILTER_CATEGORY_3(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3) -#define BIT_GET_RXFILTER_CATEGORY_3(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3) +/* 2 REG_EARLY_128US (Offset 0x05B1) */ +#define BIT_SHIFT_EARLY_128US_2ST 3 +#define BIT_MASK_EARLY_128US_2ST 0x7 +#define BIT_EARLY_128US_2ST(x) \ + (((x) & BIT_MASK_EARLY_128US_2ST) << BIT_SHIFT_EARLY_128US_2ST) +#define BITS_EARLY_128US_2ST \ + (BIT_MASK_EARLY_128US_2ST << BIT_SHIFT_EARLY_128US_2ST) +#define BIT_CLEAR_EARLY_128US_2ST(x) ((x) & (~BITS_EARLY_128US_2ST)) +#define BIT_GET_EARLY_128US_2ST(x) \ + (((x) >> BIT_SHIFT_EARLY_128US_2ST) & BIT_MASK_EARLY_128US_2ST) +#define BIT_SET_EARLY_128US_2ST(x, v) \ + (BIT_CLEAR_EARLY_128US_2ST(x) | BIT_EARLY_128US_2ST(v)) -/* 2 REG_RXFILTER_ACTION_3 (Offset 0x0687) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXFILTER_ACTION_3 0 -#define BIT_MASK_RXFILTER_ACTION_3 0xff -#define BIT_RXFILTER_ACTION_3(x) (((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3) -#define BIT_GET_RXFILTER_ACTION_3(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3) +/* 2 REG_EARLY_128US (Offset 0x05B1) */ +#define BIT_SHIFT_TSFT_SEL_TIMER1 3 +#define BIT_MASK_TSFT_SEL_TIMER1 0x7 +#define BIT_TSFT_SEL_TIMER1(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1) +#define BITS_TSFT_SEL_TIMER1 \ + (BIT_MASK_TSFT_SEL_TIMER1 << BIT_SHIFT_TSFT_SEL_TIMER1) +#define BIT_CLEAR_TSFT_SEL_TIMER1(x) ((x) & (~BITS_TSFT_SEL_TIMER1)) +#define BIT_GET_TSFT_SEL_TIMER1(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1) +#define BIT_SET_TSFT_SEL_TIMER1(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER1(x) | BIT_TSFT_SEL_TIMER1(v)) -/* 2 REG_RXFLTMAP3 (Offset 0x0688) */ +#endif -#define BIT_MGTFLT15EN_FW BIT(15) -#define BIT_MGTFLT14EN_FW BIT(14) -#define BIT_MGTFLT13EN_FW BIT(13) -#define BIT_MGTFLT12EN_FW BIT(12) -#define BIT_MGTFLT11EN_FW BIT(11) -#define BIT_MGTFLT10EN_FW BIT(10) -#define BIT_MGTFLT9EN_FW BIT(9) -#define BIT_MGTFLT8EN_FW BIT(8) -#define BIT_MGTFLT7EN_FW BIT(7) -#define BIT_MGTFLT6EN_FW BIT(6) -#define BIT_MGTFLT5EN_FW BIT(5) -#define BIT_MGTFLT4EN_FW BIT(4) -#define BIT_MGTFLT3EN_FW BIT(3) -#define BIT_MGTFLT2EN_FW BIT(2) -#define BIT_MGTFLT1EN_FW BIT(1) -#define BIT_MGTFLT0EN_FW BIT(0) +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_RXFLTMAP4 (Offset 0x068A) */ +/* 2 REG_TBTT_HOLD_PREDICT_P1 (Offset 0x05B2) */ -#define BIT_CTRLFLT15EN_FW BIT(15) -#define BIT_CTRLFLT14EN_FW BIT(14) -#define BIT_CTRLFLT13EN_FW BIT(13) -#define BIT_CTRLFLT12EN_FW BIT(12) -#define BIT_CTRLFLT11EN_FW BIT(11) -#define BIT_CTRLFLT10EN_FW BIT(10) -#define BIT_CTRLFLT9EN_FW BIT(9) -#define BIT_CTRLFLT8EN_FW BIT(8) -#define BIT_CTRLFLT7EN_FW BIT(7) -#define BIT_CTRLFLT6EN_FW BIT(6) -#define BIT_CTRLFLT5EN_FW BIT(5) -#define BIT_CTRLFLT4EN_FW BIT(4) -#define BIT_CTRLFLT3EN_FW BIT(3) -#define BIT_CTRLFLT2EN_FW BIT(2) -#define BIT_CTRLFLT1EN_FW BIT(1) -#define BIT_CTRLFLT0EN_FW BIT(0) +#define BIT_DIS_BCN_3RD BIT(7) -/* 2 REG_RXFLTMAP5 (Offset 0x068C) */ +#endif -#define BIT_DATAFLT15EN_FW BIT(15) -#define BIT_DATAFLT14EN_FW BIT(14) -#define BIT_DATAFLT13EN_FW BIT(13) -#define BIT_DATAFLT12EN_FW BIT(12) -#define BIT_DATAFLT11EN_FW BIT(11) -#define BIT_DATAFLT10EN_FW BIT(10) -#define BIT_DATAFLT9EN_FW BIT(9) -#define BIT_DATAFLT8EN_FW BIT(8) -#define BIT_DATAFLT7EN_FW BIT(7) -#define BIT_DATAFLT6EN_FW BIT(6) -#define BIT_DATAFLT5EN_FW BIT(5) -#define BIT_DATAFLT4EN_FW BIT(4) -#define BIT_DATAFLT3EN_FW BIT(3) -#define BIT_DATAFLT2EN_FW BIT(2) -#define BIT_DATAFLT1EN_FW BIT(1) -#define BIT_DATAFLT0EN_FW BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RXFLTMAP6 (Offset 0x068E) */ +/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ -#define BIT_ACTIONFLT15EN_FW BIT(15) -#define BIT_ACTIONFLT14EN_FW BIT(14) -#define BIT_ACTIONFLT13EN_FW BIT(13) -#define BIT_ACTIONFLT12EN_FW BIT(12) -#define BIT_ACTIONFLT11EN_FW BIT(11) -#define BIT_ACTIONFLT10EN_FW BIT(10) -#define BIT_ACTIONFLT9EN_FW BIT(9) -#define BIT_ACTIONFLT8EN_FW BIT(8) -#define BIT_ACTIONFLT7EN_FW BIT(7) -#define BIT_ACTIONFLT6EN_FW BIT(6) -#define BIT_ACTIONFLT5EN_FW BIT(5) -#define BIT_ACTIONFLT4EN_FW BIT(4) -#define BIT_ACTIONFLT3EN_FW BIT(3) -#define BIT_ACTIONFLT2EN_FW BIT(2) -#define BIT_ACTIONFLT1EN_FW BIT(1) -#define BIT_ACTIONFLT0EN_FW BIT(0) +#define BIT_P2P1_CTW_ALLSTASLEEP BIT(7) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TBTT_HOLD_PREDICT_P1 (Offset 0x05B2) */ +#define BIT_DIS_BCN_2ST BIT(6) -/* 2 REG_WOW_CTRL (Offset 0x0690) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6 -#define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3 -#define BIT_PSF_BSSIDSEL_B2B1(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1) -#define BIT_GET_PSF_BSSIDSEL_B2B1(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1) +/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ +#define BIT_P2P1_OFF_DISTX_EN BIT(6) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TBTT_HOLD_PREDICT_P1 (Offset 0x05B2) */ +#define BIT_DIS_BCN_1ST BIT(5) -/* 2 REG_WOW_CTRL (Offset 0x0690) */ +#endif -#define BIT_WOWHCI BIT(5) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ +#define BIT_P2P1_PWR_MGT_EN BIT(5) +#define BIT_P2P1_NOA1_EN BIT(2) +#define BIT_P2P1_NOA0_EN BIT(1) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_WOW_CTRL (Offset 0x0690) */ +/* 2 REG_TBTT_HOLD_PREDICT_P1 (Offset 0x05B2) */ -#define BIT_PSF_BSSIDSEL BIT(4) +#define BIT_SHIFT_TBTT_HOLD_PREDICT_P1 0 +#define BIT_MASK_TBTT_HOLD_PREDICT_P1 0x1f +#define BIT_TBTT_HOLD_PREDICT_P1(x) \ + (((x) & BIT_MASK_TBTT_HOLD_PREDICT_P1) \ + << BIT_SHIFT_TBTT_HOLD_PREDICT_P1) +#define BITS_TBTT_HOLD_PREDICT_P1 \ + (BIT_MASK_TBTT_HOLD_PREDICT_P1 << BIT_SHIFT_TBTT_HOLD_PREDICT_P1) +#define BIT_CLEAR_TBTT_HOLD_PREDICT_P1(x) ((x) & (~BITS_TBTT_HOLD_PREDICT_P1)) +#define BIT_GET_TBTT_HOLD_PREDICT_P1(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_PREDICT_P1) & \ + BIT_MASK_TBTT_HOLD_PREDICT_P1) +#define BIT_SET_TBTT_HOLD_PREDICT_P1(x, v) \ + (BIT_CLEAR_TBTT_HOLD_PREDICT_P1(x) | BIT_TBTT_HOLD_PREDICT_P1(v)) -#endif +/* 2 REG_MULTI_BCN_CS (Offset 0x05B3) */ +#define BIT_EN_FREECNT_V2 BIT(13) +#define BIT_RESET_FREECNT_P BIT(12) +#define BIT_TSFTR3_SYNC_EN BIT(7) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_WOW_CTRL (Offset 0x0690) */ +/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ -#define BIT_PSF_BSSIDSEL_B0 BIT(4) +#define BIT_P2P2_CTW_ALLSTASLEEP BIT(7) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MULTI_BCN_CS (Offset 0x05B3) */ +#define BIT_SHIFT_P1_TSFT_SHIFT 6 +#define BIT_MASK_P1_TSFT_SHIFT 0x3f +#define BIT_P1_TSFT_SHIFT(x) \ + (((x) & BIT_MASK_P1_TSFT_SHIFT) << BIT_SHIFT_P1_TSFT_SHIFT) +#define BITS_P1_TSFT_SHIFT (BIT_MASK_P1_TSFT_SHIFT << BIT_SHIFT_P1_TSFT_SHIFT) +#define BIT_CLEAR_P1_TSFT_SHIFT(x) ((x) & (~BITS_P1_TSFT_SHIFT)) +#define BIT_GET_P1_TSFT_SHIFT(x) \ + (((x) >> BIT_SHIFT_P1_TSFT_SHIFT) & BIT_MASK_P1_TSFT_SHIFT) +#define BIT_SET_P1_TSFT_SHIFT(x, v) \ + (BIT_CLEAR_P1_TSFT_SHIFT(x) | BIT_P1_TSFT_SHIFT(v)) -/* 2 REG_WOW_CTRL (Offset 0x0690) */ +#endif -#define BIT_UWF BIT(3) -#define BIT_MAGIC BIT(2) -#define BIT_WOWEN BIT(1) -#define BIT_FORCE_WAKEUP BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ +#define BIT_P2P2_OFF_DISTX_EN BIT(6) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_NAN_RX_TSF_FILTER (Offset 0x0691) */ +/* 2 REG_MULTI_BCN_CS (Offset 0x05B3) */ -#define BIT_CHK_TSF_TA BIT(2) -#define BIT_CHK_TSF_CBSSID BIT(1) -#define BIT_CHK_TSF_EN BIT(0) +#define BIT_TSFTR2_SYNC_EN BIT(5) -/* 2 REG_PS_RX_INFO (Offset 0x0692) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PORTSEL__PS_RX_INFO 5 -#define BIT_MASK_PORTSEL__PS_RX_INFO 0x7 -#define BIT_PORTSEL__PS_RX_INFO(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO) -#define BIT_GET_PORTSEL__PS_RX_INFO(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO) +/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ +#define BIT_P2P2_PWR_MGT_EN BIT(5) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MULTI_BCN_CS (Offset 0x05B3) */ +#define BIT_TSFTR2_RST BIT(4) -/* 2 REG_PS_RX_INFO (Offset 0x0692) */ +#endif -#define BIT_RXCTRLIN0 BIT(4) -#define BIT_RXMGTIN0 BIT(3) -#define BIT_RXDATAIN2 BIT(2) -#define BIT_RXDATAIN1 BIT(1) -#define BIT_RXDATAIN0 BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_WMMPS_UAPSD_TID (Offset 0x0693) */ +/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ -#define BIT_WMMPS_UAPSD_TID7 BIT(7) -#define BIT_WMMPS_UAPSD_TID6 BIT(6) -#define BIT_WMMPS_UAPSD_TID5 BIT(5) -#define BIT_WMMPS_UAPSD_TID4 BIT(4) -#define BIT_WMMPS_UAPSD_TID3 BIT(3) -#define BIT_WMMPS_UAPSD_TID2 BIT(2) -#define BIT_WMMPS_UAPSD_TID1 BIT(1) -#define BIT_WMMPS_UAPSD_TID0 BIT(0) +#define BIT_P2P2_NOA1_EN BIT(2) +#define BIT_P2P2_NOA0_EN BIT(1) -/* 2 REG_LPNAV_CTRL (Offset 0x0694) */ +#endif -#define BIT_LPNAV_EN BIT(31) +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_LPNAV_EARLY 16 -#define BIT_MASK_LPNAV_EARLY 0x7fff -#define BIT_LPNAV_EARLY(x) (((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY) -#define BIT_GET_LPNAV_EARLY(x) (((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY) +/* 2 REG_MULTI_BCN_CS (Offset 0x05B3) */ +#define BIT_SHIFT_MULTI_BCN_CS 0 +#define BIT_MASK_MULTI_BCN_CS 0xf +#define BIT_MULTI_BCN_CS(x) \ + (((x) & BIT_MASK_MULTI_BCN_CS) << BIT_SHIFT_MULTI_BCN_CS) +#define BITS_MULTI_BCN_CS (BIT_MASK_MULTI_BCN_CS << BIT_SHIFT_MULTI_BCN_CS) +#define BIT_CLEAR_MULTI_BCN_CS(x) ((x) & (~BITS_MULTI_BCN_CS)) +#define BIT_GET_MULTI_BCN_CS(x) \ + (((x) >> BIT_SHIFT_MULTI_BCN_CS) & BIT_MASK_MULTI_BCN_CS) +#define BIT_SET_MULTI_BCN_CS(x, v) \ + (BIT_CLEAR_MULTI_BCN_CS(x) | BIT_MULTI_BCN_CS(v)) -#define BIT_SHIFT_LPNAV_TH 0 -#define BIT_MASK_LPNAV_TH 0xffff -#define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH) -#define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH) +#define BIT_SHIFT_P0_TSFT_SHIFT 0 +#define BIT_MASK_P0_TSFT_SHIFT 0x3f +#define BIT_P0_TSFT_SHIFT(x) \ + (((x) & BIT_MASK_P0_TSFT_SHIFT) << BIT_SHIFT_P0_TSFT_SHIFT) +#define BITS_P0_TSFT_SHIFT (BIT_MASK_P0_TSFT_SHIFT << BIT_SHIFT_P0_TSFT_SHIFT) +#define BIT_CLEAR_P0_TSFT_SHIFT(x) ((x) & (~BITS_P0_TSFT_SHIFT)) +#define BIT_GET_P0_TSFT_SHIFT(x) \ + (((x) >> BIT_SHIFT_P0_TSFT_SHIFT) & BIT_MASK_P0_TSFT_SHIFT) +#define BIT_SET_P0_TSFT_SHIFT(x, v) \ + (BIT_CLEAR_P0_TSFT_SHIFT(x) | BIT_P0_TSFT_SHIFT(v)) +#define BIT_DIS_NDPA_NAV_CHK_V1 BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TIMER0_SRC_SEL (Offset 0x05B4) */ +#define BIT_SHIFT_SYNC_CLI_SEL 4 +#define BIT_MASK_SYNC_CLI_SEL 0x7 +#define BIT_SYNC_CLI_SEL(x) \ + (((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL) +#define BITS_SYNC_CLI_SEL (BIT_MASK_SYNC_CLI_SEL << BIT_SHIFT_SYNC_CLI_SEL) +#define BIT_CLEAR_SYNC_CLI_SEL(x) ((x) & (~BITS_SYNC_CLI_SEL)) +#define BIT_GET_SYNC_CLI_SEL(x) \ + (((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL) +#define BIT_SET_SYNC_CLI_SEL(x, v) \ + (BIT_CLEAR_SYNC_CLI_SEL(x) | BIT_SYNC_CLI_SEL(v)) + +#define BIT_SHIFT_TSFT_SEL_TIMER0 0 +#define BIT_MASK_TSFT_SEL_TIMER0 0x7 +#define BIT_TSFT_SEL_TIMER0(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0) +#define BITS_TSFT_SEL_TIMER0 \ + (BIT_MASK_TSFT_SEL_TIMER0 << BIT_SHIFT_TSFT_SEL_TIMER0) +#define BIT_CLEAR_TSFT_SEL_TIMER0(x) ((x) & (~BITS_TSFT_SEL_TIMER0)) +#define BIT_GET_TSFT_SEL_TIMER0(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0) +#define BIT_SET_TSFT_SEL_TIMER0(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER0(x) | BIT_TSFT_SEL_TIMER0(v)) -/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +/* 2 REG_NOA_UNIT_SEL (Offset 0x05B5) */ -#define BIT_WKFCAM_POLLING_V1 BIT(31) -#define BIT_WKFCAM_CLR_V1 BIT(30) +#define BIT_SHIFT_NOA_UNIT2_SEL 8 +#define BIT_MASK_NOA_UNIT2_SEL 0x7 +#define BIT_NOA_UNIT2_SEL(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL) +#define BITS_NOA_UNIT2_SEL (BIT_MASK_NOA_UNIT2_SEL << BIT_SHIFT_NOA_UNIT2_SEL) +#define BIT_CLEAR_NOA_UNIT2_SEL(x) ((x) & (~BITS_NOA_UNIT2_SEL)) +#define BIT_GET_NOA_UNIT2_SEL(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL) +#define BIT_SET_NOA_UNIT2_SEL(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL(x) | BIT_NOA_UNIT2_SEL(v)) + +#define BIT_SHIFT_NOA_UNIT1_SEL 4 +#define BIT_MASK_NOA_UNIT1_SEL 0x7 +#define BIT_NOA_UNIT1_SEL(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL) +#define BITS_NOA_UNIT1_SEL (BIT_MASK_NOA_UNIT1_SEL << BIT_SHIFT_NOA_UNIT1_SEL) +#define BIT_CLEAR_NOA_UNIT1_SEL(x) ((x) & (~BITS_NOA_UNIT1_SEL)) +#define BIT_GET_NOA_UNIT1_SEL(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL) +#define BIT_SET_NOA_UNIT1_SEL(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL(x) | BIT_NOA_UNIT1_SEL(v)) + +#define BIT_SHIFT_NOA_UNIT0_SEL 0 +#define BIT_MASK_NOA_UNIT0_SEL 0x7 +#define BIT_NOA_UNIT0_SEL(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL) +#define BITS_NOA_UNIT0_SEL (BIT_MASK_NOA_UNIT0_SEL << BIT_SHIFT_NOA_UNIT0_SEL) +#define BIT_CLEAR_NOA_UNIT0_SEL(x) ((x) & (~BITS_NOA_UNIT0_SEL)) +#define BIT_GET_NOA_UNIT0_SEL(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL) +#define BIT_SET_NOA_UNIT0_SEL(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL(x) | BIT_NOA_UNIT0_SEL(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_P2POFF_DIS_TXTIME (Offset 0x05B7) */ + +#define BIT_SHIFT_P2POFF_DIS_TXTIME 0 +#define BIT_MASK_P2POFF_DIS_TXTIME 0xff +#define BIT_P2POFF_DIS_TXTIME(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME) +#define BITS_P2POFF_DIS_TXTIME \ + (BIT_MASK_P2POFF_DIS_TXTIME << BIT_SHIFT_P2POFF_DIS_TXTIME) +#define BIT_CLEAR_P2POFF_DIS_TXTIME(x) ((x) & (~BITS_P2POFF_DIS_TXTIME)) +#define BIT_GET_P2POFF_DIS_TXTIME(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME) +#define BIT_SET_P2POFF_DIS_TXTIME(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME(x) | BIT_P2POFF_DIS_TXTIME(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MBSSID_BCN_SPACE2 (Offset 0x05B8) */ +#define BIT_SHIFT_BCN_SPACE_CLINT2 16 +#define BIT_MASK_BCN_SPACE_CLINT2 0xfff +#define BIT_BCN_SPACE_CLINT2(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2) +#define BITS_BCN_SPACE_CLINT2 \ + (BIT_MASK_BCN_SPACE_CLINT2 << BIT_SHIFT_BCN_SPACE_CLINT2) +#define BIT_CLEAR_BCN_SPACE_CLINT2(x) ((x) & (~BITS_BCN_SPACE_CLINT2)) +#define BIT_GET_BCN_SPACE_CLINT2(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2) +#define BIT_SET_BCN_SPACE_CLINT2(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT2(x) | BIT_BCN_SPACE_CLINT2(v)) + +#define BIT_SHIFT_BCN_SPACE_CLINT1 0 +#define BIT_MASK_BCN_SPACE_CLINT1 0xfff +#define BIT_BCN_SPACE_CLINT1(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1) +#define BITS_BCN_SPACE_CLINT1 \ + (BIT_MASK_BCN_SPACE_CLINT1 << BIT_SHIFT_BCN_SPACE_CLINT1) +#define BIT_CLEAR_BCN_SPACE_CLINT1(x) ((x) & (~BITS_BCN_SPACE_CLINT1)) +#define BIT_GET_BCN_SPACE_CLINT1(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1) +#define BIT_SET_BCN_SPACE_CLINT1(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT1(x) | BIT_BCN_SPACE_CLINT1(v)) -/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ -#define BIT_WKFCAM_WE BIT(16) +#define BIT_SHIFT_SUB_BCN_SPACE 16 +#define BIT_MASK_SUB_BCN_SPACE 0xff +#define BIT_SUB_BCN_SPACE(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE) +#define BITS_SUB_BCN_SPACE (BIT_MASK_SUB_BCN_SPACE << BIT_SHIFT_SUB_BCN_SPACE) +#define BIT_CLEAR_SUB_BCN_SPACE(x) ((x) & (~BITS_SUB_BCN_SPACE)) +#define BIT_GET_SUB_BCN_SPACE(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE) +#define BIT_SET_SUB_BCN_SPACE(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE(x) | BIT_SUB_BCN_SPACE(v)) + +#define BIT_SHIFT_BCN_SPACE_CLINT3 0 +#define BIT_MASK_BCN_SPACE_CLINT3 0xfff +#define BIT_BCN_SPACE_CLINT3(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3) +#define BITS_BCN_SPACE_CLINT3 \ + (BIT_MASK_BCN_SPACE_CLINT3 << BIT_SHIFT_BCN_SPACE_CLINT3) +#define BIT_CLEAR_BCN_SPACE_CLINT3(x) ((x) & (~BITS_BCN_SPACE_CLINT3)) +#define BIT_GET_BCN_SPACE_CLINT3(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3) +#define BIT_SET_BCN_SPACE_CLINT3(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT3(x) | BIT_BCN_SPACE_CLINT3(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_ACMHWCTRL (Offset 0x05C0) */ +#define BIT_BEQ_ACM_STATUS BIT(7) +#define BIT_VIQ_ACM_STATUS BIT(6) +#define BIT_VOQ_ACM_STATUS BIT(5) +#define BIT_BEQ_ACM_EN BIT(3) +#define BIT_VIQ_ACM_EN BIT(2) +#define BIT_VOQ_ACM_EN BIT(1) +#define BIT_ACMHWEN BIT(0) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ACMRSTCTRL (Offset 0x05C1) */ +#define BIT_BE_ACM_RESET_USED_TIME BIT(2) +#define BIT_VI_ACM_RESET_USED_TIME BIT(1) +#define BIT_VO_ACM_RESET_USED_TIME BIT(0) -/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +/* 2 REG_ACMAVG (Offset 0x05C2) */ +#define BIT_SHIFT_AVGPERIOD 0 +#define BIT_MASK_AVGPERIOD 0xffff +#define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD) +#define BITS_AVGPERIOD (BIT_MASK_AVGPERIOD << BIT_SHIFT_AVGPERIOD) +#define BIT_CLEAR_AVGPERIOD(x) ((x) & (~BITS_AVGPERIOD)) +#define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD) +#define BIT_SET_AVGPERIOD(x, v) (BIT_CLEAR_AVGPERIOD(x) | BIT_AVGPERIOD(v)) -#define BIT_SHIFT_WKFCAM_ADDR_V2 8 -#define BIT_MASK_WKFCAM_ADDR_V2 0xff -#define BIT_WKFCAM_ADDR_V2(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) -#define BIT_GET_WKFCAM_ADDR_V2(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2) +/* 2 REG_VO_ADMTIME (Offset 0x05C4) */ +#define BIT_SHIFT_VO_ADMITTED_TIME 0 +#define BIT_MASK_VO_ADMITTED_TIME 0xffff +#define BIT_VO_ADMITTED_TIME(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME) +#define BITS_VO_ADMITTED_TIME \ + (BIT_MASK_VO_ADMITTED_TIME << BIT_SHIFT_VO_ADMITTED_TIME) +#define BIT_CLEAR_VO_ADMITTED_TIME(x) ((x) & (~BITS_VO_ADMITTED_TIME)) +#define BIT_GET_VO_ADMITTED_TIME(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME) +#define BIT_SET_VO_ADMITTED_TIME(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME(x) | BIT_VO_ADMITTED_TIME(v)) -#define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0 -#define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff -#define BIT_WKFCAM_CAM_NUM_V1(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1) -#define BIT_GET_WKFCAM_CAM_NUM_V1(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1) +/* 2 REG_VI_ADMTIME (Offset 0x05C6) */ +#define BIT_SHIFT_VI_ADMITTED_TIME 0 +#define BIT_MASK_VI_ADMITTED_TIME 0xffff +#define BIT_VI_ADMITTED_TIME(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME) +#define BITS_VI_ADMITTED_TIME \ + (BIT_MASK_VI_ADMITTED_TIME << BIT_SHIFT_VI_ADMITTED_TIME) +#define BIT_CLEAR_VI_ADMITTED_TIME(x) ((x) & (~BITS_VI_ADMITTED_TIME)) +#define BIT_GET_VI_ADMITTED_TIME(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME) +#define BIT_SET_VI_ADMITTED_TIME(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME(x) | BIT_VI_ADMITTED_TIME(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_BE_ADMTIME (Offset 0x05C8) */ +#define BIT_PRETX_ERRHDL_EN BIT(15) -/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WKFCAM_ADDR 0 -#define BIT_MASK_WKFCAM_ADDR 0x7f -#define BIT_WKFCAM_ADDR(x) (((x) & BIT_MASK_WKFCAM_ADDR) << BIT_SHIFT_WKFCAM_ADDR) -#define BIT_GET_WKFCAM_ADDR(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR) & BIT_MASK_WKFCAM_ADDR) +/* 2 REG_BE_ADMTIME (Offset 0x05C8) */ +#define BIT_SHIFT_BE_ADMITTED_TIME 0 +#define BIT_MASK_BE_ADMITTED_TIME 0xffff +#define BIT_BE_ADMITTED_TIME(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME) +#define BITS_BE_ADMITTED_TIME \ + (BIT_MASK_BE_ADMITTED_TIME << BIT_SHIFT_BE_ADMITTED_TIME) +#define BIT_CLEAR_BE_ADMITTED_TIME(x) ((x) & (~BITS_BE_ADMITTED_TIME)) +#define BIT_GET_BE_ADMITTED_TIME(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME) +#define BIT_SET_BE_ADMITTED_TIME(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME(x) | BIT_BE_ADMITTED_TIME(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BE_ADMTIME (Offset 0x05C8) */ +#define BIT_SHIFT_MHDR_NAV_OFFSET 0 +#define BIT_MASK_MHDR_NAV_OFFSET 0xff +#define BIT_MHDR_NAV_OFFSET(x) \ + (((x) & BIT_MASK_MHDR_NAV_OFFSET) << BIT_SHIFT_MHDR_NAV_OFFSET) +#define BITS_MHDR_NAV_OFFSET \ + (BIT_MASK_MHDR_NAV_OFFSET << BIT_SHIFT_MHDR_NAV_OFFSET) +#define BIT_CLEAR_MHDR_NAV_OFFSET(x) ((x) & (~BITS_MHDR_NAV_OFFSET)) +#define BIT_GET_MHDR_NAV_OFFSET(x) \ + (((x) >> BIT_SHIFT_MHDR_NAV_OFFSET) & BIT_MASK_MHDR_NAV_OFFSET) +#define BIT_SET_MHDR_NAV_OFFSET(x, v) \ + (BIT_CLEAR_MHDR_NAV_OFFSET(x) | BIT_MHDR_NAV_OFFSET(v)) -/* 2 REG_WKFMCAM_RWD (Offset 0x069C) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WKFMCAM_RWD 0 -#define BIT_MASK_WKFMCAM_RWD 0xffffffffL -#define BIT_WKFMCAM_RWD(x) (((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD) -#define BIT_GET_WKFMCAM_RWD(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD) +/* 2 REG_MAC_HEADER_NAV_OFFSET (Offset 0x05CA) */ +#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET 0 +#define BIT_MASK_MAC_HEADER_NAV_OFFSET 0xff +#define BIT_MAC_HEADER_NAV_OFFSET(x) \ + (((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET) \ + << BIT_SHIFT_MAC_HEADER_NAV_OFFSET) +#define BITS_MAC_HEADER_NAV_OFFSET \ + (BIT_MASK_MAC_HEADER_NAV_OFFSET << BIT_SHIFT_MAC_HEADER_NAV_OFFSET) +#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) ((x) & (~BITS_MAC_HEADER_NAV_OFFSET)) +#define BIT_GET_MAC_HEADER_NAV_OFFSET(x) \ + (((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET) & \ + BIT_MASK_MAC_HEADER_NAV_OFFSET) +#define BIT_SET_MAC_HEADER_NAV_OFFSET(x, v) \ + (BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) | BIT_MAC_HEADER_NAV_OFFSET(v)) -/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ +#endif -#define BIT_MGTFLT15EN BIT(15) -#define BIT_MGTFLT14EN BIT(14) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_DIS_NDPA_NAV_CHECK (Offset 0x05CB) */ +#define BIT_CHG_POWER_BCN_AREA_V1 BIT(1) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ +/* 2 REG_DIS_NDPA_NAV_CHECK (Offset 0x05CB) */ -#define BIT_MGTFLT13EN BIT(13) -#define BIT_MGTFLT12EN BIT(12) -#define BIT_MGTFLT11EN BIT(11) -#define BIT_MGTFLT10EN BIT(10) -#define BIT_MGTFLT9EN BIT(9) -#define BIT_MGTFLT8EN BIT(8) +#define BIT_DIS_NDPA_NAV_CHECK BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_EDCA_RANDOM_GEN (Offset 0x05CC) */ -/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ +#define BIT_SHIFT_RANDOM_GEN 0 +#define BIT_MASK_RANDOM_GEN 0xffffff +#define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN) +#define BITS_RANDOM_GEN (BIT_MASK_RANDOM_GEN << BIT_SHIFT_RANDOM_GEN) +#define BIT_CLEAR_RANDOM_GEN(x) ((x) & (~BITS_RANDOM_GEN)) +#define BIT_GET_RANDOM_GEN(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN) +#define BIT_SET_RANDOM_GEN(x, v) (BIT_CLEAR_RANDOM_GEN(x) | BIT_RANDOM_GEN(v)) -#define BIT_MGTFLT7EN BIT(7) -#define BIT_MGTFLT6EN BIT(6) +#define BIT_SHIFT_TXCMD_SEG_SEL 0 +#define BIT_MASK_TXCMD_SEG_SEL 0xf +#define BIT_TXCMD_SEG_SEL(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL) +#define BITS_TXCMD_SEG_SEL (BIT_MASK_TXCMD_SEG_SEL << BIT_SHIFT_TXCMD_SEG_SEL) +#define BIT_CLEAR_TXCMD_SEG_SEL(x) ((x) & (~BITS_TXCMD_SEG_SEL)) +#define BIT_GET_TXCMD_SEG_SEL(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL) +#define BIT_SET_TXCMD_SEG_SEL(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL(x) | BIT_TXCMD_SEG_SEL(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ +#define BIT_SHIFT_EVTQ_EARLY 5 +#define BIT_MASK_EVTQ_EARLY 0x7 +#define BIT_EVTQ_EARLY(x) (((x) & BIT_MASK_EVTQ_EARLY) << BIT_SHIFT_EVTQ_EARLY) +#define BITS_EVTQ_EARLY (BIT_MASK_EVTQ_EARLY << BIT_SHIFT_EVTQ_EARLY) +#define BIT_CLEAR_EVTQ_EARLY(x) ((x) & (~BITS_EVTQ_EARLY)) +#define BIT_GET_EVTQ_EARLY(x) \ + (((x) >> BIT_SHIFT_EVTQ_EARLY) & BIT_MASK_EVTQ_EARLY) +#define BIT_SET_EVTQ_EARLY(x, v) (BIT_CLEAR_EVTQ_EARLY(x) | BIT_EVTQ_EARLY(v)) -/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ +#endif -#define BIT_MGTFLT5EN BIT(5) -#define BIT_MGTFLT4EN BIT(4) -#define BIT_MGTFLT3EN BIT(3) -#define BIT_MGTFLT2EN BIT(2) -#define BIT_MGTFLT1EN BIT(1) -#define BIT_MGTFLT0EN BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_RXFLTMAP1 (Offset 0x06A2) */ +/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ -#define BIT_CTRLFLT15EN BIT(15) -#define BIT_CTRLFLT14EN BIT(14) -#define BIT_CTRLFLT13EN BIT(13) -#define BIT_CTRLFLT12EN BIT(12) -#define BIT_CTRLFLT11EN BIT(11) -#define BIT_CTRLFLT10EN BIT(10) -#define BIT_CTRLFLT9EN BIT(9) -#define BIT_CTRLFLT8EN BIT(8) -#define BIT_CTRLFLT7EN BIT(7) -#define BIT_CTRLFLT6EN BIT(6) +#define BIT_NOA_SEL BIT(4) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_RXFLTMAP1 (Offset 0x06A2) */ +/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ -#define BIT_CTRLFLT5EN BIT(5) -#define BIT_CTRLFLT4EN BIT(4) -#define BIT_CTRLFLT3EN BIT(3) -#define BIT_CTRLFLT2EN BIT(2) -#define BIT_CTRLFLT1EN BIT(1) -#define BIT_CTRLFLT0EN BIT(0) +#define BIT_SHIFT_NOA_SEL_V2 4 +#define BIT_MASK_NOA_SEL_V2 0x7 +#define BIT_NOA_SEL_V2(x) (((x) & BIT_MASK_NOA_SEL_V2) << BIT_SHIFT_NOA_SEL_V2) +#define BITS_NOA_SEL_V2 (BIT_MASK_NOA_SEL_V2 << BIT_SHIFT_NOA_SEL_V2) +#define BIT_CLEAR_NOA_SEL_V2(x) ((x) & (~BITS_NOA_SEL_V2)) +#define BIT_GET_NOA_SEL_V2(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V2) & BIT_MASK_NOA_SEL_V2) +#define BIT_SET_NOA_SEL_V2(x, v) (BIT_CLEAR_NOA_SEL_V2(x) | BIT_NOA_SEL_V2(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_32K_CLK_SEL (Offset 0x05D0) */ +#define BIT_R_BCNERR_CNT_EN BIT(20) -/* 2 REG_RXFLTMAP (Offset 0x06A4) */ - -#define BIT_DATAFLT15EN BIT(15) -#define BIT_DATAFLT14EN BIT(14) -#define BIT_DATAFLT13EN BIT(13) -#define BIT_DATAFLT12EN BIT(12) -#define BIT_DATAFLT11EN BIT(11) -#define BIT_DATAFLT10EN BIT(10) -#define BIT_DATAFLT9EN BIT(9) -#define BIT_DATAFLT8EN BIT(8) -#define BIT_DATAFLT7EN BIT(7) -#define BIT_DATAFLT6EN BIT(6) -#define BIT_DATAFLT5EN BIT(5) -#define BIT_DATAFLT4EN BIT(4) -#define BIT_DATAFLT3EN BIT(3) -#define BIT_DATAFLT2EN BIT(2) -#define BIT_DATAFLT1EN BIT(1) -#define BIT_DATAFLT0EN BIT(0) - -/* 2 REG_BCN_PSR_RPT (Offset 0x06A8) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_DTIM_CNT 24 -#define BIT_MASK_DTIM_CNT 0xff -#define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT) -#define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT) +/* 2 REG_DRVERLYINT2 (Offset 0x05D0) */ +#define BIT_SHIFT_TSF_DIFF_P1P2 16 +#define BIT_MASK_TSF_DIFF_P1P2 0xffff +#define BIT_TSF_DIFF_P1P2(x) \ + (((x) & BIT_MASK_TSF_DIFF_P1P2) << BIT_SHIFT_TSF_DIFF_P1P2) +#define BITS_TSF_DIFF_P1P2 (BIT_MASK_TSF_DIFF_P1P2 << BIT_SHIFT_TSF_DIFF_P1P2) +#define BIT_CLEAR_TSF_DIFF_P1P2(x) ((x) & (~BITS_TSF_DIFF_P1P2)) +#define BIT_GET_TSF_DIFF_P1P2(x) \ + (((x) >> BIT_SHIFT_TSF_DIFF_P1P2) & BIT_MASK_TSF_DIFF_P1P2) +#define BIT_SET_TSF_DIFF_P1P2(x, v) \ + (BIT_CLEAR_TSF_DIFF_P1P2(x) | BIT_TSF_DIFF_P1P2(v)) -#define BIT_SHIFT_DTIM_PERIOD 16 -#define BIT_MASK_DTIM_PERIOD 0xff -#define BIT_DTIM_PERIOD(x) (((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD) -#define BIT_GET_DTIM_PERIOD(x) (((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD) +#endif -#define BIT_DTIM BIT(15) -#define BIT_TIM BIT(14) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PS_AID_0 0 -#define BIT_MASK_PS_AID_0 0x7ff -#define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0) -#define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0) +/* 2 REG_32K_CLK_SEL (Offset 0x05D0) */ +#define BIT_SHIFT_R_BCNERR_PORT_SEL 16 +#define BIT_MASK_R_BCNERR_PORT_SEL 0x7 +#define BIT_R_BCNERR_PORT_SEL(x) \ + (((x) & BIT_MASK_R_BCNERR_PORT_SEL) << BIT_SHIFT_R_BCNERR_PORT_SEL) +#define BITS_R_BCNERR_PORT_SEL \ + (BIT_MASK_R_BCNERR_PORT_SEL << BIT_SHIFT_R_BCNERR_PORT_SEL) +#define BIT_CLEAR_R_BCNERR_PORT_SEL(x) ((x) & (~BITS_R_BCNERR_PORT_SEL)) +#define BIT_GET_R_BCNERR_PORT_SEL(x) \ + (((x) >> BIT_SHIFT_R_BCNERR_PORT_SEL) & BIT_MASK_R_BCNERR_PORT_SEL) +#define BIT_SET_R_BCNERR_PORT_SEL(x, v) \ + (BIT_CLEAR_R_BCNERR_PORT_SEL(x) | BIT_R_BCNERR_PORT_SEL(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - +/* 2 REG_DRVERLYINT2 (Offset 0x05D0) */ -/* 2 REG_FLC_RPC (Offset 0x06AC) */ +#define BIT_SHIFT_TXPAUSE1 8 +#define BIT_MASK_TXPAUSE1 0xff +#define BIT_TXPAUSE1(x) (((x) & BIT_MASK_TXPAUSE1) << BIT_SHIFT_TXPAUSE1) +#define BITS_TXPAUSE1 (BIT_MASK_TXPAUSE1 << BIT_SHIFT_TXPAUSE1) +#define BIT_CLEAR_TXPAUSE1(x) ((x) & (~BITS_TXPAUSE1)) +#define BIT_GET_TXPAUSE1(x) (((x) >> BIT_SHIFT_TXPAUSE1) & BIT_MASK_TXPAUSE1) +#define BIT_SET_TXPAUSE1(x, v) (BIT_CLEAR_TXPAUSE1(x) | BIT_TXPAUSE1(v)) +#endif -#define BIT_SHIFT_FLC_RPC 0 -#define BIT_MASK_FLC_RPC 0xff -#define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC) -#define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_32K_CLK_SEL (Offset 0x05D0) */ -/* 2 REG_FLC_RPCT (Offset 0x06AD) */ +#define BIT_SHIFT_R_TXPAUSE1 8 +#define BIT_MASK_R_TXPAUSE1 0xff +#define BIT_R_TXPAUSE1(x) (((x) & BIT_MASK_R_TXPAUSE1) << BIT_SHIFT_R_TXPAUSE1) +#define BITS_R_TXPAUSE1 (BIT_MASK_R_TXPAUSE1 << BIT_SHIFT_R_TXPAUSE1) +#define BIT_CLEAR_R_TXPAUSE1(x) ((x) & (~BITS_R_TXPAUSE1)) +#define BIT_GET_R_TXPAUSE1(x) \ + (((x) >> BIT_SHIFT_R_TXPAUSE1) & BIT_MASK_R_TXPAUSE1) +#define BIT_SET_R_TXPAUSE1(x, v) (BIT_CLEAR_R_TXPAUSE1(x) | BIT_R_TXPAUSE1(v)) +#define BIT_SLEEP_32K_EN_V1 BIT(2) -#define BIT_SHIFT_FLC_RPCT 0 -#define BIT_MASK_FLC_RPCT 0xff -#define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT) -#define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FLC_PTS (Offset 0x06AE) */ +/* 2 REG_DRVERLYINT2 (Offset 0x05D0) */ -#define BIT_CMF BIT(2) -#define BIT_CCF BIT(1) -#define BIT_CDF BIT(0) +#define BIT_SHIFT_DRVERLYITV2 0 +#define BIT_MASK_DRVERLYITV2 0xff +#define BIT_DRVERLYITV2(x) \ + (((x) & BIT_MASK_DRVERLYITV2) << BIT_SHIFT_DRVERLYITV2) +#define BITS_DRVERLYITV2 (BIT_MASK_DRVERLYITV2 << BIT_SHIFT_DRVERLYITV2) +#define BIT_CLEAR_DRVERLYITV2(x) ((x) & (~BITS_DRVERLYITV2)) +#define BIT_GET_DRVERLYITV2(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV2) & BIT_MASK_DRVERLYITV2) +#define BIT_SET_DRVERLYITV2(x, v) \ + (BIT_CLEAR_DRVERLYITV2(x) | BIT_DRVERLYITV2(v)) -/* 2 REG_FLC_TRPC (Offset 0x06AF) */ +/* 2 REG_NAN_SETTING (Offset 0x05D4) */ -#define BIT_FLC_RPCT_V1 BIT(7) -#define BIT_MODE BIT(6) +#define BIT_EN_MULTI_BCN BIT(31) +#define BIT_ENP2P_DW_AREA BIT(30) -#define BIT_SHIFT_TRPCD 0 -#define BIT_MASK_TRPCD 0x3f -#define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD) -#define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD) +#define BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2 18 +#define BIT_MASK_TBTT_PROHIBIT_HOLD_P2 0xfff +#define BIT_TBTT_PROHIBIT_HOLD_P2(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_HOLD_P2) \ + << BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2) +#define BITS_TBTT_PROHIBIT_HOLD_P2 \ + (BIT_MASK_TBTT_PROHIBIT_HOLD_P2 << BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2) +#define BIT_CLEAR_TBTT_PROHIBIT_HOLD_P2(x) ((x) & (~BITS_TBTT_PROHIBIT_HOLD_P2)) +#define BIT_GET_TBTT_PROHIBIT_HOLD_P2(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_HOLD_P2) & \ + BIT_MASK_TBTT_PROHIBIT_HOLD_P2) +#define BIT_SET_TBTT_PROHIBIT_HOLD_P2(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_HOLD_P2(x) | BIT_TBTT_PROHIBIT_HOLD_P2(v)) +#define BIT_SHIFT_BCN_PORT_PRI 16 +#define BIT_MASK_BCN_PORT_PRI 0x3 +#define BIT_BCN_PORT_PRI(x) \ + (((x) & BIT_MASK_BCN_PORT_PRI) << BIT_SHIFT_BCN_PORT_PRI) +#define BITS_BCN_PORT_PRI (BIT_MASK_BCN_PORT_PRI << BIT_SHIFT_BCN_PORT_PRI) +#define BIT_CLEAR_BCN_PORT_PRI(x) ((x) & (~BITS_BCN_PORT_PRI)) +#define BIT_GET_BCN_PORT_PRI(x) \ + (((x) >> BIT_SHIFT_BCN_PORT_PRI) & BIT_MASK_BCN_PORT_PRI) +#define BIT_SET_BCN_PORT_PRI(x, v) \ + (BIT_CLEAR_BCN_PORT_PRI(x) | BIT_BCN_PORT_PRI(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_EARLYINT_ADJUST (Offset 0x05D4) */ +#define BIT_SHIFT_RXBCN_TIMER 16 +#define BIT_MASK_RXBCN_TIMER 0xffff +#define BIT_RXBCN_TIMER(x) \ + (((x) & BIT_MASK_RXBCN_TIMER) << BIT_SHIFT_RXBCN_TIMER) +#define BITS_RXBCN_TIMER (BIT_MASK_RXBCN_TIMER << BIT_SHIFT_RXBCN_TIMER) +#define BIT_CLEAR_RXBCN_TIMER(x) ((x) & (~BITS_RXBCN_TIMER)) +#define BIT_GET_RXBCN_TIMER(x) \ + (((x) >> BIT_SHIFT_RXBCN_TIMER) & BIT_MASK_RXBCN_TIMER) +#define BIT_SET_RXBCN_TIMER(x, v) \ + (BIT_CLEAR_RXBCN_TIMER(x) | BIT_RXBCN_TIMER(v)) -/* 2 REG_RXPKTMON_CTRL (Offset 0x06B0) */ - +#endif -#define BIT_SHIFT_RXBKQPKT_SEQ 20 -#define BIT_MASK_RXBKQPKT_SEQ 0xf -#define BIT_RXBKQPKT_SEQ(x) (((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ) -#define BIT_GET_RXBKQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ) +#if (HALMAC_8192F_SUPPORT) +/* 2 REG_NAN_SETTING (Offset 0x05D4) */ -#define BIT_SHIFT_RXBEQPKT_SEQ 16 -#define BIT_MASK_RXBEQPKT_SEQ 0xf -#define BIT_RXBEQPKT_SEQ(x) (((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ) -#define BIT_GET_RXBEQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ) +#define BIT_SHIFT_DRVERLYITV1 8 +#define BIT_MASK_DRVERLYITV1 0xff +#define BIT_DRVERLYITV1(x) \ + (((x) & BIT_MASK_DRVERLYITV1) << BIT_SHIFT_DRVERLYITV1) +#define BITS_DRVERLYITV1 (BIT_MASK_DRVERLYITV1 << BIT_SHIFT_DRVERLYITV1) +#define BIT_CLEAR_DRVERLYITV1(x) ((x) & (~BITS_DRVERLYITV1)) +#define BIT_GET_DRVERLYITV1(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV1) & BIT_MASK_DRVERLYITV1) +#define BIT_SET_DRVERLYITV1(x, v) \ + (BIT_CLEAR_DRVERLYITV1(x) | BIT_DRVERLYITV1(v)) +#define BIT_DIS_RX_BSSID_FIT2 BIT(6) +#define BIT_DIS_TSF2_UDT BIT(4) +#define BIT_EN_BCN2_FUNCTION BIT(3) -#define BIT_SHIFT_RXVIQPKT_SEQ 12 -#define BIT_MASK_RXVIQPKT_SEQ 0xf -#define BIT_RXVIQPKT_SEQ(x) (((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ) -#define BIT_GET_RXVIQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXVOQPKT_SEQ 8 -#define BIT_MASK_RXVOQPKT_SEQ 0xf -#define BIT_RXVOQPKT_SEQ(x) (((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ) -#define BIT_GET_RXVOQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ) +/* 2 REG_EARLYINT_ADJUST (Offset 0x05D4) */ -#define BIT_RXBKQPKT_ERR BIT(7) -#define BIT_RXBEQPKT_ERR BIT(6) -#define BIT_RXVIQPKT_ERR BIT(5) -#define BIT_RXVOQPKT_ERR BIT(4) -#define BIT_RXDMA_MON_EN BIT(2) -#define BIT_RXPKT_MON_RST BIT(1) -#define BIT_RXPKT_MON_EN BIT(0) +#define BIT_SHIFT_R_ERLYINTADJ 0 +#define BIT_MASK_R_ERLYINTADJ 0xffff +#define BIT_R_ERLYINTADJ(x) \ + (((x) & BIT_MASK_R_ERLYINTADJ) << BIT_SHIFT_R_ERLYINTADJ) +#define BITS_R_ERLYINTADJ (BIT_MASK_R_ERLYINTADJ << BIT_SHIFT_R_ERLYINTADJ) +#define BIT_CLEAR_R_ERLYINTADJ(x) ((x) & (~BITS_R_ERLYINTADJ)) +#define BIT_GET_R_ERLYINTADJ(x) \ + (((x) >> BIT_SHIFT_R_ERLYINTADJ) & BIT_MASK_R_ERLYINTADJ) +#define BIT_SET_R_ERLYINTADJ(x, v) \ + (BIT_CLEAR_R_ERLYINTADJ(x) | BIT_R_ERLYINTADJ(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BCNERR_CNT (Offset 0x05D8) */ +#define BIT_SHIFT_BCNERR_CNT_OTHERS 24 +#define BIT_MASK_BCNERR_CNT_OTHERS 0xff +#define BIT_BCNERR_CNT_OTHERS(x) \ + (((x) & BIT_MASK_BCNERR_CNT_OTHERS) << BIT_SHIFT_BCNERR_CNT_OTHERS) +#define BITS_BCNERR_CNT_OTHERS \ + (BIT_MASK_BCNERR_CNT_OTHERS << BIT_SHIFT_BCNERR_CNT_OTHERS) +#define BIT_CLEAR_BCNERR_CNT_OTHERS(x) ((x) & (~BITS_BCNERR_CNT_OTHERS)) +#define BIT_GET_BCNERR_CNT_OTHERS(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS) & BIT_MASK_BCNERR_CNT_OTHERS) +#define BIT_SET_BCNERR_CNT_OTHERS(x, v) \ + (BIT_CLEAR_BCNERR_CNT_OTHERS(x) | BIT_BCNERR_CNT_OTHERS(v)) -/* 2 REG_STATE_MON (Offset 0x06B4) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_DMA_MON_EN 24 -#define BIT_MASK_DMA_MON_EN 0x1f -#define BIT_DMA_MON_EN(x) (((x) & BIT_MASK_DMA_MON_EN) << BIT_SHIFT_DMA_MON_EN) -#define BIT_GET_DMA_MON_EN(x) (((x) >> BIT_SHIFT_DMA_MON_EN) & BIT_MASK_DMA_MON_EN) +/* 2 REG_NAN_BCNSPACE (Offset 0x05D8) */ +#define BIT_SHIFT_BCN_SPACE4 16 +#define BIT_MASK_BCN_SPACE4 0xffff +#define BIT_BCN_SPACE4(x) (((x) & BIT_MASK_BCN_SPACE4) << BIT_SHIFT_BCN_SPACE4) +#define BITS_BCN_SPACE4 (BIT_MASK_BCN_SPACE4 << BIT_SHIFT_BCN_SPACE4) +#define BIT_CLEAR_BCN_SPACE4(x) ((x) & (~BITS_BCN_SPACE4)) +#define BIT_GET_BCN_SPACE4(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE4) & BIT_MASK_BCN_SPACE4) +#define BIT_SET_BCN_SPACE4(x, v) (BIT_CLEAR_BCN_SPACE4(x) | BIT_BCN_SPACE4(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BCNERR_CNT (Offset 0x05D8) */ +#define BIT_SHIFT_BCNERR_CNT_INVALID 16 +#define BIT_MASK_BCNERR_CNT_INVALID 0xff +#define BIT_BCNERR_CNT_INVALID(x) \ + (((x) & BIT_MASK_BCNERR_CNT_INVALID) << BIT_SHIFT_BCNERR_CNT_INVALID) +#define BITS_BCNERR_CNT_INVALID \ + (BIT_MASK_BCNERR_CNT_INVALID << BIT_SHIFT_BCNERR_CNT_INVALID) +#define BIT_CLEAR_BCNERR_CNT_INVALID(x) ((x) & (~BITS_BCNERR_CNT_INVALID)) +#define BIT_GET_BCNERR_CNT_INVALID(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID) & BIT_MASK_BCNERR_CNT_INVALID) +#define BIT_SET_BCNERR_CNT_INVALID(x, v) \ + (BIT_CLEAR_BCNERR_CNT_INVALID(x) | BIT_BCNERR_CNT_INVALID(v)) -/* 2 REG_STATE_MON (Offset 0x06B4) */ +#define BIT_SHIFT_BCNERR_CNT_MAC 8 +#define BIT_MASK_BCNERR_CNT_MAC 0xff +#define BIT_BCNERR_CNT_MAC(x) \ + (((x) & BIT_MASK_BCNERR_CNT_MAC) << BIT_SHIFT_BCNERR_CNT_MAC) +#define BITS_BCNERR_CNT_MAC \ + (BIT_MASK_BCNERR_CNT_MAC << BIT_SHIFT_BCNERR_CNT_MAC) +#define BIT_CLEAR_BCNERR_CNT_MAC(x) ((x) & (~BITS_BCNERR_CNT_MAC)) +#define BIT_GET_BCNERR_CNT_MAC(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_MAC) & BIT_MASK_BCNERR_CNT_MAC) +#define BIT_SET_BCNERR_CNT_MAC(x, v) \ + (BIT_CLEAR_BCNERR_CNT_MAC(x) | BIT_BCNERR_CNT_MAC(v)) +#endif -#define BIT_SHIFT_STATE_SEL 24 -#define BIT_MASK_STATE_SEL 0x1f -#define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL) -#define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL) +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_NAN_BCNSPACE (Offset 0x05D8) */ +#define BIT_SHIFT_BCN_SPACE3 0 +#define BIT_MASK_BCN_SPACE3 0xffff +#define BIT_BCN_SPACE3(x) (((x) & BIT_MASK_BCN_SPACE3) << BIT_SHIFT_BCN_SPACE3) +#define BITS_BCN_SPACE3 (BIT_MASK_BCN_SPACE3 << BIT_SHIFT_BCN_SPACE3) +#define BIT_CLEAR_BCN_SPACE3(x) ((x) & (~BITS_BCN_SPACE3)) +#define BIT_GET_BCN_SPACE3(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE3) & BIT_MASK_BCN_SPACE3) +#define BIT_SET_BCN_SPACE3(x, v) (BIT_CLEAR_BCN_SPACE3(x) | BIT_BCN_SPACE3(v)) -#define BIT_SHIFT_STATE_INFO 8 -#define BIT_MASK_STATE_INFO 0xff -#define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO) -#define BIT_GET_STATE_INFO(x) (((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO) +#endif -#define BIT_UPD_NXT_STATE BIT(7) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BCNERR_CNT (Offset 0x05D8) */ +#define BIT_SHIFT_BCNERR_CNT_CCA 0 +#define BIT_MASK_BCNERR_CNT_CCA 0xff +#define BIT_BCNERR_CNT_CCA(x) \ + (((x) & BIT_MASK_BCNERR_CNT_CCA) << BIT_SHIFT_BCNERR_CNT_CCA) +#define BITS_BCNERR_CNT_CCA \ + (BIT_MASK_BCNERR_CNT_CCA << BIT_SHIFT_BCNERR_CNT_CCA) +#define BIT_CLEAR_BCNERR_CNT_CCA(x) ((x) & (~BITS_BCNERR_CNT_CCA)) +#define BIT_GET_BCNERR_CNT_CCA(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_CCA) & BIT_MASK_BCNERR_CNT_CCA) +#define BIT_SET_BCNERR_CNT_CCA(x, v) \ + (BIT_CLEAR_BCNERR_CNT_CCA(x) | BIT_BCNERR_CNT_CCA(v)) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_NAN_SETTING1 (Offset 0x05DC) */ + +#define BIT_SHIFT_SYNCBCN_RXNUM 27 +#define BIT_MASK_SYNCBCN_RXNUM 0x1f +#define BIT_SYNCBCN_RXNUM(x) \ + (((x) & BIT_MASK_SYNCBCN_RXNUM) << BIT_SHIFT_SYNCBCN_RXNUM) +#define BITS_SYNCBCN_RXNUM (BIT_MASK_SYNCBCN_RXNUM << BIT_SHIFT_SYNCBCN_RXNUM) +#define BIT_CLEAR_SYNCBCN_RXNUM(x) ((x) & (~BITS_SYNCBCN_RXNUM)) +#define BIT_GET_SYNCBCN_RXNUM(x) \ + (((x) >> BIT_SHIFT_SYNCBCN_RXNUM) & BIT_MASK_SYNCBCN_RXNUM) +#define BIT_SET_SYNCBCN_RXNUM(x, v) \ + (BIT_CLEAR_SYNCBCN_RXNUM(x) | BIT_SYNCBCN_RXNUM(v)) -/* 2 REG_STATE_MON (Offset 0x06B4) */ +#define BIT_DW_END_EARLY BIT(26) +#define BIT_SHIFT_NAN_ROLE 24 +#define BIT_MASK_NAN_ROLE 0x3 +#define BIT_NAN_ROLE(x) (((x) & BIT_MASK_NAN_ROLE) << BIT_SHIFT_NAN_ROLE) +#define BITS_NAN_ROLE (BIT_MASK_NAN_ROLE << BIT_SHIFT_NAN_ROLE) +#define BIT_CLEAR_NAN_ROLE(x) ((x) & (~BITS_NAN_ROLE)) +#define BIT_GET_NAN_ROLE(x) (((x) >> BIT_SHIFT_NAN_ROLE) & BIT_MASK_NAN_ROLE) +#define BIT_SET_NAN_ROLE(x, v) (BIT_CLEAR_NAN_ROLE(x) | BIT_NAN_ROLE(v)) + +#define BIT_SHIFT_MSLOT_EVTQ 16 +#define BIT_MASK_MSLOT_EVTQ 0xff +#define BIT_MSLOT_EVTQ(x) (((x) & BIT_MASK_MSLOT_EVTQ) << BIT_SHIFT_MSLOT_EVTQ) +#define BITS_MSLOT_EVTQ (BIT_MASK_MSLOT_EVTQ << BIT_SHIFT_MSLOT_EVTQ) +#define BIT_CLEAR_MSLOT_EVTQ(x) ((x) & (~BITS_MSLOT_EVTQ)) +#define BIT_GET_MSLOT_EVTQ(x) \ + (((x) >> BIT_SHIFT_MSLOT_EVTQ) & BIT_MASK_MSLOT_EVTQ) +#define BIT_SET_MSLOT_EVTQ(x, v) (BIT_CLEAR_MSLOT_EVTQ(x) | BIT_MSLOT_EVTQ(v)) + +#define BIT_SHIFT_MDW_EVTQ 8 +#define BIT_MASK_MDW_EVTQ 0xff +#define BIT_MDW_EVTQ(x) (((x) & BIT_MASK_MDW_EVTQ) << BIT_SHIFT_MDW_EVTQ) +#define BITS_MDW_EVTQ (BIT_MASK_MDW_EVTQ << BIT_SHIFT_MDW_EVTQ) +#define BIT_CLEAR_MDW_EVTQ(x) ((x) & (~BITS_MDW_EVTQ)) +#define BIT_GET_MDW_EVTQ(x) (((x) >> BIT_SHIFT_MDW_EVTQ) & BIT_MASK_MDW_EVTQ) +#define BIT_SET_MDW_EVTQ(x, v) (BIT_CLEAR_MDW_EVTQ(x) | BIT_MDW_EVTQ(v)) + +#define BIT_SHIFT_HC 0 +#define BIT_MASK_HC 0xff +#define BIT_HC(x) (((x) & BIT_MASK_HC) << BIT_SHIFT_HC) +#define BITS_HC (BIT_MASK_HC << BIT_SHIFT_HC) +#define BIT_CLEAR_HC(x) ((x) & (~BITS_HC)) +#define BIT_GET_HC(x) (((x) >> BIT_SHIFT_HC) & BIT_MASK_HC) +#define BIT_SET_HC(x, v) (BIT_CLEAR_HC(x) | BIT_HC(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKT_MON_EN 0 -#define BIT_MASK_PKT_MON_EN 0x7f -#define BIT_PKT_MON_EN(x) (((x) & BIT_MASK_PKT_MON_EN) << BIT_SHIFT_PKT_MON_EN) -#define BIT_GET_PKT_MON_EN(x) (((x) >> BIT_SHIFT_PKT_MON_EN) & BIT_MASK_PKT_MON_EN) +/* 2 REG_NOA_PARAM (Offset 0x05E0) */ +#define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH) +#define BIT_MASK_NOA_COUNT 0xff +#define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT) +#define BITS_NOA_COUNT (BIT_MASK_NOA_COUNT << BIT_SHIFT_NOA_COUNT) +#define BIT_CLEAR_NOA_COUNT(x) ((x) & (~BITS_NOA_COUNT)) +#define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT) +#define BIT_SET_NOA_COUNT(x, v) (BIT_CLEAR_NOA_COUNT(x) | BIT_NOA_COUNT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_NOA_PARAM (Offset 0x05E0) */ +#define BIT_SHIFT_NOA_DURATION 0 +#define BIT_MASK_NOA_DURATION 0xffffffffL +#define BIT_NOA_DURATION(x) \ + (((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION) +#define BITS_NOA_DURATION (BIT_MASK_NOA_DURATION << BIT_SHIFT_NOA_DURATION) +#define BIT_CLEAR_NOA_DURATION(x) ((x) & (~BITS_NOA_DURATION)) +#define BIT_GET_NOA_DURATION(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION) +#define BIT_SET_NOA_DURATION(x, v) \ + (BIT_CLEAR_NOA_DURATION(x) | BIT_NOA_DURATION(v)) -/* 2 REG_STATE_MON (Offset 0x06B4) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_CUR_STATE 0 -#define BIT_MASK_CUR_STATE 0x7f -#define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE) -#define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE) +/* 2 REG_NOA_PARAM (Offset 0x05E0) */ +#define BIT_SHIFT_NOA_DURATION_V1 0 +#define BIT_MASK_NOA_DURATION_V1 0xffffffffL +#define BIT_NOA_DURATION_V1(x) \ + (((x) & BIT_MASK_NOA_DURATION_V1) << BIT_SHIFT_NOA_DURATION_V1) +#define BITS_NOA_DURATION_V1 \ + (BIT_MASK_NOA_DURATION_V1 << BIT_SHIFT_NOA_DURATION_V1) +#define BIT_CLEAR_NOA_DURATION_V1(x) ((x) & (~BITS_NOA_DURATION_V1)) +#define BIT_GET_NOA_DURATION_V1(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_V1) & BIT_MASK_NOA_DURATION_V1) +#define BIT_SET_NOA_DURATION_V1(x, v) \ + (BIT_CLEAR_NOA_DURATION_V1(x) | BIT_NOA_DURATION_V1(v)) -/* 2 REG_ERROR_MON (Offset 0x06B8) */ +/* 2 REG_NOA_PARAM_1 (Offset 0x05E4) */ -#define BIT_MACRX_ERR_1 BIT(17) -#define BIT_MACRX_ERR_0 BIT(16) -#define BIT_MACTX_ERR_3 BIT(3) -#define BIT_MACTX_ERR_2 BIT(2) -#define BIT_MACTX_ERR_1 BIT(1) -#define BIT_MACTX_ERR_0 BIT(0) +#define BIT_SHIFT_NOA_INTERVAL_V1 0 +#define BIT_MASK_NOA_INTERVAL_V1 0xffffffffL +#define BIT_NOA_INTERVAL_V1(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_V1) << BIT_SHIFT_NOA_INTERVAL_V1) +#define BITS_NOA_INTERVAL_V1 \ + (BIT_MASK_NOA_INTERVAL_V1 << BIT_SHIFT_NOA_INTERVAL_V1) +#define BIT_CLEAR_NOA_INTERVAL_V1(x) ((x) & (~BITS_NOA_INTERVAL_V1)) +#define BIT_GET_NOA_INTERVAL_V1(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_V1) & BIT_MASK_NOA_INTERVAL_V1) +#define BIT_SET_NOA_INTERVAL_V1(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_V1(x) | BIT_NOA_INTERVAL_V1(v)) -/* 2 REG_SEARCH_MACID (Offset 0x06BC) */ +/* 2 REG_NOA_PARAM_2 (Offset 0x05E8) */ -#define BIT_EN_TXRPTBUF_CLK BIT(31) +#define BIT_SHIFT_NOA_START_TIME_V1 0 +#define BIT_MASK_NOA_START_TIME_V1 0xffffffffL +#define BIT_NOA_START_TIME_V1(x) \ + (((x) & BIT_MASK_NOA_START_TIME_V1) << BIT_SHIFT_NOA_START_TIME_V1) +#define BITS_NOA_START_TIME_V1 \ + (BIT_MASK_NOA_START_TIME_V1 << BIT_SHIFT_NOA_START_TIME_V1) +#define BIT_CLEAR_NOA_START_TIME_V1(x) ((x) & (~BITS_NOA_START_TIME_V1)) +#define BIT_GET_NOA_START_TIME_V1(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_V1) & BIT_MASK_NOA_START_TIME_V1) +#define BIT_SET_NOA_START_TIME_V1(x, v) \ + (BIT_CLEAR_NOA_START_TIME_V1(x) | BIT_NOA_START_TIME_V1(v)) -#define BIT_SHIFT_INFO_INDEX_OFFSET 16 -#define BIT_MASK_INFO_INDEX_OFFSET 0x1fff -#define BIT_INFO_INDEX_OFFSET(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET) -#define BIT_GET_INFO_INDEX_OFFSET(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET) +#endif +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_MU_DBG_INFO (Offset 0x05E8) */ +#define BIT_SHIFT_MU_DBG_INFO 0 +#define BIT_MASK_MU_DBG_INFO 0xffffffffL +#define BIT_MU_DBG_INFO(x) \ + (((x) & BIT_MASK_MU_DBG_INFO) << BIT_SHIFT_MU_DBG_INFO) +#define BITS_MU_DBG_INFO (BIT_MASK_MU_DBG_INFO << BIT_SHIFT_MU_DBG_INFO) +#define BIT_CLEAR_MU_DBG_INFO(x) ((x) & (~BITS_MU_DBG_INFO)) +#define BIT_GET_MU_DBG_INFO(x) \ + (((x) >> BIT_SHIFT_MU_DBG_INFO) & BIT_MASK_MU_DBG_INFO) +#define BIT_SET_MU_DBG_INFO(x, v) \ + (BIT_CLEAR_MU_DBG_INFO(x) | BIT_MU_DBG_INFO(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_SEARCH_MACID (Offset 0x06BC) */ +/* 2 REG_NOA_PARAM_3 (Offset 0x05EC) */ -#define BIT_WMAC_SRCH_FIFOFULL BIT(15) +#define BIT_SHIFT_NOA_COUNT_V3 0 +#define BIT_MASK_NOA_COUNT_V3 0xff +#define BIT_NOA_COUNT_V3(x) \ + (((x) & BIT_MASK_NOA_COUNT_V3) << BIT_SHIFT_NOA_COUNT_V3) +#define BITS_NOA_COUNT_V3 (BIT_MASK_NOA_COUNT_V3 << BIT_SHIFT_NOA_COUNT_V3) +#define BIT_CLEAR_NOA_COUNT_V3(x) ((x) & (~BITS_NOA_COUNT_V3)) +#define BIT_GET_NOA_COUNT_V3(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_V3) & BIT_MASK_NOA_COUNT_V3) +#define BIT_SET_NOA_COUNT_V3(x, v) \ + (BIT_CLEAR_NOA_COUNT_V3(x) | BIT_NOA_COUNT_V3(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_NOA_PARAM_3 (Offset 0x05EC) */ +#define BIT_SHIFT_NOA_COUNT_V1 0 +#define BIT_MASK_NOA_COUNT_V1 0xffffffffL +#define BIT_NOA_COUNT_V1(x) \ + (((x) & BIT_MASK_NOA_COUNT_V1) << BIT_SHIFT_NOA_COUNT_V1) +#define BITS_NOA_COUNT_V1 (BIT_MASK_NOA_COUNT_V1 << BIT_SHIFT_NOA_COUNT_V1) +#define BIT_CLEAR_NOA_COUNT_V1(x) ((x) & (~BITS_NOA_COUNT_V1)) +#define BIT_GET_NOA_COUNT_V1(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_V1) & BIT_MASK_NOA_COUNT_V1) +#define BIT_SET_NOA_COUNT_V1(x, v) \ + (BIT_CLEAR_NOA_COUNT_V1(x) | BIT_NOA_COUNT_V1(v)) -/* 2 REG_SEARCH_MACID (Offset 0x06BC) */ +#endif -#define BIT_DIS_INFOSRCH BIT(14) -#define BIT_DISABLE_B0 BIT(13) +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_INFO_ADDR_OFFSET 0 -#define BIT_MASK_INFO_ADDR_OFFSET 0x1fff -#define BIT_INFO_ADDR_OFFSET(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET) -#define BIT_GET_INFO_ADDR_OFFSET(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET) +/* 2 REG_MU_DBG_INFO_1 (Offset 0x05EC) */ +#define BIT_SHIFT_MU_DBG_INFO_1 0 +#define BIT_MASK_MU_DBG_INFO_1 0xffffffffL +#define BIT_MU_DBG_INFO_1(x) \ + (((x) & BIT_MASK_MU_DBG_INFO_1) << BIT_SHIFT_MU_DBG_INFO_1) +#define BITS_MU_DBG_INFO_1 (BIT_MASK_MU_DBG_INFO_1 << BIT_SHIFT_MU_DBG_INFO_1) +#define BIT_CLEAR_MU_DBG_INFO_1(x) ((x) & (~BITS_MU_DBG_INFO_1)) +#define BIT_GET_MU_DBG_INFO_1(x) \ + (((x) >> BIT_SHIFT_MU_DBG_INFO_1) & BIT_MASK_MU_DBG_INFO_1) +#define BIT_SET_MU_DBG_INFO_1(x, v) \ + (BIT_CLEAR_MU_DBG_INFO_1(x) | BIT_MU_DBG_INFO_1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_NOA_SUBIE (Offset 0x05ED) */ +#define BIT_MORE_NOA_DESC BIT(19) +#define BIT_NOA_DESC1_VALID BIT(18) +#define BIT_NOA_DESC0_VALID BIT(17) +#define BIT_NOA_HEAD_VALID BIT(16) +#define BIT_NOA_OPP_PS BIT(15) -/* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */ +#define BIT_SHIFT_NOA_CTW 8 +#define BIT_MASK_NOA_CTW 0x7f +#define BIT_NOA_CTW(x) (((x) & BIT_MASK_NOA_CTW) << BIT_SHIFT_NOA_CTW) +#define BITS_NOA_CTW (BIT_MASK_NOA_CTW << BIT_SHIFT_NOA_CTW) +#define BIT_CLEAR_NOA_CTW(x) ((x) & (~BITS_NOA_CTW)) +#define BIT_GET_NOA_CTW(x) (((x) >> BIT_SHIFT_NOA_CTW) & BIT_MASK_NOA_CTW) +#define BIT_SET_NOA_CTW(x, v) (BIT_CLEAR_NOA_CTW(x) | BIT_NOA_CTW(v)) -#define BIT_PRI_MASK_RX_RESP BIT(126) -#define BIT_PRI_MASK_RXOFDM BIT(125) -#define BIT_PRI_MASK_RXCCK BIT(124) +#define BIT_SHIFT_NOA_INDEX 0 +#define BIT_MASK_NOA_INDEX 0xff +#define BIT_NOA_INDEX(x) (((x) & BIT_MASK_NOA_INDEX) << BIT_SHIFT_NOA_INDEX) +#define BITS_NOA_INDEX (BIT_MASK_NOA_INDEX << BIT_SHIFT_NOA_INDEX) +#define BIT_CLEAR_NOA_INDEX(x) ((x) & (~BITS_NOA_INDEX)) +#define BIT_GET_NOA_INDEX(x) (((x) >> BIT_SHIFT_NOA_INDEX) & BIT_MASK_NOA_INDEX) +#define BIT_SET_NOA_INDEX(x, v) (BIT_CLEAR_NOA_INDEX(x) | BIT_NOA_INDEX(v)) -#define BIT_SHIFT_PRI_MASK_TXAC (117 & CPU_OPT_WIDTH) -#define BIT_MASK_PRI_MASK_TXAC 0x7f -#define BIT_PRI_MASK_TXAC(x) (((x) & BIT_MASK_PRI_MASK_TXAC) << BIT_SHIFT_PRI_MASK_TXAC) -#define BIT_GET_PRI_MASK_TXAC(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC) & BIT_MASK_PRI_MASK_TXAC) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PRI_MASK_NAV (109 & CPU_OPT_WIDTH) -#define BIT_MASK_PRI_MASK_NAV 0xff -#define BIT_PRI_MASK_NAV(x) (((x) & BIT_MASK_PRI_MASK_NAV) << BIT_SHIFT_PRI_MASK_NAV) -#define BIT_GET_PRI_MASK_NAV(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV) & BIT_MASK_PRI_MASK_NAV) +/* 2 REG_P2P_RST (Offset 0x05F0) */ -#define BIT_PRI_MASK_CCK BIT(108) -#define BIT_PRI_MASK_OFDM BIT(107) -#define BIT_PRI_MASK_RTY BIT(106) +#define BIT_P2P2_PWR_RST1 BIT(5) +#define BIT_P2P2_PWR_RST0 BIT(4) +#define BIT_P2P1_PWR_RST1 BIT(3) +#define BIT_P2P1_PWR_RST0 BIT(2) +#define BIT_P2P_PWR_RST1_V1 BIT(1) +#define BIT_P2P_PWR_RST0_V1 BIT(0) -#define BIT_SHIFT_PRI_MASK_NUM (102 & CPU_OPT_WIDTH) -#define BIT_MASK_PRI_MASK_NUM 0xf -#define BIT_PRI_MASK_NUM(x) (((x) & BIT_MASK_PRI_MASK_NUM) << BIT_SHIFT_PRI_MASK_NUM) -#define BIT_GET_PRI_MASK_NUM(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM) & BIT_MASK_PRI_MASK_NUM) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_PRI_MASK_TYPE (98 & CPU_OPT_WIDTH) -#define BIT_MASK_PRI_MASK_TYPE 0xf -#define BIT_PRI_MASK_TYPE(x) (((x) & BIT_MASK_PRI_MASK_TYPE) << BIT_SHIFT_PRI_MASK_TYPE) -#define BIT_GET_PRI_MASK_TYPE(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE) & BIT_MASK_PRI_MASK_TYPE) +/* 2 REG_SCH_DBG_SEL (Offset 0x05F0) */ -#define BIT_OOB BIT(97) -#define BIT_ANT_SEL BIT(96) +#define BIT_SHIFT_SCH_DBG_SEL 0 +#define BIT_MASK_SCH_DBG_SEL 0xff +#define BIT_SCH_DBG_SEL(x) \ + (((x) & BIT_MASK_SCH_DBG_SEL) << BIT_SHIFT_SCH_DBG_SEL) +#define BITS_SCH_DBG_SEL (BIT_MASK_SCH_DBG_SEL << BIT_SHIFT_SCH_DBG_SEL) +#define BIT_CLEAR_SCH_DBG_SEL(x) ((x) & (~BITS_SCH_DBG_SEL)) +#define BIT_GET_SCH_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_SCH_DBG_SEL) & BIT_MASK_SCH_DBG_SEL) +#define BIT_SET_SCH_DBG_SEL(x, v) \ + (BIT_CLEAR_SCH_DBG_SEL(x) | BIT_SCH_DBG_SEL(v)) -#define BIT_SHIFT_BREAK_TABLE_2 (80 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_2 0xffff -#define BIT_BREAK_TABLE_2(x) (((x) & BIT_MASK_BREAK_TABLE_2) << BIT_SHIFT_BREAK_TABLE_2) -#define BIT_GET_BREAK_TABLE_2(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2) & BIT_MASK_BREAK_TABLE_2) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BREAK_TABLE_1 (64 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_1 0xffff -#define BIT_BREAK_TABLE_1(x) (((x) & BIT_MASK_BREAK_TABLE_1) << BIT_SHIFT_BREAK_TABLE_1) -#define BIT_GET_BREAK_TABLE_1(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1) & BIT_MASK_BREAK_TABLE_1) +/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_MAC_STOP_CPUMGQ BIT(16) -#define BIT_SHIFT_COEX_TABLE_2 (32 & CPU_OPT_WIDTH) -#define BIT_MASK_COEX_TABLE_2 0xffffffffL -#define BIT_COEX_TABLE_2(x) (((x) & BIT_MASK_COEX_TABLE_2) << BIT_SHIFT_COEX_TABLE_2) -#define BIT_GET_COEX_TABLE_2(x) (((x) >> BIT_SHIFT_COEX_TABLE_2) & BIT_MASK_COEX_TABLE_2) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_COEX_TABLE_1 0 -#define BIT_MASK_COEX_TABLE_1 0xffffffffL -#define BIT_COEX_TABLE_1(x) (((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1) -#define BIT_GET_COEX_TABLE_1(x) (((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1) +/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_SYNC_TSF_NOW BIT(2) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_SYNC_CLI_ONCE_RIGHT_NOW BIT(2) -/* 2 REG_RXCMD_0 (Offset 0x06D0) */ +#endif -#define BIT_RXCMD_EN BIT(31) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXCMD_INFO 0 -#define BIT_MASK_RXCMD_INFO 0x7fffffffL -#define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO) -#define BIT_GET_RXCMD_INFO(x) (((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO) +/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_EN_P2P_CTWINDOW BIT(1) -/* 2 REG_RXCMD_1 (Offset 0x06D4) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_RXCMD_PRD 0 -#define BIT_MASK_RXCMD_PRD 0xffff -#define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD) -#define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD) +/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_SYNC_CLI BIT(1) -/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_RESP_MFB 25 -#define BIT_MASK_WMAC_RESP_MFB 0x7f -#define BIT_WMAC_RESP_MFB(x) (((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB) -#define BIT_GET_WMAC_RESP_MFB(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB) +/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_SYNC_CLI_ONCE_BY_TBTT BIT(1) -#define BIT_SHIFT_WMAC_ANTINF_SEL 23 -#define BIT_MASK_WMAC_ANTINF_SEL 0x3 -#define BIT_WMAC_ANTINF_SEL(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL) -#define BIT_GET_WMAC_ANTINF_SEL(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_ANTSEL_SEL 21 -#define BIT_MASK_WMAC_ANTSEL_SEL 0x3 -#define BIT_WMAC_ANTSEL_SEL(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL) -#define BIT_GET_WMAC_ANTSEL_SEL(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL) +/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ +#define BIT_SCHEDULER_RST_V1 BIT(0) +#define BIT_EN_P2P_BCNQ_AREA BIT(0) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_MU_DBG_ERR_FLAG (Offset 0x05F2) */ +#define BIT_BCN_PORTID_ERR BIT(2) -/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_MU_DBG_ERR_FLAG 0 +#define BIT_MASK_MU_DBG_ERR_FLAG 0x3 +#define BIT_MU_DBG_ERR_FLAG(x) \ + (((x) & BIT_MASK_MU_DBG_ERR_FLAG) << BIT_SHIFT_MU_DBG_ERR_FLAG) +#define BITS_MU_DBG_ERR_FLAG \ + (BIT_MASK_MU_DBG_ERR_FLAG << BIT_SHIFT_MU_DBG_ERR_FLAG) +#define BIT_CLEAR_MU_DBG_ERR_FLAG(x) ((x) & (~BITS_MU_DBG_ERR_FLAG)) +#define BIT_GET_MU_DBG_ERR_FLAG(x) \ + (((x) >> BIT_SHIFT_MU_DBG_ERR_FLAG) & BIT_MASK_MU_DBG_ERR_FLAG) +#define BIT_SET_MU_DBG_ERR_FLAG(x, v) \ + (BIT_CLEAR_MU_DBG_ERR_FLAG(x) | BIT_MU_DBG_ERR_FLAG(v)) +/* 2 REG_TX_ERR_RECOVERY_RST (Offset 0x05F3) */ -#define BIT_SHIFT_RESP_TXPOWER 18 -#define BIT_MASK_RESP_TXPOWER 0x7 -#define BIT_RESP_TXPOWER(x) (((x) & BIT_MASK_RESP_TXPOWER) << BIT_SHIFT_RESP_TXPOWER) -#define BIT_GET_RESP_TXPOWER(x) (((x) >> BIT_SHIFT_RESP_TXPOWER) & BIT_MASK_RESP_TXPOWER) +#define BIT_SHIFT_ERR_RECOVER_CNT 4 +#define BIT_MASK_ERR_RECOVER_CNT 0xf +#define BIT_ERR_RECOVER_CNT(x) \ + (((x) & BIT_MASK_ERR_RECOVER_CNT) << BIT_SHIFT_ERR_RECOVER_CNT) +#define BITS_ERR_RECOVER_CNT \ + (BIT_MASK_ERR_RECOVER_CNT << BIT_SHIFT_ERR_RECOVER_CNT) +#define BIT_CLEAR_ERR_RECOVER_CNT(x) ((x) & (~BITS_ERR_RECOVER_CNT)) +#define BIT_GET_ERR_RECOVER_CNT(x) \ + (((x) >> BIT_SHIFT_ERR_RECOVER_CNT) & BIT_MASK_ERR_RECOVER_CNT) +#define BIT_SET_ERR_RECOVER_CNT(x, v) \ + (BIT_CLEAR_ERR_RECOVER_CNT(x) | BIT_ERR_RECOVER_CNT(v)) +#define BIT_RX_HANG_ERR BIT(2) +#define BIT_TX_HANG_ERR BIT(1) +#define BIT_TX_ERR_RECOVERY_RST BIT(0) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SCH_DBG (Offset 0x05F4) */ +#define BIT_SHIFT_SCH_DBG 0 +#define BIT_MASK_SCH_DBG 0xffffffffL +#define BIT_SCH_DBG(x) (((x) & BIT_MASK_SCH_DBG) << BIT_SHIFT_SCH_DBG) +#define BITS_SCH_DBG (BIT_MASK_SCH_DBG << BIT_SHIFT_SCH_DBG) +#define BIT_CLEAR_SCH_DBG(x) ((x) & (~BITS_SCH_DBG)) +#define BIT_GET_SCH_DBG(x) (((x) >> BIT_SHIFT_SCH_DBG) & BIT_MASK_SCH_DBG) +#define BIT_SET_SCH_DBG(x, v) (BIT_CLEAR_SCH_DBG(x) | BIT_SCH_DBG(v)) -/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18 -#define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7 -#define BIT_R_WMAC_RESP_TXPOWER(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER) -#define BIT_GET_R_WMAC_RESP_TXPOWER(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER) +/* 2 REG_SCH_DBG_VALUE (Offset 0x05F4) */ +#define BIT_SHIFT_SCH_DBG_VALUE 0 +#define BIT_MASK_SCH_DBG_VALUE 0xffffffffL +#define BIT_SCH_DBG_VALUE(x) \ + (((x) & BIT_MASK_SCH_DBG_VALUE) << BIT_SHIFT_SCH_DBG_VALUE) +#define BITS_SCH_DBG_VALUE (BIT_MASK_SCH_DBG_VALUE << BIT_SHIFT_SCH_DBG_VALUE) +#define BIT_CLEAR_SCH_DBG_VALUE(x) ((x) & (~BITS_SCH_DBG_VALUE)) +#define BIT_GET_SCH_DBG_VALUE(x) \ + (((x) >> BIT_SHIFT_SCH_DBG_VALUE) & BIT_MASK_SCH_DBG_VALUE) +#define BIT_SET_SCH_DBG_VALUE(x, v) \ + (BIT_CLEAR_SCH_DBG_VALUE(x) | BIT_SCH_DBG_VALUE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_SCH_TXCMD (Offset 0x05F8) */ +#define BIT_DIS_RX_BSSID_FIT BIT(6) +#define BIT_DIS_TSF_UDT BIT(4) -/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_SCH_TXCMD 0 +#define BIT_MASK_SCH_TXCMD 0xffffffffL +#define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD) +#define BITS_SCH_TXCMD (BIT_MASK_SCH_TXCMD << BIT_SHIFT_SCH_TXCMD) +#define BIT_CLEAR_SCH_TXCMD(x) ((x) & (~BITS_SCH_TXCMD)) +#define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD) +#define BIT_SET_SCH_TXCMD(x, v) (BIT_CLEAR_SCH_TXCMD(x) | BIT_SCH_TXCMD(v)) +#define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0 +#define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf +#define BIT_TBTT_PROHIBIT_SETUP(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP) +#define BITS_TBTT_PROHIBIT_SETUP \ + (BIT_MASK_TBTT_PROHIBIT_SETUP << BIT_SHIFT_TBTT_PROHIBIT_SETUP) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) ((x) & (~BITS_TBTT_PROHIBIT_SETUP)) +#define BIT_GET_TBTT_PROHIBIT_SETUP(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP) +#define BIT_SET_TBTT_PROHIBIT_SETUP(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) | BIT_TBTT_PROHIBIT_SETUP(v)) -#define BIT_SHIFT_RESP_TXAGC_B 13 -#define BIT_MASK_RESP_TXAGC_B 0x1f -#define BIT_RESP_TXAGC_B(x) (((x) & BIT_MASK_RESP_TXAGC_B) << BIT_SHIFT_RESP_TXAGC_B) -#define BIT_GET_RESP_TXAGC_B(x) (((x) >> BIT_SHIFT_RESP_TXAGC_B) & BIT_MASK_RESP_TXAGC_B) +#define BIT_SHIFT_DRVERLYITV 0 +#define BIT_MASK_DRVERLYITV 0xff +#define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV) +#define BITS_DRVERLYITV (BIT_MASK_DRVERLYITV << BIT_SHIFT_DRVERLYITV) +#define BIT_CLEAR_DRVERLYITV(x) ((x) & (~BITS_DRVERLYITV)) +#define BIT_GET_DRVERLYITV(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV) +#define BIT_SET_DRVERLYITV(x, v) (BIT_CLEAR_DRVERLYITV(x) | BIT_DRVERLYITV(v)) +#define BIT_SHIFT_BCNDMATIM 0 +#define BIT_MASK_BCNDMATIM 0xff +#define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM) +#define BITS_BCNDMATIM (BIT_MASK_BCNDMATIM << BIT_SHIFT_BCNDMATIM) +#define BIT_CLEAR_BCNDMATIM(x) ((x) & (~BITS_BCNDMATIM)) +#define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM) +#define BIT_SET_BCNDMATIM(x, v) (BIT_CLEAR_BCNDMATIM(x) | BIT_BCNDMATIM(v)) -#define BIT_SHIFT_RESP_TXAGC_A 8 -#define BIT_MASK_RESP_TXAGC_A 0x1f -#define BIT_RESP_TXAGC_A(x) (((x) & BIT_MASK_RESP_TXAGC_A) << BIT_SHIFT_RESP_TXAGC_A) -#define BIT_GET_RESP_TXAGC_A(x) (((x) >> BIT_SHIFT_RESP_TXAGC_A) & BIT_MASK_RESP_TXAGC_A) +#define BIT_SHIFT_CTWND 0 +#define BIT_MASK_CTWND 0xff +#define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND) +#define BITS_CTWND (BIT_MASK_CTWND << BIT_SHIFT_CTWND) +#define BIT_CLEAR_CTWND(x) ((x) & (~BITS_CTWND)) +#define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND) +#define BIT_SET_CTWND(x, v) (BIT_CLEAR_CTWND(x) | BIT_CTWND(v)) -#define BIT_RESP_ANTSEL_B BIT(7) -#define BIT_RESP_ANTSEL_A BIT(6) +#endif + +#if (HALMAC_8821C_SUPPORT) -#define BIT_SHIFT_RESP_TXANT_CCK 4 -#define BIT_MASK_RESP_TXANT_CCK 0x3 -#define BIT_RESP_TXANT_CCK(x) (((x) & BIT_MASK_RESP_TXANT_CCK) << BIT_SHIFT_RESP_TXANT_CCK) -#define BIT_GET_RESP_TXANT_CCK(x) (((x) >> BIT_SHIFT_RESP_TXANT_CCK) & BIT_MASK_RESP_TXANT_CCK) +/* 2 REG_PAGE5_DUMMY (Offset 0x05FC) */ +#define BIT_ECO_TXOP_BREAK_FORCE_CFEND BIT(0) -#define BIT_SHIFT_RESP_TXANT_L 2 -#define BIT_MASK_RESP_TXANT_L 0x3 -#define BIT_RESP_TXANT_L(x) (((x) & BIT_MASK_RESP_TXANT_L) << BIT_SHIFT_RESP_TXANT_L) -#define BIT_GET_RESP_TXANT_L(x) (((x) >> BIT_SHIFT_RESP_TXANT_L) & BIT_MASK_RESP_TXANT_L) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_RESP_TXANT_HT 0 -#define BIT_MASK_RESP_TXANT_HT 0x3 -#define BIT_RESP_TXANT_HT(x) (((x) & BIT_MASK_RESP_TXANT_HT) << BIT_SHIFT_RESP_TXANT_HT) -#define BIT_GET_RESP_TXANT_HT(x) (((x) >> BIT_SHIFT_RESP_TXANT_HT) & BIT_MASK_RESP_TXANT_HT) +/* 2 REG_WMAC_CR (Offset 0x0600) */ +#define BIT_APSDOFF_STATUS BIT(7) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_CR (Offset 0x0600) */ +#define BIT_APSDOFF BIT(6) -/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_WMAC_RESP_TXANT 0 -#define BIT_MASK_WMAC_RESP_TXANT 0x3ffff -#define BIT_WMAC_RESP_TXANT(x) (((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT) -#define BIT_GET_WMAC_RESP_TXANT(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT) +/* 2 REG_WMAC_CR (Offset 0x0600) */ +#define BIT_STANDBY_STATUS BIT(5) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_CR (Offset 0x0600) */ +#define BIT_IC_MACPHY_M BIT(0) -/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#endif -#define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31) +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ +#define BIT_FWEN BIT(7) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ -#define BIT_WMAC_USE_NDPARATE BIT(30) +#define BIT_FWRX_EN BIT(7) -#define BIT_SHIFT_WMAC_CSI_RATE 24 -#define BIT_MASK_WMAC_CSI_RATE 0x3f -#define BIT_WMAC_CSI_RATE(x) (((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE) -#define BIT_GET_WMAC_CSI_RATE(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_RESP_TXRATE 16 -#define BIT_MASK_WMAC_RESP_TXRATE 0xff -#define BIT_WMAC_RESP_TXRATE(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE) -#define BIT_GET_WMAC_RESP_TXRATE(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE) +/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ +#define BIT_PHYSTS_PKT_CTRL BIT(6) #endif - #if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ -/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_FWFULL_TO_RXFF_EN BIT(5) -#define BIT_CSI_FORCE_RATE_EN BIT(15) +#endif -#define BIT_SHIFT_CSI_RSC 13 -#define BIT_MASK_CSI_RSC 0x3 -#define BIT_CSI_RSC(x) (((x) & BIT_MASK_CSI_RSC) << BIT_SHIFT_CSI_RSC) -#define BIT_GET_CSI_RSC(x) (((x) >> BIT_SHIFT_CSI_RSC) & BIT_MASK_CSI_RSC) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_CSI_GID_SEL BIT(12) -#define BIT_RDCSIMD_FLAG_TRIG_SEL BIT(11) -#define BIT_NDPVLD_POS_RST_FFPTR_DIS BIT(10) -#define BIT_NDPVLD_PROTECT_RDRDY_DIS BIT(9) -#define BIT_RDCSI_EMPTY_APPZERO BIT(8) +/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ -#endif +#define BIT_APPHDR_MIDSRCH_FAIL BIT(4) +#define BIT_FWPARSING_EN BIT(3) +#define BIT_SHIFT_APPEND_MHDR_LEN 0 +#define BIT_MASK_APPEND_MHDR_LEN 0x7 +#define BIT_APPEND_MHDR_LEN(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN) +#define BITS_APPEND_MHDR_LEN \ + (BIT_MASK_APPEND_MHDR_LEN << BIT_SHIFT_APPEND_MHDR_LEN) +#define BIT_CLEAR_APPEND_MHDR_LEN(x) ((x) & (~BITS_APPEND_MHDR_LEN)) +#define BIT_GET_APPEND_MHDR_LEN(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN) +#define BIT_SET_APPEND_MHDR_LEN(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN(x) | BIT_APPEND_MHDR_LEN(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +/* 2 REG_BWOPMODE (Offset 0x0603) */ -#define BIT_BBPSF_MPDUCHKEN BIT(5) +#define BIT_WMAC_20MHZBW BIT(2) +#define BIT_WMAC_M11J BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_EN_RTS_ADDR BIT(31) +#define BIT_WMAC_DISABLE_CCK BIT(30) +#define BIT_WMAC_RAW_LEN BIT(29) +#define BIT_WMAC_NOTX_IN_RXNDP BIT(28) +#define BIT_WMAC_EN_EOF BIT(27) -/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#endif -#define BIT_BBPSF_MHCHKEN BIT(4) -#define BIT_BBPSF_ERRCHKEN BIT(3) +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_BBPSF_ERRTHR 0 -#define BIT_MASK_BBPSF_ERRTHR 0x7 -#define BIT_BBPSF_ERRTHR(x) (((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR) -#define BIT_GET_BBPSF_ERRTHR(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_TCRPWRMGT_HWCTL_V1 BIT(26) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_BF_SEL BIT(26) -/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +#endif -#define BIT_NOA_PARSER_EN BIT(15) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_BF_SEL BIT(25) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +/* 2 REG_TCR (Offset 0x0604) */ -#define BIT_BSSID_SEL BIT(14) +#define BIT_WMAC_ANTMODE_SEL BIT(25) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_RXLEN_SEL BIT(24) -/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BSSID_SEL 12 -#define BIT_MASK_BSSID_SEL 0x7 -#define BIT_BSSID_SEL(x) (((x) & BIT_MASK_BSSID_SEL) << BIT_SHIFT_BSSID_SEL) -#define BIT_GET_BSSID_SEL(x) (((x) >> BIT_SHIFT_BSSID_SEL) & BIT_MASK_BSSID_SEL) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_TCRPWRMGT_HWCTL_EN BIT(24) -/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_P2P_OUI_TYPE 0 -#define BIT_MASK_P2P_OUI_TYPE 0xff -#define BIT_P2P_OUI_TYPE(x) (((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE) -#define BIT_GET_P2P_OUI_TYPE(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_SMOOTH_VAL BIT(23) -/* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_TXCSI_AID0 (48 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_TXCSI_AID0 0x1ff -#define BIT_R_WMAC_TXCSI_AID0(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0) << BIT_SHIFT_R_WMAC_TXCSI_AID0) -#define BIT_GET_R_WMAC_TXCSI_AID0(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0) & BIT_MASK_R_WMAC_TXCSI_AID0) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_EN_SCRAM_INC BIT(22) -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R0(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */ +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_UNDERFLOWEN_CMPLEN_SEL BIT(21) -#define BIT_SHIFT_R_WMAC_TXCSI_AID1 (48 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_TXCSI_AID1 0x1ff -#define BIT_R_WMAC_TXCSI_AID1(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1) << BIT_SHIFT_R_WMAC_TXCSI_AID1) -#define BIT_GET_R_WMAC_TXCSI_AID1(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1) & BIT_MASK_R_WMAC_TXCSI_AID1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R1(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_SHIFT_TSFT_CMP 20 +#define BIT_MASK_TSFT_CMP 0xf +#define BIT_TSFT_CMP(x) (((x) & BIT_MASK_TSFT_CMP) << BIT_SHIFT_TSFT_CMP) +#define BITS_TSFT_CMP (BIT_MASK_TSFT_CMP << BIT_SHIFT_TSFT_CMP) +#define BIT_CLEAR_TSFT_CMP(x) ((x) & (~BITS_TSFT_CMP)) +#define BIT_GET_TSFT_CMP(x) (((x) >> BIT_SHIFT_TSFT_CMP) & BIT_MASK_TSFT_CMP) +#define BIT_SET_TSFT_CMP(x, v) (BIT_CLEAR_TSFT_CMP(x) | BIT_TSFT_CMP(v)) -/* 2 REG_TX_CSI_RPT_PARAM_BW20 (Offset 0x06F4) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16 -#define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff -#define BIT_R_WMAC_BFINFO_20M_1(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1) -#define BIT_GET_R_WMAC_BFINFO_20M_1(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20) -#define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0 -#define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff -#define BIT_R_WMAC_BFINFO_20M_0(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0) -#define BIT_GET_R_WMAC_BFINFO_20M_0(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_TCR_EN_20MST BIT(19) +#define BIT_WMAC_DIS_SIGTA BIT(18) +#define BIT_WMAC_DIS_A2B0 BIT(17) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_SHIFT_TSFT_CMP_CCK 16 +#define BIT_MASK_TSFT_CMP_CCK 0xf +#define BIT_TSFT_CMP_CCK(x) \ + (((x) & BIT_MASK_TSFT_CMP_CCK) << BIT_SHIFT_TSFT_CMP_CCK) +#define BITS_TSFT_CMP_CCK (BIT_MASK_TSFT_CMP_CCK << BIT_SHIFT_TSFT_CMP_CCK) +#define BIT_CLEAR_TSFT_CMP_CCK(x) ((x) & (~BITS_TSFT_CMP_CCK)) +#define BIT_GET_TSFT_CMP_CCK(x) \ + (((x) >> BIT_SHIFT_TSFT_CMP_CCK) & BIT_MASK_TSFT_CMP_CCK) +#define BIT_SET_TSFT_CMP_CCK(x, v) \ + (BIT_CLEAR_TSFT_CMP_CCK(x) | BIT_TSFT_CMP_CCK(v)) -#define BIT_SHIFT_R_WMAC_BFINFO_40M_1 13 -#define BIT_MASK_R_WMAC_BFINFO_40M_1 0x7fff -#define BIT_R_WMAC_BFINFO_40M_1(x) (((x) & BIT_MASK_R_WMAC_BFINFO_40M_1) << BIT_SHIFT_R_WMAC_BFINFO_40M_1) -#define BIT_GET_R_WMAC_BFINFO_40M_1(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_1) & BIT_MASK_R_WMAC_BFINFO_40M_1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_BFINFO_40M_0 0 -#define BIT_MASK_R_WMAC_BFINFO_40M_0 0xfff -#define BIT_R_WMAC_BFINFO_40M_0(x) (((x) & BIT_MASK_R_WMAC_BFINFO_40M_0) << BIT_SHIFT_R_WMAC_BFINFO_40M_0) -#define BIT_GET_R_WMAC_BFINFO_40M_0(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_0) & BIT_MASK_R_WMAC_BFINFO_40M_0) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_MSK_SIGBCRC BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_TCR_ERRSTEN_3 BIT(15) +#define BIT_WMAC_TCR_ERRSTEN_2 BIT(14) +#define BIT_WMAC_TCR_ERRSTEN_1 BIT(13) +#define BIT_WMAC_TCR_ERRSTEN_0 BIT(12) +#define BIT_WMAC_TCR_TXSK_PERPKT BIT(11) -/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_WMAC_RESP_ANTCD 0 -#define BIT_MASK_WMAC_RESP_ANTCD 0xf -#define BIT_WMAC_RESP_ANTCD(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD) -#define BIT_GET_WMAC_RESP_ANTCD(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT__TXSK_PERPKT BIT(11) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) - - -/* 2 REG_TX_CSI_RPT_PARAM_BW80 (Offset 0x06FC) */ +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_ICV BIT(10) -#define BIT_SHIFT_R_WMAC_BFINFO_80M_1 16 -#define BIT_MASK_R_WMAC_BFINFO_80M_1 0xfff -#define BIT_R_WMAC_BFINFO_80M_1(x) (((x) & BIT_MASK_R_WMAC_BFINFO_80M_1) << BIT_SHIFT_R_WMAC_BFINFO_80M_1) -#define BIT_GET_R_WMAC_BFINFO_80M_1(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_1) & BIT_MASK_R_WMAC_BFINFO_80M_1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_BFINFO_80M_0 0 -#define BIT_MASK_R_WMAC_BFINFO_80M_0 0xfff -#define BIT_R_WMAC_BFINFO_80M_0(x) (((x) & BIT_MASK_R_WMAC_BFINFO_80M_0) << BIT_SHIFT_R_WMAC_BFINFO_80M_0) -#define BIT_GET_R_WMAC_BFINFO_80M_0(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_0) & BIT_MASK_R_WMAC_BFINFO_80M_0) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_CFEND_FORMAT BIT(9) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_CFENDFORM BIT(9) -/* 2 REG_MACID1 (Offset 0x0700) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MACID1 0 -#define BIT_MASK_MACID1 0xffffffffffffL -#define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1) -#define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_CRC BIT(8) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_PWRBIT_OW_EN BIT(7) -/* 2 REG_MACID1 (Offset 0x0700) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_MACID1_0 0 -#define BIT_MASK_MACID1_0 0xffffffffL -#define BIT_MACID1_0(x) (((x) & BIT_MASK_MACID1_0) << BIT_SHIFT_MACID1_0) -#define BIT_GET_MACID1_0(x) (((x) >> BIT_SHIFT_MACID1_0) & BIT_MASK_MACID1_0) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_PWRMGT_CTL BIT(7) -/* 2 REG_MACID1_1 (Offset 0x0704) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MACID1_1 0 -#define BIT_MASK_MACID1_1 0xffff -#define BIT_MACID1_1(x) (((x) & BIT_MASK_MACID1_1) << BIT_SHIFT_MACID1_1) -#define BIT_GET_MACID1_1(x) (((x) >> BIT_SHIFT_MACID1_1) & BIT_MASK_MACID1_1) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_TCRPWRMGT_HWDATA_EN BIT(7) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_PWR_ST BIT(6) -/* 2 REG_BSSID1 (Offset 0x0708) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_BSSID1 0 -#define BIT_MASK_BSSID1 0xffffffffffffL -#define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1) -#define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_PWRMGT_VAL BIT(6) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_TCR_UPD_TIMIE BIT(5) -/* 2 REG_BSSID1 (Offset 0x0708) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_BSSID1_0 0 -#define BIT_MASK_BSSID1_0 0xffffffffL -#define BIT_BSSID1_0(x) (((x) & BIT_MASK_BSSID1_0) << BIT_SHIFT_BSSID1_0) -#define BIT_GET_BSSID1_0(x) (((x) >> BIT_SHIFT_BSSID1_0) & BIT_MASK_BSSID1_0) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_UPD_TIMIE BIT(5) -/* 2 REG_BSSID1_1 (Offset 0x070C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BSSID1_1 0 -#define BIT_MASK_BSSID1_1 0xffff -#define BIT_BSSID1_1(x) (((x) & BIT_MASK_BSSID1_1) << BIT_SHIFT_BSSID1_1) -#define BIT_GET_BSSID1_1(x) (((x) >> BIT_SHIFT_BSSID1_1) & BIT_MASK_BSSID1_1) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_TCR_UPD_HGQMD BIT(4) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_UPD_HGQMD BIT(4) -/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DTIM_CNT1 24 -#define BIT_MASK_DTIM_CNT1 0xff -#define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1) -#define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_VHTSIGA1_TXPS BIT(3) -#define BIT_SHIFT_DTIM_PERIOD1 16 -#define BIT_MASK_DTIM_PERIOD1 0xff -#define BIT_DTIM_PERIOD1(x) (((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1) -#define BIT_GET_DTIM_PERIOD1(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1) +#endif -#define BIT_DTIM1 BIT(15) -#define BIT_TIM1 BIT(14) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PS_AID_1 0 -#define BIT_MASK_PS_AID_1 0x7ff -#define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1) -#define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_PAD_SEL BIT(2) +#define BIT_DIS_GCLK BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_TSFRST BIT(0) -/* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RD_BF_SEL 29 -#define BIT_MASK_RD_BF_SEL 0x7 -#define BIT_RD_BF_SEL(x) (((x) & BIT_MASK_RD_BF_SEL) << BIT_SHIFT_RD_BF_SEL) -#define BIT_GET_RD_BF_SEL(x) (((x) >> BIT_SHIFT_RD_BF_SEL) & BIT_MASK_RD_BF_SEL) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_WMAC_TCRPWRMGT_HWACT_EN BIT(0) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TCR (Offset 0x0604) */ +#define BIT_R_WMAC_TCR_LSIG BIT(0) -/* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */ +#endif -#define BIT_TXUSER_ID1 BIT(25) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_AID1 16 -#define BIT_MASK_AID1 0x1ff -#define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1) -#define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1) +/* 2 REG_RCR (Offset 0x0608) */ -#define BIT_TXUSER_ID0 BIT(9) +#define BIT_APP_FCS BIT(31) +#define BIT_APP_MIC BIT(30) +#define BIT_APP_ICV BIT(29) +#define BIT_APP_PHYSTS BIT(28) +#define BIT_APP_BASSN BIT(27) -#define BIT_SHIFT_AID0 0 -#define BIT_MASK_AID0 0x1ff -#define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0) -#define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_VHT_DACK BIT(26) -#define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24 -#define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff -#define BIT_NDP_RX_STANDBY_TIMER(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER) << BIT_SHIFT_NDP_RX_STANDBY_TIMER) -#define BIT_GET_NDP_RX_STANDBY_TIMER(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) & BIT_MASK_NDP_RX_STANDBY_TIMER) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_CSI_RPT_OFFSET_HT 16 -#define BIT_MASK_CSI_RPT_OFFSET_HT 0xff -#define BIT_CSI_RPT_OFFSET_HT(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT) -#define BIT_GET_CSI_RPT_OFFSET_HT(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_TCPOFLD_EN BIT(25) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_ENMBID BIT(24) -/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_CSI_RPT_OFFSET_VHT 8 -#define BIT_MASK_CSI_RPT_OFFSET_VHT 0xff -#define BIT_CSI_RPT_OFFSET_VHT(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT) << BIT_SHIFT_CSI_RPT_OFFSET_VHT) -#define BIT_GET_CSI_RPT_OFFSET_VHT(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT) & BIT_MASK_CSI_RPT_OFFSET_VHT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_ENADDRCAM BIT(24) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_LSIGEN BIT(23) +#define BIT_MFBEN BIT(22) +#define BIT_DISCHKPPDLLEN BIT(21) +#define BIT_PKTCTL_DLEN BIT(20) -/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8 -#define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff -#define BIT_R_WMAC_VHT_CATEGORY(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY) -#define BIT_GET_R_WMAC_VHT_CATEGORY(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_DISGCLK BIT(19) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +/* 2 REG_RCR (Offset 0x0608) */ -#define BIT_R_WMAC_USE_NSTS BIT(7) -#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6) -#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5) -#define BIT_R_WMAC_BFPARAM_SEL BIT(4) -#define BIT_R_WMAC_CSISEQ_SEL BIT(3) -#define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2) -#define BIT_R_WMAC_HT_NDPA_EN BIT(1) -#define BIT_R_WMAC_VHT_NDPA_EN BIT(0) +#define BIT_TIM_PARSER_EN BIT(18) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_TIMPSR_EN BIT(18) -/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ +#endif -#define BIT_WRITE_ENABLE BIT(31) -#define BIT_WRITE_USERID BIT(12) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WRITE_BW 10 -#define BIT_MASK_WRITE_BW 0x3 -#define BIT_WRITE_BW(x) (((x) & BIT_MASK_WRITE_BW) << BIT_SHIFT_WRITE_BW) -#define BIT_GET_WRITE_BW(x) (((x) >> BIT_SHIFT_WRITE_BW) & BIT_MASK_WRITE_BW) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_BC_MD_EN BIT(17) -#define BIT_SHIFT_WRITE_CB 8 -#define BIT_MASK_WRITE_CB 0x3 -#define BIT_WRITE_CB(x) (((x) & BIT_MASK_WRITE_CB) << BIT_SHIFT_WRITE_CB) -#define BIT_GET_WRITE_CB(x) (((x) >> BIT_SHIFT_WRITE_CB) & BIT_MASK_WRITE_CB) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_WRITE_GROUPING 6 -#define BIT_MASK_WRITE_GROUPING 0x3 -#define BIT_WRITE_GROUPING(x) (((x) & BIT_MASK_WRITE_GROUPING) << BIT_SHIFT_WRITE_GROUPING) -#define BIT_GET_WRITE_GROUPING(x) (((x) >> BIT_SHIFT_WRITE_GROUPING) & BIT_MASK_WRITE_GROUPING) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_BCMDINT_EN BIT(17) -#define BIT_SHIFT_WRITE_NR 3 -#define BIT_MASK_WRITE_NR 0x7 -#define BIT_WRITE_NR(x) (((x) & BIT_MASK_WRITE_NR) << BIT_SHIFT_WRITE_NR) -#define BIT_GET_WRITE_NR(x) (((x) >> BIT_SHIFT_WRITE_NR) & BIT_MASK_WRITE_NR) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WRITE_NC 0 -#define BIT_MASK_WRITE_NC 0x7 -#define BIT_WRITE_NC(x) (((x) & BIT_MASK_WRITE_NC) << BIT_SHIFT_WRITE_NC) -#define BIT_GET_WRITE_NC(x) (((x) >> BIT_SHIFT_WRITE_NC) & BIT_MASK_WRITE_NC) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_UC_MD_EN BIT(16) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_UCMDINT_EN BIT(16) -/* 2 REG_NS_ARP_CTRL (Offset 0x0720) */ +#endif -#define BIT_R_WMAC_NSARP_RSPEN BIT(15) -#define BIT_R_WMAC_NSARP_RARP BIT(9) -#define BIT_R_WMAC_NSARP_RIPV6 BIT(8) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_NSARP_MODEN 6 -#define BIT_MASK_R_WMAC_NSARP_MODEN 0x3 -#define BIT_R_WMAC_NSARP_MODEN(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN) -#define BIT_GET_R_WMAC_NSARP_MODEN(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_RXSK_PERPKT BIT(15) -#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4 -#define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3 -#define BIT_R_WMAC_NSARP_RSPFTP(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP) -#define BIT_GET_R_WMAC_NSARP_RSPFTP(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0 -#define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf -#define BIT_R_WMAC_NSARP_RSPSEC(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC) -#define BIT_GET_R_WMAC_NSARP_RSPSEC(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_HTC_LOC_CTRL BIT(14) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_HTCBFMC BIT(14) -/* 2 REG_NS_ARP_INFO (Offset 0x0724) */ +#endif -#define BIT_REQ_IS_MCNS BIT(23) -#define BIT_REQ_IS_UCNS BIT(22) -#define BIT_REQ_IS_USNS BIT(21) -#define BIT_REQ_IS_ARP BIT(20) -#define BIT_EXPRSP_MH_WITHQC BIT(19) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_EXPRSP_SECTYPE 16 -#define BIT_MASK_EXPRSP_SECTYPE 0x7 -#define BIT_EXPRSP_SECTYPE(x) (((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE) -#define BIT_GET_EXPRSP_SECTYPE(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_AMF BIT(13) -#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8 -#define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff -#define BIT_EXPRSP_CHKSM_7_TO_0(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) -#define BIT_GET_EXPRSP_CHKSM_7_TO_0(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0 -#define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff -#define BIT_EXPRSP_CHKSM_15_TO_8(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) -#define BIT_GET_EXPRSP_CHKSM_15_TO_8(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_CHK_PREVTCA2 BIT(13) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_ACK_WITH_CBSSID_DATA_OPTION BIT(13) -/* 2 REG_BEAMFORMING_INFO_NSARP_V1 (Offset 0x0728) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WMAC_ARPIP 0 -#define BIT_MASK_WMAC_ARPIP 0xffffffffL -#define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP) -#define BIT_GET_WMAC_ARPIP(x) (((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_ACF BIT(12) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_RPFM_CAM_ENABLE BIT(12) -/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BEAMFORMING_INFO 0 -#define BIT_MASK_BEAMFORMING_INFO 0xffffffffL -#define BIT_BEAMFORMING_INFO(x) (((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO) -#define BIT_GET_BEAMFORMING_INFO(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_ADF BIT(11) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_TA_BCN BIT(11) -/* 2 REG_IPV6 (Offset 0x0730) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_0(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_0(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_DISDECMYPKT BIT(10) -/* 2 REG_IPV6_1 (Offset 0x0734) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_1(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_1(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_DISDECNMYPKT BIT(10) -/* 2 REG_IPV6_2 (Offset 0x0738) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_2(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_2(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_AICV BIT(9) +#define BIT_ACRC32 BIT(8) -/* 2 REG_IPV6_3 (Offset 0x073C) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3 0 -#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_3(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_3(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_CBSSID_BCN BIT(7) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_CBSSID_MGNT BIT(7) -/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4 -#define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf -#define BIT_R_WMAC_CTX_SUBTYPE(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE) -#define BIT_GET_R_WMAC_CTX_SUBTYPE(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE) +/* 2 REG_RCR (Offset 0x0608) */ +#define BIT_CBSSID_DATA BIT(6) +#define BIT_APWRMGT BIT(5) +#define BIT_ADD3 BIT(4) +#define BIT_AB BIT(3) +#define BIT_AM BIT(2) +#define BIT_APM BIT(1) +#define BIT_AAP BIT(0) + +#define BIT_SHIFT_RXPKTLMT 0 +#define BIT_MASK_RXPKTLMT 0x3f +#define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT) +#define BITS_RXPKTLMT (BIT_MASK_RXPKTLMT << BIT_SHIFT_RXPKTLMT) +#define BIT_CLEAR_RXPKTLMT(x) ((x) & (~BITS_RXPKTLMT)) +#define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT) +#define BIT_SET_RXPKTLMT(x, v) (BIT_CLEAR_RXPKTLMT(x) | BIT_RXPKTLMT(v)) -#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0 -#define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf -#define BIT_R_WMAC_RTX_SUBTYPE(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE) -#define BIT_GET_R_WMAC_RTX_SUBTYPE(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE) +/* 2 REG_RX_DLK_TIME (Offset 0x060D) */ +#define BIT_SHIFT_RX_DLK_TIME 0 +#define BIT_MASK_RX_DLK_TIME 0xff +#define BIT_RX_DLK_TIME(x) \ + (((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME) +#define BITS_RX_DLK_TIME (BIT_MASK_RX_DLK_TIME << BIT_SHIFT_RX_DLK_TIME) +#define BIT_CLEAR_RX_DLK_TIME(x) ((x) & (~BITS_RX_DLK_TIME)) +#define BIT_GET_RX_DLK_TIME(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME) +#define BIT_SET_RX_DLK_TIME(x, v) \ + (BIT_CLEAR_RX_DLK_TIME(x) | BIT_RX_DLK_TIME(v)) -/* 2 REG_BT_COEX_V2 (Offset 0x0762) */ +#endif -#define BIT_GNT_BT_POLARITY BIT(12) -#define BIT_GNT_BT_BYPASS_PRIORITY BIT(8) +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_TIMER 0 -#define BIT_MASK_TIMER 0xff -#define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER) -#define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER) +/* 2 REG_SDIO_RXINT_LEN_TH (Offset 0x1025060E) */ +#define BIT_SHIFT_SDIO_RXINT_LEN_TH 0 +#define BIT_MASK_SDIO_RXINT_LEN_TH 0xff +#define BIT_SDIO_RXINT_LEN_TH(x) \ + (((x) & BIT_MASK_SDIO_RXINT_LEN_TH) << BIT_SHIFT_SDIO_RXINT_LEN_TH) +#define BITS_SDIO_RXINT_LEN_TH \ + (BIT_MASK_SDIO_RXINT_LEN_TH << BIT_SHIFT_SDIO_RXINT_LEN_TH) +#define BIT_CLEAR_SDIO_RXINT_LEN_TH(x) ((x) & (~BITS_SDIO_RXINT_LEN_TH)) +#define BIT_GET_SDIO_RXINT_LEN_TH(x) \ + (((x) >> BIT_SHIFT_SDIO_RXINT_LEN_TH) & BIT_MASK_SDIO_RXINT_LEN_TH) +#define BIT_SET_SDIO_RXINT_LEN_TH(x, v) \ + (BIT_CLEAR_SDIO_RXINT_LEN_TH(x) | BIT_SDIO_RXINT_LEN_TH(v)) -/* 2 REG_BT_COEX (Offset 0x0764) */ +#endif -#define BIT_R_GNT_BT_RFC_SW BIT(12) -#define BIT_R_GNT_BT_RFC_SW_EN BIT(11) -#define BIT_R_GNT_BT_BB_SW BIT(10) -#define BIT_R_GNT_BT_BB_SW_EN BIT(9) -#define BIT_R_BT_CNT_THREN BIT(8) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_R_BT_CNT_THR 0 -#define BIT_MASK_R_BT_CNT_THR 0xff -#define BIT_R_BT_CNT_THR(x) (((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR) -#define BIT_GET_R_BT_CNT_THR(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR) +/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#define BIT_APP_PHYSTS_PER_SUBMPDU BIT(7) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#define BIT_PHYSTS_PER_PKT_MODE BIT(7) -/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ +#endif -#define BIT_WLRX_TER_BY_CTL BIT(43) -#define BIT_WLRX_TER_BY_AD BIT(42) -#define BIT_ANT_DIVERSITY_SEL BIT(41) -#define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40) -#define BIT_WLACT_LOW_GNTWL_EN BIT(34) -#define BIT_WLACT_HIGH_GNTBT_EN BIT(33) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#define BIT_APP_MH_SHIFT_VAL BIT(6) +#define BIT_WMAC_ENSHIFT BIT(5) -#if (HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ +/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ -#define BIT_NAV_UPPER_V1 BIT(32) +#define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2 +#define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f +#define BIT_BITMAP_SSNBK_COUNTER(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER) +#define BITS_BITMAP_SSNBK_COUNTER \ + (BIT_MASK_BITMAP_SSNBK_COUNTER << BIT_SHIFT_BITMAP_SSNBK_COUNTER) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) ((x) & (~BITS_BITMAP_SSNBK_COUNTER)) +#define BIT_GET_BITMAP_SSNBK_COUNTER(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER) +#define BIT_SET_BITMAP_SSNBK_COUNTER(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) | BIT_BITMAP_SSNBK_COUNTER(v)) + +#define BIT_BITMAP_EN BIT(1) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#define BIT_SHIFT_DRVINFO_SZ 0 +#define BIT_MASK_DRVINFO_SZ 0xff +#define BIT_DRVINFO_SZ(x) (((x) & BIT_MASK_DRVINFO_SZ) << BIT_SHIFT_DRVINFO_SZ) +#define BITS_DRVINFO_SZ (BIT_MASK_DRVINFO_SZ << BIT_SHIFT_DRVINFO_SZ) +#define BIT_CLEAR_DRVINFO_SZ(x) ((x) & (~BITS_DRVINFO_SZ)) +#define BIT_GET_DRVINFO_SZ(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ) & BIT_MASK_DRVINFO_SZ) +#define BIT_SET_DRVINFO_SZ(x, v) (BIT_CLEAR_DRVINFO_SZ(x) | BIT_DRVINFO_SZ(v)) -/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXMYRTS_NAV_V1 8 -#define BIT_MASK_RXMYRTS_NAV_V1 0xff -#define BIT_RXMYRTS_NAV_V1(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1) -#define BIT_GET_RXMYRTS_NAV_V1(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1) +/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ +#define BIT_SHIFT_DRVINFO_SZ_V1 0 +#define BIT_MASK_DRVINFO_SZ_V1 0xf +#define BIT_DRVINFO_SZ_V1(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1) +#define BITS_DRVINFO_SZ_V1 (BIT_MASK_DRVINFO_SZ_V1 << BIT_SHIFT_DRVINFO_SZ_V1) +#define BIT_CLEAR_DRVINFO_SZ_V1(x) ((x) & (~BITS_DRVINFO_SZ_V1)) +#define BIT_GET_DRVINFO_SZ_V1(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1) +#define BIT_SET_DRVINFO_SZ_V1(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1(x) | BIT_DRVINFO_SZ_V1(v)) -#define BIT_SHIFT_RTSRST_V1 0 -#define BIT_MASK_RTSRST_V1 0xff -#define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1) -#define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_MACID (Offset 0x0610) */ +#define BIT_SHIFT_MACID 0 +#define BIT_MASK_MACID 0xffffffffffffL +#define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID) +#define BITS_MACID (BIT_MASK_MACID << BIT_SHIFT_MACID) +#define BIT_CLEAR_MACID(x) ((x) & (~BITS_MACID)) +#define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID) +#define BIT_SET_MACID(x, v) (BIT_CLEAR_MACID(x) | BIT_MACID(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_WLAN_ACT_MASK_CTRL_1 (Offset 0x076C) */ +/* 2 REG_MACID (Offset 0x0610) */ -#define BIT_WLRX_TER_BY_CTL_1 BIT(11) -#define BIT_WLRX_TER_BY_AD_1 BIT(10) -#define BIT_ANT_DIVERSITY_SEL_1 BIT(9) -#define BIT_ANTSEL_FOR_BT_CTRL_EN_1 BIT(8) -#define BIT_WLACT_LOW_GNTWL_EN_1 BIT(2) -#define BIT_WLACT_HIGH_GNTBT_EN_1 BIT(1) -#define BIT_NAV_UPPER_1_V1 BIT(0) +#define BIT_SHIFT_MACID_V1 0 +#define BIT_MASK_MACID_V1 0xffffffffL +#define BIT_MACID_V1(x) (((x) & BIT_MASK_MACID_V1) << BIT_SHIFT_MACID_V1) +#define BITS_MACID_V1 (BIT_MASK_MACID_V1 << BIT_SHIFT_MACID_V1) +#define BIT_CLEAR_MACID_V1(x) ((x) & (~BITS_MACID_V1)) +#define BIT_GET_MACID_V1(x) (((x) >> BIT_SHIFT_MACID_V1) & BIT_MASK_MACID_V1) +#define BIT_SET_MACID_V1(x, v) (BIT_CLEAR_MACID_V1(x) | BIT_MACID_V1(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MACID_H (Offset 0x0614) */ +#define BIT_SHIFT_MACID_H 0 +#define BIT_MASK_MACID_H 0xffff +#define BIT_MACID_H(x) (((x) & BIT_MASK_MACID_H) << BIT_SHIFT_MACID_H) +#define BITS_MACID_H (BIT_MASK_MACID_H << BIT_SHIFT_MACID_H) +#define BIT_CLEAR_MACID_H(x) ((x) & (~BITS_MACID_H)) +#define BIT_GET_MACID_H(x) (((x) >> BIT_SHIFT_MACID_H) & BIT_MASK_MACID_H) +#define BIT_SET_MACID_H(x, v) (BIT_CLEAR_MACID_H(x) | BIT_MACID_H(v)) -/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL (Offset 0x076E) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BT_STAT_DELAY 12 -#define BIT_MASK_BT_STAT_DELAY 0xf -#define BIT_BT_STAT_DELAY(x) (((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY) -#define BIT_GET_BT_STAT_DELAY(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY) +/* 2 REG_MACID_H (Offset 0x0614) */ +#define BIT_SHIFT_MACID_H_V1 0 +#define BIT_MASK_MACID_H_V1 0xffff +#define BIT_MACID_H_V1(x) (((x) & BIT_MASK_MACID_H_V1) << BIT_SHIFT_MACID_H_V1) +#define BITS_MACID_H_V1 (BIT_MASK_MACID_H_V1 << BIT_SHIFT_MACID_H_V1) +#define BIT_CLEAR_MACID_H_V1(x) ((x) & (~BITS_MACID_H_V1)) +#define BIT_GET_MACID_H_V1(x) \ + (((x) >> BIT_SHIFT_MACID_H_V1) & BIT_MASK_MACID_H_V1) +#define BIT_SET_MACID_H_V1(x, v) (BIT_CLEAR_MACID_H_V1(x) | BIT_MACID_H_V1(v)) -#define BIT_SHIFT_BT_TRX_INIT_DETECT 8 -#define BIT_MASK_BT_TRX_INIT_DETECT 0xf -#define BIT_BT_TRX_INIT_DETECT(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT) -#define BIT_GET_BT_TRX_INIT_DETECT(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT) +#define BIT_SHIFT_BSSID_H_V1 0 +#define BIT_MASK_BSSID_H_V1 0xffff +#define BIT_BSSID_H_V1(x) (((x) & BIT_MASK_BSSID_H_V1) << BIT_SHIFT_BSSID_H_V1) +#define BITS_BSSID_H_V1 (BIT_MASK_BSSID_H_V1 << BIT_SHIFT_BSSID_H_V1) +#define BIT_CLEAR_BSSID_H_V1(x) ((x) & (~BITS_BSSID_H_V1)) +#define BIT_GET_BSSID_H_V1(x) \ + (((x) >> BIT_SHIFT_BSSID_H_V1) & BIT_MASK_BSSID_H_V1) +#define BIT_SET_BSSID_H_V1(x, v) (BIT_CLEAR_BSSID_H_V1(x) | BIT_BSSID_H_V1(v)) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BT_PRI_DETECT_TO 4 -#define BIT_MASK_BT_PRI_DETECT_TO 0xf -#define BIT_BT_PRI_DETECT_TO(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO) -#define BIT_GET_BT_PRI_DETECT_TO(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO) +/* 2 REG_BSSID (Offset 0x0618) */ -#define BIT_R_GRANTALL_WLMASK BIT(3) -#define BIT_STATIS_BT_EN BIT(2) -#define BIT_WL_ACT_MASK_ENABLE BIT(1) -#define BIT_ENHANCED_BT BIT(0) +#define BIT_SHIFT_BSSID 0 +#define BIT_MASK_BSSID 0xffffffffffffL +#define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID) +#define BITS_BSSID (BIT_MASK_BSSID << BIT_SHIFT_BSSID) +#define BIT_CLEAR_BSSID(x) ((x) & (~BITS_BSSID)) +#define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID) +#define BIT_SET_BSSID(x, v) (BIT_CLEAR_BSSID(x) | BIT_BSSID(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BSSID (Offset 0x0618) */ +#define BIT_SHIFT_BSSID_V1 0 +#define BIT_MASK_BSSID_V1 0xffffffffL +#define BIT_BSSID_V1(x) (((x) & BIT_MASK_BSSID_V1) << BIT_SHIFT_BSSID_V1) +#define BITS_BSSID_V1 (BIT_MASK_BSSID_V1 << BIT_SHIFT_BSSID_V1) +#define BIT_CLEAR_BSSID_V1(x) ((x) & (~BITS_BSSID_V1)) +#define BIT_GET_BSSID_V1(x) (((x) >> BIT_SHIFT_BSSID_V1) & BIT_MASK_BSSID_V1) +#define BIT_SET_BSSID_V1(x, v) (BIT_CLEAR_BSSID_V1(x) | BIT_BSSID_V1(v)) -/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH) -#define BIT_MASK_STATIS_BT_LO_RX 0xffff -#define BIT_STATIS_BT_LO_RX(x) (((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX) -#define BIT_GET_STATIS_BT_LO_RX(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX) +/* 2 REG_BSSID_H (Offset 0x061C) */ +#define BIT_SHIFT_BSSID_H 0 +#define BIT_MASK_BSSID_H 0xffff +#define BIT_BSSID_H(x) (((x) & BIT_MASK_BSSID_H) << BIT_SHIFT_BSSID_H) +#define BITS_BSSID_H (BIT_MASK_BSSID_H << BIT_SHIFT_BSSID_H) +#define BIT_CLEAR_BSSID_H(x) ((x) & (~BITS_BSSID_H)) +#define BIT_GET_BSSID_H(x) (((x) >> BIT_SHIFT_BSSID_H) & BIT_MASK_BSSID_H) +#define BIT_SET_BSSID_H(x, v) (BIT_CLEAR_BSSID_H(x) | BIT_BSSID_H(v)) -#define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH) -#define BIT_MASK_STATIS_BT_LO_TX 0xffff -#define BIT_STATIS_BT_LO_TX(x) (((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX) -#define BIT_GET_STATIS_BT_LO_TX(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_MAR (Offset 0x0620) */ +#define BIT_SHIFT_MAR 0 +#define BIT_MASK_MAR 0xffffffffffffffffL +#define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR) +#define BITS_MAR (BIT_MASK_MAR << BIT_SHIFT_MAR) +#define BIT_CLEAR_MAR(x) ((x) & (~BITS_MAR)) +#define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR) +#define BIT_SET_MAR(x, v) (BIT_CLEAR_MAR(x) | BIT_MAR(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ +/* 2 REG_MAR (Offset 0x0620) */ +#define BIT_SHIFT_MAR_V1 0 +#define BIT_MASK_MAR_V1 0xffffffffL +#define BIT_MAR_V1(x) (((x) & BIT_MASK_MAR_V1) << BIT_SHIFT_MAR_V1) +#define BITS_MAR_V1 (BIT_MASK_MAR_V1 << BIT_SHIFT_MAR_V1) +#define BIT_CLEAR_MAR_V1(x) ((x) & (~BITS_MAR_V1)) +#define BIT_GET_MAR_V1(x) (((x) >> BIT_SHIFT_MAR_V1) & BIT_MASK_MAR_V1) +#define BIT_SET_MAR_V1(x, v) (BIT_CLEAR_MAR_V1(x) | BIT_MAR_V1(v)) -#define BIT_SHIFT_STATIS_BT_HI_RX 16 -#define BIT_MASK_STATIS_BT_HI_RX 0xffff -#define BIT_STATIS_BT_HI_RX(x) (((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX) -#define BIT_GET_STATIS_BT_HI_RX(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_STATIS_BT_HI_TX 0 -#define BIT_MASK_STATIS_BT_HI_TX 0xffff -#define BIT_STATIS_BT_HI_TX(x) (((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX) -#define BIT_GET_STATIS_BT_HI_TX(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX) +/* 2 REG_MAR_H (Offset 0x0624) */ +#define BIT_SHIFT_MAR_H 0 +#define BIT_MASK_MAR_H 0xffffffffL +#define BIT_MAR_H(x) (((x) & BIT_MASK_MAR_H) << BIT_SHIFT_MAR_H) +#define BITS_MAR_H (BIT_MASK_MAR_H << BIT_SHIFT_MAR_H) +#define BIT_CLEAR_MAR_H(x) ((x) & (~BITS_MAR_H)) +#define BIT_GET_MAR_H(x) (((x) >> BIT_SHIFT_MAR_H) & BIT_MASK_MAR_H) +#define BIT_SET_MAR_H(x, v) (BIT_CLEAR_MAR_H(x) | BIT_MAR_H(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_MAR_H (Offset 0x0624) */ +#define BIT_SHIFT_MAR_H_V1 0 +#define BIT_MASK_MAR_H_V1 0xffffffffL +#define BIT_MAR_H_V1(x) (((x) & BIT_MASK_MAR_H_V1) << BIT_SHIFT_MAR_H_V1) +#define BITS_MAR_H_V1 (BIT_MASK_MAR_H_V1 << BIT_SHIFT_MAR_H_V1) +#define BIT_CLEAR_MAR_H_V1(x) ((x) & (~BITS_MAR_H_V1)) +#define BIT_GET_MAR_H_V1(x) (((x) >> BIT_SHIFT_MAR_H_V1) & BIT_MASK_MAR_H_V1) +#define BIT_SET_MAR_H_V1(x, v) (BIT_CLEAR_MAR_H_V1(x) | BIT_MAR_H_V1(v)) -/* 2 REG_BT_ACT_STATISTICS_1 (Offset 0x0774) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_STATIS_BT_LO_RX_1 16 -#define BIT_MASK_STATIS_BT_LO_RX_1 0xffff -#define BIT_STATIS_BT_LO_RX_1(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_1) << BIT_SHIFT_STATIS_BT_LO_RX_1) -#define BIT_GET_STATIS_BT_LO_RX_1(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1) & BIT_MASK_STATIS_BT_LO_RX_1) +/* 2 REG_MBIDCAMCFG_1 (Offset 0x0628) */ +#define BIT_MBIDCAM_POLL BIT(31) +#define BIT_MBIDCAM_WT_EN BIT(30) +#define BIT_LSIC_TXOP_EN BIT(17) -#define BIT_SHIFT_STATIS_BT_LO_TX_1 0 -#define BIT_MASK_STATIS_BT_LO_TX_1 0xffff -#define BIT_STATIS_BT_LO_TX_1(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_1) << BIT_SHIFT_STATIS_BT_LO_TX_1) -#define BIT_GET_STATIS_BT_LO_TX_1(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1) & BIT_MASK_STATIS_BT_LO_TX_1) +#define BIT_SHIFT_MBIDCAM_RWDATA_L 0 +#define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL +#define BIT_MBIDCAM_RWDATA_L(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L) +#define BITS_MBIDCAM_RWDATA_L \ + (BIT_MASK_MBIDCAM_RWDATA_L << BIT_SHIFT_MBIDCAM_RWDATA_L) +#define BIT_CLEAR_MBIDCAM_RWDATA_L(x) ((x) & (~BITS_MBIDCAM_RWDATA_L)) +#define BIT_GET_MBIDCAM_RWDATA_L(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L) +#define BIT_SET_MBIDCAM_RWDATA_L(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_L(x) | BIT_MBIDCAM_RWDATA_L(v)) +#define BIT_SHIFT_MBIDCAM_RWDATA_H 0 +#define BIT_MASK_MBIDCAM_RWDATA_H 0xffff +#define BIT_MBIDCAM_RWDATA_H(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H) +#define BITS_MBIDCAM_RWDATA_H \ + (BIT_MASK_MBIDCAM_RWDATA_H << BIT_SHIFT_MBIDCAM_RWDATA_H) +#define BIT_CLEAR_MBIDCAM_RWDATA_H(x) ((x) & (~BITS_MBIDCAM_RWDATA_H)) +#define BIT_GET_MBIDCAM_RWDATA_H(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H) +#define BIT_SET_MBIDCAM_RWDATA_H(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_H(x) | BIT_MBIDCAM_RWDATA_H(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MBIDCAM_CFG (Offset 0x062C) */ +#define BIT_MBIDCAM_RST_V1 BIT(29) -/* 2 REG_BT_STATISTICS_CONTROL_REGISTER (Offset 0x0778) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ -#define BIT_SHIFT_R_BT_CMD_RPT 16 -#define BIT_MASK_R_BT_CMD_RPT 0xffff -#define BIT_R_BT_CMD_RPT(x) (((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT) -#define BIT_GET_R_BT_CMD_RPT(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT) +#define BIT_SHIFT_MBIDCAM_ADDR_V1 24 +#define BIT_MASK_MBIDCAM_ADDR_V1 0x3f +#define BIT_MBIDCAM_ADDR_V1(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_V1) << BIT_SHIFT_MBIDCAM_ADDR_V1) +#define BITS_MBIDCAM_ADDR_V1 \ + (BIT_MASK_MBIDCAM_ADDR_V1 << BIT_SHIFT_MBIDCAM_ADDR_V1) +#define BIT_CLEAR_MBIDCAM_ADDR_V1(x) ((x) & (~BITS_MBIDCAM_ADDR_V1)) +#define BIT_GET_MBIDCAM_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1) & BIT_MASK_MBIDCAM_ADDR_V1) +#define BIT_SET_MBIDCAM_ADDR_V1(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_V1(x) | BIT_MBIDCAM_ADDR_V1(v)) +#endif -#define BIT_SHIFT_R_RPT_FROM_BT 8 -#define BIT_MASK_R_RPT_FROM_BT 0xff -#define BIT_R_RPT_FROM_BT(x) (((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT) -#define BIT_GET_R_RPT_FROM_BT(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT) +#if (HALMAC_8198F_SUPPORT) +/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ -#define BIT_SHIFT_BT_HID_ISR_SET 6 -#define BIT_MASK_BT_HID_ISR_SET 0x3 -#define BIT_BT_HID_ISR_SET(x) (((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET) -#define BIT_GET_BT_HID_ISR_SET(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET) +#define BIT_SHIFT_MBIDCAM_ADDR_V2 23 +#define BIT_MASK_MBIDCAM_ADDR_V2 0x7f +#define BIT_MBIDCAM_ADDR_V2(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_V2) << BIT_SHIFT_MBIDCAM_ADDR_V2) +#define BITS_MBIDCAM_ADDR_V2 \ + (BIT_MASK_MBIDCAM_ADDR_V2 << BIT_SHIFT_MBIDCAM_ADDR_V2) +#define BIT_CLEAR_MBIDCAM_ADDR_V2(x) ((x) & (~BITS_MBIDCAM_ADDR_V2)) +#define BIT_GET_MBIDCAM_ADDR_V2(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V2) & BIT_MASK_MBIDCAM_ADDR_V2) +#define BIT_SET_MBIDCAM_ADDR_V2(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_V2(x) | BIT_MBIDCAM_ADDR_V2(v)) -#define BIT_TDMA_BT_START_NOTIFY BIT(5) -#define BIT_ENABLE_TDMA_FW_MODE BIT(4) -#define BIT_ENABLE_PTA_TDMA_MODE BIT(3) -#define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) -#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) -#define BIT_RTK_BT_ENABLE BIT(0) +#define BIT_MBIDCAM_RST BIT(19) +#define BIT_MBIDCAM_VALID_V1 BIT(18) -/* 2 REG_BT_STATUS_REPORT_REGISTER (Offset 0x077C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_BT_PROFILE 24 -#define BIT_MASK_BT_PROFILE 0xff -#define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE) -#define BIT_GET_BT_PROFILE(x) (((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE) +/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ +#define BIT_REPEAT_MODE_EN BIT(16) -#define BIT_SHIFT_BT_POWER 16 -#define BIT_MASK_BT_POWER 0xff -#define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER) -#define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER) +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_BT_PREDECT_STATUS 8 -#define BIT_MASK_BT_PREDECT_STATUS 0xff -#define BIT_BT_PREDECT_STATUS(x) (((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS) -#define BIT_GET_BT_PREDECT_STATUS(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS) +/* 2 REG_WMAC_DEBUG_SEL (Offset 0x062C) */ +#define BIT_SHIFT_WMAC_ARB_DBG_SEL 3 +#define BIT_MASK_WMAC_ARB_DBG_SEL 0x3 +#define BIT_WMAC_ARB_DBG_SEL(x) \ + (((x) & BIT_MASK_WMAC_ARB_DBG_SEL) << BIT_SHIFT_WMAC_ARB_DBG_SEL) +#define BITS_WMAC_ARB_DBG_SEL \ + (BIT_MASK_WMAC_ARB_DBG_SEL << BIT_SHIFT_WMAC_ARB_DBG_SEL) +#define BIT_CLEAR_WMAC_ARB_DBG_SEL(x) ((x) & (~BITS_WMAC_ARB_DBG_SEL)) +#define BIT_GET_WMAC_ARB_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_DBG_SEL) & BIT_MASK_WMAC_ARB_DBG_SEL) +#define BIT_SET_WMAC_ARB_DBG_SEL(x, v) \ + (BIT_CLEAR_WMAC_ARB_DBG_SEL(x) | BIT_WMAC_ARB_DBG_SEL(v)) -#define BIT_SHIFT_BT_CMD_INFO 0 -#define BIT_MASK_BT_CMD_INFO 0xff -#define BIT_BT_CMD_INFO(x) (((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO) -#define BIT_GET_BT_CMD_INFO(x) (((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO) +#define BIT_WMAC_EXT_DBG_SEL BIT(2) +#define BIT_SHIFT_WMAC_MU_DBGSEL_V1 0 +#define BIT_MASK_WMAC_MU_DBGSEL_V1 0x3 +#define BIT_WMAC_MU_DBGSEL_V1(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL_V1) << BIT_SHIFT_WMAC_MU_DBGSEL_V1) +#define BITS_WMAC_MU_DBGSEL_V1 \ + (BIT_MASK_WMAC_MU_DBGSEL_V1 << BIT_SHIFT_WMAC_MU_DBGSEL_V1) +#define BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) ((x) & (~BITS_WMAC_MU_DBGSEL_V1)) +#define BIT_GET_WMAC_MU_DBGSEL_V1(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_V1) & BIT_MASK_WMAC_MU_DBGSEL_V1) +#define BIT_SET_WMAC_MU_DBGSEL_V1(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) | BIT_WMAC_MU_DBGSEL_V1(v)) -/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER (Offset 0x0780) */ +#endif -#define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31) -#define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30) -#define BIT_EN_BT_STSTUS_RPT BIT(29) -#define BIT_EN_BT_POWER BIT(28) -#define BIT_EN_BT_CHANNEL BIT(27) -#define BIT_EN_BT_SLOT_CHANGE BIT(26) -#define BIT_EN_BT_PROFILE_OR_HID BIT(25) -#define BIT_WLAN_RPT_NOTIFY BIT(24) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WLAN_RPT_DATA 16 -#define BIT_MASK_WLAN_RPT_DATA 0xff -#define BIT_WLAN_RPT_DATA(x) (((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA) -#define BIT_GET_WLAN_RPT_DATA(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA) +/* 2 REG_MCU_TEST_1 (Offset 0x0630) */ +#define BIT_SHIFT_MCU_RSVD 0 +#define BIT_MASK_MCU_RSVD 0xffffffffL +#define BIT_MCU_RSVD(x) (((x) & BIT_MASK_MCU_RSVD) << BIT_SHIFT_MCU_RSVD) +#define BITS_MCU_RSVD (BIT_MASK_MCU_RSVD << BIT_SHIFT_MCU_RSVD) +#define BIT_CLEAR_MCU_RSVD(x) ((x) & (~BITS_MCU_RSVD)) +#define BIT_GET_MCU_RSVD(x) (((x) >> BIT_SHIFT_MCU_RSVD) & BIT_MASK_MCU_RSVD) +#define BIT_SET_MCU_RSVD(x, v) (BIT_CLEAR_MCU_RSVD(x) | BIT_MCU_RSVD(v)) -#define BIT_SHIFT_CMD_ID 8 -#define BIT_MASK_CMD_ID 0xff -#define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID) -#define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BT_DATA 0 -#define BIT_MASK_BT_DATA 0xff -#define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA) -#define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA) +/* 2 REG_WMAC_TCR_TSFT_OFS (Offset 0x0630) */ +#define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0 +#define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff +#define BIT_WMAC_TCR_TSFT_OFS(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS) +#define BITS_WMAC_TCR_TSFT_OFS \ + (BIT_MASK_WMAC_TCR_TSFT_OFS << BIT_SHIFT_WMAC_TCR_TSFT_OFS) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) ((x) & (~BITS_WMAC_TCR_TSFT_OFS)) +#define BIT_GET_WMAC_TCR_TSFT_OFS(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS) +#define BIT_SET_WMAC_TCR_TSFT_OFS(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) | BIT_WMAC_TCR_TSFT_OFS(v)) -/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WLAN_RPT_TO 0 -#define BIT_MASK_WLAN_RPT_TO 0xff -#define BIT_WLAN_RPT_TO(x) (((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO) -#define BIT_GET_WLAN_RPT_TO(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO) +/* 2 REG_UDF_THSD (Offset 0x0632) */ +#define BIT_UDF_THSD_V1 BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_UDF_THSD (Offset 0x0632) */ +#define BIT_SHIFT_UDF_THSD 0 +#define BIT_MASK_UDF_THSD 0xff +#define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD) +#define BITS_UDF_THSD (BIT_MASK_UDF_THSD << BIT_SHIFT_UDF_THSD) +#define BIT_CLEAR_UDF_THSD(x) ((x) & (~BITS_UDF_THSD)) +#define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD) +#define BIT_SET_UDF_THSD(x, v) (BIT_CLEAR_UDF_THSD(x) | BIT_UDF_THSD(v)) -/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_ISOLATION_CHK 1 -#define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL -#define BIT_ISOLATION_CHK(x) (((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK) -#define BIT_GET_ISOLATION_CHK(x) (((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK) +/* 2 REG_UDF_THSD (Offset 0x0632) */ +#define BIT_SHIFT_UDF_THSD_VALUE 0 +#define BIT_MASK_UDF_THSD_VALUE 0x7f +#define BIT_UDF_THSD_VALUE(x) \ + (((x) & BIT_MASK_UDF_THSD_VALUE) << BIT_SHIFT_UDF_THSD_VALUE) +#define BITS_UDF_THSD_VALUE \ + (BIT_MASK_UDF_THSD_VALUE << BIT_SHIFT_UDF_THSD_VALUE) +#define BIT_CLEAR_UDF_THSD_VALUE(x) ((x) & (~BITS_UDF_THSD_VALUE)) +#define BIT_GET_UDF_THSD_VALUE(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_VALUE) & BIT_MASK_UDF_THSD_VALUE) +#define BIT_SET_UDF_THSD_VALUE(x, v) \ + (BIT_CLEAR_UDF_THSD_VALUE(x) | BIT_UDF_THSD_VALUE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_ZLD_NUM (Offset 0x0633) */ +#define BIT_SHIFT_ZLD_NUM 0 +#define BIT_MASK_ZLD_NUM 0xff +#define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM) +#define BITS_ZLD_NUM (BIT_MASK_ZLD_NUM << BIT_SHIFT_ZLD_NUM) +#define BIT_CLEAR_ZLD_NUM(x) ((x) & (~BITS_ZLD_NUM)) +#define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM) +#define BIT_SET_ZLD_NUM(x, v) (BIT_CLEAR_ZLD_NUM(x) | BIT_ZLD_NUM(v)) -/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_MCU_TEST_2 (Offset 0x0634) */ -#define BIT_SHIFT_ISOLATION_CHK_0 1 -#define BIT_MASK_ISOLATION_CHK_0 0x7fffff -#define BIT_ISOLATION_CHK_0(x) (((x) & BIT_MASK_ISOLATION_CHK_0) << BIT_SHIFT_ISOLATION_CHK_0) -#define BIT_GET_ISOLATION_CHK_0(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_0) & BIT_MASK_ISOLATION_CHK_0) +#define BIT_SHIFT_MCU_RSVD_2 0 +#define BIT_MASK_MCU_RSVD_2 0xffffffffL +#define BIT_MCU_RSVD_2(x) (((x) & BIT_MASK_MCU_RSVD_2) << BIT_SHIFT_MCU_RSVD_2) +#define BITS_MCU_RSVD_2 (BIT_MASK_MCU_RSVD_2 << BIT_SHIFT_MCU_RSVD_2) +#define BIT_CLEAR_MCU_RSVD_2(x) ((x) & (~BITS_MCU_RSVD_2)) +#define BIT_GET_MCU_RSVD_2(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2) & BIT_MASK_MCU_RSVD_2) +#define BIT_SET_MCU_RSVD_2(x, v) (BIT_CLEAR_MCU_RSVD_2(x) | BIT_MCU_RSVD_2(v)) +#define BIT_SHIFT_WKFCAM_NUM 0 +#define BIT_MASK_WKFCAM_NUM 0x7f +#define BIT_WKFCAM_NUM(x) (((x) & BIT_MASK_WKFCAM_NUM) << BIT_SHIFT_WKFCAM_NUM) +#define BITS_WKFCAM_NUM (BIT_MASK_WKFCAM_NUM << BIT_SHIFT_WKFCAM_NUM) +#define BIT_CLEAR_WKFCAM_NUM(x) ((x) & (~BITS_WKFCAM_NUM)) +#define BIT_GET_WKFCAM_NUM(x) \ + (((x) >> BIT_SHIFT_WKFCAM_NUM) & BIT_MASK_WKFCAM_NUM) +#define BIT_SET_WKFCAM_NUM(x, v) (BIT_CLEAR_WKFCAM_NUM(x) | BIT_WKFCAM_NUM(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_STMP_THSD (Offset 0x0634) */ +#define BIT_SHIFT_STMP_THSD 0 +#define BIT_MASK_STMP_THSD 0xff +#define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD) +#define BITS_STMP_THSD (BIT_MASK_STMP_THSD << BIT_SHIFT_STMP_THSD) +#define BIT_CLEAR_STMP_THSD(x) ((x) & (~BITS_STMP_THSD)) +#define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD) +#define BIT_SET_STMP_THSD(x, v) (BIT_CLEAR_STMP_THSD(x) | BIT_STMP_THSD(v)) -/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ +/* 2 REG_WMAC_TXTIMEOUT (Offset 0x0635) */ -#define BIT_ISOLATION_EN BIT(0) +#define BIT_SHIFT_WMAC_TXTIMEOUT 0 +#define BIT_MASK_WMAC_TXTIMEOUT 0xff +#define BIT_WMAC_TXTIMEOUT(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT) +#define BITS_WMAC_TXTIMEOUT \ + (BIT_MASK_WMAC_TXTIMEOUT << BIT_SHIFT_WMAC_TXTIMEOUT) +#define BIT_CLEAR_WMAC_TXTIMEOUT(x) ((x) & (~BITS_WMAC_TXTIMEOUT)) +#define BIT_GET_WMAC_TXTIMEOUT(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT) +#define BIT_SET_WMAC_TXTIMEOUT(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT(x) | BIT_WMAC_TXTIMEOUT(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_MCU_TEST_2_V1 (Offset 0x0636) */ +#define BIT_SHIFT_MCU_RSVD_2_V1 0 +#define BIT_MASK_MCU_RSVD_2_V1 0xffff +#define BIT_MCU_RSVD_2_V1(x) \ + (((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1) +#define BITS_MCU_RSVD_2_V1 (BIT_MASK_MCU_RSVD_2_V1 << BIT_SHIFT_MCU_RSVD_2_V1) +#define BIT_CLEAR_MCU_RSVD_2_V1(x) ((x) & (~BITS_MCU_RSVD_2_V1)) +#define BIT_GET_MCU_RSVD_2_V1(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1) +#define BIT_SET_MCU_RSVD_2_V1(x, v) \ + (BIT_CLEAR_MCU_RSVD_2_V1(x) | BIT_MCU_RSVD_2_V1(v)) -/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 (Offset 0x0788) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_ISOLATION_CHK_1 0 -#define BIT_MASK_ISOLATION_CHK_1 0xffffffffL -#define BIT_ISOLATION_CHK_1(x) (((x) & BIT_MASK_ISOLATION_CHK_1) << BIT_SHIFT_ISOLATION_CHK_1) -#define BIT_GET_ISOLATION_CHK_1(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_1) & BIT_MASK_ISOLATION_CHK_1) +/* 2 REG_USTIME_EDCA (Offset 0x0638) */ +#define BIT_SHIFT_USTIME_EDCA 0 +#define BIT_MASK_USTIME_EDCA 0xff +#define BIT_USTIME_EDCA(x) \ + (((x) & BIT_MASK_USTIME_EDCA) << BIT_SHIFT_USTIME_EDCA) +#define BITS_USTIME_EDCA (BIT_MASK_USTIME_EDCA << BIT_SHIFT_USTIME_EDCA) +#define BIT_CLEAR_USTIME_EDCA(x) ((x) & (~BITS_USTIME_EDCA)) +#define BIT_GET_USTIME_EDCA(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA) & BIT_MASK_USTIME_EDCA) +#define BIT_SET_USTIME_EDCA(x, v) \ + (BIT_CLEAR_USTIME_EDCA(x) | BIT_USTIME_EDCA(v)) -/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 (Offset 0x078C) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_ISOLATION_CHK_2 0 -#define BIT_MASK_ISOLATION_CHK_2 0xffffff -#define BIT_ISOLATION_CHK_2(x) (((x) & BIT_MASK_ISOLATION_CHK_2) << BIT_SHIFT_ISOLATION_CHK_2) -#define BIT_GET_ISOLATION_CHK_2(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_2) & BIT_MASK_ISOLATION_CHK_2) +/* 2 REG_USTIME_EDCA (Offset 0x0638) */ +#define BIT_SHIFT_USTIME 0 +#define BIT_MASK_USTIME 0xff +#define BIT_USTIME(x) (((x) & BIT_MASK_USTIME) << BIT_SHIFT_USTIME) +#define BITS_USTIME (BIT_MASK_USTIME << BIT_SHIFT_USTIME) +#define BIT_CLEAR_USTIME(x) ((x) & (~BITS_USTIME)) +#define BIT_GET_USTIME(x) (((x) >> BIT_SHIFT_USTIME) & BIT_MASK_USTIME) +#define BIT_SET_USTIME(x, v) (BIT_CLEAR_USTIME(x) | BIT_USTIME(v)) #endif +#if (HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_USTIME_EDCA (Offset 0x0638) */ +#define BIT_SHIFT_USTIME_EDCA_V1 0 +#define BIT_MASK_USTIME_EDCA_V1 0x1ff +#define BIT_USTIME_EDCA_V1(x) \ + (((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1) +#define BITS_USTIME_EDCA_V1 \ + (BIT_MASK_USTIME_EDCA_V1 << BIT_SHIFT_USTIME_EDCA_V1) +#define BIT_CLEAR_USTIME_EDCA_V1(x) ((x) & (~BITS_USTIME_EDCA_V1)) +#define BIT_GET_USTIME_EDCA_V1(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1) +#define BIT_SET_USTIME_EDCA_V1(x, v) \ + (BIT_CLEAR_USTIME_EDCA_V1(x) | BIT_USTIME_EDCA_V1(v)) -/* 2 REG_BT_INTERRUPT_STATUS_REGISTER (Offset 0x078F) */ +#endif -#define BIT_BT_HID_ISR BIT(7) -#define BIT_BT_QUERY_ISR BIT(6) -#define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5) -#define BIT_WLAN_RPT_ISR BIT(4) -#define BIT_BT_POWER_ISR BIT(3) -#define BIT_BT_CHANNEL_ISR BIT(2) -#define BIT_BT_SLOT_CHANGE_ISR BIT(1) -#define BIT_BT_PROFILE_ISR BIT(0) +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_BT_TDMA_TIME_REGISTER (Offset 0x0790) */ +/* 2 REG_ACKTO_CCK (Offset 0x0639) */ +#define BIT_SHIFT_ACKTO_CCK 0 +#define BIT_MASK_ACKTO_CCK 0xff +#define BIT_ACKTO_CCK(x) (((x) & BIT_MASK_ACKTO_CCK) << BIT_SHIFT_ACKTO_CCK) +#define BITS_ACKTO_CCK (BIT_MASK_ACKTO_CCK << BIT_SHIFT_ACKTO_CCK) +#define BIT_CLEAR_ACKTO_CCK(x) ((x) & (~BITS_ACKTO_CCK)) +#define BIT_GET_ACKTO_CCK(x) (((x) >> BIT_SHIFT_ACKTO_CCK) & BIT_MASK_ACKTO_CCK) +#define BIT_SET_ACKTO_CCK(x, v) (BIT_CLEAR_ACKTO_CCK(x) | BIT_ACKTO_CCK(v)) -#define BIT_SHIFT_BT_TIME 6 -#define BIT_MASK_BT_TIME 0x3ffffff -#define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME) -#define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0 -#define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f -#define BIT_BT_RPT_SAMPLE_RATE(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE) -#define BIT_GET_BT_RPT_SAMPLE_RATE(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE) +/* 2 REG_MAC_SPEC_SIFS (Offset 0x063A) */ +#define BIT_SHIFT_SPEC_SIFS_OFDM 8 +#define BIT_MASK_SPEC_SIFS_OFDM 0xff +#define BIT_SPEC_SIFS_OFDM(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM) +#define BITS_SPEC_SIFS_OFDM \ + (BIT_MASK_SPEC_SIFS_OFDM << BIT_SHIFT_SPEC_SIFS_OFDM) +#define BIT_CLEAR_SPEC_SIFS_OFDM(x) ((x) & (~BITS_SPEC_SIFS_OFDM)) +#define BIT_GET_SPEC_SIFS_OFDM(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM) +#define BIT_SET_SPEC_SIFS_OFDM(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM(x) | BIT_SPEC_SIFS_OFDM(v)) + +#define BIT_SHIFT_SPEC_SIFS_CCK 0 +#define BIT_MASK_SPEC_SIFS_CCK 0xff +#define BIT_SPEC_SIFS_CCK(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK) +#define BITS_SPEC_SIFS_CCK (BIT_MASK_SPEC_SIFS_CCK << BIT_SHIFT_SPEC_SIFS_CCK) +#define BIT_CLEAR_SPEC_SIFS_CCK(x) ((x) & (~BITS_SPEC_SIFS_CCK)) +#define BIT_GET_SPEC_SIFS_CCK(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK) +#define BIT_SET_SPEC_SIFS_CCK(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK(x) | BIT_SPEC_SIFS_CCK(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ +/* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */ +#define BIT_SHIFT_SIFS_R2T_CCK 8 +#define BIT_MASK_SIFS_R2T_CCK 0xff +#define BIT_SIFS_R2T_CCK(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK) +#define BITS_SIFS_R2T_CCK (BIT_MASK_SIFS_R2T_CCK << BIT_SHIFT_SIFS_R2T_CCK) +#define BIT_CLEAR_SIFS_R2T_CCK(x) ((x) & (~BITS_SIFS_R2T_CCK)) +#define BIT_GET_SIFS_R2T_CCK(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK) +#define BIT_SET_SIFS_R2T_CCK(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK(x) | BIT_SIFS_R2T_CCK(v)) -#define BIT_SHIFT_BT_EISR_EN 16 -#define BIT_MASK_BT_EISR_EN 0xff -#define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN) -#define BIT_GET_BT_EISR_EN(x) (((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN) +#endif -#define BIT_BT_ACT_FALLING_ISR BIT(10) -#define BIT_BT_ACT_RISING_ISR BIT(9) -#define BIT_TDMA_TO_ISR BIT(8) +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_BT_CH 0 -#define BIT_MASK_BT_CH 0xff -#define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH) -#define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH) +/* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */ +#define BIT_SHIFT_R2T_SIFS_CCK 8 +#define BIT_MASK_R2T_SIFS_CCK 0xff +#define BIT_R2T_SIFS_CCK(x) \ + (((x) & BIT_MASK_R2T_SIFS_CCK) << BIT_SHIFT_R2T_SIFS_CCK) +#define BITS_R2T_SIFS_CCK (BIT_MASK_R2T_SIFS_CCK << BIT_SHIFT_R2T_SIFS_CCK) +#define BIT_CLEAR_R2T_SIFS_CCK(x) ((x) & (~BITS_R2T_SIFS_CCK)) +#define BIT_GET_R2T_SIFS_CCK(x) \ + (((x) >> BIT_SHIFT_R2T_SIFS_CCK) & BIT_MASK_R2T_SIFS_CCK) +#define BIT_SET_R2T_SIFS_CCK(x, v) \ + (BIT_CLEAR_R2T_SIFS_CCK(x) | BIT_R2T_SIFS_CCK(v)) -/* 2 REG_OBFF_CTRL_BASIC (Offset 0x0798) */ +#endif -#define BIT_OBFF_EN_V1 BIT(31) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_OBFF_STATE_V1 28 -#define BIT_MASK_OBFF_STATE_V1 0x3 -#define BIT_OBFF_STATE_V1(x) (((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1) -#define BIT_GET_OBFF_STATE_V1(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1) +/* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */ -#define BIT_OBFF_ACT_RXDMA_EN BIT(27) -#define BIT_OBFF_BLOCK_INT_EN BIT(26) -#define BIT_OBFF_AUTOACT_EN BIT(25) -#define BIT_OBFF_AUTOIDLE_EN BIT(24) +#define BIT_SHIFT_SIFS_T2T_CCK 0 +#define BIT_MASK_SIFS_T2T_CCK 0xff +#define BIT_SIFS_T2T_CCK(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK) +#define BITS_SIFS_T2T_CCK (BIT_MASK_SIFS_T2T_CCK << BIT_SHIFT_SIFS_T2T_CCK) +#define BIT_CLEAR_SIFS_T2T_CCK(x) ((x) & (~BITS_SIFS_T2T_CCK)) +#define BIT_GET_SIFS_T2T_CCK(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK) +#define BIT_SET_SIFS_T2T_CCK(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK(x) | BIT_SIFS_T2T_CCK(v)) -#define BIT_SHIFT_WAKE_MAX_PLS 20 -#define BIT_MASK_WAKE_MAX_PLS 0x7 -#define BIT_WAKE_MAX_PLS(x) (((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS) -#define BIT_GET_WAKE_MAX_PLS(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_WAKE_MIN_PLS 16 -#define BIT_MASK_WAKE_MIN_PLS 0x7 -#define BIT_WAKE_MIN_PLS(x) (((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS) -#define BIT_GET_WAKE_MIN_PLS(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS) +/* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */ +#define BIT_SHIFT_T2T_SIFS_CCK 0 +#define BIT_MASK_T2T_SIFS_CCK 0xff +#define BIT_T2T_SIFS_CCK(x) \ + (((x) & BIT_MASK_T2T_SIFS_CCK) << BIT_SHIFT_T2T_SIFS_CCK) +#define BITS_T2T_SIFS_CCK (BIT_MASK_T2T_SIFS_CCK << BIT_SHIFT_T2T_SIFS_CCK) +#define BIT_CLEAR_T2T_SIFS_CCK(x) ((x) & (~BITS_T2T_SIFS_CCK)) +#define BIT_GET_T2T_SIFS_CCK(x) \ + (((x) >> BIT_SHIFT_T2T_SIFS_CCK) & BIT_MASK_T2T_SIFS_CCK) +#define BIT_SET_T2T_SIFS_CCK(x, v) \ + (BIT_CLEAR_T2T_SIFS_CCK(x) | BIT_T2T_SIFS_CCK(v)) -#define BIT_SHIFT_WAKE_MAX_F2F 12 -#define BIT_MASK_WAKE_MAX_F2F 0x7 -#define BIT_WAKE_MAX_F2F(x) (((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F) -#define BIT_GET_WAKE_MAX_F2F(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WAKE_MIN_F2F 8 -#define BIT_MASK_WAKE_MIN_F2F 0x7 -#define BIT_WAKE_MIN_F2F(x) (((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F) -#define BIT_GET_WAKE_MIN_F2F(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F) +/* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */ -#define BIT_APP_CPU_ACT_V1 BIT(3) -#define BIT_APP_OBFF_V1 BIT(2) -#define BIT_APP_IDLE_V1 BIT(1) -#define BIT_APP_INIT_V1 BIT(0) +#define BIT_SHIFT_SIFS_R2T_OFDM 8 +#define BIT_MASK_SIFS_R2T_OFDM 0xff +#define BIT_SIFS_R2T_OFDM(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM) +#define BITS_SIFS_R2T_OFDM (BIT_MASK_SIFS_R2T_OFDM << BIT_SHIFT_SIFS_R2T_OFDM) +#define BIT_CLEAR_SIFS_R2T_OFDM(x) ((x) & (~BITS_SIFS_R2T_OFDM)) +#define BIT_GET_SIFS_R2T_OFDM(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM) +#define BIT_SET_SIFS_R2T_OFDM(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM(x) | BIT_SIFS_R2T_OFDM(v)) -/* 2 REG_OBFF_CTRL2_TIMER (Offset 0x079C) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_RX_HIGH_TIMER_IDX 24 -#define BIT_MASK_RX_HIGH_TIMER_IDX 0x7 -#define BIT_RX_HIGH_TIMER_IDX(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX) -#define BIT_GET_RX_HIGH_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX) +/* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */ +#define BIT_SHIFT_R2T_SIFS_OFDM 8 +#define BIT_MASK_R2T_SIFS_OFDM 0xff +#define BIT_R2T_SIFS_OFDM(x) \ + (((x) & BIT_MASK_R2T_SIFS_OFDM) << BIT_SHIFT_R2T_SIFS_OFDM) +#define BITS_R2T_SIFS_OFDM (BIT_MASK_R2T_SIFS_OFDM << BIT_SHIFT_R2T_SIFS_OFDM) +#define BIT_CLEAR_R2T_SIFS_OFDM(x) ((x) & (~BITS_R2T_SIFS_OFDM)) +#define BIT_GET_R2T_SIFS_OFDM(x) \ + (((x) >> BIT_SHIFT_R2T_SIFS_OFDM) & BIT_MASK_R2T_SIFS_OFDM) +#define BIT_SET_R2T_SIFS_OFDM(x, v) \ + (BIT_CLEAR_R2T_SIFS_OFDM(x) | BIT_R2T_SIFS_OFDM(v)) -#define BIT_SHIFT_RX_MED_TIMER_IDX 16 -#define BIT_MASK_RX_MED_TIMER_IDX 0x7 -#define BIT_RX_MED_TIMER_IDX(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX) -#define BIT_GET_RX_MED_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_RX_LOW_TIMER_IDX 8 -#define BIT_MASK_RX_LOW_TIMER_IDX 0x7 -#define BIT_RX_LOW_TIMER_IDX(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX) -#define BIT_GET_RX_LOW_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX) +/* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */ +#define BIT_SHIFT_SIFS_T2T_OFDM 0 +#define BIT_MASK_SIFS_T2T_OFDM 0xff +#define BIT_SIFS_T2T_OFDM(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM) +#define BITS_SIFS_T2T_OFDM (BIT_MASK_SIFS_T2T_OFDM << BIT_SHIFT_SIFS_T2T_OFDM) +#define BIT_CLEAR_SIFS_T2T_OFDM(x) ((x) & (~BITS_SIFS_T2T_OFDM)) +#define BIT_GET_SIFS_T2T_OFDM(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM) +#define BIT_SET_SIFS_T2T_OFDM(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM(x) | BIT_SIFS_T2T_OFDM(v)) -#define BIT_SHIFT_OBFF_INT_TIMER_IDX 0 -#define BIT_MASK_OBFF_INT_TIMER_IDX 0x7 -#define BIT_OBFF_INT_TIMER_IDX(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX) -#define BIT_GET_OBFF_INT_TIMER_IDX(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_LTR_CTRL_BASIC (Offset 0x07A0) */ +/* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */ -#define BIT_LTR_EN_V1 BIT(31) -#define BIT_LTR_HW_EN_V1 BIT(30) -#define BIT_LRT_ACT_CTS_EN BIT(29) -#define BIT_LTR_ACT_RXPKT_EN BIT(28) -#define BIT_LTR_ACT_RXDMA_EN BIT(27) -#define BIT_LTR_IDLE_NO_SNOOP BIT(26) -#define BIT_SPDUP_MGTPKT BIT(25) -#define BIT_RX_AGG_EN BIT(24) -#define BIT_APP_LTR_ACT BIT(23) -#define BIT_APP_LTR_IDLE BIT(22) +#define BIT_SHIFT_T2T_SIFS_OFDM 0 +#define BIT_MASK_T2T_SIFS_OFDM 0xff +#define BIT_T2T_SIFS_OFDM(x) \ + (((x) & BIT_MASK_T2T_SIFS_OFDM) << BIT_SHIFT_T2T_SIFS_OFDM) +#define BITS_T2T_SIFS_OFDM (BIT_MASK_T2T_SIFS_OFDM << BIT_SHIFT_T2T_SIFS_OFDM) +#define BIT_CLEAR_T2T_SIFS_OFDM(x) ((x) & (~BITS_T2T_SIFS_OFDM)) +#define BIT_GET_T2T_SIFS_OFDM(x) \ + (((x) >> BIT_SHIFT_T2T_SIFS_OFDM) & BIT_MASK_T2T_SIFS_OFDM) +#define BIT_SET_T2T_SIFS_OFDM(x, v) \ + (BIT_CLEAR_T2T_SIFS_OFDM(x) | BIT_T2T_SIFS_OFDM(v)) -#define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20 -#define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3 -#define BIT_HIGH_RATE_TRIG_SEL(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL) -#define BIT_GET_HIGH_RATE_TRIG_SEL(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_MED_RATE_TRIG_SEL 18 -#define BIT_MASK_MED_RATE_TRIG_SEL 0x3 -#define BIT_MED_RATE_TRIG_SEL(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL) -#define BIT_GET_MED_RATE_TRIG_SEL(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL) +/* 2 REG_ACKTO (Offset 0x0640) */ +#define BIT_SHIFT_ACKTO 0 +#define BIT_MASK_ACKTO 0xff +#define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO) +#define BITS_ACKTO (BIT_MASK_ACKTO << BIT_SHIFT_ACKTO) +#define BIT_CLEAR_ACKTO(x) ((x) & (~BITS_ACKTO)) +#define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO) +#define BIT_SET_ACKTO(x, v) (BIT_CLEAR_ACKTO(x) | BIT_ACKTO(v)) -#define BIT_SHIFT_LOW_RATE_TRIG_SEL 16 -#define BIT_MASK_LOW_RATE_TRIG_SEL 0x3 -#define BIT_LOW_RATE_TRIG_SEL(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL) -#define BIT_GET_LOW_RATE_TRIG_SEL(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL) +/* 2 REG_CTS2TO (Offset 0x0641) */ +#define BIT_SHIFT_CTS2TO 0 +#define BIT_MASK_CTS2TO 0xff +#define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO) +#define BITS_CTS2TO (BIT_MASK_CTS2TO << BIT_SHIFT_CTS2TO) +#define BIT_CLEAR_CTS2TO(x) ((x) & (~BITS_CTS2TO)) +#define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO) +#define BIT_SET_CTS2TO(x, v) (BIT_CLEAR_CTS2TO(x) | BIT_CTS2TO(v)) -#define BIT_SHIFT_HIGH_RATE_BD_IDX 8 -#define BIT_MASK_HIGH_RATE_BD_IDX 0x7f -#define BIT_HIGH_RATE_BD_IDX(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX) -#define BIT_GET_HIGH_RATE_BD_IDX(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX) +/* 2 REG_EIFS (Offset 0x0642) */ +#define BIT_SHIFT_EIFS 0 +#define BIT_MASK_EIFS 0xffff +#define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS) +#define BITS_EIFS (BIT_MASK_EIFS << BIT_SHIFT_EIFS) +#define BIT_CLEAR_EIFS(x) ((x) & (~BITS_EIFS)) +#define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS) +#define BIT_SET_EIFS(x, v) (BIT_CLEAR_EIFS(x) | BIT_EIFS(v)) -#define BIT_SHIFT_LOW_RATE_BD_IDX 0 -#define BIT_MASK_LOW_RATE_BD_IDX 0x7f -#define BIT_LOW_RATE_BD_IDX(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX) -#define BIT_GET_LOW_RATE_BD_IDX(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD (Offset 0x07A4) */ +/* 2 REG_RPFM_MAP0 (Offset 0x0644) */ + +#define BIT_MGT_RPFM15EN BIT(15) +#define BIT_MGT_RPFM14EN BIT(14) +#define BIT_MGT_RPFM13EN BIT(13) +#define BIT_MGT_RPFM12EN BIT(12) +#define BIT_MGT_RPFM11EN BIT(11) +#define BIT_MGT_RPFM10EN BIT(10) +#define BIT_MGT_RPFM9EN BIT(9) +#define BIT_MGT_RPFM8EN BIT(8) +#define BIT_MGT_RPFM7EN BIT(7) +#define BIT_MGT_RPFM6EN BIT(6) +#define BIT_MGT_RPFM5EN BIT(5) +#define BIT_MGT_RPFM4EN BIT(4) +#define BIT_MGT_RPFM3EN BIT(3) +#define BIT_MGT_RPFM2EN BIT(2) +#define BIT_MGT_RPFM1EN BIT(1) +#endif + +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24 -#define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7 -#define BIT_RX_EMPTY_TIMER_IDX(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX) -#define BIT_GET_RX_EMPTY_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX) +/* 2 REG_RPFM_MAP0 (Offset 0x0644) */ +#define BIT_SHIFT_RPFM_MAP0 0 +#define BIT_MASK_RPFM_MAP0 0xffff +#define BIT_RPFM_MAP0(x) (((x) & BIT_MASK_RPFM_MAP0) << BIT_SHIFT_RPFM_MAP0) +#define BITS_RPFM_MAP0 (BIT_MASK_RPFM_MAP0 << BIT_SHIFT_RPFM_MAP0) +#define BIT_CLEAR_RPFM_MAP0(x) ((x) & (~BITS_RPFM_MAP0)) +#define BIT_GET_RPFM_MAP0(x) (((x) >> BIT_SHIFT_RPFM_MAP0) & BIT_MASK_RPFM_MAP0) +#define BIT_SET_RPFM_MAP0(x, v) (BIT_CLEAR_RPFM_MAP0(x) | BIT_RPFM_MAP0(v)) -#define BIT_SHIFT_RX_AFULL_TH_IDX 20 -#define BIT_MASK_RX_AFULL_TH_IDX 0x7 -#define BIT_RX_AFULL_TH_IDX(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX) -#define BIT_GET_RX_AFULL_TH_IDX(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RX_HIGH_TH_IDX 16 -#define BIT_MASK_RX_HIGH_TH_IDX 0x7 -#define BIT_RX_HIGH_TH_IDX(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX) -#define BIT_GET_RX_HIGH_TH_IDX(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX) +/* 2 REG_RPFM_MAP0 (Offset 0x0644) */ +#define BIT_MGT_RPFM0EN BIT(0) -#define BIT_SHIFT_RX_MED_TH_IDX 12 -#define BIT_MASK_RX_MED_TH_IDX 0x7 -#define BIT_RX_MED_TH_IDX(x) (((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX) -#define BIT_GET_RX_MED_TH_IDX(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RX_LOW_TH_IDX 8 -#define BIT_MASK_RX_LOW_TH_IDX 0x7 -#define BIT_RX_LOW_TH_IDX(x) (((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX) -#define BIT_GET_RX_LOW_TH_IDX(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX) +/* 2 REG_RPFM_MAP1_V1 (Offset 0x0646) */ +#define BIT_DATA_RPFM15EN BIT(15) +#define BIT_DATA_RPFM14EN BIT(14) +#define BIT_DATA_RPFM13EN BIT(13) +#define BIT_DATA_RPFM12EN BIT(12) +#define BIT_DATA_RPFM11EN BIT(11) +#define BIT_DATA_RPFM10EN BIT(10) +#define BIT_DATA_RPFM9EN BIT(9) +#define BIT_DATA_RPFM8EN BIT(8) +#define BIT_DATA_RPFM7EN BIT(7) +#define BIT_DATA_RPFM6EN BIT(6) +#define BIT_DATA_RPFM5EN BIT(5) +#define BIT_DATA_RPFM4EN BIT(4) +#define BIT_DATA_RPFM3EN BIT(3) +#define BIT_DATA_RPFM2EN BIT(2) +#define BIT_DATA_RPFM1EN BIT(1) -#define BIT_SHIFT_LTR_SPACE_IDX 4 -#define BIT_MASK_LTR_SPACE_IDX 0x3 -#define BIT_LTR_SPACE_IDX(x) (((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX) -#define BIT_GET_LTR_SPACE_IDX(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0 -#define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7 -#define BIT_LTR_IDLE_TIMER_IDX(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX) -#define BIT_GET_LTR_IDLE_TIMER_IDX(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX) +/* 2 REG_RPFM_MAP1 (Offset 0x0646) */ +#define BIT_SHIFT_RPFM_MAP1 0 +#define BIT_MASK_RPFM_MAP1 0xffff +#define BIT_RPFM_MAP1(x) (((x) & BIT_MASK_RPFM_MAP1) << BIT_SHIFT_RPFM_MAP1) +#define BITS_RPFM_MAP1 (BIT_MASK_RPFM_MAP1 << BIT_SHIFT_RPFM_MAP1) +#define BIT_CLEAR_RPFM_MAP1(x) ((x) & (~BITS_RPFM_MAP1)) +#define BIT_GET_RPFM_MAP1(x) (((x) >> BIT_SHIFT_RPFM_MAP1) & BIT_MASK_RPFM_MAP1) +#define BIT_SET_RPFM_MAP1(x, v) (BIT_CLEAR_RPFM_MAP1(x) | BIT_RPFM_MAP1(v)) -/* 2 REG_LTR_IDLE_LATENCY_V1 (Offset 0x07A8) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LTR_IDLE_L 0 -#define BIT_MASK_LTR_IDLE_L 0xffffffffL -#define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L) -#define BIT_GET_LTR_IDLE_L(x) (((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L) +/* 2 REG_RPFM_MAP1_V1 (Offset 0x0646) */ +#define BIT_DATA_RPFM0EN BIT(0) -/* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */ +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LTR_ACT_L 0 -#define BIT_MASK_LTR_ACT_L 0xffffffffL -#define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L) -#define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L) +/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ +#define BIT_RPFM_CAM_POLLING BIT(31) +#define BIT_RPFM_CAM_CLR BIT(30) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ +#define BIT_RPFM_CAM_WR BIT(16) -/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ +#endif -#define BIT_APPEND_MACID_IN_RESP_EN BIT(50) -#define BIT_ADDR2_MATCH_EN BIT(49) -#define BIT_ANTTRN_EN BIT(48) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_TRAIN_STA_ADDR 0 -#define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL -#define BIT_TRAIN_STA_ADDR(x) (((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR) -#define BIT_GET_TRAIN_STA_ADDR(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR) +/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ +#define BIT_RPFM_CAM_WE BIT(16) +#define BIT_RPT_VALID BIT(13) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */ +#define BIT_SHIFT_RPFM_CAM_ADDR 0 +#define BIT_MASK_RPFM_CAM_ADDR 0x7f +#define BIT_RPFM_CAM_ADDR(x) \ + (((x) & BIT_MASK_RPFM_CAM_ADDR) << BIT_SHIFT_RPFM_CAM_ADDR) +#define BITS_RPFM_CAM_ADDR (BIT_MASK_RPFM_CAM_ADDR << BIT_SHIFT_RPFM_CAM_ADDR) +#define BIT_CLEAR_RPFM_CAM_ADDR(x) ((x) & (~BITS_RPFM_CAM_ADDR)) +#define BIT_GET_RPFM_CAM_ADDR(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_ADDR) & BIT_MASK_RPFM_CAM_ADDR) +#define BIT_SET_RPFM_CAM_ADDR(x, v) \ + (BIT_CLEAR_RPFM_CAM_ADDR(x) | BIT_RPFM_CAM_ADDR(v)) -/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ +/* 2 REG_RPFM_CAM_RWD (Offset 0x064C) */ +#define BIT_SHIFT_RPFM_CAM_RWD 0 +#define BIT_MASK_RPFM_CAM_RWD 0xffffffffL +#define BIT_RPFM_CAM_RWD(x) \ + (((x) & BIT_MASK_RPFM_CAM_RWD) << BIT_SHIFT_RPFM_CAM_RWD) +#define BITS_RPFM_CAM_RWD (BIT_MASK_RPFM_CAM_RWD << BIT_SHIFT_RPFM_CAM_RWD) +#define BIT_CLEAR_RPFM_CAM_RWD(x) ((x) & (~BITS_RPFM_CAM_RWD)) +#define BIT_GET_RPFM_CAM_RWD(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_RWD) & BIT_MASK_RPFM_CAM_RWD) +#define BIT_SET_RPFM_CAM_RWD(x, v) \ + (BIT_CLEAR_RPFM_CAM_RWD(x) | BIT_RPFM_CAM_RWD(v)) -#define BIT_SHIFT_TRAIN_STA_ADDR_0 0 -#define BIT_MASK_TRAIN_STA_ADDR_0 0xffffffffL -#define BIT_TRAIN_STA_ADDR_0(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_0) << BIT_SHIFT_TRAIN_STA_ADDR_0) -#define BIT_GET_TRAIN_STA_ADDR_0(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0) & BIT_MASK_TRAIN_STA_ADDR_0) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 (Offset 0x07B4) */ +/* 2 REG_NAV_CTRL (Offset 0x0650) */ -#define BIT_APPEND_MACID_IN_RESP_EN_1 BIT(18) -#define BIT_ADDR2_MATCH_EN_1 BIT(17) -#define BIT_ANTTRN_EN_1 BIT(16) +#define BIT_SHIFT_NAV_UPPER 16 +#define BIT_MASK_NAV_UPPER 0xff +#define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER) +#define BITS_NAV_UPPER (BIT_MASK_NAV_UPPER << BIT_SHIFT_NAV_UPPER) +#define BIT_CLEAR_NAV_UPPER(x) ((x) & (~BITS_NAV_UPPER)) +#define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER) +#define BIT_SET_NAV_UPPER(x, v) (BIT_CLEAR_NAV_UPPER(x) | BIT_NAV_UPPER(v)) + +#define BIT_SHIFT_RXMYRTS_NAV 8 +#define BIT_MASK_RXMYRTS_NAV 0xf +#define BIT_RXMYRTS_NAV(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV) +#define BITS_RXMYRTS_NAV (BIT_MASK_RXMYRTS_NAV << BIT_SHIFT_RXMYRTS_NAV) +#define BIT_CLEAR_RXMYRTS_NAV(x) ((x) & (~BITS_RXMYRTS_NAV)) +#define BIT_GET_RXMYRTS_NAV(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV) +#define BIT_SET_RXMYRTS_NAV(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV(x) | BIT_RXMYRTS_NAV(v)) + +#define BIT_SHIFT_RTSRST 0 +#define BIT_MASK_RTSRST 0xff +#define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST) +#define BITS_RTSRST (BIT_MASK_RTSRST << BIT_SHIFT_RTSRST) +#define BIT_CLEAR_RTSRST(x) ((x) & (~BITS_RTSRST)) +#define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST) +#define BIT_SET_RTSRST(x, v) (BIT_CLEAR_RTSRST(x) | BIT_RTSRST(v)) -#define BIT_SHIFT_TRAIN_STA_ADDR_1 0 -#define BIT_MASK_TRAIN_STA_ADDR_1 0xffff -#define BIT_TRAIN_STA_ADDR_1(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_1) << BIT_SHIFT_TRAIN_STA_ADDR_1) -#define BIT_GET_TRAIN_STA_ADDR_1(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1) & BIT_MASK_TRAIN_STA_ADDR_1) +/* 2 REG_BACAMCMD (Offset 0x0654) */ +#define BIT_BACAM_POLL BIT(31) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_BACAMCMD (Offset 0x0654) */ +#define BIT_BACAM_RST BIT(17) -/* 2 REG_WMAC_PKTCNT_RWD (Offset 0x07B8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKTCNT_BSSIDMAP 4 -#define BIT_MASK_PKTCNT_BSSIDMAP 0xf -#define BIT_PKTCNT_BSSIDMAP(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP) -#define BIT_GET_PKTCNT_BSSIDMAP(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP) +/* 2 REG_BACAMCMD (Offset 0x0654) */ -#define BIT_PKTCNT_CNTRST BIT(1) -#define BIT_PKTCNT_CNTEN BIT(0) +#define BIT_BACAM_RW BIT(16) -/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ +#endif -#define BIT_WMAC_PKTCNT_TRST BIT(9) -#define BIT_WMAC_PKTCNT_FEN BIT(8) +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0 -#define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff -#define BIT_WMAC_PKTCNT_CFGAD(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD) -#define BIT_GET_WMAC_PKTCNT_CFGAD(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD) +/* 2 REG_BACAMCMD (Offset 0x0654) */ +#define BIT_SHIFT_TXSBM 14 +#define BIT_MASK_TXSBM 0x3 +#define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM) +#define BITS_TXSBM (BIT_MASK_TXSBM << BIT_SHIFT_TXSBM) +#define BIT_CLEAR_TXSBM(x) ((x) & (~BITS_TXSBM)) +#define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM) +#define BIT_SET_TXSBM(x, v) (BIT_CLEAR_TXSBM(x) | BIT_TXSBM(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BACAMCMD (Offset 0x0654) */ +#define BIT_SHIFT_TXSBMPMOD 14 +#define BIT_MASK_TXSBMPMOD 0x3 +#define BIT_TXSBMPMOD(x) (((x) & BIT_MASK_TXSBMPMOD) << BIT_SHIFT_TXSBMPMOD) +#define BITS_TXSBMPMOD (BIT_MASK_TXSBMPMOD << BIT_SHIFT_TXSBMPMOD) +#define BIT_CLEAR_TXSBMPMOD(x) ((x) & (~BITS_TXSBMPMOD)) +#define BIT_GET_TXSBMPMOD(x) (((x) >> BIT_SHIFT_TXSBMPMOD) & BIT_MASK_TXSBMPMOD) +#define BIT_SET_TXSBMPMOD(x, v) (BIT_CLEAR_TXSBMPMOD(x) | BIT_TXSBMPMOD(v)) -/* 2 REG_IQ_DUMP (Offset 0x07C0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC) -#define BIT_GET_R_WMAC_MATCH_REF_MAC(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) & BIT_MASK_R_WMAC_MATCH_REF_MAC) +/* 2 REG_BACAMCMD (Offset 0x0654) */ +#define BIT_SHIFT_BACAM_ADDR 0 +#define BIT_MASK_BACAM_ADDR 0x3f +#define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR) +#define BITS_BACAM_ADDR (BIT_MASK_BACAM_ADDR << BIT_SHIFT_BACAM_ADDR) +#define BIT_CLEAR_BACAM_ADDR(x) ((x) & (~BITS_BACAM_ADDR)) +#define BIT_GET_BACAM_ADDR(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR) +#define BIT_SET_BACAM_ADDR(x, v) (BIT_CLEAR_BACAM_ADDR(x) | BIT_BACAM_ADDR(v)) -#define BIT_SHIFT_R_WMAC_RX_FIL_LEN (64 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_RX_FIL_LEN 0xffff -#define BIT_R_WMAC_RX_FIL_LEN(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN) << BIT_SHIFT_R_WMAC_RX_FIL_LEN) -#define BIT_GET_R_WMAC_RX_FIL_LEN(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN) & BIT_MASK_R_WMAC_RX_FIL_LEN) +#define BIT_SHIFT_BA_CONTENT_L 0 +#define BIT_MASK_BA_CONTENT_L 0xffffffffL +#define BIT_BA_CONTENT_L(x) \ + (((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L) +#define BITS_BA_CONTENT_L (BIT_MASK_BA_CONTENT_L << BIT_SHIFT_BA_CONTENT_L) +#define BIT_CLEAR_BA_CONTENT_L(x) ((x) & (~BITS_BA_CONTENT_L)) +#define BIT_GET_BA_CONTENT_L(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L) +#define BIT_SET_BA_CONTENT_L(x, v) \ + (BIT_CLEAR_BA_CONTENT_L(x) | BIT_BA_CONTENT_L(v)) +#define BIT_SHIFT_LBDLY 0 +#define BIT_MASK_LBDLY 0x1f +#define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY) +#define BITS_LBDLY (BIT_MASK_LBDLY << BIT_SHIFT_LBDLY) +#define BIT_CLEAR_LBDLY(x) ((x) & (~BITS_LBDLY)) +#define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY) +#define BIT_SET_LBDLY(x, v) (BIT_CLEAR_LBDLY(x) | BIT_LBDLY(v)) -#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) +#endif -#define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51) -#define BIT_R_WMAC_NDP_RST BIT(50) -#define BIT_R_WMAC_POWINT_EN BIT(49) -#define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48) -#define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47) -#define BIT_R_WMAC_PFIN_TOEN BIT(46) -#define BIT_R_WMAC_FIL_SECERR BIT(45) -#define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44) -#define BIT_R_WMAC_FIL_FCTYPE BIT(43) -#define BIT_R_WMAC_FIL_FCPROVER BIT(42) -#define BIT_R_WMAC_PHYSTS_SNIF BIT(41) -#define BIT_R_WMAC_PHYSTS_PLCP BIT(40) -#define BIT_R_MAC_TCR_VBONF_RD BIT(39) -#define BIT_R_WMAC_TCR_MPAR_NDP BIT(38) -#define BIT_R_WMAC_NDP_FILTER BIT(37) -#define BIT_R_WMAC_RXLEN_SEL BIT(36) -#define BIT_R_WMAC_RXLEN_SEL1 BIT(35) -#define BIT_R_OFDM_FILTER BIT(34) -#define BIT_R_WMAC_CHK_OFDM_LEN BIT(33) +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH) -#define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC) -#define BIT_GET_R_WMAC_MASK_LA_MAC(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC) +/* 2 REG_BITMAP_CMD (Offset 0x0661) */ -#define BIT_R_WMAC_CHK_CCK_LEN BIT(32) +#define BIT_BACAM_RPMEN BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ -/* 2 REG_IQ_DUMP (Offset 0x07C0) */ +#define BIT_WMAC_BACAM_RPMEN BIT(0) +#endif -#define BIT_SHIFT_R_OFDM_LEN 26 -#define BIT_MASK_R_OFDM_LEN 0x3f -#define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN) -#define BIT_GET_R_OFDM_LEN(x) (((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TX_RX (Offset 0x0662) */ -#define BIT_SHIFT_DUMP_OK_ADDR 15 -#define BIT_MASK_DUMP_OK_ADDR 0x1ffff -#define BIT_DUMP_OK_ADDR(x) (((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR) -#define BIT_GET_DUMP_OK_ADDR(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR) +#define BIT_SHIFT_RXPKT_TYPE 2 +#define BIT_MASK_RXPKT_TYPE 0x3f +#define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE) +#define BITS_RXPKT_TYPE (BIT_MASK_RXPKT_TYPE << BIT_SHIFT_RXPKT_TYPE) +#define BIT_CLEAR_RXPKT_TYPE(x) ((x) & (~BITS_RXPKT_TYPE)) +#define BIT_GET_RXPKT_TYPE(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE) +#define BIT_SET_RXPKT_TYPE(x, v) (BIT_CLEAR_RXPKT_TYPE(x) | BIT_RXPKT_TYPE(v)) +#define BIT_TXACT_IND BIT(1) +#define BIT_RXACT_IND BIT(0) -#define BIT_SHIFT_R_TRIG_TIME_SEL 8 -#define BIT_MASK_R_TRIG_TIME_SEL 0x7f -#define BIT_R_TRIG_TIME_SEL(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL) -#define BIT_GET_R_TRIG_TIME_SEL(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL) +/* 2 REG_WMAC_BITMAP_CTL (Offset 0x0663) */ +#define BIT_BITMAP_VO BIT(7) +#define BIT_BITMAP_VI BIT(6) +#define BIT_BITMAP_BE BIT(5) +#define BIT_BITMAP_BK BIT(4) -#define BIT_SHIFT_R_MAC_TRIG_SEL 6 -#define BIT_MASK_R_MAC_TRIG_SEL 0x3 -#define BIT_R_MAC_TRIG_SEL(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL) -#define BIT_GET_R_MAC_TRIG_SEL(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL) +#define BIT_SHIFT_BITMAP_CONDITION 2 +#define BIT_MASK_BITMAP_CONDITION 0x3 +#define BIT_BITMAP_CONDITION(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION) +#define BITS_BITMAP_CONDITION \ + (BIT_MASK_BITMAP_CONDITION << BIT_SHIFT_BITMAP_CONDITION) +#define BIT_CLEAR_BITMAP_CONDITION(x) ((x) & (~BITS_BITMAP_CONDITION)) +#define BIT_GET_BITMAP_CONDITION(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION) +#define BIT_SET_BITMAP_CONDITION(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION(x) | BIT_BITMAP_CONDITION(v)) -#define BIT_MAC_TRIG_REG BIT(5) +#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1) +#define BIT_BITMAP_FORCE BIT(0) -#define BIT_SHIFT_R_LEVEL_PULSE_SEL 3 -#define BIT_MASK_R_LEVEL_PULSE_SEL 0x3 -#define BIT_R_LEVEL_PULSE_SEL(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL) -#define BIT_GET_R_LEVEL_PULSE_SEL(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL) +#endif -#define BIT_EN_LA_MAC BIT(2) -#define BIT_R_EN_IQDUMP BIT(1) -#define BIT_R_IQDATA_DUMP BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_CCK_LEN 0 -#define BIT_MASK_R_CCK_LEN 0xffff -#define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN) -#define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN) +/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28 +#define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf +#define BIT_RXERR_RPT_SEL_V1_3_0(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) +#define BITS_RXERR_RPT_SEL_V1_3_0 \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) | BIT_RXERR_RPT_SEL_V1_3_0(v)) #endif +#if (HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#define BIT_SHIFT_RXERR_RPT_SEL 28 +#define BIT_MASK_RXERR_RPT_SEL 0xf +#define BIT_RXERR_RPT_SEL(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL) << BIT_SHIFT_RXERR_RPT_SEL) +#define BITS_RXERR_RPT_SEL (BIT_MASK_RXERR_RPT_SEL << BIT_SHIFT_RXERR_RPT_SEL) +#define BIT_CLEAR_RXERR_RPT_SEL(x) ((x) & (~BITS_RXERR_RPT_SEL)) +#define BIT_GET_RXERR_RPT_SEL(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL) & BIT_MASK_RXERR_RPT_SEL) +#define BIT_SET_RXERR_RPT_SEL(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL(x) | BIT_RXERR_RPT_SEL(v)) -/* 2 REG_IQ_DUMP_1 (Offset 0x07C4) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1 0 -#define BIT_MASK_R_WMAC_MASK_LA_MAC_1 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC_1(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) -#define BIT_GET_R_WMAC_MASK_LA_MAC_1(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) & BIT_MASK_R_WMAC_MASK_LA_MAC_1) +/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#define BIT_RXERR_RPT_RST BIT(27) -/* 2 REG_IQ_DUMP_2 (Offset 0x07C8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2 0 -#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC_2(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) -#define BIT_GET_R_WMAC_MATCH_REF_MAC_2(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2) +/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#define BIT_RXERR_RPT_SEL_V1_4 BIT(26) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ +/* 2 REG_RXERR_RPT (Offset 0x0664) */ -#define BIT_RXFTM_TXACK_SC BIT(6) -#define BIT_RXFTM_TXACK_BW BIT(5) -#define BIT_RXFTM_EN BIT(3) -#define BIT_RXFTMREQ_BYDRV BIT(2) -#define BIT_RXFTMREQ_EN BIT(1) -#define BIT_FTM_EN BIT(0) +#define BIT_SHIFT_UD_SELECT_BSSID_2_1 24 +#define BIT_MASK_UD_SELECT_BSSID_2_1 0x3 +#define BIT_UD_SELECT_BSSID_2_1(x) \ + (((x) & BIT_MASK_UD_SELECT_BSSID_2_1) << BIT_SHIFT_UD_SELECT_BSSID_2_1) +#define BITS_UD_SELECT_BSSID_2_1 \ + (BIT_MASK_UD_SELECT_BSSID_2_1 << BIT_SHIFT_UD_SELECT_BSSID_2_1) +#define BIT_CLEAR_UD_SELECT_BSSID_2_1(x) ((x) & (~BITS_UD_SELECT_BSSID_2_1)) +#define BIT_GET_UD_SELECT_BSSID_2_1(x) \ + (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1) & BIT_MASK_UD_SELECT_BSSID_2_1) +#define BIT_SET_UD_SELECT_BSSID_2_1(x, v) \ + (BIT_CLEAR_UD_SELECT_BSSID_2_1(x) | BIT_UD_SELECT_BSSID_2_1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#define BIT_W1S BIT(23) -/* 2 REG_IQ_DUMP_EXT (Offset 0x07CF) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_TIME_UNIT_SEL 0 -#define BIT_MASK_R_TIME_UNIT_SEL 0x7 -#define BIT_R_TIME_UNIT_SEL(x) (((x) & BIT_MASK_R_TIME_UNIT_SEL) << BIT_SHIFT_R_TIME_UNIT_SEL) -#define BIT_GET_R_TIME_UNIT_SEL(x) (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL) & BIT_MASK_R_TIME_UNIT_SEL) +/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#define BIT_UD_SELECT_BSSID BIT(22) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#define BIT_UD_SELECT_BSSID_0 BIT(22) -/* 2 REG_OFDM_CCK_LEN_MASK (Offset 0x07D0) */ +#endif -#define BIT_MICICV_CLR BIT(86) -#define BIT_MPDU_RDY_SET BIT(85) -#define BIT_CLR_SEC_TYPE BIT(84) -#define BIT_NEWPKT_IN BIT(83) -#define BIT_FCS_END BIT(82) -#define BIT_DEL_MESH_TYPE BIT(81) -#define BIT_MASK_MESH_TYPE BIT(80) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#define BIT_SHIFT_UD_SUB_TYPE 18 +#define BIT_MASK_UD_SUB_TYPE 0xf +#define BIT_UD_SUB_TYPE(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE) +#define BITS_UD_SUB_TYPE (BIT_MASK_UD_SUB_TYPE << BIT_SHIFT_UD_SUB_TYPE) +#define BIT_CLEAR_UD_SUB_TYPE(x) ((x) & (~BITS_UD_SUB_TYPE)) +#define BIT_GET_UD_SUB_TYPE(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE) +#define BIT_SET_UD_SUB_TYPE(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE(x) | BIT_UD_SUB_TYPE(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#define BIT_SHIFT_UD_TYPE 16 +#define BIT_MASK_UD_TYPE 0x3 +#define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE) +#define BITS_UD_TYPE (BIT_MASK_UD_TYPE << BIT_SHIFT_UD_TYPE) +#define BIT_CLEAR_UD_TYPE(x) ((x) & (~BITS_UD_TYPE)) +#define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE) +#define BIT_SET_UD_TYPE(x, v) (BIT_CLEAR_UD_TYPE(x) | BIT_UD_TYPE(v)) +#endif -/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_RXERR_RPT (Offset 0x0664) */ -#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1 24 -#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH_1(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) - -#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1 BIT(23) -#define BIT_R_WMAC_RXRST_DLY_1 BIT(22) -#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1 BIT(21) -#define BIT_R_WMAC_SRCH_TXRPT_UA1_1 BIT(20) -#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1 BIT(19) -#define BIT_R_WMAC_NDP_RST_1 BIT(18) -#define BIT_R_WMAC_POWINT_EN_1 BIT(17) -#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1 BIT(16) -#define BIT_R_WMAC_SRCH_TXRPT_MID_1 BIT(15) -#define BIT_R_WMAC_PFIN_TOEN_1 BIT(14) -#define BIT_R_WMAC_FIL_SECERR_1 BIT(13) -#define BIT_R_WMAC_FIL_CTLPKTLEN_1 BIT(12) -#define BIT_R_WMAC_FIL_FCTYPE_1 BIT(11) -#define BIT_R_WMAC_FIL_FCPROVER_1 BIT(10) -#define BIT_R_WMAC_PHYSTS_SNIF_1 BIT(9) -#define BIT_R_WMAC_PHYSTS_PLCP_1 BIT(8) -#define BIT_R_MAC_TCR_VBONF_RD_1 BIT(7) -#define BIT_R_WMAC_TCR_MPAR_NDP_1 BIT(6) -#define BIT_R_WMAC_NDP_FILTER_1 BIT(5) -#define BIT_R_WMAC_RXLEN_SEL_1 BIT(4) -#define BIT_R_WMAC_RXLEN_SEL1_1 BIT(3) -#define BIT_R_OFDM_FILTER_1 BIT(2) -#define BIT_R_WMAC_CHK_OFDM_LEN_1 BIT(1) -#define BIT_R_WMAC_CHK_CCK_LEN_1 BIT(0) +#define BIT_CTRLFLT5EN BIT(5) +#define BIT_CTRLFLT4EN BIT(4) +#define BIT_CTRLFLT3EN BIT(3) +#define BIT_CTRLFLT2EN BIT(2) +#define BIT_CTRLFLT1EN BIT(1) -/* 2 REG_WMAC_OPTION_FUNCTION_2 (Offset 0x07D8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2 0 -#define BIT_MASK_R_WMAC_RX_FIL_LEN_2 0xffff -#define BIT_R_WMAC_RX_FIL_LEN_2(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) -#define BIT_GET_R_WMAC_RX_FIL_LEN_2(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) +/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#define BIT_SHIFT_RPT_COUNTER 0 +#define BIT_MASK_RPT_COUNTER 0xffff +#define BIT_RPT_COUNTER(x) \ + (((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER) +#define BITS_RPT_COUNTER (BIT_MASK_RPT_COUNTER << BIT_SHIFT_RPT_COUNTER) +#define BIT_CLEAR_RPT_COUNTER(x) ((x) & (~BITS_RPT_COUNTER)) +#define BIT_GET_RPT_COUNTER(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER) +#define BIT_SET_RPT_COUNTER(x, v) \ + (BIT_CLEAR_RPT_COUNTER(x) | BIT_RPT_COUNTER(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_RXERR_RPT (Offset 0x0664) */ +#define BIT_CTRLFLT0EN BIT(0) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#endif -#define BIT_R_WMAC_RXHANG_EN BIT(15) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_RXBA_IGNOREA2 BIT(42) +#define BIT_EN_SAVE_ALL_TXOPADDR BIT(41) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_R_WMAC_MHRDDY_LATCH BIT(14) +#define BIT_DIS_TXBA_AMPDUFCSERR BIT(39) +#define BIT_DIS_TXBA_RXBARINFULL BIT(38) +#define BIT_DIS_TXCFE_INFULL BIT(37) +#define BIT_DIS_TXCTS_INFULL BIT(36) +#define BIT_EN_TXACKBA_IN_TX_RDG BIT(35) +#define BIT_EN_TXACKBA_IN_TXOP BIT(34) +#define BIT_EN_TXCTS_IN_RXNAV BIT(33) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_EN_TXCTS_INTXOP BIT(32) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#endif -#define BIT_R_MHRDDY_CLR BIT(13) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ + +#define BIT_BLK_EDCA_BBSLP BIT(31) +#define BIT_BLK_EDCA_BBSBY BIT(30) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_ACKTO_BLOCK_SCH_EN BIT(27) +#define BIT_EIFS_BLOCK_SCH_EN BIT(26) +#define BIT_PLCPCHK_RST_EIFS BIT(25) +#define BIT_CCA_RST_EIFS BIT(24) +#define BIT_DIS_UPD_MYRXPKTNAV BIT(23) +#define BIT_EARLY_TXBA BIT(22) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_SHIFT_RESP_CHNBUSY 20 +#define BIT_MASK_RESP_CHNBUSY 0x3 +#define BIT_RESP_CHNBUSY(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY) +#define BITS_RESP_CHNBUSY (BIT_MASK_RESP_CHNBUSY << BIT_SHIFT_RESP_CHNBUSY) +#define BIT_CLEAR_RESP_CHNBUSY(x) ((x) & (~BITS_RESP_CHNBUSY)) +#define BIT_GET_RESP_CHNBUSY(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY) +#define BIT_SET_RESP_CHNBUSY(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY(x) | BIT_RESP_CHNBUSY(v)) -#define BIT_R_WMAC_MHRDDY_CLR BIT(13) +#define BIT_RESP_DCTS_EN BIT(19) +#define BIT_RESP_DCFE_EN BIT(18) +#define BIT_RESP_SPLCPEN BIT(17) +#define BIT_RESP_SGIEN BIT(16) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_RESP_LDPC_EN BIT(15) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#endif -#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_MGTFLT15EN BIT(15) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) +#define BIT_DIS_RESP_ACKINCCA BIT(14) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_MGTFLT14EN BIT(14) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#endif -#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_DIS_RESP_CTSINCCA BIT(13) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_R_CHK_DELIMIT_LEN BIT(10) -#define BIT_R_REAPTER_ADDR_MATCH BIT(9) -#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8) -#define BIT_R_LATCH_MACHRDY BIT(7) -#define BIT_R_WMAC_RXFIL_REND BIT(6) -#define BIT_R_WMAC_MPDURDY_CLR BIT(5) -#define BIT_R_WMAC_CLRRXSEC BIT(4) -#define BIT_R_WMAC_RXFIL_RDEL BIT(3) -#define BIT_R_WMAC_RXFIL_FCSE BIT(2) -#define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1) -#define BIT_R_WMAC_RXFIL_MASKM BIT(0) +#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10 +#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7 +#define BIT_R_WMAC_SECOND_CCA_TIMER(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) +#define BITS_R_WMAC_SECOND_CCA_TIMER \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x) | BIT_R_WMAC_SECOND_CCA_TIMER(v)) #endif +#if (HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_SHIFT_SECOND_CCA_CNT 10 +#define BIT_MASK_SECOND_CCA_CNT 0x7 +#define BIT_SECOND_CCA_CNT(x) \ + (((x) & BIT_MASK_SECOND_CCA_CNT) << BIT_SHIFT_SECOND_CCA_CNT) +#define BITS_SECOND_CCA_CNT \ + (BIT_MASK_SECOND_CCA_CNT << BIT_SHIFT_SECOND_CCA_CNT) +#define BIT_CLEAR_SECOND_CCA_CNT(x) ((x) & (~BITS_SECOND_CCA_CNT)) +#define BIT_GET_SECOND_CCA_CNT(x) \ + (((x) >> BIT_SHIFT_SECOND_CCA_CNT) & BIT_MASK_SECOND_CCA_CNT) +#define BIT_SET_SECOND_CCA_CNT(x, v) \ + (BIT_CLEAR_SECOND_CCA_CNT(x) | BIT_SECOND_CCA_CNT(v)) -/* 2 REG_NDP_SIG (Offset 0x07E0) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0 -#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff -#define BIT_R_WMAC_TXNDP_SIGB(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB) -#define BIT_GET_R_WMAC_TXNDP_SIGB(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_SHIFT_RFMOD 7 +#define BIT_MASK_RFMOD 0x3 +#define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD) +#define BITS_RFMOD (BIT_MASK_RFMOD << BIT_SHIFT_RFMOD) +#define BIT_CLEAR_RFMOD(x) ((x) & (~BITS_RFMOD)) +#define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD) +#define BIT_SET_RFMOD(x, v) (BIT_CLEAR_RFMOD(x) | BIT_RFMOD(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_MGTFLT7EN BIT(7) -/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ +#endif +#if (HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH) -#define BIT_MASK_R_MAC_DEBUG 0xffffffffL -#define BIT_R_MAC_DEBUG(x) (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG) -#define BIT_GET_R_MAC_DEBUG(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_SHIFT_RF_MOD 7 +#define BIT_MASK_RF_MOD 0x3 +#define BIT_RF_MOD(x) (((x) & BIT_MASK_RF_MOD) << BIT_SHIFT_RF_MOD) +#define BITS_RF_MOD (BIT_MASK_RF_MOD << BIT_SHIFT_RF_MOD) +#define BIT_CLEAR_RF_MOD(x) ((x) & (~BITS_RF_MOD)) +#define BIT_GET_RF_MOD(x) (((x) >> BIT_SHIFT_RF_MOD) & BIT_MASK_RF_MOD) +#define BIT_SET_RF_MOD(x, v) (BIT_CLEAR_RF_MOD(x) | BIT_RF_MOD(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_MGTFLT6EN BIT(6) -/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_R_MAC_DBG_SHIFT 8 -#define BIT_MASK_R_MAC_DBG_SHIFT 0x7 -#define BIT_R_MAC_DBG_SHIFT(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT) -#define BIT_GET_R_MAC_DBG_SHIFT(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5 +#define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3 +#define BIT_RESP_CTS_DYNBW_SEL(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL) +#define BITS_RESP_CTS_DYNBW_SEL \ + (BIT_MASK_RESP_CTS_DYNBW_SEL << BIT_SHIFT_RESP_CTS_DYNBW_SEL) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_DYNBW_SEL)) +#define BIT_GET_RESP_CTS_DYNBW_SEL(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL) +#define BIT_SET_RESP_CTS_DYNBW_SEL(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) | BIT_RESP_CTS_DYNBW_SEL(v)) -#define BIT_SHIFT_R_MAC_DBG_SEL 0 -#define BIT_MASK_R_MAC_DBG_SEL 0x3 -#define BIT_R_MAC_DBG_SEL(x) (((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL) -#define BIT_GET_R_MAC_DBG_SEL(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL) +#endif +#if (HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL 5 +#define BIT_MASK_RESP_CTS_BW_DYNBW_SEL 0x3 +#define BIT_RESP_CTS_BW_DYNBW_SEL(x) \ + (((x) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL) \ + << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) +#define BITS_RESP_CTS_BW_DYNBW_SEL \ + (BIT_MASK_RESP_CTS_BW_DYNBW_SEL << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) +#define BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_BW_DYNBW_SEL)) +#define BIT_GET_RESP_CTS_BW_DYNBW_SEL(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) & \ + BIT_MASK_RESP_CTS_BW_DYNBW_SEL) +#define BIT_SET_RESP_CTS_BW_DYNBW_SEL(x, v) \ + (BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) | BIT_RESP_CTS_BW_DYNBW_SEL(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1 (Offset 0x07E8) */ +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_DLY_TX_WAIT_RXANTSEL BIT(4) -#define BIT_SHIFT_R_MAC_DEBUG_1 0 -#define BIT_MASK_R_MAC_DEBUG_1 0xffffffffL -#define BIT_R_MAC_DEBUG_1(x) (((x) & BIT_MASK_R_MAC_DEBUG_1) << BIT_SHIFT_R_MAC_DEBUG_1) -#define BIT_GET_R_MAC_DEBUG_1(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_1) & BIT_MASK_R_MAC_DEBUG_1) +#endif +#if (HALMAC_8814AMP_SUPPORT) -/* 2 REG_WSEC_OPTION (Offset 0x07EC) */ +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ -#define BIT_RXDEC_BM_MGNT BIT(22) -#define BIT_TXENC_BM_MGNT BIT(21) -#define BIT_RXDEC_UNI_MGNT BIT(20) -#define BIT_TXENC_UNI_MGNT BIT(19) +#define BIT_DELAY_TX_USE_RX_ANTSEL BIT(4) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_TXRESP_BY_RXANTSEL BIT(3) -/* 2 REG_SEC_OPT_V2 (Offset 0x07EC) */ +#endif -#define BIT_MASK_IV BIT(18) -#define BIT_EIVL_ENDIAN BIT(17) -#define BIT_EIVH_ENDIAN BIT(16) +#if (HALMAC_8814AMP_SUPPORT) -#define BIT_SHIFT_BT_TIME_CNT 0 -#define BIT_MASK_BT_TIME_CNT 0xff -#define BIT_BT_TIME_CNT(x) (((x) & BIT_MASK_BT_TIME_CNT) << BIT_SHIFT_BT_TIME_CNT) -#define BIT_GET_BT_TIME_CNT(x) (((x) >> BIT_SHIFT_BT_TIME_CNT) & BIT_MASK_BT_TIME_CNT) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_TX_USE_RX_ANTSEL BIT(3) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_RESP_EARLY_TXACK_RWEPTKIP BIT(2) -/* 2 REG_RTS_ADDR0 (Offset 0x07F0) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RTS_ADDR0 0 -#define BIT_MASK_RTS_ADDR0 0xffffffffffffL -#define BIT_RTS_ADDR0(x) (((x) & BIT_MASK_RTS_ADDR0) << BIT_SHIFT_RTS_ADDR0) -#define BIT_GET_RTS_ADDR0(x) (((x) >> BIT_SHIFT_RTS_ADDR0) & BIT_MASK_RTS_ADDR0) +/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ +#define BIT_SHIFT_ORIG_DCTS_CHK 0 +#define BIT_MASK_ORIG_DCTS_CHK 0x3 +#define BIT_ORIG_DCTS_CHK(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK) +#define BITS_ORIG_DCTS_CHK (BIT_MASK_ORIG_DCTS_CHK << BIT_SHIFT_ORIG_DCTS_CHK) +#define BIT_CLEAR_ORIG_DCTS_CHK(x) ((x) & (~BITS_ORIG_DCTS_CHK)) +#define BIT_GET_ORIG_DCTS_CHK(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK) +#define BIT_SET_ORIG_DCTS_CHK(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK(x) | BIT_ORIG_DCTS_CHK(v)) -/* 2 REG_RTS_ADDR1 (Offset 0x07F8) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RTS_ADDR1 0 -#define BIT_MASK_RTS_ADDR1 0xffffffffffffL -#define BIT_RTS_ADDR1(x) (((x) & BIT_MASK_RTS_ADDR1) << BIT_SHIFT_RTS_ADDR1) -#define BIT_GET_RTS_ADDR1(x) (((x) >> BIT_SHIFT_RTS_ADDR1) & BIT_MASK_RTS_ADDR1) +/* 2 REG_WMAC_TRXPTCL_CTL_H (Offset 0x066C) */ +#define BIT_RXBA_IGNOREA2_V1 BIT(10) +#define BIT_EN_SAVE_ALL_TXOPADDR_V1 BIT(9) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1 BIT(8) +#define BIT_DIS_TXBA_AMPDUFCSERR_V1 BIT(7) +#define BIT_DIS_TXBA_RXBARINFULL_V1 BIT(6) +#define BIT_DIS_TXCFE_INFULL_V1 BIT(5) +#define BIT_DIS_TXCTS_INFULL_V1 BIT(4) +#define BIT_EN_TXACKBA_IN_TX_RDG_V1 BIT(3) +#define BIT_EN_TXACKBA_IN_TXOP_V1 BIT(2) +#define BIT_EN_TXCTS_IN_RXNAV_V1 BIT(1) +#define BIT_EN_TXCTS_INTXOP_V1 BIT(0) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_CAMCMD (Offset 0x0670) */ +#define BIT_SECCAM_POLLING BIT(31) +#define BIT_SECCAM_CLR BIT(30) -/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +#endif -#define BIT_FEN_BB_GLB_RSTN_V1 BIT(17) -#define BIT_FEN_BBRSTB_V1 BIT(16) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_CAMCMD (Offset 0x0670) */ +#define BIT_MFBCAM_CLR BIT(29) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +/* 2 REG_CAMCMD (Offset 0x0670) */ -#define BIT_PWC_MA33V BIT(15) +#define BIT_SHIFT_RESP_TXPOWER 18 +#define BIT_MASK_RESP_TXPOWER 0x7 +#define BIT_RESP_TXPOWER(x) \ + (((x) & BIT_MASK_RESP_TXPOWER) << BIT_SHIFT_RESP_TXPOWER) +#define BITS_RESP_TXPOWER (BIT_MASK_RESP_TXPOWER << BIT_SHIFT_RESP_TXPOWER) +#define BIT_CLEAR_RESP_TXPOWER(x) ((x) & (~BITS_RESP_TXPOWER)) +#define BIT_GET_RESP_TXPOWER(x) \ + (((x) >> BIT_SHIFT_RESP_TXPOWER) & BIT_MASK_RESP_TXPOWER) +#define BIT_SET_RESP_TXPOWER(x, v) \ + (BIT_CLEAR_RESP_TXPOWER(x) | BIT_RESP_TXPOWER(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_CAMCMD (Offset 0x0670) */ +#define BIT_SECCAM_WE BIT(16) -/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +#endif -#define BIT_PWC_EV25V_1 BIT(14) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_CAMCMD (Offset 0x0670) */ +#define BIT_SHIFT_SECCAM_ADDR_V1 0 +#define BIT_MASK_SECCAM_ADDR_V1 0xff +#define BIT_SECCAM_ADDR_V1(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V1) << BIT_SHIFT_SECCAM_ADDR_V1) +#define BITS_SECCAM_ADDR_V1 \ + (BIT_MASK_SECCAM_ADDR_V1 << BIT_SHIFT_SECCAM_ADDR_V1) +#define BIT_CLEAR_SECCAM_ADDR_V1(x) ((x) & (~BITS_SECCAM_ADDR_V1)) +#define BIT_GET_SECCAM_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V1) & BIT_MASK_SECCAM_ADDR_V1) +#define BIT_SET_SECCAM_ADDR_V1(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V1(x) | BIT_SECCAM_ADDR_V1(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +/* 2 REG_CAMCMD (Offset 0x0670) */ -#define BIT_PWC_MA12V BIT(14) -#define BIT_PWC_MD12V BIT(13) -#define BIT_PWC_PD12V BIT(12) -#define BIT_PWC_UD12V BIT(11) -#define BIT_ISO_MA2MD BIT(1) +#define BIT_SHIFT_SECCAM_ADDR_V2 0 +#define BIT_MASK_SECCAM_ADDR_V2 0x3ff +#define BIT_SECCAM_ADDR_V2(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2) +#define BITS_SECCAM_ADDR_V2 \ + (BIT_MASK_SECCAM_ADDR_V2 << BIT_SHIFT_SECCAM_ADDR_V2) +#define BIT_CLEAR_SECCAM_ADDR_V2(x) ((x) & (~BITS_SECCAM_ADDR_V2)) +#define BIT_GET_SECCAM_ADDR_V2(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2) +#define BIT_SET_SECCAM_ADDR_V2(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2(x) | BIT_SECCAM_ADDR_V2(v)) #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_CAMCMD (Offset 0x0670) */ -/* 2 REG_SYS_CFG4 (Offset 0x1034) */ - -#define BIT_EF_CSER_1 BIT(26) -#define BIT_SW_PG_EN_1 BIT(10) +#define BIT_SHIFT_SECCAM_ADDR 0 +#define BIT_MASK_SECCAM_ADDR 0xff +#define BIT_SECCAM_ADDR(x) \ + (((x) & BIT_MASK_SECCAM_ADDR) << BIT_SHIFT_SECCAM_ADDR) +#define BITS_SECCAM_ADDR (BIT_MASK_SECCAM_ADDR << BIT_SHIFT_SECCAM_ADDR) +#define BIT_CLEAR_SECCAM_ADDR(x) ((x) & (~BITS_SECCAM_ADDR)) +#define BIT_GET_SECCAM_ADDR(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR) & BIT_MASK_SECCAM_ADDR) +#define BIT_SET_SECCAM_ADDR(x, v) \ + (BIT_CLEAR_SECCAM_ADDR(x) | BIT_SECCAM_ADDR(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CAMWRITE (Offset 0x0674) */ +#define BIT_SHIFT_CAMW_DATA 0 +#define BIT_MASK_CAMW_DATA 0xffffffffL +#define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA) +#define BITS_CAMW_DATA (BIT_MASK_CAMW_DATA << BIT_SHIFT_CAMW_DATA) +#define BIT_CLEAR_CAMW_DATA(x) ((x) & (~BITS_CAMW_DATA)) +#define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA) +#define BIT_SET_CAMW_DATA(x, v) (BIT_CLEAR_CAMW_DATA(x) | BIT_CAMW_DATA(v)) -/* 2 REG_SYS_CFG5 (Offset 0x1070) */ +/* 2 REG_CAMREAD (Offset 0x0678) */ -#define BIT_LPS_STATUS BIT(3) -#define BIT_HCI_TXDMA_BUSY BIT(2) -#define BIT_HCI_TXDMA_ALLOW BIT(1) -#define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0) +#define BIT_SHIFT_CAMR_DATA 0 +#define BIT_MASK_CAMR_DATA 0xffffffffL +#define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA) +#define BITS_CAMR_DATA (BIT_MASK_CAMR_DATA << BIT_SHIFT_CAMR_DATA) +#define BIT_CLEAR_CAMR_DATA(x) ((x) & (~BITS_CAMR_DATA)) +#define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA) +#define BIT_SET_CAMR_DATA(x, v) (BIT_CLEAR_CAMR_DATA(x) | BIT_CAMR_DATA(v)) -#endif +/* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_SECCAM_INFO BIT(31) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +/* 2 REG_CAMDBG (Offset 0x067C) */ + +#define BIT_SEC_KEYFOUND_V1 BIT(19) -#define BIT_WDT_AUTO_MODE BIT(22) -#define BIT_WDT_PLATFORM_EN BIT(21) -#define BIT_WDT_CPU_EN BIT(20) +#define BIT_SHIFT_CAMDBG_SEC_TYPE_V1 16 +#define BIT_MASK_CAMDBG_SEC_TYPE_V1 0x7 +#define BIT_CAMDBG_SEC_TYPE_V1(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_V1) << BIT_SHIFT_CAMDBG_SEC_TYPE_V1) +#define BITS_CAMDBG_SEC_TYPE_V1 \ + (BIT_MASK_CAMDBG_SEC_TYPE_V1 << BIT_SHIFT_CAMDBG_SEC_TYPE_V1) +#define BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_V1)) +#define BIT_GET_CAMDBG_SEC_TYPE_V1(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_V1) & BIT_MASK_CAMDBG_SEC_TYPE_V1) +#define BIT_SET_CAMDBG_SEC_TYPE_V1(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) | BIT_CAMDBG_SEC_TYPE_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_SEC_KEYFOUND BIT(15) -/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +#endif -#define BIT_WDT_OPT_IOWRAPPER BIT(19) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_CAMDBG_EXT_SEC_TYPE_V1 BIT(15) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +/* 2 REG_CAMDBG (Offset 0x067C) */ -#define BIT_ANA_PORT_IDLE BIT(18) -#define BIT_MAC_PORT_IDLE BIT(17) -#define BIT_WL_PLATFORM_RST BIT(16) -#define BIT_WL_SECURITY_CLK BIT(15) +#define BIT_SHIFT_CAMDBG_SEC_TYPE 12 +#define BIT_MASK_CAMDBG_SEC_TYPE 0x7 +#define BIT_CAMDBG_SEC_TYPE(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE) +#define BITS_CAMDBG_SEC_TYPE \ + (BIT_MASK_CAMDBG_SEC_TYPE << BIT_SHIFT_CAMDBG_SEC_TYPE) +#define BIT_CLEAR_CAMDBG_SEC_TYPE(x) ((x) & (~BITS_CAMDBG_SEC_TYPE)) +#define BIT_GET_CAMDBG_SEC_TYPE(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE) +#define BIT_SET_CAMDBG_SEC_TYPE(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE(x) | BIT_CAMDBG_SEC_TYPE(v)) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_CAMDBG_EXT_SEC_TYPE BIT(11) -/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_CPU_DMEM_CON 0 -#define BIT_MASK_CPU_DMEM_CON 0xff -#define BIT_CPU_DMEM_CON(x) (((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON) -#define BIT_GET_CPU_DMEM_CON(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON) +/* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_CAMDBG_EXT_SECTYPE BIT(11) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1 7 +#define BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 0x7f +#define BIT_CAMDBG_MIC_KEY_IDX_V1(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_V1) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) +#define BITS_CAMDBG_MIC_KEY_IDX_V1 \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_V1)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_V1(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_V1) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_V1(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) | BIT_CAMDBG_MIC_KEY_IDX_V1(v)) -/* 2 REG_BOOT_REASON (Offset 0x1088) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_BOOT_REASON 0 -#define BIT_MASK_BOOT_REASON 0x7 -#define BIT_BOOT_REASON(x) (((x) & BIT_MASK_BOOT_REASON) << BIT_SHIFT_BOOT_REASON) -#define BIT_GET_BOOT_REASON(x) (((x) >> BIT_SHIFT_BOOT_REASON) & BIT_MASK_BOOT_REASON) +/* 2 REG_CAMDBG (Offset 0x067C) */ +#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5 +#define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f +#define BIT_CAMDBG_MIC_KEY_IDX(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX) +#define BITS_CAMDBG_MIC_KEY_IDX \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX << BIT_SHIFT_CAMDBG_MIC_KEY_IDX) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX) +#define BIT_SET_CAMDBG_MIC_KEY_IDX(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) | BIT_CAMDBG_MIC_KEY_IDX(v)) + +#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0 +#define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f +#define BIT_CAMDBG_SEC_KEY_IDX(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX) +#define BITS_CAMDBG_SEC_KEY_IDX \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX << BIT_SHIFT_CAMDBG_SEC_KEY_IDX) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX) +#define BIT_SET_CAMDBG_SEC_KEY_IDX(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) | BIT_CAMDBG_SEC_KEY_IDX(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_NFCPAD_CTRL (Offset 0x10A8) */ +/* 2 REG_CAMDBG (Offset 0x067C) */ -#define BIT_PAD_SHUTDW BIT(18) -#define BIT_SYSON_NFC_PAD BIT(17) -#define BIT_NFC_INT_PAD_CTRL BIT(16) -#define BIT_NFC_RFDIS_PAD_CTRL BIT(15) -#define BIT_NFC_CLK_PAD_CTRL BIT(14) -#define BIT_NFC_DATA_PAD_CTRL BIT(13) -#define BIT_NFC_PAD_PULL_CTRL BIT(12) +#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1 0 +#define BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 0x7f +#define BIT_CAMDBG_SEC_KEY_IDX_V1(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_V1) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) +#define BITS_CAMDBG_SEC_KEY_IDX_V1 \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_V1)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_V1(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_V1) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_V1(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) | BIT_CAMDBG_SEC_KEY_IDX_V1(v)) -#define BIT_SHIFT_NFCPAD_IO_SEL 8 -#define BIT_MASK_NFCPAD_IO_SEL 0xf -#define BIT_NFCPAD_IO_SEL(x) (((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL) -#define BIT_GET_NFCPAD_IO_SEL(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_NFCPAD_OUT 4 -#define BIT_MASK_NFCPAD_OUT 0xf -#define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT) -#define BIT_GET_NFCPAD_OUT(x) (((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT) +/* 2 REG_SECCFG (Offset 0x0680) */ +#define BIT_RXDEC_BM_MGNT_V1 BIT(19) +#define BIT_TXENC_BM_MGNT_V1 BIT(18) +#define BIT_RXDEC_UNI_MGNT_V1 BIT(17) +#define BIT_TXENC_UNI_MGNT_V1 BIT(16) -#define BIT_SHIFT_NFCPAD_IN 0 -#define BIT_MASK_NFCPAD_IN 0xf -#define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN) -#define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_SECCFG (Offset 0x0680) */ +#define BIT_DIS_GCLK_WAPI BIT(15) +#define BIT_DIS_GCLK_AES BIT(14) +#define BIT_DIS_GCLK_TKIP BIT(13) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_HIMR2 (Offset 0x10B0) */ +/* 2 REG_SECCFG (Offset 0x0680) */ -#define BIT_BCNDMAINT_P4_MSK BIT(31) -#define BIT_BCNDMAINT_P3_MSK BIT(30) -#define BIT_BCNDMAINT_P2_MSK BIT(29) -#define BIT_BCNDMAINT_P1_MSK BIT(28) -#define BIT_ATIMEND7_MSK BIT(22) -#define BIT_ATIMEND6_MSK BIT(21) -#define BIT_ATIMEND5_MSK BIT(20) -#define BIT_ATIMEND4_MSK BIT(19) -#define BIT_ATIMEND3_MSK BIT(18) -#define BIT_ATIMEND2_MSK BIT(17) -#define BIT_ATIMEND1_MSK BIT(16) -#define BIT_TXBCN7OK_MSK BIT(14) -#define BIT_TXBCN6OK_MSK BIT(13) -#define BIT_TXBCN5OK_MSK BIT(12) -#define BIT_TXBCN4OK_MSK BIT(11) -#define BIT_TXBCN3OK_MSK BIT(10) -#define BIT_TXBCN2OK_MSK BIT(9) -#define BIT_TXBCN1OK_MSK_V1 BIT(8) -#define BIT_TXBCN7ERR_MSK BIT(6) -#define BIT_TXBCN6ERR_MSK BIT(5) -#define BIT_TXBCN5ERR_MSK BIT(4) -#define BIT_TXBCN4ERR_MSK BIT(3) -#define BIT_TXBCN3ERR_MSK BIT(2) -#define BIT_TXBCN2ERR_MSK BIT(1) -#define BIT_TXBCN1ERR_MSK_V1 BIT(0) - -/* 2 REG_HISR2 (Offset 0x10B4) */ - -#define BIT_BCNDMAINT_P4 BIT(31) -#define BIT_BCNDMAINT_P3 BIT(30) -#define BIT_BCNDMAINT_P2 BIT(29) -#define BIT_BCNDMAINT_P1 BIT(28) -#define BIT_ATIMEND7 BIT(22) -#define BIT_ATIMEND6 BIT(21) -#define BIT_ATIMEND5 BIT(20) -#define BIT_ATIMEND4 BIT(19) -#define BIT_ATIMEND3 BIT(18) -#define BIT_ATIMEND2 BIT(17) -#define BIT_ATIMEND1 BIT(16) -#define BIT_TXBCN7OK BIT(14) -#define BIT_TXBCN6OK BIT(13) -#define BIT_TXBCN5OK BIT(12) -#define BIT_TXBCN4OK BIT(11) -#define BIT_TXBCN3OK BIT(10) -#define BIT_TXBCN2OK BIT(9) -#define BIT_TXBCN1OK BIT(8) -#define BIT_TXBCN7ERR BIT(6) -#define BIT_TXBCN6ERR BIT(5) -#define BIT_TXBCN5ERR BIT(4) -#define BIT_TXBCN4ERR BIT(3) -#define BIT_TXBCN3ERR BIT(2) -#define BIT_TXBCN2ERR BIT(1) -#define BIT_TXBCN1ERR BIT(0) +#define BIT_AES_SEL_QC_1 BIT(12) +#define BIT_AES_SEL_QC_0 BIT(11) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SECCFG (Offset 0x0680) */ +#define BIT_WMAC_CKECK_BMC BIT(9) -/* 2 REG_HIMR3 (Offset 0x10B8) */ +#endif -#define BIT_WDT_PLATFORM_INT_MSK BIT(18) -#define BIT_WDT_CPU_INT_MSK BIT(17) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SECCFG (Offset 0x0680) */ +#define BIT_CHK_BMC BIT(9) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_HIMR3 (Offset 0x10B8) */ +/* 2 REG_SECCFG (Offset 0x0680) */ -#define BIT_SETH2CDOK_MASK BIT(16) -#define BIT_H2C_CMD_FULL_MASK BIT(15) -#define BIT_PWR_INT_127_MASK BIT(14) -#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13) -#define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12) -#define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11) -#define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10) -#define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9) -#define BIT_PWR_INT_127_MASK_V1 BIT(8) -#define BIT_PWR_INT_126TO96_MASK BIT(7) -#define BIT_PWR_INT_95TO64_MASK BIT(6) -#define BIT_PWR_INT_63TO32_MASK BIT(5) -#define BIT_PWR_INT_31TO0_MASK BIT(4) -#define BIT_DDMA0_LP_INT_MSK BIT(1) -#define BIT_DDMA0_HP_INT_MSK BIT(0) +#define BIT_CHK_KEYID BIT(8) +#define BIT_RXBCUSEDK BIT(7) +#define BIT_TXBCUSEDK BIT(6) +#define BIT_NOSKMC BIT(5) +#define BIT_SKBYA2 BIT(4) +#define BIT_RXDEC BIT(3) +#define BIT_TXENC BIT(2) +#define BIT_RXUHUSEDK BIT(1) +#define BIT_TXUHUSEDK BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RXFILTER_CATEGORY_1 (Offset 0x0682) */ +#define BIT_SHIFT_RXFILTER_CATEGORY_1 0 +#define BIT_MASK_RXFILTER_CATEGORY_1 0xff +#define BIT_RXFILTER_CATEGORY_1(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1) +#define BITS_RXFILTER_CATEGORY_1 \ + (BIT_MASK_RXFILTER_CATEGORY_1 << BIT_SHIFT_RXFILTER_CATEGORY_1) +#define BIT_CLEAR_RXFILTER_CATEGORY_1(x) ((x) & (~BITS_RXFILTER_CATEGORY_1)) +#define BIT_GET_RXFILTER_CATEGORY_1(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1) +#define BIT_SET_RXFILTER_CATEGORY_1(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1(x) | BIT_RXFILTER_CATEGORY_1(v)) -/* 2 REG_HISR3 (Offset 0x10BC) */ +/* 2 REG_RXFILTER_ACTION_1 (Offset 0x0683) */ -#define BIT_WDT_PLATFORM_INT BIT(18) -#define BIT_WDT_CPU_INT BIT(17) +#define BIT_SHIFT_RXFILTER_ACTION_1 0 +#define BIT_MASK_RXFILTER_ACTION_1 0xff +#define BIT_RXFILTER_ACTION_1(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1) +#define BITS_RXFILTER_ACTION_1 \ + (BIT_MASK_RXFILTER_ACTION_1 << BIT_SHIFT_RXFILTER_ACTION_1) +#define BIT_CLEAR_RXFILTER_ACTION_1(x) ((x) & (~BITS_RXFILTER_ACTION_1)) +#define BIT_GET_RXFILTER_ACTION_1(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1) +#define BIT_SET_RXFILTER_ACTION_1(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1(x) | BIT_RXFILTER_ACTION_1(v)) -#endif +/* 2 REG_RXFILTER_CATEGORY_2 (Offset 0x0684) */ +#define BIT_SHIFT_RXFILTER_CATEGORY_2 0 +#define BIT_MASK_RXFILTER_CATEGORY_2 0xff +#define BIT_RXFILTER_CATEGORY_2(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2) +#define BITS_RXFILTER_CATEGORY_2 \ + (BIT_MASK_RXFILTER_CATEGORY_2 << BIT_SHIFT_RXFILTER_CATEGORY_2) +#define BIT_CLEAR_RXFILTER_CATEGORY_2(x) ((x) & (~BITS_RXFILTER_CATEGORY_2)) +#define BIT_GET_RXFILTER_CATEGORY_2(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2) +#define BIT_SET_RXFILTER_CATEGORY_2(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2(x) | BIT_RXFILTER_CATEGORY_2(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RXFILTER_ACTION_2 (Offset 0x0685) */ +#define BIT_SHIFT_RXFILTER_ACTION_2 0 +#define BIT_MASK_RXFILTER_ACTION_2 0xff +#define BIT_RXFILTER_ACTION_2(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2) +#define BITS_RXFILTER_ACTION_2 \ + (BIT_MASK_RXFILTER_ACTION_2 << BIT_SHIFT_RXFILTER_ACTION_2) +#define BIT_CLEAR_RXFILTER_ACTION_2(x) ((x) & (~BITS_RXFILTER_ACTION_2)) +#define BIT_GET_RXFILTER_ACTION_2(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2) +#define BIT_SET_RXFILTER_ACTION_2(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2(x) | BIT_RXFILTER_ACTION_2(v)) -/* 2 REG_HISR3 (Offset 0x10BC) */ +/* 2 REG_RXFILTER_CATEGORY_3 (Offset 0x0686) */ -#define BIT_SETH2CDOK BIT(16) -#define BIT_H2C_CMD_FULL BIT(15) -#define BIT_PWR_INT_127 BIT(14) -#define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13) -#define BIT_TXSHORTCUT_BKUPDATEOK BIT(12) -#define BIT_TXSHORTCUT_BEUPDATEOK BIT(11) -#define BIT_TXSHORTCUT_VIUPDATEOK BIT(10) -#define BIT_TXSHORTCUT_VOUPDATEOK BIT(9) -#define BIT_PWR_INT_127_V1 BIT(8) -#define BIT_PWR_INT_126TO96 BIT(7) -#define BIT_PWR_INT_95TO64 BIT(6) -#define BIT_PWR_INT_63TO32 BIT(5) -#define BIT_PWR_INT_31TO0 BIT(4) -#define BIT_DDMA0_LP_INT BIT(1) -#define BIT_DDMA0_HP_INT BIT(0) +#define BIT_SHIFT_RXFILTER_CATEGORY_3 0 +#define BIT_MASK_RXFILTER_CATEGORY_3 0xff +#define BIT_RXFILTER_CATEGORY_3(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3) +#define BITS_RXFILTER_CATEGORY_3 \ + (BIT_MASK_RXFILTER_CATEGORY_3 << BIT_SHIFT_RXFILTER_CATEGORY_3) +#define BIT_CLEAR_RXFILTER_CATEGORY_3(x) ((x) & (~BITS_RXFILTER_CATEGORY_3)) +#define BIT_GET_RXFILTER_CATEGORY_3(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3) +#define BIT_SET_RXFILTER_CATEGORY_3(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3(x) | BIT_RXFILTER_CATEGORY_3(v)) -#endif +/* 2 REG_RXFILTER_ACTION_3 (Offset 0x0687) */ +#define BIT_SHIFT_RXFILTER_ACTION_3 0 +#define BIT_MASK_RXFILTER_ACTION_3 0xff +#define BIT_RXFILTER_ACTION_3(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3) +#define BITS_RXFILTER_ACTION_3 \ + (BIT_MASK_RXFILTER_ACTION_3 << BIT_SHIFT_RXFILTER_ACTION_3) +#define BIT_CLEAR_RXFILTER_ACTION_3(x) ((x) & (~BITS_RXFILTER_ACTION_3)) +#define BIT_GET_RXFILTER_ACTION_3(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3) +#define BIT_SET_RXFILTER_ACTION_3(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3(x) | BIT_RXFILTER_ACTION_3(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RXFLTMAP3 (Offset 0x0688) */ +#define BIT_MGTFLT15EN_FW BIT(15) +#define BIT_MGTFLT14EN_FW BIT(14) +#define BIT_MGTFLT13EN_FW BIT(13) +#define BIT_MGTFLT12EN_FW BIT(12) +#define BIT_MGTFLT11EN_FW BIT(11) +#define BIT_MGTFLT10EN_FW BIT(10) +#define BIT_MGTFLT9EN_FW BIT(9) +#define BIT_MGTFLT8EN_FW BIT(8) +#define BIT_MGTFLT7EN_FW BIT(7) +#define BIT_MGTFLT6EN_FW BIT(6) +#define BIT_MGTFLT5EN_FW BIT(5) +#define BIT_MGTFLT4EN_FW BIT(4) +#define BIT_MGTFLT3EN_FW BIT(3) +#define BIT_MGTFLT2EN_FW BIT(2) +#define BIT_MGTFLT1EN_FW BIT(1) +#define BIT_MGTFLT0EN_FW BIT(0) -/* 2 REG_SW_MDIO (Offset 0x10C0) */ +/* 2 REG_RXFLTMAP4 (Offset 0x068A) */ -#define BIT_DIS_TIMEOUT_IO BIT(24) +#define BIT_CTRLFLT15EN_FW BIT(15) +#define BIT_CTRLFLT14EN_FW BIT(14) +#define BIT_CTRLFLT13EN_FW BIT(13) +#define BIT_CTRLFLT12EN_FW BIT(12) +#define BIT_CTRLFLT11EN_FW BIT(11) +#define BIT_CTRLFLT10EN_FW BIT(10) +#define BIT_CTRLFLT9EN_FW BIT(9) +#define BIT_CTRLFLT8EN_FW BIT(8) +#define BIT_CTRLFLT7EN_FW BIT(7) +#define BIT_CTRLFLT6EN_FW BIT(6) +#define BIT_CTRLFLT5EN_FW BIT(5) +#define BIT_CTRLFLT4EN_FW BIT(4) +#define BIT_CTRLFLT3EN_FW BIT(3) +#define BIT_CTRLFLT2EN_FW BIT(2) +#define BIT_CTRLFLT1EN_FW BIT(1) +#define BIT_CTRLFLT0EN_FW BIT(0) -#endif +/* 2 REG_RXFLTMAP5 (Offset 0x068C) */ +#define BIT_DATAFLT15EN_FW BIT(15) +#define BIT_DATAFLT14EN_FW BIT(14) +#define BIT_DATAFLT13EN_FW BIT(13) +#define BIT_DATAFLT12EN_FW BIT(12) +#define BIT_DATAFLT11EN_FW BIT(11) +#define BIT_DATAFLT10EN_FW BIT(10) +#define BIT_DATAFLT9EN_FW BIT(9) +#define BIT_DATAFLT8EN_FW BIT(8) +#define BIT_DATAFLT7EN_FW BIT(7) +#define BIT_DATAFLT6EN_FW BIT(6) +#define BIT_DATAFLT5EN_FW BIT(5) +#define BIT_DATAFLT4EN_FW BIT(4) +#define BIT_DATAFLT3EN_FW BIT(3) +#define BIT_DATAFLT2EN_FW BIT(2) +#define BIT_DATAFLT1EN_FW BIT(1) +#define BIT_DATAFLT0EN_FW BIT(0) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_RXFLTMAP6 (Offset 0x068E) */ +#define BIT_ACTIONFLT15EN_FW BIT(15) +#define BIT_ACTIONFLT14EN_FW BIT(14) +#define BIT_ACTIONFLT13EN_FW BIT(13) +#define BIT_ACTIONFLT12EN_FW BIT(12) +#define BIT_ACTIONFLT11EN_FW BIT(11) +#define BIT_ACTIONFLT10EN_FW BIT(10) +#define BIT_ACTIONFLT9EN_FW BIT(9) +#define BIT_ACTIONFLT8EN_FW BIT(8) +#define BIT_ACTIONFLT7EN_FW BIT(7) +#define BIT_ACTIONFLT6EN_FW BIT(6) +#define BIT_ACTIONFLT5EN_FW BIT(5) +#define BIT_ACTIONFLT4EN_FW BIT(4) +#define BIT_ACTIONFLT3EN_FW BIT(3) +#define BIT_ACTIONFLT2EN_FW BIT(2) +#define BIT_ACTIONFLT1EN_FW BIT(1) +#define BIT_ACTIONFLT0EN_FW BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_SW_MDIO (Offset 0x10C0) */ +/* 2 REG_WOW_CTRL (Offset 0x0690) */ -#define BIT_SUS_PL BIT(18) -#define BIT_SOP_ESUS BIT(17) -#define BIT_SOP_DLDO BIT(16) -#define BIT_R_OCP_ST_CLR BIT(8) -#define BIT_SW_USB3_MD_SEL BIT(5) -#define BIT_SW_PCIE_MD_SEL BIT(4) -#define BIT_SW_MDCK BIT(2) -#define BIT_SW_MDI BIT(1) -#define BIT_MDO BIT(0) +#define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6 +#define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3 +#define BIT_PSF_BSSIDSEL_B2B1(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1) +#define BITS_PSF_BSSIDSEL_B2B1 \ + (BIT_MASK_PSF_BSSIDSEL_B2B1 << BIT_SHIFT_PSF_BSSIDSEL_B2B1) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) ((x) & (~BITS_PSF_BSSIDSEL_B2B1)) +#define BIT_GET_PSF_BSSIDSEL_B2B1(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1) +#define BIT_SET_PSF_BSSIDSEL_B2B1(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) | BIT_PSF_BSSIDSEL_B2B1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WOW_CTRL (Offset 0x0690) */ +#define BIT_WOWHCI BIT(5) -/* 2 REG_SW_FLUSH (Offset 0x10C4) */ +#endif -#define BIT_FLUSH_HOLDN_EN BIT(25) -#define BIT_FLUSH_WR_EN BIT(24) -#define BIT_SW_FLASH_CONTROL BIT(23) -#define BIT_SW_FLASH_WEN_E BIT(19) -#define BIT_SW_FLASH_HOLDN_E BIT(18) -#define BIT_SW_FLASH_SO_E BIT(17) -#define BIT_SW_FLASH_SI_E BIT(16) -#define BIT_SW_FLASH_SK_O BIT(13) -#define BIT_SW_FLASH_CEN_O BIT(12) -#define BIT_SW_FLASH_WEN_O BIT(11) -#define BIT_SW_FLASH_HOLDN_O BIT(10) -#define BIT_SW_FLASH_SO_O BIT(9) -#define BIT_SW_FLASH_SI_O BIT(8) -#define BIT_SW_FLASH_WEN_I BIT(3) -#define BIT_SW_FLASH_HOLDN_I BIT(2) -#define BIT_SW_FLASH_SO_I BIT(1) -#define BIT_SW_FLASH_SI_I BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_WOW_CTRL (Offset 0x0690) */ +#define BIT_PSF_BSSIDSEL BIT(4) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ +/* 2 REG_WOW_CTRL (Offset 0x0690) */ +#define BIT_PSF_BSSIDSEL_B0 BIT(4) -#define BIT_SHIFT_DBG_GPIO_BMUX_7 21 -#define BIT_MASK_DBG_GPIO_BMUX_7 0x7 -#define BIT_DBG_GPIO_BMUX_7(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_7) << BIT_SHIFT_DBG_GPIO_BMUX_7) -#define BIT_GET_DBG_GPIO_BMUX_7(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7) & BIT_MASK_DBG_GPIO_BMUX_7) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DBG_GPIO_BMUX_6 18 -#define BIT_MASK_DBG_GPIO_BMUX_6 0x7 -#define BIT_DBG_GPIO_BMUX_6(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_6) << BIT_SHIFT_DBG_GPIO_BMUX_6) -#define BIT_GET_DBG_GPIO_BMUX_6(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6) & BIT_MASK_DBG_GPIO_BMUX_6) +/* 2 REG_WOW_CTRL (Offset 0x0690) */ +#define BIT_UWF BIT(3) +#define BIT_MAGIC BIT(2) -#define BIT_SHIFT_DBG_GPIO_BMUX_5 15 -#define BIT_MASK_DBG_GPIO_BMUX_5 0x7 -#define BIT_DBG_GPIO_BMUX_5(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_5) << BIT_SHIFT_DBG_GPIO_BMUX_5) -#define BIT_GET_DBG_GPIO_BMUX_5(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5) & BIT_MASK_DBG_GPIO_BMUX_5) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DBG_GPIO_BMUX_4 12 -#define BIT_MASK_DBG_GPIO_BMUX_4 0x7 -#define BIT_DBG_GPIO_BMUX_4(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_4) << BIT_SHIFT_DBG_GPIO_BMUX_4) -#define BIT_GET_DBG_GPIO_BMUX_4(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4) & BIT_MASK_DBG_GPIO_BMUX_4) +/* 2 REG_WOW_CTRL (Offset 0x0690) */ +#define BIT_WOWEN BIT(1) -#define BIT_SHIFT_DBG_GPIO_BMUX_3 9 -#define BIT_MASK_DBG_GPIO_BMUX_3 0x7 -#define BIT_DBG_GPIO_BMUX_3(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_3) << BIT_SHIFT_DBG_GPIO_BMUX_3) -#define BIT_GET_DBG_GPIO_BMUX_3(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3) & BIT_MASK_DBG_GPIO_BMUX_3) +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_DBG_GPIO_BMUX_2 6 -#define BIT_MASK_DBG_GPIO_BMUX_2 0x7 -#define BIT_DBG_GPIO_BMUX_2(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_2) << BIT_SHIFT_DBG_GPIO_BMUX_2) -#define BIT_GET_DBG_GPIO_BMUX_2(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2) & BIT_MASK_DBG_GPIO_BMUX_2) +/* 2 REG_WOW_CTRL (Offset 0x0690) */ +#define BIT_WFMSK BIT(1) -#define BIT_SHIFT_DBG_GPIO_BMUX_1 3 -#define BIT_MASK_DBG_GPIO_BMUX_1 0x7 -#define BIT_DBG_GPIO_BMUX_1(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_1) << BIT_SHIFT_DBG_GPIO_BMUX_1) -#define BIT_GET_DBG_GPIO_BMUX_1(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1) & BIT_MASK_DBG_GPIO_BMUX_1) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_DBG_GPIO_BMUX_0 0 -#define BIT_MASK_DBG_GPIO_BMUX_0 0x7 -#define BIT_DBG_GPIO_BMUX_0(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_0) << BIT_SHIFT_DBG_GPIO_BMUX_0) -#define BIT_GET_DBG_GPIO_BMUX_0(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0) & BIT_MASK_DBG_GPIO_BMUX_0) +/* 2 REG_WOW_CTRL (Offset 0x0690) */ +#define BIT_FORCE_WAKEUP BIT(0) -/* 2 REG_FPGA_TAG (Offset 0x10CC) */ +#endif -#define BIT_WL_DSS_RSTN BIT(27) -#define BIT_WL_DSS_EN_CLK BIT(26) -#define BIT_WL_DSS_SPEED_EN BIT(25) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FPGA_TAG 0 -#define BIT_MASK_FPGA_TAG 0xffffffffL -#define BIT_FPGA_TAG(x) (((x) & BIT_MASK_FPGA_TAG) << BIT_SHIFT_FPGA_TAG) -#define BIT_GET_FPGA_TAG(x) (((x) >> BIT_SHIFT_FPGA_TAG) & BIT_MASK_FPGA_TAG) +/* 2 REG_NAN_RX_TSF_FILTER (Offset 0x0691) */ +#define BIT_CHK_TSF_TA BIT(2) +#define BIT_CHK_TSF_CBSSID BIT(1) +#define BIT_CHK_TSF_EN BIT(0) -#define BIT_SHIFT_WL_DSS_COUNT_OUT 0 -#define BIT_MASK_WL_DSS_COUNT_OUT 0xfffff -#define BIT_WL_DSS_COUNT_OUT(x) (((x) & BIT_MASK_WL_DSS_COUNT_OUT) << BIT_SHIFT_WL_DSS_COUNT_OUT) -#define BIT_GET_WL_DSS_COUNT_OUT(x) (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT) & BIT_MASK_WL_DSS_COUNT_OUT) +/* 2 REG_PS_RX_INFO (Offset 0x0692) */ +#define BIT_SHIFT_PORTSEL__PS_RX_INFO 5 +#define BIT_MASK_PORTSEL__PS_RX_INFO 0x7 +#define BIT_PORTSEL__PS_RX_INFO(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO) +#define BITS_PORTSEL__PS_RX_INFO \ + (BIT_MASK_PORTSEL__PS_RX_INFO << BIT_SHIFT_PORTSEL__PS_RX_INFO) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO(x) ((x) & (~BITS_PORTSEL__PS_RX_INFO)) +#define BIT_GET_PORTSEL__PS_RX_INFO(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO) +#define BIT_SET_PORTSEL__PS_RX_INFO(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO(x) | BIT_PORTSEL__PS_RX_INFO(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PS_RX_INFO (Offset 0x0692) */ +#define BIT_RXCTRLIN0 BIT(4) +#define BIT_RXMGTIN0 BIT(3) +#define BIT_RXDATAIN2 BIT(2) +#define BIT_RXDATAIN1 BIT(1) +#define BIT_RXDATAIN0 BIT(0) -/* 2 REG_H2C_PKT_READADDR (Offset 0x10D0) */ +/* 2 REG_WMMPS_UAPSD_TID (Offset 0x0693) */ +#define BIT_SHIFT_DTIM_CNT 24 +#define BIT_MASK_DTIM_CNT 0xff +#define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT) +#define BITS_DTIM_CNT (BIT_MASK_DTIM_CNT << BIT_SHIFT_DTIM_CNT) +#define BIT_CLEAR_DTIM_CNT(x) ((x) & (~BITS_DTIM_CNT)) +#define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT) +#define BIT_SET_DTIM_CNT(x, v) (BIT_CLEAR_DTIM_CNT(x) | BIT_DTIM_CNT(v)) + +#define BIT_CTRLFLT15EN BIT(15) +#define BIT_DATAFLT15EN BIT(15) +#define BIT_CTRLFLT14EN BIT(14) +#define BIT_DATAFLT14EN BIT(14) +#define BIT_MGTFLT13EN BIT(13) +#define BIT_CTRLFLT13EN BIT(13) +#define BIT_DATAFLT13EN BIT(13) +#define BIT_MGTFLT12EN BIT(12) +#define BIT_CTRLFLT12EN BIT(12) +#define BIT_DATAFLT12EN BIT(12) +#define BIT_MGTFLT11EN BIT(11) +#define BIT_CTRLFLT11EN BIT(11) +#define BIT_DATAFLT11EN BIT(11) +#define BIT_MGTFLT10EN BIT(10) +#define BIT_CTRLFLT10EN BIT(10) +#define BIT_DATAFLT10EN BIT(10) +#define BIT_MGTFLT9EN BIT(9) +#define BIT_CTRLFLT9EN BIT(9) +#define BIT_DATAFLT9EN BIT(9) +#define BIT_MGTFLT8EN BIT(8) +#define BIT_CTRLFLT8EN BIT(8) +#define BIT_DATAFLT8EN BIT(8) +#define BIT_WMMPS_UAPSD_TID7 BIT(7) +#define BIT_CTRLFLT7EN BIT(7) +#define BIT_DATAFLT7EN BIT(7) +#define BIT_WMMPS_UAPSD_TID6 BIT(6) +#define BIT_CTRLFLT6EN BIT(6) +#define BIT_DATAFLT6EN BIT(6) +#define BIT_WMMPS_UAPSD_TID5 BIT(5) +#define BIT_MGTFLT5EN BIT(5) +#define BIT_DATAFLT5EN BIT(5) +#define BIT_WMMPS_UAPSD_TID4 BIT(4) +#define BIT_MGTFLT4EN BIT(4) +#define BIT_DATAFLT4EN BIT(4) +#define BIT_WMMPS_UAPSD_TID3 BIT(3) +#define BIT_MGTFLT3EN BIT(3) +#define BIT_DATAFLT3EN BIT(3) +#define BIT_WMMPS_UAPSD_TID2 BIT(2) +#define BIT_MGTFLT2EN BIT(2) +#define BIT_DATAFLT2EN BIT(2) +#define BIT_WMMPS_UAPSD_TID1 BIT(1) +#define BIT_MGTFLT1EN BIT(1) +#define BIT_DATAFLT1EN BIT(1) +#define BIT_WMMPS_UAPSD_TID0 BIT(0) +#define BIT_MGTFLT0EN BIT(0) +#define BIT_DATAFLT0EN BIT(0) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_H2C_PKT_READADDR 0 -#define BIT_MASK_H2C_PKT_READADDR 0x3ffff -#define BIT_H2C_PKT_READADDR(x) (((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR) -#define BIT_GET_H2C_PKT_READADDR(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR) +/* 2 REG_LPNAV_CTRL (Offset 0x0694) */ +#define BIT_LPNAV_EN BIT(31) -/* 2 REG_H2C_PKT_WRITEADDR (Offset 0x10D4) */ +#define BIT_SHIFT_LPNAV_EARLY 16 +#define BIT_MASK_LPNAV_EARLY 0x7fff +#define BIT_LPNAV_EARLY(x) \ + (((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY) +#define BITS_LPNAV_EARLY (BIT_MASK_LPNAV_EARLY << BIT_SHIFT_LPNAV_EARLY) +#define BIT_CLEAR_LPNAV_EARLY(x) ((x) & (~BITS_LPNAV_EARLY)) +#define BIT_GET_LPNAV_EARLY(x) \ + (((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY) +#define BIT_SET_LPNAV_EARLY(x, v) \ + (BIT_CLEAR_LPNAV_EARLY(x) | BIT_LPNAV_EARLY(v)) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_H2C_PKT_WRITEADDR 0 -#define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff -#define BIT_H2C_PKT_WRITEADDR(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR) -#define BIT_GET_H2C_PKT_WRITEADDR(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR) +/* 2 REG_LPNAV_CTRL (Offset 0x0694) */ +#define BIT_SHIFT_LPNAV_TH 0 +#define BIT_MASK_LPNAV_TH 0xffff +#define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH) +#define BITS_LPNAV_TH (BIT_MASK_LPNAV_TH << BIT_SHIFT_LPNAV_TH) +#define BIT_CLEAR_LPNAV_TH(x) ((x) & (~BITS_LPNAV_TH)) +#define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH) +#define BIT_SET_LPNAV_TH(x, v) (BIT_CLEAR_LPNAV_TH(x) | BIT_LPNAV_TH(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_LPNAV_CTRL (Offset 0x0694) */ +#define BIT_SHIFT_LPNAV_THR 0 +#define BIT_MASK_LPNAV_THR 0xffff +#define BIT_LPNAV_THR(x) (((x) & BIT_MASK_LPNAV_THR) << BIT_SHIFT_LPNAV_THR) +#define BITS_LPNAV_THR (BIT_MASK_LPNAV_THR << BIT_SHIFT_LPNAV_THR) +#define BIT_CLEAR_LPNAV_THR(x) ((x) & (~BITS_LPNAV_THR)) +#define BIT_GET_LPNAV_THR(x) (((x) >> BIT_SHIFT_LPNAV_THR) & BIT_MASK_LPNAV_THR) +#define BIT_SET_LPNAV_THR(x, v) (BIT_CLEAR_LPNAV_THR(x) | BIT_LPNAV_THR(v)) -/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ +#endif -#define BIT_WL_DSS_WIRE_SEL BIT(24) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WL_DSS_RO_SEL 20 -#define BIT_MASK_WL_DSS_RO_SEL 0x7 -#define BIT_WL_DSS_RO_SEL(x) (((x) & BIT_MASK_WL_DSS_RO_SEL) << BIT_SHIFT_WL_DSS_RO_SEL) -#define BIT_GET_WL_DSS_RO_SEL(x) (((x) >> BIT_SHIFT_WL_DSS_RO_SEL) & BIT_MASK_WL_DSS_RO_SEL) +/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +#define BIT_WKFCAM_POLLING_V1 BIT(31) +#define BIT_WKFCAM_CLR_V1 BIT(30) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +#define BIT_WKFCAM_WE BIT(16) -/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ +#endif -#define BIT_MEM_BB_SD BIT(17) -#define BIT_MEM_BB_DS BIT(16) -#define BIT_MEM_BT_DS BIT(10) -#define BIT_MEM_SDIO_LS BIT(9) -#define BIT_MEM_SDIO_DS BIT(8) -#define BIT_MEM_USB_LS BIT(7) -#define BIT_MEM_USB_DS BIT(6) -#define BIT_MEM_PCI_LS BIT(5) -#define BIT_MEM_PCI_DS BIT(4) -#define BIT_MEM_WLMAC_LS BIT(3) -#define BIT_MEM_WLMAC_DS BIT(2) -#define BIT_MEM_WLMCU_LS BIT(1) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +#define BIT_SHIFT_WKFCAM_ADDR_V2 8 +#define BIT_MASK_WKFCAM_ADDR_V2 0xff +#define BIT_WKFCAM_ADDR_V2(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) +#define BITS_WKFCAM_ADDR_V2 \ + (BIT_MASK_WKFCAM_ADDR_V2 << BIT_SHIFT_WKFCAM_ADDR_V2) +#define BIT_CLEAR_WKFCAM_ADDR_V2(x) ((x) & (~BITS_WKFCAM_ADDR_V2)) +#define BIT_GET_WKFCAM_ADDR_V2(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2) +#define BIT_SET_WKFCAM_ADDR_V2(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2(x) | BIT_WKFCAM_ADDR_V2(v)) + +#define BIT_WMAC_RESP_NONSTA1_DIS BIT(7) + +#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4 +#define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3 +#define BIT_WMAC_TXMU_ACKPOLICY(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY) +#define BITS_WMAC_TXMU_ACKPOLICY \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY << BIT_SHIFT_WMAC_TXMU_ACKPOLICY) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) ((x) & (~BITS_WMAC_TXMU_ACKPOLICY)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY) +#define BIT_SET_WMAC_TXMU_ACKPOLICY(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) | BIT_WMAC_TXMU_ACKPOLICY(v)) + +#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1 +#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7 +#define BIT_WMAC_MU_BFEE_PORT_SEL(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) +#define BITS_WMAC_MU_BFEE_PORT_SEL \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) | BIT_WMAC_MU_BFEE_PORT_SEL(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +#define BIT_SHIFT_WKFCAM_NUM_V1 0 +#define BIT_MASK_WKFCAM_NUM_V1 0xff +#define BIT_WKFCAM_NUM_V1(x) \ + (((x) & BIT_MASK_WKFCAM_NUM_V1) << BIT_SHIFT_WKFCAM_NUM_V1) +#define BITS_WKFCAM_NUM_V1 (BIT_MASK_WKFCAM_NUM_V1 << BIT_SHIFT_WKFCAM_NUM_V1) +#define BIT_CLEAR_WKFCAM_NUM_V1(x) ((x) & (~BITS_WKFCAM_NUM_V1)) +#define BIT_GET_WKFCAM_NUM_V1(x) \ + (((x) >> BIT_SHIFT_WKFCAM_NUM_V1) & BIT_MASK_WKFCAM_NUM_V1) +#define BIT_SET_WKFCAM_NUM_V1(x, v) \ + (BIT_CLEAR_WKFCAM_NUM_V1(x) | BIT_WKFCAM_NUM_V1(v)) -/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ -#define BIT_SHIFT_WL_DSS_DATA_IN 0 -#define BIT_MASK_WL_DSS_DATA_IN 0xfffff -#define BIT_WL_DSS_DATA_IN(x) (((x) & BIT_MASK_WL_DSS_DATA_IN) << BIT_SHIFT_WL_DSS_DATA_IN) -#define BIT_GET_WL_DSS_DATA_IN(x) (((x) >> BIT_SHIFT_WL_DSS_DATA_IN) & BIT_MASK_WL_DSS_DATA_IN) +#define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0 +#define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff +#define BIT_WKFCAM_CAM_NUM_V1(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1) +#define BITS_WKFCAM_CAM_NUM_V1 \ + (BIT_MASK_WKFCAM_CAM_NUM_V1 << BIT_SHIFT_WKFCAM_CAM_NUM_V1) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) ((x) & (~BITS_WKFCAM_CAM_NUM_V1)) +#define BIT_GET_WKFCAM_CAM_NUM_V1(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1) +#define BIT_SET_WKFCAM_CAM_NUM_V1(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) | BIT_WKFCAM_CAM_NUM_V1(v)) +#define BIT_WMAC_MU_BFEE_DIS BIT(0) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ +#define BIT_SHIFT_WKFCAM_ADDR 0 +#define BIT_MASK_WKFCAM_ADDR 0x7f +#define BIT_WKFCAM_ADDR(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR) << BIT_SHIFT_WKFCAM_ADDR) +#define BITS_WKFCAM_ADDR (BIT_MASK_WKFCAM_ADDR << BIT_SHIFT_WKFCAM_ADDR) +#define BIT_CLEAR_WKFCAM_ADDR(x) ((x) & (~BITS_WKFCAM_ADDR)) +#define BIT_GET_WKFCAM_ADDR(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR) & BIT_MASK_WKFCAM_ADDR) +#define BIT_SET_WKFCAM_ADDR(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR(x) | BIT_WKFCAM_ADDR(v)) -/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_WKFMCAM_RWD (Offset 0x069C) */ -#define BIT_MEM_WLMCU_DS BIT(0) +#define BIT_SHIFT_WKFMCAM_RWD 0 +#define BIT_MASK_WKFMCAM_RWD 0xffffffffL +#define BIT_WKFMCAM_RWD(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD) +#define BITS_WKFMCAM_RWD (BIT_MASK_WKFMCAM_RWD << BIT_SHIFT_WKFMCAM_RWD) +#define BIT_CLEAR_WKFMCAM_RWD(x) ((x) & (~BITS_WKFMCAM_RWD)) +#define BIT_GET_WKFMCAM_RWD(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD) +#define BIT_SET_WKFMCAM_RWD(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD(x) | BIT_WKFMCAM_RWD(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BCN_PSR_RPT (Offset 0x06A8) */ +#define BIT_SHIFT_DTIM_PERIOD 16 +#define BIT_MASK_DTIM_PERIOD 0xff +#define BIT_DTIM_PERIOD(x) \ + (((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD) +#define BITS_DTIM_PERIOD (BIT_MASK_DTIM_PERIOD << BIT_SHIFT_DTIM_PERIOD) +#define BIT_CLEAR_DTIM_PERIOD(x) ((x) & (~BITS_DTIM_PERIOD)) +#define BIT_GET_DTIM_PERIOD(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD) +#define BIT_SET_DTIM_PERIOD(x, v) \ + (BIT_CLEAR_DTIM_PERIOD(x) | BIT_DTIM_PERIOD(v)) -/* 2 REG_WL_DSS_STATUS1 (Offset 0x10DC) */ +#define BIT_DTIM BIT(15) +#define BIT_TIM BIT(14) -#define BIT_WL_DSS_READY BIT(21) -#define BIT_WL_DSS_WSORT_GO BIT(20) +#define BIT_SHIFT_PS_AID_0 0 +#define BIT_MASK_PS_AID_0 0x7ff +#define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0) +#define BITS_PS_AID_0 (BIT_MASK_PS_AID_0 << BIT_SHIFT_PS_AID_0) +#define BIT_CLEAR_PS_AID_0(x) ((x) & (~BITS_PS_AID_0)) +#define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0) +#define BIT_SET_PS_AID_0(x, v) (BIT_CLEAR_PS_AID_0(x) | BIT_PS_AID_0(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_FLC_RPC (Offset 0x06AC) */ +#define BIT_SHIFT_FLC_RPC 0 +#define BIT_MASK_FLC_RPC 0xff +#define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC) +#define BITS_FLC_RPC (BIT_MASK_FLC_RPC << BIT_SHIFT_FLC_RPC) +#define BIT_CLEAR_FLC_RPC(x) ((x) & (~BITS_FLC_RPC)) +#define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC) +#define BIT_SET_FLC_RPC(x, v) (BIT_CLEAR_FLC_RPC(x) | BIT_FLC_RPC(v)) -/* 2 REG_FW_DBG0 (Offset 0x10E0) */ +/* 2 REG_FLC_RPCT (Offset 0x06AD) */ +#define BIT_SHIFT_FLC_RPCT 0 +#define BIT_MASK_FLC_RPCT 0xff +#define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT) +#define BITS_FLC_RPCT (BIT_MASK_FLC_RPCT << BIT_SHIFT_FLC_RPCT) +#define BIT_CLEAR_FLC_RPCT(x) ((x) & (~BITS_FLC_RPCT)) +#define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT) +#define BIT_SET_FLC_RPCT(x, v) (BIT_CLEAR_FLC_RPCT(x) | BIT_FLC_RPCT(v)) -#define BIT_SHIFT_FW_DBG0 0 -#define BIT_MASK_FW_DBG0 0xffffffffL -#define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0) -#define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0) +/* 2 REG_FLC_PTS (Offset 0x06AE) */ +#define BIT_CMF BIT(2) +#define BIT_CCF BIT(1) +#define BIT_CDF BIT(0) -/* 2 REG_FW_DBG1 (Offset 0x10E4) */ +/* 2 REG_FLC_TRPC (Offset 0x06AF) */ +#define BIT_FLC_RPCT_V1 BIT(7) +#define BIT_MODE BIT(6) -#define BIT_SHIFT_FW_DBG1 0 -#define BIT_MASK_FW_DBG1 0xffffffffL -#define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1) -#define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1) +#define BIT_SHIFT_TRPCD 0 +#define BIT_MASK_TRPCD 0x3f +#define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD) +#define BITS_TRPCD (BIT_MASK_TRPCD << BIT_SHIFT_TRPCD) +#define BIT_CLEAR_TRPCD(x) ((x) & (~BITS_TRPCD)) +#define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD) +#define BIT_SET_TRPCD(x, v) (BIT_CLEAR_TRPCD(x) | BIT_TRPCD(v)) +#endif -/* 2 REG_FW_DBG2 (Offset 0x10E8) */ +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_RXPKTMON_CTRL (Offset 0x06B0) */ -#define BIT_SHIFT_FW_DBG2 0 -#define BIT_MASK_FW_DBG2 0xffffffffL -#define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2) -#define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2) +#define BIT_SHIFT_RXBKQPKT_SEQ 20 +#define BIT_MASK_RXBKQPKT_SEQ 0xf +#define BIT_RXBKQPKT_SEQ(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ) +#define BITS_RXBKQPKT_SEQ (BIT_MASK_RXBKQPKT_SEQ << BIT_SHIFT_RXBKQPKT_SEQ) +#define BIT_CLEAR_RXBKQPKT_SEQ(x) ((x) & (~BITS_RXBKQPKT_SEQ)) +#define BIT_GET_RXBKQPKT_SEQ(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ) +#define BIT_SET_RXBKQPKT_SEQ(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ(x) | BIT_RXBKQPKT_SEQ(v)) + +#define BIT_SHIFT_RXBEQPKT_SEQ 16 +#define BIT_MASK_RXBEQPKT_SEQ 0xf +#define BIT_RXBEQPKT_SEQ(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ) +#define BITS_RXBEQPKT_SEQ (BIT_MASK_RXBEQPKT_SEQ << BIT_SHIFT_RXBEQPKT_SEQ) +#define BIT_CLEAR_RXBEQPKT_SEQ(x) ((x) & (~BITS_RXBEQPKT_SEQ)) +#define BIT_GET_RXBEQPKT_SEQ(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ) +#define BIT_SET_RXBEQPKT_SEQ(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ(x) | BIT_RXBEQPKT_SEQ(v)) + +#define BIT_SHIFT_RXVIQPKT_SEQ 12 +#define BIT_MASK_RXVIQPKT_SEQ 0xf +#define BIT_RXVIQPKT_SEQ(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ) +#define BITS_RXVIQPKT_SEQ (BIT_MASK_RXVIQPKT_SEQ << BIT_SHIFT_RXVIQPKT_SEQ) +#define BIT_CLEAR_RXVIQPKT_SEQ(x) ((x) & (~BITS_RXVIQPKT_SEQ)) +#define BIT_GET_RXVIQPKT_SEQ(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ) +#define BIT_SET_RXVIQPKT_SEQ(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ(x) | BIT_RXVIQPKT_SEQ(v)) + +#define BIT_SHIFT_RXVOQPKT_SEQ 8 +#define BIT_MASK_RXVOQPKT_SEQ 0xf +#define BIT_RXVOQPKT_SEQ(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ) +#define BITS_RXVOQPKT_SEQ (BIT_MASK_RXVOQPKT_SEQ << BIT_SHIFT_RXVOQPKT_SEQ) +#define BIT_CLEAR_RXVOQPKT_SEQ(x) ((x) & (~BITS_RXVOQPKT_SEQ)) +#define BIT_GET_RXVOQPKT_SEQ(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ) +#define BIT_SET_RXVOQPKT_SEQ(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ(x) | BIT_RXVOQPKT_SEQ(v)) + +#define BIT_RXBKQPKT_ERR BIT(7) +#define BIT_RXBEQPKT_ERR BIT(6) +#define BIT_RXVIQPKT_ERR BIT(5) +#define BIT_RXVOQPKT_ERR BIT(4) +#define BIT_RXDMA_MON_EN BIT(2) +#define BIT_RXPKT_MON_RST BIT(1) +#define BIT_RXPKT_MON_EN BIT(0) +/* 2 REG_STATE_MON (Offset 0x06B4) */ -/* 2 REG_FW_DBG3 (Offset 0x10EC) */ +#define BIT_EN_TXRPTBUF_CLK BIT(31) +#endif -#define BIT_SHIFT_FW_DBG3 0 -#define BIT_MASK_FW_DBG3 0xffffffffL -#define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3) -#define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3) +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +/* 2 REG_STATE_MON (Offset 0x06B4) */ -/* 2 REG_FW_DBG4 (Offset 0x10F0) */ +#define BIT_SHIFT_DMA_MON_EN 24 +#define BIT_MASK_DMA_MON_EN 0x1f +#define BIT_DMA_MON_EN(x) (((x) & BIT_MASK_DMA_MON_EN) << BIT_SHIFT_DMA_MON_EN) +#define BITS_DMA_MON_EN (BIT_MASK_DMA_MON_EN << BIT_SHIFT_DMA_MON_EN) +#define BIT_CLEAR_DMA_MON_EN(x) ((x) & (~BITS_DMA_MON_EN)) +#define BIT_GET_DMA_MON_EN(x) \ + (((x) >> BIT_SHIFT_DMA_MON_EN) & BIT_MASK_DMA_MON_EN) +#define BIT_SET_DMA_MON_EN(x, v) (BIT_CLEAR_DMA_MON_EN(x) | BIT_DMA_MON_EN(v)) +#endif -#define BIT_SHIFT_FW_DBG4 0 -#define BIT_MASK_FW_DBG4 0xffffffffL -#define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4) -#define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_STATE_MON (Offset 0x06B4) */ -/* 2 REG_FW_DBG5 (Offset 0x10F4) */ +#define BIT_SHIFT_STATE_SEL 24 +#define BIT_MASK_STATE_SEL 0x1f +#define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL) +#define BITS_STATE_SEL (BIT_MASK_STATE_SEL << BIT_SHIFT_STATE_SEL) +#define BIT_CLEAR_STATE_SEL(x) ((x) & (~BITS_STATE_SEL)) +#define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL) +#define BIT_SET_STATE_SEL(x, v) (BIT_CLEAR_STATE_SEL(x) | BIT_STATE_SEL(v)) +#define BIT_MACRX_ERR_1 BIT(17) +#define BIT_MACRX_ERR_0 BIT(16) +#define BIT_DIS_INFOSRCH BIT(14) -#define BIT_SHIFT_FW_DBG5 0 -#define BIT_MASK_FW_DBG5 0xffffffffL -#define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5) -#define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5) +#define BIT_SHIFT_STATE_INFO 8 +#define BIT_MASK_STATE_INFO 0xff +#define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO) +#define BITS_STATE_INFO (BIT_MASK_STATE_INFO << BIT_SHIFT_STATE_INFO) +#define BIT_CLEAR_STATE_INFO(x) ((x) & (~BITS_STATE_INFO)) +#define BIT_GET_STATE_INFO(x) \ + (((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO) +#define BIT_SET_STATE_INFO(x, v) (BIT_CLEAR_STATE_INFO(x) | BIT_STATE_INFO(v)) +#define BIT_UPD_NXT_STATE BIT(7) +#define BIT_MACTX_ERR_3 BIT(3) +#define BIT_MACTX_ERR_2 BIT(2) +#define BIT_MACTX_ERR_1 BIT(1) -/* 2 REG_FW_DBG6 (Offset 0x10F8) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_FW_DBG6 0 -#define BIT_MASK_FW_DBG6 0xffffffffL -#define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6) -#define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6) +/* 2 REG_STATE_MON (Offset 0x06B4) */ +#define BIT_SHIFT_PKT_MON_EN 0 +#define BIT_MASK_PKT_MON_EN 0x7f +#define BIT_PKT_MON_EN(x) (((x) & BIT_MASK_PKT_MON_EN) << BIT_SHIFT_PKT_MON_EN) +#define BITS_PKT_MON_EN (BIT_MASK_PKT_MON_EN << BIT_SHIFT_PKT_MON_EN) +#define BIT_CLEAR_PKT_MON_EN(x) ((x) & (~BITS_PKT_MON_EN)) +#define BIT_GET_PKT_MON_EN(x) \ + (((x) >> BIT_SHIFT_PKT_MON_EN) & BIT_MASK_PKT_MON_EN) +#define BIT_SET_PKT_MON_EN(x, v) (BIT_CLEAR_PKT_MON_EN(x) | BIT_PKT_MON_EN(v)) -/* 2 REG_FW_DBG7 (Offset 0x10FC) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_FW_DBG7 0 -#define BIT_MASK_FW_DBG7 0xffffffffL -#define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7) -#define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7) +/* 2 REG_STATE_MON (Offset 0x06B4) */ +#define BIT_SHIFT_CUR_STATE 0 +#define BIT_MASK_CUR_STATE 0x7f +#define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE) +#define BITS_CUR_STATE (BIT_MASK_CUR_STATE << BIT_SHIFT_CUR_STATE) +#define BIT_CLEAR_CUR_STATE(x) ((x) & (~BITS_CUR_STATE)) +#define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE) +#define BIT_SET_CUR_STATE(x, v) (BIT_CLEAR_CUR_STATE(x) | BIT_CUR_STATE(v)) -/* 2 REG_CR_EXT (Offset 0x1100) */ +#define BIT_MACTX_ERR_0 BIT(0) +#define BIT_SHIFT_INFO_ADDR_OFFSET 0 +#define BIT_MASK_INFO_ADDR_OFFSET 0x1fff +#define BIT_INFO_ADDR_OFFSET(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET) +#define BITS_INFO_ADDR_OFFSET \ + (BIT_MASK_INFO_ADDR_OFFSET << BIT_SHIFT_INFO_ADDR_OFFSET) +#define BIT_CLEAR_INFO_ADDR_OFFSET(x) ((x) & (~BITS_INFO_ADDR_OFFSET)) +#define BIT_GET_INFO_ADDR_OFFSET(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET) +#define BIT_SET_INFO_ADDR_OFFSET(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET(x) | BIT_INFO_ADDR_OFFSET(v)) -#define BIT_SHIFT_PHY_REQ_DELAY 24 -#define BIT_MASK_PHY_REQ_DELAY 0xf -#define BIT_PHY_REQ_DELAY(x) (((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY) -#define BIT_GET_PHY_REQ_DELAY(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY) +#endif -#define BIT_SPD_DOWN BIT(16) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_NETYPE4 4 -#define BIT_MASK_NETYPE4 0x3 -#define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4) -#define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC BIT(23) +#define BIT_CSI_CHKSUM_ERROR BIT(22) -#define BIT_SHIFT_NETYPE3 2 -#define BIT_MASK_NETYPE3 0x3 -#define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3) -#define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3) +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_NETYPE2 0 -#define BIT_MASK_NETYPE2 0x3 -#define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2) -#define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_BFM_RPTNUM_ERROR BIT(21) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_MACRX_ERR_5 BIT(21) -/* 2 REG_FWFF (Offset 0x1114) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_PKTNUM_TH 24 -#define BIT_MASK_PKTNUM_TH 0xff -#define BIT_PKTNUM_TH(x) (((x) & BIT_MASK_PKTNUM_TH) << BIT_SHIFT_PKTNUM_TH) -#define BIT_GET_PKTNUM_TH(x) (((x) >> BIT_SHIFT_PKTNUM_TH) & BIT_MASK_PKTNUM_TH) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_BFM_CHECKSUM_ERROR BIT(20) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ERROR_MON (Offset 0x06B8) */ +#define BIT_MACRX_ERR_4 BIT(20) +#define BIT_MACRX_ERR_3 BIT(19) +#define BIT_MACRX_ERR_2 BIT(18) +#define BIT_WMAC_PRETX_ERRHDL_EN BIT(15) +#define BIT_MACTX_ERR_5 BIT(5) -/* 2 REG_FWFF (Offset 0x1114) */ +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#define BIT_SHIFT_PKTNUM_TH_V1 24 -#define BIT_MASK_PKTNUM_TH_V1 0xff -#define BIT_PKTNUM_TH_V1(x) (((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1) -#define BIT_GET_PKTNUM_TH_V1(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1) +/* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */ +#define BIT_PRI_MASK_RX_RESP BIT(126) +#define BIT_PRI_MASK_RXOFDM BIT(125) +#define BIT_PRI_MASK_RXCCK BIT(124) +#define BIT_PRI_MASK_CCK BIT(108) +#define BIT_PRI_MASK_OFDM BIT(107) +#define BIT_PRI_MASK_RTY BIT(106) +#define BIT_OOB BIT(97) +#define BIT_ANT_SEL BIT(96) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */ -/* 2 REG_FWFF (Offset 0x1114) */ +#define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16 +#define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff +#define BIT_R_WMAC_BFINFO_20M_1(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1) +#define BITS_R_WMAC_BFINFO_20M_1 \ + (BIT_MASK_R_WMAC_BFINFO_20M_1 << BIT_SHIFT_R_WMAC_BFINFO_20M_1) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_1)) +#define BIT_GET_R_WMAC_BFINFO_20M_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1) +#define BIT_SET_R_WMAC_BFINFO_20M_1(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) | BIT_R_WMAC_BFINFO_20M_1(v)) + +#define BIT_SHIFT_COEX_TABLE_1 0 +#define BIT_MASK_COEX_TABLE_1 0xffffffffL +#define BIT_COEX_TABLE_1(x) \ + (((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1) +#define BITS_COEX_TABLE_1 (BIT_MASK_COEX_TABLE_1 << BIT_SHIFT_COEX_TABLE_1) +#define BIT_CLEAR_COEX_TABLE_1(x) ((x) & (~BITS_COEX_TABLE_1)) +#define BIT_GET_COEX_TABLE_1(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1) +#define BIT_SET_COEX_TABLE_1(x, v) \ + (BIT_CLEAR_COEX_TABLE_1(x) | BIT_COEX_TABLE_1(v)) + +#define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0 +#define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff +#define BIT_R_WMAC_BFINFO_20M_0(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0) +#define BITS_R_WMAC_BFINFO_20M_0 \ + (BIT_MASK_R_WMAC_BFINFO_20M_0 << BIT_SHIFT_R_WMAC_BFINFO_20M_0) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_0)) +#define BIT_GET_R_WMAC_BFINFO_20M_0(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0) +#define BIT_SET_R_WMAC_BFINFO_20M_0(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) | BIT_R_WMAC_BFINFO_20M_0(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_BT_COEX_TABLE_H (Offset 0x06CC) */ + +#define BIT_PRI_MASK_RX_RESP_V1 BIT(30) +#define BIT_PRI_MASK_RXOFDM_V1 BIT(29) +#define BIT_PRI_MASK_RXCCK_V1 BIT(28) +#define BIT_PRI_MASK_CCK_V1 BIT(12) +#define BIT_PRI_MASK_OFDM_V1 BIT(11) +#define BIT_PRI_MASK_RTY_V1 BIT(10) +#define BIT_OOB_V1 BIT(1) +#define BIT_ANT_SEL_V1 BIT(0) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_RXCMD_0 (Offset 0x06D0) */ -#define BIT_SHIFT_TIMER_TH 16 -#define BIT_MASK_TIMER_TH 0xff -#define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH) -#define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH) +#define BIT_RXCMD_EN BIT(31) +#define BIT_SHIFT_RXCMD_INFO 0 +#define BIT_MASK_RXCMD_INFO 0x7fffffffL +#define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO) +#define BITS_RXCMD_INFO (BIT_MASK_RXCMD_INFO << BIT_SHIFT_RXCMD_INFO) +#define BIT_CLEAR_RXCMD_INFO(x) ((x) & (~BITS_RXCMD_INFO)) +#define BIT_GET_RXCMD_INFO(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO) +#define BIT_SET_RXCMD_INFO(x, v) (BIT_CLEAR_RXCMD_INFO(x) | BIT_RXCMD_INFO(v)) -#endif +/* 2 REG_RXCMD_1 (Offset 0x06D4) */ +#define BIT_TXUSER_ID1 BIT(25) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FWFF (Offset 0x1114) */ +/* 2 REG_RXCMD_1 (Offset 0x06D4) */ -#define BIT_EN_SPD BIT(6) -#define BIT_EN_RXDMA_ALIGN_V1 BIT(1) +#define BIT_SHIFT_CSI_RADDR_LATCH_V1 24 +#define BIT_MASK_CSI_RADDR_LATCH_V1 0x3f +#define BIT_CSI_RADDR_LATCH_V1(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH_V1) << BIT_SHIFT_CSI_RADDR_LATCH_V1) +#define BITS_CSI_RADDR_LATCH_V1 \ + (BIT_MASK_CSI_RADDR_LATCH_V1 << BIT_SHIFT_CSI_RADDR_LATCH_V1) +#define BIT_CLEAR_CSI_RADDR_LATCH_V1(x) ((x) & (~BITS_CSI_RADDR_LATCH_V1)) +#define BIT_GET_CSI_RADDR_LATCH_V1(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V1) & BIT_MASK_CSI_RADDR_LATCH_V1) +#define BIT_SET_CSI_RADDR_LATCH_V1(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH_V1(x) | BIT_CSI_RADDR_LATCH_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RXCMD_1 (Offset 0x06D4) */ +#define BIT_SHIFT_CSI_RADDR_LATCH 24 +#define BIT_MASK_CSI_RADDR_LATCH 0xff +#define BIT_CSI_RADDR_LATCH(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH) << BIT_SHIFT_CSI_RADDR_LATCH) +#define BITS_CSI_RADDR_LATCH \ + (BIT_MASK_CSI_RADDR_LATCH << BIT_SHIFT_CSI_RADDR_LATCH) +#define BIT_CLEAR_CSI_RADDR_LATCH(x) ((x) & (~BITS_CSI_RADDR_LATCH)) +#define BIT_GET_CSI_RADDR_LATCH(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH) & BIT_MASK_CSI_RADDR_LATCH) +#define BIT_SET_CSI_RADDR_LATCH(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH(x) | BIT_CSI_RADDR_LATCH(v)) -/* 2 REG_FWFF (Offset 0x1114) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXPKT1ENADDR 0 -#define BIT_MASK_RXPKT1ENADDR 0xffff -#define BIT_RXPKT1ENADDR(x) (((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR) -#define BIT_GET_RXPKT1ENADDR(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR) +/* 2 REG_RXCMD_1 (Offset 0x06D4) */ +#define BIT_SHIFT_AID1 16 +#define BIT_MASK_AID1 0x1ff +#define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1) +#define BITS_AID1 (BIT_MASK_AID1 << BIT_SHIFT_AID1) +#define BIT_CLEAR_AID1(x) ((x) & (~BITS_AID1)) +#define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1) +#define BIT_SET_AID1(x, v) (BIT_CLEAR_AID1(x) | BIT_AID1(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_RXCMD_1 (Offset 0x06D4) */ +#define BIT_SHIFT_CSI_WADDR_LATCH_V1 16 +#define BIT_MASK_CSI_WADDR_LATCH_V1 0x3f +#define BIT_CSI_WADDR_LATCH_V1(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH_V1) << BIT_SHIFT_CSI_WADDR_LATCH_V1) +#define BITS_CSI_WADDR_LATCH_V1 \ + (BIT_MASK_CSI_WADDR_LATCH_V1 << BIT_SHIFT_CSI_WADDR_LATCH_V1) +#define BIT_CLEAR_CSI_WADDR_LATCH_V1(x) ((x) & (~BITS_CSI_WADDR_LATCH_V1)) +#define BIT_GET_CSI_WADDR_LATCH_V1(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V1) & BIT_MASK_CSI_WADDR_LATCH_V1) +#define BIT_SET_CSI_WADDR_LATCH_V1(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH_V1(x) | BIT_CSI_WADDR_LATCH_V1(v)) -/* 2 REG_FWFF (Offset 0x1114) */ +#endif -#define BIT_EN_TXDMA_ALIGN_V1 BIT(0) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -#define BIT_SHIFT_MDIO_REG_ADDR 0 -#define BIT_MASK_MDIO_REG_ADDR 0x1f -#define BIT_MDIO_REG_ADDR(x) (((x) & BIT_MASK_MDIO_REG_ADDR) << BIT_SHIFT_MDIO_REG_ADDR) -#define BIT_GET_MDIO_REG_ADDR(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR) & BIT_MASK_MDIO_REG_ADDR) +/* 2 REG_RXCMD_1 (Offset 0x06D4) */ +#define BIT_SHIFT_CSI_WADDR_LATCH 16 +#define BIT_MASK_CSI_WADDR_LATCH 0xff +#define BIT_CSI_WADDR_LATCH(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH) << BIT_SHIFT_CSI_WADDR_LATCH) +#define BITS_CSI_WADDR_LATCH \ + (BIT_MASK_CSI_WADDR_LATCH << BIT_SHIFT_CSI_WADDR_LATCH) +#define BIT_CLEAR_CSI_WADDR_LATCH(x) ((x) & (~BITS_CSI_WADDR_LATCH)) +#define BIT_GET_CSI_WADDR_LATCH(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH) & BIT_MASK_CSI_WADDR_LATCH) +#define BIT_SET_CSI_WADDR_LATCH(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH(x) | BIT_CSI_WADDR_LATCH(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RXCMD_1 (Offset 0x06D4) */ +#define BIT_TXUSER_ID0 BIT(9) -/* 2 REG_FE2IMR (Offset 0x1120) */ +#define BIT_SHIFT_RXCMD_PRD 0 +#define BIT_MASK_RXCMD_PRD 0xffff +#define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD) +#define BITS_RXCMD_PRD (BIT_MASK_RXCMD_PRD << BIT_SHIFT_RXCMD_PRD) +#define BIT_CLEAR_RXCMD_PRD(x) ((x) & (~BITS_RXCMD_PRD)) +#define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD) +#define BIT_SET_RXCMD_PRD(x, v) (BIT_CLEAR_RXCMD_PRD(x) | BIT_RXCMD_PRD(v)) -#define BIT__FE4ISR__IND_MSK BIT(29) +#define BIT_SHIFT_AID0 0 +#define BIT_MASK_AID0 0x1ff +#define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0) +#define BITS_AID0 (BIT_MASK_AID0 << BIT_SHIFT_AID0) +#define BIT_CLEAR_AID0(x) ((x) & (~BITS_AID0)) +#define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0) +#define BIT_SET_AID0(x, v) (BIT_CLEAR_AID0(x) | BIT_AID0(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RESP_TXINFO_CFG (Offset 0x06D8) */ - -/* 2 REG_FE2IMR (Offset 0x1120) */ - -#define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28) -#define BIT_FS_TXSC_BKDONE_INT_EN BIT(27) -#define BIT_FS_TXSC_BEDONE_INT_EN BIT(26) -#define BIT_FS_TXSC_VIDONE_INT_EN BIT(25) -#define BIT_FS_TXSC_VODONE_INT_EN BIT(24) +#define BIT_SHIFT_RESP_MFB 25 +#define BIT_MASK_RESP_MFB 0x7f +#define BIT_RESP_MFB(x) (((x) & BIT_MASK_RESP_MFB) << BIT_SHIFT_RESP_MFB) +#define BITS_RESP_MFB (BIT_MASK_RESP_MFB << BIT_SHIFT_RESP_MFB) +#define BIT_CLEAR_RESP_MFB(x) ((x) & (~BITS_RESP_MFB)) +#define BIT_GET_RESP_MFB(x) (((x) >> BIT_SHIFT_RESP_MFB) & BIT_MASK_RESP_MFB) +#define BIT_SET_RESP_MFB(x, v) (BIT_CLEAR_RESP_MFB(x) | BIT_RESP_MFB(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FE2IMR (Offset 0x1120) */ +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ -#define BIT_FS_ATIM_MB7_INT_EN BIT(23) -#define BIT_FS_ATIM_MB6_INT_EN BIT(22) -#define BIT_FS_ATIM_MB5_INT_EN BIT(21) -#define BIT_FS_ATIM_MB4_INT_EN BIT(20) -#define BIT_FS_ATIM_MB3_INT_EN BIT(19) -#define BIT_FS_ATIM_MB2_INT_EN BIT(18) -#define BIT_FS_ATIM_MB1_INT_EN BIT(17) -#define BIT_FS_ATIM_MB0_INT_EN BIT(16) -#define BIT_FS_TBTT4INT_EN BIT(11) -#define BIT_FS_TBTT3INT_EN BIT(10) -#define BIT_FS_TBTT2INT_EN BIT(9) -#define BIT_FS_TBTT1INT_EN BIT(8) -#define BIT_FS_TBTT0_MB7INT_EN BIT(7) -#define BIT_FS_TBTT0_MB6INT_EN BIT(6) -#define BIT_FS_TBTT0_MB5INT_EN BIT(5) -#define BIT_FS_TBTT0_MB4INT_EN BIT(4) -#define BIT_FS_TBTT0_MB3INT_EN BIT(3) -#define BIT_FS_TBTT0_MB2INT_EN BIT(2) -#define BIT_FS_TBTT0_MB1INT_EN BIT(1) -#define BIT_FS_TBTT0_INT_EN BIT(0) +#define BIT_SHIFT_WMAC_RESP_MFB 25 +#define BIT_MASK_WMAC_RESP_MFB 0x7f +#define BIT_WMAC_RESP_MFB(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB) +#define BITS_WMAC_RESP_MFB (BIT_MASK_WMAC_RESP_MFB << BIT_SHIFT_WMAC_RESP_MFB) +#define BIT_CLEAR_WMAC_RESP_MFB(x) ((x) & (~BITS_WMAC_RESP_MFB)) +#define BIT_GET_WMAC_RESP_MFB(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB) +#define BIT_SET_WMAC_RESP_MFB(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB(x) | BIT_WMAC_RESP_MFB(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RESP_TXINFO_CFG (Offset 0x06D8) */ +#define BIT_SHIFT_ANTINF_SEL 23 +#define BIT_MASK_ANTINF_SEL 0x3 +#define BIT_ANTINF_SEL(x) (((x) & BIT_MASK_ANTINF_SEL) << BIT_SHIFT_ANTINF_SEL) +#define BITS_ANTINF_SEL (BIT_MASK_ANTINF_SEL << BIT_SHIFT_ANTINF_SEL) +#define BIT_CLEAR_ANTINF_SEL(x) ((x) & (~BITS_ANTINF_SEL)) +#define BIT_GET_ANTINF_SEL(x) \ + (((x) >> BIT_SHIFT_ANTINF_SEL) & BIT_MASK_ANTINF_SEL) +#define BIT_SET_ANTINF_SEL(x, v) (BIT_CLEAR_ANTINF_SEL(x) | BIT_ANTINF_SEL(v)) -/* 2 REG_FE2ISR (Offset 0x1124) */ +#endif -#define BIT__FE4ISR__IND_INT BIT(29) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_WMAC_ANTINF_SEL 23 +#define BIT_MASK_WMAC_ANTINF_SEL 0x3 +#define BIT_WMAC_ANTINF_SEL(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL) +#define BITS_WMAC_ANTINF_SEL \ + (BIT_MASK_WMAC_ANTINF_SEL << BIT_SHIFT_WMAC_ANTINF_SEL) +#define BIT_CLEAR_WMAC_ANTINF_SEL(x) ((x) & (~BITS_WMAC_ANTINF_SEL)) +#define BIT_GET_WMAC_ANTINF_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL) +#define BIT_SET_WMAC_ANTINF_SEL(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL(x) | BIT_WMAC_ANTINF_SEL(v)) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FE2ISR (Offset 0x1124) */ +/* 2 REG_RESP_TXINFO_CFG (Offset 0x06D8) */ -#define BIT_FS_TXSC_DESC_DONE_INT BIT(28) -#define BIT_FS_TXSC_BKDONE_INT BIT(27) -#define BIT_FS_TXSC_BEDONE_INT BIT(26) -#define BIT_FS_TXSC_VIDONE_INT BIT(25) -#define BIT_FS_TXSC_VODONE_INT BIT(24) +#define BIT_SHIFT_ANTSEL_SEL 21 +#define BIT_MASK_ANTSEL_SEL 0x3 +#define BIT_ANTSEL_SEL(x) (((x) & BIT_MASK_ANTSEL_SEL) << BIT_SHIFT_ANTSEL_SEL) +#define BITS_ANTSEL_SEL (BIT_MASK_ANTSEL_SEL << BIT_SHIFT_ANTSEL_SEL) +#define BIT_CLEAR_ANTSEL_SEL(x) ((x) & (~BITS_ANTSEL_SEL)) +#define BIT_GET_ANTSEL_SEL(x) \ + (((x) >> BIT_SHIFT_ANTSEL_SEL) & BIT_MASK_ANTSEL_SEL) +#define BIT_SET_ANTSEL_SEL(x, v) (BIT_CLEAR_ANTSEL_SEL(x) | BIT_ANTSEL_SEL(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_WMAC_ANTSEL_SEL 21 +#define BIT_MASK_WMAC_ANTSEL_SEL 0x3 +#define BIT_WMAC_ANTSEL_SEL(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL) +#define BITS_WMAC_ANTSEL_SEL \ + (BIT_MASK_WMAC_ANTSEL_SEL << BIT_SHIFT_WMAC_ANTSEL_SEL) +#define BIT_CLEAR_WMAC_ANTSEL_SEL(x) ((x) & (~BITS_WMAC_ANTSEL_SEL)) +#define BIT_GET_WMAC_ANTSEL_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL) +#define BIT_SET_WMAC_ANTSEL_SEL(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL(x) | BIT_WMAC_ANTSEL_SEL(v)) -/* 2 REG_FE2ISR (Offset 0x1124) */ +#endif -#define BIT_FS_ATIM_MB7_INT BIT(23) -#define BIT_FS_ATIM_MB6_INT BIT(22) -#define BIT_FS_ATIM_MB5_INT BIT(21) -#define BIT_FS_ATIM_MB4_INT BIT(20) -#define BIT_FS_ATIM_MB3_INT BIT(19) -#define BIT_FS_ATIM_MB2_INT BIT(18) -#define BIT_FS_ATIM_MB1_INT BIT(17) -#define BIT_FS_ATIM_MB0_INT BIT(16) -#define BIT_FS_TBTT4INT BIT(11) -#define BIT_FS_TBTT3INT BIT(10) -#define BIT_FS_TBTT2INT BIT(9) -#define BIT_FS_TBTT1INT BIT(8) -#define BIT_FS_TBTT0_MB7INT BIT(7) -#define BIT_FS_TBTT0_MB6INT BIT(6) -#define BIT_FS_TBTT0_MB5INT BIT(5) -#define BIT_FS_TBTT0_MB4INT BIT(4) -#define BIT_FS_TBTT0_MB3INT BIT(3) -#define BIT_FS_TBTT0_MB2INT BIT(2) -#define BIT_FS_TBTT0_MB1INT BIT(1) -#define BIT_FS_TBTT0_INT BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18 +#define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7 +#define BIT_R_WMAC_RESP_TXPOWER(x) \ + (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER) +#define BITS_R_WMAC_RESP_TXPOWER \ + (BIT_MASK_R_WMAC_RESP_TXPOWER << BIT_SHIFT_R_WMAC_RESP_TXPOWER) +#define BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) ((x) & (~BITS_R_WMAC_RESP_TXPOWER)) +#define BIT_GET_R_WMAC_RESP_TXPOWER(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER) +#define BIT_SET_R_WMAC_RESP_TXPOWER(x, v) \ + (BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) | BIT_R_WMAC_RESP_TXPOWER(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE3IMR (Offset 0x1128) */ +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ -#define BIT_FS_BCNELY4_AGGR_INT_EN BIT(31) +#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE 18 +#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE 0x3 +#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE) \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) +#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE \ + (BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) +#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \ + ((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE)) +#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) & \ + BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE) +#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) | \ + BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_RESP_TXAGC_B 13 +#define BIT_MASK_RESP_TXAGC_B 0x1f +#define BIT_RESP_TXAGC_B(x) \ + (((x) & BIT_MASK_RESP_TXAGC_B) << BIT_SHIFT_RESP_TXAGC_B) +#define BITS_RESP_TXAGC_B (BIT_MASK_RESP_TXAGC_B << BIT_SHIFT_RESP_TXAGC_B) +#define BIT_CLEAR_RESP_TXAGC_B(x) ((x) & (~BITS_RESP_TXAGC_B)) +#define BIT_GET_RESP_TXAGC_B(x) \ + (((x) >> BIT_SHIFT_RESP_TXAGC_B) & BIT_MASK_RESP_TXAGC_B) +#define BIT_SET_RESP_TXAGC_B(x, v) \ + (BIT_CLEAR_RESP_TXAGC_B(x) | BIT_RESP_TXAGC_B(v)) -/* 2 REG_FE3IMR (Offset 0x1128) */ +#define BIT_SHIFT_RESP_TXAGC_A 8 +#define BIT_MASK_RESP_TXAGC_A 0x1f +#define BIT_RESP_TXAGC_A(x) \ + (((x) & BIT_MASK_RESP_TXAGC_A) << BIT_SHIFT_RESP_TXAGC_A) +#define BITS_RESP_TXAGC_A (BIT_MASK_RESP_TXAGC_A << BIT_SHIFT_RESP_TXAGC_A) +#define BIT_CLEAR_RESP_TXAGC_A(x) ((x) & (~BITS_RESP_TXAGC_A)) +#define BIT_GET_RESP_TXAGC_A(x) \ + (((x) >> BIT_SHIFT_RESP_TXAGC_A) & BIT_MASK_RESP_TXAGC_A) +#define BIT_SET_RESP_TXAGC_A(x, v) \ + (BIT_CLEAR_RESP_TXAGC_A(x) | BIT_RESP_TXAGC_A(v)) -#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31) +#define BIT_RESP_ANTSEL_B BIT(7) +#define BIT_RESP_ANTSEL_A BIT(6) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_FE3IMR (Offset 0x1128) */ +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ -#define BIT_FS_BCNELY3_AGGR_INT_EN BIT(30) +#define BIT_SHIFT_WMAC_RESP_TXANT_V1 6 +#define BIT_MASK_WMAC_RESP_TXANT_V1 0xfff +#define BIT_WMAC_RESP_TXANT_V1(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_V1) << BIT_SHIFT_WMAC_RESP_TXANT_V1) +#define BITS_WMAC_RESP_TXANT_V1 \ + (BIT_MASK_WMAC_RESP_TXANT_V1 << BIT_SHIFT_WMAC_RESP_TXANT_V1) +#define BIT_CLEAR_WMAC_RESP_TXANT_V1(x) ((x) & (~BITS_WMAC_RESP_TXANT_V1)) +#define BIT_GET_WMAC_RESP_TXANT_V1(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1) & BIT_MASK_WMAC_RESP_TXANT_V1) +#define BIT_SET_WMAC_RESP_TXANT_V1(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_V1(x) | BIT_WMAC_RESP_TXANT_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ +#define BIT_SHIFT_RESP_TXANT_CCK 4 +#define BIT_MASK_RESP_TXANT_CCK 0x3 +#define BIT_RESP_TXANT_CCK(x) \ + (((x) & BIT_MASK_RESP_TXANT_CCK) << BIT_SHIFT_RESP_TXANT_CCK) +#define BITS_RESP_TXANT_CCK \ + (BIT_MASK_RESP_TXANT_CCK << BIT_SHIFT_RESP_TXANT_CCK) +#define BIT_CLEAR_RESP_TXANT_CCK(x) ((x) & (~BITS_RESP_TXANT_CCK)) +#define BIT_GET_RESP_TXANT_CCK(x) \ + (((x) >> BIT_SHIFT_RESP_TXANT_CCK) & BIT_MASK_RESP_TXANT_CCK) +#define BIT_SET_RESP_TXANT_CCK(x, v) \ + (BIT_CLEAR_RESP_TXANT_CCK(x) | BIT_RESP_TXANT_CCK(v)) + +#define BIT_SHIFT_RESP_TXANT_L 2 +#define BIT_MASK_RESP_TXANT_L 0x3 +#define BIT_RESP_TXANT_L(x) \ + (((x) & BIT_MASK_RESP_TXANT_L) << BIT_SHIFT_RESP_TXANT_L) +#define BITS_RESP_TXANT_L (BIT_MASK_RESP_TXANT_L << BIT_SHIFT_RESP_TXANT_L) +#define BIT_CLEAR_RESP_TXANT_L(x) ((x) & (~BITS_RESP_TXANT_L)) +#define BIT_GET_RESP_TXANT_L(x) \ + (((x) >> BIT_SHIFT_RESP_TXANT_L) & BIT_MASK_RESP_TXANT_L) +#define BIT_SET_RESP_TXANT_L(x, v) \ + (BIT_CLEAR_RESP_TXANT_L(x) | BIT_RESP_TXANT_L(v)) + +#define BIT_SHIFT_RESP_TXANT_HT 0 +#define BIT_MASK_RESP_TXANT_HT 0x3 +#define BIT_RESP_TXANT_HT(x) \ + (((x) & BIT_MASK_RESP_TXANT_HT) << BIT_SHIFT_RESP_TXANT_HT) +#define BITS_RESP_TXANT_HT (BIT_MASK_RESP_TXANT_HT << BIT_SHIFT_RESP_TXANT_HT) +#define BIT_CLEAR_RESP_TXANT_HT(x) ((x) & (~BITS_RESP_TXANT_HT)) +#define BIT_GET_RESP_TXANT_HT(x) \ + (((x) >> BIT_SHIFT_RESP_TXANT_HT) & BIT_MASK_RESP_TXANT_HT) +#define BIT_SET_RESP_TXANT_HT(x, v) \ + (BIT_CLEAR_RESP_TXANT_HT(x) | BIT_RESP_TXANT_HT(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_RESP_TXINFO_CFG (Offset 0x06D8) */ + +#define BIT_SHIFT_RESP_TXANT 0 +#define BIT_MASK_RESP_TXANT 0x3ffff +#define BIT_RESP_TXANT(x) (((x) & BIT_MASK_RESP_TXANT) << BIT_SHIFT_RESP_TXANT) +#define BITS_RESP_TXANT (BIT_MASK_RESP_TXANT << BIT_SHIFT_RESP_TXANT) +#define BIT_CLEAR_RESP_TXANT(x) ((x) & (~BITS_RESP_TXANT)) +#define BIT_GET_RESP_TXANT(x) \ + (((x) >> BIT_SHIFT_RESP_TXANT) & BIT_MASK_RESP_TXANT) +#define BIT_SET_RESP_TXANT(x, v) (BIT_CLEAR_RESP_TXANT(x) | BIT_RESP_TXANT(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_FE3IMR (Offset 0x1128) */ +/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ -#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30) +#define BIT_SHIFT_WMAC_RESP_TXANT 0 +#define BIT_MASK_WMAC_RESP_TXANT 0x3ffff +#define BIT_WMAC_RESP_TXANT(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT) +#define BITS_WMAC_RESP_TXANT \ + (BIT_MASK_WMAC_RESP_TXANT << BIT_SHIFT_WMAC_RESP_TXANT) +#define BIT_CLEAR_WMAC_RESP_TXANT(x) ((x) & (~BITS_WMAC_RESP_TXANT)) +#define BIT_GET_WMAC_RESP_TXANT(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT) +#define BIT_SET_WMAC_RESP_TXANT(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT(x) | BIT_WMAC_RESP_TXANT(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_FE3IMR (Offset 0x1128) */ +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ -#define BIT_FS_BCNELY2_AGGR_INT_EN BIT(29) +#define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_WMAC_USE_NDPARATE BIT(30) -/* 2 REG_FE3IMR (Offset 0x1128) */ +#define BIT_SHIFT_WMAC_CSI_RATE 24 +#define BIT_MASK_WMAC_CSI_RATE 0x3f +#define BIT_WMAC_CSI_RATE(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE) +#define BITS_WMAC_CSI_RATE (BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE) +#define BIT_CLEAR_WMAC_CSI_RATE(x) ((x) & (~BITS_WMAC_CSI_RATE)) +#define BIT_GET_WMAC_CSI_RATE(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE) +#define BIT_SET_WMAC_CSI_RATE(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE(x) | BIT_WMAC_CSI_RATE(v)) -#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29) +#define BIT_SHIFT_WMAC_RESP_TXRATE 16 +#define BIT_MASK_WMAC_RESP_TXRATE 0xff +#define BIT_WMAC_RESP_TXRATE(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE) +#define BITS_WMAC_RESP_TXRATE \ + (BIT_MASK_WMAC_RESP_TXRATE << BIT_SHIFT_WMAC_RESP_TXRATE) +#define BIT_CLEAR_WMAC_RESP_TXRATE(x) ((x) & (~BITS_WMAC_RESP_TXRATE)) +#define BIT_GET_WMAC_RESP_TXRATE(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE) +#define BIT_SET_WMAC_RESP_TXRATE(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE(x) | BIT_WMAC_RESP_TXRATE(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_WMAC_CSI_RATE_FORCE_EN BIT(15) -/* 2 REG_FE3IMR (Offset 0x1128) */ +#endif -#define BIT_FS_BCNELY1_AGGR_INT_EN BIT(28) +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -#endif +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_CSI_FORCE_RATE_EN BIT(15) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FE3IMR (Offset 0x1128) */ +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ -#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28) +#define BIT_SHIFT_WMAC_CSI_RSC_FORCE 13 +#define BIT_MASK_WMAC_CSI_RSC_FORCE 0x3 +#define BIT_WMAC_CSI_RSC_FORCE(x) \ + (((x) & BIT_MASK_WMAC_CSI_RSC_FORCE) << BIT_SHIFT_WMAC_CSI_RSC_FORCE) +#define BITS_WMAC_CSI_RSC_FORCE \ + (BIT_MASK_WMAC_CSI_RSC_FORCE << BIT_SHIFT_WMAC_CSI_RSC_FORCE) +#define BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) ((x) & (~BITS_WMAC_CSI_RSC_FORCE)) +#define BIT_GET_WMAC_CSI_RSC_FORCE(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RSC_FORCE) & BIT_MASK_WMAC_CSI_RSC_FORCE) +#define BIT_SET_WMAC_CSI_RSC_FORCE(x, v) \ + (BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) | BIT_WMAC_CSI_RSC_FORCE(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_SHIFT_CSI_RSC 13 +#define BIT_MASK_CSI_RSC 0x3 +#define BIT_CSI_RSC(x) (((x) & BIT_MASK_CSI_RSC) << BIT_SHIFT_CSI_RSC) +#define BITS_CSI_RSC (BIT_MASK_CSI_RSC << BIT_SHIFT_CSI_RSC) +#define BIT_CLEAR_CSI_RSC(x) ((x) & (~BITS_CSI_RSC)) +#define BIT_GET_CSI_RSC(x) (((x) >> BIT_SHIFT_CSI_RSC) & BIT_MASK_CSI_RSC) +#define BIT_SET_CSI_RSC(x, v) (BIT_CLEAR_CSI_RSC(x) | BIT_CSI_RSC(v)) -/* 2 REG_FE3IMR (Offset 0x1128) */ +#endif -#define BIT_FS_BCNDMA4_INT_EN BIT(27) -#define BIT_FS_BCNDMA3_INT_EN BIT(26) -#define BIT_FS_BCNDMA2_INT_EN BIT(25) -#define BIT_FS_BCNDMA1_INT_EN BIT(24) -#define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23) -#define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22) -#define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21) -#define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20) -#define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19) -#define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18) -#define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17) -#define BIT_FS_BCNDMA0_INT_EN BIT(16) -#define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15) -#define BIT_FS_BCNERLY4_INT_EN BIT(11) -#define BIT_FS_BCNERLY3_INT_EN BIT(10) -#define BIT_FS_BCNERLY2_INT_EN BIT(9) -#define BIT_FS_BCNERLY1_INT_EN BIT(8) -#define BIT_FS_BCNERLY0_MB7INT_EN BIT(7) -#define BIT_FS_BCNERLY0_MB6INT_EN BIT(6) -#define BIT_FS_BCNERLY0_MB5INT_EN BIT(5) -#define BIT_FS_BCNERLY0_MB4INT_EN BIT(4) -#define BIT_FS_BCNERLY0_MB3INT_EN BIT(3) -#define BIT_FS_BCNERLY0_MB2INT_EN BIT(2) -#define BIT_FS_BCNERLY0_MB1INT_EN BIT(1) -#define BIT_FS_BCNERLY0_INT_EN BIT(0) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_WMAC_CSI_GID_SEL BIT(12) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE3ISR (Offset 0x112C) */ +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ -#define BIT_FS_BCNELY4_AGGR_INT BIT(31) +#define BIT_CSI_GID_SEL BIT(12) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_RDCSIMD_FLAG_TRIG_SEL BIT(11) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1 BIT(10) -/* 2 REG_FE3ISR (Offset 0x112C) */ +#endif -#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31) +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_NDPVLD_PROTECT_RDRDY_DIS BIT(9) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FE3ISR (Offset 0x112C) */ +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ -#define BIT_FS_BCNELY3_AGGR_INT BIT(30) +#define BIT_CSIRD_EMPTY_APPZERO BIT(8) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_RDCSI_EMPTY_APPZERO BIT(8) -/* 2 REG_FE3ISR (Offset 0x112C) */ +#endif -#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_WMC_CSI_RATE_FB_EN BIT(7) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE3ISR (Offset 0x112C) */ +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ -#define BIT_FS_BCNELY2_AGGR_INT BIT(29) +#define BIT_CSI_RATE_FB_EN BIT(7) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_RXFIFO_WRPTR_WO_CHKSUM BIT(6) -/* 2 REG_FE3ISR (Offset 0x112C) */ +#endif -#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ +#define BIT_BBPSF_MPDUCHKEN BIT(5) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -/* 2 REG_FE3ISR (Offset 0x112C) */ +/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ + +#define BIT_BBPSF_MHCHKEN BIT(4) +#define BIT_BBPSF_ERRCHKEN BIT(3) -#define BIT_FS_BCNELY1_AGGR_INT BIT(28) +#define BIT_SHIFT_BBPSF_ERRTHR 0 +#define BIT_MASK_BBPSF_ERRTHR 0x7 +#define BIT_BBPSF_ERRTHR(x) \ + (((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR) +#define BITS_BBPSF_ERRTHR (BIT_MASK_BBPSF_ERRTHR << BIT_SHIFT_BBPSF_ERRTHR) +#define BIT_CLEAR_BBPSF_ERRTHR(x) ((x) & (~BITS_BBPSF_ERRTHR)) +#define BIT_GET_BBPSF_ERRTHR(x) \ + (((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR) +#define BIT_SET_BBPSF_ERRTHR(x, v) \ + (BIT_CLEAR_BBPSF_ERRTHR(x) | BIT_BBPSF_ERRTHR(v)) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RESP_TXINFO_RATE (Offset 0x06DE) */ +#define BIT_USE_NDPARATE BIT(14) -/* 2 REG_FE3ISR (Offset 0x112C) */ +#define BIT_SHIFT_CSI_RATE 8 +#define BIT_MASK_CSI_RATE 0x3f +#define BIT_CSI_RATE(x) (((x) & BIT_MASK_CSI_RATE) << BIT_SHIFT_CSI_RATE) +#define BITS_CSI_RATE (BIT_MASK_CSI_RATE << BIT_SHIFT_CSI_RATE) +#define BIT_CLEAR_CSI_RATE(x) ((x) & (~BITS_CSI_RATE)) +#define BIT_GET_CSI_RATE(x) (((x) >> BIT_SHIFT_CSI_RATE) & BIT_MASK_CSI_RATE) +#define BIT_SET_CSI_RATE(x, v) (BIT_CLEAR_CSI_RATE(x) | BIT_CSI_RATE(v)) -#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28) +#define BIT_SHIFT_RESP_TXRATE 0 +#define BIT_MASK_RESP_TXRATE 0xff +#define BIT_RESP_TXRATE(x) \ + (((x) & BIT_MASK_RESP_TXRATE) << BIT_SHIFT_RESP_TXRATE) +#define BITS_RESP_TXRATE (BIT_MASK_RESP_TXRATE << BIT_SHIFT_RESP_TXRATE) +#define BIT_CLEAR_RESP_TXRATE(x) ((x) & (~BITS_RESP_TXRATE)) +#define BIT_GET_RESP_TXRATE(x) \ + (((x) >> BIT_SHIFT_RESP_TXRATE) & BIT_MASK_RESP_TXRATE) +#define BIT_SET_RESP_TXRATE(x, v) \ + (BIT_CLEAR_RESP_TXRATE(x) | BIT_RESP_TXRATE(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +#define BIT_NOA_PARSER_EN BIT(15) -/* 2 REG_FE3ISR (Offset 0x112C) */ +#endif -#define BIT_FS_BCNDMA4_INT BIT(27) -#define BIT_FS_BCNDMA3_INT BIT(26) -#define BIT_FS_BCNDMA2_INT BIT(25) -#define BIT_FS_BCNDMA1_INT BIT(24) -#define BIT_FS_BCNDMA0_MB7_INT BIT(23) -#define BIT_FS_BCNDMA0_MB6_INT BIT(22) -#define BIT_FS_BCNDMA0_MB5_INT BIT(21) -#define BIT_FS_BCNDMA0_MB4_INT BIT(20) -#define BIT_FS_BCNDMA0_MB3_INT BIT(19) -#define BIT_FS_BCNDMA0_MB2_INT BIT(18) -#define BIT_FS_BCNDMA0_MB1_INT BIT(17) -#define BIT_FS_BCNDMA0_INT BIT(16) -#define BIT_FS_MTI_BCNIVLEAR_INT BIT(15) -#define BIT_FS_BCNERLY4_INT BIT(11) -#define BIT_FS_BCNERLY3_INT BIT(10) -#define BIT_FS_BCNERLY2_INT BIT(9) -#define BIT_FS_BCNERLY1_INT BIT(8) -#define BIT_FS_BCNERLY0_MB7INT BIT(7) -#define BIT_FS_BCNERLY0_MB6INT BIT(6) -#define BIT_FS_BCNERLY0_MB5INT BIT(5) -#define BIT_FS_BCNERLY0_MB4INT BIT(4) -#define BIT_FS_BCNERLY0_MB3INT BIT(3) -#define BIT_FS_BCNERLY0_MB2INT BIT(2) -#define BIT_FS_BCNERLY0_MB1INT BIT(1) -#define BIT_FS_BCNERLY0_INT BIT(0) +#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +#define BIT_BSSID_SEL BIT(14) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ -#define BIT_PORT4_PKTIN_INT_EN BIT(19) +#define BIT_SHIFT_BSSID_SEL_V1 12 +#define BIT_MASK_BSSID_SEL_V1 0x7 +#define BIT_BSSID_SEL_V1(x) \ + (((x) & BIT_MASK_BSSID_SEL_V1) << BIT_SHIFT_BSSID_SEL_V1) +#define BITS_BSSID_SEL_V1 (BIT_MASK_BSSID_SEL_V1 << BIT_SHIFT_BSSID_SEL_V1) +#define BIT_CLEAR_BSSID_SEL_V1(x) ((x) & (~BITS_BSSID_SEL_V1)) +#define BIT_GET_BSSID_SEL_V1(x) \ + (((x) >> BIT_SHIFT_BSSID_SEL_V1) & BIT_MASK_BSSID_SEL_V1) +#define BIT_SET_BSSID_SEL_V1(x, v) \ + (BIT_CLEAR_BSSID_SEL_V1(x) | BIT_BSSID_SEL_V1(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +#define BIT_SHIFT_P2P_OUI_TYPE 0 +#define BIT_MASK_P2P_OUI_TYPE 0xff +#define BIT_P2P_OUI_TYPE(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE) +#define BITS_P2P_OUI_TYPE (BIT_MASK_P2P_OUI_TYPE << BIT_SHIFT_P2P_OUI_TYPE) +#define BIT_CLEAR_P2P_OUI_TYPE(x) ((x) & (~BITS_P2P_OUI_TYPE)) +#define BIT_GET_P2P_OUI_TYPE(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE) +#define BIT_SET_P2P_OUI_TYPE(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE(x) | BIT_P2P_OUI_TYPE(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ +#define BIT_SHIFT_INFO_TXRPT_OFFSET_V1 0 +#define BIT_MASK_INFO_TXRPT_OFFSET_V1 0x1fff +#define BIT_INFO_TXRPT_OFFSET_V1(x) \ + (((x) & BIT_MASK_INFO_TXRPT_OFFSET_V1) \ + << BIT_SHIFT_INFO_TXRPT_OFFSET_V1) +#define BITS_INFO_TXRPT_OFFSET_V1 \ + (BIT_MASK_INFO_TXRPT_OFFSET_V1 << BIT_SHIFT_INFO_TXRPT_OFFSET_V1) +#define BIT_CLEAR_INFO_TXRPT_OFFSET_V1(x) ((x) & (~BITS_INFO_TXRPT_OFFSET_V1)) +#define BIT_GET_INFO_TXRPT_OFFSET_V1(x) \ + (((x) >> BIT_SHIFT_INFO_TXRPT_OFFSET_V1) & \ + BIT_MASK_INFO_TXRPT_OFFSET_V1) +#define BIT_SET_INFO_TXRPT_OFFSET_V1(x, v) \ + (BIT_CLEAR_INFO_TXRPT_OFFSET_V1(x) | BIT_INFO_TXRPT_OFFSET_V1(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */ -#define BIT_PORT3_PKTIN_INT_EN BIT(18) +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) +#define BITS_R_WMAC_SOUNDING_RXADD_R0 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */ +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_V1(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_SOUNDING_CFG1 (Offset 0x06E8) */ + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R0_H(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_H \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_H(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_ASSOCIATED_BFMER0_INFO_H (Offset 0x06E8) */ + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */ -#define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18) +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) +#define BITS_R_WMAC_SOUNDING_RXADD_R1 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_SOUNDING_CFG2 (Offset 0x06EC) */ + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_V2(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_V2 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V2(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V2)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V2(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V2(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V2(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_V2(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */ +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_V1(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_SOUNDING_CFG3 (Offset 0x06F0) */ + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V2(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V2 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V2(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V2)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V2(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V2(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V2(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_H_V2(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_ASSOCIATED_BFMER1_INFO_H (Offset 0x06F0) */ + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1 \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1 \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ -#define BIT_PORT2_PKTIN_INT_EN BIT(17) +#define BIT_SHIFT_R_WMAC_BFINFO_40M_1 13 +#define BIT_MASK_R_WMAC_BFINFO_40M_1 0x7fff +#define BIT_R_WMAC_BFINFO_40M_1(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_40M_1) << BIT_SHIFT_R_WMAC_BFINFO_40M_1) +#define BITS_R_WMAC_BFINFO_40M_1 \ + (BIT_MASK_R_WMAC_BFINFO_40M_1 << BIT_SHIFT_R_WMAC_BFINFO_40M_1) +#define BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_1)) +#define BIT_GET_R_WMAC_BFINFO_40M_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_1) & BIT_MASK_R_WMAC_BFINFO_40M_1) +#define BIT_SET_R_WMAC_BFINFO_40M_1(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) | BIT_R_WMAC_BFINFO_40M_1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +#define BIT_SHIFT_WMAC_RESP_ANTD 12 +#define BIT_MASK_WMAC_RESP_ANTD 0xf +#define BIT_WMAC_RESP_ANTD(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTD) << BIT_SHIFT_WMAC_RESP_ANTD) +#define BITS_WMAC_RESP_ANTD \ + (BIT_MASK_WMAC_RESP_ANTD << BIT_SHIFT_WMAC_RESP_ANTD) +#define BIT_CLEAR_WMAC_RESP_ANTD(x) ((x) & (~BITS_WMAC_RESP_ANTD)) +#define BIT_GET_WMAC_RESP_ANTD(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTD) & BIT_MASK_WMAC_RESP_ANTD) +#define BIT_SET_WMAC_RESP_ANTD(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTD(x) | BIT_WMAC_RESP_ANTD(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17) +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_ANTCD_INFO (Offset 0x06F8) */ + +#define BIT_RESP_SMOOTH BIT(8) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +#define BIT_SHIFT_WMAC_RESP_ANTC 8 +#define BIT_MASK_WMAC_RESP_ANTC 0xf +#define BIT_WMAC_RESP_ANTC(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTC) << BIT_SHIFT_WMAC_RESP_ANTC) +#define BITS_WMAC_RESP_ANTC \ + (BIT_MASK_WMAC_RESP_ANTC << BIT_SHIFT_WMAC_RESP_ANTC) +#define BIT_CLEAR_WMAC_RESP_ANTC(x) ((x) & (~BITS_WMAC_RESP_ANTC)) +#define BIT_GET_WMAC_RESP_ANTC(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTC) & BIT_MASK_WMAC_RESP_ANTC) +#define BIT_SET_WMAC_RESP_ANTC(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTC(x) | BIT_WMAC_RESP_ANTC(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_ANTCD_INFO (Offset 0x06F8) */ + +#define BIT_SHIFT_POWER_STAGE2_NORETRY 6 +#define BIT_MASK_POWER_STAGE2_NORETRY 0x3 +#define BIT_POWER_STAGE2_NORETRY(x) \ + (((x) & BIT_MASK_POWER_STAGE2_NORETRY) \ + << BIT_SHIFT_POWER_STAGE2_NORETRY) +#define BITS_POWER_STAGE2_NORETRY \ + (BIT_MASK_POWER_STAGE2_NORETRY << BIT_SHIFT_POWER_STAGE2_NORETRY) +#define BIT_CLEAR_POWER_STAGE2_NORETRY(x) ((x) & (~BITS_POWER_STAGE2_NORETRY)) +#define BIT_GET_POWER_STAGE2_NORETRY(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2_NORETRY) & \ + BIT_MASK_POWER_STAGE2_NORETRY) +#define BIT_SET_POWER_STAGE2_NORETRY(x, v) \ + (BIT_CLEAR_POWER_STAGE2_NORETRY(x) | BIT_POWER_STAGE2_NORETRY(v)) + +#define BIT_SHIFT_POWER_STAGE1_NORETRY 4 +#define BIT_MASK_POWER_STAGE1_NORETRY 0x3 +#define BIT_POWER_STAGE1_NORETRY(x) \ + (((x) & BIT_MASK_POWER_STAGE1_NORETRY) \ + << BIT_SHIFT_POWER_STAGE1_NORETRY) +#define BITS_POWER_STAGE1_NORETRY \ + (BIT_MASK_POWER_STAGE1_NORETRY << BIT_SHIFT_POWER_STAGE1_NORETRY) +#define BIT_CLEAR_POWER_STAGE1_NORETRY(x) ((x) & (~BITS_POWER_STAGE1_NORETRY)) +#define BIT_GET_POWER_STAGE1_NORETRY(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1_NORETRY) & \ + BIT_MASK_POWER_STAGE1_NORETRY) +#define BIT_SET_POWER_STAGE1_NORETRY(x, v) \ + (BIT_CLEAR_POWER_STAGE1_NORETRY(x) | BIT_POWER_STAGE1_NORETRY(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ -#define BIT_PORT1_PKTIN_INT_EN BIT(16) +#define BIT_SHIFT_WMAC_RESP_ANTB 4 +#define BIT_MASK_WMAC_RESP_ANTB 0xf +#define BIT_WMAC_RESP_ANTB(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTB) << BIT_SHIFT_WMAC_RESP_ANTB) +#define BITS_WMAC_RESP_ANTB \ + (BIT_MASK_WMAC_RESP_ANTB << BIT_SHIFT_WMAC_RESP_ANTB) +#define BIT_CLEAR_WMAC_RESP_ANTB(x) ((x) & (~BITS_WMAC_RESP_ANTB)) +#define BIT_GET_WMAC_RESP_ANTB(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTB) & BIT_MASK_WMAC_RESP_ANTB) +#define BIT_SET_WMAC_RESP_ANTB(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTB(x) | BIT_WMAC_RESP_ANTB(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +#define BIT_SHIFT_R_WMAC_BFINFO_40M_0 0 +#define BIT_MASK_R_WMAC_BFINFO_40M_0 0xfff +#define BIT_R_WMAC_BFINFO_40M_0(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_40M_0) << BIT_SHIFT_R_WMAC_BFINFO_40M_0) +#define BITS_R_WMAC_BFINFO_40M_0 \ + (BIT_MASK_R_WMAC_BFINFO_40M_0 << BIT_SHIFT_R_WMAC_BFINFO_40M_0) +#define BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_0)) +#define BIT_GET_R_WMAC_BFINFO_40M_0(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_0) & BIT_MASK_R_WMAC_BFINFO_40M_0) +#define BIT_SET_R_WMAC_BFINFO_40M_0(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) | BIT_R_WMAC_BFINFO_40M_0(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_ANTCD_INFO (Offset 0x06F8) */ +#define BIT_SHIFT_RESP_ANTCD 0 +#define BIT_MASK_RESP_ANTCD 0xf +#define BIT_RESP_ANTCD(x) (((x) & BIT_MASK_RESP_ANTCD) << BIT_SHIFT_RESP_ANTCD) +#define BITS_RESP_ANTCD (BIT_MASK_RESP_ANTCD << BIT_SHIFT_RESP_ANTCD) +#define BIT_CLEAR_RESP_ANTCD(x) ((x) & (~BITS_RESP_ANTCD)) +#define BIT_GET_RESP_ANTCD(x) \ + (((x) >> BIT_SHIFT_RESP_ANTCD) & BIT_MASK_RESP_ANTCD) +#define BIT_SET_RESP_ANTCD(x, v) (BIT_CLEAR_RESP_ANTCD(x) | BIT_RESP_ANTCD(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ -#define BIT_PORT4_RXUCMD0_OK_INT_EN BIT(15) +#define BIT_SHIFT_WMAC_RESP_ANTCD 0 +#define BIT_MASK_WMAC_RESP_ANTCD 0xf +#define BIT_WMAC_RESP_ANTCD(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD) +#define BITS_WMAC_RESP_ANTCD \ + (BIT_MASK_WMAC_RESP_ANTCD << BIT_SHIFT_WMAC_RESP_ANTCD) +#define BIT_CLEAR_WMAC_RESP_ANTCD(x) ((x) & (~BITS_WMAC_RESP_ANTCD)) +#define BIT_GET_WMAC_RESP_ANTCD(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD) +#define BIT_SET_WMAC_RESP_ANTCD(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTCD(x) | BIT_WMAC_RESP_ANTCD(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ +#define BIT_SHIFT_WMAC_RESP_ANTA 0 +#define BIT_MASK_WMAC_RESP_ANTA 0xf +#define BIT_WMAC_RESP_ANTA(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTA) << BIT_SHIFT_WMAC_RESP_ANTA) +#define BITS_WMAC_RESP_ANTA \ + (BIT_MASK_WMAC_RESP_ANTA << BIT_SHIFT_WMAC_RESP_ANTA) +#define BIT_CLEAR_WMAC_RESP_ANTA(x) ((x) & (~BITS_WMAC_RESP_ANTA)) +#define BIT_GET_WMAC_RESP_ANTA(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTA) & BIT_MASK_WMAC_RESP_ANTA) +#define BIT_SET_WMAC_RESP_ANTA(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTA(x) | BIT_WMAC_RESP_ANTA(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */ +#define BIT_WMAC_CSI_LDPC_EN BIT(29) +#define BIT_WMAC_CSI_STBC_EN BIT(28) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_TX_CSI_RPT_PARAM_BW80 (Offset 0x06FC) */ -#define BIT_PORT4_RXUCMD1_OK_INT_EN BIT(14) +#define BIT_SHIFT_R_WMAC_BFINFO_80M_1 16 +#define BIT_MASK_R_WMAC_BFINFO_80M_1 0xfff +#define BIT_R_WMAC_BFINFO_80M_1(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_80M_1) << BIT_SHIFT_R_WMAC_BFINFO_80M_1) +#define BITS_R_WMAC_BFINFO_80M_1 \ + (BIT_MASK_R_WMAC_BFINFO_80M_1 << BIT_SHIFT_R_WMAC_BFINFO_80M_1) +#define BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_1)) +#define BIT_GET_R_WMAC_BFINFO_80M_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_1) & BIT_MASK_R_WMAC_BFINFO_80M_1) +#define BIT_SET_R_WMAC_BFINFO_80M_1(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) | BIT_R_WMAC_BFINFO_80M_1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CSI_PTR (Offset 0x06FC) */ +#define BIT_SHIFT_CSI_RADDR_LATCH_V2 16 +#define BIT_MASK_CSI_RADDR_LATCH_V2 0xffff +#define BIT_CSI_RADDR_LATCH_V2(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH_V2) << BIT_SHIFT_CSI_RADDR_LATCH_V2) +#define BITS_CSI_RADDR_LATCH_V2 \ + (BIT_MASK_CSI_RADDR_LATCH_V2 << BIT_SHIFT_CSI_RADDR_LATCH_V2) +#define BIT_CLEAR_CSI_RADDR_LATCH_V2(x) ((x) & (~BITS_CSI_RADDR_LATCH_V2)) +#define BIT_GET_CSI_RADDR_LATCH_V2(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2) & BIT_MASK_CSI_RADDR_LATCH_V2) +#define BIT_SET_CSI_RADDR_LATCH_V2(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH_V2(x) | BIT_CSI_RADDR_LATCH_V2(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14) +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */ + +#define BIT_SHIFT_WMAC_CSI_RRSC_BITMAP 4 +#define BIT_MASK_WMAC_CSI_RRSC_BITMAP 0xffffff +#define BIT_WMAC_CSI_RRSC_BITMAP(x) \ + (((x) & BIT_MASK_WMAC_CSI_RRSC_BITMAP) \ + << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) +#define BITS_WMAC_CSI_RRSC_BITMAP \ + (BIT_MASK_WMAC_CSI_RRSC_BITMAP << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) +#define BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) ((x) & (~BITS_WMAC_CSI_RRSC_BITMAP)) +#define BIT_GET_WMAC_CSI_RRSC_BITMAP(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) & \ + BIT_MASK_WMAC_CSI_RRSC_BITMAP) +#define BIT_SET_WMAC_CSI_RRSC_BITMAP(x, v) \ + (BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) | BIT_WMAC_CSI_RRSC_BITMAP(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_TX_CSI_RPT_PARAM_BW80 (Offset 0x06FC) */ +#define BIT_SHIFT_R_WMAC_BFINFO_80M_0 0 +#define BIT_MASK_R_WMAC_BFINFO_80M_0 0xfff +#define BIT_R_WMAC_BFINFO_80M_0(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_80M_0) << BIT_SHIFT_R_WMAC_BFINFO_80M_0) +#define BITS_R_WMAC_BFINFO_80M_0 \ + (BIT_MASK_R_WMAC_BFINFO_80M_0 << BIT_SHIFT_R_WMAC_BFINFO_80M_0) +#define BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_0)) +#define BIT_GET_R_WMAC_BFINFO_80M_0(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_0) & BIT_MASK_R_WMAC_BFINFO_80M_0) +#define BIT_SET_R_WMAC_BFINFO_80M_0(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) | BIT_R_WMAC_BFINFO_80M_0(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */ + +#define BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH 0 +#define BIT_MASK_WMAC_CSI_OFDM_LEN_TH 0xf +#define BIT_WMAC_CSI_OFDM_LEN_TH(x) \ + (((x) & BIT_MASK_WMAC_CSI_OFDM_LEN_TH) \ + << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) +#define BITS_WMAC_CSI_OFDM_LEN_TH \ + (BIT_MASK_WMAC_CSI_OFDM_LEN_TH << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) +#define BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) ((x) & (~BITS_WMAC_CSI_OFDM_LEN_TH)) +#define BIT_GET_WMAC_CSI_OFDM_LEN_TH(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) & \ + BIT_MASK_WMAC_CSI_OFDM_LEN_TH) +#define BIT_SET_WMAC_CSI_OFDM_LEN_TH(x, v) \ + (BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) | BIT_WMAC_CSI_OFDM_LEN_TH(v)) + +#define BIT_SHIFT_CSI_PARA_RDY_DLYCNT 0 +#define BIT_MASK_CSI_PARA_RDY_DLYCNT 0x1f +#define BIT_CSI_PARA_RDY_DLYCNT(x) \ + (((x) & BIT_MASK_CSI_PARA_RDY_DLYCNT) << BIT_SHIFT_CSI_PARA_RDY_DLYCNT) +#define BITS_CSI_PARA_RDY_DLYCNT \ + (BIT_MASK_CSI_PARA_RDY_DLYCNT << BIT_SHIFT_CSI_PARA_RDY_DLYCNT) +#define BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) ((x) & (~BITS_CSI_PARA_RDY_DLYCNT)) +#define BIT_GET_CSI_PARA_RDY_DLYCNT(x) \ + (((x) >> BIT_SHIFT_CSI_PARA_RDY_DLYCNT) & BIT_MASK_CSI_PARA_RDY_DLYCNT) +#define BIT_SET_CSI_PARA_RDY_DLYCNT(x, v) \ + (BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) | BIT_CSI_PARA_RDY_DLYCNT(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CSI_PTR (Offset 0x06FC) */ + +#define BIT_SHIFT_CSI_WADDR_LATCH_V2 0 +#define BIT_MASK_CSI_WADDR_LATCH_V2 0xffff +#define BIT_CSI_WADDR_LATCH_V2(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH_V2) << BIT_SHIFT_CSI_WADDR_LATCH_V2) +#define BITS_CSI_WADDR_LATCH_V2 \ + (BIT_MASK_CSI_WADDR_LATCH_V2 << BIT_SHIFT_CSI_WADDR_LATCH_V2) +#define BIT_CLEAR_CSI_WADDR_LATCH_V2(x) ((x) & (~BITS_CSI_WADDR_LATCH_V2)) +#define BIT_GET_CSI_WADDR_LATCH_V2(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2) & BIT_MASK_CSI_WADDR_LATCH_V2) +#define BIT_SET_CSI_WADDR_LATCH_V2(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH_V2(x) | BIT_CSI_WADDR_LATCH_V2(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_MACID1 (Offset 0x0700) */ -#define BIT_PORT4_RXBCMD0_OK_INT_EN BIT(13) +#define BIT_SHIFT_MACID1 0 +#define BIT_MASK_MACID1 0xffffffffffffL +#define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1) +#define BITS_MACID1 (BIT_MASK_MACID1 << BIT_SHIFT_MACID1) +#define BIT_CLEAR_MACID1(x) ((x) & (~BITS_MACID1)) +#define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1) +#define BIT_SET_MACID1(x, v) (BIT_CLEAR_MACID1(x) | BIT_MACID1(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MACID1 (Offset 0x0700) */ +#define BIT_SHIFT_MACID1_0 0 +#define BIT_MASK_MACID1_0 0xffffffffL +#define BIT_MACID1_0(x) (((x) & BIT_MASK_MACID1_0) << BIT_SHIFT_MACID1_0) +#define BITS_MACID1_0 (BIT_MASK_MACID1_0 << BIT_SHIFT_MACID1_0) +#define BIT_CLEAR_MACID1_0(x) ((x) & (~BITS_MACID1_0)) +#define BIT_GET_MACID1_0(x) (((x) >> BIT_SHIFT_MACID1_0) & BIT_MASK_MACID1_0) +#define BIT_SET_MACID1_0(x, v) (BIT_CLEAR_MACID1_0(x) | BIT_MACID1_0(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_MACID1_1 (Offset 0x0704) */ -#define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13) +#define BIT_SHIFT_MACID1_1 0 +#define BIT_MASK_MACID1_1 0xffff +#define BIT_MACID1_1(x) (((x) & BIT_MASK_MACID1_1) << BIT_SHIFT_MACID1_1) +#define BITS_MACID1_1 (BIT_MASK_MACID1_1 << BIT_SHIFT_MACID1_1) +#define BIT_CLEAR_MACID1_1(x) ((x) & (~BITS_MACID1_1)) +#define BIT_GET_MACID1_1(x) (((x) >> BIT_SHIFT_MACID1_1) & BIT_MASK_MACID1_1) +#define BIT_SET_MACID1_1(x, v) (BIT_CLEAR_MACID1_1(x) | BIT_MACID1_1(v)) -#endif +/* 2 REG_BSSID1 (Offset 0x0708) */ +#define BIT_SHIFT_BSSID1_0 0 +#define BIT_MASK_BSSID1_0 0xffffffffL +#define BIT_BSSID1_0(x) (((x) & BIT_MASK_BSSID1_0) << BIT_SHIFT_BSSID1_0) +#define BITS_BSSID1_0 (BIT_MASK_BSSID1_0 << BIT_SHIFT_BSSID1_0) +#define BIT_CLEAR_BSSID1_0(x) ((x) & (~BITS_BSSID1_0)) +#define BIT_GET_BSSID1_0(x) (((x) >> BIT_SHIFT_BSSID1_0) & BIT_MASK_BSSID1_0) +#define BIT_SET_BSSID1_0(x, v) (BIT_CLEAR_BSSID1_0(x) | BIT_BSSID1_0(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_BSSID1 (Offset 0x0708) */ -#define BIT_PORT4_RXBCMD1_OK_INT_EN BIT(12) +#define BIT_SHIFT_BSSID1 0 +#define BIT_MASK_BSSID1 0xffffffffffffL +#define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1) +#define BITS_BSSID1 (BIT_MASK_BSSID1 << BIT_SHIFT_BSSID1) +#define BIT_CLEAR_BSSID1(x) ((x) & (~BITS_BSSID1)) +#define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1) +#define BIT_SET_BSSID1(x, v) (BIT_CLEAR_BSSID1(x) | BIT_BSSID1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PCIE_CFG_FORCE_LINK_L (Offset 0x0709) */ +#define BIT_PCIE_CFG_FORCE_EN BIT(7) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_PCIE_CFG_FORCE_LINK_H (Offset 0x070A) */ -#define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12) +#define BIT_PCIE_CFG_TRXACT_DIS_IDLE_TIMER BIT(6) + +#define BIT_SHIFT_PCIE_CFG_LINK_STATE 0 +#define BIT_MASK_PCIE_CFG_LINK_STATE 0x3f +#define BIT_PCIE_CFG_LINK_STATE(x) \ + (((x) & BIT_MASK_PCIE_CFG_LINK_STATE) << BIT_SHIFT_PCIE_CFG_LINK_STATE) +#define BITS_PCIE_CFG_LINK_STATE \ + (BIT_MASK_PCIE_CFG_LINK_STATE << BIT_SHIFT_PCIE_CFG_LINK_STATE) +#define BIT_CLEAR_PCIE_CFG_LINK_STATE(x) ((x) & (~BITS_PCIE_CFG_LINK_STATE)) +#define BIT_GET_PCIE_CFG_LINK_STATE(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_LINK_STATE) & BIT_MASK_PCIE_CFG_LINK_STATE) +#define BIT_SET_PCIE_CFG_LINK_STATE(x, v) \ + (BIT_CLEAR_PCIE_CFG_LINK_STATE(x) | BIT_PCIE_CFG_LINK_STATE(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BSSID1_1 (Offset 0x070C) */ +#define BIT_SHIFT_BSSID1_1 0 +#define BIT_MASK_BSSID1_1 0xffff +#define BIT_BSSID1_1(x) (((x) & BIT_MASK_BSSID1_1) << BIT_SHIFT_BSSID1_1) +#define BITS_BSSID1_1 (BIT_MASK_BSSID1_1 << BIT_SHIFT_BSSID1_1) +#define BIT_CLEAR_BSSID1_1(x) ((x) & (~BITS_BSSID1_1)) +#define BIT_GET_BSSID1_1(x) (((x) >> BIT_SHIFT_BSSID1_1) & BIT_MASK_BSSID1_1) +#define BIT_SET_BSSID1_1(x, v) (BIT_CLEAR_BSSID1_1(x) | BIT_BSSID1_1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY (Offset 0x070C) */ + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0xff +#define BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) +#define BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY \ + (BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY)) +#define BIT_GET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) & \ + BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY) +#define BIT_SET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) | \ + BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(v)) + +/* 2 REG_PCIE_CFG_CX_NFTS (Offset 0x070D) */ + +#define BIT_SHIFT_PCIE_CFG_CX_NFTS 0 +#define BIT_MASK_PCIE_CFG_CX_NFTS 0xff +#define BIT_PCIE_CFG_CX_NFTS(x) \ + (((x) & BIT_MASK_PCIE_CFG_CX_NFTS) << BIT_SHIFT_PCIE_CFG_CX_NFTS) +#define BITS_PCIE_CFG_CX_NFTS \ + (BIT_MASK_PCIE_CFG_CX_NFTS << BIT_SHIFT_PCIE_CFG_CX_NFTS) +#define BIT_CLEAR_PCIE_CFG_CX_NFTS(x) ((x) & (~BITS_PCIE_CFG_CX_NFTS)) +#define BIT_GET_PCIE_CFG_CX_NFTS(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_CX_NFTS) & BIT_MASK_PCIE_CFG_CX_NFTS) +#define BIT_SET_PCIE_CFG_CX_NFTS(x, v) \ + (BIT_CLEAR_PCIE_CFG_CX_NFTS(x) | BIT_PCIE_CFG_CX_NFTS(v)) + +/* 2 REG_PCIE_CFG_DEFAULT_ENTR_LATENCY (Offset 0x070F) */ + +#define BIT_PCIE_CFG_REAL_EN_L0S BIT(7) +#define BIT_PCIE_CFG_ENTER_ASPM BIT(6) + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 3 +#define BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 0x7 +#define BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) +#define BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY \ + (BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)) +#define BIT_GET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) & \ + BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) +#define BIT_SET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) | \ + BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(v)) + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0x7 +#define BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) +#define BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY \ + (BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)) +#define BIT_GET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) & \ + BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) +#define BIT_SET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) | \ + BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ -#define BIT_PORT3_RXUCMD0_OK_INT_EN BIT(11) +#define BIT_SHIFT_DTIM_CNT1 24 +#define BIT_MASK_DTIM_CNT1 0xff +#define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1) +#define BITS_DTIM_CNT1 (BIT_MASK_DTIM_CNT1 << BIT_SHIFT_DTIM_CNT1) +#define BIT_CLEAR_DTIM_CNT1(x) ((x) & (~BITS_DTIM_CNT1)) +#define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1) +#define BIT_SET_DTIM_CNT1(x, v) (BIT_CLEAR_DTIM_CNT1(x) | BIT_DTIM_CNT1(v)) -#endif +#define BIT_SHIFT_DTIM_PERIOD1 16 +#define BIT_MASK_DTIM_PERIOD1 0xff +#define BIT_DTIM_PERIOD1(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1) +#define BITS_DTIM_PERIOD1 (BIT_MASK_DTIM_PERIOD1 << BIT_SHIFT_DTIM_PERIOD1) +#define BIT_CLEAR_DTIM_PERIOD1(x) ((x) & (~BITS_DTIM_PERIOD1)) +#define BIT_GET_DTIM_PERIOD1(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1) +#define BIT_SET_DTIM_PERIOD1(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1(x) | BIT_DTIM_PERIOD1(v)) +#define BIT_DTIM1 BIT(15) +#define BIT_TIM1 BIT(14) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ -#define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11) +#define BIT_BCN_VALID_V2 BIT(13) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ -#define BIT_PORT3_RXUCMD1_OK_INT_EN BIT(10) +#define BIT_SHIFT_PS_AID_1 0 +#define BIT_MASK_PS_AID_1 0x7ff +#define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1) +#define BITS_PS_AID_1 (BIT_MASK_PS_AID_1 << BIT_SHIFT_PS_AID_1) +#define BIT_CLEAR_PS_AID_1(x) ((x) & (~BITS_PS_AID_1)) +#define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1) +#define BIT_SET_PS_AID_1(x, v) (BIT_CLEAR_PS_AID_1(x) | BIT_PS_AID_1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_PCIE_CFG_L1_MISC_SEL (Offset 0x0711) */ -/* 2 REG_FE4IMR (Offset 0x1130) */ +#define BIT_PCIE_CFG_L1_RIDLE_SEL BIT(6) +#define BIT_PCIE_CFG_L1_TIMEOUT_SEL BIT(5) +#define BIT_PCIE_CFG_L1_EIDLE_SEL BIT(4) -#define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10) +#define BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE 0xf +#define BIT_PCIE_CFG_DEFAULT_LINK_RATE(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) +#define BITS_PCIE_CFG_DEFAULT_LINK_RATE \ + (BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_LINK_RATE)) +#define BIT_GET_PCIE_CFG_DEFAULT_LINK_RATE(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) & \ + BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE) +#define BIT_SET_PCIE_CFG_DEFAULT_LINK_RATE(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x) | \ + BIT_PCIE_CFG_DEFAULT_LINK_RATE(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */ +#define BIT_SHIFT_RD_BF_SEL 29 +#define BIT_MASK_RD_BF_SEL 0x7 +#define BIT_RD_BF_SEL(x) (((x) & BIT_MASK_RD_BF_SEL) << BIT_SHIFT_RD_BF_SEL) +#define BITS_RD_BF_SEL (BIT_MASK_RD_BF_SEL << BIT_SHIFT_RD_BF_SEL) +#define BIT_CLEAR_RD_BF_SEL(x) ((x) & (~BITS_RD_BF_SEL)) +#define BIT_GET_RD_BF_SEL(x) (((x) >> BIT_SHIFT_RD_BF_SEL) & BIT_MASK_RD_BF_SEL) +#define BIT_SET_RD_BF_SEL(x, v) (BIT_CLEAR_RD_BF_SEL(x) | BIT_RD_BF_SEL(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT3_RXBCMD0_OK_INT_EN BIT(9) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24 +#define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff +#define BIT_NDP_RX_STANDBY_TIMER(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER) +#define BITS_NDP_RX_STANDBY_TIMER \ + (BIT_MASK_NDP_RX_STANDBY_TIMER << BIT_SHIFT_NDP_RX_STANDBY_TIMER) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) ((x) & (~BITS_NDP_RX_STANDBY_TIMER)) +#define BIT_GET_NDP_RX_STANDBY_TIMER(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER) +#define BIT_SET_NDP_RX_STANDBY_TIMER(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) | BIT_NDP_RX_STANDBY_TIMER(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ -#define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9) +#define BIT_WMAC_CHK_RPTPOLL_A2_DIS BIT(23) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS BIT(23) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT3_RXBCMD1_OK_INT_EN BIT(8) +#if (HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_WMAC_CHK_UCNDPA_A2_DIS BIT(22) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ -#define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8) +#define BIT_R_WMAC_CHK_UCNDPA_A2_DIS BIT(22) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_ANTTRN_SWITCH BIT(19) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT2_RXUCMD0_OK_INT_EN BIT(7) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) -#endif +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_CSI_RPT_OFFSET_HT 16 +#define BIT_MASK_CSI_RPT_OFFSET_HT 0xff +#define BIT_CSI_RPT_OFFSET_HT(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT) +#define BITS_CSI_RPT_OFFSET_HT \ + (BIT_MASK_CSI_RPT_OFFSET_HT << BIT_SHIFT_CSI_RPT_OFFSET_HT) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT)) +#define BIT_GET_CSI_RPT_OFFSET_HT(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT) +#define BIT_SET_CSI_RPT_OFFSET_HT(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT(x) | BIT_CSI_RPT_OFFSET_HT(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ -#define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7) +#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1 16 +#define BIT_MASK_CSI_RPT_OFFSET_HT_V1 0x3f +#define BIT_CSI_RPT_OFFSET_HT_V1(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) +#define BITS_CSI_RPT_OFFSET_HT_V1 \ + (BIT_MASK_CSI_RPT_OFFSET_HT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1)) +#define BIT_GET_CSI_RPT_OFFSET_HT_V1(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_V1) +#define BIT_SET_CSI_RPT_OFFSET_HT_V1(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) | BIT_CSI_RPT_OFFSET_HT_V1(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_WMAC_OFFSET_RPTPOLL_EN BIT(15) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT2_RXUCMD1_OK_INT_EN BIT(6) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_WMAC_OFFSET_RPTPOLL_EN BIT(15) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ -#define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6) +#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL BIT(15) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_WMAC_CSI_CHKSUM_DIS BIT(14) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT2_RXBCMD0_OK_INT_EN BIT(5) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_WMAC_CSI_CHKSUM_DIS BIT(14) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8822B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ -#define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS BIT(14) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8 +#define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff +#define BIT_R_WMAC_VHT_CATEGORY(x) \ + (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY) +#define BITS_R_WMAC_VHT_CATEGORY \ + (BIT_MASK_R_WMAC_VHT_CATEGORY << BIT_SHIFT_R_WMAC_VHT_CATEGORY) +#define BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) ((x) & (~BITS_R_WMAC_VHT_CATEGORY)) +#define BIT_GET_R_WMAC_VHT_CATEGORY(x) \ + (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY) +#define BIT_SET_R_WMAC_VHT_CATEGORY(x, v) \ + (BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) | BIT_R_WMAC_VHT_CATEGORY(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT2_RXBCMD1_OK_INT_EN BIT(4) +#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_CSI_RPT_OFFSET_VHT 8 +#define BIT_MASK_CSI_RPT_OFFSET_VHT 0xff +#define BIT_CSI_RPT_OFFSET_VHT(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT) << BIT_SHIFT_CSI_RPT_OFFSET_VHT) +#define BITS_CSI_RPT_OFFSET_VHT \ + (BIT_MASK_CSI_RPT_OFFSET_VHT << BIT_SHIFT_CSI_RPT_OFFSET_VHT) +#define BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT)) +#define BIT_GET_CSI_RPT_OFFSET_VHT(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT) & BIT_MASK_CSI_RPT_OFFSET_VHT) +#define BIT_SET_CSI_RPT_OFFSET_VHT(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) | BIT_CSI_RPT_OFFSET_VHT(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ -#define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4) +#define BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1 8 +#define BIT_MASK_CSI_RPT_OFFSET_VHT_V1 0x3f +#define BIT_CSI_RPT_OFFSET_VHT_V1(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_V1) \ + << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) +#define BITS_CSI_RPT_OFFSET_VHT_V1 \ + (BIT_MASK_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) +#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT_V1)) +#define BIT_GET_CSI_RPT_OFFSET_VHT_V1(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) & \ + BIT_MASK_CSI_RPT_OFFSET_VHT_V1) +#define BIT_SET_CSI_RPT_OFFSET_VHT_V1(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) | BIT_CSI_RPT_OFFSET_VHT_V1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1 8 +#define BIT_MASK_R_WMAC_VHT_CATEGORY_V1 0x3f +#define BIT_R_WMAC_VHT_CATEGORY_V1(x) \ + (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1) \ + << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) +#define BITS_R_WMAC_VHT_CATEGORY_V1 \ + (BIT_MASK_R_WMAC_VHT_CATEGORY_V1 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) +#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x) \ + ((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1)) +#define BIT_GET_R_WMAC_VHT_CATEGORY_V1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) & \ + BIT_MASK_R_WMAC_VHT_CATEGORY_V1) +#define BIT_SET_R_WMAC_VHT_CATEGORY_V1(x, v) \ + (BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x) | BIT_R_WMAC_VHT_CATEGORY_V1(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT1_RXUCMD0_OK_INT_EN BIT(3) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1 8 +#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 0x3f +#define BIT_R_CSI_RPT_OFFSET_VHT_V1(x) \ + (((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1) \ + << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) +#define BITS_R_CSI_RPT_OFFSET_VHT_V1 \ + (BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) +#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x) \ + ((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1)) +#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1(x) \ + (((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) & \ + BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1) +#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1(x, v) \ + (BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x) | BIT_R_CSI_RPT_OFFSET_VHT_V1(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ -#define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3) +#define BIT_R_WMAC_USE_NSTS BIT(7) +#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */ +#define BIT_PCIE_CFG_REAL_PTM_ENABLE BIT(6) -/* 2 REG_FE4IMR (Offset 0x1130) */ +#endif -#define BIT_PORT1_RXUCMD1_OK_INT_EN BIT(2) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */ -#define BIT_FS_DMEM1_WPTR_UPDATE_INT_EN BIT(2) +#define BIT_PCIE_CFG_REAL_EN_L1SUB BIT(5) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ +#define BIT_R_WMAC_BFPARAM_SEL BIT(4) +#define BIT_R_WMAC_CSISEQ_SEL BIT(3) +#define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2) +#define BIT_R_WMAC_HT_NDPA_EN BIT(1) +#define BIT_R_WMAC_VHT_NDPA_EN BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */ + +#define BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM 0 +#define BIT_MASK_PCIE_CFG_MAX_FUNC_NUM 0x7 +#define BIT_PCIE_CFG_MAX_FUNC_NUM(x) \ + (((x) & BIT_MASK_PCIE_CFG_MAX_FUNC_NUM) \ + << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) +#define BITS_PCIE_CFG_MAX_FUNC_NUM \ + (BIT_MASK_PCIE_CFG_MAX_FUNC_NUM << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) +#define BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) ((x) & (~BITS_PCIE_CFG_MAX_FUNC_NUM)) +#define BIT_GET_PCIE_CFG_MAX_FUNC_NUM(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) & \ + BIT_MASK_PCIE_CFG_MAX_FUNC_NUM) +#define BIT_SET_PCIE_CFG_MAX_FUNC_NUM(x, v) \ + (BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) | BIT_PCIE_CFG_MAX_FUNC_NUM(v)) + +/* 2 REG_PCIE_CFG_FORCE_CLKREQ_N_PAD (Offset 0x0719) */ + +#define BIT_PCIE_CFG_REAL_EN_64BITS BIT(5) +#define BIT_PCIE_CFG_REAL_EN_CLKREQ BIT(4) +#define BIT_PCIE_CFG_REAL_EN_L1 BIT(3) +#define BIT_PCIE_CFG_WAKE_N_EN BIT(2) +#define BIT_PCIE_CFG_BYPASS_LTR_OPTION BIT(1) +#define BIT_PCIE_CFG_FORCE_CLKREQ_N_PAD BIT(0) + +/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY (Offset 0x071A) */ + +#define BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK 0 +#define BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK 0xff +#define BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \ + (((x) & BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK) \ + << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) +#define BITS_PCIE_CFG_TIMER_MOD_ACK_NAK \ + (BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK \ + << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) +#define BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \ + ((x) & (~BITS_PCIE_CFG_TIMER_MOD_ACK_NAK)) +#define BIT_GET_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) & \ + BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK) +#define BIT_SET_PCIE_CFG_TIMER_MOD_ACK_NAK(x, v) \ + (BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x) | \ + BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(v)) + +/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG (Offset 0x071B) */ + +#define BIT_PCIE_CFG_BYPASS_L1_SUBSTATE_OPTION BIT(7) + +#define BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR 5 +#define BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR 0x3 +#define BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \ + (((x) & BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR) \ + << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) +#define BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR \ + (BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR \ + << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) +#define BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \ + ((x) & (~BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR)) +#define BIT_GET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) & \ + BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR) +#define BIT_SET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x, v) \ + (BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) | \ + BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(v)) + +#define BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER 0 +#define BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER 0x1f +#define BIT_PCIE_CFG_UPDATE_FREQ_TIMER(x) \ + (((x) & BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER) \ + << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) +#define BITS_PCIE_CFG_UPDATE_FREQ_TIMER \ + (BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER \ + << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) +#define BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x) \ + ((x) & (~BITS_PCIE_CFG_UPDATE_FREQ_TIMER)) +#define BIT_GET_PCIE_CFG_UPDATE_FREQ_TIMER(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) & \ + BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER) +#define BIT_SET_PCIE_CFG_UPDATE_FREQ_TIMER(x, v) \ + (BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x) | \ + BIT_PCIE_CFG_UPDATE_FREQ_TIMER(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */ -#define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2) +#define BIT_WMAC_CHECK_SOUNDING_SEQ BIT(30) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_L (Offset 0x071C) */ +#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L 0 +#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L 0xff +#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \ + (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L) \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) +#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L \ + (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) +#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \ + ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L)) +#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) & \ + BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L) +#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x, v) \ + (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) | \ + BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(v)) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_H (Offset 0x071D) */ -#define BIT_PORT1_RXBCMD0_OK_INT_EN BIT(1) +#define BIT_PCIE_CFG_DISABLE_FC_WATCHDOG_TIMER BIT(7) + +#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H 0 +#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H 0x7 +#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \ + (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H) \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) +#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H \ + (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) +#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \ + ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H)) +#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) & \ + BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H) +#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x, v) \ + (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) | \ + BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_NS_ARP_CTRL (Offset 0x0720) */ +#define BIT_R_WMAC_NSARP_RSPEN BIT(15) +#define BIT_R_WMAC_NSARP_RARP BIT(9) +#define BIT_R_WMAC_NSARP_RIPV6 BIT(8) + +#define BIT_SHIFT_R_WMAC_NSARP_MODEN 6 +#define BIT_MASK_R_WMAC_NSARP_MODEN 0x3 +#define BIT_R_WMAC_NSARP_MODEN(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN) +#define BITS_R_WMAC_NSARP_MODEN \ + (BIT_MASK_R_WMAC_NSARP_MODEN << BIT_SHIFT_R_WMAC_NSARP_MODEN) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN(x) ((x) & (~BITS_R_WMAC_NSARP_MODEN)) +#define BIT_GET_R_WMAC_NSARP_MODEN(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN) +#define BIT_SET_R_WMAC_NSARP_MODEN(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN(x) | BIT_R_WMAC_NSARP_MODEN(v)) + +#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4 +#define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3 +#define BIT_R_WMAC_NSARP_RSPFTP(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP) +#define BITS_R_WMAC_NSARP_RSPFTP \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP << BIT_SHIFT_R_WMAC_NSARP_RSPFTP) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) ((x) & (~BITS_R_WMAC_NSARP_RSPFTP)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP) +#define BIT_SET_R_WMAC_NSARP_RSPFTP(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) | BIT_R_WMAC_NSARP_RSPFTP(v)) + +#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0 +#define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf +#define BIT_R_WMAC_NSARP_RSPSEC(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC) +#define BITS_R_WMAC_NSARP_RSPSEC \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC << BIT_SHIFT_R_WMAC_NSARP_RSPSEC) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) ((x) & (~BITS_R_WMAC_NSARP_RSPSEC)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC) +#define BIT_SET_R_WMAC_NSARP_RSPSEC(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) | BIT_R_WMAC_NSARP_RSPSEC(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_NS_ARP_INFO (Offset 0x0724) */ -#define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1) +#define BIT_REQ_IS_MCNS BIT(23) +#define BIT_REQ_IS_UCNS BIT(22) +#define BIT_REQ_IS_USNS BIT(21) +#define BIT_REQ_IS_ARP BIT(20) +#define BIT_EXPRSP_MH_WITHQC BIT(19) + +#define BIT_SHIFT_EXPRSP_SECTYPE 16 +#define BIT_MASK_EXPRSP_SECTYPE 0x7 +#define BIT_EXPRSP_SECTYPE(x) \ + (((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE) +#define BITS_EXPRSP_SECTYPE \ + (BIT_MASK_EXPRSP_SECTYPE << BIT_SHIFT_EXPRSP_SECTYPE) +#define BIT_CLEAR_EXPRSP_SECTYPE(x) ((x) & (~BITS_EXPRSP_SECTYPE)) +#define BIT_GET_EXPRSP_SECTYPE(x) \ + (((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE) +#define BIT_SET_EXPRSP_SECTYPE(x, v) \ + (BIT_CLEAR_EXPRSP_SECTYPE(x) | BIT_EXPRSP_SECTYPE(v)) + +#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8 +#define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff +#define BIT_EXPRSP_CHKSM_7_TO_0(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) +#define BITS_EXPRSP_CHKSM_7_TO_0 \ + (BIT_MASK_EXPRSP_CHKSM_7_TO_0 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) +#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0)) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) +#define BIT_SET_EXPRSP_CHKSM_7_TO_0(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) | BIT_EXPRSP_CHKSM_7_TO_0(v)) + +#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0 +#define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff +#define BIT_EXPRSP_CHKSM_15_TO_8(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) +#define BITS_EXPRSP_CHKSM_15_TO_8 \ + (BIT_MASK_EXPRSP_CHKSM_15_TO_8 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) +#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8)) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) & \ + BIT_MASK_EXPRSP_CHKSM_15_TO_8) +#define BIT_SET_EXPRSP_CHKSM_15_TO_8(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) | BIT_EXPRSP_CHKSM_15_TO_8(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_PCIE_CFG_L1_UNIT_SEL (Offset 0x0724) */ + +#define BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL 0 +#define BIT_MASK_PCIE_CFG_L1_UNIT_SEL 0xff +#define BIT_PCIE_CFG_L1_UNIT_SEL(x) \ + (((x) & BIT_MASK_PCIE_CFG_L1_UNIT_SEL) \ + << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) +#define BITS_PCIE_CFG_L1_UNIT_SEL \ + (BIT_MASK_PCIE_CFG_L1_UNIT_SEL << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) +#define BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) ((x) & (~BITS_PCIE_CFG_L1_UNIT_SEL)) +#define BIT_GET_PCIE_CFG_L1_UNIT_SEL(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) & \ + BIT_MASK_PCIE_CFG_L1_UNIT_SEL) +#define BIT_SET_PCIE_CFG_L1_UNIT_SEL(x, v) \ + (BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) | BIT_PCIE_CFG_L1_UNIT_SEL(v)) + +/* 2 REG_PCIE_CFG_MIN_CLKREQ_SEL (Offset 0x0725) */ + +#define BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL 0 +#define BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL 0xf +#define BIT_PCIE_CFG_MIN_CLKREQ_SEL(x) \ + (((x) & BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL) \ + << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) +#define BITS_PCIE_CFG_MIN_CLKREQ_SEL \ + (BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) +#define BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x) \ + ((x) & (~BITS_PCIE_CFG_MIN_CLKREQ_SEL)) +#define BIT_GET_PCIE_CFG_MIN_CLKREQ_SEL(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) & \ + BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL) +#define BIT_SET_PCIE_CFG_MIN_CLKREQ_SEL(x, v) \ + (BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x) | BIT_PCIE_CFG_MIN_CLKREQ_SEL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BEAMFORMING_INFO_NSARP_V1 (Offset 0x0728) */ +#define BIT_SHIFT_WMAC_ARPIP 0 +#define BIT_MASK_WMAC_ARPIP 0xffffffffL +#define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP) +#define BITS_WMAC_ARPIP (BIT_MASK_WMAC_ARPIP << BIT_SHIFT_WMAC_ARPIP) +#define BIT_CLEAR_WMAC_ARPIP(x) ((x) & (~BITS_WMAC_ARPIP)) +#define BIT_GET_WMAC_ARPIP(x) \ + (((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP) +#define BIT_SET_WMAC_ARPIP(x, v) (BIT_CLEAR_WMAC_ARPIP(x) | BIT_WMAC_ARPIP(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ -#define BIT_PORT1_RXBCMD1_OK_INT_EN BIT(0) +#define BIT_SHIFT_UPD_BFMEE_USERID 13 +#define BIT_MASK_UPD_BFMEE_USERID 0x7 +#define BIT_UPD_BFMEE_USERID(x) \ + (((x) & BIT_MASK_UPD_BFMEE_USERID) << BIT_SHIFT_UPD_BFMEE_USERID) +#define BITS_UPD_BFMEE_USERID \ + (BIT_MASK_UPD_BFMEE_USERID << BIT_SHIFT_UPD_BFMEE_USERID) +#define BIT_CLEAR_UPD_BFMEE_USERID(x) ((x) & (~BITS_UPD_BFMEE_USERID)) +#define BIT_GET_UPD_BFMEE_USERID(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_USERID) & BIT_MASK_UPD_BFMEE_USERID) +#define BIT_SET_UPD_BFMEE_USERID(x, v) \ + (BIT_CLEAR_UPD_BFMEE_USERID(x) | BIT_UPD_BFMEE_USERID(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FE4IMR (Offset 0x1130) */ +/* 2 REG_RX_CSI_RPT_INFO_V1 (Offset 0x072C) */ -#define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0) +#define BIT_WRITE_USERID BIT(12) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ +#define BIT_UPD_BFMEE_FBTP BIT(12) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT4_PKTIN_INT BIT(19) +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_RX_CSI_RPT_INFO_V1 (Offset 0x072C) */ +#define BIT_SHIFT_WRITE_BW 10 +#define BIT_MASK_WRITE_BW 0x3 +#define BIT_WRITE_BW(x) (((x) & BIT_MASK_WRITE_BW) << BIT_SHIFT_WRITE_BW) +#define BITS_WRITE_BW (BIT_MASK_WRITE_BW << BIT_SHIFT_WRITE_BW) +#define BIT_CLEAR_WRITE_BW(x) ((x) & (~BITS_WRITE_BW)) +#define BIT_GET_WRITE_BW(x) (((x) >> BIT_SHIFT_WRITE_BW) & BIT_MASK_WRITE_BW) +#define BIT_SET_WRITE_BW(x, v) (BIT_CLEAR_WRITE_BW(x) | BIT_WRITE_BW(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_WRITE_CB 8 +#define BIT_MASK_WRITE_CB 0x3 +#define BIT_WRITE_CB(x) (((x) & BIT_MASK_WRITE_CB) << BIT_SHIFT_WRITE_CB) +#define BITS_WRITE_CB (BIT_MASK_WRITE_CB << BIT_SHIFT_WRITE_CB) +#define BIT_CLEAR_WRITE_CB(x) ((x) & (~BITS_WRITE_CB)) +#define BIT_GET_WRITE_CB(x) (((x) >> BIT_SHIFT_WRITE_CB) & BIT_MASK_WRITE_CB) +#define BIT_SET_WRITE_CB(x, v) (BIT_CLEAR_WRITE_CB(x) | BIT_WRITE_CB(v)) + +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ -#define BIT_FS_CLI3_TXPKTIN_INT BIT(19) +#define BIT_SHIFT_UPD_BFMEE_CB 8 +#define BIT_MASK_UPD_BFMEE_CB 0x3 +#define BIT_UPD_BFMEE_CB(x) \ + (((x) & BIT_MASK_UPD_BFMEE_CB) << BIT_SHIFT_UPD_BFMEE_CB) +#define BITS_UPD_BFMEE_CB (BIT_MASK_UPD_BFMEE_CB << BIT_SHIFT_UPD_BFMEE_CB) +#define BIT_CLEAR_UPD_BFMEE_CB(x) ((x) & (~BITS_UPD_BFMEE_CB)) +#define BIT_GET_UPD_BFMEE_CB(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_CB) & BIT_MASK_UPD_BFMEE_CB) +#define BIT_SET_UPD_BFMEE_CB(x, v) \ + (BIT_CLEAR_UPD_BFMEE_CB(x) | BIT_UPD_BFMEE_CB(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_RX_CSI_RPT_INFO_V1 (Offset 0x072C) */ +#define BIT_SHIFT_WRITE_GROUPING 6 +#define BIT_MASK_WRITE_GROUPING 0x3 +#define BIT_WRITE_GROUPING(x) \ + (((x) & BIT_MASK_WRITE_GROUPING) << BIT_SHIFT_WRITE_GROUPING) +#define BITS_WRITE_GROUPING \ + (BIT_MASK_WRITE_GROUPING << BIT_SHIFT_WRITE_GROUPING) +#define BIT_CLEAR_WRITE_GROUPING(x) ((x) & (~BITS_WRITE_GROUPING)) +#define BIT_GET_WRITE_GROUPING(x) \ + (((x) >> BIT_SHIFT_WRITE_GROUPING) & BIT_MASK_WRITE_GROUPING) +#define BIT_SET_WRITE_GROUPING(x, v) \ + (BIT_CLEAR_WRITE_GROUPING(x) | BIT_WRITE_GROUPING(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT3_PKTIN_INT BIT(18) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ +#define BIT_SHIFT_UPD_BFMEE_NG 6 +#define BIT_MASK_UPD_BFMEE_NG 0x3 +#define BIT_UPD_BFMEE_NG(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NG) << BIT_SHIFT_UPD_BFMEE_NG) +#define BITS_UPD_BFMEE_NG (BIT_MASK_UPD_BFMEE_NG << BIT_SHIFT_UPD_BFMEE_NG) +#define BIT_CLEAR_UPD_BFMEE_NG(x) ((x) & (~BITS_UPD_BFMEE_NG)) +#define BIT_GET_UPD_BFMEE_NG(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NG) & BIT_MASK_UPD_BFMEE_NG) +#define BIT_SET_UPD_BFMEE_NG(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NG(x) | BIT_UPD_BFMEE_NG(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_RX_CSI_RPT_INFO_V1 (Offset 0x072C) */ -#define BIT_FS_CLI2_TXPKTIN_INT BIT(18) +#define BIT_SHIFT_WRITE_NR 3 +#define BIT_MASK_WRITE_NR 0x7 +#define BIT_WRITE_NR(x) (((x) & BIT_MASK_WRITE_NR) << BIT_SHIFT_WRITE_NR) +#define BITS_WRITE_NR (BIT_MASK_WRITE_NR << BIT_SHIFT_WRITE_NR) +#define BIT_CLEAR_WRITE_NR(x) ((x) & (~BITS_WRITE_NR)) +#define BIT_GET_WRITE_NR(x) (((x) >> BIT_SHIFT_WRITE_NR) & BIT_MASK_WRITE_NR) +#define BIT_SET_WRITE_NR(x, v) (BIT_CLEAR_WRITE_NR(x) | BIT_WRITE_NR(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ +#define BIT_SHIFT_UPD_BFMEE_NR 3 +#define BIT_MASK_UPD_BFMEE_NR 0x7 +#define BIT_UPD_BFMEE_NR(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NR) << BIT_SHIFT_UPD_BFMEE_NR) +#define BITS_UPD_BFMEE_NR (BIT_MASK_UPD_BFMEE_NR << BIT_SHIFT_UPD_BFMEE_NR) +#define BIT_CLEAR_UPD_BFMEE_NR(x) ((x) & (~BITS_UPD_BFMEE_NR)) +#define BIT_GET_UPD_BFMEE_NR(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NR) & BIT_MASK_UPD_BFMEE_NR) +#define BIT_SET_UPD_BFMEE_NR(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NR(x) | BIT_UPD_BFMEE_NR(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT2_PKTIN_INT BIT(17) +#if (HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_RX_CSI_RPT_INFO_V1 (Offset 0x072C) */ +#define BIT_SHIFT_WRITE_NC 0 +#define BIT_MASK_WRITE_NC 0x7 +#define BIT_WRITE_NC(x) (((x) & BIT_MASK_WRITE_NC) << BIT_SHIFT_WRITE_NC) +#define BITS_WRITE_NC (BIT_MASK_WRITE_NC << BIT_SHIFT_WRITE_NC) +#define BIT_CLEAR_WRITE_NC(x) ((x) & (~BITS_WRITE_NC)) +#define BIT_GET_WRITE_NC(x) (((x) >> BIT_SHIFT_WRITE_NC) & BIT_MASK_WRITE_NC) +#define BIT_SET_WRITE_NC(x, v) (BIT_CLEAR_WRITE_NC(x) | BIT_WRITE_NC(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ -#define BIT_FS_CLI1_TXPKTIN_INT BIT(17) +#define BIT_SHIFT_BEAMFORMING_INFO 0 +#define BIT_MASK_BEAMFORMING_INFO 0xffffffffL +#define BIT_BEAMFORMING_INFO(x) \ + (((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO) +#define BITS_BEAMFORMING_INFO \ + (BIT_MASK_BEAMFORMING_INFO << BIT_SHIFT_BEAMFORMING_INFO) +#define BIT_CLEAR_BEAMFORMING_INFO(x) ((x) & (~BITS_BEAMFORMING_INFO)) +#define BIT_GET_BEAMFORMING_INFO(x) \ + (((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO) +#define BIT_SET_BEAMFORMING_INFO(x, v) \ + (BIT_CLEAR_BEAMFORMING_INFO(x) | BIT_BEAMFORMING_INFO(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ +#define BIT_SHIFT_UPD_BFMEE_BW 0 +#define BIT_MASK_UPD_BFMEE_BW 0xfff +#define BIT_UPD_BFMEE_BW(x) \ + (((x) & BIT_MASK_UPD_BFMEE_BW) << BIT_SHIFT_UPD_BFMEE_BW) +#define BITS_UPD_BFMEE_BW (BIT_MASK_UPD_BFMEE_BW << BIT_SHIFT_UPD_BFMEE_BW) +#define BIT_CLEAR_UPD_BFMEE_BW(x) ((x) & (~BITS_UPD_BFMEE_BW)) +#define BIT_GET_UPD_BFMEE_BW(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_BW) & BIT_MASK_UPD_BFMEE_BW) +#define BIT_SET_UPD_BFMEE_BW(x, v) \ + (BIT_CLEAR_UPD_BFMEE_BW(x) | BIT_UPD_BFMEE_BW(v)) + +#define BIT_SHIFT_UPD_BFMEE_NC 0 +#define BIT_MASK_UPD_BFMEE_NC 0x7 +#define BIT_UPD_BFMEE_NC(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NC) << BIT_SHIFT_UPD_BFMEE_NC) +#define BITS_UPD_BFMEE_NC (BIT_MASK_UPD_BFMEE_NC << BIT_SHIFT_UPD_BFMEE_NC) +#define BIT_CLEAR_UPD_BFMEE_NC(x) ((x) & (~BITS_UPD_BFMEE_NC)) +#define BIT_GET_UPD_BFMEE_NC(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NC) & BIT_MASK_UPD_BFMEE_NC) +#define BIT_SET_UPD_BFMEE_NC(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NC(x) | BIT_UPD_BFMEE_NC(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_IPV6 (Offset 0x0730) */ -#define BIT_PORT1_PKTIN_INT BIT(16) +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_0(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) +#define BITS_R_WMAC_IPV6_MYIPAD_0 \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_0 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_0) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_0(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) | BIT_R_WMAC_IPV6_MYIPAD_0(v)) -#endif +/* 2 REG_IPV6_1 (Offset 0x0734) */ +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_1(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) +#define BITS_R_WMAC_IPV6_MYIPAD_1 \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_1 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_1) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_1(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) | BIT_R_WMAC_IPV6_MYIPAD_1(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_IPV6_2 (Offset 0x0738) */ +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_2(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) +#define BITS_R_WMAC_IPV6_MYIPAD_2 \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_2 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_2) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_2(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) | BIT_R_WMAC_IPV6_MYIPAD_2(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_IPV6_3 (Offset 0x073C) */ -#define BIT_FS_CLI0_TXPKTIN_INT BIT(16) +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_3(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) +#define BITS_R_WMAC_IPV6_MYIPAD_3 \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_3 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_3) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_3(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) | BIT_R_WMAC_IPV6_MYIPAD_3(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */ -#define BIT_PORT4_RXUCMD0_OK_INT BIT(15) +#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4 +#define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf +#define BIT_R_WMAC_CTX_SUBTYPE(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE) +#define BITS_R_WMAC_CTX_SUBTYPE \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE << BIT_SHIFT_R_WMAC_CTX_SUBTYPE) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_CTX_SUBTYPE)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE) +#define BIT_SET_R_WMAC_CTX_SUBTYPE(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) | BIT_R_WMAC_CTX_SUBTYPE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */ +#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0 +#define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf +#define BIT_R_WMAC_RTX_SUBTYPE(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE) +#define BITS_R_WMAC_RTX_SUBTYPE \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE << BIT_SHIFT_R_WMAC_RTX_SUBTYPE) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_RTX_SUBTYPE)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE) +#define BIT_SET_R_WMAC_RTX_SUBTYPE(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) | BIT_R_WMAC_RTX_SUBTYPE(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_WMAC_SWAES_DIO_B63_B32 (Offset 0x0754) */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B63_B32 0 +#define BIT_MASK_WMAC_SWAES_DIO_B63_B32 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B63_B32(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B63_B32) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) +#define BITS_WMAC_SWAES_DIO_B63_B32 \ + (BIT_MASK_WMAC_SWAES_DIO_B63_B32 << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) +#define BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B63_B32)) +#define BIT_GET_WMAC_SWAES_DIO_B63_B32(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) & \ + BIT_MASK_WMAC_SWAES_DIO_B63_B32) +#define BIT_SET_WMAC_SWAES_DIO_B63_B32(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x) | BIT_WMAC_SWAES_DIO_B63_B32(v)) + +/* 2 REG_WMAC_SWAES_DIO_B95_B64 (Offset 0x0758) */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B95_B64 0 +#define BIT_MASK_WMAC_SWAES_DIO_B95_B64 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B95_B64(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B95_B64) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) +#define BITS_WMAC_SWAES_DIO_B95_B64 \ + (BIT_MASK_WMAC_SWAES_DIO_B95_B64 << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) +#define BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B95_B64)) +#define BIT_GET_WMAC_SWAES_DIO_B95_B64(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) & \ + BIT_MASK_WMAC_SWAES_DIO_B95_B64) +#define BIT_SET_WMAC_SWAES_DIO_B95_B64(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x) | BIT_WMAC_SWAES_DIO_B95_B64(v)) + +/* 2 REG_WMAC_SWAES_DIO_B127_B96 (Offset 0x075C) */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B127_B96 0 +#define BIT_MASK_WMAC_SWAES_DIO_B127_B96 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B127_B96(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B127_B96) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) +#define BITS_WMAC_SWAES_DIO_B127_B96 \ + (BIT_MASK_WMAC_SWAES_DIO_B127_B96 << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) +#define BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B127_B96)) +#define BIT_GET_WMAC_SWAES_DIO_B127_B96(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) & \ + BIT_MASK_WMAC_SWAES_DIO_B127_B96) +#define BIT_SET_WMAC_SWAES_DIO_B127_B96(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x) | BIT_WMAC_SWAES_DIO_B127_B96(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_WMAC_SWAES_CFG (Offset 0x0760) */ + +#define BIT_SWAES_REQ BIT(7) +#define BIT_CLR_SWAES_REQ BIT(6) +#define BIT_R_WMAC_SWAES_WE BIT(3) +#define BIT_R_WMAC_SWAES_SEL BIT(0) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_BT_COEX_V2 (Offset 0x0762) */ -#define BIT_FS_CLI3_RX_UMD0_INT BIT(15) +#define BIT_GNT_BT_POLARITY BIT(12) +#define BIT_GNT_BT_BYPASS_PRIORITY BIT(8) -#endif +#define BIT_SHIFT_TIMER 0 +#define BIT_MASK_TIMER 0xff +#define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER) +#define BITS_TIMER (BIT_MASK_TIMER << BIT_SHIFT_TIMER) +#define BIT_CLEAR_TIMER(x) ((x) & (~BITS_TIMER)) +#define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER) +#define BIT_SET_TIMER(x, v) (BIT_CLEAR_TIMER(x) | BIT_TIMER(v)) +#endif -#if (HALMAC_8197F_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_BT_COEX (Offset 0x0764) */ -/* 2 REG_FE4ISR (Offset 0x1134) */ +#define BIT_R_GNT_BT_RFC_SW BIT(12) +#define BIT_R_GNT_BT_RFC_SW_EN BIT(11) +#define BIT_R_GNT_BT_BB_SW BIT(10) +#define BIT_R_GNT_BT_BB_SW_EN BIT(9) +#define BIT_R_BT_CNT_THREN BIT(8) -#define BIT_PORT4_RXUCMD1_OK_INT BIT(14) +#define BIT_SHIFT_R_BT_CNT_THR 0 +#define BIT_MASK_R_BT_CNT_THR 0xff +#define BIT_R_BT_CNT_THR(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR) +#define BITS_R_BT_CNT_THR (BIT_MASK_R_BT_CNT_THR << BIT_SHIFT_R_BT_CNT_THR) +#define BIT_CLEAR_R_BT_CNT_THR(x) ((x) & (~BITS_R_BT_CNT_THR)) +#define BIT_GET_R_BT_CNT_THR(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR) +#define BIT_SET_R_BT_CNT_THR(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR(x) | BIT_R_BT_CNT_THR(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ -#define BIT_FS_CLI3_RX_UMD1_INT BIT(14) +#define BIT_WLRX_TER_BY_CTL BIT(43) +#define BIT_WLRX_TER_BY_AD BIT(42) +#define BIT_ANT_DIVERSITY_SEL BIT(41) +#define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40) +#define BIT_WLACT_LOW_GNTWL_EN BIT(34) +#define BIT_WLACT_HIGH_GNTBT_EN BIT(33) #endif +#if (HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ +#define BIT_NAV_UPPER_V1 BIT(32) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT4_RXBCMD0_OK_INT BIT(13) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ +#define BIT_SHIFT_RXMYRTS_NAV_V1 8 +#define BIT_MASK_RXMYRTS_NAV_V1 0xff +#define BIT_RXMYRTS_NAV_V1(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1) +#define BITS_RXMYRTS_NAV_V1 \ + (BIT_MASK_RXMYRTS_NAV_V1 << BIT_SHIFT_RXMYRTS_NAV_V1) +#define BIT_CLEAR_RXMYRTS_NAV_V1(x) ((x) & (~BITS_RXMYRTS_NAV_V1)) +#define BIT_GET_RXMYRTS_NAV_V1(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1) +#define BIT_SET_RXMYRTS_NAV_V1(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1(x) | BIT_RXMYRTS_NAV_V1(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_RTSRST_V1 0 +#define BIT_MASK_RTSRST_V1 0xff +#define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1) +#define BITS_RTSRST_V1 (BIT_MASK_RTSRST_V1 << BIT_SHIFT_RTSRST_V1) +#define BIT_CLEAR_RTSRST_V1(x) ((x) & (~BITS_RTSRST_V1)) +#define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1) +#define BIT_SET_RTSRST_V1(x, v) (BIT_CLEAR_RTSRST_V1(x) | BIT_RTSRST_V1(v)) + +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_WLAN_ACT_MASK_CTRL_1 (Offset 0x076C) */ -#define BIT_FS_CLI3_RX_BMD0_INT BIT(13) +#define BIT_WLRX_TER_BY_CTL_1 BIT(11) +#define BIT_WLRX_TER_BY_AD_1 BIT(10) +#define BIT_ANT_DIVERSITY_SEL_1 BIT(9) +#define BIT_ANTSEL_FOR_BT_CTRL_EN_1 BIT(8) +#define BIT_WLACT_LOW_GNTWL_EN_1 BIT(2) +#define BIT_WLACT_HIGH_GNTBT_EN_1 BIT(1) +#define BIT_NAV_UPPER_1_V1 BIT(0) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL (Offset 0x076E) */ +#define BIT_SHIFT_BT_STAT_DELAY 12 +#define BIT_MASK_BT_STAT_DELAY 0xf +#define BIT_BT_STAT_DELAY(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY) +#define BITS_BT_STAT_DELAY (BIT_MASK_BT_STAT_DELAY << BIT_SHIFT_BT_STAT_DELAY) +#define BIT_CLEAR_BT_STAT_DELAY(x) ((x) & (~BITS_BT_STAT_DELAY)) +#define BIT_GET_BT_STAT_DELAY(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY) +#define BIT_SET_BT_STAT_DELAY(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY(x) | BIT_BT_STAT_DELAY(v)) + +#define BIT_SHIFT_BT_TRX_INIT_DETECT 8 +#define BIT_MASK_BT_TRX_INIT_DETECT 0xf +#define BIT_BT_TRX_INIT_DETECT(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT) +#define BITS_BT_TRX_INIT_DETECT \ + (BIT_MASK_BT_TRX_INIT_DETECT << BIT_SHIFT_BT_TRX_INIT_DETECT) +#define BIT_CLEAR_BT_TRX_INIT_DETECT(x) ((x) & (~BITS_BT_TRX_INIT_DETECT)) +#define BIT_GET_BT_TRX_INIT_DETECT(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT) +#define BIT_SET_BT_TRX_INIT_DETECT(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT(x) | BIT_BT_TRX_INIT_DETECT(v)) + +#define BIT_SHIFT_BT_PRI_DETECT_TO 4 +#define BIT_MASK_BT_PRI_DETECT_TO 0xf +#define BIT_BT_PRI_DETECT_TO(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO) +#define BITS_BT_PRI_DETECT_TO \ + (BIT_MASK_BT_PRI_DETECT_TO << BIT_SHIFT_BT_PRI_DETECT_TO) +#define BIT_CLEAR_BT_PRI_DETECT_TO(x) ((x) & (~BITS_BT_PRI_DETECT_TO)) +#define BIT_GET_BT_PRI_DETECT_TO(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO) +#define BIT_SET_BT_PRI_DETECT_TO(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO(x) | BIT_BT_PRI_DETECT_TO(v)) + +#define BIT_R_GRANTALL_WLMASK BIT(3) +#define BIT_STATIS_BT_EN BIT(2) +#define BIT_WL_ACT_MASK_ENABLE BIT(1) +#define BIT_ENHANCED_BT BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ -#define BIT_PORT4_RXBCMD1_OK_INT BIT(12) +#define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH) +#define BIT_MASK_STATIS_BT_LO_RX 0xffff +#define BIT_STATIS_BT_LO_RX(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX) +#define BITS_STATIS_BT_LO_RX \ + (BIT_MASK_STATIS_BT_LO_RX << BIT_SHIFT_STATIS_BT_LO_RX) +#define BIT_CLEAR_STATIS_BT_LO_RX(x) ((x) & (~BITS_STATIS_BT_LO_RX)) +#define BIT_GET_STATIS_BT_LO_RX(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX) +#define BIT_SET_STATIS_BT_LO_RX(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX(x) | BIT_STATIS_BT_LO_RX(v)) + +#define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH) +#define BIT_MASK_STATIS_BT_LO_TX 0xffff +#define BIT_STATIS_BT_LO_TX(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX) +#define BITS_STATIS_BT_LO_TX \ + (BIT_MASK_STATIS_BT_LO_TX << BIT_SHIFT_STATIS_BT_LO_TX) +#define BIT_CLEAR_STATIS_BT_LO_TX(x) ((x) & (~BITS_STATIS_BT_LO_TX)) +#define BIT_GET_STATIS_BT_LO_TX(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX) +#define BIT_SET_STATIS_BT_LO_TX(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX(x) | BIT_STATIS_BT_LO_TX(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ +#define BIT_SHIFT_STATIS_BT_HI_RX 16 +#define BIT_MASK_STATIS_BT_HI_RX 0xffff +#define BIT_STATIS_BT_HI_RX(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX) +#define BITS_STATIS_BT_HI_RX \ + (BIT_MASK_STATIS_BT_HI_RX << BIT_SHIFT_STATIS_BT_HI_RX) +#define BIT_CLEAR_STATIS_BT_HI_RX(x) ((x) & (~BITS_STATIS_BT_HI_RX)) +#define BIT_GET_STATIS_BT_HI_RX(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX) +#define BIT_SET_STATIS_BT_HI_RX(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX(x) | BIT_STATIS_BT_HI_RX(v)) + +#define BIT_SHIFT_STATIS_BT_HI_TX 0 +#define BIT_MASK_STATIS_BT_HI_TX 0xffff +#define BIT_STATIS_BT_HI_TX(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX) +#define BITS_STATIS_BT_HI_TX \ + (BIT_MASK_STATIS_BT_HI_TX << BIT_SHIFT_STATIS_BT_HI_TX) +#define BIT_CLEAR_STATIS_BT_HI_TX(x) ((x) & (~BITS_STATIS_BT_HI_TX)) +#define BIT_GET_STATIS_BT_HI_TX(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX) +#define BIT_SET_STATIS_BT_HI_TX(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX(x) | BIT_STATIS_BT_HI_TX(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BT_ACT_STATISTICS_1 (Offset 0x0774) */ +#define BIT_APPEND_MACID_IN_RESP_EN_1 BIT(18) +#define BIT_ADDR2_MATCH_EN_1 BIT(17) + +#define BIT_SHIFT_STATIS_BT_LO_RX_1 16 +#define BIT_MASK_STATIS_BT_LO_RX_1 0xffff +#define BIT_STATIS_BT_LO_RX_1(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_1) << BIT_SHIFT_STATIS_BT_LO_RX_1) +#define BITS_STATIS_BT_LO_RX_1 \ + (BIT_MASK_STATIS_BT_LO_RX_1 << BIT_SHIFT_STATIS_BT_LO_RX_1) +#define BIT_CLEAR_STATIS_BT_LO_RX_1(x) ((x) & (~BITS_STATIS_BT_LO_RX_1)) +#define BIT_GET_STATIS_BT_LO_RX_1(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1) & BIT_MASK_STATIS_BT_LO_RX_1) +#define BIT_SET_STATIS_BT_LO_RX_1(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_1(x) | BIT_STATIS_BT_LO_RX_1(v)) + +#define BIT_ANTTRN_EN_1 BIT(16) + +#define BIT_SHIFT_STATIS_BT_LO_TX_1 0 +#define BIT_MASK_STATIS_BT_LO_TX_1 0xffff +#define BIT_STATIS_BT_LO_TX_1(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_1) << BIT_SHIFT_STATIS_BT_LO_TX_1) +#define BITS_STATIS_BT_LO_TX_1 \ + (BIT_MASK_STATIS_BT_LO_TX_1 << BIT_SHIFT_STATIS_BT_LO_TX_1) +#define BIT_CLEAR_STATIS_BT_LO_TX_1(x) ((x) & (~BITS_STATIS_BT_LO_TX_1)) +#define BIT_GET_STATIS_BT_LO_TX_1(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1) & BIT_MASK_STATIS_BT_LO_TX_1) +#define BIT_SET_STATIS_BT_LO_TX_1(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_1(x) | BIT_STATIS_BT_LO_TX_1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_BT_STATISTICS_CONTROL_REGISTER (Offset 0x0778) */ -#define BIT_FS_CLI3_RX_BMD1_INT BIT(12) +#define BIT_SHIFT_R_BT_CMD_RPT 16 +#define BIT_MASK_R_BT_CMD_RPT 0xffff +#define BIT_R_BT_CMD_RPT(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT) +#define BITS_R_BT_CMD_RPT (BIT_MASK_R_BT_CMD_RPT << BIT_SHIFT_R_BT_CMD_RPT) +#define BIT_CLEAR_R_BT_CMD_RPT(x) ((x) & (~BITS_R_BT_CMD_RPT)) +#define BIT_GET_R_BT_CMD_RPT(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT) +#define BIT_SET_R_BT_CMD_RPT(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT(x) | BIT_R_BT_CMD_RPT(v)) + +#define BIT_SHIFT_R_RPT_FROM_BT 8 +#define BIT_MASK_R_RPT_FROM_BT 0xff +#define BIT_R_RPT_FROM_BT(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT) +#define BITS_R_RPT_FROM_BT (BIT_MASK_R_RPT_FROM_BT << BIT_SHIFT_R_RPT_FROM_BT) +#define BIT_CLEAR_R_RPT_FROM_BT(x) ((x) & (~BITS_R_RPT_FROM_BT)) +#define BIT_GET_R_RPT_FROM_BT(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT) +#define BIT_SET_R_RPT_FROM_BT(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT(x) | BIT_R_RPT_FROM_BT(v)) + +#define BIT_SHIFT_BT_HID_ISR_SET 6 +#define BIT_MASK_BT_HID_ISR_SET 0x3 +#define BIT_BT_HID_ISR_SET(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET) +#define BITS_BT_HID_ISR_SET \ + (BIT_MASK_BT_HID_ISR_SET << BIT_SHIFT_BT_HID_ISR_SET) +#define BIT_CLEAR_BT_HID_ISR_SET(x) ((x) & (~BITS_BT_HID_ISR_SET)) +#define BIT_GET_BT_HID_ISR_SET(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET) +#define BIT_SET_BT_HID_ISR_SET(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET(x) | BIT_BT_HID_ISR_SET(v)) + +#define BIT_TDMA_BT_START_NOTIFY BIT(5) +#define BIT_ENABLE_TDMA_FW_MODE BIT(4) +#define BIT_ENABLE_PTA_TDMA_MODE BIT(3) +#define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) +#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) +#define BIT_RTK_BT_ENABLE BIT(0) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BT_STATUS_REPORT_REGISTER (Offset 0x077C) */ +#define BIT_SHIFT_BT_PROFILE 24 +#define BIT_MASK_BT_PROFILE 0xff +#define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE) +#define BITS_BT_PROFILE (BIT_MASK_BT_PROFILE << BIT_SHIFT_BT_PROFILE) +#define BIT_CLEAR_BT_PROFILE(x) ((x) & (~BITS_BT_PROFILE)) +#define BIT_GET_BT_PROFILE(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE) +#define BIT_SET_BT_PROFILE(x, v) (BIT_CLEAR_BT_PROFILE(x) | BIT_BT_PROFILE(v)) + +#define BIT_SHIFT_BT_POWER 16 +#define BIT_MASK_BT_POWER 0xff +#define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER) +#define BITS_BT_POWER (BIT_MASK_BT_POWER << BIT_SHIFT_BT_POWER) +#define BIT_CLEAR_BT_POWER(x) ((x) & (~BITS_BT_POWER)) +#define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER) +#define BIT_SET_BT_POWER(x, v) (BIT_CLEAR_BT_POWER(x) | BIT_BT_POWER(v)) + +#define BIT_SHIFT_BT_PREDECT_STATUS 8 +#define BIT_MASK_BT_PREDECT_STATUS 0xff +#define BIT_BT_PREDECT_STATUS(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS) +#define BITS_BT_PREDECT_STATUS \ + (BIT_MASK_BT_PREDECT_STATUS << BIT_SHIFT_BT_PREDECT_STATUS) +#define BIT_CLEAR_BT_PREDECT_STATUS(x) ((x) & (~BITS_BT_PREDECT_STATUS)) +#define BIT_GET_BT_PREDECT_STATUS(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS) +#define BIT_SET_BT_PREDECT_STATUS(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS(x) | BIT_BT_PREDECT_STATUS(v)) + +#define BIT_SHIFT_BT_CMD_INFO 0 +#define BIT_MASK_BT_CMD_INFO 0xff +#define BIT_BT_CMD_INFO(x) \ + (((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO) +#define BITS_BT_CMD_INFO (BIT_MASK_BT_CMD_INFO << BIT_SHIFT_BT_CMD_INFO) +#define BIT_CLEAR_BT_CMD_INFO(x) ((x) & (~BITS_BT_CMD_INFO)) +#define BIT_GET_BT_CMD_INFO(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO) +#define BIT_SET_BT_CMD_INFO(x, v) \ + (BIT_CLEAR_BT_CMD_INFO(x) | BIT_BT_CMD_INFO(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER (Offset 0x0780) */ +#define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31) +#define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30) +#define BIT_EN_BT_STSTUS_RPT BIT(29) +#define BIT_EN_BT_POWER BIT(28) +#define BIT_EN_BT_CHANNEL BIT(27) +#define BIT_EN_BT_SLOT_CHANGE BIT(26) +#define BIT_EN_BT_PROFILE_OR_HID BIT(25) +#define BIT_WLAN_RPT_NOTIFY BIT(24) + +#define BIT_SHIFT_WLAN_RPT_DATA 16 +#define BIT_MASK_WLAN_RPT_DATA 0xff +#define BIT_WLAN_RPT_DATA(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA) +#define BITS_WLAN_RPT_DATA (BIT_MASK_WLAN_RPT_DATA << BIT_SHIFT_WLAN_RPT_DATA) +#define BIT_CLEAR_WLAN_RPT_DATA(x) ((x) & (~BITS_WLAN_RPT_DATA)) +#define BIT_GET_WLAN_RPT_DATA(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA) +#define BIT_SET_WLAN_RPT_DATA(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA(x) | BIT_WLAN_RPT_DATA(v)) + +#define BIT_SHIFT_CMD_ID 8 +#define BIT_MASK_CMD_ID 0xff +#define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID) +#define BITS_CMD_ID (BIT_MASK_CMD_ID << BIT_SHIFT_CMD_ID) +#define BIT_CLEAR_CMD_ID(x) ((x) & (~BITS_CMD_ID)) +#define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID) +#define BIT_SET_CMD_ID(x, v) (BIT_CLEAR_CMD_ID(x) | BIT_CMD_ID(v)) + +#define BIT_SHIFT_BT_DATA 0 +#define BIT_MASK_BT_DATA 0xff +#define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA) +#define BITS_BT_DATA (BIT_MASK_BT_DATA << BIT_SHIFT_BT_DATA) +#define BIT_CLEAR_BT_DATA(x) ((x) & (~BITS_BT_DATA)) +#define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA) +#define BIT_SET_BT_DATA(x, v) (BIT_CLEAR_BT_DATA(x) | BIT_BT_DATA(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */ -#define BIT_PORT3_RXUCMD0_OK_INT BIT(11) +#define BIT_SHIFT_WLAN_RPT_TO 0 +#define BIT_MASK_WLAN_RPT_TO 0xff +#define BIT_WLAN_RPT_TO(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO) +#define BITS_WLAN_RPT_TO (BIT_MASK_WLAN_RPT_TO << BIT_SHIFT_WLAN_RPT_TO) +#define BIT_CLEAR_WLAN_RPT_TO(x) ((x) & (~BITS_WLAN_RPT_TO)) +#define BIT_GET_WLAN_RPT_TO(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO) +#define BIT_SET_WLAN_RPT_TO(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO(x) | BIT_WLAN_RPT_TO(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ +#define BIT_SHIFT_ISOLATION_CHK_0 1 +#define BIT_MASK_ISOLATION_CHK_0 0x7fffff +#define BIT_ISOLATION_CHK_0(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_0) << BIT_SHIFT_ISOLATION_CHK_0) +#define BITS_ISOLATION_CHK_0 \ + (BIT_MASK_ISOLATION_CHK_0 << BIT_SHIFT_ISOLATION_CHK_0) +#define BIT_CLEAR_ISOLATION_CHK_0(x) ((x) & (~BITS_ISOLATION_CHK_0)) +#define BIT_GET_ISOLATION_CHK_0(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_0) & BIT_MASK_ISOLATION_CHK_0) +#define BIT_SET_ISOLATION_CHK_0(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_0(x) | BIT_ISOLATION_CHK_0(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_FS_CLI2_RX_UMD0_INT BIT(11) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ +#define BIT_SHIFT_ISOLATION_CHK 1 +#define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL +#define BIT_ISOLATION_CHK(x) \ + (((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK) +#define BITS_ISOLATION_CHK (BIT_MASK_ISOLATION_CHK << BIT_SHIFT_ISOLATION_CHK) +#define BIT_CLEAR_ISOLATION_CHK(x) ((x) & (~BITS_ISOLATION_CHK)) +#define BIT_GET_ISOLATION_CHK(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK) +#define BIT_SET_ISOLATION_CHK(x, v) \ + (BIT_CLEAR_ISOLATION_CHK(x) | BIT_ISOLATION_CHK(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ + +#define BIT_ISOLATION_EN BIT(0) -#define BIT_PORT3_RXUCMD1_OK_INT BIT(10) +#define BIT_SHIFT_R_CCK_LEN 0 +#define BIT_MASK_R_CCK_LEN 0xffff +#define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN) +#define BITS_R_CCK_LEN (BIT_MASK_R_CCK_LEN << BIT_SHIFT_R_CCK_LEN) +#define BIT_CLEAR_R_CCK_LEN(x) ((x) & (~BITS_R_CCK_LEN)) +#define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN) +#define BIT_SET_R_CCK_LEN(x, v) (BIT_CLEAR_R_CCK_LEN(x) | BIT_R_CCK_LEN(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 (Offset 0x0788) */ +#define BIT_SHIFT_ISOLATION_CHK_1 0 +#define BIT_MASK_ISOLATION_CHK_1 0xffffffffL +#define BIT_ISOLATION_CHK_1(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_1) << BIT_SHIFT_ISOLATION_CHK_1) +#define BITS_ISOLATION_CHK_1 \ + (BIT_MASK_ISOLATION_CHK_1 << BIT_SHIFT_ISOLATION_CHK_1) +#define BIT_CLEAR_ISOLATION_CHK_1(x) ((x) & (~BITS_ISOLATION_CHK_1)) +#define BIT_GET_ISOLATION_CHK_1(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_1) & BIT_MASK_ISOLATION_CHK_1) +#define BIT_SET_ISOLATION_CHK_1(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_1(x) | BIT_ISOLATION_CHK_1(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 (Offset 0x078C) */ -#define BIT_FS_CLI2_RX_UMD1_INT BIT(10) +#define BIT_SHIFT_ISOLATION_CHK_2 0 +#define BIT_MASK_ISOLATION_CHK_2 0xffffff +#define BIT_ISOLATION_CHK_2(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_2) << BIT_SHIFT_ISOLATION_CHK_2) +#define BITS_ISOLATION_CHK_2 \ + (BIT_MASK_ISOLATION_CHK_2 << BIT_SHIFT_ISOLATION_CHK_2) +#define BIT_CLEAR_ISOLATION_CHK_2(x) ((x) & (~BITS_ISOLATION_CHK_2)) +#define BIT_GET_ISOLATION_CHK_2(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_2) & BIT_MASK_ISOLATION_CHK_2) +#define BIT_SET_ISOLATION_CHK_2(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_2(x) | BIT_ISOLATION_CHK_2(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BT_INTERRUPT_STATUS_REGISTER (Offset 0x078F) */ +#define BIT_BT_HID_ISR BIT(7) +#define BIT_BT_QUERY_ISR BIT(6) +#define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5) +#define BIT_WLAN_RPT_ISR BIT(4) +#define BIT_BT_POWER_ISR BIT(3) +#define BIT_BT_CHANNEL_ISR BIT(2) +#define BIT_BT_SLOT_CHANGE_ISR BIT(1) +#define BIT_BT_PROFILE_ISR BIT(0) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_BT_TDMA_TIME_REGISTER (Offset 0x0790) */ -#define BIT_PORT3_RXBCMD0_OK_INT BIT(9) +#define BIT_SHIFT_BT_TIME 6 +#define BIT_MASK_BT_TIME 0x3ffffff +#define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME) +#define BITS_BT_TIME (BIT_MASK_BT_TIME << BIT_SHIFT_BT_TIME) +#define BIT_CLEAR_BT_TIME(x) ((x) & (~BITS_BT_TIME)) +#define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME) +#define BIT_SET_BT_TIME(x, v) (BIT_CLEAR_BT_TIME(x) | BIT_BT_TIME(v)) + +#define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0 +#define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f +#define BIT_BT_RPT_SAMPLE_RATE(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE) +#define BITS_BT_RPT_SAMPLE_RATE \ + (BIT_MASK_BT_RPT_SAMPLE_RATE << BIT_SHIFT_BT_RPT_SAMPLE_RATE) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) ((x) & (~BITS_BT_RPT_SAMPLE_RATE)) +#define BIT_GET_BT_RPT_SAMPLE_RATE(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE) +#define BIT_SET_BT_RPT_SAMPLE_RATE(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) | BIT_BT_RPT_SAMPLE_RATE(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ +#define BIT_SHIFT_R_OFDM_LEN 26 +#define BIT_MASK_R_OFDM_LEN 0x3f +#define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN) +#define BITS_R_OFDM_LEN (BIT_MASK_R_OFDM_LEN << BIT_SHIFT_R_OFDM_LEN) +#define BIT_CLEAR_R_OFDM_LEN(x) ((x) & (~BITS_R_OFDM_LEN)) +#define BIT_GET_R_OFDM_LEN(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN) +#define BIT_SET_R_OFDM_LEN(x, v) (BIT_CLEAR_R_OFDM_LEN(x) | BIT_R_OFDM_LEN(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_FS_CLI2_RX_BMD0_INT BIT(9) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ +#define BIT_SHIFT_BT_EISR_EN 16 +#define BIT_MASK_BT_EISR_EN 0xff +#define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN) +#define BITS_BT_EISR_EN (BIT_MASK_BT_EISR_EN << BIT_SHIFT_BT_EISR_EN) +#define BIT_CLEAR_BT_EISR_EN(x) ((x) & (~BITS_BT_EISR_EN)) +#define BIT_GET_BT_EISR_EN(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN) +#define BIT_SET_BT_EISR_EN(x, v) (BIT_CLEAR_BT_EISR_EN(x) | BIT_BT_EISR_EN(v)) -#if (HALMAC_8197F_SUPPORT) +#define BIT_BT_ACT_FALLING_ISR BIT(10) +#define BIT_BT_ACT_RISING_ISR BIT(9) +#define BIT_TDMA_TO_ISR BIT(8) +#endif -/* 2 REG_FE4ISR (Offset 0x1134) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) + +/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ -#define BIT_PORT3_RXBCMD1_OK_INT BIT(8) +#define BIT_SHIFT_BT_CH 0 +#define BIT_MASK_BT_CH 0xff +#define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH) +#define BITS_BT_CH (BIT_MASK_BT_CH << BIT_SHIFT_BT_CH) +#define BIT_CLEAR_BT_CH(x) ((x) & (~BITS_BT_CH)) +#define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH) +#define BIT_SET_BT_CH(x, v) (BIT_CLEAR_BT_CH(x) | BIT_BT_CH(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ +#define BIT_SHIFT_BT_CH_V1 0 +#define BIT_MASK_BT_CH_V1 0x7f +#define BIT_BT_CH_V1(x) (((x) & BIT_MASK_BT_CH_V1) << BIT_SHIFT_BT_CH_V1) +#define BITS_BT_CH_V1 (BIT_MASK_BT_CH_V1 << BIT_SHIFT_BT_CH_V1) +#define BIT_CLEAR_BT_CH_V1(x) ((x) & (~BITS_BT_CH_V1)) +#define BIT_GET_BT_CH_V1(x) (((x) >> BIT_SHIFT_BT_CH_V1) & BIT_MASK_BT_CH_V1) +#define BIT_SET_BT_CH_V1(x, v) (BIT_CLEAR_BT_CH_V1(x) | BIT_BT_CH_V1(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_FS_CLI2_RX_BMD1_INT BIT(8) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_OBFF_CTRL_BASIC (Offset 0x0798) */ +#define BIT_OBFF_EN_V1 BIT(31) + +#define BIT_SHIFT_OBFF_STATE_V1 28 +#define BIT_MASK_OBFF_STATE_V1 0x3 +#define BIT_OBFF_STATE_V1(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1) +#define BITS_OBFF_STATE_V1 (BIT_MASK_OBFF_STATE_V1 << BIT_SHIFT_OBFF_STATE_V1) +#define BIT_CLEAR_OBFF_STATE_V1(x) ((x) & (~BITS_OBFF_STATE_V1)) +#define BIT_GET_OBFF_STATE_V1(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1) +#define BIT_SET_OBFF_STATE_V1(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1(x) | BIT_OBFF_STATE_V1(v)) + +#define BIT_OBFF_ACT_RXDMA_EN BIT(27) +#define BIT_OBFF_BLOCK_INT_EN BIT(26) +#define BIT_OBFF_AUTOACT_EN BIT(25) +#define BIT_OBFF_AUTOIDLE_EN BIT(24) + +#define BIT_SHIFT_WAKE_MAX_PLS 20 +#define BIT_MASK_WAKE_MAX_PLS 0x7 +#define BIT_WAKE_MAX_PLS(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS) +#define BITS_WAKE_MAX_PLS (BIT_MASK_WAKE_MAX_PLS << BIT_SHIFT_WAKE_MAX_PLS) +#define BIT_CLEAR_WAKE_MAX_PLS(x) ((x) & (~BITS_WAKE_MAX_PLS)) +#define BIT_GET_WAKE_MAX_PLS(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS) +#define BIT_SET_WAKE_MAX_PLS(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS(x) | BIT_WAKE_MAX_PLS(v)) + +#define BIT_SHIFT_WAKE_MIN_PLS 16 +#define BIT_MASK_WAKE_MIN_PLS 0x7 +#define BIT_WAKE_MIN_PLS(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS) +#define BITS_WAKE_MIN_PLS (BIT_MASK_WAKE_MIN_PLS << BIT_SHIFT_WAKE_MIN_PLS) +#define BIT_CLEAR_WAKE_MIN_PLS(x) ((x) & (~BITS_WAKE_MIN_PLS)) +#define BIT_GET_WAKE_MIN_PLS(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS) +#define BIT_SET_WAKE_MIN_PLS(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS(x) | BIT_WAKE_MIN_PLS(v)) + +#define BIT_SHIFT_WAKE_MAX_F2F 12 +#define BIT_MASK_WAKE_MAX_F2F 0x7 +#define BIT_WAKE_MAX_F2F(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F) +#define BITS_WAKE_MAX_F2F (BIT_MASK_WAKE_MAX_F2F << BIT_SHIFT_WAKE_MAX_F2F) +#define BIT_CLEAR_WAKE_MAX_F2F(x) ((x) & (~BITS_WAKE_MAX_F2F)) +#define BIT_GET_WAKE_MAX_F2F(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F) +#define BIT_SET_WAKE_MAX_F2F(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F(x) | BIT_WAKE_MAX_F2F(v)) + +#define BIT_SHIFT_WAKE_MIN_F2F 8 +#define BIT_MASK_WAKE_MIN_F2F 0x7 +#define BIT_WAKE_MIN_F2F(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F) +#define BITS_WAKE_MIN_F2F (BIT_MASK_WAKE_MIN_F2F << BIT_SHIFT_WAKE_MIN_F2F) +#define BIT_CLEAR_WAKE_MIN_F2F(x) ((x) & (~BITS_WAKE_MIN_F2F)) +#define BIT_GET_WAKE_MIN_F2F(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F) +#define BIT_SET_WAKE_MIN_F2F(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F(x) | BIT_WAKE_MIN_F2F(v)) + +#define BIT_APP_CPU_ACT_V1 BIT(3) +#define BIT_APP_OBFF_V1 BIT(2) +#define BIT_APP_IDLE_V1 BIT(1) +#define BIT_APP_INIT_V1 BIT(0) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_OBFF_CTRL2_TIMER (Offset 0x079C) */ +#define BIT_SHIFT_RX_HIGH_TIMER_IDX 24 +#define BIT_MASK_RX_HIGH_TIMER_IDX 0x7 +#define BIT_RX_HIGH_TIMER_IDX(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX) +#define BITS_RX_HIGH_TIMER_IDX \ + (BIT_MASK_RX_HIGH_TIMER_IDX << BIT_SHIFT_RX_HIGH_TIMER_IDX) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX(x) ((x) & (~BITS_RX_HIGH_TIMER_IDX)) +#define BIT_GET_RX_HIGH_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX) +#define BIT_SET_RX_HIGH_TIMER_IDX(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX(x) | BIT_RX_HIGH_TIMER_IDX(v)) + +#define BIT_SHIFT_RX_MED_TIMER_IDX 16 +#define BIT_MASK_RX_MED_TIMER_IDX 0x7 +#define BIT_RX_MED_TIMER_IDX(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX) +#define BITS_RX_MED_TIMER_IDX \ + (BIT_MASK_RX_MED_TIMER_IDX << BIT_SHIFT_RX_MED_TIMER_IDX) +#define BIT_CLEAR_RX_MED_TIMER_IDX(x) ((x) & (~BITS_RX_MED_TIMER_IDX)) +#define BIT_GET_RX_MED_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX) +#define BIT_SET_RX_MED_TIMER_IDX(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX(x) | BIT_RX_MED_TIMER_IDX(v)) + +#define BIT_SHIFT_RX_LOW_TIMER_IDX 8 +#define BIT_MASK_RX_LOW_TIMER_IDX 0x7 +#define BIT_RX_LOW_TIMER_IDX(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX) +#define BITS_RX_LOW_TIMER_IDX \ + (BIT_MASK_RX_LOW_TIMER_IDX << BIT_SHIFT_RX_LOW_TIMER_IDX) +#define BIT_CLEAR_RX_LOW_TIMER_IDX(x) ((x) & (~BITS_RX_LOW_TIMER_IDX)) +#define BIT_GET_RX_LOW_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX) +#define BIT_SET_RX_LOW_TIMER_IDX(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX(x) | BIT_RX_LOW_TIMER_IDX(v)) + +#define BIT_SHIFT_OBFF_INT_TIMER_IDX 0 +#define BIT_MASK_OBFF_INT_TIMER_IDX 0x7 +#define BIT_OBFF_INT_TIMER_IDX(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX) +#define BITS_OBFF_INT_TIMER_IDX \ + (BIT_MASK_OBFF_INT_TIMER_IDX << BIT_SHIFT_OBFF_INT_TIMER_IDX) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX(x) ((x) & (~BITS_OBFF_INT_TIMER_IDX)) +#define BIT_GET_OBFF_INT_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX) +#define BIT_SET_OBFF_INT_TIMER_IDX(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX(x) | BIT_OBFF_INT_TIMER_IDX(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_LTR_CTRL_BASIC (Offset 0x07A0) */ -#define BIT_PORT2_RXUCMD0_OK_INT BIT(7) +#define BIT_LTR_EN_V1 BIT(31) +#define BIT_LTR_HW_EN_V1 BIT(30) +#define BIT_LRT_ACT_CTS_EN BIT(29) +#define BIT_LTR_ACT_RXPKT_EN BIT(28) +#define BIT_LTR_ACT_RXDMA_EN BIT(27) +#define BIT_LTR_IDLE_NO_SNOOP BIT(26) +#define BIT_SPDUP_MGTPKT BIT(25) +#define BIT_RX_AGG_EN BIT(24) +#define BIT_APP_LTR_ACT BIT(23) +#define BIT_APP_LTR_IDLE BIT(22) + +#define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20 +#define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3 +#define BIT_HIGH_RATE_TRIG_SEL(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL) +#define BITS_HIGH_RATE_TRIG_SEL \ + (BIT_MASK_HIGH_RATE_TRIG_SEL << BIT_SHIFT_HIGH_RATE_TRIG_SEL) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) ((x) & (~BITS_HIGH_RATE_TRIG_SEL)) +#define BIT_GET_HIGH_RATE_TRIG_SEL(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL) +#define BIT_SET_HIGH_RATE_TRIG_SEL(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) | BIT_HIGH_RATE_TRIG_SEL(v)) + +#define BIT_SHIFT_MED_RATE_TRIG_SEL 18 +#define BIT_MASK_MED_RATE_TRIG_SEL 0x3 +#define BIT_MED_RATE_TRIG_SEL(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL) +#define BITS_MED_RATE_TRIG_SEL \ + (BIT_MASK_MED_RATE_TRIG_SEL << BIT_SHIFT_MED_RATE_TRIG_SEL) +#define BIT_CLEAR_MED_RATE_TRIG_SEL(x) ((x) & (~BITS_MED_RATE_TRIG_SEL)) +#define BIT_GET_MED_RATE_TRIG_SEL(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL) +#define BIT_SET_MED_RATE_TRIG_SEL(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL(x) | BIT_MED_RATE_TRIG_SEL(v)) + +#define BIT_SHIFT_LOW_RATE_TRIG_SEL 16 +#define BIT_MASK_LOW_RATE_TRIG_SEL 0x3 +#define BIT_LOW_RATE_TRIG_SEL(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL) +#define BITS_LOW_RATE_TRIG_SEL \ + (BIT_MASK_LOW_RATE_TRIG_SEL << BIT_SHIFT_LOW_RATE_TRIG_SEL) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL(x) ((x) & (~BITS_LOW_RATE_TRIG_SEL)) +#define BIT_GET_LOW_RATE_TRIG_SEL(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL) +#define BIT_SET_LOW_RATE_TRIG_SEL(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL(x) | BIT_LOW_RATE_TRIG_SEL(v)) + +#define BIT_SHIFT_HIGH_RATE_BD_IDX 8 +#define BIT_MASK_HIGH_RATE_BD_IDX 0x7f +#define BIT_HIGH_RATE_BD_IDX(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX) +#define BITS_HIGH_RATE_BD_IDX \ + (BIT_MASK_HIGH_RATE_BD_IDX << BIT_SHIFT_HIGH_RATE_BD_IDX) +#define BIT_CLEAR_HIGH_RATE_BD_IDX(x) ((x) & (~BITS_HIGH_RATE_BD_IDX)) +#define BIT_GET_HIGH_RATE_BD_IDX(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX) +#define BIT_SET_HIGH_RATE_BD_IDX(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX(x) | BIT_HIGH_RATE_BD_IDX(v)) + +#define BIT_SHIFT_LOW_RATE_BD_IDX 0 +#define BIT_MASK_LOW_RATE_BD_IDX 0x7f +#define BIT_LOW_RATE_BD_IDX(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX) +#define BITS_LOW_RATE_BD_IDX \ + (BIT_MASK_LOW_RATE_BD_IDX << BIT_SHIFT_LOW_RATE_BD_IDX) +#define BIT_CLEAR_LOW_RATE_BD_IDX(x) ((x) & (~BITS_LOW_RATE_BD_IDX)) +#define BIT_GET_LOW_RATE_BD_IDX(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX) +#define BIT_SET_LOW_RATE_BD_IDX(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX(x) | BIT_LOW_RATE_BD_IDX(v)) -#endif +/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD (Offset 0x07A4) */ +#define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24 +#define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7 +#define BIT_RX_EMPTY_TIMER_IDX(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX) +#define BITS_RX_EMPTY_TIMER_IDX \ + (BIT_MASK_RX_EMPTY_TIMER_IDX << BIT_SHIFT_RX_EMPTY_TIMER_IDX) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) ((x) & (~BITS_RX_EMPTY_TIMER_IDX)) +#define BIT_GET_RX_EMPTY_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX) +#define BIT_SET_RX_EMPTY_TIMER_IDX(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) | BIT_RX_EMPTY_TIMER_IDX(v)) + +#define BIT_SHIFT_RX_AFULL_TH_IDX 20 +#define BIT_MASK_RX_AFULL_TH_IDX 0x7 +#define BIT_RX_AFULL_TH_IDX(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX) +#define BITS_RX_AFULL_TH_IDX \ + (BIT_MASK_RX_AFULL_TH_IDX << BIT_SHIFT_RX_AFULL_TH_IDX) +#define BIT_CLEAR_RX_AFULL_TH_IDX(x) ((x) & (~BITS_RX_AFULL_TH_IDX)) +#define BIT_GET_RX_AFULL_TH_IDX(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX) +#define BIT_SET_RX_AFULL_TH_IDX(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX(x) | BIT_RX_AFULL_TH_IDX(v)) + +#define BIT_SHIFT_RX_HIGH_TH_IDX 16 +#define BIT_MASK_RX_HIGH_TH_IDX 0x7 +#define BIT_RX_HIGH_TH_IDX(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX) +#define BITS_RX_HIGH_TH_IDX \ + (BIT_MASK_RX_HIGH_TH_IDX << BIT_SHIFT_RX_HIGH_TH_IDX) +#define BIT_CLEAR_RX_HIGH_TH_IDX(x) ((x) & (~BITS_RX_HIGH_TH_IDX)) +#define BIT_GET_RX_HIGH_TH_IDX(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX) +#define BIT_SET_RX_HIGH_TH_IDX(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX(x) | BIT_RX_HIGH_TH_IDX(v)) + +#define BIT_SHIFT_RX_MED_TH_IDX 12 +#define BIT_MASK_RX_MED_TH_IDX 0x7 +#define BIT_RX_MED_TH_IDX(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX) +#define BITS_RX_MED_TH_IDX (BIT_MASK_RX_MED_TH_IDX << BIT_SHIFT_RX_MED_TH_IDX) +#define BIT_CLEAR_RX_MED_TH_IDX(x) ((x) & (~BITS_RX_MED_TH_IDX)) +#define BIT_GET_RX_MED_TH_IDX(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX) +#define BIT_SET_RX_MED_TH_IDX(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX(x) | BIT_RX_MED_TH_IDX(v)) + +#define BIT_SHIFT_RX_LOW_TH_IDX 8 +#define BIT_MASK_RX_LOW_TH_IDX 0x7 +#define BIT_RX_LOW_TH_IDX(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX) +#define BITS_RX_LOW_TH_IDX (BIT_MASK_RX_LOW_TH_IDX << BIT_SHIFT_RX_LOW_TH_IDX) +#define BIT_CLEAR_RX_LOW_TH_IDX(x) ((x) & (~BITS_RX_LOW_TH_IDX)) +#define BIT_GET_RX_LOW_TH_IDX(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX) +#define BIT_SET_RX_LOW_TH_IDX(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX(x) | BIT_RX_LOW_TH_IDX(v)) + +#define BIT_SHIFT_LTR_SPACE_IDX 4 +#define BIT_MASK_LTR_SPACE_IDX 0x3 +#define BIT_LTR_SPACE_IDX(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX) +#define BITS_LTR_SPACE_IDX (BIT_MASK_LTR_SPACE_IDX << BIT_SHIFT_LTR_SPACE_IDX) +#define BIT_CLEAR_LTR_SPACE_IDX(x) ((x) & (~BITS_LTR_SPACE_IDX)) +#define BIT_GET_LTR_SPACE_IDX(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX) +#define BIT_SET_LTR_SPACE_IDX(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX(x) | BIT_LTR_SPACE_IDX(v)) + +#define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0 +#define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7 +#define BIT_LTR_IDLE_TIMER_IDX(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX) +#define BITS_LTR_IDLE_TIMER_IDX \ + (BIT_MASK_LTR_IDLE_TIMER_IDX << BIT_SHIFT_LTR_IDLE_TIMER_IDX) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) ((x) & (~BITS_LTR_IDLE_TIMER_IDX)) +#define BIT_GET_LTR_IDLE_TIMER_IDX(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX) +#define BIT_SET_LTR_IDLE_TIMER_IDX(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) | BIT_LTR_IDLE_TIMER_IDX(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_LTR_IDLE_LATENCY_V1 (Offset 0x07A8) */ +#define BIT_SHIFT_LTR_IDLE_L 0 +#define BIT_MASK_LTR_IDLE_L 0xffffffffL +#define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L) +#define BITS_LTR_IDLE_L (BIT_MASK_LTR_IDLE_L << BIT_SHIFT_LTR_IDLE_L) +#define BIT_CLEAR_LTR_IDLE_L(x) ((x) & (~BITS_LTR_IDLE_L)) +#define BIT_GET_LTR_IDLE_L(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L) +#define BIT_SET_LTR_IDLE_L(x, v) (BIT_CLEAR_LTR_IDLE_L(x) | BIT_LTR_IDLE_L(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */ -#define BIT_FS_CLI1_RX_UMD0_INT BIT(7) +#define BIT_SHIFT_LTR_ACT_L 0 +#define BIT_MASK_LTR_ACT_L 0xffffffffL +#define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L) +#define BITS_LTR_ACT_L (BIT_MASK_LTR_ACT_L << BIT_SHIFT_LTR_ACT_L) +#define BIT_CLEAR_LTR_ACT_L(x) ((x) & (~BITS_LTR_ACT_L)) +#define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L) +#define BIT_SET_LTR_ACT_L(x, v) (BIT_CLEAR_LTR_ACT_L(x) | BIT_LTR_ACT_L(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */ +#define BIT_SHIFT_ANT_ADDR2_1 0 +#define BIT_MASK_ANT_ADDR2_1 0xffffffffL +#define BIT_ANT_ADDR2_1(x) \ + (((x) & BIT_MASK_ANT_ADDR2_1) << BIT_SHIFT_ANT_ADDR2_1) +#define BITS_ANT_ADDR2_1 (BIT_MASK_ANT_ADDR2_1 << BIT_SHIFT_ANT_ADDR2_1) +#define BIT_CLEAR_ANT_ADDR2_1(x) ((x) & (~BITS_ANT_ADDR2_1)) +#define BIT_GET_ANT_ADDR2_1(x) \ + (((x) >> BIT_SHIFT_ANT_ADDR2_1) & BIT_MASK_ANT_ADDR2_1) +#define BIT_SET_ANT_ADDR2_1(x, v) \ + (BIT_CLEAR_ANT_ADDR2_1(x) | BIT_ANT_ADDR2_1(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT2_RXUCMD1_OK_INT BIT(6) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ + +#define BIT_APPEND_MACID_IN_RESP_EN BIT(50) +#define BIT_ADDR2_MATCH_EN BIT(49) +#define BIT_ANTTRN_EN BIT(48) + +#define BIT_SHIFT_TRAIN_STA_ADDR 0 +#define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL +#define BIT_TRAIN_STA_ADDR(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR) +#define BITS_TRAIN_STA_ADDR \ + (BIT_MASK_TRAIN_STA_ADDR << BIT_SHIFT_TRAIN_STA_ADDR) +#define BIT_CLEAR_TRAIN_STA_ADDR(x) ((x) & (~BITS_TRAIN_STA_ADDR)) +#define BIT_GET_TRAIN_STA_ADDR(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR) +#define BIT_SET_TRAIN_STA_ADDR(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR(x) | BIT_TRAIN_STA_ADDR(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ +#define BIT_SHIFT_TRAIN_STA_ADDR_0 0 +#define BIT_MASK_TRAIN_STA_ADDR_0 0xffffffffL +#define BIT_TRAIN_STA_ADDR_0(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_0) << BIT_SHIFT_TRAIN_STA_ADDR_0) +#define BITS_TRAIN_STA_ADDR_0 \ + (BIT_MASK_TRAIN_STA_ADDR_0 << BIT_SHIFT_TRAIN_STA_ADDR_0) +#define BIT_CLEAR_TRAIN_STA_ADDR_0(x) ((x) & (~BITS_TRAIN_STA_ADDR_0)) +#define BIT_GET_TRAIN_STA_ADDR_0(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0) & BIT_MASK_TRAIN_STA_ADDR_0) +#define BIT_SET_TRAIN_STA_ADDR_0(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_0(x) | BIT_TRAIN_STA_ADDR_0(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 (Offset 0x07B4) */ -#define BIT_FS_CLI1_RX_UMD1_INT BIT(6) +#define BIT_SHIFT_TRAIN_STA_ADDR_1 0 +#define BIT_MASK_TRAIN_STA_ADDR_1 0xffff +#define BIT_TRAIN_STA_ADDR_1(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_1) << BIT_SHIFT_TRAIN_STA_ADDR_1) +#define BITS_TRAIN_STA_ADDR_1 \ + (BIT_MASK_TRAIN_STA_ADDR_1 << BIT_SHIFT_TRAIN_STA_ADDR_1) +#define BIT_CLEAR_TRAIN_STA_ADDR_1(x) ((x) & (~BITS_TRAIN_STA_ADDR_1)) +#define BIT_GET_TRAIN_STA_ADDR_1(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1) & BIT_MASK_TRAIN_STA_ADDR_1) +#define BIT_SET_TRAIN_STA_ADDR_1(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_1(x) | BIT_TRAIN_STA_ADDR_1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SMART_ANT_CTRL (Offset 0x07B4) */ +#define BIT_SHIFT_ANT_ADDR2_2 0 +#define BIT_MASK_ANT_ADDR2_2 0xffff +#define BIT_ANT_ADDR2_2(x) \ + (((x) & BIT_MASK_ANT_ADDR2_2) << BIT_SHIFT_ANT_ADDR2_2) +#define BITS_ANT_ADDR2_2 (BIT_MASK_ANT_ADDR2_2 << BIT_SHIFT_ANT_ADDR2_2) +#define BIT_CLEAR_ANT_ADDR2_2(x) ((x) & (~BITS_ANT_ADDR2_2)) +#define BIT_GET_ANT_ADDR2_2(x) \ + (((x) >> BIT_SHIFT_ANT_ADDR2_2) & BIT_MASK_ANT_ADDR2_2) +#define BIT_SET_ANT_ADDR2_2(x, v) \ + (BIT_CLEAR_ANT_ADDR2_2(x) | BIT_ANT_ADDR2_2(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT2_RXBCMD0_OK_INT BIT(5) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#endif +/* 2 REG_WMAC_PKTCNT_RWD (Offset 0x07B8) */ +#define BIT_SHIFT_PKTCNT_BSSIDMAP 4 +#define BIT_MASK_PKTCNT_BSSIDMAP 0xf +#define BIT_PKTCNT_BSSIDMAP(x) \ + (((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP) +#define BITS_PKTCNT_BSSIDMAP \ + (BIT_MASK_PKTCNT_BSSIDMAP << BIT_SHIFT_PKTCNT_BSSIDMAP) +#define BIT_CLEAR_PKTCNT_BSSIDMAP(x) ((x) & (~BITS_PKTCNT_BSSIDMAP)) +#define BIT_GET_PKTCNT_BSSIDMAP(x) \ + (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP) +#define BIT_SET_PKTCNT_BSSIDMAP(x, v) \ + (BIT_CLEAR_PKTCNT_BSSIDMAP(x) | BIT_PKTCNT_BSSIDMAP(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_PKTCNT_CNTRST BIT(1) +#define BIT_PKTCNT_CNTEN BIT(0) +#endif -/* 2 REG_FE4ISR (Offset 0x1134) */ +#if (HALMAC_8814B_SUPPORT) -#define BIT_FS_CLI1_RX_BMD0_INT BIT(5) +/* 2 REG_CONTROL_FRAME_REPORT (Offset 0x07B8) */ + +#define BIT_SHIFT_CONTROL_FRAME_REPORT 0 +#define BIT_MASK_CONTROL_FRAME_REPORT 0xffffffffL +#define BIT_CONTROL_FRAME_REPORT(x) \ + (((x) & BIT_MASK_CONTROL_FRAME_REPORT) \ + << BIT_SHIFT_CONTROL_FRAME_REPORT) +#define BITS_CONTROL_FRAME_REPORT \ + (BIT_MASK_CONTROL_FRAME_REPORT << BIT_SHIFT_CONTROL_FRAME_REPORT) +#define BIT_CLEAR_CONTROL_FRAME_REPORT(x) ((x) & (~BITS_CONTROL_FRAME_REPORT)) +#define BIT_GET_CONTROL_FRAME_REPORT(x) \ + (((x) >> BIT_SHIFT_CONTROL_FRAME_REPORT) & \ + BIT_MASK_CONTROL_FRAME_REPORT) +#define BIT_SET_CONTROL_FRAME_REPORT(x, v) \ + (BIT_CLEAR_CONTROL_FRAME_REPORT(x) | BIT_CONTROL_FRAME_REPORT(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ +#define BIT_WMAC_PKTCNT_TRST BIT(9) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT2_RXBCMD1_OK_INT BIT(4) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */ +#define BIT_ALLCNTRST BIT(9) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ -#define BIT_FS_CLI1_RX_BMD1_INT BIT(4) +#define BIT_WMAC_PKTCNT_FEN BIT(8) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */ -/* 2 REG_FE4ISR (Offset 0x1134) */ +#define BIT__ALLCNTEN BIT(8) -#define BIT_PORT1_RXUCMD0_OK_INT BIT(3) +#define BIT_SHIFT_ADDR 4 +#define BIT_MASK_ADDR 0xf +#define BIT_ADDR(x) (((x) & BIT_MASK_ADDR) << BIT_SHIFT_ADDR) +#define BITS_ADDR (BIT_MASK_ADDR << BIT_SHIFT_ADDR) +#define BIT_CLEAR_ADDR(x) ((x) & (~BITS_ADDR)) +#define BIT_GET_ADDR(x) (((x) >> BIT_SHIFT_ADDR) & BIT_MASK_ADDR) +#define BIT_SET_ADDR(x, v) (BIT_CLEAR_ADDR(x) | BIT_ADDR(v)) #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ +#define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0 +#define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff +#define BIT_WMAC_PKTCNT_CFGAD(x) \ + (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD) +#define BITS_WMAC_PKTCNT_CFGAD \ + (BIT_MASK_WMAC_PKTCNT_CFGAD << BIT_SHIFT_WMAC_PKTCNT_CFGAD) +#define BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) ((x) & (~BITS_WMAC_PKTCNT_CFGAD)) +#define BIT_GET_WMAC_PKTCNT_CFGAD(x) \ + (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD) +#define BIT_SET_WMAC_PKTCNT_CFGAD(x, v) \ + (BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) | BIT_WMAC_PKTCNT_CFGAD(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_FS_CLI0_RX_UMD0_INT BIT(3) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */ +#define BIT_SHIFT_CTRL_SEL 0 +#define BIT_MASK_CTRL_SEL 0xf +#define BIT_CTRL_SEL(x) (((x) & BIT_MASK_CTRL_SEL) << BIT_SHIFT_CTRL_SEL) +#define BITS_CTRL_SEL (BIT_MASK_CTRL_SEL << BIT_SHIFT_CTRL_SEL) +#define BIT_CLEAR_CTRL_SEL(x) ((x) & (~BITS_CTRL_SEL)) +#define BIT_GET_CTRL_SEL(x) (((x) >> BIT_SHIFT_CTRL_SEL) & BIT_MASK_CTRL_SEL) +#define BIT_SET_CTRL_SEL(x, v) (BIT_CLEAR_CTRL_SEL(x) | BIT_CTRL_SEL(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_IQ_DUMP (Offset 0x07C0) */ -#define BIT_PORT1_RXUCMD1_OK_INT BIT(2) +#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL +#define BIT_R_WMAC_MATCH_REF_MAC(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC) +#define BITS_R_WMAC_MATCH_REF_MAC \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC << BIT_SHIFT_R_WMAC_MATCH_REF_MAC) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) ((x) & (~BITS_R_WMAC_MATCH_REF_MAC)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC) +#define BIT_SET_R_WMAC_MATCH_REF_MAC(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) | BIT_R_WMAC_MATCH_REF_MAC(v)) + +#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff +#define BIT_R_WMAC_RXFIFO_FULL_TH(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) +#define BITS_R_WMAC_RXFIFO_FULL_TH \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) | BIT_R_WMAC_RXFIFO_FULL_TH(v)) + +#define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51) +#define BIT_R_WMAC_NDP_RST BIT(50) +#define BIT_R_WMAC_POWINT_EN BIT(49) +#define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48) +#define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47) +#define BIT_R_WMAC_PFIN_TOEN BIT(46) +#define BIT_R_WMAC_FIL_SECERR BIT(45) +#define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44) +#define BIT_R_WMAC_FIL_FCTYPE BIT(43) +#define BIT_R_WMAC_FIL_FCPROVER BIT(42) +#define BIT_R_WMAC_PHYSTS_SNIF BIT(41) +#define BIT_R_WMAC_PHYSTS_PLCP BIT(40) +#define BIT_R_MAC_TCR_VBONF_RD BIT(39) +#define BIT_R_WMAC_TCR_MPAR_NDP BIT(38) +#define BIT_R_WMAC_NDP_FILTER BIT(37) +#define BIT_R_WMAC_RXLEN_SEL BIT(36) +#define BIT_R_WMAC_RXLEN_SEL1 BIT(35) +#define BIT_R_OFDM_FILTER BIT(34) +#define BIT_R_WMAC_CHK_OFDM_LEN BIT(33) + +#define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL +#define BIT_R_WMAC_MASK_LA_MAC(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC) +#define BITS_R_WMAC_MASK_LA_MAC \ + (BIT_MASK_R_WMAC_MASK_LA_MAC << BIT_SHIFT_R_WMAC_MASK_LA_MAC) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC)) +#define BIT_GET_R_WMAC_MASK_LA_MAC(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC) +#define BIT_SET_R_WMAC_MASK_LA_MAC(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) | BIT_R_WMAC_MASK_LA_MAC(v)) + +#define BIT_R_WMAC_CHK_CCK_LEN BIT(32) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL (Offset 0x07C0) */ + +#define BIT_LTECOEX_ACCESS_START BIT(31) +#define BIT_LTECOEX_WRITE_MODE BIT(30) +#define BIT_LTECOEX_READY_BIT BIT(29) + +#define BIT_SHIFT_WRITE_BYTE_EN 16 +#define BIT_MASK_WRITE_BYTE_EN 0xf +#define BIT_WRITE_BYTE_EN(x) \ + (((x) & BIT_MASK_WRITE_BYTE_EN) << BIT_SHIFT_WRITE_BYTE_EN) +#define BITS_WRITE_BYTE_EN (BIT_MASK_WRITE_BYTE_EN << BIT_SHIFT_WRITE_BYTE_EN) +#define BIT_CLEAR_WRITE_BYTE_EN(x) ((x) & (~BITS_WRITE_BYTE_EN)) +#define BIT_GET_WRITE_BYTE_EN(x) \ + (((x) >> BIT_SHIFT_WRITE_BYTE_EN) & BIT_MASK_WRITE_BYTE_EN) +#define BIT_SET_WRITE_BYTE_EN(x, v) \ + (BIT_CLEAR_WRITE_BYTE_EN(x) | BIT_WRITE_BYTE_EN(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_IQ_DUMP (Offset 0x07C0) */ +#define BIT_SHIFT_DUMP_OK_ADDR 16 +#define BIT_MASK_DUMP_OK_ADDR 0xffff +#define BIT_DUMP_OK_ADDR(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR) +#define BITS_DUMP_OK_ADDR (BIT_MASK_DUMP_OK_ADDR << BIT_SHIFT_DUMP_OK_ADDR) +#define BIT_CLEAR_DUMP_OK_ADDR(x) ((x) & (~BITS_DUMP_OK_ADDR)) +#define BIT_GET_DUMP_OK_ADDR(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR) +#define BIT_SET_DUMP_OK_ADDR(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR(x) | BIT_DUMP_OK_ADDR(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_IQ_DUMP (Offset 0x07C0) */ -#define BIT_FS_DMEM1_WPTR_UPDATE_INT BIT(2) +#define BIT_MACDBG_TRIG_IQDUMP BIT(15) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_IQ_DUMP (Offset 0x07C0) */ +#define BIT_SHIFT_R_TRIG_TIME_SEL 8 +#define BIT_MASK_R_TRIG_TIME_SEL 0x7f +#define BIT_R_TRIG_TIME_SEL(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL) +#define BITS_R_TRIG_TIME_SEL \ + (BIT_MASK_R_TRIG_TIME_SEL << BIT_SHIFT_R_TRIG_TIME_SEL) +#define BIT_CLEAR_R_TRIG_TIME_SEL(x) ((x) & (~BITS_R_TRIG_TIME_SEL)) +#define BIT_GET_R_TRIG_TIME_SEL(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL) +#define BIT_SET_R_TRIG_TIME_SEL(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL(x) | BIT_R_TRIG_TIME_SEL(v)) + +#define BIT_SHIFT_R_MAC_TRIG_SEL 6 +#define BIT_MASK_R_MAC_TRIG_SEL 0x3 +#define BIT_R_MAC_TRIG_SEL(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL) +#define BITS_R_MAC_TRIG_SEL \ + (BIT_MASK_R_MAC_TRIG_SEL << BIT_SHIFT_R_MAC_TRIG_SEL) +#define BIT_CLEAR_R_MAC_TRIG_SEL(x) ((x) & (~BITS_R_MAC_TRIG_SEL)) +#define BIT_GET_R_MAC_TRIG_SEL(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL) +#define BIT_SET_R_MAC_TRIG_SEL(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL(x) | BIT_R_MAC_TRIG_SEL(v)) + +#define BIT_MAC_TRIG_REG BIT(5) + +#define BIT_SHIFT_R_LEVEL_PULSE_SEL 3 +#define BIT_MASK_R_LEVEL_PULSE_SEL 0x3 +#define BIT_R_LEVEL_PULSE_SEL(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL) +#define BITS_R_LEVEL_PULSE_SEL \ + (BIT_MASK_R_LEVEL_PULSE_SEL << BIT_SHIFT_R_LEVEL_PULSE_SEL) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL(x) ((x) & (~BITS_R_LEVEL_PULSE_SEL)) +#define BIT_GET_R_LEVEL_PULSE_SEL(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL) +#define BIT_SET_R_LEVEL_PULSE_SEL(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL(x) | BIT_R_LEVEL_PULSE_SEL(v)) + +#define BIT_EN_LA_MAC BIT(2) +#define BIT_R_EN_IQDUMP BIT(1) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL (Offset 0x07C0) */ + +#define BIT_SHIFT_LTECOEX_REG_ADDR 0 +#define BIT_MASK_LTECOEX_REG_ADDR 0xffff +#define BIT_LTECOEX_REG_ADDR(x) \ + (((x) & BIT_MASK_LTECOEX_REG_ADDR) << BIT_SHIFT_LTECOEX_REG_ADDR) +#define BITS_LTECOEX_REG_ADDR \ + (BIT_MASK_LTECOEX_REG_ADDR << BIT_SHIFT_LTECOEX_REG_ADDR) +#define BIT_CLEAR_LTECOEX_REG_ADDR(x) ((x) & (~BITS_LTECOEX_REG_ADDR)) +#define BIT_GET_LTECOEX_REG_ADDR(x) \ + (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR) & BIT_MASK_LTECOEX_REG_ADDR) +#define BIT_SET_LTECOEX_REG_ADDR(x, v) \ + (BIT_CLEAR_LTECOEX_REG_ADDR(x) | BIT_LTECOEX_REG_ADDR(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_IQ_DUMP (Offset 0x07C0) */ -#define BIT_FS_CLI0_RX_UMD1_INT BIT(2) +#define BIT_R_IQDATA_DUMP BIT(0) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA (Offset 0x07C4) */ +#define BIT_SHIFT_LTECOEX_W_DATA 0 +#define BIT_MASK_LTECOEX_W_DATA 0xffffffffL +#define BIT_LTECOEX_W_DATA(x) \ + (((x) & BIT_MASK_LTECOEX_W_DATA) << BIT_SHIFT_LTECOEX_W_DATA) +#define BITS_LTECOEX_W_DATA \ + (BIT_MASK_LTECOEX_W_DATA << BIT_SHIFT_LTECOEX_W_DATA) +#define BIT_CLEAR_LTECOEX_W_DATA(x) ((x) & (~BITS_LTECOEX_W_DATA)) +#define BIT_GET_LTECOEX_W_DATA(x) \ + (((x) >> BIT_SHIFT_LTECOEX_W_DATA) & BIT_MASK_LTECOEX_W_DATA) +#define BIT_SET_LTECOEX_W_DATA(x, v) \ + (BIT_CLEAR_LTECOEX_W_DATA(x) | BIT_LTECOEX_W_DATA(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT1_RXBCMD0_OK_INT BIT(1) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_IQ_DUMP_1 (Offset 0x07C4) */ +#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1 0 +#define BIT_MASK_R_WMAC_MASK_LA_MAC_1 0xffffffffL +#define BIT_R_WMAC_MASK_LA_MAC_1(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) +#define BITS_R_WMAC_MASK_LA_MAC_1 \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_1 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_1) +#define BIT_SET_R_WMAC_MASK_LA_MAC_1(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) | BIT_R_WMAC_MASK_LA_MAC_1(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA (Offset 0x07C8) */ -#define BIT_FS_CLI0_RX_BMD0_INT BIT(1) +#define BIT_SHIFT_LTECOEX_R_DATA 0 +#define BIT_MASK_LTECOEX_R_DATA 0xffffffffL +#define BIT_LTECOEX_R_DATA(x) \ + (((x) & BIT_MASK_LTECOEX_R_DATA) << BIT_SHIFT_LTECOEX_R_DATA) +#define BITS_LTECOEX_R_DATA \ + (BIT_MASK_LTECOEX_R_DATA << BIT_SHIFT_LTECOEX_R_DATA) +#define BIT_CLEAR_LTECOEX_R_DATA(x) ((x) & (~BITS_LTECOEX_R_DATA)) +#define BIT_GET_LTECOEX_R_DATA(x) \ + (((x) >> BIT_SHIFT_LTECOEX_R_DATA) & BIT_MASK_LTECOEX_R_DATA) +#define BIT_SET_LTECOEX_R_DATA(x, v) \ + (BIT_CLEAR_LTECOEX_R_DATA(x) | BIT_LTECOEX_R_DATA(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_IQ_DUMP_2 (Offset 0x07C8) */ +#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2 0 +#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2 0xffffffffL +#define BIT_R_WMAC_MATCH_REF_MAC_2(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) +#define BITS_R_WMAC_MATCH_REF_MAC_2 \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_2 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_2) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_2(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x) | BIT_R_WMAC_MATCH_REF_MAC_2(v)) -/* 2 REG_FE4ISR (Offset 0x1134) */ +#endif -#define BIT_PORT1_RXBCMD1_OK_INT BIT(0) +#if (HALMAC_8192F_SUPPORT) -#endif +/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ +#define BIT_SHIFT_RX_STOPRXDMA_RXPOINT 16 +#define BIT_MASK_RX_STOPRXDMA_RXPOINT 0xffff +#define BIT_RX_STOPRXDMA_RXPOINT(x) \ + (((x) & BIT_MASK_RX_STOPRXDMA_RXPOINT) \ + << BIT_SHIFT_RX_STOPRXDMA_RXPOINT) +#define BITS_RX_STOPRXDMA_RXPOINT \ + (BIT_MASK_RX_STOPRXDMA_RXPOINT << BIT_SHIFT_RX_STOPRXDMA_RXPOINT) +#define BIT_CLEAR_RX_STOPRXDMA_RXPOINT(x) ((x) & (~BITS_RX_STOPRXDMA_RXPOINT)) +#define BIT_GET_RX_STOPRXDMA_RXPOINT(x) \ + (((x) >> BIT_SHIFT_RX_STOPRXDMA_RXPOINT) & \ + BIT_MASK_RX_STOPRXDMA_RXPOINT) +#define BIT_SET_RX_STOPRXDMA_RXPOINT(x, v) \ + (BIT_CLEAR_RX_STOPRXDMA_RXPOINT(x) | BIT_RX_STOPRXDMA_RXPOINT(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FE4ISR (Offset 0x1134) */ +/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ -#define BIT_FS_CLI0_RX_BMD1_INT BIT(0) +#define BIT_RXFTM_TXACK_SC BIT(6) +#define BIT_RXFTM_TXACK_BW BIT(5) #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ +#define BIT_RXFTM_STOPRXDMAEN BIT(4) -/* 2 REG_FT1IMR (Offset 0x1138) */ +#endif -#define BIT__FT2ISR__IND_MSK BIT(30) -#define BIT_FTM_PTT_INT_EN BIT(29) -#define BIT_RXFTMREQ_INT_EN BIT(28) -#define BIT_RXFTM_INT_EN BIT(27) -#define BIT_TXFTM_INT_EN BIT(26) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ +#define BIT_RXFTM_EN BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_FT1IMR (Offset 0x1138) */ +/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ -#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25) -#define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24) +#define BIT_RXFTMREQ_STOPRXDMAEN BIT(2) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ -/* 2 REG_FT1IMR (Offset 0x1138) */ +#define BIT_RXFTMREQ_BYDRV BIT(2) -#define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23) -#define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22) -#define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21) -#define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20) -#define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19) -#define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18) -#define BIT_FS_CTWEND2_INT_EN BIT(17) -#define BIT_FS_CTWEND1_INT_EN BIT(16) -#define BIT_FS_CTWEND0_INT_EN BIT(15) -#define BIT_FS_TX_NULL1_INT_EN BIT(14) -#define BIT_FS_TX_NULL0_INT_EN BIT(13) -#define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12) -#define BIT_FS_P2P_RFON2_INT_EN BIT(11) -#define BIT_FS_P2P_RFOFF2_INT_EN BIT(10) -#define BIT_FS_P2P_RFON1_INT_EN BIT(9) -#define BIT_FS_P2P_RFOFF1_INT_EN BIT(8) -#define BIT_FS_P2P_RFON0_INT_EN BIT(7) -#define BIT_FS_P2P_RFOFF0_INT_EN BIT(6) -#define BIT_FS_RX_UAPSDMD1_EN BIT(5) -#define BIT_FS_RX_UAPSDMD0_EN BIT(4) -#define BIT_FS_TRIGGER_PKT_EN BIT(3) -#define BIT_FS_EOSP_INT_EN BIT(2) -#define BIT_FS_RPWM2_INT_EN BIT(1) -#define BIT_FS_RPWM_INT_EN BIT(0) - -#endif - - -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT1ISR (Offset 0x113C) */ +/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ -#define BIT__FT2ISR__IND_INT BIT(30) -#define BIT_FTM_PTT_INT BIT(29) -#define BIT_RXFTMREQ_INT BIT(28) -#define BIT_RXFTM_INT BIT(27) -#define BIT_TXFTM_INT BIT(26) +#define BIT_RXFTMREQ_EN BIT(1) +#define BIT_FTM_EN BIT(0) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_IQ_DUMP_EXT (Offset 0x07CF) */ +#define BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL 10 +#define BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL 0x3 +#define BIT_R_LA_MAC_TIMEOUT_UNIT_SEL(x) \ + (((x) & BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL) \ + << BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL) +#define BITS_R_LA_MAC_TIMEOUT_UNIT_SEL \ + (BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL \ + << BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL) +#define BIT_CLEAR_R_LA_MAC_TIMEOUT_UNIT_SEL(x) \ + ((x) & (~BITS_R_LA_MAC_TIMEOUT_UNIT_SEL)) +#define BIT_GET_R_LA_MAC_TIMEOUT_UNIT_SEL(x) \ + (((x) >> BIT_SHIFT_R_LA_MAC_TIMEOUT_UNIT_SEL) & \ + BIT_MASK_R_LA_MAC_TIMEOUT_UNIT_SEL) +#define BIT_SET_R_LA_MAC_TIMEOUT_UNIT_SEL(x, v) \ + (BIT_CLEAR_R_LA_MAC_TIMEOUT_UNIT_SEL(x) | \ + BIT_R_LA_MAC_TIMEOUT_UNIT_SEL(v)) + +#define BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE 4 +#define BIT_MASK_R_LA_MAC_TIMEOUT_VALUE 0x3f +#define BIT_R_LA_MAC_TIMEOUT_VALUE(x) \ + (((x) & BIT_MASK_R_LA_MAC_TIMEOUT_VALUE) \ + << BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE) +#define BITS_R_LA_MAC_TIMEOUT_VALUE \ + (BIT_MASK_R_LA_MAC_TIMEOUT_VALUE << BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE) +#define BIT_CLEAR_R_LA_MAC_TIMEOUT_VALUE(x) \ + ((x) & (~BITS_R_LA_MAC_TIMEOUT_VALUE)) +#define BIT_GET_R_LA_MAC_TIMEOUT_VALUE(x) \ + (((x) >> BIT_SHIFT_R_LA_MAC_TIMEOUT_VALUE) & \ + BIT_MASK_R_LA_MAC_TIMEOUT_VALUE) +#define BIT_SET_R_LA_MAC_TIMEOUT_VALUE(x, v) \ + (BIT_CLEAR_R_LA_MAC_TIMEOUT_VALUE(x) | BIT_R_LA_MAC_TIMEOUT_VALUE(v)) + +#define BIT_R_LEVEL_PULSE_SEL_EXTL BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_FT1ISR (Offset 0x113C) */ +/* 2 REG_IQ_DUMP_EXT (Offset 0x07CF) */ -#define BIT_FS_H2C_CMD_OK_INT BIT(25) -#define BIT_FS_H2C_CMD_FULL_INT BIT(24) +#define BIT_SHIFT_R_TIME_UNIT_SEL 0 +#define BIT_MASK_R_TIME_UNIT_SEL 0x7 +#define BIT_R_TIME_UNIT_SEL(x) \ + (((x) & BIT_MASK_R_TIME_UNIT_SEL) << BIT_SHIFT_R_TIME_UNIT_SEL) +#define BITS_R_TIME_UNIT_SEL \ + (BIT_MASK_R_TIME_UNIT_SEL << BIT_SHIFT_R_TIME_UNIT_SEL) +#define BIT_CLEAR_R_TIME_UNIT_SEL(x) ((x) & (~BITS_R_TIME_UNIT_SEL)) +#define BIT_GET_R_TIME_UNIT_SEL(x) \ + (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL) & BIT_MASK_R_TIME_UNIT_SEL) +#define BIT_SET_R_TIME_UNIT_SEL(x, v) \ + (BIT_CLEAR_R_TIME_UNIT_SEL(x) | BIT_R_TIME_UNIT_SEL(v)) #endif +#if (HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_OFDM_CCK_LEN_MASK (Offset 0x07D0) */ +#define BIT_MICICV_CLR BIT(86) +#define BIT_MPDU_RDY_SET BIT(85) +#define BIT_CLR_SEC_TYPE BIT(84) +#define BIT_NEWPKT_IN BIT(83) +#define BIT_FCS_END BIT(82) +#define BIT_DEL_MESH_TYPE BIT(81) +#define BIT_MASK_MESH_TYPE BIT(80) -/* 2 REG_FT1ISR (Offset 0x113C) */ +#endif -#define BIT_FS_MACID_PWRCHANGE5_INT BIT(23) -#define BIT_FS_MACID_PWRCHANGE4_INT BIT(22) -#define BIT_FS_MACID_PWRCHANGE3_INT BIT(21) -#define BIT_FS_MACID_PWRCHANGE2_INT BIT(20) -#define BIT_FS_MACID_PWRCHANGE1_INT BIT(19) -#define BIT_FS_MACID_PWRCHANGE0_INT BIT(18) -#define BIT_FS_CTWEND2_INT BIT(17) -#define BIT_FS_CTWEND1_INT BIT(16) -#define BIT_FS_CTWEND0_INT BIT(15) -#define BIT_FS_TX_NULL1_INT BIT(14) -#define BIT_FS_TX_NULL0_INT BIT(13) -#define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12) -#define BIT_FS_P2P_RFON2_INT BIT(11) -#define BIT_FS_P2P_RFOFF2_INT BIT(10) -#define BIT_FS_P2P_RFON1_INT BIT(9) -#define BIT_FS_P2P_RFOFF1_INT BIT(8) -#define BIT_FS_P2P_RFON0_INT BIT(7) -#define BIT_FS_P2P_RFOFF0_INT BIT(6) -#define BIT_FS_RX_UAPSDMD1_INT BIT(5) -#define BIT_FS_RX_UAPSDMD0_INT BIT(4) -#define BIT_FS_TRIGGER_PKT_INT BIT(3) -#define BIT_FS_EOSP_INT BIT(2) -#define BIT_FS_RPWM2_INT BIT(1) -#define BIT_FS_RPWM_INT BIT(0) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_SPWR0 (Offset 0x1140) */ +/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ +#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1 24 +#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 0xff +#define BIT_R_WMAC_RXFIFO_FULL_TH_1(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) +#define BITS_R_WMAC_RXFIFO_FULL_TH_1 \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x) | BIT_R_WMAC_RXFIFO_FULL_TH_1(v)) -#define BIT_SHIFT_MID_31TO0 0 -#define BIT_MASK_MID_31TO0 0xffffffffL -#define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0) -#define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0) +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1 BIT(23) +#define BIT_R_WMAC_RXRST_DLY_1 BIT(22) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1 BIT(21) +#define BIT_R_WMAC_SRCH_TXRPT_UA1_1 BIT(20) +#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1 BIT(19) +#define BIT_R_WMAC_NDP_RST_1 BIT(18) +#define BIT_R_WMAC_POWINT_EN_1 BIT(17) +#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1 BIT(16) +#define BIT_R_WMAC_SRCH_TXRPT_MID_1 BIT(15) +#define BIT_R_WMAC_PFIN_TOEN_1 BIT(14) +#endif -/* 2 REG_SPWR1 (Offset 0x1144) */ +#if (HALMAC_8192F_SUPPORT) +/* 2 REG_FA_FILTER1 (Offset 0x07D4) */ -#define BIT_SHIFT_MID_63TO32 0 -#define BIT_MASK_MID_63TO32 0xffffffffL -#define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32) -#define BIT_GET_MID_63TO32(x) (((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32) +#define BIT_R_WMAC_FIL_SECERR_V1 BIT(13) +#endif -/* 2 REG_SPWR2 (Offset 0x1148) */ +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ -#define BIT_SHIFT_MID_95O64 0 -#define BIT_MASK_MID_95O64 0xffffffffL -#define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64) -#define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64) +#define BIT_R_WMAC_FIL_SECERR_1 BIT(13) +#endif -/* 2 REG_SPWR3 (Offset 0x114C) */ +#if (HALMAC_8192F_SUPPORT) +/* 2 REG_FA_FILTER1 (Offset 0x07D4) */ -#define BIT_SHIFT_MID_127TO96 0 -#define BIT_MASK_MID_127TO96 0xffffffffL -#define BIT_MID_127TO96(x) (((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96) -#define BIT_GET_MID_127TO96(x) (((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96) +#define BIT_R_WMAC_FIL_CTLPKTLEN_V1 BIT(12) +#endif -/* 2 REG_POWSEQ (Offset 0x1150) */ +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ -#define BIT_SHIFT_SEQNUM_MID 16 -#define BIT_MASK_SEQNUM_MID 0xffff -#define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID) -#define BIT_GET_SEQNUM_MID(x) (((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID) +#define BIT_R_WMAC_FIL_CTLPKTLEN_1 BIT(12) +#endif -#define BIT_SHIFT_REF_MID 0 -#define BIT_MASK_REF_MID 0x7f -#define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID) -#define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID) +#if (HALMAC_8192F_SUPPORT) +/* 2 REG_FA_FILTER1 (Offset 0x07D4) */ -/* 2 REG_TC7_CTRL_V1 (Offset 0x1158) */ +#define BIT_R_WMAC_FIL_FCTYPE_V1 BIT(11) -#define BIT_TC7INT_EN BIT(26) -#define BIT_TC7MODE BIT(25) -#define BIT_TC7EN BIT(24) +#endif -#define BIT_SHIFT_TC7DATA 0 -#define BIT_MASK_TC7DATA 0xffffff -#define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA) -#define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ -/* 2 REG_TC8_CTRL_V1 (Offset 0x115C) */ +#define BIT_R_WMAC_FIL_FCTYPE_1 BIT(11) -#define BIT_TC8INT_EN BIT(26) -#define BIT_TC8MODE BIT(25) -#define BIT_TC8EN BIT(24) +#endif + +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_TC8DATA 0 -#define BIT_MASK_TC8DATA 0xffffff -#define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA) -#define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA) +/* 2 REG_FA_FILTER1 (Offset 0x07D4) */ +#define BIT_R_WMAC_FIL_FCPROVER_V1 BIT(10) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ +#define BIT_R_WMAC_FIL_FCPROVER_1 BIT(10) +#define BIT_R_WMAC_PHYSTS_SNIF_1 BIT(9) +#define BIT_R_WMAC_PHYSTS_PLCP_1 BIT(8) +#define BIT_R_MAC_TCR_VBONF_RD_1 BIT(7) +#define BIT_R_WMAC_TCR_MPAR_NDP_1 BIT(6) +#define BIT_R_WMAC_NDP_FILTER_1 BIT(5) +#define BIT_R_WMAC_RXLEN_SEL_1 BIT(4) +#define BIT_R_WMAC_RXLEN_SEL1_1 BIT(3) +#define BIT_R_OFDM_FILTER_1 BIT(2) -/* 2 REG_EXT_QUEUE_REG (Offset 0x11C0) */ +#endif +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_PCIE_PRIORITY_SEL 0 -#define BIT_MASK_PCIE_PRIORITY_SEL 0x3 -#define BIT_PCIE_PRIORITY_SEL(x) (((x) & BIT_MASK_PCIE_PRIORITY_SEL) << BIT_SHIFT_PCIE_PRIORITY_SEL) -#define BIT_GET_PCIE_PRIORITY_SEL(x) (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL) & BIT_MASK_PCIE_PRIORITY_SEL) +/* 2 REG_FA_FILTER1 (Offset 0x07D4) */ +#define BIT_R_WMAC_CHK_OFDM_LEN_V1 BIT(1) -/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_COUNTER_BASE 16 -#define BIT_MASK_COUNTER_BASE 0x1fff -#define BIT_COUNTER_BASE(x) (((x) & BIT_MASK_COUNTER_BASE) << BIT_SHIFT_COUNTER_BASE) -#define BIT_GET_COUNTER_BASE(x) (((x) >> BIT_SHIFT_COUNTER_BASE) & BIT_MASK_COUNTER_BASE) +/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ -#define BIT_EN_RTS_REQ BIT(9) -#define BIT_EN_EDCA_REQ BIT(8) -#define BIT_EN_PTCL_REQ BIT(7) -#define BIT_EN_SCH_REQ BIT(6) -#define BIT_EN_USB_CNT BIT(5) -#define BIT_EN_PCIE_CNT BIT(4) -#define BIT_RQPN_CNT BIT(3) -#define BIT_RDE_CNT BIT(2) -#define BIT_TDE_CNT BIT(1) -#define BIT_DIS_CNT BIT(0) +#define BIT_R_WMAC_CHK_OFDM_LEN_1 BIT(1) -/* 2 REG_COUNTER_TH (Offset 0x11C8) */ +#endif -#define BIT_CNT_ALL_MACID BIT(31) +#if (HALMAC_8192F_SUPPORT) -#define BIT_SHIFT_CNT_MACID 24 -#define BIT_MASK_CNT_MACID 0x7f -#define BIT_CNT_MACID(x) (((x) & BIT_MASK_CNT_MACID) << BIT_SHIFT_CNT_MACID) -#define BIT_GET_CNT_MACID(x) (((x) >> BIT_SHIFT_CNT_MACID) & BIT_MASK_CNT_MACID) +/* 2 REG_FA_FILTER1 (Offset 0x07D4) */ +#define BIT_R_WMAC_CHK_CCK_LEN_V1 BIT(0) -#define BIT_SHIFT_AGG_VALUE2 16 -#define BIT_MASK_AGG_VALUE2 0x7f -#define BIT_AGG_VALUE2(x) (((x) & BIT_MASK_AGG_VALUE2) << BIT_SHIFT_AGG_VALUE2) -#define BIT_GET_AGG_VALUE2(x) (((x) >> BIT_SHIFT_AGG_VALUE2) & BIT_MASK_AGG_VALUE2) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AGG_VALUE1 8 -#define BIT_MASK_AGG_VALUE1 0x7f -#define BIT_AGG_VALUE1(x) (((x) & BIT_MASK_AGG_VALUE1) << BIT_SHIFT_AGG_VALUE1) -#define BIT_GET_AGG_VALUE1(x) (((x) >> BIT_SHIFT_AGG_VALUE1) & BIT_MASK_AGG_VALUE1) +/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */ +#define BIT_R_WMAC_CHK_CCK_LEN_1 BIT(0) -#define BIT_SHIFT_AGG_VALUE0 0 -#define BIT_MASK_AGG_VALUE0 0x7f -#define BIT_AGG_VALUE0(x) (((x) & BIT_MASK_AGG_VALUE0) << BIT_SHIFT_AGG_VALUE0) -#define BIT_GET_AGG_VALUE0(x) (((x) >> BIT_SHIFT_AGG_VALUE0) & BIT_MASK_AGG_VALUE0) +#endif +#if (HALMAC_8192F_SUPPORT) -/* 2 REG_COUNTER_SET (Offset 0x11CC) */ +/* 2 REG_FA_FILTER2 (Offset 0x07D8) */ -#define BIT_RTS_RST BIT(24) -#define BIT_PTCL_RST BIT(23) -#define BIT_SCH_RST BIT(22) -#define BIT_EDCA_RST BIT(21) -#define BIT_RQPN_RST BIT(20) -#define BIT_USB_RST BIT(19) -#define BIT_PCIE_RST BIT(18) -#define BIT_RXDMA_RST BIT(17) -#define BIT_TXDMA_RST BIT(16) -#define BIT_EN_RTS_START BIT(8) -#define BIT_EN_PTCL_START BIT(7) -#define BIT_EN_SCH_START BIT(6) -#define BIT_EN_EDCA_START BIT(5) -#define BIT_EN_RQPN_START BIT(4) -#define BIT_EN_USB_START BIT(3) -#define BIT_EN_PCIE_START BIT(2) -#define BIT_EN_RXDMA_START BIT(1) -#define BIT_EN_TXDMA_START BIT(0) +#define BIT_DEL_MESH_TYPE_V1 BIT(17) -/* 2 REG_COUNTER_OVERFLOW (Offset 0x11D0) */ +#endif -#define BIT_RTS_OVF BIT(8) -#define BIT_PTCL_OVF BIT(7) -#define BIT_SCH_OVF BIT(6) -#define BIT_EDCA_OVF BIT(5) -#define BIT_RQPN_OVF BIT(4) -#define BIT_USB_OVF BIT(3) -#define BIT_PCIE_OVF BIT(2) -#define BIT_RXDMA_OVF BIT(1) -#define BIT_TXDMA_OVF BIT(0) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_TDE_LEN_TH (Offset 0x11D4) */ +/* 2 REG_WMAC_OPTION_FUNCTION_2 (Offset 0x07D8) */ +#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2 0 +#define BIT_MASK_R_WMAC_RX_FIL_LEN_2 0xffff +#define BIT_R_WMAC_RX_FIL_LEN_2(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) +#define BITS_R_WMAC_RX_FIL_LEN_2 \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_2 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) +#define BIT_SET_R_WMAC_RX_FIL_LEN_2(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) | BIT_R_WMAC_RX_FIL_LEN_2(v)) -#define BIT_SHIFT_TXDMA_LEN_TH0 16 -#define BIT_MASK_TXDMA_LEN_TH0 0xffff -#define BIT_TXDMA_LEN_TH0(x) (((x) & BIT_MASK_TXDMA_LEN_TH0) << BIT_SHIFT_TXDMA_LEN_TH0) -#define BIT_GET_TXDMA_LEN_TH0(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH0) & BIT_MASK_TXDMA_LEN_TH0) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_TXDMA_LEN_TH1 0 -#define BIT_MASK_TXDMA_LEN_TH1 0xffff -#define BIT_TXDMA_LEN_TH1(x) (((x) & BIT_MASK_TXDMA_LEN_TH1) << BIT_SHIFT_TXDMA_LEN_TH1) -#define BIT_GET_TXDMA_LEN_TH1(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH1) & BIT_MASK_TXDMA_LEN_TH1) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_R_WMAC_RXHANG_EN BIT(15) -/* 2 REG_RDE_LEN_TH (Offset 0x11D8) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_RXDMA_LEN_TH0 16 -#define BIT_MASK_RXDMA_LEN_TH0 0xffff -#define BIT_RXDMA_LEN_TH0(x) (((x) & BIT_MASK_RXDMA_LEN_TH0) << BIT_SHIFT_RXDMA_LEN_TH0) -#define BIT_GET_RXDMA_LEN_TH0(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH0) & BIT_MASK_RXDMA_LEN_TH0) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_RXHANG_EN BIT(15) -#define BIT_SHIFT_RXDMA_LEN_TH1 0 -#define BIT_MASK_RXDMA_LEN_TH1 0xffff -#define BIT_RXDMA_LEN_TH1(x) (((x) & BIT_MASK_RXDMA_LEN_TH1) << BIT_SHIFT_RXDMA_LEN_TH1) -#define BIT_GET_RXDMA_LEN_TH1(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH1) & BIT_MASK_RXDMA_LEN_TH1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_PCIE_EXEC_TIME (Offset 0x11DC) */ +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_R_WMAC_MHRDDY_LATCH BIT(14) -#define BIT_SHIFT_COUNTER_INTERVAL_SEL 16 -#define BIT_MASK_COUNTER_INTERVAL_SEL 0x3 -#define BIT_COUNTER_INTERVAL_SEL(x) (((x) & BIT_MASK_COUNTER_INTERVAL_SEL) << BIT_SHIFT_COUNTER_INTERVAL_SEL) -#define BIT_GET_COUNTER_INTERVAL_SEL(x) (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL) & BIT_MASK_COUNTER_INTERVAL_SEL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_PCIE_TRANS_DATA_TH1 0 -#define BIT_MASK_PCIE_TRANS_DATA_TH1 0xffff -#define BIT_PCIE_TRANS_DATA_TH1(x) (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1) << BIT_SHIFT_PCIE_TRANS_DATA_TH1) -#define BIT_GET_PCIE_TRANS_DATA_TH1(x) (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1) & BIT_MASK_PCIE_TRANS_DATA_TH1) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_R_MHRDDY_CLR BIT(13) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - - -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ -#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN BIT(31) +#define BIT_R_WMAC_MHRDDY_CLR BIT(13) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ -#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN BIT(30) +#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ +#define BIT_R_CHK_DELIMIT_LEN BIT(10) +#define BIT_R_REAPTER_ADDR_MATCH BIT(9) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8) +#define BIT_R_LATCH_MACHRDY BIT(7) +#define BIT_R_WMAC_RXFIL_REND BIT(6) +#define BIT_R_WMAC_MPDURDY_CLR BIT(5) +#define BIT_R_WMAC_CLRRXSEC BIT(4) +#define BIT_R_WMAC_RXFIL_RDEL BIT(3) +#define BIT_R_WMAC_RXFIL_FCSE BIT(2) +#define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1) +#define BIT_R_WMAC_RXFIL_MASKM BIT(0) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_NDP_SIG (Offset 0x07E0) */ +#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0 +#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff +#define BIT_R_WMAC_TXNDP_SIGB(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB) +#define BITS_R_WMAC_TXNDP_SIGB \ + (BIT_MASK_R_WMAC_TXNDP_SIGB << BIT_SHIFT_R_WMAC_TXNDP_SIGB) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) ((x) & (~BITS_R_WMAC_TXNDP_SIGB)) +#define BIT_GET_R_WMAC_TXNDP_SIGB(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB) +#define BIT_SET_R_WMAC_TXNDP_SIGB(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) | BIT_R_WMAC_TXNDP_SIGB(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ -#define BIT_PORT4_TRIPKT_OK_INT_EN BIT(29) +#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH) +#define BIT_MASK_R_MAC_DEBUG 0xffffffffL +#define BIT_R_MAC_DEBUG(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG) +#define BITS_R_MAC_DEBUG (BIT_MASK_R_MAC_DEBUG << BIT_SHIFT_R_MAC_DEBUG) +#define BIT_CLEAR_R_MAC_DEBUG(x) ((x) & (~BITS_R_MAC_DEBUG)) +#define BIT_GET_R_MAC_DEBUG(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG) +#define BIT_SET_R_MAC_DEBUG(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG(x) | BIT_R_MAC_DEBUG(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ +#define BIT_SHIFT_R_MAC_DBG_SHIFT 8 +#define BIT_MASK_R_MAC_DBG_SHIFT 0x7 +#define BIT_R_MAC_DBG_SHIFT(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT) +#define BITS_R_MAC_DBG_SHIFT \ + (BIT_MASK_R_MAC_DBG_SHIFT << BIT_SHIFT_R_MAC_DBG_SHIFT) +#define BIT_CLEAR_R_MAC_DBG_SHIFT(x) ((x) & (~BITS_R_MAC_DBG_SHIFT)) +#define BIT_GET_R_MAC_DBG_SHIFT(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT) +#define BIT_SET_R_MAC_DBG_SHIFT(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT(x) | BIT_R_MAC_DBG_SHIFT(v)) + +#define BIT_SHIFT_R_MAC_DBG_SEL 0 +#define BIT_MASK_R_MAC_DBG_SEL 0x3 +#define BIT_R_MAC_DBG_SEL(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL) +#define BITS_R_MAC_DBG_SEL (BIT_MASK_R_MAC_DBG_SEL << BIT_SHIFT_R_MAC_DBG_SEL) +#define BIT_CLEAR_R_MAC_DBG_SEL(x) ((x) & (~BITS_R_MAC_DBG_SEL)) +#define BIT_GET_R_MAC_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL) +#define BIT_SET_R_MAC_DBG_SEL(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL(x) | BIT_R_MAC_DBG_SEL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1 (Offset 0x07E8) */ -#define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29) +#define BIT_SHIFT_R_MAC_DEBUG_1 0 +#define BIT_MASK_R_MAC_DEBUG_1 0xffffffffL +#define BIT_R_MAC_DEBUG_1(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_1) << BIT_SHIFT_R_MAC_DEBUG_1) +#define BITS_R_MAC_DEBUG_1 (BIT_MASK_R_MAC_DEBUG_1 << BIT_SHIFT_R_MAC_DEBUG_1) +#define BIT_CLEAR_R_MAC_DEBUG_1(x) ((x) & (~BITS_R_MAC_DEBUG_1)) +#define BIT_GET_R_MAC_DEBUG_1(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_1) & BIT_MASK_R_MAC_DEBUG_1) +#define BIT_SET_R_MAC_DEBUG_1(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_1(x) | BIT_R_MAC_DEBUG_1(v)) #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_WSEC_OPTION (Offset 0x07EC) */ +#define BIT_RXDEC_BM_MGNT BIT(22) +#define BIT_TXENC_BM_MGNT BIT(21) +#define BIT_RXDEC_UNI_MGNT BIT(20) +#define BIT_TXENC_UNI_MGNT BIT(19) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT4_RX_EOSP_OK_INT_EN BIT(28) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SEC_OPT_V2 (Offset 0x07EC) */ +#define BIT_MASK_IV BIT(18) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_WSEC_OPTION (Offset 0x07EC) */ -#define BIT_FS_CLI3_EOSP_INT_EN BIT(28) +#define BIT_WMAC_SEC_MASKIV BIT(18) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SEC_OPT_V2 (Offset 0x07EC) */ +#define BIT_EIVL_ENDIAN BIT(17) +#define BIT_EIVH_ENDIAN BIT(16) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN BIT(27) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_WSEC_OPTION (Offset 0x07EC) */ +#define BIT_SHIFT_WMAC_SEC_PN_SEL 16 +#define BIT_MASK_WMAC_SEC_PN_SEL 0x3 +#define BIT_WMAC_SEC_PN_SEL(x) \ + (((x) & BIT_MASK_WMAC_SEC_PN_SEL) << BIT_SHIFT_WMAC_SEC_PN_SEL) +#define BITS_WMAC_SEC_PN_SEL \ + (BIT_MASK_WMAC_SEC_PN_SEL << BIT_SHIFT_WMAC_SEC_PN_SEL) +#define BIT_CLEAR_WMAC_SEC_PN_SEL(x) ((x) & (~BITS_WMAC_SEC_PN_SEL)) +#define BIT_GET_WMAC_SEC_PN_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL) & BIT_MASK_WMAC_SEC_PN_SEL) +#define BIT_SET_WMAC_SEC_PN_SEL(x, v) \ + (BIT_CLEAR_WMAC_SEC_PN_SEL(x) | BIT_WMAC_SEC_PN_SEL(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_WSEC_OPTION (Offset 0x07EC) */ -#define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27) +#define BIT_SHIFT_BT_TIME_CNT 0 +#define BIT_MASK_BT_TIME_CNT 0xff +#define BIT_BT_TIME_CNT(x) \ + (((x) & BIT_MASK_BT_TIME_CNT) << BIT_SHIFT_BT_TIME_CNT) +#define BITS_BT_TIME_CNT (BIT_MASK_BT_TIME_CNT << BIT_SHIFT_BT_TIME_CNT) +#define BIT_CLEAR_BT_TIME_CNT(x) ((x) & (~BITS_BT_TIME_CNT)) +#define BIT_GET_BT_TIME_CNT(x) \ + (((x) >> BIT_SHIFT_BT_TIME_CNT) & BIT_MASK_BT_TIME_CNT) +#define BIT_SET_BT_TIME_CNT(x, v) \ + (BIT_CLEAR_BT_TIME_CNT(x) | BIT_BT_TIME_CNT(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_RTS_ADDRESS_0 (Offset 0x07F0) */ +#define BIT_SHIFT_R_WMAC_RTS_ADDR0 0 +#define BIT_MASK_R_WMAC_RTS_ADDR0 0xffffffffffffL +#define BIT_R_WMAC_RTS_ADDR0(x) \ + (((x) & BIT_MASK_R_WMAC_RTS_ADDR0) << BIT_SHIFT_R_WMAC_RTS_ADDR0) +#define BITS_R_WMAC_RTS_ADDR0 \ + (BIT_MASK_R_WMAC_RTS_ADDR0 << BIT_SHIFT_R_WMAC_RTS_ADDR0) +#define BIT_CLEAR_R_WMAC_RTS_ADDR0(x) ((x) & (~BITS_R_WMAC_RTS_ADDR0)) +#define BIT_GET_R_WMAC_RTS_ADDR0(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTS_ADDR0) & BIT_MASK_R_WMAC_RTS_ADDR0) +#define BIT_SET_R_WMAC_RTS_ADDR0(x, v) \ + (BIT_CLEAR_R_WMAC_RTS_ADDR0(x) | BIT_R_WMAC_RTS_ADDR0(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN BIT(26) +#if (HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_RTS_ADDR0 (Offset 0x07F0) */ +#define BIT_SHIFT_RTS_ADDR0 0 +#define BIT_MASK_RTS_ADDR0 0xffffffffffffL +#define BIT_RTS_ADDR0(x) (((x) & BIT_MASK_RTS_ADDR0) << BIT_SHIFT_RTS_ADDR0) +#define BITS_RTS_ADDR0 (BIT_MASK_RTS_ADDR0 << BIT_SHIFT_RTS_ADDR0) +#define BIT_CLEAR_RTS_ADDR0(x) ((x) & (~BITS_RTS_ADDR0)) +#define BIT_GET_RTS_ADDR0(x) (((x) >> BIT_SHIFT_RTS_ADDR0) & BIT_MASK_RTS_ADDR0) +#define BIT_SET_RTS_ADDR0(x, v) (BIT_CLEAR_RTS_ADDR0(x) | BIT_RTS_ADDR0(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_RTS_ADDRESS_1 (Offset 0x07F8) */ -#define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26) +#define BIT_SHIFT_R_WMAC_RTS_ADDR1 0 +#define BIT_MASK_R_WMAC_RTS_ADDR1 0xffffffffffffL +#define BIT_R_WMAC_RTS_ADDR1(x) \ + (((x) & BIT_MASK_R_WMAC_RTS_ADDR1) << BIT_SHIFT_R_WMAC_RTS_ADDR1) +#define BITS_R_WMAC_RTS_ADDR1 \ + (BIT_MASK_R_WMAC_RTS_ADDR1 << BIT_SHIFT_R_WMAC_RTS_ADDR1) +#define BIT_CLEAR_R_WMAC_RTS_ADDR1(x) ((x) & (~BITS_R_WMAC_RTS_ADDR1)) +#define BIT_GET_R_WMAC_RTS_ADDR1(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTS_ADDR1) & BIT_MASK_R_WMAC_RTS_ADDR1) +#define BIT_SET_R_WMAC_RTS_ADDR1(x, v) \ + (BIT_CLEAR_R_WMAC_RTS_ADDR1(x) | BIT_R_WMAC_RTS_ADDR1(v)) #endif +#if (HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_RTS_ADDR1 (Offset 0x07F8) */ +#define BIT_SHIFT_RTS_ADDR1 0 +#define BIT_MASK_RTS_ADDR1 0xffffffffffffL +#define BIT_RTS_ADDR1(x) (((x) & BIT_MASK_RTS_ADDR1) << BIT_SHIFT_RTS_ADDR1) +#define BITS_RTS_ADDR1 (BIT_MASK_RTS_ADDR1 << BIT_SHIFT_RTS_ADDR1) +#define BIT_CLEAR_RTS_ADDR1(x) ((x) & (~BITS_RTS_ADDR1)) +#define BIT_GET_RTS_ADDR1(x) (((x) >> BIT_SHIFT_RTS_ADDR1) & BIT_MASK_RTS_ADDR1) +#define BIT_SET_RTS_ADDR1(x, v) (BIT_CLEAR_RTS_ADDR1(x) | BIT_RTS_ADDR1(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT3_TRIPKT_OK_INT_EN BIT(25) +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#endif +/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +#define BIT_FEN_BB_GLB_RSTN_V1 BIT(17) +#define BIT_FEN_BBRSTB_V1 BIT(16) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_SYS_CFG3 (Offset 0x1000) */ -#define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25) +#define BIT_PWC_MA33V BIT(15) #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +#define BIT_PWC_EV25V_1 BIT(14) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT3_RX_EOSP_OK_INT_EN BIT(24) +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_SYS_CFG3 (Offset 0x1000) */ +#define BIT_PWC_MA12V BIT(14) +#define BIT_PWC_MD12V BIT(13) +#define BIT_PWC_PD12V BIT(12) +#define BIT_PWC_UD12V BIT(11) +#define BIT_ISO_MA2MD BIT(1) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_FS_CLI2_EOSP_INT_EN BIT(24) +#define BIT_OCP_L BIT(31) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_OCP_L_0 BIT(31) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN BIT(23) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_POWOCP_L BIT(30) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23) +#define BIT_SHIFT_CF_L_V2 28 +#define BIT_MASK_CF_L_V2 0x3 +#define BIT_CF_L_V2(x) (((x) & BIT_MASK_CF_L_V2) << BIT_SHIFT_CF_L_V2) +#define BITS_CF_L_V2 (BIT_MASK_CF_L_V2 << BIT_SHIFT_CF_L_V2) +#define BIT_CLEAR_CF_L_V2(x) ((x) & (~BITS_CF_L_V2)) +#define BIT_GET_CF_L_V2(x) (((x) >> BIT_SHIFT_CF_L_V2) & BIT_MASK_CF_L_V2) +#define BIT_SET_CF_L_V2(x, v) (BIT_CLEAR_CF_L_V2(x) | BIT_CF_L_V2(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_CF_L_1_0 28 +#define BIT_MASK_CF_L_1_0 0x3 +#define BIT_CF_L_1_0(x) (((x) & BIT_MASK_CF_L_1_0) << BIT_SHIFT_CF_L_1_0) +#define BITS_CF_L_1_0 (BIT_MASK_CF_L_1_0 << BIT_SHIFT_CF_L_1_0) +#define BIT_CLEAR_CF_L_1_0(x) ((x) & (~BITS_CF_L_1_0)) +#define BIT_GET_CF_L_1_0(x) (((x) >> BIT_SHIFT_CF_L_1_0) & BIT_MASK_CF_L_1_0) +#define BIT_SET_CF_L_1_0(x, v) (BIT_CLEAR_CF_L_1_0(x) | BIT_CF_L_1_0(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN BIT(22) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_CFC_L_V2 26 +#define BIT_MASK_CFC_L_V2 0x3 +#define BIT_CFC_L_V2(x) (((x) & BIT_MASK_CFC_L_V2) << BIT_SHIFT_CFC_L_V2) +#define BITS_CFC_L_V2 (BIT_MASK_CFC_L_V2 << BIT_SHIFT_CFC_L_V2) +#define BIT_CLEAR_CFC_L_V2(x) ((x) & (~BITS_CFC_L_V2)) +#define BIT_GET_CFC_L_V2(x) (((x) >> BIT_SHIFT_CFC_L_V2) & BIT_MASK_CFC_L_V2) +#define BIT_SET_CFC_L_V2(x, v) (BIT_CLEAR_CFC_L_V2(x) | BIT_CFC_L_V2(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22) +#define BIT_SHIFT_CFC_L_1_0 26 +#define BIT_MASK_CFC_L_1_0 0x3 +#define BIT_CFC_L_1_0(x) (((x) & BIT_MASK_CFC_L_1_0) << BIT_SHIFT_CFC_L_1_0) +#define BITS_CFC_L_1_0 (BIT_MASK_CFC_L_1_0 << BIT_SHIFT_CFC_L_1_0) +#define BIT_CLEAR_CFC_L_1_0(x) ((x) & (~BITS_CFC_L_1_0)) +#define BIT_GET_CFC_L_1_0(x) (((x) >> BIT_SHIFT_CFC_L_1_0) & BIT_MASK_CFC_L_1_0) +#define BIT_SET_CFC_L_1_0(x, v) (BIT_CLEAR_CFC_L_1_0(x) | BIT_CFC_L_1_0(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_R3_L_V2 24 +#define BIT_MASK_R3_L_V2 0x3 +#define BIT_R3_L_V2(x) (((x) & BIT_MASK_R3_L_V2) << BIT_SHIFT_R3_L_V2) +#define BITS_R3_L_V2 (BIT_MASK_R3_L_V2 << BIT_SHIFT_R3_L_V2) +#define BIT_CLEAR_R3_L_V2(x) ((x) & (~BITS_R3_L_V2)) +#define BIT_GET_R3_L_V2(x) (((x) >> BIT_SHIFT_R3_L_V2) & BIT_MASK_R3_L_V2) +#define BIT_SET_R3_L_V2(x, v) (BIT_CLEAR_R3_L_V2(x) | BIT_R3_L_V2(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT2_TRIPKT_OK_INT_EN BIT(21) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_R3_L_1_0 24 +#define BIT_MASK_R3_L_1_0 0x3 +#define BIT_R3_L_1_0(x) (((x) & BIT_MASK_R3_L_1_0) << BIT_SHIFT_R3_L_1_0) +#define BITS_R3_L_1_0 (BIT_MASK_R3_L_1_0 << BIT_SHIFT_R3_L_1_0) +#define BIT_CLEAR_R3_L_1_0(x) ((x) & (~BITS_R3_L_1_0)) +#define BIT_GET_R3_L_1_0(x) (((x) >> BIT_SHIFT_R3_L_1_0) & BIT_MASK_R3_L_1_0) +#define BIT_SET_R3_L_1_0(x, v) (BIT_CLEAR_R3_L_1_0(x) | BIT_R3_L_1_0(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21) +#define BIT_SHIFT_R2_L 22 +#define BIT_MASK_R2_L 0x3 +#define BIT_R2_L(x) (((x) & BIT_MASK_R2_L) << BIT_SHIFT_R2_L) +#define BITS_R2_L (BIT_MASK_R2_L << BIT_SHIFT_R2_L) +#define BIT_CLEAR_R2_L(x) ((x) & (~BITS_R2_L)) +#define BIT_GET_R2_L(x) (((x) >> BIT_SHIFT_R2_L) & BIT_MASK_R2_L) +#define BIT_SET_R2_L(x, v) (BIT_CLEAR_R2_L(x) | BIT_R2_L(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_R2_L_1_0 22 +#define BIT_MASK_R2_L_1_0 0x3 +#define BIT_R2_L_1_0(x) (((x) & BIT_MASK_R2_L_1_0) << BIT_SHIFT_R2_L_1_0) +#define BITS_R2_L_1_0 (BIT_MASK_R2_L_1_0 << BIT_SHIFT_R2_L_1_0) +#define BIT_CLEAR_R2_L_1_0(x) ((x) & (~BITS_R2_L_1_0)) +#define BIT_GET_R2_L_1_0(x) (((x) >> BIT_SHIFT_R2_L_1_0) & BIT_MASK_R2_L_1_0) +#define BIT_SET_R2_L_1_0(x, v) (BIT_CLEAR_R2_L_1_0(x) | BIT_R2_L_1_0(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT2_RX_EOSP_OK_INT_EN BIT(20) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_R1_L 20 +#define BIT_MASK_R1_L 0x3 +#define BIT_R1_L(x) (((x) & BIT_MASK_R1_L) << BIT_SHIFT_R1_L) +#define BITS_R1_L (BIT_MASK_R1_L << BIT_SHIFT_R1_L) +#define BIT_CLEAR_R1_L(x) ((x) & (~BITS_R1_L)) +#define BIT_GET_R1_L(x) (((x) >> BIT_SHIFT_R1_L) & BIT_MASK_R1_L) +#define BIT_SET_R1_L(x, v) (BIT_CLEAR_R1_L(x) | BIT_R1_L(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_FS_CLI1_EOSP_INT_EN BIT(20) +#define BIT_SHIFT_R1_L_1_0 20 +#define BIT_MASK_R1_L_1_0 0x3 +#define BIT_R1_L_1_0(x) (((x) & BIT_MASK_R1_L_1_0) << BIT_SHIFT_R1_L_1_0) +#define BITS_R1_L_1_0 (BIT_MASK_R1_L_1_0 << BIT_SHIFT_R1_L_1_0) +#define BIT_CLEAR_R1_L_1_0(x) ((x) & (~BITS_R1_L_1_0)) +#define BIT_GET_R1_L_1_0(x) (((x) >> BIT_SHIFT_R1_L_1_0) & BIT_MASK_R1_L_1_0) +#define BIT_SET_R1_L_1_0(x, v) (BIT_CLEAR_R1_L_1_0(x) | BIT_R1_L_1_0(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_C3_L 18 +#define BIT_MASK_C3_L 0x3 +#define BIT_C3_L(x) (((x) & BIT_MASK_C3_L) << BIT_SHIFT_C3_L) +#define BITS_C3_L (BIT_MASK_C3_L << BIT_SHIFT_C3_L) +#define BIT_CLEAR_C3_L(x) ((x) & (~BITS_C3_L)) +#define BIT_GET_C3_L(x) (((x) >> BIT_SHIFT_C3_L) & BIT_MASK_C3_L) +#define BIT_SET_C3_L(x, v) (BIT_CLEAR_C3_L(x) | BIT_C3_L(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN BIT(19) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_C3_L_1_0 18 +#define BIT_MASK_C3_L_1_0 0x3 +#define BIT_C3_L_1_0(x) (((x) & BIT_MASK_C3_L_1_0) << BIT_SHIFT_C3_L_1_0) +#define BITS_C3_L_1_0 (BIT_MASK_C3_L_1_0 << BIT_SHIFT_C3_L_1_0) +#define BIT_CLEAR_C3_L_1_0(x) ((x) & (~BITS_C3_L_1_0)) +#define BIT_GET_C3_L_1_0(x) (((x) >> BIT_SHIFT_C3_L_1_0) & BIT_MASK_C3_L_1_0) +#define BIT_SET_C3_L_1_0(x, v) (BIT_CLEAR_C3_L_1_0(x) | BIT_C3_L_1_0(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19) +#define BIT_SHIFT_C2_L 16 +#define BIT_MASK_C2_L 0x3 +#define BIT_C2_L(x) (((x) & BIT_MASK_C2_L) << BIT_SHIFT_C2_L) +#define BITS_C2_L (BIT_MASK_C2_L << BIT_SHIFT_C2_L) +#define BIT_CLEAR_C2_L(x) ((x) & (~BITS_C2_L)) +#define BIT_GET_C2_L(x) (((x) >> BIT_SHIFT_C2_L) & BIT_MASK_C2_L) +#define BIT_SET_C2_L(x, v) (BIT_CLEAR_C2_L(x) | BIT_C2_L(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_C2_L_1_0 16 +#define BIT_MASK_C2_L_1_0 0x3 +#define BIT_C2_L_1_0(x) (((x) & BIT_MASK_C2_L_1_0) << BIT_SHIFT_C2_L_1_0) +#define BITS_C2_L_1_0 (BIT_MASK_C2_L_1_0 << BIT_SHIFT_C2_L_1_0) +#define BIT_CLEAR_C2_L_1_0(x) ((x) & (~BITS_C2_L_1_0)) +#define BIT_GET_C2_L_1_0(x) (((x) >> BIT_SHIFT_C2_L_1_0) & BIT_MASK_C2_L_1_0) +#define BIT_SET_C2_L_1_0(x, v) (BIT_CLEAR_C2_L_1_0(x) | BIT_C2_L_1_0(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN BIT(18) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_C1_L_V2 14 +#define BIT_MASK_C1_L_V2 0x3 +#define BIT_C1_L_V2(x) (((x) & BIT_MASK_C1_L_V2) << BIT_SHIFT_C1_L_V2) +#define BITS_C1_L_V2 (BIT_MASK_C1_L_V2 << BIT_SHIFT_C1_L_V2) +#define BIT_CLEAR_C1_L_V2(x) ((x) & (~BITS_C1_L_V2)) +#define BIT_GET_C1_L_V2(x) (((x) >> BIT_SHIFT_C1_L_V2) & BIT_MASK_C1_L_V2) +#define BIT_SET_C1_L_V2(x, v) (BIT_CLEAR_C1_L_V2(x) | BIT_C1_L_V2(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18) +#define BIT_SHIFT_C1_L_1_0 14 +#define BIT_MASK_C1_L_1_0 0x3 +#define BIT_C1_L_1_0(x) (((x) & BIT_MASK_C1_L_1_0) << BIT_SHIFT_C1_L_1_0) +#define BITS_C1_L_1_0 (BIT_MASK_C1_L_1_0 << BIT_SHIFT_C1_L_1_0) +#define BIT_CLEAR_C1_L_1_0(x) ((x) & (~BITS_C1_L_1_0)) +#define BIT_GET_C1_L_1_0(x) (((x) >> BIT_SHIFT_C1_L_1_0) & BIT_MASK_C1_L_1_0) +#define BIT_SET_C1_L_1_0(x, v) (BIT_CLEAR_C1_L_1_0(x) | BIT_C1_L_1_0(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_REG_TYPE_L_V2 BIT(13) +#define BIT_REG_PWM_L BIT(12) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT1_TRIPKT_OK_INT_EN BIT(17) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_V15ADJ_L 9 +#define BIT_MASK_V15ADJ_L 0x7 +#define BIT_V15ADJ_L(x) (((x) & BIT_MASK_V15ADJ_L) << BIT_SHIFT_V15ADJ_L) +#define BITS_V15ADJ_L (BIT_MASK_V15ADJ_L << BIT_SHIFT_V15ADJ_L) +#define BIT_CLEAR_V15ADJ_L(x) ((x) & (~BITS_V15ADJ_L)) +#define BIT_GET_V15ADJ_L(x) (((x) >> BIT_SHIFT_V15ADJ_L) & BIT_MASK_V15ADJ_L) +#define BIT_SET_V15ADJ_L(x, v) (BIT_CLEAR_V15ADJ_L(x) | BIT_V15ADJ_L(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17) +#define BIT_SHIFT_V15ADJ_L_2_0 9 +#define BIT_MASK_V15ADJ_L_2_0 0x7 +#define BIT_V15ADJ_L_2_0(x) \ + (((x) & BIT_MASK_V15ADJ_L_2_0) << BIT_SHIFT_V15ADJ_L_2_0) +#define BITS_V15ADJ_L_2_0 (BIT_MASK_V15ADJ_L_2_0 << BIT_SHIFT_V15ADJ_L_2_0) +#define BIT_CLEAR_V15ADJ_L_2_0(x) ((x) & (~BITS_V15ADJ_L_2_0)) +#define BIT_GET_V15ADJ_L_2_0(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L_2_0) & BIT_MASK_V15ADJ_L_2_0) +#define BIT_SET_V15ADJ_L_2_0(x, v) \ + (BIT_CLEAR_V15ADJ_L_2_0(x) | BIT_V15ADJ_L_2_0(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_IN_L 6 +#define BIT_MASK_IN_L 0x7 +#define BIT_IN_L(x) (((x) & BIT_MASK_IN_L) << BIT_SHIFT_IN_L) +#define BITS_IN_L (BIT_MASK_IN_L << BIT_SHIFT_IN_L) +#define BIT_CLEAR_IN_L(x) ((x) & (~BITS_IN_L)) +#define BIT_GET_IN_L(x) (((x) >> BIT_SHIFT_IN_L) & BIT_MASK_IN_L) +#define BIT_SET_IN_L(x, v) (BIT_CLEAR_IN_L(x) | BIT_IN_L(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT1_RX_EOSP_OK_INT_EN BIT(16) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_IN_L_2_0 6 +#define BIT_MASK_IN_L_2_0 0x7 +#define BIT_IN_L_2_0(x) (((x) & BIT_MASK_IN_L_2_0) << BIT_SHIFT_IN_L_2_0) +#define BITS_IN_L_2_0 (BIT_MASK_IN_L_2_0 << BIT_SHIFT_IN_L_2_0) +#define BIT_CLEAR_IN_L_2_0(x) ((x) & (~BITS_IN_L_2_0)) +#define BIT_GET_IN_L_2_0(x) (((x) >> BIT_SHIFT_IN_L_2_0) & BIT_MASK_IN_L_2_0) +#define BIT_SET_IN_L_2_0(x, v) (BIT_CLEAR_IN_L_2_0(x) | BIT_IN_L_2_0(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_FS_CLI0_EOSP_INT_EN BIT(16) +#define BIT_SHIFT_STD_L 4 +#define BIT_MASK_STD_L 0x3 +#define BIT_STD_L(x) (((x) & BIT_MASK_STD_L) << BIT_SHIFT_STD_L) +#define BITS_STD_L (BIT_MASK_STD_L << BIT_SHIFT_STD_L) +#define BIT_CLEAR_STD_L(x) ((x) & (~BITS_STD_L)) +#define BIT_GET_STD_L(x) (((x) >> BIT_SHIFT_STD_L) & BIT_MASK_STD_L) +#define BIT_SET_STD_L(x, v) (BIT_CLEAR_STD_L(x) | BIT_STD_L(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_STD_L_1_0 4 +#define BIT_MASK_STD_L_1_0 0x3 +#define BIT_STD_L_1_0(x) (((x) & BIT_MASK_STD_L_1_0) << BIT_SHIFT_STD_L_1_0) +#define BITS_STD_L_1_0 (BIT_MASK_STD_L_1_0 << BIT_SHIFT_STD_L_1_0) +#define BIT_CLEAR_STD_L_1_0(x) ((x) & (~BITS_STD_L_1_0)) +#define BIT_GET_STD_L_1_0(x) (((x) >> BIT_SHIFT_STD_L_1_0) & BIT_MASK_STD_L_1_0) +#define BIT_SET_STD_L_1_0(x, v) (BIT_CLEAR_STD_L_1_0(x) | BIT_STD_L_1_0(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN BIT(9) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ +#define BIT_SHIFT_VOL_L 0 +#define BIT_MASK_VOL_L 0xf +#define BIT_VOL_L(x) (((x) & BIT_MASK_VOL_L) << BIT_SHIFT_VOL_L) +#define BITS_VOL_L (BIT_MASK_VOL_L << BIT_SHIFT_VOL_L) +#define BIT_CLEAR_VOL_L(x) ((x) & (~BITS_VOL_L)) +#define BIT_GET_VOL_L(x) (((x) >> BIT_SHIFT_VOL_L) & BIT_MASK_VOL_L) +#define BIT_SET_VOL_L(x, v) (BIT_CLEAR_VOL_L(x) | BIT_VOL_L(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */ -#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9) +#define BIT_SHIFT_VOL_L_3_0 0 +#define BIT_MASK_VOL_L_3_0 0xf +#define BIT_VOL_L_3_0(x) (((x) & BIT_MASK_VOL_L_3_0) << BIT_SHIFT_VOL_L_3_0) +#define BITS_VOL_L_3_0 (BIT_MASK_VOL_L_3_0 << BIT_SHIFT_VOL_L_3_0) +#define BIT_CLEAR_VOL_L_3_0(x) ((x) & (~BITS_VOL_L_3_0)) +#define BIT_GET_VOL_L_3_0(x) (((x) >> BIT_SHIFT_VOL_L_3_0) & BIT_MASK_VOL_L_3_0) +#define BIT_SET_VOL_L_3_0(x, v) (BIT_CLEAR_VOL_L_3_0(x) | BIT_VOL_L_3_0(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#define BIT_SHIFT_OCP_L_PFM 29 +#define BIT_MASK_OCP_L_PFM 0x7 +#define BIT_OCP_L_PFM(x) (((x) & BIT_MASK_OCP_L_PFM) << BIT_SHIFT_OCP_L_PFM) +#define BITS_OCP_L_PFM (BIT_MASK_OCP_L_PFM << BIT_SHIFT_OCP_L_PFM) +#define BIT_CLEAR_OCP_L_PFM(x) ((x) & (~BITS_OCP_L_PFM)) +#define BIT_GET_OCP_L_PFM(x) (((x) >> BIT_SHIFT_OCP_L_PFM) & BIT_MASK_OCP_L_PFM) +#define BIT_SET_OCP_L_PFM(x, v) (BIT_CLEAR_OCP_L_PFM(x) | BIT_OCP_L_PFM(v)) -#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN BIT(8) +#define BIT_SHIFT_CFC_L_PFM 27 +#define BIT_MASK_CFC_L_PFM 0x3 +#define BIT_CFC_L_PFM(x) (((x) & BIT_MASK_CFC_L_PFM) << BIT_SHIFT_CFC_L_PFM) +#define BITS_CFC_L_PFM (BIT_MASK_CFC_L_PFM << BIT_SHIFT_CFC_L_PFM) +#define BIT_CLEAR_CFC_L_PFM(x) ((x) & (~BITS_CFC_L_PFM)) +#define BIT_GET_CFC_L_PFM(x) (((x) >> BIT_SHIFT_CFC_L_PFM) & BIT_MASK_CFC_L_PFM) +#define BIT_SET_CFC_L_PFM(x, v) (BIT_CLEAR_CFC_L_PFM(x) | BIT_CFC_L_PFM(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#define BIT_SHIFT_REG_FREQ_L_V1 20 +#define BIT_MASK_REG_FREQ_L_V1 0x7 +#define BIT_REG_FREQ_L_V1(x) \ + (((x) & BIT_MASK_REG_FREQ_L_V1) << BIT_SHIFT_REG_FREQ_L_V1) +#define BITS_REG_FREQ_L_V1 (BIT_MASK_REG_FREQ_L_V1 << BIT_SHIFT_REG_FREQ_L_V1) +#define BIT_CLEAR_REG_FREQ_L_V1(x) ((x) & (~BITS_REG_FREQ_L_V1)) +#define BIT_GET_REG_FREQ_L_V1(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_V1) & BIT_MASK_REG_FREQ_L_V1) +#define BIT_SET_REG_FREQ_L_V1(x, v) \ + (BIT_CLEAR_REG_FREQ_L_V1(x) | BIT_REG_FREQ_L_V1(v)) -#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8) +#define BIT_EN_DUTY BIT(19) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_REG_MODE_V2 17 +#define BIT_MASK_REG_MODE_V2 0x3 +#define BIT_REG_MODE_V2(x) \ + (((x) & BIT_MASK_REG_MODE_V2) << BIT_SHIFT_REG_MODE_V2) +#define BITS_REG_MODE_V2 (BIT_MASK_REG_MODE_V2 << BIT_SHIFT_REG_MODE_V2) +#define BIT_CLEAR_REG_MODE_V2(x) ((x) & (~BITS_REG_MODE_V2)) +#define BIT_GET_REG_MODE_V2(x) \ + (((x) >> BIT_SHIFT_REG_MODE_V2) & BIT_MASK_REG_MODE_V2) +#define BIT_SET_REG_MODE_V2(x, v) \ + (BIT_CLEAR_REG_MODE_V2(x) | BIT_REG_MODE_V2(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT4_TX_NULL1_DONE_INT_EN BIT(7) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_REG_MOS_HALF 17 +#define BIT_MASK_REG_MOS_HALF 0x3 +#define BIT_REG_MOS_HALF(x) \ + (((x) & BIT_MASK_REG_MOS_HALF) << BIT_SHIFT_REG_MOS_HALF) +#define BITS_REG_MOS_HALF (BIT_MASK_REG_MOS_HALF << BIT_SHIFT_REG_MOS_HALF) +#define BIT_CLEAR_REG_MOS_HALF(x) ((x) & (~BITS_REG_MOS_HALF)) +#define BIT_GET_REG_MOS_HALF(x) \ + (((x) >> BIT_SHIFT_REG_MOS_HALF) & BIT_MASK_REG_MOS_HALF) +#define BIT_SET_REG_MOS_HALF(x, v) \ + (BIT_CLEAR_REG_MOS_HALF(x) | BIT_REG_MOS_HALF(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -#define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7) +#define BIT_EN_SP BIT(16) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_REG_AUTO_L_V2 BIT(15) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT4_TX_NULL0_DONE_INT_EN BIT(6) +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ + +#define BIT_REG_AUTO_L_V1 BIT(15) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_REG_LDOF_L_V2 BIT(14) +#define BIT_REG_OCPS_L_V2 BIT(13) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ + +#define BIT_VO15_V1P05_H BIT(12) +#define BIT_ARENB_L_V2 BIT(11) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_ARENB_L_V1 BIT(11) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -#define BIT_PORT3_TX_NULL1_DONE_INT_EN BIT(5) +#define BIT_SHIFT_TBOX_L1_V2 9 +#define BIT_MASK_TBOX_L1_V2 0x3 +#define BIT_TBOX_L1_V2(x) (((x) & BIT_MASK_TBOX_L1_V2) << BIT_SHIFT_TBOX_L1_V2) +#define BITS_TBOX_L1_V2 (BIT_MASK_TBOX_L1_V2 << BIT_SHIFT_TBOX_L1_V2) +#define BIT_CLEAR_TBOX_L1_V2(x) ((x) & (~BITS_TBOX_L1_V2)) +#define BIT_GET_TBOX_L1_V2(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_V2) & BIT_MASK_TBOX_L1_V2) +#define BIT_SET_TBOX_L1_V2(x, v) (BIT_CLEAR_TBOX_L1_V2(x) | BIT_TBOX_L1_V2(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_TBOX_L1_1_0 9 +#define BIT_MASK_TBOX_L1_1_0 0x3 +#define BIT_TBOX_L1_1_0(x) \ + (((x) & BIT_MASK_TBOX_L1_1_0) << BIT_SHIFT_TBOX_L1_1_0) +#define BITS_TBOX_L1_1_0 (BIT_MASK_TBOX_L1_1_0 << BIT_SHIFT_TBOX_L1_1_0) +#define BIT_CLEAR_TBOX_L1_1_0(x) ((x) & (~BITS_TBOX_L1_1_0)) +#define BIT_GET_TBOX_L1_1_0(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_1_0) & BIT_MASK_TBOX_L1_1_0) +#define BIT_SET_TBOX_L1_1_0(x, v) \ + (BIT_CLEAR_TBOX_L1_1_0(x) | BIT_TBOX_L1_1_0(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ + +#define BIT_SHIFT_REG_DELAY_L 7 +#define BIT_MASK_REG_DELAY_L 0x3 +#define BIT_REG_DELAY_L(x) \ + (((x) & BIT_MASK_REG_DELAY_L) << BIT_SHIFT_REG_DELAY_L) +#define BITS_REG_DELAY_L (BIT_MASK_REG_DELAY_L << BIT_SHIFT_REG_DELAY_L) +#define BIT_CLEAR_REG_DELAY_L(x) ((x) & (~BITS_REG_DELAY_L)) +#define BIT_GET_REG_DELAY_L(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_L) & BIT_MASK_REG_DELAY_L) +#define BIT_SET_REG_DELAY_L(x, v) \ + (BIT_CLEAR_REG_DELAY_L(x) | BIT_REG_DELAY_L(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_REG_DELAY_L_1_0 7 +#define BIT_MASK_REG_DELAY_L_1_0 0x3 +#define BIT_REG_DELAY_L_1_0(x) \ + (((x) & BIT_MASK_REG_DELAY_L_1_0) << BIT_SHIFT_REG_DELAY_L_1_0) +#define BITS_REG_DELAY_L_1_0 \ + (BIT_MASK_REG_DELAY_L_1_0 << BIT_SHIFT_REG_DELAY_L_1_0) +#define BIT_CLEAR_REG_DELAY_L_1_0(x) ((x) & (~BITS_REG_DELAY_L_1_0)) +#define BIT_GET_REG_DELAY_L_1_0(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_L_1_0) & BIT_MASK_REG_DELAY_L_1_0) +#define BIT_SET_REG_DELAY_L_1_0(x, v) \ + (BIT_CLEAR_REG_DELAY_L_1_0(x) | BIT_REG_DELAY_L_1_0(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT3_TX_NULL0_DONE_INT_EN BIT(4) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ + +#define BIT_REG_CLAMP_D_L BIT(6) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_REG_BYPASS_L_V2 BIT(5) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ + +#define BIT_REG_BYPASS_L_V1 BIT(5) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_REG_AUTOZCD_L BIT(4) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ -#define BIT_PORT2_TX_NULL1_DONE_INT_EN BIT(3) +#define BIT_POW_ZCD_L_V2 BIT(3) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_POW_ZCD_L_V1 BIT(3) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ + +#define BIT_REG_HALF_L BIT(2) + +#define BIT_SHIFT_OCP_L_V2 0 +#define BIT_MASK_OCP_L_V2 0x3 +#define BIT_OCP_L_V2(x) (((x) & BIT_MASK_OCP_L_V2) << BIT_SHIFT_OCP_L_V2) +#define BITS_OCP_L_V2 (BIT_MASK_OCP_L_V2 << BIT_SHIFT_OCP_L_V2) +#define BIT_CLEAR_OCP_L_V2(x) ((x) & (~BITS_OCP_L_V2)) +#define BIT_GET_OCP_L_V2(x) (((x) >> BIT_SHIFT_OCP_L_V2) & BIT_MASK_OCP_L_V2) +#define BIT_SET_OCP_L_V2(x, v) (BIT_CLEAR_OCP_L_V2(x) | BIT_OCP_L_V2(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */ +#define BIT_SHIFT_OCP_L_2_1 0 +#define BIT_MASK_OCP_L_2_1 0x3 +#define BIT_OCP_L_2_1(x) (((x) & BIT_MASK_OCP_L_2_1) << BIT_SHIFT_OCP_L_2_1) +#define BITS_OCP_L_2_1 (BIT_MASK_OCP_L_2_1 << BIT_SHIFT_OCP_L_2_1) +#define BIT_CLEAR_OCP_L_2_1(x) ((x) & (~BITS_OCP_L_2_1)) +#define BIT_GET_OCP_L_2_1(x) (((x) >> BIT_SHIFT_OCP_L_2_1) & BIT_MASK_OCP_L_2_1) +#define BIT_SET_OCP_L_2_1(x, v) (BIT_CLEAR_OCP_L_2_1(x) | BIT_OCP_L_2_1(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ -#define BIT_PORT2_TX_NULL0_DONE_INT_EN BIT(2) +#define BIT_SHIFT_LPF_C2_1_0 30 +#define BIT_MASK_LPF_C2_1_0 0x3 +#define BIT_LPF_C2_1_0(x) (((x) & BIT_MASK_LPF_C2_1_0) << BIT_SHIFT_LPF_C2_1_0) +#define BITS_LPF_C2_1_0 (BIT_MASK_LPF_C2_1_0 << BIT_SHIFT_LPF_C2_1_0) +#define BIT_CLEAR_LPF_C2_1_0(x) ((x) & (~BITS_LPF_C2_1_0)) +#define BIT_GET_LPF_C2_1_0(x) \ + (((x) >> BIT_SHIFT_LPF_C2_1_0) & BIT_MASK_LPF_C2_1_0) +#define BIT_SET_LPF_C2_1_0(x, v) (BIT_CLEAR_LPF_C2_1_0(x) | BIT_LPF_C2_1_0(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_REG_LPF_R3 29 +#define BIT_MASK_REG_LPF_R3 0x7 +#define BIT_REG_LPF_R3(x) (((x) & BIT_MASK_REG_LPF_R3) << BIT_SHIFT_REG_LPF_R3) +#define BITS_REG_LPF_R3 (BIT_MASK_REG_LPF_R3 << BIT_SHIFT_REG_LPF_R3) +#define BIT_CLEAR_REG_LPF_R3(x) ((x) & (~BITS_REG_LPF_R3)) +#define BIT_GET_REG_LPF_R3(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3) & BIT_MASK_REG_LPF_R3) +#define BIT_SET_REG_LPF_R3(x, v) (BIT_CLEAR_REG_LPF_R3(x) | BIT_REG_LPF_R3(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ + +#define BIT_EN_XTAL_AAC_TRIG BIT(28) +#define BIT_EN_XTAL_AAC BIT(27) +#define BIT_EN_XTAL_AAC_DIGI BIT(26) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_REG_LPF_R2 24 +#define BIT_MASK_REG_LPF_R2 0x1f +#define BIT_REG_LPF_R2(x) (((x) & BIT_MASK_REG_LPF_R2) << BIT_SHIFT_REG_LPF_R2) +#define BITS_REG_LPF_R2 (BIT_MASK_REG_LPF_R2 << BIT_SHIFT_REG_LPF_R2) +#define BIT_CLEAR_REG_LPF_R2(x) ((x) & (~BITS_REG_LPF_R2)) +#define BIT_GET_REG_LPF_R2(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R2) & BIT_MASK_REG_LPF_R2) +#define BIT_SET_REG_LPF_R2(x, v) (BIT_CLEAR_REG_LPF_R2(x) | BIT_REG_LPF_R2(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif -#define BIT_PORT1_TX_NULL1_DONE_INT_EN BIT(1) +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ + +#define BIT_SHIFT_LPF_C1_5_0 24 +#define BIT_MASK_LPF_C1_5_0 0x3f +#define BIT_LPF_C1_5_0(x) (((x) & BIT_MASK_LPF_C1_5_0) << BIT_SHIFT_LPF_C1_5_0) +#define BITS_LPF_C1_5_0 (BIT_MASK_LPF_C1_5_0 << BIT_SHIFT_LPF_C1_5_0) +#define BIT_CLEAR_LPF_C1_5_0(x) ((x) & (~BITS_LPF_C1_5_0)) +#define BIT_GET_LPF_C1_5_0(x) \ + (((x) >> BIT_SHIFT_LPF_C1_5_0) & BIT_MASK_LPF_C1_5_0) +#define BIT_SET_LPF_C1_5_0(x, v) (BIT_CLEAR_LPF_C1_5_0(x) | BIT_LPF_C1_5_0(v)) + +#define BIT_LPF_TIEL BIT(23) +#define BIT_LPF_TIEH BIT(22) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_REG_LPF_C3 21 +#define BIT_MASK_REG_LPF_C3 0x7 +#define BIT_REG_LPF_C3(x) (((x) & BIT_MASK_REG_LPF_C3) << BIT_SHIFT_REG_LPF_C3) +#define BITS_REG_LPF_C3 (BIT_MASK_REG_LPF_C3 << BIT_SHIFT_REG_LPF_C3) +#define BIT_CLEAR_REG_LPF_C3(x) ((x) & (~BITS_REG_LPF_C3)) +#define BIT_GET_REG_LPF_C3(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C3) & BIT_MASK_REG_LPF_C3) +#define BIT_SET_REG_LPF_C3(x, v) (BIT_CLEAR_REG_LPF_C3(x) | BIT_REG_LPF_C3(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ -#define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1) +#define BIT_SHIFT_LOCKDET_VREF_L_1_0 20 +#define BIT_MASK_LOCKDET_VREF_L_1_0 0x3 +#define BIT_LOCKDET_VREF_L_1_0(x) \ + (((x) & BIT_MASK_LOCKDET_VREF_L_1_0) << BIT_SHIFT_LOCKDET_VREF_L_1_0) +#define BITS_LOCKDET_VREF_L_1_0 \ + (BIT_MASK_LOCKDET_VREF_L_1_0 << BIT_SHIFT_LOCKDET_VREF_L_1_0) +#define BIT_CLEAR_LOCKDET_VREF_L_1_0(x) ((x) & (~BITS_LOCKDET_VREF_L_1_0)) +#define BIT_GET_LOCKDET_VREF_L_1_0(x) \ + (((x) >> BIT_SHIFT_LOCKDET_VREF_L_1_0) & BIT_MASK_LOCKDET_VREF_L_1_0) +#define BIT_SET_LOCKDET_VREF_L_1_0(x, v) \ + (BIT_CLEAR_LOCKDET_VREF_L_1_0(x) | BIT_LOCKDET_VREF_L_1_0(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_REG_LPF_C2 18 +#define BIT_MASK_REG_LPF_C2 0x7 +#define BIT_REG_LPF_C2(x) (((x) & BIT_MASK_REG_LPF_C2) << BIT_SHIFT_REG_LPF_C2) +#define BITS_REG_LPF_C2 (BIT_MASK_REG_LPF_C2 << BIT_SHIFT_REG_LPF_C2) +#define BIT_CLEAR_REG_LPF_C2(x) ((x) & (~BITS_REG_LPF_C2)) +#define BIT_GET_REG_LPF_C2(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C2) & BIT_MASK_REG_LPF_C2) +#define BIT_SET_REG_LPF_C2(x, v) (BIT_CLEAR_REG_LPF_C2(x) | BIT_REG_LPF_C2(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_PORT1_TX_NULL0_DONE_INT_EN BIT(0) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ + +#define BIT_SHIFT_LOCKDET_VREF_H_1_0 18 +#define BIT_MASK_LOCKDET_VREF_H_1_0 0x3 +#define BIT_LOCKDET_VREF_H_1_0(x) \ + (((x) & BIT_MASK_LOCKDET_VREF_H_1_0) << BIT_SHIFT_LOCKDET_VREF_H_1_0) +#define BITS_LOCKDET_VREF_H_1_0 \ + (BIT_MASK_LOCKDET_VREF_H_1_0 << BIT_SHIFT_LOCKDET_VREF_H_1_0) +#define BIT_CLEAR_LOCKDET_VREF_H_1_0(x) ((x) & (~BITS_LOCKDET_VREF_H_1_0)) +#define BIT_GET_LOCKDET_VREF_H_1_0(x) \ + (((x) >> BIT_SHIFT_LOCKDET_VREF_H_1_0) & BIT_MASK_LOCKDET_VREF_H_1_0) +#define BIT_SET_LOCKDET_VREF_H_1_0(x, v) \ + (BIT_CLEAR_LOCKDET_VREF_H_1_0(x) | BIT_LOCKDET_VREF_H_1_0(v)) + +#define BIT_SHIFT_LDO_SEL_1_0 16 +#define BIT_MASK_LDO_SEL_1_0 0x3 +#define BIT_LDO_SEL_1_0(x) \ + (((x) & BIT_MASK_LDO_SEL_1_0) << BIT_SHIFT_LDO_SEL_1_0) +#define BITS_LDO_SEL_1_0 (BIT_MASK_LDO_SEL_1_0 << BIT_SHIFT_LDO_SEL_1_0) +#define BIT_CLEAR_LDO_SEL_1_0(x) ((x) & (~BITS_LDO_SEL_1_0)) +#define BIT_GET_LDO_SEL_1_0(x) \ + (((x) >> BIT_SHIFT_LDO_SEL_1_0) & BIT_MASK_LDO_SEL_1_0) +#define BIT_SET_LDO_SEL_1_0(x, v) \ + (BIT_CLEAR_LDO_SEL_1_0(x) | BIT_LDO_SEL_1_0(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_REG_LPF_C1 15 +#define BIT_MASK_REG_LPF_C1 0x7 +#define BIT_REG_LPF_C1(x) (((x) & BIT_MASK_REG_LPF_C1) << BIT_SHIFT_REG_LPF_C1) +#define BITS_REG_LPF_C1 (BIT_MASK_REG_LPF_C1 << BIT_SHIFT_REG_LPF_C1) +#define BIT_CLEAR_REG_LPF_C1(x) ((x) & (~BITS_REG_LPF_C1)) +#define BIT_GET_REG_LPF_C1(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C1) & BIT_MASK_REG_LPF_C1) +#define BIT_SET_REG_LPF_C1(x, v) (BIT_CLEAR_REG_LPF_C1(x) | BIT_REG_LPF_C1(v)) -/* 2 REG_FT2IMR (Offset 0x11E0) */ +#define BIT_SHIFT_REG_LDO_SEL_V1 13 +#define BIT_MASK_REG_LDO_SEL_V1 0x3 +#define BIT_REG_LDO_SEL_V1(x) \ + (((x) & BIT_MASK_REG_LDO_SEL_V1) << BIT_SHIFT_REG_LDO_SEL_V1) +#define BITS_REG_LDO_SEL_V1 \ + (BIT_MASK_REG_LDO_SEL_V1 << BIT_SHIFT_REG_LDO_SEL_V1) +#define BIT_CLEAR_REG_LDO_SEL_V1(x) ((x) & (~BITS_REG_LDO_SEL_V1)) +#define BIT_GET_REG_LDO_SEL_V1(x) \ + (((x) >> BIT_SHIFT_REG_LDO_SEL_V1) & BIT_MASK_REG_LDO_SEL_V1) +#define BIT_SET_REG_LDO_SEL_V1(x, v) \ + (BIT_CLEAR_REG_LDO_SEL_V1(x) | BIT_REG_LDO_SEL_V1(v)) -#define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0) +#define BIT_REG_CP_ICPX2 BIT(12) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_IOFFSET_5_0 10 +#define BIT_MASK_IOFFSET_5_0 0x3f +#define BIT_IOFFSET_5_0(x) \ + (((x) & BIT_MASK_IOFFSET_5_0) << BIT_SHIFT_IOFFSET_5_0) +#define BITS_IOFFSET_5_0 (BIT_MASK_IOFFSET_5_0 << BIT_SHIFT_IOFFSET_5_0) +#define BIT_CLEAR_IOFFSET_5_0(x) ((x) & (~BITS_IOFFSET_5_0)) +#define BIT_GET_IOFFSET_5_0(x) \ + (((x) >> BIT_SHIFT_IOFFSET_5_0) & BIT_MASK_IOFFSET_5_0) +#define BIT_SET_IOFFSET_5_0(x, v) \ + (BIT_CLEAR_IOFFSET_5_0(x) | BIT_IOFFSET_5_0(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT BIT(31) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ + +#define BIT_SHIFT_REG_CP_ICP_SEL_FAST 9 +#define BIT_MASK_REG_CP_ICP_SEL_FAST 0x7 +#define BIT_REG_CP_ICP_SEL_FAST(x) \ + (((x) & BIT_MASK_REG_CP_ICP_SEL_FAST) << BIT_SHIFT_REG_CP_ICP_SEL_FAST) +#define BITS_REG_CP_ICP_SEL_FAST \ + (BIT_MASK_REG_CP_ICP_SEL_FAST << BIT_SHIFT_REG_CP_ICP_SEL_FAST) +#define BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) ((x) & (~BITS_REG_CP_ICP_SEL_FAST)) +#define BIT_GET_REG_CP_ICP_SEL_FAST(x) \ + (((x) >> BIT_SHIFT_REG_CP_ICP_SEL_FAST) & BIT_MASK_REG_CP_ICP_SEL_FAST) +#define BIT_SET_REG_CP_ICP_SEL_FAST(x, v) \ + (BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) | BIT_REG_CP_ICP_SEL_FAST(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_CP_ICPX2 BIT(9) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ + +#define BIT_GM_STEP BIT(7) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_SHIFT_REG_CP_ICP_SEL 6 +#define BIT_MASK_REG_CP_ICP_SEL 0x7 +#define BIT_REG_CP_ICP_SEL(x) \ + (((x) & BIT_MASK_REG_CP_ICP_SEL) << BIT_SHIFT_REG_CP_ICP_SEL) +#define BITS_REG_CP_ICP_SEL \ + (BIT_MASK_REG_CP_ICP_SEL << BIT_SHIFT_REG_CP_ICP_SEL) +#define BIT_CLEAR_REG_CP_ICP_SEL(x) ((x) & (~BITS_REG_CP_ICP_SEL)) +#define BIT_GET_REG_CP_ICP_SEL(x) \ + (((x) >> BIT_SHIFT_REG_CP_ICP_SEL) & BIT_MASK_REG_CP_ICP_SEL) +#define BIT_SET_REG_CP_ICP_SEL(x, v) \ + (BIT_CLEAR_REG_CP_ICP_SEL(x) | BIT_REG_CP_ICP_SEL(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_SHIFT_REG_IB_PI 4 +#define BIT_MASK_REG_IB_PI 0x3 +#define BIT_REG_IB_PI(x) (((x) & BIT_MASK_REG_IB_PI) << BIT_SHIFT_REG_IB_PI) +#define BITS_REG_IB_PI (BIT_MASK_REG_IB_PI << BIT_SHIFT_REG_IB_PI) +#define BIT_CLEAR_REG_IB_PI(x) ((x) & (~BITS_REG_IB_PI)) +#define BIT_GET_REG_IB_PI(x) (((x) >> BIT_SHIFT_REG_IB_PI) & BIT_MASK_REG_IB_PI) +#define BIT_SET_REG_IB_PI(x, v) (BIT_CLEAR_REG_IB_PI(x) | BIT_REG_IB_PI(v)) -#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT BIT(30) +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ + +#define BIT_SHIFT_CP_ICP_SEL_4_0 4 +#define BIT_MASK_CP_ICP_SEL_4_0 0x1f +#define BIT_CP_ICP_SEL_4_0(x) \ + (((x) & BIT_MASK_CP_ICP_SEL_4_0) << BIT_SHIFT_CP_ICP_SEL_4_0) +#define BITS_CP_ICP_SEL_4_0 \ + (BIT_MASK_CP_ICP_SEL_4_0 << BIT_SHIFT_CP_ICP_SEL_4_0) +#define BIT_CLEAR_CP_ICP_SEL_4_0(x) ((x) & (~BITS_CP_ICP_SEL_4_0)) +#define BIT_GET_CP_ICP_SEL_4_0(x) \ + (((x) >> BIT_SHIFT_CP_ICP_SEL_4_0) & BIT_MASK_CP_ICP_SEL_4_0) +#define BIT_SET_CP_ICP_SEL_4_0(x, v) \ + (BIT_CLEAR_CP_ICP_SEL_4_0(x) | BIT_CP_ICP_SEL_4_0(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_LDO2PWRCUT BIT(3) +#define BIT_VPULSE_LDO BIT(2) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ + +#define BIT_SHIFT_IB_PI_1_0 2 +#define BIT_MASK_IB_PI_1_0 0x3 +#define BIT_IB_PI_1_0(x) (((x) & BIT_MASK_IB_PI_1_0) << BIT_SHIFT_IB_PI_1_0) +#define BITS_IB_PI_1_0 (BIT_MASK_IB_PI_1_0 << BIT_SHIFT_IB_PI_1_0) +#define BIT_CLEAR_IB_PI_1_0(x) ((x) & (~BITS_IB_PI_1_0)) +#define BIT_GET_IB_PI_1_0(x) (((x) >> BIT_SHIFT_IB_PI_1_0) & BIT_MASK_IB_PI_1_0) +#define BIT_SET_IB_PI_1_0(x, v) (BIT_CLEAR_IB_PI_1_0(x) | BIT_IB_PI_1_0(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */ +#define BIT_OFFSET_PLUS BIT(1) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_SHIFT_LDO_VSEL 0 +#define BIT_MASK_LDO_VSEL 0x3 +#define BIT_LDO_VSEL(x) (((x) & BIT_MASK_LDO_VSEL) << BIT_SHIFT_LDO_VSEL) +#define BITS_LDO_VSEL (BIT_MASK_LDO_VSEL << BIT_SHIFT_LDO_VSEL) +#define BIT_CLEAR_LDO_VSEL(x) ((x) & (~BITS_LDO_VSEL)) +#define BIT_GET_LDO_VSEL(x) (((x) >> BIT_SHIFT_LDO_VSEL) & BIT_MASK_LDO_VSEL) +#define BIT_SET_LDO_VSEL(x, v) (BIT_CLEAR_LDO_VSEL(x) | BIT_LDO_VSEL(v)) -#define BIT_PORT4_TRIPKT_OK_INT BIT(29) +#define BIT_RESET_N BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_REG_CK_MON_SEL 29 +#define BIT_MASK_REG_CK_MON_SEL 0x7 +#define BIT_REG_CK_MON_SEL(x) \ + (((x) & BIT_MASK_REG_CK_MON_SEL) << BIT_SHIFT_REG_CK_MON_SEL) +#define BITS_REG_CK_MON_SEL \ + (BIT_MASK_REG_CK_MON_SEL << BIT_SHIFT_REG_CK_MON_SEL) +#define BIT_CLEAR_REG_CK_MON_SEL(x) ((x) & (~BITS_REG_CK_MON_SEL)) +#define BIT_GET_REG_CK_MON_SEL(x) \ + (((x) >> BIT_SHIFT_REG_CK_MON_SEL) & BIT_MASK_REG_CK_MON_SEL) +#define BIT_SET_REG_CK_MON_SEL(x, v) \ + (BIT_CLEAR_REG_CK_MON_SEL(x) | BIT_REG_CK_MON_SEL(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_CKX_USB_IB_SEL 29 +#define BIT_MASK_CKX_USB_IB_SEL 0x7 +#define BIT_CKX_USB_IB_SEL(x) \ + (((x) & BIT_MASK_CKX_USB_IB_SEL) << BIT_SHIFT_CKX_USB_IB_SEL) +#define BITS_CKX_USB_IB_SEL \ + (BIT_MASK_CKX_USB_IB_SEL << BIT_SHIFT_CKX_USB_IB_SEL) +#define BIT_CLEAR_CKX_USB_IB_SEL(x) ((x) & (~BITS_CKX_USB_IB_SEL)) +#define BIT_GET_CKX_USB_IB_SEL(x) \ + (((x) >> BIT_SHIFT_CKX_USB_IB_SEL) & BIT_MASK_CKX_USB_IB_SEL) +#define BIT_SET_CKX_USB_IB_SEL(x, v) \ + (BIT_CLEAR_CKX_USB_IB_SEL(x) | BIT_CKX_USB_IB_SEL(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ -#define BIT_PORT4_RX_EOSP_OK_INT BIT(28) +#define BIT_REG_CK_MON_EN BIT(28) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_PFD_DN_GATED BIT(28) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_FS_CLI3_EOSP_INT BIT(28) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ + +#define BIT_REG_XTAL_FREQ_SEL BIT(27) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_PFD_UP_GATED BIT(27) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ -#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT BIT(27) +#define BIT_REG_XTAL_EDGE_SEL BIT(26) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_PFD_RESET_GATED BIT(26) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ + +#define BIT_REG_VCO_KVCO BIT(25) +#define BIT_REG_SDM_EDGE_SEL BIT(24) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_PFD_OUT_DRV_1_0 24 +#define BIT_MASK_PFD_OUT_DRV_1_0 0x3 +#define BIT_PFD_OUT_DRV_1_0(x) \ + (((x) & BIT_MASK_PFD_OUT_DRV_1_0) << BIT_SHIFT_PFD_OUT_DRV_1_0) +#define BITS_PFD_OUT_DRV_1_0 \ + (BIT_MASK_PFD_OUT_DRV_1_0 << BIT_SHIFT_PFD_OUT_DRV_1_0) +#define BIT_CLEAR_PFD_OUT_DRV_1_0(x) ((x) & (~BITS_PFD_OUT_DRV_1_0)) +#define BIT_GET_PFD_OUT_DRV_1_0(x) \ + (((x) >> BIT_SHIFT_PFD_OUT_DRV_1_0) & BIT_MASK_PFD_OUT_DRV_1_0) +#define BIT_SET_PFD_OUT_DRV_1_0(x, v) \ + (BIT_CLEAR_PFD_OUT_DRV_1_0(x) | BIT_PFD_OUT_DRV_1_0(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT BIT(26) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ + +#define BIT_REG_SDM_CK_SEL BIT(23) +#define BIT_REG_SDM_CK_GATED BIT(22) +#define BIT_REG_PFD_RESET_GATED BIT(21) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_LPF_TIEMID_2_0 20 +#define BIT_MASK_LPF_TIEMID_2_0 0x7 +#define BIT_LPF_TIEMID_2_0(x) \ + (((x) & BIT_MASK_LPF_TIEMID_2_0) << BIT_SHIFT_LPF_TIEMID_2_0) +#define BITS_LPF_TIEMID_2_0 \ + (BIT_MASK_LPF_TIEMID_2_0 << BIT_SHIFT_LPF_TIEMID_2_0) +#define BIT_CLEAR_LPF_TIEMID_2_0(x) ((x) & (~BITS_LPF_TIEMID_2_0)) +#define BIT_GET_LPF_TIEMID_2_0(x) \ + (((x) >> BIT_SHIFT_LPF_TIEMID_2_0) & BIT_MASK_LPF_TIEMID_2_0) +#define BIT_SET_LPF_TIEMID_2_0(x, v) \ + (BIT_CLEAR_LPF_TIEMID_2_0(x) | BIT_LPF_TIEMID_2_0(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ + +#define BIT_SHIFT_REG_LPF_R3_FAST 16 +#define BIT_MASK_REG_LPF_R3_FAST 0x1f +#define BIT_REG_LPF_R3_FAST(x) \ + (((x) & BIT_MASK_REG_LPF_R3_FAST) << BIT_SHIFT_REG_LPF_R3_FAST) +#define BITS_REG_LPF_R3_FAST \ + (BIT_MASK_REG_LPF_R3_FAST << BIT_SHIFT_REG_LPF_R3_FAST) +#define BIT_CLEAR_REG_LPF_R3_FAST(x) ((x) & (~BITS_REG_LPF_R3_FAST)) +#define BIT_GET_REG_LPF_R3_FAST(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3_FAST) & BIT_MASK_REG_LPF_R3_FAST) +#define BIT_SET_REG_LPF_R3_FAST(x, v) \ + (BIT_CLEAR_REG_LPF_R3_FAST(x) | BIT_REG_LPF_R3_FAST(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_LPF_R3_4_0 15 +#define BIT_MASK_LPF_R3_4_0 0x1f +#define BIT_LPF_R3_4_0(x) (((x) & BIT_MASK_LPF_R3_4_0) << BIT_SHIFT_LPF_R3_4_0) +#define BITS_LPF_R3_4_0 (BIT_MASK_LPF_R3_4_0 << BIT_SHIFT_LPF_R3_4_0) +#define BIT_CLEAR_LPF_R3_4_0(x) ((x) & (~BITS_LPF_R3_4_0)) +#define BIT_GET_LPF_R3_4_0(x) \ + (((x) >> BIT_SHIFT_LPF_R3_4_0) & BIT_MASK_LPF_R3_4_0) +#define BIT_SET_LPF_R3_4_0(x, v) (BIT_CLEAR_LPF_R3_4_0(x) | BIT_LPF_R3_4_0(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ -#define BIT_PORT3_TRIPKT_OK_INT BIT(25) +#define BIT_SHIFT_REG_LPF_R2_FAST 11 +#define BIT_MASK_REG_LPF_R2_FAST 0x1f +#define BIT_REG_LPF_R2_FAST(x) \ + (((x) & BIT_MASK_REG_LPF_R2_FAST) << BIT_SHIFT_REG_LPF_R2_FAST) +#define BITS_REG_LPF_R2_FAST \ + (BIT_MASK_REG_LPF_R2_FAST << BIT_SHIFT_REG_LPF_R2_FAST) +#define BIT_CLEAR_REG_LPF_R2_FAST(x) ((x) & (~BITS_REG_LPF_R2_FAST)) +#define BIT_GET_REG_LPF_R2_FAST(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R2_FAST) & BIT_MASK_REG_LPF_R2_FAST) +#define BIT_SET_REG_LPF_R2_FAST(x, v) \ + (BIT_CLEAR_REG_LPF_R2_FAST(x) | BIT_REG_LPF_R2_FAST(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_LPF_R2_4_0 10 +#define BIT_MASK_LPF_R2_4_0 0x1f +#define BIT_LPF_R2_4_0(x) (((x) & BIT_MASK_LPF_R2_4_0) << BIT_SHIFT_LPF_R2_4_0) +#define BITS_LPF_R2_4_0 (BIT_MASK_LPF_R2_4_0 << BIT_SHIFT_LPF_R2_4_0) +#define BIT_CLEAR_LPF_R2_4_0(x) ((x) & (~BITS_LPF_R2_4_0)) +#define BIT_GET_LPF_R2_4_0(x) \ + (((x) >> BIT_SHIFT_LPF_R2_4_0) & BIT_MASK_LPF_R2_4_0) +#define BIT_SET_LPF_R2_4_0(x, v) (BIT_CLEAR_LPF_R2_4_0(x) | BIT_LPF_R2_4_0(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ + +#define BIT_SHIFT_REG_LPF_C3_FAST 8 +#define BIT_MASK_REG_LPF_C3_FAST 0x7 +#define BIT_REG_LPF_C3_FAST(x) \ + (((x) & BIT_MASK_REG_LPF_C3_FAST) << BIT_SHIFT_REG_LPF_C3_FAST) +#define BITS_REG_LPF_C3_FAST \ + (BIT_MASK_REG_LPF_C3_FAST << BIT_SHIFT_REG_LPF_C3_FAST) +#define BIT_CLEAR_REG_LPF_C3_FAST(x) ((x) & (~BITS_REG_LPF_C3_FAST)) +#define BIT_GET_REG_LPF_C3_FAST(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C3_FAST) & BIT_MASK_REG_LPF_C3_FAST) +#define BIT_SET_REG_LPF_C3_FAST(x, v) \ + (BIT_CLEAR_REG_LPF_C3_FAST(x) | BIT_REG_LPF_C3_FAST(v)) + +#define BIT_SHIFT_REG_LPF_C2_FAST 5 +#define BIT_MASK_REG_LPF_C2_FAST 0x7 +#define BIT_REG_LPF_C2_FAST(x) \ + (((x) & BIT_MASK_REG_LPF_C2_FAST) << BIT_SHIFT_REG_LPF_C2_FAST) +#define BITS_REG_LPF_C2_FAST \ + (BIT_MASK_REG_LPF_C2_FAST << BIT_SHIFT_REG_LPF_C2_FAST) +#define BIT_CLEAR_REG_LPF_C2_FAST(x) ((x) & (~BITS_REG_LPF_C2_FAST)) +#define BIT_GET_REG_LPF_C2_FAST(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C2_FAST) & BIT_MASK_REG_LPF_C2_FAST) +#define BIT_SET_REG_LPF_C2_FAST(x, v) \ + (BIT_CLEAR_REG_LPF_C2_FAST(x) | BIT_REG_LPF_C2_FAST(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_LPF_C3_5_0 4 +#define BIT_MASK_LPF_C3_5_0 0x3f +#define BIT_LPF_C3_5_0(x) (((x) & BIT_MASK_LPF_C3_5_0) << BIT_SHIFT_LPF_C3_5_0) +#define BITS_LPF_C3_5_0 (BIT_MASK_LPF_C3_5_0 << BIT_SHIFT_LPF_C3_5_0) +#define BIT_CLEAR_LPF_C3_5_0(x) ((x) & (~BITS_LPF_C3_5_0)) +#define BIT_GET_LPF_C3_5_0(x) \ + (((x) >> BIT_SHIFT_LPF_C3_5_0) & BIT_MASK_LPF_C3_5_0) +#define BIT_SET_LPF_C3_5_0(x, v) (BIT_CLEAR_LPF_C3_5_0(x) | BIT_LPF_C3_5_0(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ + +#define BIT_SHIFT_REG_LPF_C1_FAST 2 +#define BIT_MASK_REG_LPF_C1_FAST 0x7 +#define BIT_REG_LPF_C1_FAST(x) \ + (((x) & BIT_MASK_REG_LPF_C1_FAST) << BIT_SHIFT_REG_LPF_C1_FAST) +#define BITS_REG_LPF_C1_FAST \ + (BIT_MASK_REG_LPF_C1_FAST << BIT_SHIFT_REG_LPF_C1_FAST) +#define BIT_CLEAR_REG_LPF_C1_FAST(x) ((x) & (~BITS_REG_LPF_C1_FAST)) +#define BIT_GET_REG_LPF_C1_FAST(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C1_FAST) & BIT_MASK_REG_LPF_C1_FAST) +#define BIT_SET_REG_LPF_C1_FAST(x, v) \ + (BIT_CLEAR_REG_LPF_C1_FAST(x) | BIT_REG_LPF_C1_FAST(v)) -#define BIT_PORT3_RX_EOSP_OK_INT BIT(24) +#define BIT_SHIFT_REG_LPF_R3_V1 0 +#define BIT_MASK_REG_LPF_R3_V1 0x3 +#define BIT_REG_LPF_R3_V1(x) \ + (((x) & BIT_MASK_REG_LPF_R3_V1) << BIT_SHIFT_REG_LPF_R3_V1) +#define BITS_REG_LPF_R3_V1 (BIT_MASK_REG_LPF_R3_V1 << BIT_SHIFT_REG_LPF_R3_V1) +#define BIT_CLEAR_REG_LPF_R3_V1(x) ((x) & (~BITS_REG_LPF_R3_V1)) +#define BIT_GET_REG_LPF_R3_V1(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3_V1) & BIT_MASK_REG_LPF_R3_V1) +#define BIT_SET_REG_LPF_R3_V1(x, v) \ + (BIT_CLEAR_REG_LPF_R3_V1(x) | BIT_REG_LPF_R3_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */ +#define BIT_SHIFT_LPF_C2_5_2 0 +#define BIT_MASK_LPF_C2_5_2 0xf +#define BIT_LPF_C2_5_2(x) (((x) & BIT_MASK_LPF_C2_5_2) << BIT_SHIFT_LPF_C2_5_2) +#define BITS_LPF_C2_5_2 (BIT_MASK_LPF_C2_5_2 << BIT_SHIFT_LPF_C2_5_2) +#define BIT_CLEAR_LPF_C2_5_2(x) ((x) & (~BITS_LPF_C2_5_2)) +#define BIT_GET_LPF_C2_5_2(x) \ + (((x) >> BIT_SHIFT_LPF_C2_5_2) & BIT_MASK_LPF_C2_5_2) +#define BIT_SET_LPF_C2_5_2(x, v) (BIT_CLEAR_LPF_C2_5_2(x) | BIT_LPF_C2_5_2(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ -#define BIT_FS_CLI2_EOSP_INT BIT(24) +#define BIT_CK_PHASE_SEL BIT(31) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_SHIFT_AGPIO_DRV_V1 30 +#define BIT_MASK_AGPIO_DRV_V1 0x3 +#define BIT_AGPIO_DRV_V1(x) \ + (((x) & BIT_MASK_AGPIO_DRV_V1) << BIT_SHIFT_AGPIO_DRV_V1) +#define BITS_AGPIO_DRV_V1 (BIT_MASK_AGPIO_DRV_V1 << BIT_SHIFT_AGPIO_DRV_V1) +#define BIT_CLEAR_AGPIO_DRV_V1(x) ((x) & (~BITS_AGPIO_DRV_V1)) +#define BIT_GET_AGPIO_DRV_V1(x) \ + (((x) >> BIT_SHIFT_AGPIO_DRV_V1) & BIT_MASK_AGPIO_DRV_V1) +#define BIT_SET_AGPIO_DRV_V1(x, v) \ + (BIT_CLEAR_AGPIO_DRV_V1(x) | BIT_AGPIO_DRV_V1(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT BIT(23) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_CK960M_EN BIT(30) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_AGPIO_GPO_V1 BIT(29) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ -#define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23) +#define BIT_CK640M_EN BIT(29) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_AGPIO_GPE_V1 BIT(28) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT BIT(22) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_CK240M_EN BIT(28) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_SEL_CLK BIT(27) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22) +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_SHIFT_CK_MON_SEL_2_0 25 +#define BIT_MASK_CK_MON_SEL_2_0 0x7 +#define BIT_CK_MON_SEL_2_0(x) \ + (((x) & BIT_MASK_CK_MON_SEL_2_0) << BIT_SHIFT_CK_MON_SEL_2_0) +#define BITS_CK_MON_SEL_2_0 \ + (BIT_MASK_CK_MON_SEL_2_0 << BIT_SHIFT_CK_MON_SEL_2_0) +#define BIT_CLEAR_CK_MON_SEL_2_0(x) ((x) & (~BITS_CK_MON_SEL_2_0)) +#define BIT_GET_CK_MON_SEL_2_0(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_2_0) & BIT_MASK_CK_MON_SEL_2_0) +#define BIT_SET_CK_MON_SEL_2_0(x, v) \ + (BIT_CLEAR_CK_MON_SEL_2_0(x) | BIT_CK_MON_SEL_2_0(v)) + +#define BIT_CK_MON_EN_V1 BIT(24) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_SHIFT_LS_XTAL_SEL 23 +#define BIT_MASK_LS_XTAL_SEL 0xf +#define BIT_LS_XTAL_SEL(x) \ + (((x) & BIT_MASK_LS_XTAL_SEL) << BIT_SHIFT_LS_XTAL_SEL) +#define BITS_LS_XTAL_SEL (BIT_MASK_LS_XTAL_SEL << BIT_SHIFT_LS_XTAL_SEL) +#define BIT_CLEAR_LS_XTAL_SEL(x) ((x) & (~BITS_LS_XTAL_SEL)) +#define BIT_GET_LS_XTAL_SEL(x) \ + (((x) >> BIT_SHIFT_LS_XTAL_SEL) & BIT_MASK_LS_XTAL_SEL) +#define BIT_SET_LS_XTAL_SEL(x, v) \ + (BIT_CLEAR_LS_XTAL_SEL(x) | BIT_LS_XTAL_SEL(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ -#define BIT_PORT2_TRIPKT_OK_INT BIT(21) +#define BIT_XTAL_SOURCE_SEL BIT(23) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_LS_SDM_ORDER_V1 BIT(22) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_XTAL_FREQ_SEL BIT(22) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_LS_DELAY_PH BIT(21) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT2_RX_EOSP_OK_INT BIT(20) +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_XTAL_EDGE_SEL BIT(21) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_DIVIDER_SEL BIT(20) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_FS_CLI1_EOSP_INT BIT(20) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_XTAL_BUF_SEL BIT(20) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_SHIFT_PCODE 15 +#define BIT_MASK_PCODE 0x1f +#define BIT_PCODE(x) (((x) & BIT_MASK_PCODE) << BIT_SHIFT_PCODE) +#define BITS_PCODE (BIT_MASK_PCODE << BIT_SHIFT_PCODE) +#define BIT_CLEAR_PCODE(x) ((x) & (~BITS_PCODE)) +#define BIT_GET_PCODE(x) (((x) >> BIT_SHIFT_PCODE) & BIT_MASK_PCODE) +#define BIT_SET_PCODE(x, v) (BIT_CLEAR_PCODE(x) | BIT_PCODE(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_SHIFT_NCODE 7 +#define BIT_MASK_NCODE 0xff +#define BIT_NCODE(x) (((x) & BIT_MASK_NCODE) << BIT_SHIFT_NCODE) +#define BITS_NCODE (BIT_MASK_NCODE << BIT_SHIFT_NCODE) +#define BIT_CLEAR_NCODE(x) ((x) & (~BITS_NCODE)) +#define BIT_GET_NCODE(x) (((x) >> BIT_SHIFT_NCODE) & BIT_MASK_NCODE) +#define BIT_SET_NCODE(x, v) (BIT_CLEAR_NCODE(x) | BIT_NCODE(v)) -#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT BIT(19) +#define BIT_REG_BEACON BIT(6) +#define BIT_REG_MBIASE BIT(5) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_SHIFT_VCO_CV_7_0 4 +#define BIT_MASK_VCO_CV_7_0 0xff +#define BIT_VCO_CV_7_0(x) (((x) & BIT_MASK_VCO_CV_7_0) << BIT_SHIFT_VCO_CV_7_0) +#define BITS_VCO_CV_7_0 (BIT_MASK_VCO_CV_7_0 << BIT_SHIFT_VCO_CV_7_0) +#define BIT_CLEAR_VCO_CV_7_0(x) ((x) & (~BITS_VCO_CV_7_0)) +#define BIT_GET_VCO_CV_7_0(x) \ + (((x) >> BIT_SHIFT_VCO_CV_7_0) & BIT_MASK_VCO_CV_7_0) +#define BIT_SET_VCO_CV_7_0(x, v) (BIT_CLEAR_VCO_CV_7_0(x) | BIT_VCO_CV_7_0(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_SHIFT_REG_FAST_SEL 3 +#define BIT_MASK_REG_FAST_SEL 0x3 +#define BIT_REG_FAST_SEL(x) \ + (((x) & BIT_MASK_REG_FAST_SEL) << BIT_SHIFT_REG_FAST_SEL) +#define BITS_REG_FAST_SEL (BIT_MASK_REG_FAST_SEL << BIT_SHIFT_REG_FAST_SEL) +#define BIT_CLEAR_REG_FAST_SEL(x) ((x) & (~BITS_REG_FAST_SEL)) +#define BIT_GET_REG_FAST_SEL(x) \ + (((x) >> BIT_SHIFT_REG_FAST_SEL) & BIT_MASK_REG_FAST_SEL) +#define BIT_SET_REG_FAST_SEL(x, v) \ + (BIT_CLEAR_REG_FAST_SEL(x) | BIT_REG_FAST_SEL(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ +#define BIT_VCO_KVCO BIT(3) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_REG_CK960M_EN BIT(2) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_SDM_EDGE_SEL BIT(2) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_REG_CK320M_EN BIT(1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_SDM_CK_SEL BIT(1) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_REG_CK_5M_EN BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */ + +#define BIT_SDM_CK_GATED BIT(0) + +/* 2 REG_ANAPAR_MAC_3 (Offset 0x1024) */ + +#define BIT_SHIFT_LCK_WAIT_CYCLE_2_0 28 +#define BIT_MASK_LCK_WAIT_CYCLE_2_0 0x7 +#define BIT_LCK_WAIT_CYCLE_2_0(x) \ + (((x) & BIT_MASK_LCK_WAIT_CYCLE_2_0) << BIT_SHIFT_LCK_WAIT_CYCLE_2_0) +#define BITS_LCK_WAIT_CYCLE_2_0 \ + (BIT_MASK_LCK_WAIT_CYCLE_2_0 << BIT_SHIFT_LCK_WAIT_CYCLE_2_0) +#define BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) ((x) & (~BITS_LCK_WAIT_CYCLE_2_0)) +#define BIT_GET_LCK_WAIT_CYCLE_2_0(x) \ + (((x) >> BIT_SHIFT_LCK_WAIT_CYCLE_2_0) & BIT_MASK_LCK_WAIT_CYCLE_2_0) +#define BIT_SET_LCK_WAIT_CYCLE_2_0(x, v) \ + (BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) | BIT_LCK_WAIT_CYCLE_2_0(v)) + +#define BIT_SHIFT_LCK_VCO_DIVISOR_1_0 26 +#define BIT_MASK_LCK_VCO_DIVISOR_1_0 0x3 +#define BIT_LCK_VCO_DIVISOR_1_0(x) \ + (((x) & BIT_MASK_LCK_VCO_DIVISOR_1_0) << BIT_SHIFT_LCK_VCO_DIVISOR_1_0) +#define BITS_LCK_VCO_DIVISOR_1_0 \ + (BIT_MASK_LCK_VCO_DIVISOR_1_0 << BIT_SHIFT_LCK_VCO_DIVISOR_1_0) +#define BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) ((x) & (~BITS_LCK_VCO_DIVISOR_1_0)) +#define BIT_GET_LCK_VCO_DIVISOR_1_0(x) \ + (((x) >> BIT_SHIFT_LCK_VCO_DIVISOR_1_0) & BIT_MASK_LCK_VCO_DIVISOR_1_0) +#define BIT_SET_LCK_VCO_DIVISOR_1_0(x, v) \ + (BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) | BIT_LCK_VCO_DIVISOR_1_0(v)) + +#define BIT_SHIFT_LCK_SEARCH_MODE_1_0 24 +#define BIT_MASK_LCK_SEARCH_MODE_1_0 0x3 +#define BIT_LCK_SEARCH_MODE_1_0(x) \ + (((x) & BIT_MASK_LCK_SEARCH_MODE_1_0) << BIT_SHIFT_LCK_SEARCH_MODE_1_0) +#define BITS_LCK_SEARCH_MODE_1_0 \ + (BIT_MASK_LCK_SEARCH_MODE_1_0 << BIT_SHIFT_LCK_SEARCH_MODE_1_0) +#define BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) ((x) & (~BITS_LCK_SEARCH_MODE_1_0)) +#define BIT_GET_LCK_SEARCH_MODE_1_0(x) \ + (((x) >> BIT_SHIFT_LCK_SEARCH_MODE_1_0) & BIT_MASK_LCK_SEARCH_MODE_1_0) +#define BIT_SET_LCK_SEARCH_MODE_1_0(x, v) \ + (BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) | BIT_LCK_SEARCH_MODE_1_0(v)) + +#define BIT_SHIFT_LS_CV_OFFSET_3_0 12 +#define BIT_MASK_LS_CV_OFFSET_3_0 0xf +#define BIT_LS_CV_OFFSET_3_0(x) \ + (((x) & BIT_MASK_LS_CV_OFFSET_3_0) << BIT_SHIFT_LS_CV_OFFSET_3_0) +#define BITS_LS_CV_OFFSET_3_0 \ + (BIT_MASK_LS_CV_OFFSET_3_0 << BIT_SHIFT_LS_CV_OFFSET_3_0) +#define BIT_CLEAR_LS_CV_OFFSET_3_0(x) ((x) & (~BITS_LS_CV_OFFSET_3_0)) +#define BIT_GET_LS_CV_OFFSET_3_0(x) \ + (((x) >> BIT_SHIFT_LS_CV_OFFSET_3_0) & BIT_MASK_LS_CV_OFFSET_3_0) +#define BIT_SET_LS_CV_OFFSET_3_0(x, v) \ + (BIT_CLEAR_LS_CV_OFFSET_3_0(x) | BIT_LS_CV_OFFSET_3_0(v)) + +#define BIT_LS_EN_LC_CK40M BIT(11) +#define BIT_LS__CV_MANUAL BIT(10) +#define BIT_LS_PYPASS_PI BIT(9) +#define BIT_MBIASE BIT(4) + +/* 2 REG_ANAPAR_MAC_4 (Offset 0x1028) */ + +#define BIT_LS_TIE_MID_MODE BIT(28) + +#define BIT_SHIFT_LS_SYNC_CYCLE_1_0 26 +#define BIT_MASK_LS_SYNC_CYCLE_1_0 0x3 +#define BIT_LS_SYNC_CYCLE_1_0(x) \ + (((x) & BIT_MASK_LS_SYNC_CYCLE_1_0) << BIT_SHIFT_LS_SYNC_CYCLE_1_0) +#define BITS_LS_SYNC_CYCLE_1_0 \ + (BIT_MASK_LS_SYNC_CYCLE_1_0 << BIT_SHIFT_LS_SYNC_CYCLE_1_0) +#define BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) ((x) & (~BITS_LS_SYNC_CYCLE_1_0)) +#define BIT_GET_LS_SYNC_CYCLE_1_0(x) \ + (((x) >> BIT_SHIFT_LS_SYNC_CYCLE_1_0) & BIT_MASK_LS_SYNC_CYCLE_1_0) +#define BIT_SET_LS_SYNC_CYCLE_1_0(x, v) \ + (BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) | BIT_LS_SYNC_CYCLE_1_0(v)) + +#define BIT_LS_SDM_ORDER BIT(25) +#define BIT_LS_RST_LC_CAL BIT(14) +#define BIT_LS_RSTB BIT(13) +#define BIT_LS_POW_LC_CAL_PREP BIT(11) + +#define BIT_SHIFT_LCK_XTAL_DIVISOR_1_0 0 +#define BIT_MASK_LCK_XTAL_DIVISOR_1_0 0x3 +#define BIT_LCK_XTAL_DIVISOR_1_0(x) \ + (((x) & BIT_MASK_LCK_XTAL_DIVISOR_1_0) \ + << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) +#define BITS_LCK_XTAL_DIVISOR_1_0 \ + (BIT_MASK_LCK_XTAL_DIVISOR_1_0 << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) +#define BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) ((x) & (~BITS_LCK_XTAL_DIVISOR_1_0)) +#define BIT_GET_LCK_XTAL_DIVISOR_1_0(x) \ + (((x) >> BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) & \ + BIT_MASK_LCK_XTAL_DIVISOR_1_0) +#define BIT_SET_LCK_XTAL_DIVISOR_1_0(x, v) \ + (BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) | BIT_LCK_XTAL_DIVISOR_1_0(v)) + +/* 2 REG_ANAPAR_MAC_5 (Offset 0x102C) */ + +#define BIT_SHIFT_LS_XTAL_SEL_3_0 0 +#define BIT_MASK_LS_XTAL_SEL_3_0 0xf +#define BIT_LS_XTAL_SEL_3_0(x) \ + (((x) & BIT_MASK_LS_XTAL_SEL_3_0) << BIT_SHIFT_LS_XTAL_SEL_3_0) +#define BITS_LS_XTAL_SEL_3_0 \ + (BIT_MASK_LS_XTAL_SEL_3_0 << BIT_SHIFT_LS_XTAL_SEL_3_0) +#define BIT_CLEAR_LS_XTAL_SEL_3_0(x) ((x) & (~BITS_LS_XTAL_SEL_3_0)) +#define BIT_GET_LS_XTAL_SEL_3_0(x) \ + (((x) >> BIT_SHIFT_LS_XTAL_SEL_3_0) & BIT_MASK_LS_XTAL_SEL_3_0) +#define BIT_SET_LS_XTAL_SEL_3_0(x, v) \ + (BIT_CLEAR_LS_XTAL_SEL_3_0(x) | BIT_LS_XTAL_SEL_3_0(v)) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SYS_CFG4 (Offset 0x1034) */ + +#define BIT_EF_CSER_1 BIT(26) +#define BIT_SW_PG_EN_1 BIT(10) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_XTAL_SC_LPS BIT(31) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_XTAL_DRV_RF1_0 BIT(31) +#define BIT_XTAL_GATED_RF1N BIT(30) +#define BIT_XTAL_GATED_RF1P BIT(29) +#define BIT_XTAL_GM_SEP_V2 BIT(28) + +#define BIT_SHIFT_XTAL_LDO_1_0 26 +#define BIT_MASK_XTAL_LDO_1_0 0x3 +#define BIT_XTAL_LDO_1_0(x) \ + (((x) & BIT_MASK_XTAL_LDO_1_0) << BIT_SHIFT_XTAL_LDO_1_0) +#define BITS_XTAL_LDO_1_0 (BIT_MASK_XTAL_LDO_1_0 << BIT_SHIFT_XTAL_LDO_1_0) +#define BIT_CLEAR_XTAL_LDO_1_0(x) ((x) & (~BITS_XTAL_LDO_1_0)) +#define BIT_GET_XTAL_LDO_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_1_0) & BIT_MASK_XTAL_LDO_1_0) +#define BIT_SET_XTAL_LDO_1_0(x, v) \ + (BIT_CLEAR_XTAL_LDO_1_0(x) | BIT_XTAL_LDO_1_0(v)) + +#define BIT_XQSEL_V1 BIT(25) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_SHIFT_XTAL_SC_INIT 24 +#define BIT_MASK_XTAL_SC_INIT 0x7f +#define BIT_XTAL_SC_INIT(x) \ + (((x) & BIT_MASK_XTAL_SC_INIT) << BIT_SHIFT_XTAL_SC_INIT) +#define BITS_XTAL_SC_INIT (BIT_MASK_XTAL_SC_INIT << BIT_SHIFT_XTAL_SC_INIT) +#define BIT_CLEAR_XTAL_SC_INIT(x) ((x) & (~BITS_XTAL_SC_INIT)) +#define BIT_GET_XTAL_SC_INIT(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_INIT) & BIT_MASK_XTAL_SC_INIT) +#define BIT_SET_XTAL_SC_INIT(x, v) \ + (BIT_CLEAR_XTAL_SC_INIT(x) | BIT_XTAL_SC_INIT(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_GATED_XTAL_OK0 BIT(24) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_SHIFT_XTAL_SC_XO 17 +#define BIT_MASK_XTAL_SC_XO 0x7f +#define BIT_XTAL_SC_XO(x) (((x) & BIT_MASK_XTAL_SC_XO) << BIT_SHIFT_XTAL_SC_XO) +#define BITS_XTAL_SC_XO (BIT_MASK_XTAL_SC_XO << BIT_SHIFT_XTAL_SC_XO) +#define BIT_CLEAR_XTAL_SC_XO(x) ((x) & (~BITS_XTAL_SC_XO)) +#define BIT_GET_XTAL_SC_XO(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XO) & BIT_MASK_XTAL_SC_XO) +#define BIT_SET_XTAL_SC_XO(x, v) (BIT_CLEAR_XTAL_SC_XO(x) | BIT_XTAL_SC_XO(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_SHIFT_XTAL_SC_XO_6_0 17 +#define BIT_MASK_XTAL_SC_XO_6_0 0x7f +#define BIT_XTAL_SC_XO_6_0(x) \ + (((x) & BIT_MASK_XTAL_SC_XO_6_0) << BIT_SHIFT_XTAL_SC_XO_6_0) +#define BITS_XTAL_SC_XO_6_0 \ + (BIT_MASK_XTAL_SC_XO_6_0 << BIT_SHIFT_XTAL_SC_XO_6_0) +#define BIT_CLEAR_XTAL_SC_XO_6_0(x) ((x) & (~BITS_XTAL_SC_XO_6_0)) +#define BIT_GET_XTAL_SC_XO_6_0(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XO_6_0) & BIT_MASK_XTAL_SC_XO_6_0) +#define BIT_SET_XTAL_SC_XO_6_0(x, v) \ + (BIT_CLEAR_XTAL_SC_XO_6_0(x) | BIT_XTAL_SC_XO_6_0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_SHIFT_XTAL_SC_XI 10 +#define BIT_MASK_XTAL_SC_XI 0x7f +#define BIT_XTAL_SC_XI(x) (((x) & BIT_MASK_XTAL_SC_XI) << BIT_SHIFT_XTAL_SC_XI) +#define BITS_XTAL_SC_XI (BIT_MASK_XTAL_SC_XI << BIT_SHIFT_XTAL_SC_XI) +#define BIT_CLEAR_XTAL_SC_XI(x) ((x) & (~BITS_XTAL_SC_XI)) +#define BIT_GET_XTAL_SC_XI(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XI) & BIT_MASK_XTAL_SC_XI) +#define BIT_SET_XTAL_SC_XI(x, v) (BIT_CLEAR_XTAL_SC_XI(x) | BIT_XTAL_SC_XI(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_SHIFT_XTAL_SC_XI_6_0 10 +#define BIT_MASK_XTAL_SC_XI_6_0 0x7f +#define BIT_XTAL_SC_XI_6_0(x) \ + (((x) & BIT_MASK_XTAL_SC_XI_6_0) << BIT_SHIFT_XTAL_SC_XI_6_0) +#define BITS_XTAL_SC_XI_6_0 \ + (BIT_MASK_XTAL_SC_XI_6_0 << BIT_SHIFT_XTAL_SC_XI_6_0) +#define BIT_CLEAR_XTAL_SC_XI_6_0(x) ((x) & (~BITS_XTAL_SC_XI_6_0)) +#define BIT_GET_XTAL_SC_XI_6_0(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XI_6_0) & BIT_MASK_XTAL_SC_XI_6_0) +#define BIT_SET_XTAL_SC_XI_6_0(x, v) \ + (BIT_CLEAR_XTAL_SC_XI_6_0(x) | BIT_XTAL_SC_XI_6_0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_SHIFT_XTAL_GMN_V3 5 +#define BIT_MASK_XTAL_GMN_V3 0x1f +#define BIT_XTAL_GMN_V3(x) \ + (((x) & BIT_MASK_XTAL_GMN_V3) << BIT_SHIFT_XTAL_GMN_V3) +#define BITS_XTAL_GMN_V3 (BIT_MASK_XTAL_GMN_V3 << BIT_SHIFT_XTAL_GMN_V3) +#define BIT_CLEAR_XTAL_GMN_V3(x) ((x) & (~BITS_XTAL_GMN_V3)) +#define BIT_GET_XTAL_GMN_V3(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V3) & BIT_MASK_XTAL_GMN_V3) +#define BIT_SET_XTAL_GMN_V3(x, v) \ + (BIT_CLEAR_XTAL_GMN_V3(x) | BIT_XTAL_GMN_V3(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_SHIFT_XTAL_GMN_4_0 5 +#define BIT_MASK_XTAL_GMN_4_0 0x1f +#define BIT_XTAL_GMN_4_0(x) \ + (((x) & BIT_MASK_XTAL_GMN_4_0) << BIT_SHIFT_XTAL_GMN_4_0) +#define BITS_XTAL_GMN_4_0 (BIT_MASK_XTAL_GMN_4_0 << BIT_SHIFT_XTAL_GMN_4_0) +#define BIT_CLEAR_XTAL_GMN_4_0(x) ((x) & (~BITS_XTAL_GMN_4_0)) +#define BIT_GET_XTAL_GMN_4_0(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_4_0) & BIT_MASK_XTAL_GMN_4_0) +#define BIT_SET_XTAL_GMN_4_0(x, v) \ + (BIT_CLEAR_XTAL_GMN_4_0(x) | BIT_XTAL_GMN_4_0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_SHIFT_XTAL_GMP_V3 0 +#define BIT_MASK_XTAL_GMP_V3 0x1f +#define BIT_XTAL_GMP_V3(x) \ + (((x) & BIT_MASK_XTAL_GMP_V3) << BIT_SHIFT_XTAL_GMP_V3) +#define BITS_XTAL_GMP_V3 (BIT_MASK_XTAL_GMP_V3 << BIT_SHIFT_XTAL_GMP_V3) +#define BIT_CLEAR_XTAL_GMP_V3(x) ((x) & (~BITS_XTAL_GMP_V3)) +#define BIT_GET_XTAL_GMP_V3(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V3) & BIT_MASK_XTAL_GMP_V3) +#define BIT_SET_XTAL_GMP_V3(x, v) \ + (BIT_CLEAR_XTAL_GMP_V3(x) | BIT_XTAL_GMP_V3(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */ + +#define BIT_SHIFT_XTAL_GMP_4_0 0 +#define BIT_MASK_XTAL_GMP_4_0 0x1f +#define BIT_XTAL_GMP_4_0(x) \ + (((x) & BIT_MASK_XTAL_GMP_4_0) << BIT_SHIFT_XTAL_GMP_4_0) +#define BITS_XTAL_GMP_4_0 (BIT_MASK_XTAL_GMP_4_0 << BIT_SHIFT_XTAL_GMP_4_0) +#define BIT_CLEAR_XTAL_GMP_4_0(x) ((x) & (~BITS_XTAL_GMP_4_0)) +#define BIT_GET_XTAL_GMP_4_0(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_4_0) & BIT_MASK_XTAL_GMP_4_0) +#define BIT_SET_XTAL_GMP_4_0(x, v) \ + (BIT_CLEAR_XTAL_GMP_4_0(x) | BIT_XTAL_GMP_4_0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XTAL_SEL_TOK_V1 BIT(31) +#define BIT_XTAL_DELAY_DIGI_V2 BIT(30) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_SHIFT_XTAL_LDO_OK_1_0 30 +#define BIT_MASK_XTAL_LDO_OK_1_0 0x3 +#define BIT_XTAL_LDO_OK_1_0(x) \ + (((x) & BIT_MASK_XTAL_LDO_OK_1_0) << BIT_SHIFT_XTAL_LDO_OK_1_0) +#define BITS_XTAL_LDO_OK_1_0 \ + (BIT_MASK_XTAL_LDO_OK_1_0 << BIT_SHIFT_XTAL_LDO_OK_1_0) +#define BIT_CLEAR_XTAL_LDO_OK_1_0(x) ((x) & (~BITS_XTAL_LDO_OK_1_0)) +#define BIT_GET_XTAL_LDO_OK_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_OK_1_0) & BIT_MASK_XTAL_LDO_OK_1_0) +#define BIT_SET_XTAL_LDO_OK_1_0(x, v) \ + (BIT_CLEAR_XTAL_LDO_OK_1_0(x) | BIT_XTAL_LDO_OK_1_0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XTAL_DELAY_USB_V2 BIT(29) +#define BIT_XTAL_DELAY_AFE_V2 BIT(28) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_SHIFT_XTAL_XORES_SEL_2_0 27 +#define BIT_MASK_XTAL_XORES_SEL_2_0 0x7 +#define BIT_XTAL_XORES_SEL_2_0(x) \ + (((x) & BIT_MASK_XTAL_XORES_SEL_2_0) << BIT_SHIFT_XTAL_XORES_SEL_2_0) +#define BITS_XTAL_XORES_SEL_2_0 \ + (BIT_MASK_XTAL_XORES_SEL_2_0 << BIT_SHIFT_XTAL_XORES_SEL_2_0) +#define BIT_CLEAR_XTAL_XORES_SEL_2_0(x) ((x) & (~BITS_XTAL_XORES_SEL_2_0)) +#define BIT_GET_XTAL_XORES_SEL_2_0(x) \ + (((x) >> BIT_SHIFT_XTAL_XORES_SEL_2_0) & BIT_MASK_XTAL_XORES_SEL_2_0) +#define BIT_SET_XTAL_XORES_SEL_2_0(x, v) \ + (BIT_CLEAR_XTAL_XORES_SEL_2_0(x) | BIT_XTAL_XORES_SEL_2_0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_SHIFT_XTAL_DRV_DIGI_V2 26 +#define BIT_MASK_XTAL_DRV_DIGI_V2 0x3 +#define BIT_XTAL_DRV_DIGI_V2(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_V2) << BIT_SHIFT_XTAL_DRV_DIGI_V2) +#define BITS_XTAL_DRV_DIGI_V2 \ + (BIT_MASK_XTAL_DRV_DIGI_V2 << BIT_SHIFT_XTAL_DRV_DIGI_V2) +#define BIT_CLEAR_XTAL_DRV_DIGI_V2(x) ((x) & (~BITS_XTAL_DRV_DIGI_V2)) +#define BIT_GET_XTAL_DRV_DIGI_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_V2) & BIT_MASK_XTAL_DRV_DIGI_V2) +#define BIT_SET_XTAL_DRV_DIGI_V2(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_V2(x) | BIT_XTAL_DRV_DIGI_V2(v)) + +#define BIT_EN_XTAL_DRV_LPS BIT(25) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_SHIFT_XTAL_AAC_PK_SEL_1_0 25 +#define BIT_MASK_XTAL_AAC_PK_SEL_1_0 0x3 +#define BIT_XTAL_AAC_PK_SEL_1_0(x) \ + (((x) & BIT_MASK_XTAL_AAC_PK_SEL_1_0) << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) +#define BITS_XTAL_AAC_PK_SEL_1_0 \ + (BIT_MASK_XTAL_AAC_PK_SEL_1_0 << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) +#define BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) ((x) & (~BITS_XTAL_AAC_PK_SEL_1_0)) +#define BIT_GET_XTAL_AAC_PK_SEL_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) & BIT_MASK_XTAL_AAC_PK_SEL_1_0) +#define BIT_SET_XTAL_AAC_PK_SEL_1_0(x, v) \ + (BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) | BIT_XTAL_AAC_PK_SEL_1_0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_EN_XTAL_DRV_DIGI_V2 BIT(24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_EN_XTAL_AAC_PKDET BIT(24) +#define BIT_EN_XTAL_AAC_GM BIT(23) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_SHIFT_XTAL_DRV_USB 22 +#define BIT_MASK_XTAL_DRV_USB 0x3 +#define BIT_XTAL_DRV_USB(x) \ + (((x) & BIT_MASK_XTAL_DRV_USB) << BIT_SHIFT_XTAL_DRV_USB) +#define BITS_XTAL_DRV_USB (BIT_MASK_XTAL_DRV_USB << BIT_SHIFT_XTAL_DRV_USB) +#define BIT_CLEAR_XTAL_DRV_USB(x) ((x) & (~BITS_XTAL_DRV_USB)) +#define BIT_GET_XTAL_DRV_USB(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_USB) & BIT_MASK_XTAL_DRV_USB) +#define BIT_SET_XTAL_DRV_USB(x, v) \ + (BIT_CLEAR_XTAL_DRV_USB(x) | BIT_XTAL_DRV_USB(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XTAL_LPMODE BIT(22) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_EN_XTAL_DRV_USB BIT(21) + +#define BIT_SHIFT_XTAL_DRV_AFE_V2 19 +#define BIT_MASK_XTAL_DRV_AFE_V2 0x3 +#define BIT_XTAL_DRV_AFE_V2(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_V2) << BIT_SHIFT_XTAL_DRV_AFE_V2) +#define BITS_XTAL_DRV_AFE_V2 \ + (BIT_MASK_XTAL_DRV_AFE_V2 << BIT_SHIFT_XTAL_DRV_AFE_V2) +#define BIT_CLEAR_XTAL_DRV_AFE_V2(x) ((x) & (~BITS_XTAL_DRV_AFE_V2)) +#define BIT_GET_XTAL_DRV_AFE_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_V2) & BIT_MASK_XTAL_DRV_AFE_V2) +#define BIT_SET_XTAL_DRV_AFE_V2(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_V2(x) | BIT_XTAL_DRV_AFE_V2(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_SHIFT_XTAL_SEL_TOK_2_0 19 +#define BIT_MASK_XTAL_SEL_TOK_2_0 0x7 +#define BIT_XTAL_SEL_TOK_2_0(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_2_0) << BIT_SHIFT_XTAL_SEL_TOK_2_0) +#define BITS_XTAL_SEL_TOK_2_0 \ + (BIT_MASK_XTAL_SEL_TOK_2_0 << BIT_SHIFT_XTAL_SEL_TOK_2_0) +#define BIT_CLEAR_XTAL_SEL_TOK_2_0(x) ((x) & (~BITS_XTAL_SEL_TOK_2_0)) +#define BIT_GET_XTAL_SEL_TOK_2_0(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_2_0) & BIT_MASK_XTAL_SEL_TOK_2_0) +#define BIT_SET_XTAL_SEL_TOK_2_0(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_2_0(x) | BIT_XTAL_SEL_TOK_2_0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_EN_XTAL_DRV_AFE BIT(18) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XQSEL_RF_AWAKE_V2 BIT(18) +#define BIT_XQSEL_RF_INITIAL_V2 BIT(17) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_SHIFT_XTAL_DRV_RF2_V2 16 +#define BIT_MASK_XTAL_DRV_RF2_V2 0x3 +#define BIT_XTAL_DRV_RF2_V2(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_V2) << BIT_SHIFT_XTAL_DRV_RF2_V2) +#define BITS_XTAL_DRV_RF2_V2 \ + (BIT_MASK_XTAL_DRV_RF2_V2 << BIT_SHIFT_XTAL_DRV_RF2_V2) +#define BIT_CLEAR_XTAL_DRV_RF2_V2(x) ((x) & (~BITS_XTAL_DRV_RF2_V2)) +#define BIT_GET_XTAL_DRV_RF2_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_V2) & BIT_MASK_XTAL_DRV_RF2_V2) +#define BIT_SET_XTAL_DRV_RF2_V2(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_V2(x) | BIT_XTAL_DRV_RF2_V2(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XTAL_DELAY_USB_V1 BIT(16) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_EN_XTAL_DRV_RF2 BIT(15) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XTAL_DELAY_DIGI_V1 BIT(15) +#define BIT_XTAL_DELAY_AFE_V1 BIT(14) +#define BIT_XTAL_DRV_RF_LATCH_V3 BIT(13) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_EN_XTAL_DRV_RF1 BIT(12) +#define BIT_XTAL_DRV_RF_LATCH_V4 BIT(11) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_SHIFT_XTAL_DRV_DIGI_1_0 11 +#define BIT_MASK_XTAL_DRV_DIGI_1_0 0x3 +#define BIT_XTAL_DRV_DIGI_1_0(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_1_0) << BIT_SHIFT_XTAL_DRV_DIGI_1_0) +#define BITS_XTAL_DRV_DIGI_1_0 \ + (BIT_MASK_XTAL_DRV_DIGI_1_0 << BIT_SHIFT_XTAL_DRV_DIGI_1_0) +#define BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) ((x) & (~BITS_XTAL_DRV_DIGI_1_0)) +#define BIT_GET_XTAL_DRV_DIGI_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_1_0) & BIT_MASK_XTAL_DRV_DIGI_1_0) +#define BIT_SET_XTAL_DRV_DIGI_1_0(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) | BIT_XTAL_DRV_DIGI_1_0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XTAL_GM_SEP_V3 BIT(10) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XTAL_GATED_DIGIN BIT(10) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XQSEL_RF_AWAKE_V3 BIT(9) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XTAL_GATED_DIGIP BIT(9) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XQSEL_RF_INITIAL_V3 BIT(8) +#define BIT_XQSEL_V2 BIT(7) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_SHIFT_XTAL_DRV_USB_1_0 7 +#define BIT_MASK_XTAL_DRV_USB_1_0 0x3 +#define BIT_XTAL_DRV_USB_1_0(x) \ + (((x) & BIT_MASK_XTAL_DRV_USB_1_0) << BIT_SHIFT_XTAL_DRV_USB_1_0) +#define BITS_XTAL_DRV_USB_1_0 \ + (BIT_MASK_XTAL_DRV_USB_1_0 << BIT_SHIFT_XTAL_DRV_USB_1_0) +#define BIT_CLEAR_XTAL_DRV_USB_1_0(x) ((x) & (~BITS_XTAL_DRV_USB_1_0)) +#define BIT_GET_XTAL_DRV_USB_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_USB_1_0) & BIT_MASK_XTAL_DRV_USB_1_0) +#define BIT_SET_XTAL_DRV_USB_1_0(x, v) \ + (BIT_CLEAR_XTAL_DRV_USB_1_0(x) | BIT_XTAL_DRV_USB_1_0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_GATED_XTAL_OK0_V2 BIT(6) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XTAL_GATED_USBN BIT(6) +#define BIT_XTAL_GATED_USBP BIT(5) + +#define BIT_SHIFT_XTAL_DRV_AFE_1_0 3 +#define BIT_MASK_XTAL_DRV_AFE_1_0 0x3 +#define BIT_XTAL_DRV_AFE_1_0(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_1_0) << BIT_SHIFT_XTAL_DRV_AFE_1_0) +#define BITS_XTAL_DRV_AFE_1_0 \ + (BIT_MASK_XTAL_DRV_AFE_1_0 << BIT_SHIFT_XTAL_DRV_AFE_1_0) +#define BIT_CLEAR_XTAL_DRV_AFE_1_0(x) ((x) & (~BITS_XTAL_DRV_AFE_1_0)) +#define BIT_GET_XTAL_DRV_AFE_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_1_0) & BIT_MASK_XTAL_DRV_AFE_1_0) +#define BIT_SET_XTAL_DRV_AFE_1_0(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_1_0(x) | BIT_XTAL_DRV_AFE_1_0(v)) + +#define BIT_XTAL_GATED_AFEN BIT(2) +#define BIT_XTAL_GATED_AFEP BIT(1) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_SHIFT_XTAL_SC_LPS_V2 0 +#define BIT_MASK_XTAL_SC_LPS_V2 0x3f +#define BIT_XTAL_SC_LPS_V2(x) \ + (((x) & BIT_MASK_XTAL_SC_LPS_V2) << BIT_SHIFT_XTAL_SC_LPS_V2) +#define BITS_XTAL_SC_LPS_V2 \ + (BIT_MASK_XTAL_SC_LPS_V2 << BIT_SHIFT_XTAL_SC_LPS_V2) +#define BIT_CLEAR_XTAL_SC_LPS_V2(x) ((x) & (~BITS_XTAL_SC_LPS_V2)) +#define BIT_GET_XTAL_SC_LPS_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_LPS_V2) & BIT_MASK_XTAL_SC_LPS_V2) +#define BIT_SET_XTAL_SC_LPS_V2(x, v) \ + (BIT_CLEAR_XTAL_SC_LPS_V2(x) | BIT_XTAL_SC_LPS_V2(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */ + +#define BIT_XTAL_DRV_RF1_1 BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_XTAL_AAC_CAP BIT(31) + +#define BIT_SHIFT_XTAL_PDSW 29 +#define BIT_MASK_XTAL_PDSW 0x3 +#define BIT_XTAL_PDSW(x) (((x) & BIT_MASK_XTAL_PDSW) << BIT_SHIFT_XTAL_PDSW) +#define BITS_XTAL_PDSW (BIT_MASK_XTAL_PDSW << BIT_SHIFT_XTAL_PDSW) +#define BIT_CLEAR_XTAL_PDSW(x) ((x) & (~BITS_XTAL_PDSW)) +#define BIT_GET_XTAL_PDSW(x) (((x) >> BIT_SHIFT_XTAL_PDSW) & BIT_MASK_XTAL_PDSW) +#define BIT_SET_XTAL_PDSW(x, v) (BIT_CLEAR_XTAL_PDSW(x) | BIT_XTAL_PDSW(v)) + +#define BIT_SHIFT_XTAL_LPS_BUF_VB 27 +#define BIT_MASK_XTAL_LPS_BUF_VB 0x3 +#define BIT_XTAL_LPS_BUF_VB(x) \ + (((x) & BIT_MASK_XTAL_LPS_BUF_VB) << BIT_SHIFT_XTAL_LPS_BUF_VB) +#define BITS_XTAL_LPS_BUF_VB \ + (BIT_MASK_XTAL_LPS_BUF_VB << BIT_SHIFT_XTAL_LPS_BUF_VB) +#define BIT_CLEAR_XTAL_LPS_BUF_VB(x) ((x) & (~BITS_XTAL_LPS_BUF_VB)) +#define BIT_GET_XTAL_LPS_BUF_VB(x) \ + (((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB) & BIT_MASK_XTAL_LPS_BUF_VB) +#define BIT_SET_XTAL_LPS_BUF_VB(x, v) \ + (BIT_CLEAR_XTAL_LPS_BUF_VB(x) | BIT_XTAL_LPS_BUF_VB(v)) + +#define BIT_XTAL_PDCK_MANU BIT(26) +#define BIT_XTAL_PDCK_OK_MANU BIT(25) + +#define BIT_SHIFT_XTAL_VREF_SEL 20 +#define BIT_MASK_XTAL_VREF_SEL 0x1f +#define BIT_XTAL_VREF_SEL(x) \ + (((x) & BIT_MASK_XTAL_VREF_SEL) << BIT_SHIFT_XTAL_VREF_SEL) +#define BITS_XTAL_VREF_SEL (BIT_MASK_XTAL_VREF_SEL << BIT_SHIFT_XTAL_VREF_SEL) +#define BIT_CLEAR_XTAL_VREF_SEL(x) ((x) & (~BITS_XTAL_VREF_SEL)) +#define BIT_GET_XTAL_VREF_SEL(x) \ + (((x) >> BIT_SHIFT_XTAL_VREF_SEL) & BIT_MASK_XTAL_VREF_SEL) +#define BIT_SET_XTAL_VREF_SEL(x, v) \ + (BIT_CLEAR_XTAL_VREF_SEL(x) | BIT_XTAL_VREF_SEL(v)) + +#define BIT_EN_XTAL_PDCK_VREF BIT(19) +#define BIT_XTAL_SEL_PWR_V1 BIT(18) +#define BIT_XTAL_LPS_DIVISOR BIT(17) +#define BIT_XTAL_CKDIGI_SEL BIT(16) +#define BIT_EN_XTAL_LPS_CLK BIT(15) +#define BIT_EN_XTAL_SCHMITT BIT(14) +#define BIT_XTAL_PK_SEL_OFFSET BIT(13) + +#define BIT_SHIFT_XTAL_MANU_PK_SEL 11 +#define BIT_MASK_XTAL_MANU_PK_SEL 0x3 +#define BIT_XTAL_MANU_PK_SEL(x) \ + (((x) & BIT_MASK_XTAL_MANU_PK_SEL) << BIT_SHIFT_XTAL_MANU_PK_SEL) +#define BITS_XTAL_MANU_PK_SEL \ + (BIT_MASK_XTAL_MANU_PK_SEL << BIT_SHIFT_XTAL_MANU_PK_SEL) +#define BIT_CLEAR_XTAL_MANU_PK_SEL(x) ((x) & (~BITS_XTAL_MANU_PK_SEL)) +#define BIT_GET_XTAL_MANU_PK_SEL(x) \ + (((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL) & BIT_MASK_XTAL_MANU_PK_SEL) +#define BIT_SET_XTAL_MANU_PK_SEL(x, v) \ + (BIT_CLEAR_XTAL_MANU_PK_SEL(x) | BIT_XTAL_MANU_PK_SEL(v)) + +#define BIT_XTAL_AACK_PK_MANU BIT(10) +#define BIT_EN_XTAL_AAC_PKDET_V1 BIT(9) +#define BIT_EN_XTAL_AAC_GM_V1 BIT(8) +#define BIT_XTAL_LDO_OPVB_SEL BIT(7) + +#define BIT_SHIFT_XTAL_DUMMY_V1 7 +#define BIT_MASK_XTAL_DUMMY_V1 0x3f +#define BIT_XTAL_DUMMY_V1(x) \ + (((x) & BIT_MASK_XTAL_DUMMY_V1) << BIT_SHIFT_XTAL_DUMMY_V1) +#define BITS_XTAL_DUMMY_V1 (BIT_MASK_XTAL_DUMMY_V1 << BIT_SHIFT_XTAL_DUMMY_V1) +#define BIT_CLEAR_XTAL_DUMMY_V1(x) ((x) & (~BITS_XTAL_DUMMY_V1)) +#define BIT_GET_XTAL_DUMMY_V1(x) \ + (((x) >> BIT_SHIFT_XTAL_DUMMY_V1) & BIT_MASK_XTAL_DUMMY_V1) +#define BIT_SET_XTAL_DUMMY_V1(x, v) \ + (BIT_CLEAR_XTAL_DUMMY_V1(x) | BIT_XTAL_DUMMY_V1(v)) + +#define BIT_XTAL_LDO_NC BIT(6) +#define BIT_XTAL_EN_LNBUF BIT(6) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_XTAL_DRV_RF2_LATCH BIT(6) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_XTAL__AAC_TIE_MID BIT(5) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_SHIFT_XTAL_DRV_RF2_1_0 4 +#define BIT_MASK_XTAL_DRV_RF2_1_0 0x3 +#define BIT_XTAL_DRV_RF2_1_0(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_1_0) << BIT_SHIFT_XTAL_DRV_RF2_1_0) +#define BITS_XTAL_DRV_RF2_1_0 \ + (BIT_MASK_XTAL_DRV_RF2_1_0 << BIT_SHIFT_XTAL_DRV_RF2_1_0) +#define BIT_CLEAR_XTAL_DRV_RF2_1_0(x) ((x) & (~BITS_XTAL_DRV_RF2_1_0)) +#define BIT_GET_XTAL_DRV_RF2_1_0(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_1_0) & BIT_MASK_XTAL_DRV_RF2_1_0) +#define BIT_SET_XTAL_DRV_RF2_1_0(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_1_0(x) | BIT_XTAL_DRV_RF2_1_0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_SHIFT_XTAL_LDO_VREF_V2 3 +#define BIT_MASK_XTAL_LDO_VREF_V2 0x7 +#define BIT_XTAL_LDO_VREF_V2(x) \ + (((x) & BIT_MASK_XTAL_LDO_VREF_V2) << BIT_SHIFT_XTAL_LDO_VREF_V2) +#define BITS_XTAL_LDO_VREF_V2 \ + (BIT_MASK_XTAL_LDO_VREF_V2 << BIT_SHIFT_XTAL_LDO_VREF_V2) +#define BIT_CLEAR_XTAL_LDO_VREF_V2(x) ((x) & (~BITS_XTAL_LDO_VREF_V2)) +#define BIT_GET_XTAL_LDO_VREF_V2(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VREF_V2) & BIT_MASK_XTAL_LDO_VREF_V2) +#define BIT_SET_XTAL_LDO_VREF_V2(x, v) \ + (BIT_CLEAR_XTAL_LDO_VREF_V2(x) | BIT_XTAL_LDO_VREF_V2(v)) + +#define BIT_SHIFT_XTAL_AAC_OPCUR 3 +#define BIT_MASK_XTAL_AAC_OPCUR 0x3 +#define BIT_XTAL_AAC_OPCUR(x) \ + (((x) & BIT_MASK_XTAL_AAC_OPCUR) << BIT_SHIFT_XTAL_AAC_OPCUR) +#define BITS_XTAL_AAC_OPCUR \ + (BIT_MASK_XTAL_AAC_OPCUR << BIT_SHIFT_XTAL_AAC_OPCUR) +#define BIT_CLEAR_XTAL_AAC_OPCUR(x) ((x) & (~BITS_XTAL_AAC_OPCUR)) +#define BIT_GET_XTAL_AAC_OPCUR(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_OPCUR) & BIT_MASK_XTAL_AAC_OPCUR) +#define BIT_SET_XTAL_AAC_OPCUR(x, v) \ + (BIT_CLEAR_XTAL_AAC_OPCUR(x) | BIT_XTAL_AAC_OPCUR(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_XTAL_GATED_RF2N BIT(3) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_XTAL_LPMODE_V1 BIT(2) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_XTAL_GATED_RF2P BIT(2) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_SHIFT_XTAL_AAC_IOFFSET 1 +#define BIT_MASK_XTAL_AAC_IOFFSET 0x3 +#define BIT_XTAL_AAC_IOFFSET(x) \ + (((x) & BIT_MASK_XTAL_AAC_IOFFSET) << BIT_SHIFT_XTAL_AAC_IOFFSET) +#define BITS_XTAL_AAC_IOFFSET \ + (BIT_MASK_XTAL_AAC_IOFFSET << BIT_SHIFT_XTAL_AAC_IOFFSET) +#define BIT_CLEAR_XTAL_AAC_IOFFSET(x) ((x) & (~BITS_XTAL_AAC_IOFFSET)) +#define BIT_GET_XTAL_AAC_IOFFSET(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET) & BIT_MASK_XTAL_AAC_IOFFSET) +#define BIT_SET_XTAL_AAC_IOFFSET(x, v) \ + (BIT_CLEAR_XTAL_AAC_IOFFSET(x) | BIT_XTAL_AAC_IOFFSET(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_XTAL_LDO_DI BIT(1) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_SHIFT_XTAL_SEL_TOK_V3 0 +#define BIT_MASK_XTAL_SEL_TOK_V3 0x3 +#define BIT_XTAL_SEL_TOK_V3(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_V3) << BIT_SHIFT_XTAL_SEL_TOK_V3) +#define BITS_XTAL_SEL_TOK_V3 \ + (BIT_MASK_XTAL_SEL_TOK_V3 << BIT_SHIFT_XTAL_SEL_TOK_V3) +#define BIT_CLEAR_XTAL_SEL_TOK_V3(x) ((x) & (~BITS_XTAL_SEL_TOK_V3)) +#define BIT_GET_XTAL_SEL_TOK_V3(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V3) & BIT_MASK_XTAL_SEL_TOK_V3) +#define BIT_SET_XTAL_SEL_TOK_V3(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_V3(x) | BIT_XTAL_SEL_TOK_V3(v)) + +#define BIT_XTAL_AAC_CAP_V1 BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */ + +#define BIT_XTAL_SEL_PWR BIT(0) + +/* 2 REG_ANAPAR_XTAL_AAC (Offset 0x104C) */ + +#define BIT_SHIFT_GM_MANUAL_4_0 21 +#define BIT_MASK_GM_MANUAL_4_0 0x1f +#define BIT_GM_MANUAL_4_0(x) \ + (((x) & BIT_MASK_GM_MANUAL_4_0) << BIT_SHIFT_GM_MANUAL_4_0) +#define BITS_GM_MANUAL_4_0 (BIT_MASK_GM_MANUAL_4_0 << BIT_SHIFT_GM_MANUAL_4_0) +#define BIT_CLEAR_GM_MANUAL_4_0(x) ((x) & (~BITS_GM_MANUAL_4_0)) +#define BIT_GET_GM_MANUAL_4_0(x) \ + (((x) >> BIT_SHIFT_GM_MANUAL_4_0) & BIT_MASK_GM_MANUAL_4_0) +#define BIT_SET_GM_MANUAL_4_0(x, v) \ + (BIT_CLEAR_GM_MANUAL_4_0(x) | BIT_GM_MANUAL_4_0(v)) + +#define BIT_SHIFT_GM_STUP_4_0 16 +#define BIT_MASK_GM_STUP_4_0 0x1f +#define BIT_GM_STUP_4_0(x) \ + (((x) & BIT_MASK_GM_STUP_4_0) << BIT_SHIFT_GM_STUP_4_0) +#define BITS_GM_STUP_4_0 (BIT_MASK_GM_STUP_4_0 << BIT_SHIFT_GM_STUP_4_0) +#define BIT_CLEAR_GM_STUP_4_0(x) ((x) & (~BITS_GM_STUP_4_0)) +#define BIT_GET_GM_STUP_4_0(x) \ + (((x) >> BIT_SHIFT_GM_STUP_4_0) & BIT_MASK_GM_STUP_4_0) +#define BIT_SET_GM_STUP_4_0(x, v) \ + (BIT_CLEAR_GM_STUP_4_0(x) | BIT_GM_STUP_4_0(v)) + +#define BIT_SHIFT_XTAL_CK_SET_2_0 13 +#define BIT_MASK_XTAL_CK_SET_2_0 0x7 +#define BIT_XTAL_CK_SET_2_0(x) \ + (((x) & BIT_MASK_XTAL_CK_SET_2_0) << BIT_SHIFT_XTAL_CK_SET_2_0) +#define BITS_XTAL_CK_SET_2_0 \ + (BIT_MASK_XTAL_CK_SET_2_0 << BIT_SHIFT_XTAL_CK_SET_2_0) +#define BIT_CLEAR_XTAL_CK_SET_2_0(x) ((x) & (~BITS_XTAL_CK_SET_2_0)) +#define BIT_GET_XTAL_CK_SET_2_0(x) \ + (((x) >> BIT_SHIFT_XTAL_CK_SET_2_0) & BIT_MASK_XTAL_CK_SET_2_0) +#define BIT_SET_XTAL_CK_SET_2_0(x, v) \ + (BIT_CLEAR_XTAL_CK_SET_2_0(x) | BIT_XTAL_CK_SET_2_0(v)) + +#define BIT_SHIFT_GM_INIT_4_0 8 +#define BIT_MASK_GM_INIT_4_0 0x1f +#define BIT_GM_INIT_4_0(x) \ + (((x) & BIT_MASK_GM_INIT_4_0) << BIT_SHIFT_GM_INIT_4_0) +#define BITS_GM_INIT_4_0 (BIT_MASK_GM_INIT_4_0 << BIT_SHIFT_GM_INIT_4_0) +#define BIT_CLEAR_GM_INIT_4_0(x) ((x) & (~BITS_GM_INIT_4_0)) +#define BIT_GET_GM_INIT_4_0(x) \ + (((x) >> BIT_SHIFT_GM_INIT_4_0) & BIT_MASK_GM_INIT_4_0) +#define BIT_SET_GM_INIT_4_0(x, v) \ + (BIT_CLEAR_GM_INIT_4_0(x) | BIT_GM_INIT_4_0(v)) + +#define BIT_SHIFT_XAAC_GM_OFFSET_4_0 2 +#define BIT_MASK_XAAC_GM_OFFSET_4_0 0x1f +#define BIT_XAAC_GM_OFFSET_4_0(x) \ + (((x) & BIT_MASK_XAAC_GM_OFFSET_4_0) << BIT_SHIFT_XAAC_GM_OFFSET_4_0) +#define BITS_XAAC_GM_OFFSET_4_0 \ + (BIT_MASK_XAAC_GM_OFFSET_4_0 << BIT_SHIFT_XAAC_GM_OFFSET_4_0) +#define BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) ((x) & (~BITS_XAAC_GM_OFFSET_4_0)) +#define BIT_GET_XAAC_GM_OFFSET_4_0(x) \ + (((x) >> BIT_SHIFT_XAAC_GM_OFFSET_4_0) & BIT_MASK_XAAC_GM_OFFSET_4_0) +#define BIT_SET_XAAC_GM_OFFSET_4_0(x, v) \ + (BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) | BIT_XAAC_GM_OFFSET_4_0(v)) + +/* 2 REG_ANAPAR_XTAL_R_ONLY (Offset 0x1050) */ + +#define BIT_XTAL_PKDET_OUT BIT(6) + +#define BIT_SHIFT_XTAL_GM_AAC_4_0 1 +#define BIT_MASK_XTAL_GM_AAC_4_0 0x1f +#define BIT_XTAL_GM_AAC_4_0(x) \ + (((x) & BIT_MASK_XTAL_GM_AAC_4_0) << BIT_SHIFT_XTAL_GM_AAC_4_0) +#define BITS_XTAL_GM_AAC_4_0 \ + (BIT_MASK_XTAL_GM_AAC_4_0 << BIT_SHIFT_XTAL_GM_AAC_4_0) +#define BIT_CLEAR_XTAL_GM_AAC_4_0(x) ((x) & (~BITS_XTAL_GM_AAC_4_0)) +#define BIT_GET_XTAL_GM_AAC_4_0(x) \ + (((x) >> BIT_SHIFT_XTAL_GM_AAC_4_0) & BIT_MASK_XTAL_GM_AAC_4_0) +#define BIT_SET_XTAL_GM_AAC_4_0(x, v) \ + (BIT_CLEAR_XTAL_GM_AAC_4_0(x) | BIT_XTAL_GM_AAC_4_0(v)) + +#define BIT_XAAC_READY BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ + +#define BIT_XAAC_LPOW BIT(31) + +#define BIT_SHIFT_AAC_MODE 29 +#define BIT_MASK_AAC_MODE 0x3 +#define BIT_AAC_MODE(x) (((x) & BIT_MASK_AAC_MODE) << BIT_SHIFT_AAC_MODE) +#define BITS_AAC_MODE (BIT_MASK_AAC_MODE << BIT_SHIFT_AAC_MODE) +#define BIT_CLEAR_AAC_MODE(x) ((x) & (~BITS_AAC_MODE)) +#define BIT_GET_AAC_MODE(x) (((x) >> BIT_SHIFT_AAC_MODE) & BIT_MASK_AAC_MODE) +#define BIT_SET_AAC_MODE(x, v) (BIT_CLEAR_AAC_MODE(x) | BIT_AAC_MODE(v)) + +#define BIT_SHIFT_GM_MANUAL 21 +#define BIT_MASK_GM_MANUAL 0x1f +#define BIT_GM_MANUAL(x) (((x) & BIT_MASK_GM_MANUAL) << BIT_SHIFT_GM_MANUAL) +#define BITS_GM_MANUAL (BIT_MASK_GM_MANUAL << BIT_SHIFT_GM_MANUAL) +#define BIT_CLEAR_GM_MANUAL(x) ((x) & (~BITS_GM_MANUAL)) +#define BIT_GET_GM_MANUAL(x) (((x) >> BIT_SHIFT_GM_MANUAL) & BIT_MASK_GM_MANUAL) +#define BIT_SET_GM_MANUAL(x, v) (BIT_CLEAR_GM_MANUAL(x) | BIT_GM_MANUAL(v)) + +#define BIT_SHIFT_XTAL_LDO_LPS 21 +#define BIT_MASK_XTAL_LDO_LPS 0x7 +#define BIT_XTAL_LDO_LPS(x) \ + (((x) & BIT_MASK_XTAL_LDO_LPS) << BIT_SHIFT_XTAL_LDO_LPS) +#define BITS_XTAL_LDO_LPS (BIT_MASK_XTAL_LDO_LPS << BIT_SHIFT_XTAL_LDO_LPS) +#define BIT_CLEAR_XTAL_LDO_LPS(x) ((x) & (~BITS_XTAL_LDO_LPS)) +#define BIT_GET_XTAL_LDO_LPS(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_LPS) & BIT_MASK_XTAL_LDO_LPS) +#define BIT_SET_XTAL_LDO_LPS(x, v) \ + (BIT_CLEAR_XTAL_LDO_LPS(x) | BIT_XTAL_LDO_LPS(v)) + +#define BIT_SHIFT_GM_STUP 16 +#define BIT_MASK_GM_STUP 0x1f +#define BIT_GM_STUP(x) (((x) & BIT_MASK_GM_STUP) << BIT_SHIFT_GM_STUP) +#define BITS_GM_STUP (BIT_MASK_GM_STUP << BIT_SHIFT_GM_STUP) +#define BIT_CLEAR_GM_STUP(x) ((x) & (~BITS_GM_STUP)) +#define BIT_GET_GM_STUP(x) (((x) >> BIT_SHIFT_GM_STUP) & BIT_MASK_GM_STUP) +#define BIT_SET_GM_STUP(x, v) (BIT_CLEAR_GM_STUP(x) | BIT_GM_STUP(v)) + +#define BIT_SHIFT_XTAL_WAIT_CYC 15 +#define BIT_MASK_XTAL_WAIT_CYC 0x3f +#define BIT_XTAL_WAIT_CYC(x) \ + (((x) & BIT_MASK_XTAL_WAIT_CYC) << BIT_SHIFT_XTAL_WAIT_CYC) +#define BITS_XTAL_WAIT_CYC (BIT_MASK_XTAL_WAIT_CYC << BIT_SHIFT_XTAL_WAIT_CYC) +#define BIT_CLEAR_XTAL_WAIT_CYC(x) ((x) & (~BITS_XTAL_WAIT_CYC)) +#define BIT_GET_XTAL_WAIT_CYC(x) \ + (((x) >> BIT_SHIFT_XTAL_WAIT_CYC) & BIT_MASK_XTAL_WAIT_CYC) +#define BIT_SET_XTAL_WAIT_CYC(x, v) \ + (BIT_CLEAR_XTAL_WAIT_CYC(x) | BIT_XTAL_WAIT_CYC(v)) + +#define BIT_SHIFT_XTAL_CK_SET 13 +#define BIT_MASK_XTAL_CK_SET 0x7 +#define BIT_XTAL_CK_SET(x) \ + (((x) & BIT_MASK_XTAL_CK_SET) << BIT_SHIFT_XTAL_CK_SET) +#define BITS_XTAL_CK_SET (BIT_MASK_XTAL_CK_SET << BIT_SHIFT_XTAL_CK_SET) +#define BIT_CLEAR_XTAL_CK_SET(x) ((x) & (~BITS_XTAL_CK_SET)) +#define BIT_GET_XTAL_CK_SET(x) \ + (((x) >> BIT_SHIFT_XTAL_CK_SET) & BIT_MASK_XTAL_CK_SET) +#define BIT_SET_XTAL_CK_SET(x, v) \ + (BIT_CLEAR_XTAL_CK_SET(x) | BIT_XTAL_CK_SET(v)) + +#define BIT_SHIFT_XTAL_LDO_OK 12 +#define BIT_MASK_XTAL_LDO_OK 0x7 +#define BIT_XTAL_LDO_OK(x) \ + (((x) & BIT_MASK_XTAL_LDO_OK) << BIT_SHIFT_XTAL_LDO_OK) +#define BITS_XTAL_LDO_OK (BIT_MASK_XTAL_LDO_OK << BIT_SHIFT_XTAL_LDO_OK) +#define BIT_CLEAR_XTAL_LDO_OK(x) ((x) & (~BITS_XTAL_LDO_OK)) +#define BIT_GET_XTAL_LDO_OK(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_OK) & BIT_MASK_XTAL_LDO_OK) +#define BIT_SET_XTAL_LDO_OK(x, v) \ + (BIT_CLEAR_XTAL_LDO_OK(x) | BIT_XTAL_LDO_OK(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CPHY_LDO (Offset 0x1054) */ + +#define BIT_SHIFT_CPHY_LDO_PD 12 +#define BIT_MASK_CPHY_LDO_PD 0x3 +#define BIT_CPHY_LDO_PD(x) \ + (((x) & BIT_MASK_CPHY_LDO_PD) << BIT_SHIFT_CPHY_LDO_PD) +#define BITS_CPHY_LDO_PD (BIT_MASK_CPHY_LDO_PD << BIT_SHIFT_CPHY_LDO_PD) +#define BIT_CLEAR_CPHY_LDO_PD(x) ((x) & (~BITS_CPHY_LDO_PD)) +#define BIT_GET_CPHY_LDO_PD(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_PD) & BIT_MASK_CPHY_LDO_PD) +#define BIT_SET_CPHY_LDO_PD(x, v) \ + (BIT_CLEAR_CPHY_LDO_PD(x) | BIT_CPHY_LDO_PD(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ + +#define BIT_XTAL_MD_LPOW BIT(11) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CPHY_LDO (Offset 0x1054) */ + +#define BIT_SHIFT_CPHY_LDO_SR 10 +#define BIT_MASK_CPHY_LDO_SR 0x3 +#define BIT_CPHY_LDO_SR(x) \ + (((x) & BIT_MASK_CPHY_LDO_SR) << BIT_SHIFT_CPHY_LDO_SR) +#define BITS_CPHY_LDO_SR (BIT_MASK_CPHY_LDO_SR << BIT_SHIFT_CPHY_LDO_SR) +#define BIT_CLEAR_CPHY_LDO_SR(x) ((x) & (~BITS_CPHY_LDO_SR)) +#define BIT_GET_CPHY_LDO_SR(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_SR) & BIT_MASK_CPHY_LDO_SR) +#define BIT_SET_CPHY_LDO_SR(x, v) \ + (BIT_CLEAR_CPHY_LDO_SR(x) | BIT_CPHY_LDO_SR(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ + +#define BIT_SHIFT_XTAL_OV_RATIO 9 +#define BIT_MASK_XTAL_OV_RATIO 0x3 +#define BIT_XTAL_OV_RATIO(x) \ + (((x) & BIT_MASK_XTAL_OV_RATIO) << BIT_SHIFT_XTAL_OV_RATIO) +#define BITS_XTAL_OV_RATIO (BIT_MASK_XTAL_OV_RATIO << BIT_SHIFT_XTAL_OV_RATIO) +#define BIT_CLEAR_XTAL_OV_RATIO(x) ((x) & (~BITS_XTAL_OV_RATIO)) +#define BIT_GET_XTAL_OV_RATIO(x) \ + (((x) >> BIT_SHIFT_XTAL_OV_RATIO) & BIT_MASK_XTAL_OV_RATIO) +#define BIT_SET_XTAL_OV_RATIO(x, v) \ + (BIT_CLEAR_XTAL_OV_RATIO(x) | BIT_XTAL_OV_RATIO(v)) + +#define BIT_SHIFT_GM_INIT 8 +#define BIT_MASK_GM_INIT 0x1f +#define BIT_GM_INIT(x) (((x) & BIT_MASK_GM_INIT) << BIT_SHIFT_GM_INIT) +#define BITS_GM_INIT (BIT_MASK_GM_INIT << BIT_SHIFT_GM_INIT) +#define BIT_CLEAR_GM_INIT(x) ((x) & (~BITS_GM_INIT)) +#define BIT_GET_GM_INIT(x) (((x) >> BIT_SHIFT_GM_INIT) & BIT_MASK_GM_INIT) +#define BIT_SET_GM_INIT(x, v) (BIT_CLEAR_GM_INIT(x) | BIT_GM_INIT(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CPHY_LDO (Offset 0x1054) */ + +#define BIT_SHIFT_CPHY_LDO_TUNEREF 8 +#define BIT_MASK_CPHY_LDO_TUNEREF 0x3 +#define BIT_CPHY_LDO_TUNEREF(x) \ + (((x) & BIT_MASK_CPHY_LDO_TUNEREF) << BIT_SHIFT_CPHY_LDO_TUNEREF) +#define BITS_CPHY_LDO_TUNEREF \ + (BIT_MASK_CPHY_LDO_TUNEREF << BIT_SHIFT_CPHY_LDO_TUNEREF) +#define BIT_CLEAR_CPHY_LDO_TUNEREF(x) ((x) & (~BITS_CPHY_LDO_TUNEREF)) +#define BIT_GET_CPHY_LDO_TUNEREF(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_TUNEREF) & BIT_MASK_CPHY_LDO_TUNEREF) +#define BIT_SET_CPHY_LDO_TUNEREF(x, v) \ + (BIT_CLEAR_CPHY_LDO_TUNEREF(x) | BIT_CPHY_LDO_TUNEREF(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ + +#define BIT_SHIFT_XTAL_OV_UNIT 6 +#define BIT_MASK_XTAL_OV_UNIT 0x7 +#define BIT_XTAL_OV_UNIT(x) \ + (((x) & BIT_MASK_XTAL_OV_UNIT) << BIT_SHIFT_XTAL_OV_UNIT) +#define BITS_XTAL_OV_UNIT (BIT_MASK_XTAL_OV_UNIT << BIT_SHIFT_XTAL_OV_UNIT) +#define BIT_CLEAR_XTAL_OV_UNIT(x) ((x) & (~BITS_XTAL_OV_UNIT)) +#define BIT_GET_XTAL_OV_UNIT(x) \ + (((x) >> BIT_SHIFT_XTAL_OV_UNIT) & BIT_MASK_XTAL_OV_UNIT) +#define BIT_SET_XTAL_OV_UNIT(x, v) \ + (BIT_CLEAR_XTAL_OV_UNIT(x) | BIT_XTAL_OV_UNIT(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CPHY_LDO (Offset 0x1054) */ + +#define BIT_SHIFT_CPHY_LDO_TUNE_VO 5 +#define BIT_MASK_CPHY_LDO_TUNE_VO 0x7 +#define BIT_CPHY_LDO_TUNE_VO(x) \ + (((x) & BIT_MASK_CPHY_LDO_TUNE_VO) << BIT_SHIFT_CPHY_LDO_TUNE_VO) +#define BITS_CPHY_LDO_TUNE_VO \ + (BIT_MASK_CPHY_LDO_TUNE_VO << BIT_SHIFT_CPHY_LDO_TUNE_VO) +#define BIT_CLEAR_CPHY_LDO_TUNE_VO(x) ((x) & (~BITS_CPHY_LDO_TUNE_VO)) +#define BIT_GET_CPHY_LDO_TUNE_VO(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_TUNE_VO) & BIT_MASK_CPHY_LDO_TUNE_VO) +#define BIT_SET_CPHY_LDO_TUNE_VO(x, v) \ + (BIT_CLEAR_CPHY_LDO_TUNE_VO(x) | BIT_CPHY_LDO_TUNE_VO(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ + +#define BIT_SHIFT_XTAL_MODE_MANUAL 4 +#define BIT_MASK_XTAL_MODE_MANUAL 0x3 +#define BIT_XTAL_MODE_MANUAL(x) \ + (((x) & BIT_MASK_XTAL_MODE_MANUAL) << BIT_SHIFT_XTAL_MODE_MANUAL) +#define BITS_XTAL_MODE_MANUAL \ + (BIT_MASK_XTAL_MODE_MANUAL << BIT_SHIFT_XTAL_MODE_MANUAL) +#define BIT_CLEAR_XTAL_MODE_MANUAL(x) ((x) & (~BITS_XTAL_MODE_MANUAL)) +#define BIT_GET_XTAL_MODE_MANUAL(x) \ + (((x) >> BIT_SHIFT_XTAL_MODE_MANUAL) & BIT_MASK_XTAL_MODE_MANUAL) +#define BIT_SET_XTAL_MODE_MANUAL(x, v) \ + (BIT_CLEAR_XTAL_MODE_MANUAL(x) | BIT_XTAL_MODE_MANUAL(v)) + +#define BIT_SHIFT_PK_END_AR 3 +#define BIT_MASK_PK_END_AR 0x3 +#define BIT_PK_END_AR(x) (((x) & BIT_MASK_PK_END_AR) << BIT_SHIFT_PK_END_AR) +#define BITS_PK_END_AR (BIT_MASK_PK_END_AR << BIT_SHIFT_PK_END_AR) +#define BIT_CLEAR_PK_END_AR(x) ((x) & (~BITS_PK_END_AR)) +#define BIT_GET_PK_END_AR(x) (((x) >> BIT_SHIFT_PK_END_AR) & BIT_MASK_PK_END_AR) +#define BIT_SET_PK_END_AR(x, v) (BIT_CLEAR_PK_END_AR(x) | BIT_PK_END_AR(v)) + +#define BIT_XTAL_MANU_SEL BIT(3) + +#define BIT_SHIFT_XAAC_GM_OFFSET 2 +#define BIT_MASK_XAAC_GM_OFFSET 0x1f +#define BIT_XAAC_GM_OFFSET(x) \ + (((x) & BIT_MASK_XAAC_GM_OFFSET) << BIT_SHIFT_XAAC_GM_OFFSET) +#define BITS_XAAC_GM_OFFSET \ + (BIT_MASK_XAAC_GM_OFFSET << BIT_SHIFT_XAAC_GM_OFFSET) +#define BIT_CLEAR_XAAC_GM_OFFSET(x) ((x) & (~BITS_XAAC_GM_OFFSET)) +#define BIT_GET_XAAC_GM_OFFSET(x) \ + (((x) >> BIT_SHIFT_XAAC_GM_OFFSET) & BIT_MASK_XAAC_GM_OFFSET) +#define BIT_SET_XAAC_GM_OFFSET(x, v) \ + (BIT_CLEAR_XAAC_GM_OFFSET(x) | BIT_XAAC_GM_OFFSET(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CPHY_LDO (Offset 0x1054) */ + +#define BIT_SHIFT_CPHY_LDO_OCP_VTH 2 +#define BIT_MASK_CPHY_LDO_OCP_VTH 0x7 +#define BIT_CPHY_LDO_OCP_VTH(x) \ + (((x) & BIT_MASK_CPHY_LDO_OCP_VTH) << BIT_SHIFT_CPHY_LDO_OCP_VTH) +#define BITS_CPHY_LDO_OCP_VTH \ + (BIT_MASK_CPHY_LDO_OCP_VTH << BIT_SHIFT_CPHY_LDO_OCP_VTH) +#define BIT_CLEAR_CPHY_LDO_OCP_VTH(x) ((x) & (~BITS_CPHY_LDO_OCP_VTH)) +#define BIT_GET_CPHY_LDO_OCP_VTH(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_OCP_VTH) & BIT_MASK_CPHY_LDO_OCP_VTH) +#define BIT_SET_CPHY_LDO_OCP_VTH(x, v) \ + (BIT_CLEAR_CPHY_LDO_OCP_VTH(x) | BIT_CPHY_LDO_OCP_VTH(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */ + +#define BIT_SHIFT_PK_START_AR 1 +#define BIT_MASK_PK_START_AR 0x3 +#define BIT_PK_START_AR(x) \ + (((x) & BIT_MASK_PK_START_AR) << BIT_SHIFT_PK_START_AR) +#define BITS_PK_START_AR (BIT_MASK_PK_START_AR << BIT_SHIFT_PK_START_AR) +#define BIT_CLEAR_PK_START_AR(x) ((x) & (~BITS_PK_START_AR)) +#define BIT_GET_PK_START_AR(x) \ + (((x) >> BIT_SHIFT_PK_START_AR) & BIT_MASK_PK_START_AR) +#define BIT_SET_PK_START_AR(x, v) \ + (BIT_CLEAR_PK_START_AR(x) | BIT_PK_START_AR(v)) + +#define BIT_XTAL_MODE BIT(1) +#define BIT_XAAC_LUT_MANUAL_EN BIT(0) +#define BIT_RESET_N_DECODER BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CPHY_LDO (Offset 0x1054) */ + +#define BIT_SHIFT_VREF_LDO_OK 0 +#define BIT_MASK_VREF_LDO_OK 0x3 +#define BIT_VREF_LDO_OK(x) \ + (((x) & BIT_MASK_VREF_LDO_OK) << BIT_SHIFT_VREF_LDO_OK) +#define BITS_VREF_LDO_OK (BIT_MASK_VREF_LDO_OK << BIT_SHIFT_VREF_LDO_OK) +#define BIT_CLEAR_VREF_LDO_OK(x) ((x) & (~BITS_VREF_LDO_OK)) +#define BIT_GET_VREF_LDO_OK(x) \ + (((x) >> BIT_SHIFT_VREF_LDO_OK) & BIT_MASK_VREF_LDO_OK) +#define BIT_SET_VREF_LDO_OK(x, v) \ + (BIT_CLEAR_VREF_LDO_OK(x) | BIT_VREF_LDO_OK(v)) + +/* 2 REG_CPHY_BG (Offset 0x1058) */ + +#define BIT_TXBCN_OK_PORT4 BIT(31) +#define BIT_ATIMEND_PORT4 BIT(31) +#define BIT_TXBCN_OK_PORT3 BIT(30) +#define BIT_ATIMEND_PORT3 BIT(30) +#define BIT_TXBCN_OK_PORT2 BIT(29) +#define BIT_ATIMEND_PORT2 BIT(29) +#define BIT_TXBCN_OK_PORT1 BIT(28) +#define BIT_ATIMEND_PORT1 BIT(28) +#define BIT_TXBCN15OK BIT(23) +#define BIT_BCNDMAINT15 BIT(23) +#define BIT_ATIMEND15 BIT(23) +#define BIT_TXBCN14OK BIT(22) +#define BIT_BCNDMAINT14 BIT(22) +#define BIT_ATIMEND14 BIT(22) +#define BIT_TXBCN13OK BIT(21) +#define BIT_BCNDMAINT13 BIT(21) +#define BIT_ATIMEND13 BIT(21) +#define BIT_TXBCN12OK BIT(20) +#define BIT_BCNDMAINT12 BIT(20) +#define BIT_ATIMEND12 BIT(20) +#define BIT_TXBCN11OK BIT(19) +#define BIT_BCNDMAINT11 BIT(19) +#define BIT_ATIMEND11 BIT(19) +#define BIT_TXBCN10OK BIT(18) +#define BIT_BCNDMAINT10 BIT(18) +#define BIT_ATIMEND10 BIT(18) +#define BIT_TXBCN9OK BIT(17) +#define BIT_BCNDMAINT9 BIT(17) +#define BIT_ATIMEND9 BIT(17) +#define BIT_TXBCN8OK BIT(16) +#define BIT_BCNDMAINT8 BIT(16) +#define BIT_ATIMEND8 BIT(16) +#define BIT_BCNDERR_PORT4 BIT(15) +#define BIT_BCNDERR_PORT3 BIT(14) +#define BIT_BCNDERR_PORT2 BIT(13) +#define BIT_BCNDERR_PORT1 BIT(12) +#define BIT_TXBCN15ERR BIT(7) +#define BIT_BCNDERR15 BIT(7) +#define BIT_TXBCN14ERR BIT(6) +#define BIT_BCNDERR14 BIT(6) +#define BIT_TXBCN13ERR BIT(5) +#define BIT_BCNDERR13 BIT(5) +#define BIT_PS_TIMER_EARLY_INT_5 BIT(5) +#define BIT_TXBCN12ERR BIT(4) +#define BIT_BCNDERR12 BIT(4) +#define BIT_PS_TIMER_EARLY_INT_4 BIT(4) +#define BIT_TXBCN11ERR BIT(3) +#define BIT_BCNDERR11 BIT(3) +#define BIT_PS_TIMER_EARLY_INT_3 BIT(3) +#define BIT_TXBCN10ERR BIT(2) +#define BIT_BCNDERR10 BIT(2) +#define BIT_PS_TIMER_EARLY_INT_2 BIT(2) +#define BIT_TXBCN9ERR BIT(1) +#define BIT_BCNDERR9 BIT(1) +#define BIT_PS_TIMER_EARLY_INT_1 BIT(1) + +#define BIT_SHIFT_BG 0 +#define BIT_MASK_BG 0x7 +#define BIT_BG(x) (((x) & BIT_MASK_BG) << BIT_SHIFT_BG) +#define BITS_BG (BIT_MASK_BG << BIT_SHIFT_BG) +#define BIT_CLEAR_BG(x) ((x) & (~BITS_BG)) +#define BIT_GET_BG(x) (((x) >> BIT_SHIFT_BG) & BIT_MASK_BG) +#define BIT_SET_BG(x, v) (BIT_CLEAR_BG(x) | BIT_BG(v)) + +#define BIT_TXBCN8ERR BIT(0) +#define BIT_BCNDERR8 BIT(0) +#define BIT_PS_TIMER_EARLY_INT_0 BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SYS_CFG5 (Offset 0x1070) */ + +#define BIT_LPS_STATUS BIT(3) +#define BIT_HCI_TXDMA_BUSY BIT(2) +#define BIT_HCI_TXDMA_ALLOW BIT(1) +#define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT) + +/* 2 REG_REGU_32K_1 (Offset 0x1078) */ + +#define BIT_OUT_SEL BIT(26) + +#define BIT_SHIFT_FREQ_SEL 24 +#define BIT_MASK_FREQ_SEL 0x3 +#define BIT_FREQ_SEL(x) (((x) & BIT_MASK_FREQ_SEL) << BIT_SHIFT_FREQ_SEL) +#define BITS_FREQ_SEL (BIT_MASK_FREQ_SEL << BIT_SHIFT_FREQ_SEL) +#define BIT_CLEAR_FREQ_SEL(x) ((x) & (~BITS_FREQ_SEL)) +#define BIT_GET_FREQ_SEL(x) (((x) >> BIT_SHIFT_FREQ_SEL) & BIT_MASK_FREQ_SEL) +#define BIT_SET_FREQ_SEL(x, v) (BIT_CLEAR_FREQ_SEL(x) | BIT_FREQ_SEL(v)) + +#define BIT_SHIFT_CLKGEN0 16 +#define BIT_MASK_CLKGEN0 0xff +#define BIT_CLKGEN0(x) (((x) & BIT_MASK_CLKGEN0) << BIT_SHIFT_CLKGEN0) +#define BITS_CLKGEN0 (BIT_MASK_CLKGEN0 << BIT_SHIFT_CLKGEN0) +#define BIT_CLEAR_CLKGEN0(x) ((x) & (~BITS_CLKGEN0)) +#define BIT_GET_CLKGEN0(x) (((x) >> BIT_SHIFT_CLKGEN0) & BIT_MASK_CLKGEN0) +#define BIT_SET_CLKGEN0(x, v) (BIT_CLEAR_CLKGEN0(x) | BIT_CLKGEN0(v)) + +#define BIT_SHIFT_TEMP_COMP 12 +#define BIT_MASK_TEMP_COMP 0xf +#define BIT_TEMP_COMP(x) (((x) & BIT_MASK_TEMP_COMP) << BIT_SHIFT_TEMP_COMP) +#define BITS_TEMP_COMP (BIT_MASK_TEMP_COMP << BIT_SHIFT_TEMP_COMP) +#define BIT_CLEAR_TEMP_COMP(x) ((x) & (~BITS_TEMP_COMP)) +#define BIT_GET_TEMP_COMP(x) (((x) >> BIT_SHIFT_TEMP_COMP) & BIT_MASK_TEMP_COMP) +#define BIT_SET_TEMP_COMP(x, v) (BIT_CLEAR_TEMP_COMP(x) | BIT_TEMP_COMP(v)) + +#define BIT_SHIFT_LDO_V18ADJ 8 +#define BIT_MASK_LDO_V18ADJ 0xf +#define BIT_LDO_V18ADJ(x) (((x) & BIT_MASK_LDO_V18ADJ) << BIT_SHIFT_LDO_V18ADJ) +#define BITS_LDO_V18ADJ (BIT_MASK_LDO_V18ADJ << BIT_SHIFT_LDO_V18ADJ) +#define BIT_CLEAR_LDO_V18ADJ(x) ((x) & (~BITS_LDO_V18ADJ)) +#define BIT_GET_LDO_V18ADJ(x) \ + (((x) >> BIT_SHIFT_LDO_V18ADJ) & BIT_MASK_LDO_V18ADJ) +#define BIT_SET_LDO_V18ADJ(x, v) (BIT_CLEAR_LDO_V18ADJ(x) | BIT_LDO_V18ADJ(v)) + +#define BIT_SHIFT_COMP_LOAD_CUR 5 +#define BIT_MASK_COMP_LOAD_CUR 0x3 +#define BIT_COMP_LOAD_CUR(x) \ + (((x) & BIT_MASK_COMP_LOAD_CUR) << BIT_SHIFT_COMP_LOAD_CUR) +#define BITS_COMP_LOAD_CUR (BIT_MASK_COMP_LOAD_CUR << BIT_SHIFT_COMP_LOAD_CUR) +#define BIT_CLEAR_COMP_LOAD_CUR(x) ((x) & (~BITS_COMP_LOAD_CUR)) +#define BIT_GET_COMP_LOAD_CUR(x) \ + (((x) >> BIT_SHIFT_COMP_LOAD_CUR) & BIT_MASK_COMP_LOAD_CUR) +#define BIT_SET_COMP_LOAD_CUR(x, v) \ + (BIT_CLEAR_COMP_LOAD_CUR(x) | BIT_COMP_LOAD_CUR(v)) + +#define BIT_SHIFT_COMP_LATCH_CUR 3 +#define BIT_MASK_COMP_LATCH_CUR 0x3 +#define BIT_COMP_LATCH_CUR(x) \ + (((x) & BIT_MASK_COMP_LATCH_CUR) << BIT_SHIFT_COMP_LATCH_CUR) +#define BITS_COMP_LATCH_CUR \ + (BIT_MASK_COMP_LATCH_CUR << BIT_SHIFT_COMP_LATCH_CUR) +#define BIT_CLEAR_COMP_LATCH_CUR(x) ((x) & (~BITS_COMP_LATCH_CUR)) +#define BIT_GET_COMP_LATCH_CUR(x) \ + (((x) >> BIT_SHIFT_COMP_LATCH_CUR) & BIT_MASK_COMP_LATCH_CUR) +#define BIT_SET_COMP_LATCH_CUR(x, v) \ + (BIT_CLEAR_COMP_LATCH_CUR(x) | BIT_COMP_LATCH_CUR(v)) + +#define BIT_SHIFT_COMP_GM_CUR 1 +#define BIT_MASK_COMP_GM_CUR 0x3 +#define BIT_COMP_GM_CUR(x) \ + (((x) & BIT_MASK_COMP_GM_CUR) << BIT_SHIFT_COMP_GM_CUR) +#define BITS_COMP_GM_CUR (BIT_MASK_COMP_GM_CUR << BIT_SHIFT_COMP_GM_CUR) +#define BIT_CLEAR_COMP_GM_CUR(x) ((x) & (~BITS_COMP_GM_CUR)) +#define BIT_GET_COMP_GM_CUR(x) \ + (((x) >> BIT_SHIFT_COMP_GM_CUR) & BIT_MASK_COMP_GM_CUR) +#define BIT_SET_COMP_GM_CUR(x, v) \ + (BIT_CLEAR_COMP_GM_CUR(x) | BIT_COMP_GM_CUR(v)) + +/* 2 REG_REGU_32K_2 (Offset 0x107C) */ + +#define BIT_SEL_RCAL_SOURCE BIT(16) + +#define BIT_SHIFT_RCAL 0 +#define BIT_MASK_RCAL 0x3f +#define BIT_RCAL(x) (((x) & BIT_MASK_RCAL) << BIT_SHIFT_RCAL) +#define BITS_RCAL (BIT_MASK_RCAL << BIT_SHIFT_RCAL) +#define BIT_CLEAR_RCAL(x) ((x) & (~BITS_RCAL)) +#define BIT_GET_RCAL(x) (((x) >> BIT_SHIFT_RCAL) & BIT_MASK_RCAL) +#define BIT_SET_RCAL(x, v) (BIT_CLEAR_RCAL(x) | BIT_RCAL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ + +#define BIT_SCH_PHY_TXOP_SIFS_INT BIT(23) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ + +#define BIT_WDT_AUTO_MODE BIT(22) +#define BIT_WDT_PLATFORM_EN BIT(21) +#define BIT_WDT_CPU_EN BIT(20) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ + +#define BIT_WDT_OPT_IOWRAPPER BIT(19) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ + +#define BIT_ANA_PORT_IDLE BIT(18) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ + +#define BIT_TEST_EPHY_BY_REG BIT(17) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ + +#define BIT_MAC_PORT_IDLE BIT(17) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ + +#define BIT_SYM_FEN_WLPLT BIT(16) +#define BIT_TEST_UPHY_BY_REG BIT(16) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ + +#define BIT_WL_PLATFORM_RST BIT(16) +#define BIT_WL_SECURITY_CLK BIT(15) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ + +#define BIT_DDMA_EN BIT(8) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ + +#define BIT_UPHY_SLB_HW_PRD BIT(7) +#define BIT_UPHY_FS_SLB_OK BIT(6) +#define BIT_UPHY_HS_SLB_OK BIT(5) +#define BIT_UPHY_SLB_CMD BIT(4) +#define BIT_UPHY_SLB_FAIL BIT(3) +#define BIT_UPHY_SLB_DONE BIT(2) +#define BIT_UPHY_FORCE_SLB BIT(1) + +#define BIT_SHIFT_SYM_CPU_DMEN_CON 0 +#define BIT_MASK_SYM_CPU_DMEN_CON 0xff +#define BIT_SYM_CPU_DMEN_CON(x) \ + (((x) & BIT_MASK_SYM_CPU_DMEN_CON) << BIT_SHIFT_SYM_CPU_DMEN_CON) +#define BITS_SYM_CPU_DMEN_CON \ + (BIT_MASK_SYM_CPU_DMEN_CON << BIT_SHIFT_SYM_CPU_DMEN_CON) +#define BIT_CLEAR_SYM_CPU_DMEN_CON(x) ((x) & (~BITS_SYM_CPU_DMEN_CON)) +#define BIT_GET_SYM_CPU_DMEN_CON(x) \ + (((x) >> BIT_SHIFT_SYM_CPU_DMEN_CON) & BIT_MASK_SYM_CPU_DMEN_CON) +#define BIT_SET_SYM_CPU_DMEN_CON(x, v) \ + (BIT_CLEAR_SYM_CPU_DMEN_CON(x) | BIT_SYM_CPU_DMEN_CON(v)) + +#define BIT_SHIFT_BCAM_CTRL 0 +#define BIT_MASK_BCAM_CTRL 0xffffffffL +#define BIT_BCAM_CTRL(x) (((x) & BIT_MASK_BCAM_CTRL) << BIT_SHIFT_BCAM_CTRL) +#define BITS_BCAM_CTRL (BIT_MASK_BCAM_CTRL << BIT_SHIFT_BCAM_CTRL) +#define BIT_CLEAR_BCAM_CTRL(x) ((x) & (~BITS_BCAM_CTRL)) +#define BIT_GET_BCAM_CTRL(x) (((x) >> BIT_SHIFT_BCAM_CTRL) & BIT_MASK_BCAM_CTRL) +#define BIT_SET_BCAM_CTRL(x, v) (BIT_CLEAR_BCAM_CTRL(x) | BIT_BCAM_CTRL(v)) + +#define BIT_UPHY_SLB_HS BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ + +#define BIT_SHIFT_CPU_DMEM_CON 0 +#define BIT_MASK_CPU_DMEM_CON 0xff +#define BIT_CPU_DMEM_CON(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON) +#define BITS_CPU_DMEM_CON (BIT_MASK_CPU_DMEM_CON << BIT_SHIFT_CPU_DMEM_CON) +#define BIT_CLEAR_CPU_DMEM_CON(x) ((x) & (~BITS_CPU_DMEM_CON)) +#define BIT_GET_CPU_DMEM_CON(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON) +#define BIT_SET_CPU_DMEM_CON(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON(x) | BIT_CPU_DMEM_CON(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_BOOT_REASON (Offset 0x1088) */ + +#define BIT_SHIFT_BOOT_REASON_V1 0 +#define BIT_MASK_BOOT_REASON_V1 0x7 +#define BIT_BOOT_REASON_V1(x) \ + (((x) & BIT_MASK_BOOT_REASON_V1) << BIT_SHIFT_BOOT_REASON_V1) +#define BITS_BOOT_REASON_V1 \ + (BIT_MASK_BOOT_REASON_V1 << BIT_SHIFT_BOOT_REASON_V1) +#define BIT_CLEAR_BOOT_REASON_V1(x) ((x) & (~BITS_BOOT_REASON_V1)) +#define BIT_GET_BOOT_REASON_V1(x) \ + (((x) >> BIT_SHIFT_BOOT_REASON_V1) & BIT_MASK_BOOT_REASON_V1) +#define BIT_SET_BOOT_REASON_V1(x, v) \ + (BIT_CLEAR_BOOT_REASON_V1(x) | BIT_BOOT_REASON_V1(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HIMR4 (Offset 0x1090) */ + +#define BIT_ATIM_END_INT16_MSK BIT(32) +#define BIT_ATIM_END_INT15_MSK BIT(31) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ + +#define BIT_DATA_FW_READY BIT(31) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HIMR4 (Offset 0x1090) */ + +#define BIT_ATIM_END_INT14_MSK BIT(30) +#define BIT_ATIM_END_INT13_MSK BIT(29) +#define BIT_ATIM_END_INT12_MSK BIT(28) +#define BIT_ATIM_END_INT11_MSK BIT(27) +#define BIT_ATIM_END_INT10_MSK BIT(26) +#define BIT_ATIM_END_INT9_MSK BIT(25) +#define BIT_ATIM_END_INT8_MSK BIT(24) +#define BIT_TX_BCN_ERR_INT15_MSK BIT(23) +#define BIT_TX_BCN_ERR_INT14_MSK BIT(22) +#define BIT_TX_BCN_ERR_INT13_MSK BIT(21) +#define BIT_TX_BCN_ERR_INT12_MSK BIT(20) +#define BIT_TX_BCN_ERR_INT11_MSK BIT(19) +#define BIT_TX_BCN_ERR_INT10_MSK BIT(18) +#define BIT_TX_BCN_ERR_INT9_MSK BIT(17) +#define BIT_TX_BCN_ERR_INT8_MSK BIT(16) +#define BIT_TX_BCN_OK_INT15_MSK BIT(15) +#define BIT_TX_BCN_OK_INT14_MSK BIT(14) +#define BIT_TX_BCN_OK_INT13_MSK BIT(13) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ + +#define BIT_WDT_SYS_RST BIT(13) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HIMR4 (Offset 0x1090) */ + +#define BIT_TX_BCN_OK_INT12_MSK BIT(12) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ + +#define BIT_WDT_ENABLE BIT(12) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HIMR4 (Offset 0x1090) */ + +#define BIT_TX_BCN_OK_INT11_MSK BIT(11) +#define BIT_TX_BCN_OK_INT10_MSK BIT(10) +#define BIT_TX_BCN_OK_INT9_MSK BIT(9) +#define BIT_TX_BCN_OK_INT8_MSK BIT(8) +#define BIT_BCN_DMA_INT15_MSK BIT(7) +#define BIT_BCN_DMA_INT14_MSK BIT(6) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ + +#define BIT_SHIFT_BOOT_SEL 6 +#define BIT_MASK_BOOT_SEL 0x3 +#define BIT_BOOT_SEL(x) (((x) & BIT_MASK_BOOT_SEL) << BIT_SHIFT_BOOT_SEL) +#define BITS_BOOT_SEL (BIT_MASK_BOOT_SEL << BIT_SHIFT_BOOT_SEL) +#define BIT_CLEAR_BOOT_SEL(x) ((x) & (~BITS_BOOT_SEL)) +#define BIT_GET_BOOT_SEL(x) (((x) >> BIT_SHIFT_BOOT_SEL) & BIT_MASK_BOOT_SEL) +#define BIT_SET_BOOT_SEL(x, v) (BIT_CLEAR_BOOT_SEL(x) | BIT_BOOT_SEL(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HIMR4 (Offset 0x1090) */ + +#define BIT_BCN_DMA_INT13_MSK BIT(5) +#define BIT_BCN_DMA_INT12_MSK BIT(4) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ + +#define BIT_CLK_SEL BIT(4) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HIMR4 (Offset 0x1090) */ + +#define BIT_BCN_DMA_INT11_MSK BIT(3) +#define BIT_BCN_DMA_INT10_MSK BIT(2) +#define BIT_BCN_DMA_INT9_MSK BIT(1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ + +#define BIT_DATA_PLATFORM_RST BIT(1) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HIMR4 (Offset 0x1090) */ + +#define BIT_BCN_DMA_INT8_MSK BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */ + +#define BIT_DATA_CPU_RST BIT(0) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HISR4 (Offset 0x1094) */ + +#define BIT_TX_BCN_ERR_INT15 BIT(23) +#define BIT_TX_BCN_ERR_INT14 BIT(22) +#define BIT_TX_BCN_ERR_INT13 BIT(21) +#define BIT_TX_BCN_ERR_INT12 BIT(20) +#define BIT_TX_BCN_ERR_INT11 BIT(19) +#define BIT_TX_BCN_ERR_INT10 BIT(18) +#define BIT_TX_BCN_ERR_INT9 BIT(17) +#define BIT_TX_BCN_ERR_INT8 BIT(16) +#define BIT_TX_BCN_OK_INT15 BIT(15) +#define BIT_TX_BCN_OK_INT14 BIT(14) +#define BIT_TX_BCN_OK_INT13 BIT(13) +#define BIT_TX_BCN_OK_INT12 BIT(12) +#define BIT_TX_BCN_OK_INT11 BIT(11) +#define BIT_TX_BCN_OK_INT10 BIT(10) +#define BIT_TX_BCN_OK_INT9 BIT(9) +#define BIT_TX_BCN_OK_INT8 BIT(8) +#define BIT_BCN_DMA_INT15 BIT(7) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ + +#define BIT_HOST_INTERFACE_IO_PATH BIT(7) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HISR4 (Offset 0x1094) */ + +#define BIT_BCN_DMA_INT14 BIT(6) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ + +#define BIT_EN_TXDMA_OFLD BIT(6) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HISR4 (Offset 0x1094) */ + +#define BIT_BCN_DMA_INT13 BIT(5) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ + +#define BIT_EN_RXDMA_OFLD BIT(5) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HISR4 (Offset 0x1094) */ + +#define BIT_BCN_DMA_INT12 BIT(4) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ + +#define BIT_EN_HCI_DMA_TX BIT(4) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HISR4 (Offset 0x1094) */ + +#define BIT_BCN_DMA_INT11 BIT(3) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ + +#define BIT_EN_HCI_DMA_RX BIT(3) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HISR4 (Offset 0x1094) */ + +#define BIT_BCN_DMA_INT10 BIT(2) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ + +#define BIT_EN_AXI_DMA_TX BIT(2) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HISR4 (Offset 0x1094) */ + +#define BIT_BCN_DMA_INT9 BIT(1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ + +#define BIT_EN_AXI_DMA_RX BIT(1) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HISR4 (Offset 0x1094) */ + +#define BIT_BCN_DMA_INT8 BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */ + +#define BIT_EN_PKT_ENG BIT(0) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HIMR5 (Offset 0x1098) */ + +#define BIT_BCN_QDMA_ERR_INT15_MSK BIT(7) +#define BIT_BCN_QDMA_ERR_INT14_MSK BIT(6) +#define BIT_BCN_QDMA_ERR_INT13_MSK BIT(5) +#define BIT_BCN_QDMA_ERR_INT12_MSK BIT(4) +#define BIT_BCN_QDMA_ERR_INT11_MSK BIT(3) +#define BIT_BCN_QDMA_ERR_INT10_MSK BIT(2) +#define BIT_BCN_QDMA_ERR_INT9_MSK BIT(1) +#define BIT_BCN_QDMA_ERR_INT8_MSK BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_TXDMA_STOP_HIMR (Offset 0x1098) */ + +#define BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK 0 +#define BIT_MASK_NTH_TXDMA_STOP_INT_MSK 0x1ffff +#define BIT_NTH_TXDMA_STOP_INT_MSK(x) \ + (((x) & BIT_MASK_NTH_TXDMA_STOP_INT_MSK) \ + << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) +#define BITS_NTH_TXDMA_STOP_INT_MSK \ + (BIT_MASK_NTH_TXDMA_STOP_INT_MSK << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) +#define BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x) \ + ((x) & (~BITS_NTH_TXDMA_STOP_INT_MSK)) +#define BIT_GET_NTH_TXDMA_STOP_INT_MSK(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) & \ + BIT_MASK_NTH_TXDMA_STOP_INT_MSK) +#define BIT_SET_NTH_TXDMA_STOP_INT_MSK(x, v) \ + (BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x) | BIT_NTH_TXDMA_STOP_INT_MSK(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HISR5 (Offset 0x109C) */ + +#define BIT_BCN_QDMA_ERR_INT15 BIT(7) +#define BIT_BCN_QDMA_ERR_INT14 BIT(6) +#define BIT_BCN_QDMA_ERR_INT13 BIT(5) +#define BIT_BCN_QDMA_ERR_INT12 BIT(4) +#define BIT_BCN_QDMA_ERR_INT11 BIT(3) +#define BIT_BCN_QDMA_ERR_INT10 BIT(2) +#define BIT_BCN_QDMA_ERR_INT9 BIT(1) +#define BIT_BCN_QDMA_ERR_INT8 BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_TXDMA_STOP_HISR (Offset 0x109C) */ + +#define BIT_SHIFT_NTH_TXDMA_STOP_INT 0 +#define BIT_MASK_NTH_TXDMA_STOP_INT 0x1ffff +#define BIT_NTH_TXDMA_STOP_INT(x) \ + (((x) & BIT_MASK_NTH_TXDMA_STOP_INT) << BIT_SHIFT_NTH_TXDMA_STOP_INT) +#define BITS_NTH_TXDMA_STOP_INT \ + (BIT_MASK_NTH_TXDMA_STOP_INT << BIT_SHIFT_NTH_TXDMA_STOP_INT) +#define BIT_CLEAR_NTH_TXDMA_STOP_INT(x) ((x) & (~BITS_NTH_TXDMA_STOP_INT)) +#define BIT_GET_NTH_TXDMA_STOP_INT(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT) & BIT_MASK_NTH_TXDMA_STOP_INT) +#define BIT_SET_NTH_TXDMA_STOP_INT(x, v) \ + (BIT_CLEAR_NTH_TXDMA_STOP_INT(x) | BIT_NTH_TXDMA_STOP_INT(v)) + +/* 2 REG_TXDMA_START_HIMR (Offset 0x10A0) */ + +#define BIT_SHIFT_NTH_TXDMA_START_INT_MSK 0 +#define BIT_MASK_NTH_TXDMA_START_INT_MSK 0x1ffff +#define BIT_NTH_TXDMA_START_INT_MSK(x) \ + (((x) & BIT_MASK_NTH_TXDMA_START_INT_MSK) \ + << BIT_SHIFT_NTH_TXDMA_START_INT_MSK) +#define BITS_NTH_TXDMA_START_INT_MSK \ + (BIT_MASK_NTH_TXDMA_START_INT_MSK << BIT_SHIFT_NTH_TXDMA_START_INT_MSK) +#define BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x) \ + ((x) & (~BITS_NTH_TXDMA_START_INT_MSK)) +#define BIT_GET_NTH_TXDMA_START_INT_MSK(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_MSK) & \ + BIT_MASK_NTH_TXDMA_START_INT_MSK) +#define BIT_SET_NTH_TXDMA_START_INT_MSK(x, v) \ + (BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x) | BIT_NTH_TXDMA_START_INT_MSK(v)) + +/* 2 REG_TXDMA_START_HISR (Offset 0x10A4) */ + +#define BIT_SHIFT_NTH_TXDMA_START_INT 0 +#define BIT_MASK_NTH_TXDMA_START_INT 0x1ffff +#define BIT_NTH_TXDMA_START_INT(x) \ + (((x) & BIT_MASK_NTH_TXDMA_START_INT) << BIT_SHIFT_NTH_TXDMA_START_INT) +#define BITS_NTH_TXDMA_START_INT \ + (BIT_MASK_NTH_TXDMA_START_INT << BIT_SHIFT_NTH_TXDMA_START_INT) +#define BIT_CLEAR_NTH_TXDMA_START_INT(x) ((x) & (~BITS_NTH_TXDMA_START_INT)) +#define BIT_GET_NTH_TXDMA_START_INT(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT) & BIT_MASK_NTH_TXDMA_START_INT) +#define BIT_SET_NTH_TXDMA_START_INT(x, v) \ + (BIT_CLEAR_NTH_TXDMA_START_INT(x) | BIT_NTH_TXDMA_START_INT(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +/* 2 REG_NFCPAD_CTRL (Offset 0x10A8) */ + +#define BIT_PAD_SHUTDW BIT(18) +#define BIT_SYSON_NFC_PAD BIT(17) +#define BIT_NFC_INT_PAD_CTRL BIT(16) +#define BIT_NFC_RFDIS_PAD_CTRL BIT(15) +#define BIT_NFC_CLK_PAD_CTRL BIT(14) +#define BIT_NFC_DATA_PAD_CTRL BIT(13) +#define BIT_NFC_PAD_PULL_CTRL BIT(12) + +#define BIT_SHIFT_NFCPAD_IO_SEL 8 +#define BIT_MASK_NFCPAD_IO_SEL 0xf +#define BIT_NFCPAD_IO_SEL(x) \ + (((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL) +#define BITS_NFCPAD_IO_SEL (BIT_MASK_NFCPAD_IO_SEL << BIT_SHIFT_NFCPAD_IO_SEL) +#define BIT_CLEAR_NFCPAD_IO_SEL(x) ((x) & (~BITS_NFCPAD_IO_SEL)) +#define BIT_GET_NFCPAD_IO_SEL(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL) +#define BIT_SET_NFCPAD_IO_SEL(x, v) \ + (BIT_CLEAR_NFCPAD_IO_SEL(x) | BIT_NFCPAD_IO_SEL(v)) + +#define BIT_SHIFT_NFCPAD_OUT 4 +#define BIT_MASK_NFCPAD_OUT 0xf +#define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT) +#define BITS_NFCPAD_OUT (BIT_MASK_NFCPAD_OUT << BIT_SHIFT_NFCPAD_OUT) +#define BIT_CLEAR_NFCPAD_OUT(x) ((x) & (~BITS_NFCPAD_OUT)) +#define BIT_GET_NFCPAD_OUT(x) \ + (((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT) +#define BIT_SET_NFCPAD_OUT(x, v) (BIT_CLEAR_NFCPAD_OUT(x) | BIT_NFCPAD_OUT(v)) + +#define BIT_SHIFT_NFCPAD_IN 0 +#define BIT_MASK_NFCPAD_IN 0xf +#define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN) +#define BITS_NFCPAD_IN (BIT_MASK_NFCPAD_IN << BIT_SHIFT_NFCPAD_IN) +#define BIT_CLEAR_NFCPAD_IN(x) ((x) & (~BITS_NFCPAD_IN)) +#define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN) +#define BIT_SET_NFCPAD_IN(x, v) (BIT_CLEAR_NFCPAD_IN(x) | BIT_NFCPAD_IN(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR2 (Offset 0x10B0) */ + +#define BIT_BCNDMAINT_P4_MSK BIT(31) +#define BIT_BCNDMAINT_P4 BIT(31) +#define BIT_BCNDMAINT_P3_MSK BIT(30) +#define BIT_BCNDMAINT_P3 BIT(30) +#define BIT_BCNDMAINT_P2_MSK BIT(29) +#define BIT_BCNDMAINT_P2 BIT(29) +#define BIT_BCNDMAINT_P1_MSK BIT(28) +#define BIT_BCNDMAINT_P1 BIT(28) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR2 (Offset 0x10B0) */ + +#define BIT_SCH_PHY_TXOP_SIFS_INT_MSK BIT(23) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR2 (Offset 0x10B0) */ + +#define BIT_ATIMEND7_MSK BIT(22) +#define BIT_ATIMEND7 BIT(22) +#define BIT_ATIMEND6_MSK BIT(21) +#define BIT_ATIMEND6 BIT(21) +#define BIT_ATIMEND5_MSK BIT(20) +#define BIT_ATIMEND5 BIT(20) +#define BIT_ATIMEND4_MSK BIT(19) +#define BIT_ATIMEND4 BIT(19) +#define BIT_ATIMEND3_MSK BIT(18) +#define BIT_ATIMEND3 BIT(18) +#define BIT_ATIMEND2_MSK BIT(17) +#define BIT_ATIMEND2 BIT(17) +#define BIT_ATIMEND1_MSK BIT(16) +#define BIT_ATIMEND1 BIT(16) +#define BIT_TXBCN7OK_MSK BIT(14) +#define BIT_TXBCN7OK BIT(14) +#define BIT_TXBCN6OK_MSK BIT(13) +#define BIT_TXBCN6OK BIT(13) +#define BIT_TXBCN5OK_MSK BIT(12) +#define BIT_TXBCN5OK BIT(12) +#define BIT_TXBCN4OK_MSK BIT(11) +#define BIT_TXBCN4OK BIT(11) +#define BIT_TXBCN3OK_MSK BIT(10) +#define BIT_TXBCN3OK BIT(10) +#define BIT_TXBCN2OK_MSK BIT(9) +#define BIT_TXBCN2OK BIT(9) +#define BIT_TXBCN1OK_MSK_V1 BIT(8) +#define BIT_TXBCN1OK BIT(8) +#define BIT_TXBCN7ERR_MSK BIT(6) +#define BIT_TXBCN7ERR BIT(6) +#define BIT_TXBCN6ERR_MSK BIT(5) +#define BIT_TXBCN6ERR BIT(5) +#define BIT_TXBCN5ERR_MSK BIT(4) +#define BIT_TXBCN5ERR BIT(4) +#define BIT_TXBCN4ERR_MSK BIT(3) +#define BIT_TXBCN4ERR BIT(3) +#define BIT_TXBCN3ERR_MSK BIT(2) +#define BIT_TXBCN3ERR BIT(2) +#define BIT_TXBCN2ERR_MSK BIT(1) +#define BIT_TXBCN2ERR BIT(1) +#define BIT_TXBCN1ERR_MSK_V1 BIT(0) +#define BIT_TXBCN1ERR BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_GTINT12 BIT(24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_GTINT12_MSK BIT(24) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_GTINT11 BIT(23) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_GTINT11_MSK BIT(23) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_GTINT10 BIT(22) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_GTINT10_MSK BIT(22) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_GTINT9 BIT(21) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_GTINT9_MSK BIT(21) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_RX_DESC_BUF_FULL BIT(20) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_RX_DESC_BUF_FULL_MSK BIT(20) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_CPHY_LDO_OCP_DET_INT BIT(19) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_CPHY_LDO_OCP_DET_INT_MSK BIT(19) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_WDT_PLATFORM_INT_MSK BIT(18) +#define BIT_WDT_PLATFORM_INT BIT(18) +#define BIT_WDT_CPU_INT_MSK BIT(17) +#define BIT_WDT_CPU_INT BIT(17) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_SETH2CDOK_MASK BIT(16) +#define BIT_SETH2CDOK BIT(16) +#define BIT_H2C_CMD_FULL_MASK BIT(15) +#define BIT_H2C_CMD_FULL BIT(15) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_PWR_INT_127_MASK BIT(14) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_PKT_TRANS_ERR BIT(14) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_PKT_TRANS_ERR_MASK BIT(14) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13) +#define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12) +#define BIT_TXSHORTCUT_BKUPDATEOK BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11) +#define BIT_TXSHORTCUT_BEUPDATEOK BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10) +#define BIT_TXSHORTCUT_VIUPDATEOK BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9) +#define BIT_TXSHORTCUT_VOUPDATEOK BIT(9) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_PWR_INT_127_MASK_V1 BIT(8) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_SEARCH_FAIL BIT(8) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_SEARCH_FAIL_MSK BIT(8) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_PWR_INT_126TO96_MASK BIT(7) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_PWR_INT_127TO96 BIT(7) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_PWR_INT_127TO96_MASK BIT(7) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_PWR_INT_95TO64_MASK BIT(6) +#define BIT_PWR_INT_95TO64 BIT(6) +#define BIT_PWR_INT_63TO32_MASK BIT(5) +#define BIT_PWR_INT_63TO32 BIT(5) +#define BIT_PWR_INT_31TO0_MASK BIT(4) +#define BIT_PWR_INT_31TO0 BIT(4) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_RX_DMA_STUCK_MSK BIT(3) +#define BIT_RX_DMA_STUCK BIT(3) +#define BIT_TX_DMA_STUCK_MSK BIT(2) +#define BIT_TX_DMA_STUCK BIT(2) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_HIMR3 (Offset 0x10B8) */ + +#define BIT_DDMA0_LP_INT_MSK BIT(1) +#define BIT_DDMA0_LP_INT BIT(1) +#define BIT_DDMA0_HP_INT_MSK BIT(0) +#define BIT_DDMA0_HP_INT BIT(0) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_HISR3 (Offset 0x10BC) */ + +#define BIT_PWR_INT_127 BIT(14) +#define BIT_PWR_INT_127_V1 BIT(8) +#define BIT_PWR_INT_126TO96 BIT(7) +#define BIT_ECRC_EN_V1 BIT(7) +#define BIT_MDIO_RFLAG_V1 BIT(6) +#define BIT_MDIO_WFLAG_V1 BIT(5) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_SW_MDIO (Offset 0x10C0) */ + +#define BIT_WLDSS_RST_N_0 BIT(27) +#define BIT_WLDSS_RST_N_1 BIT(27) +#define BIT_WLDSS_RST_N_2 BIT(27) +#define BIT_WLDSS_ENCLK_0 BIT(26) +#define BIT_WLDSS_ENCLK_1 BIT(26) +#define BIT_WLDSS_ENCLK_2 BIT(26) +#define BIT_WLDSS_SPEED_EN_0 BIT(25) +#define BIT_WLDSS_SPEED_EN_1 BIT(25) +#define BIT_WLDSS_SPEED_EN_2 BIT(25) +#define BIT_WLDSS_WIRE_SEL_0 BIT(24) +#define BIT_WLDSS_WIRE_SEL_1 BIT(24) +#define BIT_WLDSS_WIRE_SEL_2 BIT(24) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SW_MDIO (Offset 0x10C0) */ + +#define BIT_DIS_TIMEOUT_IO BIT(24) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_SW_MDIO (Offset 0x10C0) */ + +#define BIT_WLDSS_READY_0 BIT(21) +#define BIT_WLDSS_READY_1 BIT(21) +#define BIT_WLDSS_READY_2 BIT(21) + +#define BIT_SHIFT_WLDSS_RO_SEL_0 20 +#define BIT_MASK_WLDSS_RO_SEL_0 0x7 +#define BIT_WLDSS_RO_SEL_0(x) \ + (((x) & BIT_MASK_WLDSS_RO_SEL_0) << BIT_SHIFT_WLDSS_RO_SEL_0) +#define BITS_WLDSS_RO_SEL_0 \ + (BIT_MASK_WLDSS_RO_SEL_0 << BIT_SHIFT_WLDSS_RO_SEL_0) +#define BIT_CLEAR_WLDSS_RO_SEL_0(x) ((x) & (~BITS_WLDSS_RO_SEL_0)) +#define BIT_GET_WLDSS_RO_SEL_0(x) \ + (((x) >> BIT_SHIFT_WLDSS_RO_SEL_0) & BIT_MASK_WLDSS_RO_SEL_0) +#define BIT_SET_WLDSS_RO_SEL_0(x, v) \ + (BIT_CLEAR_WLDSS_RO_SEL_0(x) | BIT_WLDSS_RO_SEL_0(v)) + +#define BIT_WLDSS_WSORT_GO_0 BIT(20) + +#define BIT_SHIFT_WLDSS_RO_SEL_1 20 +#define BIT_MASK_WLDSS_RO_SEL_1 0x7 +#define BIT_WLDSS_RO_SEL_1(x) \ + (((x) & BIT_MASK_WLDSS_RO_SEL_1) << BIT_SHIFT_WLDSS_RO_SEL_1) +#define BITS_WLDSS_RO_SEL_1 \ + (BIT_MASK_WLDSS_RO_SEL_1 << BIT_SHIFT_WLDSS_RO_SEL_1) +#define BIT_CLEAR_WLDSS_RO_SEL_1(x) ((x) & (~BITS_WLDSS_RO_SEL_1)) +#define BIT_GET_WLDSS_RO_SEL_1(x) \ + (((x) >> BIT_SHIFT_WLDSS_RO_SEL_1) & BIT_MASK_WLDSS_RO_SEL_1) +#define BIT_SET_WLDSS_RO_SEL_1(x, v) \ + (BIT_CLEAR_WLDSS_RO_SEL_1(x) | BIT_WLDSS_RO_SEL_1(v)) + +#define BIT_WLDSS_WSORT_GO_1 BIT(20) + +#define BIT_SHIFT_WLDSS_RO_SEL_2 20 +#define BIT_MASK_WLDSS_RO_SEL_2 0x7 +#define BIT_WLDSS_RO_SEL_2(x) \ + (((x) & BIT_MASK_WLDSS_RO_SEL_2) << BIT_SHIFT_WLDSS_RO_SEL_2) +#define BITS_WLDSS_RO_SEL_2 \ + (BIT_MASK_WLDSS_RO_SEL_2 << BIT_SHIFT_WLDSS_RO_SEL_2) +#define BIT_CLEAR_WLDSS_RO_SEL_2(x) ((x) & (~BITS_WLDSS_RO_SEL_2)) +#define BIT_GET_WLDSS_RO_SEL_2(x) \ + (((x) >> BIT_SHIFT_WLDSS_RO_SEL_2) & BIT_MASK_WLDSS_RO_SEL_2) +#define BIT_SET_WLDSS_RO_SEL_2(x, v) \ + (BIT_CLEAR_WLDSS_RO_SEL_2(x) | BIT_WLDSS_RO_SEL_2(v)) + +#define BIT_WLDSS_WSORT_GO_2 BIT(20) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SW_MDIO (Offset 0x10C0) */ + +#define BIT_SUS_PL BIT(18) +#define BIT_SOP_ESUS BIT(17) +#define BIT_SOP_DLDO BIT(16) +#define BIT_R_OCP_ST_CLR BIT(8) +#define BIT_SW_USB3_MD_SEL BIT(5) +#define BIT_SW_PCIE_MD_SEL BIT(4) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_SW_MDIO (Offset 0x10C0) */ + +#define BIT_SYM_SW_PCIE_MDSL BIT(3) +#define BIT_SYM_SW_PCIE_MDCK BIT(2) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SW_MDIO (Offset 0x10C0) */ + +#define BIT_SW_MDCK BIT(2) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_SW_MDIO (Offset 0x10C0) */ + +#define BIT_SYM_SW_PCIE_MDI BIT(1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SW_MDIO (Offset 0x10C0) */ + +#define BIT_SW_MDI BIT(1) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_SW_MDIO (Offset 0x10C0) */ + +#define BIT_SYM_SW_PCIE_MDO BIT(0) + +#define BIT_SHIFT_WLDSS_DATA_IN_0 0 +#define BIT_MASK_WLDSS_DATA_IN_0 0xfffff +#define BIT_WLDSS_DATA_IN_0(x) \ + (((x) & BIT_MASK_WLDSS_DATA_IN_0) << BIT_SHIFT_WLDSS_DATA_IN_0) +#define BITS_WLDSS_DATA_IN_0 \ + (BIT_MASK_WLDSS_DATA_IN_0 << BIT_SHIFT_WLDSS_DATA_IN_0) +#define BIT_CLEAR_WLDSS_DATA_IN_0(x) ((x) & (~BITS_WLDSS_DATA_IN_0)) +#define BIT_GET_WLDSS_DATA_IN_0(x) \ + (((x) >> BIT_SHIFT_WLDSS_DATA_IN_0) & BIT_MASK_WLDSS_DATA_IN_0) +#define BIT_SET_WLDSS_DATA_IN_0(x, v) \ + (BIT_CLEAR_WLDSS_DATA_IN_0(x) | BIT_WLDSS_DATA_IN_0(v)) + +#define BIT_SHIFT_WLDSS_COUNT_OUT_0 0 +#define BIT_MASK_WLDSS_COUNT_OUT_0 0xfffff +#define BIT_WLDSS_COUNT_OUT_0(x) \ + (((x) & BIT_MASK_WLDSS_COUNT_OUT_0) << BIT_SHIFT_WLDSS_COUNT_OUT_0) +#define BITS_WLDSS_COUNT_OUT_0 \ + (BIT_MASK_WLDSS_COUNT_OUT_0 << BIT_SHIFT_WLDSS_COUNT_OUT_0) +#define BIT_CLEAR_WLDSS_COUNT_OUT_0(x) ((x) & (~BITS_WLDSS_COUNT_OUT_0)) +#define BIT_GET_WLDSS_COUNT_OUT_0(x) \ + (((x) >> BIT_SHIFT_WLDSS_COUNT_OUT_0) & BIT_MASK_WLDSS_COUNT_OUT_0) +#define BIT_SET_WLDSS_COUNT_OUT_0(x, v) \ + (BIT_CLEAR_WLDSS_COUNT_OUT_0(x) | BIT_WLDSS_COUNT_OUT_0(v)) + +#define BIT_SHIFT_WLDSS_DATA_IN_1 0 +#define BIT_MASK_WLDSS_DATA_IN_1 0xfffff +#define BIT_WLDSS_DATA_IN_1(x) \ + (((x) & BIT_MASK_WLDSS_DATA_IN_1) << BIT_SHIFT_WLDSS_DATA_IN_1) +#define BITS_WLDSS_DATA_IN_1 \ + (BIT_MASK_WLDSS_DATA_IN_1 << BIT_SHIFT_WLDSS_DATA_IN_1) +#define BIT_CLEAR_WLDSS_DATA_IN_1(x) ((x) & (~BITS_WLDSS_DATA_IN_1)) +#define BIT_GET_WLDSS_DATA_IN_1(x) \ + (((x) >> BIT_SHIFT_WLDSS_DATA_IN_1) & BIT_MASK_WLDSS_DATA_IN_1) +#define BIT_SET_WLDSS_DATA_IN_1(x, v) \ + (BIT_CLEAR_WLDSS_DATA_IN_1(x) | BIT_WLDSS_DATA_IN_1(v)) + +#define BIT_SHIFT_WLDSS_COUNT_OUT_1 0 +#define BIT_MASK_WLDSS_COUNT_OUT_1 0xfffff +#define BIT_WLDSS_COUNT_OUT_1(x) \ + (((x) & BIT_MASK_WLDSS_COUNT_OUT_1) << BIT_SHIFT_WLDSS_COUNT_OUT_1) +#define BITS_WLDSS_COUNT_OUT_1 \ + (BIT_MASK_WLDSS_COUNT_OUT_1 << BIT_SHIFT_WLDSS_COUNT_OUT_1) +#define BIT_CLEAR_WLDSS_COUNT_OUT_1(x) ((x) & (~BITS_WLDSS_COUNT_OUT_1)) +#define BIT_GET_WLDSS_COUNT_OUT_1(x) \ + (((x) >> BIT_SHIFT_WLDSS_COUNT_OUT_1) & BIT_MASK_WLDSS_COUNT_OUT_1) +#define BIT_SET_WLDSS_COUNT_OUT_1(x, v) \ + (BIT_CLEAR_WLDSS_COUNT_OUT_1(x) | BIT_WLDSS_COUNT_OUT_1(v)) + +#define BIT_SHIFT_WLDSS_DATA_IN_2 0 +#define BIT_MASK_WLDSS_DATA_IN_2 0xfffff +#define BIT_WLDSS_DATA_IN_2(x) \ + (((x) & BIT_MASK_WLDSS_DATA_IN_2) << BIT_SHIFT_WLDSS_DATA_IN_2) +#define BITS_WLDSS_DATA_IN_2 \ + (BIT_MASK_WLDSS_DATA_IN_2 << BIT_SHIFT_WLDSS_DATA_IN_2) +#define BIT_CLEAR_WLDSS_DATA_IN_2(x) ((x) & (~BITS_WLDSS_DATA_IN_2)) +#define BIT_GET_WLDSS_DATA_IN_2(x) \ + (((x) >> BIT_SHIFT_WLDSS_DATA_IN_2) & BIT_MASK_WLDSS_DATA_IN_2) +#define BIT_SET_WLDSS_DATA_IN_2(x, v) \ + (BIT_CLEAR_WLDSS_DATA_IN_2(x) | BIT_WLDSS_DATA_IN_2(v)) + +#define BIT_SHIFT_WLDSS_COUNT_OUT_2 0 +#define BIT_MASK_WLDSS_COUNT_OUT_2 0xfffff +#define BIT_WLDSS_COUNT_OUT_2(x) \ + (((x) & BIT_MASK_WLDSS_COUNT_OUT_2) << BIT_SHIFT_WLDSS_COUNT_OUT_2) +#define BITS_WLDSS_COUNT_OUT_2 \ + (BIT_MASK_WLDSS_COUNT_OUT_2 << BIT_SHIFT_WLDSS_COUNT_OUT_2) +#define BIT_CLEAR_WLDSS_COUNT_OUT_2(x) ((x) & (~BITS_WLDSS_COUNT_OUT_2)) +#define BIT_GET_WLDSS_COUNT_OUT_2(x) \ + (((x) >> BIT_SHIFT_WLDSS_COUNT_OUT_2) & BIT_MASK_WLDSS_COUNT_OUT_2) +#define BIT_SET_WLDSS_COUNT_OUT_2(x, v) \ + (BIT_CLEAR_WLDSS_COUNT_OUT_2(x) | BIT_WLDSS_COUNT_OUT_2(v)) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_SW_MDIO (Offset 0x10C0) */ + +#define BIT_MDO BIT(0) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + +/* 2 REG_SW_FLUSH (Offset 0x10C4) */ + +#define BIT_FLUSH_HOLDN_EN BIT(25) +#define BIT_FLUSH_WR_EN BIT(24) +#define BIT_SW_FLASH_CONTROL BIT(23) +#define BIT_SW_FLASH_WEN_E BIT(19) +#define BIT_SW_FLASH_HOLDN_E BIT(18) +#define BIT_SW_FLASH_SO_E BIT(17) +#define BIT_SW_FLASH_SI_E BIT(16) +#define BIT_SW_FLASH_SK_O BIT(13) +#define BIT_SW_FLASH_CEN_O BIT(12) +#define BIT_SW_FLASH_WEN_O BIT(11) +#define BIT_SW_FLASH_HOLDN_O BIT(10) +#define BIT_SW_FLASH_SO_O BIT(9) +#define BIT_SW_FLASH_SI_O BIT(8) +#define BIT_SW_FLASH_WEN_I BIT(3) +#define BIT_SW_FLASH_HOLDN_I BIT(2) +#define BIT_SW_FLASH_SO_I BIT(1) +#define BIT_SW_FLASH_SI_I BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR_7 (Offset 0x10C8) */ + +#define BIT_DATA_CPU_WDT_INT_MSK BIT(31) +#define BIT_OFLD_TXDMA_ERR_MSK BIT(30) +#define BIT_OFLD_TXDMA_FULL_MSK BIT(29) +#define BIT_OFLD_RXDMA_OVR_MSK BIT(28) +#define BIT_OFLD_RXDMA_ERR_MSK BIT(27) +#define BIT_OFLD_RXDMA_DES_UA_MSK BIT(26) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ + +#define BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR 24 +#define BIT_MASK_WL_DSS_CLKEN_BACKDOOR 0x3 +#define BIT_WL_DSS_CLKEN_BACKDOOR(x) \ + (((x) & BIT_MASK_WL_DSS_CLKEN_BACKDOOR) \ + << BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR) +#define BITS_WL_DSS_CLKEN_BACKDOOR \ + (BIT_MASK_WL_DSS_CLKEN_BACKDOOR << BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR) +#define BIT_CLEAR_WL_DSS_CLKEN_BACKDOOR(x) ((x) & (~BITS_WL_DSS_CLKEN_BACKDOOR)) +#define BIT_GET_WL_DSS_CLKEN_BACKDOOR(x) \ + (((x) >> BIT_SHIFT_WL_DSS_CLKEN_BACKDOOR) & \ + BIT_MASK_WL_DSS_CLKEN_BACKDOOR) +#define BIT_SET_WL_DSS_CLKEN_BACKDOOR(x, v) \ + (BIT_CLEAR_WL_DSS_CLKEN_BACKDOOR(x) | BIT_WL_DSS_CLKEN_BACKDOOR(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ + +#define BIT_SHIFT_DBG_GPIO_BMUX_7 21 +#define BIT_MASK_DBG_GPIO_BMUX_7 0x7 +#define BIT_DBG_GPIO_BMUX_7(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_7) << BIT_SHIFT_DBG_GPIO_BMUX_7) +#define BITS_DBG_GPIO_BMUX_7 \ + (BIT_MASK_DBG_GPIO_BMUX_7 << BIT_SHIFT_DBG_GPIO_BMUX_7) +#define BIT_CLEAR_DBG_GPIO_BMUX_7(x) ((x) & (~BITS_DBG_GPIO_BMUX_7)) +#define BIT_GET_DBG_GPIO_BMUX_7(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7) & BIT_MASK_DBG_GPIO_BMUX_7) +#define BIT_SET_DBG_GPIO_BMUX_7(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_7(x) | BIT_DBG_GPIO_BMUX_7(v)) + +#define BIT_SHIFT_DBG_GPIO_BMUX_6 18 +#define BIT_MASK_DBG_GPIO_BMUX_6 0x7 +#define BIT_DBG_GPIO_BMUX_6(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_6) << BIT_SHIFT_DBG_GPIO_BMUX_6) +#define BITS_DBG_GPIO_BMUX_6 \ + (BIT_MASK_DBG_GPIO_BMUX_6 << BIT_SHIFT_DBG_GPIO_BMUX_6) +#define BIT_CLEAR_DBG_GPIO_BMUX_6(x) ((x) & (~BITS_DBG_GPIO_BMUX_6)) +#define BIT_GET_DBG_GPIO_BMUX_6(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6) & BIT_MASK_DBG_GPIO_BMUX_6) +#define BIT_SET_DBG_GPIO_BMUX_6(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_6(x) | BIT_DBG_GPIO_BMUX_6(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR_7 (Offset 0x10C8) */ + +#define BIT_TXDMAOK_CHANNEL_16_MSK BIT(16) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ + +#define BIT_SHIFT_DBG_GPIO_BMUX_5 15 +#define BIT_MASK_DBG_GPIO_BMUX_5 0x7 +#define BIT_DBG_GPIO_BMUX_5(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_5) << BIT_SHIFT_DBG_GPIO_BMUX_5) +#define BITS_DBG_GPIO_BMUX_5 \ + (BIT_MASK_DBG_GPIO_BMUX_5 << BIT_SHIFT_DBG_GPIO_BMUX_5) +#define BIT_CLEAR_DBG_GPIO_BMUX_5(x) ((x) & (~BITS_DBG_GPIO_BMUX_5)) +#define BIT_GET_DBG_GPIO_BMUX_5(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5) & BIT_MASK_DBG_GPIO_BMUX_5) +#define BIT_SET_DBG_GPIO_BMUX_5(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_5(x) | BIT_DBG_GPIO_BMUX_5(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR_7 (Offset 0x10C8) */ + +#define BIT_TXDMAOK_CHANNEL_13_MSK BIT(13) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ + +#define BIT_SHIFT_DBG_GPIO_BMUX_4 12 +#define BIT_MASK_DBG_GPIO_BMUX_4 0x7 +#define BIT_DBG_GPIO_BMUX_4(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_4) << BIT_SHIFT_DBG_GPIO_BMUX_4) +#define BITS_DBG_GPIO_BMUX_4 \ + (BIT_MASK_DBG_GPIO_BMUX_4 << BIT_SHIFT_DBG_GPIO_BMUX_4) +#define BIT_CLEAR_DBG_GPIO_BMUX_4(x) ((x) & (~BITS_DBG_GPIO_BMUX_4)) +#define BIT_GET_DBG_GPIO_BMUX_4(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4) & BIT_MASK_DBG_GPIO_BMUX_4) +#define BIT_SET_DBG_GPIO_BMUX_4(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_4(x) | BIT_DBG_GPIO_BMUX_4(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR_7 (Offset 0x10C8) */ + +#define BIT_TXDMAOK_CHANNEL_12_MSK BIT(12) +#define BIT_TXDMAOK_CHANNEL_11_MSK BIT(11) +#define BIT_TXDMAOK_CHANNEL_10_MSK BIT(10) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ + +#define BIT_SHIFT_DBG_GPIO_BMUX_3 9 +#define BIT_MASK_DBG_GPIO_BMUX_3 0x7 +#define BIT_DBG_GPIO_BMUX_3(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_3) << BIT_SHIFT_DBG_GPIO_BMUX_3) +#define BITS_DBG_GPIO_BMUX_3 \ + (BIT_MASK_DBG_GPIO_BMUX_3 << BIT_SHIFT_DBG_GPIO_BMUX_3) +#define BIT_CLEAR_DBG_GPIO_BMUX_3(x) ((x) & (~BITS_DBG_GPIO_BMUX_3)) +#define BIT_GET_DBG_GPIO_BMUX_3(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3) & BIT_MASK_DBG_GPIO_BMUX_3) +#define BIT_SET_DBG_GPIO_BMUX_3(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_3(x) | BIT_DBG_GPIO_BMUX_3(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR_7 (Offset 0x10C8) */ + +#define BIT_TXDMAOK_CHANNEL_9_MSK BIT(9) +#define BIT_TXDMAOK_CHANNEL_8_MSK BIT(8) +#define BIT_TXDMAOK_CHANNEL_7_MSK BIT(7) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ + +#define BIT_SHIFT_DBG_GPIO_BMUX_2 6 +#define BIT_MASK_DBG_GPIO_BMUX_2 0x7 +#define BIT_DBG_GPIO_BMUX_2(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_2) << BIT_SHIFT_DBG_GPIO_BMUX_2) +#define BITS_DBG_GPIO_BMUX_2 \ + (BIT_MASK_DBG_GPIO_BMUX_2 << BIT_SHIFT_DBG_GPIO_BMUX_2) +#define BIT_CLEAR_DBG_GPIO_BMUX_2(x) ((x) & (~BITS_DBG_GPIO_BMUX_2)) +#define BIT_GET_DBG_GPIO_BMUX_2(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2) & BIT_MASK_DBG_GPIO_BMUX_2) +#define BIT_SET_DBG_GPIO_BMUX_2(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_2(x) | BIT_DBG_GPIO_BMUX_2(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIMR_7 (Offset 0x10C8) */ + +#define BIT_TXDMAOK_CHANNEL_6_MSK BIT(6) +#define BIT_TXDMAOK_CHANNEL_5_MSK BIT(5) +#define BIT_TXDMAOK_CHANNEL_4_MSK BIT(4) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */ + +#define BIT_SHIFT_DBG_GPIO_BMUX_1 3 +#define BIT_MASK_DBG_GPIO_BMUX_1 0x7 +#define BIT_DBG_GPIO_BMUX_1(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_1) << BIT_SHIFT_DBG_GPIO_BMUX_1) +#define BITS_DBG_GPIO_BMUX_1 \ + (BIT_MASK_DBG_GPIO_BMUX_1 << BIT_SHIFT_DBG_GPIO_BMUX_1) +#define BIT_CLEAR_DBG_GPIO_BMUX_1(x) ((x) & (~BITS_DBG_GPIO_BMUX_1)) +#define BIT_GET_DBG_GPIO_BMUX_1(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1) & BIT_MASK_DBG_GPIO_BMUX_1) +#define BIT_SET_DBG_GPIO_BMUX_1(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_1(x) | BIT_DBG_GPIO_BMUX_1(v)) + +#define BIT_SHIFT_DBG_GPIO_BMUX_0 0 +#define BIT_MASK_DBG_GPIO_BMUX_0 0x7 +#define BIT_DBG_GPIO_BMUX_0(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_0) << BIT_SHIFT_DBG_GPIO_BMUX_0) +#define BITS_DBG_GPIO_BMUX_0 \ + (BIT_MASK_DBG_GPIO_BMUX_0 << BIT_SHIFT_DBG_GPIO_BMUX_0) +#define BIT_CLEAR_DBG_GPIO_BMUX_0(x) ((x) & (~BITS_DBG_GPIO_BMUX_0)) +#define BIT_GET_DBG_GPIO_BMUX_0(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0) & BIT_MASK_DBG_GPIO_BMUX_0) +#define BIT_SET_DBG_GPIO_BMUX_0(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_0(x) | BIT_DBG_GPIO_BMUX_0(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HISR_7 (Offset 0x10CC) */ + +#define BIT_DATA_CPU_WDT_INT BIT(31) +#define BIT_OFLD_TXDMA_ERR BIT(30) +#define BIT_OFLD_TXDMA_FULL BIT(29) +#define BIT_OFLD_RXDMA_OVR BIT(28) +#define BIT_OFLD_RXDMA_ERR BIT(27) +#define BIT_OFLD_RXDMA_DES_UA BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FPGA_TAG (Offset 0x10CC) */ + +#define BIT_WL_DSS_SPEED_EN BIT(25) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HISR_7 (Offset 0x10CC) */ + +#define BIT_TXDMAOK_CHANNEL_16 BIT(16) +#define BIT_TXDMAOK_CHANNEL_13 BIT(13) +#define BIT_TXDMAOK_CHANNEL_12 BIT(12) +#define BIT_TXDMAOK_CHANNEL_11 BIT(11) +#define BIT_TXDMAOK_CHANNEL_10 BIT(10) +#define BIT_TXDMAOK_CHANNEL_9 BIT(9) +#define BIT_TXDMAOK_CHANNEL_8 BIT(8) +#define BIT_TXDMAOK_CHANNEL_7 BIT(7) +#define BIT_TXDMAOK_CHANNEL_6 BIT(6) +#define BIT_TXDMAOK_CHANNEL_5 BIT(5) +#define BIT_TXDMAOK_CHANNEL_4 BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FPGA_TAG (Offset 0x10CC) */ + +#define BIT_SHIFT_FPGA_TAG 0 +#define BIT_MASK_FPGA_TAG 0xffffffffL +#define BIT_FPGA_TAG(x) (((x) & BIT_MASK_FPGA_TAG) << BIT_SHIFT_FPGA_TAG) +#define BITS_FPGA_TAG (BIT_MASK_FPGA_TAG << BIT_SHIFT_FPGA_TAG) +#define BIT_CLEAR_FPGA_TAG(x) ((x) & (~BITS_FPGA_TAG)) +#define BIT_GET_FPGA_TAG(x) (((x) >> BIT_SHIFT_FPGA_TAG) & BIT_MASK_FPGA_TAG) +#define BIT_SET_FPGA_TAG(x, v) (BIT_CLEAR_FPGA_TAG(x) | BIT_FPGA_TAG(v)) + +#define BIT_SHIFT_WL_DSS_COUNT_OUT 0 +#define BIT_MASK_WL_DSS_COUNT_OUT 0xfffff +#define BIT_WL_DSS_COUNT_OUT(x) \ + (((x) & BIT_MASK_WL_DSS_COUNT_OUT) << BIT_SHIFT_WL_DSS_COUNT_OUT) +#define BITS_WL_DSS_COUNT_OUT \ + (BIT_MASK_WL_DSS_COUNT_OUT << BIT_SHIFT_WL_DSS_COUNT_OUT) +#define BIT_CLEAR_WL_DSS_COUNT_OUT(x) ((x) & (~BITS_WL_DSS_COUNT_OUT)) +#define BIT_GET_WL_DSS_COUNT_OUT(x) \ + (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT) & BIT_MASK_WL_DSS_COUNT_OUT) +#define BIT_SET_WL_DSS_COUNT_OUT(x, v) \ + (BIT_CLEAR_WL_DSS_COUNT_OUT(x) | BIT_WL_DSS_COUNT_OUT(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_WL_DSS_CTRL0 (Offset 0x10D0) */ + +#define BIT_SHIFT_WL_DSS_DBG0_5_0 26 +#define BIT_MASK_WL_DSS_DBG0_5_0 0x3f +#define BIT_WL_DSS_DBG0_5_0(x) \ + (((x) & BIT_MASK_WL_DSS_DBG0_5_0) << BIT_SHIFT_WL_DSS_DBG0_5_0) +#define BITS_WL_DSS_DBG0_5_0 \ + (BIT_MASK_WL_DSS_DBG0_5_0 << BIT_SHIFT_WL_DSS_DBG0_5_0) +#define BIT_CLEAR_WL_DSS_DBG0_5_0(x) ((x) & (~BITS_WL_DSS_DBG0_5_0)) +#define BIT_GET_WL_DSS_DBG0_5_0(x) \ + (((x) >> BIT_SHIFT_WL_DSS_DBG0_5_0) & BIT_MASK_WL_DSS_DBG0_5_0) +#define BIT_SET_WL_DSS_DBG0_5_0(x, v) \ + (BIT_CLEAR_WL_DSS_DBG0_5_0(x) | BIT_WL_DSS_DBG0_5_0(v)) + +#define BIT_SHIFT_WL_DSS_DATA_IN_V1 5 +#define BIT_MASK_WL_DSS_DATA_IN_V1 0xfffff +#define BIT_WL_DSS_DATA_IN_V1(x) \ + (((x) & BIT_MASK_WL_DSS_DATA_IN_V1) << BIT_SHIFT_WL_DSS_DATA_IN_V1) +#define BITS_WL_DSS_DATA_IN_V1 \ + (BIT_MASK_WL_DSS_DATA_IN_V1 << BIT_SHIFT_WL_DSS_DATA_IN_V1) +#define BIT_CLEAR_WL_DSS_DATA_IN_V1(x) ((x) & (~BITS_WL_DSS_DATA_IN_V1)) +#define BIT_GET_WL_DSS_DATA_IN_V1(x) \ + (((x) >> BIT_SHIFT_WL_DSS_DATA_IN_V1) & BIT_MASK_WL_DSS_DATA_IN_V1) +#define BIT_SET_WL_DSS_DATA_IN_V1(x, v) \ + (BIT_CLEAR_WL_DSS_DATA_IN_V1(x) | BIT_WL_DSS_DATA_IN_V1(v)) + +#define BIT_WL_DSS_WIRE_SEL_V1 BIT(4) + +#define BIT_SHIFT_WL_DSS_RO_SEL_V1 1 +#define BIT_MASK_WL_DSS_RO_SEL_V1 0x7 +#define BIT_WL_DSS_RO_SEL_V1(x) \ + (((x) & BIT_MASK_WL_DSS_RO_SEL_V1) << BIT_SHIFT_WL_DSS_RO_SEL_V1) +#define BITS_WL_DSS_RO_SEL_V1 \ + (BIT_MASK_WL_DSS_RO_SEL_V1 << BIT_SHIFT_WL_DSS_RO_SEL_V1) +#define BIT_CLEAR_WL_DSS_RO_SEL_V1(x) ((x) & (~BITS_WL_DSS_RO_SEL_V1)) +#define BIT_GET_WL_DSS_RO_SEL_V1(x) \ + (((x) >> BIT_SHIFT_WL_DSS_RO_SEL_V1) & BIT_MASK_WL_DSS_RO_SEL_V1) +#define BIT_SET_WL_DSS_RO_SEL_V1(x, v) \ + (BIT_CLEAR_WL_DSS_RO_SEL_V1(x) | BIT_WL_DSS_RO_SEL_V1(v)) + +#define BIT_WL_DSS_RSTN_V1 BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_H2C_PKT_READADDR (Offset 0x10D0) */ + +#define BIT_SHIFT_H2C_PKT_READADDR 0 +#define BIT_MASK_H2C_PKT_READADDR 0x3ffff +#define BIT_H2C_PKT_READADDR(x) \ + (((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR) +#define BITS_H2C_PKT_READADDR \ + (BIT_MASK_H2C_PKT_READADDR << BIT_SHIFT_H2C_PKT_READADDR) +#define BIT_CLEAR_H2C_PKT_READADDR(x) ((x) & (~BITS_H2C_PKT_READADDR)) +#define BIT_GET_H2C_PKT_READADDR(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR) +#define BIT_SET_H2C_PKT_READADDR(x, v) \ + (BIT_CLEAR_H2C_PKT_READADDR(x) | BIT_H2C_PKT_READADDR(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_WL_DSS_STATUS0 (Offset 0x10D4) */ + +#define BIT_SHIFT_WL_DSS_DBG0_15_6 22 +#define BIT_MASK_WL_DSS_DBG0_15_6 0x3ff +#define BIT_WL_DSS_DBG0_15_6(x) \ + (((x) & BIT_MASK_WL_DSS_DBG0_15_6) << BIT_SHIFT_WL_DSS_DBG0_15_6) +#define BITS_WL_DSS_DBG0_15_6 \ + (BIT_MASK_WL_DSS_DBG0_15_6 << BIT_SHIFT_WL_DSS_DBG0_15_6) +#define BIT_CLEAR_WL_DSS_DBG0_15_6(x) ((x) & (~BITS_WL_DSS_DBG0_15_6)) +#define BIT_GET_WL_DSS_DBG0_15_6(x) \ + (((x) >> BIT_SHIFT_WL_DSS_DBG0_15_6) & BIT_MASK_WL_DSS_DBG0_15_6) +#define BIT_SET_WL_DSS_DBG0_15_6(x, v) \ + (BIT_CLEAR_WL_DSS_DBG0_15_6(x) | BIT_WL_DSS_DBG0_15_6(v)) + +#define BIT_WL_DSS_WSORT_GO_V1 BIT(21) +#define BIT_WL_DSS_READY_V1 BIT(20) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_H2C_PKT_WRITEADDR (Offset 0x10D4) */ + +#define BIT_SHIFT_H2C_PKT_WRITEADDR 0 +#define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff +#define BIT_H2C_PKT_WRITEADDR(x) \ + (((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR) +#define BITS_H2C_PKT_WRITEADDR \ + (BIT_MASK_H2C_PKT_WRITEADDR << BIT_SHIFT_H2C_PKT_WRITEADDR) +#define BIT_CLEAR_H2C_PKT_WRITEADDR(x) ((x) & (~BITS_H2C_PKT_WRITEADDR)) +#define BIT_GET_H2C_PKT_WRITEADDR(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR) +#define BIT_SET_H2C_PKT_WRITEADDR(x, v) \ + (BIT_CLEAR_H2C_PKT_WRITEADDR(x) | BIT_H2C_PKT_WRITEADDR(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ + +#define BIT_SHIFT_WL_DSS_DBG1_5_0 26 +#define BIT_MASK_WL_DSS_DBG1_5_0 0x3f +#define BIT_WL_DSS_DBG1_5_0(x) \ + (((x) & BIT_MASK_WL_DSS_DBG1_5_0) << BIT_SHIFT_WL_DSS_DBG1_5_0) +#define BITS_WL_DSS_DBG1_5_0 \ + (BIT_MASK_WL_DSS_DBG1_5_0 << BIT_SHIFT_WL_DSS_DBG1_5_0) +#define BIT_CLEAR_WL_DSS_DBG1_5_0(x) ((x) & (~BITS_WL_DSS_DBG1_5_0)) +#define BIT_GET_WL_DSS_DBG1_5_0(x) \ + (((x) >> BIT_SHIFT_WL_DSS_DBG1_5_0) & BIT_MASK_WL_DSS_DBG1_5_0) +#define BIT_SET_WL_DSS_DBG1_5_0(x, v) \ + (BIT_CLEAR_WL_DSS_DBG1_5_0(x) | BIT_WL_DSS_DBG1_5_0(v)) + +#define BIT_WL_DSS_SPEED_EN1 BIT(25) + +#endif + +#if (HALMAC_8197F_SUPPORT) + +/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ + +#define BIT_WL_DSS_WIRE_SEL BIT(24) + +#define BIT_SHIFT_WL_DSS_RO_SEL 20 +#define BIT_MASK_WL_DSS_RO_SEL 0x7 +#define BIT_WL_DSS_RO_SEL(x) \ + (((x) & BIT_MASK_WL_DSS_RO_SEL) << BIT_SHIFT_WL_DSS_RO_SEL) +#define BITS_WL_DSS_RO_SEL (BIT_MASK_WL_DSS_RO_SEL << BIT_SHIFT_WL_DSS_RO_SEL) +#define BIT_CLEAR_WL_DSS_RO_SEL(x) ((x) & (~BITS_WL_DSS_RO_SEL)) +#define BIT_GET_WL_DSS_RO_SEL(x) \ + (((x) >> BIT_SHIFT_WL_DSS_RO_SEL) & BIT_MASK_WL_DSS_RO_SEL) +#define BIT_SET_WL_DSS_RO_SEL(x, v) \ + (BIT_CLEAR_WL_DSS_RO_SEL(x) | BIT_WL_DSS_RO_SEL(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ + +#define BIT_MEM_BB_SD BIT(17) +#define BIT_MEM_BB_DS BIT(16) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ + +#define BIT_MEM_DENG_LS BIT(13) +#define BIT_MEM_DENG_DS BIT(12) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ + +#define BIT_MEM_BT_DS BIT(10) +#define BIT_MEM_SDIO_LS BIT(9) +#define BIT_MEM_SDIO_DS BIT(8) +#define BIT_MEM_USB_LS BIT(7) +#define BIT_MEM_USB_DS BIT(6) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ + +#define BIT_SHIFT_WL_DSS_DATA_IN1 5 +#define BIT_MASK_WL_DSS_DATA_IN1 0xfffff +#define BIT_WL_DSS_DATA_IN1(x) \ + (((x) & BIT_MASK_WL_DSS_DATA_IN1) << BIT_SHIFT_WL_DSS_DATA_IN1) +#define BITS_WL_DSS_DATA_IN1 \ + (BIT_MASK_WL_DSS_DATA_IN1 << BIT_SHIFT_WL_DSS_DATA_IN1) +#define BIT_CLEAR_WL_DSS_DATA_IN1(x) ((x) & (~BITS_WL_DSS_DATA_IN1)) +#define BIT_GET_WL_DSS_DATA_IN1(x) \ + (((x) >> BIT_SHIFT_WL_DSS_DATA_IN1) & BIT_MASK_WL_DSS_DATA_IN1) +#define BIT_SET_WL_DSS_DATA_IN1(x, v) \ + (BIT_CLEAR_WL_DSS_DATA_IN1(x) | BIT_WL_DSS_DATA_IN1(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ + +#define BIT_MEM_PCI_LS BIT(5) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ + +#define BIT_WL_DSS_WIRE_SEL1 BIT(4) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ + +#define BIT_MEM_PCI_DS BIT(4) +#define BIT_MEM_WLMAC_LS BIT(3) +#define BIT_MEM_WLMAC_DS BIT(2) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ + +#define BIT_SHIFT_WL_DSS_RO_SEL1 1 +#define BIT_MASK_WL_DSS_RO_SEL1 0x7 +#define BIT_WL_DSS_RO_SEL1(x) \ + (((x) & BIT_MASK_WL_DSS_RO_SEL1) << BIT_SHIFT_WL_DSS_RO_SEL1) +#define BITS_WL_DSS_RO_SEL1 \ + (BIT_MASK_WL_DSS_RO_SEL1 << BIT_SHIFT_WL_DSS_RO_SEL1) +#define BIT_CLEAR_WL_DSS_RO_SEL1(x) ((x) & (~BITS_WL_DSS_RO_SEL1)) +#define BIT_GET_WL_DSS_RO_SEL1(x) \ + (((x) >> BIT_SHIFT_WL_DSS_RO_SEL1) & BIT_MASK_WL_DSS_RO_SEL1) +#define BIT_SET_WL_DSS_RO_SEL1(x, v) \ + (BIT_CLEAR_WL_DSS_RO_SEL1(x) | BIT_WL_DSS_RO_SEL1(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ + +#define BIT_MEM_WLMCU_LS BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT) + +/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ + +#define BIT_SHIFT_WL_DSS_DATA_IN 0 +#define BIT_MASK_WL_DSS_DATA_IN 0xfffff +#define BIT_WL_DSS_DATA_IN(x) \ + (((x) & BIT_MASK_WL_DSS_DATA_IN) << BIT_SHIFT_WL_DSS_DATA_IN) +#define BITS_WL_DSS_DATA_IN \ + (BIT_MASK_WL_DSS_DATA_IN << BIT_SHIFT_WL_DSS_DATA_IN) +#define BIT_CLEAR_WL_DSS_DATA_IN(x) ((x) & (~BITS_WL_DSS_DATA_IN)) +#define BIT_GET_WL_DSS_DATA_IN(x) \ + (((x) >> BIT_SHIFT_WL_DSS_DATA_IN) & BIT_MASK_WL_DSS_DATA_IN) +#define BIT_SET_WL_DSS_DATA_IN(x, v) \ + (BIT_CLEAR_WL_DSS_DATA_IN(x) | BIT_WL_DSS_DATA_IN(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */ + +#define BIT_WL_DSS_RSTN1 BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ + +#define BIT_MEM_WLMCU_DS BIT(0) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_WL_DSS_STATUS1 (Offset 0x10DC) */ + +#define BIT_SHIFT_WL_DSS_DBG1_15_6 22 +#define BIT_MASK_WL_DSS_DBG1_15_6 0x3ff +#define BIT_WL_DSS_DBG1_15_6(x) \ + (((x) & BIT_MASK_WL_DSS_DBG1_15_6) << BIT_SHIFT_WL_DSS_DBG1_15_6) +#define BITS_WL_DSS_DBG1_15_6 \ + (BIT_MASK_WL_DSS_DBG1_15_6 << BIT_SHIFT_WL_DSS_DBG1_15_6) +#define BIT_CLEAR_WL_DSS_DBG1_15_6(x) ((x) & (~BITS_WL_DSS_DBG1_15_6)) +#define BIT_GET_WL_DSS_DBG1_15_6(x) \ + (((x) >> BIT_SHIFT_WL_DSS_DBG1_15_6) & BIT_MASK_WL_DSS_DBG1_15_6) +#define BIT_SET_WL_DSS_DBG1_15_6(x, v) \ + (BIT_CLEAR_WL_DSS_DBG1_15_6(x) | BIT_WL_DSS_DBG1_15_6(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT) + +/* 2 REG_WL_DSS_STATUS1 (Offset 0x10DC) */ + +#define BIT_WL_DSS_READY BIT(21) +#define BIT_WL_DSS_WSORT_GO BIT(20) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FW_DRV_HANDSHAKE (Offset 0x10DC) */ + +#define BIT_SHIFT_FW_DRV_HANDSHAKE 0 +#define BIT_MASK_FW_DRV_HANDSHAKE 0xffffffffL +#define BIT_FW_DRV_HANDSHAKE(x) \ + (((x) & BIT_MASK_FW_DRV_HANDSHAKE) << BIT_SHIFT_FW_DRV_HANDSHAKE) +#define BITS_FW_DRV_HANDSHAKE \ + (BIT_MASK_FW_DRV_HANDSHAKE << BIT_SHIFT_FW_DRV_HANDSHAKE) +#define BIT_CLEAR_FW_DRV_HANDSHAKE(x) ((x) & (~BITS_FW_DRV_HANDSHAKE)) +#define BIT_GET_FW_DRV_HANDSHAKE(x) \ + (((x) >> BIT_SHIFT_FW_DRV_HANDSHAKE) & BIT_MASK_FW_DRV_HANDSHAKE) +#define BIT_SET_FW_DRV_HANDSHAKE(x, v) \ + (BIT_CLEAR_FW_DRV_HANDSHAKE(x) | BIT_FW_DRV_HANDSHAKE(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) + +/* 2 REG_FW_DBG0 (Offset 0x10E0) */ + +#define BIT_SHIFT_FW_DBG0 0 +#define BIT_MASK_FW_DBG0 0xffffffffL +#define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0) +#define BITS_FW_DBG0 (BIT_MASK_FW_DBG0 << BIT_SHIFT_FW_DBG0) +#define BIT_CLEAR_FW_DBG0(x) ((x) & (~BITS_FW_DBG0)) +#define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0) +#define BIT_SET_FW_DBG0(x, v) (BIT_CLEAR_FW_DBG0(x) | BIT_FW_DBG0(v)) + +/* 2 REG_FW_DBG1 (Offset 0x10E4) */ + +#define BIT_SHIFT_FW_DBG1 0 +#define BIT_MASK_FW_DBG1 0xffffffffL +#define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1) +#define BITS_FW_DBG1 (BIT_MASK_FW_DBG1 << BIT_SHIFT_FW_DBG1) +#define BIT_CLEAR_FW_DBG1(x) ((x) & (~BITS_FW_DBG1)) +#define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1) +#define BIT_SET_FW_DBG1(x, v) (BIT_CLEAR_FW_DBG1(x) | BIT_FW_DBG1(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822B_SUPPORT) + +/* 2 REG_FW_DBG2 (Offset 0x10E8) */ + +#define BIT_SHIFT_FW_DBG2 0 +#define BIT_MASK_FW_DBG2 0xffffffffL +#define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2) +#define BITS_FW_DBG2 (BIT_MASK_FW_DBG2 << BIT_SHIFT_FW_DBG2) +#define BIT_CLEAR_FW_DBG2(x) ((x) & (~BITS_FW_DBG2)) +#define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2) +#define BIT_SET_FW_DBG2(x, v) (BIT_CLEAR_FW_DBG2(x) | BIT_FW_DBG2(v)) + +/* 2 REG_FW_DBG3 (Offset 0x10EC) */ + +#define BIT_SHIFT_FW_DBG3 0 +#define BIT_MASK_FW_DBG3 0xffffffffL +#define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3) +#define BITS_FW_DBG3 (BIT_MASK_FW_DBG3 << BIT_SHIFT_FW_DBG3) +#define BIT_CLEAR_FW_DBG3(x) ((x) & (~BITS_FW_DBG3)) +#define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3) +#define BIT_SET_FW_DBG3(x, v) (BIT_CLEAR_FW_DBG3(x) | BIT_FW_DBG3(v)) + +/* 2 REG_FW_DBG4 (Offset 0x10F0) */ + +#define BIT_SHIFT_FW_DBG4 0 +#define BIT_MASK_FW_DBG4 0xffffffffL +#define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4) +#define BITS_FW_DBG4 (BIT_MASK_FW_DBG4 << BIT_SHIFT_FW_DBG4) +#define BIT_CLEAR_FW_DBG4(x) ((x) & (~BITS_FW_DBG4)) +#define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4) +#define BIT_SET_FW_DBG4(x, v) (BIT_CLEAR_FW_DBG4(x) | BIT_FW_DBG4(v)) + +/* 2 REG_FW_DBG5 (Offset 0x10F4) */ + +#define BIT_SHIFT_FW_DBG5 0 +#define BIT_MASK_FW_DBG5 0xffffffffL +#define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5) +#define BITS_FW_DBG5 (BIT_MASK_FW_DBG5 << BIT_SHIFT_FW_DBG5) +#define BIT_CLEAR_FW_DBG5(x) ((x) & (~BITS_FW_DBG5)) +#define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5) +#define BIT_SET_FW_DBG5(x, v) (BIT_CLEAR_FW_DBG5(x) | BIT_FW_DBG5(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FW_DBG6 (Offset 0x10F8) */ + +#define BIT_SHIFT_FW_DBG6 0 +#define BIT_MASK_FW_DBG6 0xffffffffL +#define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6) +#define BITS_FW_DBG6 (BIT_MASK_FW_DBG6 << BIT_SHIFT_FW_DBG6) +#define BIT_CLEAR_FW_DBG6(x) ((x) & (~BITS_FW_DBG6)) +#define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6) +#define BIT_SET_FW_DBG6(x, v) (BIT_CLEAR_FW_DBG6(x) | BIT_FW_DBG6(v)) + +/* 2 REG_FW_DBG7 (Offset 0x10FC) */ + +#define BIT_SHIFT_FW_DBG7 0 +#define BIT_MASK_FW_DBG7 0xffffffffL +#define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7) +#define BITS_FW_DBG7 (BIT_MASK_FW_DBG7 << BIT_SHIFT_FW_DBG7) +#define BIT_CLEAR_FW_DBG7(x) ((x) & (~BITS_FW_DBG7)) +#define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7) +#define BIT_SET_FW_DBG7(x, v) (BIT_CLEAR_FW_DBG7(x) | BIT_FW_DBG7(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CR_EXT (Offset 0x1100) */ + +#define BIT_SHIFT_PHY_REQ_DELAY 24 +#define BIT_MASK_PHY_REQ_DELAY 0xf +#define BIT_PHY_REQ_DELAY(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY) +#define BITS_PHY_REQ_DELAY (BIT_MASK_PHY_REQ_DELAY << BIT_SHIFT_PHY_REQ_DELAY) +#define BIT_CLEAR_PHY_REQ_DELAY(x) ((x) & (~BITS_PHY_REQ_DELAY)) +#define BIT_GET_PHY_REQ_DELAY(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY) +#define BIT_SET_PHY_REQ_DELAY(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY(x) | BIT_PHY_REQ_DELAY(v)) + +#define BIT_SPD_DOWN BIT(16) + +#define BIT_SHIFT_NETYPE4 4 +#define BIT_MASK_NETYPE4 0x3 +#define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4) +#define BITS_NETYPE4 (BIT_MASK_NETYPE4 << BIT_SHIFT_NETYPE4) +#define BIT_CLEAR_NETYPE4(x) ((x) & (~BITS_NETYPE4)) +#define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4) +#define BIT_SET_NETYPE4(x, v) (BIT_CLEAR_NETYPE4(x) | BIT_NETYPE4(v)) + +#define BIT_SHIFT_NETYPE3 2 +#define BIT_MASK_NETYPE3 0x3 +#define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3) +#define BITS_NETYPE3 (BIT_MASK_NETYPE3 << BIT_SHIFT_NETYPE3) +#define BIT_CLEAR_NETYPE3(x) ((x) & (~BITS_NETYPE3)) +#define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3) +#define BIT_SET_NETYPE3(x, v) (BIT_CLEAR_NETYPE3(x) | BIT_NETYPE3(v)) + +#define BIT_SHIFT_NETYPE2 0 +#define BIT_MASK_NETYPE2 0x3 +#define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2) +#define BITS_NETYPE2 (BIT_MASK_NETYPE2 << BIT_SHIFT_NETYPE2) +#define BIT_CLEAR_NETYPE2(x) ((x) & (~BITS_NETYPE2)) +#define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2) +#define BIT_SET_NETYPE2(x, v) (BIT_CLEAR_NETYPE2(x) | BIT_NETYPE2(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_TC9_CTRL (Offset 0x1104) */ + +#define BIT_TC9INT_EN BIT(26) +#define BIT_TC9MODE BIT(25) +#define BIT_TC9EN BIT(24) + +#define BIT_SHIFT_TC9DATA 0 +#define BIT_MASK_TC9DATA 0xffffff +#define BIT_TC9DATA(x) (((x) & BIT_MASK_TC9DATA) << BIT_SHIFT_TC9DATA) +#define BITS_TC9DATA (BIT_MASK_TC9DATA << BIT_SHIFT_TC9DATA) +#define BIT_CLEAR_TC9DATA(x) ((x) & (~BITS_TC9DATA)) +#define BIT_GET_TC9DATA(x) (((x) >> BIT_SHIFT_TC9DATA) & BIT_MASK_TC9DATA) +#define BIT_SET_TC9DATA(x, v) (BIT_CLEAR_TC9DATA(x) | BIT_TC9DATA(v)) + +/* 2 REG_TC10_CTRL (Offset 0x1108) */ + +#define BIT_TC10INT_EN BIT(26) +#define BIT_TC10MODE BIT(25) +#define BIT_TC10EN BIT(24) + +#define BIT_SHIFT_TC10DATA 0 +#define BIT_MASK_TC10DATA 0xffffff +#define BIT_TC10DATA(x) (((x) & BIT_MASK_TC10DATA) << BIT_SHIFT_TC10DATA) +#define BITS_TC10DATA (BIT_MASK_TC10DATA << BIT_SHIFT_TC10DATA) +#define BIT_CLEAR_TC10DATA(x) ((x) & (~BITS_TC10DATA)) +#define BIT_GET_TC10DATA(x) (((x) >> BIT_SHIFT_TC10DATA) & BIT_MASK_TC10DATA) +#define BIT_SET_TC10DATA(x, v) (BIT_CLEAR_TC10DATA(x) | BIT_TC10DATA(v)) + +/* 2 REG_TC11_CTRL (Offset 0x110C) */ + +#define BIT_TC11INT_EN BIT(26) +#define BIT_TC11MODE BIT(25) +#define BIT_TC11EN BIT(24) + +#define BIT_SHIFT_TC11DATA 0 +#define BIT_MASK_TC11DATA 0xffffff +#define BIT_TC11DATA(x) (((x) & BIT_MASK_TC11DATA) << BIT_SHIFT_TC11DATA) +#define BITS_TC11DATA (BIT_MASK_TC11DATA << BIT_SHIFT_TC11DATA) +#define BIT_CLEAR_TC11DATA(x) ((x) & (~BITS_TC11DATA)) +#define BIT_GET_TC11DATA(x) (((x) >> BIT_SHIFT_TC11DATA) & BIT_MASK_TC11DATA) +#define BIT_SET_TC11DATA(x, v) (BIT_CLEAR_TC11DATA(x) | BIT_TC11DATA(v)) + +/* 2 REG_TC12_CTRL (Offset 0x1110) */ + +#define BIT_TC12INT_EN BIT(26) +#define BIT_TC12MODE BIT(25) +#define BIT_TC12EN BIT(24) +#define BIT_P2P_PWROFF_NOA2_ERLY_INT BIT(22) +#define BIT_P2P_PWROFF_NOA1_ERLY_INT BIT(21) +#define BIT_P2P_PWROFF_NOA0_ERLY_INT BIT(20) + +#define BIT_SHIFT_TC12DATA 0 +#define BIT_MASK_TC12DATA 0xffffff +#define BIT_TC12DATA(x) (((x) & BIT_MASK_TC12DATA) << BIT_SHIFT_TC12DATA) +#define BITS_TC12DATA (BIT_MASK_TC12DATA << BIT_SHIFT_TC12DATA) +#define BIT_CLEAR_TC12DATA(x) ((x) & (~BITS_TC12DATA)) +#define BIT_GET_TC12DATA(x) (((x) >> BIT_SHIFT_TC12DATA) & BIT_MASK_TC12DATA) +#define BIT_SET_TC12DATA(x, v) (BIT_CLEAR_TC12DATA(x) | BIT_TC12DATA(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT) + +/* 2 REG_FWFF (Offset 0x1114) */ + +#define BIT_SHIFT_PKTNUM_TH 24 +#define BIT_MASK_PKTNUM_TH 0xff +#define BIT_PKTNUM_TH(x) (((x) & BIT_MASK_PKTNUM_TH) << BIT_SHIFT_PKTNUM_TH) +#define BITS_PKTNUM_TH (BIT_MASK_PKTNUM_TH << BIT_SHIFT_PKTNUM_TH) +#define BIT_CLEAR_PKTNUM_TH(x) ((x) & (~BITS_PKTNUM_TH)) +#define BIT_GET_PKTNUM_TH(x) (((x) >> BIT_SHIFT_PKTNUM_TH) & BIT_MASK_PKTNUM_TH) +#define BIT_SET_PKTNUM_TH(x, v) (BIT_CLEAR_PKTNUM_TH(x) | BIT_PKTNUM_TH(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FWFF (Offset 0x1114) */ + +#define BIT_SHIFT_PKTNUM_TH_V1 24 +#define BIT_MASK_PKTNUM_TH_V1 0xff +#define BIT_PKTNUM_TH_V1(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1) +#define BITS_PKTNUM_TH_V1 (BIT_MASK_PKTNUM_TH_V1 << BIT_SHIFT_PKTNUM_TH_V1) +#define BIT_CLEAR_PKTNUM_TH_V1(x) ((x) & (~BITS_PKTNUM_TH_V1)) +#define BIT_GET_PKTNUM_TH_V1(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1) +#define BIT_SET_PKTNUM_TH_V1(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V1(x) | BIT_PKTNUM_TH_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FWFF (Offset 0x1114) */ + +#define BIT_SHIFT_TIMER_TH 16 +#define BIT_MASK_TIMER_TH 0xff +#define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH) +#define BITS_TIMER_TH (BIT_MASK_TIMER_TH << BIT_SHIFT_TIMER_TH) +#define BIT_CLEAR_TIMER_TH(x) ((x) & (~BITS_TIMER_TH)) +#define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH) +#define BIT_SET_TIMER_TH(x, v) (BIT_CLEAR_TIMER_TH(x) | BIT_TIMER_TH(v)) + +#define BIT_SHIFT_RXPKT1ENADDR 0 +#define BIT_MASK_RXPKT1ENADDR 0xffff +#define BIT_RXPKT1ENADDR(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR) +#define BITS_RXPKT1ENADDR (BIT_MASK_RXPKT1ENADDR << BIT_SHIFT_RXPKT1ENADDR) +#define BIT_CLEAR_RXPKT1ENADDR(x) ((x) & (~BITS_RXPKT1ENADDR)) +#define BIT_GET_RXPKT1ENADDR(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR) +#define BIT_SET_RXPKT1ENADDR(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR(x) | BIT_RXPKT1ENADDR(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE2IMR (Offset 0x1120) */ + +#define BIT__FE4ISR__IND_MSK BIT(29) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE2IMR (Offset 0x1120) */ + +#define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_EN BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_EN BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_EN BIT(25) +#define BIT_FS_TXSC_VODONE_INT_EN BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE2IMR (Offset 0x1120) */ + +#define BIT_FS_ATIM_MB7_INT_EN BIT(23) +#define BIT_FS_ATIM_MB6_INT_EN BIT(22) +#define BIT_FS_ATIM_MB5_INT_EN BIT(21) +#define BIT_FS_ATIM_MB4_INT_EN BIT(20) +#define BIT_FS_ATIM_MB3_INT_EN BIT(19) +#define BIT_FS_ATIM_MB2_INT_EN BIT(18) +#define BIT_FS_ATIM_MB1_INT_EN BIT(17) +#define BIT_FS_ATIM_MB0_INT_EN BIT(16) +#define BIT_FS_TBTT4INT_EN BIT(11) +#define BIT_FS_TBTT3INT_EN BIT(10) +#define BIT_FS_TBTT2INT_EN BIT(9) +#define BIT_FS_TBTT1INT_EN BIT(8) +#define BIT_FS_TBTT0_MB7INT_EN BIT(7) +#define BIT_FS_TBTT0_MB6INT_EN BIT(6) +#define BIT_FS_TBTT0_MB5INT_EN BIT(5) +#define BIT_FS_TBTT0_MB4INT_EN BIT(4) +#define BIT_FS_TBTT0_MB3INT_EN BIT(3) +#define BIT_FS_TBTT0_MB2INT_EN BIT(2) +#define BIT_FS_TBTT0_MB1INT_EN BIT(1) +#define BIT_FS_TBTT0_INT_EN BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE2ISR (Offset 0x1124) */ + +#define BIT__FE4ISR__IND_INT BIT(29) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FE2ISR (Offset 0x1124) */ + +#define BIT_FS_TXSC_DESC_DONE_INT BIT(28) +#define BIT_FS_TXSC_BKDONE_INT BIT(27) +#define BIT_FS_TXSC_BEDONE_INT BIT(26) +#define BIT_FS_TXSC_VIDONE_INT BIT(25) +#define BIT_FS_TXSC_VODONE_INT BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE2ISR (Offset 0x1124) */ + +#define BIT_FS_ATIM_MB7_INT BIT(23) +#define BIT_FS_ATIM_MB6_INT BIT(22) +#define BIT_FS_ATIM_MB5_INT BIT(21) +#define BIT_FS_ATIM_MB4_INT BIT(20) +#define BIT_FS_ATIM_MB3_INT BIT(19) +#define BIT_FS_ATIM_MB2_INT BIT(18) +#define BIT_FS_ATIM_MB1_INT BIT(17) +#define BIT_FS_ATIM_MB0_INT BIT(16) +#define BIT_FS_TBTT4INT BIT(11) +#define BIT_FS_TBTT3INT BIT(10) +#define BIT_FS_TBTT2INT BIT(9) +#define BIT_FS_TBTT1INT BIT(8) +#define BIT_FS_TBTT0_MB7INT BIT(7) +#define BIT_FS_TBTT0_MB6INT BIT(6) +#define BIT_FS_TBTT0_MB5INT BIT(5) +#define BIT_FS_TBTT0_MB4INT BIT(4) +#define BIT_FS_TBTT0_MB3INT BIT(3) +#define BIT_FS_TBTT0_MB2INT BIT(2) +#define BIT_FS_TBTT0_MB1INT BIT(1) +#define BIT_FS_TBTT0_INT BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE3IMR (Offset 0x1128) */ + +#define BIT_FS_BCNELY4_AGGR_INT_EN BIT(31) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3IMR (Offset 0x1128) */ + +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE3IMR (Offset 0x1128) */ + +#define BIT_FS_BCNELY3_AGGR_INT_EN BIT(30) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3IMR (Offset 0x1128) */ + +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE3IMR (Offset 0x1128) */ + +#define BIT_FS_BCNELY2_AGGR_INT_EN BIT(29) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3IMR (Offset 0x1128) */ + +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE3IMR (Offset 0x1128) */ + +#define BIT_FS_BCNELY1_AGGR_INT_EN BIT(28) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3IMR (Offset 0x1128) */ + +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3IMR (Offset 0x1128) */ + +#define BIT_FS_BCNDMA4_INT_EN BIT(27) +#define BIT_FS_BCNDMA3_INT_EN BIT(26) +#define BIT_FS_BCNDMA2_INT_EN BIT(25) +#define BIT_FS_BCNDMA1_INT_EN BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17) +#define BIT_FS_BCNDMA0_INT_EN BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15) +#define BIT_FS_BCNERLY4_INT_EN BIT(11) +#define BIT_FS_BCNERLY3_INT_EN BIT(10) +#define BIT_FS_BCNERLY2_INT_EN BIT(9) +#define BIT_FS_BCNERLY1_INT_EN BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_EN BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_EN BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_EN BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_EN BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_EN BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_EN BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_EN BIT(1) +#define BIT_FS_BCNERLY0_INT_EN BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_BCNELY4_AGGR_INT BIT(31) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_BCNELY3_AGGR_INT BIT(30) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_BCNELY2_AGGR_INT BIT(29) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_BCNELY1_AGGR_INT BIT(28) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE3ISR (Offset 0x112C) */ + +#define BIT_FS_BCNDMA4_INT BIT(27) +#define BIT_FS_BCNDMA3_INT BIT(26) +#define BIT_FS_BCNDMA2_INT BIT(25) +#define BIT_FS_BCNDMA1_INT BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT BIT(17) +#define BIT_FS_BCNDMA0_INT BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT BIT(15) +#define BIT_FS_BCNERLY4_INT BIT(11) +#define BIT_FS_BCNERLY3_INT BIT(10) +#define BIT_FS_BCNERLY2_INT BIT(9) +#define BIT_FS_BCNERLY1_INT BIT(8) +#define BIT_FS_BCNERLY0_MB7INT BIT(7) +#define BIT_FS_BCNERLY0_MB6INT BIT(6) +#define BIT_FS_BCNERLY0_MB5INT BIT(5) +#define BIT_FS_BCNERLY0_MB4INT BIT(4) +#define BIT_FS_BCNERLY0_MB3INT BIT(3) +#define BIT_FS_BCNERLY0_MB2INT BIT(2) +#define BIT_FS_BCNERLY0_MB1INT BIT(1) +#define BIT_FS_BCNERLY0_INT BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT4_PKTIN_INT_EN BIT(19) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT3_PKTIN_INT_EN BIT(18) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT2_PKTIN_INT_EN BIT(17) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT1_PKTIN_INT_EN BIT(16) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT4_RXUCMD0_OK_INT_EN BIT(15) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT4_RXUCMD1_OK_INT_EN BIT(14) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT4_RXBCMD0_OK_INT_EN BIT(13) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT4_RXBCMD1_OK_INT_EN BIT(12) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT3_RXUCMD0_OK_INT_EN BIT(11) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT3_RXUCMD1_OK_INT_EN BIT(10) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT3_RXBCMD0_OK_INT_EN BIT(9) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT3_RXBCMD1_OK_INT_EN BIT(8) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT2_RXUCMD0_OK_INT_EN BIT(7) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT2_RXUCMD1_OK_INT_EN BIT(6) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT2_RXBCMD0_OK_INT_EN BIT(5) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT2_RXBCMD1_OK_INT_EN BIT(4) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT1_RXUCMD0_OK_INT_EN BIT(3) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT1_RXUCMD1_OK_INT_EN BIT(2) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_DMEM1_WPTR_UPDATE_INT_EN BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT1_RXBCMD0_OK_INT_EN BIT(1) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_PORT1_RXBCMD1_OK_INT_EN BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4IMR (Offset 0x1130) */ + +#define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT4_PKTIN_INT BIT(19) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI3_TXPKTIN_INT BIT(19) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT3_PKTIN_INT BIT(18) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI2_TXPKTIN_INT BIT(18) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT2_PKTIN_INT BIT(17) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI1_TXPKTIN_INT BIT(17) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT1_PKTIN_INT BIT(16) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI0_TXPKTIN_INT BIT(16) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT4_RXUCMD0_OK_INT BIT(15) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI3_RX_UMD0_INT BIT(15) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT4_RXUCMD1_OK_INT BIT(14) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI3_RX_UMD1_INT BIT(14) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT4_RXBCMD0_OK_INT BIT(13) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI3_RX_BMD0_INT BIT(13) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT4_RXBCMD1_OK_INT BIT(12) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI3_RX_BMD1_INT BIT(12) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT3_RXUCMD0_OK_INT BIT(11) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI2_RX_UMD0_INT BIT(11) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT3_RXUCMD1_OK_INT BIT(10) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI2_RX_UMD1_INT BIT(10) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT3_RXBCMD0_OK_INT BIT(9) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI2_RX_BMD0_INT BIT(9) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT3_RXBCMD1_OK_INT BIT(8) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI2_RX_BMD1_INT BIT(8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT2_RXUCMD0_OK_INT BIT(7) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI1_RX_UMD0_INT BIT(7) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT2_RXUCMD1_OK_INT BIT(6) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI1_RX_UMD1_INT BIT(6) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT2_RXBCMD0_OK_INT BIT(5) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI1_RX_BMD0_INT BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT2_RXBCMD1_OK_INT BIT(4) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI1_RX_BMD1_INT BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT1_RXUCMD0_OK_INT BIT(3) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI0_RX_UMD0_INT BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT1_RXUCMD1_OK_INT BIT(2) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI0_RX_UMD1_INT BIT(2) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_DMEM1_WPTR_UPDATE_INT BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT1_RXBCMD0_OK_INT BIT(1) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI0_RX_BMD0_INT BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_PORT1_RXBCMD1_OK_INT BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FE4ISR (Offset 0x1134) */ + +#define BIT_FS_CLI0_RX_BMD1_INT BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1IMR (Offset 0x1138) */ + +#define BIT__FT2ISR__IND_MSK BIT(30) +#define BIT_FTM_PTT_INT_EN BIT(29) +#define BIT_RXFTMREQ_INT_EN BIT(28) +#define BIT_RXFTM_INT_EN BIT(27) +#define BIT_TXFTM_INT_EN BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1IMR (Offset 0x1138) */ + +#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1IMR (Offset 0x1138) */ + +#define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1IMR (Offset 0x1138) */ + +#define BIT_FS_MACID_SEARCH_FAIL_INT_EN BIT(22) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1IMR (Offset 0x1138) */ + +#define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18) +#define BIT_FS_CTWEND2_INT_EN BIT(17) +#define BIT_FS_CTWEND1_INT_EN BIT(16) +#define BIT_FS_CTWEND0_INT_EN BIT(15) +#define BIT_FS_TX_NULL1_INT_EN BIT(14) +#define BIT_FS_TX_NULL0_INT_EN BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12) +#define BIT_FS_P2P_RFON2_INT_EN BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_EN BIT(10) +#define BIT_FS_P2P_RFON1_INT_EN BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_EN BIT(8) +#define BIT_FS_P2P_RFON0_INT_EN BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_EN BIT(6) +#define BIT_FS_RX_UAPSDMD1_EN BIT(5) +#define BIT_FS_RX_UAPSDMD0_EN BIT(4) +#define BIT_FS_TRIGGER_PKT_EN BIT(3) +#define BIT_FS_EOSP_INT_EN BIT(2) +#define BIT_FS_RPWM2_INT_EN BIT(1) +#define BIT_FS_RPWM_INT_EN BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT__FT2ISR__IND_INT BIT(30) +#define BIT_FTM_PTT_INT BIT(29) +#define BIT_RXFTMREQ_INT BIT(28) +#define BIT_RXFTM_INT BIT(27) +#define BIT_TXFTM_INT BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_H2C_CMD_OK_INT BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_MACID_PWRCHANGE5_INT BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT BIT(22) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_MACID_SEARCH_FAIL_INT BIT(22) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_MACID_PWRCHANGE3_INT BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT BIT(18) +#define BIT_FS_CTWEND2_INT BIT(17) +#define BIT_FS_CTWEND1_INT BIT(16) +#define BIT_FS_CTWEND0_INT BIT(15) +#define BIT_FS_TX_NULL1_INT BIT(14) +#define BIT_FS_TX_NULL0_INT BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12) +#define BIT_FS_P2P_RFON2_INT BIT(11) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNOK_PORT4_INT_EN BIT(11) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_P2P_RFOFF2_INT BIT(10) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNOK_PORT3_INT_EN BIT(10) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_P2P_RFON1_INT BIT(9) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNOK_PORT2_INT_EN BIT(9) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_P2P_RFOFF1_INT BIT(8) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNOK_PORT1_INT_EN BIT(8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_P2P_RFON0_INT BIT(7) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNERR_PORT4_INT_EN BIT(7) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_P2P_RFOFF0_INT BIT(6) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNERR_PORT3_INT_EN BIT(6) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_RX_UAPSDMD1_INT BIT(5) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNERR_PORT2_INT_EN BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_RX_UAPSDMD0_INT BIT(4) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TXBCNERR_PORT1_INT_EN BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_TRIGGER_PKT_INT BIT(3) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_ATIM_PORT4_INT_EN BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_EOSP_INT BIT(2) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_ATIM_PORT3_INT_EN BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_RPWM2_INT BIT(1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_ATIM_PORT2_INT_EN BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_RPWM_INT BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FT1ISR (Offset 0x113C) */ + +#define BIT_FS_ATIM_PORT1_INT_EN BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SPWR0 (Offset 0x1140) */ + +#define BIT_SHIFT_MID_31TO0 0 +#define BIT_MASK_MID_31TO0 0xffffffffL +#define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0) +#define BITS_MID_31TO0 (BIT_MASK_MID_31TO0 << BIT_SHIFT_MID_31TO0) +#define BIT_CLEAR_MID_31TO0(x) ((x) & (~BITS_MID_31TO0)) +#define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0) +#define BIT_SET_MID_31TO0(x, v) (BIT_CLEAR_MID_31TO0(x) | BIT_MID_31TO0(v)) + +/* 2 REG_SPWR1 (Offset 0x1144) */ + +#define BIT_SHIFT_MID_63TO32 0 +#define BIT_MASK_MID_63TO32 0xffffffffL +#define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32) +#define BITS_MID_63TO32 (BIT_MASK_MID_63TO32 << BIT_SHIFT_MID_63TO32) +#define BIT_CLEAR_MID_63TO32(x) ((x) & (~BITS_MID_63TO32)) +#define BIT_GET_MID_63TO32(x) \ + (((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32) +#define BIT_SET_MID_63TO32(x, v) (BIT_CLEAR_MID_63TO32(x) | BIT_MID_63TO32(v)) + +/* 2 REG_SPWR2 (Offset 0x1148) */ + +#define BIT_SHIFT_MID_95O64 0 +#define BIT_MASK_MID_95O64 0xffffffffL +#define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64) +#define BITS_MID_95O64 (BIT_MASK_MID_95O64 << BIT_SHIFT_MID_95O64) +#define BIT_CLEAR_MID_95O64(x) ((x) & (~BITS_MID_95O64)) +#define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64) +#define BIT_SET_MID_95O64(x, v) (BIT_CLEAR_MID_95O64(x) | BIT_MID_95O64(v)) + +/* 2 REG_SPWR3 (Offset 0x114C) */ + +#define BIT_SHIFT_MID_127TO96 0 +#define BIT_MASK_MID_127TO96 0xffffffffL +#define BIT_MID_127TO96(x) \ + (((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96) +#define BITS_MID_127TO96 (BIT_MASK_MID_127TO96 << BIT_SHIFT_MID_127TO96) +#define BIT_CLEAR_MID_127TO96(x) ((x) & (~BITS_MID_127TO96)) +#define BIT_GET_MID_127TO96(x) \ + (((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96) +#define BIT_SET_MID_127TO96(x, v) \ + (BIT_CLEAR_MID_127TO96(x) | BIT_MID_127TO96(v)) + +/* 2 REG_POWSEQ (Offset 0x1150) */ + +#define BIT_SHIFT_REF_MID 0 +#define BIT_MASK_REF_MID 0x7f +#define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID) +#define BITS_REF_MID (BIT_MASK_REF_MID << BIT_SHIFT_REF_MID) +#define BIT_CLEAR_REF_MID(x) ((x) & (~BITS_REF_MID)) +#define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID) +#define BIT_SET_REF_MID(x, v) (BIT_CLEAR_REF_MID(x) | BIT_REF_MID(v)) + +/* 2 REG_TC7_CTRL_V1 (Offset 0x1158) */ + +#define BIT_TC7INT_EN BIT(26) +#define BIT_TC7MODE BIT(25) +#define BIT_TC7EN BIT(24) + +#define BIT_SHIFT_TC7DATA 0 +#define BIT_MASK_TC7DATA 0xffffff +#define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA) +#define BITS_TC7DATA (BIT_MASK_TC7DATA << BIT_SHIFT_TC7DATA) +#define BIT_CLEAR_TC7DATA(x) ((x) & (~BITS_TC7DATA)) +#define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA) +#define BIT_SET_TC7DATA(x, v) (BIT_CLEAR_TC7DATA(x) | BIT_TC7DATA(v)) + +/* 2 REG_TC8_CTRL_V1 (Offset 0x115C) */ + +#define BIT_TC8INT_EN BIT(26) +#define BIT_TC8MODE BIT(25) +#define BIT_TC8EN BIT(24) + +#define BIT_SHIFT_TC8DATA 0 +#define BIT_MASK_TC8DATA 0xffffff +#define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA) +#define BITS_TC8DATA (BIT_MASK_TC8DATA << BIT_SHIFT_TC8DATA) +#define BIT_CLEAR_TC8DATA(x) ((x) & (~BITS_TC8DATA)) +#define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA) +#define BIT_SET_TC8DATA(x, v) (BIT_CLEAR_TC8DATA(x) | BIT_TC8DATA(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3 (Offset 0x1160) */ + +#define BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL 24 +#define BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL 0xff +#define BIT_PORT3_RXBCN_TBTT_INTERVAL(x) \ + (((x) & BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL) \ + << BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL) +#define BITS_PORT3_RXBCN_TBTT_INTERVAL \ + (BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL \ + << BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL) +#define BIT_CLEAR_PORT3_RXBCN_TBTT_INTERVAL(x) \ + ((x) & (~BITS_PORT3_RXBCN_TBTT_INTERVAL)) +#define BIT_GET_PORT3_RXBCN_TBTT_INTERVAL(x) \ + (((x) >> BIT_SHIFT_PORT3_RXBCN_TBTT_INTERVAL) & \ + BIT_MASK_PORT3_RXBCN_TBTT_INTERVAL) +#define BIT_SET_PORT3_RXBCN_TBTT_INTERVAL(x, v) \ + (BIT_CLEAR_PORT3_RXBCN_TBTT_INTERVAL(x) | \ + BIT_PORT3_RXBCN_TBTT_INTERVAL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_RX_BCN_TBTT_ITVL0 (Offset 0x1160) */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2 24 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT2(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT2 \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2 \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT2(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3 (Offset 0x1160) */ + +#define BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL 16 +#define BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL 0xff +#define BIT_PORT2_RXBCN_TBTT_INTERVAL(x) \ + (((x) & BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL) \ + << BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL) +#define BITS_PORT2_RXBCN_TBTT_INTERVAL \ + (BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL \ + << BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL) +#define BIT_CLEAR_PORT2_RXBCN_TBTT_INTERVAL(x) \ + ((x) & (~BITS_PORT2_RXBCN_TBTT_INTERVAL)) +#define BIT_GET_PORT2_RXBCN_TBTT_INTERVAL(x) \ + (((x) >> BIT_SHIFT_PORT2_RXBCN_TBTT_INTERVAL) & \ + BIT_MASK_PORT2_RXBCN_TBTT_INTERVAL) +#define BIT_SET_PORT2_RXBCN_TBTT_INTERVAL(x, v) \ + (BIT_CLEAR_PORT2_RXBCN_TBTT_INTERVAL(x) | \ + BIT_PORT2_RXBCN_TBTT_INTERVAL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_RX_BCN_TBTT_ITVL0 (Offset 0x1160) */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1 16 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT1(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT1 \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1 \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT1(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3 (Offset 0x1160) */ + +#define BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL 8 +#define BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL 0xff +#define BIT_PORT1_RXBCN_TBTT_INTERVAL(x) \ + (((x) & BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL) \ + << BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL) +#define BITS_PORT1_RXBCN_TBTT_INTERVAL \ + (BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL \ + << BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL) +#define BIT_CLEAR_PORT1_RXBCN_TBTT_INTERVAL(x) \ + ((x) & (~BITS_PORT1_RXBCN_TBTT_INTERVAL)) +#define BIT_GET_PORT1_RXBCN_TBTT_INTERVAL(x) \ + (((x) >> BIT_SHIFT_PORT1_RXBCN_TBTT_INTERVAL) & \ + BIT_MASK_PORT1_RXBCN_TBTT_INTERVAL) +#define BIT_SET_PORT1_RXBCN_TBTT_INTERVAL(x, v) \ + (BIT_CLEAR_PORT1_RXBCN_TBTT_INTERVAL(x) | \ + BIT_PORT1_RXBCN_TBTT_INTERVAL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_RX_BCN_TBTT_ITVL0 (Offset 0x1160) */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0 8 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT0(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT0 \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0 \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT0(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3 (Offset 0x1160) */ + +#define BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL 0 +#define BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL 0xff +#define BIT_PORT0_RXBCN_TBTT_INTERVAL(x) \ + (((x) & BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL) \ + << BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL) +#define BITS_PORT0_RXBCN_TBTT_INTERVAL \ + (BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL \ + << BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL) +#define BIT_CLEAR_PORT0_RXBCN_TBTT_INTERVAL(x) \ + ((x) & (~BITS_PORT0_RXBCN_TBTT_INTERVAL)) +#define BIT_GET_PORT0_RXBCN_TBTT_INTERVAL(x) \ + (((x) >> BIT_SHIFT_PORT0_RXBCN_TBTT_INTERVAL) & \ + BIT_MASK_PORT0_RXBCN_TBTT_INTERVAL) +#define BIT_SET_PORT0_RXBCN_TBTT_INTERVAL(x, v) \ + (BIT_CLEAR_PORT0_RXBCN_TBTT_INTERVAL(x) | \ + BIT_PORT0_RXBCN_TBTT_INTERVAL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_RX_BCN_TBTT_ITVL0 (Offset 0x1160) */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 0xff +#define BIT_RX_BCN_TBTT_ITVL_PORT0(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) +#define BITS_RX_BCN_TBTT_ITVL_PORT0 \ + (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0)) +#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_PORT0) +#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x) | BIT_RX_BCN_TBTT_ITVL_PORT0(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_RXBCN_TBTT_INTERVAL_PORT4 (Offset 0x1164) */ + +#define BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL 0 +#define BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL 0xff +#define BIT_PORT4_RXBCN_TBTT_INTERVAL(x) \ + (((x) & BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL) \ + << BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL) +#define BITS_PORT4_RXBCN_TBTT_INTERVAL \ + (BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL \ + << BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL) +#define BIT_CLEAR_PORT4_RXBCN_TBTT_INTERVAL(x) \ + ((x) & (~BITS_PORT4_RXBCN_TBTT_INTERVAL)) +#define BIT_GET_PORT4_RXBCN_TBTT_INTERVAL(x) \ + (((x) >> BIT_SHIFT_PORT4_RXBCN_TBTT_INTERVAL) & \ + BIT_MASK_PORT4_RXBCN_TBTT_INTERVAL) +#define BIT_SET_PORT4_RXBCN_TBTT_INTERVAL(x, v) \ + (BIT_CLEAR_PORT4_RXBCN_TBTT_INTERVAL(x) | \ + BIT_PORT4_RXBCN_TBTT_INTERVAL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_RX_BCN_TBTT_ITVL1 (Offset 0x1164) */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT3(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT3 \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3 \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT3(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) + +/* 2 REG_FWIMR1 (Offset 0x1168) */ + +#define BIT_FS_ATIM_MB15_INT_EN BIT(31) +#define BIT_FS_ATIM_MB14_INT_EN BIT(30) +#define BIT_FS_ATIM_MB13_INT_EN BIT(29) +#define BIT_FS_ATIM_MB12_INT_EN BIT(28) +#define BIT_FS_ATIM_MB11_INT_EN BIT(27) +#define BIT_FS_ATIM_MB10_INT_EN BIT(26) +#define BIT_FS_ATIM_MB9_INT_EN BIT(25) +#define BIT_FS_ATIM_MB8_INT_EN BIT(24) +#define BIT_FS_TXBCNERR_MB15_INT_EN BIT(23) +#define BIT_FS_TXBCNERR_MB14_INT_EN BIT(22) +#define BIT_FS_TXBCNERR_MB13_INT_EN BIT(21) +#define BIT_FS_TXBCNERR_MB12_INT_EN BIT(20) +#define BIT_FS_TXBCNERR_MB11_INT_EN BIT(19) +#define BIT_FS_TXBCNERR_MB10_INT_EN BIT(18) +#define BIT_FS_TXBCNERR_MB9_INT_EN BIT(17) +#define BIT_FS_TXBCNERR_MB8_INT_EN BIT(16) +#define BIT_FS_TXBCNOK_MB15_INT_EN BIT(15) +#define BIT_FS_TXBCNOK_MB14_INT_EN BIT(14) +#define BIT_FS_TXBCNOK_MB13_INT_EN BIT(13) +#define BIT_FS_TXBCNOK_MB12_INT_EN BIT(12) +#define BIT_FS_TXBCNOK_MB11_INT_EN BIT(11) +#define BIT_FS_TXBCNOK_MB10_INT_EN BIT(10) +#define BIT_FS_TXBCNOK_MB9_INT_EN BIT(9) +#define BIT_FS_TXBCNOK_MB8_INT_EN BIT(8) +#define BIT_FS_BCNERLY0_MB15INT_EN BIT(7) +#define BIT_FS_BCNERLY0_MB14INT_EN BIT(6) +#define BIT_FS_BCNERLY0_MB13INT_EN BIT(5) +#define BIT_FS_BCNERLY0_MB12INT_EN BIT(4) +#define BIT_FS_BCNERLY0_MB11INT_EN BIT(3) +#define BIT_FS_BCNERLY0_MB10INT_EN BIT(2) +#define BIT_FS_BCNERLY0_MB9INT_EN BIT(1) +#define BIT_FS_BCNERLY0_MB8INT_EN BIT(0) + +/* 2 REG_FWISR1 (Offset 0x116C) */ + +#define BIT_FS_ATIM_MB15_INT BIT(31) +#define BIT_FS_ATIM_MB14_INT BIT(30) +#define BIT_FS_ATIM_MB13_INT BIT(29) +#define BIT_FS_ATIM_MB12_INT BIT(28) +#define BIT_FS_ATIM_MB11_INT BIT(27) +#define BIT_FS_ATIM_MB10_INT BIT(26) +#define BIT_FS_ATIM_MB9_INT BIT(25) +#define BIT_FS_ATIM_MB8_INT BIT(24) +#define BIT_FS_TXBCNERR_MB15_INT BIT(23) +#define BIT_FS_TXBCNERR_MB14_INT BIT(22) +#define BIT_FS_TXBCNERR_MB13_INT BIT(21) +#define BIT_FS_TXBCNERR_MB12_INT BIT(20) +#define BIT_FS_TXBCNERR_MB11_INT BIT(19) +#define BIT_FS_TXBCNERR_MB10_INT BIT(18) +#define BIT_FS_TXBCNERR_MB9_INT BIT(17) +#define BIT_FS_TXBCNERR_MB8_INT BIT(16) +#define BIT_FS_TXBCNOK_MB15_INT BIT(15) +#define BIT_FS_TXBCNOK_MB14_INT BIT(14) +#define BIT_FS_TXBCNOK_MB13_INT BIT(13) +#define BIT_FS_TXBCNOK_MB12_INT BIT(12) +#define BIT_FS_TXBCNOK_MB11_INT BIT(11) +#define BIT_FS_TXBCNOK_MB10_INT BIT(10) +#define BIT_FS_TXBCNOK_MB9_INT BIT(9) +#define BIT_FS_TXBCNOK_MB8_INT BIT(8) +#define BIT_FS_BCNERLY0_MB15INT BIT(7) +#define BIT_FS_BCNERLY0_MB14INT BIT(6) +#define BIT_FS_BCNERLY0_MB13INT BIT(5) +#define BIT_FS_BCNERLY0_MB12INT BIT(4) +#define BIT_FS_BCNERLY0_MB11INT BIT(3) +#define BIT_FS_BCNERLY0_MB10INT BIT(2) +#define BIT_FS_BCNERLY0_MB9INT BIT(1) +#define BIT_FS_BCNERLY0_MB8INT BIT(0) + +/* 2 REG_FWIMR2 (Offset 0x1170) */ + +#define BIT_FS_BCNDMA0_MB15_INT_EN BIT(15) +#define BIT_FS_BCNDMA0_MB14_INT_EN BIT(14) +#define BIT_FS_BCNDMA0_MB13_INT_EN BIT(13) +#define BIT_FS_BCNDMA0_MB12_INT_EN BIT(12) +#define BIT_FS_BCNDMA0_MB11_INT_EN BIT(11) +#define BIT_FS_BCNDMA0_MB10_INT_EN BIT(10) +#define BIT_FS_BCNDMA0_MB9_INT_EN BIT(9) +#define BIT_FS_BCNDMA0_MB8_INT_EN BIT(8) +#define BIT_FS_TBTT0_MB15INT_EN BIT(7) +#define BIT_FS_TBTT0_MB14INT_EN BIT(6) +#define BIT_FS_TBTT0_MB13INT_EN BIT(5) +#define BIT_FS_TBTT0_MB12INT_EN BIT(4) +#define BIT_FS_TBTT0_MB11INT_EN BIT(3) +#define BIT_FS_TBTT0_MB10INT_EN BIT(2) +#define BIT_FS_TBTT0_MB9INT_EN BIT(1) +#define BIT_FS_TBTT0_MB8INT_EN BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_IO_WRAP_ERR_FLAG (Offset 0x1170) */ + +#define BIT_IO_WRAP_ERR BIT(0) + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) + +/* 2 REG_FWISR2 (Offset 0x1174) */ + +#define BIT_FS_BCNDMA0_MB15_INT BIT(15) +#define BIT_FS_BCNDMA0_MB14_INT BIT(14) +#define BIT_FS_BCNDMA0_MB13_INT BIT(13) +#define BIT_FS_BCNDMA0_MB12_INT BIT(12) +#define BIT_FS_BCNDMA0_MB11_INT BIT(11) +#define BIT_FS_BCNDMA0_MB10_INT BIT(10) +#define BIT_FS_BCNDMA0_MB9_INT BIT(9) +#define BIT_FS_BCNDMA0_MB8_INT BIT(8) +#define BIT_FS_TBTT0_MB15INT BIT(7) +#define BIT_FS_TBTT0_MB14INT BIT(6) +#define BIT_FS_TBTT0_MB13INT BIT(5) +#define BIT_FS_TBTT0_MB12INT BIT(4) +#define BIT_FS_TBTT0_MB11INT BIT(3) +#define BIT_FS_TBTT0_MB10INT BIT(2) +#define BIT_FS_TBTT0_MB9INT BIT(1) +#define BIT_FS_TBTT0_MB8INT BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FWISR3 (Offset 0x117C) */ + +#define BIT_FS_TXBCNOK_PORT4_INT BIT(11) +#define BIT_FS_TXBCNOK_PORT3_INT BIT(10) +#define BIT_FS_TXBCNOK_PORT2_INT BIT(9) +#define BIT_FS_TXBCNOK_PORT1_INT BIT(8) +#define BIT_FS_TXBCNERR_PORT4_INT BIT(7) +#define BIT_FS_TXBCNERR_PORT3_INT BIT(6) +#define BIT_FS_TXBCNERR_PORT2_INT BIT(5) +#define BIT_FS_TXBCNERR_PORT1_INT BIT(4) +#define BIT_FS_ATIM_PORT4_INT BIT(3) +#define BIT_FS_ATIM_PORT3_INT BIT(2) +#define BIT_FS_ATIM_PORT2_INT BIT(1) +#define BIT_FS_ATIM_PORT1_INT BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_SPEED_SENSOR (Offset 0x1180) */ + +#define BIT_DSS_1_RST_N BIT(31) +#define BIT_DSS_1_SPEED_EN BIT(30) +#define BIT_DSS_1_WIRE_SEL BIT(29) +#define BIT_DSS_ENCLK BIT(28) + +#define BIT_SHIFT_DSS_1_RO_SEL 24 +#define BIT_MASK_DSS_1_RO_SEL 0x7 +#define BIT_DSS_1_RO_SEL(x) \ + (((x) & BIT_MASK_DSS_1_RO_SEL) << BIT_SHIFT_DSS_1_RO_SEL) +#define BITS_DSS_1_RO_SEL (BIT_MASK_DSS_1_RO_SEL << BIT_SHIFT_DSS_1_RO_SEL) +#define BIT_CLEAR_DSS_1_RO_SEL(x) ((x) & (~BITS_DSS_1_RO_SEL)) +#define BIT_GET_DSS_1_RO_SEL(x) \ + (((x) >> BIT_SHIFT_DSS_1_RO_SEL) & BIT_MASK_DSS_1_RO_SEL) +#define BIT_SET_DSS_1_RO_SEL(x, v) \ + (BIT_CLEAR_DSS_1_RO_SEL(x) | BIT_DSS_1_RO_SEL(v)) + +#define BIT_SHIFT_DSS_1_DATA_IN 0 +#define BIT_MASK_DSS_1_DATA_IN 0xfffff +#define BIT_DSS_1_DATA_IN(x) \ + (((x) & BIT_MASK_DSS_1_DATA_IN) << BIT_SHIFT_DSS_1_DATA_IN) +#define BITS_DSS_1_DATA_IN (BIT_MASK_DSS_1_DATA_IN << BIT_SHIFT_DSS_1_DATA_IN) +#define BIT_CLEAR_DSS_1_DATA_IN(x) ((x) & (~BITS_DSS_1_DATA_IN)) +#define BIT_GET_DSS_1_DATA_IN(x) \ + (((x) >> BIT_SHIFT_DSS_1_DATA_IN) & BIT_MASK_DSS_1_DATA_IN) +#define BIT_SET_DSS_1_DATA_IN(x, v) \ + (BIT_CLEAR_DSS_1_DATA_IN(x) | BIT_DSS_1_DATA_IN(v)) + +/* 2 REG_SPEED_SENSOR1 (Offset 0x1184) */ + +#define BIT_DSS_1_READY BIT(31) +#define BIT_DSS_1_WSORT_GO BIT(30) + +#define BIT_SHIFT_DSS_1_COUNT_OUT 0 +#define BIT_MASK_DSS_1_COUNT_OUT 0xfffff +#define BIT_DSS_1_COUNT_OUT(x) \ + (((x) & BIT_MASK_DSS_1_COUNT_OUT) << BIT_SHIFT_DSS_1_COUNT_OUT) +#define BITS_DSS_1_COUNT_OUT \ + (BIT_MASK_DSS_1_COUNT_OUT << BIT_SHIFT_DSS_1_COUNT_OUT) +#define BIT_CLEAR_DSS_1_COUNT_OUT(x) ((x) & (~BITS_DSS_1_COUNT_OUT)) +#define BIT_GET_DSS_1_COUNT_OUT(x) \ + (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT) & BIT_MASK_DSS_1_COUNT_OUT) +#define BIT_SET_DSS_1_COUNT_OUT(x, v) \ + (BIT_CLEAR_DSS_1_COUNT_OUT(x) | BIT_DSS_1_COUNT_OUT(v)) + +/* 2 REG_SPEED_SENSOR2 (Offset 0x1188) */ + +#define BIT_DSS_2_RST_N BIT(31) +#define BIT_DSS_2_SPEED_EN BIT(30) +#define BIT_DSS_2_WIRE_SEL BIT(29) + +#define BIT_SHIFT_DSS_2_RO_SEL 24 +#define BIT_MASK_DSS_2_RO_SEL 0x7 +#define BIT_DSS_2_RO_SEL(x) \ + (((x) & BIT_MASK_DSS_2_RO_SEL) << BIT_SHIFT_DSS_2_RO_SEL) +#define BITS_DSS_2_RO_SEL (BIT_MASK_DSS_2_RO_SEL << BIT_SHIFT_DSS_2_RO_SEL) +#define BIT_CLEAR_DSS_2_RO_SEL(x) ((x) & (~BITS_DSS_2_RO_SEL)) +#define BIT_GET_DSS_2_RO_SEL(x) \ + (((x) >> BIT_SHIFT_DSS_2_RO_SEL) & BIT_MASK_DSS_2_RO_SEL) +#define BIT_SET_DSS_2_RO_SEL(x, v) \ + (BIT_CLEAR_DSS_2_RO_SEL(x) | BIT_DSS_2_RO_SEL(v)) + +#define BIT_SHIFT_DSS_2_DATA_IN 0 +#define BIT_MASK_DSS_2_DATA_IN 0xfffff +#define BIT_DSS_2_DATA_IN(x) \ + (((x) & BIT_MASK_DSS_2_DATA_IN) << BIT_SHIFT_DSS_2_DATA_IN) +#define BITS_DSS_2_DATA_IN (BIT_MASK_DSS_2_DATA_IN << BIT_SHIFT_DSS_2_DATA_IN) +#define BIT_CLEAR_DSS_2_DATA_IN(x) ((x) & (~BITS_DSS_2_DATA_IN)) +#define BIT_GET_DSS_2_DATA_IN(x) \ + (((x) >> BIT_SHIFT_DSS_2_DATA_IN) & BIT_MASK_DSS_2_DATA_IN) +#define BIT_SET_DSS_2_DATA_IN(x, v) \ + (BIT_CLEAR_DSS_2_DATA_IN(x) | BIT_DSS_2_DATA_IN(v)) + +/* 2 REG_SPEED_SENSOR3 (Offset 0x118C) */ + +#define BIT_DSS_2_READY BIT(31) +#define BIT_DSS_2_WSORT_GO BIT(30) + +#define BIT_SHIFT_DSS_2_COUNT_OUT 0 +#define BIT_MASK_DSS_2_COUNT_OUT 0xfffff +#define BIT_DSS_2_COUNT_OUT(x) \ + (((x) & BIT_MASK_DSS_2_COUNT_OUT) << BIT_SHIFT_DSS_2_COUNT_OUT) +#define BITS_DSS_2_COUNT_OUT \ + (BIT_MASK_DSS_2_COUNT_OUT << BIT_SHIFT_DSS_2_COUNT_OUT) +#define BIT_CLEAR_DSS_2_COUNT_OUT(x) ((x) & (~BITS_DSS_2_COUNT_OUT)) +#define BIT_GET_DSS_2_COUNT_OUT(x) \ + (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT) & BIT_MASK_DSS_2_COUNT_OUT) +#define BIT_SET_DSS_2_COUNT_OUT(x, v) \ + (BIT_CLEAR_DSS_2_COUNT_OUT(x) | BIT_DSS_2_COUNT_OUT(v)) + +/* 2 REG_SPEED_SENSOR4 (Offset 0x1190) */ + +#define BIT_DSS_3_RST_N BIT(31) +#define BIT_DSS_3_SPEED_EN BIT(30) +#define BIT_DSS_3_WIRE_SEL BIT(29) + +#define BIT_SHIFT_DSS_3_RO_SEL 24 +#define BIT_MASK_DSS_3_RO_SEL 0x7 +#define BIT_DSS_3_RO_SEL(x) \ + (((x) & BIT_MASK_DSS_3_RO_SEL) << BIT_SHIFT_DSS_3_RO_SEL) +#define BITS_DSS_3_RO_SEL (BIT_MASK_DSS_3_RO_SEL << BIT_SHIFT_DSS_3_RO_SEL) +#define BIT_CLEAR_DSS_3_RO_SEL(x) ((x) & (~BITS_DSS_3_RO_SEL)) +#define BIT_GET_DSS_3_RO_SEL(x) \ + (((x) >> BIT_SHIFT_DSS_3_RO_SEL) & BIT_MASK_DSS_3_RO_SEL) +#define BIT_SET_DSS_3_RO_SEL(x, v) \ + (BIT_CLEAR_DSS_3_RO_SEL(x) | BIT_DSS_3_RO_SEL(v)) + +#define BIT_SHIFT_DSS_3_DATA_IN 0 +#define BIT_MASK_DSS_3_DATA_IN 0xfffff +#define BIT_DSS_3_DATA_IN(x) \ + (((x) & BIT_MASK_DSS_3_DATA_IN) << BIT_SHIFT_DSS_3_DATA_IN) +#define BITS_DSS_3_DATA_IN (BIT_MASK_DSS_3_DATA_IN << BIT_SHIFT_DSS_3_DATA_IN) +#define BIT_CLEAR_DSS_3_DATA_IN(x) ((x) & (~BITS_DSS_3_DATA_IN)) +#define BIT_GET_DSS_3_DATA_IN(x) \ + (((x) >> BIT_SHIFT_DSS_3_DATA_IN) & BIT_MASK_DSS_3_DATA_IN) +#define BIT_SET_DSS_3_DATA_IN(x, v) \ + (BIT_CLEAR_DSS_3_DATA_IN(x) | BIT_DSS_3_DATA_IN(v)) + +/* 2 REG_SPEED_SENSOR5 (Offset 0x1194) */ + +#define BIT_DSS_3_READY BIT(31) +#define BIT_DSS_3_WSORT_GO BIT(30) + +#define BIT_SHIFT_DSS_3_COUNT_OUT 0 +#define BIT_MASK_DSS_3_COUNT_OUT 0xfffff +#define BIT_DSS_3_COUNT_OUT(x) \ + (((x) & BIT_MASK_DSS_3_COUNT_OUT) << BIT_SHIFT_DSS_3_COUNT_OUT) +#define BITS_DSS_3_COUNT_OUT \ + (BIT_MASK_DSS_3_COUNT_OUT << BIT_SHIFT_DSS_3_COUNT_OUT) +#define BIT_CLEAR_DSS_3_COUNT_OUT(x) ((x) & (~BITS_DSS_3_COUNT_OUT)) +#define BIT_GET_DSS_3_COUNT_OUT(x) \ + (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT) & BIT_MASK_DSS_3_COUNT_OUT) +#define BIT_SET_DSS_3_COUNT_OUT(x, v) \ + (BIT_CLEAR_DSS_3_COUNT_OUT(x) | BIT_DSS_3_COUNT_OUT(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_RXPKTBUF_1_MAX_ADDR (Offset 0x1198) */ + +#define BIT_SHIFT_RXPKTBUF_SIZE 30 +#define BIT_MASK_RXPKTBUF_SIZE 0x3 +#define BIT_RXPKTBUF_SIZE(x) \ + (((x) & BIT_MASK_RXPKTBUF_SIZE) << BIT_SHIFT_RXPKTBUF_SIZE) +#define BITS_RXPKTBUF_SIZE (BIT_MASK_RXPKTBUF_SIZE << BIT_SHIFT_RXPKTBUF_SIZE) +#define BIT_CLEAR_RXPKTBUF_SIZE(x) ((x) & (~BITS_RXPKTBUF_SIZE)) +#define BIT_GET_RXPKTBUF_SIZE(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_SIZE) & BIT_MASK_RXPKTBUF_SIZE) +#define BIT_SET_RXPKTBUF_SIZE(x, v) \ + (BIT_CLEAR_RXPKTBUF_SIZE(x) | BIT_RXPKTBUF_SIZE(v)) + +#define BIT_RXPKTBUF_DBG_SEL BIT(29) + +#define BIT_SHIFT_RXPKTBUF_1_MAX_ADDR 0 +#define BIT_MASK_RXPKTBUF_1_MAX_ADDR 0x3ffff +#define BIT_RXPKTBUF_1_MAX_ADDR(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_MAX_ADDR) << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) +#define BITS_RXPKTBUF_1_MAX_ADDR \ + (BIT_MASK_RXPKTBUF_1_MAX_ADDR << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) +#define BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXPKTBUF_1_MAX_ADDR)) +#define BIT_GET_RXPKTBUF_1_MAX_ADDR(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) & BIT_MASK_RXPKTBUF_1_MAX_ADDR) +#define BIT_SET_RXPKTBUF_1_MAX_ADDR(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) | BIT_RXPKTBUF_1_MAX_ADDR(v)) + +/* 2 REG_RXFWBUF_1_MAX_ADDR (Offset 0x119C) */ + +#define BIT_SHIFT_RXFWBUF_1_MAX_ADDR 0 +#define BIT_MASK_RXFWBUF_1_MAX_ADDR 0xffff +#define BIT_RXFWBUF_1_MAX_ADDR(x) \ + (((x) & BIT_MASK_RXFWBUF_1_MAX_ADDR) << BIT_SHIFT_RXFWBUF_1_MAX_ADDR) +#define BITS_RXFWBUF_1_MAX_ADDR \ + (BIT_MASK_RXFWBUF_1_MAX_ADDR << BIT_SHIFT_RXFWBUF_1_MAX_ADDR) +#define BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXFWBUF_1_MAX_ADDR)) +#define BIT_GET_RXFWBUF_1_MAX_ADDR(x) \ + (((x) >> BIT_SHIFT_RXFWBUF_1_MAX_ADDR) & BIT_MASK_RXFWBUF_1_MAX_ADDR) +#define BIT_SET_RXFWBUF_1_MAX_ADDR(x, v) \ + (BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) | BIT_RXFWBUF_1_MAX_ADDR(v)) + +/* 2 REG_RXPKTBUF_1_READ (Offset 0x11A4) */ + +#define BIT_SHIFT_RXPKTBUF_1_READ 0 +#define BIT_MASK_RXPKTBUF_1_READ 0x3ffff +#define BIT_RXPKTBUF_1_READ(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_READ) << BIT_SHIFT_RXPKTBUF_1_READ) +#define BITS_RXPKTBUF_1_READ \ + (BIT_MASK_RXPKTBUF_1_READ << BIT_SHIFT_RXPKTBUF_1_READ) +#define BIT_CLEAR_RXPKTBUF_1_READ(x) ((x) & (~BITS_RXPKTBUF_1_READ)) +#define BIT_GET_RXPKTBUF_1_READ(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_READ) & BIT_MASK_RXPKTBUF_1_READ) +#define BIT_SET_RXPKTBUF_1_READ(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_READ(x) | BIT_RXPKTBUF_1_READ(v)) + +/* 2 REG_RXPKTBUF_1_WRITE (Offset 0x11A8) */ + +#define BIT_SHIFT_R_OQT_DBG_SEL 16 +#define BIT_MASK_R_OQT_DBG_SEL 0xff +#define BIT_R_OQT_DBG_SEL(x) \ + (((x) & BIT_MASK_R_OQT_DBG_SEL) << BIT_SHIFT_R_OQT_DBG_SEL) +#define BITS_R_OQT_DBG_SEL (BIT_MASK_R_OQT_DBG_SEL << BIT_SHIFT_R_OQT_DBG_SEL) +#define BIT_CLEAR_R_OQT_DBG_SEL(x) ((x) & (~BITS_R_OQT_DBG_SEL)) +#define BIT_GET_R_OQT_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_R_OQT_DBG_SEL) & BIT_MASK_R_OQT_DBG_SEL) +#define BIT_SET_R_OQT_DBG_SEL(x, v) \ + (BIT_CLEAR_R_OQT_DBG_SEL(x) | BIT_R_OQT_DBG_SEL(v)) + +#define BIT_SHIFT_R_TXPKTBF_DBG_SEL 8 +#define BIT_MASK_R_TXPKTBF_DBG_SEL 0x7 +#define BIT_R_TXPKTBF_DBG_SEL(x) \ + (((x) & BIT_MASK_R_TXPKTBF_DBG_SEL) << BIT_SHIFT_R_TXPKTBF_DBG_SEL) +#define BITS_R_TXPKTBF_DBG_SEL \ + (BIT_MASK_R_TXPKTBF_DBG_SEL << BIT_SHIFT_R_TXPKTBF_DBG_SEL) +#define BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_TXPKTBF_DBG_SEL)) +#define BIT_GET_R_TXPKTBF_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_R_TXPKTBF_DBG_SEL) & BIT_MASK_R_TXPKTBF_DBG_SEL) +#define BIT_SET_R_TXPKTBF_DBG_SEL(x, v) \ + (BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) | BIT_R_TXPKTBF_DBG_SEL(v)) + +#define BIT_SHIFT_R_RXPKT_DBG_SEL 6 +#define BIT_MASK_R_RXPKT_DBG_SEL 0x3 +#define BIT_R_RXPKT_DBG_SEL(x) \ + (((x) & BIT_MASK_R_RXPKT_DBG_SEL) << BIT_SHIFT_R_RXPKT_DBG_SEL) +#define BITS_R_RXPKT_DBG_SEL \ + (BIT_MASK_R_RXPKT_DBG_SEL << BIT_SHIFT_R_RXPKT_DBG_SEL) +#define BIT_CLEAR_R_RXPKT_DBG_SEL(x) ((x) & (~BITS_R_RXPKT_DBG_SEL)) +#define BIT_GET_R_RXPKT_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_R_RXPKT_DBG_SEL) & BIT_MASK_R_RXPKT_DBG_SEL) +#define BIT_SET_R_RXPKT_DBG_SEL(x, v) \ + (BIT_CLEAR_R_RXPKT_DBG_SEL(x) | BIT_R_RXPKT_DBG_SEL(v)) + +#define BIT_SHIFT_RXPKTBUF_1_WRITE 0 +#define BIT_MASK_RXPKTBUF_1_WRITE 0x3ffff +#define BIT_RXPKTBUF_1_WRITE(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_WRITE) << BIT_SHIFT_RXPKTBUF_1_WRITE) +#define BITS_RXPKTBUF_1_WRITE \ + (BIT_MASK_RXPKTBUF_1_WRITE << BIT_SHIFT_RXPKTBUF_1_WRITE) +#define BIT_CLEAR_RXPKTBUF_1_WRITE(x) ((x) & (~BITS_RXPKTBUF_1_WRITE)) +#define BIT_GET_RXPKTBUF_1_WRITE(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_WRITE) & BIT_MASK_RXPKTBUF_1_WRITE) +#define BIT_SET_RXPKTBUF_1_WRITE(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_WRITE(x) | BIT_RXPKTBUF_1_WRITE(v)) + +#define BIT_SHIFT_R_RXPKTBF_DBG_SEL 0 +#define BIT_MASK_R_RXPKTBF_DBG_SEL 0x3 +#define BIT_R_RXPKTBF_DBG_SEL(x) \ + (((x) & BIT_MASK_R_RXPKTBF_DBG_SEL) << BIT_SHIFT_R_RXPKTBF_DBG_SEL) +#define BITS_R_RXPKTBF_DBG_SEL \ + (BIT_MASK_R_RXPKTBF_DBG_SEL << BIT_SHIFT_R_RXPKTBF_DBG_SEL) +#define BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_RXPKTBF_DBG_SEL)) +#define BIT_GET_R_RXPKTBF_DBG_SEL(x) \ + (((x) >> BIT_SHIFT_R_RXPKTBF_DBG_SEL) & BIT_MASK_R_RXPKTBF_DBG_SEL) +#define BIT_SET_R_RXPKTBF_DBG_SEL(x, v) \ + (BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) | BIT_R_RXPKTBF_DBG_SEL(v)) + +/* 2 REG_RFE_CTRL_PAD_E2 (Offset 0x11B0) */ + +#define BIT_RFE_CTRL_ANTSW_E2 BIT(16) +#define BIT_RFE_CTRL_PIN15_E2 BIT(15) +#define BIT_RFE_CTRL_PIN14_E2 BIT(14) +#define BIT_RFE_CTRL_PIN13_E2 BIT(13) +#define BIT_RFE_CTRL_PIN12_E2 BIT(12) +#define BIT_RFE_CTRL_PIN11_E2 BIT(11) +#define BIT_RFE_CTRL_PIN10_E2 BIT(10) +#define BIT_RFE_CTRL_PIN9_E2 BIT(9) +#define BIT_RFE_CTRL_PIN8_E2 BIT(8) +#define BIT_RFE_CTRL_PIN7_E2 BIT(7) +#define BIT_RFE_CTRL_PIN6_E2 BIT(6) +#define BIT_RFE_CTRL_PIN5_E2 BIT(5) +#define BIT_RFE_CTRL_PIN4_E2 BIT(4) +#define BIT_RFE_CTRL_PIN3_E2 BIT(3) +#define BIT_RFE_CTRL_PIN2_E2 BIT(2) +#define BIT_RFE_CTRL_PIN1_E2 BIT(1) +#define BIT_RFE_CTRL_PIN0_E2 BIT(0) + +/* 2 REG_RFE_CTRL_PAD_SR (Offset 0x11B4) */ + +#define BIT_RFE_CTRL_ANTSW_SR BIT(16) +#define BIT_RFE_CTRL_PIN15_SR BIT(15) +#define BIT_RFE_CTRL_PIN14_SR BIT(14) +#define BIT_RFE_CTRL_PIN13_SR BIT(13) +#define BIT_RFE_CTRL_PIN12_SR BIT(12) +#define BIT_RFE_CTRL_PIN11_SR BIT(11) +#define BIT_RFE_CTRL_PIN10_SR BIT(10) +#define BIT_RFE_CTRL_PIN9_SR BIT(9) +#define BIT_RFE_CTRL_PIN8_SR BIT(8) +#define BIT_RFE_CTRL_PIN7_SR BIT(7) +#define BIT_RFE_CTRL_PIN6_SR BIT(6) +#define BIT_RFE_CTRL_PIN5_SR BIT(5) +#define BIT_RFE_CTRL_PIN4_SR BIT(4) +#define BIT_RFE_CTRL_PIN3_SR BIT(3) +#define BIT_RFE_CTRL_PIN2_SR BIT(2) +#define BIT_RFE_CTRL_PIN1_SR BIT(1) +#define BIT_RFE_CTRL_PIN0_SR BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_EXT_QUEUE_REG (Offset 0x11C0) */ + +#define BIT_SHIFT_PCIE_PRIORITY_SEL 0 +#define BIT_MASK_PCIE_PRIORITY_SEL 0x3 +#define BIT_PCIE_PRIORITY_SEL(x) \ + (((x) & BIT_MASK_PCIE_PRIORITY_SEL) << BIT_SHIFT_PCIE_PRIORITY_SEL) +#define BITS_PCIE_PRIORITY_SEL \ + (BIT_MASK_PCIE_PRIORITY_SEL << BIT_SHIFT_PCIE_PRIORITY_SEL) +#define BIT_CLEAR_PCIE_PRIORITY_SEL(x) ((x) & (~BITS_PCIE_PRIORITY_SEL)) +#define BIT_GET_PCIE_PRIORITY_SEL(x) \ + (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL) & BIT_MASK_PCIE_PRIORITY_SEL) +#define BIT_SET_PCIE_PRIORITY_SEL(x, v) \ + (BIT_CLEAR_PCIE_PRIORITY_SEL(x) | BIT_PCIE_PRIORITY_SEL(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_H2C_PRIORITY_SEL (Offset 0x11C0) */ + +#define BIT_SHIFT_H2C_PRIORITY_SEL 0 +#define BIT_MASK_H2C_PRIORITY_SEL 0x3 +#define BIT_H2C_PRIORITY_SEL(x) \ + (((x) & BIT_MASK_H2C_PRIORITY_SEL) << BIT_SHIFT_H2C_PRIORITY_SEL) +#define BITS_H2C_PRIORITY_SEL \ + (BIT_MASK_H2C_PRIORITY_SEL << BIT_SHIFT_H2C_PRIORITY_SEL) +#define BIT_CLEAR_H2C_PRIORITY_SEL(x) ((x) & (~BITS_H2C_PRIORITY_SEL)) +#define BIT_GET_H2C_PRIORITY_SEL(x) \ + (((x) >> BIT_SHIFT_H2C_PRIORITY_SEL) & BIT_MASK_H2C_PRIORITY_SEL) +#define BIT_SET_H2C_PRIORITY_SEL(x, v) \ + (BIT_CLEAR_H2C_PRIORITY_SEL(x) | BIT_H2C_PRIORITY_SEL(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_EN_USB_CNT BIT(5) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_USB_COUNT_EN BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_EN_PCIE_CNT BIT(4) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_PCIE_COUNT_EN BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_RQPN_CNT BIT(3) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_RQPN_COUNT_EN BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_RDE_CNT BIT(2) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_RDE_COUNT_EN BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_TDE_CNT BIT(1) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_TDE_COUNT_EN BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */ + +#define BIT_DIS_CNT BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */ + +#define BIT_DISABLE_COUNTER BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_TH (Offset 0x11C8) */ + +#define BIT_CNT_ALL_MACID BIT(31) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_THRESHOLD (Offset 0x11C8) */ + +#define BIT_SEL_ALL_MACID BIT(31) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_TH (Offset 0x11C8) */ + +#define BIT_SHIFT_CNT_MACID 24 +#define BIT_MASK_CNT_MACID 0x7f +#define BIT_CNT_MACID(x) (((x) & BIT_MASK_CNT_MACID) << BIT_SHIFT_CNT_MACID) +#define BITS_CNT_MACID (BIT_MASK_CNT_MACID << BIT_SHIFT_CNT_MACID) +#define BIT_CLEAR_CNT_MACID(x) ((x) & (~BITS_CNT_MACID)) +#define BIT_GET_CNT_MACID(x) (((x) >> BIT_SHIFT_CNT_MACID) & BIT_MASK_CNT_MACID) +#define BIT_SET_CNT_MACID(x, v) (BIT_CLEAR_CNT_MACID(x) | BIT_CNT_MACID(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_THRESHOLD (Offset 0x11C8) */ + +#define BIT_SHIFT_COUNTER_MACID 24 +#define BIT_MASK_COUNTER_MACID 0x7f +#define BIT_COUNTER_MACID(x) \ + (((x) & BIT_MASK_COUNTER_MACID) << BIT_SHIFT_COUNTER_MACID) +#define BITS_COUNTER_MACID (BIT_MASK_COUNTER_MACID << BIT_SHIFT_COUNTER_MACID) +#define BIT_CLEAR_COUNTER_MACID(x) ((x) & (~BITS_COUNTER_MACID)) +#define BIT_GET_COUNTER_MACID(x) \ + (((x) >> BIT_SHIFT_COUNTER_MACID) & BIT_MASK_COUNTER_MACID) +#define BIT_SET_COUNTER_MACID(x, v) \ + (BIT_CLEAR_COUNTER_MACID(x) | BIT_COUNTER_MACID(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_SET (Offset 0x11CC) */ + +#define BIT_RTS_RST BIT(24) +#define BIT_PTCL_RST BIT(23) +#define BIT_SCH_RST BIT(22) +#define BIT_EDCA_RST BIT(21) +#define BIT_RQPN_RST BIT(20) +#define BIT_USB_RST BIT(19) +#define BIT_PCIE_RST BIT(18) +#define BIT_RXDMA_RST BIT(17) +#define BIT_TXDMA_RST BIT(16) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_SET (Offset 0x11CC) */ + +#define BIT_SHIFT_REQUEST_RESET 16 +#define BIT_MASK_REQUEST_RESET 0xffff +#define BIT_REQUEST_RESET(x) \ + (((x) & BIT_MASK_REQUEST_RESET) << BIT_SHIFT_REQUEST_RESET) +#define BITS_REQUEST_RESET (BIT_MASK_REQUEST_RESET << BIT_SHIFT_REQUEST_RESET) +#define BIT_CLEAR_REQUEST_RESET(x) ((x) & (~BITS_REQUEST_RESET)) +#define BIT_GET_REQUEST_RESET(x) \ + (((x) >> BIT_SHIFT_REQUEST_RESET) & BIT_MASK_REQUEST_RESET) +#define BIT_SET_REQUEST_RESET(x, v) \ + (BIT_CLEAR_REQUEST_RESET(x) | BIT_REQUEST_RESET(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_SET (Offset 0x11CC) */ + +#define BIT_EN_RTS_START BIT(8) +#define BIT_EN_PTCL_START BIT(7) +#define BIT_EN_SCH_START BIT(6) +#define BIT_EN_EDCA_START BIT(5) +#define BIT_EN_RQPN_START BIT(4) +#define BIT_EN_USB_START BIT(3) +#define BIT_EN_PCIE_START BIT(2) +#define BIT_EN_RXDMA_START BIT(1) +#define BIT_EN_TXDMA_START BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_SET (Offset 0x11CC) */ + +#define BIT_SHIFT_REQUEST_START 0 +#define BIT_MASK_REQUEST_START 0xffff +#define BIT_REQUEST_START(x) \ + (((x) & BIT_MASK_REQUEST_START) << BIT_SHIFT_REQUEST_START) +#define BITS_REQUEST_START (BIT_MASK_REQUEST_START << BIT_SHIFT_REQUEST_START) +#define BIT_CLEAR_REQUEST_START(x) ((x) & (~BITS_REQUEST_START)) +#define BIT_GET_REQUEST_START(x) \ + (((x) >> BIT_SHIFT_REQUEST_START) & BIT_MASK_REQUEST_START) +#define BIT_SET_REQUEST_START(x, v) \ + (BIT_CLEAR_REQUEST_START(x) | BIT_REQUEST_START(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_COUNTER_OVERFLOW (Offset 0x11D0) */ + +#define BIT_RTS_OVF BIT(8) +#define BIT_PTCL_OVF BIT(7) +#define BIT_SCH_OVF BIT(6) +#define BIT_EDCA_OVF BIT(5) +#define BIT_RQPN_OVF BIT(4) +#define BIT_USB_OVF BIT(3) +#define BIT_PCIE_OVF BIT(2) +#define BIT_RXDMA_OVF BIT(1) +#define BIT_TXDMA_OVF BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_COUNTER_OVERFLOW (Offset 0x11D0) */ + +#define BIT_SHIFT_CNT_OVF_REG 0 +#define BIT_MASK_CNT_OVF_REG 0xffff +#define BIT_CNT_OVF_REG(x) \ + (((x) & BIT_MASK_CNT_OVF_REG) << BIT_SHIFT_CNT_OVF_REG) +#define BITS_CNT_OVF_REG (BIT_MASK_CNT_OVF_REG << BIT_SHIFT_CNT_OVF_REG) +#define BIT_CLEAR_CNT_OVF_REG(x) ((x) & (~BITS_CNT_OVF_REG)) +#define BIT_GET_CNT_OVF_REG(x) \ + (((x) >> BIT_SHIFT_CNT_OVF_REG) & BIT_MASK_CNT_OVF_REG) +#define BIT_SET_CNT_OVF_REG(x, v) \ + (BIT_CLEAR_CNT_OVF_REG(x) | BIT_CNT_OVF_REG(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_TDE_LEN_TH (Offset 0x11D4) */ + +#define BIT_SHIFT_TXDMA_LEN_TH0 16 +#define BIT_MASK_TXDMA_LEN_TH0 0xffff +#define BIT_TXDMA_LEN_TH0(x) \ + (((x) & BIT_MASK_TXDMA_LEN_TH0) << BIT_SHIFT_TXDMA_LEN_TH0) +#define BITS_TXDMA_LEN_TH0 (BIT_MASK_TXDMA_LEN_TH0 << BIT_SHIFT_TXDMA_LEN_TH0) +#define BIT_CLEAR_TXDMA_LEN_TH0(x) ((x) & (~BITS_TXDMA_LEN_TH0)) +#define BIT_GET_TXDMA_LEN_TH0(x) \ + (((x) >> BIT_SHIFT_TXDMA_LEN_TH0) & BIT_MASK_TXDMA_LEN_TH0) +#define BIT_SET_TXDMA_LEN_TH0(x, v) \ + (BIT_CLEAR_TXDMA_LEN_TH0(x) | BIT_TXDMA_LEN_TH0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_TXDMA_LEN_THRESHOLD (Offset 0x11D4) */ + +#define BIT_SHIFT_TDE_LEN_TH1 16 +#define BIT_MASK_TDE_LEN_TH1 0xffff +#define BIT_TDE_LEN_TH1(x) \ + (((x) & BIT_MASK_TDE_LEN_TH1) << BIT_SHIFT_TDE_LEN_TH1) +#define BITS_TDE_LEN_TH1 (BIT_MASK_TDE_LEN_TH1 << BIT_SHIFT_TDE_LEN_TH1) +#define BIT_CLEAR_TDE_LEN_TH1(x) ((x) & (~BITS_TDE_LEN_TH1)) +#define BIT_GET_TDE_LEN_TH1(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH1) & BIT_MASK_TDE_LEN_TH1) +#define BIT_SET_TDE_LEN_TH1(x, v) \ + (BIT_CLEAR_TDE_LEN_TH1(x) | BIT_TDE_LEN_TH1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_TDE_LEN_TH (Offset 0x11D4) */ + +#define BIT_SHIFT_TXDMA_LEN_TH1 0 +#define BIT_MASK_TXDMA_LEN_TH1 0xffff +#define BIT_TXDMA_LEN_TH1(x) \ + (((x) & BIT_MASK_TXDMA_LEN_TH1) << BIT_SHIFT_TXDMA_LEN_TH1) +#define BITS_TXDMA_LEN_TH1 (BIT_MASK_TXDMA_LEN_TH1 << BIT_SHIFT_TXDMA_LEN_TH1) +#define BIT_CLEAR_TXDMA_LEN_TH1(x) ((x) & (~BITS_TXDMA_LEN_TH1)) +#define BIT_GET_TXDMA_LEN_TH1(x) \ + (((x) >> BIT_SHIFT_TXDMA_LEN_TH1) & BIT_MASK_TXDMA_LEN_TH1) +#define BIT_SET_TXDMA_LEN_TH1(x, v) \ + (BIT_CLEAR_TXDMA_LEN_TH1(x) | BIT_TXDMA_LEN_TH1(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_TXDMA_LEN_THRESHOLD (Offset 0x11D4) */ + +#define BIT_SHIFT_TDE_LEN_TH0 0 +#define BIT_MASK_TDE_LEN_TH0 0xffff +#define BIT_TDE_LEN_TH0(x) \ + (((x) & BIT_MASK_TDE_LEN_TH0) << BIT_SHIFT_TDE_LEN_TH0) +#define BITS_TDE_LEN_TH0 (BIT_MASK_TDE_LEN_TH0 << BIT_SHIFT_TDE_LEN_TH0) +#define BIT_CLEAR_TDE_LEN_TH0(x) ((x) & (~BITS_TDE_LEN_TH0)) +#define BIT_GET_TDE_LEN_TH0(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH0) & BIT_MASK_TDE_LEN_TH0) +#define BIT_SET_TDE_LEN_TH0(x, v) \ + (BIT_CLEAR_TDE_LEN_TH0(x) | BIT_TDE_LEN_TH0(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_RDE_LEN_TH (Offset 0x11D8) */ + +#define BIT_SHIFT_RXDMA_LEN_TH0 16 +#define BIT_MASK_RXDMA_LEN_TH0 0xffff +#define BIT_RXDMA_LEN_TH0(x) \ + (((x) & BIT_MASK_RXDMA_LEN_TH0) << BIT_SHIFT_RXDMA_LEN_TH0) +#define BITS_RXDMA_LEN_TH0 (BIT_MASK_RXDMA_LEN_TH0 << BIT_SHIFT_RXDMA_LEN_TH0) +#define BIT_CLEAR_RXDMA_LEN_TH0(x) ((x) & (~BITS_RXDMA_LEN_TH0)) +#define BIT_GET_RXDMA_LEN_TH0(x) \ + (((x) >> BIT_SHIFT_RXDMA_LEN_TH0) & BIT_MASK_RXDMA_LEN_TH0) +#define BIT_SET_RXDMA_LEN_TH0(x, v) \ + (BIT_CLEAR_RXDMA_LEN_TH0(x) | BIT_RXDMA_LEN_TH0(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_RXDMA_LEN_THRESHOLD (Offset 0x11D8) */ + +#define BIT_SHIFT_RDE_LEN_TH1 16 +#define BIT_MASK_RDE_LEN_TH1 0xffff +#define BIT_RDE_LEN_TH1(x) \ + (((x) & BIT_MASK_RDE_LEN_TH1) << BIT_SHIFT_RDE_LEN_TH1) +#define BITS_RDE_LEN_TH1 (BIT_MASK_RDE_LEN_TH1 << BIT_SHIFT_RDE_LEN_TH1) +#define BIT_CLEAR_RDE_LEN_TH1(x) ((x) & (~BITS_RDE_LEN_TH1)) +#define BIT_GET_RDE_LEN_TH1(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH1) & BIT_MASK_RDE_LEN_TH1) +#define BIT_SET_RDE_LEN_TH1(x, v) \ + (BIT_CLEAR_RDE_LEN_TH1(x) | BIT_RDE_LEN_TH1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_RDE_LEN_TH (Offset 0x11D8) */ + +#define BIT_SHIFT_RXDMA_LEN_TH1 0 +#define BIT_MASK_RXDMA_LEN_TH1 0xffff +#define BIT_RXDMA_LEN_TH1(x) \ + (((x) & BIT_MASK_RXDMA_LEN_TH1) << BIT_SHIFT_RXDMA_LEN_TH1) +#define BITS_RXDMA_LEN_TH1 (BIT_MASK_RXDMA_LEN_TH1 << BIT_SHIFT_RXDMA_LEN_TH1) +#define BIT_CLEAR_RXDMA_LEN_TH1(x) ((x) & (~BITS_RXDMA_LEN_TH1)) +#define BIT_GET_RXDMA_LEN_TH1(x) \ + (((x) >> BIT_SHIFT_RXDMA_LEN_TH1) & BIT_MASK_RXDMA_LEN_TH1) +#define BIT_SET_RXDMA_LEN_TH1(x, v) \ + (BIT_CLEAR_RXDMA_LEN_TH1(x) | BIT_RXDMA_LEN_TH1(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_RXDMA_LEN_THRESHOLD (Offset 0x11D8) */ + +#define BIT_SHIFT_RDE_LEN_TH0 0 +#define BIT_MASK_RDE_LEN_TH0 0xffff +#define BIT_RDE_LEN_TH0(x) \ + (((x) & BIT_MASK_RDE_LEN_TH0) << BIT_SHIFT_RDE_LEN_TH0) +#define BITS_RDE_LEN_TH0 (BIT_MASK_RDE_LEN_TH0 << BIT_SHIFT_RDE_LEN_TH0) +#define BIT_CLEAR_RDE_LEN_TH0(x) ((x) & (~BITS_RDE_LEN_TH0)) +#define BIT_GET_RDE_LEN_TH0(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH0) & BIT_MASK_RDE_LEN_TH0) +#define BIT_SET_RDE_LEN_TH0(x, v) \ + (BIT_CLEAR_RDE_LEN_TH0(x) | BIT_RDE_LEN_TH0(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_PCIE_EXEC_TIME (Offset 0x11DC) */ + +#define BIT_SHIFT_COUNTER_INTERVAL_SEL 16 +#define BIT_MASK_COUNTER_INTERVAL_SEL 0x3 +#define BIT_COUNTER_INTERVAL_SEL(x) \ + (((x) & BIT_MASK_COUNTER_INTERVAL_SEL) \ + << BIT_SHIFT_COUNTER_INTERVAL_SEL) +#define BITS_COUNTER_INTERVAL_SEL \ + (BIT_MASK_COUNTER_INTERVAL_SEL << BIT_SHIFT_COUNTER_INTERVAL_SEL) +#define BIT_CLEAR_COUNTER_INTERVAL_SEL(x) ((x) & (~BITS_COUNTER_INTERVAL_SEL)) +#define BIT_GET_COUNTER_INTERVAL_SEL(x) \ + (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL) & \ + BIT_MASK_COUNTER_INTERVAL_SEL) +#define BIT_SET_COUNTER_INTERVAL_SEL(x, v) \ + (BIT_CLEAR_COUNTER_INTERVAL_SEL(x) | BIT_COUNTER_INTERVAL_SEL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_PCIE_EXEC_TIME_THRESHOLD (Offset 0x11DC) */ + +#define BIT_SHIFT_COUNT_INT_SEL 16 +#define BIT_MASK_COUNT_INT_SEL 0x3 +#define BIT_COUNT_INT_SEL(x) \ + (((x) & BIT_MASK_COUNT_INT_SEL) << BIT_SHIFT_COUNT_INT_SEL) +#define BITS_COUNT_INT_SEL (BIT_MASK_COUNT_INT_SEL << BIT_SHIFT_COUNT_INT_SEL) +#define BIT_CLEAR_COUNT_INT_SEL(x) ((x) & (~BITS_COUNT_INT_SEL)) +#define BIT_GET_COUNT_INT_SEL(x) \ + (((x) >> BIT_SHIFT_COUNT_INT_SEL) & BIT_MASK_COUNT_INT_SEL) +#define BIT_SET_COUNT_INT_SEL(x, v) \ + (BIT_CLEAR_COUNT_INT_SEL(x) | BIT_COUNT_INT_SEL(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +/* 2 REG_PCIE_EXEC_TIME (Offset 0x11DC) */ + +#define BIT_SHIFT_PCIE_TRANS_DATA_TH1 0 +#define BIT_MASK_PCIE_TRANS_DATA_TH1 0xffff +#define BIT_PCIE_TRANS_DATA_TH1(x) \ + (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1) << BIT_SHIFT_PCIE_TRANS_DATA_TH1) +#define BITS_PCIE_TRANS_DATA_TH1 \ + (BIT_MASK_PCIE_TRANS_DATA_TH1 << BIT_SHIFT_PCIE_TRANS_DATA_TH1) +#define BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) ((x) & (~BITS_PCIE_TRANS_DATA_TH1)) +#define BIT_GET_PCIE_TRANS_DATA_TH1(x) \ + (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1) & BIT_MASK_PCIE_TRANS_DATA_TH1) +#define BIT_SET_PCIE_TRANS_DATA_TH1(x, v) \ + (BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) | BIT_PCIE_TRANS_DATA_TH1(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_PCIE_EXEC_TIME_THRESHOLD (Offset 0x11DC) */ + +#define BIT_SHIFT_EXEC_TIME_TH 0 +#define BIT_MASK_EXEC_TIME_TH 0xffff +#define BIT_EXEC_TIME_TH(x) \ + (((x) & BIT_MASK_EXEC_TIME_TH) << BIT_SHIFT_EXEC_TIME_TH) +#define BITS_EXEC_TIME_TH (BIT_MASK_EXEC_TIME_TH << BIT_SHIFT_EXEC_TIME_TH) +#define BIT_CLEAR_EXEC_TIME_TH(x) ((x) & (~BITS_EXEC_TIME_TH)) +#define BIT_GET_EXEC_TIME_TH(x) \ + (((x) >> BIT_SHIFT_EXEC_TIME_TH) & BIT_MASK_EXEC_TIME_TH) +#define BIT_SET_EXEC_TIME_TH(x, v) \ + (BIT_CLEAR_EXEC_TIME_TH(x) | BIT_EXEC_TIME_TH(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN BIT(31) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN BIT(30) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_TRIPKT_OK_INT_EN BIT(29) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_RX_EOSP_OK_INT_EN BIT(28) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_EOSP_INT_EN BIT(28) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN BIT(27) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN BIT(26) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_TRIPKT_OK_INT_EN BIT(25) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_RX_EOSP_OK_INT_EN BIT(24) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_EOSP_INT_EN BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN BIT(23) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN BIT(22) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT2_TRIPKT_OK_INT_EN BIT(21) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT2_RX_EOSP_OK_INT_EN BIT(20) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI1_EOSP_INT_EN BIT(20) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN BIT(19) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN BIT(18) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT1_TRIPKT_OK_INT_EN BIT(17) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT1_RX_EOSP_OK_INT_EN BIT(16) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI0_EOSP_INT_EN BIT(16) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN BIT(9) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN BIT(8) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_TX_NULL1_DONE_INT_EN BIT(7) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT4_TX_NULL0_DONE_INT_EN BIT(6) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_TX_NULL1_DONE_INT_EN BIT(5) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT3_TX_NULL0_DONE_INT_EN BIT(4) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT2_TX_NULL1_DONE_INT_EN BIT(3) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT2_TX_NULL0_DONE_INT_EN BIT(2) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT1_TX_NULL1_DONE_INT_EN BIT(1) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_PORT1_TX_NULL0_DONE_INT_EN BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2IMR (Offset 0x11E0) */ + +#define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT BIT(31) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT BIT(30) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT4_TRIPKT_OK_INT BIT(29) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT4_RX_EOSP_OK_INT BIT(28) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI3_EOSP_INT BIT(28) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT BIT(27) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT BIT(26) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT3_TRIPKT_OK_INT BIT(25) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT3_RX_EOSP_OK_INT BIT(24) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI2_EOSP_INT BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT BIT(23) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT BIT(22) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT2_TRIPKT_OK_INT BIT(21) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT2_RX_EOSP_OK_INT BIT(20) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI1_EOSP_INT BIT(20) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT BIT(19) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT BIT(18) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT1_TRIPKT_OK_INT BIT(17) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT1_RX_EOSP_OK_INT BIT(16) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI0_EOSP_INT BIT(16) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT BIT(9) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT BIT(8) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT4_TX_NULL1_DONE_INT BIT(7) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI3_TX_NULL1_INT BIT(7) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT4_TX_NULL0_DONE_INT BIT(6) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI3_TX_NULL0_INT BIT(6) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT3_TX_NULL1_DONE_INT BIT(5) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI2_TX_NULL1_INT BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT3_TX_NULL0_DONE_INT BIT(4) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI2_TX_NULL0_INT BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT2_TX_NULL1_DONE_INT BIT(3) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI1_TX_NULL1_INT BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT2_TX_NULL0_DONE_INT BIT(2) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI1_TX_NULL0_INT BIT(2) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT1_TX_NULL1_DONE_INT BIT(1) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI0_TX_NULL1_INT BIT(1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_PORT1_TX_NULL0_DONE_INT BIT(0) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_FT2ISR (Offset 0x11E4) */ + +#define BIT_FS_CLI0_TX_NULL0_INT BIT(0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MSG2 (Offset 0x11F0) */ + +#define BIT_SHIFT_FW_MSG2 0 +#define BIT_MASK_FW_MSG2 0xffffffffL +#define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2) +#define BITS_FW_MSG2 (BIT_MASK_FW_MSG2 << BIT_SHIFT_FW_MSG2) +#define BIT_CLEAR_FW_MSG2(x) ((x) & (~BITS_FW_MSG2)) +#define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2) +#define BIT_SET_FW_MSG2(x, v) (BIT_CLEAR_FW_MSG2(x) | BIT_FW_MSG2(v)) + +/* 2 REG_MSG3 (Offset 0x11F4) */ + +#define BIT_SHIFT_FW_MSG3 0 +#define BIT_MASK_FW_MSG3 0xffffffffL +#define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3) +#define BITS_FW_MSG3 (BIT_MASK_FW_MSG3 << BIT_SHIFT_FW_MSG3) +#define BIT_CLEAR_FW_MSG3(x) ((x) & (~BITS_FW_MSG3)) +#define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3) +#define BIT_SET_FW_MSG3(x, v) (BIT_CLEAR_FW_MSG3(x) | BIT_FW_MSG3(v)) + +/* 2 REG_MSG4 (Offset 0x11F8) */ + +#define BIT_SHIFT_FW_MSG4 0 +#define BIT_MASK_FW_MSG4 0xffffffffL +#define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4) +#define BITS_FW_MSG4 (BIT_MASK_FW_MSG4 << BIT_SHIFT_FW_MSG4) +#define BIT_CLEAR_FW_MSG4(x) ((x) & (~BITS_FW_MSG4)) +#define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4) +#define BIT_SET_FW_MSG4(x, v) (BIT_CLEAR_FW_MSG4(x) | BIT_FW_MSG4(v)) + +/* 2 REG_MSG5 (Offset 0x11FC) */ + +#define BIT_SHIFT_FW_MSG5 0 +#define BIT_MASK_FW_MSG5 0xffffffffL +#define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5) +#define BITS_FW_MSG5 (BIT_MASK_FW_MSG5 << BIT_SHIFT_FW_MSG5) +#define BIT_CLEAR_FW_MSG5(x) ((x) & (~BITS_FW_MSG5)) +#define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5) +#define BIT_SET_FW_MSG5(x, v) (BIT_CLEAR_FW_MSG5(x) | BIT_FW_MSG5(v)) + +/* 2 REG_DDMA_CH0SA (Offset 0x1200) */ + +#define BIT_SHIFT_DDMACH0_SA 0 +#define BIT_MASK_DDMACH0_SA 0xffffffffL +#define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA) +#define BITS_DDMACH0_SA (BIT_MASK_DDMACH0_SA << BIT_SHIFT_DDMACH0_SA) +#define BIT_CLEAR_DDMACH0_SA(x) ((x) & (~BITS_DDMACH0_SA)) +#define BIT_GET_DDMACH0_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA) +#define BIT_SET_DDMACH0_SA(x, v) (BIT_CLEAR_DDMACH0_SA(x) | BIT_DDMACH0_SA(v)) + +/* 2 REG_DDMA_CH0DA (Offset 0x1204) */ + +#define BIT_SHIFT_DDMACH0_DA 0 +#define BIT_MASK_DDMACH0_DA 0xffffffffL +#define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA) +#define BITS_DDMACH0_DA (BIT_MASK_DDMACH0_DA << BIT_SHIFT_DDMACH0_DA) +#define BIT_CLEAR_DDMACH0_DA(x) ((x) & (~BITS_DDMACH0_DA)) +#define BIT_GET_DDMACH0_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA) +#define BIT_SET_DDMACH0_DA(x, v) (BIT_CLEAR_DDMACH0_DA(x) | BIT_DDMACH0_DA(v)) + +/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ + +#define BIT_DDMACH0_OWN BIT(31) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ + +#define BIT_DDMACH0_ERR_MON BIT(30) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ + +#define BIT_DDMACH0_IDMEM_ERR BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ + +#define BIT_DDMACH0_CHKSUM_EN BIT(29) +#define BIT_DDMACH0_DA_W_DISABLE BIT(28) +#define BIT_DDMACH0_CHKSUM_STS BIT(27) +#define BIT_DDMACH0_DDMA_MODE BIT(26) +#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH0_CHKSUM_CONT BIT(24) + +#define BIT_SHIFT_DDMACH0_DLEN 0 +#define BIT_MASK_DDMACH0_DLEN 0x3ffff +#define BIT_DDMACH0_DLEN(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN) +#define BITS_DDMACH0_DLEN (BIT_MASK_DDMACH0_DLEN << BIT_SHIFT_DDMACH0_DLEN) +#define BIT_CLEAR_DDMACH0_DLEN(x) ((x) & (~BITS_DDMACH0_DLEN)) +#define BIT_GET_DDMACH0_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN) +#define BIT_SET_DDMACH0_DLEN(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN(x) | BIT_DDMACH0_DLEN(v)) + +/* 2 REG_DDMA_CH1SA (Offset 0x1210) */ + +#define BIT_SHIFT_DDMACH1_SA 0 +#define BIT_MASK_DDMACH1_SA 0xffffffffL +#define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA) +#define BITS_DDMACH1_SA (BIT_MASK_DDMACH1_SA << BIT_SHIFT_DDMACH1_SA) +#define BIT_CLEAR_DDMACH1_SA(x) ((x) & (~BITS_DDMACH1_SA)) +#define BIT_GET_DDMACH1_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA) +#define BIT_SET_DDMACH1_SA(x, v) (BIT_CLEAR_DDMACH1_SA(x) | BIT_DDMACH1_SA(v)) + +/* 2 REG_DDMA_CH1DA (Offset 0x1214) */ + +#define BIT_SHIFT_DDMACH1_DA 0 +#define BIT_MASK_DDMACH1_DA 0xffffffffL +#define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA) +#define BITS_DDMACH1_DA (BIT_MASK_DDMACH1_DA << BIT_SHIFT_DDMACH1_DA) +#define BIT_CLEAR_DDMACH1_DA(x) ((x) & (~BITS_DDMACH1_DA)) +#define BIT_GET_DDMACH1_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA) +#define BIT_SET_DDMACH1_DA(x, v) (BIT_CLEAR_DDMACH1_DA(x) | BIT_DDMACH1_DA(v)) + +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ + +#define BIT_DDMACH1_OWN BIT(31) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ + +#define BIT_DDMACH1_ERR_MON BIT(30) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ + +#define BIT_DDMACH1_IDMEM_ERR BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ + +#define BIT_DDMACH1_CHKSUM_EN BIT(29) +#define BIT_DDMACH1_DA_W_DISABLE BIT(28) +#define BIT_DDMACH1_CHKSUM_STS BIT(27) +#define BIT_DDMACH1_DDMA_MODE BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) + +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ + +#define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH1_CHKSUM_CONT BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ + +#define BIT_SHIFT_DDMACH1_DLEN 0 +#define BIT_MASK_DDMACH1_DLEN 0x3ffff +#define BIT_DDMACH1_DLEN(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN) +#define BITS_DDMACH1_DLEN (BIT_MASK_DDMACH1_DLEN << BIT_SHIFT_DDMACH1_DLEN) +#define BIT_CLEAR_DDMACH1_DLEN(x) ((x) & (~BITS_DDMACH1_DLEN)) +#define BIT_GET_DDMACH1_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN) +#define BIT_SET_DDMACH1_DLEN(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN(x) | BIT_DDMACH1_DLEN(v)) + +/* 2 REG_DDMA_CH2SA (Offset 0x1220) */ + +#define BIT_SHIFT_DDMACH2_SA 0 +#define BIT_MASK_DDMACH2_SA 0xffffffffL +#define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA) +#define BITS_DDMACH2_SA (BIT_MASK_DDMACH2_SA << BIT_SHIFT_DDMACH2_SA) +#define BIT_CLEAR_DDMACH2_SA(x) ((x) & (~BITS_DDMACH2_SA)) +#define BIT_GET_DDMACH2_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA) +#define BIT_SET_DDMACH2_SA(x, v) (BIT_CLEAR_DDMACH2_SA(x) | BIT_DDMACH2_SA(v)) + +/* 2 REG_DDMA_CH2DA (Offset 0x1224) */ + +#define BIT_SHIFT_DDMACH2_DA 0 +#define BIT_MASK_DDMACH2_DA 0xffffffffL +#define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA) +#define BITS_DDMACH2_DA (BIT_MASK_DDMACH2_DA << BIT_SHIFT_DDMACH2_DA) +#define BIT_CLEAR_DDMACH2_DA(x) ((x) & (~BITS_DDMACH2_DA)) +#define BIT_GET_DDMACH2_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA) +#define BIT_SET_DDMACH2_DA(x, v) (BIT_CLEAR_DDMACH2_DA(x) | BIT_DDMACH2_DA(v)) + +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ + +#define BIT_DDMACH2_OWN BIT(31) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ + +#define BIT_DDMACH2_ERR_MON BIT(30) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ + +#define BIT_DDMACH2_IDMEM_ERR BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ + +#define BIT_DDMACH2_CHKSUM_EN BIT(29) +#define BIT_DDMACH2_DA_W_DISABLE BIT(28) +#define BIT_DDMACH2_CHKSUM_STS BIT(27) +#define BIT_DDMACH2_DDMA_MODE BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) + +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ + +#define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH2_CHKSUM_CONT BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ + +#define BIT_SHIFT_DDMACH2_DLEN 0 +#define BIT_MASK_DDMACH2_DLEN 0x3ffff +#define BIT_DDMACH2_DLEN(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN) +#define BITS_DDMACH2_DLEN (BIT_MASK_DDMACH2_DLEN << BIT_SHIFT_DDMACH2_DLEN) +#define BIT_CLEAR_DDMACH2_DLEN(x) ((x) & (~BITS_DDMACH2_DLEN)) +#define BIT_GET_DDMACH2_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN) +#define BIT_SET_DDMACH2_DLEN(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN(x) | BIT_DDMACH2_DLEN(v)) + +/* 2 REG_DDMA_CH3SA (Offset 0x1230) */ + +#define BIT_SHIFT_DDMACH3_SA 0 +#define BIT_MASK_DDMACH3_SA 0xffffffffL +#define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA) +#define BITS_DDMACH3_SA (BIT_MASK_DDMACH3_SA << BIT_SHIFT_DDMACH3_SA) +#define BIT_CLEAR_DDMACH3_SA(x) ((x) & (~BITS_DDMACH3_SA)) +#define BIT_GET_DDMACH3_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA) +#define BIT_SET_DDMACH3_SA(x, v) (BIT_CLEAR_DDMACH3_SA(x) | BIT_DDMACH3_SA(v)) + +/* 2 REG_DDMA_CH3DA (Offset 0x1234) */ + +#define BIT_SHIFT_DDMACH3_DA 0 +#define BIT_MASK_DDMACH3_DA 0xffffffffL +#define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA) +#define BITS_DDMACH3_DA (BIT_MASK_DDMACH3_DA << BIT_SHIFT_DDMACH3_DA) +#define BIT_CLEAR_DDMACH3_DA(x) ((x) & (~BITS_DDMACH3_DA)) +#define BIT_GET_DDMACH3_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA) +#define BIT_SET_DDMACH3_DA(x, v) (BIT_CLEAR_DDMACH3_DA(x) | BIT_DDMACH3_DA(v)) + +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ + +#define BIT_DDMACH3_OWN BIT(31) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ + +#define BIT_DDMACH3_ERR_MON BIT(30) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ + +#define BIT_DDMACH3_IDMEM_ERR BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ + +#define BIT_DDMACH3_CHKSUM_EN BIT(29) +#define BIT_DDMACH3_DA_W_DISABLE BIT(28) +#define BIT_DDMACH3_CHKSUM_STS BIT(27) +#define BIT_DDMACH3_DDMA_MODE BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) + +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ + +#define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH3_CHKSUM_CONT BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ + +#define BIT_SHIFT_DDMACH3_DLEN 0 +#define BIT_MASK_DDMACH3_DLEN 0x3ffff +#define BIT_DDMACH3_DLEN(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN) +#define BITS_DDMACH3_DLEN (BIT_MASK_DDMACH3_DLEN << BIT_SHIFT_DDMACH3_DLEN) +#define BIT_CLEAR_DDMACH3_DLEN(x) ((x) & (~BITS_DDMACH3_DLEN)) +#define BIT_GET_DDMACH3_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN) +#define BIT_SET_DDMACH3_DLEN(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN(x) | BIT_DDMACH3_DLEN(v)) + +/* 2 REG_DDMA_CH4SA (Offset 0x1240) */ + +#define BIT_SHIFT_DDMACH4_SA 0 +#define BIT_MASK_DDMACH4_SA 0xffffffffL +#define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA) +#define BITS_DDMACH4_SA (BIT_MASK_DDMACH4_SA << BIT_SHIFT_DDMACH4_SA) +#define BIT_CLEAR_DDMACH4_SA(x) ((x) & (~BITS_DDMACH4_SA)) +#define BIT_GET_DDMACH4_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA) +#define BIT_SET_DDMACH4_SA(x, v) (BIT_CLEAR_DDMACH4_SA(x) | BIT_DDMACH4_SA(v)) + +/* 2 REG_DDMA_CH4DA (Offset 0x1244) */ + +#define BIT_SHIFT_DDMACH4_DA 0 +#define BIT_MASK_DDMACH4_DA 0xffffffffL +#define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA) +#define BITS_DDMACH4_DA (BIT_MASK_DDMACH4_DA << BIT_SHIFT_DDMACH4_DA) +#define BIT_CLEAR_DDMACH4_DA(x) ((x) & (~BITS_DDMACH4_DA)) +#define BIT_GET_DDMACH4_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA) +#define BIT_SET_DDMACH4_DA(x, v) (BIT_CLEAR_DDMACH4_DA(x) | BIT_DDMACH4_DA(v)) + +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ + +#define BIT_DDMACH4_OWN BIT(31) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ + +#define BIT_DDMACH4_ERR_MON BIT(30) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ + +#define BIT_DDMACH4_IDMEM_ERR BIT(30) +#define BIT_DDMACH5_IDMEM_ERR BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ + +#define BIT_DDMACH4_CHKSUM_EN BIT(29) +#define BIT_DDMACH4_DA_W_DISABLE BIT(28) +#define BIT_DDMACH4_CHKSUM_STS BIT(27) +#define BIT_DDMACH4_DDMA_MODE BIT(26) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) + +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ + +#define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH4_CHKSUM_CONT BIT(24) +#define BIT_DDMACH5_CHKSUM_CONT BIT(24) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ + +#define BIT_SHIFT_DDMACH4_DLEN 0 +#define BIT_MASK_DDMACH4_DLEN 0x3ffff +#define BIT_DDMACH4_DLEN(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN) +#define BITS_DDMACH4_DLEN (BIT_MASK_DDMACH4_DLEN << BIT_SHIFT_DDMACH4_DLEN) +#define BIT_CLEAR_DDMACH4_DLEN(x) ((x) & (~BITS_DDMACH4_DLEN)) +#define BIT_GET_DDMACH4_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN) +#define BIT_SET_DDMACH4_DLEN(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN(x) | BIT_DDMACH4_DLEN(v)) + +/* 2 REG_DDMA_CH5SA (Offset 0x1250) */ + +#define BIT_SHIFT_DDMACH5_SA 0 +#define BIT_MASK_DDMACH5_SA 0xffffffffL +#define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA) +#define BITS_DDMACH5_SA (BIT_MASK_DDMACH5_SA << BIT_SHIFT_DDMACH5_SA) +#define BIT_CLEAR_DDMACH5_SA(x) ((x) & (~BITS_DDMACH5_SA)) +#define BIT_GET_DDMACH5_SA(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA) +#define BIT_SET_DDMACH5_SA(x, v) (BIT_CLEAR_DDMACH5_SA(x) | BIT_DDMACH5_SA(v)) + +/* 2 REG_DDMA_CH5DA (Offset 0x1254) */ + +#define BIT_DDMACH5_OWN BIT(31) +#define BIT_DDMACH5_CHKSUM_EN BIT(29) +#define BIT_DDMACH5_DA_W_DISABLE BIT(28) +#define BIT_DDMACH5_CHKSUM_STS BIT(27) +#define BIT_DDMACH5_DDMA_MODE BIT(26) + +#define BIT_SHIFT_DDMACH5_DA 0 +#define BIT_MASK_DDMACH5_DA 0xffffffffL +#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA) +#define BITS_DDMACH5_DA (BIT_MASK_DDMACH5_DA << BIT_SHIFT_DDMACH5_DA) +#define BIT_CLEAR_DDMACH5_DA(x) ((x) & (~BITS_DDMACH5_DA)) +#define BIT_GET_DDMACH5_DA(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA) +#define BIT_SET_DDMACH5_DA(x, v) (BIT_CLEAR_DDMACH5_DA(x) | BIT_DDMACH5_DA(v)) + +#define BIT_SHIFT_DDMACH5_DLEN 0 +#define BIT_MASK_DDMACH5_DLEN 0x3ffff +#define BIT_DDMACH5_DLEN(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN) +#define BITS_DDMACH5_DLEN (BIT_MASK_DDMACH5_DLEN << BIT_SHIFT_DDMACH5_DLEN) +#define BIT_CLEAR_DDMACH5_DLEN(x) ((x) & (~BITS_DDMACH5_DLEN)) +#define BIT_GET_DDMACH5_DLEN(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN) +#define BIT_SET_DDMACH5_DLEN(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN(x) | BIT_DDMACH5_DLEN(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_REG_DDMA_CH5CTRL (Offset 0x1258) */ + +#define BIT_DDMACH5_ERR_MON BIT(30) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DDMA_INT_MSK (Offset 0x12E0) */ + +#define BIT_DDMACH5_MSK BIT(5) +#define BIT_DDMACH4_MSK BIT(4) +#define BIT_DDMACH3_MSK BIT(3) +#define BIT_DDMACH2_MSK BIT(2) +#define BIT_DDMACH1_MSK BIT(1) +#define BIT_DDMACH0_MSK BIT(0) + +/* 2 REG_DDMA_CHSTATUS (Offset 0x12E8) */ + +#define BIT_DDMACH5_BUSY BIT(5) +#define BIT_DDMACH4_BUSY BIT(4) +#define BIT_DDMACH3_BUSY BIT(3) +#define BIT_DDMACH2_BUSY BIT(2) +#define BIT_DDMACH1_BUSY BIT(1) +#define BIT_DDMACH0_BUSY BIT(0) + +/* 2 REG_DDMA_CHKSUM (Offset 0x12F0) */ + +#define BIT_SHIFT_IDDMA0_CHKSUM 0 +#define BIT_MASK_IDDMA0_CHKSUM 0xffff +#define BIT_IDDMA0_CHKSUM(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM) +#define BITS_IDDMA0_CHKSUM (BIT_MASK_IDDMA0_CHKSUM << BIT_SHIFT_IDDMA0_CHKSUM) +#define BIT_CLEAR_IDDMA0_CHKSUM(x) ((x) & (~BITS_IDDMA0_CHKSUM)) +#define BIT_GET_IDDMA0_CHKSUM(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM) +#define BIT_SET_IDDMA0_CHKSUM(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM(x) | BIT_IDDMA0_CHKSUM(v)) + +/* 2 REG_DDMA_MONITOR (Offset 0x12FC) */ + +#define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14) +#define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13) +#define BIT_IDDMA0_FIFO_OVERFLOW BIT(12) +#define BIT_CH5_ERR BIT(5) +#define BIT_CH4_ERR BIT(4) +#define BIT_CH3_ERR BIT(3) +#define BIT_CH2_ERR BIT(2) +#define BIT_CH1_ERR BIT(1) +#define BIT_CH0_ERR BIT(0) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_STC_INT_CS (Offset 0x1300) */ + +#define BIT_STC_INT_EN BIT(31) +#define BIT_STC_INT_GRP_EN BIT(31) + +#define BIT_SHIFT_STC_INT_FLAG 16 +#define BIT_MASK_STC_INT_FLAG 0xff +#define BIT_STC_INT_FLAG(x) \ + (((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG) +#define BITS_STC_INT_FLAG (BIT_MASK_STC_INT_FLAG << BIT_SHIFT_STC_INT_FLAG) +#define BIT_CLEAR_STC_INT_FLAG(x) ((x) & (~BITS_STC_INT_FLAG)) +#define BIT_GET_STC_INT_FLAG(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG) +#define BIT_SET_STC_INT_FLAG(x, v) \ + (BIT_CLEAR_STC_INT_FLAG(x) | BIT_STC_INT_FLAG(v)) + +#define BIT_SHIFT_STC_INT_IDX 8 +#define BIT_MASK_STC_INT_IDX 0x7 +#define BIT_STC_INT_IDX(x) \ + (((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX) +#define BITS_STC_INT_IDX (BIT_MASK_STC_INT_IDX << BIT_SHIFT_STC_INT_IDX) +#define BIT_CLEAR_STC_INT_IDX(x) ((x) & (~BITS_STC_INT_IDX)) +#define BIT_GET_STC_INT_IDX(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX) +#define BIT_SET_STC_INT_IDX(x, v) \ + (BIT_CLEAR_STC_INT_IDX(x) | BIT_STC_INT_IDX(v)) + +#define BIT_SHIFT_STC_INT_EXPECT_LS 8 +#define BIT_MASK_STC_INT_EXPECT_LS 0x3f +#define BIT_STC_INT_EXPECT_LS(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS) +#define BITS_STC_INT_EXPECT_LS \ + (BIT_MASK_STC_INT_EXPECT_LS << BIT_SHIFT_STC_INT_EXPECT_LS) +#define BIT_CLEAR_STC_INT_EXPECT_LS(x) ((x) & (~BITS_STC_INT_EXPECT_LS)) +#define BIT_GET_STC_INT_EXPECT_LS(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS) +#define BIT_SET_STC_INT_EXPECT_LS(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS(x) | BIT_STC_INT_EXPECT_LS(v)) + +#define BIT_SHIFT_STC_INT_REALTIME_CS 0 +#define BIT_MASK_STC_INT_REALTIME_CS 0x3f +#define BIT_STC_INT_REALTIME_CS(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS) +#define BITS_STC_INT_REALTIME_CS \ + (BIT_MASK_STC_INT_REALTIME_CS << BIT_SHIFT_STC_INT_REALTIME_CS) +#define BIT_CLEAR_STC_INT_REALTIME_CS(x) ((x) & (~BITS_STC_INT_REALTIME_CS)) +#define BIT_GET_STC_INT_REALTIME_CS(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS) +#define BIT_SET_STC_INT_REALTIME_CS(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS(x) | BIT_STC_INT_REALTIME_CS(v)) + +#define BIT_SHIFT_STC_INT_EXPECT_CS 0 +#define BIT_MASK_STC_INT_EXPECT_CS 0x3f +#define BIT_STC_INT_EXPECT_CS(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS) +#define BITS_STC_INT_EXPECT_CS \ + (BIT_MASK_STC_INT_EXPECT_CS << BIT_SHIFT_STC_INT_EXPECT_CS) +#define BIT_CLEAR_STC_INT_EXPECT_CS(x) ((x) & (~BITS_STC_INT_EXPECT_CS)) +#define BIT_GET_STC_INT_EXPECT_CS(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS) +#define BIT_SET_STC_INT_EXPECT_CS(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS(x) | BIT_STC_INT_EXPECT_CS(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH4_ACH5_TXBD_NUM (Offset 0x130C) */ + +#define BIT_PCIE_ACH5_FLAG BIT(30) + +#define BIT_SHIFT_ACH5_DESC_MODE 28 +#define BIT_MASK_ACH5_DESC_MODE 0x3 +#define BIT_ACH5_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH5_DESC_MODE) << BIT_SHIFT_ACH5_DESC_MODE) +#define BITS_ACH5_DESC_MODE \ + (BIT_MASK_ACH5_DESC_MODE << BIT_SHIFT_ACH5_DESC_MODE) +#define BIT_CLEAR_ACH5_DESC_MODE(x) ((x) & (~BITS_ACH5_DESC_MODE)) +#define BIT_GET_ACH5_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH5_DESC_MODE) & BIT_MASK_ACH5_DESC_MODE) +#define BIT_SET_ACH5_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH5_DESC_MODE(x) | BIT_ACH5_DESC_MODE(v)) + +#define BIT_SHIFT_ACH5_DESC_NUM 16 +#define BIT_MASK_ACH5_DESC_NUM 0xfff +#define BIT_ACH5_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH5_DESC_NUM) << BIT_SHIFT_ACH5_DESC_NUM) +#define BITS_ACH5_DESC_NUM (BIT_MASK_ACH5_DESC_NUM << BIT_SHIFT_ACH5_DESC_NUM) +#define BIT_CLEAR_ACH5_DESC_NUM(x) ((x) & (~BITS_ACH5_DESC_NUM)) +#define BIT_GET_ACH5_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH5_DESC_NUM) & BIT_MASK_ACH5_DESC_NUM) +#define BIT_SET_ACH5_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH5_DESC_NUM(x) | BIT_ACH5_DESC_NUM(v)) + +#define BIT_PCIE_ACH4_FLAG BIT(14) + +#define BIT_SHIFT_ACH4_DESC_MODE 12 +#define BIT_MASK_ACH4_DESC_MODE 0x3 +#define BIT_ACH4_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH4_DESC_MODE) << BIT_SHIFT_ACH4_DESC_MODE) +#define BITS_ACH4_DESC_MODE \ + (BIT_MASK_ACH4_DESC_MODE << BIT_SHIFT_ACH4_DESC_MODE) +#define BIT_CLEAR_ACH4_DESC_MODE(x) ((x) & (~BITS_ACH4_DESC_MODE)) +#define BIT_GET_ACH4_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH4_DESC_MODE) & BIT_MASK_ACH4_DESC_MODE) +#define BIT_SET_ACH4_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH4_DESC_MODE(x) | BIT_ACH4_DESC_MODE(v)) + +#define BIT_SHIFT_ACH4_DESC_NUM 0 +#define BIT_MASK_ACH4_DESC_NUM 0xfff +#define BIT_ACH4_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH4_DESC_NUM) << BIT_SHIFT_ACH4_DESC_NUM) +#define BITS_ACH4_DESC_NUM (BIT_MASK_ACH4_DESC_NUM << BIT_SHIFT_ACH4_DESC_NUM) +#define BIT_CLEAR_ACH4_DESC_NUM(x) ((x) & (~BITS_ACH4_DESC_NUM)) +#define BIT_GET_ACH4_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH4_DESC_NUM) & BIT_MASK_ACH4_DESC_NUM) +#define BIT_SET_ACH4_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH4_DESC_NUM(x) | BIT_ACH4_DESC_NUM(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +/* 2 REG_CMU_DLY_CTRL (Offset 0x1310) */ + +#define BIT_CMU_DLY_EN BIT(31) +#define BIT_CMU_DLY_MODE BIT(30) + +#define BIT_SHIFT_CMU_DLY_PRE_DIV 0 +#define BIT_MASK_CMU_DLY_PRE_DIV 0xff +#define BIT_CMU_DLY_PRE_DIV(x) \ + (((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV) +#define BITS_CMU_DLY_PRE_DIV \ + (BIT_MASK_CMU_DLY_PRE_DIV << BIT_SHIFT_CMU_DLY_PRE_DIV) +#define BIT_CLEAR_CMU_DLY_PRE_DIV(x) ((x) & (~BITS_CMU_DLY_PRE_DIV)) +#define BIT_GET_CMU_DLY_PRE_DIV(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV) +#define BIT_SET_CMU_DLY_PRE_DIV(x, v) \ + (BIT_CLEAR_CMU_DLY_PRE_DIV(x) | BIT_CMU_DLY_PRE_DIV(v)) + +/* 2 REG_CMU_DLY_CFG (Offset 0x1314) */ + +#define BIT_SHIFT_CMU_DLY_LTR_A2I 24 +#define BIT_MASK_CMU_DLY_LTR_A2I 0xff +#define BIT_CMU_DLY_LTR_A2I(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I) +#define BITS_CMU_DLY_LTR_A2I \ + (BIT_MASK_CMU_DLY_LTR_A2I << BIT_SHIFT_CMU_DLY_LTR_A2I) +#define BIT_CLEAR_CMU_DLY_LTR_A2I(x) ((x) & (~BITS_CMU_DLY_LTR_A2I)) +#define BIT_GET_CMU_DLY_LTR_A2I(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I) +#define BIT_SET_CMU_DLY_LTR_A2I(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_A2I(x) | BIT_CMU_DLY_LTR_A2I(v)) + +#define BIT_SHIFT_CMU_DLY_LTR_I2A 16 +#define BIT_MASK_CMU_DLY_LTR_I2A 0xff +#define BIT_CMU_DLY_LTR_I2A(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A) +#define BITS_CMU_DLY_LTR_I2A \ + (BIT_MASK_CMU_DLY_LTR_I2A << BIT_SHIFT_CMU_DLY_LTR_I2A) +#define BIT_CLEAR_CMU_DLY_LTR_I2A(x) ((x) & (~BITS_CMU_DLY_LTR_I2A)) +#define BIT_GET_CMU_DLY_LTR_I2A(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A) +#define BIT_SET_CMU_DLY_LTR_I2A(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_I2A(x) | BIT_CMU_DLY_LTR_I2A(v)) + +#define BIT_SHIFT_CMU_DLY_LTR_IDLE 8 +#define BIT_MASK_CMU_DLY_LTR_IDLE 0xff +#define BIT_CMU_DLY_LTR_IDLE(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE) +#define BITS_CMU_DLY_LTR_IDLE \ + (BIT_MASK_CMU_DLY_LTR_IDLE << BIT_SHIFT_CMU_DLY_LTR_IDLE) +#define BIT_CLEAR_CMU_DLY_LTR_IDLE(x) ((x) & (~BITS_CMU_DLY_LTR_IDLE)) +#define BIT_GET_CMU_DLY_LTR_IDLE(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE) +#define BIT_SET_CMU_DLY_LTR_IDLE(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_IDLE(x) | BIT_CMU_DLY_LTR_IDLE(v)) + +#define BIT_SHIFT_CMU_DLY_LTR_ACT 0 +#define BIT_MASK_CMU_DLY_LTR_ACT 0xff +#define BIT_CMU_DLY_LTR_ACT(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT) +#define BITS_CMU_DLY_LTR_ACT \ + (BIT_MASK_CMU_DLY_LTR_ACT << BIT_SHIFT_CMU_DLY_LTR_ACT) +#define BIT_CLEAR_CMU_DLY_LTR_ACT(x) ((x) & (~BITS_CMU_DLY_LTR_ACT)) +#define BIT_GET_CMU_DLY_LTR_ACT(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT) +#define BIT_SET_CMU_DLY_LTR_ACT(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_ACT(x) | BIT_CMU_DLY_LTR_ACT(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_FWCMDQ_TXBD_IDX (Offset 0x1318) */ + +#define BIT_SHIFT_FWCMDQ_HW_IDX 16 +#define BIT_MASK_FWCMDQ_HW_IDX 0xfff +#define BIT_FWCMDQ_HW_IDX(x) \ + (((x) & BIT_MASK_FWCMDQ_HW_IDX) << BIT_SHIFT_FWCMDQ_HW_IDX) +#define BITS_FWCMDQ_HW_IDX (BIT_MASK_FWCMDQ_HW_IDX << BIT_SHIFT_FWCMDQ_HW_IDX) +#define BIT_CLEAR_FWCMDQ_HW_IDX(x) ((x) & (~BITS_FWCMDQ_HW_IDX)) +#define BIT_GET_FWCMDQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HW_IDX) & BIT_MASK_FWCMDQ_HW_IDX) +#define BIT_SET_FWCMDQ_HW_IDX(x, v) \ + (BIT_CLEAR_FWCMDQ_HW_IDX(x) | BIT_FWCMDQ_HW_IDX(v)) + +#define BIT_SHIFT_FWCMDQ_HOST_IDX 0 +#define BIT_MASK_FWCMDQ_HOST_IDX 0xfff +#define BIT_FWCMDQ_HOST_IDX(x) \ + (((x) & BIT_MASK_FWCMDQ_HOST_IDX) << BIT_SHIFT_FWCMDQ_HOST_IDX) +#define BITS_FWCMDQ_HOST_IDX \ + (BIT_MASK_FWCMDQ_HOST_IDX << BIT_SHIFT_FWCMDQ_HOST_IDX) +#define BIT_CLEAR_FWCMDQ_HOST_IDX(x) ((x) & (~BITS_FWCMDQ_HOST_IDX)) +#define BIT_GET_FWCMDQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HOST_IDX) & BIT_MASK_FWCMDQ_HOST_IDX) +#define BIT_SET_FWCMDQ_HOST_IDX(x, v) \ + (BIT_CLEAR_FWCMDQ_HOST_IDX(x) | BIT_FWCMDQ_HOST_IDX(v)) + +/* 2 REG_P0HI8Q_TXBD_IDX (Offset 0x131C) */ + +#define BIT_SHIFT_P0HI8Q_HW_IDX 16 +#define BIT_MASK_P0HI8Q_HW_IDX 0xfff +#define BIT_P0HI8Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI8Q_HW_IDX) << BIT_SHIFT_P0HI8Q_HW_IDX) +#define BITS_P0HI8Q_HW_IDX (BIT_MASK_P0HI8Q_HW_IDX << BIT_SHIFT_P0HI8Q_HW_IDX) +#define BIT_CLEAR_P0HI8Q_HW_IDX(x) ((x) & (~BITS_P0HI8Q_HW_IDX)) +#define BIT_GET_P0HI8Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_HW_IDX) & BIT_MASK_P0HI8Q_HW_IDX) +#define BIT_SET_P0HI8Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI8Q_HW_IDX(x) | BIT_P0HI8Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI8Q_HOST_IDX 0 +#define BIT_MASK_P0HI8Q_HOST_IDX 0xfff +#define BIT_P0HI8Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI8Q_HOST_IDX) << BIT_SHIFT_P0HI8Q_HOST_IDX) +#define BITS_P0HI8Q_HOST_IDX \ + (BIT_MASK_P0HI8Q_HOST_IDX << BIT_SHIFT_P0HI8Q_HOST_IDX) +#define BIT_CLEAR_P0HI8Q_HOST_IDX(x) ((x) & (~BITS_P0HI8Q_HOST_IDX)) +#define BIT_GET_P0HI8Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_HOST_IDX) & BIT_MASK_P0HI8Q_HOST_IDX) +#define BIT_SET_P0HI8Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI8Q_HOST_IDX(x) | BIT_P0HI8Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_H2CQ_TXBD_DESA (Offset 0x1320) */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA 0 +#define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL +#define BIT_H2CQ_TXBD_DESA(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA) +#define BITS_H2CQ_TXBD_DESA \ + (BIT_MASK_H2CQ_TXBD_DESA << BIT_SHIFT_H2CQ_TXBD_DESA) +#define BIT_CLEAR_H2CQ_TXBD_DESA(x) ((x) & (~BITS_H2CQ_TXBD_DESA)) +#define BIT_GET_H2CQ_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA) +#define BIT_SET_H2CQ_TXBD_DESA(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA(x) | BIT_H2CQ_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_H2CQ_TXBD_DESA_L (Offset 0x1320) */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA_L 0 +#define BIT_MASK_H2CQ_TXBD_DESA_L 0xffffffffL +#define BIT_H2CQ_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_L) << BIT_SHIFT_H2CQ_TXBD_DESA_L) +#define BITS_H2CQ_TXBD_DESA_L \ + (BIT_MASK_H2CQ_TXBD_DESA_L << BIT_SHIFT_H2CQ_TXBD_DESA_L) +#define BIT_CLEAR_H2CQ_TXBD_DESA_L(x) ((x) & (~BITS_H2CQ_TXBD_DESA_L)) +#define BIT_GET_H2CQ_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_L) & BIT_MASK_H2CQ_TXBD_DESA_L) +#define BIT_SET_H2CQ_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_L(x) | BIT_H2CQ_TXBD_DESA_L(v)) + +/* 2 REG_H2CQ_TXBD_DESA_H (Offset 0x1324) */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA_H 0 +#define BIT_MASK_H2CQ_TXBD_DESA_H 0xffffffffL +#define BIT_H2CQ_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_H) << BIT_SHIFT_H2CQ_TXBD_DESA_H) +#define BITS_H2CQ_TXBD_DESA_H \ + (BIT_MASK_H2CQ_TXBD_DESA_H << BIT_SHIFT_H2CQ_TXBD_DESA_H) +#define BIT_CLEAR_H2CQ_TXBD_DESA_H(x) ((x) & (~BITS_H2CQ_TXBD_DESA_H)) +#define BIT_GET_H2CQ_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_H) & BIT_MASK_H2CQ_TXBD_DESA_H) +#define BIT_SET_H2CQ_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_H(x) | BIT_H2CQ_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ + +#define BIT_PCIE_H2CQ_FLAG BIT(14) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ + +#define BIT_HCI_H2CQ_FLAG BIT(14) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ + +#define BIT_SHIFT_H2CQ_DESC_MODE 12 +#define BIT_MASK_H2CQ_DESC_MODE 0x3 +#define BIT_H2CQ_DESC_MODE(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE) +#define BITS_H2CQ_DESC_MODE \ + (BIT_MASK_H2CQ_DESC_MODE << BIT_SHIFT_H2CQ_DESC_MODE) +#define BIT_CLEAR_H2CQ_DESC_MODE(x) ((x) & (~BITS_H2CQ_DESC_MODE)) +#define BIT_GET_H2CQ_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE) +#define BIT_SET_H2CQ_DESC_MODE(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE(x) | BIT_H2CQ_DESC_MODE(v)) + +#define BIT_SHIFT_H2CQ_DESC_NUM 0 +#define BIT_MASK_H2CQ_DESC_NUM 0xfff +#define BIT_H2CQ_DESC_NUM(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM) +#define BITS_H2CQ_DESC_NUM (BIT_MASK_H2CQ_DESC_NUM << BIT_SHIFT_H2CQ_DESC_NUM) +#define BIT_CLEAR_H2CQ_DESC_NUM(x) ((x) & (~BITS_H2CQ_DESC_NUM)) +#define BIT_GET_H2CQ_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM) +#define BIT_SET_H2CQ_DESC_NUM(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM(x) | BIT_H2CQ_DESC_NUM(v)) + +/* 2 REG_H2CQ_TXBD_IDX (Offset 0x132C) */ + +#define BIT_SHIFT_H2CQ_HW_IDX 16 +#define BIT_MASK_H2CQ_HW_IDX 0xfff +#define BIT_H2CQ_HW_IDX(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX) +#define BITS_H2CQ_HW_IDX (BIT_MASK_H2CQ_HW_IDX << BIT_SHIFT_H2CQ_HW_IDX) +#define BIT_CLEAR_H2CQ_HW_IDX(x) ((x) & (~BITS_H2CQ_HW_IDX)) +#define BIT_GET_H2CQ_HW_IDX(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX) +#define BIT_SET_H2CQ_HW_IDX(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX(x) | BIT_H2CQ_HW_IDX(v)) + +#define BIT_SHIFT_H2CQ_HOST_IDX 0 +#define BIT_MASK_H2CQ_HOST_IDX 0xfff +#define BIT_H2CQ_HOST_IDX(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX) +#define BITS_H2CQ_HOST_IDX (BIT_MASK_H2CQ_HOST_IDX << BIT_SHIFT_H2CQ_HOST_IDX) +#define BIT_CLEAR_H2CQ_HOST_IDX(x) ((x) & (~BITS_H2CQ_HOST_IDX)) +#define BIT_GET_H2CQ_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX) +#define BIT_SET_H2CQ_HOST_IDX(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX(x) | BIT_H2CQ_HOST_IDX(v)) + +/* 2 REG_H2CQ_CSR (Offset 0x1330) */ + +#define BIT_H2CQ_FULL BIT(31) +#define BIT_CLR_H2CQ_HOST_IDX BIT(16) +#define BIT_CLR_H2CQ_HW_IDX BIT(8) +#define BIT_STOP_H2CQ BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI9Q_TXBD_IDX (Offset 0x1334) */ + +#define BIT_SHIFT_P0HI9Q_HW_IDX 16 +#define BIT_MASK_P0HI9Q_HW_IDX 0xfff +#define BIT_P0HI9Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI9Q_HW_IDX) << BIT_SHIFT_P0HI9Q_HW_IDX) +#define BITS_P0HI9Q_HW_IDX (BIT_MASK_P0HI9Q_HW_IDX << BIT_SHIFT_P0HI9Q_HW_IDX) +#define BIT_CLEAR_P0HI9Q_HW_IDX(x) ((x) & (~BITS_P0HI9Q_HW_IDX)) +#define BIT_GET_P0HI9Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_HW_IDX) & BIT_MASK_P0HI9Q_HW_IDX) +#define BIT_SET_P0HI9Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI9Q_HW_IDX(x) | BIT_P0HI9Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI9Q_HOST_IDX 0 +#define BIT_MASK_P0HI9Q_HOST_IDX 0xfff +#define BIT_P0HI9Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI9Q_HOST_IDX) << BIT_SHIFT_P0HI9Q_HOST_IDX) +#define BITS_P0HI9Q_HOST_IDX \ + (BIT_MASK_P0HI9Q_HOST_IDX << BIT_SHIFT_P0HI9Q_HOST_IDX) +#define BIT_CLEAR_P0HI9Q_HOST_IDX(x) ((x) & (~BITS_P0HI9Q_HOST_IDX)) +#define BIT_GET_P0HI9Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_HOST_IDX) & BIT_MASK_P0HI9Q_HOST_IDX) +#define BIT_SET_P0HI9Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI9Q_HOST_IDX(x) | BIT_P0HI9Q_HOST_IDX(v)) + +/* 2 REG_P0HI10Q_TXBD_IDX (Offset 0x1338) */ + +#define BIT_SHIFT_P0HI10Q_HW_IDX 16 +#define BIT_MASK_P0HI10Q_HW_IDX 0xfff +#define BIT_P0HI10Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI10Q_HW_IDX) << BIT_SHIFT_P0HI10Q_HW_IDX) +#define BITS_P0HI10Q_HW_IDX \ + (BIT_MASK_P0HI10Q_HW_IDX << BIT_SHIFT_P0HI10Q_HW_IDX) +#define BIT_CLEAR_P0HI10Q_HW_IDX(x) ((x) & (~BITS_P0HI10Q_HW_IDX)) +#define BIT_GET_P0HI10Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_HW_IDX) & BIT_MASK_P0HI10Q_HW_IDX) +#define BIT_SET_P0HI10Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI10Q_HW_IDX(x) | BIT_P0HI10Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI10Q_HOST_IDX 0 +#define BIT_MASK_P0HI10Q_HOST_IDX 0xfff +#define BIT_P0HI10Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI10Q_HOST_IDX) << BIT_SHIFT_P0HI10Q_HOST_IDX) +#define BITS_P0HI10Q_HOST_IDX \ + (BIT_MASK_P0HI10Q_HOST_IDX << BIT_SHIFT_P0HI10Q_HOST_IDX) +#define BIT_CLEAR_P0HI10Q_HOST_IDX(x) ((x) & (~BITS_P0HI10Q_HOST_IDX)) +#define BIT_GET_P0HI10Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_HOST_IDX) & BIT_MASK_P0HI10Q_HOST_IDX) +#define BIT_SET_P0HI10Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI10Q_HOST_IDX(x) | BIT_P0HI10Q_HOST_IDX(v)) + +/* 2 REG_P0HI11Q_TXBD_IDX (Offset 0x133C) */ + +#define BIT_SHIFT_P0HI11Q_HW_IDX 16 +#define BIT_MASK_P0HI11Q_HW_IDX 0xfff +#define BIT_P0HI11Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI11Q_HW_IDX) << BIT_SHIFT_P0HI11Q_HW_IDX) +#define BITS_P0HI11Q_HW_IDX \ + (BIT_MASK_P0HI11Q_HW_IDX << BIT_SHIFT_P0HI11Q_HW_IDX) +#define BIT_CLEAR_P0HI11Q_HW_IDX(x) ((x) & (~BITS_P0HI11Q_HW_IDX)) +#define BIT_GET_P0HI11Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_HW_IDX) & BIT_MASK_P0HI11Q_HW_IDX) +#define BIT_SET_P0HI11Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI11Q_HW_IDX(x) | BIT_P0HI11Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI11Q_HOST_IDX 0 +#define BIT_MASK_P0HI11Q_HOST_IDX 0xfff +#define BIT_P0HI11Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI11Q_HOST_IDX) << BIT_SHIFT_P0HI11Q_HOST_IDX) +#define BITS_P0HI11Q_HOST_IDX \ + (BIT_MASK_P0HI11Q_HOST_IDX << BIT_SHIFT_P0HI11Q_HOST_IDX) +#define BIT_CLEAR_P0HI11Q_HOST_IDX(x) ((x) & (~BITS_P0HI11Q_HOST_IDX)) +#define BIT_GET_P0HI11Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_HOST_IDX) & BIT_MASK_P0HI11Q_HOST_IDX) +#define BIT_SET_P0HI11Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI11Q_HOST_IDX(x) | BIT_P0HI11Q_HOST_IDX(v)) + +/* 2 REG_P0HI12Q_TXBD_IDX (Offset 0x1340) */ + +#define BIT_SHIFT_P0HI12Q_HW_IDX 16 +#define BIT_MASK_P0HI12Q_HW_IDX 0xfff +#define BIT_P0HI12Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI12Q_HW_IDX) << BIT_SHIFT_P0HI12Q_HW_IDX) +#define BITS_P0HI12Q_HW_IDX \ + (BIT_MASK_P0HI12Q_HW_IDX << BIT_SHIFT_P0HI12Q_HW_IDX) +#define BIT_CLEAR_P0HI12Q_HW_IDX(x) ((x) & (~BITS_P0HI12Q_HW_IDX)) +#define BIT_GET_P0HI12Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_HW_IDX) & BIT_MASK_P0HI12Q_HW_IDX) +#define BIT_SET_P0HI12Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI12Q_HW_IDX(x) | BIT_P0HI12Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI12Q_HOST_IDX 0 +#define BIT_MASK_P0HI12Q_HOST_IDX 0xfff +#define BIT_P0HI12Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI12Q_HOST_IDX) << BIT_SHIFT_P0HI12Q_HOST_IDX) +#define BITS_P0HI12Q_HOST_IDX \ + (BIT_MASK_P0HI12Q_HOST_IDX << BIT_SHIFT_P0HI12Q_HOST_IDX) +#define BIT_CLEAR_P0HI12Q_HOST_IDX(x) ((x) & (~BITS_P0HI12Q_HOST_IDX)) +#define BIT_GET_P0HI12Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_HOST_IDX) & BIT_MASK_P0HI12Q_HOST_IDX) +#define BIT_SET_P0HI12Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI12Q_HOST_IDX(x) | BIT_P0HI12Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_CPL_BUFFER_MONITOR (Offset 0x1344) */ + +#define BIT_TXQFULL_FLAG BIT(19) + +#define BIT_SHIFT_RELAX_ORDERING_ATTR 17 +#define BIT_MASK_RELAX_ORDERING_ATTR 0x3 +#define BIT_RELAX_ORDERING_ATTR(x) \ + (((x) & BIT_MASK_RELAX_ORDERING_ATTR) << BIT_SHIFT_RELAX_ORDERING_ATTR) +#define BITS_RELAX_ORDERING_ATTR \ + (BIT_MASK_RELAX_ORDERING_ATTR << BIT_SHIFT_RELAX_ORDERING_ATTR) +#define BIT_CLEAR_RELAX_ORDERING_ATTR(x) ((x) & (~BITS_RELAX_ORDERING_ATTR)) +#define BIT_GET_RELAX_ORDERING_ATTR(x) \ + (((x) >> BIT_SHIFT_RELAX_ORDERING_ATTR) & BIT_MASK_RELAX_ORDERING_ATTR) +#define BIT_SET_RELAX_ORDERING_ATTR(x, v) \ + (BIT_CLEAR_RELAX_ORDERING_ATTR(x) | BIT_RELAX_ORDERING_ATTR(v)) + +#define BIT_CLR_QD_CPL_MIN_REMAIN BIT(16) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI13Q_TXBD_IDX (Offset 0x1344) */ + +#define BIT_SHIFT_P0HI13Q_HW_IDX 16 +#define BIT_MASK_P0HI13Q_HW_IDX 0xfff +#define BIT_P0HI13Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI13Q_HW_IDX) << BIT_SHIFT_P0HI13Q_HW_IDX) +#define BITS_P0HI13Q_HW_IDX \ + (BIT_MASK_P0HI13Q_HW_IDX << BIT_SHIFT_P0HI13Q_HW_IDX) +#define BIT_CLEAR_P0HI13Q_HW_IDX(x) ((x) & (~BITS_P0HI13Q_HW_IDX)) +#define BIT_GET_P0HI13Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_HW_IDX) & BIT_MASK_P0HI13Q_HW_IDX) +#define BIT_SET_P0HI13Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI13Q_HW_IDX(x) | BIT_P0HI13Q_HW_IDX(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_CPL_BUFFER_MONITOR (Offset 0x1344) */ + +#define BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR 8 +#define BIT_MASK_QD_CPL_MIN_REMAIN_ADDR 0xff +#define BIT_QD_CPL_MIN_REMAIN_ADDR(x) \ + (((x) & BIT_MASK_QD_CPL_MIN_REMAIN_ADDR) \ + << BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR) +#define BITS_QD_CPL_MIN_REMAIN_ADDR \ + (BIT_MASK_QD_CPL_MIN_REMAIN_ADDR << BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR) +#define BIT_CLEAR_QD_CPL_MIN_REMAIN_ADDR(x) \ + ((x) & (~BITS_QD_CPL_MIN_REMAIN_ADDR)) +#define BIT_GET_QD_CPL_MIN_REMAIN_ADDR(x) \ + (((x) >> BIT_SHIFT_QD_CPL_MIN_REMAIN_ADDR) & \ + BIT_MASK_QD_CPL_MIN_REMAIN_ADDR) +#define BIT_SET_QD_CPL_MIN_REMAIN_ADDR(x, v) \ + (BIT_CLEAR_QD_CPL_MIN_REMAIN_ADDR(x) | BIT_QD_CPL_MIN_REMAIN_ADDR(v)) + +#define BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR 0 +#define BIT_MASK_QD_CPL_CUR_REMAIN_ADDR 0xff +#define BIT_QD_CPL_CUR_REMAIN_ADDR(x) \ + (((x) & BIT_MASK_QD_CPL_CUR_REMAIN_ADDR) \ + << BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR) +#define BITS_QD_CPL_CUR_REMAIN_ADDR \ + (BIT_MASK_QD_CPL_CUR_REMAIN_ADDR << BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR) +#define BIT_CLEAR_QD_CPL_CUR_REMAIN_ADDR(x) \ + ((x) & (~BITS_QD_CPL_CUR_REMAIN_ADDR)) +#define BIT_GET_QD_CPL_CUR_REMAIN_ADDR(x) \ + (((x) >> BIT_SHIFT_QD_CPL_CUR_REMAIN_ADDR) & \ + BIT_MASK_QD_CPL_CUR_REMAIN_ADDR) +#define BIT_SET_QD_CPL_CUR_REMAIN_ADDR(x, v) \ + (BIT_CLEAR_QD_CPL_CUR_REMAIN_ADDR(x) | BIT_QD_CPL_CUR_REMAIN_ADDR(v)) + +#define BIT_SHIFT_PTM_LOCAL_CLOCK 0 +#define BIT_MASK_PTM_LOCAL_CLOCK 0xffffffffL +#define BIT_PTM_LOCAL_CLOCK(x) \ + (((x) & BIT_MASK_PTM_LOCAL_CLOCK) << BIT_SHIFT_PTM_LOCAL_CLOCK) +#define BITS_PTM_LOCAL_CLOCK \ + (BIT_MASK_PTM_LOCAL_CLOCK << BIT_SHIFT_PTM_LOCAL_CLOCK) +#define BIT_CLEAR_PTM_LOCAL_CLOCK(x) ((x) & (~BITS_PTM_LOCAL_CLOCK)) +#define BIT_GET_PTM_LOCAL_CLOCK(x) \ + (((x) >> BIT_SHIFT_PTM_LOCAL_CLOCK) & BIT_MASK_PTM_LOCAL_CLOCK) +#define BIT_SET_PTM_LOCAL_CLOCK(x, v) \ + (BIT_CLEAR_PTM_LOCAL_CLOCK(x) | BIT_PTM_LOCAL_CLOCK(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI13Q_TXBD_IDX (Offset 0x1344) */ + +#define BIT_SHIFT_P0HI13Q_HOST_IDX 0 +#define BIT_MASK_P0HI13Q_HOST_IDX 0xfff +#define BIT_P0HI13Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI13Q_HOST_IDX) << BIT_SHIFT_P0HI13Q_HOST_IDX) +#define BITS_P0HI13Q_HOST_IDX \ + (BIT_MASK_P0HI13Q_HOST_IDX << BIT_SHIFT_P0HI13Q_HOST_IDX) +#define BIT_CLEAR_P0HI13Q_HOST_IDX(x) ((x) & (~BITS_P0HI13Q_HOST_IDX)) +#define BIT_GET_P0HI13Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_HOST_IDX) & BIT_MASK_P0HI13Q_HOST_IDX) +#define BIT_SET_P0HI13Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI13Q_HOST_IDX(x) | BIT_P0HI13Q_HOST_IDX(v)) + +/* 2 REG_P0HI14Q_TXBD_IDX (Offset 0x1348) */ + +#define BIT_SHIFT_P0HI14Q_HW_IDX 16 +#define BIT_MASK_P0HI14Q_HW_IDX 0xfff +#define BIT_P0HI14Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI14Q_HW_IDX) << BIT_SHIFT_P0HI14Q_HW_IDX) +#define BITS_P0HI14Q_HW_IDX \ + (BIT_MASK_P0HI14Q_HW_IDX << BIT_SHIFT_P0HI14Q_HW_IDX) +#define BIT_CLEAR_P0HI14Q_HW_IDX(x) ((x) & (~BITS_P0HI14Q_HW_IDX)) +#define BIT_GET_P0HI14Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_HW_IDX) & BIT_MASK_P0HI14Q_HW_IDX) +#define BIT_SET_P0HI14Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI14Q_HW_IDX(x) | BIT_P0HI14Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI14Q_HOST_IDX 0 +#define BIT_MASK_P0HI14Q_HOST_IDX 0xfff +#define BIT_P0HI14Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI14Q_HOST_IDX) << BIT_SHIFT_P0HI14Q_HOST_IDX) +#define BITS_P0HI14Q_HOST_IDX \ + (BIT_MASK_P0HI14Q_HOST_IDX << BIT_SHIFT_P0HI14Q_HOST_IDX) +#define BIT_CLEAR_P0HI14Q_HOST_IDX(x) ((x) & (~BITS_P0HI14Q_HOST_IDX)) +#define BIT_GET_P0HI14Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_HOST_IDX) & BIT_MASK_P0HI14Q_HOST_IDX) +#define BIT_SET_P0HI14Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI14Q_HOST_IDX(x) | BIT_P0HI14Q_HOST_IDX(v)) + +/* 2 REG_P0HI15Q_TXBD_IDX (Offset 0x134C) */ + +#define BIT_SHIFT_P0HI15Q_HW_IDX 16 +#define BIT_MASK_P0HI15Q_HW_IDX 0xfff +#define BIT_P0HI15Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI15Q_HW_IDX) << BIT_SHIFT_P0HI15Q_HW_IDX) +#define BITS_P0HI15Q_HW_IDX \ + (BIT_MASK_P0HI15Q_HW_IDX << BIT_SHIFT_P0HI15Q_HW_IDX) +#define BIT_CLEAR_P0HI15Q_HW_IDX(x) ((x) & (~BITS_P0HI15Q_HW_IDX)) +#define BIT_GET_P0HI15Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_HW_IDX) & BIT_MASK_P0HI15Q_HW_IDX) +#define BIT_SET_P0HI15Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI15Q_HW_IDX(x) | BIT_P0HI15Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI15Q_HOST_IDX 0 +#define BIT_MASK_P0HI15Q_HOST_IDX 0xfff +#define BIT_P0HI15Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI15Q_HOST_IDX) << BIT_SHIFT_P0HI15Q_HOST_IDX) +#define BITS_P0HI15Q_HOST_IDX \ + (BIT_MASK_P0HI15Q_HOST_IDX << BIT_SHIFT_P0HI15Q_HOST_IDX) +#define BIT_CLEAR_P0HI15Q_HOST_IDX(x) ((x) & (~BITS_P0HI15Q_HOST_IDX)) +#define BIT_GET_P0HI15Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_HOST_IDX) & BIT_MASK_P0HI15Q_HOST_IDX) +#define BIT_SET_P0HI15Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI15Q_HOST_IDX(x) | BIT_P0HI15Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ + +#define BIT_AXI_RXDMA_TIMEOUT_RE BIT(21) +#define BIT_AXI_TXDMA_TIMEOUT_RE BIT(20) +#define BIT_AXI_DECERR_W_RE BIT(19) +#define BIT_AXI_DECERR_R_RE BIT(18) + +#endif + +#if (HALMAC_8822B_SUPPORT) + +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ + +#define BIT_CHANGE_PCIE_SPEED BIT(18) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ + +#define BIT_AXI_SLVERR_W_RE BIT(17) +#define BIT_AXI_SLVERR_R_RE BIT(16) + +#endif + +#if (HALMAC_8822B_SUPPORT) + +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ + +#define BIT_SHIFT_GEN1_GEN2 16 +#define BIT_MASK_GEN1_GEN2 0x3 +#define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2) +#define BITS_GEN1_GEN2 (BIT_MASK_GEN1_GEN2 << BIT_SHIFT_GEN1_GEN2) +#define BIT_CLEAR_GEN1_GEN2(x) ((x) & (~BITS_GEN1_GEN2)) +#define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2) +#define BIT_SET_GEN1_GEN2(x, v) (BIT_CLEAR_GEN1_GEN2(x) | BIT_GEN1_GEN2(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ + +#define BIT_AXI_RXDMA_TIMEOUT_IE BIT(13) +#define BIT_AXI_TXDMA_TIMEOUT_IE BIT(12) +#define BIT_AXI_DECERR_W_IE BIT(11) +#define BIT_AXI_DECERR_R_IE BIT(10) +#define BIT_AXI_SLVERR_W_IE BIT(9) +#define BIT_AXI_SLVERR_R_IE BIT(8) + +#endif + +#if (HALMAC_8822B_SUPPORT) + +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ + +#define BIT_SHIFT_RXDMA_ERROR_COUNTER 8 +#define BIT_MASK_RXDMA_ERROR_COUNTER 0xff +#define BIT_RXDMA_ERROR_COUNTER(x) \ + (((x) & BIT_MASK_RXDMA_ERROR_COUNTER) << BIT_SHIFT_RXDMA_ERROR_COUNTER) +#define BITS_RXDMA_ERROR_COUNTER \ + (BIT_MASK_RXDMA_ERROR_COUNTER << BIT_SHIFT_RXDMA_ERROR_COUNTER) +#define BIT_CLEAR_RXDMA_ERROR_COUNTER(x) ((x) & (~BITS_RXDMA_ERROR_COUNTER)) +#define BIT_GET_RXDMA_ERROR_COUNTER(x) \ + (((x) >> BIT_SHIFT_RXDMA_ERROR_COUNTER) & BIT_MASK_RXDMA_ERROR_COUNTER) +#define BIT_SET_RXDMA_ERROR_COUNTER(x, v) \ + (BIT_CLEAR_RXDMA_ERROR_COUNTER(x) | BIT_RXDMA_ERROR_COUNTER(v)) + +#define BIT_TXDMA_ERROR_HANDLE_STATUS BIT(7) +#define BIT_TXDMA_ERROR_PULSE BIT(6) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ + +#define BIT_AXI_RXDMA_TIMEOUT_FLAG BIT(5) + +#endif + +#if (HALMAC_8822B_SUPPORT) + +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ + +#define BIT_TXDMA_STUCK_ERROR_HANDLE_ENABLE BIT(5) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ + +#define BIT_AXI_TXDMA_TIMEOUT_FLAG BIT(4) + +#endif + +#if (HALMAC_8822B_SUPPORT) + +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ + +#define BIT_TXDMA_RETURN_ERROR_ENABLE BIT(4) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ + +#define BIT_AXI_DECERR_W_FLAG BIT(3) + +#endif + +#if (HALMAC_8822B_SUPPORT) + +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ + +#define BIT_RXDMA_ERROR_HANDLE_STATUS BIT(3) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ + +#define BIT_AXI_DECERR_R_FLAG BIT(2) +#define BIT_AXI_SLVERR_W_FLAG BIT(1) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_TSFT_PTM_DIFF (Offset 0x1350) */ + +#define BIT_SHIFT_TSFT_PTM_DIFF 0 +#define BIT_MASK_TSFT_PTM_DIFF 0xffffffffL +#define BIT_TSFT_PTM_DIFF(x) \ + (((x) & BIT_MASK_TSFT_PTM_DIFF) << BIT_SHIFT_TSFT_PTM_DIFF) +#define BITS_TSFT_PTM_DIFF (BIT_MASK_TSFT_PTM_DIFF << BIT_SHIFT_TSFT_PTM_DIFF) +#define BIT_CLEAR_TSFT_PTM_DIFF(x) ((x) & (~BITS_TSFT_PTM_DIFF)) +#define BIT_GET_TSFT_PTM_DIFF(x) \ + (((x) >> BIT_SHIFT_TSFT_PTM_DIFF) & BIT_MASK_TSFT_PTM_DIFF) +#define BIT_SET_TSFT_PTM_DIFF(x, v) \ + (BIT_CLEAR_TSFT_PTM_DIFF(x) | BIT_TSFT_PTM_DIFF(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ + +#define BIT_AXI_SLVERR_R_FLAG BIT(0) + +#endif + +#if (HALMAC_8822B_SUPPORT) + +/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ + +#define BIT_SHIFT_AUTO_HANG_RELEASE 0 +#define BIT_MASK_AUTO_HANG_RELEASE 0x7 +#define BIT_AUTO_HANG_RELEASE(x) \ + (((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE) +#define BITS_AUTO_HANG_RELEASE \ + (BIT_MASK_AUTO_HANG_RELEASE << BIT_SHIFT_AUTO_HANG_RELEASE) +#define BIT_CLEAR_AUTO_HANG_RELEASE(x) ((x) & (~BITS_AUTO_HANG_RELEASE)) +#define BIT_GET_AUTO_HANG_RELEASE(x) \ + (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE) +#define BIT_SET_AUTO_HANG_RELEASE(x, v) \ + (BIT_CLEAR_AUTO_HANG_RELEASE(x) | BIT_AUTO_HANG_RELEASE(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_AXI_EXCEPT_TIME (Offset 0x1354) */ + +#define BIT_SHIFT_AXI_RECOVERY_TIME 24 +#define BIT_MASK_AXI_RECOVERY_TIME 0xff +#define BIT_AXI_RECOVERY_TIME(x) \ + (((x) & BIT_MASK_AXI_RECOVERY_TIME) << BIT_SHIFT_AXI_RECOVERY_TIME) +#define BITS_AXI_RECOVERY_TIME \ + (BIT_MASK_AXI_RECOVERY_TIME << BIT_SHIFT_AXI_RECOVERY_TIME) +#define BIT_CLEAR_AXI_RECOVERY_TIME(x) ((x) & (~BITS_AXI_RECOVERY_TIME)) +#define BIT_GET_AXI_RECOVERY_TIME(x) \ + (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME) & BIT_MASK_AXI_RECOVERY_TIME) +#define BIT_SET_AXI_RECOVERY_TIME(x, v) \ + (BIT_CLEAR_AXI_RECOVERY_TIME(x) | BIT_AXI_RECOVERY_TIME(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_PTM_CTRL_STATUS (Offset 0x1354) */ + +#define BIT_BCNQ2_EMPTY BIT(23) +#define BIT_BCNQ1_EMPTY BIT(22) +#define BIT_BCNQ0_EMPTY BIT(21) +#define BIT_EVTQ_EMPTY BIT(20) +#define BIT_MGQ_CPU_EMPTY_V2 BIT(19) +#define BIT_BCNQ_EMPTY_V2 BIT(18) +#define BIT_HQQ_EMPTY_V2 BIT(17) + +#define BIT_SHIFT_TAIL_PKT_V1 16 +#define BIT_MASK_TAIL_PKT_V1 0xff +#define BIT_TAIL_PKT_V1(x) \ + (((x) & BIT_MASK_TAIL_PKT_V1) << BIT_SHIFT_TAIL_PKT_V1) +#define BITS_TAIL_PKT_V1 (BIT_MASK_TAIL_PKT_V1 << BIT_SHIFT_TAIL_PKT_V1) +#define BIT_CLEAR_TAIL_PKT_V1(x) ((x) & (~BITS_TAIL_PKT_V1)) +#define BIT_GET_TAIL_PKT_V1(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_V1) & BIT_MASK_TAIL_PKT_V1) +#define BIT_SET_TAIL_PKT_V1(x, v) \ + (BIT_CLEAR_TAIL_PKT_V1(x) | BIT_TAIL_PKT_V1(v)) + +#define BIT_MQQ_EMPTY_V3 BIT(16) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_AXI_EXCEPT_TIME (Offset 0x1354) */ + +#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL 12 +#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL 0xfff +#define BIT_AXI_RXDMA_TIMEOUT_VAL(x) \ + (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) \ + << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) +#define BITS_AXI_RXDMA_TIMEOUT_VAL \ + (BIT_MASK_AXI_RXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) +#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL)) +#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL(x) \ + (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) & \ + BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) +#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL(x, v) \ + (BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) | BIT_AXI_RXDMA_TIMEOUT_VAL(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_PTM_CTRL_STATUS (Offset 0x1354) */ + +#define BIT_SHIFT_PKT_NUM_V1 8 +#define BIT_MASK_PKT_NUM_V1 0xff +#define BIT_PKT_NUM_V1(x) (((x) & BIT_MASK_PKT_NUM_V1) << BIT_SHIFT_PKT_NUM_V1) +#define BITS_PKT_NUM_V1 (BIT_MASK_PKT_NUM_V1 << BIT_SHIFT_PKT_NUM_V1) +#define BIT_CLEAR_PKT_NUM_V1(x) ((x) & (~BITS_PKT_NUM_V1)) +#define BIT_GET_PKT_NUM_V1(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_V1) & BIT_MASK_PKT_NUM_V1) +#define BIT_SET_PKT_NUM_V1(x, v) (BIT_CLEAR_PKT_NUM_V1(x) | BIT_PKT_NUM_V1(v)) + +#define BIT_SHIFT_QUEUEAC_V1 8 +#define BIT_MASK_QUEUEAC_V1 0x3 +#define BIT_QUEUEAC_V1(x) (((x) & BIT_MASK_QUEUEAC_V1) << BIT_SHIFT_QUEUEAC_V1) +#define BITS_QUEUEAC_V1 (BIT_MASK_QUEUEAC_V1 << BIT_SHIFT_QUEUEAC_V1) +#define BIT_CLEAR_QUEUEAC_V1(x) ((x) & (~BITS_QUEUEAC_V1)) +#define BIT_GET_QUEUEAC_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_V1) & BIT_MASK_QUEUEAC_V1) +#define BIT_SET_QUEUEAC_V1(x, v) (BIT_CLEAR_QUEUEAC_V1(x) | BIT_QUEUEAC_V1(v)) + +#define BIT_SHIFT_ACQ_STOP 5 +#define BIT_MASK_ACQ_STOP 0xffff +#define BIT_ACQ_STOP(x) (((x) & BIT_MASK_ACQ_STOP) << BIT_SHIFT_ACQ_STOP) +#define BITS_ACQ_STOP (BIT_MASK_ACQ_STOP << BIT_SHIFT_ACQ_STOP) +#define BIT_CLEAR_ACQ_STOP(x) ((x) & (~BITS_ACQ_STOP)) +#define BIT_GET_ACQ_STOP(x) (((x) >> BIT_SHIFT_ACQ_STOP) & BIT_MASK_ACQ_STOP) +#define BIT_SET_ACQ_STOP(x, v) (BIT_CLEAR_ACQ_STOP(x) | BIT_ACQ_STOP(v)) + +#define BIT_SHIFT_TSFT_PORT_SEL 3 +#define BIT_MASK_TSFT_PORT_SEL 0x3 +#define BIT_TSFT_PORT_SEL(x) \ + (((x) & BIT_MASK_TSFT_PORT_SEL) << BIT_SHIFT_TSFT_PORT_SEL) +#define BITS_TSFT_PORT_SEL (BIT_MASK_TSFT_PORT_SEL << BIT_SHIFT_TSFT_PORT_SEL) +#define BIT_CLEAR_TSFT_PORT_SEL(x) ((x) & (~BITS_TSFT_PORT_SEL)) +#define BIT_GET_TSFT_PORT_SEL(x) \ + (((x) >> BIT_SHIFT_TSFT_PORT_SEL) & BIT_MASK_TSFT_PORT_SEL) +#define BIT_SET_TSFT_PORT_SEL(x, v) \ + (BIT_CLEAR_TSFT_PORT_SEL(x) | BIT_TSFT_PORT_SEL(v)) + +#define BIT_PTM_CONTEXT_VALID BIT(2) +#define BIT_PTM_MANUL_UPDATE BIT(1) +#define BIT_PTM_AUTO_UPDATE BIT(0) + +#define BIT_SHIFT_HEAD_PKT_V1 0 +#define BIT_MASK_HEAD_PKT_V1 0xff +#define BIT_HEAD_PKT_V1(x) \ + (((x) & BIT_MASK_HEAD_PKT_V1) << BIT_SHIFT_HEAD_PKT_V1) +#define BITS_HEAD_PKT_V1 (BIT_MASK_HEAD_PKT_V1 << BIT_SHIFT_HEAD_PKT_V1) +#define BIT_CLEAR_HEAD_PKT_V1(x) ((x) & (~BITS_HEAD_PKT_V1)) +#define BIT_GET_HEAD_PKT_V1(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_V1) & BIT_MASK_HEAD_PKT_V1) +#define BIT_SET_HEAD_PKT_V1(x, v) \ + (BIT_CLEAR_HEAD_PKT_V1(x) | BIT_HEAD_PKT_V1(v)) + +#define BIT_SHIFT_QUEUEMACID_V1 0 +#define BIT_MASK_QUEUEMACID_V1 0x7f +#define BIT_QUEUEMACID_V1(x) \ + (((x) & BIT_MASK_QUEUEMACID_V1) << BIT_SHIFT_QUEUEMACID_V1) +#define BITS_QUEUEMACID_V1 (BIT_MASK_QUEUEMACID_V1 << BIT_SHIFT_QUEUEMACID_V1) +#define BIT_CLEAR_QUEUEMACID_V1(x) ((x) & (~BITS_QUEUEMACID_V1)) +#define BIT_GET_QUEUEMACID_V1(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_V1) & BIT_MASK_QUEUEMACID_V1) +#define BIT_SET_QUEUEMACID_V1(x, v) \ + (BIT_CLEAR_QUEUEMACID_V1(x) | BIT_QUEUEMACID_V1(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +/* 2 REG_AXI_EXCEPT_TIME (Offset 0x1354) */ + +#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL 0 +#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL 0xfff +#define BIT_AXI_TXDMA_TIMEOUT_VAL(x) \ + (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) \ + << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) +#define BITS_AXI_TXDMA_TIMEOUT_VAL \ + (BIT_MASK_AXI_TXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) +#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL)) +#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL(x) \ + (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) & \ + BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) +#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL(x, v) \ + (BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) | BIT_AXI_TXDMA_TIMEOUT_VAL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DEBUG_STATE1 (Offset 0x1354) */ + +#define BIT_SHIFT_DEBUG_STATE1 0 +#define BIT_MASK_DEBUG_STATE1 0xffffffffL +#define BIT_DEBUG_STATE1(x) \ + (((x) & BIT_MASK_DEBUG_STATE1) << BIT_SHIFT_DEBUG_STATE1) +#define BITS_DEBUG_STATE1 (BIT_MASK_DEBUG_STATE1 << BIT_SHIFT_DEBUG_STATE1) +#define BIT_CLEAR_DEBUG_STATE1(x) ((x) & (~BITS_DEBUG_STATE1)) +#define BIT_GET_DEBUG_STATE1(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE1) & BIT_MASK_DEBUG_STATE1) +#define BIT_SET_DEBUG_STATE1(x, v) \ + (BIT_CLEAR_DEBUG_STATE1(x) | BIT_DEBUG_STATE1(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI8Q_TXBD_IDX (Offset 0x1358) */ + +#define BIT_SHIFT_HI8Q_HW_IDX 16 +#define BIT_MASK_HI8Q_HW_IDX 0xfff +#define BIT_HI8Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI8Q_HW_IDX) << BIT_SHIFT_HI8Q_HW_IDX) +#define BITS_HI8Q_HW_IDX (BIT_MASK_HI8Q_HW_IDX << BIT_SHIFT_HI8Q_HW_IDX) +#define BIT_CLEAR_HI8Q_HW_IDX(x) ((x) & (~BITS_HI8Q_HW_IDX)) +#define BIT_GET_HI8Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI8Q_HW_IDX) & BIT_MASK_HI8Q_HW_IDX) +#define BIT_SET_HI8Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI8Q_HW_IDX(x) | BIT_HI8Q_HW_IDX(v)) + +#define BIT_SHIFT_HI8Q_HOST_IDX 0 +#define BIT_MASK_HI8Q_HOST_IDX 0xfff +#define BIT_HI8Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI8Q_HOST_IDX) << BIT_SHIFT_HI8Q_HOST_IDX) +#define BITS_HI8Q_HOST_IDX (BIT_MASK_HI8Q_HOST_IDX << BIT_SHIFT_HI8Q_HOST_IDX) +#define BIT_CLEAR_HI8Q_HOST_IDX(x) ((x) & (~BITS_HI8Q_HOST_IDX)) +#define BIT_GET_HI8Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI8Q_HOST_IDX) & BIT_MASK_HI8Q_HOST_IDX) +#define BIT_SET_HI8Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI8Q_HOST_IDX(x) | BIT_HI8Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DEBUG_STATE2 (Offset 0x1358) */ + +#define BIT_SHIFT_DEBUG_STATE2 0 +#define BIT_MASK_DEBUG_STATE2 0xffffffffL +#define BIT_DEBUG_STATE2(x) \ + (((x) & BIT_MASK_DEBUG_STATE2) << BIT_SHIFT_DEBUG_STATE2) +#define BITS_DEBUG_STATE2 (BIT_MASK_DEBUG_STATE2 << BIT_SHIFT_DEBUG_STATE2) +#define BIT_CLEAR_DEBUG_STATE2(x) ((x) & (~BITS_DEBUG_STATE2)) +#define BIT_GET_DEBUG_STATE2(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE2) & BIT_MASK_DEBUG_STATE2) +#define BIT_SET_DEBUG_STATE2(x, v) \ + (BIT_CLEAR_DEBUG_STATE2(x) | BIT_DEBUG_STATE2(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI9Q_TXBD_IDX (Offset 0x135C) */ + +#define BIT_SHIFT_HI9Q_HW_IDX 16 +#define BIT_MASK_HI9Q_HW_IDX 0xfff +#define BIT_HI9Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI9Q_HW_IDX) << BIT_SHIFT_HI9Q_HW_IDX) +#define BITS_HI9Q_HW_IDX (BIT_MASK_HI9Q_HW_IDX << BIT_SHIFT_HI9Q_HW_IDX) +#define BIT_CLEAR_HI9Q_HW_IDX(x) ((x) & (~BITS_HI9Q_HW_IDX)) +#define BIT_GET_HI9Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI9Q_HW_IDX) & BIT_MASK_HI9Q_HW_IDX) +#define BIT_SET_HI9Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI9Q_HW_IDX(x) | BIT_HI9Q_HW_IDX(v)) + +#define BIT_SHIFT_HI9Q_HOST_IDX 0 +#define BIT_MASK_HI9Q_HOST_IDX 0xfff +#define BIT_HI9Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI9Q_HOST_IDX) << BIT_SHIFT_HI9Q_HOST_IDX) +#define BITS_HI9Q_HOST_IDX (BIT_MASK_HI9Q_HOST_IDX << BIT_SHIFT_HI9Q_HOST_IDX) +#define BIT_CLEAR_HI9Q_HOST_IDX(x) ((x) & (~BITS_HI9Q_HOST_IDX)) +#define BIT_GET_HI9Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI9Q_HOST_IDX) & BIT_MASK_HI9Q_HOST_IDX) +#define BIT_SET_HI9Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI9Q_HOST_IDX(x) | BIT_HI9Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_DEBUG_STATE3 (Offset 0x135C) */ + +#define BIT_SHIFT_DEBUG_STATE3 0 +#define BIT_MASK_DEBUG_STATE3 0xffffffffL +#define BIT_DEBUG_STATE3(x) \ + (((x) & BIT_MASK_DEBUG_STATE3) << BIT_SHIFT_DEBUG_STATE3) +#define BITS_DEBUG_STATE3 (BIT_MASK_DEBUG_STATE3 << BIT_SHIFT_DEBUG_STATE3) +#define BIT_CLEAR_DEBUG_STATE3(x) ((x) & (~BITS_DEBUG_STATE3)) +#define BIT_GET_DEBUG_STATE3(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE3) & BIT_MASK_DEBUG_STATE3) +#define BIT_SET_DEBUG_STATE3(x, v) \ + (BIT_CLEAR_DEBUG_STATE3(x) | BIT_DEBUG_STATE3(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI10Q_TXBD_IDX (Offset 0x1360) */ + +#define BIT_SHIFT_HI10Q_HW_IDX 16 +#define BIT_MASK_HI10Q_HW_IDX 0xfff +#define BIT_HI10Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI10Q_HW_IDX) << BIT_SHIFT_HI10Q_HW_IDX) +#define BITS_HI10Q_HW_IDX (BIT_MASK_HI10Q_HW_IDX << BIT_SHIFT_HI10Q_HW_IDX) +#define BIT_CLEAR_HI10Q_HW_IDX(x) ((x) & (~BITS_HI10Q_HW_IDX)) +#define BIT_GET_HI10Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI10Q_HW_IDX) & BIT_MASK_HI10Q_HW_IDX) +#define BIT_SET_HI10Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI10Q_HW_IDX(x) | BIT_HI10Q_HW_IDX(v)) + +#define BIT_SHIFT_HI10Q_HOST_IDX 0 +#define BIT_MASK_HI10Q_HOST_IDX 0xfff +#define BIT_HI10Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI10Q_HOST_IDX) << BIT_SHIFT_HI10Q_HOST_IDX) +#define BITS_HI10Q_HOST_IDX \ + (BIT_MASK_HI10Q_HOST_IDX << BIT_SHIFT_HI10Q_HOST_IDX) +#define BIT_CLEAR_HI10Q_HOST_IDX(x) ((x) & (~BITS_HI10Q_HOST_IDX)) +#define BIT_GET_HI10Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI10Q_HOST_IDX) & BIT_MASK_HI10Q_HOST_IDX) +#define BIT_SET_HI10Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI10Q_HOST_IDX(x) | BIT_HI10Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH5_TXBD_DESA_L (Offset 0x1360) */ + +#define BIT_SHIFT_ACH5_TXBD_DESA_L 0 +#define BIT_MASK_ACH5_TXBD_DESA_L 0xffffffffL +#define BIT_ACH5_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH5_TXBD_DESA_L) << BIT_SHIFT_ACH5_TXBD_DESA_L) +#define BITS_ACH5_TXBD_DESA_L \ + (BIT_MASK_ACH5_TXBD_DESA_L << BIT_SHIFT_ACH5_TXBD_DESA_L) +#define BIT_CLEAR_ACH5_TXBD_DESA_L(x) ((x) & (~BITS_ACH5_TXBD_DESA_L)) +#define BIT_GET_ACH5_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_L) & BIT_MASK_ACH5_TXBD_DESA_L) +#define BIT_SET_ACH5_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH5_TXBD_DESA_L(x) | BIT_ACH5_TXBD_DESA_L(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI11Q_TXBD_IDX (Offset 0x1364) */ + +#define BIT_SHIFT_HI11Q_HW_IDX 16 +#define BIT_MASK_HI11Q_HW_IDX 0xfff +#define BIT_HI11Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI11Q_HW_IDX) << BIT_SHIFT_HI11Q_HW_IDX) +#define BITS_HI11Q_HW_IDX (BIT_MASK_HI11Q_HW_IDX << BIT_SHIFT_HI11Q_HW_IDX) +#define BIT_CLEAR_HI11Q_HW_IDX(x) ((x) & (~BITS_HI11Q_HW_IDX)) +#define BIT_GET_HI11Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI11Q_HW_IDX) & BIT_MASK_HI11Q_HW_IDX) +#define BIT_SET_HI11Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI11Q_HW_IDX(x) | BIT_HI11Q_HW_IDX(v)) + +#define BIT_SHIFT_HI11Q_HOST_IDX 0 +#define BIT_MASK_HI11Q_HOST_IDX 0xfff +#define BIT_HI11Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI11Q_HOST_IDX) << BIT_SHIFT_HI11Q_HOST_IDX) +#define BITS_HI11Q_HOST_IDX \ + (BIT_MASK_HI11Q_HOST_IDX << BIT_SHIFT_HI11Q_HOST_IDX) +#define BIT_CLEAR_HI11Q_HOST_IDX(x) ((x) & (~BITS_HI11Q_HOST_IDX)) +#define BIT_GET_HI11Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI11Q_HOST_IDX) & BIT_MASK_HI11Q_HOST_IDX) +#define BIT_SET_HI11Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI11Q_HOST_IDX(x) | BIT_HI11Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH5_TXBD_DESA_H (Offset 0x1364) */ + +#define BIT_SHIFT_ACH5_TXBD_DESA_H 0 +#define BIT_MASK_ACH5_TXBD_DESA_H 0xffffffffL +#define BIT_ACH5_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH5_TXBD_DESA_H) << BIT_SHIFT_ACH5_TXBD_DESA_H) +#define BITS_ACH5_TXBD_DESA_H \ + (BIT_MASK_ACH5_TXBD_DESA_H << BIT_SHIFT_ACH5_TXBD_DESA_H) +#define BIT_CLEAR_ACH5_TXBD_DESA_H(x) ((x) & (~BITS_ACH5_TXBD_DESA_H)) +#define BIT_GET_ACH5_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_H) & BIT_MASK_ACH5_TXBD_DESA_H) +#define BIT_SET_ACH5_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH5_TXBD_DESA_H(x) | BIT_ACH5_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI12Q_TXBD_IDX (Offset 0x1368) */ + +#define BIT_SHIFT_HI12Q_HW_IDX 16 +#define BIT_MASK_HI12Q_HW_IDX 0xfff +#define BIT_HI12Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI12Q_HW_IDX) << BIT_SHIFT_HI12Q_HW_IDX) +#define BITS_HI12Q_HW_IDX (BIT_MASK_HI12Q_HW_IDX << BIT_SHIFT_HI12Q_HW_IDX) +#define BIT_CLEAR_HI12Q_HW_IDX(x) ((x) & (~BITS_HI12Q_HW_IDX)) +#define BIT_GET_HI12Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI12Q_HW_IDX) & BIT_MASK_HI12Q_HW_IDX) +#define BIT_SET_HI12Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI12Q_HW_IDX(x) | BIT_HI12Q_HW_IDX(v)) + +#define BIT_SHIFT_HI12Q_HOST_IDX 0 +#define BIT_MASK_HI12Q_HOST_IDX 0xfff +#define BIT_HI12Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI12Q_HOST_IDX) << BIT_SHIFT_HI12Q_HOST_IDX) +#define BITS_HI12Q_HOST_IDX \ + (BIT_MASK_HI12Q_HOST_IDX << BIT_SHIFT_HI12Q_HOST_IDX) +#define BIT_CLEAR_HI12Q_HOST_IDX(x) ((x) & (~BITS_HI12Q_HOST_IDX)) +#define BIT_GET_HI12Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI12Q_HOST_IDX) & BIT_MASK_HI12Q_HOST_IDX) +#define BIT_SET_HI12Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI12Q_HOST_IDX(x) | BIT_HI12Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH6_TXBD_DESA_L (Offset 0x1368) */ + +#define BIT_SHIFT_ACH6_TXBD_DESA_L 0 +#define BIT_MASK_ACH6_TXBD_DESA_L 0xffffffffL +#define BIT_ACH6_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH6_TXBD_DESA_L) << BIT_SHIFT_ACH6_TXBD_DESA_L) +#define BITS_ACH6_TXBD_DESA_L \ + (BIT_MASK_ACH6_TXBD_DESA_L << BIT_SHIFT_ACH6_TXBD_DESA_L) +#define BIT_CLEAR_ACH6_TXBD_DESA_L(x) ((x) & (~BITS_ACH6_TXBD_DESA_L)) +#define BIT_GET_ACH6_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_L) & BIT_MASK_ACH6_TXBD_DESA_L) +#define BIT_SET_ACH6_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH6_TXBD_DESA_L(x) | BIT_ACH6_TXBD_DESA_L(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI13Q_TXBD_IDX (Offset 0x136C) */ + +#define BIT_SHIFT_HI13Q_HW_IDX 16 +#define BIT_MASK_HI13Q_HW_IDX 0xfff +#define BIT_HI13Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI13Q_HW_IDX) << BIT_SHIFT_HI13Q_HW_IDX) +#define BITS_HI13Q_HW_IDX (BIT_MASK_HI13Q_HW_IDX << BIT_SHIFT_HI13Q_HW_IDX) +#define BIT_CLEAR_HI13Q_HW_IDX(x) ((x) & (~BITS_HI13Q_HW_IDX)) +#define BIT_GET_HI13Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI13Q_HW_IDX) & BIT_MASK_HI13Q_HW_IDX) +#define BIT_SET_HI13Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI13Q_HW_IDX(x) | BIT_HI13Q_HW_IDX(v)) + +#define BIT_SHIFT_HI13Q_HOST_IDX 0 +#define BIT_MASK_HI13Q_HOST_IDX 0xfff +#define BIT_HI13Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI13Q_HOST_IDX) << BIT_SHIFT_HI13Q_HOST_IDX) +#define BITS_HI13Q_HOST_IDX \ + (BIT_MASK_HI13Q_HOST_IDX << BIT_SHIFT_HI13Q_HOST_IDX) +#define BIT_CLEAR_HI13Q_HOST_IDX(x) ((x) & (~BITS_HI13Q_HOST_IDX)) +#define BIT_GET_HI13Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI13Q_HOST_IDX) & BIT_MASK_HI13Q_HOST_IDX) +#define BIT_SET_HI13Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI13Q_HOST_IDX(x) | BIT_HI13Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH6_TXBD_DESA_H (Offset 0x136C) */ + +#define BIT_SHIFT_ACH6_TXBD_DESA_H 0 +#define BIT_MASK_ACH6_TXBD_DESA_H 0xffffffffL +#define BIT_ACH6_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH6_TXBD_DESA_H) << BIT_SHIFT_ACH6_TXBD_DESA_H) +#define BITS_ACH6_TXBD_DESA_H \ + (BIT_MASK_ACH6_TXBD_DESA_H << BIT_SHIFT_ACH6_TXBD_DESA_H) +#define BIT_CLEAR_ACH6_TXBD_DESA_H(x) ((x) & (~BITS_ACH6_TXBD_DESA_H)) +#define BIT_GET_ACH6_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_H) & BIT_MASK_ACH6_TXBD_DESA_H) +#define BIT_SET_ACH6_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH6_TXBD_DESA_H(x) | BIT_ACH6_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI14Q_TXBD_IDX (Offset 0x1370) */ + +#define BIT_SHIFT_HI14Q_HW_IDX 16 +#define BIT_MASK_HI14Q_HW_IDX 0xfff +#define BIT_HI14Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI14Q_HW_IDX) << BIT_SHIFT_HI14Q_HW_IDX) +#define BITS_HI14Q_HW_IDX (BIT_MASK_HI14Q_HW_IDX << BIT_SHIFT_HI14Q_HW_IDX) +#define BIT_CLEAR_HI14Q_HW_IDX(x) ((x) & (~BITS_HI14Q_HW_IDX)) +#define BIT_GET_HI14Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI14Q_HW_IDX) & BIT_MASK_HI14Q_HW_IDX) +#define BIT_SET_HI14Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI14Q_HW_IDX(x) | BIT_HI14Q_HW_IDX(v)) + +#define BIT_SHIFT_HI14Q_HOST_IDX 0 +#define BIT_MASK_HI14Q_HOST_IDX 0xfff +#define BIT_HI14Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI14Q_HOST_IDX) << BIT_SHIFT_HI14Q_HOST_IDX) +#define BITS_HI14Q_HOST_IDX \ + (BIT_MASK_HI14Q_HOST_IDX << BIT_SHIFT_HI14Q_HOST_IDX) +#define BIT_CLEAR_HI14Q_HOST_IDX(x) ((x) & (~BITS_HI14Q_HOST_IDX)) +#define BIT_GET_HI14Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI14Q_HOST_IDX) & BIT_MASK_HI14Q_HOST_IDX) +#define BIT_SET_HI14Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI14Q_HOST_IDX(x) | BIT_HI14Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH7_TXBD_DESA_L (Offset 0x1370) */ + +#define BIT_SHIFT_ACH7_TXBD_DESA_L 0 +#define BIT_MASK_ACH7_TXBD_DESA_L 0xffffffffL +#define BIT_ACH7_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH7_TXBD_DESA_L) << BIT_SHIFT_ACH7_TXBD_DESA_L) +#define BITS_ACH7_TXBD_DESA_L \ + (BIT_MASK_ACH7_TXBD_DESA_L << BIT_SHIFT_ACH7_TXBD_DESA_L) +#define BIT_CLEAR_ACH7_TXBD_DESA_L(x) ((x) & (~BITS_ACH7_TXBD_DESA_L)) +#define BIT_GET_ACH7_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_L) & BIT_MASK_ACH7_TXBD_DESA_L) +#define BIT_SET_ACH7_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH7_TXBD_DESA_L(x) | BIT_ACH7_TXBD_DESA_L(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI15Q_TXBD_IDX (Offset 0x1374) */ + +#define BIT_SHIFT_HI15Q_HW_IDX 16 +#define BIT_MASK_HI15Q_HW_IDX 0xfff +#define BIT_HI15Q_HW_IDX(x) \ + (((x) & BIT_MASK_HI15Q_HW_IDX) << BIT_SHIFT_HI15Q_HW_IDX) +#define BITS_HI15Q_HW_IDX (BIT_MASK_HI15Q_HW_IDX << BIT_SHIFT_HI15Q_HW_IDX) +#define BIT_CLEAR_HI15Q_HW_IDX(x) ((x) & (~BITS_HI15Q_HW_IDX)) +#define BIT_GET_HI15Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_HI15Q_HW_IDX) & BIT_MASK_HI15Q_HW_IDX) +#define BIT_SET_HI15Q_HW_IDX(x, v) \ + (BIT_CLEAR_HI15Q_HW_IDX(x) | BIT_HI15Q_HW_IDX(v)) + +#define BIT_SHIFT_HI15Q_HOST_IDX 0 +#define BIT_MASK_HI15Q_HOST_IDX 0xfff +#define BIT_HI15Q_HOST_IDX(x) \ + (((x) & BIT_MASK_HI15Q_HOST_IDX) << BIT_SHIFT_HI15Q_HOST_IDX) +#define BITS_HI15Q_HOST_IDX \ + (BIT_MASK_HI15Q_HOST_IDX << BIT_SHIFT_HI15Q_HOST_IDX) +#define BIT_CLEAR_HI15Q_HOST_IDX(x) ((x) & (~BITS_HI15Q_HOST_IDX)) +#define BIT_GET_HI15Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_HI15Q_HOST_IDX) & BIT_MASK_HI15Q_HOST_IDX) +#define BIT_SET_HI15Q_HOST_IDX(x, v) \ + (BIT_CLEAR_HI15Q_HOST_IDX(x) | BIT_HI15Q_HOST_IDX(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH7_TXBD_DESA_H (Offset 0x1374) */ -#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT BIT(18) +#define BIT_SHIFT_ACH7_TXBD_DESA_H 0 +#define BIT_MASK_ACH7_TXBD_DESA_H 0xffffffffL +#define BIT_ACH7_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH7_TXBD_DESA_H) << BIT_SHIFT_ACH7_TXBD_DESA_H) +#define BITS_ACH7_TXBD_DESA_H \ + (BIT_MASK_ACH7_TXBD_DESA_H << BIT_SHIFT_ACH7_TXBD_DESA_H) +#define BIT_CLEAR_ACH7_TXBD_DESA_H(x) ((x) & (~BITS_ACH7_TXBD_DESA_H)) +#define BIT_GET_ACH7_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_H) & BIT_MASK_ACH7_TXBD_DESA_H) +#define BIT_SET_ACH7_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH7_TXBD_DESA_H(x) | BIT_ACH7_TXBD_DESA_H(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HI8Q_TXBD_DESA (Offset 0x1378) */ +#define BIT_SHIFT_HI8Q_TXBD_DESA 0 +#define BIT_MASK_HI8Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI8Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI8Q_TXBD_DESA) << BIT_SHIFT_HI8Q_TXBD_DESA) +#define BITS_HI8Q_TXBD_DESA \ + (BIT_MASK_HI8Q_TXBD_DESA << BIT_SHIFT_HI8Q_TXBD_DESA) +#define BIT_CLEAR_HI8Q_TXBD_DESA(x) ((x) & (~BITS_HI8Q_TXBD_DESA)) +#define BIT_GET_HI8Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA) & BIT_MASK_HI8Q_TXBD_DESA) +#define BIT_SET_HI8Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI8Q_TXBD_DESA(x) | BIT_HI8Q_TXBD_DESA(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ACH8_TXBD_DESA_L (Offset 0x1378) */ +#define BIT_SHIFT_ACH8_TXBD_DESA_L 0 +#define BIT_MASK_ACH8_TXBD_DESA_L 0xffffffffL +#define BIT_ACH8_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH8_TXBD_DESA_L) << BIT_SHIFT_ACH8_TXBD_DESA_L) +#define BITS_ACH8_TXBD_DESA_L \ + (BIT_MASK_ACH8_TXBD_DESA_L << BIT_SHIFT_ACH8_TXBD_DESA_L) +#define BIT_CLEAR_ACH8_TXBD_DESA_L(x) ((x) & (~BITS_ACH8_TXBD_DESA_L)) +#define BIT_GET_ACH8_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_L) & BIT_MASK_ACH8_TXBD_DESA_L) +#define BIT_SET_ACH8_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH8_TXBD_DESA_L(x) | BIT_ACH8_TXBD_DESA_L(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_CHNL_DMA_CFG_V1 (Offset 0x137C) */ -#define BIT_PORT1_TRIPKT_OK_INT BIT(17) +#define BIT_TXHCI_EN_V1 BIT(26) +#define BIT_TXHCI_IDLE_V1 BIT(25) +#define BIT_DMA_PRI_EN_V1 BIT(24) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ACH8_TXBD_DESA_H (Offset 0x137C) */ +#define BIT_SHIFT_ACH8_TXBD_DESA_H 0 +#define BIT_MASK_ACH8_TXBD_DESA_H 0xffffffffL +#define BIT_ACH8_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH8_TXBD_DESA_H) << BIT_SHIFT_ACH8_TXBD_DESA_H) +#define BITS_ACH8_TXBD_DESA_H \ + (BIT_MASK_ACH8_TXBD_DESA_H << BIT_SHIFT_ACH8_TXBD_DESA_H) +#define BIT_CLEAR_ACH8_TXBD_DESA_H(x) ((x) & (~BITS_ACH8_TXBD_DESA_H)) +#define BIT_GET_ACH8_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_H) & BIT_MASK_ACH8_TXBD_DESA_H) +#define BIT_SET_ACH8_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH8_TXBD_DESA_H(x) | BIT_ACH8_TXBD_DESA_H(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI9Q_TXBD_DESA (Offset 0x1380) */ -#define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17) +#define BIT_SHIFT_HI9Q_TXBD_DESA 0 +#define BIT_MASK_HI9Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI9Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI9Q_TXBD_DESA) << BIT_SHIFT_HI9Q_TXBD_DESA) +#define BITS_HI9Q_TXBD_DESA \ + (BIT_MASK_HI9Q_TXBD_DESA << BIT_SHIFT_HI9Q_TXBD_DESA) +#define BIT_CLEAR_HI9Q_TXBD_DESA(x) ((x) & (~BITS_HI9Q_TXBD_DESA)) +#define BIT_GET_HI9Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA) & BIT_MASK_HI9Q_TXBD_DESA) +#define BIT_SET_HI9Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI9Q_TXBD_DESA(x) | BIT_HI9Q_TXBD_DESA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ACH9_TXBD_DESA_L (Offset 0x1380) */ +#define BIT_SHIFT_ACH9_TXBD_DESA_L 0 +#define BIT_MASK_ACH9_TXBD_DESA_L 0xffffffffL +#define BIT_ACH9_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH9_TXBD_DESA_L) << BIT_SHIFT_ACH9_TXBD_DESA_L) +#define BITS_ACH9_TXBD_DESA_L \ + (BIT_MASK_ACH9_TXBD_DESA_L << BIT_SHIFT_ACH9_TXBD_DESA_L) +#define BIT_CLEAR_ACH9_TXBD_DESA_L(x) ((x) & (~BITS_ACH9_TXBD_DESA_L)) +#define BIT_GET_ACH9_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_L) & BIT_MASK_ACH9_TXBD_DESA_L) +#define BIT_SET_ACH9_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH9_TXBD_DESA_L(x) | BIT_ACH9_TXBD_DESA_L(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_ACH9_TXBD_DESA_H (Offset 0x1384) */ -#define BIT_PORT1_RX_EOSP_OK_INT BIT(16) +#define BIT_SHIFT_ACH9_TXBD_DESA_H 0 +#define BIT_MASK_ACH9_TXBD_DESA_H 0xffffffffL +#define BIT_ACH9_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH9_TXBD_DESA_H) << BIT_SHIFT_ACH9_TXBD_DESA_H) +#define BITS_ACH9_TXBD_DESA_H \ + (BIT_MASK_ACH9_TXBD_DESA_H << BIT_SHIFT_ACH9_TXBD_DESA_H) +#define BIT_CLEAR_ACH9_TXBD_DESA_H(x) ((x) & (~BITS_ACH9_TXBD_DESA_H)) +#define BIT_GET_ACH9_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_H) & BIT_MASK_ACH9_TXBD_DESA_H) +#define BIT_SET_ACH9_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH9_TXBD_DESA_H(x) | BIT_ACH9_TXBD_DESA_H(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HI10Q_TXBD_DESA (Offset 0x1388) */ +#define BIT_SHIFT_HI10Q_TXBD_DESA 0 +#define BIT_MASK_HI10Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI10Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI10Q_TXBD_DESA) << BIT_SHIFT_HI10Q_TXBD_DESA) +#define BITS_HI10Q_TXBD_DESA \ + (BIT_MASK_HI10Q_TXBD_DESA << BIT_SHIFT_HI10Q_TXBD_DESA) +#define BIT_CLEAR_HI10Q_TXBD_DESA(x) ((x) & (~BITS_HI10Q_TXBD_DESA)) +#define BIT_GET_HI10Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA) & BIT_MASK_HI10Q_TXBD_DESA) +#define BIT_SET_HI10Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI10Q_TXBD_DESA(x) | BIT_HI10Q_TXBD_DESA(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI0_EOSP_INT BIT(16) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_ACH10_TXBD_DESA_L (Offset 0x1388) */ +#define BIT_SHIFT_ACH10_TXBD_DESA_L 0 +#define BIT_MASK_ACH10_TXBD_DESA_L 0xffffffffL +#define BIT_ACH10_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH10_TXBD_DESA_L) << BIT_SHIFT_ACH10_TXBD_DESA_L) +#define BITS_ACH10_TXBD_DESA_L \ + (BIT_MASK_ACH10_TXBD_DESA_L << BIT_SHIFT_ACH10_TXBD_DESA_L) +#define BIT_CLEAR_ACH10_TXBD_DESA_L(x) ((x) & (~BITS_ACH10_TXBD_DESA_L)) +#define BIT_GET_ACH10_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_L) & BIT_MASK_ACH10_TXBD_DESA_L) +#define BIT_SET_ACH10_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH10_TXBD_DESA_L(x) | BIT_ACH10_TXBD_DESA_L(v)) + +/* 2 REG_ACH10_TXBD_DESA_H (Offset 0x138C) */ + +#define BIT_SHIFT_ACH10_TXBD_DESA_H 0 +#define BIT_MASK_ACH10_TXBD_DESA_H 0xffffffffL +#define BIT_ACH10_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH10_TXBD_DESA_H) << BIT_SHIFT_ACH10_TXBD_DESA_H) +#define BITS_ACH10_TXBD_DESA_H \ + (BIT_MASK_ACH10_TXBD_DESA_H << BIT_SHIFT_ACH10_TXBD_DESA_H) +#define BIT_CLEAR_ACH10_TXBD_DESA_H(x) ((x) & (~BITS_ACH10_TXBD_DESA_H)) +#define BIT_GET_ACH10_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_H) & BIT_MASK_ACH10_TXBD_DESA_H) +#define BIT_SET_ACH10_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH10_TXBD_DESA_H(x) | BIT_ACH10_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI11Q_TXBD_DESA (Offset 0x1390) */ + +#define BIT_SHIFT_HI11Q_TXBD_DESA 0 +#define BIT_MASK_HI11Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI11Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI11Q_TXBD_DESA) << BIT_SHIFT_HI11Q_TXBD_DESA) +#define BITS_HI11Q_TXBD_DESA \ + (BIT_MASK_HI11Q_TXBD_DESA << BIT_SHIFT_HI11Q_TXBD_DESA) +#define BIT_CLEAR_HI11Q_TXBD_DESA(x) ((x) & (~BITS_HI11Q_TXBD_DESA)) +#define BIT_GET_HI11Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA) & BIT_MASK_HI11Q_TXBD_DESA) +#define BIT_SET_HI11Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI11Q_TXBD_DESA(x) | BIT_HI11Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH11_TXBD_DESA_L (Offset 0x1390) */ + +#define BIT_SHIFT_ACH11_TXBD_DESA_L 0 +#define BIT_MASK_ACH11_TXBD_DESA_L 0xffffffffL +#define BIT_ACH11_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH11_TXBD_DESA_L) << BIT_SHIFT_ACH11_TXBD_DESA_L) +#define BITS_ACH11_TXBD_DESA_L \ + (BIT_MASK_ACH11_TXBD_DESA_L << BIT_SHIFT_ACH11_TXBD_DESA_L) +#define BIT_CLEAR_ACH11_TXBD_DESA_L(x) ((x) & (~BITS_ACH11_TXBD_DESA_L)) +#define BIT_GET_ACH11_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_L) & BIT_MASK_ACH11_TXBD_DESA_L) +#define BIT_SET_ACH11_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH11_TXBD_DESA_L(x) | BIT_ACH11_TXBD_DESA_L(v)) + +/* 2 REG_ACH11_TXBD_DESA_H (Offset 0x1394) */ + +#define BIT_SHIFT_ACH11_TXBD_DESA_H 0 +#define BIT_MASK_ACH11_TXBD_DESA_H 0xffffffffL +#define BIT_ACH11_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH11_TXBD_DESA_H) << BIT_SHIFT_ACH11_TXBD_DESA_H) +#define BITS_ACH11_TXBD_DESA_H \ + (BIT_MASK_ACH11_TXBD_DESA_H << BIT_SHIFT_ACH11_TXBD_DESA_H) +#define BIT_CLEAR_ACH11_TXBD_DESA_H(x) ((x) & (~BITS_ACH11_TXBD_DESA_H)) +#define BIT_GET_ACH11_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_H) & BIT_MASK_ACH11_TXBD_DESA_H) +#define BIT_SET_ACH11_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH11_TXBD_DESA_H(x) | BIT_ACH11_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI12Q_TXBD_DESA (Offset 0x1398) */ + +#define BIT_SHIFT_HI12Q_TXBD_DESA 0 +#define BIT_MASK_HI12Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI12Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI12Q_TXBD_DESA) << BIT_SHIFT_HI12Q_TXBD_DESA) +#define BITS_HI12Q_TXBD_DESA \ + (BIT_MASK_HI12Q_TXBD_DESA << BIT_SHIFT_HI12Q_TXBD_DESA) +#define BIT_CLEAR_HI12Q_TXBD_DESA(x) ((x) & (~BITS_HI12Q_TXBD_DESA)) +#define BIT_GET_HI12Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA) & BIT_MASK_HI12Q_TXBD_DESA) +#define BIT_SET_HI12Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI12Q_TXBD_DESA(x) | BIT_HI12Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH12_TXBD_DESA_L (Offset 0x1398) */ + +#define BIT_SHIFT_ACH12_TXBD_DESA_L 0 +#define BIT_MASK_ACH12_TXBD_DESA_L 0xffffffffL +#define BIT_ACH12_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH12_TXBD_DESA_L) << BIT_SHIFT_ACH12_TXBD_DESA_L) +#define BITS_ACH12_TXBD_DESA_L \ + (BIT_MASK_ACH12_TXBD_DESA_L << BIT_SHIFT_ACH12_TXBD_DESA_L) +#define BIT_CLEAR_ACH12_TXBD_DESA_L(x) ((x) & (~BITS_ACH12_TXBD_DESA_L)) +#define BIT_GET_ACH12_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_L) & BIT_MASK_ACH12_TXBD_DESA_L) +#define BIT_SET_ACH12_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH12_TXBD_DESA_L(x) | BIT_ACH12_TXBD_DESA_L(v)) + +/* 2 REG_ACH12_TXBD_DESA_H (Offset 0x139C) */ + +#define BIT_SHIFT_ACH12_TXBD_DESA_H 0 +#define BIT_MASK_ACH12_TXBD_DESA_H 0xffffffffL +#define BIT_ACH12_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH12_TXBD_DESA_H) << BIT_SHIFT_ACH12_TXBD_DESA_H) +#define BITS_ACH12_TXBD_DESA_H \ + (BIT_MASK_ACH12_TXBD_DESA_H << BIT_SHIFT_ACH12_TXBD_DESA_H) +#define BIT_CLEAR_ACH12_TXBD_DESA_H(x) ((x) & (~BITS_ACH12_TXBD_DESA_H)) +#define BIT_GET_ACH12_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_H) & BIT_MASK_ACH12_TXBD_DESA_H) +#define BIT_SET_ACH12_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH12_TXBD_DESA_H(x) | BIT_ACH12_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI13Q_TXBD_DESA (Offset 0x13A0) */ + +#define BIT_SHIFT_HI13Q_TXBD_DESA 0 +#define BIT_MASK_HI13Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI13Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI13Q_TXBD_DESA) << BIT_SHIFT_HI13Q_TXBD_DESA) +#define BITS_HI13Q_TXBD_DESA \ + (BIT_MASK_HI13Q_TXBD_DESA << BIT_SHIFT_HI13Q_TXBD_DESA) +#define BIT_CLEAR_HI13Q_TXBD_DESA(x) ((x) & (~BITS_HI13Q_TXBD_DESA)) +#define BIT_GET_HI13Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA) & BIT_MASK_HI13Q_TXBD_DESA) +#define BIT_SET_HI13Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI13Q_TXBD_DESA(x) | BIT_HI13Q_TXBD_DESA(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_ACH13_TXBD_DESA_L (Offset 0x13A0) */ + +#define BIT_SHIFT_ACH13_TXBD_DESA_L 0 +#define BIT_MASK_ACH13_TXBD_DESA_L 0xffffffffL +#define BIT_ACH13_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH13_TXBD_DESA_L) << BIT_SHIFT_ACH13_TXBD_DESA_L) +#define BITS_ACH13_TXBD_DESA_L \ + (BIT_MASK_ACH13_TXBD_DESA_L << BIT_SHIFT_ACH13_TXBD_DESA_L) +#define BIT_CLEAR_ACH13_TXBD_DESA_L(x) ((x) & (~BITS_ACH13_TXBD_DESA_L)) +#define BIT_GET_ACH13_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_L) & BIT_MASK_ACH13_TXBD_DESA_L) +#define BIT_SET_ACH13_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH13_TXBD_DESA_L(x) | BIT_ACH13_TXBD_DESA_L(v)) + +/* 2 REG_ACH13_TXBD_DESA_H (Offset 0x13A4) */ -#if (HALMAC_8197F_SUPPORT) +#define BIT_SHIFT_ACH13_TXBD_DESA_H 0 +#define BIT_MASK_ACH13_TXBD_DESA_H 0xffffffffL +#define BIT_ACH13_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH13_TXBD_DESA_H) << BIT_SHIFT_ACH13_TXBD_DESA_H) +#define BITS_ACH13_TXBD_DESA_H \ + (BIT_MASK_ACH13_TXBD_DESA_H << BIT_SHIFT_ACH13_TXBD_DESA_H) +#define BIT_CLEAR_ACH13_TXBD_DESA_H(x) ((x) & (~BITS_ACH13_TXBD_DESA_H)) +#define BIT_GET_ACH13_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_H) & BIT_MASK_ACH13_TXBD_DESA_H) +#define BIT_SET_ACH13_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH13_TXBD_DESA_H(x) | BIT_ACH13_TXBD_DESA_H(v)) + +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_HI14Q_TXBD_DESA (Offset 0x13A8) */ -#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT BIT(9) +#define BIT_SHIFT_HI14Q_TXBD_DESA 0 +#define BIT_MASK_HI14Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI14Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI14Q_TXBD_DESA) << BIT_SHIFT_HI14Q_TXBD_DESA) +#define BITS_HI14Q_TXBD_DESA \ + (BIT_MASK_HI14Q_TXBD_DESA << BIT_SHIFT_HI14Q_TXBD_DESA) +#define BIT_CLEAR_HI14Q_TXBD_DESA(x) ((x) & (~BITS_HI14Q_TXBD_DESA)) +#define BIT_GET_HI14Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA) & BIT_MASK_HI14Q_TXBD_DESA) +#define BIT_SET_HI14Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI14Q_TXBD_DESA(x) | BIT_HI14Q_TXBD_DESA(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_HI0Q_TXBD_DESA_L (Offset 0x13A8) */ +#define BIT_SHIFT_HI0Q_TXBD_DESA_L 0 +#define BIT_MASK_HI0Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI0Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_L) << BIT_SHIFT_HI0Q_TXBD_DESA_L) +#define BITS_HI0Q_TXBD_DESA_L \ + (BIT_MASK_HI0Q_TXBD_DESA_L << BIT_SHIFT_HI0Q_TXBD_DESA_L) +#define BIT_CLEAR_HI0Q_TXBD_DESA_L(x) ((x) & (~BITS_HI0Q_TXBD_DESA_L)) +#define BIT_GET_HI0Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_L) & BIT_MASK_HI0Q_TXBD_DESA_L) +#define BIT_SET_HI0Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_L(x) | BIT_HI0Q_TXBD_DESA_L(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_HI0Q_TXBD_DESA_H (Offset 0x13AC) */ -#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9) +#define BIT_SHIFT_HI0Q_TXBD_DESA_H 0 +#define BIT_MASK_HI0Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI0Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_H) << BIT_SHIFT_HI0Q_TXBD_DESA_H) +#define BITS_HI0Q_TXBD_DESA_H \ + (BIT_MASK_HI0Q_TXBD_DESA_H << BIT_SHIFT_HI0Q_TXBD_DESA_H) +#define BIT_CLEAR_HI0Q_TXBD_DESA_H(x) ((x) & (~BITS_HI0Q_TXBD_DESA_H)) +#define BIT_GET_HI0Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_H) & BIT_MASK_HI0Q_TXBD_DESA_H) +#define BIT_SET_HI0Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_H(x) | BIT_HI0Q_TXBD_DESA_H(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HI15Q_TXBD_DESA (Offset 0x13B0) */ +#define BIT_SHIFT_HI15Q_TXBD_DESA 0 +#define BIT_MASK_HI15Q_TXBD_DESA 0xffffffffffffffffL +#define BIT_HI15Q_TXBD_DESA(x) \ + (((x) & BIT_MASK_HI15Q_TXBD_DESA) << BIT_SHIFT_HI15Q_TXBD_DESA) +#define BITS_HI15Q_TXBD_DESA \ + (BIT_MASK_HI15Q_TXBD_DESA << BIT_SHIFT_HI15Q_TXBD_DESA) +#define BIT_CLEAR_HI15Q_TXBD_DESA(x) ((x) & (~BITS_HI15Q_TXBD_DESA)) +#define BIT_GET_HI15Q_TXBD_DESA(x) \ + (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA) & BIT_MASK_HI15Q_TXBD_DESA) +#define BIT_SET_HI15Q_TXBD_DESA(x, v) \ + (BIT_CLEAR_HI15Q_TXBD_DESA(x) | BIT_HI15Q_TXBD_DESA(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT BIT(8) +/* 2 REG_HI1Q_TXBD_DESA_L (Offset 0x13B0) */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_L 0 +#define BIT_MASK_HI1Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI1Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_L) << BIT_SHIFT_HI1Q_TXBD_DESA_L) +#define BITS_HI1Q_TXBD_DESA_L \ + (BIT_MASK_HI1Q_TXBD_DESA_L << BIT_SHIFT_HI1Q_TXBD_DESA_L) +#define BIT_CLEAR_HI1Q_TXBD_DESA_L(x) ((x) & (~BITS_HI1Q_TXBD_DESA_L)) +#define BIT_GET_HI1Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_L) & BIT_MASK_HI1Q_TXBD_DESA_L) +#define BIT_SET_HI1Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_L(x) | BIT_HI1Q_TXBD_DESA_L(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PCIE_HISR0_V1 (Offset 0x13B4) */ +#define BIT_PRE_TX_ERR_INT BIT(31) +#define BIT_HISR1_IND BIT(11) +#define BIT_TXDMAOK_CHANNEL15 BIT(7) +#define BIT_TXDMAOK_CHANNEL14 BIT(6) +#define BIT_TXDMAOK_CHANNEL3 BIT(5) +#define BIT_TXDMAOK_CHANNEL2 BIT(4) +#define BIT_TXDMAOK_CHANNEL1 BIT(3) +#define BIT_TXDMAOK_CHANNEL0 BIT(2) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8) +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI1Q_TXBD_DESA_H (Offset 0x13B4) */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_H 0 +#define BIT_MASK_HI1Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI1Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_H) << BIT_SHIFT_HI1Q_TXBD_DESA_H) +#define BITS_HI1Q_TXBD_DESA_H \ + (BIT_MASK_HI1Q_TXBD_DESA_H << BIT_SHIFT_HI1Q_TXBD_DESA_H) +#define BIT_CLEAR_HI1Q_TXBD_DESA_H(x) ((x) & (~BITS_HI1Q_TXBD_DESA_H)) +#define BIT_GET_HI1Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_H) & BIT_MASK_HI1Q_TXBD_DESA_H) +#define BIT_SET_HI1Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_H(x) | BIT_HI1Q_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI8Q_TXBD_NUM (Offset 0x13B8) */ + +#define BIT_HI8Q_FLAG BIT(14) + +#define BIT_SHIFT_HI8Q_DESC_MODE 12 +#define BIT_MASK_HI8Q_DESC_MODE 0x3 +#define BIT_HI8Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI8Q_DESC_MODE) << BIT_SHIFT_HI8Q_DESC_MODE) +#define BITS_HI8Q_DESC_MODE \ + (BIT_MASK_HI8Q_DESC_MODE << BIT_SHIFT_HI8Q_DESC_MODE) +#define BIT_CLEAR_HI8Q_DESC_MODE(x) ((x) & (~BITS_HI8Q_DESC_MODE)) +#define BIT_GET_HI8Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI8Q_DESC_MODE) & BIT_MASK_HI8Q_DESC_MODE) +#define BIT_SET_HI8Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI8Q_DESC_MODE(x) | BIT_HI8Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI8Q_DESC_NUM 0 +#define BIT_MASK_HI8Q_DESC_NUM 0xfff +#define BIT_HI8Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI8Q_DESC_NUM) << BIT_SHIFT_HI8Q_DESC_NUM) +#define BITS_HI8Q_DESC_NUM (BIT_MASK_HI8Q_DESC_NUM << BIT_SHIFT_HI8Q_DESC_NUM) +#define BIT_CLEAR_HI8Q_DESC_NUM(x) ((x) & (~BITS_HI8Q_DESC_NUM)) +#define BIT_GET_HI8Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI8Q_DESC_NUM) & BIT_MASK_HI8Q_DESC_NUM) +#define BIT_SET_HI8Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI8Q_DESC_NUM(x) | BIT_HI8Q_DESC_NUM(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_HI2Q_TXBD_DESA_L (Offset 0x13B8) */ +#define BIT_SHIFT_HI2Q_TXBD_DESA_L 0 +#define BIT_MASK_HI2Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI2Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_L) << BIT_SHIFT_HI2Q_TXBD_DESA_L) +#define BITS_HI2Q_TXBD_DESA_L \ + (BIT_MASK_HI2Q_TXBD_DESA_L << BIT_SHIFT_HI2Q_TXBD_DESA_L) +#define BIT_CLEAR_HI2Q_TXBD_DESA_L(x) ((x) & (~BITS_HI2Q_TXBD_DESA_L)) +#define BIT_GET_HI2Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_L) & BIT_MASK_HI2Q_TXBD_DESA_L) +#define BIT_SET_HI2Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_L(x) | BIT_HI2Q_TXBD_DESA_L(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI9Q_TXBD_NUM (Offset 0x13BA) */ + +#define BIT_HI9Q_FLAG BIT(14) + +#define BIT_SHIFT_HI9Q_DESC_MODE 12 +#define BIT_MASK_HI9Q_DESC_MODE 0x3 +#define BIT_HI9Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI9Q_DESC_MODE) << BIT_SHIFT_HI9Q_DESC_MODE) +#define BITS_HI9Q_DESC_MODE \ + (BIT_MASK_HI9Q_DESC_MODE << BIT_SHIFT_HI9Q_DESC_MODE) +#define BIT_CLEAR_HI9Q_DESC_MODE(x) ((x) & (~BITS_HI9Q_DESC_MODE)) +#define BIT_GET_HI9Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI9Q_DESC_MODE) & BIT_MASK_HI9Q_DESC_MODE) +#define BIT_SET_HI9Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI9Q_DESC_MODE(x) | BIT_HI9Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI9Q_DESC_NUM 0 +#define BIT_MASK_HI9Q_DESC_NUM 0xfff +#define BIT_HI9Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI9Q_DESC_NUM) << BIT_SHIFT_HI9Q_DESC_NUM) +#define BITS_HI9Q_DESC_NUM (BIT_MASK_HI9Q_DESC_NUM << BIT_SHIFT_HI9Q_DESC_NUM) +#define BIT_CLEAR_HI9Q_DESC_NUM(x) ((x) & (~BITS_HI9Q_DESC_NUM)) +#define BIT_GET_HI9Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI9Q_DESC_NUM) & BIT_MASK_HI9Q_DESC_NUM) +#define BIT_SET_HI9Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI9Q_DESC_NUM(x) | BIT_HI9Q_DESC_NUM(v)) + +/* 2 REG_HI10Q_TXBD_NUM (Offset 0x13BC) */ + +#define BIT_HI10Q_FLAG BIT(14) + +#define BIT_SHIFT_HI10Q_DESC_MODE 12 +#define BIT_MASK_HI10Q_DESC_MODE 0x3 +#define BIT_HI10Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI10Q_DESC_MODE) << BIT_SHIFT_HI10Q_DESC_MODE) +#define BITS_HI10Q_DESC_MODE \ + (BIT_MASK_HI10Q_DESC_MODE << BIT_SHIFT_HI10Q_DESC_MODE) +#define BIT_CLEAR_HI10Q_DESC_MODE(x) ((x) & (~BITS_HI10Q_DESC_MODE)) +#define BIT_GET_HI10Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI10Q_DESC_MODE) & BIT_MASK_HI10Q_DESC_MODE) +#define BIT_SET_HI10Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI10Q_DESC_MODE(x) | BIT_HI10Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI10Q_DESC_NUM 0 +#define BIT_MASK_HI10Q_DESC_NUM 0xfff +#define BIT_HI10Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI10Q_DESC_NUM) << BIT_SHIFT_HI10Q_DESC_NUM) +#define BITS_HI10Q_DESC_NUM \ + (BIT_MASK_HI10Q_DESC_NUM << BIT_SHIFT_HI10Q_DESC_NUM) +#define BIT_CLEAR_HI10Q_DESC_NUM(x) ((x) & (~BITS_HI10Q_DESC_NUM)) +#define BIT_GET_HI10Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI10Q_DESC_NUM) & BIT_MASK_HI10Q_DESC_NUM) +#define BIT_SET_HI10Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI10Q_DESC_NUM(x) | BIT_HI10Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI2Q_TXBD_DESA_H (Offset 0x13BC) */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_H 0 +#define BIT_MASK_HI2Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI2Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_H) << BIT_SHIFT_HI2Q_TXBD_DESA_H) +#define BITS_HI2Q_TXBD_DESA_H \ + (BIT_MASK_HI2Q_TXBD_DESA_H << BIT_SHIFT_HI2Q_TXBD_DESA_H) +#define BIT_CLEAR_HI2Q_TXBD_DESA_H(x) ((x) & (~BITS_HI2Q_TXBD_DESA_H)) +#define BIT_GET_HI2Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_H) & BIT_MASK_HI2Q_TXBD_DESA_H) +#define BIT_SET_HI2Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_H(x) | BIT_HI2Q_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI11Q_TXBD_NUM (Offset 0x13BE) */ + +#define BIT_HI11Q_FLAG BIT(14) + +#define BIT_SHIFT_HI11Q_DESC_MODE 12 +#define BIT_MASK_HI11Q_DESC_MODE 0x3 +#define BIT_HI11Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI11Q_DESC_MODE) << BIT_SHIFT_HI11Q_DESC_MODE) +#define BITS_HI11Q_DESC_MODE \ + (BIT_MASK_HI11Q_DESC_MODE << BIT_SHIFT_HI11Q_DESC_MODE) +#define BIT_CLEAR_HI11Q_DESC_MODE(x) ((x) & (~BITS_HI11Q_DESC_MODE)) +#define BIT_GET_HI11Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI11Q_DESC_MODE) & BIT_MASK_HI11Q_DESC_MODE) +#define BIT_SET_HI11Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI11Q_DESC_MODE(x) | BIT_HI11Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI11Q_DESC_NUM 0 +#define BIT_MASK_HI11Q_DESC_NUM 0xfff +#define BIT_HI11Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI11Q_DESC_NUM) << BIT_SHIFT_HI11Q_DESC_NUM) +#define BITS_HI11Q_DESC_NUM \ + (BIT_MASK_HI11Q_DESC_NUM << BIT_SHIFT_HI11Q_DESC_NUM) +#define BIT_CLEAR_HI11Q_DESC_NUM(x) ((x) & (~BITS_HI11Q_DESC_NUM)) +#define BIT_GET_HI11Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI11Q_DESC_NUM) & BIT_MASK_HI11Q_DESC_NUM) +#define BIT_SET_HI11Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI11Q_DESC_NUM(x) | BIT_HI11Q_DESC_NUM(v)) + +/* 2 REG_HI12Q_TXBD_NUM (Offset 0x13C0) */ + +#define BIT_HI12Q_FLAG BIT(14) + +#define BIT_SHIFT_HI12Q_DESC_MODE 12 +#define BIT_MASK_HI12Q_DESC_MODE 0x3 +#define BIT_HI12Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI12Q_DESC_MODE) << BIT_SHIFT_HI12Q_DESC_MODE) +#define BITS_HI12Q_DESC_MODE \ + (BIT_MASK_HI12Q_DESC_MODE << BIT_SHIFT_HI12Q_DESC_MODE) +#define BIT_CLEAR_HI12Q_DESC_MODE(x) ((x) & (~BITS_HI12Q_DESC_MODE)) +#define BIT_GET_HI12Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI12Q_DESC_MODE) & BIT_MASK_HI12Q_DESC_MODE) +#define BIT_SET_HI12Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI12Q_DESC_MODE(x) | BIT_HI12Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI12Q_DESC_NUM 0 +#define BIT_MASK_HI12Q_DESC_NUM 0xfff +#define BIT_HI12Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI12Q_DESC_NUM) << BIT_SHIFT_HI12Q_DESC_NUM) +#define BITS_HI12Q_DESC_NUM \ + (BIT_MASK_HI12Q_DESC_NUM << BIT_SHIFT_HI12Q_DESC_NUM) +#define BIT_CLEAR_HI12Q_DESC_NUM(x) ((x) & (~BITS_HI12Q_DESC_NUM)) +#define BIT_GET_HI12Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI12Q_DESC_NUM) & BIT_MASK_HI12Q_DESC_NUM) +#define BIT_SET_HI12Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI12Q_DESC_NUM(x) | BIT_HI12Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI3Q_TXBD_DESA_L (Offset 0x13C0) */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_L 0 +#define BIT_MASK_HI3Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI3Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_L) << BIT_SHIFT_HI3Q_TXBD_DESA_L) +#define BITS_HI3Q_TXBD_DESA_L \ + (BIT_MASK_HI3Q_TXBD_DESA_L << BIT_SHIFT_HI3Q_TXBD_DESA_L) +#define BIT_CLEAR_HI3Q_TXBD_DESA_L(x) ((x) & (~BITS_HI3Q_TXBD_DESA_L)) +#define BIT_GET_HI3Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_L) & BIT_MASK_HI3Q_TXBD_DESA_L) +#define BIT_SET_HI3Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_L(x) | BIT_HI3Q_TXBD_DESA_L(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI13Q_TXBD_NUM (Offset 0x13C2) */ + +#define BIT_HI13Q_FLAG BIT(14) + +#define BIT_SHIFT_HI13Q_DESC_MODE 12 +#define BIT_MASK_HI13Q_DESC_MODE 0x3 +#define BIT_HI13Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI13Q_DESC_MODE) << BIT_SHIFT_HI13Q_DESC_MODE) +#define BITS_HI13Q_DESC_MODE \ + (BIT_MASK_HI13Q_DESC_MODE << BIT_SHIFT_HI13Q_DESC_MODE) +#define BIT_CLEAR_HI13Q_DESC_MODE(x) ((x) & (~BITS_HI13Q_DESC_MODE)) +#define BIT_GET_HI13Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI13Q_DESC_MODE) & BIT_MASK_HI13Q_DESC_MODE) +#define BIT_SET_HI13Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI13Q_DESC_MODE(x) | BIT_HI13Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI13Q_DESC_NUM 0 +#define BIT_MASK_HI13Q_DESC_NUM 0xfff +#define BIT_HI13Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI13Q_DESC_NUM) << BIT_SHIFT_HI13Q_DESC_NUM) +#define BITS_HI13Q_DESC_NUM \ + (BIT_MASK_HI13Q_DESC_NUM << BIT_SHIFT_HI13Q_DESC_NUM) +#define BIT_CLEAR_HI13Q_DESC_NUM(x) ((x) & (~BITS_HI13Q_DESC_NUM)) +#define BIT_GET_HI13Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI13Q_DESC_NUM) & BIT_MASK_HI13Q_DESC_NUM) +#define BIT_SET_HI13Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI13Q_DESC_NUM(x) | BIT_HI13Q_DESC_NUM(v)) + +/* 2 REG_HI14Q_TXBD_NUM (Offset 0x13C4) */ + +#define BIT_HI14Q_FLAG BIT(14) + +#define BIT_SHIFT_HI14Q_DESC_MODE 12 +#define BIT_MASK_HI14Q_DESC_MODE 0x3 +#define BIT_HI14Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI14Q_DESC_MODE) << BIT_SHIFT_HI14Q_DESC_MODE) +#define BITS_HI14Q_DESC_MODE \ + (BIT_MASK_HI14Q_DESC_MODE << BIT_SHIFT_HI14Q_DESC_MODE) +#define BIT_CLEAR_HI14Q_DESC_MODE(x) ((x) & (~BITS_HI14Q_DESC_MODE)) +#define BIT_GET_HI14Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI14Q_DESC_MODE) & BIT_MASK_HI14Q_DESC_MODE) +#define BIT_SET_HI14Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI14Q_DESC_MODE(x) | BIT_HI14Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI14Q_DESC_NUM 0 +#define BIT_MASK_HI14Q_DESC_NUM 0xfff +#define BIT_HI14Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI14Q_DESC_NUM) << BIT_SHIFT_HI14Q_DESC_NUM) +#define BITS_HI14Q_DESC_NUM \ + (BIT_MASK_HI14Q_DESC_NUM << BIT_SHIFT_HI14Q_DESC_NUM) +#define BIT_CLEAR_HI14Q_DESC_NUM(x) ((x) & (~BITS_HI14Q_DESC_NUM)) +#define BIT_GET_HI14Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI14Q_DESC_NUM) & BIT_MASK_HI14Q_DESC_NUM) +#define BIT_SET_HI14Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI14Q_DESC_NUM(x) | BIT_HI14Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI3Q_TXBD_DESA_H (Offset 0x13C4) */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_H 0 +#define BIT_MASK_HI3Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI3Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_H) << BIT_SHIFT_HI3Q_TXBD_DESA_H) +#define BITS_HI3Q_TXBD_DESA_H \ + (BIT_MASK_HI3Q_TXBD_DESA_H << BIT_SHIFT_HI3Q_TXBD_DESA_H) +#define BIT_CLEAR_HI3Q_TXBD_DESA_H(x) ((x) & (~BITS_HI3Q_TXBD_DESA_H)) +#define BIT_GET_HI3Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_H) & BIT_MASK_HI3Q_TXBD_DESA_H) +#define BIT_SET_HI3Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_H(x) | BIT_HI3Q_TXBD_DESA_H(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_HI15Q_TXBD_NUM (Offset 0x13C6) */ + +#define BIT_HI15Q_FLAG BIT(14) + +#define BIT_SHIFT_HI15Q_DESC_MODE 12 +#define BIT_MASK_HI15Q_DESC_MODE 0x3 +#define BIT_HI15Q_DESC_MODE(x) \ + (((x) & BIT_MASK_HI15Q_DESC_MODE) << BIT_SHIFT_HI15Q_DESC_MODE) +#define BITS_HI15Q_DESC_MODE \ + (BIT_MASK_HI15Q_DESC_MODE << BIT_SHIFT_HI15Q_DESC_MODE) +#define BIT_CLEAR_HI15Q_DESC_MODE(x) ((x) & (~BITS_HI15Q_DESC_MODE)) +#define BIT_GET_HI15Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_HI15Q_DESC_MODE) & BIT_MASK_HI15Q_DESC_MODE) +#define BIT_SET_HI15Q_DESC_MODE(x, v) \ + (BIT_CLEAR_HI15Q_DESC_MODE(x) | BIT_HI15Q_DESC_MODE(v)) + +#define BIT_SHIFT_HI15Q_DESC_NUM 0 +#define BIT_MASK_HI15Q_DESC_NUM 0xfff +#define BIT_HI15Q_DESC_NUM(x) \ + (((x) & BIT_MASK_HI15Q_DESC_NUM) << BIT_SHIFT_HI15Q_DESC_NUM) +#define BITS_HI15Q_DESC_NUM \ + (BIT_MASK_HI15Q_DESC_NUM << BIT_SHIFT_HI15Q_DESC_NUM) +#define BIT_CLEAR_HI15Q_DESC_NUM(x) ((x) & (~BITS_HI15Q_DESC_NUM)) +#define BIT_GET_HI15Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_HI15Q_DESC_NUM) & BIT_MASK_HI15Q_DESC_NUM) +#define BIT_SET_HI15Q_DESC_NUM(x, v) \ + (BIT_CLEAR_HI15Q_DESC_NUM(x) | BIT_HI15Q_DESC_NUM(v)) + +/* 2 REG_HIQ_DMA_STOP (Offset 0x13C8) */ + +#define BIT_STOP_HI15Q BIT(7) +#define BIT_STOP_HI14Q BIT(6) +#define BIT_STOP_HI13Q BIT(5) +#define BIT_STOP_HI12Q BIT(4) +#define BIT_STOP_HI11Q BIT(3) +#define BIT_STOP_HI10Q BIT(2) +#define BIT_STOP_HI9Q BIT(1) +#define BIT_STOP_HI8Q BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HI4Q_TXBD_DESA_L (Offset 0x13C8) */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_L 0 +#define BIT_MASK_HI4Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI4Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_L) << BIT_SHIFT_HI4Q_TXBD_DESA_L) +#define BITS_HI4Q_TXBD_DESA_L \ + (BIT_MASK_HI4Q_TXBD_DESA_L << BIT_SHIFT_HI4Q_TXBD_DESA_L) +#define BIT_CLEAR_HI4Q_TXBD_DESA_L(x) ((x) & (~BITS_HI4Q_TXBD_DESA_L)) +#define BIT_GET_HI4Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_L) & BIT_MASK_HI4Q_TXBD_DESA_L) +#define BIT_SET_HI4Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_L(x) | BIT_HI4Q_TXBD_DESA_L(v)) + +/* 2 REG_HI4Q_TXBD_DESA_H (Offset 0x13CC) */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_H 0 +#define BIT_MASK_HI4Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI4Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_H) << BIT_SHIFT_HI4Q_TXBD_DESA_H) +#define BITS_HI4Q_TXBD_DESA_H \ + (BIT_MASK_HI4Q_TXBD_DESA_H << BIT_SHIFT_HI4Q_TXBD_DESA_H) +#define BIT_CLEAR_HI4Q_TXBD_DESA_H(x) ((x) & (~BITS_HI4Q_TXBD_DESA_H)) +#define BIT_GET_HI4Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_H) & BIT_MASK_HI4Q_TXBD_DESA_H) +#define BIT_SET_HI4Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_H(x) | BIT_HI4Q_TXBD_DESA_H(v)) + +/* 2 REG_HI5Q_TXBD_DESA_L (Offset 0x13D0) */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_L 0 +#define BIT_MASK_HI5Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI5Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_L) << BIT_SHIFT_HI5Q_TXBD_DESA_L) +#define BITS_HI5Q_TXBD_DESA_L \ + (BIT_MASK_HI5Q_TXBD_DESA_L << BIT_SHIFT_HI5Q_TXBD_DESA_L) +#define BIT_CLEAR_HI5Q_TXBD_DESA_L(x) ((x) & (~BITS_HI5Q_TXBD_DESA_L)) +#define BIT_GET_HI5Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_L) & BIT_MASK_HI5Q_TXBD_DESA_L) +#define BIT_SET_HI5Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_L(x) | BIT_HI5Q_TXBD_DESA_L(v)) + +/* 2 REG_HI5Q_TXBD_DESA_H (Offset 0x13D4) */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_H 0 +#define BIT_MASK_HI5Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI5Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_H) << BIT_SHIFT_HI5Q_TXBD_DESA_H) +#define BITS_HI5Q_TXBD_DESA_H \ + (BIT_MASK_HI5Q_TXBD_DESA_H << BIT_SHIFT_HI5Q_TXBD_DESA_H) +#define BIT_CLEAR_HI5Q_TXBD_DESA_H(x) ((x) & (~BITS_HI5Q_TXBD_DESA_H)) +#define BIT_GET_HI5Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_H) & BIT_MASK_HI5Q_TXBD_DESA_H) +#define BIT_SET_HI5Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_H(x) | BIT_HI5Q_TXBD_DESA_H(v)) + +/* 2 REG_HI6Q_TXBD_DESA_L (Offset 0x13D8) */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_L 0 +#define BIT_MASK_HI6Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI6Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_L) << BIT_SHIFT_HI6Q_TXBD_DESA_L) +#define BITS_HI6Q_TXBD_DESA_L \ + (BIT_MASK_HI6Q_TXBD_DESA_L << BIT_SHIFT_HI6Q_TXBD_DESA_L) +#define BIT_CLEAR_HI6Q_TXBD_DESA_L(x) ((x) & (~BITS_HI6Q_TXBD_DESA_L)) +#define BIT_GET_HI6Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_L) & BIT_MASK_HI6Q_TXBD_DESA_L) +#define BIT_SET_HI6Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_L(x) | BIT_HI6Q_TXBD_DESA_L(v)) + +/* 2 REG_HI6Q_TXBD_DESA_H (Offset 0x13DC) */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_H 0 +#define BIT_MASK_HI6Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI6Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_H) << BIT_SHIFT_HI6Q_TXBD_DESA_H) +#define BITS_HI6Q_TXBD_DESA_H \ + (BIT_MASK_HI6Q_TXBD_DESA_H << BIT_SHIFT_HI6Q_TXBD_DESA_H) +#define BIT_CLEAR_HI6Q_TXBD_DESA_H(x) ((x) & (~BITS_HI6Q_TXBD_DESA_H)) +#define BIT_GET_HI6Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_H) & BIT_MASK_HI6Q_TXBD_DESA_H) +#define BIT_SET_HI6Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_H(x) | BIT_HI6Q_TXBD_DESA_H(v)) + +/* 2 REG_HI7Q_TXBD_DESA_L (Offset 0x13E0) */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_L 0 +#define BIT_MASK_HI7Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI7Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_L) << BIT_SHIFT_HI7Q_TXBD_DESA_L) +#define BITS_HI7Q_TXBD_DESA_L \ + (BIT_MASK_HI7Q_TXBD_DESA_L << BIT_SHIFT_HI7Q_TXBD_DESA_L) +#define BIT_CLEAR_HI7Q_TXBD_DESA_L(x) ((x) & (~BITS_HI7Q_TXBD_DESA_L)) +#define BIT_GET_HI7Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_L) & BIT_MASK_HI7Q_TXBD_DESA_L) +#define BIT_SET_HI7Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_L(x) | BIT_HI7Q_TXBD_DESA_L(v)) + +/* 2 REG_HI7Q_TXBD_DESA_H (Offset 0x13E4) */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_H 0 +#define BIT_MASK_HI7Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI7Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_H) << BIT_SHIFT_HI7Q_TXBD_DESA_H) +#define BITS_HI7Q_TXBD_DESA_H \ + (BIT_MASK_HI7Q_TXBD_DESA_H << BIT_SHIFT_HI7Q_TXBD_DESA_H) +#define BIT_CLEAR_HI7Q_TXBD_DESA_H(x) ((x) & (~BITS_HI7Q_TXBD_DESA_H)) +#define BIT_GET_HI7Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_H) & BIT_MASK_HI7Q_TXBD_DESA_H) +#define BIT_SET_HI7Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_H(x) | BIT_HI7Q_TXBD_DESA_H(v)) + +/* 2 REG_ACH8_ACH9_TXBD_NUM (Offset 0x13E8) */ + +#define BIT_PCIE_ACH9_FLAG BIT(30) + +#define BIT_SHIFT_ACH9_DESC_MODE 28 +#define BIT_MASK_ACH9_DESC_MODE 0x3 +#define BIT_ACH9_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH9_DESC_MODE) << BIT_SHIFT_ACH9_DESC_MODE) +#define BITS_ACH9_DESC_MODE \ + (BIT_MASK_ACH9_DESC_MODE << BIT_SHIFT_ACH9_DESC_MODE) +#define BIT_CLEAR_ACH9_DESC_MODE(x) ((x) & (~BITS_ACH9_DESC_MODE)) +#define BIT_GET_ACH9_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH9_DESC_MODE) & BIT_MASK_ACH9_DESC_MODE) +#define BIT_SET_ACH9_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH9_DESC_MODE(x) | BIT_ACH9_DESC_MODE(v)) + +#define BIT_SHIFT_ACH9_DESC_NUM 16 +#define BIT_MASK_ACH9_DESC_NUM 0xfff +#define BIT_ACH9_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH9_DESC_NUM) << BIT_SHIFT_ACH9_DESC_NUM) +#define BITS_ACH9_DESC_NUM (BIT_MASK_ACH9_DESC_NUM << BIT_SHIFT_ACH9_DESC_NUM) +#define BIT_CLEAR_ACH9_DESC_NUM(x) ((x) & (~BITS_ACH9_DESC_NUM)) +#define BIT_GET_ACH9_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH9_DESC_NUM) & BIT_MASK_ACH9_DESC_NUM) +#define BIT_SET_ACH9_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH9_DESC_NUM(x) | BIT_ACH9_DESC_NUM(v)) + +#define BIT_PCIE_ACH8_FLAG BIT(14) + +#define BIT_SHIFT_ACH8_DESC_MODE 12 +#define BIT_MASK_ACH8_DESC_MODE 0x3 +#define BIT_ACH8_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH8_DESC_MODE) << BIT_SHIFT_ACH8_DESC_MODE) +#define BITS_ACH8_DESC_MODE \ + (BIT_MASK_ACH8_DESC_MODE << BIT_SHIFT_ACH8_DESC_MODE) +#define BIT_CLEAR_ACH8_DESC_MODE(x) ((x) & (~BITS_ACH8_DESC_MODE)) +#define BIT_GET_ACH8_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH8_DESC_MODE) & BIT_MASK_ACH8_DESC_MODE) +#define BIT_SET_ACH8_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH8_DESC_MODE(x) | BIT_ACH8_DESC_MODE(v)) + +#define BIT_SHIFT_ACH8_DESC_NUM 0 +#define BIT_MASK_ACH8_DESC_NUM 0xfff +#define BIT_ACH8_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH8_DESC_NUM) << BIT_SHIFT_ACH8_DESC_NUM) +#define BITS_ACH8_DESC_NUM (BIT_MASK_ACH8_DESC_NUM << BIT_SHIFT_ACH8_DESC_NUM) +#define BIT_CLEAR_ACH8_DESC_NUM(x) ((x) & (~BITS_ACH8_DESC_NUM)) +#define BIT_GET_ACH8_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH8_DESC_NUM) & BIT_MASK_ACH8_DESC_NUM) +#define BIT_SET_ACH8_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH8_DESC_NUM(x) | BIT_ACH8_DESC_NUM(v)) + +/* 2 REG_ACH10_ACH11_TXBD_NUM (Offset 0x13EC) */ + +#define BIT_PCIE_ACH11_FLAG BIT(30) + +#define BIT_SHIFT_ACH11_DESC_MODE 28 +#define BIT_MASK_ACH11_DESC_MODE 0x3 +#define BIT_ACH11_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH11_DESC_MODE) << BIT_SHIFT_ACH11_DESC_MODE) +#define BITS_ACH11_DESC_MODE \ + (BIT_MASK_ACH11_DESC_MODE << BIT_SHIFT_ACH11_DESC_MODE) +#define BIT_CLEAR_ACH11_DESC_MODE(x) ((x) & (~BITS_ACH11_DESC_MODE)) +#define BIT_GET_ACH11_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH11_DESC_MODE) & BIT_MASK_ACH11_DESC_MODE) +#define BIT_SET_ACH11_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH11_DESC_MODE(x) | BIT_ACH11_DESC_MODE(v)) + +#define BIT_SHIFT_ACH11_DESC_NUM 16 +#define BIT_MASK_ACH11_DESC_NUM 0xfff +#define BIT_ACH11_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH11_DESC_NUM) << BIT_SHIFT_ACH11_DESC_NUM) +#define BITS_ACH11_DESC_NUM \ + (BIT_MASK_ACH11_DESC_NUM << BIT_SHIFT_ACH11_DESC_NUM) +#define BIT_CLEAR_ACH11_DESC_NUM(x) ((x) & (~BITS_ACH11_DESC_NUM)) +#define BIT_GET_ACH11_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH11_DESC_NUM) & BIT_MASK_ACH11_DESC_NUM) +#define BIT_SET_ACH11_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH11_DESC_NUM(x) | BIT_ACH11_DESC_NUM(v)) + +#define BIT_PCIE_ACH10_FLAG BIT(14) + +#define BIT_SHIFT_ACH10_DESC_MODE 12 +#define BIT_MASK_ACH10_DESC_MODE 0x3 +#define BIT_ACH10_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH10_DESC_MODE) << BIT_SHIFT_ACH10_DESC_MODE) +#define BITS_ACH10_DESC_MODE \ + (BIT_MASK_ACH10_DESC_MODE << BIT_SHIFT_ACH10_DESC_MODE) +#define BIT_CLEAR_ACH10_DESC_MODE(x) ((x) & (~BITS_ACH10_DESC_MODE)) +#define BIT_GET_ACH10_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH10_DESC_MODE) & BIT_MASK_ACH10_DESC_MODE) +#define BIT_SET_ACH10_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH10_DESC_MODE(x) | BIT_ACH10_DESC_MODE(v)) + +#define BIT_SHIFT_ACH10_DESC_NUM 0 +#define BIT_MASK_ACH10_DESC_NUM 0xfff +#define BIT_ACH10_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH10_DESC_NUM) << BIT_SHIFT_ACH10_DESC_NUM) +#define BITS_ACH10_DESC_NUM \ + (BIT_MASK_ACH10_DESC_NUM << BIT_SHIFT_ACH10_DESC_NUM) +#define BIT_CLEAR_ACH10_DESC_NUM(x) ((x) & (~BITS_ACH10_DESC_NUM)) +#define BIT_GET_ACH10_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH10_DESC_NUM) & BIT_MASK_ACH10_DESC_NUM) +#define BIT_SET_ACH10_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH10_DESC_NUM(x) | BIT_ACH10_DESC_NUM(v)) + +/* 2 REG_ACH12_ACH13_TXBD_NUM (Offset 0x13F0) */ + +#define BIT_PCIE_ACH13_FLAG BIT(30) + +#define BIT_SHIFT_ACH13_DESC_MODE 28 +#define BIT_MASK_ACH13_DESC_MODE 0x3 +#define BIT_ACH13_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH13_DESC_MODE) << BIT_SHIFT_ACH13_DESC_MODE) +#define BITS_ACH13_DESC_MODE \ + (BIT_MASK_ACH13_DESC_MODE << BIT_SHIFT_ACH13_DESC_MODE) +#define BIT_CLEAR_ACH13_DESC_MODE(x) ((x) & (~BITS_ACH13_DESC_MODE)) +#define BIT_GET_ACH13_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH13_DESC_MODE) & BIT_MASK_ACH13_DESC_MODE) +#define BIT_SET_ACH13_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH13_DESC_MODE(x) | BIT_ACH13_DESC_MODE(v)) + +#define BIT_SHIFT_ACH13_DESC_NUM 16 +#define BIT_MASK_ACH13_DESC_NUM 0xfff +#define BIT_ACH13_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH13_DESC_NUM) << BIT_SHIFT_ACH13_DESC_NUM) +#define BITS_ACH13_DESC_NUM \ + (BIT_MASK_ACH13_DESC_NUM << BIT_SHIFT_ACH13_DESC_NUM) +#define BIT_CLEAR_ACH13_DESC_NUM(x) ((x) & (~BITS_ACH13_DESC_NUM)) +#define BIT_GET_ACH13_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH13_DESC_NUM) & BIT_MASK_ACH13_DESC_NUM) +#define BIT_SET_ACH13_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH13_DESC_NUM(x) | BIT_ACH13_DESC_NUM(v)) + +#define BIT_PCIE_ACH12_FLAG BIT(14) + +#define BIT_SHIFT_ACH12_DESC_MODE 12 +#define BIT_MASK_ACH12_DESC_MODE 0x3 +#define BIT_ACH12_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH12_DESC_MODE) << BIT_SHIFT_ACH12_DESC_MODE) +#define BITS_ACH12_DESC_MODE \ + (BIT_MASK_ACH12_DESC_MODE << BIT_SHIFT_ACH12_DESC_MODE) +#define BIT_CLEAR_ACH12_DESC_MODE(x) ((x) & (~BITS_ACH12_DESC_MODE)) +#define BIT_GET_ACH12_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH12_DESC_MODE) & BIT_MASK_ACH12_DESC_MODE) +#define BIT_SET_ACH12_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH12_DESC_MODE(x) | BIT_ACH12_DESC_MODE(v)) + +#define BIT_SHIFT_ACH12_DESC_NUM 0 +#define BIT_MASK_ACH12_DESC_NUM 0xfff +#define BIT_ACH12_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH12_DESC_NUM) << BIT_SHIFT_ACH12_DESC_NUM) +#define BITS_ACH12_DESC_NUM \ + (BIT_MASK_ACH12_DESC_NUM << BIT_SHIFT_ACH12_DESC_NUM) +#define BIT_CLEAR_ACH12_DESC_NUM(x) ((x) & (~BITS_ACH12_DESC_NUM)) +#define BIT_GET_ACH12_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH12_DESC_NUM) & BIT_MASK_ACH12_DESC_NUM) +#define BIT_SET_ACH12_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH12_DESC_NUM(x) | BIT_ACH12_DESC_NUM(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) + +/* 2 REG_OLD_DEHANG (Offset 0x13F4) */ -#define BIT_PORT4_TX_NULL1_DONE_INT BIT(7) +#define BIT_OLD_DEHANG BIT(1) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_ACH4_TXBD_DESA_L (Offset 0x13F8) */ +#define BIT_SHIFT_ACH4_TXBD_DESA_L 0 +#define BIT_MASK_ACH4_TXBD_DESA_L 0xffffffffL +#define BIT_ACH4_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_ACH4_TXBD_DESA_L) << BIT_SHIFT_ACH4_TXBD_DESA_L) +#define BITS_ACH4_TXBD_DESA_L \ + (BIT_MASK_ACH4_TXBD_DESA_L << BIT_SHIFT_ACH4_TXBD_DESA_L) +#define BIT_CLEAR_ACH4_TXBD_DESA_L(x) ((x) & (~BITS_ACH4_TXBD_DESA_L)) +#define BIT_GET_ACH4_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_L) & BIT_MASK_ACH4_TXBD_DESA_L) +#define BIT_SET_ACH4_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_ACH4_TXBD_DESA_L(x) | BIT_ACH4_TXBD_DESA_L(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_ACH4_TXBD_DESA_H (Offset 0x13FC) */ -#define BIT_FS_CLI3_TX_NULL1_INT BIT(7) +#define BIT_SHIFT_ACH4_TXBD_DESA_H 0 +#define BIT_MASK_ACH4_TXBD_DESA_H 0xffffffffL +#define BIT_ACH4_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_ACH4_TXBD_DESA_H) << BIT_SHIFT_ACH4_TXBD_DESA_H) +#define BITS_ACH4_TXBD_DESA_H \ + (BIT_MASK_ACH4_TXBD_DESA_H << BIT_SHIFT_ACH4_TXBD_DESA_H) +#define BIT_CLEAR_ACH4_TXBD_DESA_H(x) ((x) & (~BITS_ACH4_TXBD_DESA_H)) +#define BIT_GET_ACH4_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_H) & BIT_MASK_ACH4_TXBD_DESA_H) +#define BIT_SET_ACH4_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_ACH4_TXBD_DESA_H(x) | BIT_ACH4_TXBD_DESA_H(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_Q0_Q1_INFO (Offset 0x1400) */ +#define BIT_SHIFT_AC1_PKT_INFO 16 +#define BIT_MASK_AC1_PKT_INFO 0xfff +#define BIT_AC1_PKT_INFO(x) \ + (((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO) +#define BITS_AC1_PKT_INFO (BIT_MASK_AC1_PKT_INFO << BIT_SHIFT_AC1_PKT_INFO) +#define BIT_CLEAR_AC1_PKT_INFO(x) ((x) & (~BITS_AC1_PKT_INFO)) +#define BIT_GET_AC1_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO) +#define BIT_SET_AC1_PKT_INFO(x, v) \ + (BIT_CLEAR_AC1_PKT_INFO(x) | BIT_AC1_PKT_INFO(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT4_TX_NULL0_DONE_INT BIT(6) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_MU_OFFSET (Offset 0x1400) */ +#define BIT_SHIFT_MU_RATETABLE_OFFSET 16 +#define BIT_MASK_MU_RATETABLE_OFFSET 0x1ff +#define BIT_MU_RATETABLE_OFFSET(x) \ + (((x) & BIT_MASK_MU_RATETABLE_OFFSET) << BIT_SHIFT_MU_RATETABLE_OFFSET) +#define BITS_MU_RATETABLE_OFFSET \ + (BIT_MASK_MU_RATETABLE_OFFSET << BIT_SHIFT_MU_RATETABLE_OFFSET) +#define BIT_CLEAR_MU_RATETABLE_OFFSET(x) ((x) & (~BITS_MU_RATETABLE_OFFSET)) +#define BIT_GET_MU_RATETABLE_OFFSET(x) \ + (((x) >> BIT_SHIFT_MU_RATETABLE_OFFSET) & BIT_MASK_MU_RATETABLE_OFFSET) +#define BIT_SET_MU_RATETABLE_OFFSET(x, v) \ + (BIT_CLEAR_MU_RATETABLE_OFFSET(x) | BIT_MU_RATETABLE_OFFSET(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_Q0_Q1_INFO (Offset 0x1400) */ -#define BIT_FS_CLI3_TX_NULL0_INT BIT(6) +#define BIT_SHIFT_AC0_PKT_INFO 0 +#define BIT_MASK_AC0_PKT_INFO 0xfff +#define BIT_AC0_PKT_INFO(x) \ + (((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO) +#define BITS_AC0_PKT_INFO (BIT_MASK_AC0_PKT_INFO << BIT_SHIFT_AC0_PKT_INFO) +#define BIT_CLEAR_AC0_PKT_INFO(x) ((x) & (~BITS_AC0_PKT_INFO)) +#define BIT_GET_AC0_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO) +#define BIT_SET_AC0_PKT_INFO(x, v) \ + (BIT_CLEAR_AC0_PKT_INFO(x) | BIT_AC0_PKT_INFO(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_ARFR6 (Offset 0x1400) */ +#define BIT_SHIFT_ARFR6_V1 0 +#define BIT_MASK_ARFR6_V1 0xffffffffffffffffL +#define BIT_ARFR6_V1(x) (((x) & BIT_MASK_ARFR6_V1) << BIT_SHIFT_ARFR6_V1) +#define BITS_ARFR6_V1 (BIT_MASK_ARFR6_V1 << BIT_SHIFT_ARFR6_V1) +#define BIT_CLEAR_ARFR6_V1(x) ((x) & (~BITS_ARFR6_V1)) +#define BIT_GET_ARFR6_V1(x) (((x) >> BIT_SHIFT_ARFR6_V1) & BIT_MASK_ARFR6_V1) +#define BIT_SET_ARFR6_V1(x, v) (BIT_CLEAR_ARFR6_V1(x) | BIT_ARFR6_V1(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT3_TX_NULL1_DONE_INT BIT(5) +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_MU_OFFSET (Offset 0x1400) */ +#define BIT_SHIFT_MU_SCORETABLE_OFFSET 0 +#define BIT_MASK_MU_SCORETABLE_OFFSET 0x1ff +#define BIT_MU_SCORETABLE_OFFSET(x) \ + (((x) & BIT_MASK_MU_SCORETABLE_OFFSET) \ + << BIT_SHIFT_MU_SCORETABLE_OFFSET) +#define BITS_MU_SCORETABLE_OFFSET \ + (BIT_MASK_MU_SCORETABLE_OFFSET << BIT_SHIFT_MU_SCORETABLE_OFFSET) +#define BIT_CLEAR_MU_SCORETABLE_OFFSET(x) ((x) & (~BITS_MU_SCORETABLE_OFFSET)) +#define BIT_GET_MU_SCORETABLE_OFFSET(x) \ + (((x) >> BIT_SHIFT_MU_SCORETABLE_OFFSET) & \ + BIT_MASK_MU_SCORETABLE_OFFSET) +#define BIT_SET_MU_SCORETABLE_OFFSET(x, v) \ + (BIT_CLEAR_MU_SCORETABLE_OFFSET(x) | BIT_MU_SCORETABLE_OFFSET(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_Q2_Q3_INFO (Offset 0x1404) */ -#define BIT_FS_CLI2_TX_NULL1_INT BIT(5) +#define BIT_SHIFT_AC3_PKT_INFO 16 +#define BIT_MASK_AC3_PKT_INFO 0xfff +#define BIT_AC3_PKT_INFO(x) \ + (((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO) +#define BITS_AC3_PKT_INFO (BIT_MASK_AC3_PKT_INFO << BIT_SHIFT_AC3_PKT_INFO) +#define BIT_CLEAR_AC3_PKT_INFO(x) ((x) & (~BITS_AC3_PKT_INFO)) +#define BIT_GET_AC3_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO) +#define BIT_SET_AC3_PKT_INFO(x, v) \ + (BIT_CLEAR_AC3_PKT_INFO(x) | BIT_AC3_PKT_INFO(v)) + +#define BIT_SHIFT_AC2_PKT_INFO 0 +#define BIT_MASK_AC2_PKT_INFO 0xfff +#define BIT_AC2_PKT_INFO(x) \ + (((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO) +#define BITS_AC2_PKT_INFO (BIT_MASK_AC2_PKT_INFO << BIT_SHIFT_AC2_PKT_INFO) +#define BIT_CLEAR_AC2_PKT_INFO(x) ((x) & (~BITS_AC2_PKT_INFO)) +#define BIT_GET_AC2_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO) +#define BIT_SET_AC2_PKT_INFO(x, v) \ + (BIT_CLEAR_AC2_PKT_INFO(x) | BIT_AC2_PKT_INFO(v)) -#endif +/* 2 REG_Q4_Q5_INFO (Offset 0x1408) */ +#define BIT_SHIFT_AC5_PKT_INFO 16 +#define BIT_MASK_AC5_PKT_INFO 0xfff +#define BIT_AC5_PKT_INFO(x) \ + (((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO) +#define BITS_AC5_PKT_INFO (BIT_MASK_AC5_PKT_INFO << BIT_SHIFT_AC5_PKT_INFO) +#define BIT_CLEAR_AC5_PKT_INFO(x) ((x) & (~BITS_AC5_PKT_INFO)) +#define BIT_GET_AC5_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO) +#define BIT_SET_AC5_PKT_INFO(x, v) \ + (BIT_CLEAR_AC5_PKT_INFO(x) | BIT_AC5_PKT_INFO(v)) -#if (HALMAC_8197F_SUPPORT) +#define BIT_SHIFT_AC4_PKT_INFO 0 +#define BIT_MASK_AC4_PKT_INFO 0xfff +#define BIT_AC4_PKT_INFO(x) \ + (((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO) +#define BITS_AC4_PKT_INFO (BIT_MASK_AC4_PKT_INFO << BIT_SHIFT_AC4_PKT_INFO) +#define BIT_CLEAR_AC4_PKT_INFO(x) ((x) & (~BITS_AC4_PKT_INFO)) +#define BIT_GET_AC4_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO) +#define BIT_SET_AC4_PKT_INFO(x, v) \ + (BIT_CLEAR_AC4_PKT_INFO(x) | BIT_AC4_PKT_INFO(v)) + +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_ARFR7 (Offset 0x1408) */ -#define BIT_PORT3_TX_NULL0_DONE_INT BIT(4) +#define BIT_SHIFT_ARFR7_V1 0 +#define BIT_MASK_ARFR7_V1 0xffffffffffffffffL +#define BIT_ARFR7_V1(x) (((x) & BIT_MASK_ARFR7_V1) << BIT_SHIFT_ARFR7_V1) +#define BITS_ARFR7_V1 (BIT_MASK_ARFR7_V1 << BIT_SHIFT_ARFR7_V1) +#define BIT_CLEAR_ARFR7_V1(x) ((x) & (~BITS_ARFR7_V1)) +#define BIT_GET_ARFR7_V1(x) (((x) >> BIT_SHIFT_ARFR7_V1) & BIT_MASK_ARFR7_V1) +#define BIT_SET_ARFR7_V1(x, v) (BIT_CLEAR_ARFR7_V1(x) | BIT_ARFR7_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_Q6_Q7_INFO (Offset 0x140C) */ +#define BIT_SHIFT_AC7_PKT_INFO 16 +#define BIT_MASK_AC7_PKT_INFO 0xfff +#define BIT_AC7_PKT_INFO(x) \ + (((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO) +#define BITS_AC7_PKT_INFO (BIT_MASK_AC7_PKT_INFO << BIT_SHIFT_AC7_PKT_INFO) +#define BIT_CLEAR_AC7_PKT_INFO(x) ((x) & (~BITS_AC7_PKT_INFO)) +#define BIT_GET_AC7_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO) +#define BIT_SET_AC7_PKT_INFO(x, v) \ + (BIT_CLEAR_AC7_PKT_INFO(x) | BIT_AC7_PKT_INFO(v)) + +#define BIT_SHIFT_AC6_PKT_INFO 0 +#define BIT_MASK_AC6_PKT_INFO 0xfff +#define BIT_AC6_PKT_INFO(x) \ + (((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO) +#define BITS_AC6_PKT_INFO (BIT_MASK_AC6_PKT_INFO << BIT_SHIFT_AC6_PKT_INFO) +#define BIT_CLEAR_AC6_PKT_INFO(x) ((x) & (~BITS_AC6_PKT_INFO)) +#define BIT_GET_AC6_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO) +#define BIT_SET_AC6_PKT_INFO(x, v) \ + (BIT_CLEAR_AC6_PKT_INFO(x) | BIT_AC6_PKT_INFO(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_MGQ_HIQ_INFO (Offset 0x1410) */ -#define BIT_FS_CLI2_TX_NULL0_INT BIT(4) +#define BIT_SHIFT_HIQ_PKT_INFO 16 +#define BIT_MASK_HIQ_PKT_INFO 0xfff +#define BIT_HIQ_PKT_INFO(x) \ + (((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO) +#define BITS_HIQ_PKT_INFO (BIT_MASK_HIQ_PKT_INFO << BIT_SHIFT_HIQ_PKT_INFO) +#define BIT_CLEAR_HIQ_PKT_INFO(x) ((x) & (~BITS_HIQ_PKT_INFO)) +#define BIT_GET_HIQ_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO) +#define BIT_SET_HIQ_PKT_INFO(x, v) \ + (BIT_CLEAR_HIQ_PKT_INFO(x) | BIT_HIQ_PKT_INFO(v)) + +#define BIT_SHIFT_MGQ_PKT_INFO 0 +#define BIT_MASK_MGQ_PKT_INFO 0xfff +#define BIT_MGQ_PKT_INFO(x) \ + (((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO) +#define BITS_MGQ_PKT_INFO (BIT_MASK_MGQ_PKT_INFO << BIT_SHIFT_MGQ_PKT_INFO) +#define BIT_CLEAR_MGQ_PKT_INFO(x) ((x) & (~BITS_MGQ_PKT_INFO)) +#define BIT_GET_MGQ_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO) +#define BIT_SET_MGQ_PKT_INFO(x, v) \ + (BIT_CLEAR_MGQ_PKT_INFO(x) | BIT_MGQ_PKT_INFO(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_ARFR8 (Offset 0x1410) */ + +#define BIT_SHIFT_ARFR8_V1 0 +#define BIT_MASK_ARFR8_V1 0xffffffffffffffffL +#define BIT_ARFR8_V1(x) (((x) & BIT_MASK_ARFR8_V1) << BIT_SHIFT_ARFR8_V1) +#define BITS_ARFR8_V1 (BIT_MASK_ARFR8_V1 << BIT_SHIFT_ARFR8_V1) +#define BIT_CLEAR_ARFR8_V1(x) ((x) & (~BITS_ARFR8_V1)) +#define BIT_GET_ARFR8_V1(x) (((x) >> BIT_SHIFT_ARFR8_V1) & BIT_MASK_ARFR8_V1) +#define BIT_SET_ARFR8_V1(x, v) (BIT_CLEAR_ARFR8_V1(x) | BIT_ARFR8_V1(v)) + +#define BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER 0 +#define BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER 0xff +#define BIT_MEDIUM_HAS_IDLE_TRIGGER(x) \ + (((x) & BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER) \ + << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) +#define BITS_MEDIUM_HAS_IDLE_TRIGGER \ + (BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) +#define BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x) \ + ((x) & (~BITS_MEDIUM_HAS_IDLE_TRIGGER)) +#define BIT_GET_MEDIUM_HAS_IDLE_TRIGGER(x) \ + (((x) >> BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) & \ + BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER) +#define BIT_SET_MEDIUM_HAS_IDLE_TRIGGER(x, v) \ + (BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x) | BIT_MEDIUM_HAS_IDLE_TRIGGER(v)) #endif - #if (HALMAC_8197F_SUPPORT) +/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ + +#define BIT_SHIFT_BCNQ_PKT_INFO_V1 16 +#define BIT_MASK_BCNQ_PKT_INFO_V1 0xfff +#define BIT_BCNQ_PKT_INFO_V1(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO_V1) << BIT_SHIFT_BCNQ_PKT_INFO_V1) +#define BITS_BCNQ_PKT_INFO_V1 \ + (BIT_MASK_BCNQ_PKT_INFO_V1 << BIT_SHIFT_BCNQ_PKT_INFO_V1) +#define BIT_CLEAR_BCNQ_PKT_INFO_V1(x) ((x) & (~BITS_BCNQ_PKT_INFO_V1)) +#define BIT_GET_BCNQ_PKT_INFO_V1(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1) & BIT_MASK_BCNQ_PKT_INFO_V1) +#define BIT_SET_BCNQ_PKT_INFO_V1(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO_V1(x) | BIT_BCNQ_PKT_INFO_V1(v)) + +#define BIT_SHIFT_BCNERR_PORT_SEL 16 +#define BIT_MASK_BCNERR_PORT_SEL 0x7 +#define BIT_BCNERR_PORT_SEL(x) \ + (((x) & BIT_MASK_BCNERR_PORT_SEL) << BIT_SHIFT_BCNERR_PORT_SEL) +#define BITS_BCNERR_PORT_SEL \ + (BIT_MASK_BCNERR_PORT_SEL << BIT_SHIFT_BCNERR_PORT_SEL) +#define BIT_CLEAR_BCNERR_PORT_SEL(x) ((x) & (~BITS_BCNERR_PORT_SEL)) +#define BIT_GET_BCNERR_PORT_SEL(x) \ + (((x) >> BIT_SHIFT_BCNERR_PORT_SEL) & BIT_MASK_BCNERR_PORT_SEL) +#define BIT_SET_BCNERR_PORT_SEL(x, v) \ + (BIT_CLEAR_BCNERR_PORT_SEL(x) | BIT_BCNERR_PORT_SEL(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ -#define BIT_PORT2_TX_NULL1_DONE_INT BIT(3) +#define BIT_SHIFT_CMDQ_PKT_INFO 16 +#define BIT_MASK_CMDQ_PKT_INFO 0xfff +#define BIT_CMDQ_PKT_INFO(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO) +#define BITS_CMDQ_PKT_INFO (BIT_MASK_CMDQ_PKT_INFO << BIT_SHIFT_CMDQ_PKT_INFO) +#define BIT_CLEAR_CMDQ_PKT_INFO(x) ((x) & (~BITS_CMDQ_PKT_INFO)) +#define BIT_GET_CMDQ_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO) +#define BIT_SET_CMDQ_PKT_INFO(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO(x) | BIT_CMDQ_PKT_INFO(v)) #endif +#if (HALMAC_8197F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +#define BIT_SHIFT_CMDQ_PKT_INFO_V1 0 +#define BIT_MASK_CMDQ_PKT_INFO_V1 0xfff +#define BIT_CMDQ_PKT_INFO_V1(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO_V1) << BIT_SHIFT_CMDQ_PKT_INFO_V1) +#define BITS_CMDQ_PKT_INFO_V1 \ + (BIT_MASK_CMDQ_PKT_INFO_V1 << BIT_SHIFT_CMDQ_PKT_INFO_V1) +#define BIT_CLEAR_CMDQ_PKT_INFO_V1(x) ((x) & (~BITS_CMDQ_PKT_INFO_V1)) +#define BIT_GET_CMDQ_PKT_INFO_V1(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1) & BIT_MASK_CMDQ_PKT_INFO_V1) +#define BIT_SET_CMDQ_PKT_INFO_V1(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO_V1(x) | BIT_CMDQ_PKT_INFO_V1(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_FS_CLI1_TX_NULL1_INT BIT(3) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +#define BIT_SHIFT_BCNQ_PKT_INFO 0 +#define BIT_MASK_BCNQ_PKT_INFO 0xfff +#define BIT_BCNQ_PKT_INFO(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO) +#define BITS_BCNQ_PKT_INFO (BIT_MASK_BCNQ_PKT_INFO << BIT_SHIFT_BCNQ_PKT_INFO) +#define BIT_CLEAR_BCNQ_PKT_INFO(x) ((x) & (~BITS_BCNQ_PKT_INFO)) +#define BIT_GET_BCNQ_PKT_INFO(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO) +#define BIT_SET_BCNQ_PKT_INFO(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO(x) | BIT_BCNQ_PKT_INFO(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_LOOPBACK_OPTION (Offset 0x1420) */ -#define BIT_PORT2_TX_NULL0_DONE_INT BIT(2) +#define BIT_LOOPACK_FAST_EDCA_EN BIT(24) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_USEREG_SETTING (Offset 0x1420) */ +#define BIT_NDPA_USEREG BIT(21) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#define BIT_SHIFT_RETRY_USEREG 19 +#define BIT_MASK_RETRY_USEREG 0x3 +#define BIT_RETRY_USEREG(x) \ + (((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG) +#define BITS_RETRY_USEREG (BIT_MASK_RETRY_USEREG << BIT_SHIFT_RETRY_USEREG) +#define BIT_CLEAR_RETRY_USEREG(x) ((x) & (~BITS_RETRY_USEREG)) +#define BIT_GET_RETRY_USEREG(x) \ + (((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG) +#define BIT_SET_RETRY_USEREG(x, v) \ + (BIT_CLEAR_RETRY_USEREG(x) | BIT_RETRY_USEREG(v)) -#define BIT_FS_CLI1_TX_NULL0_INT BIT(2) +#define BIT_SHIFT_TRYPKT_USEREG 17 +#define BIT_MASK_TRYPKT_USEREG 0x3 +#define BIT_TRYPKT_USEREG(x) \ + (((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG) +#define BITS_TRYPKT_USEREG (BIT_MASK_TRYPKT_USEREG << BIT_SHIFT_TRYPKT_USEREG) +#define BIT_CLEAR_TRYPKT_USEREG(x) ((x) & (~BITS_TRYPKT_USEREG)) +#define BIT_GET_TRYPKT_USEREG(x) \ + (((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG) +#define BIT_SET_TRYPKT_USEREG(x, v) \ + (BIT_CLEAR_TRYPKT_USEREG(x) | BIT_TRYPKT_USEREG(v)) + +#define BIT_CTLPKT_USEREG BIT(16) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_AESIV_SETTING (Offset 0x1424) */ +#define BIT_SHIFT_AESIV_OFFSET 0 +#define BIT_MASK_AESIV_OFFSET 0xfff +#define BIT_AESIV_OFFSET(x) \ + (((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET) +#define BITS_AESIV_OFFSET (BIT_MASK_AESIV_OFFSET << BIT_SHIFT_AESIV_OFFSET) +#define BIT_CLEAR_AESIV_OFFSET(x) ((x) & (~BITS_AESIV_OFFSET)) +#define BIT_GET_AESIV_OFFSET(x) \ + (((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET) +#define BIT_SET_AESIV_OFFSET(x, v) \ + (BIT_CLEAR_AESIV_OFFSET(x) | BIT_AESIV_OFFSET(v)) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT1_TX_NULL1_DONE_INT BIT(1) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_BF0_TIME_SETTING (Offset 0x1428) */ +#define BIT_BF0_TIMER_SET BIT(31) +#define BIT_BF0_TIMER_CLR BIT(30) +#define BIT_BF0_UPDATE_EN BIT(29) +#define BIT_BF0_TIMER_EN BIT(28) + +#define BIT_SHIFT_BF0_PRETIME_OVER 16 +#define BIT_MASK_BF0_PRETIME_OVER 0xfff +#define BIT_BF0_PRETIME_OVER(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER) +#define BITS_BF0_PRETIME_OVER \ + (BIT_MASK_BF0_PRETIME_OVER << BIT_SHIFT_BF0_PRETIME_OVER) +#define BIT_CLEAR_BF0_PRETIME_OVER(x) ((x) & (~BITS_BF0_PRETIME_OVER)) +#define BIT_GET_BF0_PRETIME_OVER(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER) +#define BIT_SET_BF0_PRETIME_OVER(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER(x) | BIT_BF0_PRETIME_OVER(v)) + +#define BIT_SHIFT_BF0_LIFETIME 0 +#define BIT_MASK_BF0_LIFETIME 0xffff +#define BIT_BF0_LIFETIME(x) \ + (((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME) +#define BITS_BF0_LIFETIME (BIT_MASK_BF0_LIFETIME << BIT_SHIFT_BF0_LIFETIME) +#define BIT_CLEAR_BF0_LIFETIME(x) ((x) & (~BITS_BF0_LIFETIME)) +#define BIT_GET_BF0_LIFETIME(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME) +#define BIT_SET_BF0_LIFETIME(x, v) \ + (BIT_CLEAR_BF0_LIFETIME(x) | BIT_BF0_LIFETIME(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_BF1_TIME_SETTING (Offset 0x142C) */ +#define BIT_BF1_TIMER_SET BIT(31) +#define BIT_BF1_TIMER_CLR BIT(30) +#define BIT_BF1_UPDATE_EN BIT(29) +#define BIT_BF1_TIMER_EN BIT(28) + +#define BIT_SHIFT_BF1_PRETIME_OVER 16 +#define BIT_MASK_BF1_PRETIME_OVER 0xfff +#define BIT_BF1_PRETIME_OVER(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER) +#define BITS_BF1_PRETIME_OVER \ + (BIT_MASK_BF1_PRETIME_OVER << BIT_SHIFT_BF1_PRETIME_OVER) +#define BIT_CLEAR_BF1_PRETIME_OVER(x) ((x) & (~BITS_BF1_PRETIME_OVER)) +#define BIT_GET_BF1_PRETIME_OVER(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER) +#define BIT_SET_BF1_PRETIME_OVER(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER(x) | BIT_BF1_PRETIME_OVER(v)) + +#define BIT_SHIFT_BF1_LIFETIME 0 +#define BIT_MASK_BF1_LIFETIME 0xffff +#define BIT_BF1_LIFETIME(x) \ + (((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME) +#define BITS_BF1_LIFETIME (BIT_MASK_BF1_LIFETIME << BIT_SHIFT_BF1_LIFETIME) +#define BIT_CLEAR_BF1_LIFETIME(x) ((x) & (~BITS_BF1_LIFETIME)) +#define BIT_GET_BF1_LIFETIME(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME) +#define BIT_SET_BF1_LIFETIME(x, v) \ + (BIT_CLEAR_BF1_LIFETIME(x) | BIT_BF1_LIFETIME(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_BF_TIMEOUT_EN (Offset 0x1430) */ -#define BIT_FS_CLI0_TX_NULL1_INT BIT(1) +#define BIT_EN_VHT_LDPC BIT(9) +#define BIT_EN_HT_LDPC BIT(8) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_BF_TIMEOUT_EN (Offset 0x1430) */ +#define BIT_BF1_TIMEOUT_EN BIT(1) +#define BIT_BF0_TIMEOUT_EN BIT(0) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +#endif -#define BIT_PORT1_TX_NULL0_DONE_INT BIT(0) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#endif +/* 2 REG_MACID_RELEASE0 (Offset 0x1434) */ +#define BIT_SHIFT_MACID31_0_RELEASE 0 +#define BIT_MASK_MACID31_0_RELEASE 0xffffffffL +#define BIT_MACID31_0_RELEASE(x) \ + (((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE) +#define BITS_MACID31_0_RELEASE \ + (BIT_MASK_MACID31_0_RELEASE << BIT_SHIFT_MACID31_0_RELEASE) +#define BIT_CLEAR_MACID31_0_RELEASE(x) ((x) & (~BITS_MACID31_0_RELEASE)) +#define BIT_GET_MACID31_0_RELEASE(x) \ + (((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE) +#define BIT_SET_MACID31_0_RELEASE(x, v) \ + (BIT_CLEAR_MACID31_0_RELEASE(x) | BIT_MACID31_0_RELEASE(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FT2ISR (Offset 0x11E4) */ +/* 2 REG_MACID_RELEASE_INFO (Offset 0x1434) */ -#define BIT_FS_CLI0_TX_NULL0_INT BIT(0) +#define BIT_SHIFT_MACID_RELEASE_INFO 0 +#define BIT_MASK_MACID_RELEASE_INFO 0xffffffffL +#define BIT_MACID_RELEASE_INFO(x) \ + (((x) & BIT_MASK_MACID_RELEASE_INFO) << BIT_SHIFT_MACID_RELEASE_INFO) +#define BITS_MACID_RELEASE_INFO \ + (BIT_MASK_MACID_RELEASE_INFO << BIT_SHIFT_MACID_RELEASE_INFO) +#define BIT_CLEAR_MACID_RELEASE_INFO(x) ((x) & (~BITS_MACID_RELEASE_INFO)) +#define BIT_GET_MACID_RELEASE_INFO(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_INFO) & BIT_MASK_MACID_RELEASE_INFO) +#define BIT_SET_MACID_RELEASE_INFO(x, v) \ + (BIT_CLEAR_MACID_RELEASE_INFO(x) | BIT_MACID_RELEASE_INFO(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_MACID_RELEASE1 (Offset 0x1438) */ -/* 2 REG_MSG2 (Offset 0x11F0) */ +#define BIT_SHIFT_MACID63_32_RELEASE 0 +#define BIT_MASK_MACID63_32_RELEASE 0xffffffffL +#define BIT_MACID63_32_RELEASE(x) \ + (((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE) +#define BITS_MACID63_32_RELEASE \ + (BIT_MASK_MACID63_32_RELEASE << BIT_SHIFT_MACID63_32_RELEASE) +#define BIT_CLEAR_MACID63_32_RELEASE(x) ((x) & (~BITS_MACID63_32_RELEASE)) +#define BIT_GET_MACID63_32_RELEASE(x) \ + (((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE) +#define BIT_SET_MACID63_32_RELEASE(x, v) \ + (BIT_CLEAR_MACID63_32_RELEASE(x) | BIT_MACID63_32_RELEASE(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_MACID_RELEASE_SUCCESS_INFO (Offset 0x1438) */ + +#define BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO 0 +#define BIT_MASK_MACID_RELEASE_SUCCESS_INFO 0xffffffffL +#define BIT_MACID_RELEASE_SUCCESS_INFO(x) \ + (((x) & BIT_MASK_MACID_RELEASE_SUCCESS_INFO) \ + << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) +#define BITS_MACID_RELEASE_SUCCESS_INFO \ + (BIT_MASK_MACID_RELEASE_SUCCESS_INFO \ + << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) +#define BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x) \ + ((x) & (~BITS_MACID_RELEASE_SUCCESS_INFO)) +#define BIT_GET_MACID_RELEASE_SUCCESS_INFO(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) & \ + BIT_MASK_MACID_RELEASE_SUCCESS_INFO) +#define BIT_SET_MACID_RELEASE_SUCCESS_INFO(x, v) \ + (BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x) | \ + BIT_MACID_RELEASE_SUCCESS_INFO(v)) + +/* 2 REG_MACID_RELEASE_CTRL (Offset 0x143C) */ + +#define BIT_SHIFT_MACID_RELEASE_SEL 24 +#define BIT_MASK_MACID_RELEASE_SEL 0x7 +#define BIT_MACID_RELEASE_SEL(x) \ + (((x) & BIT_MASK_MACID_RELEASE_SEL) << BIT_SHIFT_MACID_RELEASE_SEL) +#define BITS_MACID_RELEASE_SEL \ + (BIT_MASK_MACID_RELEASE_SEL << BIT_SHIFT_MACID_RELEASE_SEL) +#define BIT_CLEAR_MACID_RELEASE_SEL(x) ((x) & (~BITS_MACID_RELEASE_SEL)) +#define BIT_GET_MACID_RELEASE_SEL(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_SEL) & BIT_MASK_MACID_RELEASE_SEL) +#define BIT_SET_MACID_RELEASE_SEL(x, v) \ + (BIT_CLEAR_MACID_RELEASE_SEL(x) | BIT_MACID_RELEASE_SEL(v)) + +#define BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET 16 +#define BIT_MASK_MACID_RELEASE_CLEAR_OFFSET 0xff +#define BIT_MACID_RELEASE_CLEAR_OFFSET(x) \ + (((x) & BIT_MASK_MACID_RELEASE_CLEAR_OFFSET) \ + << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) +#define BITS_MACID_RELEASE_CLEAR_OFFSET \ + (BIT_MASK_MACID_RELEASE_CLEAR_OFFSET \ + << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) +#define BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x) \ + ((x) & (~BITS_MACID_RELEASE_CLEAR_OFFSET)) +#define BIT_GET_MACID_RELEASE_CLEAR_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) & \ + BIT_MASK_MACID_RELEASE_CLEAR_OFFSET) +#define BIT_SET_MACID_RELEASE_CLEAR_OFFSET(x, v) \ + (BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x) | \ + BIT_MACID_RELEASE_CLEAR_OFFSET(v)) + +#define BIT_MACID_RELEASE_VALUE BIT(8) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_MACID_RELEASE2 (Offset 0x143C) */ -#define BIT_SHIFT_FW_MSG2 0 -#define BIT_MASK_FW_MSG2 0xffffffffL -#define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2) -#define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2) +#define BIT_SHIFT_MACID95_64_RELEASE 0 +#define BIT_MASK_MACID95_64_RELEASE 0xffffffffL +#define BIT_MACID95_64_RELEASE(x) \ + (((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE) +#define BITS_MACID95_64_RELEASE \ + (BIT_MASK_MACID95_64_RELEASE << BIT_SHIFT_MACID95_64_RELEASE) +#define BIT_CLEAR_MACID95_64_RELEASE(x) ((x) & (~BITS_MACID95_64_RELEASE)) +#define BIT_GET_MACID95_64_RELEASE(x) \ + (((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE) +#define BIT_SET_MACID95_64_RELEASE(x, v) \ + (BIT_CLEAR_MACID95_64_RELEASE(x) | BIT_MACID95_64_RELEASE(v)) +#endif -/* 2 REG_MSG3 (Offset 0x11F4) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_MACID_RELEASE_CTRL (Offset 0x143C) */ -#define BIT_SHIFT_FW_MSG3 0 -#define BIT_MASK_FW_MSG3 0xffffffffL -#define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3) -#define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3) +#define BIT_SHIFT_MACID_RELEASE_OFFSET 0 +#define BIT_MASK_MACID_RELEASE_OFFSET 0xff +#define BIT_MACID_RELEASE_OFFSET(x) \ + (((x) & BIT_MASK_MACID_RELEASE_OFFSET) \ + << BIT_SHIFT_MACID_RELEASE_OFFSET) +#define BITS_MACID_RELEASE_OFFSET \ + (BIT_MASK_MACID_RELEASE_OFFSET << BIT_SHIFT_MACID_RELEASE_OFFSET) +#define BIT_CLEAR_MACID_RELEASE_OFFSET(x) ((x) & (~BITS_MACID_RELEASE_OFFSET)) +#define BIT_GET_MACID_RELEASE_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_OFFSET) & \ + BIT_MASK_MACID_RELEASE_OFFSET) +#define BIT_SET_MACID_RELEASE_OFFSET(x, v) \ + (BIT_CLEAR_MACID_RELEASE_OFFSET(x) | BIT_MACID_RELEASE_OFFSET(v)) +#endif -/* 2 REG_MSG4 (Offset 0x11F8) */ +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_MACID_RELEASE3 (Offset 0x1440) */ -#define BIT_SHIFT_FW_MSG4 0 -#define BIT_MASK_FW_MSG4 0xffffffffL -#define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4) -#define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4) +#define BIT_SHIFT_MACID127_96_RELEASE 0 +#define BIT_MASK_MACID127_96_RELEASE 0xffffffffL +#define BIT_MACID127_96_RELEASE(x) \ + (((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE) +#define BITS_MACID127_96_RELEASE \ + (BIT_MASK_MACID127_96_RELEASE << BIT_SHIFT_MACID127_96_RELEASE) +#define BIT_CLEAR_MACID127_96_RELEASE(x) ((x) & (~BITS_MACID127_96_RELEASE)) +#define BIT_GET_MACID127_96_RELEASE(x) \ + (((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE) +#define BIT_SET_MACID127_96_RELEASE(x, v) \ + (BIT_CLEAR_MACID127_96_RELEASE(x) | BIT_MACID127_96_RELEASE(v)) +/* 2 REG_MACID_RELEASE_SETTING (Offset 0x1444) */ -/* 2 REG_MSG5 (Offset 0x11FC) */ +#define BIT_MACID_VALUE BIT(7) +#define BIT_SHIFT_MACID_OFFSET 0 +#define BIT_MASK_MACID_OFFSET 0x7f +#define BIT_MACID_OFFSET(x) \ + (((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET) +#define BITS_MACID_OFFSET (BIT_MASK_MACID_OFFSET << BIT_SHIFT_MACID_OFFSET) +#define BIT_CLEAR_MACID_OFFSET(x) ((x) & (~BITS_MACID_OFFSET)) +#define BIT_GET_MACID_OFFSET(x) \ + (((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET) +#define BIT_SET_MACID_OFFSET(x, v) \ + (BIT_CLEAR_MACID_OFFSET(x) | BIT_MACID_OFFSET(v)) -#define BIT_SHIFT_FW_MSG5 0 -#define BIT_MASK_FW_MSG5 0xffffffffL -#define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5) -#define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_DDMA_CH0SA (Offset 0x1200) */ +/* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */ +#define BIT_SHIFT_VI_FAST_EDCA_TO 24 +#define BIT_MASK_VI_FAST_EDCA_TO 0xff +#define BIT_VI_FAST_EDCA_TO(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO) +#define BITS_VI_FAST_EDCA_TO \ + (BIT_MASK_VI_FAST_EDCA_TO << BIT_SHIFT_VI_FAST_EDCA_TO) +#define BIT_CLEAR_VI_FAST_EDCA_TO(x) ((x) & (~BITS_VI_FAST_EDCA_TO)) +#define BIT_GET_VI_FAST_EDCA_TO(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO) +#define BIT_SET_VI_FAST_EDCA_TO(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO(x) | BIT_VI_FAST_EDCA_TO(v)) + +#define BIT_VI_THRESHOLD_SEL BIT(23) + +#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16 +#define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f +#define BIT_VI_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH) +#define BITS_VI_FAST_EDCA_PKT_TH \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH << BIT_SHIFT_VI_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VI_FAST_EDCA_PKT_TH)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH) +#define BIT_SET_VI_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) | BIT_VI_FAST_EDCA_PKT_TH(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DDMACH0_SA 0 -#define BIT_MASK_DDMACH0_SA 0xffffffffL -#define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA) -#define BIT_GET_DDMACH0_SA(x) (((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA) +/* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */ +#define BIT_SHIFT_VO_FAST_EDCA_TO 8 +#define BIT_MASK_VO_FAST_EDCA_TO 0xff +#define BIT_VO_FAST_EDCA_TO(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO) +#define BITS_VO_FAST_EDCA_TO \ + (BIT_MASK_VO_FAST_EDCA_TO << BIT_SHIFT_VO_FAST_EDCA_TO) +#define BIT_CLEAR_VO_FAST_EDCA_TO(x) ((x) & (~BITS_VO_FAST_EDCA_TO)) +#define BIT_GET_VO_FAST_EDCA_TO(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO) +#define BIT_SET_VO_FAST_EDCA_TO(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO(x) | BIT_VO_FAST_EDCA_TO(v)) -/* 2 REG_DDMA_CH0DA (Offset 0x1204) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DDMACH0_DA 0 -#define BIT_MASK_DDMACH0_DA 0xffffffffL -#define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA) -#define BIT_GET_DDMACH0_DA(x) (((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA) +/* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */ +#define BIT_VO_THRESHOLD_SEL BIT(7) -/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ +#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0 +#define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f +#define BIT_VO_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH) +#define BITS_VO_FAST_EDCA_PKT_TH \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH << BIT_SHIFT_VO_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VO_FAST_EDCA_PKT_TH)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH) +#define BIT_SET_VO_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) | BIT_VO_FAST_EDCA_PKT_TH(v)) -#define BIT_DDMACH0_OWN BIT(31) -#define BIT_DDMACH0_CHKSUM_EN BIT(29) -#define BIT_DDMACH0_DA_W_DISABLE BIT(28) -#define BIT_DDMACH0_CHKSUM_STS BIT(27) -#define BIT_DDMACH0_DDMA_MODE BIT(26) -#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH0_CHKSUM_CONT BIT(24) +/* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */ -#define BIT_SHIFT_DDMACH0_DLEN 0 -#define BIT_MASK_DDMACH0_DLEN 0x3ffff -#define BIT_DDMACH0_DLEN(x) (((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN) -#define BIT_GET_DDMACH0_DLEN(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN) +#define BIT_SHIFT_BK_FAST_EDCA_TO 24 +#define BIT_MASK_BK_FAST_EDCA_TO 0xff +#define BIT_BK_FAST_EDCA_TO(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO) +#define BITS_BK_FAST_EDCA_TO \ + (BIT_MASK_BK_FAST_EDCA_TO << BIT_SHIFT_BK_FAST_EDCA_TO) +#define BIT_CLEAR_BK_FAST_EDCA_TO(x) ((x) & (~BITS_BK_FAST_EDCA_TO)) +#define BIT_GET_BK_FAST_EDCA_TO(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO) +#define BIT_SET_BK_FAST_EDCA_TO(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO(x) | BIT_BK_FAST_EDCA_TO(v)) + +#define BIT_BK_THRESHOLD_SEL BIT(23) + +#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16 +#define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f +#define BIT_BK_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH) +#define BITS_BK_FAST_EDCA_PKT_TH \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH << BIT_SHIFT_BK_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BK_FAST_EDCA_PKT_TH)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH) +#define BIT_SET_BK_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) | BIT_BK_FAST_EDCA_PKT_TH(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */ -/* 2 REG_DDMA_CH1SA (Offset 0x1210) */ +#define BIT_SHIFT_BE_FAST_EDCA_TO 8 +#define BIT_MASK_BE_FAST_EDCA_TO 0xff +#define BIT_BE_FAST_EDCA_TO(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO) +#define BITS_BE_FAST_EDCA_TO \ + (BIT_MASK_BE_FAST_EDCA_TO << BIT_SHIFT_BE_FAST_EDCA_TO) +#define BIT_CLEAR_BE_FAST_EDCA_TO(x) ((x) & (~BITS_BE_FAST_EDCA_TO)) +#define BIT_GET_BE_FAST_EDCA_TO(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO) +#define BIT_SET_BE_FAST_EDCA_TO(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO(x) | BIT_BE_FAST_EDCA_TO(v)) +#endif -#define BIT_SHIFT_DDMACH1_SA 0 -#define BIT_MASK_DDMACH1_SA 0xffffffffL -#define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA) -#define BIT_GET_DDMACH1_SA(x) (((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA) +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */ -/* 2 REG_DDMA_CH1DA (Offset 0x1214) */ +#define BIT_BE_THRESHOLD_SEL BIT(7) +#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0 +#define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f +#define BIT_BE_FAST_EDCA_PKT_TH(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH) +#define BITS_BE_FAST_EDCA_PKT_TH \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH << BIT_SHIFT_BE_FAST_EDCA_PKT_TH) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BE_FAST_EDCA_PKT_TH)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH) +#define BIT_SET_BE_FAST_EDCA_PKT_TH(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) | BIT_BE_FAST_EDCA_PKT_TH(v)) -#define BIT_SHIFT_DDMACH1_DA 0 -#define BIT_MASK_DDMACH1_DA 0xffffffffL -#define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA) -#define BIT_GET_DDMACH1_DA(x) (((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ +/* 2 REG_MACID_DROP0 (Offset 0x1450) */ -#define BIT_DDMACH1_OWN BIT(31) -#define BIT_DDMACH1_CHKSUM_EN BIT(29) -#define BIT_DDMACH1_DA_W_DISABLE BIT(28) -#define BIT_DDMACH1_CHKSUM_STS BIT(27) -#define BIT_DDMACH1_DDMA_MODE BIT(26) -#define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH1_CHKSUM_CONT BIT(24) +#define BIT_SHIFT_MACID31_0_DROP 0 +#define BIT_MASK_MACID31_0_DROP 0xffffffffL +#define BIT_MACID31_0_DROP(x) \ + (((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP) +#define BITS_MACID31_0_DROP \ + (BIT_MASK_MACID31_0_DROP << BIT_SHIFT_MACID31_0_DROP) +#define BIT_CLEAR_MACID31_0_DROP(x) ((x) & (~BITS_MACID31_0_DROP)) +#define BIT_GET_MACID31_0_DROP(x) \ + (((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP) +#define BIT_SET_MACID31_0_DROP(x, v) \ + (BIT_CLEAR_MACID31_0_DROP(x) | BIT_MACID31_0_DROP(v)) -#define BIT_SHIFT_DDMACH1_DLEN 0 -#define BIT_MASK_DDMACH1_DLEN 0x3ffff -#define BIT_DDMACH1_DLEN(x) (((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN) -#define BIT_GET_DDMACH1_DLEN(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_DDMA_CH2SA (Offset 0x1220) */ +/* 2 REG_MACID_DROP_INFO (Offset 0x1450) */ +#define BIT_SHIFT_MACID_DROP_INFO 0 +#define BIT_MASK_MACID_DROP_INFO 0xffffffffL +#define BIT_MACID_DROP_INFO(x) \ + (((x) & BIT_MASK_MACID_DROP_INFO) << BIT_SHIFT_MACID_DROP_INFO) +#define BITS_MACID_DROP_INFO \ + (BIT_MASK_MACID_DROP_INFO << BIT_SHIFT_MACID_DROP_INFO) +#define BIT_CLEAR_MACID_DROP_INFO(x) ((x) & (~BITS_MACID_DROP_INFO)) +#define BIT_GET_MACID_DROP_INFO(x) \ + (((x) >> BIT_SHIFT_MACID_DROP_INFO) & BIT_MASK_MACID_DROP_INFO) +#define BIT_SET_MACID_DROP_INFO(x, v) \ + (BIT_CLEAR_MACID_DROP_INFO(x) | BIT_MACID_DROP_INFO(v)) -#define BIT_SHIFT_DDMACH2_SA 0 -#define BIT_MASK_DDMACH2_SA 0xffffffffL -#define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA) -#define BIT_GET_DDMACH2_SA(x) (((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DDMA_CH2DA (Offset 0x1224) */ +/* 2 REG_MACID_DROP1 (Offset 0x1454) */ +#define BIT_SHIFT_MACID63_32_DROP 0 +#define BIT_MASK_MACID63_32_DROP 0xffffffffL +#define BIT_MACID63_32_DROP(x) \ + (((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP) +#define BITS_MACID63_32_DROP \ + (BIT_MASK_MACID63_32_DROP << BIT_SHIFT_MACID63_32_DROP) +#define BIT_CLEAR_MACID63_32_DROP(x) ((x) & (~BITS_MACID63_32_DROP)) +#define BIT_GET_MACID63_32_DROP(x) \ + (((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP) +#define BIT_SET_MACID63_32_DROP(x, v) \ + (BIT_CLEAR_MACID63_32_DROP(x) | BIT_MACID63_32_DROP(v)) -#define BIT_SHIFT_DDMACH2_DA 0 -#define BIT_MASK_DDMACH2_DA 0xffffffffL -#define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA) -#define BIT_GET_DDMACH2_DA(x) (((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ +/* 2 REG_MACID_DROP_CTRL (Offset 0x1454) */ -#define BIT_DDMACH2_OWN BIT(31) -#define BIT_DDMACH2_CHKSUM_EN BIT(29) -#define BIT_DDMACH2_DA_W_DISABLE BIT(28) -#define BIT_DDMACH2_CHKSUM_STS BIT(27) -#define BIT_DDMACH2_DDMA_MODE BIT(26) -#define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH2_CHKSUM_CONT BIT(24) +#define BIT_SHIFT_MACID_DROP_SEL 0 +#define BIT_MASK_MACID_DROP_SEL 0x7 +#define BIT_MACID_DROP_SEL(x) \ + (((x) & BIT_MASK_MACID_DROP_SEL) << BIT_SHIFT_MACID_DROP_SEL) +#define BITS_MACID_DROP_SEL \ + (BIT_MASK_MACID_DROP_SEL << BIT_SHIFT_MACID_DROP_SEL) +#define BIT_CLEAR_MACID_DROP_SEL(x) ((x) & (~BITS_MACID_DROP_SEL)) +#define BIT_GET_MACID_DROP_SEL(x) \ + (((x) >> BIT_SHIFT_MACID_DROP_SEL) & BIT_MASK_MACID_DROP_SEL) +#define BIT_SET_MACID_DROP_SEL(x, v) \ + (BIT_CLEAR_MACID_DROP_SEL(x) | BIT_MACID_DROP_SEL(v)) -#define BIT_SHIFT_DDMACH2_DLEN 0 -#define BIT_MASK_DDMACH2_DLEN 0x3ffff -#define BIT_DDMACH2_DLEN(x) (((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN) -#define BIT_GET_DDMACH2_DLEN(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DDMA_CH3SA (Offset 0x1230) */ +/* 2 REG_MACID_DROP2 (Offset 0x1458) */ +#define BIT_SHIFT_MACID95_64_DROP 0 +#define BIT_MASK_MACID95_64_DROP 0xffffffffL +#define BIT_MACID95_64_DROP(x) \ + (((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP) +#define BITS_MACID95_64_DROP \ + (BIT_MASK_MACID95_64_DROP << BIT_SHIFT_MACID95_64_DROP) +#define BIT_CLEAR_MACID95_64_DROP(x) ((x) & (~BITS_MACID95_64_DROP)) +#define BIT_GET_MACID95_64_DROP(x) \ + (((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP) +#define BIT_SET_MACID95_64_DROP(x, v) \ + (BIT_CLEAR_MACID95_64_DROP(x) | BIT_MACID95_64_DROP(v)) -#define BIT_SHIFT_DDMACH3_SA 0 -#define BIT_MASK_DDMACH3_SA 0xffffffffL -#define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA) -#define BIT_GET_DDMACH3_SA(x) (((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA) +/* 2 REG_MACID_DROP3 (Offset 0x145C) */ +#define BIT_SHIFT_MACID127_96_DROP 0 +#define BIT_MASK_MACID127_96_DROP 0xffffffffL +#define BIT_MACID127_96_DROP(x) \ + (((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP) +#define BITS_MACID127_96_DROP \ + (BIT_MASK_MACID127_96_DROP << BIT_SHIFT_MACID127_96_DROP) +#define BIT_CLEAR_MACID127_96_DROP(x) ((x) & (~BITS_MACID127_96_DROP)) +#define BIT_GET_MACID127_96_DROP(x) \ + (((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP) +#define BIT_SET_MACID127_96_DROP(x, v) \ + (BIT_CLEAR_MACID127_96_DROP(x) | BIT_MACID127_96_DROP(v)) -/* 2 REG_DDMA_CH3DA (Offset 0x1234) */ +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DDMACH3_DA 0 -#define BIT_MASK_DDMACH3_DA 0xffffffffL -#define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA) -#define BIT_GET_DDMACH3_DA(x) (((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA) +/* 2 REG_R_MACID_RELEASE_SUCCESS_1 (Offset 0x1464) */ +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_1(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) +#define BITS_R_MACID_RELEASE_SUCCESS_1 \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_1 \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_1) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_1(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_1(v)) -/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ +/* 2 REG_R_MACID_RELEASE_SUCCESS_3 (Offset 0x146C) */ -#define BIT_DDMACH3_OWN BIT(31) -#define BIT_DDMACH3_CHKSUM_EN BIT(29) -#define BIT_DDMACH3_DA_W_DISABLE BIT(28) -#define BIT_DDMACH3_CHKSUM_STS BIT(27) -#define BIT_DDMACH3_DDMA_MODE BIT(26) -#define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH3_CHKSUM_CONT BIT(24) +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_3(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) +#define BITS_R_MACID_RELEASE_SUCCESS_3 \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_3 \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_3) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_3(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_3(v)) -#define BIT_SHIFT_DDMACH3_DLEN 0 -#define BIT_MASK_DDMACH3_DLEN 0x3ffff -#define BIT_DDMACH3_DLEN(x) (((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN) -#define BIT_GET_DDMACH3_DLEN(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_DDMA_CH4SA (Offset 0x1240) */ +/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ +#define BIT_R_MGG_FIFO_EN BIT(31) + +#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28 +#define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7 +#define BIT_R_MGG_FIFO_PG_SIZE(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE) +#define BITS_R_MGG_FIFO_PG_SIZE \ + (BIT_MASK_R_MGG_FIFO_PG_SIZE << BIT_SHIFT_R_MGG_FIFO_PG_SIZE) +#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_PG_SIZE)) +#define BIT_GET_R_MGG_FIFO_PG_SIZE(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE) +#define BIT_SET_R_MGG_FIFO_PG_SIZE(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) | BIT_R_MGG_FIFO_PG_SIZE(v)) + +#define BIT_SHIFT_R_MGG_FIFO_START_PG 16 +#define BIT_MASK_R_MGG_FIFO_START_PG 0xfff +#define BIT_R_MGG_FIFO_START_PG(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG) +#define BITS_R_MGG_FIFO_START_PG \ + (BIT_MASK_R_MGG_FIFO_START_PG << BIT_SHIFT_R_MGG_FIFO_START_PG) +#define BIT_CLEAR_R_MGG_FIFO_START_PG(x) ((x) & (~BITS_R_MGG_FIFO_START_PG)) +#define BIT_GET_R_MGG_FIFO_START_PG(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG) +#define BIT_SET_R_MGG_FIFO_START_PG(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_START_PG(x) | BIT_R_MGG_FIFO_START_PG(v)) + +#define BIT_SHIFT_R_MGG_FIFO_SIZE 14 +#define BIT_MASK_R_MGG_FIFO_SIZE 0x3 +#define BIT_R_MGG_FIFO_SIZE(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE) +#define BITS_R_MGG_FIFO_SIZE \ + (BIT_MASK_R_MGG_FIFO_SIZE << BIT_SHIFT_R_MGG_FIFO_SIZE) +#define BIT_CLEAR_R_MGG_FIFO_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_SIZE)) +#define BIT_GET_R_MGG_FIFO_SIZE(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE) +#define BIT_SET_R_MGG_FIFO_SIZE(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_SIZE(x) | BIT_R_MGG_FIFO_SIZE(v)) + +#define BIT_R_MGG_FIFO_PAUSE BIT(13) + +#define BIT_SHIFT_R_MGG_FIFO_RPTR 8 +#define BIT_MASK_R_MGG_FIFO_RPTR 0x1f +#define BIT_R_MGG_FIFO_RPTR(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR) +#define BITS_R_MGG_FIFO_RPTR \ + (BIT_MASK_R_MGG_FIFO_RPTR << BIT_SHIFT_R_MGG_FIFO_RPTR) +#define BIT_CLEAR_R_MGG_FIFO_RPTR(x) ((x) & (~BITS_R_MGG_FIFO_RPTR)) +#define BIT_GET_R_MGG_FIFO_RPTR(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR) +#define BIT_SET_R_MGG_FIFO_RPTR(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_RPTR(x) | BIT_R_MGG_FIFO_RPTR(v)) + +#define BIT_R_MGG_FIFO_OV BIT(7) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ + +#define BIT_MGQ_FIFO_OV BIT(7) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_DDMACH4_SA 0 -#define BIT_MASK_DDMACH4_SA 0xffffffffL -#define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA) -#define BIT_GET_DDMACH4_SA(x) (((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA) +/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ +#define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6) -/* 2 REG_DDMA_CH4DA (Offset 0x1244) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DDMACH4_DA 0 -#define BIT_MASK_DDMACH4_DA 0xffffffffL -#define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA) -#define BIT_GET_DDMACH4_DA(x) (((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA) +/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ +#define BIT_MGQ_FIFO_WPTR_ERROR BIT(6) -/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ +#endif -#define BIT_DDMACH4_OWN BIT(31) -#define BIT_DDMACH4_CHKSUM_EN BIT(29) -#define BIT_DDMACH4_DA_W_DISABLE BIT(28) -#define BIT_DDMACH4_CHKSUM_STS BIT(27) -#define BIT_DDMACH4_DDMA_MODE BIT(26) -#define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH4_CHKSUM_CONT BIT(24) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_DDMACH4_DLEN 0 -#define BIT_MASK_DDMACH4_DLEN 0x3ffff -#define BIT_DDMACH4_DLEN(x) (((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN) -#define BIT_GET_DDMACH4_DLEN(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN) +/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ +#define BIT_R_EN_CPU_LIFETIME BIT(5) -/* 2 REG_DDMA_CH5SA (Offset 0x1250) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_DDMACH5_SA 0 -#define BIT_MASK_DDMACH5_SA 0xffffffffL -#define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA) -#define BIT_GET_DDMACH5_SA(x) (((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA) +/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ +#define BIT_EN_MGQ_FIFO_LIFETIME BIT(5) -/* 2 REG_DDMA_CH5DA (Offset 0x1254) */ +#endif -#define BIT_DDMACH5_OWN BIT(31) -#define BIT_DDMACH5_CHKSUM_EN BIT(29) -#define BIT_DDMACH5_DA_W_DISABLE BIT(28) -#define BIT_DDMACH5_CHKSUM_STS BIT(27) -#define BIT_DDMACH5_DDMA_MODE BIT(26) -#define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25) -#define BIT_DDMACH5_CHKSUM_CONT BIT(24) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_DDMACH5_DA 0 -#define BIT_MASK_DDMACH5_DA 0xffffffffL -#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA) -#define BIT_GET_DDMACH5_DA(x) (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA) +/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ +#define BIT_SHIFT_R_MGG_FIFO_WPTR 0 +#define BIT_MASK_R_MGG_FIFO_WPTR 0x1f +#define BIT_R_MGG_FIFO_WPTR(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR) +#define BITS_R_MGG_FIFO_WPTR \ + (BIT_MASK_R_MGG_FIFO_WPTR << BIT_SHIFT_R_MGG_FIFO_WPTR) +#define BIT_CLEAR_R_MGG_FIFO_WPTR(x) ((x) & (~BITS_R_MGG_FIFO_WPTR)) +#define BIT_GET_R_MGG_FIFO_WPTR(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR) +#define BIT_SET_R_MGG_FIFO_WPTR(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_WPTR(x) | BIT_R_MGG_FIFO_WPTR(v)) -#define BIT_SHIFT_DDMACH5_DLEN 0 -#define BIT_MASK_DDMACH5_DLEN 0x3ffff -#define BIT_DDMACH5_DLEN(x) (((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN) -#define BIT_GET_DDMACH5_DLEN(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_DDMA_INT_MSK (Offset 0x12E0) */ +/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */ -#define BIT_DDMACH5_MSK BIT(5) -#define BIT_DDMACH4_MSK BIT(4) -#define BIT_DDMACH3_MSK BIT(3) -#define BIT_DDMACH2_MSK BIT(2) -#define BIT_DDMACH1_MSK BIT(1) -#define BIT_DDMACH0_MSK BIT(0) +#define BIT_SHIFT_MGQ_FIFO_WPTR 0 +#define BIT_MASK_MGQ_FIFO_WPTR 0x1f +#define BIT_MGQ_FIFO_WPTR(x) \ + (((x) & BIT_MASK_MGQ_FIFO_WPTR) << BIT_SHIFT_MGQ_FIFO_WPTR) +#define BITS_MGQ_FIFO_WPTR (BIT_MASK_MGQ_FIFO_WPTR << BIT_SHIFT_MGQ_FIFO_WPTR) +#define BIT_CLEAR_MGQ_FIFO_WPTR(x) ((x) & (~BITS_MGQ_FIFO_WPTR)) +#define BIT_GET_MGQ_FIFO_WPTR(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR) & BIT_MASK_MGQ_FIFO_WPTR) +#define BIT_SET_MGQ_FIFO_WPTR(x, v) \ + (BIT_CLEAR_MGQ_FIFO_WPTR(x) | BIT_MGQ_FIFO_WPTR(v)) -/* 2 REG_DDMA_CHSTATUS (Offset 0x12E8) */ +#endif -#define BIT_DDMACH5_BUSY BIT(5) -#define BIT_DDMACH4_BUSY BIT(4) -#define BIT_DDMACH3_BUSY BIT(3) -#define BIT_DDMACH2_BUSY BIT(2) -#define BIT_DDMACH1_BUSY BIT(1) -#define BIT_DDMACH0_BUSY BIT(0) +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_DDMA_CHKSUM (Offset 0x12F0) */ +/* 2 REG_MGQ_FIFO_ENABLE (Offset 0x1472) */ +#define BIT_MGQ_FIFO_EN BIT(15) -#define BIT_SHIFT_IDDMA0_CHKSUM 0 -#define BIT_MASK_IDDMA0_CHKSUM 0xffff -#define BIT_IDDMA0_CHKSUM(x) (((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM) -#define BIT_GET_IDDMA0_CHKSUM(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_DDMA_MONITOR (Offset 0x12FC) */ +/* 2 REG_MGQ_FIFO_ENABLE (Offset 0x1472) */ -#define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14) -#define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13) -#define BIT_IDDMA0_FIFO_OVERFLOW BIT(12) -#define BIT_ECRC_EN_V1 BIT(7) -#define BIT_MDIO_RFLAG_V1 BIT(6) -#define BIT_CH5_ERR BIT(5) -#define BIT_MDIO_WFLAG_V1 BIT(5) -#define BIT_CH4_ERR BIT(4) -#define BIT_CH3_ERR BIT(3) -#define BIT_CH2_ERR BIT(2) -#define BIT_CH1_ERR BIT(1) -#define BIT_CH0_ERR BIT(0) +#define BIT_MGQ_FIFO_EN_V1 BIT(15) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_MGQ_FIFO_READ_POINTER (Offset 0x1472) */ -/* 2 REG_STC_INT_CS (Offset 0x1300) */ +#define BIT_SHIFT_MGQ_FIFO_SIZE 14 +#define BIT_MASK_MGQ_FIFO_SIZE 0x3 +#define BIT_MGQ_FIFO_SIZE(x) \ + (((x) & BIT_MASK_MGQ_FIFO_SIZE) << BIT_SHIFT_MGQ_FIFO_SIZE) +#define BITS_MGQ_FIFO_SIZE (BIT_MASK_MGQ_FIFO_SIZE << BIT_SHIFT_MGQ_FIFO_SIZE) +#define BIT_CLEAR_MGQ_FIFO_SIZE(x) ((x) & (~BITS_MGQ_FIFO_SIZE)) +#define BIT_GET_MGQ_FIFO_SIZE(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE) & BIT_MASK_MGQ_FIFO_SIZE) +#define BIT_SET_MGQ_FIFO_SIZE(x, v) \ + (BIT_CLEAR_MGQ_FIFO_SIZE(x) | BIT_MGQ_FIFO_SIZE(v)) -#define BIT_STC_INT_EN BIT(31) +#define BIT_MGQ_FIFO_PAUSE BIT(13) -#define BIT_SHIFT_STC_INT_FLAG 16 -#define BIT_MASK_STC_INT_FLAG 0xff -#define BIT_STC_INT_FLAG(x) (((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG) -#define BIT_GET_STC_INT_FLAG(x) (((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG) +#define BIT_SHIFT_MGQ_FIFO_PG_SIZE 12 +#define BIT_MASK_MGQ_FIFO_PG_SIZE 0x7 +#define BIT_MGQ_FIFO_PG_SIZE(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE) << BIT_SHIFT_MGQ_FIFO_PG_SIZE) +#define BITS_MGQ_FIFO_PG_SIZE \ + (BIT_MASK_MGQ_FIFO_PG_SIZE << BIT_SHIFT_MGQ_FIFO_PG_SIZE) +#define BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) ((x) & (~BITS_MGQ_FIFO_PG_SIZE)) +#define BIT_GET_MGQ_FIFO_PG_SIZE(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE) & BIT_MASK_MGQ_FIFO_PG_SIZE) +#define BIT_SET_MGQ_FIFO_PG_SIZE(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) | BIT_MGQ_FIFO_PG_SIZE(v)) +#define BIT_SHIFT_MGQ_FIFO_RPTR 8 +#define BIT_MASK_MGQ_FIFO_RPTR 0x1f +#define BIT_MGQ_FIFO_RPTR(x) \ + (((x) & BIT_MASK_MGQ_FIFO_RPTR) << BIT_SHIFT_MGQ_FIFO_RPTR) +#define BITS_MGQ_FIFO_RPTR (BIT_MASK_MGQ_FIFO_RPTR << BIT_SHIFT_MGQ_FIFO_RPTR) +#define BIT_CLEAR_MGQ_FIFO_RPTR(x) ((x) & (~BITS_MGQ_FIFO_RPTR)) +#define BIT_GET_MGQ_FIFO_RPTR(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR) & BIT_MASK_MGQ_FIFO_RPTR) +#define BIT_SET_MGQ_FIFO_RPTR(x, v) \ + (BIT_CLEAR_MGQ_FIFO_RPTR(x) | BIT_MGQ_FIFO_RPTR(v)) -#define BIT_SHIFT_STC_INT_IDX 8 -#define BIT_MASK_STC_INT_IDX 0x7 -#define BIT_STC_INT_IDX(x) (((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX) -#define BIT_GET_STC_INT_IDX(x) (((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX) +#define BIT_SHIFT_MGQ_FIFO_START_PG 0 +#define BIT_MASK_MGQ_FIFO_START_PG 0xfff +#define BIT_MGQ_FIFO_START_PG(x) \ + (((x) & BIT_MASK_MGQ_FIFO_START_PG) << BIT_SHIFT_MGQ_FIFO_START_PG) +#define BITS_MGQ_FIFO_START_PG \ + (BIT_MASK_MGQ_FIFO_START_PG << BIT_SHIFT_MGQ_FIFO_START_PG) +#define BIT_CLEAR_MGQ_FIFO_START_PG(x) ((x) & (~BITS_MGQ_FIFO_START_PG)) +#define BIT_GET_MGQ_FIFO_START_PG(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG) & BIT_MASK_MGQ_FIFO_START_PG) +#define BIT_SET_MGQ_FIFO_START_PG(x, v) \ + (BIT_CLEAR_MGQ_FIFO_START_PG(x) | BIT_MGQ_FIFO_START_PG(v)) +#endif -#define BIT_SHIFT_STC_INT_REALTIME_CS 0 -#define BIT_MASK_STC_INT_REALTIME_CS 0x3f -#define BIT_STC_INT_REALTIME_CS(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS) -#define BIT_GET_STC_INT_REALTIME_CS(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MGG_FIFO_INT (Offset 0x1474) */ -/* 2 REG_ST_INT_CFG (Offset 0x1304) */ +#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16 +#define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff +#define BIT_R_MGG_FIFO_INT_FLAG(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG) +#define BITS_R_MGG_FIFO_INT_FLAG \ + (BIT_MASK_R_MGG_FIFO_INT_FLAG << BIT_SHIFT_R_MGG_FIFO_INT_FLAG) +#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) ((x) & (~BITS_R_MGG_FIFO_INT_FLAG)) +#define BIT_GET_R_MGG_FIFO_INT_FLAG(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG) +#define BIT_SET_R_MGG_FIFO_INT_FLAG(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) | BIT_R_MGG_FIFO_INT_FLAG(v)) + +#define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0 +#define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff +#define BIT_R_MGG_FIFO_INT_MASK(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK) +#define BITS_R_MGG_FIFO_INT_MASK \ + (BIT_MASK_R_MGG_FIFO_INT_MASK << BIT_SHIFT_R_MGG_FIFO_INT_MASK) +#define BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) ((x) & (~BITS_R_MGG_FIFO_INT_MASK)) +#define BIT_GET_R_MGG_FIFO_INT_MASK(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK) +#define BIT_SET_R_MGG_FIFO_INT_MASK(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) | BIT_R_MGG_FIFO_INT_MASK(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK (Offset 0x1474) */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_MASK 0xffff +#define BIT_MGQ_FIFO_REL_INT_MASK(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) +#define BITS_MGQ_FIFO_REL_INT_MASK \ + (BIT_MASK_MGQ_FIFO_REL_INT_MASK << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK)) +#define BIT_GET_MGQ_FIFO_REL_INT_MASK(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) & \ + BIT_MASK_MGQ_FIFO_REL_INT_MASK) +#define BIT_SET_MGQ_FIFO_REL_INT_MASK(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) | BIT_MGQ_FIFO_REL_INT_MASK(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG (Offset 0x1476) */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG 0xffff +#define BIT_MGQ_FIFO_REL_INT_FLAG(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) +#define BITS_MGQ_FIFO_REL_INT_FLAG \ + (BIT_MASK_MGQ_FIFO_REL_INT_FLAG << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG)) +#define BIT_GET_MGQ_FIFO_REL_INT_FLAG(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) & \ + BIT_MASK_MGQ_FIFO_REL_INT_FLAG) +#define BIT_SET_MGQ_FIFO_REL_INT_FLAG(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) | BIT_MGQ_FIFO_REL_INT_FLAG(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_STC_INT_GRP_EN BIT(31) +/* 2 REG_MGG_FIFO_LIFETIME (Offset 0x1478) */ -#define BIT_SHIFT_STC_INT_EXPECT_LS 8 -#define BIT_MASK_STC_INT_EXPECT_LS 0x3f -#define BIT_STC_INT_EXPECT_LS(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS) -#define BIT_GET_STC_INT_EXPECT_LS(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS) +#define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16 +#define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff +#define BIT_R_MGG_FIFO_LIFETIME(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME) +#define BITS_R_MGG_FIFO_LIFETIME \ + (BIT_MASK_R_MGG_FIFO_LIFETIME << BIT_SHIFT_R_MGG_FIFO_LIFETIME) +#define BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) ((x) & (~BITS_R_MGG_FIFO_LIFETIME)) +#define BIT_GET_R_MGG_FIFO_LIFETIME(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME) +#define BIT_SET_R_MGG_FIFO_LIFETIME(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) | BIT_R_MGG_FIFO_LIFETIME(v)) + +#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0 +#define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff +#define BIT_R_MGG_FIFO_VALID_MAP(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP) \ + << BIT_SHIFT_R_MGG_FIFO_VALID_MAP) +#define BITS_R_MGG_FIFO_VALID_MAP \ + (BIT_MASK_R_MGG_FIFO_VALID_MAP << BIT_SHIFT_R_MGG_FIFO_VALID_MAP) +#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) ((x) & (~BITS_R_MGG_FIFO_VALID_MAP)) +#define BIT_GET_R_MGG_FIFO_VALID_MAP(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) & \ + BIT_MASK_R_MGG_FIFO_VALID_MAP) +#define BIT_SET_R_MGG_FIFO_VALID_MAP(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) | BIT_R_MGG_FIFO_VALID_MAP(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_MGQ_FIFO_VALID_MAP (Offset 0x1478) */ + +#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP 0 +#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP 0xffff +#define BIT_MGQ_FIFO_PKT_VALID_MAP(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP) \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) +#define BITS_MGQ_FIFO_PKT_VALID_MAP \ + (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) +#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x) \ + ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP)) +#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) & \ + BIT_MASK_MGQ_FIFO_PKT_VALID_MAP) +#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x) | BIT_MGQ_FIFO_PKT_VALID_MAP(v)) + +/* 2 REG_MGQ_FIFO_LIFETIME (Offset 0x147A) */ + +#define BIT_SHIFT_MGQ_FIFO_LIFETIME 0 +#define BIT_MASK_MGQ_FIFO_LIFETIME 0xffff +#define BIT_MGQ_FIFO_LIFETIME(x) \ + (((x) & BIT_MASK_MGQ_FIFO_LIFETIME) << BIT_SHIFT_MGQ_FIFO_LIFETIME) +#define BITS_MGQ_FIFO_LIFETIME \ + (BIT_MASK_MGQ_FIFO_LIFETIME << BIT_SHIFT_MGQ_FIFO_LIFETIME) +#define BIT_CLEAR_MGQ_FIFO_LIFETIME(x) ((x) & (~BITS_MGQ_FIFO_LIFETIME)) +#define BIT_GET_MGQ_FIFO_LIFETIME(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME) & BIT_MASK_MGQ_FIFO_LIFETIME) +#define BIT_SET_MGQ_FIFO_LIFETIME(x, v) \ + (BIT_CLEAR_MGQ_FIFO_LIFETIME(x) | BIT_MGQ_FIFO_LIFETIME(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_PKT_TRANS (Offset 0x1480) */ + +#define BIT_SHIFT_IE_DESC_OFFSET 16 +#define BIT_MASK_IE_DESC_OFFSET 0x1ff +#define BIT_IE_DESC_OFFSET(x) \ + (((x) & BIT_MASK_IE_DESC_OFFSET) << BIT_SHIFT_IE_DESC_OFFSET) +#define BITS_IE_DESC_OFFSET \ + (BIT_MASK_IE_DESC_OFFSET << BIT_SHIFT_IE_DESC_OFFSET) +#define BIT_CLEAR_IE_DESC_OFFSET(x) ((x) & (~BITS_IE_DESC_OFFSET)) +#define BIT_GET_IE_DESC_OFFSET(x) \ + (((x) >> BIT_SHIFT_IE_DESC_OFFSET) & BIT_MASK_IE_DESC_OFFSET) +#define BIT_SET_IE_DESC_OFFSET(x, v) \ + (BIT_CLEAR_IE_DESC_OFFSET(x) | BIT_IE_DESC_OFFSET(v)) + +#define BIT_DIS_FWCMD_PATH_ERRCHK BIT(13) +#define BIT_MAC_HDR_CONVERT_EN BIT(12) +#define BIT_TXDESC_TRANS_EN BIT(8) +#define BIT_PKT_TRANS_ERRINT_EN BIT(7) + +#define BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL 4 +#define BIT_MASK_PKT_TRANS_ERR_MACID_SEL 0x3 +#define BIT_PKT_TRANS_ERR_MACID_SEL(x) \ + (((x) & BIT_MASK_PKT_TRANS_ERR_MACID_SEL) \ + << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) +#define BITS_PKT_TRANS_ERR_MACID_SEL \ + (BIT_MASK_PKT_TRANS_ERR_MACID_SEL << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) +#define BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x) \ + ((x) & (~BITS_PKT_TRANS_ERR_MACID_SEL)) +#define BIT_GET_PKT_TRANS_ERR_MACID_SEL(x) \ + (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) & \ + BIT_MASK_PKT_TRANS_ERR_MACID_SEL) +#define BIT_SET_PKT_TRANS_ERR_MACID_SEL(x, v) \ + (BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x) | BIT_PKT_TRANS_ERR_MACID_SEL(v)) + +#define BIT_PKT_TRANS_IEINIT_ERR BIT(3) +#define BIT_PKT_TRANS_IENUM_ERR BIT(2) +#define BIT_PKT_TRANS_IECNT_ERR1 BIT(1) +#define BIT_PKT_TRANS_IECNT_ERR0 BIT(0) + +/* 2 REG_SHCUT_LLC_ETH_TYPE1 (Offset 0x1488) */ + +#define BIT_SHIFT_SHCUT_MHDR_OFFSET 16 +#define BIT_MASK_SHCUT_MHDR_OFFSET 0x1ff +#define BIT_SHCUT_MHDR_OFFSET(x) \ + (((x) & BIT_MASK_SHCUT_MHDR_OFFSET) << BIT_SHIFT_SHCUT_MHDR_OFFSET) +#define BITS_SHCUT_MHDR_OFFSET \ + (BIT_MASK_SHCUT_MHDR_OFFSET << BIT_SHIFT_SHCUT_MHDR_OFFSET) +#define BIT_CLEAR_SHCUT_MHDR_OFFSET(x) ((x) & (~BITS_SHCUT_MHDR_OFFSET)) +#define BIT_GET_SHCUT_MHDR_OFFSET(x) \ + (((x) >> BIT_SHIFT_SHCUT_MHDR_OFFSET) & BIT_MASK_SHCUT_MHDR_OFFSET) +#define BIT_SET_SHCUT_MHDR_OFFSET(x, v) \ + (BIT_CLEAR_SHCUT_MHDR_OFFSET(x) | BIT_SHCUT_MHDR_OFFSET(v)) + +#define BIT_SHIFT_PKT_TRANS_ERR_MACID 0 +#define BIT_MASK_PKT_TRANS_ERR_MACID 0xffffffffL +#define BIT_PKT_TRANS_ERR_MACID(x) \ + (((x) & BIT_MASK_PKT_TRANS_ERR_MACID) << BIT_SHIFT_PKT_TRANS_ERR_MACID) +#define BITS_PKT_TRANS_ERR_MACID \ + (BIT_MASK_PKT_TRANS_ERR_MACID << BIT_SHIFT_PKT_TRANS_ERR_MACID) +#define BIT_CLEAR_PKT_TRANS_ERR_MACID(x) ((x) & (~BITS_PKT_TRANS_ERR_MACID)) +#define BIT_GET_PKT_TRANS_ERR_MACID(x) \ + (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID) & BIT_MASK_PKT_TRANS_ERR_MACID) +#define BIT_SET_PKT_TRANS_ERR_MACID(x, v) \ + (BIT_CLEAR_PKT_TRANS_ERR_MACID(x) | BIT_PKT_TRANS_ERR_MACID(v)) + +/* 2 REG_FWCMDQ_CTRL (Offset 0x14A0) */ + +#define BIT_FW_RELEASEPKT_POLLING BIT(31) + +#define BIT_SHIFT_FWCMDQ_RELEASE_HEAD 16 +#define BIT_MASK_FWCMDQ_RELEASE_HEAD 0xfff +#define BIT_FWCMDQ_RELEASE_HEAD(x) \ + (((x) & BIT_MASK_FWCMDQ_RELEASE_HEAD) << BIT_SHIFT_FWCMDQ_RELEASE_HEAD) +#define BITS_FWCMDQ_RELEASE_HEAD \ + (BIT_MASK_FWCMDQ_RELEASE_HEAD << BIT_SHIFT_FWCMDQ_RELEASE_HEAD) +#define BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) ((x) & (~BITS_FWCMDQ_RELEASE_HEAD)) +#define BIT_GET_FWCMDQ_RELEASE_HEAD(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_RELEASE_HEAD) & BIT_MASK_FWCMDQ_RELEASE_HEAD) +#define BIT_SET_FWCMDQ_RELEASE_HEAD(x, v) \ + (BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) | BIT_FWCMDQ_RELEASE_HEAD(v)) + +#define BIT_FW_GETPKTT_POLLING BIT(15) + +#define BIT_SHIFT_FWCMDQ_H 0 +#define BIT_MASK_FWCMDQ_H 0xfff +#define BIT_FWCMDQ_H(x) (((x) & BIT_MASK_FWCMDQ_H) << BIT_SHIFT_FWCMDQ_H) +#define BITS_FWCMDQ_H (BIT_MASK_FWCMDQ_H << BIT_SHIFT_FWCMDQ_H) +#define BIT_CLEAR_FWCMDQ_H(x) ((x) & (~BITS_FWCMDQ_H)) +#define BIT_GET_FWCMDQ_H(x) (((x) >> BIT_SHIFT_FWCMDQ_H) & BIT_MASK_FWCMDQ_H) +#define BIT_SET_FWCMDQ_H(x, v) (BIT_CLEAR_FWCMDQ_H(x) | BIT_FWCMDQ_H(v)) + +/* 2 REG_FWCMDQ_PAGE (Offset 0x14A4) */ + +#define BIT_SHIFT_FWCMDQ_TOTAL_PAGE 16 +#define BIT_MASK_FWCMDQ_TOTAL_PAGE 0xfff +#define BIT_FWCMDQ_TOTAL_PAGE(x) \ + (((x) & BIT_MASK_FWCMDQ_TOTAL_PAGE) << BIT_SHIFT_FWCMDQ_TOTAL_PAGE) +#define BITS_FWCMDQ_TOTAL_PAGE \ + (BIT_MASK_FWCMDQ_TOTAL_PAGE << BIT_SHIFT_FWCMDQ_TOTAL_PAGE) +#define BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) ((x) & (~BITS_FWCMDQ_TOTAL_PAGE)) +#define BIT_GET_FWCMDQ_TOTAL_PAGE(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PAGE) & BIT_MASK_FWCMDQ_TOTAL_PAGE) +#define BIT_SET_FWCMDQ_TOTAL_PAGE(x, v) \ + (BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) | BIT_FWCMDQ_TOTAL_PAGE(v)) + +#define BIT_SHIFT_FWCMDQ_QUEUE_PAGE 0 +#define BIT_MASK_FWCMDQ_QUEUE_PAGE 0xfff +#define BIT_FWCMDQ_QUEUE_PAGE(x) \ + (((x) & BIT_MASK_FWCMDQ_QUEUE_PAGE) << BIT_SHIFT_FWCMDQ_QUEUE_PAGE) +#define BITS_FWCMDQ_QUEUE_PAGE \ + (BIT_MASK_FWCMDQ_QUEUE_PAGE << BIT_SHIFT_FWCMDQ_QUEUE_PAGE) +#define BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) ((x) & (~BITS_FWCMDQ_QUEUE_PAGE)) +#define BIT_GET_FWCMDQ_QUEUE_PAGE(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PAGE) & BIT_MASK_FWCMDQ_QUEUE_PAGE) +#define BIT_SET_FWCMDQ_QUEUE_PAGE(x, v) \ + (BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) | BIT_FWCMDQ_QUEUE_PAGE(v)) + +/* 2 REG_FWCMDQ_INFO (Offset 0x14A8) */ + +#define BIT_FWCMD_READY BIT(31) +#define BIT_FWCMDQ_OVERFLOW BIT(30) +#define BIT_FWCMDQ_UNDERFLOW BIT(29) +#define BIT_FWCMDQ_RELEASE_MISS BIT(28) + +#define BIT_SHIFT_FWCMDQ_TOTAL_PKT 16 +#define BIT_MASK_FWCMDQ_TOTAL_PKT 0xfff +#define BIT_FWCMDQ_TOTAL_PKT(x) \ + (((x) & BIT_MASK_FWCMDQ_TOTAL_PKT) << BIT_SHIFT_FWCMDQ_TOTAL_PKT) +#define BITS_FWCMDQ_TOTAL_PKT \ + (BIT_MASK_FWCMDQ_TOTAL_PKT << BIT_SHIFT_FWCMDQ_TOTAL_PKT) +#define BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) ((x) & (~BITS_FWCMDQ_TOTAL_PKT)) +#define BIT_GET_FWCMDQ_TOTAL_PKT(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PKT) & BIT_MASK_FWCMDQ_TOTAL_PKT) +#define BIT_SET_FWCMDQ_TOTAL_PKT(x, v) \ + (BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) | BIT_FWCMDQ_TOTAL_PKT(v)) + +#define BIT_SHIFT_FWCMDQ_QUEUE_PKT 0 +#define BIT_MASK_FWCMDQ_QUEUE_PKT 0xfff +#define BIT_FWCMDQ_QUEUE_PKT(x) \ + (((x) & BIT_MASK_FWCMDQ_QUEUE_PKT) << BIT_SHIFT_FWCMDQ_QUEUE_PKT) +#define BITS_FWCMDQ_QUEUE_PKT \ + (BIT_MASK_FWCMDQ_QUEUE_PKT << BIT_SHIFT_FWCMDQ_QUEUE_PKT) +#define BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) ((x) & (~BITS_FWCMDQ_QUEUE_PKT)) +#define BIT_GET_FWCMDQ_QUEUE_PKT(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PKT) & BIT_MASK_FWCMDQ_QUEUE_PKT) +#define BIT_SET_FWCMDQ_QUEUE_PKT(x, v) \ + (BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) | BIT_FWCMDQ_QUEUE_PKT(v)) + +/* 2 REG_FWCMDQ_HOLD_PKTNUM (Offset 0x14AC) */ + +#define BIT_SHIFT_FWCMDQ_HOLD__PKTNUM 0 +#define BIT_MASK_FWCMDQ_HOLD__PKTNUM 0xfff +#define BIT_FWCMDQ_HOLD__PKTNUM(x) \ + (((x) & BIT_MASK_FWCMDQ_HOLD__PKTNUM) << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) +#define BITS_FWCMDQ_HOLD__PKTNUM \ + (BIT_MASK_FWCMDQ_HOLD__PKTNUM << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) +#define BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) ((x) & (~BITS_FWCMDQ_HOLD__PKTNUM)) +#define BIT_GET_FWCMDQ_HOLD__PKTNUM(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) & BIT_MASK_FWCMDQ_HOLD__PKTNUM) +#define BIT_SET_FWCMDQ_HOLD__PKTNUM(x, v) \ + (BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) | BIT_FWCMDQ_HOLD__PKTNUM(v)) + +/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ + +#define BIT_SEARCH_DONE_RDY BIT(31) +#define BIT_MU_EN BIT(30) +#define BIT_MU_SECONDARY_WAITMODE_EN BIT(29) +#define BIT_MU_BB_SCORE_EN BIT(28) +#define BIT_MU_SECONDARY_ANT_COUNT_EN BIT(27) +#define BIT_MUARB_SEARCH_ERR_EN BIT(26) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ -#define BIT_SHIFT_STC_INT_EXPECT_CS 0 -#define BIT_MASK_STC_INT_EXPECT_CS 0x3f -#define BIT_STC_INT_EXPECT_CS(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS) -#define BIT_GET_STC_INT_EXPECT_CS(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS) +#define BIT_R_MU_P1_WAIT_STATE_EN BIT(16) +#endif -/* 2 REG_CMU_DLY_CTRL (Offset 0x1310) */ +#if (HALMAC_8814B_SUPPORT) -#define BIT_CMU_DLY_EN BIT(31) -#define BIT_CMU_DLY_MODE BIT(30) +/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ -#define BIT_SHIFT_CMU_DLY_PRE_DIV 0 -#define BIT_MASK_CMU_DLY_PRE_DIV 0xff -#define BIT_CMU_DLY_PRE_DIV(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV) -#define BIT_GET_CMU_DLY_PRE_DIV(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV) +#define BIT_SHIFT_DIS_SU_TXBF 16 +#define BIT_MASK_DIS_SU_TXBF 0x3f +#define BIT_DIS_SU_TXBF(x) \ + (((x) & BIT_MASK_DIS_SU_TXBF) << BIT_SHIFT_DIS_SU_TXBF) +#define BITS_DIS_SU_TXBF (BIT_MASK_DIS_SU_TXBF << BIT_SHIFT_DIS_SU_TXBF) +#define BIT_CLEAR_DIS_SU_TXBF(x) ((x) & (~BITS_DIS_SU_TXBF)) +#define BIT_GET_DIS_SU_TXBF(x) \ + (((x) >> BIT_SHIFT_DIS_SU_TXBF) & BIT_MASK_DIS_SU_TXBF) +#define BIT_SET_DIS_SU_TXBF(x, v) \ + (BIT_CLEAR_DIS_SU_TXBF(x) | BIT_DIS_SU_TXBF(v)) +#endif -/* 2 REG_CMU_DLY_CFG (Offset 0x1314) */ +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ -#define BIT_SHIFT_CMU_DLY_LTR_A2I 24 -#define BIT_MASK_CMU_DLY_LTR_A2I 0xff -#define BIT_CMU_DLY_LTR_A2I(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I) -#define BIT_GET_CMU_DLY_LTR_A2I(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I) +#define BIT_SHIFT_R_MU_RL 12 +#define BIT_MASK_R_MU_RL 0xf +#define BIT_R_MU_RL(x) (((x) & BIT_MASK_R_MU_RL) << BIT_SHIFT_R_MU_RL) +#define BITS_R_MU_RL (BIT_MASK_R_MU_RL << BIT_SHIFT_R_MU_RL) +#define BIT_CLEAR_R_MU_RL(x) ((x) & (~BITS_R_MU_RL)) +#define BIT_GET_R_MU_RL(x) (((x) >> BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL) +#define BIT_SET_R_MU_RL(x, v) (BIT_CLEAR_R_MU_RL(x) | BIT_R_MU_RL(v)) +#endif -#define BIT_SHIFT_CMU_DLY_LTR_I2A 16 -#define BIT_MASK_CMU_DLY_LTR_I2A 0xff -#define BIT_CMU_DLY_LTR_I2A(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A) -#define BIT_GET_CMU_DLY_LTR_I2A(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ -#define BIT_SHIFT_CMU_DLY_LTR_IDLE 8 -#define BIT_MASK_CMU_DLY_LTR_IDLE 0xff -#define BIT_CMU_DLY_LTR_IDLE(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE) -#define BIT_GET_CMU_DLY_LTR_IDLE(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE) +#define BIT_SHIFT_MU_RL 12 +#define BIT_MASK_MU_RL 0xf +#define BIT_MU_RL(x) (((x) & BIT_MASK_MU_RL) << BIT_SHIFT_MU_RL) +#define BITS_MU_RL (BIT_MASK_MU_RL << BIT_SHIFT_MU_RL) +#define BIT_CLEAR_MU_RL(x) ((x) & (~BITS_MU_RL)) +#define BIT_GET_MU_RL(x) (((x) >> BIT_SHIFT_MU_RL) & BIT_MASK_MU_RL) +#define BIT_SET_MU_RL(x, v) (BIT_CLEAR_MU_RL(x) | BIT_MU_RL(v)) +#endif -#define BIT_SHIFT_CMU_DLY_LTR_ACT 0 -#define BIT_MASK_CMU_DLY_LTR_ACT 0xff -#define BIT_CMU_DLY_LTR_ACT(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT) -#define BIT_GET_CMU_DLY_LTR_ACT(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT) +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ -/* 2 REG_H2CQ_TXBD_DESA (Offset 0x1320) */ +#define BIT_R_FORCE_P1_RATEDOWN BIT(11) +#define BIT_SHIFT_R_MU_TAB_SEL 8 +#define BIT_MASK_R_MU_TAB_SEL 0x7 +#define BIT_R_MU_TAB_SEL(x) \ + (((x) & BIT_MASK_R_MU_TAB_SEL) << BIT_SHIFT_R_MU_TAB_SEL) +#define BITS_R_MU_TAB_SEL (BIT_MASK_R_MU_TAB_SEL << BIT_SHIFT_R_MU_TAB_SEL) +#define BIT_CLEAR_R_MU_TAB_SEL(x) ((x) & (~BITS_R_MU_TAB_SEL)) +#define BIT_GET_R_MU_TAB_SEL(x) \ + (((x) >> BIT_SHIFT_R_MU_TAB_SEL) & BIT_MASK_R_MU_TAB_SEL) +#define BIT_SET_R_MU_TAB_SEL(x, v) \ + (BIT_CLEAR_R_MU_TAB_SEL(x) | BIT_R_MU_TAB_SEL(v)) -#define BIT_SHIFT_H2CQ_TXBD_DESA 0 -#define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL -#define BIT_H2CQ_TXBD_DESA(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA) -#define BIT_GET_H2CQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA) +#endif +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ +#define BIT_SHIFT_MU_TAB_SEL 8 +#define BIT_MASK_MU_TAB_SEL 0xf +#define BIT_MU_TAB_SEL(x) (((x) & BIT_MASK_MU_TAB_SEL) << BIT_SHIFT_MU_TAB_SEL) +#define BITS_MU_TAB_SEL (BIT_MASK_MU_TAB_SEL << BIT_SHIFT_MU_TAB_SEL) +#define BIT_CLEAR_MU_TAB_SEL(x) ((x) & (~BITS_MU_TAB_SEL)) +#define BIT_GET_MU_TAB_SEL(x) \ + (((x) >> BIT_SHIFT_MU_TAB_SEL) & BIT_MASK_MU_TAB_SEL) +#define BIT_SET_MU_TAB_SEL(x, v) (BIT_CLEAR_MU_TAB_SEL(x) | BIT_MU_TAB_SEL(v)) -#if (HALMAC_8197F_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ +/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ -#define BIT_HCI_H2CQ_FLAG BIT(14) +#define BIT_R_EN_MU_MIMO BIT(7) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ -/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ +#define BIT_R_EN_REVERS_GTAB BIT(6) -#define BIT_PCIE_H2CQ_FLAG BIT(14) +#define BIT_SHIFT_R_MU_TABLE_VALID 0 +#define BIT_MASK_R_MU_TABLE_VALID 0x3f +#define BIT_R_MU_TABLE_VALID(x) \ + (((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID) +#define BITS_R_MU_TABLE_VALID \ + (BIT_MASK_R_MU_TABLE_VALID << BIT_SHIFT_R_MU_TABLE_VALID) +#define BIT_CLEAR_R_MU_TABLE_VALID(x) ((x) & (~BITS_R_MU_TABLE_VALID)) +#define BIT_GET_R_MU_TABLE_VALID(x) \ + (((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID) +#define BIT_SET_R_MU_TABLE_VALID(x, v) \ + (BIT_CLEAR_R_MU_TABLE_VALID(x) | BIT_R_MU_TABLE_VALID(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */ +#define BIT_SHIFT_MU_TAB_VALID 0 +#define BIT_MASK_MU_TAB_VALID 0x3f +#define BIT_MU_TAB_VALID(x) \ + (((x) & BIT_MASK_MU_TAB_VALID) << BIT_SHIFT_MU_TAB_VALID) +#define BITS_MU_TAB_VALID (BIT_MASK_MU_TAB_VALID << BIT_SHIFT_MU_TAB_VALID) +#define BIT_CLEAR_MU_TAB_VALID(x) ((x) & (~BITS_MU_TAB_VALID)) +#define BIT_GET_MU_TAB_VALID(x) \ + (((x) >> BIT_SHIFT_MU_TAB_VALID) & BIT_MASK_MU_TAB_VALID) +#define BIT_SET_MU_TAB_VALID(x, v) \ + (BIT_CLEAR_MU_TAB_VALID(x) | BIT_MU_TAB_VALID(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ +/* 2 REG_MU_STA_GID_VLD (Offset 0x14C4) */ +#define BIT_SHIFT_R_MU_STA_GTAB_VALID 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID) +#define BITS_R_MU_STA_GTAB_VALID \ + (BIT_MASK_R_MU_STA_GTAB_VALID << BIT_SHIFT_R_MU_STA_GTAB_VALID) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID(x) ((x) & (~BITS_R_MU_STA_GTAB_VALID)) +#define BIT_GET_R_MU_STA_GTAB_VALID(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID) +#define BIT_SET_R_MU_STA_GTAB_VALID(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID(x) | BIT_R_MU_STA_GTAB_VALID(v)) -#define BIT_SHIFT_H2CQ_DESC_MODE 12 -#define BIT_MASK_H2CQ_DESC_MODE 0x3 -#define BIT_H2CQ_DESC_MODE(x) (((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE) -#define BIT_GET_H2CQ_DESC_MODE(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE) +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_MU_STA_GID_VLD (Offset 0x14C4) */ + +#define BIT_SHIFT_MU_STA_GTAB_VALID 0 +#define BIT_MASK_MU_STA_GTAB_VALID 0xffffffffL +#define BIT_MU_STA_GTAB_VALID(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_VALID) << BIT_SHIFT_MU_STA_GTAB_VALID) +#define BITS_MU_STA_GTAB_VALID \ + (BIT_MASK_MU_STA_GTAB_VALID << BIT_SHIFT_MU_STA_GTAB_VALID) +#define BIT_CLEAR_MU_STA_GTAB_VALID(x) ((x) & (~BITS_MU_STA_GTAB_VALID)) +#define BIT_GET_MU_STA_GTAB_VALID(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_VALID) & BIT_MASK_MU_STA_GTAB_VALID) +#define BIT_SET_MU_STA_GTAB_VALID(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_VALID(x) | BIT_MU_STA_GTAB_VALID(v)) +#endif -#define BIT_SHIFT_H2CQ_DESC_NUM 0 -#define BIT_MASK_H2CQ_DESC_NUM 0xfff -#define BIT_H2CQ_DESC_NUM(x) (((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM) -#define BIT_GET_H2CQ_DESC_NUM(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM) +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_MU_STA_USER_POS_INFO (Offset 0x14C8) */ -/* 2 REG_H2CQ_TXBD_IDX (Offset 0x132C) */ +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_L 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_L(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) +#define BITS_R_MU_STA_GTAB_POSITION_L \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_L \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_L)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_L(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_L) +#define BIT_SET_R_MU_STA_GTAB_POSITION_L(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x) | \ + BIT_R_MU_STA_GTAB_POSITION_L(v)) +#endif + +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_H2CQ_HW_IDX 16 -#define BIT_MASK_H2CQ_HW_IDX 0xfff -#define BIT_H2CQ_HW_IDX(x) (((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX) -#define BIT_GET_H2CQ_HW_IDX(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX) +/* 2 REG_MU_STA_USER_POS_INFO (Offset 0x14C8) */ +#define BIT_SHIFT_MU_STA_GTAB_POSITION_L 0 +#define BIT_MASK_MU_STA_GTAB_POSITION_L 0xffffffffL +#define BIT_MU_STA_GTAB_POSITION_L(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_POSITION_L) \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_L) +#define BITS_MU_STA_GTAB_POSITION_L \ + (BIT_MASK_MU_STA_GTAB_POSITION_L << BIT_SHIFT_MU_STA_GTAB_POSITION_L) +#define BIT_CLEAR_MU_STA_GTAB_POSITION_L(x) \ + ((x) & (~BITS_MU_STA_GTAB_POSITION_L)) +#define BIT_GET_MU_STA_GTAB_POSITION_L(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_L) & \ + BIT_MASK_MU_STA_GTAB_POSITION_L) +#define BIT_SET_MU_STA_GTAB_POSITION_L(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_POSITION_L(x) | BIT_MU_STA_GTAB_POSITION_L(v)) -#define BIT_SHIFT_H2CQ_HOST_IDX 0 -#define BIT_MASK_H2CQ_HOST_IDX 0xfff -#define BIT_H2CQ_HOST_IDX(x) (((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX) -#define BIT_GET_H2CQ_HOST_IDX(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_H2CQ_CSR (Offset 0x1330) */ +/* 2 REG_MU_STA_USER_POS_INFO_H (Offset 0x14CC) */ -#define BIT_H2CQ_FULL BIT(31) -#define BIT_CLR_H2CQ_HOST_IDX BIT(16) -#define BIT_CLR_H2CQ_HW_IDX BIT(8) +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_H 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_H(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) +#define BITS_R_MU_STA_GTAB_POSITION_H \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_H \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_H)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_H(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_H) +#define BIT_SET_R_MU_STA_GTAB_POSITION_H(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x) | \ + BIT_R_MU_STA_GTAB_POSITION_H(v)) #endif +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_MU_STA_USER_POS_INFO_H (Offset 0x14CC) */ + +#define BIT_SHIFT_MU_STA_GTAB_POSITION_H 0 +#define BIT_MASK_MU_STA_GTAB_POSITION_H 0xffffffffL +#define BIT_MU_STA_GTAB_POSITION_H(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_POSITION_H) \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_H) +#define BITS_MU_STA_GTAB_POSITION_H \ + (BIT_MASK_MU_STA_GTAB_POSITION_H << BIT_SHIFT_MU_STA_GTAB_POSITION_H) +#define BIT_CLEAR_MU_STA_GTAB_POSITION_H(x) \ + ((x) & (~BITS_MU_STA_GTAB_POSITION_H)) +#define BIT_GET_MU_STA_GTAB_POSITION_H(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_H) & \ + BIT_MASK_MU_STA_GTAB_POSITION_H) +#define BIT_SET_MU_STA_GTAB_POSITION_H(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_POSITION_H(x) | BIT_MU_STA_GTAB_POSITION_H(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) +#define BIT_MU_DNGCNT_RST BIT(20) +#endif -/* 2 REG_H2CQ_CSR (Offset 0x1330) */ +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_STOP_H2CQ BIT(0) +/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ + +#define BIT_SHIFT_MU_DBGCNT_SEL 16 +#define BIT_MASK_MU_DBGCNT_SEL 0xf +#define BIT_MU_DBGCNT_SEL(x) \ + (((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL) +#define BITS_MU_DBGCNT_SEL (BIT_MASK_MU_DBGCNT_SEL << BIT_SHIFT_MU_DBGCNT_SEL) +#define BIT_CLEAR_MU_DBGCNT_SEL(x) ((x) & (~BITS_MU_DBGCNT_SEL)) +#define BIT_GET_MU_DBGCNT_SEL(x) \ + (((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL) +#define BIT_SET_MU_DBGCNT_SEL(x, v) \ + (BIT_CLEAR_MU_DBGCNT_SEL(x) | BIT_MU_DBGCNT_SEL(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */ +#define BIT_CHNL_REF_RXNAV BIT(7) +#define BIT_CHNL_REF_VBON BIT(6) -/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ +#endif -#define BIT_AXI_RXDMA_TIMEOUT_RE BIT(21) -#define BIT_AXI_TXDMA_TIMEOUT_RE BIT(20) -#define BIT_AXI_DECERR_W_RE BIT(19) -#define BIT_AXI_DECERR_R_RE BIT(18) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#endif +/* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */ +#define BIT_CHNL_REF_EDCCA BIT(5) -#if (HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ +/* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */ -#define BIT_CHANGE_PCIE_SPEED BIT(18) +#define BIT_RST_CHNL_BUSY BIT(3) +#define BIT_RST_CHNL_IDLE BIT(2) +#define BIT_CHNL_INFO_RST BIT(1) +#define BIT_ATM_AIRTIME_EN BIT(0) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ +#define BIT_SHIFT_MU_DNGCNT 0 +#define BIT_MASK_MU_DNGCNT 0xffff +#define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT) +#define BITS_MU_DNGCNT (BIT_MASK_MU_DNGCNT << BIT_SHIFT_MU_DNGCNT) +#define BIT_CLEAR_MU_DNGCNT(x) ((x) & (~BITS_MU_DNGCNT)) +#define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT) +#define BIT_SET_MU_DNGCNT(x, v) (BIT_CLEAR_MU_DNGCNT(x) | BIT_MU_DNGCNT(v)) -/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_AXI_SLVERR_W_RE BIT(17) -#define BIT_AXI_SLVERR_R_RE BIT(16) +/* 2 REG_CHNL_BUSY_TIME (Offset 0x14D8) */ + +#define BIT_SHIFT_CHNL_BUSY_TIME 0 +#define BIT_MASK_CHNL_BUSY_TIME 0xffffffffL +#define BIT_CHNL_BUSY_TIME(x) \ + (((x) & BIT_MASK_CHNL_BUSY_TIME) << BIT_SHIFT_CHNL_BUSY_TIME) +#define BITS_CHNL_BUSY_TIME \ + (BIT_MASK_CHNL_BUSY_TIME << BIT_SHIFT_CHNL_BUSY_TIME) +#define BIT_CLEAR_CHNL_BUSY_TIME(x) ((x) & (~BITS_CHNL_BUSY_TIME)) +#define BIT_GET_CHNL_BUSY_TIME(x) \ + (((x) >> BIT_SHIFT_CHNL_BUSY_TIME) & BIT_MASK_CHNL_BUSY_TIME) +#define BIT_SET_CHNL_BUSY_TIME(x, v) \ + (BIT_CLEAR_CHNL_BUSY_TIME(x) | BIT_CHNL_BUSY_TIME(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_MU_TRX_DBG_CNT_V1 (Offset 0x14DC) */ +#define BIT_FORCE_SND_STS_EN BIT(31) -/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ +#define BIT_SHIFT_SND_STS_VALUE 24 +#define BIT_MASK_SND_STS_VALUE 0x3f +#define BIT_SND_STS_VALUE(x) \ + (((x) & BIT_MASK_SND_STS_VALUE) << BIT_SHIFT_SND_STS_VALUE) +#define BITS_SND_STS_VALUE (BIT_MASK_SND_STS_VALUE << BIT_SHIFT_SND_STS_VALUE) +#define BIT_CLEAR_SND_STS_VALUE(x) ((x) & (~BITS_SND_STS_VALUE)) +#define BIT_GET_SND_STS_VALUE(x) \ + (((x) >> BIT_SHIFT_SND_STS_VALUE) & BIT_MASK_SND_STS_VALUE) +#define BIT_SET_SND_STS_VALUE(x, v) \ + (BIT_CLEAR_SND_STS_VALUE(x) | BIT_SND_STS_VALUE(v)) + +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_GEN1_GEN2 16 -#define BIT_MASK_GEN1_GEN2 0x3 -#define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2) -#define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2) +/* 2 REG_MU_TRX_DBG_CNT_V1 (Offset 0x14DC) */ +#define BIT_SHIFT_MU_DNGCNT_SEL 16 +#define BIT_MASK_MU_DNGCNT_SEL 0xf +#define BIT_MU_DNGCNT_SEL(x) \ + (((x) & BIT_MASK_MU_DNGCNT_SEL) << BIT_SHIFT_MU_DNGCNT_SEL) +#define BITS_MU_DNGCNT_SEL (BIT_MASK_MU_DNGCNT_SEL << BIT_SHIFT_MU_DNGCNT_SEL) +#define BIT_CLEAR_MU_DNGCNT_SEL(x) ((x) & (~BITS_MU_DNGCNT_SEL)) +#define BIT_GET_MU_DNGCNT_SEL(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_SEL) & BIT_MASK_MU_DNGCNT_SEL) +#define BIT_SET_MU_DNGCNT_SEL(x, v) \ + (BIT_CLEAR_MU_DNGCNT_SEL(x) | BIT_MU_DNGCNT_SEL(v)) #endif +#if (HALMAC_8812F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SU_DURATION (Offset 0x14F0) */ +#define BIT_SHIFT_SU_DURATION 0 +#define BIT_MASK_SU_DURATION 0xffff +#define BIT_SU_DURATION(x) \ + (((x) & BIT_MASK_SU_DURATION) << BIT_SHIFT_SU_DURATION) +#define BITS_SU_DURATION (BIT_MASK_SU_DURATION << BIT_SHIFT_SU_DURATION) +#define BIT_CLEAR_SU_DURATION(x) ((x) & (~BITS_SU_DURATION)) +#define BIT_GET_SU_DURATION(x) \ + (((x) >> BIT_SHIFT_SU_DURATION) & BIT_MASK_SU_DURATION) +#define BIT_SET_SU_DURATION(x, v) \ + (BIT_CLEAR_SU_DURATION(x) | BIT_SU_DURATION(v)) -/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */ +/* 2 REG_MU_DURATION (Offset 0x14F2) */ -#define BIT_AXI_RXDMA_TIMEOUT_IE BIT(13) -#define BIT_AXI_TXDMA_TIMEOUT_IE BIT(12) -#define BIT_AXI_DECERR_W_IE BIT(11) -#define BIT_AXI_DECERR_R_IE BIT(10) -#define BIT_AXI_SLVERR_W_IE BIT(9) -#define BIT_AXI_SLVERR_R_IE BIT(8) -#define BIT_AXI_RXDMA_TIMEOUT_FLAG BIT(5) -#define BIT_AXI_TXDMA_TIMEOUT_FLAG BIT(4) -#define BIT_AXI_DECERR_W_FLAG BIT(3) -#define BIT_AXI_DECERR_R_FLAG BIT(2) -#define BIT_AXI_SLVERR_W_FLAG BIT(1) -#define BIT_AXI_SLVERR_R_FLAG BIT(0) +#define BIT_SHIFT_MU_DURATION 0 +#define BIT_MASK_MU_DURATION 0xffff +#define BIT_MU_DURATION(x) \ + (((x) & BIT_MASK_MU_DURATION) << BIT_SHIFT_MU_DURATION) +#define BITS_MU_DURATION (BIT_MASK_MU_DURATION << BIT_SHIFT_MU_DURATION) +#define BIT_CLEAR_MU_DURATION(x) ((x) & (~BITS_MU_DURATION)) +#define BIT_GET_MU_DURATION(x) \ + (((x) >> BIT_SHIFT_MU_DURATION) & BIT_MASK_MU_DURATION) +#define BIT_SET_MU_DURATION(x, v) \ + (BIT_CLEAR_MU_DURATION(x) | BIT_MU_DURATION(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_SWPS_CTRL (Offset 0x14F4) */ +#define BIT_SHIFT_SWPS_RPT_LENGTH 8 +#define BIT_MASK_SWPS_RPT_LENGTH 0x7f +#define BIT_SWPS_RPT_LENGTH(x) \ + (((x) & BIT_MASK_SWPS_RPT_LENGTH) << BIT_SHIFT_SWPS_RPT_LENGTH) +#define BITS_SWPS_RPT_LENGTH \ + (BIT_MASK_SWPS_RPT_LENGTH << BIT_SHIFT_SWPS_RPT_LENGTH) +#define BIT_CLEAR_SWPS_RPT_LENGTH(x) ((x) & (~BITS_SWPS_RPT_LENGTH)) +#define BIT_GET_SWPS_RPT_LENGTH(x) \ + (((x) >> BIT_SHIFT_SWPS_RPT_LENGTH) & BIT_MASK_SWPS_RPT_LENGTH) +#define BIT_SET_SWPS_RPT_LENGTH(x, v) \ + (BIT_CLEAR_SWPS_RPT_LENGTH(x) | BIT_SWPS_RPT_LENGTH(v)) -/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ +#define BIT_SHIFT_MACID_SWPS_EN_SEL 2 +#define BIT_MASK_MACID_SWPS_EN_SEL 0x3 +#define BIT_MACID_SWPS_EN_SEL(x) \ + (((x) & BIT_MASK_MACID_SWPS_EN_SEL) << BIT_SHIFT_MACID_SWPS_EN_SEL) +#define BITS_MACID_SWPS_EN_SEL \ + (BIT_MASK_MACID_SWPS_EN_SEL << BIT_SHIFT_MACID_SWPS_EN_SEL) +#define BIT_CLEAR_MACID_SWPS_EN_SEL(x) ((x) & (~BITS_MACID_SWPS_EN_SEL)) +#define BIT_GET_MACID_SWPS_EN_SEL(x) \ + (((x) >> BIT_SHIFT_MACID_SWPS_EN_SEL) & BIT_MASK_MACID_SWPS_EN_SEL) +#define BIT_SET_MACID_SWPS_EN_SEL(x, v) \ + (BIT_CLEAR_MACID_SWPS_EN_SEL(x) | BIT_MACID_SWPS_EN_SEL(v)) + +#define BIT_SWPS_MANUALL_POLLING BIT(1) +#define BIT_SWPS_EN BIT(0) +#endif + +#if (HALMAC_8812F_SUPPORT) -#define BIT_SHIFT_AUTO_HANG_RELEASE 0 -#define BIT_MASK_AUTO_HANG_RELEASE 0x7 -#define BIT_AUTO_HANG_RELEASE(x) (((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE) -#define BIT_GET_AUTO_HANG_RELEASE(x) (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE) +/* 2 REG_HW_NDPA_RTY_LIMIT (Offset 0x14F4) */ +#define BIT_SHIFT_HW_NDPA_RTY_LIMIT 0 +#define BIT_MASK_HW_NDPA_RTY_LIMIT 0xf +#define BIT_HW_NDPA_RTY_LIMIT(x) \ + (((x) & BIT_MASK_HW_NDPA_RTY_LIMIT) << BIT_SHIFT_HW_NDPA_RTY_LIMIT) +#define BITS_HW_NDPA_RTY_LIMIT \ + (BIT_MASK_HW_NDPA_RTY_LIMIT << BIT_SHIFT_HW_NDPA_RTY_LIMIT) +#define BIT_CLEAR_HW_NDPA_RTY_LIMIT(x) ((x) & (~BITS_HW_NDPA_RTY_LIMIT)) +#define BIT_GET_HW_NDPA_RTY_LIMIT(x) \ + (((x) >> BIT_SHIFT_HW_NDPA_RTY_LIMIT) & BIT_MASK_HW_NDPA_RTY_LIMIT) +#define BIT_SET_HW_NDPA_RTY_LIMIT(x, v) \ + (BIT_CLEAR_HW_NDPA_RTY_LIMIT(x) | BIT_HW_NDPA_RTY_LIMIT(v)) #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_MACID_SWPS_EN (Offset 0x14FC) */ +#define BIT_SHIFT_MACID_SWPS_EN 0 +#define BIT_MASK_MACID_SWPS_EN 0xffffffffL +#define BIT_MACID_SWPS_EN(x) \ + (((x) & BIT_MASK_MACID_SWPS_EN) << BIT_SHIFT_MACID_SWPS_EN) +#define BITS_MACID_SWPS_EN (BIT_MASK_MACID_SWPS_EN << BIT_SHIFT_MACID_SWPS_EN) +#define BIT_CLEAR_MACID_SWPS_EN(x) ((x) & (~BITS_MACID_SWPS_EN)) +#define BIT_GET_MACID_SWPS_EN(x) \ + (((x) >> BIT_SHIFT_MACID_SWPS_EN) & BIT_MASK_MACID_SWPS_EN) +#define BIT_SET_MACID_SWPS_EN(x, v) \ + (BIT_CLEAR_MACID_SWPS_EN(x) | BIT_MACID_SWPS_EN(v)) -/* 2 REG_AXI_EXCEPT_TIME (Offset 0x1354) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_AXI_RECOVERY_TIME 24 -#define BIT_MASK_AXI_RECOVERY_TIME 0xff -#define BIT_AXI_RECOVERY_TIME(x) (((x) & BIT_MASK_AXI_RECOVERY_TIME) << BIT_SHIFT_AXI_RECOVERY_TIME) -#define BIT_GET_AXI_RECOVERY_TIME(x) (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME) & BIT_MASK_AXI_RECOVERY_TIME) +/* 2 REG_PORT_CTRL_SEL (Offset 0x1500) */ +#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1 4 +#define BIT_MASK_BCN_TIMER_SEL_FWRD_V1 0x7 +#define BIT_BCN_TIMER_SEL_FWRD_V1(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_V1) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) +#define BITS_BCN_TIMER_SEL_FWRD_V1 \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_V1 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD_V1)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_V1(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_V1) +#define BIT_SET_BCN_TIMER_SEL_FWRD_V1(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) | BIT_BCN_TIMER_SEL_FWRD_V1(v)) -#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL 12 -#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL 0xfff -#define BIT_AXI_RXDMA_TIMEOUT_VAL(x) (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) -#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL(x) (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL 0 -#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL 0xfff -#define BIT_AXI_TXDMA_TIMEOUT_VAL(x) (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) -#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL(x) (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) +/* 2 REG_CPUMGQ_TX_TIMER (Offset 0x1500) */ +#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL +#define BIT_CPUMGQ_TX_TIMER_V1(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1) +#define BITS_CPUMGQ_TX_TIMER_V1 \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_V1)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1) +#define BIT_SET_CPUMGQ_TX_TIMER_V1(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) | BIT_CPUMGQ_TX_TIMER_V1(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_PORT_CTRL_SEL (Offset 0x1500) */ +#define BIT_SHIFT_PORT_CTRL_SEL 0 +#define BIT_MASK_PORT_CTRL_SEL 0x7 +#define BIT_PORT_CTRL_SEL(x) \ + (((x) & BIT_MASK_PORT_CTRL_SEL) << BIT_SHIFT_PORT_CTRL_SEL) +#define BITS_PORT_CTRL_SEL (BIT_MASK_PORT_CTRL_SEL << BIT_SHIFT_PORT_CTRL_SEL) +#define BIT_CLEAR_PORT_CTRL_SEL(x) ((x) & (~BITS_PORT_CTRL_SEL)) +#define BIT_GET_PORT_CTRL_SEL(x) \ + (((x) >> BIT_SHIFT_PORT_CTRL_SEL) & BIT_MASK_PORT_CTRL_SEL) +#define BIT_SET_PORT_CTRL_SEL(x, v) \ + (BIT_CLEAR_PORT_CTRL_SEL(x) | BIT_PORT_CTRL_SEL(v)) -/* 2 REG_OLD_DEHANG (Offset 0x13F4) */ +/* 2 REG_PORT_CTRL_CFG (Offset 0x1501) */ -#define BIT_OLD_DEHANG BIT(1) +#define BIT_BCNERR_CNT_EN_V1 BIT(11) +#define BIT_DIS_TRX_CAL_BCN_V1 BIT(10) +#define BIT_DIS_TX_CAL_TBTT_V1 BIT(9) +#define BIT_BCN_AGGRESSION_V1 BIT(8) +#define BIT_TSFTR_RST_V1 BIT(7) +#define BIT_EN_TXBCN_RPT_V1 BIT(5) +#define BIT_EN_PORT_FUNCTION BIT(3) +#define BIT_EN_RXBCN_RPT BIT(2) -#endif +/* 2 REG_TBTT_PROHIBIT_CFG (Offset 0x1504) */ +#define BIT_MASK_PROHIBIT BIT(23) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_TBTT_HOLD_TIME 8 +#define BIT_MASK_TBTT_HOLD_TIME 0xfff +#define BIT_TBTT_HOLD_TIME(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME) << BIT_SHIFT_TBTT_HOLD_TIME) +#define BITS_TBTT_HOLD_TIME \ + (BIT_MASK_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME) +#define BIT_CLEAR_TBTT_HOLD_TIME(x) ((x) & (~BITS_TBTT_HOLD_TIME)) +#define BIT_GET_TBTT_HOLD_TIME(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME) & BIT_MASK_TBTT_HOLD_TIME) +#define BIT_SET_TBTT_HOLD_TIME(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME(x) | BIT_TBTT_HOLD_TIME(v)) +#endif -/* 2 REG_Q0_Q1_INFO (Offset 0x1400) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_PS_TIMER_A (Offset 0x1504) */ -#define BIT_SHIFT_AC1_PKT_INFO 16 -#define BIT_MASK_AC1_PKT_INFO 0xfff -#define BIT_AC1_PKT_INFO(x) (((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO) -#define BIT_GET_AC1_PKT_INFO(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO) +#define BIT_SHIFT_PS_TIMER_A_V1 0 +#define BIT_MASK_PS_TIMER_A_V1 0xffffffffL +#define BIT_PS_TIMER_A_V1(x) \ + (((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1) +#define BITS_PS_TIMER_A_V1 (BIT_MASK_PS_TIMER_A_V1 << BIT_SHIFT_PS_TIMER_A_V1) +#define BIT_CLEAR_PS_TIMER_A_V1(x) ((x) & (~BITS_PS_TIMER_A_V1)) +#define BIT_GET_PS_TIMER_A_V1(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1) +#define BIT_SET_PS_TIMER_A_V1(x, v) \ + (BIT_CLEAR_PS_TIMER_A_V1(x) | BIT_PS_TIMER_A_V1(v)) +/* 2 REG_PS_TIMER_B (Offset 0x1508) */ -#define BIT_SHIFT_AC0_PKT_INFO 0 -#define BIT_MASK_AC0_PKT_INFO 0xfff -#define BIT_AC0_PKT_INFO(x) (((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO) -#define BIT_GET_AC0_PKT_INFO(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO) +#define BIT_SHIFT_PS_TIMER_B_V1 0 +#define BIT_MASK_PS_TIMER_B_V1 0xffffffffL +#define BIT_PS_TIMER_B_V1(x) \ + (((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1) +#define BITS_PS_TIMER_B_V1 (BIT_MASK_PS_TIMER_B_V1 << BIT_SHIFT_PS_TIMER_B_V1) +#define BIT_CLEAR_PS_TIMER_B_V1(x) ((x) & (~BITS_PS_TIMER_B_V1)) +#define BIT_GET_PS_TIMER_B_V1(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1) +#define BIT_SET_PS_TIMER_B_V1(x, v) \ + (BIT_CLEAR_PS_TIMER_B_V1(x) | BIT_PS_TIMER_B_V1(v)) +/* 2 REG_PS_TIMER_C (Offset 0x150C) */ -/* 2 REG_Q2_Q3_INFO (Offset 0x1404) */ +#define BIT_SHIFT_PS_TIMER_C_V1 0 +#define BIT_MASK_PS_TIMER_C_V1 0xffffffffL +#define BIT_PS_TIMER_C_V1(x) \ + (((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1) +#define BITS_PS_TIMER_C_V1 (BIT_MASK_PS_TIMER_C_V1 << BIT_SHIFT_PS_TIMER_C_V1) +#define BIT_CLEAR_PS_TIMER_C_V1(x) ((x) & (~BITS_PS_TIMER_C_V1)) +#define BIT_GET_PS_TIMER_C_V1(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1) +#define BIT_SET_PS_TIMER_C_V1(x, v) \ + (BIT_CLEAR_PS_TIMER_C_V1(x) | BIT_PS_TIMER_C_V1(v)) +#endif -#define BIT_SHIFT_AC3_PKT_INFO 16 -#define BIT_MASK_AC3_PKT_INFO 0xfff -#define BIT_AC3_PKT_INFO(x) (((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO) -#define BIT_GET_AC3_PKT_INFO(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_TSFTR_SYNC_OFFSET_CFG (Offset 0x150C) */ -#define BIT_SHIFT_AC2_PKT_INFO 0 -#define BIT_MASK_AC2_PKT_INFO 0xfff -#define BIT_AC2_PKT_INFO(x) (((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO) -#define BIT_GET_AC2_PKT_INFO(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO) +#define BIT_SHIFT_TSFTR_SNC_OFFSET_V1 0 +#define BIT_MASK_TSFTR_SNC_OFFSET_V1 0xffffff +#define BIT_TSFTR_SNC_OFFSET_V1(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_V1) << BIT_SHIFT_TSFTR_SNC_OFFSET_V1) +#define BITS_TSFTR_SNC_OFFSET_V1 \ + (BIT_MASK_TSFTR_SNC_OFFSET_V1 << BIT_SHIFT_TSFTR_SNC_OFFSET_V1) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) ((x) & (~BITS_TSFTR_SNC_OFFSET_V1)) +#define BIT_GET_TSFTR_SNC_OFFSET_V1(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_V1) & BIT_MASK_TSFTR_SNC_OFFSET_V1) +#define BIT_SET_TSFTR_SNC_OFFSET_V1(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) | BIT_TSFTR_SNC_OFFSET_V1(v)) +/* 2 REG_TSFTR_SYNC_CTRL_CFG (Offset 0x150F) */ -/* 2 REG_Q4_Q5_INFO (Offset 0x1408) */ +#define BIT_SYNC_TSF_NOW_V1 BIT(5) +#define BIT_SYNC_TSF_ONCE BIT(4) +#define BIT_SYNC_TSF_AUTO BIT(3) +#define BIT_SHIFT_SYNC_PORT_SEL 0 +#define BIT_MASK_SYNC_PORT_SEL 0x7 +#define BIT_SYNC_PORT_SEL(x) \ + (((x) & BIT_MASK_SYNC_PORT_SEL) << BIT_SHIFT_SYNC_PORT_SEL) +#define BITS_SYNC_PORT_SEL (BIT_MASK_SYNC_PORT_SEL << BIT_SHIFT_SYNC_PORT_SEL) +#define BIT_CLEAR_SYNC_PORT_SEL(x) ((x) & (~BITS_SYNC_PORT_SEL)) +#define BIT_GET_SYNC_PORT_SEL(x) \ + (((x) >> BIT_SHIFT_SYNC_PORT_SEL) & BIT_MASK_SYNC_PORT_SEL) +#define BIT_SET_SYNC_PORT_SEL(x, v) \ + (BIT_CLEAR_SYNC_PORT_SEL(x) | BIT_SYNC_PORT_SEL(v)) + +#endif -#define BIT_SHIFT_AC5_PKT_INFO 16 -#define BIT_MASK_AC5_PKT_INFO 0xfff -#define BIT_AC5_PKT_INFO(x) (((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO) -#define BIT_GET_AC5_PKT_INFO(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL (Offset 0x1510) */ -#define BIT_SHIFT_AC4_PKT_INFO 0 -#define BIT_MASK_AC4_PKT_INFO 0xfff -#define BIT_AC4_PKT_INFO(x) (((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO) -#define BIT_GET_AC4_PKT_INFO(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO) +#define BIT_CPUMGQ_TIMER_EN BIT(31) +#define BIT_CPUMGQ_TX_EN BIT(28) + +#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24 +#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7 +#define BIT_CPUMGQ_TIMER_TSF_SEL(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) +#define BITS_CPUMGQ_TIMER_TSF_SEL \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) | BIT_CPUMGQ_TIMER_TSF_SEL(v)) + +#define BIT_PS_TIMER_C_EN BIT(23) + +#define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16 +#define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7 +#define BIT_PS_TIMER_C_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL) +#define BITS_PS_TIMER_C_TSF_SEL \ + (BIT_MASK_PS_TIMER_C_TSF_SEL << BIT_SHIFT_PS_TIMER_C_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_C_TSF_SEL)) +#define BIT_GET_PS_TIMER_C_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL) +#define BIT_SET_PS_TIMER_C_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) | BIT_PS_TIMER_C_TSF_SEL(v)) + +#define BIT_PS_TIMER_B_EN BIT(15) + +#define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8 +#define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7 +#define BIT_PS_TIMER_B_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL) +#define BITS_PS_TIMER_B_TSF_SEL \ + (BIT_MASK_PS_TIMER_B_TSF_SEL << BIT_SHIFT_PS_TIMER_B_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL)) +#define BIT_GET_PS_TIMER_B_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL) +#define BIT_SET_PS_TIMER_B_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) | BIT_PS_TIMER_B_TSF_SEL(v)) + +#define BIT_PS_TIMER_A_EN BIT(7) + +#define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0 +#define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7 +#define BIT_PS_TIMER_A_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL) +#define BITS_PS_TIMER_A_TSF_SEL \ + (BIT_MASK_PS_TIMER_A_TSF_SEL << BIT_SHIFT_PS_TIMER_A_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL)) +#define BIT_GET_PS_TIMER_A_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL) +#define BIT_SET_PS_TIMER_A_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) | BIT_PS_TIMER_A_TSF_SEL(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_BCN_SPACE_CFG (Offset 0x1510) */ + +#define BIT_SHIFT_BCN_SPACE 0 +#define BIT_MASK_BCN_SPACE 0xffff +#define BIT_BCN_SPACE(x) (((x) & BIT_MASK_BCN_SPACE) << BIT_SHIFT_BCN_SPACE) +#define BITS_BCN_SPACE (BIT_MASK_BCN_SPACE << BIT_SHIFT_BCN_SPACE) +#define BIT_CLEAR_BCN_SPACE(x) ((x) & (~BITS_BCN_SPACE)) +#define BIT_GET_BCN_SPACE(x) (((x) >> BIT_SHIFT_BCN_SPACE) & BIT_MASK_BCN_SPACE) +#define BIT_SET_BCN_SPACE(x, v) (BIT_CLEAR_BCN_SPACE(x) | BIT_BCN_SPACE(v)) + +/* 2 REG_EARLY_INT_ADJUST_CFG (Offset 0x1512) */ + +#define BIT_SHIFT_EARLY_INT_ADJUST 0 +#define BIT_MASK_EARLY_INT_ADJUST 0xffff +#define BIT_EARLY_INT_ADJUST(x) \ + (((x) & BIT_MASK_EARLY_INT_ADJUST) << BIT_SHIFT_EARLY_INT_ADJUST) +#define BITS_EARLY_INT_ADJUST \ + (BIT_MASK_EARLY_INT_ADJUST << BIT_SHIFT_EARLY_INT_ADJUST) +#define BIT_CLEAR_EARLY_INT_ADJUST(x) ((x) & (~BITS_EARLY_INT_ADJUST)) +#define BIT_GET_EARLY_INT_ADJUST(x) \ + (((x) >> BIT_SHIFT_EARLY_INT_ADJUST) & BIT_MASK_EARLY_INT_ADJUST) +#define BIT_SET_EARLY_INT_ADJUST(x, v) \ + (BIT_CLEAR_EARLY_INT_ADJUST(x) | BIT_EARLY_INT_ADJUST(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_CPUMGQ_TX_TIMER_EARLY (Offset 0x1514) */ -/* 2 REG_Q6_Q7_INFO (Offset 0x140C) */ +#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff +#define BIT_CPUMGQ_TX_TIMER_EARLY(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) +#define BITS_CPUMGQ_TX_TIMER_EARLY \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) | BIT_CPUMGQ_TX_TIMER_EARLY(v)) +/* 2 REG_PS_TIMER_A_EARLY (Offset 0x1515) */ -#define BIT_SHIFT_AC7_PKT_INFO 16 -#define BIT_MASK_AC7_PKT_INFO 0xfff -#define BIT_AC7_PKT_INFO(x) (((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO) -#define BIT_GET_AC7_PKT_INFO(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO) +#define BIT_SHIFT_PS_TIMER_A_EARLY 0 +#define BIT_MASK_PS_TIMER_A_EARLY 0xff +#define BIT_PS_TIMER_A_EARLY(x) \ + (((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY) +#define BITS_PS_TIMER_A_EARLY \ + (BIT_MASK_PS_TIMER_A_EARLY << BIT_SHIFT_PS_TIMER_A_EARLY) +#define BIT_CLEAR_PS_TIMER_A_EARLY(x) ((x) & (~BITS_PS_TIMER_A_EARLY)) +#define BIT_GET_PS_TIMER_A_EARLY(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY) +#define BIT_SET_PS_TIMER_A_EARLY(x, v) \ + (BIT_CLEAR_PS_TIMER_A_EARLY(x) | BIT_PS_TIMER_A_EARLY(v)) +/* 2 REG_PS_TIMER_B_EARLY (Offset 0x1516) */ -#define BIT_SHIFT_AC6_PKT_INFO 0 -#define BIT_MASK_AC6_PKT_INFO 0xfff -#define BIT_AC6_PKT_INFO(x) (((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO) -#define BIT_GET_AC6_PKT_INFO(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO) +#define BIT_SHIFT_PS_TIMER_B_EARLY 0 +#define BIT_MASK_PS_TIMER_B_EARLY 0xff +#define BIT_PS_TIMER_B_EARLY(x) \ + (((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY) +#define BITS_PS_TIMER_B_EARLY \ + (BIT_MASK_PS_TIMER_B_EARLY << BIT_SHIFT_PS_TIMER_B_EARLY) +#define BIT_CLEAR_PS_TIMER_B_EARLY(x) ((x) & (~BITS_PS_TIMER_B_EARLY)) +#define BIT_GET_PS_TIMER_B_EARLY(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY) +#define BIT_SET_PS_TIMER_B_EARLY(x, v) \ + (BIT_CLEAR_PS_TIMER_B_EARLY(x) | BIT_PS_TIMER_B_EARLY(v)) +/* 2 REG_PS_TIMER_C_EARLY (Offset 0x1517) */ -/* 2 REG_MGQ_HIQ_INFO (Offset 0x1410) */ +#define BIT_SHIFT_PS_TIMER_C_EARLY 0 +#define BIT_MASK_PS_TIMER_C_EARLY 0xff +#define BIT_PS_TIMER_C_EARLY(x) \ + (((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY) +#define BITS_PS_TIMER_C_EARLY \ + (BIT_MASK_PS_TIMER_C_EARLY << BIT_SHIFT_PS_TIMER_C_EARLY) +#define BIT_CLEAR_PS_TIMER_C_EARLY(x) ((x) & (~BITS_PS_TIMER_C_EARLY)) +#define BIT_GET_PS_TIMER_C_EARLY(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY) +#define BIT_SET_PS_TIMER_C_EARLY(x, v) \ + (BIT_CLEAR_PS_TIMER_C_EARLY(x) | BIT_PS_TIMER_C_EARLY(v)) +#endif -#define BIT_SHIFT_HIQ_PKT_INFO 16 -#define BIT_MASK_HIQ_PKT_INFO 0xfff -#define BIT_HIQ_PKT_INFO(x) (((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO) -#define BIT_GET_HIQ_PKT_INFO(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) +/* 2 REG_CPUMGQ_PARAMETER (Offset 0x1518) */ -#define BIT_SHIFT_MGQ_PKT_INFO 0 -#define BIT_MASK_MGQ_PKT_INFO 0xfff -#define BIT_MGQ_PKT_INFO(x) (((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO) -#define BIT_GET_MGQ_PKT_INFO(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO) +#define BIT_STOP_CPUMGQ BIT(16) +#define BIT_SHIFT_CPUMGQ_PARAMETER 0 +#define BIT_MASK_CPUMGQ_PARAMETER 0xffff +#define BIT_CPUMGQ_PARAMETER(x) \ + (((x) & BIT_MASK_CPUMGQ_PARAMETER) << BIT_SHIFT_CPUMGQ_PARAMETER) +#define BITS_CPUMGQ_PARAMETER \ + (BIT_MASK_CPUMGQ_PARAMETER << BIT_SHIFT_CPUMGQ_PARAMETER) +#define BIT_CLEAR_CPUMGQ_PARAMETER(x) ((x) & (~BITS_CPUMGQ_PARAMETER)) +#define BIT_GET_CPUMGQ_PARAMETER(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER) & BIT_MASK_CPUMGQ_PARAMETER) +#define BIT_SET_CPUMGQ_PARAMETER(x, v) \ + (BIT_CLEAR_CPUMGQ_PARAMETER(x) | BIT_CPUMGQ_PARAMETER(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) +/* 2 REG_SW_TBTT_TSF_INFO (Offset 0x151C) */ +#define BIT_SHIFT_SW_TBTT_TSF_INFO 0 +#define BIT_MASK_SW_TBTT_TSF_INFO 0xffffffffL +#define BIT_SW_TBTT_TSF_INFO(x) \ + (((x) & BIT_MASK_SW_TBTT_TSF_INFO) << BIT_SHIFT_SW_TBTT_TSF_INFO) +#define BITS_SW_TBTT_TSF_INFO \ + (BIT_MASK_SW_TBTT_TSF_INFO << BIT_SHIFT_SW_TBTT_TSF_INFO) +#define BIT_CLEAR_SW_TBTT_TSF_INFO(x) ((x) & (~BITS_SW_TBTT_TSF_INFO)) +#define BIT_GET_SW_TBTT_TSF_INFO(x) \ + (((x) >> BIT_SHIFT_SW_TBTT_TSF_INFO) & BIT_MASK_SW_TBTT_TSF_INFO) +#define BIT_SET_SW_TBTT_TSF_INFO(x, v) \ + (BIT_CLEAR_SW_TBTT_TSF_INFO(x) | BIT_SW_TBTT_TSF_INFO(v)) -/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */ -#define BIT_SHIFT_BCNQ_PKT_INFO_V1 16 -#define BIT_MASK_BCNQ_PKT_INFO_V1 0xfff -#define BIT_BCNQ_PKT_INFO_V1(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_V1) << BIT_SHIFT_BCNQ_PKT_INFO_V1) -#define BIT_GET_BCNQ_PKT_INFO_V1(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1) & BIT_MASK_BCNQ_PKT_INFO_V1) +#define BIT_SHIFT_R_P0_TSFT_ADJ_VAL 16 +#define BIT_MASK_R_P0_TSFT_ADJ_VAL 0xffff +#define BIT_R_P0_TSFT_ADJ_VAL(x) \ + (((x) & BIT_MASK_R_P0_TSFT_ADJ_VAL) << BIT_SHIFT_R_P0_TSFT_ADJ_VAL) +#define BITS_R_P0_TSFT_ADJ_VAL \ + (BIT_MASK_R_P0_TSFT_ADJ_VAL << BIT_SHIFT_R_P0_TSFT_ADJ_VAL) +#define BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_P0_TSFT_ADJ_VAL)) +#define BIT_GET_R_P0_TSFT_ADJ_VAL(x) \ + (((x) >> BIT_SHIFT_R_P0_TSFT_ADJ_VAL) & BIT_MASK_R_P0_TSFT_ADJ_VAL) +#define BIT_SET_R_P0_TSFT_ADJ_VAL(x, v) \ + (BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) | BIT_R_P0_TSFT_ADJ_VAL(v)) +#define BIT_R_X_COMP_Y_OVER BIT(8) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TSF_SYN_CTRL0 (Offset 0x1520) */ +#define BIT_TSF_SYNC_COMPARE_POLLING BIT(7) +#define BIT_TSF_SYNC_POLLING BIT(6) -/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +#define BIT_SHIFT_TSF_SYNC_DUT 3 +#define BIT_MASK_TSF_SYNC_DUT 0x7 +#define BIT_TSF_SYNC_DUT(x) \ + (((x) & BIT_MASK_TSF_SYNC_DUT) << BIT_SHIFT_TSF_SYNC_DUT) +#define BITS_TSF_SYNC_DUT (BIT_MASK_TSF_SYNC_DUT << BIT_SHIFT_TSF_SYNC_DUT) +#define BIT_CLEAR_TSF_SYNC_DUT(x) ((x) & (~BITS_TSF_SYNC_DUT)) +#define BIT_GET_TSF_SYNC_DUT(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_DUT) & BIT_MASK_TSF_SYNC_DUT) +#define BIT_SET_TSF_SYNC_DUT(x, v) \ + (BIT_CLEAR_TSF_SYNC_DUT(x) | BIT_TSF_SYNC_DUT(v)) + +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_CMDQ_PKT_INFO 16 -#define BIT_MASK_CMDQ_PKT_INFO 0xfff -#define BIT_CMDQ_PKT_INFO(x) (((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO) -#define BIT_GET_CMDQ_PKT_INFO(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO) +/* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */ +#define BIT_SHIFT_R_X_SYNC_SEL 3 +#define BIT_MASK_R_X_SYNC_SEL 0x7 +#define BIT_R_X_SYNC_SEL(x) \ + (((x) & BIT_MASK_R_X_SYNC_SEL) << BIT_SHIFT_R_X_SYNC_SEL) +#define BITS_R_X_SYNC_SEL (BIT_MASK_R_X_SYNC_SEL << BIT_SHIFT_R_X_SYNC_SEL) +#define BIT_CLEAR_R_X_SYNC_SEL(x) ((x) & (~BITS_R_X_SYNC_SEL)) +#define BIT_GET_R_X_SYNC_SEL(x) \ + (((x) >> BIT_SHIFT_R_X_SYNC_SEL) & BIT_MASK_R_X_SYNC_SEL) +#define BIT_SET_R_X_SYNC_SEL(x, v) \ + (BIT_CLEAR_R_X_SYNC_SEL(x) | BIT_R_X_SYNC_SEL(v)) #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - +/* 2 REG_TSF_SYN_CTRL0 (Offset 0x1520) */ -/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +#define BIT_SHIFT_TSF_SYNC_SOURCE 0 +#define BIT_MASK_TSF_SYNC_SOURCE 0x7 +#define BIT_TSF_SYNC_SOURCE(x) \ + (((x) & BIT_MASK_TSF_SYNC_SOURCE) << BIT_SHIFT_TSF_SYNC_SOURCE) +#define BITS_TSF_SYNC_SOURCE \ + (BIT_MASK_TSF_SYNC_SOURCE << BIT_SHIFT_TSF_SYNC_SOURCE) +#define BIT_CLEAR_TSF_SYNC_SOURCE(x) ((x) & (~BITS_TSF_SYNC_SOURCE)) +#define BIT_GET_TSF_SYNC_SOURCE(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_SOURCE) & BIT_MASK_TSF_SYNC_SOURCE) +#define BIT_SET_TSF_SYNC_SOURCE(x, v) \ + (BIT_CLEAR_TSF_SYNC_SOURCE(x) | BIT_TSF_SYNC_SOURCE(v)) -#define BIT_CHNL_REF_RXNAV BIT(7) -#define BIT_CHNL_REF_VBON BIT(6) -#define BIT_CHNL_REF_EDCCA BIT(5) -#define BIT_RST_CHNL_BUSY BIT(3) -#define BIT_RST_CHNL_IDLE BIT(2) -#define BIT_CHNL_INFO_RST BIT(1) +#define BIT_TSF_SYNC_SIGNAL BIT(0) -#define BIT_SHIFT_CMDQ_PKT_INFO_V1 0 -#define BIT_MASK_CMDQ_PKT_INFO_V1 0xfff -#define BIT_CMDQ_PKT_INFO_V1(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_V1) << BIT_SHIFT_CMDQ_PKT_INFO_V1) -#define BIT_GET_CMDQ_PKT_INFO_V1(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1) & BIT_MASK_CMDQ_PKT_INFO_V1) +#endif -#define BIT_ATM_AIRTIME_EN BIT(0) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_CHNL_IDLE_TIME 0 -#define BIT_MASK_CHNL_IDLE_TIME 0xffffffffL -#define BIT_CHNL_IDLE_TIME(x) (((x) & BIT_MASK_CHNL_IDLE_TIME) << BIT_SHIFT_CHNL_IDLE_TIME) -#define BIT_GET_CHNL_IDLE_TIME(x) (((x) >> BIT_SHIFT_CHNL_IDLE_TIME) & BIT_MASK_CHNL_IDLE_TIME) +/* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */ +#define BIT_SHIFT_R_SYNC_Y_SEL 0 +#define BIT_MASK_R_SYNC_Y_SEL 0x7 +#define BIT_R_SYNC_Y_SEL(x) \ + (((x) & BIT_MASK_R_SYNC_Y_SEL) << BIT_SHIFT_R_SYNC_Y_SEL) +#define BITS_R_SYNC_Y_SEL (BIT_MASK_R_SYNC_Y_SEL << BIT_SHIFT_R_SYNC_Y_SEL) +#define BIT_CLEAR_R_SYNC_Y_SEL(x) ((x) & (~BITS_R_SYNC_Y_SEL)) +#define BIT_GET_R_SYNC_Y_SEL(x) \ + (((x) >> BIT_SHIFT_R_SYNC_Y_SEL) & BIT_MASK_R_SYNC_Y_SEL) +#define BIT_SET_R_SYNC_Y_SEL(x, v) \ + (BIT_CLEAR_R_SYNC_Y_SEL(x) | BIT_R_SYNC_Y_SEL(v)) -#define BIT_SHIFT_CHNL_BUSY_TIME 0 -#define BIT_MASK_CHNL_BUSY_TIME 0xffffffffL -#define BIT_CHNL_BUSY_TIME(x) (((x) & BIT_MASK_CHNL_BUSY_TIME) << BIT_SHIFT_CHNL_BUSY_TIME) -#define BIT_GET_CHNL_BUSY_TIME(x) (((x) >> BIT_SHIFT_CHNL_BUSY_TIME) & BIT_MASK_CHNL_BUSY_TIME) +#endif +#if (HALMAC_8814B_SUPPORT) -#endif +/* 2 REG_TSFTR_LOW (Offset 0x1520) */ +#define BIT_SHIFT_TSF_TIMER_LOW 0 +#define BIT_MASK_TSF_TIMER_LOW 0xffffffffL +#define BIT_TSF_TIMER_LOW(x) \ + (((x) & BIT_MASK_TSF_TIMER_LOW) << BIT_SHIFT_TSF_TIMER_LOW) +#define BITS_TSF_TIMER_LOW (BIT_MASK_TSF_TIMER_LOW << BIT_SHIFT_TSF_TIMER_LOW) +#define BIT_CLEAR_TSF_TIMER_LOW(x) ((x) & (~BITS_TSF_TIMER_LOW)) +#define BIT_GET_TSF_TIMER_LOW(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_LOW) & BIT_MASK_TSF_TIMER_LOW) +#define BIT_SET_TSF_TIMER_LOW(x, v) \ + (BIT_CLEAR_TSF_TIMER_LOW(x) | BIT_TSF_TIMER_LOW(v)) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ +/* 2 REG_TSF_SYN_OFFSET0 (Offset 0x1522) */ +#define BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0 0 +#define BIT_MASK_TSF_SYNC_INTERVAL_PORT0 0xffff +#define BIT_TSF_SYNC_INTERVAL_PORT0(x) \ + (((x) & BIT_MASK_TSF_SYNC_INTERVAL_PORT0) \ + << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) +#define BITS_TSF_SYNC_INTERVAL_PORT0 \ + (BIT_MASK_TSF_SYNC_INTERVAL_PORT0 << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) +#define BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x) \ + ((x) & (~BITS_TSF_SYNC_INTERVAL_PORT0)) +#define BIT_GET_TSF_SYNC_INTERVAL_PORT0(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) & \ + BIT_MASK_TSF_SYNC_INTERVAL_PORT0) +#define BIT_SET_TSF_SYNC_INTERVAL_PORT0(x, v) \ + (BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x) | BIT_TSF_SYNC_INTERVAL_PORT0(v)) -#define BIT_SHIFT_BCNQ_PKT_INFO 0 -#define BIT_MASK_BCNQ_PKT_INFO 0xfff -#define BIT_BCNQ_PKT_INFO(x) (((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO) -#define BIT_GET_BCNQ_PKT_INFO(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO) +/* 2 REG_TSF_SYN_OFFSET1 (Offset 0x1524) */ +#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1 16 +#define BIT_MASK_TSF_SYNC_INTERVAL_CLI1 0xffff +#define BIT_TSF_SYNC_INTERVAL_CLI1(x) \ + (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI1) \ + << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) +#define BITS_TSF_SYNC_INTERVAL_CLI1 \ + (BIT_MASK_TSF_SYNC_INTERVAL_CLI1 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) +#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x) \ + ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI1)) +#define BIT_GET_TSF_SYNC_INTERVAL_CLI1(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) & \ + BIT_MASK_TSF_SYNC_INTERVAL_CLI1) +#define BIT_SET_TSF_SYNC_INTERVAL_CLI1(x, v) \ + (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x) | BIT_TSF_SYNC_INTERVAL_CLI1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_TSF_ADJ_VLAUE (Offset 0x1524) */ -/* 2 REG_USEREG_SETTING (Offset 0x1420) */ +#define BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL 16 +#define BIT_MASK_R_CLI1_TSFT_ADJ_VAL 0xffff +#define BIT_R_CLI1_TSFT_ADJ_VAL(x) \ + (((x) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) +#define BITS_R_CLI1_TSFT_ADJ_VAL \ + (BIT_MASK_R_CLI1_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) +#define BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI1_TSFT_ADJ_VAL)) +#define BIT_GET_R_CLI1_TSFT_ADJ_VAL(x) \ + (((x) >> BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL) +#define BIT_SET_R_CLI1_TSFT_ADJ_VAL(x, v) \ + (BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) | BIT_R_CLI1_TSFT_ADJ_VAL(v)) -#define BIT_NDPA_USEREG BIT(21) +#endif -#define BIT_SHIFT_RETRY_USEREG 19 -#define BIT_MASK_RETRY_USEREG 0x3 -#define BIT_RETRY_USEREG(x) (((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG) -#define BIT_GET_RETRY_USEREG(x) (((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG) +#if (HALMAC_8198F_SUPPORT) +/* 2 REG_TSF_SYN_OFFSET1 (Offset 0x1524) */ -#define BIT_SHIFT_TRYPKT_USEREG 17 -#define BIT_MASK_TRYPKT_USEREG 0x3 -#define BIT_TRYPKT_USEREG(x) (((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG) -#define BIT_GET_TRYPKT_USEREG(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG) +#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0 0 +#define BIT_MASK_TSF_SYNC_INTERVAL_CLI0 0xffff +#define BIT_TSF_SYNC_INTERVAL_CLI0(x) \ + (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI0) \ + << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) +#define BITS_TSF_SYNC_INTERVAL_CLI0 \ + (BIT_MASK_TSF_SYNC_INTERVAL_CLI0 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) +#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x) \ + ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI0)) +#define BIT_GET_TSF_SYNC_INTERVAL_CLI0(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) & \ + BIT_MASK_TSF_SYNC_INTERVAL_CLI0) +#define BIT_SET_TSF_SYNC_INTERVAL_CLI0(x, v) \ + (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x) | BIT_TSF_SYNC_INTERVAL_CLI0(v)) -#define BIT_CTLPKT_USEREG BIT(16) +#endif -/* 2 REG_AESIV_SETTING (Offset 0x1424) */ +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TSF_ADJ_VLAUE (Offset 0x1524) */ -#define BIT_SHIFT_AESIV_OFFSET 0 -#define BIT_MASK_AESIV_OFFSET 0xfff -#define BIT_AESIV_OFFSET(x) (((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET) -#define BIT_GET_AESIV_OFFSET(x) (((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET) +#define BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL 0 +#define BIT_MASK_R_CLI0_TSFT_ADJ_VAL 0xffff +#define BIT_R_CLI0_TSFT_ADJ_VAL(x) \ + (((x) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) +#define BITS_R_CLI0_TSFT_ADJ_VAL \ + (BIT_MASK_R_CLI0_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) +#define BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI0_TSFT_ADJ_VAL)) +#define BIT_GET_R_CLI0_TSFT_ADJ_VAL(x) \ + (((x) >> BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL) +#define BIT_SET_R_CLI0_TSFT_ADJ_VAL(x, v) \ + (BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) | BIT_R_CLI0_TSFT_ADJ_VAL(v)) +#endif -/* 2 REG_BF0_TIME_SETTING (Offset 0x1428) */ +#if (HALMAC_8814B_SUPPORT) -#define BIT_BF0_TIMER_SET BIT(31) -#define BIT_BF0_TIMER_CLR BIT(30) -#define BIT_BF0_UPDATE_EN BIT(29) -#define BIT_BF0_TIMER_EN BIT(28) +/* 2 REG_TSFTR_HIGH (Offset 0x1524) */ -#define BIT_SHIFT_BF0_PRETIME_OVER 16 -#define BIT_MASK_BF0_PRETIME_OVER 0xfff -#define BIT_BF0_PRETIME_OVER(x) (((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER) -#define BIT_GET_BF0_PRETIME_OVER(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER) +#define BIT_SHIFT_TSF_TIMER_HIGH 0 +#define BIT_MASK_TSF_TIMER_HIGH 0xffffffffL +#define BIT_TSF_TIMER_HIGH(x) \ + (((x) & BIT_MASK_TSF_TIMER_HIGH) << BIT_SHIFT_TSF_TIMER_HIGH) +#define BITS_TSF_TIMER_HIGH \ + (BIT_MASK_TSF_TIMER_HIGH << BIT_SHIFT_TSF_TIMER_HIGH) +#define BIT_CLEAR_TSF_TIMER_HIGH(x) ((x) & (~BITS_TSF_TIMER_HIGH)) +#define BIT_GET_TSF_TIMER_HIGH(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_HIGH) & BIT_MASK_TSF_TIMER_HIGH) +#define BIT_SET_TSF_TIMER_HIGH(x, v) \ + (BIT_CLEAR_TSF_TIMER_HIGH(x) | BIT_TSF_TIMER_HIGH(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_TSF_SYN_OFFSET2 (Offset 0x1528) */ + +#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3 16 +#define BIT_MASK_TSF_SYNC_INTERVAL_CLI3 0xffff +#define BIT_TSF_SYNC_INTERVAL_CLI3(x) \ + (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI3) \ + << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) +#define BITS_TSF_SYNC_INTERVAL_CLI3 \ + (BIT_MASK_TSF_SYNC_INTERVAL_CLI3 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) +#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x) \ + ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI3)) +#define BIT_GET_TSF_SYNC_INTERVAL_CLI3(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) & \ + BIT_MASK_TSF_SYNC_INTERVAL_CLI3) +#define BIT_SET_TSF_SYNC_INTERVAL_CLI3(x, v) \ + (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x) | BIT_TSF_SYNC_INTERVAL_CLI3(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_TSF_ADJ_VLAUE_2 (Offset 0x1528) */ + +#define BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL 16 +#define BIT_MASK_R_CLI3_TSFT_ADJ_VAL 0xffff +#define BIT_R_CLI3_TSFT_ADJ_VAL(x) \ + (((x) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) +#define BITS_R_CLI3_TSFT_ADJ_VAL \ + (BIT_MASK_R_CLI3_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) +#define BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI3_TSFT_ADJ_VAL)) +#define BIT_GET_R_CLI3_TSFT_ADJ_VAL(x) \ + (((x) >> BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL) +#define BIT_SET_R_CLI3_TSFT_ADJ_VAL(x, v) \ + (BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) | BIT_R_CLI3_TSFT_ADJ_VAL(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_TSF_SYN_OFFSET2 (Offset 0x1528) */ + +#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2 0 +#define BIT_MASK_TSF_SYNC_INTERVAL_CLI2 0xffff +#define BIT_TSF_SYNC_INTERVAL_CLI2(x) \ + (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI2) \ + << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) +#define BITS_TSF_SYNC_INTERVAL_CLI2 \ + (BIT_MASK_TSF_SYNC_INTERVAL_CLI2 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) +#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x) \ + ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI2)) +#define BIT_GET_TSF_SYNC_INTERVAL_CLI2(x) \ + (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) & \ + BIT_MASK_TSF_SYNC_INTERVAL_CLI2) +#define BIT_SET_TSF_SYNC_INTERVAL_CLI2(x, v) \ + (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x) | BIT_TSF_SYNC_INTERVAL_CLI2(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_TSF_ADJ_VLAUE_2 (Offset 0x1528) */ + +#define BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL 0 +#define BIT_MASK_R_CLI2_TSFT_ADJ_VAL 0xffff +#define BIT_R_CLI2_TSFT_ADJ_VAL(x) \ + (((x) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) +#define BITS_R_CLI2_TSFT_ADJ_VAL \ + (BIT_MASK_R_CLI2_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) +#define BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI2_TSFT_ADJ_VAL)) +#define BIT_GET_R_CLI2_TSFT_ADJ_VAL(x) \ + (((x) >> BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL) +#define BIT_SET_R_CLI2_TSFT_ADJ_VAL(x, v) \ + (BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) | BIT_R_CLI2_TSFT_ADJ_VAL(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_BCN_ERR_CNT_MAC (Offset 0x1528) */ + +#define BIT_SHIFT_BCN_ERR_CNT_MAC 0 +#define BIT_MASK_BCN_ERR_CNT_MAC 0xff +#define BIT_BCN_ERR_CNT_MAC(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_MAC) << BIT_SHIFT_BCN_ERR_CNT_MAC) +#define BITS_BCN_ERR_CNT_MAC \ + (BIT_MASK_BCN_ERR_CNT_MAC << BIT_SHIFT_BCN_ERR_CNT_MAC) +#define BIT_CLEAR_BCN_ERR_CNT_MAC(x) ((x) & (~BITS_BCN_ERR_CNT_MAC)) +#define BIT_GET_BCN_ERR_CNT_MAC(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_MAC) & BIT_MASK_BCN_ERR_CNT_MAC) +#define BIT_SET_BCN_ERR_CNT_MAC(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_MAC(x) | BIT_BCN_ERR_CNT_MAC(v)) + +/* 2 REG_BCN_ERR_CNT_EDCCA (Offset 0x1529) */ + +#define BIT_SHIFT_BCN_ERR_CNT_EDCCA 0 +#define BIT_MASK_BCN_ERR_CNT_EDCCA 0xff +#define BIT_BCN_ERR_CNT_EDCCA(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_EDCCA) << BIT_SHIFT_BCN_ERR_CNT_EDCCA) +#define BITS_BCN_ERR_CNT_EDCCA \ + (BIT_MASK_BCN_ERR_CNT_EDCCA << BIT_SHIFT_BCN_ERR_CNT_EDCCA) +#define BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) ((x) & (~BITS_BCN_ERR_CNT_EDCCA)) +#define BIT_GET_BCN_ERR_CNT_EDCCA(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_EDCCA) & BIT_MASK_BCN_ERR_CNT_EDCCA) +#define BIT_SET_BCN_ERR_CNT_EDCCA(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) | BIT_BCN_ERR_CNT_EDCCA(v)) + +/* 2 REG_BCN_ERR_CNT_CCA (Offset 0x152A) */ + +#define BIT_SHIFT_BCN_ERR_CNT_CCA 0 +#define BIT_MASK_BCN_ERR_CNT_CCA 0xff +#define BIT_BCN_ERR_CNT_CCA(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_CCA) << BIT_SHIFT_BCN_ERR_CNT_CCA) +#define BITS_BCN_ERR_CNT_CCA \ + (BIT_MASK_BCN_ERR_CNT_CCA << BIT_SHIFT_BCN_ERR_CNT_CCA) +#define BIT_CLEAR_BCN_ERR_CNT_CCA(x) ((x) & (~BITS_BCN_ERR_CNT_CCA)) +#define BIT_GET_BCN_ERR_CNT_CCA(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_CCA) & BIT_MASK_BCN_ERR_CNT_CCA) +#define BIT_SET_BCN_ERR_CNT_CCA(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_CCA(x) | BIT_BCN_ERR_CNT_CCA(v)) + +/* 2 REG_BCN_ERR_CNT_INVALID (Offset 0x152B) */ + +#define BIT_SHIFT_BCN_ERR_CNT_INVALID 0 +#define BIT_MASK_BCN_ERR_CNT_INVALID 0xff +#define BIT_BCN_ERR_CNT_INVALID(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_INVALID) << BIT_SHIFT_BCN_ERR_CNT_INVALID) +#define BITS_BCN_ERR_CNT_INVALID \ + (BIT_MASK_BCN_ERR_CNT_INVALID << BIT_SHIFT_BCN_ERR_CNT_INVALID) +#define BIT_CLEAR_BCN_ERR_CNT_INVALID(x) ((x) & (~BITS_BCN_ERR_CNT_INVALID)) +#define BIT_GET_BCN_ERR_CNT_INVALID(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_INVALID) & BIT_MASK_BCN_ERR_CNT_INVALID) +#define BIT_SET_BCN_ERR_CNT_INVALID(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_INVALID(x) | BIT_BCN_ERR_CNT_INVALID(v)) + +/* 2 REG_BCN_ERR_CNT_OTHERS (Offset 0x152C) */ + +#define BIT_SHIFT_BCN_ERR_CNT_OTHERS 0 +#define BIT_MASK_BCN_ERR_CNT_OTHERS 0xff +#define BIT_BCN_ERR_CNT_OTHERS(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_OTHERS) << BIT_SHIFT_BCN_ERR_CNT_OTHERS) +#define BITS_BCN_ERR_CNT_OTHERS \ + (BIT_MASK_BCN_ERR_CNT_OTHERS << BIT_SHIFT_BCN_ERR_CNT_OTHERS) +#define BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) ((x) & (~BITS_BCN_ERR_CNT_OTHERS)) +#define BIT_GET_BCN_ERR_CNT_OTHERS(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_OTHERS) & BIT_MASK_BCN_ERR_CNT_OTHERS) +#define BIT_SET_BCN_ERR_CNT_OTHERS(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) | BIT_BCN_ERR_CNT_OTHERS(v)) + +/* 2 REG_RX_BCN_TIMER (Offset 0x152D) */ + +#define BIT_SHIFT_RX_BCN_TIMER 0 +#define BIT_MASK_RX_BCN_TIMER 0xffff +#define BIT_RX_BCN_TIMER(x) \ + (((x) & BIT_MASK_RX_BCN_TIMER) << BIT_SHIFT_RX_BCN_TIMER) +#define BITS_RX_BCN_TIMER (BIT_MASK_RX_BCN_TIMER << BIT_SHIFT_RX_BCN_TIMER) +#define BIT_CLEAR_RX_BCN_TIMER(x) ((x) & (~BITS_RX_BCN_TIMER)) +#define BIT_GET_RX_BCN_TIMER(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TIMER) & BIT_MASK_RX_BCN_TIMER) +#define BIT_SET_RX_BCN_TIMER(x, v) \ + (BIT_CLEAR_RX_BCN_TIMER(x) | BIT_RX_BCN_TIMER(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/* 2 REG_TSF_SYN_COMPARE_VALUE (Offset 0x1530) */ + +#define BIT_SHIFT_TSF_SYN_COMPARE_VALUE 0 +#define BIT_MASK_TSF_SYN_COMPARE_VALUE 0xffffffffffffffffL +#define BIT_TSF_SYN_COMPARE_VALUE(x) \ + (((x) & BIT_MASK_TSF_SYN_COMPARE_VALUE) \ + << BIT_SHIFT_TSF_SYN_COMPARE_VALUE) +#define BITS_TSF_SYN_COMPARE_VALUE \ + (BIT_MASK_TSF_SYN_COMPARE_VALUE << BIT_SHIFT_TSF_SYN_COMPARE_VALUE) +#define BIT_CLEAR_TSF_SYN_COMPARE_VALUE(x) ((x) & (~BITS_TSF_SYN_COMPARE_VALUE)) +#define BIT_GET_TSF_SYN_COMPARE_VALUE(x) \ + (((x) >> BIT_SHIFT_TSF_SYN_COMPARE_VALUE) & \ + BIT_MASK_TSF_SYN_COMPARE_VALUE) +#define BIT_SET_TSF_SYN_COMPARE_VALUE(x, v) \ + (BIT_CLEAR_TSF_SYN_COMPARE_VALUE(x) | BIT_TSF_SYN_COMPARE_VALUE(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_SUB_BCN_SPACE (Offset 0x1534) */ + +#define BIT_SHIFT_SUB_BCN_SPACE_V2 0 +#define BIT_MASK_SUB_BCN_SPACE_V2 0xff +#define BIT_SUB_BCN_SPACE_V2(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_V2) << BIT_SHIFT_SUB_BCN_SPACE_V2) +#define BITS_SUB_BCN_SPACE_V2 \ + (BIT_MASK_SUB_BCN_SPACE_V2 << BIT_SHIFT_SUB_BCN_SPACE_V2) +#define BIT_CLEAR_SUB_BCN_SPACE_V2(x) ((x) & (~BITS_SUB_BCN_SPACE_V2)) +#define BIT_GET_SUB_BCN_SPACE_V2(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V2) & BIT_MASK_SUB_BCN_SPACE_V2) +#define BIT_SET_SUB_BCN_SPACE_V2(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_V2(x) | BIT_SUB_BCN_SPACE_V2(v)) + +/* 2 REG_MBID_NUM_V1 (Offset 0x1535) */ + +#define BIT_SHIFT_BCN_ERR_PORT_SEL 4 +#define BIT_MASK_BCN_ERR_PORT_SEL 0xf +#define BIT_BCN_ERR_PORT_SEL(x) \ + (((x) & BIT_MASK_BCN_ERR_PORT_SEL) << BIT_SHIFT_BCN_ERR_PORT_SEL) +#define BITS_BCN_ERR_PORT_SEL \ + (BIT_MASK_BCN_ERR_PORT_SEL << BIT_SHIFT_BCN_ERR_PORT_SEL) +#define BIT_CLEAR_BCN_ERR_PORT_SEL(x) ((x) & (~BITS_BCN_ERR_PORT_SEL)) +#define BIT_GET_BCN_ERR_PORT_SEL(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_PORT_SEL) & BIT_MASK_BCN_ERR_PORT_SEL) +#define BIT_SET_BCN_ERR_PORT_SEL(x, v) \ + (BIT_CLEAR_BCN_ERR_PORT_SEL(x) | BIT_BCN_ERR_PORT_SEL(v)) + +#define BIT_SHIFT_MBID_BCN_NUM_V1 0 +#define BIT_MASK_MBID_BCN_NUM_V1 0xf +#define BIT_MBID_BCN_NUM_V1(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_V1) << BIT_SHIFT_MBID_BCN_NUM_V1) +#define BITS_MBID_BCN_NUM_V1 \ + (BIT_MASK_MBID_BCN_NUM_V1 << BIT_SHIFT_MBID_BCN_NUM_V1) +#define BIT_CLEAR_MBID_BCN_NUM_V1(x) ((x) & (~BITS_MBID_BCN_NUM_V1)) +#define BIT_GET_MBID_BCN_NUM_V1(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_V1) & BIT_MASK_MBID_BCN_NUM_V1) +#define BIT_SET_MBID_BCN_NUM_V1(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_V1(x) | BIT_MBID_BCN_NUM_V1(v)) + +/* 2 REG_MBSSID_CTRL_V1 (Offset 0x1536) */ + +#define BIT_MBID_BCNQ15_EN BIT(15) +#define BIT_MBID_BCNQ14_EN BIT(14) +#define BIT_MBID_BCNQ13_EN BIT(13) +#define BIT_MBID_BCNQ12_EN BIT(12) +#define BIT_MBID_BCNQ11_EN BIT(11) +#define BIT_MBID_BCNQ10_EN BIT(10) +#define BIT_MBID_BCNQ9_EN BIT(9) +#define BIT_MBID_BCNQ8_EN BIT(8) + +/* 2 REG_BW_CFG (Offset 0x1539) */ + +#define BIT_SLEEP_32K_EN BIT(3) +#define BIT_DIS_MARK_TSF_US_V1 BIT(2) + +/* 2 REG_ATIMWND_CFG (Offset 0x153A) */ + +#define BIT_SHIFT_ATIMWND_V1 0 +#define BIT_MASK_ATIMWND_V1 0xff +#define BIT_ATIMWND_V1(x) (((x) & BIT_MASK_ATIMWND_V1) << BIT_SHIFT_ATIMWND_V1) +#define BITS_ATIMWND_V1 (BIT_MASK_ATIMWND_V1 << BIT_SHIFT_ATIMWND_V1) +#define BIT_CLEAR_ATIMWND_V1(x) ((x) & (~BITS_ATIMWND_V1)) +#define BIT_GET_ATIMWND_V1(x) \ + (((x) >> BIT_SHIFT_ATIMWND_V1) & BIT_MASK_ATIMWND_V1) +#define BIT_SET_ATIMWND_V1(x, v) (BIT_CLEAR_ATIMWND_V1(x) | BIT_ATIMWND_V1(v)) + +/* 2 REG_DTIM_COUNTER_CFG (Offset 0x153B) */ + +#define BIT_SHIFT_DTIM_COUNT 0 +#define BIT_MASK_DTIM_COUNT 0xff +#define BIT_DTIM_COUNT(x) (((x) & BIT_MASK_DTIM_COUNT) << BIT_SHIFT_DTIM_COUNT) +#define BITS_DTIM_COUNT (BIT_MASK_DTIM_COUNT << BIT_SHIFT_DTIM_COUNT) +#define BIT_CLEAR_DTIM_COUNT(x) ((x) & (~BITS_DTIM_COUNT)) +#define BIT_GET_DTIM_COUNT(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT) & BIT_MASK_DTIM_COUNT) +#define BIT_SET_DTIM_COUNT(x, v) (BIT_CLEAR_DTIM_COUNT(x) | BIT_DTIM_COUNT(v)) + +/* 2 REG_ATIM_DTIM_CTRL_SEL (Offset 0x153C) */ + +#define BIT_DTIM_BYPASS_V1 BIT(7) + +#define BIT_SHIFT_ATIM_DTIM_SEL 0 +#define BIT_MASK_ATIM_DTIM_SEL 0x1f +#define BIT_ATIM_DTIM_SEL(x) \ + (((x) & BIT_MASK_ATIM_DTIM_SEL) << BIT_SHIFT_ATIM_DTIM_SEL) +#define BITS_ATIM_DTIM_SEL (BIT_MASK_ATIM_DTIM_SEL << BIT_SHIFT_ATIM_DTIM_SEL) +#define BIT_CLEAR_ATIM_DTIM_SEL(x) ((x) & (~BITS_ATIM_DTIM_SEL)) +#define BIT_GET_ATIM_DTIM_SEL(x) \ + (((x) >> BIT_SHIFT_ATIM_DTIM_SEL) & BIT_MASK_ATIM_DTIM_SEL) +#define BIT_SET_ATIM_DTIM_SEL(x, v) \ + (BIT_CLEAR_ATIM_DTIM_SEL(x) | BIT_ATIM_DTIM_SEL(v)) + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +/* 2 REG_ATIMUGT_V1 (Offset 0x153D) */ + +#define BIT_SHIFT_ATIM_URGENT 0 +#define BIT_MASK_ATIM_URGENT 0xff +#define BIT_ATIM_URGENT(x) \ + (((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT) +#define BITS_ATIM_URGENT (BIT_MASK_ATIM_URGENT << BIT_SHIFT_ATIM_URGENT) +#define BIT_CLEAR_ATIM_URGENT(x) ((x) & (~BITS_ATIM_URGENT)) +#define BIT_GET_ATIM_URGENT(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT) +#define BIT_SET_ATIM_URGENT(x, v) \ + (BIT_CLEAR_ATIM_URGENT(x) | BIT_ATIM_URGENT(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DIS_ATIM_V1 (Offset 0x1540) */ + +#define BIT_DIS_ATIM_P4 BIT(19) +#define BIT_DIS_ATIM_P3 BIT(18) +#define BIT_DIS_ATIM_P2 BIT(17) +#define BIT_DIS_ATIM_P1 BIT(16) +#define BIT_DIS_ATIM_VAP15 BIT(15) +#define BIT_DIS_ATIM_VAP14 BIT(14) +#define BIT_DIS_ATIM_VAP13 BIT(13) +#define BIT_DIS_ATIM_VAP12 BIT(12) +#define BIT_DIS_ATIM_VAP11 BIT(11) +#define BIT_DIS_ATIM_VAP10 BIT(10) +#define BIT_DIS_ATIM_VAP9 BIT(9) +#define BIT_DIS_ATIM_VAP8 BIT(8) +#define BIT_DIS_ATIM_ROOT_P0 BIT(0) + +/* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */ + +#define BIT_HIQ_NO_LMT_EN_P4 BIT(19) +#define BIT_HIQ_NO_LMT_EN_P3 BIT(18) +#define BIT_HIQ_NO_LMT_EN_P2 BIT(17) +#define BIT_HIQ_NO_LMT_EN_P1 BIT(16) + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) + +/* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */ -#define BIT_SHIFT_BF0_LIFETIME 0 -#define BIT_MASK_BF0_LIFETIME 0xffff -#define BIT_BF0_LIFETIME(x) (((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME) -#define BIT_GET_BF0_LIFETIME(x) (((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME) +#define BIT_HIQ_NO_LMT_EN_VAP15 BIT(15) +#define BIT_HIQ_NO_LMT_EN_VAP14 BIT(14) +#define BIT_HIQ_NO_LMT_EN_VAP13 BIT(13) +#define BIT_HIQ_NO_LMT_EN_VAP12 BIT(12) +#define BIT_HIQ_NO_LMT_EN_VAP11 BIT(11) +#define BIT_HIQ_NO_LMT_EN_VAP10 BIT(10) +#define BIT_HIQ_NO_LMT_EN_VAP9 BIT(9) +#define BIT_HIQ_NO_LMT_EN_VAP8 BIT(8) +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */ + +#define BIT_HIQ_NO_LMT_EN_ROOT_P0 BIT(0) + +/* 2 REG_P2PPS_CTRL_V1 (Offset 0x1548) */ -/* 2 REG_BF1_TIME_SETTING (Offset 0x142C) */ +#define BIT_P2P_PWR_RST1_V2 BIT(15) +#define BIT_P2P_PWR_RST0_V2 BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P_V1 BIT(13) -#define BIT_BF1_TIMER_SET BIT(31) -#define BIT_BF1_TIMER_CLR BIT(30) -#define BIT_BF1_UPDATE_EN BIT(29) -#define BIT_BF1_TIMER_EN BIT(28) +#define BIT_SHIFT_NOA_UNIT0_SEL_V1 8 +#define BIT_MASK_NOA_UNIT0_SEL_V1 0x7 +#define BIT_NOA_UNIT0_SEL_V1(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_V1) << BIT_SHIFT_NOA_UNIT0_SEL_V1) +#define BITS_NOA_UNIT0_SEL_V1 \ + (BIT_MASK_NOA_UNIT0_SEL_V1 << BIT_SHIFT_NOA_UNIT0_SEL_V1) +#define BIT_CLEAR_NOA_UNIT0_SEL_V1(x) ((x) & (~BITS_NOA_UNIT0_SEL_V1)) +#define BIT_GET_NOA_UNIT0_SEL_V1(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_V1) & BIT_MASK_NOA_UNIT0_SEL_V1) +#define BIT_SET_NOA_UNIT0_SEL_V1(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_V1(x) | BIT_NOA_UNIT0_SEL_V1(v)) -#define BIT_SHIFT_BF1_PRETIME_OVER 16 -#define BIT_MASK_BF1_PRETIME_OVER 0xfff -#define BIT_BF1_PRETIME_OVER(x) (((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER) -#define BIT_GET_BF1_PRETIME_OVER(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER) +#define BIT_P2P_CTW_ALLSTASLEEP_V1 BIT(7) +#define BIT_P2P_OFF_DISTX_EN_V1 BIT(6) +#define BIT_PWR_MGT_EN_V1 BIT(5) +#define BIT_P2P_NOA1_EN_V1 BIT(2) +#define BIT_P2P_NOA0_EN_V1 BIT(1) +/* 2 REG_P2PPS1_CTRL_V1 (Offset 0x154C) */ -#define BIT_SHIFT_BF1_LIFETIME 0 -#define BIT_MASK_BF1_LIFETIME 0xffff -#define BIT_BF1_LIFETIME(x) (((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME) -#define BIT_GET_BF1_LIFETIME(x) (((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME) +#define BIT_P2P1_PWR_RST1_V2 BIT(15) +#define BIT_P2P1_PWR_RST0_V2 BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P1_V1 BIT(13) +#define BIT_SHIFT_NOA_UNIT1_SEL_V1 8 +#define BIT_MASK_NOA_UNIT1_SEL_V1 0x7 +#define BIT_NOA_UNIT1_SEL_V1(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_V1) << BIT_SHIFT_NOA_UNIT1_SEL_V1) +#define BITS_NOA_UNIT1_SEL_V1 \ + (BIT_MASK_NOA_UNIT1_SEL_V1 << BIT_SHIFT_NOA_UNIT1_SEL_V1) +#define BIT_CLEAR_NOA_UNIT1_SEL_V1(x) ((x) & (~BITS_NOA_UNIT1_SEL_V1)) +#define BIT_GET_NOA_UNIT1_SEL_V1(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_V1) & BIT_MASK_NOA_UNIT1_SEL_V1) +#define BIT_SET_NOA_UNIT1_SEL_V1(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_V1(x) | BIT_NOA_UNIT1_SEL_V1(v)) -/* 2 REG_BF_TIMEOUT_EN (Offset 0x1430) */ +#define BIT_P2P1_CTW_ALLSTASLEEP_V1 BIT(7) +#define BIT_P2P1_PWR_MGT_EN_V1 BIT(5) +#define BIT_P2P1_NOA1_EN_V1 BIT(2) +#define BIT_P2P1_NOA0_EN_V1 BIT(1) -#define BIT_EN_VHT_LDPC BIT(9) -#define BIT_EN_HT_LDPC BIT(8) -#define BIT_BF1_TIMEOUT_EN BIT(1) -#define BIT_BF0_TIMEOUT_EN BIT(0) +/* 2 REG_P2PPS1_SPEC_STATE_V1 (Offset 0x154E) */ -/* 2 REG_MACID_RELEASE0 (Offset 0x1434) */ +#define BIT_P2P1_SPEC_POWER_STATEP BIT(7) +#define BIT_P2P1_SPEC_BEACON_AREA_ON BIT(5) +/* 2 REG_P2PPS2_CTRL_V1 (Offset 0x1550) */ -#define BIT_SHIFT_MACID31_0_RELEASE 0 -#define BIT_MASK_MACID31_0_RELEASE 0xffffffffL -#define BIT_MACID31_0_RELEASE(x) (((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE) -#define BIT_GET_MACID31_0_RELEASE(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE) +#define BIT_P2P2_PWR_RST1_V2 BIT(15) +#define BIT_P2P2_PWR_RST0_V2 BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P2_V1 BIT(13) +#define BIT_SHIFT_NOA_UNIT2_SEL_V1 8 +#define BIT_MASK_NOA_UNIT2_SEL_V1 0x7 +#define BIT_NOA_UNIT2_SEL_V1(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_V1) << BIT_SHIFT_NOA_UNIT2_SEL_V1) +#define BITS_NOA_UNIT2_SEL_V1 \ + (BIT_MASK_NOA_UNIT2_SEL_V1 << BIT_SHIFT_NOA_UNIT2_SEL_V1) +#define BIT_CLEAR_NOA_UNIT2_SEL_V1(x) ((x) & (~BITS_NOA_UNIT2_SEL_V1)) +#define BIT_GET_NOA_UNIT2_SEL_V1(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_V1) & BIT_MASK_NOA_UNIT2_SEL_V1) +#define BIT_SET_NOA_UNIT2_SEL_V1(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_V1(x) | BIT_NOA_UNIT2_SEL_V1(v)) -/* 2 REG_MACID_RELEASE1 (Offset 0x1438) */ +#define BIT_P2P2_CTW_ALLSTASLEEP_V1 BIT(7) +#define BIT_P2P2_OFF_DISTX_EN_V1 BIT(6) +#define BIT_P2P2_PWR_MGT_EN_V1 BIT(5) +#define BIT_P2P2_NOA1_EN_V1 BIT(2) +#define BIT_P2P2_NOA0_EN_V1 BIT(1) +/* 2 REG_P2PPS2_SPEC_STATE_V1 (Offset 0x1552) */ -#define BIT_SHIFT_MACID63_32_RELEASE 0 -#define BIT_MASK_MACID63_32_RELEASE 0xffffffffL -#define BIT_MACID63_32_RELEASE(x) (((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE) -#define BIT_GET_MACID63_32_RELEASE(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE) +#define BIT_P2P2_SPEC_POWER_STATEP BIT(7) +#define BIT_P2P2_SPEC_BEACON_AREA_ON BIT(5) +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_P2PON_DIS_TXTIME_V1 (Offset 0x1554) */ + +#define BIT_SHIFT_P2PON_DIS_TXTIME 0 +#define BIT_MASK_P2PON_DIS_TXTIME 0xff +#define BIT_P2PON_DIS_TXTIME(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME) +#define BITS_P2PON_DIS_TXTIME \ + (BIT_MASK_P2PON_DIS_TXTIME << BIT_SHIFT_P2PON_DIS_TXTIME) +#define BIT_CLEAR_P2PON_DIS_TXTIME(x) ((x) & (~BITS_P2PON_DIS_TXTIME)) +#define BIT_GET_P2PON_DIS_TXTIME(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME) +#define BIT_SET_P2PON_DIS_TXTIME(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME(x) | BIT_P2PON_DIS_TXTIME(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CHG_POWER_BCN_AREA (Offset 0x1556) */ + +#define BIT_CHG_POWER_BCN_AREA BIT(0) + +/* 2 REG_NOA_SEL (Offset 0x1557) */ + +#define BIT_SHIFT_NOA_SEL_V1 0 +#define BIT_MASK_NOA_SEL_V1 0x7 +#define BIT_NOA_SEL_V1(x) (((x) & BIT_MASK_NOA_SEL_V1) << BIT_SHIFT_NOA_SEL_V1) +#define BITS_NOA_SEL_V1 (BIT_MASK_NOA_SEL_V1 << BIT_SHIFT_NOA_SEL_V1) +#define BIT_CLEAR_NOA_SEL_V1(x) ((x) & (~BITS_NOA_SEL_V1)) +#define BIT_GET_NOA_SEL_V1(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V1) & BIT_MASK_NOA_SEL_V1) +#define BIT_SET_NOA_SEL_V1(x, v) (BIT_CLEAR_NOA_SEL_V1(x) | BIT_NOA_SEL_V1(v)) + +/* 2 REG_NOA_PARAM_3_V1 (Offset 0x1564) */ + +#define BIT_SHIFT_NOA_COUNT_V2 0 +#define BIT_MASK_NOA_COUNT_V2 0xffffffffL +#define BIT_NOA_COUNT_V2(x) \ + (((x) & BIT_MASK_NOA_COUNT_V2) << BIT_SHIFT_NOA_COUNT_V2) +#define BITS_NOA_COUNT_V2 (BIT_MASK_NOA_COUNT_V2 << BIT_SHIFT_NOA_COUNT_V2) +#define BIT_CLEAR_NOA_COUNT_V2(x) ((x) & (~BITS_NOA_COUNT_V2)) +#define BIT_GET_NOA_COUNT_V2(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_V2) & BIT_MASK_NOA_COUNT_V2) +#define BIT_SET_NOA_COUNT_V2(x, v) \ + (BIT_CLEAR_NOA_COUNT_V2(x) | BIT_NOA_COUNT_V2(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_NOA_ON_ERLY_TIME_V1 (Offset 0x1568) */ + +#define BIT_SHIFT__NOA_ON_ERLY_TIME 0 +#define BIT_MASK__NOA_ON_ERLY_TIME 0xff +#define BIT__NOA_ON_ERLY_TIME(x) \ + (((x) & BIT_MASK__NOA_ON_ERLY_TIME) << BIT_SHIFT__NOA_ON_ERLY_TIME) +#define BITS__NOA_ON_ERLY_TIME \ + (BIT_MASK__NOA_ON_ERLY_TIME << BIT_SHIFT__NOA_ON_ERLY_TIME) +#define BIT_CLEAR__NOA_ON_ERLY_TIME(x) ((x) & (~BITS__NOA_ON_ERLY_TIME)) +#define BIT_GET__NOA_ON_ERLY_TIME(x) \ + (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME) & BIT_MASK__NOA_ON_ERLY_TIME) +#define BIT_SET__NOA_ON_ERLY_TIME(x, v) \ + (BIT_CLEAR__NOA_ON_ERLY_TIME(x) | BIT__NOA_ON_ERLY_TIME(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL (Offset 0x156C) */ + +#define BIT_P2PPS_NOA_STOP_TX_HANG BIT(31) +#define BIT_P2PPS_MACID_PAUSE_EN BIT(11) +#define BIT_P2PPS__MGQ_PAUSE BIT(10) +#define BIT_P2PPS__HIQ_PAUSE BIT(9) +#define BIT_P2PPS__BCNQ_PAUSE BIT(8) + +#define BIT_SHIFT_P2PPS_MACID_PAUSE 0 +#define BIT_MASK_P2PPS_MACID_PAUSE 0xff +#define BIT_P2PPS_MACID_PAUSE(x) \ + (((x) & BIT_MASK_P2PPS_MACID_PAUSE) << BIT_SHIFT_P2PPS_MACID_PAUSE) +#define BITS_P2PPS_MACID_PAUSE \ + (BIT_MASK_P2PPS_MACID_PAUSE << BIT_SHIFT_P2PPS_MACID_PAUSE) +#define BIT_CLEAR_P2PPS_MACID_PAUSE(x) ((x) & (~BITS_P2PPS_MACID_PAUSE)) +#define BIT_GET_P2PPS_MACID_PAUSE(x) \ + (((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE) & BIT_MASK_P2PPS_MACID_PAUSE) +#define BIT_SET_P2PPS_MACID_PAUSE(x, v) \ + (BIT_CLEAR_P2PPS_MACID_PAUSE(x) | BIT_P2PPS_MACID_PAUSE(v)) + +/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL (Offset 0x1570) */ + +#define BIT_P2PPS1_NOA_STOP_TX_HANG BIT(31) +#define BIT_P2PPS1_MACID_PAUSE_EN BIT(11) +#define BIT_P2PPS1__MGQ_PAUSE BIT(10) +#define BIT_P2PPS1__HIQ_PAUSE BIT(9) +#define BIT_P2PPS1__BCNQ_PAUSE BIT(8) + +#define BIT_SHIFT_P2PPS1_MACID_PAUSE 0 +#define BIT_MASK_P2PPS1_MACID_PAUSE 0xff +#define BIT_P2PPS1_MACID_PAUSE(x) \ + (((x) & BIT_MASK_P2PPS1_MACID_PAUSE) << BIT_SHIFT_P2PPS1_MACID_PAUSE) +#define BITS_P2PPS1_MACID_PAUSE \ + (BIT_MASK_P2PPS1_MACID_PAUSE << BIT_SHIFT_P2PPS1_MACID_PAUSE) +#define BIT_CLEAR_P2PPS1_MACID_PAUSE(x) ((x) & (~BITS_P2PPS1_MACID_PAUSE)) +#define BIT_GET_P2PPS1_MACID_PAUSE(x) \ + (((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE) & BIT_MASK_P2PPS1_MACID_PAUSE) +#define BIT_SET_P2PPS1_MACID_PAUSE(x, v) \ + (BIT_CLEAR_P2PPS1_MACID_PAUSE(x) | BIT_P2PPS1_MACID_PAUSE(v)) + +/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL (Offset 0x1574) */ + +#define BIT_P2PPS2_NOA_STOP_TX_HANG BIT(31) +#define BIT_P2PPS2_MACID_PAUSE_EN BIT(11) +#define BIT_P2PPS2__MGQ_PAUSE BIT(10) +#define BIT_P2PPS2__HIQ_PAUSE BIT(9) +#define BIT_P2PPS2__BCNQ_PAUSE BIT(8) + +#define BIT_SHIFT_P2PPS2_MACID_PAUSE 0 +#define BIT_MASK_P2PPS2_MACID_PAUSE 0xff +#define BIT_P2PPS2_MACID_PAUSE(x) \ + (((x) & BIT_MASK_P2PPS2_MACID_PAUSE) << BIT_SHIFT_P2PPS2_MACID_PAUSE) +#define BITS_P2PPS2_MACID_PAUSE \ + (BIT_MASK_P2PPS2_MACID_PAUSE << BIT_SHIFT_P2PPS2_MACID_PAUSE) +#define BIT_CLEAR_P2PPS2_MACID_PAUSE(x) ((x) & (~BITS_P2PPS2_MACID_PAUSE)) +#define BIT_GET_P2PPS2_MACID_PAUSE(x) \ + (((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE) & BIT_MASK_P2PPS2_MACID_PAUSE) +#define BIT_SET_P2PPS2_MACID_PAUSE(x, v) \ + (BIT_CLEAR_P2PPS2_MACID_PAUSE(x) | BIT_P2PPS2_MACID_PAUSE(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_RX_TBTT_SHIFT (Offset 0x1578) */ + +#define BIT_SHIFT_RX_TBTT_SHIFT_SEL 24 +#define BIT_MASK_RX_TBTT_SHIFT_SEL 0x7 +#define BIT_RX_TBTT_SHIFT_SEL(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL) << BIT_SHIFT_RX_TBTT_SHIFT_SEL) +#define BITS_RX_TBTT_SHIFT_SEL \ + (BIT_MASK_RX_TBTT_SHIFT_SEL << BIT_SHIFT_RX_TBTT_SHIFT_SEL) +#define BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL)) +#define BIT_GET_RX_TBTT_SHIFT_SEL(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL) & BIT_MASK_RX_TBTT_SHIFT_SEL) +#define BIT_SET_RX_TBTT_SHIFT_SEL(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) | BIT_RX_TBTT_SHIFT_SEL(v)) + +#define BIT_RX_TBTT_SHIFT_RW_FLAG BIT(15) + +#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET 0 +#define BIT_MASK_RX_TBTT_SHIFT_OFFSET 0xfff +#define BIT_RX_TBTT_SHIFT_OFFSET(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET) \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) +#define BITS_RX_TBTT_SHIFT_OFFSET \ + (BIT_MASK_RX_TBTT_SHIFT_OFFSET << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) +#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET)) +#define BIT_GET_RX_TBTT_SHIFT_OFFSET(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) & \ + BIT_MASK_RX_TBTT_SHIFT_OFFSET) +#define BIT_SET_RX_TBTT_SHIFT_OFFSET(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) | BIT_RX_TBTT_SHIFT_OFFSET(v)) + +/* 2 REG_FREERUN_CNT_LOW (Offset 0x1580) */ + +#define BIT_SHIFT_FREERUN_CNT_LOW 0 +#define BIT_MASK_FREERUN_CNT_LOW 0xffffffffL +#define BIT_FREERUN_CNT_LOW(x) \ + (((x) & BIT_MASK_FREERUN_CNT_LOW) << BIT_SHIFT_FREERUN_CNT_LOW) +#define BITS_FREERUN_CNT_LOW \ + (BIT_MASK_FREERUN_CNT_LOW << BIT_SHIFT_FREERUN_CNT_LOW) +#define BIT_CLEAR_FREERUN_CNT_LOW(x) ((x) & (~BITS_FREERUN_CNT_LOW)) +#define BIT_GET_FREERUN_CNT_LOW(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_LOW) & BIT_MASK_FREERUN_CNT_LOW) +#define BIT_SET_FREERUN_CNT_LOW(x, v) \ + (BIT_CLEAR_FREERUN_CNT_LOW(x) | BIT_FREERUN_CNT_LOW(v)) + +/* 2 REG_FREERUN_CNT_HIGH (Offset 0x1584) */ + +#define BIT_SHIFT_FREERUN_CNT_HIGH 0 +#define BIT_MASK_FREERUN_CNT_HIGH 0xffffffffL +#define BIT_FREERUN_CNT_HIGH(x) \ + (((x) & BIT_MASK_FREERUN_CNT_HIGH) << BIT_SHIFT_FREERUN_CNT_HIGH) +#define BITS_FREERUN_CNT_HIGH \ + (BIT_MASK_FREERUN_CNT_HIGH << BIT_SHIFT_FREERUN_CNT_HIGH) +#define BIT_CLEAR_FREERUN_CNT_HIGH(x) ((x) & (~BITS_FREERUN_CNT_HIGH)) +#define BIT_GET_FREERUN_CNT_HIGH(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_HIGH) & BIT_MASK_FREERUN_CNT_HIGH) +#define BIT_SET_FREERUN_CNT_HIGH(x, v) \ + (BIT_CLEAR_FREERUN_CNT_HIGH(x) | BIT_FREERUN_CNT_HIGH(v)) + +/* 2 REG_PS_TIMER_0 (Offset 0x158C) */ + +#define BIT_SHIFT_PS_TIMER_0 0 +#define BIT_MASK_PS_TIMER_0 0xffffffffL +#define BIT_PS_TIMER_0(x) (((x) & BIT_MASK_PS_TIMER_0) << BIT_SHIFT_PS_TIMER_0) +#define BITS_PS_TIMER_0 (BIT_MASK_PS_TIMER_0 << BIT_SHIFT_PS_TIMER_0) +#define BIT_CLEAR_PS_TIMER_0(x) ((x) & (~BITS_PS_TIMER_0)) +#define BIT_GET_PS_TIMER_0(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0) & BIT_MASK_PS_TIMER_0) +#define BIT_SET_PS_TIMER_0(x, v) (BIT_CLEAR_PS_TIMER_0(x) | BIT_PS_TIMER_0(v)) + +/* 2 REG_PS_TIMER_1 (Offset 0x1590) */ + +#define BIT_SHIFT_PS_TIMER_1 0 +#define BIT_MASK_PS_TIMER_1 0xffffffffL +#define BIT_PS_TIMER_1(x) (((x) & BIT_MASK_PS_TIMER_1) << BIT_SHIFT_PS_TIMER_1) +#define BITS_PS_TIMER_1 (BIT_MASK_PS_TIMER_1 << BIT_SHIFT_PS_TIMER_1) +#define BIT_CLEAR_PS_TIMER_1(x) ((x) & (~BITS_PS_TIMER_1)) +#define BIT_GET_PS_TIMER_1(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1) & BIT_MASK_PS_TIMER_1) +#define BIT_SET_PS_TIMER_1(x, v) (BIT_CLEAR_PS_TIMER_1(x) | BIT_PS_TIMER_1(v)) + +/* 2 REG_PS_TIMER_2 (Offset 0x1594) */ + +#define BIT_SHIFT_PS_TIMER_2 0 +#define BIT_MASK_PS_TIMER_2 0xffffffffL +#define BIT_PS_TIMER_2(x) (((x) & BIT_MASK_PS_TIMER_2) << BIT_SHIFT_PS_TIMER_2) +#define BITS_PS_TIMER_2 (BIT_MASK_PS_TIMER_2 << BIT_SHIFT_PS_TIMER_2) +#define BIT_CLEAR_PS_TIMER_2(x) ((x) & (~BITS_PS_TIMER_2)) +#define BIT_GET_PS_TIMER_2(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2) & BIT_MASK_PS_TIMER_2) +#define BIT_SET_PS_TIMER_2(x, v) (BIT_CLEAR_PS_TIMER_2(x) | BIT_PS_TIMER_2(v)) + +/* 2 REG_PS_TIMER_3 (Offset 0x1598) */ + +#define BIT_SHIFT_PS_TIMER_3 0 +#define BIT_MASK_PS_TIMER_3 0xffffffffL +#define BIT_PS_TIMER_3(x) (((x) & BIT_MASK_PS_TIMER_3) << BIT_SHIFT_PS_TIMER_3) +#define BITS_PS_TIMER_3 (BIT_MASK_PS_TIMER_3 << BIT_SHIFT_PS_TIMER_3) +#define BIT_CLEAR_PS_TIMER_3(x) ((x) & (~BITS_PS_TIMER_3)) +#define BIT_GET_PS_TIMER_3(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3) & BIT_MASK_PS_TIMER_3) +#define BIT_SET_PS_TIMER_3(x, v) (BIT_CLEAR_PS_TIMER_3(x) | BIT_PS_TIMER_3(v)) + +/* 2 REG_PS_TIMER_4 (Offset 0x159C) */ + +#define BIT_SHIFT_PS_TIMER_4 0 +#define BIT_MASK_PS_TIMER_4 0xffffffffL +#define BIT_PS_TIMER_4(x) (((x) & BIT_MASK_PS_TIMER_4) << BIT_SHIFT_PS_TIMER_4) +#define BITS_PS_TIMER_4 (BIT_MASK_PS_TIMER_4 << BIT_SHIFT_PS_TIMER_4) +#define BIT_CLEAR_PS_TIMER_4(x) ((x) & (~BITS_PS_TIMER_4)) +#define BIT_GET_PS_TIMER_4(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4) & BIT_MASK_PS_TIMER_4) +#define BIT_SET_PS_TIMER_4(x, v) (BIT_CLEAR_PS_TIMER_4(x) | BIT_PS_TIMER_4(v)) + +/* 2 REG_PS_TIMER_5 (Offset 0x15A0) */ + +#define BIT_SHIFT_PS_TIMER_5 0 +#define BIT_MASK_PS_TIMER_5 0xffffffffL +#define BIT_PS_TIMER_5(x) (((x) & BIT_MASK_PS_TIMER_5) << BIT_SHIFT_PS_TIMER_5) +#define BITS_PS_TIMER_5 (BIT_MASK_PS_TIMER_5 << BIT_SHIFT_PS_TIMER_5) +#define BIT_CLEAR_PS_TIMER_5(x) ((x) & (~BITS_PS_TIMER_5)) +#define BIT_GET_PS_TIMER_5(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5) & BIT_MASK_PS_TIMER_5) +#define BIT_SET_PS_TIMER_5(x, v) (BIT_CLEAR_PS_TIMER_5(x) | BIT_PS_TIMER_5(v)) + +/* 2 REG_PS_TIMER_01_CTRL (Offset 0x15A4) */ + +#define BIT_SHIFT_PS_TIMER_1_EARLY_TIME 24 +#define BIT_MASK_PS_TIMER_1_EARLY_TIME 0xff +#define BIT_PS_TIMER_1_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_1_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_1_EARLY_TIME) +#define BITS_PS_TIMER_1_EARLY_TIME \ + (BIT_MASK_PS_TIMER_1_EARLY_TIME << BIT_SHIFT_PS_TIMER_1_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_1_EARLY_TIME)) +#define BIT_GET_PS_TIMER_1_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_1_EARLY_TIME) +#define BIT_SET_PS_TIMER_1_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) | BIT_PS_TIMER_1_EARLY_TIME(v)) + +#define BIT_PS_TIMER_1_EN BIT(23) + +#define BIT_SHIFT_PS_TIMER_1_TSF_SEL 16 +#define BIT_MASK_PS_TIMER_1_TSF_SEL 0x7 +#define BIT_PS_TIMER_1_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_1_TSF_SEL) << BIT_SHIFT_PS_TIMER_1_TSF_SEL) +#define BITS_PS_TIMER_1_TSF_SEL \ + (BIT_MASK_PS_TIMER_1_TSF_SEL << BIT_SHIFT_PS_TIMER_1_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_1_TSF_SEL)) +#define BIT_GET_PS_TIMER_1_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1_TSF_SEL) & BIT_MASK_PS_TIMER_1_TSF_SEL) +#define BIT_SET_PS_TIMER_1_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) | BIT_PS_TIMER_1_TSF_SEL(v)) + +#define BIT_SHIFT_PS_TIMER_0_EARLY_TIME 8 +#define BIT_MASK_PS_TIMER_0_EARLY_TIME 0xff +#define BIT_PS_TIMER_0_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_0_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_0_EARLY_TIME) +#define BITS_PS_TIMER_0_EARLY_TIME \ + (BIT_MASK_PS_TIMER_0_EARLY_TIME << BIT_SHIFT_PS_TIMER_0_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_0_EARLY_TIME)) +#define BIT_GET_PS_TIMER_0_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_0_EARLY_TIME) +#define BIT_SET_PS_TIMER_0_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) | BIT_PS_TIMER_0_EARLY_TIME(v)) + +#define BIT_PS_TIMER_0_EN BIT(7) + +#define BIT_SHIFT_PS_TIMER_0_TSF_SEL 0 +#define BIT_MASK_PS_TIMER_0_TSF_SEL 0x7 +#define BIT_PS_TIMER_0_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_0_TSF_SEL) << BIT_SHIFT_PS_TIMER_0_TSF_SEL) +#define BITS_PS_TIMER_0_TSF_SEL \ + (BIT_MASK_PS_TIMER_0_TSF_SEL << BIT_SHIFT_PS_TIMER_0_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_0_TSF_SEL)) +#define BIT_GET_PS_TIMER_0_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0_TSF_SEL) & BIT_MASK_PS_TIMER_0_TSF_SEL) +#define BIT_SET_PS_TIMER_0_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) | BIT_PS_TIMER_0_TSF_SEL(v)) + +/* 2 REG_PS_TIMER_23_CTRL (Offset 0x15A8) */ + +#define BIT_SHIFT_PS_TIMER_3_EARLY_TIME 24 +#define BIT_MASK_PS_TIMER_3_EARLY_TIME 0xff +#define BIT_PS_TIMER_3_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_3_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_3_EARLY_TIME) +#define BITS_PS_TIMER_3_EARLY_TIME \ + (BIT_MASK_PS_TIMER_3_EARLY_TIME << BIT_SHIFT_PS_TIMER_3_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_3_EARLY_TIME)) +#define BIT_GET_PS_TIMER_3_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_3_EARLY_TIME) +#define BIT_SET_PS_TIMER_3_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) | BIT_PS_TIMER_3_EARLY_TIME(v)) + +#define BIT_PS_TIMER_3_EN BIT(23) + +#define BIT_SHIFT_PS_TIMER_3_TSF_SEL 16 +#define BIT_MASK_PS_TIMER_3_TSF_SEL 0x7 +#define BIT_PS_TIMER_3_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_3_TSF_SEL) << BIT_SHIFT_PS_TIMER_3_TSF_SEL) +#define BITS_PS_TIMER_3_TSF_SEL \ + (BIT_MASK_PS_TIMER_3_TSF_SEL << BIT_SHIFT_PS_TIMER_3_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_3_TSF_SEL)) +#define BIT_GET_PS_TIMER_3_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3_TSF_SEL) & BIT_MASK_PS_TIMER_3_TSF_SEL) +#define BIT_SET_PS_TIMER_3_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) | BIT_PS_TIMER_3_TSF_SEL(v)) + +#define BIT_SHIFT_PS_TIMER_2_EARLY_TIME 8 +#define BIT_MASK_PS_TIMER_2_EARLY_TIME 0xff +#define BIT_PS_TIMER_2_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_2_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_2_EARLY_TIME) +#define BITS_PS_TIMER_2_EARLY_TIME \ + (BIT_MASK_PS_TIMER_2_EARLY_TIME << BIT_SHIFT_PS_TIMER_2_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_2_EARLY_TIME)) +#define BIT_GET_PS_TIMER_2_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_2_EARLY_TIME) +#define BIT_SET_PS_TIMER_2_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) | BIT_PS_TIMER_2_EARLY_TIME(v)) + +#define BIT_PS_TIMER_2_EN BIT(7) + +#define BIT_SHIFT_PS_TIMER_2_TSF_SEL 0 +#define BIT_MASK_PS_TIMER_2_TSF_SEL 0x7 +#define BIT_PS_TIMER_2_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_2_TSF_SEL) << BIT_SHIFT_PS_TIMER_2_TSF_SEL) +#define BITS_PS_TIMER_2_TSF_SEL \ + (BIT_MASK_PS_TIMER_2_TSF_SEL << BIT_SHIFT_PS_TIMER_2_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_2_TSF_SEL)) +#define BIT_GET_PS_TIMER_2_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2_TSF_SEL) & BIT_MASK_PS_TIMER_2_TSF_SEL) +#define BIT_SET_PS_TIMER_2_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) | BIT_PS_TIMER_2_TSF_SEL(v)) + +/* 2 REG_PS_TIMER_45_CTRL (Offset 0x15AC) */ + +#define BIT_SHIFT_PS_TIMER_5_EARLY_TIME 24 +#define BIT_MASK_PS_TIMER_5_EARLY_TIME 0xff +#define BIT_PS_TIMER_5_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_5_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_5_EARLY_TIME) +#define BITS_PS_TIMER_5_EARLY_TIME \ + (BIT_MASK_PS_TIMER_5_EARLY_TIME << BIT_SHIFT_PS_TIMER_5_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_5_EARLY_TIME)) +#define BIT_GET_PS_TIMER_5_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_5_EARLY_TIME) +#define BIT_SET_PS_TIMER_5_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) | BIT_PS_TIMER_5_EARLY_TIME(v)) + +#define BIT_PS_TIMER_5_EN BIT(23) + +#define BIT_SHIFT_PS_TIMER_5_TSF_SEL 16 +#define BIT_MASK_PS_TIMER_5_TSF_SEL 0x7 +#define BIT_PS_TIMER_5_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_5_TSF_SEL) << BIT_SHIFT_PS_TIMER_5_TSF_SEL) +#define BITS_PS_TIMER_5_TSF_SEL \ + (BIT_MASK_PS_TIMER_5_TSF_SEL << BIT_SHIFT_PS_TIMER_5_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_5_TSF_SEL)) +#define BIT_GET_PS_TIMER_5_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5_TSF_SEL) & BIT_MASK_PS_TIMER_5_TSF_SEL) +#define BIT_SET_PS_TIMER_5_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) | BIT_PS_TIMER_5_TSF_SEL(v)) + +#define BIT_SHIFT_PS_TIMER_4_EARLY_TIME 8 +#define BIT_MASK_PS_TIMER_4_EARLY_TIME 0xff +#define BIT_PS_TIMER_4_EARLY_TIME(x) \ + (((x) & BIT_MASK_PS_TIMER_4_EARLY_TIME) \ + << BIT_SHIFT_PS_TIMER_4_EARLY_TIME) +#define BITS_PS_TIMER_4_EARLY_TIME \ + (BIT_MASK_PS_TIMER_4_EARLY_TIME << BIT_SHIFT_PS_TIMER_4_EARLY_TIME) +#define BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_4_EARLY_TIME)) +#define BIT_GET_PS_TIMER_4_EARLY_TIME(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4_EARLY_TIME) & \ + BIT_MASK_PS_TIMER_4_EARLY_TIME) +#define BIT_SET_PS_TIMER_4_EARLY_TIME(x, v) \ + (BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) | BIT_PS_TIMER_4_EARLY_TIME(v)) + +#define BIT_PS_TIMER_4_EN BIT(7) + +#define BIT_SHIFT_PS_TIMER_4_TSF_SEL 0 +#define BIT_MASK_PS_TIMER_4_TSF_SEL 0x7 +#define BIT_PS_TIMER_4_TSF_SEL(x) \ + (((x) & BIT_MASK_PS_TIMER_4_TSF_SEL) << BIT_SHIFT_PS_TIMER_4_TSF_SEL) +#define BITS_PS_TIMER_4_TSF_SEL \ + (BIT_MASK_PS_TIMER_4_TSF_SEL << BIT_SHIFT_PS_TIMER_4_TSF_SEL) +#define BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_4_TSF_SEL)) +#define BIT_GET_PS_TIMER_4_TSF_SEL(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4_TSF_SEL) & BIT_MASK_PS_TIMER_4_TSF_SEL) +#define BIT_SET_PS_TIMER_4_TSF_SEL(x, v) \ + (BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) | BIT_PS_TIMER_4_TSF_SEL(v)) + +/* 2 REG_CPUMGQ_FREERUN_TIMER_CTRL (Offset 0x15B0) */ + +#define BIT_FREECNT_RST_V1 BIT(23) +#define BIT_EN_FREECNT_V1 BIT(16) + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1 8 +#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1 0xff +#define BIT_CPUMGQ_TX_TIMER_EARLY_V1(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) +#define BITS_CPUMGQ_TX_TIMER_EARLY_V1 \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1 \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_V1)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_V1(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_V1(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_V1(v)) + +#define BIT_CPUMGQ_TIMER_EN_V1 BIT(7) +#define BIT_CPUMGQ_DROP_BY_HOLDTIME BIT(5) +#define BIT_CPUMGQ_TX_EN_V1 BIT(4) + +#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1 0 +#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 0x7 +#define BIT_CPUMGQ_TIMER_TSF_SEL_V1(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) +#define BITS_CPUMGQ_TIMER_TSF_SEL_V1 \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_V1)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_V1(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_V1(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x) | BIT_CPUMGQ_TIMER_TSF_SEL_V1(v)) + +/* 2 REG_CPUMGQ_PROHIBIT (Offset 0x15B4) */ + +#define BIT_SHIFT_CPUMGQ_HOLD_TIME 8 +#define BIT_MASK_CPUMGQ_HOLD_TIME 0xfff +#define BIT_CPUMGQ_HOLD_TIME(x) \ + (((x) & BIT_MASK_CPUMGQ_HOLD_TIME) << BIT_SHIFT_CPUMGQ_HOLD_TIME) +#define BITS_CPUMGQ_HOLD_TIME \ + (BIT_MASK_CPUMGQ_HOLD_TIME << BIT_SHIFT_CPUMGQ_HOLD_TIME) +#define BIT_CLEAR_CPUMGQ_HOLD_TIME(x) ((x) & (~BITS_CPUMGQ_HOLD_TIME)) +#define BIT_GET_CPUMGQ_HOLD_TIME(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_HOLD_TIME) & BIT_MASK_CPUMGQ_HOLD_TIME) +#define BIT_SET_CPUMGQ_HOLD_TIME(x, v) \ + (BIT_CLEAR_CPUMGQ_HOLD_TIME(x) | BIT_CPUMGQ_HOLD_TIME(v)) + +#define BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP 0 +#define BIT_MASK_CPUMGQ_PROHIBIT_SETUP 0xf +#define BIT_CPUMGQ_PROHIBIT_SETUP(x) \ + (((x) & BIT_MASK_CPUMGQ_PROHIBIT_SETUP) \ + << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) +#define BITS_CPUMGQ_PROHIBIT_SETUP \ + (BIT_MASK_CPUMGQ_PROHIBIT_SETUP << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) +#define BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) ((x) & (~BITS_CPUMGQ_PROHIBIT_SETUP)) +#define BIT_GET_CPUMGQ_PROHIBIT_SETUP(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) & \ + BIT_MASK_CPUMGQ_PROHIBIT_SETUP) +#define BIT_SET_CPUMGQ_PROHIBIT_SETUP(x, v) \ + (BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) | BIT_CPUMGQ_PROHIBIT_SETUP(v)) + +/* 2 REG_TIMER_COMPARE (Offset 0x15C0) */ + +#define BIT_COMP_TRIGGER BIT(7) + +#define BIT_SHIFT_Y_COMP 4 +#define BIT_MASK_Y_COMP 0x7 +#define BIT_Y_COMP(x) (((x) & BIT_MASK_Y_COMP) << BIT_SHIFT_Y_COMP) +#define BITS_Y_COMP (BIT_MASK_Y_COMP << BIT_SHIFT_Y_COMP) +#define BIT_CLEAR_Y_COMP(x) ((x) & (~BITS_Y_COMP)) +#define BIT_GET_Y_COMP(x) (((x) >> BIT_SHIFT_Y_COMP) & BIT_MASK_Y_COMP) +#define BIT_SET_Y_COMP(x, v) (BIT_CLEAR_Y_COMP(x) | BIT_Y_COMP(v)) + +#define BIT_X_COMP_Y_OVERFLOW BIT(3) + +#define BIT_SHIFT_X_COMP 0 +#define BIT_MASK_X_COMP 0x7 +#define BIT_X_COMP(x) (((x) & BIT_MASK_X_COMP) << BIT_SHIFT_X_COMP) +#define BITS_X_COMP (BIT_MASK_X_COMP << BIT_SHIFT_X_COMP) +#define BIT_CLEAR_X_COMP(x) ((x) & (~BITS_X_COMP)) +#define BIT_GET_X_COMP(x) (((x) >> BIT_SHIFT_X_COMP) & BIT_MASK_X_COMP) +#define BIT_SET_X_COMP(x, v) (BIT_CLEAR_X_COMP(x) | BIT_X_COMP(v)) + +/* 2 REG_TIMER_COMPARE_VALUE_LOW (Offset 0x15C4) */ + +#define BIT_SHIFT_COMP_VALUE_LOW 0 +#define BIT_MASK_COMP_VALUE_LOW 0xffffffffL +#define BIT_COMP_VALUE_LOW(x) \ + (((x) & BIT_MASK_COMP_VALUE_LOW) << BIT_SHIFT_COMP_VALUE_LOW) +#define BITS_COMP_VALUE_LOW \ + (BIT_MASK_COMP_VALUE_LOW << BIT_SHIFT_COMP_VALUE_LOW) +#define BIT_CLEAR_COMP_VALUE_LOW(x) ((x) & (~BITS_COMP_VALUE_LOW)) +#define BIT_GET_COMP_VALUE_LOW(x) \ + (((x) >> BIT_SHIFT_COMP_VALUE_LOW) & BIT_MASK_COMP_VALUE_LOW) +#define BIT_SET_COMP_VALUE_LOW(x, v) \ + (BIT_CLEAR_COMP_VALUE_LOW(x) | BIT_COMP_VALUE_LOW(v)) + +/* 2 REG_TIMER_COMPARE_VALUE_HIGH (Offset 0x15C8) */ + +#define BIT_SHIFT_COMP_VALUE_HIGH 0 +#define BIT_MASK_COMP_VALUE_HIGH 0xffffffffL +#define BIT_COMP_VALUE_HIGH(x) \ + (((x) & BIT_MASK_COMP_VALUE_HIGH) << BIT_SHIFT_COMP_VALUE_HIGH) +#define BITS_COMP_VALUE_HIGH \ + (BIT_MASK_COMP_VALUE_HIGH << BIT_SHIFT_COMP_VALUE_HIGH) +#define BIT_CLEAR_COMP_VALUE_HIGH(x) ((x) & (~BITS_COMP_VALUE_HIGH)) +#define BIT_GET_COMP_VALUE_HIGH(x) \ + (((x) >> BIT_SHIFT_COMP_VALUE_HIGH) & BIT_MASK_COMP_VALUE_HIGH) +#define BIT_SET_COMP_VALUE_HIGH(x, v) \ + (BIT_CLEAR_COMP_VALUE_HIGH(x) | BIT_COMP_VALUE_HIGH(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_SCHEDULER_COUNTER (Offset 0x15D0) */ + +#define BIT_SHIFT__SCHEDULER_COUNTER 16 +#define BIT_MASK__SCHEDULER_COUNTER 0xffff +#define BIT__SCHEDULER_COUNTER(x) \ + (((x) & BIT_MASK__SCHEDULER_COUNTER) << BIT_SHIFT__SCHEDULER_COUNTER) +#define BITS__SCHEDULER_COUNTER \ + (BIT_MASK__SCHEDULER_COUNTER << BIT_SHIFT__SCHEDULER_COUNTER) +#define BIT_CLEAR__SCHEDULER_COUNTER(x) ((x) & (~BITS__SCHEDULER_COUNTER)) +#define BIT_GET__SCHEDULER_COUNTER(x) \ + (((x) >> BIT_SHIFT__SCHEDULER_COUNTER) & BIT_MASK__SCHEDULER_COUNTER) +#define BIT_SET__SCHEDULER_COUNTER(x, v) \ + (BIT_CLEAR__SCHEDULER_COUNTER(x) | BIT__SCHEDULER_COUNTER(v)) + +#define BIT__SCHEDULER_COUNTER_RST BIT(8) + +#define BIT_SHIFT_SCHEDULER_COUNTER_SEL 0 +#define BIT_MASK_SCHEDULER_COUNTER_SEL 0xff +#define BIT_SCHEDULER_COUNTER_SEL(x) \ + (((x) & BIT_MASK_SCHEDULER_COUNTER_SEL) \ + << BIT_SHIFT_SCHEDULER_COUNTER_SEL) +#define BITS_SCHEDULER_COUNTER_SEL \ + (BIT_MASK_SCHEDULER_COUNTER_SEL << BIT_SHIFT_SCHEDULER_COUNTER_SEL) +#define BIT_CLEAR_SCHEDULER_COUNTER_SEL(x) ((x) & (~BITS_SCHEDULER_COUNTER_SEL)) +#define BIT_GET_SCHEDULER_COUNTER_SEL(x) \ + (((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL) & \ + BIT_MASK_SCHEDULER_COUNTER_SEL) +#define BIT_SET_SCHEDULER_COUNTER_SEL(x, v) \ + (BIT_CLEAR_SCHEDULER_COUNTER_SEL(x) | BIT_SCHEDULER_COUNTER_SEL(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_MACID_RELEASE2 (Offset 0x143C) */ +/* 2 REG_BCN_PSR_RPT2 (Offset 0x1600) */ +#define BIT_SHIFT_DTIM_CNT2 24 +#define BIT_MASK_DTIM_CNT2 0xff +#define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2) +#define BITS_DTIM_CNT2 (BIT_MASK_DTIM_CNT2 << BIT_SHIFT_DTIM_CNT2) +#define BIT_CLEAR_DTIM_CNT2(x) ((x) & (~BITS_DTIM_CNT2)) +#define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2) +#define BIT_SET_DTIM_CNT2(x, v) (BIT_CLEAR_DTIM_CNT2(x) | BIT_DTIM_CNT2(v)) + +#define BIT_SHIFT_DTIM_PERIOD2 16 +#define BIT_MASK_DTIM_PERIOD2 0xff +#define BIT_DTIM_PERIOD2(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2) +#define BITS_DTIM_PERIOD2 (BIT_MASK_DTIM_PERIOD2 << BIT_SHIFT_DTIM_PERIOD2) +#define BIT_CLEAR_DTIM_PERIOD2(x) ((x) & (~BITS_DTIM_PERIOD2)) +#define BIT_GET_DTIM_PERIOD2(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2) +#define BIT_SET_DTIM_PERIOD2(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2(x) | BIT_DTIM_PERIOD2(v)) + +#define BIT_DTIM2 BIT(15) +#define BIT_TIM2 BIT(14) + +#define BIT_SHIFT_PS_AID_2 0 +#define BIT_MASK_PS_AID_2 0x7ff +#define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2) +#define BITS_PS_AID_2 (BIT_MASK_PS_AID_2 << BIT_SHIFT_PS_AID_2) +#define BIT_CLEAR_PS_AID_2(x) ((x) & (~BITS_PS_AID_2)) +#define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2) +#define BIT_SET_PS_AID_2(x, v) (BIT_CLEAR_PS_AID_2(x) | BIT_PS_AID_2(v)) -#define BIT_SHIFT_MACID95_64_RELEASE 0 -#define BIT_MASK_MACID95_64_RELEASE 0xffffffffL -#define BIT_MACID95_64_RELEASE(x) (((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE) -#define BIT_GET_MACID95_64_RELEASE(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE) +/* 2 REG_BCN_PSR_RPT3 (Offset 0x1604) */ +#define BIT_SHIFT_DTIM_CNT3 24 +#define BIT_MASK_DTIM_CNT3 0xff +#define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3) +#define BITS_DTIM_CNT3 (BIT_MASK_DTIM_CNT3 << BIT_SHIFT_DTIM_CNT3) +#define BIT_CLEAR_DTIM_CNT3(x) ((x) & (~BITS_DTIM_CNT3)) +#define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3) +#define BIT_SET_DTIM_CNT3(x, v) (BIT_CLEAR_DTIM_CNT3(x) | BIT_DTIM_CNT3(v)) + +#define BIT_SHIFT_DTIM_PERIOD3 16 +#define BIT_MASK_DTIM_PERIOD3 0xff +#define BIT_DTIM_PERIOD3(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3) +#define BITS_DTIM_PERIOD3 (BIT_MASK_DTIM_PERIOD3 << BIT_SHIFT_DTIM_PERIOD3) +#define BIT_CLEAR_DTIM_PERIOD3(x) ((x) & (~BITS_DTIM_PERIOD3)) +#define BIT_GET_DTIM_PERIOD3(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3) +#define BIT_SET_DTIM_PERIOD3(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3(x) | BIT_DTIM_PERIOD3(v)) + +#define BIT_DTIM3 BIT(15) +#define BIT_TIM3 BIT(14) + +#define BIT_SHIFT_PS_AID_3 0 +#define BIT_MASK_PS_AID_3 0x7ff +#define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3) +#define BITS_PS_AID_3 (BIT_MASK_PS_AID_3 << BIT_SHIFT_PS_AID_3) +#define BIT_CLEAR_PS_AID_3(x) ((x) & (~BITS_PS_AID_3)) +#define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3) +#define BIT_SET_PS_AID_3(x, v) (BIT_CLEAR_PS_AID_3(x) | BIT_PS_AID_3(v)) -/* 2 REG_MACID_RELEASE3 (Offset 0x1440) */ +/* 2 REG_BCN_PSR_RPT4 (Offset 0x1608) */ +#define BIT_SHIFT_DTIM_CNT4 24 +#define BIT_MASK_DTIM_CNT4 0xff +#define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4) +#define BITS_DTIM_CNT4 (BIT_MASK_DTIM_CNT4 << BIT_SHIFT_DTIM_CNT4) +#define BIT_CLEAR_DTIM_CNT4(x) ((x) & (~BITS_DTIM_CNT4)) +#define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4) +#define BIT_SET_DTIM_CNT4(x, v) (BIT_CLEAR_DTIM_CNT4(x) | BIT_DTIM_CNT4(v)) + +#define BIT_SHIFT_DTIM_PERIOD4 16 +#define BIT_MASK_DTIM_PERIOD4 0xff +#define BIT_DTIM_PERIOD4(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4) +#define BITS_DTIM_PERIOD4 (BIT_MASK_DTIM_PERIOD4 << BIT_SHIFT_DTIM_PERIOD4) +#define BIT_CLEAR_DTIM_PERIOD4(x) ((x) & (~BITS_DTIM_PERIOD4)) +#define BIT_GET_DTIM_PERIOD4(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4) +#define BIT_SET_DTIM_PERIOD4(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4(x) | BIT_DTIM_PERIOD4(v)) + +#define BIT_DTIM4 BIT(15) +#define BIT_TIM4 BIT(14) + +#define BIT_SHIFT_PS_AID_4 0 +#define BIT_MASK_PS_AID_4 0x7ff +#define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4) +#define BITS_PS_AID_4 (BIT_MASK_PS_AID_4 << BIT_SHIFT_PS_AID_4) +#define BIT_CLEAR_PS_AID_4(x) ((x) & (~BITS_PS_AID_4)) +#define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4) +#define BIT_SET_PS_AID_4(x, v) (BIT_CLEAR_PS_AID_4(x) | BIT_PS_AID_4(v)) -#define BIT_SHIFT_MACID127_96_RELEASE 0 -#define BIT_MASK_MACID127_96_RELEASE 0xffffffffL -#define BIT_MACID127_96_RELEASE(x) (((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE) -#define BIT_GET_MACID127_96_RELEASE(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE) +/* 2 REG_A1_ADDR_MASK (Offset 0x160C) */ +#define BIT_SHIFT_A1_ADDR_MASK 0 +#define BIT_MASK_A1_ADDR_MASK 0xffffffffL +#define BIT_A1_ADDR_MASK(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK) +#define BITS_A1_ADDR_MASK (BIT_MASK_A1_ADDR_MASK << BIT_SHIFT_A1_ADDR_MASK) +#define BIT_CLEAR_A1_ADDR_MASK(x) ((x) & (~BITS_A1_ADDR_MASK)) +#define BIT_GET_A1_ADDR_MASK(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK) +#define BIT_SET_A1_ADDR_MASK(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK(x) | BIT_A1_ADDR_MASK(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_RXPSF_CTRL (Offset 0x1610) */ + +#define BIT_RXGCK_FIFOTHR_EN BIT(28) + +#define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26 +#define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3 +#define BIT_RXGCK_VHT_FIFOTHR(x) \ + (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR) +#define BITS_RXGCK_VHT_FIFOTHR \ + (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR) +#define BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) ((x) & (~BITS_RXGCK_VHT_FIFOTHR)) +#define BIT_GET_RXGCK_VHT_FIFOTHR(x) \ + (((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR) & BIT_MASK_RXGCK_VHT_FIFOTHR) +#define BIT_SET_RXGCK_VHT_FIFOTHR(x, v) \ + (BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) | BIT_RXGCK_VHT_FIFOTHR(v)) + +#define BIT_SHIFT_RXGCK_HT_FIFOTHR 24 +#define BIT_MASK_RXGCK_HT_FIFOTHR 0x3 +#define BIT_RXGCK_HT_FIFOTHR(x) \ + (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR) +#define BITS_RXGCK_HT_FIFOTHR \ + (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR) +#define BIT_CLEAR_RXGCK_HT_FIFOTHR(x) ((x) & (~BITS_RXGCK_HT_FIFOTHR)) +#define BIT_GET_RXGCK_HT_FIFOTHR(x) \ + (((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR) & BIT_MASK_RXGCK_HT_FIFOTHR) +#define BIT_SET_RXGCK_HT_FIFOTHR(x, v) \ + (BIT_CLEAR_RXGCK_HT_FIFOTHR(x) | BIT_RXGCK_HT_FIFOTHR(v)) + +#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22 +#define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3 +#define BIT_RXGCK_OFDM_FIFOTHR(x) \ + (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) +#define BITS_RXGCK_OFDM_FIFOTHR \ + (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR) +#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) ((x) & (~BITS_RXGCK_OFDM_FIFOTHR)) +#define BIT_GET_RXGCK_OFDM_FIFOTHR(x) \ + (((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR) & BIT_MASK_RXGCK_OFDM_FIFOTHR) +#define BIT_SET_RXGCK_OFDM_FIFOTHR(x, v) \ + (BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) | BIT_RXGCK_OFDM_FIFOTHR(v)) + +#define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20 +#define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3 +#define BIT_RXGCK_CCK_FIFOTHR(x) \ + (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR) +#define BITS_RXGCK_CCK_FIFOTHR \ + (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR) +#define BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) ((x) & (~BITS_RXGCK_CCK_FIFOTHR)) +#define BIT_GET_RXGCK_CCK_FIFOTHR(x) \ + (((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR) & BIT_MASK_RXGCK_CCK_FIFOTHR) +#define BIT_SET_RXGCK_CCK_FIFOTHR(x, v) \ + (BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) | BIT_RXGCK_CCK_FIFOTHR(v)) + +#define BIT_SHIFT_RXGCK_ENTRY_DELAY 17 +#define BIT_MASK_RXGCK_ENTRY_DELAY 0x7 +#define BIT_RXGCK_ENTRY_DELAY(x) \ + (((x) & BIT_MASK_RXGCK_ENTRY_DELAY) << BIT_SHIFT_RXGCK_ENTRY_DELAY) +#define BITS_RXGCK_ENTRY_DELAY \ + (BIT_MASK_RXGCK_ENTRY_DELAY << BIT_SHIFT_RXGCK_ENTRY_DELAY) +#define BIT_CLEAR_RXGCK_ENTRY_DELAY(x) ((x) & (~BITS_RXGCK_ENTRY_DELAY)) +#define BIT_GET_RXGCK_ENTRY_DELAY(x) \ + (((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY) & BIT_MASK_RXGCK_ENTRY_DELAY) +#define BIT_SET_RXGCK_ENTRY_DELAY(x, v) \ + (BIT_CLEAR_RXGCK_ENTRY_DELAY(x) | BIT_RXGCK_ENTRY_DELAY(v)) + +#define BIT_RXGCK_OFDMCCA_EN BIT(16) + +#define BIT_SHIFT_RXPSF_PKTLENTHR 13 +#define BIT_MASK_RXPSF_PKTLENTHR 0x7 +#define BIT_RXPSF_PKTLENTHR(x) \ + (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR) +#define BITS_RXPSF_PKTLENTHR \ + (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR) +#define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR)) +#define BIT_GET_RXPSF_PKTLENTHR(x) \ + (((x) >> BIT_SHIFT_RXPSF_PKTLENTHR) & BIT_MASK_RXPSF_PKTLENTHR) +#define BIT_SET_RXPSF_PKTLENTHR(x, v) \ + (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v)) + +#define BIT_RXPSF_CTRLEN BIT(12) +#define BIT_RXPSF_VHTCHKEN BIT(11) +#define BIT_RXPSF_HTCHKEN BIT(10) +#define BIT_RXPSF_OFDMCHKEN BIT(9) +#define BIT_RXPSF_CCKCHKEN BIT(8) +#define BIT_RXPSF_OFDMRST BIT(7) +#define BIT_RXPSF_CCKRST BIT(6) +#define BIT_RXPSF_MHCHKEN BIT(5) +#define BIT_RXPSF_CONT_ERRCHKEN BIT(4) +#define BIT_RXPSF_ALL_ERRCHKEN BIT(3) + +#define BIT_SHIFT_RXPSF_ERRTHR 0 +#define BIT_MASK_RXPSF_ERRTHR 0x7 +#define BIT_RXPSF_ERRTHR(x) \ + (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR) +#define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR) +#define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR)) +#define BIT_GET_RXPSF_ERRTHR(x) \ + (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR) +#define BIT_SET_RXPSF_ERRTHR(x, v) \ + (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v)) + +/* 2 REG_RXPSF_TYPE_CTRL (Offset 0x1614) */ + +#define BIT_RXPSF_DATA15EN BIT(31) +#define BIT_RXPSF_DATA14EN BIT(30) +#define BIT_RXPSF_DATA13EN BIT(29) +#define BIT_RXPSF_DATA12EN BIT(28) +#define BIT_RXPSF_DATA11EN BIT(27) +#define BIT_RXPSF_DATA10EN BIT(26) +#define BIT_RXPSF_DATA9EN BIT(25) +#define BIT_RXPSF_DATA8EN BIT(24) +#define BIT_RXPSF_DATA7EN BIT(23) +#define BIT_RXPSF_DATA6EN BIT(22) +#define BIT_RXPSF_DATA5EN BIT(21) +#define BIT_RXPSF_DATA4EN BIT(20) +#define BIT_RXPSF_DATA3EN BIT(19) +#define BIT_RXPSF_DATA2EN BIT(18) +#define BIT_RXPSF_DATA1EN BIT(17) +#define BIT_RXPSF_DATA0EN BIT(16) +#define BIT_RXPSF_MGT15EN BIT(15) +#define BIT_RXPSF_MGT14EN BIT(14) +#define BIT_RXPSF_MGT13EN BIT(13) +#define BIT_RXPSF_MGT12EN BIT(12) +#define BIT_RXPSF_MGT11EN BIT(11) +#define BIT_RXPSF_MGT10EN BIT(10) +#define BIT_RXPSF_MGT9EN BIT(9) +#define BIT_RXPSF_MGT8EN BIT(8) +#define BIT_RXPSF_MGT7EN BIT(7) +#define BIT_RXPSF_MGT6EN BIT(6) +#define BIT_RXPSF_MGT5EN BIT(5) +#define BIT_RXPSF_MGT4EN BIT(4) +#define BIT_RXPSF_MGT3EN BIT(3) +#define BIT_RXPSF_MGT2EN BIT(2) +#define BIT_RXPSF_MGT1EN BIT(1) +#define BIT_RXPSF_MGT0EN BIT(0) + +/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ + +#define BIT_INDIRECT_ERR BIT(6) +#define BIT_DIRECT_ERR BIT(5) +#define BIT_DIR_ACCESS_EN_RX_BA BIT(4) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ + +#define BIT_DIR_ACCESS_EN_MBSSIDCAM BIT(3) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ + +#define BIT_DIR_ACCESS_EN_ADDRCAM BIT(3) + +#endif -/* 2 REG_MACID_RELEASE_SETTING (Offset 0x1444) */ +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_MACID_VALUE BIT(7) +/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */ -#define BIT_SHIFT_MACID_OFFSET 0 -#define BIT_MASK_MACID_OFFSET 0x7f -#define BIT_MACID_OFFSET(x) (((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET) -#define BIT_GET_MACID_OFFSET(x) (((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET) +#define BIT_DIR_ACCESS_EN_KEY BIT(2) +#define BIT_DIR_ACCESS_EN_WOWLAN BIT(1) +#define BIT_DIR_ACCESS_EN_FW_FILTER BIT(0) +#endif -/* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */ +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_CUT_AMSDU_CTRL (Offset 0x161C) */ -#define BIT_SHIFT_VI_FAST_EDCA_TO 24 -#define BIT_MASK_VI_FAST_EDCA_TO 0xff -#define BIT_VI_FAST_EDCA_TO(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO) -#define BIT_GET_VI_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO) +#define BIT__CUT_AMSDU_CHKLEN_EN BIT(31) +#define BIT_EN_CUT_AMSDU BIT(30) -#define BIT_VI_THRESHOLD_SEL BIT(23) +#define BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH 16 +#define BIT_MASK_CUT_AMSDU_CHKLEN_L_TH 0xff +#define BIT_CUT_AMSDU_CHKLEN_L_TH(x) \ + (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_L_TH) \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) +#define BITS_CUT_AMSDU_CHKLEN_L_TH \ + (BIT_MASK_CUT_AMSDU_CHKLEN_L_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) +#define BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_L_TH)) +#define BIT_GET_CUT_AMSDU_CHKLEN_L_TH(x) \ + (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) & \ + BIT_MASK_CUT_AMSDU_CHKLEN_L_TH) +#define BIT_SET_CUT_AMSDU_CHKLEN_L_TH(x, v) \ + (BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) | BIT_CUT_AMSDU_CHKLEN_L_TH(v)) -#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16 -#define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f -#define BIT_VI_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH) -#define BIT_GET_VI_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_VO_FAST_EDCA_TO 8 -#define BIT_MASK_VO_FAST_EDCA_TO 0xff -#define BIT_VO_FAST_EDCA_TO(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO) -#define BIT_GET_VO_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO) +/* 2 REG_HT_SND_REF_RATE (Offset 0x161C) */ -#define BIT_VO_THRESHOLD_SEL BIT(7) +#define BIT_SHIFT_WMAC_HT_CSI_RATE 0 +#define BIT_MASK_WMAC_HT_CSI_RATE 0x3f +#define BIT_WMAC_HT_CSI_RATE(x) \ + (((x) & BIT_MASK_WMAC_HT_CSI_RATE) << BIT_SHIFT_WMAC_HT_CSI_RATE) +#define BITS_WMAC_HT_CSI_RATE \ + (BIT_MASK_WMAC_HT_CSI_RATE << BIT_SHIFT_WMAC_HT_CSI_RATE) +#define BIT_CLEAR_WMAC_HT_CSI_RATE(x) ((x) & (~BITS_WMAC_HT_CSI_RATE)) +#define BIT_GET_WMAC_HT_CSI_RATE(x) \ + (((x) >> BIT_SHIFT_WMAC_HT_CSI_RATE) & BIT_MASK_WMAC_HT_CSI_RATE) +#define BIT_SET_WMAC_HT_CSI_RATE(x, v) \ + (BIT_CLEAR_WMAC_HT_CSI_RATE(x) | BIT_WMAC_HT_CSI_RATE(v)) -#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0 -#define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f -#define BIT_VO_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH) -#define BIT_GET_VO_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */ +/* 2 REG_CUT_AMSDU_CTRL (Offset 0x161C) */ +#define BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH 0 +#define BIT_MASK_CUT_AMSDU_CHKLEN_H_TH 0xffff +#define BIT_CUT_AMSDU_CHKLEN_H_TH(x) \ + (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_H_TH) \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) +#define BITS_CUT_AMSDU_CHKLEN_H_TH \ + (BIT_MASK_CUT_AMSDU_CHKLEN_H_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) +#define BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_H_TH)) +#define BIT_GET_CUT_AMSDU_CHKLEN_H_TH(x) \ + (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) & \ + BIT_MASK_CUT_AMSDU_CHKLEN_H_TH) +#define BIT_SET_CUT_AMSDU_CHKLEN_H_TH(x, v) \ + (BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) | BIT_CUT_AMSDU_CHKLEN_H_TH(v)) -#define BIT_SHIFT_BK_FAST_EDCA_TO 24 -#define BIT_MASK_BK_FAST_EDCA_TO 0xff -#define BIT_BK_FAST_EDCA_TO(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO) -#define BIT_GET_BK_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO) +#endif -#define BIT_BK_THRESHOLD_SEL BIT(23) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16 -#define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f -#define BIT_BK_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH) -#define BIT_GET_BK_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH) +/* 2 REG_MACID2 (Offset 0x1620) */ +#define BIT_SHIFT_MACID2 0 +#define BIT_MASK_MACID2 0xffffffffffffL +#define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2) +#define BITS_MACID2 (BIT_MASK_MACID2 << BIT_SHIFT_MACID2) +#define BIT_CLEAR_MACID2(x) ((x) & (~BITS_MACID2)) +#define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2) +#define BIT_SET_MACID2(x, v) (BIT_CLEAR_MACID2(x) | BIT_MACID2(v)) -#define BIT_SHIFT_BE_FAST_EDCA_TO 8 -#define BIT_MASK_BE_FAST_EDCA_TO 0xff -#define BIT_BE_FAST_EDCA_TO(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO) -#define BIT_GET_BE_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO) +#endif -#define BIT_BE_THRESHOLD_SEL BIT(7) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0 -#define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f -#define BIT_BE_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH) -#define BIT_GET_BE_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH) +/* 2 REG_MACID2 (Offset 0x1620) */ +#define BIT_SHIFT_MACID2_V1 0 +#define BIT_MASK_MACID2_V1 0xffffffffL +#define BIT_MACID2_V1(x) (((x) & BIT_MASK_MACID2_V1) << BIT_SHIFT_MACID2_V1) +#define BITS_MACID2_V1 (BIT_MASK_MACID2_V1 << BIT_SHIFT_MACID2_V1) +#define BIT_CLEAR_MACID2_V1(x) ((x) & (~BITS_MACID2_V1)) +#define BIT_GET_MACID2_V1(x) (((x) >> BIT_SHIFT_MACID2_V1) & BIT_MASK_MACID2_V1) +#define BIT_SET_MACID2_V1(x, v) (BIT_CLEAR_MACID2_V1(x) | BIT_MACID2_V1(v)) -/* 2 REG_MACID_DROP0 (Offset 0x1450) */ +/* 2 REG_MACID2_H (Offset 0x1624) */ +#define BIT_SHIFT_MACID2_H_V1 0 +#define BIT_MASK_MACID2_H_V1 0xffff +#define BIT_MACID2_H_V1(x) \ + (((x) & BIT_MASK_MACID2_H_V1) << BIT_SHIFT_MACID2_H_V1) +#define BITS_MACID2_H_V1 (BIT_MASK_MACID2_H_V1 << BIT_SHIFT_MACID2_H_V1) +#define BIT_CLEAR_MACID2_H_V1(x) ((x) & (~BITS_MACID2_H_V1)) +#define BIT_GET_MACID2_H_V1(x) \ + (((x) >> BIT_SHIFT_MACID2_H_V1) & BIT_MASK_MACID2_H_V1) +#define BIT_SET_MACID2_H_V1(x, v) \ + (BIT_CLEAR_MACID2_H_V1(x) | BIT_MACID2_H_V1(v)) -#define BIT_SHIFT_MACID31_0_DROP 0 -#define BIT_MASK_MACID31_0_DROP 0xffffffffL -#define BIT_MACID31_0_DROP(x) (((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP) -#define BIT_GET_MACID31_0_DROP(x) (((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_MACID_DROP1 (Offset 0x1454) */ +/* 2 REG_BSSID2 (Offset 0x1628) */ +#define BIT_SHIFT_BSSID2 0 +#define BIT_MASK_BSSID2 0xffffffffffffL +#define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2) +#define BITS_BSSID2 (BIT_MASK_BSSID2 << BIT_SHIFT_BSSID2) +#define BIT_CLEAR_BSSID2(x) ((x) & (~BITS_BSSID2)) +#define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2) +#define BIT_SET_BSSID2(x, v) (BIT_CLEAR_BSSID2(x) | BIT_BSSID2(v)) -#define BIT_SHIFT_MACID63_32_DROP 0 -#define BIT_MASK_MACID63_32_DROP 0xffffffffL -#define BIT_MACID63_32_DROP(x) (((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP) -#define BIT_GET_MACID63_32_DROP(x) (((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_MACID_DROP2 (Offset 0x1458) */ +/* 2 REG_BSSID2 (Offset 0x1628) */ +#define BIT_SHIFT_BSSID2_V1 0 +#define BIT_MASK_BSSID2_V1 0xffffffffL +#define BIT_BSSID2_V1(x) (((x) & BIT_MASK_BSSID2_V1) << BIT_SHIFT_BSSID2_V1) +#define BITS_BSSID2_V1 (BIT_MASK_BSSID2_V1 << BIT_SHIFT_BSSID2_V1) +#define BIT_CLEAR_BSSID2_V1(x) ((x) & (~BITS_BSSID2_V1)) +#define BIT_GET_BSSID2_V1(x) (((x) >> BIT_SHIFT_BSSID2_V1) & BIT_MASK_BSSID2_V1) +#define BIT_SET_BSSID2_V1(x, v) (BIT_CLEAR_BSSID2_V1(x) | BIT_BSSID2_V1(v)) -#define BIT_SHIFT_MACID95_64_DROP 0 -#define BIT_MASK_MACID95_64_DROP 0xffffffffL -#define BIT_MACID95_64_DROP(x) (((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP) -#define BIT_GET_MACID95_64_DROP(x) (((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP) +/* 2 REG_BSSID2_H (Offset 0x162C) */ +#define BIT_SHIFT_BSSID2_H_V1 0 +#define BIT_MASK_BSSID2_H_V1 0xffff +#define BIT_BSSID2_H_V1(x) \ + (((x) & BIT_MASK_BSSID2_H_V1) << BIT_SHIFT_BSSID2_H_V1) +#define BITS_BSSID2_H_V1 (BIT_MASK_BSSID2_H_V1 << BIT_SHIFT_BSSID2_H_V1) +#define BIT_CLEAR_BSSID2_H_V1(x) ((x) & (~BITS_BSSID2_H_V1)) +#define BIT_GET_BSSID2_H_V1(x) \ + (((x) >> BIT_SHIFT_BSSID2_H_V1) & BIT_MASK_BSSID2_H_V1) +#define BIT_SET_BSSID2_H_V1(x, v) \ + (BIT_CLEAR_BSSID2_H_V1(x) | BIT_BSSID2_H_V1(v)) -/* 2 REG_MACID_DROP3 (Offset 0x145C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_MACID127_96_DROP 0 -#define BIT_MASK_MACID127_96_DROP 0xffffffffL -#define BIT_MACID127_96_DROP(x) (((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP) -#define BIT_GET_MACID127_96_DROP(x) (((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP) +/* 2 REG_MACID3 (Offset 0x1630) */ +#define BIT_SHIFT_MACID3 0 +#define BIT_MASK_MACID3 0xffffffffffffL +#define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3) +#define BITS_MACID3 (BIT_MASK_MACID3 << BIT_SHIFT_MACID3) +#define BIT_CLEAR_MACID3(x) ((x) & (~BITS_MACID3)) +#define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3) +#define BIT_SET_MACID3(x, v) (BIT_CLEAR_MACID3(x) | BIT_MACID3(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_MACID3 (Offset 0x1630) */ +#define BIT_SHIFT_MACID3_V1 0 +#define BIT_MASK_MACID3_V1 0xffffffffL +#define BIT_MACID3_V1(x) (((x) & BIT_MASK_MACID3_V1) << BIT_SHIFT_MACID3_V1) +#define BITS_MACID3_V1 (BIT_MASK_MACID3_V1 << BIT_SHIFT_MACID3_V1) +#define BIT_CLEAR_MACID3_V1(x) ((x) & (~BITS_MACID3_V1)) +#define BIT_GET_MACID3_V1(x) (((x) >> BIT_SHIFT_MACID3_V1) & BIT_MASK_MACID3_V1) +#define BIT_SET_MACID3_V1(x, v) (BIT_CLEAR_MACID3_V1(x) | BIT_MACID3_V1(v)) -/* 2 REG_R_MACID_RELEASE_SUCCESS_0 (Offset 0x1460) */ +/* 2 REG_MACID3_H (Offset 0x1634) */ +#define BIT_SHIFT_MACID3_H_V1 0 +#define BIT_MASK_MACID3_H_V1 0xffff +#define BIT_MACID3_H_V1(x) \ + (((x) & BIT_MASK_MACID3_H_V1) << BIT_SHIFT_MACID3_H_V1) +#define BITS_MACID3_H_V1 (BIT_MASK_MACID3_H_V1 << BIT_SHIFT_MACID3_H_V1) +#define BIT_CLEAR_MACID3_H_V1(x) ((x) & (~BITS_MACID3_H_V1)) +#define BIT_GET_MACID3_H_V1(x) \ + (((x) >> BIT_SHIFT_MACID3_H_V1) & BIT_MASK_MACID3_H_V1) +#define BIT_SET_MACID3_H_V1(x, v) \ + (BIT_CLEAR_MACID3_H_V1(x) | BIT_MACID3_H_V1(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_0(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_R_MACID_RELEASE_SUCCESS_1 (Offset 0x1464) */ +/* 2 REG_BSSID3 (Offset 0x1638) */ +#define BIT_SHIFT_BSSID3 0 +#define BIT_MASK_BSSID3 0xffffffffffffL +#define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3) +#define BITS_BSSID3 (BIT_MASK_BSSID3 << BIT_SHIFT_BSSID3) +#define BIT_CLEAR_BSSID3(x) ((x) & (~BITS_BSSID3)) +#define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3) +#define BIT_SET_BSSID3(x, v) (BIT_CLEAR_BSSID3(x) | BIT_BSSID3(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_1(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_R_MACID_RELEASE_SUCCESS_2 (Offset 0x1468) */ +/* 2 REG_BSSID3 (Offset 0x1638) */ +#define BIT_SHIFT_BSSID3_V1 0 +#define BIT_MASK_BSSID3_V1 0xffffffffL +#define BIT_BSSID3_V1(x) (((x) & BIT_MASK_BSSID3_V1) << BIT_SHIFT_BSSID3_V1) +#define BITS_BSSID3_V1 (BIT_MASK_BSSID3_V1 << BIT_SHIFT_BSSID3_V1) +#define BIT_CLEAR_BSSID3_V1(x) ((x) & (~BITS_BSSID3_V1)) +#define BIT_GET_BSSID3_V1(x) (((x) >> BIT_SHIFT_BSSID3_V1) & BIT_MASK_BSSID3_V1) +#define BIT_SET_BSSID3_V1(x, v) (BIT_CLEAR_BSSID3_V1(x) | BIT_BSSID3_V1(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_2(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) +/* 2 REG_BSSID3_H (Offset 0x163C) */ +#define BIT_SHIFT_BSSID3_H_V1 0 +#define BIT_MASK_BSSID3_H_V1 0xffff +#define BIT_BSSID3_H_V1(x) \ + (((x) & BIT_MASK_BSSID3_H_V1) << BIT_SHIFT_BSSID3_H_V1) +#define BITS_BSSID3_H_V1 (BIT_MASK_BSSID3_H_V1 << BIT_SHIFT_BSSID3_H_V1) +#define BIT_CLEAR_BSSID3_H_V1(x) ((x) & (~BITS_BSSID3_H_V1)) +#define BIT_GET_BSSID3_H_V1(x) \ + (((x) >> BIT_SHIFT_BSSID3_H_V1) & BIT_MASK_BSSID3_H_V1) +#define BIT_SET_BSSID3_H_V1(x, v) \ + (BIT_CLEAR_BSSID3_H_V1(x) | BIT_BSSID3_H_V1(v)) -/* 2 REG_R_MACID_RELEASE_SUCCESS_3 (Offset 0x146C) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_3(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) +/* 2 REG_MACID4 (Offset 0x1640) */ +#define BIT_SHIFT_MACID4 0 +#define BIT_MASK_MACID4 0xffffffffffffL +#define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4) +#define BITS_MACID4 (BIT_MASK_MACID4 << BIT_SHIFT_MACID4) +#define BIT_CLEAR_MACID4(x) ((x) & (~BITS_MACID4)) +#define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4) +#define BIT_SET_MACID4(x, v) (BIT_CLEAR_MACID4(x) | BIT_MACID4(v)) -/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ +#endif -#define BIT_R_MGG_FIFO_EN BIT(31) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28 -#define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7 -#define BIT_R_MGG_FIFO_PG_SIZE(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE) -#define BIT_GET_R_MGG_FIFO_PG_SIZE(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE) +/* 2 REG_MACID4 (Offset 0x1640) */ +#define BIT_SHIFT_MACID4_V1 0 +#define BIT_MASK_MACID4_V1 0xffffffffL +#define BIT_MACID4_V1(x) (((x) & BIT_MASK_MACID4_V1) << BIT_SHIFT_MACID4_V1) +#define BITS_MACID4_V1 (BIT_MASK_MACID4_V1 << BIT_SHIFT_MACID4_V1) +#define BIT_CLEAR_MACID4_V1(x) ((x) & (~BITS_MACID4_V1)) +#define BIT_GET_MACID4_V1(x) (((x) >> BIT_SHIFT_MACID4_V1) & BIT_MASK_MACID4_V1) +#define BIT_SET_MACID4_V1(x, v) (BIT_CLEAR_MACID4_V1(x) | BIT_MACID4_V1(v)) -#define BIT_SHIFT_R_MGG_FIFO_START_PG 16 -#define BIT_MASK_R_MGG_FIFO_START_PG 0xfff -#define BIT_R_MGG_FIFO_START_PG(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG) -#define BIT_GET_R_MGG_FIFO_START_PG(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG) +/* 2 REG_MACID4_H (Offset 0x1644) */ +#define BIT_SHIFT_MACID4_H_V1 0 +#define BIT_MASK_MACID4_H_V1 0xffff +#define BIT_MACID4_H_V1(x) \ + (((x) & BIT_MASK_MACID4_H_V1) << BIT_SHIFT_MACID4_H_V1) +#define BITS_MACID4_H_V1 (BIT_MASK_MACID4_H_V1 << BIT_SHIFT_MACID4_H_V1) +#define BIT_CLEAR_MACID4_H_V1(x) ((x) & (~BITS_MACID4_H_V1)) +#define BIT_GET_MACID4_H_V1(x) \ + (((x) >> BIT_SHIFT_MACID4_H_V1) & BIT_MASK_MACID4_H_V1) +#define BIT_SET_MACID4_H_V1(x, v) \ + (BIT_CLEAR_MACID4_H_V1(x) | BIT_MACID4_H_V1(v)) -#define BIT_SHIFT_R_MGG_FIFO_SIZE 14 -#define BIT_MASK_R_MGG_FIFO_SIZE 0x3 -#define BIT_R_MGG_FIFO_SIZE(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE) -#define BIT_GET_R_MGG_FIFO_SIZE(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE) +#endif -#define BIT_R_MGG_FIFO_PAUSE BIT(13) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_R_MGG_FIFO_RPTR 8 -#define BIT_MASK_R_MGG_FIFO_RPTR 0x1f -#define BIT_R_MGG_FIFO_RPTR(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR) -#define BIT_GET_R_MGG_FIFO_RPTR(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR) +/* 2 REG_BSSID4 (Offset 0x1648) */ -#define BIT_R_MGG_FIFO_OV BIT(7) -#define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6) -#define BIT_R_EN_CPU_LIFETIME BIT(5) +#define BIT_SHIFT_BSSID4 0 +#define BIT_MASK_BSSID4 0xffffffffffffL +#define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4) +#define BITS_BSSID4 (BIT_MASK_BSSID4 << BIT_SHIFT_BSSID4) +#define BIT_CLEAR_BSSID4(x) ((x) & (~BITS_BSSID4)) +#define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4) +#define BIT_SET_BSSID4(x, v) (BIT_CLEAR_BSSID4(x) | BIT_BSSID4(v)) -#define BIT_SHIFT_R_MGG_FIFO_WPTR 0 -#define BIT_MASK_R_MGG_FIFO_WPTR 0x1f -#define BIT_R_MGG_FIFO_WPTR(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR) -#define BIT_GET_R_MGG_FIFO_WPTR(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_MGG_FIFO_INT (Offset 0x1474) */ +/* 2 REG_BSSID4 (Offset 0x1648) */ +#define BIT_SHIFT_BSSID4_V1 0 +#define BIT_MASK_BSSID4_V1 0xffffffffL +#define BIT_BSSID4_V1(x) (((x) & BIT_MASK_BSSID4_V1) << BIT_SHIFT_BSSID4_V1) +#define BITS_BSSID4_V1 (BIT_MASK_BSSID4_V1 << BIT_SHIFT_BSSID4_V1) +#define BIT_CLEAR_BSSID4_V1(x) ((x) & (~BITS_BSSID4_V1)) +#define BIT_GET_BSSID4_V1(x) (((x) >> BIT_SHIFT_BSSID4_V1) & BIT_MASK_BSSID4_V1) +#define BIT_SET_BSSID4_V1(x, v) (BIT_CLEAR_BSSID4_V1(x) | BIT_BSSID4_V1(v)) -#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16 -#define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff -#define BIT_R_MGG_FIFO_INT_FLAG(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG) -#define BIT_GET_R_MGG_FIFO_INT_FLAG(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG) +/* 2 REG_BSSID4_H (Offset 0x164C) */ +#define BIT_SHIFT_BSSID4_H_V1 0 +#define BIT_MASK_BSSID4_H_V1 0xffff +#define BIT_BSSID4_H_V1(x) \ + (((x) & BIT_MASK_BSSID4_H_V1) << BIT_SHIFT_BSSID4_H_V1) +#define BITS_BSSID4_H_V1 (BIT_MASK_BSSID4_H_V1 << BIT_SHIFT_BSSID4_H_V1) +#define BIT_CLEAR_BSSID4_H_V1(x) ((x) & (~BITS_BSSID4_H_V1)) +#define BIT_GET_BSSID4_H_V1(x) \ + (((x) >> BIT_SHIFT_BSSID4_H_V1) & BIT_MASK_BSSID4_H_V1) +#define BIT_SET_BSSID4_H_V1(x, v) \ + (BIT_CLEAR_BSSID4_H_V1(x) | BIT_BSSID4_H_V1(v)) -#define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0 -#define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff -#define BIT_R_MGG_FIFO_INT_MASK(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK) -#define BIT_GET_R_MGG_FIFO_INT_MASK(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK) +#endif +#if (HALMAC_8814B_SUPPORT) -/* 2 REG_MGG_FIFO_LIFETIME (Offset 0x1478) */ +/* 2 REG_NOA_REPORT (Offset 0x1650) */ +#define BIT_SHIFT_NOA_RPT 0 +#define BIT_MASK_NOA_RPT 0xffffffffL +#define BIT_NOA_RPT(x) (((x) & BIT_MASK_NOA_RPT) << BIT_SHIFT_NOA_RPT) +#define BITS_NOA_RPT (BIT_MASK_NOA_RPT << BIT_SHIFT_NOA_RPT) +#define BIT_CLEAR_NOA_RPT(x) ((x) & (~BITS_NOA_RPT)) +#define BIT_GET_NOA_RPT(x) (((x) >> BIT_SHIFT_NOA_RPT) & BIT_MASK_NOA_RPT) +#define BIT_SET_NOA_RPT(x, v) (BIT_CLEAR_NOA_RPT(x) | BIT_NOA_RPT(v)) -#define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16 -#define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff -#define BIT_R_MGG_FIFO_LIFETIME(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME) -#define BIT_GET_R_MGG_FIFO_LIFETIME(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME) +/* 2 REG_NOA_REPORT_1 (Offset 0x1654) */ +#define BIT_SHIFT_NOA_RPT_1 0 +#define BIT_MASK_NOA_RPT_1 0xffffffffL +#define BIT_NOA_RPT_1(x) (((x) & BIT_MASK_NOA_RPT_1) << BIT_SHIFT_NOA_RPT_1) +#define BITS_NOA_RPT_1 (BIT_MASK_NOA_RPT_1 << BIT_SHIFT_NOA_RPT_1) +#define BIT_CLEAR_NOA_RPT_1(x) ((x) & (~BITS_NOA_RPT_1)) +#define BIT_GET_NOA_RPT_1(x) (((x) >> BIT_SHIFT_NOA_RPT_1) & BIT_MASK_NOA_RPT_1) +#define BIT_SET_NOA_RPT_1(x, v) (BIT_CLEAR_NOA_RPT_1(x) | BIT_NOA_RPT_1(v)) -#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0 -#define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff -#define BIT_R_MGG_FIFO_VALID_MAP(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP) -#define BIT_GET_R_MGG_FIFO_VALID_MAP(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) & BIT_MASK_R_MGG_FIFO_VALID_MAP) +/* 2 REG_NOA_REPORT_2 (Offset 0x1658) */ +#define BIT_SHIFT_NOA_RPT_2 0 +#define BIT_MASK_NOA_RPT_2 0xffffffffL +#define BIT_NOA_RPT_2(x) (((x) & BIT_MASK_NOA_RPT_2) << BIT_SHIFT_NOA_RPT_2) +#define BITS_NOA_RPT_2 (BIT_MASK_NOA_RPT_2 << BIT_SHIFT_NOA_RPT_2) +#define BIT_CLEAR_NOA_RPT_2(x) ((x) & (~BITS_NOA_RPT_2)) +#define BIT_GET_NOA_RPT_2(x) (((x) >> BIT_SHIFT_NOA_RPT_2) & BIT_MASK_NOA_RPT_2) +#define BIT_SET_NOA_RPT_2(x, v) (BIT_CLEAR_NOA_RPT_2(x) | BIT_NOA_RPT_2(v)) -/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET (Offset 0x147C) */ +/* 2 REG_NOA_REPORT_3 (Offset 0x165C) */ +#define BIT_SHIFT_NOA_RPT_3 0 +#define BIT_MASK_NOA_RPT_3 0xff +#define BIT_NOA_RPT_3(x) (((x) & BIT_MASK_NOA_RPT_3) << BIT_SHIFT_NOA_RPT_3) +#define BITS_NOA_RPT_3 (BIT_MASK_NOA_RPT_3 << BIT_SHIFT_NOA_RPT_3) +#define BIT_CLEAR_NOA_RPT_3(x) ((x) & (~BITS_NOA_RPT_3)) +#define BIT_GET_NOA_RPT_3(x) (((x) >> BIT_SHIFT_NOA_RPT_3) & BIT_MASK_NOA_RPT_3) +#define BIT_SET_NOA_RPT_3(x, v) (BIT_CLEAR_NOA_RPT_3(x) | BIT_NOA_RPT_3(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f -#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_P2PON_DIS_TXTIME 0 -#define BIT_MASK_P2PON_DIS_TXTIME 0xff -#define BIT_P2PON_DIS_TXTIME(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME) -#define BIT_GET_P2PON_DIS_TXTIME(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN BIT(15) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN BIT(14) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN BIT(13) +#define BIT_CLI3_PWR_ST_V1 BIT(12) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN BIT(11) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN BIT(10) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN BIT(9) +#define BIT_CLI2_PWR_ST_V1 BIT(8) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI3_PWRBIT_OW_EN BIT(7) -/* 2 REG_MACID_SHCUT_OFFSET (Offset 0x1480) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MACID_SHCUT_OFFSET_V1 0 -#define BIT_MASK_MACID_SHCUT_OFFSET_V1 0xff -#define BIT_MACID_SHCUT_OFFSET_V1(x) (((x) & BIT_MASK_MACID_SHCUT_OFFSET_V1) << BIT_SHIFT_MACID_SHCUT_OFFSET_V1) -#define BIT_GET_MACID_SHCUT_OFFSET_V1(x) (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET_V1) & BIT_MASK_MACID_SHCUT_OFFSET_V1) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN BIT(7) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI3_PWR_ST BIT(6) -/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ +#endif -#define BIT_R_FORCE_P1_RATEDOWN BIT(11) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_MU_TAB_SEL 8 -#define BIT_MASK_R_MU_TAB_SEL 0x7 -#define BIT_R_MU_TAB_SEL(x) (((x) & BIT_MASK_R_MU_TAB_SEL) << BIT_SHIFT_R_MU_TAB_SEL) -#define BIT_GET_R_MU_TAB_SEL(x) (((x) >> BIT_SHIFT_R_MU_TAB_SEL) & BIT_MASK_R_MU_TAB_SEL) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ -#define BIT_R_EN_MU_MIMO BIT(7) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN BIT(6) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI2_PWRBIT_OW_EN BIT(5) -/* 2 REG_MU_TX_CTL (Offset 0x14C0) */ +#endif -#define BIT_R_EN_REVERS_GTAB BIT(6) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_R_MU_TABLE_VALID 0 -#define BIT_MASK_R_MU_TABLE_VALID 0x3f -#define BIT_R_MU_TABLE_VALID(x) (((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID) -#define BIT_GET_R_MU_TABLE_VALID(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN BIT(5) -#define BIT_SHIFT_R_MU_STA_GTAB_VALID 0 -#define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID) -#define BIT_GET_R_MU_STA_GTAB_VALID(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0 -#define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION) << BIT_SHIFT_R_MU_STA_GTAB_POSITION) -#define BIT_GET_R_MU_STA_GTAB_POSITION(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) & BIT_MASK_R_MU_STA_GTAB_POSITION) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI2_PWR_ST BIT(4) -/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ +#endif -#define BIT_MU_DNGCNT_RST BIT(20) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_MU_DBGCNT_SEL 16 -#define BIT_MASK_MU_DBGCNT_SEL 0xf -#define BIT_MU_DBGCNT_SEL(x) (((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL) -#define BIT_GET_MU_DBGCNT_SEL(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI1_PWR_ST_V1 BIT(4) -#define BIT_SHIFT_MU_DNGCNT 0 -#define BIT_MASK_MU_DNGCNT 0xffff -#define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT) -#define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#endif +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI1_PWRBIT_OW_EN BIT(3) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_CPUMGQ_TX_TIMER (Offset 0x1500) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN BIT(3) -#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0 -#define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL -#define BIT_CPUMGQ_TX_TIMER_V1(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1) -#define BIT_GET_CPUMGQ_TX_TIMER_V1(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -/* 2 REG_PS_TIMER_A (Offset 0x1504) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI1_PWR_ST BIT(2) -#define BIT_SHIFT_PS_TIMER_A_V1 0 -#define BIT_MASK_PS_TIMER_A_V1 0xffffffffL -#define BIT_PS_TIMER_A_V1(x) (((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1) -#define BIT_GET_PS_TIMER_A_V1(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_PS_TIMER_B (Offset 0x1508) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN BIT(2) -#define BIT_SHIFT_PS_TIMER_B_V1 0 -#define BIT_MASK_PS_TIMER_B_V1 0xffffffffL -#define BIT_PS_TIMER_B_V1(x) (((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1) -#define BIT_GET_PS_TIMER_B_V1(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -/* 2 REG_PS_TIMER_C (Offset 0x150C) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI0_PWRBIT_OW_EN BIT(1) -#define BIT_SHIFT_PS_TIMER_C_V1 0 -#define BIT_MASK_PS_TIMER_C_V1 0xffffffffL -#define BIT_PS_TIMER_C_V1(x) (((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1) -#define BIT_GET_PS_TIMER_C_V1(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL (Offset 0x1510) */ +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ -#define BIT_CPUMGQ_TIMER_EN BIT(31) -#define BIT_CPUMGQ_TX_EN BIT(28) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN BIT(1) -#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24 -#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7 -#define BIT_CPUMGQ_TIMER_TSF_SEL(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) -#define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) +#endif -#define BIT_PS_TIMER_C_EN BIT(23) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16 -#define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7 -#define BIT_PS_TIMER_C_TSF_SEL(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL) -#define BIT_GET_PS_TIMER_C_TSF_SEL(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ -#define BIT_PS_TIMER_B_EN BIT(15) +#define BIT_CLI0_PWR_ST BIT(0) -#define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8 -#define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7 -#define BIT_PS_TIMER_B_TSF_SEL(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL) -#define BIT_GET_PS_TIMER_B_TSF_SEL(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL) +#endif -#define BIT_PS_TIMER_A_EN BIT(7) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0 -#define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7 -#define BIT_PS_TIMER_A_TSF_SEL(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL) -#define BIT_GET_PS_TIMER_A_TSF_SEL(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL) +/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#define BIT_CLI0_PWR_ST_V1 BIT(0) -/* 2 REG_CPUMGQ_TX_TIMER_EARLY (Offset 0x1514) */ +#endif +#if (HALMAC_8814B_SUPPORT) -#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0 -#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff -#define BIT_CPUMGQ_TX_TIMER_EARLY(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) -#define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ +#define BIT_FIX_MSDU_TAIL_WR BIT(12) +#define BIT_FIX_MSDU_SHIFT BIT(11) -/* 2 REG_PS_TIMER_A_EARLY (Offset 0x1515) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PS_TIMER_A_EARLY 0 -#define BIT_MASK_PS_TIMER_A_EARLY 0xff -#define BIT_PS_TIMER_A_EARLY(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY) -#define BIT_GET_PS_TIMER_A_EARLY(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY) +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ +#define BIT_WMAC_RXRST_NDP_TIMEOUT BIT(11) +#define BIT_WMAC_NDP_STANDBY_WAIT_RXEND BIT(10) +#define BIT_DUMMY_FCS_READY_MASK_EN BIT(9) -/* 2 REG_PS_TIMER_B_EARLY (Offset 0x1516) */ +#endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PS_TIMER_B_EARLY 0 -#define BIT_MASK_PS_TIMER_B_EARLY 0xff -#define BIT_PS_TIMER_B_EARLY(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY) -#define BIT_GET_PS_TIMER_B_EARLY(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY) +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ +#define BIT_RXFIFO_GNT_CUT BIT(8) -/* 2 REG_PS_TIMER_C_EARLY (Offset 0x1517) */ +#endif +#if (HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_PS_TIMER_C_EARLY 0 -#define BIT_MASK_PS_TIMER_C_EARLY 0xff -#define BIT_PS_TIMER_C_EARLY(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY) -#define BIT_GET_PS_TIMER_C_EARLY(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY) +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ +#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_V1 BIT(7) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ -/* 2 REG_BCN_PSR_RPT2 (Offset 0x1600) */ +#define BIT_WMAC_EXT_DBG_SEL_V1 BIT(6) +#endif -#define BIT_SHIFT_DTIM_CNT2 24 -#define BIT_MASK_DTIM_CNT2 0xff -#define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2) -#define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ -#define BIT_SHIFT_DTIM_PERIOD2 16 -#define BIT_MASK_DTIM_PERIOD2 0xff -#define BIT_DTIM_PERIOD2(x) (((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2) -#define BIT_GET_DTIM_PERIOD2(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2) +#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS BIT(5) -#define BIT_DTIM2 BIT(15) -#define BIT_TIM2 BIT(14) +#endif -#define BIT_SHIFT_PS_AID_2 0 -#define BIT_MASK_PS_AID_2 0x7ff -#define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2) -#define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ -/* 2 REG_BCN_PSR_RPT3 (Offset 0x1604) */ +#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA BIT(4) +#endif -#define BIT_SHIFT_DTIM_CNT3 24 -#define BIT_MASK_DTIM_CNT3 0xff -#define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3) -#define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ -#define BIT_SHIFT_DTIM_PERIOD3 16 -#define BIT_MASK_DTIM_PERIOD3 0xff -#define BIT_DTIM_PERIOD3(x) (((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3) -#define BIT_GET_DTIM_PERIOD3(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3) +#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN BIT(4) -#define BIT_DTIM3 BIT(15) -#define BIT_TIM3 BIT(14) +#endif -#define BIT_SHIFT_PS_AID_3 0 -#define BIT_MASK_PS_AID_3 0x7ff -#define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3) -#define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ -/* 2 REG_BCN_PSR_RPT4 (Offset 0x1608) */ +#define BIT_RX_DMA_BYPASS_CHECK_MGTBIT_RX_DMA_BYPASS_CHECK_MGT BIT(3) +#endif -#define BIT_SHIFT_DTIM_CNT4 24 -#define BIT_MASK_DTIM_CNT4 0xff -#define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4) -#define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ -#define BIT_SHIFT_DTIM_PERIOD4 16 -#define BIT_MASK_DTIM_PERIOD4 0xff -#define BIT_DTIM_PERIOD4(x) (((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4) -#define BIT_GET_DTIM_PERIOD4(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4) +#define BIT_PATTERN_MATCH_FIX_EN BIT(3) -#define BIT_DTIM4 BIT(15) -#define BIT_TIM4 BIT(14) +#endif -#define BIT_SHIFT_PS_AID_4 0 -#define BIT_MASK_PS_AID_4 0x7ff -#define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4) -#define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_GENERAL_OPTION (Offset 0x1664) */ -/* 2 REG_A1_ADDR_MASK (Offset 0x160C) */ +#define BIT_TXSERV_FIELD_SEL BIT(2) +#define BIT_RXVHT_LEN_SEL BIT(1) +#define BIT_RXMIC_PROTECT_EN BIT(0) +#endif -#define BIT_SHIFT_A1_ADDR_MASK 0 -#define BIT_MASK_A1_ADDR_MASK 0xffffffffL -#define BIT_A1_ADDR_MASK(x) (((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK) -#define BIT_GET_A1_ADDR_MASK(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK) +#if (HALMAC_8814B_SUPPORT) +/* 2 REG_FWPHYFF_RCR (Offset 0x1668) */ -/* 2 REG_MACID2 (Offset 0x1620) */ +#define BIT_RCR2_AAMSDU BIT(25) +#define BIT_RCR2_CBSSID_BCN BIT(24) +#define BIT_RCR2_ACRC32 BIT(23) +#define BIT_RCR2_TA_BCN BIT(22) +#define BIT_RCR2_CBSSID_DATA BIT(21) +#define BIT_RCR2_ADD3 BIT(20) +#define BIT_RCR2_AB BIT(19) +#define BIT_RCR2_AM BIT(18) +#define BIT_RCR2_APM BIT(17) +#define BIT_RCR2_AAP BIT(16) +#define BIT_RCR1_AAMSDU BIT(9) +#define BIT_RCR1_CBSSID_BCN BIT(8) +#define BIT_RCR1_ACRC32 BIT(7) +#define BIT_RCR1_TA_BCN BIT(6) +#define BIT_RCR1_CBSSID_DATA BIT(5) +#define BIT_RCR1_ADD3 BIT(4) +#define BIT_RCR1_AB BIT(3) +#define BIT_RCR1_AM BIT(2) +#define BIT_RCR1_APM BIT(1) +#define BIT_RCR1_AAP BIT(0) +/* 2 REG_ADDRCAM_WRITE_CONTENT (Offset 0x166C) */ -#define BIT_SHIFT_MACID2 0 -#define BIT_MASK_MACID2 0xffffffffffffL -#define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2) -#define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2) +#define BIT_SHIFT_ADDRCAM_WDATA 0 +#define BIT_MASK_ADDRCAM_WDATA 0xffffffffL +#define BIT_ADDRCAM_WDATA(x) \ + (((x) & BIT_MASK_ADDRCAM_WDATA) << BIT_SHIFT_ADDRCAM_WDATA) +#define BITS_ADDRCAM_WDATA (BIT_MASK_ADDRCAM_WDATA << BIT_SHIFT_ADDRCAM_WDATA) +#define BIT_CLEAR_ADDRCAM_WDATA(x) ((x) & (~BITS_ADDRCAM_WDATA)) +#define BIT_GET_ADDRCAM_WDATA(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_WDATA) & BIT_MASK_ADDRCAM_WDATA) +#define BIT_SET_ADDRCAM_WDATA(x, v) \ + (BIT_CLEAR_ADDRCAM_WDATA(x) | BIT_ADDRCAM_WDATA(v)) +/* 2 REG_ADDRCAM_READ_CONTENT (Offset 0x1670) */ -/* 2 REG_BSSID2 (Offset 0x1628) */ +#define BIT_SHIFT_ADDRCAM_RDATA 0 +#define BIT_MASK_ADDRCAM_RDATA 0xffffffffL +#define BIT_ADDRCAM_RDATA(x) \ + (((x) & BIT_MASK_ADDRCAM_RDATA) << BIT_SHIFT_ADDRCAM_RDATA) +#define BITS_ADDRCAM_RDATA (BIT_MASK_ADDRCAM_RDATA << BIT_SHIFT_ADDRCAM_RDATA) +#define BIT_CLEAR_ADDRCAM_RDATA(x) ((x) & (~BITS_ADDRCAM_RDATA)) +#define BIT_GET_ADDRCAM_RDATA(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_RDATA) & BIT_MASK_ADDRCAM_RDATA) +#define BIT_SET_ADDRCAM_RDATA(x, v) \ + (BIT_CLEAR_ADDRCAM_RDATA(x) | BIT_ADDRCAM_RDATA(v)) +/* 2 REG_ADDRCAM_CFG (Offset 0x1674) */ -#define BIT_SHIFT_BSSID2 0 -#define BIT_MASK_BSSID2 0xffffffffffffL -#define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2) -#define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2) +#define BIT_ADDRCAM_POLL BIT(31) +#define BIT__ADDRCAM_WT_EN BIT(30) +#define BIT_CLRADDRCAM BIT(29) +#define BIT_SHIFT__ADDRCAM_ADDR 8 +#define BIT_MASK__ADDRCAM_ADDR 0x3ff +#define BIT__ADDRCAM_ADDR(x) \ + (((x) & BIT_MASK__ADDRCAM_ADDR) << BIT_SHIFT__ADDRCAM_ADDR) +#define BITS__ADDRCAM_ADDR (BIT_MASK__ADDRCAM_ADDR << BIT_SHIFT__ADDRCAM_ADDR) +#define BIT_CLEAR__ADDRCAM_ADDR(x) ((x) & (~BITS__ADDRCAM_ADDR)) +#define BIT_GET__ADDRCAM_ADDR(x) \ + (((x) >> BIT_SHIFT__ADDRCAM_ADDR) & BIT_MASK__ADDRCAM_ADDR) +#define BIT_SET__ADDRCAM_ADDR(x, v) \ + (BIT_CLEAR__ADDRCAM_ADDR(x) | BIT__ADDRCAM_ADDR(v)) -/* 2 REG_MACID3 (Offset 0x1630) */ +#define BIT_SHIFT_ADDRCAM_RANGE 0 +#define BIT_MASK_ADDRCAM_RANGE 0x7f +#define BIT_ADDRCAM_RANGE(x) \ + (((x) & BIT_MASK_ADDRCAM_RANGE) << BIT_SHIFT_ADDRCAM_RANGE) +#define BITS_ADDRCAM_RANGE (BIT_MASK_ADDRCAM_RANGE << BIT_SHIFT_ADDRCAM_RANGE) +#define BIT_CLEAR_ADDRCAM_RANGE(x) ((x) & (~BITS_ADDRCAM_RANGE)) +#define BIT_GET_ADDRCAM_RANGE(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_RANGE) & BIT_MASK_ADDRCAM_RANGE) +#define BIT_SET_ADDRCAM_RANGE(x, v) \ + (BIT_CLEAR_ADDRCAM_RANGE(x) | BIT_ADDRCAM_RANGE(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CSI_RRSR (Offset 0x1678) */ + +#define BIT_CSI_LDPC_EN BIT(29) +#define BIT_CSI_STBC_EN BIT(28) + +#define BIT_SHIFT_CSI_RRSC_BITMAP 4 +#define BIT_MASK_CSI_RRSC_BITMAP 0xffffff +#define BIT_CSI_RRSC_BITMAP(x) \ + (((x) & BIT_MASK_CSI_RRSC_BITMAP) << BIT_SHIFT_CSI_RRSC_BITMAP) +#define BITS_CSI_RRSC_BITMAP \ + (BIT_MASK_CSI_RRSC_BITMAP << BIT_SHIFT_CSI_RRSC_BITMAP) +#define BIT_CLEAR_CSI_RRSC_BITMAP(x) ((x) & (~BITS_CSI_RRSC_BITMAP)) +#define BIT_GET_CSI_RRSC_BITMAP(x) \ + (((x) >> BIT_SHIFT_CSI_RRSC_BITMAP) & BIT_MASK_CSI_RRSC_BITMAP) +#define BIT_SET_CSI_RRSC_BITMAP(x, v) \ + (BIT_CLEAR_CSI_RRSC_BITMAP(x) | BIT_CSI_RRSC_BITMAP(v)) + +#define BIT_SHIFT_OFDM_LEN_TH 0 +#define BIT_MASK_OFDM_LEN_TH 0xf +#define BIT_OFDM_LEN_TH(x) \ + (((x) & BIT_MASK_OFDM_LEN_TH) << BIT_SHIFT_OFDM_LEN_TH) +#define BITS_OFDM_LEN_TH (BIT_MASK_OFDM_LEN_TH << BIT_SHIFT_OFDM_LEN_TH) +#define BIT_CLEAR_OFDM_LEN_TH(x) ((x) & (~BITS_OFDM_LEN_TH)) +#define BIT_GET_OFDM_LEN_TH(x) \ + (((x) >> BIT_SHIFT_OFDM_LEN_TH) & BIT_MASK_OFDM_LEN_TH) +#define BIT_SET_OFDM_LEN_TH(x, v) \ + (BIT_CLEAR_OFDM_LEN_TH(x) | BIT_OFDM_LEN_TH(v)) + +#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE 0 +#define BIT_MASK_WMAC_MULBK_PAGE_SIZE 0xff +#define BIT_WMAC_MULBK_PAGE_SIZE(x) \ + (((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE) \ + << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) +#define BITS_WMAC_MULBK_PAGE_SIZE \ + (BIT_MASK_WMAC_MULBK_PAGE_SIZE << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) +#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE)) +#define BIT_GET_WMAC_MULBK_PAGE_SIZE(x) \ + (((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) & \ + BIT_MASK_WMAC_MULBK_PAGE_SIZE) +#define BIT_SET_WMAC_MULBK_PAGE_SIZE(x, v) \ + (BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) | BIT_WMAC_MULBK_PAGE_SIZE(v)) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ -#define BIT_SHIFT_MACID3 0 -#define BIT_MASK_MACID3 0xffffffffffffL -#define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3) -#define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3) +#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) +#endif -/* 2 REG_BSSID3 (Offset 0x1638) */ +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_MU_BF_OPTION (Offset 0x167C) */ -#define BIT_SHIFT_BSSID3 0 -#define BIT_MASK_BSSID3 0xffffffffffffL -#define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3) -#define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3) +#define BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) +#endif -/* 2 REG_MACID4 (Offset 0x1640) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) +/* 2 REG_WMAC_PAUSE_BB_CLR_TH (Offset 0x167D) */ -#define BIT_SHIFT_MACID4 0 -#define BIT_MASK_MACID4 0xffffffffffffL -#define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4) -#define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4) +#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0 +#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff +#define BIT_WMAC_PAUSE_BB_CLR_TH(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) +#define BITS_WMAC_PAUSE_BB_CLR_TH \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) | BIT_WMAC_PAUSE_BB_CLR_TH(v)) +#endif -/* 2 REG_BSSID4 (Offset 0x1648) */ +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_MU_ARB (Offset 0x167E) */ -#define BIT_SHIFT_BSSID4 0 -#define BIT_MASK_BSSID4 0xffffffffffffL -#define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4) -#define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4) +#define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7) +#define BIT_WMAC_ARB_SW_EN BIT(6) +#define BIT_SHIFT_WMAC_ARB_SW_STATE 0 +#define BIT_MASK_WMAC_ARB_SW_STATE 0x3f +#define BIT_WMAC_ARB_SW_STATE(x) \ + (((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE) +#define BITS_WMAC_ARB_SW_STATE \ + (BIT_MASK_WMAC_ARB_SW_STATE << BIT_SHIFT_WMAC_ARB_SW_STATE) +#define BIT_CLEAR_WMAC_ARB_SW_STATE(x) ((x) & (~BITS_WMAC_ARB_SW_STATE)) +#define BIT_GET_WMAC_ARB_SW_STATE(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE) +#define BIT_SET_WMAC_ARB_SW_STATE(x, v) \ + (BIT_CLEAR_WMAC_ARB_SW_STATE(x) | BIT_WMAC_ARB_SW_STATE(v)) #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ +#define BIT_NOCHK_BFPOLL_BMP BIT(7) -/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ +#endif -#define BIT_CLI3_PWRBIT_OW_EN BIT(7) -#define BIT_CLI3_PWR_ST BIT(6) -#define BIT_CLI2_PWRBIT_OW_EN BIT(5) -#define BIT_CLI2_PWR_ST BIT(4) -#define BIT_CLI1_PWRBIT_OW_EN BIT(3) -#define BIT_CLI1_PWR_ST BIT(2) -#define BIT_CLI0_PWRBIT_OW_EN BIT(1) -#define BIT_CLI0_PWR_ST BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ +/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ -#define BIT_WMAC_RESP_NONSTA1_DIS BIT(7) +#define BIT_SHIFT_WMAC_MU_DBGSEL 5 +#define BIT_MASK_WMAC_MU_DBGSEL 0x3 +#define BIT_WMAC_MU_DBGSEL(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL) +#define BITS_WMAC_MU_DBGSEL \ + (BIT_MASK_WMAC_MU_DBGSEL << BIT_SHIFT_WMAC_MU_DBGSEL) +#define BIT_CLEAR_WMAC_MU_DBGSEL(x) ((x) & (~BITS_WMAC_MU_DBGSEL)) +#define BIT_GET_WMAC_MU_DBGSEL(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL) +#define BIT_SET_WMAC_MU_DBGSEL(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL(x) | BIT_WMAC_MU_DBGSEL(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) - - -/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ +/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ -#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) +#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0 +#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f +#define BIT_WMAC_MU_CPRD_TIMEOUT(x) \ + (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) +#define BITS_WMAC_MU_CPRD_TIMEOUT \ + (BIT_MASK_WMAC_MU_CPRD_TIMEOUT << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) +#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT)) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) & \ + BIT_MASK_WMAC_MU_CPRD_TIMEOUT) +#define BIT_SET_WMAC_MU_CPRD_TIMEOUT(x, v) \ + (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) | BIT_WMAC_MU_CPRD_TIMEOUT(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +/* 2 REG_WMAC_MU_BF_CTL (Offset 0x1680) */ +#define BIT_WMAC_INVLD_BFPRT_CHK BIT(15) +#define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14) + +#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12 +#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3 +#define BIT_WMAC_MU_BFRPTSEG_SEL(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) +#define BITS_WMAC_MU_BFRPTSEG_SEL \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) | BIT_WMAC_MU_BFRPTSEG_SEL(v)) + +#define BIT_SHIFT_WMAC_MU_BF_MYAID 0 +#define BIT_MASK_WMAC_MU_BF_MYAID 0xfff +#define BIT_WMAC_MU_BF_MYAID(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID) +#define BITS_WMAC_MU_BF_MYAID \ + (BIT_MASK_WMAC_MU_BF_MYAID << BIT_SHIFT_WMAC_MU_BF_MYAID) +#define BIT_CLEAR_WMAC_MU_BF_MYAID(x) ((x) & (~BITS_WMAC_MU_BF_MYAID)) +#define BIT_GET_WMAC_MU_BF_MYAID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID) +#define BIT_SET_WMAC_MU_BF_MYAID(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID(x) | BIT_WMAC_MU_BF_MYAID(v)) + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ +/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ -#define BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1 13 +#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1 0x7 +#define BIT_BFRPT_PARA_USERID_SEL_V1(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) +#define BITS_BFRPT_PARA_USERID_SEL_V1 \ + (BIT_MASK_BFRPT_PARA_USERID_SEL_V1 \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x) \ + ((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1)) +#define BIT_GET_BFRPT_PARA_USERID_SEL_V1(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL_V1) +#define BIT_SET_BFRPT_PARA_USERID_SEL_V1(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x) | \ + BIT_BFRPT_PARA_USERID_SEL_V1(v)) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL 12 +#define BIT_MASK_BFRPT_PARA_USERID_SEL 0x7 +#define BIT_BFRPT_PARA_USERID_SEL(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL) +#define BITS_BFRPT_PARA_USERID_SEL \ + (BIT_MASK_BFRPT_PARA_USERID_SEL << BIT_SHIFT_BFRPT_PARA_USERID_SEL) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) ((x) & (~BITS_BFRPT_PARA_USERID_SEL)) +#define BIT_GET_BFRPT_PARA_USERID_SEL(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL) +#define BIT_SET_BFRPT_PARA_USERID_SEL(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) | BIT_BFRPT_PARA_USERID_SEL(v)) -/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ +#endif +#if (HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4 -#define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3 -#define BIT_WMAC_TXMU_ACKPOLICY(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY) -#define BIT_GET_WMAC_TXMU_ACKPOLICY(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY) +/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ +#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12 +#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7 +#define BIT_BIT_BFRPT_PARA_USERID_SEL(x) \ + (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) \ + << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) +#define BITS_BIT_BFRPT_PARA_USERID_SEL \ + (BIT_MASK_BIT_BFRPT_PARA_USERID_SEL \ + << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) +#define BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x) \ + ((x) & (~BITS_BIT_BFRPT_PARA_USERID_SEL)) +#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x) \ + (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) & \ + BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) +#define BIT_SET_BIT_BFRPT_PARA_USERID_SEL(x, v) \ + (BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x) | \ + BIT_BIT_BFRPT_PARA_USERID_SEL(v)) -#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1 -#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7 -#define BIT_WMAC_MU_BFEE_PORT_SEL(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) -#define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) +#endif -#define BIT_WMAC_MU_BFEE_DIS BIT(0) +#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_WMAC_PAUSE_BB_CLR_TH (Offset 0x167D) */ +/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ +#define BIT_SHIFT_BFRPT_PARA 0 +#define BIT_MASK_BFRPT_PARA 0xfff +#define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA) +#define BITS_BFRPT_PARA (BIT_MASK_BFRPT_PARA << BIT_SHIFT_BFRPT_PARA) +#define BIT_CLEAR_BFRPT_PARA(x) ((x) & (~BITS_BFRPT_PARA)) +#define BIT_GET_BFRPT_PARA(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA) +#define BIT_SET_BFRPT_PARA(x, v) (BIT_CLEAR_BFRPT_PARA(x) | BIT_BFRPT_PARA(v)) -#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0 -#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff -#define BIT_WMAC_PAUSE_BB_CLR_TH(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) -#define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) +#endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_WMAC_MU_ARB (Offset 0x167E) */ +/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ + +#define BIT_SHIFT_BFRPT_PARA_V1 0 +#define BIT_MASK_BFRPT_PARA_V1 0x1fff +#define BIT_BFRPT_PARA_V1(x) \ + (((x) & BIT_MASK_BFRPT_PARA_V1) << BIT_SHIFT_BFRPT_PARA_V1) +#define BITS_BFRPT_PARA_V1 (BIT_MASK_BFRPT_PARA_V1 << BIT_SHIFT_BFRPT_PARA_V1) +#define BIT_CLEAR_BFRPT_PARA_V1(x) ((x) & (~BITS_BFRPT_PARA_V1)) +#define BIT_GET_BFRPT_PARA_V1(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_V1) & BIT_MASK_BFRPT_PARA_V1) +#define BIT_SET_BFRPT_PARA_V1(x, v) \ + (BIT_CLEAR_BFRPT_PARA_V1(x) | BIT_BFRPT_PARA_V1(v)) -#define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7) -#define BIT_WMAC_ARB_SW_EN BIT(6) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_ARB_SW_STATE 0 -#define BIT_MASK_WMAC_ARB_SW_STATE 0x3f -#define BIT_WMAC_ARB_SW_STATE(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE) -#define BIT_GET_WMAC_ARB_SW_STATE(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ +#define BIT_STATUS_BFEE2 BIT(10) -/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_MU_DBGSEL 5 -#define BIT_MASK_WMAC_MU_DBGSEL 0x3 -#define BIT_WMAC_MU_DBGSEL(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL) -#define BIT_GET_WMAC_MU_DBGSEL(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ +#define BIT_WMAC_MU_BFEE2_EN BIT(9) -#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0 -#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f -#define BIT_WMAC_MU_CPRD_TIMEOUT(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) -#define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) +#endif +#if (HALMAC_8198F_SUPPORT) -/* 2 REG_WMAC_MU_BF_CTL (Offset 0x1680) */ +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ -#define BIT_WMAC_INVLD_BFPRT_CHK BIT(15) -#define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14) +#define BIT_WMAC_MU_BFEE2_USER_EN BIT(9) -#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12 -#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3 -#define BIT_WMAC_MU_BFRPTSEG_SEL(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) -#define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_MU_BF_MYAID 0 -#define BIT_MASK_WMAC_MU_BF_MYAID 0xfff -#define BIT_WMAC_MU_BF_MYAID(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID) -#define BIT_GET_WMAC_MU_BF_MYAID(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ +#define BIT_SHIFT_WMAC_MU_BFEE2_AID 0 +#define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff +#define BIT_WMAC_MU_BFEE2_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID) +#define BITS_WMAC_MU_BFEE2_AID \ + (BIT_MASK_WMAC_MU_BFEE2_AID << BIT_SHIFT_WMAC_MU_BFEE2_AID) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID(x) ((x) & (~BITS_WMAC_MU_BFEE2_AID)) +#define BIT_GET_WMAC_MU_BFEE2_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID) +#define BIT_SET_WMAC_MU_BFEE2_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID(x) | BIT_WMAC_MU_BFEE2_AID(v)) -#define BIT_SHIFT_BFRPT_PARA 0 -#define BIT_MASK_BFRPT_PARA 0xfff -#define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA) -#define BIT_GET_BFRPT_PARA(x) (((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ +#define BIT_STATUS_BFEE3 BIT(10) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ +#define BIT_WMAC_MU_BFEE3_EN BIT(9) -/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ +#endif +#if (HALMAC_8198F_SUPPORT) -#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12 -#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7 -#define BIT_BIT_BFRPT_PARA_USERID_SEL(x) (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) -#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x) (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ +#define BIT_WMAC_MU_BFEE3_USER_EN BIT(9) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ -/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ +#define BIT_SHIFT_WMAC_MU_BFEE3_AID 0 +#define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff +#define BIT_WMAC_MU_BFEE3_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID) +#define BITS_WMAC_MU_BFEE3_AID \ + (BIT_MASK_WMAC_MU_BFEE3_AID << BIT_SHIFT_WMAC_MU_BFEE3_AID) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID(x) ((x) & (~BITS_WMAC_MU_BFEE3_AID)) +#define BIT_GET_WMAC_MU_BFEE3_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID) +#define BIT_SET_WMAC_MU_BFEE3_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID(x) | BIT_WMAC_MU_BFEE3_AID(v)) -#define BIT_STATUS_BFEE2 BIT(10) -#define BIT_WMAC_MU_BFEE2_EN BIT(9) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4 (Offset 0x1688) */ -#define BIT_SHIFT_WMAC_MU_BFEE2_AID 0 -#define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff -#define BIT_WMAC_MU_BFEE2_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID) -#define BIT_GET_WMAC_MU_BFEE2_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID) +#define BIT_STATUS_BFEE4 BIT(10) +#define BIT_WMAC_MU_BFEE4_EN BIT(9) +#define BIT_SHIFT_WMAC_MU_BFEE4_AID 0 +#define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff +#define BIT_WMAC_MU_BFEE4_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID) +#define BITS_WMAC_MU_BFEE4_AID \ + (BIT_MASK_WMAC_MU_BFEE4_AID << BIT_SHIFT_WMAC_MU_BFEE4_AID) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID(x) ((x) & (~BITS_WMAC_MU_BFEE4_AID)) +#define BIT_GET_WMAC_MU_BFEE4_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID) +#define BIT_SET_WMAC_MU_BFEE4_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID(x) | BIT_WMAC_MU_BFEE4_AID(v)) -/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ +#endif -#define BIT_STATUS_BFEE3 BIT(10) -#define BIT_WMAC_MU_BFEE3_EN BIT(9) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_WMAC_MU_BFEE3_AID 0 -#define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff -#define BIT_WMAC_MU_BFEE3_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID) -#define BIT_GET_WMAC_MU_BFEE3_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ +#define BIT_STATUS_BFEE5 BIT(10) -/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4 (Offset 0x1688) */ +#endif -#define BIT_STATUS_BFEE4 BIT(10) -#define BIT_WMAC_MU_BFEE4_EN BIT(9) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_MU_BFEE4_AID 0 -#define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff -#define BIT_WMAC_MU_BFEE4_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID) -#define BIT_GET_WMAC_MU_BFEE4_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ +#define BIT_BIT_STATUS_BFEE5 BIT(10) #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ +#define BIT_WMAC_MU_BFEE5_EN BIT(9) -/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ +#define BIT_SHIFT_WMAC_MU_BFEE5_AID 0 +#define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff +#define BIT_WMAC_MU_BFEE5_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID) +#define BITS_WMAC_MU_BFEE5_AID \ + (BIT_MASK_WMAC_MU_BFEE5_AID << BIT_SHIFT_WMAC_MU_BFEE5_AID) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID(x) ((x) & (~BITS_WMAC_MU_BFEE5_AID)) +#define BIT_GET_WMAC_MU_BFEE5_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID) +#define BIT_SET_WMAC_MU_BFEE5_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID(x) | BIT_WMAC_MU_BFEE5_AID(v)) -#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55) -#define BIT_R_WMAC_RXRST_DLY BIT(54) -#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53) -#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52) -#define BIT_STATUS_BFEE5 BIT(10) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6 (Offset 0x168C) */ -#endif +#define BIT_STATUS_BFEE6 BIT(10) +#define BIT_WMAC_MU_BFEE6_EN BIT(9) +#define BIT_SHIFT_WMAC_MU_BFEE6_AID 0 +#define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff +#define BIT_WMAC_MU_BFEE6_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID) +#define BITS_WMAC_MU_BFEE6_AID \ + (BIT_MASK_WMAC_MU_BFEE6_AID << BIT_SHIFT_WMAC_MU_BFEE6_AID) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID(x) ((x) & (~BITS_WMAC_MU_BFEE6_AID)) +#define BIT_GET_WMAC_MU_BFEE6_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID) +#define BIT_SET_WMAC_MU_BFEE6_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID(x) | BIT_WMAC_MU_BFEE6_AID(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ -#define BIT_BIT_STATUS_BFEE5 BIT(10) +#define BIT_BIT_STATUS_BFEE4 BIT(10) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ +#define BIT_STATUS_BFEE7 BIT(10) -/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ +#endif -#define BIT_WMAC_MU_BFEE5_EN BIT(9) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_MU_BFEE5_AID 0 -#define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff -#define BIT_WMAC_MU_BFEE5_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID) -#define BIT_GET_WMAC_MU_BFEE5_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID) +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ +#define BIT_WMAC_MU_BFEE7_EN BIT(9) -/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6 (Offset 0x168C) */ +#define BIT_SHIFT_WMAC_MU_BFEE7_AID 0 +#define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff +#define BIT_WMAC_MU_BFEE7_AID(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID) +#define BITS_WMAC_MU_BFEE7_AID \ + (BIT_MASK_WMAC_MU_BFEE7_AID << BIT_SHIFT_WMAC_MU_BFEE7_AID) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID(x) ((x) & (~BITS_WMAC_MU_BFEE7_AID)) +#define BIT_GET_WMAC_MU_BFEE7_AID(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID) +#define BIT_SET_WMAC_MU_BFEE7_AID(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID(x) | BIT_WMAC_MU_BFEE7_AID(v)) -#define BIT_STATUS_BFEE6 BIT(10) -#define BIT_WMAC_MU_BFEE6_EN BIT(9) +/* 2 REG_WMAC_BB_STOP_RX_COUNTER (Offset 0x1690) */ -#define BIT_SHIFT_WMAC_MU_BFEE6_AID 0 -#define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff -#define BIT_WMAC_MU_BFEE6_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID) -#define BIT_GET_WMAC_MU_BFEE6_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID) +#define BIT_RST_ALL_COUNTER BIT(31) + +#define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16 +#define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff +#define BIT_ABORT_RX_VBON_COUNTER(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER) +#define BITS_ABORT_RX_VBON_COUNTER \ + (BIT_MASK_ABORT_RX_VBON_COUNTER << BIT_SHIFT_ABORT_RX_VBON_COUNTER) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) ((x) & (~BITS_ABORT_RX_VBON_COUNTER)) +#define BIT_GET_ABORT_RX_VBON_COUNTER(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER) +#define BIT_SET_ABORT_RX_VBON_COUNTER(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) | BIT_ABORT_RX_VBON_COUNTER(v)) + +#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8 +#define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff +#define BIT_ABORT_RX_RDRDY_COUNTER(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) +#define BITS_ABORT_RX_RDRDY_COUNTER \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x) | BIT_ABORT_RX_RDRDY_COUNTER(v)) + +#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0 +#define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff +#define BIT_VBON_EARLY_FALLING_COUNTER(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) +#define BITS_VBON_EARLY_FALLING_COUNTER \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER(v)) +/* 2 REG_WMAC_PLCP_MONITOR (Offset 0x1694) */ -/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ +#define BIT_WMAC_PLCP_TRX_SEL BIT(31) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28 +#define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7 +#define BIT_WMAC_PLCP_RDSIG_SEL(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) +#define BITS_WMAC_PLCP_RDSIG_SEL \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) | BIT_WMAC_PLCP_RDSIG_SEL(v)) + +#define BIT_SHIFT_WMAC_RATE_IDX 24 +#define BIT_MASK_WMAC_RATE_IDX 0xf +#define BIT_WMAC_RATE_IDX(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX) +#define BITS_WMAC_RATE_IDX (BIT_MASK_WMAC_RATE_IDX << BIT_SHIFT_WMAC_RATE_IDX) +#define BIT_CLEAR_WMAC_RATE_IDX(x) ((x) & (~BITS_WMAC_RATE_IDX)) +#define BIT_GET_WMAC_RATE_IDX(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX) +#define BIT_SET_WMAC_RATE_IDX(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX(x) | BIT_WMAC_RATE_IDX(v)) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG 0 +#define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff +#define BIT_WMAC_PLCP_RDSIG(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG) +#define BITS_WMAC_PLCP_RDSIG \ + (BIT_MASK_WMAC_PLCP_RDSIG << BIT_SHIFT_WMAC_PLCP_RDSIG) +#define BIT_CLEAR_WMAC_PLCP_RDSIG(x) ((x) & (~BITS_WMAC_PLCP_RDSIG)) +#define BIT_GET_WMAC_PLCP_RDSIG(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG) +#define BIT_SET_WMAC_PLCP_RDSIG(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG(x) | BIT_WMAC_PLCP_RDSIG(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_BIT_STATUS_BFEE4 BIT(10) -#define BIT_WMAC_MU_BFEE7_EN BIT(9) +/* 2 REG_WMAC_PLCP_MONITOR_MUTX (Offset 0x1698) */ -#define BIT_SHIFT_WMAC_MU_BFEE7_AID 0 -#define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff -#define BIT_WMAC_MU_BFEE7_AID(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID) -#define BIT_GET_WMAC_MU_BFEE7_AID(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID) +#define BIT_WMAC_MUTX_IDX BIT(24) +#endif -/* 2 REG_WMAC_BB_STOP_RX_COUNTER (Offset 0x1690) */ +#if (HALMAC_8814B_SUPPORT) -#define BIT_RST_ALL_COUNTER BIT(31) +/* 2 REG_WMAC_DEBUG_PORT (Offset 0x1698) */ -#define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16 -#define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff -#define BIT_ABORT_RX_VBON_COUNTER(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER) << BIT_SHIFT_ABORT_RX_VBON_COUNTER) -#define BIT_GET_ABORT_RX_VBON_COUNTER(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) & BIT_MASK_ABORT_RX_VBON_COUNTER) +#define BIT_SHIFT_WMAC_DEBUG_PORT 0 +#define BIT_MASK_WMAC_DEBUG_PORT 0xffffffffL +#define BIT_WMAC_DEBUG_PORT(x) \ + (((x) & BIT_MASK_WMAC_DEBUG_PORT) << BIT_SHIFT_WMAC_DEBUG_PORT) +#define BITS_WMAC_DEBUG_PORT \ + (BIT_MASK_WMAC_DEBUG_PORT << BIT_SHIFT_WMAC_DEBUG_PORT) +#define BIT_CLEAR_WMAC_DEBUG_PORT(x) ((x) & (~BITS_WMAC_DEBUG_PORT)) +#define BIT_GET_WMAC_DEBUG_PORT(x) \ + (((x) >> BIT_SHIFT_WMAC_DEBUG_PORT) & BIT_MASK_WMAC_DEBUG_PORT) +#define BIT_SET_WMAC_DEBUG_PORT(x, v) \ + (BIT_CLEAR_WMAC_DEBUG_PORT(x) | BIT_WMAC_DEBUG_PORT(v)) +#endif -#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8 -#define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff -#define BIT_ABORT_RX_RDRDY_COUNTER(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) -#define BIT_GET_ABORT_RX_RDRDY_COUNTER(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) +/* 2 REG_WMAC_CSIDMA_CFG (Offset 0x169C) */ -#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0 -#define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff -#define BIT_VBON_EARLY_FALLING_COUNTER(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) -#define BIT_GET_VBON_EARLY_FALLING_COUNTER(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) +#define BIT_SHIFT_CSI_SEG_SIZE 16 +#define BIT_MASK_CSI_SEG_SIZE 0xfff +#define BIT_CSI_SEG_SIZE(x) \ + (((x) & BIT_MASK_CSI_SEG_SIZE) << BIT_SHIFT_CSI_SEG_SIZE) +#define BITS_CSI_SEG_SIZE (BIT_MASK_CSI_SEG_SIZE << BIT_SHIFT_CSI_SEG_SIZE) +#define BIT_CLEAR_CSI_SEG_SIZE(x) ((x) & (~BITS_CSI_SEG_SIZE)) +#define BIT_GET_CSI_SEG_SIZE(x) \ + (((x) >> BIT_SHIFT_CSI_SEG_SIZE) & BIT_MASK_CSI_SEG_SIZE) +#define BIT_SET_CSI_SEG_SIZE(x, v) \ + (BIT_CLEAR_CSI_SEG_SIZE(x) | BIT_CSI_SEG_SIZE(v)) +#define BIT_SHIFT_CSI_START_PAGE 0 +#define BIT_MASK_CSI_START_PAGE 0xfff +#define BIT_CSI_START_PAGE(x) \ + (((x) & BIT_MASK_CSI_START_PAGE) << BIT_SHIFT_CSI_START_PAGE) +#define BITS_CSI_START_PAGE \ + (BIT_MASK_CSI_START_PAGE << BIT_SHIFT_CSI_START_PAGE) +#define BIT_CLEAR_CSI_START_PAGE(x) ((x) & (~BITS_CSI_START_PAGE)) +#define BIT_GET_CSI_START_PAGE(x) \ + (((x) >> BIT_SHIFT_CSI_START_PAGE) & BIT_MASK_CSI_START_PAGE) +#define BIT_SET_CSI_START_PAGE(x, v) \ + (BIT_CLEAR_CSI_START_PAGE(x) | BIT_CSI_START_PAGE(v)) -/* 2 REG_WMAC_PLCP_MONITOR (Offset 0x1694) */ +#endif -#define BIT_WMAC_PLCP_TRX_SEL BIT(31) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28 -#define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7 -#define BIT_WMAC_PLCP_RDSIG_SEL(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) -#define BIT_GET_WMAC_PLCP_RDSIG_SEL(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) +/* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */ +#define BIT_SHIFT_TA0 0 +#define BIT_MASK_TA0 0xffffffffffffL +#define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0) +#define BITS_TA0 (BIT_MASK_TA0 << BIT_SHIFT_TA0) +#define BIT_CLEAR_TA0(x) ((x) & (~BITS_TA0)) +#define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0) +#define BIT_SET_TA0(x, v) (BIT_CLEAR_TA0(x) | BIT_TA0(v)) -#define BIT_SHIFT_WMAC_RATE_IDX 24 -#define BIT_MASK_WMAC_RATE_IDX 0xf -#define BIT_WMAC_RATE_IDX(x) (((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX) -#define BIT_GET_WMAC_RATE_IDX(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_WMAC_PLCP_RDSIG 0 -#define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff -#define BIT_WMAC_PLCP_RDSIG(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG) -#define BIT_GET_WMAC_PLCP_RDSIG(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG) +/* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */ +#define BIT_SHIFT_TA0_V1 0 +#define BIT_MASK_TA0_V1 0xffffffffL +#define BIT_TA0_V1(x) (((x) & BIT_MASK_TA0_V1) << BIT_SHIFT_TA0_V1) +#define BITS_TA0_V1 (BIT_MASK_TA0_V1 << BIT_SHIFT_TA0_V1) +#define BIT_CLEAR_TA0_V1(x) ((x) & (~BITS_TA0_V1)) +#define BIT_GET_TA0_V1(x) (((x) >> BIT_SHIFT_TA0_V1) & BIT_MASK_TA0_V1) +#define BIT_SET_TA0_V1(x, v) (BIT_CLEAR_TA0_V1(x) | BIT_TA0_V1(v)) -#endif +/* 2 REG_TRANSMIT_ADDRSS_0_H (Offset 0x16A4) */ +#define BIT_SHIFT_TA0_H_V1 0 +#define BIT_MASK_TA0_H_V1 0xffff +#define BIT_TA0_H_V1(x) (((x) & BIT_MASK_TA0_H_V1) << BIT_SHIFT_TA0_H_V1) +#define BITS_TA0_H_V1 (BIT_MASK_TA0_H_V1 << BIT_SHIFT_TA0_H_V1) +#define BIT_CLEAR_TA0_H_V1(x) ((x) & (~BITS_TA0_H_V1)) +#define BIT_GET_TA0_H_V1(x) (((x) >> BIT_SHIFT_TA0_H_V1) & BIT_MASK_TA0_H_V1) +#define BIT_SET_TA0_H_V1(x, v) (BIT_CLEAR_TA0_H_V1(x) | BIT_TA0_H_V1(v)) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_WMAC_PLCP_MONITOR_MUTX (Offset 0x1698) */ +/* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */ -#define BIT_WMAC_MUTX_IDX BIT(24) +#define BIT_SHIFT_TA1 0 +#define BIT_MASK_TA1 0xffffffffffffL +#define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1) +#define BITS_TA1 (BIT_MASK_TA1 << BIT_SHIFT_TA1) +#define BIT_CLEAR_TA1(x) ((x) & (~BITS_TA1)) +#define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1) +#define BIT_SET_TA1(x, v) (BIT_CLEAR_TA1(x) | BIT_TA1(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */ -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define BIT_SHIFT_TA1_V1 0 +#define BIT_MASK_TA1_V1 0xffffffffL +#define BIT_TA1_V1(x) (((x) & BIT_MASK_TA1_V1) << BIT_SHIFT_TA1_V1) +#define BITS_TA1_V1 (BIT_MASK_TA1_V1 << BIT_SHIFT_TA1_V1) +#define BIT_CLEAR_TA1_V1(x) ((x) & (~BITS_TA1_V1)) +#define BIT_GET_TA1_V1(x) (((x) >> BIT_SHIFT_TA1_V1) & BIT_MASK_TA1_V1) +#define BIT_SET_TA1_V1(x, v) (BIT_CLEAR_TA1_V1(x) | BIT_TA1_V1(v)) +/* 2 REG_TRANSMIT_ADDRSS_1_H (Offset 0x16AC) */ -/* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */ +#define BIT_SHIFT_TA1_H_V1 0 +#define BIT_MASK_TA1_H_V1 0xffff +#define BIT_TA1_H_V1(x) (((x) & BIT_MASK_TA1_H_V1) << BIT_SHIFT_TA1_H_V1) +#define BITS_TA1_H_V1 (BIT_MASK_TA1_H_V1 << BIT_SHIFT_TA1_H_V1) +#define BIT_CLEAR_TA1_H_V1(x) ((x) & (~BITS_TA1_H_V1)) +#define BIT_GET_TA1_H_V1(x) (((x) >> BIT_SHIFT_TA1_H_V1) & BIT_MASK_TA1_H_V1) +#define BIT_SET_TA1_H_V1(x, v) (BIT_CLEAR_TA1_H_V1(x) | BIT_TA1_H_V1(v)) +#define BIT_SHIFT_TA2_V1 0 +#define BIT_MASK_TA2_V1 0xffffffffL +#define BIT_TA2_V1(x) (((x) & BIT_MASK_TA2_V1) << BIT_SHIFT_TA2_V1) +#define BITS_TA2_V1 (BIT_MASK_TA2_V1 << BIT_SHIFT_TA2_V1) +#define BIT_CLEAR_TA2_V1(x) ((x) & (~BITS_TA2_V1)) +#define BIT_GET_TA2_V1(x) (((x) >> BIT_SHIFT_TA2_V1) & BIT_MASK_TA2_V1) +#define BIT_SET_TA2_V1(x, v) (BIT_CLEAR_TA2_V1(x) | BIT_TA2_V1(v)) -#define BIT_SHIFT_TA0 0 -#define BIT_MASK_TA0 0xffffffffffffL -#define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0) -#define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -/* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */ +/* 2 REG_TRANSMIT_ADDRSS_2 (Offset 0x16B0) */ +#define BIT_SHIFT_TA2 0 +#define BIT_MASK_TA2 0xffffffffffffL +#define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2) +#define BITS_TA2 (BIT_MASK_TA2 << BIT_SHIFT_TA2) +#define BIT_CLEAR_TA2(x) ((x) & (~BITS_TA2)) +#define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2) +#define BIT_SET_TA2(x, v) (BIT_CLEAR_TA2(x) | BIT_TA2(v)) -#define BIT_SHIFT_TA1 0 -#define BIT_MASK_TA1 0xffffffffffffL -#define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1) -#define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_TRANSMIT_ADDRSS_2 (Offset 0x16B0) */ +/* 2 REG_TRANSMIT_ADDRSS_2_H (Offset 0x16B4) */ +#define BIT_SHIFT_TA2_H_V1 0 +#define BIT_MASK_TA2_H_V1 0xffff +#define BIT_TA2_H_V1(x) (((x) & BIT_MASK_TA2_H_V1) << BIT_SHIFT_TA2_H_V1) +#define BITS_TA2_H_V1 (BIT_MASK_TA2_H_V1 << BIT_SHIFT_TA2_H_V1) +#define BIT_CLEAR_TA2_H_V1(x) ((x) & (~BITS_TA2_H_V1)) +#define BIT_GET_TA2_H_V1(x) (((x) >> BIT_SHIFT_TA2_H_V1) & BIT_MASK_TA2_H_V1) +#define BIT_SET_TA2_H_V1(x, v) (BIT_CLEAR_TA2_H_V1(x) | BIT_TA2_H_V1(v)) -#define BIT_SHIFT_TA2 0 -#define BIT_MASK_TA2 0xffffffffffffL -#define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2) -#define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2) +#endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) /* 2 REG_TRANSMIT_ADDRSS_3 (Offset 0x16B8) */ +#define BIT_SHIFT_TA3 0 +#define BIT_MASK_TA3 0xffffffffffffL +#define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3) +#define BITS_TA3 (BIT_MASK_TA3 << BIT_SHIFT_TA3) +#define BIT_CLEAR_TA3(x) ((x) & (~BITS_TA3)) +#define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3) +#define BIT_SET_TA3(x, v) (BIT_CLEAR_TA3(x) | BIT_TA3(v)) -#define BIT_SHIFT_TA3 0 -#define BIT_MASK_TA3 0xffffffffffffL -#define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3) -#define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3) +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -/* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */ +/* 2 REG_TRANSMIT_ADDRSS_3_H (Offset 0x16BC) */ +#define BIT_SHIFT_TA3_H_V1 0 +#define BIT_MASK_TA3_H_V1 0xffff +#define BIT_TA3_H_V1(x) (((x) & BIT_MASK_TA3_H_V1) << BIT_SHIFT_TA3_H_V1) +#define BITS_TA3_H_V1 (BIT_MASK_TA3_H_V1 << BIT_SHIFT_TA3_H_V1) +#define BIT_CLEAR_TA3_H_V1(x) ((x) & (~BITS_TA3_H_V1)) +#define BIT_GET_TA3_H_V1(x) (((x) >> BIT_SHIFT_TA3_H_V1) & BIT_MASK_TA3_H_V1) +#define BIT_SET_TA3_H_V1(x, v) (BIT_CLEAR_TA3_H_V1(x) | BIT_TA3_H_V1(v)) -#define BIT_SHIFT_TA4 0 -#define BIT_MASK_TA4 0xffffffffffffL -#define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4) -#define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4) +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) + +/* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */ +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55) +#define BIT_R_WMAC_RXRST_DLY BIT(54) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53) +#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52) + +#define BIT_SHIFT_TA4 0 +#define BIT_MASK_TA4 0xffffffffffffL +#define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4) +#define BITS_TA4 (BIT_MASK_TA4 << BIT_SHIFT_TA4) +#define BIT_CLEAR_TA4(x) ((x) & (~BITS_TA4)) +#define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4) +#define BIT_SET_TA4(x, v) (BIT_CLEAR_TA4(x) | BIT_TA4(v)) #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +/* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */ +#define BIT_SHIFT_TA4_V1 0 +#define BIT_MASK_TA4_V1 0xffffffffL +#define BIT_TA4_V1(x) (((x) & BIT_MASK_TA4_V1) << BIT_SHIFT_TA4_V1) +#define BITS_TA4_V1 (BIT_MASK_TA4_V1 << BIT_SHIFT_TA4_V1) +#define BIT_CLEAR_TA4_V1(x) ((x) & (~BITS_TA4_V1)) +#define BIT_GET_TA4_V1(x) (((x) >> BIT_SHIFT_TA4_V1) & BIT_MASK_TA4_V1) +#define BIT_SET_TA4_V1(x, v) (BIT_CLEAR_TA4_V1(x) | BIT_TA4_V1(v)) -/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */ +/* 2 REG_TRANSMIT_ADDRSS_4_H (Offset 0x16C4) */ -#define BIT_LTECOEX_ACCESS_START_V1 BIT(31) -#define BIT_LTECOEX_WRITE_MODE_V1 BIT(30) -#define BIT_LTECOEX_READY_BIT_V1 BIT(29) +#define BIT_SHIFT_TA4_H_V1 0 +#define BIT_MASK_TA4_H_V1 0xffff +#define BIT_TA4_H_V1(x) (((x) & BIT_MASK_TA4_H_V1) << BIT_SHIFT_TA4_H_V1) +#define BITS_TA4_H_V1 (BIT_MASK_TA4_H_V1 << BIT_SHIFT_TA4_H_V1) +#define BIT_CLEAR_TA4_H_V1(x) ((x) & (~BITS_TA4_H_V1)) +#define BIT_GET_TA4_H_V1(x) (((x) >> BIT_SHIFT_TA4_H_V1) & BIT_MASK_TA4_H_V1) +#define BIT_SET_TA4_H_V1(x, v) (BIT_CLEAR_TA4_H_V1(x) | BIT_TA4_H_V1(v)) -#define BIT_SHIFT_WRITE_BYTE_EN_V1 16 -#define BIT_MASK_WRITE_BYTE_EN_V1 0xf -#define BIT_WRITE_BYTE_EN_V1(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1) -#define BIT_GET_WRITE_BYTE_EN_V1(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1) +#endif +#if (HALMAC_8812F_SUPPORT) -#define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0 -#define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff -#define BIT_LTECOEX_REG_ADDR_V1(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1) -#define BIT_GET_LTECOEX_REG_ADDR_V1(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1) +/* 2 REG_SND_AID12 (Offset 0x16D0) */ +#define BIT_SHIFT_USERID_SEL 12 +#define BIT_MASK_USERID_SEL 0x7 +#define BIT_USERID_SEL(x) (((x) & BIT_MASK_USERID_SEL) << BIT_SHIFT_USERID_SEL) +#define BITS_USERID_SEL (BIT_MASK_USERID_SEL << BIT_SHIFT_USERID_SEL) +#define BIT_CLEAR_USERID_SEL(x) ((x) & (~BITS_USERID_SEL)) +#define BIT_GET_USERID_SEL(x) \ + (((x) >> BIT_SHIFT_USERID_SEL) & BIT_MASK_USERID_SEL) +#define BIT_SET_USERID_SEL(x, v) (BIT_CLEAR_USERID_SEL(x) | BIT_USERID_SEL(v)) -/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */ +#define BIT_SHIFT_USERID_AID12 0 +#define BIT_MASK_USERID_AID12 0xfff +#define BIT_USERID_AID12(x) \ + (((x) & BIT_MASK_USERID_AID12) << BIT_SHIFT_USERID_AID12) +#define BITS_USERID_AID12 (BIT_MASK_USERID_AID12 << BIT_SHIFT_USERID_AID12) +#define BIT_CLEAR_USERID_AID12(x) ((x) & (~BITS_USERID_AID12)) +#define BIT_GET_USERID_AID12(x) \ + (((x) >> BIT_SHIFT_USERID_AID12) & BIT_MASK_USERID_AID12) +#define BIT_SET_USERID_AID12(x, v) \ + (BIT_CLEAR_USERID_AID12(x) | BIT_USERID_AID12(v)) +/* 2 REG_SND_PKT_INFO (Offset 0x16D2) */ -#define BIT_SHIFT_LTECOEX_W_DATA_V1 0 -#define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL -#define BIT_LTECOEX_W_DATA_V1(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1) -#define BIT_GET_LTECOEX_W_DATA_V1(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1) +#define BIT_SND_FROM_DS BIT(7) +#define BIT_SND_TO_DS BIT(6) +#define BIT_SHIFT_SND_TOKEN 0 +#define BIT_MASK_SND_TOKEN 0x3f +#define BIT_SND_TOKEN(x) (((x) & BIT_MASK_SND_TOKEN) << BIT_SHIFT_SND_TOKEN) +#define BITS_SND_TOKEN (BIT_MASK_SND_TOKEN << BIT_SHIFT_SND_TOKEN) +#define BIT_CLEAR_SND_TOKEN(x) ((x) & (~BITS_SND_TOKEN)) +#define BIT_GET_SND_TOKEN(x) (((x) >> BIT_SHIFT_SND_TOKEN) & BIT_MASK_SND_TOKEN) +#define BIT_SET_SND_TOKEN(x, v) (BIT_CLEAR_SND_TOKEN(x) | BIT_SND_TOKEN(v)) -/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */ +#endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define BIT_SHIFT_LTECOEX_R_DATA_V1 0 -#define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL -#define BIT_LTECOEX_R_DATA_V1(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1) -#define BIT_GET_LTECOEX_R_DATA_V1(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1) +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */ +#define BIT_LTECOEX_ACCESS_START_V1 BIT(31) +#define BIT_LTECOEX_WRITE_MODE_V1 BIT(30) +#define BIT_LTECOEX_READY_BIT_V1 BIT(29) + +#define BIT_SHIFT_WRITE_BYTE_EN_V1 16 +#define BIT_MASK_WRITE_BYTE_EN_V1 0xf +#define BIT_WRITE_BYTE_EN_V1(x) \ + (((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1) +#define BITS_WRITE_BYTE_EN_V1 \ + (BIT_MASK_WRITE_BYTE_EN_V1 << BIT_SHIFT_WRITE_BYTE_EN_V1) +#define BIT_CLEAR_WRITE_BYTE_EN_V1(x) ((x) & (~BITS_WRITE_BYTE_EN_V1)) +#define BIT_GET_WRITE_BYTE_EN_V1(x) \ + (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1) +#define BIT_SET_WRITE_BYTE_EN_V1(x, v) \ + (BIT_CLEAR_WRITE_BYTE_EN_V1(x) | BIT_WRITE_BYTE_EN_V1(v)) + +#define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0 +#define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff +#define BIT_LTECOEX_REG_ADDR_V1(x) \ + (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1) +#define BITS_LTECOEX_REG_ADDR_V1 \ + (BIT_MASK_LTECOEX_REG_ADDR_V1 << BIT_SHIFT_LTECOEX_REG_ADDR_V1) +#define BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) ((x) & (~BITS_LTECOEX_REG_ADDR_V1)) +#define BIT_GET_LTECOEX_REG_ADDR_V1(x) \ + (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1) +#define BIT_SET_LTECOEX_REG_ADDR_V1(x, v) \ + (BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) | BIT_LTECOEX_REG_ADDR_V1(v)) -#endif +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */ +#define BIT_SHIFT_LTECOEX_W_DATA_V1 0 +#define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL +#define BIT_LTECOEX_W_DATA_V1(x) \ + (((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1) +#define BITS_LTECOEX_W_DATA_V1 \ + (BIT_MASK_LTECOEX_W_DATA_V1 << BIT_SHIFT_LTECOEX_W_DATA_V1) +#define BIT_CLEAR_LTECOEX_W_DATA_V1(x) ((x) & (~BITS_LTECOEX_W_DATA_V1)) +#define BIT_GET_LTECOEX_W_DATA_V1(x) \ + (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1) +#define BIT_SET_LTECOEX_W_DATA_V1(x, v) \ + (BIT_CLEAR_LTECOEX_W_DATA_V1(x) | BIT_LTECOEX_W_DATA_V1(v)) +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */ -#endif/* __RTL_WLAN_BITDEF_H__ */ +#define BIT_SHIFT_LTECOEX_R_DATA_V1 0 +#define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL +#define BIT_LTECOEX_R_DATA_V1(x) \ + (((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1) +#define BITS_LTECOEX_R_DATA_V1 \ + (BIT_MASK_LTECOEX_R_DATA_V1 << BIT_SHIFT_LTECOEX_R_DATA_V1) +#define BIT_CLEAR_LTECOEX_R_DATA_V1(x) ((x) & (~BITS_LTECOEX_R_DATA_V1)) +#define BIT_GET_LTECOEX_R_DATA_V1(x) \ + (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1) +#define BIT_SET_LTECOEX_R_DATA_V1(x, v) \ + (BIT_CLEAR_LTECOEX_R_DATA_V1(x) | BIT_LTECOEX_R_DATA_V1(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_DMA_RQPN_INFO_0 (Offset 0x2200) */ + +#define BIT_SHIFT_CH0_AVAL_PG 16 +#define BIT_MASK_CH0_AVAL_PG 0xfff +#define BIT_CH0_AVAL_PG(x) \ + (((x) & BIT_MASK_CH0_AVAL_PG) << BIT_SHIFT_CH0_AVAL_PG) +#define BITS_CH0_AVAL_PG (BIT_MASK_CH0_AVAL_PG << BIT_SHIFT_CH0_AVAL_PG) +#define BIT_CLEAR_CH0_AVAL_PG(x) ((x) & (~BITS_CH0_AVAL_PG)) +#define BIT_GET_CH0_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH0_AVAL_PG) & BIT_MASK_CH0_AVAL_PG) +#define BIT_SET_CH0_AVAL_PG(x, v) \ + (BIT_CLEAR_CH0_AVAL_PG(x) | BIT_CH0_AVAL_PG(v)) + +#define BIT_SHIFT_CH0_RSVD_PG 0 +#define BIT_MASK_CH0_RSVD_PG 0xfff +#define BIT_CH0_RSVD_PG(x) \ + (((x) & BIT_MASK_CH0_RSVD_PG) << BIT_SHIFT_CH0_RSVD_PG) +#define BITS_CH0_RSVD_PG (BIT_MASK_CH0_RSVD_PG << BIT_SHIFT_CH0_RSVD_PG) +#define BIT_CLEAR_CH0_RSVD_PG(x) ((x) & (~BITS_CH0_RSVD_PG)) +#define BIT_GET_CH0_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH0_RSVD_PG) & BIT_MASK_CH0_RSVD_PG) +#define BIT_SET_CH0_RSVD_PG(x, v) \ + (BIT_CLEAR_CH0_RSVD_PG(x) | BIT_CH0_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_1 (Offset 0x2204) */ + +#define BIT_SHIFT_CH1_AVAL_PG 16 +#define BIT_MASK_CH1_AVAL_PG 0xfff +#define BIT_CH1_AVAL_PG(x) \ + (((x) & BIT_MASK_CH1_AVAL_PG) << BIT_SHIFT_CH1_AVAL_PG) +#define BITS_CH1_AVAL_PG (BIT_MASK_CH1_AVAL_PG << BIT_SHIFT_CH1_AVAL_PG) +#define BIT_CLEAR_CH1_AVAL_PG(x) ((x) & (~BITS_CH1_AVAL_PG)) +#define BIT_GET_CH1_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH1_AVAL_PG) & BIT_MASK_CH1_AVAL_PG) +#define BIT_SET_CH1_AVAL_PG(x, v) \ + (BIT_CLEAR_CH1_AVAL_PG(x) | BIT_CH1_AVAL_PG(v)) + +#define BIT_SHIFT_CH1_RSVD_PG 0 +#define BIT_MASK_CH1_RSVD_PG 0xfff +#define BIT_CH1_RSVD_PG(x) \ + (((x) & BIT_MASK_CH1_RSVD_PG) << BIT_SHIFT_CH1_RSVD_PG) +#define BITS_CH1_RSVD_PG (BIT_MASK_CH1_RSVD_PG << BIT_SHIFT_CH1_RSVD_PG) +#define BIT_CLEAR_CH1_RSVD_PG(x) ((x) & (~BITS_CH1_RSVD_PG)) +#define BIT_GET_CH1_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH1_RSVD_PG) & BIT_MASK_CH1_RSVD_PG) +#define BIT_SET_CH1_RSVD_PG(x, v) \ + (BIT_CLEAR_CH1_RSVD_PG(x) | BIT_CH1_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_2 (Offset 0x2208) */ + +#define BIT_SHIFT_CH2_AVAL_PG 16 +#define BIT_MASK_CH2_AVAL_PG 0xfff +#define BIT_CH2_AVAL_PG(x) \ + (((x) & BIT_MASK_CH2_AVAL_PG) << BIT_SHIFT_CH2_AVAL_PG) +#define BITS_CH2_AVAL_PG (BIT_MASK_CH2_AVAL_PG << BIT_SHIFT_CH2_AVAL_PG) +#define BIT_CLEAR_CH2_AVAL_PG(x) ((x) & (~BITS_CH2_AVAL_PG)) +#define BIT_GET_CH2_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH2_AVAL_PG) & BIT_MASK_CH2_AVAL_PG) +#define BIT_SET_CH2_AVAL_PG(x, v) \ + (BIT_CLEAR_CH2_AVAL_PG(x) | BIT_CH2_AVAL_PG(v)) + +#define BIT_SHIFT_CH2_RSVD_PG 0 +#define BIT_MASK_CH2_RSVD_PG 0xfff +#define BIT_CH2_RSVD_PG(x) \ + (((x) & BIT_MASK_CH2_RSVD_PG) << BIT_SHIFT_CH2_RSVD_PG) +#define BITS_CH2_RSVD_PG (BIT_MASK_CH2_RSVD_PG << BIT_SHIFT_CH2_RSVD_PG) +#define BIT_CLEAR_CH2_RSVD_PG(x) ((x) & (~BITS_CH2_RSVD_PG)) +#define BIT_GET_CH2_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH2_RSVD_PG) & BIT_MASK_CH2_RSVD_PG) +#define BIT_SET_CH2_RSVD_PG(x, v) \ + (BIT_CLEAR_CH2_RSVD_PG(x) | BIT_CH2_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_3 (Offset 0x220C) */ + +#define BIT_SHIFT_CH3_AVAL_PG 16 +#define BIT_MASK_CH3_AVAL_PG 0xfff +#define BIT_CH3_AVAL_PG(x) \ + (((x) & BIT_MASK_CH3_AVAL_PG) << BIT_SHIFT_CH3_AVAL_PG) +#define BITS_CH3_AVAL_PG (BIT_MASK_CH3_AVAL_PG << BIT_SHIFT_CH3_AVAL_PG) +#define BIT_CLEAR_CH3_AVAL_PG(x) ((x) & (~BITS_CH3_AVAL_PG)) +#define BIT_GET_CH3_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH3_AVAL_PG) & BIT_MASK_CH3_AVAL_PG) +#define BIT_SET_CH3_AVAL_PG(x, v) \ + (BIT_CLEAR_CH3_AVAL_PG(x) | BIT_CH3_AVAL_PG(v)) + +#define BIT_SHIFT_CH3_RSVD_PG 0 +#define BIT_MASK_CH3_RSVD_PG 0xfff +#define BIT_CH3_RSVD_PG(x) \ + (((x) & BIT_MASK_CH3_RSVD_PG) << BIT_SHIFT_CH3_RSVD_PG) +#define BITS_CH3_RSVD_PG (BIT_MASK_CH3_RSVD_PG << BIT_SHIFT_CH3_RSVD_PG) +#define BIT_CLEAR_CH3_RSVD_PG(x) ((x) & (~BITS_CH3_RSVD_PG)) +#define BIT_GET_CH3_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH3_RSVD_PG) & BIT_MASK_CH3_RSVD_PG) +#define BIT_SET_CH3_RSVD_PG(x, v) \ + (BIT_CLEAR_CH3_RSVD_PG(x) | BIT_CH3_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_4 (Offset 0x2210) */ + +#define BIT_SHIFT_CH4_AVAL_PG 16 +#define BIT_MASK_CH4_AVAL_PG 0xfff +#define BIT_CH4_AVAL_PG(x) \ + (((x) & BIT_MASK_CH4_AVAL_PG) << BIT_SHIFT_CH4_AVAL_PG) +#define BITS_CH4_AVAL_PG (BIT_MASK_CH4_AVAL_PG << BIT_SHIFT_CH4_AVAL_PG) +#define BIT_CLEAR_CH4_AVAL_PG(x) ((x) & (~BITS_CH4_AVAL_PG)) +#define BIT_GET_CH4_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH4_AVAL_PG) & BIT_MASK_CH4_AVAL_PG) +#define BIT_SET_CH4_AVAL_PG(x, v) \ + (BIT_CLEAR_CH4_AVAL_PG(x) | BIT_CH4_AVAL_PG(v)) + +#define BIT_SHIFT_CH4_RSVD_PG 0 +#define BIT_MASK_CH4_RSVD_PG 0xfff +#define BIT_CH4_RSVD_PG(x) \ + (((x) & BIT_MASK_CH4_RSVD_PG) << BIT_SHIFT_CH4_RSVD_PG) +#define BITS_CH4_RSVD_PG (BIT_MASK_CH4_RSVD_PG << BIT_SHIFT_CH4_RSVD_PG) +#define BIT_CLEAR_CH4_RSVD_PG(x) ((x) & (~BITS_CH4_RSVD_PG)) +#define BIT_GET_CH4_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH4_RSVD_PG) & BIT_MASK_CH4_RSVD_PG) +#define BIT_SET_CH4_RSVD_PG(x, v) \ + (BIT_CLEAR_CH4_RSVD_PG(x) | BIT_CH4_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_5 (Offset 0x2214) */ + +#define BIT_SHIFT_CH5_AVAL_PG 16 +#define BIT_MASK_CH5_AVAL_PG 0xfff +#define BIT_CH5_AVAL_PG(x) \ + (((x) & BIT_MASK_CH5_AVAL_PG) << BIT_SHIFT_CH5_AVAL_PG) +#define BITS_CH5_AVAL_PG (BIT_MASK_CH5_AVAL_PG << BIT_SHIFT_CH5_AVAL_PG) +#define BIT_CLEAR_CH5_AVAL_PG(x) ((x) & (~BITS_CH5_AVAL_PG)) +#define BIT_GET_CH5_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH5_AVAL_PG) & BIT_MASK_CH5_AVAL_PG) +#define BIT_SET_CH5_AVAL_PG(x, v) \ + (BIT_CLEAR_CH5_AVAL_PG(x) | BIT_CH5_AVAL_PG(v)) + +#define BIT_SHIFT_CH5_RSVD_PG 0 +#define BIT_MASK_CH5_RSVD_PG 0xfff +#define BIT_CH5_RSVD_PG(x) \ + (((x) & BIT_MASK_CH5_RSVD_PG) << BIT_SHIFT_CH5_RSVD_PG) +#define BITS_CH5_RSVD_PG (BIT_MASK_CH5_RSVD_PG << BIT_SHIFT_CH5_RSVD_PG) +#define BIT_CLEAR_CH5_RSVD_PG(x) ((x) & (~BITS_CH5_RSVD_PG)) +#define BIT_GET_CH5_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH5_RSVD_PG) & BIT_MASK_CH5_RSVD_PG) +#define BIT_SET_CH5_RSVD_PG(x, v) \ + (BIT_CLEAR_CH5_RSVD_PG(x) | BIT_CH5_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_6 (Offset 0x2218) */ + +#define BIT_SHIFT_CH6_AVAL_PG 16 +#define BIT_MASK_CH6_AVAL_PG 0xfff +#define BIT_CH6_AVAL_PG(x) \ + (((x) & BIT_MASK_CH6_AVAL_PG) << BIT_SHIFT_CH6_AVAL_PG) +#define BITS_CH6_AVAL_PG (BIT_MASK_CH6_AVAL_PG << BIT_SHIFT_CH6_AVAL_PG) +#define BIT_CLEAR_CH6_AVAL_PG(x) ((x) & (~BITS_CH6_AVAL_PG)) +#define BIT_GET_CH6_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH6_AVAL_PG) & BIT_MASK_CH6_AVAL_PG) +#define BIT_SET_CH6_AVAL_PG(x, v) \ + (BIT_CLEAR_CH6_AVAL_PG(x) | BIT_CH6_AVAL_PG(v)) + +#define BIT_SHIFT_CH6_RSVD_PG 0 +#define BIT_MASK_CH6_RSVD_PG 0xfff +#define BIT_CH6_RSVD_PG(x) \ + (((x) & BIT_MASK_CH6_RSVD_PG) << BIT_SHIFT_CH6_RSVD_PG) +#define BITS_CH6_RSVD_PG (BIT_MASK_CH6_RSVD_PG << BIT_SHIFT_CH6_RSVD_PG) +#define BIT_CLEAR_CH6_RSVD_PG(x) ((x) & (~BITS_CH6_RSVD_PG)) +#define BIT_GET_CH6_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH6_RSVD_PG) & BIT_MASK_CH6_RSVD_PG) +#define BIT_SET_CH6_RSVD_PG(x, v) \ + (BIT_CLEAR_CH6_RSVD_PG(x) | BIT_CH6_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_7 (Offset 0x221C) */ + +#define BIT_SHIFT_CH7_AVAL_PG 16 +#define BIT_MASK_CH7_AVAL_PG 0xfff +#define BIT_CH7_AVAL_PG(x) \ + (((x) & BIT_MASK_CH7_AVAL_PG) << BIT_SHIFT_CH7_AVAL_PG) +#define BITS_CH7_AVAL_PG (BIT_MASK_CH7_AVAL_PG << BIT_SHIFT_CH7_AVAL_PG) +#define BIT_CLEAR_CH7_AVAL_PG(x) ((x) & (~BITS_CH7_AVAL_PG)) +#define BIT_GET_CH7_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH7_AVAL_PG) & BIT_MASK_CH7_AVAL_PG) +#define BIT_SET_CH7_AVAL_PG(x, v) \ + (BIT_CLEAR_CH7_AVAL_PG(x) | BIT_CH7_AVAL_PG(v)) + +#define BIT_SHIFT_CH7_RSVD_PG 0 +#define BIT_MASK_CH7_RSVD_PG 0xfff +#define BIT_CH7_RSVD_PG(x) \ + (((x) & BIT_MASK_CH7_RSVD_PG) << BIT_SHIFT_CH7_RSVD_PG) +#define BITS_CH7_RSVD_PG (BIT_MASK_CH7_RSVD_PG << BIT_SHIFT_CH7_RSVD_PG) +#define BIT_CLEAR_CH7_RSVD_PG(x) ((x) & (~BITS_CH7_RSVD_PG)) +#define BIT_GET_CH7_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH7_RSVD_PG) & BIT_MASK_CH7_RSVD_PG) +#define BIT_SET_CH7_RSVD_PG(x, v) \ + (BIT_CLEAR_CH7_RSVD_PG(x) | BIT_CH7_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_8 (Offset 0x2220) */ + +#define BIT_SHIFT_CH8_AVAL_PG 16 +#define BIT_MASK_CH8_AVAL_PG 0xfff +#define BIT_CH8_AVAL_PG(x) \ + (((x) & BIT_MASK_CH8_AVAL_PG) << BIT_SHIFT_CH8_AVAL_PG) +#define BITS_CH8_AVAL_PG (BIT_MASK_CH8_AVAL_PG << BIT_SHIFT_CH8_AVAL_PG) +#define BIT_CLEAR_CH8_AVAL_PG(x) ((x) & (~BITS_CH8_AVAL_PG)) +#define BIT_GET_CH8_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH8_AVAL_PG) & BIT_MASK_CH8_AVAL_PG) +#define BIT_SET_CH8_AVAL_PG(x, v) \ + (BIT_CLEAR_CH8_AVAL_PG(x) | BIT_CH8_AVAL_PG(v)) + +#define BIT_SHIFT_CH8_RSVD_PG 0 +#define BIT_MASK_CH8_RSVD_PG 0xfff +#define BIT_CH8_RSVD_PG(x) \ + (((x) & BIT_MASK_CH8_RSVD_PG) << BIT_SHIFT_CH8_RSVD_PG) +#define BITS_CH8_RSVD_PG (BIT_MASK_CH8_RSVD_PG << BIT_SHIFT_CH8_RSVD_PG) +#define BIT_CLEAR_CH8_RSVD_PG(x) ((x) & (~BITS_CH8_RSVD_PG)) +#define BIT_GET_CH8_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH8_RSVD_PG) & BIT_MASK_CH8_RSVD_PG) +#define BIT_SET_CH8_RSVD_PG(x, v) \ + (BIT_CLEAR_CH8_RSVD_PG(x) | BIT_CH8_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_9 (Offset 0x2224) */ + +#define BIT_SHIFT_CH9_AVAL_PG 16 +#define BIT_MASK_CH9_AVAL_PG 0xfff +#define BIT_CH9_AVAL_PG(x) \ + (((x) & BIT_MASK_CH9_AVAL_PG) << BIT_SHIFT_CH9_AVAL_PG) +#define BITS_CH9_AVAL_PG (BIT_MASK_CH9_AVAL_PG << BIT_SHIFT_CH9_AVAL_PG) +#define BIT_CLEAR_CH9_AVAL_PG(x) ((x) & (~BITS_CH9_AVAL_PG)) +#define BIT_GET_CH9_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH9_AVAL_PG) & BIT_MASK_CH9_AVAL_PG) +#define BIT_SET_CH9_AVAL_PG(x, v) \ + (BIT_CLEAR_CH9_AVAL_PG(x) | BIT_CH9_AVAL_PG(v)) + +#define BIT_SHIFT_CH9_RSVD_PG 0 +#define BIT_MASK_CH9_RSVD_PG 0xfff +#define BIT_CH9_RSVD_PG(x) \ + (((x) & BIT_MASK_CH9_RSVD_PG) << BIT_SHIFT_CH9_RSVD_PG) +#define BITS_CH9_RSVD_PG (BIT_MASK_CH9_RSVD_PG << BIT_SHIFT_CH9_RSVD_PG) +#define BIT_CLEAR_CH9_RSVD_PG(x) ((x) & (~BITS_CH9_RSVD_PG)) +#define BIT_GET_CH9_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH9_RSVD_PG) & BIT_MASK_CH9_RSVD_PG) +#define BIT_SET_CH9_RSVD_PG(x, v) \ + (BIT_CLEAR_CH9_RSVD_PG(x) | BIT_CH9_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_10 (Offset 0x2228) */ + +#define BIT_SHIFT_CH10_AVAL_PG 16 +#define BIT_MASK_CH10_AVAL_PG 0xfff +#define BIT_CH10_AVAL_PG(x) \ + (((x) & BIT_MASK_CH10_AVAL_PG) << BIT_SHIFT_CH10_AVAL_PG) +#define BITS_CH10_AVAL_PG (BIT_MASK_CH10_AVAL_PG << BIT_SHIFT_CH10_AVAL_PG) +#define BIT_CLEAR_CH10_AVAL_PG(x) ((x) & (~BITS_CH10_AVAL_PG)) +#define BIT_GET_CH10_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH10_AVAL_PG) & BIT_MASK_CH10_AVAL_PG) +#define BIT_SET_CH10_AVAL_PG(x, v) \ + (BIT_CLEAR_CH10_AVAL_PG(x) | BIT_CH10_AVAL_PG(v)) + +#define BIT_SHIFT_CH10_RSVD_PG 0 +#define BIT_MASK_CH10_RSVD_PG 0xfff +#define BIT_CH10_RSVD_PG(x) \ + (((x) & BIT_MASK_CH10_RSVD_PG) << BIT_SHIFT_CH10_RSVD_PG) +#define BITS_CH10_RSVD_PG (BIT_MASK_CH10_RSVD_PG << BIT_SHIFT_CH10_RSVD_PG) +#define BIT_CLEAR_CH10_RSVD_PG(x) ((x) & (~BITS_CH10_RSVD_PG)) +#define BIT_GET_CH10_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH10_RSVD_PG) & BIT_MASK_CH10_RSVD_PG) +#define BIT_SET_CH10_RSVD_PG(x, v) \ + (BIT_CLEAR_CH10_RSVD_PG(x) | BIT_CH10_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_11 (Offset 0x222C) */ + +#define BIT_SHIFT_CH11_AVAL_PG 16 +#define BIT_MASK_CH11_AVAL_PG 0xfff +#define BIT_CH11_AVAL_PG(x) \ + (((x) & BIT_MASK_CH11_AVAL_PG) << BIT_SHIFT_CH11_AVAL_PG) +#define BITS_CH11_AVAL_PG (BIT_MASK_CH11_AVAL_PG << BIT_SHIFT_CH11_AVAL_PG) +#define BIT_CLEAR_CH11_AVAL_PG(x) ((x) & (~BITS_CH11_AVAL_PG)) +#define BIT_GET_CH11_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH11_AVAL_PG) & BIT_MASK_CH11_AVAL_PG) +#define BIT_SET_CH11_AVAL_PG(x, v) \ + (BIT_CLEAR_CH11_AVAL_PG(x) | BIT_CH11_AVAL_PG(v)) + +#define BIT_SHIFT_CH11_RSVD_PG 0 +#define BIT_MASK_CH11_RSVD_PG 0xfff +#define BIT_CH11_RSVD_PG(x) \ + (((x) & BIT_MASK_CH11_RSVD_PG) << BIT_SHIFT_CH11_RSVD_PG) +#define BITS_CH11_RSVD_PG (BIT_MASK_CH11_RSVD_PG << BIT_SHIFT_CH11_RSVD_PG) +#define BIT_CLEAR_CH11_RSVD_PG(x) ((x) & (~BITS_CH11_RSVD_PG)) +#define BIT_GET_CH11_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH11_RSVD_PG) & BIT_MASK_CH11_RSVD_PG) +#define BIT_SET_CH11_RSVD_PG(x, v) \ + (BIT_CLEAR_CH11_RSVD_PG(x) | BIT_CH11_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_12 (Offset 0x2230) */ + +#define BIT_SHIFT_CH12_AVAL_PG 16 +#define BIT_MASK_CH12_AVAL_PG 0xfff +#define BIT_CH12_AVAL_PG(x) \ + (((x) & BIT_MASK_CH12_AVAL_PG) << BIT_SHIFT_CH12_AVAL_PG) +#define BITS_CH12_AVAL_PG (BIT_MASK_CH12_AVAL_PG << BIT_SHIFT_CH12_AVAL_PG) +#define BIT_CLEAR_CH12_AVAL_PG(x) ((x) & (~BITS_CH12_AVAL_PG)) +#define BIT_GET_CH12_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH12_AVAL_PG) & BIT_MASK_CH12_AVAL_PG) +#define BIT_SET_CH12_AVAL_PG(x, v) \ + (BIT_CLEAR_CH12_AVAL_PG(x) | BIT_CH12_AVAL_PG(v)) + +#define BIT_SHIFT_CH12_RSVD_PG 0 +#define BIT_MASK_CH12_RSVD_PG 0xfff +#define BIT_CH12_RSVD_PG(x) \ + (((x) & BIT_MASK_CH12_RSVD_PG) << BIT_SHIFT_CH12_RSVD_PG) +#define BITS_CH12_RSVD_PG (BIT_MASK_CH12_RSVD_PG << BIT_SHIFT_CH12_RSVD_PG) +#define BIT_CLEAR_CH12_RSVD_PG(x) ((x) & (~BITS_CH12_RSVD_PG)) +#define BIT_GET_CH12_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH12_RSVD_PG) & BIT_MASK_CH12_RSVD_PG) +#define BIT_SET_CH12_RSVD_PG(x, v) \ + (BIT_CLEAR_CH12_RSVD_PG(x) | BIT_CH12_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_13 (Offset 0x2234) */ + +#define BIT_SHIFT_CH13_AVAL_PG 16 +#define BIT_MASK_CH13_AVAL_PG 0xfff +#define BIT_CH13_AVAL_PG(x) \ + (((x) & BIT_MASK_CH13_AVAL_PG) << BIT_SHIFT_CH13_AVAL_PG) +#define BITS_CH13_AVAL_PG (BIT_MASK_CH13_AVAL_PG << BIT_SHIFT_CH13_AVAL_PG) +#define BIT_CLEAR_CH13_AVAL_PG(x) ((x) & (~BITS_CH13_AVAL_PG)) +#define BIT_GET_CH13_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH13_AVAL_PG) & BIT_MASK_CH13_AVAL_PG) +#define BIT_SET_CH13_AVAL_PG(x, v) \ + (BIT_CLEAR_CH13_AVAL_PG(x) | BIT_CH13_AVAL_PG(v)) + +#define BIT_SHIFT_CH13_RSVD_PG 0 +#define BIT_MASK_CH13_RSVD_PG 0xfff +#define BIT_CH13_RSVD_PG(x) \ + (((x) & BIT_MASK_CH13_RSVD_PG) << BIT_SHIFT_CH13_RSVD_PG) +#define BITS_CH13_RSVD_PG (BIT_MASK_CH13_RSVD_PG << BIT_SHIFT_CH13_RSVD_PG) +#define BIT_CLEAR_CH13_RSVD_PG(x) ((x) & (~BITS_CH13_RSVD_PG)) +#define BIT_GET_CH13_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH13_RSVD_PG) & BIT_MASK_CH13_RSVD_PG) +#define BIT_SET_CH13_RSVD_PG(x, v) \ + (BIT_CLEAR_CH13_RSVD_PG(x) | BIT_CH13_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_14 (Offset 0x2238) */ + +#define BIT_SHIFT_CH14_AVAL_PG 16 +#define BIT_MASK_CH14_AVAL_PG 0xfff +#define BIT_CH14_AVAL_PG(x) \ + (((x) & BIT_MASK_CH14_AVAL_PG) << BIT_SHIFT_CH14_AVAL_PG) +#define BITS_CH14_AVAL_PG (BIT_MASK_CH14_AVAL_PG << BIT_SHIFT_CH14_AVAL_PG) +#define BIT_CLEAR_CH14_AVAL_PG(x) ((x) & (~BITS_CH14_AVAL_PG)) +#define BIT_GET_CH14_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH14_AVAL_PG) & BIT_MASK_CH14_AVAL_PG) +#define BIT_SET_CH14_AVAL_PG(x, v) \ + (BIT_CLEAR_CH14_AVAL_PG(x) | BIT_CH14_AVAL_PG(v)) + +#define BIT_SHIFT_CH14_RSVD_PG 0 +#define BIT_MASK_CH14_RSVD_PG 0xfff +#define BIT_CH14_RSVD_PG(x) \ + (((x) & BIT_MASK_CH14_RSVD_PG) << BIT_SHIFT_CH14_RSVD_PG) +#define BITS_CH14_RSVD_PG (BIT_MASK_CH14_RSVD_PG << BIT_SHIFT_CH14_RSVD_PG) +#define BIT_CLEAR_CH14_RSVD_PG(x) ((x) & (~BITS_CH14_RSVD_PG)) +#define BIT_GET_CH14_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH14_RSVD_PG) & BIT_MASK_CH14_RSVD_PG) +#define BIT_SET_CH14_RSVD_PG(x, v) \ + (BIT_CLEAR_CH14_RSVD_PG(x) | BIT_CH14_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_15 (Offset 0x223C) */ + +#define BIT_SHIFT_CH15_AVAL_PG 16 +#define BIT_MASK_CH15_AVAL_PG 0xfff +#define BIT_CH15_AVAL_PG(x) \ + (((x) & BIT_MASK_CH15_AVAL_PG) << BIT_SHIFT_CH15_AVAL_PG) +#define BITS_CH15_AVAL_PG (BIT_MASK_CH15_AVAL_PG << BIT_SHIFT_CH15_AVAL_PG) +#define BIT_CLEAR_CH15_AVAL_PG(x) ((x) & (~BITS_CH15_AVAL_PG)) +#define BIT_GET_CH15_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH15_AVAL_PG) & BIT_MASK_CH15_AVAL_PG) +#define BIT_SET_CH15_AVAL_PG(x, v) \ + (BIT_CLEAR_CH15_AVAL_PG(x) | BIT_CH15_AVAL_PG(v)) + +#define BIT_SHIFT_CH15_RSVD_PG 0 +#define BIT_MASK_CH15_RSVD_PG 0xfff +#define BIT_CH15_RSVD_PG(x) \ + (((x) & BIT_MASK_CH15_RSVD_PG) << BIT_SHIFT_CH15_RSVD_PG) +#define BITS_CH15_RSVD_PG (BIT_MASK_CH15_RSVD_PG << BIT_SHIFT_CH15_RSVD_PG) +#define BIT_CLEAR_CH15_RSVD_PG(x) ((x) & (~BITS_CH15_RSVD_PG)) +#define BIT_GET_CH15_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH15_RSVD_PG) & BIT_MASK_CH15_RSVD_PG) +#define BIT_SET_CH15_RSVD_PG(x, v) \ + (BIT_CLEAR_CH15_RSVD_PG(x) | BIT_CH15_RSVD_PG(v)) + +/* 2 REG_DMA_RQPN_INFO_16 (Offset 0x2240) */ + +#define BIT_SHIFT_CH16_AVAL_PG 16 +#define BIT_MASK_CH16_AVAL_PG 0xfff +#define BIT_CH16_AVAL_PG(x) \ + (((x) & BIT_MASK_CH16_AVAL_PG) << BIT_SHIFT_CH16_AVAL_PG) +#define BITS_CH16_AVAL_PG (BIT_MASK_CH16_AVAL_PG << BIT_SHIFT_CH16_AVAL_PG) +#define BIT_CLEAR_CH16_AVAL_PG(x) ((x) & (~BITS_CH16_AVAL_PG)) +#define BIT_GET_CH16_AVAL_PG(x) \ + (((x) >> BIT_SHIFT_CH16_AVAL_PG) & BIT_MASK_CH16_AVAL_PG) +#define BIT_SET_CH16_AVAL_PG(x, v) \ + (BIT_CLEAR_CH16_AVAL_PG(x) | BIT_CH16_AVAL_PG(v)) + +#define BIT_SHIFT_CH16_RSVD_PG 0 +#define BIT_MASK_CH16_RSVD_PG 0xfff +#define BIT_CH16_RSVD_PG(x) \ + (((x) & BIT_MASK_CH16_RSVD_PG) << BIT_SHIFT_CH16_RSVD_PG) +#define BITS_CH16_RSVD_PG (BIT_MASK_CH16_RSVD_PG << BIT_SHIFT_CH16_RSVD_PG) +#define BIT_CLEAR_CH16_RSVD_PG(x) ((x) & (~BITS_CH16_RSVD_PG)) +#define BIT_GET_CH16_RSVD_PG(x) \ + (((x) >> BIT_SHIFT_CH16_RSVD_PG) & BIT_MASK_CH16_RSVD_PG) +#define BIT_SET_CH16_RSVD_PG(x, v) \ + (BIT_CLEAR_CH16_RSVD_PG(x) | BIT_CH16_RSVD_PG(v)) + +/* 2 REG_HWAMSDU_CTL1 (Offset 0x2250) */ + +#define BIT_SHIFT_HWAMSDU_PKTNUM 8 +#define BIT_MASK_HWAMSDU_PKTNUM 0x3f +#define BIT_HWAMSDU_PKTNUM(x) \ + (((x) & BIT_MASK_HWAMSDU_PKTNUM) << BIT_SHIFT_HWAMSDU_PKTNUM) +#define BITS_HWAMSDU_PKTNUM \ + (BIT_MASK_HWAMSDU_PKTNUM << BIT_SHIFT_HWAMSDU_PKTNUM) +#define BIT_CLEAR_HWAMSDU_PKTNUM(x) ((x) & (~BITS_HWAMSDU_PKTNUM)) +#define BIT_GET_HWAMSDU_PKTNUM(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_PKTNUM) & BIT_MASK_HWAMSDU_PKTNUM) +#define BIT_SET_HWAMSDU_PKTNUM(x, v) \ + (BIT_CLEAR_HWAMSDU_PKTNUM(x) | BIT_HWAMSDU_PKTNUM(v)) + +#define BIT_HWAMSDU_BUSY BIT(7) +#define BIT_SINGLE_AMSDU BIT(2) +#define BIT_HWAMSDU_PADDING_MODE BIT(1) +#define BIT_HWAMSDU_EN BIT(0) + +/* 2 REG_HWAMSDU_CTL2 (Offset 0x2254) */ + +#define BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT 16 +#define BIT_MASK_HWAMSDU_AMSDU_TIMEOUT 0xffff +#define BIT_HWAMSDU_AMSDU_TIMEOUT(x) \ + (((x) & BIT_MASK_HWAMSDU_AMSDU_TIMEOUT) \ + << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) +#define BITS_HWAMSDU_AMSDU_TIMEOUT \ + (BIT_MASK_HWAMSDU_AMSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) +#define BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_AMSDU_TIMEOUT)) +#define BIT_GET_HWAMSDU_AMSDU_TIMEOUT(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) & \ + BIT_MASK_HWAMSDU_AMSDU_TIMEOUT) +#define BIT_SET_HWAMSDU_AMSDU_TIMEOUT(x, v) \ + (BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) | BIT_HWAMSDU_AMSDU_TIMEOUT(v)) + +#define BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT 0 +#define BIT_MASK_HWAMSDU_MSDU_TIMEOUT 0xffff +#define BIT_HWAMSDU_MSDU_TIMEOUT(x) \ + (((x) & BIT_MASK_HWAMSDU_MSDU_TIMEOUT) \ + << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) +#define BITS_HWAMSDU_MSDU_TIMEOUT \ + (BIT_MASK_HWAMSDU_MSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) +#define BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_MSDU_TIMEOUT)) +#define BIT_GET_HWAMSDU_MSDU_TIMEOUT(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) & \ + BIT_MASK_HWAMSDU_MSDU_TIMEOUT) +#define BIT_SET_HWAMSDU_MSDU_TIMEOUT(x, v) \ + (BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) | BIT_HWAMSDU_MSDU_TIMEOUT(v)) + +/* 2 REG_HI8Q_TXBD_DESA_L (Offset 0x2300) */ + +#define BIT_SHIFT_HI8Q_TXBD_DESA_L 0 +#define BIT_MASK_HI8Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI8Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI8Q_TXBD_DESA_L) << BIT_SHIFT_HI8Q_TXBD_DESA_L) +#define BITS_HI8Q_TXBD_DESA_L \ + (BIT_MASK_HI8Q_TXBD_DESA_L << BIT_SHIFT_HI8Q_TXBD_DESA_L) +#define BIT_CLEAR_HI8Q_TXBD_DESA_L(x) ((x) & (~BITS_HI8Q_TXBD_DESA_L)) +#define BIT_GET_HI8Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_L) & BIT_MASK_HI8Q_TXBD_DESA_L) +#define BIT_SET_HI8Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI8Q_TXBD_DESA_L(x) | BIT_HI8Q_TXBD_DESA_L(v)) + +/* 2 REG_HI8Q_TXBD_DESA_H (Offset 0x2304) */ + +#define BIT_SHIFT_HI8Q_TXBD_DESA_H 0 +#define BIT_MASK_HI8Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI8Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI8Q_TXBD_DESA_H) << BIT_SHIFT_HI8Q_TXBD_DESA_H) +#define BITS_HI8Q_TXBD_DESA_H \ + (BIT_MASK_HI8Q_TXBD_DESA_H << BIT_SHIFT_HI8Q_TXBD_DESA_H) +#define BIT_CLEAR_HI8Q_TXBD_DESA_H(x) ((x) & (~BITS_HI8Q_TXBD_DESA_H)) +#define BIT_GET_HI8Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_H) & BIT_MASK_HI8Q_TXBD_DESA_H) +#define BIT_SET_HI8Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI8Q_TXBD_DESA_H(x) | BIT_HI8Q_TXBD_DESA_H(v)) + +/* 2 REG_HI9Q_TXBD_DESA_L (Offset 0x2308) */ + +#define BIT_SHIFT_HI9Q_TXBD_DESA_L 0 +#define BIT_MASK_HI9Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI9Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI9Q_TXBD_DESA_L) << BIT_SHIFT_HI9Q_TXBD_DESA_L) +#define BITS_HI9Q_TXBD_DESA_L \ + (BIT_MASK_HI9Q_TXBD_DESA_L << BIT_SHIFT_HI9Q_TXBD_DESA_L) +#define BIT_CLEAR_HI9Q_TXBD_DESA_L(x) ((x) & (~BITS_HI9Q_TXBD_DESA_L)) +#define BIT_GET_HI9Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_L) & BIT_MASK_HI9Q_TXBD_DESA_L) +#define BIT_SET_HI9Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI9Q_TXBD_DESA_L(x) | BIT_HI9Q_TXBD_DESA_L(v)) + +/* 2 REG_HI9Q_TXBD_DESA_H (Offset 0x230C) */ + +#define BIT_SHIFT_HI9Q_TXBD_DESA_H 0 +#define BIT_MASK_HI9Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI9Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI9Q_TXBD_DESA_H) << BIT_SHIFT_HI9Q_TXBD_DESA_H) +#define BITS_HI9Q_TXBD_DESA_H \ + (BIT_MASK_HI9Q_TXBD_DESA_H << BIT_SHIFT_HI9Q_TXBD_DESA_H) +#define BIT_CLEAR_HI9Q_TXBD_DESA_H(x) ((x) & (~BITS_HI9Q_TXBD_DESA_H)) +#define BIT_GET_HI9Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_H) & BIT_MASK_HI9Q_TXBD_DESA_H) +#define BIT_SET_HI9Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI9Q_TXBD_DESA_H(x) | BIT_HI9Q_TXBD_DESA_H(v)) + +/* 2 REG_HI10Q_TXBD_DESA_L (Offset 0x2310) */ + +#define BIT_SHIFT_HI10Q_TXBD_DESA_L 0 +#define BIT_MASK_HI10Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI10Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI10Q_TXBD_DESA_L) << BIT_SHIFT_HI10Q_TXBD_DESA_L) +#define BITS_HI10Q_TXBD_DESA_L \ + (BIT_MASK_HI10Q_TXBD_DESA_L << BIT_SHIFT_HI10Q_TXBD_DESA_L) +#define BIT_CLEAR_HI10Q_TXBD_DESA_L(x) ((x) & (~BITS_HI10Q_TXBD_DESA_L)) +#define BIT_GET_HI10Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_L) & BIT_MASK_HI10Q_TXBD_DESA_L) +#define BIT_SET_HI10Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI10Q_TXBD_DESA_L(x) | BIT_HI10Q_TXBD_DESA_L(v)) + +/* 2 REG_HI10Q_TXBD_DESA_H (Offset 0x2314) */ + +#define BIT_SHIFT_HI10Q_TXBD_DESA_H 0 +#define BIT_MASK_HI10Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI10Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI10Q_TXBD_DESA_H) << BIT_SHIFT_HI10Q_TXBD_DESA_H) +#define BITS_HI10Q_TXBD_DESA_H \ + (BIT_MASK_HI10Q_TXBD_DESA_H << BIT_SHIFT_HI10Q_TXBD_DESA_H) +#define BIT_CLEAR_HI10Q_TXBD_DESA_H(x) ((x) & (~BITS_HI10Q_TXBD_DESA_H)) +#define BIT_GET_HI10Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_H) & BIT_MASK_HI10Q_TXBD_DESA_H) +#define BIT_SET_HI10Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI10Q_TXBD_DESA_H(x) | BIT_HI10Q_TXBD_DESA_H(v)) + +/* 2 REG_HI11Q_TXBD_DESA_L (Offset 0x2318) */ + +#define BIT_SHIFT_HI11Q_TXBD_DESA_L 0 +#define BIT_MASK_HI11Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI11Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI11Q_TXBD_DESA_L) << BIT_SHIFT_HI11Q_TXBD_DESA_L) +#define BITS_HI11Q_TXBD_DESA_L \ + (BIT_MASK_HI11Q_TXBD_DESA_L << BIT_SHIFT_HI11Q_TXBD_DESA_L) +#define BIT_CLEAR_HI11Q_TXBD_DESA_L(x) ((x) & (~BITS_HI11Q_TXBD_DESA_L)) +#define BIT_GET_HI11Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_L) & BIT_MASK_HI11Q_TXBD_DESA_L) +#define BIT_SET_HI11Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI11Q_TXBD_DESA_L(x) | BIT_HI11Q_TXBD_DESA_L(v)) + +/* 2 REG_HI11Q_TXBD_DESA_H (Offset 0x231C) */ + +#define BIT_SHIFT_HI11Q_TXBD_DESA_H 0 +#define BIT_MASK_HI11Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI11Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI11Q_TXBD_DESA_H) << BIT_SHIFT_HI11Q_TXBD_DESA_H) +#define BITS_HI11Q_TXBD_DESA_H \ + (BIT_MASK_HI11Q_TXBD_DESA_H << BIT_SHIFT_HI11Q_TXBD_DESA_H) +#define BIT_CLEAR_HI11Q_TXBD_DESA_H(x) ((x) & (~BITS_HI11Q_TXBD_DESA_H)) +#define BIT_GET_HI11Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_H) & BIT_MASK_HI11Q_TXBD_DESA_H) +#define BIT_SET_HI11Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI11Q_TXBD_DESA_H(x) | BIT_HI11Q_TXBD_DESA_H(v)) + +/* 2 REG_HI12Q_TXBD_DESA_L (Offset 0x2320) */ + +#define BIT_SHIFT_HI12Q_TXBD_DESA_L 0 +#define BIT_MASK_HI12Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI12Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI12Q_TXBD_DESA_L) << BIT_SHIFT_HI12Q_TXBD_DESA_L) +#define BITS_HI12Q_TXBD_DESA_L \ + (BIT_MASK_HI12Q_TXBD_DESA_L << BIT_SHIFT_HI12Q_TXBD_DESA_L) +#define BIT_CLEAR_HI12Q_TXBD_DESA_L(x) ((x) & (~BITS_HI12Q_TXBD_DESA_L)) +#define BIT_GET_HI12Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_L) & BIT_MASK_HI12Q_TXBD_DESA_L) +#define BIT_SET_HI12Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI12Q_TXBD_DESA_L(x) | BIT_HI12Q_TXBD_DESA_L(v)) + +/* 2 REG_HI12Q_TXBD_DESA_H (Offset 0x2324) */ + +#define BIT_SHIFT_HI12Q_TXBD_DESA_H 0 +#define BIT_MASK_HI12Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI12Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI12Q_TXBD_DESA_H) << BIT_SHIFT_HI12Q_TXBD_DESA_H) +#define BITS_HI12Q_TXBD_DESA_H \ + (BIT_MASK_HI12Q_TXBD_DESA_H << BIT_SHIFT_HI12Q_TXBD_DESA_H) +#define BIT_CLEAR_HI12Q_TXBD_DESA_H(x) ((x) & (~BITS_HI12Q_TXBD_DESA_H)) +#define BIT_GET_HI12Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_H) & BIT_MASK_HI12Q_TXBD_DESA_H) +#define BIT_SET_HI12Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI12Q_TXBD_DESA_H(x) | BIT_HI12Q_TXBD_DESA_H(v)) + +/* 2 REG_HI13Q_TXBD_DESA_L (Offset 0x2328) */ + +#define BIT_SHIFT_HI13Q_TXBD_DESA_L 0 +#define BIT_MASK_HI13Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI13Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI13Q_TXBD_DESA_L) << BIT_SHIFT_HI13Q_TXBD_DESA_L) +#define BITS_HI13Q_TXBD_DESA_L \ + (BIT_MASK_HI13Q_TXBD_DESA_L << BIT_SHIFT_HI13Q_TXBD_DESA_L) +#define BIT_CLEAR_HI13Q_TXBD_DESA_L(x) ((x) & (~BITS_HI13Q_TXBD_DESA_L)) +#define BIT_GET_HI13Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_L) & BIT_MASK_HI13Q_TXBD_DESA_L) +#define BIT_SET_HI13Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI13Q_TXBD_DESA_L(x) | BIT_HI13Q_TXBD_DESA_L(v)) + +/* 2 REG_HI13Q_TXBD_DESA_H (Offset 0x232C) */ + +#define BIT_SHIFT_HI13Q_TXBD_DESA_H 0 +#define BIT_MASK_HI13Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI13Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI13Q_TXBD_DESA_H) << BIT_SHIFT_HI13Q_TXBD_DESA_H) +#define BITS_HI13Q_TXBD_DESA_H \ + (BIT_MASK_HI13Q_TXBD_DESA_H << BIT_SHIFT_HI13Q_TXBD_DESA_H) +#define BIT_CLEAR_HI13Q_TXBD_DESA_H(x) ((x) & (~BITS_HI13Q_TXBD_DESA_H)) +#define BIT_GET_HI13Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_H) & BIT_MASK_HI13Q_TXBD_DESA_H) +#define BIT_SET_HI13Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI13Q_TXBD_DESA_H(x) | BIT_HI13Q_TXBD_DESA_H(v)) + +/* 2 REG_HI14Q_TXBD_DESA_L (Offset 0x2330) */ + +#define BIT_SHIFT_HI14Q_TXBD_DESA_L 0 +#define BIT_MASK_HI14Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI14Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI14Q_TXBD_DESA_L) << BIT_SHIFT_HI14Q_TXBD_DESA_L) +#define BITS_HI14Q_TXBD_DESA_L \ + (BIT_MASK_HI14Q_TXBD_DESA_L << BIT_SHIFT_HI14Q_TXBD_DESA_L) +#define BIT_CLEAR_HI14Q_TXBD_DESA_L(x) ((x) & (~BITS_HI14Q_TXBD_DESA_L)) +#define BIT_GET_HI14Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_L) & BIT_MASK_HI14Q_TXBD_DESA_L) +#define BIT_SET_HI14Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI14Q_TXBD_DESA_L(x) | BIT_HI14Q_TXBD_DESA_L(v)) + +/* 2 REG_HI14Q_TXBD_DESA_H (Offset 0x2334) */ + +#define BIT_SHIFT_HI14Q_TXBD_DESA_H 0 +#define BIT_MASK_HI14Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI14Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI14Q_TXBD_DESA_H) << BIT_SHIFT_HI14Q_TXBD_DESA_H) +#define BITS_HI14Q_TXBD_DESA_H \ + (BIT_MASK_HI14Q_TXBD_DESA_H << BIT_SHIFT_HI14Q_TXBD_DESA_H) +#define BIT_CLEAR_HI14Q_TXBD_DESA_H(x) ((x) & (~BITS_HI14Q_TXBD_DESA_H)) +#define BIT_GET_HI14Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_H) & BIT_MASK_HI14Q_TXBD_DESA_H) +#define BIT_SET_HI14Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI14Q_TXBD_DESA_H(x) | BIT_HI14Q_TXBD_DESA_H(v)) + +/* 2 REG_HI15Q_TXBD_DESA_L (Offset 0x2338) */ + +#define BIT_SHIFT_HI15Q_TXBD_DESA_L 0 +#define BIT_MASK_HI15Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI15Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI15Q_TXBD_DESA_L) << BIT_SHIFT_HI15Q_TXBD_DESA_L) +#define BITS_HI15Q_TXBD_DESA_L \ + (BIT_MASK_HI15Q_TXBD_DESA_L << BIT_SHIFT_HI15Q_TXBD_DESA_L) +#define BIT_CLEAR_HI15Q_TXBD_DESA_L(x) ((x) & (~BITS_HI15Q_TXBD_DESA_L)) +#define BIT_GET_HI15Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_L) & BIT_MASK_HI15Q_TXBD_DESA_L) +#define BIT_SET_HI15Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI15Q_TXBD_DESA_L(x) | BIT_HI15Q_TXBD_DESA_L(v)) + +/* 2 REG_HI15Q_TXBD_DESA_H (Offset 0x233C) */ + +#define BIT_SHIFT_HI15Q_TXBD_DESA_H 0 +#define BIT_MASK_HI15Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI15Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI15Q_TXBD_DESA_H) << BIT_SHIFT_HI15Q_TXBD_DESA_H) +#define BITS_HI15Q_TXBD_DESA_H \ + (BIT_MASK_HI15Q_TXBD_DESA_H << BIT_SHIFT_HI15Q_TXBD_DESA_H) +#define BIT_CLEAR_HI15Q_TXBD_DESA_H(x) ((x) & (~BITS_HI15Q_TXBD_DESA_H)) +#define BIT_GET_HI15Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_H) & BIT_MASK_HI15Q_TXBD_DESA_H) +#define BIT_SET_HI15Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI15Q_TXBD_DESA_H(x) | BIT_HI15Q_TXBD_DESA_H(v)) + +/* 2 REG_HI16Q_TXBD_DESA_L (Offset 0x2340) */ + +#define BIT_SHIFT_HI16Q_TXBD_DESA_L 0 +#define BIT_MASK_HI16Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI16Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI16Q_TXBD_DESA_L) << BIT_SHIFT_HI16Q_TXBD_DESA_L) +#define BITS_HI16Q_TXBD_DESA_L \ + (BIT_MASK_HI16Q_TXBD_DESA_L << BIT_SHIFT_HI16Q_TXBD_DESA_L) +#define BIT_CLEAR_HI16Q_TXBD_DESA_L(x) ((x) & (~BITS_HI16Q_TXBD_DESA_L)) +#define BIT_GET_HI16Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_L) & BIT_MASK_HI16Q_TXBD_DESA_L) +#define BIT_SET_HI16Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI16Q_TXBD_DESA_L(x) | BIT_HI16Q_TXBD_DESA_L(v)) + +/* 2 REG_HI16Q_TXBD_DESA_H (Offset 0x2344) */ + +#define BIT_SHIFT_HI16Q_TXBD_DESA_H 0 +#define BIT_MASK_HI16Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI16Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI16Q_TXBD_DESA_H) << BIT_SHIFT_HI16Q_TXBD_DESA_H) +#define BITS_HI16Q_TXBD_DESA_H \ + (BIT_MASK_HI16Q_TXBD_DESA_H << BIT_SHIFT_HI16Q_TXBD_DESA_H) +#define BIT_CLEAR_HI16Q_TXBD_DESA_H(x) ((x) & (~BITS_HI16Q_TXBD_DESA_H)) +#define BIT_GET_HI16Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_H) & BIT_MASK_HI16Q_TXBD_DESA_H) +#define BIT_SET_HI16Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI16Q_TXBD_DESA_H(x) | BIT_HI16Q_TXBD_DESA_H(v)) + +/* 2 REG_HI17Q_TXBD_DESA_L (Offset 0x2348) */ + +#define BIT_SHIFT_HI17Q_TXBD_DESA_L 0 +#define BIT_MASK_HI17Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI17Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI17Q_TXBD_DESA_L) << BIT_SHIFT_HI17Q_TXBD_DESA_L) +#define BITS_HI17Q_TXBD_DESA_L \ + (BIT_MASK_HI17Q_TXBD_DESA_L << BIT_SHIFT_HI17Q_TXBD_DESA_L) +#define BIT_CLEAR_HI17Q_TXBD_DESA_L(x) ((x) & (~BITS_HI17Q_TXBD_DESA_L)) +#define BIT_GET_HI17Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_L) & BIT_MASK_HI17Q_TXBD_DESA_L) +#define BIT_SET_HI17Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI17Q_TXBD_DESA_L(x) | BIT_HI17Q_TXBD_DESA_L(v)) + +/* 2 REG_HI17Q_TXBD_DESA_H (Offset 0x234C) */ + +#define BIT_SHIFT_HI17Q_TXBD_DESA_H 0 +#define BIT_MASK_HI17Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI17Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI17Q_TXBD_DESA_H) << BIT_SHIFT_HI17Q_TXBD_DESA_H) +#define BITS_HI17Q_TXBD_DESA_H \ + (BIT_MASK_HI17Q_TXBD_DESA_H << BIT_SHIFT_HI17Q_TXBD_DESA_H) +#define BIT_CLEAR_HI17Q_TXBD_DESA_H(x) ((x) & (~BITS_HI17Q_TXBD_DESA_H)) +#define BIT_GET_HI17Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_H) & BIT_MASK_HI17Q_TXBD_DESA_H) +#define BIT_SET_HI17Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI17Q_TXBD_DESA_H(x) | BIT_HI17Q_TXBD_DESA_H(v)) + +/* 2 REG_HI18Q_TXBD_DESA_L (Offset 0x2350) */ + +#define BIT_SHIFT_HI18Q_TXBD_DESA_L 0 +#define BIT_MASK_HI18Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI18Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI18Q_TXBD_DESA_L) << BIT_SHIFT_HI18Q_TXBD_DESA_L) +#define BITS_HI18Q_TXBD_DESA_L \ + (BIT_MASK_HI18Q_TXBD_DESA_L << BIT_SHIFT_HI18Q_TXBD_DESA_L) +#define BIT_CLEAR_HI18Q_TXBD_DESA_L(x) ((x) & (~BITS_HI18Q_TXBD_DESA_L)) +#define BIT_GET_HI18Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_L) & BIT_MASK_HI18Q_TXBD_DESA_L) +#define BIT_SET_HI18Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI18Q_TXBD_DESA_L(x) | BIT_HI18Q_TXBD_DESA_L(v)) + +/* 2 REG_HI18Q_TXBD_DESA_H (Offset 0x2354) */ + +#define BIT_SHIFT_HI18Q_TXBD_DESA_H 0 +#define BIT_MASK_HI18Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI18Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI18Q_TXBD_DESA_H) << BIT_SHIFT_HI18Q_TXBD_DESA_H) +#define BITS_HI18Q_TXBD_DESA_H \ + (BIT_MASK_HI18Q_TXBD_DESA_H << BIT_SHIFT_HI18Q_TXBD_DESA_H) +#define BIT_CLEAR_HI18Q_TXBD_DESA_H(x) ((x) & (~BITS_HI18Q_TXBD_DESA_H)) +#define BIT_GET_HI18Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_H) & BIT_MASK_HI18Q_TXBD_DESA_H) +#define BIT_SET_HI18Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI18Q_TXBD_DESA_H(x) | BIT_HI18Q_TXBD_DESA_H(v)) + +/* 2 REG_HI19Q_TXBD_DESA_L (Offset 0x2358) */ + +#define BIT_SHIFT_HI19Q_TXBD_DESA_L 0 +#define BIT_MASK_HI19Q_TXBD_DESA_L 0xffffffffL +#define BIT_HI19Q_TXBD_DESA_L(x) \ + (((x) & BIT_MASK_HI19Q_TXBD_DESA_L) << BIT_SHIFT_HI19Q_TXBD_DESA_L) +#define BITS_HI19Q_TXBD_DESA_L \ + (BIT_MASK_HI19Q_TXBD_DESA_L << BIT_SHIFT_HI19Q_TXBD_DESA_L) +#define BIT_CLEAR_HI19Q_TXBD_DESA_L(x) ((x) & (~BITS_HI19Q_TXBD_DESA_L)) +#define BIT_GET_HI19Q_TXBD_DESA_L(x) \ + (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_L) & BIT_MASK_HI19Q_TXBD_DESA_L) +#define BIT_SET_HI19Q_TXBD_DESA_L(x, v) \ + (BIT_CLEAR_HI19Q_TXBD_DESA_L(x) | BIT_HI19Q_TXBD_DESA_L(v)) + +/* 2 REG_HI19Q_TXBD_DESA_H (Offset 0x235C) */ + +#define BIT_CLR_P0HI19Q_HW_IDX BIT(25) +#define BIT_CLR_P0HI18Q_HW_IDX BIT(24) +#define BIT_CLR_P0HI17Q_HW_IDX BIT(23) +#define BIT_CLR_P0HI16Q_HW_IDX BIT(22) +#define BIT_CLR_P0HI19Q_HOST_IDX BIT(9) +#define BIT_CLR_P0HI18Q_HOST_IDX BIT(8) +#define BIT_CLR_P0HI17Q_HOST_IDX BIT(7) +#define BIT_CLR_P0HI16Q_HOST_IDX BIT(6) + +#define BIT_SHIFT_HI19Q_TXBD_DESA_H 0 +#define BIT_MASK_HI19Q_TXBD_DESA_H 0xffffffffL +#define BIT_HI19Q_TXBD_DESA_H(x) \ + (((x) & BIT_MASK_HI19Q_TXBD_DESA_H) << BIT_SHIFT_HI19Q_TXBD_DESA_H) +#define BITS_HI19Q_TXBD_DESA_H \ + (BIT_MASK_HI19Q_TXBD_DESA_H << BIT_SHIFT_HI19Q_TXBD_DESA_H) +#define BIT_CLEAR_HI19Q_TXBD_DESA_H(x) ((x) & (~BITS_HI19Q_TXBD_DESA_H)) +#define BIT_GET_HI19Q_TXBD_DESA_H(x) \ + (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_H) & BIT_MASK_HI19Q_TXBD_DESA_H) +#define BIT_SET_HI19Q_TXBD_DESA_H(x, v) \ + (BIT_CLEAR_HI19Q_TXBD_DESA_H(x) | BIT_HI19Q_TXBD_DESA_H(v)) + +/* 2 REG_P0HI16Q_TXBD_IDX (Offset 0x2370) */ + +#define BIT_SHIFT_P0HI16Q_HW_IDX 16 +#define BIT_MASK_P0HI16Q_HW_IDX 0xfff +#define BIT_P0HI16Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI16Q_HW_IDX) << BIT_SHIFT_P0HI16Q_HW_IDX) +#define BITS_P0HI16Q_HW_IDX \ + (BIT_MASK_P0HI16Q_HW_IDX << BIT_SHIFT_P0HI16Q_HW_IDX) +#define BIT_CLEAR_P0HI16Q_HW_IDX(x) ((x) & (~BITS_P0HI16Q_HW_IDX)) +#define BIT_GET_P0HI16Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_HW_IDX) & BIT_MASK_P0HI16Q_HW_IDX) +#define BIT_SET_P0HI16Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI16Q_HW_IDX(x) | BIT_P0HI16Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI16Q_HOST_IDX 0 +#define BIT_MASK_P0HI16Q_HOST_IDX 0xfff +#define BIT_P0HI16Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI16Q_HOST_IDX) << BIT_SHIFT_P0HI16Q_HOST_IDX) +#define BITS_P0HI16Q_HOST_IDX \ + (BIT_MASK_P0HI16Q_HOST_IDX << BIT_SHIFT_P0HI16Q_HOST_IDX) +#define BIT_CLEAR_P0HI16Q_HOST_IDX(x) ((x) & (~BITS_P0HI16Q_HOST_IDX)) +#define BIT_GET_P0HI16Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_HOST_IDX) & BIT_MASK_P0HI16Q_HOST_IDX) +#define BIT_SET_P0HI16Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI16Q_HOST_IDX(x) | BIT_P0HI16Q_HOST_IDX(v)) + +/* 2 REG_P0HI17Q_TXBD_IDX (Offset 0x2374) */ + +#define BIT_SHIFT_P0HI17Q_HW_IDX 16 +#define BIT_MASK_P0HI17Q_HW_IDX 0xfff +#define BIT_P0HI17Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI17Q_HW_IDX) << BIT_SHIFT_P0HI17Q_HW_IDX) +#define BITS_P0HI17Q_HW_IDX \ + (BIT_MASK_P0HI17Q_HW_IDX << BIT_SHIFT_P0HI17Q_HW_IDX) +#define BIT_CLEAR_P0HI17Q_HW_IDX(x) ((x) & (~BITS_P0HI17Q_HW_IDX)) +#define BIT_GET_P0HI17Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_HW_IDX) & BIT_MASK_P0HI17Q_HW_IDX) +#define BIT_SET_P0HI17Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI17Q_HW_IDX(x) | BIT_P0HI17Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI17Q_HOST_IDX 0 +#define BIT_MASK_P0HI17Q_HOST_IDX 0xfff +#define BIT_P0HI17Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI17Q_HOST_IDX) << BIT_SHIFT_P0HI17Q_HOST_IDX) +#define BITS_P0HI17Q_HOST_IDX \ + (BIT_MASK_P0HI17Q_HOST_IDX << BIT_SHIFT_P0HI17Q_HOST_IDX) +#define BIT_CLEAR_P0HI17Q_HOST_IDX(x) ((x) & (~BITS_P0HI17Q_HOST_IDX)) +#define BIT_GET_P0HI17Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_HOST_IDX) & BIT_MASK_P0HI17Q_HOST_IDX) +#define BIT_SET_P0HI17Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI17Q_HOST_IDX(x) | BIT_P0HI17Q_HOST_IDX(v)) + +/* 2 REG_P0HI18Q_TXBD_IDX (Offset 0x2378) */ + +#define BIT_SHIFT_P0HI18Q_HW_IDX 16 +#define BIT_MASK_P0HI18Q_HW_IDX 0xfff +#define BIT_P0HI18Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI18Q_HW_IDX) << BIT_SHIFT_P0HI18Q_HW_IDX) +#define BITS_P0HI18Q_HW_IDX \ + (BIT_MASK_P0HI18Q_HW_IDX << BIT_SHIFT_P0HI18Q_HW_IDX) +#define BIT_CLEAR_P0HI18Q_HW_IDX(x) ((x) & (~BITS_P0HI18Q_HW_IDX)) +#define BIT_GET_P0HI18Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_HW_IDX) & BIT_MASK_P0HI18Q_HW_IDX) +#define BIT_SET_P0HI18Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI18Q_HW_IDX(x) | BIT_P0HI18Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI18Q_HOST_IDX 0 +#define BIT_MASK_P0HI18Q_HOST_IDX 0xfff +#define BIT_P0HI18Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI18Q_HOST_IDX) << BIT_SHIFT_P0HI18Q_HOST_IDX) +#define BITS_P0HI18Q_HOST_IDX \ + (BIT_MASK_P0HI18Q_HOST_IDX << BIT_SHIFT_P0HI18Q_HOST_IDX) +#define BIT_CLEAR_P0HI18Q_HOST_IDX(x) ((x) & (~BITS_P0HI18Q_HOST_IDX)) +#define BIT_GET_P0HI18Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_HOST_IDX) & BIT_MASK_P0HI18Q_HOST_IDX) +#define BIT_SET_P0HI18Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI18Q_HOST_IDX(x) | BIT_P0HI18Q_HOST_IDX(v)) + +/* 2 REG_P0HI19Q_TXBD_IDX (Offset 0x237C) */ + +#define BIT_SHIFT_P0HI19Q_HW_IDX 16 +#define BIT_MASK_P0HI19Q_HW_IDX 0xfff +#define BIT_P0HI19Q_HW_IDX(x) \ + (((x) & BIT_MASK_P0HI19Q_HW_IDX) << BIT_SHIFT_P0HI19Q_HW_IDX) +#define BITS_P0HI19Q_HW_IDX \ + (BIT_MASK_P0HI19Q_HW_IDX << BIT_SHIFT_P0HI19Q_HW_IDX) +#define BIT_CLEAR_P0HI19Q_HW_IDX(x) ((x) & (~BITS_P0HI19Q_HW_IDX)) +#define BIT_GET_P0HI19Q_HW_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_HW_IDX) & BIT_MASK_P0HI19Q_HW_IDX) +#define BIT_SET_P0HI19Q_HW_IDX(x, v) \ + (BIT_CLEAR_P0HI19Q_HW_IDX(x) | BIT_P0HI19Q_HW_IDX(v)) + +#define BIT_SHIFT_P0HI19Q_HOST_IDX 0 +#define BIT_MASK_P0HI19Q_HOST_IDX 0xfff +#define BIT_P0HI19Q_HOST_IDX(x) \ + (((x) & BIT_MASK_P0HI19Q_HOST_IDX) << BIT_SHIFT_P0HI19Q_HOST_IDX) +#define BITS_P0HI19Q_HOST_IDX \ + (BIT_MASK_P0HI19Q_HOST_IDX << BIT_SHIFT_P0HI19Q_HOST_IDX) +#define BIT_CLEAR_P0HI19Q_HOST_IDX(x) ((x) & (~BITS_P0HI19Q_HOST_IDX)) +#define BIT_GET_P0HI19Q_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_HOST_IDX) & BIT_MASK_P0HI19Q_HOST_IDX) +#define BIT_SET_P0HI19Q_HOST_IDX(x, v) \ + (BIT_CLEAR_P0HI19Q_HOST_IDX(x) | BIT_P0HI19Q_HOST_IDX(v)) + +/* 2 REG_P0HI16Q_HI17Q_TXBD_NUM (Offset 0x2380) */ + +#define BIT_P0HI17Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI17Q_DESC_MODE 28 +#define BIT_MASK_P0HI17Q_DESC_MODE 0x3 +#define BIT_P0HI17Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI17Q_DESC_MODE) << BIT_SHIFT_P0HI17Q_DESC_MODE) +#define BITS_P0HI17Q_DESC_MODE \ + (BIT_MASK_P0HI17Q_DESC_MODE << BIT_SHIFT_P0HI17Q_DESC_MODE) +#define BIT_CLEAR_P0HI17Q_DESC_MODE(x) ((x) & (~BITS_P0HI17Q_DESC_MODE)) +#define BIT_GET_P0HI17Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_DESC_MODE) & BIT_MASK_P0HI17Q_DESC_MODE) +#define BIT_SET_P0HI17Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI17Q_DESC_MODE(x) | BIT_P0HI17Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI17Q_DESC_NUM 16 +#define BIT_MASK_P0HI17Q_DESC_NUM 0xfff +#define BIT_P0HI17Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI17Q_DESC_NUM) << BIT_SHIFT_P0HI17Q_DESC_NUM) +#define BITS_P0HI17Q_DESC_NUM \ + (BIT_MASK_P0HI17Q_DESC_NUM << BIT_SHIFT_P0HI17Q_DESC_NUM) +#define BIT_CLEAR_P0HI17Q_DESC_NUM(x) ((x) & (~BITS_P0HI17Q_DESC_NUM)) +#define BIT_GET_P0HI17Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_DESC_NUM) & BIT_MASK_P0HI17Q_DESC_NUM) +#define BIT_SET_P0HI17Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI17Q_DESC_NUM(x) | BIT_P0HI17Q_DESC_NUM(v)) + +#define BIT_P0HI16Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI16Q_DESC_MODE 12 +#define BIT_MASK_P0HI16Q_DESC_MODE 0x3 +#define BIT_P0HI16Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI16Q_DESC_MODE) << BIT_SHIFT_P0HI16Q_DESC_MODE) +#define BITS_P0HI16Q_DESC_MODE \ + (BIT_MASK_P0HI16Q_DESC_MODE << BIT_SHIFT_P0HI16Q_DESC_MODE) +#define BIT_CLEAR_P0HI16Q_DESC_MODE(x) ((x) & (~BITS_P0HI16Q_DESC_MODE)) +#define BIT_GET_P0HI16Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_DESC_MODE) & BIT_MASK_P0HI16Q_DESC_MODE) +#define BIT_SET_P0HI16Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI16Q_DESC_MODE(x) | BIT_P0HI16Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI16Q_DESC_NUM 0 +#define BIT_MASK_P0HI16Q_DESC_NUM 0xfff +#define BIT_P0HI16Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI16Q_DESC_NUM) << BIT_SHIFT_P0HI16Q_DESC_NUM) +#define BITS_P0HI16Q_DESC_NUM \ + (BIT_MASK_P0HI16Q_DESC_NUM << BIT_SHIFT_P0HI16Q_DESC_NUM) +#define BIT_CLEAR_P0HI16Q_DESC_NUM(x) ((x) & (~BITS_P0HI16Q_DESC_NUM)) +#define BIT_GET_P0HI16Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_DESC_NUM) & BIT_MASK_P0HI16Q_DESC_NUM) +#define BIT_SET_P0HI16Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI16Q_DESC_NUM(x) | BIT_P0HI16Q_DESC_NUM(v)) + +/* 2 REG_P0HI18Q_HI19Q_TXBD_NUM (Offset 0x2384) */ + +#define BIT_P0HI19Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI19Q_DESC_MODE 28 +#define BIT_MASK_P0HI19Q_DESC_MODE 0x3 +#define BIT_P0HI19Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI19Q_DESC_MODE) << BIT_SHIFT_P0HI19Q_DESC_MODE) +#define BITS_P0HI19Q_DESC_MODE \ + (BIT_MASK_P0HI19Q_DESC_MODE << BIT_SHIFT_P0HI19Q_DESC_MODE) +#define BIT_CLEAR_P0HI19Q_DESC_MODE(x) ((x) & (~BITS_P0HI19Q_DESC_MODE)) +#define BIT_GET_P0HI19Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_DESC_MODE) & BIT_MASK_P0HI19Q_DESC_MODE) +#define BIT_SET_P0HI19Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI19Q_DESC_MODE(x) | BIT_P0HI19Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI19Q_DESC_NUM 16 +#define BIT_MASK_P0HI19Q_DESC_NUM 0xfff +#define BIT_P0HI19Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI19Q_DESC_NUM) << BIT_SHIFT_P0HI19Q_DESC_NUM) +#define BITS_P0HI19Q_DESC_NUM \ + (BIT_MASK_P0HI19Q_DESC_NUM << BIT_SHIFT_P0HI19Q_DESC_NUM) +#define BIT_CLEAR_P0HI19Q_DESC_NUM(x) ((x) & (~BITS_P0HI19Q_DESC_NUM)) +#define BIT_GET_P0HI19Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_DESC_NUM) & BIT_MASK_P0HI19Q_DESC_NUM) +#define BIT_SET_P0HI19Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI19Q_DESC_NUM(x) | BIT_P0HI19Q_DESC_NUM(v)) + +#define BIT_P0HI18Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI18Q_DESC_MODE 12 +#define BIT_MASK_P0HI18Q_DESC_MODE 0x3 +#define BIT_P0HI18Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI18Q_DESC_MODE) << BIT_SHIFT_P0HI18Q_DESC_MODE) +#define BITS_P0HI18Q_DESC_MODE \ + (BIT_MASK_P0HI18Q_DESC_MODE << BIT_SHIFT_P0HI18Q_DESC_MODE) +#define BIT_CLEAR_P0HI18Q_DESC_MODE(x) ((x) & (~BITS_P0HI18Q_DESC_MODE)) +#define BIT_GET_P0HI18Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_DESC_MODE) & BIT_MASK_P0HI18Q_DESC_MODE) +#define BIT_SET_P0HI18Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI18Q_DESC_MODE(x) | BIT_P0HI18Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI18Q_DESC_NUM 0 +#define BIT_MASK_P0HI18Q_DESC_NUM 0xfff +#define BIT_P0HI18Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI18Q_DESC_NUM) << BIT_SHIFT_P0HI18Q_DESC_NUM) +#define BITS_P0HI18Q_DESC_NUM \ + (BIT_MASK_P0HI18Q_DESC_NUM << BIT_SHIFT_P0HI18Q_DESC_NUM) +#define BIT_CLEAR_P0HI18Q_DESC_NUM(x) ((x) & (~BITS_P0HI18Q_DESC_NUM)) +#define BIT_GET_P0HI18Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_DESC_NUM) & BIT_MASK_P0HI18Q_DESC_NUM) +#define BIT_SET_P0HI18Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI18Q_DESC_NUM(x) | BIT_P0HI18Q_DESC_NUM(v)) + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_PCIE_HISR1 (Offset 0x23BC) */ + +#define BIT_CPU_MGQ_EARLY_INT BIT(6) +#define BIT_PSTIMER_5 BIT(4) +#define BIT_PSTIMER_4 BIT(3) +#define BIT_PSTIMER_3 BIT(2) +#define BIT_BB_STOPRX_INT BIT(0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_P0HI8Q_HI9Q_TXBD_NUM (Offset 0x23C0) */ + +#define BIT_P0HI9Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI9Q_DESC_MODE 28 +#define BIT_MASK_P0HI9Q_DESC_MODE 0x3 +#define BIT_P0HI9Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI9Q_DESC_MODE) << BIT_SHIFT_P0HI9Q_DESC_MODE) +#define BITS_P0HI9Q_DESC_MODE \ + (BIT_MASK_P0HI9Q_DESC_MODE << BIT_SHIFT_P0HI9Q_DESC_MODE) +#define BIT_CLEAR_P0HI9Q_DESC_MODE(x) ((x) & (~BITS_P0HI9Q_DESC_MODE)) +#define BIT_GET_P0HI9Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_DESC_MODE) & BIT_MASK_P0HI9Q_DESC_MODE) +#define BIT_SET_P0HI9Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI9Q_DESC_MODE(x) | BIT_P0HI9Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI9Q_DESC_NUM 16 +#define BIT_MASK_P0HI9Q_DESC_NUM 0xfff +#define BIT_P0HI9Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI9Q_DESC_NUM) << BIT_SHIFT_P0HI9Q_DESC_NUM) +#define BITS_P0HI9Q_DESC_NUM \ + (BIT_MASK_P0HI9Q_DESC_NUM << BIT_SHIFT_P0HI9Q_DESC_NUM) +#define BIT_CLEAR_P0HI9Q_DESC_NUM(x) ((x) & (~BITS_P0HI9Q_DESC_NUM)) +#define BIT_GET_P0HI9Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_DESC_NUM) & BIT_MASK_P0HI9Q_DESC_NUM) +#define BIT_SET_P0HI9Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI9Q_DESC_NUM(x) | BIT_P0HI9Q_DESC_NUM(v)) + +#define BIT_P0HI8Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI8Q_DESC_MODE 12 +#define BIT_MASK_P0HI8Q_DESC_MODE 0x3 +#define BIT_P0HI8Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI8Q_DESC_MODE) << BIT_SHIFT_P0HI8Q_DESC_MODE) +#define BITS_P0HI8Q_DESC_MODE \ + (BIT_MASK_P0HI8Q_DESC_MODE << BIT_SHIFT_P0HI8Q_DESC_MODE) +#define BIT_CLEAR_P0HI8Q_DESC_MODE(x) ((x) & (~BITS_P0HI8Q_DESC_MODE)) +#define BIT_GET_P0HI8Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_DESC_MODE) & BIT_MASK_P0HI8Q_DESC_MODE) +#define BIT_SET_P0HI8Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI8Q_DESC_MODE(x) | BIT_P0HI8Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI8Q_DESC_NUM 0 +#define BIT_MASK_P0HI8Q_DESC_NUM 0xfff +#define BIT_P0HI8Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI8Q_DESC_NUM) << BIT_SHIFT_P0HI8Q_DESC_NUM) +#define BITS_P0HI8Q_DESC_NUM \ + (BIT_MASK_P0HI8Q_DESC_NUM << BIT_SHIFT_P0HI8Q_DESC_NUM) +#define BIT_CLEAR_P0HI8Q_DESC_NUM(x) ((x) & (~BITS_P0HI8Q_DESC_NUM)) +#define BIT_GET_P0HI8Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_DESC_NUM) & BIT_MASK_P0HI8Q_DESC_NUM) +#define BIT_SET_P0HI8Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI8Q_DESC_NUM(x) | BIT_P0HI8Q_DESC_NUM(v)) + +/* 2 REG_P0HI10Q_HI11Q_TXBD_NUM (Offset 0x23C4) */ + +#define BIT_P0HI11Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI11Q_DESC_MODE 28 +#define BIT_MASK_P0HI11Q_DESC_MODE 0x3 +#define BIT_P0HI11Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI11Q_DESC_MODE) << BIT_SHIFT_P0HI11Q_DESC_MODE) +#define BITS_P0HI11Q_DESC_MODE \ + (BIT_MASK_P0HI11Q_DESC_MODE << BIT_SHIFT_P0HI11Q_DESC_MODE) +#define BIT_CLEAR_P0HI11Q_DESC_MODE(x) ((x) & (~BITS_P0HI11Q_DESC_MODE)) +#define BIT_GET_P0HI11Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_DESC_MODE) & BIT_MASK_P0HI11Q_DESC_MODE) +#define BIT_SET_P0HI11Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI11Q_DESC_MODE(x) | BIT_P0HI11Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI11Q_DESC_NUM 16 +#define BIT_MASK_P0HI11Q_DESC_NUM 0xfff +#define BIT_P0HI11Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI11Q_DESC_NUM) << BIT_SHIFT_P0HI11Q_DESC_NUM) +#define BITS_P0HI11Q_DESC_NUM \ + (BIT_MASK_P0HI11Q_DESC_NUM << BIT_SHIFT_P0HI11Q_DESC_NUM) +#define BIT_CLEAR_P0HI11Q_DESC_NUM(x) ((x) & (~BITS_P0HI11Q_DESC_NUM)) +#define BIT_GET_P0HI11Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_DESC_NUM) & BIT_MASK_P0HI11Q_DESC_NUM) +#define BIT_SET_P0HI11Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI11Q_DESC_NUM(x) | BIT_P0HI11Q_DESC_NUM(v)) + +#define BIT_P0HI10Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI10Q_DESC_MODE 12 +#define BIT_MASK_P0HI10Q_DESC_MODE 0x3 +#define BIT_P0HI10Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI10Q_DESC_MODE) << BIT_SHIFT_P0HI10Q_DESC_MODE) +#define BITS_P0HI10Q_DESC_MODE \ + (BIT_MASK_P0HI10Q_DESC_MODE << BIT_SHIFT_P0HI10Q_DESC_MODE) +#define BIT_CLEAR_P0HI10Q_DESC_MODE(x) ((x) & (~BITS_P0HI10Q_DESC_MODE)) +#define BIT_GET_P0HI10Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_DESC_MODE) & BIT_MASK_P0HI10Q_DESC_MODE) +#define BIT_SET_P0HI10Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI10Q_DESC_MODE(x) | BIT_P0HI10Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI10Q_DESC_NUM 0 +#define BIT_MASK_P0HI10Q_DESC_NUM 0xfff +#define BIT_P0HI10Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI10Q_DESC_NUM) << BIT_SHIFT_P0HI10Q_DESC_NUM) +#define BITS_P0HI10Q_DESC_NUM \ + (BIT_MASK_P0HI10Q_DESC_NUM << BIT_SHIFT_P0HI10Q_DESC_NUM) +#define BIT_CLEAR_P0HI10Q_DESC_NUM(x) ((x) & (~BITS_P0HI10Q_DESC_NUM)) +#define BIT_GET_P0HI10Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_DESC_NUM) & BIT_MASK_P0HI10Q_DESC_NUM) +#define BIT_SET_P0HI10Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI10Q_DESC_NUM(x) | BIT_P0HI10Q_DESC_NUM(v)) + +/* 2 REG_P0HI12Q_HI13Q_TXBD_NUM (Offset 0x23C8) */ + +#define BIT_P0HI13Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI13Q_DESC_MODE 28 +#define BIT_MASK_P0HI13Q_DESC_MODE 0x3 +#define BIT_P0HI13Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI13Q_DESC_MODE) << BIT_SHIFT_P0HI13Q_DESC_MODE) +#define BITS_P0HI13Q_DESC_MODE \ + (BIT_MASK_P0HI13Q_DESC_MODE << BIT_SHIFT_P0HI13Q_DESC_MODE) +#define BIT_CLEAR_P0HI13Q_DESC_MODE(x) ((x) & (~BITS_P0HI13Q_DESC_MODE)) +#define BIT_GET_P0HI13Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_DESC_MODE) & BIT_MASK_P0HI13Q_DESC_MODE) +#define BIT_SET_P0HI13Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI13Q_DESC_MODE(x) | BIT_P0HI13Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI13Q_DESC_NUM 16 +#define BIT_MASK_P0HI13Q_DESC_NUM 0xfff +#define BIT_P0HI13Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI13Q_DESC_NUM) << BIT_SHIFT_P0HI13Q_DESC_NUM) +#define BITS_P0HI13Q_DESC_NUM \ + (BIT_MASK_P0HI13Q_DESC_NUM << BIT_SHIFT_P0HI13Q_DESC_NUM) +#define BIT_CLEAR_P0HI13Q_DESC_NUM(x) ((x) & (~BITS_P0HI13Q_DESC_NUM)) +#define BIT_GET_P0HI13Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_DESC_NUM) & BIT_MASK_P0HI13Q_DESC_NUM) +#define BIT_SET_P0HI13Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI13Q_DESC_NUM(x) | BIT_P0HI13Q_DESC_NUM(v)) + +#define BIT_P0HI12Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI12Q_DESC_MODE 12 +#define BIT_MASK_P0HI12Q_DESC_MODE 0x3 +#define BIT_P0HI12Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI12Q_DESC_MODE) << BIT_SHIFT_P0HI12Q_DESC_MODE) +#define BITS_P0HI12Q_DESC_MODE \ + (BIT_MASK_P0HI12Q_DESC_MODE << BIT_SHIFT_P0HI12Q_DESC_MODE) +#define BIT_CLEAR_P0HI12Q_DESC_MODE(x) ((x) & (~BITS_P0HI12Q_DESC_MODE)) +#define BIT_GET_P0HI12Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_DESC_MODE) & BIT_MASK_P0HI12Q_DESC_MODE) +#define BIT_SET_P0HI12Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI12Q_DESC_MODE(x) | BIT_P0HI12Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI12Q_DESC_NUM 0 +#define BIT_MASK_P0HI12Q_DESC_NUM 0xfff +#define BIT_P0HI12Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI12Q_DESC_NUM) << BIT_SHIFT_P0HI12Q_DESC_NUM) +#define BITS_P0HI12Q_DESC_NUM \ + (BIT_MASK_P0HI12Q_DESC_NUM << BIT_SHIFT_P0HI12Q_DESC_NUM) +#define BIT_CLEAR_P0HI12Q_DESC_NUM(x) ((x) & (~BITS_P0HI12Q_DESC_NUM)) +#define BIT_GET_P0HI12Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_DESC_NUM) & BIT_MASK_P0HI12Q_DESC_NUM) +#define BIT_SET_P0HI12Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI12Q_DESC_NUM(x) | BIT_P0HI12Q_DESC_NUM(v)) + +/* 2 REG_P0HI14Q_HI15Q_TXBD_NUM (Offset 0x23CC) */ + +#define BIT_P0HI15Q_FLAG BIT(30) + +#define BIT_SHIFT_P0HI15Q_DESC_MODE 28 +#define BIT_MASK_P0HI15Q_DESC_MODE 0x3 +#define BIT_P0HI15Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI15Q_DESC_MODE) << BIT_SHIFT_P0HI15Q_DESC_MODE) +#define BITS_P0HI15Q_DESC_MODE \ + (BIT_MASK_P0HI15Q_DESC_MODE << BIT_SHIFT_P0HI15Q_DESC_MODE) +#define BIT_CLEAR_P0HI15Q_DESC_MODE(x) ((x) & (~BITS_P0HI15Q_DESC_MODE)) +#define BIT_GET_P0HI15Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_DESC_MODE) & BIT_MASK_P0HI15Q_DESC_MODE) +#define BIT_SET_P0HI15Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI15Q_DESC_MODE(x) | BIT_P0HI15Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI15Q_DESC_NUM 16 +#define BIT_MASK_P0HI15Q_DESC_NUM 0xfff +#define BIT_P0HI15Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI15Q_DESC_NUM) << BIT_SHIFT_P0HI15Q_DESC_NUM) +#define BITS_P0HI15Q_DESC_NUM \ + (BIT_MASK_P0HI15Q_DESC_NUM << BIT_SHIFT_P0HI15Q_DESC_NUM) +#define BIT_CLEAR_P0HI15Q_DESC_NUM(x) ((x) & (~BITS_P0HI15Q_DESC_NUM)) +#define BIT_GET_P0HI15Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_DESC_NUM) & BIT_MASK_P0HI15Q_DESC_NUM) +#define BIT_SET_P0HI15Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI15Q_DESC_NUM(x) | BIT_P0HI15Q_DESC_NUM(v)) + +#define BIT_P0HI14Q_FLAG BIT(14) + +#define BIT_SHIFT_P0HI14Q_DESC_MODE 12 +#define BIT_MASK_P0HI14Q_DESC_MODE 0x3 +#define BIT_P0HI14Q_DESC_MODE(x) \ + (((x) & BIT_MASK_P0HI14Q_DESC_MODE) << BIT_SHIFT_P0HI14Q_DESC_MODE) +#define BITS_P0HI14Q_DESC_MODE \ + (BIT_MASK_P0HI14Q_DESC_MODE << BIT_SHIFT_P0HI14Q_DESC_MODE) +#define BIT_CLEAR_P0HI14Q_DESC_MODE(x) ((x) & (~BITS_P0HI14Q_DESC_MODE)) +#define BIT_GET_P0HI14Q_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_DESC_MODE) & BIT_MASK_P0HI14Q_DESC_MODE) +#define BIT_SET_P0HI14Q_DESC_MODE(x, v) \ + (BIT_CLEAR_P0HI14Q_DESC_MODE(x) | BIT_P0HI14Q_DESC_MODE(v)) + +#define BIT_SHIFT_P0HI14Q_DESC_NUM 0 +#define BIT_MASK_P0HI14Q_DESC_NUM 0xfff +#define BIT_P0HI14Q_DESC_NUM(x) \ + (((x) & BIT_MASK_P0HI14Q_DESC_NUM) << BIT_SHIFT_P0HI14Q_DESC_NUM) +#define BITS_P0HI14Q_DESC_NUM \ + (BIT_MASK_P0HI14Q_DESC_NUM << BIT_SHIFT_P0HI14Q_DESC_NUM) +#define BIT_CLEAR_P0HI14Q_DESC_NUM(x) ((x) & (~BITS_P0HI14Q_DESC_NUM)) +#define BIT_GET_P0HI14Q_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_DESC_NUM) & BIT_MASK_P0HI14Q_DESC_NUM) +#define BIT_SET_P0HI14Q_DESC_NUM(x, v) \ + (BIT_CLEAR_P0HI14Q_DESC_NUM(x) | BIT_P0HI14Q_DESC_NUM(v)) + +/* 2 REG_ACH6_ACH7_TXBD_NUM (Offset 0x23F0) */ + +#define BIT_PCIE_ACH7_FLAG BIT(30) + +#define BIT_SHIFT_ACH7_DESC_MODE 28 +#define BIT_MASK_ACH7_DESC_MODE 0x3 +#define BIT_ACH7_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH7_DESC_MODE) << BIT_SHIFT_ACH7_DESC_MODE) +#define BITS_ACH7_DESC_MODE \ + (BIT_MASK_ACH7_DESC_MODE << BIT_SHIFT_ACH7_DESC_MODE) +#define BIT_CLEAR_ACH7_DESC_MODE(x) ((x) & (~BITS_ACH7_DESC_MODE)) +#define BIT_GET_ACH7_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH7_DESC_MODE) & BIT_MASK_ACH7_DESC_MODE) +#define BIT_SET_ACH7_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH7_DESC_MODE(x) | BIT_ACH7_DESC_MODE(v)) + +#define BIT_SHIFT_ACH7_DESC_NUM 16 +#define BIT_MASK_ACH7_DESC_NUM 0xfff +#define BIT_ACH7_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH7_DESC_NUM) << BIT_SHIFT_ACH7_DESC_NUM) +#define BITS_ACH7_DESC_NUM (BIT_MASK_ACH7_DESC_NUM << BIT_SHIFT_ACH7_DESC_NUM) +#define BIT_CLEAR_ACH7_DESC_NUM(x) ((x) & (~BITS_ACH7_DESC_NUM)) +#define BIT_GET_ACH7_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH7_DESC_NUM) & BIT_MASK_ACH7_DESC_NUM) +#define BIT_SET_ACH7_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH7_DESC_NUM(x) | BIT_ACH7_DESC_NUM(v)) + +#define BIT_PCIE_ACH6_FLAG BIT(14) + +#define BIT_SHIFT_ACH6_DESC_MODE 12 +#define BIT_MASK_ACH6_DESC_MODE 0x3 +#define BIT_ACH6_DESC_MODE(x) \ + (((x) & BIT_MASK_ACH6_DESC_MODE) << BIT_SHIFT_ACH6_DESC_MODE) +#define BITS_ACH6_DESC_MODE \ + (BIT_MASK_ACH6_DESC_MODE << BIT_SHIFT_ACH6_DESC_MODE) +#define BIT_CLEAR_ACH6_DESC_MODE(x) ((x) & (~BITS_ACH6_DESC_MODE)) +#define BIT_GET_ACH6_DESC_MODE(x) \ + (((x) >> BIT_SHIFT_ACH6_DESC_MODE) & BIT_MASK_ACH6_DESC_MODE) +#define BIT_SET_ACH6_DESC_MODE(x, v) \ + (BIT_CLEAR_ACH6_DESC_MODE(x) | BIT_ACH6_DESC_MODE(v)) + +#define BIT_SHIFT_ACH6_DESC_NUM 0 +#define BIT_MASK_ACH6_DESC_NUM 0xfff +#define BIT_ACH6_DESC_NUM(x) \ + (((x) & BIT_MASK_ACH6_DESC_NUM) << BIT_SHIFT_ACH6_DESC_NUM) +#define BITS_ACH6_DESC_NUM (BIT_MASK_ACH6_DESC_NUM << BIT_SHIFT_ACH6_DESC_NUM) +#define BIT_CLEAR_ACH6_DESC_NUM(x) ((x) & (~BITS_ACH6_DESC_NUM)) +#define BIT_GET_ACH6_DESC_NUM(x) \ + (((x) >> BIT_SHIFT_ACH6_DESC_NUM) & BIT_MASK_ACH6_DESC_NUM) +#define BIT_SET_ACH6_DESC_NUM(x, v) \ + (BIT_CLEAR_ACH6_DESC_NUM(x) | BIT_ACH6_DESC_NUM(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_FAST_EDCA_VOVI_SETTING_V1 (Offset 0x2448) */ + +#define BIT_SHIFT_VO_FAST_EDCA_TO_V1 0 +#define BIT_MASK_VO_FAST_EDCA_TO_V1 0xffff +#define BIT_VO_FAST_EDCA_TO_V1(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO_V1) << BIT_SHIFT_VO_FAST_EDCA_TO_V1) +#define BITS_VO_FAST_EDCA_TO_V1 \ + (BIT_MASK_VO_FAST_EDCA_TO_V1 << BIT_SHIFT_VO_FAST_EDCA_TO_V1) +#define BIT_CLEAR_VO_FAST_EDCA_TO_V1(x) ((x) & (~BITS_VO_FAST_EDCA_TO_V1)) +#define BIT_GET_VO_FAST_EDCA_TO_V1(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_V1) & BIT_MASK_VO_FAST_EDCA_TO_V1) +#define BIT_SET_VO_FAST_EDCA_TO_V1(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO_V1(x) | BIT_VO_FAST_EDCA_TO_V1(v)) + +/* 2 REG_FAST_EDCA_BEBK_SETTING_V1 (Offset 0x244C) */ + +#define BIT_SHIFT_BE_FAST_EDCA_TO_V1 0 +#define BIT_MASK_BE_FAST_EDCA_TO_V1 0xffff +#define BIT_BE_FAST_EDCA_TO_V1(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO_V1) << BIT_SHIFT_BE_FAST_EDCA_TO_V1) +#define BITS_BE_FAST_EDCA_TO_V1 \ + (BIT_MASK_BE_FAST_EDCA_TO_V1 << BIT_SHIFT_BE_FAST_EDCA_TO_V1) +#define BIT_CLEAR_BE_FAST_EDCA_TO_V1(x) ((x) & (~BITS_BE_FAST_EDCA_TO_V1)) +#define BIT_GET_BE_FAST_EDCA_TO_V1(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_V1) & BIT_MASK_BE_FAST_EDCA_TO_V1) +#define BIT_SET_BE_FAST_EDCA_TO_V1(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO_V1(x) | BIT_BE_FAST_EDCA_TO_V1(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_0_V1 (Offset 0x2460) */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_0(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) +#define BITS_R_MACID_RELEASE_SUCCESS_0 \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_0 \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_0) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_0(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_0(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_2_V1 (Offset 0x2468) */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_2(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) +#define BITS_R_MACID_RELEASE_SUCCESS_2 \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_2 \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_2) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_2(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_2(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_V1 (Offset 0x247C) */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) +#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT) + +/* 2 REG_NAN_INFO0 (Offset 0x2480) */ + +#define BIT_SHIFT_NAN_INFO0 0 +#define BIT_MASK_NAN_INFO0 0xffffffffL +#define BIT_NAN_INFO0(x) (((x) & BIT_MASK_NAN_INFO0) << BIT_SHIFT_NAN_INFO0) +#define BITS_NAN_INFO0 (BIT_MASK_NAN_INFO0 << BIT_SHIFT_NAN_INFO0) +#define BIT_CLEAR_NAN_INFO0(x) ((x) & (~BITS_NAN_INFO0)) +#define BIT_GET_NAN_INFO0(x) (((x) >> BIT_SHIFT_NAN_INFO0) & BIT_MASK_NAN_INFO0) +#define BIT_SET_NAN_INFO0(x, v) (BIT_CLEAR_NAN_INFO0(x) | BIT_NAN_INFO0(v)) + +/* 2 REG_NAN_INFO1 (Offset 0x2484) */ + +#define BIT_SHIFT_NAN_INFO1 0 +#define BIT_MASK_NAN_INFO1 0xffffffffL +#define BIT_NAN_INFO1(x) (((x) & BIT_MASK_NAN_INFO1) << BIT_SHIFT_NAN_INFO1) +#define BITS_NAN_INFO1 (BIT_MASK_NAN_INFO1 << BIT_SHIFT_NAN_INFO1) +#define BIT_CLEAR_NAN_INFO1(x) ((x) & (~BITS_NAN_INFO1)) +#define BIT_GET_NAN_INFO1(x) (((x) >> BIT_SHIFT_NAN_INFO1) & BIT_MASK_NAN_INFO1) +#define BIT_SET_NAN_INFO1(x, v) (BIT_CLEAR_NAN_INFO1(x) | BIT_NAN_INFO1(v)) + +/* 2 REG_NAN_INFO2 (Offset 0x2488) */ + +#define BIT_SHIFT_NAN_INFO2 0 +#define BIT_MASK_NAN_INFO2 0xffffffffL +#define BIT_NAN_INFO2(x) (((x) & BIT_MASK_NAN_INFO2) << BIT_SHIFT_NAN_INFO2) +#define BITS_NAN_INFO2 (BIT_MASK_NAN_INFO2 << BIT_SHIFT_NAN_INFO2) +#define BIT_CLEAR_NAN_INFO2(x) ((x) & (~BITS_NAN_INFO2)) +#define BIT_GET_NAN_INFO2(x) (((x) >> BIT_SHIFT_NAN_INFO2) & BIT_MASK_NAN_INFO2) +#define BIT_SET_NAN_INFO2(x, v) (BIT_CLEAR_NAN_INFO2(x) | BIT_NAN_INFO2(v)) + +/* 2 REG_NAN_INFO3 (Offset 0x248C) */ + +#define BIT_SHIFT_NAN_INFO3 0 +#define BIT_MASK_NAN_INFO3 0xffffffffL +#define BIT_NAN_INFO3(x) (((x) & BIT_MASK_NAN_INFO3) << BIT_SHIFT_NAN_INFO3) +#define BITS_NAN_INFO3 (BIT_MASK_NAN_INFO3 << BIT_SHIFT_NAN_INFO3) +#define BIT_CLEAR_NAN_INFO3(x) ((x) & (~BITS_NAN_INFO3)) +#define BIT_GET_NAN_INFO3(x) (((x) >> BIT_SHIFT_NAN_INFO3) & BIT_MASK_NAN_INFO3) +#define BIT_SET_NAN_INFO3(x, v) (BIT_CLEAR_NAN_INFO3(x) | BIT_NAN_INFO3(v)) + +/* 2 REG_NAN_INFO4 (Offset 0x2490) */ + +#define BIT_SHIFT_NAN_INFO4 0 +#define BIT_MASK_NAN_INFO4 0xffffffffL +#define BIT_NAN_INFO4(x) (((x) & BIT_MASK_NAN_INFO4) << BIT_SHIFT_NAN_INFO4) +#define BITS_NAN_INFO4 (BIT_MASK_NAN_INFO4 << BIT_SHIFT_NAN_INFO4) +#define BIT_CLEAR_NAN_INFO4(x) ((x) & (~BITS_NAN_INFO4)) +#define BIT_GET_NAN_INFO4(x) (((x) >> BIT_SHIFT_NAN_INFO4) & BIT_MASK_NAN_INFO4) +#define BIT_SET_NAN_INFO4(x, v) (BIT_CLEAR_NAN_INFO4(x) | BIT_NAN_INFO4(v)) + +/* 2 REG_NAN_INFO5 (Offset 0x2494) */ + +#define BIT_SHIFT_NAN_INFO5 0 +#define BIT_MASK_NAN_INFO5 0xffffffffL +#define BIT_NAN_INFO5(x) (((x) & BIT_MASK_NAN_INFO5) << BIT_SHIFT_NAN_INFO5) +#define BITS_NAN_INFO5 (BIT_MASK_NAN_INFO5 << BIT_SHIFT_NAN_INFO5) +#define BIT_CLEAR_NAN_INFO5(x) ((x) & (~BITS_NAN_INFO5)) +#define BIT_GET_NAN_INFO5(x) (((x) >> BIT_SHIFT_NAN_INFO5) & BIT_MASK_NAN_INFO5) +#define BIT_SET_NAN_INFO5(x, v) (BIT_CLEAR_NAN_INFO5(x) | BIT_NAN_INFO5(v)) + +/* 2 REG_NAN_INFO6 (Offset 0x2498) */ + +#define BIT_SHIFT_NAN_INFO6 0 +#define BIT_MASK_NAN_INFO6 0xffffffffL +#define BIT_NAN_INFO6(x) (((x) & BIT_MASK_NAN_INFO6) << BIT_SHIFT_NAN_INFO6) +#define BITS_NAN_INFO6 (BIT_MASK_NAN_INFO6 << BIT_SHIFT_NAN_INFO6) +#define BIT_CLEAR_NAN_INFO6(x) ((x) & (~BITS_NAN_INFO6)) +#define BIT_GET_NAN_INFO6(x) (((x) >> BIT_SHIFT_NAN_INFO6) & BIT_MASK_NAN_INFO6) +#define BIT_SET_NAN_INFO6(x, v) (BIT_CLEAR_NAN_INFO6(x) | BIT_NAN_INFO6(v)) + +/* 2 REG_NAN_INFO7 (Offset 0x249C) */ + +#define BIT_SHIFT_NAN_INFO7 0 +#define BIT_MASK_NAN_INFO7 0xffffffffL +#define BIT_NAN_INFO7(x) (((x) & BIT_MASK_NAN_INFO7) << BIT_SHIFT_NAN_INFO7) +#define BITS_NAN_INFO7 (BIT_MASK_NAN_INFO7 << BIT_SHIFT_NAN_INFO7) +#define BIT_CLEAR_NAN_INFO7(x) ((x) & (~BITS_NAN_INFO7)) +#define BIT_GET_NAN_INFO7(x) (((x) >> BIT_SHIFT_NAN_INFO7) & BIT_MASK_NAN_INFO7) +#define BIT_SET_NAN_INFO7(x, v) (BIT_CLEAR_NAN_INFO7(x) | BIT_NAN_INFO7(v)) + +/* 2 REG_NAN_INFO8 (Offset 0x24A0) */ + +#define BIT_SHIFT_NAN_INFO8 0 +#define BIT_MASK_NAN_INFO8 0xffffffffL +#define BIT_NAN_INFO8(x) (((x) & BIT_MASK_NAN_INFO8) << BIT_SHIFT_NAN_INFO8) +#define BITS_NAN_INFO8 (BIT_MASK_NAN_INFO8 << BIT_SHIFT_NAN_INFO8) +#define BIT_CLEAR_NAN_INFO8(x) ((x) & (~BITS_NAN_INFO8)) +#define BIT_GET_NAN_INFO8(x) (((x) >> BIT_SHIFT_NAN_INFO8) & BIT_MASK_NAN_INFO8) +#define BIT_SET_NAN_INFO8(x, v) (BIT_CLEAR_NAN_INFO8(x) | BIT_NAN_INFO8(v)) + +/* 2 REG_NAN_INFO9 (Offset 0x24A4) */ + +#define BIT_SHIFT_NAN_INFO9 0 +#define BIT_MASK_NAN_INFO9 0xffffffffL +#define BIT_NAN_INFO9(x) (((x) & BIT_MASK_NAN_INFO9) << BIT_SHIFT_NAN_INFO9) +#define BITS_NAN_INFO9 (BIT_MASK_NAN_INFO9 << BIT_SHIFT_NAN_INFO9) +#define BIT_CLEAR_NAN_INFO9(x) ((x) & (~BITS_NAN_INFO9)) +#define BIT_GET_NAN_INFO9(x) (((x) >> BIT_SHIFT_NAN_INFO9) & BIT_MASK_NAN_INFO9) +#define BIT_SET_NAN_INFO9(x, v) (BIT_CLEAR_NAN_INFO9(x) | BIT_NAN_INFO9(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +/* 2 REG_CHNL_INFO_CTRL_V1 (Offset 0x24D0) */ + +#define BIT_CHNL_REF_EDCA BIT(5) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CHNL_INFO_CTRL_V1 (Offset 0x24D0) */ + +#define BIT_CHNL_REF_CCA BIT(4) +#define BIT_MACTX_ERR_4 BIT(4) + +#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD 1 +#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD 0xffffff +#define BIT_VHTHT_MIMO_CTRL_FIELD(x) \ + (((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD) \ + << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) +#define BITS_VHTHT_MIMO_CTRL_FIELD \ + (BIT_MASK_VHTHT_MIMO_CTRL_FIELD << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) +#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD)) +#define BIT_GET_VHTHT_MIMO_CTRL_FIELD(x) \ + (((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) & \ + BIT_MASK_VHTHT_MIMO_CTRL_FIELD) +#define BIT_SET_VHTHT_MIMO_CTRL_FIELD(x, v) \ + (BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) | BIT_VHTHT_MIMO_CTRL_FIELD(v)) + +#define BIT_CSI_INTERRUPT_STATUS BIT(0) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +/* 2 REG_CHNL_IDLE_TIME_V1 (Offset 0x24D4) */ + +#define BIT_SHIFT_CHNL_IDLE_TIME 0 +#define BIT_MASK_CHNL_IDLE_TIME 0xffffffffL +#define BIT_CHNL_IDLE_TIME(x) \ + (((x) & BIT_MASK_CHNL_IDLE_TIME) << BIT_SHIFT_CHNL_IDLE_TIME) +#define BITS_CHNL_IDLE_TIME \ + (BIT_MASK_CHNL_IDLE_TIME << BIT_SHIFT_CHNL_IDLE_TIME) +#define BIT_CLEAR_CHNL_IDLE_TIME(x) ((x) & (~BITS_CHNL_IDLE_TIME)) +#define BIT_GET_CHNL_IDLE_TIME(x) \ + (((x) >> BIT_SHIFT_CHNL_IDLE_TIME) & BIT_MASK_CHNL_IDLE_TIME) +#define BIT_SET_CHNL_IDLE_TIME(x, v) \ + (BIT_CLEAR_CHNL_IDLE_TIME(x) | BIT_CHNL_IDLE_TIME(v)) + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) + +/* 2 REG_SWPS_PKT_TH_V1 (Offset 0x24F6) */ + +#define BIT_SHIFT_SWPS_PKT_TH 0 +#define BIT_MASK_SWPS_PKT_TH 0xffff +#define BIT_SWPS_PKT_TH(x) \ + (((x) & BIT_MASK_SWPS_PKT_TH) << BIT_SHIFT_SWPS_PKT_TH) +#define BITS_SWPS_PKT_TH (BIT_MASK_SWPS_PKT_TH << BIT_SHIFT_SWPS_PKT_TH) +#define BIT_CLEAR_SWPS_PKT_TH(x) ((x) & (~BITS_SWPS_PKT_TH)) +#define BIT_GET_SWPS_PKT_TH(x) \ + (((x) >> BIT_SHIFT_SWPS_PKT_TH) & BIT_MASK_SWPS_PKT_TH) +#define BIT_SET_SWPS_PKT_TH(x, v) \ + (BIT_CLEAR_SWPS_PKT_TH(x) | BIT_SWPS_PKT_TH(v)) + +/* 2 REG_SWPS_TIME_TH_V1 (Offset 0x24F8) */ + +#define BIT_SHIFT_SWPS_PSTIME_TH 16 +#define BIT_MASK_SWPS_PSTIME_TH 0xffff +#define BIT_SWPS_PSTIME_TH(x) \ + (((x) & BIT_MASK_SWPS_PSTIME_TH) << BIT_SHIFT_SWPS_PSTIME_TH) +#define BITS_SWPS_PSTIME_TH \ + (BIT_MASK_SWPS_PSTIME_TH << BIT_SHIFT_SWPS_PSTIME_TH) +#define BIT_CLEAR_SWPS_PSTIME_TH(x) ((x) & (~BITS_SWPS_PSTIME_TH)) +#define BIT_GET_SWPS_PSTIME_TH(x) \ + (((x) >> BIT_SHIFT_SWPS_PSTIME_TH) & BIT_MASK_SWPS_PSTIME_TH) +#define BIT_SET_SWPS_PSTIME_TH(x, v) \ + (BIT_CLEAR_SWPS_PSTIME_TH(x) | BIT_SWPS_PSTIME_TH(v)) + +#define BIT_SHIFT_SWPS_TIME_TH 0 +#define BIT_MASK_SWPS_TIME_TH 0xffff +#define BIT_SWPS_TIME_TH(x) \ + (((x) & BIT_MASK_SWPS_TIME_TH) << BIT_SHIFT_SWPS_TIME_TH) +#define BITS_SWPS_TIME_TH (BIT_MASK_SWPS_TIME_TH << BIT_SHIFT_SWPS_TIME_TH) +#define BIT_CLEAR_SWPS_TIME_TH(x) ((x) & (~BITS_SWPS_TIME_TH)) +#define BIT_GET_SWPS_TIME_TH(x) \ + (((x) >> BIT_SHIFT_SWPS_TIME_TH) & BIT_MASK_SWPS_TIME_TH) +#define BIT_SET_SWPS_TIME_TH(x, v) \ + (BIT_CLEAR_SWPS_TIME_TH(x) | BIT_SWPS_TIME_TH(v)) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/* 2 REG_TXPAGE_INT_CTRL_0 (Offset 0x3200) */ + +#define BIT_CH0_INT_EN BIT(31) + +#define BIT_SHIFT_CH0_HIGH_TH 16 +#define BIT_MASK_CH0_HIGH_TH 0xfff +#define BIT_CH0_HIGH_TH(x) \ + (((x) & BIT_MASK_CH0_HIGH_TH) << BIT_SHIFT_CH0_HIGH_TH) +#define BITS_CH0_HIGH_TH (BIT_MASK_CH0_HIGH_TH << BIT_SHIFT_CH0_HIGH_TH) +#define BIT_CLEAR_CH0_HIGH_TH(x) ((x) & (~BITS_CH0_HIGH_TH)) +#define BIT_GET_CH0_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH0_HIGH_TH) & BIT_MASK_CH0_HIGH_TH) +#define BIT_SET_CH0_HIGH_TH(x, v) \ + (BIT_CLEAR_CH0_HIGH_TH(x) | BIT_CH0_HIGH_TH(v)) + +#define BIT_SHIFT_CH0_LOW_TH 0 +#define BIT_MASK_CH0_LOW_TH 0xfff +#define BIT_CH0_LOW_TH(x) (((x) & BIT_MASK_CH0_LOW_TH) << BIT_SHIFT_CH0_LOW_TH) +#define BITS_CH0_LOW_TH (BIT_MASK_CH0_LOW_TH << BIT_SHIFT_CH0_LOW_TH) +#define BIT_CLEAR_CH0_LOW_TH(x) ((x) & (~BITS_CH0_LOW_TH)) +#define BIT_GET_CH0_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH0_LOW_TH) & BIT_MASK_CH0_LOW_TH) +#define BIT_SET_CH0_LOW_TH(x, v) (BIT_CLEAR_CH0_LOW_TH(x) | BIT_CH0_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_1 (Offset 0x3204) */ + +#define BIT_CH1_INT_EN BIT(31) + +#define BIT_SHIFT_CH1_HIGH_TH 16 +#define BIT_MASK_CH1_HIGH_TH 0xfff +#define BIT_CH1_HIGH_TH(x) \ + (((x) & BIT_MASK_CH1_HIGH_TH) << BIT_SHIFT_CH1_HIGH_TH) +#define BITS_CH1_HIGH_TH (BIT_MASK_CH1_HIGH_TH << BIT_SHIFT_CH1_HIGH_TH) +#define BIT_CLEAR_CH1_HIGH_TH(x) ((x) & (~BITS_CH1_HIGH_TH)) +#define BIT_GET_CH1_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH1_HIGH_TH) & BIT_MASK_CH1_HIGH_TH) +#define BIT_SET_CH1_HIGH_TH(x, v) \ + (BIT_CLEAR_CH1_HIGH_TH(x) | BIT_CH1_HIGH_TH(v)) + +#define BIT_SHIFT_CH1_LOW_TH 0 +#define BIT_MASK_CH1_LOW_TH 0xfff +#define BIT_CH1_LOW_TH(x) (((x) & BIT_MASK_CH1_LOW_TH) << BIT_SHIFT_CH1_LOW_TH) +#define BITS_CH1_LOW_TH (BIT_MASK_CH1_LOW_TH << BIT_SHIFT_CH1_LOW_TH) +#define BIT_CLEAR_CH1_LOW_TH(x) ((x) & (~BITS_CH1_LOW_TH)) +#define BIT_GET_CH1_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH1_LOW_TH) & BIT_MASK_CH1_LOW_TH) +#define BIT_SET_CH1_LOW_TH(x, v) (BIT_CLEAR_CH1_LOW_TH(x) | BIT_CH1_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_2 (Offset 0x3208) */ + +#define BIT_CH2_INT_EN BIT(31) + +#define BIT_SHIFT_CH2_HIGH_TH 16 +#define BIT_MASK_CH2_HIGH_TH 0xfff +#define BIT_CH2_HIGH_TH(x) \ + (((x) & BIT_MASK_CH2_HIGH_TH) << BIT_SHIFT_CH2_HIGH_TH) +#define BITS_CH2_HIGH_TH (BIT_MASK_CH2_HIGH_TH << BIT_SHIFT_CH2_HIGH_TH) +#define BIT_CLEAR_CH2_HIGH_TH(x) ((x) & (~BITS_CH2_HIGH_TH)) +#define BIT_GET_CH2_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH2_HIGH_TH) & BIT_MASK_CH2_HIGH_TH) +#define BIT_SET_CH2_HIGH_TH(x, v) \ + (BIT_CLEAR_CH2_HIGH_TH(x) | BIT_CH2_HIGH_TH(v)) + +#define BIT_SHIFT_CH2_LOW_TH 0 +#define BIT_MASK_CH2_LOW_TH 0xfff +#define BIT_CH2_LOW_TH(x) (((x) & BIT_MASK_CH2_LOW_TH) << BIT_SHIFT_CH2_LOW_TH) +#define BITS_CH2_LOW_TH (BIT_MASK_CH2_LOW_TH << BIT_SHIFT_CH2_LOW_TH) +#define BIT_CLEAR_CH2_LOW_TH(x) ((x) & (~BITS_CH2_LOW_TH)) +#define BIT_GET_CH2_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH2_LOW_TH) & BIT_MASK_CH2_LOW_TH) +#define BIT_SET_CH2_LOW_TH(x, v) (BIT_CLEAR_CH2_LOW_TH(x) | BIT_CH2_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_3 (Offset 0x320C) */ + +#define BIT_CH3_INT_EN BIT(31) + +#define BIT_SHIFT_CH3_HIGH_TH 16 +#define BIT_MASK_CH3_HIGH_TH 0xfff +#define BIT_CH3_HIGH_TH(x) \ + (((x) & BIT_MASK_CH3_HIGH_TH) << BIT_SHIFT_CH3_HIGH_TH) +#define BITS_CH3_HIGH_TH (BIT_MASK_CH3_HIGH_TH << BIT_SHIFT_CH3_HIGH_TH) +#define BIT_CLEAR_CH3_HIGH_TH(x) ((x) & (~BITS_CH3_HIGH_TH)) +#define BIT_GET_CH3_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH3_HIGH_TH) & BIT_MASK_CH3_HIGH_TH) +#define BIT_SET_CH3_HIGH_TH(x, v) \ + (BIT_CLEAR_CH3_HIGH_TH(x) | BIT_CH3_HIGH_TH(v)) + +#define BIT_SHIFT_CH3_LOW_TH 0 +#define BIT_MASK_CH3_LOW_TH 0xfff +#define BIT_CH3_LOW_TH(x) (((x) & BIT_MASK_CH3_LOW_TH) << BIT_SHIFT_CH3_LOW_TH) +#define BITS_CH3_LOW_TH (BIT_MASK_CH3_LOW_TH << BIT_SHIFT_CH3_LOW_TH) +#define BIT_CLEAR_CH3_LOW_TH(x) ((x) & (~BITS_CH3_LOW_TH)) +#define BIT_GET_CH3_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH3_LOW_TH) & BIT_MASK_CH3_LOW_TH) +#define BIT_SET_CH3_LOW_TH(x, v) (BIT_CLEAR_CH3_LOW_TH(x) | BIT_CH3_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_4 (Offset 0x3210) */ + +#define BIT_CH4_INT_EN BIT(31) + +#define BIT_SHIFT_CH4_HIGH_TH 16 +#define BIT_MASK_CH4_HIGH_TH 0xfff +#define BIT_CH4_HIGH_TH(x) \ + (((x) & BIT_MASK_CH4_HIGH_TH) << BIT_SHIFT_CH4_HIGH_TH) +#define BITS_CH4_HIGH_TH (BIT_MASK_CH4_HIGH_TH << BIT_SHIFT_CH4_HIGH_TH) +#define BIT_CLEAR_CH4_HIGH_TH(x) ((x) & (~BITS_CH4_HIGH_TH)) +#define BIT_GET_CH4_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH4_HIGH_TH) & BIT_MASK_CH4_HIGH_TH) +#define BIT_SET_CH4_HIGH_TH(x, v) \ + (BIT_CLEAR_CH4_HIGH_TH(x) | BIT_CH4_HIGH_TH(v)) + +#define BIT_SHIFT_CH4_LOW_TH 0 +#define BIT_MASK_CH4_LOW_TH 0xfff +#define BIT_CH4_LOW_TH(x) (((x) & BIT_MASK_CH4_LOW_TH) << BIT_SHIFT_CH4_LOW_TH) +#define BITS_CH4_LOW_TH (BIT_MASK_CH4_LOW_TH << BIT_SHIFT_CH4_LOW_TH) +#define BIT_CLEAR_CH4_LOW_TH(x) ((x) & (~BITS_CH4_LOW_TH)) +#define BIT_GET_CH4_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH4_LOW_TH) & BIT_MASK_CH4_LOW_TH) +#define BIT_SET_CH4_LOW_TH(x, v) (BIT_CLEAR_CH4_LOW_TH(x) | BIT_CH4_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_5 (Offset 0x3214) */ + +#define BIT_CH5_INT_EN BIT(31) + +#define BIT_SHIFT_CH5_HIGH_TH 16 +#define BIT_MASK_CH5_HIGH_TH 0xfff +#define BIT_CH5_HIGH_TH(x) \ + (((x) & BIT_MASK_CH5_HIGH_TH) << BIT_SHIFT_CH5_HIGH_TH) +#define BITS_CH5_HIGH_TH (BIT_MASK_CH5_HIGH_TH << BIT_SHIFT_CH5_HIGH_TH) +#define BIT_CLEAR_CH5_HIGH_TH(x) ((x) & (~BITS_CH5_HIGH_TH)) +#define BIT_GET_CH5_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH5_HIGH_TH) & BIT_MASK_CH5_HIGH_TH) +#define BIT_SET_CH5_HIGH_TH(x, v) \ + (BIT_CLEAR_CH5_HIGH_TH(x) | BIT_CH5_HIGH_TH(v)) + +#define BIT_SHIFT_CH5_LOW_TH 0 +#define BIT_MASK_CH5_LOW_TH 0xfff +#define BIT_CH5_LOW_TH(x) (((x) & BIT_MASK_CH5_LOW_TH) << BIT_SHIFT_CH5_LOW_TH) +#define BITS_CH5_LOW_TH (BIT_MASK_CH5_LOW_TH << BIT_SHIFT_CH5_LOW_TH) +#define BIT_CLEAR_CH5_LOW_TH(x) ((x) & (~BITS_CH5_LOW_TH)) +#define BIT_GET_CH5_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH5_LOW_TH) & BIT_MASK_CH5_LOW_TH) +#define BIT_SET_CH5_LOW_TH(x, v) (BIT_CLEAR_CH5_LOW_TH(x) | BIT_CH5_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_6 (Offset 0x3218) */ + +#define BIT_CH6_INT_EN BIT(31) + +#define BIT_SHIFT_CH6_HIGH_TH 16 +#define BIT_MASK_CH6_HIGH_TH 0xfff +#define BIT_CH6_HIGH_TH(x) \ + (((x) & BIT_MASK_CH6_HIGH_TH) << BIT_SHIFT_CH6_HIGH_TH) +#define BITS_CH6_HIGH_TH (BIT_MASK_CH6_HIGH_TH << BIT_SHIFT_CH6_HIGH_TH) +#define BIT_CLEAR_CH6_HIGH_TH(x) ((x) & (~BITS_CH6_HIGH_TH)) +#define BIT_GET_CH6_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH6_HIGH_TH) & BIT_MASK_CH6_HIGH_TH) +#define BIT_SET_CH6_HIGH_TH(x, v) \ + (BIT_CLEAR_CH6_HIGH_TH(x) | BIT_CH6_HIGH_TH(v)) + +#define BIT_SHIFT_CH6_LOW_TH 0 +#define BIT_MASK_CH6_LOW_TH 0xfff +#define BIT_CH6_LOW_TH(x) (((x) & BIT_MASK_CH6_LOW_TH) << BIT_SHIFT_CH6_LOW_TH) +#define BITS_CH6_LOW_TH (BIT_MASK_CH6_LOW_TH << BIT_SHIFT_CH6_LOW_TH) +#define BIT_CLEAR_CH6_LOW_TH(x) ((x) & (~BITS_CH6_LOW_TH)) +#define BIT_GET_CH6_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH6_LOW_TH) & BIT_MASK_CH6_LOW_TH) +#define BIT_SET_CH6_LOW_TH(x, v) (BIT_CLEAR_CH6_LOW_TH(x) | BIT_CH6_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_7 (Offset 0x321C) */ + +#define BIT_CH7_INT_EN BIT(31) + +#define BIT_SHIFT_CH7_HIGH_TH 16 +#define BIT_MASK_CH7_HIGH_TH 0xfff +#define BIT_CH7_HIGH_TH(x) \ + (((x) & BIT_MASK_CH7_HIGH_TH) << BIT_SHIFT_CH7_HIGH_TH) +#define BITS_CH7_HIGH_TH (BIT_MASK_CH7_HIGH_TH << BIT_SHIFT_CH7_HIGH_TH) +#define BIT_CLEAR_CH7_HIGH_TH(x) ((x) & (~BITS_CH7_HIGH_TH)) +#define BIT_GET_CH7_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH7_HIGH_TH) & BIT_MASK_CH7_HIGH_TH) +#define BIT_SET_CH7_HIGH_TH(x, v) \ + (BIT_CLEAR_CH7_HIGH_TH(x) | BIT_CH7_HIGH_TH(v)) + +#define BIT_SHIFT_CH7_LOW_TH 0 +#define BIT_MASK_CH7_LOW_TH 0xfff +#define BIT_CH7_LOW_TH(x) (((x) & BIT_MASK_CH7_LOW_TH) << BIT_SHIFT_CH7_LOW_TH) +#define BITS_CH7_LOW_TH (BIT_MASK_CH7_LOW_TH << BIT_SHIFT_CH7_LOW_TH) +#define BIT_CLEAR_CH7_LOW_TH(x) ((x) & (~BITS_CH7_LOW_TH)) +#define BIT_GET_CH7_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH7_LOW_TH) & BIT_MASK_CH7_LOW_TH) +#define BIT_SET_CH7_LOW_TH(x, v) (BIT_CLEAR_CH7_LOW_TH(x) | BIT_CH7_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_8 (Offset 0x3220) */ + +#define BIT_CH8_INT_EN BIT(31) + +#define BIT_SHIFT_CH8_HIGH_TH 16 +#define BIT_MASK_CH8_HIGH_TH 0xfff +#define BIT_CH8_HIGH_TH(x) \ + (((x) & BIT_MASK_CH8_HIGH_TH) << BIT_SHIFT_CH8_HIGH_TH) +#define BITS_CH8_HIGH_TH (BIT_MASK_CH8_HIGH_TH << BIT_SHIFT_CH8_HIGH_TH) +#define BIT_CLEAR_CH8_HIGH_TH(x) ((x) & (~BITS_CH8_HIGH_TH)) +#define BIT_GET_CH8_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH8_HIGH_TH) & BIT_MASK_CH8_HIGH_TH) +#define BIT_SET_CH8_HIGH_TH(x, v) \ + (BIT_CLEAR_CH8_HIGH_TH(x) | BIT_CH8_HIGH_TH(v)) + +#define BIT_SHIFT_CH8_LOW_TH 0 +#define BIT_MASK_CH8_LOW_TH 0xfff +#define BIT_CH8_LOW_TH(x) (((x) & BIT_MASK_CH8_LOW_TH) << BIT_SHIFT_CH8_LOW_TH) +#define BITS_CH8_LOW_TH (BIT_MASK_CH8_LOW_TH << BIT_SHIFT_CH8_LOW_TH) +#define BIT_CLEAR_CH8_LOW_TH(x) ((x) & (~BITS_CH8_LOW_TH)) +#define BIT_GET_CH8_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH8_LOW_TH) & BIT_MASK_CH8_LOW_TH) +#define BIT_SET_CH8_LOW_TH(x, v) (BIT_CLEAR_CH8_LOW_TH(x) | BIT_CH8_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_9 (Offset 0x3224) */ + +#define BIT_CH9_INT_EN BIT(31) + +#define BIT_SHIFT_CH9_HIGH_TH 16 +#define BIT_MASK_CH9_HIGH_TH 0xfff +#define BIT_CH9_HIGH_TH(x) \ + (((x) & BIT_MASK_CH9_HIGH_TH) << BIT_SHIFT_CH9_HIGH_TH) +#define BITS_CH9_HIGH_TH (BIT_MASK_CH9_HIGH_TH << BIT_SHIFT_CH9_HIGH_TH) +#define BIT_CLEAR_CH9_HIGH_TH(x) ((x) & (~BITS_CH9_HIGH_TH)) +#define BIT_GET_CH9_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH9_HIGH_TH) & BIT_MASK_CH9_HIGH_TH) +#define BIT_SET_CH9_HIGH_TH(x, v) \ + (BIT_CLEAR_CH9_HIGH_TH(x) | BIT_CH9_HIGH_TH(v)) + +#define BIT_SHIFT_CH9_LOW_TH 0 +#define BIT_MASK_CH9_LOW_TH 0xfff +#define BIT_CH9_LOW_TH(x) (((x) & BIT_MASK_CH9_LOW_TH) << BIT_SHIFT_CH9_LOW_TH) +#define BITS_CH9_LOW_TH (BIT_MASK_CH9_LOW_TH << BIT_SHIFT_CH9_LOW_TH) +#define BIT_CLEAR_CH9_LOW_TH(x) ((x) & (~BITS_CH9_LOW_TH)) +#define BIT_GET_CH9_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH9_LOW_TH) & BIT_MASK_CH9_LOW_TH) +#define BIT_SET_CH9_LOW_TH(x, v) (BIT_CLEAR_CH9_LOW_TH(x) | BIT_CH9_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_10 (Offset 0x3228) */ + +#define BIT_CH10_INT_EN BIT(31) + +#define BIT_SHIFT_CH10_HIGH_TH 16 +#define BIT_MASK_CH10_HIGH_TH 0xfff +#define BIT_CH10_HIGH_TH(x) \ + (((x) & BIT_MASK_CH10_HIGH_TH) << BIT_SHIFT_CH10_HIGH_TH) +#define BITS_CH10_HIGH_TH (BIT_MASK_CH10_HIGH_TH << BIT_SHIFT_CH10_HIGH_TH) +#define BIT_CLEAR_CH10_HIGH_TH(x) ((x) & (~BITS_CH10_HIGH_TH)) +#define BIT_GET_CH10_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH10_HIGH_TH) & BIT_MASK_CH10_HIGH_TH) +#define BIT_SET_CH10_HIGH_TH(x, v) \ + (BIT_CLEAR_CH10_HIGH_TH(x) | BIT_CH10_HIGH_TH(v)) + +#define BIT_SHIFT_CH10_LOW_TH 0 +#define BIT_MASK_CH10_LOW_TH 0xfff +#define BIT_CH10_LOW_TH(x) \ + (((x) & BIT_MASK_CH10_LOW_TH) << BIT_SHIFT_CH10_LOW_TH) +#define BITS_CH10_LOW_TH (BIT_MASK_CH10_LOW_TH << BIT_SHIFT_CH10_LOW_TH) +#define BIT_CLEAR_CH10_LOW_TH(x) ((x) & (~BITS_CH10_LOW_TH)) +#define BIT_GET_CH10_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH10_LOW_TH) & BIT_MASK_CH10_LOW_TH) +#define BIT_SET_CH10_LOW_TH(x, v) \ + (BIT_CLEAR_CH10_LOW_TH(x) | BIT_CH10_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_11 (Offset 0x322C) */ + +#define BIT_CH11_INT_EN BIT(31) + +#define BIT_SHIFT_CH11_HIGH_TH 16 +#define BIT_MASK_CH11_HIGH_TH 0xfff +#define BIT_CH11_HIGH_TH(x) \ + (((x) & BIT_MASK_CH11_HIGH_TH) << BIT_SHIFT_CH11_HIGH_TH) +#define BITS_CH11_HIGH_TH (BIT_MASK_CH11_HIGH_TH << BIT_SHIFT_CH11_HIGH_TH) +#define BIT_CLEAR_CH11_HIGH_TH(x) ((x) & (~BITS_CH11_HIGH_TH)) +#define BIT_GET_CH11_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH11_HIGH_TH) & BIT_MASK_CH11_HIGH_TH) +#define BIT_SET_CH11_HIGH_TH(x, v) \ + (BIT_CLEAR_CH11_HIGH_TH(x) | BIT_CH11_HIGH_TH(v)) + +#define BIT_SHIFT_CH11_LOW_TH 0 +#define BIT_MASK_CH11_LOW_TH 0xfff +#define BIT_CH11_LOW_TH(x) \ + (((x) & BIT_MASK_CH11_LOW_TH) << BIT_SHIFT_CH11_LOW_TH) +#define BITS_CH11_LOW_TH (BIT_MASK_CH11_LOW_TH << BIT_SHIFT_CH11_LOW_TH) +#define BIT_CLEAR_CH11_LOW_TH(x) ((x) & (~BITS_CH11_LOW_TH)) +#define BIT_GET_CH11_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH11_LOW_TH) & BIT_MASK_CH11_LOW_TH) +#define BIT_SET_CH11_LOW_TH(x, v) \ + (BIT_CLEAR_CH11_LOW_TH(x) | BIT_CH11_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_12 (Offset 0x3230) */ + +#define BIT_CH12_INT_EN BIT(31) + +#define BIT_SHIFT_CH12_HIGH_TH 16 +#define BIT_MASK_CH12_HIGH_TH 0xfff +#define BIT_CH12_HIGH_TH(x) \ + (((x) & BIT_MASK_CH12_HIGH_TH) << BIT_SHIFT_CH12_HIGH_TH) +#define BITS_CH12_HIGH_TH (BIT_MASK_CH12_HIGH_TH << BIT_SHIFT_CH12_HIGH_TH) +#define BIT_CLEAR_CH12_HIGH_TH(x) ((x) & (~BITS_CH12_HIGH_TH)) +#define BIT_GET_CH12_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH12_HIGH_TH) & BIT_MASK_CH12_HIGH_TH) +#define BIT_SET_CH12_HIGH_TH(x, v) \ + (BIT_CLEAR_CH12_HIGH_TH(x) | BIT_CH12_HIGH_TH(v)) + +#define BIT_SHIFT_CH12_LOW_TH 0 +#define BIT_MASK_CH12_LOW_TH 0xfff +#define BIT_CH12_LOW_TH(x) \ + (((x) & BIT_MASK_CH12_LOW_TH) << BIT_SHIFT_CH12_LOW_TH) +#define BITS_CH12_LOW_TH (BIT_MASK_CH12_LOW_TH << BIT_SHIFT_CH12_LOW_TH) +#define BIT_CLEAR_CH12_LOW_TH(x) ((x) & (~BITS_CH12_LOW_TH)) +#define BIT_GET_CH12_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH12_LOW_TH) & BIT_MASK_CH12_LOW_TH) +#define BIT_SET_CH12_LOW_TH(x, v) \ + (BIT_CLEAR_CH12_LOW_TH(x) | BIT_CH12_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_13 (Offset 0x3234) */ + +#define BIT_CH13_INT_EN BIT(31) + +#define BIT_SHIFT_CH13_HIGH_TH 16 +#define BIT_MASK_CH13_HIGH_TH 0xfff +#define BIT_CH13_HIGH_TH(x) \ + (((x) & BIT_MASK_CH13_HIGH_TH) << BIT_SHIFT_CH13_HIGH_TH) +#define BITS_CH13_HIGH_TH (BIT_MASK_CH13_HIGH_TH << BIT_SHIFT_CH13_HIGH_TH) +#define BIT_CLEAR_CH13_HIGH_TH(x) ((x) & (~BITS_CH13_HIGH_TH)) +#define BIT_GET_CH13_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH13_HIGH_TH) & BIT_MASK_CH13_HIGH_TH) +#define BIT_SET_CH13_HIGH_TH(x, v) \ + (BIT_CLEAR_CH13_HIGH_TH(x) | BIT_CH13_HIGH_TH(v)) + +#define BIT_SHIFT_CH13_LOW_TH 0 +#define BIT_MASK_CH13_LOW_TH 0xfff +#define BIT_CH13_LOW_TH(x) \ + (((x) & BIT_MASK_CH13_LOW_TH) << BIT_SHIFT_CH13_LOW_TH) +#define BITS_CH13_LOW_TH (BIT_MASK_CH13_LOW_TH << BIT_SHIFT_CH13_LOW_TH) +#define BIT_CLEAR_CH13_LOW_TH(x) ((x) & (~BITS_CH13_LOW_TH)) +#define BIT_GET_CH13_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH13_LOW_TH) & BIT_MASK_CH13_LOW_TH) +#define BIT_SET_CH13_LOW_TH(x, v) \ + (BIT_CLEAR_CH13_LOW_TH(x) | BIT_CH13_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_14 (Offset 0x3238) */ + +#define BIT_CH14_INT_EN BIT(31) + +#define BIT_SHIFT_CH14_HIGH_TH 16 +#define BIT_MASK_CH14_HIGH_TH 0xfff +#define BIT_CH14_HIGH_TH(x) \ + (((x) & BIT_MASK_CH14_HIGH_TH) << BIT_SHIFT_CH14_HIGH_TH) +#define BITS_CH14_HIGH_TH (BIT_MASK_CH14_HIGH_TH << BIT_SHIFT_CH14_HIGH_TH) +#define BIT_CLEAR_CH14_HIGH_TH(x) ((x) & (~BITS_CH14_HIGH_TH)) +#define BIT_GET_CH14_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH14_HIGH_TH) & BIT_MASK_CH14_HIGH_TH) +#define BIT_SET_CH14_HIGH_TH(x, v) \ + (BIT_CLEAR_CH14_HIGH_TH(x) | BIT_CH14_HIGH_TH(v)) + +#define BIT_SHIFT_CH14_LOW_TH 0 +#define BIT_MASK_CH14_LOW_TH 0xfff +#define BIT_CH14_LOW_TH(x) \ + (((x) & BIT_MASK_CH14_LOW_TH) << BIT_SHIFT_CH14_LOW_TH) +#define BITS_CH14_LOW_TH (BIT_MASK_CH14_LOW_TH << BIT_SHIFT_CH14_LOW_TH) +#define BIT_CLEAR_CH14_LOW_TH(x) ((x) & (~BITS_CH14_LOW_TH)) +#define BIT_GET_CH14_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH14_LOW_TH) & BIT_MASK_CH14_LOW_TH) +#define BIT_SET_CH14_LOW_TH(x, v) \ + (BIT_CLEAR_CH14_LOW_TH(x) | BIT_CH14_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_15 (Offset 0x323C) */ + +#define BIT_CH15_INT_EN BIT(31) + +#define BIT_SHIFT_CH15_HIGH_TH 16 +#define BIT_MASK_CH15_HIGH_TH 0xfff +#define BIT_CH15_HIGH_TH(x) \ + (((x) & BIT_MASK_CH15_HIGH_TH) << BIT_SHIFT_CH15_HIGH_TH) +#define BITS_CH15_HIGH_TH (BIT_MASK_CH15_HIGH_TH << BIT_SHIFT_CH15_HIGH_TH) +#define BIT_CLEAR_CH15_HIGH_TH(x) ((x) & (~BITS_CH15_HIGH_TH)) +#define BIT_GET_CH15_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH15_HIGH_TH) & BIT_MASK_CH15_HIGH_TH) +#define BIT_SET_CH15_HIGH_TH(x, v) \ + (BIT_CLEAR_CH15_HIGH_TH(x) | BIT_CH15_HIGH_TH(v)) + +#define BIT_SHIFT_CH15_LOW_TH 0 +#define BIT_MASK_CH15_LOW_TH 0xfff +#define BIT_CH15_LOW_TH(x) \ + (((x) & BIT_MASK_CH15_LOW_TH) << BIT_SHIFT_CH15_LOW_TH) +#define BITS_CH15_LOW_TH (BIT_MASK_CH15_LOW_TH << BIT_SHIFT_CH15_LOW_TH) +#define BIT_CLEAR_CH15_LOW_TH(x) ((x) & (~BITS_CH15_LOW_TH)) +#define BIT_GET_CH15_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH15_LOW_TH) & BIT_MASK_CH15_LOW_TH) +#define BIT_SET_CH15_LOW_TH(x, v) \ + (BIT_CLEAR_CH15_LOW_TH(x) | BIT_CH15_LOW_TH(v)) + +/* 2 REG_TXPAGE_INT_CTRL_16 (Offset 0x3240) */ + +#define BIT_CH16_INT_EN BIT(31) + +#define BIT_SHIFT_CH16_HIGH_TH 16 +#define BIT_MASK_CH16_HIGH_TH 0xfff +#define BIT_CH16_HIGH_TH(x) \ + (((x) & BIT_MASK_CH16_HIGH_TH) << BIT_SHIFT_CH16_HIGH_TH) +#define BITS_CH16_HIGH_TH (BIT_MASK_CH16_HIGH_TH << BIT_SHIFT_CH16_HIGH_TH) +#define BIT_CLEAR_CH16_HIGH_TH(x) ((x) & (~BITS_CH16_HIGH_TH)) +#define BIT_GET_CH16_HIGH_TH(x) \ + (((x) >> BIT_SHIFT_CH16_HIGH_TH) & BIT_MASK_CH16_HIGH_TH) +#define BIT_SET_CH16_HIGH_TH(x, v) \ + (BIT_CLEAR_CH16_HIGH_TH(x) | BIT_CH16_HIGH_TH(v)) + +#define BIT_SHIFT_CH16_LOW_TH 0 +#define BIT_MASK_CH16_LOW_TH 0xfff +#define BIT_CH16_LOW_TH(x) \ + (((x) & BIT_MASK_CH16_LOW_TH) << BIT_SHIFT_CH16_LOW_TH) +#define BITS_CH16_LOW_TH (BIT_MASK_CH16_LOW_TH << BIT_SHIFT_CH16_LOW_TH) +#define BIT_CLEAR_CH16_LOW_TH(x) ((x) & (~BITS_CH16_LOW_TH)) +#define BIT_GET_CH16_LOW_TH(x) \ + (((x) >> BIT_SHIFT_CH16_LOW_TH) & BIT_MASK_CH16_LOW_TH) +#define BIT_SET_CH16_LOW_TH(x, v) \ + (BIT_CLEAR_CH16_LOW_TH(x) | BIT_CH16_LOW_TH(v)) + +/* 2 REG_ACH4_TXBD_IDX (Offset 0x3340) */ + +#define BIT_SHIFT_ACH4_HW_IDX 16 +#define BIT_MASK_ACH4_HW_IDX 0xfff +#define BIT_ACH4_HW_IDX(x) \ + (((x) & BIT_MASK_ACH4_HW_IDX) << BIT_SHIFT_ACH4_HW_IDX) +#define BITS_ACH4_HW_IDX (BIT_MASK_ACH4_HW_IDX << BIT_SHIFT_ACH4_HW_IDX) +#define BIT_CLEAR_ACH4_HW_IDX(x) ((x) & (~BITS_ACH4_HW_IDX)) +#define BIT_GET_ACH4_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH4_HW_IDX) & BIT_MASK_ACH4_HW_IDX) +#define BIT_SET_ACH4_HW_IDX(x, v) \ + (BIT_CLEAR_ACH4_HW_IDX(x) | BIT_ACH4_HW_IDX(v)) + +#define BIT_SHIFT_ACH4_HOST_IDX 0 +#define BIT_MASK_ACH4_HOST_IDX 0xfff +#define BIT_ACH4_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH4_HOST_IDX) << BIT_SHIFT_ACH4_HOST_IDX) +#define BITS_ACH4_HOST_IDX (BIT_MASK_ACH4_HOST_IDX << BIT_SHIFT_ACH4_HOST_IDX) +#define BIT_CLEAR_ACH4_HOST_IDX(x) ((x) & (~BITS_ACH4_HOST_IDX)) +#define BIT_GET_ACH4_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH4_HOST_IDX) & BIT_MASK_ACH4_HOST_IDX) +#define BIT_SET_ACH4_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH4_HOST_IDX(x) | BIT_ACH4_HOST_IDX(v)) + +/* 2 REG_ACH5_TXBD_IDX (Offset 0x3344) */ + +#define BIT_SHIFT_ACH5_HW_IDX 16 +#define BIT_MASK_ACH5_HW_IDX 0xfff +#define BIT_ACH5_HW_IDX(x) \ + (((x) & BIT_MASK_ACH5_HW_IDX) << BIT_SHIFT_ACH5_HW_IDX) +#define BITS_ACH5_HW_IDX (BIT_MASK_ACH5_HW_IDX << BIT_SHIFT_ACH5_HW_IDX) +#define BIT_CLEAR_ACH5_HW_IDX(x) ((x) & (~BITS_ACH5_HW_IDX)) +#define BIT_GET_ACH5_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH5_HW_IDX) & BIT_MASK_ACH5_HW_IDX) +#define BIT_SET_ACH5_HW_IDX(x, v) \ + (BIT_CLEAR_ACH5_HW_IDX(x) | BIT_ACH5_HW_IDX(v)) + +#define BIT_SHIFT_ACH5_HOST_IDX 0 +#define BIT_MASK_ACH5_HOST_IDX 0xfff +#define BIT_ACH5_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH5_HOST_IDX) << BIT_SHIFT_ACH5_HOST_IDX) +#define BITS_ACH5_HOST_IDX (BIT_MASK_ACH5_HOST_IDX << BIT_SHIFT_ACH5_HOST_IDX) +#define BIT_CLEAR_ACH5_HOST_IDX(x) ((x) & (~BITS_ACH5_HOST_IDX)) +#define BIT_GET_ACH5_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH5_HOST_IDX) & BIT_MASK_ACH5_HOST_IDX) +#define BIT_SET_ACH5_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH5_HOST_IDX(x) | BIT_ACH5_HOST_IDX(v)) + +/* 2 REG_ACH6_TXBD_IDX (Offset 0x3348) */ + +#define BIT_SHIFT_ACH6_HW_IDX 16 +#define BIT_MASK_ACH6_HW_IDX 0xfff +#define BIT_ACH6_HW_IDX(x) \ + (((x) & BIT_MASK_ACH6_HW_IDX) << BIT_SHIFT_ACH6_HW_IDX) +#define BITS_ACH6_HW_IDX (BIT_MASK_ACH6_HW_IDX << BIT_SHIFT_ACH6_HW_IDX) +#define BIT_CLEAR_ACH6_HW_IDX(x) ((x) & (~BITS_ACH6_HW_IDX)) +#define BIT_GET_ACH6_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH6_HW_IDX) & BIT_MASK_ACH6_HW_IDX) +#define BIT_SET_ACH6_HW_IDX(x, v) \ + (BIT_CLEAR_ACH6_HW_IDX(x) | BIT_ACH6_HW_IDX(v)) + +#define BIT_SHIFT_ACH6_HOST_IDX 0 +#define BIT_MASK_ACH6_HOST_IDX 0xfff +#define BIT_ACH6_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH6_HOST_IDX) << BIT_SHIFT_ACH6_HOST_IDX) +#define BITS_ACH6_HOST_IDX (BIT_MASK_ACH6_HOST_IDX << BIT_SHIFT_ACH6_HOST_IDX) +#define BIT_CLEAR_ACH6_HOST_IDX(x) ((x) & (~BITS_ACH6_HOST_IDX)) +#define BIT_GET_ACH6_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH6_HOST_IDX) & BIT_MASK_ACH6_HOST_IDX) +#define BIT_SET_ACH6_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH6_HOST_IDX(x) | BIT_ACH6_HOST_IDX(v)) + +/* 2 REG_ACH7_TXBD_IDX (Offset 0x334C) */ + +#define BIT_SHIFT_ACH7_HW_IDX 16 +#define BIT_MASK_ACH7_HW_IDX 0xfff +#define BIT_ACH7_HW_IDX(x) \ + (((x) & BIT_MASK_ACH7_HW_IDX) << BIT_SHIFT_ACH7_HW_IDX) +#define BITS_ACH7_HW_IDX (BIT_MASK_ACH7_HW_IDX << BIT_SHIFT_ACH7_HW_IDX) +#define BIT_CLEAR_ACH7_HW_IDX(x) ((x) & (~BITS_ACH7_HW_IDX)) +#define BIT_GET_ACH7_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH7_HW_IDX) & BIT_MASK_ACH7_HW_IDX) +#define BIT_SET_ACH7_HW_IDX(x, v) \ + (BIT_CLEAR_ACH7_HW_IDX(x) | BIT_ACH7_HW_IDX(v)) + +#define BIT_SHIFT_ACH7_HOST_IDX 0 +#define BIT_MASK_ACH7_HOST_IDX 0xfff +#define BIT_ACH7_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH7_HOST_IDX) << BIT_SHIFT_ACH7_HOST_IDX) +#define BITS_ACH7_HOST_IDX (BIT_MASK_ACH7_HOST_IDX << BIT_SHIFT_ACH7_HOST_IDX) +#define BIT_CLEAR_ACH7_HOST_IDX(x) ((x) & (~BITS_ACH7_HOST_IDX)) +#define BIT_GET_ACH7_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH7_HOST_IDX) & BIT_MASK_ACH7_HOST_IDX) +#define BIT_SET_ACH7_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH7_HOST_IDX(x) | BIT_ACH7_HOST_IDX(v)) + +/* 2 REG_ACH8_TXBD_IDX (Offset 0x3350) */ + +#define BIT_SHIFT_ACH8_HW_IDX 16 +#define BIT_MASK_ACH8_HW_IDX 0xfff +#define BIT_ACH8_HW_IDX(x) \ + (((x) & BIT_MASK_ACH8_HW_IDX) << BIT_SHIFT_ACH8_HW_IDX) +#define BITS_ACH8_HW_IDX (BIT_MASK_ACH8_HW_IDX << BIT_SHIFT_ACH8_HW_IDX) +#define BIT_CLEAR_ACH8_HW_IDX(x) ((x) & (~BITS_ACH8_HW_IDX)) +#define BIT_GET_ACH8_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH8_HW_IDX) & BIT_MASK_ACH8_HW_IDX) +#define BIT_SET_ACH8_HW_IDX(x, v) \ + (BIT_CLEAR_ACH8_HW_IDX(x) | BIT_ACH8_HW_IDX(v)) + +#define BIT_SHIFT_ACH8_HOST_IDX 0 +#define BIT_MASK_ACH8_HOST_IDX 0xfff +#define BIT_ACH8_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH8_HOST_IDX) << BIT_SHIFT_ACH8_HOST_IDX) +#define BITS_ACH8_HOST_IDX (BIT_MASK_ACH8_HOST_IDX << BIT_SHIFT_ACH8_HOST_IDX) +#define BIT_CLEAR_ACH8_HOST_IDX(x) ((x) & (~BITS_ACH8_HOST_IDX)) +#define BIT_GET_ACH8_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH8_HOST_IDX) & BIT_MASK_ACH8_HOST_IDX) +#define BIT_SET_ACH8_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH8_HOST_IDX(x) | BIT_ACH8_HOST_IDX(v)) + +/* 2 REG_ACH9_TXBD_IDX (Offset 0x3354) */ + +#define BIT_SHIFT_ACH9_HW_IDX 16 +#define BIT_MASK_ACH9_HW_IDX 0xfff +#define BIT_ACH9_HW_IDX(x) \ + (((x) & BIT_MASK_ACH9_HW_IDX) << BIT_SHIFT_ACH9_HW_IDX) +#define BITS_ACH9_HW_IDX (BIT_MASK_ACH9_HW_IDX << BIT_SHIFT_ACH9_HW_IDX) +#define BIT_CLEAR_ACH9_HW_IDX(x) ((x) & (~BITS_ACH9_HW_IDX)) +#define BIT_GET_ACH9_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH9_HW_IDX) & BIT_MASK_ACH9_HW_IDX) +#define BIT_SET_ACH9_HW_IDX(x, v) \ + (BIT_CLEAR_ACH9_HW_IDX(x) | BIT_ACH9_HW_IDX(v)) + +#define BIT_SHIFT_ACH9_HOST_IDX 0 +#define BIT_MASK_ACH9_HOST_IDX 0xfff +#define BIT_ACH9_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH9_HOST_IDX) << BIT_SHIFT_ACH9_HOST_IDX) +#define BITS_ACH9_HOST_IDX (BIT_MASK_ACH9_HOST_IDX << BIT_SHIFT_ACH9_HOST_IDX) +#define BIT_CLEAR_ACH9_HOST_IDX(x) ((x) & (~BITS_ACH9_HOST_IDX)) +#define BIT_GET_ACH9_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH9_HOST_IDX) & BIT_MASK_ACH9_HOST_IDX) +#define BIT_SET_ACH9_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH9_HOST_IDX(x) | BIT_ACH9_HOST_IDX(v)) + +/* 2 REG_ACH10_TXBD_IDX (Offset 0x3358) */ + +#define BIT_SHIFT_ACH10_HW_IDX 16 +#define BIT_MASK_ACH10_HW_IDX 0xfff +#define BIT_ACH10_HW_IDX(x) \ + (((x) & BIT_MASK_ACH10_HW_IDX) << BIT_SHIFT_ACH10_HW_IDX) +#define BITS_ACH10_HW_IDX (BIT_MASK_ACH10_HW_IDX << BIT_SHIFT_ACH10_HW_IDX) +#define BIT_CLEAR_ACH10_HW_IDX(x) ((x) & (~BITS_ACH10_HW_IDX)) +#define BIT_GET_ACH10_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH10_HW_IDX) & BIT_MASK_ACH10_HW_IDX) +#define BIT_SET_ACH10_HW_IDX(x, v) \ + (BIT_CLEAR_ACH10_HW_IDX(x) | BIT_ACH10_HW_IDX(v)) + +#define BIT_SHIFT_ACH10_HOST_IDX 0 +#define BIT_MASK_ACH10_HOST_IDX 0xfff +#define BIT_ACH10_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH10_HOST_IDX) << BIT_SHIFT_ACH10_HOST_IDX) +#define BITS_ACH10_HOST_IDX \ + (BIT_MASK_ACH10_HOST_IDX << BIT_SHIFT_ACH10_HOST_IDX) +#define BIT_CLEAR_ACH10_HOST_IDX(x) ((x) & (~BITS_ACH10_HOST_IDX)) +#define BIT_GET_ACH10_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH10_HOST_IDX) & BIT_MASK_ACH10_HOST_IDX) +#define BIT_SET_ACH10_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH10_HOST_IDX(x) | BIT_ACH10_HOST_IDX(v)) + +/* 2 REG_ACH11_TXBD_IDX (Offset 0x335C) */ + +#define BIT_SHIFT_ACH11_HW_IDX 16 +#define BIT_MASK_ACH11_HW_IDX 0xfff +#define BIT_ACH11_HW_IDX(x) \ + (((x) & BIT_MASK_ACH11_HW_IDX) << BIT_SHIFT_ACH11_HW_IDX) +#define BITS_ACH11_HW_IDX (BIT_MASK_ACH11_HW_IDX << BIT_SHIFT_ACH11_HW_IDX) +#define BIT_CLEAR_ACH11_HW_IDX(x) ((x) & (~BITS_ACH11_HW_IDX)) +#define BIT_GET_ACH11_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH11_HW_IDX) & BIT_MASK_ACH11_HW_IDX) +#define BIT_SET_ACH11_HW_IDX(x, v) \ + (BIT_CLEAR_ACH11_HW_IDX(x) | BIT_ACH11_HW_IDX(v)) + +#define BIT_SHIFT_ACH11_HOST_IDX 0 +#define BIT_MASK_ACH11_HOST_IDX 0xfff +#define BIT_ACH11_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH11_HOST_IDX) << BIT_SHIFT_ACH11_HOST_IDX) +#define BITS_ACH11_HOST_IDX \ + (BIT_MASK_ACH11_HOST_IDX << BIT_SHIFT_ACH11_HOST_IDX) +#define BIT_CLEAR_ACH11_HOST_IDX(x) ((x) & (~BITS_ACH11_HOST_IDX)) +#define BIT_GET_ACH11_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH11_HOST_IDX) & BIT_MASK_ACH11_HOST_IDX) +#define BIT_SET_ACH11_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH11_HOST_IDX(x) | BIT_ACH11_HOST_IDX(v)) + +/* 2 REG_ACH12_TXBD_IDX (Offset 0x3360) */ + +#define BIT_SHIFT_ACH12_HW_IDX 16 +#define BIT_MASK_ACH12_HW_IDX 0xfff +#define BIT_ACH12_HW_IDX(x) \ + (((x) & BIT_MASK_ACH12_HW_IDX) << BIT_SHIFT_ACH12_HW_IDX) +#define BITS_ACH12_HW_IDX (BIT_MASK_ACH12_HW_IDX << BIT_SHIFT_ACH12_HW_IDX) +#define BIT_CLEAR_ACH12_HW_IDX(x) ((x) & (~BITS_ACH12_HW_IDX)) +#define BIT_GET_ACH12_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH12_HW_IDX) & BIT_MASK_ACH12_HW_IDX) +#define BIT_SET_ACH12_HW_IDX(x, v) \ + (BIT_CLEAR_ACH12_HW_IDX(x) | BIT_ACH12_HW_IDX(v)) + +#define BIT_SHIFT_ACH12_HOST_IDX 0 +#define BIT_MASK_ACH12_HOST_IDX 0xfff +#define BIT_ACH12_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH12_HOST_IDX) << BIT_SHIFT_ACH12_HOST_IDX) +#define BITS_ACH12_HOST_IDX \ + (BIT_MASK_ACH12_HOST_IDX << BIT_SHIFT_ACH12_HOST_IDX) +#define BIT_CLEAR_ACH12_HOST_IDX(x) ((x) & (~BITS_ACH12_HOST_IDX)) +#define BIT_GET_ACH12_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH12_HOST_IDX) & BIT_MASK_ACH12_HOST_IDX) +#define BIT_SET_ACH12_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH12_HOST_IDX(x) | BIT_ACH12_HOST_IDX(v)) + +/* 2 REG_ACH13_TXBD_IDX (Offset 0x3364) */ + +#define BIT_SHIFT_ACH13_HW_IDX 16 +#define BIT_MASK_ACH13_HW_IDX 0xfff +#define BIT_ACH13_HW_IDX(x) \ + (((x) & BIT_MASK_ACH13_HW_IDX) << BIT_SHIFT_ACH13_HW_IDX) +#define BITS_ACH13_HW_IDX (BIT_MASK_ACH13_HW_IDX << BIT_SHIFT_ACH13_HW_IDX) +#define BIT_CLEAR_ACH13_HW_IDX(x) ((x) & (~BITS_ACH13_HW_IDX)) +#define BIT_GET_ACH13_HW_IDX(x) \ + (((x) >> BIT_SHIFT_ACH13_HW_IDX) & BIT_MASK_ACH13_HW_IDX) +#define BIT_SET_ACH13_HW_IDX(x, v) \ + (BIT_CLEAR_ACH13_HW_IDX(x) | BIT_ACH13_HW_IDX(v)) + +#define BIT_SHIFT_ACH13_HOST_IDX 0 +#define BIT_MASK_ACH13_HOST_IDX 0xfff +#define BIT_ACH13_HOST_IDX(x) \ + (((x) & BIT_MASK_ACH13_HOST_IDX) << BIT_SHIFT_ACH13_HOST_IDX) +#define BITS_ACH13_HOST_IDX \ + (BIT_MASK_ACH13_HOST_IDX << BIT_SHIFT_ACH13_HOST_IDX) +#define BIT_CLEAR_ACH13_HOST_IDX(x) ((x) & (~BITS_ACH13_HOST_IDX)) +#define BIT_GET_ACH13_HOST_IDX(x) \ + (((x) >> BIT_SHIFT_ACH13_HOST_IDX) & BIT_MASK_ACH13_HOST_IDX) +#define BIT_SET_ACH13_HOST_IDX(x, v) \ + (BIT_CLEAR_ACH13_HOST_IDX(x) | BIT_ACH13_HOST_IDX(v)) + +/* 2 REG_AC_CHANNEL0_WEIGHT (Offset 0x3368) */ + +#define BIT_SHIFT_AC_CHANNEL0_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL0_WEIGHT 0xff +#define BIT_AC_CHANNEL0_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL0_WEIGHT) << BIT_SHIFT_AC_CHANNEL0_WEIGHT) +#define BITS_AC_CHANNEL0_WEIGHT \ + (BIT_MASK_AC_CHANNEL0_WEIGHT << BIT_SHIFT_AC_CHANNEL0_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL0_WEIGHT)) +#define BIT_GET_AC_CHANNEL0_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL0_WEIGHT) & BIT_MASK_AC_CHANNEL0_WEIGHT) +#define BIT_SET_AC_CHANNEL0_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) | BIT_AC_CHANNEL0_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL1_WEIGHT (Offset 0x3369) */ + +#define BIT_SHIFT_AC_CHANNEL1_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL1_WEIGHT 0xff +#define BIT_AC_CHANNEL1_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL1_WEIGHT) << BIT_SHIFT_AC_CHANNEL1_WEIGHT) +#define BITS_AC_CHANNEL1_WEIGHT \ + (BIT_MASK_AC_CHANNEL1_WEIGHT << BIT_SHIFT_AC_CHANNEL1_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL1_WEIGHT)) +#define BIT_GET_AC_CHANNEL1_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL1_WEIGHT) & BIT_MASK_AC_CHANNEL1_WEIGHT) +#define BIT_SET_AC_CHANNEL1_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) | BIT_AC_CHANNEL1_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL2_WEIGHT (Offset 0x336A) */ + +#define BIT_SHIFT_AC_CHANNEL2_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL2_WEIGHT 0xff +#define BIT_AC_CHANNEL2_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL2_WEIGHT) << BIT_SHIFT_AC_CHANNEL2_WEIGHT) +#define BITS_AC_CHANNEL2_WEIGHT \ + (BIT_MASK_AC_CHANNEL2_WEIGHT << BIT_SHIFT_AC_CHANNEL2_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL2_WEIGHT)) +#define BIT_GET_AC_CHANNEL2_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL2_WEIGHT) & BIT_MASK_AC_CHANNEL2_WEIGHT) +#define BIT_SET_AC_CHANNEL2_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) | BIT_AC_CHANNEL2_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL3_WEIGHT (Offset 0x336B) */ + +#define BIT_SHIFT_AC_CHANNEL3_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL3_WEIGHT 0xff +#define BIT_AC_CHANNEL3_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL3_WEIGHT) << BIT_SHIFT_AC_CHANNEL3_WEIGHT) +#define BITS_AC_CHANNEL3_WEIGHT \ + (BIT_MASK_AC_CHANNEL3_WEIGHT << BIT_SHIFT_AC_CHANNEL3_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL3_WEIGHT)) +#define BIT_GET_AC_CHANNEL3_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL3_WEIGHT) & BIT_MASK_AC_CHANNEL3_WEIGHT) +#define BIT_SET_AC_CHANNEL3_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) | BIT_AC_CHANNEL3_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL4_WEIGHT (Offset 0x336C) */ + +#define BIT_SHIFT_AC_CHANNEL4_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL4_WEIGHT 0xff +#define BIT_AC_CHANNEL4_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL4_WEIGHT) << BIT_SHIFT_AC_CHANNEL4_WEIGHT) +#define BITS_AC_CHANNEL4_WEIGHT \ + (BIT_MASK_AC_CHANNEL4_WEIGHT << BIT_SHIFT_AC_CHANNEL4_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL4_WEIGHT)) +#define BIT_GET_AC_CHANNEL4_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL4_WEIGHT) & BIT_MASK_AC_CHANNEL4_WEIGHT) +#define BIT_SET_AC_CHANNEL4_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) | BIT_AC_CHANNEL4_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL5_WEIGHT (Offset 0x336D) */ + +#define BIT_SHIFT_AC_CHANNEL5_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL5_WEIGHT 0xff +#define BIT_AC_CHANNEL5_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL5_WEIGHT) << BIT_SHIFT_AC_CHANNEL5_WEIGHT) +#define BITS_AC_CHANNEL5_WEIGHT \ + (BIT_MASK_AC_CHANNEL5_WEIGHT << BIT_SHIFT_AC_CHANNEL5_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL5_WEIGHT)) +#define BIT_GET_AC_CHANNEL5_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL5_WEIGHT) & BIT_MASK_AC_CHANNEL5_WEIGHT) +#define BIT_SET_AC_CHANNEL5_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) | BIT_AC_CHANNEL5_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL6_WEIGHT (Offset 0x336E) */ + +#define BIT_SHIFT_AC_CHANNEL6_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL6_WEIGHT 0xff +#define BIT_AC_CHANNEL6_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL6_WEIGHT) << BIT_SHIFT_AC_CHANNEL6_WEIGHT) +#define BITS_AC_CHANNEL6_WEIGHT \ + (BIT_MASK_AC_CHANNEL6_WEIGHT << BIT_SHIFT_AC_CHANNEL6_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL6_WEIGHT)) +#define BIT_GET_AC_CHANNEL6_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL6_WEIGHT) & BIT_MASK_AC_CHANNEL6_WEIGHT) +#define BIT_SET_AC_CHANNEL6_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) | BIT_AC_CHANNEL6_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL7_WEIGHT (Offset 0x336F) */ + +#define BIT_SHIFT_AC_CHANNEL7_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL7_WEIGHT 0xff +#define BIT_AC_CHANNEL7_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL7_WEIGHT) << BIT_SHIFT_AC_CHANNEL7_WEIGHT) +#define BITS_AC_CHANNEL7_WEIGHT \ + (BIT_MASK_AC_CHANNEL7_WEIGHT << BIT_SHIFT_AC_CHANNEL7_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL7_WEIGHT)) +#define BIT_GET_AC_CHANNEL7_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL7_WEIGHT) & BIT_MASK_AC_CHANNEL7_WEIGHT) +#define BIT_SET_AC_CHANNEL7_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) | BIT_AC_CHANNEL7_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL8_WEIGHT (Offset 0x3370) */ + +#define BIT_SHIFT_AC_CHANNEL8_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL8_WEIGHT 0xff +#define BIT_AC_CHANNEL8_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL8_WEIGHT) << BIT_SHIFT_AC_CHANNEL8_WEIGHT) +#define BITS_AC_CHANNEL8_WEIGHT \ + (BIT_MASK_AC_CHANNEL8_WEIGHT << BIT_SHIFT_AC_CHANNEL8_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL8_WEIGHT)) +#define BIT_GET_AC_CHANNEL8_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL8_WEIGHT) & BIT_MASK_AC_CHANNEL8_WEIGHT) +#define BIT_SET_AC_CHANNEL8_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) | BIT_AC_CHANNEL8_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL9_WEIGHT (Offset 0x3371) */ + +#define BIT_SHIFT_AC_CHANNEL9_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL9_WEIGHT 0xff +#define BIT_AC_CHANNEL9_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL9_WEIGHT) << BIT_SHIFT_AC_CHANNEL9_WEIGHT) +#define BITS_AC_CHANNEL9_WEIGHT \ + (BIT_MASK_AC_CHANNEL9_WEIGHT << BIT_SHIFT_AC_CHANNEL9_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL9_WEIGHT)) +#define BIT_GET_AC_CHANNEL9_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL9_WEIGHT) & BIT_MASK_AC_CHANNEL9_WEIGHT) +#define BIT_SET_AC_CHANNEL9_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) | BIT_AC_CHANNEL9_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL10_WEIGHT (Offset 0x3372) */ + +#define BIT_SHIFT_AC_CHANNEL10_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL10_WEIGHT 0xff +#define BIT_AC_CHANNEL10_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL10_WEIGHT) << BIT_SHIFT_AC_CHANNEL10_WEIGHT) +#define BITS_AC_CHANNEL10_WEIGHT \ + (BIT_MASK_AC_CHANNEL10_WEIGHT << BIT_SHIFT_AC_CHANNEL10_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL10_WEIGHT)) +#define BIT_GET_AC_CHANNEL10_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL10_WEIGHT) & BIT_MASK_AC_CHANNEL10_WEIGHT) +#define BIT_SET_AC_CHANNEL10_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) | BIT_AC_CHANNEL10_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL11_WEIGHT (Offset 0x3373) */ + +#define BIT_SHIFT_AC_CHANNEL11_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL11_WEIGHT 0xff +#define BIT_AC_CHANNEL11_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL11_WEIGHT) << BIT_SHIFT_AC_CHANNEL11_WEIGHT) +#define BITS_AC_CHANNEL11_WEIGHT \ + (BIT_MASK_AC_CHANNEL11_WEIGHT << BIT_SHIFT_AC_CHANNEL11_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL11_WEIGHT)) +#define BIT_GET_AC_CHANNEL11_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL11_WEIGHT) & BIT_MASK_AC_CHANNEL11_WEIGHT) +#define BIT_SET_AC_CHANNEL11_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) | BIT_AC_CHANNEL11_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL12_WEIGHT (Offset 0x3374) */ + +#define BIT_SHIFT_AC_CHANNEL12_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL12_WEIGHT 0xff +#define BIT_AC_CHANNEL12_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL12_WEIGHT) << BIT_SHIFT_AC_CHANNEL12_WEIGHT) +#define BITS_AC_CHANNEL12_WEIGHT \ + (BIT_MASK_AC_CHANNEL12_WEIGHT << BIT_SHIFT_AC_CHANNEL12_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL12_WEIGHT)) +#define BIT_GET_AC_CHANNEL12_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL12_WEIGHT) & BIT_MASK_AC_CHANNEL12_WEIGHT) +#define BIT_SET_AC_CHANNEL12_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) | BIT_AC_CHANNEL12_WEIGHT(v)) + +/* 2 REG_AC_CHANNEL13_WEIGHT (Offset 0x3375) */ + +#define BIT_SHIFT_AC_CHANNEL13_WEIGHT 0 +#define BIT_MASK_AC_CHANNEL13_WEIGHT 0xff +#define BIT_AC_CHANNEL13_WEIGHT(x) \ + (((x) & BIT_MASK_AC_CHANNEL13_WEIGHT) << BIT_SHIFT_AC_CHANNEL13_WEIGHT) +#define BITS_AC_CHANNEL13_WEIGHT \ + (BIT_MASK_AC_CHANNEL13_WEIGHT << BIT_SHIFT_AC_CHANNEL13_WEIGHT) +#define BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL13_WEIGHT)) +#define BIT_GET_AC_CHANNEL13_WEIGHT(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL13_WEIGHT) & BIT_MASK_AC_CHANNEL13_WEIGHT) +#define BIT_SET_AC_CHANNEL13_WEIGHT(x, v) \ + (BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) | BIT_AC_CHANNEL13_WEIGHT(v)) + +#endif + +#endif /* __RTL_WLAN_BITDEF_H__ */ diff --git a/hal/halmac/halmac_bit_8197f.h b/hal/halmac/halmac_bit_8197f.h index da10b49..a8cf8eb 100644 --- a/hal/halmac/halmac_bit_8197f.h +++ b/hal/halmac/halmac_bit_8197f.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_BIT_8197F_H #define __INC_HALMAC_BIT_8197F_H @@ -91,20 +106,25 @@ #define BIT_SHIFT_VPDIDX_8197F 8 #define BIT_MASK_VPDIDX_8197F 0xff -#define BIT_VPDIDX_8197F(x) (((x) & BIT_MASK_VPDIDX_8197F) << BIT_SHIFT_VPDIDX_8197F) +#define BIT_VPDIDX_8197F(x) \ + (((x) & BIT_MASK_VPDIDX_8197F) << BIT_SHIFT_VPDIDX_8197F) #define BITS_VPDIDX_8197F (BIT_MASK_VPDIDX_8197F << BIT_SHIFT_VPDIDX_8197F) #define BIT_CLEAR_VPDIDX_8197F(x) ((x) & (~BITS_VPDIDX_8197F)) -#define BIT_GET_VPDIDX_8197F(x) (((x) >> BIT_SHIFT_VPDIDX_8197F) & BIT_MASK_VPDIDX_8197F) -#define BIT_SET_VPDIDX_8197F(x, v) (BIT_CLEAR_VPDIDX_8197F(x) | BIT_VPDIDX_8197F(v)) - +#define BIT_GET_VPDIDX_8197F(x) \ + (((x) >> BIT_SHIFT_VPDIDX_8197F) & BIT_MASK_VPDIDX_8197F) +#define BIT_SET_VPDIDX_8197F(x, v) \ + (BIT_CLEAR_VPDIDX_8197F(x) | BIT_VPDIDX_8197F(v)) #define BIT_SHIFT_EEM1_0_8197F 6 #define BIT_MASK_EEM1_0_8197F 0x3 -#define BIT_EEM1_0_8197F(x) (((x) & BIT_MASK_EEM1_0_8197F) << BIT_SHIFT_EEM1_0_8197F) +#define BIT_EEM1_0_8197F(x) \ + (((x) & BIT_MASK_EEM1_0_8197F) << BIT_SHIFT_EEM1_0_8197F) #define BITS_EEM1_0_8197F (BIT_MASK_EEM1_0_8197F << BIT_SHIFT_EEM1_0_8197F) #define BIT_CLEAR_EEM1_0_8197F(x) ((x) & (~BITS_EEM1_0_8197F)) -#define BIT_GET_EEM1_0_8197F(x) (((x) >> BIT_SHIFT_EEM1_0_8197F) & BIT_MASK_EEM1_0_8197F) -#define BIT_SET_EEM1_0_8197F(x, v) (BIT_CLEAR_EEM1_0_8197F(x) | BIT_EEM1_0_8197F(v)) +#define BIT_GET_EEM1_0_8197F(x) \ + (((x) >> BIT_SHIFT_EEM1_0_8197F) & BIT_MASK_EEM1_0_8197F) +#define BIT_SET_EEM1_0_8197F(x, v) \ + (BIT_CLEAR_EEM1_0_8197F(x) | BIT_EEM1_0_8197F(v)) #define BIT_AUTOLOAD_SUS_8197F BIT(5) #define BIT_EERPOMSEL_8197F BIT(4) @@ -117,42 +137,55 @@ #define BIT_SHIFT_VPD_DATA_8197F 0 #define BIT_MASK_VPD_DATA_8197F 0xffffffffL -#define BIT_VPD_DATA_8197F(x) (((x) & BIT_MASK_VPD_DATA_8197F) << BIT_SHIFT_VPD_DATA_8197F) -#define BITS_VPD_DATA_8197F (BIT_MASK_VPD_DATA_8197F << BIT_SHIFT_VPD_DATA_8197F) +#define BIT_VPD_DATA_8197F(x) \ + (((x) & BIT_MASK_VPD_DATA_8197F) << BIT_SHIFT_VPD_DATA_8197F) +#define BITS_VPD_DATA_8197F \ + (BIT_MASK_VPD_DATA_8197F << BIT_SHIFT_VPD_DATA_8197F) #define BIT_CLEAR_VPD_DATA_8197F(x) ((x) & (~BITS_VPD_DATA_8197F)) -#define BIT_GET_VPD_DATA_8197F(x) (((x) >> BIT_SHIFT_VPD_DATA_8197F) & BIT_MASK_VPD_DATA_8197F) -#define BIT_SET_VPD_DATA_8197F(x, v) (BIT_CLEAR_VPD_DATA_8197F(x) | BIT_VPD_DATA_8197F(v)) - +#define BIT_GET_VPD_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_VPD_DATA_8197F) & BIT_MASK_VPD_DATA_8197F) +#define BIT_SET_VPD_DATA_8197F(x, v) \ + (BIT_CLEAR_VPD_DATA_8197F(x) | BIT_VPD_DATA_8197F(v)) /* 2 REG_SYS_SWR_CTRL1_8197F */ #define BIT_SW18_C2_BIT0_8197F BIT(31) #define BIT_SHIFT_SW18_C1_8197F 29 #define BIT_MASK_SW18_C1_8197F 0x3 -#define BIT_SW18_C1_8197F(x) (((x) & BIT_MASK_SW18_C1_8197F) << BIT_SHIFT_SW18_C1_8197F) +#define BIT_SW18_C1_8197F(x) \ + (((x) & BIT_MASK_SW18_C1_8197F) << BIT_SHIFT_SW18_C1_8197F) #define BITS_SW18_C1_8197F (BIT_MASK_SW18_C1_8197F << BIT_SHIFT_SW18_C1_8197F) #define BIT_CLEAR_SW18_C1_8197F(x) ((x) & (~BITS_SW18_C1_8197F)) -#define BIT_GET_SW18_C1_8197F(x) (((x) >> BIT_SHIFT_SW18_C1_8197F) & BIT_MASK_SW18_C1_8197F) -#define BIT_SET_SW18_C1_8197F(x, v) (BIT_CLEAR_SW18_C1_8197F(x) | BIT_SW18_C1_8197F(v)) - +#define BIT_GET_SW18_C1_8197F(x) \ + (((x) >> BIT_SHIFT_SW18_C1_8197F) & BIT_MASK_SW18_C1_8197F) +#define BIT_SET_SW18_C1_8197F(x, v) \ + (BIT_CLEAR_SW18_C1_8197F(x) | BIT_SW18_C1_8197F(v)) #define BIT_SHIFT_REG_FREQ_L_8197F 25 #define BIT_MASK_REG_FREQ_L_8197F 0x7 -#define BIT_REG_FREQ_L_8197F(x) (((x) & BIT_MASK_REG_FREQ_L_8197F) << BIT_SHIFT_REG_FREQ_L_8197F) -#define BITS_REG_FREQ_L_8197F (BIT_MASK_REG_FREQ_L_8197F << BIT_SHIFT_REG_FREQ_L_8197F) +#define BIT_REG_FREQ_L_8197F(x) \ + (((x) & BIT_MASK_REG_FREQ_L_8197F) << BIT_SHIFT_REG_FREQ_L_8197F) +#define BITS_REG_FREQ_L_8197F \ + (BIT_MASK_REG_FREQ_L_8197F << BIT_SHIFT_REG_FREQ_L_8197F) #define BIT_CLEAR_REG_FREQ_L_8197F(x) ((x) & (~BITS_REG_FREQ_L_8197F)) -#define BIT_GET_REG_FREQ_L_8197F(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8197F) & BIT_MASK_REG_FREQ_L_8197F) -#define BIT_SET_REG_FREQ_L_8197F(x, v) (BIT_CLEAR_REG_FREQ_L_8197F(x) | BIT_REG_FREQ_L_8197F(v)) +#define BIT_GET_REG_FREQ_L_8197F(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_8197F) & BIT_MASK_REG_FREQ_L_8197F) +#define BIT_SET_REG_FREQ_L_8197F(x, v) \ + (BIT_CLEAR_REG_FREQ_L_8197F(x) | BIT_REG_FREQ_L_8197F(v)) #define BIT_REG_EN_DUTY_8197F BIT(24) #define BIT_SHIFT_REG_MODE_8197F 22 #define BIT_MASK_REG_MODE_8197F 0x3 -#define BIT_REG_MODE_8197F(x) (((x) & BIT_MASK_REG_MODE_8197F) << BIT_SHIFT_REG_MODE_8197F) -#define BITS_REG_MODE_8197F (BIT_MASK_REG_MODE_8197F << BIT_SHIFT_REG_MODE_8197F) +#define BIT_REG_MODE_8197F(x) \ + (((x) & BIT_MASK_REG_MODE_8197F) << BIT_SHIFT_REG_MODE_8197F) +#define BITS_REG_MODE_8197F \ + (BIT_MASK_REG_MODE_8197F << BIT_SHIFT_REG_MODE_8197F) #define BIT_CLEAR_REG_MODE_8197F(x) ((x) & (~BITS_REG_MODE_8197F)) -#define BIT_GET_REG_MODE_8197F(x) (((x) >> BIT_SHIFT_REG_MODE_8197F) & BIT_MASK_REG_MODE_8197F) -#define BIT_SET_REG_MODE_8197F(x, v) (BIT_CLEAR_REG_MODE_8197F(x) | BIT_REG_MODE_8197F(v)) +#define BIT_GET_REG_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_REG_MODE_8197F) & BIT_MASK_REG_MODE_8197F) +#define BIT_SET_REG_MODE_8197F(x, v) \ + (BIT_CLEAR_REG_MODE_8197F(x) | BIT_REG_MODE_8197F(v)) #define BIT_REG_EN_SP_8197F BIT(21) #define BIT_REG_AUTO_L_8197F BIT(20) @@ -161,20 +194,29 @@ #define BIT_SHIFT_SW18_OCP_8197F 15 #define BIT_MASK_SW18_OCP_8197F 0x7 -#define BIT_SW18_OCP_8197F(x) (((x) & BIT_MASK_SW18_OCP_8197F) << BIT_SHIFT_SW18_OCP_8197F) -#define BITS_SW18_OCP_8197F (BIT_MASK_SW18_OCP_8197F << BIT_SHIFT_SW18_OCP_8197F) +#define BIT_SW18_OCP_8197F(x) \ + (((x) & BIT_MASK_SW18_OCP_8197F) << BIT_SHIFT_SW18_OCP_8197F) +#define BITS_SW18_OCP_8197F \ + (BIT_MASK_SW18_OCP_8197F << BIT_SHIFT_SW18_OCP_8197F) #define BIT_CLEAR_SW18_OCP_8197F(x) ((x) & (~BITS_SW18_OCP_8197F)) -#define BIT_GET_SW18_OCP_8197F(x) (((x) >> BIT_SHIFT_SW18_OCP_8197F) & BIT_MASK_SW18_OCP_8197F) -#define BIT_SET_SW18_OCP_8197F(x, v) (BIT_CLEAR_SW18_OCP_8197F(x) | BIT_SW18_OCP_8197F(v)) - +#define BIT_GET_SW18_OCP_8197F(x) \ + (((x) >> BIT_SHIFT_SW18_OCP_8197F) & BIT_MASK_SW18_OCP_8197F) +#define BIT_SET_SW18_OCP_8197F(x, v) \ + (BIT_CLEAR_SW18_OCP_8197F(x) | BIT_SW18_OCP_8197F(v)) #define BIT_SHIFT_CF_L_BIT0_TO_1_8197F 13 #define BIT_MASK_CF_L_BIT0_TO_1_8197F 0x3 -#define BIT_CF_L_BIT0_TO_1_8197F(x) (((x) & BIT_MASK_CF_L_BIT0_TO_1_8197F) << BIT_SHIFT_CF_L_BIT0_TO_1_8197F) -#define BITS_CF_L_BIT0_TO_1_8197F (BIT_MASK_CF_L_BIT0_TO_1_8197F << BIT_SHIFT_CF_L_BIT0_TO_1_8197F) +#define BIT_CF_L_BIT0_TO_1_8197F(x) \ + (((x) & BIT_MASK_CF_L_BIT0_TO_1_8197F) \ + << BIT_SHIFT_CF_L_BIT0_TO_1_8197F) +#define BITS_CF_L_BIT0_TO_1_8197F \ + (BIT_MASK_CF_L_BIT0_TO_1_8197F << BIT_SHIFT_CF_L_BIT0_TO_1_8197F) #define BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) ((x) & (~BITS_CF_L_BIT0_TO_1_8197F)) -#define BIT_GET_CF_L_BIT0_TO_1_8197F(x) (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1_8197F) & BIT_MASK_CF_L_BIT0_TO_1_8197F) -#define BIT_SET_CF_L_BIT0_TO_1_8197F(x, v) (BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) | BIT_CF_L_BIT0_TO_1_8197F(v)) +#define BIT_GET_CF_L_BIT0_TO_1_8197F(x) \ + (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1_8197F) & \ + BIT_MASK_CF_L_BIT0_TO_1_8197F) +#define BIT_SET_CF_L_BIT0_TO_1_8197F(x, v) \ + (BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) | BIT_CF_L_BIT0_TO_1_8197F(v)) #define BIT_SW18_FPWM_8197F BIT(11) #define BIT_SW18_SWEN_8197F BIT(9) @@ -226,21 +268,27 @@ #define BIT_SHIFT_SPS18_OCP_TH_8197F 16 #define BIT_MASK_SPS18_OCP_TH_8197F 0x7fff -#define BIT_SPS18_OCP_TH_8197F(x) (((x) & BIT_MASK_SPS18_OCP_TH_8197F) << BIT_SHIFT_SPS18_OCP_TH_8197F) -#define BITS_SPS18_OCP_TH_8197F (BIT_MASK_SPS18_OCP_TH_8197F << BIT_SHIFT_SPS18_OCP_TH_8197F) +#define BIT_SPS18_OCP_TH_8197F(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH_8197F) << BIT_SHIFT_SPS18_OCP_TH_8197F) +#define BITS_SPS18_OCP_TH_8197F \ + (BIT_MASK_SPS18_OCP_TH_8197F << BIT_SHIFT_SPS18_OCP_TH_8197F) #define BIT_CLEAR_SPS18_OCP_TH_8197F(x) ((x) & (~BITS_SPS18_OCP_TH_8197F)) -#define BIT_GET_SPS18_OCP_TH_8197F(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8197F) & BIT_MASK_SPS18_OCP_TH_8197F) -#define BIT_SET_SPS18_OCP_TH_8197F(x, v) (BIT_CLEAR_SPS18_OCP_TH_8197F(x) | BIT_SPS18_OCP_TH_8197F(v)) - +#define BIT_GET_SPS18_OCP_TH_8197F(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH_8197F) & BIT_MASK_SPS18_OCP_TH_8197F) +#define BIT_SET_SPS18_OCP_TH_8197F(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH_8197F(x) | BIT_SPS18_OCP_TH_8197F(v)) #define BIT_SHIFT_OCP_WINDOW_8197F 0 #define BIT_MASK_OCP_WINDOW_8197F 0xffff -#define BIT_OCP_WINDOW_8197F(x) (((x) & BIT_MASK_OCP_WINDOW_8197F) << BIT_SHIFT_OCP_WINDOW_8197F) -#define BITS_OCP_WINDOW_8197F (BIT_MASK_OCP_WINDOW_8197F << BIT_SHIFT_OCP_WINDOW_8197F) +#define BIT_OCP_WINDOW_8197F(x) \ + (((x) & BIT_MASK_OCP_WINDOW_8197F) << BIT_SHIFT_OCP_WINDOW_8197F) +#define BITS_OCP_WINDOW_8197F \ + (BIT_MASK_OCP_WINDOW_8197F << BIT_SHIFT_OCP_WINDOW_8197F) #define BIT_CLEAR_OCP_WINDOW_8197F(x) ((x) & (~BITS_OCP_WINDOW_8197F)) -#define BIT_GET_OCP_WINDOW_8197F(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8197F) & BIT_MASK_OCP_WINDOW_8197F) -#define BIT_SET_OCP_WINDOW_8197F(x, v) (BIT_CLEAR_OCP_WINDOW_8197F(x) | BIT_OCP_WINDOW_8197F(v)) - +#define BIT_GET_OCP_WINDOW_8197F(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW_8197F) & BIT_MASK_OCP_WINDOW_8197F) +#define BIT_SET_OCP_WINDOW_8197F(x, v) \ + (BIT_CLEAR_OCP_WINDOW_8197F(x) | BIT_OCP_WINDOW_8197F(v)) /* 2 REG_RSV_CTRL_8197F */ #define BIT_HREG_DBG_8197F BIT(23) @@ -263,21 +311,29 @@ #define BIT_SHIFT_LPLDH12_RSV_8197F 29 #define BIT_MASK_LPLDH12_RSV_8197F 0x7 -#define BIT_LPLDH12_RSV_8197F(x) (((x) & BIT_MASK_LPLDH12_RSV_8197F) << BIT_SHIFT_LPLDH12_RSV_8197F) -#define BITS_LPLDH12_RSV_8197F (BIT_MASK_LPLDH12_RSV_8197F << BIT_SHIFT_LPLDH12_RSV_8197F) +#define BIT_LPLDH12_RSV_8197F(x) \ + (((x) & BIT_MASK_LPLDH12_RSV_8197F) << BIT_SHIFT_LPLDH12_RSV_8197F) +#define BITS_LPLDH12_RSV_8197F \ + (BIT_MASK_LPLDH12_RSV_8197F << BIT_SHIFT_LPLDH12_RSV_8197F) #define BIT_CLEAR_LPLDH12_RSV_8197F(x) ((x) & (~BITS_LPLDH12_RSV_8197F)) -#define BIT_GET_LPLDH12_RSV_8197F(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8197F) & BIT_MASK_LPLDH12_RSV_8197F) -#define BIT_SET_LPLDH12_RSV_8197F(x, v) (BIT_CLEAR_LPLDH12_RSV_8197F(x) | BIT_LPLDH12_RSV_8197F(v)) +#define BIT_GET_LPLDH12_RSV_8197F(x) \ + (((x) >> BIT_SHIFT_LPLDH12_RSV_8197F) & BIT_MASK_LPLDH12_RSV_8197F) +#define BIT_SET_LPLDH12_RSV_8197F(x, v) \ + (BIT_CLEAR_LPLDH12_RSV_8197F(x) | BIT_LPLDH12_RSV_8197F(v)) #define BIT_LPLDH12_SLP_8197F BIT(28) #define BIT_SHIFT_LPLDH12_VADJ_8197F 24 #define BIT_MASK_LPLDH12_VADJ_8197F 0xf -#define BIT_LPLDH12_VADJ_8197F(x) (((x) & BIT_MASK_LPLDH12_VADJ_8197F) << BIT_SHIFT_LPLDH12_VADJ_8197F) -#define BITS_LPLDH12_VADJ_8197F (BIT_MASK_LPLDH12_VADJ_8197F << BIT_SHIFT_LPLDH12_VADJ_8197F) +#define BIT_LPLDH12_VADJ_8197F(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_8197F) << BIT_SHIFT_LPLDH12_VADJ_8197F) +#define BITS_LPLDH12_VADJ_8197F \ + (BIT_MASK_LPLDH12_VADJ_8197F << BIT_SHIFT_LPLDH12_VADJ_8197F) #define BIT_CLEAR_LPLDH12_VADJ_8197F(x) ((x) & (~BITS_LPLDH12_VADJ_8197F)) -#define BIT_GET_LPLDH12_VADJ_8197F(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8197F) & BIT_MASK_LPLDH12_VADJ_8197F) -#define BIT_SET_LPLDH12_VADJ_8197F(x, v) (BIT_CLEAR_LPLDH12_VADJ_8197F(x) | BIT_LPLDH12_VADJ_8197F(v)) +#define BIT_GET_LPLDH12_VADJ_8197F(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_8197F) & BIT_MASK_LPLDH12_VADJ_8197F) +#define BIT_SET_LPLDH12_VADJ_8197F(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_8197F(x) | BIT_LPLDH12_VADJ_8197F(v)) #define BIT_LDH12_EN_8197F BIT(16) #define BIT_POW_REGU_P1_8197F BIT(10) @@ -297,58 +353,79 @@ #define BIT_SHIFT_XTAL_CAP_XI_8197F 25 #define BIT_MASK_XTAL_CAP_XI_8197F 0x3f -#define BIT_XTAL_CAP_XI_8197F(x) (((x) & BIT_MASK_XTAL_CAP_XI_8197F) << BIT_SHIFT_XTAL_CAP_XI_8197F) -#define BITS_XTAL_CAP_XI_8197F (BIT_MASK_XTAL_CAP_XI_8197F << BIT_SHIFT_XTAL_CAP_XI_8197F) +#define BIT_XTAL_CAP_XI_8197F(x) \ + (((x) & BIT_MASK_XTAL_CAP_XI_8197F) << BIT_SHIFT_XTAL_CAP_XI_8197F) +#define BITS_XTAL_CAP_XI_8197F \ + (BIT_MASK_XTAL_CAP_XI_8197F << BIT_SHIFT_XTAL_CAP_XI_8197F) #define BIT_CLEAR_XTAL_CAP_XI_8197F(x) ((x) & (~BITS_XTAL_CAP_XI_8197F)) -#define BIT_GET_XTAL_CAP_XI_8197F(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8197F) & BIT_MASK_XTAL_CAP_XI_8197F) -#define BIT_SET_XTAL_CAP_XI_8197F(x, v) (BIT_CLEAR_XTAL_CAP_XI_8197F(x) | BIT_XTAL_CAP_XI_8197F(v)) - +#define BIT_GET_XTAL_CAP_XI_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XI_8197F) & BIT_MASK_XTAL_CAP_XI_8197F) +#define BIT_SET_XTAL_CAP_XI_8197F(x, v) \ + (BIT_CLEAR_XTAL_CAP_XI_8197F(x) | BIT_XTAL_CAP_XI_8197F(v)) #define BIT_SHIFT_XTAL_DRV_DIGI_8197F 23 #define BIT_MASK_XTAL_DRV_DIGI_8197F 0x3 -#define BIT_XTAL_DRV_DIGI_8197F(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8197F) << BIT_SHIFT_XTAL_DRV_DIGI_8197F) -#define BITS_XTAL_DRV_DIGI_8197F (BIT_MASK_XTAL_DRV_DIGI_8197F << BIT_SHIFT_XTAL_DRV_DIGI_8197F) +#define BIT_XTAL_DRV_DIGI_8197F(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_8197F) << BIT_SHIFT_XTAL_DRV_DIGI_8197F) +#define BITS_XTAL_DRV_DIGI_8197F \ + (BIT_MASK_XTAL_DRV_DIGI_8197F << BIT_SHIFT_XTAL_DRV_DIGI_8197F) #define BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) ((x) & (~BITS_XTAL_DRV_DIGI_8197F)) -#define BIT_GET_XTAL_DRV_DIGI_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8197F) & BIT_MASK_XTAL_DRV_DIGI_8197F) -#define BIT_SET_XTAL_DRV_DIGI_8197F(x, v) (BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) | BIT_XTAL_DRV_DIGI_8197F(v)) +#define BIT_GET_XTAL_DRV_DIGI_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8197F) & BIT_MASK_XTAL_DRV_DIGI_8197F) +#define BIT_SET_XTAL_DRV_DIGI_8197F(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) | BIT_XTAL_DRV_DIGI_8197F(v)) #define BIT_XTAL_DRV_USB_BIT1_8197F BIT(22) #define BIT_SHIFT_MAC_CLK_SEL_8197F 20 #define BIT_MASK_MAC_CLK_SEL_8197F 0x3 -#define BIT_MAC_CLK_SEL_8197F(x) (((x) & BIT_MASK_MAC_CLK_SEL_8197F) << BIT_SHIFT_MAC_CLK_SEL_8197F) -#define BITS_MAC_CLK_SEL_8197F (BIT_MASK_MAC_CLK_SEL_8197F << BIT_SHIFT_MAC_CLK_SEL_8197F) +#define BIT_MAC_CLK_SEL_8197F(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_8197F) << BIT_SHIFT_MAC_CLK_SEL_8197F) +#define BITS_MAC_CLK_SEL_8197F \ + (BIT_MASK_MAC_CLK_SEL_8197F << BIT_SHIFT_MAC_CLK_SEL_8197F) #define BIT_CLEAR_MAC_CLK_SEL_8197F(x) ((x) & (~BITS_MAC_CLK_SEL_8197F)) -#define BIT_GET_MAC_CLK_SEL_8197F(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8197F) & BIT_MASK_MAC_CLK_SEL_8197F) -#define BIT_SET_MAC_CLK_SEL_8197F(x, v) (BIT_CLEAR_MAC_CLK_SEL_8197F(x) | BIT_MAC_CLK_SEL_8197F(v)) +#define BIT_GET_MAC_CLK_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_8197F) & BIT_MASK_MAC_CLK_SEL_8197F) +#define BIT_SET_MAC_CLK_SEL_8197F(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_8197F(x) | BIT_MAC_CLK_SEL_8197F(v)) #define BIT_XTAL_DRV_USB_BIT0_8197F BIT(19) #define BIT_SHIFT_XTAL_DRV_AFE_8197F 17 #define BIT_MASK_XTAL_DRV_AFE_8197F 0x3 -#define BIT_XTAL_DRV_AFE_8197F(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8197F) << BIT_SHIFT_XTAL_DRV_AFE_8197F) -#define BITS_XTAL_DRV_AFE_8197F (BIT_MASK_XTAL_DRV_AFE_8197F << BIT_SHIFT_XTAL_DRV_AFE_8197F) +#define BIT_XTAL_DRV_AFE_8197F(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_8197F) << BIT_SHIFT_XTAL_DRV_AFE_8197F) +#define BITS_XTAL_DRV_AFE_8197F \ + (BIT_MASK_XTAL_DRV_AFE_8197F << BIT_SHIFT_XTAL_DRV_AFE_8197F) #define BIT_CLEAR_XTAL_DRV_AFE_8197F(x) ((x) & (~BITS_XTAL_DRV_AFE_8197F)) -#define BIT_GET_XTAL_DRV_AFE_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8197F) & BIT_MASK_XTAL_DRV_AFE_8197F) -#define BIT_SET_XTAL_DRV_AFE_8197F(x, v) (BIT_CLEAR_XTAL_DRV_AFE_8197F(x) | BIT_XTAL_DRV_AFE_8197F(v)) - +#define BIT_GET_XTAL_DRV_AFE_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8197F) & BIT_MASK_XTAL_DRV_AFE_8197F) +#define BIT_SET_XTAL_DRV_AFE_8197F(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_8197F(x) | BIT_XTAL_DRV_AFE_8197F(v)) #define BIT_SHIFT_XTAL_DRV_RF2_8197F 15 #define BIT_MASK_XTAL_DRV_RF2_8197F 0x3 -#define BIT_XTAL_DRV_RF2_8197F(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8197F) << BIT_SHIFT_XTAL_DRV_RF2_8197F) -#define BITS_XTAL_DRV_RF2_8197F (BIT_MASK_XTAL_DRV_RF2_8197F << BIT_SHIFT_XTAL_DRV_RF2_8197F) +#define BIT_XTAL_DRV_RF2_8197F(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_8197F) << BIT_SHIFT_XTAL_DRV_RF2_8197F) +#define BITS_XTAL_DRV_RF2_8197F \ + (BIT_MASK_XTAL_DRV_RF2_8197F << BIT_SHIFT_XTAL_DRV_RF2_8197F) #define BIT_CLEAR_XTAL_DRV_RF2_8197F(x) ((x) & (~BITS_XTAL_DRV_RF2_8197F)) -#define BIT_GET_XTAL_DRV_RF2_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8197F) & BIT_MASK_XTAL_DRV_RF2_8197F) -#define BIT_SET_XTAL_DRV_RF2_8197F(x, v) (BIT_CLEAR_XTAL_DRV_RF2_8197F(x) | BIT_XTAL_DRV_RF2_8197F(v)) - +#define BIT_GET_XTAL_DRV_RF2_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8197F) & BIT_MASK_XTAL_DRV_RF2_8197F) +#define BIT_SET_XTAL_DRV_RF2_8197F(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_8197F(x) | BIT_XTAL_DRV_RF2_8197F(v)) #define BIT_SHIFT_XTAL_DRV_RF1_8197F 13 #define BIT_MASK_XTAL_DRV_RF1_8197F 0x3 -#define BIT_XTAL_DRV_RF1_8197F(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8197F) << BIT_SHIFT_XTAL_DRV_RF1_8197F) -#define BITS_XTAL_DRV_RF1_8197F (BIT_MASK_XTAL_DRV_RF1_8197F << BIT_SHIFT_XTAL_DRV_RF1_8197F) +#define BIT_XTAL_DRV_RF1_8197F(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF1_8197F) << BIT_SHIFT_XTAL_DRV_RF1_8197F) +#define BITS_XTAL_DRV_RF1_8197F \ + (BIT_MASK_XTAL_DRV_RF1_8197F << BIT_SHIFT_XTAL_DRV_RF1_8197F) #define BIT_CLEAR_XTAL_DRV_RF1_8197F(x) ((x) & (~BITS_XTAL_DRV_RF1_8197F)) -#define BIT_GET_XTAL_DRV_RF1_8197F(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8197F) & BIT_MASK_XTAL_DRV_RF1_8197F) -#define BIT_SET_XTAL_DRV_RF1_8197F(x, v) (BIT_CLEAR_XTAL_DRV_RF1_8197F(x) | BIT_XTAL_DRV_RF1_8197F(v)) +#define BIT_GET_XTAL_DRV_RF1_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8197F) & BIT_MASK_XTAL_DRV_RF1_8197F) +#define BIT_SET_XTAL_DRV_RF1_8197F(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF1_8197F(x) | BIT_XTAL_DRV_RF1_8197F(v)) #define BIT_XTAL_DELAY_DIGI_8197F BIT(12) #define BIT_XTAL_DELAY_USB_8197F BIT(11) @@ -361,20 +438,27 @@ #define BIT_SHIFT_XTAL_GMN_V1_8197F 3 #define BIT_MASK_XTAL_GMN_V1_8197F 0x3 -#define BIT_XTAL_GMN_V1_8197F(x) (((x) & BIT_MASK_XTAL_GMN_V1_8197F) << BIT_SHIFT_XTAL_GMN_V1_8197F) -#define BITS_XTAL_GMN_V1_8197F (BIT_MASK_XTAL_GMN_V1_8197F << BIT_SHIFT_XTAL_GMN_V1_8197F) +#define BIT_XTAL_GMN_V1_8197F(x) \ + (((x) & BIT_MASK_XTAL_GMN_V1_8197F) << BIT_SHIFT_XTAL_GMN_V1_8197F) +#define BITS_XTAL_GMN_V1_8197F \ + (BIT_MASK_XTAL_GMN_V1_8197F << BIT_SHIFT_XTAL_GMN_V1_8197F) #define BIT_CLEAR_XTAL_GMN_V1_8197F(x) ((x) & (~BITS_XTAL_GMN_V1_8197F)) -#define BIT_GET_XTAL_GMN_V1_8197F(x) (((x) >> BIT_SHIFT_XTAL_GMN_V1_8197F) & BIT_MASK_XTAL_GMN_V1_8197F) -#define BIT_SET_XTAL_GMN_V1_8197F(x, v) (BIT_CLEAR_XTAL_GMN_V1_8197F(x) | BIT_XTAL_GMN_V1_8197F(v)) - +#define BIT_GET_XTAL_GMN_V1_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V1_8197F) & BIT_MASK_XTAL_GMN_V1_8197F) +#define BIT_SET_XTAL_GMN_V1_8197F(x, v) \ + (BIT_CLEAR_XTAL_GMN_V1_8197F(x) | BIT_XTAL_GMN_V1_8197F(v)) #define BIT_SHIFT_XTAL_GMP_V1_8197F 1 #define BIT_MASK_XTAL_GMP_V1_8197F 0x3 -#define BIT_XTAL_GMP_V1_8197F(x) (((x) & BIT_MASK_XTAL_GMP_V1_8197F) << BIT_SHIFT_XTAL_GMP_V1_8197F) -#define BITS_XTAL_GMP_V1_8197F (BIT_MASK_XTAL_GMP_V1_8197F << BIT_SHIFT_XTAL_GMP_V1_8197F) +#define BIT_XTAL_GMP_V1_8197F(x) \ + (((x) & BIT_MASK_XTAL_GMP_V1_8197F) << BIT_SHIFT_XTAL_GMP_V1_8197F) +#define BITS_XTAL_GMP_V1_8197F \ + (BIT_MASK_XTAL_GMP_V1_8197F << BIT_SHIFT_XTAL_GMP_V1_8197F) #define BIT_CLEAR_XTAL_GMP_V1_8197F(x) ((x) & (~BITS_XTAL_GMP_V1_8197F)) -#define BIT_GET_XTAL_GMP_V1_8197F(x) (((x) >> BIT_SHIFT_XTAL_GMP_V1_8197F) & BIT_MASK_XTAL_GMP_V1_8197F) -#define BIT_SET_XTAL_GMP_V1_8197F(x, v) (BIT_CLEAR_XTAL_GMP_V1_8197F(x) | BIT_XTAL_GMP_V1_8197F(v)) +#define BIT_GET_XTAL_GMP_V1_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V1_8197F) & BIT_MASK_XTAL_GMP_V1_8197F) +#define BIT_SET_XTAL_GMP_V1_8197F(x, v) \ + (BIT_CLEAR_XTAL_GMP_V1_8197F(x) | BIT_XTAL_GMP_V1_8197F(v)) #define BIT_XTAL_EN_8197F BIT(0) @@ -382,58 +466,78 @@ #define BIT_SHIFT_RS_SET_V2_8197F 26 #define BIT_MASK_RS_SET_V2_8197F 0x7 -#define BIT_RS_SET_V2_8197F(x) (((x) & BIT_MASK_RS_SET_V2_8197F) << BIT_SHIFT_RS_SET_V2_8197F) -#define BITS_RS_SET_V2_8197F (BIT_MASK_RS_SET_V2_8197F << BIT_SHIFT_RS_SET_V2_8197F) +#define BIT_RS_SET_V2_8197F(x) \ + (((x) & BIT_MASK_RS_SET_V2_8197F) << BIT_SHIFT_RS_SET_V2_8197F) +#define BITS_RS_SET_V2_8197F \ + (BIT_MASK_RS_SET_V2_8197F << BIT_SHIFT_RS_SET_V2_8197F) #define BIT_CLEAR_RS_SET_V2_8197F(x) ((x) & (~BITS_RS_SET_V2_8197F)) -#define BIT_GET_RS_SET_V2_8197F(x) (((x) >> BIT_SHIFT_RS_SET_V2_8197F) & BIT_MASK_RS_SET_V2_8197F) -#define BIT_SET_RS_SET_V2_8197F(x, v) (BIT_CLEAR_RS_SET_V2_8197F(x) | BIT_RS_SET_V2_8197F(v)) - +#define BIT_GET_RS_SET_V2_8197F(x) \ + (((x) >> BIT_SHIFT_RS_SET_V2_8197F) & BIT_MASK_RS_SET_V2_8197F) +#define BIT_SET_RS_SET_V2_8197F(x, v) \ + (BIT_CLEAR_RS_SET_V2_8197F(x) | BIT_RS_SET_V2_8197F(v)) #define BIT_SHIFT_CP_BIAS_V2_8197F 18 #define BIT_MASK_CP_BIAS_V2_8197F 0x7 -#define BIT_CP_BIAS_V2_8197F(x) (((x) & BIT_MASK_CP_BIAS_V2_8197F) << BIT_SHIFT_CP_BIAS_V2_8197F) -#define BITS_CP_BIAS_V2_8197F (BIT_MASK_CP_BIAS_V2_8197F << BIT_SHIFT_CP_BIAS_V2_8197F) +#define BIT_CP_BIAS_V2_8197F(x) \ + (((x) & BIT_MASK_CP_BIAS_V2_8197F) << BIT_SHIFT_CP_BIAS_V2_8197F) +#define BITS_CP_BIAS_V2_8197F \ + (BIT_MASK_CP_BIAS_V2_8197F << BIT_SHIFT_CP_BIAS_V2_8197F) #define BIT_CLEAR_CP_BIAS_V2_8197F(x) ((x) & (~BITS_CP_BIAS_V2_8197F)) -#define BIT_GET_CP_BIAS_V2_8197F(x) (((x) >> BIT_SHIFT_CP_BIAS_V2_8197F) & BIT_MASK_CP_BIAS_V2_8197F) -#define BIT_SET_CP_BIAS_V2_8197F(x, v) (BIT_CLEAR_CP_BIAS_V2_8197F(x) | BIT_CP_BIAS_V2_8197F(v)) +#define BIT_GET_CP_BIAS_V2_8197F(x) \ + (((x) >> BIT_SHIFT_CP_BIAS_V2_8197F) & BIT_MASK_CP_BIAS_V2_8197F) +#define BIT_SET_CP_BIAS_V2_8197F(x, v) \ + (BIT_CLEAR_CP_BIAS_V2_8197F(x) | BIT_CP_BIAS_V2_8197F(v)) #define BIT_FREF_SEL_8197F BIT(16) #define BIT_SHIFT_MCCO_V2_8197F 14 #define BIT_MASK_MCCO_V2_8197F 0x3 -#define BIT_MCCO_V2_8197F(x) (((x) & BIT_MASK_MCCO_V2_8197F) << BIT_SHIFT_MCCO_V2_8197F) +#define BIT_MCCO_V2_8197F(x) \ + (((x) & BIT_MASK_MCCO_V2_8197F) << BIT_SHIFT_MCCO_V2_8197F) #define BITS_MCCO_V2_8197F (BIT_MASK_MCCO_V2_8197F << BIT_SHIFT_MCCO_V2_8197F) #define BIT_CLEAR_MCCO_V2_8197F(x) ((x) & (~BITS_MCCO_V2_8197F)) -#define BIT_GET_MCCO_V2_8197F(x) (((x) >> BIT_SHIFT_MCCO_V2_8197F) & BIT_MASK_MCCO_V2_8197F) -#define BIT_SET_MCCO_V2_8197F(x, v) (BIT_CLEAR_MCCO_V2_8197F(x) | BIT_MCCO_V2_8197F(v)) - +#define BIT_GET_MCCO_V2_8197F(x) \ + (((x) >> BIT_SHIFT_MCCO_V2_8197F) & BIT_MASK_MCCO_V2_8197F) +#define BIT_SET_MCCO_V2_8197F(x, v) \ + (BIT_CLEAR_MCCO_V2_8197F(x) | BIT_MCCO_V2_8197F(v)) #define BIT_SHIFT_CK320_EN_8197F 12 #define BIT_MASK_CK320_EN_8197F 0x3 -#define BIT_CK320_EN_8197F(x) (((x) & BIT_MASK_CK320_EN_8197F) << BIT_SHIFT_CK320_EN_8197F) -#define BITS_CK320_EN_8197F (BIT_MASK_CK320_EN_8197F << BIT_SHIFT_CK320_EN_8197F) +#define BIT_CK320_EN_8197F(x) \ + (((x) & BIT_MASK_CK320_EN_8197F) << BIT_SHIFT_CK320_EN_8197F) +#define BITS_CK320_EN_8197F \ + (BIT_MASK_CK320_EN_8197F << BIT_SHIFT_CK320_EN_8197F) #define BIT_CLEAR_CK320_EN_8197F(x) ((x) & (~BITS_CK320_EN_8197F)) -#define BIT_GET_CK320_EN_8197F(x) (((x) >> BIT_SHIFT_CK320_EN_8197F) & BIT_MASK_CK320_EN_8197F) -#define BIT_SET_CK320_EN_8197F(x, v) (BIT_CLEAR_CK320_EN_8197F(x) | BIT_CK320_EN_8197F(v)) +#define BIT_GET_CK320_EN_8197F(x) \ + (((x) >> BIT_SHIFT_CK320_EN_8197F) & BIT_MASK_CK320_EN_8197F) +#define BIT_SET_CK320_EN_8197F(x, v) \ + (BIT_CLEAR_CK320_EN_8197F(x) | BIT_CK320_EN_8197F(v)) #define BIT_AGPIO_GPO_8197F BIT(9) #define BIT_SHIFT_AGPIO_DRV_8197F 7 #define BIT_MASK_AGPIO_DRV_8197F 0x3 -#define BIT_AGPIO_DRV_8197F(x) (((x) & BIT_MASK_AGPIO_DRV_8197F) << BIT_SHIFT_AGPIO_DRV_8197F) -#define BITS_AGPIO_DRV_8197F (BIT_MASK_AGPIO_DRV_8197F << BIT_SHIFT_AGPIO_DRV_8197F) +#define BIT_AGPIO_DRV_8197F(x) \ + (((x) & BIT_MASK_AGPIO_DRV_8197F) << BIT_SHIFT_AGPIO_DRV_8197F) +#define BITS_AGPIO_DRV_8197F \ + (BIT_MASK_AGPIO_DRV_8197F << BIT_SHIFT_AGPIO_DRV_8197F) #define BIT_CLEAR_AGPIO_DRV_8197F(x) ((x) & (~BITS_AGPIO_DRV_8197F)) -#define BIT_GET_AGPIO_DRV_8197F(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8197F) & BIT_MASK_AGPIO_DRV_8197F) -#define BIT_SET_AGPIO_DRV_8197F(x, v) (BIT_CLEAR_AGPIO_DRV_8197F(x) | BIT_AGPIO_DRV_8197F(v)) - +#define BIT_GET_AGPIO_DRV_8197F(x) \ + (((x) >> BIT_SHIFT_AGPIO_DRV_8197F) & BIT_MASK_AGPIO_DRV_8197F) +#define BIT_SET_AGPIO_DRV_8197F(x, v) \ + (BIT_CLEAR_AGPIO_DRV_8197F(x) | BIT_AGPIO_DRV_8197F(v)) #define BIT_SHIFT_XTAL_CAP_XO_8197F 1 #define BIT_MASK_XTAL_CAP_XO_8197F 0x3f -#define BIT_XTAL_CAP_XO_8197F(x) (((x) & BIT_MASK_XTAL_CAP_XO_8197F) << BIT_SHIFT_XTAL_CAP_XO_8197F) -#define BITS_XTAL_CAP_XO_8197F (BIT_MASK_XTAL_CAP_XO_8197F << BIT_SHIFT_XTAL_CAP_XO_8197F) +#define BIT_XTAL_CAP_XO_8197F(x) \ + (((x) & BIT_MASK_XTAL_CAP_XO_8197F) << BIT_SHIFT_XTAL_CAP_XO_8197F) +#define BITS_XTAL_CAP_XO_8197F \ + (BIT_MASK_XTAL_CAP_XO_8197F << BIT_SHIFT_XTAL_CAP_XO_8197F) #define BIT_CLEAR_XTAL_CAP_XO_8197F(x) ((x) & (~BITS_XTAL_CAP_XO_8197F)) -#define BIT_GET_XTAL_CAP_XO_8197F(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8197F) & BIT_MASK_XTAL_CAP_XO_8197F) -#define BIT_SET_XTAL_CAP_XO_8197F(x, v) (BIT_CLEAR_XTAL_CAP_XO_8197F(x) | BIT_XTAL_CAP_XO_8197F(v)) +#define BIT_GET_XTAL_CAP_XO_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XO_8197F) & BIT_MASK_XTAL_CAP_XO_8197F) +#define BIT_SET_XTAL_CAP_XO_8197F(x, v) \ + (BIT_CLEAR_XTAL_CAP_XO_8197F(x) | BIT_XTAL_CAP_XO_8197F(v)) #define BIT_POW_PLL_8197F BIT(0) @@ -441,11 +545,14 @@ #define BIT_SHIFT_PS_V2_8197F 7 #define BIT_MASK_PS_V2_8197F 0x7 -#define BIT_PS_V2_8197F(x) (((x) & BIT_MASK_PS_V2_8197F) << BIT_SHIFT_PS_V2_8197F) +#define BIT_PS_V2_8197F(x) \ + (((x) & BIT_MASK_PS_V2_8197F) << BIT_SHIFT_PS_V2_8197F) #define BITS_PS_V2_8197F (BIT_MASK_PS_V2_8197F << BIT_SHIFT_PS_V2_8197F) #define BIT_CLEAR_PS_V2_8197F(x) ((x) & (~BITS_PS_V2_8197F)) -#define BIT_GET_PS_V2_8197F(x) (((x) >> BIT_SHIFT_PS_V2_8197F) & BIT_MASK_PS_V2_8197F) -#define BIT_SET_PS_V2_8197F(x, v) (BIT_CLEAR_PS_V2_8197F(x) | BIT_PS_V2_8197F(v)) +#define BIT_GET_PS_V2_8197F(x) \ + (((x) >> BIT_SHIFT_PS_V2_8197F) & BIT_MASK_PS_V2_8197F) +#define BIT_SET_PS_V2_8197F(x, v) \ + (BIT_CLEAR_PS_V2_8197F(x) | BIT_PS_V2_8197F(v)) #define BIT_PSEN_8197F BIT(6) #define BIT_DOGENB_8197F BIT(5) @@ -455,127 +562,168 @@ #define BIT_SHIFT_EF_PGPD_8197F 28 #define BIT_MASK_EF_PGPD_8197F 0x7 -#define BIT_EF_PGPD_8197F(x) (((x) & BIT_MASK_EF_PGPD_8197F) << BIT_SHIFT_EF_PGPD_8197F) +#define BIT_EF_PGPD_8197F(x) \ + (((x) & BIT_MASK_EF_PGPD_8197F) << BIT_SHIFT_EF_PGPD_8197F) #define BITS_EF_PGPD_8197F (BIT_MASK_EF_PGPD_8197F << BIT_SHIFT_EF_PGPD_8197F) #define BIT_CLEAR_EF_PGPD_8197F(x) ((x) & (~BITS_EF_PGPD_8197F)) -#define BIT_GET_EF_PGPD_8197F(x) (((x) >> BIT_SHIFT_EF_PGPD_8197F) & BIT_MASK_EF_PGPD_8197F) -#define BIT_SET_EF_PGPD_8197F(x, v) (BIT_CLEAR_EF_PGPD_8197F(x) | BIT_EF_PGPD_8197F(v)) - +#define BIT_GET_EF_PGPD_8197F(x) \ + (((x) >> BIT_SHIFT_EF_PGPD_8197F) & BIT_MASK_EF_PGPD_8197F) +#define BIT_SET_EF_PGPD_8197F(x, v) \ + (BIT_CLEAR_EF_PGPD_8197F(x) | BIT_EF_PGPD_8197F(v)) #define BIT_SHIFT_EF_RDT_8197F 24 #define BIT_MASK_EF_RDT_8197F 0xf -#define BIT_EF_RDT_8197F(x) (((x) & BIT_MASK_EF_RDT_8197F) << BIT_SHIFT_EF_RDT_8197F) +#define BIT_EF_RDT_8197F(x) \ + (((x) & BIT_MASK_EF_RDT_8197F) << BIT_SHIFT_EF_RDT_8197F) #define BITS_EF_RDT_8197F (BIT_MASK_EF_RDT_8197F << BIT_SHIFT_EF_RDT_8197F) #define BIT_CLEAR_EF_RDT_8197F(x) ((x) & (~BITS_EF_RDT_8197F)) -#define BIT_GET_EF_RDT_8197F(x) (((x) >> BIT_SHIFT_EF_RDT_8197F) & BIT_MASK_EF_RDT_8197F) -#define BIT_SET_EF_RDT_8197F(x, v) (BIT_CLEAR_EF_RDT_8197F(x) | BIT_EF_RDT_8197F(v)) - +#define BIT_GET_EF_RDT_8197F(x) \ + (((x) >> BIT_SHIFT_EF_RDT_8197F) & BIT_MASK_EF_RDT_8197F) +#define BIT_SET_EF_RDT_8197F(x, v) \ + (BIT_CLEAR_EF_RDT_8197F(x) | BIT_EF_RDT_8197F(v)) #define BIT_SHIFT_EF_PGTS_8197F 20 #define BIT_MASK_EF_PGTS_8197F 0xf -#define BIT_EF_PGTS_8197F(x) (((x) & BIT_MASK_EF_PGTS_8197F) << BIT_SHIFT_EF_PGTS_8197F) +#define BIT_EF_PGTS_8197F(x) \ + (((x) & BIT_MASK_EF_PGTS_8197F) << BIT_SHIFT_EF_PGTS_8197F) #define BITS_EF_PGTS_8197F (BIT_MASK_EF_PGTS_8197F << BIT_SHIFT_EF_PGTS_8197F) #define BIT_CLEAR_EF_PGTS_8197F(x) ((x) & (~BITS_EF_PGTS_8197F)) -#define BIT_GET_EF_PGTS_8197F(x) (((x) >> BIT_SHIFT_EF_PGTS_8197F) & BIT_MASK_EF_PGTS_8197F) -#define BIT_SET_EF_PGTS_8197F(x, v) (BIT_CLEAR_EF_PGTS_8197F(x) | BIT_EF_PGTS_8197F(v)) +#define BIT_GET_EF_PGTS_8197F(x) \ + (((x) >> BIT_SHIFT_EF_PGTS_8197F) & BIT_MASK_EF_PGTS_8197F) +#define BIT_SET_EF_PGTS_8197F(x, v) \ + (BIT_CLEAR_EF_PGTS_8197F(x) | BIT_EF_PGTS_8197F(v)) #define BIT_EF_PDWN_8197F BIT(19) #define BIT_EF_ALDEN_8197F BIT(18) #define BIT_SHIFT_EF_ADDR_8197F 8 #define BIT_MASK_EF_ADDR_8197F 0x3ff -#define BIT_EF_ADDR_8197F(x) (((x) & BIT_MASK_EF_ADDR_8197F) << BIT_SHIFT_EF_ADDR_8197F) +#define BIT_EF_ADDR_8197F(x) \ + (((x) & BIT_MASK_EF_ADDR_8197F) << BIT_SHIFT_EF_ADDR_8197F) #define BITS_EF_ADDR_8197F (BIT_MASK_EF_ADDR_8197F << BIT_SHIFT_EF_ADDR_8197F) #define BIT_CLEAR_EF_ADDR_8197F(x) ((x) & (~BITS_EF_ADDR_8197F)) -#define BIT_GET_EF_ADDR_8197F(x) (((x) >> BIT_SHIFT_EF_ADDR_8197F) & BIT_MASK_EF_ADDR_8197F) -#define BIT_SET_EF_ADDR_8197F(x, v) (BIT_CLEAR_EF_ADDR_8197F(x) | BIT_EF_ADDR_8197F(v)) - +#define BIT_GET_EF_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_EF_ADDR_8197F) & BIT_MASK_EF_ADDR_8197F) +#define BIT_SET_EF_ADDR_8197F(x, v) \ + (BIT_CLEAR_EF_ADDR_8197F(x) | BIT_EF_ADDR_8197F(v)) #define BIT_SHIFT_EF_DATA_8197F 0 #define BIT_MASK_EF_DATA_8197F 0xff -#define BIT_EF_DATA_8197F(x) (((x) & BIT_MASK_EF_DATA_8197F) << BIT_SHIFT_EF_DATA_8197F) +#define BIT_EF_DATA_8197F(x) \ + (((x) & BIT_MASK_EF_DATA_8197F) << BIT_SHIFT_EF_DATA_8197F) #define BITS_EF_DATA_8197F (BIT_MASK_EF_DATA_8197F << BIT_SHIFT_EF_DATA_8197F) #define BIT_CLEAR_EF_DATA_8197F(x) ((x) & (~BITS_EF_DATA_8197F)) -#define BIT_GET_EF_DATA_8197F(x) (((x) >> BIT_SHIFT_EF_DATA_8197F) & BIT_MASK_EF_DATA_8197F) -#define BIT_SET_EF_DATA_8197F(x, v) (BIT_CLEAR_EF_DATA_8197F(x) | BIT_EF_DATA_8197F(v)) - +#define BIT_GET_EF_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_EF_DATA_8197F) & BIT_MASK_EF_DATA_8197F) +#define BIT_SET_EF_DATA_8197F(x, v) \ + (BIT_CLEAR_EF_DATA_8197F(x) | BIT_EF_DATA_8197F(v)) /* 2 REG_LDO_EFUSE_CTRL_8197F */ #define BIT_LDOE25_EN_8197F BIT(31) #define BIT_SHIFT_LDOE25_V12ADJ_L_8197F 27 #define BIT_MASK_LDOE25_V12ADJ_L_8197F 0xf -#define BIT_LDOE25_V12ADJ_L_8197F(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8197F) << BIT_SHIFT_LDOE25_V12ADJ_L_8197F) -#define BITS_LDOE25_V12ADJ_L_8197F (BIT_MASK_LDOE25_V12ADJ_L_8197F << BIT_SHIFT_LDOE25_V12ADJ_L_8197F) +#define BIT_LDOE25_V12ADJ_L_8197F(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L_8197F) \ + << BIT_SHIFT_LDOE25_V12ADJ_L_8197F) +#define BITS_LDOE25_V12ADJ_L_8197F \ + (BIT_MASK_LDOE25_V12ADJ_L_8197F << BIT_SHIFT_LDOE25_V12ADJ_L_8197F) #define BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8197F)) -#define BIT_GET_LDOE25_V12ADJ_L_8197F(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8197F) & BIT_MASK_LDOE25_V12ADJ_L_8197F) -#define BIT_SET_LDOE25_V12ADJ_L_8197F(x, v) (BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) | BIT_LDOE25_V12ADJ_L_8197F(v)) - +#define BIT_GET_LDOE25_V12ADJ_L_8197F(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8197F) & \ + BIT_MASK_LDOE25_V12ADJ_L_8197F) +#define BIT_SET_LDOE25_V12ADJ_L_8197F(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) | BIT_LDOE25_V12ADJ_L_8197F(v)) #define BIT_SHIFT_EF_SCAN_START_V1_8197F 16 #define BIT_MASK_EF_SCAN_START_V1_8197F 0x3ff -#define BIT_EF_SCAN_START_V1_8197F(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8197F) << BIT_SHIFT_EF_SCAN_START_V1_8197F) -#define BITS_EF_SCAN_START_V1_8197F (BIT_MASK_EF_SCAN_START_V1_8197F << BIT_SHIFT_EF_SCAN_START_V1_8197F) -#define BIT_CLEAR_EF_SCAN_START_V1_8197F(x) ((x) & (~BITS_EF_SCAN_START_V1_8197F)) -#define BIT_GET_EF_SCAN_START_V1_8197F(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8197F) & BIT_MASK_EF_SCAN_START_V1_8197F) -#define BIT_SET_EF_SCAN_START_V1_8197F(x, v) (BIT_CLEAR_EF_SCAN_START_V1_8197F(x) | BIT_EF_SCAN_START_V1_8197F(v)) - +#define BIT_EF_SCAN_START_V1_8197F(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1_8197F) \ + << BIT_SHIFT_EF_SCAN_START_V1_8197F) +#define BITS_EF_SCAN_START_V1_8197F \ + (BIT_MASK_EF_SCAN_START_V1_8197F << BIT_SHIFT_EF_SCAN_START_V1_8197F) +#define BIT_CLEAR_EF_SCAN_START_V1_8197F(x) \ + ((x) & (~BITS_EF_SCAN_START_V1_8197F)) +#define BIT_GET_EF_SCAN_START_V1_8197F(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8197F) & \ + BIT_MASK_EF_SCAN_START_V1_8197F) +#define BIT_SET_EF_SCAN_START_V1_8197F(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1_8197F(x) | BIT_EF_SCAN_START_V1_8197F(v)) #define BIT_SHIFT_EF_SCAN_END_8197F 12 #define BIT_MASK_EF_SCAN_END_8197F 0xf -#define BIT_EF_SCAN_END_8197F(x) (((x) & BIT_MASK_EF_SCAN_END_8197F) << BIT_SHIFT_EF_SCAN_END_8197F) -#define BITS_EF_SCAN_END_8197F (BIT_MASK_EF_SCAN_END_8197F << BIT_SHIFT_EF_SCAN_END_8197F) +#define BIT_EF_SCAN_END_8197F(x) \ + (((x) & BIT_MASK_EF_SCAN_END_8197F) << BIT_SHIFT_EF_SCAN_END_8197F) +#define BITS_EF_SCAN_END_8197F \ + (BIT_MASK_EF_SCAN_END_8197F << BIT_SHIFT_EF_SCAN_END_8197F) #define BIT_CLEAR_EF_SCAN_END_8197F(x) ((x) & (~BITS_EF_SCAN_END_8197F)) -#define BIT_GET_EF_SCAN_END_8197F(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8197F) & BIT_MASK_EF_SCAN_END_8197F) -#define BIT_SET_EF_SCAN_END_8197F(x, v) (BIT_CLEAR_EF_SCAN_END_8197F(x) | BIT_EF_SCAN_END_8197F(v)) - +#define BIT_GET_EF_SCAN_END_8197F(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END_8197F) & BIT_MASK_EF_SCAN_END_8197F) +#define BIT_SET_EF_SCAN_END_8197F(x, v) \ + (BIT_CLEAR_EF_SCAN_END_8197F(x) | BIT_EF_SCAN_END_8197F(v)) #define BIT_SHIFT_EF_CELL_SEL_8197F 8 #define BIT_MASK_EF_CELL_SEL_8197F 0x3 -#define BIT_EF_CELL_SEL_8197F(x) (((x) & BIT_MASK_EF_CELL_SEL_8197F) << BIT_SHIFT_EF_CELL_SEL_8197F) -#define BITS_EF_CELL_SEL_8197F (BIT_MASK_EF_CELL_SEL_8197F << BIT_SHIFT_EF_CELL_SEL_8197F) +#define BIT_EF_CELL_SEL_8197F(x) \ + (((x) & BIT_MASK_EF_CELL_SEL_8197F) << BIT_SHIFT_EF_CELL_SEL_8197F) +#define BITS_EF_CELL_SEL_8197F \ + (BIT_MASK_EF_CELL_SEL_8197F << BIT_SHIFT_EF_CELL_SEL_8197F) #define BIT_CLEAR_EF_CELL_SEL_8197F(x) ((x) & (~BITS_EF_CELL_SEL_8197F)) -#define BIT_GET_EF_CELL_SEL_8197F(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8197F) & BIT_MASK_EF_CELL_SEL_8197F) -#define BIT_SET_EF_CELL_SEL_8197F(x, v) (BIT_CLEAR_EF_CELL_SEL_8197F(x) | BIT_EF_CELL_SEL_8197F(v)) +#define BIT_GET_EF_CELL_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL_8197F) & BIT_MASK_EF_CELL_SEL_8197F) +#define BIT_SET_EF_CELL_SEL_8197F(x, v) \ + (BIT_CLEAR_EF_CELL_SEL_8197F(x) | BIT_EF_CELL_SEL_8197F(v)) #define BIT_EF_TRPT_8197F BIT(7) #define BIT_SHIFT_EF_TTHD_8197F 0 #define BIT_MASK_EF_TTHD_8197F 0x7f -#define BIT_EF_TTHD_8197F(x) (((x) & BIT_MASK_EF_TTHD_8197F) << BIT_SHIFT_EF_TTHD_8197F) +#define BIT_EF_TTHD_8197F(x) \ + (((x) & BIT_MASK_EF_TTHD_8197F) << BIT_SHIFT_EF_TTHD_8197F) #define BITS_EF_TTHD_8197F (BIT_MASK_EF_TTHD_8197F << BIT_SHIFT_EF_TTHD_8197F) #define BIT_CLEAR_EF_TTHD_8197F(x) ((x) & (~BITS_EF_TTHD_8197F)) -#define BIT_GET_EF_TTHD_8197F(x) (((x) >> BIT_SHIFT_EF_TTHD_8197F) & BIT_MASK_EF_TTHD_8197F) -#define BIT_SET_EF_TTHD_8197F(x, v) (BIT_CLEAR_EF_TTHD_8197F(x) | BIT_EF_TTHD_8197F(v)) - +#define BIT_GET_EF_TTHD_8197F(x) \ + (((x) >> BIT_SHIFT_EF_TTHD_8197F) & BIT_MASK_EF_TTHD_8197F) +#define BIT_SET_EF_TTHD_8197F(x, v) \ + (BIT_CLEAR_EF_TTHD_8197F(x) | BIT_EF_TTHD_8197F(v)) /* 2 REG_PWR_OPTION_CTRL_8197F */ #define BIT_SHIFT_DBG_SEL_V1_8197F 16 #define BIT_MASK_DBG_SEL_V1_8197F 0xff -#define BIT_DBG_SEL_V1_8197F(x) (((x) & BIT_MASK_DBG_SEL_V1_8197F) << BIT_SHIFT_DBG_SEL_V1_8197F) -#define BITS_DBG_SEL_V1_8197F (BIT_MASK_DBG_SEL_V1_8197F << BIT_SHIFT_DBG_SEL_V1_8197F) +#define BIT_DBG_SEL_V1_8197F(x) \ + (((x) & BIT_MASK_DBG_SEL_V1_8197F) << BIT_SHIFT_DBG_SEL_V1_8197F) +#define BITS_DBG_SEL_V1_8197F \ + (BIT_MASK_DBG_SEL_V1_8197F << BIT_SHIFT_DBG_SEL_V1_8197F) #define BIT_CLEAR_DBG_SEL_V1_8197F(x) ((x) & (~BITS_DBG_SEL_V1_8197F)) -#define BIT_GET_DBG_SEL_V1_8197F(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8197F) & BIT_MASK_DBG_SEL_V1_8197F) -#define BIT_SET_DBG_SEL_V1_8197F(x, v) (BIT_CLEAR_DBG_SEL_V1_8197F(x) | BIT_DBG_SEL_V1_8197F(v)) - +#define BIT_GET_DBG_SEL_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1_8197F) & BIT_MASK_DBG_SEL_V1_8197F) +#define BIT_SET_DBG_SEL_V1_8197F(x, v) \ + (BIT_CLEAR_DBG_SEL_V1_8197F(x) | BIT_DBG_SEL_V1_8197F(v)) #define BIT_SHIFT_DBG_SEL_BYTE_8197F 14 #define BIT_MASK_DBG_SEL_BYTE_8197F 0x3 -#define BIT_DBG_SEL_BYTE_8197F(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8197F) << BIT_SHIFT_DBG_SEL_BYTE_8197F) -#define BITS_DBG_SEL_BYTE_8197F (BIT_MASK_DBG_SEL_BYTE_8197F << BIT_SHIFT_DBG_SEL_BYTE_8197F) +#define BIT_DBG_SEL_BYTE_8197F(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE_8197F) << BIT_SHIFT_DBG_SEL_BYTE_8197F) +#define BITS_DBG_SEL_BYTE_8197F \ + (BIT_MASK_DBG_SEL_BYTE_8197F << BIT_SHIFT_DBG_SEL_BYTE_8197F) #define BIT_CLEAR_DBG_SEL_BYTE_8197F(x) ((x) & (~BITS_DBG_SEL_BYTE_8197F)) -#define BIT_GET_DBG_SEL_BYTE_8197F(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8197F) & BIT_MASK_DBG_SEL_BYTE_8197F) -#define BIT_SET_DBG_SEL_BYTE_8197F(x, v) (BIT_CLEAR_DBG_SEL_BYTE_8197F(x) | BIT_DBG_SEL_BYTE_8197F(v)) - +#define BIT_GET_DBG_SEL_BYTE_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8197F) & BIT_MASK_DBG_SEL_BYTE_8197F) +#define BIT_SET_DBG_SEL_BYTE_8197F(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE_8197F(x) | BIT_DBG_SEL_BYTE_8197F(v)) #define BIT_SHIFT_STD_L1_V1_8197F 12 #define BIT_MASK_STD_L1_V1_8197F 0x3 -#define BIT_STD_L1_V1_8197F(x) (((x) & BIT_MASK_STD_L1_V1_8197F) << BIT_SHIFT_STD_L1_V1_8197F) -#define BITS_STD_L1_V1_8197F (BIT_MASK_STD_L1_V1_8197F << BIT_SHIFT_STD_L1_V1_8197F) +#define BIT_STD_L1_V1_8197F(x) \ + (((x) & BIT_MASK_STD_L1_V1_8197F) << BIT_SHIFT_STD_L1_V1_8197F) +#define BITS_STD_L1_V1_8197F \ + (BIT_MASK_STD_L1_V1_8197F << BIT_SHIFT_STD_L1_V1_8197F) #define BIT_CLEAR_STD_L1_V1_8197F(x) ((x) & (~BITS_STD_L1_V1_8197F)) -#define BIT_GET_STD_L1_V1_8197F(x) (((x) >> BIT_SHIFT_STD_L1_V1_8197F) & BIT_MASK_STD_L1_V1_8197F) -#define BIT_SET_STD_L1_V1_8197F(x, v) (BIT_CLEAR_STD_L1_V1_8197F(x) | BIT_STD_L1_V1_8197F(v)) +#define BIT_GET_STD_L1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_STD_L1_V1_8197F) & BIT_MASK_STD_L1_V1_8197F) +#define BIT_SET_STD_L1_V1_8197F(x, v) \ + (BIT_CLEAR_STD_L1_V1_8197F(x) | BIT_STD_L1_V1_8197F(v)) #define BIT_SYSON_DBG_PAD_E2_8197F BIT(11) #define BIT_SYSON_LED_PAD_E2_8197F BIT(10) @@ -585,70 +733,101 @@ #define BIT_SHIFT_SYSON_SPS0WWV_WT_8197F 4 #define BIT_MASK_SYSON_SPS0WWV_WT_8197F 0x3 -#define BIT_SYSON_SPS0WWV_WT_8197F(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8197F) << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) -#define BITS_SYSON_SPS0WWV_WT_8197F (BIT_MASK_SYSON_SPS0WWV_WT_8197F << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) -#define BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) ((x) & (~BITS_SYSON_SPS0WWV_WT_8197F)) -#define BIT_GET_SYSON_SPS0WWV_WT_8197F(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) & BIT_MASK_SYSON_SPS0WWV_WT_8197F) -#define BIT_SET_SYSON_SPS0WWV_WT_8197F(x, v) (BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) | BIT_SYSON_SPS0WWV_WT_8197F(v)) - +#define BIT_SYSON_SPS0WWV_WT_8197F(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8197F) \ + << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) +#define BITS_SYSON_SPS0WWV_WT_8197F \ + (BIT_MASK_SYSON_SPS0WWV_WT_8197F << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) +#define BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) \ + ((x) & (~BITS_SYSON_SPS0WWV_WT_8197F)) +#define BIT_GET_SYSON_SPS0WWV_WT_8197F(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) & \ + BIT_MASK_SYSON_SPS0WWV_WT_8197F) +#define BIT_SET_SYSON_SPS0WWV_WT_8197F(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) | BIT_SYSON_SPS0WWV_WT_8197F(v)) #define BIT_SHIFT_SYSON_SPS0LDO_WT_8197F 2 #define BIT_MASK_SYSON_SPS0LDO_WT_8197F 0x3 -#define BIT_SYSON_SPS0LDO_WT_8197F(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8197F) << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) -#define BITS_SYSON_SPS0LDO_WT_8197F (BIT_MASK_SYSON_SPS0LDO_WT_8197F << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) -#define BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) ((x) & (~BITS_SYSON_SPS0LDO_WT_8197F)) -#define BIT_GET_SYSON_SPS0LDO_WT_8197F(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) & BIT_MASK_SYSON_SPS0LDO_WT_8197F) -#define BIT_SET_SYSON_SPS0LDO_WT_8197F(x, v) (BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) | BIT_SYSON_SPS0LDO_WT_8197F(v)) - +#define BIT_SYSON_SPS0LDO_WT_8197F(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8197F) \ + << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) +#define BITS_SYSON_SPS0LDO_WT_8197F \ + (BIT_MASK_SYSON_SPS0LDO_WT_8197F << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) +#define BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) \ + ((x) & (~BITS_SYSON_SPS0LDO_WT_8197F)) +#define BIT_GET_SYSON_SPS0LDO_WT_8197F(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) & \ + BIT_MASK_SYSON_SPS0LDO_WT_8197F) +#define BIT_SET_SYSON_SPS0LDO_WT_8197F(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) | BIT_SYSON_SPS0LDO_WT_8197F(v)) #define BIT_SHIFT_SYSON_RCLK_SCALE_8197F 0 #define BIT_MASK_SYSON_RCLK_SCALE_8197F 0x3 -#define BIT_SYSON_RCLK_SCALE_8197F(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8197F) << BIT_SHIFT_SYSON_RCLK_SCALE_8197F) -#define BITS_SYSON_RCLK_SCALE_8197F (BIT_MASK_SYSON_RCLK_SCALE_8197F << BIT_SHIFT_SYSON_RCLK_SCALE_8197F) -#define BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) ((x) & (~BITS_SYSON_RCLK_SCALE_8197F)) -#define BIT_GET_SYSON_RCLK_SCALE_8197F(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8197F) & BIT_MASK_SYSON_RCLK_SCALE_8197F) -#define BIT_SET_SYSON_RCLK_SCALE_8197F(x, v) (BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) | BIT_SYSON_RCLK_SCALE_8197F(v)) - +#define BIT_SYSON_RCLK_SCALE_8197F(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE_8197F) \ + << BIT_SHIFT_SYSON_RCLK_SCALE_8197F) +#define BITS_SYSON_RCLK_SCALE_8197F \ + (BIT_MASK_SYSON_RCLK_SCALE_8197F << BIT_SHIFT_SYSON_RCLK_SCALE_8197F) +#define BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) \ + ((x) & (~BITS_SYSON_RCLK_SCALE_8197F)) +#define BIT_GET_SYSON_RCLK_SCALE_8197F(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8197F) & \ + BIT_MASK_SYSON_RCLK_SCALE_8197F) +#define BIT_SET_SYSON_RCLK_SCALE_8197F(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) | BIT_SYSON_RCLK_SCALE_8197F(v)) /* 2 REG_CAL_TIMER_8197F */ #define BIT_SHIFT_MATCH_CNT_8197F 8 #define BIT_MASK_MATCH_CNT_8197F 0xff -#define BIT_MATCH_CNT_8197F(x) (((x) & BIT_MASK_MATCH_CNT_8197F) << BIT_SHIFT_MATCH_CNT_8197F) -#define BITS_MATCH_CNT_8197F (BIT_MASK_MATCH_CNT_8197F << BIT_SHIFT_MATCH_CNT_8197F) +#define BIT_MATCH_CNT_8197F(x) \ + (((x) & BIT_MASK_MATCH_CNT_8197F) << BIT_SHIFT_MATCH_CNT_8197F) +#define BITS_MATCH_CNT_8197F \ + (BIT_MASK_MATCH_CNT_8197F << BIT_SHIFT_MATCH_CNT_8197F) #define BIT_CLEAR_MATCH_CNT_8197F(x) ((x) & (~BITS_MATCH_CNT_8197F)) -#define BIT_GET_MATCH_CNT_8197F(x) (((x) >> BIT_SHIFT_MATCH_CNT_8197F) & BIT_MASK_MATCH_CNT_8197F) -#define BIT_SET_MATCH_CNT_8197F(x, v) (BIT_CLEAR_MATCH_CNT_8197F(x) | BIT_MATCH_CNT_8197F(v)) - +#define BIT_GET_MATCH_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8197F) & BIT_MASK_MATCH_CNT_8197F) +#define BIT_SET_MATCH_CNT_8197F(x, v) \ + (BIT_CLEAR_MATCH_CNT_8197F(x) | BIT_MATCH_CNT_8197F(v)) #define BIT_SHIFT_CAL_SCAL_8197F 0 #define BIT_MASK_CAL_SCAL_8197F 0xff -#define BIT_CAL_SCAL_8197F(x) (((x) & BIT_MASK_CAL_SCAL_8197F) << BIT_SHIFT_CAL_SCAL_8197F) -#define BITS_CAL_SCAL_8197F (BIT_MASK_CAL_SCAL_8197F << BIT_SHIFT_CAL_SCAL_8197F) +#define BIT_CAL_SCAL_8197F(x) \ + (((x) & BIT_MASK_CAL_SCAL_8197F) << BIT_SHIFT_CAL_SCAL_8197F) +#define BITS_CAL_SCAL_8197F \ + (BIT_MASK_CAL_SCAL_8197F << BIT_SHIFT_CAL_SCAL_8197F) #define BIT_CLEAR_CAL_SCAL_8197F(x) ((x) & (~BITS_CAL_SCAL_8197F)) -#define BIT_GET_CAL_SCAL_8197F(x) (((x) >> BIT_SHIFT_CAL_SCAL_8197F) & BIT_MASK_CAL_SCAL_8197F) -#define BIT_SET_CAL_SCAL_8197F(x, v) (BIT_CLEAR_CAL_SCAL_8197F(x) | BIT_CAL_SCAL_8197F(v)) - +#define BIT_GET_CAL_SCAL_8197F(x) \ + (((x) >> BIT_SHIFT_CAL_SCAL_8197F) & BIT_MASK_CAL_SCAL_8197F) +#define BIT_SET_CAL_SCAL_8197F(x, v) \ + (BIT_CLEAR_CAL_SCAL_8197F(x) | BIT_CAL_SCAL_8197F(v)) /* 2 REG_ACLK_MON_8197F */ #define BIT_SHIFT_RCLK_MON_8197F 5 #define BIT_MASK_RCLK_MON_8197F 0x7ff -#define BIT_RCLK_MON_8197F(x) (((x) & BIT_MASK_RCLK_MON_8197F) << BIT_SHIFT_RCLK_MON_8197F) -#define BITS_RCLK_MON_8197F (BIT_MASK_RCLK_MON_8197F << BIT_SHIFT_RCLK_MON_8197F) +#define BIT_RCLK_MON_8197F(x) \ + (((x) & BIT_MASK_RCLK_MON_8197F) << BIT_SHIFT_RCLK_MON_8197F) +#define BITS_RCLK_MON_8197F \ + (BIT_MASK_RCLK_MON_8197F << BIT_SHIFT_RCLK_MON_8197F) #define BIT_CLEAR_RCLK_MON_8197F(x) ((x) & (~BITS_RCLK_MON_8197F)) -#define BIT_GET_RCLK_MON_8197F(x) (((x) >> BIT_SHIFT_RCLK_MON_8197F) & BIT_MASK_RCLK_MON_8197F) -#define BIT_SET_RCLK_MON_8197F(x, v) (BIT_CLEAR_RCLK_MON_8197F(x) | BIT_RCLK_MON_8197F(v)) +#define BIT_GET_RCLK_MON_8197F(x) \ + (((x) >> BIT_SHIFT_RCLK_MON_8197F) & BIT_MASK_RCLK_MON_8197F) +#define BIT_SET_RCLK_MON_8197F(x, v) \ + (BIT_CLEAR_RCLK_MON_8197F(x) | BIT_RCLK_MON_8197F(v)) #define BIT_CAL_EN_8197F BIT(4) #define BIT_SHIFT_DPSTU_8197F 2 #define BIT_MASK_DPSTU_8197F 0x3 -#define BIT_DPSTU_8197F(x) (((x) & BIT_MASK_DPSTU_8197F) << BIT_SHIFT_DPSTU_8197F) +#define BIT_DPSTU_8197F(x) \ + (((x) & BIT_MASK_DPSTU_8197F) << BIT_SHIFT_DPSTU_8197F) #define BITS_DPSTU_8197F (BIT_MASK_DPSTU_8197F << BIT_SHIFT_DPSTU_8197F) #define BIT_CLEAR_DPSTU_8197F(x) ((x) & (~BITS_DPSTU_8197F)) -#define BIT_GET_DPSTU_8197F(x) (((x) >> BIT_SHIFT_DPSTU_8197F) & BIT_MASK_DPSTU_8197F) -#define BIT_SET_DPSTU_8197F(x, v) (BIT_CLEAR_DPSTU_8197F(x) | BIT_DPSTU_8197F(v)) +#define BIT_GET_DPSTU_8197F(x) \ + (((x) >> BIT_SHIFT_DPSTU_8197F) & BIT_MASK_DPSTU_8197F) +#define BIT_SET_DPSTU_8197F(x, v) \ + (BIT_CLEAR_DPSTU_8197F(x) | BIT_DPSTU_8197F(v)) #define BIT_SUS_16X_8197F BIT(1) @@ -659,11 +838,15 @@ #define BIT_SHIFT_PIN_USECASE_8197F 24 #define BIT_MASK_PIN_USECASE_8197F 0xf -#define BIT_PIN_USECASE_8197F(x) (((x) & BIT_MASK_PIN_USECASE_8197F) << BIT_SHIFT_PIN_USECASE_8197F) -#define BITS_PIN_USECASE_8197F (BIT_MASK_PIN_USECASE_8197F << BIT_SHIFT_PIN_USECASE_8197F) +#define BIT_PIN_USECASE_8197F(x) \ + (((x) & BIT_MASK_PIN_USECASE_8197F) << BIT_SHIFT_PIN_USECASE_8197F) +#define BITS_PIN_USECASE_8197F \ + (BIT_MASK_PIN_USECASE_8197F << BIT_SHIFT_PIN_USECASE_8197F) #define BIT_CLEAR_PIN_USECASE_8197F(x) ((x) & (~BITS_PIN_USECASE_8197F)) -#define BIT_GET_PIN_USECASE_8197F(x) (((x) >> BIT_SHIFT_PIN_USECASE_8197F) & BIT_MASK_PIN_USECASE_8197F) -#define BIT_SET_PIN_USECASE_8197F(x, v) (BIT_CLEAR_PIN_USECASE_8197F(x) | BIT_PIN_USECASE_8197F(v)) +#define BIT_GET_PIN_USECASE_8197F(x) \ + (((x) >> BIT_SHIFT_PIN_USECASE_8197F) & BIT_MASK_PIN_USECASE_8197F) +#define BIT_SET_PIN_USECASE_8197F(x, v) \ + (BIT_CLEAR_PIN_USECASE_8197F(x) | BIT_PIN_USECASE_8197F(v)) #define BIT_FSPI_EN_8197F BIT(19) #define BIT_WL_RTS_EXT_32K_SEL_8197F BIT(18) @@ -679,11 +862,14 @@ #define BIT_SHIFT_BTMODE_8197F 6 #define BIT_MASK_BTMODE_8197F 0x3 -#define BIT_BTMODE_8197F(x) (((x) & BIT_MASK_BTMODE_8197F) << BIT_SHIFT_BTMODE_8197F) +#define BIT_BTMODE_8197F(x) \ + (((x) & BIT_MASK_BTMODE_8197F) << BIT_SHIFT_BTMODE_8197F) #define BITS_BTMODE_8197F (BIT_MASK_BTMODE_8197F << BIT_SHIFT_BTMODE_8197F) #define BIT_CLEAR_BTMODE_8197F(x) ((x) & (~BITS_BTMODE_8197F)) -#define BIT_GET_BTMODE_8197F(x) (((x) >> BIT_SHIFT_BTMODE_8197F) & BIT_MASK_BTMODE_8197F) -#define BIT_SET_BTMODE_8197F(x, v) (BIT_CLEAR_BTMODE_8197F(x) | BIT_BTMODE_8197F(v)) +#define BIT_GET_BTMODE_8197F(x) \ + (((x) >> BIT_SHIFT_BTMODE_8197F) & BIT_MASK_BTMODE_8197F) +#define BIT_SET_BTMODE_8197F(x, v) \ + (BIT_CLEAR_BTMODE_8197F(x) | BIT_BTMODE_8197F(v)) #define BIT_ENBT_8197F BIT(5) #define BIT_EROM_EN_8197F BIT(4) @@ -692,60 +878,89 @@ #define BIT_SHIFT_GPIOSEL_8197F 0 #define BIT_MASK_GPIOSEL_8197F 0x3 -#define BIT_GPIOSEL_8197F(x) (((x) & BIT_MASK_GPIOSEL_8197F) << BIT_SHIFT_GPIOSEL_8197F) +#define BIT_GPIOSEL_8197F(x) \ + (((x) & BIT_MASK_GPIOSEL_8197F) << BIT_SHIFT_GPIOSEL_8197F) #define BITS_GPIOSEL_8197F (BIT_MASK_GPIOSEL_8197F << BIT_SHIFT_GPIOSEL_8197F) #define BIT_CLEAR_GPIOSEL_8197F(x) ((x) & (~BITS_GPIOSEL_8197F)) -#define BIT_GET_GPIOSEL_8197F(x) (((x) >> BIT_SHIFT_GPIOSEL_8197F) & BIT_MASK_GPIOSEL_8197F) -#define BIT_SET_GPIOSEL_8197F(x, v) (BIT_CLEAR_GPIOSEL_8197F(x) | BIT_GPIOSEL_8197F(v)) - +#define BIT_GET_GPIOSEL_8197F(x) \ + (((x) >> BIT_SHIFT_GPIOSEL_8197F) & BIT_MASK_GPIOSEL_8197F) +#define BIT_SET_GPIOSEL_8197F(x, v) \ + (BIT_CLEAR_GPIOSEL_8197F(x) | BIT_GPIOSEL_8197F(v)) /* 2 REG_GPIO_PIN_CTRL_8197F */ #define BIT_SHIFT_GPIO_MOD_7_TO_0_8197F 24 #define BIT_MASK_GPIO_MOD_7_TO_0_8197F 0xff -#define BIT_GPIO_MOD_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8197F) << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) -#define BITS_GPIO_MOD_7_TO_0_8197F (BIT_MASK_GPIO_MOD_7_TO_0_8197F << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) +#define BIT_GPIO_MOD_7_TO_0_8197F(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8197F) \ + << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) +#define BITS_GPIO_MOD_7_TO_0_8197F \ + (BIT_MASK_GPIO_MOD_7_TO_0_8197F << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) #define BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8197F)) -#define BIT_GET_GPIO_MOD_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) & BIT_MASK_GPIO_MOD_7_TO_0_8197F) -#define BIT_SET_GPIO_MOD_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) | BIT_GPIO_MOD_7_TO_0_8197F(v)) - +#define BIT_GET_GPIO_MOD_7_TO_0_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) & \ + BIT_MASK_GPIO_MOD_7_TO_0_8197F) +#define BIT_SET_GPIO_MOD_7_TO_0_8197F(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) | BIT_GPIO_MOD_7_TO_0_8197F(v)) #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F 16 #define BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F 0xff -#define BIT_GPIO_IO_SEL_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) -#define BITS_GPIO_IO_SEL_7_TO_0_8197F (BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) -#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8197F)) -#define BIT_GET_GPIO_IO_SEL_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F) -#define BIT_SET_GPIO_IO_SEL_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) | BIT_GPIO_IO_SEL_7_TO_0_8197F(v)) - +#define BIT_GPIO_IO_SEL_7_TO_0_8197F(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F) \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) +#define BITS_GPIO_IO_SEL_7_TO_0_8197F \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) \ + ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8197F)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) & \ + BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F) +#define BIT_SET_GPIO_IO_SEL_7_TO_0_8197F(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) | \ + BIT_GPIO_IO_SEL_7_TO_0_8197F(v)) #define BIT_SHIFT_GPIO_OUT_7_TO_0_8197F 8 #define BIT_MASK_GPIO_OUT_7_TO_0_8197F 0xff -#define BIT_GPIO_OUT_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8197F) << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) -#define BITS_GPIO_OUT_7_TO_0_8197F (BIT_MASK_GPIO_OUT_7_TO_0_8197F << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) +#define BIT_GPIO_OUT_7_TO_0_8197F(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8197F) \ + << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) +#define BITS_GPIO_OUT_7_TO_0_8197F \ + (BIT_MASK_GPIO_OUT_7_TO_0_8197F << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) #define BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8197F)) -#define BIT_GET_GPIO_OUT_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) & BIT_MASK_GPIO_OUT_7_TO_0_8197F) -#define BIT_SET_GPIO_OUT_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) | BIT_GPIO_OUT_7_TO_0_8197F(v)) - +#define BIT_GET_GPIO_OUT_7_TO_0_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) & \ + BIT_MASK_GPIO_OUT_7_TO_0_8197F) +#define BIT_SET_GPIO_OUT_7_TO_0_8197F(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) | BIT_GPIO_OUT_7_TO_0_8197F(v)) #define BIT_SHIFT_GPIO_IN_7_TO_0_8197F 0 #define BIT_MASK_GPIO_IN_7_TO_0_8197F 0xff -#define BIT_GPIO_IN_7_TO_0_8197F(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8197F) << BIT_SHIFT_GPIO_IN_7_TO_0_8197F) -#define BITS_GPIO_IN_7_TO_0_8197F (BIT_MASK_GPIO_IN_7_TO_0_8197F << BIT_SHIFT_GPIO_IN_7_TO_0_8197F) +#define BIT_GPIO_IN_7_TO_0_8197F(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0_8197F) \ + << BIT_SHIFT_GPIO_IN_7_TO_0_8197F) +#define BITS_GPIO_IN_7_TO_0_8197F \ + (BIT_MASK_GPIO_IN_7_TO_0_8197F << BIT_SHIFT_GPIO_IN_7_TO_0_8197F) #define BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8197F)) -#define BIT_GET_GPIO_IN_7_TO_0_8197F(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8197F) & BIT_MASK_GPIO_IN_7_TO_0_8197F) -#define BIT_SET_GPIO_IN_7_TO_0_8197F(x, v) (BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) | BIT_GPIO_IN_7_TO_0_8197F(v)) - +#define BIT_GET_GPIO_IN_7_TO_0_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8197F) & \ + BIT_MASK_GPIO_IN_7_TO_0_8197F) +#define BIT_SET_GPIO_IN_7_TO_0_8197F(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) | BIT_GPIO_IN_7_TO_0_8197F(v)) /* 2 REG_GPIO_INTM_8197F */ #define BIT_SHIFT_MUXDBG_SEL_8197F 30 #define BIT_MASK_MUXDBG_SEL_8197F 0x3 -#define BIT_MUXDBG_SEL_8197F(x) (((x) & BIT_MASK_MUXDBG_SEL_8197F) << BIT_SHIFT_MUXDBG_SEL_8197F) -#define BITS_MUXDBG_SEL_8197F (BIT_MASK_MUXDBG_SEL_8197F << BIT_SHIFT_MUXDBG_SEL_8197F) +#define BIT_MUXDBG_SEL_8197F(x) \ + (((x) & BIT_MASK_MUXDBG_SEL_8197F) << BIT_SHIFT_MUXDBG_SEL_8197F) +#define BITS_MUXDBG_SEL_8197F \ + (BIT_MASK_MUXDBG_SEL_8197F << BIT_SHIFT_MUXDBG_SEL_8197F) #define BIT_CLEAR_MUXDBG_SEL_8197F(x) ((x) & (~BITS_MUXDBG_SEL_8197F)) -#define BIT_GET_MUXDBG_SEL_8197F(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8197F) & BIT_MASK_MUXDBG_SEL_8197F) -#define BIT_SET_MUXDBG_SEL_8197F(x, v) (BIT_CLEAR_MUXDBG_SEL_8197F(x) | BIT_MUXDBG_SEL_8197F(v)) +#define BIT_GET_MUXDBG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL_8197F) & BIT_MASK_MUXDBG_SEL_8197F) +#define BIT_SET_MUXDBG_SEL_8197F(x, v) \ + (BIT_CLEAR_MUXDBG_SEL_8197F(x) | BIT_MUXDBG_SEL_8197F(v)) #define BIT_EXTWOL_SEL_8197F BIT(17) #define BIT_EXTWOL_EN_8197F BIT(16) @@ -778,11 +993,14 @@ #define BIT_SHIFT_LED2CM_8197F 16 #define BIT_MASK_LED2CM_8197F 0x7 -#define BIT_LED2CM_8197F(x) (((x) & BIT_MASK_LED2CM_8197F) << BIT_SHIFT_LED2CM_8197F) +#define BIT_LED2CM_8197F(x) \ + (((x) & BIT_MASK_LED2CM_8197F) << BIT_SHIFT_LED2CM_8197F) #define BITS_LED2CM_8197F (BIT_MASK_LED2CM_8197F << BIT_SHIFT_LED2CM_8197F) #define BIT_CLEAR_LED2CM_8197F(x) ((x) & (~BITS_LED2CM_8197F)) -#define BIT_GET_LED2CM_8197F(x) (((x) >> BIT_SHIFT_LED2CM_8197F) & BIT_MASK_LED2CM_8197F) -#define BIT_SET_LED2CM_8197F(x, v) (BIT_CLEAR_LED2CM_8197F(x) | BIT_LED2CM_8197F(v)) +#define BIT_GET_LED2CM_8197F(x) \ + (((x) >> BIT_SHIFT_LED2CM_8197F) & BIT_MASK_LED2CM_8197F) +#define BIT_SET_LED2CM_8197F(x, v) \ + (BIT_CLEAR_LED2CM_8197F(x) | BIT_LED2CM_8197F(v)) #define BIT_LED1DIS_8197F BIT(15) #define BIT_LED1PL_8197F BIT(12) @@ -790,33 +1008,45 @@ #define BIT_SHIFT_LED1CM_8197F 8 #define BIT_MASK_LED1CM_8197F 0x7 -#define BIT_LED1CM_8197F(x) (((x) & BIT_MASK_LED1CM_8197F) << BIT_SHIFT_LED1CM_8197F) +#define BIT_LED1CM_8197F(x) \ + (((x) & BIT_MASK_LED1CM_8197F) << BIT_SHIFT_LED1CM_8197F) #define BITS_LED1CM_8197F (BIT_MASK_LED1CM_8197F << BIT_SHIFT_LED1CM_8197F) #define BIT_CLEAR_LED1CM_8197F(x) ((x) & (~BITS_LED1CM_8197F)) -#define BIT_GET_LED1CM_8197F(x) (((x) >> BIT_SHIFT_LED1CM_8197F) & BIT_MASK_LED1CM_8197F) -#define BIT_SET_LED1CM_8197F(x, v) (BIT_CLEAR_LED1CM_8197F(x) | BIT_LED1CM_8197F(v)) +#define BIT_GET_LED1CM_8197F(x) \ + (((x) >> BIT_SHIFT_LED1CM_8197F) & BIT_MASK_LED1CM_8197F) +#define BIT_SET_LED1CM_8197F(x, v) \ + (BIT_CLEAR_LED1CM_8197F(x) | BIT_LED1CM_8197F(v)) #define BIT_LED0DIS_8197F BIT(7) #define BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F 5 #define BIT_MASK_AFE_LDO_SWR_CHECK_8197F 0x3 -#define BIT_AFE_LDO_SWR_CHECK_8197F(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8197F) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) -#define BITS_AFE_LDO_SWR_CHECK_8197F (BIT_MASK_AFE_LDO_SWR_CHECK_8197F << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) -#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) ((x) & (~BITS_AFE_LDO_SWR_CHECK_8197F)) -#define BIT_GET_AFE_LDO_SWR_CHECK_8197F(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) & BIT_MASK_AFE_LDO_SWR_CHECK_8197F) -#define BIT_SET_AFE_LDO_SWR_CHECK_8197F(x, v) (BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) | BIT_AFE_LDO_SWR_CHECK_8197F(v)) +#define BIT_AFE_LDO_SWR_CHECK_8197F(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8197F) \ + << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) +#define BITS_AFE_LDO_SWR_CHECK_8197F \ + (BIT_MASK_AFE_LDO_SWR_CHECK_8197F << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) \ + ((x) & (~BITS_AFE_LDO_SWR_CHECK_8197F)) +#define BIT_GET_AFE_LDO_SWR_CHECK_8197F(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) & \ + BIT_MASK_AFE_LDO_SWR_CHECK_8197F) +#define BIT_SET_AFE_LDO_SWR_CHECK_8197F(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) | BIT_AFE_LDO_SWR_CHECK_8197F(v)) #define BIT_LED0PL_8197F BIT(4) #define BIT_LED0SV_8197F BIT(3) #define BIT_SHIFT_LED0CM_8197F 0 #define BIT_MASK_LED0CM_8197F 0x7 -#define BIT_LED0CM_8197F(x) (((x) & BIT_MASK_LED0CM_8197F) << BIT_SHIFT_LED0CM_8197F) +#define BIT_LED0CM_8197F(x) \ + (((x) & BIT_MASK_LED0CM_8197F) << BIT_SHIFT_LED0CM_8197F) #define BITS_LED0CM_8197F (BIT_MASK_LED0CM_8197F << BIT_SHIFT_LED0CM_8197F) #define BIT_CLEAR_LED0CM_8197F(x) ((x) & (~BITS_LED0CM_8197F)) -#define BIT_GET_LED0CM_8197F(x) (((x) >> BIT_SHIFT_LED0CM_8197F) & BIT_MASK_LED0CM_8197F) -#define BIT_SET_LED0CM_8197F(x, v) (BIT_CLEAR_LED0CM_8197F(x) | BIT_LED0CM_8197F(v)) - +#define BIT_GET_LED0CM_8197F(x) \ + (((x) >> BIT_SHIFT_LED0CM_8197F) & BIT_MASK_LED0CM_8197F) +#define BIT_SET_LED0CM_8197F(x, v) \ + (BIT_CLEAR_LED0CM_8197F(x) | BIT_LED0CM_8197F(v)) /* 2 REG_FSIMR_8197F */ #define BIT_FS_PDNINT_EN_8197F BIT(31) @@ -935,39 +1165,64 @@ #define BIT_SHIFT_GPIO_MOD_15_TO_8_8197F 24 #define BIT_MASK_GPIO_MOD_15_TO_8_8197F 0xff -#define BIT_GPIO_MOD_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8197F) << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) -#define BITS_GPIO_MOD_15_TO_8_8197F (BIT_MASK_GPIO_MOD_15_TO_8_8197F << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) -#define BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_MOD_15_TO_8_8197F)) -#define BIT_GET_GPIO_MOD_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) & BIT_MASK_GPIO_MOD_15_TO_8_8197F) -#define BIT_SET_GPIO_MOD_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) | BIT_GPIO_MOD_15_TO_8_8197F(v)) - +#define BIT_GPIO_MOD_15_TO_8_8197F(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8197F) \ + << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) +#define BITS_GPIO_MOD_15_TO_8_8197F \ + (BIT_MASK_GPIO_MOD_15_TO_8_8197F << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) +#define BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) \ + ((x) & (~BITS_GPIO_MOD_15_TO_8_8197F)) +#define BIT_GET_GPIO_MOD_15_TO_8_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) & \ + BIT_MASK_GPIO_MOD_15_TO_8_8197F) +#define BIT_SET_GPIO_MOD_15_TO_8_8197F(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) | BIT_GPIO_MOD_15_TO_8_8197F(v)) #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F 16 #define BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F 0xff -#define BIT_GPIO_IO_SEL_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) -#define BITS_GPIO_IO_SEL_15_TO_8_8197F (BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) -#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8197F)) -#define BIT_GET_GPIO_IO_SEL_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F) -#define BIT_SET_GPIO_IO_SEL_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) | BIT_GPIO_IO_SEL_15_TO_8_8197F(v)) - +#define BIT_GPIO_IO_SEL_15_TO_8_8197F(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F) \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) +#define BITS_GPIO_IO_SEL_15_TO_8_8197F \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) \ + ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8197F)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) & \ + BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F) +#define BIT_SET_GPIO_IO_SEL_15_TO_8_8197F(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) | \ + BIT_GPIO_IO_SEL_15_TO_8_8197F(v)) #define BIT_SHIFT_GPIO_OUT_15_TO_8_8197F 8 #define BIT_MASK_GPIO_OUT_15_TO_8_8197F 0xff -#define BIT_GPIO_OUT_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8197F) << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) -#define BITS_GPIO_OUT_15_TO_8_8197F (BIT_MASK_GPIO_OUT_15_TO_8_8197F << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) -#define BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_OUT_15_TO_8_8197F)) -#define BIT_GET_GPIO_OUT_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) & BIT_MASK_GPIO_OUT_15_TO_8_8197F) -#define BIT_SET_GPIO_OUT_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) | BIT_GPIO_OUT_15_TO_8_8197F(v)) - +#define BIT_GPIO_OUT_15_TO_8_8197F(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8197F) \ + << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) +#define BITS_GPIO_OUT_15_TO_8_8197F \ + (BIT_MASK_GPIO_OUT_15_TO_8_8197F << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) +#define BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) \ + ((x) & (~BITS_GPIO_OUT_15_TO_8_8197F)) +#define BIT_GET_GPIO_OUT_15_TO_8_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) & \ + BIT_MASK_GPIO_OUT_15_TO_8_8197F) +#define BIT_SET_GPIO_OUT_15_TO_8_8197F(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) | BIT_GPIO_OUT_15_TO_8_8197F(v)) #define BIT_SHIFT_GPIO_IN_15_TO_8_8197F 0 #define BIT_MASK_GPIO_IN_15_TO_8_8197F 0xff -#define BIT_GPIO_IN_15_TO_8_8197F(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8197F) << BIT_SHIFT_GPIO_IN_15_TO_8_8197F) -#define BITS_GPIO_IN_15_TO_8_8197F (BIT_MASK_GPIO_IN_15_TO_8_8197F << BIT_SHIFT_GPIO_IN_15_TO_8_8197F) +#define BIT_GPIO_IN_15_TO_8_8197F(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8_8197F) \ + << BIT_SHIFT_GPIO_IN_15_TO_8_8197F) +#define BITS_GPIO_IN_15_TO_8_8197F \ + (BIT_MASK_GPIO_IN_15_TO_8_8197F << BIT_SHIFT_GPIO_IN_15_TO_8_8197F) #define BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8197F)) -#define BIT_GET_GPIO_IN_15_TO_8_8197F(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8197F) & BIT_MASK_GPIO_IN_15_TO_8_8197F) -#define BIT_SET_GPIO_IN_15_TO_8_8197F(x, v) (BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) | BIT_GPIO_IN_15_TO_8_8197F(v)) - +#define BIT_GET_GPIO_IN_15_TO_8_8197F(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8197F) & \ + BIT_MASK_GPIO_IN_15_TO_8_8197F) +#define BIT_SET_GPIO_IN_15_TO_8_8197F(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) | BIT_GPIO_IN_15_TO_8_8197F(v)) /* 2 REG_PAD_CTRL1_8197F */ #define BIT_PAPE_WLBT_SEL_8197F BIT(29) @@ -984,11 +1239,15 @@ #define BIT_SHIFT_BTGP_GPIO_SL_8197F 16 #define BIT_MASK_BTGP_GPIO_SL_8197F 0x3 -#define BIT_BTGP_GPIO_SL_8197F(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8197F) << BIT_SHIFT_BTGP_GPIO_SL_8197F) -#define BITS_BTGP_GPIO_SL_8197F (BIT_MASK_BTGP_GPIO_SL_8197F << BIT_SHIFT_BTGP_GPIO_SL_8197F) +#define BIT_BTGP_GPIO_SL_8197F(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL_8197F) << BIT_SHIFT_BTGP_GPIO_SL_8197F) +#define BITS_BTGP_GPIO_SL_8197F \ + (BIT_MASK_BTGP_GPIO_SL_8197F << BIT_SHIFT_BTGP_GPIO_SL_8197F) #define BIT_CLEAR_BTGP_GPIO_SL_8197F(x) ((x) & (~BITS_BTGP_GPIO_SL_8197F)) -#define BIT_GET_BTGP_GPIO_SL_8197F(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8197F) & BIT_MASK_BTGP_GPIO_SL_8197F) -#define BIT_SET_BTGP_GPIO_SL_8197F(x, v) (BIT_CLEAR_BTGP_GPIO_SL_8197F(x) | BIT_BTGP_GPIO_SL_8197F(v)) +#define BIT_GET_BTGP_GPIO_SL_8197F(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8197F) & BIT_MASK_BTGP_GPIO_SL_8197F) +#define BIT_SET_BTGP_GPIO_SL_8197F(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL_8197F(x) | BIT_BTGP_GPIO_SL_8197F(v)) #define BIT_PAD_SDIO_SR_8197F BIT(14) #define BIT_GPIO14_OUTPUT_PL_8197F BIT(13) @@ -1039,12 +1298,15 @@ #define BIT_SHIFT_WLCLK_PHASE_8197F 0 #define BIT_MASK_WLCLK_PHASE_8197F 0x1f -#define BIT_WLCLK_PHASE_8197F(x) (((x) & BIT_MASK_WLCLK_PHASE_8197F) << BIT_SHIFT_WLCLK_PHASE_8197F) -#define BITS_WLCLK_PHASE_8197F (BIT_MASK_WLCLK_PHASE_8197F << BIT_SHIFT_WLCLK_PHASE_8197F) +#define BIT_WLCLK_PHASE_8197F(x) \ + (((x) & BIT_MASK_WLCLK_PHASE_8197F) << BIT_SHIFT_WLCLK_PHASE_8197F) +#define BITS_WLCLK_PHASE_8197F \ + (BIT_MASK_WLCLK_PHASE_8197F << BIT_SHIFT_WLCLK_PHASE_8197F) #define BIT_CLEAR_WLCLK_PHASE_8197F(x) ((x) & (~BITS_WLCLK_PHASE_8197F)) -#define BIT_GET_WLCLK_PHASE_8197F(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8197F) & BIT_MASK_WLCLK_PHASE_8197F) -#define BIT_SET_WLCLK_PHASE_8197F(x, v) (BIT_CLEAR_WLCLK_PHASE_8197F(x) | BIT_WLCLK_PHASE_8197F(v)) - +#define BIT_GET_WLCLK_PHASE_8197F(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE_8197F) & BIT_MASK_WLCLK_PHASE_8197F) +#define BIT_SET_WLCLK_PHASE_8197F(x, v) \ + (BIT_CLEAR_WLCLK_PHASE_8197F(x) | BIT_WLCLK_PHASE_8197F(v)) /* 2 REG_SYS_SDIO_CTRL_8197F */ #define BIT_DBG_GNT_WL_BT_8197F BIT(27) @@ -1063,11 +1325,15 @@ #define BIT_SHIFT_SDIO_PAD_E_8197F 5 #define BIT_MASK_SDIO_PAD_E_8197F 0x7 -#define BIT_SDIO_PAD_E_8197F(x) (((x) & BIT_MASK_SDIO_PAD_E_8197F) << BIT_SHIFT_SDIO_PAD_E_8197F) -#define BITS_SDIO_PAD_E_8197F (BIT_MASK_SDIO_PAD_E_8197F << BIT_SHIFT_SDIO_PAD_E_8197F) +#define BIT_SDIO_PAD_E_8197F(x) \ + (((x) & BIT_MASK_SDIO_PAD_E_8197F) << BIT_SHIFT_SDIO_PAD_E_8197F) +#define BITS_SDIO_PAD_E_8197F \ + (BIT_MASK_SDIO_PAD_E_8197F << BIT_SHIFT_SDIO_PAD_E_8197F) #define BIT_CLEAR_SDIO_PAD_E_8197F(x) ((x) & (~BITS_SDIO_PAD_E_8197F)) -#define BIT_GET_SDIO_PAD_E_8197F(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8197F) & BIT_MASK_SDIO_PAD_E_8197F) -#define BIT_SET_SDIO_PAD_E_8197F(x, v) (BIT_CLEAR_SDIO_PAD_E_8197F(x) | BIT_SDIO_PAD_E_8197F(v)) +#define BIT_GET_SDIO_PAD_E_8197F(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E_8197F) & BIT_MASK_SDIO_PAD_E_8197F) +#define BIT_SET_SDIO_PAD_E_8197F(x, v) \ + (BIT_CLEAR_SDIO_PAD_E_8197F(x) | BIT_SDIO_PAD_E_8197F(v)) #define BIT_USB_LPPLL_EN_8197F BIT(4) #define BIT_ROP_SW15_8197F BIT(2) @@ -1081,11 +1347,15 @@ #define BIT_SHIFT_XTAL_LDO_8197F 20 #define BIT_MASK_XTAL_LDO_8197F 0x7 -#define BIT_XTAL_LDO_8197F(x) (((x) & BIT_MASK_XTAL_LDO_8197F) << BIT_SHIFT_XTAL_LDO_8197F) -#define BITS_XTAL_LDO_8197F (BIT_MASK_XTAL_LDO_8197F << BIT_SHIFT_XTAL_LDO_8197F) +#define BIT_XTAL_LDO_8197F(x) \ + (((x) & BIT_MASK_XTAL_LDO_8197F) << BIT_SHIFT_XTAL_LDO_8197F) +#define BITS_XTAL_LDO_8197F \ + (BIT_MASK_XTAL_LDO_8197F << BIT_SHIFT_XTAL_LDO_8197F) #define BIT_CLEAR_XTAL_LDO_8197F(x) ((x) & (~BITS_XTAL_LDO_8197F)) -#define BIT_GET_XTAL_LDO_8197F(x) (((x) >> BIT_SHIFT_XTAL_LDO_8197F) & BIT_MASK_XTAL_LDO_8197F) -#define BIT_SET_XTAL_LDO_8197F(x, v) (BIT_CLEAR_XTAL_LDO_8197F(x) | BIT_XTAL_LDO_8197F(v)) +#define BIT_GET_XTAL_LDO_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_8197F) & BIT_MASK_XTAL_LDO_8197F) +#define BIT_SET_XTAL_LDO_8197F(x, v) \ + (BIT_CLEAR_XTAL_LDO_8197F(x) | BIT_XTAL_LDO_8197F(v)) #define BIT_ADC_CK_SYNC_EN_8197F BIT(16) @@ -1134,7 +1404,8 @@ #define BIT_RPWM_8197F(x) (((x) & BIT_MASK_RPWM_8197F) << BIT_SHIFT_RPWM_8197F) #define BITS_RPWM_8197F (BIT_MASK_RPWM_8197F << BIT_SHIFT_RPWM_8197F) #define BIT_CLEAR_RPWM_8197F(x) ((x) & (~BITS_RPWM_8197F)) -#define BIT_GET_RPWM_8197F(x) (((x) >> BIT_SHIFT_RPWM_8197F) & BIT_MASK_RPWM_8197F) +#define BIT_GET_RPWM_8197F(x) \ + (((x) >> BIT_SHIFT_RPWM_8197F) & BIT_MASK_RPWM_8197F) #define BIT_SET_RPWM_8197F(x, v) (BIT_CLEAR_RPWM_8197F(x) | BIT_RPWM_8197F(v)) #define BIT_CPRST_8197F BIT(23) @@ -1145,22 +1416,29 @@ #define BIT_SHIFT_ROM_PGE_8197F 16 #define BIT_MASK_ROM_PGE_8197F 0x7 -#define BIT_ROM_PGE_8197F(x) (((x) & BIT_MASK_ROM_PGE_8197F) << BIT_SHIFT_ROM_PGE_8197F) +#define BIT_ROM_PGE_8197F(x) \ + (((x) & BIT_MASK_ROM_PGE_8197F) << BIT_SHIFT_ROM_PGE_8197F) #define BITS_ROM_PGE_8197F (BIT_MASK_ROM_PGE_8197F << BIT_SHIFT_ROM_PGE_8197F) #define BIT_CLEAR_ROM_PGE_8197F(x) ((x) & (~BITS_ROM_PGE_8197F)) -#define BIT_GET_ROM_PGE_8197F(x) (((x) >> BIT_SHIFT_ROM_PGE_8197F) & BIT_MASK_ROM_PGE_8197F) -#define BIT_SET_ROM_PGE_8197F(x, v) (BIT_CLEAR_ROM_PGE_8197F(x) | BIT_ROM_PGE_8197F(v)) +#define BIT_GET_ROM_PGE_8197F(x) \ + (((x) >> BIT_SHIFT_ROM_PGE_8197F) & BIT_MASK_ROM_PGE_8197F) +#define BIT_SET_ROM_PGE_8197F(x, v) \ + (BIT_CLEAR_ROM_PGE_8197F(x) | BIT_ROM_PGE_8197F(v)) #define BIT_FW_INIT_RDY_8197F BIT(15) #define BIT_FW_DW_RDY_8197F BIT(14) #define BIT_SHIFT_CPU_CLK_SEL_8197F 12 #define BIT_MASK_CPU_CLK_SEL_8197F 0x3 -#define BIT_CPU_CLK_SEL_8197F(x) (((x) & BIT_MASK_CPU_CLK_SEL_8197F) << BIT_SHIFT_CPU_CLK_SEL_8197F) -#define BITS_CPU_CLK_SEL_8197F (BIT_MASK_CPU_CLK_SEL_8197F << BIT_SHIFT_CPU_CLK_SEL_8197F) +#define BIT_CPU_CLK_SEL_8197F(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL_8197F) << BIT_SHIFT_CPU_CLK_SEL_8197F) +#define BITS_CPU_CLK_SEL_8197F \ + (BIT_MASK_CPU_CLK_SEL_8197F << BIT_SHIFT_CPU_CLK_SEL_8197F) #define BIT_CLEAR_CPU_CLK_SEL_8197F(x) ((x) & (~BITS_CPU_CLK_SEL_8197F)) -#define BIT_GET_CPU_CLK_SEL_8197F(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8197F) & BIT_MASK_CPU_CLK_SEL_8197F) -#define BIT_SET_CPU_CLK_SEL_8197F(x, v) (BIT_CLEAR_CPU_CLK_SEL_8197F(x) | BIT_CPU_CLK_SEL_8197F(v)) +#define BIT_GET_CPU_CLK_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL_8197F) & BIT_MASK_CPU_CLK_SEL_8197F) +#define BIT_SET_CPU_CLK_SEL_8197F(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL_8197F(x) | BIT_CPU_CLK_SEL_8197F(v)) #define BIT_CCLK_CHG_MASK_8197F BIT(11) #define BIT_FW_INIT_RDY_V1_8197F BIT(10) @@ -1178,52 +1456,66 @@ #define BIT_SHIFT_LBKTST_8197F 0 #define BIT_MASK_LBKTST_8197F 0xffff -#define BIT_LBKTST_8197F(x) (((x) & BIT_MASK_LBKTST_8197F) << BIT_SHIFT_LBKTST_8197F) +#define BIT_LBKTST_8197F(x) \ + (((x) & BIT_MASK_LBKTST_8197F) << BIT_SHIFT_LBKTST_8197F) #define BITS_LBKTST_8197F (BIT_MASK_LBKTST_8197F << BIT_SHIFT_LBKTST_8197F) #define BIT_CLEAR_LBKTST_8197F(x) ((x) & (~BITS_LBKTST_8197F)) -#define BIT_GET_LBKTST_8197F(x) (((x) >> BIT_SHIFT_LBKTST_8197F) & BIT_MASK_LBKTST_8197F) -#define BIT_SET_LBKTST_8197F(x, v) (BIT_CLEAR_LBKTST_8197F(x) | BIT_LBKTST_8197F(v)) - +#define BIT_GET_LBKTST_8197F(x) \ + (((x) >> BIT_SHIFT_LBKTST_8197F) & BIT_MASK_LBKTST_8197F) +#define BIT_SET_LBKTST_8197F(x, v) \ + (BIT_CLEAR_LBKTST_8197F(x) | BIT_LBKTST_8197F(v)) /* 2 REG_HMEBOX_E0_E1_8197F */ #define BIT_SHIFT_HOST_MSG_E1_8197F 16 #define BIT_MASK_HOST_MSG_E1_8197F 0xffff -#define BIT_HOST_MSG_E1_8197F(x) (((x) & BIT_MASK_HOST_MSG_E1_8197F) << BIT_SHIFT_HOST_MSG_E1_8197F) -#define BITS_HOST_MSG_E1_8197F (BIT_MASK_HOST_MSG_E1_8197F << BIT_SHIFT_HOST_MSG_E1_8197F) +#define BIT_HOST_MSG_E1_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_E1_8197F) << BIT_SHIFT_HOST_MSG_E1_8197F) +#define BITS_HOST_MSG_E1_8197F \ + (BIT_MASK_HOST_MSG_E1_8197F << BIT_SHIFT_HOST_MSG_E1_8197F) #define BIT_CLEAR_HOST_MSG_E1_8197F(x) ((x) & (~BITS_HOST_MSG_E1_8197F)) -#define BIT_GET_HOST_MSG_E1_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8197F) & BIT_MASK_HOST_MSG_E1_8197F) -#define BIT_SET_HOST_MSG_E1_8197F(x, v) (BIT_CLEAR_HOST_MSG_E1_8197F(x) | BIT_HOST_MSG_E1_8197F(v)) - +#define BIT_GET_HOST_MSG_E1_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1_8197F) & BIT_MASK_HOST_MSG_E1_8197F) +#define BIT_SET_HOST_MSG_E1_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_E1_8197F(x) | BIT_HOST_MSG_E1_8197F(v)) #define BIT_SHIFT_HOST_MSG_E0_8197F 0 #define BIT_MASK_HOST_MSG_E0_8197F 0xffff -#define BIT_HOST_MSG_E0_8197F(x) (((x) & BIT_MASK_HOST_MSG_E0_8197F) << BIT_SHIFT_HOST_MSG_E0_8197F) -#define BITS_HOST_MSG_E0_8197F (BIT_MASK_HOST_MSG_E0_8197F << BIT_SHIFT_HOST_MSG_E0_8197F) +#define BIT_HOST_MSG_E0_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_E0_8197F) << BIT_SHIFT_HOST_MSG_E0_8197F) +#define BITS_HOST_MSG_E0_8197F \ + (BIT_MASK_HOST_MSG_E0_8197F << BIT_SHIFT_HOST_MSG_E0_8197F) #define BIT_CLEAR_HOST_MSG_E0_8197F(x) ((x) & (~BITS_HOST_MSG_E0_8197F)) -#define BIT_GET_HOST_MSG_E0_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8197F) & BIT_MASK_HOST_MSG_E0_8197F) -#define BIT_SET_HOST_MSG_E0_8197F(x, v) (BIT_CLEAR_HOST_MSG_E0_8197F(x) | BIT_HOST_MSG_E0_8197F(v)) - +#define BIT_GET_HOST_MSG_E0_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0_8197F) & BIT_MASK_HOST_MSG_E0_8197F) +#define BIT_SET_HOST_MSG_E0_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_E0_8197F(x) | BIT_HOST_MSG_E0_8197F(v)) /* 2 REG_HMEBOX_E2_E3_8197F */ #define BIT_SHIFT_HOST_MSG_E3_8197F 16 #define BIT_MASK_HOST_MSG_E3_8197F 0xffff -#define BIT_HOST_MSG_E3_8197F(x) (((x) & BIT_MASK_HOST_MSG_E3_8197F) << BIT_SHIFT_HOST_MSG_E3_8197F) -#define BITS_HOST_MSG_E3_8197F (BIT_MASK_HOST_MSG_E3_8197F << BIT_SHIFT_HOST_MSG_E3_8197F) +#define BIT_HOST_MSG_E3_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_E3_8197F) << BIT_SHIFT_HOST_MSG_E3_8197F) +#define BITS_HOST_MSG_E3_8197F \ + (BIT_MASK_HOST_MSG_E3_8197F << BIT_SHIFT_HOST_MSG_E3_8197F) #define BIT_CLEAR_HOST_MSG_E3_8197F(x) ((x) & (~BITS_HOST_MSG_E3_8197F)) -#define BIT_GET_HOST_MSG_E3_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8197F) & BIT_MASK_HOST_MSG_E3_8197F) -#define BIT_SET_HOST_MSG_E3_8197F(x, v) (BIT_CLEAR_HOST_MSG_E3_8197F(x) | BIT_HOST_MSG_E3_8197F(v)) - +#define BIT_GET_HOST_MSG_E3_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3_8197F) & BIT_MASK_HOST_MSG_E3_8197F) +#define BIT_SET_HOST_MSG_E3_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_E3_8197F(x) | BIT_HOST_MSG_E3_8197F(v)) #define BIT_SHIFT_HOST_MSG_E2_8197F 0 #define BIT_MASK_HOST_MSG_E2_8197F 0xffff -#define BIT_HOST_MSG_E2_8197F(x) (((x) & BIT_MASK_HOST_MSG_E2_8197F) << BIT_SHIFT_HOST_MSG_E2_8197F) -#define BITS_HOST_MSG_E2_8197F (BIT_MASK_HOST_MSG_E2_8197F << BIT_SHIFT_HOST_MSG_E2_8197F) +#define BIT_HOST_MSG_E2_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_E2_8197F) << BIT_SHIFT_HOST_MSG_E2_8197F) +#define BITS_HOST_MSG_E2_8197F \ + (BIT_MASK_HOST_MSG_E2_8197F << BIT_SHIFT_HOST_MSG_E2_8197F) #define BIT_CLEAR_HOST_MSG_E2_8197F(x) ((x) & (~BITS_HOST_MSG_E2_8197F)) -#define BIT_GET_HOST_MSG_E2_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8197F) & BIT_MASK_HOST_MSG_E2_8197F) -#define BIT_SET_HOST_MSG_E2_8197F(x, v) (BIT_CLEAR_HOST_MSG_E2_8197F(x) | BIT_HOST_MSG_E2_8197F(v)) - +#define BIT_GET_HOST_MSG_E2_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2_8197F) & BIT_MASK_HOST_MSG_E2_8197F) +#define BIT_SET_HOST_MSG_E2_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_E2_8197F(x) | BIT_HOST_MSG_E2_8197F(v)) /* 2 REG_WLLPS_CTRL_8197F */ @@ -1264,156 +1556,207 @@ #define BIT_SHIFT_REF_SEL_8197F 25 #define BIT_MASK_REF_SEL_8197F 0xf -#define BIT_REF_SEL_8197F(x) (((x) & BIT_MASK_REF_SEL_8197F) << BIT_SHIFT_REF_SEL_8197F) +#define BIT_REF_SEL_8197F(x) \ + (((x) & BIT_MASK_REF_SEL_8197F) << BIT_SHIFT_REF_SEL_8197F) #define BITS_REF_SEL_8197F (BIT_MASK_REF_SEL_8197F << BIT_SHIFT_REF_SEL_8197F) #define BIT_CLEAR_REF_SEL_8197F(x) ((x) & (~BITS_REF_SEL_8197F)) -#define BIT_GET_REF_SEL_8197F(x) (((x) >> BIT_SHIFT_REF_SEL_8197F) & BIT_MASK_REF_SEL_8197F) -#define BIT_SET_REF_SEL_8197F(x, v) (BIT_CLEAR_REF_SEL_8197F(x) | BIT_REF_SEL_8197F(v)) - +#define BIT_GET_REF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_REF_SEL_8197F) & BIT_MASK_REF_SEL_8197F) +#define BIT_SET_REF_SEL_8197F(x, v) \ + (BIT_CLEAR_REF_SEL_8197F(x) | BIT_REF_SEL_8197F(v)) #define BIT_SHIFT_F0F_SDM_V2_8197F 12 #define BIT_MASK_F0F_SDM_V2_8197F 0x1fff -#define BIT_F0F_SDM_V2_8197F(x) (((x) & BIT_MASK_F0F_SDM_V2_8197F) << BIT_SHIFT_F0F_SDM_V2_8197F) -#define BITS_F0F_SDM_V2_8197F (BIT_MASK_F0F_SDM_V2_8197F << BIT_SHIFT_F0F_SDM_V2_8197F) +#define BIT_F0F_SDM_V2_8197F(x) \ + (((x) & BIT_MASK_F0F_SDM_V2_8197F) << BIT_SHIFT_F0F_SDM_V2_8197F) +#define BITS_F0F_SDM_V2_8197F \ + (BIT_MASK_F0F_SDM_V2_8197F << BIT_SHIFT_F0F_SDM_V2_8197F) #define BIT_CLEAR_F0F_SDM_V2_8197F(x) ((x) & (~BITS_F0F_SDM_V2_8197F)) -#define BIT_GET_F0F_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_F0F_SDM_V2_8197F) & BIT_MASK_F0F_SDM_V2_8197F) -#define BIT_SET_F0F_SDM_V2_8197F(x, v) (BIT_CLEAR_F0F_SDM_V2_8197F(x) | BIT_F0F_SDM_V2_8197F(v)) - +#define BIT_GET_F0F_SDM_V2_8197F(x) \ + (((x) >> BIT_SHIFT_F0F_SDM_V2_8197F) & BIT_MASK_F0F_SDM_V2_8197F) +#define BIT_SET_F0F_SDM_V2_8197F(x, v) \ + (BIT_CLEAR_F0F_SDM_V2_8197F(x) | BIT_F0F_SDM_V2_8197F(v)) #define BIT_SHIFT_F0N_SDM_V2_8197F 9 #define BIT_MASK_F0N_SDM_V2_8197F 0x7 -#define BIT_F0N_SDM_V2_8197F(x) (((x) & BIT_MASK_F0N_SDM_V2_8197F) << BIT_SHIFT_F0N_SDM_V2_8197F) -#define BITS_F0N_SDM_V2_8197F (BIT_MASK_F0N_SDM_V2_8197F << BIT_SHIFT_F0N_SDM_V2_8197F) +#define BIT_F0N_SDM_V2_8197F(x) \ + (((x) & BIT_MASK_F0N_SDM_V2_8197F) << BIT_SHIFT_F0N_SDM_V2_8197F) +#define BITS_F0N_SDM_V2_8197F \ + (BIT_MASK_F0N_SDM_V2_8197F << BIT_SHIFT_F0N_SDM_V2_8197F) #define BIT_CLEAR_F0N_SDM_V2_8197F(x) ((x) & (~BITS_F0N_SDM_V2_8197F)) -#define BIT_GET_F0N_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_F0N_SDM_V2_8197F) & BIT_MASK_F0N_SDM_V2_8197F) -#define BIT_SET_F0N_SDM_V2_8197F(x, v) (BIT_CLEAR_F0N_SDM_V2_8197F(x) | BIT_F0N_SDM_V2_8197F(v)) - +#define BIT_GET_F0N_SDM_V2_8197F(x) \ + (((x) >> BIT_SHIFT_F0N_SDM_V2_8197F) & BIT_MASK_F0N_SDM_V2_8197F) +#define BIT_SET_F0N_SDM_V2_8197F(x, v) \ + (BIT_CLEAR_F0N_SDM_V2_8197F(x) | BIT_F0N_SDM_V2_8197F(v)) #define BIT_SHIFT_DIVN_SDM_V2_8197F 3 #define BIT_MASK_DIVN_SDM_V2_8197F 0x3f -#define BIT_DIVN_SDM_V2_8197F(x) (((x) & BIT_MASK_DIVN_SDM_V2_8197F) << BIT_SHIFT_DIVN_SDM_V2_8197F) -#define BITS_DIVN_SDM_V2_8197F (BIT_MASK_DIVN_SDM_V2_8197F << BIT_SHIFT_DIVN_SDM_V2_8197F) +#define BIT_DIVN_SDM_V2_8197F(x) \ + (((x) & BIT_MASK_DIVN_SDM_V2_8197F) << BIT_SHIFT_DIVN_SDM_V2_8197F) +#define BITS_DIVN_SDM_V2_8197F \ + (BIT_MASK_DIVN_SDM_V2_8197F << BIT_SHIFT_DIVN_SDM_V2_8197F) #define BIT_CLEAR_DIVN_SDM_V2_8197F(x) ((x) & (~BITS_DIVN_SDM_V2_8197F)) -#define BIT_GET_DIVN_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_DIVN_SDM_V2_8197F) & BIT_MASK_DIVN_SDM_V2_8197F) -#define BIT_SET_DIVN_SDM_V2_8197F(x, v) (BIT_CLEAR_DIVN_SDM_V2_8197F(x) | BIT_DIVN_SDM_V2_8197F(v)) - +#define BIT_GET_DIVN_SDM_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DIVN_SDM_V2_8197F) & BIT_MASK_DIVN_SDM_V2_8197F) +#define BIT_SET_DIVN_SDM_V2_8197F(x, v) \ + (BIT_CLEAR_DIVN_SDM_V2_8197F(x) | BIT_DIVN_SDM_V2_8197F(v)) #define BIT_SHIFT_DITHER_SDM_V2_8197F 0 #define BIT_MASK_DITHER_SDM_V2_8197F 0x7 -#define BIT_DITHER_SDM_V2_8197F(x) (((x) & BIT_MASK_DITHER_SDM_V2_8197F) << BIT_SHIFT_DITHER_SDM_V2_8197F) -#define BITS_DITHER_SDM_V2_8197F (BIT_MASK_DITHER_SDM_V2_8197F << BIT_SHIFT_DITHER_SDM_V2_8197F) +#define BIT_DITHER_SDM_V2_8197F(x) \ + (((x) & BIT_MASK_DITHER_SDM_V2_8197F) << BIT_SHIFT_DITHER_SDM_V2_8197F) +#define BITS_DITHER_SDM_V2_8197F \ + (BIT_MASK_DITHER_SDM_V2_8197F << BIT_SHIFT_DITHER_SDM_V2_8197F) #define BIT_CLEAR_DITHER_SDM_V2_8197F(x) ((x) & (~BITS_DITHER_SDM_V2_8197F)) -#define BIT_GET_DITHER_SDM_V2_8197F(x) (((x) >> BIT_SHIFT_DITHER_SDM_V2_8197F) & BIT_MASK_DITHER_SDM_V2_8197F) -#define BIT_SET_DITHER_SDM_V2_8197F(x, v) (BIT_CLEAR_DITHER_SDM_V2_8197F(x) | BIT_DITHER_SDM_V2_8197F(v)) - +#define BIT_GET_DITHER_SDM_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DITHER_SDM_V2_8197F) & BIT_MASK_DITHER_SDM_V2_8197F) +#define BIT_SET_DITHER_SDM_V2_8197F(x, v) \ + (BIT_CLEAR_DITHER_SDM_V2_8197F(x) | BIT_DITHER_SDM_V2_8197F(v)) /* 2 REG_GPIO_DEBOUNCE_CTRL_8197F */ #define BIT_WLGP_DBC1EN_8197F BIT(15) #define BIT_SHIFT_WLGP_DBC1_8197F 8 #define BIT_MASK_WLGP_DBC1_8197F 0xf -#define BIT_WLGP_DBC1_8197F(x) (((x) & BIT_MASK_WLGP_DBC1_8197F) << BIT_SHIFT_WLGP_DBC1_8197F) -#define BITS_WLGP_DBC1_8197F (BIT_MASK_WLGP_DBC1_8197F << BIT_SHIFT_WLGP_DBC1_8197F) +#define BIT_WLGP_DBC1_8197F(x) \ + (((x) & BIT_MASK_WLGP_DBC1_8197F) << BIT_SHIFT_WLGP_DBC1_8197F) +#define BITS_WLGP_DBC1_8197F \ + (BIT_MASK_WLGP_DBC1_8197F << BIT_SHIFT_WLGP_DBC1_8197F) #define BIT_CLEAR_WLGP_DBC1_8197F(x) ((x) & (~BITS_WLGP_DBC1_8197F)) -#define BIT_GET_WLGP_DBC1_8197F(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8197F) & BIT_MASK_WLGP_DBC1_8197F) -#define BIT_SET_WLGP_DBC1_8197F(x, v) (BIT_CLEAR_WLGP_DBC1_8197F(x) | BIT_WLGP_DBC1_8197F(v)) +#define BIT_GET_WLGP_DBC1_8197F(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC1_8197F) & BIT_MASK_WLGP_DBC1_8197F) +#define BIT_SET_WLGP_DBC1_8197F(x, v) \ + (BIT_CLEAR_WLGP_DBC1_8197F(x) | BIT_WLGP_DBC1_8197F(v)) #define BIT_WLGP_DBC0EN_8197F BIT(7) #define BIT_SHIFT_WLGP_DBC0_8197F 0 #define BIT_MASK_WLGP_DBC0_8197F 0xf -#define BIT_WLGP_DBC0_8197F(x) (((x) & BIT_MASK_WLGP_DBC0_8197F) << BIT_SHIFT_WLGP_DBC0_8197F) -#define BITS_WLGP_DBC0_8197F (BIT_MASK_WLGP_DBC0_8197F << BIT_SHIFT_WLGP_DBC0_8197F) +#define BIT_WLGP_DBC0_8197F(x) \ + (((x) & BIT_MASK_WLGP_DBC0_8197F) << BIT_SHIFT_WLGP_DBC0_8197F) +#define BITS_WLGP_DBC0_8197F \ + (BIT_MASK_WLGP_DBC0_8197F << BIT_SHIFT_WLGP_DBC0_8197F) #define BIT_CLEAR_WLGP_DBC0_8197F(x) ((x) & (~BITS_WLGP_DBC0_8197F)) -#define BIT_GET_WLGP_DBC0_8197F(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8197F) & BIT_MASK_WLGP_DBC0_8197F) -#define BIT_SET_WLGP_DBC0_8197F(x, v) (BIT_CLEAR_WLGP_DBC0_8197F(x) | BIT_WLGP_DBC0_8197F(v)) - +#define BIT_GET_WLGP_DBC0_8197F(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC0_8197F) & BIT_MASK_WLGP_DBC0_8197F) +#define BIT_SET_WLGP_DBC0_8197F(x, v) \ + (BIT_CLEAR_WLGP_DBC0_8197F(x) | BIT_WLGP_DBC0_8197F(v)) /* 2 REG_RPWM2_8197F */ #define BIT_SHIFT_RPWM2_8197F 16 #define BIT_MASK_RPWM2_8197F 0xffff -#define BIT_RPWM2_8197F(x) (((x) & BIT_MASK_RPWM2_8197F) << BIT_SHIFT_RPWM2_8197F) +#define BIT_RPWM2_8197F(x) \ + (((x) & BIT_MASK_RPWM2_8197F) << BIT_SHIFT_RPWM2_8197F) #define BITS_RPWM2_8197F (BIT_MASK_RPWM2_8197F << BIT_SHIFT_RPWM2_8197F) #define BIT_CLEAR_RPWM2_8197F(x) ((x) & (~BITS_RPWM2_8197F)) -#define BIT_GET_RPWM2_8197F(x) (((x) >> BIT_SHIFT_RPWM2_8197F) & BIT_MASK_RPWM2_8197F) -#define BIT_SET_RPWM2_8197F(x, v) (BIT_CLEAR_RPWM2_8197F(x) | BIT_RPWM2_8197F(v)) - +#define BIT_GET_RPWM2_8197F(x) \ + (((x) >> BIT_SHIFT_RPWM2_8197F) & BIT_MASK_RPWM2_8197F) +#define BIT_SET_RPWM2_8197F(x, v) \ + (BIT_CLEAR_RPWM2_8197F(x) | BIT_RPWM2_8197F(v)) /* 2 REG_SYSON_FSM_MON_8197F */ #define BIT_SHIFT_FSM_MON_SEL_8197F 24 #define BIT_MASK_FSM_MON_SEL_8197F 0x7 -#define BIT_FSM_MON_SEL_8197F(x) (((x) & BIT_MASK_FSM_MON_SEL_8197F) << BIT_SHIFT_FSM_MON_SEL_8197F) -#define BITS_FSM_MON_SEL_8197F (BIT_MASK_FSM_MON_SEL_8197F << BIT_SHIFT_FSM_MON_SEL_8197F) +#define BIT_FSM_MON_SEL_8197F(x) \ + (((x) & BIT_MASK_FSM_MON_SEL_8197F) << BIT_SHIFT_FSM_MON_SEL_8197F) +#define BITS_FSM_MON_SEL_8197F \ + (BIT_MASK_FSM_MON_SEL_8197F << BIT_SHIFT_FSM_MON_SEL_8197F) #define BIT_CLEAR_FSM_MON_SEL_8197F(x) ((x) & (~BITS_FSM_MON_SEL_8197F)) -#define BIT_GET_FSM_MON_SEL_8197F(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8197F) & BIT_MASK_FSM_MON_SEL_8197F) -#define BIT_SET_FSM_MON_SEL_8197F(x, v) (BIT_CLEAR_FSM_MON_SEL_8197F(x) | BIT_FSM_MON_SEL_8197F(v)) +#define BIT_GET_FSM_MON_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL_8197F) & BIT_MASK_FSM_MON_SEL_8197F) +#define BIT_SET_FSM_MON_SEL_8197F(x, v) \ + (BIT_CLEAR_FSM_MON_SEL_8197F(x) | BIT_FSM_MON_SEL_8197F(v)) #define BIT_DOP_ELDO_8197F BIT(23) #define BIT_FSM_MON_UPD_8197F BIT(15) #define BIT_SHIFT_FSM_PAR_8197F 0 #define BIT_MASK_FSM_PAR_8197F 0x7fff -#define BIT_FSM_PAR_8197F(x) (((x) & BIT_MASK_FSM_PAR_8197F) << BIT_SHIFT_FSM_PAR_8197F) +#define BIT_FSM_PAR_8197F(x) \ + (((x) & BIT_MASK_FSM_PAR_8197F) << BIT_SHIFT_FSM_PAR_8197F) #define BITS_FSM_PAR_8197F (BIT_MASK_FSM_PAR_8197F << BIT_SHIFT_FSM_PAR_8197F) #define BIT_CLEAR_FSM_PAR_8197F(x) ((x) & (~BITS_FSM_PAR_8197F)) -#define BIT_GET_FSM_PAR_8197F(x) (((x) >> BIT_SHIFT_FSM_PAR_8197F) & BIT_MASK_FSM_PAR_8197F) -#define BIT_SET_FSM_PAR_8197F(x, v) (BIT_CLEAR_FSM_PAR_8197F(x) | BIT_FSM_PAR_8197F(v)) - +#define BIT_GET_FSM_PAR_8197F(x) \ + (((x) >> BIT_SHIFT_FSM_PAR_8197F) & BIT_MASK_FSM_PAR_8197F) +#define BIT_SET_FSM_PAR_8197F(x, v) \ + (BIT_CLEAR_FSM_PAR_8197F(x) | BIT_FSM_PAR_8197F(v)) /* 2 REG_AFE_CTRL6_8197F */ #define BIT_SHIFT_TSFT_SEL_V1_8197F 0 #define BIT_MASK_TSFT_SEL_V1_8197F 0x7 -#define BIT_TSFT_SEL_V1_8197F(x) (((x) & BIT_MASK_TSFT_SEL_V1_8197F) << BIT_SHIFT_TSFT_SEL_V1_8197F) -#define BITS_TSFT_SEL_V1_8197F (BIT_MASK_TSFT_SEL_V1_8197F << BIT_SHIFT_TSFT_SEL_V1_8197F) +#define BIT_TSFT_SEL_V1_8197F(x) \ + (((x) & BIT_MASK_TSFT_SEL_V1_8197F) << BIT_SHIFT_TSFT_SEL_V1_8197F) +#define BITS_TSFT_SEL_V1_8197F \ + (BIT_MASK_TSFT_SEL_V1_8197F << BIT_SHIFT_TSFT_SEL_V1_8197F) #define BIT_CLEAR_TSFT_SEL_V1_8197F(x) ((x) & (~BITS_TSFT_SEL_V1_8197F)) -#define BIT_GET_TSFT_SEL_V1_8197F(x) (((x) >> BIT_SHIFT_TSFT_SEL_V1_8197F) & BIT_MASK_TSFT_SEL_V1_8197F) -#define BIT_SET_TSFT_SEL_V1_8197F(x, v) (BIT_CLEAR_TSFT_SEL_V1_8197F(x) | BIT_TSFT_SEL_V1_8197F(v)) - +#define BIT_GET_TSFT_SEL_V1_8197F(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_V1_8197F) & BIT_MASK_TSFT_SEL_V1_8197F) +#define BIT_SET_TSFT_SEL_V1_8197F(x, v) \ + (BIT_CLEAR_TSFT_SEL_V1_8197F(x) | BIT_TSFT_SEL_V1_8197F(v)) /* 2 REG_PMC_DBG_CTRL1_8197F */ #define BIT_BT_INT_EN_8197F BIT(31) #define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F 16 #define BIT_MASK_RD_WR_WIFI_BT_INFO_8197F 0x7fff -#define BIT_RD_WR_WIFI_BT_INFO_8197F(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8197F) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) -#define BITS_RD_WR_WIFI_BT_INFO_8197F (BIT_MASK_RD_WR_WIFI_BT_INFO_8197F << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) -#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8197F)) -#define BIT_GET_RD_WR_WIFI_BT_INFO_8197F(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) & BIT_MASK_RD_WR_WIFI_BT_INFO_8197F) -#define BIT_SET_RD_WR_WIFI_BT_INFO_8197F(x, v) (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) | BIT_RD_WR_WIFI_BT_INFO_8197F(v)) +#define BIT_RD_WR_WIFI_BT_INFO_8197F(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8197F) \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) +#define BITS_RD_WR_WIFI_BT_INFO_8197F \ + (BIT_MASK_RD_WR_WIFI_BT_INFO_8197F \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) \ + ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8197F)) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) & \ + BIT_MASK_RD_WR_WIFI_BT_INFO_8197F) +#define BIT_SET_RD_WR_WIFI_BT_INFO_8197F(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) | \ + BIT_RD_WR_WIFI_BT_INFO_8197F(v)) #define BIT_PMC_WR_OVF_8197F BIT(8) #define BIT_SHIFT_WLPMC_ERRINT_8197F 0 #define BIT_MASK_WLPMC_ERRINT_8197F 0xff -#define BIT_WLPMC_ERRINT_8197F(x) (((x) & BIT_MASK_WLPMC_ERRINT_8197F) << BIT_SHIFT_WLPMC_ERRINT_8197F) -#define BITS_WLPMC_ERRINT_8197F (BIT_MASK_WLPMC_ERRINT_8197F << BIT_SHIFT_WLPMC_ERRINT_8197F) +#define BIT_WLPMC_ERRINT_8197F(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT_8197F) << BIT_SHIFT_WLPMC_ERRINT_8197F) +#define BITS_WLPMC_ERRINT_8197F \ + (BIT_MASK_WLPMC_ERRINT_8197F << BIT_SHIFT_WLPMC_ERRINT_8197F) #define BIT_CLEAR_WLPMC_ERRINT_8197F(x) ((x) & (~BITS_WLPMC_ERRINT_8197F)) -#define BIT_GET_WLPMC_ERRINT_8197F(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8197F) & BIT_MASK_WLPMC_ERRINT_8197F) -#define BIT_SET_WLPMC_ERRINT_8197F(x, v) (BIT_CLEAR_WLPMC_ERRINT_8197F(x) | BIT_WLPMC_ERRINT_8197F(v)) - +#define BIT_GET_WLPMC_ERRINT_8197F(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT_8197F) & BIT_MASK_WLPMC_ERRINT_8197F) +#define BIT_SET_WLPMC_ERRINT_8197F(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT_8197F(x) | BIT_WLPMC_ERRINT_8197F(v)) /* 2 REG_AFE_CTRL7_8197F */ #define BIT_SHIFT_SEL_V_8197F 30 #define BIT_MASK_SEL_V_8197F 0x3 -#define BIT_SEL_V_8197F(x) (((x) & BIT_MASK_SEL_V_8197F) << BIT_SHIFT_SEL_V_8197F) +#define BIT_SEL_V_8197F(x) \ + (((x) & BIT_MASK_SEL_V_8197F) << BIT_SHIFT_SEL_V_8197F) #define BITS_SEL_V_8197F (BIT_MASK_SEL_V_8197F << BIT_SHIFT_SEL_V_8197F) #define BIT_CLEAR_SEL_V_8197F(x) ((x) & (~BITS_SEL_V_8197F)) -#define BIT_GET_SEL_V_8197F(x) (((x) >> BIT_SHIFT_SEL_V_8197F) & BIT_MASK_SEL_V_8197F) -#define BIT_SET_SEL_V_8197F(x, v) (BIT_CLEAR_SEL_V_8197F(x) | BIT_SEL_V_8197F(v)) +#define BIT_GET_SEL_V_8197F(x) \ + (((x) >> BIT_SHIFT_SEL_V_8197F) & BIT_MASK_SEL_V_8197F) +#define BIT_SET_SEL_V_8197F(x, v) \ + (BIT_CLEAR_SEL_V_8197F(x) | BIT_SEL_V_8197F(v)) #define BIT_SEL_LDO_PC_8197F BIT(29) #define BIT_SHIFT_CK_MON_SEL_V2_8197F 26 #define BIT_MASK_CK_MON_SEL_V2_8197F 0x7 -#define BIT_CK_MON_SEL_V2_8197F(x) (((x) & BIT_MASK_CK_MON_SEL_V2_8197F) << BIT_SHIFT_CK_MON_SEL_V2_8197F) -#define BITS_CK_MON_SEL_V2_8197F (BIT_MASK_CK_MON_SEL_V2_8197F << BIT_SHIFT_CK_MON_SEL_V2_8197F) +#define BIT_CK_MON_SEL_V2_8197F(x) \ + (((x) & BIT_MASK_CK_MON_SEL_V2_8197F) << BIT_SHIFT_CK_MON_SEL_V2_8197F) +#define BITS_CK_MON_SEL_V2_8197F \ + (BIT_MASK_CK_MON_SEL_V2_8197F << BIT_SHIFT_CK_MON_SEL_V2_8197F) #define BIT_CLEAR_CK_MON_SEL_V2_8197F(x) ((x) & (~BITS_CK_MON_SEL_V2_8197F)) -#define BIT_GET_CK_MON_SEL_V2_8197F(x) (((x) >> BIT_SHIFT_CK_MON_SEL_V2_8197F) & BIT_MASK_CK_MON_SEL_V2_8197F) -#define BIT_SET_CK_MON_SEL_V2_8197F(x, v) (BIT_CLEAR_CK_MON_SEL_V2_8197F(x) | BIT_CK_MON_SEL_V2_8197F(v)) +#define BIT_GET_CK_MON_SEL_V2_8197F(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_V2_8197F) & BIT_MASK_CK_MON_SEL_V2_8197F) +#define BIT_SET_CK_MON_SEL_V2_8197F(x, v) \ + (BIT_CLEAR_CK_MON_SEL_V2_8197F(x) | BIT_CK_MON_SEL_V2_8197F(v)) #define BIT_CK_MON_EN_8197F BIT(25) #define BIT_FREF_EDGE_8197F BIT(24) @@ -1433,7 +1776,8 @@ #define BIT_BCNDMAINT0_MSK_8197F BIT(20) #define BIT_BCNDERR0_MSK_8197F BIT(16) #define BIT_HSISR_IND_ON_INT_MSK_8197F BIT(15) -#define BIT_BCNDMAINT_E_MSK_8197F BIT(14) +#define BIT_HISR3_IND_INT_MSK_8197F BIT(14) +#define BIT_HISR2_IND_INT_MSK_8197F BIT(13) #define BIT_CTWEND_MSK_8197F BIT(12) #define BIT_HISR1_IND_MSK_8197F BIT(11) #define BIT_C2HCMD_MSK_8197F BIT(10) @@ -1449,8 +1793,8 @@ #define BIT_RXOK_MSK_8197F BIT(0) /* 2 REG_HISR0_8197F */ -#define BIT_TIMEOUT_INTERRUPT2_8197F BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_8197F BIT(30) +#define BIT_PSTIMEOUT2_8197F BIT(31) +#define BIT_PSTIMEOUT1_8197F BIT(30) #define BIT_PSTIMEOUT_8197F BIT(29) #define BIT_GTINT4_8197F BIT(28) #define BIT_GTINT3_8197F BIT(27) @@ -1460,7 +1804,8 @@ #define BIT_BCNDMAINT0_8197F BIT(20) #define BIT_BCNDERR0_8197F BIT(16) #define BIT_HSISR_IND_ON_INT_8197F BIT(15) -#define BIT_BCNDMAINT_E_8197F BIT(14) +#define BIT_HISR3_IND_INT_8197F BIT(14) +#define BIT_HISR2_IND_INT_8197F BIT(13) #define BIT_CTWEND_8197F BIT(12) #define BIT_HISR1_IND_INT_8197F BIT(11) #define BIT_C2HCMD_8197F BIT(10) @@ -1527,12 +1872,15 @@ #define BIT_SHIFT_DEBUG_ST_8197F 0 #define BIT_MASK_DEBUG_ST_8197F 0xffffffffL -#define BIT_DEBUG_ST_8197F(x) (((x) & BIT_MASK_DEBUG_ST_8197F) << BIT_SHIFT_DEBUG_ST_8197F) -#define BITS_DEBUG_ST_8197F (BIT_MASK_DEBUG_ST_8197F << BIT_SHIFT_DEBUG_ST_8197F) +#define BIT_DEBUG_ST_8197F(x) \ + (((x) & BIT_MASK_DEBUG_ST_8197F) << BIT_SHIFT_DEBUG_ST_8197F) +#define BITS_DEBUG_ST_8197F \ + (BIT_MASK_DEBUG_ST_8197F << BIT_SHIFT_DEBUG_ST_8197F) #define BIT_CLEAR_DEBUG_ST_8197F(x) ((x) & (~BITS_DEBUG_ST_8197F)) -#define BIT_GET_DEBUG_ST_8197F(x) (((x) >> BIT_SHIFT_DEBUG_ST_8197F) & BIT_MASK_DEBUG_ST_8197F) -#define BIT_SET_DEBUG_ST_8197F(x, v) (BIT_CLEAR_DEBUG_ST_8197F(x) | BIT_DEBUG_ST_8197F(v)) - +#define BIT_GET_DEBUG_ST_8197F(x) \ + (((x) >> BIT_SHIFT_DEBUG_ST_8197F) & BIT_MASK_DEBUG_ST_8197F) +#define BIT_SET_DEBUG_ST_8197F(x, v) \ + (BIT_CLEAR_DEBUG_ST_8197F(x) | BIT_DEBUG_ST_8197F(v)) /* 2 REG_PAD_CTRL2_8197F */ @@ -1559,11 +1907,17 @@ #define BIT_SHIFT_EFUSE_BURN_GNT_8197F 24 #define BIT_MASK_EFUSE_BURN_GNT_8197F 0xff -#define BIT_EFUSE_BURN_GNT_8197F(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8197F) << BIT_SHIFT_EFUSE_BURN_GNT_8197F) -#define BITS_EFUSE_BURN_GNT_8197F (BIT_MASK_EFUSE_BURN_GNT_8197F << BIT_SHIFT_EFUSE_BURN_GNT_8197F) +#define BIT_EFUSE_BURN_GNT_8197F(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT_8197F) \ + << BIT_SHIFT_EFUSE_BURN_GNT_8197F) +#define BITS_EFUSE_BURN_GNT_8197F \ + (BIT_MASK_EFUSE_BURN_GNT_8197F << BIT_SHIFT_EFUSE_BURN_GNT_8197F) #define BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) ((x) & (~BITS_EFUSE_BURN_GNT_8197F)) -#define BIT_GET_EFUSE_BURN_GNT_8197F(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8197F) & BIT_MASK_EFUSE_BURN_GNT_8197F) -#define BIT_SET_EFUSE_BURN_GNT_8197F(x, v) (BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) | BIT_EFUSE_BURN_GNT_8197F(v)) +#define BIT_GET_EFUSE_BURN_GNT_8197F(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8197F) & \ + BIT_MASK_EFUSE_BURN_GNT_8197F) +#define BIT_SET_EFUSE_BURN_GNT_8197F(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) | BIT_EFUSE_BURN_GNT_8197F(v)) #define BIT_STOP_WL_PMC_8197F BIT(9) #define BIT_STOP_SYM_PMC_8197F BIT(8) @@ -1574,12 +1928,15 @@ #define BIT_SHIFT_SYSON_REG_ARB_8197F 0 #define BIT_MASK_SYSON_REG_ARB_8197F 0x3 -#define BIT_SYSON_REG_ARB_8197F(x) (((x) & BIT_MASK_SYSON_REG_ARB_8197F) << BIT_SHIFT_SYSON_REG_ARB_8197F) -#define BITS_SYSON_REG_ARB_8197F (BIT_MASK_SYSON_REG_ARB_8197F << BIT_SHIFT_SYSON_REG_ARB_8197F) +#define BIT_SYSON_REG_ARB_8197F(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB_8197F) << BIT_SHIFT_SYSON_REG_ARB_8197F) +#define BITS_SYSON_REG_ARB_8197F \ + (BIT_MASK_SYSON_REG_ARB_8197F << BIT_SHIFT_SYSON_REG_ARB_8197F) #define BIT_CLEAR_SYSON_REG_ARB_8197F(x) ((x) & (~BITS_SYSON_REG_ARB_8197F)) -#define BIT_GET_SYSON_REG_ARB_8197F(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8197F) & BIT_MASK_SYSON_REG_ARB_8197F) -#define BIT_SET_SYSON_REG_ARB_8197F(x, v) (BIT_CLEAR_SYSON_REG_ARB_8197F(x) | BIT_SYSON_REG_ARB_8197F(v)) - +#define BIT_GET_SYSON_REG_ARB_8197F(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB_8197F) & BIT_MASK_SYSON_REG_ARB_8197F) +#define BIT_SET_SYSON_REG_ARB_8197F(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB_8197F(x) | BIT_SYSON_REG_ARB_8197F(v)) /* 2 REG_BIST_CTRL_8197F */ #define BIT_BIST_USB_DIS_8197F BIT(27) @@ -1589,11 +1946,15 @@ #define BIT_SHIFT_BIST_RPT_SEL_8197F 16 #define BIT_MASK_BIST_RPT_SEL_8197F 0xf -#define BIT_BIST_RPT_SEL_8197F(x) (((x) & BIT_MASK_BIST_RPT_SEL_8197F) << BIT_SHIFT_BIST_RPT_SEL_8197F) -#define BITS_BIST_RPT_SEL_8197F (BIT_MASK_BIST_RPT_SEL_8197F << BIT_SHIFT_BIST_RPT_SEL_8197F) +#define BIT_BIST_RPT_SEL_8197F(x) \ + (((x) & BIT_MASK_BIST_RPT_SEL_8197F) << BIT_SHIFT_BIST_RPT_SEL_8197F) +#define BITS_BIST_RPT_SEL_8197F \ + (BIT_MASK_BIST_RPT_SEL_8197F << BIT_SHIFT_BIST_RPT_SEL_8197F) #define BIT_CLEAR_BIST_RPT_SEL_8197F(x) ((x) & (~BITS_BIST_RPT_SEL_8197F)) -#define BIT_GET_BIST_RPT_SEL_8197F(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8197F) & BIT_MASK_BIST_RPT_SEL_8197F) -#define BIT_SET_BIST_RPT_SEL_8197F(x, v) (BIT_CLEAR_BIST_RPT_SEL_8197F(x) | BIT_BIST_RPT_SEL_8197F(v)) +#define BIT_GET_BIST_RPT_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_BIST_RPT_SEL_8197F) & BIT_MASK_BIST_RPT_SEL_8197F) +#define BIT_SET_BIST_RPT_SEL_8197F(x, v) \ + (BIT_CLEAR_BIST_RPT_SEL_8197F(x) | BIT_BIST_RPT_SEL_8197F(v)) #define BIT_BIST_RESUME_PS_8197F BIT(4) #define BIT_BIST_RESUME_8197F BIT(3) @@ -1605,99 +1966,135 @@ #define BIT_SHIFT_MBIST_REPORT_8197F 0 #define BIT_MASK_MBIST_REPORT_8197F 0xffffffffL -#define BIT_MBIST_REPORT_8197F(x) (((x) & BIT_MASK_MBIST_REPORT_8197F) << BIT_SHIFT_MBIST_REPORT_8197F) -#define BITS_MBIST_REPORT_8197F (BIT_MASK_MBIST_REPORT_8197F << BIT_SHIFT_MBIST_REPORT_8197F) +#define BIT_MBIST_REPORT_8197F(x) \ + (((x) & BIT_MASK_MBIST_REPORT_8197F) << BIT_SHIFT_MBIST_REPORT_8197F) +#define BITS_MBIST_REPORT_8197F \ + (BIT_MASK_MBIST_REPORT_8197F << BIT_SHIFT_MBIST_REPORT_8197F) #define BIT_CLEAR_MBIST_REPORT_8197F(x) ((x) & (~BITS_MBIST_REPORT_8197F)) -#define BIT_GET_MBIST_REPORT_8197F(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8197F) & BIT_MASK_MBIST_REPORT_8197F) -#define BIT_SET_MBIST_REPORT_8197F(x, v) (BIT_CLEAR_MBIST_REPORT_8197F(x) | BIT_MBIST_REPORT_8197F(v)) - +#define BIT_GET_MBIST_REPORT_8197F(x) \ + (((x) >> BIT_SHIFT_MBIST_REPORT_8197F) & BIT_MASK_MBIST_REPORT_8197F) +#define BIT_SET_MBIST_REPORT_8197F(x, v) \ + (BIT_CLEAR_MBIST_REPORT_8197F(x) | BIT_MBIST_REPORT_8197F(v)) /* 2 REG_MEM_CTRL_8197F */ #define BIT_UMEM_RME_8197F BIT(31) #define BIT_SHIFT_BT_SPRAM_8197F 28 #define BIT_MASK_BT_SPRAM_8197F 0x3 -#define BIT_BT_SPRAM_8197F(x) (((x) & BIT_MASK_BT_SPRAM_8197F) << BIT_SHIFT_BT_SPRAM_8197F) -#define BITS_BT_SPRAM_8197F (BIT_MASK_BT_SPRAM_8197F << BIT_SHIFT_BT_SPRAM_8197F) +#define BIT_BT_SPRAM_8197F(x) \ + (((x) & BIT_MASK_BT_SPRAM_8197F) << BIT_SHIFT_BT_SPRAM_8197F) +#define BITS_BT_SPRAM_8197F \ + (BIT_MASK_BT_SPRAM_8197F << BIT_SHIFT_BT_SPRAM_8197F) #define BIT_CLEAR_BT_SPRAM_8197F(x) ((x) & (~BITS_BT_SPRAM_8197F)) -#define BIT_GET_BT_SPRAM_8197F(x) (((x) >> BIT_SHIFT_BT_SPRAM_8197F) & BIT_MASK_BT_SPRAM_8197F) -#define BIT_SET_BT_SPRAM_8197F(x, v) (BIT_CLEAR_BT_SPRAM_8197F(x) | BIT_BT_SPRAM_8197F(v)) - +#define BIT_GET_BT_SPRAM_8197F(x) \ + (((x) >> BIT_SHIFT_BT_SPRAM_8197F) & BIT_MASK_BT_SPRAM_8197F) +#define BIT_SET_BT_SPRAM_8197F(x, v) \ + (BIT_CLEAR_BT_SPRAM_8197F(x) | BIT_BT_SPRAM_8197F(v)) #define BIT_SHIFT_BT_ROM_8197F 24 #define BIT_MASK_BT_ROM_8197F 0xf -#define BIT_BT_ROM_8197F(x) (((x) & BIT_MASK_BT_ROM_8197F) << BIT_SHIFT_BT_ROM_8197F) +#define BIT_BT_ROM_8197F(x) \ + (((x) & BIT_MASK_BT_ROM_8197F) << BIT_SHIFT_BT_ROM_8197F) #define BITS_BT_ROM_8197F (BIT_MASK_BT_ROM_8197F << BIT_SHIFT_BT_ROM_8197F) #define BIT_CLEAR_BT_ROM_8197F(x) ((x) & (~BITS_BT_ROM_8197F)) -#define BIT_GET_BT_ROM_8197F(x) (((x) >> BIT_SHIFT_BT_ROM_8197F) & BIT_MASK_BT_ROM_8197F) -#define BIT_SET_BT_ROM_8197F(x, v) (BIT_CLEAR_BT_ROM_8197F(x) | BIT_BT_ROM_8197F(v)) - +#define BIT_GET_BT_ROM_8197F(x) \ + (((x) >> BIT_SHIFT_BT_ROM_8197F) & BIT_MASK_BT_ROM_8197F) +#define BIT_SET_BT_ROM_8197F(x, v) \ + (BIT_CLEAR_BT_ROM_8197F(x) | BIT_BT_ROM_8197F(v)) #define BIT_SHIFT_PCI_DPRAM_8197F 10 #define BIT_MASK_PCI_DPRAM_8197F 0x3 -#define BIT_PCI_DPRAM_8197F(x) (((x) & BIT_MASK_PCI_DPRAM_8197F) << BIT_SHIFT_PCI_DPRAM_8197F) -#define BITS_PCI_DPRAM_8197F (BIT_MASK_PCI_DPRAM_8197F << BIT_SHIFT_PCI_DPRAM_8197F) +#define BIT_PCI_DPRAM_8197F(x) \ + (((x) & BIT_MASK_PCI_DPRAM_8197F) << BIT_SHIFT_PCI_DPRAM_8197F) +#define BITS_PCI_DPRAM_8197F \ + (BIT_MASK_PCI_DPRAM_8197F << BIT_SHIFT_PCI_DPRAM_8197F) #define BIT_CLEAR_PCI_DPRAM_8197F(x) ((x) & (~BITS_PCI_DPRAM_8197F)) -#define BIT_GET_PCI_DPRAM_8197F(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8197F) & BIT_MASK_PCI_DPRAM_8197F) -#define BIT_SET_PCI_DPRAM_8197F(x, v) (BIT_CLEAR_PCI_DPRAM_8197F(x) | BIT_PCI_DPRAM_8197F(v)) - +#define BIT_GET_PCI_DPRAM_8197F(x) \ + (((x) >> BIT_SHIFT_PCI_DPRAM_8197F) & BIT_MASK_PCI_DPRAM_8197F) +#define BIT_SET_PCI_DPRAM_8197F(x, v) \ + (BIT_CLEAR_PCI_DPRAM_8197F(x) | BIT_PCI_DPRAM_8197F(v)) #define BIT_SHIFT_PCI_SPRAM_8197F 8 #define BIT_MASK_PCI_SPRAM_8197F 0x3 -#define BIT_PCI_SPRAM_8197F(x) (((x) & BIT_MASK_PCI_SPRAM_8197F) << BIT_SHIFT_PCI_SPRAM_8197F) -#define BITS_PCI_SPRAM_8197F (BIT_MASK_PCI_SPRAM_8197F << BIT_SHIFT_PCI_SPRAM_8197F) +#define BIT_PCI_SPRAM_8197F(x) \ + (((x) & BIT_MASK_PCI_SPRAM_8197F) << BIT_SHIFT_PCI_SPRAM_8197F) +#define BITS_PCI_SPRAM_8197F \ + (BIT_MASK_PCI_SPRAM_8197F << BIT_SHIFT_PCI_SPRAM_8197F) #define BIT_CLEAR_PCI_SPRAM_8197F(x) ((x) & (~BITS_PCI_SPRAM_8197F)) -#define BIT_GET_PCI_SPRAM_8197F(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8197F) & BIT_MASK_PCI_SPRAM_8197F) -#define BIT_SET_PCI_SPRAM_8197F(x, v) (BIT_CLEAR_PCI_SPRAM_8197F(x) | BIT_PCI_SPRAM_8197F(v)) - +#define BIT_GET_PCI_SPRAM_8197F(x) \ + (((x) >> BIT_SHIFT_PCI_SPRAM_8197F) & BIT_MASK_PCI_SPRAM_8197F) +#define BIT_SET_PCI_SPRAM_8197F(x, v) \ + (BIT_CLEAR_PCI_SPRAM_8197F(x) | BIT_PCI_SPRAM_8197F(v)) #define BIT_SHIFT_USB_SPRAM_8197F 6 #define BIT_MASK_USB_SPRAM_8197F 0x3 -#define BIT_USB_SPRAM_8197F(x) (((x) & BIT_MASK_USB_SPRAM_8197F) << BIT_SHIFT_USB_SPRAM_8197F) -#define BITS_USB_SPRAM_8197F (BIT_MASK_USB_SPRAM_8197F << BIT_SHIFT_USB_SPRAM_8197F) +#define BIT_USB_SPRAM_8197F(x) \ + (((x) & BIT_MASK_USB_SPRAM_8197F) << BIT_SHIFT_USB_SPRAM_8197F) +#define BITS_USB_SPRAM_8197F \ + (BIT_MASK_USB_SPRAM_8197F << BIT_SHIFT_USB_SPRAM_8197F) #define BIT_CLEAR_USB_SPRAM_8197F(x) ((x) & (~BITS_USB_SPRAM_8197F)) -#define BIT_GET_USB_SPRAM_8197F(x) (((x) >> BIT_SHIFT_USB_SPRAM_8197F) & BIT_MASK_USB_SPRAM_8197F) -#define BIT_SET_USB_SPRAM_8197F(x, v) (BIT_CLEAR_USB_SPRAM_8197F(x) | BIT_USB_SPRAM_8197F(v)) - +#define BIT_GET_USB_SPRAM_8197F(x) \ + (((x) >> BIT_SHIFT_USB_SPRAM_8197F) & BIT_MASK_USB_SPRAM_8197F) +#define BIT_SET_USB_SPRAM_8197F(x, v) \ + (BIT_CLEAR_USB_SPRAM_8197F(x) | BIT_USB_SPRAM_8197F(v)) #define BIT_SHIFT_USB_SPRF_8197F 4 #define BIT_MASK_USB_SPRF_8197F 0x3 -#define BIT_USB_SPRF_8197F(x) (((x) & BIT_MASK_USB_SPRF_8197F) << BIT_SHIFT_USB_SPRF_8197F) -#define BITS_USB_SPRF_8197F (BIT_MASK_USB_SPRF_8197F << BIT_SHIFT_USB_SPRF_8197F) +#define BIT_USB_SPRF_8197F(x) \ + (((x) & BIT_MASK_USB_SPRF_8197F) << BIT_SHIFT_USB_SPRF_8197F) +#define BITS_USB_SPRF_8197F \ + (BIT_MASK_USB_SPRF_8197F << BIT_SHIFT_USB_SPRF_8197F) #define BIT_CLEAR_USB_SPRF_8197F(x) ((x) & (~BITS_USB_SPRF_8197F)) -#define BIT_GET_USB_SPRF_8197F(x) (((x) >> BIT_SHIFT_USB_SPRF_8197F) & BIT_MASK_USB_SPRF_8197F) -#define BIT_SET_USB_SPRF_8197F(x, v) (BIT_CLEAR_USB_SPRF_8197F(x) | BIT_USB_SPRF_8197F(v)) - +#define BIT_GET_USB_SPRF_8197F(x) \ + (((x) >> BIT_SHIFT_USB_SPRF_8197F) & BIT_MASK_USB_SPRF_8197F) +#define BIT_SET_USB_SPRF_8197F(x, v) \ + (BIT_CLEAR_USB_SPRF_8197F(x) | BIT_USB_SPRF_8197F(v)) #define BIT_SHIFT_MCU_ROM_8197F 0 #define BIT_MASK_MCU_ROM_8197F 0xf -#define BIT_MCU_ROM_8197F(x) (((x) & BIT_MASK_MCU_ROM_8197F) << BIT_SHIFT_MCU_ROM_8197F) +#define BIT_MCU_ROM_8197F(x) \ + (((x) & BIT_MASK_MCU_ROM_8197F) << BIT_SHIFT_MCU_ROM_8197F) #define BITS_MCU_ROM_8197F (BIT_MASK_MCU_ROM_8197F << BIT_SHIFT_MCU_ROM_8197F) #define BIT_CLEAR_MCU_ROM_8197F(x) ((x) & (~BITS_MCU_ROM_8197F)) -#define BIT_GET_MCU_ROM_8197F(x) (((x) >> BIT_SHIFT_MCU_ROM_8197F) & BIT_MASK_MCU_ROM_8197F) -#define BIT_SET_MCU_ROM_8197F(x, v) (BIT_CLEAR_MCU_ROM_8197F(x) | BIT_MCU_ROM_8197F(v)) - +#define BIT_GET_MCU_ROM_8197F(x) \ + (((x) >> BIT_SHIFT_MCU_ROM_8197F) & BIT_MASK_MCU_ROM_8197F) +#define BIT_SET_MCU_ROM_8197F(x, v) \ + (BIT_CLEAR_MCU_ROM_8197F(x) | BIT_MCU_ROM_8197F(v)) /* 2 REG_AFE_CTRL8_8197F */ #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F 26 #define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) -#define BITS_BB_DBG_SEL_AFE_SDM_V4_8197F (BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) -#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4_8197F)) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4_8197F(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F) -#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4_8197F(x, v) (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) | BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(v)) +#define BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) +#define BITS_BB_DBG_SEL_AFE_SDM_V4_8197F \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) \ + ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4_8197F)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4_8197F(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4_8197F(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) | \ + BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(v)) #define BIT_SYN_AGPIO_8197F BIT(20) #define BIT_SHIFT_XTAL_SEL_TOK_V2_8197F 0 #define BIT_MASK_XTAL_SEL_TOK_V2_8197F 0x7 -#define BIT_XTAL_SEL_TOK_V2_8197F(x) (((x) & BIT_MASK_XTAL_SEL_TOK_V2_8197F) << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) -#define BITS_XTAL_SEL_TOK_V2_8197F (BIT_MASK_XTAL_SEL_TOK_V2_8197F << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) +#define BIT_XTAL_SEL_TOK_V2_8197F(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_V2_8197F) \ + << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) +#define BITS_XTAL_SEL_TOK_V2_8197F \ + (BIT_MASK_XTAL_SEL_TOK_V2_8197F << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) #define BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) ((x) & (~BITS_XTAL_SEL_TOK_V2_8197F)) -#define BIT_GET_XTAL_SEL_TOK_V2_8197F(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) & BIT_MASK_XTAL_SEL_TOK_V2_8197F) -#define BIT_SET_XTAL_SEL_TOK_V2_8197F(x, v) (BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) | BIT_XTAL_SEL_TOK_V2_8197F(v)) - +#define BIT_GET_XTAL_SEL_TOK_V2_8197F(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) & \ + BIT_MASK_XTAL_SEL_TOK_V2_8197F) +#define BIT_SET_XTAL_SEL_TOK_V2_8197F(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) | BIT_XTAL_SEL_TOK_V2_8197F(v)) /* 2 REG_USB_SIE_INTF_8197F */ @@ -1721,32 +2118,41 @@ #define BIT_SHIFT_PCIE_MIO_WE_8197F 8 #define BIT_MASK_PCIE_MIO_WE_8197F 0xf -#define BIT_PCIE_MIO_WE_8197F(x) (((x) & BIT_MASK_PCIE_MIO_WE_8197F) << BIT_SHIFT_PCIE_MIO_WE_8197F) -#define BITS_PCIE_MIO_WE_8197F (BIT_MASK_PCIE_MIO_WE_8197F << BIT_SHIFT_PCIE_MIO_WE_8197F) +#define BIT_PCIE_MIO_WE_8197F(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE_8197F) << BIT_SHIFT_PCIE_MIO_WE_8197F) +#define BITS_PCIE_MIO_WE_8197F \ + (BIT_MASK_PCIE_MIO_WE_8197F << BIT_SHIFT_PCIE_MIO_WE_8197F) #define BIT_CLEAR_PCIE_MIO_WE_8197F(x) ((x) & (~BITS_PCIE_MIO_WE_8197F)) -#define BIT_GET_PCIE_MIO_WE_8197F(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8197F) & BIT_MASK_PCIE_MIO_WE_8197F) -#define BIT_SET_PCIE_MIO_WE_8197F(x, v) (BIT_CLEAR_PCIE_MIO_WE_8197F(x) | BIT_PCIE_MIO_WE_8197F(v)) - +#define BIT_GET_PCIE_MIO_WE_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE_8197F) & BIT_MASK_PCIE_MIO_WE_8197F) +#define BIT_SET_PCIE_MIO_WE_8197F(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE_8197F(x) | BIT_PCIE_MIO_WE_8197F(v)) #define BIT_SHIFT_PCIE_MIO_ADDR_8197F 0 #define BIT_MASK_PCIE_MIO_ADDR_8197F 0xff -#define BIT_PCIE_MIO_ADDR_8197F(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8197F) << BIT_SHIFT_PCIE_MIO_ADDR_8197F) -#define BITS_PCIE_MIO_ADDR_8197F (BIT_MASK_PCIE_MIO_ADDR_8197F << BIT_SHIFT_PCIE_MIO_ADDR_8197F) +#define BIT_PCIE_MIO_ADDR_8197F(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_8197F) << BIT_SHIFT_PCIE_MIO_ADDR_8197F) +#define BITS_PCIE_MIO_ADDR_8197F \ + (BIT_MASK_PCIE_MIO_ADDR_8197F << BIT_SHIFT_PCIE_MIO_ADDR_8197F) #define BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) ((x) & (~BITS_PCIE_MIO_ADDR_8197F)) -#define BIT_GET_PCIE_MIO_ADDR_8197F(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8197F) & BIT_MASK_PCIE_MIO_ADDR_8197F) -#define BIT_SET_PCIE_MIO_ADDR_8197F(x, v) (BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) | BIT_PCIE_MIO_ADDR_8197F(v)) - +#define BIT_GET_PCIE_MIO_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8197F) & BIT_MASK_PCIE_MIO_ADDR_8197F) +#define BIT_SET_PCIE_MIO_ADDR_8197F(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) | BIT_PCIE_MIO_ADDR_8197F(v)) /* 2 REG_PCIE_MIO_INTD_8197F */ #define BIT_SHIFT_PCIE_MIO_DATA_8197F 0 #define BIT_MASK_PCIE_MIO_DATA_8197F 0xffffffffL -#define BIT_PCIE_MIO_DATA_8197F(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8197F) << BIT_SHIFT_PCIE_MIO_DATA_8197F) -#define BITS_PCIE_MIO_DATA_8197F (BIT_MASK_PCIE_MIO_DATA_8197F << BIT_SHIFT_PCIE_MIO_DATA_8197F) +#define BIT_PCIE_MIO_DATA_8197F(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA_8197F) << BIT_SHIFT_PCIE_MIO_DATA_8197F) +#define BITS_PCIE_MIO_DATA_8197F \ + (BIT_MASK_PCIE_MIO_DATA_8197F << BIT_SHIFT_PCIE_MIO_DATA_8197F) #define BIT_CLEAR_PCIE_MIO_DATA_8197F(x) ((x) & (~BITS_PCIE_MIO_DATA_8197F)) -#define BIT_GET_PCIE_MIO_DATA_8197F(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8197F) & BIT_MASK_PCIE_MIO_DATA_8197F) -#define BIT_SET_PCIE_MIO_DATA_8197F(x, v) (BIT_CLEAR_PCIE_MIO_DATA_8197F(x) | BIT_PCIE_MIO_DATA_8197F(v)) - +#define BIT_GET_PCIE_MIO_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8197F) & BIT_MASK_PCIE_MIO_DATA_8197F) +#define BIT_SET_PCIE_MIO_DATA_8197F(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA_8197F(x) | BIT_PCIE_MIO_DATA_8197F(v)) /* 2 REG_WLRF1_8197F */ @@ -1754,11 +2160,15 @@ #define BIT_SHIFT_TRP_ICFG_8197F 28 #define BIT_MASK_TRP_ICFG_8197F 0xf -#define BIT_TRP_ICFG_8197F(x) (((x) & BIT_MASK_TRP_ICFG_8197F) << BIT_SHIFT_TRP_ICFG_8197F) -#define BITS_TRP_ICFG_8197F (BIT_MASK_TRP_ICFG_8197F << BIT_SHIFT_TRP_ICFG_8197F) +#define BIT_TRP_ICFG_8197F(x) \ + (((x) & BIT_MASK_TRP_ICFG_8197F) << BIT_SHIFT_TRP_ICFG_8197F) +#define BITS_TRP_ICFG_8197F \ + (BIT_MASK_TRP_ICFG_8197F << BIT_SHIFT_TRP_ICFG_8197F) #define BIT_CLEAR_TRP_ICFG_8197F(x) ((x) & (~BITS_TRP_ICFG_8197F)) -#define BIT_GET_TRP_ICFG_8197F(x) (((x) >> BIT_SHIFT_TRP_ICFG_8197F) & BIT_MASK_TRP_ICFG_8197F) -#define BIT_SET_TRP_ICFG_8197F(x, v) (BIT_CLEAR_TRP_ICFG_8197F(x) | BIT_TRP_ICFG_8197F(v)) +#define BIT_GET_TRP_ICFG_8197F(x) \ + (((x) >> BIT_SHIFT_TRP_ICFG_8197F) & BIT_MASK_TRP_ICFG_8197F) +#define BIT_SET_TRP_ICFG_8197F(x, v) \ + (BIT_CLEAR_TRP_ICFG_8197F(x) | BIT_TRP_ICFG_8197F(v)) #define BIT_RF_TYPE_ID_8197F BIT(27) #define BIT_BD_HCI_SEL_8197F BIT(26) @@ -1770,20 +2180,27 @@ #define BIT_SHIFT_VENDOR_ID_8197F 16 #define BIT_MASK_VENDOR_ID_8197F 0xf -#define BIT_VENDOR_ID_8197F(x) (((x) & BIT_MASK_VENDOR_ID_8197F) << BIT_SHIFT_VENDOR_ID_8197F) -#define BITS_VENDOR_ID_8197F (BIT_MASK_VENDOR_ID_8197F << BIT_SHIFT_VENDOR_ID_8197F) +#define BIT_VENDOR_ID_8197F(x) \ + (((x) & BIT_MASK_VENDOR_ID_8197F) << BIT_SHIFT_VENDOR_ID_8197F) +#define BITS_VENDOR_ID_8197F \ + (BIT_MASK_VENDOR_ID_8197F << BIT_SHIFT_VENDOR_ID_8197F) #define BIT_CLEAR_VENDOR_ID_8197F(x) ((x) & (~BITS_VENDOR_ID_8197F)) -#define BIT_GET_VENDOR_ID_8197F(x) (((x) >> BIT_SHIFT_VENDOR_ID_8197F) & BIT_MASK_VENDOR_ID_8197F) -#define BIT_SET_VENDOR_ID_8197F(x, v) (BIT_CLEAR_VENDOR_ID_8197F(x) | BIT_VENDOR_ID_8197F(v)) - +#define BIT_GET_VENDOR_ID_8197F(x) \ + (((x) >> BIT_SHIFT_VENDOR_ID_8197F) & BIT_MASK_VENDOR_ID_8197F) +#define BIT_SET_VENDOR_ID_8197F(x, v) \ + (BIT_CLEAR_VENDOR_ID_8197F(x) | BIT_VENDOR_ID_8197F(v)) #define BIT_SHIFT_CHIP_VER_8197F 12 #define BIT_MASK_CHIP_VER_8197F 0xf -#define BIT_CHIP_VER_8197F(x) (((x) & BIT_MASK_CHIP_VER_8197F) << BIT_SHIFT_CHIP_VER_8197F) -#define BITS_CHIP_VER_8197F (BIT_MASK_CHIP_VER_8197F << BIT_SHIFT_CHIP_VER_8197F) +#define BIT_CHIP_VER_8197F(x) \ + (((x) & BIT_MASK_CHIP_VER_8197F) << BIT_SHIFT_CHIP_VER_8197F) +#define BITS_CHIP_VER_8197F \ + (BIT_MASK_CHIP_VER_8197F << BIT_SHIFT_CHIP_VER_8197F) #define BIT_CLEAR_CHIP_VER_8197F(x) ((x) & (~BITS_CHIP_VER_8197F)) -#define BIT_GET_CHIP_VER_8197F(x) (((x) >> BIT_SHIFT_CHIP_VER_8197F) & BIT_MASK_CHIP_VER_8197F) -#define BIT_SET_CHIP_VER_8197F(x, v) (BIT_CLEAR_CHIP_VER_8197F(x) | BIT_CHIP_VER_8197F(v)) +#define BIT_GET_CHIP_VER_8197F(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_8197F) & BIT_MASK_CHIP_VER_8197F) +#define BIT_SET_CHIP_VER_8197F(x, v) \ + (BIT_CLEAR_CHIP_VER_8197F(x) | BIT_CHIP_VER_8197F(v)) #define BIT_BD_MAC1_8197F BIT(10) #define BIT_BD_MAC2_8197F BIT(9) @@ -1801,21 +2218,29 @@ #define BIT_SHIFT_RF_RL_ID_8197F 28 #define BIT_MASK_RF_RL_ID_8197F 0xf -#define BIT_RF_RL_ID_8197F(x) (((x) & BIT_MASK_RF_RL_ID_8197F) << BIT_SHIFT_RF_RL_ID_8197F) -#define BITS_RF_RL_ID_8197F (BIT_MASK_RF_RL_ID_8197F << BIT_SHIFT_RF_RL_ID_8197F) +#define BIT_RF_RL_ID_8197F(x) \ + (((x) & BIT_MASK_RF_RL_ID_8197F) << BIT_SHIFT_RF_RL_ID_8197F) +#define BITS_RF_RL_ID_8197F \ + (BIT_MASK_RF_RL_ID_8197F << BIT_SHIFT_RF_RL_ID_8197F) #define BIT_CLEAR_RF_RL_ID_8197F(x) ((x) & (~BITS_RF_RL_ID_8197F)) -#define BIT_GET_RF_RL_ID_8197F(x) (((x) >> BIT_SHIFT_RF_RL_ID_8197F) & BIT_MASK_RF_RL_ID_8197F) -#define BIT_SET_RF_RL_ID_8197F(x, v) (BIT_CLEAR_RF_RL_ID_8197F(x) | BIT_RF_RL_ID_8197F(v)) +#define BIT_GET_RF_RL_ID_8197F(x) \ + (((x) >> BIT_SHIFT_RF_RL_ID_8197F) & BIT_MASK_RF_RL_ID_8197F) +#define BIT_SET_RF_RL_ID_8197F(x, v) \ + (BIT_CLEAR_RF_RL_ID_8197F(x) | BIT_RF_RL_ID_8197F(v)) #define BIT_HPHY_ICFG_8197F BIT(19) #define BIT_SHIFT_SEL_0XC0_8197F 16 #define BIT_MASK_SEL_0XC0_8197F 0x3 -#define BIT_SEL_0XC0_8197F(x) (((x) & BIT_MASK_SEL_0XC0_8197F) << BIT_SHIFT_SEL_0XC0_8197F) -#define BITS_SEL_0XC0_8197F (BIT_MASK_SEL_0XC0_8197F << BIT_SHIFT_SEL_0XC0_8197F) +#define BIT_SEL_0XC0_8197F(x) \ + (((x) & BIT_MASK_SEL_0XC0_8197F) << BIT_SHIFT_SEL_0XC0_8197F) +#define BITS_SEL_0XC0_8197F \ + (BIT_MASK_SEL_0XC0_8197F << BIT_SHIFT_SEL_0XC0_8197F) #define BIT_CLEAR_SEL_0XC0_8197F(x) ((x) & (~BITS_SEL_0XC0_8197F)) -#define BIT_GET_SEL_0XC0_8197F(x) (((x) >> BIT_SHIFT_SEL_0XC0_8197F) & BIT_MASK_SEL_0XC0_8197F) -#define BIT_SET_SEL_0XC0_8197F(x, v) (BIT_CLEAR_SEL_0XC0_8197F(x) | BIT_SEL_0XC0_8197F(v)) +#define BIT_GET_SEL_0XC0_8197F(x) \ + (((x) >> BIT_SHIFT_SEL_0XC0_8197F) & BIT_MASK_SEL_0XC0_8197F) +#define BIT_SET_SEL_0XC0_8197F(x, v) \ + (BIT_CLEAR_SEL_0XC0_8197F(x) | BIT_SEL_0XC0_8197F(v)) #define BIT_USB_OPERATION_MODE_8197F BIT(10) #define BIT_BT_PDN_8197F BIT(9) @@ -1825,30 +2250,38 @@ #define BIT_SHIFT_HCI_SEL_8197F 4 #define BIT_MASK_HCI_SEL_8197F 0x3 -#define BIT_HCI_SEL_8197F(x) (((x) & BIT_MASK_HCI_SEL_8197F) << BIT_SHIFT_HCI_SEL_8197F) +#define BIT_HCI_SEL_8197F(x) \ + (((x) & BIT_MASK_HCI_SEL_8197F) << BIT_SHIFT_HCI_SEL_8197F) #define BITS_HCI_SEL_8197F (BIT_MASK_HCI_SEL_8197F << BIT_SHIFT_HCI_SEL_8197F) #define BIT_CLEAR_HCI_SEL_8197F(x) ((x) & (~BITS_HCI_SEL_8197F)) -#define BIT_GET_HCI_SEL_8197F(x) (((x) >> BIT_SHIFT_HCI_SEL_8197F) & BIT_MASK_HCI_SEL_8197F) -#define BIT_SET_HCI_SEL_8197F(x, v) (BIT_CLEAR_HCI_SEL_8197F(x) | BIT_HCI_SEL_8197F(v)) - +#define BIT_GET_HCI_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_8197F) & BIT_MASK_HCI_SEL_8197F) +#define BIT_SET_HCI_SEL_8197F(x, v) \ + (BIT_CLEAR_HCI_SEL_8197F(x) | BIT_HCI_SEL_8197F(v)) #define BIT_SHIFT_PAD_HCI_SEL_8197F 2 #define BIT_MASK_PAD_HCI_SEL_8197F 0x3 -#define BIT_PAD_HCI_SEL_8197F(x) (((x) & BIT_MASK_PAD_HCI_SEL_8197F) << BIT_SHIFT_PAD_HCI_SEL_8197F) -#define BITS_PAD_HCI_SEL_8197F (BIT_MASK_PAD_HCI_SEL_8197F << BIT_SHIFT_PAD_HCI_SEL_8197F) +#define BIT_PAD_HCI_SEL_8197F(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_8197F) << BIT_SHIFT_PAD_HCI_SEL_8197F) +#define BITS_PAD_HCI_SEL_8197F \ + (BIT_MASK_PAD_HCI_SEL_8197F << BIT_SHIFT_PAD_HCI_SEL_8197F) #define BIT_CLEAR_PAD_HCI_SEL_8197F(x) ((x) & (~BITS_PAD_HCI_SEL_8197F)) -#define BIT_GET_PAD_HCI_SEL_8197F(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_8197F) & BIT_MASK_PAD_HCI_SEL_8197F) -#define BIT_SET_PAD_HCI_SEL_8197F(x, v) (BIT_CLEAR_PAD_HCI_SEL_8197F(x) | BIT_PAD_HCI_SEL_8197F(v)) - +#define BIT_GET_PAD_HCI_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_8197F) & BIT_MASK_PAD_HCI_SEL_8197F) +#define BIT_SET_PAD_HCI_SEL_8197F(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_8197F(x) | BIT_PAD_HCI_SEL_8197F(v)) #define BIT_SHIFT_EFS_HCI_SEL_8197F 0 #define BIT_MASK_EFS_HCI_SEL_8197F 0x3 -#define BIT_EFS_HCI_SEL_8197F(x) (((x) & BIT_MASK_EFS_HCI_SEL_8197F) << BIT_SHIFT_EFS_HCI_SEL_8197F) -#define BITS_EFS_HCI_SEL_8197F (BIT_MASK_EFS_HCI_SEL_8197F << BIT_SHIFT_EFS_HCI_SEL_8197F) +#define BIT_EFS_HCI_SEL_8197F(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_8197F) << BIT_SHIFT_EFS_HCI_SEL_8197F) +#define BITS_EFS_HCI_SEL_8197F \ + (BIT_MASK_EFS_HCI_SEL_8197F << BIT_SHIFT_EFS_HCI_SEL_8197F) #define BIT_CLEAR_EFS_HCI_SEL_8197F(x) ((x) & (~BITS_EFS_HCI_SEL_8197F)) -#define BIT_GET_EFS_HCI_SEL_8197F(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_8197F) & BIT_MASK_EFS_HCI_SEL_8197F) -#define BIT_SET_EFS_HCI_SEL_8197F(x, v) (BIT_CLEAR_EFS_HCI_SEL_8197F(x) | BIT_EFS_HCI_SEL_8197F(v)) - +#define BIT_GET_EFS_HCI_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_8197F) & BIT_MASK_EFS_HCI_SEL_8197F) +#define BIT_SET_EFS_HCI_SEL_8197F(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_8197F(x) | BIT_EFS_HCI_SEL_8197F(v)) /* 2 REG_SYS_STATUS2_8197F */ #define BIT_SIO_ALDN_8197F BIT(19) @@ -1858,32 +2291,38 @@ #define BIT_SHIFT_EPVID1_8197F 8 #define BIT_MASK_EPVID1_8197F 0xff -#define BIT_EPVID1_8197F(x) (((x) & BIT_MASK_EPVID1_8197F) << BIT_SHIFT_EPVID1_8197F) +#define BIT_EPVID1_8197F(x) \ + (((x) & BIT_MASK_EPVID1_8197F) << BIT_SHIFT_EPVID1_8197F) #define BITS_EPVID1_8197F (BIT_MASK_EPVID1_8197F << BIT_SHIFT_EPVID1_8197F) #define BIT_CLEAR_EPVID1_8197F(x) ((x) & (~BITS_EPVID1_8197F)) -#define BIT_GET_EPVID1_8197F(x) (((x) >> BIT_SHIFT_EPVID1_8197F) & BIT_MASK_EPVID1_8197F) -#define BIT_SET_EPVID1_8197F(x, v) (BIT_CLEAR_EPVID1_8197F(x) | BIT_EPVID1_8197F(v)) - +#define BIT_GET_EPVID1_8197F(x) \ + (((x) >> BIT_SHIFT_EPVID1_8197F) & BIT_MASK_EPVID1_8197F) +#define BIT_SET_EPVID1_8197F(x, v) \ + (BIT_CLEAR_EPVID1_8197F(x) | BIT_EPVID1_8197F(v)) #define BIT_SHIFT_EPVID0_8197F 0 #define BIT_MASK_EPVID0_8197F 0xff -#define BIT_EPVID0_8197F(x) (((x) & BIT_MASK_EPVID0_8197F) << BIT_SHIFT_EPVID0_8197F) +#define BIT_EPVID0_8197F(x) \ + (((x) & BIT_MASK_EPVID0_8197F) << BIT_SHIFT_EPVID0_8197F) #define BITS_EPVID0_8197F (BIT_MASK_EPVID0_8197F << BIT_SHIFT_EPVID0_8197F) #define BIT_CLEAR_EPVID0_8197F(x) ((x) & (~BITS_EPVID0_8197F)) -#define BIT_GET_EPVID0_8197F(x) (((x) >> BIT_SHIFT_EPVID0_8197F) & BIT_MASK_EPVID0_8197F) -#define BIT_SET_EPVID0_8197F(x, v) (BIT_CLEAR_EPVID0_8197F(x) | BIT_EPVID0_8197F(v)) - +#define BIT_GET_EPVID0_8197F(x) \ + (((x) >> BIT_SHIFT_EPVID0_8197F) & BIT_MASK_EPVID0_8197F) +#define BIT_SET_EPVID0_8197F(x, v) \ + (BIT_CLEAR_EPVID0_8197F(x) | BIT_EPVID0_8197F(v)) /* 2 REG_SYS_CFG2_8197F */ #define BIT_SHIFT_HW_ID_8197F 0 #define BIT_MASK_HW_ID_8197F 0xff -#define BIT_HW_ID_8197F(x) (((x) & BIT_MASK_HW_ID_8197F) << BIT_SHIFT_HW_ID_8197F) +#define BIT_HW_ID_8197F(x) \ + (((x) & BIT_MASK_HW_ID_8197F) << BIT_SHIFT_HW_ID_8197F) #define BITS_HW_ID_8197F (BIT_MASK_HW_ID_8197F << BIT_SHIFT_HW_ID_8197F) #define BIT_CLEAR_HW_ID_8197F(x) ((x) & (~BITS_HW_ID_8197F)) -#define BIT_GET_HW_ID_8197F(x) (((x) >> BIT_SHIFT_HW_ID_8197F) & BIT_MASK_HW_ID_8197F) -#define BIT_SET_HW_ID_8197F(x, v) (BIT_CLEAR_HW_ID_8197F(x) | BIT_HW_ID_8197F(v)) - +#define BIT_GET_HW_ID_8197F(x) \ + (((x) >> BIT_SHIFT_HW_ID_8197F) & BIT_MASK_HW_ID_8197F) +#define BIT_SET_HW_ID_8197F(x, v) \ + (BIT_CLEAR_HW_ID_8197F(x) | BIT_HW_ID_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -1899,12 +2338,15 @@ #define BIT_SHIFT_CPU_DMEM_CON_8197F 0 #define BIT_MASK_CPU_DMEM_CON_8197F 0xff -#define BIT_CPU_DMEM_CON_8197F(x) (((x) & BIT_MASK_CPU_DMEM_CON_8197F) << BIT_SHIFT_CPU_DMEM_CON_8197F) -#define BITS_CPU_DMEM_CON_8197F (BIT_MASK_CPU_DMEM_CON_8197F << BIT_SHIFT_CPU_DMEM_CON_8197F) +#define BIT_CPU_DMEM_CON_8197F(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON_8197F) << BIT_SHIFT_CPU_DMEM_CON_8197F) +#define BITS_CPU_DMEM_CON_8197F \ + (BIT_MASK_CPU_DMEM_CON_8197F << BIT_SHIFT_CPU_DMEM_CON_8197F) #define BIT_CLEAR_CPU_DMEM_CON_8197F(x) ((x) & (~BITS_CPU_DMEM_CON_8197F)) -#define BIT_GET_CPU_DMEM_CON_8197F(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8197F) & BIT_MASK_CPU_DMEM_CON_8197F) -#define BIT_SET_CPU_DMEM_CON_8197F(x, v) (BIT_CLEAR_CPU_DMEM_CON_8197F(x) | BIT_CPU_DMEM_CON_8197F(v)) - +#define BIT_GET_CPU_DMEM_CON_8197F(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON_8197F) & BIT_MASK_CPU_DMEM_CON_8197F) +#define BIT_SET_CPU_DMEM_CON_8197F(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON_8197F(x) | BIT_CPU_DMEM_CON_8197F(v)) /* 2 REG_HIMR2_8197F */ #define BIT_BCNDMAINT_P4_MSK_8197F BIT(31) @@ -2019,86 +2461,129 @@ #define BIT_SHIFT_DBG_GPIO_BMUX_7_8197F 21 #define BIT_MASK_DBG_GPIO_BMUX_7_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_7_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_7_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) -#define BITS_DBG_GPIO_BMUX_7_8197F (BIT_MASK_DBG_GPIO_BMUX_7_8197F << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) +#define BIT_DBG_GPIO_BMUX_7_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_7_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) +#define BITS_DBG_GPIO_BMUX_7_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_7_8197F << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_7_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_7_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) & BIT_MASK_DBG_GPIO_BMUX_7_8197F) -#define BIT_SET_DBG_GPIO_BMUX_7_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) | BIT_DBG_GPIO_BMUX_7_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_7_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_7_8197F) +#define BIT_SET_DBG_GPIO_BMUX_7_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) | BIT_DBG_GPIO_BMUX_7_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_6_8197F 18 #define BIT_MASK_DBG_GPIO_BMUX_6_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_6_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_6_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) -#define BITS_DBG_GPIO_BMUX_6_8197F (BIT_MASK_DBG_GPIO_BMUX_6_8197F << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) +#define BIT_DBG_GPIO_BMUX_6_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_6_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) +#define BITS_DBG_GPIO_BMUX_6_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_6_8197F << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_6_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_6_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) & BIT_MASK_DBG_GPIO_BMUX_6_8197F) -#define BIT_SET_DBG_GPIO_BMUX_6_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) | BIT_DBG_GPIO_BMUX_6_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_6_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_6_8197F) +#define BIT_SET_DBG_GPIO_BMUX_6_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) | BIT_DBG_GPIO_BMUX_6_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_5_8197F 15 #define BIT_MASK_DBG_GPIO_BMUX_5_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_5_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_5_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) -#define BITS_DBG_GPIO_BMUX_5_8197F (BIT_MASK_DBG_GPIO_BMUX_5_8197F << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) +#define BIT_DBG_GPIO_BMUX_5_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_5_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) +#define BITS_DBG_GPIO_BMUX_5_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_5_8197F << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_5_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_5_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) & BIT_MASK_DBG_GPIO_BMUX_5_8197F) -#define BIT_SET_DBG_GPIO_BMUX_5_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) | BIT_DBG_GPIO_BMUX_5_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_5_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_5_8197F) +#define BIT_SET_DBG_GPIO_BMUX_5_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) | BIT_DBG_GPIO_BMUX_5_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_4_8197F 12 #define BIT_MASK_DBG_GPIO_BMUX_4_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_4_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_4_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) -#define BITS_DBG_GPIO_BMUX_4_8197F (BIT_MASK_DBG_GPIO_BMUX_4_8197F << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) +#define BIT_DBG_GPIO_BMUX_4_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_4_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) +#define BITS_DBG_GPIO_BMUX_4_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_4_8197F << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_4_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_4_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) & BIT_MASK_DBG_GPIO_BMUX_4_8197F) -#define BIT_SET_DBG_GPIO_BMUX_4_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) | BIT_DBG_GPIO_BMUX_4_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_4_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_4_8197F) +#define BIT_SET_DBG_GPIO_BMUX_4_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) | BIT_DBG_GPIO_BMUX_4_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_3_8197F 9 #define BIT_MASK_DBG_GPIO_BMUX_3_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_3_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_3_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) -#define BITS_DBG_GPIO_BMUX_3_8197F (BIT_MASK_DBG_GPIO_BMUX_3_8197F << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) +#define BIT_DBG_GPIO_BMUX_3_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_3_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) +#define BITS_DBG_GPIO_BMUX_3_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_3_8197F << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_3_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_3_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) & BIT_MASK_DBG_GPIO_BMUX_3_8197F) -#define BIT_SET_DBG_GPIO_BMUX_3_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) | BIT_DBG_GPIO_BMUX_3_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_3_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_3_8197F) +#define BIT_SET_DBG_GPIO_BMUX_3_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) | BIT_DBG_GPIO_BMUX_3_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_2_8197F 6 #define BIT_MASK_DBG_GPIO_BMUX_2_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_2_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_2_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) -#define BITS_DBG_GPIO_BMUX_2_8197F (BIT_MASK_DBG_GPIO_BMUX_2_8197F << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) +#define BIT_DBG_GPIO_BMUX_2_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_2_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) +#define BITS_DBG_GPIO_BMUX_2_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_2_8197F << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_2_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_2_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) & BIT_MASK_DBG_GPIO_BMUX_2_8197F) -#define BIT_SET_DBG_GPIO_BMUX_2_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) | BIT_DBG_GPIO_BMUX_2_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_2_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_2_8197F) +#define BIT_SET_DBG_GPIO_BMUX_2_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) | BIT_DBG_GPIO_BMUX_2_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_1_8197F 3 #define BIT_MASK_DBG_GPIO_BMUX_1_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_1_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_1_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) -#define BITS_DBG_GPIO_BMUX_1_8197F (BIT_MASK_DBG_GPIO_BMUX_1_8197F << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) +#define BIT_DBG_GPIO_BMUX_1_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_1_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) +#define BITS_DBG_GPIO_BMUX_1_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_1_8197F << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_1_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_1_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) & BIT_MASK_DBG_GPIO_BMUX_1_8197F) -#define BIT_SET_DBG_GPIO_BMUX_1_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) | BIT_DBG_GPIO_BMUX_1_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_1_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_1_8197F) +#define BIT_SET_DBG_GPIO_BMUX_1_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) | BIT_DBG_GPIO_BMUX_1_8197F(v)) #define BIT_SHIFT_DBG_GPIO_BMUX_0_8197F 0 #define BIT_MASK_DBG_GPIO_BMUX_0_8197F 0x7 -#define BIT_DBG_GPIO_BMUX_0_8197F(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_0_8197F) << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) -#define BITS_DBG_GPIO_BMUX_0_8197F (BIT_MASK_DBG_GPIO_BMUX_0_8197F << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) +#define BIT_DBG_GPIO_BMUX_0_8197F(x) \ + (((x) & BIT_MASK_DBG_GPIO_BMUX_0_8197F) \ + << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) +#define BITS_DBG_GPIO_BMUX_0_8197F \ + (BIT_MASK_DBG_GPIO_BMUX_0_8197F << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) #define BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_0_8197F)) -#define BIT_GET_DBG_GPIO_BMUX_0_8197F(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) & BIT_MASK_DBG_GPIO_BMUX_0_8197F) -#define BIT_SET_DBG_GPIO_BMUX_0_8197F(x, v) (BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) | BIT_DBG_GPIO_BMUX_0_8197F(v)) - +#define BIT_GET_DBG_GPIO_BMUX_0_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) & \ + BIT_MASK_DBG_GPIO_BMUX_0_8197F) +#define BIT_SET_DBG_GPIO_BMUX_0_8197F(x, v) \ + (BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) | BIT_DBG_GPIO_BMUX_0_8197F(v)) /* 2 REG_FPGA_TAG_8197F (NO USE IN ASIC) */ #define BIT_SHIFT_FPGA_TAG_8197F 0 #define BIT_MASK_FPGA_TAG_8197F 0xffffffffL -#define BIT_FPGA_TAG_8197F(x) (((x) & BIT_MASK_FPGA_TAG_8197F) << BIT_SHIFT_FPGA_TAG_8197F) -#define BITS_FPGA_TAG_8197F (BIT_MASK_FPGA_TAG_8197F << BIT_SHIFT_FPGA_TAG_8197F) +#define BIT_FPGA_TAG_8197F(x) \ + (((x) & BIT_MASK_FPGA_TAG_8197F) << BIT_SHIFT_FPGA_TAG_8197F) +#define BITS_FPGA_TAG_8197F \ + (BIT_MASK_FPGA_TAG_8197F << BIT_SHIFT_FPGA_TAG_8197F) #define BIT_CLEAR_FPGA_TAG_8197F(x) ((x) & (~BITS_FPGA_TAG_8197F)) -#define BIT_GET_FPGA_TAG_8197F(x) (((x) >> BIT_SHIFT_FPGA_TAG_8197F) & BIT_MASK_FPGA_TAG_8197F) -#define BIT_SET_FPGA_TAG_8197F(x, v) (BIT_CLEAR_FPGA_TAG_8197F(x) | BIT_FPGA_TAG_8197F(v)) - +#define BIT_GET_FPGA_TAG_8197F(x) \ + (((x) >> BIT_SHIFT_FPGA_TAG_8197F) & BIT_MASK_FPGA_TAG_8197F) +#define BIT_SET_FPGA_TAG_8197F(x, v) \ + (BIT_CLEAR_FPGA_TAG_8197F(x) | BIT_FPGA_TAG_8197F(v)) /* 2 REG_WL_DSS_CTRL0_8197F */ #define BIT_WL_DSS_RSTN_8197F BIT(27) @@ -2107,12 +2592,18 @@ #define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0 #define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff -#define BIT_WL_DSS_COUNT_OUT_8197F(x) (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) -#define BITS_WL_DSS_COUNT_OUT_8197F (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) -#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F)) -#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) -#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v)) - +#define BIT_WL_DSS_COUNT_OUT_8197F(x) \ + (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) \ + << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BITS_WL_DSS_COUNT_OUT_8197F \ + (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) \ + ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F)) +#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) \ + (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & \ + BIT_MASK_WL_DSS_COUNT_OUT_8197F) +#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) \ + (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v)) /* 2 REG_WL_DSS_CTRL1_8197F */ #define BIT_WL_DSS_RSTN_8197F BIT(27) @@ -2122,21 +2613,29 @@ #define BIT_SHIFT_WL_DSS_RO_SEL_8197F 20 #define BIT_MASK_WL_DSS_RO_SEL_8197F 0x7 -#define BIT_WL_DSS_RO_SEL_8197F(x) (((x) & BIT_MASK_WL_DSS_RO_SEL_8197F) << BIT_SHIFT_WL_DSS_RO_SEL_8197F) -#define BITS_WL_DSS_RO_SEL_8197F (BIT_MASK_WL_DSS_RO_SEL_8197F << BIT_SHIFT_WL_DSS_RO_SEL_8197F) +#define BIT_WL_DSS_RO_SEL_8197F(x) \ + (((x) & BIT_MASK_WL_DSS_RO_SEL_8197F) << BIT_SHIFT_WL_DSS_RO_SEL_8197F) +#define BITS_WL_DSS_RO_SEL_8197F \ + (BIT_MASK_WL_DSS_RO_SEL_8197F << BIT_SHIFT_WL_DSS_RO_SEL_8197F) #define BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) ((x) & (~BITS_WL_DSS_RO_SEL_8197F)) -#define BIT_GET_WL_DSS_RO_SEL_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_RO_SEL_8197F) & BIT_MASK_WL_DSS_RO_SEL_8197F) -#define BIT_SET_WL_DSS_RO_SEL_8197F(x, v) (BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) | BIT_WL_DSS_RO_SEL_8197F(v)) - +#define BIT_GET_WL_DSS_RO_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WL_DSS_RO_SEL_8197F) & BIT_MASK_WL_DSS_RO_SEL_8197F) +#define BIT_SET_WL_DSS_RO_SEL_8197F(x, v) \ + (BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) | BIT_WL_DSS_RO_SEL_8197F(v)) #define BIT_SHIFT_WL_DSS_DATA_IN_8197F 0 #define BIT_MASK_WL_DSS_DATA_IN_8197F 0xfffff -#define BIT_WL_DSS_DATA_IN_8197F(x) (((x) & BIT_MASK_WL_DSS_DATA_IN_8197F) << BIT_SHIFT_WL_DSS_DATA_IN_8197F) -#define BITS_WL_DSS_DATA_IN_8197F (BIT_MASK_WL_DSS_DATA_IN_8197F << BIT_SHIFT_WL_DSS_DATA_IN_8197F) +#define BIT_WL_DSS_DATA_IN_8197F(x) \ + (((x) & BIT_MASK_WL_DSS_DATA_IN_8197F) \ + << BIT_SHIFT_WL_DSS_DATA_IN_8197F) +#define BITS_WL_DSS_DATA_IN_8197F \ + (BIT_MASK_WL_DSS_DATA_IN_8197F << BIT_SHIFT_WL_DSS_DATA_IN_8197F) #define BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) ((x) & (~BITS_WL_DSS_DATA_IN_8197F)) -#define BIT_GET_WL_DSS_DATA_IN_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_DATA_IN_8197F) & BIT_MASK_WL_DSS_DATA_IN_8197F) -#define BIT_SET_WL_DSS_DATA_IN_8197F(x, v) (BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) | BIT_WL_DSS_DATA_IN_8197F(v)) - +#define BIT_GET_WL_DSS_DATA_IN_8197F(x) \ + (((x) >> BIT_SHIFT_WL_DSS_DATA_IN_8197F) & \ + BIT_MASK_WL_DSS_DATA_IN_8197F) +#define BIT_SET_WL_DSS_DATA_IN_8197F(x, v) \ + (BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) | BIT_WL_DSS_DATA_IN_8197F(v)) /* 2 REG_WL_DSS_STATUS1_8197F */ #define BIT_WL_DSS_READY_8197F BIT(21) @@ -2144,100 +2643,122 @@ #define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0 #define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff -#define BIT_WL_DSS_COUNT_OUT_8197F(x) (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) -#define BITS_WL_DSS_COUNT_OUT_8197F (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) -#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F)) -#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) -#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v)) - +#define BIT_WL_DSS_COUNT_OUT_8197F(x) \ + (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) \ + << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BITS_WL_DSS_COUNT_OUT_8197F \ + (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) +#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) \ + ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F)) +#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) \ + (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & \ + BIT_MASK_WL_DSS_COUNT_OUT_8197F) +#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) \ + (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v)) /* 2 REG_FW_DBG0_8197F */ #define BIT_SHIFT_FW_DBG0_8197F 0 #define BIT_MASK_FW_DBG0_8197F 0xffffffffL -#define BIT_FW_DBG0_8197F(x) (((x) & BIT_MASK_FW_DBG0_8197F) << BIT_SHIFT_FW_DBG0_8197F) +#define BIT_FW_DBG0_8197F(x) \ + (((x) & BIT_MASK_FW_DBG0_8197F) << BIT_SHIFT_FW_DBG0_8197F) #define BITS_FW_DBG0_8197F (BIT_MASK_FW_DBG0_8197F << BIT_SHIFT_FW_DBG0_8197F) #define BIT_CLEAR_FW_DBG0_8197F(x) ((x) & (~BITS_FW_DBG0_8197F)) -#define BIT_GET_FW_DBG0_8197F(x) (((x) >> BIT_SHIFT_FW_DBG0_8197F) & BIT_MASK_FW_DBG0_8197F) -#define BIT_SET_FW_DBG0_8197F(x, v) (BIT_CLEAR_FW_DBG0_8197F(x) | BIT_FW_DBG0_8197F(v)) - +#define BIT_GET_FW_DBG0_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG0_8197F) & BIT_MASK_FW_DBG0_8197F) +#define BIT_SET_FW_DBG0_8197F(x, v) \ + (BIT_CLEAR_FW_DBG0_8197F(x) | BIT_FW_DBG0_8197F(v)) /* 2 REG_FW_DBG1_8197F */ #define BIT_SHIFT_FW_DBG1_8197F 0 #define BIT_MASK_FW_DBG1_8197F 0xffffffffL -#define BIT_FW_DBG1_8197F(x) (((x) & BIT_MASK_FW_DBG1_8197F) << BIT_SHIFT_FW_DBG1_8197F) +#define BIT_FW_DBG1_8197F(x) \ + (((x) & BIT_MASK_FW_DBG1_8197F) << BIT_SHIFT_FW_DBG1_8197F) #define BITS_FW_DBG1_8197F (BIT_MASK_FW_DBG1_8197F << BIT_SHIFT_FW_DBG1_8197F) #define BIT_CLEAR_FW_DBG1_8197F(x) ((x) & (~BITS_FW_DBG1_8197F)) -#define BIT_GET_FW_DBG1_8197F(x) (((x) >> BIT_SHIFT_FW_DBG1_8197F) & BIT_MASK_FW_DBG1_8197F) -#define BIT_SET_FW_DBG1_8197F(x, v) (BIT_CLEAR_FW_DBG1_8197F(x) | BIT_FW_DBG1_8197F(v)) - +#define BIT_GET_FW_DBG1_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG1_8197F) & BIT_MASK_FW_DBG1_8197F) +#define BIT_SET_FW_DBG1_8197F(x, v) \ + (BIT_CLEAR_FW_DBG1_8197F(x) | BIT_FW_DBG1_8197F(v)) /* 2 REG_FW_DBG2_8197F */ #define BIT_SHIFT_FW_DBG2_8197F 0 #define BIT_MASK_FW_DBG2_8197F 0xffffffffL -#define BIT_FW_DBG2_8197F(x) (((x) & BIT_MASK_FW_DBG2_8197F) << BIT_SHIFT_FW_DBG2_8197F) +#define BIT_FW_DBG2_8197F(x) \ + (((x) & BIT_MASK_FW_DBG2_8197F) << BIT_SHIFT_FW_DBG2_8197F) #define BITS_FW_DBG2_8197F (BIT_MASK_FW_DBG2_8197F << BIT_SHIFT_FW_DBG2_8197F) #define BIT_CLEAR_FW_DBG2_8197F(x) ((x) & (~BITS_FW_DBG2_8197F)) -#define BIT_GET_FW_DBG2_8197F(x) (((x) >> BIT_SHIFT_FW_DBG2_8197F) & BIT_MASK_FW_DBG2_8197F) -#define BIT_SET_FW_DBG2_8197F(x, v) (BIT_CLEAR_FW_DBG2_8197F(x) | BIT_FW_DBG2_8197F(v)) - +#define BIT_GET_FW_DBG2_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG2_8197F) & BIT_MASK_FW_DBG2_8197F) +#define BIT_SET_FW_DBG2_8197F(x, v) \ + (BIT_CLEAR_FW_DBG2_8197F(x) | BIT_FW_DBG2_8197F(v)) /* 2 REG_FW_DBG3_8197F */ #define BIT_SHIFT_FW_DBG3_8197F 0 #define BIT_MASK_FW_DBG3_8197F 0xffffffffL -#define BIT_FW_DBG3_8197F(x) (((x) & BIT_MASK_FW_DBG3_8197F) << BIT_SHIFT_FW_DBG3_8197F) +#define BIT_FW_DBG3_8197F(x) \ + (((x) & BIT_MASK_FW_DBG3_8197F) << BIT_SHIFT_FW_DBG3_8197F) #define BITS_FW_DBG3_8197F (BIT_MASK_FW_DBG3_8197F << BIT_SHIFT_FW_DBG3_8197F) #define BIT_CLEAR_FW_DBG3_8197F(x) ((x) & (~BITS_FW_DBG3_8197F)) -#define BIT_GET_FW_DBG3_8197F(x) (((x) >> BIT_SHIFT_FW_DBG3_8197F) & BIT_MASK_FW_DBG3_8197F) -#define BIT_SET_FW_DBG3_8197F(x, v) (BIT_CLEAR_FW_DBG3_8197F(x) | BIT_FW_DBG3_8197F(v)) - +#define BIT_GET_FW_DBG3_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG3_8197F) & BIT_MASK_FW_DBG3_8197F) +#define BIT_SET_FW_DBG3_8197F(x, v) \ + (BIT_CLEAR_FW_DBG3_8197F(x) | BIT_FW_DBG3_8197F(v)) /* 2 REG_FW_DBG4_8197F */ #define BIT_SHIFT_FW_DBG4_8197F 0 #define BIT_MASK_FW_DBG4_8197F 0xffffffffL -#define BIT_FW_DBG4_8197F(x) (((x) & BIT_MASK_FW_DBG4_8197F) << BIT_SHIFT_FW_DBG4_8197F) +#define BIT_FW_DBG4_8197F(x) \ + (((x) & BIT_MASK_FW_DBG4_8197F) << BIT_SHIFT_FW_DBG4_8197F) #define BITS_FW_DBG4_8197F (BIT_MASK_FW_DBG4_8197F << BIT_SHIFT_FW_DBG4_8197F) #define BIT_CLEAR_FW_DBG4_8197F(x) ((x) & (~BITS_FW_DBG4_8197F)) -#define BIT_GET_FW_DBG4_8197F(x) (((x) >> BIT_SHIFT_FW_DBG4_8197F) & BIT_MASK_FW_DBG4_8197F) -#define BIT_SET_FW_DBG4_8197F(x, v) (BIT_CLEAR_FW_DBG4_8197F(x) | BIT_FW_DBG4_8197F(v)) - +#define BIT_GET_FW_DBG4_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG4_8197F) & BIT_MASK_FW_DBG4_8197F) +#define BIT_SET_FW_DBG4_8197F(x, v) \ + (BIT_CLEAR_FW_DBG4_8197F(x) | BIT_FW_DBG4_8197F(v)) /* 2 REG_FW_DBG5_8197F */ #define BIT_SHIFT_FW_DBG5_8197F 0 #define BIT_MASK_FW_DBG5_8197F 0xffffffffL -#define BIT_FW_DBG5_8197F(x) (((x) & BIT_MASK_FW_DBG5_8197F) << BIT_SHIFT_FW_DBG5_8197F) +#define BIT_FW_DBG5_8197F(x) \ + (((x) & BIT_MASK_FW_DBG5_8197F) << BIT_SHIFT_FW_DBG5_8197F) #define BITS_FW_DBG5_8197F (BIT_MASK_FW_DBG5_8197F << BIT_SHIFT_FW_DBG5_8197F) #define BIT_CLEAR_FW_DBG5_8197F(x) ((x) & (~BITS_FW_DBG5_8197F)) -#define BIT_GET_FW_DBG5_8197F(x) (((x) >> BIT_SHIFT_FW_DBG5_8197F) & BIT_MASK_FW_DBG5_8197F) -#define BIT_SET_FW_DBG5_8197F(x, v) (BIT_CLEAR_FW_DBG5_8197F(x) | BIT_FW_DBG5_8197F(v)) - +#define BIT_GET_FW_DBG5_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG5_8197F) & BIT_MASK_FW_DBG5_8197F) +#define BIT_SET_FW_DBG5_8197F(x, v) \ + (BIT_CLEAR_FW_DBG5_8197F(x) | BIT_FW_DBG5_8197F(v)) /* 2 REG_FW_DBG6_8197F */ #define BIT_SHIFT_FW_DBG6_8197F 0 #define BIT_MASK_FW_DBG6_8197F 0xffffffffL -#define BIT_FW_DBG6_8197F(x) (((x) & BIT_MASK_FW_DBG6_8197F) << BIT_SHIFT_FW_DBG6_8197F) +#define BIT_FW_DBG6_8197F(x) \ + (((x) & BIT_MASK_FW_DBG6_8197F) << BIT_SHIFT_FW_DBG6_8197F) #define BITS_FW_DBG6_8197F (BIT_MASK_FW_DBG6_8197F << BIT_SHIFT_FW_DBG6_8197F) #define BIT_CLEAR_FW_DBG6_8197F(x) ((x) & (~BITS_FW_DBG6_8197F)) -#define BIT_GET_FW_DBG6_8197F(x) (((x) >> BIT_SHIFT_FW_DBG6_8197F) & BIT_MASK_FW_DBG6_8197F) -#define BIT_SET_FW_DBG6_8197F(x, v) (BIT_CLEAR_FW_DBG6_8197F(x) | BIT_FW_DBG6_8197F(v)) - +#define BIT_GET_FW_DBG6_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG6_8197F) & BIT_MASK_FW_DBG6_8197F) +#define BIT_SET_FW_DBG6_8197F(x, v) \ + (BIT_CLEAR_FW_DBG6_8197F(x) | BIT_FW_DBG6_8197F(v)) /* 2 REG_FW_DBG7_8197F */ #define BIT_SHIFT_FW_DBG7_8197F 0 #define BIT_MASK_FW_DBG7_8197F 0xffffffffL -#define BIT_FW_DBG7_8197F(x) (((x) & BIT_MASK_FW_DBG7_8197F) << BIT_SHIFT_FW_DBG7_8197F) +#define BIT_FW_DBG7_8197F(x) \ + (((x) & BIT_MASK_FW_DBG7_8197F) << BIT_SHIFT_FW_DBG7_8197F) #define BITS_FW_DBG7_8197F (BIT_MASK_FW_DBG7_8197F << BIT_SHIFT_FW_DBG7_8197F) #define BIT_CLEAR_FW_DBG7_8197F(x) ((x) & (~BITS_FW_DBG7_8197F)) -#define BIT_GET_FW_DBG7_8197F(x) (((x) >> BIT_SHIFT_FW_DBG7_8197F) & BIT_MASK_FW_DBG7_8197F) -#define BIT_SET_FW_DBG7_8197F(x, v) (BIT_CLEAR_FW_DBG7_8197F(x) | BIT_FW_DBG7_8197F(v)) - +#define BIT_GET_FW_DBG7_8197F(x) \ + (((x) >> BIT_SHIFT_FW_DBG7_8197F) & BIT_MASK_FW_DBG7_8197F) +#define BIT_SET_FW_DBG7_8197F(x, v) \ + (BIT_CLEAR_FW_DBG7_8197F(x) | BIT_FW_DBG7_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -2246,29 +2767,36 @@ #define BIT_SHIFT_LBMODE_8197F 24 #define BIT_MASK_LBMODE_8197F 0x1f -#define BIT_LBMODE_8197F(x) (((x) & BIT_MASK_LBMODE_8197F) << BIT_SHIFT_LBMODE_8197F) +#define BIT_LBMODE_8197F(x) \ + (((x) & BIT_MASK_LBMODE_8197F) << BIT_SHIFT_LBMODE_8197F) #define BITS_LBMODE_8197F (BIT_MASK_LBMODE_8197F << BIT_SHIFT_LBMODE_8197F) #define BIT_CLEAR_LBMODE_8197F(x) ((x) & (~BITS_LBMODE_8197F)) -#define BIT_GET_LBMODE_8197F(x) (((x) >> BIT_SHIFT_LBMODE_8197F) & BIT_MASK_LBMODE_8197F) -#define BIT_SET_LBMODE_8197F(x, v) (BIT_CLEAR_LBMODE_8197F(x) | BIT_LBMODE_8197F(v)) - +#define BIT_GET_LBMODE_8197F(x) \ + (((x) >> BIT_SHIFT_LBMODE_8197F) & BIT_MASK_LBMODE_8197F) +#define BIT_SET_LBMODE_8197F(x, v) \ + (BIT_CLEAR_LBMODE_8197F(x) | BIT_LBMODE_8197F(v)) #define BIT_SHIFT_NETYPE1_8197F 18 #define BIT_MASK_NETYPE1_8197F 0x3 -#define BIT_NETYPE1_8197F(x) (((x) & BIT_MASK_NETYPE1_8197F) << BIT_SHIFT_NETYPE1_8197F) +#define BIT_NETYPE1_8197F(x) \ + (((x) & BIT_MASK_NETYPE1_8197F) << BIT_SHIFT_NETYPE1_8197F) #define BITS_NETYPE1_8197F (BIT_MASK_NETYPE1_8197F << BIT_SHIFT_NETYPE1_8197F) #define BIT_CLEAR_NETYPE1_8197F(x) ((x) & (~BITS_NETYPE1_8197F)) -#define BIT_GET_NETYPE1_8197F(x) (((x) >> BIT_SHIFT_NETYPE1_8197F) & BIT_MASK_NETYPE1_8197F) -#define BIT_SET_NETYPE1_8197F(x, v) (BIT_CLEAR_NETYPE1_8197F(x) | BIT_NETYPE1_8197F(v)) - +#define BIT_GET_NETYPE1_8197F(x) \ + (((x) >> BIT_SHIFT_NETYPE1_8197F) & BIT_MASK_NETYPE1_8197F) +#define BIT_SET_NETYPE1_8197F(x, v) \ + (BIT_CLEAR_NETYPE1_8197F(x) | BIT_NETYPE1_8197F(v)) #define BIT_SHIFT_NETYPE0_8197F 16 #define BIT_MASK_NETYPE0_8197F 0x3 -#define BIT_NETYPE0_8197F(x) (((x) & BIT_MASK_NETYPE0_8197F) << BIT_SHIFT_NETYPE0_8197F) +#define BIT_NETYPE0_8197F(x) \ + (((x) & BIT_MASK_NETYPE0_8197F) << BIT_SHIFT_NETYPE0_8197F) #define BITS_NETYPE0_8197F (BIT_MASK_NETYPE0_8197F << BIT_SHIFT_NETYPE0_8197F) #define BIT_CLEAR_NETYPE0_8197F(x) ((x) & (~BITS_NETYPE0_8197F)) -#define BIT_GET_NETYPE0_8197F(x) (((x) >> BIT_SHIFT_NETYPE0_8197F) & BIT_MASK_NETYPE0_8197F) -#define BIT_SET_NETYPE0_8197F(x, v) (BIT_CLEAR_NETYPE0_8197F(x) | BIT_NETYPE0_8197F(v)) +#define BIT_GET_NETYPE0_8197F(x) \ + (((x) >> BIT_SHIFT_NETYPE0_8197F) & BIT_MASK_NETYPE0_8197F) +#define BIT_SET_NETYPE0_8197F(x, v) \ + (BIT_CLEAR_NETYPE0_8197F(x) | BIT_NETYPE0_8197F(v)) #define BIT_STAT_FUNC_RST_8197F BIT(13) #define BIT_I2C_MAILBOX_EN_8197F BIT(12) @@ -2292,57 +2820,75 @@ #define BIT_SHIFT_TXDMA_HIQ_MAP_8197F 14 #define BIT_MASK_TXDMA_HIQ_MAP_8197F 0x3 -#define BIT_TXDMA_HIQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8197F) << BIT_SHIFT_TXDMA_HIQ_MAP_8197F) -#define BITS_TXDMA_HIQ_MAP_8197F (BIT_MASK_TXDMA_HIQ_MAP_8197F << BIT_SHIFT_TXDMA_HIQ_MAP_8197F) +#define BIT_TXDMA_HIQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_8197F) << BIT_SHIFT_TXDMA_HIQ_MAP_8197F) +#define BITS_TXDMA_HIQ_MAP_8197F \ + (BIT_MASK_TXDMA_HIQ_MAP_8197F << BIT_SHIFT_TXDMA_HIQ_MAP_8197F) #define BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8197F)) -#define BIT_GET_TXDMA_HIQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8197F) & BIT_MASK_TXDMA_HIQ_MAP_8197F) -#define BIT_SET_TXDMA_HIQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) | BIT_TXDMA_HIQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_HIQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8197F) & BIT_MASK_TXDMA_HIQ_MAP_8197F) +#define BIT_SET_TXDMA_HIQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) | BIT_TXDMA_HIQ_MAP_8197F(v)) #define BIT_SHIFT_TXDMA_MGQ_MAP_8197F 12 #define BIT_MASK_TXDMA_MGQ_MAP_8197F 0x3 -#define BIT_TXDMA_MGQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8197F) << BIT_SHIFT_TXDMA_MGQ_MAP_8197F) -#define BITS_TXDMA_MGQ_MAP_8197F (BIT_MASK_TXDMA_MGQ_MAP_8197F << BIT_SHIFT_TXDMA_MGQ_MAP_8197F) +#define BIT_TXDMA_MGQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_8197F) << BIT_SHIFT_TXDMA_MGQ_MAP_8197F) +#define BITS_TXDMA_MGQ_MAP_8197F \ + (BIT_MASK_TXDMA_MGQ_MAP_8197F << BIT_SHIFT_TXDMA_MGQ_MAP_8197F) #define BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8197F)) -#define BIT_GET_TXDMA_MGQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8197F) & BIT_MASK_TXDMA_MGQ_MAP_8197F) -#define BIT_SET_TXDMA_MGQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) | BIT_TXDMA_MGQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_MGQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8197F) & BIT_MASK_TXDMA_MGQ_MAP_8197F) +#define BIT_SET_TXDMA_MGQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) | BIT_TXDMA_MGQ_MAP_8197F(v)) #define BIT_SHIFT_TXDMA_BKQ_MAP_8197F 10 #define BIT_MASK_TXDMA_BKQ_MAP_8197F 0x3 -#define BIT_TXDMA_BKQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8197F) << BIT_SHIFT_TXDMA_BKQ_MAP_8197F) -#define BITS_TXDMA_BKQ_MAP_8197F (BIT_MASK_TXDMA_BKQ_MAP_8197F << BIT_SHIFT_TXDMA_BKQ_MAP_8197F) +#define BIT_TXDMA_BKQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_8197F) << BIT_SHIFT_TXDMA_BKQ_MAP_8197F) +#define BITS_TXDMA_BKQ_MAP_8197F \ + (BIT_MASK_TXDMA_BKQ_MAP_8197F << BIT_SHIFT_TXDMA_BKQ_MAP_8197F) #define BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8197F)) -#define BIT_GET_TXDMA_BKQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8197F) & BIT_MASK_TXDMA_BKQ_MAP_8197F) -#define BIT_SET_TXDMA_BKQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) | BIT_TXDMA_BKQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_BKQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8197F) & BIT_MASK_TXDMA_BKQ_MAP_8197F) +#define BIT_SET_TXDMA_BKQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) | BIT_TXDMA_BKQ_MAP_8197F(v)) #define BIT_SHIFT_TXDMA_BEQ_MAP_8197F 8 #define BIT_MASK_TXDMA_BEQ_MAP_8197F 0x3 -#define BIT_TXDMA_BEQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8197F) << BIT_SHIFT_TXDMA_BEQ_MAP_8197F) -#define BITS_TXDMA_BEQ_MAP_8197F (BIT_MASK_TXDMA_BEQ_MAP_8197F << BIT_SHIFT_TXDMA_BEQ_MAP_8197F) +#define BIT_TXDMA_BEQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_8197F) << BIT_SHIFT_TXDMA_BEQ_MAP_8197F) +#define BITS_TXDMA_BEQ_MAP_8197F \ + (BIT_MASK_TXDMA_BEQ_MAP_8197F << BIT_SHIFT_TXDMA_BEQ_MAP_8197F) #define BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8197F)) -#define BIT_GET_TXDMA_BEQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8197F) & BIT_MASK_TXDMA_BEQ_MAP_8197F) -#define BIT_SET_TXDMA_BEQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) | BIT_TXDMA_BEQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_BEQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8197F) & BIT_MASK_TXDMA_BEQ_MAP_8197F) +#define BIT_SET_TXDMA_BEQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) | BIT_TXDMA_BEQ_MAP_8197F(v)) #define BIT_SHIFT_TXDMA_VIQ_MAP_8197F 6 #define BIT_MASK_TXDMA_VIQ_MAP_8197F 0x3 -#define BIT_TXDMA_VIQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8197F) << BIT_SHIFT_TXDMA_VIQ_MAP_8197F) -#define BITS_TXDMA_VIQ_MAP_8197F (BIT_MASK_TXDMA_VIQ_MAP_8197F << BIT_SHIFT_TXDMA_VIQ_MAP_8197F) +#define BIT_TXDMA_VIQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_8197F) << BIT_SHIFT_TXDMA_VIQ_MAP_8197F) +#define BITS_TXDMA_VIQ_MAP_8197F \ + (BIT_MASK_TXDMA_VIQ_MAP_8197F << BIT_SHIFT_TXDMA_VIQ_MAP_8197F) #define BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8197F)) -#define BIT_GET_TXDMA_VIQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8197F) & BIT_MASK_TXDMA_VIQ_MAP_8197F) -#define BIT_SET_TXDMA_VIQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) | BIT_TXDMA_VIQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_VIQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8197F) & BIT_MASK_TXDMA_VIQ_MAP_8197F) +#define BIT_SET_TXDMA_VIQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) | BIT_TXDMA_VIQ_MAP_8197F(v)) #define BIT_SHIFT_TXDMA_VOQ_MAP_8197F 4 #define BIT_MASK_TXDMA_VOQ_MAP_8197F 0x3 -#define BIT_TXDMA_VOQ_MAP_8197F(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8197F) << BIT_SHIFT_TXDMA_VOQ_MAP_8197F) -#define BITS_TXDMA_VOQ_MAP_8197F (BIT_MASK_TXDMA_VOQ_MAP_8197F << BIT_SHIFT_TXDMA_VOQ_MAP_8197F) +#define BIT_TXDMA_VOQ_MAP_8197F(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_8197F) << BIT_SHIFT_TXDMA_VOQ_MAP_8197F) +#define BITS_TXDMA_VOQ_MAP_8197F \ + (BIT_MASK_TXDMA_VOQ_MAP_8197F << BIT_SHIFT_TXDMA_VOQ_MAP_8197F) #define BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8197F)) -#define BIT_GET_TXDMA_VOQ_MAP_8197F(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8197F) & BIT_MASK_TXDMA_VOQ_MAP_8197F) -#define BIT_SET_TXDMA_VOQ_MAP_8197F(x, v) (BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) | BIT_TXDMA_VOQ_MAP_8197F(v)) - +#define BIT_GET_TXDMA_VOQ_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8197F) & BIT_MASK_TXDMA_VOQ_MAP_8197F) +#define BIT_SET_TXDMA_VOQ_MAP_8197F(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) | BIT_TXDMA_VOQ_MAP_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_RXDMA_AGG_EN_8197F BIT(2) @@ -2353,21 +2899,31 @@ #define BIT_SHIFT_RXFFOVFL_RSV_V2_8197F 8 #define BIT_MASK_RXFFOVFL_RSV_V2_8197F 0xf -#define BIT_RXFFOVFL_RSV_V2_8197F(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8197F) << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) -#define BITS_RXFFOVFL_RSV_V2_8197F (BIT_MASK_RXFFOVFL_RSV_V2_8197F << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) +#define BIT_RXFFOVFL_RSV_V2_8197F(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8197F) \ + << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) +#define BITS_RXFFOVFL_RSV_V2_8197F \ + (BIT_MASK_RXFFOVFL_RSV_V2_8197F << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) #define BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8197F)) -#define BIT_GET_RXFFOVFL_RSV_V2_8197F(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) & BIT_MASK_RXFFOVFL_RSV_V2_8197F) -#define BIT_SET_RXFFOVFL_RSV_V2_8197F(x, v) (BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) | BIT_RXFFOVFL_RSV_V2_8197F(v)) - +#define BIT_GET_RXFFOVFL_RSV_V2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) & \ + BIT_MASK_RXFFOVFL_RSV_V2_8197F) +#define BIT_SET_RXFFOVFL_RSV_V2_8197F(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) | BIT_RXFFOVFL_RSV_V2_8197F(v)) #define BIT_SHIFT_TXPKTBUF_PGBNDY_8197F 0 #define BIT_MASK_TXPKTBUF_PGBNDY_8197F 0xff -#define BIT_TXPKTBUF_PGBNDY_8197F(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8197F) << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) -#define BITS_TXPKTBUF_PGBNDY_8197F (BIT_MASK_TXPKTBUF_PGBNDY_8197F << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) +#define BIT_TXPKTBUF_PGBNDY_8197F(x) \ + (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8197F) \ + << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) +#define BITS_TXPKTBUF_PGBNDY_8197F \ + (BIT_MASK_TXPKTBUF_PGBNDY_8197F << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) #define BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) ((x) & (~BITS_TXPKTBUF_PGBNDY_8197F)) -#define BIT_GET_TXPKTBUF_PGBNDY_8197F(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) & BIT_MASK_TXPKTBUF_PGBNDY_8197F) -#define BIT_SET_TXPKTBUF_PGBNDY_8197F(x, v) (BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) | BIT_TXPKTBUF_PGBNDY_8197F(v)) - +#define BIT_GET_TXPKTBUF_PGBNDY_8197F(x) \ + (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) & \ + BIT_MASK_TXPKTBUF_PGBNDY_8197F) +#define BIT_SET_TXPKTBUF_PGBNDY_8197F(x, v) \ + (BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) | BIT_TXPKTBUF_PGBNDY_8197F(v)) /* 2 REG_PTA_I2C_MBOX_8197F */ @@ -2375,30 +2931,44 @@ #define BIT_SHIFT_I2C_M_STATUS_8197F 8 #define BIT_MASK_I2C_M_STATUS_8197F 0xf -#define BIT_I2C_M_STATUS_8197F(x) (((x) & BIT_MASK_I2C_M_STATUS_8197F) << BIT_SHIFT_I2C_M_STATUS_8197F) -#define BITS_I2C_M_STATUS_8197F (BIT_MASK_I2C_M_STATUS_8197F << BIT_SHIFT_I2C_M_STATUS_8197F) +#define BIT_I2C_M_STATUS_8197F(x) \ + (((x) & BIT_MASK_I2C_M_STATUS_8197F) << BIT_SHIFT_I2C_M_STATUS_8197F) +#define BITS_I2C_M_STATUS_8197F \ + (BIT_MASK_I2C_M_STATUS_8197F << BIT_SHIFT_I2C_M_STATUS_8197F) #define BIT_CLEAR_I2C_M_STATUS_8197F(x) ((x) & (~BITS_I2C_M_STATUS_8197F)) -#define BIT_GET_I2C_M_STATUS_8197F(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8197F) & BIT_MASK_I2C_M_STATUS_8197F) -#define BIT_SET_I2C_M_STATUS_8197F(x, v) (BIT_CLEAR_I2C_M_STATUS_8197F(x) | BIT_I2C_M_STATUS_8197F(v)) - +#define BIT_GET_I2C_M_STATUS_8197F(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS_8197F) & BIT_MASK_I2C_M_STATUS_8197F) +#define BIT_SET_I2C_M_STATUS_8197F(x, v) \ + (BIT_CLEAR_I2C_M_STATUS_8197F(x) | BIT_I2C_M_STATUS_8197F(v)) #define BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F 4 #define BIT_MASK_I2C_M_BUS_GNT_FW_8197F 0x7 -#define BIT_I2C_M_BUS_GNT_FW_8197F(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8197F) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) -#define BITS_I2C_M_BUS_GNT_FW_8197F (BIT_MASK_I2C_M_BUS_GNT_FW_8197F << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) -#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) ((x) & (~BITS_I2C_M_BUS_GNT_FW_8197F)) -#define BIT_GET_I2C_M_BUS_GNT_FW_8197F(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) & BIT_MASK_I2C_M_BUS_GNT_FW_8197F) -#define BIT_SET_I2C_M_BUS_GNT_FW_8197F(x, v) (BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) | BIT_I2C_M_BUS_GNT_FW_8197F(v)) +#define BIT_I2C_M_BUS_GNT_FW_8197F(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8197F) \ + << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) +#define BITS_I2C_M_BUS_GNT_FW_8197F \ + (BIT_MASK_I2C_M_BUS_GNT_FW_8197F << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) \ + ((x) & (~BITS_I2C_M_BUS_GNT_FW_8197F)) +#define BIT_GET_I2C_M_BUS_GNT_FW_8197F(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) & \ + BIT_MASK_I2C_M_BUS_GNT_FW_8197F) +#define BIT_SET_I2C_M_BUS_GNT_FW_8197F(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) | BIT_I2C_M_BUS_GNT_FW_8197F(v)) #define BIT_I2C_M_GNT_FW_8197F BIT(3) #define BIT_SHIFT_I2C_M_SPEED_8197F 1 #define BIT_MASK_I2C_M_SPEED_8197F 0x3 -#define BIT_I2C_M_SPEED_8197F(x) (((x) & BIT_MASK_I2C_M_SPEED_8197F) << BIT_SHIFT_I2C_M_SPEED_8197F) -#define BITS_I2C_M_SPEED_8197F (BIT_MASK_I2C_M_SPEED_8197F << BIT_SHIFT_I2C_M_SPEED_8197F) +#define BIT_I2C_M_SPEED_8197F(x) \ + (((x) & BIT_MASK_I2C_M_SPEED_8197F) << BIT_SHIFT_I2C_M_SPEED_8197F) +#define BITS_I2C_M_SPEED_8197F \ + (BIT_MASK_I2C_M_SPEED_8197F << BIT_SHIFT_I2C_M_SPEED_8197F) #define BIT_CLEAR_I2C_M_SPEED_8197F(x) ((x) & (~BITS_I2C_M_SPEED_8197F)) -#define BIT_GET_I2C_M_SPEED_8197F(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8197F) & BIT_MASK_I2C_M_SPEED_8197F) -#define BIT_SET_I2C_M_SPEED_8197F(x, v) (BIT_CLEAR_I2C_M_SPEED_8197F(x) | BIT_I2C_M_SPEED_8197F(v)) +#define BIT_GET_I2C_M_SPEED_8197F(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED_8197F) & BIT_MASK_I2C_M_SPEED_8197F) +#define BIT_SET_I2C_M_SPEED_8197F(x, v) \ + (BIT_CLEAR_I2C_M_SPEED_8197F(x) | BIT_I2C_M_SPEED_8197F(v)) #define BIT_I2C_M_UNLOCK_8197F BIT(0) @@ -2408,12 +2978,15 @@ #define BIT_SHIFT_RXFF0_BNDY_V2_8197F 0 #define BIT_MASK_RXFF0_BNDY_V2_8197F 0x3ffff -#define BIT_RXFF0_BNDY_V2_8197F(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8197F) << BIT_SHIFT_RXFF0_BNDY_V2_8197F) -#define BITS_RXFF0_BNDY_V2_8197F (BIT_MASK_RXFF0_BNDY_V2_8197F << BIT_SHIFT_RXFF0_BNDY_V2_8197F) +#define BIT_RXFF0_BNDY_V2_8197F(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2_8197F) << BIT_SHIFT_RXFF0_BNDY_V2_8197F) +#define BITS_RXFF0_BNDY_V2_8197F \ + (BIT_MASK_RXFF0_BNDY_V2_8197F << BIT_SHIFT_RXFF0_BNDY_V2_8197F) #define BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) ((x) & (~BITS_RXFF0_BNDY_V2_8197F)) -#define BIT_GET_RXFF0_BNDY_V2_8197F(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8197F) & BIT_MASK_RXFF0_BNDY_V2_8197F) -#define BIT_SET_RXFF0_BNDY_V2_8197F(x, v) (BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) | BIT_RXFF0_BNDY_V2_8197F(v)) - +#define BIT_GET_RXFF0_BNDY_V2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8197F) & BIT_MASK_RXFF0_BNDY_V2_8197F) +#define BIT_SET_RXFF0_BNDY_V2_8197F(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) | BIT_RXFF0_BNDY_V2_8197F(v)) /* 2 REG_FE1IMR_8197F */ #define BIT_BB_STOP_RX_INT_EN_8197F BIT(29) @@ -2482,12 +3055,15 @@ #define BIT_SHIFT_CPWM_MOD_8197F 24 #define BIT_MASK_CPWM_MOD_8197F 0x7f -#define BIT_CPWM_MOD_8197F(x) (((x) & BIT_MASK_CPWM_MOD_8197F) << BIT_SHIFT_CPWM_MOD_8197F) -#define BITS_CPWM_MOD_8197F (BIT_MASK_CPWM_MOD_8197F << BIT_SHIFT_CPWM_MOD_8197F) +#define BIT_CPWM_MOD_8197F(x) \ + (((x) & BIT_MASK_CPWM_MOD_8197F) << BIT_SHIFT_CPWM_MOD_8197F) +#define BITS_CPWM_MOD_8197F \ + (BIT_MASK_CPWM_MOD_8197F << BIT_SHIFT_CPWM_MOD_8197F) #define BIT_CLEAR_CPWM_MOD_8197F(x) ((x) & (~BITS_CPWM_MOD_8197F)) -#define BIT_GET_CPWM_MOD_8197F(x) (((x) >> BIT_SHIFT_CPWM_MOD_8197F) & BIT_MASK_CPWM_MOD_8197F) -#define BIT_SET_CPWM_MOD_8197F(x, v) (BIT_CLEAR_CPWM_MOD_8197F(x) | BIT_CPWM_MOD_8197F(v)) - +#define BIT_GET_CPWM_MOD_8197F(x) \ + (((x) >> BIT_SHIFT_CPWM_MOD_8197F) & BIT_MASK_CPWM_MOD_8197F) +#define BIT_SET_CPWM_MOD_8197F(x, v) \ + (BIT_CLEAR_CPWM_MOD_8197F(x) | BIT_CPWM_MOD_8197F(v)) /* 2 REG_FWIMR_8197F */ #define BIT_FS_TXBCNOK_MB7_INT_EN_8197F BIT(31) @@ -2509,7 +3085,8 @@ #define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN_8197F BIT(15) #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8197F BIT(13) #define BIT_FS_MGNTQFF_TO_INT_EN_8197F BIT(12) -#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN_8197F BIT(11) +#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN_8197F \ + BIT(11) #define BIT_FS_DDMA1_HP_INT_EN_8197F BIT(10) #define BIT_FS_DDMA0_LP_INT_EN_8197F BIT(9) #define BIT_FS_DDMA0_HP_INT_EN_8197F BIT(8) @@ -2603,11 +3180,17 @@ #define BIT_SHIFT_PKTBUF_WRITE_EN_8197F 24 #define BIT_MASK_PKTBUF_WRITE_EN_8197F 0xff -#define BIT_PKTBUF_WRITE_EN_8197F(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8197F) << BIT_SHIFT_PKTBUF_WRITE_EN_8197F) -#define BITS_PKTBUF_WRITE_EN_8197F (BIT_MASK_PKTBUF_WRITE_EN_8197F << BIT_SHIFT_PKTBUF_WRITE_EN_8197F) +#define BIT_PKTBUF_WRITE_EN_8197F(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN_8197F) \ + << BIT_SHIFT_PKTBUF_WRITE_EN_8197F) +#define BITS_PKTBUF_WRITE_EN_8197F \ + (BIT_MASK_PKTBUF_WRITE_EN_8197F << BIT_SHIFT_PKTBUF_WRITE_EN_8197F) #define BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8197F)) -#define BIT_GET_PKTBUF_WRITE_EN_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8197F) & BIT_MASK_PKTBUF_WRITE_EN_8197F) -#define BIT_SET_PKTBUF_WRITE_EN_8197F(x, v) (BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) | BIT_PKTBUF_WRITE_EN_8197F(v)) +#define BIT_GET_PKTBUF_WRITE_EN_8197F(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8197F) & \ + BIT_MASK_PKTBUF_WRITE_EN_8197F) +#define BIT_SET_PKTBUF_WRITE_EN_8197F(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) | BIT_PKTBUF_WRITE_EN_8197F(v)) #define BIT_TXRPTBUF_DBG_8197F BIT(23) @@ -2617,55 +3200,81 @@ #define BIT_SHIFT_PKTBUF_DBG_ADDR_8197F 0 #define BIT_MASK_PKTBUF_DBG_ADDR_8197F 0x1fff -#define BIT_PKTBUF_DBG_ADDR_8197F(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8197F) << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) -#define BITS_PKTBUF_DBG_ADDR_8197F (BIT_MASK_PKTBUF_DBG_ADDR_8197F << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) +#define BIT_PKTBUF_DBG_ADDR_8197F(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8197F) \ + << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) +#define BITS_PKTBUF_DBG_ADDR_8197F \ + (BIT_MASK_PKTBUF_DBG_ADDR_8197F << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) #define BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8197F)) -#define BIT_GET_PKTBUF_DBG_ADDR_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) & BIT_MASK_PKTBUF_DBG_ADDR_8197F) -#define BIT_SET_PKTBUF_DBG_ADDR_8197F(x, v) (BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) | BIT_PKTBUF_DBG_ADDR_8197F(v)) - +#define BIT_GET_PKTBUF_DBG_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) & \ + BIT_MASK_PKTBUF_DBG_ADDR_8197F) +#define BIT_SET_PKTBUF_DBG_ADDR_8197F(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) | BIT_PKTBUF_DBG_ADDR_8197F(v)) /* 2 REG_PKTBUF_DBG_DATA_L_8197F */ #define BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F 0 #define BIT_MASK_PKTBUF_DBG_DATA_L_8197F 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_L_8197F(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8197F) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) -#define BITS_PKTBUF_DBG_DATA_L_8197F (BIT_MASK_PKTBUF_DBG_DATA_L_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) -#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) ((x) & (~BITS_PKTBUF_DBG_DATA_L_8197F)) -#define BIT_GET_PKTBUF_DBG_DATA_L_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) & BIT_MASK_PKTBUF_DBG_DATA_L_8197F) -#define BIT_SET_PKTBUF_DBG_DATA_L_8197F(x, v) (BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) | BIT_PKTBUF_DBG_DATA_L_8197F(v)) - +#define BIT_PKTBUF_DBG_DATA_L_8197F(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8197F) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) +#define BITS_PKTBUF_DBG_DATA_L_8197F \ + (BIT_MASK_PKTBUF_DBG_DATA_L_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_L_8197F)) +#define BIT_GET_PKTBUF_DBG_DATA_L_8197F(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) & \ + BIT_MASK_PKTBUF_DBG_DATA_L_8197F) +#define BIT_SET_PKTBUF_DBG_DATA_L_8197F(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) | BIT_PKTBUF_DBG_DATA_L_8197F(v)) /* 2 REG_PKTBUF_DBG_DATA_H_8197F */ #define BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F 0 #define BIT_MASK_PKTBUF_DBG_DATA_H_8197F 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_H_8197F(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8197F) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) -#define BITS_PKTBUF_DBG_DATA_H_8197F (BIT_MASK_PKTBUF_DBG_DATA_H_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) -#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) ((x) & (~BITS_PKTBUF_DBG_DATA_H_8197F)) -#define BIT_GET_PKTBUF_DBG_DATA_H_8197F(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) & BIT_MASK_PKTBUF_DBG_DATA_H_8197F) -#define BIT_SET_PKTBUF_DBG_DATA_H_8197F(x, v) (BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) | BIT_PKTBUF_DBG_DATA_H_8197F(v)) - +#define BIT_PKTBUF_DBG_DATA_H_8197F(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8197F) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) +#define BITS_PKTBUF_DBG_DATA_H_8197F \ + (BIT_MASK_PKTBUF_DBG_DATA_H_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_H_8197F)) +#define BIT_GET_PKTBUF_DBG_DATA_H_8197F(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) & \ + BIT_MASK_PKTBUF_DBG_DATA_H_8197F) +#define BIT_SET_PKTBUF_DBG_DATA_H_8197F(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) | BIT_PKTBUF_DBG_DATA_H_8197F(v)) /* 2 REG_CPWM2_8197F */ #define BIT_SHIFT_L0S_TO_RCVY_NUM_8197F 16 #define BIT_MASK_L0S_TO_RCVY_NUM_8197F 0xff -#define BIT_L0S_TO_RCVY_NUM_8197F(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8197F) << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) -#define BITS_L0S_TO_RCVY_NUM_8197F (BIT_MASK_L0S_TO_RCVY_NUM_8197F << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) +#define BIT_L0S_TO_RCVY_NUM_8197F(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8197F) \ + << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) +#define BITS_L0S_TO_RCVY_NUM_8197F \ + (BIT_MASK_L0S_TO_RCVY_NUM_8197F << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) #define BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8197F)) -#define BIT_GET_L0S_TO_RCVY_NUM_8197F(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) & BIT_MASK_L0S_TO_RCVY_NUM_8197F) -#define BIT_SET_L0S_TO_RCVY_NUM_8197F(x, v) (BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) | BIT_L0S_TO_RCVY_NUM_8197F(v)) +#define BIT_GET_L0S_TO_RCVY_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) & \ + BIT_MASK_L0S_TO_RCVY_NUM_8197F) +#define BIT_SET_L0S_TO_RCVY_NUM_8197F(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) | BIT_L0S_TO_RCVY_NUM_8197F(v)) #define BIT_CPWM2_TOGGLING_8197F BIT(15) #define BIT_SHIFT_CPWM2_MOD_8197F 0 #define BIT_MASK_CPWM2_MOD_8197F 0x7fff -#define BIT_CPWM2_MOD_8197F(x) (((x) & BIT_MASK_CPWM2_MOD_8197F) << BIT_SHIFT_CPWM2_MOD_8197F) -#define BITS_CPWM2_MOD_8197F (BIT_MASK_CPWM2_MOD_8197F << BIT_SHIFT_CPWM2_MOD_8197F) +#define BIT_CPWM2_MOD_8197F(x) \ + (((x) & BIT_MASK_CPWM2_MOD_8197F) << BIT_SHIFT_CPWM2_MOD_8197F) +#define BITS_CPWM2_MOD_8197F \ + (BIT_MASK_CPWM2_MOD_8197F << BIT_SHIFT_CPWM2_MOD_8197F) #define BIT_CLEAR_CPWM2_MOD_8197F(x) ((x) & (~BITS_CPWM2_MOD_8197F)) -#define BIT_GET_CPWM2_MOD_8197F(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8197F) & BIT_MASK_CPWM2_MOD_8197F) -#define BIT_SET_CPWM2_MOD_8197F(x, v) (BIT_CLEAR_CPWM2_MOD_8197F(x) | BIT_CPWM2_MOD_8197F(v)) - +#define BIT_GET_CPWM2_MOD_8197F(x) \ + (((x) >> BIT_SHIFT_CPWM2_MOD_8197F) & BIT_MASK_CPWM2_MOD_8197F) +#define BIT_SET_CPWM2_MOD_8197F(x, v) \ + (BIT_CLEAR_CPWM2_MOD_8197F(x) | BIT_CPWM2_MOD_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -2676,12 +3285,14 @@ #define BIT_SHIFT_TC0DATA_8197F 0 #define BIT_MASK_TC0DATA_8197F 0xffffff -#define BIT_TC0DATA_8197F(x) (((x) & BIT_MASK_TC0DATA_8197F) << BIT_SHIFT_TC0DATA_8197F) +#define BIT_TC0DATA_8197F(x) \ + (((x) & BIT_MASK_TC0DATA_8197F) << BIT_SHIFT_TC0DATA_8197F) #define BITS_TC0DATA_8197F (BIT_MASK_TC0DATA_8197F << BIT_SHIFT_TC0DATA_8197F) #define BIT_CLEAR_TC0DATA_8197F(x) ((x) & (~BITS_TC0DATA_8197F)) -#define BIT_GET_TC0DATA_8197F(x) (((x) >> BIT_SHIFT_TC0DATA_8197F) & BIT_MASK_TC0DATA_8197F) -#define BIT_SET_TC0DATA_8197F(x, v) (BIT_CLEAR_TC0DATA_8197F(x) | BIT_TC0DATA_8197F(v)) - +#define BIT_GET_TC0DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC0DATA_8197F) & BIT_MASK_TC0DATA_8197F) +#define BIT_SET_TC0DATA_8197F(x, v) \ + (BIT_CLEAR_TC0DATA_8197F(x) | BIT_TC0DATA_8197F(v)) /* 2 REG_TC1_CTRL_8197F */ #define BIT_TC1INT_EN_8197F BIT(26) @@ -2690,12 +3301,14 @@ #define BIT_SHIFT_TC1DATA_8197F 0 #define BIT_MASK_TC1DATA_8197F 0xffffff -#define BIT_TC1DATA_8197F(x) (((x) & BIT_MASK_TC1DATA_8197F) << BIT_SHIFT_TC1DATA_8197F) +#define BIT_TC1DATA_8197F(x) \ + (((x) & BIT_MASK_TC1DATA_8197F) << BIT_SHIFT_TC1DATA_8197F) #define BITS_TC1DATA_8197F (BIT_MASK_TC1DATA_8197F << BIT_SHIFT_TC1DATA_8197F) #define BIT_CLEAR_TC1DATA_8197F(x) ((x) & (~BITS_TC1DATA_8197F)) -#define BIT_GET_TC1DATA_8197F(x) (((x) >> BIT_SHIFT_TC1DATA_8197F) & BIT_MASK_TC1DATA_8197F) -#define BIT_SET_TC1DATA_8197F(x, v) (BIT_CLEAR_TC1DATA_8197F(x) | BIT_TC1DATA_8197F(v)) - +#define BIT_GET_TC1DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC1DATA_8197F) & BIT_MASK_TC1DATA_8197F) +#define BIT_SET_TC1DATA_8197F(x, v) \ + (BIT_CLEAR_TC1DATA_8197F(x) | BIT_TC1DATA_8197F(v)) /* 2 REG_TC2_CTRL_8197F */ #define BIT_TC2INT_EN_8197F BIT(26) @@ -2704,12 +3317,14 @@ #define BIT_SHIFT_TC2DATA_8197F 0 #define BIT_MASK_TC2DATA_8197F 0xffffff -#define BIT_TC2DATA_8197F(x) (((x) & BIT_MASK_TC2DATA_8197F) << BIT_SHIFT_TC2DATA_8197F) +#define BIT_TC2DATA_8197F(x) \ + (((x) & BIT_MASK_TC2DATA_8197F) << BIT_SHIFT_TC2DATA_8197F) #define BITS_TC2DATA_8197F (BIT_MASK_TC2DATA_8197F << BIT_SHIFT_TC2DATA_8197F) #define BIT_CLEAR_TC2DATA_8197F(x) ((x) & (~BITS_TC2DATA_8197F)) -#define BIT_GET_TC2DATA_8197F(x) (((x) >> BIT_SHIFT_TC2DATA_8197F) & BIT_MASK_TC2DATA_8197F) -#define BIT_SET_TC2DATA_8197F(x, v) (BIT_CLEAR_TC2DATA_8197F(x) | BIT_TC2DATA_8197F(v)) - +#define BIT_GET_TC2DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC2DATA_8197F) & BIT_MASK_TC2DATA_8197F) +#define BIT_SET_TC2DATA_8197F(x, v) \ + (BIT_CLEAR_TC2DATA_8197F(x) | BIT_TC2DATA_8197F(v)) /* 2 REG_TC3_CTRL_8197F */ #define BIT_TC3INT_EN_8197F BIT(26) @@ -2718,12 +3333,14 @@ #define BIT_SHIFT_TC3DATA_8197F 0 #define BIT_MASK_TC3DATA_8197F 0xffffff -#define BIT_TC3DATA_8197F(x) (((x) & BIT_MASK_TC3DATA_8197F) << BIT_SHIFT_TC3DATA_8197F) +#define BIT_TC3DATA_8197F(x) \ + (((x) & BIT_MASK_TC3DATA_8197F) << BIT_SHIFT_TC3DATA_8197F) #define BITS_TC3DATA_8197F (BIT_MASK_TC3DATA_8197F << BIT_SHIFT_TC3DATA_8197F) #define BIT_CLEAR_TC3DATA_8197F(x) ((x) & (~BITS_TC3DATA_8197F)) -#define BIT_GET_TC3DATA_8197F(x) (((x) >> BIT_SHIFT_TC3DATA_8197F) & BIT_MASK_TC3DATA_8197F) -#define BIT_SET_TC3DATA_8197F(x, v) (BIT_CLEAR_TC3DATA_8197F(x) | BIT_TC3DATA_8197F(v)) - +#define BIT_GET_TC3DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC3DATA_8197F) & BIT_MASK_TC3DATA_8197F) +#define BIT_SET_TC3DATA_8197F(x, v) \ + (BIT_CLEAR_TC3DATA_8197F(x) | BIT_TC3DATA_8197F(v)) /* 2 REG_TC4_CTRL_8197F */ #define BIT_TC4INT_EN_8197F BIT(26) @@ -2732,23 +3349,28 @@ #define BIT_SHIFT_TC4DATA_8197F 0 #define BIT_MASK_TC4DATA_8197F 0xffffff -#define BIT_TC4DATA_8197F(x) (((x) & BIT_MASK_TC4DATA_8197F) << BIT_SHIFT_TC4DATA_8197F) +#define BIT_TC4DATA_8197F(x) \ + (((x) & BIT_MASK_TC4DATA_8197F) << BIT_SHIFT_TC4DATA_8197F) #define BITS_TC4DATA_8197F (BIT_MASK_TC4DATA_8197F << BIT_SHIFT_TC4DATA_8197F) #define BIT_CLEAR_TC4DATA_8197F(x) ((x) & (~BITS_TC4DATA_8197F)) -#define BIT_GET_TC4DATA_8197F(x) (((x) >> BIT_SHIFT_TC4DATA_8197F) & BIT_MASK_TC4DATA_8197F) -#define BIT_SET_TC4DATA_8197F(x, v) (BIT_CLEAR_TC4DATA_8197F(x) | BIT_TC4DATA_8197F(v)) - +#define BIT_GET_TC4DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC4DATA_8197F) & BIT_MASK_TC4DATA_8197F) +#define BIT_SET_TC4DATA_8197F(x, v) \ + (BIT_CLEAR_TC4DATA_8197F(x) | BIT_TC4DATA_8197F(v)) /* 2 REG_TCUNIT_BASE_8197F */ #define BIT_SHIFT_TCUNIT_BASE_8197F 0 #define BIT_MASK_TCUNIT_BASE_8197F 0x3fff -#define BIT_TCUNIT_BASE_8197F(x) (((x) & BIT_MASK_TCUNIT_BASE_8197F) << BIT_SHIFT_TCUNIT_BASE_8197F) -#define BITS_TCUNIT_BASE_8197F (BIT_MASK_TCUNIT_BASE_8197F << BIT_SHIFT_TCUNIT_BASE_8197F) +#define BIT_TCUNIT_BASE_8197F(x) \ + (((x) & BIT_MASK_TCUNIT_BASE_8197F) << BIT_SHIFT_TCUNIT_BASE_8197F) +#define BITS_TCUNIT_BASE_8197F \ + (BIT_MASK_TCUNIT_BASE_8197F << BIT_SHIFT_TCUNIT_BASE_8197F) #define BIT_CLEAR_TCUNIT_BASE_8197F(x) ((x) & (~BITS_TCUNIT_BASE_8197F)) -#define BIT_GET_TCUNIT_BASE_8197F(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8197F) & BIT_MASK_TCUNIT_BASE_8197F) -#define BIT_SET_TCUNIT_BASE_8197F(x, v) (BIT_CLEAR_TCUNIT_BASE_8197F(x) | BIT_TCUNIT_BASE_8197F(v)) - +#define BIT_GET_TCUNIT_BASE_8197F(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE_8197F) & BIT_MASK_TCUNIT_BASE_8197F) +#define BIT_SET_TCUNIT_BASE_8197F(x, v) \ + (BIT_CLEAR_TCUNIT_BASE_8197F(x) | BIT_TCUNIT_BASE_8197F(v)) /* 2 REG_TC5_CTRL_8197F */ #define BIT_TC5INT_EN_8197F BIT(26) @@ -2757,12 +3379,14 @@ #define BIT_SHIFT_TC5DATA_8197F 0 #define BIT_MASK_TC5DATA_8197F 0xffffff -#define BIT_TC5DATA_8197F(x) (((x) & BIT_MASK_TC5DATA_8197F) << BIT_SHIFT_TC5DATA_8197F) +#define BIT_TC5DATA_8197F(x) \ + (((x) & BIT_MASK_TC5DATA_8197F) << BIT_SHIFT_TC5DATA_8197F) #define BITS_TC5DATA_8197F (BIT_MASK_TC5DATA_8197F << BIT_SHIFT_TC5DATA_8197F) #define BIT_CLEAR_TC5DATA_8197F(x) ((x) & (~BITS_TC5DATA_8197F)) -#define BIT_GET_TC5DATA_8197F(x) (((x) >> BIT_SHIFT_TC5DATA_8197F) & BIT_MASK_TC5DATA_8197F) -#define BIT_SET_TC5DATA_8197F(x, v) (BIT_CLEAR_TC5DATA_8197F(x) | BIT_TC5DATA_8197F(v)) - +#define BIT_GET_TC5DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC5DATA_8197F) & BIT_MASK_TC5DATA_8197F) +#define BIT_SET_TC5DATA_8197F(x, v) \ + (BIT_CLEAR_TC5DATA_8197F(x) | BIT_TC5DATA_8197F(v)) /* 2 REG_TC6_CTRL_8197F */ #define BIT_TC6INT_EN_8197F BIT(26) @@ -2771,159 +3395,251 @@ #define BIT_SHIFT_TC6DATA_8197F 0 #define BIT_MASK_TC6DATA_8197F 0xffffff -#define BIT_TC6DATA_8197F(x) (((x) & BIT_MASK_TC6DATA_8197F) << BIT_SHIFT_TC6DATA_8197F) +#define BIT_TC6DATA_8197F(x) \ + (((x) & BIT_MASK_TC6DATA_8197F) << BIT_SHIFT_TC6DATA_8197F) #define BITS_TC6DATA_8197F (BIT_MASK_TC6DATA_8197F << BIT_SHIFT_TC6DATA_8197F) #define BIT_CLEAR_TC6DATA_8197F(x) ((x) & (~BITS_TC6DATA_8197F)) -#define BIT_GET_TC6DATA_8197F(x) (((x) >> BIT_SHIFT_TC6DATA_8197F) & BIT_MASK_TC6DATA_8197F) -#define BIT_SET_TC6DATA_8197F(x, v) (BIT_CLEAR_TC6DATA_8197F(x) | BIT_TC6DATA_8197F(v)) - +#define BIT_GET_TC6DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC6DATA_8197F) & BIT_MASK_TC6DATA_8197F) +#define BIT_SET_TC6DATA_8197F(x, v) \ + (BIT_CLEAR_TC6DATA_8197F(x) | BIT_TC6DATA_8197F(v)) /* 2 REG_MBIST_FAIL_8197F */ #define BIT_SHIFT_8051_MBIST_FAIL_8197F 26 #define BIT_MASK_8051_MBIST_FAIL_8197F 0x7 -#define BIT_8051_MBIST_FAIL_8197F(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8197F) << BIT_SHIFT_8051_MBIST_FAIL_8197F) -#define BITS_8051_MBIST_FAIL_8197F (BIT_MASK_8051_MBIST_FAIL_8197F << BIT_SHIFT_8051_MBIST_FAIL_8197F) +#define BIT_8051_MBIST_FAIL_8197F(x) \ + (((x) & BIT_MASK_8051_MBIST_FAIL_8197F) \ + << BIT_SHIFT_8051_MBIST_FAIL_8197F) +#define BITS_8051_MBIST_FAIL_8197F \ + (BIT_MASK_8051_MBIST_FAIL_8197F << BIT_SHIFT_8051_MBIST_FAIL_8197F) #define BIT_CLEAR_8051_MBIST_FAIL_8197F(x) ((x) & (~BITS_8051_MBIST_FAIL_8197F)) -#define BIT_GET_8051_MBIST_FAIL_8197F(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8197F) & BIT_MASK_8051_MBIST_FAIL_8197F) -#define BIT_SET_8051_MBIST_FAIL_8197F(x, v) (BIT_CLEAR_8051_MBIST_FAIL_8197F(x) | BIT_8051_MBIST_FAIL_8197F(v)) - +#define BIT_GET_8051_MBIST_FAIL_8197F(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8197F) & \ + BIT_MASK_8051_MBIST_FAIL_8197F) +#define BIT_SET_8051_MBIST_FAIL_8197F(x, v) \ + (BIT_CLEAR_8051_MBIST_FAIL_8197F(x) | BIT_8051_MBIST_FAIL_8197F(v)) #define BIT_SHIFT_USB_MBIST_FAIL_8197F 24 #define BIT_MASK_USB_MBIST_FAIL_8197F 0x3 -#define BIT_USB_MBIST_FAIL_8197F(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8197F) << BIT_SHIFT_USB_MBIST_FAIL_8197F) -#define BITS_USB_MBIST_FAIL_8197F (BIT_MASK_USB_MBIST_FAIL_8197F << BIT_SHIFT_USB_MBIST_FAIL_8197F) +#define BIT_USB_MBIST_FAIL_8197F(x) \ + (((x) & BIT_MASK_USB_MBIST_FAIL_8197F) \ + << BIT_SHIFT_USB_MBIST_FAIL_8197F) +#define BITS_USB_MBIST_FAIL_8197F \ + (BIT_MASK_USB_MBIST_FAIL_8197F << BIT_SHIFT_USB_MBIST_FAIL_8197F) #define BIT_CLEAR_USB_MBIST_FAIL_8197F(x) ((x) & (~BITS_USB_MBIST_FAIL_8197F)) -#define BIT_GET_USB_MBIST_FAIL_8197F(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8197F) & BIT_MASK_USB_MBIST_FAIL_8197F) -#define BIT_SET_USB_MBIST_FAIL_8197F(x, v) (BIT_CLEAR_USB_MBIST_FAIL_8197F(x) | BIT_USB_MBIST_FAIL_8197F(v)) - +#define BIT_GET_USB_MBIST_FAIL_8197F(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8197F) & \ + BIT_MASK_USB_MBIST_FAIL_8197F) +#define BIT_SET_USB_MBIST_FAIL_8197F(x, v) \ + (BIT_CLEAR_USB_MBIST_FAIL_8197F(x) | BIT_USB_MBIST_FAIL_8197F(v)) #define BIT_SHIFT_PCIE_MBIST_FAIL_8197F 16 #define BIT_MASK_PCIE_MBIST_FAIL_8197F 0x3f -#define BIT_PCIE_MBIST_FAIL_8197F(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8197F) << BIT_SHIFT_PCIE_MBIST_FAIL_8197F) -#define BITS_PCIE_MBIST_FAIL_8197F (BIT_MASK_PCIE_MBIST_FAIL_8197F << BIT_SHIFT_PCIE_MBIST_FAIL_8197F) +#define BIT_PCIE_MBIST_FAIL_8197F(x) \ + (((x) & BIT_MASK_PCIE_MBIST_FAIL_8197F) \ + << BIT_SHIFT_PCIE_MBIST_FAIL_8197F) +#define BITS_PCIE_MBIST_FAIL_8197F \ + (BIT_MASK_PCIE_MBIST_FAIL_8197F << BIT_SHIFT_PCIE_MBIST_FAIL_8197F) #define BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) ((x) & (~BITS_PCIE_MBIST_FAIL_8197F)) -#define BIT_GET_PCIE_MBIST_FAIL_8197F(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8197F) & BIT_MASK_PCIE_MBIST_FAIL_8197F) -#define BIT_SET_PCIE_MBIST_FAIL_8197F(x, v) (BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) | BIT_PCIE_MBIST_FAIL_8197F(v)) - +#define BIT_GET_PCIE_MBIST_FAIL_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8197F) & \ + BIT_MASK_PCIE_MBIST_FAIL_8197F) +#define BIT_SET_PCIE_MBIST_FAIL_8197F(x, v) \ + (BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) | BIT_PCIE_MBIST_FAIL_8197F(v)) #define BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F 0 #define BIT_MASK_MAC_MBIST_FAIL_DRF_8197F 0x3ffff -#define BIT_MAC_MBIST_FAIL_DRF_8197F(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF_8197F) << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) -#define BITS_MAC_MBIST_FAIL_DRF_8197F (BIT_MASK_MAC_MBIST_FAIL_DRF_8197F << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) -#define BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) ((x) & (~BITS_MAC_MBIST_FAIL_DRF_8197F)) -#define BIT_GET_MAC_MBIST_FAIL_DRF_8197F(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) & BIT_MASK_MAC_MBIST_FAIL_DRF_8197F) -#define BIT_SET_MAC_MBIST_FAIL_DRF_8197F(x, v) (BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) | BIT_MAC_MBIST_FAIL_DRF_8197F(v)) - +#define BIT_MAC_MBIST_FAIL_DRF_8197F(x) \ + (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF_8197F) \ + << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) +#define BITS_MAC_MBIST_FAIL_DRF_8197F \ + (BIT_MASK_MAC_MBIST_FAIL_DRF_8197F \ + << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) +#define BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) \ + ((x) & (~BITS_MAC_MBIST_FAIL_DRF_8197F)) +#define BIT_GET_MAC_MBIST_FAIL_DRF_8197F(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) & \ + BIT_MASK_MAC_MBIST_FAIL_DRF_8197F) +#define BIT_SET_MAC_MBIST_FAIL_DRF_8197F(x, v) \ + (BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) | \ + BIT_MAC_MBIST_FAIL_DRF_8197F(v)) /* 2 REG_MBIST_START_PAUSE_8197F */ #define BIT_SHIFT_8051_MBIST_START_PAUSE_8197F 26 #define BIT_MASK_8051_MBIST_START_PAUSE_8197F 0x7 -#define BIT_8051_MBIST_START_PAUSE_8197F(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8197F) << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) -#define BITS_8051_MBIST_START_PAUSE_8197F (BIT_MASK_8051_MBIST_START_PAUSE_8197F << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) -#define BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) ((x) & (~BITS_8051_MBIST_START_PAUSE_8197F)) -#define BIT_GET_8051_MBIST_START_PAUSE_8197F(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) & BIT_MASK_8051_MBIST_START_PAUSE_8197F) -#define BIT_SET_8051_MBIST_START_PAUSE_8197F(x, v) (BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) | BIT_8051_MBIST_START_PAUSE_8197F(v)) - +#define BIT_8051_MBIST_START_PAUSE_8197F(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8197F) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) +#define BITS_8051_MBIST_START_PAUSE_8197F \ + (BIT_MASK_8051_MBIST_START_PAUSE_8197F \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) +#define BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE_8197F)) +#define BIT_GET_8051_MBIST_START_PAUSE_8197F(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) & \ + BIT_MASK_8051_MBIST_START_PAUSE_8197F) +#define BIT_SET_8051_MBIST_START_PAUSE_8197F(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) | \ + BIT_8051_MBIST_START_PAUSE_8197F(v)) #define BIT_SHIFT_USB_MBIST_START_PAUSE_8197F 24 #define BIT_MASK_USB_MBIST_START_PAUSE_8197F 0x3 -#define BIT_USB_MBIST_START_PAUSE_8197F(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8197F) << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) -#define BITS_USB_MBIST_START_PAUSE_8197F (BIT_MASK_USB_MBIST_START_PAUSE_8197F << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) -#define BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) ((x) & (~BITS_USB_MBIST_START_PAUSE_8197F)) -#define BIT_GET_USB_MBIST_START_PAUSE_8197F(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) & BIT_MASK_USB_MBIST_START_PAUSE_8197F) -#define BIT_SET_USB_MBIST_START_PAUSE_8197F(x, v) (BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) | BIT_USB_MBIST_START_PAUSE_8197F(v)) - +#define BIT_USB_MBIST_START_PAUSE_8197F(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8197F) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) +#define BITS_USB_MBIST_START_PAUSE_8197F \ + (BIT_MASK_USB_MBIST_START_PAUSE_8197F \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) \ + ((x) & (~BITS_USB_MBIST_START_PAUSE_8197F)) +#define BIT_GET_USB_MBIST_START_PAUSE_8197F(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) & \ + BIT_MASK_USB_MBIST_START_PAUSE_8197F) +#define BIT_SET_USB_MBIST_START_PAUSE_8197F(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) | \ + BIT_USB_MBIST_START_PAUSE_8197F(v)) #define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F 16 #define BIT_MASK_PCIE_MBIST_START_PAUSE_8197F 0x3f -#define BIT_PCIE_MBIST_START_PAUSE_8197F(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8197F) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) -#define BITS_PCIE_MBIST_START_PAUSE_8197F (BIT_MASK_PCIE_MBIST_START_PAUSE_8197F << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) -#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) ((x) & (~BITS_PCIE_MBIST_START_PAUSE_8197F)) -#define BIT_GET_PCIE_MBIST_START_PAUSE_8197F(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) & BIT_MASK_PCIE_MBIST_START_PAUSE_8197F) -#define BIT_SET_PCIE_MBIST_START_PAUSE_8197F(x, v) (BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) | BIT_PCIE_MBIST_START_PAUSE_8197F(v)) - +#define BIT_PCIE_MBIST_START_PAUSE_8197F(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8197F) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) +#define BITS_PCIE_MBIST_START_PAUSE_8197F \ + (BIT_MASK_PCIE_MBIST_START_PAUSE_8197F \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE_8197F)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE_8197F) +#define BIT_SET_PCIE_MBIST_START_PAUSE_8197F(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) | \ + BIT_PCIE_MBIST_START_PAUSE_8197F(v)) #define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F 0 #define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F 0x3ffff -#define BIT_MAC_MBIST_START_PAUSE_V1_8197F(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F) << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) -#define BITS_MAC_MBIST_START_PAUSE_V1_8197F (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) -#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8197F)) -#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8197F(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F) -#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8197F(x, v) (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) | BIT_MAC_MBIST_START_PAUSE_V1_8197F(v)) - +#define BIT_MAC_MBIST_START_PAUSE_V1_8197F(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) +#define BITS_MAC_MBIST_START_PAUSE_V1_8197F \ + (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) \ + ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8197F)) +#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) & \ + BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F) +#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8197F(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) | \ + BIT_MAC_MBIST_START_PAUSE_V1_8197F(v)) /* 2 REG_MBIST_DONE_8197F */ #define BIT_SHIFT_8051_MBIST_DONE_8197F 26 #define BIT_MASK_8051_MBIST_DONE_8197F 0x7 -#define BIT_8051_MBIST_DONE_8197F(x) (((x) & BIT_MASK_8051_MBIST_DONE_8197F) << BIT_SHIFT_8051_MBIST_DONE_8197F) -#define BITS_8051_MBIST_DONE_8197F (BIT_MASK_8051_MBIST_DONE_8197F << BIT_SHIFT_8051_MBIST_DONE_8197F) +#define BIT_8051_MBIST_DONE_8197F(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE_8197F) \ + << BIT_SHIFT_8051_MBIST_DONE_8197F) +#define BITS_8051_MBIST_DONE_8197F \ + (BIT_MASK_8051_MBIST_DONE_8197F << BIT_SHIFT_8051_MBIST_DONE_8197F) #define BIT_CLEAR_8051_MBIST_DONE_8197F(x) ((x) & (~BITS_8051_MBIST_DONE_8197F)) -#define BIT_GET_8051_MBIST_DONE_8197F(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8197F) & BIT_MASK_8051_MBIST_DONE_8197F) -#define BIT_SET_8051_MBIST_DONE_8197F(x, v) (BIT_CLEAR_8051_MBIST_DONE_8197F(x) | BIT_8051_MBIST_DONE_8197F(v)) - +#define BIT_GET_8051_MBIST_DONE_8197F(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE_8197F) & \ + BIT_MASK_8051_MBIST_DONE_8197F) +#define BIT_SET_8051_MBIST_DONE_8197F(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE_8197F(x) | BIT_8051_MBIST_DONE_8197F(v)) #define BIT_SHIFT_USB_MBIST_DONE_8197F 24 #define BIT_MASK_USB_MBIST_DONE_8197F 0x3 -#define BIT_USB_MBIST_DONE_8197F(x) (((x) & BIT_MASK_USB_MBIST_DONE_8197F) << BIT_SHIFT_USB_MBIST_DONE_8197F) -#define BITS_USB_MBIST_DONE_8197F (BIT_MASK_USB_MBIST_DONE_8197F << BIT_SHIFT_USB_MBIST_DONE_8197F) +#define BIT_USB_MBIST_DONE_8197F(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE_8197F) \ + << BIT_SHIFT_USB_MBIST_DONE_8197F) +#define BITS_USB_MBIST_DONE_8197F \ + (BIT_MASK_USB_MBIST_DONE_8197F << BIT_SHIFT_USB_MBIST_DONE_8197F) #define BIT_CLEAR_USB_MBIST_DONE_8197F(x) ((x) & (~BITS_USB_MBIST_DONE_8197F)) -#define BIT_GET_USB_MBIST_DONE_8197F(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8197F) & BIT_MASK_USB_MBIST_DONE_8197F) -#define BIT_SET_USB_MBIST_DONE_8197F(x, v) (BIT_CLEAR_USB_MBIST_DONE_8197F(x) | BIT_USB_MBIST_DONE_8197F(v)) - +#define BIT_GET_USB_MBIST_DONE_8197F(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE_8197F) & \ + BIT_MASK_USB_MBIST_DONE_8197F) +#define BIT_SET_USB_MBIST_DONE_8197F(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE_8197F(x) | BIT_USB_MBIST_DONE_8197F(v)) #define BIT_SHIFT_PCIE_MBIST_DONE_8197F 16 #define BIT_MASK_PCIE_MBIST_DONE_8197F 0x3f -#define BIT_PCIE_MBIST_DONE_8197F(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8197F) << BIT_SHIFT_PCIE_MBIST_DONE_8197F) -#define BITS_PCIE_MBIST_DONE_8197F (BIT_MASK_PCIE_MBIST_DONE_8197F << BIT_SHIFT_PCIE_MBIST_DONE_8197F) +#define BIT_PCIE_MBIST_DONE_8197F(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE_8197F) \ + << BIT_SHIFT_PCIE_MBIST_DONE_8197F) +#define BITS_PCIE_MBIST_DONE_8197F \ + (BIT_MASK_PCIE_MBIST_DONE_8197F << BIT_SHIFT_PCIE_MBIST_DONE_8197F) #define BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) ((x) & (~BITS_PCIE_MBIST_DONE_8197F)) -#define BIT_GET_PCIE_MBIST_DONE_8197F(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8197F) & BIT_MASK_PCIE_MBIST_DONE_8197F) -#define BIT_SET_PCIE_MBIST_DONE_8197F(x, v) (BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) | BIT_PCIE_MBIST_DONE_8197F(v)) - +#define BIT_GET_PCIE_MBIST_DONE_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8197F) & \ + BIT_MASK_PCIE_MBIST_DONE_8197F) +#define BIT_SET_PCIE_MBIST_DONE_8197F(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) | BIT_PCIE_MBIST_DONE_8197F(v)) #define BIT_SHIFT_MAC_MBIST_DONE_V1_8197F 0 #define BIT_MASK_MAC_MBIST_DONE_V1_8197F 0x3ffff -#define BIT_MAC_MBIST_DONE_V1_8197F(x) (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8197F) << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) -#define BITS_MAC_MBIST_DONE_V1_8197F (BIT_MASK_MAC_MBIST_DONE_V1_8197F << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) -#define BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) ((x) & (~BITS_MAC_MBIST_DONE_V1_8197F)) -#define BIT_GET_MAC_MBIST_DONE_V1_8197F(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) & BIT_MASK_MAC_MBIST_DONE_V1_8197F) -#define BIT_SET_MAC_MBIST_DONE_V1_8197F(x, v) (BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) | BIT_MAC_MBIST_DONE_V1_8197F(v)) - +#define BIT_MAC_MBIST_DONE_V1_8197F(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8197F) \ + << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) +#define BITS_MAC_MBIST_DONE_V1_8197F \ + (BIT_MASK_MAC_MBIST_DONE_V1_8197F << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) +#define BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) \ + ((x) & (~BITS_MAC_MBIST_DONE_V1_8197F)) +#define BIT_GET_MAC_MBIST_DONE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) & \ + BIT_MASK_MAC_MBIST_DONE_V1_8197F) +#define BIT_SET_MAC_MBIST_DONE_V1_8197F(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) | BIT_MAC_MBIST_DONE_V1_8197F(v)) /* 2 REG_MBIST_FAIL_NRML_8197F */ #define BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F 0 #define BIT_MASK_MBIST_FAIL_NRML_V1_8197F 0x3ffff -#define BIT_MBIST_FAIL_NRML_V1_8197F(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_V1_8197F) << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) -#define BITS_MBIST_FAIL_NRML_V1_8197F (BIT_MASK_MBIST_FAIL_NRML_V1_8197F << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) -#define BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) ((x) & (~BITS_MBIST_FAIL_NRML_V1_8197F)) -#define BIT_GET_MBIST_FAIL_NRML_V1_8197F(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) & BIT_MASK_MBIST_FAIL_NRML_V1_8197F) -#define BIT_SET_MBIST_FAIL_NRML_V1_8197F(x, v) (BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) | BIT_MBIST_FAIL_NRML_V1_8197F(v)) - +#define BIT_MBIST_FAIL_NRML_V1_8197F(x) \ + (((x) & BIT_MASK_MBIST_FAIL_NRML_V1_8197F) \ + << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) +#define BITS_MBIST_FAIL_NRML_V1_8197F \ + (BIT_MASK_MBIST_FAIL_NRML_V1_8197F \ + << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) +#define BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) \ + ((x) & (~BITS_MBIST_FAIL_NRML_V1_8197F)) +#define BIT_GET_MBIST_FAIL_NRML_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) & \ + BIT_MASK_MBIST_FAIL_NRML_V1_8197F) +#define BIT_SET_MBIST_FAIL_NRML_V1_8197F(x, v) \ + (BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) | \ + BIT_MBIST_FAIL_NRML_V1_8197F(v)) /* 2 REG_AES_DECRPT_DATA_8197F */ #define BIT_SHIFT_IPS_CFG_ADDR_8197F 0 #define BIT_MASK_IPS_CFG_ADDR_8197F 0xff -#define BIT_IPS_CFG_ADDR_8197F(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8197F) << BIT_SHIFT_IPS_CFG_ADDR_8197F) -#define BITS_IPS_CFG_ADDR_8197F (BIT_MASK_IPS_CFG_ADDR_8197F << BIT_SHIFT_IPS_CFG_ADDR_8197F) +#define BIT_IPS_CFG_ADDR_8197F(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR_8197F) << BIT_SHIFT_IPS_CFG_ADDR_8197F) +#define BITS_IPS_CFG_ADDR_8197F \ + (BIT_MASK_IPS_CFG_ADDR_8197F << BIT_SHIFT_IPS_CFG_ADDR_8197F) #define BIT_CLEAR_IPS_CFG_ADDR_8197F(x) ((x) & (~BITS_IPS_CFG_ADDR_8197F)) -#define BIT_GET_IPS_CFG_ADDR_8197F(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8197F) & BIT_MASK_IPS_CFG_ADDR_8197F) -#define BIT_SET_IPS_CFG_ADDR_8197F(x, v) (BIT_CLEAR_IPS_CFG_ADDR_8197F(x) | BIT_IPS_CFG_ADDR_8197F(v)) - +#define BIT_GET_IPS_CFG_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8197F) & BIT_MASK_IPS_CFG_ADDR_8197F) +#define BIT_SET_IPS_CFG_ADDR_8197F(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR_8197F(x) | BIT_IPS_CFG_ADDR_8197F(v)) /* 2 REG_AES_DECRPT_CFG_8197F */ #define BIT_SHIFT_IPS_CFG_DATA_8197F 0 #define BIT_MASK_IPS_CFG_DATA_8197F 0xffffffffL -#define BIT_IPS_CFG_DATA_8197F(x) (((x) & BIT_MASK_IPS_CFG_DATA_8197F) << BIT_SHIFT_IPS_CFG_DATA_8197F) -#define BITS_IPS_CFG_DATA_8197F (BIT_MASK_IPS_CFG_DATA_8197F << BIT_SHIFT_IPS_CFG_DATA_8197F) +#define BIT_IPS_CFG_DATA_8197F(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA_8197F) << BIT_SHIFT_IPS_CFG_DATA_8197F) +#define BITS_IPS_CFG_DATA_8197F \ + (BIT_MASK_IPS_CFG_DATA_8197F << BIT_SHIFT_IPS_CFG_DATA_8197F) #define BIT_CLEAR_IPS_CFG_DATA_8197F(x) ((x) & (~BITS_IPS_CFG_DATA_8197F)) -#define BIT_GET_IPS_CFG_DATA_8197F(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8197F) & BIT_MASK_IPS_CFG_DATA_8197F) -#define BIT_SET_IPS_CFG_DATA_8197F(x, v) (BIT_CLEAR_IPS_CFG_DATA_8197F(x) | BIT_IPS_CFG_DATA_8197F(v)) - +#define BIT_GET_IPS_CFG_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA_8197F) & BIT_MASK_IPS_CFG_DATA_8197F) +#define BIT_SET_IPS_CFG_DATA_8197F(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA_8197F(x) | BIT_IPS_CFG_DATA_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -2931,56 +3647,90 @@ #define BIT_SHIFT_MACCLK_FREQ_LOW32_8197F 0 #define BIT_MASK_MACCLK_FREQ_LOW32_8197F 0xffffffffL -#define BIT_MACCLK_FREQ_LOW32_8197F(x) (((x) & BIT_MASK_MACCLK_FREQ_LOW32_8197F) << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) -#define BITS_MACCLK_FREQ_LOW32_8197F (BIT_MASK_MACCLK_FREQ_LOW32_8197F << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) -#define BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) ((x) & (~BITS_MACCLK_FREQ_LOW32_8197F)) -#define BIT_GET_MACCLK_FREQ_LOW32_8197F(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) & BIT_MASK_MACCLK_FREQ_LOW32_8197F) -#define BIT_SET_MACCLK_FREQ_LOW32_8197F(x, v) (BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) | BIT_MACCLK_FREQ_LOW32_8197F(v)) - +#define BIT_MACCLK_FREQ_LOW32_8197F(x) \ + (((x) & BIT_MASK_MACCLK_FREQ_LOW32_8197F) \ + << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) +#define BITS_MACCLK_FREQ_LOW32_8197F \ + (BIT_MASK_MACCLK_FREQ_LOW32_8197F << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) +#define BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) \ + ((x) & (~BITS_MACCLK_FREQ_LOW32_8197F)) +#define BIT_GET_MACCLK_FREQ_LOW32_8197F(x) \ + (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) & \ + BIT_MASK_MACCLK_FREQ_LOW32_8197F) +#define BIT_SET_MACCLK_FREQ_LOW32_8197F(x, v) \ + (BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) | BIT_MACCLK_FREQ_LOW32_8197F(v)) /* 2 REG_TMETER_8197F */ #define BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F 0 #define BIT_MASK_MACCLK_FREQ_HIGH10_8197F 0x3ff -#define BIT_MACCLK_FREQ_HIGH10_8197F(x) (((x) & BIT_MASK_MACCLK_FREQ_HIGH10_8197F) << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) -#define BITS_MACCLK_FREQ_HIGH10_8197F (BIT_MASK_MACCLK_FREQ_HIGH10_8197F << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) -#define BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) ((x) & (~BITS_MACCLK_FREQ_HIGH10_8197F)) -#define BIT_GET_MACCLK_FREQ_HIGH10_8197F(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) & BIT_MASK_MACCLK_FREQ_HIGH10_8197F) -#define BIT_SET_MACCLK_FREQ_HIGH10_8197F(x, v) (BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) | BIT_MACCLK_FREQ_HIGH10_8197F(v)) - +#define BIT_MACCLK_FREQ_HIGH10_8197F(x) \ + (((x) & BIT_MASK_MACCLK_FREQ_HIGH10_8197F) \ + << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) +#define BITS_MACCLK_FREQ_HIGH10_8197F \ + (BIT_MASK_MACCLK_FREQ_HIGH10_8197F \ + << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) +#define BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) \ + ((x) & (~BITS_MACCLK_FREQ_HIGH10_8197F)) +#define BIT_GET_MACCLK_FREQ_HIGH10_8197F(x) \ + (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) & \ + BIT_MASK_MACCLK_FREQ_HIGH10_8197F) +#define BIT_SET_MACCLK_FREQ_HIGH10_8197F(x, v) \ + (BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) | \ + BIT_MACCLK_FREQ_HIGH10_8197F(v)) /* 2 REG_OSC_32K_CTRL_8197F */ #define BIT_32K_CLK_OUT_RDY_8197F BIT(12) #define BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F 8 #define BIT_MASK_MONITOR_CYCLE_LOG2_8197F 0xf -#define BIT_MONITOR_CYCLE_LOG2_8197F(x) (((x) & BIT_MASK_MONITOR_CYCLE_LOG2_8197F) << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) -#define BITS_MONITOR_CYCLE_LOG2_8197F (BIT_MASK_MONITOR_CYCLE_LOG2_8197F << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) -#define BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) ((x) & (~BITS_MONITOR_CYCLE_LOG2_8197F)) -#define BIT_GET_MONITOR_CYCLE_LOG2_8197F(x) (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) & BIT_MASK_MONITOR_CYCLE_LOG2_8197F) -#define BIT_SET_MONITOR_CYCLE_LOG2_8197F(x, v) (BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) | BIT_MONITOR_CYCLE_LOG2_8197F(v)) - +#define BIT_MONITOR_CYCLE_LOG2_8197F(x) \ + (((x) & BIT_MASK_MONITOR_CYCLE_LOG2_8197F) \ + << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) +#define BITS_MONITOR_CYCLE_LOG2_8197F \ + (BIT_MASK_MONITOR_CYCLE_LOG2_8197F \ + << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) +#define BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) \ + ((x) & (~BITS_MONITOR_CYCLE_LOG2_8197F)) +#define BIT_GET_MONITOR_CYCLE_LOG2_8197F(x) \ + (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) & \ + BIT_MASK_MONITOR_CYCLE_LOG2_8197F) +#define BIT_SET_MONITOR_CYCLE_LOG2_8197F(x, v) \ + (BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) | \ + BIT_MONITOR_CYCLE_LOG2_8197F(v)) /* 2 REG_32K_CAL_REG1_8197F */ #define BIT_SHIFT_FREQVALUE_UNREGCLK_8197F 8 #define BIT_MASK_FREQVALUE_UNREGCLK_8197F 0xffffff -#define BIT_FREQVALUE_UNREGCLK_8197F(x) (((x) & BIT_MASK_FREQVALUE_UNREGCLK_8197F) << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) -#define BITS_FREQVALUE_UNREGCLK_8197F (BIT_MASK_FREQVALUE_UNREGCLK_8197F << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) -#define BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) ((x) & (~BITS_FREQVALUE_UNREGCLK_8197F)) -#define BIT_GET_FREQVALUE_UNREGCLK_8197F(x) (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) & BIT_MASK_FREQVALUE_UNREGCLK_8197F) -#define BIT_SET_FREQVALUE_UNREGCLK_8197F(x, v) (BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) | BIT_FREQVALUE_UNREGCLK_8197F(v)) +#define BIT_FREQVALUE_UNREGCLK_8197F(x) \ + (((x) & BIT_MASK_FREQVALUE_UNREGCLK_8197F) \ + << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) +#define BITS_FREQVALUE_UNREGCLK_8197F \ + (BIT_MASK_FREQVALUE_UNREGCLK_8197F \ + << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) +#define BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) \ + ((x) & (~BITS_FREQVALUE_UNREGCLK_8197F)) +#define BIT_GET_FREQVALUE_UNREGCLK_8197F(x) \ + (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) & \ + BIT_MASK_FREQVALUE_UNREGCLK_8197F) +#define BIT_SET_FREQVALUE_UNREGCLK_8197F(x, v) \ + (BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) | \ + BIT_FREQVALUE_UNREGCLK_8197F(v)) #define BIT_CAL32K_DBGMOD_8197F BIT(7) #define BIT_SHIFT_NCO_THRS_8197F 0 #define BIT_MASK_NCO_THRS_8197F 0x7f -#define BIT_NCO_THRS_8197F(x) (((x) & BIT_MASK_NCO_THRS_8197F) << BIT_SHIFT_NCO_THRS_8197F) -#define BITS_NCO_THRS_8197F (BIT_MASK_NCO_THRS_8197F << BIT_SHIFT_NCO_THRS_8197F) +#define BIT_NCO_THRS_8197F(x) \ + (((x) & BIT_MASK_NCO_THRS_8197F) << BIT_SHIFT_NCO_THRS_8197F) +#define BITS_NCO_THRS_8197F \ + (BIT_MASK_NCO_THRS_8197F << BIT_SHIFT_NCO_THRS_8197F) #define BIT_CLEAR_NCO_THRS_8197F(x) ((x) & (~BITS_NCO_THRS_8197F)) -#define BIT_GET_NCO_THRS_8197F(x) (((x) >> BIT_SHIFT_NCO_THRS_8197F) & BIT_MASK_NCO_THRS_8197F) -#define BIT_SET_NCO_THRS_8197F(x, v) (BIT_CLEAR_NCO_THRS_8197F(x) | BIT_NCO_THRS_8197F(v)) - +#define BIT_GET_NCO_THRS_8197F(x) \ + (((x) >> BIT_SHIFT_NCO_THRS_8197F) & BIT_MASK_NCO_THRS_8197F) +#define BIT_SET_NCO_THRS_8197F(x, v) \ + (BIT_CLEAR_NCO_THRS_8197F(x) | BIT_NCO_THRS_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -2988,67 +3738,88 @@ #define BIT_SHIFT_C2HEVT_MSG_8197F 0 #define BIT_MASK_C2HEVT_MSG_8197F 0xffffffffffffffffffffffffffffffffL -#define BIT_C2HEVT_MSG_8197F(x) (((x) & BIT_MASK_C2HEVT_MSG_8197F) << BIT_SHIFT_C2HEVT_MSG_8197F) -#define BITS_C2HEVT_MSG_8197F (BIT_MASK_C2HEVT_MSG_8197F << BIT_SHIFT_C2HEVT_MSG_8197F) +#define BIT_C2HEVT_MSG_8197F(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_8197F) << BIT_SHIFT_C2HEVT_MSG_8197F) +#define BITS_C2HEVT_MSG_8197F \ + (BIT_MASK_C2HEVT_MSG_8197F << BIT_SHIFT_C2HEVT_MSG_8197F) #define BIT_CLEAR_C2HEVT_MSG_8197F(x) ((x) & (~BITS_C2HEVT_MSG_8197F)) -#define BIT_GET_C2HEVT_MSG_8197F(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_8197F) & BIT_MASK_C2HEVT_MSG_8197F) -#define BIT_SET_C2HEVT_MSG_8197F(x, v) (BIT_CLEAR_C2HEVT_MSG_8197F(x) | BIT_C2HEVT_MSG_8197F(v)) - +#define BIT_GET_C2HEVT_MSG_8197F(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_8197F) & BIT_MASK_C2HEVT_MSG_8197F) +#define BIT_SET_C2HEVT_MSG_8197F(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_8197F(x) | BIT_C2HEVT_MSG_8197F(v)) /* 2 REG_SW_DEFINED_PAGE1_8197F */ #define BIT_SHIFT_SW_DEFINED_PAGE1_8197F 0 #define BIT_MASK_SW_DEFINED_PAGE1_8197F 0xffffffffffffffffL -#define BIT_SW_DEFINED_PAGE1_8197F(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_8197F) << BIT_SHIFT_SW_DEFINED_PAGE1_8197F) -#define BITS_SW_DEFINED_PAGE1_8197F (BIT_MASK_SW_DEFINED_PAGE1_8197F << BIT_SHIFT_SW_DEFINED_PAGE1_8197F) -#define BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) ((x) & (~BITS_SW_DEFINED_PAGE1_8197F)) -#define BIT_GET_SW_DEFINED_PAGE1_8197F(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8197F) & BIT_MASK_SW_DEFINED_PAGE1_8197F) -#define BIT_SET_SW_DEFINED_PAGE1_8197F(x, v) (BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) | BIT_SW_DEFINED_PAGE1_8197F(v)) - +#define BIT_SW_DEFINED_PAGE1_8197F(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_8197F) \ + << BIT_SHIFT_SW_DEFINED_PAGE1_8197F) +#define BITS_SW_DEFINED_PAGE1_8197F \ + (BIT_MASK_SW_DEFINED_PAGE1_8197F << BIT_SHIFT_SW_DEFINED_PAGE1_8197F) +#define BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE1_8197F)) +#define BIT_GET_SW_DEFINED_PAGE1_8197F(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8197F) & \ + BIT_MASK_SW_DEFINED_PAGE1_8197F) +#define BIT_SET_SW_DEFINED_PAGE1_8197F(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) | BIT_SW_DEFINED_PAGE1_8197F(v)) /* 2 REG_MCUTST_I_8197F */ #define BIT_SHIFT_MCUDMSG_I_8197F 0 #define BIT_MASK_MCUDMSG_I_8197F 0xffffffffL -#define BIT_MCUDMSG_I_8197F(x) (((x) & BIT_MASK_MCUDMSG_I_8197F) << BIT_SHIFT_MCUDMSG_I_8197F) -#define BITS_MCUDMSG_I_8197F (BIT_MASK_MCUDMSG_I_8197F << BIT_SHIFT_MCUDMSG_I_8197F) +#define BIT_MCUDMSG_I_8197F(x) \ + (((x) & BIT_MASK_MCUDMSG_I_8197F) << BIT_SHIFT_MCUDMSG_I_8197F) +#define BITS_MCUDMSG_I_8197F \ + (BIT_MASK_MCUDMSG_I_8197F << BIT_SHIFT_MCUDMSG_I_8197F) #define BIT_CLEAR_MCUDMSG_I_8197F(x) ((x) & (~BITS_MCUDMSG_I_8197F)) -#define BIT_GET_MCUDMSG_I_8197F(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8197F) & BIT_MASK_MCUDMSG_I_8197F) -#define BIT_SET_MCUDMSG_I_8197F(x, v) (BIT_CLEAR_MCUDMSG_I_8197F(x) | BIT_MCUDMSG_I_8197F(v)) - +#define BIT_GET_MCUDMSG_I_8197F(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_I_8197F) & BIT_MASK_MCUDMSG_I_8197F) +#define BIT_SET_MCUDMSG_I_8197F(x, v) \ + (BIT_CLEAR_MCUDMSG_I_8197F(x) | BIT_MCUDMSG_I_8197F(v)) /* 2 REG_MCUTST_II_8197F */ #define BIT_SHIFT_MCUDMSG_II_8197F 0 #define BIT_MASK_MCUDMSG_II_8197F 0xffffffffL -#define BIT_MCUDMSG_II_8197F(x) (((x) & BIT_MASK_MCUDMSG_II_8197F) << BIT_SHIFT_MCUDMSG_II_8197F) -#define BITS_MCUDMSG_II_8197F (BIT_MASK_MCUDMSG_II_8197F << BIT_SHIFT_MCUDMSG_II_8197F) +#define BIT_MCUDMSG_II_8197F(x) \ + (((x) & BIT_MASK_MCUDMSG_II_8197F) << BIT_SHIFT_MCUDMSG_II_8197F) +#define BITS_MCUDMSG_II_8197F \ + (BIT_MASK_MCUDMSG_II_8197F << BIT_SHIFT_MCUDMSG_II_8197F) #define BIT_CLEAR_MCUDMSG_II_8197F(x) ((x) & (~BITS_MCUDMSG_II_8197F)) -#define BIT_GET_MCUDMSG_II_8197F(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8197F) & BIT_MASK_MCUDMSG_II_8197F) -#define BIT_SET_MCUDMSG_II_8197F(x, v) (BIT_CLEAR_MCUDMSG_II_8197F(x) | BIT_MCUDMSG_II_8197F(v)) - +#define BIT_GET_MCUDMSG_II_8197F(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II_8197F) & BIT_MASK_MCUDMSG_II_8197F) +#define BIT_SET_MCUDMSG_II_8197F(x, v) \ + (BIT_CLEAR_MCUDMSG_II_8197F(x) | BIT_MCUDMSG_II_8197F(v)) /* 2 REG_FMETHR_8197F */ #define BIT_FMSG_INT_8197F BIT(31) #define BIT_SHIFT_FW_MSG_8197F 0 #define BIT_MASK_FW_MSG_8197F 0xffffffffL -#define BIT_FW_MSG_8197F(x) (((x) & BIT_MASK_FW_MSG_8197F) << BIT_SHIFT_FW_MSG_8197F) +#define BIT_FW_MSG_8197F(x) \ + (((x) & BIT_MASK_FW_MSG_8197F) << BIT_SHIFT_FW_MSG_8197F) #define BITS_FW_MSG_8197F (BIT_MASK_FW_MSG_8197F << BIT_SHIFT_FW_MSG_8197F) #define BIT_CLEAR_FW_MSG_8197F(x) ((x) & (~BITS_FW_MSG_8197F)) -#define BIT_GET_FW_MSG_8197F(x) (((x) >> BIT_SHIFT_FW_MSG_8197F) & BIT_MASK_FW_MSG_8197F) -#define BIT_SET_FW_MSG_8197F(x, v) (BIT_CLEAR_FW_MSG_8197F(x) | BIT_FW_MSG_8197F(v)) - +#define BIT_GET_FW_MSG_8197F(x) \ + (((x) >> BIT_SHIFT_FW_MSG_8197F) & BIT_MASK_FW_MSG_8197F) +#define BIT_SET_FW_MSG_8197F(x, v) \ + (BIT_CLEAR_FW_MSG_8197F(x) | BIT_FW_MSG_8197F(v)) /* 2 REG_HMETFR_8197F */ #define BIT_SHIFT_HRCV_MSG_8197F 24 #define BIT_MASK_HRCV_MSG_8197F 0xff -#define BIT_HRCV_MSG_8197F(x) (((x) & BIT_MASK_HRCV_MSG_8197F) << BIT_SHIFT_HRCV_MSG_8197F) -#define BITS_HRCV_MSG_8197F (BIT_MASK_HRCV_MSG_8197F << BIT_SHIFT_HRCV_MSG_8197F) +#define BIT_HRCV_MSG_8197F(x) \ + (((x) & BIT_MASK_HRCV_MSG_8197F) << BIT_SHIFT_HRCV_MSG_8197F) +#define BITS_HRCV_MSG_8197F \ + (BIT_MASK_HRCV_MSG_8197F << BIT_SHIFT_HRCV_MSG_8197F) #define BIT_CLEAR_HRCV_MSG_8197F(x) ((x) & (~BITS_HRCV_MSG_8197F)) -#define BIT_GET_HRCV_MSG_8197F(x) (((x) >> BIT_SHIFT_HRCV_MSG_8197F) & BIT_MASK_HRCV_MSG_8197F) -#define BIT_SET_HRCV_MSG_8197F(x, v) (BIT_CLEAR_HRCV_MSG_8197F(x) | BIT_HRCV_MSG_8197F(v)) +#define BIT_GET_HRCV_MSG_8197F(x) \ + (((x) >> BIT_SHIFT_HRCV_MSG_8197F) & BIT_MASK_HRCV_MSG_8197F) +#define BIT_SET_HRCV_MSG_8197F(x, v) \ + (BIT_CLEAR_HRCV_MSG_8197F(x) | BIT_HRCV_MSG_8197F(v)) #define BIT_INT_BOX3_8197F BIT(3) #define BIT_INT_BOX2_8197F BIT(2) @@ -3059,113 +3830,155 @@ #define BIT_SHIFT_HOST_MSG_0_8197F 0 #define BIT_MASK_HOST_MSG_0_8197F 0xffffffffL -#define BIT_HOST_MSG_0_8197F(x) (((x) & BIT_MASK_HOST_MSG_0_8197F) << BIT_SHIFT_HOST_MSG_0_8197F) -#define BITS_HOST_MSG_0_8197F (BIT_MASK_HOST_MSG_0_8197F << BIT_SHIFT_HOST_MSG_0_8197F) +#define BIT_HOST_MSG_0_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_0_8197F) << BIT_SHIFT_HOST_MSG_0_8197F) +#define BITS_HOST_MSG_0_8197F \ + (BIT_MASK_HOST_MSG_0_8197F << BIT_SHIFT_HOST_MSG_0_8197F) #define BIT_CLEAR_HOST_MSG_0_8197F(x) ((x) & (~BITS_HOST_MSG_0_8197F)) -#define BIT_GET_HOST_MSG_0_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8197F) & BIT_MASK_HOST_MSG_0_8197F) -#define BIT_SET_HOST_MSG_0_8197F(x, v) (BIT_CLEAR_HOST_MSG_0_8197F(x) | BIT_HOST_MSG_0_8197F(v)) - +#define BIT_GET_HOST_MSG_0_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0_8197F) & BIT_MASK_HOST_MSG_0_8197F) +#define BIT_SET_HOST_MSG_0_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_0_8197F(x) | BIT_HOST_MSG_0_8197F(v)) /* 2 REG_HMEBOX1_8197F */ #define BIT_SHIFT_HOST_MSG_1_8197F 0 #define BIT_MASK_HOST_MSG_1_8197F 0xffffffffL -#define BIT_HOST_MSG_1_8197F(x) (((x) & BIT_MASK_HOST_MSG_1_8197F) << BIT_SHIFT_HOST_MSG_1_8197F) -#define BITS_HOST_MSG_1_8197F (BIT_MASK_HOST_MSG_1_8197F << BIT_SHIFT_HOST_MSG_1_8197F) +#define BIT_HOST_MSG_1_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_1_8197F) << BIT_SHIFT_HOST_MSG_1_8197F) +#define BITS_HOST_MSG_1_8197F \ + (BIT_MASK_HOST_MSG_1_8197F << BIT_SHIFT_HOST_MSG_1_8197F) #define BIT_CLEAR_HOST_MSG_1_8197F(x) ((x) & (~BITS_HOST_MSG_1_8197F)) -#define BIT_GET_HOST_MSG_1_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8197F) & BIT_MASK_HOST_MSG_1_8197F) -#define BIT_SET_HOST_MSG_1_8197F(x, v) (BIT_CLEAR_HOST_MSG_1_8197F(x) | BIT_HOST_MSG_1_8197F(v)) - +#define BIT_GET_HOST_MSG_1_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1_8197F) & BIT_MASK_HOST_MSG_1_8197F) +#define BIT_SET_HOST_MSG_1_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_1_8197F(x) | BIT_HOST_MSG_1_8197F(v)) /* 2 REG_HMEBOX2_8197F */ #define BIT_SHIFT_HOST_MSG_2_8197F 0 #define BIT_MASK_HOST_MSG_2_8197F 0xffffffffL -#define BIT_HOST_MSG_2_8197F(x) (((x) & BIT_MASK_HOST_MSG_2_8197F) << BIT_SHIFT_HOST_MSG_2_8197F) -#define BITS_HOST_MSG_2_8197F (BIT_MASK_HOST_MSG_2_8197F << BIT_SHIFT_HOST_MSG_2_8197F) +#define BIT_HOST_MSG_2_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_2_8197F) << BIT_SHIFT_HOST_MSG_2_8197F) +#define BITS_HOST_MSG_2_8197F \ + (BIT_MASK_HOST_MSG_2_8197F << BIT_SHIFT_HOST_MSG_2_8197F) #define BIT_CLEAR_HOST_MSG_2_8197F(x) ((x) & (~BITS_HOST_MSG_2_8197F)) -#define BIT_GET_HOST_MSG_2_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8197F) & BIT_MASK_HOST_MSG_2_8197F) -#define BIT_SET_HOST_MSG_2_8197F(x, v) (BIT_CLEAR_HOST_MSG_2_8197F(x) | BIT_HOST_MSG_2_8197F(v)) - +#define BIT_GET_HOST_MSG_2_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2_8197F) & BIT_MASK_HOST_MSG_2_8197F) +#define BIT_SET_HOST_MSG_2_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_2_8197F(x) | BIT_HOST_MSG_2_8197F(v)) /* 2 REG_HMEBOX3_8197F */ #define BIT_SHIFT_HOST_MSG_3_8197F 0 #define BIT_MASK_HOST_MSG_3_8197F 0xffffffffL -#define BIT_HOST_MSG_3_8197F(x) (((x) & BIT_MASK_HOST_MSG_3_8197F) << BIT_SHIFT_HOST_MSG_3_8197F) -#define BITS_HOST_MSG_3_8197F (BIT_MASK_HOST_MSG_3_8197F << BIT_SHIFT_HOST_MSG_3_8197F) +#define BIT_HOST_MSG_3_8197F(x) \ + (((x) & BIT_MASK_HOST_MSG_3_8197F) << BIT_SHIFT_HOST_MSG_3_8197F) +#define BITS_HOST_MSG_3_8197F \ + (BIT_MASK_HOST_MSG_3_8197F << BIT_SHIFT_HOST_MSG_3_8197F) #define BIT_CLEAR_HOST_MSG_3_8197F(x) ((x) & (~BITS_HOST_MSG_3_8197F)) -#define BIT_GET_HOST_MSG_3_8197F(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8197F) & BIT_MASK_HOST_MSG_3_8197F) -#define BIT_SET_HOST_MSG_3_8197F(x, v) (BIT_CLEAR_HOST_MSG_3_8197F(x) | BIT_HOST_MSG_3_8197F(v)) - +#define BIT_GET_HOST_MSG_3_8197F(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3_8197F) & BIT_MASK_HOST_MSG_3_8197F) +#define BIT_SET_HOST_MSG_3_8197F(x, v) \ + (BIT_CLEAR_HOST_MSG_3_8197F(x) | BIT_HOST_MSG_3_8197F(v)) /* 2 REG_LLT_INIT_8197F */ #define BIT_SHIFT_LLTE_RWM_8197F 30 #define BIT_MASK_LLTE_RWM_8197F 0x3 -#define BIT_LLTE_RWM_8197F(x) (((x) & BIT_MASK_LLTE_RWM_8197F) << BIT_SHIFT_LLTE_RWM_8197F) -#define BITS_LLTE_RWM_8197F (BIT_MASK_LLTE_RWM_8197F << BIT_SHIFT_LLTE_RWM_8197F) +#define BIT_LLTE_RWM_8197F(x) \ + (((x) & BIT_MASK_LLTE_RWM_8197F) << BIT_SHIFT_LLTE_RWM_8197F) +#define BITS_LLTE_RWM_8197F \ + (BIT_MASK_LLTE_RWM_8197F << BIT_SHIFT_LLTE_RWM_8197F) #define BIT_CLEAR_LLTE_RWM_8197F(x) ((x) & (~BITS_LLTE_RWM_8197F)) -#define BIT_GET_LLTE_RWM_8197F(x) (((x) >> BIT_SHIFT_LLTE_RWM_8197F) & BIT_MASK_LLTE_RWM_8197F) -#define BIT_SET_LLTE_RWM_8197F(x, v) (BIT_CLEAR_LLTE_RWM_8197F(x) | BIT_LLTE_RWM_8197F(v)) - +#define BIT_GET_LLTE_RWM_8197F(x) \ + (((x) >> BIT_SHIFT_LLTE_RWM_8197F) & BIT_MASK_LLTE_RWM_8197F) +#define BIT_SET_LLTE_RWM_8197F(x, v) \ + (BIT_CLEAR_LLTE_RWM_8197F(x) | BIT_LLTE_RWM_8197F(v)) #define BIT_SHIFT_LLTINI_PDATA_V1_8197F 16 #define BIT_MASK_LLTINI_PDATA_V1_8197F 0xfff -#define BIT_LLTINI_PDATA_V1_8197F(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8197F) << BIT_SHIFT_LLTINI_PDATA_V1_8197F) -#define BITS_LLTINI_PDATA_V1_8197F (BIT_MASK_LLTINI_PDATA_V1_8197F << BIT_SHIFT_LLTINI_PDATA_V1_8197F) +#define BIT_LLTINI_PDATA_V1_8197F(x) \ + (((x) & BIT_MASK_LLTINI_PDATA_V1_8197F) \ + << BIT_SHIFT_LLTINI_PDATA_V1_8197F) +#define BITS_LLTINI_PDATA_V1_8197F \ + (BIT_MASK_LLTINI_PDATA_V1_8197F << BIT_SHIFT_LLTINI_PDATA_V1_8197F) #define BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_PDATA_V1_8197F)) -#define BIT_GET_LLTINI_PDATA_V1_8197F(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8197F) & BIT_MASK_LLTINI_PDATA_V1_8197F) -#define BIT_SET_LLTINI_PDATA_V1_8197F(x, v) (BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) | BIT_LLTINI_PDATA_V1_8197F(v)) - +#define BIT_GET_LLTINI_PDATA_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8197F) & \ + BIT_MASK_LLTINI_PDATA_V1_8197F) +#define BIT_SET_LLTINI_PDATA_V1_8197F(x, v) \ + (BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) | BIT_LLTINI_PDATA_V1_8197F(v)) #define BIT_SHIFT_LLTINI_HDATA_V1_8197F 0 #define BIT_MASK_LLTINI_HDATA_V1_8197F 0xfff -#define BIT_LLTINI_HDATA_V1_8197F(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8197F) << BIT_SHIFT_LLTINI_HDATA_V1_8197F) -#define BITS_LLTINI_HDATA_V1_8197F (BIT_MASK_LLTINI_HDATA_V1_8197F << BIT_SHIFT_LLTINI_HDATA_V1_8197F) +#define BIT_LLTINI_HDATA_V1_8197F(x) \ + (((x) & BIT_MASK_LLTINI_HDATA_V1_8197F) \ + << BIT_SHIFT_LLTINI_HDATA_V1_8197F) +#define BITS_LLTINI_HDATA_V1_8197F \ + (BIT_MASK_LLTINI_HDATA_V1_8197F << BIT_SHIFT_LLTINI_HDATA_V1_8197F) #define BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_HDATA_V1_8197F)) -#define BIT_GET_LLTINI_HDATA_V1_8197F(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8197F) & BIT_MASK_LLTINI_HDATA_V1_8197F) -#define BIT_SET_LLTINI_HDATA_V1_8197F(x, v) (BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) | BIT_LLTINI_HDATA_V1_8197F(v)) - +#define BIT_GET_LLTINI_HDATA_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8197F) & \ + BIT_MASK_LLTINI_HDATA_V1_8197F) +#define BIT_SET_LLTINI_HDATA_V1_8197F(x, v) \ + (BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) | BIT_LLTINI_HDATA_V1_8197F(v)) /* 2 REG_LLT_INIT_ADDR_8197F */ #define BIT_SHIFT_LLTINI_ADDR_V1_8197F 0 #define BIT_MASK_LLTINI_ADDR_V1_8197F 0xfff -#define BIT_LLTINI_ADDR_V1_8197F(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8197F) << BIT_SHIFT_LLTINI_ADDR_V1_8197F) -#define BITS_LLTINI_ADDR_V1_8197F (BIT_MASK_LLTINI_ADDR_V1_8197F << BIT_SHIFT_LLTINI_ADDR_V1_8197F) +#define BIT_LLTINI_ADDR_V1_8197F(x) \ + (((x) & BIT_MASK_LLTINI_ADDR_V1_8197F) \ + << BIT_SHIFT_LLTINI_ADDR_V1_8197F) +#define BITS_LLTINI_ADDR_V1_8197F \ + (BIT_MASK_LLTINI_ADDR_V1_8197F << BIT_SHIFT_LLTINI_ADDR_V1_8197F) #define BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) ((x) & (~BITS_LLTINI_ADDR_V1_8197F)) -#define BIT_GET_LLTINI_ADDR_V1_8197F(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8197F) & BIT_MASK_LLTINI_ADDR_V1_8197F) -#define BIT_SET_LLTINI_ADDR_V1_8197F(x, v) (BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) | BIT_LLTINI_ADDR_V1_8197F(v)) - +#define BIT_GET_LLTINI_ADDR_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8197F) & \ + BIT_MASK_LLTINI_ADDR_V1_8197F) +#define BIT_SET_LLTINI_ADDR_V1_8197F(x, v) \ + (BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) | BIT_LLTINI_ADDR_V1_8197F(v)) /* 2 REG_BB_ACCESS_CTRL_8197F */ #define BIT_SHIFT_BB_WRITE_READ_8197F 30 #define BIT_MASK_BB_WRITE_READ_8197F 0x3 -#define BIT_BB_WRITE_READ_8197F(x) (((x) & BIT_MASK_BB_WRITE_READ_8197F) << BIT_SHIFT_BB_WRITE_READ_8197F) -#define BITS_BB_WRITE_READ_8197F (BIT_MASK_BB_WRITE_READ_8197F << BIT_SHIFT_BB_WRITE_READ_8197F) +#define BIT_BB_WRITE_READ_8197F(x) \ + (((x) & BIT_MASK_BB_WRITE_READ_8197F) << BIT_SHIFT_BB_WRITE_READ_8197F) +#define BITS_BB_WRITE_READ_8197F \ + (BIT_MASK_BB_WRITE_READ_8197F << BIT_SHIFT_BB_WRITE_READ_8197F) #define BIT_CLEAR_BB_WRITE_READ_8197F(x) ((x) & (~BITS_BB_WRITE_READ_8197F)) -#define BIT_GET_BB_WRITE_READ_8197F(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8197F) & BIT_MASK_BB_WRITE_READ_8197F) -#define BIT_SET_BB_WRITE_READ_8197F(x, v) (BIT_CLEAR_BB_WRITE_READ_8197F(x) | BIT_BB_WRITE_READ_8197F(v)) - +#define BIT_GET_BB_WRITE_READ_8197F(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ_8197F) & BIT_MASK_BB_WRITE_READ_8197F) +#define BIT_SET_BB_WRITE_READ_8197F(x, v) \ + (BIT_CLEAR_BB_WRITE_READ_8197F(x) | BIT_BB_WRITE_READ_8197F(v)) #define BIT_SHIFT_BB_WRITE_EN_V1_8197F 16 #define BIT_MASK_BB_WRITE_EN_V1_8197F 0xf -#define BIT_BB_WRITE_EN_V1_8197F(x) (((x) & BIT_MASK_BB_WRITE_EN_V1_8197F) << BIT_SHIFT_BB_WRITE_EN_V1_8197F) -#define BITS_BB_WRITE_EN_V1_8197F (BIT_MASK_BB_WRITE_EN_V1_8197F << BIT_SHIFT_BB_WRITE_EN_V1_8197F) +#define BIT_BB_WRITE_EN_V1_8197F(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_V1_8197F) \ + << BIT_SHIFT_BB_WRITE_EN_V1_8197F) +#define BITS_BB_WRITE_EN_V1_8197F \ + (BIT_MASK_BB_WRITE_EN_V1_8197F << BIT_SHIFT_BB_WRITE_EN_V1_8197F) #define BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) ((x) & (~BITS_BB_WRITE_EN_V1_8197F)) -#define BIT_GET_BB_WRITE_EN_V1_8197F(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_V1_8197F) & BIT_MASK_BB_WRITE_EN_V1_8197F) -#define BIT_SET_BB_WRITE_EN_V1_8197F(x, v) (BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) | BIT_BB_WRITE_EN_V1_8197F(v)) - +#define BIT_GET_BB_WRITE_EN_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_V1_8197F) & \ + BIT_MASK_BB_WRITE_EN_V1_8197F) +#define BIT_SET_BB_WRITE_EN_V1_8197F(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) | BIT_BB_WRITE_EN_V1_8197F(v)) #define BIT_SHIFT_BB_ADDR_V1_8197F 2 #define BIT_MASK_BB_ADDR_V1_8197F 0xfff -#define BIT_BB_ADDR_V1_8197F(x) (((x) & BIT_MASK_BB_ADDR_V1_8197F) << BIT_SHIFT_BB_ADDR_V1_8197F) -#define BITS_BB_ADDR_V1_8197F (BIT_MASK_BB_ADDR_V1_8197F << BIT_SHIFT_BB_ADDR_V1_8197F) +#define BIT_BB_ADDR_V1_8197F(x) \ + (((x) & BIT_MASK_BB_ADDR_V1_8197F) << BIT_SHIFT_BB_ADDR_V1_8197F) +#define BITS_BB_ADDR_V1_8197F \ + (BIT_MASK_BB_ADDR_V1_8197F << BIT_SHIFT_BB_ADDR_V1_8197F) #define BIT_CLEAR_BB_ADDR_V1_8197F(x) ((x) & (~BITS_BB_ADDR_V1_8197F)) -#define BIT_GET_BB_ADDR_V1_8197F(x) (((x) >> BIT_SHIFT_BB_ADDR_V1_8197F) & BIT_MASK_BB_ADDR_V1_8197F) -#define BIT_SET_BB_ADDR_V1_8197F(x, v) (BIT_CLEAR_BB_ADDR_V1_8197F(x) | BIT_BB_ADDR_V1_8197F(v)) +#define BIT_GET_BB_ADDR_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_V1_8197F) & BIT_MASK_BB_ADDR_V1_8197F) +#define BIT_SET_BB_ADDR_V1_8197F(x, v) \ + (BIT_CLEAR_BB_ADDR_V1_8197F(x) | BIT_BB_ADDR_V1_8197F(v)) #define BIT_BB_ERRACC_8197F BIT(0) @@ -3173,56 +3986,70 @@ #define BIT_SHIFT_BB_DATA_8197F 0 #define BIT_MASK_BB_DATA_8197F 0xffffffffL -#define BIT_BB_DATA_8197F(x) (((x) & BIT_MASK_BB_DATA_8197F) << BIT_SHIFT_BB_DATA_8197F) +#define BIT_BB_DATA_8197F(x) \ + (((x) & BIT_MASK_BB_DATA_8197F) << BIT_SHIFT_BB_DATA_8197F) #define BITS_BB_DATA_8197F (BIT_MASK_BB_DATA_8197F << BIT_SHIFT_BB_DATA_8197F) #define BIT_CLEAR_BB_DATA_8197F(x) ((x) & (~BITS_BB_DATA_8197F)) -#define BIT_GET_BB_DATA_8197F(x) (((x) >> BIT_SHIFT_BB_DATA_8197F) & BIT_MASK_BB_DATA_8197F) -#define BIT_SET_BB_DATA_8197F(x, v) (BIT_CLEAR_BB_DATA_8197F(x) | BIT_BB_DATA_8197F(v)) - +#define BIT_GET_BB_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_BB_DATA_8197F) & BIT_MASK_BB_DATA_8197F) +#define BIT_SET_BB_DATA_8197F(x, v) \ + (BIT_CLEAR_BB_DATA_8197F(x) | BIT_BB_DATA_8197F(v)) /* 2 REG_HMEBOX_E0_8197F */ #define BIT_SHIFT_HMEBOX_E0_8197F 0 #define BIT_MASK_HMEBOX_E0_8197F 0xffffffffL -#define BIT_HMEBOX_E0_8197F(x) (((x) & BIT_MASK_HMEBOX_E0_8197F) << BIT_SHIFT_HMEBOX_E0_8197F) -#define BITS_HMEBOX_E0_8197F (BIT_MASK_HMEBOX_E0_8197F << BIT_SHIFT_HMEBOX_E0_8197F) +#define BIT_HMEBOX_E0_8197F(x) \ + (((x) & BIT_MASK_HMEBOX_E0_8197F) << BIT_SHIFT_HMEBOX_E0_8197F) +#define BITS_HMEBOX_E0_8197F \ + (BIT_MASK_HMEBOX_E0_8197F << BIT_SHIFT_HMEBOX_E0_8197F) #define BIT_CLEAR_HMEBOX_E0_8197F(x) ((x) & (~BITS_HMEBOX_E0_8197F)) -#define BIT_GET_HMEBOX_E0_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8197F) & BIT_MASK_HMEBOX_E0_8197F) -#define BIT_SET_HMEBOX_E0_8197F(x, v) (BIT_CLEAR_HMEBOX_E0_8197F(x) | BIT_HMEBOX_E0_8197F(v)) - +#define BIT_GET_HMEBOX_E0_8197F(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E0_8197F) & BIT_MASK_HMEBOX_E0_8197F) +#define BIT_SET_HMEBOX_E0_8197F(x, v) \ + (BIT_CLEAR_HMEBOX_E0_8197F(x) | BIT_HMEBOX_E0_8197F(v)) /* 2 REG_HMEBOX_E1_8197F */ #define BIT_SHIFT_HMEBOX_E1_8197F 0 #define BIT_MASK_HMEBOX_E1_8197F 0xffffffffL -#define BIT_HMEBOX_E1_8197F(x) (((x) & BIT_MASK_HMEBOX_E1_8197F) << BIT_SHIFT_HMEBOX_E1_8197F) -#define BITS_HMEBOX_E1_8197F (BIT_MASK_HMEBOX_E1_8197F << BIT_SHIFT_HMEBOX_E1_8197F) +#define BIT_HMEBOX_E1_8197F(x) \ + (((x) & BIT_MASK_HMEBOX_E1_8197F) << BIT_SHIFT_HMEBOX_E1_8197F) +#define BITS_HMEBOX_E1_8197F \ + (BIT_MASK_HMEBOX_E1_8197F << BIT_SHIFT_HMEBOX_E1_8197F) #define BIT_CLEAR_HMEBOX_E1_8197F(x) ((x) & (~BITS_HMEBOX_E1_8197F)) -#define BIT_GET_HMEBOX_E1_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8197F) & BIT_MASK_HMEBOX_E1_8197F) -#define BIT_SET_HMEBOX_E1_8197F(x, v) (BIT_CLEAR_HMEBOX_E1_8197F(x) | BIT_HMEBOX_E1_8197F(v)) - +#define BIT_GET_HMEBOX_E1_8197F(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E1_8197F) & BIT_MASK_HMEBOX_E1_8197F) +#define BIT_SET_HMEBOX_E1_8197F(x, v) \ + (BIT_CLEAR_HMEBOX_E1_8197F(x) | BIT_HMEBOX_E1_8197F(v)) /* 2 REG_HMEBOX_E2_8197F */ #define BIT_SHIFT_HMEBOX_E2_8197F 0 #define BIT_MASK_HMEBOX_E2_8197F 0xffffffffL -#define BIT_HMEBOX_E2_8197F(x) (((x) & BIT_MASK_HMEBOX_E2_8197F) << BIT_SHIFT_HMEBOX_E2_8197F) -#define BITS_HMEBOX_E2_8197F (BIT_MASK_HMEBOX_E2_8197F << BIT_SHIFT_HMEBOX_E2_8197F) +#define BIT_HMEBOX_E2_8197F(x) \ + (((x) & BIT_MASK_HMEBOX_E2_8197F) << BIT_SHIFT_HMEBOX_E2_8197F) +#define BITS_HMEBOX_E2_8197F \ + (BIT_MASK_HMEBOX_E2_8197F << BIT_SHIFT_HMEBOX_E2_8197F) #define BIT_CLEAR_HMEBOX_E2_8197F(x) ((x) & (~BITS_HMEBOX_E2_8197F)) -#define BIT_GET_HMEBOX_E2_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8197F) & BIT_MASK_HMEBOX_E2_8197F) -#define BIT_SET_HMEBOX_E2_8197F(x, v) (BIT_CLEAR_HMEBOX_E2_8197F(x) | BIT_HMEBOX_E2_8197F(v)) - +#define BIT_GET_HMEBOX_E2_8197F(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E2_8197F) & BIT_MASK_HMEBOX_E2_8197F) +#define BIT_SET_HMEBOX_E2_8197F(x, v) \ + (BIT_CLEAR_HMEBOX_E2_8197F(x) | BIT_HMEBOX_E2_8197F(v)) /* 2 REG_HMEBOX_E3_8197F */ #define BIT_SHIFT_HMEBOX_E3_8197F 0 #define BIT_MASK_HMEBOX_E3_8197F 0xffffffffL -#define BIT_HMEBOX_E3_8197F(x) (((x) & BIT_MASK_HMEBOX_E3_8197F) << BIT_SHIFT_HMEBOX_E3_8197F) -#define BITS_HMEBOX_E3_8197F (BIT_MASK_HMEBOX_E3_8197F << BIT_SHIFT_HMEBOX_E3_8197F) +#define BIT_HMEBOX_E3_8197F(x) \ + (((x) & BIT_MASK_HMEBOX_E3_8197F) << BIT_SHIFT_HMEBOX_E3_8197F) +#define BITS_HMEBOX_E3_8197F \ + (BIT_MASK_HMEBOX_E3_8197F << BIT_SHIFT_HMEBOX_E3_8197F) #define BIT_CLEAR_HMEBOX_E3_8197F(x) ((x) & (~BITS_HMEBOX_E3_8197F)) -#define BIT_GET_HMEBOX_E3_8197F(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8197F) & BIT_MASK_HMEBOX_E3_8197F) -#define BIT_SET_HMEBOX_E3_8197F(x, v) (BIT_CLEAR_HMEBOX_E3_8197F(x) | BIT_HMEBOX_E3_8197F(v)) - +#define BIT_GET_HMEBOX_E3_8197F(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E3_8197F) & BIT_MASK_HMEBOX_E3_8197F) +#define BIT_SET_HMEBOX_E3_8197F(x, v) \ + (BIT_CLEAR_HMEBOX_E3_8197F(x) | BIT_HMEBOX_E3_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -3230,69 +4057,88 @@ #define BIT_SHIFT_PHY_REQ_DELAY_8197F 24 #define BIT_MASK_PHY_REQ_DELAY_8197F 0xf -#define BIT_PHY_REQ_DELAY_8197F(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8197F) << BIT_SHIFT_PHY_REQ_DELAY_8197F) -#define BITS_PHY_REQ_DELAY_8197F (BIT_MASK_PHY_REQ_DELAY_8197F << BIT_SHIFT_PHY_REQ_DELAY_8197F) +#define BIT_PHY_REQ_DELAY_8197F(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY_8197F) << BIT_SHIFT_PHY_REQ_DELAY_8197F) +#define BITS_PHY_REQ_DELAY_8197F \ + (BIT_MASK_PHY_REQ_DELAY_8197F << BIT_SHIFT_PHY_REQ_DELAY_8197F) #define BIT_CLEAR_PHY_REQ_DELAY_8197F(x) ((x) & (~BITS_PHY_REQ_DELAY_8197F)) -#define BIT_GET_PHY_REQ_DELAY_8197F(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8197F) & BIT_MASK_PHY_REQ_DELAY_8197F) -#define BIT_SET_PHY_REQ_DELAY_8197F(x, v) (BIT_CLEAR_PHY_REQ_DELAY_8197F(x) | BIT_PHY_REQ_DELAY_8197F(v)) +#define BIT_GET_PHY_REQ_DELAY_8197F(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8197F) & BIT_MASK_PHY_REQ_DELAY_8197F) +#define BIT_SET_PHY_REQ_DELAY_8197F(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY_8197F(x) | BIT_PHY_REQ_DELAY_8197F(v)) #define BIT_SPD_DOWN_8197F BIT(16) #define BIT_SHIFT_NETYPE4_8197F 4 #define BIT_MASK_NETYPE4_8197F 0x3 -#define BIT_NETYPE4_8197F(x) (((x) & BIT_MASK_NETYPE4_8197F) << BIT_SHIFT_NETYPE4_8197F) +#define BIT_NETYPE4_8197F(x) \ + (((x) & BIT_MASK_NETYPE4_8197F) << BIT_SHIFT_NETYPE4_8197F) #define BITS_NETYPE4_8197F (BIT_MASK_NETYPE4_8197F << BIT_SHIFT_NETYPE4_8197F) #define BIT_CLEAR_NETYPE4_8197F(x) ((x) & (~BITS_NETYPE4_8197F)) -#define BIT_GET_NETYPE4_8197F(x) (((x) >> BIT_SHIFT_NETYPE4_8197F) & BIT_MASK_NETYPE4_8197F) -#define BIT_SET_NETYPE4_8197F(x, v) (BIT_CLEAR_NETYPE4_8197F(x) | BIT_NETYPE4_8197F(v)) - +#define BIT_GET_NETYPE4_8197F(x) \ + (((x) >> BIT_SHIFT_NETYPE4_8197F) & BIT_MASK_NETYPE4_8197F) +#define BIT_SET_NETYPE4_8197F(x, v) \ + (BIT_CLEAR_NETYPE4_8197F(x) | BIT_NETYPE4_8197F(v)) #define BIT_SHIFT_NETYPE3_8197F 2 #define BIT_MASK_NETYPE3_8197F 0x3 -#define BIT_NETYPE3_8197F(x) (((x) & BIT_MASK_NETYPE3_8197F) << BIT_SHIFT_NETYPE3_8197F) +#define BIT_NETYPE3_8197F(x) \ + (((x) & BIT_MASK_NETYPE3_8197F) << BIT_SHIFT_NETYPE3_8197F) #define BITS_NETYPE3_8197F (BIT_MASK_NETYPE3_8197F << BIT_SHIFT_NETYPE3_8197F) #define BIT_CLEAR_NETYPE3_8197F(x) ((x) & (~BITS_NETYPE3_8197F)) -#define BIT_GET_NETYPE3_8197F(x) (((x) >> BIT_SHIFT_NETYPE3_8197F) & BIT_MASK_NETYPE3_8197F) -#define BIT_SET_NETYPE3_8197F(x, v) (BIT_CLEAR_NETYPE3_8197F(x) | BIT_NETYPE3_8197F(v)) - +#define BIT_GET_NETYPE3_8197F(x) \ + (((x) >> BIT_SHIFT_NETYPE3_8197F) & BIT_MASK_NETYPE3_8197F) +#define BIT_SET_NETYPE3_8197F(x, v) \ + (BIT_CLEAR_NETYPE3_8197F(x) | BIT_NETYPE3_8197F(v)) #define BIT_SHIFT_NETYPE2_8197F 0 #define BIT_MASK_NETYPE2_8197F 0x3 -#define BIT_NETYPE2_8197F(x) (((x) & BIT_MASK_NETYPE2_8197F) << BIT_SHIFT_NETYPE2_8197F) +#define BIT_NETYPE2_8197F(x) \ + (((x) & BIT_MASK_NETYPE2_8197F) << BIT_SHIFT_NETYPE2_8197F) #define BITS_NETYPE2_8197F (BIT_MASK_NETYPE2_8197F << BIT_SHIFT_NETYPE2_8197F) #define BIT_CLEAR_NETYPE2_8197F(x) ((x) & (~BITS_NETYPE2_8197F)) -#define BIT_GET_NETYPE2_8197F(x) (((x) >> BIT_SHIFT_NETYPE2_8197F) & BIT_MASK_NETYPE2_8197F) -#define BIT_SET_NETYPE2_8197F(x, v) (BIT_CLEAR_NETYPE2_8197F(x) | BIT_NETYPE2_8197F(v)) - +#define BIT_GET_NETYPE2_8197F(x) \ + (((x) >> BIT_SHIFT_NETYPE2_8197F) & BIT_MASK_NETYPE2_8197F) +#define BIT_SET_NETYPE2_8197F(x, v) \ + (BIT_CLEAR_NETYPE2_8197F(x) | BIT_NETYPE2_8197F(v)) /* 2 REG_FWFF_8197F */ #define BIT_SHIFT_PKTNUM_TH_8197F 24 #define BIT_MASK_PKTNUM_TH_8197F 0xff -#define BIT_PKTNUM_TH_8197F(x) (((x) & BIT_MASK_PKTNUM_TH_8197F) << BIT_SHIFT_PKTNUM_TH_8197F) -#define BITS_PKTNUM_TH_8197F (BIT_MASK_PKTNUM_TH_8197F << BIT_SHIFT_PKTNUM_TH_8197F) +#define BIT_PKTNUM_TH_8197F(x) \ + (((x) & BIT_MASK_PKTNUM_TH_8197F) << BIT_SHIFT_PKTNUM_TH_8197F) +#define BITS_PKTNUM_TH_8197F \ + (BIT_MASK_PKTNUM_TH_8197F << BIT_SHIFT_PKTNUM_TH_8197F) #define BIT_CLEAR_PKTNUM_TH_8197F(x) ((x) & (~BITS_PKTNUM_TH_8197F)) -#define BIT_GET_PKTNUM_TH_8197F(x) (((x) >> BIT_SHIFT_PKTNUM_TH_8197F) & BIT_MASK_PKTNUM_TH_8197F) -#define BIT_SET_PKTNUM_TH_8197F(x, v) (BIT_CLEAR_PKTNUM_TH_8197F(x) | BIT_PKTNUM_TH_8197F(v)) - +#define BIT_GET_PKTNUM_TH_8197F(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_8197F) & BIT_MASK_PKTNUM_TH_8197F) +#define BIT_SET_PKTNUM_TH_8197F(x, v) \ + (BIT_CLEAR_PKTNUM_TH_8197F(x) | BIT_PKTNUM_TH_8197F(v)) #define BIT_SHIFT_TIMER_TH_8197F 16 #define BIT_MASK_TIMER_TH_8197F 0xff -#define BIT_TIMER_TH_8197F(x) (((x) & BIT_MASK_TIMER_TH_8197F) << BIT_SHIFT_TIMER_TH_8197F) -#define BITS_TIMER_TH_8197F (BIT_MASK_TIMER_TH_8197F << BIT_SHIFT_TIMER_TH_8197F) +#define BIT_TIMER_TH_8197F(x) \ + (((x) & BIT_MASK_TIMER_TH_8197F) << BIT_SHIFT_TIMER_TH_8197F) +#define BITS_TIMER_TH_8197F \ + (BIT_MASK_TIMER_TH_8197F << BIT_SHIFT_TIMER_TH_8197F) #define BIT_CLEAR_TIMER_TH_8197F(x) ((x) & (~BITS_TIMER_TH_8197F)) -#define BIT_GET_TIMER_TH_8197F(x) (((x) >> BIT_SHIFT_TIMER_TH_8197F) & BIT_MASK_TIMER_TH_8197F) -#define BIT_SET_TIMER_TH_8197F(x, v) (BIT_CLEAR_TIMER_TH_8197F(x) | BIT_TIMER_TH_8197F(v)) - +#define BIT_GET_TIMER_TH_8197F(x) \ + (((x) >> BIT_SHIFT_TIMER_TH_8197F) & BIT_MASK_TIMER_TH_8197F) +#define BIT_SET_TIMER_TH_8197F(x, v) \ + (BIT_CLEAR_TIMER_TH_8197F(x) | BIT_TIMER_TH_8197F(v)) #define BIT_SHIFT_RXPKT1ENADDR_8197F 0 #define BIT_MASK_RXPKT1ENADDR_8197F 0xffff -#define BIT_RXPKT1ENADDR_8197F(x) (((x) & BIT_MASK_RXPKT1ENADDR_8197F) << BIT_SHIFT_RXPKT1ENADDR_8197F) -#define BITS_RXPKT1ENADDR_8197F (BIT_MASK_RXPKT1ENADDR_8197F << BIT_SHIFT_RXPKT1ENADDR_8197F) +#define BIT_RXPKT1ENADDR_8197F(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR_8197F) << BIT_SHIFT_RXPKT1ENADDR_8197F) +#define BITS_RXPKT1ENADDR_8197F \ + (BIT_MASK_RXPKT1ENADDR_8197F << BIT_SHIFT_RXPKT1ENADDR_8197F) #define BIT_CLEAR_RXPKT1ENADDR_8197F(x) ((x) & (~BITS_RXPKT1ENADDR_8197F)) -#define BIT_GET_RXPKT1ENADDR_8197F(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8197F) & BIT_MASK_RXPKT1ENADDR_8197F) -#define BIT_SET_RXPKT1ENADDR_8197F(x, v) (BIT_CLEAR_RXPKT1ENADDR_8197F(x) | BIT_RXPKT1ENADDR_8197F(v)) - +#define BIT_GET_RXPKT1ENADDR_8197F(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR_8197F) & BIT_MASK_RXPKT1ENADDR_8197F) +#define BIT_SET_RXPKT1ENADDR_8197F(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR_8197F(x) | BIT_RXPKT1ENADDR_8197F(v)) /* 2 REG_RXFF_PTR_V1_8197F */ @@ -3300,12 +4146,17 @@ #define BIT_SHIFT_RXFF0_RDPTR_V2_8197F 0 #define BIT_MASK_RXFF0_RDPTR_V2_8197F 0x3ffff -#define BIT_RXFF0_RDPTR_V2_8197F(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8197F) << BIT_SHIFT_RXFF0_RDPTR_V2_8197F) -#define BITS_RXFF0_RDPTR_V2_8197F (BIT_MASK_RXFF0_RDPTR_V2_8197F << BIT_SHIFT_RXFF0_RDPTR_V2_8197F) +#define BIT_RXFF0_RDPTR_V2_8197F(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2_8197F) \ + << BIT_SHIFT_RXFF0_RDPTR_V2_8197F) +#define BITS_RXFF0_RDPTR_V2_8197F \ + (BIT_MASK_RXFF0_RDPTR_V2_8197F << BIT_SHIFT_RXFF0_RDPTR_V2_8197F) #define BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8197F)) -#define BIT_GET_RXFF0_RDPTR_V2_8197F(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8197F) & BIT_MASK_RXFF0_RDPTR_V2_8197F) -#define BIT_SET_RXFF0_RDPTR_V2_8197F(x, v) (BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) | BIT_RXFF0_RDPTR_V2_8197F(v)) - +#define BIT_GET_RXFF0_RDPTR_V2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8197F) & \ + BIT_MASK_RXFF0_RDPTR_V2_8197F) +#define BIT_SET_RXFF0_RDPTR_V2_8197F(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) | BIT_RXFF0_RDPTR_V2_8197F(v)) /* 2 REG_RXFF_WTR_V1_8197F */ @@ -3313,12 +4164,17 @@ #define BIT_SHIFT_RXFF0_WTPTR_V2_8197F 0 #define BIT_MASK_RXFF0_WTPTR_V2_8197F 0x3ffff -#define BIT_RXFF0_WTPTR_V2_8197F(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8197F) << BIT_SHIFT_RXFF0_WTPTR_V2_8197F) -#define BITS_RXFF0_WTPTR_V2_8197F (BIT_MASK_RXFF0_WTPTR_V2_8197F << BIT_SHIFT_RXFF0_WTPTR_V2_8197F) +#define BIT_RXFF0_WTPTR_V2_8197F(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2_8197F) \ + << BIT_SHIFT_RXFF0_WTPTR_V2_8197F) +#define BITS_RXFF0_WTPTR_V2_8197F \ + (BIT_MASK_RXFF0_WTPTR_V2_8197F << BIT_SHIFT_RXFF0_WTPTR_V2_8197F) #define BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8197F)) -#define BIT_GET_RXFF0_WTPTR_V2_8197F(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8197F) & BIT_MASK_RXFF0_WTPTR_V2_8197F) -#define BIT_SET_RXFF0_WTPTR_V2_8197F(x, v) (BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) | BIT_RXFF0_WTPTR_V2_8197F(v)) - +#define BIT_GET_RXFF0_WTPTR_V2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8197F) & \ + BIT_MASK_RXFF0_WTPTR_V2_8197F) +#define BIT_SET_RXFF0_WTPTR_V2_8197F(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) | BIT_RXFF0_WTPTR_V2_8197F(v)) /* 2 REG_FE2IMR_8197F */ #define BIT_FS_TXSC_DESC_DONE_INT_EN_8197F BIT(28) @@ -3550,65 +4406,82 @@ #define BIT_SHIFT_MID_31TO0_8197F 0 #define BIT_MASK_MID_31TO0_8197F 0xffffffffL -#define BIT_MID_31TO0_8197F(x) (((x) & BIT_MASK_MID_31TO0_8197F) << BIT_SHIFT_MID_31TO0_8197F) -#define BITS_MID_31TO0_8197F (BIT_MASK_MID_31TO0_8197F << BIT_SHIFT_MID_31TO0_8197F) +#define BIT_MID_31TO0_8197F(x) \ + (((x) & BIT_MASK_MID_31TO0_8197F) << BIT_SHIFT_MID_31TO0_8197F) +#define BITS_MID_31TO0_8197F \ + (BIT_MASK_MID_31TO0_8197F << BIT_SHIFT_MID_31TO0_8197F) #define BIT_CLEAR_MID_31TO0_8197F(x) ((x) & (~BITS_MID_31TO0_8197F)) -#define BIT_GET_MID_31TO0_8197F(x) (((x) >> BIT_SHIFT_MID_31TO0_8197F) & BIT_MASK_MID_31TO0_8197F) -#define BIT_SET_MID_31TO0_8197F(x, v) (BIT_CLEAR_MID_31TO0_8197F(x) | BIT_MID_31TO0_8197F(v)) - +#define BIT_GET_MID_31TO0_8197F(x) \ + (((x) >> BIT_SHIFT_MID_31TO0_8197F) & BIT_MASK_MID_31TO0_8197F) +#define BIT_SET_MID_31TO0_8197F(x, v) \ + (BIT_CLEAR_MID_31TO0_8197F(x) | BIT_MID_31TO0_8197F(v)) /* 2 REG_SPWR1_8197F */ #define BIT_SHIFT_MID_63TO32_8197F 0 #define BIT_MASK_MID_63TO32_8197F 0xffffffffL -#define BIT_MID_63TO32_8197F(x) (((x) & BIT_MASK_MID_63TO32_8197F) << BIT_SHIFT_MID_63TO32_8197F) -#define BITS_MID_63TO32_8197F (BIT_MASK_MID_63TO32_8197F << BIT_SHIFT_MID_63TO32_8197F) +#define BIT_MID_63TO32_8197F(x) \ + (((x) & BIT_MASK_MID_63TO32_8197F) << BIT_SHIFT_MID_63TO32_8197F) +#define BITS_MID_63TO32_8197F \ + (BIT_MASK_MID_63TO32_8197F << BIT_SHIFT_MID_63TO32_8197F) #define BIT_CLEAR_MID_63TO32_8197F(x) ((x) & (~BITS_MID_63TO32_8197F)) -#define BIT_GET_MID_63TO32_8197F(x) (((x) >> BIT_SHIFT_MID_63TO32_8197F) & BIT_MASK_MID_63TO32_8197F) -#define BIT_SET_MID_63TO32_8197F(x, v) (BIT_CLEAR_MID_63TO32_8197F(x) | BIT_MID_63TO32_8197F(v)) - +#define BIT_GET_MID_63TO32_8197F(x) \ + (((x) >> BIT_SHIFT_MID_63TO32_8197F) & BIT_MASK_MID_63TO32_8197F) +#define BIT_SET_MID_63TO32_8197F(x, v) \ + (BIT_CLEAR_MID_63TO32_8197F(x) | BIT_MID_63TO32_8197F(v)) /* 2 REG_SPWR2_8197F */ #define BIT_SHIFT_MID_95O64_8197F 0 #define BIT_MASK_MID_95O64_8197F 0xffffffffL -#define BIT_MID_95O64_8197F(x) (((x) & BIT_MASK_MID_95O64_8197F) << BIT_SHIFT_MID_95O64_8197F) -#define BITS_MID_95O64_8197F (BIT_MASK_MID_95O64_8197F << BIT_SHIFT_MID_95O64_8197F) +#define BIT_MID_95O64_8197F(x) \ + (((x) & BIT_MASK_MID_95O64_8197F) << BIT_SHIFT_MID_95O64_8197F) +#define BITS_MID_95O64_8197F \ + (BIT_MASK_MID_95O64_8197F << BIT_SHIFT_MID_95O64_8197F) #define BIT_CLEAR_MID_95O64_8197F(x) ((x) & (~BITS_MID_95O64_8197F)) -#define BIT_GET_MID_95O64_8197F(x) (((x) >> BIT_SHIFT_MID_95O64_8197F) & BIT_MASK_MID_95O64_8197F) -#define BIT_SET_MID_95O64_8197F(x, v) (BIT_CLEAR_MID_95O64_8197F(x) | BIT_MID_95O64_8197F(v)) - +#define BIT_GET_MID_95O64_8197F(x) \ + (((x) >> BIT_SHIFT_MID_95O64_8197F) & BIT_MASK_MID_95O64_8197F) +#define BIT_SET_MID_95O64_8197F(x, v) \ + (BIT_CLEAR_MID_95O64_8197F(x) | BIT_MID_95O64_8197F(v)) /* 2 REG_SPWR3_8197F */ #define BIT_SHIFT_MID_127TO96_8197F 0 #define BIT_MASK_MID_127TO96_8197F 0xffffffffL -#define BIT_MID_127TO96_8197F(x) (((x) & BIT_MASK_MID_127TO96_8197F) << BIT_SHIFT_MID_127TO96_8197F) -#define BITS_MID_127TO96_8197F (BIT_MASK_MID_127TO96_8197F << BIT_SHIFT_MID_127TO96_8197F) +#define BIT_MID_127TO96_8197F(x) \ + (((x) & BIT_MASK_MID_127TO96_8197F) << BIT_SHIFT_MID_127TO96_8197F) +#define BITS_MID_127TO96_8197F \ + (BIT_MASK_MID_127TO96_8197F << BIT_SHIFT_MID_127TO96_8197F) #define BIT_CLEAR_MID_127TO96_8197F(x) ((x) & (~BITS_MID_127TO96_8197F)) -#define BIT_GET_MID_127TO96_8197F(x) (((x) >> BIT_SHIFT_MID_127TO96_8197F) & BIT_MASK_MID_127TO96_8197F) -#define BIT_SET_MID_127TO96_8197F(x, v) (BIT_CLEAR_MID_127TO96_8197F(x) | BIT_MID_127TO96_8197F(v)) - +#define BIT_GET_MID_127TO96_8197F(x) \ + (((x) >> BIT_SHIFT_MID_127TO96_8197F) & BIT_MASK_MID_127TO96_8197F) +#define BIT_SET_MID_127TO96_8197F(x, v) \ + (BIT_CLEAR_MID_127TO96_8197F(x) | BIT_MID_127TO96_8197F(v)) /* 2 REG_POWSEQ_8197F */ #define BIT_SHIFT_SEQNUM_MID_8197F 16 #define BIT_MASK_SEQNUM_MID_8197F 0xffff -#define BIT_SEQNUM_MID_8197F(x) (((x) & BIT_MASK_SEQNUM_MID_8197F) << BIT_SHIFT_SEQNUM_MID_8197F) -#define BITS_SEQNUM_MID_8197F (BIT_MASK_SEQNUM_MID_8197F << BIT_SHIFT_SEQNUM_MID_8197F) +#define BIT_SEQNUM_MID_8197F(x) \ + (((x) & BIT_MASK_SEQNUM_MID_8197F) << BIT_SHIFT_SEQNUM_MID_8197F) +#define BITS_SEQNUM_MID_8197F \ + (BIT_MASK_SEQNUM_MID_8197F << BIT_SHIFT_SEQNUM_MID_8197F) #define BIT_CLEAR_SEQNUM_MID_8197F(x) ((x) & (~BITS_SEQNUM_MID_8197F)) -#define BIT_GET_SEQNUM_MID_8197F(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8197F) & BIT_MASK_SEQNUM_MID_8197F) -#define BIT_SET_SEQNUM_MID_8197F(x, v) (BIT_CLEAR_SEQNUM_MID_8197F(x) | BIT_SEQNUM_MID_8197F(v)) - +#define BIT_GET_SEQNUM_MID_8197F(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID_8197F) & BIT_MASK_SEQNUM_MID_8197F) +#define BIT_SET_SEQNUM_MID_8197F(x, v) \ + (BIT_CLEAR_SEQNUM_MID_8197F(x) | BIT_SEQNUM_MID_8197F(v)) #define BIT_SHIFT_REF_MID_8197F 0 #define BIT_MASK_REF_MID_8197F 0x7f -#define BIT_REF_MID_8197F(x) (((x) & BIT_MASK_REF_MID_8197F) << BIT_SHIFT_REF_MID_8197F) +#define BIT_REF_MID_8197F(x) \ + (((x) & BIT_MASK_REF_MID_8197F) << BIT_SHIFT_REF_MID_8197F) #define BITS_REF_MID_8197F (BIT_MASK_REF_MID_8197F << BIT_SHIFT_REF_MID_8197F) #define BIT_CLEAR_REF_MID_8197F(x) ((x) & (~BITS_REF_MID_8197F)) -#define BIT_GET_REF_MID_8197F(x) (((x) >> BIT_SHIFT_REF_MID_8197F) & BIT_MASK_REF_MID_8197F) -#define BIT_SET_REF_MID_8197F(x, v) (BIT_CLEAR_REF_MID_8197F(x) | BIT_REF_MID_8197F(v)) - +#define BIT_GET_REF_MID_8197F(x) \ + (((x) >> BIT_SHIFT_REF_MID_8197F) & BIT_MASK_REF_MID_8197F) +#define BIT_SET_REF_MID_8197F(x, v) \ + (BIT_CLEAR_REF_MID_8197F(x) | BIT_REF_MID_8197F(v)) /* 2 REG_TC7_CTRL_V1_8197F */ #define BIT_TC7INT_EN_8197F BIT(26) @@ -3617,12 +4490,14 @@ #define BIT_SHIFT_TC7DATA_8197F 0 #define BIT_MASK_TC7DATA_8197F 0xffffff -#define BIT_TC7DATA_8197F(x) (((x) & BIT_MASK_TC7DATA_8197F) << BIT_SHIFT_TC7DATA_8197F) +#define BIT_TC7DATA_8197F(x) \ + (((x) & BIT_MASK_TC7DATA_8197F) << BIT_SHIFT_TC7DATA_8197F) #define BITS_TC7DATA_8197F (BIT_MASK_TC7DATA_8197F << BIT_SHIFT_TC7DATA_8197F) #define BIT_CLEAR_TC7DATA_8197F(x) ((x) & (~BITS_TC7DATA_8197F)) -#define BIT_GET_TC7DATA_8197F(x) (((x) >> BIT_SHIFT_TC7DATA_8197F) & BIT_MASK_TC7DATA_8197F) -#define BIT_SET_TC7DATA_8197F(x, v) (BIT_CLEAR_TC7DATA_8197F(x) | BIT_TC7DATA_8197F(v)) - +#define BIT_GET_TC7DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC7DATA_8197F) & BIT_MASK_TC7DATA_8197F) +#define BIT_SET_TC7DATA_8197F(x, v) \ + (BIT_CLEAR_TC7DATA_8197F(x) | BIT_TC7DATA_8197F(v)) /* 2 REG_TC8_CTRL_V1_8197F */ #define BIT_TC8INT_EN_8197F BIT(26) @@ -3631,12 +4506,14 @@ #define BIT_SHIFT_TC8DATA_8197F 0 #define BIT_MASK_TC8DATA_8197F 0xffffff -#define BIT_TC8DATA_8197F(x) (((x) & BIT_MASK_TC8DATA_8197F) << BIT_SHIFT_TC8DATA_8197F) +#define BIT_TC8DATA_8197F(x) \ + (((x) & BIT_MASK_TC8DATA_8197F) << BIT_SHIFT_TC8DATA_8197F) #define BITS_TC8DATA_8197F (BIT_MASK_TC8DATA_8197F << BIT_SHIFT_TC8DATA_8197F) #define BIT_CLEAR_TC8DATA_8197F(x) ((x) & (~BITS_TC8DATA_8197F)) -#define BIT_GET_TC8DATA_8197F(x) (((x) >> BIT_SHIFT_TC8DATA_8197F) & BIT_MASK_TC8DATA_8197F) -#define BIT_SET_TC8DATA_8197F(x, v) (BIT_CLEAR_TC8DATA_8197F(x) | BIT_TC8DATA_8197F(v)) - +#define BIT_GET_TC8DATA_8197F(x) \ + (((x) >> BIT_SHIFT_TC8DATA_8197F) & BIT_MASK_TC8DATA_8197F) +#define BIT_SET_TC8DATA_8197F(x, v) \ + (BIT_CLEAR_TC8DATA_8197F(x) | BIT_TC8DATA_8197F(v)) /* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F */ @@ -3646,22 +4523,32 @@ #define BIT_SHIFT_PCIE_PRIORITY_SEL_8197F 0 #define BIT_MASK_PCIE_PRIORITY_SEL_8197F 0x3 -#define BIT_PCIE_PRIORITY_SEL_8197F(x) (((x) & BIT_MASK_PCIE_PRIORITY_SEL_8197F) << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) -#define BITS_PCIE_PRIORITY_SEL_8197F (BIT_MASK_PCIE_PRIORITY_SEL_8197F << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) -#define BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) ((x) & (~BITS_PCIE_PRIORITY_SEL_8197F)) -#define BIT_GET_PCIE_PRIORITY_SEL_8197F(x) (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) & BIT_MASK_PCIE_PRIORITY_SEL_8197F) -#define BIT_SET_PCIE_PRIORITY_SEL_8197F(x, v) (BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) | BIT_PCIE_PRIORITY_SEL_8197F(v)) - +#define BIT_PCIE_PRIORITY_SEL_8197F(x) \ + (((x) & BIT_MASK_PCIE_PRIORITY_SEL_8197F) \ + << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) +#define BITS_PCIE_PRIORITY_SEL_8197F \ + (BIT_MASK_PCIE_PRIORITY_SEL_8197F << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) +#define BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) \ + ((x) & (~BITS_PCIE_PRIORITY_SEL_8197F)) +#define BIT_GET_PCIE_PRIORITY_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) & \ + BIT_MASK_PCIE_PRIORITY_SEL_8197F) +#define BIT_SET_PCIE_PRIORITY_SEL_8197F(x, v) \ + (BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) | BIT_PCIE_PRIORITY_SEL_8197F(v)) /* 2 REG_COUNTER_CONTROL_8197F */ #define BIT_SHIFT_COUNTER_BASE_8197F 16 #define BIT_MASK_COUNTER_BASE_8197F 0x1fff -#define BIT_COUNTER_BASE_8197F(x) (((x) & BIT_MASK_COUNTER_BASE_8197F) << BIT_SHIFT_COUNTER_BASE_8197F) -#define BITS_COUNTER_BASE_8197F (BIT_MASK_COUNTER_BASE_8197F << BIT_SHIFT_COUNTER_BASE_8197F) +#define BIT_COUNTER_BASE_8197F(x) \ + (((x) & BIT_MASK_COUNTER_BASE_8197F) << BIT_SHIFT_COUNTER_BASE_8197F) +#define BITS_COUNTER_BASE_8197F \ + (BIT_MASK_COUNTER_BASE_8197F << BIT_SHIFT_COUNTER_BASE_8197F) #define BIT_CLEAR_COUNTER_BASE_8197F(x) ((x) & (~BITS_COUNTER_BASE_8197F)) -#define BIT_GET_COUNTER_BASE_8197F(x) (((x) >> BIT_SHIFT_COUNTER_BASE_8197F) & BIT_MASK_COUNTER_BASE_8197F) -#define BIT_SET_COUNTER_BASE_8197F(x, v) (BIT_CLEAR_COUNTER_BASE_8197F(x) | BIT_COUNTER_BASE_8197F(v)) +#define BIT_GET_COUNTER_BASE_8197F(x) \ + (((x) >> BIT_SHIFT_COUNTER_BASE_8197F) & BIT_MASK_COUNTER_BASE_8197F) +#define BIT_SET_COUNTER_BASE_8197F(x, v) \ + (BIT_CLEAR_COUNTER_BASE_8197F(x) | BIT_COUNTER_BASE_8197F(v)) #define BIT_EN_RTS_REQ_8197F BIT(9) #define BIT_EN_EDCA_REQ_8197F BIT(8) @@ -3679,39 +4566,51 @@ #define BIT_SHIFT_CNT_MACID_8197F 24 #define BIT_MASK_CNT_MACID_8197F 0x7f -#define BIT_CNT_MACID_8197F(x) (((x) & BIT_MASK_CNT_MACID_8197F) << BIT_SHIFT_CNT_MACID_8197F) -#define BITS_CNT_MACID_8197F (BIT_MASK_CNT_MACID_8197F << BIT_SHIFT_CNT_MACID_8197F) +#define BIT_CNT_MACID_8197F(x) \ + (((x) & BIT_MASK_CNT_MACID_8197F) << BIT_SHIFT_CNT_MACID_8197F) +#define BITS_CNT_MACID_8197F \ + (BIT_MASK_CNT_MACID_8197F << BIT_SHIFT_CNT_MACID_8197F) #define BIT_CLEAR_CNT_MACID_8197F(x) ((x) & (~BITS_CNT_MACID_8197F)) -#define BIT_GET_CNT_MACID_8197F(x) (((x) >> BIT_SHIFT_CNT_MACID_8197F) & BIT_MASK_CNT_MACID_8197F) -#define BIT_SET_CNT_MACID_8197F(x, v) (BIT_CLEAR_CNT_MACID_8197F(x) | BIT_CNT_MACID_8197F(v)) - +#define BIT_GET_CNT_MACID_8197F(x) \ + (((x) >> BIT_SHIFT_CNT_MACID_8197F) & BIT_MASK_CNT_MACID_8197F) +#define BIT_SET_CNT_MACID_8197F(x, v) \ + (BIT_CLEAR_CNT_MACID_8197F(x) | BIT_CNT_MACID_8197F(v)) #define BIT_SHIFT_AGG_VALUE2_8197F 16 #define BIT_MASK_AGG_VALUE2_8197F 0x7f -#define BIT_AGG_VALUE2_8197F(x) (((x) & BIT_MASK_AGG_VALUE2_8197F) << BIT_SHIFT_AGG_VALUE2_8197F) -#define BITS_AGG_VALUE2_8197F (BIT_MASK_AGG_VALUE2_8197F << BIT_SHIFT_AGG_VALUE2_8197F) +#define BIT_AGG_VALUE2_8197F(x) \ + (((x) & BIT_MASK_AGG_VALUE2_8197F) << BIT_SHIFT_AGG_VALUE2_8197F) +#define BITS_AGG_VALUE2_8197F \ + (BIT_MASK_AGG_VALUE2_8197F << BIT_SHIFT_AGG_VALUE2_8197F) #define BIT_CLEAR_AGG_VALUE2_8197F(x) ((x) & (~BITS_AGG_VALUE2_8197F)) -#define BIT_GET_AGG_VALUE2_8197F(x) (((x) >> BIT_SHIFT_AGG_VALUE2_8197F) & BIT_MASK_AGG_VALUE2_8197F) -#define BIT_SET_AGG_VALUE2_8197F(x, v) (BIT_CLEAR_AGG_VALUE2_8197F(x) | BIT_AGG_VALUE2_8197F(v)) - +#define BIT_GET_AGG_VALUE2_8197F(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE2_8197F) & BIT_MASK_AGG_VALUE2_8197F) +#define BIT_SET_AGG_VALUE2_8197F(x, v) \ + (BIT_CLEAR_AGG_VALUE2_8197F(x) | BIT_AGG_VALUE2_8197F(v)) #define BIT_SHIFT_AGG_VALUE1_8197F 8 #define BIT_MASK_AGG_VALUE1_8197F 0x7f -#define BIT_AGG_VALUE1_8197F(x) (((x) & BIT_MASK_AGG_VALUE1_8197F) << BIT_SHIFT_AGG_VALUE1_8197F) -#define BITS_AGG_VALUE1_8197F (BIT_MASK_AGG_VALUE1_8197F << BIT_SHIFT_AGG_VALUE1_8197F) +#define BIT_AGG_VALUE1_8197F(x) \ + (((x) & BIT_MASK_AGG_VALUE1_8197F) << BIT_SHIFT_AGG_VALUE1_8197F) +#define BITS_AGG_VALUE1_8197F \ + (BIT_MASK_AGG_VALUE1_8197F << BIT_SHIFT_AGG_VALUE1_8197F) #define BIT_CLEAR_AGG_VALUE1_8197F(x) ((x) & (~BITS_AGG_VALUE1_8197F)) -#define BIT_GET_AGG_VALUE1_8197F(x) (((x) >> BIT_SHIFT_AGG_VALUE1_8197F) & BIT_MASK_AGG_VALUE1_8197F) -#define BIT_SET_AGG_VALUE1_8197F(x, v) (BIT_CLEAR_AGG_VALUE1_8197F(x) | BIT_AGG_VALUE1_8197F(v)) - +#define BIT_GET_AGG_VALUE1_8197F(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE1_8197F) & BIT_MASK_AGG_VALUE1_8197F) +#define BIT_SET_AGG_VALUE1_8197F(x, v) \ + (BIT_CLEAR_AGG_VALUE1_8197F(x) | BIT_AGG_VALUE1_8197F(v)) #define BIT_SHIFT_AGG_VALUE0_8197F 0 #define BIT_MASK_AGG_VALUE0_8197F 0x7f -#define BIT_AGG_VALUE0_8197F(x) (((x) & BIT_MASK_AGG_VALUE0_8197F) << BIT_SHIFT_AGG_VALUE0_8197F) -#define BITS_AGG_VALUE0_8197F (BIT_MASK_AGG_VALUE0_8197F << BIT_SHIFT_AGG_VALUE0_8197F) +#define BIT_AGG_VALUE0_8197F(x) \ + (((x) & BIT_MASK_AGG_VALUE0_8197F) << BIT_SHIFT_AGG_VALUE0_8197F) +#define BITS_AGG_VALUE0_8197F \ + (BIT_MASK_AGG_VALUE0_8197F << BIT_SHIFT_AGG_VALUE0_8197F) #define BIT_CLEAR_AGG_VALUE0_8197F(x) ((x) & (~BITS_AGG_VALUE0_8197F)) -#define BIT_GET_AGG_VALUE0_8197F(x) (((x) >> BIT_SHIFT_AGG_VALUE0_8197F) & BIT_MASK_AGG_VALUE0_8197F) -#define BIT_SET_AGG_VALUE0_8197F(x, v) (BIT_CLEAR_AGG_VALUE0_8197F(x) | BIT_AGG_VALUE0_8197F(v)) - +#define BIT_GET_AGG_VALUE0_8197F(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE0_8197F) & BIT_MASK_AGG_VALUE0_8197F) +#define BIT_SET_AGG_VALUE0_8197F(x, v) \ + (BIT_CLEAR_AGG_VALUE0_8197F(x) | BIT_AGG_VALUE0_8197F(v)) /* 2 REG_COUNTER_SET_8197F */ #define BIT_RTS_RST_8197F BIT(24) @@ -3748,61 +4647,89 @@ #define BIT_SHIFT_TXDMA_LEN_TH0_8197F 16 #define BIT_MASK_TXDMA_LEN_TH0_8197F 0xffff -#define BIT_TXDMA_LEN_TH0_8197F(x) (((x) & BIT_MASK_TXDMA_LEN_TH0_8197F) << BIT_SHIFT_TXDMA_LEN_TH0_8197F) -#define BITS_TXDMA_LEN_TH0_8197F (BIT_MASK_TXDMA_LEN_TH0_8197F << BIT_SHIFT_TXDMA_LEN_TH0_8197F) +#define BIT_TXDMA_LEN_TH0_8197F(x) \ + (((x) & BIT_MASK_TXDMA_LEN_TH0_8197F) << BIT_SHIFT_TXDMA_LEN_TH0_8197F) +#define BITS_TXDMA_LEN_TH0_8197F \ + (BIT_MASK_TXDMA_LEN_TH0_8197F << BIT_SHIFT_TXDMA_LEN_TH0_8197F) #define BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH0_8197F)) -#define BIT_GET_TXDMA_LEN_TH0_8197F(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH0_8197F) & BIT_MASK_TXDMA_LEN_TH0_8197F) -#define BIT_SET_TXDMA_LEN_TH0_8197F(x, v) (BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) | BIT_TXDMA_LEN_TH0_8197F(v)) - +#define BIT_GET_TXDMA_LEN_TH0_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_LEN_TH0_8197F) & BIT_MASK_TXDMA_LEN_TH0_8197F) +#define BIT_SET_TXDMA_LEN_TH0_8197F(x, v) \ + (BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) | BIT_TXDMA_LEN_TH0_8197F(v)) #define BIT_SHIFT_TXDMA_LEN_TH1_8197F 0 #define BIT_MASK_TXDMA_LEN_TH1_8197F 0xffff -#define BIT_TXDMA_LEN_TH1_8197F(x) (((x) & BIT_MASK_TXDMA_LEN_TH1_8197F) << BIT_SHIFT_TXDMA_LEN_TH1_8197F) -#define BITS_TXDMA_LEN_TH1_8197F (BIT_MASK_TXDMA_LEN_TH1_8197F << BIT_SHIFT_TXDMA_LEN_TH1_8197F) +#define BIT_TXDMA_LEN_TH1_8197F(x) \ + (((x) & BIT_MASK_TXDMA_LEN_TH1_8197F) << BIT_SHIFT_TXDMA_LEN_TH1_8197F) +#define BITS_TXDMA_LEN_TH1_8197F \ + (BIT_MASK_TXDMA_LEN_TH1_8197F << BIT_SHIFT_TXDMA_LEN_TH1_8197F) #define BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH1_8197F)) -#define BIT_GET_TXDMA_LEN_TH1_8197F(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH1_8197F) & BIT_MASK_TXDMA_LEN_TH1_8197F) -#define BIT_SET_TXDMA_LEN_TH1_8197F(x, v) (BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) | BIT_TXDMA_LEN_TH1_8197F(v)) - +#define BIT_GET_TXDMA_LEN_TH1_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_LEN_TH1_8197F) & BIT_MASK_TXDMA_LEN_TH1_8197F) +#define BIT_SET_TXDMA_LEN_TH1_8197F(x, v) \ + (BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) | BIT_TXDMA_LEN_TH1_8197F(v)) /* 2 REG_RDE_LEN_TH_8197F */ #define BIT_SHIFT_RXDMA_LEN_TH0_8197F 16 #define BIT_MASK_RXDMA_LEN_TH0_8197F 0xffff -#define BIT_RXDMA_LEN_TH0_8197F(x) (((x) & BIT_MASK_RXDMA_LEN_TH0_8197F) << BIT_SHIFT_RXDMA_LEN_TH0_8197F) -#define BITS_RXDMA_LEN_TH0_8197F (BIT_MASK_RXDMA_LEN_TH0_8197F << BIT_SHIFT_RXDMA_LEN_TH0_8197F) +#define BIT_RXDMA_LEN_TH0_8197F(x) \ + (((x) & BIT_MASK_RXDMA_LEN_TH0_8197F) << BIT_SHIFT_RXDMA_LEN_TH0_8197F) +#define BITS_RXDMA_LEN_TH0_8197F \ + (BIT_MASK_RXDMA_LEN_TH0_8197F << BIT_SHIFT_RXDMA_LEN_TH0_8197F) #define BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH0_8197F)) -#define BIT_GET_RXDMA_LEN_TH0_8197F(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH0_8197F) & BIT_MASK_RXDMA_LEN_TH0_8197F) -#define BIT_SET_RXDMA_LEN_TH0_8197F(x, v) (BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) | BIT_RXDMA_LEN_TH0_8197F(v)) - +#define BIT_GET_RXDMA_LEN_TH0_8197F(x) \ + (((x) >> BIT_SHIFT_RXDMA_LEN_TH0_8197F) & BIT_MASK_RXDMA_LEN_TH0_8197F) +#define BIT_SET_RXDMA_LEN_TH0_8197F(x, v) \ + (BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) | BIT_RXDMA_LEN_TH0_8197F(v)) #define BIT_SHIFT_RXDMA_LEN_TH1_8197F 0 #define BIT_MASK_RXDMA_LEN_TH1_8197F 0xffff -#define BIT_RXDMA_LEN_TH1_8197F(x) (((x) & BIT_MASK_RXDMA_LEN_TH1_8197F) << BIT_SHIFT_RXDMA_LEN_TH1_8197F) -#define BITS_RXDMA_LEN_TH1_8197F (BIT_MASK_RXDMA_LEN_TH1_8197F << BIT_SHIFT_RXDMA_LEN_TH1_8197F) +#define BIT_RXDMA_LEN_TH1_8197F(x) \ + (((x) & BIT_MASK_RXDMA_LEN_TH1_8197F) << BIT_SHIFT_RXDMA_LEN_TH1_8197F) +#define BITS_RXDMA_LEN_TH1_8197F \ + (BIT_MASK_RXDMA_LEN_TH1_8197F << BIT_SHIFT_RXDMA_LEN_TH1_8197F) #define BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH1_8197F)) -#define BIT_GET_RXDMA_LEN_TH1_8197F(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH1_8197F) & BIT_MASK_RXDMA_LEN_TH1_8197F) -#define BIT_SET_RXDMA_LEN_TH1_8197F(x, v) (BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) | BIT_RXDMA_LEN_TH1_8197F(v)) - +#define BIT_GET_RXDMA_LEN_TH1_8197F(x) \ + (((x) >> BIT_SHIFT_RXDMA_LEN_TH1_8197F) & BIT_MASK_RXDMA_LEN_TH1_8197F) +#define BIT_SET_RXDMA_LEN_TH1_8197F(x, v) \ + (BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) | BIT_RXDMA_LEN_TH1_8197F(v)) /* 2 REG_PCIE_EXEC_TIME_8197F */ #define BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F 16 #define BIT_MASK_COUNTER_INTERVAL_SEL_8197F 0x3 -#define BIT_COUNTER_INTERVAL_SEL_8197F(x) (((x) & BIT_MASK_COUNTER_INTERVAL_SEL_8197F) << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) -#define BITS_COUNTER_INTERVAL_SEL_8197F (BIT_MASK_COUNTER_INTERVAL_SEL_8197F << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) -#define BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) ((x) & (~BITS_COUNTER_INTERVAL_SEL_8197F)) -#define BIT_GET_COUNTER_INTERVAL_SEL_8197F(x) (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) & BIT_MASK_COUNTER_INTERVAL_SEL_8197F) -#define BIT_SET_COUNTER_INTERVAL_SEL_8197F(x, v) (BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) | BIT_COUNTER_INTERVAL_SEL_8197F(v)) - +#define BIT_COUNTER_INTERVAL_SEL_8197F(x) \ + (((x) & BIT_MASK_COUNTER_INTERVAL_SEL_8197F) \ + << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) +#define BITS_COUNTER_INTERVAL_SEL_8197F \ + (BIT_MASK_COUNTER_INTERVAL_SEL_8197F \ + << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) +#define BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) \ + ((x) & (~BITS_COUNTER_INTERVAL_SEL_8197F)) +#define BIT_GET_COUNTER_INTERVAL_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) & \ + BIT_MASK_COUNTER_INTERVAL_SEL_8197F) +#define BIT_SET_COUNTER_INTERVAL_SEL_8197F(x, v) \ + (BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) | \ + BIT_COUNTER_INTERVAL_SEL_8197F(v)) #define BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F 0 #define BIT_MASK_PCIE_TRANS_DATA_TH1_8197F 0xffff -#define BIT_PCIE_TRANS_DATA_TH1_8197F(x) (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1_8197F) << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) -#define BITS_PCIE_TRANS_DATA_TH1_8197F (BIT_MASK_PCIE_TRANS_DATA_TH1_8197F << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) -#define BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) ((x) & (~BITS_PCIE_TRANS_DATA_TH1_8197F)) -#define BIT_GET_PCIE_TRANS_DATA_TH1_8197F(x) (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) & BIT_MASK_PCIE_TRANS_DATA_TH1_8197F) -#define BIT_SET_PCIE_TRANS_DATA_TH1_8197F(x, v) (BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) | BIT_PCIE_TRANS_DATA_TH1_8197F(v)) - +#define BIT_PCIE_TRANS_DATA_TH1_8197F(x) \ + (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1_8197F) \ + << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) +#define BITS_PCIE_TRANS_DATA_TH1_8197F \ + (BIT_MASK_PCIE_TRANS_DATA_TH1_8197F \ + << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) +#define BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) \ + ((x) & (~BITS_PCIE_TRANS_DATA_TH1_8197F)) +#define BIT_GET_PCIE_TRANS_DATA_TH1_8197F(x) \ + (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) & \ + BIT_MASK_PCIE_TRANS_DATA_TH1_8197F) +#define BIT_SET_PCIE_TRANS_DATA_TH1_8197F(x, v) \ + (BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) | \ + BIT_PCIE_TRANS_DATA_TH1_8197F(v)) /* 2 REG_FT2IMR_8197F */ #define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(31) @@ -3864,45 +4791,53 @@ #define BIT_SHIFT_FW_MSG2_8197F 0 #define BIT_MASK_FW_MSG2_8197F 0xffffffffL -#define BIT_FW_MSG2_8197F(x) (((x) & BIT_MASK_FW_MSG2_8197F) << BIT_SHIFT_FW_MSG2_8197F) +#define BIT_FW_MSG2_8197F(x) \ + (((x) & BIT_MASK_FW_MSG2_8197F) << BIT_SHIFT_FW_MSG2_8197F) #define BITS_FW_MSG2_8197F (BIT_MASK_FW_MSG2_8197F << BIT_SHIFT_FW_MSG2_8197F) #define BIT_CLEAR_FW_MSG2_8197F(x) ((x) & (~BITS_FW_MSG2_8197F)) -#define BIT_GET_FW_MSG2_8197F(x) (((x) >> BIT_SHIFT_FW_MSG2_8197F) & BIT_MASK_FW_MSG2_8197F) -#define BIT_SET_FW_MSG2_8197F(x, v) (BIT_CLEAR_FW_MSG2_8197F(x) | BIT_FW_MSG2_8197F(v)) - +#define BIT_GET_FW_MSG2_8197F(x) \ + (((x) >> BIT_SHIFT_FW_MSG2_8197F) & BIT_MASK_FW_MSG2_8197F) +#define BIT_SET_FW_MSG2_8197F(x, v) \ + (BIT_CLEAR_FW_MSG2_8197F(x) | BIT_FW_MSG2_8197F(v)) /* 2 REG_MSG3_8197F */ #define BIT_SHIFT_FW_MSG3_8197F 0 #define BIT_MASK_FW_MSG3_8197F 0xffffffffL -#define BIT_FW_MSG3_8197F(x) (((x) & BIT_MASK_FW_MSG3_8197F) << BIT_SHIFT_FW_MSG3_8197F) +#define BIT_FW_MSG3_8197F(x) \ + (((x) & BIT_MASK_FW_MSG3_8197F) << BIT_SHIFT_FW_MSG3_8197F) #define BITS_FW_MSG3_8197F (BIT_MASK_FW_MSG3_8197F << BIT_SHIFT_FW_MSG3_8197F) #define BIT_CLEAR_FW_MSG3_8197F(x) ((x) & (~BITS_FW_MSG3_8197F)) -#define BIT_GET_FW_MSG3_8197F(x) (((x) >> BIT_SHIFT_FW_MSG3_8197F) & BIT_MASK_FW_MSG3_8197F) -#define BIT_SET_FW_MSG3_8197F(x, v) (BIT_CLEAR_FW_MSG3_8197F(x) | BIT_FW_MSG3_8197F(v)) - +#define BIT_GET_FW_MSG3_8197F(x) \ + (((x) >> BIT_SHIFT_FW_MSG3_8197F) & BIT_MASK_FW_MSG3_8197F) +#define BIT_SET_FW_MSG3_8197F(x, v) \ + (BIT_CLEAR_FW_MSG3_8197F(x) | BIT_FW_MSG3_8197F(v)) /* 2 REG_MSG4_8197F */ #define BIT_SHIFT_FW_MSG4_8197F 0 #define BIT_MASK_FW_MSG4_8197F 0xffffffffL -#define BIT_FW_MSG4_8197F(x) (((x) & BIT_MASK_FW_MSG4_8197F) << BIT_SHIFT_FW_MSG4_8197F) +#define BIT_FW_MSG4_8197F(x) \ + (((x) & BIT_MASK_FW_MSG4_8197F) << BIT_SHIFT_FW_MSG4_8197F) #define BITS_FW_MSG4_8197F (BIT_MASK_FW_MSG4_8197F << BIT_SHIFT_FW_MSG4_8197F) #define BIT_CLEAR_FW_MSG4_8197F(x) ((x) & (~BITS_FW_MSG4_8197F)) -#define BIT_GET_FW_MSG4_8197F(x) (((x) >> BIT_SHIFT_FW_MSG4_8197F) & BIT_MASK_FW_MSG4_8197F) -#define BIT_SET_FW_MSG4_8197F(x, v) (BIT_CLEAR_FW_MSG4_8197F(x) | BIT_FW_MSG4_8197F(v)) - +#define BIT_GET_FW_MSG4_8197F(x) \ + (((x) >> BIT_SHIFT_FW_MSG4_8197F) & BIT_MASK_FW_MSG4_8197F) +#define BIT_SET_FW_MSG4_8197F(x, v) \ + (BIT_CLEAR_FW_MSG4_8197F(x) | BIT_FW_MSG4_8197F(v)) /* 2 REG_MSG5_8197F */ #define BIT_SHIFT_FW_MSG5_8197F 0 #define BIT_MASK_FW_MSG5_8197F 0xffffffffL -#define BIT_FW_MSG5_8197F(x) (((x) & BIT_MASK_FW_MSG5_8197F) << BIT_SHIFT_FW_MSG5_8197F) +#define BIT_FW_MSG5_8197F(x) \ + (((x) & BIT_MASK_FW_MSG5_8197F) << BIT_SHIFT_FW_MSG5_8197F) #define BITS_FW_MSG5_8197F (BIT_MASK_FW_MSG5_8197F << BIT_SHIFT_FW_MSG5_8197F) #define BIT_CLEAR_FW_MSG5_8197F(x) ((x) & (~BITS_FW_MSG5_8197F)) -#define BIT_GET_FW_MSG5_8197F(x) (((x) >> BIT_SHIFT_FW_MSG5_8197F) & BIT_MASK_FW_MSG5_8197F) -#define BIT_SET_FW_MSG5_8197F(x, v) (BIT_CLEAR_FW_MSG5_8197F(x) | BIT_FW_MSG5_8197F(v)) - +#define BIT_GET_FW_MSG5_8197F(x) \ + (((x) >> BIT_SHIFT_FW_MSG5_8197F) & BIT_MASK_FW_MSG5_8197F) +#define BIT_SET_FW_MSG5_8197F(x, v) \ + (BIT_CLEAR_FW_MSG5_8197F(x) | BIT_FW_MSG5_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -3910,71 +4845,112 @@ #define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F 16 #define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F 0xff -#define BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) -#define BITS_TX_OQT_HE_FREE_SPACE_V1_8197F (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) -#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8197F)) -#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8197F(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F) -#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8197F(x, v) (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) | BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(v)) - +#define BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) +#define BITS_TX_OQT_HE_FREE_SPACE_V1_8197F \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) \ + ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8197F)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F) +#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8197F(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) | \ + BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(v)) #define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F 0 #define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F 0xff -#define BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) -#define BITS_TX_OQT_NL_FREE_SPACE_V1_8197F (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) -#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8197F)) -#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8197F(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F) -#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8197F(x, v) (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) | BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(v)) - +#define BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) +#define BITS_TX_OQT_NL_FREE_SPACE_V1_8197F \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) \ + ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8197F)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F) +#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8197F(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) | \ + BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(v)) /* 2 REG_FIFOPAGE_CTRL_2_8197F */ #define BIT_BCN_VALID_1_V1_8197F BIT(31) #define BIT_SHIFT_BCN_HEAD_1_V1_8197F 16 #define BIT_MASK_BCN_HEAD_1_V1_8197F 0xfff -#define BIT_BCN_HEAD_1_V1_8197F(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8197F) << BIT_SHIFT_BCN_HEAD_1_V1_8197F) -#define BITS_BCN_HEAD_1_V1_8197F (BIT_MASK_BCN_HEAD_1_V1_8197F << BIT_SHIFT_BCN_HEAD_1_V1_8197F) +#define BIT_BCN_HEAD_1_V1_8197F(x) \ + (((x) & BIT_MASK_BCN_HEAD_1_V1_8197F) << BIT_SHIFT_BCN_HEAD_1_V1_8197F) +#define BITS_BCN_HEAD_1_V1_8197F \ + (BIT_MASK_BCN_HEAD_1_V1_8197F << BIT_SHIFT_BCN_HEAD_1_V1_8197F) #define BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_1_V1_8197F)) -#define BIT_GET_BCN_HEAD_1_V1_8197F(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8197F) & BIT_MASK_BCN_HEAD_1_V1_8197F) -#define BIT_SET_BCN_HEAD_1_V1_8197F(x, v) (BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) | BIT_BCN_HEAD_1_V1_8197F(v)) +#define BIT_GET_BCN_HEAD_1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8197F) & BIT_MASK_BCN_HEAD_1_V1_8197F) +#define BIT_SET_BCN_HEAD_1_V1_8197F(x, v) \ + (BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) | BIT_BCN_HEAD_1_V1_8197F(v)) #define BIT_BCN_VALID_V1_8197F BIT(15) #define BIT_SHIFT_BCN_HEAD_V1_8197F 0 #define BIT_MASK_BCN_HEAD_V1_8197F 0xfff -#define BIT_BCN_HEAD_V1_8197F(x) (((x) & BIT_MASK_BCN_HEAD_V1_8197F) << BIT_SHIFT_BCN_HEAD_V1_8197F) -#define BITS_BCN_HEAD_V1_8197F (BIT_MASK_BCN_HEAD_V1_8197F << BIT_SHIFT_BCN_HEAD_V1_8197F) +#define BIT_BCN_HEAD_V1_8197F(x) \ + (((x) & BIT_MASK_BCN_HEAD_V1_8197F) << BIT_SHIFT_BCN_HEAD_V1_8197F) +#define BITS_BCN_HEAD_V1_8197F \ + (BIT_MASK_BCN_HEAD_V1_8197F << BIT_SHIFT_BCN_HEAD_V1_8197F) #define BIT_CLEAR_BCN_HEAD_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_V1_8197F)) -#define BIT_GET_BCN_HEAD_V1_8197F(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8197F) & BIT_MASK_BCN_HEAD_V1_8197F) -#define BIT_SET_BCN_HEAD_V1_8197F(x, v) (BIT_CLEAR_BCN_HEAD_V1_8197F(x) | BIT_BCN_HEAD_V1_8197F(v)) - +#define BIT_GET_BCN_HEAD_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_V1_8197F) & BIT_MASK_BCN_HEAD_V1_8197F) +#define BIT_SET_BCN_HEAD_V1_8197F(x, v) \ + (BIT_CLEAR_BCN_HEAD_V1_8197F(x) | BIT_BCN_HEAD_V1_8197F(v)) /* 2 REG_AUTO_LLT_V1_8197F */ #define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 24 #define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) -#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) -#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) -#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x, v) (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) | BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(v)) - +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) +#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F \ + (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) +#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) \ + ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) & \ + BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) +#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) | \ + BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(v)) #define BIT_SHIFT_LLT_FREE_PAGE_V1_8197F 8 #define BIT_MASK_LLT_FREE_PAGE_V1_8197F 0xffff -#define BIT_LLT_FREE_PAGE_V1_8197F(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8197F) << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) -#define BITS_LLT_FREE_PAGE_V1_8197F (BIT_MASK_LLT_FREE_PAGE_V1_8197F << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) -#define BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) ((x) & (~BITS_LLT_FREE_PAGE_V1_8197F)) -#define BIT_GET_LLT_FREE_PAGE_V1_8197F(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) & BIT_MASK_LLT_FREE_PAGE_V1_8197F) -#define BIT_SET_LLT_FREE_PAGE_V1_8197F(x, v) (BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) | BIT_LLT_FREE_PAGE_V1_8197F(v)) - +#define BIT_LLT_FREE_PAGE_V1_8197F(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8197F) \ + << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) +#define BITS_LLT_FREE_PAGE_V1_8197F \ + (BIT_MASK_LLT_FREE_PAGE_V1_8197F << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) +#define BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) \ + ((x) & (~BITS_LLT_FREE_PAGE_V1_8197F)) +#define BIT_GET_LLT_FREE_PAGE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) & \ + BIT_MASK_LLT_FREE_PAGE_V1_8197F) +#define BIT_SET_LLT_FREE_PAGE_V1_8197F(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) | BIT_LLT_FREE_PAGE_V1_8197F(v)) #define BIT_SHIFT_BLK_DESC_NUM_8197F 4 #define BIT_MASK_BLK_DESC_NUM_8197F 0xf -#define BIT_BLK_DESC_NUM_8197F(x) (((x) & BIT_MASK_BLK_DESC_NUM_8197F) << BIT_SHIFT_BLK_DESC_NUM_8197F) -#define BITS_BLK_DESC_NUM_8197F (BIT_MASK_BLK_DESC_NUM_8197F << BIT_SHIFT_BLK_DESC_NUM_8197F) +#define BIT_BLK_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM_8197F) << BIT_SHIFT_BLK_DESC_NUM_8197F) +#define BITS_BLK_DESC_NUM_8197F \ + (BIT_MASK_BLK_DESC_NUM_8197F << BIT_SHIFT_BLK_DESC_NUM_8197F) #define BIT_CLEAR_BLK_DESC_NUM_8197F(x) ((x) & (~BITS_BLK_DESC_NUM_8197F)) -#define BIT_GET_BLK_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8197F) & BIT_MASK_BLK_DESC_NUM_8197F) -#define BIT_SET_BLK_DESC_NUM_8197F(x, v) (BIT_CLEAR_BLK_DESC_NUM_8197F(x) | BIT_BLK_DESC_NUM_8197F(v)) +#define BIT_GET_BLK_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM_8197F) & BIT_MASK_BLK_DESC_NUM_8197F) +#define BIT_SET_BLK_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM_8197F(x) | BIT_BLK_DESC_NUM_8197F(v)) #define BIT_R_BCN_HEAD_SEL_8197F BIT(3) #define BIT_R_EN_BCN_SW_HEAD_SEL_8197F BIT(2) @@ -3989,11 +4965,17 @@ #define BIT_SHIFT_PG_UNDER_TH_V1_8197F 16 #define BIT_MASK_PG_UNDER_TH_V1_8197F 0xfff -#define BIT_PG_UNDER_TH_V1_8197F(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8197F) << BIT_SHIFT_PG_UNDER_TH_V1_8197F) -#define BITS_PG_UNDER_TH_V1_8197F (BIT_MASK_PG_UNDER_TH_V1_8197F << BIT_SHIFT_PG_UNDER_TH_V1_8197F) +#define BIT_PG_UNDER_TH_V1_8197F(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1_8197F) \ + << BIT_SHIFT_PG_UNDER_TH_V1_8197F) +#define BITS_PG_UNDER_TH_V1_8197F \ + (BIT_MASK_PG_UNDER_TH_V1_8197F << BIT_SHIFT_PG_UNDER_TH_V1_8197F) #define BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) ((x) & (~BITS_PG_UNDER_TH_V1_8197F)) -#define BIT_GET_PG_UNDER_TH_V1_8197F(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8197F) & BIT_MASK_PG_UNDER_TH_V1_8197F) -#define BIT_SET_PG_UNDER_TH_V1_8197F(x, v) (BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) | BIT_PG_UNDER_TH_V1_8197F(v)) +#define BIT_GET_PG_UNDER_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8197F) & \ + BIT_MASK_PG_UNDER_TH_V1_8197F) +#define BIT_SET_PG_UNDER_TH_V1_8197F(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) | BIT_PG_UNDER_TH_V1_8197F(v)) #define BIT_EN_RESET_RESTORE_H2C_8197F BIT(15) #define BIT_SDIO_TDE_FINISH_8197F BIT(14) @@ -4006,12 +4988,15 @@ #define BIT_SHIFT_CHECK_OFFSET_8197F 0 #define BIT_MASK_CHECK_OFFSET_8197F 0xff -#define BIT_CHECK_OFFSET_8197F(x) (((x) & BIT_MASK_CHECK_OFFSET_8197F) << BIT_SHIFT_CHECK_OFFSET_8197F) -#define BITS_CHECK_OFFSET_8197F (BIT_MASK_CHECK_OFFSET_8197F << BIT_SHIFT_CHECK_OFFSET_8197F) +#define BIT_CHECK_OFFSET_8197F(x) \ + (((x) & BIT_MASK_CHECK_OFFSET_8197F) << BIT_SHIFT_CHECK_OFFSET_8197F) +#define BITS_CHECK_OFFSET_8197F \ + (BIT_MASK_CHECK_OFFSET_8197F << BIT_SHIFT_CHECK_OFFSET_8197F) #define BIT_CLEAR_CHECK_OFFSET_8197F(x) ((x) & (~BITS_CHECK_OFFSET_8197F)) -#define BIT_GET_CHECK_OFFSET_8197F(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8197F) & BIT_MASK_CHECK_OFFSET_8197F) -#define BIT_SET_CHECK_OFFSET_8197F(x, v) (BIT_CLEAR_CHECK_OFFSET_8197F(x) | BIT_CHECK_OFFSET_8197F(v)) - +#define BIT_GET_CHECK_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET_8197F) & BIT_MASK_CHECK_OFFSET_8197F) +#define BIT_SET_CHECK_OFFSET_8197F(x, v) \ + (BIT_CLEAR_CHECK_OFFSET_8197F(x) | BIT_CHECK_OFFSET_8197F(v)) /* 2 REG_TXDMA_STATUS_8197F */ #define BIT_HI_OQT_UDN_8197F BIT(17) @@ -4039,101 +5024,139 @@ #define BIT_SHIFT_HPQ_HIGH_TH_V1_8197F 16 #define BIT_MASK_HPQ_HIGH_TH_V1_8197F 0xfff -#define BIT_HPQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8197F) << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) -#define BITS_HPQ_HIGH_TH_V1_8197F (BIT_MASK_HPQ_HIGH_TH_V1_8197F << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) +#define BIT_HPQ_HIGH_TH_V1_8197F(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8197F) \ + << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) +#define BITS_HPQ_HIGH_TH_V1_8197F \ + (BIT_MASK_HPQ_HIGH_TH_V1_8197F << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) #define BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8197F)) -#define BIT_GET_HPQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) & BIT_MASK_HPQ_HIGH_TH_V1_8197F) -#define BIT_SET_HPQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) | BIT_HPQ_HIGH_TH_V1_8197F(v)) - +#define BIT_GET_HPQ_HIGH_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) & \ + BIT_MASK_HPQ_HIGH_TH_V1_8197F) +#define BIT_SET_HPQ_HIGH_TH_V1_8197F(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) | BIT_HPQ_HIGH_TH_V1_8197F(v)) #define BIT_SHIFT_HPQ_LOW_TH_V1_8197F 0 #define BIT_MASK_HPQ_LOW_TH_V1_8197F 0xfff -#define BIT_HPQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8197F) << BIT_SHIFT_HPQ_LOW_TH_V1_8197F) -#define BITS_HPQ_LOW_TH_V1_8197F (BIT_MASK_HPQ_LOW_TH_V1_8197F << BIT_SHIFT_HPQ_LOW_TH_V1_8197F) +#define BIT_HPQ_LOW_TH_V1_8197F(x) \ + (((x) & BIT_MASK_HPQ_LOW_TH_V1_8197F) << BIT_SHIFT_HPQ_LOW_TH_V1_8197F) +#define BITS_HPQ_LOW_TH_V1_8197F \ + (BIT_MASK_HPQ_LOW_TH_V1_8197F << BIT_SHIFT_HPQ_LOW_TH_V1_8197F) #define BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8197F)) -#define BIT_GET_HPQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8197F) & BIT_MASK_HPQ_LOW_TH_V1_8197F) -#define BIT_SET_HPQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) | BIT_HPQ_LOW_TH_V1_8197F(v)) - +#define BIT_GET_HPQ_LOW_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8197F) & BIT_MASK_HPQ_LOW_TH_V1_8197F) +#define BIT_SET_HPQ_LOW_TH_V1_8197F(x, v) \ + (BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) | BIT_HPQ_LOW_TH_V1_8197F(v)) /* 2 REG_TQPNT2_8197F */ #define BIT_SHIFT_NPQ_HIGH_TH_V1_8197F 16 #define BIT_MASK_NPQ_HIGH_TH_V1_8197F 0xfff -#define BIT_NPQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8197F) << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) -#define BITS_NPQ_HIGH_TH_V1_8197F (BIT_MASK_NPQ_HIGH_TH_V1_8197F << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) +#define BIT_NPQ_HIGH_TH_V1_8197F(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8197F) \ + << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) +#define BITS_NPQ_HIGH_TH_V1_8197F \ + (BIT_MASK_NPQ_HIGH_TH_V1_8197F << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) #define BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8197F)) -#define BIT_GET_NPQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) & BIT_MASK_NPQ_HIGH_TH_V1_8197F) -#define BIT_SET_NPQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) | BIT_NPQ_HIGH_TH_V1_8197F(v)) - +#define BIT_GET_NPQ_HIGH_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) & \ + BIT_MASK_NPQ_HIGH_TH_V1_8197F) +#define BIT_SET_NPQ_HIGH_TH_V1_8197F(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) | BIT_NPQ_HIGH_TH_V1_8197F(v)) #define BIT_SHIFT_NPQ_LOW_TH_V1_8197F 0 #define BIT_MASK_NPQ_LOW_TH_V1_8197F 0xfff -#define BIT_NPQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8197F) << BIT_SHIFT_NPQ_LOW_TH_V1_8197F) -#define BITS_NPQ_LOW_TH_V1_8197F (BIT_MASK_NPQ_LOW_TH_V1_8197F << BIT_SHIFT_NPQ_LOW_TH_V1_8197F) +#define BIT_NPQ_LOW_TH_V1_8197F(x) \ + (((x) & BIT_MASK_NPQ_LOW_TH_V1_8197F) << BIT_SHIFT_NPQ_LOW_TH_V1_8197F) +#define BITS_NPQ_LOW_TH_V1_8197F \ + (BIT_MASK_NPQ_LOW_TH_V1_8197F << BIT_SHIFT_NPQ_LOW_TH_V1_8197F) #define BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8197F)) -#define BIT_GET_NPQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8197F) & BIT_MASK_NPQ_LOW_TH_V1_8197F) -#define BIT_SET_NPQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) | BIT_NPQ_LOW_TH_V1_8197F(v)) - +#define BIT_GET_NPQ_LOW_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8197F) & BIT_MASK_NPQ_LOW_TH_V1_8197F) +#define BIT_SET_NPQ_LOW_TH_V1_8197F(x, v) \ + (BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) | BIT_NPQ_LOW_TH_V1_8197F(v)) /* 2 REG_TQPNT3_8197F */ #define BIT_SHIFT_LPQ_HIGH_TH_V1_8197F 16 #define BIT_MASK_LPQ_HIGH_TH_V1_8197F 0xfff -#define BIT_LPQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8197F) << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) -#define BITS_LPQ_HIGH_TH_V1_8197F (BIT_MASK_LPQ_HIGH_TH_V1_8197F << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) +#define BIT_LPQ_HIGH_TH_V1_8197F(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8197F) \ + << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) +#define BITS_LPQ_HIGH_TH_V1_8197F \ + (BIT_MASK_LPQ_HIGH_TH_V1_8197F << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) #define BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8197F)) -#define BIT_GET_LPQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) & BIT_MASK_LPQ_HIGH_TH_V1_8197F) -#define BIT_SET_LPQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) | BIT_LPQ_HIGH_TH_V1_8197F(v)) - +#define BIT_GET_LPQ_HIGH_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) & \ + BIT_MASK_LPQ_HIGH_TH_V1_8197F) +#define BIT_SET_LPQ_HIGH_TH_V1_8197F(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) | BIT_LPQ_HIGH_TH_V1_8197F(v)) #define BIT_SHIFT_LPQ_LOW_TH_V1_8197F 0 #define BIT_MASK_LPQ_LOW_TH_V1_8197F 0xfff -#define BIT_LPQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8197F) << BIT_SHIFT_LPQ_LOW_TH_V1_8197F) -#define BITS_LPQ_LOW_TH_V1_8197F (BIT_MASK_LPQ_LOW_TH_V1_8197F << BIT_SHIFT_LPQ_LOW_TH_V1_8197F) +#define BIT_LPQ_LOW_TH_V1_8197F(x) \ + (((x) & BIT_MASK_LPQ_LOW_TH_V1_8197F) << BIT_SHIFT_LPQ_LOW_TH_V1_8197F) +#define BITS_LPQ_LOW_TH_V1_8197F \ + (BIT_MASK_LPQ_LOW_TH_V1_8197F << BIT_SHIFT_LPQ_LOW_TH_V1_8197F) #define BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8197F)) -#define BIT_GET_LPQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8197F) & BIT_MASK_LPQ_LOW_TH_V1_8197F) -#define BIT_SET_LPQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) | BIT_LPQ_LOW_TH_V1_8197F(v)) - +#define BIT_GET_LPQ_LOW_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8197F) & BIT_MASK_LPQ_LOW_TH_V1_8197F) +#define BIT_SET_LPQ_LOW_TH_V1_8197F(x, v) \ + (BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) | BIT_LPQ_LOW_TH_V1_8197F(v)) /* 2 REG_TQPNT4_8197F */ #define BIT_SHIFT_EXQ_HIGH_TH_V1_8197F 16 #define BIT_MASK_EXQ_HIGH_TH_V1_8197F 0xfff -#define BIT_EXQ_HIGH_TH_V1_8197F(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8197F) << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) -#define BITS_EXQ_HIGH_TH_V1_8197F (BIT_MASK_EXQ_HIGH_TH_V1_8197F << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) +#define BIT_EXQ_HIGH_TH_V1_8197F(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8197F) \ + << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) +#define BITS_EXQ_HIGH_TH_V1_8197F \ + (BIT_MASK_EXQ_HIGH_TH_V1_8197F << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) #define BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8197F)) -#define BIT_GET_EXQ_HIGH_TH_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) & BIT_MASK_EXQ_HIGH_TH_V1_8197F) -#define BIT_SET_EXQ_HIGH_TH_V1_8197F(x, v) (BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) | BIT_EXQ_HIGH_TH_V1_8197F(v)) - +#define BIT_GET_EXQ_HIGH_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) & \ + BIT_MASK_EXQ_HIGH_TH_V1_8197F) +#define BIT_SET_EXQ_HIGH_TH_V1_8197F(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) | BIT_EXQ_HIGH_TH_V1_8197F(v)) #define BIT_SHIFT_EXQ_LOW_TH_V1_8197F 0 #define BIT_MASK_EXQ_LOW_TH_V1_8197F 0xfff -#define BIT_EXQ_LOW_TH_V1_8197F(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8197F) << BIT_SHIFT_EXQ_LOW_TH_V1_8197F) -#define BITS_EXQ_LOW_TH_V1_8197F (BIT_MASK_EXQ_LOW_TH_V1_8197F << BIT_SHIFT_EXQ_LOW_TH_V1_8197F) +#define BIT_EXQ_LOW_TH_V1_8197F(x) \ + (((x) & BIT_MASK_EXQ_LOW_TH_V1_8197F) << BIT_SHIFT_EXQ_LOW_TH_V1_8197F) +#define BITS_EXQ_LOW_TH_V1_8197F \ + (BIT_MASK_EXQ_LOW_TH_V1_8197F << BIT_SHIFT_EXQ_LOW_TH_V1_8197F) #define BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8197F)) -#define BIT_GET_EXQ_LOW_TH_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8197F) & BIT_MASK_EXQ_LOW_TH_V1_8197F) -#define BIT_SET_EXQ_LOW_TH_V1_8197F(x, v) (BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) | BIT_EXQ_LOW_TH_V1_8197F(v)) - +#define BIT_GET_EXQ_LOW_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8197F) & BIT_MASK_EXQ_LOW_TH_V1_8197F) +#define BIT_SET_EXQ_LOW_TH_V1_8197F(x, v) \ + (BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) | BIT_EXQ_LOW_TH_V1_8197F(v)) /* 2 REG_RQPN_CTRL_1_8197F */ #define BIT_SHIFT_TXPKTNUM_H_8197F 16 #define BIT_MASK_TXPKTNUM_H_8197F 0xffff -#define BIT_TXPKTNUM_H_8197F(x) (((x) & BIT_MASK_TXPKTNUM_H_8197F) << BIT_SHIFT_TXPKTNUM_H_8197F) -#define BITS_TXPKTNUM_H_8197F (BIT_MASK_TXPKTNUM_H_8197F << BIT_SHIFT_TXPKTNUM_H_8197F) +#define BIT_TXPKTNUM_H_8197F(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_8197F) << BIT_SHIFT_TXPKTNUM_H_8197F) +#define BITS_TXPKTNUM_H_8197F \ + (BIT_MASK_TXPKTNUM_H_8197F << BIT_SHIFT_TXPKTNUM_H_8197F) #define BIT_CLEAR_TXPKTNUM_H_8197F(x) ((x) & (~BITS_TXPKTNUM_H_8197F)) -#define BIT_GET_TXPKTNUM_H_8197F(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8197F) & BIT_MASK_TXPKTNUM_H_8197F) -#define BIT_SET_TXPKTNUM_H_8197F(x, v) (BIT_CLEAR_TXPKTNUM_H_8197F(x) | BIT_TXPKTNUM_H_8197F(v)) - +#define BIT_GET_TXPKTNUM_H_8197F(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_8197F) & BIT_MASK_TXPKTNUM_H_8197F) +#define BIT_SET_TXPKTNUM_H_8197F(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_8197F(x) | BIT_TXPKTNUM_H_8197F(v)) #define BIT_SHIFT_TXPKTNUM_H_V1_8197F 0 #define BIT_MASK_TXPKTNUM_H_V1_8197F 0xffff -#define BIT_TXPKTNUM_H_V1_8197F(x) (((x) & BIT_MASK_TXPKTNUM_H_V1_8197F) << BIT_SHIFT_TXPKTNUM_H_V1_8197F) -#define BITS_TXPKTNUM_H_V1_8197F (BIT_MASK_TXPKTNUM_H_V1_8197F << BIT_SHIFT_TXPKTNUM_H_V1_8197F) +#define BIT_TXPKTNUM_H_V1_8197F(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_V1_8197F) << BIT_SHIFT_TXPKTNUM_H_V1_8197F) +#define BITS_TXPKTNUM_H_V1_8197F \ + (BIT_MASK_TXPKTNUM_H_V1_8197F << BIT_SHIFT_TXPKTNUM_H_V1_8197F) #define BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) ((x) & (~BITS_TXPKTNUM_H_V1_8197F)) -#define BIT_GET_TXPKTNUM_H_V1_8197F(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_V1_8197F) & BIT_MASK_TXPKTNUM_H_V1_8197F) -#define BIT_SET_TXPKTNUM_H_V1_8197F(x, v) (BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) | BIT_TXPKTNUM_H_V1_8197F(v)) - +#define BIT_GET_TXPKTNUM_H_V1_8197F(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_V1_8197F) & BIT_MASK_TXPKTNUM_H_V1_8197F) +#define BIT_SET_TXPKTNUM_H_V1_8197F(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) | BIT_TXPKTNUM_H_V1_8197F(v)) /* 2 REG_RQPN_CTRL_2_8197F */ #define BIT_LD_RQPN_8197F BIT(31) @@ -4146,145 +5169,192 @@ #define BIT_SHIFT_HPQ_AVAL_PG_V1_8197F 16 #define BIT_MASK_HPQ_AVAL_PG_V1_8197F 0xfff -#define BIT_HPQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8197F) << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) -#define BITS_HPQ_AVAL_PG_V1_8197F (BIT_MASK_HPQ_AVAL_PG_V1_8197F << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) +#define BIT_HPQ_AVAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8197F) \ + << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) +#define BITS_HPQ_AVAL_PG_V1_8197F \ + (BIT_MASK_HPQ_AVAL_PG_V1_8197F << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) #define BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8197F)) -#define BIT_GET_HPQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) & BIT_MASK_HPQ_AVAL_PG_V1_8197F) -#define BIT_SET_HPQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) | BIT_HPQ_AVAL_PG_V1_8197F(v)) - +#define BIT_GET_HPQ_AVAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) & \ + BIT_MASK_HPQ_AVAL_PG_V1_8197F) +#define BIT_SET_HPQ_AVAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) | BIT_HPQ_AVAL_PG_V1_8197F(v)) #define BIT_SHIFT_HPQ_V1_8197F 0 #define BIT_MASK_HPQ_V1_8197F 0xfff -#define BIT_HPQ_V1_8197F(x) (((x) & BIT_MASK_HPQ_V1_8197F) << BIT_SHIFT_HPQ_V1_8197F) +#define BIT_HPQ_V1_8197F(x) \ + (((x) & BIT_MASK_HPQ_V1_8197F) << BIT_SHIFT_HPQ_V1_8197F) #define BITS_HPQ_V1_8197F (BIT_MASK_HPQ_V1_8197F << BIT_SHIFT_HPQ_V1_8197F) #define BIT_CLEAR_HPQ_V1_8197F(x) ((x) & (~BITS_HPQ_V1_8197F)) -#define BIT_GET_HPQ_V1_8197F(x) (((x) >> BIT_SHIFT_HPQ_V1_8197F) & BIT_MASK_HPQ_V1_8197F) -#define BIT_SET_HPQ_V1_8197F(x, v) (BIT_CLEAR_HPQ_V1_8197F(x) | BIT_HPQ_V1_8197F(v)) - +#define BIT_GET_HPQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HPQ_V1_8197F) & BIT_MASK_HPQ_V1_8197F) +#define BIT_SET_HPQ_V1_8197F(x, v) \ + (BIT_CLEAR_HPQ_V1_8197F(x) | BIT_HPQ_V1_8197F(v)) /* 2 REG_FIFOPAGE_INFO_2_8197F */ #define BIT_SHIFT_LPQ_AVAL_PG_V1_8197F 16 #define BIT_MASK_LPQ_AVAL_PG_V1_8197F 0xfff -#define BIT_LPQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8197F) << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) -#define BITS_LPQ_AVAL_PG_V1_8197F (BIT_MASK_LPQ_AVAL_PG_V1_8197F << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) +#define BIT_LPQ_AVAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8197F) \ + << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) +#define BITS_LPQ_AVAL_PG_V1_8197F \ + (BIT_MASK_LPQ_AVAL_PG_V1_8197F << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) #define BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8197F)) -#define BIT_GET_LPQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) & BIT_MASK_LPQ_AVAL_PG_V1_8197F) -#define BIT_SET_LPQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) | BIT_LPQ_AVAL_PG_V1_8197F(v)) - +#define BIT_GET_LPQ_AVAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) & \ + BIT_MASK_LPQ_AVAL_PG_V1_8197F) +#define BIT_SET_LPQ_AVAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) | BIT_LPQ_AVAL_PG_V1_8197F(v)) #define BIT_SHIFT_LPQ_V1_8197F 0 #define BIT_MASK_LPQ_V1_8197F 0xfff -#define BIT_LPQ_V1_8197F(x) (((x) & BIT_MASK_LPQ_V1_8197F) << BIT_SHIFT_LPQ_V1_8197F) +#define BIT_LPQ_V1_8197F(x) \ + (((x) & BIT_MASK_LPQ_V1_8197F) << BIT_SHIFT_LPQ_V1_8197F) #define BITS_LPQ_V1_8197F (BIT_MASK_LPQ_V1_8197F << BIT_SHIFT_LPQ_V1_8197F) #define BIT_CLEAR_LPQ_V1_8197F(x) ((x) & (~BITS_LPQ_V1_8197F)) -#define BIT_GET_LPQ_V1_8197F(x) (((x) >> BIT_SHIFT_LPQ_V1_8197F) & BIT_MASK_LPQ_V1_8197F) -#define BIT_SET_LPQ_V1_8197F(x, v) (BIT_CLEAR_LPQ_V1_8197F(x) | BIT_LPQ_V1_8197F(v)) - +#define BIT_GET_LPQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_LPQ_V1_8197F) & BIT_MASK_LPQ_V1_8197F) +#define BIT_SET_LPQ_V1_8197F(x, v) \ + (BIT_CLEAR_LPQ_V1_8197F(x) | BIT_LPQ_V1_8197F(v)) /* 2 REG_FIFOPAGE_INFO_3_8197F */ -#define BIT_SHIFT_NPQ_AVAL_PG_8197F 8 -#define BIT_MASK_NPQ_AVAL_PG_8197F 0xff -#define BIT_NPQ_AVAL_PG_8197F(x) (((x) & BIT_MASK_NPQ_AVAL_PG_8197F) << BIT_SHIFT_NPQ_AVAL_PG_8197F) -#define BITS_NPQ_AVAL_PG_8197F (BIT_MASK_NPQ_AVAL_PG_8197F << BIT_SHIFT_NPQ_AVAL_PG_8197F) -#define BIT_CLEAR_NPQ_AVAL_PG_8197F(x) ((x) & (~BITS_NPQ_AVAL_PG_8197F)) -#define BIT_GET_NPQ_AVAL_PG_8197F(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_8197F) & BIT_MASK_NPQ_AVAL_PG_8197F) -#define BIT_SET_NPQ_AVAL_PG_8197F(x, v) (BIT_CLEAR_NPQ_AVAL_PG_8197F(x) | BIT_NPQ_AVAL_PG_8197F(v)) - +#define BIT_SHIFT_NPQ_AVAL_PG_V1_8197F 16 +#define BIT_MASK_NPQ_AVAL_PG_V1_8197F 0xfff +#define BIT_NPQ_AVAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8197F) \ + << BIT_SHIFT_NPQ_AVAL_PG_V1_8197F) +#define BITS_NPQ_AVAL_PG_V1_8197F \ + (BIT_MASK_NPQ_AVAL_PG_V1_8197F << BIT_SHIFT_NPQ_AVAL_PG_V1_8197F) +#define BIT_CLEAR_NPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8197F)) +#define BIT_GET_NPQ_AVAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8197F) & \ + BIT_MASK_NPQ_AVAL_PG_V1_8197F) +#define BIT_SET_NPQ_AVAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG_V1_8197F(x) | BIT_NPQ_AVAL_PG_V1_8197F(v)) #define BIT_SHIFT_NPQ_V1_8197F 0 #define BIT_MASK_NPQ_V1_8197F 0xfff -#define BIT_NPQ_V1_8197F(x) (((x) & BIT_MASK_NPQ_V1_8197F) << BIT_SHIFT_NPQ_V1_8197F) +#define BIT_NPQ_V1_8197F(x) \ + (((x) & BIT_MASK_NPQ_V1_8197F) << BIT_SHIFT_NPQ_V1_8197F) #define BITS_NPQ_V1_8197F (BIT_MASK_NPQ_V1_8197F << BIT_SHIFT_NPQ_V1_8197F) #define BIT_CLEAR_NPQ_V1_8197F(x) ((x) & (~BITS_NPQ_V1_8197F)) -#define BIT_GET_NPQ_V1_8197F(x) (((x) >> BIT_SHIFT_NPQ_V1_8197F) & BIT_MASK_NPQ_V1_8197F) -#define BIT_SET_NPQ_V1_8197F(x, v) (BIT_CLEAR_NPQ_V1_8197F(x) | BIT_NPQ_V1_8197F(v)) - +#define BIT_GET_NPQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_NPQ_V1_8197F) & BIT_MASK_NPQ_V1_8197F) +#define BIT_SET_NPQ_V1_8197F(x, v) \ + (BIT_CLEAR_NPQ_V1_8197F(x) | BIT_NPQ_V1_8197F(v)) /* 2 REG_FIFOPAGE_INFO_4_8197F */ #define BIT_SHIFT_EXQ_AVAL_PG_V1_8197F 16 #define BIT_MASK_EXQ_AVAL_PG_V1_8197F 0xfff -#define BIT_EXQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8197F) << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) -#define BITS_EXQ_AVAL_PG_V1_8197F (BIT_MASK_EXQ_AVAL_PG_V1_8197F << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) +#define BIT_EXQ_AVAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8197F) \ + << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) +#define BITS_EXQ_AVAL_PG_V1_8197F \ + (BIT_MASK_EXQ_AVAL_PG_V1_8197F << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) #define BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8197F)) -#define BIT_GET_EXQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) & BIT_MASK_EXQ_AVAL_PG_V1_8197F) -#define BIT_SET_EXQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) | BIT_EXQ_AVAL_PG_V1_8197F(v)) - +#define BIT_GET_EXQ_AVAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) & \ + BIT_MASK_EXQ_AVAL_PG_V1_8197F) +#define BIT_SET_EXQ_AVAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) | BIT_EXQ_AVAL_PG_V1_8197F(v)) #define BIT_SHIFT_EXQ_V1_8197F 0 #define BIT_MASK_EXQ_V1_8197F 0xfff -#define BIT_EXQ_V1_8197F(x) (((x) & BIT_MASK_EXQ_V1_8197F) << BIT_SHIFT_EXQ_V1_8197F) +#define BIT_EXQ_V1_8197F(x) \ + (((x) & BIT_MASK_EXQ_V1_8197F) << BIT_SHIFT_EXQ_V1_8197F) #define BITS_EXQ_V1_8197F (BIT_MASK_EXQ_V1_8197F << BIT_SHIFT_EXQ_V1_8197F) #define BIT_CLEAR_EXQ_V1_8197F(x) ((x) & (~BITS_EXQ_V1_8197F)) -#define BIT_GET_EXQ_V1_8197F(x) (((x) >> BIT_SHIFT_EXQ_V1_8197F) & BIT_MASK_EXQ_V1_8197F) -#define BIT_SET_EXQ_V1_8197F(x, v) (BIT_CLEAR_EXQ_V1_8197F(x) | BIT_EXQ_V1_8197F(v)) - +#define BIT_GET_EXQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_EXQ_V1_8197F) & BIT_MASK_EXQ_V1_8197F) +#define BIT_SET_EXQ_V1_8197F(x, v) \ + (BIT_CLEAR_EXQ_V1_8197F(x) | BIT_EXQ_V1_8197F(v)) /* 2 REG_FIFOPAGE_INFO_5_8197F */ #define BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F 16 #define BIT_MASK_PUBQ_AVAL_PG_V1_8197F 0xfff -#define BIT_PUBQ_AVAL_PG_V1_8197F(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8197F) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) -#define BITS_PUBQ_AVAL_PG_V1_8197F (BIT_MASK_PUBQ_AVAL_PG_V1_8197F << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) +#define BIT_PUBQ_AVAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8197F) \ + << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) +#define BITS_PUBQ_AVAL_PG_V1_8197F \ + (BIT_MASK_PUBQ_AVAL_PG_V1_8197F << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) #define BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8197F)) -#define BIT_GET_PUBQ_AVAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) & BIT_MASK_PUBQ_AVAL_PG_V1_8197F) -#define BIT_SET_PUBQ_AVAL_PG_V1_8197F(x, v) (BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) | BIT_PUBQ_AVAL_PG_V1_8197F(v)) - +#define BIT_GET_PUBQ_AVAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) & \ + BIT_MASK_PUBQ_AVAL_PG_V1_8197F) +#define BIT_SET_PUBQ_AVAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) | BIT_PUBQ_AVAL_PG_V1_8197F(v)) #define BIT_SHIFT_PUBQ_V1_8197F 0 #define BIT_MASK_PUBQ_V1_8197F 0xfff -#define BIT_PUBQ_V1_8197F(x) (((x) & BIT_MASK_PUBQ_V1_8197F) << BIT_SHIFT_PUBQ_V1_8197F) +#define BIT_PUBQ_V1_8197F(x) \ + (((x) & BIT_MASK_PUBQ_V1_8197F) << BIT_SHIFT_PUBQ_V1_8197F) #define BITS_PUBQ_V1_8197F (BIT_MASK_PUBQ_V1_8197F << BIT_SHIFT_PUBQ_V1_8197F) #define BIT_CLEAR_PUBQ_V1_8197F(x) ((x) & (~BITS_PUBQ_V1_8197F)) -#define BIT_GET_PUBQ_V1_8197F(x) (((x) >> BIT_SHIFT_PUBQ_V1_8197F) & BIT_MASK_PUBQ_V1_8197F) -#define BIT_SET_PUBQ_V1_8197F(x, v) (BIT_CLEAR_PUBQ_V1_8197F(x) | BIT_PUBQ_V1_8197F(v)) - +#define BIT_GET_PUBQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PUBQ_V1_8197F) & BIT_MASK_PUBQ_V1_8197F) +#define BIT_SET_PUBQ_V1_8197F(x, v) \ + (BIT_CLEAR_PUBQ_V1_8197F(x) | BIT_PUBQ_V1_8197F(v)) /* 2 REG_H2C_HEAD_8197F */ #define BIT_SHIFT_H2C_HEAD_8197F 0 #define BIT_MASK_H2C_HEAD_8197F 0x3ffff -#define BIT_H2C_HEAD_8197F(x) (((x) & BIT_MASK_H2C_HEAD_8197F) << BIT_SHIFT_H2C_HEAD_8197F) -#define BITS_H2C_HEAD_8197F (BIT_MASK_H2C_HEAD_8197F << BIT_SHIFT_H2C_HEAD_8197F) +#define BIT_H2C_HEAD_8197F(x) \ + (((x) & BIT_MASK_H2C_HEAD_8197F) << BIT_SHIFT_H2C_HEAD_8197F) +#define BITS_H2C_HEAD_8197F \ + (BIT_MASK_H2C_HEAD_8197F << BIT_SHIFT_H2C_HEAD_8197F) #define BIT_CLEAR_H2C_HEAD_8197F(x) ((x) & (~BITS_H2C_HEAD_8197F)) -#define BIT_GET_H2C_HEAD_8197F(x) (((x) >> BIT_SHIFT_H2C_HEAD_8197F) & BIT_MASK_H2C_HEAD_8197F) -#define BIT_SET_H2C_HEAD_8197F(x, v) (BIT_CLEAR_H2C_HEAD_8197F(x) | BIT_H2C_HEAD_8197F(v)) - +#define BIT_GET_H2C_HEAD_8197F(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_8197F) & BIT_MASK_H2C_HEAD_8197F) +#define BIT_SET_H2C_HEAD_8197F(x, v) \ + (BIT_CLEAR_H2C_HEAD_8197F(x) | BIT_H2C_HEAD_8197F(v)) /* 2 REG_H2C_TAIL_8197F */ #define BIT_SHIFT_H2C_TAIL_8197F 0 #define BIT_MASK_H2C_TAIL_8197F 0x3ffff -#define BIT_H2C_TAIL_8197F(x) (((x) & BIT_MASK_H2C_TAIL_8197F) << BIT_SHIFT_H2C_TAIL_8197F) -#define BITS_H2C_TAIL_8197F (BIT_MASK_H2C_TAIL_8197F << BIT_SHIFT_H2C_TAIL_8197F) +#define BIT_H2C_TAIL_8197F(x) \ + (((x) & BIT_MASK_H2C_TAIL_8197F) << BIT_SHIFT_H2C_TAIL_8197F) +#define BITS_H2C_TAIL_8197F \ + (BIT_MASK_H2C_TAIL_8197F << BIT_SHIFT_H2C_TAIL_8197F) #define BIT_CLEAR_H2C_TAIL_8197F(x) ((x) & (~BITS_H2C_TAIL_8197F)) -#define BIT_GET_H2C_TAIL_8197F(x) (((x) >> BIT_SHIFT_H2C_TAIL_8197F) & BIT_MASK_H2C_TAIL_8197F) -#define BIT_SET_H2C_TAIL_8197F(x, v) (BIT_CLEAR_H2C_TAIL_8197F(x) | BIT_H2C_TAIL_8197F(v)) - +#define BIT_GET_H2C_TAIL_8197F(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_8197F) & BIT_MASK_H2C_TAIL_8197F) +#define BIT_SET_H2C_TAIL_8197F(x, v) \ + (BIT_CLEAR_H2C_TAIL_8197F(x) | BIT_H2C_TAIL_8197F(v)) /* 2 REG_H2C_READ_ADDR_8197F */ #define BIT_SHIFT_H2C_READ_ADDR_8197F 0 #define BIT_MASK_H2C_READ_ADDR_8197F 0x3ffff -#define BIT_H2C_READ_ADDR_8197F(x) (((x) & BIT_MASK_H2C_READ_ADDR_8197F) << BIT_SHIFT_H2C_READ_ADDR_8197F) -#define BITS_H2C_READ_ADDR_8197F (BIT_MASK_H2C_READ_ADDR_8197F << BIT_SHIFT_H2C_READ_ADDR_8197F) +#define BIT_H2C_READ_ADDR_8197F(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_8197F) << BIT_SHIFT_H2C_READ_ADDR_8197F) +#define BITS_H2C_READ_ADDR_8197F \ + (BIT_MASK_H2C_READ_ADDR_8197F << BIT_SHIFT_H2C_READ_ADDR_8197F) #define BIT_CLEAR_H2C_READ_ADDR_8197F(x) ((x) & (~BITS_H2C_READ_ADDR_8197F)) -#define BIT_GET_H2C_READ_ADDR_8197F(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8197F) & BIT_MASK_H2C_READ_ADDR_8197F) -#define BIT_SET_H2C_READ_ADDR_8197F(x, v) (BIT_CLEAR_H2C_READ_ADDR_8197F(x) | BIT_H2C_READ_ADDR_8197F(v)) - +#define BIT_GET_H2C_READ_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_8197F) & BIT_MASK_H2C_READ_ADDR_8197F) +#define BIT_SET_H2C_READ_ADDR_8197F(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_8197F(x) | BIT_H2C_READ_ADDR_8197F(v)) /* 2 REG_H2C_WR_ADDR_8197F */ #define BIT_SHIFT_H2C_WR_ADDR_8197F 0 #define BIT_MASK_H2C_WR_ADDR_8197F 0x3ffff -#define BIT_H2C_WR_ADDR_8197F(x) (((x) & BIT_MASK_H2C_WR_ADDR_8197F) << BIT_SHIFT_H2C_WR_ADDR_8197F) -#define BITS_H2C_WR_ADDR_8197F (BIT_MASK_H2C_WR_ADDR_8197F << BIT_SHIFT_H2C_WR_ADDR_8197F) +#define BIT_H2C_WR_ADDR_8197F(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_8197F) << BIT_SHIFT_H2C_WR_ADDR_8197F) +#define BITS_H2C_WR_ADDR_8197F \ + (BIT_MASK_H2C_WR_ADDR_8197F << BIT_SHIFT_H2C_WR_ADDR_8197F) #define BIT_CLEAR_H2C_WR_ADDR_8197F(x) ((x) & (~BITS_H2C_WR_ADDR_8197F)) -#define BIT_GET_H2C_WR_ADDR_8197F(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8197F) & BIT_MASK_H2C_WR_ADDR_8197F) -#define BIT_SET_H2C_WR_ADDR_8197F(x, v) (BIT_CLEAR_H2C_WR_ADDR_8197F(x) | BIT_H2C_WR_ADDR_8197F(v)) - +#define BIT_GET_H2C_WR_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_8197F) & BIT_MASK_H2C_WR_ADDR_8197F) +#define BIT_SET_H2C_WR_ADDR_8197F(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_8197F(x) | BIT_H2C_WR_ADDR_8197F(v)) /* 2 REG_H2C_INFO_8197F */ #define BIT_EXQ_EN_PUBLIC_LIMIT_8197F BIT(11) @@ -4296,48 +5366,63 @@ #define BIT_SHIFT_H2C_LEN_SEL_8197F 0 #define BIT_MASK_H2C_LEN_SEL_8197F 0x3 -#define BIT_H2C_LEN_SEL_8197F(x) (((x) & BIT_MASK_H2C_LEN_SEL_8197F) << BIT_SHIFT_H2C_LEN_SEL_8197F) -#define BITS_H2C_LEN_SEL_8197F (BIT_MASK_H2C_LEN_SEL_8197F << BIT_SHIFT_H2C_LEN_SEL_8197F) +#define BIT_H2C_LEN_SEL_8197F(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL_8197F) << BIT_SHIFT_H2C_LEN_SEL_8197F) +#define BITS_H2C_LEN_SEL_8197F \ + (BIT_MASK_H2C_LEN_SEL_8197F << BIT_SHIFT_H2C_LEN_SEL_8197F) #define BIT_CLEAR_H2C_LEN_SEL_8197F(x) ((x) & (~BITS_H2C_LEN_SEL_8197F)) -#define BIT_GET_H2C_LEN_SEL_8197F(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8197F) & BIT_MASK_H2C_LEN_SEL_8197F) -#define BIT_SET_H2C_LEN_SEL_8197F(x, v) (BIT_CLEAR_H2C_LEN_SEL_8197F(x) | BIT_H2C_LEN_SEL_8197F(v)) - +#define BIT_GET_H2C_LEN_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL_8197F) & BIT_MASK_H2C_LEN_SEL_8197F) +#define BIT_SET_H2C_LEN_SEL_8197F(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL_8197F(x) | BIT_H2C_LEN_SEL_8197F(v)) #define BIT_SHIFT_VI_PUB_LIMIT_8197F 16 #define BIT_MASK_VI_PUB_LIMIT_8197F 0xfff -#define BIT_VI_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_VI_PUB_LIMIT_8197F) << BIT_SHIFT_VI_PUB_LIMIT_8197F) -#define BITS_VI_PUB_LIMIT_8197F (BIT_MASK_VI_PUB_LIMIT_8197F << BIT_SHIFT_VI_PUB_LIMIT_8197F) +#define BIT_VI_PUB_LIMIT_8197F(x) \ + (((x) & BIT_MASK_VI_PUB_LIMIT_8197F) << BIT_SHIFT_VI_PUB_LIMIT_8197F) +#define BITS_VI_PUB_LIMIT_8197F \ + (BIT_MASK_VI_PUB_LIMIT_8197F << BIT_SHIFT_VI_PUB_LIMIT_8197F) #define BIT_CLEAR_VI_PUB_LIMIT_8197F(x) ((x) & (~BITS_VI_PUB_LIMIT_8197F)) -#define BIT_GET_VI_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_VI_PUB_LIMIT_8197F) & BIT_MASK_VI_PUB_LIMIT_8197F) -#define BIT_SET_VI_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_VI_PUB_LIMIT_8197F(x) | BIT_VI_PUB_LIMIT_8197F(v)) - +#define BIT_GET_VI_PUB_LIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_VI_PUB_LIMIT_8197F) & BIT_MASK_VI_PUB_LIMIT_8197F) +#define BIT_SET_VI_PUB_LIMIT_8197F(x, v) \ + (BIT_CLEAR_VI_PUB_LIMIT_8197F(x) | BIT_VI_PUB_LIMIT_8197F(v)) #define BIT_SHIFT_VO_PUB_LIMIT_8197F 0 #define BIT_MASK_VO_PUB_LIMIT_8197F 0xfff -#define BIT_VO_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_VO_PUB_LIMIT_8197F) << BIT_SHIFT_VO_PUB_LIMIT_8197F) -#define BITS_VO_PUB_LIMIT_8197F (BIT_MASK_VO_PUB_LIMIT_8197F << BIT_SHIFT_VO_PUB_LIMIT_8197F) +#define BIT_VO_PUB_LIMIT_8197F(x) \ + (((x) & BIT_MASK_VO_PUB_LIMIT_8197F) << BIT_SHIFT_VO_PUB_LIMIT_8197F) +#define BITS_VO_PUB_LIMIT_8197F \ + (BIT_MASK_VO_PUB_LIMIT_8197F << BIT_SHIFT_VO_PUB_LIMIT_8197F) #define BIT_CLEAR_VO_PUB_LIMIT_8197F(x) ((x) & (~BITS_VO_PUB_LIMIT_8197F)) -#define BIT_GET_VO_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_VO_PUB_LIMIT_8197F) & BIT_MASK_VO_PUB_LIMIT_8197F) -#define BIT_SET_VO_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_VO_PUB_LIMIT_8197F(x) | BIT_VO_PUB_LIMIT_8197F(v)) - +#define BIT_GET_VO_PUB_LIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_VO_PUB_LIMIT_8197F) & BIT_MASK_VO_PUB_LIMIT_8197F) +#define BIT_SET_VO_PUB_LIMIT_8197F(x, v) \ + (BIT_CLEAR_VO_PUB_LIMIT_8197F(x) | BIT_VO_PUB_LIMIT_8197F(v)) #define BIT_SHIFT_BK_PUB_LIMIT_8197F 16 #define BIT_MASK_BK_PUB_LIMIT_8197F 0xfff -#define BIT_BK_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_BK_PUB_LIMIT_8197F) << BIT_SHIFT_BK_PUB_LIMIT_8197F) -#define BITS_BK_PUB_LIMIT_8197F (BIT_MASK_BK_PUB_LIMIT_8197F << BIT_SHIFT_BK_PUB_LIMIT_8197F) +#define BIT_BK_PUB_LIMIT_8197F(x) \ + (((x) & BIT_MASK_BK_PUB_LIMIT_8197F) << BIT_SHIFT_BK_PUB_LIMIT_8197F) +#define BITS_BK_PUB_LIMIT_8197F \ + (BIT_MASK_BK_PUB_LIMIT_8197F << BIT_SHIFT_BK_PUB_LIMIT_8197F) #define BIT_CLEAR_BK_PUB_LIMIT_8197F(x) ((x) & (~BITS_BK_PUB_LIMIT_8197F)) -#define BIT_GET_BK_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_BK_PUB_LIMIT_8197F) & BIT_MASK_BK_PUB_LIMIT_8197F) -#define BIT_SET_BK_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_BK_PUB_LIMIT_8197F(x) | BIT_BK_PUB_LIMIT_8197F(v)) - +#define BIT_GET_BK_PUB_LIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_BK_PUB_LIMIT_8197F) & BIT_MASK_BK_PUB_LIMIT_8197F) +#define BIT_SET_BK_PUB_LIMIT_8197F(x, v) \ + (BIT_CLEAR_BK_PUB_LIMIT_8197F(x) | BIT_BK_PUB_LIMIT_8197F(v)) #define BIT_SHIFT_BE_PUB_LIMIT_8197F 0 #define BIT_MASK_BE_PUB_LIMIT_8197F 0xfff -#define BIT_BE_PUB_LIMIT_8197F(x) (((x) & BIT_MASK_BE_PUB_LIMIT_8197F) << BIT_SHIFT_BE_PUB_LIMIT_8197F) -#define BITS_BE_PUB_LIMIT_8197F (BIT_MASK_BE_PUB_LIMIT_8197F << BIT_SHIFT_BE_PUB_LIMIT_8197F) +#define BIT_BE_PUB_LIMIT_8197F(x) \ + (((x) & BIT_MASK_BE_PUB_LIMIT_8197F) << BIT_SHIFT_BE_PUB_LIMIT_8197F) +#define BITS_BE_PUB_LIMIT_8197F \ + (BIT_MASK_BE_PUB_LIMIT_8197F << BIT_SHIFT_BE_PUB_LIMIT_8197F) #define BIT_CLEAR_BE_PUB_LIMIT_8197F(x) ((x) & (~BITS_BE_PUB_LIMIT_8197F)) -#define BIT_GET_BE_PUB_LIMIT_8197F(x) (((x) >> BIT_SHIFT_BE_PUB_LIMIT_8197F) & BIT_MASK_BE_PUB_LIMIT_8197F) -#define BIT_SET_BE_PUB_LIMIT_8197F(x, v) (BIT_CLEAR_BE_PUB_LIMIT_8197F(x) | BIT_BE_PUB_LIMIT_8197F(v)) - +#define BIT_GET_BE_PUB_LIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_BE_PUB_LIMIT_8197F) & BIT_MASK_BE_PUB_LIMIT_8197F) +#define BIT_SET_BE_PUB_LIMIT_8197F(x, v) \ + (BIT_CLEAR_BE_PUB_LIMIT_8197F(x) | BIT_BE_PUB_LIMIT_8197F(v)) /* 2 REG_RXDMA_AGG_PG_TH_8197F */ #define BIT_DMA_STORE_MODE_8197F BIT(31) @@ -4347,49 +5432,72 @@ #define BIT_SHIFT_PKT_NUM_WOL_8197F 16 #define BIT_MASK_PKT_NUM_WOL_8197F 0xff -#define BIT_PKT_NUM_WOL_8197F(x) (((x) & BIT_MASK_PKT_NUM_WOL_8197F) << BIT_SHIFT_PKT_NUM_WOL_8197F) -#define BITS_PKT_NUM_WOL_8197F (BIT_MASK_PKT_NUM_WOL_8197F << BIT_SHIFT_PKT_NUM_WOL_8197F) +#define BIT_PKT_NUM_WOL_8197F(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_8197F) << BIT_SHIFT_PKT_NUM_WOL_8197F) +#define BITS_PKT_NUM_WOL_8197F \ + (BIT_MASK_PKT_NUM_WOL_8197F << BIT_SHIFT_PKT_NUM_WOL_8197F) #define BIT_CLEAR_PKT_NUM_WOL_8197F(x) ((x) & (~BITS_PKT_NUM_WOL_8197F)) -#define BIT_GET_PKT_NUM_WOL_8197F(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8197F) & BIT_MASK_PKT_NUM_WOL_8197F) -#define BIT_SET_PKT_NUM_WOL_8197F(x, v) (BIT_CLEAR_PKT_NUM_WOL_8197F(x) | BIT_PKT_NUM_WOL_8197F(v)) - - -#define BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F 8 -#define BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F 0xff -#define BIT_RXDMA_AGG_TIMEOUT_TH_8197F(x) (((x) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F) << BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F) -#define BITS_RXDMA_AGG_TIMEOUT_TH_8197F (BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F << BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F) -#define BIT_CLEAR_RXDMA_AGG_TIMEOUT_TH_8197F(x) ((x) & (~BITS_RXDMA_AGG_TIMEOUT_TH_8197F)) -#define BIT_GET_RXDMA_AGG_TIMEOUT_TH_8197F(x) (((x) >> BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH_8197F) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH_8197F) -#define BIT_SET_RXDMA_AGG_TIMEOUT_TH_8197F(x, v) (BIT_CLEAR_RXDMA_AGG_TIMEOUT_TH_8197F(x) | BIT_RXDMA_AGG_TIMEOUT_TH_8197F(v)) - +#define BIT_GET_PKT_NUM_WOL_8197F(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_8197F) & BIT_MASK_PKT_NUM_WOL_8197F) +#define BIT_SET_PKT_NUM_WOL_8197F(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_8197F(x) | BIT_PKT_NUM_WOL_8197F(v)) + +#define BIT_SHIFT_DMA_AGG_TO_V1_8197F 8 +#define BIT_MASK_DMA_AGG_TO_V1_8197F 0xff +#define BIT_DMA_AGG_TO_V1_8197F(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1_8197F) << BIT_SHIFT_DMA_AGG_TO_V1_8197F) +#define BITS_DMA_AGG_TO_V1_8197F \ + (BIT_MASK_DMA_AGG_TO_V1_8197F << BIT_SHIFT_DMA_AGG_TO_V1_8197F) +#define BIT_CLEAR_DMA_AGG_TO_V1_8197F(x) ((x) & (~BITS_DMA_AGG_TO_V1_8197F)) +#define BIT_GET_DMA_AGG_TO_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8197F) & BIT_MASK_DMA_AGG_TO_V1_8197F) +#define BIT_SET_DMA_AGG_TO_V1_8197F(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1_8197F(x) | BIT_DMA_AGG_TO_V1_8197F(v)) #define BIT_SHIFT_RXDMA_AGG_PG_TH_8197F 0 #define BIT_MASK_RXDMA_AGG_PG_TH_8197F 0xff -#define BIT_RXDMA_AGG_PG_TH_8197F(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8197F) << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) -#define BITS_RXDMA_AGG_PG_TH_8197F (BIT_MASK_RXDMA_AGG_PG_TH_8197F << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) +#define BIT_RXDMA_AGG_PG_TH_8197F(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8197F) \ + << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) +#define BITS_RXDMA_AGG_PG_TH_8197F \ + (BIT_MASK_RXDMA_AGG_PG_TH_8197F << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) #define BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8197F)) -#define BIT_GET_RXDMA_AGG_PG_TH_8197F(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) & BIT_MASK_RXDMA_AGG_PG_TH_8197F) -#define BIT_SET_RXDMA_AGG_PG_TH_8197F(x, v) (BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) | BIT_RXDMA_AGG_PG_TH_8197F(v)) - +#define BIT_GET_RXDMA_AGG_PG_TH_8197F(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) & \ + BIT_MASK_RXDMA_AGG_PG_TH_8197F) +#define BIT_SET_RXDMA_AGG_PG_TH_8197F(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) | BIT_RXDMA_AGG_PG_TH_8197F(v)) /* 2 REG_RXPKT_NUM_8197F */ #define BIT_SHIFT_RXPKT_NUM_8197F 24 #define BIT_MASK_RXPKT_NUM_8197F 0xff -#define BIT_RXPKT_NUM_8197F(x) (((x) & BIT_MASK_RXPKT_NUM_8197F) << BIT_SHIFT_RXPKT_NUM_8197F) -#define BITS_RXPKT_NUM_8197F (BIT_MASK_RXPKT_NUM_8197F << BIT_SHIFT_RXPKT_NUM_8197F) +#define BIT_RXPKT_NUM_8197F(x) \ + (((x) & BIT_MASK_RXPKT_NUM_8197F) << BIT_SHIFT_RXPKT_NUM_8197F) +#define BITS_RXPKT_NUM_8197F \ + (BIT_MASK_RXPKT_NUM_8197F << BIT_SHIFT_RXPKT_NUM_8197F) #define BIT_CLEAR_RXPKT_NUM_8197F(x) ((x) & (~BITS_RXPKT_NUM_8197F)) -#define BIT_GET_RXPKT_NUM_8197F(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8197F) & BIT_MASK_RXPKT_NUM_8197F) -#define BIT_SET_RXPKT_NUM_8197F(x, v) (BIT_CLEAR_RXPKT_NUM_8197F(x) | BIT_RXPKT_NUM_8197F(v)) - +#define BIT_GET_RXPKT_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_8197F) & BIT_MASK_RXPKT_NUM_8197F) +#define BIT_SET_RXPKT_NUM_8197F(x, v) \ + (BIT_CLEAR_RXPKT_NUM_8197F(x) | BIT_RXPKT_NUM_8197F(v)) #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F 20 #define BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F 0xf -#define BIT_FW_UPD_RDPTR19_TO_16_8197F(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) -#define BITS_FW_UPD_RDPTR19_TO_16_8197F (BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) -#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8197F)) -#define BIT_GET_FW_UPD_RDPTR19_TO_16_8197F(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F) -#define BIT_SET_FW_UPD_RDPTR19_TO_16_8197F(x, v) (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) | BIT_FW_UPD_RDPTR19_TO_16_8197F(v)) +#define BIT_FW_UPD_RDPTR19_TO_16_8197F(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) +#define BITS_FW_UPD_RDPTR19_TO_16_8197F \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) \ + ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8197F)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8197F(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F) +#define BIT_SET_FW_UPD_RDPTR19_TO_16_8197F(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) | \ + BIT_FW_UPD_RDPTR19_TO_16_8197F(v)) #define BIT_RXDMA_REQ_8197F BIT(19) #define BIT_RW_RELEASE_EN_8197F BIT(18) @@ -4398,12 +5506,15 @@ #define BIT_SHIFT_FW_UPD_RDPTR_8197F 0 #define BIT_MASK_FW_UPD_RDPTR_8197F 0xffff -#define BIT_FW_UPD_RDPTR_8197F(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8197F) << BIT_SHIFT_FW_UPD_RDPTR_8197F) -#define BITS_FW_UPD_RDPTR_8197F (BIT_MASK_FW_UPD_RDPTR_8197F << BIT_SHIFT_FW_UPD_RDPTR_8197F) +#define BIT_FW_UPD_RDPTR_8197F(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR_8197F) << BIT_SHIFT_FW_UPD_RDPTR_8197F) +#define BITS_FW_UPD_RDPTR_8197F \ + (BIT_MASK_FW_UPD_RDPTR_8197F << BIT_SHIFT_FW_UPD_RDPTR_8197F) #define BIT_CLEAR_FW_UPD_RDPTR_8197F(x) ((x) & (~BITS_FW_UPD_RDPTR_8197F)) -#define BIT_GET_FW_UPD_RDPTR_8197F(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8197F) & BIT_MASK_FW_UPD_RDPTR_8197F) -#define BIT_SET_FW_UPD_RDPTR_8197F(x, v) (BIT_CLEAR_FW_UPD_RDPTR_8197F(x) | BIT_FW_UPD_RDPTR_8197F(v)) - +#define BIT_GET_FW_UPD_RDPTR_8197F(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8197F) & BIT_MASK_FW_UPD_RDPTR_8197F) +#define BIT_SET_FW_UPD_RDPTR_8197F(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR_8197F(x) | BIT_FW_UPD_RDPTR_8197F(v)) /* 2 REG_RXDMA_STATUS_8197F */ #define BIT_FC2H_PKT_OVERFLOW_8197F BIT(8) @@ -4419,12 +5530,15 @@ #define BIT_SHIFT_RDE_DEBUG_8197F 0 #define BIT_MASK_RDE_DEBUG_8197F 0xffffffffL -#define BIT_RDE_DEBUG_8197F(x) (((x) & BIT_MASK_RDE_DEBUG_8197F) << BIT_SHIFT_RDE_DEBUG_8197F) -#define BITS_RDE_DEBUG_8197F (BIT_MASK_RDE_DEBUG_8197F << BIT_SHIFT_RDE_DEBUG_8197F) +#define BIT_RDE_DEBUG_8197F(x) \ + (((x) & BIT_MASK_RDE_DEBUG_8197F) << BIT_SHIFT_RDE_DEBUG_8197F) +#define BITS_RDE_DEBUG_8197F \ + (BIT_MASK_RDE_DEBUG_8197F << BIT_SHIFT_RDE_DEBUG_8197F) #define BIT_CLEAR_RDE_DEBUG_8197F(x) ((x) & (~BITS_RDE_DEBUG_8197F)) -#define BIT_GET_RDE_DEBUG_8197F(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8197F) & BIT_MASK_RDE_DEBUG_8197F) -#define BIT_SET_RDE_DEBUG_8197F(x, v) (BIT_CLEAR_RDE_DEBUG_8197F(x) | BIT_RDE_DEBUG_8197F(v)) - +#define BIT_GET_RDE_DEBUG_8197F(x) \ + (((x) >> BIT_SHIFT_RDE_DEBUG_8197F) & BIT_MASK_RDE_DEBUG_8197F) +#define BIT_SET_RDE_DEBUG_8197F(x, v) \ + (BIT_CLEAR_RDE_DEBUG_8197F(x) | BIT_RDE_DEBUG_8197F(v)) /* 2 REG_RXDMA_MODE_8197F */ @@ -4437,20 +5551,27 @@ #define BIT_SHIFT_BURST_SIZE_8197F 4 #define BIT_MASK_BURST_SIZE_8197F 0x3 -#define BIT_BURST_SIZE_8197F(x) (((x) & BIT_MASK_BURST_SIZE_8197F) << BIT_SHIFT_BURST_SIZE_8197F) -#define BITS_BURST_SIZE_8197F (BIT_MASK_BURST_SIZE_8197F << BIT_SHIFT_BURST_SIZE_8197F) +#define BIT_BURST_SIZE_8197F(x) \ + (((x) & BIT_MASK_BURST_SIZE_8197F) << BIT_SHIFT_BURST_SIZE_8197F) +#define BITS_BURST_SIZE_8197F \ + (BIT_MASK_BURST_SIZE_8197F << BIT_SHIFT_BURST_SIZE_8197F) #define BIT_CLEAR_BURST_SIZE_8197F(x) ((x) & (~BITS_BURST_SIZE_8197F)) -#define BIT_GET_BURST_SIZE_8197F(x) (((x) >> BIT_SHIFT_BURST_SIZE_8197F) & BIT_MASK_BURST_SIZE_8197F) -#define BIT_SET_BURST_SIZE_8197F(x, v) (BIT_CLEAR_BURST_SIZE_8197F(x) | BIT_BURST_SIZE_8197F(v)) - +#define BIT_GET_BURST_SIZE_8197F(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE_8197F) & BIT_MASK_BURST_SIZE_8197F) +#define BIT_SET_BURST_SIZE_8197F(x, v) \ + (BIT_CLEAR_BURST_SIZE_8197F(x) | BIT_BURST_SIZE_8197F(v)) #define BIT_SHIFT_BURST_CNT_8197F 2 #define BIT_MASK_BURST_CNT_8197F 0x3 -#define BIT_BURST_CNT_8197F(x) (((x) & BIT_MASK_BURST_CNT_8197F) << BIT_SHIFT_BURST_CNT_8197F) -#define BITS_BURST_CNT_8197F (BIT_MASK_BURST_CNT_8197F << BIT_SHIFT_BURST_CNT_8197F) +#define BIT_BURST_CNT_8197F(x) \ + (((x) & BIT_MASK_BURST_CNT_8197F) << BIT_SHIFT_BURST_CNT_8197F) +#define BITS_BURST_CNT_8197F \ + (BIT_MASK_BURST_CNT_8197F << BIT_SHIFT_BURST_CNT_8197F) #define BIT_CLEAR_BURST_CNT_8197F(x) ((x) & (~BITS_BURST_CNT_8197F)) -#define BIT_GET_BURST_CNT_8197F(x) (((x) >> BIT_SHIFT_BURST_CNT_8197F) & BIT_MASK_BURST_CNT_8197F) -#define BIT_SET_BURST_CNT_8197F(x, v) (BIT_CLEAR_BURST_CNT_8197F(x) | BIT_BURST_CNT_8197F(v)) +#define BIT_GET_BURST_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_BURST_CNT_8197F) & BIT_MASK_BURST_CNT_8197F) +#define BIT_SET_BURST_CNT_8197F(x, v) \ + (BIT_CLEAR_BURST_CNT_8197F(x) | BIT_BURST_CNT_8197F(v)) #define BIT_DMA_MODE_8197F BIT(1) @@ -4458,86 +5579,126 @@ #define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F 24 #define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F 0xf -#define BIT_R_C2H_STR_ADDR_16_TO_19_8197F(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) -#define BITS_R_C2H_STR_ADDR_16_TO_19_8197F (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) -#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8197F)) -#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8197F(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F) -#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8197F(x, v) (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) | BIT_R_C2H_STR_ADDR_16_TO_19_8197F(v)) +#define BIT_R_C2H_STR_ADDR_16_TO_19_8197F(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) +#define BITS_R_C2H_STR_ADDR_16_TO_19_8197F \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8197F)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8197F(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8197F(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) | \ + BIT_R_C2H_STR_ADDR_16_TO_19_8197F(v)) #define BIT_R_C2H_PKT_REQ_8197F BIT(16) #define BIT_SHIFT_R_C2H_STR_ADDR_8197F 0 #define BIT_MASK_R_C2H_STR_ADDR_8197F 0xffff -#define BIT_R_C2H_STR_ADDR_8197F(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8197F) << BIT_SHIFT_R_C2H_STR_ADDR_8197F) -#define BITS_R_C2H_STR_ADDR_8197F (BIT_MASK_R_C2H_STR_ADDR_8197F << BIT_SHIFT_R_C2H_STR_ADDR_8197F) +#define BIT_R_C2H_STR_ADDR_8197F(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_8197F) \ + << BIT_SHIFT_R_C2H_STR_ADDR_8197F) +#define BITS_R_C2H_STR_ADDR_8197F \ + (BIT_MASK_R_C2H_STR_ADDR_8197F << BIT_SHIFT_R_C2H_STR_ADDR_8197F) #define BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) ((x) & (~BITS_R_C2H_STR_ADDR_8197F)) -#define BIT_GET_R_C2H_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8197F) & BIT_MASK_R_C2H_STR_ADDR_8197F) -#define BIT_SET_R_C2H_STR_ADDR_8197F(x, v) (BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) | BIT_R_C2H_STR_ADDR_8197F(v)) - +#define BIT_GET_R_C2H_STR_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8197F) & \ + BIT_MASK_R_C2H_STR_ADDR_8197F) +#define BIT_SET_R_C2H_STR_ADDR_8197F(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) | BIT_R_C2H_STR_ADDR_8197F(v)) /* 2 REG_FWFF_C2H_8197F */ #define BIT_SHIFT_C2H_DMA_ADDR_8197F 0 #define BIT_MASK_C2H_DMA_ADDR_8197F 0x3ffff -#define BIT_C2H_DMA_ADDR_8197F(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8197F) << BIT_SHIFT_C2H_DMA_ADDR_8197F) -#define BITS_C2H_DMA_ADDR_8197F (BIT_MASK_C2H_DMA_ADDR_8197F << BIT_SHIFT_C2H_DMA_ADDR_8197F) +#define BIT_C2H_DMA_ADDR_8197F(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR_8197F) << BIT_SHIFT_C2H_DMA_ADDR_8197F) +#define BITS_C2H_DMA_ADDR_8197F \ + (BIT_MASK_C2H_DMA_ADDR_8197F << BIT_SHIFT_C2H_DMA_ADDR_8197F) #define BIT_CLEAR_C2H_DMA_ADDR_8197F(x) ((x) & (~BITS_C2H_DMA_ADDR_8197F)) -#define BIT_GET_C2H_DMA_ADDR_8197F(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8197F) & BIT_MASK_C2H_DMA_ADDR_8197F) -#define BIT_SET_C2H_DMA_ADDR_8197F(x, v) (BIT_CLEAR_C2H_DMA_ADDR_8197F(x) | BIT_C2H_DMA_ADDR_8197F(v)) - +#define BIT_GET_C2H_DMA_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8197F) & BIT_MASK_C2H_DMA_ADDR_8197F) +#define BIT_SET_C2H_DMA_ADDR_8197F(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR_8197F(x) | BIT_C2H_DMA_ADDR_8197F(v)) /* 2 REG_FWFF_CTRL_8197F */ #define BIT_FWFF_DMAPKT_REQ_8197F BIT(31) #define BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F 16 #define BIT_MASK_FWFF_DMA_PKT_NUM_8197F 0xff -#define BIT_FWFF_DMA_PKT_NUM_8197F(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8197F) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) -#define BITS_FWFF_DMA_PKT_NUM_8197F (BIT_MASK_FWFF_DMA_PKT_NUM_8197F << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) -#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM_8197F)) -#define BIT_GET_FWFF_DMA_PKT_NUM_8197F(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) & BIT_MASK_FWFF_DMA_PKT_NUM_8197F) -#define BIT_SET_FWFF_DMA_PKT_NUM_8197F(x, v) (BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) | BIT_FWFF_DMA_PKT_NUM_8197F(v)) - +#define BIT_FWFF_DMA_PKT_NUM_8197F(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8197F) \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) +#define BITS_FWFF_DMA_PKT_NUM_8197F \ + (BIT_MASK_FWFF_DMA_PKT_NUM_8197F << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) \ + ((x) & (~BITS_FWFF_DMA_PKT_NUM_8197F)) +#define BIT_GET_FWFF_DMA_PKT_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) & \ + BIT_MASK_FWFF_DMA_PKT_NUM_8197F) +#define BIT_SET_FWFF_DMA_PKT_NUM_8197F(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) | BIT_FWFF_DMA_PKT_NUM_8197F(v)) #define BIT_SHIFT_FWFF_STR_ADDR_8197F 0 #define BIT_MASK_FWFF_STR_ADDR_8197F 0xffff -#define BIT_FWFF_STR_ADDR_8197F(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8197F) << BIT_SHIFT_FWFF_STR_ADDR_8197F) -#define BITS_FWFF_STR_ADDR_8197F (BIT_MASK_FWFF_STR_ADDR_8197F << BIT_SHIFT_FWFF_STR_ADDR_8197F) +#define BIT_FWFF_STR_ADDR_8197F(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR_8197F) << BIT_SHIFT_FWFF_STR_ADDR_8197F) +#define BITS_FWFF_STR_ADDR_8197F \ + (BIT_MASK_FWFF_STR_ADDR_8197F << BIT_SHIFT_FWFF_STR_ADDR_8197F) #define BIT_CLEAR_FWFF_STR_ADDR_8197F(x) ((x) & (~BITS_FWFF_STR_ADDR_8197F)) -#define BIT_GET_FWFF_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8197F) & BIT_MASK_FWFF_STR_ADDR_8197F) -#define BIT_SET_FWFF_STR_ADDR_8197F(x, v) (BIT_CLEAR_FWFF_STR_ADDR_8197F(x) | BIT_FWFF_STR_ADDR_8197F(v)) - +#define BIT_GET_FWFF_STR_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8197F) & BIT_MASK_FWFF_STR_ADDR_8197F) +#define BIT_SET_FWFF_STR_ADDR_8197F(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR_8197F(x) | BIT_FWFF_STR_ADDR_8197F(v)) /* 2 REG_FWFF_PKT_INFO_8197F */ #define BIT_SHIFT_FWFF_PKT_QUEUED_8197F 16 #define BIT_MASK_FWFF_PKT_QUEUED_8197F 0xff -#define BIT_FWFF_PKT_QUEUED_8197F(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8197F) << BIT_SHIFT_FWFF_PKT_QUEUED_8197F) -#define BITS_FWFF_PKT_QUEUED_8197F (BIT_MASK_FWFF_PKT_QUEUED_8197F << BIT_SHIFT_FWFF_PKT_QUEUED_8197F) +#define BIT_FWFF_PKT_QUEUED_8197F(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_8197F) \ + << BIT_SHIFT_FWFF_PKT_QUEUED_8197F) +#define BITS_FWFF_PKT_QUEUED_8197F \ + (BIT_MASK_FWFF_PKT_QUEUED_8197F << BIT_SHIFT_FWFF_PKT_QUEUED_8197F) #define BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8197F)) -#define BIT_GET_FWFF_PKT_QUEUED_8197F(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8197F) & BIT_MASK_FWFF_PKT_QUEUED_8197F) -#define BIT_SET_FWFF_PKT_QUEUED_8197F(x, v) (BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) | BIT_FWFF_PKT_QUEUED_8197F(v)) - +#define BIT_GET_FWFF_PKT_QUEUED_8197F(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8197F) & \ + BIT_MASK_FWFF_PKT_QUEUED_8197F) +#define BIT_SET_FWFF_PKT_QUEUED_8197F(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) | BIT_FWFF_PKT_QUEUED_8197F(v)) #define BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F 0 #define BIT_MASK_FWFF_PKT_STR_ADDR_8197F 0xffff -#define BIT_FWFF_PKT_STR_ADDR_8197F(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8197F) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) -#define BITS_FWFF_PKT_STR_ADDR_8197F (BIT_MASK_FWFF_PKT_STR_ADDR_8197F << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) -#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_8197F)) -#define BIT_GET_FWFF_PKT_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) & BIT_MASK_FWFF_PKT_STR_ADDR_8197F) -#define BIT_SET_FWFF_PKT_STR_ADDR_8197F(x, v) (BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) | BIT_FWFF_PKT_STR_ADDR_8197F(v)) - +#define BIT_FWFF_PKT_STR_ADDR_8197F(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8197F) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) +#define BITS_FWFF_PKT_STR_ADDR_8197F \ + (BIT_MASK_FWFF_PKT_STR_ADDR_8197F << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) \ + ((x) & (~BITS_FWFF_PKT_STR_ADDR_8197F)) +#define BIT_GET_FWFF_PKT_STR_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_8197F) +#define BIT_SET_FWFF_PKT_STR_ADDR_8197F(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) | BIT_FWFF_PKT_STR_ADDR_8197F(v)) /* 2 REG_FC2H_INFO_8197F */ #define BIT_FC2H_PKT_REQ_8197F BIT(16) -#define BIT_SHIFT_FC2H_STR_ADDR_8197F 17 -#define BIT_MASK_FC2H_STR_ADDR_8197F 0x7fff -#define BIT_FC2H_STR_ADDR_8197F(x) (((x) & BIT_MASK_FC2H_STR_ADDR_8197F) << BIT_SHIFT_FC2H_STR_ADDR_8197F) -#define BITS_FC2H_STR_ADDR_8197F (BIT_MASK_FC2H_STR_ADDR_8197F << BIT_SHIFT_FC2H_STR_ADDR_8197F) +#define BIT_SHIFT_FC2H_STR_ADDR_8197F 0 +#define BIT_MASK_FC2H_STR_ADDR_8197F 0xffff +#define BIT_FC2H_STR_ADDR_8197F(x) \ + (((x) & BIT_MASK_FC2H_STR_ADDR_8197F) << BIT_SHIFT_FC2H_STR_ADDR_8197F) +#define BITS_FC2H_STR_ADDR_8197F \ + (BIT_MASK_FC2H_STR_ADDR_8197F << BIT_SHIFT_FC2H_STR_ADDR_8197F) #define BIT_CLEAR_FC2H_STR_ADDR_8197F(x) ((x) & (~BITS_FC2H_STR_ADDR_8197F)) -#define BIT_GET_FC2H_STR_ADDR_8197F(x) (((x) >> BIT_SHIFT_FC2H_STR_ADDR_8197F) & BIT_MASK_FC2H_STR_ADDR_8197F) -#define BIT_SET_FC2H_STR_ADDR_8197F(x, v) (BIT_CLEAR_FC2H_STR_ADDR_8197F(x) | BIT_FC2H_STR_ADDR_8197F(v)) - +#define BIT_GET_FC2H_STR_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_FC2H_STR_ADDR_8197F) & BIT_MASK_FC2H_STR_ADDR_8197F) +#define BIT_SET_FC2H_STR_ADDR_8197F(x, v) \ + (BIT_CLEAR_FC2H_STR_ADDR_8197F(x) | BIT_FC2H_STR_ADDR_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -4545,23 +5706,29 @@ #define BIT_SHIFT_DDMACH0_SA_8197F 0 #define BIT_MASK_DDMACH0_SA_8197F 0xffffffffL -#define BIT_DDMACH0_SA_8197F(x) (((x) & BIT_MASK_DDMACH0_SA_8197F) << BIT_SHIFT_DDMACH0_SA_8197F) -#define BITS_DDMACH0_SA_8197F (BIT_MASK_DDMACH0_SA_8197F << BIT_SHIFT_DDMACH0_SA_8197F) +#define BIT_DDMACH0_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH0_SA_8197F) << BIT_SHIFT_DDMACH0_SA_8197F) +#define BITS_DDMACH0_SA_8197F \ + (BIT_MASK_DDMACH0_SA_8197F << BIT_SHIFT_DDMACH0_SA_8197F) #define BIT_CLEAR_DDMACH0_SA_8197F(x) ((x) & (~BITS_DDMACH0_SA_8197F)) -#define BIT_GET_DDMACH0_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8197F) & BIT_MASK_DDMACH0_SA_8197F) -#define BIT_SET_DDMACH0_SA_8197F(x, v) (BIT_CLEAR_DDMACH0_SA_8197F(x) | BIT_DDMACH0_SA_8197F(v)) - +#define BIT_GET_DDMACH0_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA_8197F) & BIT_MASK_DDMACH0_SA_8197F) +#define BIT_SET_DDMACH0_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH0_SA_8197F(x) | BIT_DDMACH0_SA_8197F(v)) /* 2 REG_DDMA_CH0DA_8197F */ #define BIT_SHIFT_DDMACH0_DA_8197F 0 #define BIT_MASK_DDMACH0_DA_8197F 0xffffffffL -#define BIT_DDMACH0_DA_8197F(x) (((x) & BIT_MASK_DDMACH0_DA_8197F) << BIT_SHIFT_DDMACH0_DA_8197F) -#define BITS_DDMACH0_DA_8197F (BIT_MASK_DDMACH0_DA_8197F << BIT_SHIFT_DDMACH0_DA_8197F) +#define BIT_DDMACH0_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH0_DA_8197F) << BIT_SHIFT_DDMACH0_DA_8197F) +#define BITS_DDMACH0_DA_8197F \ + (BIT_MASK_DDMACH0_DA_8197F << BIT_SHIFT_DDMACH0_DA_8197F) #define BIT_CLEAR_DDMACH0_DA_8197F(x) ((x) & (~BITS_DDMACH0_DA_8197F)) -#define BIT_GET_DDMACH0_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8197F) & BIT_MASK_DDMACH0_DA_8197F) -#define BIT_SET_DDMACH0_DA_8197F(x, v) (BIT_CLEAR_DDMACH0_DA_8197F(x) | BIT_DDMACH0_DA_8197F(v)) - +#define BIT_GET_DDMACH0_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA_8197F) & BIT_MASK_DDMACH0_DA_8197F) +#define BIT_SET_DDMACH0_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH0_DA_8197F(x) | BIT_DDMACH0_DA_8197F(v)) /* 2 REG_DDMA_CH0CTRL_8197F */ #define BIT_DDMACH0_OWN_8197F BIT(31) @@ -4574,34 +5741,43 @@ #define BIT_SHIFT_DDMACH0_DLEN_8197F 0 #define BIT_MASK_DDMACH0_DLEN_8197F 0x3ffff -#define BIT_DDMACH0_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH0_DLEN_8197F) << BIT_SHIFT_DDMACH0_DLEN_8197F) -#define BITS_DDMACH0_DLEN_8197F (BIT_MASK_DDMACH0_DLEN_8197F << BIT_SHIFT_DDMACH0_DLEN_8197F) +#define BIT_DDMACH0_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN_8197F) << BIT_SHIFT_DDMACH0_DLEN_8197F) +#define BITS_DDMACH0_DLEN_8197F \ + (BIT_MASK_DDMACH0_DLEN_8197F << BIT_SHIFT_DDMACH0_DLEN_8197F) #define BIT_CLEAR_DDMACH0_DLEN_8197F(x) ((x) & (~BITS_DDMACH0_DLEN_8197F)) -#define BIT_GET_DDMACH0_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8197F) & BIT_MASK_DDMACH0_DLEN_8197F) -#define BIT_SET_DDMACH0_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH0_DLEN_8197F(x) | BIT_DDMACH0_DLEN_8197F(v)) - +#define BIT_GET_DDMACH0_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN_8197F) & BIT_MASK_DDMACH0_DLEN_8197F) +#define BIT_SET_DDMACH0_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN_8197F(x) | BIT_DDMACH0_DLEN_8197F(v)) /* 2 REG_DDMA_CH1SA_8197F */ #define BIT_SHIFT_DDMACH1_SA_8197F 0 #define BIT_MASK_DDMACH1_SA_8197F 0xffffffffL -#define BIT_DDMACH1_SA_8197F(x) (((x) & BIT_MASK_DDMACH1_SA_8197F) << BIT_SHIFT_DDMACH1_SA_8197F) -#define BITS_DDMACH1_SA_8197F (BIT_MASK_DDMACH1_SA_8197F << BIT_SHIFT_DDMACH1_SA_8197F) +#define BIT_DDMACH1_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH1_SA_8197F) << BIT_SHIFT_DDMACH1_SA_8197F) +#define BITS_DDMACH1_SA_8197F \ + (BIT_MASK_DDMACH1_SA_8197F << BIT_SHIFT_DDMACH1_SA_8197F) #define BIT_CLEAR_DDMACH1_SA_8197F(x) ((x) & (~BITS_DDMACH1_SA_8197F)) -#define BIT_GET_DDMACH1_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8197F) & BIT_MASK_DDMACH1_SA_8197F) -#define BIT_SET_DDMACH1_SA_8197F(x, v) (BIT_CLEAR_DDMACH1_SA_8197F(x) | BIT_DDMACH1_SA_8197F(v)) - +#define BIT_GET_DDMACH1_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA_8197F) & BIT_MASK_DDMACH1_SA_8197F) +#define BIT_SET_DDMACH1_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH1_SA_8197F(x) | BIT_DDMACH1_SA_8197F(v)) /* 2 REG_DDMA_CH1DA_8197F */ #define BIT_SHIFT_DDMACH1_DA_8197F 0 #define BIT_MASK_DDMACH1_DA_8197F 0xffffffffL -#define BIT_DDMACH1_DA_8197F(x) (((x) & BIT_MASK_DDMACH1_DA_8197F) << BIT_SHIFT_DDMACH1_DA_8197F) -#define BITS_DDMACH1_DA_8197F (BIT_MASK_DDMACH1_DA_8197F << BIT_SHIFT_DDMACH1_DA_8197F) +#define BIT_DDMACH1_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH1_DA_8197F) << BIT_SHIFT_DDMACH1_DA_8197F) +#define BITS_DDMACH1_DA_8197F \ + (BIT_MASK_DDMACH1_DA_8197F << BIT_SHIFT_DDMACH1_DA_8197F) #define BIT_CLEAR_DDMACH1_DA_8197F(x) ((x) & (~BITS_DDMACH1_DA_8197F)) -#define BIT_GET_DDMACH1_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8197F) & BIT_MASK_DDMACH1_DA_8197F) -#define BIT_SET_DDMACH1_DA_8197F(x, v) (BIT_CLEAR_DDMACH1_DA_8197F(x) | BIT_DDMACH1_DA_8197F(v)) - +#define BIT_GET_DDMACH1_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA_8197F) & BIT_MASK_DDMACH1_DA_8197F) +#define BIT_SET_DDMACH1_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH1_DA_8197F(x) | BIT_DDMACH1_DA_8197F(v)) /* 2 REG_DDMA_CH1CTRL_8197F */ #define BIT_DDMACH1_OWN_8197F BIT(31) @@ -4614,34 +5790,43 @@ #define BIT_SHIFT_DDMACH1_DLEN_8197F 0 #define BIT_MASK_DDMACH1_DLEN_8197F 0x3ffff -#define BIT_DDMACH1_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH1_DLEN_8197F) << BIT_SHIFT_DDMACH1_DLEN_8197F) -#define BITS_DDMACH1_DLEN_8197F (BIT_MASK_DDMACH1_DLEN_8197F << BIT_SHIFT_DDMACH1_DLEN_8197F) +#define BIT_DDMACH1_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN_8197F) << BIT_SHIFT_DDMACH1_DLEN_8197F) +#define BITS_DDMACH1_DLEN_8197F \ + (BIT_MASK_DDMACH1_DLEN_8197F << BIT_SHIFT_DDMACH1_DLEN_8197F) #define BIT_CLEAR_DDMACH1_DLEN_8197F(x) ((x) & (~BITS_DDMACH1_DLEN_8197F)) -#define BIT_GET_DDMACH1_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8197F) & BIT_MASK_DDMACH1_DLEN_8197F) -#define BIT_SET_DDMACH1_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH1_DLEN_8197F(x) | BIT_DDMACH1_DLEN_8197F(v)) - +#define BIT_GET_DDMACH1_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN_8197F) & BIT_MASK_DDMACH1_DLEN_8197F) +#define BIT_SET_DDMACH1_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN_8197F(x) | BIT_DDMACH1_DLEN_8197F(v)) /* 2 REG_DDMA_CH2SA_8197F */ #define BIT_SHIFT_DDMACH2_SA_8197F 0 #define BIT_MASK_DDMACH2_SA_8197F 0xffffffffL -#define BIT_DDMACH2_SA_8197F(x) (((x) & BIT_MASK_DDMACH2_SA_8197F) << BIT_SHIFT_DDMACH2_SA_8197F) -#define BITS_DDMACH2_SA_8197F (BIT_MASK_DDMACH2_SA_8197F << BIT_SHIFT_DDMACH2_SA_8197F) +#define BIT_DDMACH2_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH2_SA_8197F) << BIT_SHIFT_DDMACH2_SA_8197F) +#define BITS_DDMACH2_SA_8197F \ + (BIT_MASK_DDMACH2_SA_8197F << BIT_SHIFT_DDMACH2_SA_8197F) #define BIT_CLEAR_DDMACH2_SA_8197F(x) ((x) & (~BITS_DDMACH2_SA_8197F)) -#define BIT_GET_DDMACH2_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8197F) & BIT_MASK_DDMACH2_SA_8197F) -#define BIT_SET_DDMACH2_SA_8197F(x, v) (BIT_CLEAR_DDMACH2_SA_8197F(x) | BIT_DDMACH2_SA_8197F(v)) - +#define BIT_GET_DDMACH2_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA_8197F) & BIT_MASK_DDMACH2_SA_8197F) +#define BIT_SET_DDMACH2_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH2_SA_8197F(x) | BIT_DDMACH2_SA_8197F(v)) /* 2 REG_DDMA_CH2DA_8197F */ #define BIT_SHIFT_DDMACH2_DA_8197F 0 #define BIT_MASK_DDMACH2_DA_8197F 0xffffffffL -#define BIT_DDMACH2_DA_8197F(x) (((x) & BIT_MASK_DDMACH2_DA_8197F) << BIT_SHIFT_DDMACH2_DA_8197F) -#define BITS_DDMACH2_DA_8197F (BIT_MASK_DDMACH2_DA_8197F << BIT_SHIFT_DDMACH2_DA_8197F) +#define BIT_DDMACH2_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH2_DA_8197F) << BIT_SHIFT_DDMACH2_DA_8197F) +#define BITS_DDMACH2_DA_8197F \ + (BIT_MASK_DDMACH2_DA_8197F << BIT_SHIFT_DDMACH2_DA_8197F) #define BIT_CLEAR_DDMACH2_DA_8197F(x) ((x) & (~BITS_DDMACH2_DA_8197F)) -#define BIT_GET_DDMACH2_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8197F) & BIT_MASK_DDMACH2_DA_8197F) -#define BIT_SET_DDMACH2_DA_8197F(x, v) (BIT_CLEAR_DDMACH2_DA_8197F(x) | BIT_DDMACH2_DA_8197F(v)) - +#define BIT_GET_DDMACH2_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA_8197F) & BIT_MASK_DDMACH2_DA_8197F) +#define BIT_SET_DDMACH2_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH2_DA_8197F(x) | BIT_DDMACH2_DA_8197F(v)) /* 2 REG_DDMA_CH2CTRL_8197F */ #define BIT_DDMACH2_OWN_8197F BIT(31) @@ -4654,34 +5839,43 @@ #define BIT_SHIFT_DDMACH2_DLEN_8197F 0 #define BIT_MASK_DDMACH2_DLEN_8197F 0x3ffff -#define BIT_DDMACH2_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH2_DLEN_8197F) << BIT_SHIFT_DDMACH2_DLEN_8197F) -#define BITS_DDMACH2_DLEN_8197F (BIT_MASK_DDMACH2_DLEN_8197F << BIT_SHIFT_DDMACH2_DLEN_8197F) +#define BIT_DDMACH2_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN_8197F) << BIT_SHIFT_DDMACH2_DLEN_8197F) +#define BITS_DDMACH2_DLEN_8197F \ + (BIT_MASK_DDMACH2_DLEN_8197F << BIT_SHIFT_DDMACH2_DLEN_8197F) #define BIT_CLEAR_DDMACH2_DLEN_8197F(x) ((x) & (~BITS_DDMACH2_DLEN_8197F)) -#define BIT_GET_DDMACH2_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8197F) & BIT_MASK_DDMACH2_DLEN_8197F) -#define BIT_SET_DDMACH2_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH2_DLEN_8197F(x) | BIT_DDMACH2_DLEN_8197F(v)) - +#define BIT_GET_DDMACH2_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN_8197F) & BIT_MASK_DDMACH2_DLEN_8197F) +#define BIT_SET_DDMACH2_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN_8197F(x) | BIT_DDMACH2_DLEN_8197F(v)) /* 2 REG_DDMA_CH3SA_8197F */ #define BIT_SHIFT_DDMACH3_SA_8197F 0 #define BIT_MASK_DDMACH3_SA_8197F 0xffffffffL -#define BIT_DDMACH3_SA_8197F(x) (((x) & BIT_MASK_DDMACH3_SA_8197F) << BIT_SHIFT_DDMACH3_SA_8197F) -#define BITS_DDMACH3_SA_8197F (BIT_MASK_DDMACH3_SA_8197F << BIT_SHIFT_DDMACH3_SA_8197F) +#define BIT_DDMACH3_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH3_SA_8197F) << BIT_SHIFT_DDMACH3_SA_8197F) +#define BITS_DDMACH3_SA_8197F \ + (BIT_MASK_DDMACH3_SA_8197F << BIT_SHIFT_DDMACH3_SA_8197F) #define BIT_CLEAR_DDMACH3_SA_8197F(x) ((x) & (~BITS_DDMACH3_SA_8197F)) -#define BIT_GET_DDMACH3_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8197F) & BIT_MASK_DDMACH3_SA_8197F) -#define BIT_SET_DDMACH3_SA_8197F(x, v) (BIT_CLEAR_DDMACH3_SA_8197F(x) | BIT_DDMACH3_SA_8197F(v)) - +#define BIT_GET_DDMACH3_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA_8197F) & BIT_MASK_DDMACH3_SA_8197F) +#define BIT_SET_DDMACH3_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH3_SA_8197F(x) | BIT_DDMACH3_SA_8197F(v)) /* 2 REG_DDMA_CH3DA_8197F */ #define BIT_SHIFT_DDMACH3_DA_8197F 0 #define BIT_MASK_DDMACH3_DA_8197F 0xffffffffL -#define BIT_DDMACH3_DA_8197F(x) (((x) & BIT_MASK_DDMACH3_DA_8197F) << BIT_SHIFT_DDMACH3_DA_8197F) -#define BITS_DDMACH3_DA_8197F (BIT_MASK_DDMACH3_DA_8197F << BIT_SHIFT_DDMACH3_DA_8197F) +#define BIT_DDMACH3_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH3_DA_8197F) << BIT_SHIFT_DDMACH3_DA_8197F) +#define BITS_DDMACH3_DA_8197F \ + (BIT_MASK_DDMACH3_DA_8197F << BIT_SHIFT_DDMACH3_DA_8197F) #define BIT_CLEAR_DDMACH3_DA_8197F(x) ((x) & (~BITS_DDMACH3_DA_8197F)) -#define BIT_GET_DDMACH3_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8197F) & BIT_MASK_DDMACH3_DA_8197F) -#define BIT_SET_DDMACH3_DA_8197F(x, v) (BIT_CLEAR_DDMACH3_DA_8197F(x) | BIT_DDMACH3_DA_8197F(v)) - +#define BIT_GET_DDMACH3_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA_8197F) & BIT_MASK_DDMACH3_DA_8197F) +#define BIT_SET_DDMACH3_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH3_DA_8197F(x) | BIT_DDMACH3_DA_8197F(v)) /* 2 REG_DDMA_CH3CTRL_8197F */ #define BIT_DDMACH3_OWN_8197F BIT(31) @@ -4694,34 +5888,43 @@ #define BIT_SHIFT_DDMACH3_DLEN_8197F 0 #define BIT_MASK_DDMACH3_DLEN_8197F 0x3ffff -#define BIT_DDMACH3_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH3_DLEN_8197F) << BIT_SHIFT_DDMACH3_DLEN_8197F) -#define BITS_DDMACH3_DLEN_8197F (BIT_MASK_DDMACH3_DLEN_8197F << BIT_SHIFT_DDMACH3_DLEN_8197F) +#define BIT_DDMACH3_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN_8197F) << BIT_SHIFT_DDMACH3_DLEN_8197F) +#define BITS_DDMACH3_DLEN_8197F \ + (BIT_MASK_DDMACH3_DLEN_8197F << BIT_SHIFT_DDMACH3_DLEN_8197F) #define BIT_CLEAR_DDMACH3_DLEN_8197F(x) ((x) & (~BITS_DDMACH3_DLEN_8197F)) -#define BIT_GET_DDMACH3_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8197F) & BIT_MASK_DDMACH3_DLEN_8197F) -#define BIT_SET_DDMACH3_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH3_DLEN_8197F(x) | BIT_DDMACH3_DLEN_8197F(v)) - +#define BIT_GET_DDMACH3_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN_8197F) & BIT_MASK_DDMACH3_DLEN_8197F) +#define BIT_SET_DDMACH3_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN_8197F(x) | BIT_DDMACH3_DLEN_8197F(v)) /* 2 REG_DDMA_CH4SA_8197F */ #define BIT_SHIFT_DDMACH4_SA_8197F 0 #define BIT_MASK_DDMACH4_SA_8197F 0xffffffffL -#define BIT_DDMACH4_SA_8197F(x) (((x) & BIT_MASK_DDMACH4_SA_8197F) << BIT_SHIFT_DDMACH4_SA_8197F) -#define BITS_DDMACH4_SA_8197F (BIT_MASK_DDMACH4_SA_8197F << BIT_SHIFT_DDMACH4_SA_8197F) +#define BIT_DDMACH4_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH4_SA_8197F) << BIT_SHIFT_DDMACH4_SA_8197F) +#define BITS_DDMACH4_SA_8197F \ + (BIT_MASK_DDMACH4_SA_8197F << BIT_SHIFT_DDMACH4_SA_8197F) #define BIT_CLEAR_DDMACH4_SA_8197F(x) ((x) & (~BITS_DDMACH4_SA_8197F)) -#define BIT_GET_DDMACH4_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8197F) & BIT_MASK_DDMACH4_SA_8197F) -#define BIT_SET_DDMACH4_SA_8197F(x, v) (BIT_CLEAR_DDMACH4_SA_8197F(x) | BIT_DDMACH4_SA_8197F(v)) - +#define BIT_GET_DDMACH4_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA_8197F) & BIT_MASK_DDMACH4_SA_8197F) +#define BIT_SET_DDMACH4_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH4_SA_8197F(x) | BIT_DDMACH4_SA_8197F(v)) /* 2 REG_DDMA_CH4DA_8197F */ #define BIT_SHIFT_DDMACH4_DA_8197F 0 #define BIT_MASK_DDMACH4_DA_8197F 0xffffffffL -#define BIT_DDMACH4_DA_8197F(x) (((x) & BIT_MASK_DDMACH4_DA_8197F) << BIT_SHIFT_DDMACH4_DA_8197F) -#define BITS_DDMACH4_DA_8197F (BIT_MASK_DDMACH4_DA_8197F << BIT_SHIFT_DDMACH4_DA_8197F) +#define BIT_DDMACH4_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH4_DA_8197F) << BIT_SHIFT_DDMACH4_DA_8197F) +#define BITS_DDMACH4_DA_8197F \ + (BIT_MASK_DDMACH4_DA_8197F << BIT_SHIFT_DDMACH4_DA_8197F) #define BIT_CLEAR_DDMACH4_DA_8197F(x) ((x) & (~BITS_DDMACH4_DA_8197F)) -#define BIT_GET_DDMACH4_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8197F) & BIT_MASK_DDMACH4_DA_8197F) -#define BIT_SET_DDMACH4_DA_8197F(x, v) (BIT_CLEAR_DDMACH4_DA_8197F(x) | BIT_DDMACH4_DA_8197F(v)) - +#define BIT_GET_DDMACH4_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA_8197F) & BIT_MASK_DDMACH4_DA_8197F) +#define BIT_SET_DDMACH4_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH4_DA_8197F(x) | BIT_DDMACH4_DA_8197F(v)) /* 2 REG_DDMA_CH4CTRL_8197F */ #define BIT_DDMACH4_OWN_8197F BIT(31) @@ -4734,34 +5937,43 @@ #define BIT_SHIFT_DDMACH4_DLEN_8197F 0 #define BIT_MASK_DDMACH4_DLEN_8197F 0x3ffff -#define BIT_DDMACH4_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH4_DLEN_8197F) << BIT_SHIFT_DDMACH4_DLEN_8197F) -#define BITS_DDMACH4_DLEN_8197F (BIT_MASK_DDMACH4_DLEN_8197F << BIT_SHIFT_DDMACH4_DLEN_8197F) +#define BIT_DDMACH4_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN_8197F) << BIT_SHIFT_DDMACH4_DLEN_8197F) +#define BITS_DDMACH4_DLEN_8197F \ + (BIT_MASK_DDMACH4_DLEN_8197F << BIT_SHIFT_DDMACH4_DLEN_8197F) #define BIT_CLEAR_DDMACH4_DLEN_8197F(x) ((x) & (~BITS_DDMACH4_DLEN_8197F)) -#define BIT_GET_DDMACH4_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8197F) & BIT_MASK_DDMACH4_DLEN_8197F) -#define BIT_SET_DDMACH4_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH4_DLEN_8197F(x) | BIT_DDMACH4_DLEN_8197F(v)) - +#define BIT_GET_DDMACH4_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN_8197F) & BIT_MASK_DDMACH4_DLEN_8197F) +#define BIT_SET_DDMACH4_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN_8197F(x) | BIT_DDMACH4_DLEN_8197F(v)) /* 2 REG_DDMA_CH5SA_8197F */ #define BIT_SHIFT_DDMACH5_SA_8197F 0 #define BIT_MASK_DDMACH5_SA_8197F 0xffffffffL -#define BIT_DDMACH5_SA_8197F(x) (((x) & BIT_MASK_DDMACH5_SA_8197F) << BIT_SHIFT_DDMACH5_SA_8197F) -#define BITS_DDMACH5_SA_8197F (BIT_MASK_DDMACH5_SA_8197F << BIT_SHIFT_DDMACH5_SA_8197F) +#define BIT_DDMACH5_SA_8197F(x) \ + (((x) & BIT_MASK_DDMACH5_SA_8197F) << BIT_SHIFT_DDMACH5_SA_8197F) +#define BITS_DDMACH5_SA_8197F \ + (BIT_MASK_DDMACH5_SA_8197F << BIT_SHIFT_DDMACH5_SA_8197F) #define BIT_CLEAR_DDMACH5_SA_8197F(x) ((x) & (~BITS_DDMACH5_SA_8197F)) -#define BIT_GET_DDMACH5_SA_8197F(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8197F) & BIT_MASK_DDMACH5_SA_8197F) -#define BIT_SET_DDMACH5_SA_8197F(x, v) (BIT_CLEAR_DDMACH5_SA_8197F(x) | BIT_DDMACH5_SA_8197F(v)) - +#define BIT_GET_DDMACH5_SA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA_8197F) & BIT_MASK_DDMACH5_SA_8197F) +#define BIT_SET_DDMACH5_SA_8197F(x, v) \ + (BIT_CLEAR_DDMACH5_SA_8197F(x) | BIT_DDMACH5_SA_8197F(v)) /* 2 REG_DDMA_CH5DA_8197F */ #define BIT_SHIFT_DDMACH5_DA_8197F 0 #define BIT_MASK_DDMACH5_DA_8197F 0xffffffffL -#define BIT_DDMACH5_DA_8197F(x) (((x) & BIT_MASK_DDMACH5_DA_8197F) << BIT_SHIFT_DDMACH5_DA_8197F) -#define BITS_DDMACH5_DA_8197F (BIT_MASK_DDMACH5_DA_8197F << BIT_SHIFT_DDMACH5_DA_8197F) +#define BIT_DDMACH5_DA_8197F(x) \ + (((x) & BIT_MASK_DDMACH5_DA_8197F) << BIT_SHIFT_DDMACH5_DA_8197F) +#define BITS_DDMACH5_DA_8197F \ + (BIT_MASK_DDMACH5_DA_8197F << BIT_SHIFT_DDMACH5_DA_8197F) #define BIT_CLEAR_DDMACH5_DA_8197F(x) ((x) & (~BITS_DDMACH5_DA_8197F)) -#define BIT_GET_DDMACH5_DA_8197F(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8197F) & BIT_MASK_DDMACH5_DA_8197F) -#define BIT_SET_DDMACH5_DA_8197F(x, v) (BIT_CLEAR_DDMACH5_DA_8197F(x) | BIT_DDMACH5_DA_8197F(v)) - +#define BIT_GET_DDMACH5_DA_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA_8197F) & BIT_MASK_DDMACH5_DA_8197F) +#define BIT_SET_DDMACH5_DA_8197F(x, v) \ + (BIT_CLEAR_DDMACH5_DA_8197F(x) | BIT_DDMACH5_DA_8197F(v)) /* 2 REG_REG_DDMA_CH5CTRL_8197F */ #define BIT_DDMACH5_OWN_8197F BIT(31) @@ -4774,12 +5986,15 @@ #define BIT_SHIFT_DDMACH5_DLEN_8197F 0 #define BIT_MASK_DDMACH5_DLEN_8197F 0x3ffff -#define BIT_DDMACH5_DLEN_8197F(x) (((x) & BIT_MASK_DDMACH5_DLEN_8197F) << BIT_SHIFT_DDMACH5_DLEN_8197F) -#define BITS_DDMACH5_DLEN_8197F (BIT_MASK_DDMACH5_DLEN_8197F << BIT_SHIFT_DDMACH5_DLEN_8197F) +#define BIT_DDMACH5_DLEN_8197F(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN_8197F) << BIT_SHIFT_DDMACH5_DLEN_8197F) +#define BITS_DDMACH5_DLEN_8197F \ + (BIT_MASK_DDMACH5_DLEN_8197F << BIT_SHIFT_DDMACH5_DLEN_8197F) #define BIT_CLEAR_DDMACH5_DLEN_8197F(x) ((x) & (~BITS_DDMACH5_DLEN_8197F)) -#define BIT_GET_DDMACH5_DLEN_8197F(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8197F) & BIT_MASK_DDMACH5_DLEN_8197F) -#define BIT_SET_DDMACH5_DLEN_8197F(x, v) (BIT_CLEAR_DDMACH5_DLEN_8197F(x) | BIT_DDMACH5_DLEN_8197F(v)) - +#define BIT_GET_DDMACH5_DLEN_8197F(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN_8197F) & BIT_MASK_DDMACH5_DLEN_8197F) +#define BIT_SET_DDMACH5_DLEN_8197F(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN_8197F(x) | BIT_DDMACH5_DLEN_8197F(v)) /* 2 REG_DDMA_INT_MSK_8197F */ #define BIT_DDMACH5_MSK_8197F BIT(5) @@ -4801,12 +6016,15 @@ #define BIT_SHIFT_IDDMA0_CHKSUM_8197F 0 #define BIT_MASK_IDDMA0_CHKSUM_8197F 0xffff -#define BIT_IDDMA0_CHKSUM_8197F(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8197F) << BIT_SHIFT_IDDMA0_CHKSUM_8197F) -#define BITS_IDDMA0_CHKSUM_8197F (BIT_MASK_IDDMA0_CHKSUM_8197F << BIT_SHIFT_IDDMA0_CHKSUM_8197F) +#define BIT_IDDMA0_CHKSUM_8197F(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM_8197F) << BIT_SHIFT_IDDMA0_CHKSUM_8197F) +#define BITS_IDDMA0_CHKSUM_8197F \ + (BIT_MASK_IDDMA0_CHKSUM_8197F << BIT_SHIFT_IDDMA0_CHKSUM_8197F) #define BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) ((x) & (~BITS_IDDMA0_CHKSUM_8197F)) -#define BIT_GET_IDDMA0_CHKSUM_8197F(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8197F) & BIT_MASK_IDDMA0_CHKSUM_8197F) -#define BIT_SET_IDDMA0_CHKSUM_8197F(x, v) (BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) | BIT_IDDMA0_CHKSUM_8197F(v)) - +#define BIT_GET_IDDMA0_CHKSUM_8197F(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8197F) & BIT_MASK_IDDMA0_CHKSUM_8197F) +#define BIT_SET_IDDMA0_CHKSUM_8197F(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) | BIT_IDDMA0_CHKSUM_8197F(v)) /* 2 REG_DDMA_MONITOR_8197F */ #define BIT_IDDMA0_PERMU_UNDERFLOW_8197F BIT(14) @@ -4826,21 +6044,29 @@ #define BIT_SHIFT_HCI_MAX_RXDMA_8197F 28 #define BIT_MASK_HCI_MAX_RXDMA_8197F 0x7 -#define BIT_HCI_MAX_RXDMA_8197F(x) (((x) & BIT_MASK_HCI_MAX_RXDMA_8197F) << BIT_SHIFT_HCI_MAX_RXDMA_8197F) -#define BITS_HCI_MAX_RXDMA_8197F (BIT_MASK_HCI_MAX_RXDMA_8197F << BIT_SHIFT_HCI_MAX_RXDMA_8197F) +#define BIT_HCI_MAX_RXDMA_8197F(x) \ + (((x) & BIT_MASK_HCI_MAX_RXDMA_8197F) << BIT_SHIFT_HCI_MAX_RXDMA_8197F) +#define BITS_HCI_MAX_RXDMA_8197F \ + (BIT_MASK_HCI_MAX_RXDMA_8197F << BIT_SHIFT_HCI_MAX_RXDMA_8197F) #define BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_RXDMA_8197F)) -#define BIT_GET_HCI_MAX_RXDMA_8197F(x) (((x) >> BIT_SHIFT_HCI_MAX_RXDMA_8197F) & BIT_MASK_HCI_MAX_RXDMA_8197F) -#define BIT_SET_HCI_MAX_RXDMA_8197F(x, v) (BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) | BIT_HCI_MAX_RXDMA_8197F(v)) +#define BIT_GET_HCI_MAX_RXDMA_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_MAX_RXDMA_8197F) & BIT_MASK_HCI_MAX_RXDMA_8197F) +#define BIT_SET_HCI_MAX_RXDMA_8197F(x, v) \ + (BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) | BIT_HCI_MAX_RXDMA_8197F(v)) #define BIT_MULRW_8197F BIT(27) #define BIT_SHIFT_HCI_MAX_TXDMA_8197F 24 #define BIT_MASK_HCI_MAX_TXDMA_8197F 0x7 -#define BIT_HCI_MAX_TXDMA_8197F(x) (((x) & BIT_MASK_HCI_MAX_TXDMA_8197F) << BIT_SHIFT_HCI_MAX_TXDMA_8197F) -#define BITS_HCI_MAX_TXDMA_8197F (BIT_MASK_HCI_MAX_TXDMA_8197F << BIT_SHIFT_HCI_MAX_TXDMA_8197F) +#define BIT_HCI_MAX_TXDMA_8197F(x) \ + (((x) & BIT_MASK_HCI_MAX_TXDMA_8197F) << BIT_SHIFT_HCI_MAX_TXDMA_8197F) +#define BITS_HCI_MAX_TXDMA_8197F \ + (BIT_MASK_HCI_MAX_TXDMA_8197F << BIT_SHIFT_HCI_MAX_TXDMA_8197F) #define BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_TXDMA_8197F)) -#define BIT_GET_HCI_MAX_TXDMA_8197F(x) (((x) >> BIT_SHIFT_HCI_MAX_TXDMA_8197F) & BIT_MASK_HCI_MAX_TXDMA_8197F) -#define BIT_SET_HCI_MAX_TXDMA_8197F(x, v) (BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) | BIT_HCI_MAX_TXDMA_8197F(v)) +#define BIT_GET_HCI_MAX_TXDMA_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_MAX_TXDMA_8197F) & BIT_MASK_HCI_MAX_TXDMA_8197F) +#define BIT_SET_HCI_MAX_TXDMA_8197F(x, v) \ + (BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) | BIT_HCI_MAX_TXDMA_8197F(v)) #define BIT_EN_CPL_TIMEOUT_PS_8197F BIT(22) #define BIT_REG_TXDMA_FAIL_PS_8197F BIT(21) @@ -4870,528 +6096,729 @@ #define BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F 28 #define BIT_MASK_TXTTIMER_MATCH_NUM_8197F 0xf -#define BIT_TXTTIMER_MATCH_NUM_8197F(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8197F) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) -#define BITS_TXTTIMER_MATCH_NUM_8197F (BIT_MASK_TXTTIMER_MATCH_NUM_8197F << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) -#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) ((x) & (~BITS_TXTTIMER_MATCH_NUM_8197F)) -#define BIT_GET_TXTTIMER_MATCH_NUM_8197F(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) & BIT_MASK_TXTTIMER_MATCH_NUM_8197F) -#define BIT_SET_TXTTIMER_MATCH_NUM_8197F(x, v) (BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) | BIT_TXTTIMER_MATCH_NUM_8197F(v)) - +#define BIT_TXTTIMER_MATCH_NUM_8197F(x) \ + (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8197F) \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) +#define BITS_TXTTIMER_MATCH_NUM_8197F \ + (BIT_MASK_TXTTIMER_MATCH_NUM_8197F \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) +#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) \ + ((x) & (~BITS_TXTTIMER_MATCH_NUM_8197F)) +#define BIT_GET_TXTTIMER_MATCH_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) & \ + BIT_MASK_TXTTIMER_MATCH_NUM_8197F) +#define BIT_SET_TXTTIMER_MATCH_NUM_8197F(x, v) \ + (BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) | \ + BIT_TXTTIMER_MATCH_NUM_8197F(v)) #define BIT_SHIFT_TXPKT_NUM_MATCH_8197F 24 #define BIT_MASK_TXPKT_NUM_MATCH_8197F 0xf -#define BIT_TXPKT_NUM_MATCH_8197F(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8197F) << BIT_SHIFT_TXPKT_NUM_MATCH_8197F) -#define BITS_TXPKT_NUM_MATCH_8197F (BIT_MASK_TXPKT_NUM_MATCH_8197F << BIT_SHIFT_TXPKT_NUM_MATCH_8197F) +#define BIT_TXPKT_NUM_MATCH_8197F(x) \ + (((x) & BIT_MASK_TXPKT_NUM_MATCH_8197F) \ + << BIT_SHIFT_TXPKT_NUM_MATCH_8197F) +#define BITS_TXPKT_NUM_MATCH_8197F \ + (BIT_MASK_TXPKT_NUM_MATCH_8197F << BIT_SHIFT_TXPKT_NUM_MATCH_8197F) #define BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8197F)) -#define BIT_GET_TXPKT_NUM_MATCH_8197F(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8197F) & BIT_MASK_TXPKT_NUM_MATCH_8197F) -#define BIT_SET_TXPKT_NUM_MATCH_8197F(x, v) (BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) | BIT_TXPKT_NUM_MATCH_8197F(v)) - +#define BIT_GET_TXPKT_NUM_MATCH_8197F(x) \ + (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8197F) & \ + BIT_MASK_TXPKT_NUM_MATCH_8197F) +#define BIT_SET_TXPKT_NUM_MATCH_8197F(x, v) \ + (BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) | BIT_TXPKT_NUM_MATCH_8197F(v)) #define BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F 20 #define BIT_MASK_RXTTIMER_MATCH_NUM_8197F 0xf -#define BIT_RXTTIMER_MATCH_NUM_8197F(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8197F) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) -#define BITS_RXTTIMER_MATCH_NUM_8197F (BIT_MASK_RXTTIMER_MATCH_NUM_8197F << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) -#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) ((x) & (~BITS_RXTTIMER_MATCH_NUM_8197F)) -#define BIT_GET_RXTTIMER_MATCH_NUM_8197F(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) & BIT_MASK_RXTTIMER_MATCH_NUM_8197F) -#define BIT_SET_RXTTIMER_MATCH_NUM_8197F(x, v) (BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) | BIT_RXTTIMER_MATCH_NUM_8197F(v)) - +#define BIT_RXTTIMER_MATCH_NUM_8197F(x) \ + (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8197F) \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) +#define BITS_RXTTIMER_MATCH_NUM_8197F \ + (BIT_MASK_RXTTIMER_MATCH_NUM_8197F \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) +#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) \ + ((x) & (~BITS_RXTTIMER_MATCH_NUM_8197F)) +#define BIT_GET_RXTTIMER_MATCH_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) & \ + BIT_MASK_RXTTIMER_MATCH_NUM_8197F) +#define BIT_SET_RXTTIMER_MATCH_NUM_8197F(x, v) \ + (BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) | \ + BIT_RXTTIMER_MATCH_NUM_8197F(v)) #define BIT_SHIFT_RXPKT_NUM_MATCH_8197F 16 #define BIT_MASK_RXPKT_NUM_MATCH_8197F 0xf -#define BIT_RXPKT_NUM_MATCH_8197F(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8197F) << BIT_SHIFT_RXPKT_NUM_MATCH_8197F) -#define BITS_RXPKT_NUM_MATCH_8197F (BIT_MASK_RXPKT_NUM_MATCH_8197F << BIT_SHIFT_RXPKT_NUM_MATCH_8197F) +#define BIT_RXPKT_NUM_MATCH_8197F(x) \ + (((x) & BIT_MASK_RXPKT_NUM_MATCH_8197F) \ + << BIT_SHIFT_RXPKT_NUM_MATCH_8197F) +#define BITS_RXPKT_NUM_MATCH_8197F \ + (BIT_MASK_RXPKT_NUM_MATCH_8197F << BIT_SHIFT_RXPKT_NUM_MATCH_8197F) #define BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8197F)) -#define BIT_GET_RXPKT_NUM_MATCH_8197F(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8197F) & BIT_MASK_RXPKT_NUM_MATCH_8197F) -#define BIT_SET_RXPKT_NUM_MATCH_8197F(x, v) (BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) | BIT_RXPKT_NUM_MATCH_8197F(v)) - +#define BIT_GET_RXPKT_NUM_MATCH_8197F(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8197F) & \ + BIT_MASK_RXPKT_NUM_MATCH_8197F) +#define BIT_SET_RXPKT_NUM_MATCH_8197F(x, v) \ + (BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) | BIT_RXPKT_NUM_MATCH_8197F(v)) #define BIT_SHIFT_MIGRATE_TIMER_8197F 0 #define BIT_MASK_MIGRATE_TIMER_8197F 0xffff -#define BIT_MIGRATE_TIMER_8197F(x) (((x) & BIT_MASK_MIGRATE_TIMER_8197F) << BIT_SHIFT_MIGRATE_TIMER_8197F) -#define BITS_MIGRATE_TIMER_8197F (BIT_MASK_MIGRATE_TIMER_8197F << BIT_SHIFT_MIGRATE_TIMER_8197F) +#define BIT_MIGRATE_TIMER_8197F(x) \ + (((x) & BIT_MASK_MIGRATE_TIMER_8197F) << BIT_SHIFT_MIGRATE_TIMER_8197F) +#define BITS_MIGRATE_TIMER_8197F \ + (BIT_MASK_MIGRATE_TIMER_8197F << BIT_SHIFT_MIGRATE_TIMER_8197F) #define BIT_CLEAR_MIGRATE_TIMER_8197F(x) ((x) & (~BITS_MIGRATE_TIMER_8197F)) -#define BIT_GET_MIGRATE_TIMER_8197F(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8197F) & BIT_MASK_MIGRATE_TIMER_8197F) -#define BIT_SET_MIGRATE_TIMER_8197F(x, v) (BIT_CLEAR_MIGRATE_TIMER_8197F(x) | BIT_MIGRATE_TIMER_8197F(v)) - +#define BIT_GET_MIGRATE_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_MIGRATE_TIMER_8197F) & BIT_MASK_MIGRATE_TIMER_8197F) +#define BIT_SET_MIGRATE_TIMER_8197F(x, v) \ + (BIT_CLEAR_MIGRATE_TIMER_8197F(x) | BIT_MIGRATE_TIMER_8197F(v)) /* 2 REG_BCNQ_TXBD_DESA_8197F */ #define BIT_SHIFT_BCNQ_TXBD_DESA_8197F 0 #define BIT_MASK_BCNQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_BCNQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8197F) << BIT_SHIFT_BCNQ_TXBD_DESA_8197F) -#define BITS_BCNQ_TXBD_DESA_8197F (BIT_MASK_BCNQ_TXBD_DESA_8197F << BIT_SHIFT_BCNQ_TXBD_DESA_8197F) +#define BIT_BCNQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_BCNQ_TXBD_DESA_8197F) \ + << BIT_SHIFT_BCNQ_TXBD_DESA_8197F) +#define BITS_BCNQ_TXBD_DESA_8197F \ + (BIT_MASK_BCNQ_TXBD_DESA_8197F << BIT_SHIFT_BCNQ_TXBD_DESA_8197F) #define BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8197F)) -#define BIT_GET_BCNQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8197F) & BIT_MASK_BCNQ_TXBD_DESA_8197F) -#define BIT_SET_BCNQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) | BIT_BCNQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_BCNQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8197F) & \ + BIT_MASK_BCNQ_TXBD_DESA_8197F) +#define BIT_SET_BCNQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) | BIT_BCNQ_TXBD_DESA_8197F(v)) /* 2 REG_MGQ_TXBD_DESA_8197F */ #define BIT_SHIFT_MGQ_TXBD_DESA_8197F 0 #define BIT_MASK_MGQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_MGQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8197F) << BIT_SHIFT_MGQ_TXBD_DESA_8197F) -#define BITS_MGQ_TXBD_DESA_8197F (BIT_MASK_MGQ_TXBD_DESA_8197F << BIT_SHIFT_MGQ_TXBD_DESA_8197F) +#define BIT_MGQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_MGQ_TXBD_DESA_8197F) << BIT_SHIFT_MGQ_TXBD_DESA_8197F) +#define BITS_MGQ_TXBD_DESA_8197F \ + (BIT_MASK_MGQ_TXBD_DESA_8197F << BIT_SHIFT_MGQ_TXBD_DESA_8197F) #define BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) ((x) & (~BITS_MGQ_TXBD_DESA_8197F)) -#define BIT_GET_MGQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8197F) & BIT_MASK_MGQ_TXBD_DESA_8197F) -#define BIT_SET_MGQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) | BIT_MGQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_MGQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8197F) & BIT_MASK_MGQ_TXBD_DESA_8197F) +#define BIT_SET_MGQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) | BIT_MGQ_TXBD_DESA_8197F(v)) /* 2 REG_VOQ_TXBD_DESA_8197F */ #define BIT_SHIFT_VOQ_TXBD_DESA_8197F 0 #define BIT_MASK_VOQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_VOQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8197F) << BIT_SHIFT_VOQ_TXBD_DESA_8197F) -#define BITS_VOQ_TXBD_DESA_8197F (BIT_MASK_VOQ_TXBD_DESA_8197F << BIT_SHIFT_VOQ_TXBD_DESA_8197F) +#define BIT_VOQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_VOQ_TXBD_DESA_8197F) << BIT_SHIFT_VOQ_TXBD_DESA_8197F) +#define BITS_VOQ_TXBD_DESA_8197F \ + (BIT_MASK_VOQ_TXBD_DESA_8197F << BIT_SHIFT_VOQ_TXBD_DESA_8197F) #define BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VOQ_TXBD_DESA_8197F)) -#define BIT_GET_VOQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8197F) & BIT_MASK_VOQ_TXBD_DESA_8197F) -#define BIT_SET_VOQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) | BIT_VOQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_VOQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8197F) & BIT_MASK_VOQ_TXBD_DESA_8197F) +#define BIT_SET_VOQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) | BIT_VOQ_TXBD_DESA_8197F(v)) /* 2 REG_VIQ_TXBD_DESA_8197F */ #define BIT_SHIFT_VIQ_TXBD_DESA_8197F 0 #define BIT_MASK_VIQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_VIQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8197F) << BIT_SHIFT_VIQ_TXBD_DESA_8197F) -#define BITS_VIQ_TXBD_DESA_8197F (BIT_MASK_VIQ_TXBD_DESA_8197F << BIT_SHIFT_VIQ_TXBD_DESA_8197F) +#define BIT_VIQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_VIQ_TXBD_DESA_8197F) << BIT_SHIFT_VIQ_TXBD_DESA_8197F) +#define BITS_VIQ_TXBD_DESA_8197F \ + (BIT_MASK_VIQ_TXBD_DESA_8197F << BIT_SHIFT_VIQ_TXBD_DESA_8197F) #define BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VIQ_TXBD_DESA_8197F)) -#define BIT_GET_VIQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8197F) & BIT_MASK_VIQ_TXBD_DESA_8197F) -#define BIT_SET_VIQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) | BIT_VIQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_VIQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8197F) & BIT_MASK_VIQ_TXBD_DESA_8197F) +#define BIT_SET_VIQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) | BIT_VIQ_TXBD_DESA_8197F(v)) /* 2 REG_BEQ_TXBD_DESA_8197F */ #define BIT_SHIFT_BEQ_TXBD_DESA_8197F 0 #define BIT_MASK_BEQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_BEQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8197F) << BIT_SHIFT_BEQ_TXBD_DESA_8197F) -#define BITS_BEQ_TXBD_DESA_8197F (BIT_MASK_BEQ_TXBD_DESA_8197F << BIT_SHIFT_BEQ_TXBD_DESA_8197F) +#define BIT_BEQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_BEQ_TXBD_DESA_8197F) << BIT_SHIFT_BEQ_TXBD_DESA_8197F) +#define BITS_BEQ_TXBD_DESA_8197F \ + (BIT_MASK_BEQ_TXBD_DESA_8197F << BIT_SHIFT_BEQ_TXBD_DESA_8197F) #define BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BEQ_TXBD_DESA_8197F)) -#define BIT_GET_BEQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8197F) & BIT_MASK_BEQ_TXBD_DESA_8197F) -#define BIT_SET_BEQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) | BIT_BEQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_BEQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8197F) & BIT_MASK_BEQ_TXBD_DESA_8197F) +#define BIT_SET_BEQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) | BIT_BEQ_TXBD_DESA_8197F(v)) /* 2 REG_BKQ_TXBD_DESA_8197F */ #define BIT_SHIFT_BKQ_TXBD_DESA_8197F 0 #define BIT_MASK_BKQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_BKQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8197F) << BIT_SHIFT_BKQ_TXBD_DESA_8197F) -#define BITS_BKQ_TXBD_DESA_8197F (BIT_MASK_BKQ_TXBD_DESA_8197F << BIT_SHIFT_BKQ_TXBD_DESA_8197F) +#define BIT_BKQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_BKQ_TXBD_DESA_8197F) << BIT_SHIFT_BKQ_TXBD_DESA_8197F) +#define BITS_BKQ_TXBD_DESA_8197F \ + (BIT_MASK_BKQ_TXBD_DESA_8197F << BIT_SHIFT_BKQ_TXBD_DESA_8197F) #define BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BKQ_TXBD_DESA_8197F)) -#define BIT_GET_BKQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8197F) & BIT_MASK_BKQ_TXBD_DESA_8197F) -#define BIT_SET_BKQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) | BIT_BKQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_BKQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8197F) & BIT_MASK_BKQ_TXBD_DESA_8197F) +#define BIT_SET_BKQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) | BIT_BKQ_TXBD_DESA_8197F(v)) /* 2 REG_RXQ_RXBD_DESA_8197F */ #define BIT_SHIFT_RXQ_RXBD_DESA_8197F 0 #define BIT_MASK_RXQ_RXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_RXQ_RXBD_DESA_8197F(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8197F) << BIT_SHIFT_RXQ_RXBD_DESA_8197F) -#define BITS_RXQ_RXBD_DESA_8197F (BIT_MASK_RXQ_RXBD_DESA_8197F << BIT_SHIFT_RXQ_RXBD_DESA_8197F) +#define BIT_RXQ_RXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_RXQ_RXBD_DESA_8197F) << BIT_SHIFT_RXQ_RXBD_DESA_8197F) +#define BITS_RXQ_RXBD_DESA_8197F \ + (BIT_MASK_RXQ_RXBD_DESA_8197F << BIT_SHIFT_RXQ_RXBD_DESA_8197F) #define BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) ((x) & (~BITS_RXQ_RXBD_DESA_8197F)) -#define BIT_GET_RXQ_RXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8197F) & BIT_MASK_RXQ_RXBD_DESA_8197F) -#define BIT_SET_RXQ_RXBD_DESA_8197F(x, v) (BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) | BIT_RXQ_RXBD_DESA_8197F(v)) - +#define BIT_GET_RXQ_RXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8197F) & BIT_MASK_RXQ_RXBD_DESA_8197F) +#define BIT_SET_RXQ_RXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) | BIT_RXQ_RXBD_DESA_8197F(v)) /* 2 REG_HI0Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI0Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI0Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI0Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8197F) << BIT_SHIFT_HI0Q_TXBD_DESA_8197F) -#define BITS_HI0Q_TXBD_DESA_8197F (BIT_MASK_HI0Q_TXBD_DESA_8197F << BIT_SHIFT_HI0Q_TXBD_DESA_8197F) +#define BIT_HI0Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_8197F) +#define BITS_HI0Q_TXBD_DESA_8197F \ + (BIT_MASK_HI0Q_TXBD_DESA_8197F << BIT_SHIFT_HI0Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8197F)) -#define BIT_GET_HI0Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8197F) & BIT_MASK_HI0Q_TXBD_DESA_8197F) -#define BIT_SET_HI0Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) | BIT_HI0Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI0Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI0Q_TXBD_DESA_8197F) +#define BIT_SET_HI0Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) | BIT_HI0Q_TXBD_DESA_8197F(v)) /* 2 REG_HI1Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI1Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI1Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI1Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8197F) << BIT_SHIFT_HI1Q_TXBD_DESA_8197F) -#define BITS_HI1Q_TXBD_DESA_8197F (BIT_MASK_HI1Q_TXBD_DESA_8197F << BIT_SHIFT_HI1Q_TXBD_DESA_8197F) +#define BIT_HI1Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_8197F) +#define BITS_HI1Q_TXBD_DESA_8197F \ + (BIT_MASK_HI1Q_TXBD_DESA_8197F << BIT_SHIFT_HI1Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8197F)) -#define BIT_GET_HI1Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8197F) & BIT_MASK_HI1Q_TXBD_DESA_8197F) -#define BIT_SET_HI1Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) | BIT_HI1Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI1Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI1Q_TXBD_DESA_8197F) +#define BIT_SET_HI1Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) | BIT_HI1Q_TXBD_DESA_8197F(v)) /* 2 REG_HI2Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI2Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI2Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI2Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8197F) << BIT_SHIFT_HI2Q_TXBD_DESA_8197F) -#define BITS_HI2Q_TXBD_DESA_8197F (BIT_MASK_HI2Q_TXBD_DESA_8197F << BIT_SHIFT_HI2Q_TXBD_DESA_8197F) +#define BIT_HI2Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_8197F) +#define BITS_HI2Q_TXBD_DESA_8197F \ + (BIT_MASK_HI2Q_TXBD_DESA_8197F << BIT_SHIFT_HI2Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8197F)) -#define BIT_GET_HI2Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8197F) & BIT_MASK_HI2Q_TXBD_DESA_8197F) -#define BIT_SET_HI2Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) | BIT_HI2Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI2Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI2Q_TXBD_DESA_8197F) +#define BIT_SET_HI2Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) | BIT_HI2Q_TXBD_DESA_8197F(v)) /* 2 REG_HI3Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI3Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI3Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI3Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8197F) << BIT_SHIFT_HI3Q_TXBD_DESA_8197F) -#define BITS_HI3Q_TXBD_DESA_8197F (BIT_MASK_HI3Q_TXBD_DESA_8197F << BIT_SHIFT_HI3Q_TXBD_DESA_8197F) +#define BIT_HI3Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_8197F) +#define BITS_HI3Q_TXBD_DESA_8197F \ + (BIT_MASK_HI3Q_TXBD_DESA_8197F << BIT_SHIFT_HI3Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8197F)) -#define BIT_GET_HI3Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8197F) & BIT_MASK_HI3Q_TXBD_DESA_8197F) -#define BIT_SET_HI3Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) | BIT_HI3Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI3Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI3Q_TXBD_DESA_8197F) +#define BIT_SET_HI3Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) | BIT_HI3Q_TXBD_DESA_8197F(v)) /* 2 REG_HI4Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI4Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI4Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI4Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8197F) << BIT_SHIFT_HI4Q_TXBD_DESA_8197F) -#define BITS_HI4Q_TXBD_DESA_8197F (BIT_MASK_HI4Q_TXBD_DESA_8197F << BIT_SHIFT_HI4Q_TXBD_DESA_8197F) +#define BIT_HI4Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_8197F) +#define BITS_HI4Q_TXBD_DESA_8197F \ + (BIT_MASK_HI4Q_TXBD_DESA_8197F << BIT_SHIFT_HI4Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8197F)) -#define BIT_GET_HI4Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8197F) & BIT_MASK_HI4Q_TXBD_DESA_8197F) -#define BIT_SET_HI4Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) | BIT_HI4Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI4Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI4Q_TXBD_DESA_8197F) +#define BIT_SET_HI4Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) | BIT_HI4Q_TXBD_DESA_8197F(v)) /* 2 REG_HI5Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI5Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI5Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI5Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8197F) << BIT_SHIFT_HI5Q_TXBD_DESA_8197F) -#define BITS_HI5Q_TXBD_DESA_8197F (BIT_MASK_HI5Q_TXBD_DESA_8197F << BIT_SHIFT_HI5Q_TXBD_DESA_8197F) +#define BIT_HI5Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_8197F) +#define BITS_HI5Q_TXBD_DESA_8197F \ + (BIT_MASK_HI5Q_TXBD_DESA_8197F << BIT_SHIFT_HI5Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8197F)) -#define BIT_GET_HI5Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8197F) & BIT_MASK_HI5Q_TXBD_DESA_8197F) -#define BIT_SET_HI5Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) | BIT_HI5Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI5Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI5Q_TXBD_DESA_8197F) +#define BIT_SET_HI5Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) | BIT_HI5Q_TXBD_DESA_8197F(v)) /* 2 REG_HI6Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI6Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI6Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI6Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8197F) << BIT_SHIFT_HI6Q_TXBD_DESA_8197F) -#define BITS_HI6Q_TXBD_DESA_8197F (BIT_MASK_HI6Q_TXBD_DESA_8197F << BIT_SHIFT_HI6Q_TXBD_DESA_8197F) +#define BIT_HI6Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_8197F) +#define BITS_HI6Q_TXBD_DESA_8197F \ + (BIT_MASK_HI6Q_TXBD_DESA_8197F << BIT_SHIFT_HI6Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8197F)) -#define BIT_GET_HI6Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8197F) & BIT_MASK_HI6Q_TXBD_DESA_8197F) -#define BIT_SET_HI6Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) | BIT_HI6Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI6Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI6Q_TXBD_DESA_8197F) +#define BIT_SET_HI6Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) | BIT_HI6Q_TXBD_DESA_8197F(v)) /* 2 REG_HI7Q_TXBD_DESA_8197F */ #define BIT_SHIFT_HI7Q_TXBD_DESA_8197F 0 #define BIT_MASK_HI7Q_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_HI7Q_TXBD_DESA_8197F(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8197F) << BIT_SHIFT_HI7Q_TXBD_DESA_8197F) -#define BITS_HI7Q_TXBD_DESA_8197F (BIT_MASK_HI7Q_TXBD_DESA_8197F << BIT_SHIFT_HI7Q_TXBD_DESA_8197F) +#define BIT_HI7Q_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_8197F) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_8197F) +#define BITS_HI7Q_TXBD_DESA_8197F \ + (BIT_MASK_HI7Q_TXBD_DESA_8197F << BIT_SHIFT_HI7Q_TXBD_DESA_8197F) #define BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8197F)) -#define BIT_GET_HI7Q_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8197F) & BIT_MASK_HI7Q_TXBD_DESA_8197F) -#define BIT_SET_HI7Q_TXBD_DESA_8197F(x, v) (BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) | BIT_HI7Q_TXBD_DESA_8197F(v)) - +#define BIT_GET_HI7Q_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8197F) & \ + BIT_MASK_HI7Q_TXBD_DESA_8197F) +#define BIT_SET_HI7Q_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) | BIT_HI7Q_TXBD_DESA_8197F(v)) /* 2 REG_MGQ_TXBD_NUM_8197F */ #define BIT_HCI_MGQ_FLAG_8197F BIT(14) #define BIT_SHIFT_MGQ_DESC_MODE_8197F 12 #define BIT_MASK_MGQ_DESC_MODE_8197F 0x3 -#define BIT_MGQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8197F) << BIT_SHIFT_MGQ_DESC_MODE_8197F) -#define BITS_MGQ_DESC_MODE_8197F (BIT_MASK_MGQ_DESC_MODE_8197F << BIT_SHIFT_MGQ_DESC_MODE_8197F) +#define BIT_MGQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_MGQ_DESC_MODE_8197F) << BIT_SHIFT_MGQ_DESC_MODE_8197F) +#define BITS_MGQ_DESC_MODE_8197F \ + (BIT_MASK_MGQ_DESC_MODE_8197F << BIT_SHIFT_MGQ_DESC_MODE_8197F) #define BIT_CLEAR_MGQ_DESC_MODE_8197F(x) ((x) & (~BITS_MGQ_DESC_MODE_8197F)) -#define BIT_GET_MGQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8197F) & BIT_MASK_MGQ_DESC_MODE_8197F) -#define BIT_SET_MGQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_MGQ_DESC_MODE_8197F(x) | BIT_MGQ_DESC_MODE_8197F(v)) - +#define BIT_GET_MGQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8197F) & BIT_MASK_MGQ_DESC_MODE_8197F) +#define BIT_SET_MGQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_MGQ_DESC_MODE_8197F(x) | BIT_MGQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_MGQ_DESC_NUM_8197F 0 #define BIT_MASK_MGQ_DESC_NUM_8197F 0xfff -#define BIT_MGQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8197F) << BIT_SHIFT_MGQ_DESC_NUM_8197F) -#define BITS_MGQ_DESC_NUM_8197F (BIT_MASK_MGQ_DESC_NUM_8197F << BIT_SHIFT_MGQ_DESC_NUM_8197F) +#define BIT_MGQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_MGQ_DESC_NUM_8197F) << BIT_SHIFT_MGQ_DESC_NUM_8197F) +#define BITS_MGQ_DESC_NUM_8197F \ + (BIT_MASK_MGQ_DESC_NUM_8197F << BIT_SHIFT_MGQ_DESC_NUM_8197F) #define BIT_CLEAR_MGQ_DESC_NUM_8197F(x) ((x) & (~BITS_MGQ_DESC_NUM_8197F)) -#define BIT_GET_MGQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8197F) & BIT_MASK_MGQ_DESC_NUM_8197F) -#define BIT_SET_MGQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_MGQ_DESC_NUM_8197F(x) | BIT_MGQ_DESC_NUM_8197F(v)) - +#define BIT_GET_MGQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8197F) & BIT_MASK_MGQ_DESC_NUM_8197F) +#define BIT_SET_MGQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_MGQ_DESC_NUM_8197F(x) | BIT_MGQ_DESC_NUM_8197F(v)) /* 2 REG_RX_RXBD_NUM_8197F */ #define BIT_SYS_32_64_8197F BIT(15) #define BIT_SHIFT_BCNQ_DESC_MODE_8197F 13 #define BIT_MASK_BCNQ_DESC_MODE_8197F 0x3 -#define BIT_BCNQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8197F) << BIT_SHIFT_BCNQ_DESC_MODE_8197F) -#define BITS_BCNQ_DESC_MODE_8197F (BIT_MASK_BCNQ_DESC_MODE_8197F << BIT_SHIFT_BCNQ_DESC_MODE_8197F) +#define BIT_BCNQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_BCNQ_DESC_MODE_8197F) \ + << BIT_SHIFT_BCNQ_DESC_MODE_8197F) +#define BITS_BCNQ_DESC_MODE_8197F \ + (BIT_MASK_BCNQ_DESC_MODE_8197F << BIT_SHIFT_BCNQ_DESC_MODE_8197F) #define BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) ((x) & (~BITS_BCNQ_DESC_MODE_8197F)) -#define BIT_GET_BCNQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8197F) & BIT_MASK_BCNQ_DESC_MODE_8197F) -#define BIT_SET_BCNQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) | BIT_BCNQ_DESC_MODE_8197F(v)) +#define BIT_GET_BCNQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8197F) & \ + BIT_MASK_BCNQ_DESC_MODE_8197F) +#define BIT_SET_BCNQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) | BIT_BCNQ_DESC_MODE_8197F(v)) #define BIT_HCI_BCNQ_FLAG_8197F BIT(12) #define BIT_SHIFT_RXQ_DESC_NUM_8197F 0 #define BIT_MASK_RXQ_DESC_NUM_8197F 0xfff -#define BIT_RXQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8197F) << BIT_SHIFT_RXQ_DESC_NUM_8197F) -#define BITS_RXQ_DESC_NUM_8197F (BIT_MASK_RXQ_DESC_NUM_8197F << BIT_SHIFT_RXQ_DESC_NUM_8197F) +#define BIT_RXQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_RXQ_DESC_NUM_8197F) << BIT_SHIFT_RXQ_DESC_NUM_8197F) +#define BITS_RXQ_DESC_NUM_8197F \ + (BIT_MASK_RXQ_DESC_NUM_8197F << BIT_SHIFT_RXQ_DESC_NUM_8197F) #define BIT_CLEAR_RXQ_DESC_NUM_8197F(x) ((x) & (~BITS_RXQ_DESC_NUM_8197F)) -#define BIT_GET_RXQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8197F) & BIT_MASK_RXQ_DESC_NUM_8197F) -#define BIT_SET_RXQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_RXQ_DESC_NUM_8197F(x) | BIT_RXQ_DESC_NUM_8197F(v)) - +#define BIT_GET_RXQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8197F) & BIT_MASK_RXQ_DESC_NUM_8197F) +#define BIT_SET_RXQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_RXQ_DESC_NUM_8197F(x) | BIT_RXQ_DESC_NUM_8197F(v)) /* 2 REG_VOQ_TXBD_NUM_8197F */ #define BIT_HCI_VOQ_FLAG_8197F BIT(14) #define BIT_SHIFT_VOQ_DESC_MODE_8197F 12 #define BIT_MASK_VOQ_DESC_MODE_8197F 0x3 -#define BIT_VOQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8197F) << BIT_SHIFT_VOQ_DESC_MODE_8197F) -#define BITS_VOQ_DESC_MODE_8197F (BIT_MASK_VOQ_DESC_MODE_8197F << BIT_SHIFT_VOQ_DESC_MODE_8197F) +#define BIT_VOQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_VOQ_DESC_MODE_8197F) << BIT_SHIFT_VOQ_DESC_MODE_8197F) +#define BITS_VOQ_DESC_MODE_8197F \ + (BIT_MASK_VOQ_DESC_MODE_8197F << BIT_SHIFT_VOQ_DESC_MODE_8197F) #define BIT_CLEAR_VOQ_DESC_MODE_8197F(x) ((x) & (~BITS_VOQ_DESC_MODE_8197F)) -#define BIT_GET_VOQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8197F) & BIT_MASK_VOQ_DESC_MODE_8197F) -#define BIT_SET_VOQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_VOQ_DESC_MODE_8197F(x) | BIT_VOQ_DESC_MODE_8197F(v)) - +#define BIT_GET_VOQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8197F) & BIT_MASK_VOQ_DESC_MODE_8197F) +#define BIT_SET_VOQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_VOQ_DESC_MODE_8197F(x) | BIT_VOQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_VOQ_DESC_NUM_8197F 0 #define BIT_MASK_VOQ_DESC_NUM_8197F 0xfff -#define BIT_VOQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8197F) << BIT_SHIFT_VOQ_DESC_NUM_8197F) -#define BITS_VOQ_DESC_NUM_8197F (BIT_MASK_VOQ_DESC_NUM_8197F << BIT_SHIFT_VOQ_DESC_NUM_8197F) +#define BIT_VOQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_VOQ_DESC_NUM_8197F) << BIT_SHIFT_VOQ_DESC_NUM_8197F) +#define BITS_VOQ_DESC_NUM_8197F \ + (BIT_MASK_VOQ_DESC_NUM_8197F << BIT_SHIFT_VOQ_DESC_NUM_8197F) #define BIT_CLEAR_VOQ_DESC_NUM_8197F(x) ((x) & (~BITS_VOQ_DESC_NUM_8197F)) -#define BIT_GET_VOQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8197F) & BIT_MASK_VOQ_DESC_NUM_8197F) -#define BIT_SET_VOQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_VOQ_DESC_NUM_8197F(x) | BIT_VOQ_DESC_NUM_8197F(v)) - +#define BIT_GET_VOQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8197F) & BIT_MASK_VOQ_DESC_NUM_8197F) +#define BIT_SET_VOQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_VOQ_DESC_NUM_8197F(x) | BIT_VOQ_DESC_NUM_8197F(v)) /* 2 REG_VIQ_TXBD_NUM_8197F */ #define BIT_HCI_VIQ_FLAG_8197F BIT(14) #define BIT_SHIFT_VIQ_DESC_MODE_8197F 12 #define BIT_MASK_VIQ_DESC_MODE_8197F 0x3 -#define BIT_VIQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8197F) << BIT_SHIFT_VIQ_DESC_MODE_8197F) -#define BITS_VIQ_DESC_MODE_8197F (BIT_MASK_VIQ_DESC_MODE_8197F << BIT_SHIFT_VIQ_DESC_MODE_8197F) +#define BIT_VIQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_VIQ_DESC_MODE_8197F) << BIT_SHIFT_VIQ_DESC_MODE_8197F) +#define BITS_VIQ_DESC_MODE_8197F \ + (BIT_MASK_VIQ_DESC_MODE_8197F << BIT_SHIFT_VIQ_DESC_MODE_8197F) #define BIT_CLEAR_VIQ_DESC_MODE_8197F(x) ((x) & (~BITS_VIQ_DESC_MODE_8197F)) -#define BIT_GET_VIQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8197F) & BIT_MASK_VIQ_DESC_MODE_8197F) -#define BIT_SET_VIQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_VIQ_DESC_MODE_8197F(x) | BIT_VIQ_DESC_MODE_8197F(v)) - +#define BIT_GET_VIQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8197F) & BIT_MASK_VIQ_DESC_MODE_8197F) +#define BIT_SET_VIQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_VIQ_DESC_MODE_8197F(x) | BIT_VIQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_VIQ_DESC_NUM_8197F 0 #define BIT_MASK_VIQ_DESC_NUM_8197F 0xfff -#define BIT_VIQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8197F) << BIT_SHIFT_VIQ_DESC_NUM_8197F) -#define BITS_VIQ_DESC_NUM_8197F (BIT_MASK_VIQ_DESC_NUM_8197F << BIT_SHIFT_VIQ_DESC_NUM_8197F) +#define BIT_VIQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_VIQ_DESC_NUM_8197F) << BIT_SHIFT_VIQ_DESC_NUM_8197F) +#define BITS_VIQ_DESC_NUM_8197F \ + (BIT_MASK_VIQ_DESC_NUM_8197F << BIT_SHIFT_VIQ_DESC_NUM_8197F) #define BIT_CLEAR_VIQ_DESC_NUM_8197F(x) ((x) & (~BITS_VIQ_DESC_NUM_8197F)) -#define BIT_GET_VIQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8197F) & BIT_MASK_VIQ_DESC_NUM_8197F) -#define BIT_SET_VIQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_VIQ_DESC_NUM_8197F(x) | BIT_VIQ_DESC_NUM_8197F(v)) - +#define BIT_GET_VIQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8197F) & BIT_MASK_VIQ_DESC_NUM_8197F) +#define BIT_SET_VIQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_VIQ_DESC_NUM_8197F(x) | BIT_VIQ_DESC_NUM_8197F(v)) /* 2 REG_BEQ_TXBD_NUM_8197F */ #define BIT_HCI_BEQ_FLAG_8197F BIT(14) #define BIT_SHIFT_BEQ_DESC_MODE_8197F 12 #define BIT_MASK_BEQ_DESC_MODE_8197F 0x3 -#define BIT_BEQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8197F) << BIT_SHIFT_BEQ_DESC_MODE_8197F) -#define BITS_BEQ_DESC_MODE_8197F (BIT_MASK_BEQ_DESC_MODE_8197F << BIT_SHIFT_BEQ_DESC_MODE_8197F) +#define BIT_BEQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_BEQ_DESC_MODE_8197F) << BIT_SHIFT_BEQ_DESC_MODE_8197F) +#define BITS_BEQ_DESC_MODE_8197F \ + (BIT_MASK_BEQ_DESC_MODE_8197F << BIT_SHIFT_BEQ_DESC_MODE_8197F) #define BIT_CLEAR_BEQ_DESC_MODE_8197F(x) ((x) & (~BITS_BEQ_DESC_MODE_8197F)) -#define BIT_GET_BEQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8197F) & BIT_MASK_BEQ_DESC_MODE_8197F) -#define BIT_SET_BEQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_BEQ_DESC_MODE_8197F(x) | BIT_BEQ_DESC_MODE_8197F(v)) - +#define BIT_GET_BEQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8197F) & BIT_MASK_BEQ_DESC_MODE_8197F) +#define BIT_SET_BEQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_BEQ_DESC_MODE_8197F(x) | BIT_BEQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_BEQ_DESC_NUM_8197F 0 #define BIT_MASK_BEQ_DESC_NUM_8197F 0xfff -#define BIT_BEQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8197F) << BIT_SHIFT_BEQ_DESC_NUM_8197F) -#define BITS_BEQ_DESC_NUM_8197F (BIT_MASK_BEQ_DESC_NUM_8197F << BIT_SHIFT_BEQ_DESC_NUM_8197F) +#define BIT_BEQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_BEQ_DESC_NUM_8197F) << BIT_SHIFT_BEQ_DESC_NUM_8197F) +#define BITS_BEQ_DESC_NUM_8197F \ + (BIT_MASK_BEQ_DESC_NUM_8197F << BIT_SHIFT_BEQ_DESC_NUM_8197F) #define BIT_CLEAR_BEQ_DESC_NUM_8197F(x) ((x) & (~BITS_BEQ_DESC_NUM_8197F)) -#define BIT_GET_BEQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8197F) & BIT_MASK_BEQ_DESC_NUM_8197F) -#define BIT_SET_BEQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_BEQ_DESC_NUM_8197F(x) | BIT_BEQ_DESC_NUM_8197F(v)) - +#define BIT_GET_BEQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8197F) & BIT_MASK_BEQ_DESC_NUM_8197F) +#define BIT_SET_BEQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_BEQ_DESC_NUM_8197F(x) | BIT_BEQ_DESC_NUM_8197F(v)) /* 2 REG_BKQ_TXBD_NUM_8197F */ #define BIT_HCI_BKQ_FLAG_8197F BIT(14) #define BIT_SHIFT_BKQ_DESC_MODE_8197F 12 #define BIT_MASK_BKQ_DESC_MODE_8197F 0x3 -#define BIT_BKQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8197F) << BIT_SHIFT_BKQ_DESC_MODE_8197F) -#define BITS_BKQ_DESC_MODE_8197F (BIT_MASK_BKQ_DESC_MODE_8197F << BIT_SHIFT_BKQ_DESC_MODE_8197F) +#define BIT_BKQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_BKQ_DESC_MODE_8197F) << BIT_SHIFT_BKQ_DESC_MODE_8197F) +#define BITS_BKQ_DESC_MODE_8197F \ + (BIT_MASK_BKQ_DESC_MODE_8197F << BIT_SHIFT_BKQ_DESC_MODE_8197F) #define BIT_CLEAR_BKQ_DESC_MODE_8197F(x) ((x) & (~BITS_BKQ_DESC_MODE_8197F)) -#define BIT_GET_BKQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8197F) & BIT_MASK_BKQ_DESC_MODE_8197F) -#define BIT_SET_BKQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_BKQ_DESC_MODE_8197F(x) | BIT_BKQ_DESC_MODE_8197F(v)) - +#define BIT_GET_BKQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8197F) & BIT_MASK_BKQ_DESC_MODE_8197F) +#define BIT_SET_BKQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_BKQ_DESC_MODE_8197F(x) | BIT_BKQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_BKQ_DESC_NUM_8197F 0 #define BIT_MASK_BKQ_DESC_NUM_8197F 0xfff -#define BIT_BKQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8197F) << BIT_SHIFT_BKQ_DESC_NUM_8197F) -#define BITS_BKQ_DESC_NUM_8197F (BIT_MASK_BKQ_DESC_NUM_8197F << BIT_SHIFT_BKQ_DESC_NUM_8197F) +#define BIT_BKQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_BKQ_DESC_NUM_8197F) << BIT_SHIFT_BKQ_DESC_NUM_8197F) +#define BITS_BKQ_DESC_NUM_8197F \ + (BIT_MASK_BKQ_DESC_NUM_8197F << BIT_SHIFT_BKQ_DESC_NUM_8197F) #define BIT_CLEAR_BKQ_DESC_NUM_8197F(x) ((x) & (~BITS_BKQ_DESC_NUM_8197F)) -#define BIT_GET_BKQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8197F) & BIT_MASK_BKQ_DESC_NUM_8197F) -#define BIT_SET_BKQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_BKQ_DESC_NUM_8197F(x) | BIT_BKQ_DESC_NUM_8197F(v)) - +#define BIT_GET_BKQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8197F) & BIT_MASK_BKQ_DESC_NUM_8197F) +#define BIT_SET_BKQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_BKQ_DESC_NUM_8197F(x) | BIT_BKQ_DESC_NUM_8197F(v)) /* 2 REG_HI0Q_TXBD_NUM_8197F */ #define BIT_HI0Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI0Q_DESC_MODE_8197F 12 #define BIT_MASK_HI0Q_DESC_MODE_8197F 0x3 -#define BIT_HI0Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8197F) << BIT_SHIFT_HI0Q_DESC_MODE_8197F) -#define BITS_HI0Q_DESC_MODE_8197F (BIT_MASK_HI0Q_DESC_MODE_8197F << BIT_SHIFT_HI0Q_DESC_MODE_8197F) +#define BIT_HI0Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI0Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI0Q_DESC_MODE_8197F) +#define BITS_HI0Q_DESC_MODE_8197F \ + (BIT_MASK_HI0Q_DESC_MODE_8197F << BIT_SHIFT_HI0Q_DESC_MODE_8197F) #define BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI0Q_DESC_MODE_8197F)) -#define BIT_GET_HI0Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8197F) & BIT_MASK_HI0Q_DESC_MODE_8197F) -#define BIT_SET_HI0Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) | BIT_HI0Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI0Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8197F) & \ + BIT_MASK_HI0Q_DESC_MODE_8197F) +#define BIT_SET_HI0Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) | BIT_HI0Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI0Q_DESC_NUM_8197F 0 #define BIT_MASK_HI0Q_DESC_NUM_8197F 0xfff -#define BIT_HI0Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8197F) << BIT_SHIFT_HI0Q_DESC_NUM_8197F) -#define BITS_HI0Q_DESC_NUM_8197F (BIT_MASK_HI0Q_DESC_NUM_8197F << BIT_SHIFT_HI0Q_DESC_NUM_8197F) +#define BIT_HI0Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI0Q_DESC_NUM_8197F) << BIT_SHIFT_HI0Q_DESC_NUM_8197F) +#define BITS_HI0Q_DESC_NUM_8197F \ + (BIT_MASK_HI0Q_DESC_NUM_8197F << BIT_SHIFT_HI0Q_DESC_NUM_8197F) #define BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI0Q_DESC_NUM_8197F)) -#define BIT_GET_HI0Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8197F) & BIT_MASK_HI0Q_DESC_NUM_8197F) -#define BIT_SET_HI0Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) | BIT_HI0Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI0Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8197F) & BIT_MASK_HI0Q_DESC_NUM_8197F) +#define BIT_SET_HI0Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) | BIT_HI0Q_DESC_NUM_8197F(v)) /* 2 REG_HI1Q_TXBD_NUM_8197F */ #define BIT_HI1Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI1Q_DESC_MODE_8197F 12 #define BIT_MASK_HI1Q_DESC_MODE_8197F 0x3 -#define BIT_HI1Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8197F) << BIT_SHIFT_HI1Q_DESC_MODE_8197F) -#define BITS_HI1Q_DESC_MODE_8197F (BIT_MASK_HI1Q_DESC_MODE_8197F << BIT_SHIFT_HI1Q_DESC_MODE_8197F) +#define BIT_HI1Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI1Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI1Q_DESC_MODE_8197F) +#define BITS_HI1Q_DESC_MODE_8197F \ + (BIT_MASK_HI1Q_DESC_MODE_8197F << BIT_SHIFT_HI1Q_DESC_MODE_8197F) #define BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI1Q_DESC_MODE_8197F)) -#define BIT_GET_HI1Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8197F) & BIT_MASK_HI1Q_DESC_MODE_8197F) -#define BIT_SET_HI1Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) | BIT_HI1Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI1Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8197F) & \ + BIT_MASK_HI1Q_DESC_MODE_8197F) +#define BIT_SET_HI1Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) | BIT_HI1Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI1Q_DESC_NUM_8197F 0 #define BIT_MASK_HI1Q_DESC_NUM_8197F 0xfff -#define BIT_HI1Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8197F) << BIT_SHIFT_HI1Q_DESC_NUM_8197F) -#define BITS_HI1Q_DESC_NUM_8197F (BIT_MASK_HI1Q_DESC_NUM_8197F << BIT_SHIFT_HI1Q_DESC_NUM_8197F) +#define BIT_HI1Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI1Q_DESC_NUM_8197F) << BIT_SHIFT_HI1Q_DESC_NUM_8197F) +#define BITS_HI1Q_DESC_NUM_8197F \ + (BIT_MASK_HI1Q_DESC_NUM_8197F << BIT_SHIFT_HI1Q_DESC_NUM_8197F) #define BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI1Q_DESC_NUM_8197F)) -#define BIT_GET_HI1Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8197F) & BIT_MASK_HI1Q_DESC_NUM_8197F) -#define BIT_SET_HI1Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) | BIT_HI1Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI1Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8197F) & BIT_MASK_HI1Q_DESC_NUM_8197F) +#define BIT_SET_HI1Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) | BIT_HI1Q_DESC_NUM_8197F(v)) /* 2 REG_HI2Q_TXBD_NUM_8197F */ #define BIT_HI2Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI2Q_DESC_MODE_8197F 12 #define BIT_MASK_HI2Q_DESC_MODE_8197F 0x3 -#define BIT_HI2Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8197F) << BIT_SHIFT_HI2Q_DESC_MODE_8197F) -#define BITS_HI2Q_DESC_MODE_8197F (BIT_MASK_HI2Q_DESC_MODE_8197F << BIT_SHIFT_HI2Q_DESC_MODE_8197F) +#define BIT_HI2Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI2Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI2Q_DESC_MODE_8197F) +#define BITS_HI2Q_DESC_MODE_8197F \ + (BIT_MASK_HI2Q_DESC_MODE_8197F << BIT_SHIFT_HI2Q_DESC_MODE_8197F) #define BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI2Q_DESC_MODE_8197F)) -#define BIT_GET_HI2Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8197F) & BIT_MASK_HI2Q_DESC_MODE_8197F) -#define BIT_SET_HI2Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) | BIT_HI2Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI2Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8197F) & \ + BIT_MASK_HI2Q_DESC_MODE_8197F) +#define BIT_SET_HI2Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) | BIT_HI2Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI2Q_DESC_NUM_8197F 0 #define BIT_MASK_HI2Q_DESC_NUM_8197F 0xfff -#define BIT_HI2Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8197F) << BIT_SHIFT_HI2Q_DESC_NUM_8197F) -#define BITS_HI2Q_DESC_NUM_8197F (BIT_MASK_HI2Q_DESC_NUM_8197F << BIT_SHIFT_HI2Q_DESC_NUM_8197F) +#define BIT_HI2Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI2Q_DESC_NUM_8197F) << BIT_SHIFT_HI2Q_DESC_NUM_8197F) +#define BITS_HI2Q_DESC_NUM_8197F \ + (BIT_MASK_HI2Q_DESC_NUM_8197F << BIT_SHIFT_HI2Q_DESC_NUM_8197F) #define BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI2Q_DESC_NUM_8197F)) -#define BIT_GET_HI2Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8197F) & BIT_MASK_HI2Q_DESC_NUM_8197F) -#define BIT_SET_HI2Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) | BIT_HI2Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI2Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8197F) & BIT_MASK_HI2Q_DESC_NUM_8197F) +#define BIT_SET_HI2Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) | BIT_HI2Q_DESC_NUM_8197F(v)) /* 2 REG_HI3Q_TXBD_NUM_8197F */ #define BIT_HI3Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI3Q_DESC_MODE_8197F 12 #define BIT_MASK_HI3Q_DESC_MODE_8197F 0x3 -#define BIT_HI3Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8197F) << BIT_SHIFT_HI3Q_DESC_MODE_8197F) -#define BITS_HI3Q_DESC_MODE_8197F (BIT_MASK_HI3Q_DESC_MODE_8197F << BIT_SHIFT_HI3Q_DESC_MODE_8197F) +#define BIT_HI3Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI3Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI3Q_DESC_MODE_8197F) +#define BITS_HI3Q_DESC_MODE_8197F \ + (BIT_MASK_HI3Q_DESC_MODE_8197F << BIT_SHIFT_HI3Q_DESC_MODE_8197F) #define BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI3Q_DESC_MODE_8197F)) -#define BIT_GET_HI3Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8197F) & BIT_MASK_HI3Q_DESC_MODE_8197F) -#define BIT_SET_HI3Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) | BIT_HI3Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI3Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8197F) & \ + BIT_MASK_HI3Q_DESC_MODE_8197F) +#define BIT_SET_HI3Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) | BIT_HI3Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI3Q_DESC_NUM_8197F 0 #define BIT_MASK_HI3Q_DESC_NUM_8197F 0xfff -#define BIT_HI3Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8197F) << BIT_SHIFT_HI3Q_DESC_NUM_8197F) -#define BITS_HI3Q_DESC_NUM_8197F (BIT_MASK_HI3Q_DESC_NUM_8197F << BIT_SHIFT_HI3Q_DESC_NUM_8197F) +#define BIT_HI3Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI3Q_DESC_NUM_8197F) << BIT_SHIFT_HI3Q_DESC_NUM_8197F) +#define BITS_HI3Q_DESC_NUM_8197F \ + (BIT_MASK_HI3Q_DESC_NUM_8197F << BIT_SHIFT_HI3Q_DESC_NUM_8197F) #define BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI3Q_DESC_NUM_8197F)) -#define BIT_GET_HI3Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8197F) & BIT_MASK_HI3Q_DESC_NUM_8197F) -#define BIT_SET_HI3Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) | BIT_HI3Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI3Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8197F) & BIT_MASK_HI3Q_DESC_NUM_8197F) +#define BIT_SET_HI3Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) | BIT_HI3Q_DESC_NUM_8197F(v)) /* 2 REG_HI4Q_TXBD_NUM_8197F */ #define BIT_HI4Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI4Q_DESC_MODE_8197F 12 #define BIT_MASK_HI4Q_DESC_MODE_8197F 0x3 -#define BIT_HI4Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8197F) << BIT_SHIFT_HI4Q_DESC_MODE_8197F) -#define BITS_HI4Q_DESC_MODE_8197F (BIT_MASK_HI4Q_DESC_MODE_8197F << BIT_SHIFT_HI4Q_DESC_MODE_8197F) +#define BIT_HI4Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI4Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI4Q_DESC_MODE_8197F) +#define BITS_HI4Q_DESC_MODE_8197F \ + (BIT_MASK_HI4Q_DESC_MODE_8197F << BIT_SHIFT_HI4Q_DESC_MODE_8197F) #define BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI4Q_DESC_MODE_8197F)) -#define BIT_GET_HI4Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8197F) & BIT_MASK_HI4Q_DESC_MODE_8197F) -#define BIT_SET_HI4Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) | BIT_HI4Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI4Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8197F) & \ + BIT_MASK_HI4Q_DESC_MODE_8197F) +#define BIT_SET_HI4Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) | BIT_HI4Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI4Q_DESC_NUM_8197F 0 #define BIT_MASK_HI4Q_DESC_NUM_8197F 0xfff -#define BIT_HI4Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8197F) << BIT_SHIFT_HI4Q_DESC_NUM_8197F) -#define BITS_HI4Q_DESC_NUM_8197F (BIT_MASK_HI4Q_DESC_NUM_8197F << BIT_SHIFT_HI4Q_DESC_NUM_8197F) +#define BIT_HI4Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI4Q_DESC_NUM_8197F) << BIT_SHIFT_HI4Q_DESC_NUM_8197F) +#define BITS_HI4Q_DESC_NUM_8197F \ + (BIT_MASK_HI4Q_DESC_NUM_8197F << BIT_SHIFT_HI4Q_DESC_NUM_8197F) #define BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI4Q_DESC_NUM_8197F)) -#define BIT_GET_HI4Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8197F) & BIT_MASK_HI4Q_DESC_NUM_8197F) -#define BIT_SET_HI4Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) | BIT_HI4Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI4Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8197F) & BIT_MASK_HI4Q_DESC_NUM_8197F) +#define BIT_SET_HI4Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) | BIT_HI4Q_DESC_NUM_8197F(v)) /* 2 REG_HI5Q_TXBD_NUM_8197F */ #define BIT_HI5Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI5Q_DESC_MODE_8197F 12 #define BIT_MASK_HI5Q_DESC_MODE_8197F 0x3 -#define BIT_HI5Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8197F) << BIT_SHIFT_HI5Q_DESC_MODE_8197F) -#define BITS_HI5Q_DESC_MODE_8197F (BIT_MASK_HI5Q_DESC_MODE_8197F << BIT_SHIFT_HI5Q_DESC_MODE_8197F) +#define BIT_HI5Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI5Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI5Q_DESC_MODE_8197F) +#define BITS_HI5Q_DESC_MODE_8197F \ + (BIT_MASK_HI5Q_DESC_MODE_8197F << BIT_SHIFT_HI5Q_DESC_MODE_8197F) #define BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI5Q_DESC_MODE_8197F)) -#define BIT_GET_HI5Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8197F) & BIT_MASK_HI5Q_DESC_MODE_8197F) -#define BIT_SET_HI5Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) | BIT_HI5Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI5Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8197F) & \ + BIT_MASK_HI5Q_DESC_MODE_8197F) +#define BIT_SET_HI5Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) | BIT_HI5Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI5Q_DESC_NUM_8197F 0 #define BIT_MASK_HI5Q_DESC_NUM_8197F 0xfff -#define BIT_HI5Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8197F) << BIT_SHIFT_HI5Q_DESC_NUM_8197F) -#define BITS_HI5Q_DESC_NUM_8197F (BIT_MASK_HI5Q_DESC_NUM_8197F << BIT_SHIFT_HI5Q_DESC_NUM_8197F) +#define BIT_HI5Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI5Q_DESC_NUM_8197F) << BIT_SHIFT_HI5Q_DESC_NUM_8197F) +#define BITS_HI5Q_DESC_NUM_8197F \ + (BIT_MASK_HI5Q_DESC_NUM_8197F << BIT_SHIFT_HI5Q_DESC_NUM_8197F) #define BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI5Q_DESC_NUM_8197F)) -#define BIT_GET_HI5Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8197F) & BIT_MASK_HI5Q_DESC_NUM_8197F) -#define BIT_SET_HI5Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) | BIT_HI5Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI5Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8197F) & BIT_MASK_HI5Q_DESC_NUM_8197F) +#define BIT_SET_HI5Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) | BIT_HI5Q_DESC_NUM_8197F(v)) /* 2 REG_HI6Q_TXBD_NUM_8197F */ #define BIT_HI6Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI6Q_DESC_MODE_8197F 12 #define BIT_MASK_HI6Q_DESC_MODE_8197F 0x3 -#define BIT_HI6Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8197F) << BIT_SHIFT_HI6Q_DESC_MODE_8197F) -#define BITS_HI6Q_DESC_MODE_8197F (BIT_MASK_HI6Q_DESC_MODE_8197F << BIT_SHIFT_HI6Q_DESC_MODE_8197F) +#define BIT_HI6Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI6Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI6Q_DESC_MODE_8197F) +#define BITS_HI6Q_DESC_MODE_8197F \ + (BIT_MASK_HI6Q_DESC_MODE_8197F << BIT_SHIFT_HI6Q_DESC_MODE_8197F) #define BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI6Q_DESC_MODE_8197F)) -#define BIT_GET_HI6Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8197F) & BIT_MASK_HI6Q_DESC_MODE_8197F) -#define BIT_SET_HI6Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) | BIT_HI6Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI6Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8197F) & \ + BIT_MASK_HI6Q_DESC_MODE_8197F) +#define BIT_SET_HI6Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) | BIT_HI6Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI6Q_DESC_NUM_8197F 0 #define BIT_MASK_HI6Q_DESC_NUM_8197F 0xfff -#define BIT_HI6Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8197F) << BIT_SHIFT_HI6Q_DESC_NUM_8197F) -#define BITS_HI6Q_DESC_NUM_8197F (BIT_MASK_HI6Q_DESC_NUM_8197F << BIT_SHIFT_HI6Q_DESC_NUM_8197F) +#define BIT_HI6Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI6Q_DESC_NUM_8197F) << BIT_SHIFT_HI6Q_DESC_NUM_8197F) +#define BITS_HI6Q_DESC_NUM_8197F \ + (BIT_MASK_HI6Q_DESC_NUM_8197F << BIT_SHIFT_HI6Q_DESC_NUM_8197F) #define BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI6Q_DESC_NUM_8197F)) -#define BIT_GET_HI6Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8197F) & BIT_MASK_HI6Q_DESC_NUM_8197F) -#define BIT_SET_HI6Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) | BIT_HI6Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI6Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8197F) & BIT_MASK_HI6Q_DESC_NUM_8197F) +#define BIT_SET_HI6Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) | BIT_HI6Q_DESC_NUM_8197F(v)) /* 2 REG_HI7Q_TXBD_NUM_8197F */ #define BIT_HI7Q_FLAG_8197F BIT(14) #define BIT_SHIFT_HI7Q_DESC_MODE_8197F 12 #define BIT_MASK_HI7Q_DESC_MODE_8197F 0x3 -#define BIT_HI7Q_DESC_MODE_8197F(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8197F) << BIT_SHIFT_HI7Q_DESC_MODE_8197F) -#define BITS_HI7Q_DESC_MODE_8197F (BIT_MASK_HI7Q_DESC_MODE_8197F << BIT_SHIFT_HI7Q_DESC_MODE_8197F) +#define BIT_HI7Q_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_HI7Q_DESC_MODE_8197F) \ + << BIT_SHIFT_HI7Q_DESC_MODE_8197F) +#define BITS_HI7Q_DESC_MODE_8197F \ + (BIT_MASK_HI7Q_DESC_MODE_8197F << BIT_SHIFT_HI7Q_DESC_MODE_8197F) #define BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI7Q_DESC_MODE_8197F)) -#define BIT_GET_HI7Q_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8197F) & BIT_MASK_HI7Q_DESC_MODE_8197F) -#define BIT_SET_HI7Q_DESC_MODE_8197F(x, v) (BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) | BIT_HI7Q_DESC_MODE_8197F(v)) - +#define BIT_GET_HI7Q_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8197F) & \ + BIT_MASK_HI7Q_DESC_MODE_8197F) +#define BIT_SET_HI7Q_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) | BIT_HI7Q_DESC_MODE_8197F(v)) #define BIT_SHIFT_HI7Q_DESC_NUM_8197F 0 #define BIT_MASK_HI7Q_DESC_NUM_8197F 0xfff -#define BIT_HI7Q_DESC_NUM_8197F(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8197F) << BIT_SHIFT_HI7Q_DESC_NUM_8197F) -#define BITS_HI7Q_DESC_NUM_8197F (BIT_MASK_HI7Q_DESC_NUM_8197F << BIT_SHIFT_HI7Q_DESC_NUM_8197F) +#define BIT_HI7Q_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_HI7Q_DESC_NUM_8197F) << BIT_SHIFT_HI7Q_DESC_NUM_8197F) +#define BITS_HI7Q_DESC_NUM_8197F \ + (BIT_MASK_HI7Q_DESC_NUM_8197F << BIT_SHIFT_HI7Q_DESC_NUM_8197F) #define BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI7Q_DESC_NUM_8197F)) -#define BIT_GET_HI7Q_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8197F) & BIT_MASK_HI7Q_DESC_NUM_8197F) -#define BIT_SET_HI7Q_DESC_NUM_8197F(x, v) (BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) | BIT_HI7Q_DESC_NUM_8197F(v)) - +#define BIT_GET_HI7Q_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8197F) & BIT_MASK_HI7Q_DESC_NUM_8197F) +#define BIT_SET_HI7Q_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) | BIT_HI7Q_DESC_NUM_8197F(v)) /* 2 REG_TSFTIMER_HCI_8197F */ #define BIT_SHIFT_TSFT2_HCI_8197F 16 #define BIT_MASK_TSFT2_HCI_8197F 0xffff -#define BIT_TSFT2_HCI_8197F(x) (((x) & BIT_MASK_TSFT2_HCI_8197F) << BIT_SHIFT_TSFT2_HCI_8197F) -#define BITS_TSFT2_HCI_8197F (BIT_MASK_TSFT2_HCI_8197F << BIT_SHIFT_TSFT2_HCI_8197F) +#define BIT_TSFT2_HCI_8197F(x) \ + (((x) & BIT_MASK_TSFT2_HCI_8197F) << BIT_SHIFT_TSFT2_HCI_8197F) +#define BITS_TSFT2_HCI_8197F \ + (BIT_MASK_TSFT2_HCI_8197F << BIT_SHIFT_TSFT2_HCI_8197F) #define BIT_CLEAR_TSFT2_HCI_8197F(x) ((x) & (~BITS_TSFT2_HCI_8197F)) -#define BIT_GET_TSFT2_HCI_8197F(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8197F) & BIT_MASK_TSFT2_HCI_8197F) -#define BIT_SET_TSFT2_HCI_8197F(x, v) (BIT_CLEAR_TSFT2_HCI_8197F(x) | BIT_TSFT2_HCI_8197F(v)) - +#define BIT_GET_TSFT2_HCI_8197F(x) \ + (((x) >> BIT_SHIFT_TSFT2_HCI_8197F) & BIT_MASK_TSFT2_HCI_8197F) +#define BIT_SET_TSFT2_HCI_8197F(x, v) \ + (BIT_CLEAR_TSFT2_HCI_8197F(x) | BIT_TSFT2_HCI_8197F(v)) #define BIT_SHIFT_TSFT1_HCI_8197F 0 #define BIT_MASK_TSFT1_HCI_8197F 0xffff -#define BIT_TSFT1_HCI_8197F(x) (((x) & BIT_MASK_TSFT1_HCI_8197F) << BIT_SHIFT_TSFT1_HCI_8197F) -#define BITS_TSFT1_HCI_8197F (BIT_MASK_TSFT1_HCI_8197F << BIT_SHIFT_TSFT1_HCI_8197F) +#define BIT_TSFT1_HCI_8197F(x) \ + (((x) & BIT_MASK_TSFT1_HCI_8197F) << BIT_SHIFT_TSFT1_HCI_8197F) +#define BITS_TSFT1_HCI_8197F \ + (BIT_MASK_TSFT1_HCI_8197F << BIT_SHIFT_TSFT1_HCI_8197F) #define BIT_CLEAR_TSFT1_HCI_8197F(x) ((x) & (~BITS_TSFT1_HCI_8197F)) -#define BIT_GET_TSFT1_HCI_8197F(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8197F) & BIT_MASK_TSFT1_HCI_8197F) -#define BIT_SET_TSFT1_HCI_8197F(x, v) (BIT_CLEAR_TSFT1_HCI_8197F(x) | BIT_TSFT1_HCI_8197F(v)) - +#define BIT_GET_TSFT1_HCI_8197F(x) \ + (((x) >> BIT_SHIFT_TSFT1_HCI_8197F) & BIT_MASK_TSFT1_HCI_8197F) +#define BIT_SET_TSFT1_HCI_8197F(x, v) \ + (BIT_CLEAR_TSFT1_HCI_8197F(x) | BIT_TSFT1_HCI_8197F(v)) /* 2 REG_BD_RWPTR_CLR_8197F */ #define BIT_CLR_HI7Q_HW_IDX_8197F BIT(29) @@ -5427,314 +6854,406 @@ #define BIT_SHIFT_VOQ_HW_IDX_8197F 16 #define BIT_MASK_VOQ_HW_IDX_8197F 0xfff -#define BIT_VOQ_HW_IDX_8197F(x) (((x) & BIT_MASK_VOQ_HW_IDX_8197F) << BIT_SHIFT_VOQ_HW_IDX_8197F) -#define BITS_VOQ_HW_IDX_8197F (BIT_MASK_VOQ_HW_IDX_8197F << BIT_SHIFT_VOQ_HW_IDX_8197F) +#define BIT_VOQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_VOQ_HW_IDX_8197F) << BIT_SHIFT_VOQ_HW_IDX_8197F) +#define BITS_VOQ_HW_IDX_8197F \ + (BIT_MASK_VOQ_HW_IDX_8197F << BIT_SHIFT_VOQ_HW_IDX_8197F) #define BIT_CLEAR_VOQ_HW_IDX_8197F(x) ((x) & (~BITS_VOQ_HW_IDX_8197F)) -#define BIT_GET_VOQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8197F) & BIT_MASK_VOQ_HW_IDX_8197F) -#define BIT_SET_VOQ_HW_IDX_8197F(x, v) (BIT_CLEAR_VOQ_HW_IDX_8197F(x) | BIT_VOQ_HW_IDX_8197F(v)) - +#define BIT_GET_VOQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_VOQ_HW_IDX_8197F) & BIT_MASK_VOQ_HW_IDX_8197F) +#define BIT_SET_VOQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_VOQ_HW_IDX_8197F(x) | BIT_VOQ_HW_IDX_8197F(v)) #define BIT_SHIFT_VOQ_HOST_IDX_8197F 0 #define BIT_MASK_VOQ_HOST_IDX_8197F 0xfff -#define BIT_VOQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8197F) << BIT_SHIFT_VOQ_HOST_IDX_8197F) -#define BITS_VOQ_HOST_IDX_8197F (BIT_MASK_VOQ_HOST_IDX_8197F << BIT_SHIFT_VOQ_HOST_IDX_8197F) +#define BIT_VOQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_VOQ_HOST_IDX_8197F) << BIT_SHIFT_VOQ_HOST_IDX_8197F) +#define BITS_VOQ_HOST_IDX_8197F \ + (BIT_MASK_VOQ_HOST_IDX_8197F << BIT_SHIFT_VOQ_HOST_IDX_8197F) #define BIT_CLEAR_VOQ_HOST_IDX_8197F(x) ((x) & (~BITS_VOQ_HOST_IDX_8197F)) -#define BIT_GET_VOQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8197F) & BIT_MASK_VOQ_HOST_IDX_8197F) -#define BIT_SET_VOQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_VOQ_HOST_IDX_8197F(x) | BIT_VOQ_HOST_IDX_8197F(v)) - +#define BIT_GET_VOQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8197F) & BIT_MASK_VOQ_HOST_IDX_8197F) +#define BIT_SET_VOQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_VOQ_HOST_IDX_8197F(x) | BIT_VOQ_HOST_IDX_8197F(v)) /* 2 REG_VIQ_TXBD_IDX_8197F */ #define BIT_SHIFT_VIQ_HW_IDX_8197F 16 #define BIT_MASK_VIQ_HW_IDX_8197F 0xfff -#define BIT_VIQ_HW_IDX_8197F(x) (((x) & BIT_MASK_VIQ_HW_IDX_8197F) << BIT_SHIFT_VIQ_HW_IDX_8197F) -#define BITS_VIQ_HW_IDX_8197F (BIT_MASK_VIQ_HW_IDX_8197F << BIT_SHIFT_VIQ_HW_IDX_8197F) +#define BIT_VIQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_VIQ_HW_IDX_8197F) << BIT_SHIFT_VIQ_HW_IDX_8197F) +#define BITS_VIQ_HW_IDX_8197F \ + (BIT_MASK_VIQ_HW_IDX_8197F << BIT_SHIFT_VIQ_HW_IDX_8197F) #define BIT_CLEAR_VIQ_HW_IDX_8197F(x) ((x) & (~BITS_VIQ_HW_IDX_8197F)) -#define BIT_GET_VIQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8197F) & BIT_MASK_VIQ_HW_IDX_8197F) -#define BIT_SET_VIQ_HW_IDX_8197F(x, v) (BIT_CLEAR_VIQ_HW_IDX_8197F(x) | BIT_VIQ_HW_IDX_8197F(v)) - +#define BIT_GET_VIQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_VIQ_HW_IDX_8197F) & BIT_MASK_VIQ_HW_IDX_8197F) +#define BIT_SET_VIQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_VIQ_HW_IDX_8197F(x) | BIT_VIQ_HW_IDX_8197F(v)) #define BIT_SHIFT_VIQ_HOST_IDX_8197F 0 #define BIT_MASK_VIQ_HOST_IDX_8197F 0xfff -#define BIT_VIQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8197F) << BIT_SHIFT_VIQ_HOST_IDX_8197F) -#define BITS_VIQ_HOST_IDX_8197F (BIT_MASK_VIQ_HOST_IDX_8197F << BIT_SHIFT_VIQ_HOST_IDX_8197F) +#define BIT_VIQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_VIQ_HOST_IDX_8197F) << BIT_SHIFT_VIQ_HOST_IDX_8197F) +#define BITS_VIQ_HOST_IDX_8197F \ + (BIT_MASK_VIQ_HOST_IDX_8197F << BIT_SHIFT_VIQ_HOST_IDX_8197F) #define BIT_CLEAR_VIQ_HOST_IDX_8197F(x) ((x) & (~BITS_VIQ_HOST_IDX_8197F)) -#define BIT_GET_VIQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8197F) & BIT_MASK_VIQ_HOST_IDX_8197F) -#define BIT_SET_VIQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_VIQ_HOST_IDX_8197F(x) | BIT_VIQ_HOST_IDX_8197F(v)) - +#define BIT_GET_VIQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8197F) & BIT_MASK_VIQ_HOST_IDX_8197F) +#define BIT_SET_VIQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_VIQ_HOST_IDX_8197F(x) | BIT_VIQ_HOST_IDX_8197F(v)) /* 2 REG_BEQ_TXBD_IDX_8197F */ #define BIT_SHIFT_BEQ_HW_IDX_8197F 16 #define BIT_MASK_BEQ_HW_IDX_8197F 0xfff -#define BIT_BEQ_HW_IDX_8197F(x) (((x) & BIT_MASK_BEQ_HW_IDX_8197F) << BIT_SHIFT_BEQ_HW_IDX_8197F) -#define BITS_BEQ_HW_IDX_8197F (BIT_MASK_BEQ_HW_IDX_8197F << BIT_SHIFT_BEQ_HW_IDX_8197F) +#define BIT_BEQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_BEQ_HW_IDX_8197F) << BIT_SHIFT_BEQ_HW_IDX_8197F) +#define BITS_BEQ_HW_IDX_8197F \ + (BIT_MASK_BEQ_HW_IDX_8197F << BIT_SHIFT_BEQ_HW_IDX_8197F) #define BIT_CLEAR_BEQ_HW_IDX_8197F(x) ((x) & (~BITS_BEQ_HW_IDX_8197F)) -#define BIT_GET_BEQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8197F) & BIT_MASK_BEQ_HW_IDX_8197F) -#define BIT_SET_BEQ_HW_IDX_8197F(x, v) (BIT_CLEAR_BEQ_HW_IDX_8197F(x) | BIT_BEQ_HW_IDX_8197F(v)) - +#define BIT_GET_BEQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_BEQ_HW_IDX_8197F) & BIT_MASK_BEQ_HW_IDX_8197F) +#define BIT_SET_BEQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_BEQ_HW_IDX_8197F(x) | BIT_BEQ_HW_IDX_8197F(v)) #define BIT_SHIFT_BEQ_HOST_IDX_8197F 0 #define BIT_MASK_BEQ_HOST_IDX_8197F 0xfff -#define BIT_BEQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8197F) << BIT_SHIFT_BEQ_HOST_IDX_8197F) -#define BITS_BEQ_HOST_IDX_8197F (BIT_MASK_BEQ_HOST_IDX_8197F << BIT_SHIFT_BEQ_HOST_IDX_8197F) +#define BIT_BEQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_BEQ_HOST_IDX_8197F) << BIT_SHIFT_BEQ_HOST_IDX_8197F) +#define BITS_BEQ_HOST_IDX_8197F \ + (BIT_MASK_BEQ_HOST_IDX_8197F << BIT_SHIFT_BEQ_HOST_IDX_8197F) #define BIT_CLEAR_BEQ_HOST_IDX_8197F(x) ((x) & (~BITS_BEQ_HOST_IDX_8197F)) -#define BIT_GET_BEQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8197F) & BIT_MASK_BEQ_HOST_IDX_8197F) -#define BIT_SET_BEQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_BEQ_HOST_IDX_8197F(x) | BIT_BEQ_HOST_IDX_8197F(v)) - +#define BIT_GET_BEQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8197F) & BIT_MASK_BEQ_HOST_IDX_8197F) +#define BIT_SET_BEQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_BEQ_HOST_IDX_8197F(x) | BIT_BEQ_HOST_IDX_8197F(v)) /* 2 REG_BKQ_TXBD_IDX_8197F */ #define BIT_SHIFT_BKQ_HW_IDX_8197F 16 #define BIT_MASK_BKQ_HW_IDX_8197F 0xfff -#define BIT_BKQ_HW_IDX_8197F(x) (((x) & BIT_MASK_BKQ_HW_IDX_8197F) << BIT_SHIFT_BKQ_HW_IDX_8197F) -#define BITS_BKQ_HW_IDX_8197F (BIT_MASK_BKQ_HW_IDX_8197F << BIT_SHIFT_BKQ_HW_IDX_8197F) +#define BIT_BKQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_BKQ_HW_IDX_8197F) << BIT_SHIFT_BKQ_HW_IDX_8197F) +#define BITS_BKQ_HW_IDX_8197F \ + (BIT_MASK_BKQ_HW_IDX_8197F << BIT_SHIFT_BKQ_HW_IDX_8197F) #define BIT_CLEAR_BKQ_HW_IDX_8197F(x) ((x) & (~BITS_BKQ_HW_IDX_8197F)) -#define BIT_GET_BKQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8197F) & BIT_MASK_BKQ_HW_IDX_8197F) -#define BIT_SET_BKQ_HW_IDX_8197F(x, v) (BIT_CLEAR_BKQ_HW_IDX_8197F(x) | BIT_BKQ_HW_IDX_8197F(v)) - +#define BIT_GET_BKQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_BKQ_HW_IDX_8197F) & BIT_MASK_BKQ_HW_IDX_8197F) +#define BIT_SET_BKQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_BKQ_HW_IDX_8197F(x) | BIT_BKQ_HW_IDX_8197F(v)) #define BIT_SHIFT_BKQ_HOST_IDX_8197F 0 #define BIT_MASK_BKQ_HOST_IDX_8197F 0xfff -#define BIT_BKQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8197F) << BIT_SHIFT_BKQ_HOST_IDX_8197F) -#define BITS_BKQ_HOST_IDX_8197F (BIT_MASK_BKQ_HOST_IDX_8197F << BIT_SHIFT_BKQ_HOST_IDX_8197F) +#define BIT_BKQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_BKQ_HOST_IDX_8197F) << BIT_SHIFT_BKQ_HOST_IDX_8197F) +#define BITS_BKQ_HOST_IDX_8197F \ + (BIT_MASK_BKQ_HOST_IDX_8197F << BIT_SHIFT_BKQ_HOST_IDX_8197F) #define BIT_CLEAR_BKQ_HOST_IDX_8197F(x) ((x) & (~BITS_BKQ_HOST_IDX_8197F)) -#define BIT_GET_BKQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8197F) & BIT_MASK_BKQ_HOST_IDX_8197F) -#define BIT_SET_BKQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_BKQ_HOST_IDX_8197F(x) | BIT_BKQ_HOST_IDX_8197F(v)) - +#define BIT_GET_BKQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8197F) & BIT_MASK_BKQ_HOST_IDX_8197F) +#define BIT_SET_BKQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_BKQ_HOST_IDX_8197F(x) | BIT_BKQ_HOST_IDX_8197F(v)) /* 2 REG_MGQ_TXBD_IDX_8197F */ #define BIT_SHIFT_MGQ_HW_IDX_8197F 16 #define BIT_MASK_MGQ_HW_IDX_8197F 0xfff -#define BIT_MGQ_HW_IDX_8197F(x) (((x) & BIT_MASK_MGQ_HW_IDX_8197F) << BIT_SHIFT_MGQ_HW_IDX_8197F) -#define BITS_MGQ_HW_IDX_8197F (BIT_MASK_MGQ_HW_IDX_8197F << BIT_SHIFT_MGQ_HW_IDX_8197F) +#define BIT_MGQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_MGQ_HW_IDX_8197F) << BIT_SHIFT_MGQ_HW_IDX_8197F) +#define BITS_MGQ_HW_IDX_8197F \ + (BIT_MASK_MGQ_HW_IDX_8197F << BIT_SHIFT_MGQ_HW_IDX_8197F) #define BIT_CLEAR_MGQ_HW_IDX_8197F(x) ((x) & (~BITS_MGQ_HW_IDX_8197F)) -#define BIT_GET_MGQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8197F) & BIT_MASK_MGQ_HW_IDX_8197F) -#define BIT_SET_MGQ_HW_IDX_8197F(x, v) (BIT_CLEAR_MGQ_HW_IDX_8197F(x) | BIT_MGQ_HW_IDX_8197F(v)) - +#define BIT_GET_MGQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_HW_IDX_8197F) & BIT_MASK_MGQ_HW_IDX_8197F) +#define BIT_SET_MGQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_MGQ_HW_IDX_8197F(x) | BIT_MGQ_HW_IDX_8197F(v)) #define BIT_SHIFT_MGQ_HOST_IDX_8197F 0 #define BIT_MASK_MGQ_HOST_IDX_8197F 0xfff -#define BIT_MGQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8197F) << BIT_SHIFT_MGQ_HOST_IDX_8197F) -#define BITS_MGQ_HOST_IDX_8197F (BIT_MASK_MGQ_HOST_IDX_8197F << BIT_SHIFT_MGQ_HOST_IDX_8197F) +#define BIT_MGQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_MGQ_HOST_IDX_8197F) << BIT_SHIFT_MGQ_HOST_IDX_8197F) +#define BITS_MGQ_HOST_IDX_8197F \ + (BIT_MASK_MGQ_HOST_IDX_8197F << BIT_SHIFT_MGQ_HOST_IDX_8197F) #define BIT_CLEAR_MGQ_HOST_IDX_8197F(x) ((x) & (~BITS_MGQ_HOST_IDX_8197F)) -#define BIT_GET_MGQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8197F) & BIT_MASK_MGQ_HOST_IDX_8197F) -#define BIT_SET_MGQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_MGQ_HOST_IDX_8197F(x) | BIT_MGQ_HOST_IDX_8197F(v)) - +#define BIT_GET_MGQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8197F) & BIT_MASK_MGQ_HOST_IDX_8197F) +#define BIT_SET_MGQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_MGQ_HOST_IDX_8197F(x) | BIT_MGQ_HOST_IDX_8197F(v)) /* 2 REG_RXQ_RXBD_IDX_8197F */ #define BIT_SHIFT_RXQ_HW_IDX_8197F 16 #define BIT_MASK_RXQ_HW_IDX_8197F 0xfff -#define BIT_RXQ_HW_IDX_8197F(x) (((x) & BIT_MASK_RXQ_HW_IDX_8197F) << BIT_SHIFT_RXQ_HW_IDX_8197F) -#define BITS_RXQ_HW_IDX_8197F (BIT_MASK_RXQ_HW_IDX_8197F << BIT_SHIFT_RXQ_HW_IDX_8197F) +#define BIT_RXQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_RXQ_HW_IDX_8197F) << BIT_SHIFT_RXQ_HW_IDX_8197F) +#define BITS_RXQ_HW_IDX_8197F \ + (BIT_MASK_RXQ_HW_IDX_8197F << BIT_SHIFT_RXQ_HW_IDX_8197F) #define BIT_CLEAR_RXQ_HW_IDX_8197F(x) ((x) & (~BITS_RXQ_HW_IDX_8197F)) -#define BIT_GET_RXQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8197F) & BIT_MASK_RXQ_HW_IDX_8197F) -#define BIT_SET_RXQ_HW_IDX_8197F(x, v) (BIT_CLEAR_RXQ_HW_IDX_8197F(x) | BIT_RXQ_HW_IDX_8197F(v)) - +#define BIT_GET_RXQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RXQ_HW_IDX_8197F) & BIT_MASK_RXQ_HW_IDX_8197F) +#define BIT_SET_RXQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_RXQ_HW_IDX_8197F(x) | BIT_RXQ_HW_IDX_8197F(v)) #define BIT_SHIFT_RXQ_HOST_IDX_8197F 0 #define BIT_MASK_RXQ_HOST_IDX_8197F 0xfff -#define BIT_RXQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8197F) << BIT_SHIFT_RXQ_HOST_IDX_8197F) -#define BITS_RXQ_HOST_IDX_8197F (BIT_MASK_RXQ_HOST_IDX_8197F << BIT_SHIFT_RXQ_HOST_IDX_8197F) +#define BIT_RXQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_RXQ_HOST_IDX_8197F) << BIT_SHIFT_RXQ_HOST_IDX_8197F) +#define BITS_RXQ_HOST_IDX_8197F \ + (BIT_MASK_RXQ_HOST_IDX_8197F << BIT_SHIFT_RXQ_HOST_IDX_8197F) #define BIT_CLEAR_RXQ_HOST_IDX_8197F(x) ((x) & (~BITS_RXQ_HOST_IDX_8197F)) -#define BIT_GET_RXQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8197F) & BIT_MASK_RXQ_HOST_IDX_8197F) -#define BIT_SET_RXQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_RXQ_HOST_IDX_8197F(x) | BIT_RXQ_HOST_IDX_8197F(v)) - +#define BIT_GET_RXQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8197F) & BIT_MASK_RXQ_HOST_IDX_8197F) +#define BIT_SET_RXQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_RXQ_HOST_IDX_8197F(x) | BIT_RXQ_HOST_IDX_8197F(v)) /* 2 REG_HI0Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI0Q_HW_IDX_8197F 16 #define BIT_MASK_HI0Q_HW_IDX_8197F 0xfff -#define BIT_HI0Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8197F) << BIT_SHIFT_HI0Q_HW_IDX_8197F) -#define BITS_HI0Q_HW_IDX_8197F (BIT_MASK_HI0Q_HW_IDX_8197F << BIT_SHIFT_HI0Q_HW_IDX_8197F) +#define BIT_HI0Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI0Q_HW_IDX_8197F) << BIT_SHIFT_HI0Q_HW_IDX_8197F) +#define BITS_HI0Q_HW_IDX_8197F \ + (BIT_MASK_HI0Q_HW_IDX_8197F << BIT_SHIFT_HI0Q_HW_IDX_8197F) #define BIT_CLEAR_HI0Q_HW_IDX_8197F(x) ((x) & (~BITS_HI0Q_HW_IDX_8197F)) -#define BIT_GET_HI0Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8197F) & BIT_MASK_HI0Q_HW_IDX_8197F) -#define BIT_SET_HI0Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI0Q_HW_IDX_8197F(x) | BIT_HI0Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI0Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8197F) & BIT_MASK_HI0Q_HW_IDX_8197F) +#define BIT_SET_HI0Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI0Q_HW_IDX_8197F(x) | BIT_HI0Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI0Q_HOST_IDX_8197F 0 #define BIT_MASK_HI0Q_HOST_IDX_8197F 0xfff -#define BIT_HI0Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8197F) << BIT_SHIFT_HI0Q_HOST_IDX_8197F) -#define BITS_HI0Q_HOST_IDX_8197F (BIT_MASK_HI0Q_HOST_IDX_8197F << BIT_SHIFT_HI0Q_HOST_IDX_8197F) +#define BIT_HI0Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI0Q_HOST_IDX_8197F) << BIT_SHIFT_HI0Q_HOST_IDX_8197F) +#define BITS_HI0Q_HOST_IDX_8197F \ + (BIT_MASK_HI0Q_HOST_IDX_8197F << BIT_SHIFT_HI0Q_HOST_IDX_8197F) #define BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI0Q_HOST_IDX_8197F)) -#define BIT_GET_HI0Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8197F) & BIT_MASK_HI0Q_HOST_IDX_8197F) -#define BIT_SET_HI0Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) | BIT_HI0Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI0Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8197F) & BIT_MASK_HI0Q_HOST_IDX_8197F) +#define BIT_SET_HI0Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) | BIT_HI0Q_HOST_IDX_8197F(v)) /* 2 REG_HI1Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI1Q_HW_IDX_8197F 16 #define BIT_MASK_HI1Q_HW_IDX_8197F 0xfff -#define BIT_HI1Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8197F) << BIT_SHIFT_HI1Q_HW_IDX_8197F) -#define BITS_HI1Q_HW_IDX_8197F (BIT_MASK_HI1Q_HW_IDX_8197F << BIT_SHIFT_HI1Q_HW_IDX_8197F) +#define BIT_HI1Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI1Q_HW_IDX_8197F) << BIT_SHIFT_HI1Q_HW_IDX_8197F) +#define BITS_HI1Q_HW_IDX_8197F \ + (BIT_MASK_HI1Q_HW_IDX_8197F << BIT_SHIFT_HI1Q_HW_IDX_8197F) #define BIT_CLEAR_HI1Q_HW_IDX_8197F(x) ((x) & (~BITS_HI1Q_HW_IDX_8197F)) -#define BIT_GET_HI1Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8197F) & BIT_MASK_HI1Q_HW_IDX_8197F) -#define BIT_SET_HI1Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI1Q_HW_IDX_8197F(x) | BIT_HI1Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI1Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8197F) & BIT_MASK_HI1Q_HW_IDX_8197F) +#define BIT_SET_HI1Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI1Q_HW_IDX_8197F(x) | BIT_HI1Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI1Q_HOST_IDX_8197F 0 #define BIT_MASK_HI1Q_HOST_IDX_8197F 0xfff -#define BIT_HI1Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8197F) << BIT_SHIFT_HI1Q_HOST_IDX_8197F) -#define BITS_HI1Q_HOST_IDX_8197F (BIT_MASK_HI1Q_HOST_IDX_8197F << BIT_SHIFT_HI1Q_HOST_IDX_8197F) +#define BIT_HI1Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI1Q_HOST_IDX_8197F) << BIT_SHIFT_HI1Q_HOST_IDX_8197F) +#define BITS_HI1Q_HOST_IDX_8197F \ + (BIT_MASK_HI1Q_HOST_IDX_8197F << BIT_SHIFT_HI1Q_HOST_IDX_8197F) #define BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI1Q_HOST_IDX_8197F)) -#define BIT_GET_HI1Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8197F) & BIT_MASK_HI1Q_HOST_IDX_8197F) -#define BIT_SET_HI1Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) | BIT_HI1Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI1Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8197F) & BIT_MASK_HI1Q_HOST_IDX_8197F) +#define BIT_SET_HI1Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) | BIT_HI1Q_HOST_IDX_8197F(v)) /* 2 REG_HI2Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI2Q_HW_IDX_8197F 16 #define BIT_MASK_HI2Q_HW_IDX_8197F 0xfff -#define BIT_HI2Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8197F) << BIT_SHIFT_HI2Q_HW_IDX_8197F) -#define BITS_HI2Q_HW_IDX_8197F (BIT_MASK_HI2Q_HW_IDX_8197F << BIT_SHIFT_HI2Q_HW_IDX_8197F) +#define BIT_HI2Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI2Q_HW_IDX_8197F) << BIT_SHIFT_HI2Q_HW_IDX_8197F) +#define BITS_HI2Q_HW_IDX_8197F \ + (BIT_MASK_HI2Q_HW_IDX_8197F << BIT_SHIFT_HI2Q_HW_IDX_8197F) #define BIT_CLEAR_HI2Q_HW_IDX_8197F(x) ((x) & (~BITS_HI2Q_HW_IDX_8197F)) -#define BIT_GET_HI2Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8197F) & BIT_MASK_HI2Q_HW_IDX_8197F) -#define BIT_SET_HI2Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI2Q_HW_IDX_8197F(x) | BIT_HI2Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI2Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8197F) & BIT_MASK_HI2Q_HW_IDX_8197F) +#define BIT_SET_HI2Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI2Q_HW_IDX_8197F(x) | BIT_HI2Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI2Q_HOST_IDX_8197F 0 #define BIT_MASK_HI2Q_HOST_IDX_8197F 0xfff -#define BIT_HI2Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8197F) << BIT_SHIFT_HI2Q_HOST_IDX_8197F) -#define BITS_HI2Q_HOST_IDX_8197F (BIT_MASK_HI2Q_HOST_IDX_8197F << BIT_SHIFT_HI2Q_HOST_IDX_8197F) +#define BIT_HI2Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI2Q_HOST_IDX_8197F) << BIT_SHIFT_HI2Q_HOST_IDX_8197F) +#define BITS_HI2Q_HOST_IDX_8197F \ + (BIT_MASK_HI2Q_HOST_IDX_8197F << BIT_SHIFT_HI2Q_HOST_IDX_8197F) #define BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI2Q_HOST_IDX_8197F)) -#define BIT_GET_HI2Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8197F) & BIT_MASK_HI2Q_HOST_IDX_8197F) -#define BIT_SET_HI2Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) | BIT_HI2Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI2Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8197F) & BIT_MASK_HI2Q_HOST_IDX_8197F) +#define BIT_SET_HI2Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) | BIT_HI2Q_HOST_IDX_8197F(v)) /* 2 REG_HI3Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI3Q_HW_IDX_8197F 16 #define BIT_MASK_HI3Q_HW_IDX_8197F 0xfff -#define BIT_HI3Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8197F) << BIT_SHIFT_HI3Q_HW_IDX_8197F) -#define BITS_HI3Q_HW_IDX_8197F (BIT_MASK_HI3Q_HW_IDX_8197F << BIT_SHIFT_HI3Q_HW_IDX_8197F) +#define BIT_HI3Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI3Q_HW_IDX_8197F) << BIT_SHIFT_HI3Q_HW_IDX_8197F) +#define BITS_HI3Q_HW_IDX_8197F \ + (BIT_MASK_HI3Q_HW_IDX_8197F << BIT_SHIFT_HI3Q_HW_IDX_8197F) #define BIT_CLEAR_HI3Q_HW_IDX_8197F(x) ((x) & (~BITS_HI3Q_HW_IDX_8197F)) -#define BIT_GET_HI3Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8197F) & BIT_MASK_HI3Q_HW_IDX_8197F) -#define BIT_SET_HI3Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI3Q_HW_IDX_8197F(x) | BIT_HI3Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI3Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8197F) & BIT_MASK_HI3Q_HW_IDX_8197F) +#define BIT_SET_HI3Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI3Q_HW_IDX_8197F(x) | BIT_HI3Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI3Q_HOST_IDX_8197F 0 #define BIT_MASK_HI3Q_HOST_IDX_8197F 0xfff -#define BIT_HI3Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8197F) << BIT_SHIFT_HI3Q_HOST_IDX_8197F) -#define BITS_HI3Q_HOST_IDX_8197F (BIT_MASK_HI3Q_HOST_IDX_8197F << BIT_SHIFT_HI3Q_HOST_IDX_8197F) +#define BIT_HI3Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI3Q_HOST_IDX_8197F) << BIT_SHIFT_HI3Q_HOST_IDX_8197F) +#define BITS_HI3Q_HOST_IDX_8197F \ + (BIT_MASK_HI3Q_HOST_IDX_8197F << BIT_SHIFT_HI3Q_HOST_IDX_8197F) #define BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI3Q_HOST_IDX_8197F)) -#define BIT_GET_HI3Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8197F) & BIT_MASK_HI3Q_HOST_IDX_8197F) -#define BIT_SET_HI3Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) | BIT_HI3Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI3Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8197F) & BIT_MASK_HI3Q_HOST_IDX_8197F) +#define BIT_SET_HI3Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) | BIT_HI3Q_HOST_IDX_8197F(v)) /* 2 REG_HI4Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI4Q_HW_IDX_8197F 16 #define BIT_MASK_HI4Q_HW_IDX_8197F 0xfff -#define BIT_HI4Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8197F) << BIT_SHIFT_HI4Q_HW_IDX_8197F) -#define BITS_HI4Q_HW_IDX_8197F (BIT_MASK_HI4Q_HW_IDX_8197F << BIT_SHIFT_HI4Q_HW_IDX_8197F) +#define BIT_HI4Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI4Q_HW_IDX_8197F) << BIT_SHIFT_HI4Q_HW_IDX_8197F) +#define BITS_HI4Q_HW_IDX_8197F \ + (BIT_MASK_HI4Q_HW_IDX_8197F << BIT_SHIFT_HI4Q_HW_IDX_8197F) #define BIT_CLEAR_HI4Q_HW_IDX_8197F(x) ((x) & (~BITS_HI4Q_HW_IDX_8197F)) -#define BIT_GET_HI4Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8197F) & BIT_MASK_HI4Q_HW_IDX_8197F) -#define BIT_SET_HI4Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI4Q_HW_IDX_8197F(x) | BIT_HI4Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI4Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8197F) & BIT_MASK_HI4Q_HW_IDX_8197F) +#define BIT_SET_HI4Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI4Q_HW_IDX_8197F(x) | BIT_HI4Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI4Q_HOST_IDX_8197F 0 #define BIT_MASK_HI4Q_HOST_IDX_8197F 0xfff -#define BIT_HI4Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8197F) << BIT_SHIFT_HI4Q_HOST_IDX_8197F) -#define BITS_HI4Q_HOST_IDX_8197F (BIT_MASK_HI4Q_HOST_IDX_8197F << BIT_SHIFT_HI4Q_HOST_IDX_8197F) +#define BIT_HI4Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI4Q_HOST_IDX_8197F) << BIT_SHIFT_HI4Q_HOST_IDX_8197F) +#define BITS_HI4Q_HOST_IDX_8197F \ + (BIT_MASK_HI4Q_HOST_IDX_8197F << BIT_SHIFT_HI4Q_HOST_IDX_8197F) #define BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI4Q_HOST_IDX_8197F)) -#define BIT_GET_HI4Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8197F) & BIT_MASK_HI4Q_HOST_IDX_8197F) -#define BIT_SET_HI4Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) | BIT_HI4Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI4Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8197F) & BIT_MASK_HI4Q_HOST_IDX_8197F) +#define BIT_SET_HI4Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) | BIT_HI4Q_HOST_IDX_8197F(v)) /* 2 REG_HI5Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI5Q_HW_IDX_8197F 16 #define BIT_MASK_HI5Q_HW_IDX_8197F 0xfff -#define BIT_HI5Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8197F) << BIT_SHIFT_HI5Q_HW_IDX_8197F) -#define BITS_HI5Q_HW_IDX_8197F (BIT_MASK_HI5Q_HW_IDX_8197F << BIT_SHIFT_HI5Q_HW_IDX_8197F) +#define BIT_HI5Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI5Q_HW_IDX_8197F) << BIT_SHIFT_HI5Q_HW_IDX_8197F) +#define BITS_HI5Q_HW_IDX_8197F \ + (BIT_MASK_HI5Q_HW_IDX_8197F << BIT_SHIFT_HI5Q_HW_IDX_8197F) #define BIT_CLEAR_HI5Q_HW_IDX_8197F(x) ((x) & (~BITS_HI5Q_HW_IDX_8197F)) -#define BIT_GET_HI5Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8197F) & BIT_MASK_HI5Q_HW_IDX_8197F) -#define BIT_SET_HI5Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI5Q_HW_IDX_8197F(x) | BIT_HI5Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI5Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8197F) & BIT_MASK_HI5Q_HW_IDX_8197F) +#define BIT_SET_HI5Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI5Q_HW_IDX_8197F(x) | BIT_HI5Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI5Q_HOST_IDX_8197F 0 #define BIT_MASK_HI5Q_HOST_IDX_8197F 0xfff -#define BIT_HI5Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8197F) << BIT_SHIFT_HI5Q_HOST_IDX_8197F) -#define BITS_HI5Q_HOST_IDX_8197F (BIT_MASK_HI5Q_HOST_IDX_8197F << BIT_SHIFT_HI5Q_HOST_IDX_8197F) +#define BIT_HI5Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI5Q_HOST_IDX_8197F) << BIT_SHIFT_HI5Q_HOST_IDX_8197F) +#define BITS_HI5Q_HOST_IDX_8197F \ + (BIT_MASK_HI5Q_HOST_IDX_8197F << BIT_SHIFT_HI5Q_HOST_IDX_8197F) #define BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI5Q_HOST_IDX_8197F)) -#define BIT_GET_HI5Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8197F) & BIT_MASK_HI5Q_HOST_IDX_8197F) -#define BIT_SET_HI5Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) | BIT_HI5Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI5Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8197F) & BIT_MASK_HI5Q_HOST_IDX_8197F) +#define BIT_SET_HI5Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) | BIT_HI5Q_HOST_IDX_8197F(v)) /* 2 REG_HI6Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI6Q_HW_IDX_8197F 16 #define BIT_MASK_HI6Q_HW_IDX_8197F 0xfff -#define BIT_HI6Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8197F) << BIT_SHIFT_HI6Q_HW_IDX_8197F) -#define BITS_HI6Q_HW_IDX_8197F (BIT_MASK_HI6Q_HW_IDX_8197F << BIT_SHIFT_HI6Q_HW_IDX_8197F) +#define BIT_HI6Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI6Q_HW_IDX_8197F) << BIT_SHIFT_HI6Q_HW_IDX_8197F) +#define BITS_HI6Q_HW_IDX_8197F \ + (BIT_MASK_HI6Q_HW_IDX_8197F << BIT_SHIFT_HI6Q_HW_IDX_8197F) #define BIT_CLEAR_HI6Q_HW_IDX_8197F(x) ((x) & (~BITS_HI6Q_HW_IDX_8197F)) -#define BIT_GET_HI6Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8197F) & BIT_MASK_HI6Q_HW_IDX_8197F) -#define BIT_SET_HI6Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI6Q_HW_IDX_8197F(x) | BIT_HI6Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI6Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8197F) & BIT_MASK_HI6Q_HW_IDX_8197F) +#define BIT_SET_HI6Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI6Q_HW_IDX_8197F(x) | BIT_HI6Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI6Q_HOST_IDX_8197F 0 #define BIT_MASK_HI6Q_HOST_IDX_8197F 0xfff -#define BIT_HI6Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8197F) << BIT_SHIFT_HI6Q_HOST_IDX_8197F) -#define BITS_HI6Q_HOST_IDX_8197F (BIT_MASK_HI6Q_HOST_IDX_8197F << BIT_SHIFT_HI6Q_HOST_IDX_8197F) +#define BIT_HI6Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI6Q_HOST_IDX_8197F) << BIT_SHIFT_HI6Q_HOST_IDX_8197F) +#define BITS_HI6Q_HOST_IDX_8197F \ + (BIT_MASK_HI6Q_HOST_IDX_8197F << BIT_SHIFT_HI6Q_HOST_IDX_8197F) #define BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI6Q_HOST_IDX_8197F)) -#define BIT_GET_HI6Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8197F) & BIT_MASK_HI6Q_HOST_IDX_8197F) -#define BIT_SET_HI6Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) | BIT_HI6Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI6Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8197F) & BIT_MASK_HI6Q_HOST_IDX_8197F) +#define BIT_SET_HI6Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) | BIT_HI6Q_HOST_IDX_8197F(v)) /* 2 REG_HI7Q_TXBD_IDX_8197F */ #define BIT_SHIFT_HI7Q_HW_IDX_8197F 16 #define BIT_MASK_HI7Q_HW_IDX_8197F 0xfff -#define BIT_HI7Q_HW_IDX_8197F(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8197F) << BIT_SHIFT_HI7Q_HW_IDX_8197F) -#define BITS_HI7Q_HW_IDX_8197F (BIT_MASK_HI7Q_HW_IDX_8197F << BIT_SHIFT_HI7Q_HW_IDX_8197F) +#define BIT_HI7Q_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_HI7Q_HW_IDX_8197F) << BIT_SHIFT_HI7Q_HW_IDX_8197F) +#define BITS_HI7Q_HW_IDX_8197F \ + (BIT_MASK_HI7Q_HW_IDX_8197F << BIT_SHIFT_HI7Q_HW_IDX_8197F) #define BIT_CLEAR_HI7Q_HW_IDX_8197F(x) ((x) & (~BITS_HI7Q_HW_IDX_8197F)) -#define BIT_GET_HI7Q_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8197F) & BIT_MASK_HI7Q_HW_IDX_8197F) -#define BIT_SET_HI7Q_HW_IDX_8197F(x, v) (BIT_CLEAR_HI7Q_HW_IDX_8197F(x) | BIT_HI7Q_HW_IDX_8197F(v)) - +#define BIT_GET_HI7Q_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8197F) & BIT_MASK_HI7Q_HW_IDX_8197F) +#define BIT_SET_HI7Q_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_HI7Q_HW_IDX_8197F(x) | BIT_HI7Q_HW_IDX_8197F(v)) #define BIT_SHIFT_HI7Q_HOST_IDX_8197F 0 #define BIT_MASK_HI7Q_HOST_IDX_8197F 0xfff -#define BIT_HI7Q_HOST_IDX_8197F(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8197F) << BIT_SHIFT_HI7Q_HOST_IDX_8197F) -#define BITS_HI7Q_HOST_IDX_8197F (BIT_MASK_HI7Q_HOST_IDX_8197F << BIT_SHIFT_HI7Q_HOST_IDX_8197F) +#define BIT_HI7Q_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_HI7Q_HOST_IDX_8197F) << BIT_SHIFT_HI7Q_HOST_IDX_8197F) +#define BITS_HI7Q_HOST_IDX_8197F \ + (BIT_MASK_HI7Q_HOST_IDX_8197F << BIT_SHIFT_HI7Q_HOST_IDX_8197F) #define BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI7Q_HOST_IDX_8197F)) -#define BIT_GET_HI7Q_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8197F) & BIT_MASK_HI7Q_HOST_IDX_8197F) -#define BIT_SET_HI7Q_HOST_IDX_8197F(x, v) (BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) | BIT_HI7Q_HOST_IDX_8197F(v)) - +#define BIT_GET_HI7Q_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8197F) & BIT_MASK_HI7Q_HOST_IDX_8197F) +#define BIT_SET_HI7Q_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) | BIT_HI7Q_HOST_IDX_8197F(v)) /* 2 REG_DBG_SEL_V1_8197F */ #define BIT_SHIFT_DBG_SEL_8197F 0 #define BIT_MASK_DBG_SEL_8197F 0xff -#define BIT_DBG_SEL_8197F(x) (((x) & BIT_MASK_DBG_SEL_8197F) << BIT_SHIFT_DBG_SEL_8197F) +#define BIT_DBG_SEL_8197F(x) \ + (((x) & BIT_MASK_DBG_SEL_8197F) << BIT_SHIFT_DBG_SEL_8197F) #define BITS_DBG_SEL_8197F (BIT_MASK_DBG_SEL_8197F << BIT_SHIFT_DBG_SEL_8197F) #define BIT_CLEAR_DBG_SEL_8197F(x) ((x) & (~BITS_DBG_SEL_8197F)) -#define BIT_GET_DBG_SEL_8197F(x) (((x) >> BIT_SHIFT_DBG_SEL_8197F) & BIT_MASK_DBG_SEL_8197F) -#define BIT_SET_DBG_SEL_8197F(x, v) (BIT_CLEAR_DBG_SEL_8197F(x) | BIT_DBG_SEL_8197F(v)) - +#define BIT_GET_DBG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_8197F) & BIT_MASK_DBG_SEL_8197F) +#define BIT_SET_DBG_SEL_8197F(x, v) \ + (BIT_CLEAR_DBG_SEL_8197F(x) | BIT_DBG_SEL_8197F(v)) /* 2 REG_HCI_HRPWM1_V1_8197F */ #define BIT_SHIFT_HCI_HRPWM_8197F 0 #define BIT_MASK_HCI_HRPWM_8197F 0xff -#define BIT_HCI_HRPWM_8197F(x) (((x) & BIT_MASK_HCI_HRPWM_8197F) << BIT_SHIFT_HCI_HRPWM_8197F) -#define BITS_HCI_HRPWM_8197F (BIT_MASK_HCI_HRPWM_8197F << BIT_SHIFT_HCI_HRPWM_8197F) +#define BIT_HCI_HRPWM_8197F(x) \ + (((x) & BIT_MASK_HCI_HRPWM_8197F) << BIT_SHIFT_HCI_HRPWM_8197F) +#define BITS_HCI_HRPWM_8197F \ + (BIT_MASK_HCI_HRPWM_8197F << BIT_SHIFT_HCI_HRPWM_8197F) #define BIT_CLEAR_HCI_HRPWM_8197F(x) ((x) & (~BITS_HCI_HRPWM_8197F)) -#define BIT_GET_HCI_HRPWM_8197F(x) (((x) >> BIT_SHIFT_HCI_HRPWM_8197F) & BIT_MASK_HCI_HRPWM_8197F) -#define BIT_SET_HCI_HRPWM_8197F(x, v) (BIT_CLEAR_HCI_HRPWM_8197F(x) | BIT_HCI_HRPWM_8197F(v)) - +#define BIT_GET_HCI_HRPWM_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_HRPWM_8197F) & BIT_MASK_HCI_HRPWM_8197F) +#define BIT_SET_HCI_HRPWM_8197F(x, v) \ + (BIT_CLEAR_HCI_HRPWM_8197F(x) | BIT_HCI_HRPWM_8197F(v)) /* 2 REG_HCI_HCPWM1_V1_8197F */ #define BIT_SHIFT_HCI_HCPWM_8197F 0 #define BIT_MASK_HCI_HCPWM_8197F 0xff -#define BIT_HCI_HCPWM_8197F(x) (((x) & BIT_MASK_HCI_HCPWM_8197F) << BIT_SHIFT_HCI_HCPWM_8197F) -#define BITS_HCI_HCPWM_8197F (BIT_MASK_HCI_HCPWM_8197F << BIT_SHIFT_HCI_HCPWM_8197F) +#define BIT_HCI_HCPWM_8197F(x) \ + (((x) & BIT_MASK_HCI_HCPWM_8197F) << BIT_SHIFT_HCI_HCPWM_8197F) +#define BITS_HCI_HCPWM_8197F \ + (BIT_MASK_HCI_HCPWM_8197F << BIT_SHIFT_HCI_HCPWM_8197F) #define BIT_CLEAR_HCI_HCPWM_8197F(x) ((x) & (~BITS_HCI_HCPWM_8197F)) -#define BIT_GET_HCI_HCPWM_8197F(x) (((x) >> BIT_SHIFT_HCI_HCPWM_8197F) & BIT_MASK_HCI_HCPWM_8197F) -#define BIT_SET_HCI_HCPWM_8197F(x, v) (BIT_CLEAR_HCI_HCPWM_8197F(x) | BIT_HCI_HCPWM_8197F(v)) - +#define BIT_GET_HCI_HCPWM_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_HCPWM_8197F) & BIT_MASK_HCI_HCPWM_8197F) +#define BIT_SET_HCI_HCPWM_8197F(x, v) \ + (BIT_CLEAR_HCI_HCPWM_8197F(x) | BIT_HCI_HCPWM_8197F(v)) /* 2 REG_HCI_CTRL2_8197F */ #define BIT_DIS_TXDMA_PRE_8197F BIT(7) @@ -5742,11 +7261,15 @@ #define BIT_SHIFT_HPS_CLKR_HCI_8197F 4 #define BIT_MASK_HPS_CLKR_HCI_8197F 0x3 -#define BIT_HPS_CLKR_HCI_8197F(x) (((x) & BIT_MASK_HPS_CLKR_HCI_8197F) << BIT_SHIFT_HPS_CLKR_HCI_8197F) -#define BITS_HPS_CLKR_HCI_8197F (BIT_MASK_HPS_CLKR_HCI_8197F << BIT_SHIFT_HPS_CLKR_HCI_8197F) +#define BIT_HPS_CLKR_HCI_8197F(x) \ + (((x) & BIT_MASK_HPS_CLKR_HCI_8197F) << BIT_SHIFT_HPS_CLKR_HCI_8197F) +#define BITS_HPS_CLKR_HCI_8197F \ + (BIT_MASK_HPS_CLKR_HCI_8197F << BIT_SHIFT_HPS_CLKR_HCI_8197F) #define BIT_CLEAR_HPS_CLKR_HCI_8197F(x) ((x) & (~BITS_HPS_CLKR_HCI_8197F)) -#define BIT_GET_HPS_CLKR_HCI_8197F(x) (((x) >> BIT_SHIFT_HPS_CLKR_HCI_8197F) & BIT_MASK_HPS_CLKR_HCI_8197F) -#define BIT_SET_HPS_CLKR_HCI_8197F(x, v) (BIT_CLEAR_HPS_CLKR_HCI_8197F(x) | BIT_HPS_CLKR_HCI_8197F(v)) +#define BIT_GET_HPS_CLKR_HCI_8197F(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_HCI_8197F) & BIT_MASK_HPS_CLKR_HCI_8197F) +#define BIT_SET_HPS_CLKR_HCI_8197F(x, v) \ + (BIT_CLEAR_HPS_CLKR_HCI_8197F(x) | BIT_HPS_CLKR_HCI_8197F(v)) #define BIT_HCI_INT_8197F BIT(3) #define BIT_TXFLAG_EXIT_L1_EN_8197F BIT(2) @@ -5757,67 +7280,85 @@ #define BIT_SHIFT_HCI_HRPWM2_8197F 0 #define BIT_MASK_HCI_HRPWM2_8197F 0xffff -#define BIT_HCI_HRPWM2_8197F(x) (((x) & BIT_MASK_HCI_HRPWM2_8197F) << BIT_SHIFT_HCI_HRPWM2_8197F) -#define BITS_HCI_HRPWM2_8197F (BIT_MASK_HCI_HRPWM2_8197F << BIT_SHIFT_HCI_HRPWM2_8197F) +#define BIT_HCI_HRPWM2_8197F(x) \ + (((x) & BIT_MASK_HCI_HRPWM2_8197F) << BIT_SHIFT_HCI_HRPWM2_8197F) +#define BITS_HCI_HRPWM2_8197F \ + (BIT_MASK_HCI_HRPWM2_8197F << BIT_SHIFT_HCI_HRPWM2_8197F) #define BIT_CLEAR_HCI_HRPWM2_8197F(x) ((x) & (~BITS_HCI_HRPWM2_8197F)) -#define BIT_GET_HCI_HRPWM2_8197F(x) (((x) >> BIT_SHIFT_HCI_HRPWM2_8197F) & BIT_MASK_HCI_HRPWM2_8197F) -#define BIT_SET_HCI_HRPWM2_8197F(x, v) (BIT_CLEAR_HCI_HRPWM2_8197F(x) | BIT_HCI_HRPWM2_8197F(v)) - +#define BIT_GET_HCI_HRPWM2_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_HRPWM2_8197F) & BIT_MASK_HCI_HRPWM2_8197F) +#define BIT_SET_HCI_HRPWM2_8197F(x, v) \ + (BIT_CLEAR_HCI_HRPWM2_8197F(x) | BIT_HCI_HRPWM2_8197F(v)) /* 2 REG_HCI_HCPWM2_V1_8197F */ #define BIT_SHIFT_HCI_HCPWM2_8197F 0 #define BIT_MASK_HCI_HCPWM2_8197F 0xffff -#define BIT_HCI_HCPWM2_8197F(x) (((x) & BIT_MASK_HCI_HCPWM2_8197F) << BIT_SHIFT_HCI_HCPWM2_8197F) -#define BITS_HCI_HCPWM2_8197F (BIT_MASK_HCI_HCPWM2_8197F << BIT_SHIFT_HCI_HCPWM2_8197F) +#define BIT_HCI_HCPWM2_8197F(x) \ + (((x) & BIT_MASK_HCI_HCPWM2_8197F) << BIT_SHIFT_HCI_HCPWM2_8197F) +#define BITS_HCI_HCPWM2_8197F \ + (BIT_MASK_HCI_HCPWM2_8197F << BIT_SHIFT_HCI_HCPWM2_8197F) #define BIT_CLEAR_HCI_HCPWM2_8197F(x) ((x) & (~BITS_HCI_HCPWM2_8197F)) -#define BIT_GET_HCI_HCPWM2_8197F(x) (((x) >> BIT_SHIFT_HCI_HCPWM2_8197F) & BIT_MASK_HCI_HCPWM2_8197F) -#define BIT_SET_HCI_HCPWM2_8197F(x, v) (BIT_CLEAR_HCI_HCPWM2_8197F(x) | BIT_HCI_HCPWM2_8197F(v)) - +#define BIT_GET_HCI_HCPWM2_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_HCPWM2_8197F) & BIT_MASK_HCI_HCPWM2_8197F) +#define BIT_SET_HCI_HCPWM2_8197F(x, v) \ + (BIT_CLEAR_HCI_HCPWM2_8197F(x) | BIT_HCI_HCPWM2_8197F(v)) /* 2 REG_HCI_H2C_MSG_V1_8197F */ #define BIT_SHIFT_DRV2FW_INFO_8197F 0 #define BIT_MASK_DRV2FW_INFO_8197F 0xffffffffL -#define BIT_DRV2FW_INFO_8197F(x) (((x) & BIT_MASK_DRV2FW_INFO_8197F) << BIT_SHIFT_DRV2FW_INFO_8197F) -#define BITS_DRV2FW_INFO_8197F (BIT_MASK_DRV2FW_INFO_8197F << BIT_SHIFT_DRV2FW_INFO_8197F) +#define BIT_DRV2FW_INFO_8197F(x) \ + (((x) & BIT_MASK_DRV2FW_INFO_8197F) << BIT_SHIFT_DRV2FW_INFO_8197F) +#define BITS_DRV2FW_INFO_8197F \ + (BIT_MASK_DRV2FW_INFO_8197F << BIT_SHIFT_DRV2FW_INFO_8197F) #define BIT_CLEAR_DRV2FW_INFO_8197F(x) ((x) & (~BITS_DRV2FW_INFO_8197F)) -#define BIT_GET_DRV2FW_INFO_8197F(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8197F) & BIT_MASK_DRV2FW_INFO_8197F) -#define BIT_SET_DRV2FW_INFO_8197F(x, v) (BIT_CLEAR_DRV2FW_INFO_8197F(x) | BIT_DRV2FW_INFO_8197F(v)) - +#define BIT_GET_DRV2FW_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO_8197F) & BIT_MASK_DRV2FW_INFO_8197F) +#define BIT_SET_DRV2FW_INFO_8197F(x, v) \ + (BIT_CLEAR_DRV2FW_INFO_8197F(x) | BIT_DRV2FW_INFO_8197F(v)) /* 2 REG_HCI_C2H_MSG_V1_8197F */ #define BIT_SHIFT_HCI_C2H_MSG_8197F 0 #define BIT_MASK_HCI_C2H_MSG_8197F 0xffffffffL -#define BIT_HCI_C2H_MSG_8197F(x) (((x) & BIT_MASK_HCI_C2H_MSG_8197F) << BIT_SHIFT_HCI_C2H_MSG_8197F) -#define BITS_HCI_C2H_MSG_8197F (BIT_MASK_HCI_C2H_MSG_8197F << BIT_SHIFT_HCI_C2H_MSG_8197F) +#define BIT_HCI_C2H_MSG_8197F(x) \ + (((x) & BIT_MASK_HCI_C2H_MSG_8197F) << BIT_SHIFT_HCI_C2H_MSG_8197F) +#define BITS_HCI_C2H_MSG_8197F \ + (BIT_MASK_HCI_C2H_MSG_8197F << BIT_SHIFT_HCI_C2H_MSG_8197F) #define BIT_CLEAR_HCI_C2H_MSG_8197F(x) ((x) & (~BITS_HCI_C2H_MSG_8197F)) -#define BIT_GET_HCI_C2H_MSG_8197F(x) (((x) >> BIT_SHIFT_HCI_C2H_MSG_8197F) & BIT_MASK_HCI_C2H_MSG_8197F) -#define BIT_SET_HCI_C2H_MSG_8197F(x, v) (BIT_CLEAR_HCI_C2H_MSG_8197F(x) | BIT_HCI_C2H_MSG_8197F(v)) - +#define BIT_GET_HCI_C2H_MSG_8197F(x) \ + (((x) >> BIT_SHIFT_HCI_C2H_MSG_8197F) & BIT_MASK_HCI_C2H_MSG_8197F) +#define BIT_SET_HCI_C2H_MSG_8197F(x, v) \ + (BIT_CLEAR_HCI_C2H_MSG_8197F(x) | BIT_HCI_C2H_MSG_8197F(v)) /* 2 REG_DBI_WDATA_V1_8197F */ #define BIT_SHIFT_DBI_WDATA_8197F 0 #define BIT_MASK_DBI_WDATA_8197F 0xffffffffL -#define BIT_DBI_WDATA_8197F(x) (((x) & BIT_MASK_DBI_WDATA_8197F) << BIT_SHIFT_DBI_WDATA_8197F) -#define BITS_DBI_WDATA_8197F (BIT_MASK_DBI_WDATA_8197F << BIT_SHIFT_DBI_WDATA_8197F) +#define BIT_DBI_WDATA_8197F(x) \ + (((x) & BIT_MASK_DBI_WDATA_8197F) << BIT_SHIFT_DBI_WDATA_8197F) +#define BITS_DBI_WDATA_8197F \ + (BIT_MASK_DBI_WDATA_8197F << BIT_SHIFT_DBI_WDATA_8197F) #define BIT_CLEAR_DBI_WDATA_8197F(x) ((x) & (~BITS_DBI_WDATA_8197F)) -#define BIT_GET_DBI_WDATA_8197F(x) (((x) >> BIT_SHIFT_DBI_WDATA_8197F) & BIT_MASK_DBI_WDATA_8197F) -#define BIT_SET_DBI_WDATA_8197F(x, v) (BIT_CLEAR_DBI_WDATA_8197F(x) | BIT_DBI_WDATA_8197F(v)) - +#define BIT_GET_DBI_WDATA_8197F(x) \ + (((x) >> BIT_SHIFT_DBI_WDATA_8197F) & BIT_MASK_DBI_WDATA_8197F) +#define BIT_SET_DBI_WDATA_8197F(x, v) \ + (BIT_CLEAR_DBI_WDATA_8197F(x) | BIT_DBI_WDATA_8197F(v)) /* 2 REG_DBI_RDATA_V1_8197F */ #define BIT_SHIFT_DBI_RDATA_8197F 0 #define BIT_MASK_DBI_RDATA_8197F 0xffffffffL -#define BIT_DBI_RDATA_8197F(x) (((x) & BIT_MASK_DBI_RDATA_8197F) << BIT_SHIFT_DBI_RDATA_8197F) -#define BITS_DBI_RDATA_8197F (BIT_MASK_DBI_RDATA_8197F << BIT_SHIFT_DBI_RDATA_8197F) +#define BIT_DBI_RDATA_8197F(x) \ + (((x) & BIT_MASK_DBI_RDATA_8197F) << BIT_SHIFT_DBI_RDATA_8197F) +#define BITS_DBI_RDATA_8197F \ + (BIT_MASK_DBI_RDATA_8197F << BIT_SHIFT_DBI_RDATA_8197F) #define BIT_CLEAR_DBI_RDATA_8197F(x) ((x) & (~BITS_DBI_RDATA_8197F)) -#define BIT_GET_DBI_RDATA_8197F(x) (((x) >> BIT_SHIFT_DBI_RDATA_8197F) & BIT_MASK_DBI_RDATA_8197F) -#define BIT_SET_DBI_RDATA_8197F(x, v) (BIT_CLEAR_DBI_RDATA_8197F(x) | BIT_DBI_RDATA_8197F(v)) - +#define BIT_GET_DBI_RDATA_8197F(x) \ + (((x) >> BIT_SHIFT_DBI_RDATA_8197F) & BIT_MASK_DBI_RDATA_8197F) +#define BIT_SET_DBI_RDATA_8197F(x, v) \ + (BIT_CLEAR_DBI_RDATA_8197F(x) | BIT_DBI_RDATA_8197F(v)) /* 2 REG_STUCK_FLAG_V1_8197F */ #define BIT_EN_STUCK_DBG_8197F BIT(26) @@ -5828,60 +7369,84 @@ #define BIT_SHIFT_DBI_WREN_8197F 12 #define BIT_MASK_DBI_WREN_8197F 0xf -#define BIT_DBI_WREN_8197F(x) (((x) & BIT_MASK_DBI_WREN_8197F) << BIT_SHIFT_DBI_WREN_8197F) -#define BITS_DBI_WREN_8197F (BIT_MASK_DBI_WREN_8197F << BIT_SHIFT_DBI_WREN_8197F) +#define BIT_DBI_WREN_8197F(x) \ + (((x) & BIT_MASK_DBI_WREN_8197F) << BIT_SHIFT_DBI_WREN_8197F) +#define BITS_DBI_WREN_8197F \ + (BIT_MASK_DBI_WREN_8197F << BIT_SHIFT_DBI_WREN_8197F) #define BIT_CLEAR_DBI_WREN_8197F(x) ((x) & (~BITS_DBI_WREN_8197F)) -#define BIT_GET_DBI_WREN_8197F(x) (((x) >> BIT_SHIFT_DBI_WREN_8197F) & BIT_MASK_DBI_WREN_8197F) -#define BIT_SET_DBI_WREN_8197F(x, v) (BIT_CLEAR_DBI_WREN_8197F(x) | BIT_DBI_WREN_8197F(v)) - +#define BIT_GET_DBI_WREN_8197F(x) \ + (((x) >> BIT_SHIFT_DBI_WREN_8197F) & BIT_MASK_DBI_WREN_8197F) +#define BIT_SET_DBI_WREN_8197F(x, v) \ + (BIT_CLEAR_DBI_WREN_8197F(x) | BIT_DBI_WREN_8197F(v)) #define BIT_SHIFT_DBI_ADDR_8197F 0 #define BIT_MASK_DBI_ADDR_8197F 0xfff -#define BIT_DBI_ADDR_8197F(x) (((x) & BIT_MASK_DBI_ADDR_8197F) << BIT_SHIFT_DBI_ADDR_8197F) -#define BITS_DBI_ADDR_8197F (BIT_MASK_DBI_ADDR_8197F << BIT_SHIFT_DBI_ADDR_8197F) +#define BIT_DBI_ADDR_8197F(x) \ + (((x) & BIT_MASK_DBI_ADDR_8197F) << BIT_SHIFT_DBI_ADDR_8197F) +#define BITS_DBI_ADDR_8197F \ + (BIT_MASK_DBI_ADDR_8197F << BIT_SHIFT_DBI_ADDR_8197F) #define BIT_CLEAR_DBI_ADDR_8197F(x) ((x) & (~BITS_DBI_ADDR_8197F)) -#define BIT_GET_DBI_ADDR_8197F(x) (((x) >> BIT_SHIFT_DBI_ADDR_8197F) & BIT_MASK_DBI_ADDR_8197F) -#define BIT_SET_DBI_ADDR_8197F(x, v) (BIT_CLEAR_DBI_ADDR_8197F(x) | BIT_DBI_ADDR_8197F(v)) - +#define BIT_GET_DBI_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_DBI_ADDR_8197F) & BIT_MASK_DBI_ADDR_8197F) +#define BIT_SET_DBI_ADDR_8197F(x, v) \ + (BIT_CLEAR_DBI_ADDR_8197F(x) | BIT_DBI_ADDR_8197F(v)) /* 2 REG_MDIO_V1_8197F */ #define BIT_SHIFT_MDIO_RDATA_8197F 16 #define BIT_MASK_MDIO_RDATA_8197F 0xffff -#define BIT_MDIO_RDATA_8197F(x) (((x) & BIT_MASK_MDIO_RDATA_8197F) << BIT_SHIFT_MDIO_RDATA_8197F) -#define BITS_MDIO_RDATA_8197F (BIT_MASK_MDIO_RDATA_8197F << BIT_SHIFT_MDIO_RDATA_8197F) +#define BIT_MDIO_RDATA_8197F(x) \ + (((x) & BIT_MASK_MDIO_RDATA_8197F) << BIT_SHIFT_MDIO_RDATA_8197F) +#define BITS_MDIO_RDATA_8197F \ + (BIT_MASK_MDIO_RDATA_8197F << BIT_SHIFT_MDIO_RDATA_8197F) #define BIT_CLEAR_MDIO_RDATA_8197F(x) ((x) & (~BITS_MDIO_RDATA_8197F)) -#define BIT_GET_MDIO_RDATA_8197F(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8197F) & BIT_MASK_MDIO_RDATA_8197F) -#define BIT_SET_MDIO_RDATA_8197F(x, v) (BIT_CLEAR_MDIO_RDATA_8197F(x) | BIT_MDIO_RDATA_8197F(v)) - +#define BIT_GET_MDIO_RDATA_8197F(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA_8197F) & BIT_MASK_MDIO_RDATA_8197F) +#define BIT_SET_MDIO_RDATA_8197F(x, v) \ + (BIT_CLEAR_MDIO_RDATA_8197F(x) | BIT_MDIO_RDATA_8197F(v)) #define BIT_SHIFT_MDIO_WDATA_8197F 0 #define BIT_MASK_MDIO_WDATA_8197F 0xffff -#define BIT_MDIO_WDATA_8197F(x) (((x) & BIT_MASK_MDIO_WDATA_8197F) << BIT_SHIFT_MDIO_WDATA_8197F) -#define BITS_MDIO_WDATA_8197F (BIT_MASK_MDIO_WDATA_8197F << BIT_SHIFT_MDIO_WDATA_8197F) +#define BIT_MDIO_WDATA_8197F(x) \ + (((x) & BIT_MASK_MDIO_WDATA_8197F) << BIT_SHIFT_MDIO_WDATA_8197F) +#define BITS_MDIO_WDATA_8197F \ + (BIT_MASK_MDIO_WDATA_8197F << BIT_SHIFT_MDIO_WDATA_8197F) #define BIT_CLEAR_MDIO_WDATA_8197F(x) ((x) & (~BITS_MDIO_WDATA_8197F)) -#define BIT_GET_MDIO_WDATA_8197F(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8197F) & BIT_MASK_MDIO_WDATA_8197F) -#define BIT_SET_MDIO_WDATA_8197F(x, v) (BIT_CLEAR_MDIO_WDATA_8197F(x) | BIT_MDIO_WDATA_8197F(v)) - +#define BIT_GET_MDIO_WDATA_8197F(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA_8197F) & BIT_MASK_MDIO_WDATA_8197F) +#define BIT_SET_MDIO_WDATA_8197F(x, v) \ + (BIT_CLEAR_MDIO_WDATA_8197F(x) | BIT_MDIO_WDATA_8197F(v)) /* 2 REG_WDT_CFG_8197F */ #define BIT_SHIFT_MDIO_PHY_ADDR_8197F 24 #define BIT_MASK_MDIO_PHY_ADDR_8197F 0x1f -#define BIT_MDIO_PHY_ADDR_8197F(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8197F) << BIT_SHIFT_MDIO_PHY_ADDR_8197F) -#define BITS_MDIO_PHY_ADDR_8197F (BIT_MASK_MDIO_PHY_ADDR_8197F << BIT_SHIFT_MDIO_PHY_ADDR_8197F) +#define BIT_MDIO_PHY_ADDR_8197F(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR_8197F) << BIT_SHIFT_MDIO_PHY_ADDR_8197F) +#define BITS_MDIO_PHY_ADDR_8197F \ + (BIT_MASK_MDIO_PHY_ADDR_8197F << BIT_SHIFT_MDIO_PHY_ADDR_8197F) #define BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) ((x) & (~BITS_MDIO_PHY_ADDR_8197F)) -#define BIT_GET_MDIO_PHY_ADDR_8197F(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8197F) & BIT_MASK_MDIO_PHY_ADDR_8197F) -#define BIT_SET_MDIO_PHY_ADDR_8197F(x, v) (BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) | BIT_MDIO_PHY_ADDR_8197F(v)) - +#define BIT_GET_MDIO_PHY_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8197F) & BIT_MASK_MDIO_PHY_ADDR_8197F) +#define BIT_SET_MDIO_PHY_ADDR_8197F(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) | BIT_MDIO_PHY_ADDR_8197F(v)) #define BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F 10 #define BIT_MASK_WATCH_DOG_RECORD_V1_8197F 0x3fff -#define BIT_WATCH_DOG_RECORD_V1_8197F(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8197F) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) -#define BITS_WATCH_DOG_RECORD_V1_8197F (BIT_MASK_WATCH_DOG_RECORD_V1_8197F << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) -#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) ((x) & (~BITS_WATCH_DOG_RECORD_V1_8197F)) -#define BIT_GET_WATCH_DOG_RECORD_V1_8197F(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) & BIT_MASK_WATCH_DOG_RECORD_V1_8197F) -#define BIT_SET_WATCH_DOG_RECORD_V1_8197F(x, v) (BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) | BIT_WATCH_DOG_RECORD_V1_8197F(v)) +#define BIT_WATCH_DOG_RECORD_V1_8197F(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8197F) \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) +#define BITS_WATCH_DOG_RECORD_V1_8197F \ + (BIT_MASK_WATCH_DOG_RECORD_V1_8197F \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) \ + ((x) & (~BITS_WATCH_DOG_RECORD_V1_8197F)) +#define BIT_GET_WATCH_DOG_RECORD_V1_8197F(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) & \ + BIT_MASK_WATCH_DOG_RECORD_V1_8197F) +#define BIT_SET_WATCH_DOG_RECORD_V1_8197F(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) | \ + BIT_WATCH_DOG_RECORD_V1_8197F(v)) #define BIT_R_IO_TIMEOUT_FLAG_V1_8197F BIT(9) #define BIT_EN_WATCH_DOG_V1_8197F BIT(8) @@ -5891,12 +7456,15 @@ #define BIT_SHIFT_MDIO_REG_ADDR_8197F 0 #define BIT_MASK_MDIO_REG_ADDR_8197F 0x1f -#define BIT_MDIO_REG_ADDR_8197F(x) (((x) & BIT_MASK_MDIO_REG_ADDR_8197F) << BIT_SHIFT_MDIO_REG_ADDR_8197F) -#define BITS_MDIO_REG_ADDR_8197F (BIT_MASK_MDIO_REG_ADDR_8197F << BIT_SHIFT_MDIO_REG_ADDR_8197F) +#define BIT_MDIO_REG_ADDR_8197F(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_8197F) << BIT_SHIFT_MDIO_REG_ADDR_8197F) +#define BITS_MDIO_REG_ADDR_8197F \ + (BIT_MASK_MDIO_REG_ADDR_8197F << BIT_SHIFT_MDIO_REG_ADDR_8197F) #define BIT_CLEAR_MDIO_REG_ADDR_8197F(x) ((x) & (~BITS_MDIO_REG_ADDR_8197F)) -#define BIT_GET_MDIO_REG_ADDR_8197F(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_8197F) & BIT_MASK_MDIO_REG_ADDR_8197F) -#define BIT_SET_MDIO_REG_ADDR_8197F(x, v) (BIT_CLEAR_MDIO_REG_ADDR_8197F(x) | BIT_MDIO_REG_ADDR_8197F(v)) - +#define BIT_GET_MDIO_REG_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_8197F) & BIT_MASK_MDIO_REG_ADDR_8197F) +#define BIT_SET_MDIO_REG_ADDR_8197F(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_8197F(x) | BIT_MDIO_REG_ADDR_8197F(v)) /* 2 REG_HCI_MIX_CFG_8197F */ #define BIT_RXRST_BACKDOOR_8197F BIT(31) @@ -5912,30 +7480,48 @@ #define BIT_SHIFT_TXDMA_ERR_FLAG_8197F 16 #define BIT_MASK_TXDMA_ERR_FLAG_8197F 0xf -#define BIT_TXDMA_ERR_FLAG_8197F(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8197F) << BIT_SHIFT_TXDMA_ERR_FLAG_8197F) -#define BITS_TXDMA_ERR_FLAG_8197F (BIT_MASK_TXDMA_ERR_FLAG_8197F << BIT_SHIFT_TXDMA_ERR_FLAG_8197F) +#define BIT_TXDMA_ERR_FLAG_8197F(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_8197F) \ + << BIT_SHIFT_TXDMA_ERR_FLAG_8197F) +#define BITS_TXDMA_ERR_FLAG_8197F \ + (BIT_MASK_TXDMA_ERR_FLAG_8197F << BIT_SHIFT_TXDMA_ERR_FLAG_8197F) #define BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8197F)) -#define BIT_GET_TXDMA_ERR_FLAG_8197F(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8197F) & BIT_MASK_TXDMA_ERR_FLAG_8197F) -#define BIT_SET_TXDMA_ERR_FLAG_8197F(x, v) (BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) | BIT_TXDMA_ERR_FLAG_8197F(v)) - +#define BIT_GET_TXDMA_ERR_FLAG_8197F(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8197F) & \ + BIT_MASK_TXDMA_ERR_FLAG_8197F) +#define BIT_SET_TXDMA_ERR_FLAG_8197F(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) | BIT_TXDMA_ERR_FLAG_8197F(v)) #define BIT_SHIFT_EARLY_MODE_SEL_8197F 12 #define BIT_MASK_EARLY_MODE_SEL_8197F 0xf -#define BIT_EARLY_MODE_SEL_8197F(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8197F) << BIT_SHIFT_EARLY_MODE_SEL_8197F) -#define BITS_EARLY_MODE_SEL_8197F (BIT_MASK_EARLY_MODE_SEL_8197F << BIT_SHIFT_EARLY_MODE_SEL_8197F) +#define BIT_EARLY_MODE_SEL_8197F(x) \ + (((x) & BIT_MASK_EARLY_MODE_SEL_8197F) \ + << BIT_SHIFT_EARLY_MODE_SEL_8197F) +#define BITS_EARLY_MODE_SEL_8197F \ + (BIT_MASK_EARLY_MODE_SEL_8197F << BIT_SHIFT_EARLY_MODE_SEL_8197F) #define BIT_CLEAR_EARLY_MODE_SEL_8197F(x) ((x) & (~BITS_EARLY_MODE_SEL_8197F)) -#define BIT_GET_EARLY_MODE_SEL_8197F(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8197F) & BIT_MASK_EARLY_MODE_SEL_8197F) -#define BIT_SET_EARLY_MODE_SEL_8197F(x, v) (BIT_CLEAR_EARLY_MODE_SEL_8197F(x) | BIT_EARLY_MODE_SEL_8197F(v)) +#define BIT_GET_EARLY_MODE_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8197F) & \ + BIT_MASK_EARLY_MODE_SEL_8197F) +#define BIT_SET_EARLY_MODE_SEL_8197F(x, v) \ + (BIT_CLEAR_EARLY_MODE_SEL_8197F(x) | BIT_EARLY_MODE_SEL_8197F(v)) #define BIT_EPHY_RX50_EN_8197F BIT(11) #define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F 8 #define BIT_MASK_MSI_TIMEOUT_ID_V1_8197F 0x7 -#define BIT_MSI_TIMEOUT_ID_V1_8197F(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8197F) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) -#define BITS_MSI_TIMEOUT_ID_V1_8197F (BIT_MASK_MSI_TIMEOUT_ID_V1_8197F << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) -#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8197F)) -#define BIT_GET_MSI_TIMEOUT_ID_V1_8197F(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) & BIT_MASK_MSI_TIMEOUT_ID_V1_8197F) -#define BIT_SET_MSI_TIMEOUT_ID_V1_8197F(x, v) (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) | BIT_MSI_TIMEOUT_ID_V1_8197F(v)) +#define BIT_MSI_TIMEOUT_ID_V1_8197F(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8197F) \ + << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) +#define BITS_MSI_TIMEOUT_ID_V1_8197F \ + (BIT_MASK_MSI_TIMEOUT_ID_V1_8197F << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) \ + ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8197F)) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) & \ + BIT_MASK_MSI_TIMEOUT_ID_V1_8197F) +#define BIT_SET_MSI_TIMEOUT_ID_V1_8197F(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) | BIT_MSI_TIMEOUT_ID_V1_8197F(v)) #define BIT_RADDR_RD_8197F BIT(7) #define BIT_EN_MUL_TAG_8197F BIT(6) @@ -5948,51 +7534,77 @@ #define BIT_SHIFT_STC_INT_FLAG_8197F 16 #define BIT_MASK_STC_INT_FLAG_8197F 0xff -#define BIT_STC_INT_FLAG_8197F(x) (((x) & BIT_MASK_STC_INT_FLAG_8197F) << BIT_SHIFT_STC_INT_FLAG_8197F) -#define BITS_STC_INT_FLAG_8197F (BIT_MASK_STC_INT_FLAG_8197F << BIT_SHIFT_STC_INT_FLAG_8197F) +#define BIT_STC_INT_FLAG_8197F(x) \ + (((x) & BIT_MASK_STC_INT_FLAG_8197F) << BIT_SHIFT_STC_INT_FLAG_8197F) +#define BITS_STC_INT_FLAG_8197F \ + (BIT_MASK_STC_INT_FLAG_8197F << BIT_SHIFT_STC_INT_FLAG_8197F) #define BIT_CLEAR_STC_INT_FLAG_8197F(x) ((x) & (~BITS_STC_INT_FLAG_8197F)) -#define BIT_GET_STC_INT_FLAG_8197F(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8197F) & BIT_MASK_STC_INT_FLAG_8197F) -#define BIT_SET_STC_INT_FLAG_8197F(x, v) (BIT_CLEAR_STC_INT_FLAG_8197F(x) | BIT_STC_INT_FLAG_8197F(v)) - +#define BIT_GET_STC_INT_FLAG_8197F(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG_8197F) & BIT_MASK_STC_INT_FLAG_8197F) +#define BIT_SET_STC_INT_FLAG_8197F(x, v) \ + (BIT_CLEAR_STC_INT_FLAG_8197F(x) | BIT_STC_INT_FLAG_8197F(v)) #define BIT_SHIFT_STC_INT_IDX_8197F 8 #define BIT_MASK_STC_INT_IDX_8197F 0x7 -#define BIT_STC_INT_IDX_8197F(x) (((x) & BIT_MASK_STC_INT_IDX_8197F) << BIT_SHIFT_STC_INT_IDX_8197F) -#define BITS_STC_INT_IDX_8197F (BIT_MASK_STC_INT_IDX_8197F << BIT_SHIFT_STC_INT_IDX_8197F) +#define BIT_STC_INT_IDX_8197F(x) \ + (((x) & BIT_MASK_STC_INT_IDX_8197F) << BIT_SHIFT_STC_INT_IDX_8197F) +#define BITS_STC_INT_IDX_8197F \ + (BIT_MASK_STC_INT_IDX_8197F << BIT_SHIFT_STC_INT_IDX_8197F) #define BIT_CLEAR_STC_INT_IDX_8197F(x) ((x) & (~BITS_STC_INT_IDX_8197F)) -#define BIT_GET_STC_INT_IDX_8197F(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8197F) & BIT_MASK_STC_INT_IDX_8197F) -#define BIT_SET_STC_INT_IDX_8197F(x, v) (BIT_CLEAR_STC_INT_IDX_8197F(x) | BIT_STC_INT_IDX_8197F(v)) - +#define BIT_GET_STC_INT_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX_8197F) & BIT_MASK_STC_INT_IDX_8197F) +#define BIT_SET_STC_INT_IDX_8197F(x, v) \ + (BIT_CLEAR_STC_INT_IDX_8197F(x) | BIT_STC_INT_IDX_8197F(v)) #define BIT_SHIFT_STC_INT_REALTIME_CS_8197F 0 #define BIT_MASK_STC_INT_REALTIME_CS_8197F 0x3f -#define BIT_STC_INT_REALTIME_CS_8197F(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8197F) << BIT_SHIFT_STC_INT_REALTIME_CS_8197F) -#define BITS_STC_INT_REALTIME_CS_8197F (BIT_MASK_STC_INT_REALTIME_CS_8197F << BIT_SHIFT_STC_INT_REALTIME_CS_8197F) -#define BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) ((x) & (~BITS_STC_INT_REALTIME_CS_8197F)) -#define BIT_GET_STC_INT_REALTIME_CS_8197F(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8197F) & BIT_MASK_STC_INT_REALTIME_CS_8197F) -#define BIT_SET_STC_INT_REALTIME_CS_8197F(x, v) (BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) | BIT_STC_INT_REALTIME_CS_8197F(v)) - +#define BIT_STC_INT_REALTIME_CS_8197F(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS_8197F) \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8197F) +#define BITS_STC_INT_REALTIME_CS_8197F \ + (BIT_MASK_STC_INT_REALTIME_CS_8197F \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8197F) +#define BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) \ + ((x) & (~BITS_STC_INT_REALTIME_CS_8197F)) +#define BIT_GET_STC_INT_REALTIME_CS_8197F(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8197F) & \ + BIT_MASK_STC_INT_REALTIME_CS_8197F) +#define BIT_SET_STC_INT_REALTIME_CS_8197F(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) | \ + BIT_STC_INT_REALTIME_CS_8197F(v)) /* 2 REG_ST_INT_CFG_8197F(HCI STATE CHANGE INTERRUPT CONFIGURATION) */ #define BIT_STC_INT_GRP_EN_8197F BIT(31) #define BIT_SHIFT_STC_INT_EXPECT_LS_8197F 8 #define BIT_MASK_STC_INT_EXPECT_LS_8197F 0x3f -#define BIT_STC_INT_EXPECT_LS_8197F(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8197F) << BIT_SHIFT_STC_INT_EXPECT_LS_8197F) -#define BITS_STC_INT_EXPECT_LS_8197F (BIT_MASK_STC_INT_EXPECT_LS_8197F << BIT_SHIFT_STC_INT_EXPECT_LS_8197F) -#define BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) ((x) & (~BITS_STC_INT_EXPECT_LS_8197F)) -#define BIT_GET_STC_INT_EXPECT_LS_8197F(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8197F) & BIT_MASK_STC_INT_EXPECT_LS_8197F) -#define BIT_SET_STC_INT_EXPECT_LS_8197F(x, v) (BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) | BIT_STC_INT_EXPECT_LS_8197F(v)) - +#define BIT_STC_INT_EXPECT_LS_8197F(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS_8197F) \ + << BIT_SHIFT_STC_INT_EXPECT_LS_8197F) +#define BITS_STC_INT_EXPECT_LS_8197F \ + (BIT_MASK_STC_INT_EXPECT_LS_8197F << BIT_SHIFT_STC_INT_EXPECT_LS_8197F) +#define BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) \ + ((x) & (~BITS_STC_INT_EXPECT_LS_8197F)) +#define BIT_GET_STC_INT_EXPECT_LS_8197F(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8197F) & \ + BIT_MASK_STC_INT_EXPECT_LS_8197F) +#define BIT_SET_STC_INT_EXPECT_LS_8197F(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) | BIT_STC_INT_EXPECT_LS_8197F(v)) #define BIT_SHIFT_STC_INT_EXPECT_CS_8197F 0 #define BIT_MASK_STC_INT_EXPECT_CS_8197F 0x3f -#define BIT_STC_INT_EXPECT_CS_8197F(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8197F) << BIT_SHIFT_STC_INT_EXPECT_CS_8197F) -#define BITS_STC_INT_EXPECT_CS_8197F (BIT_MASK_STC_INT_EXPECT_CS_8197F << BIT_SHIFT_STC_INT_EXPECT_CS_8197F) -#define BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) ((x) & (~BITS_STC_INT_EXPECT_CS_8197F)) -#define BIT_GET_STC_INT_EXPECT_CS_8197F(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8197F) & BIT_MASK_STC_INT_EXPECT_CS_8197F) -#define BIT_SET_STC_INT_EXPECT_CS_8197F(x, v) (BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) | BIT_STC_INT_EXPECT_CS_8197F(v)) - +#define BIT_STC_INT_EXPECT_CS_8197F(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS_8197F) \ + << BIT_SHIFT_STC_INT_EXPECT_CS_8197F) +#define BITS_STC_INT_EXPECT_CS_8197F \ + (BIT_MASK_STC_INT_EXPECT_CS_8197F << BIT_SHIFT_STC_INT_EXPECT_CS_8197F) +#define BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) \ + ((x) & (~BITS_STC_INT_EXPECT_CS_8197F)) +#define BIT_GET_STC_INT_EXPECT_CS_8197F(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8197F) & \ + BIT_MASK_STC_INT_EXPECT_CS_8197F) +#define BIT_SET_STC_INT_EXPECT_CS_8197F(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) | BIT_STC_INT_EXPECT_CS_8197F(v)) /* 2 REG_CMU_DLY_CTRL_8197F(HCI PHY CLOCK MGT UNIT DELAY CONTROL ) */ #define BIT_CMU_DLY_EN_8197F BIT(31) @@ -6000,102 +7612,147 @@ #define BIT_SHIFT_CMU_DLY_PRE_DIV_8197F 0 #define BIT_MASK_CMU_DLY_PRE_DIV_8197F 0xff -#define BIT_CMU_DLY_PRE_DIV_8197F(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8197F) << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) -#define BITS_CMU_DLY_PRE_DIV_8197F (BIT_MASK_CMU_DLY_PRE_DIV_8197F << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) +#define BIT_CMU_DLY_PRE_DIV_8197F(x) \ + (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8197F) \ + << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) +#define BITS_CMU_DLY_PRE_DIV_8197F \ + (BIT_MASK_CMU_DLY_PRE_DIV_8197F << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) #define BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8197F)) -#define BIT_GET_CMU_DLY_PRE_DIV_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) & BIT_MASK_CMU_DLY_PRE_DIV_8197F) -#define BIT_SET_CMU_DLY_PRE_DIV_8197F(x, v) (BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) | BIT_CMU_DLY_PRE_DIV_8197F(v)) - +#define BIT_GET_CMU_DLY_PRE_DIV_8197F(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) & \ + BIT_MASK_CMU_DLY_PRE_DIV_8197F) +#define BIT_SET_CMU_DLY_PRE_DIV_8197F(x, v) \ + (BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) | BIT_CMU_DLY_PRE_DIV_8197F(v)) /* 2 REG_CMU_DLY_CFG_8197F(HCI PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ #define BIT_SHIFT_CMU_DLY_LTR_A2I_8197F 24 #define BIT_MASK_CMU_DLY_LTR_A2I_8197F 0xff -#define BIT_CMU_DLY_LTR_A2I_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8197F) << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) -#define BITS_CMU_DLY_LTR_A2I_8197F (BIT_MASK_CMU_DLY_LTR_A2I_8197F << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) +#define BIT_CMU_DLY_LTR_A2I_8197F(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8197F) \ + << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) +#define BITS_CMU_DLY_LTR_A2I_8197F \ + (BIT_MASK_CMU_DLY_LTR_A2I_8197F << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) #define BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8197F)) -#define BIT_GET_CMU_DLY_LTR_A2I_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) & BIT_MASK_CMU_DLY_LTR_A2I_8197F) -#define BIT_SET_CMU_DLY_LTR_A2I_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) | BIT_CMU_DLY_LTR_A2I_8197F(v)) - +#define BIT_GET_CMU_DLY_LTR_A2I_8197F(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) & \ + BIT_MASK_CMU_DLY_LTR_A2I_8197F) +#define BIT_SET_CMU_DLY_LTR_A2I_8197F(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) | BIT_CMU_DLY_LTR_A2I_8197F(v)) #define BIT_SHIFT_CMU_DLY_LTR_I2A_8197F 16 #define BIT_MASK_CMU_DLY_LTR_I2A_8197F 0xff -#define BIT_CMU_DLY_LTR_I2A_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8197F) << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) -#define BITS_CMU_DLY_LTR_I2A_8197F (BIT_MASK_CMU_DLY_LTR_I2A_8197F << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) +#define BIT_CMU_DLY_LTR_I2A_8197F(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8197F) \ + << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) +#define BITS_CMU_DLY_LTR_I2A_8197F \ + (BIT_MASK_CMU_DLY_LTR_I2A_8197F << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) #define BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8197F)) -#define BIT_GET_CMU_DLY_LTR_I2A_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) & BIT_MASK_CMU_DLY_LTR_I2A_8197F) -#define BIT_SET_CMU_DLY_LTR_I2A_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) | BIT_CMU_DLY_LTR_I2A_8197F(v)) - +#define BIT_GET_CMU_DLY_LTR_I2A_8197F(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) & \ + BIT_MASK_CMU_DLY_LTR_I2A_8197F) +#define BIT_SET_CMU_DLY_LTR_I2A_8197F(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) | BIT_CMU_DLY_LTR_I2A_8197F(v)) #define BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F 8 #define BIT_MASK_CMU_DLY_LTR_IDLE_8197F 0xff -#define BIT_CMU_DLY_LTR_IDLE_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8197F) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) -#define BITS_CMU_DLY_LTR_IDLE_8197F (BIT_MASK_CMU_DLY_LTR_IDLE_8197F << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) -#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_IDLE_8197F)) -#define BIT_GET_CMU_DLY_LTR_IDLE_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) & BIT_MASK_CMU_DLY_LTR_IDLE_8197F) -#define BIT_SET_CMU_DLY_LTR_IDLE_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) | BIT_CMU_DLY_LTR_IDLE_8197F(v)) - +#define BIT_CMU_DLY_LTR_IDLE_8197F(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8197F) \ + << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) +#define BITS_CMU_DLY_LTR_IDLE_8197F \ + (BIT_MASK_CMU_DLY_LTR_IDLE_8197F << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) +#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) \ + ((x) & (~BITS_CMU_DLY_LTR_IDLE_8197F)) +#define BIT_GET_CMU_DLY_LTR_IDLE_8197F(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) & \ + BIT_MASK_CMU_DLY_LTR_IDLE_8197F) +#define BIT_SET_CMU_DLY_LTR_IDLE_8197F(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) | BIT_CMU_DLY_LTR_IDLE_8197F(v)) #define BIT_SHIFT_CMU_DLY_LTR_ACT_8197F 0 #define BIT_MASK_CMU_DLY_LTR_ACT_8197F 0xff -#define BIT_CMU_DLY_LTR_ACT_8197F(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8197F) << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) -#define BITS_CMU_DLY_LTR_ACT_8197F (BIT_MASK_CMU_DLY_LTR_ACT_8197F << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) +#define BIT_CMU_DLY_LTR_ACT_8197F(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8197F) \ + << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) +#define BITS_CMU_DLY_LTR_ACT_8197F \ + (BIT_MASK_CMU_DLY_LTR_ACT_8197F << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) #define BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8197F)) -#define BIT_GET_CMU_DLY_LTR_ACT_8197F(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) & BIT_MASK_CMU_DLY_LTR_ACT_8197F) -#define BIT_SET_CMU_DLY_LTR_ACT_8197F(x, v) (BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) | BIT_CMU_DLY_LTR_ACT_8197F(v)) - +#define BIT_GET_CMU_DLY_LTR_ACT_8197F(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) & \ + BIT_MASK_CMU_DLY_LTR_ACT_8197F) +#define BIT_SET_CMU_DLY_LTR_ACT_8197F(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) | BIT_CMU_DLY_LTR_ACT_8197F(v)) /* 2 REG_H2CQ_TXBD_DESA_8197F */ #define BIT_SHIFT_H2CQ_TXBD_DESA_8197F 0 #define BIT_MASK_H2CQ_TXBD_DESA_8197F 0xffffffffffffffffL -#define BIT_H2CQ_TXBD_DESA_8197F(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8197F) << BIT_SHIFT_H2CQ_TXBD_DESA_8197F) -#define BITS_H2CQ_TXBD_DESA_8197F (BIT_MASK_H2CQ_TXBD_DESA_8197F << BIT_SHIFT_H2CQ_TXBD_DESA_8197F) +#define BIT_H2CQ_TXBD_DESA_8197F(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_8197F) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_8197F) +#define BITS_H2CQ_TXBD_DESA_8197F \ + (BIT_MASK_H2CQ_TXBD_DESA_8197F << BIT_SHIFT_H2CQ_TXBD_DESA_8197F) #define BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8197F)) -#define BIT_GET_H2CQ_TXBD_DESA_8197F(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8197F) & BIT_MASK_H2CQ_TXBD_DESA_8197F) -#define BIT_SET_H2CQ_TXBD_DESA_8197F(x, v) (BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) | BIT_H2CQ_TXBD_DESA_8197F(v)) - +#define BIT_GET_H2CQ_TXBD_DESA_8197F(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8197F) & \ + BIT_MASK_H2CQ_TXBD_DESA_8197F) +#define BIT_SET_H2CQ_TXBD_DESA_8197F(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) | BIT_H2CQ_TXBD_DESA_8197F(v)) /* 2 REG_H2CQ_TXBD_NUM_8197F */ #define BIT_HCI_H2CQ_FLAG_8197F BIT(14) #define BIT_SHIFT_H2CQ_DESC_MODE_8197F 12 #define BIT_MASK_H2CQ_DESC_MODE_8197F 0x3 -#define BIT_H2CQ_DESC_MODE_8197F(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8197F) << BIT_SHIFT_H2CQ_DESC_MODE_8197F) -#define BITS_H2CQ_DESC_MODE_8197F (BIT_MASK_H2CQ_DESC_MODE_8197F << BIT_SHIFT_H2CQ_DESC_MODE_8197F) +#define BIT_H2CQ_DESC_MODE_8197F(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE_8197F) \ + << BIT_SHIFT_H2CQ_DESC_MODE_8197F) +#define BITS_H2CQ_DESC_MODE_8197F \ + (BIT_MASK_H2CQ_DESC_MODE_8197F << BIT_SHIFT_H2CQ_DESC_MODE_8197F) #define BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) ((x) & (~BITS_H2CQ_DESC_MODE_8197F)) -#define BIT_GET_H2CQ_DESC_MODE_8197F(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8197F) & BIT_MASK_H2CQ_DESC_MODE_8197F) -#define BIT_SET_H2CQ_DESC_MODE_8197F(x, v) (BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) | BIT_H2CQ_DESC_MODE_8197F(v)) - +#define BIT_GET_H2CQ_DESC_MODE_8197F(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8197F) & \ + BIT_MASK_H2CQ_DESC_MODE_8197F) +#define BIT_SET_H2CQ_DESC_MODE_8197F(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) | BIT_H2CQ_DESC_MODE_8197F(v)) #define BIT_SHIFT_H2CQ_DESC_NUM_8197F 0 #define BIT_MASK_H2CQ_DESC_NUM_8197F 0xfff -#define BIT_H2CQ_DESC_NUM_8197F(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8197F) << BIT_SHIFT_H2CQ_DESC_NUM_8197F) -#define BITS_H2CQ_DESC_NUM_8197F (BIT_MASK_H2CQ_DESC_NUM_8197F << BIT_SHIFT_H2CQ_DESC_NUM_8197F) +#define BIT_H2CQ_DESC_NUM_8197F(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM_8197F) << BIT_SHIFT_H2CQ_DESC_NUM_8197F) +#define BITS_H2CQ_DESC_NUM_8197F \ + (BIT_MASK_H2CQ_DESC_NUM_8197F << BIT_SHIFT_H2CQ_DESC_NUM_8197F) #define BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) ((x) & (~BITS_H2CQ_DESC_NUM_8197F)) -#define BIT_GET_H2CQ_DESC_NUM_8197F(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8197F) & BIT_MASK_H2CQ_DESC_NUM_8197F) -#define BIT_SET_H2CQ_DESC_NUM_8197F(x, v) (BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) | BIT_H2CQ_DESC_NUM_8197F(v)) - +#define BIT_GET_H2CQ_DESC_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8197F) & BIT_MASK_H2CQ_DESC_NUM_8197F) +#define BIT_SET_H2CQ_DESC_NUM_8197F(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) | BIT_H2CQ_DESC_NUM_8197F(v)) /* 2 REG_H2CQ_TXBD_IDX_8197F */ #define BIT_SHIFT_H2CQ_HW_IDX_8197F 16 #define BIT_MASK_H2CQ_HW_IDX_8197F 0xfff -#define BIT_H2CQ_HW_IDX_8197F(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8197F) << BIT_SHIFT_H2CQ_HW_IDX_8197F) -#define BITS_H2CQ_HW_IDX_8197F (BIT_MASK_H2CQ_HW_IDX_8197F << BIT_SHIFT_H2CQ_HW_IDX_8197F) +#define BIT_H2CQ_HW_IDX_8197F(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX_8197F) << BIT_SHIFT_H2CQ_HW_IDX_8197F) +#define BITS_H2CQ_HW_IDX_8197F \ + (BIT_MASK_H2CQ_HW_IDX_8197F << BIT_SHIFT_H2CQ_HW_IDX_8197F) #define BIT_CLEAR_H2CQ_HW_IDX_8197F(x) ((x) & (~BITS_H2CQ_HW_IDX_8197F)) -#define BIT_GET_H2CQ_HW_IDX_8197F(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8197F) & BIT_MASK_H2CQ_HW_IDX_8197F) -#define BIT_SET_H2CQ_HW_IDX_8197F(x, v) (BIT_CLEAR_H2CQ_HW_IDX_8197F(x) | BIT_H2CQ_HW_IDX_8197F(v)) - +#define BIT_GET_H2CQ_HW_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8197F) & BIT_MASK_H2CQ_HW_IDX_8197F) +#define BIT_SET_H2CQ_HW_IDX_8197F(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX_8197F(x) | BIT_H2CQ_HW_IDX_8197F(v)) #define BIT_SHIFT_H2CQ_HOST_IDX_8197F 0 #define BIT_MASK_H2CQ_HOST_IDX_8197F 0xfff -#define BIT_H2CQ_HOST_IDX_8197F(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8197F) << BIT_SHIFT_H2CQ_HOST_IDX_8197F) -#define BITS_H2CQ_HOST_IDX_8197F (BIT_MASK_H2CQ_HOST_IDX_8197F << BIT_SHIFT_H2CQ_HOST_IDX_8197F) +#define BIT_H2CQ_HOST_IDX_8197F(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX_8197F) << BIT_SHIFT_H2CQ_HOST_IDX_8197F) +#define BITS_H2CQ_HOST_IDX_8197F \ + (BIT_MASK_H2CQ_HOST_IDX_8197F << BIT_SHIFT_H2CQ_HOST_IDX_8197F) #define BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) ((x) & (~BITS_H2CQ_HOST_IDX_8197F)) -#define BIT_GET_H2CQ_HOST_IDX_8197F(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8197F) & BIT_MASK_H2CQ_HOST_IDX_8197F) -#define BIT_SET_H2CQ_HOST_IDX_8197F(x, v) (BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) | BIT_H2CQ_HOST_IDX_8197F(v)) - +#define BIT_GET_H2CQ_HOST_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8197F) & BIT_MASK_H2CQ_HOST_IDX_8197F) +#define BIT_SET_H2CQ_HOST_IDX_8197F(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) | BIT_H2CQ_HOST_IDX_8197F(v)) /* 2 REG_H2CQ_CSR_8197F[31:0] (H2CQ CONTROL AND STATUS) */ #define BIT_H2CQ_FULL_8197F BIT(31) @@ -6127,275 +7784,426 @@ #define BIT_SHIFT_AXI_RECOVERY_TIME_8197F 24 #define BIT_MASK_AXI_RECOVERY_TIME_8197F 0xff -#define BIT_AXI_RECOVERY_TIME_8197F(x) (((x) & BIT_MASK_AXI_RECOVERY_TIME_8197F) << BIT_SHIFT_AXI_RECOVERY_TIME_8197F) -#define BITS_AXI_RECOVERY_TIME_8197F (BIT_MASK_AXI_RECOVERY_TIME_8197F << BIT_SHIFT_AXI_RECOVERY_TIME_8197F) -#define BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) ((x) & (~BITS_AXI_RECOVERY_TIME_8197F)) -#define BIT_GET_AXI_RECOVERY_TIME_8197F(x) (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME_8197F) & BIT_MASK_AXI_RECOVERY_TIME_8197F) -#define BIT_SET_AXI_RECOVERY_TIME_8197F(x, v) (BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) | BIT_AXI_RECOVERY_TIME_8197F(v)) - +#define BIT_AXI_RECOVERY_TIME_8197F(x) \ + (((x) & BIT_MASK_AXI_RECOVERY_TIME_8197F) \ + << BIT_SHIFT_AXI_RECOVERY_TIME_8197F) +#define BITS_AXI_RECOVERY_TIME_8197F \ + (BIT_MASK_AXI_RECOVERY_TIME_8197F << BIT_SHIFT_AXI_RECOVERY_TIME_8197F) +#define BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) \ + ((x) & (~BITS_AXI_RECOVERY_TIME_8197F)) +#define BIT_GET_AXI_RECOVERY_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME_8197F) & \ + BIT_MASK_AXI_RECOVERY_TIME_8197F) +#define BIT_SET_AXI_RECOVERY_TIME_8197F(x, v) \ + (BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) | BIT_AXI_RECOVERY_TIME_8197F(v)) #define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F 12 #define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F 0xfff -#define BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(x) (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F) << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) -#define BITS_AXI_RXDMA_TIMEOUT_VAL_8197F (BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) -#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL_8197F)) -#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL_8197F(x) (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F) -#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL_8197F(x, v) (BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) | BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(v)) - +#define BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(x) \ + (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F) \ + << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) +#define BITS_AXI_RXDMA_TIMEOUT_VAL_8197F \ + (BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F \ + << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) +#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) \ + ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL_8197F)) +#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL_8197F(x) \ + (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) & \ + BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F) +#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL_8197F(x, v) \ + (BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) | \ + BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(v)) #define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F 0 #define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F 0xfff -#define BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(x) (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F) << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) -#define BITS_AXI_TXDMA_TIMEOUT_VAL_8197F (BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) -#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL_8197F)) -#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL_8197F(x) (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F) -#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL_8197F(x, v) (BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) | BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(v)) - +#define BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(x) \ + (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F) \ + << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) +#define BITS_AXI_TXDMA_TIMEOUT_VAL_8197F \ + (BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F \ + << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) +#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) \ + ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL_8197F)) +#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL_8197F(x) \ + (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) & \ + BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F) +#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL_8197F(x, v) \ + (BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) | \ + BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(v)) /* 2 REG_Q0_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q0_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q0_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q0_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) -#define BITS_QUEUEMACID_Q0_V1_8197F (BIT_MASK_QUEUEMACID_Q0_V1_8197F << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q0_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q0_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) & BIT_MASK_QUEUEMACID_Q0_V1_8197F) -#define BIT_SET_QUEUEMACID_Q0_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) | BIT_QUEUEMACID_Q0_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q0_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) +#define BITS_QUEUEMACID_Q0_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q0_V1_8197F << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q0_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q0_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q0_V1_8197F) +#define BIT_SET_QUEUEMACID_Q0_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) | BIT_QUEUEMACID_Q0_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q0_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q0_V1_8197F 0x3 -#define BIT_QUEUEAC_Q0_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8197F) << BIT_SHIFT_QUEUEAC_Q0_V1_8197F) -#define BITS_QUEUEAC_Q0_V1_8197F (BIT_MASK_QUEUEAC_Q0_V1_8197F << BIT_SHIFT_QUEUEAC_Q0_V1_8197F) +#define BIT_QUEUEAC_Q0_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q0_V1_8197F) << BIT_SHIFT_QUEUEAC_Q0_V1_8197F) +#define BITS_QUEUEAC_Q0_V1_8197F \ + (BIT_MASK_QUEUEAC_Q0_V1_8197F << BIT_SHIFT_QUEUEAC_Q0_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8197F)) -#define BIT_GET_QUEUEAC_Q0_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8197F) & BIT_MASK_QUEUEAC_Q0_V1_8197F) -#define BIT_SET_QUEUEAC_Q0_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) | BIT_QUEUEAC_Q0_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q0_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8197F) & BIT_MASK_QUEUEAC_Q0_V1_8197F) +#define BIT_SET_QUEUEAC_Q0_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) | BIT_QUEUEAC_Q0_V1_8197F(v)) #define BIT_TIDEMPTY_Q0_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q0_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q0_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q0_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) -#define BITS_TAIL_PKT_Q0_V2_8197F (BIT_MASK_TAIL_PKT_Q0_V2_8197F << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) +#define BIT_TAIL_PKT_Q0_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) +#define BITS_TAIL_PKT_Q0_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q0_V2_8197F << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q0_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) & BIT_MASK_TAIL_PKT_Q0_V2_8197F) -#define BIT_SET_TAIL_PKT_Q0_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) | BIT_TAIL_PKT_Q0_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q0_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q0_V2_8197F) +#define BIT_SET_TAIL_PKT_Q0_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) | BIT_TAIL_PKT_Q0_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q0_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q0_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q0_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) -#define BITS_HEAD_PKT_Q0_V1_8197F (BIT_MASK_HEAD_PKT_Q0_V1_8197F << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) +#define BIT_HEAD_PKT_Q0_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) +#define BITS_HEAD_PKT_Q0_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q0_V1_8197F << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q0_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) & BIT_MASK_HEAD_PKT_Q0_V1_8197F) -#define BIT_SET_HEAD_PKT_Q0_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) | BIT_HEAD_PKT_Q0_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q0_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q0_V1_8197F) +#define BIT_SET_HEAD_PKT_Q0_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) | BIT_HEAD_PKT_Q0_V1_8197F(v)) /* 2 REG_Q1_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q1_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q1_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q1_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) -#define BITS_QUEUEMACID_Q1_V1_8197F (BIT_MASK_QUEUEMACID_Q1_V1_8197F << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q1_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q1_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) & BIT_MASK_QUEUEMACID_Q1_V1_8197F) -#define BIT_SET_QUEUEMACID_Q1_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) | BIT_QUEUEMACID_Q1_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q1_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) +#define BITS_QUEUEMACID_Q1_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q1_V1_8197F << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q1_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q1_V1_8197F) +#define BIT_SET_QUEUEMACID_Q1_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) | BIT_QUEUEMACID_Q1_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q1_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q1_V1_8197F 0x3 -#define BIT_QUEUEAC_Q1_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8197F) << BIT_SHIFT_QUEUEAC_Q1_V1_8197F) -#define BITS_QUEUEAC_Q1_V1_8197F (BIT_MASK_QUEUEAC_Q1_V1_8197F << BIT_SHIFT_QUEUEAC_Q1_V1_8197F) +#define BIT_QUEUEAC_Q1_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q1_V1_8197F) << BIT_SHIFT_QUEUEAC_Q1_V1_8197F) +#define BITS_QUEUEAC_Q1_V1_8197F \ + (BIT_MASK_QUEUEAC_Q1_V1_8197F << BIT_SHIFT_QUEUEAC_Q1_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8197F)) -#define BIT_GET_QUEUEAC_Q1_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8197F) & BIT_MASK_QUEUEAC_Q1_V1_8197F) -#define BIT_SET_QUEUEAC_Q1_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) | BIT_QUEUEAC_Q1_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8197F) & BIT_MASK_QUEUEAC_Q1_V1_8197F) +#define BIT_SET_QUEUEAC_Q1_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) | BIT_QUEUEAC_Q1_V1_8197F(v)) #define BIT_TIDEMPTY_Q1_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q1_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q1_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q1_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) -#define BITS_TAIL_PKT_Q1_V2_8197F (BIT_MASK_TAIL_PKT_Q1_V2_8197F << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) +#define BIT_TAIL_PKT_Q1_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) +#define BITS_TAIL_PKT_Q1_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q1_V2_8197F << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q1_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) & BIT_MASK_TAIL_PKT_Q1_V2_8197F) -#define BIT_SET_TAIL_PKT_Q1_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) | BIT_TAIL_PKT_Q1_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q1_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q1_V2_8197F) +#define BIT_SET_TAIL_PKT_Q1_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) | BIT_TAIL_PKT_Q1_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q1_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q1_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q1_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) -#define BITS_HEAD_PKT_Q1_V1_8197F (BIT_MASK_HEAD_PKT_Q1_V1_8197F << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) +#define BIT_HEAD_PKT_Q1_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) +#define BITS_HEAD_PKT_Q1_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q1_V1_8197F << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q1_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) & BIT_MASK_HEAD_PKT_Q1_V1_8197F) -#define BIT_SET_HEAD_PKT_Q1_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) | BIT_HEAD_PKT_Q1_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q1_V1_8197F) +#define BIT_SET_HEAD_PKT_Q1_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) | BIT_HEAD_PKT_Q1_V1_8197F(v)) /* 2 REG_Q2_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q2_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q2_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q2_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) -#define BITS_QUEUEMACID_Q2_V1_8197F (BIT_MASK_QUEUEMACID_Q2_V1_8197F << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q2_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q2_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) & BIT_MASK_QUEUEMACID_Q2_V1_8197F) -#define BIT_SET_QUEUEMACID_Q2_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) | BIT_QUEUEMACID_Q2_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q2_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) +#define BITS_QUEUEMACID_Q2_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q2_V1_8197F << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q2_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q2_V1_8197F) +#define BIT_SET_QUEUEMACID_Q2_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) | BIT_QUEUEMACID_Q2_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q2_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q2_V1_8197F 0x3 -#define BIT_QUEUEAC_Q2_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8197F) << BIT_SHIFT_QUEUEAC_Q2_V1_8197F) -#define BITS_QUEUEAC_Q2_V1_8197F (BIT_MASK_QUEUEAC_Q2_V1_8197F << BIT_SHIFT_QUEUEAC_Q2_V1_8197F) +#define BIT_QUEUEAC_Q2_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q2_V1_8197F) << BIT_SHIFT_QUEUEAC_Q2_V1_8197F) +#define BITS_QUEUEAC_Q2_V1_8197F \ + (BIT_MASK_QUEUEAC_Q2_V1_8197F << BIT_SHIFT_QUEUEAC_Q2_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8197F)) -#define BIT_GET_QUEUEAC_Q2_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8197F) & BIT_MASK_QUEUEAC_Q2_V1_8197F) -#define BIT_SET_QUEUEAC_Q2_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) | BIT_QUEUEAC_Q2_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8197F) & BIT_MASK_QUEUEAC_Q2_V1_8197F) +#define BIT_SET_QUEUEAC_Q2_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) | BIT_QUEUEAC_Q2_V1_8197F(v)) #define BIT_TIDEMPTY_Q2_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q2_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q2_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q2_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) -#define BITS_TAIL_PKT_Q2_V2_8197F (BIT_MASK_TAIL_PKT_Q2_V2_8197F << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) +#define BIT_TAIL_PKT_Q2_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) +#define BITS_TAIL_PKT_Q2_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q2_V2_8197F << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q2_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) & BIT_MASK_TAIL_PKT_Q2_V2_8197F) -#define BIT_SET_TAIL_PKT_Q2_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) | BIT_TAIL_PKT_Q2_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q2_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q2_V2_8197F) +#define BIT_SET_TAIL_PKT_Q2_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) | BIT_TAIL_PKT_Q2_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q2_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q2_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q2_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) -#define BITS_HEAD_PKT_Q2_V1_8197F (BIT_MASK_HEAD_PKT_Q2_V1_8197F << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) +#define BIT_HEAD_PKT_Q2_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) +#define BITS_HEAD_PKT_Q2_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q2_V1_8197F << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q2_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) & BIT_MASK_HEAD_PKT_Q2_V1_8197F) -#define BIT_SET_HEAD_PKT_Q2_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) | BIT_HEAD_PKT_Q2_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q2_V1_8197F) +#define BIT_SET_HEAD_PKT_Q2_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) | BIT_HEAD_PKT_Q2_V1_8197F(v)) /* 2 REG_Q3_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q3_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q3_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q3_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) -#define BITS_QUEUEMACID_Q3_V1_8197F (BIT_MASK_QUEUEMACID_Q3_V1_8197F << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q3_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q3_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) & BIT_MASK_QUEUEMACID_Q3_V1_8197F) -#define BIT_SET_QUEUEMACID_Q3_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) | BIT_QUEUEMACID_Q3_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q3_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) +#define BITS_QUEUEMACID_Q3_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q3_V1_8197F << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q3_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q3_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q3_V1_8197F) +#define BIT_SET_QUEUEMACID_Q3_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) | BIT_QUEUEMACID_Q3_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q3_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q3_V1_8197F 0x3 -#define BIT_QUEUEAC_Q3_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8197F) << BIT_SHIFT_QUEUEAC_Q3_V1_8197F) -#define BITS_QUEUEAC_Q3_V1_8197F (BIT_MASK_QUEUEAC_Q3_V1_8197F << BIT_SHIFT_QUEUEAC_Q3_V1_8197F) +#define BIT_QUEUEAC_Q3_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q3_V1_8197F) << BIT_SHIFT_QUEUEAC_Q3_V1_8197F) +#define BITS_QUEUEAC_Q3_V1_8197F \ + (BIT_MASK_QUEUEAC_Q3_V1_8197F << BIT_SHIFT_QUEUEAC_Q3_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8197F)) -#define BIT_GET_QUEUEAC_Q3_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8197F) & BIT_MASK_QUEUEAC_Q3_V1_8197F) -#define BIT_SET_QUEUEAC_Q3_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) | BIT_QUEUEAC_Q3_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q3_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8197F) & BIT_MASK_QUEUEAC_Q3_V1_8197F) +#define BIT_SET_QUEUEAC_Q3_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) | BIT_QUEUEAC_Q3_V1_8197F(v)) #define BIT_TIDEMPTY_Q3_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q3_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q3_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q3_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) -#define BITS_TAIL_PKT_Q3_V2_8197F (BIT_MASK_TAIL_PKT_Q3_V2_8197F << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) +#define BIT_TAIL_PKT_Q3_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) +#define BITS_TAIL_PKT_Q3_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q3_V2_8197F << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q3_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) & BIT_MASK_TAIL_PKT_Q3_V2_8197F) -#define BIT_SET_TAIL_PKT_Q3_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) | BIT_TAIL_PKT_Q3_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q3_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q3_V2_8197F) +#define BIT_SET_TAIL_PKT_Q3_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) | BIT_TAIL_PKT_Q3_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q3_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q3_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q3_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) -#define BITS_HEAD_PKT_Q3_V1_8197F (BIT_MASK_HEAD_PKT_Q3_V1_8197F << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) +#define BIT_HEAD_PKT_Q3_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) +#define BITS_HEAD_PKT_Q3_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q3_V1_8197F << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q3_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) & BIT_MASK_HEAD_PKT_Q3_V1_8197F) -#define BIT_SET_HEAD_PKT_Q3_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) | BIT_HEAD_PKT_Q3_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q3_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q3_V1_8197F) +#define BIT_SET_HEAD_PKT_Q3_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) | BIT_HEAD_PKT_Q3_V1_8197F(v)) /* 2 REG_MGQ_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F 25 #define BIT_MASK_QUEUEMACID_MGQ_V1_8197F 0x7f -#define BIT_QUEUEMACID_MGQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8197F) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) -#define BITS_QUEUEMACID_MGQ_V1_8197F (BIT_MASK_QUEUEMACID_MGQ_V1_8197F << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_MGQ_V1_8197F)) -#define BIT_GET_QUEUEMACID_MGQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) & BIT_MASK_QUEUEMACID_MGQ_V1_8197F) -#define BIT_SET_QUEUEMACID_MGQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) | BIT_QUEUEMACID_MGQ_V1_8197F(v)) - +#define BIT_QUEUEMACID_MGQ_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) +#define BITS_QUEUEMACID_MGQ_V1_8197F \ + (BIT_MASK_QUEUEMACID_MGQ_V1_8197F << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_MGQ_V1_8197F)) +#define BIT_GET_QUEUEMACID_MGQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) & \ + BIT_MASK_QUEUEMACID_MGQ_V1_8197F) +#define BIT_SET_QUEUEMACID_MGQ_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) | BIT_QUEUEMACID_MGQ_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_MGQ_V1_8197F 23 #define BIT_MASK_QUEUEAC_MGQ_V1_8197F 0x3 -#define BIT_QUEUEAC_MGQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8197F) << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) -#define BITS_QUEUEAC_MGQ_V1_8197F (BIT_MASK_QUEUEAC_MGQ_V1_8197F << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) +#define BIT_QUEUEAC_MGQ_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8197F) \ + << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) +#define BITS_QUEUEAC_MGQ_V1_8197F \ + (BIT_MASK_QUEUEAC_MGQ_V1_8197F << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) #define BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8197F)) -#define BIT_GET_QUEUEAC_MGQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) & BIT_MASK_QUEUEAC_MGQ_V1_8197F) -#define BIT_SET_QUEUEAC_MGQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) | BIT_QUEUEAC_MGQ_V1_8197F(v)) +#define BIT_GET_QUEUEAC_MGQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) & \ + BIT_MASK_QUEUEAC_MGQ_V1_8197F) +#define BIT_SET_QUEUEAC_MGQ_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) | BIT_QUEUEAC_MGQ_V1_8197F(v)) #define BIT_TIDEMPTY_MGQ_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F 11 #define BIT_MASK_TAIL_PKT_MGQ_V2_8197F 0x7ff -#define BIT_TAIL_PKT_MGQ_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8197F) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) -#define BITS_TAIL_PKT_MGQ_V2_8197F (BIT_MASK_TAIL_PKT_MGQ_V2_8197F << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) +#define BIT_TAIL_PKT_MGQ_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) +#define BITS_TAIL_PKT_MGQ_V2_8197F \ + (BIT_MASK_TAIL_PKT_MGQ_V2_8197F << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) #define BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8197F)) -#define BIT_GET_TAIL_PKT_MGQ_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) & BIT_MASK_TAIL_PKT_MGQ_V2_8197F) -#define BIT_SET_TAIL_PKT_MGQ_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) | BIT_TAIL_PKT_MGQ_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_MGQ_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) & \ + BIT_MASK_TAIL_PKT_MGQ_V2_8197F) +#define BIT_SET_TAIL_PKT_MGQ_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) | BIT_TAIL_PKT_MGQ_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F 0 #define BIT_MASK_HEAD_PKT_MGQ_V1_8197F 0x7ff -#define BIT_HEAD_PKT_MGQ_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8197F) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) -#define BITS_HEAD_PKT_MGQ_V1_8197F (BIT_MASK_HEAD_PKT_MGQ_V1_8197F << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) +#define BIT_HEAD_PKT_MGQ_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) +#define BITS_HEAD_PKT_MGQ_V1_8197F \ + (BIT_MASK_HEAD_PKT_MGQ_V1_8197F << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) #define BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8197F)) -#define BIT_GET_HEAD_PKT_MGQ_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) & BIT_MASK_HEAD_PKT_MGQ_V1_8197F) -#define BIT_SET_HEAD_PKT_MGQ_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) | BIT_HEAD_PKT_MGQ_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_MGQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) & \ + BIT_MASK_HEAD_PKT_MGQ_V1_8197F) +#define BIT_SET_HEAD_PKT_MGQ_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) | BIT_HEAD_PKT_MGQ_V1_8197F(v)) /* 2 REG_HIQ_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F 25 #define BIT_MASK_QUEUEMACID_HIQ_V1_8197F 0x7f -#define BIT_QUEUEMACID_HIQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8197F) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) -#define BITS_QUEUEMACID_HIQ_V1_8197F (BIT_MASK_QUEUEMACID_HIQ_V1_8197F << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_HIQ_V1_8197F)) -#define BIT_GET_QUEUEMACID_HIQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) & BIT_MASK_QUEUEMACID_HIQ_V1_8197F) -#define BIT_SET_QUEUEMACID_HIQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) | BIT_QUEUEMACID_HIQ_V1_8197F(v)) - +#define BIT_QUEUEMACID_HIQ_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) +#define BITS_QUEUEMACID_HIQ_V1_8197F \ + (BIT_MASK_QUEUEMACID_HIQ_V1_8197F << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_HIQ_V1_8197F)) +#define BIT_GET_QUEUEMACID_HIQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) & \ + BIT_MASK_QUEUEMACID_HIQ_V1_8197F) +#define BIT_SET_QUEUEMACID_HIQ_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) | BIT_QUEUEMACID_HIQ_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_HIQ_V1_8197F 23 #define BIT_MASK_QUEUEAC_HIQ_V1_8197F 0x3 -#define BIT_QUEUEAC_HIQ_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8197F) << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) -#define BITS_QUEUEAC_HIQ_V1_8197F (BIT_MASK_QUEUEAC_HIQ_V1_8197F << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) +#define BIT_QUEUEAC_HIQ_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8197F) \ + << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) +#define BITS_QUEUEAC_HIQ_V1_8197F \ + (BIT_MASK_QUEUEAC_HIQ_V1_8197F << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) #define BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8197F)) -#define BIT_GET_QUEUEAC_HIQ_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) & BIT_MASK_QUEUEAC_HIQ_V1_8197F) -#define BIT_SET_QUEUEAC_HIQ_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) | BIT_QUEUEAC_HIQ_V1_8197F(v)) +#define BIT_GET_QUEUEAC_HIQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) & \ + BIT_MASK_QUEUEAC_HIQ_V1_8197F) +#define BIT_SET_QUEUEAC_HIQ_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) | BIT_QUEUEAC_HIQ_V1_8197F(v)) #define BIT_TIDEMPTY_HIQ_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F 11 #define BIT_MASK_TAIL_PKT_HIQ_V2_8197F 0x7ff -#define BIT_TAIL_PKT_HIQ_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8197F) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) -#define BITS_TAIL_PKT_HIQ_V2_8197F (BIT_MASK_TAIL_PKT_HIQ_V2_8197F << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) +#define BIT_TAIL_PKT_HIQ_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) +#define BITS_TAIL_PKT_HIQ_V2_8197F \ + (BIT_MASK_TAIL_PKT_HIQ_V2_8197F << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) #define BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8197F)) -#define BIT_GET_TAIL_PKT_HIQ_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) & BIT_MASK_TAIL_PKT_HIQ_V2_8197F) -#define BIT_SET_TAIL_PKT_HIQ_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) | BIT_TAIL_PKT_HIQ_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_HIQ_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) & \ + BIT_MASK_TAIL_PKT_HIQ_V2_8197F) +#define BIT_SET_TAIL_PKT_HIQ_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) | BIT_TAIL_PKT_HIQ_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F 0 #define BIT_MASK_HEAD_PKT_HIQ_V1_8197F 0x7ff -#define BIT_HEAD_PKT_HIQ_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8197F) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) -#define BITS_HEAD_PKT_HIQ_V1_8197F (BIT_MASK_HEAD_PKT_HIQ_V1_8197F << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) +#define BIT_HEAD_PKT_HIQ_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) +#define BITS_HEAD_PKT_HIQ_V1_8197F \ + (BIT_MASK_HEAD_PKT_HIQ_V1_8197F << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) #define BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8197F)) -#define BIT_GET_HEAD_PKT_HIQ_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) & BIT_MASK_HEAD_PKT_HIQ_V1_8197F) -#define BIT_SET_HEAD_PKT_HIQ_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) | BIT_HEAD_PKT_HIQ_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_HIQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) & \ + BIT_MASK_HEAD_PKT_HIQ_V1_8197F) +#define BIT_SET_HEAD_PKT_HIQ_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) | BIT_HEAD_PKT_HIQ_V1_8197F(v)) /* 2 REG_BCNQ_INFO_8197F */ #define BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F 0 #define BIT_MASK_BCNQ_HEAD_PG_V1_8197F 0xfff -#define BIT_BCNQ_HEAD_PG_V1_8197F(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8197F) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) -#define BITS_BCNQ_HEAD_PG_V1_8197F (BIT_MASK_BCNQ_HEAD_PG_V1_8197F << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) +#define BIT_BCNQ_HEAD_PG_V1_8197F(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8197F) \ + << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) +#define BITS_BCNQ_HEAD_PG_V1_8197F \ + (BIT_MASK_BCNQ_HEAD_PG_V1_8197F << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) #define BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8197F)) -#define BIT_GET_BCNQ_HEAD_PG_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) & BIT_MASK_BCNQ_HEAD_PG_V1_8197F) -#define BIT_SET_BCNQ_HEAD_PG_V1_8197F(x, v) (BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) | BIT_BCNQ_HEAD_PG_V1_8197F(v)) - +#define BIT_GET_BCNQ_HEAD_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) & \ + BIT_MASK_BCNQ_HEAD_PG_V1_8197F) +#define BIT_SET_BCNQ_HEAD_PG_V1_8197F(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) | BIT_BCNQ_HEAD_PG_V1_8197F(v)) /* 2 REG_TXPKT_EMPTY_8197F */ #define BIT_BCNQ_EMPTY_8197F BIT(11) @@ -6419,12 +8227,17 @@ #define BIT_SHIFT_FW_FREE_TAIL_V1_8197F 0 #define BIT_MASK_FW_FREE_TAIL_V1_8197F 0xfff -#define BIT_FW_FREE_TAIL_V1_8197F(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8197F) << BIT_SHIFT_FW_FREE_TAIL_V1_8197F) -#define BITS_FW_FREE_TAIL_V1_8197F (BIT_MASK_FW_FREE_TAIL_V1_8197F << BIT_SHIFT_FW_FREE_TAIL_V1_8197F) +#define BIT_FW_FREE_TAIL_V1_8197F(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL_V1_8197F) \ + << BIT_SHIFT_FW_FREE_TAIL_V1_8197F) +#define BITS_FW_FREE_TAIL_V1_8197F \ + (BIT_MASK_FW_FREE_TAIL_V1_8197F << BIT_SHIFT_FW_FREE_TAIL_V1_8197F) #define BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8197F)) -#define BIT_GET_FW_FREE_TAIL_V1_8197F(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8197F) & BIT_MASK_FW_FREE_TAIL_V1_8197F) -#define BIT_SET_FW_FREE_TAIL_V1_8197F(x, v) (BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) | BIT_FW_FREE_TAIL_V1_8197F(v)) - +#define BIT_GET_FW_FREE_TAIL_V1_8197F(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8197F) & \ + BIT_MASK_FW_FREE_TAIL_V1_8197F) +#define BIT_SET_FW_FREE_TAIL_V1_8197F(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) | BIT_FW_FREE_TAIL_V1_8197F(v)) /* 2 REG_FWHW_TXQ_CTRL_8197F */ #define BIT_RTS_LIMIT_IN_OFDM_8197F BIT(23) @@ -6434,11 +8247,15 @@ #define BIT_SHIFT_EN_QUEUE_RPT_8197F 8 #define BIT_MASK_EN_QUEUE_RPT_8197F 0xff -#define BIT_EN_QUEUE_RPT_8197F(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8197F) << BIT_SHIFT_EN_QUEUE_RPT_8197F) -#define BITS_EN_QUEUE_RPT_8197F (BIT_MASK_EN_QUEUE_RPT_8197F << BIT_SHIFT_EN_QUEUE_RPT_8197F) +#define BIT_EN_QUEUE_RPT_8197F(x) \ + (((x) & BIT_MASK_EN_QUEUE_RPT_8197F) << BIT_SHIFT_EN_QUEUE_RPT_8197F) +#define BITS_EN_QUEUE_RPT_8197F \ + (BIT_MASK_EN_QUEUE_RPT_8197F << BIT_SHIFT_EN_QUEUE_RPT_8197F) #define BIT_CLEAR_EN_QUEUE_RPT_8197F(x) ((x) & (~BITS_EN_QUEUE_RPT_8197F)) -#define BIT_GET_EN_QUEUE_RPT_8197F(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8197F) & BIT_MASK_EN_QUEUE_RPT_8197F) -#define BIT_SET_EN_QUEUE_RPT_8197F(x, v) (BIT_CLEAR_EN_QUEUE_RPT_8197F(x) | BIT_EN_QUEUE_RPT_8197F(v)) +#define BIT_GET_EN_QUEUE_RPT_8197F(x) \ + (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8197F) & BIT_MASK_EN_QUEUE_RPT_8197F) +#define BIT_SET_EN_QUEUE_RPT_8197F(x, v) \ + (BIT_CLEAR_EN_QUEUE_RPT_8197F(x) | BIT_EN_QUEUE_RPT_8197F(v)) #define BIT_EN_RTY_BK_8197F BIT(7) #define BIT_EN_USE_INI_RAT_8197F BIT(6) @@ -6454,23 +8271,36 @@ #define BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F 0 #define BIT_MASK__R_DATA_FALLBACK_SEL_8197F 0x3 -#define BIT__R_DATA_FALLBACK_SEL_8197F(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8197F) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) -#define BITS__R_DATA_FALLBACK_SEL_8197F (BIT_MASK__R_DATA_FALLBACK_SEL_8197F << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) -#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) ((x) & (~BITS__R_DATA_FALLBACK_SEL_8197F)) -#define BIT_GET__R_DATA_FALLBACK_SEL_8197F(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) & BIT_MASK__R_DATA_FALLBACK_SEL_8197F) -#define BIT_SET__R_DATA_FALLBACK_SEL_8197F(x, v) (BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) | BIT__R_DATA_FALLBACK_SEL_8197F(v)) - +#define BIT__R_DATA_FALLBACK_SEL_8197F(x) \ + (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8197F) \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) +#define BITS__R_DATA_FALLBACK_SEL_8197F \ + (BIT_MASK__R_DATA_FALLBACK_SEL_8197F \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) +#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) \ + ((x) & (~BITS__R_DATA_FALLBACK_SEL_8197F)) +#define BIT_GET__R_DATA_FALLBACK_SEL_8197F(x) \ + (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) & \ + BIT_MASK__R_DATA_FALLBACK_SEL_8197F) +#define BIT_SET__R_DATA_FALLBACK_SEL_8197F(x, v) \ + (BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) | \ + BIT__R_DATA_FALLBACK_SEL_8197F(v)) /* 2 REG_BCNQ_BDNY_V1_8197F */ #define BIT_SHIFT_BCNQ_PGBNDY_V1_8197F 0 #define BIT_MASK_BCNQ_PGBNDY_V1_8197F 0xfff -#define BIT_BCNQ_PGBNDY_V1_8197F(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8197F) << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) -#define BITS_BCNQ_PGBNDY_V1_8197F (BIT_MASK_BCNQ_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) +#define BIT_BCNQ_PGBNDY_V1_8197F(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8197F) \ + << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) +#define BITS_BCNQ_PGBNDY_V1_8197F \ + (BIT_MASK_BCNQ_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) #define BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8197F)) -#define BIT_GET_BCNQ_PGBNDY_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) & BIT_MASK_BCNQ_PGBNDY_V1_8197F) -#define BIT_SET_BCNQ_PGBNDY_V1_8197F(x, v) (BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) | BIT_BCNQ_PGBNDY_V1_8197F(v)) - +#define BIT_GET_BCNQ_PGBNDY_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) & \ + BIT_MASK_BCNQ_PGBNDY_V1_8197F) +#define BIT_SET_BCNQ_PGBNDY_V1_8197F(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) | BIT_BCNQ_PGBNDY_V1_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -6489,21 +8319,37 @@ #define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F 8 #define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F 0xff -#define BIT_SPEC_SIFS_OFDM_PTCL_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) -#define BITS_SPEC_SIFS_OFDM_PTCL_8197F (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) -#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8197F)) -#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F) -#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) | BIT_SPEC_SIFS_OFDM_PTCL_8197F(v)) - +#define BIT_SPEC_SIFS_OFDM_PTCL_8197F(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) +#define BITS_SPEC_SIFS_OFDM_PTCL_8197F \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) \ + ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8197F)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8197F(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) & \ + BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8197F(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) | \ + BIT_SPEC_SIFS_OFDM_PTCL_8197F(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F 0 #define BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F 0xff -#define BIT_SPEC_SIFS_CCK_PTCL_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) -#define BITS_SPEC_SIFS_CCK_PTCL_8197F (BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) -#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8197F)) -#define BIT_GET_SPEC_SIFS_CCK_PTCL_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F) -#define BIT_SET_SPEC_SIFS_CCK_PTCL_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) | BIT_SPEC_SIFS_CCK_PTCL_8197F(v)) - +#define BIT_SPEC_SIFS_CCK_PTCL_8197F(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F) \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) +#define BITS_SPEC_SIFS_CCK_PTCL_8197F \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) \ + ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8197F)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8197F(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) & \ + BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F) +#define BIT_SET_SPEC_SIFS_CCK_PTCL_8197F(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) | \ + BIT_SPEC_SIFS_CCK_PTCL_8197F(v)) /* 2 REG_RETRY_LIMIT_8197F */ @@ -6515,7 +8361,6 @@ #define BIT_GET_SRL_8197F(x) (((x) >> BIT_SHIFT_SRL_8197F) & BIT_MASK_SRL_8197F) #define BIT_SET_SRL_8197F(x, v) (BIT_CLEAR_SRL_8197F(x) | BIT_SRL_8197F(v)) - #define BIT_SHIFT_LRL_8197F 0 #define BIT_MASK_LRL_8197F 0x3f #define BIT_LRL_8197F(x) (((x) & BIT_MASK_LRL_8197F) << BIT_SHIFT_LRL_8197F) @@ -6524,7 +8369,6 @@ #define BIT_GET_LRL_8197F(x) (((x) >> BIT_SHIFT_LRL_8197F) & BIT_MASK_LRL_8197F) #define BIT_SET_LRL_8197F(x, v) (BIT_CLEAR_LRL_8197F(x) | BIT_LRL_8197F(v)) - /* 2 REG_TXBF_CTRL_8197F */ #define BIT_R_ENABLE_NDPA_8197F BIT(31) #define BIT_USE_NDPA_PARAMETER_8197F BIT(30) @@ -6536,11 +8380,15 @@ #define BIT_SHIFT_R_TXBF1_AID_8197F 16 #define BIT_MASK_R_TXBF1_AID_8197F 0x1ff -#define BIT_R_TXBF1_AID_8197F(x) (((x) & BIT_MASK_R_TXBF1_AID_8197F) << BIT_SHIFT_R_TXBF1_AID_8197F) -#define BITS_R_TXBF1_AID_8197F (BIT_MASK_R_TXBF1_AID_8197F << BIT_SHIFT_R_TXBF1_AID_8197F) +#define BIT_R_TXBF1_AID_8197F(x) \ + (((x) & BIT_MASK_R_TXBF1_AID_8197F) << BIT_SHIFT_R_TXBF1_AID_8197F) +#define BITS_R_TXBF1_AID_8197F \ + (BIT_MASK_R_TXBF1_AID_8197F << BIT_SHIFT_R_TXBF1_AID_8197F) #define BIT_CLEAR_R_TXBF1_AID_8197F(x) ((x) & (~BITS_R_TXBF1_AID_8197F)) -#define BIT_GET_R_TXBF1_AID_8197F(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8197F) & BIT_MASK_R_TXBF1_AID_8197F) -#define BIT_SET_R_TXBF1_AID_8197F(x, v) (BIT_CLEAR_R_TXBF1_AID_8197F(x) | BIT_R_TXBF1_AID_8197F(v)) +#define BIT_GET_R_TXBF1_AID_8197F(x) \ + (((x) >> BIT_SHIFT_R_TXBF1_AID_8197F) & BIT_MASK_R_TXBF1_AID_8197F) +#define BIT_SET_R_TXBF1_AID_8197F(x, v) \ + (BIT_CLEAR_R_TXBF1_AID_8197F(x) | BIT_R_TXBF1_AID_8197F(v)) #define BIT_DIS_NDP_BFEN_8197F BIT(15) #define BIT_R_TXBCN_NOBLOCK_NDP_8197F BIT(14) @@ -6550,160 +8398,211 @@ #define BIT_SHIFT_R_TXBF0_AID_8197F 0 #define BIT_MASK_R_TXBF0_AID_8197F 0x1ff -#define BIT_R_TXBF0_AID_8197F(x) (((x) & BIT_MASK_R_TXBF0_AID_8197F) << BIT_SHIFT_R_TXBF0_AID_8197F) -#define BITS_R_TXBF0_AID_8197F (BIT_MASK_R_TXBF0_AID_8197F << BIT_SHIFT_R_TXBF0_AID_8197F) +#define BIT_R_TXBF0_AID_8197F(x) \ + (((x) & BIT_MASK_R_TXBF0_AID_8197F) << BIT_SHIFT_R_TXBF0_AID_8197F) +#define BITS_R_TXBF0_AID_8197F \ + (BIT_MASK_R_TXBF0_AID_8197F << BIT_SHIFT_R_TXBF0_AID_8197F) #define BIT_CLEAR_R_TXBF0_AID_8197F(x) ((x) & (~BITS_R_TXBF0_AID_8197F)) -#define BIT_GET_R_TXBF0_AID_8197F(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8197F) & BIT_MASK_R_TXBF0_AID_8197F) -#define BIT_SET_R_TXBF0_AID_8197F(x, v) (BIT_CLEAR_R_TXBF0_AID_8197F(x) | BIT_R_TXBF0_AID_8197F(v)) - +#define BIT_GET_R_TXBF0_AID_8197F(x) \ + (((x) >> BIT_SHIFT_R_TXBF0_AID_8197F) & BIT_MASK_R_TXBF0_AID_8197F) +#define BIT_SET_R_TXBF0_AID_8197F(x, v) \ + (BIT_CLEAR_R_TXBF0_AID_8197F(x) | BIT_R_TXBF0_AID_8197F(v)) /* 2 REG_DARFRC_8197F */ -#define BIT_SHIFT_DARF_RC8_8197F (56 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC8_8197F 0x1f -#define BIT_DARF_RC8_8197F(x) (((x) & BIT_MASK_DARF_RC8_8197F) << BIT_SHIFT_DARF_RC8_8197F) -#define BITS_DARF_RC8_8197F (BIT_MASK_DARF_RC8_8197F << BIT_SHIFT_DARF_RC8_8197F) -#define BIT_CLEAR_DARF_RC8_8197F(x) ((x) & (~BITS_DARF_RC8_8197F)) -#define BIT_GET_DARF_RC8_8197F(x) (((x) >> BIT_SHIFT_DARF_RC8_8197F) & BIT_MASK_DARF_RC8_8197F) -#define BIT_SET_DARF_RC8_8197F(x, v) (BIT_CLEAR_DARF_RC8_8197F(x) | BIT_DARF_RC8_8197F(v)) - - -#define BIT_SHIFT_DARF_RC7_8197F (48 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC7_8197F 0x1f -#define BIT_DARF_RC7_8197F(x) (((x) & BIT_MASK_DARF_RC7_8197F) << BIT_SHIFT_DARF_RC7_8197F) -#define BITS_DARF_RC7_8197F (BIT_MASK_DARF_RC7_8197F << BIT_SHIFT_DARF_RC7_8197F) -#define BIT_CLEAR_DARF_RC7_8197F(x) ((x) & (~BITS_DARF_RC7_8197F)) -#define BIT_GET_DARF_RC7_8197F(x) (((x) >> BIT_SHIFT_DARF_RC7_8197F) & BIT_MASK_DARF_RC7_8197F) -#define BIT_SET_DARF_RC7_8197F(x, v) (BIT_CLEAR_DARF_RC7_8197F(x) | BIT_DARF_RC7_8197F(v)) - - -#define BIT_SHIFT_DARF_RC6_8197F (40 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC6_8197F 0x1f -#define BIT_DARF_RC6_8197F(x) (((x) & BIT_MASK_DARF_RC6_8197F) << BIT_SHIFT_DARF_RC6_8197F) -#define BITS_DARF_RC6_8197F (BIT_MASK_DARF_RC6_8197F << BIT_SHIFT_DARF_RC6_8197F) -#define BIT_CLEAR_DARF_RC6_8197F(x) ((x) & (~BITS_DARF_RC6_8197F)) -#define BIT_GET_DARF_RC6_8197F(x) (((x) >> BIT_SHIFT_DARF_RC6_8197F) & BIT_MASK_DARF_RC6_8197F) -#define BIT_SET_DARF_RC6_8197F(x, v) (BIT_CLEAR_DARF_RC6_8197F(x) | BIT_DARF_RC6_8197F(v)) - - -#define BIT_SHIFT_DARF_RC5_8197F (32 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC5_8197F 0x1f -#define BIT_DARF_RC5_8197F(x) (((x) & BIT_MASK_DARF_RC5_8197F) << BIT_SHIFT_DARF_RC5_8197F) -#define BITS_DARF_RC5_8197F (BIT_MASK_DARF_RC5_8197F << BIT_SHIFT_DARF_RC5_8197F) -#define BIT_CLEAR_DARF_RC5_8197F(x) ((x) & (~BITS_DARF_RC5_8197F)) -#define BIT_GET_DARF_RC5_8197F(x) (((x) >> BIT_SHIFT_DARF_RC5_8197F) & BIT_MASK_DARF_RC5_8197F) -#define BIT_SET_DARF_RC5_8197F(x, v) (BIT_CLEAR_DARF_RC5_8197F(x) | BIT_DARF_RC5_8197F(v)) - - -#define BIT_SHIFT_DARF_RC4_8197F 24 -#define BIT_MASK_DARF_RC4_8197F 0x1f -#define BIT_DARF_RC4_8197F(x) (((x) & BIT_MASK_DARF_RC4_8197F) << BIT_SHIFT_DARF_RC4_8197F) -#define BITS_DARF_RC4_8197F (BIT_MASK_DARF_RC4_8197F << BIT_SHIFT_DARF_RC4_8197F) -#define BIT_CLEAR_DARF_RC4_8197F(x) ((x) & (~BITS_DARF_RC4_8197F)) -#define BIT_GET_DARF_RC4_8197F(x) (((x) >> BIT_SHIFT_DARF_RC4_8197F) & BIT_MASK_DARF_RC4_8197F) -#define BIT_SET_DARF_RC4_8197F(x, v) (BIT_CLEAR_DARF_RC4_8197F(x) | BIT_DARF_RC4_8197F(v)) - - -#define BIT_SHIFT_DARF_RC3_8197F 16 -#define BIT_MASK_DARF_RC3_8197F 0x1f -#define BIT_DARF_RC3_8197F(x) (((x) & BIT_MASK_DARF_RC3_8197F) << BIT_SHIFT_DARF_RC3_8197F) -#define BITS_DARF_RC3_8197F (BIT_MASK_DARF_RC3_8197F << BIT_SHIFT_DARF_RC3_8197F) -#define BIT_CLEAR_DARF_RC3_8197F(x) ((x) & (~BITS_DARF_RC3_8197F)) -#define BIT_GET_DARF_RC3_8197F(x) (((x) >> BIT_SHIFT_DARF_RC3_8197F) & BIT_MASK_DARF_RC3_8197F) -#define BIT_SET_DARF_RC3_8197F(x, v) (BIT_CLEAR_DARF_RC3_8197F(x) | BIT_DARF_RC3_8197F(v)) - - -#define BIT_SHIFT_DARF_RC2_8197F 8 -#define BIT_MASK_DARF_RC2_8197F 0x1f -#define BIT_DARF_RC2_8197F(x) (((x) & BIT_MASK_DARF_RC2_8197F) << BIT_SHIFT_DARF_RC2_8197F) -#define BITS_DARF_RC2_8197F (BIT_MASK_DARF_RC2_8197F << BIT_SHIFT_DARF_RC2_8197F) -#define BIT_CLEAR_DARF_RC2_8197F(x) ((x) & (~BITS_DARF_RC2_8197F)) -#define BIT_GET_DARF_RC2_8197F(x) (((x) >> BIT_SHIFT_DARF_RC2_8197F) & BIT_MASK_DARF_RC2_8197F) -#define BIT_SET_DARF_RC2_8197F(x, v) (BIT_CLEAR_DARF_RC2_8197F(x) | BIT_DARF_RC2_8197F(v)) - - -#define BIT_SHIFT_DARF_RC1_8197F 0 -#define BIT_MASK_DARF_RC1_8197F 0x1f -#define BIT_DARF_RC1_8197F(x) (((x) & BIT_MASK_DARF_RC1_8197F) << BIT_SHIFT_DARF_RC1_8197F) -#define BITS_DARF_RC1_8197F (BIT_MASK_DARF_RC1_8197F << BIT_SHIFT_DARF_RC1_8197F) -#define BIT_CLEAR_DARF_RC1_8197F(x) ((x) & (~BITS_DARF_RC1_8197F)) -#define BIT_GET_DARF_RC1_8197F(x) (((x) >> BIT_SHIFT_DARF_RC1_8197F) & BIT_MASK_DARF_RC1_8197F) -#define BIT_SET_DARF_RC1_8197F(x, v) (BIT_CLEAR_DARF_RC1_8197F(x) | BIT_DARF_RC1_8197F(v)) - +#define BIT_SHIFT_DARF_RC8_V2_8197F (56 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC8_V2_8197F 0x3f +#define BIT_DARF_RC8_V2_8197F(x) \ + (((x) & BIT_MASK_DARF_RC8_V2_8197F) << BIT_SHIFT_DARF_RC8_V2_8197F) +#define BITS_DARF_RC8_V2_8197F \ + (BIT_MASK_DARF_RC8_V2_8197F << BIT_SHIFT_DARF_RC8_V2_8197F) +#define BIT_CLEAR_DARF_RC8_V2_8197F(x) ((x) & (~BITS_DARF_RC8_V2_8197F)) +#define BIT_GET_DARF_RC8_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_V2_8197F) & BIT_MASK_DARF_RC8_V2_8197F) +#define BIT_SET_DARF_RC8_V2_8197F(x, v) \ + (BIT_CLEAR_DARF_RC8_V2_8197F(x) | BIT_DARF_RC8_V2_8197F(v)) + +#define BIT_SHIFT_DARF_RC7_V2_8197F (48 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC7_V2_8197F 0x3f +#define BIT_DARF_RC7_V2_8197F(x) \ + (((x) & BIT_MASK_DARF_RC7_V2_8197F) << BIT_SHIFT_DARF_RC7_V2_8197F) +#define BITS_DARF_RC7_V2_8197F \ + (BIT_MASK_DARF_RC7_V2_8197F << BIT_SHIFT_DARF_RC7_V2_8197F) +#define BIT_CLEAR_DARF_RC7_V2_8197F(x) ((x) & (~BITS_DARF_RC7_V2_8197F)) +#define BIT_GET_DARF_RC7_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_V2_8197F) & BIT_MASK_DARF_RC7_V2_8197F) +#define BIT_SET_DARF_RC7_V2_8197F(x, v) \ + (BIT_CLEAR_DARF_RC7_V2_8197F(x) | BIT_DARF_RC7_V2_8197F(v)) + +#define BIT_SHIFT_DARF_RC6_V2_8197F (40 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC6_V2_8197F 0x3f +#define BIT_DARF_RC6_V2_8197F(x) \ + (((x) & BIT_MASK_DARF_RC6_V2_8197F) << BIT_SHIFT_DARF_RC6_V2_8197F) +#define BITS_DARF_RC6_V2_8197F \ + (BIT_MASK_DARF_RC6_V2_8197F << BIT_SHIFT_DARF_RC6_V2_8197F) +#define BIT_CLEAR_DARF_RC6_V2_8197F(x) ((x) & (~BITS_DARF_RC6_V2_8197F)) +#define BIT_GET_DARF_RC6_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_V2_8197F) & BIT_MASK_DARF_RC6_V2_8197F) +#define BIT_SET_DARF_RC6_V2_8197F(x, v) \ + (BIT_CLEAR_DARF_RC6_V2_8197F(x) | BIT_DARF_RC6_V2_8197F(v)) + +#define BIT_SHIFT_DARF_RC5_V2_8197F (32 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC5_V2_8197F 0x3f +#define BIT_DARF_RC5_V2_8197F(x) \ + (((x) & BIT_MASK_DARF_RC5_V2_8197F) << BIT_SHIFT_DARF_RC5_V2_8197F) +#define BITS_DARF_RC5_V2_8197F \ + (BIT_MASK_DARF_RC5_V2_8197F << BIT_SHIFT_DARF_RC5_V2_8197F) +#define BIT_CLEAR_DARF_RC5_V2_8197F(x) ((x) & (~BITS_DARF_RC5_V2_8197F)) +#define BIT_GET_DARF_RC5_V2_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_V2_8197F) & BIT_MASK_DARF_RC5_V2_8197F) +#define BIT_SET_DARF_RC5_V2_8197F(x, v) \ + (BIT_CLEAR_DARF_RC5_V2_8197F(x) | BIT_DARF_RC5_V2_8197F(v)) + +#define BIT_SHIFT_DARF_RC4_V1_8197F 24 +#define BIT_MASK_DARF_RC4_V1_8197F 0x3f +#define BIT_DARF_RC4_V1_8197F(x) \ + (((x) & BIT_MASK_DARF_RC4_V1_8197F) << BIT_SHIFT_DARF_RC4_V1_8197F) +#define BITS_DARF_RC4_V1_8197F \ + (BIT_MASK_DARF_RC4_V1_8197F << BIT_SHIFT_DARF_RC4_V1_8197F) +#define BIT_CLEAR_DARF_RC4_V1_8197F(x) ((x) & (~BITS_DARF_RC4_V1_8197F)) +#define BIT_GET_DARF_RC4_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_V1_8197F) & BIT_MASK_DARF_RC4_V1_8197F) +#define BIT_SET_DARF_RC4_V1_8197F(x, v) \ + (BIT_CLEAR_DARF_RC4_V1_8197F(x) | BIT_DARF_RC4_V1_8197F(v)) + +#define BIT_SHIFT_DARF_RC3_V1_8197F 16 +#define BIT_MASK_DARF_RC3_V1_8197F 0x3f +#define BIT_DARF_RC3_V1_8197F(x) \ + (((x) & BIT_MASK_DARF_RC3_V1_8197F) << BIT_SHIFT_DARF_RC3_V1_8197F) +#define BITS_DARF_RC3_V1_8197F \ + (BIT_MASK_DARF_RC3_V1_8197F << BIT_SHIFT_DARF_RC3_V1_8197F) +#define BIT_CLEAR_DARF_RC3_V1_8197F(x) ((x) & (~BITS_DARF_RC3_V1_8197F)) +#define BIT_GET_DARF_RC3_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_V1_8197F) & BIT_MASK_DARF_RC3_V1_8197F) +#define BIT_SET_DARF_RC3_V1_8197F(x, v) \ + (BIT_CLEAR_DARF_RC3_V1_8197F(x) | BIT_DARF_RC3_V1_8197F(v)) + +#define BIT_SHIFT_DARF_RC2_V1_8197F 8 +#define BIT_MASK_DARF_RC2_V1_8197F 0x3f +#define BIT_DARF_RC2_V1_8197F(x) \ + (((x) & BIT_MASK_DARF_RC2_V1_8197F) << BIT_SHIFT_DARF_RC2_V1_8197F) +#define BITS_DARF_RC2_V1_8197F \ + (BIT_MASK_DARF_RC2_V1_8197F << BIT_SHIFT_DARF_RC2_V1_8197F) +#define BIT_CLEAR_DARF_RC2_V1_8197F(x) ((x) & (~BITS_DARF_RC2_V1_8197F)) +#define BIT_GET_DARF_RC2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_V1_8197F) & BIT_MASK_DARF_RC2_V1_8197F) +#define BIT_SET_DARF_RC2_V1_8197F(x, v) \ + (BIT_CLEAR_DARF_RC2_V1_8197F(x) | BIT_DARF_RC2_V1_8197F(v)) + +#define BIT_SHIFT_DARF_RC1_V1_8197F 0 +#define BIT_MASK_DARF_RC1_V1_8197F 0x3f +#define BIT_DARF_RC1_V1_8197F(x) \ + (((x) & BIT_MASK_DARF_RC1_V1_8197F) << BIT_SHIFT_DARF_RC1_V1_8197F) +#define BITS_DARF_RC1_V1_8197F \ + (BIT_MASK_DARF_RC1_V1_8197F << BIT_SHIFT_DARF_RC1_V1_8197F) +#define BIT_CLEAR_DARF_RC1_V1_8197F(x) ((x) & (~BITS_DARF_RC1_V1_8197F)) +#define BIT_GET_DARF_RC1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_V1_8197F) & BIT_MASK_DARF_RC1_V1_8197F) +#define BIT_SET_DARF_RC1_V1_8197F(x, v) \ + (BIT_CLEAR_DARF_RC1_V1_8197F(x) | BIT_DARF_RC1_V1_8197F(v)) /* 2 REG_RARFRC_8197F */ #define BIT_SHIFT_RARF_RC8_8197F (56 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC8_8197F 0x1f -#define BIT_RARF_RC8_8197F(x) (((x) & BIT_MASK_RARF_RC8_8197F) << BIT_SHIFT_RARF_RC8_8197F) -#define BITS_RARF_RC8_8197F (BIT_MASK_RARF_RC8_8197F << BIT_SHIFT_RARF_RC8_8197F) +#define BIT_RARF_RC8_8197F(x) \ + (((x) & BIT_MASK_RARF_RC8_8197F) << BIT_SHIFT_RARF_RC8_8197F) +#define BITS_RARF_RC8_8197F \ + (BIT_MASK_RARF_RC8_8197F << BIT_SHIFT_RARF_RC8_8197F) #define BIT_CLEAR_RARF_RC8_8197F(x) ((x) & (~BITS_RARF_RC8_8197F)) -#define BIT_GET_RARF_RC8_8197F(x) (((x) >> BIT_SHIFT_RARF_RC8_8197F) & BIT_MASK_RARF_RC8_8197F) -#define BIT_SET_RARF_RC8_8197F(x, v) (BIT_CLEAR_RARF_RC8_8197F(x) | BIT_RARF_RC8_8197F(v)) - +#define BIT_GET_RARF_RC8_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_8197F) & BIT_MASK_RARF_RC8_8197F) +#define BIT_SET_RARF_RC8_8197F(x, v) \ + (BIT_CLEAR_RARF_RC8_8197F(x) | BIT_RARF_RC8_8197F(v)) #define BIT_SHIFT_RARF_RC7_8197F (48 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC7_8197F 0x1f -#define BIT_RARF_RC7_8197F(x) (((x) & BIT_MASK_RARF_RC7_8197F) << BIT_SHIFT_RARF_RC7_8197F) -#define BITS_RARF_RC7_8197F (BIT_MASK_RARF_RC7_8197F << BIT_SHIFT_RARF_RC7_8197F) +#define BIT_RARF_RC7_8197F(x) \ + (((x) & BIT_MASK_RARF_RC7_8197F) << BIT_SHIFT_RARF_RC7_8197F) +#define BITS_RARF_RC7_8197F \ + (BIT_MASK_RARF_RC7_8197F << BIT_SHIFT_RARF_RC7_8197F) #define BIT_CLEAR_RARF_RC7_8197F(x) ((x) & (~BITS_RARF_RC7_8197F)) -#define BIT_GET_RARF_RC7_8197F(x) (((x) >> BIT_SHIFT_RARF_RC7_8197F) & BIT_MASK_RARF_RC7_8197F) -#define BIT_SET_RARF_RC7_8197F(x, v) (BIT_CLEAR_RARF_RC7_8197F(x) | BIT_RARF_RC7_8197F(v)) - +#define BIT_GET_RARF_RC7_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_8197F) & BIT_MASK_RARF_RC7_8197F) +#define BIT_SET_RARF_RC7_8197F(x, v) \ + (BIT_CLEAR_RARF_RC7_8197F(x) | BIT_RARF_RC7_8197F(v)) #define BIT_SHIFT_RARF_RC6_8197F (40 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC6_8197F 0x1f -#define BIT_RARF_RC6_8197F(x) (((x) & BIT_MASK_RARF_RC6_8197F) << BIT_SHIFT_RARF_RC6_8197F) -#define BITS_RARF_RC6_8197F (BIT_MASK_RARF_RC6_8197F << BIT_SHIFT_RARF_RC6_8197F) +#define BIT_RARF_RC6_8197F(x) \ + (((x) & BIT_MASK_RARF_RC6_8197F) << BIT_SHIFT_RARF_RC6_8197F) +#define BITS_RARF_RC6_8197F \ + (BIT_MASK_RARF_RC6_8197F << BIT_SHIFT_RARF_RC6_8197F) #define BIT_CLEAR_RARF_RC6_8197F(x) ((x) & (~BITS_RARF_RC6_8197F)) -#define BIT_GET_RARF_RC6_8197F(x) (((x) >> BIT_SHIFT_RARF_RC6_8197F) & BIT_MASK_RARF_RC6_8197F) -#define BIT_SET_RARF_RC6_8197F(x, v) (BIT_CLEAR_RARF_RC6_8197F(x) | BIT_RARF_RC6_8197F(v)) - +#define BIT_GET_RARF_RC6_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_8197F) & BIT_MASK_RARF_RC6_8197F) +#define BIT_SET_RARF_RC6_8197F(x, v) \ + (BIT_CLEAR_RARF_RC6_8197F(x) | BIT_RARF_RC6_8197F(v)) #define BIT_SHIFT_RARF_RC5_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC5_8197F 0x1f -#define BIT_RARF_RC5_8197F(x) (((x) & BIT_MASK_RARF_RC5_8197F) << BIT_SHIFT_RARF_RC5_8197F) -#define BITS_RARF_RC5_8197F (BIT_MASK_RARF_RC5_8197F << BIT_SHIFT_RARF_RC5_8197F) +#define BIT_RARF_RC5_8197F(x) \ + (((x) & BIT_MASK_RARF_RC5_8197F) << BIT_SHIFT_RARF_RC5_8197F) +#define BITS_RARF_RC5_8197F \ + (BIT_MASK_RARF_RC5_8197F << BIT_SHIFT_RARF_RC5_8197F) #define BIT_CLEAR_RARF_RC5_8197F(x) ((x) & (~BITS_RARF_RC5_8197F)) -#define BIT_GET_RARF_RC5_8197F(x) (((x) >> BIT_SHIFT_RARF_RC5_8197F) & BIT_MASK_RARF_RC5_8197F) -#define BIT_SET_RARF_RC5_8197F(x, v) (BIT_CLEAR_RARF_RC5_8197F(x) | BIT_RARF_RC5_8197F(v)) - +#define BIT_GET_RARF_RC5_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_8197F) & BIT_MASK_RARF_RC5_8197F) +#define BIT_SET_RARF_RC5_8197F(x, v) \ + (BIT_CLEAR_RARF_RC5_8197F(x) | BIT_RARF_RC5_8197F(v)) #define BIT_SHIFT_RARF_RC4_8197F 24 #define BIT_MASK_RARF_RC4_8197F 0x1f -#define BIT_RARF_RC4_8197F(x) (((x) & BIT_MASK_RARF_RC4_8197F) << BIT_SHIFT_RARF_RC4_8197F) -#define BITS_RARF_RC4_8197F (BIT_MASK_RARF_RC4_8197F << BIT_SHIFT_RARF_RC4_8197F) +#define BIT_RARF_RC4_8197F(x) \ + (((x) & BIT_MASK_RARF_RC4_8197F) << BIT_SHIFT_RARF_RC4_8197F) +#define BITS_RARF_RC4_8197F \ + (BIT_MASK_RARF_RC4_8197F << BIT_SHIFT_RARF_RC4_8197F) #define BIT_CLEAR_RARF_RC4_8197F(x) ((x) & (~BITS_RARF_RC4_8197F)) -#define BIT_GET_RARF_RC4_8197F(x) (((x) >> BIT_SHIFT_RARF_RC4_8197F) & BIT_MASK_RARF_RC4_8197F) -#define BIT_SET_RARF_RC4_8197F(x, v) (BIT_CLEAR_RARF_RC4_8197F(x) | BIT_RARF_RC4_8197F(v)) - +#define BIT_GET_RARF_RC4_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC4_8197F) & BIT_MASK_RARF_RC4_8197F) +#define BIT_SET_RARF_RC4_8197F(x, v) \ + (BIT_CLEAR_RARF_RC4_8197F(x) | BIT_RARF_RC4_8197F(v)) #define BIT_SHIFT_RARF_RC3_8197F 16 #define BIT_MASK_RARF_RC3_8197F 0x1f -#define BIT_RARF_RC3_8197F(x) (((x) & BIT_MASK_RARF_RC3_8197F) << BIT_SHIFT_RARF_RC3_8197F) -#define BITS_RARF_RC3_8197F (BIT_MASK_RARF_RC3_8197F << BIT_SHIFT_RARF_RC3_8197F) +#define BIT_RARF_RC3_8197F(x) \ + (((x) & BIT_MASK_RARF_RC3_8197F) << BIT_SHIFT_RARF_RC3_8197F) +#define BITS_RARF_RC3_8197F \ + (BIT_MASK_RARF_RC3_8197F << BIT_SHIFT_RARF_RC3_8197F) #define BIT_CLEAR_RARF_RC3_8197F(x) ((x) & (~BITS_RARF_RC3_8197F)) -#define BIT_GET_RARF_RC3_8197F(x) (((x) >> BIT_SHIFT_RARF_RC3_8197F) & BIT_MASK_RARF_RC3_8197F) -#define BIT_SET_RARF_RC3_8197F(x, v) (BIT_CLEAR_RARF_RC3_8197F(x) | BIT_RARF_RC3_8197F(v)) - +#define BIT_GET_RARF_RC3_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC3_8197F) & BIT_MASK_RARF_RC3_8197F) +#define BIT_SET_RARF_RC3_8197F(x, v) \ + (BIT_CLEAR_RARF_RC3_8197F(x) | BIT_RARF_RC3_8197F(v)) #define BIT_SHIFT_RARF_RC2_8197F 8 #define BIT_MASK_RARF_RC2_8197F 0x1f -#define BIT_RARF_RC2_8197F(x) (((x) & BIT_MASK_RARF_RC2_8197F) << BIT_SHIFT_RARF_RC2_8197F) -#define BITS_RARF_RC2_8197F (BIT_MASK_RARF_RC2_8197F << BIT_SHIFT_RARF_RC2_8197F) +#define BIT_RARF_RC2_8197F(x) \ + (((x) & BIT_MASK_RARF_RC2_8197F) << BIT_SHIFT_RARF_RC2_8197F) +#define BITS_RARF_RC2_8197F \ + (BIT_MASK_RARF_RC2_8197F << BIT_SHIFT_RARF_RC2_8197F) #define BIT_CLEAR_RARF_RC2_8197F(x) ((x) & (~BITS_RARF_RC2_8197F)) -#define BIT_GET_RARF_RC2_8197F(x) (((x) >> BIT_SHIFT_RARF_RC2_8197F) & BIT_MASK_RARF_RC2_8197F) -#define BIT_SET_RARF_RC2_8197F(x, v) (BIT_CLEAR_RARF_RC2_8197F(x) | BIT_RARF_RC2_8197F(v)) - +#define BIT_GET_RARF_RC2_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC2_8197F) & BIT_MASK_RARF_RC2_8197F) +#define BIT_SET_RARF_RC2_8197F(x, v) \ + (BIT_CLEAR_RARF_RC2_8197F(x) | BIT_RARF_RC2_8197F(v)) #define BIT_SHIFT_RARF_RC1_8197F 0 #define BIT_MASK_RARF_RC1_8197F 0x1f -#define BIT_RARF_RC1_8197F(x) (((x) & BIT_MASK_RARF_RC1_8197F) << BIT_SHIFT_RARF_RC1_8197F) -#define BITS_RARF_RC1_8197F (BIT_MASK_RARF_RC1_8197F << BIT_SHIFT_RARF_RC1_8197F) +#define BIT_RARF_RC1_8197F(x) \ + (((x) & BIT_MASK_RARF_RC1_8197F) << BIT_SHIFT_RARF_RC1_8197F) +#define BITS_RARF_RC1_8197F \ + (BIT_MASK_RARF_RC1_8197F << BIT_SHIFT_RARF_RC1_8197F) #define BIT_CLEAR_RARF_RC1_8197F(x) ((x) & (~BITS_RARF_RC1_8197F)) -#define BIT_GET_RARF_RC1_8197F(x) (((x) >> BIT_SHIFT_RARF_RC1_8197F) & BIT_MASK_RARF_RC1_8197F) -#define BIT_SET_RARF_RC1_8197F(x, v) (BIT_CLEAR_RARF_RC1_8197F(x) | BIT_RARF_RC1_8197F(v)) - +#define BIT_GET_RARF_RC1_8197F(x) \ + (((x) >> BIT_SHIFT_RARF_RC1_8197F) & BIT_MASK_RARF_RC1_8197F) +#define BIT_SET_RARF_RC1_8197F(x, v) \ + (BIT_CLEAR_RARF_RC1_8197F(x) | BIT_RARF_RC1_8197F(v)) /* 2 REG_RRSR_8197F */ #define BIT_EN_VHTBW_FALL_8197F BIT(31) @@ -6711,44 +8610,57 @@ #define BIT_SHIFT_RRSR_RSC_8197F 21 #define BIT_MASK_RRSR_RSC_8197F 0x3 -#define BIT_RRSR_RSC_8197F(x) (((x) & BIT_MASK_RRSR_RSC_8197F) << BIT_SHIFT_RRSR_RSC_8197F) -#define BITS_RRSR_RSC_8197F (BIT_MASK_RRSR_RSC_8197F << BIT_SHIFT_RRSR_RSC_8197F) +#define BIT_RRSR_RSC_8197F(x) \ + (((x) & BIT_MASK_RRSR_RSC_8197F) << BIT_SHIFT_RRSR_RSC_8197F) +#define BITS_RRSR_RSC_8197F \ + (BIT_MASK_RRSR_RSC_8197F << BIT_SHIFT_RRSR_RSC_8197F) #define BIT_CLEAR_RRSR_RSC_8197F(x) ((x) & (~BITS_RRSR_RSC_8197F)) -#define BIT_GET_RRSR_RSC_8197F(x) (((x) >> BIT_SHIFT_RRSR_RSC_8197F) & BIT_MASK_RRSR_RSC_8197F) -#define BIT_SET_RRSR_RSC_8197F(x, v) (BIT_CLEAR_RRSR_RSC_8197F(x) | BIT_RRSR_RSC_8197F(v)) +#define BIT_GET_RRSR_RSC_8197F(x) \ + (((x) >> BIT_SHIFT_RRSR_RSC_8197F) & BIT_MASK_RRSR_RSC_8197F) +#define BIT_SET_RRSR_RSC_8197F(x, v) \ + (BIT_CLEAR_RRSR_RSC_8197F(x) | BIT_RRSR_RSC_8197F(v)) #define BIT_RRSR_BW_8197F BIT(20) #define BIT_SHIFT_RRSC_BITMAP_8197F 0 #define BIT_MASK_RRSC_BITMAP_8197F 0xfffff -#define BIT_RRSC_BITMAP_8197F(x) (((x) & BIT_MASK_RRSC_BITMAP_8197F) << BIT_SHIFT_RRSC_BITMAP_8197F) -#define BITS_RRSC_BITMAP_8197F (BIT_MASK_RRSC_BITMAP_8197F << BIT_SHIFT_RRSC_BITMAP_8197F) +#define BIT_RRSC_BITMAP_8197F(x) \ + (((x) & BIT_MASK_RRSC_BITMAP_8197F) << BIT_SHIFT_RRSC_BITMAP_8197F) +#define BITS_RRSC_BITMAP_8197F \ + (BIT_MASK_RRSC_BITMAP_8197F << BIT_SHIFT_RRSC_BITMAP_8197F) #define BIT_CLEAR_RRSC_BITMAP_8197F(x) ((x) & (~BITS_RRSC_BITMAP_8197F)) -#define BIT_GET_RRSC_BITMAP_8197F(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8197F) & BIT_MASK_RRSC_BITMAP_8197F) -#define BIT_SET_RRSC_BITMAP_8197F(x, v) (BIT_CLEAR_RRSC_BITMAP_8197F(x) | BIT_RRSC_BITMAP_8197F(v)) - +#define BIT_GET_RRSC_BITMAP_8197F(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP_8197F) & BIT_MASK_RRSC_BITMAP_8197F) +#define BIT_SET_RRSC_BITMAP_8197F(x, v) \ + (BIT_CLEAR_RRSC_BITMAP_8197F(x) | BIT_RRSC_BITMAP_8197F(v)) /* 2 REG_ARFR0_8197F */ #define BIT_SHIFT_ARFR0_V1_8197F 0 #define BIT_MASK_ARFR0_V1_8197F 0xffffffffffffffffL -#define BIT_ARFR0_V1_8197F(x) (((x) & BIT_MASK_ARFR0_V1_8197F) << BIT_SHIFT_ARFR0_V1_8197F) -#define BITS_ARFR0_V1_8197F (BIT_MASK_ARFR0_V1_8197F << BIT_SHIFT_ARFR0_V1_8197F) +#define BIT_ARFR0_V1_8197F(x) \ + (((x) & BIT_MASK_ARFR0_V1_8197F) << BIT_SHIFT_ARFR0_V1_8197F) +#define BITS_ARFR0_V1_8197F \ + (BIT_MASK_ARFR0_V1_8197F << BIT_SHIFT_ARFR0_V1_8197F) #define BIT_CLEAR_ARFR0_V1_8197F(x) ((x) & (~BITS_ARFR0_V1_8197F)) -#define BIT_GET_ARFR0_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR0_V1_8197F) & BIT_MASK_ARFR0_V1_8197F) -#define BIT_SET_ARFR0_V1_8197F(x, v) (BIT_CLEAR_ARFR0_V1_8197F(x) | BIT_ARFR0_V1_8197F(v)) - +#define BIT_GET_ARFR0_V1_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR0_V1_8197F) & BIT_MASK_ARFR0_V1_8197F) +#define BIT_SET_ARFR0_V1_8197F(x, v) \ + (BIT_CLEAR_ARFR0_V1_8197F(x) | BIT_ARFR0_V1_8197F(v)) /* 2 REG_ARFR1_V1_8197F */ #define BIT_SHIFT_ARFR1_V1_8197F 0 #define BIT_MASK_ARFR1_V1_8197F 0xffffffffffffffffL -#define BIT_ARFR1_V1_8197F(x) (((x) & BIT_MASK_ARFR1_V1_8197F) << BIT_SHIFT_ARFR1_V1_8197F) -#define BITS_ARFR1_V1_8197F (BIT_MASK_ARFR1_V1_8197F << BIT_SHIFT_ARFR1_V1_8197F) +#define BIT_ARFR1_V1_8197F(x) \ + (((x) & BIT_MASK_ARFR1_V1_8197F) << BIT_SHIFT_ARFR1_V1_8197F) +#define BITS_ARFR1_V1_8197F \ + (BIT_MASK_ARFR1_V1_8197F << BIT_SHIFT_ARFR1_V1_8197F) #define BIT_CLEAR_ARFR1_V1_8197F(x) ((x) & (~BITS_ARFR1_V1_8197F)) -#define BIT_GET_ARFR1_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR1_V1_8197F) & BIT_MASK_ARFR1_V1_8197F) -#define BIT_SET_ARFR1_V1_8197F(x, v) (BIT_CLEAR_ARFR1_V1_8197F(x) | BIT_ARFR1_V1_8197F(v)) - +#define BIT_GET_ARFR1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR1_V1_8197F) & BIT_MASK_ARFR1_V1_8197F) +#define BIT_SET_ARFR1_V1_8197F(x, v) \ + (BIT_CLEAR_ARFR1_V1_8197F(x) | BIT_ARFR1_V1_8197F(v)) /* 2 REG_CCK_CHECK_8197F */ #define BIT_CHECK_CCK_EN_8197F BIT(7) @@ -6764,34 +8676,50 @@ #define BIT_SHIFT_AMPDU_MAX_TIME_8197F 0 #define BIT_MASK_AMPDU_MAX_TIME_8197F 0xff -#define BIT_AMPDU_MAX_TIME_8197F(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8197F) << BIT_SHIFT_AMPDU_MAX_TIME_8197F) -#define BITS_AMPDU_MAX_TIME_8197F (BIT_MASK_AMPDU_MAX_TIME_8197F << BIT_SHIFT_AMPDU_MAX_TIME_8197F) +#define BIT_AMPDU_MAX_TIME_8197F(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME_8197F) \ + << BIT_SHIFT_AMPDU_MAX_TIME_8197F) +#define BITS_AMPDU_MAX_TIME_8197F \ + (BIT_MASK_AMPDU_MAX_TIME_8197F << BIT_SHIFT_AMPDU_MAX_TIME_8197F) #define BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) ((x) & (~BITS_AMPDU_MAX_TIME_8197F)) -#define BIT_GET_AMPDU_MAX_TIME_8197F(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8197F) & BIT_MASK_AMPDU_MAX_TIME_8197F) -#define BIT_SET_AMPDU_MAX_TIME_8197F(x, v) (BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) | BIT_AMPDU_MAX_TIME_8197F(v)) - +#define BIT_GET_AMPDU_MAX_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8197F) & \ + BIT_MASK_AMPDU_MAX_TIME_8197F) +#define BIT_SET_AMPDU_MAX_TIME_8197F(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) | BIT_AMPDU_MAX_TIME_8197F(v)) /* 2 REG_BCNQ1_BDNY_V1_8197F */ #define BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F 0 #define BIT_MASK_BCNQ1_PGBNDY_V1_8197F 0xfff -#define BIT_BCNQ1_PGBNDY_V1_8197F(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8197F) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) -#define BITS_BCNQ1_PGBNDY_V1_8197F (BIT_MASK_BCNQ1_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) +#define BIT_BCNQ1_PGBNDY_V1_8197F(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8197F) \ + << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) +#define BITS_BCNQ1_PGBNDY_V1_8197F \ + (BIT_MASK_BCNQ1_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) #define BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8197F)) -#define BIT_GET_BCNQ1_PGBNDY_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) & BIT_MASK_BCNQ1_PGBNDY_V1_8197F) -#define BIT_SET_BCNQ1_PGBNDY_V1_8197F(x, v) (BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) | BIT_BCNQ1_PGBNDY_V1_8197F(v)) - +#define BIT_GET_BCNQ1_PGBNDY_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) & \ + BIT_MASK_BCNQ1_PGBNDY_V1_8197F) +#define BIT_SET_BCNQ1_PGBNDY_V1_8197F(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) | BIT_BCNQ1_PGBNDY_V1_8197F(v)) /* 2 REG_AMPDU_MAX_LENGTH_8197F */ #define BIT_SHIFT_AMPDU_MAX_LENGTH_8197F 0 #define BIT_MASK_AMPDU_MAX_LENGTH_8197F 0xffffffffL -#define BIT_AMPDU_MAX_LENGTH_8197F(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8197F) << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) -#define BITS_AMPDU_MAX_LENGTH_8197F (BIT_MASK_AMPDU_MAX_LENGTH_8197F << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) -#define BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_8197F)) -#define BIT_GET_AMPDU_MAX_LENGTH_8197F(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) & BIT_MASK_AMPDU_MAX_LENGTH_8197F) -#define BIT_SET_AMPDU_MAX_LENGTH_8197F(x, v) (BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) | BIT_AMPDU_MAX_LENGTH_8197F(v)) - +#define BIT_AMPDU_MAX_LENGTH_8197F(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8197F) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) +#define BITS_AMPDU_MAX_LENGTH_8197F \ + (BIT_MASK_AMPDU_MAX_LENGTH_8197F << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_8197F)) +#define BIT_GET_AMPDU_MAX_LENGTH_8197F(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) & \ + BIT_MASK_AMPDU_MAX_LENGTH_8197F) +#define BIT_SET_AMPDU_MAX_LENGTH_8197F(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) | BIT_AMPDU_MAX_LENGTH_8197F(v)) /* 2 REG_ACQ_STOP_8197F */ #define BIT_AC7Q_STOP_8197F BIT(7) @@ -6807,12 +8735,17 @@ #define BIT_SHIFT_R_NDPA_RATE_V1_8197F 0 #define BIT_MASK_R_NDPA_RATE_V1_8197F 0xff -#define BIT_R_NDPA_RATE_V1_8197F(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8197F) << BIT_SHIFT_R_NDPA_RATE_V1_8197F) -#define BITS_R_NDPA_RATE_V1_8197F (BIT_MASK_R_NDPA_RATE_V1_8197F << BIT_SHIFT_R_NDPA_RATE_V1_8197F) +#define BIT_R_NDPA_RATE_V1_8197F(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1_8197F) \ + << BIT_SHIFT_R_NDPA_RATE_V1_8197F) +#define BITS_R_NDPA_RATE_V1_8197F \ + (BIT_MASK_R_NDPA_RATE_V1_8197F << BIT_SHIFT_R_NDPA_RATE_V1_8197F) #define BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) ((x) & (~BITS_R_NDPA_RATE_V1_8197F)) -#define BIT_GET_R_NDPA_RATE_V1_8197F(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8197F) & BIT_MASK_R_NDPA_RATE_V1_8197F) -#define BIT_SET_R_NDPA_RATE_V1_8197F(x, v) (BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) | BIT_R_NDPA_RATE_V1_8197F(v)) - +#define BIT_GET_R_NDPA_RATE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8197F) & \ + BIT_MASK_R_NDPA_RATE_V1_8197F) +#define BIT_SET_R_NDPA_RATE_V1_8197F(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) | BIT_R_NDPA_RATE_V1_8197F(v)) /* 2 REG_TX_HANG_CTRL_8197F */ #define BIT_R_EN_GNT_BT_AWAKE_8197F BIT(3) @@ -6825,22 +8758,29 @@ #define BIT_SHIFT_BW_SIGTA_8197F 3 #define BIT_MASK_BW_SIGTA_8197F 0x3 -#define BIT_BW_SIGTA_8197F(x) (((x) & BIT_MASK_BW_SIGTA_8197F) << BIT_SHIFT_BW_SIGTA_8197F) -#define BITS_BW_SIGTA_8197F (BIT_MASK_BW_SIGTA_8197F << BIT_SHIFT_BW_SIGTA_8197F) +#define BIT_BW_SIGTA_8197F(x) \ + (((x) & BIT_MASK_BW_SIGTA_8197F) << BIT_SHIFT_BW_SIGTA_8197F) +#define BITS_BW_SIGTA_8197F \ + (BIT_MASK_BW_SIGTA_8197F << BIT_SHIFT_BW_SIGTA_8197F) #define BIT_CLEAR_BW_SIGTA_8197F(x) ((x) & (~BITS_BW_SIGTA_8197F)) -#define BIT_GET_BW_SIGTA_8197F(x) (((x) >> BIT_SHIFT_BW_SIGTA_8197F) & BIT_MASK_BW_SIGTA_8197F) -#define BIT_SET_BW_SIGTA_8197F(x, v) (BIT_CLEAR_BW_SIGTA_8197F(x) | BIT_BW_SIGTA_8197F(v)) +#define BIT_GET_BW_SIGTA_8197F(x) \ + (((x) >> BIT_SHIFT_BW_SIGTA_8197F) & BIT_MASK_BW_SIGTA_8197F) +#define BIT_SET_BW_SIGTA_8197F(x, v) \ + (BIT_CLEAR_BW_SIGTA_8197F(x) | BIT_BW_SIGTA_8197F(v)) #define BIT_EN_BAR_SIGTA_8197F BIT(2) #define BIT_SHIFT_R_NDPA_BW_8197F 0 #define BIT_MASK_R_NDPA_BW_8197F 0x3 -#define BIT_R_NDPA_BW_8197F(x) (((x) & BIT_MASK_R_NDPA_BW_8197F) << BIT_SHIFT_R_NDPA_BW_8197F) -#define BITS_R_NDPA_BW_8197F (BIT_MASK_R_NDPA_BW_8197F << BIT_SHIFT_R_NDPA_BW_8197F) +#define BIT_R_NDPA_BW_8197F(x) \ + (((x) & BIT_MASK_R_NDPA_BW_8197F) << BIT_SHIFT_R_NDPA_BW_8197F) +#define BITS_R_NDPA_BW_8197F \ + (BIT_MASK_R_NDPA_BW_8197F << BIT_SHIFT_R_NDPA_BW_8197F) #define BIT_CLEAR_R_NDPA_BW_8197F(x) ((x) & (~BITS_R_NDPA_BW_8197F)) -#define BIT_GET_R_NDPA_BW_8197F(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8197F) & BIT_MASK_R_NDPA_BW_8197F) -#define BIT_SET_R_NDPA_BW_8197F(x, v) (BIT_CLEAR_R_NDPA_BW_8197F(x) | BIT_R_NDPA_BW_8197F(v)) - +#define BIT_GET_R_NDPA_BW_8197F(x) \ + (((x) >> BIT_SHIFT_R_NDPA_BW_8197F) & BIT_MASK_R_NDPA_BW_8197F) +#define BIT_SET_R_NDPA_BW_8197F(x, v) \ + (BIT_CLEAR_R_NDPA_BW_8197F(x) | BIT_R_NDPA_BW_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -6850,258 +8790,389 @@ #define BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F 0 #define BIT_MASK_RD_RESP_PKT_TH_V1_8197F 0x3f -#define BIT_RD_RESP_PKT_TH_V1_8197F(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8197F) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) -#define BITS_RD_RESP_PKT_TH_V1_8197F (BIT_MASK_RD_RESP_PKT_TH_V1_8197F << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) -#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) ((x) & (~BITS_RD_RESP_PKT_TH_V1_8197F)) -#define BIT_GET_RD_RESP_PKT_TH_V1_8197F(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) & BIT_MASK_RD_RESP_PKT_TH_V1_8197F) -#define BIT_SET_RD_RESP_PKT_TH_V1_8197F(x, v) (BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) | BIT_RD_RESP_PKT_TH_V1_8197F(v)) - +#define BIT_RD_RESP_PKT_TH_V1_8197F(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8197F) \ + << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) +#define BITS_RD_RESP_PKT_TH_V1_8197F \ + (BIT_MASK_RD_RESP_PKT_TH_V1_8197F << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) \ + ((x) & (~BITS_RD_RESP_PKT_TH_V1_8197F)) +#define BIT_GET_RD_RESP_PKT_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) & \ + BIT_MASK_RD_RESP_PKT_TH_V1_8197F) +#define BIT_SET_RD_RESP_PKT_TH_V1_8197F(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) | BIT_RD_RESP_PKT_TH_V1_8197F(v)) /* 2 REG_CMDQ_INFO_8197F */ #define BIT_SHIFT_PKT_NUM_8197F 23 #define BIT_MASK_PKT_NUM_8197F 0x1ff -#define BIT_PKT_NUM_8197F(x) (((x) & BIT_MASK_PKT_NUM_8197F) << BIT_SHIFT_PKT_NUM_8197F) +#define BIT_PKT_NUM_8197F(x) \ + (((x) & BIT_MASK_PKT_NUM_8197F) << BIT_SHIFT_PKT_NUM_8197F) #define BITS_PKT_NUM_8197F (BIT_MASK_PKT_NUM_8197F << BIT_SHIFT_PKT_NUM_8197F) #define BIT_CLEAR_PKT_NUM_8197F(x) ((x) & (~BITS_PKT_NUM_8197F)) -#define BIT_GET_PKT_NUM_8197F(x) (((x) >> BIT_SHIFT_PKT_NUM_8197F) & BIT_MASK_PKT_NUM_8197F) -#define BIT_SET_PKT_NUM_8197F(x, v) (BIT_CLEAR_PKT_NUM_8197F(x) | BIT_PKT_NUM_8197F(v)) +#define BIT_GET_PKT_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_8197F) & BIT_MASK_PKT_NUM_8197F) +#define BIT_SET_PKT_NUM_8197F(x, v) \ + (BIT_CLEAR_PKT_NUM_8197F(x) | BIT_PKT_NUM_8197F(v)) #define BIT_TIDEMPTY_CMDQ_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F 11 #define BIT_MASK_TAIL_PKT_CMDQ_V2_8197F 0x7ff -#define BIT_TAIL_PKT_CMDQ_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8197F) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) -#define BITS_TAIL_PKT_CMDQ_V2_8197F (BIT_MASK_TAIL_PKT_CMDQ_V2_8197F << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) -#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_CMDQ_V2_8197F)) -#define BIT_GET_TAIL_PKT_CMDQ_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) & BIT_MASK_TAIL_PKT_CMDQ_V2_8197F) -#define BIT_SET_TAIL_PKT_CMDQ_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) | BIT_TAIL_PKT_CMDQ_V2_8197F(v)) - +#define BIT_TAIL_PKT_CMDQ_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) +#define BITS_TAIL_PKT_CMDQ_V2_8197F \ + (BIT_MASK_TAIL_PKT_CMDQ_V2_8197F << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) +#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) \ + ((x) & (~BITS_TAIL_PKT_CMDQ_V2_8197F)) +#define BIT_GET_TAIL_PKT_CMDQ_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) & \ + BIT_MASK_TAIL_PKT_CMDQ_V2_8197F) +#define BIT_SET_TAIL_PKT_CMDQ_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) | BIT_TAIL_PKT_CMDQ_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F 0 #define BIT_MASK_HEAD_PKT_CMDQ_V1_8197F 0x7ff -#define BIT_HEAD_PKT_CMDQ_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8197F) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) -#define BITS_HEAD_PKT_CMDQ_V1_8197F (BIT_MASK_HEAD_PKT_CMDQ_V1_8197F << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) -#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8197F)) -#define BIT_GET_HEAD_PKT_CMDQ_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) & BIT_MASK_HEAD_PKT_CMDQ_V1_8197F) -#define BIT_SET_HEAD_PKT_CMDQ_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) | BIT_HEAD_PKT_CMDQ_V1_8197F(v)) - +#define BIT_HEAD_PKT_CMDQ_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) +#define BITS_HEAD_PKT_CMDQ_V1_8197F \ + (BIT_MASK_HEAD_PKT_CMDQ_V1_8197F << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) +#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) \ + ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8197F)) +#define BIT_GET_HEAD_PKT_CMDQ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) & \ + BIT_MASK_HEAD_PKT_CMDQ_V1_8197F) +#define BIT_SET_HEAD_PKT_CMDQ_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) | BIT_HEAD_PKT_CMDQ_V1_8197F(v)) /* 2 REG_Q4_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q4_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q4_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q4_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) -#define BITS_QUEUEMACID_Q4_V1_8197F (BIT_MASK_QUEUEMACID_Q4_V1_8197F << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q4_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q4_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) & BIT_MASK_QUEUEMACID_Q4_V1_8197F) -#define BIT_SET_QUEUEMACID_Q4_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) | BIT_QUEUEMACID_Q4_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q4_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) +#define BITS_QUEUEMACID_Q4_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q4_V1_8197F << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q4_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q4_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q4_V1_8197F) +#define BIT_SET_QUEUEMACID_Q4_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) | BIT_QUEUEMACID_Q4_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q4_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q4_V1_8197F 0x3 -#define BIT_QUEUEAC_Q4_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8197F) << BIT_SHIFT_QUEUEAC_Q4_V1_8197F) -#define BITS_QUEUEAC_Q4_V1_8197F (BIT_MASK_QUEUEAC_Q4_V1_8197F << BIT_SHIFT_QUEUEAC_Q4_V1_8197F) +#define BIT_QUEUEAC_Q4_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q4_V1_8197F) << BIT_SHIFT_QUEUEAC_Q4_V1_8197F) +#define BITS_QUEUEAC_Q4_V1_8197F \ + (BIT_MASK_QUEUEAC_Q4_V1_8197F << BIT_SHIFT_QUEUEAC_Q4_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8197F)) -#define BIT_GET_QUEUEAC_Q4_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8197F) & BIT_MASK_QUEUEAC_Q4_V1_8197F) -#define BIT_SET_QUEUEAC_Q4_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) | BIT_QUEUEAC_Q4_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q4_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8197F) & BIT_MASK_QUEUEAC_Q4_V1_8197F) +#define BIT_SET_QUEUEAC_Q4_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) | BIT_QUEUEAC_Q4_V1_8197F(v)) #define BIT_TIDEMPTY_Q4_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q4_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q4_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q4_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) -#define BITS_TAIL_PKT_Q4_V2_8197F (BIT_MASK_TAIL_PKT_Q4_V2_8197F << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) +#define BIT_TAIL_PKT_Q4_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) +#define BITS_TAIL_PKT_Q4_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q4_V2_8197F << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q4_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) & BIT_MASK_TAIL_PKT_Q4_V2_8197F) -#define BIT_SET_TAIL_PKT_Q4_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) | BIT_TAIL_PKT_Q4_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q4_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8197F) +#define BIT_SET_TAIL_PKT_Q4_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) | BIT_TAIL_PKT_Q4_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q4_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q4_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q4_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) -#define BITS_HEAD_PKT_Q4_V1_8197F (BIT_MASK_HEAD_PKT_Q4_V1_8197F << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) +#define BIT_HEAD_PKT_Q4_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) +#define BITS_HEAD_PKT_Q4_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q4_V1_8197F << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q4_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) & BIT_MASK_HEAD_PKT_Q4_V1_8197F) -#define BIT_SET_HEAD_PKT_Q4_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) | BIT_HEAD_PKT_Q4_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q4_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q4_V1_8197F) +#define BIT_SET_HEAD_PKT_Q4_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) | BIT_HEAD_PKT_Q4_V1_8197F(v)) /* 2 REG_Q5_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q5_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q5_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q5_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) -#define BITS_QUEUEMACID_Q5_V1_8197F (BIT_MASK_QUEUEMACID_Q5_V1_8197F << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q5_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q5_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) & BIT_MASK_QUEUEMACID_Q5_V1_8197F) -#define BIT_SET_QUEUEMACID_Q5_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) | BIT_QUEUEMACID_Q5_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q5_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) +#define BITS_QUEUEMACID_Q5_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q5_V1_8197F << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q5_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q5_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q5_V1_8197F) +#define BIT_SET_QUEUEMACID_Q5_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) | BIT_QUEUEMACID_Q5_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q5_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q5_V1_8197F 0x3 -#define BIT_QUEUEAC_Q5_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8197F) << BIT_SHIFT_QUEUEAC_Q5_V1_8197F) -#define BITS_QUEUEAC_Q5_V1_8197F (BIT_MASK_QUEUEAC_Q5_V1_8197F << BIT_SHIFT_QUEUEAC_Q5_V1_8197F) +#define BIT_QUEUEAC_Q5_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q5_V1_8197F) << BIT_SHIFT_QUEUEAC_Q5_V1_8197F) +#define BITS_QUEUEAC_Q5_V1_8197F \ + (BIT_MASK_QUEUEAC_Q5_V1_8197F << BIT_SHIFT_QUEUEAC_Q5_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8197F)) -#define BIT_GET_QUEUEAC_Q5_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8197F) & BIT_MASK_QUEUEAC_Q5_V1_8197F) -#define BIT_SET_QUEUEAC_Q5_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) | BIT_QUEUEAC_Q5_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q5_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8197F) & BIT_MASK_QUEUEAC_Q5_V1_8197F) +#define BIT_SET_QUEUEAC_Q5_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) | BIT_QUEUEAC_Q5_V1_8197F(v)) #define BIT_TIDEMPTY_Q5_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q5_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q5_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q5_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) -#define BITS_TAIL_PKT_Q5_V2_8197F (BIT_MASK_TAIL_PKT_Q5_V2_8197F << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) +#define BIT_TAIL_PKT_Q5_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) +#define BITS_TAIL_PKT_Q5_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q5_V2_8197F << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q5_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) & BIT_MASK_TAIL_PKT_Q5_V2_8197F) -#define BIT_SET_TAIL_PKT_Q5_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) | BIT_TAIL_PKT_Q5_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q5_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q5_V2_8197F) +#define BIT_SET_TAIL_PKT_Q5_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) | BIT_TAIL_PKT_Q5_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q5_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q5_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q5_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) -#define BITS_HEAD_PKT_Q5_V1_8197F (BIT_MASK_HEAD_PKT_Q5_V1_8197F << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) +#define BIT_HEAD_PKT_Q5_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) +#define BITS_HEAD_PKT_Q5_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q5_V1_8197F << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q5_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) & BIT_MASK_HEAD_PKT_Q5_V1_8197F) -#define BIT_SET_HEAD_PKT_Q5_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) | BIT_HEAD_PKT_Q5_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q5_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q5_V1_8197F) +#define BIT_SET_HEAD_PKT_Q5_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) | BIT_HEAD_PKT_Q5_V1_8197F(v)) /* 2 REG_Q6_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q6_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q6_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q6_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) -#define BITS_QUEUEMACID_Q6_V1_8197F (BIT_MASK_QUEUEMACID_Q6_V1_8197F << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q6_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q6_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) & BIT_MASK_QUEUEMACID_Q6_V1_8197F) -#define BIT_SET_QUEUEMACID_Q6_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) | BIT_QUEUEMACID_Q6_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q6_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) +#define BITS_QUEUEMACID_Q6_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q6_V1_8197F << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q6_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q6_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q6_V1_8197F) +#define BIT_SET_QUEUEMACID_Q6_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) | BIT_QUEUEMACID_Q6_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q6_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q6_V1_8197F 0x3 -#define BIT_QUEUEAC_Q6_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8197F) << BIT_SHIFT_QUEUEAC_Q6_V1_8197F) -#define BITS_QUEUEAC_Q6_V1_8197F (BIT_MASK_QUEUEAC_Q6_V1_8197F << BIT_SHIFT_QUEUEAC_Q6_V1_8197F) +#define BIT_QUEUEAC_Q6_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q6_V1_8197F) << BIT_SHIFT_QUEUEAC_Q6_V1_8197F) +#define BITS_QUEUEAC_Q6_V1_8197F \ + (BIT_MASK_QUEUEAC_Q6_V1_8197F << BIT_SHIFT_QUEUEAC_Q6_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8197F)) -#define BIT_GET_QUEUEAC_Q6_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8197F) & BIT_MASK_QUEUEAC_Q6_V1_8197F) -#define BIT_SET_QUEUEAC_Q6_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) | BIT_QUEUEAC_Q6_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q6_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8197F) & BIT_MASK_QUEUEAC_Q6_V1_8197F) +#define BIT_SET_QUEUEAC_Q6_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) | BIT_QUEUEAC_Q6_V1_8197F(v)) #define BIT_TIDEMPTY_Q6_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q6_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q6_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q6_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) -#define BITS_TAIL_PKT_Q6_V2_8197F (BIT_MASK_TAIL_PKT_Q6_V2_8197F << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) +#define BIT_TAIL_PKT_Q6_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) +#define BITS_TAIL_PKT_Q6_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q6_V2_8197F << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q6_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) & BIT_MASK_TAIL_PKT_Q6_V2_8197F) -#define BIT_SET_TAIL_PKT_Q6_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) | BIT_TAIL_PKT_Q6_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q6_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q6_V2_8197F) +#define BIT_SET_TAIL_PKT_Q6_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) | BIT_TAIL_PKT_Q6_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q6_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q6_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q6_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) -#define BITS_HEAD_PKT_Q6_V1_8197F (BIT_MASK_HEAD_PKT_Q6_V1_8197F << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) +#define BIT_HEAD_PKT_Q6_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) +#define BITS_HEAD_PKT_Q6_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q6_V1_8197F << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q6_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) & BIT_MASK_HEAD_PKT_Q6_V1_8197F) -#define BIT_SET_HEAD_PKT_Q6_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) | BIT_HEAD_PKT_Q6_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q6_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q6_V1_8197F) +#define BIT_SET_HEAD_PKT_Q6_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) | BIT_HEAD_PKT_Q6_V1_8197F(v)) /* 2 REG_Q7_INFO_8197F */ #define BIT_SHIFT_QUEUEMACID_Q7_V1_8197F 25 #define BIT_MASK_QUEUEMACID_Q7_V1_8197F 0x7f -#define BIT_QUEUEMACID_Q7_V1_8197F(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8197F) << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) -#define BITS_QUEUEMACID_Q7_V1_8197F (BIT_MASK_QUEUEMACID_Q7_V1_8197F << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) -#define BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) ((x) & (~BITS_QUEUEMACID_Q7_V1_8197F)) -#define BIT_GET_QUEUEMACID_Q7_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) & BIT_MASK_QUEUEMACID_Q7_V1_8197F) -#define BIT_SET_QUEUEMACID_Q7_V1_8197F(x, v) (BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) | BIT_QUEUEMACID_Q7_V1_8197F(v)) - +#define BIT_QUEUEMACID_Q7_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8197F) \ + << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) +#define BITS_QUEUEMACID_Q7_V1_8197F \ + (BIT_MASK_QUEUEMACID_Q7_V1_8197F << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) +#define BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) \ + ((x) & (~BITS_QUEUEMACID_Q7_V1_8197F)) +#define BIT_GET_QUEUEMACID_Q7_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) & \ + BIT_MASK_QUEUEMACID_Q7_V1_8197F) +#define BIT_SET_QUEUEMACID_Q7_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) | BIT_QUEUEMACID_Q7_V1_8197F(v)) #define BIT_SHIFT_QUEUEAC_Q7_V1_8197F 23 #define BIT_MASK_QUEUEAC_Q7_V1_8197F 0x3 -#define BIT_QUEUEAC_Q7_V1_8197F(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8197F) << BIT_SHIFT_QUEUEAC_Q7_V1_8197F) -#define BITS_QUEUEAC_Q7_V1_8197F (BIT_MASK_QUEUEAC_Q7_V1_8197F << BIT_SHIFT_QUEUEAC_Q7_V1_8197F) +#define BIT_QUEUEAC_Q7_V1_8197F(x) \ + (((x) & BIT_MASK_QUEUEAC_Q7_V1_8197F) << BIT_SHIFT_QUEUEAC_Q7_V1_8197F) +#define BITS_QUEUEAC_Q7_V1_8197F \ + (BIT_MASK_QUEUEAC_Q7_V1_8197F << BIT_SHIFT_QUEUEAC_Q7_V1_8197F) #define BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8197F)) -#define BIT_GET_QUEUEAC_Q7_V1_8197F(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8197F) & BIT_MASK_QUEUEAC_Q7_V1_8197F) -#define BIT_SET_QUEUEAC_Q7_V1_8197F(x, v) (BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) | BIT_QUEUEAC_Q7_V1_8197F(v)) +#define BIT_GET_QUEUEAC_Q7_V1_8197F(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8197F) & BIT_MASK_QUEUEAC_Q7_V1_8197F) +#define BIT_SET_QUEUEAC_Q7_V1_8197F(x, v) \ + (BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) | BIT_QUEUEAC_Q7_V1_8197F(v)) #define BIT_TIDEMPTY_Q7_V1_8197F BIT(22) #define BIT_SHIFT_TAIL_PKT_Q7_V2_8197F 11 #define BIT_MASK_TAIL_PKT_Q7_V2_8197F 0x7ff -#define BIT_TAIL_PKT_Q7_V2_8197F(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8197F) << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) -#define BITS_TAIL_PKT_Q7_V2_8197F (BIT_MASK_TAIL_PKT_Q7_V2_8197F << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) +#define BIT_TAIL_PKT_Q7_V2_8197F(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8197F) \ + << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) +#define BITS_TAIL_PKT_Q7_V2_8197F \ + (BIT_MASK_TAIL_PKT_Q7_V2_8197F << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) #define BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8197F)) -#define BIT_GET_TAIL_PKT_Q7_V2_8197F(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) & BIT_MASK_TAIL_PKT_Q7_V2_8197F) -#define BIT_SET_TAIL_PKT_Q7_V2_8197F(x, v) (BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) | BIT_TAIL_PKT_Q7_V2_8197F(v)) - +#define BIT_GET_TAIL_PKT_Q7_V2_8197F(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) & \ + BIT_MASK_TAIL_PKT_Q7_V2_8197F) +#define BIT_SET_TAIL_PKT_Q7_V2_8197F(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) | BIT_TAIL_PKT_Q7_V2_8197F(v)) #define BIT_SHIFT_HEAD_PKT_Q7_V1_8197F 0 #define BIT_MASK_HEAD_PKT_Q7_V1_8197F 0x7ff -#define BIT_HEAD_PKT_Q7_V1_8197F(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8197F) << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) -#define BITS_HEAD_PKT_Q7_V1_8197F (BIT_MASK_HEAD_PKT_Q7_V1_8197F << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) +#define BIT_HEAD_PKT_Q7_V1_8197F(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8197F) \ + << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) +#define BITS_HEAD_PKT_Q7_V1_8197F \ + (BIT_MASK_HEAD_PKT_Q7_V1_8197F << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) #define BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8197F)) -#define BIT_GET_HEAD_PKT_Q7_V1_8197F(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) & BIT_MASK_HEAD_PKT_Q7_V1_8197F) -#define BIT_SET_HEAD_PKT_Q7_V1_8197F(x, v) (BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) | BIT_HEAD_PKT_Q7_V1_8197F(v)) - +#define BIT_GET_HEAD_PKT_Q7_V1_8197F(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) & \ + BIT_MASK_HEAD_PKT_Q7_V1_8197F) +#define BIT_SET_HEAD_PKT_Q7_V1_8197F(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) | BIT_HEAD_PKT_Q7_V1_8197F(v)) /* 2 REG_WMAC_LBK_BUF_HD_V1_8197F */ #define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F 0 #define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F 0xfff -#define BIT_WMAC_LBK_BUF_HEAD_V1_8197F(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) -#define BITS_WMAC_LBK_BUF_HEAD_V1_8197F (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) -#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8197F)) -#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8197F(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F) -#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8197F(x, v) (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) | BIT_WMAC_LBK_BUF_HEAD_V1_8197F(v)) - +#define BIT_WMAC_LBK_BUF_HEAD_V1_8197F(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) +#define BITS_WMAC_LBK_BUF_HEAD_V1_8197F \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) \ + ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8197F)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8197F(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) | \ + BIT_WMAC_LBK_BUF_HEAD_V1_8197F(v)) /* 2 REG_MGQ_BDNY_V1_8197F */ #define BIT_SHIFT_MGQ_PGBNDY_V1_8197F 0 #define BIT_MASK_MGQ_PGBNDY_V1_8197F 0xfff -#define BIT_MGQ_PGBNDY_V1_8197F(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8197F) << BIT_SHIFT_MGQ_PGBNDY_V1_8197F) -#define BITS_MGQ_PGBNDY_V1_8197F (BIT_MASK_MGQ_PGBNDY_V1_8197F << BIT_SHIFT_MGQ_PGBNDY_V1_8197F) +#define BIT_MGQ_PGBNDY_V1_8197F(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1_8197F) << BIT_SHIFT_MGQ_PGBNDY_V1_8197F) +#define BITS_MGQ_PGBNDY_V1_8197F \ + (BIT_MASK_MGQ_PGBNDY_V1_8197F << BIT_SHIFT_MGQ_PGBNDY_V1_8197F) #define BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8197F)) -#define BIT_GET_MGQ_PGBNDY_V1_8197F(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8197F) & BIT_MASK_MGQ_PGBNDY_V1_8197F) -#define BIT_SET_MGQ_PGBNDY_V1_8197F(x, v) (BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) | BIT_MGQ_PGBNDY_V1_8197F(v)) - +#define BIT_GET_MGQ_PGBNDY_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8197F) & BIT_MASK_MGQ_PGBNDY_V1_8197F) +#define BIT_SET_MGQ_PGBNDY_V1_8197F(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) | BIT_MGQ_PGBNDY_V1_8197F(v)) /* 2 REG_TXRPT_CTRL_8197F */ #define BIT_SHIFT_TRXRPT_TIMER_TH_8197F 24 #define BIT_MASK_TRXRPT_TIMER_TH_8197F 0xff -#define BIT_TRXRPT_TIMER_TH_8197F(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8197F) << BIT_SHIFT_TRXRPT_TIMER_TH_8197F) -#define BITS_TRXRPT_TIMER_TH_8197F (BIT_MASK_TRXRPT_TIMER_TH_8197F << BIT_SHIFT_TRXRPT_TIMER_TH_8197F) +#define BIT_TRXRPT_TIMER_TH_8197F(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH_8197F) \ + << BIT_SHIFT_TRXRPT_TIMER_TH_8197F) +#define BITS_TRXRPT_TIMER_TH_8197F \ + (BIT_MASK_TRXRPT_TIMER_TH_8197F << BIT_SHIFT_TRXRPT_TIMER_TH_8197F) #define BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8197F)) -#define BIT_GET_TRXRPT_TIMER_TH_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8197F) & BIT_MASK_TRXRPT_TIMER_TH_8197F) -#define BIT_SET_TRXRPT_TIMER_TH_8197F(x, v) (BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) | BIT_TRXRPT_TIMER_TH_8197F(v)) - +#define BIT_GET_TRXRPT_TIMER_TH_8197F(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8197F) & \ + BIT_MASK_TRXRPT_TIMER_TH_8197F) +#define BIT_SET_TRXRPT_TIMER_TH_8197F(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) | BIT_TRXRPT_TIMER_TH_8197F(v)) #define BIT_SHIFT_TRXRPT_LEN_TH_8197F 16 #define BIT_MASK_TRXRPT_LEN_TH_8197F 0xff -#define BIT_TRXRPT_LEN_TH_8197F(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8197F) << BIT_SHIFT_TRXRPT_LEN_TH_8197F) -#define BITS_TRXRPT_LEN_TH_8197F (BIT_MASK_TRXRPT_LEN_TH_8197F << BIT_SHIFT_TRXRPT_LEN_TH_8197F) +#define BIT_TRXRPT_LEN_TH_8197F(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH_8197F) << BIT_SHIFT_TRXRPT_LEN_TH_8197F) +#define BITS_TRXRPT_LEN_TH_8197F \ + (BIT_MASK_TRXRPT_LEN_TH_8197F << BIT_SHIFT_TRXRPT_LEN_TH_8197F) #define BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) ((x) & (~BITS_TRXRPT_LEN_TH_8197F)) -#define BIT_GET_TRXRPT_LEN_TH_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8197F) & BIT_MASK_TRXRPT_LEN_TH_8197F) -#define BIT_SET_TRXRPT_LEN_TH_8197F(x, v) (BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) | BIT_TRXRPT_LEN_TH_8197F(v)) - +#define BIT_GET_TRXRPT_LEN_TH_8197F(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8197F) & BIT_MASK_TRXRPT_LEN_TH_8197F) +#define BIT_SET_TRXRPT_LEN_TH_8197F(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) | BIT_TRXRPT_LEN_TH_8197F(v)) #define BIT_SHIFT_TRXRPT_READ_PTR_8197F 8 #define BIT_MASK_TRXRPT_READ_PTR_8197F 0xff -#define BIT_TRXRPT_READ_PTR_8197F(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8197F) << BIT_SHIFT_TRXRPT_READ_PTR_8197F) -#define BITS_TRXRPT_READ_PTR_8197F (BIT_MASK_TRXRPT_READ_PTR_8197F << BIT_SHIFT_TRXRPT_READ_PTR_8197F) +#define BIT_TRXRPT_READ_PTR_8197F(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR_8197F) \ + << BIT_SHIFT_TRXRPT_READ_PTR_8197F) +#define BITS_TRXRPT_READ_PTR_8197F \ + (BIT_MASK_TRXRPT_READ_PTR_8197F << BIT_SHIFT_TRXRPT_READ_PTR_8197F) #define BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) ((x) & (~BITS_TRXRPT_READ_PTR_8197F)) -#define BIT_GET_TRXRPT_READ_PTR_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8197F) & BIT_MASK_TRXRPT_READ_PTR_8197F) -#define BIT_SET_TRXRPT_READ_PTR_8197F(x, v) (BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) | BIT_TRXRPT_READ_PTR_8197F(v)) - +#define BIT_GET_TRXRPT_READ_PTR_8197F(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8197F) & \ + BIT_MASK_TRXRPT_READ_PTR_8197F) +#define BIT_SET_TRXRPT_READ_PTR_8197F(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) | BIT_TRXRPT_READ_PTR_8197F(v)) #define BIT_SHIFT_TRXRPT_WRITE_PTR_8197F 0 #define BIT_MASK_TRXRPT_WRITE_PTR_8197F 0xff -#define BIT_TRXRPT_WRITE_PTR_8197F(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8197F) << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) -#define BITS_TRXRPT_WRITE_PTR_8197F (BIT_MASK_TRXRPT_WRITE_PTR_8197F << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) -#define BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) ((x) & (~BITS_TRXRPT_WRITE_PTR_8197F)) -#define BIT_GET_TRXRPT_WRITE_PTR_8197F(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) & BIT_MASK_TRXRPT_WRITE_PTR_8197F) -#define BIT_SET_TRXRPT_WRITE_PTR_8197F(x, v) (BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) | BIT_TRXRPT_WRITE_PTR_8197F(v)) - +#define BIT_TRXRPT_WRITE_PTR_8197F(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8197F) \ + << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) +#define BITS_TRXRPT_WRITE_PTR_8197F \ + (BIT_MASK_TRXRPT_WRITE_PTR_8197F << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) +#define BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) \ + ((x) & (~BITS_TRXRPT_WRITE_PTR_8197F)) +#define BIT_GET_TRXRPT_WRITE_PTR_8197F(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) & \ + BIT_MASK_TRXRPT_WRITE_PTR_8197F) +#define BIT_SET_TRXRPT_WRITE_PTR_8197F(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) | BIT_TRXRPT_WRITE_PTR_8197F(v)) /* 2 REG_INIRTS_RATE_SEL_8197F */ #define BIT_LEAG_RTS_BW_DUP_8197F BIT(5) @@ -7110,109 +9181,152 @@ #define BIT_SHIFT_BASIC_CFEND_RATE_8197F 0 #define BIT_MASK_BASIC_CFEND_RATE_8197F 0x1f -#define BIT_BASIC_CFEND_RATE_8197F(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8197F) << BIT_SHIFT_BASIC_CFEND_RATE_8197F) -#define BITS_BASIC_CFEND_RATE_8197F (BIT_MASK_BASIC_CFEND_RATE_8197F << BIT_SHIFT_BASIC_CFEND_RATE_8197F) -#define BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) ((x) & (~BITS_BASIC_CFEND_RATE_8197F)) -#define BIT_GET_BASIC_CFEND_RATE_8197F(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8197F) & BIT_MASK_BASIC_CFEND_RATE_8197F) -#define BIT_SET_BASIC_CFEND_RATE_8197F(x, v) (BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) | BIT_BASIC_CFEND_RATE_8197F(v)) - +#define BIT_BASIC_CFEND_RATE_8197F(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE_8197F) \ + << BIT_SHIFT_BASIC_CFEND_RATE_8197F) +#define BITS_BASIC_CFEND_RATE_8197F \ + (BIT_MASK_BASIC_CFEND_RATE_8197F << BIT_SHIFT_BASIC_CFEND_RATE_8197F) +#define BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) \ + ((x) & (~BITS_BASIC_CFEND_RATE_8197F)) +#define BIT_GET_BASIC_CFEND_RATE_8197F(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8197F) & \ + BIT_MASK_BASIC_CFEND_RATE_8197F) +#define BIT_SET_BASIC_CFEND_RATE_8197F(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) | BIT_BASIC_CFEND_RATE_8197F(v)) /* 2 REG_STBC_CFEND_RATE_8197F */ #define BIT_SHIFT_STBC_CFEND_RATE_8197F 0 #define BIT_MASK_STBC_CFEND_RATE_8197F 0x1f -#define BIT_STBC_CFEND_RATE_8197F(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8197F) << BIT_SHIFT_STBC_CFEND_RATE_8197F) -#define BITS_STBC_CFEND_RATE_8197F (BIT_MASK_STBC_CFEND_RATE_8197F << BIT_SHIFT_STBC_CFEND_RATE_8197F) +#define BIT_STBC_CFEND_RATE_8197F(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE_8197F) \ + << BIT_SHIFT_STBC_CFEND_RATE_8197F) +#define BITS_STBC_CFEND_RATE_8197F \ + (BIT_MASK_STBC_CFEND_RATE_8197F << BIT_SHIFT_STBC_CFEND_RATE_8197F) #define BIT_CLEAR_STBC_CFEND_RATE_8197F(x) ((x) & (~BITS_STBC_CFEND_RATE_8197F)) -#define BIT_GET_STBC_CFEND_RATE_8197F(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8197F) & BIT_MASK_STBC_CFEND_RATE_8197F) -#define BIT_SET_STBC_CFEND_RATE_8197F(x, v) (BIT_CLEAR_STBC_CFEND_RATE_8197F(x) | BIT_STBC_CFEND_RATE_8197F(v)) - +#define BIT_GET_STBC_CFEND_RATE_8197F(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8197F) & \ + BIT_MASK_STBC_CFEND_RATE_8197F) +#define BIT_SET_STBC_CFEND_RATE_8197F(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE_8197F(x) | BIT_STBC_CFEND_RATE_8197F(v)) /* 2 REG_DATA_SC_8197F */ #define BIT_SHIFT_TXSC_40M_8197F 4 #define BIT_MASK_TXSC_40M_8197F 0xf -#define BIT_TXSC_40M_8197F(x) (((x) & BIT_MASK_TXSC_40M_8197F) << BIT_SHIFT_TXSC_40M_8197F) -#define BITS_TXSC_40M_8197F (BIT_MASK_TXSC_40M_8197F << BIT_SHIFT_TXSC_40M_8197F) +#define BIT_TXSC_40M_8197F(x) \ + (((x) & BIT_MASK_TXSC_40M_8197F) << BIT_SHIFT_TXSC_40M_8197F) +#define BITS_TXSC_40M_8197F \ + (BIT_MASK_TXSC_40M_8197F << BIT_SHIFT_TXSC_40M_8197F) #define BIT_CLEAR_TXSC_40M_8197F(x) ((x) & (~BITS_TXSC_40M_8197F)) -#define BIT_GET_TXSC_40M_8197F(x) (((x) >> BIT_SHIFT_TXSC_40M_8197F) & BIT_MASK_TXSC_40M_8197F) -#define BIT_SET_TXSC_40M_8197F(x, v) (BIT_CLEAR_TXSC_40M_8197F(x) | BIT_TXSC_40M_8197F(v)) - +#define BIT_GET_TXSC_40M_8197F(x) \ + (((x) >> BIT_SHIFT_TXSC_40M_8197F) & BIT_MASK_TXSC_40M_8197F) +#define BIT_SET_TXSC_40M_8197F(x, v) \ + (BIT_CLEAR_TXSC_40M_8197F(x) | BIT_TXSC_40M_8197F(v)) #define BIT_SHIFT_TXSC_20M_8197F 0 #define BIT_MASK_TXSC_20M_8197F 0xf -#define BIT_TXSC_20M_8197F(x) (((x) & BIT_MASK_TXSC_20M_8197F) << BIT_SHIFT_TXSC_20M_8197F) -#define BITS_TXSC_20M_8197F (BIT_MASK_TXSC_20M_8197F << BIT_SHIFT_TXSC_20M_8197F) +#define BIT_TXSC_20M_8197F(x) \ + (((x) & BIT_MASK_TXSC_20M_8197F) << BIT_SHIFT_TXSC_20M_8197F) +#define BITS_TXSC_20M_8197F \ + (BIT_MASK_TXSC_20M_8197F << BIT_SHIFT_TXSC_20M_8197F) #define BIT_CLEAR_TXSC_20M_8197F(x) ((x) & (~BITS_TXSC_20M_8197F)) -#define BIT_GET_TXSC_20M_8197F(x) (((x) >> BIT_SHIFT_TXSC_20M_8197F) & BIT_MASK_TXSC_20M_8197F) -#define BIT_SET_TXSC_20M_8197F(x, v) (BIT_CLEAR_TXSC_20M_8197F(x) | BIT_TXSC_20M_8197F(v)) - +#define BIT_GET_TXSC_20M_8197F(x) \ + (((x) >> BIT_SHIFT_TXSC_20M_8197F) & BIT_MASK_TXSC_20M_8197F) +#define BIT_SET_TXSC_20M_8197F(x, v) \ + (BIT_CLEAR_TXSC_20M_8197F(x) | BIT_TXSC_20M_8197F(v)) /* 2 REG_MACID_SLEEP3_8197F */ #define BIT_SHIFT_MACID127_96_PKTSLEEP_8197F 0 #define BIT_MASK_MACID127_96_PKTSLEEP_8197F 0xffffffffL -#define BIT_MACID127_96_PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8197F) << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) -#define BITS_MACID127_96_PKTSLEEP_8197F (BIT_MASK_MACID127_96_PKTSLEEP_8197F << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) -#define BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) ((x) & (~BITS_MACID127_96_PKTSLEEP_8197F)) -#define BIT_GET_MACID127_96_PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) & BIT_MASK_MACID127_96_PKTSLEEP_8197F) -#define BIT_SET_MACID127_96_PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) | BIT_MACID127_96_PKTSLEEP_8197F(v)) - +#define BIT_MACID127_96_PKTSLEEP_8197F(x) \ + (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8197F) \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) +#define BITS_MACID127_96_PKTSLEEP_8197F \ + (BIT_MASK_MACID127_96_PKTSLEEP_8197F \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) +#define BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) \ + ((x) & (~BITS_MACID127_96_PKTSLEEP_8197F)) +#define BIT_GET_MACID127_96_PKTSLEEP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) & \ + BIT_MASK_MACID127_96_PKTSLEEP_8197F) +#define BIT_SET_MACID127_96_PKTSLEEP_8197F(x, v) \ + (BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) | \ + BIT_MACID127_96_PKTSLEEP_8197F(v)) /* 2 REG_MACID_SLEEP1_8197F */ #define BIT_SHIFT_MACID63_32_PKTSLEEP_8197F 0 #define BIT_MASK_MACID63_32_PKTSLEEP_8197F 0xffffffffL -#define BIT_MACID63_32_PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8197F) << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) -#define BITS_MACID63_32_PKTSLEEP_8197F (BIT_MASK_MACID63_32_PKTSLEEP_8197F << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) -#define BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) ((x) & (~BITS_MACID63_32_PKTSLEEP_8197F)) -#define BIT_GET_MACID63_32_PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) & BIT_MASK_MACID63_32_PKTSLEEP_8197F) -#define BIT_SET_MACID63_32_PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) | BIT_MACID63_32_PKTSLEEP_8197F(v)) - +#define BIT_MACID63_32_PKTSLEEP_8197F(x) \ + (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8197F) \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) +#define BITS_MACID63_32_PKTSLEEP_8197F \ + (BIT_MASK_MACID63_32_PKTSLEEP_8197F \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) +#define BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) \ + ((x) & (~BITS_MACID63_32_PKTSLEEP_8197F)) +#define BIT_GET_MACID63_32_PKTSLEEP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) & \ + BIT_MASK_MACID63_32_PKTSLEEP_8197F) +#define BIT_SET_MACID63_32_PKTSLEEP_8197F(x, v) \ + (BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) | \ + BIT_MACID63_32_PKTSLEEP_8197F(v)) /* 2 REG_ARFR2_V1_8197F */ #define BIT_SHIFT_ARFR2_V1_8197F 0 #define BIT_MASK_ARFR2_V1_8197F 0xffffffffffffffffL -#define BIT_ARFR2_V1_8197F(x) (((x) & BIT_MASK_ARFR2_V1_8197F) << BIT_SHIFT_ARFR2_V1_8197F) -#define BITS_ARFR2_V1_8197F (BIT_MASK_ARFR2_V1_8197F << BIT_SHIFT_ARFR2_V1_8197F) +#define BIT_ARFR2_V1_8197F(x) \ + (((x) & BIT_MASK_ARFR2_V1_8197F) << BIT_SHIFT_ARFR2_V1_8197F) +#define BITS_ARFR2_V1_8197F \ + (BIT_MASK_ARFR2_V1_8197F << BIT_SHIFT_ARFR2_V1_8197F) #define BIT_CLEAR_ARFR2_V1_8197F(x) ((x) & (~BITS_ARFR2_V1_8197F)) -#define BIT_GET_ARFR2_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR2_V1_8197F) & BIT_MASK_ARFR2_V1_8197F) -#define BIT_SET_ARFR2_V1_8197F(x, v) (BIT_CLEAR_ARFR2_V1_8197F(x) | BIT_ARFR2_V1_8197F(v)) - +#define BIT_GET_ARFR2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR2_V1_8197F) & BIT_MASK_ARFR2_V1_8197F) +#define BIT_SET_ARFR2_V1_8197F(x, v) \ + (BIT_CLEAR_ARFR2_V1_8197F(x) | BIT_ARFR2_V1_8197F(v)) /* 2 REG_ARFR3_V1_8197F */ #define BIT_SHIFT_ARFR3_V1_8197F 0 #define BIT_MASK_ARFR3_V1_8197F 0xffffffffffffffffL -#define BIT_ARFR3_V1_8197F(x) (((x) & BIT_MASK_ARFR3_V1_8197F) << BIT_SHIFT_ARFR3_V1_8197F) -#define BITS_ARFR3_V1_8197F (BIT_MASK_ARFR3_V1_8197F << BIT_SHIFT_ARFR3_V1_8197F) +#define BIT_ARFR3_V1_8197F(x) \ + (((x) & BIT_MASK_ARFR3_V1_8197F) << BIT_SHIFT_ARFR3_V1_8197F) +#define BITS_ARFR3_V1_8197F \ + (BIT_MASK_ARFR3_V1_8197F << BIT_SHIFT_ARFR3_V1_8197F) #define BIT_CLEAR_ARFR3_V1_8197F(x) ((x) & (~BITS_ARFR3_V1_8197F)) -#define BIT_GET_ARFR3_V1_8197F(x) (((x) >> BIT_SHIFT_ARFR3_V1_8197F) & BIT_MASK_ARFR3_V1_8197F) -#define BIT_SET_ARFR3_V1_8197F(x, v) (BIT_CLEAR_ARFR3_V1_8197F(x) | BIT_ARFR3_V1_8197F(v)) - +#define BIT_GET_ARFR3_V1_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR3_V1_8197F) & BIT_MASK_ARFR3_V1_8197F) +#define BIT_SET_ARFR3_V1_8197F(x, v) \ + (BIT_CLEAR_ARFR3_V1_8197F(x) | BIT_ARFR3_V1_8197F(v)) /* 2 REG_ARFR4_8197F */ #define BIT_SHIFT_ARFR4_8197F 0 #define BIT_MASK_ARFR4_8197F 0xffffffffffffffffL -#define BIT_ARFR4_8197F(x) (((x) & BIT_MASK_ARFR4_8197F) << BIT_SHIFT_ARFR4_8197F) +#define BIT_ARFR4_8197F(x) \ + (((x) & BIT_MASK_ARFR4_8197F) << BIT_SHIFT_ARFR4_8197F) #define BITS_ARFR4_8197F (BIT_MASK_ARFR4_8197F << BIT_SHIFT_ARFR4_8197F) #define BIT_CLEAR_ARFR4_8197F(x) ((x) & (~BITS_ARFR4_8197F)) -#define BIT_GET_ARFR4_8197F(x) (((x) >> BIT_SHIFT_ARFR4_8197F) & BIT_MASK_ARFR4_8197F) -#define BIT_SET_ARFR4_8197F(x, v) (BIT_CLEAR_ARFR4_8197F(x) | BIT_ARFR4_8197F(v)) - +#define BIT_GET_ARFR4_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR4_8197F) & BIT_MASK_ARFR4_8197F) +#define BIT_SET_ARFR4_8197F(x, v) \ + (BIT_CLEAR_ARFR4_8197F(x) | BIT_ARFR4_8197F(v)) /* 2 REG_ARFR5_8197F */ #define BIT_SHIFT_ARFR5_8197F 0 #define BIT_MASK_ARFR5_8197F 0xffffffffffffffffL -#define BIT_ARFR5_8197F(x) (((x) & BIT_MASK_ARFR5_8197F) << BIT_SHIFT_ARFR5_8197F) +#define BIT_ARFR5_8197F(x) \ + (((x) & BIT_MASK_ARFR5_8197F) << BIT_SHIFT_ARFR5_8197F) #define BITS_ARFR5_8197F (BIT_MASK_ARFR5_8197F << BIT_SHIFT_ARFR5_8197F) #define BIT_CLEAR_ARFR5_8197F(x) ((x) & (~BITS_ARFR5_8197F)) -#define BIT_GET_ARFR5_8197F(x) (((x) >> BIT_SHIFT_ARFR5_8197F) & BIT_MASK_ARFR5_8197F) -#define BIT_SET_ARFR5_8197F(x, v) (BIT_CLEAR_ARFR5_8197F(x) | BIT_ARFR5_8197F(v)) - +#define BIT_GET_ARFR5_8197F(x) \ + (((x) >> BIT_SHIFT_ARFR5_8197F) & BIT_MASK_ARFR5_8197F) +#define BIT_SET_ARFR5_8197F(x, v) \ + (BIT_CLEAR_ARFR5_8197F(x) | BIT_ARFR5_8197F(v)) /* 2 REG_TXRPT_START_OFFSET_8197F */ #define BIT_SHCUT_PARSE_DASA_8197F BIT(25) @@ -7221,21 +9335,35 @@ #define BIT_SHIFT_MACID_CTRL_OFFSET_8197F 8 #define BIT_MASK_MACID_CTRL_OFFSET_8197F 0xff -#define BIT_MACID_CTRL_OFFSET_8197F(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8197F) << BIT_SHIFT_MACID_CTRL_OFFSET_8197F) -#define BITS_MACID_CTRL_OFFSET_8197F (BIT_MASK_MACID_CTRL_OFFSET_8197F << BIT_SHIFT_MACID_CTRL_OFFSET_8197F) -#define BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) ((x) & (~BITS_MACID_CTRL_OFFSET_8197F)) -#define BIT_GET_MACID_CTRL_OFFSET_8197F(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8197F) & BIT_MASK_MACID_CTRL_OFFSET_8197F) -#define BIT_SET_MACID_CTRL_OFFSET_8197F(x, v) (BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) | BIT_MACID_CTRL_OFFSET_8197F(v)) - +#define BIT_MACID_CTRL_OFFSET_8197F(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_8197F) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_8197F) +#define BITS_MACID_CTRL_OFFSET_8197F \ + (BIT_MASK_MACID_CTRL_OFFSET_8197F << BIT_SHIFT_MACID_CTRL_OFFSET_8197F) +#define BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) \ + ((x) & (~BITS_MACID_CTRL_OFFSET_8197F)) +#define BIT_GET_MACID_CTRL_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8197F) & \ + BIT_MASK_MACID_CTRL_OFFSET_8197F) +#define BIT_SET_MACID_CTRL_OFFSET_8197F(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) | BIT_MACID_CTRL_OFFSET_8197F(v)) #define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F 0 #define BIT_MASK_AMPDU_TXRPT_OFFSET_8197F 0xff -#define BIT_AMPDU_TXRPT_OFFSET_8197F(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8197F) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) -#define BITS_AMPDU_TXRPT_OFFSET_8197F (BIT_MASK_AMPDU_TXRPT_OFFSET_8197F << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) -#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8197F)) -#define BIT_GET_AMPDU_TXRPT_OFFSET_8197F(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) & BIT_MASK_AMPDU_TXRPT_OFFSET_8197F) -#define BIT_SET_AMPDU_TXRPT_OFFSET_8197F(x, v) (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) | BIT_AMPDU_TXRPT_OFFSET_8197F(v)) - +#define BIT_AMPDU_TXRPT_OFFSET_8197F(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8197F) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) +#define BITS_AMPDU_TXRPT_OFFSET_8197F \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_8197F \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) \ + ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8197F)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_8197F) +#define BIT_SET_AMPDU_TXRPT_OFFSET_8197F(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) | \ + BIT_AMPDU_TXRPT_OFFSET_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -7251,34 +9379,44 @@ #define BIT_SHIFT_POWER_STAGE1_8197F 0 #define BIT_MASK_POWER_STAGE1_8197F 0xffffff -#define BIT_POWER_STAGE1_8197F(x) (((x) & BIT_MASK_POWER_STAGE1_8197F) << BIT_SHIFT_POWER_STAGE1_8197F) -#define BITS_POWER_STAGE1_8197F (BIT_MASK_POWER_STAGE1_8197F << BIT_SHIFT_POWER_STAGE1_8197F) +#define BIT_POWER_STAGE1_8197F(x) \ + (((x) & BIT_MASK_POWER_STAGE1_8197F) << BIT_SHIFT_POWER_STAGE1_8197F) +#define BITS_POWER_STAGE1_8197F \ + (BIT_MASK_POWER_STAGE1_8197F << BIT_SHIFT_POWER_STAGE1_8197F) #define BIT_CLEAR_POWER_STAGE1_8197F(x) ((x) & (~BITS_POWER_STAGE1_8197F)) -#define BIT_GET_POWER_STAGE1_8197F(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8197F) & BIT_MASK_POWER_STAGE1_8197F) -#define BIT_SET_POWER_STAGE1_8197F(x, v) (BIT_CLEAR_POWER_STAGE1_8197F(x) | BIT_POWER_STAGE1_8197F(v)) - +#define BIT_GET_POWER_STAGE1_8197F(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1_8197F) & BIT_MASK_POWER_STAGE1_8197F) +#define BIT_SET_POWER_STAGE1_8197F(x, v) \ + (BIT_CLEAR_POWER_STAGE1_8197F(x) | BIT_POWER_STAGE1_8197F(v)) /* 2 REG_POWER_STAGE2_8197F */ #define BIT__R_CTRL_PKT_POW_ADJ_8197F BIT(24) #define BIT_SHIFT_POWER_STAGE2_8197F 0 #define BIT_MASK_POWER_STAGE2_8197F 0xffffff -#define BIT_POWER_STAGE2_8197F(x) (((x) & BIT_MASK_POWER_STAGE2_8197F) << BIT_SHIFT_POWER_STAGE2_8197F) -#define BITS_POWER_STAGE2_8197F (BIT_MASK_POWER_STAGE2_8197F << BIT_SHIFT_POWER_STAGE2_8197F) +#define BIT_POWER_STAGE2_8197F(x) \ + (((x) & BIT_MASK_POWER_STAGE2_8197F) << BIT_SHIFT_POWER_STAGE2_8197F) +#define BITS_POWER_STAGE2_8197F \ + (BIT_MASK_POWER_STAGE2_8197F << BIT_SHIFT_POWER_STAGE2_8197F) #define BIT_CLEAR_POWER_STAGE2_8197F(x) ((x) & (~BITS_POWER_STAGE2_8197F)) -#define BIT_GET_POWER_STAGE2_8197F(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8197F) & BIT_MASK_POWER_STAGE2_8197F) -#define BIT_SET_POWER_STAGE2_8197F(x, v) (BIT_CLEAR_POWER_STAGE2_8197F(x) | BIT_POWER_STAGE2_8197F(v)) - +#define BIT_GET_POWER_STAGE2_8197F(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2_8197F) & BIT_MASK_POWER_STAGE2_8197F) +#define BIT_SET_POWER_STAGE2_8197F(x, v) \ + (BIT_CLEAR_POWER_STAGE2_8197F(x) | BIT_POWER_STAGE2_8197F(v)) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8197F */ #define BIT_SHIFT_PAD_NUM_THRES_8197F 24 #define BIT_MASK_PAD_NUM_THRES_8197F 0x3f -#define BIT_PAD_NUM_THRES_8197F(x) (((x) & BIT_MASK_PAD_NUM_THRES_8197F) << BIT_SHIFT_PAD_NUM_THRES_8197F) -#define BITS_PAD_NUM_THRES_8197F (BIT_MASK_PAD_NUM_THRES_8197F << BIT_SHIFT_PAD_NUM_THRES_8197F) +#define BIT_PAD_NUM_THRES_8197F(x) \ + (((x) & BIT_MASK_PAD_NUM_THRES_8197F) << BIT_SHIFT_PAD_NUM_THRES_8197F) +#define BITS_PAD_NUM_THRES_8197F \ + (BIT_MASK_PAD_NUM_THRES_8197F << BIT_SHIFT_PAD_NUM_THRES_8197F) #define BIT_CLEAR_PAD_NUM_THRES_8197F(x) ((x) & (~BITS_PAD_NUM_THRES_8197F)) -#define BIT_GET_PAD_NUM_THRES_8197F(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8197F) & BIT_MASK_PAD_NUM_THRES_8197F) -#define BIT_SET_PAD_NUM_THRES_8197F(x, v) (BIT_CLEAR_PAD_NUM_THRES_8197F(x) | BIT_PAD_NUM_THRES_8197F(v)) +#define BIT_GET_PAD_NUM_THRES_8197F(x) \ + (((x) >> BIT_SHIFT_PAD_NUM_THRES_8197F) & BIT_MASK_PAD_NUM_THRES_8197F) +#define BIT_SET_PAD_NUM_THRES_8197F(x, v) \ + (BIT_CLEAR_PAD_NUM_THRES_8197F(x) | BIT_PAD_NUM_THRES_8197F(v)) #define BIT_R_DMA_THIS_QUEUE_BK_8197F BIT(23) #define BIT_R_DMA_THIS_QUEUE_BE_8197F BIT(22) @@ -7287,22 +9425,32 @@ #define BIT_SHIFT_R_TOTAL_LEN_TH_8197F 8 #define BIT_MASK_R_TOTAL_LEN_TH_8197F 0xfff -#define BIT_R_TOTAL_LEN_TH_8197F(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8197F) << BIT_SHIFT_R_TOTAL_LEN_TH_8197F) -#define BITS_R_TOTAL_LEN_TH_8197F (BIT_MASK_R_TOTAL_LEN_TH_8197F << BIT_SHIFT_R_TOTAL_LEN_TH_8197F) +#define BIT_R_TOTAL_LEN_TH_8197F(x) \ + (((x) & BIT_MASK_R_TOTAL_LEN_TH_8197F) \ + << BIT_SHIFT_R_TOTAL_LEN_TH_8197F) +#define BITS_R_TOTAL_LEN_TH_8197F \ + (BIT_MASK_R_TOTAL_LEN_TH_8197F << BIT_SHIFT_R_TOTAL_LEN_TH_8197F) #define BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8197F)) -#define BIT_GET_R_TOTAL_LEN_TH_8197F(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8197F) & BIT_MASK_R_TOTAL_LEN_TH_8197F) -#define BIT_SET_R_TOTAL_LEN_TH_8197F(x, v) (BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) | BIT_R_TOTAL_LEN_TH_8197F(v)) +#define BIT_GET_R_TOTAL_LEN_TH_8197F(x) \ + (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8197F) & \ + BIT_MASK_R_TOTAL_LEN_TH_8197F) +#define BIT_SET_R_TOTAL_LEN_TH_8197F(x, v) \ + (BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) | BIT_R_TOTAL_LEN_TH_8197F(v)) #define BIT_EN_NEW_EARLY_8197F BIT(7) #define BIT_PRE_TX_CMD_8197F BIT(6) #define BIT_SHIFT_NUM_SCL_EN_8197F 4 #define BIT_MASK_NUM_SCL_EN_8197F 0x3 -#define BIT_NUM_SCL_EN_8197F(x) (((x) & BIT_MASK_NUM_SCL_EN_8197F) << BIT_SHIFT_NUM_SCL_EN_8197F) -#define BITS_NUM_SCL_EN_8197F (BIT_MASK_NUM_SCL_EN_8197F << BIT_SHIFT_NUM_SCL_EN_8197F) +#define BIT_NUM_SCL_EN_8197F(x) \ + (((x) & BIT_MASK_NUM_SCL_EN_8197F) << BIT_SHIFT_NUM_SCL_EN_8197F) +#define BITS_NUM_SCL_EN_8197F \ + (BIT_MASK_NUM_SCL_EN_8197F << BIT_SHIFT_NUM_SCL_EN_8197F) #define BIT_CLEAR_NUM_SCL_EN_8197F(x) ((x) & (~BITS_NUM_SCL_EN_8197F)) -#define BIT_GET_NUM_SCL_EN_8197F(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8197F) & BIT_MASK_NUM_SCL_EN_8197F) -#define BIT_SET_NUM_SCL_EN_8197F(x, v) (BIT_CLEAR_NUM_SCL_EN_8197F(x) | BIT_NUM_SCL_EN_8197F(v)) +#define BIT_GET_NUM_SCL_EN_8197F(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN_8197F) & BIT_MASK_NUM_SCL_EN_8197F) +#define BIT_SET_NUM_SCL_EN_8197F(x, v) \ + (BIT_CLEAR_NUM_SCL_EN_8197F(x) | BIT_NUM_SCL_EN_8197F(v)) #define BIT_BK_EN_8197F BIT(3) #define BIT_BE_EN_8197F BIT(2) @@ -7313,61 +9461,86 @@ #define BIT_SHIFT_PKT_LIFTIME_BEBK_8197F 16 #define BIT_MASK_PKT_LIFTIME_BEBK_8197F 0xffff -#define BIT_PKT_LIFTIME_BEBK_8197F(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8197F) << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) -#define BITS_PKT_LIFTIME_BEBK_8197F (BIT_MASK_PKT_LIFTIME_BEBK_8197F << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) -#define BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) ((x) & (~BITS_PKT_LIFTIME_BEBK_8197F)) -#define BIT_GET_PKT_LIFTIME_BEBK_8197F(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) & BIT_MASK_PKT_LIFTIME_BEBK_8197F) -#define BIT_SET_PKT_LIFTIME_BEBK_8197F(x, v) (BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) | BIT_PKT_LIFTIME_BEBK_8197F(v)) - +#define BIT_PKT_LIFTIME_BEBK_8197F(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8197F) \ + << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) +#define BITS_PKT_LIFTIME_BEBK_8197F \ + (BIT_MASK_PKT_LIFTIME_BEBK_8197F << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) +#define BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) \ + ((x) & (~BITS_PKT_LIFTIME_BEBK_8197F)) +#define BIT_GET_PKT_LIFTIME_BEBK_8197F(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) & \ + BIT_MASK_PKT_LIFTIME_BEBK_8197F) +#define BIT_SET_PKT_LIFTIME_BEBK_8197F(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) | BIT_PKT_LIFTIME_BEBK_8197F(v)) #define BIT_SHIFT_PKT_LIFTIME_VOVI_8197F 0 #define BIT_MASK_PKT_LIFTIME_VOVI_8197F 0xffff -#define BIT_PKT_LIFTIME_VOVI_8197F(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8197F) << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) -#define BITS_PKT_LIFTIME_VOVI_8197F (BIT_MASK_PKT_LIFTIME_VOVI_8197F << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) -#define BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) ((x) & (~BITS_PKT_LIFTIME_VOVI_8197F)) -#define BIT_GET_PKT_LIFTIME_VOVI_8197F(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) & BIT_MASK_PKT_LIFTIME_VOVI_8197F) -#define BIT_SET_PKT_LIFTIME_VOVI_8197F(x, v) (BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) | BIT_PKT_LIFTIME_VOVI_8197F(v)) - +#define BIT_PKT_LIFTIME_VOVI_8197F(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8197F) \ + << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) +#define BITS_PKT_LIFTIME_VOVI_8197F \ + (BIT_MASK_PKT_LIFTIME_VOVI_8197F << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) +#define BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) \ + ((x) & (~BITS_PKT_LIFTIME_VOVI_8197F)) +#define BIT_GET_PKT_LIFTIME_VOVI_8197F(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) & \ + BIT_MASK_PKT_LIFTIME_VOVI_8197F) +#define BIT_SET_PKT_LIFTIME_VOVI_8197F(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) | BIT_PKT_LIFTIME_VOVI_8197F(v)) /* 2 REG_STBC_SETTING_8197F */ #define BIT_SHIFT_CDEND_TXTIME_L_8197F 4 #define BIT_MASK_CDEND_TXTIME_L_8197F 0xf -#define BIT_CDEND_TXTIME_L_8197F(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8197F) << BIT_SHIFT_CDEND_TXTIME_L_8197F) -#define BITS_CDEND_TXTIME_L_8197F (BIT_MASK_CDEND_TXTIME_L_8197F << BIT_SHIFT_CDEND_TXTIME_L_8197F) +#define BIT_CDEND_TXTIME_L_8197F(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L_8197F) \ + << BIT_SHIFT_CDEND_TXTIME_L_8197F) +#define BITS_CDEND_TXTIME_L_8197F \ + (BIT_MASK_CDEND_TXTIME_L_8197F << BIT_SHIFT_CDEND_TXTIME_L_8197F) #define BIT_CLEAR_CDEND_TXTIME_L_8197F(x) ((x) & (~BITS_CDEND_TXTIME_L_8197F)) -#define BIT_GET_CDEND_TXTIME_L_8197F(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8197F) & BIT_MASK_CDEND_TXTIME_L_8197F) -#define BIT_SET_CDEND_TXTIME_L_8197F(x, v) (BIT_CLEAR_CDEND_TXTIME_L_8197F(x) | BIT_CDEND_TXTIME_L_8197F(v)) - +#define BIT_GET_CDEND_TXTIME_L_8197F(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8197F) & \ + BIT_MASK_CDEND_TXTIME_L_8197F) +#define BIT_SET_CDEND_TXTIME_L_8197F(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L_8197F(x) | BIT_CDEND_TXTIME_L_8197F(v)) #define BIT_SHIFT_NESS_8197F 2 #define BIT_MASK_NESS_8197F 0x3 #define BIT_NESS_8197F(x) (((x) & BIT_MASK_NESS_8197F) << BIT_SHIFT_NESS_8197F) #define BITS_NESS_8197F (BIT_MASK_NESS_8197F << BIT_SHIFT_NESS_8197F) #define BIT_CLEAR_NESS_8197F(x) ((x) & (~BITS_NESS_8197F)) -#define BIT_GET_NESS_8197F(x) (((x) >> BIT_SHIFT_NESS_8197F) & BIT_MASK_NESS_8197F) +#define BIT_GET_NESS_8197F(x) \ + (((x) >> BIT_SHIFT_NESS_8197F) & BIT_MASK_NESS_8197F) #define BIT_SET_NESS_8197F(x, v) (BIT_CLEAR_NESS_8197F(x) | BIT_NESS_8197F(v)) - #define BIT_SHIFT_STBC_CFEND_8197F 0 #define BIT_MASK_STBC_CFEND_8197F 0x3 -#define BIT_STBC_CFEND_8197F(x) (((x) & BIT_MASK_STBC_CFEND_8197F) << BIT_SHIFT_STBC_CFEND_8197F) -#define BITS_STBC_CFEND_8197F (BIT_MASK_STBC_CFEND_8197F << BIT_SHIFT_STBC_CFEND_8197F) +#define BIT_STBC_CFEND_8197F(x) \ + (((x) & BIT_MASK_STBC_CFEND_8197F) << BIT_SHIFT_STBC_CFEND_8197F) +#define BITS_STBC_CFEND_8197F \ + (BIT_MASK_STBC_CFEND_8197F << BIT_SHIFT_STBC_CFEND_8197F) #define BIT_CLEAR_STBC_CFEND_8197F(x) ((x) & (~BITS_STBC_CFEND_8197F)) -#define BIT_GET_STBC_CFEND_8197F(x) (((x) >> BIT_SHIFT_STBC_CFEND_8197F) & BIT_MASK_STBC_CFEND_8197F) -#define BIT_SET_STBC_CFEND_8197F(x, v) (BIT_CLEAR_STBC_CFEND_8197F(x) | BIT_STBC_CFEND_8197F(v)) - +#define BIT_GET_STBC_CFEND_8197F(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_8197F) & BIT_MASK_STBC_CFEND_8197F) +#define BIT_SET_STBC_CFEND_8197F(x, v) \ + (BIT_CLEAR_STBC_CFEND_8197F(x) | BIT_STBC_CFEND_8197F(v)) /* 2 REG_STBC_SETTING2_8197F */ #define BIT_SHIFT_CDEND_TXTIME_H_8197F 0 #define BIT_MASK_CDEND_TXTIME_H_8197F 0x1f -#define BIT_CDEND_TXTIME_H_8197F(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8197F) << BIT_SHIFT_CDEND_TXTIME_H_8197F) -#define BITS_CDEND_TXTIME_H_8197F (BIT_MASK_CDEND_TXTIME_H_8197F << BIT_SHIFT_CDEND_TXTIME_H_8197F) +#define BIT_CDEND_TXTIME_H_8197F(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H_8197F) \ + << BIT_SHIFT_CDEND_TXTIME_H_8197F) +#define BITS_CDEND_TXTIME_H_8197F \ + (BIT_MASK_CDEND_TXTIME_H_8197F << BIT_SHIFT_CDEND_TXTIME_H_8197F) #define BIT_CLEAR_CDEND_TXTIME_H_8197F(x) ((x) & (~BITS_CDEND_TXTIME_H_8197F)) -#define BIT_GET_CDEND_TXTIME_H_8197F(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8197F) & BIT_MASK_CDEND_TXTIME_H_8197F) -#define BIT_SET_CDEND_TXTIME_H_8197F(x, v) (BIT_CLEAR_CDEND_TXTIME_H_8197F(x) | BIT_CDEND_TXTIME_H_8197F(v)) - +#define BIT_GET_CDEND_TXTIME_H_8197F(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8197F) & \ + BIT_MASK_CDEND_TXTIME_H_8197F) +#define BIT_SET_CDEND_TXTIME_H_8197F(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H_8197F(x) | BIT_CDEND_TXTIME_H_8197F(v)) /* 2 REG_QUEUE_CTRL_8197F */ #define BIT_PTA_EDCCA_EN_8197F BIT(5) @@ -7384,165 +9557,241 @@ #define BIT_SHIFT_RTS_MAX_AGG_NUM_8197F 24 #define BIT_MASK_RTS_MAX_AGG_NUM_8197F 0x3f -#define BIT_RTS_MAX_AGG_NUM_8197F(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8197F) << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) -#define BITS_RTS_MAX_AGG_NUM_8197F (BIT_MASK_RTS_MAX_AGG_NUM_8197F << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) +#define BIT_RTS_MAX_AGG_NUM_8197F(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8197F) \ + << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) +#define BITS_RTS_MAX_AGG_NUM_8197F \ + (BIT_MASK_RTS_MAX_AGG_NUM_8197F << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) #define BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8197F)) -#define BIT_GET_RTS_MAX_AGG_NUM_8197F(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) & BIT_MASK_RTS_MAX_AGG_NUM_8197F) -#define BIT_SET_RTS_MAX_AGG_NUM_8197F(x, v) (BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) | BIT_RTS_MAX_AGG_NUM_8197F(v)) - +#define BIT_GET_RTS_MAX_AGG_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) & \ + BIT_MASK_RTS_MAX_AGG_NUM_8197F) +#define BIT_SET_RTS_MAX_AGG_NUM_8197F(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) | BIT_RTS_MAX_AGG_NUM_8197F(v)) #define BIT_SHIFT_MAX_AGG_NUM_8197F 16 #define BIT_MASK_MAX_AGG_NUM_8197F 0x3f -#define BIT_MAX_AGG_NUM_8197F(x) (((x) & BIT_MASK_MAX_AGG_NUM_8197F) << BIT_SHIFT_MAX_AGG_NUM_8197F) -#define BITS_MAX_AGG_NUM_8197F (BIT_MASK_MAX_AGG_NUM_8197F << BIT_SHIFT_MAX_AGG_NUM_8197F) +#define BIT_MAX_AGG_NUM_8197F(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM_8197F) << BIT_SHIFT_MAX_AGG_NUM_8197F) +#define BITS_MAX_AGG_NUM_8197F \ + (BIT_MASK_MAX_AGG_NUM_8197F << BIT_SHIFT_MAX_AGG_NUM_8197F) #define BIT_CLEAR_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_MAX_AGG_NUM_8197F)) -#define BIT_GET_MAX_AGG_NUM_8197F(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8197F) & BIT_MASK_MAX_AGG_NUM_8197F) -#define BIT_SET_MAX_AGG_NUM_8197F(x, v) (BIT_CLEAR_MAX_AGG_NUM_8197F(x) | BIT_MAX_AGG_NUM_8197F(v)) - +#define BIT_GET_MAX_AGG_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM_8197F) & BIT_MASK_MAX_AGG_NUM_8197F) +#define BIT_SET_MAX_AGG_NUM_8197F(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM_8197F(x) | BIT_MAX_AGG_NUM_8197F(v)) #define BIT_SHIFT_RTS_TXTIME_TH_8197F 8 #define BIT_MASK_RTS_TXTIME_TH_8197F 0xff -#define BIT_RTS_TXTIME_TH_8197F(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8197F) << BIT_SHIFT_RTS_TXTIME_TH_8197F) -#define BITS_RTS_TXTIME_TH_8197F (BIT_MASK_RTS_TXTIME_TH_8197F << BIT_SHIFT_RTS_TXTIME_TH_8197F) +#define BIT_RTS_TXTIME_TH_8197F(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH_8197F) << BIT_SHIFT_RTS_TXTIME_TH_8197F) +#define BITS_RTS_TXTIME_TH_8197F \ + (BIT_MASK_RTS_TXTIME_TH_8197F << BIT_SHIFT_RTS_TXTIME_TH_8197F) #define BIT_CLEAR_RTS_TXTIME_TH_8197F(x) ((x) & (~BITS_RTS_TXTIME_TH_8197F)) -#define BIT_GET_RTS_TXTIME_TH_8197F(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8197F) & BIT_MASK_RTS_TXTIME_TH_8197F) -#define BIT_SET_RTS_TXTIME_TH_8197F(x, v) (BIT_CLEAR_RTS_TXTIME_TH_8197F(x) | BIT_RTS_TXTIME_TH_8197F(v)) - +#define BIT_GET_RTS_TXTIME_TH_8197F(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8197F) & BIT_MASK_RTS_TXTIME_TH_8197F) +#define BIT_SET_RTS_TXTIME_TH_8197F(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH_8197F(x) | BIT_RTS_TXTIME_TH_8197F(v)) #define BIT_SHIFT_RTS_LEN_TH_8197F 0 #define BIT_MASK_RTS_LEN_TH_8197F 0xff -#define BIT_RTS_LEN_TH_8197F(x) (((x) & BIT_MASK_RTS_LEN_TH_8197F) << BIT_SHIFT_RTS_LEN_TH_8197F) -#define BITS_RTS_LEN_TH_8197F (BIT_MASK_RTS_LEN_TH_8197F << BIT_SHIFT_RTS_LEN_TH_8197F) +#define BIT_RTS_LEN_TH_8197F(x) \ + (((x) & BIT_MASK_RTS_LEN_TH_8197F) << BIT_SHIFT_RTS_LEN_TH_8197F) +#define BITS_RTS_LEN_TH_8197F \ + (BIT_MASK_RTS_LEN_TH_8197F << BIT_SHIFT_RTS_LEN_TH_8197F) #define BIT_CLEAR_RTS_LEN_TH_8197F(x) ((x) & (~BITS_RTS_LEN_TH_8197F)) -#define BIT_GET_RTS_LEN_TH_8197F(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8197F) & BIT_MASK_RTS_LEN_TH_8197F) -#define BIT_SET_RTS_LEN_TH_8197F(x, v) (BIT_CLEAR_RTS_LEN_TH_8197F(x) | BIT_RTS_LEN_TH_8197F(v)) - +#define BIT_GET_RTS_LEN_TH_8197F(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH_8197F) & BIT_MASK_RTS_LEN_TH_8197F) +#define BIT_SET_RTS_LEN_TH_8197F(x, v) \ + (BIT_CLEAR_RTS_LEN_TH_8197F(x) | BIT_RTS_LEN_TH_8197F(v)) /* 2 REG_BAR_MODE_CTRL_8197F */ #define BIT_SHIFT_BAR_RTY_LMT_8197F 16 #define BIT_MASK_BAR_RTY_LMT_8197F 0x3 -#define BIT_BAR_RTY_LMT_8197F(x) (((x) & BIT_MASK_BAR_RTY_LMT_8197F) << BIT_SHIFT_BAR_RTY_LMT_8197F) -#define BITS_BAR_RTY_LMT_8197F (BIT_MASK_BAR_RTY_LMT_8197F << BIT_SHIFT_BAR_RTY_LMT_8197F) +#define BIT_BAR_RTY_LMT_8197F(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT_8197F) << BIT_SHIFT_BAR_RTY_LMT_8197F) +#define BITS_BAR_RTY_LMT_8197F \ + (BIT_MASK_BAR_RTY_LMT_8197F << BIT_SHIFT_BAR_RTY_LMT_8197F) #define BIT_CLEAR_BAR_RTY_LMT_8197F(x) ((x) & (~BITS_BAR_RTY_LMT_8197F)) -#define BIT_GET_BAR_RTY_LMT_8197F(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8197F) & BIT_MASK_BAR_RTY_LMT_8197F) -#define BIT_SET_BAR_RTY_LMT_8197F(x, v) (BIT_CLEAR_BAR_RTY_LMT_8197F(x) | BIT_BAR_RTY_LMT_8197F(v)) - +#define BIT_GET_BAR_RTY_LMT_8197F(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT_8197F) & BIT_MASK_BAR_RTY_LMT_8197F) +#define BIT_SET_BAR_RTY_LMT_8197F(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT_8197F(x) | BIT_BAR_RTY_LMT_8197F(v)) #define BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F 8 #define BIT_MASK_BAR_PKT_TXTIME_TH_8197F 0xff -#define BIT_BAR_PKT_TXTIME_TH_8197F(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8197F) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) -#define BITS_BAR_PKT_TXTIME_TH_8197F (BIT_MASK_BAR_PKT_TXTIME_TH_8197F << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) -#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) ((x) & (~BITS_BAR_PKT_TXTIME_TH_8197F)) -#define BIT_GET_BAR_PKT_TXTIME_TH_8197F(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) & BIT_MASK_BAR_PKT_TXTIME_TH_8197F) -#define BIT_SET_BAR_PKT_TXTIME_TH_8197F(x, v) (BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) | BIT_BAR_PKT_TXTIME_TH_8197F(v)) +#define BIT_BAR_PKT_TXTIME_TH_8197F(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8197F) \ + << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) +#define BITS_BAR_PKT_TXTIME_TH_8197F \ + (BIT_MASK_BAR_PKT_TXTIME_TH_8197F << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) \ + ((x) & (~BITS_BAR_PKT_TXTIME_TH_8197F)) +#define BIT_GET_BAR_PKT_TXTIME_TH_8197F(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) & \ + BIT_MASK_BAR_PKT_TXTIME_TH_8197F) +#define BIT_SET_BAR_PKT_TXTIME_TH_8197F(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) | BIT_BAR_PKT_TXTIME_TH_8197F(v)) #define BIT_BAR_EN_V1_8197F BIT(6) #define BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F 0 #define BIT_MASK_BAR_PKTNUM_TH_V1_8197F 0x3f -#define BIT_BAR_PKTNUM_TH_V1_8197F(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8197F) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) -#define BITS_BAR_PKTNUM_TH_V1_8197F (BIT_MASK_BAR_PKTNUM_TH_V1_8197F << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) -#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) ((x) & (~BITS_BAR_PKTNUM_TH_V1_8197F)) -#define BIT_GET_BAR_PKTNUM_TH_V1_8197F(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) & BIT_MASK_BAR_PKTNUM_TH_V1_8197F) -#define BIT_SET_BAR_PKTNUM_TH_V1_8197F(x, v) (BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) | BIT_BAR_PKTNUM_TH_V1_8197F(v)) - +#define BIT_BAR_PKTNUM_TH_V1_8197F(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8197F) \ + << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) +#define BITS_BAR_PKTNUM_TH_V1_8197F \ + (BIT_MASK_BAR_PKTNUM_TH_V1_8197F << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) \ + ((x) & (~BITS_BAR_PKTNUM_TH_V1_8197F)) +#define BIT_GET_BAR_PKTNUM_TH_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) & \ + BIT_MASK_BAR_PKTNUM_TH_V1_8197F) +#define BIT_SET_BAR_PKTNUM_TH_V1_8197F(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) | BIT_BAR_PKTNUM_TH_V1_8197F(v)) /* 2 REG_RA_TRY_RATE_AGG_LMT_8197F */ #define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F 0 #define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F 0x3f -#define BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) -#define BITS_RA_TRY_RATE_AGG_LMT_V1_8197F (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) -#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8197F)) -#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8197F(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F) -#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8197F(x, v) (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) | BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(v)) - +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) +#define BITS_RA_TRY_RATE_AGG_LMT_V1_8197F \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8197F)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8197F(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8197F(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) | \ + BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(v)) /* 2 REG_MACID_SLEEP2_8197F */ #define BIT_SHIFT_MACID95_64PKTSLEEP_8197F 0 #define BIT_MASK_MACID95_64PKTSLEEP_8197F 0xffffffffL -#define BIT_MACID95_64PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8197F) << BIT_SHIFT_MACID95_64PKTSLEEP_8197F) -#define BITS_MACID95_64PKTSLEEP_8197F (BIT_MASK_MACID95_64PKTSLEEP_8197F << BIT_SHIFT_MACID95_64PKTSLEEP_8197F) -#define BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) ((x) & (~BITS_MACID95_64PKTSLEEP_8197F)) -#define BIT_GET_MACID95_64PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8197F) & BIT_MASK_MACID95_64PKTSLEEP_8197F) -#define BIT_SET_MACID95_64PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) | BIT_MACID95_64PKTSLEEP_8197F(v)) - +#define BIT_MACID95_64PKTSLEEP_8197F(x) \ + (((x) & BIT_MASK_MACID95_64PKTSLEEP_8197F) \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8197F) +#define BITS_MACID95_64PKTSLEEP_8197F \ + (BIT_MASK_MACID95_64PKTSLEEP_8197F \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8197F) +#define BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) \ + ((x) & (~BITS_MACID95_64PKTSLEEP_8197F)) +#define BIT_GET_MACID95_64PKTSLEEP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8197F) & \ + BIT_MASK_MACID95_64PKTSLEEP_8197F) +#define BIT_SET_MACID95_64PKTSLEEP_8197F(x, v) \ + (BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) | \ + BIT_MACID95_64PKTSLEEP_8197F(v)) /* 2 REG_MACID_SLEEP_8197F */ #define BIT_SHIFT_MACID31_0_PKTSLEEP_8197F 0 #define BIT_MASK_MACID31_0_PKTSLEEP_8197F 0xffffffffL -#define BIT_MACID31_0_PKTSLEEP_8197F(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8197F) << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) -#define BITS_MACID31_0_PKTSLEEP_8197F (BIT_MASK_MACID31_0_PKTSLEEP_8197F << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) -#define BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) ((x) & (~BITS_MACID31_0_PKTSLEEP_8197F)) -#define BIT_GET_MACID31_0_PKTSLEEP_8197F(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) & BIT_MASK_MACID31_0_PKTSLEEP_8197F) -#define BIT_SET_MACID31_0_PKTSLEEP_8197F(x, v) (BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) | BIT_MACID31_0_PKTSLEEP_8197F(v)) - +#define BIT_MACID31_0_PKTSLEEP_8197F(x) \ + (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8197F) \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) +#define BITS_MACID31_0_PKTSLEEP_8197F \ + (BIT_MASK_MACID31_0_PKTSLEEP_8197F \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) +#define BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) \ + ((x) & (~BITS_MACID31_0_PKTSLEEP_8197F)) +#define BIT_GET_MACID31_0_PKTSLEEP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) & \ + BIT_MASK_MACID31_0_PKTSLEEP_8197F) +#define BIT_SET_MACID31_0_PKTSLEEP_8197F(x, v) \ + (BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) | \ + BIT_MACID31_0_PKTSLEEP_8197F(v)) /* 2 REG_HW_SEQ0_8197F */ #define BIT_SHIFT_HW_SSN_SEQ0_8197F 0 #define BIT_MASK_HW_SSN_SEQ0_8197F 0xfff -#define BIT_HW_SSN_SEQ0_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8197F) << BIT_SHIFT_HW_SSN_SEQ0_8197F) -#define BITS_HW_SSN_SEQ0_8197F (BIT_MASK_HW_SSN_SEQ0_8197F << BIT_SHIFT_HW_SSN_SEQ0_8197F) +#define BIT_HW_SSN_SEQ0_8197F(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0_8197F) << BIT_SHIFT_HW_SSN_SEQ0_8197F) +#define BITS_HW_SSN_SEQ0_8197F \ + (BIT_MASK_HW_SSN_SEQ0_8197F << BIT_SHIFT_HW_SSN_SEQ0_8197F) #define BIT_CLEAR_HW_SSN_SEQ0_8197F(x) ((x) & (~BITS_HW_SSN_SEQ0_8197F)) -#define BIT_GET_HW_SSN_SEQ0_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8197F) & BIT_MASK_HW_SSN_SEQ0_8197F) -#define BIT_SET_HW_SSN_SEQ0_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ0_8197F(x) | BIT_HW_SSN_SEQ0_8197F(v)) - +#define BIT_GET_HW_SSN_SEQ0_8197F(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8197F) & BIT_MASK_HW_SSN_SEQ0_8197F) +#define BIT_SET_HW_SSN_SEQ0_8197F(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0_8197F(x) | BIT_HW_SSN_SEQ0_8197F(v)) /* 2 REG_HW_SEQ1_8197F */ #define BIT_SHIFT_HW_SSN_SEQ1_8197F 0 #define BIT_MASK_HW_SSN_SEQ1_8197F 0xfff -#define BIT_HW_SSN_SEQ1_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8197F) << BIT_SHIFT_HW_SSN_SEQ1_8197F) -#define BITS_HW_SSN_SEQ1_8197F (BIT_MASK_HW_SSN_SEQ1_8197F << BIT_SHIFT_HW_SSN_SEQ1_8197F) +#define BIT_HW_SSN_SEQ1_8197F(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1_8197F) << BIT_SHIFT_HW_SSN_SEQ1_8197F) +#define BITS_HW_SSN_SEQ1_8197F \ + (BIT_MASK_HW_SSN_SEQ1_8197F << BIT_SHIFT_HW_SSN_SEQ1_8197F) #define BIT_CLEAR_HW_SSN_SEQ1_8197F(x) ((x) & (~BITS_HW_SSN_SEQ1_8197F)) -#define BIT_GET_HW_SSN_SEQ1_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8197F) & BIT_MASK_HW_SSN_SEQ1_8197F) -#define BIT_SET_HW_SSN_SEQ1_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ1_8197F(x) | BIT_HW_SSN_SEQ1_8197F(v)) - +#define BIT_GET_HW_SSN_SEQ1_8197F(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8197F) & BIT_MASK_HW_SSN_SEQ1_8197F) +#define BIT_SET_HW_SSN_SEQ1_8197F(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1_8197F(x) | BIT_HW_SSN_SEQ1_8197F(v)) /* 2 REG_HW_SEQ2_8197F */ #define BIT_SHIFT_HW_SSN_SEQ2_8197F 0 #define BIT_MASK_HW_SSN_SEQ2_8197F 0xfff -#define BIT_HW_SSN_SEQ2_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8197F) << BIT_SHIFT_HW_SSN_SEQ2_8197F) -#define BITS_HW_SSN_SEQ2_8197F (BIT_MASK_HW_SSN_SEQ2_8197F << BIT_SHIFT_HW_SSN_SEQ2_8197F) +#define BIT_HW_SSN_SEQ2_8197F(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2_8197F) << BIT_SHIFT_HW_SSN_SEQ2_8197F) +#define BITS_HW_SSN_SEQ2_8197F \ + (BIT_MASK_HW_SSN_SEQ2_8197F << BIT_SHIFT_HW_SSN_SEQ2_8197F) #define BIT_CLEAR_HW_SSN_SEQ2_8197F(x) ((x) & (~BITS_HW_SSN_SEQ2_8197F)) -#define BIT_GET_HW_SSN_SEQ2_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8197F) & BIT_MASK_HW_SSN_SEQ2_8197F) -#define BIT_SET_HW_SSN_SEQ2_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ2_8197F(x) | BIT_HW_SSN_SEQ2_8197F(v)) - +#define BIT_GET_HW_SSN_SEQ2_8197F(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8197F) & BIT_MASK_HW_SSN_SEQ2_8197F) +#define BIT_SET_HW_SSN_SEQ2_8197F(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2_8197F(x) | BIT_HW_SSN_SEQ2_8197F(v)) /* 2 REG_HW_SEQ3_8197F */ #define BIT_SHIFT_CSI_HWSSN_SEL_8197F 12 #define BIT_MASK_CSI_HWSSN_SEL_8197F 0x3 -#define BIT_CSI_HWSSN_SEL_8197F(x) (((x) & BIT_MASK_CSI_HWSSN_SEL_8197F) << BIT_SHIFT_CSI_HWSSN_SEL_8197F) -#define BITS_CSI_HWSSN_SEL_8197F (BIT_MASK_CSI_HWSSN_SEL_8197F << BIT_SHIFT_CSI_HWSSN_SEL_8197F) +#define BIT_CSI_HWSSN_SEL_8197F(x) \ + (((x) & BIT_MASK_CSI_HWSSN_SEL_8197F) << BIT_SHIFT_CSI_HWSSN_SEL_8197F) +#define BITS_CSI_HWSSN_SEL_8197F \ + (BIT_MASK_CSI_HWSSN_SEL_8197F << BIT_SHIFT_CSI_HWSSN_SEL_8197F) #define BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) ((x) & (~BITS_CSI_HWSSN_SEL_8197F)) -#define BIT_GET_CSI_HWSSN_SEL_8197F(x) (((x) >> BIT_SHIFT_CSI_HWSSN_SEL_8197F) & BIT_MASK_CSI_HWSSN_SEL_8197F) -#define BIT_SET_CSI_HWSSN_SEL_8197F(x, v) (BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) | BIT_CSI_HWSSN_SEL_8197F(v)) - +#define BIT_GET_CSI_HWSSN_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_CSI_HWSSN_SEL_8197F) & BIT_MASK_CSI_HWSSN_SEL_8197F) +#define BIT_SET_CSI_HWSSN_SEL_8197F(x, v) \ + (BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) | BIT_CSI_HWSSN_SEL_8197F(v)) #define BIT_SHIFT_HW_SSN_SEQ3_8197F 0 #define BIT_MASK_HW_SSN_SEQ3_8197F 0xfff -#define BIT_HW_SSN_SEQ3_8197F(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8197F) << BIT_SHIFT_HW_SSN_SEQ3_8197F) -#define BITS_HW_SSN_SEQ3_8197F (BIT_MASK_HW_SSN_SEQ3_8197F << BIT_SHIFT_HW_SSN_SEQ3_8197F) +#define BIT_HW_SSN_SEQ3_8197F(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3_8197F) << BIT_SHIFT_HW_SSN_SEQ3_8197F) +#define BITS_HW_SSN_SEQ3_8197F \ + (BIT_MASK_HW_SSN_SEQ3_8197F << BIT_SHIFT_HW_SSN_SEQ3_8197F) #define BIT_CLEAR_HW_SSN_SEQ3_8197F(x) ((x) & (~BITS_HW_SSN_SEQ3_8197F)) -#define BIT_GET_HW_SSN_SEQ3_8197F(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8197F) & BIT_MASK_HW_SSN_SEQ3_8197F) -#define BIT_SET_HW_SSN_SEQ3_8197F(x, v) (BIT_CLEAR_HW_SSN_SEQ3_8197F(x) | BIT_HW_SSN_SEQ3_8197F(v)) - +#define BIT_GET_HW_SSN_SEQ3_8197F(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8197F) & BIT_MASK_HW_SSN_SEQ3_8197F) +#define BIT_SET_HW_SSN_SEQ3_8197F(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3_8197F(x) | BIT_HW_SSN_SEQ3_8197F(v)) /* 2 REG_NULL_PKT_STATUS_V1_8197F */ #define BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F 2 #define BIT_MASK_PTCL_TOTAL_PG_V1_8197F 0x1fff -#define BIT_PTCL_TOTAL_PG_V1_8197F(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V1_8197F) << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) -#define BITS_PTCL_TOTAL_PG_V1_8197F (BIT_MASK_PTCL_TOTAL_PG_V1_8197F << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) -#define BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) ((x) & (~BITS_PTCL_TOTAL_PG_V1_8197F)) -#define BIT_GET_PTCL_TOTAL_PG_V1_8197F(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) & BIT_MASK_PTCL_TOTAL_PG_V1_8197F) -#define BIT_SET_PTCL_TOTAL_PG_V1_8197F(x, v) (BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) | BIT_PTCL_TOTAL_PG_V1_8197F(v)) +#define BIT_PTCL_TOTAL_PG_V1_8197F(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V1_8197F) \ + << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) +#define BITS_PTCL_TOTAL_PG_V1_8197F \ + (BIT_MASK_PTCL_TOTAL_PG_V1_8197F << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) +#define BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) \ + ((x) & (~BITS_PTCL_TOTAL_PG_V1_8197F)) +#define BIT_GET_PTCL_TOTAL_PG_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) & \ + BIT_MASK_PTCL_TOTAL_PG_V1_8197F) +#define BIT_SET_PTCL_TOTAL_PG_V1_8197F(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) | BIT_PTCL_TOTAL_PG_V1_8197F(v)) #define BIT_TX_NULL_1_8197F BIT(1) #define BIT_TX_NULL_0_8197F BIT(0) @@ -7575,12 +9824,20 @@ #define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F 0 #define BIT_MASK_BT_POLLUTE_PKT_CNT_8197F 0xffff -#define BIT_BT_POLLUTE_PKT_CNT_8197F(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8197F) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) -#define BITS_BT_POLLUTE_PKT_CNT_8197F (BIT_MASK_BT_POLLUTE_PKT_CNT_8197F << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) -#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8197F)) -#define BIT_GET_BT_POLLUTE_PKT_CNT_8197F(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) & BIT_MASK_BT_POLLUTE_PKT_CNT_8197F) -#define BIT_SET_BT_POLLUTE_PKT_CNT_8197F(x, v) (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) | BIT_BT_POLLUTE_PKT_CNT_8197F(v)) - +#define BIT_BT_POLLUTE_PKT_CNT_8197F(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8197F) \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) +#define BITS_BT_POLLUTE_PKT_CNT_8197F \ + (BIT_MASK_BT_POLLUTE_PKT_CNT_8197F \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) +#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) \ + ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8197F)) +#define BIT_GET_BT_POLLUTE_PKT_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) & \ + BIT_MASK_BT_POLLUTE_PKT_CNT_8197F) +#define BIT_SET_BT_POLLUTE_PKT_CNT_8197F(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) | \ + BIT_BT_POLLUTE_PKT_CNT_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -7588,12 +9845,15 @@ #define BIT_SHIFT_PTCL_DBG_8197F 0 #define BIT_MASK_PTCL_DBG_8197F 0xffffffffL -#define BIT_PTCL_DBG_8197F(x) (((x) & BIT_MASK_PTCL_DBG_8197F) << BIT_SHIFT_PTCL_DBG_8197F) -#define BITS_PTCL_DBG_8197F (BIT_MASK_PTCL_DBG_8197F << BIT_SHIFT_PTCL_DBG_8197F) +#define BIT_PTCL_DBG_8197F(x) \ + (((x) & BIT_MASK_PTCL_DBG_8197F) << BIT_SHIFT_PTCL_DBG_8197F) +#define BITS_PTCL_DBG_8197F \ + (BIT_MASK_PTCL_DBG_8197F << BIT_SHIFT_PTCL_DBG_8197F) #define BIT_CLEAR_PTCL_DBG_8197F(x) ((x) & (~BITS_PTCL_DBG_8197F)) -#define BIT_GET_PTCL_DBG_8197F(x) (((x) >> BIT_SHIFT_PTCL_DBG_8197F) & BIT_MASK_PTCL_DBG_8197F) -#define BIT_SET_PTCL_DBG_8197F(x, v) (BIT_CLEAR_PTCL_DBG_8197F(x) | BIT_PTCL_DBG_8197F(v)) - +#define BIT_GET_PTCL_DBG_8197F(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_8197F) & BIT_MASK_PTCL_DBG_8197F) +#define BIT_SET_PTCL_DBG_8197F(x, v) \ + (BIT_CLEAR_PTCL_DBG_8197F(x) | BIT_PTCL_DBG_8197F(v)) /* 2 REG_TXOP_EXTRA_CTRL_8197F */ #define BIT_TXOP_EFFICIENCY_EN_8197F BIT(0) @@ -7604,22 +9864,28 @@ #define BIT_SHIFT_TRI_HEAD_ADDR_8197F 16 #define BIT_MASK_TRI_HEAD_ADDR_8197F 0xfff -#define BIT_TRI_HEAD_ADDR_8197F(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8197F) << BIT_SHIFT_TRI_HEAD_ADDR_8197F) -#define BITS_TRI_HEAD_ADDR_8197F (BIT_MASK_TRI_HEAD_ADDR_8197F << BIT_SHIFT_TRI_HEAD_ADDR_8197F) +#define BIT_TRI_HEAD_ADDR_8197F(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR_8197F) << BIT_SHIFT_TRI_HEAD_ADDR_8197F) +#define BITS_TRI_HEAD_ADDR_8197F \ + (BIT_MASK_TRI_HEAD_ADDR_8197F << BIT_SHIFT_TRI_HEAD_ADDR_8197F) #define BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) ((x) & (~BITS_TRI_HEAD_ADDR_8197F)) -#define BIT_GET_TRI_HEAD_ADDR_8197F(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8197F) & BIT_MASK_TRI_HEAD_ADDR_8197F) -#define BIT_SET_TRI_HEAD_ADDR_8197F(x, v) (BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) | BIT_TRI_HEAD_ADDR_8197F(v)) +#define BIT_GET_TRI_HEAD_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8197F) & BIT_MASK_TRI_HEAD_ADDR_8197F) +#define BIT_SET_TRI_HEAD_ADDR_8197F(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) | BIT_TRI_HEAD_ADDR_8197F(v)) #define BIT_DROP_TH_EN_8197F BIT(8) #define BIT_SHIFT_DROP_TH_8197F 0 #define BIT_MASK_DROP_TH_8197F 0xff -#define BIT_DROP_TH_8197F(x) (((x) & BIT_MASK_DROP_TH_8197F) << BIT_SHIFT_DROP_TH_8197F) +#define BIT_DROP_TH_8197F(x) \ + (((x) & BIT_MASK_DROP_TH_8197F) << BIT_SHIFT_DROP_TH_8197F) #define BITS_DROP_TH_8197F (BIT_MASK_DROP_TH_8197F << BIT_SHIFT_DROP_TH_8197F) #define BIT_CLEAR_DROP_TH_8197F(x) ((x) & (~BITS_DROP_TH_8197F)) -#define BIT_GET_DROP_TH_8197F(x) (((x) >> BIT_SHIFT_DROP_TH_8197F) & BIT_MASK_DROP_TH_8197F) -#define BIT_SET_DROP_TH_8197F(x, v) (BIT_CLEAR_DROP_TH_8197F(x) | BIT_DROP_TH_8197F(v)) - +#define BIT_GET_DROP_TH_8197F(x) \ + (((x) >> BIT_SHIFT_DROP_TH_8197F) & BIT_MASK_DROP_TH_8197F) +#define BIT_SET_DROP_TH_8197F(x, v) \ + (BIT_CLEAR_DROP_TH_8197F(x) | BIT_DROP_TH_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -7635,220 +9901,293 @@ #define BIT_SHIFT_GTAB_ID_8197F 28 #define BIT_MASK_GTAB_ID_8197F 0x7 -#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_GTAB_ID_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) #define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) #define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) -#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) -#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) - +#define BIT_GET_GTAB_ID_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) #define BIT_SHIFT_AC1_PKT_INFO_8197F 16 #define BIT_MASK_AC1_PKT_INFO_8197F 0xfff -#define BIT_AC1_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC1_PKT_INFO_8197F) << BIT_SHIFT_AC1_PKT_INFO_8197F) -#define BITS_AC1_PKT_INFO_8197F (BIT_MASK_AC1_PKT_INFO_8197F << BIT_SHIFT_AC1_PKT_INFO_8197F) +#define BIT_AC1_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC1_PKT_INFO_8197F) << BIT_SHIFT_AC1_PKT_INFO_8197F) +#define BITS_AC1_PKT_INFO_8197F \ + (BIT_MASK_AC1_PKT_INFO_8197F << BIT_SHIFT_AC1_PKT_INFO_8197F) #define BIT_CLEAR_AC1_PKT_INFO_8197F(x) ((x) & (~BITS_AC1_PKT_INFO_8197F)) -#define BIT_GET_AC1_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8197F) & BIT_MASK_AC1_PKT_INFO_8197F) -#define BIT_SET_AC1_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC1_PKT_INFO_8197F(x) | BIT_AC1_PKT_INFO_8197F(v)) +#define BIT_GET_AC1_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC1_PKT_INFO_8197F) & BIT_MASK_AC1_PKT_INFO_8197F) +#define BIT_SET_AC1_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC1_PKT_INFO_8197F(x) | BIT_AC1_PKT_INFO_8197F(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8197F 12 #define BIT_MASK_GTAB_ID_V1_8197F 0x7 -#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) -#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_GTAB_ID_V1_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F \ + (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) #define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) -#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) -#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) - +#define BIT_GET_GTAB_ID_V1_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) #define BIT_SHIFT_AC0_PKT_INFO_8197F 0 #define BIT_MASK_AC0_PKT_INFO_8197F 0xfff -#define BIT_AC0_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC0_PKT_INFO_8197F) << BIT_SHIFT_AC0_PKT_INFO_8197F) -#define BITS_AC0_PKT_INFO_8197F (BIT_MASK_AC0_PKT_INFO_8197F << BIT_SHIFT_AC0_PKT_INFO_8197F) +#define BIT_AC0_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC0_PKT_INFO_8197F) << BIT_SHIFT_AC0_PKT_INFO_8197F) +#define BITS_AC0_PKT_INFO_8197F \ + (BIT_MASK_AC0_PKT_INFO_8197F << BIT_SHIFT_AC0_PKT_INFO_8197F) #define BIT_CLEAR_AC0_PKT_INFO_8197F(x) ((x) & (~BITS_AC0_PKT_INFO_8197F)) -#define BIT_GET_AC0_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8197F) & BIT_MASK_AC0_PKT_INFO_8197F) -#define BIT_SET_AC0_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC0_PKT_INFO_8197F(x) | BIT_AC0_PKT_INFO_8197F(v)) - +#define BIT_GET_AC0_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC0_PKT_INFO_8197F) & BIT_MASK_AC0_PKT_INFO_8197F) +#define BIT_SET_AC0_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC0_PKT_INFO_8197F(x) | BIT_AC0_PKT_INFO_8197F(v)) /* 2 REG_Q2_Q3_INFO_8197F */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31) #define BIT_SHIFT_GTAB_ID_8197F 28 #define BIT_MASK_GTAB_ID_8197F 0x7 -#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_GTAB_ID_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) #define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) #define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) -#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) -#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) - +#define BIT_GET_GTAB_ID_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) #define BIT_SHIFT_AC3_PKT_INFO_8197F 16 #define BIT_MASK_AC3_PKT_INFO_8197F 0xfff -#define BIT_AC3_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC3_PKT_INFO_8197F) << BIT_SHIFT_AC3_PKT_INFO_8197F) -#define BITS_AC3_PKT_INFO_8197F (BIT_MASK_AC3_PKT_INFO_8197F << BIT_SHIFT_AC3_PKT_INFO_8197F) +#define BIT_AC3_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC3_PKT_INFO_8197F) << BIT_SHIFT_AC3_PKT_INFO_8197F) +#define BITS_AC3_PKT_INFO_8197F \ + (BIT_MASK_AC3_PKT_INFO_8197F << BIT_SHIFT_AC3_PKT_INFO_8197F) #define BIT_CLEAR_AC3_PKT_INFO_8197F(x) ((x) & (~BITS_AC3_PKT_INFO_8197F)) -#define BIT_GET_AC3_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8197F) & BIT_MASK_AC3_PKT_INFO_8197F) -#define BIT_SET_AC3_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC3_PKT_INFO_8197F(x) | BIT_AC3_PKT_INFO_8197F(v)) +#define BIT_GET_AC3_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC3_PKT_INFO_8197F) & BIT_MASK_AC3_PKT_INFO_8197F) +#define BIT_SET_AC3_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC3_PKT_INFO_8197F(x) | BIT_AC3_PKT_INFO_8197F(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8197F 12 #define BIT_MASK_GTAB_ID_V1_8197F 0x7 -#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) -#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_GTAB_ID_V1_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F \ + (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) #define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) -#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) -#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) - +#define BIT_GET_GTAB_ID_V1_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) #define BIT_SHIFT_AC2_PKT_INFO_8197F 0 #define BIT_MASK_AC2_PKT_INFO_8197F 0xfff -#define BIT_AC2_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC2_PKT_INFO_8197F) << BIT_SHIFT_AC2_PKT_INFO_8197F) -#define BITS_AC2_PKT_INFO_8197F (BIT_MASK_AC2_PKT_INFO_8197F << BIT_SHIFT_AC2_PKT_INFO_8197F) +#define BIT_AC2_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC2_PKT_INFO_8197F) << BIT_SHIFT_AC2_PKT_INFO_8197F) +#define BITS_AC2_PKT_INFO_8197F \ + (BIT_MASK_AC2_PKT_INFO_8197F << BIT_SHIFT_AC2_PKT_INFO_8197F) #define BIT_CLEAR_AC2_PKT_INFO_8197F(x) ((x) & (~BITS_AC2_PKT_INFO_8197F)) -#define BIT_GET_AC2_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8197F) & BIT_MASK_AC2_PKT_INFO_8197F) -#define BIT_SET_AC2_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC2_PKT_INFO_8197F(x) | BIT_AC2_PKT_INFO_8197F(v)) - +#define BIT_GET_AC2_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC2_PKT_INFO_8197F) & BIT_MASK_AC2_PKT_INFO_8197F) +#define BIT_SET_AC2_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC2_PKT_INFO_8197F(x) | BIT_AC2_PKT_INFO_8197F(v)) /* 2 REG_Q4_Q5_INFO_8197F */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31) #define BIT_SHIFT_GTAB_ID_8197F 28 #define BIT_MASK_GTAB_ID_8197F 0x7 -#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_GTAB_ID_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) #define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) #define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) -#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) -#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) - +#define BIT_GET_GTAB_ID_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) #define BIT_SHIFT_AC5_PKT_INFO_8197F 16 #define BIT_MASK_AC5_PKT_INFO_8197F 0xfff -#define BIT_AC5_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC5_PKT_INFO_8197F) << BIT_SHIFT_AC5_PKT_INFO_8197F) -#define BITS_AC5_PKT_INFO_8197F (BIT_MASK_AC5_PKT_INFO_8197F << BIT_SHIFT_AC5_PKT_INFO_8197F) +#define BIT_AC5_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC5_PKT_INFO_8197F) << BIT_SHIFT_AC5_PKT_INFO_8197F) +#define BITS_AC5_PKT_INFO_8197F \ + (BIT_MASK_AC5_PKT_INFO_8197F << BIT_SHIFT_AC5_PKT_INFO_8197F) #define BIT_CLEAR_AC5_PKT_INFO_8197F(x) ((x) & (~BITS_AC5_PKT_INFO_8197F)) -#define BIT_GET_AC5_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8197F) & BIT_MASK_AC5_PKT_INFO_8197F) -#define BIT_SET_AC5_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC5_PKT_INFO_8197F(x) | BIT_AC5_PKT_INFO_8197F(v)) +#define BIT_GET_AC5_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC5_PKT_INFO_8197F) & BIT_MASK_AC5_PKT_INFO_8197F) +#define BIT_SET_AC5_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC5_PKT_INFO_8197F(x) | BIT_AC5_PKT_INFO_8197F(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8197F 12 #define BIT_MASK_GTAB_ID_V1_8197F 0x7 -#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) -#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_GTAB_ID_V1_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F \ + (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) #define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) -#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) -#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) - +#define BIT_GET_GTAB_ID_V1_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) #define BIT_SHIFT_AC4_PKT_INFO_8197F 0 #define BIT_MASK_AC4_PKT_INFO_8197F 0xfff -#define BIT_AC4_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC4_PKT_INFO_8197F) << BIT_SHIFT_AC4_PKT_INFO_8197F) -#define BITS_AC4_PKT_INFO_8197F (BIT_MASK_AC4_PKT_INFO_8197F << BIT_SHIFT_AC4_PKT_INFO_8197F) +#define BIT_AC4_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC4_PKT_INFO_8197F) << BIT_SHIFT_AC4_PKT_INFO_8197F) +#define BITS_AC4_PKT_INFO_8197F \ + (BIT_MASK_AC4_PKT_INFO_8197F << BIT_SHIFT_AC4_PKT_INFO_8197F) #define BIT_CLEAR_AC4_PKT_INFO_8197F(x) ((x) & (~BITS_AC4_PKT_INFO_8197F)) -#define BIT_GET_AC4_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8197F) & BIT_MASK_AC4_PKT_INFO_8197F) -#define BIT_SET_AC4_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC4_PKT_INFO_8197F(x) | BIT_AC4_PKT_INFO_8197F(v)) - +#define BIT_GET_AC4_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC4_PKT_INFO_8197F) & BIT_MASK_AC4_PKT_INFO_8197F) +#define BIT_SET_AC4_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC4_PKT_INFO_8197F(x) | BIT_AC4_PKT_INFO_8197F(v)) /* 2 REG_Q6_Q7_INFO_8197F */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31) #define BIT_SHIFT_GTAB_ID_8197F 28 #define BIT_MASK_GTAB_ID_8197F 0x7 -#define BIT_GTAB_ID_8197F(x) (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) +#define BIT_GTAB_ID_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F) #define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F) #define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F)) -#define BIT_GET_GTAB_ID_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) -#define BIT_SET_GTAB_ID_8197F(x, v) (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) - +#define BIT_GET_GTAB_ID_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F) +#define BIT_SET_GTAB_ID_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v)) #define BIT_SHIFT_AC7_PKT_INFO_8197F 16 #define BIT_MASK_AC7_PKT_INFO_8197F 0xfff -#define BIT_AC7_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC7_PKT_INFO_8197F) << BIT_SHIFT_AC7_PKT_INFO_8197F) -#define BITS_AC7_PKT_INFO_8197F (BIT_MASK_AC7_PKT_INFO_8197F << BIT_SHIFT_AC7_PKT_INFO_8197F) +#define BIT_AC7_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC7_PKT_INFO_8197F) << BIT_SHIFT_AC7_PKT_INFO_8197F) +#define BITS_AC7_PKT_INFO_8197F \ + (BIT_MASK_AC7_PKT_INFO_8197F << BIT_SHIFT_AC7_PKT_INFO_8197F) #define BIT_CLEAR_AC7_PKT_INFO_8197F(x) ((x) & (~BITS_AC7_PKT_INFO_8197F)) -#define BIT_GET_AC7_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8197F) & BIT_MASK_AC7_PKT_INFO_8197F) -#define BIT_SET_AC7_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC7_PKT_INFO_8197F(x) | BIT_AC7_PKT_INFO_8197F(v)) +#define BIT_GET_AC7_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC7_PKT_INFO_8197F) & BIT_MASK_AC7_PKT_INFO_8197F) +#define BIT_SET_AC7_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC7_PKT_INFO_8197F(x) | BIT_AC7_PKT_INFO_8197F(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8197F 12 #define BIT_MASK_GTAB_ID_V1_8197F 0x7 -#define BIT_GTAB_ID_V1_8197F(x) (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) -#define BITS_GTAB_ID_V1_8197F (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BIT_GTAB_ID_V1_8197F(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F) +#define BITS_GTAB_ID_V1_8197F \ + (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F) #define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F)) -#define BIT_GET_GTAB_ID_V1_8197F(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) -#define BIT_SET_GTAB_ID_V1_8197F(x, v) (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) - +#define BIT_GET_GTAB_ID_V1_8197F(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F) +#define BIT_SET_GTAB_ID_V1_8197F(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v)) #define BIT_SHIFT_AC6_PKT_INFO_8197F 0 #define BIT_MASK_AC6_PKT_INFO_8197F 0xfff -#define BIT_AC6_PKT_INFO_8197F(x) (((x) & BIT_MASK_AC6_PKT_INFO_8197F) << BIT_SHIFT_AC6_PKT_INFO_8197F) -#define BITS_AC6_PKT_INFO_8197F (BIT_MASK_AC6_PKT_INFO_8197F << BIT_SHIFT_AC6_PKT_INFO_8197F) +#define BIT_AC6_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_AC6_PKT_INFO_8197F) << BIT_SHIFT_AC6_PKT_INFO_8197F) +#define BITS_AC6_PKT_INFO_8197F \ + (BIT_MASK_AC6_PKT_INFO_8197F << BIT_SHIFT_AC6_PKT_INFO_8197F) #define BIT_CLEAR_AC6_PKT_INFO_8197F(x) ((x) & (~BITS_AC6_PKT_INFO_8197F)) -#define BIT_GET_AC6_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8197F) & BIT_MASK_AC6_PKT_INFO_8197F) -#define BIT_SET_AC6_PKT_INFO_8197F(x, v) (BIT_CLEAR_AC6_PKT_INFO_8197F(x) | BIT_AC6_PKT_INFO_8197F(v)) - +#define BIT_GET_AC6_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_AC6_PKT_INFO_8197F) & BIT_MASK_AC6_PKT_INFO_8197F) +#define BIT_SET_AC6_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_AC6_PKT_INFO_8197F(x) | BIT_AC6_PKT_INFO_8197F(v)) /* 2 REG_MGQ_HIQ_INFO_8197F */ #define BIT_SHIFT_HIQ_PKT_INFO_8197F 16 #define BIT_MASK_HIQ_PKT_INFO_8197F 0xfff -#define BIT_HIQ_PKT_INFO_8197F(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8197F) << BIT_SHIFT_HIQ_PKT_INFO_8197F) -#define BITS_HIQ_PKT_INFO_8197F (BIT_MASK_HIQ_PKT_INFO_8197F << BIT_SHIFT_HIQ_PKT_INFO_8197F) +#define BIT_HIQ_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_HIQ_PKT_INFO_8197F) << BIT_SHIFT_HIQ_PKT_INFO_8197F) +#define BITS_HIQ_PKT_INFO_8197F \ + (BIT_MASK_HIQ_PKT_INFO_8197F << BIT_SHIFT_HIQ_PKT_INFO_8197F) #define BIT_CLEAR_HIQ_PKT_INFO_8197F(x) ((x) & (~BITS_HIQ_PKT_INFO_8197F)) -#define BIT_GET_HIQ_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8197F) & BIT_MASK_HIQ_PKT_INFO_8197F) -#define BIT_SET_HIQ_PKT_INFO_8197F(x, v) (BIT_CLEAR_HIQ_PKT_INFO_8197F(x) | BIT_HIQ_PKT_INFO_8197F(v)) - +#define BIT_GET_HIQ_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8197F) & BIT_MASK_HIQ_PKT_INFO_8197F) +#define BIT_SET_HIQ_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_HIQ_PKT_INFO_8197F(x) | BIT_HIQ_PKT_INFO_8197F(v)) #define BIT_SHIFT_MGQ_PKT_INFO_8197F 0 #define BIT_MASK_MGQ_PKT_INFO_8197F 0xfff -#define BIT_MGQ_PKT_INFO_8197F(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8197F) << BIT_SHIFT_MGQ_PKT_INFO_8197F) -#define BITS_MGQ_PKT_INFO_8197F (BIT_MASK_MGQ_PKT_INFO_8197F << BIT_SHIFT_MGQ_PKT_INFO_8197F) +#define BIT_MGQ_PKT_INFO_8197F(x) \ + (((x) & BIT_MASK_MGQ_PKT_INFO_8197F) << BIT_SHIFT_MGQ_PKT_INFO_8197F) +#define BITS_MGQ_PKT_INFO_8197F \ + (BIT_MASK_MGQ_PKT_INFO_8197F << BIT_SHIFT_MGQ_PKT_INFO_8197F) #define BIT_CLEAR_MGQ_PKT_INFO_8197F(x) ((x) & (~BITS_MGQ_PKT_INFO_8197F)) -#define BIT_GET_MGQ_PKT_INFO_8197F(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8197F) & BIT_MASK_MGQ_PKT_INFO_8197F) -#define BIT_SET_MGQ_PKT_INFO_8197F(x, v) (BIT_CLEAR_MGQ_PKT_INFO_8197F(x) | BIT_MGQ_PKT_INFO_8197F(v)) - +#define BIT_GET_MGQ_PKT_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8197F) & BIT_MASK_MGQ_PKT_INFO_8197F) +#define BIT_SET_MGQ_PKT_INFO_8197F(x, v) \ + (BIT_CLEAR_MGQ_PKT_INFO_8197F(x) | BIT_MGQ_PKT_INFO_8197F(v)) /* 2 REG_CMDQ_BCNQ_INFO_8197F */ #define BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F 16 #define BIT_MASK_BCNQ_PKT_INFO_V1_8197F 0xfff -#define BIT_BCNQ_PKT_INFO_V1_8197F(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_V1_8197F) << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) -#define BITS_BCNQ_PKT_INFO_V1_8197F (BIT_MASK_BCNQ_PKT_INFO_V1_8197F << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) -#define BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) ((x) & (~BITS_BCNQ_PKT_INFO_V1_8197F)) -#define BIT_GET_BCNQ_PKT_INFO_V1_8197F(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) & BIT_MASK_BCNQ_PKT_INFO_V1_8197F) -#define BIT_SET_BCNQ_PKT_INFO_V1_8197F(x, v) (BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) | BIT_BCNQ_PKT_INFO_V1_8197F(v)) - +#define BIT_BCNQ_PKT_INFO_V1_8197F(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO_V1_8197F) \ + << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) +#define BITS_BCNQ_PKT_INFO_V1_8197F \ + (BIT_MASK_BCNQ_PKT_INFO_V1_8197F << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) +#define BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) \ + ((x) & (~BITS_BCNQ_PKT_INFO_V1_8197F)) +#define BIT_GET_BCNQ_PKT_INFO_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) & \ + BIT_MASK_BCNQ_PKT_INFO_V1_8197F) +#define BIT_SET_BCNQ_PKT_INFO_V1_8197F(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) | BIT_BCNQ_PKT_INFO_V1_8197F(v)) #define BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F 0 #define BIT_MASK_CMDQ_PKT_INFO_V1_8197F 0xfff -#define BIT_CMDQ_PKT_INFO_V1_8197F(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_V1_8197F) << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) -#define BITS_CMDQ_PKT_INFO_V1_8197F (BIT_MASK_CMDQ_PKT_INFO_V1_8197F << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) -#define BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) ((x) & (~BITS_CMDQ_PKT_INFO_V1_8197F)) -#define BIT_GET_CMDQ_PKT_INFO_V1_8197F(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) & BIT_MASK_CMDQ_PKT_INFO_V1_8197F) -#define BIT_SET_CMDQ_PKT_INFO_V1_8197F(x, v) (BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) | BIT_CMDQ_PKT_INFO_V1_8197F(v)) - +#define BIT_CMDQ_PKT_INFO_V1_8197F(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO_V1_8197F) \ + << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) +#define BITS_CMDQ_PKT_INFO_V1_8197F \ + (BIT_MASK_CMDQ_PKT_INFO_V1_8197F << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) +#define BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) \ + ((x) & (~BITS_CMDQ_PKT_INFO_V1_8197F)) +#define BIT_GET_CMDQ_PKT_INFO_V1_8197F(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) & \ + BIT_MASK_CMDQ_PKT_INFO_V1_8197F) +#define BIT_SET_CMDQ_PKT_INFO_V1_8197F(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) | BIT_CMDQ_PKT_INFO_V1_8197F(v)) /* 2 REG_USEREG_SETTING_8197F */ #define BIT_NDPA_USEREG_8197F BIT(21) #define BIT_SHIFT_RETRY_USEREG_8197F 19 #define BIT_MASK_RETRY_USEREG_8197F 0x3 -#define BIT_RETRY_USEREG_8197F(x) (((x) & BIT_MASK_RETRY_USEREG_8197F) << BIT_SHIFT_RETRY_USEREG_8197F) -#define BITS_RETRY_USEREG_8197F (BIT_MASK_RETRY_USEREG_8197F << BIT_SHIFT_RETRY_USEREG_8197F) +#define BIT_RETRY_USEREG_8197F(x) \ + (((x) & BIT_MASK_RETRY_USEREG_8197F) << BIT_SHIFT_RETRY_USEREG_8197F) +#define BITS_RETRY_USEREG_8197F \ + (BIT_MASK_RETRY_USEREG_8197F << BIT_SHIFT_RETRY_USEREG_8197F) #define BIT_CLEAR_RETRY_USEREG_8197F(x) ((x) & (~BITS_RETRY_USEREG_8197F)) -#define BIT_GET_RETRY_USEREG_8197F(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8197F) & BIT_MASK_RETRY_USEREG_8197F) -#define BIT_SET_RETRY_USEREG_8197F(x, v) (BIT_CLEAR_RETRY_USEREG_8197F(x) | BIT_RETRY_USEREG_8197F(v)) - +#define BIT_GET_RETRY_USEREG_8197F(x) \ + (((x) >> BIT_SHIFT_RETRY_USEREG_8197F) & BIT_MASK_RETRY_USEREG_8197F) +#define BIT_SET_RETRY_USEREG_8197F(x, v) \ + (BIT_CLEAR_RETRY_USEREG_8197F(x) | BIT_RETRY_USEREG_8197F(v)) #define BIT_SHIFT_TRYPKT_USEREG_8197F 17 #define BIT_MASK_TRYPKT_USEREG_8197F 0x3 -#define BIT_TRYPKT_USEREG_8197F(x) (((x) & BIT_MASK_TRYPKT_USEREG_8197F) << BIT_SHIFT_TRYPKT_USEREG_8197F) -#define BITS_TRYPKT_USEREG_8197F (BIT_MASK_TRYPKT_USEREG_8197F << BIT_SHIFT_TRYPKT_USEREG_8197F) +#define BIT_TRYPKT_USEREG_8197F(x) \ + (((x) & BIT_MASK_TRYPKT_USEREG_8197F) << BIT_SHIFT_TRYPKT_USEREG_8197F) +#define BITS_TRYPKT_USEREG_8197F \ + (BIT_MASK_TRYPKT_USEREG_8197F << BIT_SHIFT_TRYPKT_USEREG_8197F) #define BIT_CLEAR_TRYPKT_USEREG_8197F(x) ((x) & (~BITS_TRYPKT_USEREG_8197F)) -#define BIT_GET_TRYPKT_USEREG_8197F(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8197F) & BIT_MASK_TRYPKT_USEREG_8197F) -#define BIT_SET_TRYPKT_USEREG_8197F(x, v) (BIT_CLEAR_TRYPKT_USEREG_8197F(x) | BIT_TRYPKT_USEREG_8197F(v)) +#define BIT_GET_TRYPKT_USEREG_8197F(x) \ + (((x) >> BIT_SHIFT_TRYPKT_USEREG_8197F) & BIT_MASK_TRYPKT_USEREG_8197F) +#define BIT_SET_TRYPKT_USEREG_8197F(x, v) \ + (BIT_CLEAR_TRYPKT_USEREG_8197F(x) | BIT_TRYPKT_USEREG_8197F(v)) #define BIT_CTLPKT_USEREG_8197F BIT(16) @@ -7856,12 +10195,15 @@ #define BIT_SHIFT_AESIV_OFFSET_8197F 0 #define BIT_MASK_AESIV_OFFSET_8197F 0xfff -#define BIT_AESIV_OFFSET_8197F(x) (((x) & BIT_MASK_AESIV_OFFSET_8197F) << BIT_SHIFT_AESIV_OFFSET_8197F) -#define BITS_AESIV_OFFSET_8197F (BIT_MASK_AESIV_OFFSET_8197F << BIT_SHIFT_AESIV_OFFSET_8197F) +#define BIT_AESIV_OFFSET_8197F(x) \ + (((x) & BIT_MASK_AESIV_OFFSET_8197F) << BIT_SHIFT_AESIV_OFFSET_8197F) +#define BITS_AESIV_OFFSET_8197F \ + (BIT_MASK_AESIV_OFFSET_8197F << BIT_SHIFT_AESIV_OFFSET_8197F) #define BIT_CLEAR_AESIV_OFFSET_8197F(x) ((x) & (~BITS_AESIV_OFFSET_8197F)) -#define BIT_GET_AESIV_OFFSET_8197F(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8197F) & BIT_MASK_AESIV_OFFSET_8197F) -#define BIT_SET_AESIV_OFFSET_8197F(x, v) (BIT_CLEAR_AESIV_OFFSET_8197F(x) | BIT_AESIV_OFFSET_8197F(v)) - +#define BIT_GET_AESIV_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_AESIV_OFFSET_8197F) & BIT_MASK_AESIV_OFFSET_8197F) +#define BIT_SET_AESIV_OFFSET_8197F(x, v) \ + (BIT_CLEAR_AESIV_OFFSET_8197F(x) | BIT_AESIV_OFFSET_8197F(v)) /* 2 REG_BF0_TIME_SETTING_8197F */ #define BIT_BF0_TIMER_SET_8197F BIT(31) @@ -7871,21 +10213,30 @@ #define BIT_SHIFT_BF0_PRETIME_OVER_8197F 16 #define BIT_MASK_BF0_PRETIME_OVER_8197F 0xfff -#define BIT_BF0_PRETIME_OVER_8197F(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8197F) << BIT_SHIFT_BF0_PRETIME_OVER_8197F) -#define BITS_BF0_PRETIME_OVER_8197F (BIT_MASK_BF0_PRETIME_OVER_8197F << BIT_SHIFT_BF0_PRETIME_OVER_8197F) -#define BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) ((x) & (~BITS_BF0_PRETIME_OVER_8197F)) -#define BIT_GET_BF0_PRETIME_OVER_8197F(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8197F) & BIT_MASK_BF0_PRETIME_OVER_8197F) -#define BIT_SET_BF0_PRETIME_OVER_8197F(x, v) (BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) | BIT_BF0_PRETIME_OVER_8197F(v)) - +#define BIT_BF0_PRETIME_OVER_8197F(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER_8197F) \ + << BIT_SHIFT_BF0_PRETIME_OVER_8197F) +#define BITS_BF0_PRETIME_OVER_8197F \ + (BIT_MASK_BF0_PRETIME_OVER_8197F << BIT_SHIFT_BF0_PRETIME_OVER_8197F) +#define BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) \ + ((x) & (~BITS_BF0_PRETIME_OVER_8197F)) +#define BIT_GET_BF0_PRETIME_OVER_8197F(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8197F) & \ + BIT_MASK_BF0_PRETIME_OVER_8197F) +#define BIT_SET_BF0_PRETIME_OVER_8197F(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) | BIT_BF0_PRETIME_OVER_8197F(v)) #define BIT_SHIFT_BF0_LIFETIME_8197F 0 #define BIT_MASK_BF0_LIFETIME_8197F 0xffff -#define BIT_BF0_LIFETIME_8197F(x) (((x) & BIT_MASK_BF0_LIFETIME_8197F) << BIT_SHIFT_BF0_LIFETIME_8197F) -#define BITS_BF0_LIFETIME_8197F (BIT_MASK_BF0_LIFETIME_8197F << BIT_SHIFT_BF0_LIFETIME_8197F) +#define BIT_BF0_LIFETIME_8197F(x) \ + (((x) & BIT_MASK_BF0_LIFETIME_8197F) << BIT_SHIFT_BF0_LIFETIME_8197F) +#define BITS_BF0_LIFETIME_8197F \ + (BIT_MASK_BF0_LIFETIME_8197F << BIT_SHIFT_BF0_LIFETIME_8197F) #define BIT_CLEAR_BF0_LIFETIME_8197F(x) ((x) & (~BITS_BF0_LIFETIME_8197F)) -#define BIT_GET_BF0_LIFETIME_8197F(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8197F) & BIT_MASK_BF0_LIFETIME_8197F) -#define BIT_SET_BF0_LIFETIME_8197F(x, v) (BIT_CLEAR_BF0_LIFETIME_8197F(x) | BIT_BF0_LIFETIME_8197F(v)) - +#define BIT_GET_BF0_LIFETIME_8197F(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME_8197F) & BIT_MASK_BF0_LIFETIME_8197F) +#define BIT_SET_BF0_LIFETIME_8197F(x, v) \ + (BIT_CLEAR_BF0_LIFETIME_8197F(x) | BIT_BF0_LIFETIME_8197F(v)) /* 2 REG_BF1_TIME_SETTING_8197F */ #define BIT_BF1_TIMER_SET_8197F BIT(31) @@ -7895,21 +10246,30 @@ #define BIT_SHIFT_BF1_PRETIME_OVER_8197F 16 #define BIT_MASK_BF1_PRETIME_OVER_8197F 0xfff -#define BIT_BF1_PRETIME_OVER_8197F(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8197F) << BIT_SHIFT_BF1_PRETIME_OVER_8197F) -#define BITS_BF1_PRETIME_OVER_8197F (BIT_MASK_BF1_PRETIME_OVER_8197F << BIT_SHIFT_BF1_PRETIME_OVER_8197F) -#define BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) ((x) & (~BITS_BF1_PRETIME_OVER_8197F)) -#define BIT_GET_BF1_PRETIME_OVER_8197F(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8197F) & BIT_MASK_BF1_PRETIME_OVER_8197F) -#define BIT_SET_BF1_PRETIME_OVER_8197F(x, v) (BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) | BIT_BF1_PRETIME_OVER_8197F(v)) - +#define BIT_BF1_PRETIME_OVER_8197F(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER_8197F) \ + << BIT_SHIFT_BF1_PRETIME_OVER_8197F) +#define BITS_BF1_PRETIME_OVER_8197F \ + (BIT_MASK_BF1_PRETIME_OVER_8197F << BIT_SHIFT_BF1_PRETIME_OVER_8197F) +#define BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) \ + ((x) & (~BITS_BF1_PRETIME_OVER_8197F)) +#define BIT_GET_BF1_PRETIME_OVER_8197F(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8197F) & \ + BIT_MASK_BF1_PRETIME_OVER_8197F) +#define BIT_SET_BF1_PRETIME_OVER_8197F(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) | BIT_BF1_PRETIME_OVER_8197F(v)) #define BIT_SHIFT_BF1_LIFETIME_8197F 0 #define BIT_MASK_BF1_LIFETIME_8197F 0xffff -#define BIT_BF1_LIFETIME_8197F(x) (((x) & BIT_MASK_BF1_LIFETIME_8197F) << BIT_SHIFT_BF1_LIFETIME_8197F) -#define BITS_BF1_LIFETIME_8197F (BIT_MASK_BF1_LIFETIME_8197F << BIT_SHIFT_BF1_LIFETIME_8197F) +#define BIT_BF1_LIFETIME_8197F(x) \ + (((x) & BIT_MASK_BF1_LIFETIME_8197F) << BIT_SHIFT_BF1_LIFETIME_8197F) +#define BITS_BF1_LIFETIME_8197F \ + (BIT_MASK_BF1_LIFETIME_8197F << BIT_SHIFT_BF1_LIFETIME_8197F) #define BIT_CLEAR_BF1_LIFETIME_8197F(x) ((x) & (~BITS_BF1_LIFETIME_8197F)) -#define BIT_GET_BF1_LIFETIME_8197F(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8197F) & BIT_MASK_BF1_LIFETIME_8197F) -#define BIT_SET_BF1_LIFETIME_8197F(x, v) (BIT_CLEAR_BF1_LIFETIME_8197F(x) | BIT_BF1_LIFETIME_8197F(v)) - +#define BIT_GET_BF1_LIFETIME_8197F(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME_8197F) & BIT_MASK_BF1_LIFETIME_8197F) +#define BIT_SET_BF1_LIFETIME_8197F(x, v) \ + (BIT_CLEAR_BF1_LIFETIME_8197F(x) | BIT_BF1_LIFETIME_8197F(v)) /* 2 REG_BF_TIMEOUT_EN_8197F */ #define BIT_EN_VHT_LDPC_8197F BIT(9) @@ -7921,264 +10281,434 @@ #define BIT_SHIFT_MACID31_0_RELEASE_8197F 0 #define BIT_MASK_MACID31_0_RELEASE_8197F 0xffffffffL -#define BIT_MACID31_0_RELEASE_8197F(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8197F) << BIT_SHIFT_MACID31_0_RELEASE_8197F) -#define BITS_MACID31_0_RELEASE_8197F (BIT_MASK_MACID31_0_RELEASE_8197F << BIT_SHIFT_MACID31_0_RELEASE_8197F) -#define BIT_CLEAR_MACID31_0_RELEASE_8197F(x) ((x) & (~BITS_MACID31_0_RELEASE_8197F)) -#define BIT_GET_MACID31_0_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8197F) & BIT_MASK_MACID31_0_RELEASE_8197F) -#define BIT_SET_MACID31_0_RELEASE_8197F(x, v) (BIT_CLEAR_MACID31_0_RELEASE_8197F(x) | BIT_MACID31_0_RELEASE_8197F(v)) - +#define BIT_MACID31_0_RELEASE_8197F(x) \ + (((x) & BIT_MASK_MACID31_0_RELEASE_8197F) \ + << BIT_SHIFT_MACID31_0_RELEASE_8197F) +#define BITS_MACID31_0_RELEASE_8197F \ + (BIT_MASK_MACID31_0_RELEASE_8197F << BIT_SHIFT_MACID31_0_RELEASE_8197F) +#define BIT_CLEAR_MACID31_0_RELEASE_8197F(x) \ + ((x) & (~BITS_MACID31_0_RELEASE_8197F)) +#define BIT_GET_MACID31_0_RELEASE_8197F(x) \ + (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8197F) & \ + BIT_MASK_MACID31_0_RELEASE_8197F) +#define BIT_SET_MACID31_0_RELEASE_8197F(x, v) \ + (BIT_CLEAR_MACID31_0_RELEASE_8197F(x) | BIT_MACID31_0_RELEASE_8197F(v)) /* 2 REG_MACID_RELEASE1_8197F */ #define BIT_SHIFT_MACID63_32_RELEASE_8197F 0 #define BIT_MASK_MACID63_32_RELEASE_8197F 0xffffffffL -#define BIT_MACID63_32_RELEASE_8197F(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8197F) << BIT_SHIFT_MACID63_32_RELEASE_8197F) -#define BITS_MACID63_32_RELEASE_8197F (BIT_MASK_MACID63_32_RELEASE_8197F << BIT_SHIFT_MACID63_32_RELEASE_8197F) -#define BIT_CLEAR_MACID63_32_RELEASE_8197F(x) ((x) & (~BITS_MACID63_32_RELEASE_8197F)) -#define BIT_GET_MACID63_32_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8197F) & BIT_MASK_MACID63_32_RELEASE_8197F) -#define BIT_SET_MACID63_32_RELEASE_8197F(x, v) (BIT_CLEAR_MACID63_32_RELEASE_8197F(x) | BIT_MACID63_32_RELEASE_8197F(v)) - +#define BIT_MACID63_32_RELEASE_8197F(x) \ + (((x) & BIT_MASK_MACID63_32_RELEASE_8197F) \ + << BIT_SHIFT_MACID63_32_RELEASE_8197F) +#define BITS_MACID63_32_RELEASE_8197F \ + (BIT_MASK_MACID63_32_RELEASE_8197F \ + << BIT_SHIFT_MACID63_32_RELEASE_8197F) +#define BIT_CLEAR_MACID63_32_RELEASE_8197F(x) \ + ((x) & (~BITS_MACID63_32_RELEASE_8197F)) +#define BIT_GET_MACID63_32_RELEASE_8197F(x) \ + (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8197F) & \ + BIT_MASK_MACID63_32_RELEASE_8197F) +#define BIT_SET_MACID63_32_RELEASE_8197F(x, v) \ + (BIT_CLEAR_MACID63_32_RELEASE_8197F(x) | \ + BIT_MACID63_32_RELEASE_8197F(v)) /* 2 REG_MACID_RELEASE2_8197F */ #define BIT_SHIFT_MACID95_64_RELEASE_8197F 0 #define BIT_MASK_MACID95_64_RELEASE_8197F 0xffffffffL -#define BIT_MACID95_64_RELEASE_8197F(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8197F) << BIT_SHIFT_MACID95_64_RELEASE_8197F) -#define BITS_MACID95_64_RELEASE_8197F (BIT_MASK_MACID95_64_RELEASE_8197F << BIT_SHIFT_MACID95_64_RELEASE_8197F) -#define BIT_CLEAR_MACID95_64_RELEASE_8197F(x) ((x) & (~BITS_MACID95_64_RELEASE_8197F)) -#define BIT_GET_MACID95_64_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8197F) & BIT_MASK_MACID95_64_RELEASE_8197F) -#define BIT_SET_MACID95_64_RELEASE_8197F(x, v) (BIT_CLEAR_MACID95_64_RELEASE_8197F(x) | BIT_MACID95_64_RELEASE_8197F(v)) - +#define BIT_MACID95_64_RELEASE_8197F(x) \ + (((x) & BIT_MASK_MACID95_64_RELEASE_8197F) \ + << BIT_SHIFT_MACID95_64_RELEASE_8197F) +#define BITS_MACID95_64_RELEASE_8197F \ + (BIT_MASK_MACID95_64_RELEASE_8197F \ + << BIT_SHIFT_MACID95_64_RELEASE_8197F) +#define BIT_CLEAR_MACID95_64_RELEASE_8197F(x) \ + ((x) & (~BITS_MACID95_64_RELEASE_8197F)) +#define BIT_GET_MACID95_64_RELEASE_8197F(x) \ + (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8197F) & \ + BIT_MASK_MACID95_64_RELEASE_8197F) +#define BIT_SET_MACID95_64_RELEASE_8197F(x, v) \ + (BIT_CLEAR_MACID95_64_RELEASE_8197F(x) | \ + BIT_MACID95_64_RELEASE_8197F(v)) /* 2 REG_MACID_RELEASE3_8197F */ #define BIT_SHIFT_MACID127_96_RELEASE_8197F 0 #define BIT_MASK_MACID127_96_RELEASE_8197F 0xffffffffL -#define BIT_MACID127_96_RELEASE_8197F(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8197F) << BIT_SHIFT_MACID127_96_RELEASE_8197F) -#define BITS_MACID127_96_RELEASE_8197F (BIT_MASK_MACID127_96_RELEASE_8197F << BIT_SHIFT_MACID127_96_RELEASE_8197F) -#define BIT_CLEAR_MACID127_96_RELEASE_8197F(x) ((x) & (~BITS_MACID127_96_RELEASE_8197F)) -#define BIT_GET_MACID127_96_RELEASE_8197F(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8197F) & BIT_MASK_MACID127_96_RELEASE_8197F) -#define BIT_SET_MACID127_96_RELEASE_8197F(x, v) (BIT_CLEAR_MACID127_96_RELEASE_8197F(x) | BIT_MACID127_96_RELEASE_8197F(v)) - +#define BIT_MACID127_96_RELEASE_8197F(x) \ + (((x) & BIT_MASK_MACID127_96_RELEASE_8197F) \ + << BIT_SHIFT_MACID127_96_RELEASE_8197F) +#define BITS_MACID127_96_RELEASE_8197F \ + (BIT_MASK_MACID127_96_RELEASE_8197F \ + << BIT_SHIFT_MACID127_96_RELEASE_8197F) +#define BIT_CLEAR_MACID127_96_RELEASE_8197F(x) \ + ((x) & (~BITS_MACID127_96_RELEASE_8197F)) +#define BIT_GET_MACID127_96_RELEASE_8197F(x) \ + (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8197F) & \ + BIT_MASK_MACID127_96_RELEASE_8197F) +#define BIT_SET_MACID127_96_RELEASE_8197F(x, v) \ + (BIT_CLEAR_MACID127_96_RELEASE_8197F(x) | \ + BIT_MACID127_96_RELEASE_8197F(v)) /* 2 REG_MACID_RELEASE_SETTING_8197F */ #define BIT_MACID_VALUE_8197F BIT(7) #define BIT_SHIFT_MACID_OFFSET_8197F 0 #define BIT_MASK_MACID_OFFSET_8197F 0x7f -#define BIT_MACID_OFFSET_8197F(x) (((x) & BIT_MASK_MACID_OFFSET_8197F) << BIT_SHIFT_MACID_OFFSET_8197F) -#define BITS_MACID_OFFSET_8197F (BIT_MASK_MACID_OFFSET_8197F << BIT_SHIFT_MACID_OFFSET_8197F) +#define BIT_MACID_OFFSET_8197F(x) \ + (((x) & BIT_MASK_MACID_OFFSET_8197F) << BIT_SHIFT_MACID_OFFSET_8197F) +#define BITS_MACID_OFFSET_8197F \ + (BIT_MASK_MACID_OFFSET_8197F << BIT_SHIFT_MACID_OFFSET_8197F) #define BIT_CLEAR_MACID_OFFSET_8197F(x) ((x) & (~BITS_MACID_OFFSET_8197F)) -#define BIT_GET_MACID_OFFSET_8197F(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8197F) & BIT_MASK_MACID_OFFSET_8197F) -#define BIT_SET_MACID_OFFSET_8197F(x, v) (BIT_CLEAR_MACID_OFFSET_8197F(x) | BIT_MACID_OFFSET_8197F(v)) - +#define BIT_GET_MACID_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_MACID_OFFSET_8197F) & BIT_MASK_MACID_OFFSET_8197F) +#define BIT_SET_MACID_OFFSET_8197F(x, v) \ + (BIT_CLEAR_MACID_OFFSET_8197F(x) | BIT_MACID_OFFSET_8197F(v)) /* 2 REG_FAST_EDCA_VOVI_SETTING_8197F */ #define BIT_SHIFT_VI_FAST_EDCA_TO_8197F 24 #define BIT_MASK_VI_FAST_EDCA_TO_8197F 0xff -#define BIT_VI_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8197F) << BIT_SHIFT_VI_FAST_EDCA_TO_8197F) -#define BITS_VI_FAST_EDCA_TO_8197F (BIT_MASK_VI_FAST_EDCA_TO_8197F << BIT_SHIFT_VI_FAST_EDCA_TO_8197F) +#define BIT_VI_FAST_EDCA_TO_8197F(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO_8197F) \ + << BIT_SHIFT_VI_FAST_EDCA_TO_8197F) +#define BITS_VI_FAST_EDCA_TO_8197F \ + (BIT_MASK_VI_FAST_EDCA_TO_8197F << BIT_SHIFT_VI_FAST_EDCA_TO_8197F) #define BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8197F)) -#define BIT_GET_VI_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8197F) & BIT_MASK_VI_FAST_EDCA_TO_8197F) -#define BIT_SET_VI_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) | BIT_VI_FAST_EDCA_TO_8197F(v)) +#define BIT_GET_VI_FAST_EDCA_TO_8197F(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8197F) & \ + BIT_MASK_VI_FAST_EDCA_TO_8197F) +#define BIT_SET_VI_FAST_EDCA_TO_8197F(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) | BIT_VI_FAST_EDCA_TO_8197F(v)) #define BIT_VI_THRESHOLD_SEL_8197F BIT(23) #define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F 16 #define BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F 0x7f -#define BIT_VI_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) -#define BITS_VI_FAST_EDCA_PKT_TH_8197F (BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) -#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8197F)) -#define BIT_GET_VI_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F) -#define BIT_SET_VI_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) | BIT_VI_FAST_EDCA_PKT_TH_8197F(v)) - +#define BIT_VI_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F) \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) +#define BITS_VI_FAST_EDCA_PKT_TH_8197F \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) \ + ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) & \ + BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_VI_FAST_EDCA_PKT_TH_8197F(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) | \ + BIT_VI_FAST_EDCA_PKT_TH_8197F(v)) #define BIT_SHIFT_VO_FAST_EDCA_TO_8197F 8 #define BIT_MASK_VO_FAST_EDCA_TO_8197F 0xff -#define BIT_VO_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8197F) << BIT_SHIFT_VO_FAST_EDCA_TO_8197F) -#define BITS_VO_FAST_EDCA_TO_8197F (BIT_MASK_VO_FAST_EDCA_TO_8197F << BIT_SHIFT_VO_FAST_EDCA_TO_8197F) +#define BIT_VO_FAST_EDCA_TO_8197F(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO_8197F) \ + << BIT_SHIFT_VO_FAST_EDCA_TO_8197F) +#define BITS_VO_FAST_EDCA_TO_8197F \ + (BIT_MASK_VO_FAST_EDCA_TO_8197F << BIT_SHIFT_VO_FAST_EDCA_TO_8197F) #define BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8197F)) -#define BIT_GET_VO_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8197F) & BIT_MASK_VO_FAST_EDCA_TO_8197F) -#define BIT_SET_VO_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) | BIT_VO_FAST_EDCA_TO_8197F(v)) +#define BIT_GET_VO_FAST_EDCA_TO_8197F(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8197F) & \ + BIT_MASK_VO_FAST_EDCA_TO_8197F) +#define BIT_SET_VO_FAST_EDCA_TO_8197F(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) | BIT_VO_FAST_EDCA_TO_8197F(v)) #define BIT_VO_THRESHOLD_SEL_8197F BIT(7) #define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F 0 #define BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F 0x7f -#define BIT_VO_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) -#define BITS_VO_FAST_EDCA_PKT_TH_8197F (BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) -#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8197F)) -#define BIT_GET_VO_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F) -#define BIT_SET_VO_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) | BIT_VO_FAST_EDCA_PKT_TH_8197F(v)) - +#define BIT_VO_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F) \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) +#define BITS_VO_FAST_EDCA_PKT_TH_8197F \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) \ + ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) & \ + BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_VO_FAST_EDCA_PKT_TH_8197F(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) | \ + BIT_VO_FAST_EDCA_PKT_TH_8197F(v)) /* 2 REG_FAST_EDCA_BEBK_SETTING_8197F */ #define BIT_SHIFT_BK_FAST_EDCA_TO_8197F 24 #define BIT_MASK_BK_FAST_EDCA_TO_8197F 0xff -#define BIT_BK_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8197F) << BIT_SHIFT_BK_FAST_EDCA_TO_8197F) -#define BITS_BK_FAST_EDCA_TO_8197F (BIT_MASK_BK_FAST_EDCA_TO_8197F << BIT_SHIFT_BK_FAST_EDCA_TO_8197F) +#define BIT_BK_FAST_EDCA_TO_8197F(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO_8197F) \ + << BIT_SHIFT_BK_FAST_EDCA_TO_8197F) +#define BITS_BK_FAST_EDCA_TO_8197F \ + (BIT_MASK_BK_FAST_EDCA_TO_8197F << BIT_SHIFT_BK_FAST_EDCA_TO_8197F) #define BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8197F)) -#define BIT_GET_BK_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8197F) & BIT_MASK_BK_FAST_EDCA_TO_8197F) -#define BIT_SET_BK_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) | BIT_BK_FAST_EDCA_TO_8197F(v)) +#define BIT_GET_BK_FAST_EDCA_TO_8197F(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8197F) & \ + BIT_MASK_BK_FAST_EDCA_TO_8197F) +#define BIT_SET_BK_FAST_EDCA_TO_8197F(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) | BIT_BK_FAST_EDCA_TO_8197F(v)) #define BIT_BK_THRESHOLD_SEL_8197F BIT(23) #define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F 16 #define BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F 0x7f -#define BIT_BK_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) -#define BITS_BK_FAST_EDCA_PKT_TH_8197F (BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) -#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8197F)) -#define BIT_GET_BK_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F) -#define BIT_SET_BK_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) | BIT_BK_FAST_EDCA_PKT_TH_8197F(v)) - +#define BIT_BK_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F) \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) +#define BITS_BK_FAST_EDCA_PKT_TH_8197F \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) \ + ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) & \ + BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_BK_FAST_EDCA_PKT_TH_8197F(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) | \ + BIT_BK_FAST_EDCA_PKT_TH_8197F(v)) #define BIT_SHIFT_BE_FAST_EDCA_TO_8197F 8 #define BIT_MASK_BE_FAST_EDCA_TO_8197F 0xff -#define BIT_BE_FAST_EDCA_TO_8197F(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8197F) << BIT_SHIFT_BE_FAST_EDCA_TO_8197F) -#define BITS_BE_FAST_EDCA_TO_8197F (BIT_MASK_BE_FAST_EDCA_TO_8197F << BIT_SHIFT_BE_FAST_EDCA_TO_8197F) +#define BIT_BE_FAST_EDCA_TO_8197F(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO_8197F) \ + << BIT_SHIFT_BE_FAST_EDCA_TO_8197F) +#define BITS_BE_FAST_EDCA_TO_8197F \ + (BIT_MASK_BE_FAST_EDCA_TO_8197F << BIT_SHIFT_BE_FAST_EDCA_TO_8197F) #define BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8197F)) -#define BIT_GET_BE_FAST_EDCA_TO_8197F(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8197F) & BIT_MASK_BE_FAST_EDCA_TO_8197F) -#define BIT_SET_BE_FAST_EDCA_TO_8197F(x, v) (BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) | BIT_BE_FAST_EDCA_TO_8197F(v)) +#define BIT_GET_BE_FAST_EDCA_TO_8197F(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8197F) & \ + BIT_MASK_BE_FAST_EDCA_TO_8197F) +#define BIT_SET_BE_FAST_EDCA_TO_8197F(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) | BIT_BE_FAST_EDCA_TO_8197F(v)) #define BIT_BE_THRESHOLD_SEL_8197F BIT(7) #define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F 0 #define BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F 0x7f -#define BIT_BE_FAST_EDCA_PKT_TH_8197F(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) -#define BITS_BE_FAST_EDCA_PKT_TH_8197F (BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) -#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8197F)) -#define BIT_GET_BE_FAST_EDCA_PKT_TH_8197F(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F) -#define BIT_SET_BE_FAST_EDCA_PKT_TH_8197F(x, v) (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) | BIT_BE_FAST_EDCA_PKT_TH_8197F(v)) - +#define BIT_BE_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F) \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) +#define BITS_BE_FAST_EDCA_PKT_TH_8197F \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) \ + ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8197F)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8197F(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) & \ + BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F) +#define BIT_SET_BE_FAST_EDCA_PKT_TH_8197F(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) | \ + BIT_BE_FAST_EDCA_PKT_TH_8197F(v)) /* 2 REG_MACID_DROP0_8197F */ #define BIT_SHIFT_MACID31_0_DROP_8197F 0 #define BIT_MASK_MACID31_0_DROP_8197F 0xffffffffL -#define BIT_MACID31_0_DROP_8197F(x) (((x) & BIT_MASK_MACID31_0_DROP_8197F) << BIT_SHIFT_MACID31_0_DROP_8197F) -#define BITS_MACID31_0_DROP_8197F (BIT_MASK_MACID31_0_DROP_8197F << BIT_SHIFT_MACID31_0_DROP_8197F) +#define BIT_MACID31_0_DROP_8197F(x) \ + (((x) & BIT_MASK_MACID31_0_DROP_8197F) \ + << BIT_SHIFT_MACID31_0_DROP_8197F) +#define BITS_MACID31_0_DROP_8197F \ + (BIT_MASK_MACID31_0_DROP_8197F << BIT_SHIFT_MACID31_0_DROP_8197F) #define BIT_CLEAR_MACID31_0_DROP_8197F(x) ((x) & (~BITS_MACID31_0_DROP_8197F)) -#define BIT_GET_MACID31_0_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8197F) & BIT_MASK_MACID31_0_DROP_8197F) -#define BIT_SET_MACID31_0_DROP_8197F(x, v) (BIT_CLEAR_MACID31_0_DROP_8197F(x) | BIT_MACID31_0_DROP_8197F(v)) - +#define BIT_GET_MACID31_0_DROP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID31_0_DROP_8197F) & \ + BIT_MASK_MACID31_0_DROP_8197F) +#define BIT_SET_MACID31_0_DROP_8197F(x, v) \ + (BIT_CLEAR_MACID31_0_DROP_8197F(x) | BIT_MACID31_0_DROP_8197F(v)) /* 2 REG_MACID_DROP1_8197F */ #define BIT_SHIFT_MACID63_32_DROP_8197F 0 #define BIT_MASK_MACID63_32_DROP_8197F 0xffffffffL -#define BIT_MACID63_32_DROP_8197F(x) (((x) & BIT_MASK_MACID63_32_DROP_8197F) << BIT_SHIFT_MACID63_32_DROP_8197F) -#define BITS_MACID63_32_DROP_8197F (BIT_MASK_MACID63_32_DROP_8197F << BIT_SHIFT_MACID63_32_DROP_8197F) +#define BIT_MACID63_32_DROP_8197F(x) \ + (((x) & BIT_MASK_MACID63_32_DROP_8197F) \ + << BIT_SHIFT_MACID63_32_DROP_8197F) +#define BITS_MACID63_32_DROP_8197F \ + (BIT_MASK_MACID63_32_DROP_8197F << BIT_SHIFT_MACID63_32_DROP_8197F) #define BIT_CLEAR_MACID63_32_DROP_8197F(x) ((x) & (~BITS_MACID63_32_DROP_8197F)) -#define BIT_GET_MACID63_32_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8197F) & BIT_MASK_MACID63_32_DROP_8197F) -#define BIT_SET_MACID63_32_DROP_8197F(x, v) (BIT_CLEAR_MACID63_32_DROP_8197F(x) | BIT_MACID63_32_DROP_8197F(v)) - +#define BIT_GET_MACID63_32_DROP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID63_32_DROP_8197F) & \ + BIT_MASK_MACID63_32_DROP_8197F) +#define BIT_SET_MACID63_32_DROP_8197F(x, v) \ + (BIT_CLEAR_MACID63_32_DROP_8197F(x) | BIT_MACID63_32_DROP_8197F(v)) /* 2 REG_MACID_DROP2_8197F */ #define BIT_SHIFT_MACID95_64_DROP_8197F 0 #define BIT_MASK_MACID95_64_DROP_8197F 0xffffffffL -#define BIT_MACID95_64_DROP_8197F(x) (((x) & BIT_MASK_MACID95_64_DROP_8197F) << BIT_SHIFT_MACID95_64_DROP_8197F) -#define BITS_MACID95_64_DROP_8197F (BIT_MASK_MACID95_64_DROP_8197F << BIT_SHIFT_MACID95_64_DROP_8197F) +#define BIT_MACID95_64_DROP_8197F(x) \ + (((x) & BIT_MASK_MACID95_64_DROP_8197F) \ + << BIT_SHIFT_MACID95_64_DROP_8197F) +#define BITS_MACID95_64_DROP_8197F \ + (BIT_MASK_MACID95_64_DROP_8197F << BIT_SHIFT_MACID95_64_DROP_8197F) #define BIT_CLEAR_MACID95_64_DROP_8197F(x) ((x) & (~BITS_MACID95_64_DROP_8197F)) -#define BIT_GET_MACID95_64_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8197F) & BIT_MASK_MACID95_64_DROP_8197F) -#define BIT_SET_MACID95_64_DROP_8197F(x, v) (BIT_CLEAR_MACID95_64_DROP_8197F(x) | BIT_MACID95_64_DROP_8197F(v)) - +#define BIT_GET_MACID95_64_DROP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID95_64_DROP_8197F) & \ + BIT_MASK_MACID95_64_DROP_8197F) +#define BIT_SET_MACID95_64_DROP_8197F(x, v) \ + (BIT_CLEAR_MACID95_64_DROP_8197F(x) | BIT_MACID95_64_DROP_8197F(v)) /* 2 REG_MACID_DROP3_8197F */ #define BIT_SHIFT_MACID127_96_DROP_8197F 0 #define BIT_MASK_MACID127_96_DROP_8197F 0xffffffffL -#define BIT_MACID127_96_DROP_8197F(x) (((x) & BIT_MASK_MACID127_96_DROP_8197F) << BIT_SHIFT_MACID127_96_DROP_8197F) -#define BITS_MACID127_96_DROP_8197F (BIT_MASK_MACID127_96_DROP_8197F << BIT_SHIFT_MACID127_96_DROP_8197F) -#define BIT_CLEAR_MACID127_96_DROP_8197F(x) ((x) & (~BITS_MACID127_96_DROP_8197F)) -#define BIT_GET_MACID127_96_DROP_8197F(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8197F) & BIT_MASK_MACID127_96_DROP_8197F) -#define BIT_SET_MACID127_96_DROP_8197F(x, v) (BIT_CLEAR_MACID127_96_DROP_8197F(x) | BIT_MACID127_96_DROP_8197F(v)) - +#define BIT_MACID127_96_DROP_8197F(x) \ + (((x) & BIT_MASK_MACID127_96_DROP_8197F) \ + << BIT_SHIFT_MACID127_96_DROP_8197F) +#define BITS_MACID127_96_DROP_8197F \ + (BIT_MASK_MACID127_96_DROP_8197F << BIT_SHIFT_MACID127_96_DROP_8197F) +#define BIT_CLEAR_MACID127_96_DROP_8197F(x) \ + ((x) & (~BITS_MACID127_96_DROP_8197F)) +#define BIT_GET_MACID127_96_DROP_8197F(x) \ + (((x) >> BIT_SHIFT_MACID127_96_DROP_8197F) & \ + BIT_MASK_MACID127_96_DROP_8197F) +#define BIT_SET_MACID127_96_DROP_8197F(x, v) \ + (BIT_CLEAR_MACID127_96_DROP_8197F(x) | BIT_MACID127_96_DROP_8197F(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_0_8197F */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_0_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) -#define BITS_R_MACID_RELEASE_SUCCESS_0_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) -#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8197F)) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F) -#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_0_8197F(v)) - +#define BIT_R_MACID_RELEASE_SUCCESS_0_8197F(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_0_8197F \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8197F(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8197F(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_0_8197F(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_1_8197F */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_1_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) -#define BITS_R_MACID_RELEASE_SUCCESS_1_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) -#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8197F)) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F) -#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_1_8197F(v)) - +#define BIT_R_MACID_RELEASE_SUCCESS_1_8197F(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_1_8197F \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8197F(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8197F(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_1_8197F(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_2_8197F */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_2_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) -#define BITS_R_MACID_RELEASE_SUCCESS_2_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) -#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8197F)) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F) -#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_2_8197F(v)) - +#define BIT_R_MACID_RELEASE_SUCCESS_2_8197F(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_2_8197F \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8197F(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8197F(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_2_8197F(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_3_8197F */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_3_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) -#define BITS_R_MACID_RELEASE_SUCCESS_3_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) -#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8197F)) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F) -#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_3_8197F(v)) - +#define BIT_R_MACID_RELEASE_SUCCESS_3_8197F(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_3_8197F \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8197F(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8197F(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_3_8197F(v)) /* 2 REG_MGG_FIFO_CRTL_8197F */ #define BIT_R_MGG_FIFO_EN_8197F BIT(31) #define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F 28 #define BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F 0x7 -#define BIT_R_MGG_FIFO_PG_SIZE_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) -#define BITS_R_MGG_FIFO_PG_SIZE_8197F (BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) -#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) ((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8197F)) -#define BIT_GET_R_MGG_FIFO_PG_SIZE_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F) -#define BIT_SET_R_MGG_FIFO_PG_SIZE_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) | BIT_R_MGG_FIFO_PG_SIZE_8197F(v)) - +#define BIT_R_MGG_FIFO_PG_SIZE_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) +#define BITS_R_MGG_FIFO_PG_SIZE_8197F \ + (BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F \ + << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) +#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8197F)) +#define BIT_GET_R_MGG_FIFO_PG_SIZE_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) & \ + BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F) +#define BIT_SET_R_MGG_FIFO_PG_SIZE_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) | \ + BIT_R_MGG_FIFO_PG_SIZE_8197F(v)) #define BIT_SHIFT_R_MGG_FIFO_START_PG_8197F 16 #define BIT_MASK_R_MGG_FIFO_START_PG_8197F 0xfff -#define BIT_R_MGG_FIFO_START_PG_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8197F) << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) -#define BITS_R_MGG_FIFO_START_PG_8197F (BIT_MASK_R_MGG_FIFO_START_PG_8197F << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) -#define BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) ((x) & (~BITS_R_MGG_FIFO_START_PG_8197F)) -#define BIT_GET_R_MGG_FIFO_START_PG_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) & BIT_MASK_R_MGG_FIFO_START_PG_8197F) -#define BIT_SET_R_MGG_FIFO_START_PG_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) | BIT_R_MGG_FIFO_START_PG_8197F(v)) - +#define BIT_R_MGG_FIFO_START_PG_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) +#define BITS_R_MGG_FIFO_START_PG_8197F \ + (BIT_MASK_R_MGG_FIFO_START_PG_8197F \ + << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) +#define BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_START_PG_8197F)) +#define BIT_GET_R_MGG_FIFO_START_PG_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) & \ + BIT_MASK_R_MGG_FIFO_START_PG_8197F) +#define BIT_SET_R_MGG_FIFO_START_PG_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) | \ + BIT_R_MGG_FIFO_START_PG_8197F(v)) #define BIT_SHIFT_R_MGG_FIFO_SIZE_8197F 14 #define BIT_MASK_R_MGG_FIFO_SIZE_8197F 0x3 -#define BIT_R_MGG_FIFO_SIZE_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8197F) << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) -#define BITS_R_MGG_FIFO_SIZE_8197F (BIT_MASK_R_MGG_FIFO_SIZE_8197F << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) +#define BIT_R_MGG_FIFO_SIZE_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) +#define BITS_R_MGG_FIFO_SIZE_8197F \ + (BIT_MASK_R_MGG_FIFO_SIZE_8197F << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) #define BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) ((x) & (~BITS_R_MGG_FIFO_SIZE_8197F)) -#define BIT_GET_R_MGG_FIFO_SIZE_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) & BIT_MASK_R_MGG_FIFO_SIZE_8197F) -#define BIT_SET_R_MGG_FIFO_SIZE_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) | BIT_R_MGG_FIFO_SIZE_8197F(v)) +#define BIT_GET_R_MGG_FIFO_SIZE_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) & \ + BIT_MASK_R_MGG_FIFO_SIZE_8197F) +#define BIT_SET_R_MGG_FIFO_SIZE_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) | BIT_R_MGG_FIFO_SIZE_8197F(v)) #define BIT_R_MGG_FIFO_PAUSE_8197F BIT(13) #define BIT_SHIFT_R_MGG_FIFO_RPTR_8197F 8 #define BIT_MASK_R_MGG_FIFO_RPTR_8197F 0x1f -#define BIT_R_MGG_FIFO_RPTR_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8197F) << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) -#define BITS_R_MGG_FIFO_RPTR_8197F (BIT_MASK_R_MGG_FIFO_RPTR_8197F << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) +#define BIT_R_MGG_FIFO_RPTR_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) +#define BITS_R_MGG_FIFO_RPTR_8197F \ + (BIT_MASK_R_MGG_FIFO_RPTR_8197F << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) #define BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_RPTR_8197F)) -#define BIT_GET_R_MGG_FIFO_RPTR_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) & BIT_MASK_R_MGG_FIFO_RPTR_8197F) -#define BIT_SET_R_MGG_FIFO_RPTR_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) | BIT_R_MGG_FIFO_RPTR_8197F(v)) +#define BIT_GET_R_MGG_FIFO_RPTR_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) & \ + BIT_MASK_R_MGG_FIFO_RPTR_8197F) +#define BIT_SET_R_MGG_FIFO_RPTR_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) | BIT_R_MGG_FIFO_RPTR_8197F(v)) #define BIT_R_MGG_FIFO_OV_8197F BIT(7) #define BIT_R_MGG_FIFO_WPTR_ERROR_8197F BIT(6) @@ -8186,63 +10716,108 @@ #define BIT_SHIFT_R_MGG_FIFO_WPTR_8197F 0 #define BIT_MASK_R_MGG_FIFO_WPTR_8197F 0x1f -#define BIT_R_MGG_FIFO_WPTR_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8197F) << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) -#define BITS_R_MGG_FIFO_WPTR_8197F (BIT_MASK_R_MGG_FIFO_WPTR_8197F << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) +#define BIT_R_MGG_FIFO_WPTR_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) +#define BITS_R_MGG_FIFO_WPTR_8197F \ + (BIT_MASK_R_MGG_FIFO_WPTR_8197F << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) #define BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_WPTR_8197F)) -#define BIT_GET_R_MGG_FIFO_WPTR_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) & BIT_MASK_R_MGG_FIFO_WPTR_8197F) -#define BIT_SET_R_MGG_FIFO_WPTR_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) | BIT_R_MGG_FIFO_WPTR_8197F(v)) - +#define BIT_GET_R_MGG_FIFO_WPTR_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) & \ + BIT_MASK_R_MGG_FIFO_WPTR_8197F) +#define BIT_SET_R_MGG_FIFO_WPTR_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) | BIT_R_MGG_FIFO_WPTR_8197F(v)) /* 2 REG_MGG_FIFO_INT_8197F */ #define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F 16 #define BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F 0xffff -#define BIT_R_MGG_FIFO_INT_FLAG_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) -#define BITS_R_MGG_FIFO_INT_FLAG_8197F (BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) -#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) ((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8197F)) -#define BIT_GET_R_MGG_FIFO_INT_FLAG_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F) -#define BIT_SET_R_MGG_FIFO_INT_FLAG_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) | BIT_R_MGG_FIFO_INT_FLAG_8197F(v)) - +#define BIT_R_MGG_FIFO_INT_FLAG_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) +#define BITS_R_MGG_FIFO_INT_FLAG_8197F \ + (BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F \ + << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) +#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8197F)) +#define BIT_GET_R_MGG_FIFO_INT_FLAG_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) & \ + BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F) +#define BIT_SET_R_MGG_FIFO_INT_FLAG_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) | \ + BIT_R_MGG_FIFO_INT_FLAG_8197F(v)) #define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F 0 #define BIT_MASK_R_MGG_FIFO_INT_MASK_8197F 0xffff -#define BIT_R_MGG_FIFO_INT_MASK_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8197F) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) -#define BITS_R_MGG_FIFO_INT_MASK_8197F (BIT_MASK_R_MGG_FIFO_INT_MASK_8197F << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) -#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) ((x) & (~BITS_R_MGG_FIFO_INT_MASK_8197F)) -#define BIT_GET_R_MGG_FIFO_INT_MASK_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) & BIT_MASK_R_MGG_FIFO_INT_MASK_8197F) -#define BIT_SET_R_MGG_FIFO_INT_MASK_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) | BIT_R_MGG_FIFO_INT_MASK_8197F(v)) - +#define BIT_R_MGG_FIFO_INT_MASK_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) +#define BITS_R_MGG_FIFO_INT_MASK_8197F \ + (BIT_MASK_R_MGG_FIFO_INT_MASK_8197F \ + << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) +#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_INT_MASK_8197F)) +#define BIT_GET_R_MGG_FIFO_INT_MASK_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) & \ + BIT_MASK_R_MGG_FIFO_INT_MASK_8197F) +#define BIT_SET_R_MGG_FIFO_INT_MASK_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) | \ + BIT_R_MGG_FIFO_INT_MASK_8197F(v)) /* 2 REG_MGG_FIFO_LIFETIME_8197F */ #define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F 16 #define BIT_MASK_R_MGG_FIFO_LIFETIME_8197F 0xffff -#define BIT_R_MGG_FIFO_LIFETIME_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8197F) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) -#define BITS_R_MGG_FIFO_LIFETIME_8197F (BIT_MASK_R_MGG_FIFO_LIFETIME_8197F << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) -#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) ((x) & (~BITS_R_MGG_FIFO_LIFETIME_8197F)) -#define BIT_GET_R_MGG_FIFO_LIFETIME_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) & BIT_MASK_R_MGG_FIFO_LIFETIME_8197F) -#define BIT_SET_R_MGG_FIFO_LIFETIME_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) | BIT_R_MGG_FIFO_LIFETIME_8197F(v)) - +#define BIT_R_MGG_FIFO_LIFETIME_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) +#define BITS_R_MGG_FIFO_LIFETIME_8197F \ + (BIT_MASK_R_MGG_FIFO_LIFETIME_8197F \ + << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) +#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_LIFETIME_8197F)) +#define BIT_GET_R_MGG_FIFO_LIFETIME_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) & \ + BIT_MASK_R_MGG_FIFO_LIFETIME_8197F) +#define BIT_SET_R_MGG_FIFO_LIFETIME_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) | \ + BIT_R_MGG_FIFO_LIFETIME_8197F(v)) #define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F 0 #define BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F 0xffff -#define BIT_R_MGG_FIFO_VALID_MAP_8197F(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) -#define BITS_R_MGG_FIFO_VALID_MAP_8197F (BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) -#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) ((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8197F)) -#define BIT_GET_R_MGG_FIFO_VALID_MAP_8197F(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F) -#define BIT_SET_R_MGG_FIFO_VALID_MAP_8197F(x, v) (BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) | BIT_R_MGG_FIFO_VALID_MAP_8197F(v)) - +#define BIT_R_MGG_FIFO_VALID_MAP_8197F(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F) \ + << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) +#define BITS_R_MGG_FIFO_VALID_MAP_8197F \ + (BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F \ + << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) +#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) \ + ((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8197F)) +#define BIT_GET_R_MGG_FIFO_VALID_MAP_8197F(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) & \ + BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F) +#define BIT_SET_R_MGG_FIFO_VALID_MAP_8197F(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) | \ + BIT_R_MGG_FIFO_VALID_MAP_8197F(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x7f -#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) -#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) -#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) -#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x, v) (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) | BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(v)) - +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) +#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(v)) /* 2 REG_SHCUT_SETTING_8197F */ @@ -8302,7 +10877,7 @@ /* 2 REG_NOT_VALID_8197F */ -/* 2 REG_NOT_VALID_8197F */ +/* 2 REG_CHNL_INFO_CTRL_8197F */ #define BIT_CHNL_REF_RXNAV_8197F BIT(7) #define BIT_CHNL_REF_VBON_8197F BIT(6) #define BIT_CHNL_REF_EDCCA_8197F BIT(5) @@ -8311,27 +10886,37 @@ #define BIT_CHNL_INFO_RST_8197F BIT(1) #define BIT_ATM_AIRTIME_EN_8197F BIT(0) -/* 2 REG_NOT_VALID_8197F */ +/* 2 REG_CHNL_IDLE_TIME_8197F */ #define BIT_SHIFT_CHNL_IDLE_TIME_8197F 0 #define BIT_MASK_CHNL_IDLE_TIME_8197F 0xffffffffL -#define BIT_CHNL_IDLE_TIME_8197F(x) (((x) & BIT_MASK_CHNL_IDLE_TIME_8197F) << BIT_SHIFT_CHNL_IDLE_TIME_8197F) -#define BITS_CHNL_IDLE_TIME_8197F (BIT_MASK_CHNL_IDLE_TIME_8197F << BIT_SHIFT_CHNL_IDLE_TIME_8197F) +#define BIT_CHNL_IDLE_TIME_8197F(x) \ + (((x) & BIT_MASK_CHNL_IDLE_TIME_8197F) \ + << BIT_SHIFT_CHNL_IDLE_TIME_8197F) +#define BITS_CHNL_IDLE_TIME_8197F \ + (BIT_MASK_CHNL_IDLE_TIME_8197F << BIT_SHIFT_CHNL_IDLE_TIME_8197F) #define BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) ((x) & (~BITS_CHNL_IDLE_TIME_8197F)) -#define BIT_GET_CHNL_IDLE_TIME_8197F(x) (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8197F) & BIT_MASK_CHNL_IDLE_TIME_8197F) -#define BIT_SET_CHNL_IDLE_TIME_8197F(x, v) (BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) | BIT_CHNL_IDLE_TIME_8197F(v)) - +#define BIT_GET_CHNL_IDLE_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8197F) & \ + BIT_MASK_CHNL_IDLE_TIME_8197F) +#define BIT_SET_CHNL_IDLE_TIME_8197F(x, v) \ + (BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) | BIT_CHNL_IDLE_TIME_8197F(v)) -/* 2 REG_NOT_VALID_8197F */ +/* 2 REG_CHNL_BUSY_TIME_8197F */ #define BIT_SHIFT_CHNL_BUSY_TIME_8197F 0 #define BIT_MASK_CHNL_BUSY_TIME_8197F 0xffffffffL -#define BIT_CHNL_BUSY_TIME_8197F(x) (((x) & BIT_MASK_CHNL_BUSY_TIME_8197F) << BIT_SHIFT_CHNL_BUSY_TIME_8197F) -#define BITS_CHNL_BUSY_TIME_8197F (BIT_MASK_CHNL_BUSY_TIME_8197F << BIT_SHIFT_CHNL_BUSY_TIME_8197F) +#define BIT_CHNL_BUSY_TIME_8197F(x) \ + (((x) & BIT_MASK_CHNL_BUSY_TIME_8197F) \ + << BIT_SHIFT_CHNL_BUSY_TIME_8197F) +#define BITS_CHNL_BUSY_TIME_8197F \ + (BIT_MASK_CHNL_BUSY_TIME_8197F << BIT_SHIFT_CHNL_BUSY_TIME_8197F) #define BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) ((x) & (~BITS_CHNL_BUSY_TIME_8197F)) -#define BIT_GET_CHNL_BUSY_TIME_8197F(x) (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8197F) & BIT_MASK_CHNL_BUSY_TIME_8197F) -#define BIT_SET_CHNL_BUSY_TIME_8197F(x, v) (BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) | BIT_CHNL_BUSY_TIME_8197F(v)) - +#define BIT_GET_CHNL_BUSY_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8197F) & \ + BIT_MASK_CHNL_BUSY_TIME_8197F) +#define BIT_SET_CHNL_BUSY_TIME_8197F(x, v) \ + (BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) | BIT_CHNL_BUSY_TIME_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -8339,12 +10924,15 @@ #define BIT_SHIFT_TXOPLIMIT_8197F 16 #define BIT_MASK_TXOPLIMIT_8197F 0x7ff -#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) -#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_TXOPLIMIT_8197F(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F \ + (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) #define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) -#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) -#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) - +#define BIT_GET_TXOPLIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) #define BIT_SHIFT_CW_8197F 8 #define BIT_MASK_CW_8197F 0xff @@ -8354,28 +10942,30 @@ #define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) #define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) - #define BIT_SHIFT_AIFS_8197F 0 #define BIT_MASK_AIFS_8197F 0xff #define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) #define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) #define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) -#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_GET_AIFS_8197F(x) \ + (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) #define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) - /* 2 REG_EDCA_VI_PARAM_8197F */ /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_TXOPLIMIT_8197F 16 #define BIT_MASK_TXOPLIMIT_8197F 0x7ff -#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) -#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_TXOPLIMIT_8197F(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F \ + (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) #define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) -#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) -#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) - +#define BIT_GET_TXOPLIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) #define BIT_SHIFT_CW_8197F 8 #define BIT_MASK_CW_8197F 0xff @@ -8385,28 +10975,30 @@ #define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) #define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) - #define BIT_SHIFT_AIFS_8197F 0 #define BIT_MASK_AIFS_8197F 0xff #define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) #define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) #define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) -#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_GET_AIFS_8197F(x) \ + (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) #define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) - /* 2 REG_EDCA_BE_PARAM_8197F */ /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_TXOPLIMIT_8197F 16 #define BIT_MASK_TXOPLIMIT_8197F 0x7ff -#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) -#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_TXOPLIMIT_8197F(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F \ + (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) #define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) -#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) -#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) - +#define BIT_GET_TXOPLIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) #define BIT_SHIFT_CW_8197F 8 #define BIT_MASK_CW_8197F 0xff @@ -8416,28 +11008,30 @@ #define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) #define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) - #define BIT_SHIFT_AIFS_8197F 0 #define BIT_MASK_AIFS_8197F 0xff #define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) #define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) #define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) -#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_GET_AIFS_8197F(x) \ + (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) #define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) - /* 2 REG_EDCA_BK_PARAM_8197F */ /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_TXOPLIMIT_8197F 16 #define BIT_MASK_TXOPLIMIT_8197F 0x7ff -#define BIT_TXOPLIMIT_8197F(x) (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) -#define BITS_TXOPLIMIT_8197F (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) +#define BIT_TXOPLIMIT_8197F(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F) +#define BITS_TXOPLIMIT_8197F \ + (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F) #define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F)) -#define BIT_GET_TXOPLIMIT_8197F(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) -#define BIT_SET_TXOPLIMIT_8197F(x, v) (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) - +#define BIT_GET_TXOPLIMIT_8197F(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F) +#define BIT_SET_TXOPLIMIT_8197F(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v)) #define BIT_SHIFT_CW_8197F 8 #define BIT_MASK_CW_8197F 0xff @@ -8447,44 +11041,51 @@ #define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F) #define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v)) - #define BIT_SHIFT_AIFS_8197F 0 #define BIT_MASK_AIFS_8197F 0xff #define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F) #define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F) #define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F)) -#define BIT_GET_AIFS_8197F(x) (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) +#define BIT_GET_AIFS_8197F(x) \ + (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F) #define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v)) - /* 2 REG_BCNTCFG_8197F */ #define BIT_SHIFT_BCNCW_MAX_8197F 12 #define BIT_MASK_BCNCW_MAX_8197F 0xf -#define BIT_BCNCW_MAX_8197F(x) (((x) & BIT_MASK_BCNCW_MAX_8197F) << BIT_SHIFT_BCNCW_MAX_8197F) -#define BITS_BCNCW_MAX_8197F (BIT_MASK_BCNCW_MAX_8197F << BIT_SHIFT_BCNCW_MAX_8197F) +#define BIT_BCNCW_MAX_8197F(x) \ + (((x) & BIT_MASK_BCNCW_MAX_8197F) << BIT_SHIFT_BCNCW_MAX_8197F) +#define BITS_BCNCW_MAX_8197F \ + (BIT_MASK_BCNCW_MAX_8197F << BIT_SHIFT_BCNCW_MAX_8197F) #define BIT_CLEAR_BCNCW_MAX_8197F(x) ((x) & (~BITS_BCNCW_MAX_8197F)) -#define BIT_GET_BCNCW_MAX_8197F(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8197F) & BIT_MASK_BCNCW_MAX_8197F) -#define BIT_SET_BCNCW_MAX_8197F(x, v) (BIT_CLEAR_BCNCW_MAX_8197F(x) | BIT_BCNCW_MAX_8197F(v)) - +#define BIT_GET_BCNCW_MAX_8197F(x) \ + (((x) >> BIT_SHIFT_BCNCW_MAX_8197F) & BIT_MASK_BCNCW_MAX_8197F) +#define BIT_SET_BCNCW_MAX_8197F(x, v) \ + (BIT_CLEAR_BCNCW_MAX_8197F(x) | BIT_BCNCW_MAX_8197F(v)) #define BIT_SHIFT_BCNCW_MIN_8197F 8 #define BIT_MASK_BCNCW_MIN_8197F 0xf -#define BIT_BCNCW_MIN_8197F(x) (((x) & BIT_MASK_BCNCW_MIN_8197F) << BIT_SHIFT_BCNCW_MIN_8197F) -#define BITS_BCNCW_MIN_8197F (BIT_MASK_BCNCW_MIN_8197F << BIT_SHIFT_BCNCW_MIN_8197F) +#define BIT_BCNCW_MIN_8197F(x) \ + (((x) & BIT_MASK_BCNCW_MIN_8197F) << BIT_SHIFT_BCNCW_MIN_8197F) +#define BITS_BCNCW_MIN_8197F \ + (BIT_MASK_BCNCW_MIN_8197F << BIT_SHIFT_BCNCW_MIN_8197F) #define BIT_CLEAR_BCNCW_MIN_8197F(x) ((x) & (~BITS_BCNCW_MIN_8197F)) -#define BIT_GET_BCNCW_MIN_8197F(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8197F) & BIT_MASK_BCNCW_MIN_8197F) -#define BIT_SET_BCNCW_MIN_8197F(x, v) (BIT_CLEAR_BCNCW_MIN_8197F(x) | BIT_BCNCW_MIN_8197F(v)) - +#define BIT_GET_BCNCW_MIN_8197F(x) \ + (((x) >> BIT_SHIFT_BCNCW_MIN_8197F) & BIT_MASK_BCNCW_MIN_8197F) +#define BIT_SET_BCNCW_MIN_8197F(x, v) \ + (BIT_CLEAR_BCNCW_MIN_8197F(x) | BIT_BCNCW_MIN_8197F(v)) #define BIT_SHIFT_BCNIFS_8197F 0 #define BIT_MASK_BCNIFS_8197F 0xff -#define BIT_BCNIFS_8197F(x) (((x) & BIT_MASK_BCNIFS_8197F) << BIT_SHIFT_BCNIFS_8197F) +#define BIT_BCNIFS_8197F(x) \ + (((x) & BIT_MASK_BCNIFS_8197F) << BIT_SHIFT_BCNIFS_8197F) #define BITS_BCNIFS_8197F (BIT_MASK_BCNIFS_8197F << BIT_SHIFT_BCNIFS_8197F) #define BIT_CLEAR_BCNIFS_8197F(x) ((x) & (~BITS_BCNIFS_8197F)) -#define BIT_GET_BCNIFS_8197F(x) (((x) >> BIT_SHIFT_BCNIFS_8197F) & BIT_MASK_BCNIFS_8197F) -#define BIT_SET_BCNIFS_8197F(x, v) (BIT_CLEAR_BCNIFS_8197F(x) | BIT_BCNIFS_8197F(v)) - +#define BIT_GET_BCNIFS_8197F(x) \ + (((x) >> BIT_SHIFT_BCNIFS_8197F) & BIT_MASK_BCNIFS_8197F) +#define BIT_SET_BCNIFS_8197F(x, v) \ + (BIT_CLEAR_BCNIFS_8197F(x) | BIT_BCNIFS_8197F(v)) /* 2 REG_PIFS_8197F */ @@ -8493,80 +11094,104 @@ #define BIT_PIFS_8197F(x) (((x) & BIT_MASK_PIFS_8197F) << BIT_SHIFT_PIFS_8197F) #define BITS_PIFS_8197F (BIT_MASK_PIFS_8197F << BIT_SHIFT_PIFS_8197F) #define BIT_CLEAR_PIFS_8197F(x) ((x) & (~BITS_PIFS_8197F)) -#define BIT_GET_PIFS_8197F(x) (((x) >> BIT_SHIFT_PIFS_8197F) & BIT_MASK_PIFS_8197F) +#define BIT_GET_PIFS_8197F(x) \ + (((x) >> BIT_SHIFT_PIFS_8197F) & BIT_MASK_PIFS_8197F) #define BIT_SET_PIFS_8197F(x, v) (BIT_CLEAR_PIFS_8197F(x) | BIT_PIFS_8197F(v)) - /* 2 REG_RDG_PIFS_8197F */ #define BIT_SHIFT_RDG_PIFS_8197F 0 #define BIT_MASK_RDG_PIFS_8197F 0xff -#define BIT_RDG_PIFS_8197F(x) (((x) & BIT_MASK_RDG_PIFS_8197F) << BIT_SHIFT_RDG_PIFS_8197F) -#define BITS_RDG_PIFS_8197F (BIT_MASK_RDG_PIFS_8197F << BIT_SHIFT_RDG_PIFS_8197F) +#define BIT_RDG_PIFS_8197F(x) \ + (((x) & BIT_MASK_RDG_PIFS_8197F) << BIT_SHIFT_RDG_PIFS_8197F) +#define BITS_RDG_PIFS_8197F \ + (BIT_MASK_RDG_PIFS_8197F << BIT_SHIFT_RDG_PIFS_8197F) #define BIT_CLEAR_RDG_PIFS_8197F(x) ((x) & (~BITS_RDG_PIFS_8197F)) -#define BIT_GET_RDG_PIFS_8197F(x) (((x) >> BIT_SHIFT_RDG_PIFS_8197F) & BIT_MASK_RDG_PIFS_8197F) -#define BIT_SET_RDG_PIFS_8197F(x, v) (BIT_CLEAR_RDG_PIFS_8197F(x) | BIT_RDG_PIFS_8197F(v)) - +#define BIT_GET_RDG_PIFS_8197F(x) \ + (((x) >> BIT_SHIFT_RDG_PIFS_8197F) & BIT_MASK_RDG_PIFS_8197F) +#define BIT_SET_RDG_PIFS_8197F(x, v) \ + (BIT_CLEAR_RDG_PIFS_8197F(x) | BIT_RDG_PIFS_8197F(v)) /* 2 REG_SIFS_8197F */ #define BIT_SHIFT_SIFS_OFDM_TRX_8197F 24 #define BIT_MASK_SIFS_OFDM_TRX_8197F 0xff -#define BIT_SIFS_OFDM_TRX_8197F(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8197F) << BIT_SHIFT_SIFS_OFDM_TRX_8197F) -#define BITS_SIFS_OFDM_TRX_8197F (BIT_MASK_SIFS_OFDM_TRX_8197F << BIT_SHIFT_SIFS_OFDM_TRX_8197F) +#define BIT_SIFS_OFDM_TRX_8197F(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX_8197F) << BIT_SHIFT_SIFS_OFDM_TRX_8197F) +#define BITS_SIFS_OFDM_TRX_8197F \ + (BIT_MASK_SIFS_OFDM_TRX_8197F << BIT_SHIFT_SIFS_OFDM_TRX_8197F) #define BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) ((x) & (~BITS_SIFS_OFDM_TRX_8197F)) -#define BIT_GET_SIFS_OFDM_TRX_8197F(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8197F) & BIT_MASK_SIFS_OFDM_TRX_8197F) -#define BIT_SET_SIFS_OFDM_TRX_8197F(x, v) (BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) | BIT_SIFS_OFDM_TRX_8197F(v)) - +#define BIT_GET_SIFS_OFDM_TRX_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8197F) & BIT_MASK_SIFS_OFDM_TRX_8197F) +#define BIT_SET_SIFS_OFDM_TRX_8197F(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) | BIT_SIFS_OFDM_TRX_8197F(v)) #define BIT_SHIFT_SIFS_CCK_TRX_8197F 16 #define BIT_MASK_SIFS_CCK_TRX_8197F 0xff -#define BIT_SIFS_CCK_TRX_8197F(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8197F) << BIT_SHIFT_SIFS_CCK_TRX_8197F) -#define BITS_SIFS_CCK_TRX_8197F (BIT_MASK_SIFS_CCK_TRX_8197F << BIT_SHIFT_SIFS_CCK_TRX_8197F) +#define BIT_SIFS_CCK_TRX_8197F(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX_8197F) << BIT_SHIFT_SIFS_CCK_TRX_8197F) +#define BITS_SIFS_CCK_TRX_8197F \ + (BIT_MASK_SIFS_CCK_TRX_8197F << BIT_SHIFT_SIFS_CCK_TRX_8197F) #define BIT_CLEAR_SIFS_CCK_TRX_8197F(x) ((x) & (~BITS_SIFS_CCK_TRX_8197F)) -#define BIT_GET_SIFS_CCK_TRX_8197F(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8197F) & BIT_MASK_SIFS_CCK_TRX_8197F) -#define BIT_SET_SIFS_CCK_TRX_8197F(x, v) (BIT_CLEAR_SIFS_CCK_TRX_8197F(x) | BIT_SIFS_CCK_TRX_8197F(v)) - +#define BIT_GET_SIFS_CCK_TRX_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8197F) & BIT_MASK_SIFS_CCK_TRX_8197F) +#define BIT_SET_SIFS_CCK_TRX_8197F(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX_8197F(x) | BIT_SIFS_CCK_TRX_8197F(v)) #define BIT_SHIFT_SIFS_OFDM_CTX_8197F 8 #define BIT_MASK_SIFS_OFDM_CTX_8197F 0xff -#define BIT_SIFS_OFDM_CTX_8197F(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8197F) << BIT_SHIFT_SIFS_OFDM_CTX_8197F) -#define BITS_SIFS_OFDM_CTX_8197F (BIT_MASK_SIFS_OFDM_CTX_8197F << BIT_SHIFT_SIFS_OFDM_CTX_8197F) +#define BIT_SIFS_OFDM_CTX_8197F(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX_8197F) << BIT_SHIFT_SIFS_OFDM_CTX_8197F) +#define BITS_SIFS_OFDM_CTX_8197F \ + (BIT_MASK_SIFS_OFDM_CTX_8197F << BIT_SHIFT_SIFS_OFDM_CTX_8197F) #define BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) ((x) & (~BITS_SIFS_OFDM_CTX_8197F)) -#define BIT_GET_SIFS_OFDM_CTX_8197F(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8197F) & BIT_MASK_SIFS_OFDM_CTX_8197F) -#define BIT_SET_SIFS_OFDM_CTX_8197F(x, v) (BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) | BIT_SIFS_OFDM_CTX_8197F(v)) - +#define BIT_GET_SIFS_OFDM_CTX_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8197F) & BIT_MASK_SIFS_OFDM_CTX_8197F) +#define BIT_SET_SIFS_OFDM_CTX_8197F(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) | BIT_SIFS_OFDM_CTX_8197F(v)) #define BIT_SHIFT_SIFS_CCK_CTX_8197F 0 #define BIT_MASK_SIFS_CCK_CTX_8197F 0xff -#define BIT_SIFS_CCK_CTX_8197F(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8197F) << BIT_SHIFT_SIFS_CCK_CTX_8197F) -#define BITS_SIFS_CCK_CTX_8197F (BIT_MASK_SIFS_CCK_CTX_8197F << BIT_SHIFT_SIFS_CCK_CTX_8197F) +#define BIT_SIFS_CCK_CTX_8197F(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX_8197F) << BIT_SHIFT_SIFS_CCK_CTX_8197F) +#define BITS_SIFS_CCK_CTX_8197F \ + (BIT_MASK_SIFS_CCK_CTX_8197F << BIT_SHIFT_SIFS_CCK_CTX_8197F) #define BIT_CLEAR_SIFS_CCK_CTX_8197F(x) ((x) & (~BITS_SIFS_CCK_CTX_8197F)) -#define BIT_GET_SIFS_CCK_CTX_8197F(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8197F) & BIT_MASK_SIFS_CCK_CTX_8197F) -#define BIT_SET_SIFS_CCK_CTX_8197F(x, v) (BIT_CLEAR_SIFS_CCK_CTX_8197F(x) | BIT_SIFS_CCK_CTX_8197F(v)) - +#define BIT_GET_SIFS_CCK_CTX_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8197F) & BIT_MASK_SIFS_CCK_CTX_8197F) +#define BIT_SET_SIFS_CCK_CTX_8197F(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX_8197F(x) | BIT_SIFS_CCK_CTX_8197F(v)) /* 2 REG_TSFTR_SYN_OFFSET_8197F */ #define BIT_SHIFT_TSFTR_SNC_OFFSET_8197F 0 #define BIT_MASK_TSFTR_SNC_OFFSET_8197F 0xffff -#define BIT_TSFTR_SNC_OFFSET_8197F(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8197F) << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) -#define BITS_TSFTR_SNC_OFFSET_8197F (BIT_MASK_TSFTR_SNC_OFFSET_8197F << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) -#define BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) ((x) & (~BITS_TSFTR_SNC_OFFSET_8197F)) -#define BIT_GET_TSFTR_SNC_OFFSET_8197F(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) & BIT_MASK_TSFTR_SNC_OFFSET_8197F) -#define BIT_SET_TSFTR_SNC_OFFSET_8197F(x, v) (BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) | BIT_TSFTR_SNC_OFFSET_8197F(v)) - +#define BIT_TSFTR_SNC_OFFSET_8197F(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8197F) \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) +#define BITS_TSFTR_SNC_OFFSET_8197F \ + (BIT_MASK_TSFTR_SNC_OFFSET_8197F << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) \ + ((x) & (~BITS_TSFTR_SNC_OFFSET_8197F)) +#define BIT_GET_TSFTR_SNC_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) & \ + BIT_MASK_TSFTR_SNC_OFFSET_8197F) +#define BIT_SET_TSFTR_SNC_OFFSET_8197F(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) | BIT_TSFTR_SNC_OFFSET_8197F(v)) /* 2 REG_AGGR_BREAK_TIME_8197F */ #define BIT_SHIFT_AGGR_BK_TIME_8197F 0 #define BIT_MASK_AGGR_BK_TIME_8197F 0xff -#define BIT_AGGR_BK_TIME_8197F(x) (((x) & BIT_MASK_AGGR_BK_TIME_8197F) << BIT_SHIFT_AGGR_BK_TIME_8197F) -#define BITS_AGGR_BK_TIME_8197F (BIT_MASK_AGGR_BK_TIME_8197F << BIT_SHIFT_AGGR_BK_TIME_8197F) +#define BIT_AGGR_BK_TIME_8197F(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME_8197F) << BIT_SHIFT_AGGR_BK_TIME_8197F) +#define BITS_AGGR_BK_TIME_8197F \ + (BIT_MASK_AGGR_BK_TIME_8197F << BIT_SHIFT_AGGR_BK_TIME_8197F) #define BIT_CLEAR_AGGR_BK_TIME_8197F(x) ((x) & (~BITS_AGGR_BK_TIME_8197F)) -#define BIT_GET_AGGR_BK_TIME_8197F(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8197F) & BIT_MASK_AGGR_BK_TIME_8197F) -#define BIT_SET_AGGR_BK_TIME_8197F(x, v) (BIT_CLEAR_AGGR_BK_TIME_8197F(x) | BIT_AGGR_BK_TIME_8197F(v)) - +#define BIT_GET_AGGR_BK_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME_8197F) & BIT_MASK_AGGR_BK_TIME_8197F) +#define BIT_SET_AGGR_BK_TIME_8197F(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME_8197F(x) | BIT_AGGR_BK_TIME_8197F(v)) /* 2 REG_SLOT_8197F */ @@ -8575,10 +11200,10 @@ #define BIT_SLOT_8197F(x) (((x) & BIT_MASK_SLOT_8197F) << BIT_SHIFT_SLOT_8197F) #define BITS_SLOT_8197F (BIT_MASK_SLOT_8197F << BIT_SHIFT_SLOT_8197F) #define BIT_CLEAR_SLOT_8197F(x) ((x) & (~BITS_SLOT_8197F)) -#define BIT_GET_SLOT_8197F(x) (((x) >> BIT_SHIFT_SLOT_8197F) & BIT_MASK_SLOT_8197F) +#define BIT_GET_SLOT_8197F(x) \ + (((x) >> BIT_SHIFT_SLOT_8197F) & BIT_MASK_SLOT_8197F) #define BIT_SET_SLOT_8197F(x, v) (BIT_CLEAR_SLOT_8197F(x) | BIT_SLOT_8197F(v)) - /* 2 REG_TX_PTCL_CTRL_8197F */ #define BIT_DIS_EDCCA_8197F BIT(15) #define BIT_DIS_CCA_8197F BIT(14) @@ -8587,11 +11212,15 @@ #define BIT_SHIFT_TXQ_NAV_MSK_8197F 8 #define BIT_MASK_TXQ_NAV_MSK_8197F 0xf -#define BIT_TXQ_NAV_MSK_8197F(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8197F) << BIT_SHIFT_TXQ_NAV_MSK_8197F) -#define BITS_TXQ_NAV_MSK_8197F (BIT_MASK_TXQ_NAV_MSK_8197F << BIT_SHIFT_TXQ_NAV_MSK_8197F) +#define BIT_TXQ_NAV_MSK_8197F(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK_8197F) << BIT_SHIFT_TXQ_NAV_MSK_8197F) +#define BITS_TXQ_NAV_MSK_8197F \ + (BIT_MASK_TXQ_NAV_MSK_8197F << BIT_SHIFT_TXQ_NAV_MSK_8197F) #define BIT_CLEAR_TXQ_NAV_MSK_8197F(x) ((x) & (~BITS_TXQ_NAV_MSK_8197F)) -#define BIT_GET_TXQ_NAV_MSK_8197F(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8197F) & BIT_MASK_TXQ_NAV_MSK_8197F) -#define BIT_SET_TXQ_NAV_MSK_8197F(x, v) (BIT_CLEAR_TXQ_NAV_MSK_8197F(x) | BIT_TXQ_NAV_MSK_8197F(v)) +#define BIT_GET_TXQ_NAV_MSK_8197F(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8197F) & BIT_MASK_TXQ_NAV_MSK_8197F) +#define BIT_SET_TXQ_NAV_MSK_8197F(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK_8197F(x) | BIT_TXQ_NAV_MSK_8197F(v)) #define BIT_DIS_CW_8197F BIT(7) #define BIT_NAV_END_TXOP_8197F BIT(6) @@ -8669,21 +11298,29 @@ #define BIT_SHIFT_CCA_FILTER_THRS_8197F 8 #define BIT_MASK_CCA_FILTER_THRS_8197F 0xff -#define BIT_CCA_FILTER_THRS_8197F(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8197F) << BIT_SHIFT_CCA_FILTER_THRS_8197F) -#define BITS_CCA_FILTER_THRS_8197F (BIT_MASK_CCA_FILTER_THRS_8197F << BIT_SHIFT_CCA_FILTER_THRS_8197F) +#define BIT_CCA_FILTER_THRS_8197F(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS_8197F) \ + << BIT_SHIFT_CCA_FILTER_THRS_8197F) +#define BITS_CCA_FILTER_THRS_8197F \ + (BIT_MASK_CCA_FILTER_THRS_8197F << BIT_SHIFT_CCA_FILTER_THRS_8197F) #define BIT_CLEAR_CCA_FILTER_THRS_8197F(x) ((x) & (~BITS_CCA_FILTER_THRS_8197F)) -#define BIT_GET_CCA_FILTER_THRS_8197F(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8197F) & BIT_MASK_CCA_FILTER_THRS_8197F) -#define BIT_SET_CCA_FILTER_THRS_8197F(x, v) (BIT_CLEAR_CCA_FILTER_THRS_8197F(x) | BIT_CCA_FILTER_THRS_8197F(v)) - +#define BIT_GET_CCA_FILTER_THRS_8197F(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8197F) & \ + BIT_MASK_CCA_FILTER_THRS_8197F) +#define BIT_SET_CCA_FILTER_THRS_8197F(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS_8197F(x) | BIT_CCA_FILTER_THRS_8197F(v)) #define BIT_SHIFT_EDCCA_THRS_8197F 0 #define BIT_MASK_EDCCA_THRS_8197F 0xff -#define BIT_EDCCA_THRS_8197F(x) (((x) & BIT_MASK_EDCCA_THRS_8197F) << BIT_SHIFT_EDCCA_THRS_8197F) -#define BITS_EDCCA_THRS_8197F (BIT_MASK_EDCCA_THRS_8197F << BIT_SHIFT_EDCCA_THRS_8197F) +#define BIT_EDCCA_THRS_8197F(x) \ + (((x) & BIT_MASK_EDCCA_THRS_8197F) << BIT_SHIFT_EDCCA_THRS_8197F) +#define BITS_EDCCA_THRS_8197F \ + (BIT_MASK_EDCCA_THRS_8197F << BIT_SHIFT_EDCCA_THRS_8197F) #define BIT_CLEAR_EDCCA_THRS_8197F(x) ((x) & (~BITS_EDCCA_THRS_8197F)) -#define BIT_GET_EDCCA_THRS_8197F(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8197F) & BIT_MASK_EDCCA_THRS_8197F) -#define BIT_SET_EDCCA_THRS_8197F(x, v) (BIT_CLEAR_EDCCA_THRS_8197F(x) | BIT_EDCCA_THRS_8197F(v)) - +#define BIT_GET_EDCCA_THRS_8197F(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS_8197F) & BIT_MASK_EDCCA_THRS_8197F) +#define BIT_SET_EDCCA_THRS_8197F(x, v) \ + (BIT_CLEAR_EDCCA_THRS_8197F(x) | BIT_EDCCA_THRS_8197F(v)) /* 2 REG_P2PPS_SPEC_STATE_8197F */ #define BIT_SPEC_POWER_STATE_8197F BIT(7) @@ -8699,109 +11336,163 @@ #define BIT_SHIFT_P2PON_DIS_TXTIME_8197F 0 #define BIT_MASK_P2PON_DIS_TXTIME_8197F 0xff -#define BIT_P2PON_DIS_TXTIME_8197F(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8197F) << BIT_SHIFT_P2PON_DIS_TXTIME_8197F) -#define BITS_P2PON_DIS_TXTIME_8197F (BIT_MASK_P2PON_DIS_TXTIME_8197F << BIT_SHIFT_P2PON_DIS_TXTIME_8197F) -#define BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) ((x) & (~BITS_P2PON_DIS_TXTIME_8197F)) -#define BIT_GET_P2PON_DIS_TXTIME_8197F(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8197F) & BIT_MASK_P2PON_DIS_TXTIME_8197F) -#define BIT_SET_P2PON_DIS_TXTIME_8197F(x, v) (BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) | BIT_P2PON_DIS_TXTIME_8197F(v)) - +#define BIT_P2PON_DIS_TXTIME_8197F(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME_8197F) \ + << BIT_SHIFT_P2PON_DIS_TXTIME_8197F) +#define BITS_P2PON_DIS_TXTIME_8197F \ + (BIT_MASK_P2PON_DIS_TXTIME_8197F << BIT_SHIFT_P2PON_DIS_TXTIME_8197F) +#define BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) \ + ((x) & (~BITS_P2PON_DIS_TXTIME_8197F)) +#define BIT_GET_P2PON_DIS_TXTIME_8197F(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8197F) & \ + BIT_MASK_P2PON_DIS_TXTIME_8197F) +#define BIT_SET_P2PON_DIS_TXTIME_8197F(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) | BIT_P2PON_DIS_TXTIME_8197F(v)) /* 2 REG_QUEUE_INCOL_THR_8197F */ #define BIT_SHIFT_BK_QUEUE_THR_8197F 24 #define BIT_MASK_BK_QUEUE_THR_8197F 0xff -#define BIT_BK_QUEUE_THR_8197F(x) (((x) & BIT_MASK_BK_QUEUE_THR_8197F) << BIT_SHIFT_BK_QUEUE_THR_8197F) -#define BITS_BK_QUEUE_THR_8197F (BIT_MASK_BK_QUEUE_THR_8197F << BIT_SHIFT_BK_QUEUE_THR_8197F) +#define BIT_BK_QUEUE_THR_8197F(x) \ + (((x) & BIT_MASK_BK_QUEUE_THR_8197F) << BIT_SHIFT_BK_QUEUE_THR_8197F) +#define BITS_BK_QUEUE_THR_8197F \ + (BIT_MASK_BK_QUEUE_THR_8197F << BIT_SHIFT_BK_QUEUE_THR_8197F) #define BIT_CLEAR_BK_QUEUE_THR_8197F(x) ((x) & (~BITS_BK_QUEUE_THR_8197F)) -#define BIT_GET_BK_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_BK_QUEUE_THR_8197F) & BIT_MASK_BK_QUEUE_THR_8197F) -#define BIT_SET_BK_QUEUE_THR_8197F(x, v) (BIT_CLEAR_BK_QUEUE_THR_8197F(x) | BIT_BK_QUEUE_THR_8197F(v)) - +#define BIT_GET_BK_QUEUE_THR_8197F(x) \ + (((x) >> BIT_SHIFT_BK_QUEUE_THR_8197F) & BIT_MASK_BK_QUEUE_THR_8197F) +#define BIT_SET_BK_QUEUE_THR_8197F(x, v) \ + (BIT_CLEAR_BK_QUEUE_THR_8197F(x) | BIT_BK_QUEUE_THR_8197F(v)) #define BIT_SHIFT_BE_QUEUE_THR_8197F 16 #define BIT_MASK_BE_QUEUE_THR_8197F 0xff -#define BIT_BE_QUEUE_THR_8197F(x) (((x) & BIT_MASK_BE_QUEUE_THR_8197F) << BIT_SHIFT_BE_QUEUE_THR_8197F) -#define BITS_BE_QUEUE_THR_8197F (BIT_MASK_BE_QUEUE_THR_8197F << BIT_SHIFT_BE_QUEUE_THR_8197F) +#define BIT_BE_QUEUE_THR_8197F(x) \ + (((x) & BIT_MASK_BE_QUEUE_THR_8197F) << BIT_SHIFT_BE_QUEUE_THR_8197F) +#define BITS_BE_QUEUE_THR_8197F \ + (BIT_MASK_BE_QUEUE_THR_8197F << BIT_SHIFT_BE_QUEUE_THR_8197F) #define BIT_CLEAR_BE_QUEUE_THR_8197F(x) ((x) & (~BITS_BE_QUEUE_THR_8197F)) -#define BIT_GET_BE_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_BE_QUEUE_THR_8197F) & BIT_MASK_BE_QUEUE_THR_8197F) -#define BIT_SET_BE_QUEUE_THR_8197F(x, v) (BIT_CLEAR_BE_QUEUE_THR_8197F(x) | BIT_BE_QUEUE_THR_8197F(v)) - +#define BIT_GET_BE_QUEUE_THR_8197F(x) \ + (((x) >> BIT_SHIFT_BE_QUEUE_THR_8197F) & BIT_MASK_BE_QUEUE_THR_8197F) +#define BIT_SET_BE_QUEUE_THR_8197F(x, v) \ + (BIT_CLEAR_BE_QUEUE_THR_8197F(x) | BIT_BE_QUEUE_THR_8197F(v)) #define BIT_SHIFT_VI_QUEUE_THR_8197F 8 #define BIT_MASK_VI_QUEUE_THR_8197F 0xff -#define BIT_VI_QUEUE_THR_8197F(x) (((x) & BIT_MASK_VI_QUEUE_THR_8197F) << BIT_SHIFT_VI_QUEUE_THR_8197F) -#define BITS_VI_QUEUE_THR_8197F (BIT_MASK_VI_QUEUE_THR_8197F << BIT_SHIFT_VI_QUEUE_THR_8197F) +#define BIT_VI_QUEUE_THR_8197F(x) \ + (((x) & BIT_MASK_VI_QUEUE_THR_8197F) << BIT_SHIFT_VI_QUEUE_THR_8197F) +#define BITS_VI_QUEUE_THR_8197F \ + (BIT_MASK_VI_QUEUE_THR_8197F << BIT_SHIFT_VI_QUEUE_THR_8197F) #define BIT_CLEAR_VI_QUEUE_THR_8197F(x) ((x) & (~BITS_VI_QUEUE_THR_8197F)) -#define BIT_GET_VI_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_VI_QUEUE_THR_8197F) & BIT_MASK_VI_QUEUE_THR_8197F) -#define BIT_SET_VI_QUEUE_THR_8197F(x, v) (BIT_CLEAR_VI_QUEUE_THR_8197F(x) | BIT_VI_QUEUE_THR_8197F(v)) - +#define BIT_GET_VI_QUEUE_THR_8197F(x) \ + (((x) >> BIT_SHIFT_VI_QUEUE_THR_8197F) & BIT_MASK_VI_QUEUE_THR_8197F) +#define BIT_SET_VI_QUEUE_THR_8197F(x, v) \ + (BIT_CLEAR_VI_QUEUE_THR_8197F(x) | BIT_VI_QUEUE_THR_8197F(v)) #define BIT_SHIFT_VO_QUEUE_THR_8197F 0 #define BIT_MASK_VO_QUEUE_THR_8197F 0xff -#define BIT_VO_QUEUE_THR_8197F(x) (((x) & BIT_MASK_VO_QUEUE_THR_8197F) << BIT_SHIFT_VO_QUEUE_THR_8197F) -#define BITS_VO_QUEUE_THR_8197F (BIT_MASK_VO_QUEUE_THR_8197F << BIT_SHIFT_VO_QUEUE_THR_8197F) +#define BIT_VO_QUEUE_THR_8197F(x) \ + (((x) & BIT_MASK_VO_QUEUE_THR_8197F) << BIT_SHIFT_VO_QUEUE_THR_8197F) +#define BITS_VO_QUEUE_THR_8197F \ + (BIT_MASK_VO_QUEUE_THR_8197F << BIT_SHIFT_VO_QUEUE_THR_8197F) #define BIT_CLEAR_VO_QUEUE_THR_8197F(x) ((x) & (~BITS_VO_QUEUE_THR_8197F)) -#define BIT_GET_VO_QUEUE_THR_8197F(x) (((x) >> BIT_SHIFT_VO_QUEUE_THR_8197F) & BIT_MASK_VO_QUEUE_THR_8197F) -#define BIT_SET_VO_QUEUE_THR_8197F(x, v) (BIT_CLEAR_VO_QUEUE_THR_8197F(x) | BIT_VO_QUEUE_THR_8197F(v)) - +#define BIT_GET_VO_QUEUE_THR_8197F(x) \ + (((x) >> BIT_SHIFT_VO_QUEUE_THR_8197F) & BIT_MASK_VO_QUEUE_THR_8197F) +#define BIT_SET_VO_QUEUE_THR_8197F(x, v) \ + (BIT_CLEAR_VO_QUEUE_THR_8197F(x) | BIT_VO_QUEUE_THR_8197F(v)) /* 2 REG_QUEUE_INCOL_EN_8197F */ #define BIT_QUEUE_INCOL_EN_8197F BIT(16) #define BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F 12 #define BIT_MASK_BK_TRIGGER_NUM_V1_8197F 0xf -#define BIT_BK_TRIGGER_NUM_V1_8197F(x) (((x) & BIT_MASK_BK_TRIGGER_NUM_V1_8197F) << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) -#define BITS_BK_TRIGGER_NUM_V1_8197F (BIT_MASK_BK_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) -#define BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) ((x) & (~BITS_BK_TRIGGER_NUM_V1_8197F)) -#define BIT_GET_BK_TRIGGER_NUM_V1_8197F(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) & BIT_MASK_BK_TRIGGER_NUM_V1_8197F) -#define BIT_SET_BK_TRIGGER_NUM_V1_8197F(x, v) (BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) | BIT_BK_TRIGGER_NUM_V1_8197F(v)) - +#define BIT_BK_TRIGGER_NUM_V1_8197F(x) \ + (((x) & BIT_MASK_BK_TRIGGER_NUM_V1_8197F) \ + << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) +#define BITS_BK_TRIGGER_NUM_V1_8197F \ + (BIT_MASK_BK_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) +#define BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) \ + ((x) & (~BITS_BK_TRIGGER_NUM_V1_8197F)) +#define BIT_GET_BK_TRIGGER_NUM_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) & \ + BIT_MASK_BK_TRIGGER_NUM_V1_8197F) +#define BIT_SET_BK_TRIGGER_NUM_V1_8197F(x, v) \ + (BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) | BIT_BK_TRIGGER_NUM_V1_8197F(v)) #define BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F 8 #define BIT_MASK_BE_TRIGGER_NUM_V1_8197F 0xf -#define BIT_BE_TRIGGER_NUM_V1_8197F(x) (((x) & BIT_MASK_BE_TRIGGER_NUM_V1_8197F) << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) -#define BITS_BE_TRIGGER_NUM_V1_8197F (BIT_MASK_BE_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) -#define BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) ((x) & (~BITS_BE_TRIGGER_NUM_V1_8197F)) -#define BIT_GET_BE_TRIGGER_NUM_V1_8197F(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) & BIT_MASK_BE_TRIGGER_NUM_V1_8197F) -#define BIT_SET_BE_TRIGGER_NUM_V1_8197F(x, v) (BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) | BIT_BE_TRIGGER_NUM_V1_8197F(v)) - +#define BIT_BE_TRIGGER_NUM_V1_8197F(x) \ + (((x) & BIT_MASK_BE_TRIGGER_NUM_V1_8197F) \ + << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) +#define BITS_BE_TRIGGER_NUM_V1_8197F \ + (BIT_MASK_BE_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) +#define BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) \ + ((x) & (~BITS_BE_TRIGGER_NUM_V1_8197F)) +#define BIT_GET_BE_TRIGGER_NUM_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) & \ + BIT_MASK_BE_TRIGGER_NUM_V1_8197F) +#define BIT_SET_BE_TRIGGER_NUM_V1_8197F(x, v) \ + (BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) | BIT_BE_TRIGGER_NUM_V1_8197F(v)) #define BIT_SHIFT_VI_TRIGGER_NUM_8197F 4 #define BIT_MASK_VI_TRIGGER_NUM_8197F 0xf -#define BIT_VI_TRIGGER_NUM_8197F(x) (((x) & BIT_MASK_VI_TRIGGER_NUM_8197F) << BIT_SHIFT_VI_TRIGGER_NUM_8197F) -#define BITS_VI_TRIGGER_NUM_8197F (BIT_MASK_VI_TRIGGER_NUM_8197F << BIT_SHIFT_VI_TRIGGER_NUM_8197F) +#define BIT_VI_TRIGGER_NUM_8197F(x) \ + (((x) & BIT_MASK_VI_TRIGGER_NUM_8197F) \ + << BIT_SHIFT_VI_TRIGGER_NUM_8197F) +#define BITS_VI_TRIGGER_NUM_8197F \ + (BIT_MASK_VI_TRIGGER_NUM_8197F << BIT_SHIFT_VI_TRIGGER_NUM_8197F) #define BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VI_TRIGGER_NUM_8197F)) -#define BIT_GET_VI_TRIGGER_NUM_8197F(x) (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8197F) & BIT_MASK_VI_TRIGGER_NUM_8197F) -#define BIT_SET_VI_TRIGGER_NUM_8197F(x, v) (BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) | BIT_VI_TRIGGER_NUM_8197F(v)) - +#define BIT_GET_VI_TRIGGER_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8197F) & \ + BIT_MASK_VI_TRIGGER_NUM_8197F) +#define BIT_SET_VI_TRIGGER_NUM_8197F(x, v) \ + (BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) | BIT_VI_TRIGGER_NUM_8197F(v)) #define BIT_SHIFT_VO_TRIGGER_NUM_8197F 0 #define BIT_MASK_VO_TRIGGER_NUM_8197F 0xf -#define BIT_VO_TRIGGER_NUM_8197F(x) (((x) & BIT_MASK_VO_TRIGGER_NUM_8197F) << BIT_SHIFT_VO_TRIGGER_NUM_8197F) -#define BITS_VO_TRIGGER_NUM_8197F (BIT_MASK_VO_TRIGGER_NUM_8197F << BIT_SHIFT_VO_TRIGGER_NUM_8197F) +#define BIT_VO_TRIGGER_NUM_8197F(x) \ + (((x) & BIT_MASK_VO_TRIGGER_NUM_8197F) \ + << BIT_SHIFT_VO_TRIGGER_NUM_8197F) +#define BITS_VO_TRIGGER_NUM_8197F \ + (BIT_MASK_VO_TRIGGER_NUM_8197F << BIT_SHIFT_VO_TRIGGER_NUM_8197F) #define BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VO_TRIGGER_NUM_8197F)) -#define BIT_GET_VO_TRIGGER_NUM_8197F(x) (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8197F) & BIT_MASK_VO_TRIGGER_NUM_8197F) -#define BIT_SET_VO_TRIGGER_NUM_8197F(x, v) (BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) | BIT_VO_TRIGGER_NUM_8197F(v)) - +#define BIT_GET_VO_TRIGGER_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8197F) & \ + BIT_MASK_VO_TRIGGER_NUM_8197F) +#define BIT_SET_VO_TRIGGER_NUM_8197F(x, v) \ + (BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) | BIT_VO_TRIGGER_NUM_8197F(v)) /* 2 REG_TBTT_PROHIBIT_8197F */ #define BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F 8 #define BIT_MASK_TBTT_HOLD_TIME_AP_8197F 0xfff -#define BIT_TBTT_HOLD_TIME_AP_8197F(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8197F) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) -#define BITS_TBTT_HOLD_TIME_AP_8197F (BIT_MASK_TBTT_HOLD_TIME_AP_8197F << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) -#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) ((x) & (~BITS_TBTT_HOLD_TIME_AP_8197F)) -#define BIT_GET_TBTT_HOLD_TIME_AP_8197F(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) & BIT_MASK_TBTT_HOLD_TIME_AP_8197F) -#define BIT_SET_TBTT_HOLD_TIME_AP_8197F(x, v) (BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) | BIT_TBTT_HOLD_TIME_AP_8197F(v)) - +#define BIT_TBTT_HOLD_TIME_AP_8197F(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8197F) \ + << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) +#define BITS_TBTT_HOLD_TIME_AP_8197F \ + (BIT_MASK_TBTT_HOLD_TIME_AP_8197F << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) +#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) \ + ((x) & (~BITS_TBTT_HOLD_TIME_AP_8197F)) +#define BIT_GET_TBTT_HOLD_TIME_AP_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) & \ + BIT_MASK_TBTT_HOLD_TIME_AP_8197F) +#define BIT_SET_TBTT_HOLD_TIME_AP_8197F(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) | BIT_TBTT_HOLD_TIME_AP_8197F(v)) #define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F 0 #define BIT_MASK_TBTT_PROHIBIT_SETUP_8197F 0xf -#define BIT_TBTT_PROHIBIT_SETUP_8197F(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8197F) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) -#define BITS_TBTT_PROHIBIT_SETUP_8197F (BIT_MASK_TBTT_PROHIBIT_SETUP_8197F << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) -#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8197F)) -#define BIT_GET_TBTT_PROHIBIT_SETUP_8197F(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) & BIT_MASK_TBTT_PROHIBIT_SETUP_8197F) -#define BIT_SET_TBTT_PROHIBIT_SETUP_8197F(x, v) (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) | BIT_TBTT_PROHIBIT_SETUP_8197F(v)) - +#define BIT_TBTT_PROHIBIT_SETUP_8197F(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8197F) \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) +#define BITS_TBTT_PROHIBIT_SETUP_8197F \ + (BIT_MASK_TBTT_PROHIBIT_SETUP_8197F \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8197F)) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) & \ + BIT_MASK_TBTT_PROHIBIT_SETUP_8197F) +#define BIT_SET_TBTT_PROHIBIT_SETUP_8197F(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) | \ + BIT_TBTT_PROHIBIT_SETUP_8197F(v)) /* 2 REG_P2PPS_STATE_8197F */ #define BIT_POWER_STATE_8197F BIT(7) @@ -8817,81 +11508,112 @@ #define BIT_SHIFT_RD_NAV_PROT_NXT_8197F 0 #define BIT_MASK_RD_NAV_PROT_NXT_8197F 0xffff -#define BIT_RD_NAV_PROT_NXT_8197F(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8197F) << BIT_SHIFT_RD_NAV_PROT_NXT_8197F) -#define BITS_RD_NAV_PROT_NXT_8197F (BIT_MASK_RD_NAV_PROT_NXT_8197F << BIT_SHIFT_RD_NAV_PROT_NXT_8197F) +#define BIT_RD_NAV_PROT_NXT_8197F(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT_8197F) \ + << BIT_SHIFT_RD_NAV_PROT_NXT_8197F) +#define BITS_RD_NAV_PROT_NXT_8197F \ + (BIT_MASK_RD_NAV_PROT_NXT_8197F << BIT_SHIFT_RD_NAV_PROT_NXT_8197F) #define BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8197F)) -#define BIT_GET_RD_NAV_PROT_NXT_8197F(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8197F) & BIT_MASK_RD_NAV_PROT_NXT_8197F) -#define BIT_SET_RD_NAV_PROT_NXT_8197F(x, v) (BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) | BIT_RD_NAV_PROT_NXT_8197F(v)) - +#define BIT_GET_RD_NAV_PROT_NXT_8197F(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8197F) & \ + BIT_MASK_RD_NAV_PROT_NXT_8197F) +#define BIT_SET_RD_NAV_PROT_NXT_8197F(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) | BIT_RD_NAV_PROT_NXT_8197F(v)) /* 2 REG_NAV_PROT_LEN_8197F */ #define BIT_SHIFT_NAV_PROT_LEN_8197F 0 #define BIT_MASK_NAV_PROT_LEN_8197F 0xffff -#define BIT_NAV_PROT_LEN_8197F(x) (((x) & BIT_MASK_NAV_PROT_LEN_8197F) << BIT_SHIFT_NAV_PROT_LEN_8197F) -#define BITS_NAV_PROT_LEN_8197F (BIT_MASK_NAV_PROT_LEN_8197F << BIT_SHIFT_NAV_PROT_LEN_8197F) +#define BIT_NAV_PROT_LEN_8197F(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN_8197F) << BIT_SHIFT_NAV_PROT_LEN_8197F) +#define BITS_NAV_PROT_LEN_8197F \ + (BIT_MASK_NAV_PROT_LEN_8197F << BIT_SHIFT_NAV_PROT_LEN_8197F) #define BIT_CLEAR_NAV_PROT_LEN_8197F(x) ((x) & (~BITS_NAV_PROT_LEN_8197F)) -#define BIT_GET_NAV_PROT_LEN_8197F(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8197F) & BIT_MASK_NAV_PROT_LEN_8197F) -#define BIT_SET_NAV_PROT_LEN_8197F(x, v) (BIT_CLEAR_NAV_PROT_LEN_8197F(x) | BIT_NAV_PROT_LEN_8197F(v)) - +#define BIT_GET_NAV_PROT_LEN_8197F(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN_8197F) & BIT_MASK_NAV_PROT_LEN_8197F) +#define BIT_SET_NAV_PROT_LEN_8197F(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN_8197F(x) | BIT_NAV_PROT_LEN_8197F(v)) /* 2 REG_FTM_CTRL_8197F */ #define BIT_SHIFT_FTM_TSF_R2T_PORT_8197F 22 #define BIT_MASK_FTM_TSF_R2T_PORT_8197F 0x7 -#define BIT_FTM_TSF_R2T_PORT_8197F(x) (((x) & BIT_MASK_FTM_TSF_R2T_PORT_8197F) << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) -#define BITS_FTM_TSF_R2T_PORT_8197F (BIT_MASK_FTM_TSF_R2T_PORT_8197F << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) -#define BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) ((x) & (~BITS_FTM_TSF_R2T_PORT_8197F)) -#define BIT_GET_FTM_TSF_R2T_PORT_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) & BIT_MASK_FTM_TSF_R2T_PORT_8197F) -#define BIT_SET_FTM_TSF_R2T_PORT_8197F(x, v) (BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) | BIT_FTM_TSF_R2T_PORT_8197F(v)) - +#define BIT_FTM_TSF_R2T_PORT_8197F(x) \ + (((x) & BIT_MASK_FTM_TSF_R2T_PORT_8197F) \ + << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) +#define BITS_FTM_TSF_R2T_PORT_8197F \ + (BIT_MASK_FTM_TSF_R2T_PORT_8197F << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) +#define BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) \ + ((x) & (~BITS_FTM_TSF_R2T_PORT_8197F)) +#define BIT_GET_FTM_TSF_R2T_PORT_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) & \ + BIT_MASK_FTM_TSF_R2T_PORT_8197F) +#define BIT_SET_FTM_TSF_R2T_PORT_8197F(x, v) \ + (BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) | BIT_FTM_TSF_R2T_PORT_8197F(v)) #define BIT_SHIFT_FTM_TSF_T2R_PORT_8197F 19 #define BIT_MASK_FTM_TSF_T2R_PORT_8197F 0x7 -#define BIT_FTM_TSF_T2R_PORT_8197F(x) (((x) & BIT_MASK_FTM_TSF_T2R_PORT_8197F) << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) -#define BITS_FTM_TSF_T2R_PORT_8197F (BIT_MASK_FTM_TSF_T2R_PORT_8197F << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) -#define BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) ((x) & (~BITS_FTM_TSF_T2R_PORT_8197F)) -#define BIT_GET_FTM_TSF_T2R_PORT_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) & BIT_MASK_FTM_TSF_T2R_PORT_8197F) -#define BIT_SET_FTM_TSF_T2R_PORT_8197F(x, v) (BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) | BIT_FTM_TSF_T2R_PORT_8197F(v)) - +#define BIT_FTM_TSF_T2R_PORT_8197F(x) \ + (((x) & BIT_MASK_FTM_TSF_T2R_PORT_8197F) \ + << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) +#define BITS_FTM_TSF_T2R_PORT_8197F \ + (BIT_MASK_FTM_TSF_T2R_PORT_8197F << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) +#define BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) \ + ((x) & (~BITS_FTM_TSF_T2R_PORT_8197F)) +#define BIT_GET_FTM_TSF_T2R_PORT_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) & \ + BIT_MASK_FTM_TSF_T2R_PORT_8197F) +#define BIT_SET_FTM_TSF_T2R_PORT_8197F(x, v) \ + (BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) | BIT_FTM_TSF_T2R_PORT_8197F(v)) #define BIT_SHIFT_FTM_PTT_PORT_8197F 16 #define BIT_MASK_FTM_PTT_PORT_8197F 0x7 -#define BIT_FTM_PTT_PORT_8197F(x) (((x) & BIT_MASK_FTM_PTT_PORT_8197F) << BIT_SHIFT_FTM_PTT_PORT_8197F) -#define BITS_FTM_PTT_PORT_8197F (BIT_MASK_FTM_PTT_PORT_8197F << BIT_SHIFT_FTM_PTT_PORT_8197F) +#define BIT_FTM_PTT_PORT_8197F(x) \ + (((x) & BIT_MASK_FTM_PTT_PORT_8197F) << BIT_SHIFT_FTM_PTT_PORT_8197F) +#define BITS_FTM_PTT_PORT_8197F \ + (BIT_MASK_FTM_PTT_PORT_8197F << BIT_SHIFT_FTM_PTT_PORT_8197F) #define BIT_CLEAR_FTM_PTT_PORT_8197F(x) ((x) & (~BITS_FTM_PTT_PORT_8197F)) -#define BIT_GET_FTM_PTT_PORT_8197F(x) (((x) >> BIT_SHIFT_FTM_PTT_PORT_8197F) & BIT_MASK_FTM_PTT_PORT_8197F) -#define BIT_SET_FTM_PTT_PORT_8197F(x, v) (BIT_CLEAR_FTM_PTT_PORT_8197F(x) | BIT_FTM_PTT_PORT_8197F(v)) - +#define BIT_GET_FTM_PTT_PORT_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_PORT_8197F) & BIT_MASK_FTM_PTT_PORT_8197F) +#define BIT_SET_FTM_PTT_PORT_8197F(x, v) \ + (BIT_CLEAR_FTM_PTT_PORT_8197F(x) | BIT_FTM_PTT_PORT_8197F(v)) #define BIT_SHIFT_FTM_PTT_8197F 0 #define BIT_MASK_FTM_PTT_8197F 0xffff -#define BIT_FTM_PTT_8197F(x) (((x) & BIT_MASK_FTM_PTT_8197F) << BIT_SHIFT_FTM_PTT_8197F) +#define BIT_FTM_PTT_8197F(x) \ + (((x) & BIT_MASK_FTM_PTT_8197F) << BIT_SHIFT_FTM_PTT_8197F) #define BITS_FTM_PTT_8197F (BIT_MASK_FTM_PTT_8197F << BIT_SHIFT_FTM_PTT_8197F) #define BIT_CLEAR_FTM_PTT_8197F(x) ((x) & (~BITS_FTM_PTT_8197F)) -#define BIT_GET_FTM_PTT_8197F(x) (((x) >> BIT_SHIFT_FTM_PTT_8197F) & BIT_MASK_FTM_PTT_8197F) -#define BIT_SET_FTM_PTT_8197F(x, v) (BIT_CLEAR_FTM_PTT_8197F(x) | BIT_FTM_PTT_8197F(v)) - +#define BIT_GET_FTM_PTT_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_8197F) & BIT_MASK_FTM_PTT_8197F) +#define BIT_SET_FTM_PTT_8197F(x, v) \ + (BIT_CLEAR_FTM_PTT_8197F(x) | BIT_FTM_PTT_8197F(v)) /* 2 REG_FTM_TSF_CNT_8197F */ #define BIT_SHIFT_FTM_TSF_R2T_8197F 16 #define BIT_MASK_FTM_TSF_R2T_8197F 0xffff -#define BIT_FTM_TSF_R2T_8197F(x) (((x) & BIT_MASK_FTM_TSF_R2T_8197F) << BIT_SHIFT_FTM_TSF_R2T_8197F) -#define BITS_FTM_TSF_R2T_8197F (BIT_MASK_FTM_TSF_R2T_8197F << BIT_SHIFT_FTM_TSF_R2T_8197F) +#define BIT_FTM_TSF_R2T_8197F(x) \ + (((x) & BIT_MASK_FTM_TSF_R2T_8197F) << BIT_SHIFT_FTM_TSF_R2T_8197F) +#define BITS_FTM_TSF_R2T_8197F \ + (BIT_MASK_FTM_TSF_R2T_8197F << BIT_SHIFT_FTM_TSF_R2T_8197F) #define BIT_CLEAR_FTM_TSF_R2T_8197F(x) ((x) & (~BITS_FTM_TSF_R2T_8197F)) -#define BIT_GET_FTM_TSF_R2T_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T_8197F) & BIT_MASK_FTM_TSF_R2T_8197F) -#define BIT_SET_FTM_TSF_R2T_8197F(x, v) (BIT_CLEAR_FTM_TSF_R2T_8197F(x) | BIT_FTM_TSF_R2T_8197F(v)) - +#define BIT_GET_FTM_TSF_R2T_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_R2T_8197F) & BIT_MASK_FTM_TSF_R2T_8197F) +#define BIT_SET_FTM_TSF_R2T_8197F(x, v) \ + (BIT_CLEAR_FTM_TSF_R2T_8197F(x) | BIT_FTM_TSF_R2T_8197F(v)) #define BIT_SHIFT_FTM_TSF_T2R_8197F 0 #define BIT_MASK_FTM_TSF_T2R_8197F 0xffff -#define BIT_FTM_TSF_T2R_8197F(x) (((x) & BIT_MASK_FTM_TSF_T2R_8197F) << BIT_SHIFT_FTM_TSF_T2R_8197F) -#define BITS_FTM_TSF_T2R_8197F (BIT_MASK_FTM_TSF_T2R_8197F << BIT_SHIFT_FTM_TSF_T2R_8197F) +#define BIT_FTM_TSF_T2R_8197F(x) \ + (((x) & BIT_MASK_FTM_TSF_T2R_8197F) << BIT_SHIFT_FTM_TSF_T2R_8197F) +#define BITS_FTM_TSF_T2R_8197F \ + (BIT_MASK_FTM_TSF_T2R_8197F << BIT_SHIFT_FTM_TSF_T2R_8197F) #define BIT_CLEAR_FTM_TSF_T2R_8197F(x) ((x) & (~BITS_FTM_TSF_T2R_8197F)) -#define BIT_GET_FTM_TSF_T2R_8197F(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R_8197F) & BIT_MASK_FTM_TSF_T2R_8197F) -#define BIT_SET_FTM_TSF_T2R_8197F(x, v) (BIT_CLEAR_FTM_TSF_T2R_8197F(x) | BIT_FTM_TSF_T2R_8197F(v)) - +#define BIT_GET_FTM_TSF_T2R_8197F(x) \ + (((x) >> BIT_SHIFT_FTM_TSF_T2R_8197F) & BIT_MASK_FTM_TSF_T2R_8197F) +#define BIT_SET_FTM_TSF_T2R_8197F(x, v) \ + (BIT_CLEAR_FTM_TSF_T2R_8197F(x) | BIT_FTM_TSF_T2R_8197F(v)) /* 2 REG_BCN_CTRL_8197F */ #define BIT_DIS_RX_BSSID_FIT_8197F BIT(6) @@ -8915,12 +11637,15 @@ #define BIT_SHIFT_MBID_BCN_NUM_8197F 0 #define BIT_MASK_MBID_BCN_NUM_8197F 0x7 -#define BIT_MBID_BCN_NUM_8197F(x) (((x) & BIT_MASK_MBID_BCN_NUM_8197F) << BIT_SHIFT_MBID_BCN_NUM_8197F) -#define BITS_MBID_BCN_NUM_8197F (BIT_MASK_MBID_BCN_NUM_8197F << BIT_SHIFT_MBID_BCN_NUM_8197F) +#define BIT_MBID_BCN_NUM_8197F(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_8197F) << BIT_SHIFT_MBID_BCN_NUM_8197F) +#define BITS_MBID_BCN_NUM_8197F \ + (BIT_MASK_MBID_BCN_NUM_8197F << BIT_SHIFT_MBID_BCN_NUM_8197F) #define BIT_CLEAR_MBID_BCN_NUM_8197F(x) ((x) & (~BITS_MBID_BCN_NUM_8197F)) -#define BIT_GET_MBID_BCN_NUM_8197F(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8197F) & BIT_MASK_MBID_BCN_NUM_8197F) -#define BIT_SET_MBID_BCN_NUM_8197F(x, v) (BIT_CLEAR_MBID_BCN_NUM_8197F(x) | BIT_MBID_BCN_NUM_8197F(v)) - +#define BIT_GET_MBID_BCN_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_8197F) & BIT_MASK_MBID_BCN_NUM_8197F) +#define BIT_SET_MBID_BCN_NUM_8197F(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_8197F(x) | BIT_MBID_BCN_NUM_8197F(v)) /* 2 REG_DUAL_TSF_RST_8197F */ #define BIT_FREECNT_RST_8197F BIT(5) @@ -8934,207 +11659,294 @@ #define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F 28 #define BIT_MASK_BCN_TIMER_SEL_FWRD_8197F 0x7 -#define BIT_BCN_TIMER_SEL_FWRD_8197F(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8197F) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) -#define BITS_BCN_TIMER_SEL_FWRD_8197F (BIT_MASK_BCN_TIMER_SEL_FWRD_8197F << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) -#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8197F)) -#define BIT_GET_BCN_TIMER_SEL_FWRD_8197F(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) & BIT_MASK_BCN_TIMER_SEL_FWRD_8197F) -#define BIT_SET_BCN_TIMER_SEL_FWRD_8197F(x, v) (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) | BIT_BCN_TIMER_SEL_FWRD_8197F(v)) - +#define BIT_BCN_TIMER_SEL_FWRD_8197F(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8197F) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) +#define BITS_BCN_TIMER_SEL_FWRD_8197F \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_8197F \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) \ + ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8197F)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_8197F) +#define BIT_SET_BCN_TIMER_SEL_FWRD_8197F(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) | \ + BIT_BCN_TIMER_SEL_FWRD_8197F(v)) #define BIT_SHIFT_BCN_SPACE_CLINT0_8197F 16 #define BIT_MASK_BCN_SPACE_CLINT0_8197F 0xfff -#define BIT_BCN_SPACE_CLINT0_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8197F) << BIT_SHIFT_BCN_SPACE_CLINT0_8197F) -#define BITS_BCN_SPACE_CLINT0_8197F (BIT_MASK_BCN_SPACE_CLINT0_8197F << BIT_SHIFT_BCN_SPACE_CLINT0_8197F) -#define BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT0_8197F)) -#define BIT_GET_BCN_SPACE_CLINT0_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8197F) & BIT_MASK_BCN_SPACE_CLINT0_8197F) -#define BIT_SET_BCN_SPACE_CLINT0_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) | BIT_BCN_SPACE_CLINT0_8197F(v)) - +#define BIT_BCN_SPACE_CLINT0_8197F(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT0_8197F) \ + << BIT_SHIFT_BCN_SPACE_CLINT0_8197F) +#define BITS_BCN_SPACE_CLINT0_8197F \ + (BIT_MASK_BCN_SPACE_CLINT0_8197F << BIT_SHIFT_BCN_SPACE_CLINT0_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT0_8197F)) +#define BIT_GET_BCN_SPACE_CLINT0_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8197F) & \ + BIT_MASK_BCN_SPACE_CLINT0_8197F) +#define BIT_SET_BCN_SPACE_CLINT0_8197F(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) | BIT_BCN_SPACE_CLINT0_8197F(v)) #define BIT_SHIFT_BCN_SPACE0_8197F 0 #define BIT_MASK_BCN_SPACE0_8197F 0xffff -#define BIT_BCN_SPACE0_8197F(x) (((x) & BIT_MASK_BCN_SPACE0_8197F) << BIT_SHIFT_BCN_SPACE0_8197F) -#define BITS_BCN_SPACE0_8197F (BIT_MASK_BCN_SPACE0_8197F << BIT_SHIFT_BCN_SPACE0_8197F) +#define BIT_BCN_SPACE0_8197F(x) \ + (((x) & BIT_MASK_BCN_SPACE0_8197F) << BIT_SHIFT_BCN_SPACE0_8197F) +#define BITS_BCN_SPACE0_8197F \ + (BIT_MASK_BCN_SPACE0_8197F << BIT_SHIFT_BCN_SPACE0_8197F) #define BIT_CLEAR_BCN_SPACE0_8197F(x) ((x) & (~BITS_BCN_SPACE0_8197F)) -#define BIT_GET_BCN_SPACE0_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8197F) & BIT_MASK_BCN_SPACE0_8197F) -#define BIT_SET_BCN_SPACE0_8197F(x, v) (BIT_CLEAR_BCN_SPACE0_8197F(x) | BIT_BCN_SPACE0_8197F(v)) - +#define BIT_GET_BCN_SPACE0_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE0_8197F) & BIT_MASK_BCN_SPACE0_8197F) +#define BIT_SET_BCN_SPACE0_8197F(x, v) \ + (BIT_CLEAR_BCN_SPACE0_8197F(x) | BIT_BCN_SPACE0_8197F(v)) /* 2 REG_DRVERLYINT_8197F */ #define BIT_SHIFT_DRVERLYITV_8197F 0 #define BIT_MASK_DRVERLYITV_8197F 0xff -#define BIT_DRVERLYITV_8197F(x) (((x) & BIT_MASK_DRVERLYITV_8197F) << BIT_SHIFT_DRVERLYITV_8197F) -#define BITS_DRVERLYITV_8197F (BIT_MASK_DRVERLYITV_8197F << BIT_SHIFT_DRVERLYITV_8197F) +#define BIT_DRVERLYITV_8197F(x) \ + (((x) & BIT_MASK_DRVERLYITV_8197F) << BIT_SHIFT_DRVERLYITV_8197F) +#define BITS_DRVERLYITV_8197F \ + (BIT_MASK_DRVERLYITV_8197F << BIT_SHIFT_DRVERLYITV_8197F) #define BIT_CLEAR_DRVERLYITV_8197F(x) ((x) & (~BITS_DRVERLYITV_8197F)) -#define BIT_GET_DRVERLYITV_8197F(x) (((x) >> BIT_SHIFT_DRVERLYITV_8197F) & BIT_MASK_DRVERLYITV_8197F) -#define BIT_SET_DRVERLYITV_8197F(x, v) (BIT_CLEAR_DRVERLYITV_8197F(x) | BIT_DRVERLYITV_8197F(v)) - +#define BIT_GET_DRVERLYITV_8197F(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV_8197F) & BIT_MASK_DRVERLYITV_8197F) +#define BIT_SET_DRVERLYITV_8197F(x, v) \ + (BIT_CLEAR_DRVERLYITV_8197F(x) | BIT_DRVERLYITV_8197F(v)) /* 2 REG_BCNDMATIM_8197F */ #define BIT_SHIFT_BCNDMATIM_8197F 0 #define BIT_MASK_BCNDMATIM_8197F 0xff -#define BIT_BCNDMATIM_8197F(x) (((x) & BIT_MASK_BCNDMATIM_8197F) << BIT_SHIFT_BCNDMATIM_8197F) -#define BITS_BCNDMATIM_8197F (BIT_MASK_BCNDMATIM_8197F << BIT_SHIFT_BCNDMATIM_8197F) +#define BIT_BCNDMATIM_8197F(x) \ + (((x) & BIT_MASK_BCNDMATIM_8197F) << BIT_SHIFT_BCNDMATIM_8197F) +#define BITS_BCNDMATIM_8197F \ + (BIT_MASK_BCNDMATIM_8197F << BIT_SHIFT_BCNDMATIM_8197F) #define BIT_CLEAR_BCNDMATIM_8197F(x) ((x) & (~BITS_BCNDMATIM_8197F)) -#define BIT_GET_BCNDMATIM_8197F(x) (((x) >> BIT_SHIFT_BCNDMATIM_8197F) & BIT_MASK_BCNDMATIM_8197F) -#define BIT_SET_BCNDMATIM_8197F(x, v) (BIT_CLEAR_BCNDMATIM_8197F(x) | BIT_BCNDMATIM_8197F(v)) - +#define BIT_GET_BCNDMATIM_8197F(x) \ + (((x) >> BIT_SHIFT_BCNDMATIM_8197F) & BIT_MASK_BCNDMATIM_8197F) +#define BIT_SET_BCNDMATIM_8197F(x, v) \ + (BIT_CLEAR_BCNDMATIM_8197F(x) | BIT_BCNDMATIM_8197F(v)) /* 2 REG_ATIMWND_8197F */ #define BIT_SHIFT_ATIMWND0_8197F 0 #define BIT_MASK_ATIMWND0_8197F 0xffff -#define BIT_ATIMWND0_8197F(x) (((x) & BIT_MASK_ATIMWND0_8197F) << BIT_SHIFT_ATIMWND0_8197F) -#define BITS_ATIMWND0_8197F (BIT_MASK_ATIMWND0_8197F << BIT_SHIFT_ATIMWND0_8197F) +#define BIT_ATIMWND0_8197F(x) \ + (((x) & BIT_MASK_ATIMWND0_8197F) << BIT_SHIFT_ATIMWND0_8197F) +#define BITS_ATIMWND0_8197F \ + (BIT_MASK_ATIMWND0_8197F << BIT_SHIFT_ATIMWND0_8197F) #define BIT_CLEAR_ATIMWND0_8197F(x) ((x) & (~BITS_ATIMWND0_8197F)) -#define BIT_GET_ATIMWND0_8197F(x) (((x) >> BIT_SHIFT_ATIMWND0_8197F) & BIT_MASK_ATIMWND0_8197F) -#define BIT_SET_ATIMWND0_8197F(x, v) (BIT_CLEAR_ATIMWND0_8197F(x) | BIT_ATIMWND0_8197F(v)) - +#define BIT_GET_ATIMWND0_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND0_8197F) & BIT_MASK_ATIMWND0_8197F) +#define BIT_SET_ATIMWND0_8197F(x, v) \ + (BIT_CLEAR_ATIMWND0_8197F(x) | BIT_ATIMWND0_8197F(v)) /* 2 REG_USTIME_TSF_8197F */ #define BIT_SHIFT_USTIME_TSF_V1_8197F 0 #define BIT_MASK_USTIME_TSF_V1_8197F 0xff -#define BIT_USTIME_TSF_V1_8197F(x) (((x) & BIT_MASK_USTIME_TSF_V1_8197F) << BIT_SHIFT_USTIME_TSF_V1_8197F) -#define BITS_USTIME_TSF_V1_8197F (BIT_MASK_USTIME_TSF_V1_8197F << BIT_SHIFT_USTIME_TSF_V1_8197F) +#define BIT_USTIME_TSF_V1_8197F(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1_8197F) << BIT_SHIFT_USTIME_TSF_V1_8197F) +#define BITS_USTIME_TSF_V1_8197F \ + (BIT_MASK_USTIME_TSF_V1_8197F << BIT_SHIFT_USTIME_TSF_V1_8197F) #define BIT_CLEAR_USTIME_TSF_V1_8197F(x) ((x) & (~BITS_USTIME_TSF_V1_8197F)) -#define BIT_GET_USTIME_TSF_V1_8197F(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8197F) & BIT_MASK_USTIME_TSF_V1_8197F) -#define BIT_SET_USTIME_TSF_V1_8197F(x, v) (BIT_CLEAR_USTIME_TSF_V1_8197F(x) | BIT_USTIME_TSF_V1_8197F(v)) - +#define BIT_GET_USTIME_TSF_V1_8197F(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1_8197F) & BIT_MASK_USTIME_TSF_V1_8197F) +#define BIT_SET_USTIME_TSF_V1_8197F(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1_8197F(x) | BIT_USTIME_TSF_V1_8197F(v)) /* 2 REG_BCN_MAX_ERR_8197F */ #define BIT_SHIFT_BCN_MAX_ERR_8197F 0 #define BIT_MASK_BCN_MAX_ERR_8197F 0xff -#define BIT_BCN_MAX_ERR_8197F(x) (((x) & BIT_MASK_BCN_MAX_ERR_8197F) << BIT_SHIFT_BCN_MAX_ERR_8197F) -#define BITS_BCN_MAX_ERR_8197F (BIT_MASK_BCN_MAX_ERR_8197F << BIT_SHIFT_BCN_MAX_ERR_8197F) +#define BIT_BCN_MAX_ERR_8197F(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR_8197F) << BIT_SHIFT_BCN_MAX_ERR_8197F) +#define BITS_BCN_MAX_ERR_8197F \ + (BIT_MASK_BCN_MAX_ERR_8197F << BIT_SHIFT_BCN_MAX_ERR_8197F) #define BIT_CLEAR_BCN_MAX_ERR_8197F(x) ((x) & (~BITS_BCN_MAX_ERR_8197F)) -#define BIT_GET_BCN_MAX_ERR_8197F(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8197F) & BIT_MASK_BCN_MAX_ERR_8197F) -#define BIT_SET_BCN_MAX_ERR_8197F(x, v) (BIT_CLEAR_BCN_MAX_ERR_8197F(x) | BIT_BCN_MAX_ERR_8197F(v)) - +#define BIT_GET_BCN_MAX_ERR_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR_8197F) & BIT_MASK_BCN_MAX_ERR_8197F) +#define BIT_SET_BCN_MAX_ERR_8197F(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR_8197F(x) | BIT_BCN_MAX_ERR_8197F(v)) /* 2 REG_RXTSF_OFFSET_CCK_8197F */ #define BIT_SHIFT_CCK_RXTSF_OFFSET_8197F 0 #define BIT_MASK_CCK_RXTSF_OFFSET_8197F 0xff -#define BIT_CCK_RXTSF_OFFSET_8197F(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8197F) << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) -#define BITS_CCK_RXTSF_OFFSET_8197F (BIT_MASK_CCK_RXTSF_OFFSET_8197F << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) -#define BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) ((x) & (~BITS_CCK_RXTSF_OFFSET_8197F)) -#define BIT_GET_CCK_RXTSF_OFFSET_8197F(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) & BIT_MASK_CCK_RXTSF_OFFSET_8197F) -#define BIT_SET_CCK_RXTSF_OFFSET_8197F(x, v) (BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) | BIT_CCK_RXTSF_OFFSET_8197F(v)) - +#define BIT_CCK_RXTSF_OFFSET_8197F(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8197F) \ + << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) +#define BITS_CCK_RXTSF_OFFSET_8197F \ + (BIT_MASK_CCK_RXTSF_OFFSET_8197F << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) +#define BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) \ + ((x) & (~BITS_CCK_RXTSF_OFFSET_8197F)) +#define BIT_GET_CCK_RXTSF_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) & \ + BIT_MASK_CCK_RXTSF_OFFSET_8197F) +#define BIT_SET_CCK_RXTSF_OFFSET_8197F(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) | BIT_CCK_RXTSF_OFFSET_8197F(v)) /* 2 REG_RXTSF_OFFSET_OFDM_8197F */ #define BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F 0 #define BIT_MASK_OFDM_RXTSF_OFFSET_8197F 0xff -#define BIT_OFDM_RXTSF_OFFSET_8197F(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8197F) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) -#define BITS_OFDM_RXTSF_OFFSET_8197F (BIT_MASK_OFDM_RXTSF_OFFSET_8197F << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) -#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) ((x) & (~BITS_OFDM_RXTSF_OFFSET_8197F)) -#define BIT_GET_OFDM_RXTSF_OFFSET_8197F(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) & BIT_MASK_OFDM_RXTSF_OFFSET_8197F) -#define BIT_SET_OFDM_RXTSF_OFFSET_8197F(x, v) (BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) | BIT_OFDM_RXTSF_OFFSET_8197F(v)) - +#define BIT_OFDM_RXTSF_OFFSET_8197F(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8197F) \ + << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) +#define BITS_OFDM_RXTSF_OFFSET_8197F \ + (BIT_MASK_OFDM_RXTSF_OFFSET_8197F << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) \ + ((x) & (~BITS_OFDM_RXTSF_OFFSET_8197F)) +#define BIT_GET_OFDM_RXTSF_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) & \ + BIT_MASK_OFDM_RXTSF_OFFSET_8197F) +#define BIT_SET_OFDM_RXTSF_OFFSET_8197F(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) | BIT_OFDM_RXTSF_OFFSET_8197F(v)) /* 2 REG_TSFTR_8197F */ #define BIT_SHIFT_TSF_TIMER_8197F 0 #define BIT_MASK_TSF_TIMER_8197F 0xffffffffffffffffL -#define BIT_TSF_TIMER_8197F(x) (((x) & BIT_MASK_TSF_TIMER_8197F) << BIT_SHIFT_TSF_TIMER_8197F) -#define BITS_TSF_TIMER_8197F (BIT_MASK_TSF_TIMER_8197F << BIT_SHIFT_TSF_TIMER_8197F) +#define BIT_TSF_TIMER_8197F(x) \ + (((x) & BIT_MASK_TSF_TIMER_8197F) << BIT_SHIFT_TSF_TIMER_8197F) +#define BITS_TSF_TIMER_8197F \ + (BIT_MASK_TSF_TIMER_8197F << BIT_SHIFT_TSF_TIMER_8197F) #define BIT_CLEAR_TSF_TIMER_8197F(x) ((x) & (~BITS_TSF_TIMER_8197F)) -#define BIT_GET_TSF_TIMER_8197F(x) (((x) >> BIT_SHIFT_TSF_TIMER_8197F) & BIT_MASK_TSF_TIMER_8197F) -#define BIT_SET_TSF_TIMER_8197F(x, v) (BIT_CLEAR_TSF_TIMER_8197F(x) | BIT_TSF_TIMER_8197F(v)) - +#define BIT_GET_TSF_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_8197F) & BIT_MASK_TSF_TIMER_8197F) +#define BIT_SET_TSF_TIMER_8197F(x, v) \ + (BIT_CLEAR_TSF_TIMER_8197F(x) | BIT_TSF_TIMER_8197F(v)) /* 2 REG_FREERUN_CNT_8197F */ #define BIT_SHIFT_FREERUN_CNT_8197F 0 #define BIT_MASK_FREERUN_CNT_8197F 0xffffffffffffffffL -#define BIT_FREERUN_CNT_8197F(x) (((x) & BIT_MASK_FREERUN_CNT_8197F) << BIT_SHIFT_FREERUN_CNT_8197F) -#define BITS_FREERUN_CNT_8197F (BIT_MASK_FREERUN_CNT_8197F << BIT_SHIFT_FREERUN_CNT_8197F) +#define BIT_FREERUN_CNT_8197F(x) \ + (((x) & BIT_MASK_FREERUN_CNT_8197F) << BIT_SHIFT_FREERUN_CNT_8197F) +#define BITS_FREERUN_CNT_8197F \ + (BIT_MASK_FREERUN_CNT_8197F << BIT_SHIFT_FREERUN_CNT_8197F) #define BIT_CLEAR_FREERUN_CNT_8197F(x) ((x) & (~BITS_FREERUN_CNT_8197F)) -#define BIT_GET_FREERUN_CNT_8197F(x) (((x) >> BIT_SHIFT_FREERUN_CNT_8197F) & BIT_MASK_FREERUN_CNT_8197F) -#define BIT_SET_FREERUN_CNT_8197F(x, v) (BIT_CLEAR_FREERUN_CNT_8197F(x) | BIT_FREERUN_CNT_8197F(v)) - +#define BIT_GET_FREERUN_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_8197F) & BIT_MASK_FREERUN_CNT_8197F) +#define BIT_SET_FREERUN_CNT_8197F(x, v) \ + (BIT_CLEAR_FREERUN_CNT_8197F(x) | BIT_FREERUN_CNT_8197F(v)) /* 2 REG_ATIMWND1_8197F */ #define BIT_SHIFT_ATIMWND1_V1_8197F 0 #define BIT_MASK_ATIMWND1_V1_8197F 0xff -#define BIT_ATIMWND1_V1_8197F(x) (((x) & BIT_MASK_ATIMWND1_V1_8197F) << BIT_SHIFT_ATIMWND1_V1_8197F) -#define BITS_ATIMWND1_V1_8197F (BIT_MASK_ATIMWND1_V1_8197F << BIT_SHIFT_ATIMWND1_V1_8197F) +#define BIT_ATIMWND1_V1_8197F(x) \ + (((x) & BIT_MASK_ATIMWND1_V1_8197F) << BIT_SHIFT_ATIMWND1_V1_8197F) +#define BITS_ATIMWND1_V1_8197F \ + (BIT_MASK_ATIMWND1_V1_8197F << BIT_SHIFT_ATIMWND1_V1_8197F) #define BIT_CLEAR_ATIMWND1_V1_8197F(x) ((x) & (~BITS_ATIMWND1_V1_8197F)) -#define BIT_GET_ATIMWND1_V1_8197F(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8197F) & BIT_MASK_ATIMWND1_V1_8197F) -#define BIT_SET_ATIMWND1_V1_8197F(x, v) (BIT_CLEAR_ATIMWND1_V1_8197F(x) | BIT_ATIMWND1_V1_8197F(v)) - +#define BIT_GET_ATIMWND1_V1_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND1_V1_8197F) & BIT_MASK_ATIMWND1_V1_8197F) +#define BIT_SET_ATIMWND1_V1_8197F(x, v) \ + (BIT_CLEAR_ATIMWND1_V1_8197F(x) | BIT_ATIMWND1_V1_8197F(v)) /* 2 REG_TBTT_PROHIBIT_INFRA_8197F */ #define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F 0 #define BIT_MASK_TBTT_PROHIBIT_INFRA_8197F 0xff -#define BIT_TBTT_PROHIBIT_INFRA_8197F(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8197F) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) -#define BITS_TBTT_PROHIBIT_INFRA_8197F (BIT_MASK_TBTT_PROHIBIT_INFRA_8197F << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) -#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8197F)) -#define BIT_GET_TBTT_PROHIBIT_INFRA_8197F(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) & BIT_MASK_TBTT_PROHIBIT_INFRA_8197F) -#define BIT_SET_TBTT_PROHIBIT_INFRA_8197F(x, v) (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) | BIT_TBTT_PROHIBIT_INFRA_8197F(v)) - +#define BIT_TBTT_PROHIBIT_INFRA_8197F(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8197F) \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) +#define BITS_TBTT_PROHIBIT_INFRA_8197F \ + (BIT_MASK_TBTT_PROHIBIT_INFRA_8197F \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) +#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8197F)) +#define BIT_GET_TBTT_PROHIBIT_INFRA_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) & \ + BIT_MASK_TBTT_PROHIBIT_INFRA_8197F) +#define BIT_SET_TBTT_PROHIBIT_INFRA_8197F(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) | \ + BIT_TBTT_PROHIBIT_INFRA_8197F(v)) /* 2 REG_CTWND_8197F */ #define BIT_SHIFT_CTWND_8197F 0 #define BIT_MASK_CTWND_8197F 0xff -#define BIT_CTWND_8197F(x) (((x) & BIT_MASK_CTWND_8197F) << BIT_SHIFT_CTWND_8197F) +#define BIT_CTWND_8197F(x) \ + (((x) & BIT_MASK_CTWND_8197F) << BIT_SHIFT_CTWND_8197F) #define BITS_CTWND_8197F (BIT_MASK_CTWND_8197F << BIT_SHIFT_CTWND_8197F) #define BIT_CLEAR_CTWND_8197F(x) ((x) & (~BITS_CTWND_8197F)) -#define BIT_GET_CTWND_8197F(x) (((x) >> BIT_SHIFT_CTWND_8197F) & BIT_MASK_CTWND_8197F) -#define BIT_SET_CTWND_8197F(x, v) (BIT_CLEAR_CTWND_8197F(x) | BIT_CTWND_8197F(v)) - +#define BIT_GET_CTWND_8197F(x) \ + (((x) >> BIT_SHIFT_CTWND_8197F) & BIT_MASK_CTWND_8197F) +#define BIT_SET_CTWND_8197F(x, v) \ + (BIT_CLEAR_CTWND_8197F(x) | BIT_CTWND_8197F(v)) /* 2 REG_BCNIVLCUNT_8197F */ #define BIT_SHIFT_BCNIVLCUNT_8197F 0 #define BIT_MASK_BCNIVLCUNT_8197F 0x7f -#define BIT_BCNIVLCUNT_8197F(x) (((x) & BIT_MASK_BCNIVLCUNT_8197F) << BIT_SHIFT_BCNIVLCUNT_8197F) -#define BITS_BCNIVLCUNT_8197F (BIT_MASK_BCNIVLCUNT_8197F << BIT_SHIFT_BCNIVLCUNT_8197F) +#define BIT_BCNIVLCUNT_8197F(x) \ + (((x) & BIT_MASK_BCNIVLCUNT_8197F) << BIT_SHIFT_BCNIVLCUNT_8197F) +#define BITS_BCNIVLCUNT_8197F \ + (BIT_MASK_BCNIVLCUNT_8197F << BIT_SHIFT_BCNIVLCUNT_8197F) #define BIT_CLEAR_BCNIVLCUNT_8197F(x) ((x) & (~BITS_BCNIVLCUNT_8197F)) -#define BIT_GET_BCNIVLCUNT_8197F(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8197F) & BIT_MASK_BCNIVLCUNT_8197F) -#define BIT_SET_BCNIVLCUNT_8197F(x, v) (BIT_CLEAR_BCNIVLCUNT_8197F(x) | BIT_BCNIVLCUNT_8197F(v)) - +#define BIT_GET_BCNIVLCUNT_8197F(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT_8197F) & BIT_MASK_BCNIVLCUNT_8197F) +#define BIT_SET_BCNIVLCUNT_8197F(x, v) \ + (BIT_CLEAR_BCNIVLCUNT_8197F(x) | BIT_BCNIVLCUNT_8197F(v)) /* 2 REG_BCNDROPCTRL_8197F */ #define BIT_BEACON_DROP_EN_8197F BIT(7) #define BIT_SHIFT_BEACON_DROP_IVL_8197F 0 #define BIT_MASK_BEACON_DROP_IVL_8197F 0x7f -#define BIT_BEACON_DROP_IVL_8197F(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8197F) << BIT_SHIFT_BEACON_DROP_IVL_8197F) -#define BITS_BEACON_DROP_IVL_8197F (BIT_MASK_BEACON_DROP_IVL_8197F << BIT_SHIFT_BEACON_DROP_IVL_8197F) +#define BIT_BEACON_DROP_IVL_8197F(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL_8197F) \ + << BIT_SHIFT_BEACON_DROP_IVL_8197F) +#define BITS_BEACON_DROP_IVL_8197F \ + (BIT_MASK_BEACON_DROP_IVL_8197F << BIT_SHIFT_BEACON_DROP_IVL_8197F) #define BIT_CLEAR_BEACON_DROP_IVL_8197F(x) ((x) & (~BITS_BEACON_DROP_IVL_8197F)) -#define BIT_GET_BEACON_DROP_IVL_8197F(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8197F) & BIT_MASK_BEACON_DROP_IVL_8197F) -#define BIT_SET_BEACON_DROP_IVL_8197F(x, v) (BIT_CLEAR_BEACON_DROP_IVL_8197F(x) | BIT_BEACON_DROP_IVL_8197F(v)) - +#define BIT_GET_BEACON_DROP_IVL_8197F(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8197F) & \ + BIT_MASK_BEACON_DROP_IVL_8197F) +#define BIT_SET_BEACON_DROP_IVL_8197F(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL_8197F(x) | BIT_BEACON_DROP_IVL_8197F(v)) /* 2 REG_HGQ_TIMEOUT_PERIOD_8197F */ #define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F 0 #define BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F 0xff -#define BIT_HGQ_TIMEOUT_PERIOD_8197F(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) -#define BITS_HGQ_TIMEOUT_PERIOD_8197F (BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) -#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8197F)) -#define BIT_GET_HGQ_TIMEOUT_PERIOD_8197F(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F) -#define BIT_SET_HGQ_TIMEOUT_PERIOD_8197F(x, v) (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) | BIT_HGQ_TIMEOUT_PERIOD_8197F(v)) - +#define BIT_HGQ_TIMEOUT_PERIOD_8197F(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F) \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) +#define BITS_HGQ_TIMEOUT_PERIOD_8197F \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) \ + ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8197F)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8197F(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) & \ + BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F) +#define BIT_SET_HGQ_TIMEOUT_PERIOD_8197F(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) | \ + BIT_HGQ_TIMEOUT_PERIOD_8197F(v)) /* 2 REG_TXCMD_TIMEOUT_PERIOD_8197F */ #define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F 0 #define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F 0xff -#define BIT_TXCMD_TIMEOUT_PERIOD_8197F(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) -#define BITS_TXCMD_TIMEOUT_PERIOD_8197F (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) -#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8197F)) -#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8197F(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F) -#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8197F(x, v) (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) | BIT_TXCMD_TIMEOUT_PERIOD_8197F(v)) - +#define BIT_TXCMD_TIMEOUT_PERIOD_8197F(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) +#define BITS_TXCMD_TIMEOUT_PERIOD_8197F \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) \ + ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8197F)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8197F(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8197F(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) | \ + BIT_TXCMD_TIMEOUT_PERIOD_8197F(v)) /* 2 REG_MISC_CTRL_8197F */ #define BIT_DIS_MARK_TSF_US_8197F BIT(7) @@ -9146,12 +11958,18 @@ #define BIT_SHIFT_DIS_SECONDARY_CCA_8197F 0 #define BIT_MASK_DIS_SECONDARY_CCA_8197F 0x3 -#define BIT_DIS_SECONDARY_CCA_8197F(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8197F) << BIT_SHIFT_DIS_SECONDARY_CCA_8197F) -#define BITS_DIS_SECONDARY_CCA_8197F (BIT_MASK_DIS_SECONDARY_CCA_8197F << BIT_SHIFT_DIS_SECONDARY_CCA_8197F) -#define BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) ((x) & (~BITS_DIS_SECONDARY_CCA_8197F)) -#define BIT_GET_DIS_SECONDARY_CCA_8197F(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8197F) & BIT_MASK_DIS_SECONDARY_CCA_8197F) -#define BIT_SET_DIS_SECONDARY_CCA_8197F(x, v) (BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) | BIT_DIS_SECONDARY_CCA_8197F(v)) - +#define BIT_DIS_SECONDARY_CCA_8197F(x) \ + (((x) & BIT_MASK_DIS_SECONDARY_CCA_8197F) \ + << BIT_SHIFT_DIS_SECONDARY_CCA_8197F) +#define BITS_DIS_SECONDARY_CCA_8197F \ + (BIT_MASK_DIS_SECONDARY_CCA_8197F << BIT_SHIFT_DIS_SECONDARY_CCA_8197F) +#define BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) \ + ((x) & (~BITS_DIS_SECONDARY_CCA_8197F)) +#define BIT_GET_DIS_SECONDARY_CCA_8197F(x) \ + (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8197F) & \ + BIT_MASK_DIS_SECONDARY_CCA_8197F) +#define BIT_SET_DIS_SECONDARY_CCA_8197F(x, v) \ + (BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) | BIT_DIS_SECONDARY_CCA_8197F(v)) /* 2 REG_BCN_CTRL_CLINT1_8197F */ #define BIT_CLI1_DIS_RX_BSSID_FIT_8197F BIT(6) @@ -9183,12 +12001,15 @@ #define BIT_SHIFT_PORT_SEL_8197F 0 #define BIT_MASK_PORT_SEL_8197F 0x7 -#define BIT_PORT_SEL_8197F(x) (((x) & BIT_MASK_PORT_SEL_8197F) << BIT_SHIFT_PORT_SEL_8197F) -#define BITS_PORT_SEL_8197F (BIT_MASK_PORT_SEL_8197F << BIT_SHIFT_PORT_SEL_8197F) +#define BIT_PORT_SEL_8197F(x) \ + (((x) & BIT_MASK_PORT_SEL_8197F) << BIT_SHIFT_PORT_SEL_8197F) +#define BITS_PORT_SEL_8197F \ + (BIT_MASK_PORT_SEL_8197F << BIT_SHIFT_PORT_SEL_8197F) #define BIT_CLEAR_PORT_SEL_8197F(x) ((x) & (~BITS_PORT_SEL_8197F)) -#define BIT_GET_PORT_SEL_8197F(x) (((x) >> BIT_SHIFT_PORT_SEL_8197F) & BIT_MASK_PORT_SEL_8197F) -#define BIT_SET_PORT_SEL_8197F(x, v) (BIT_CLEAR_PORT_SEL_8197F(x) | BIT_PORT_SEL_8197F(v)) - +#define BIT_GET_PORT_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PORT_SEL_8197F) & BIT_MASK_PORT_SEL_8197F) +#define BIT_SET_PORT_SEL_8197F(x, v) \ + (BIT_CLEAR_PORT_SEL_8197F(x) | BIT_PORT_SEL_8197F(v)) /* 2 REG_P2PPS1_SPEC_STATE_8197F */ #define BIT_P2P1_SPEC_POWER_STATE_8197F BIT(7) @@ -9234,56 +12055,71 @@ #define BIT_SHIFT_PSTIMER0_INT_8197F 5 #define BIT_MASK_PSTIMER0_INT_8197F 0x7ffffff -#define BIT_PSTIMER0_INT_8197F(x) (((x) & BIT_MASK_PSTIMER0_INT_8197F) << BIT_SHIFT_PSTIMER0_INT_8197F) -#define BITS_PSTIMER0_INT_8197F (BIT_MASK_PSTIMER0_INT_8197F << BIT_SHIFT_PSTIMER0_INT_8197F) +#define BIT_PSTIMER0_INT_8197F(x) \ + (((x) & BIT_MASK_PSTIMER0_INT_8197F) << BIT_SHIFT_PSTIMER0_INT_8197F) +#define BITS_PSTIMER0_INT_8197F \ + (BIT_MASK_PSTIMER0_INT_8197F << BIT_SHIFT_PSTIMER0_INT_8197F) #define BIT_CLEAR_PSTIMER0_INT_8197F(x) ((x) & (~BITS_PSTIMER0_INT_8197F)) -#define BIT_GET_PSTIMER0_INT_8197F(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8197F) & BIT_MASK_PSTIMER0_INT_8197F) -#define BIT_SET_PSTIMER0_INT_8197F(x, v) (BIT_CLEAR_PSTIMER0_INT_8197F(x) | BIT_PSTIMER0_INT_8197F(v)) - +#define BIT_GET_PSTIMER0_INT_8197F(x) \ + (((x) >> BIT_SHIFT_PSTIMER0_INT_8197F) & BIT_MASK_PSTIMER0_INT_8197F) +#define BIT_SET_PSTIMER0_INT_8197F(x, v) \ + (BIT_CLEAR_PSTIMER0_INT_8197F(x) | BIT_PSTIMER0_INT_8197F(v)) /* 2 REG_PS_TIMER1_8197F */ #define BIT_SHIFT_PSTIMER1_INT_8197F 5 #define BIT_MASK_PSTIMER1_INT_8197F 0x7ffffff -#define BIT_PSTIMER1_INT_8197F(x) (((x) & BIT_MASK_PSTIMER1_INT_8197F) << BIT_SHIFT_PSTIMER1_INT_8197F) -#define BITS_PSTIMER1_INT_8197F (BIT_MASK_PSTIMER1_INT_8197F << BIT_SHIFT_PSTIMER1_INT_8197F) +#define BIT_PSTIMER1_INT_8197F(x) \ + (((x) & BIT_MASK_PSTIMER1_INT_8197F) << BIT_SHIFT_PSTIMER1_INT_8197F) +#define BITS_PSTIMER1_INT_8197F \ + (BIT_MASK_PSTIMER1_INT_8197F << BIT_SHIFT_PSTIMER1_INT_8197F) #define BIT_CLEAR_PSTIMER1_INT_8197F(x) ((x) & (~BITS_PSTIMER1_INT_8197F)) -#define BIT_GET_PSTIMER1_INT_8197F(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8197F) & BIT_MASK_PSTIMER1_INT_8197F) -#define BIT_SET_PSTIMER1_INT_8197F(x, v) (BIT_CLEAR_PSTIMER1_INT_8197F(x) | BIT_PSTIMER1_INT_8197F(v)) - +#define BIT_GET_PSTIMER1_INT_8197F(x) \ + (((x) >> BIT_SHIFT_PSTIMER1_INT_8197F) & BIT_MASK_PSTIMER1_INT_8197F) +#define BIT_SET_PSTIMER1_INT_8197F(x, v) \ + (BIT_CLEAR_PSTIMER1_INT_8197F(x) | BIT_PSTIMER1_INT_8197F(v)) /* 2 REG_PS_TIMER2_8197F */ #define BIT_SHIFT_PSTIMER2_INT_8197F 5 #define BIT_MASK_PSTIMER2_INT_8197F 0x7ffffff -#define BIT_PSTIMER2_INT_8197F(x) (((x) & BIT_MASK_PSTIMER2_INT_8197F) << BIT_SHIFT_PSTIMER2_INT_8197F) -#define BITS_PSTIMER2_INT_8197F (BIT_MASK_PSTIMER2_INT_8197F << BIT_SHIFT_PSTIMER2_INT_8197F) +#define BIT_PSTIMER2_INT_8197F(x) \ + (((x) & BIT_MASK_PSTIMER2_INT_8197F) << BIT_SHIFT_PSTIMER2_INT_8197F) +#define BITS_PSTIMER2_INT_8197F \ + (BIT_MASK_PSTIMER2_INT_8197F << BIT_SHIFT_PSTIMER2_INT_8197F) #define BIT_CLEAR_PSTIMER2_INT_8197F(x) ((x) & (~BITS_PSTIMER2_INT_8197F)) -#define BIT_GET_PSTIMER2_INT_8197F(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8197F) & BIT_MASK_PSTIMER2_INT_8197F) -#define BIT_SET_PSTIMER2_INT_8197F(x, v) (BIT_CLEAR_PSTIMER2_INT_8197F(x) | BIT_PSTIMER2_INT_8197F(v)) - +#define BIT_GET_PSTIMER2_INT_8197F(x) \ + (((x) >> BIT_SHIFT_PSTIMER2_INT_8197F) & BIT_MASK_PSTIMER2_INT_8197F) +#define BIT_SET_PSTIMER2_INT_8197F(x, v) \ + (BIT_CLEAR_PSTIMER2_INT_8197F(x) | BIT_PSTIMER2_INT_8197F(v)) /* 2 REG_TBTT_CTN_AREA_8197F */ #define BIT_SHIFT_TBTT_CTN_AREA_8197F 0 #define BIT_MASK_TBTT_CTN_AREA_8197F 0xff -#define BIT_TBTT_CTN_AREA_8197F(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8197F) << BIT_SHIFT_TBTT_CTN_AREA_8197F) -#define BITS_TBTT_CTN_AREA_8197F (BIT_MASK_TBTT_CTN_AREA_8197F << BIT_SHIFT_TBTT_CTN_AREA_8197F) +#define BIT_TBTT_CTN_AREA_8197F(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA_8197F) << BIT_SHIFT_TBTT_CTN_AREA_8197F) +#define BITS_TBTT_CTN_AREA_8197F \ + (BIT_MASK_TBTT_CTN_AREA_8197F << BIT_SHIFT_TBTT_CTN_AREA_8197F) #define BIT_CLEAR_TBTT_CTN_AREA_8197F(x) ((x) & (~BITS_TBTT_CTN_AREA_8197F)) -#define BIT_GET_TBTT_CTN_AREA_8197F(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8197F) & BIT_MASK_TBTT_CTN_AREA_8197F) -#define BIT_SET_TBTT_CTN_AREA_8197F(x, v) (BIT_CLEAR_TBTT_CTN_AREA_8197F(x) | BIT_TBTT_CTN_AREA_8197F(v)) - +#define BIT_GET_TBTT_CTN_AREA_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8197F) & BIT_MASK_TBTT_CTN_AREA_8197F) +#define BIT_SET_TBTT_CTN_AREA_8197F(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA_8197F(x) | BIT_TBTT_CTN_AREA_8197F(v)) /* 2 REG_FORCE_BCN_IFS_8197F */ #define BIT_SHIFT_FORCE_BCN_IFS_8197F 0 #define BIT_MASK_FORCE_BCN_IFS_8197F 0xff -#define BIT_FORCE_BCN_IFS_8197F(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8197F) << BIT_SHIFT_FORCE_BCN_IFS_8197F) -#define BITS_FORCE_BCN_IFS_8197F (BIT_MASK_FORCE_BCN_IFS_8197F << BIT_SHIFT_FORCE_BCN_IFS_8197F) +#define BIT_FORCE_BCN_IFS_8197F(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS_8197F) << BIT_SHIFT_FORCE_BCN_IFS_8197F) +#define BITS_FORCE_BCN_IFS_8197F \ + (BIT_MASK_FORCE_BCN_IFS_8197F << BIT_SHIFT_FORCE_BCN_IFS_8197F) #define BIT_CLEAR_FORCE_BCN_IFS_8197F(x) ((x) & (~BITS_FORCE_BCN_IFS_8197F)) -#define BIT_GET_FORCE_BCN_IFS_8197F(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8197F) & BIT_MASK_FORCE_BCN_IFS_8197F) -#define BIT_SET_FORCE_BCN_IFS_8197F(x, v) (BIT_CLEAR_FORCE_BCN_IFS_8197F(x) | BIT_FORCE_BCN_IFS_8197F(v)) - +#define BIT_GET_FORCE_BCN_IFS_8197F(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8197F) & BIT_MASK_FORCE_BCN_IFS_8197F) +#define BIT_SET_FORCE_BCN_IFS_8197F(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS_8197F(x) | BIT_FORCE_BCN_IFS_8197F(v)) /* 2 REG_TXOP_MIN_8197F */ #define BIT_NAV_BLK_HGQ_8197F BIT(15) @@ -9291,23 +12127,29 @@ #define BIT_SHIFT_TXOP_MIN_8197F 0 #define BIT_MASK_TXOP_MIN_8197F 0x3fff -#define BIT_TXOP_MIN_8197F(x) (((x) & BIT_MASK_TXOP_MIN_8197F) << BIT_SHIFT_TXOP_MIN_8197F) -#define BITS_TXOP_MIN_8197F (BIT_MASK_TXOP_MIN_8197F << BIT_SHIFT_TXOP_MIN_8197F) +#define BIT_TXOP_MIN_8197F(x) \ + (((x) & BIT_MASK_TXOP_MIN_8197F) << BIT_SHIFT_TXOP_MIN_8197F) +#define BITS_TXOP_MIN_8197F \ + (BIT_MASK_TXOP_MIN_8197F << BIT_SHIFT_TXOP_MIN_8197F) #define BIT_CLEAR_TXOP_MIN_8197F(x) ((x) & (~BITS_TXOP_MIN_8197F)) -#define BIT_GET_TXOP_MIN_8197F(x) (((x) >> BIT_SHIFT_TXOP_MIN_8197F) & BIT_MASK_TXOP_MIN_8197F) -#define BIT_SET_TXOP_MIN_8197F(x, v) (BIT_CLEAR_TXOP_MIN_8197F(x) | BIT_TXOP_MIN_8197F(v)) - +#define BIT_GET_TXOP_MIN_8197F(x) \ + (((x) >> BIT_SHIFT_TXOP_MIN_8197F) & BIT_MASK_TXOP_MIN_8197F) +#define BIT_SET_TXOP_MIN_8197F(x, v) \ + (BIT_CLEAR_TXOP_MIN_8197F(x) | BIT_TXOP_MIN_8197F(v)) /* 2 REG_PRE_BKF_TIME_8197F */ #define BIT_SHIFT_PRE_BKF_TIME_8197F 0 #define BIT_MASK_PRE_BKF_TIME_8197F 0xff -#define BIT_PRE_BKF_TIME_8197F(x) (((x) & BIT_MASK_PRE_BKF_TIME_8197F) << BIT_SHIFT_PRE_BKF_TIME_8197F) -#define BITS_PRE_BKF_TIME_8197F (BIT_MASK_PRE_BKF_TIME_8197F << BIT_SHIFT_PRE_BKF_TIME_8197F) +#define BIT_PRE_BKF_TIME_8197F(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME_8197F) << BIT_SHIFT_PRE_BKF_TIME_8197F) +#define BITS_PRE_BKF_TIME_8197F \ + (BIT_MASK_PRE_BKF_TIME_8197F << BIT_SHIFT_PRE_BKF_TIME_8197F) #define BIT_CLEAR_PRE_BKF_TIME_8197F(x) ((x) & (~BITS_PRE_BKF_TIME_8197F)) -#define BIT_GET_PRE_BKF_TIME_8197F(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8197F) & BIT_MASK_PRE_BKF_TIME_8197F) -#define BIT_SET_PRE_BKF_TIME_8197F(x, v) (BIT_CLEAR_PRE_BKF_TIME_8197F(x) | BIT_PRE_BKF_TIME_8197F(v)) - +#define BIT_GET_PRE_BKF_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME_8197F) & BIT_MASK_PRE_BKF_TIME_8197F) +#define BIT_SET_PRE_BKF_TIME_8197F(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME_8197F(x) | BIT_PRE_BKF_TIME_8197F(v)) /* 2 REG_CROSS_TXOP_CTRL_8197F */ #define BIT_DTIM_BYPASS_8197F BIT(2) @@ -9319,48 +12161,80 @@ #define BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F 0x7f -#define BIT_TBTT_INT_SHIFT_CLI0_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) -#define BITS_TBTT_INT_SHIFT_CLI0_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) -#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI0_8197F)) -#define BIT_GET_TBTT_INT_SHIFT_CLI0_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F) -#define BIT_SET_TBTT_INT_SHIFT_CLI0_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) | BIT_TBTT_INT_SHIFT_CLI0_8197F(v)) - +#define BIT_TBTT_INT_SHIFT_CLI0_8197F(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F) \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) +#define BITS_TBTT_INT_SHIFT_CLI0_8197F \ + (BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) \ + ((x) & (~BITS_TBTT_INT_SHIFT_CLI0_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI0_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) & \ + BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI0_8197F(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) | \ + BIT_TBTT_INT_SHIFT_CLI0_8197F(v)) /* 2 REG_TBTT_INT_SHIFT_CLI1_8197F */ #define BIT_TBTT_INT_SHIFT_DIR_CLI1_8197F BIT(7) #define BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F 0x7f -#define BIT_TBTT_INT_SHIFT_CLI1_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) -#define BITS_TBTT_INT_SHIFT_CLI1_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) -#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI1_8197F)) -#define BIT_GET_TBTT_INT_SHIFT_CLI1_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F) -#define BIT_SET_TBTT_INT_SHIFT_CLI1_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) | BIT_TBTT_INT_SHIFT_CLI1_8197F(v)) - +#define BIT_TBTT_INT_SHIFT_CLI1_8197F(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F) \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) +#define BITS_TBTT_INT_SHIFT_CLI1_8197F \ + (BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) \ + ((x) & (~BITS_TBTT_INT_SHIFT_CLI1_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI1_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) & \ + BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI1_8197F(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) | \ + BIT_TBTT_INT_SHIFT_CLI1_8197F(v)) /* 2 REG_TBTT_INT_SHIFT_CLI2_8197F */ #define BIT_TBTT_INT_SHIFT_DIR_CLI2_8197F BIT(7) #define BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F 0x7f -#define BIT_TBTT_INT_SHIFT_CLI2_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) -#define BITS_TBTT_INT_SHIFT_CLI2_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) -#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI2_8197F)) -#define BIT_GET_TBTT_INT_SHIFT_CLI2_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F) -#define BIT_SET_TBTT_INT_SHIFT_CLI2_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) | BIT_TBTT_INT_SHIFT_CLI2_8197F(v)) - +#define BIT_TBTT_INT_SHIFT_CLI2_8197F(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F) \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) +#define BITS_TBTT_INT_SHIFT_CLI2_8197F \ + (BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) \ + ((x) & (~BITS_TBTT_INT_SHIFT_CLI2_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI2_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) & \ + BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI2_8197F(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) | \ + BIT_TBTT_INT_SHIFT_CLI2_8197F(v)) /* 2 REG_TBTT_INT_SHIFT_CLI3_8197F */ #define BIT_TBTT_INT_SHIFT_DIR_CLI3_8197F BIT(7) #define BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F 0 #define BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F 0x7f -#define BIT_TBTT_INT_SHIFT_CLI3_8197F(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) -#define BITS_TBTT_INT_SHIFT_CLI3_8197F (BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) -#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI3_8197F)) -#define BIT_GET_TBTT_INT_SHIFT_CLI3_8197F(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) & BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F) -#define BIT_SET_TBTT_INT_SHIFT_CLI3_8197F(x, v) (BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) | BIT_TBTT_INT_SHIFT_CLI3_8197F(v)) - +#define BIT_TBTT_INT_SHIFT_CLI3_8197F(x) \ + (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F) \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) +#define BITS_TBTT_INT_SHIFT_CLI3_8197F \ + (BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F \ + << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) +#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) \ + ((x) & (~BITS_TBTT_INT_SHIFT_CLI3_8197F)) +#define BIT_GET_TBTT_INT_SHIFT_CLI3_8197F(x) \ + (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) & \ + BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F) +#define BIT_SET_TBTT_INT_SHIFT_CLI3_8197F(x, v) \ + (BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) | \ + BIT_TBTT_INT_SHIFT_CLI3_8197F(v)) /* 2 REG_TBTT_INT_SHIFT_ENABLE_8197F */ #define BIT_EN_TBTT_RTY_8197F BIT(1) @@ -9370,78 +12244,99 @@ #define BIT_SHIFT_ATIMWND2_8197F 0 #define BIT_MASK_ATIMWND2_8197F 0xff -#define BIT_ATIMWND2_8197F(x) (((x) & BIT_MASK_ATIMWND2_8197F) << BIT_SHIFT_ATIMWND2_8197F) -#define BITS_ATIMWND2_8197F (BIT_MASK_ATIMWND2_8197F << BIT_SHIFT_ATIMWND2_8197F) +#define BIT_ATIMWND2_8197F(x) \ + (((x) & BIT_MASK_ATIMWND2_8197F) << BIT_SHIFT_ATIMWND2_8197F) +#define BITS_ATIMWND2_8197F \ + (BIT_MASK_ATIMWND2_8197F << BIT_SHIFT_ATIMWND2_8197F) #define BIT_CLEAR_ATIMWND2_8197F(x) ((x) & (~BITS_ATIMWND2_8197F)) -#define BIT_GET_ATIMWND2_8197F(x) (((x) >> BIT_SHIFT_ATIMWND2_8197F) & BIT_MASK_ATIMWND2_8197F) -#define BIT_SET_ATIMWND2_8197F(x, v) (BIT_CLEAR_ATIMWND2_8197F(x) | BIT_ATIMWND2_8197F(v)) - +#define BIT_GET_ATIMWND2_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND2_8197F) & BIT_MASK_ATIMWND2_8197F) +#define BIT_SET_ATIMWND2_8197F(x, v) \ + (BIT_CLEAR_ATIMWND2_8197F(x) | BIT_ATIMWND2_8197F(v)) /* 2 REG_ATIMWND3_8197F */ #define BIT_SHIFT_ATIMWND3_8197F 0 #define BIT_MASK_ATIMWND3_8197F 0xff -#define BIT_ATIMWND3_8197F(x) (((x) & BIT_MASK_ATIMWND3_8197F) << BIT_SHIFT_ATIMWND3_8197F) -#define BITS_ATIMWND3_8197F (BIT_MASK_ATIMWND3_8197F << BIT_SHIFT_ATIMWND3_8197F) +#define BIT_ATIMWND3_8197F(x) \ + (((x) & BIT_MASK_ATIMWND3_8197F) << BIT_SHIFT_ATIMWND3_8197F) +#define BITS_ATIMWND3_8197F \ + (BIT_MASK_ATIMWND3_8197F << BIT_SHIFT_ATIMWND3_8197F) #define BIT_CLEAR_ATIMWND3_8197F(x) ((x) & (~BITS_ATIMWND3_8197F)) -#define BIT_GET_ATIMWND3_8197F(x) (((x) >> BIT_SHIFT_ATIMWND3_8197F) & BIT_MASK_ATIMWND3_8197F) -#define BIT_SET_ATIMWND3_8197F(x, v) (BIT_CLEAR_ATIMWND3_8197F(x) | BIT_ATIMWND3_8197F(v)) - +#define BIT_GET_ATIMWND3_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND3_8197F) & BIT_MASK_ATIMWND3_8197F) +#define BIT_SET_ATIMWND3_8197F(x, v) \ + (BIT_CLEAR_ATIMWND3_8197F(x) | BIT_ATIMWND3_8197F(v)) /* 2 REG_ATIMWND4_8197F */ #define BIT_SHIFT_ATIMWND4_8197F 0 #define BIT_MASK_ATIMWND4_8197F 0xff -#define BIT_ATIMWND4_8197F(x) (((x) & BIT_MASK_ATIMWND4_8197F) << BIT_SHIFT_ATIMWND4_8197F) -#define BITS_ATIMWND4_8197F (BIT_MASK_ATIMWND4_8197F << BIT_SHIFT_ATIMWND4_8197F) +#define BIT_ATIMWND4_8197F(x) \ + (((x) & BIT_MASK_ATIMWND4_8197F) << BIT_SHIFT_ATIMWND4_8197F) +#define BITS_ATIMWND4_8197F \ + (BIT_MASK_ATIMWND4_8197F << BIT_SHIFT_ATIMWND4_8197F) #define BIT_CLEAR_ATIMWND4_8197F(x) ((x) & (~BITS_ATIMWND4_8197F)) -#define BIT_GET_ATIMWND4_8197F(x) (((x) >> BIT_SHIFT_ATIMWND4_8197F) & BIT_MASK_ATIMWND4_8197F) -#define BIT_SET_ATIMWND4_8197F(x, v) (BIT_CLEAR_ATIMWND4_8197F(x) | BIT_ATIMWND4_8197F(v)) - +#define BIT_GET_ATIMWND4_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND4_8197F) & BIT_MASK_ATIMWND4_8197F) +#define BIT_SET_ATIMWND4_8197F(x, v) \ + (BIT_CLEAR_ATIMWND4_8197F(x) | BIT_ATIMWND4_8197F(v)) /* 2 REG_ATIMWND5_8197F */ #define BIT_SHIFT_ATIMWND5_8197F 0 #define BIT_MASK_ATIMWND5_8197F 0xff -#define BIT_ATIMWND5_8197F(x) (((x) & BIT_MASK_ATIMWND5_8197F) << BIT_SHIFT_ATIMWND5_8197F) -#define BITS_ATIMWND5_8197F (BIT_MASK_ATIMWND5_8197F << BIT_SHIFT_ATIMWND5_8197F) +#define BIT_ATIMWND5_8197F(x) \ + (((x) & BIT_MASK_ATIMWND5_8197F) << BIT_SHIFT_ATIMWND5_8197F) +#define BITS_ATIMWND5_8197F \ + (BIT_MASK_ATIMWND5_8197F << BIT_SHIFT_ATIMWND5_8197F) #define BIT_CLEAR_ATIMWND5_8197F(x) ((x) & (~BITS_ATIMWND5_8197F)) -#define BIT_GET_ATIMWND5_8197F(x) (((x) >> BIT_SHIFT_ATIMWND5_8197F) & BIT_MASK_ATIMWND5_8197F) -#define BIT_SET_ATIMWND5_8197F(x, v) (BIT_CLEAR_ATIMWND5_8197F(x) | BIT_ATIMWND5_8197F(v)) - +#define BIT_GET_ATIMWND5_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND5_8197F) & BIT_MASK_ATIMWND5_8197F) +#define BIT_SET_ATIMWND5_8197F(x, v) \ + (BIT_CLEAR_ATIMWND5_8197F(x) | BIT_ATIMWND5_8197F(v)) /* 2 REG_ATIMWND6_8197F */ #define BIT_SHIFT_ATIMWND6_8197F 0 #define BIT_MASK_ATIMWND6_8197F 0xff -#define BIT_ATIMWND6_8197F(x) (((x) & BIT_MASK_ATIMWND6_8197F) << BIT_SHIFT_ATIMWND6_8197F) -#define BITS_ATIMWND6_8197F (BIT_MASK_ATIMWND6_8197F << BIT_SHIFT_ATIMWND6_8197F) +#define BIT_ATIMWND6_8197F(x) \ + (((x) & BIT_MASK_ATIMWND6_8197F) << BIT_SHIFT_ATIMWND6_8197F) +#define BITS_ATIMWND6_8197F \ + (BIT_MASK_ATIMWND6_8197F << BIT_SHIFT_ATIMWND6_8197F) #define BIT_CLEAR_ATIMWND6_8197F(x) ((x) & (~BITS_ATIMWND6_8197F)) -#define BIT_GET_ATIMWND6_8197F(x) (((x) >> BIT_SHIFT_ATIMWND6_8197F) & BIT_MASK_ATIMWND6_8197F) -#define BIT_SET_ATIMWND6_8197F(x, v) (BIT_CLEAR_ATIMWND6_8197F(x) | BIT_ATIMWND6_8197F(v)) - +#define BIT_GET_ATIMWND6_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND6_8197F) & BIT_MASK_ATIMWND6_8197F) +#define BIT_SET_ATIMWND6_8197F(x, v) \ + (BIT_CLEAR_ATIMWND6_8197F(x) | BIT_ATIMWND6_8197F(v)) /* 2 REG_ATIMWND7_8197F */ #define BIT_SHIFT_ATIMWND7_8197F 0 #define BIT_MASK_ATIMWND7_8197F 0xff -#define BIT_ATIMWND7_8197F(x) (((x) & BIT_MASK_ATIMWND7_8197F) << BIT_SHIFT_ATIMWND7_8197F) -#define BITS_ATIMWND7_8197F (BIT_MASK_ATIMWND7_8197F << BIT_SHIFT_ATIMWND7_8197F) +#define BIT_ATIMWND7_8197F(x) \ + (((x) & BIT_MASK_ATIMWND7_8197F) << BIT_SHIFT_ATIMWND7_8197F) +#define BITS_ATIMWND7_8197F \ + (BIT_MASK_ATIMWND7_8197F << BIT_SHIFT_ATIMWND7_8197F) #define BIT_CLEAR_ATIMWND7_8197F(x) ((x) & (~BITS_ATIMWND7_8197F)) -#define BIT_GET_ATIMWND7_8197F(x) (((x) >> BIT_SHIFT_ATIMWND7_8197F) & BIT_MASK_ATIMWND7_8197F) -#define BIT_SET_ATIMWND7_8197F(x, v) (BIT_CLEAR_ATIMWND7_8197F(x) | BIT_ATIMWND7_8197F(v)) - +#define BIT_GET_ATIMWND7_8197F(x) \ + (((x) >> BIT_SHIFT_ATIMWND7_8197F) & BIT_MASK_ATIMWND7_8197F) +#define BIT_SET_ATIMWND7_8197F(x, v) \ + (BIT_CLEAR_ATIMWND7_8197F(x) | BIT_ATIMWND7_8197F(v)) /* 2 REG_ATIMUGT_8197F */ #define BIT_SHIFT_ATIM_URGENT_8197F 0 #define BIT_MASK_ATIM_URGENT_8197F 0xff -#define BIT_ATIM_URGENT_8197F(x) (((x) & BIT_MASK_ATIM_URGENT_8197F) << BIT_SHIFT_ATIM_URGENT_8197F) -#define BITS_ATIM_URGENT_8197F (BIT_MASK_ATIM_URGENT_8197F << BIT_SHIFT_ATIM_URGENT_8197F) +#define BIT_ATIM_URGENT_8197F(x) \ + (((x) & BIT_MASK_ATIM_URGENT_8197F) << BIT_SHIFT_ATIM_URGENT_8197F) +#define BITS_ATIM_URGENT_8197F \ + (BIT_MASK_ATIM_URGENT_8197F << BIT_SHIFT_ATIM_URGENT_8197F) #define BIT_CLEAR_ATIM_URGENT_8197F(x) ((x) & (~BITS_ATIM_URGENT_8197F)) -#define BIT_GET_ATIM_URGENT_8197F(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8197F) & BIT_MASK_ATIM_URGENT_8197F) -#define BIT_SET_ATIM_URGENT_8197F(x, v) (BIT_CLEAR_ATIM_URGENT_8197F(x) | BIT_ATIM_URGENT_8197F(v)) - +#define BIT_GET_ATIM_URGENT_8197F(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_8197F) & BIT_MASK_ATIM_URGENT_8197F) +#define BIT_SET_ATIM_URGENT_8197F(x, v) \ + (BIT_CLEAR_ATIM_URGENT_8197F(x) | BIT_ATIM_URGENT_8197F(v)) /* 2 REG_HIQ_NO_LMT_EN_8197F */ #define BIT_HIQ_NO_LMT_EN_VAP7_8197F BIT(7) @@ -9457,89 +12352,129 @@ #define BIT_SHIFT_DTIM_COUNT_ROOT_8197F 0 #define BIT_MASK_DTIM_COUNT_ROOT_8197F 0xff -#define BIT_DTIM_COUNT_ROOT_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8197F) << BIT_SHIFT_DTIM_COUNT_ROOT_8197F) -#define BITS_DTIM_COUNT_ROOT_8197F (BIT_MASK_DTIM_COUNT_ROOT_8197F << BIT_SHIFT_DTIM_COUNT_ROOT_8197F) +#define BIT_DTIM_COUNT_ROOT_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_ROOT_8197F) \ + << BIT_SHIFT_DTIM_COUNT_ROOT_8197F) +#define BITS_DTIM_COUNT_ROOT_8197F \ + (BIT_MASK_DTIM_COUNT_ROOT_8197F << BIT_SHIFT_DTIM_COUNT_ROOT_8197F) #define BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8197F)) -#define BIT_GET_DTIM_COUNT_ROOT_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8197F) & BIT_MASK_DTIM_COUNT_ROOT_8197F) -#define BIT_SET_DTIM_COUNT_ROOT_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) | BIT_DTIM_COUNT_ROOT_8197F(v)) - +#define BIT_GET_DTIM_COUNT_ROOT_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8197F) & \ + BIT_MASK_DTIM_COUNT_ROOT_8197F) +#define BIT_SET_DTIM_COUNT_ROOT_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) | BIT_DTIM_COUNT_ROOT_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP1_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP1_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP1_8197F 0xff -#define BIT_DTIM_COUNT_VAP1_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8197F) << BIT_SHIFT_DTIM_COUNT_VAP1_8197F) -#define BITS_DTIM_COUNT_VAP1_8197F (BIT_MASK_DTIM_COUNT_VAP1_8197F << BIT_SHIFT_DTIM_COUNT_VAP1_8197F) +#define BIT_DTIM_COUNT_VAP1_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP1_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP1_8197F) +#define BITS_DTIM_COUNT_VAP1_8197F \ + (BIT_MASK_DTIM_COUNT_VAP1_8197F << BIT_SHIFT_DTIM_COUNT_VAP1_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8197F)) -#define BIT_GET_DTIM_COUNT_VAP1_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8197F) & BIT_MASK_DTIM_COUNT_VAP1_8197F) -#define BIT_SET_DTIM_COUNT_VAP1_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) | BIT_DTIM_COUNT_VAP1_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP1_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP1_8197F) +#define BIT_SET_DTIM_COUNT_VAP1_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) | BIT_DTIM_COUNT_VAP1_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP2_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP2_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP2_8197F 0xff -#define BIT_DTIM_COUNT_VAP2_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8197F) << BIT_SHIFT_DTIM_COUNT_VAP2_8197F) -#define BITS_DTIM_COUNT_VAP2_8197F (BIT_MASK_DTIM_COUNT_VAP2_8197F << BIT_SHIFT_DTIM_COUNT_VAP2_8197F) +#define BIT_DTIM_COUNT_VAP2_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP2_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP2_8197F) +#define BITS_DTIM_COUNT_VAP2_8197F \ + (BIT_MASK_DTIM_COUNT_VAP2_8197F << BIT_SHIFT_DTIM_COUNT_VAP2_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8197F)) -#define BIT_GET_DTIM_COUNT_VAP2_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8197F) & BIT_MASK_DTIM_COUNT_VAP2_8197F) -#define BIT_SET_DTIM_COUNT_VAP2_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) | BIT_DTIM_COUNT_VAP2_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP2_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP2_8197F) +#define BIT_SET_DTIM_COUNT_VAP2_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) | BIT_DTIM_COUNT_VAP2_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP3_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP3_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP3_8197F 0xff -#define BIT_DTIM_COUNT_VAP3_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8197F) << BIT_SHIFT_DTIM_COUNT_VAP3_8197F) -#define BITS_DTIM_COUNT_VAP3_8197F (BIT_MASK_DTIM_COUNT_VAP3_8197F << BIT_SHIFT_DTIM_COUNT_VAP3_8197F) +#define BIT_DTIM_COUNT_VAP3_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP3_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP3_8197F) +#define BITS_DTIM_COUNT_VAP3_8197F \ + (BIT_MASK_DTIM_COUNT_VAP3_8197F << BIT_SHIFT_DTIM_COUNT_VAP3_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8197F)) -#define BIT_GET_DTIM_COUNT_VAP3_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8197F) & BIT_MASK_DTIM_COUNT_VAP3_8197F) -#define BIT_SET_DTIM_COUNT_VAP3_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) | BIT_DTIM_COUNT_VAP3_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP3_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP3_8197F) +#define BIT_SET_DTIM_COUNT_VAP3_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) | BIT_DTIM_COUNT_VAP3_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP4_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP4_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP4_8197F 0xff -#define BIT_DTIM_COUNT_VAP4_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8197F) << BIT_SHIFT_DTIM_COUNT_VAP4_8197F) -#define BITS_DTIM_COUNT_VAP4_8197F (BIT_MASK_DTIM_COUNT_VAP4_8197F << BIT_SHIFT_DTIM_COUNT_VAP4_8197F) +#define BIT_DTIM_COUNT_VAP4_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP4_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP4_8197F) +#define BITS_DTIM_COUNT_VAP4_8197F \ + (BIT_MASK_DTIM_COUNT_VAP4_8197F << BIT_SHIFT_DTIM_COUNT_VAP4_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8197F)) -#define BIT_GET_DTIM_COUNT_VAP4_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8197F) & BIT_MASK_DTIM_COUNT_VAP4_8197F) -#define BIT_SET_DTIM_COUNT_VAP4_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) | BIT_DTIM_COUNT_VAP4_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP4_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP4_8197F) +#define BIT_SET_DTIM_COUNT_VAP4_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) | BIT_DTIM_COUNT_VAP4_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP5_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP5_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP5_8197F 0xff -#define BIT_DTIM_COUNT_VAP5_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8197F) << BIT_SHIFT_DTIM_COUNT_VAP5_8197F) -#define BITS_DTIM_COUNT_VAP5_8197F (BIT_MASK_DTIM_COUNT_VAP5_8197F << BIT_SHIFT_DTIM_COUNT_VAP5_8197F) +#define BIT_DTIM_COUNT_VAP5_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP5_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP5_8197F) +#define BITS_DTIM_COUNT_VAP5_8197F \ + (BIT_MASK_DTIM_COUNT_VAP5_8197F << BIT_SHIFT_DTIM_COUNT_VAP5_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8197F)) -#define BIT_GET_DTIM_COUNT_VAP5_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8197F) & BIT_MASK_DTIM_COUNT_VAP5_8197F) -#define BIT_SET_DTIM_COUNT_VAP5_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) | BIT_DTIM_COUNT_VAP5_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP5_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP5_8197F) +#define BIT_SET_DTIM_COUNT_VAP5_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) | BIT_DTIM_COUNT_VAP5_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP6_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP6_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP6_8197F 0xff -#define BIT_DTIM_COUNT_VAP6_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8197F) << BIT_SHIFT_DTIM_COUNT_VAP6_8197F) -#define BITS_DTIM_COUNT_VAP6_8197F (BIT_MASK_DTIM_COUNT_VAP6_8197F << BIT_SHIFT_DTIM_COUNT_VAP6_8197F) +#define BIT_DTIM_COUNT_VAP6_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP6_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP6_8197F) +#define BITS_DTIM_COUNT_VAP6_8197F \ + (BIT_MASK_DTIM_COUNT_VAP6_8197F << BIT_SHIFT_DTIM_COUNT_VAP6_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8197F)) -#define BIT_GET_DTIM_COUNT_VAP6_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8197F) & BIT_MASK_DTIM_COUNT_VAP6_8197F) -#define BIT_SET_DTIM_COUNT_VAP6_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) | BIT_DTIM_COUNT_VAP6_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP6_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP6_8197F) +#define BIT_SET_DTIM_COUNT_VAP6_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) | BIT_DTIM_COUNT_VAP6_8197F(v)) /* 2 REG_DTIM_COUNTER_VAP7_8197F */ #define BIT_SHIFT_DTIM_COUNT_VAP7_8197F 0 #define BIT_MASK_DTIM_COUNT_VAP7_8197F 0xff -#define BIT_DTIM_COUNT_VAP7_8197F(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8197F) << BIT_SHIFT_DTIM_COUNT_VAP7_8197F) -#define BITS_DTIM_COUNT_VAP7_8197F (BIT_MASK_DTIM_COUNT_VAP7_8197F << BIT_SHIFT_DTIM_COUNT_VAP7_8197F) +#define BIT_DTIM_COUNT_VAP7_8197F(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP7_8197F) \ + << BIT_SHIFT_DTIM_COUNT_VAP7_8197F) +#define BITS_DTIM_COUNT_VAP7_8197F \ + (BIT_MASK_DTIM_COUNT_VAP7_8197F << BIT_SHIFT_DTIM_COUNT_VAP7_8197F) #define BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8197F)) -#define BIT_GET_DTIM_COUNT_VAP7_8197F(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8197F) & BIT_MASK_DTIM_COUNT_VAP7_8197F) -#define BIT_SET_DTIM_COUNT_VAP7_8197F(x, v) (BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) | BIT_DTIM_COUNT_VAP7_8197F(v)) - +#define BIT_GET_DTIM_COUNT_VAP7_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8197F) & \ + BIT_MASK_DTIM_COUNT_VAP7_8197F) +#define BIT_SET_DTIM_COUNT_VAP7_8197F(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) | BIT_DTIM_COUNT_VAP7_8197F(v)) /* 2 REG_DIS_ATIM_8197F */ #define BIT_DIS_ATIM_VAP7_8197F BIT(7) @@ -9555,21 +12490,29 @@ #define BIT_SHIFT_TSFT_SEL_TIMER1_8197F 3 #define BIT_MASK_TSFT_SEL_TIMER1_8197F 0x7 -#define BIT_TSFT_SEL_TIMER1_8197F(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8197F) << BIT_SHIFT_TSFT_SEL_TIMER1_8197F) -#define BITS_TSFT_SEL_TIMER1_8197F (BIT_MASK_TSFT_SEL_TIMER1_8197F << BIT_SHIFT_TSFT_SEL_TIMER1_8197F) +#define BIT_TSFT_SEL_TIMER1_8197F(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER1_8197F) \ + << BIT_SHIFT_TSFT_SEL_TIMER1_8197F) +#define BITS_TSFT_SEL_TIMER1_8197F \ + (BIT_MASK_TSFT_SEL_TIMER1_8197F << BIT_SHIFT_TSFT_SEL_TIMER1_8197F) #define BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8197F)) -#define BIT_GET_TSFT_SEL_TIMER1_8197F(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8197F) & BIT_MASK_TSFT_SEL_TIMER1_8197F) -#define BIT_SET_TSFT_SEL_TIMER1_8197F(x, v) (BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) | BIT_TSFT_SEL_TIMER1_8197F(v)) - +#define BIT_GET_TSFT_SEL_TIMER1_8197F(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8197F) & \ + BIT_MASK_TSFT_SEL_TIMER1_8197F) +#define BIT_SET_TSFT_SEL_TIMER1_8197F(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) | BIT_TSFT_SEL_TIMER1_8197F(v)) #define BIT_SHIFT_EARLY_128US_8197F 0 #define BIT_MASK_EARLY_128US_8197F 0x7 -#define BIT_EARLY_128US_8197F(x) (((x) & BIT_MASK_EARLY_128US_8197F) << BIT_SHIFT_EARLY_128US_8197F) -#define BITS_EARLY_128US_8197F (BIT_MASK_EARLY_128US_8197F << BIT_SHIFT_EARLY_128US_8197F) +#define BIT_EARLY_128US_8197F(x) \ + (((x) & BIT_MASK_EARLY_128US_8197F) << BIT_SHIFT_EARLY_128US_8197F) +#define BITS_EARLY_128US_8197F \ + (BIT_MASK_EARLY_128US_8197F << BIT_SHIFT_EARLY_128US_8197F) #define BIT_CLEAR_EARLY_128US_8197F(x) ((x) & (~BITS_EARLY_128US_8197F)) -#define BIT_GET_EARLY_128US_8197F(x) (((x) >> BIT_SHIFT_EARLY_128US_8197F) & BIT_MASK_EARLY_128US_8197F) -#define BIT_SET_EARLY_128US_8197F(x, v) (BIT_CLEAR_EARLY_128US_8197F(x) | BIT_EARLY_128US_8197F(v)) - +#define BIT_GET_EARLY_128US_8197F(x) \ + (((x) >> BIT_SHIFT_EARLY_128US_8197F) & BIT_MASK_EARLY_128US_8197F) +#define BIT_SET_EARLY_128US_8197F(x, v) \ + (BIT_CLEAR_EARLY_128US_8197F(x) | BIT_EARLY_128US_8197F(v)) /* 2 REG_P2PPS1_CTRL_8197F */ #define BIT_P2P1_CTW_ALLSTASLEEP_8197F BIT(7) @@ -9589,101 +12532,145 @@ #define BIT_SHIFT_SYNC_CLI_SEL_8197F 4 #define BIT_MASK_SYNC_CLI_SEL_8197F 0x7 -#define BIT_SYNC_CLI_SEL_8197F(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8197F) << BIT_SHIFT_SYNC_CLI_SEL_8197F) -#define BITS_SYNC_CLI_SEL_8197F (BIT_MASK_SYNC_CLI_SEL_8197F << BIT_SHIFT_SYNC_CLI_SEL_8197F) +#define BIT_SYNC_CLI_SEL_8197F(x) \ + (((x) & BIT_MASK_SYNC_CLI_SEL_8197F) << BIT_SHIFT_SYNC_CLI_SEL_8197F) +#define BITS_SYNC_CLI_SEL_8197F \ + (BIT_MASK_SYNC_CLI_SEL_8197F << BIT_SHIFT_SYNC_CLI_SEL_8197F) #define BIT_CLEAR_SYNC_CLI_SEL_8197F(x) ((x) & (~BITS_SYNC_CLI_SEL_8197F)) -#define BIT_GET_SYNC_CLI_SEL_8197F(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8197F) & BIT_MASK_SYNC_CLI_SEL_8197F) -#define BIT_SET_SYNC_CLI_SEL_8197F(x, v) (BIT_CLEAR_SYNC_CLI_SEL_8197F(x) | BIT_SYNC_CLI_SEL_8197F(v)) - +#define BIT_GET_SYNC_CLI_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8197F) & BIT_MASK_SYNC_CLI_SEL_8197F) +#define BIT_SET_SYNC_CLI_SEL_8197F(x, v) \ + (BIT_CLEAR_SYNC_CLI_SEL_8197F(x) | BIT_SYNC_CLI_SEL_8197F(v)) #define BIT_SHIFT_TSFT_SEL_TIMER0_8197F 0 #define BIT_MASK_TSFT_SEL_TIMER0_8197F 0x7 -#define BIT_TSFT_SEL_TIMER0_8197F(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8197F) << BIT_SHIFT_TSFT_SEL_TIMER0_8197F) -#define BITS_TSFT_SEL_TIMER0_8197F (BIT_MASK_TSFT_SEL_TIMER0_8197F << BIT_SHIFT_TSFT_SEL_TIMER0_8197F) +#define BIT_TSFT_SEL_TIMER0_8197F(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER0_8197F) \ + << BIT_SHIFT_TSFT_SEL_TIMER0_8197F) +#define BITS_TSFT_SEL_TIMER0_8197F \ + (BIT_MASK_TSFT_SEL_TIMER0_8197F << BIT_SHIFT_TSFT_SEL_TIMER0_8197F) #define BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8197F)) -#define BIT_GET_TSFT_SEL_TIMER0_8197F(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8197F) & BIT_MASK_TSFT_SEL_TIMER0_8197F) -#define BIT_SET_TSFT_SEL_TIMER0_8197F(x, v) (BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) | BIT_TSFT_SEL_TIMER0_8197F(v)) - +#define BIT_GET_TSFT_SEL_TIMER0_8197F(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8197F) & \ + BIT_MASK_TSFT_SEL_TIMER0_8197F) +#define BIT_SET_TSFT_SEL_TIMER0_8197F(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) | BIT_TSFT_SEL_TIMER0_8197F(v)) /* 2 REG_NOA_UNIT_SEL_8197F */ #define BIT_SHIFT_NOA_UNIT2_SEL_8197F 8 #define BIT_MASK_NOA_UNIT2_SEL_8197F 0x7 -#define BIT_NOA_UNIT2_SEL_8197F(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8197F) << BIT_SHIFT_NOA_UNIT2_SEL_8197F) -#define BITS_NOA_UNIT2_SEL_8197F (BIT_MASK_NOA_UNIT2_SEL_8197F << BIT_SHIFT_NOA_UNIT2_SEL_8197F) +#define BIT_NOA_UNIT2_SEL_8197F(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_8197F) << BIT_SHIFT_NOA_UNIT2_SEL_8197F) +#define BITS_NOA_UNIT2_SEL_8197F \ + (BIT_MASK_NOA_UNIT2_SEL_8197F << BIT_SHIFT_NOA_UNIT2_SEL_8197F) #define BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT2_SEL_8197F)) -#define BIT_GET_NOA_UNIT2_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8197F) & BIT_MASK_NOA_UNIT2_SEL_8197F) -#define BIT_SET_NOA_UNIT2_SEL_8197F(x, v) (BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) | BIT_NOA_UNIT2_SEL_8197F(v)) - +#define BIT_GET_NOA_UNIT2_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8197F) & BIT_MASK_NOA_UNIT2_SEL_8197F) +#define BIT_SET_NOA_UNIT2_SEL_8197F(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) | BIT_NOA_UNIT2_SEL_8197F(v)) #define BIT_SHIFT_NOA_UNIT1_SEL_8197F 4 #define BIT_MASK_NOA_UNIT1_SEL_8197F 0x7 -#define BIT_NOA_UNIT1_SEL_8197F(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8197F) << BIT_SHIFT_NOA_UNIT1_SEL_8197F) -#define BITS_NOA_UNIT1_SEL_8197F (BIT_MASK_NOA_UNIT1_SEL_8197F << BIT_SHIFT_NOA_UNIT1_SEL_8197F) +#define BIT_NOA_UNIT1_SEL_8197F(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_8197F) << BIT_SHIFT_NOA_UNIT1_SEL_8197F) +#define BITS_NOA_UNIT1_SEL_8197F \ + (BIT_MASK_NOA_UNIT1_SEL_8197F << BIT_SHIFT_NOA_UNIT1_SEL_8197F) #define BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT1_SEL_8197F)) -#define BIT_GET_NOA_UNIT1_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8197F) & BIT_MASK_NOA_UNIT1_SEL_8197F) -#define BIT_SET_NOA_UNIT1_SEL_8197F(x, v) (BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) | BIT_NOA_UNIT1_SEL_8197F(v)) - +#define BIT_GET_NOA_UNIT1_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8197F) & BIT_MASK_NOA_UNIT1_SEL_8197F) +#define BIT_SET_NOA_UNIT1_SEL_8197F(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) | BIT_NOA_UNIT1_SEL_8197F(v)) #define BIT_SHIFT_NOA_UNIT0_SEL_8197F 0 #define BIT_MASK_NOA_UNIT0_SEL_8197F 0x7 -#define BIT_NOA_UNIT0_SEL_8197F(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8197F) << BIT_SHIFT_NOA_UNIT0_SEL_8197F) -#define BITS_NOA_UNIT0_SEL_8197F (BIT_MASK_NOA_UNIT0_SEL_8197F << BIT_SHIFT_NOA_UNIT0_SEL_8197F) +#define BIT_NOA_UNIT0_SEL_8197F(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_8197F) << BIT_SHIFT_NOA_UNIT0_SEL_8197F) +#define BITS_NOA_UNIT0_SEL_8197F \ + (BIT_MASK_NOA_UNIT0_SEL_8197F << BIT_SHIFT_NOA_UNIT0_SEL_8197F) #define BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT0_SEL_8197F)) -#define BIT_GET_NOA_UNIT0_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8197F) & BIT_MASK_NOA_UNIT0_SEL_8197F) -#define BIT_SET_NOA_UNIT0_SEL_8197F(x, v) (BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) | BIT_NOA_UNIT0_SEL_8197F(v)) - +#define BIT_GET_NOA_UNIT0_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8197F) & BIT_MASK_NOA_UNIT0_SEL_8197F) +#define BIT_SET_NOA_UNIT0_SEL_8197F(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) | BIT_NOA_UNIT0_SEL_8197F(v)) /* 2 REG_P2POFF_DIS_TXTIME_8197F */ #define BIT_SHIFT_P2POFF_DIS_TXTIME_8197F 0 #define BIT_MASK_P2POFF_DIS_TXTIME_8197F 0xff -#define BIT_P2POFF_DIS_TXTIME_8197F(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8197F) << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) -#define BITS_P2POFF_DIS_TXTIME_8197F (BIT_MASK_P2POFF_DIS_TXTIME_8197F << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) -#define BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) ((x) & (~BITS_P2POFF_DIS_TXTIME_8197F)) -#define BIT_GET_P2POFF_DIS_TXTIME_8197F(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) & BIT_MASK_P2POFF_DIS_TXTIME_8197F) -#define BIT_SET_P2POFF_DIS_TXTIME_8197F(x, v) (BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) | BIT_P2POFF_DIS_TXTIME_8197F(v)) - +#define BIT_P2POFF_DIS_TXTIME_8197F(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8197F) \ + << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) +#define BITS_P2POFF_DIS_TXTIME_8197F \ + (BIT_MASK_P2POFF_DIS_TXTIME_8197F << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) +#define BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) \ + ((x) & (~BITS_P2POFF_DIS_TXTIME_8197F)) +#define BIT_GET_P2POFF_DIS_TXTIME_8197F(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) & \ + BIT_MASK_P2POFF_DIS_TXTIME_8197F) +#define BIT_SET_P2POFF_DIS_TXTIME_8197F(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) | BIT_P2POFF_DIS_TXTIME_8197F(v)) /* 2 REG_MBSSID_BCN_SPACE2_8197F */ #define BIT_SHIFT_BCN_SPACE_CLINT2_8197F 16 #define BIT_MASK_BCN_SPACE_CLINT2_8197F 0xfff -#define BIT_BCN_SPACE_CLINT2_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8197F) << BIT_SHIFT_BCN_SPACE_CLINT2_8197F) -#define BITS_BCN_SPACE_CLINT2_8197F (BIT_MASK_BCN_SPACE_CLINT2_8197F << BIT_SHIFT_BCN_SPACE_CLINT2_8197F) -#define BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT2_8197F)) -#define BIT_GET_BCN_SPACE_CLINT2_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8197F) & BIT_MASK_BCN_SPACE_CLINT2_8197F) -#define BIT_SET_BCN_SPACE_CLINT2_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) | BIT_BCN_SPACE_CLINT2_8197F(v)) - +#define BIT_BCN_SPACE_CLINT2_8197F(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT2_8197F) \ + << BIT_SHIFT_BCN_SPACE_CLINT2_8197F) +#define BITS_BCN_SPACE_CLINT2_8197F \ + (BIT_MASK_BCN_SPACE_CLINT2_8197F << BIT_SHIFT_BCN_SPACE_CLINT2_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT2_8197F)) +#define BIT_GET_BCN_SPACE_CLINT2_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8197F) & \ + BIT_MASK_BCN_SPACE_CLINT2_8197F) +#define BIT_SET_BCN_SPACE_CLINT2_8197F(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) | BIT_BCN_SPACE_CLINT2_8197F(v)) #define BIT_SHIFT_BCN_SPACE_CLINT1_8197F 0 #define BIT_MASK_BCN_SPACE_CLINT1_8197F 0xfff -#define BIT_BCN_SPACE_CLINT1_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8197F) << BIT_SHIFT_BCN_SPACE_CLINT1_8197F) -#define BITS_BCN_SPACE_CLINT1_8197F (BIT_MASK_BCN_SPACE_CLINT1_8197F << BIT_SHIFT_BCN_SPACE_CLINT1_8197F) -#define BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT1_8197F)) -#define BIT_GET_BCN_SPACE_CLINT1_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8197F) & BIT_MASK_BCN_SPACE_CLINT1_8197F) -#define BIT_SET_BCN_SPACE_CLINT1_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) | BIT_BCN_SPACE_CLINT1_8197F(v)) - +#define BIT_BCN_SPACE_CLINT1_8197F(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT1_8197F) \ + << BIT_SHIFT_BCN_SPACE_CLINT1_8197F) +#define BITS_BCN_SPACE_CLINT1_8197F \ + (BIT_MASK_BCN_SPACE_CLINT1_8197F << BIT_SHIFT_BCN_SPACE_CLINT1_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT1_8197F)) +#define BIT_GET_BCN_SPACE_CLINT1_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8197F) & \ + BIT_MASK_BCN_SPACE_CLINT1_8197F) +#define BIT_SET_BCN_SPACE_CLINT1_8197F(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) | BIT_BCN_SPACE_CLINT1_8197F(v)) /* 2 REG_MBSSID_BCN_SPACE3_8197F */ -#define BIT_SHIFT_SUB_BCN_SPACE_V1_8197F 16 -#define BIT_MASK_SUB_BCN_SPACE_V1_8197F 0xfff -#define BIT_SUB_BCN_SPACE_V1_8197F(x) (((x) & BIT_MASK_SUB_BCN_SPACE_V1_8197F) << BIT_SHIFT_SUB_BCN_SPACE_V1_8197F) -#define BITS_SUB_BCN_SPACE_V1_8197F (BIT_MASK_SUB_BCN_SPACE_V1_8197F << BIT_SHIFT_SUB_BCN_SPACE_V1_8197F) -#define BIT_CLEAR_SUB_BCN_SPACE_V1_8197F(x) ((x) & (~BITS_SUB_BCN_SPACE_V1_8197F)) -#define BIT_GET_SUB_BCN_SPACE_V1_8197F(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V1_8197F) & BIT_MASK_SUB_BCN_SPACE_V1_8197F) -#define BIT_SET_SUB_BCN_SPACE_V1_8197F(x, v) (BIT_CLEAR_SUB_BCN_SPACE_V1_8197F(x) | BIT_SUB_BCN_SPACE_V1_8197F(v)) - +#define BIT_SHIFT_SUB_BCN_SPACE_8197F 16 +#define BIT_MASK_SUB_BCN_SPACE_8197F 0xff +#define BIT_SUB_BCN_SPACE_8197F(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_8197F) << BIT_SHIFT_SUB_BCN_SPACE_8197F) +#define BITS_SUB_BCN_SPACE_8197F \ + (BIT_MASK_SUB_BCN_SPACE_8197F << BIT_SHIFT_SUB_BCN_SPACE_8197F) +#define BIT_CLEAR_SUB_BCN_SPACE_8197F(x) ((x) & (~BITS_SUB_BCN_SPACE_8197F)) +#define BIT_GET_SUB_BCN_SPACE_8197F(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8197F) & BIT_MASK_SUB_BCN_SPACE_8197F) +#define BIT_SET_SUB_BCN_SPACE_8197F(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_8197F(x) | BIT_SUB_BCN_SPACE_8197F(v)) #define BIT_SHIFT_BCN_SPACE_CLINT3_8197F 0 #define BIT_MASK_BCN_SPACE_CLINT3_8197F 0xfff -#define BIT_BCN_SPACE_CLINT3_8197F(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8197F) << BIT_SHIFT_BCN_SPACE_CLINT3_8197F) -#define BITS_BCN_SPACE_CLINT3_8197F (BIT_MASK_BCN_SPACE_CLINT3_8197F << BIT_SHIFT_BCN_SPACE_CLINT3_8197F) -#define BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) ((x) & (~BITS_BCN_SPACE_CLINT3_8197F)) -#define BIT_GET_BCN_SPACE_CLINT3_8197F(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8197F) & BIT_MASK_BCN_SPACE_CLINT3_8197F) -#define BIT_SET_BCN_SPACE_CLINT3_8197F(x, v) (BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) | BIT_BCN_SPACE_CLINT3_8197F(v)) - +#define BIT_BCN_SPACE_CLINT3_8197F(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT3_8197F) \ + << BIT_SHIFT_BCN_SPACE_CLINT3_8197F) +#define BITS_BCN_SPACE_CLINT3_8197F \ + (BIT_MASK_BCN_SPACE_CLINT3_8197F << BIT_SHIFT_BCN_SPACE_CLINT3_8197F) +#define BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT3_8197F)) +#define BIT_GET_BCN_SPACE_CLINT3_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8197F) & \ + BIT_MASK_BCN_SPACE_CLINT3_8197F) +#define BIT_SET_BCN_SPACE_CLINT3_8197F(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) | BIT_BCN_SPACE_CLINT3_8197F(v)) /* 2 REG_ACMHWCTRL_8197F */ #define BIT_BEQ_ACM_STATUS_8197F BIT(7) @@ -9703,205 +12690,289 @@ #define BIT_SHIFT_AVGPERIOD_8197F 0 #define BIT_MASK_AVGPERIOD_8197F 0xffff -#define BIT_AVGPERIOD_8197F(x) (((x) & BIT_MASK_AVGPERIOD_8197F) << BIT_SHIFT_AVGPERIOD_8197F) -#define BITS_AVGPERIOD_8197F (BIT_MASK_AVGPERIOD_8197F << BIT_SHIFT_AVGPERIOD_8197F) +#define BIT_AVGPERIOD_8197F(x) \ + (((x) & BIT_MASK_AVGPERIOD_8197F) << BIT_SHIFT_AVGPERIOD_8197F) +#define BITS_AVGPERIOD_8197F \ + (BIT_MASK_AVGPERIOD_8197F << BIT_SHIFT_AVGPERIOD_8197F) #define BIT_CLEAR_AVGPERIOD_8197F(x) ((x) & (~BITS_AVGPERIOD_8197F)) -#define BIT_GET_AVGPERIOD_8197F(x) (((x) >> BIT_SHIFT_AVGPERIOD_8197F) & BIT_MASK_AVGPERIOD_8197F) -#define BIT_SET_AVGPERIOD_8197F(x, v) (BIT_CLEAR_AVGPERIOD_8197F(x) | BIT_AVGPERIOD_8197F(v)) - +#define BIT_GET_AVGPERIOD_8197F(x) \ + (((x) >> BIT_SHIFT_AVGPERIOD_8197F) & BIT_MASK_AVGPERIOD_8197F) +#define BIT_SET_AVGPERIOD_8197F(x, v) \ + (BIT_CLEAR_AVGPERIOD_8197F(x) | BIT_AVGPERIOD_8197F(v)) /* 2 REG_VO_ADMTIME_8197F */ #define BIT_SHIFT_VO_ADMITTED_TIME_8197F 0 #define BIT_MASK_VO_ADMITTED_TIME_8197F 0xffff -#define BIT_VO_ADMITTED_TIME_8197F(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8197F) << BIT_SHIFT_VO_ADMITTED_TIME_8197F) -#define BITS_VO_ADMITTED_TIME_8197F (BIT_MASK_VO_ADMITTED_TIME_8197F << BIT_SHIFT_VO_ADMITTED_TIME_8197F) -#define BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) ((x) & (~BITS_VO_ADMITTED_TIME_8197F)) -#define BIT_GET_VO_ADMITTED_TIME_8197F(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8197F) & BIT_MASK_VO_ADMITTED_TIME_8197F) -#define BIT_SET_VO_ADMITTED_TIME_8197F(x, v) (BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) | BIT_VO_ADMITTED_TIME_8197F(v)) - +#define BIT_VO_ADMITTED_TIME_8197F(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME_8197F) \ + << BIT_SHIFT_VO_ADMITTED_TIME_8197F) +#define BITS_VO_ADMITTED_TIME_8197F \ + (BIT_MASK_VO_ADMITTED_TIME_8197F << BIT_SHIFT_VO_ADMITTED_TIME_8197F) +#define BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) \ + ((x) & (~BITS_VO_ADMITTED_TIME_8197F)) +#define BIT_GET_VO_ADMITTED_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8197F) & \ + BIT_MASK_VO_ADMITTED_TIME_8197F) +#define BIT_SET_VO_ADMITTED_TIME_8197F(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) | BIT_VO_ADMITTED_TIME_8197F(v)) /* 2 REG_VI_ADMTIME_8197F */ #define BIT_SHIFT_VI_ADMITTED_TIME_8197F 0 #define BIT_MASK_VI_ADMITTED_TIME_8197F 0xffff -#define BIT_VI_ADMITTED_TIME_8197F(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8197F) << BIT_SHIFT_VI_ADMITTED_TIME_8197F) -#define BITS_VI_ADMITTED_TIME_8197F (BIT_MASK_VI_ADMITTED_TIME_8197F << BIT_SHIFT_VI_ADMITTED_TIME_8197F) -#define BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) ((x) & (~BITS_VI_ADMITTED_TIME_8197F)) -#define BIT_GET_VI_ADMITTED_TIME_8197F(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8197F) & BIT_MASK_VI_ADMITTED_TIME_8197F) -#define BIT_SET_VI_ADMITTED_TIME_8197F(x, v) (BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) | BIT_VI_ADMITTED_TIME_8197F(v)) - +#define BIT_VI_ADMITTED_TIME_8197F(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME_8197F) \ + << BIT_SHIFT_VI_ADMITTED_TIME_8197F) +#define BITS_VI_ADMITTED_TIME_8197F \ + (BIT_MASK_VI_ADMITTED_TIME_8197F << BIT_SHIFT_VI_ADMITTED_TIME_8197F) +#define BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) \ + ((x) & (~BITS_VI_ADMITTED_TIME_8197F)) +#define BIT_GET_VI_ADMITTED_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8197F) & \ + BIT_MASK_VI_ADMITTED_TIME_8197F) +#define BIT_SET_VI_ADMITTED_TIME_8197F(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) | BIT_VI_ADMITTED_TIME_8197F(v)) /* 2 REG_BE_ADMTIME_8197F */ #define BIT_SHIFT_BE_ADMITTED_TIME_8197F 0 #define BIT_MASK_BE_ADMITTED_TIME_8197F 0xffff -#define BIT_BE_ADMITTED_TIME_8197F(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8197F) << BIT_SHIFT_BE_ADMITTED_TIME_8197F) -#define BITS_BE_ADMITTED_TIME_8197F (BIT_MASK_BE_ADMITTED_TIME_8197F << BIT_SHIFT_BE_ADMITTED_TIME_8197F) -#define BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) ((x) & (~BITS_BE_ADMITTED_TIME_8197F)) -#define BIT_GET_BE_ADMITTED_TIME_8197F(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8197F) & BIT_MASK_BE_ADMITTED_TIME_8197F) -#define BIT_SET_BE_ADMITTED_TIME_8197F(x, v) (BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) | BIT_BE_ADMITTED_TIME_8197F(v)) - +#define BIT_BE_ADMITTED_TIME_8197F(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME_8197F) \ + << BIT_SHIFT_BE_ADMITTED_TIME_8197F) +#define BITS_BE_ADMITTED_TIME_8197F \ + (BIT_MASK_BE_ADMITTED_TIME_8197F << BIT_SHIFT_BE_ADMITTED_TIME_8197F) +#define BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) \ + ((x) & (~BITS_BE_ADMITTED_TIME_8197F)) +#define BIT_GET_BE_ADMITTED_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8197F) & \ + BIT_MASK_BE_ADMITTED_TIME_8197F) +#define BIT_SET_BE_ADMITTED_TIME_8197F(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) | BIT_BE_ADMITTED_TIME_8197F(v)) /* 2 REG_NOT_VALID_8197F */ -#define BIT_CHANGE_POW_BCN_AREA_8197F BIT(1) +#define BIT_CHANGE_POW_BCN_AREA_8197F BIT(9) /* 2 REG_EDCA_RANDOM_GEN_8197F */ #define BIT_SHIFT_RANDOM_GEN_8197F 0 #define BIT_MASK_RANDOM_GEN_8197F 0xffffff -#define BIT_RANDOM_GEN_8197F(x) (((x) & BIT_MASK_RANDOM_GEN_8197F) << BIT_SHIFT_RANDOM_GEN_8197F) -#define BITS_RANDOM_GEN_8197F (BIT_MASK_RANDOM_GEN_8197F << BIT_SHIFT_RANDOM_GEN_8197F) +#define BIT_RANDOM_GEN_8197F(x) \ + (((x) & BIT_MASK_RANDOM_GEN_8197F) << BIT_SHIFT_RANDOM_GEN_8197F) +#define BITS_RANDOM_GEN_8197F \ + (BIT_MASK_RANDOM_GEN_8197F << BIT_SHIFT_RANDOM_GEN_8197F) #define BIT_CLEAR_RANDOM_GEN_8197F(x) ((x) & (~BITS_RANDOM_GEN_8197F)) -#define BIT_GET_RANDOM_GEN_8197F(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8197F) & BIT_MASK_RANDOM_GEN_8197F) -#define BIT_SET_RANDOM_GEN_8197F(x, v) (BIT_CLEAR_RANDOM_GEN_8197F(x) | BIT_RANDOM_GEN_8197F(v)) - +#define BIT_GET_RANDOM_GEN_8197F(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN_8197F) & BIT_MASK_RANDOM_GEN_8197F) +#define BIT_SET_RANDOM_GEN_8197F(x, v) \ + (BIT_CLEAR_RANDOM_GEN_8197F(x) | BIT_RANDOM_GEN_8197F(v)) /* 2 REG_TXCMD_NOA_SEL_8197F */ -#define BIT_SHIFT_NOA_SEL_8197F 4 -#define BIT_MASK_NOA_SEL_8197F 0x7 -#define BIT_NOA_SEL_8197F(x) (((x) & BIT_MASK_NOA_SEL_8197F) << BIT_SHIFT_NOA_SEL_8197F) -#define BITS_NOA_SEL_8197F (BIT_MASK_NOA_SEL_8197F << BIT_SHIFT_NOA_SEL_8197F) -#define BIT_CLEAR_NOA_SEL_8197F(x) ((x) & (~BITS_NOA_SEL_8197F)) -#define BIT_GET_NOA_SEL_8197F(x) (((x) >> BIT_SHIFT_NOA_SEL_8197F) & BIT_MASK_NOA_SEL_8197F) -#define BIT_SET_NOA_SEL_8197F(x, v) (BIT_CLEAR_NOA_SEL_8197F(x) | BIT_NOA_SEL_8197F(v)) - +#define BIT_SHIFT_NOA_SEL_V2_8197F 4 +#define BIT_MASK_NOA_SEL_V2_8197F 0x7 +#define BIT_NOA_SEL_V2_8197F(x) \ + (((x) & BIT_MASK_NOA_SEL_V2_8197F) << BIT_SHIFT_NOA_SEL_V2_8197F) +#define BITS_NOA_SEL_V2_8197F \ + (BIT_MASK_NOA_SEL_V2_8197F << BIT_SHIFT_NOA_SEL_V2_8197F) +#define BIT_CLEAR_NOA_SEL_V2_8197F(x) ((x) & (~BITS_NOA_SEL_V2_8197F)) +#define BIT_GET_NOA_SEL_V2_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V2_8197F) & BIT_MASK_NOA_SEL_V2_8197F) +#define BIT_SET_NOA_SEL_V2_8197F(x, v) \ + (BIT_CLEAR_NOA_SEL_V2_8197F(x) | BIT_NOA_SEL_V2_8197F(v)) #define BIT_SHIFT_TXCMD_SEG_SEL_8197F 0 #define BIT_MASK_TXCMD_SEG_SEL_8197F 0xf -#define BIT_TXCMD_SEG_SEL_8197F(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8197F) << BIT_SHIFT_TXCMD_SEG_SEL_8197F) -#define BITS_TXCMD_SEG_SEL_8197F (BIT_MASK_TXCMD_SEG_SEL_8197F << BIT_SHIFT_TXCMD_SEG_SEL_8197F) +#define BIT_TXCMD_SEG_SEL_8197F(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL_8197F) << BIT_SHIFT_TXCMD_SEG_SEL_8197F) +#define BITS_TXCMD_SEG_SEL_8197F \ + (BIT_MASK_TXCMD_SEG_SEL_8197F << BIT_SHIFT_TXCMD_SEG_SEL_8197F) #define BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) ((x) & (~BITS_TXCMD_SEG_SEL_8197F)) -#define BIT_GET_TXCMD_SEG_SEL_8197F(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8197F) & BIT_MASK_TXCMD_SEG_SEL_8197F) -#define BIT_SET_TXCMD_SEG_SEL_8197F(x, v) (BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) | BIT_TXCMD_SEG_SEL_8197F(v)) - +#define BIT_GET_TXCMD_SEG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8197F) & BIT_MASK_TXCMD_SEG_SEL_8197F) +#define BIT_SET_TXCMD_SEG_SEL_8197F(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) | BIT_TXCMD_SEG_SEL_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_BCNERR_CNT_EN_8197F BIT(20) #define BIT_SHIFT_BCNERR_PORT_SEL_8197F 16 #define BIT_MASK_BCNERR_PORT_SEL_8197F 0x7 -#define BIT_BCNERR_PORT_SEL_8197F(x) (((x) & BIT_MASK_BCNERR_PORT_SEL_8197F) << BIT_SHIFT_BCNERR_PORT_SEL_8197F) -#define BITS_BCNERR_PORT_SEL_8197F (BIT_MASK_BCNERR_PORT_SEL_8197F << BIT_SHIFT_BCNERR_PORT_SEL_8197F) +#define BIT_BCNERR_PORT_SEL_8197F(x) \ + (((x) & BIT_MASK_BCNERR_PORT_SEL_8197F) \ + << BIT_SHIFT_BCNERR_PORT_SEL_8197F) +#define BITS_BCNERR_PORT_SEL_8197F \ + (BIT_MASK_BCNERR_PORT_SEL_8197F << BIT_SHIFT_BCNERR_PORT_SEL_8197F) #define BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) ((x) & (~BITS_BCNERR_PORT_SEL_8197F)) -#define BIT_GET_BCNERR_PORT_SEL_8197F(x) (((x) >> BIT_SHIFT_BCNERR_PORT_SEL_8197F) & BIT_MASK_BCNERR_PORT_SEL_8197F) -#define BIT_SET_BCNERR_PORT_SEL_8197F(x, v) (BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) | BIT_BCNERR_PORT_SEL_8197F(v)) - +#define BIT_GET_BCNERR_PORT_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_BCNERR_PORT_SEL_8197F) & \ + BIT_MASK_BCNERR_PORT_SEL_8197F) +#define BIT_SET_BCNERR_PORT_SEL_8197F(x, v) \ + (BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) | BIT_BCNERR_PORT_SEL_8197F(v)) #define BIT_SHIFT_TXPAUSE1_8197F 8 #define BIT_MASK_TXPAUSE1_8197F 0xff -#define BIT_TXPAUSE1_8197F(x) (((x) & BIT_MASK_TXPAUSE1_8197F) << BIT_SHIFT_TXPAUSE1_8197F) -#define BITS_TXPAUSE1_8197F (BIT_MASK_TXPAUSE1_8197F << BIT_SHIFT_TXPAUSE1_8197F) +#define BIT_TXPAUSE1_8197F(x) \ + (((x) & BIT_MASK_TXPAUSE1_8197F) << BIT_SHIFT_TXPAUSE1_8197F) +#define BITS_TXPAUSE1_8197F \ + (BIT_MASK_TXPAUSE1_8197F << BIT_SHIFT_TXPAUSE1_8197F) #define BIT_CLEAR_TXPAUSE1_8197F(x) ((x) & (~BITS_TXPAUSE1_8197F)) -#define BIT_GET_TXPAUSE1_8197F(x) (((x) >> BIT_SHIFT_TXPAUSE1_8197F) & BIT_MASK_TXPAUSE1_8197F) -#define BIT_SET_TXPAUSE1_8197F(x, v) (BIT_CLEAR_TXPAUSE1_8197F(x) | BIT_TXPAUSE1_8197F(v)) - +#define BIT_GET_TXPAUSE1_8197F(x) \ + (((x) >> BIT_SHIFT_TXPAUSE1_8197F) & BIT_MASK_TXPAUSE1_8197F) +#define BIT_SET_TXPAUSE1_8197F(x, v) \ + (BIT_CLEAR_TXPAUSE1_8197F(x) | BIT_TXPAUSE1_8197F(v)) #define BIT_SHIFT_BW_CFG_8197F 0 #define BIT_MASK_BW_CFG_8197F 0x3 -#define BIT_BW_CFG_8197F(x) (((x) & BIT_MASK_BW_CFG_8197F) << BIT_SHIFT_BW_CFG_8197F) +#define BIT_BW_CFG_8197F(x) \ + (((x) & BIT_MASK_BW_CFG_8197F) << BIT_SHIFT_BW_CFG_8197F) #define BITS_BW_CFG_8197F (BIT_MASK_BW_CFG_8197F << BIT_SHIFT_BW_CFG_8197F) #define BIT_CLEAR_BW_CFG_8197F(x) ((x) & (~BITS_BW_CFG_8197F)) -#define BIT_GET_BW_CFG_8197F(x) (((x) >> BIT_SHIFT_BW_CFG_8197F) & BIT_MASK_BW_CFG_8197F) -#define BIT_SET_BW_CFG_8197F(x, v) (BIT_CLEAR_BW_CFG_8197F(x) | BIT_BW_CFG_8197F(v)) - +#define BIT_GET_BW_CFG_8197F(x) \ + (((x) >> BIT_SHIFT_BW_CFG_8197F) & BIT_MASK_BW_CFG_8197F) +#define BIT_SET_BW_CFG_8197F(x, v) \ + (BIT_CLEAR_BW_CFG_8197F(x) | BIT_BW_CFG_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_RXBCN_TIMER_8197F 16 #define BIT_MASK_RXBCN_TIMER_8197F 0xffff -#define BIT_RXBCN_TIMER_8197F(x) (((x) & BIT_MASK_RXBCN_TIMER_8197F) << BIT_SHIFT_RXBCN_TIMER_8197F) -#define BITS_RXBCN_TIMER_8197F (BIT_MASK_RXBCN_TIMER_8197F << BIT_SHIFT_RXBCN_TIMER_8197F) +#define BIT_RXBCN_TIMER_8197F(x) \ + (((x) & BIT_MASK_RXBCN_TIMER_8197F) << BIT_SHIFT_RXBCN_TIMER_8197F) +#define BITS_RXBCN_TIMER_8197F \ + (BIT_MASK_RXBCN_TIMER_8197F << BIT_SHIFT_RXBCN_TIMER_8197F) #define BIT_CLEAR_RXBCN_TIMER_8197F(x) ((x) & (~BITS_RXBCN_TIMER_8197F)) -#define BIT_GET_RXBCN_TIMER_8197F(x) (((x) >> BIT_SHIFT_RXBCN_TIMER_8197F) & BIT_MASK_RXBCN_TIMER_8197F) -#define BIT_SET_RXBCN_TIMER_8197F(x, v) (BIT_CLEAR_RXBCN_TIMER_8197F(x) | BIT_RXBCN_TIMER_8197F(v)) - +#define BIT_GET_RXBCN_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_RXBCN_TIMER_8197F) & BIT_MASK_RXBCN_TIMER_8197F) +#define BIT_SET_RXBCN_TIMER_8197F(x, v) \ + (BIT_CLEAR_RXBCN_TIMER_8197F(x) | BIT_RXBCN_TIMER_8197F(v)) #define BIT_SHIFT_BCN_ELY_ADJ_8197F 0 #define BIT_MASK_BCN_ELY_ADJ_8197F 0xffff -#define BIT_BCN_ELY_ADJ_8197F(x) (((x) & BIT_MASK_BCN_ELY_ADJ_8197F) << BIT_SHIFT_BCN_ELY_ADJ_8197F) -#define BITS_BCN_ELY_ADJ_8197F (BIT_MASK_BCN_ELY_ADJ_8197F << BIT_SHIFT_BCN_ELY_ADJ_8197F) +#define BIT_BCN_ELY_ADJ_8197F(x) \ + (((x) & BIT_MASK_BCN_ELY_ADJ_8197F) << BIT_SHIFT_BCN_ELY_ADJ_8197F) +#define BITS_BCN_ELY_ADJ_8197F \ + (BIT_MASK_BCN_ELY_ADJ_8197F << BIT_SHIFT_BCN_ELY_ADJ_8197F) #define BIT_CLEAR_BCN_ELY_ADJ_8197F(x) ((x) & (~BITS_BCN_ELY_ADJ_8197F)) -#define BIT_GET_BCN_ELY_ADJ_8197F(x) (((x) >> BIT_SHIFT_BCN_ELY_ADJ_8197F) & BIT_MASK_BCN_ELY_ADJ_8197F) -#define BIT_SET_BCN_ELY_ADJ_8197F(x, v) (BIT_CLEAR_BCN_ELY_ADJ_8197F(x) | BIT_BCN_ELY_ADJ_8197F(v)) - +#define BIT_GET_BCN_ELY_ADJ_8197F(x) \ + (((x) >> BIT_SHIFT_BCN_ELY_ADJ_8197F) & BIT_MASK_BCN_ELY_ADJ_8197F) +#define BIT_SET_BCN_ELY_ADJ_8197F(x, v) \ + (BIT_CLEAR_BCN_ELY_ADJ_8197F(x) | BIT_BCN_ELY_ADJ_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_BCNERR_CNT_OTHERS_8197F 24 #define BIT_MASK_BCNERR_CNT_OTHERS_8197F 0xff -#define BIT_BCNERR_CNT_OTHERS_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_OTHERS_8197F) << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) -#define BITS_BCNERR_CNT_OTHERS_8197F (BIT_MASK_BCNERR_CNT_OTHERS_8197F << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) -#define BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) ((x) & (~BITS_BCNERR_CNT_OTHERS_8197F)) -#define BIT_GET_BCNERR_CNT_OTHERS_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) & BIT_MASK_BCNERR_CNT_OTHERS_8197F) -#define BIT_SET_BCNERR_CNT_OTHERS_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) | BIT_BCNERR_CNT_OTHERS_8197F(v)) - +#define BIT_BCNERR_CNT_OTHERS_8197F(x) \ + (((x) & BIT_MASK_BCNERR_CNT_OTHERS_8197F) \ + << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) +#define BITS_BCNERR_CNT_OTHERS_8197F \ + (BIT_MASK_BCNERR_CNT_OTHERS_8197F << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) +#define BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) \ + ((x) & (~BITS_BCNERR_CNT_OTHERS_8197F)) +#define BIT_GET_BCNERR_CNT_OTHERS_8197F(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) & \ + BIT_MASK_BCNERR_CNT_OTHERS_8197F) +#define BIT_SET_BCNERR_CNT_OTHERS_8197F(x, v) \ + (BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) | BIT_BCNERR_CNT_OTHERS_8197F(v)) #define BIT_SHIFT_BCNERR_CNT_INVALID_8197F 16 #define BIT_MASK_BCNERR_CNT_INVALID_8197F 0xff -#define BIT_BCNERR_CNT_INVALID_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_INVALID_8197F) << BIT_SHIFT_BCNERR_CNT_INVALID_8197F) -#define BITS_BCNERR_CNT_INVALID_8197F (BIT_MASK_BCNERR_CNT_INVALID_8197F << BIT_SHIFT_BCNERR_CNT_INVALID_8197F) -#define BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) ((x) & (~BITS_BCNERR_CNT_INVALID_8197F)) -#define BIT_GET_BCNERR_CNT_INVALID_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8197F) & BIT_MASK_BCNERR_CNT_INVALID_8197F) -#define BIT_SET_BCNERR_CNT_INVALID_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) | BIT_BCNERR_CNT_INVALID_8197F(v)) - +#define BIT_BCNERR_CNT_INVALID_8197F(x) \ + (((x) & BIT_MASK_BCNERR_CNT_INVALID_8197F) \ + << BIT_SHIFT_BCNERR_CNT_INVALID_8197F) +#define BITS_BCNERR_CNT_INVALID_8197F \ + (BIT_MASK_BCNERR_CNT_INVALID_8197F \ + << BIT_SHIFT_BCNERR_CNT_INVALID_8197F) +#define BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) \ + ((x) & (~BITS_BCNERR_CNT_INVALID_8197F)) +#define BIT_GET_BCNERR_CNT_INVALID_8197F(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8197F) & \ + BIT_MASK_BCNERR_CNT_INVALID_8197F) +#define BIT_SET_BCNERR_CNT_INVALID_8197F(x, v) \ + (BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) | \ + BIT_BCNERR_CNT_INVALID_8197F(v)) #define BIT_SHIFT_BCNERR_CNT_MAC_8197F 8 #define BIT_MASK_BCNERR_CNT_MAC_8197F 0xff -#define BIT_BCNERR_CNT_MAC_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_MAC_8197F) << BIT_SHIFT_BCNERR_CNT_MAC_8197F) -#define BITS_BCNERR_CNT_MAC_8197F (BIT_MASK_BCNERR_CNT_MAC_8197F << BIT_SHIFT_BCNERR_CNT_MAC_8197F) +#define BIT_BCNERR_CNT_MAC_8197F(x) \ + (((x) & BIT_MASK_BCNERR_CNT_MAC_8197F) \ + << BIT_SHIFT_BCNERR_CNT_MAC_8197F) +#define BITS_BCNERR_CNT_MAC_8197F \ + (BIT_MASK_BCNERR_CNT_MAC_8197F << BIT_SHIFT_BCNERR_CNT_MAC_8197F) #define BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) ((x) & (~BITS_BCNERR_CNT_MAC_8197F)) -#define BIT_GET_BCNERR_CNT_MAC_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8197F) & BIT_MASK_BCNERR_CNT_MAC_8197F) -#define BIT_SET_BCNERR_CNT_MAC_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) | BIT_BCNERR_CNT_MAC_8197F(v)) - +#define BIT_GET_BCNERR_CNT_MAC_8197F(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8197F) & \ + BIT_MASK_BCNERR_CNT_MAC_8197F) +#define BIT_SET_BCNERR_CNT_MAC_8197F(x, v) \ + (BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) | BIT_BCNERR_CNT_MAC_8197F(v)) #define BIT_SHIFT_BCNERR_CNT_CCA_8197F 0 #define BIT_MASK_BCNERR_CNT_CCA_8197F 0xff -#define BIT_BCNERR_CNT_CCA_8197F(x) (((x) & BIT_MASK_BCNERR_CNT_CCA_8197F) << BIT_SHIFT_BCNERR_CNT_CCA_8197F) -#define BITS_BCNERR_CNT_CCA_8197F (BIT_MASK_BCNERR_CNT_CCA_8197F << BIT_SHIFT_BCNERR_CNT_CCA_8197F) +#define BIT_BCNERR_CNT_CCA_8197F(x) \ + (((x) & BIT_MASK_BCNERR_CNT_CCA_8197F) \ + << BIT_SHIFT_BCNERR_CNT_CCA_8197F) +#define BITS_BCNERR_CNT_CCA_8197F \ + (BIT_MASK_BCNERR_CNT_CCA_8197F << BIT_SHIFT_BCNERR_CNT_CCA_8197F) #define BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) ((x) & (~BITS_BCNERR_CNT_CCA_8197F)) -#define BIT_GET_BCNERR_CNT_CCA_8197F(x) (((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8197F) & BIT_MASK_BCNERR_CNT_CCA_8197F) -#define BIT_SET_BCNERR_CNT_CCA_8197F(x, v) (BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) | BIT_BCNERR_CNT_CCA_8197F(v)) - +#define BIT_GET_BCNERR_CNT_CCA_8197F(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8197F) & \ + BIT_MASK_BCNERR_CNT_CCA_8197F) +#define BIT_SET_BCNERR_CNT_CCA_8197F(x, v) \ + (BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) | BIT_BCNERR_CNT_CCA_8197F(v)) /* 2 REG_NOA_PARAM_8197F */ #define BIT_SHIFT_NOA_COUNT_8197F (96 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_COUNT_8197F 0xff -#define BIT_NOA_COUNT_8197F(x) (((x) & BIT_MASK_NOA_COUNT_8197F) << BIT_SHIFT_NOA_COUNT_8197F) -#define BITS_NOA_COUNT_8197F (BIT_MASK_NOA_COUNT_8197F << BIT_SHIFT_NOA_COUNT_8197F) +#define BIT_NOA_COUNT_8197F(x) \ + (((x) & BIT_MASK_NOA_COUNT_8197F) << BIT_SHIFT_NOA_COUNT_8197F) +#define BITS_NOA_COUNT_8197F \ + (BIT_MASK_NOA_COUNT_8197F << BIT_SHIFT_NOA_COUNT_8197F) #define BIT_CLEAR_NOA_COUNT_8197F(x) ((x) & (~BITS_NOA_COUNT_8197F)) -#define BIT_GET_NOA_COUNT_8197F(x) (((x) >> BIT_SHIFT_NOA_COUNT_8197F) & BIT_MASK_NOA_COUNT_8197F) -#define BIT_SET_NOA_COUNT_8197F(x, v) (BIT_CLEAR_NOA_COUNT_8197F(x) | BIT_NOA_COUNT_8197F(v)) - +#define BIT_GET_NOA_COUNT_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_8197F) & BIT_MASK_NOA_COUNT_8197F) +#define BIT_SET_NOA_COUNT_8197F(x, v) \ + (BIT_CLEAR_NOA_COUNT_8197F(x) | BIT_NOA_COUNT_8197F(v)) #define BIT_SHIFT_NOA_START_TIME_8197F (64 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_START_TIME_8197F 0xffffffffL -#define BIT_NOA_START_TIME_8197F(x) (((x) & BIT_MASK_NOA_START_TIME_8197F) << BIT_SHIFT_NOA_START_TIME_8197F) -#define BITS_NOA_START_TIME_8197F (BIT_MASK_NOA_START_TIME_8197F << BIT_SHIFT_NOA_START_TIME_8197F) +#define BIT_NOA_START_TIME_8197F(x) \ + (((x) & BIT_MASK_NOA_START_TIME_8197F) \ + << BIT_SHIFT_NOA_START_TIME_8197F) +#define BITS_NOA_START_TIME_8197F \ + (BIT_MASK_NOA_START_TIME_8197F << BIT_SHIFT_NOA_START_TIME_8197F) #define BIT_CLEAR_NOA_START_TIME_8197F(x) ((x) & (~BITS_NOA_START_TIME_8197F)) -#define BIT_GET_NOA_START_TIME_8197F(x) (((x) >> BIT_SHIFT_NOA_START_TIME_8197F) & BIT_MASK_NOA_START_TIME_8197F) -#define BIT_SET_NOA_START_TIME_8197F(x, v) (BIT_CLEAR_NOA_START_TIME_8197F(x) | BIT_NOA_START_TIME_8197F(v)) - +#define BIT_GET_NOA_START_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_8197F) & \ + BIT_MASK_NOA_START_TIME_8197F) +#define BIT_SET_NOA_START_TIME_8197F(x, v) \ + (BIT_CLEAR_NOA_START_TIME_8197F(x) | BIT_NOA_START_TIME_8197F(v)) #define BIT_SHIFT_NOA_INTERVAL_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_INTERVAL_8197F 0xffffffffL -#define BIT_NOA_INTERVAL_8197F(x) (((x) & BIT_MASK_NOA_INTERVAL_8197F) << BIT_SHIFT_NOA_INTERVAL_8197F) -#define BITS_NOA_INTERVAL_8197F (BIT_MASK_NOA_INTERVAL_8197F << BIT_SHIFT_NOA_INTERVAL_8197F) +#define BIT_NOA_INTERVAL_8197F(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_8197F) << BIT_SHIFT_NOA_INTERVAL_8197F) +#define BITS_NOA_INTERVAL_8197F \ + (BIT_MASK_NOA_INTERVAL_8197F << BIT_SHIFT_NOA_INTERVAL_8197F) #define BIT_CLEAR_NOA_INTERVAL_8197F(x) ((x) & (~BITS_NOA_INTERVAL_8197F)) -#define BIT_GET_NOA_INTERVAL_8197F(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_8197F) & BIT_MASK_NOA_INTERVAL_8197F) -#define BIT_SET_NOA_INTERVAL_8197F(x, v) (BIT_CLEAR_NOA_INTERVAL_8197F(x) | BIT_NOA_INTERVAL_8197F(v)) - +#define BIT_GET_NOA_INTERVAL_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_8197F) & BIT_MASK_NOA_INTERVAL_8197F) +#define BIT_SET_NOA_INTERVAL_8197F(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_8197F(x) | BIT_NOA_INTERVAL_8197F(v)) #define BIT_SHIFT_NOA_DURATION_8197F 0 #define BIT_MASK_NOA_DURATION_8197F 0xffffffffL -#define BIT_NOA_DURATION_8197F(x) (((x) & BIT_MASK_NOA_DURATION_8197F) << BIT_SHIFT_NOA_DURATION_8197F) -#define BITS_NOA_DURATION_8197F (BIT_MASK_NOA_DURATION_8197F << BIT_SHIFT_NOA_DURATION_8197F) +#define BIT_NOA_DURATION_8197F(x) \ + (((x) & BIT_MASK_NOA_DURATION_8197F) << BIT_SHIFT_NOA_DURATION_8197F) +#define BITS_NOA_DURATION_8197F \ + (BIT_MASK_NOA_DURATION_8197F << BIT_SHIFT_NOA_DURATION_8197F) #define BIT_CLEAR_NOA_DURATION_8197F(x) ((x) & (~BITS_NOA_DURATION_8197F)) -#define BIT_GET_NOA_DURATION_8197F(x) (((x) >> BIT_SHIFT_NOA_DURATION_8197F) & BIT_MASK_NOA_DURATION_8197F) -#define BIT_SET_NOA_DURATION_8197F(x, v) (BIT_CLEAR_NOA_DURATION_8197F(x) | BIT_NOA_DURATION_8197F(v)) - +#define BIT_GET_NOA_DURATION_8197F(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_8197F) & BIT_MASK_NOA_DURATION_8197F) +#define BIT_SET_NOA_DURATION_8197F(x, v) \ + (BIT_CLEAR_NOA_DURATION_8197F(x) | BIT_NOA_DURATION_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -9922,12 +12993,15 @@ #define BIT_SHIFT_SCH_TXCMD_8197F 0 #define BIT_MASK_SCH_TXCMD_8197F 0xffffffffL -#define BIT_SCH_TXCMD_8197F(x) (((x) & BIT_MASK_SCH_TXCMD_8197F) << BIT_SHIFT_SCH_TXCMD_8197F) -#define BITS_SCH_TXCMD_8197F (BIT_MASK_SCH_TXCMD_8197F << BIT_SHIFT_SCH_TXCMD_8197F) +#define BIT_SCH_TXCMD_8197F(x) \ + (((x) & BIT_MASK_SCH_TXCMD_8197F) << BIT_SHIFT_SCH_TXCMD_8197F) +#define BITS_SCH_TXCMD_8197F \ + (BIT_MASK_SCH_TXCMD_8197F << BIT_SHIFT_SCH_TXCMD_8197F) #define BIT_CLEAR_SCH_TXCMD_8197F(x) ((x) & (~BITS_SCH_TXCMD_8197F)) -#define BIT_GET_SCH_TXCMD_8197F(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8197F) & BIT_MASK_SCH_TXCMD_8197F) -#define BIT_SET_SCH_TXCMD_8197F(x, v) (BIT_CLEAR_SCH_TXCMD_8197F(x) | BIT_SCH_TXCMD_8197F(v)) - +#define BIT_GET_SCH_TXCMD_8197F(x) \ + (((x) >> BIT_SHIFT_SCH_TXCMD_8197F) & BIT_MASK_SCH_TXCMD_8197F) +#define BIT_SET_SCH_TXCMD_8197F(x, v) \ + (BIT_CLEAR_SCH_TXCMD_8197F(x) | BIT_SCH_TXCMD_8197F(v)) /* 2 REG_PAGE5_DUMMY_8197F */ @@ -9935,45 +13009,62 @@ #define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F 0 #define BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F 0xffffffffL -#define BIT_CPUMGQ_TX_TIMER_V1_8197F(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) -#define BITS_CPUMGQ_TX_TIMER_V1_8197F (BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) -#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8197F)) -#define BIT_GET_CPUMGQ_TX_TIMER_V1_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F) -#define BIT_SET_CPUMGQ_TX_TIMER_V1_8197F(x, v) (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) | BIT_CPUMGQ_TX_TIMER_V1_8197F(v)) - +#define BIT_CPUMGQ_TX_TIMER_V1_8197F(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) +#define BITS_CPUMGQ_TX_TIMER_V1_8197F \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8197F)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8197F(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) & \ + BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F) +#define BIT_SET_CPUMGQ_TX_TIMER_V1_8197F(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) | \ + BIT_CPUMGQ_TX_TIMER_V1_8197F(v)) /* 2 REG_PS_TIMER_A_8197F */ #define BIT_SHIFT_PS_TIMER_A_V1_8197F 0 #define BIT_MASK_PS_TIMER_A_V1_8197F 0xffffffffL -#define BIT_PS_TIMER_A_V1_8197F(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8197F) << BIT_SHIFT_PS_TIMER_A_V1_8197F) -#define BITS_PS_TIMER_A_V1_8197F (BIT_MASK_PS_TIMER_A_V1_8197F << BIT_SHIFT_PS_TIMER_A_V1_8197F) +#define BIT_PS_TIMER_A_V1_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_A_V1_8197F) << BIT_SHIFT_PS_TIMER_A_V1_8197F) +#define BITS_PS_TIMER_A_V1_8197F \ + (BIT_MASK_PS_TIMER_A_V1_8197F << BIT_SHIFT_PS_TIMER_A_V1_8197F) #define BIT_CLEAR_PS_TIMER_A_V1_8197F(x) ((x) & (~BITS_PS_TIMER_A_V1_8197F)) -#define BIT_GET_PS_TIMER_A_V1_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8197F) & BIT_MASK_PS_TIMER_A_V1_8197F) -#define BIT_SET_PS_TIMER_A_V1_8197F(x, v) (BIT_CLEAR_PS_TIMER_A_V1_8197F(x) | BIT_PS_TIMER_A_V1_8197F(v)) - +#define BIT_GET_PS_TIMER_A_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8197F) & BIT_MASK_PS_TIMER_A_V1_8197F) +#define BIT_SET_PS_TIMER_A_V1_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_A_V1_8197F(x) | BIT_PS_TIMER_A_V1_8197F(v)) /* 2 REG_PS_TIMER_B_8197F */ #define BIT_SHIFT_PS_TIMER_B_V1_8197F 0 #define BIT_MASK_PS_TIMER_B_V1_8197F 0xffffffffL -#define BIT_PS_TIMER_B_V1_8197F(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8197F) << BIT_SHIFT_PS_TIMER_B_V1_8197F) -#define BITS_PS_TIMER_B_V1_8197F (BIT_MASK_PS_TIMER_B_V1_8197F << BIT_SHIFT_PS_TIMER_B_V1_8197F) +#define BIT_PS_TIMER_B_V1_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_B_V1_8197F) << BIT_SHIFT_PS_TIMER_B_V1_8197F) +#define BITS_PS_TIMER_B_V1_8197F \ + (BIT_MASK_PS_TIMER_B_V1_8197F << BIT_SHIFT_PS_TIMER_B_V1_8197F) #define BIT_CLEAR_PS_TIMER_B_V1_8197F(x) ((x) & (~BITS_PS_TIMER_B_V1_8197F)) -#define BIT_GET_PS_TIMER_B_V1_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8197F) & BIT_MASK_PS_TIMER_B_V1_8197F) -#define BIT_SET_PS_TIMER_B_V1_8197F(x, v) (BIT_CLEAR_PS_TIMER_B_V1_8197F(x) | BIT_PS_TIMER_B_V1_8197F(v)) - +#define BIT_GET_PS_TIMER_B_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8197F) & BIT_MASK_PS_TIMER_B_V1_8197F) +#define BIT_SET_PS_TIMER_B_V1_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_B_V1_8197F(x) | BIT_PS_TIMER_B_V1_8197F(v)) /* 2 REG_PS_TIMER_C_8197F */ #define BIT_SHIFT_PS_TIMER_C_V1_8197F 0 #define BIT_MASK_PS_TIMER_C_V1_8197F 0xffffffffL -#define BIT_PS_TIMER_C_V1_8197F(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8197F) << BIT_SHIFT_PS_TIMER_C_V1_8197F) -#define BITS_PS_TIMER_C_V1_8197F (BIT_MASK_PS_TIMER_C_V1_8197F << BIT_SHIFT_PS_TIMER_C_V1_8197F) +#define BIT_PS_TIMER_C_V1_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_C_V1_8197F) << BIT_SHIFT_PS_TIMER_C_V1_8197F) +#define BITS_PS_TIMER_C_V1_8197F \ + (BIT_MASK_PS_TIMER_C_V1_8197F << BIT_SHIFT_PS_TIMER_C_V1_8197F) #define BIT_CLEAR_PS_TIMER_C_V1_8197F(x) ((x) & (~BITS_PS_TIMER_C_V1_8197F)) -#define BIT_GET_PS_TIMER_C_V1_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8197F) & BIT_MASK_PS_TIMER_C_V1_8197F) -#define BIT_SET_PS_TIMER_C_V1_8197F(x, v) (BIT_CLEAR_PS_TIMER_C_V1_8197F(x) | BIT_PS_TIMER_C_V1_8197F(v)) - +#define BIT_GET_PS_TIMER_C_V1_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8197F) & BIT_MASK_PS_TIMER_C_V1_8197F) +#define BIT_SET_PS_TIMER_C_V1_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_C_V1_8197F(x) | BIT_PS_TIMER_C_V1_8197F(v)) /* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F */ #define BIT_CPUMGQ_TIMER_EN_8197F BIT(31) @@ -9981,98 +13072,165 @@ #define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F 24 #define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F 0x7 -#define BIT_CPUMGQ_TIMER_TSF_SEL_8197F(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) -#define BITS_CPUMGQ_TIMER_TSF_SEL_8197F (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) -#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8197F)) -#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F) -#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8197F(x, v) (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) | BIT_CPUMGQ_TIMER_TSF_SEL_8197F(v)) +#define BIT_CPUMGQ_TIMER_TSF_SEL_8197F(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) +#define BITS_CPUMGQ_TIMER_TSF_SEL_8197F \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8197F)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8197F(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) | \ + BIT_CPUMGQ_TIMER_TSF_SEL_8197F(v)) #define BIT_PS_TIMER_C_EN_8197F BIT(23) #define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F 16 #define BIT_MASK_PS_TIMER_C_TSF_SEL_8197F 0x7 -#define BIT_PS_TIMER_C_TSF_SEL_8197F(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8197F) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) -#define BITS_PS_TIMER_C_TSF_SEL_8197F (BIT_MASK_PS_TIMER_C_TSF_SEL_8197F << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) -#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8197F)) -#define BIT_GET_PS_TIMER_C_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) & BIT_MASK_PS_TIMER_C_TSF_SEL_8197F) -#define BIT_SET_PS_TIMER_C_TSF_SEL_8197F(x, v) (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) | BIT_PS_TIMER_C_TSF_SEL_8197F(v)) +#define BIT_PS_TIMER_C_TSF_SEL_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8197F) \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) +#define BITS_PS_TIMER_C_TSF_SEL_8197F \ + (BIT_MASK_PS_TIMER_C_TSF_SEL_8197F \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) +#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) \ + ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8197F)) +#define BIT_GET_PS_TIMER_C_TSF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) & \ + BIT_MASK_PS_TIMER_C_TSF_SEL_8197F) +#define BIT_SET_PS_TIMER_C_TSF_SEL_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) | \ + BIT_PS_TIMER_C_TSF_SEL_8197F(v)) #define BIT_PS_TIMER_B_EN_8197F BIT(15) #define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F 8 #define BIT_MASK_PS_TIMER_B_TSF_SEL_8197F 0x7 -#define BIT_PS_TIMER_B_TSF_SEL_8197F(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8197F) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) -#define BITS_PS_TIMER_B_TSF_SEL_8197F (BIT_MASK_PS_TIMER_B_TSF_SEL_8197F << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) -#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8197F)) -#define BIT_GET_PS_TIMER_B_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) & BIT_MASK_PS_TIMER_B_TSF_SEL_8197F) -#define BIT_SET_PS_TIMER_B_TSF_SEL_8197F(x, v) (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) | BIT_PS_TIMER_B_TSF_SEL_8197F(v)) +#define BIT_PS_TIMER_B_TSF_SEL_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8197F) \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) +#define BITS_PS_TIMER_B_TSF_SEL_8197F \ + (BIT_MASK_PS_TIMER_B_TSF_SEL_8197F \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) \ + ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8197F)) +#define BIT_GET_PS_TIMER_B_TSF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) & \ + BIT_MASK_PS_TIMER_B_TSF_SEL_8197F) +#define BIT_SET_PS_TIMER_B_TSF_SEL_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) | \ + BIT_PS_TIMER_B_TSF_SEL_8197F(v)) #define BIT_PS_TIMER_A_EN_8197F BIT(7) #define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F 0 #define BIT_MASK_PS_TIMER_A_TSF_SEL_8197F 0x7 -#define BIT_PS_TIMER_A_TSF_SEL_8197F(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8197F) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) -#define BITS_PS_TIMER_A_TSF_SEL_8197F (BIT_MASK_PS_TIMER_A_TSF_SEL_8197F << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) -#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8197F)) -#define BIT_GET_PS_TIMER_A_TSF_SEL_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) & BIT_MASK_PS_TIMER_A_TSF_SEL_8197F) -#define BIT_SET_PS_TIMER_A_TSF_SEL_8197F(x, v) (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) | BIT_PS_TIMER_A_TSF_SEL_8197F(v)) - +#define BIT_PS_TIMER_A_TSF_SEL_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8197F) \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) +#define BITS_PS_TIMER_A_TSF_SEL_8197F \ + (BIT_MASK_PS_TIMER_A_TSF_SEL_8197F \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) \ + ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8197F)) +#define BIT_GET_PS_TIMER_A_TSF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) & \ + BIT_MASK_PS_TIMER_A_TSF_SEL_8197F) +#define BIT_SET_PS_TIMER_A_TSF_SEL_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) | \ + BIT_PS_TIMER_A_TSF_SEL_8197F(v)) /* 2 REG_CPUMGQ_TX_TIMER_EARLY_8197F */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F 0 #define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F 0xff -#define BIT_CPUMGQ_TX_TIMER_EARLY_8197F(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) -#define BITS_CPUMGQ_TX_TIMER_EARLY_8197F (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) -#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8197F)) -#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F) -#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8197F(x, v) (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) | BIT_CPUMGQ_TX_TIMER_EARLY_8197F(v)) - +#define BIT_CPUMGQ_TX_TIMER_EARLY_8197F(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) +#define BITS_CPUMGQ_TX_TIMER_EARLY_8197F \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8197F)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8197F(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8197F(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_8197F(v)) /* 2 REG_PS_TIMER_A_EARLY_8197F */ #define BIT_SHIFT_PS_TIMER_A_EARLY_8197F 0 #define BIT_MASK_PS_TIMER_A_EARLY_8197F 0xff -#define BIT_PS_TIMER_A_EARLY_8197F(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8197F) << BIT_SHIFT_PS_TIMER_A_EARLY_8197F) -#define BITS_PS_TIMER_A_EARLY_8197F (BIT_MASK_PS_TIMER_A_EARLY_8197F << BIT_SHIFT_PS_TIMER_A_EARLY_8197F) -#define BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) ((x) & (~BITS_PS_TIMER_A_EARLY_8197F)) -#define BIT_GET_PS_TIMER_A_EARLY_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8197F) & BIT_MASK_PS_TIMER_A_EARLY_8197F) -#define BIT_SET_PS_TIMER_A_EARLY_8197F(x, v) (BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) | BIT_PS_TIMER_A_EARLY_8197F(v)) - +#define BIT_PS_TIMER_A_EARLY_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_A_EARLY_8197F) \ + << BIT_SHIFT_PS_TIMER_A_EARLY_8197F) +#define BITS_PS_TIMER_A_EARLY_8197F \ + (BIT_MASK_PS_TIMER_A_EARLY_8197F << BIT_SHIFT_PS_TIMER_A_EARLY_8197F) +#define BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) \ + ((x) & (~BITS_PS_TIMER_A_EARLY_8197F)) +#define BIT_GET_PS_TIMER_A_EARLY_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8197F) & \ + BIT_MASK_PS_TIMER_A_EARLY_8197F) +#define BIT_SET_PS_TIMER_A_EARLY_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) | BIT_PS_TIMER_A_EARLY_8197F(v)) /* 2 REG_PS_TIMER_B_EARLY_8197F */ #define BIT_SHIFT_PS_TIMER_B_EARLY_8197F 0 #define BIT_MASK_PS_TIMER_B_EARLY_8197F 0xff -#define BIT_PS_TIMER_B_EARLY_8197F(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8197F) << BIT_SHIFT_PS_TIMER_B_EARLY_8197F) -#define BITS_PS_TIMER_B_EARLY_8197F (BIT_MASK_PS_TIMER_B_EARLY_8197F << BIT_SHIFT_PS_TIMER_B_EARLY_8197F) -#define BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) ((x) & (~BITS_PS_TIMER_B_EARLY_8197F)) -#define BIT_GET_PS_TIMER_B_EARLY_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8197F) & BIT_MASK_PS_TIMER_B_EARLY_8197F) -#define BIT_SET_PS_TIMER_B_EARLY_8197F(x, v) (BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) | BIT_PS_TIMER_B_EARLY_8197F(v)) - +#define BIT_PS_TIMER_B_EARLY_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_B_EARLY_8197F) \ + << BIT_SHIFT_PS_TIMER_B_EARLY_8197F) +#define BITS_PS_TIMER_B_EARLY_8197F \ + (BIT_MASK_PS_TIMER_B_EARLY_8197F << BIT_SHIFT_PS_TIMER_B_EARLY_8197F) +#define BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) \ + ((x) & (~BITS_PS_TIMER_B_EARLY_8197F)) +#define BIT_GET_PS_TIMER_B_EARLY_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8197F) & \ + BIT_MASK_PS_TIMER_B_EARLY_8197F) +#define BIT_SET_PS_TIMER_B_EARLY_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) | BIT_PS_TIMER_B_EARLY_8197F(v)) /* 2 REG_PS_TIMER_C_EARLY_8197F */ #define BIT_SHIFT_PS_TIMER_C_EARLY_8197F 0 #define BIT_MASK_PS_TIMER_C_EARLY_8197F 0xff -#define BIT_PS_TIMER_C_EARLY_8197F(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8197F) << BIT_SHIFT_PS_TIMER_C_EARLY_8197F) -#define BITS_PS_TIMER_C_EARLY_8197F (BIT_MASK_PS_TIMER_C_EARLY_8197F << BIT_SHIFT_PS_TIMER_C_EARLY_8197F) -#define BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) ((x) & (~BITS_PS_TIMER_C_EARLY_8197F)) -#define BIT_GET_PS_TIMER_C_EARLY_8197F(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8197F) & BIT_MASK_PS_TIMER_C_EARLY_8197F) -#define BIT_SET_PS_TIMER_C_EARLY_8197F(x, v) (BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) | BIT_PS_TIMER_C_EARLY_8197F(v)) - +#define BIT_PS_TIMER_C_EARLY_8197F(x) \ + (((x) & BIT_MASK_PS_TIMER_C_EARLY_8197F) \ + << BIT_SHIFT_PS_TIMER_C_EARLY_8197F) +#define BITS_PS_TIMER_C_EARLY_8197F \ + (BIT_MASK_PS_TIMER_C_EARLY_8197F << BIT_SHIFT_PS_TIMER_C_EARLY_8197F) +#define BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) \ + ((x) & (~BITS_PS_TIMER_C_EARLY_8197F)) +#define BIT_GET_PS_TIMER_C_EARLY_8197F(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8197F) & \ + BIT_MASK_PS_TIMER_C_EARLY_8197F) +#define BIT_SET_PS_TIMER_C_EARLY_8197F(x, v) \ + (BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) | BIT_PS_TIMER_C_EARLY_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_STOP_CPUMGQ_8197F BIT(16) #define BIT_SHIFT_CPUMGQ_PARAMETER_8197F 0 #define BIT_MASK_CPUMGQ_PARAMETER_8197F 0xffff -#define BIT_CPUMGQ_PARAMETER_8197F(x) (((x) & BIT_MASK_CPUMGQ_PARAMETER_8197F) << BIT_SHIFT_CPUMGQ_PARAMETER_8197F) -#define BITS_CPUMGQ_PARAMETER_8197F (BIT_MASK_CPUMGQ_PARAMETER_8197F << BIT_SHIFT_CPUMGQ_PARAMETER_8197F) -#define BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) ((x) & (~BITS_CPUMGQ_PARAMETER_8197F)) -#define BIT_GET_CPUMGQ_PARAMETER_8197F(x) (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER_8197F) & BIT_MASK_CPUMGQ_PARAMETER_8197F) -#define BIT_SET_CPUMGQ_PARAMETER_8197F(x, v) (BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) | BIT_CPUMGQ_PARAMETER_8197F(v)) - +#define BIT_CPUMGQ_PARAMETER_8197F(x) \ + (((x) & BIT_MASK_CPUMGQ_PARAMETER_8197F) \ + << BIT_SHIFT_CPUMGQ_PARAMETER_8197F) +#define BITS_CPUMGQ_PARAMETER_8197F \ + (BIT_MASK_CPUMGQ_PARAMETER_8197F << BIT_SHIFT_CPUMGQ_PARAMETER_8197F) +#define BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) \ + ((x) & (~BITS_CPUMGQ_PARAMETER_8197F)) +#define BIT_GET_CPUMGQ_PARAMETER_8197F(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER_8197F) & \ + BIT_MASK_CPUMGQ_PARAMETER_8197F) +#define BIT_SET_CPUMGQ_PARAMETER_8197F(x, v) \ + (BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) | BIT_CPUMGQ_PARAMETER_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -10086,12 +13244,17 @@ #define BIT_SHIFT_APPEND_MHDR_LEN_8197F 0 #define BIT_MASK_APPEND_MHDR_LEN_8197F 0x7 -#define BIT_APPEND_MHDR_LEN_8197F(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8197F) << BIT_SHIFT_APPEND_MHDR_LEN_8197F) -#define BITS_APPEND_MHDR_LEN_8197F (BIT_MASK_APPEND_MHDR_LEN_8197F << BIT_SHIFT_APPEND_MHDR_LEN_8197F) +#define BIT_APPEND_MHDR_LEN_8197F(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN_8197F) \ + << BIT_SHIFT_APPEND_MHDR_LEN_8197F) +#define BITS_APPEND_MHDR_LEN_8197F \ + (BIT_MASK_APPEND_MHDR_LEN_8197F << BIT_SHIFT_APPEND_MHDR_LEN_8197F) #define BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) ((x) & (~BITS_APPEND_MHDR_LEN_8197F)) -#define BIT_GET_APPEND_MHDR_LEN_8197F(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8197F) & BIT_MASK_APPEND_MHDR_LEN_8197F) -#define BIT_SET_APPEND_MHDR_LEN_8197F(x, v) (BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) | BIT_APPEND_MHDR_LEN_8197F(v)) - +#define BIT_GET_APPEND_MHDR_LEN_8197F(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8197F) & \ + BIT_MASK_APPEND_MHDR_LEN_8197F) +#define BIT_SET_APPEND_MHDR_LEN_8197F(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) | BIT_APPEND_MHDR_LEN_8197F(v)) /* 2 REG_WMAC_CR_8197F (WMAC CR AND APSD CONTROL REGISTER) */ #define BIT_APSDOFF_8197F BIT(6) @@ -10167,56 +13330,69 @@ #define BIT_SHIFT_DRVINFO_SZ_V1_8197F 0 #define BIT_MASK_DRVINFO_SZ_V1_8197F 0xf -#define BIT_DRVINFO_SZ_V1_8197F(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8197F) << BIT_SHIFT_DRVINFO_SZ_V1_8197F) -#define BITS_DRVINFO_SZ_V1_8197F (BIT_MASK_DRVINFO_SZ_V1_8197F << BIT_SHIFT_DRVINFO_SZ_V1_8197F) +#define BIT_DRVINFO_SZ_V1_8197F(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1_8197F) << BIT_SHIFT_DRVINFO_SZ_V1_8197F) +#define BITS_DRVINFO_SZ_V1_8197F \ + (BIT_MASK_DRVINFO_SZ_V1_8197F << BIT_SHIFT_DRVINFO_SZ_V1_8197F) #define BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) ((x) & (~BITS_DRVINFO_SZ_V1_8197F)) -#define BIT_GET_DRVINFO_SZ_V1_8197F(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8197F) & BIT_MASK_DRVINFO_SZ_V1_8197F) -#define BIT_SET_DRVINFO_SZ_V1_8197F(x, v) (BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) | BIT_DRVINFO_SZ_V1_8197F(v)) - +#define BIT_GET_DRVINFO_SZ_V1_8197F(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8197F) & BIT_MASK_DRVINFO_SZ_V1_8197F) +#define BIT_SET_DRVINFO_SZ_V1_8197F(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) | BIT_DRVINFO_SZ_V1_8197F(v)) /* 2 REG_RX_DLK_TIME_8197F (RX DEADLOCK TIME REGISTER) */ #define BIT_SHIFT_RX_DLK_TIME_8197F 0 #define BIT_MASK_RX_DLK_TIME_8197F 0xff -#define BIT_RX_DLK_TIME_8197F(x) (((x) & BIT_MASK_RX_DLK_TIME_8197F) << BIT_SHIFT_RX_DLK_TIME_8197F) -#define BITS_RX_DLK_TIME_8197F (BIT_MASK_RX_DLK_TIME_8197F << BIT_SHIFT_RX_DLK_TIME_8197F) +#define BIT_RX_DLK_TIME_8197F(x) \ + (((x) & BIT_MASK_RX_DLK_TIME_8197F) << BIT_SHIFT_RX_DLK_TIME_8197F) +#define BITS_RX_DLK_TIME_8197F \ + (BIT_MASK_RX_DLK_TIME_8197F << BIT_SHIFT_RX_DLK_TIME_8197F) #define BIT_CLEAR_RX_DLK_TIME_8197F(x) ((x) & (~BITS_RX_DLK_TIME_8197F)) -#define BIT_GET_RX_DLK_TIME_8197F(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8197F) & BIT_MASK_RX_DLK_TIME_8197F) -#define BIT_SET_RX_DLK_TIME_8197F(x, v) (BIT_CLEAR_RX_DLK_TIME_8197F(x) | BIT_RX_DLK_TIME_8197F(v)) - +#define BIT_GET_RX_DLK_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME_8197F) & BIT_MASK_RX_DLK_TIME_8197F) +#define BIT_SET_RX_DLK_TIME_8197F(x, v) \ + (BIT_CLEAR_RX_DLK_TIME_8197F(x) | BIT_RX_DLK_TIME_8197F(v)) /* 2 REG_RX_PKT_LIMIT_8197F (RX PACKET LENGTH LIMIT REGISTER) */ #define BIT_SHIFT_RXPKTLMT_8197F 0 #define BIT_MASK_RXPKTLMT_8197F 0x3f -#define BIT_RXPKTLMT_8197F(x) (((x) & BIT_MASK_RXPKTLMT_8197F) << BIT_SHIFT_RXPKTLMT_8197F) -#define BITS_RXPKTLMT_8197F (BIT_MASK_RXPKTLMT_8197F << BIT_SHIFT_RXPKTLMT_8197F) +#define BIT_RXPKTLMT_8197F(x) \ + (((x) & BIT_MASK_RXPKTLMT_8197F) << BIT_SHIFT_RXPKTLMT_8197F) +#define BITS_RXPKTLMT_8197F \ + (BIT_MASK_RXPKTLMT_8197F << BIT_SHIFT_RXPKTLMT_8197F) #define BIT_CLEAR_RXPKTLMT_8197F(x) ((x) & (~BITS_RXPKTLMT_8197F)) -#define BIT_GET_RXPKTLMT_8197F(x) (((x) >> BIT_SHIFT_RXPKTLMT_8197F) & BIT_MASK_RXPKTLMT_8197F) -#define BIT_SET_RXPKTLMT_8197F(x, v) (BIT_CLEAR_RXPKTLMT_8197F(x) | BIT_RXPKTLMT_8197F(v)) - +#define BIT_GET_RXPKTLMT_8197F(x) \ + (((x) >> BIT_SHIFT_RXPKTLMT_8197F) & BIT_MASK_RXPKTLMT_8197F) +#define BIT_SET_RXPKTLMT_8197F(x, v) \ + (BIT_CLEAR_RXPKTLMT_8197F(x) | BIT_RXPKTLMT_8197F(v)) /* 2 REG_MACID_8197F (MAC ID REGISTER) */ #define BIT_SHIFT_MACID_8197F 0 #define BIT_MASK_MACID_8197F 0xffffffffffffL -#define BIT_MACID_8197F(x) (((x) & BIT_MASK_MACID_8197F) << BIT_SHIFT_MACID_8197F) +#define BIT_MACID_8197F(x) \ + (((x) & BIT_MASK_MACID_8197F) << BIT_SHIFT_MACID_8197F) #define BITS_MACID_8197F (BIT_MASK_MACID_8197F << BIT_SHIFT_MACID_8197F) #define BIT_CLEAR_MACID_8197F(x) ((x) & (~BITS_MACID_8197F)) -#define BIT_GET_MACID_8197F(x) (((x) >> BIT_SHIFT_MACID_8197F) & BIT_MASK_MACID_8197F) -#define BIT_SET_MACID_8197F(x, v) (BIT_CLEAR_MACID_8197F(x) | BIT_MACID_8197F(v)) - +#define BIT_GET_MACID_8197F(x) \ + (((x) >> BIT_SHIFT_MACID_8197F) & BIT_MASK_MACID_8197F) +#define BIT_SET_MACID_8197F(x, v) \ + (BIT_CLEAR_MACID_8197F(x) | BIT_MACID_8197F(v)) /* 2 REG_BSSID_8197F (BSSID REGISTER) */ #define BIT_SHIFT_BSSID_8197F 0 #define BIT_MASK_BSSID_8197F 0xffffffffffffL -#define BIT_BSSID_8197F(x) (((x) & BIT_MASK_BSSID_8197F) << BIT_SHIFT_BSSID_8197F) +#define BIT_BSSID_8197F(x) \ + (((x) & BIT_MASK_BSSID_8197F) << BIT_SHIFT_BSSID_8197F) #define BITS_BSSID_8197F (BIT_MASK_BSSID_8197F << BIT_SHIFT_BSSID_8197F) #define BIT_CLEAR_BSSID_8197F(x) ((x) & (~BITS_BSSID_8197F)) -#define BIT_GET_BSSID_8197F(x) (((x) >> BIT_SHIFT_BSSID_8197F) & BIT_MASK_BSSID_8197F) -#define BIT_SET_BSSID_8197F(x, v) (BIT_CLEAR_BSSID_8197F(x) | BIT_BSSID_8197F(v)) - +#define BIT_GET_BSSID_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID_8197F) & BIT_MASK_BSSID_8197F) +#define BIT_SET_BSSID_8197F(x, v) \ + (BIT_CLEAR_BSSID_8197F(x) | BIT_BSSID_8197F(v)) /* 2 REG_MAR_8197F (MULTICAST ADDRESS REGISTER) */ @@ -10228,29 +13404,40 @@ #define BIT_GET_MAR_8197F(x) (((x) >> BIT_SHIFT_MAR_8197F) & BIT_MASK_MAR_8197F) #define BIT_SET_MAR_8197F(x, v) (BIT_CLEAR_MAR_8197F(x) | BIT_MAR_8197F(v)) - /* 2 REG_MBIDCAMCFG_1_8197F (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_SHIFT_MBIDCAM_RWDATA_L_8197F 0 #define BIT_MASK_MBIDCAM_RWDATA_L_8197F 0xffffffffL -#define BIT_MBIDCAM_RWDATA_L_8197F(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8197F) << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) -#define BITS_MBIDCAM_RWDATA_L_8197F (BIT_MASK_MBIDCAM_RWDATA_L_8197F << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) -#define BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) ((x) & (~BITS_MBIDCAM_RWDATA_L_8197F)) -#define BIT_GET_MBIDCAM_RWDATA_L_8197F(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) & BIT_MASK_MBIDCAM_RWDATA_L_8197F) -#define BIT_SET_MBIDCAM_RWDATA_L_8197F(x, v) (BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) | BIT_MBIDCAM_RWDATA_L_8197F(v)) - +#define BIT_MBIDCAM_RWDATA_L_8197F(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8197F) \ + << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) +#define BITS_MBIDCAM_RWDATA_L_8197F \ + (BIT_MASK_MBIDCAM_RWDATA_L_8197F << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) +#define BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_L_8197F)) +#define BIT_GET_MBIDCAM_RWDATA_L_8197F(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) & \ + BIT_MASK_MBIDCAM_RWDATA_L_8197F) +#define BIT_SET_MBIDCAM_RWDATA_L_8197F(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) | BIT_MBIDCAM_RWDATA_L_8197F(v)) /* 2 REG_MBIDCAMCFG_2_8197F (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_MBIDCAM_POLL_8197F BIT(31) #define BIT_MBIDCAM_WT_EN_8197F BIT(30) -#define BIT_SHIFT_MBIDCAM_ADDR_8197F 24 -#define BIT_MASK_MBIDCAM_ADDR_8197F 0x1f -#define BIT_MBIDCAM_ADDR_8197F(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8197F) << BIT_SHIFT_MBIDCAM_ADDR_8197F) -#define BITS_MBIDCAM_ADDR_8197F (BIT_MASK_MBIDCAM_ADDR_8197F << BIT_SHIFT_MBIDCAM_ADDR_8197F) -#define BIT_CLEAR_MBIDCAM_ADDR_8197F(x) ((x) & (~BITS_MBIDCAM_ADDR_8197F)) -#define BIT_GET_MBIDCAM_ADDR_8197F(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8197F) & BIT_MASK_MBIDCAM_ADDR_8197F) -#define BIT_SET_MBIDCAM_ADDR_8197F(x, v) (BIT_CLEAR_MBIDCAM_ADDR_8197F(x) | BIT_MBIDCAM_ADDR_8197F(v)) +#define BIT_SHIFT_MBIDCAM_ADDR_V1_8197F 24 +#define BIT_MASK_MBIDCAM_ADDR_V1_8197F 0x3f +#define BIT_MBIDCAM_ADDR_V1_8197F(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_V1_8197F) \ + << BIT_SHIFT_MBIDCAM_ADDR_V1_8197F) +#define BITS_MBIDCAM_ADDR_V1_8197F \ + (BIT_MASK_MBIDCAM_ADDR_V1_8197F << BIT_SHIFT_MBIDCAM_ADDR_V1_8197F) +#define BIT_CLEAR_MBIDCAM_ADDR_V1_8197F(x) ((x) & (~BITS_MBIDCAM_ADDR_V1_8197F)) +#define BIT_GET_MBIDCAM_ADDR_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1_8197F) & \ + BIT_MASK_MBIDCAM_ADDR_V1_8197F) +#define BIT_SET_MBIDCAM_ADDR_V1_8197F(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_V1_8197F(x) | BIT_MBIDCAM_ADDR_V1_8197F(v)) #define BIT_MBIDCAM_VALID_8197F BIT(23) #define BIT_LSIC_TXOP_EN_8197F BIT(17) @@ -10258,149 +13445,200 @@ #define BIT_SHIFT_MBIDCAM_RWDATA_H_8197F 0 #define BIT_MASK_MBIDCAM_RWDATA_H_8197F 0xffff -#define BIT_MBIDCAM_RWDATA_H_8197F(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8197F) << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) -#define BITS_MBIDCAM_RWDATA_H_8197F (BIT_MASK_MBIDCAM_RWDATA_H_8197F << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) -#define BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) ((x) & (~BITS_MBIDCAM_RWDATA_H_8197F)) -#define BIT_GET_MBIDCAM_RWDATA_H_8197F(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) & BIT_MASK_MBIDCAM_RWDATA_H_8197F) -#define BIT_SET_MBIDCAM_RWDATA_H_8197F(x, v) (BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) | BIT_MBIDCAM_RWDATA_H_8197F(v)) - +#define BIT_MBIDCAM_RWDATA_H_8197F(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8197F) \ + << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) +#define BITS_MBIDCAM_RWDATA_H_8197F \ + (BIT_MASK_MBIDCAM_RWDATA_H_8197F << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) +#define BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_H_8197F)) +#define BIT_GET_MBIDCAM_RWDATA_H_8197F(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) & \ + BIT_MASK_MBIDCAM_RWDATA_H_8197F) +#define BIT_SET_MBIDCAM_RWDATA_H_8197F(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) | BIT_MBIDCAM_RWDATA_H_8197F(v)) /* 2 REG_ZLD_NUM_8197F */ #define BIT_SHIFT_ZLD_NUM_8197F 0 #define BIT_MASK_ZLD_NUM_8197F 0xff -#define BIT_ZLD_NUM_8197F(x) (((x) & BIT_MASK_ZLD_NUM_8197F) << BIT_SHIFT_ZLD_NUM_8197F) +#define BIT_ZLD_NUM_8197F(x) \ + (((x) & BIT_MASK_ZLD_NUM_8197F) << BIT_SHIFT_ZLD_NUM_8197F) #define BITS_ZLD_NUM_8197F (BIT_MASK_ZLD_NUM_8197F << BIT_SHIFT_ZLD_NUM_8197F) #define BIT_CLEAR_ZLD_NUM_8197F(x) ((x) & (~BITS_ZLD_NUM_8197F)) -#define BIT_GET_ZLD_NUM_8197F(x) (((x) >> BIT_SHIFT_ZLD_NUM_8197F) & BIT_MASK_ZLD_NUM_8197F) -#define BIT_SET_ZLD_NUM_8197F(x, v) (BIT_CLEAR_ZLD_NUM_8197F(x) | BIT_ZLD_NUM_8197F(v)) - +#define BIT_GET_ZLD_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_ZLD_NUM_8197F) & BIT_MASK_ZLD_NUM_8197F) +#define BIT_SET_ZLD_NUM_8197F(x, v) \ + (BIT_CLEAR_ZLD_NUM_8197F(x) | BIT_ZLD_NUM_8197F(v)) /* 2 REG_UDF_THSD_8197F */ #define BIT_SHIFT_UDF_THSD_8197F 0 #define BIT_MASK_UDF_THSD_8197F 0xff -#define BIT_UDF_THSD_8197F(x) (((x) & BIT_MASK_UDF_THSD_8197F) << BIT_SHIFT_UDF_THSD_8197F) -#define BITS_UDF_THSD_8197F (BIT_MASK_UDF_THSD_8197F << BIT_SHIFT_UDF_THSD_8197F) +#define BIT_UDF_THSD_8197F(x) \ + (((x) & BIT_MASK_UDF_THSD_8197F) << BIT_SHIFT_UDF_THSD_8197F) +#define BITS_UDF_THSD_8197F \ + (BIT_MASK_UDF_THSD_8197F << BIT_SHIFT_UDF_THSD_8197F) #define BIT_CLEAR_UDF_THSD_8197F(x) ((x) & (~BITS_UDF_THSD_8197F)) -#define BIT_GET_UDF_THSD_8197F(x) (((x) >> BIT_SHIFT_UDF_THSD_8197F) & BIT_MASK_UDF_THSD_8197F) -#define BIT_SET_UDF_THSD_8197F(x, v) (BIT_CLEAR_UDF_THSD_8197F(x) | BIT_UDF_THSD_8197F(v)) - +#define BIT_GET_UDF_THSD_8197F(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_8197F) & BIT_MASK_UDF_THSD_8197F) +#define BIT_SET_UDF_THSD_8197F(x, v) \ + (BIT_CLEAR_UDF_THSD_8197F(x) | BIT_UDF_THSD_8197F(v)) /* 2 REG_WMAC_TCR_TSFT_OFS_8197F */ #define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F 0 #define BIT_MASK_WMAC_TCR_TSFT_OFS_8197F 0xffff -#define BIT_WMAC_TCR_TSFT_OFS_8197F(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8197F) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) -#define BITS_WMAC_TCR_TSFT_OFS_8197F (BIT_MASK_WMAC_TCR_TSFT_OFS_8197F << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) -#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8197F)) -#define BIT_GET_WMAC_TCR_TSFT_OFS_8197F(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) & BIT_MASK_WMAC_TCR_TSFT_OFS_8197F) -#define BIT_SET_WMAC_TCR_TSFT_OFS_8197F(x, v) (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) | BIT_WMAC_TCR_TSFT_OFS_8197F(v)) - +#define BIT_WMAC_TCR_TSFT_OFS_8197F(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8197F) \ + << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) +#define BITS_WMAC_TCR_TSFT_OFS_8197F \ + (BIT_MASK_WMAC_TCR_TSFT_OFS_8197F << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) \ + ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8197F)) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) & \ + BIT_MASK_WMAC_TCR_TSFT_OFS_8197F) +#define BIT_SET_WMAC_TCR_TSFT_OFS_8197F(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) | BIT_WMAC_TCR_TSFT_OFS_8197F(v)) /* 2 REG_MCU_TEST_2_V1_8197F */ #define BIT_SHIFT_MCU_RSVD_2_V1_8197F 0 #define BIT_MASK_MCU_RSVD_2_V1_8197F 0xffff -#define BIT_MCU_RSVD_2_V1_8197F(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8197F) << BIT_SHIFT_MCU_RSVD_2_V1_8197F) -#define BITS_MCU_RSVD_2_V1_8197F (BIT_MASK_MCU_RSVD_2_V1_8197F << BIT_SHIFT_MCU_RSVD_2_V1_8197F) +#define BIT_MCU_RSVD_2_V1_8197F(x) \ + (((x) & BIT_MASK_MCU_RSVD_2_V1_8197F) << BIT_SHIFT_MCU_RSVD_2_V1_8197F) +#define BITS_MCU_RSVD_2_V1_8197F \ + (BIT_MASK_MCU_RSVD_2_V1_8197F << BIT_SHIFT_MCU_RSVD_2_V1_8197F) #define BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) ((x) & (~BITS_MCU_RSVD_2_V1_8197F)) -#define BIT_GET_MCU_RSVD_2_V1_8197F(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8197F) & BIT_MASK_MCU_RSVD_2_V1_8197F) -#define BIT_SET_MCU_RSVD_2_V1_8197F(x, v) (BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) | BIT_MCU_RSVD_2_V1_8197F(v)) - +#define BIT_GET_MCU_RSVD_2_V1_8197F(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8197F) & BIT_MASK_MCU_RSVD_2_V1_8197F) +#define BIT_SET_MCU_RSVD_2_V1_8197F(x, v) \ + (BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) | BIT_MCU_RSVD_2_V1_8197F(v)) /* 2 REG_WMAC_TXTIMEOUT_8197F */ #define BIT_SHIFT_WMAC_TXTIMEOUT_8197F 0 #define BIT_MASK_WMAC_TXTIMEOUT_8197F 0xff -#define BIT_WMAC_TXTIMEOUT_8197F(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8197F) << BIT_SHIFT_WMAC_TXTIMEOUT_8197F) -#define BITS_WMAC_TXTIMEOUT_8197F (BIT_MASK_WMAC_TXTIMEOUT_8197F << BIT_SHIFT_WMAC_TXTIMEOUT_8197F) +#define BIT_WMAC_TXTIMEOUT_8197F(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT_8197F) \ + << BIT_SHIFT_WMAC_TXTIMEOUT_8197F) +#define BITS_WMAC_TXTIMEOUT_8197F \ + (BIT_MASK_WMAC_TXTIMEOUT_8197F << BIT_SHIFT_WMAC_TXTIMEOUT_8197F) #define BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8197F)) -#define BIT_GET_WMAC_TXTIMEOUT_8197F(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8197F) & BIT_MASK_WMAC_TXTIMEOUT_8197F) -#define BIT_SET_WMAC_TXTIMEOUT_8197F(x, v) (BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) | BIT_WMAC_TXTIMEOUT_8197F(v)) - +#define BIT_GET_WMAC_TXTIMEOUT_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8197F) & \ + BIT_MASK_WMAC_TXTIMEOUT_8197F) +#define BIT_SET_WMAC_TXTIMEOUT_8197F(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) | BIT_WMAC_TXTIMEOUT_8197F(v)) /* 2 REG_STMP_THSD_8197F */ #define BIT_SHIFT_STMP_THSD_8197F 0 #define BIT_MASK_STMP_THSD_8197F 0xff -#define BIT_STMP_THSD_8197F(x) (((x) & BIT_MASK_STMP_THSD_8197F) << BIT_SHIFT_STMP_THSD_8197F) -#define BITS_STMP_THSD_8197F (BIT_MASK_STMP_THSD_8197F << BIT_SHIFT_STMP_THSD_8197F) +#define BIT_STMP_THSD_8197F(x) \ + (((x) & BIT_MASK_STMP_THSD_8197F) << BIT_SHIFT_STMP_THSD_8197F) +#define BITS_STMP_THSD_8197F \ + (BIT_MASK_STMP_THSD_8197F << BIT_SHIFT_STMP_THSD_8197F) #define BIT_CLEAR_STMP_THSD_8197F(x) ((x) & (~BITS_STMP_THSD_8197F)) -#define BIT_GET_STMP_THSD_8197F(x) (((x) >> BIT_SHIFT_STMP_THSD_8197F) & BIT_MASK_STMP_THSD_8197F) -#define BIT_SET_STMP_THSD_8197F(x, v) (BIT_CLEAR_STMP_THSD_8197F(x) | BIT_STMP_THSD_8197F(v)) - +#define BIT_GET_STMP_THSD_8197F(x) \ + (((x) >> BIT_SHIFT_STMP_THSD_8197F) & BIT_MASK_STMP_THSD_8197F) +#define BIT_SET_STMP_THSD_8197F(x, v) \ + (BIT_CLEAR_STMP_THSD_8197F(x) | BIT_STMP_THSD_8197F(v)) /* 2 REG_MAC_SPEC_SIFS_8197F (SPECIFICATION SIFS REGISTER) */ #define BIT_SHIFT_SPEC_SIFS_OFDM_8197F 8 #define BIT_MASK_SPEC_SIFS_OFDM_8197F 0xff -#define BIT_SPEC_SIFS_OFDM_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8197F) << BIT_SHIFT_SPEC_SIFS_OFDM_8197F) -#define BITS_SPEC_SIFS_OFDM_8197F (BIT_MASK_SPEC_SIFS_OFDM_8197F << BIT_SHIFT_SPEC_SIFS_OFDM_8197F) +#define BIT_SPEC_SIFS_OFDM_8197F(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_8197F) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_8197F) +#define BITS_SPEC_SIFS_OFDM_8197F \ + (BIT_MASK_SPEC_SIFS_OFDM_8197F << BIT_SHIFT_SPEC_SIFS_OFDM_8197F) #define BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8197F)) -#define BIT_GET_SPEC_SIFS_OFDM_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8197F) & BIT_MASK_SPEC_SIFS_OFDM_8197F) -#define BIT_SET_SPEC_SIFS_OFDM_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) | BIT_SPEC_SIFS_OFDM_8197F(v)) - +#define BIT_GET_SPEC_SIFS_OFDM_8197F(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8197F) & \ + BIT_MASK_SPEC_SIFS_OFDM_8197F) +#define BIT_SET_SPEC_SIFS_OFDM_8197F(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) | BIT_SPEC_SIFS_OFDM_8197F(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_8197F 0 #define BIT_MASK_SPEC_SIFS_CCK_8197F 0xff -#define BIT_SPEC_SIFS_CCK_8197F(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8197F) << BIT_SHIFT_SPEC_SIFS_CCK_8197F) -#define BITS_SPEC_SIFS_CCK_8197F (BIT_MASK_SPEC_SIFS_CCK_8197F << BIT_SHIFT_SPEC_SIFS_CCK_8197F) +#define BIT_SPEC_SIFS_CCK_8197F(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_8197F) << BIT_SHIFT_SPEC_SIFS_CCK_8197F) +#define BITS_SPEC_SIFS_CCK_8197F \ + (BIT_MASK_SPEC_SIFS_CCK_8197F << BIT_SHIFT_SPEC_SIFS_CCK_8197F) #define BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) ((x) & (~BITS_SPEC_SIFS_CCK_8197F)) -#define BIT_GET_SPEC_SIFS_CCK_8197F(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8197F) & BIT_MASK_SPEC_SIFS_CCK_8197F) -#define BIT_SET_SPEC_SIFS_CCK_8197F(x, v) (BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) | BIT_SPEC_SIFS_CCK_8197F(v)) - +#define BIT_GET_SPEC_SIFS_CCK_8197F(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8197F) & BIT_MASK_SPEC_SIFS_CCK_8197F) +#define BIT_SET_SPEC_SIFS_CCK_8197F(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) | BIT_SPEC_SIFS_CCK_8197F(v)) /* 2 REG_USTIME_EDCA_8197F (US TIME TUNING FOR EDCA REGISTER) */ #define BIT_SHIFT_USTIME_EDCA_8197F 0 #define BIT_MASK_USTIME_EDCA_8197F 0xff -#define BIT_USTIME_EDCA_8197F(x) (((x) & BIT_MASK_USTIME_EDCA_8197F) << BIT_SHIFT_USTIME_EDCA_8197F) -#define BITS_USTIME_EDCA_8197F (BIT_MASK_USTIME_EDCA_8197F << BIT_SHIFT_USTIME_EDCA_8197F) +#define BIT_USTIME_EDCA_8197F(x) \ + (((x) & BIT_MASK_USTIME_EDCA_8197F) << BIT_SHIFT_USTIME_EDCA_8197F) +#define BITS_USTIME_EDCA_8197F \ + (BIT_MASK_USTIME_EDCA_8197F << BIT_SHIFT_USTIME_EDCA_8197F) #define BIT_CLEAR_USTIME_EDCA_8197F(x) ((x) & (~BITS_USTIME_EDCA_8197F)) -#define BIT_GET_USTIME_EDCA_8197F(x) (((x) >> BIT_SHIFT_USTIME_EDCA_8197F) & BIT_MASK_USTIME_EDCA_8197F) -#define BIT_SET_USTIME_EDCA_8197F(x, v) (BIT_CLEAR_USTIME_EDCA_8197F(x) | BIT_USTIME_EDCA_8197F(v)) - +#define BIT_GET_USTIME_EDCA_8197F(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_8197F) & BIT_MASK_USTIME_EDCA_8197F) +#define BIT_SET_USTIME_EDCA_8197F(x, v) \ + (BIT_CLEAR_USTIME_EDCA_8197F(x) | BIT_USTIME_EDCA_8197F(v)) /* 2 REG_RESP_SIFS_OFDM_8197F (RESPONSE SIFS FOR OFDM REGISTER) */ #define BIT_SHIFT_SIFS_R2T_OFDM_8197F 8 #define BIT_MASK_SIFS_R2T_OFDM_8197F 0xff -#define BIT_SIFS_R2T_OFDM_8197F(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8197F) << BIT_SHIFT_SIFS_R2T_OFDM_8197F) -#define BITS_SIFS_R2T_OFDM_8197F (BIT_MASK_SIFS_R2T_OFDM_8197F << BIT_SHIFT_SIFS_R2T_OFDM_8197F) +#define BIT_SIFS_R2T_OFDM_8197F(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM_8197F) << BIT_SHIFT_SIFS_R2T_OFDM_8197F) +#define BITS_SIFS_R2T_OFDM_8197F \ + (BIT_MASK_SIFS_R2T_OFDM_8197F << BIT_SHIFT_SIFS_R2T_OFDM_8197F) #define BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_R2T_OFDM_8197F)) -#define BIT_GET_SIFS_R2T_OFDM_8197F(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8197F) & BIT_MASK_SIFS_R2T_OFDM_8197F) -#define BIT_SET_SIFS_R2T_OFDM_8197F(x, v) (BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) | BIT_SIFS_R2T_OFDM_8197F(v)) - +#define BIT_GET_SIFS_R2T_OFDM_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8197F) & BIT_MASK_SIFS_R2T_OFDM_8197F) +#define BIT_SET_SIFS_R2T_OFDM_8197F(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) | BIT_SIFS_R2T_OFDM_8197F(v)) #define BIT_SHIFT_SIFS_T2T_OFDM_8197F 0 #define BIT_MASK_SIFS_T2T_OFDM_8197F 0xff -#define BIT_SIFS_T2T_OFDM_8197F(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8197F) << BIT_SHIFT_SIFS_T2T_OFDM_8197F) -#define BITS_SIFS_T2T_OFDM_8197F (BIT_MASK_SIFS_T2T_OFDM_8197F << BIT_SHIFT_SIFS_T2T_OFDM_8197F) +#define BIT_SIFS_T2T_OFDM_8197F(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM_8197F) << BIT_SHIFT_SIFS_T2T_OFDM_8197F) +#define BITS_SIFS_T2T_OFDM_8197F \ + (BIT_MASK_SIFS_T2T_OFDM_8197F << BIT_SHIFT_SIFS_T2T_OFDM_8197F) #define BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_T2T_OFDM_8197F)) -#define BIT_GET_SIFS_T2T_OFDM_8197F(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8197F) & BIT_MASK_SIFS_T2T_OFDM_8197F) -#define BIT_SET_SIFS_T2T_OFDM_8197F(x, v) (BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) | BIT_SIFS_T2T_OFDM_8197F(v)) - +#define BIT_GET_SIFS_T2T_OFDM_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8197F) & BIT_MASK_SIFS_T2T_OFDM_8197F) +#define BIT_SET_SIFS_T2T_OFDM_8197F(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) | BIT_SIFS_T2T_OFDM_8197F(v)) /* 2 REG_RESP_SIFS_CCK_8197F (RESPONSE SIFS FOR CCK REGISTER) */ #define BIT_SHIFT_SIFS_R2T_CCK_8197F 8 #define BIT_MASK_SIFS_R2T_CCK_8197F 0xff -#define BIT_SIFS_R2T_CCK_8197F(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8197F) << BIT_SHIFT_SIFS_R2T_CCK_8197F) -#define BITS_SIFS_R2T_CCK_8197F (BIT_MASK_SIFS_R2T_CCK_8197F << BIT_SHIFT_SIFS_R2T_CCK_8197F) +#define BIT_SIFS_R2T_CCK_8197F(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK_8197F) << BIT_SHIFT_SIFS_R2T_CCK_8197F) +#define BITS_SIFS_R2T_CCK_8197F \ + (BIT_MASK_SIFS_R2T_CCK_8197F << BIT_SHIFT_SIFS_R2T_CCK_8197F) #define BIT_CLEAR_SIFS_R2T_CCK_8197F(x) ((x) & (~BITS_SIFS_R2T_CCK_8197F)) -#define BIT_GET_SIFS_R2T_CCK_8197F(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8197F) & BIT_MASK_SIFS_R2T_CCK_8197F) -#define BIT_SET_SIFS_R2T_CCK_8197F(x, v) (BIT_CLEAR_SIFS_R2T_CCK_8197F(x) | BIT_SIFS_R2T_CCK_8197F(v)) - +#define BIT_GET_SIFS_R2T_CCK_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8197F) & BIT_MASK_SIFS_R2T_CCK_8197F) +#define BIT_SET_SIFS_R2T_CCK_8197F(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK_8197F(x) | BIT_SIFS_R2T_CCK_8197F(v)) #define BIT_SHIFT_SIFS_T2T_CCK_8197F 0 #define BIT_MASK_SIFS_T2T_CCK_8197F 0xff -#define BIT_SIFS_T2T_CCK_8197F(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8197F) << BIT_SHIFT_SIFS_T2T_CCK_8197F) -#define BITS_SIFS_T2T_CCK_8197F (BIT_MASK_SIFS_T2T_CCK_8197F << BIT_SHIFT_SIFS_T2T_CCK_8197F) +#define BIT_SIFS_T2T_CCK_8197F(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK_8197F) << BIT_SHIFT_SIFS_T2T_CCK_8197F) +#define BITS_SIFS_T2T_CCK_8197F \ + (BIT_MASK_SIFS_T2T_CCK_8197F << BIT_SHIFT_SIFS_T2T_CCK_8197F) #define BIT_CLEAR_SIFS_T2T_CCK_8197F(x) ((x) & (~BITS_SIFS_T2T_CCK_8197F)) -#define BIT_GET_SIFS_T2T_CCK_8197F(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8197F) & BIT_MASK_SIFS_T2T_CCK_8197F) -#define BIT_SET_SIFS_T2T_CCK_8197F(x, v) (BIT_CLEAR_SIFS_T2T_CCK_8197F(x) | BIT_SIFS_T2T_CCK_8197F(v)) - +#define BIT_GET_SIFS_T2T_CCK_8197F(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8197F) & BIT_MASK_SIFS_T2T_CCK_8197F) +#define BIT_SET_SIFS_T2T_CCK_8197F(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK_8197F(x) | BIT_SIFS_T2T_CCK_8197F(v)) /* 2 REG_EIFS_8197F (EIFS REGISTER) */ @@ -10409,31 +13647,35 @@ #define BIT_EIFS_8197F(x) (((x) & BIT_MASK_EIFS_8197F) << BIT_SHIFT_EIFS_8197F) #define BITS_EIFS_8197F (BIT_MASK_EIFS_8197F << BIT_SHIFT_EIFS_8197F) #define BIT_CLEAR_EIFS_8197F(x) ((x) & (~BITS_EIFS_8197F)) -#define BIT_GET_EIFS_8197F(x) (((x) >> BIT_SHIFT_EIFS_8197F) & BIT_MASK_EIFS_8197F) +#define BIT_GET_EIFS_8197F(x) \ + (((x) >> BIT_SHIFT_EIFS_8197F) & BIT_MASK_EIFS_8197F) #define BIT_SET_EIFS_8197F(x, v) (BIT_CLEAR_EIFS_8197F(x) | BIT_EIFS_8197F(v)) - /* 2 REG_CTS2TO_8197F (CTS2 TIMEOUT REGISTER) */ #define BIT_SHIFT_CTS2TO_8197F 0 #define BIT_MASK_CTS2TO_8197F 0xff -#define BIT_CTS2TO_8197F(x) (((x) & BIT_MASK_CTS2TO_8197F) << BIT_SHIFT_CTS2TO_8197F) +#define BIT_CTS2TO_8197F(x) \ + (((x) & BIT_MASK_CTS2TO_8197F) << BIT_SHIFT_CTS2TO_8197F) #define BITS_CTS2TO_8197F (BIT_MASK_CTS2TO_8197F << BIT_SHIFT_CTS2TO_8197F) #define BIT_CLEAR_CTS2TO_8197F(x) ((x) & (~BITS_CTS2TO_8197F)) -#define BIT_GET_CTS2TO_8197F(x) (((x) >> BIT_SHIFT_CTS2TO_8197F) & BIT_MASK_CTS2TO_8197F) -#define BIT_SET_CTS2TO_8197F(x, v) (BIT_CLEAR_CTS2TO_8197F(x) | BIT_CTS2TO_8197F(v)) - +#define BIT_GET_CTS2TO_8197F(x) \ + (((x) >> BIT_SHIFT_CTS2TO_8197F) & BIT_MASK_CTS2TO_8197F) +#define BIT_SET_CTS2TO_8197F(x, v) \ + (BIT_CLEAR_CTS2TO_8197F(x) | BIT_CTS2TO_8197F(v)) /* 2 REG_ACKTO_8197F (ACK TIMEOUT REGISTER) */ #define BIT_SHIFT_ACKTO_8197F 0 #define BIT_MASK_ACKTO_8197F 0xff -#define BIT_ACKTO_8197F(x) (((x) & BIT_MASK_ACKTO_8197F) << BIT_SHIFT_ACKTO_8197F) +#define BIT_ACKTO_8197F(x) \ + (((x) & BIT_MASK_ACKTO_8197F) << BIT_SHIFT_ACKTO_8197F) #define BITS_ACKTO_8197F (BIT_MASK_ACKTO_8197F << BIT_SHIFT_ACKTO_8197F) #define BIT_CLEAR_ACKTO_8197F(x) ((x) & (~BITS_ACKTO_8197F)) -#define BIT_GET_ACKTO_8197F(x) (((x) >> BIT_SHIFT_ACKTO_8197F) & BIT_MASK_ACKTO_8197F) -#define BIT_SET_ACKTO_8197F(x, v) (BIT_CLEAR_ACKTO_8197F(x) | BIT_ACKTO_8197F(v)) - +#define BIT_GET_ACKTO_8197F(x) \ + (((x) >> BIT_SHIFT_ACKTO_8197F) & BIT_MASK_ACKTO_8197F) +#define BIT_SET_ACKTO_8197F(x, v) \ + (BIT_CLEAR_ACKTO_8197F(x) | BIT_ACKTO_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -10441,30 +13683,38 @@ #define BIT_SHIFT_NAV_UPPER_8197F 16 #define BIT_MASK_NAV_UPPER_8197F 0xff -#define BIT_NAV_UPPER_8197F(x) (((x) & BIT_MASK_NAV_UPPER_8197F) << BIT_SHIFT_NAV_UPPER_8197F) -#define BITS_NAV_UPPER_8197F (BIT_MASK_NAV_UPPER_8197F << BIT_SHIFT_NAV_UPPER_8197F) +#define BIT_NAV_UPPER_8197F(x) \ + (((x) & BIT_MASK_NAV_UPPER_8197F) << BIT_SHIFT_NAV_UPPER_8197F) +#define BITS_NAV_UPPER_8197F \ + (BIT_MASK_NAV_UPPER_8197F << BIT_SHIFT_NAV_UPPER_8197F) #define BIT_CLEAR_NAV_UPPER_8197F(x) ((x) & (~BITS_NAV_UPPER_8197F)) -#define BIT_GET_NAV_UPPER_8197F(x) (((x) >> BIT_SHIFT_NAV_UPPER_8197F) & BIT_MASK_NAV_UPPER_8197F) -#define BIT_SET_NAV_UPPER_8197F(x, v) (BIT_CLEAR_NAV_UPPER_8197F(x) | BIT_NAV_UPPER_8197F(v)) - +#define BIT_GET_NAV_UPPER_8197F(x) \ + (((x) >> BIT_SHIFT_NAV_UPPER_8197F) & BIT_MASK_NAV_UPPER_8197F) +#define BIT_SET_NAV_UPPER_8197F(x, v) \ + (BIT_CLEAR_NAV_UPPER_8197F(x) | BIT_NAV_UPPER_8197F(v)) #define BIT_SHIFT_RXMYRTS_NAV_8197F 8 #define BIT_MASK_RXMYRTS_NAV_8197F 0xf -#define BIT_RXMYRTS_NAV_8197F(x) (((x) & BIT_MASK_RXMYRTS_NAV_8197F) << BIT_SHIFT_RXMYRTS_NAV_8197F) -#define BITS_RXMYRTS_NAV_8197F (BIT_MASK_RXMYRTS_NAV_8197F << BIT_SHIFT_RXMYRTS_NAV_8197F) +#define BIT_RXMYRTS_NAV_8197F(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_8197F) << BIT_SHIFT_RXMYRTS_NAV_8197F) +#define BITS_RXMYRTS_NAV_8197F \ + (BIT_MASK_RXMYRTS_NAV_8197F << BIT_SHIFT_RXMYRTS_NAV_8197F) #define BIT_CLEAR_RXMYRTS_NAV_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_8197F)) -#define BIT_GET_RXMYRTS_NAV_8197F(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8197F) & BIT_MASK_RXMYRTS_NAV_8197F) -#define BIT_SET_RXMYRTS_NAV_8197F(x, v) (BIT_CLEAR_RXMYRTS_NAV_8197F(x) | BIT_RXMYRTS_NAV_8197F(v)) - +#define BIT_GET_RXMYRTS_NAV_8197F(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_8197F) & BIT_MASK_RXMYRTS_NAV_8197F) +#define BIT_SET_RXMYRTS_NAV_8197F(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_8197F(x) | BIT_RXMYRTS_NAV_8197F(v)) #define BIT_SHIFT_RTSRST_8197F 0 #define BIT_MASK_RTSRST_8197F 0xff -#define BIT_RTSRST_8197F(x) (((x) & BIT_MASK_RTSRST_8197F) << BIT_SHIFT_RTSRST_8197F) +#define BIT_RTSRST_8197F(x) \ + (((x) & BIT_MASK_RTSRST_8197F) << BIT_SHIFT_RTSRST_8197F) #define BITS_RTSRST_8197F (BIT_MASK_RTSRST_8197F << BIT_SHIFT_RTSRST_8197F) #define BIT_CLEAR_RTSRST_8197F(x) ((x) & (~BITS_RTSRST_8197F)) -#define BIT_GET_RTSRST_8197F(x) (((x) >> BIT_SHIFT_RTSRST_8197F) & BIT_MASK_RTSRST_8197F) -#define BIT_SET_RTSRST_8197F(x, v) (BIT_CLEAR_RTSRST_8197F(x) | BIT_RTSRST_8197F(v)) - +#define BIT_GET_RTSRST_8197F(x) \ + (((x) >> BIT_SHIFT_RTSRST_8197F) & BIT_MASK_RTSRST_8197F) +#define BIT_SET_RTSRST_8197F(x, v) \ + (BIT_CLEAR_RTSRST_8197F(x) | BIT_RTSRST_8197F(v)) /* 2 REG_BACAMCMD_8197F (BLOCK ACK CAM COMMAND REGISTER) */ #define BIT_BACAM_POLL_8197F BIT(31) @@ -10473,41 +13723,52 @@ #define BIT_SHIFT_TXSBM_8197F 14 #define BIT_MASK_TXSBM_8197F 0x3 -#define BIT_TXSBM_8197F(x) (((x) & BIT_MASK_TXSBM_8197F) << BIT_SHIFT_TXSBM_8197F) +#define BIT_TXSBM_8197F(x) \ + (((x) & BIT_MASK_TXSBM_8197F) << BIT_SHIFT_TXSBM_8197F) #define BITS_TXSBM_8197F (BIT_MASK_TXSBM_8197F << BIT_SHIFT_TXSBM_8197F) #define BIT_CLEAR_TXSBM_8197F(x) ((x) & (~BITS_TXSBM_8197F)) -#define BIT_GET_TXSBM_8197F(x) (((x) >> BIT_SHIFT_TXSBM_8197F) & BIT_MASK_TXSBM_8197F) -#define BIT_SET_TXSBM_8197F(x, v) (BIT_CLEAR_TXSBM_8197F(x) | BIT_TXSBM_8197F(v)) - +#define BIT_GET_TXSBM_8197F(x) \ + (((x) >> BIT_SHIFT_TXSBM_8197F) & BIT_MASK_TXSBM_8197F) +#define BIT_SET_TXSBM_8197F(x, v) \ + (BIT_CLEAR_TXSBM_8197F(x) | BIT_TXSBM_8197F(v)) #define BIT_SHIFT_BACAM_ADDR_8197F 0 #define BIT_MASK_BACAM_ADDR_8197F 0x3f -#define BIT_BACAM_ADDR_8197F(x) (((x) & BIT_MASK_BACAM_ADDR_8197F) << BIT_SHIFT_BACAM_ADDR_8197F) -#define BITS_BACAM_ADDR_8197F (BIT_MASK_BACAM_ADDR_8197F << BIT_SHIFT_BACAM_ADDR_8197F) +#define BIT_BACAM_ADDR_8197F(x) \ + (((x) & BIT_MASK_BACAM_ADDR_8197F) << BIT_SHIFT_BACAM_ADDR_8197F) +#define BITS_BACAM_ADDR_8197F \ + (BIT_MASK_BACAM_ADDR_8197F << BIT_SHIFT_BACAM_ADDR_8197F) #define BIT_CLEAR_BACAM_ADDR_8197F(x) ((x) & (~BITS_BACAM_ADDR_8197F)) -#define BIT_GET_BACAM_ADDR_8197F(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8197F) & BIT_MASK_BACAM_ADDR_8197F) -#define BIT_SET_BACAM_ADDR_8197F(x, v) (BIT_CLEAR_BACAM_ADDR_8197F(x) | BIT_BACAM_ADDR_8197F(v)) - +#define BIT_GET_BACAM_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR_8197F) & BIT_MASK_BACAM_ADDR_8197F) +#define BIT_SET_BACAM_ADDR_8197F(x, v) \ + (BIT_CLEAR_BACAM_ADDR_8197F(x) | BIT_BACAM_ADDR_8197F(v)) /* 2 REG_BACAMCONTENT_8197F (BLOCK ACK CAM CONTENT REGISTER) */ #define BIT_SHIFT_BA_CONTENT_H_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_BA_CONTENT_H_8197F 0xffffffffL -#define BIT_BA_CONTENT_H_8197F(x) (((x) & BIT_MASK_BA_CONTENT_H_8197F) << BIT_SHIFT_BA_CONTENT_H_8197F) -#define BITS_BA_CONTENT_H_8197F (BIT_MASK_BA_CONTENT_H_8197F << BIT_SHIFT_BA_CONTENT_H_8197F) +#define BIT_BA_CONTENT_H_8197F(x) \ + (((x) & BIT_MASK_BA_CONTENT_H_8197F) << BIT_SHIFT_BA_CONTENT_H_8197F) +#define BITS_BA_CONTENT_H_8197F \ + (BIT_MASK_BA_CONTENT_H_8197F << BIT_SHIFT_BA_CONTENT_H_8197F) #define BIT_CLEAR_BA_CONTENT_H_8197F(x) ((x) & (~BITS_BA_CONTENT_H_8197F)) -#define BIT_GET_BA_CONTENT_H_8197F(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8197F) & BIT_MASK_BA_CONTENT_H_8197F) -#define BIT_SET_BA_CONTENT_H_8197F(x, v) (BIT_CLEAR_BA_CONTENT_H_8197F(x) | BIT_BA_CONTENT_H_8197F(v)) - +#define BIT_GET_BA_CONTENT_H_8197F(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_H_8197F) & BIT_MASK_BA_CONTENT_H_8197F) +#define BIT_SET_BA_CONTENT_H_8197F(x, v) \ + (BIT_CLEAR_BA_CONTENT_H_8197F(x) | BIT_BA_CONTENT_H_8197F(v)) #define BIT_SHIFT_BA_CONTENT_L_8197F 0 #define BIT_MASK_BA_CONTENT_L_8197F 0xffffffffL -#define BIT_BA_CONTENT_L_8197F(x) (((x) & BIT_MASK_BA_CONTENT_L_8197F) << BIT_SHIFT_BA_CONTENT_L_8197F) -#define BITS_BA_CONTENT_L_8197F (BIT_MASK_BA_CONTENT_L_8197F << BIT_SHIFT_BA_CONTENT_L_8197F) +#define BIT_BA_CONTENT_L_8197F(x) \ + (((x) & BIT_MASK_BA_CONTENT_L_8197F) << BIT_SHIFT_BA_CONTENT_L_8197F) +#define BITS_BA_CONTENT_L_8197F \ + (BIT_MASK_BA_CONTENT_L_8197F << BIT_SHIFT_BA_CONTENT_L_8197F) #define BIT_CLEAR_BA_CONTENT_L_8197F(x) ((x) & (~BITS_BA_CONTENT_L_8197F)) -#define BIT_GET_BA_CONTENT_L_8197F(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8197F) & BIT_MASK_BA_CONTENT_L_8197F) -#define BIT_SET_BA_CONTENT_L_8197F(x, v) (BIT_CLEAR_BA_CONTENT_L_8197F(x) | BIT_BA_CONTENT_L_8197F(v)) - +#define BIT_GET_BA_CONTENT_L_8197F(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L_8197F) & BIT_MASK_BA_CONTENT_L_8197F) +#define BIT_SET_BA_CONTENT_L_8197F(x, v) \ + (BIT_CLEAR_BA_CONTENT_L_8197F(x) | BIT_BA_CONTENT_L_8197F(v)) /* 2 REG_WMAC_BITMAP_CTL_8197F */ #define BIT_BITMAP_VO_8197F BIT(7) @@ -10517,11 +13778,18 @@ #define BIT_SHIFT_BITMAP_CONDITION_8197F 2 #define BIT_MASK_BITMAP_CONDITION_8197F 0x3 -#define BIT_BITMAP_CONDITION_8197F(x) (((x) & BIT_MASK_BITMAP_CONDITION_8197F) << BIT_SHIFT_BITMAP_CONDITION_8197F) -#define BITS_BITMAP_CONDITION_8197F (BIT_MASK_BITMAP_CONDITION_8197F << BIT_SHIFT_BITMAP_CONDITION_8197F) -#define BIT_CLEAR_BITMAP_CONDITION_8197F(x) ((x) & (~BITS_BITMAP_CONDITION_8197F)) -#define BIT_GET_BITMAP_CONDITION_8197F(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8197F) & BIT_MASK_BITMAP_CONDITION_8197F) -#define BIT_SET_BITMAP_CONDITION_8197F(x, v) (BIT_CLEAR_BITMAP_CONDITION_8197F(x) | BIT_BITMAP_CONDITION_8197F(v)) +#define BIT_BITMAP_CONDITION_8197F(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION_8197F) \ + << BIT_SHIFT_BITMAP_CONDITION_8197F) +#define BITS_BITMAP_CONDITION_8197F \ + (BIT_MASK_BITMAP_CONDITION_8197F << BIT_SHIFT_BITMAP_CONDITION_8197F) +#define BIT_CLEAR_BITMAP_CONDITION_8197F(x) \ + ((x) & (~BITS_BITMAP_CONDITION_8197F)) +#define BIT_GET_BITMAP_CONDITION_8197F(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION_8197F) & \ + BIT_MASK_BITMAP_CONDITION_8197F) +#define BIT_SET_BITMAP_CONDITION_8197F(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION_8197F(x) | BIT_BITMAP_CONDITION_8197F(v)) #define BIT_BITMAP_SSNBK_COUNTER_CLR_8197F BIT(1) #define BIT_BITMAP_FORCE_8197F BIT(0) @@ -10530,11 +13798,15 @@ #define BIT_SHIFT_RXPKT_TYPE_8197F 2 #define BIT_MASK_RXPKT_TYPE_8197F 0x3f -#define BIT_RXPKT_TYPE_8197F(x) (((x) & BIT_MASK_RXPKT_TYPE_8197F) << BIT_SHIFT_RXPKT_TYPE_8197F) -#define BITS_RXPKT_TYPE_8197F (BIT_MASK_RXPKT_TYPE_8197F << BIT_SHIFT_RXPKT_TYPE_8197F) +#define BIT_RXPKT_TYPE_8197F(x) \ + (((x) & BIT_MASK_RXPKT_TYPE_8197F) << BIT_SHIFT_RXPKT_TYPE_8197F) +#define BITS_RXPKT_TYPE_8197F \ + (BIT_MASK_RXPKT_TYPE_8197F << BIT_SHIFT_RXPKT_TYPE_8197F) #define BIT_CLEAR_RXPKT_TYPE_8197F(x) ((x) & (~BITS_RXPKT_TYPE_8197F)) -#define BIT_GET_RXPKT_TYPE_8197F(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8197F) & BIT_MASK_RXPKT_TYPE_8197F) -#define BIT_SET_RXPKT_TYPE_8197F(x, v) (BIT_CLEAR_RXPKT_TYPE_8197F(x) | BIT_RXPKT_TYPE_8197F(v)) +#define BIT_GET_RXPKT_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE_8197F) & BIT_MASK_RXPKT_TYPE_8197F) +#define BIT_SET_RXPKT_TYPE_8197F(x, v) \ + (BIT_CLEAR_RXPKT_TYPE_8197F(x) | BIT_RXPKT_TYPE_8197F(v)) #define BIT_TXACT_IND_8197F BIT(1) #define BIT_RXACT_IND_8197F BIT(0) @@ -10543,11 +13815,20 @@ #define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F 2 #define BIT_MASK_BITMAP_SSNBK_COUNTER_8197F 0x3f -#define BIT_BITMAP_SSNBK_COUNTER_8197F(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8197F) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) -#define BITS_BITMAP_SSNBK_COUNTER_8197F (BIT_MASK_BITMAP_SSNBK_COUNTER_8197F << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) -#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8197F)) -#define BIT_GET_BITMAP_SSNBK_COUNTER_8197F(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) & BIT_MASK_BITMAP_SSNBK_COUNTER_8197F) -#define BIT_SET_BITMAP_SSNBK_COUNTER_8197F(x, v) (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) | BIT_BITMAP_SSNBK_COUNTER_8197F(v)) +#define BIT_BITMAP_SSNBK_COUNTER_8197F(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8197F) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) +#define BITS_BITMAP_SSNBK_COUNTER_8197F \ + (BIT_MASK_BITMAP_SSNBK_COUNTER_8197F \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) \ + ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8197F)) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8197F(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER_8197F) +#define BIT_SET_BITMAP_SSNBK_COUNTER_8197F(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) | \ + BIT_BITMAP_SSNBK_COUNTER_8197F(v)) #define BIT_BITMAP_EN_8197F BIT(1) #define BIT_WMAC_BACAM_RPMEN_8197F BIT(0) @@ -10556,100 +13837,145 @@ #define BIT_SHIFT_LBDLY_8197F 0 #define BIT_MASK_LBDLY_8197F 0x1f -#define BIT_LBDLY_8197F(x) (((x) & BIT_MASK_LBDLY_8197F) << BIT_SHIFT_LBDLY_8197F) +#define BIT_LBDLY_8197F(x) \ + (((x) & BIT_MASK_LBDLY_8197F) << BIT_SHIFT_LBDLY_8197F) #define BITS_LBDLY_8197F (BIT_MASK_LBDLY_8197F << BIT_SHIFT_LBDLY_8197F) #define BIT_CLEAR_LBDLY_8197F(x) ((x) & (~BITS_LBDLY_8197F)) -#define BIT_GET_LBDLY_8197F(x) (((x) >> BIT_SHIFT_LBDLY_8197F) & BIT_MASK_LBDLY_8197F) -#define BIT_SET_LBDLY_8197F(x, v) (BIT_CLEAR_LBDLY_8197F(x) | BIT_LBDLY_8197F(v)) - +#define BIT_GET_LBDLY_8197F(x) \ + (((x) >> BIT_SHIFT_LBDLY_8197F) & BIT_MASK_LBDLY_8197F) +#define BIT_SET_LBDLY_8197F(x, v) \ + (BIT_CLEAR_LBDLY_8197F(x) | BIT_LBDLY_8197F(v)) /* 2 REG_RXERR_RPT_8197F (RX ERROR REPORT REGISTER) */ #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F 28 #define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F 0xf -#define BIT_RXERR_RPT_SEL_V1_3_0_8197F(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) -#define BITS_RXERR_RPT_SEL_V1_3_0_8197F (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) -#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8197F)) -#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8197F(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F) -#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8197F(x, v) (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) | BIT_RXERR_RPT_SEL_V1_3_0_8197F(v)) +#define BIT_RXERR_RPT_SEL_V1_3_0_8197F(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) +#define BITS_RXERR_RPT_SEL_V1_3_0_8197F \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) \ + ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8197F)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8197F(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8197F(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) | \ + BIT_RXERR_RPT_SEL_V1_3_0_8197F(v)) #define BIT_RXERR_RPT_RST_8197F BIT(27) #define BIT_RXERR_RPT_SEL_V1_4_8197F BIT(26) #define BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F 24 #define BIT_MASK_UD_SELECT_BSSID_2_1_8197F 0x3 -#define BIT_UD_SELECT_BSSID_2_1_8197F(x) (((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8197F) << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) -#define BITS_UD_SELECT_BSSID_2_1_8197F (BIT_MASK_UD_SELECT_BSSID_2_1_8197F << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) -#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) ((x) & (~BITS_UD_SELECT_BSSID_2_1_8197F)) -#define BIT_GET_UD_SELECT_BSSID_2_1_8197F(x) (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) & BIT_MASK_UD_SELECT_BSSID_2_1_8197F) -#define BIT_SET_UD_SELECT_BSSID_2_1_8197F(x, v) (BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) | BIT_UD_SELECT_BSSID_2_1_8197F(v)) +#define BIT_UD_SELECT_BSSID_2_1_8197F(x) \ + (((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8197F) \ + << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) +#define BITS_UD_SELECT_BSSID_2_1_8197F \ + (BIT_MASK_UD_SELECT_BSSID_2_1_8197F \ + << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) +#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) \ + ((x) & (~BITS_UD_SELECT_BSSID_2_1_8197F)) +#define BIT_GET_UD_SELECT_BSSID_2_1_8197F(x) \ + (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) & \ + BIT_MASK_UD_SELECT_BSSID_2_1_8197F) +#define BIT_SET_UD_SELECT_BSSID_2_1_8197F(x, v) \ + (BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) | \ + BIT_UD_SELECT_BSSID_2_1_8197F(v)) #define BIT_W1S_8197F BIT(23) #define BIT_UD_SELECT_BSSID_0_8197F BIT(22) #define BIT_SHIFT_UD_SUB_TYPE_8197F 18 #define BIT_MASK_UD_SUB_TYPE_8197F 0xf -#define BIT_UD_SUB_TYPE_8197F(x) (((x) & BIT_MASK_UD_SUB_TYPE_8197F) << BIT_SHIFT_UD_SUB_TYPE_8197F) -#define BITS_UD_SUB_TYPE_8197F (BIT_MASK_UD_SUB_TYPE_8197F << BIT_SHIFT_UD_SUB_TYPE_8197F) +#define BIT_UD_SUB_TYPE_8197F(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE_8197F) << BIT_SHIFT_UD_SUB_TYPE_8197F) +#define BITS_UD_SUB_TYPE_8197F \ + (BIT_MASK_UD_SUB_TYPE_8197F << BIT_SHIFT_UD_SUB_TYPE_8197F) #define BIT_CLEAR_UD_SUB_TYPE_8197F(x) ((x) & (~BITS_UD_SUB_TYPE_8197F)) -#define BIT_GET_UD_SUB_TYPE_8197F(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8197F) & BIT_MASK_UD_SUB_TYPE_8197F) -#define BIT_SET_UD_SUB_TYPE_8197F(x, v) (BIT_CLEAR_UD_SUB_TYPE_8197F(x) | BIT_UD_SUB_TYPE_8197F(v)) - +#define BIT_GET_UD_SUB_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE_8197F) & BIT_MASK_UD_SUB_TYPE_8197F) +#define BIT_SET_UD_SUB_TYPE_8197F(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE_8197F(x) | BIT_UD_SUB_TYPE_8197F(v)) #define BIT_SHIFT_UD_TYPE_8197F 16 #define BIT_MASK_UD_TYPE_8197F 0x3 -#define BIT_UD_TYPE_8197F(x) (((x) & BIT_MASK_UD_TYPE_8197F) << BIT_SHIFT_UD_TYPE_8197F) +#define BIT_UD_TYPE_8197F(x) \ + (((x) & BIT_MASK_UD_TYPE_8197F) << BIT_SHIFT_UD_TYPE_8197F) #define BITS_UD_TYPE_8197F (BIT_MASK_UD_TYPE_8197F << BIT_SHIFT_UD_TYPE_8197F) #define BIT_CLEAR_UD_TYPE_8197F(x) ((x) & (~BITS_UD_TYPE_8197F)) -#define BIT_GET_UD_TYPE_8197F(x) (((x) >> BIT_SHIFT_UD_TYPE_8197F) & BIT_MASK_UD_TYPE_8197F) -#define BIT_SET_UD_TYPE_8197F(x, v) (BIT_CLEAR_UD_TYPE_8197F(x) | BIT_UD_TYPE_8197F(v)) - +#define BIT_GET_UD_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_UD_TYPE_8197F) & BIT_MASK_UD_TYPE_8197F) +#define BIT_SET_UD_TYPE_8197F(x, v) \ + (BIT_CLEAR_UD_TYPE_8197F(x) | BIT_UD_TYPE_8197F(v)) #define BIT_SHIFT_RPT_COUNTER_8197F 0 #define BIT_MASK_RPT_COUNTER_8197F 0xffff -#define BIT_RPT_COUNTER_8197F(x) (((x) & BIT_MASK_RPT_COUNTER_8197F) << BIT_SHIFT_RPT_COUNTER_8197F) -#define BITS_RPT_COUNTER_8197F (BIT_MASK_RPT_COUNTER_8197F << BIT_SHIFT_RPT_COUNTER_8197F) +#define BIT_RPT_COUNTER_8197F(x) \ + (((x) & BIT_MASK_RPT_COUNTER_8197F) << BIT_SHIFT_RPT_COUNTER_8197F) +#define BITS_RPT_COUNTER_8197F \ + (BIT_MASK_RPT_COUNTER_8197F << BIT_SHIFT_RPT_COUNTER_8197F) #define BIT_CLEAR_RPT_COUNTER_8197F(x) ((x) & (~BITS_RPT_COUNTER_8197F)) -#define BIT_GET_RPT_COUNTER_8197F(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8197F) & BIT_MASK_RPT_COUNTER_8197F) -#define BIT_SET_RPT_COUNTER_8197F(x, v) (BIT_CLEAR_RPT_COUNTER_8197F(x) | BIT_RPT_COUNTER_8197F(v)) - +#define BIT_GET_RPT_COUNTER_8197F(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER_8197F) & BIT_MASK_RPT_COUNTER_8197F) +#define BIT_SET_RPT_COUNTER_8197F(x, v) \ + (BIT_CLEAR_RPT_COUNTER_8197F(x) | BIT_RPT_COUNTER_8197F(v)) /* 2 REG_WMAC_TRXPTCL_CTL_8197F (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ #define BIT_SHIFT_ACKBA_TYPSEL_8197F (60 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBA_TYPSEL_8197F 0xf -#define BIT_ACKBA_TYPSEL_8197F(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8197F) << BIT_SHIFT_ACKBA_TYPSEL_8197F) -#define BITS_ACKBA_TYPSEL_8197F (BIT_MASK_ACKBA_TYPSEL_8197F << BIT_SHIFT_ACKBA_TYPSEL_8197F) +#define BIT_ACKBA_TYPSEL_8197F(x) \ + (((x) & BIT_MASK_ACKBA_TYPSEL_8197F) << BIT_SHIFT_ACKBA_TYPSEL_8197F) +#define BITS_ACKBA_TYPSEL_8197F \ + (BIT_MASK_ACKBA_TYPSEL_8197F << BIT_SHIFT_ACKBA_TYPSEL_8197F) #define BIT_CLEAR_ACKBA_TYPSEL_8197F(x) ((x) & (~BITS_ACKBA_TYPSEL_8197F)) -#define BIT_GET_ACKBA_TYPSEL_8197F(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8197F) & BIT_MASK_ACKBA_TYPSEL_8197F) -#define BIT_SET_ACKBA_TYPSEL_8197F(x, v) (BIT_CLEAR_ACKBA_TYPSEL_8197F(x) | BIT_ACKBA_TYPSEL_8197F(v)) - +#define BIT_GET_ACKBA_TYPSEL_8197F(x) \ + (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8197F) & BIT_MASK_ACKBA_TYPSEL_8197F) +#define BIT_SET_ACKBA_TYPSEL_8197F(x, v) \ + (BIT_CLEAR_ACKBA_TYPSEL_8197F(x) | BIT_ACKBA_TYPSEL_8197F(v)) #define BIT_SHIFT_ACKBA_ACKPCHK_8197F (56 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBA_ACKPCHK_8197F 0xf -#define BIT_ACKBA_ACKPCHK_8197F(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8197F) << BIT_SHIFT_ACKBA_ACKPCHK_8197F) -#define BITS_ACKBA_ACKPCHK_8197F (BIT_MASK_ACKBA_ACKPCHK_8197F << BIT_SHIFT_ACKBA_ACKPCHK_8197F) +#define BIT_ACKBA_ACKPCHK_8197F(x) \ + (((x) & BIT_MASK_ACKBA_ACKPCHK_8197F) << BIT_SHIFT_ACKBA_ACKPCHK_8197F) +#define BITS_ACKBA_ACKPCHK_8197F \ + (BIT_MASK_ACKBA_ACKPCHK_8197F << BIT_SHIFT_ACKBA_ACKPCHK_8197F) #define BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBA_ACKPCHK_8197F)) -#define BIT_GET_ACKBA_ACKPCHK_8197F(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8197F) & BIT_MASK_ACKBA_ACKPCHK_8197F) -#define BIT_SET_ACKBA_ACKPCHK_8197F(x, v) (BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) | BIT_ACKBA_ACKPCHK_8197F(v)) - +#define BIT_GET_ACKBA_ACKPCHK_8197F(x) \ + (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8197F) & BIT_MASK_ACKBA_ACKPCHK_8197F) +#define BIT_SET_ACKBA_ACKPCHK_8197F(x, v) \ + (BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) | BIT_ACKBA_ACKPCHK_8197F(v)) #define BIT_SHIFT_ACKBAR_TYPESEL_8197F (48 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_TYPESEL_8197F 0xff -#define BIT_ACKBAR_TYPESEL_8197F(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8197F) << BIT_SHIFT_ACKBAR_TYPESEL_8197F) -#define BITS_ACKBAR_TYPESEL_8197F (BIT_MASK_ACKBAR_TYPESEL_8197F << BIT_SHIFT_ACKBAR_TYPESEL_8197F) +#define BIT_ACKBAR_TYPESEL_8197F(x) \ + (((x) & BIT_MASK_ACKBAR_TYPESEL_8197F) \ + << BIT_SHIFT_ACKBAR_TYPESEL_8197F) +#define BITS_ACKBAR_TYPESEL_8197F \ + (BIT_MASK_ACKBAR_TYPESEL_8197F << BIT_SHIFT_ACKBAR_TYPESEL_8197F) #define BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) ((x) & (~BITS_ACKBAR_TYPESEL_8197F)) -#define BIT_GET_ACKBAR_TYPESEL_8197F(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8197F) & BIT_MASK_ACKBAR_TYPESEL_8197F) -#define BIT_SET_ACKBAR_TYPESEL_8197F(x, v) (BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) | BIT_ACKBAR_TYPESEL_8197F(v)) - +#define BIT_GET_ACKBAR_TYPESEL_8197F(x) \ + (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8197F) & \ + BIT_MASK_ACKBAR_TYPESEL_8197F) +#define BIT_SET_ACKBAR_TYPESEL_8197F(x, v) \ + (BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) | BIT_ACKBAR_TYPESEL_8197F(v)) #define BIT_SHIFT_ACKBAR_ACKPCHK_8197F (44 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_ACKPCHK_8197F 0xf -#define BIT_ACKBAR_ACKPCHK_8197F(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8197F) << BIT_SHIFT_ACKBAR_ACKPCHK_8197F) -#define BITS_ACKBAR_ACKPCHK_8197F (BIT_MASK_ACKBAR_ACKPCHK_8197F << BIT_SHIFT_ACKBAR_ACKPCHK_8197F) +#define BIT_ACKBAR_ACKPCHK_8197F(x) \ + (((x) & BIT_MASK_ACKBAR_ACKPCHK_8197F) \ + << BIT_SHIFT_ACKBAR_ACKPCHK_8197F) +#define BITS_ACKBAR_ACKPCHK_8197F \ + (BIT_MASK_ACKBAR_ACKPCHK_8197F << BIT_SHIFT_ACKBAR_ACKPCHK_8197F) #define BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8197F)) -#define BIT_GET_ACKBAR_ACKPCHK_8197F(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8197F) & BIT_MASK_ACKBAR_ACKPCHK_8197F) -#define BIT_SET_ACKBAR_ACKPCHK_8197F(x, v) (BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) | BIT_ACKBAR_ACKPCHK_8197F(v)) +#define BIT_GET_ACKBAR_ACKPCHK_8197F(x) \ + (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8197F) & \ + BIT_MASK_ACKBAR_ACKPCHK_8197F) +#define BIT_SET_ACKBAR_ACKPCHK_8197F(x, v) \ + (BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) | BIT_ACKBAR_ACKPCHK_8197F(v)) #define BIT_RXBA_IGNOREA2_8197F BIT(42) #define BIT_EN_SAVE_ALL_TXOPADDR_8197F BIT(41) @@ -10673,11 +13999,15 @@ #define BIT_SHIFT_RESP_CHNBUSY_8197F 20 #define BIT_MASK_RESP_CHNBUSY_8197F 0x3 -#define BIT_RESP_CHNBUSY_8197F(x) (((x) & BIT_MASK_RESP_CHNBUSY_8197F) << BIT_SHIFT_RESP_CHNBUSY_8197F) -#define BITS_RESP_CHNBUSY_8197F (BIT_MASK_RESP_CHNBUSY_8197F << BIT_SHIFT_RESP_CHNBUSY_8197F) +#define BIT_RESP_CHNBUSY_8197F(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY_8197F) << BIT_SHIFT_RESP_CHNBUSY_8197F) +#define BITS_RESP_CHNBUSY_8197F \ + (BIT_MASK_RESP_CHNBUSY_8197F << BIT_SHIFT_RESP_CHNBUSY_8197F) #define BIT_CLEAR_RESP_CHNBUSY_8197F(x) ((x) & (~BITS_RESP_CHNBUSY_8197F)) -#define BIT_GET_RESP_CHNBUSY_8197F(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8197F) & BIT_MASK_RESP_CHNBUSY_8197F) -#define BIT_SET_RESP_CHNBUSY_8197F(x, v) (BIT_CLEAR_RESP_CHNBUSY_8197F(x) | BIT_RESP_CHNBUSY_8197F(v)) +#define BIT_GET_RESP_CHNBUSY_8197F(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY_8197F) & BIT_MASK_RESP_CHNBUSY_8197F) +#define BIT_SET_RESP_CHNBUSY_8197F(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY_8197F(x) | BIT_RESP_CHNBUSY_8197F(v)) #define BIT_RESP_DCTS_EN_8197F BIT(19) #define BIT_RESP_DCFE_EN_8197F BIT(18) @@ -10689,41 +14019,63 @@ #define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F 10 #define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F 0x7 -#define BIT_R_WMAC_SECOND_CCA_TIMER_8197F(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) -#define BITS_R_WMAC_SECOND_CCA_TIMER_8197F (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) -#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8197F)) -#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F) -#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8197F(x, v) (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) | BIT_R_WMAC_SECOND_CCA_TIMER_8197F(v)) - +#define BIT_R_WMAC_SECOND_CCA_TIMER_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) +#define BITS_R_WMAC_SECOND_CCA_TIMER_8197F \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8197F)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) | \ + BIT_R_WMAC_SECOND_CCA_TIMER_8197F(v)) #define BIT_SHIFT_RFMOD_8197F 7 #define BIT_MASK_RFMOD_8197F 0x3 -#define BIT_RFMOD_8197F(x) (((x) & BIT_MASK_RFMOD_8197F) << BIT_SHIFT_RFMOD_8197F) +#define BIT_RFMOD_8197F(x) \ + (((x) & BIT_MASK_RFMOD_8197F) << BIT_SHIFT_RFMOD_8197F) #define BITS_RFMOD_8197F (BIT_MASK_RFMOD_8197F << BIT_SHIFT_RFMOD_8197F) #define BIT_CLEAR_RFMOD_8197F(x) ((x) & (~BITS_RFMOD_8197F)) -#define BIT_GET_RFMOD_8197F(x) (((x) >> BIT_SHIFT_RFMOD_8197F) & BIT_MASK_RFMOD_8197F) -#define BIT_SET_RFMOD_8197F(x, v) (BIT_CLEAR_RFMOD_8197F(x) | BIT_RFMOD_8197F(v)) - +#define BIT_GET_RFMOD_8197F(x) \ + (((x) >> BIT_SHIFT_RFMOD_8197F) & BIT_MASK_RFMOD_8197F) +#define BIT_SET_RFMOD_8197F(x, v) \ + (BIT_CLEAR_RFMOD_8197F(x) | BIT_RFMOD_8197F(v)) #define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F 5 #define BIT_MASK_RESP_CTS_DYNBW_SEL_8197F 0x3 -#define BIT_RESP_CTS_DYNBW_SEL_8197F(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8197F) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) -#define BITS_RESP_CTS_DYNBW_SEL_8197F (BIT_MASK_RESP_CTS_DYNBW_SEL_8197F << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) -#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8197F)) -#define BIT_GET_RESP_CTS_DYNBW_SEL_8197F(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) & BIT_MASK_RESP_CTS_DYNBW_SEL_8197F) -#define BIT_SET_RESP_CTS_DYNBW_SEL_8197F(x, v) (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) | BIT_RESP_CTS_DYNBW_SEL_8197F(v)) +#define BIT_RESP_CTS_DYNBW_SEL_8197F(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8197F) \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) +#define BITS_RESP_CTS_DYNBW_SEL_8197F \ + (BIT_MASK_RESP_CTS_DYNBW_SEL_8197F \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) \ + ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8197F)) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) & \ + BIT_MASK_RESP_CTS_DYNBW_SEL_8197F) +#define BIT_SET_RESP_CTS_DYNBW_SEL_8197F(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) | \ + BIT_RESP_CTS_DYNBW_SEL_8197F(v)) #define BIT_DLY_TX_WAIT_RXANTSEL_8197F BIT(4) #define BIT_TXRESP_BY_RXANTSEL_8197F BIT(3) #define BIT_SHIFT_ORIG_DCTS_CHK_8197F 0 #define BIT_MASK_ORIG_DCTS_CHK_8197F 0x3 -#define BIT_ORIG_DCTS_CHK_8197F(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8197F) << BIT_SHIFT_ORIG_DCTS_CHK_8197F) -#define BITS_ORIG_DCTS_CHK_8197F (BIT_MASK_ORIG_DCTS_CHK_8197F << BIT_SHIFT_ORIG_DCTS_CHK_8197F) +#define BIT_ORIG_DCTS_CHK_8197F(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK_8197F) << BIT_SHIFT_ORIG_DCTS_CHK_8197F) +#define BITS_ORIG_DCTS_CHK_8197F \ + (BIT_MASK_ORIG_DCTS_CHK_8197F << BIT_SHIFT_ORIG_DCTS_CHK_8197F) #define BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) ((x) & (~BITS_ORIG_DCTS_CHK_8197F)) -#define BIT_GET_ORIG_DCTS_CHK_8197F(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8197F) & BIT_MASK_ORIG_DCTS_CHK_8197F) -#define BIT_SET_ORIG_DCTS_CHK_8197F(x, v) (BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) | BIT_ORIG_DCTS_CHK_8197F(v)) - +#define BIT_GET_ORIG_DCTS_CHK_8197F(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8197F) & BIT_MASK_ORIG_DCTS_CHK_8197F) +#define BIT_SET_ORIG_DCTS_CHK_8197F(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) | BIT_ORIG_DCTS_CHK_8197F(v)) /* 2 REG_CAMCMD_8197F (CAM COMMAND REGISTER) */ #define BIT_SECCAM_POLLING_8197F BIT(31) @@ -10733,34 +14085,45 @@ #define BIT_SHIFT_SECCAM_ADDR_V2_8197F 0 #define BIT_MASK_SECCAM_ADDR_V2_8197F 0x3ff -#define BIT_SECCAM_ADDR_V2_8197F(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8197F) << BIT_SHIFT_SECCAM_ADDR_V2_8197F) -#define BITS_SECCAM_ADDR_V2_8197F (BIT_MASK_SECCAM_ADDR_V2_8197F << BIT_SHIFT_SECCAM_ADDR_V2_8197F) +#define BIT_SECCAM_ADDR_V2_8197F(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2_8197F) \ + << BIT_SHIFT_SECCAM_ADDR_V2_8197F) +#define BITS_SECCAM_ADDR_V2_8197F \ + (BIT_MASK_SECCAM_ADDR_V2_8197F << BIT_SHIFT_SECCAM_ADDR_V2_8197F) #define BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) ((x) & (~BITS_SECCAM_ADDR_V2_8197F)) -#define BIT_GET_SECCAM_ADDR_V2_8197F(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8197F) & BIT_MASK_SECCAM_ADDR_V2_8197F) -#define BIT_SET_SECCAM_ADDR_V2_8197F(x, v) (BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) | BIT_SECCAM_ADDR_V2_8197F(v)) - +#define BIT_GET_SECCAM_ADDR_V2_8197F(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8197F) & \ + BIT_MASK_SECCAM_ADDR_V2_8197F) +#define BIT_SET_SECCAM_ADDR_V2_8197F(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) | BIT_SECCAM_ADDR_V2_8197F(v)) /* 2 REG_CAMWRITE_8197F (CAM WRITE REGISTER) */ #define BIT_SHIFT_CAMW_DATA_8197F 0 #define BIT_MASK_CAMW_DATA_8197F 0xffffffffL -#define BIT_CAMW_DATA_8197F(x) (((x) & BIT_MASK_CAMW_DATA_8197F) << BIT_SHIFT_CAMW_DATA_8197F) -#define BITS_CAMW_DATA_8197F (BIT_MASK_CAMW_DATA_8197F << BIT_SHIFT_CAMW_DATA_8197F) +#define BIT_CAMW_DATA_8197F(x) \ + (((x) & BIT_MASK_CAMW_DATA_8197F) << BIT_SHIFT_CAMW_DATA_8197F) +#define BITS_CAMW_DATA_8197F \ + (BIT_MASK_CAMW_DATA_8197F << BIT_SHIFT_CAMW_DATA_8197F) #define BIT_CLEAR_CAMW_DATA_8197F(x) ((x) & (~BITS_CAMW_DATA_8197F)) -#define BIT_GET_CAMW_DATA_8197F(x) (((x) >> BIT_SHIFT_CAMW_DATA_8197F) & BIT_MASK_CAMW_DATA_8197F) -#define BIT_SET_CAMW_DATA_8197F(x, v) (BIT_CLEAR_CAMW_DATA_8197F(x) | BIT_CAMW_DATA_8197F(v)) - +#define BIT_GET_CAMW_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_CAMW_DATA_8197F) & BIT_MASK_CAMW_DATA_8197F) +#define BIT_SET_CAMW_DATA_8197F(x, v) \ + (BIT_CLEAR_CAMW_DATA_8197F(x) | BIT_CAMW_DATA_8197F(v)) /* 2 REG_CAMREAD_8197F (CAM READ REGISTER) */ #define BIT_SHIFT_CAMR_DATA_8197F 0 #define BIT_MASK_CAMR_DATA_8197F 0xffffffffL -#define BIT_CAMR_DATA_8197F(x) (((x) & BIT_MASK_CAMR_DATA_8197F) << BIT_SHIFT_CAMR_DATA_8197F) -#define BITS_CAMR_DATA_8197F (BIT_MASK_CAMR_DATA_8197F << BIT_SHIFT_CAMR_DATA_8197F) +#define BIT_CAMR_DATA_8197F(x) \ + (((x) & BIT_MASK_CAMR_DATA_8197F) << BIT_SHIFT_CAMR_DATA_8197F) +#define BITS_CAMR_DATA_8197F \ + (BIT_MASK_CAMR_DATA_8197F << BIT_SHIFT_CAMR_DATA_8197F) #define BIT_CLEAR_CAMR_DATA_8197F(x) ((x) & (~BITS_CAMR_DATA_8197F)) -#define BIT_GET_CAMR_DATA_8197F(x) (((x) >> BIT_SHIFT_CAMR_DATA_8197F) & BIT_MASK_CAMR_DATA_8197F) -#define BIT_SET_CAMR_DATA_8197F(x, v) (BIT_CLEAR_CAMR_DATA_8197F(x) | BIT_CAMR_DATA_8197F(v)) - +#define BIT_GET_CAMR_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_CAMR_DATA_8197F) & BIT_MASK_CAMR_DATA_8197F) +#define BIT_SET_CAMR_DATA_8197F(x, v) \ + (BIT_CLEAR_CAMR_DATA_8197F(x) | BIT_CAMR_DATA_8197F(v)) /* 2 REG_CAMDBG_8197F (CAM DEBUG REGISTER) */ #define BIT_SECCAM_INFO_8197F BIT(31) @@ -10768,53 +14131,89 @@ #define BIT_SHIFT_CAMDBG_SEC_TYPE_8197F 12 #define BIT_MASK_CAMDBG_SEC_TYPE_8197F 0x7 -#define BIT_CAMDBG_SEC_TYPE_8197F(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8197F) << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) -#define BITS_CAMDBG_SEC_TYPE_8197F (BIT_MASK_CAMDBG_SEC_TYPE_8197F << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) +#define BIT_CAMDBG_SEC_TYPE_8197F(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8197F) \ + << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) +#define BITS_CAMDBG_SEC_TYPE_8197F \ + (BIT_MASK_CAMDBG_SEC_TYPE_8197F << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) #define BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8197F)) -#define BIT_GET_CAMDBG_SEC_TYPE_8197F(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) & BIT_MASK_CAMDBG_SEC_TYPE_8197F) -#define BIT_SET_CAMDBG_SEC_TYPE_8197F(x, v) (BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) | BIT_CAMDBG_SEC_TYPE_8197F(v)) +#define BIT_GET_CAMDBG_SEC_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) & \ + BIT_MASK_CAMDBG_SEC_TYPE_8197F) +#define BIT_SET_CAMDBG_SEC_TYPE_8197F(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) | BIT_CAMDBG_SEC_TYPE_8197F(v)) #define BIT_CAMDBG_EXT_SEC_TYPE_8197F BIT(11) #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F 5 #define BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F 0x1f -#define BIT_CAMDBG_MIC_KEY_IDX_8197F(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) -#define BITS_CAMDBG_MIC_KEY_IDX_8197F (BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) -#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8197F)) -#define BIT_GET_CAMDBG_MIC_KEY_IDX_8197F(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F) -#define BIT_SET_CAMDBG_MIC_KEY_IDX_8197F(x, v) (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) | BIT_CAMDBG_MIC_KEY_IDX_8197F(v)) - +#define BIT_CAMDBG_MIC_KEY_IDX_8197F(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) +#define BITS_CAMDBG_MIC_KEY_IDX_8197F \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) \ + ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8197F)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_8197F(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) | \ + BIT_CAMDBG_MIC_KEY_IDX_8197F(v)) #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F 0x1f -#define BIT_CAMDBG_SEC_KEY_IDX_8197F(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) -#define BITS_CAMDBG_SEC_KEY_IDX_8197F (BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) -#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8197F)) -#define BIT_GET_CAMDBG_SEC_KEY_IDX_8197F(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F) -#define BIT_SET_CAMDBG_SEC_KEY_IDX_8197F(x, v) (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) | BIT_CAMDBG_SEC_KEY_IDX_8197F(v)) - +#define BIT_CAMDBG_SEC_KEY_IDX_8197F(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) +#define BITS_CAMDBG_SEC_KEY_IDX_8197F \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) \ + ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8197F)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_8197F(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) | \ + BIT_CAMDBG_SEC_KEY_IDX_8197F(v)) /* 2 REG_RXFILTER_ACTION_1_8197F */ #define BIT_SHIFT_RXFILTER_ACTION_1_8197F 0 #define BIT_MASK_RXFILTER_ACTION_1_8197F 0xff -#define BIT_RXFILTER_ACTION_1_8197F(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8197F) << BIT_SHIFT_RXFILTER_ACTION_1_8197F) -#define BITS_RXFILTER_ACTION_1_8197F (BIT_MASK_RXFILTER_ACTION_1_8197F << BIT_SHIFT_RXFILTER_ACTION_1_8197F) -#define BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) ((x) & (~BITS_RXFILTER_ACTION_1_8197F)) -#define BIT_GET_RXFILTER_ACTION_1_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8197F) & BIT_MASK_RXFILTER_ACTION_1_8197F) -#define BIT_SET_RXFILTER_ACTION_1_8197F(x, v) (BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) | BIT_RXFILTER_ACTION_1_8197F(v)) - +#define BIT_RXFILTER_ACTION_1_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1_8197F) \ + << BIT_SHIFT_RXFILTER_ACTION_1_8197F) +#define BITS_RXFILTER_ACTION_1_8197F \ + (BIT_MASK_RXFILTER_ACTION_1_8197F << BIT_SHIFT_RXFILTER_ACTION_1_8197F) +#define BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) \ + ((x) & (~BITS_RXFILTER_ACTION_1_8197F)) +#define BIT_GET_RXFILTER_ACTION_1_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8197F) & \ + BIT_MASK_RXFILTER_ACTION_1_8197F) +#define BIT_SET_RXFILTER_ACTION_1_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) | BIT_RXFILTER_ACTION_1_8197F(v)) /* 2 REG_RXFILTER_CATEGORY_1_8197F */ #define BIT_SHIFT_RXFILTER_CATEGORY_1_8197F 0 #define BIT_MASK_RXFILTER_CATEGORY_1_8197F 0xff -#define BIT_RXFILTER_CATEGORY_1_8197F(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8197F) << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) -#define BITS_RXFILTER_CATEGORY_1_8197F (BIT_MASK_RXFILTER_CATEGORY_1_8197F << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) -#define BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) ((x) & (~BITS_RXFILTER_CATEGORY_1_8197F)) -#define BIT_GET_RXFILTER_CATEGORY_1_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) & BIT_MASK_RXFILTER_CATEGORY_1_8197F) -#define BIT_SET_RXFILTER_CATEGORY_1_8197F(x, v) (BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) | BIT_RXFILTER_CATEGORY_1_8197F(v)) - +#define BIT_RXFILTER_CATEGORY_1_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8197F) \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) +#define BITS_RXFILTER_CATEGORY_1_8197F \ + (BIT_MASK_RXFILTER_CATEGORY_1_8197F \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) +#define BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_1_8197F)) +#define BIT_GET_RXFILTER_CATEGORY_1_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) & \ + BIT_MASK_RXFILTER_CATEGORY_1_8197F) +#define BIT_SET_RXFILTER_CATEGORY_1_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) | \ + BIT_RXFILTER_CATEGORY_1_8197F(v)) /* 2 REG_SECCFG_8197F (SECURITY CONFIGURATION REGISTER) */ #define BIT_DIS_GCLK_WAPI_8197F BIT(15) @@ -10837,45 +14236,73 @@ #define BIT_SHIFT_RXFILTER_ACTION_3_8197F 0 #define BIT_MASK_RXFILTER_ACTION_3_8197F 0xff -#define BIT_RXFILTER_ACTION_3_8197F(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8197F) << BIT_SHIFT_RXFILTER_ACTION_3_8197F) -#define BITS_RXFILTER_ACTION_3_8197F (BIT_MASK_RXFILTER_ACTION_3_8197F << BIT_SHIFT_RXFILTER_ACTION_3_8197F) -#define BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) ((x) & (~BITS_RXFILTER_ACTION_3_8197F)) -#define BIT_GET_RXFILTER_ACTION_3_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8197F) & BIT_MASK_RXFILTER_ACTION_3_8197F) -#define BIT_SET_RXFILTER_ACTION_3_8197F(x, v) (BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) | BIT_RXFILTER_ACTION_3_8197F(v)) - +#define BIT_RXFILTER_ACTION_3_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3_8197F) \ + << BIT_SHIFT_RXFILTER_ACTION_3_8197F) +#define BITS_RXFILTER_ACTION_3_8197F \ + (BIT_MASK_RXFILTER_ACTION_3_8197F << BIT_SHIFT_RXFILTER_ACTION_3_8197F) +#define BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) \ + ((x) & (~BITS_RXFILTER_ACTION_3_8197F)) +#define BIT_GET_RXFILTER_ACTION_3_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8197F) & \ + BIT_MASK_RXFILTER_ACTION_3_8197F) +#define BIT_SET_RXFILTER_ACTION_3_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) | BIT_RXFILTER_ACTION_3_8197F(v)) /* 2 REG_RXFILTER_CATEGORY_3_8197F */ #define BIT_SHIFT_RXFILTER_CATEGORY_3_8197F 0 #define BIT_MASK_RXFILTER_CATEGORY_3_8197F 0xff -#define BIT_RXFILTER_CATEGORY_3_8197F(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8197F) << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) -#define BITS_RXFILTER_CATEGORY_3_8197F (BIT_MASK_RXFILTER_CATEGORY_3_8197F << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) -#define BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) ((x) & (~BITS_RXFILTER_CATEGORY_3_8197F)) -#define BIT_GET_RXFILTER_CATEGORY_3_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) & BIT_MASK_RXFILTER_CATEGORY_3_8197F) -#define BIT_SET_RXFILTER_CATEGORY_3_8197F(x, v) (BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) | BIT_RXFILTER_CATEGORY_3_8197F(v)) - +#define BIT_RXFILTER_CATEGORY_3_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8197F) \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) +#define BITS_RXFILTER_CATEGORY_3_8197F \ + (BIT_MASK_RXFILTER_CATEGORY_3_8197F \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) +#define BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_3_8197F)) +#define BIT_GET_RXFILTER_CATEGORY_3_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) & \ + BIT_MASK_RXFILTER_CATEGORY_3_8197F) +#define BIT_SET_RXFILTER_CATEGORY_3_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) | \ + BIT_RXFILTER_CATEGORY_3_8197F(v)) /* 2 REG_RXFILTER_ACTION_2_8197F */ #define BIT_SHIFT_RXFILTER_ACTION_2_8197F 0 #define BIT_MASK_RXFILTER_ACTION_2_8197F 0xff -#define BIT_RXFILTER_ACTION_2_8197F(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8197F) << BIT_SHIFT_RXFILTER_ACTION_2_8197F) -#define BITS_RXFILTER_ACTION_2_8197F (BIT_MASK_RXFILTER_ACTION_2_8197F << BIT_SHIFT_RXFILTER_ACTION_2_8197F) -#define BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) ((x) & (~BITS_RXFILTER_ACTION_2_8197F)) -#define BIT_GET_RXFILTER_ACTION_2_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8197F) & BIT_MASK_RXFILTER_ACTION_2_8197F) -#define BIT_SET_RXFILTER_ACTION_2_8197F(x, v) (BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) | BIT_RXFILTER_ACTION_2_8197F(v)) - +#define BIT_RXFILTER_ACTION_2_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2_8197F) \ + << BIT_SHIFT_RXFILTER_ACTION_2_8197F) +#define BITS_RXFILTER_ACTION_2_8197F \ + (BIT_MASK_RXFILTER_ACTION_2_8197F << BIT_SHIFT_RXFILTER_ACTION_2_8197F) +#define BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) \ + ((x) & (~BITS_RXFILTER_ACTION_2_8197F)) +#define BIT_GET_RXFILTER_ACTION_2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8197F) & \ + BIT_MASK_RXFILTER_ACTION_2_8197F) +#define BIT_SET_RXFILTER_ACTION_2_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) | BIT_RXFILTER_ACTION_2_8197F(v)) /* 2 REG_RXFILTER_CATEGORY_2_8197F */ #define BIT_SHIFT_RXFILTER_CATEGORY_2_8197F 0 #define BIT_MASK_RXFILTER_CATEGORY_2_8197F 0xff -#define BIT_RXFILTER_CATEGORY_2_8197F(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8197F) << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) -#define BITS_RXFILTER_CATEGORY_2_8197F (BIT_MASK_RXFILTER_CATEGORY_2_8197F << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) -#define BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) ((x) & (~BITS_RXFILTER_CATEGORY_2_8197F)) -#define BIT_GET_RXFILTER_CATEGORY_2_8197F(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) & BIT_MASK_RXFILTER_CATEGORY_2_8197F) -#define BIT_SET_RXFILTER_CATEGORY_2_8197F(x, v) (BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) | BIT_RXFILTER_CATEGORY_2_8197F(v)) - +#define BIT_RXFILTER_CATEGORY_2_8197F(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8197F) \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) +#define BITS_RXFILTER_CATEGORY_2_8197F \ + (BIT_MASK_RXFILTER_CATEGORY_2_8197F \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) +#define BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_2_8197F)) +#define BIT_GET_RXFILTER_CATEGORY_2_8197F(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) & \ + BIT_MASK_RXFILTER_CATEGORY_2_8197F) +#define BIT_SET_RXFILTER_CATEGORY_2_8197F(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) | \ + BIT_RXFILTER_CATEGORY_2_8197F(v)) /* 2 REG_RXFLTMAP4_8197F (RX FILTER MAP GROUP 4) */ #define BIT_CTRLFLT15EN_FW_8197F BIT(15) @@ -10963,11 +14390,20 @@ #define BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F 5 #define BIT_MASK_PORTSEL__PS_RX_INFO_8197F 0x7 -#define BIT_PORTSEL__PS_RX_INFO_8197F(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8197F) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) -#define BITS_PORTSEL__PS_RX_INFO_8197F (BIT_MASK_PORTSEL__PS_RX_INFO_8197F << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) -#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) ((x) & (~BITS_PORTSEL__PS_RX_INFO_8197F)) -#define BIT_GET_PORTSEL__PS_RX_INFO_8197F(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) & BIT_MASK_PORTSEL__PS_RX_INFO_8197F) -#define BIT_SET_PORTSEL__PS_RX_INFO_8197F(x, v) (BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) | BIT_PORTSEL__PS_RX_INFO_8197F(v)) +#define BIT_PORTSEL__PS_RX_INFO_8197F(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8197F) \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) +#define BITS_PORTSEL__PS_RX_INFO_8197F \ + (BIT_MASK_PORTSEL__PS_RX_INFO_8197F \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) \ + ((x) & (~BITS_PORTSEL__PS_RX_INFO_8197F)) +#define BIT_GET_PORTSEL__PS_RX_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) & \ + BIT_MASK_PORTSEL__PS_RX_INFO_8197F) +#define BIT_SET_PORTSEL__PS_RX_INFO_8197F(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) | \ + BIT_PORTSEL__PS_RX_INFO_8197F(v)) #define BIT_RXCTRLIN0_8197F BIT(4) #define BIT_RXMGTIN0_8197F BIT(3) @@ -10984,11 +14420,18 @@ #define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F 6 #define BIT_MASK_PSF_BSSIDSEL_B2B1_8197F 0x3 -#define BIT_PSF_BSSIDSEL_B2B1_8197F(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8197F) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) -#define BITS_PSF_BSSIDSEL_B2B1_8197F (BIT_MASK_PSF_BSSIDSEL_B2B1_8197F << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) -#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8197F)) -#define BIT_GET_PSF_BSSIDSEL_B2B1_8197F(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) & BIT_MASK_PSF_BSSIDSEL_B2B1_8197F) -#define BIT_SET_PSF_BSSIDSEL_B2B1_8197F(x, v) (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) | BIT_PSF_BSSIDSEL_B2B1_8197F(v)) +#define BIT_PSF_BSSIDSEL_B2B1_8197F(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8197F) \ + << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) +#define BITS_PSF_BSSIDSEL_B2B1_8197F \ + (BIT_MASK_PSF_BSSIDSEL_B2B1_8197F << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) \ + ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8197F)) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8197F(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) & \ + BIT_MASK_PSF_BSSIDSEL_B2B1_8197F) +#define BIT_SET_PSF_BSSIDSEL_B2B1_8197F(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) | BIT_PSF_BSSIDSEL_B2B1_8197F(v)) #define BIT_WOWHCI_8197F BIT(5) #define BIT_PSF_BSSIDSEL_B0_8197F BIT(4) @@ -11002,21 +14445,27 @@ #define BIT_SHIFT_LPNAV_EARLY_8197F 16 #define BIT_MASK_LPNAV_EARLY_8197F 0x7fff -#define BIT_LPNAV_EARLY_8197F(x) (((x) & BIT_MASK_LPNAV_EARLY_8197F) << BIT_SHIFT_LPNAV_EARLY_8197F) -#define BITS_LPNAV_EARLY_8197F (BIT_MASK_LPNAV_EARLY_8197F << BIT_SHIFT_LPNAV_EARLY_8197F) +#define BIT_LPNAV_EARLY_8197F(x) \ + (((x) & BIT_MASK_LPNAV_EARLY_8197F) << BIT_SHIFT_LPNAV_EARLY_8197F) +#define BITS_LPNAV_EARLY_8197F \ + (BIT_MASK_LPNAV_EARLY_8197F << BIT_SHIFT_LPNAV_EARLY_8197F) #define BIT_CLEAR_LPNAV_EARLY_8197F(x) ((x) & (~BITS_LPNAV_EARLY_8197F)) -#define BIT_GET_LPNAV_EARLY_8197F(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8197F) & BIT_MASK_LPNAV_EARLY_8197F) -#define BIT_SET_LPNAV_EARLY_8197F(x, v) (BIT_CLEAR_LPNAV_EARLY_8197F(x) | BIT_LPNAV_EARLY_8197F(v)) - +#define BIT_GET_LPNAV_EARLY_8197F(x) \ + (((x) >> BIT_SHIFT_LPNAV_EARLY_8197F) & BIT_MASK_LPNAV_EARLY_8197F) +#define BIT_SET_LPNAV_EARLY_8197F(x, v) \ + (BIT_CLEAR_LPNAV_EARLY_8197F(x) | BIT_LPNAV_EARLY_8197F(v)) #define BIT_SHIFT_LPNAV_TH_8197F 0 #define BIT_MASK_LPNAV_TH_8197F 0xffff -#define BIT_LPNAV_TH_8197F(x) (((x) & BIT_MASK_LPNAV_TH_8197F) << BIT_SHIFT_LPNAV_TH_8197F) -#define BITS_LPNAV_TH_8197F (BIT_MASK_LPNAV_TH_8197F << BIT_SHIFT_LPNAV_TH_8197F) +#define BIT_LPNAV_TH_8197F(x) \ + (((x) & BIT_MASK_LPNAV_TH_8197F) << BIT_SHIFT_LPNAV_TH_8197F) +#define BITS_LPNAV_TH_8197F \ + (BIT_MASK_LPNAV_TH_8197F << BIT_SHIFT_LPNAV_TH_8197F) #define BIT_CLEAR_LPNAV_TH_8197F(x) ((x) & (~BITS_LPNAV_TH_8197F)) -#define BIT_GET_LPNAV_TH_8197F(x) (((x) >> BIT_SHIFT_LPNAV_TH_8197F) & BIT_MASK_LPNAV_TH_8197F) -#define BIT_SET_LPNAV_TH_8197F(x, v) (BIT_CLEAR_LPNAV_TH_8197F(x) | BIT_LPNAV_TH_8197F(v)) - +#define BIT_GET_LPNAV_TH_8197F(x) \ + (((x) >> BIT_SHIFT_LPNAV_TH_8197F) & BIT_MASK_LPNAV_TH_8197F) +#define BIT_SET_LPNAV_TH_8197F(x, v) \ + (BIT_CLEAR_LPNAV_TH_8197F(x) | BIT_LPNAV_TH_8197F(v)) /* 2 REG_WKFMCAM_CMD_8197F (WAKEUP FRAME CAM COMMAND REGISTER) */ #define BIT_WKFCAM_POLLING_V1_8197F BIT(31) @@ -11025,32 +14474,46 @@ #define BIT_SHIFT_WKFCAM_ADDR_V2_8197F 8 #define BIT_MASK_WKFCAM_ADDR_V2_8197F 0xff -#define BIT_WKFCAM_ADDR_V2_8197F(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8197F) << BIT_SHIFT_WKFCAM_ADDR_V2_8197F) -#define BITS_WKFCAM_ADDR_V2_8197F (BIT_MASK_WKFCAM_ADDR_V2_8197F << BIT_SHIFT_WKFCAM_ADDR_V2_8197F) +#define BIT_WKFCAM_ADDR_V2_8197F(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2_8197F) \ + << BIT_SHIFT_WKFCAM_ADDR_V2_8197F) +#define BITS_WKFCAM_ADDR_V2_8197F \ + (BIT_MASK_WKFCAM_ADDR_V2_8197F << BIT_SHIFT_WKFCAM_ADDR_V2_8197F) #define BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8197F)) -#define BIT_GET_WKFCAM_ADDR_V2_8197F(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8197F) & BIT_MASK_WKFCAM_ADDR_V2_8197F) -#define BIT_SET_WKFCAM_ADDR_V2_8197F(x, v) (BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) | BIT_WKFCAM_ADDR_V2_8197F(v)) - +#define BIT_GET_WKFCAM_ADDR_V2_8197F(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8197F) & \ + BIT_MASK_WKFCAM_ADDR_V2_8197F) +#define BIT_SET_WKFCAM_ADDR_V2_8197F(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) | BIT_WKFCAM_ADDR_V2_8197F(v)) #define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F 0 #define BIT_MASK_WKFCAM_CAM_NUM_V1_8197F 0xff -#define BIT_WKFCAM_CAM_NUM_V1_8197F(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8197F) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) -#define BITS_WKFCAM_CAM_NUM_V1_8197F (BIT_MASK_WKFCAM_CAM_NUM_V1_8197F << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) -#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8197F)) -#define BIT_GET_WKFCAM_CAM_NUM_V1_8197F(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) & BIT_MASK_WKFCAM_CAM_NUM_V1_8197F) -#define BIT_SET_WKFCAM_CAM_NUM_V1_8197F(x, v) (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) | BIT_WKFCAM_CAM_NUM_V1_8197F(v)) - +#define BIT_WKFCAM_CAM_NUM_V1_8197F(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8197F) \ + << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) +#define BITS_WKFCAM_CAM_NUM_V1_8197F \ + (BIT_MASK_WKFCAM_CAM_NUM_V1_8197F << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) \ + ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8197F)) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8197F(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) & \ + BIT_MASK_WKFCAM_CAM_NUM_V1_8197F) +#define BIT_SET_WKFCAM_CAM_NUM_V1_8197F(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) | BIT_WKFCAM_CAM_NUM_V1_8197F(v)) /* 2 REG_WKFMCAM_RWD_8197F (WAKEUP FRAME READ/WRITE DATA) */ #define BIT_SHIFT_WKFMCAM_RWD_8197F 0 #define BIT_MASK_WKFMCAM_RWD_8197F 0xffffffffL -#define BIT_WKFMCAM_RWD_8197F(x) (((x) & BIT_MASK_WKFMCAM_RWD_8197F) << BIT_SHIFT_WKFMCAM_RWD_8197F) -#define BITS_WKFMCAM_RWD_8197F (BIT_MASK_WKFMCAM_RWD_8197F << BIT_SHIFT_WKFMCAM_RWD_8197F) +#define BIT_WKFMCAM_RWD_8197F(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD_8197F) << BIT_SHIFT_WKFMCAM_RWD_8197F) +#define BITS_WKFMCAM_RWD_8197F \ + (BIT_MASK_WKFMCAM_RWD_8197F << BIT_SHIFT_WKFMCAM_RWD_8197F) #define BIT_CLEAR_WKFMCAM_RWD_8197F(x) ((x) & (~BITS_WKFMCAM_RWD_8197F)) -#define BIT_GET_WKFMCAM_RWD_8197F(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8197F) & BIT_MASK_WKFMCAM_RWD_8197F) -#define BIT_SET_WKFMCAM_RWD_8197F(x, v) (BIT_CLEAR_WKFMCAM_RWD_8197F(x) | BIT_WKFMCAM_RWD_8197F(v)) - +#define BIT_GET_WKFMCAM_RWD_8197F(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD_8197F) & BIT_MASK_WKFMCAM_RWD_8197F) +#define BIT_SET_WKFMCAM_RWD_8197F(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD_8197F(x) | BIT_WKFMCAM_RWD_8197F(v)) /* 2 REG_RXFLTMAP1_8197F (RX FILTER MAP GROUP 1) */ #define BIT_CTRLFLT15EN_8197F BIT(15) @@ -11112,32 +14575,42 @@ #define BIT_SHIFT_DTIM_CNT_8197F 24 #define BIT_MASK_DTIM_CNT_8197F 0xff -#define BIT_DTIM_CNT_8197F(x) (((x) & BIT_MASK_DTIM_CNT_8197F) << BIT_SHIFT_DTIM_CNT_8197F) -#define BITS_DTIM_CNT_8197F (BIT_MASK_DTIM_CNT_8197F << BIT_SHIFT_DTIM_CNT_8197F) +#define BIT_DTIM_CNT_8197F(x) \ + (((x) & BIT_MASK_DTIM_CNT_8197F) << BIT_SHIFT_DTIM_CNT_8197F) +#define BITS_DTIM_CNT_8197F \ + (BIT_MASK_DTIM_CNT_8197F << BIT_SHIFT_DTIM_CNT_8197F) #define BIT_CLEAR_DTIM_CNT_8197F(x) ((x) & (~BITS_DTIM_CNT_8197F)) -#define BIT_GET_DTIM_CNT_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT_8197F) & BIT_MASK_DTIM_CNT_8197F) -#define BIT_SET_DTIM_CNT_8197F(x, v) (BIT_CLEAR_DTIM_CNT_8197F(x) | BIT_DTIM_CNT_8197F(v)) - +#define BIT_GET_DTIM_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT_8197F) & BIT_MASK_DTIM_CNT_8197F) +#define BIT_SET_DTIM_CNT_8197F(x, v) \ + (BIT_CLEAR_DTIM_CNT_8197F(x) | BIT_DTIM_CNT_8197F(v)) #define BIT_SHIFT_DTIM_PERIOD_8197F 16 #define BIT_MASK_DTIM_PERIOD_8197F 0xff -#define BIT_DTIM_PERIOD_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD_8197F) << BIT_SHIFT_DTIM_PERIOD_8197F) -#define BITS_DTIM_PERIOD_8197F (BIT_MASK_DTIM_PERIOD_8197F << BIT_SHIFT_DTIM_PERIOD_8197F) +#define BIT_DTIM_PERIOD_8197F(x) \ + (((x) & BIT_MASK_DTIM_PERIOD_8197F) << BIT_SHIFT_DTIM_PERIOD_8197F) +#define BITS_DTIM_PERIOD_8197F \ + (BIT_MASK_DTIM_PERIOD_8197F << BIT_SHIFT_DTIM_PERIOD_8197F) #define BIT_CLEAR_DTIM_PERIOD_8197F(x) ((x) & (~BITS_DTIM_PERIOD_8197F)) -#define BIT_GET_DTIM_PERIOD_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8197F) & BIT_MASK_DTIM_PERIOD_8197F) -#define BIT_SET_DTIM_PERIOD_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD_8197F(x) | BIT_DTIM_PERIOD_8197F(v)) +#define BIT_GET_DTIM_PERIOD_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD_8197F) & BIT_MASK_DTIM_PERIOD_8197F) +#define BIT_SET_DTIM_PERIOD_8197F(x, v) \ + (BIT_CLEAR_DTIM_PERIOD_8197F(x) | BIT_DTIM_PERIOD_8197F(v)) #define BIT_DTIM_8197F BIT(15) #define BIT_TIM_8197F BIT(14) #define BIT_SHIFT_PS_AID_0_8197F 0 #define BIT_MASK_PS_AID_0_8197F 0x7ff -#define BIT_PS_AID_0_8197F(x) (((x) & BIT_MASK_PS_AID_0_8197F) << BIT_SHIFT_PS_AID_0_8197F) -#define BITS_PS_AID_0_8197F (BIT_MASK_PS_AID_0_8197F << BIT_SHIFT_PS_AID_0_8197F) +#define BIT_PS_AID_0_8197F(x) \ + (((x) & BIT_MASK_PS_AID_0_8197F) << BIT_SHIFT_PS_AID_0_8197F) +#define BITS_PS_AID_0_8197F \ + (BIT_MASK_PS_AID_0_8197F << BIT_SHIFT_PS_AID_0_8197F) #define BIT_CLEAR_PS_AID_0_8197F(x) ((x) & (~BITS_PS_AID_0_8197F)) -#define BIT_GET_PS_AID_0_8197F(x) (((x) >> BIT_SHIFT_PS_AID_0_8197F) & BIT_MASK_PS_AID_0_8197F) -#define BIT_SET_PS_AID_0_8197F(x, v) (BIT_CLEAR_PS_AID_0_8197F(x) | BIT_PS_AID_0_8197F(v)) - +#define BIT_GET_PS_AID_0_8197F(x) \ + (((x) >> BIT_SHIFT_PS_AID_0_8197F) & BIT_MASK_PS_AID_0_8197F) +#define BIT_SET_PS_AID_0_8197F(x, v) \ + (BIT_CLEAR_PS_AID_0_8197F(x) | BIT_PS_AID_0_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_FLC_RPCT_V1_8197F BIT(7) @@ -11145,12 +14618,14 @@ #define BIT_SHIFT_TRPCD_8197F 0 #define BIT_MASK_TRPCD_8197F 0x3f -#define BIT_TRPCD_8197F(x) (((x) & BIT_MASK_TRPCD_8197F) << BIT_SHIFT_TRPCD_8197F) +#define BIT_TRPCD_8197F(x) \ + (((x) & BIT_MASK_TRPCD_8197F) << BIT_SHIFT_TRPCD_8197F) #define BITS_TRPCD_8197F (BIT_MASK_TRPCD_8197F << BIT_SHIFT_TRPCD_8197F) #define BIT_CLEAR_TRPCD_8197F(x) ((x) & (~BITS_TRPCD_8197F)) -#define BIT_GET_TRPCD_8197F(x) (((x) >> BIT_SHIFT_TRPCD_8197F) & BIT_MASK_TRPCD_8197F) -#define BIT_SET_TRPCD_8197F(x, v) (BIT_CLEAR_TRPCD_8197F(x) | BIT_TRPCD_8197F(v)) - +#define BIT_GET_TRPCD_8197F(x) \ + (((x) >> BIT_SHIFT_TRPCD_8197F) & BIT_MASK_TRPCD_8197F) +#define BIT_SET_TRPCD_8197F(x, v) \ + (BIT_CLEAR_TRPCD_8197F(x) | BIT_TRPCD_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_CMF_8197F BIT(2) @@ -11161,60 +14636,78 @@ #define BIT_SHIFT_FLC_RPCT_8197F 0 #define BIT_MASK_FLC_RPCT_8197F 0xff -#define BIT_FLC_RPCT_8197F(x) (((x) & BIT_MASK_FLC_RPCT_8197F) << BIT_SHIFT_FLC_RPCT_8197F) -#define BITS_FLC_RPCT_8197F (BIT_MASK_FLC_RPCT_8197F << BIT_SHIFT_FLC_RPCT_8197F) +#define BIT_FLC_RPCT_8197F(x) \ + (((x) & BIT_MASK_FLC_RPCT_8197F) << BIT_SHIFT_FLC_RPCT_8197F) +#define BITS_FLC_RPCT_8197F \ + (BIT_MASK_FLC_RPCT_8197F << BIT_SHIFT_FLC_RPCT_8197F) #define BIT_CLEAR_FLC_RPCT_8197F(x) ((x) & (~BITS_FLC_RPCT_8197F)) -#define BIT_GET_FLC_RPCT_8197F(x) (((x) >> BIT_SHIFT_FLC_RPCT_8197F) & BIT_MASK_FLC_RPCT_8197F) -#define BIT_SET_FLC_RPCT_8197F(x, v) (BIT_CLEAR_FLC_RPCT_8197F(x) | BIT_FLC_RPCT_8197F(v)) - +#define BIT_GET_FLC_RPCT_8197F(x) \ + (((x) >> BIT_SHIFT_FLC_RPCT_8197F) & BIT_MASK_FLC_RPCT_8197F) +#define BIT_SET_FLC_RPCT_8197F(x, v) \ + (BIT_CLEAR_FLC_RPCT_8197F(x) | BIT_FLC_RPCT_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_SHIFT_FLC_RPC_8197F 0 #define BIT_MASK_FLC_RPC_8197F 0xff -#define BIT_FLC_RPC_8197F(x) (((x) & BIT_MASK_FLC_RPC_8197F) << BIT_SHIFT_FLC_RPC_8197F) +#define BIT_FLC_RPC_8197F(x) \ + (((x) & BIT_MASK_FLC_RPC_8197F) << BIT_SHIFT_FLC_RPC_8197F) #define BITS_FLC_RPC_8197F (BIT_MASK_FLC_RPC_8197F << BIT_SHIFT_FLC_RPC_8197F) #define BIT_CLEAR_FLC_RPC_8197F(x) ((x) & (~BITS_FLC_RPC_8197F)) -#define BIT_GET_FLC_RPC_8197F(x) (((x) >> BIT_SHIFT_FLC_RPC_8197F) & BIT_MASK_FLC_RPC_8197F) -#define BIT_SET_FLC_RPC_8197F(x, v) (BIT_CLEAR_FLC_RPC_8197F(x) | BIT_FLC_RPC_8197F(v)) - +#define BIT_GET_FLC_RPC_8197F(x) \ + (((x) >> BIT_SHIFT_FLC_RPC_8197F) & BIT_MASK_FLC_RPC_8197F) +#define BIT_SET_FLC_RPC_8197F(x, v) \ + (BIT_CLEAR_FLC_RPC_8197F(x) | BIT_FLC_RPC_8197F(v)) /* 2 REG_RXPKTMON_CTRL_8197F */ #define BIT_SHIFT_RXBKQPKT_SEQ_8197F 20 #define BIT_MASK_RXBKQPKT_SEQ_8197F 0xf -#define BIT_RXBKQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8197F) << BIT_SHIFT_RXBKQPKT_SEQ_8197F) -#define BITS_RXBKQPKT_SEQ_8197F (BIT_MASK_RXBKQPKT_SEQ_8197F << BIT_SHIFT_RXBKQPKT_SEQ_8197F) +#define BIT_RXBKQPKT_SEQ_8197F(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ_8197F) << BIT_SHIFT_RXBKQPKT_SEQ_8197F) +#define BITS_RXBKQPKT_SEQ_8197F \ + (BIT_MASK_RXBKQPKT_SEQ_8197F << BIT_SHIFT_RXBKQPKT_SEQ_8197F) #define BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBKQPKT_SEQ_8197F)) -#define BIT_GET_RXBKQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8197F) & BIT_MASK_RXBKQPKT_SEQ_8197F) -#define BIT_SET_RXBKQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) | BIT_RXBKQPKT_SEQ_8197F(v)) - +#define BIT_GET_RXBKQPKT_SEQ_8197F(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8197F) & BIT_MASK_RXBKQPKT_SEQ_8197F) +#define BIT_SET_RXBKQPKT_SEQ_8197F(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) | BIT_RXBKQPKT_SEQ_8197F(v)) #define BIT_SHIFT_RXBEQPKT_SEQ_8197F 16 #define BIT_MASK_RXBEQPKT_SEQ_8197F 0xf -#define BIT_RXBEQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8197F) << BIT_SHIFT_RXBEQPKT_SEQ_8197F) -#define BITS_RXBEQPKT_SEQ_8197F (BIT_MASK_RXBEQPKT_SEQ_8197F << BIT_SHIFT_RXBEQPKT_SEQ_8197F) +#define BIT_RXBEQPKT_SEQ_8197F(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ_8197F) << BIT_SHIFT_RXBEQPKT_SEQ_8197F) +#define BITS_RXBEQPKT_SEQ_8197F \ + (BIT_MASK_RXBEQPKT_SEQ_8197F << BIT_SHIFT_RXBEQPKT_SEQ_8197F) #define BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBEQPKT_SEQ_8197F)) -#define BIT_GET_RXBEQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8197F) & BIT_MASK_RXBEQPKT_SEQ_8197F) -#define BIT_SET_RXBEQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) | BIT_RXBEQPKT_SEQ_8197F(v)) - +#define BIT_GET_RXBEQPKT_SEQ_8197F(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8197F) & BIT_MASK_RXBEQPKT_SEQ_8197F) +#define BIT_SET_RXBEQPKT_SEQ_8197F(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) | BIT_RXBEQPKT_SEQ_8197F(v)) #define BIT_SHIFT_RXVIQPKT_SEQ_8197F 12 #define BIT_MASK_RXVIQPKT_SEQ_8197F 0xf -#define BIT_RXVIQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8197F) << BIT_SHIFT_RXVIQPKT_SEQ_8197F) -#define BITS_RXVIQPKT_SEQ_8197F (BIT_MASK_RXVIQPKT_SEQ_8197F << BIT_SHIFT_RXVIQPKT_SEQ_8197F) +#define BIT_RXVIQPKT_SEQ_8197F(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ_8197F) << BIT_SHIFT_RXVIQPKT_SEQ_8197F) +#define BITS_RXVIQPKT_SEQ_8197F \ + (BIT_MASK_RXVIQPKT_SEQ_8197F << BIT_SHIFT_RXVIQPKT_SEQ_8197F) #define BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVIQPKT_SEQ_8197F)) -#define BIT_GET_RXVIQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8197F) & BIT_MASK_RXVIQPKT_SEQ_8197F) -#define BIT_SET_RXVIQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) | BIT_RXVIQPKT_SEQ_8197F(v)) - +#define BIT_GET_RXVIQPKT_SEQ_8197F(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8197F) & BIT_MASK_RXVIQPKT_SEQ_8197F) +#define BIT_SET_RXVIQPKT_SEQ_8197F(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) | BIT_RXVIQPKT_SEQ_8197F(v)) #define BIT_SHIFT_RXVOQPKT_SEQ_8197F 8 #define BIT_MASK_RXVOQPKT_SEQ_8197F 0xf -#define BIT_RXVOQPKT_SEQ_8197F(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8197F) << BIT_SHIFT_RXVOQPKT_SEQ_8197F) -#define BITS_RXVOQPKT_SEQ_8197F (BIT_MASK_RXVOQPKT_SEQ_8197F << BIT_SHIFT_RXVOQPKT_SEQ_8197F) +#define BIT_RXVOQPKT_SEQ_8197F(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ_8197F) << BIT_SHIFT_RXVOQPKT_SEQ_8197F) +#define BITS_RXVOQPKT_SEQ_8197F \ + (BIT_MASK_RXVOQPKT_SEQ_8197F << BIT_SHIFT_RXVOQPKT_SEQ_8197F) #define BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVOQPKT_SEQ_8197F)) -#define BIT_GET_RXVOQPKT_SEQ_8197F(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8197F) & BIT_MASK_RXVOQPKT_SEQ_8197F) -#define BIT_SET_RXVOQPKT_SEQ_8197F(x, v) (BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) | BIT_RXVOQPKT_SEQ_8197F(v)) +#define BIT_GET_RXVOQPKT_SEQ_8197F(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8197F) & BIT_MASK_RXVOQPKT_SEQ_8197F) +#define BIT_SET_RXVOQPKT_SEQ_8197F(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) | BIT_RXVOQPKT_SEQ_8197F(v)) #define BIT_RXBKQPKT_ERR_8197F BIT(7) #define BIT_RXBEQPKT_ERR_8197F BIT(6) @@ -11228,31 +14721,41 @@ #define BIT_SHIFT_STATE_SEL_8197F 24 #define BIT_MASK_STATE_SEL_8197F 0x1f -#define BIT_STATE_SEL_8197F(x) (((x) & BIT_MASK_STATE_SEL_8197F) << BIT_SHIFT_STATE_SEL_8197F) -#define BITS_STATE_SEL_8197F (BIT_MASK_STATE_SEL_8197F << BIT_SHIFT_STATE_SEL_8197F) +#define BIT_STATE_SEL_8197F(x) \ + (((x) & BIT_MASK_STATE_SEL_8197F) << BIT_SHIFT_STATE_SEL_8197F) +#define BITS_STATE_SEL_8197F \ + (BIT_MASK_STATE_SEL_8197F << BIT_SHIFT_STATE_SEL_8197F) #define BIT_CLEAR_STATE_SEL_8197F(x) ((x) & (~BITS_STATE_SEL_8197F)) -#define BIT_GET_STATE_SEL_8197F(x) (((x) >> BIT_SHIFT_STATE_SEL_8197F) & BIT_MASK_STATE_SEL_8197F) -#define BIT_SET_STATE_SEL_8197F(x, v) (BIT_CLEAR_STATE_SEL_8197F(x) | BIT_STATE_SEL_8197F(v)) - +#define BIT_GET_STATE_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_STATE_SEL_8197F) & BIT_MASK_STATE_SEL_8197F) +#define BIT_SET_STATE_SEL_8197F(x, v) \ + (BIT_CLEAR_STATE_SEL_8197F(x) | BIT_STATE_SEL_8197F(v)) #define BIT_SHIFT_STATE_INFO_8197F 8 #define BIT_MASK_STATE_INFO_8197F 0xff -#define BIT_STATE_INFO_8197F(x) (((x) & BIT_MASK_STATE_INFO_8197F) << BIT_SHIFT_STATE_INFO_8197F) -#define BITS_STATE_INFO_8197F (BIT_MASK_STATE_INFO_8197F << BIT_SHIFT_STATE_INFO_8197F) +#define BIT_STATE_INFO_8197F(x) \ + (((x) & BIT_MASK_STATE_INFO_8197F) << BIT_SHIFT_STATE_INFO_8197F) +#define BITS_STATE_INFO_8197F \ + (BIT_MASK_STATE_INFO_8197F << BIT_SHIFT_STATE_INFO_8197F) #define BIT_CLEAR_STATE_INFO_8197F(x) ((x) & (~BITS_STATE_INFO_8197F)) -#define BIT_GET_STATE_INFO_8197F(x) (((x) >> BIT_SHIFT_STATE_INFO_8197F) & BIT_MASK_STATE_INFO_8197F) -#define BIT_SET_STATE_INFO_8197F(x, v) (BIT_CLEAR_STATE_INFO_8197F(x) | BIT_STATE_INFO_8197F(v)) +#define BIT_GET_STATE_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_STATE_INFO_8197F) & BIT_MASK_STATE_INFO_8197F) +#define BIT_SET_STATE_INFO_8197F(x, v) \ + (BIT_CLEAR_STATE_INFO_8197F(x) | BIT_STATE_INFO_8197F(v)) #define BIT_UPD_NXT_STATE_8197F BIT(7) #define BIT_SHIFT_CUR_STATE_8197F 0 #define BIT_MASK_CUR_STATE_8197F 0x7f -#define BIT_CUR_STATE_8197F(x) (((x) & BIT_MASK_CUR_STATE_8197F) << BIT_SHIFT_CUR_STATE_8197F) -#define BITS_CUR_STATE_8197F (BIT_MASK_CUR_STATE_8197F << BIT_SHIFT_CUR_STATE_8197F) +#define BIT_CUR_STATE_8197F(x) \ + (((x) & BIT_MASK_CUR_STATE_8197F) << BIT_SHIFT_CUR_STATE_8197F) +#define BITS_CUR_STATE_8197F \ + (BIT_MASK_CUR_STATE_8197F << BIT_SHIFT_CUR_STATE_8197F) #define BIT_CLEAR_CUR_STATE_8197F(x) ((x) & (~BITS_CUR_STATE_8197F)) -#define BIT_GET_CUR_STATE_8197F(x) (((x) >> BIT_SHIFT_CUR_STATE_8197F) & BIT_MASK_CUR_STATE_8197F) -#define BIT_SET_CUR_STATE_8197F(x, v) (BIT_CLEAR_CUR_STATE_8197F(x) | BIT_CUR_STATE_8197F(v)) - +#define BIT_GET_CUR_STATE_8197F(x) \ + (((x) >> BIT_SHIFT_CUR_STATE_8197F) & BIT_MASK_CUR_STATE_8197F) +#define BIT_SET_CUR_STATE_8197F(x, v) \ + (BIT_CLEAR_CUR_STATE_8197F(x) | BIT_CUR_STATE_8197F(v)) /* 2 REG_ERROR_MON_8197F */ #define BIT_MACRX_ERR_1_8197F BIT(17) @@ -11267,23 +14770,36 @@ #define BIT_SHIFT_INFO_INDEX_OFFSET_8197F 16 #define BIT_MASK_INFO_INDEX_OFFSET_8197F 0x1fff -#define BIT_INFO_INDEX_OFFSET_8197F(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8197F) << BIT_SHIFT_INFO_INDEX_OFFSET_8197F) -#define BITS_INFO_INDEX_OFFSET_8197F (BIT_MASK_INFO_INDEX_OFFSET_8197F << BIT_SHIFT_INFO_INDEX_OFFSET_8197F) -#define BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) ((x) & (~BITS_INFO_INDEX_OFFSET_8197F)) -#define BIT_GET_INFO_INDEX_OFFSET_8197F(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8197F) & BIT_MASK_INFO_INDEX_OFFSET_8197F) -#define BIT_SET_INFO_INDEX_OFFSET_8197F(x, v) (BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) | BIT_INFO_INDEX_OFFSET_8197F(v)) +#define BIT_INFO_INDEX_OFFSET_8197F(x) \ + (((x) & BIT_MASK_INFO_INDEX_OFFSET_8197F) \ + << BIT_SHIFT_INFO_INDEX_OFFSET_8197F) +#define BITS_INFO_INDEX_OFFSET_8197F \ + (BIT_MASK_INFO_INDEX_OFFSET_8197F << BIT_SHIFT_INFO_INDEX_OFFSET_8197F) +#define BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) \ + ((x) & (~BITS_INFO_INDEX_OFFSET_8197F)) +#define BIT_GET_INFO_INDEX_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8197F) & \ + BIT_MASK_INFO_INDEX_OFFSET_8197F) +#define BIT_SET_INFO_INDEX_OFFSET_8197F(x, v) \ + (BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) | BIT_INFO_INDEX_OFFSET_8197F(v)) #define BIT_DIS_INFOSRCH_8197F BIT(14) #define BIT_DISABLE_B0_8197F BIT(13) #define BIT_SHIFT_INFO_ADDR_OFFSET_8197F 0 #define BIT_MASK_INFO_ADDR_OFFSET_8197F 0x1fff -#define BIT_INFO_ADDR_OFFSET_8197F(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8197F) << BIT_SHIFT_INFO_ADDR_OFFSET_8197F) -#define BITS_INFO_ADDR_OFFSET_8197F (BIT_MASK_INFO_ADDR_OFFSET_8197F << BIT_SHIFT_INFO_ADDR_OFFSET_8197F) -#define BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) ((x) & (~BITS_INFO_ADDR_OFFSET_8197F)) -#define BIT_GET_INFO_ADDR_OFFSET_8197F(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8197F) & BIT_MASK_INFO_ADDR_OFFSET_8197F) -#define BIT_SET_INFO_ADDR_OFFSET_8197F(x, v) (BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) | BIT_INFO_ADDR_OFFSET_8197F(v)) - +#define BIT_INFO_ADDR_OFFSET_8197F(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET_8197F) \ + << BIT_SHIFT_INFO_ADDR_OFFSET_8197F) +#define BITS_INFO_ADDR_OFFSET_8197F \ + (BIT_MASK_INFO_ADDR_OFFSET_8197F << BIT_SHIFT_INFO_ADDR_OFFSET_8197F) +#define BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) \ + ((x) & (~BITS_INFO_ADDR_OFFSET_8197F)) +#define BIT_GET_INFO_ADDR_OFFSET_8197F(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8197F) & \ + BIT_MASK_INFO_ADDR_OFFSET_8197F) +#define BIT_SET_INFO_ADDR_OFFSET_8197F(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) | BIT_INFO_ADDR_OFFSET_8197F(v)) /* 2 REG_BT_COEX_TABLE_8197F (BT-COEXISTENCE CONTROL REGISTER) */ #define BIT_PRI_MASK_RX_RESP_8197F BIT(126) @@ -11292,20 +14808,27 @@ #define BIT_SHIFT_PRI_MASK_TXAC_8197F (117 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_TXAC_8197F 0x7f -#define BIT_PRI_MASK_TXAC_8197F(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8197F) << BIT_SHIFT_PRI_MASK_TXAC_8197F) -#define BITS_PRI_MASK_TXAC_8197F (BIT_MASK_PRI_MASK_TXAC_8197F << BIT_SHIFT_PRI_MASK_TXAC_8197F) +#define BIT_PRI_MASK_TXAC_8197F(x) \ + (((x) & BIT_MASK_PRI_MASK_TXAC_8197F) << BIT_SHIFT_PRI_MASK_TXAC_8197F) +#define BITS_PRI_MASK_TXAC_8197F \ + (BIT_MASK_PRI_MASK_TXAC_8197F << BIT_SHIFT_PRI_MASK_TXAC_8197F) #define BIT_CLEAR_PRI_MASK_TXAC_8197F(x) ((x) & (~BITS_PRI_MASK_TXAC_8197F)) -#define BIT_GET_PRI_MASK_TXAC_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8197F) & BIT_MASK_PRI_MASK_TXAC_8197F) -#define BIT_SET_PRI_MASK_TXAC_8197F(x, v) (BIT_CLEAR_PRI_MASK_TXAC_8197F(x) | BIT_PRI_MASK_TXAC_8197F(v)) - +#define BIT_GET_PRI_MASK_TXAC_8197F(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8197F) & BIT_MASK_PRI_MASK_TXAC_8197F) +#define BIT_SET_PRI_MASK_TXAC_8197F(x, v) \ + (BIT_CLEAR_PRI_MASK_TXAC_8197F(x) | BIT_PRI_MASK_TXAC_8197F(v)) #define BIT_SHIFT_PRI_MASK_NAV_8197F (109 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_NAV_8197F 0xff -#define BIT_PRI_MASK_NAV_8197F(x) (((x) & BIT_MASK_PRI_MASK_NAV_8197F) << BIT_SHIFT_PRI_MASK_NAV_8197F) -#define BITS_PRI_MASK_NAV_8197F (BIT_MASK_PRI_MASK_NAV_8197F << BIT_SHIFT_PRI_MASK_NAV_8197F) +#define BIT_PRI_MASK_NAV_8197F(x) \ + (((x) & BIT_MASK_PRI_MASK_NAV_8197F) << BIT_SHIFT_PRI_MASK_NAV_8197F) +#define BITS_PRI_MASK_NAV_8197F \ + (BIT_MASK_PRI_MASK_NAV_8197F << BIT_SHIFT_PRI_MASK_NAV_8197F) #define BIT_CLEAR_PRI_MASK_NAV_8197F(x) ((x) & (~BITS_PRI_MASK_NAV_8197F)) -#define BIT_GET_PRI_MASK_NAV_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8197F) & BIT_MASK_PRI_MASK_NAV_8197F) -#define BIT_SET_PRI_MASK_NAV_8197F(x, v) (BIT_CLEAR_PRI_MASK_NAV_8197F(x) | BIT_PRI_MASK_NAV_8197F(v)) +#define BIT_GET_PRI_MASK_NAV_8197F(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NAV_8197F) & BIT_MASK_PRI_MASK_NAV_8197F) +#define BIT_SET_PRI_MASK_NAV_8197F(x, v) \ + (BIT_CLEAR_PRI_MASK_NAV_8197F(x) | BIT_PRI_MASK_NAV_8197F(v)) #define BIT_PRI_MASK_CCK_8197F BIT(108) #define BIT_PRI_MASK_OFDM_8197F BIT(107) @@ -11313,82 +14836,107 @@ #define BIT_SHIFT_PRI_MASK_NUM_8197F (102 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_NUM_8197F 0xf -#define BIT_PRI_MASK_NUM_8197F(x) (((x) & BIT_MASK_PRI_MASK_NUM_8197F) << BIT_SHIFT_PRI_MASK_NUM_8197F) -#define BITS_PRI_MASK_NUM_8197F (BIT_MASK_PRI_MASK_NUM_8197F << BIT_SHIFT_PRI_MASK_NUM_8197F) +#define BIT_PRI_MASK_NUM_8197F(x) \ + (((x) & BIT_MASK_PRI_MASK_NUM_8197F) << BIT_SHIFT_PRI_MASK_NUM_8197F) +#define BITS_PRI_MASK_NUM_8197F \ + (BIT_MASK_PRI_MASK_NUM_8197F << BIT_SHIFT_PRI_MASK_NUM_8197F) #define BIT_CLEAR_PRI_MASK_NUM_8197F(x) ((x) & (~BITS_PRI_MASK_NUM_8197F)) -#define BIT_GET_PRI_MASK_NUM_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8197F) & BIT_MASK_PRI_MASK_NUM_8197F) -#define BIT_SET_PRI_MASK_NUM_8197F(x, v) (BIT_CLEAR_PRI_MASK_NUM_8197F(x) | BIT_PRI_MASK_NUM_8197F(v)) - +#define BIT_GET_PRI_MASK_NUM_8197F(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NUM_8197F) & BIT_MASK_PRI_MASK_NUM_8197F) +#define BIT_SET_PRI_MASK_NUM_8197F(x, v) \ + (BIT_CLEAR_PRI_MASK_NUM_8197F(x) | BIT_PRI_MASK_NUM_8197F(v)) #define BIT_SHIFT_PRI_MASK_TYPE_8197F (98 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_TYPE_8197F 0xf -#define BIT_PRI_MASK_TYPE_8197F(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8197F) << BIT_SHIFT_PRI_MASK_TYPE_8197F) -#define BITS_PRI_MASK_TYPE_8197F (BIT_MASK_PRI_MASK_TYPE_8197F << BIT_SHIFT_PRI_MASK_TYPE_8197F) +#define BIT_PRI_MASK_TYPE_8197F(x) \ + (((x) & BIT_MASK_PRI_MASK_TYPE_8197F) << BIT_SHIFT_PRI_MASK_TYPE_8197F) +#define BITS_PRI_MASK_TYPE_8197F \ + (BIT_MASK_PRI_MASK_TYPE_8197F << BIT_SHIFT_PRI_MASK_TYPE_8197F) #define BIT_CLEAR_PRI_MASK_TYPE_8197F(x) ((x) & (~BITS_PRI_MASK_TYPE_8197F)) -#define BIT_GET_PRI_MASK_TYPE_8197F(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8197F) & BIT_MASK_PRI_MASK_TYPE_8197F) -#define BIT_SET_PRI_MASK_TYPE_8197F(x, v) (BIT_CLEAR_PRI_MASK_TYPE_8197F(x) | BIT_PRI_MASK_TYPE_8197F(v)) +#define BIT_GET_PRI_MASK_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8197F) & BIT_MASK_PRI_MASK_TYPE_8197F) +#define BIT_SET_PRI_MASK_TYPE_8197F(x, v) \ + (BIT_CLEAR_PRI_MASK_TYPE_8197F(x) | BIT_PRI_MASK_TYPE_8197F(v)) #define BIT_OOB_8197F BIT(97) #define BIT_ANT_SEL_8197F BIT(96) #define BIT_SHIFT_BREAK_TABLE_2_8197F (80 & CPU_OPT_WIDTH) #define BIT_MASK_BREAK_TABLE_2_8197F 0xffff -#define BIT_BREAK_TABLE_2_8197F(x) (((x) & BIT_MASK_BREAK_TABLE_2_8197F) << BIT_SHIFT_BREAK_TABLE_2_8197F) -#define BITS_BREAK_TABLE_2_8197F (BIT_MASK_BREAK_TABLE_2_8197F << BIT_SHIFT_BREAK_TABLE_2_8197F) +#define BIT_BREAK_TABLE_2_8197F(x) \ + (((x) & BIT_MASK_BREAK_TABLE_2_8197F) << BIT_SHIFT_BREAK_TABLE_2_8197F) +#define BITS_BREAK_TABLE_2_8197F \ + (BIT_MASK_BREAK_TABLE_2_8197F << BIT_SHIFT_BREAK_TABLE_2_8197F) #define BIT_CLEAR_BREAK_TABLE_2_8197F(x) ((x) & (~BITS_BREAK_TABLE_2_8197F)) -#define BIT_GET_BREAK_TABLE_2_8197F(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8197F) & BIT_MASK_BREAK_TABLE_2_8197F) -#define BIT_SET_BREAK_TABLE_2_8197F(x, v) (BIT_CLEAR_BREAK_TABLE_2_8197F(x) | BIT_BREAK_TABLE_2_8197F(v)) - +#define BIT_GET_BREAK_TABLE_2_8197F(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_2_8197F) & BIT_MASK_BREAK_TABLE_2_8197F) +#define BIT_SET_BREAK_TABLE_2_8197F(x, v) \ + (BIT_CLEAR_BREAK_TABLE_2_8197F(x) | BIT_BREAK_TABLE_2_8197F(v)) #define BIT_SHIFT_BREAK_TABLE_1_8197F (64 & CPU_OPT_WIDTH) #define BIT_MASK_BREAK_TABLE_1_8197F 0xffff -#define BIT_BREAK_TABLE_1_8197F(x) (((x) & BIT_MASK_BREAK_TABLE_1_8197F) << BIT_SHIFT_BREAK_TABLE_1_8197F) -#define BITS_BREAK_TABLE_1_8197F (BIT_MASK_BREAK_TABLE_1_8197F << BIT_SHIFT_BREAK_TABLE_1_8197F) +#define BIT_BREAK_TABLE_1_8197F(x) \ + (((x) & BIT_MASK_BREAK_TABLE_1_8197F) << BIT_SHIFT_BREAK_TABLE_1_8197F) +#define BITS_BREAK_TABLE_1_8197F \ + (BIT_MASK_BREAK_TABLE_1_8197F << BIT_SHIFT_BREAK_TABLE_1_8197F) #define BIT_CLEAR_BREAK_TABLE_1_8197F(x) ((x) & (~BITS_BREAK_TABLE_1_8197F)) -#define BIT_GET_BREAK_TABLE_1_8197F(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8197F) & BIT_MASK_BREAK_TABLE_1_8197F) -#define BIT_SET_BREAK_TABLE_1_8197F(x, v) (BIT_CLEAR_BREAK_TABLE_1_8197F(x) | BIT_BREAK_TABLE_1_8197F(v)) - +#define BIT_GET_BREAK_TABLE_1_8197F(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_1_8197F) & BIT_MASK_BREAK_TABLE_1_8197F) +#define BIT_SET_BREAK_TABLE_1_8197F(x, v) \ + (BIT_CLEAR_BREAK_TABLE_1_8197F(x) | BIT_BREAK_TABLE_1_8197F(v)) #define BIT_SHIFT_COEX_TABLE_2_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_COEX_TABLE_2_8197F 0xffffffffL -#define BIT_COEX_TABLE_2_8197F(x) (((x) & BIT_MASK_COEX_TABLE_2_8197F) << BIT_SHIFT_COEX_TABLE_2_8197F) -#define BITS_COEX_TABLE_2_8197F (BIT_MASK_COEX_TABLE_2_8197F << BIT_SHIFT_COEX_TABLE_2_8197F) +#define BIT_COEX_TABLE_2_8197F(x) \ + (((x) & BIT_MASK_COEX_TABLE_2_8197F) << BIT_SHIFT_COEX_TABLE_2_8197F) +#define BITS_COEX_TABLE_2_8197F \ + (BIT_MASK_COEX_TABLE_2_8197F << BIT_SHIFT_COEX_TABLE_2_8197F) #define BIT_CLEAR_COEX_TABLE_2_8197F(x) ((x) & (~BITS_COEX_TABLE_2_8197F)) -#define BIT_GET_COEX_TABLE_2_8197F(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8197F) & BIT_MASK_COEX_TABLE_2_8197F) -#define BIT_SET_COEX_TABLE_2_8197F(x, v) (BIT_CLEAR_COEX_TABLE_2_8197F(x) | BIT_COEX_TABLE_2_8197F(v)) - +#define BIT_GET_COEX_TABLE_2_8197F(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_2_8197F) & BIT_MASK_COEX_TABLE_2_8197F) +#define BIT_SET_COEX_TABLE_2_8197F(x, v) \ + (BIT_CLEAR_COEX_TABLE_2_8197F(x) | BIT_COEX_TABLE_2_8197F(v)) #define BIT_SHIFT_COEX_TABLE_1_8197F 0 #define BIT_MASK_COEX_TABLE_1_8197F 0xffffffffL -#define BIT_COEX_TABLE_1_8197F(x) (((x) & BIT_MASK_COEX_TABLE_1_8197F) << BIT_SHIFT_COEX_TABLE_1_8197F) -#define BITS_COEX_TABLE_1_8197F (BIT_MASK_COEX_TABLE_1_8197F << BIT_SHIFT_COEX_TABLE_1_8197F) +#define BIT_COEX_TABLE_1_8197F(x) \ + (((x) & BIT_MASK_COEX_TABLE_1_8197F) << BIT_SHIFT_COEX_TABLE_1_8197F) +#define BITS_COEX_TABLE_1_8197F \ + (BIT_MASK_COEX_TABLE_1_8197F << BIT_SHIFT_COEX_TABLE_1_8197F) #define BIT_CLEAR_COEX_TABLE_1_8197F(x) ((x) & (~BITS_COEX_TABLE_1_8197F)) -#define BIT_GET_COEX_TABLE_1_8197F(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8197F) & BIT_MASK_COEX_TABLE_1_8197F) -#define BIT_SET_COEX_TABLE_1_8197F(x, v) (BIT_CLEAR_COEX_TABLE_1_8197F(x) | BIT_COEX_TABLE_1_8197F(v)) - +#define BIT_GET_COEX_TABLE_1_8197F(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1_8197F) & BIT_MASK_COEX_TABLE_1_8197F) +#define BIT_SET_COEX_TABLE_1_8197F(x, v) \ + (BIT_CLEAR_COEX_TABLE_1_8197F(x) | BIT_COEX_TABLE_1_8197F(v)) /* 2 REG_RXCMD_0_8197F */ #define BIT_RXCMD_EN_8197F BIT(31) #define BIT_SHIFT_RXCMD_INFO_8197F 0 #define BIT_MASK_RXCMD_INFO_8197F 0x7fffffffL -#define BIT_RXCMD_INFO_8197F(x) (((x) & BIT_MASK_RXCMD_INFO_8197F) << BIT_SHIFT_RXCMD_INFO_8197F) -#define BITS_RXCMD_INFO_8197F (BIT_MASK_RXCMD_INFO_8197F << BIT_SHIFT_RXCMD_INFO_8197F) +#define BIT_RXCMD_INFO_8197F(x) \ + (((x) & BIT_MASK_RXCMD_INFO_8197F) << BIT_SHIFT_RXCMD_INFO_8197F) +#define BITS_RXCMD_INFO_8197F \ + (BIT_MASK_RXCMD_INFO_8197F << BIT_SHIFT_RXCMD_INFO_8197F) #define BIT_CLEAR_RXCMD_INFO_8197F(x) ((x) & (~BITS_RXCMD_INFO_8197F)) -#define BIT_GET_RXCMD_INFO_8197F(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8197F) & BIT_MASK_RXCMD_INFO_8197F) -#define BIT_SET_RXCMD_INFO_8197F(x, v) (BIT_CLEAR_RXCMD_INFO_8197F(x) | BIT_RXCMD_INFO_8197F(v)) - +#define BIT_GET_RXCMD_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO_8197F) & BIT_MASK_RXCMD_INFO_8197F) +#define BIT_SET_RXCMD_INFO_8197F(x, v) \ + (BIT_CLEAR_RXCMD_INFO_8197F(x) | BIT_RXCMD_INFO_8197F(v)) /* 2 REG_RXCMD_1_8197F */ #define BIT_SHIFT_RXCMD_PRD_8197F 0 #define BIT_MASK_RXCMD_PRD_8197F 0xffff -#define BIT_RXCMD_PRD_8197F(x) (((x) & BIT_MASK_RXCMD_PRD_8197F) << BIT_SHIFT_RXCMD_PRD_8197F) -#define BITS_RXCMD_PRD_8197F (BIT_MASK_RXCMD_PRD_8197F << BIT_SHIFT_RXCMD_PRD_8197F) +#define BIT_RXCMD_PRD_8197F(x) \ + (((x) & BIT_MASK_RXCMD_PRD_8197F) << BIT_SHIFT_RXCMD_PRD_8197F) +#define BITS_RXCMD_PRD_8197F \ + (BIT_MASK_RXCMD_PRD_8197F << BIT_SHIFT_RXCMD_PRD_8197F) #define BIT_CLEAR_RXCMD_PRD_8197F(x) ((x) & (~BITS_RXCMD_PRD_8197F)) -#define BIT_GET_RXCMD_PRD_8197F(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8197F) & BIT_MASK_RXCMD_PRD_8197F) -#define BIT_SET_RXCMD_PRD_8197F(x, v) (BIT_CLEAR_RXCMD_PRD_8197F(x) | BIT_RXCMD_PRD_8197F(v)) - +#define BIT_GET_RXCMD_PRD_8197F(x) \ + (((x) >> BIT_SHIFT_RXCMD_PRD_8197F) & BIT_MASK_RXCMD_PRD_8197F) +#define BIT_SET_RXCMD_PRD_8197F(x, v) \ + (BIT_CLEAR_RXCMD_PRD_8197F(x) | BIT_RXCMD_PRD_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -11396,48 +14944,74 @@ #define BIT_SHIFT_WMAC_RESP_MFB_8197F 25 #define BIT_MASK_WMAC_RESP_MFB_8197F 0x7f -#define BIT_WMAC_RESP_MFB_8197F(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8197F) << BIT_SHIFT_WMAC_RESP_MFB_8197F) -#define BITS_WMAC_RESP_MFB_8197F (BIT_MASK_WMAC_RESP_MFB_8197F << BIT_SHIFT_WMAC_RESP_MFB_8197F) +#define BIT_WMAC_RESP_MFB_8197F(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB_8197F) << BIT_SHIFT_WMAC_RESP_MFB_8197F) +#define BITS_WMAC_RESP_MFB_8197F \ + (BIT_MASK_WMAC_RESP_MFB_8197F << BIT_SHIFT_WMAC_RESP_MFB_8197F) #define BIT_CLEAR_WMAC_RESP_MFB_8197F(x) ((x) & (~BITS_WMAC_RESP_MFB_8197F)) -#define BIT_GET_WMAC_RESP_MFB_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8197F) & BIT_MASK_WMAC_RESP_MFB_8197F) -#define BIT_SET_WMAC_RESP_MFB_8197F(x, v) (BIT_CLEAR_WMAC_RESP_MFB_8197F(x) | BIT_WMAC_RESP_MFB_8197F(v)) - +#define BIT_GET_WMAC_RESP_MFB_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8197F) & BIT_MASK_WMAC_RESP_MFB_8197F) +#define BIT_SET_WMAC_RESP_MFB_8197F(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB_8197F(x) | BIT_WMAC_RESP_MFB_8197F(v)) #define BIT_SHIFT_WMAC_ANTINF_SEL_8197F 23 #define BIT_MASK_WMAC_ANTINF_SEL_8197F 0x3 -#define BIT_WMAC_ANTINF_SEL_8197F(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8197F) << BIT_SHIFT_WMAC_ANTINF_SEL_8197F) -#define BITS_WMAC_ANTINF_SEL_8197F (BIT_MASK_WMAC_ANTINF_SEL_8197F << BIT_SHIFT_WMAC_ANTINF_SEL_8197F) +#define BIT_WMAC_ANTINF_SEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL_8197F) \ + << BIT_SHIFT_WMAC_ANTINF_SEL_8197F) +#define BITS_WMAC_ANTINF_SEL_8197F \ + (BIT_MASK_WMAC_ANTINF_SEL_8197F << BIT_SHIFT_WMAC_ANTINF_SEL_8197F) #define BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8197F)) -#define BIT_GET_WMAC_ANTINF_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8197F) & BIT_MASK_WMAC_ANTINF_SEL_8197F) -#define BIT_SET_WMAC_ANTINF_SEL_8197F(x, v) (BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) | BIT_WMAC_ANTINF_SEL_8197F(v)) - +#define BIT_GET_WMAC_ANTINF_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8197F) & \ + BIT_MASK_WMAC_ANTINF_SEL_8197F) +#define BIT_SET_WMAC_ANTINF_SEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) | BIT_WMAC_ANTINF_SEL_8197F(v)) #define BIT_SHIFT_WMAC_ANTSEL_SEL_8197F 21 #define BIT_MASK_WMAC_ANTSEL_SEL_8197F 0x3 -#define BIT_WMAC_ANTSEL_SEL_8197F(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8197F) << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) -#define BITS_WMAC_ANTSEL_SEL_8197F (BIT_MASK_WMAC_ANTSEL_SEL_8197F << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) +#define BIT_WMAC_ANTSEL_SEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8197F) \ + << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) +#define BITS_WMAC_ANTSEL_SEL_8197F \ + (BIT_MASK_WMAC_ANTSEL_SEL_8197F << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) #define BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8197F)) -#define BIT_GET_WMAC_ANTSEL_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) & BIT_MASK_WMAC_ANTSEL_SEL_8197F) -#define BIT_SET_WMAC_ANTSEL_SEL_8197F(x, v) (BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) | BIT_WMAC_ANTSEL_SEL_8197F(v)) - +#define BIT_GET_WMAC_ANTSEL_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) & \ + BIT_MASK_WMAC_ANTSEL_SEL_8197F) +#define BIT_SET_WMAC_ANTSEL_SEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) | BIT_WMAC_ANTSEL_SEL_8197F(v)) #define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F 18 #define BIT_MASK_R_WMAC_RESP_TXPOWER_8197F 0x7 -#define BIT_R_WMAC_RESP_TXPOWER_8197F(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8197F) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) -#define BITS_R_WMAC_RESP_TXPOWER_8197F (BIT_MASK_R_WMAC_RESP_TXPOWER_8197F << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) -#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8197F)) -#define BIT_GET_R_WMAC_RESP_TXPOWER_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) & BIT_MASK_R_WMAC_RESP_TXPOWER_8197F) -#define BIT_SET_R_WMAC_RESP_TXPOWER_8197F(x, v) (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) | BIT_R_WMAC_RESP_TXPOWER_8197F(v)) - +#define BIT_R_WMAC_RESP_TXPOWER_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8197F) \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) +#define BITS_R_WMAC_RESP_TXPOWER_8197F \ + (BIT_MASK_R_WMAC_RESP_TXPOWER_8197F \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) +#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) \ + ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8197F)) +#define BIT_GET_R_WMAC_RESP_TXPOWER_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) & \ + BIT_MASK_R_WMAC_RESP_TXPOWER_8197F) +#define BIT_SET_R_WMAC_RESP_TXPOWER_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) | \ + BIT_R_WMAC_RESP_TXPOWER_8197F(v)) #define BIT_SHIFT_WMAC_RESP_TXANT_8197F 0 #define BIT_MASK_WMAC_RESP_TXANT_8197F 0x3ffff -#define BIT_WMAC_RESP_TXANT_8197F(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8197F) << BIT_SHIFT_WMAC_RESP_TXANT_8197F) -#define BITS_WMAC_RESP_TXANT_8197F (BIT_MASK_WMAC_RESP_TXANT_8197F << BIT_SHIFT_WMAC_RESP_TXANT_8197F) +#define BIT_WMAC_RESP_TXANT_8197F(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_8197F) \ + << BIT_SHIFT_WMAC_RESP_TXANT_8197F) +#define BITS_WMAC_RESP_TXANT_8197F \ + (BIT_MASK_WMAC_RESP_TXANT_8197F << BIT_SHIFT_WMAC_RESP_TXANT_8197F) #define BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) ((x) & (~BITS_WMAC_RESP_TXANT_8197F)) -#define BIT_GET_WMAC_RESP_TXANT_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8197F) & BIT_MASK_WMAC_RESP_TXANT_8197F) -#define BIT_SET_WMAC_RESP_TXANT_8197F(x, v) (BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) | BIT_WMAC_RESP_TXANT_8197F(v)) - +#define BIT_GET_WMAC_RESP_TXANT_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8197F) & \ + BIT_MASK_WMAC_RESP_TXANT_8197F) +#define BIT_SET_WMAC_RESP_TXANT_8197F(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) | BIT_WMAC_RESP_TXANT_8197F(v)) /* 2 REG_BBPSF_CTRL_8197F */ #define BIT_CTL_IDLE_CLR_CSI_RPT_8197F BIT(31) @@ -11445,20 +15019,30 @@ #define BIT_SHIFT_WMAC_CSI_RATE_8197F 24 #define BIT_MASK_WMAC_CSI_RATE_8197F 0x3f -#define BIT_WMAC_CSI_RATE_8197F(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8197F) << BIT_SHIFT_WMAC_CSI_RATE_8197F) -#define BITS_WMAC_CSI_RATE_8197F (BIT_MASK_WMAC_CSI_RATE_8197F << BIT_SHIFT_WMAC_CSI_RATE_8197F) +#define BIT_WMAC_CSI_RATE_8197F(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE_8197F) << BIT_SHIFT_WMAC_CSI_RATE_8197F) +#define BITS_WMAC_CSI_RATE_8197F \ + (BIT_MASK_WMAC_CSI_RATE_8197F << BIT_SHIFT_WMAC_CSI_RATE_8197F) #define BIT_CLEAR_WMAC_CSI_RATE_8197F(x) ((x) & (~BITS_WMAC_CSI_RATE_8197F)) -#define BIT_GET_WMAC_CSI_RATE_8197F(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8197F) & BIT_MASK_WMAC_CSI_RATE_8197F) -#define BIT_SET_WMAC_CSI_RATE_8197F(x, v) (BIT_CLEAR_WMAC_CSI_RATE_8197F(x) | BIT_WMAC_CSI_RATE_8197F(v)) - +#define BIT_GET_WMAC_CSI_RATE_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8197F) & BIT_MASK_WMAC_CSI_RATE_8197F) +#define BIT_SET_WMAC_CSI_RATE_8197F(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE_8197F(x) | BIT_WMAC_CSI_RATE_8197F(v)) #define BIT_SHIFT_WMAC_RESP_TXRATE_8197F 16 #define BIT_MASK_WMAC_RESP_TXRATE_8197F 0xff -#define BIT_WMAC_RESP_TXRATE_8197F(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8197F) << BIT_SHIFT_WMAC_RESP_TXRATE_8197F) -#define BITS_WMAC_RESP_TXRATE_8197F (BIT_MASK_WMAC_RESP_TXRATE_8197F << BIT_SHIFT_WMAC_RESP_TXRATE_8197F) -#define BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) ((x) & (~BITS_WMAC_RESP_TXRATE_8197F)) -#define BIT_GET_WMAC_RESP_TXRATE_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8197F) & BIT_MASK_WMAC_RESP_TXRATE_8197F) -#define BIT_SET_WMAC_RESP_TXRATE_8197F(x, v) (BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) | BIT_WMAC_RESP_TXRATE_8197F(v)) +#define BIT_WMAC_RESP_TXRATE_8197F(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE_8197F) \ + << BIT_SHIFT_WMAC_RESP_TXRATE_8197F) +#define BITS_WMAC_RESP_TXRATE_8197F \ + (BIT_MASK_WMAC_RESP_TXRATE_8197F << BIT_SHIFT_WMAC_RESP_TXRATE_8197F) +#define BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) \ + ((x) & (~BITS_WMAC_RESP_TXRATE_8197F)) +#define BIT_GET_WMAC_RESP_TXRATE_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8197F) & \ + BIT_MASK_WMAC_RESP_TXRATE_8197F) +#define BIT_SET_WMAC_RESP_TXRATE_8197F(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) | BIT_WMAC_RESP_TXRATE_8197F(v)) #define BIT_BBPSF_MPDUCHKEN_8197F BIT(5) #define BIT_BBPSF_MHCHKEN_8197F BIT(4) @@ -11466,75 +15050,112 @@ #define BIT_SHIFT_BBPSF_ERRTHR_8197F 0 #define BIT_MASK_BBPSF_ERRTHR_8197F 0x7 -#define BIT_BBPSF_ERRTHR_8197F(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8197F) << BIT_SHIFT_BBPSF_ERRTHR_8197F) -#define BITS_BBPSF_ERRTHR_8197F (BIT_MASK_BBPSF_ERRTHR_8197F << BIT_SHIFT_BBPSF_ERRTHR_8197F) +#define BIT_BBPSF_ERRTHR_8197F(x) \ + (((x) & BIT_MASK_BBPSF_ERRTHR_8197F) << BIT_SHIFT_BBPSF_ERRTHR_8197F) +#define BITS_BBPSF_ERRTHR_8197F \ + (BIT_MASK_BBPSF_ERRTHR_8197F << BIT_SHIFT_BBPSF_ERRTHR_8197F) #define BIT_CLEAR_BBPSF_ERRTHR_8197F(x) ((x) & (~BITS_BBPSF_ERRTHR_8197F)) -#define BIT_GET_BBPSF_ERRTHR_8197F(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8197F) & BIT_MASK_BBPSF_ERRTHR_8197F) -#define BIT_SET_BBPSF_ERRTHR_8197F(x, v) (BIT_CLEAR_BBPSF_ERRTHR_8197F(x) | BIT_BBPSF_ERRTHR_8197F(v)) - +#define BIT_GET_BBPSF_ERRTHR_8197F(x) \ + (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8197F) & BIT_MASK_BBPSF_ERRTHR_8197F) +#define BIT_SET_BBPSF_ERRTHR_8197F(x, v) \ + (BIT_CLEAR_BBPSF_ERRTHR_8197F(x) | BIT_BBPSF_ERRTHR_8197F(v)) /* 2 REG_NOT_VALID_8197F */ /* 2 REG_P2P_RX_BCN_NOA_8197F (P2P RX BEACON NOA REGISTER) */ #define BIT_NOA_PARSER_EN_8197F BIT(15) -#define BIT_SHIFT_BSSID_SEL_8197F 12 -#define BIT_MASK_BSSID_SEL_8197F 0x7 -#define BIT_BSSID_SEL_8197F(x) (((x) & BIT_MASK_BSSID_SEL_8197F) << BIT_SHIFT_BSSID_SEL_8197F) -#define BITS_BSSID_SEL_8197F (BIT_MASK_BSSID_SEL_8197F << BIT_SHIFT_BSSID_SEL_8197F) -#define BIT_CLEAR_BSSID_SEL_8197F(x) ((x) & (~BITS_BSSID_SEL_8197F)) -#define BIT_GET_BSSID_SEL_8197F(x) (((x) >> BIT_SHIFT_BSSID_SEL_8197F) & BIT_MASK_BSSID_SEL_8197F) -#define BIT_SET_BSSID_SEL_8197F(x, v) (BIT_CLEAR_BSSID_SEL_8197F(x) | BIT_BSSID_SEL_8197F(v)) - +#define BIT_SHIFT_BSSID_SEL_V1_8197F 12 +#define BIT_MASK_BSSID_SEL_V1_8197F 0x7 +#define BIT_BSSID_SEL_V1_8197F(x) \ + (((x) & BIT_MASK_BSSID_SEL_V1_8197F) << BIT_SHIFT_BSSID_SEL_V1_8197F) +#define BITS_BSSID_SEL_V1_8197F \ + (BIT_MASK_BSSID_SEL_V1_8197F << BIT_SHIFT_BSSID_SEL_V1_8197F) +#define BIT_CLEAR_BSSID_SEL_V1_8197F(x) ((x) & (~BITS_BSSID_SEL_V1_8197F)) +#define BIT_GET_BSSID_SEL_V1_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID_SEL_V1_8197F) & BIT_MASK_BSSID_SEL_V1_8197F) +#define BIT_SET_BSSID_SEL_V1_8197F(x, v) \ + (BIT_CLEAR_BSSID_SEL_V1_8197F(x) | BIT_BSSID_SEL_V1_8197F(v)) #define BIT_SHIFT_P2P_OUI_TYPE_8197F 0 #define BIT_MASK_P2P_OUI_TYPE_8197F 0xff -#define BIT_P2P_OUI_TYPE_8197F(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8197F) << BIT_SHIFT_P2P_OUI_TYPE_8197F) -#define BITS_P2P_OUI_TYPE_8197F (BIT_MASK_P2P_OUI_TYPE_8197F << BIT_SHIFT_P2P_OUI_TYPE_8197F) +#define BIT_P2P_OUI_TYPE_8197F(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE_8197F) << BIT_SHIFT_P2P_OUI_TYPE_8197F) +#define BITS_P2P_OUI_TYPE_8197F \ + (BIT_MASK_P2P_OUI_TYPE_8197F << BIT_SHIFT_P2P_OUI_TYPE_8197F) #define BIT_CLEAR_P2P_OUI_TYPE_8197F(x) ((x) & (~BITS_P2P_OUI_TYPE_8197F)) -#define BIT_GET_P2P_OUI_TYPE_8197F(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8197F) & BIT_MASK_P2P_OUI_TYPE_8197F) -#define BIT_SET_P2P_OUI_TYPE_8197F(x, v) (BIT_CLEAR_P2P_OUI_TYPE_8197F(x) | BIT_P2P_OUI_TYPE_8197F(v)) - +#define BIT_GET_P2P_OUI_TYPE_8197F(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8197F) & BIT_MASK_P2P_OUI_TYPE_8197F) +#define BIT_SET_P2P_OUI_TYPE_8197F(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE_8197F(x) | BIT_P2P_OUI_TYPE_8197F(v)) /* 2 REG_ASSOCIATED_BFMER0_INFO_8197F (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F (48 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_TXCSI_AID0_8197F 0x1ff -#define BIT_R_WMAC_TXCSI_AID0_8197F(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8197F) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) -#define BITS_R_WMAC_TXCSI_AID0_8197F (BIT_MASK_R_WMAC_TXCSI_AID0_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) -#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) ((x) & (~BITS_R_WMAC_TXCSI_AID0_8197F)) -#define BIT_GET_R_WMAC_TXCSI_AID0_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) & BIT_MASK_R_WMAC_TXCSI_AID0_8197F) -#define BIT_SET_R_WMAC_TXCSI_AID0_8197F(x, v) (BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) | BIT_R_WMAC_TXCSI_AID0_8197F(v)) - +#define BIT_R_WMAC_TXCSI_AID0_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8197F) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) +#define BITS_R_WMAC_TXCSI_AID0_8197F \ + (BIT_MASK_R_WMAC_TXCSI_AID0_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) +#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID0_8197F)) +#define BIT_GET_R_WMAC_TXCSI_AID0_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) & \ + BIT_MASK_R_WMAC_TXCSI_AID0_8197F) +#define BIT_SET_R_WMAC_TXCSI_AID0_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) | BIT_R_WMAC_TXCSI_AID0_8197F(v)) #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) -#define BITS_R_WMAC_SOUNDING_RXADD_R0_8197F (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) -#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8197F)) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F) -#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8197F(x, v) (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) | BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(v)) - +#define BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_8197F \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8197F)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(v)) /* 2 REG_ASSOCIATED_BFMER1_INFO_8197F (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F (48 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_TXCSI_AID1_8197F 0x1ff -#define BIT_R_WMAC_TXCSI_AID1_8197F(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8197F) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) -#define BITS_R_WMAC_TXCSI_AID1_8197F (BIT_MASK_R_WMAC_TXCSI_AID1_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) -#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) ((x) & (~BITS_R_WMAC_TXCSI_AID1_8197F)) -#define BIT_GET_R_WMAC_TXCSI_AID1_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) & BIT_MASK_R_WMAC_TXCSI_AID1_8197F) -#define BIT_SET_R_WMAC_TXCSI_AID1_8197F(x, v) (BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) | BIT_R_WMAC_TXCSI_AID1_8197F(v)) - +#define BIT_R_WMAC_TXCSI_AID1_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8197F) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) +#define BITS_R_WMAC_TXCSI_AID1_8197F \ + (BIT_MASK_R_WMAC_TXCSI_AID1_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) +#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID1_8197F)) +#define BIT_GET_R_WMAC_TXCSI_AID1_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) & \ + BIT_MASK_R_WMAC_TXCSI_AID1_8197F) +#define BIT_SET_R_WMAC_TXCSI_AID1_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) | BIT_R_WMAC_TXCSI_AID1_8197F(v)) #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) -#define BITS_R_WMAC_SOUNDING_RXADD_R1_8197F (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) -#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8197F)) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F) -#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8197F(x, v) (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) | BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(v)) - +#define BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_8197F \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8197F)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -11550,32 +15171,53 @@ #define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F 16 #define BIT_MASK_R_WMAC_BFINFO_20M_1_8197F 0xfff -#define BIT_R_WMAC_BFINFO_20M_1_8197F(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8197F) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) -#define BITS_R_WMAC_BFINFO_20M_1_8197F (BIT_MASK_R_WMAC_BFINFO_20M_1_8197F << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) -#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8197F)) -#define BIT_GET_R_WMAC_BFINFO_20M_1_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) & BIT_MASK_R_WMAC_BFINFO_20M_1_8197F) -#define BIT_SET_R_WMAC_BFINFO_20M_1_8197F(x, v) (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) | BIT_R_WMAC_BFINFO_20M_1_8197F(v)) - +#define BIT_R_WMAC_BFINFO_20M_1_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8197F) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) +#define BITS_R_WMAC_BFINFO_20M_1_8197F \ + (BIT_MASK_R_WMAC_BFINFO_20M_1_8197F \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8197F)) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) & \ + BIT_MASK_R_WMAC_BFINFO_20M_1_8197F) +#define BIT_SET_R_WMAC_BFINFO_20M_1_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) | \ + BIT_R_WMAC_BFINFO_20M_1_8197F(v)) #define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F 0 #define BIT_MASK_R_WMAC_BFINFO_20M_0_8197F 0xfff -#define BIT_R_WMAC_BFINFO_20M_0_8197F(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8197F) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) -#define BITS_R_WMAC_BFINFO_20M_0_8197F (BIT_MASK_R_WMAC_BFINFO_20M_0_8197F << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) -#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8197F)) -#define BIT_GET_R_WMAC_BFINFO_20M_0_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) & BIT_MASK_R_WMAC_BFINFO_20M_0_8197F) -#define BIT_SET_R_WMAC_BFINFO_20M_0_8197F(x, v) (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) | BIT_R_WMAC_BFINFO_20M_0_8197F(v)) - +#define BIT_R_WMAC_BFINFO_20M_0_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8197F) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) +#define BITS_R_WMAC_BFINFO_20M_0_8197F \ + (BIT_MASK_R_WMAC_BFINFO_20M_0_8197F \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8197F)) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) & \ + BIT_MASK_R_WMAC_BFINFO_20M_0_8197F) +#define BIT_SET_R_WMAC_BFINFO_20M_0_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) | \ + BIT_R_WMAC_BFINFO_20M_0_8197F(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW40_8197F (TX CSI REPORT PARAMETER_BW40 REGISTER) */ #define BIT_SHIFT_WMAC_RESP_ANTCD_8197F 0 #define BIT_MASK_WMAC_RESP_ANTCD_8197F 0xf -#define BIT_WMAC_RESP_ANTCD_8197F(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8197F) << BIT_SHIFT_WMAC_RESP_ANTCD_8197F) -#define BITS_WMAC_RESP_ANTCD_8197F (BIT_MASK_WMAC_RESP_ANTCD_8197F << BIT_SHIFT_WMAC_RESP_ANTCD_8197F) +#define BIT_WMAC_RESP_ANTCD_8197F(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTCD_8197F) \ + << BIT_SHIFT_WMAC_RESP_ANTCD_8197F) +#define BITS_WMAC_RESP_ANTCD_8197F \ + (BIT_MASK_WMAC_RESP_ANTCD_8197F << BIT_SHIFT_WMAC_RESP_ANTCD_8197F) #define BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8197F)) -#define BIT_GET_WMAC_RESP_ANTCD_8197F(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8197F) & BIT_MASK_WMAC_RESP_ANTCD_8197F) -#define BIT_SET_WMAC_RESP_ANTCD_8197F(x, v) (BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) | BIT_WMAC_RESP_ANTCD_8197F(v)) - +#define BIT_GET_WMAC_RESP_ANTCD_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8197F) & \ + BIT_MASK_WMAC_RESP_ANTCD_8197F) +#define BIT_SET_WMAC_RESP_ANTCD_8197F(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) | BIT_WMAC_RESP_ANTCD_8197F(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW80_8197F (TX CSI REPORT PARAMETER_BW80 REGISTER) */ @@ -11583,171 +15225,216 @@ #define BIT_SHIFT_DTIM_CNT2_8197F 24 #define BIT_MASK_DTIM_CNT2_8197F 0xff -#define BIT_DTIM_CNT2_8197F(x) (((x) & BIT_MASK_DTIM_CNT2_8197F) << BIT_SHIFT_DTIM_CNT2_8197F) -#define BITS_DTIM_CNT2_8197F (BIT_MASK_DTIM_CNT2_8197F << BIT_SHIFT_DTIM_CNT2_8197F) +#define BIT_DTIM_CNT2_8197F(x) \ + (((x) & BIT_MASK_DTIM_CNT2_8197F) << BIT_SHIFT_DTIM_CNT2_8197F) +#define BITS_DTIM_CNT2_8197F \ + (BIT_MASK_DTIM_CNT2_8197F << BIT_SHIFT_DTIM_CNT2_8197F) #define BIT_CLEAR_DTIM_CNT2_8197F(x) ((x) & (~BITS_DTIM_CNT2_8197F)) -#define BIT_GET_DTIM_CNT2_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8197F) & BIT_MASK_DTIM_CNT2_8197F) -#define BIT_SET_DTIM_CNT2_8197F(x, v) (BIT_CLEAR_DTIM_CNT2_8197F(x) | BIT_DTIM_CNT2_8197F(v)) - +#define BIT_GET_DTIM_CNT2_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT2_8197F) & BIT_MASK_DTIM_CNT2_8197F) +#define BIT_SET_DTIM_CNT2_8197F(x, v) \ + (BIT_CLEAR_DTIM_CNT2_8197F(x) | BIT_DTIM_CNT2_8197F(v)) #define BIT_SHIFT_DTIM_PERIOD2_8197F 16 #define BIT_MASK_DTIM_PERIOD2_8197F 0xff -#define BIT_DTIM_PERIOD2_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD2_8197F) << BIT_SHIFT_DTIM_PERIOD2_8197F) -#define BITS_DTIM_PERIOD2_8197F (BIT_MASK_DTIM_PERIOD2_8197F << BIT_SHIFT_DTIM_PERIOD2_8197F) +#define BIT_DTIM_PERIOD2_8197F(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2_8197F) << BIT_SHIFT_DTIM_PERIOD2_8197F) +#define BITS_DTIM_PERIOD2_8197F \ + (BIT_MASK_DTIM_PERIOD2_8197F << BIT_SHIFT_DTIM_PERIOD2_8197F) #define BIT_CLEAR_DTIM_PERIOD2_8197F(x) ((x) & (~BITS_DTIM_PERIOD2_8197F)) -#define BIT_GET_DTIM_PERIOD2_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8197F) & BIT_MASK_DTIM_PERIOD2_8197F) -#define BIT_SET_DTIM_PERIOD2_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD2_8197F(x) | BIT_DTIM_PERIOD2_8197F(v)) +#define BIT_GET_DTIM_PERIOD2_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2_8197F) & BIT_MASK_DTIM_PERIOD2_8197F) +#define BIT_SET_DTIM_PERIOD2_8197F(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2_8197F(x) | BIT_DTIM_PERIOD2_8197F(v)) #define BIT_DTIM2_8197F BIT(15) #define BIT_TIM2_8197F BIT(14) #define BIT_SHIFT_PS_AID_2_8197F 0 #define BIT_MASK_PS_AID_2_8197F 0x7ff -#define BIT_PS_AID_2_8197F(x) (((x) & BIT_MASK_PS_AID_2_8197F) << BIT_SHIFT_PS_AID_2_8197F) -#define BITS_PS_AID_2_8197F (BIT_MASK_PS_AID_2_8197F << BIT_SHIFT_PS_AID_2_8197F) +#define BIT_PS_AID_2_8197F(x) \ + (((x) & BIT_MASK_PS_AID_2_8197F) << BIT_SHIFT_PS_AID_2_8197F) +#define BITS_PS_AID_2_8197F \ + (BIT_MASK_PS_AID_2_8197F << BIT_SHIFT_PS_AID_2_8197F) #define BIT_CLEAR_PS_AID_2_8197F(x) ((x) & (~BITS_PS_AID_2_8197F)) -#define BIT_GET_PS_AID_2_8197F(x) (((x) >> BIT_SHIFT_PS_AID_2_8197F) & BIT_MASK_PS_AID_2_8197F) -#define BIT_SET_PS_AID_2_8197F(x, v) (BIT_CLEAR_PS_AID_2_8197F(x) | BIT_PS_AID_2_8197F(v)) - +#define BIT_GET_PS_AID_2_8197F(x) \ + (((x) >> BIT_SHIFT_PS_AID_2_8197F) & BIT_MASK_PS_AID_2_8197F) +#define BIT_SET_PS_AID_2_8197F(x, v) \ + (BIT_CLEAR_PS_AID_2_8197F(x) | BIT_PS_AID_2_8197F(v)) /* 2 REG_BCN_PSR_RPT3_8197F (BEACON PARSER REPORT REGISTER3) */ #define BIT_SHIFT_DTIM_CNT3_8197F 24 #define BIT_MASK_DTIM_CNT3_8197F 0xff -#define BIT_DTIM_CNT3_8197F(x) (((x) & BIT_MASK_DTIM_CNT3_8197F) << BIT_SHIFT_DTIM_CNT3_8197F) -#define BITS_DTIM_CNT3_8197F (BIT_MASK_DTIM_CNT3_8197F << BIT_SHIFT_DTIM_CNT3_8197F) +#define BIT_DTIM_CNT3_8197F(x) \ + (((x) & BIT_MASK_DTIM_CNT3_8197F) << BIT_SHIFT_DTIM_CNT3_8197F) +#define BITS_DTIM_CNT3_8197F \ + (BIT_MASK_DTIM_CNT3_8197F << BIT_SHIFT_DTIM_CNT3_8197F) #define BIT_CLEAR_DTIM_CNT3_8197F(x) ((x) & (~BITS_DTIM_CNT3_8197F)) -#define BIT_GET_DTIM_CNT3_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8197F) & BIT_MASK_DTIM_CNT3_8197F) -#define BIT_SET_DTIM_CNT3_8197F(x, v) (BIT_CLEAR_DTIM_CNT3_8197F(x) | BIT_DTIM_CNT3_8197F(v)) - +#define BIT_GET_DTIM_CNT3_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT3_8197F) & BIT_MASK_DTIM_CNT3_8197F) +#define BIT_SET_DTIM_CNT3_8197F(x, v) \ + (BIT_CLEAR_DTIM_CNT3_8197F(x) | BIT_DTIM_CNT3_8197F(v)) #define BIT_SHIFT_DTIM_PERIOD3_8197F 16 #define BIT_MASK_DTIM_PERIOD3_8197F 0xff -#define BIT_DTIM_PERIOD3_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD3_8197F) << BIT_SHIFT_DTIM_PERIOD3_8197F) -#define BITS_DTIM_PERIOD3_8197F (BIT_MASK_DTIM_PERIOD3_8197F << BIT_SHIFT_DTIM_PERIOD3_8197F) +#define BIT_DTIM_PERIOD3_8197F(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3_8197F) << BIT_SHIFT_DTIM_PERIOD3_8197F) +#define BITS_DTIM_PERIOD3_8197F \ + (BIT_MASK_DTIM_PERIOD3_8197F << BIT_SHIFT_DTIM_PERIOD3_8197F) #define BIT_CLEAR_DTIM_PERIOD3_8197F(x) ((x) & (~BITS_DTIM_PERIOD3_8197F)) -#define BIT_GET_DTIM_PERIOD3_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8197F) & BIT_MASK_DTIM_PERIOD3_8197F) -#define BIT_SET_DTIM_PERIOD3_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD3_8197F(x) | BIT_DTIM_PERIOD3_8197F(v)) +#define BIT_GET_DTIM_PERIOD3_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3_8197F) & BIT_MASK_DTIM_PERIOD3_8197F) +#define BIT_SET_DTIM_PERIOD3_8197F(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3_8197F(x) | BIT_DTIM_PERIOD3_8197F(v)) #define BIT_DTIM3_8197F BIT(15) #define BIT_TIM3_8197F BIT(14) #define BIT_SHIFT_PS_AID_3_8197F 0 #define BIT_MASK_PS_AID_3_8197F 0x7ff -#define BIT_PS_AID_3_8197F(x) (((x) & BIT_MASK_PS_AID_3_8197F) << BIT_SHIFT_PS_AID_3_8197F) -#define BITS_PS_AID_3_8197F (BIT_MASK_PS_AID_3_8197F << BIT_SHIFT_PS_AID_3_8197F) +#define BIT_PS_AID_3_8197F(x) \ + (((x) & BIT_MASK_PS_AID_3_8197F) << BIT_SHIFT_PS_AID_3_8197F) +#define BITS_PS_AID_3_8197F \ + (BIT_MASK_PS_AID_3_8197F << BIT_SHIFT_PS_AID_3_8197F) #define BIT_CLEAR_PS_AID_3_8197F(x) ((x) & (~BITS_PS_AID_3_8197F)) -#define BIT_GET_PS_AID_3_8197F(x) (((x) >> BIT_SHIFT_PS_AID_3_8197F) & BIT_MASK_PS_AID_3_8197F) -#define BIT_SET_PS_AID_3_8197F(x, v) (BIT_CLEAR_PS_AID_3_8197F(x) | BIT_PS_AID_3_8197F(v)) - +#define BIT_GET_PS_AID_3_8197F(x) \ + (((x) >> BIT_SHIFT_PS_AID_3_8197F) & BIT_MASK_PS_AID_3_8197F) +#define BIT_SET_PS_AID_3_8197F(x, v) \ + (BIT_CLEAR_PS_AID_3_8197F(x) | BIT_PS_AID_3_8197F(v)) /* 2 REG_BCN_PSR_RPT4_8197F (BEACON PARSER REPORT REGISTER4) */ #define BIT_SHIFT_DTIM_CNT4_8197F 24 #define BIT_MASK_DTIM_CNT4_8197F 0xff -#define BIT_DTIM_CNT4_8197F(x) (((x) & BIT_MASK_DTIM_CNT4_8197F) << BIT_SHIFT_DTIM_CNT4_8197F) -#define BITS_DTIM_CNT4_8197F (BIT_MASK_DTIM_CNT4_8197F << BIT_SHIFT_DTIM_CNT4_8197F) +#define BIT_DTIM_CNT4_8197F(x) \ + (((x) & BIT_MASK_DTIM_CNT4_8197F) << BIT_SHIFT_DTIM_CNT4_8197F) +#define BITS_DTIM_CNT4_8197F \ + (BIT_MASK_DTIM_CNT4_8197F << BIT_SHIFT_DTIM_CNT4_8197F) #define BIT_CLEAR_DTIM_CNT4_8197F(x) ((x) & (~BITS_DTIM_CNT4_8197F)) -#define BIT_GET_DTIM_CNT4_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8197F) & BIT_MASK_DTIM_CNT4_8197F) -#define BIT_SET_DTIM_CNT4_8197F(x, v) (BIT_CLEAR_DTIM_CNT4_8197F(x) | BIT_DTIM_CNT4_8197F(v)) - +#define BIT_GET_DTIM_CNT4_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT4_8197F) & BIT_MASK_DTIM_CNT4_8197F) +#define BIT_SET_DTIM_CNT4_8197F(x, v) \ + (BIT_CLEAR_DTIM_CNT4_8197F(x) | BIT_DTIM_CNT4_8197F(v)) #define BIT_SHIFT_DTIM_PERIOD4_8197F 16 #define BIT_MASK_DTIM_PERIOD4_8197F 0xff -#define BIT_DTIM_PERIOD4_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD4_8197F) << BIT_SHIFT_DTIM_PERIOD4_8197F) -#define BITS_DTIM_PERIOD4_8197F (BIT_MASK_DTIM_PERIOD4_8197F << BIT_SHIFT_DTIM_PERIOD4_8197F) +#define BIT_DTIM_PERIOD4_8197F(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4_8197F) << BIT_SHIFT_DTIM_PERIOD4_8197F) +#define BITS_DTIM_PERIOD4_8197F \ + (BIT_MASK_DTIM_PERIOD4_8197F << BIT_SHIFT_DTIM_PERIOD4_8197F) #define BIT_CLEAR_DTIM_PERIOD4_8197F(x) ((x) & (~BITS_DTIM_PERIOD4_8197F)) -#define BIT_GET_DTIM_PERIOD4_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8197F) & BIT_MASK_DTIM_PERIOD4_8197F) -#define BIT_SET_DTIM_PERIOD4_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD4_8197F(x) | BIT_DTIM_PERIOD4_8197F(v)) +#define BIT_GET_DTIM_PERIOD4_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4_8197F) & BIT_MASK_DTIM_PERIOD4_8197F) +#define BIT_SET_DTIM_PERIOD4_8197F(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4_8197F(x) | BIT_DTIM_PERIOD4_8197F(v)) #define BIT_DTIM4_8197F BIT(15) #define BIT_TIM4_8197F BIT(14) #define BIT_SHIFT_PS_AID_4_8197F 0 #define BIT_MASK_PS_AID_4_8197F 0x7ff -#define BIT_PS_AID_4_8197F(x) (((x) & BIT_MASK_PS_AID_4_8197F) << BIT_SHIFT_PS_AID_4_8197F) -#define BITS_PS_AID_4_8197F (BIT_MASK_PS_AID_4_8197F << BIT_SHIFT_PS_AID_4_8197F) +#define BIT_PS_AID_4_8197F(x) \ + (((x) & BIT_MASK_PS_AID_4_8197F) << BIT_SHIFT_PS_AID_4_8197F) +#define BITS_PS_AID_4_8197F \ + (BIT_MASK_PS_AID_4_8197F << BIT_SHIFT_PS_AID_4_8197F) #define BIT_CLEAR_PS_AID_4_8197F(x) ((x) & (~BITS_PS_AID_4_8197F)) -#define BIT_GET_PS_AID_4_8197F(x) (((x) >> BIT_SHIFT_PS_AID_4_8197F) & BIT_MASK_PS_AID_4_8197F) -#define BIT_SET_PS_AID_4_8197F(x, v) (BIT_CLEAR_PS_AID_4_8197F(x) | BIT_PS_AID_4_8197F(v)) - +#define BIT_GET_PS_AID_4_8197F(x) \ + (((x) >> BIT_SHIFT_PS_AID_4_8197F) & BIT_MASK_PS_AID_4_8197F) +#define BIT_SET_PS_AID_4_8197F(x, v) \ + (BIT_CLEAR_PS_AID_4_8197F(x) | BIT_PS_AID_4_8197F(v)) /* 2 REG_A1_ADDR_MASK_8197F (A1 ADDR MASK REGISTER) */ #define BIT_SHIFT_A1_ADDR_MASK_8197F 0 #define BIT_MASK_A1_ADDR_MASK_8197F 0xffffffffL -#define BIT_A1_ADDR_MASK_8197F(x) (((x) & BIT_MASK_A1_ADDR_MASK_8197F) << BIT_SHIFT_A1_ADDR_MASK_8197F) -#define BITS_A1_ADDR_MASK_8197F (BIT_MASK_A1_ADDR_MASK_8197F << BIT_SHIFT_A1_ADDR_MASK_8197F) +#define BIT_A1_ADDR_MASK_8197F(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK_8197F) << BIT_SHIFT_A1_ADDR_MASK_8197F) +#define BITS_A1_ADDR_MASK_8197F \ + (BIT_MASK_A1_ADDR_MASK_8197F << BIT_SHIFT_A1_ADDR_MASK_8197F) #define BIT_CLEAR_A1_ADDR_MASK_8197F(x) ((x) & (~BITS_A1_ADDR_MASK_8197F)) -#define BIT_GET_A1_ADDR_MASK_8197F(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8197F) & BIT_MASK_A1_ADDR_MASK_8197F) -#define BIT_SET_A1_ADDR_MASK_8197F(x, v) (BIT_CLEAR_A1_ADDR_MASK_8197F(x) | BIT_A1_ADDR_MASK_8197F(v)) - +#define BIT_GET_A1_ADDR_MASK_8197F(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK_8197F) & BIT_MASK_A1_ADDR_MASK_8197F) +#define BIT_SET_A1_ADDR_MASK_8197F(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK_8197F(x) | BIT_A1_ADDR_MASK_8197F(v)) /* 2 REG_MACID2_8197F (MAC ID2 REGISTER) */ #define BIT_SHIFT_MACID2_8197F 0 #define BIT_MASK_MACID2_8197F 0xffffffffffffL -#define BIT_MACID2_8197F(x) (((x) & BIT_MASK_MACID2_8197F) << BIT_SHIFT_MACID2_8197F) +#define BIT_MACID2_8197F(x) \ + (((x) & BIT_MASK_MACID2_8197F) << BIT_SHIFT_MACID2_8197F) #define BITS_MACID2_8197F (BIT_MASK_MACID2_8197F << BIT_SHIFT_MACID2_8197F) #define BIT_CLEAR_MACID2_8197F(x) ((x) & (~BITS_MACID2_8197F)) -#define BIT_GET_MACID2_8197F(x) (((x) >> BIT_SHIFT_MACID2_8197F) & BIT_MASK_MACID2_8197F) -#define BIT_SET_MACID2_8197F(x, v) (BIT_CLEAR_MACID2_8197F(x) | BIT_MACID2_8197F(v)) - +#define BIT_GET_MACID2_8197F(x) \ + (((x) >> BIT_SHIFT_MACID2_8197F) & BIT_MASK_MACID2_8197F) +#define BIT_SET_MACID2_8197F(x, v) \ + (BIT_CLEAR_MACID2_8197F(x) | BIT_MACID2_8197F(v)) /* 2 REG_BSSID2_8197F (BSSID2 REGISTER) */ #define BIT_SHIFT_BSSID2_8197F 0 #define BIT_MASK_BSSID2_8197F 0xffffffffffffL -#define BIT_BSSID2_8197F(x) (((x) & BIT_MASK_BSSID2_8197F) << BIT_SHIFT_BSSID2_8197F) +#define BIT_BSSID2_8197F(x) \ + (((x) & BIT_MASK_BSSID2_8197F) << BIT_SHIFT_BSSID2_8197F) #define BITS_BSSID2_8197F (BIT_MASK_BSSID2_8197F << BIT_SHIFT_BSSID2_8197F) #define BIT_CLEAR_BSSID2_8197F(x) ((x) & (~BITS_BSSID2_8197F)) -#define BIT_GET_BSSID2_8197F(x) (((x) >> BIT_SHIFT_BSSID2_8197F) & BIT_MASK_BSSID2_8197F) -#define BIT_SET_BSSID2_8197F(x, v) (BIT_CLEAR_BSSID2_8197F(x) | BIT_BSSID2_8197F(v)) - +#define BIT_GET_BSSID2_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID2_8197F) & BIT_MASK_BSSID2_8197F) +#define BIT_SET_BSSID2_8197F(x, v) \ + (BIT_CLEAR_BSSID2_8197F(x) | BIT_BSSID2_8197F(v)) /* 2 REG_MACID3_8197F (MAC ID3 REGISTER) */ #define BIT_SHIFT_MACID3_8197F 0 #define BIT_MASK_MACID3_8197F 0xffffffffffffL -#define BIT_MACID3_8197F(x) (((x) & BIT_MASK_MACID3_8197F) << BIT_SHIFT_MACID3_8197F) +#define BIT_MACID3_8197F(x) \ + (((x) & BIT_MASK_MACID3_8197F) << BIT_SHIFT_MACID3_8197F) #define BITS_MACID3_8197F (BIT_MASK_MACID3_8197F << BIT_SHIFT_MACID3_8197F) #define BIT_CLEAR_MACID3_8197F(x) ((x) & (~BITS_MACID3_8197F)) -#define BIT_GET_MACID3_8197F(x) (((x) >> BIT_SHIFT_MACID3_8197F) & BIT_MASK_MACID3_8197F) -#define BIT_SET_MACID3_8197F(x, v) (BIT_CLEAR_MACID3_8197F(x) | BIT_MACID3_8197F(v)) - +#define BIT_GET_MACID3_8197F(x) \ + (((x) >> BIT_SHIFT_MACID3_8197F) & BIT_MASK_MACID3_8197F) +#define BIT_SET_MACID3_8197F(x, v) \ + (BIT_CLEAR_MACID3_8197F(x) | BIT_MACID3_8197F(v)) /* 2 REG_BSSID3_8197F (BSSID3 REGISTER) */ #define BIT_SHIFT_BSSID3_8197F 0 #define BIT_MASK_BSSID3_8197F 0xffffffffffffL -#define BIT_BSSID3_8197F(x) (((x) & BIT_MASK_BSSID3_8197F) << BIT_SHIFT_BSSID3_8197F) +#define BIT_BSSID3_8197F(x) \ + (((x) & BIT_MASK_BSSID3_8197F) << BIT_SHIFT_BSSID3_8197F) #define BITS_BSSID3_8197F (BIT_MASK_BSSID3_8197F << BIT_SHIFT_BSSID3_8197F) #define BIT_CLEAR_BSSID3_8197F(x) ((x) & (~BITS_BSSID3_8197F)) -#define BIT_GET_BSSID3_8197F(x) (((x) >> BIT_SHIFT_BSSID3_8197F) & BIT_MASK_BSSID3_8197F) -#define BIT_SET_BSSID3_8197F(x, v) (BIT_CLEAR_BSSID3_8197F(x) | BIT_BSSID3_8197F(v)) - +#define BIT_GET_BSSID3_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID3_8197F) & BIT_MASK_BSSID3_8197F) +#define BIT_SET_BSSID3_8197F(x, v) \ + (BIT_CLEAR_BSSID3_8197F(x) | BIT_BSSID3_8197F(v)) /* 2 REG_MACID4_8197F (MAC ID4 REGISTER) */ #define BIT_SHIFT_MACID4_8197F 0 #define BIT_MASK_MACID4_8197F 0xffffffffffffL -#define BIT_MACID4_8197F(x) (((x) & BIT_MASK_MACID4_8197F) << BIT_SHIFT_MACID4_8197F) +#define BIT_MACID4_8197F(x) \ + (((x) & BIT_MASK_MACID4_8197F) << BIT_SHIFT_MACID4_8197F) #define BITS_MACID4_8197F (BIT_MASK_MACID4_8197F << BIT_SHIFT_MACID4_8197F) #define BIT_CLEAR_MACID4_8197F(x) ((x) & (~BITS_MACID4_8197F)) -#define BIT_GET_MACID4_8197F(x) (((x) >> BIT_SHIFT_MACID4_8197F) & BIT_MASK_MACID4_8197F) -#define BIT_SET_MACID4_8197F(x, v) (BIT_CLEAR_MACID4_8197F(x) | BIT_MACID4_8197F(v)) - +#define BIT_GET_MACID4_8197F(x) \ + (((x) >> BIT_SHIFT_MACID4_8197F) & BIT_MASK_MACID4_8197F) +#define BIT_SET_MACID4_8197F(x, v) \ + (BIT_CLEAR_MACID4_8197F(x) | BIT_MACID4_8197F(v)) /* 2 REG_BSSID4_8197F (BSSID4 REGISTER) */ #define BIT_SHIFT_BSSID4_8197F 0 #define BIT_MASK_BSSID4_8197F 0xffffffffffffL -#define BIT_BSSID4_8197F(x) (((x) & BIT_MASK_BSSID4_8197F) << BIT_SHIFT_BSSID4_8197F) +#define BIT_BSSID4_8197F(x) \ + (((x) & BIT_MASK_BSSID4_8197F) << BIT_SHIFT_BSSID4_8197F) #define BITS_BSSID4_8197F (BIT_MASK_BSSID4_8197F << BIT_SHIFT_BSSID4_8197F) #define BIT_CLEAR_BSSID4_8197F(x) ((x) & (~BITS_BSSID4_8197F)) -#define BIT_GET_BSSID4_8197F(x) (((x) >> BIT_SHIFT_BSSID4_8197F) & BIT_MASK_BSSID4_8197F) -#define BIT_SET_BSSID4_8197F(x, v) (BIT_CLEAR_BSSID4_8197F(x) | BIT_BSSID4_8197F(v)) - +#define BIT_GET_BSSID4_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID4_8197F) & BIT_MASK_BSSID4_8197F) +#define BIT_SET_BSSID4_8197F(x, v) \ + (BIT_CLEAR_BSSID4_8197F(x) | BIT_BSSID4_8197F(v)) /* 2 REG_NOA_REPORT_8197F */ @@ -11767,20 +15454,37 @@ #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F 4 #define BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F 0x3 -#define BIT_WMAC_TXMU_ACKPOLICY_8197F(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) -#define BITS_WMAC_TXMU_ACKPOLICY_8197F (BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) -#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8197F)) -#define BIT_GET_WMAC_TXMU_ACKPOLICY_8197F(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F) -#define BIT_SET_WMAC_TXMU_ACKPOLICY_8197F(x, v) (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) | BIT_WMAC_TXMU_ACKPOLICY_8197F(v)) - +#define BIT_WMAC_TXMU_ACKPOLICY_8197F(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F) \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) +#define BITS_WMAC_TXMU_ACKPOLICY_8197F \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) \ + ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8197F)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) & \ + BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F) +#define BIT_SET_WMAC_TXMU_ACKPOLICY_8197F(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) | \ + BIT_WMAC_TXMU_ACKPOLICY_8197F(v)) #define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F 1 #define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F 0x7 -#define BIT_WMAC_MU_BFEE_PORT_SEL_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) -#define BITS_WMAC_MU_BFEE_PORT_SEL_8197F (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8197F)) -#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F) -#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) | BIT_WMAC_MU_BFEE_PORT_SEL_8197F(v)) +#define BIT_WMAC_MU_BFEE_PORT_SEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) +#define BITS_WMAC_MU_BFEE_PORT_SEL_8197F \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8197F)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) | \ + BIT_WMAC_MU_BFEE_PORT_SEL_8197F(v)) #define BIT_WMAC_MU_BFEE_DIS_8197F BIT(0) @@ -11788,12 +15492,20 @@ #define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F 0 #define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F 0xff -#define BIT_WMAC_PAUSE_BB_CLR_TH_8197F(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) -#define BITS_WMAC_PAUSE_BB_CLR_TH_8197F (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) -#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8197F)) -#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8197F(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F) -#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8197F(x, v) (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) | BIT_WMAC_PAUSE_BB_CLR_TH_8197F(v)) - +#define BIT_WMAC_PAUSE_BB_CLR_TH_8197F(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) +#define BITS_WMAC_PAUSE_BB_CLR_TH_8197F \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) \ + ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8197F)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8197F(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) | \ + BIT_WMAC_PAUSE_BB_CLR_TH_8197F(v)) /* 2 REG_WMAC_MU_ARB_8197F */ #define BIT_WMAC_ARB_HW_ADAPT_EN_8197F BIT(7) @@ -11801,32 +15513,51 @@ #define BIT_SHIFT_WMAC_ARB_SW_STATE_8197F 0 #define BIT_MASK_WMAC_ARB_SW_STATE_8197F 0x3f -#define BIT_WMAC_ARB_SW_STATE_8197F(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8197F) << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) -#define BITS_WMAC_ARB_SW_STATE_8197F (BIT_MASK_WMAC_ARB_SW_STATE_8197F << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) -#define BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) ((x) & (~BITS_WMAC_ARB_SW_STATE_8197F)) -#define BIT_GET_WMAC_ARB_SW_STATE_8197F(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) & BIT_MASK_WMAC_ARB_SW_STATE_8197F) -#define BIT_SET_WMAC_ARB_SW_STATE_8197F(x, v) (BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) | BIT_WMAC_ARB_SW_STATE_8197F(v)) - +#define BIT_WMAC_ARB_SW_STATE_8197F(x) \ + (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8197F) \ + << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) +#define BITS_WMAC_ARB_SW_STATE_8197F \ + (BIT_MASK_WMAC_ARB_SW_STATE_8197F << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) +#define BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) \ + ((x) & (~BITS_WMAC_ARB_SW_STATE_8197F)) +#define BIT_GET_WMAC_ARB_SW_STATE_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) & \ + BIT_MASK_WMAC_ARB_SW_STATE_8197F) +#define BIT_SET_WMAC_ARB_SW_STATE_8197F(x, v) \ + (BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) | BIT_WMAC_ARB_SW_STATE_8197F(v)) /* 2 REG_WMAC_MU_OPTION_8197F */ #define BIT_SHIFT_WMAC_MU_DBGSEL_8197F 5 #define BIT_MASK_WMAC_MU_DBGSEL_8197F 0x3 -#define BIT_WMAC_MU_DBGSEL_8197F(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8197F) << BIT_SHIFT_WMAC_MU_DBGSEL_8197F) -#define BITS_WMAC_MU_DBGSEL_8197F (BIT_MASK_WMAC_MU_DBGSEL_8197F << BIT_SHIFT_WMAC_MU_DBGSEL_8197F) +#define BIT_WMAC_MU_DBGSEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL_8197F) \ + << BIT_SHIFT_WMAC_MU_DBGSEL_8197F) +#define BITS_WMAC_MU_DBGSEL_8197F \ + (BIT_MASK_WMAC_MU_DBGSEL_8197F << BIT_SHIFT_WMAC_MU_DBGSEL_8197F) #define BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8197F)) -#define BIT_GET_WMAC_MU_DBGSEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8197F) & BIT_MASK_WMAC_MU_DBGSEL_8197F) -#define BIT_SET_WMAC_MU_DBGSEL_8197F(x, v) (BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) | BIT_WMAC_MU_DBGSEL_8197F(v)) - +#define BIT_GET_WMAC_MU_DBGSEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8197F) & \ + BIT_MASK_WMAC_MU_DBGSEL_8197F) +#define BIT_SET_WMAC_MU_DBGSEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) | BIT_WMAC_MU_DBGSEL_8197F(v)) #define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F 0 #define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F 0x1f -#define BIT_WMAC_MU_CPRD_TIMEOUT_8197F(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) -#define BITS_WMAC_MU_CPRD_TIMEOUT_8197F (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) -#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8197F)) -#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F) -#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8197F(x, v) (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) | BIT_WMAC_MU_CPRD_TIMEOUT_8197F(v)) - +#define BIT_WMAC_MU_CPRD_TIMEOUT_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F) \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) +#define BITS_WMAC_MU_CPRD_TIMEOUT_8197F \ + (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) +#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) \ + ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8197F)) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) & \ + BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F) +#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) | \ + BIT_WMAC_MU_CPRD_TIMEOUT_8197F(v)) /* 2 REG_WMAC_MU_BF_CTL_8197F */ #define BIT_WMAC_INVLD_BFPRT_CHK_8197F BIT(15) @@ -11834,41 +15565,66 @@ #define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F 12 #define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F 0x3 -#define BIT_WMAC_MU_BFRPTSEG_SEL_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) -#define BITS_WMAC_MU_BFRPTSEG_SEL_8197F (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) -#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8197F)) -#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F) -#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) | BIT_WMAC_MU_BFRPTSEG_SEL_8197F(v)) - +#define BIT_WMAC_MU_BFRPTSEG_SEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) +#define BITS_WMAC_MU_BFRPTSEG_SEL_8197F \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8197F)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) | \ + BIT_WMAC_MU_BFRPTSEG_SEL_8197F(v)) #define BIT_SHIFT_WMAC_MU_BF_MYAID_8197F 0 #define BIT_MASK_WMAC_MU_BF_MYAID_8197F 0xfff -#define BIT_WMAC_MU_BF_MYAID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8197F) << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) -#define BITS_WMAC_MU_BF_MYAID_8197F (BIT_MASK_WMAC_MU_BF_MYAID_8197F << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) -#define BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) ((x) & (~BITS_WMAC_MU_BF_MYAID_8197F)) -#define BIT_GET_WMAC_MU_BF_MYAID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) & BIT_MASK_WMAC_MU_BF_MYAID_8197F) -#define BIT_SET_WMAC_MU_BF_MYAID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) | BIT_WMAC_MU_BF_MYAID_8197F(v)) - +#define BIT_WMAC_MU_BF_MYAID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8197F) \ + << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) +#define BITS_WMAC_MU_BF_MYAID_8197F \ + (BIT_MASK_WMAC_MU_BF_MYAID_8197F << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BF_MYAID_8197F)) +#define BIT_GET_WMAC_MU_BF_MYAID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) & \ + BIT_MASK_WMAC_MU_BF_MYAID_8197F) +#define BIT_SET_WMAC_MU_BF_MYAID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) | BIT_WMAC_MU_BF_MYAID_8197F(v)) /* 2 REG_WMAC_MU_BFRPT_PARA_8197F */ #define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F 12 #define BIT_MASK_BFRPT_PARA_USERID_SEL_8197F 0x7 -#define BIT_BFRPT_PARA_USERID_SEL_8197F(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8197F) << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) -#define BITS_BFRPT_PARA_USERID_SEL_8197F (BIT_MASK_BFRPT_PARA_USERID_SEL_8197F << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) -#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) ((x) & (~BITS_BFRPT_PARA_USERID_SEL_8197F)) -#define BIT_GET_BFRPT_PARA_USERID_SEL_8197F(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) & BIT_MASK_BFRPT_PARA_USERID_SEL_8197F) -#define BIT_SET_BFRPT_PARA_USERID_SEL_8197F(x, v) (BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) | BIT_BFRPT_PARA_USERID_SEL_8197F(v)) - +#define BIT_BFRPT_PARA_USERID_SEL_8197F(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8197F) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) +#define BITS_BFRPT_PARA_USERID_SEL_8197F \ + (BIT_MASK_BFRPT_PARA_USERID_SEL_8197F \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) \ + ((x) & (~BITS_BFRPT_PARA_USERID_SEL_8197F)) +#define BIT_GET_BFRPT_PARA_USERID_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL_8197F) +#define BIT_SET_BFRPT_PARA_USERID_SEL_8197F(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) | \ + BIT_BFRPT_PARA_USERID_SEL_8197F(v)) #define BIT_SHIFT_BFRPT_PARA_8197F 0 #define BIT_MASK_BFRPT_PARA_8197F 0xfff -#define BIT_BFRPT_PARA_8197F(x) (((x) & BIT_MASK_BFRPT_PARA_8197F) << BIT_SHIFT_BFRPT_PARA_8197F) -#define BITS_BFRPT_PARA_8197F (BIT_MASK_BFRPT_PARA_8197F << BIT_SHIFT_BFRPT_PARA_8197F) +#define BIT_BFRPT_PARA_8197F(x) \ + (((x) & BIT_MASK_BFRPT_PARA_8197F) << BIT_SHIFT_BFRPT_PARA_8197F) +#define BITS_BFRPT_PARA_8197F \ + (BIT_MASK_BFRPT_PARA_8197F << BIT_SHIFT_BFRPT_PARA_8197F) #define BIT_CLEAR_BFRPT_PARA_8197F(x) ((x) & (~BITS_BFRPT_PARA_8197F)) -#define BIT_GET_BFRPT_PARA_8197F(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8197F) & BIT_MASK_BFRPT_PARA_8197F) -#define BIT_SET_BFRPT_PARA_8197F(x, v) (BIT_CLEAR_BFRPT_PARA_8197F(x) | BIT_BFRPT_PARA_8197F(v)) - +#define BIT_GET_BFRPT_PARA_8197F(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_8197F) & BIT_MASK_BFRPT_PARA_8197F) +#define BIT_SET_BFRPT_PARA_8197F(x, v) \ + (BIT_CLEAR_BFRPT_PARA_8197F(x) | BIT_BFRPT_PARA_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F */ #define BIT_STATUS_BFEE2_8197F BIT(10) @@ -11876,12 +15632,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE2_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE2_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) -#define BITS_WMAC_MU_BFEE2_AID_8197F (BIT_MASK_WMAC_MU_BFEE2_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE2_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE2_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) & BIT_MASK_WMAC_MU_BFEE2_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE2_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) | BIT_WMAC_MU_BFEE2_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE2_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) +#define BITS_WMAC_MU_BFEE2_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE2_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE2_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE2_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE2_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE2_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) | BIT_WMAC_MU_BFEE2_AID_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F */ #define BIT_STATUS_BFEE3_8197F BIT(10) @@ -11889,12 +15651,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE3_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE3_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) -#define BITS_WMAC_MU_BFEE3_AID_8197F (BIT_MASK_WMAC_MU_BFEE3_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE3_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE3_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) & BIT_MASK_WMAC_MU_BFEE3_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE3_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) | BIT_WMAC_MU_BFEE3_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE3_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) +#define BITS_WMAC_MU_BFEE3_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE3_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE3_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE3_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE3_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE3_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) | BIT_WMAC_MU_BFEE3_AID_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F */ #define BIT_STATUS_BFEE4_8197F BIT(10) @@ -11902,12 +15670,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE4_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE4_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) -#define BITS_WMAC_MU_BFEE4_AID_8197F (BIT_MASK_WMAC_MU_BFEE4_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE4_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE4_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) & BIT_MASK_WMAC_MU_BFEE4_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE4_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) | BIT_WMAC_MU_BFEE4_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE4_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) +#define BITS_WMAC_MU_BFEE4_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE4_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE4_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE4_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE4_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE4_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) | BIT_WMAC_MU_BFEE4_AID_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F */ #define BIT_STATUS_BFEE5_8197F BIT(10) @@ -11915,12 +15689,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE5_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE5_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) -#define BITS_WMAC_MU_BFEE5_AID_8197F (BIT_MASK_WMAC_MU_BFEE5_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE5_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE5_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) & BIT_MASK_WMAC_MU_BFEE5_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE5_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) | BIT_WMAC_MU_BFEE5_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE5_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) +#define BITS_WMAC_MU_BFEE5_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE5_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE5_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE5_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE5_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE5_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) | BIT_WMAC_MU_BFEE5_AID_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F */ #define BIT_STATUS_BFEE6_8197F BIT(10) @@ -11928,12 +15708,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE6_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE6_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) -#define BITS_WMAC_MU_BFEE6_AID_8197F (BIT_MASK_WMAC_MU_BFEE6_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE6_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE6_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) & BIT_MASK_WMAC_MU_BFEE6_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE6_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) | BIT_WMAC_MU_BFEE6_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE6_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) +#define BITS_WMAC_MU_BFEE6_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE6_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE6_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE6_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE6_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE6_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) | BIT_WMAC_MU_BFEE6_AID_8197F(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F */ #define BIT_BIT_STATUS_BFEE4_8197F BIT(10) @@ -11941,72 +15727,118 @@ #define BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F 0 #define BIT_MASK_WMAC_MU_BFEE7_AID_8197F 0x1ff -#define BIT_WMAC_MU_BFEE7_AID_8197F(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8197F) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) -#define BITS_WMAC_MU_BFEE7_AID_8197F (BIT_MASK_WMAC_MU_BFEE7_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) -#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) ((x) & (~BITS_WMAC_MU_BFEE7_AID_8197F)) -#define BIT_GET_WMAC_MU_BFEE7_AID_8197F(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) & BIT_MASK_WMAC_MU_BFEE7_AID_8197F) -#define BIT_SET_WMAC_MU_BFEE7_AID_8197F(x, v) (BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) | BIT_WMAC_MU_BFEE7_AID_8197F(v)) - +#define BIT_WMAC_MU_BFEE7_AID_8197F(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8197F) \ + << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) +#define BITS_WMAC_MU_BFEE7_AID_8197F \ + (BIT_MASK_WMAC_MU_BFEE7_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) \ + ((x) & (~BITS_WMAC_MU_BFEE7_AID_8197F)) +#define BIT_GET_WMAC_MU_BFEE7_AID_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) & \ + BIT_MASK_WMAC_MU_BFEE7_AID_8197F) +#define BIT_SET_WMAC_MU_BFEE7_AID_8197F(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) | BIT_WMAC_MU_BFEE7_AID_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_RST_ALL_COUNTER_8197F BIT(31) #define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F 16 #define BIT_MASK_ABORT_RX_VBON_COUNTER_8197F 0xff -#define BIT_ABORT_RX_VBON_COUNTER_8197F(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8197F) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) -#define BITS_ABORT_RX_VBON_COUNTER_8197F (BIT_MASK_ABORT_RX_VBON_COUNTER_8197F << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) -#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8197F)) -#define BIT_GET_ABORT_RX_VBON_COUNTER_8197F(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) & BIT_MASK_ABORT_RX_VBON_COUNTER_8197F) -#define BIT_SET_ABORT_RX_VBON_COUNTER_8197F(x, v) (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) | BIT_ABORT_RX_VBON_COUNTER_8197F(v)) - +#define BIT_ABORT_RX_VBON_COUNTER_8197F(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8197F) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) +#define BITS_ABORT_RX_VBON_COUNTER_8197F \ + (BIT_MASK_ABORT_RX_VBON_COUNTER_8197F \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) \ + ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8197F)) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8197F(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER_8197F) +#define BIT_SET_ABORT_RX_VBON_COUNTER_8197F(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) | \ + BIT_ABORT_RX_VBON_COUNTER_8197F(v)) #define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F 8 #define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F 0xff -#define BIT_ABORT_RX_RDRDY_COUNTER_8197F(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) -#define BITS_ABORT_RX_RDRDY_COUNTER_8197F (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) -#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8197F)) -#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8197F(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F) -#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8197F(x, v) (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) | BIT_ABORT_RX_RDRDY_COUNTER_8197F(v)) - +#define BIT_ABORT_RX_RDRDY_COUNTER_8197F(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) +#define BITS_ABORT_RX_RDRDY_COUNTER_8197F \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8197F)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8197F(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8197F(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) | \ + BIT_ABORT_RX_RDRDY_COUNTER_8197F(v)) #define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F 0 #define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F 0xff -#define BIT_VBON_EARLY_FALLING_COUNTER_8197F(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) -#define BITS_VBON_EARLY_FALLING_COUNTER_8197F (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) -#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8197F)) -#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8197F(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F) -#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8197F(x, v) (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) | BIT_VBON_EARLY_FALLING_COUNTER_8197F(v)) - +#define BIT_VBON_EARLY_FALLING_COUNTER_8197F(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) +#define BITS_VBON_EARLY_FALLING_COUNTER_8197F \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8197F)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8197F(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8197F(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER_8197F(v)) /* 2 REG_NOT_VALID_8197F */ #define BIT_WMAC_PLCP_TRX_SEL_8197F BIT(31) #define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F 28 #define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F 0x7 -#define BIT_WMAC_PLCP_RDSIG_SEL_8197F(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) -#define BITS_WMAC_PLCP_RDSIG_SEL_8197F (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) -#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8197F)) -#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8197F(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F) -#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8197F(x, v) (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) | BIT_WMAC_PLCP_RDSIG_SEL_8197F(v)) - +#define BIT_WMAC_PLCP_RDSIG_SEL_8197F(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) +#define BITS_WMAC_PLCP_RDSIG_SEL_8197F \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) \ + ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8197F)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) & \ + BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8197F(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) | \ + BIT_WMAC_PLCP_RDSIG_SEL_8197F(v)) #define BIT_SHIFT_WMAC_RATE_IDX_8197F 24 #define BIT_MASK_WMAC_RATE_IDX_8197F 0xf -#define BIT_WMAC_RATE_IDX_8197F(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8197F) << BIT_SHIFT_WMAC_RATE_IDX_8197F) -#define BITS_WMAC_RATE_IDX_8197F (BIT_MASK_WMAC_RATE_IDX_8197F << BIT_SHIFT_WMAC_RATE_IDX_8197F) +#define BIT_WMAC_RATE_IDX_8197F(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX_8197F) << BIT_SHIFT_WMAC_RATE_IDX_8197F) +#define BITS_WMAC_RATE_IDX_8197F \ + (BIT_MASK_WMAC_RATE_IDX_8197F << BIT_SHIFT_WMAC_RATE_IDX_8197F) #define BIT_CLEAR_WMAC_RATE_IDX_8197F(x) ((x) & (~BITS_WMAC_RATE_IDX_8197F)) -#define BIT_GET_WMAC_RATE_IDX_8197F(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8197F) & BIT_MASK_WMAC_RATE_IDX_8197F) -#define BIT_SET_WMAC_RATE_IDX_8197F(x, v) (BIT_CLEAR_WMAC_RATE_IDX_8197F(x) | BIT_WMAC_RATE_IDX_8197F(v)) - +#define BIT_GET_WMAC_RATE_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8197F) & BIT_MASK_WMAC_RATE_IDX_8197F) +#define BIT_SET_WMAC_RATE_IDX_8197F(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX_8197F(x) | BIT_WMAC_RATE_IDX_8197F(v)) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8197F 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8197F 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8197F(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8197F) << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) -#define BITS_WMAC_PLCP_RDSIG_8197F (BIT_MASK_WMAC_PLCP_RDSIG_8197F << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) +#define BIT_WMAC_PLCP_RDSIG_8197F(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8197F) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) +#define BITS_WMAC_PLCP_RDSIG_8197F \ + (BIT_MASK_WMAC_PLCP_RDSIG_8197F << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) #define BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8197F)) -#define BIT_GET_WMAC_PLCP_RDSIG_8197F(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) & BIT_MASK_WMAC_PLCP_RDSIG_8197F) -#define BIT_SET_WMAC_PLCP_RDSIG_8197F(x, v) (BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) | BIT_WMAC_PLCP_RDSIG_8197F(v)) - +#define BIT_GET_WMAC_PLCP_RDSIG_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8197F) +#define BIT_SET_WMAC_PLCP_RDSIG_8197F(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) | BIT_WMAC_PLCP_RDSIG_8197F(v)) /* 2 REG_NOT_VALID_8197F */ @@ -12028,7 +15860,6 @@ #define BIT_GET_TA0_8197F(x) (((x) >> BIT_SHIFT_TA0_8197F) & BIT_MASK_TA0_8197F) #define BIT_SET_TA0_8197F(x, v) (BIT_CLEAR_TA0_8197F(x) | BIT_TA0_8197F(v)) - /* 2 REG_TRANSMIT_ADDRSS_1_8197F (TA1 REGISTER) */ #define BIT_SHIFT_TA1_8197F 0 @@ -12039,7 +15870,6 @@ #define BIT_GET_TA1_8197F(x) (((x) >> BIT_SHIFT_TA1_8197F) & BIT_MASK_TA1_8197F) #define BIT_SET_TA1_8197F(x, v) (BIT_CLEAR_TA1_8197F(x) | BIT_TA1_8197F(v)) - /* 2 REG_TRANSMIT_ADDRSS_2_8197F (TA2 REGISTER) */ #define BIT_SHIFT_TA2_8197F 0 @@ -12050,7 +15880,6 @@ #define BIT_GET_TA2_8197F(x) (((x) >> BIT_SHIFT_TA2_8197F) & BIT_MASK_TA2_8197F) #define BIT_SET_TA2_8197F(x, v) (BIT_CLEAR_TA2_8197F(x) | BIT_TA2_8197F(v)) - /* 2 REG_TRANSMIT_ADDRSS_3_8197F (TA3 REGISTER) */ #define BIT_SHIFT_TA3_8197F 0 @@ -12061,7 +15890,6 @@ #define BIT_GET_TA3_8197F(x) (((x) >> BIT_SHIFT_TA3_8197F) & BIT_MASK_TA3_8197F) #define BIT_SET_TA3_8197F(x, v) (BIT_CLEAR_TA3_8197F(x) | BIT_TA3_8197F(v)) - /* 2 REG_TRANSMIT_ADDRSS_4_8197F (TA4 REGISTER) */ #define BIT_SHIFT_TA4_8197F 0 @@ -12072,61 +15900,74 @@ #define BIT_GET_TA4_8197F(x) (((x) >> BIT_SHIFT_TA4_8197F) & BIT_MASK_TA4_8197F) #define BIT_SET_TA4_8197F(x, v) (BIT_CLEAR_TA4_8197F(x) | BIT_TA4_8197F(v)) - /* 2 REG_NOT_VALID_8197F */ /* 2 REG_MACID1_8197F */ #define BIT_SHIFT_MACID1_8197F 0 #define BIT_MASK_MACID1_8197F 0xffffffffffffL -#define BIT_MACID1_8197F(x) (((x) & BIT_MASK_MACID1_8197F) << BIT_SHIFT_MACID1_8197F) +#define BIT_MACID1_8197F(x) \ + (((x) & BIT_MASK_MACID1_8197F) << BIT_SHIFT_MACID1_8197F) #define BITS_MACID1_8197F (BIT_MASK_MACID1_8197F << BIT_SHIFT_MACID1_8197F) #define BIT_CLEAR_MACID1_8197F(x) ((x) & (~BITS_MACID1_8197F)) -#define BIT_GET_MACID1_8197F(x) (((x) >> BIT_SHIFT_MACID1_8197F) & BIT_MASK_MACID1_8197F) -#define BIT_SET_MACID1_8197F(x, v) (BIT_CLEAR_MACID1_8197F(x) | BIT_MACID1_8197F(v)) - +#define BIT_GET_MACID1_8197F(x) \ + (((x) >> BIT_SHIFT_MACID1_8197F) & BIT_MASK_MACID1_8197F) +#define BIT_SET_MACID1_8197F(x, v) \ + (BIT_CLEAR_MACID1_8197F(x) | BIT_MACID1_8197F(v)) /* 2 REG_BSSID1_8197F */ #define BIT_SHIFT_BSSID1_8197F 0 #define BIT_MASK_BSSID1_8197F 0xffffffffffffL -#define BIT_BSSID1_8197F(x) (((x) & BIT_MASK_BSSID1_8197F) << BIT_SHIFT_BSSID1_8197F) +#define BIT_BSSID1_8197F(x) \ + (((x) & BIT_MASK_BSSID1_8197F) << BIT_SHIFT_BSSID1_8197F) #define BITS_BSSID1_8197F (BIT_MASK_BSSID1_8197F << BIT_SHIFT_BSSID1_8197F) #define BIT_CLEAR_BSSID1_8197F(x) ((x) & (~BITS_BSSID1_8197F)) -#define BIT_GET_BSSID1_8197F(x) (((x) >> BIT_SHIFT_BSSID1_8197F) & BIT_MASK_BSSID1_8197F) -#define BIT_SET_BSSID1_8197F(x, v) (BIT_CLEAR_BSSID1_8197F(x) | BIT_BSSID1_8197F(v)) - +#define BIT_GET_BSSID1_8197F(x) \ + (((x) >> BIT_SHIFT_BSSID1_8197F) & BIT_MASK_BSSID1_8197F) +#define BIT_SET_BSSID1_8197F(x, v) \ + (BIT_CLEAR_BSSID1_8197F(x) | BIT_BSSID1_8197F(v)) /* 2 REG_BCN_PSR_RPT1_8197F */ #define BIT_SHIFT_DTIM_CNT1_8197F 24 #define BIT_MASK_DTIM_CNT1_8197F 0xff -#define BIT_DTIM_CNT1_8197F(x) (((x) & BIT_MASK_DTIM_CNT1_8197F) << BIT_SHIFT_DTIM_CNT1_8197F) -#define BITS_DTIM_CNT1_8197F (BIT_MASK_DTIM_CNT1_8197F << BIT_SHIFT_DTIM_CNT1_8197F) +#define BIT_DTIM_CNT1_8197F(x) \ + (((x) & BIT_MASK_DTIM_CNT1_8197F) << BIT_SHIFT_DTIM_CNT1_8197F) +#define BITS_DTIM_CNT1_8197F \ + (BIT_MASK_DTIM_CNT1_8197F << BIT_SHIFT_DTIM_CNT1_8197F) #define BIT_CLEAR_DTIM_CNT1_8197F(x) ((x) & (~BITS_DTIM_CNT1_8197F)) -#define BIT_GET_DTIM_CNT1_8197F(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8197F) & BIT_MASK_DTIM_CNT1_8197F) -#define BIT_SET_DTIM_CNT1_8197F(x, v) (BIT_CLEAR_DTIM_CNT1_8197F(x) | BIT_DTIM_CNT1_8197F(v)) - +#define BIT_GET_DTIM_CNT1_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT1_8197F) & BIT_MASK_DTIM_CNT1_8197F) +#define BIT_SET_DTIM_CNT1_8197F(x, v) \ + (BIT_CLEAR_DTIM_CNT1_8197F(x) | BIT_DTIM_CNT1_8197F(v)) #define BIT_SHIFT_DTIM_PERIOD1_8197F 16 #define BIT_MASK_DTIM_PERIOD1_8197F 0xff -#define BIT_DTIM_PERIOD1_8197F(x) (((x) & BIT_MASK_DTIM_PERIOD1_8197F) << BIT_SHIFT_DTIM_PERIOD1_8197F) -#define BITS_DTIM_PERIOD1_8197F (BIT_MASK_DTIM_PERIOD1_8197F << BIT_SHIFT_DTIM_PERIOD1_8197F) +#define BIT_DTIM_PERIOD1_8197F(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1_8197F) << BIT_SHIFT_DTIM_PERIOD1_8197F) +#define BITS_DTIM_PERIOD1_8197F \ + (BIT_MASK_DTIM_PERIOD1_8197F << BIT_SHIFT_DTIM_PERIOD1_8197F) #define BIT_CLEAR_DTIM_PERIOD1_8197F(x) ((x) & (~BITS_DTIM_PERIOD1_8197F)) -#define BIT_GET_DTIM_PERIOD1_8197F(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8197F) & BIT_MASK_DTIM_PERIOD1_8197F) -#define BIT_SET_DTIM_PERIOD1_8197F(x, v) (BIT_CLEAR_DTIM_PERIOD1_8197F(x) | BIT_DTIM_PERIOD1_8197F(v)) +#define BIT_GET_DTIM_PERIOD1_8197F(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1_8197F) & BIT_MASK_DTIM_PERIOD1_8197F) +#define BIT_SET_DTIM_PERIOD1_8197F(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1_8197F(x) | BIT_DTIM_PERIOD1_8197F(v)) #define BIT_DTIM1_8197F BIT(15) #define BIT_TIM1_8197F BIT(14) #define BIT_SHIFT_PS_AID_1_8197F 0 #define BIT_MASK_PS_AID_1_8197F 0x7ff -#define BIT_PS_AID_1_8197F(x) (((x) & BIT_MASK_PS_AID_1_8197F) << BIT_SHIFT_PS_AID_1_8197F) -#define BITS_PS_AID_1_8197F (BIT_MASK_PS_AID_1_8197F << BIT_SHIFT_PS_AID_1_8197F) +#define BIT_PS_AID_1_8197F(x) \ + (((x) & BIT_MASK_PS_AID_1_8197F) << BIT_SHIFT_PS_AID_1_8197F) +#define BITS_PS_AID_1_8197F \ + (BIT_MASK_PS_AID_1_8197F << BIT_SHIFT_PS_AID_1_8197F) #define BIT_CLEAR_PS_AID_1_8197F(x) ((x) & (~BITS_PS_AID_1_8197F)) -#define BIT_GET_PS_AID_1_8197F(x) (((x) >> BIT_SHIFT_PS_AID_1_8197F) & BIT_MASK_PS_AID_1_8197F) -#define BIT_SET_PS_AID_1_8197F(x, v) (BIT_CLEAR_PS_AID_1_8197F(x) | BIT_PS_AID_1_8197F(v)) - +#define BIT_GET_PS_AID_1_8197F(x) \ + (((x) >> BIT_SHIFT_PS_AID_1_8197F) & BIT_MASK_PS_AID_1_8197F) +#define BIT_SET_PS_AID_1_8197F(x, v) \ + (BIT_CLEAR_PS_AID_1_8197F(x) | BIT_PS_AID_1_8197F(v)) /* 2 REG_ASSOCIATED_BFMEE_SEL_8197F */ #define BIT_TXUSER_ID1_8197F BIT(25) @@ -12136,7 +15977,8 @@ #define BIT_AID1_8197F(x) (((x) & BIT_MASK_AID1_8197F) << BIT_SHIFT_AID1_8197F) #define BITS_AID1_8197F (BIT_MASK_AID1_8197F << BIT_SHIFT_AID1_8197F) #define BIT_CLEAR_AID1_8197F(x) ((x) & (~BITS_AID1_8197F)) -#define BIT_GET_AID1_8197F(x) (((x) >> BIT_SHIFT_AID1_8197F) & BIT_MASK_AID1_8197F) +#define BIT_GET_AID1_8197F(x) \ + (((x) >> BIT_SHIFT_AID1_8197F) & BIT_MASK_AID1_8197F) #define BIT_SET_AID1_8197F(x, v) (BIT_CLEAR_AID1_8197F(x) | BIT_AID1_8197F(v)) #define BIT_TXUSER_ID0_8197F BIT(9) @@ -12146,37 +15988,60 @@ #define BIT_AID0_8197F(x) (((x) & BIT_MASK_AID0_8197F) << BIT_SHIFT_AID0_8197F) #define BITS_AID0_8197F (BIT_MASK_AID0_8197F << BIT_SHIFT_AID0_8197F) #define BIT_CLEAR_AID0_8197F(x) ((x) & (~BITS_AID0_8197F)) -#define BIT_GET_AID0_8197F(x) (((x) >> BIT_SHIFT_AID0_8197F) & BIT_MASK_AID0_8197F) +#define BIT_GET_AID0_8197F(x) \ + (((x) >> BIT_SHIFT_AID0_8197F) & BIT_MASK_AID0_8197F) #define BIT_SET_AID0_8197F(x, v) (BIT_CLEAR_AID0_8197F(x) | BIT_AID0_8197F(v)) - /* 2 REG_SND_PTCL_CTRL_8197F */ #define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F 24 #define BIT_MASK_NDP_RX_STANDBY_TIMER_8197F 0xff -#define BIT_NDP_RX_STANDBY_TIMER_8197F(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8197F) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) -#define BITS_NDP_RX_STANDBY_TIMER_8197F (BIT_MASK_NDP_RX_STANDBY_TIMER_8197F << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) -#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8197F)) -#define BIT_GET_NDP_RX_STANDBY_TIMER_8197F(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) & BIT_MASK_NDP_RX_STANDBY_TIMER_8197F) -#define BIT_SET_NDP_RX_STANDBY_TIMER_8197F(x, v) (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) | BIT_NDP_RX_STANDBY_TIMER_8197F(v)) - +#define BIT_NDP_RX_STANDBY_TIMER_8197F(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8197F) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) +#define BITS_NDP_RX_STANDBY_TIMER_8197F \ + (BIT_MASK_NDP_RX_STANDBY_TIMER_8197F \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) \ + ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8197F)) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER_8197F) +#define BIT_SET_NDP_RX_STANDBY_TIMER_8197F(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) | \ + BIT_NDP_RX_STANDBY_TIMER_8197F(v)) #define BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F 16 #define BIT_MASK_CSI_RPT_OFFSET_HT_8197F 0xff -#define BIT_CSI_RPT_OFFSET_HT_8197F(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8197F) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) -#define BITS_CSI_RPT_OFFSET_HT_8197F (BIT_MASK_CSI_RPT_OFFSET_HT_8197F << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) -#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT_8197F)) -#define BIT_GET_CSI_RPT_OFFSET_HT_8197F(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) & BIT_MASK_CSI_RPT_OFFSET_HT_8197F) -#define BIT_SET_CSI_RPT_OFFSET_HT_8197F(x, v) (BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) | BIT_CSI_RPT_OFFSET_HT_8197F(v)) - +#define BIT_CSI_RPT_OFFSET_HT_8197F(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8197F) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) +#define BITS_CSI_RPT_OFFSET_HT_8197F \ + (BIT_MASK_CSI_RPT_OFFSET_HT_8197F << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_HT_8197F)) +#define BIT_GET_CSI_RPT_OFFSET_HT_8197F(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_8197F) +#define BIT_SET_CSI_RPT_OFFSET_HT_8197F(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) | BIT_CSI_RPT_OFFSET_HT_8197F(v)) #define BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F 8 #define BIT_MASK_CSI_RPT_OFFSET_VHT_8197F 0xff -#define BIT_CSI_RPT_OFFSET_VHT_8197F(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_8197F) << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) -#define BITS_CSI_RPT_OFFSET_VHT_8197F (BIT_MASK_CSI_RPT_OFFSET_VHT_8197F << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) -#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT_8197F)) -#define BIT_GET_CSI_RPT_OFFSET_VHT_8197F(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) & BIT_MASK_CSI_RPT_OFFSET_VHT_8197F) -#define BIT_SET_CSI_RPT_OFFSET_VHT_8197F(x, v) (BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) | BIT_CSI_RPT_OFFSET_VHT_8197F(v)) +#define BIT_CSI_RPT_OFFSET_VHT_8197F(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_8197F) \ + << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) +#define BITS_CSI_RPT_OFFSET_VHT_8197F \ + (BIT_MASK_CSI_RPT_OFFSET_VHT_8197F \ + << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) +#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_VHT_8197F)) +#define BIT_GET_CSI_RPT_OFFSET_VHT_8197F(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) & \ + BIT_MASK_CSI_RPT_OFFSET_VHT_8197F) +#define BIT_SET_CSI_RPT_OFFSET_VHT_8197F(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) | \ + BIT_CSI_RPT_OFFSET_VHT_8197F(v)) #define BIT_R_WMAC_USE_NSTS_8197F BIT(7) #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8197F BIT(6) @@ -12196,30 +16061,54 @@ #define BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F 6 #define BIT_MASK_R_WMAC_NSARP_MODEN_8197F 0x3 -#define BIT_R_WMAC_NSARP_MODEN_8197F(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8197F) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) -#define BITS_R_WMAC_NSARP_MODEN_8197F (BIT_MASK_R_WMAC_NSARP_MODEN_8197F << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) -#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) ((x) & (~BITS_R_WMAC_NSARP_MODEN_8197F)) -#define BIT_GET_R_WMAC_NSARP_MODEN_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) & BIT_MASK_R_WMAC_NSARP_MODEN_8197F) -#define BIT_SET_R_WMAC_NSARP_MODEN_8197F(x, v) (BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) | BIT_R_WMAC_NSARP_MODEN_8197F(v)) - +#define BIT_R_WMAC_NSARP_MODEN_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8197F) \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) +#define BITS_R_WMAC_NSARP_MODEN_8197F \ + (BIT_MASK_R_WMAC_NSARP_MODEN_8197F \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) \ + ((x) & (~BITS_R_WMAC_NSARP_MODEN_8197F)) +#define BIT_GET_R_WMAC_NSARP_MODEN_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) & \ + BIT_MASK_R_WMAC_NSARP_MODEN_8197F) +#define BIT_SET_R_WMAC_NSARP_MODEN_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) | \ + BIT_R_WMAC_NSARP_MODEN_8197F(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F 4 #define BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F 0x3 -#define BIT_R_WMAC_NSARP_RSPFTP_8197F(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) -#define BITS_R_WMAC_NSARP_RSPFTP_8197F (BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) -#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8197F)) -#define BIT_GET_R_WMAC_NSARP_RSPFTP_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F) -#define BIT_SET_R_WMAC_NSARP_RSPFTP_8197F(x, v) (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) | BIT_R_WMAC_NSARP_RSPFTP_8197F(v)) - +#define BIT_R_WMAC_NSARP_RSPFTP_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) +#define BITS_R_WMAC_NSARP_RSPFTP_8197F \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8197F)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) & \ + BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F) +#define BIT_SET_R_WMAC_NSARP_RSPFTP_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) | \ + BIT_R_WMAC_NSARP_RSPFTP_8197F(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F 0 #define BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F 0xf -#define BIT_R_WMAC_NSARP_RSPSEC_8197F(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) -#define BITS_R_WMAC_NSARP_RSPSEC_8197F (BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) -#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8197F)) -#define BIT_GET_R_WMAC_NSARP_RSPSEC_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F) -#define BIT_SET_R_WMAC_NSARP_RSPSEC_8197F(x, v) (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) | BIT_R_WMAC_NSARP_RSPSEC_8197F(v)) - +#define BIT_R_WMAC_NSARP_RSPSEC_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) +#define BITS_R_WMAC_NSARP_RSPSEC_8197F \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8197F)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) & \ + BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F) +#define BIT_SET_R_WMAC_NSARP_RSPSEC_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) | \ + BIT_R_WMAC_NSARP_RSPSEC_8197F(v)) /* 2 REG_NS_ARP_INFO_8197F */ @@ -12235,21 +16124,37 @@ #define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F 4 #define BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F 0xf -#define BIT_R_WMAC_CTX_SUBTYPE_8197F(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) -#define BITS_R_WMAC_CTX_SUBTYPE_8197F (BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) -#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8197F)) -#define BIT_GET_R_WMAC_CTX_SUBTYPE_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F) -#define BIT_SET_R_WMAC_CTX_SUBTYPE_8197F(x, v) (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) | BIT_R_WMAC_CTX_SUBTYPE_8197F(v)) - +#define BIT_R_WMAC_CTX_SUBTYPE_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F) \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) +#define BITS_R_WMAC_CTX_SUBTYPE_8197F \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) \ + ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8197F)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) & \ + BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F) +#define BIT_SET_R_WMAC_CTX_SUBTYPE_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) | \ + BIT_R_WMAC_CTX_SUBTYPE_8197F(v)) #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F 0 #define BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F 0xf -#define BIT_R_WMAC_RTX_SUBTYPE_8197F(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) -#define BITS_R_WMAC_RTX_SUBTYPE_8197F (BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) -#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8197F)) -#define BIT_GET_R_WMAC_RTX_SUBTYPE_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F) -#define BIT_SET_R_WMAC_RTX_SUBTYPE_8197F(x, v) (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) | BIT_R_WMAC_RTX_SUBTYPE_8197F(v)) - +#define BIT_R_WMAC_RTX_SUBTYPE_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F) \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) +#define BITS_R_WMAC_RTX_SUBTYPE_8197F \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) \ + ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8197F)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) & \ + BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F) +#define BIT_SET_R_WMAC_RTX_SUBTYPE_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) | \ + BIT_R_WMAC_RTX_SUBTYPE_8197F(v)) /* 2 REG_WMAC_SWAES_CFG_8197F */ @@ -12259,12 +16164,14 @@ #define BIT_SHIFT_TIMER_8197F 0 #define BIT_MASK_TIMER_8197F 0xff -#define BIT_TIMER_8197F(x) (((x) & BIT_MASK_TIMER_8197F) << BIT_SHIFT_TIMER_8197F) +#define BIT_TIMER_8197F(x) \ + (((x) & BIT_MASK_TIMER_8197F) << BIT_SHIFT_TIMER_8197F) #define BITS_TIMER_8197F (BIT_MASK_TIMER_8197F << BIT_SHIFT_TIMER_8197F) #define BIT_CLEAR_TIMER_8197F(x) ((x) & (~BITS_TIMER_8197F)) -#define BIT_GET_TIMER_8197F(x) (((x) >> BIT_SHIFT_TIMER_8197F) & BIT_MASK_TIMER_8197F) -#define BIT_SET_TIMER_8197F(x, v) (BIT_CLEAR_TIMER_8197F(x) | BIT_TIMER_8197F(v)) - +#define BIT_GET_TIMER_8197F(x) \ + (((x) >> BIT_SHIFT_TIMER_8197F) & BIT_MASK_TIMER_8197F) +#define BIT_SET_TIMER_8197F(x, v) \ + (BIT_CLEAR_TIMER_8197F(x) | BIT_TIMER_8197F(v)) /* 2 REG_BT_COEX_8197F */ #define BIT_R_GNT_BT_RFC_SW_8197F BIT(12) @@ -12275,12 +16182,15 @@ #define BIT_SHIFT_R_BT_CNT_THR_8197F 0 #define BIT_MASK_R_BT_CNT_THR_8197F 0xff -#define BIT_R_BT_CNT_THR_8197F(x) (((x) & BIT_MASK_R_BT_CNT_THR_8197F) << BIT_SHIFT_R_BT_CNT_THR_8197F) -#define BITS_R_BT_CNT_THR_8197F (BIT_MASK_R_BT_CNT_THR_8197F << BIT_SHIFT_R_BT_CNT_THR_8197F) +#define BIT_R_BT_CNT_THR_8197F(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR_8197F) << BIT_SHIFT_R_BT_CNT_THR_8197F) +#define BITS_R_BT_CNT_THR_8197F \ + (BIT_MASK_R_BT_CNT_THR_8197F << BIT_SHIFT_R_BT_CNT_THR_8197F) #define BIT_CLEAR_R_BT_CNT_THR_8197F(x) ((x) & (~BITS_R_BT_CNT_THR_8197F)) -#define BIT_GET_R_BT_CNT_THR_8197F(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8197F) & BIT_MASK_R_BT_CNT_THR_8197F) -#define BIT_SET_R_BT_CNT_THR_8197F(x, v) (BIT_CLEAR_R_BT_CNT_THR_8197F(x) | BIT_R_BT_CNT_THR_8197F(v)) - +#define BIT_GET_R_BT_CNT_THR_8197F(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR_8197F) & BIT_MASK_R_BT_CNT_THR_8197F) +#define BIT_SET_R_BT_CNT_THR_8197F(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR_8197F(x) | BIT_R_BT_CNT_THR_8197F(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_8197F */ #define BIT_WLRX_TER_BY_CTL_8197F BIT(43) @@ -12292,49 +16202,75 @@ #define BIT_SHIFT_RXMYRTS_NAV_V1_8197F 8 #define BIT_MASK_RXMYRTS_NAV_V1_8197F 0xff -#define BIT_RXMYRTS_NAV_V1_8197F(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8197F) << BIT_SHIFT_RXMYRTS_NAV_V1_8197F) -#define BITS_RXMYRTS_NAV_V1_8197F (BIT_MASK_RXMYRTS_NAV_V1_8197F << BIT_SHIFT_RXMYRTS_NAV_V1_8197F) +#define BIT_RXMYRTS_NAV_V1_8197F(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1_8197F) \ + << BIT_SHIFT_RXMYRTS_NAV_V1_8197F) +#define BITS_RXMYRTS_NAV_V1_8197F \ + (BIT_MASK_RXMYRTS_NAV_V1_8197F << BIT_SHIFT_RXMYRTS_NAV_V1_8197F) #define BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8197F)) -#define BIT_GET_RXMYRTS_NAV_V1_8197F(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8197F) & BIT_MASK_RXMYRTS_NAV_V1_8197F) -#define BIT_SET_RXMYRTS_NAV_V1_8197F(x, v) (BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) | BIT_RXMYRTS_NAV_V1_8197F(v)) - +#define BIT_GET_RXMYRTS_NAV_V1_8197F(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8197F) & \ + BIT_MASK_RXMYRTS_NAV_V1_8197F) +#define BIT_SET_RXMYRTS_NAV_V1_8197F(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) | BIT_RXMYRTS_NAV_V1_8197F(v)) #define BIT_SHIFT_RTSRST_V1_8197F 0 #define BIT_MASK_RTSRST_V1_8197F 0xff -#define BIT_RTSRST_V1_8197F(x) (((x) & BIT_MASK_RTSRST_V1_8197F) << BIT_SHIFT_RTSRST_V1_8197F) -#define BITS_RTSRST_V1_8197F (BIT_MASK_RTSRST_V1_8197F << BIT_SHIFT_RTSRST_V1_8197F) +#define BIT_RTSRST_V1_8197F(x) \ + (((x) & BIT_MASK_RTSRST_V1_8197F) << BIT_SHIFT_RTSRST_V1_8197F) +#define BITS_RTSRST_V1_8197F \ + (BIT_MASK_RTSRST_V1_8197F << BIT_SHIFT_RTSRST_V1_8197F) #define BIT_CLEAR_RTSRST_V1_8197F(x) ((x) & (~BITS_RTSRST_V1_8197F)) -#define BIT_GET_RTSRST_V1_8197F(x) (((x) >> BIT_SHIFT_RTSRST_V1_8197F) & BIT_MASK_RTSRST_V1_8197F) -#define BIT_SET_RTSRST_V1_8197F(x, v) (BIT_CLEAR_RTSRST_V1_8197F(x) | BIT_RTSRST_V1_8197F(v)) - +#define BIT_GET_RTSRST_V1_8197F(x) \ + (((x) >> BIT_SHIFT_RTSRST_V1_8197F) & BIT_MASK_RTSRST_V1_8197F) +#define BIT_SET_RTSRST_V1_8197F(x, v) \ + (BIT_CLEAR_RTSRST_V1_8197F(x) | BIT_RTSRST_V1_8197F(v)) /* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8197F */ #define BIT_SHIFT_BT_STAT_DELAY_8197F 12 #define BIT_MASK_BT_STAT_DELAY_8197F 0xf -#define BIT_BT_STAT_DELAY_8197F(x) (((x) & BIT_MASK_BT_STAT_DELAY_8197F) << BIT_SHIFT_BT_STAT_DELAY_8197F) -#define BITS_BT_STAT_DELAY_8197F (BIT_MASK_BT_STAT_DELAY_8197F << BIT_SHIFT_BT_STAT_DELAY_8197F) +#define BIT_BT_STAT_DELAY_8197F(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY_8197F) << BIT_SHIFT_BT_STAT_DELAY_8197F) +#define BITS_BT_STAT_DELAY_8197F \ + (BIT_MASK_BT_STAT_DELAY_8197F << BIT_SHIFT_BT_STAT_DELAY_8197F) #define BIT_CLEAR_BT_STAT_DELAY_8197F(x) ((x) & (~BITS_BT_STAT_DELAY_8197F)) -#define BIT_GET_BT_STAT_DELAY_8197F(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8197F) & BIT_MASK_BT_STAT_DELAY_8197F) -#define BIT_SET_BT_STAT_DELAY_8197F(x, v) (BIT_CLEAR_BT_STAT_DELAY_8197F(x) | BIT_BT_STAT_DELAY_8197F(v)) - +#define BIT_GET_BT_STAT_DELAY_8197F(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY_8197F) & BIT_MASK_BT_STAT_DELAY_8197F) +#define BIT_SET_BT_STAT_DELAY_8197F(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY_8197F(x) | BIT_BT_STAT_DELAY_8197F(v)) #define BIT_SHIFT_BT_TRX_INIT_DETECT_8197F 8 #define BIT_MASK_BT_TRX_INIT_DETECT_8197F 0xf -#define BIT_BT_TRX_INIT_DETECT_8197F(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8197F) << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) -#define BITS_BT_TRX_INIT_DETECT_8197F (BIT_MASK_BT_TRX_INIT_DETECT_8197F << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) -#define BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) ((x) & (~BITS_BT_TRX_INIT_DETECT_8197F)) -#define BIT_GET_BT_TRX_INIT_DETECT_8197F(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) & BIT_MASK_BT_TRX_INIT_DETECT_8197F) -#define BIT_SET_BT_TRX_INIT_DETECT_8197F(x, v) (BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) | BIT_BT_TRX_INIT_DETECT_8197F(v)) - +#define BIT_BT_TRX_INIT_DETECT_8197F(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8197F) \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) +#define BITS_BT_TRX_INIT_DETECT_8197F \ + (BIT_MASK_BT_TRX_INIT_DETECT_8197F \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) +#define BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) \ + ((x) & (~BITS_BT_TRX_INIT_DETECT_8197F)) +#define BIT_GET_BT_TRX_INIT_DETECT_8197F(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) & \ + BIT_MASK_BT_TRX_INIT_DETECT_8197F) +#define BIT_SET_BT_TRX_INIT_DETECT_8197F(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) | \ + BIT_BT_TRX_INIT_DETECT_8197F(v)) #define BIT_SHIFT_BT_PRI_DETECT_TO_8197F 4 #define BIT_MASK_BT_PRI_DETECT_TO_8197F 0xf -#define BIT_BT_PRI_DETECT_TO_8197F(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8197F) << BIT_SHIFT_BT_PRI_DETECT_TO_8197F) -#define BITS_BT_PRI_DETECT_TO_8197F (BIT_MASK_BT_PRI_DETECT_TO_8197F << BIT_SHIFT_BT_PRI_DETECT_TO_8197F) -#define BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) ((x) & (~BITS_BT_PRI_DETECT_TO_8197F)) -#define BIT_GET_BT_PRI_DETECT_TO_8197F(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8197F) & BIT_MASK_BT_PRI_DETECT_TO_8197F) -#define BIT_SET_BT_PRI_DETECT_TO_8197F(x, v) (BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) | BIT_BT_PRI_DETECT_TO_8197F(v)) +#define BIT_BT_PRI_DETECT_TO_8197F(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO_8197F) \ + << BIT_SHIFT_BT_PRI_DETECT_TO_8197F) +#define BITS_BT_PRI_DETECT_TO_8197F \ + (BIT_MASK_BT_PRI_DETECT_TO_8197F << BIT_SHIFT_BT_PRI_DETECT_TO_8197F) +#define BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) \ + ((x) & (~BITS_BT_PRI_DETECT_TO_8197F)) +#define BIT_GET_BT_PRI_DETECT_TO_8197F(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8197F) & \ + BIT_MASK_BT_PRI_DETECT_TO_8197F) +#define BIT_SET_BT_PRI_DETECT_TO_8197F(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) | BIT_BT_PRI_DETECT_TO_8197F(v)) #define BIT_R_GRANTALL_WLMASK_8197F BIT(3) #define BIT_STATIS_BT_EN_8197F BIT(2) @@ -12345,67 +16281,99 @@ #define BIT_SHIFT_STATIS_BT_LO_RX_8197F (48 & CPU_OPT_WIDTH) #define BIT_MASK_STATIS_BT_LO_RX_8197F 0xffff -#define BIT_STATIS_BT_LO_RX_8197F(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_8197F) << BIT_SHIFT_STATIS_BT_LO_RX_8197F) -#define BITS_STATIS_BT_LO_RX_8197F (BIT_MASK_STATIS_BT_LO_RX_8197F << BIT_SHIFT_STATIS_BT_LO_RX_8197F) +#define BIT_STATIS_BT_LO_RX_8197F(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_8197F) \ + << BIT_SHIFT_STATIS_BT_LO_RX_8197F) +#define BITS_STATIS_BT_LO_RX_8197F \ + (BIT_MASK_STATIS_BT_LO_RX_8197F << BIT_SHIFT_STATIS_BT_LO_RX_8197F) #define BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_RX_8197F)) -#define BIT_GET_STATIS_BT_LO_RX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8197F) & BIT_MASK_STATIS_BT_LO_RX_8197F) -#define BIT_SET_STATIS_BT_LO_RX_8197F(x, v) (BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) | BIT_STATIS_BT_LO_RX_8197F(v)) - +#define BIT_GET_STATIS_BT_LO_RX_8197F(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8197F) & \ + BIT_MASK_STATIS_BT_LO_RX_8197F) +#define BIT_SET_STATIS_BT_LO_RX_8197F(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) | BIT_STATIS_BT_LO_RX_8197F(v)) #define BIT_SHIFT_STATIS_BT_LO_TX_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_STATIS_BT_LO_TX_8197F 0xffff -#define BIT_STATIS_BT_LO_TX_8197F(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_8197F) << BIT_SHIFT_STATIS_BT_LO_TX_8197F) -#define BITS_STATIS_BT_LO_TX_8197F (BIT_MASK_STATIS_BT_LO_TX_8197F << BIT_SHIFT_STATIS_BT_LO_TX_8197F) +#define BIT_STATIS_BT_LO_TX_8197F(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_8197F) \ + << BIT_SHIFT_STATIS_BT_LO_TX_8197F) +#define BITS_STATIS_BT_LO_TX_8197F \ + (BIT_MASK_STATIS_BT_LO_TX_8197F << BIT_SHIFT_STATIS_BT_LO_TX_8197F) #define BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_TX_8197F)) -#define BIT_GET_STATIS_BT_LO_TX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8197F) & BIT_MASK_STATIS_BT_LO_TX_8197F) -#define BIT_SET_STATIS_BT_LO_TX_8197F(x, v) (BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) | BIT_STATIS_BT_LO_TX_8197F(v)) - +#define BIT_GET_STATIS_BT_LO_TX_8197F(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8197F) & \ + BIT_MASK_STATIS_BT_LO_TX_8197F) +#define BIT_SET_STATIS_BT_LO_TX_8197F(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) | BIT_STATIS_BT_LO_TX_8197F(v)) #define BIT_SHIFT_STATIS_BT_HI_RX_8197F 16 #define BIT_MASK_STATIS_BT_HI_RX_8197F 0xffff -#define BIT_STATIS_BT_HI_RX_8197F(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8197F) << BIT_SHIFT_STATIS_BT_HI_RX_8197F) -#define BITS_STATIS_BT_HI_RX_8197F (BIT_MASK_STATIS_BT_HI_RX_8197F << BIT_SHIFT_STATIS_BT_HI_RX_8197F) +#define BIT_STATIS_BT_HI_RX_8197F(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX_8197F) \ + << BIT_SHIFT_STATIS_BT_HI_RX_8197F) +#define BITS_STATIS_BT_HI_RX_8197F \ + (BIT_MASK_STATIS_BT_HI_RX_8197F << BIT_SHIFT_STATIS_BT_HI_RX_8197F) #define BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_RX_8197F)) -#define BIT_GET_STATIS_BT_HI_RX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8197F) & BIT_MASK_STATIS_BT_HI_RX_8197F) -#define BIT_SET_STATIS_BT_HI_RX_8197F(x, v) (BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) | BIT_STATIS_BT_HI_RX_8197F(v)) - +#define BIT_GET_STATIS_BT_HI_RX_8197F(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8197F) & \ + BIT_MASK_STATIS_BT_HI_RX_8197F) +#define BIT_SET_STATIS_BT_HI_RX_8197F(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) | BIT_STATIS_BT_HI_RX_8197F(v)) #define BIT_SHIFT_STATIS_BT_HI_TX_8197F 0 #define BIT_MASK_STATIS_BT_HI_TX_8197F 0xffff -#define BIT_STATIS_BT_HI_TX_8197F(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8197F) << BIT_SHIFT_STATIS_BT_HI_TX_8197F) -#define BITS_STATIS_BT_HI_TX_8197F (BIT_MASK_STATIS_BT_HI_TX_8197F << BIT_SHIFT_STATIS_BT_HI_TX_8197F) +#define BIT_STATIS_BT_HI_TX_8197F(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX_8197F) \ + << BIT_SHIFT_STATIS_BT_HI_TX_8197F) +#define BITS_STATIS_BT_HI_TX_8197F \ + (BIT_MASK_STATIS_BT_HI_TX_8197F << BIT_SHIFT_STATIS_BT_HI_TX_8197F) #define BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_TX_8197F)) -#define BIT_GET_STATIS_BT_HI_TX_8197F(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8197F) & BIT_MASK_STATIS_BT_HI_TX_8197F) -#define BIT_SET_STATIS_BT_HI_TX_8197F(x, v) (BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) | BIT_STATIS_BT_HI_TX_8197F(v)) - +#define BIT_GET_STATIS_BT_HI_TX_8197F(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8197F) & \ + BIT_MASK_STATIS_BT_HI_TX_8197F) +#define BIT_SET_STATIS_BT_HI_TX_8197F(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) | BIT_STATIS_BT_HI_TX_8197F(v)) /* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8197F */ #define BIT_SHIFT_R_BT_CMD_RPT_8197F 16 #define BIT_MASK_R_BT_CMD_RPT_8197F 0xffff -#define BIT_R_BT_CMD_RPT_8197F(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8197F) << BIT_SHIFT_R_BT_CMD_RPT_8197F) -#define BITS_R_BT_CMD_RPT_8197F (BIT_MASK_R_BT_CMD_RPT_8197F << BIT_SHIFT_R_BT_CMD_RPT_8197F) +#define BIT_R_BT_CMD_RPT_8197F(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT_8197F) << BIT_SHIFT_R_BT_CMD_RPT_8197F) +#define BITS_R_BT_CMD_RPT_8197F \ + (BIT_MASK_R_BT_CMD_RPT_8197F << BIT_SHIFT_R_BT_CMD_RPT_8197F) #define BIT_CLEAR_R_BT_CMD_RPT_8197F(x) ((x) & (~BITS_R_BT_CMD_RPT_8197F)) -#define BIT_GET_R_BT_CMD_RPT_8197F(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8197F) & BIT_MASK_R_BT_CMD_RPT_8197F) -#define BIT_SET_R_BT_CMD_RPT_8197F(x, v) (BIT_CLEAR_R_BT_CMD_RPT_8197F(x) | BIT_R_BT_CMD_RPT_8197F(v)) - +#define BIT_GET_R_BT_CMD_RPT_8197F(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8197F) & BIT_MASK_R_BT_CMD_RPT_8197F) +#define BIT_SET_R_BT_CMD_RPT_8197F(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT_8197F(x) | BIT_R_BT_CMD_RPT_8197F(v)) #define BIT_SHIFT_R_RPT_FROM_BT_8197F 8 #define BIT_MASK_R_RPT_FROM_BT_8197F 0xff -#define BIT_R_RPT_FROM_BT_8197F(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8197F) << BIT_SHIFT_R_RPT_FROM_BT_8197F) -#define BITS_R_RPT_FROM_BT_8197F (BIT_MASK_R_RPT_FROM_BT_8197F << BIT_SHIFT_R_RPT_FROM_BT_8197F) +#define BIT_R_RPT_FROM_BT_8197F(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT_8197F) << BIT_SHIFT_R_RPT_FROM_BT_8197F) +#define BITS_R_RPT_FROM_BT_8197F \ + (BIT_MASK_R_RPT_FROM_BT_8197F << BIT_SHIFT_R_RPT_FROM_BT_8197F) #define BIT_CLEAR_R_RPT_FROM_BT_8197F(x) ((x) & (~BITS_R_RPT_FROM_BT_8197F)) -#define BIT_GET_R_RPT_FROM_BT_8197F(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8197F) & BIT_MASK_R_RPT_FROM_BT_8197F) -#define BIT_SET_R_RPT_FROM_BT_8197F(x, v) (BIT_CLEAR_R_RPT_FROM_BT_8197F(x) | BIT_R_RPT_FROM_BT_8197F(v)) - +#define BIT_GET_R_RPT_FROM_BT_8197F(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8197F) & BIT_MASK_R_RPT_FROM_BT_8197F) +#define BIT_SET_R_RPT_FROM_BT_8197F(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT_8197F(x) | BIT_R_RPT_FROM_BT_8197F(v)) #define BIT_SHIFT_BT_HID_ISR_SET_8197F 6 #define BIT_MASK_BT_HID_ISR_SET_8197F 0x3 -#define BIT_BT_HID_ISR_SET_8197F(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8197F) << BIT_SHIFT_BT_HID_ISR_SET_8197F) -#define BITS_BT_HID_ISR_SET_8197F (BIT_MASK_BT_HID_ISR_SET_8197F << BIT_SHIFT_BT_HID_ISR_SET_8197F) +#define BIT_BT_HID_ISR_SET_8197F(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET_8197F) \ + << BIT_SHIFT_BT_HID_ISR_SET_8197F) +#define BITS_BT_HID_ISR_SET_8197F \ + (BIT_MASK_BT_HID_ISR_SET_8197F << BIT_SHIFT_BT_HID_ISR_SET_8197F) #define BIT_CLEAR_BT_HID_ISR_SET_8197F(x) ((x) & (~BITS_BT_HID_ISR_SET_8197F)) -#define BIT_GET_BT_HID_ISR_SET_8197F(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8197F) & BIT_MASK_BT_HID_ISR_SET_8197F) -#define BIT_SET_BT_HID_ISR_SET_8197F(x, v) (BIT_CLEAR_BT_HID_ISR_SET_8197F(x) | BIT_BT_HID_ISR_SET_8197F(v)) +#define BIT_GET_BT_HID_ISR_SET_8197F(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8197F) & \ + BIT_MASK_BT_HID_ISR_SET_8197F) +#define BIT_SET_BT_HID_ISR_SET_8197F(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET_8197F(x) | BIT_BT_HID_ISR_SET_8197F(v)) #define BIT_TDMA_BT_START_NOTIFY_8197F BIT(5) #define BIT_ENABLE_TDMA_FW_MODE_8197F BIT(4) @@ -12418,39 +16386,54 @@ #define BIT_SHIFT_BT_PROFILE_8197F 24 #define BIT_MASK_BT_PROFILE_8197F 0xff -#define BIT_BT_PROFILE_8197F(x) (((x) & BIT_MASK_BT_PROFILE_8197F) << BIT_SHIFT_BT_PROFILE_8197F) -#define BITS_BT_PROFILE_8197F (BIT_MASK_BT_PROFILE_8197F << BIT_SHIFT_BT_PROFILE_8197F) +#define BIT_BT_PROFILE_8197F(x) \ + (((x) & BIT_MASK_BT_PROFILE_8197F) << BIT_SHIFT_BT_PROFILE_8197F) +#define BITS_BT_PROFILE_8197F \ + (BIT_MASK_BT_PROFILE_8197F << BIT_SHIFT_BT_PROFILE_8197F) #define BIT_CLEAR_BT_PROFILE_8197F(x) ((x) & (~BITS_BT_PROFILE_8197F)) -#define BIT_GET_BT_PROFILE_8197F(x) (((x) >> BIT_SHIFT_BT_PROFILE_8197F) & BIT_MASK_BT_PROFILE_8197F) -#define BIT_SET_BT_PROFILE_8197F(x, v) (BIT_CLEAR_BT_PROFILE_8197F(x) | BIT_BT_PROFILE_8197F(v)) - +#define BIT_GET_BT_PROFILE_8197F(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE_8197F) & BIT_MASK_BT_PROFILE_8197F) +#define BIT_SET_BT_PROFILE_8197F(x, v) \ + (BIT_CLEAR_BT_PROFILE_8197F(x) | BIT_BT_PROFILE_8197F(v)) #define BIT_SHIFT_BT_POWER_8197F 16 #define BIT_MASK_BT_POWER_8197F 0xff -#define BIT_BT_POWER_8197F(x) (((x) & BIT_MASK_BT_POWER_8197F) << BIT_SHIFT_BT_POWER_8197F) -#define BITS_BT_POWER_8197F (BIT_MASK_BT_POWER_8197F << BIT_SHIFT_BT_POWER_8197F) +#define BIT_BT_POWER_8197F(x) \ + (((x) & BIT_MASK_BT_POWER_8197F) << BIT_SHIFT_BT_POWER_8197F) +#define BITS_BT_POWER_8197F \ + (BIT_MASK_BT_POWER_8197F << BIT_SHIFT_BT_POWER_8197F) #define BIT_CLEAR_BT_POWER_8197F(x) ((x) & (~BITS_BT_POWER_8197F)) -#define BIT_GET_BT_POWER_8197F(x) (((x) >> BIT_SHIFT_BT_POWER_8197F) & BIT_MASK_BT_POWER_8197F) -#define BIT_SET_BT_POWER_8197F(x, v) (BIT_CLEAR_BT_POWER_8197F(x) | BIT_BT_POWER_8197F(v)) - +#define BIT_GET_BT_POWER_8197F(x) \ + (((x) >> BIT_SHIFT_BT_POWER_8197F) & BIT_MASK_BT_POWER_8197F) +#define BIT_SET_BT_POWER_8197F(x, v) \ + (BIT_CLEAR_BT_POWER_8197F(x) | BIT_BT_POWER_8197F(v)) #define BIT_SHIFT_BT_PREDECT_STATUS_8197F 8 #define BIT_MASK_BT_PREDECT_STATUS_8197F 0xff -#define BIT_BT_PREDECT_STATUS_8197F(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8197F) << BIT_SHIFT_BT_PREDECT_STATUS_8197F) -#define BITS_BT_PREDECT_STATUS_8197F (BIT_MASK_BT_PREDECT_STATUS_8197F << BIT_SHIFT_BT_PREDECT_STATUS_8197F) -#define BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) ((x) & (~BITS_BT_PREDECT_STATUS_8197F)) -#define BIT_GET_BT_PREDECT_STATUS_8197F(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8197F) & BIT_MASK_BT_PREDECT_STATUS_8197F) -#define BIT_SET_BT_PREDECT_STATUS_8197F(x, v) (BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) | BIT_BT_PREDECT_STATUS_8197F(v)) - +#define BIT_BT_PREDECT_STATUS_8197F(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS_8197F) \ + << BIT_SHIFT_BT_PREDECT_STATUS_8197F) +#define BITS_BT_PREDECT_STATUS_8197F \ + (BIT_MASK_BT_PREDECT_STATUS_8197F << BIT_SHIFT_BT_PREDECT_STATUS_8197F) +#define BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) \ + ((x) & (~BITS_BT_PREDECT_STATUS_8197F)) +#define BIT_GET_BT_PREDECT_STATUS_8197F(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8197F) & \ + BIT_MASK_BT_PREDECT_STATUS_8197F) +#define BIT_SET_BT_PREDECT_STATUS_8197F(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) | BIT_BT_PREDECT_STATUS_8197F(v)) #define BIT_SHIFT_BT_CMD_INFO_8197F 0 #define BIT_MASK_BT_CMD_INFO_8197F 0xff -#define BIT_BT_CMD_INFO_8197F(x) (((x) & BIT_MASK_BT_CMD_INFO_8197F) << BIT_SHIFT_BT_CMD_INFO_8197F) -#define BITS_BT_CMD_INFO_8197F (BIT_MASK_BT_CMD_INFO_8197F << BIT_SHIFT_BT_CMD_INFO_8197F) +#define BIT_BT_CMD_INFO_8197F(x) \ + (((x) & BIT_MASK_BT_CMD_INFO_8197F) << BIT_SHIFT_BT_CMD_INFO_8197F) +#define BITS_BT_CMD_INFO_8197F \ + (BIT_MASK_BT_CMD_INFO_8197F << BIT_SHIFT_BT_CMD_INFO_8197F) #define BIT_CLEAR_BT_CMD_INFO_8197F(x) ((x) & (~BITS_BT_CMD_INFO_8197F)) -#define BIT_GET_BT_CMD_INFO_8197F(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8197F) & BIT_MASK_BT_CMD_INFO_8197F) -#define BIT_SET_BT_CMD_INFO_8197F(x, v) (BIT_CLEAR_BT_CMD_INFO_8197F(x) | BIT_BT_CMD_INFO_8197F(v)) - +#define BIT_GET_BT_CMD_INFO_8197F(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO_8197F) & BIT_MASK_BT_CMD_INFO_8197F) +#define BIT_SET_BT_CMD_INFO_8197F(x, v) \ + (BIT_CLEAR_BT_CMD_INFO_8197F(x) | BIT_BT_CMD_INFO_8197F(v)) /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8197F */ #define BIT_EN_MAC_NULL_PKT_NOTIFY_8197F BIT(31) @@ -12464,51 +16447,65 @@ #define BIT_SHIFT_WLAN_RPT_DATA_8197F 16 #define BIT_MASK_WLAN_RPT_DATA_8197F 0xff -#define BIT_WLAN_RPT_DATA_8197F(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8197F) << BIT_SHIFT_WLAN_RPT_DATA_8197F) -#define BITS_WLAN_RPT_DATA_8197F (BIT_MASK_WLAN_RPT_DATA_8197F << BIT_SHIFT_WLAN_RPT_DATA_8197F) +#define BIT_WLAN_RPT_DATA_8197F(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA_8197F) << BIT_SHIFT_WLAN_RPT_DATA_8197F) +#define BITS_WLAN_RPT_DATA_8197F \ + (BIT_MASK_WLAN_RPT_DATA_8197F << BIT_SHIFT_WLAN_RPT_DATA_8197F) #define BIT_CLEAR_WLAN_RPT_DATA_8197F(x) ((x) & (~BITS_WLAN_RPT_DATA_8197F)) -#define BIT_GET_WLAN_RPT_DATA_8197F(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8197F) & BIT_MASK_WLAN_RPT_DATA_8197F) -#define BIT_SET_WLAN_RPT_DATA_8197F(x, v) (BIT_CLEAR_WLAN_RPT_DATA_8197F(x) | BIT_WLAN_RPT_DATA_8197F(v)) - +#define BIT_GET_WLAN_RPT_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8197F) & BIT_MASK_WLAN_RPT_DATA_8197F) +#define BIT_SET_WLAN_RPT_DATA_8197F(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA_8197F(x) | BIT_WLAN_RPT_DATA_8197F(v)) #define BIT_SHIFT_CMD_ID_8197F 8 #define BIT_MASK_CMD_ID_8197F 0xff -#define BIT_CMD_ID_8197F(x) (((x) & BIT_MASK_CMD_ID_8197F) << BIT_SHIFT_CMD_ID_8197F) +#define BIT_CMD_ID_8197F(x) \ + (((x) & BIT_MASK_CMD_ID_8197F) << BIT_SHIFT_CMD_ID_8197F) #define BITS_CMD_ID_8197F (BIT_MASK_CMD_ID_8197F << BIT_SHIFT_CMD_ID_8197F) #define BIT_CLEAR_CMD_ID_8197F(x) ((x) & (~BITS_CMD_ID_8197F)) -#define BIT_GET_CMD_ID_8197F(x) (((x) >> BIT_SHIFT_CMD_ID_8197F) & BIT_MASK_CMD_ID_8197F) -#define BIT_SET_CMD_ID_8197F(x, v) (BIT_CLEAR_CMD_ID_8197F(x) | BIT_CMD_ID_8197F(v)) - +#define BIT_GET_CMD_ID_8197F(x) \ + (((x) >> BIT_SHIFT_CMD_ID_8197F) & BIT_MASK_CMD_ID_8197F) +#define BIT_SET_CMD_ID_8197F(x, v) \ + (BIT_CLEAR_CMD_ID_8197F(x) | BIT_CMD_ID_8197F(v)) #define BIT_SHIFT_BT_DATA_8197F 0 #define BIT_MASK_BT_DATA_8197F 0xff -#define BIT_BT_DATA_8197F(x) (((x) & BIT_MASK_BT_DATA_8197F) << BIT_SHIFT_BT_DATA_8197F) +#define BIT_BT_DATA_8197F(x) \ + (((x) & BIT_MASK_BT_DATA_8197F) << BIT_SHIFT_BT_DATA_8197F) #define BITS_BT_DATA_8197F (BIT_MASK_BT_DATA_8197F << BIT_SHIFT_BT_DATA_8197F) #define BIT_CLEAR_BT_DATA_8197F(x) ((x) & (~BITS_BT_DATA_8197F)) -#define BIT_GET_BT_DATA_8197F(x) (((x) >> BIT_SHIFT_BT_DATA_8197F) & BIT_MASK_BT_DATA_8197F) -#define BIT_SET_BT_DATA_8197F(x, v) (BIT_CLEAR_BT_DATA_8197F(x) | BIT_BT_DATA_8197F(v)) - +#define BIT_GET_BT_DATA_8197F(x) \ + (((x) >> BIT_SHIFT_BT_DATA_8197F) & BIT_MASK_BT_DATA_8197F) +#define BIT_SET_BT_DATA_8197F(x, v) \ + (BIT_CLEAR_BT_DATA_8197F(x) | BIT_BT_DATA_8197F(v)) /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F */ #define BIT_SHIFT_WLAN_RPT_TO_8197F 0 #define BIT_MASK_WLAN_RPT_TO_8197F 0xff -#define BIT_WLAN_RPT_TO_8197F(x) (((x) & BIT_MASK_WLAN_RPT_TO_8197F) << BIT_SHIFT_WLAN_RPT_TO_8197F) -#define BITS_WLAN_RPT_TO_8197F (BIT_MASK_WLAN_RPT_TO_8197F << BIT_SHIFT_WLAN_RPT_TO_8197F) +#define BIT_WLAN_RPT_TO_8197F(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO_8197F) << BIT_SHIFT_WLAN_RPT_TO_8197F) +#define BITS_WLAN_RPT_TO_8197F \ + (BIT_MASK_WLAN_RPT_TO_8197F << BIT_SHIFT_WLAN_RPT_TO_8197F) #define BIT_CLEAR_WLAN_RPT_TO_8197F(x) ((x) & (~BITS_WLAN_RPT_TO_8197F)) -#define BIT_GET_WLAN_RPT_TO_8197F(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8197F) & BIT_MASK_WLAN_RPT_TO_8197F) -#define BIT_SET_WLAN_RPT_TO_8197F(x, v) (BIT_CLEAR_WLAN_RPT_TO_8197F(x) | BIT_WLAN_RPT_TO_8197F(v)) - +#define BIT_GET_WLAN_RPT_TO_8197F(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO_8197F) & BIT_MASK_WLAN_RPT_TO_8197F) +#define BIT_SET_WLAN_RPT_TO_8197F(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO_8197F(x) | BIT_WLAN_RPT_TO_8197F(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F */ #define BIT_SHIFT_ISOLATION_CHK_8197F 1 #define BIT_MASK_ISOLATION_CHK_8197F 0x7fffffffffffffffffffL -#define BIT_ISOLATION_CHK_8197F(x) (((x) & BIT_MASK_ISOLATION_CHK_8197F) << BIT_SHIFT_ISOLATION_CHK_8197F) -#define BITS_ISOLATION_CHK_8197F (BIT_MASK_ISOLATION_CHK_8197F << BIT_SHIFT_ISOLATION_CHK_8197F) +#define BIT_ISOLATION_CHK_8197F(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_8197F) << BIT_SHIFT_ISOLATION_CHK_8197F) +#define BITS_ISOLATION_CHK_8197F \ + (BIT_MASK_ISOLATION_CHK_8197F << BIT_SHIFT_ISOLATION_CHK_8197F) #define BIT_CLEAR_ISOLATION_CHK_8197F(x) ((x) & (~BITS_ISOLATION_CHK_8197F)) -#define BIT_GET_ISOLATION_CHK_8197F(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_8197F) & BIT_MASK_ISOLATION_CHK_8197F) -#define BIT_SET_ISOLATION_CHK_8197F(x, v) (BIT_CLEAR_ISOLATION_CHK_8197F(x) | BIT_ISOLATION_CHK_8197F(v)) +#define BIT_GET_ISOLATION_CHK_8197F(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_8197F) & BIT_MASK_ISOLATION_CHK_8197F) +#define BIT_SET_ISOLATION_CHK_8197F(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_8197F(x) | BIT_ISOLATION_CHK_8197F(v)) #define BIT_ISOLATION_EN_8197F BIT(0) @@ -12526,31 +16523,45 @@ #define BIT_SHIFT_BT_TIME_8197F 6 #define BIT_MASK_BT_TIME_8197F 0x3ffffff -#define BIT_BT_TIME_8197F(x) (((x) & BIT_MASK_BT_TIME_8197F) << BIT_SHIFT_BT_TIME_8197F) +#define BIT_BT_TIME_8197F(x) \ + (((x) & BIT_MASK_BT_TIME_8197F) << BIT_SHIFT_BT_TIME_8197F) #define BITS_BT_TIME_8197F (BIT_MASK_BT_TIME_8197F << BIT_SHIFT_BT_TIME_8197F) #define BIT_CLEAR_BT_TIME_8197F(x) ((x) & (~BITS_BT_TIME_8197F)) -#define BIT_GET_BT_TIME_8197F(x) (((x) >> BIT_SHIFT_BT_TIME_8197F) & BIT_MASK_BT_TIME_8197F) -#define BIT_SET_BT_TIME_8197F(x, v) (BIT_CLEAR_BT_TIME_8197F(x) | BIT_BT_TIME_8197F(v)) - +#define BIT_GET_BT_TIME_8197F(x) \ + (((x) >> BIT_SHIFT_BT_TIME_8197F) & BIT_MASK_BT_TIME_8197F) +#define BIT_SET_BT_TIME_8197F(x, v) \ + (BIT_CLEAR_BT_TIME_8197F(x) | BIT_BT_TIME_8197F(v)) #define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F 0 #define BIT_MASK_BT_RPT_SAMPLE_RATE_8197F 0x3f -#define BIT_BT_RPT_SAMPLE_RATE_8197F(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8197F) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) -#define BITS_BT_RPT_SAMPLE_RATE_8197F (BIT_MASK_BT_RPT_SAMPLE_RATE_8197F << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) -#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8197F)) -#define BIT_GET_BT_RPT_SAMPLE_RATE_8197F(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) & BIT_MASK_BT_RPT_SAMPLE_RATE_8197F) -#define BIT_SET_BT_RPT_SAMPLE_RATE_8197F(x, v) (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) | BIT_BT_RPT_SAMPLE_RATE_8197F(v)) - +#define BIT_BT_RPT_SAMPLE_RATE_8197F(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8197F) \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) +#define BITS_BT_RPT_SAMPLE_RATE_8197F \ + (BIT_MASK_BT_RPT_SAMPLE_RATE_8197F \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) \ + ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8197F)) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8197F(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) & \ + BIT_MASK_BT_RPT_SAMPLE_RATE_8197F) +#define BIT_SET_BT_RPT_SAMPLE_RATE_8197F(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) | \ + BIT_BT_RPT_SAMPLE_RATE_8197F(v)) /* 2 REG_BT_ACT_REGISTER_8197F */ #define BIT_SHIFT_BT_EISR_EN_8197F 16 #define BIT_MASK_BT_EISR_EN_8197F 0xff -#define BIT_BT_EISR_EN_8197F(x) (((x) & BIT_MASK_BT_EISR_EN_8197F) << BIT_SHIFT_BT_EISR_EN_8197F) -#define BITS_BT_EISR_EN_8197F (BIT_MASK_BT_EISR_EN_8197F << BIT_SHIFT_BT_EISR_EN_8197F) +#define BIT_BT_EISR_EN_8197F(x) \ + (((x) & BIT_MASK_BT_EISR_EN_8197F) << BIT_SHIFT_BT_EISR_EN_8197F) +#define BITS_BT_EISR_EN_8197F \ + (BIT_MASK_BT_EISR_EN_8197F << BIT_SHIFT_BT_EISR_EN_8197F) #define BIT_CLEAR_BT_EISR_EN_8197F(x) ((x) & (~BITS_BT_EISR_EN_8197F)) -#define BIT_GET_BT_EISR_EN_8197F(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8197F) & BIT_MASK_BT_EISR_EN_8197F) -#define BIT_SET_BT_EISR_EN_8197F(x, v) (BIT_CLEAR_BT_EISR_EN_8197F(x) | BIT_BT_EISR_EN_8197F(v)) +#define BIT_GET_BT_EISR_EN_8197F(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN_8197F) & BIT_MASK_BT_EISR_EN_8197F) +#define BIT_SET_BT_EISR_EN_8197F(x, v) \ + (BIT_CLEAR_BT_EISR_EN_8197F(x) | BIT_BT_EISR_EN_8197F(v)) #define BIT_BT_ACT_FALLING_ISR_8197F BIT(10) #define BIT_BT_ACT_RISING_ISR_8197F BIT(9) @@ -12558,23 +16569,29 @@ #define BIT_SHIFT_BT_CH_8197F 0 #define BIT_MASK_BT_CH_8197F 0xff -#define BIT_BT_CH_8197F(x) (((x) & BIT_MASK_BT_CH_8197F) << BIT_SHIFT_BT_CH_8197F) +#define BIT_BT_CH_8197F(x) \ + (((x) & BIT_MASK_BT_CH_8197F) << BIT_SHIFT_BT_CH_8197F) #define BITS_BT_CH_8197F (BIT_MASK_BT_CH_8197F << BIT_SHIFT_BT_CH_8197F) #define BIT_CLEAR_BT_CH_8197F(x) ((x) & (~BITS_BT_CH_8197F)) -#define BIT_GET_BT_CH_8197F(x) (((x) >> BIT_SHIFT_BT_CH_8197F) & BIT_MASK_BT_CH_8197F) -#define BIT_SET_BT_CH_8197F(x, v) (BIT_CLEAR_BT_CH_8197F(x) | BIT_BT_CH_8197F(v)) - +#define BIT_GET_BT_CH_8197F(x) \ + (((x) >> BIT_SHIFT_BT_CH_8197F) & BIT_MASK_BT_CH_8197F) +#define BIT_SET_BT_CH_8197F(x, v) \ + (BIT_CLEAR_BT_CH_8197F(x) | BIT_BT_CH_8197F(v)) /* 2 REG_OBFF_CTRL_BASIC_8197F */ #define BIT_OBFF_EN_V1_8197F BIT(31) #define BIT_SHIFT_OBFF_STATE_V1_8197F 28 #define BIT_MASK_OBFF_STATE_V1_8197F 0x3 -#define BIT_OBFF_STATE_V1_8197F(x) (((x) & BIT_MASK_OBFF_STATE_V1_8197F) << BIT_SHIFT_OBFF_STATE_V1_8197F) -#define BITS_OBFF_STATE_V1_8197F (BIT_MASK_OBFF_STATE_V1_8197F << BIT_SHIFT_OBFF_STATE_V1_8197F) +#define BIT_OBFF_STATE_V1_8197F(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1_8197F) << BIT_SHIFT_OBFF_STATE_V1_8197F) +#define BITS_OBFF_STATE_V1_8197F \ + (BIT_MASK_OBFF_STATE_V1_8197F << BIT_SHIFT_OBFF_STATE_V1_8197F) #define BIT_CLEAR_OBFF_STATE_V1_8197F(x) ((x) & (~BITS_OBFF_STATE_V1_8197F)) -#define BIT_GET_OBFF_STATE_V1_8197F(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8197F) & BIT_MASK_OBFF_STATE_V1_8197F) -#define BIT_SET_OBFF_STATE_V1_8197F(x, v) (BIT_CLEAR_OBFF_STATE_V1_8197F(x) | BIT_OBFF_STATE_V1_8197F(v)) +#define BIT_GET_OBFF_STATE_V1_8197F(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1_8197F) & BIT_MASK_OBFF_STATE_V1_8197F) +#define BIT_SET_OBFF_STATE_V1_8197F(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1_8197F(x) | BIT_OBFF_STATE_V1_8197F(v)) #define BIT_OBFF_ACT_RXDMA_EN_8197F BIT(27) #define BIT_OBFF_BLOCK_INT_EN_8197F BIT(26) @@ -12583,38 +16600,51 @@ #define BIT_SHIFT_WAKE_MAX_PLS_8197F 20 #define BIT_MASK_WAKE_MAX_PLS_8197F 0x7 -#define BIT_WAKE_MAX_PLS_8197F(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8197F) << BIT_SHIFT_WAKE_MAX_PLS_8197F) -#define BITS_WAKE_MAX_PLS_8197F (BIT_MASK_WAKE_MAX_PLS_8197F << BIT_SHIFT_WAKE_MAX_PLS_8197F) +#define BIT_WAKE_MAX_PLS_8197F(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS_8197F) << BIT_SHIFT_WAKE_MAX_PLS_8197F) +#define BITS_WAKE_MAX_PLS_8197F \ + (BIT_MASK_WAKE_MAX_PLS_8197F << BIT_SHIFT_WAKE_MAX_PLS_8197F) #define BIT_CLEAR_WAKE_MAX_PLS_8197F(x) ((x) & (~BITS_WAKE_MAX_PLS_8197F)) -#define BIT_GET_WAKE_MAX_PLS_8197F(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8197F) & BIT_MASK_WAKE_MAX_PLS_8197F) -#define BIT_SET_WAKE_MAX_PLS_8197F(x, v) (BIT_CLEAR_WAKE_MAX_PLS_8197F(x) | BIT_WAKE_MAX_PLS_8197F(v)) - +#define BIT_GET_WAKE_MAX_PLS_8197F(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8197F) & BIT_MASK_WAKE_MAX_PLS_8197F) +#define BIT_SET_WAKE_MAX_PLS_8197F(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS_8197F(x) | BIT_WAKE_MAX_PLS_8197F(v)) #define BIT_SHIFT_WAKE_MIN_PLS_8197F 16 #define BIT_MASK_WAKE_MIN_PLS_8197F 0x7 -#define BIT_WAKE_MIN_PLS_8197F(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8197F) << BIT_SHIFT_WAKE_MIN_PLS_8197F) -#define BITS_WAKE_MIN_PLS_8197F (BIT_MASK_WAKE_MIN_PLS_8197F << BIT_SHIFT_WAKE_MIN_PLS_8197F) +#define BIT_WAKE_MIN_PLS_8197F(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS_8197F) << BIT_SHIFT_WAKE_MIN_PLS_8197F) +#define BITS_WAKE_MIN_PLS_8197F \ + (BIT_MASK_WAKE_MIN_PLS_8197F << BIT_SHIFT_WAKE_MIN_PLS_8197F) #define BIT_CLEAR_WAKE_MIN_PLS_8197F(x) ((x) & (~BITS_WAKE_MIN_PLS_8197F)) -#define BIT_GET_WAKE_MIN_PLS_8197F(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8197F) & BIT_MASK_WAKE_MIN_PLS_8197F) -#define BIT_SET_WAKE_MIN_PLS_8197F(x, v) (BIT_CLEAR_WAKE_MIN_PLS_8197F(x) | BIT_WAKE_MIN_PLS_8197F(v)) - +#define BIT_GET_WAKE_MIN_PLS_8197F(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8197F) & BIT_MASK_WAKE_MIN_PLS_8197F) +#define BIT_SET_WAKE_MIN_PLS_8197F(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS_8197F(x) | BIT_WAKE_MIN_PLS_8197F(v)) #define BIT_SHIFT_WAKE_MAX_F2F_8197F 12 #define BIT_MASK_WAKE_MAX_F2F_8197F 0x7 -#define BIT_WAKE_MAX_F2F_8197F(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8197F) << BIT_SHIFT_WAKE_MAX_F2F_8197F) -#define BITS_WAKE_MAX_F2F_8197F (BIT_MASK_WAKE_MAX_F2F_8197F << BIT_SHIFT_WAKE_MAX_F2F_8197F) +#define BIT_WAKE_MAX_F2F_8197F(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F_8197F) << BIT_SHIFT_WAKE_MAX_F2F_8197F) +#define BITS_WAKE_MAX_F2F_8197F \ + (BIT_MASK_WAKE_MAX_F2F_8197F << BIT_SHIFT_WAKE_MAX_F2F_8197F) #define BIT_CLEAR_WAKE_MAX_F2F_8197F(x) ((x) & (~BITS_WAKE_MAX_F2F_8197F)) -#define BIT_GET_WAKE_MAX_F2F_8197F(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8197F) & BIT_MASK_WAKE_MAX_F2F_8197F) -#define BIT_SET_WAKE_MAX_F2F_8197F(x, v) (BIT_CLEAR_WAKE_MAX_F2F_8197F(x) | BIT_WAKE_MAX_F2F_8197F(v)) - +#define BIT_GET_WAKE_MAX_F2F_8197F(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8197F) & BIT_MASK_WAKE_MAX_F2F_8197F) +#define BIT_SET_WAKE_MAX_F2F_8197F(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F_8197F(x) | BIT_WAKE_MAX_F2F_8197F(v)) #define BIT_SHIFT_WAKE_MIN_F2F_8197F 8 #define BIT_MASK_WAKE_MIN_F2F_8197F 0x7 -#define BIT_WAKE_MIN_F2F_8197F(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8197F) << BIT_SHIFT_WAKE_MIN_F2F_8197F) -#define BITS_WAKE_MIN_F2F_8197F (BIT_MASK_WAKE_MIN_F2F_8197F << BIT_SHIFT_WAKE_MIN_F2F_8197F) +#define BIT_WAKE_MIN_F2F_8197F(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F_8197F) << BIT_SHIFT_WAKE_MIN_F2F_8197F) +#define BITS_WAKE_MIN_F2F_8197F \ + (BIT_MASK_WAKE_MIN_F2F_8197F << BIT_SHIFT_WAKE_MIN_F2F_8197F) #define BIT_CLEAR_WAKE_MIN_F2F_8197F(x) ((x) & (~BITS_WAKE_MIN_F2F_8197F)) -#define BIT_GET_WAKE_MIN_F2F_8197F(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8197F) & BIT_MASK_WAKE_MIN_F2F_8197F) -#define BIT_SET_WAKE_MIN_F2F_8197F(x, v) (BIT_CLEAR_WAKE_MIN_F2F_8197F(x) | BIT_WAKE_MIN_F2F_8197F(v)) +#define BIT_GET_WAKE_MIN_F2F_8197F(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8197F) & BIT_MASK_WAKE_MIN_F2F_8197F) +#define BIT_SET_WAKE_MIN_F2F_8197F(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F_8197F(x) | BIT_WAKE_MIN_F2F_8197F(v)) #define BIT_APP_CPU_ACT_V1_8197F BIT(3) #define BIT_APP_OBFF_V1_8197F BIT(2) @@ -12625,39 +16655,65 @@ #define BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F 24 #define BIT_MASK_RX_HIGH_TIMER_IDX_8197F 0x7 -#define BIT_RX_HIGH_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8197F) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) -#define BITS_RX_HIGH_TIMER_IDX_8197F (BIT_MASK_RX_HIGH_TIMER_IDX_8197F << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) -#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_HIGH_TIMER_IDX_8197F)) -#define BIT_GET_RX_HIGH_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) & BIT_MASK_RX_HIGH_TIMER_IDX_8197F) -#define BIT_SET_RX_HIGH_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) | BIT_RX_HIGH_TIMER_IDX_8197F(v)) - +#define BIT_RX_HIGH_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8197F) \ + << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) +#define BITS_RX_HIGH_TIMER_IDX_8197F \ + (BIT_MASK_RX_HIGH_TIMER_IDX_8197F << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_RX_HIGH_TIMER_IDX_8197F)) +#define BIT_GET_RX_HIGH_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) & \ + BIT_MASK_RX_HIGH_TIMER_IDX_8197F) +#define BIT_SET_RX_HIGH_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) | BIT_RX_HIGH_TIMER_IDX_8197F(v)) #define BIT_SHIFT_RX_MED_TIMER_IDX_8197F 16 #define BIT_MASK_RX_MED_TIMER_IDX_8197F 0x7 -#define BIT_RX_MED_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8197F) << BIT_SHIFT_RX_MED_TIMER_IDX_8197F) -#define BITS_RX_MED_TIMER_IDX_8197F (BIT_MASK_RX_MED_TIMER_IDX_8197F << BIT_SHIFT_RX_MED_TIMER_IDX_8197F) -#define BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_MED_TIMER_IDX_8197F)) -#define BIT_GET_RX_MED_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8197F) & BIT_MASK_RX_MED_TIMER_IDX_8197F) -#define BIT_SET_RX_MED_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) | BIT_RX_MED_TIMER_IDX_8197F(v)) - +#define BIT_RX_MED_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX_8197F) \ + << BIT_SHIFT_RX_MED_TIMER_IDX_8197F) +#define BITS_RX_MED_TIMER_IDX_8197F \ + (BIT_MASK_RX_MED_TIMER_IDX_8197F << BIT_SHIFT_RX_MED_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_RX_MED_TIMER_IDX_8197F)) +#define BIT_GET_RX_MED_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8197F) & \ + BIT_MASK_RX_MED_TIMER_IDX_8197F) +#define BIT_SET_RX_MED_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) | BIT_RX_MED_TIMER_IDX_8197F(v)) #define BIT_SHIFT_RX_LOW_TIMER_IDX_8197F 8 #define BIT_MASK_RX_LOW_TIMER_IDX_8197F 0x7 -#define BIT_RX_LOW_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8197F) << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) -#define BITS_RX_LOW_TIMER_IDX_8197F (BIT_MASK_RX_LOW_TIMER_IDX_8197F << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) -#define BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_LOW_TIMER_IDX_8197F)) -#define BIT_GET_RX_LOW_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) & BIT_MASK_RX_LOW_TIMER_IDX_8197F) -#define BIT_SET_RX_LOW_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) | BIT_RX_LOW_TIMER_IDX_8197F(v)) - +#define BIT_RX_LOW_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8197F) \ + << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) +#define BITS_RX_LOW_TIMER_IDX_8197F \ + (BIT_MASK_RX_LOW_TIMER_IDX_8197F << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_RX_LOW_TIMER_IDX_8197F)) +#define BIT_GET_RX_LOW_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) & \ + BIT_MASK_RX_LOW_TIMER_IDX_8197F) +#define BIT_SET_RX_LOW_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) | BIT_RX_LOW_TIMER_IDX_8197F(v)) #define BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F 0 #define BIT_MASK_OBFF_INT_TIMER_IDX_8197F 0x7 -#define BIT_OBFF_INT_TIMER_IDX_8197F(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8197F) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) -#define BITS_OBFF_INT_TIMER_IDX_8197F (BIT_MASK_OBFF_INT_TIMER_IDX_8197F << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) -#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) ((x) & (~BITS_OBFF_INT_TIMER_IDX_8197F)) -#define BIT_GET_OBFF_INT_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) & BIT_MASK_OBFF_INT_TIMER_IDX_8197F) -#define BIT_SET_OBFF_INT_TIMER_IDX_8197F(x, v) (BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) | BIT_OBFF_INT_TIMER_IDX_8197F(v)) - +#define BIT_OBFF_INT_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8197F) \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) +#define BITS_OBFF_INT_TIMER_IDX_8197F \ + (BIT_MASK_OBFF_INT_TIMER_IDX_8197F \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_OBFF_INT_TIMER_IDX_8197F)) +#define BIT_GET_OBFF_INT_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) & \ + BIT_MASK_OBFF_INT_TIMER_IDX_8197F) +#define BIT_SET_OBFF_INT_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) | \ + BIT_OBFF_INT_TIMER_IDX_8197F(v)) /* 2 REG_LTR_CTRL_BASIC_8197F */ #define BIT_LTR_EN_V1_8197F BIT(31) @@ -12673,135 +16729,207 @@ #define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F 20 #define BIT_MASK_HIGH_RATE_TRIG_SEL_8197F 0x3 -#define BIT_HIGH_RATE_TRIG_SEL_8197F(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8197F) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) -#define BITS_HIGH_RATE_TRIG_SEL_8197F (BIT_MASK_HIGH_RATE_TRIG_SEL_8197F << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) -#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8197F)) -#define BIT_GET_HIGH_RATE_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) & BIT_MASK_HIGH_RATE_TRIG_SEL_8197F) -#define BIT_SET_HIGH_RATE_TRIG_SEL_8197F(x, v) (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) | BIT_HIGH_RATE_TRIG_SEL_8197F(v)) - +#define BIT_HIGH_RATE_TRIG_SEL_8197F(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8197F) \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) +#define BITS_HIGH_RATE_TRIG_SEL_8197F \ + (BIT_MASK_HIGH_RATE_TRIG_SEL_8197F \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) \ + ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8197F)) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) & \ + BIT_MASK_HIGH_RATE_TRIG_SEL_8197F) +#define BIT_SET_HIGH_RATE_TRIG_SEL_8197F(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) | \ + BIT_HIGH_RATE_TRIG_SEL_8197F(v)) #define BIT_SHIFT_MED_RATE_TRIG_SEL_8197F 18 #define BIT_MASK_MED_RATE_TRIG_SEL_8197F 0x3 -#define BIT_MED_RATE_TRIG_SEL_8197F(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8197F) << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) -#define BITS_MED_RATE_TRIG_SEL_8197F (BIT_MASK_MED_RATE_TRIG_SEL_8197F << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) -#define BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) ((x) & (~BITS_MED_RATE_TRIG_SEL_8197F)) -#define BIT_GET_MED_RATE_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) & BIT_MASK_MED_RATE_TRIG_SEL_8197F) -#define BIT_SET_MED_RATE_TRIG_SEL_8197F(x, v) (BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) | BIT_MED_RATE_TRIG_SEL_8197F(v)) - +#define BIT_MED_RATE_TRIG_SEL_8197F(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8197F) \ + << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) +#define BITS_MED_RATE_TRIG_SEL_8197F \ + (BIT_MASK_MED_RATE_TRIG_SEL_8197F << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) +#define BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) \ + ((x) & (~BITS_MED_RATE_TRIG_SEL_8197F)) +#define BIT_GET_MED_RATE_TRIG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) & \ + BIT_MASK_MED_RATE_TRIG_SEL_8197F) +#define BIT_SET_MED_RATE_TRIG_SEL_8197F(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) | BIT_MED_RATE_TRIG_SEL_8197F(v)) #define BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F 16 #define BIT_MASK_LOW_RATE_TRIG_SEL_8197F 0x3 -#define BIT_LOW_RATE_TRIG_SEL_8197F(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8197F) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) -#define BITS_LOW_RATE_TRIG_SEL_8197F (BIT_MASK_LOW_RATE_TRIG_SEL_8197F << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) -#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) ((x) & (~BITS_LOW_RATE_TRIG_SEL_8197F)) -#define BIT_GET_LOW_RATE_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) & BIT_MASK_LOW_RATE_TRIG_SEL_8197F) -#define BIT_SET_LOW_RATE_TRIG_SEL_8197F(x, v) (BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) | BIT_LOW_RATE_TRIG_SEL_8197F(v)) - +#define BIT_LOW_RATE_TRIG_SEL_8197F(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8197F) \ + << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) +#define BITS_LOW_RATE_TRIG_SEL_8197F \ + (BIT_MASK_LOW_RATE_TRIG_SEL_8197F << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) \ + ((x) & (~BITS_LOW_RATE_TRIG_SEL_8197F)) +#define BIT_GET_LOW_RATE_TRIG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) & \ + BIT_MASK_LOW_RATE_TRIG_SEL_8197F) +#define BIT_SET_LOW_RATE_TRIG_SEL_8197F(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) | BIT_LOW_RATE_TRIG_SEL_8197F(v)) #define BIT_SHIFT_HIGH_RATE_BD_IDX_8197F 8 #define BIT_MASK_HIGH_RATE_BD_IDX_8197F 0x7f -#define BIT_HIGH_RATE_BD_IDX_8197F(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8197F) << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) -#define BITS_HIGH_RATE_BD_IDX_8197F (BIT_MASK_HIGH_RATE_BD_IDX_8197F << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) -#define BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) ((x) & (~BITS_HIGH_RATE_BD_IDX_8197F)) -#define BIT_GET_HIGH_RATE_BD_IDX_8197F(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) & BIT_MASK_HIGH_RATE_BD_IDX_8197F) -#define BIT_SET_HIGH_RATE_BD_IDX_8197F(x, v) (BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) | BIT_HIGH_RATE_BD_IDX_8197F(v)) - +#define BIT_HIGH_RATE_BD_IDX_8197F(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8197F) \ + << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) +#define BITS_HIGH_RATE_BD_IDX_8197F \ + (BIT_MASK_HIGH_RATE_BD_IDX_8197F << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) +#define BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) \ + ((x) & (~BITS_HIGH_RATE_BD_IDX_8197F)) +#define BIT_GET_HIGH_RATE_BD_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) & \ + BIT_MASK_HIGH_RATE_BD_IDX_8197F) +#define BIT_SET_HIGH_RATE_BD_IDX_8197F(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) | BIT_HIGH_RATE_BD_IDX_8197F(v)) #define BIT_SHIFT_LOW_RATE_BD_IDX_8197F 0 #define BIT_MASK_LOW_RATE_BD_IDX_8197F 0x7f -#define BIT_LOW_RATE_BD_IDX_8197F(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8197F) << BIT_SHIFT_LOW_RATE_BD_IDX_8197F) -#define BITS_LOW_RATE_BD_IDX_8197F (BIT_MASK_LOW_RATE_BD_IDX_8197F << BIT_SHIFT_LOW_RATE_BD_IDX_8197F) +#define BIT_LOW_RATE_BD_IDX_8197F(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX_8197F) \ + << BIT_SHIFT_LOW_RATE_BD_IDX_8197F) +#define BITS_LOW_RATE_BD_IDX_8197F \ + (BIT_MASK_LOW_RATE_BD_IDX_8197F << BIT_SHIFT_LOW_RATE_BD_IDX_8197F) #define BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8197F)) -#define BIT_GET_LOW_RATE_BD_IDX_8197F(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8197F) & BIT_MASK_LOW_RATE_BD_IDX_8197F) -#define BIT_SET_LOW_RATE_BD_IDX_8197F(x, v) (BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) | BIT_LOW_RATE_BD_IDX_8197F(v)) - +#define BIT_GET_LOW_RATE_BD_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8197F) & \ + BIT_MASK_LOW_RATE_BD_IDX_8197F) +#define BIT_SET_LOW_RATE_BD_IDX_8197F(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) | BIT_LOW_RATE_BD_IDX_8197F(v)) /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8197F */ #define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F 24 #define BIT_MASK_RX_EMPTY_TIMER_IDX_8197F 0x7 -#define BIT_RX_EMPTY_TIMER_IDX_8197F(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8197F) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) -#define BITS_RX_EMPTY_TIMER_IDX_8197F (BIT_MASK_RX_EMPTY_TIMER_IDX_8197F << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) -#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8197F)) -#define BIT_GET_RX_EMPTY_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) & BIT_MASK_RX_EMPTY_TIMER_IDX_8197F) -#define BIT_SET_RX_EMPTY_TIMER_IDX_8197F(x, v) (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) | BIT_RX_EMPTY_TIMER_IDX_8197F(v)) - +#define BIT_RX_EMPTY_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8197F) \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) +#define BITS_RX_EMPTY_TIMER_IDX_8197F \ + (BIT_MASK_RX_EMPTY_TIMER_IDX_8197F \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8197F)) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) & \ + BIT_MASK_RX_EMPTY_TIMER_IDX_8197F) +#define BIT_SET_RX_EMPTY_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) | \ + BIT_RX_EMPTY_TIMER_IDX_8197F(v)) #define BIT_SHIFT_RX_AFULL_TH_IDX_8197F 20 #define BIT_MASK_RX_AFULL_TH_IDX_8197F 0x7 -#define BIT_RX_AFULL_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8197F) << BIT_SHIFT_RX_AFULL_TH_IDX_8197F) -#define BITS_RX_AFULL_TH_IDX_8197F (BIT_MASK_RX_AFULL_TH_IDX_8197F << BIT_SHIFT_RX_AFULL_TH_IDX_8197F) +#define BIT_RX_AFULL_TH_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX_8197F) \ + << BIT_SHIFT_RX_AFULL_TH_IDX_8197F) +#define BITS_RX_AFULL_TH_IDX_8197F \ + (BIT_MASK_RX_AFULL_TH_IDX_8197F << BIT_SHIFT_RX_AFULL_TH_IDX_8197F) #define BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8197F)) -#define BIT_GET_RX_AFULL_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8197F) & BIT_MASK_RX_AFULL_TH_IDX_8197F) -#define BIT_SET_RX_AFULL_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) | BIT_RX_AFULL_TH_IDX_8197F(v)) - +#define BIT_GET_RX_AFULL_TH_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8197F) & \ + BIT_MASK_RX_AFULL_TH_IDX_8197F) +#define BIT_SET_RX_AFULL_TH_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) | BIT_RX_AFULL_TH_IDX_8197F(v)) #define BIT_SHIFT_RX_HIGH_TH_IDX_8197F 16 #define BIT_MASK_RX_HIGH_TH_IDX_8197F 0x7 -#define BIT_RX_HIGH_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8197F) << BIT_SHIFT_RX_HIGH_TH_IDX_8197F) -#define BITS_RX_HIGH_TH_IDX_8197F (BIT_MASK_RX_HIGH_TH_IDX_8197F << BIT_SHIFT_RX_HIGH_TH_IDX_8197F) +#define BIT_RX_HIGH_TH_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX_8197F) \ + << BIT_SHIFT_RX_HIGH_TH_IDX_8197F) +#define BITS_RX_HIGH_TH_IDX_8197F \ + (BIT_MASK_RX_HIGH_TH_IDX_8197F << BIT_SHIFT_RX_HIGH_TH_IDX_8197F) #define BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8197F)) -#define BIT_GET_RX_HIGH_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8197F) & BIT_MASK_RX_HIGH_TH_IDX_8197F) -#define BIT_SET_RX_HIGH_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) | BIT_RX_HIGH_TH_IDX_8197F(v)) - +#define BIT_GET_RX_HIGH_TH_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8197F) & \ + BIT_MASK_RX_HIGH_TH_IDX_8197F) +#define BIT_SET_RX_HIGH_TH_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) | BIT_RX_HIGH_TH_IDX_8197F(v)) #define BIT_SHIFT_RX_MED_TH_IDX_8197F 12 #define BIT_MASK_RX_MED_TH_IDX_8197F 0x7 -#define BIT_RX_MED_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8197F) << BIT_SHIFT_RX_MED_TH_IDX_8197F) -#define BITS_RX_MED_TH_IDX_8197F (BIT_MASK_RX_MED_TH_IDX_8197F << BIT_SHIFT_RX_MED_TH_IDX_8197F) +#define BIT_RX_MED_TH_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX_8197F) << BIT_SHIFT_RX_MED_TH_IDX_8197F) +#define BITS_RX_MED_TH_IDX_8197F \ + (BIT_MASK_RX_MED_TH_IDX_8197F << BIT_SHIFT_RX_MED_TH_IDX_8197F) #define BIT_CLEAR_RX_MED_TH_IDX_8197F(x) ((x) & (~BITS_RX_MED_TH_IDX_8197F)) -#define BIT_GET_RX_MED_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8197F) & BIT_MASK_RX_MED_TH_IDX_8197F) -#define BIT_SET_RX_MED_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_MED_TH_IDX_8197F(x) | BIT_RX_MED_TH_IDX_8197F(v)) - +#define BIT_GET_RX_MED_TH_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8197F) & BIT_MASK_RX_MED_TH_IDX_8197F) +#define BIT_SET_RX_MED_TH_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX_8197F(x) | BIT_RX_MED_TH_IDX_8197F(v)) #define BIT_SHIFT_RX_LOW_TH_IDX_8197F 8 #define BIT_MASK_RX_LOW_TH_IDX_8197F 0x7 -#define BIT_RX_LOW_TH_IDX_8197F(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8197F) << BIT_SHIFT_RX_LOW_TH_IDX_8197F) -#define BITS_RX_LOW_TH_IDX_8197F (BIT_MASK_RX_LOW_TH_IDX_8197F << BIT_SHIFT_RX_LOW_TH_IDX_8197F) +#define BIT_RX_LOW_TH_IDX_8197F(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX_8197F) << BIT_SHIFT_RX_LOW_TH_IDX_8197F) +#define BITS_RX_LOW_TH_IDX_8197F \ + (BIT_MASK_RX_LOW_TH_IDX_8197F << BIT_SHIFT_RX_LOW_TH_IDX_8197F) #define BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) ((x) & (~BITS_RX_LOW_TH_IDX_8197F)) -#define BIT_GET_RX_LOW_TH_IDX_8197F(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8197F) & BIT_MASK_RX_LOW_TH_IDX_8197F) -#define BIT_SET_RX_LOW_TH_IDX_8197F(x, v) (BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) | BIT_RX_LOW_TH_IDX_8197F(v)) - +#define BIT_GET_RX_LOW_TH_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8197F) & BIT_MASK_RX_LOW_TH_IDX_8197F) +#define BIT_SET_RX_LOW_TH_IDX_8197F(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) | BIT_RX_LOW_TH_IDX_8197F(v)) #define BIT_SHIFT_LTR_SPACE_IDX_8197F 4 #define BIT_MASK_LTR_SPACE_IDX_8197F 0x3 -#define BIT_LTR_SPACE_IDX_8197F(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8197F) << BIT_SHIFT_LTR_SPACE_IDX_8197F) -#define BITS_LTR_SPACE_IDX_8197F (BIT_MASK_LTR_SPACE_IDX_8197F << BIT_SHIFT_LTR_SPACE_IDX_8197F) +#define BIT_LTR_SPACE_IDX_8197F(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX_8197F) << BIT_SHIFT_LTR_SPACE_IDX_8197F) +#define BITS_LTR_SPACE_IDX_8197F \ + (BIT_MASK_LTR_SPACE_IDX_8197F << BIT_SHIFT_LTR_SPACE_IDX_8197F) #define BIT_CLEAR_LTR_SPACE_IDX_8197F(x) ((x) & (~BITS_LTR_SPACE_IDX_8197F)) -#define BIT_GET_LTR_SPACE_IDX_8197F(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8197F) & BIT_MASK_LTR_SPACE_IDX_8197F) -#define BIT_SET_LTR_SPACE_IDX_8197F(x, v) (BIT_CLEAR_LTR_SPACE_IDX_8197F(x) | BIT_LTR_SPACE_IDX_8197F(v)) - +#define BIT_GET_LTR_SPACE_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8197F) & BIT_MASK_LTR_SPACE_IDX_8197F) +#define BIT_SET_LTR_SPACE_IDX_8197F(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX_8197F(x) | BIT_LTR_SPACE_IDX_8197F(v)) #define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F 0 #define BIT_MASK_LTR_IDLE_TIMER_IDX_8197F 0x7 -#define BIT_LTR_IDLE_TIMER_IDX_8197F(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8197F) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) -#define BITS_LTR_IDLE_TIMER_IDX_8197F (BIT_MASK_LTR_IDLE_TIMER_IDX_8197F << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) -#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8197F)) -#define BIT_GET_LTR_IDLE_TIMER_IDX_8197F(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) & BIT_MASK_LTR_IDLE_TIMER_IDX_8197F) -#define BIT_SET_LTR_IDLE_TIMER_IDX_8197F(x, v) (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) | BIT_LTR_IDLE_TIMER_IDX_8197F(v)) - +#define BIT_LTR_IDLE_TIMER_IDX_8197F(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8197F) \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) +#define BITS_LTR_IDLE_TIMER_IDX_8197F \ + (BIT_MASK_LTR_IDLE_TIMER_IDX_8197F \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) \ + ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8197F)) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8197F(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) & \ + BIT_MASK_LTR_IDLE_TIMER_IDX_8197F) +#define BIT_SET_LTR_IDLE_TIMER_IDX_8197F(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) | \ + BIT_LTR_IDLE_TIMER_IDX_8197F(v)) /* 2 REG_LTR_IDLE_LATENCY_V1_8197F */ #define BIT_SHIFT_LTR_IDLE_L_8197F 0 #define BIT_MASK_LTR_IDLE_L_8197F 0xffffffffL -#define BIT_LTR_IDLE_L_8197F(x) (((x) & BIT_MASK_LTR_IDLE_L_8197F) << BIT_SHIFT_LTR_IDLE_L_8197F) -#define BITS_LTR_IDLE_L_8197F (BIT_MASK_LTR_IDLE_L_8197F << BIT_SHIFT_LTR_IDLE_L_8197F) +#define BIT_LTR_IDLE_L_8197F(x) \ + (((x) & BIT_MASK_LTR_IDLE_L_8197F) << BIT_SHIFT_LTR_IDLE_L_8197F) +#define BITS_LTR_IDLE_L_8197F \ + (BIT_MASK_LTR_IDLE_L_8197F << BIT_SHIFT_LTR_IDLE_L_8197F) #define BIT_CLEAR_LTR_IDLE_L_8197F(x) ((x) & (~BITS_LTR_IDLE_L_8197F)) -#define BIT_GET_LTR_IDLE_L_8197F(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8197F) & BIT_MASK_LTR_IDLE_L_8197F) -#define BIT_SET_LTR_IDLE_L_8197F(x, v) (BIT_CLEAR_LTR_IDLE_L_8197F(x) | BIT_LTR_IDLE_L_8197F(v)) - +#define BIT_GET_LTR_IDLE_L_8197F(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L_8197F) & BIT_MASK_LTR_IDLE_L_8197F) +#define BIT_SET_LTR_IDLE_L_8197F(x, v) \ + (BIT_CLEAR_LTR_IDLE_L_8197F(x) | BIT_LTR_IDLE_L_8197F(v)) /* 2 REG_LTR_ACTIVE_LATENCY_V1_8197F */ #define BIT_SHIFT_LTR_ACT_L_8197F 0 #define BIT_MASK_LTR_ACT_L_8197F 0xffffffffL -#define BIT_LTR_ACT_L_8197F(x) (((x) & BIT_MASK_LTR_ACT_L_8197F) << BIT_SHIFT_LTR_ACT_L_8197F) -#define BITS_LTR_ACT_L_8197F (BIT_MASK_LTR_ACT_L_8197F << BIT_SHIFT_LTR_ACT_L_8197F) +#define BIT_LTR_ACT_L_8197F(x) \ + (((x) & BIT_MASK_LTR_ACT_L_8197F) << BIT_SHIFT_LTR_ACT_L_8197F) +#define BITS_LTR_ACT_L_8197F \ + (BIT_MASK_LTR_ACT_L_8197F << BIT_SHIFT_LTR_ACT_L_8197F) #define BIT_CLEAR_LTR_ACT_L_8197F(x) ((x) & (~BITS_LTR_ACT_L_8197F)) -#define BIT_GET_LTR_ACT_L_8197F(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8197F) & BIT_MASK_LTR_ACT_L_8197F) -#define BIT_SET_LTR_ACT_L_8197F(x, v) (BIT_CLEAR_LTR_ACT_L_8197F(x) | BIT_LTR_ACT_L_8197F(v)) - +#define BIT_GET_LTR_ACT_L_8197F(x) \ + (((x) >> BIT_SHIFT_LTR_ACT_L_8197F) & BIT_MASK_LTR_ACT_L_8197F) +#define BIT_SET_LTR_ACT_L_8197F(x, v) \ + (BIT_CLEAR_LTR_ACT_L_8197F(x) | BIT_LTR_ACT_L_8197F(v)) /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F */ #define BIT_APPEND_MACID_IN_RESP_EN_8197F BIT(50) @@ -12810,12 +16938,17 @@ #define BIT_SHIFT_TRAIN_STA_ADDR_8197F 0 #define BIT_MASK_TRAIN_STA_ADDR_8197F 0xffffffffffffL -#define BIT_TRAIN_STA_ADDR_8197F(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_8197F) << BIT_SHIFT_TRAIN_STA_ADDR_8197F) -#define BITS_TRAIN_STA_ADDR_8197F (BIT_MASK_TRAIN_STA_ADDR_8197F << BIT_SHIFT_TRAIN_STA_ADDR_8197F) +#define BIT_TRAIN_STA_ADDR_8197F(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_8197F) \ + << BIT_SHIFT_TRAIN_STA_ADDR_8197F) +#define BITS_TRAIN_STA_ADDR_8197F \ + (BIT_MASK_TRAIN_STA_ADDR_8197F << BIT_SHIFT_TRAIN_STA_ADDR_8197F) #define BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) ((x) & (~BITS_TRAIN_STA_ADDR_8197F)) -#define BIT_GET_TRAIN_STA_ADDR_8197F(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8197F) & BIT_MASK_TRAIN_STA_ADDR_8197F) -#define BIT_SET_TRAIN_STA_ADDR_8197F(x, v) (BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) | BIT_TRAIN_STA_ADDR_8197F(v)) - +#define BIT_GET_TRAIN_STA_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8197F) & \ + BIT_MASK_TRAIN_STA_ADDR_8197F) +#define BIT_SET_TRAIN_STA_ADDR_8197F(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) | BIT_TRAIN_STA_ADDR_8197F(v)) /* 2 REG_RSVD_0X7B4_8197F */ @@ -12823,11 +16956,17 @@ #define BIT_SHIFT_PKTCNT_BSSIDMAP_8197F 4 #define BIT_MASK_PKTCNT_BSSIDMAP_8197F 0xf -#define BIT_PKTCNT_BSSIDMAP_8197F(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8197F) << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) -#define BITS_PKTCNT_BSSIDMAP_8197F (BIT_MASK_PKTCNT_BSSIDMAP_8197F << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) +#define BIT_PKTCNT_BSSIDMAP_8197F(x) \ + (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8197F) \ + << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) +#define BITS_PKTCNT_BSSIDMAP_8197F \ + (BIT_MASK_PKTCNT_BSSIDMAP_8197F << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) #define BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8197F)) -#define BIT_GET_PKTCNT_BSSIDMAP_8197F(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) & BIT_MASK_PKTCNT_BSSIDMAP_8197F) -#define BIT_SET_PKTCNT_BSSIDMAP_8197F(x, v) (BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) | BIT_PKTCNT_BSSIDMAP_8197F(v)) +#define BIT_GET_PKTCNT_BSSIDMAP_8197F(x) \ + (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) & \ + BIT_MASK_PKTCNT_BSSIDMAP_8197F) +#define BIT_SET_PKTCNT_BSSIDMAP_8197F(x, v) \ + (BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) | BIT_PKTCNT_BSSIDMAP_8197F(v)) #define BIT_PKTCNT_CNTRST_8197F BIT(1) #define BIT_PKTCNT_CNTEN_8197F BIT(0) @@ -12838,68 +16977,111 @@ #define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F 0 #define BIT_MASK_WMAC_PKTCNT_CFGAD_8197F 0xff -#define BIT_WMAC_PKTCNT_CFGAD_8197F(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8197F) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) -#define BITS_WMAC_PKTCNT_CFGAD_8197F (BIT_MASK_WMAC_PKTCNT_CFGAD_8197F << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) -#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8197F)) -#define BIT_GET_WMAC_PKTCNT_CFGAD_8197F(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) & BIT_MASK_WMAC_PKTCNT_CFGAD_8197F) -#define BIT_SET_WMAC_PKTCNT_CFGAD_8197F(x, v) (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) | BIT_WMAC_PKTCNT_CFGAD_8197F(v)) - +#define BIT_WMAC_PKTCNT_CFGAD_8197F(x) \ + (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8197F) \ + << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) +#define BITS_WMAC_PKTCNT_CFGAD_8197F \ + (BIT_MASK_WMAC_PKTCNT_CFGAD_8197F << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) +#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) \ + ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8197F)) +#define BIT_GET_WMAC_PKTCNT_CFGAD_8197F(x) \ + (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) & \ + BIT_MASK_WMAC_PKTCNT_CFGAD_8197F) +#define BIT_SET_WMAC_PKTCNT_CFGAD_8197F(x, v) \ + (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) | BIT_WMAC_PKTCNT_CFGAD_8197F(v)) /* 2 REG_IQ_DUMP_8197F */ #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F (64 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC_8197F(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) -#define BITS_R_WMAC_MATCH_REF_MAC_8197F (BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) -#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8197F)) -#define BIT_GET_R_WMAC_MATCH_REF_MAC_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F) -#define BIT_SET_R_WMAC_MATCH_REF_MAC_8197F(x, v) (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) | BIT_R_WMAC_MATCH_REF_MAC_8197F(v)) - +#define BIT_R_WMAC_MATCH_REF_MAC_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) +#define BITS_R_WMAC_MATCH_REF_MAC_8197F \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8197F)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) | \ + BIT_R_WMAC_MATCH_REF_MAC_8197F(v)) #define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_MASK_LA_MAC_8197F 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC_8197F(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8197F) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) -#define BITS_R_WMAC_MASK_LA_MAC_8197F (BIT_MASK_R_WMAC_MASK_LA_MAC_8197F << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) -#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC_8197F)) -#define BIT_GET_R_WMAC_MASK_LA_MAC_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) & BIT_MASK_R_WMAC_MASK_LA_MAC_8197F) -#define BIT_SET_R_WMAC_MASK_LA_MAC_8197F(x, v) (BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) | BIT_R_WMAC_MASK_LA_MAC_8197F(v)) - +#define BIT_R_WMAC_MASK_LA_MAC_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8197F) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) +#define BITS_R_WMAC_MASK_LA_MAC_8197F \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_8197F \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) \ + ((x) & (~BITS_R_WMAC_MASK_LA_MAC_8197F)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_8197F) +#define BIT_SET_R_WMAC_MASK_LA_MAC_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) | \ + BIT_R_WMAC_MASK_LA_MAC_8197F(v)) #define BIT_SHIFT_DUMP_OK_ADDR_8197F 16 #define BIT_MASK_DUMP_OK_ADDR_8197F 0xffff -#define BIT_DUMP_OK_ADDR_8197F(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8197F) << BIT_SHIFT_DUMP_OK_ADDR_8197F) -#define BITS_DUMP_OK_ADDR_8197F (BIT_MASK_DUMP_OK_ADDR_8197F << BIT_SHIFT_DUMP_OK_ADDR_8197F) +#define BIT_DUMP_OK_ADDR_8197F(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR_8197F) << BIT_SHIFT_DUMP_OK_ADDR_8197F) +#define BITS_DUMP_OK_ADDR_8197F \ + (BIT_MASK_DUMP_OK_ADDR_8197F << BIT_SHIFT_DUMP_OK_ADDR_8197F) #define BIT_CLEAR_DUMP_OK_ADDR_8197F(x) ((x) & (~BITS_DUMP_OK_ADDR_8197F)) -#define BIT_GET_DUMP_OK_ADDR_8197F(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8197F) & BIT_MASK_DUMP_OK_ADDR_8197F) -#define BIT_SET_DUMP_OK_ADDR_8197F(x, v) (BIT_CLEAR_DUMP_OK_ADDR_8197F(x) | BIT_DUMP_OK_ADDR_8197F(v)) - +#define BIT_GET_DUMP_OK_ADDR_8197F(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8197F) & BIT_MASK_DUMP_OK_ADDR_8197F) +#define BIT_SET_DUMP_OK_ADDR_8197F(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR_8197F(x) | BIT_DUMP_OK_ADDR_8197F(v)) #define BIT_SHIFT_R_TRIG_TIME_SEL_8197F 8 #define BIT_MASK_R_TRIG_TIME_SEL_8197F 0x7f -#define BIT_R_TRIG_TIME_SEL_8197F(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8197F) << BIT_SHIFT_R_TRIG_TIME_SEL_8197F) -#define BITS_R_TRIG_TIME_SEL_8197F (BIT_MASK_R_TRIG_TIME_SEL_8197F << BIT_SHIFT_R_TRIG_TIME_SEL_8197F) +#define BIT_R_TRIG_TIME_SEL_8197F(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL_8197F) \ + << BIT_SHIFT_R_TRIG_TIME_SEL_8197F) +#define BITS_R_TRIG_TIME_SEL_8197F \ + (BIT_MASK_R_TRIG_TIME_SEL_8197F << BIT_SHIFT_R_TRIG_TIME_SEL_8197F) #define BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8197F)) -#define BIT_GET_R_TRIG_TIME_SEL_8197F(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8197F) & BIT_MASK_R_TRIG_TIME_SEL_8197F) -#define BIT_SET_R_TRIG_TIME_SEL_8197F(x, v) (BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) | BIT_R_TRIG_TIME_SEL_8197F(v)) - +#define BIT_GET_R_TRIG_TIME_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8197F) & \ + BIT_MASK_R_TRIG_TIME_SEL_8197F) +#define BIT_SET_R_TRIG_TIME_SEL_8197F(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) | BIT_R_TRIG_TIME_SEL_8197F(v)) #define BIT_SHIFT_R_MAC_TRIG_SEL_8197F 6 #define BIT_MASK_R_MAC_TRIG_SEL_8197F 0x3 -#define BIT_R_MAC_TRIG_SEL_8197F(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8197F) << BIT_SHIFT_R_MAC_TRIG_SEL_8197F) -#define BITS_R_MAC_TRIG_SEL_8197F (BIT_MASK_R_MAC_TRIG_SEL_8197F << BIT_SHIFT_R_MAC_TRIG_SEL_8197F) +#define BIT_R_MAC_TRIG_SEL_8197F(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL_8197F) \ + << BIT_SHIFT_R_MAC_TRIG_SEL_8197F) +#define BITS_R_MAC_TRIG_SEL_8197F \ + (BIT_MASK_R_MAC_TRIG_SEL_8197F << BIT_SHIFT_R_MAC_TRIG_SEL_8197F) #define BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8197F)) -#define BIT_GET_R_MAC_TRIG_SEL_8197F(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8197F) & BIT_MASK_R_MAC_TRIG_SEL_8197F) -#define BIT_SET_R_MAC_TRIG_SEL_8197F(x, v) (BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) | BIT_R_MAC_TRIG_SEL_8197F(v)) +#define BIT_GET_R_MAC_TRIG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8197F) & \ + BIT_MASK_R_MAC_TRIG_SEL_8197F) +#define BIT_SET_R_MAC_TRIG_SEL_8197F(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) | BIT_R_MAC_TRIG_SEL_8197F(v)) #define BIT_MAC_TRIG_REG_8197F BIT(5) #define BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F 3 #define BIT_MASK_R_LEVEL_PULSE_SEL_8197F 0x3 -#define BIT_R_LEVEL_PULSE_SEL_8197F(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8197F) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) -#define BITS_R_LEVEL_PULSE_SEL_8197F (BIT_MASK_R_LEVEL_PULSE_SEL_8197F << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) -#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) ((x) & (~BITS_R_LEVEL_PULSE_SEL_8197F)) -#define BIT_GET_R_LEVEL_PULSE_SEL_8197F(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) & BIT_MASK_R_LEVEL_PULSE_SEL_8197F) -#define BIT_SET_R_LEVEL_PULSE_SEL_8197F(x, v) (BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) | BIT_R_LEVEL_PULSE_SEL_8197F(v)) +#define BIT_R_LEVEL_PULSE_SEL_8197F(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8197F) \ + << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) +#define BITS_R_LEVEL_PULSE_SEL_8197F \ + (BIT_MASK_R_LEVEL_PULSE_SEL_8197F << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) \ + ((x) & (~BITS_R_LEVEL_PULSE_SEL_8197F)) +#define BIT_GET_R_LEVEL_PULSE_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) & \ + BIT_MASK_R_LEVEL_PULSE_SEL_8197F) +#define BIT_SET_R_LEVEL_PULSE_SEL_8197F(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) | BIT_R_LEVEL_PULSE_SEL_8197F(v)) #define BIT_EN_LA_MAC_8197F BIT(2) #define BIT_R_EN_IQDUMP_8197F BIT(1) @@ -12917,31 +17099,51 @@ #define BIT_SHIFT_R_TIME_UNIT_SEL_8197F 0 #define BIT_MASK_R_TIME_UNIT_SEL_8197F 0x7 -#define BIT_R_TIME_UNIT_SEL_8197F(x) (((x) & BIT_MASK_R_TIME_UNIT_SEL_8197F) << BIT_SHIFT_R_TIME_UNIT_SEL_8197F) -#define BITS_R_TIME_UNIT_SEL_8197F (BIT_MASK_R_TIME_UNIT_SEL_8197F << BIT_SHIFT_R_TIME_UNIT_SEL_8197F) +#define BIT_R_TIME_UNIT_SEL_8197F(x) \ + (((x) & BIT_MASK_R_TIME_UNIT_SEL_8197F) \ + << BIT_SHIFT_R_TIME_UNIT_SEL_8197F) +#define BITS_R_TIME_UNIT_SEL_8197F \ + (BIT_MASK_R_TIME_UNIT_SEL_8197F << BIT_SHIFT_R_TIME_UNIT_SEL_8197F) #define BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) ((x) & (~BITS_R_TIME_UNIT_SEL_8197F)) -#define BIT_GET_R_TIME_UNIT_SEL_8197F(x) (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL_8197F) & BIT_MASK_R_TIME_UNIT_SEL_8197F) -#define BIT_SET_R_TIME_UNIT_SEL_8197F(x, v) (BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) | BIT_R_TIME_UNIT_SEL_8197F(v)) - +#define BIT_GET_R_TIME_UNIT_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL_8197F) & \ + BIT_MASK_R_TIME_UNIT_SEL_8197F) +#define BIT_SET_R_TIME_UNIT_SEL_8197F(x, v) \ + (BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) | BIT_R_TIME_UNIT_SEL_8197F(v)) /* 2 REG_OFDM_CCK_LEN_MASK_8197F */ #define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F (64 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_RX_FIL_LEN_8197F 0xffff -#define BIT_R_WMAC_RX_FIL_LEN_8197F(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8197F) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) -#define BITS_R_WMAC_RX_FIL_LEN_8197F (BIT_MASK_R_WMAC_RX_FIL_LEN_8197F << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) -#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN_8197F)) -#define BIT_GET_R_WMAC_RX_FIL_LEN_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) & BIT_MASK_R_WMAC_RX_FIL_LEN_8197F) -#define BIT_SET_R_WMAC_RX_FIL_LEN_8197F(x, v) (BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) | BIT_R_WMAC_RX_FIL_LEN_8197F(v)) - +#define BIT_R_WMAC_RX_FIL_LEN_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8197F) \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) +#define BITS_R_WMAC_RX_FIL_LEN_8197F \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_8197F << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) \ + ((x) & (~BITS_R_WMAC_RX_FIL_LEN_8197F)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) & \ + BIT_MASK_R_WMAC_RX_FIL_LEN_8197F) +#define BIT_SET_R_WMAC_RX_FIL_LEN_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) | BIT_R_WMAC_RX_FIL_LEN_8197F(v)) #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F (56 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH_8197F(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) -#define BITS_R_WMAC_RXFIFO_FULL_TH_8197F (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) -#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8197F)) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F) -#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8197F(x, v) (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) | BIT_R_WMAC_RXFIFO_FULL_TH_8197F(v)) +#define BIT_R_WMAC_RXFIFO_FULL_TH_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) +#define BITS_R_WMAC_RXFIFO_FULL_TH_8197F \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8197F)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) | \ + BIT_R_WMAC_RXFIFO_FULL_TH_8197F(v)) #define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8197F BIT(55) #define BIT_R_WMAC_RXRST_DLY_8197F BIT(54) @@ -12970,21 +17172,27 @@ #define BIT_SHIFT_R_OFDM_LEN_8197F 26 #define BIT_MASK_R_OFDM_LEN_8197F 0x3f -#define BIT_R_OFDM_LEN_8197F(x) (((x) & BIT_MASK_R_OFDM_LEN_8197F) << BIT_SHIFT_R_OFDM_LEN_8197F) -#define BITS_R_OFDM_LEN_8197F (BIT_MASK_R_OFDM_LEN_8197F << BIT_SHIFT_R_OFDM_LEN_8197F) +#define BIT_R_OFDM_LEN_8197F(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_8197F) << BIT_SHIFT_R_OFDM_LEN_8197F) +#define BITS_R_OFDM_LEN_8197F \ + (BIT_MASK_R_OFDM_LEN_8197F << BIT_SHIFT_R_OFDM_LEN_8197F) #define BIT_CLEAR_R_OFDM_LEN_8197F(x) ((x) & (~BITS_R_OFDM_LEN_8197F)) -#define BIT_GET_R_OFDM_LEN_8197F(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8197F) & BIT_MASK_R_OFDM_LEN_8197F) -#define BIT_SET_R_OFDM_LEN_8197F(x, v) (BIT_CLEAR_R_OFDM_LEN_8197F(x) | BIT_R_OFDM_LEN_8197F(v)) - +#define BIT_GET_R_OFDM_LEN_8197F(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_8197F) & BIT_MASK_R_OFDM_LEN_8197F) +#define BIT_SET_R_OFDM_LEN_8197F(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_8197F(x) | BIT_R_OFDM_LEN_8197F(v)) #define BIT_SHIFT_R_CCK_LEN_8197F 0 #define BIT_MASK_R_CCK_LEN_8197F 0xffff -#define BIT_R_CCK_LEN_8197F(x) (((x) & BIT_MASK_R_CCK_LEN_8197F) << BIT_SHIFT_R_CCK_LEN_8197F) -#define BITS_R_CCK_LEN_8197F (BIT_MASK_R_CCK_LEN_8197F << BIT_SHIFT_R_CCK_LEN_8197F) +#define BIT_R_CCK_LEN_8197F(x) \ + (((x) & BIT_MASK_R_CCK_LEN_8197F) << BIT_SHIFT_R_CCK_LEN_8197F) +#define BITS_R_CCK_LEN_8197F \ + (BIT_MASK_R_CCK_LEN_8197F << BIT_SHIFT_R_CCK_LEN_8197F) #define BIT_CLEAR_R_CCK_LEN_8197F(x) ((x) & (~BITS_R_CCK_LEN_8197F)) -#define BIT_GET_R_CCK_LEN_8197F(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8197F) & BIT_MASK_R_CCK_LEN_8197F) -#define BIT_SET_R_CCK_LEN_8197F(x, v) (BIT_CLEAR_R_CCK_LEN_8197F(x) | BIT_R_CCK_LEN_8197F(v)) - +#define BIT_GET_R_CCK_LEN_8197F(x) \ + (((x) >> BIT_SHIFT_R_CCK_LEN_8197F) & BIT_MASK_R_CCK_LEN_8197F) +#define BIT_SET_R_CCK_LEN_8197F(x, v) \ + (BIT_CLEAR_R_CCK_LEN_8197F(x) | BIT_R_CCK_LEN_8197F(v)) /* 2 REG_RX_FILTER_FUNCTION_8197F */ #define BIT_R_WMAC_RXHANG_EN_8197F BIT(15) @@ -13008,41 +17216,58 @@ #define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F 0 #define BIT_MASK_R_WMAC_TXNDP_SIGB_8197F 0x1fffff -#define BIT_R_WMAC_TXNDP_SIGB_8197F(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8197F) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) -#define BITS_R_WMAC_TXNDP_SIGB_8197F (BIT_MASK_R_WMAC_TXNDP_SIGB_8197F << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) -#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8197F)) -#define BIT_GET_R_WMAC_TXNDP_SIGB_8197F(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) & BIT_MASK_R_WMAC_TXNDP_SIGB_8197F) -#define BIT_SET_R_WMAC_TXNDP_SIGB_8197F(x, v) (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) | BIT_R_WMAC_TXNDP_SIGB_8197F(v)) - +#define BIT_R_WMAC_TXNDP_SIGB_8197F(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8197F) \ + << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) +#define BITS_R_WMAC_TXNDP_SIGB_8197F \ + (BIT_MASK_R_WMAC_TXNDP_SIGB_8197F << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) \ + ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8197F)) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8197F(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) & \ + BIT_MASK_R_WMAC_TXNDP_SIGB_8197F) +#define BIT_SET_R_WMAC_TXNDP_SIGB_8197F(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) | BIT_R_WMAC_TXNDP_SIGB_8197F(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8197F */ #define BIT_SHIFT_R_MAC_DEBUG_8197F (32 & CPU_OPT_WIDTH) #define BIT_MASK_R_MAC_DEBUG_8197F 0xffffffffL -#define BIT_R_MAC_DEBUG_8197F(x) (((x) & BIT_MASK_R_MAC_DEBUG_8197F) << BIT_SHIFT_R_MAC_DEBUG_8197F) -#define BITS_R_MAC_DEBUG_8197F (BIT_MASK_R_MAC_DEBUG_8197F << BIT_SHIFT_R_MAC_DEBUG_8197F) +#define BIT_R_MAC_DEBUG_8197F(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_8197F) << BIT_SHIFT_R_MAC_DEBUG_8197F) +#define BITS_R_MAC_DEBUG_8197F \ + (BIT_MASK_R_MAC_DEBUG_8197F << BIT_SHIFT_R_MAC_DEBUG_8197F) #define BIT_CLEAR_R_MAC_DEBUG_8197F(x) ((x) & (~BITS_R_MAC_DEBUG_8197F)) -#define BIT_GET_R_MAC_DEBUG_8197F(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_8197F) & BIT_MASK_R_MAC_DEBUG_8197F) -#define BIT_SET_R_MAC_DEBUG_8197F(x, v) (BIT_CLEAR_R_MAC_DEBUG_8197F(x) | BIT_R_MAC_DEBUG_8197F(v)) - +#define BIT_GET_R_MAC_DEBUG_8197F(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_8197F) & BIT_MASK_R_MAC_DEBUG_8197F) +#define BIT_SET_R_MAC_DEBUG_8197F(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_8197F(x) | BIT_R_MAC_DEBUG_8197F(v)) #define BIT_SHIFT_R_MAC_DBG_SHIFT_8197F 8 #define BIT_MASK_R_MAC_DBG_SHIFT_8197F 0x7 -#define BIT_R_MAC_DBG_SHIFT_8197F(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8197F) << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) -#define BITS_R_MAC_DBG_SHIFT_8197F (BIT_MASK_R_MAC_DBG_SHIFT_8197F << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) +#define BIT_R_MAC_DBG_SHIFT_8197F(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8197F) \ + << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) +#define BITS_R_MAC_DBG_SHIFT_8197F \ + (BIT_MASK_R_MAC_DBG_SHIFT_8197F << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) #define BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8197F)) -#define BIT_GET_R_MAC_DBG_SHIFT_8197F(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) & BIT_MASK_R_MAC_DBG_SHIFT_8197F) -#define BIT_SET_R_MAC_DBG_SHIFT_8197F(x, v) (BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) | BIT_R_MAC_DBG_SHIFT_8197F(v)) - +#define BIT_GET_R_MAC_DBG_SHIFT_8197F(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) & \ + BIT_MASK_R_MAC_DBG_SHIFT_8197F) +#define BIT_SET_R_MAC_DBG_SHIFT_8197F(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) | BIT_R_MAC_DBG_SHIFT_8197F(v)) #define BIT_SHIFT_R_MAC_DBG_SEL_8197F 0 #define BIT_MASK_R_MAC_DBG_SEL_8197F 0x3 -#define BIT_R_MAC_DBG_SEL_8197F(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8197F) << BIT_SHIFT_R_MAC_DBG_SEL_8197F) -#define BITS_R_MAC_DBG_SEL_8197F (BIT_MASK_R_MAC_DBG_SEL_8197F << BIT_SHIFT_R_MAC_DBG_SEL_8197F) +#define BIT_R_MAC_DBG_SEL_8197F(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL_8197F) << BIT_SHIFT_R_MAC_DBG_SEL_8197F) +#define BITS_R_MAC_DBG_SEL_8197F \ + (BIT_MASK_R_MAC_DBG_SEL_8197F << BIT_SHIFT_R_MAC_DBG_SEL_8197F) #define BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) ((x) & (~BITS_R_MAC_DBG_SEL_8197F)) -#define BIT_GET_R_MAC_DBG_SEL_8197F(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8197F) & BIT_MASK_R_MAC_DBG_SEL_8197F) -#define BIT_SET_R_MAC_DBG_SEL_8197F(x, v) (BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) | BIT_R_MAC_DBG_SEL_8197F(v)) - +#define BIT_GET_R_MAC_DBG_SEL_8197F(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8197F) & BIT_MASK_R_MAC_DBG_SEL_8197F) +#define BIT_SET_R_MAC_DBG_SEL_8197F(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) | BIT_R_MAC_DBG_SEL_8197F(v)) /* 2 REG_SEC_OPT_V2_8197F */ #define BIT_MASK_IV_8197F BIT(18) @@ -13051,12 +17276,15 @@ #define BIT_SHIFT_BT_TIME_CNT_8197F 0 #define BIT_MASK_BT_TIME_CNT_8197F 0xff -#define BIT_BT_TIME_CNT_8197F(x) (((x) & BIT_MASK_BT_TIME_CNT_8197F) << BIT_SHIFT_BT_TIME_CNT_8197F) -#define BITS_BT_TIME_CNT_8197F (BIT_MASK_BT_TIME_CNT_8197F << BIT_SHIFT_BT_TIME_CNT_8197F) +#define BIT_BT_TIME_CNT_8197F(x) \ + (((x) & BIT_MASK_BT_TIME_CNT_8197F) << BIT_SHIFT_BT_TIME_CNT_8197F) +#define BITS_BT_TIME_CNT_8197F \ + (BIT_MASK_BT_TIME_CNT_8197F << BIT_SHIFT_BT_TIME_CNT_8197F) #define BIT_CLEAR_BT_TIME_CNT_8197F(x) ((x) & (~BITS_BT_TIME_CNT_8197F)) -#define BIT_GET_BT_TIME_CNT_8197F(x) (((x) >> BIT_SHIFT_BT_TIME_CNT_8197F) & BIT_MASK_BT_TIME_CNT_8197F) -#define BIT_SET_BT_TIME_CNT_8197F(x, v) (BIT_CLEAR_BT_TIME_CNT_8197F(x) | BIT_BT_TIME_CNT_8197F(v)) - +#define BIT_GET_BT_TIME_CNT_8197F(x) \ + (((x) >> BIT_SHIFT_BT_TIME_CNT_8197F) & BIT_MASK_BT_TIME_CNT_8197F) +#define BIT_SET_BT_TIME_CNT_8197F(x, v) \ + (BIT_CLEAR_BT_TIME_CNT_8197F(x) | BIT_BT_TIME_CNT_8197F(v)) /* 2 REG_RTS_ADDRESS_0_8197F */ diff --git a/hal/halmac/halmac_bit_8814b.h b/hal/halmac/halmac_bit_8814b.h index 5ce9102..0ffa133 100644 --- a/hal/halmac/halmac_bit_8814b.h +++ b/hal/halmac/halmac_bit_8814b.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_BIT_8814B_H #define __INC_HALMAC_BIT_8814B_H @@ -7,7 +22,8 @@ /* 2 REG_SYS_ISO_CTRL_8814B */ #define BIT_PWC_EV12V_8814B BIT(15) -#define BIT_PWC_EV25V_8814B BIT(14) + +/* 2 REG_NOT_VALID_8814B */ #define BIT_PA33V_EN_8814B BIT(13) #define BIT_PA12V_EN_8814B BIT(12) #define BIT_UA33V_EN_8814B BIT(11) @@ -26,7 +42,8 @@ /* 2 REG_SYS_FUNC_EN_8814B */ #define BIT_FEN_MREGEN_8814B BIT(15) #define BIT_FEN_HWPDN_8814B BIT(14) -#define BIT_EN_25_1_8814B BIT(13) + +/* 2 REG_NOT_VALID_8814B */ #define BIT_FEN_ELDR_8814B BIT(12) #define BIT_FEN_DCORE_8814B BIT(11) #define BIT_FEN_CPUEN_8814B BIT(10) @@ -63,14 +80,15 @@ #define BIT_APFN_ONMAC_8814B BIT(8) #define BIT_CHIP_PDN_EN_8814B BIT(7) #define BIT_RDY_MACDIS_8814B BIT(6) -#define BIT_RING_CLK_12M_EN_8814B BIT(4) + +/* 2 REG_NOT_VALID_8814B */ #define BIT_PFM_WOWL_8814B BIT(3) #define BIT_PFM_LDKP_8814B BIT(2) #define BIT_WL_HCI_ALD_8814B BIT(1) #define BIT_PFM_LDALL_8814B BIT(0) /* 2 REG_SYS_CLK_CTRL_8814B */ -#define BIT_LDO_DUMMY_8814B BIT(15) +#define BIT_DATA_CPU_CLK_EN_8814B BIT(15) #define BIT_CPU_CLK_EN_8814B BIT(14) #define BIT_SYMREG_CLK_EN_8814B BIT(13) #define BIT_HCI_CLK_EN_8814B BIT(12) @@ -84,23 +102,33 @@ #define BIT_MACSLP_8814B BIT(4) #define BIT_WAKEPAD_EN_8814B BIT(3) #define BIT_ROMD16V_EN_8814B BIT(2) -#define BIT_CKANA12M_EN_8814B BIT(1) + +/* 2 REG_NOT_VALID_8814B */ #define BIT_CNTD16V_EN_8814B BIT(0) /* 2 REG_SYS_EEPROM_CTRL_8814B */ #define BIT_SHIFT_VPDIDX_8814B 8 #define BIT_MASK_VPDIDX_8814B 0xff -#define BIT_VPDIDX_8814B(x) (((x) & BIT_MASK_VPDIDX_8814B) << BIT_SHIFT_VPDIDX_8814B) -#define BIT_GET_VPDIDX_8814B(x) (((x) >> BIT_SHIFT_VPDIDX_8814B) & BIT_MASK_VPDIDX_8814B) - - +#define BIT_VPDIDX_8814B(x) \ + (((x) & BIT_MASK_VPDIDX_8814B) << BIT_SHIFT_VPDIDX_8814B) +#define BITS_VPDIDX_8814B (BIT_MASK_VPDIDX_8814B << BIT_SHIFT_VPDIDX_8814B) +#define BIT_CLEAR_VPDIDX_8814B(x) ((x) & (~BITS_VPDIDX_8814B)) +#define BIT_GET_VPDIDX_8814B(x) \ + (((x) >> BIT_SHIFT_VPDIDX_8814B) & BIT_MASK_VPDIDX_8814B) +#define BIT_SET_VPDIDX_8814B(x, v) \ + (BIT_CLEAR_VPDIDX_8814B(x) | BIT_VPDIDX_8814B(v)) #define BIT_SHIFT_EEM1_0_8814B 6 #define BIT_MASK_EEM1_0_8814B 0x3 -#define BIT_EEM1_0_8814B(x) (((x) & BIT_MASK_EEM1_0_8814B) << BIT_SHIFT_EEM1_0_8814B) -#define BIT_GET_EEM1_0_8814B(x) (((x) >> BIT_SHIFT_EEM1_0_8814B) & BIT_MASK_EEM1_0_8814B) - +#define BIT_EEM1_0_8814B(x) \ + (((x) & BIT_MASK_EEM1_0_8814B) << BIT_SHIFT_EEM1_0_8814B) +#define BITS_EEM1_0_8814B (BIT_MASK_EEM1_0_8814B << BIT_SHIFT_EEM1_0_8814B) +#define BIT_CLEAR_EEM1_0_8814B(x) ((x) & (~BITS_EEM1_0_8814B)) +#define BIT_GET_EEM1_0_8814B(x) \ + (((x) >> BIT_SHIFT_EEM1_0_8814B) & BIT_MASK_EEM1_0_8814B) +#define BIT_SET_EEM1_0_8814B(x, v) \ + (BIT_CLEAR_EEM1_0_8814B(x) | BIT_EEM1_0_8814B(v)) #define BIT_AUTOLOAD_SUS_8814B BIT(5) #define BIT_EERPOMSEL_8814B BIT(4) @@ -113,150 +141,126 @@ #define BIT_SHIFT_VPD_DATA_8814B 0 #define BIT_MASK_VPD_DATA_8814B 0xffffffffL -#define BIT_VPD_DATA_8814B(x) (((x) & BIT_MASK_VPD_DATA_8814B) << BIT_SHIFT_VPD_DATA_8814B) -#define BIT_GET_VPD_DATA_8814B(x) (((x) >> BIT_SHIFT_VPD_DATA_8814B) & BIT_MASK_VPD_DATA_8814B) - - +#define BIT_VPD_DATA_8814B(x) \ + (((x) & BIT_MASK_VPD_DATA_8814B) << BIT_SHIFT_VPD_DATA_8814B) +#define BITS_VPD_DATA_8814B \ + (BIT_MASK_VPD_DATA_8814B << BIT_SHIFT_VPD_DATA_8814B) +#define BIT_CLEAR_VPD_DATA_8814B(x) ((x) & (~BITS_VPD_DATA_8814B)) +#define BIT_GET_VPD_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_VPD_DATA_8814B) & BIT_MASK_VPD_DATA_8814B) +#define BIT_SET_VPD_DATA_8814B(x, v) \ + (BIT_CLEAR_VPD_DATA_8814B(x) | BIT_VPD_DATA_8814B(v)) /* 2 REG_SYS_SWR_CTRL1_8814B */ -#define BIT_C2_L_BIT0_8814B BIT(31) - -#define BIT_SHIFT_C1_L_8814B 29 -#define BIT_MASK_C1_L_8814B 0x3 -#define BIT_C1_L_8814B(x) (((x) & BIT_MASK_C1_L_8814B) << BIT_SHIFT_C1_L_8814B) -#define BIT_GET_C1_L_8814B(x) (((x) >> BIT_SHIFT_C1_L_8814B) & BIT_MASK_C1_L_8814B) - +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG_FREQ_L_8814B 25 -#define BIT_MASK_REG_FREQ_L_8814B 0x7 -#define BIT_REG_FREQ_L_8814B(x) (((x) & BIT_MASK_REG_FREQ_L_8814B) << BIT_SHIFT_REG_FREQ_L_8814B) -#define BIT_GET_REG_FREQ_L_8814B(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8814B) & BIT_MASK_REG_FREQ_L_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_EN_DUTY_8814B BIT(24) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG_MODE_8814B 22 -#define BIT_MASK_REG_MODE_8814B 0x3 -#define BIT_REG_MODE_8814B(x) (((x) & BIT_MASK_REG_MODE_8814B) << BIT_SHIFT_REG_MODE_8814B) -#define BIT_GET_REG_MODE_8814B(x) (((x) >> BIT_SHIFT_REG_MODE_8814B) & BIT_MASK_REG_MODE_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_EN_SP_8814B BIT(21) -#define BIT_REG_AUTO_L_8814B BIT(20) -#define BIT_SW18_SELD_BIT0_8814B BIT(19) -#define BIT_SW18_POWOCP_8814B BIT(18) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_OCP_L1_8814B 15 -#define BIT_MASK_OCP_L1_8814B 0x7 -#define BIT_OCP_L1_8814B(x) (((x) & BIT_MASK_OCP_L1_8814B) << BIT_SHIFT_OCP_L1_8814B) -#define BIT_GET_OCP_L1_8814B(x) (((x) >> BIT_SHIFT_OCP_L1_8814B) & BIT_MASK_OCP_L1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CF_L_8814B 13 -#define BIT_MASK_CF_L_8814B 0x3 -#define BIT_CF_L_8814B(x) (((x) & BIT_MASK_CF_L_8814B) << BIT_SHIFT_CF_L_8814B) -#define BIT_GET_CF_L_8814B(x) (((x) >> BIT_SHIFT_CF_L_8814B) & BIT_MASK_CF_L_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CTRL_SPS_PWM_FREQ_8814B BIT(10) -#define BIT_SW18_FPWM_8814B BIT(11) -#define BIT_SW18_SWEN_8814B BIT(9) -#define BIT_SW18_LDEN_8814B BIT(8) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_DISABLE_OPEN_SPS_LDO_8814B BIT(8) #define BIT_MAC_ID_EN_8814B BIT(7) -#define BIT_AFE_BGEN_8814B BIT(0) - -/* 2 REG_SYS_SWR_CTRL2_8814B */ -#define BIT_POW_ZCD_L_8814B BIT(31) -#define BIT_AUTOZCD_L_8814B BIT(30) - -#define BIT_SHIFT_REG_DELAY_8814B 28 -#define BIT_MASK_REG_DELAY_8814B 0x3 -#define BIT_REG_DELAY_8814B(x) (((x) & BIT_MASK_REG_DELAY_8814B) << BIT_SHIFT_REG_DELAY_8814B) -#define BIT_GET_REG_DELAY_8814B(x) (((x) >> BIT_SHIFT_REG_DELAY_8814B) & BIT_MASK_REG_DELAY_8814B) - - - -#define BIT_SHIFT_V15ADJ_L1_V1_8814B 24 -#define BIT_MASK_V15ADJ_L1_V1_8814B 0x7 -#define BIT_V15ADJ_L1_V1_8814B(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8814B) << BIT_SHIFT_V15ADJ_L1_V1_8814B) -#define BIT_GET_V15ADJ_L1_V1_8814B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8814B) & BIT_MASK_V15ADJ_L1_V1_8814B) - - - -#define BIT_SHIFT_VOL_L1_V1_8814B 20 -#define BIT_MASK_VOL_L1_V1_8814B 0xf -#define BIT_VOL_L1_V1_8814B(x) (((x) & BIT_MASK_VOL_L1_V1_8814B) << BIT_SHIFT_VOL_L1_V1_8814B) -#define BIT_GET_VOL_L1_V1_8814B(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8814B) & BIT_MASK_VOL_L1_V1_8814B) - - - -#define BIT_SHIFT_IN_L1_V1_8814B 17 -#define BIT_MASK_IN_L1_V1_8814B 0x7 -#define BIT_IN_L1_V1_8814B(x) (((x) & BIT_MASK_IN_L1_V1_8814B) << BIT_SHIFT_IN_L1_V1_8814B) -#define BIT_GET_IN_L1_V1_8814B(x) (((x) >> BIT_SHIFT_IN_L1_V1_8814B) & BIT_MASK_IN_L1_V1_8814B) +#define BIT_WL_CTRL_XTAL_CADJ_8814B BIT(6) +#define BIT_AFE_BGEN_PCIE_OP_8814B BIT(2) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_SYS_SWR_CTRL2_8814B */ -#define BIT_SHIFT_TBOX_L1_8814B 15 -#define BIT_MASK_TBOX_L1_8814B 0x3 -#define BIT_TBOX_L1_8814B(x) (((x) & BIT_MASK_TBOX_L1_8814B) << BIT_SHIFT_TBOX_L1_8814B) -#define BIT_GET_TBOX_L1_8814B(x) (((x) >> BIT_SHIFT_TBOX_L1_8814B) & BIT_MASK_TBOX_L1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SW18_SEL_8814B BIT(13) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SW18_SD_8814B BIT(10) -#define BIT_SHIFT_R3_L_8814B 7 -#define BIT_MASK_R3_L_8814B 0x3 -#define BIT_R3_L_8814B(x) (((x) & BIT_MASK_R3_L_8814B) << BIT_SHIFT_R3_L_8814B) -#define BIT_GET_R3_L_8814B(x) (((x) >> BIT_SHIFT_R3_L_8814B) & BIT_MASK_R3_L_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SW18_R2_8814B 5 -#define BIT_MASK_SW18_R2_8814B 0x3 -#define BIT_SW18_R2_8814B(x) (((x) & BIT_MASK_SW18_R2_8814B) << BIT_SHIFT_SW18_R2_8814B) -#define BIT_GET_SW18_R2_8814B(x) (((x) >> BIT_SHIFT_SW18_R2_8814B) & BIT_MASK_SW18_R2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SW18_R1_8814B 3 -#define BIT_MASK_SW18_R1_8814B 0x3 -#define BIT_SW18_R1_8814B(x) (((x) & BIT_MASK_SW18_R1_8814B) << BIT_SHIFT_SW18_R1_8814B) -#define BIT_GET_SW18_R1_8814B(x) (((x) >> BIT_SHIFT_SW18_R1_8814B) & BIT_MASK_SW18_R1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_C3_L_C3_8814B 1 -#define BIT_MASK_C3_L_C3_8814B 0x3 -#define BIT_C3_L_C3_8814B(x) (((x) & BIT_MASK_C3_L_C3_8814B) << BIT_SHIFT_C3_L_C3_8814B) -#define BIT_GET_C3_L_C3_8814B(x) (((x) >> BIT_SHIFT_C3_L_C3_8814B) & BIT_MASK_C3_L_C3_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_C2_L_BIT1_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_SYS_SWR_CTRL3_8814B */ #define BIT_SPS18_OCP_DIS_8814B BIT(31) #define BIT_SHIFT_SPS18_OCP_TH_8814B 16 #define BIT_MASK_SPS18_OCP_TH_8814B 0x7fff -#define BIT_SPS18_OCP_TH_8814B(x) (((x) & BIT_MASK_SPS18_OCP_TH_8814B) << BIT_SHIFT_SPS18_OCP_TH_8814B) -#define BIT_GET_SPS18_OCP_TH_8814B(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8814B) & BIT_MASK_SPS18_OCP_TH_8814B) - - +#define BIT_SPS18_OCP_TH_8814B(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH_8814B) << BIT_SHIFT_SPS18_OCP_TH_8814B) +#define BITS_SPS18_OCP_TH_8814B \ + (BIT_MASK_SPS18_OCP_TH_8814B << BIT_SHIFT_SPS18_OCP_TH_8814B) +#define BIT_CLEAR_SPS18_OCP_TH_8814B(x) ((x) & (~BITS_SPS18_OCP_TH_8814B)) +#define BIT_GET_SPS18_OCP_TH_8814B(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH_8814B) & BIT_MASK_SPS18_OCP_TH_8814B) +#define BIT_SET_SPS18_OCP_TH_8814B(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH_8814B(x) | BIT_SPS18_OCP_TH_8814B(v)) #define BIT_SHIFT_OCP_WINDOW_8814B 0 #define BIT_MASK_OCP_WINDOW_8814B 0xffff -#define BIT_OCP_WINDOW_8814B(x) (((x) & BIT_MASK_OCP_WINDOW_8814B) << BIT_SHIFT_OCP_WINDOW_8814B) -#define BIT_GET_OCP_WINDOW_8814B(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8814B) & BIT_MASK_OCP_WINDOW_8814B) +#define BIT_OCP_WINDOW_8814B(x) \ + (((x) & BIT_MASK_OCP_WINDOW_8814B) << BIT_SHIFT_OCP_WINDOW_8814B) +#define BITS_OCP_WINDOW_8814B \ + (BIT_MASK_OCP_WINDOW_8814B << BIT_SHIFT_OCP_WINDOW_8814B) +#define BIT_CLEAR_OCP_WINDOW_8814B(x) ((x) & (~BITS_OCP_WINDOW_8814B)) +#define BIT_GET_OCP_WINDOW_8814B(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW_8814B) & BIT_MASK_OCP_WINDOW_8814B) +#define BIT_SET_OCP_WINDOW_8814B(x, v) \ + (BIT_CLEAR_OCP_WINDOW_8814B(x) | BIT_OCP_WINDOW_8814B(v)) +/* 2 REG_RSV_CTRL_8814B */ +#define BIT_SHIFT_HREG_DBG_V1_8814B 12 +#define BIT_MASK_HREG_DBG_V1_8814B 0xfff +#define BIT_HREG_DBG_V1_8814B(x) \ + (((x) & BIT_MASK_HREG_DBG_V1_8814B) << BIT_SHIFT_HREG_DBG_V1_8814B) +#define BITS_HREG_DBG_V1_8814B \ + (BIT_MASK_HREG_DBG_V1_8814B << BIT_SHIFT_HREG_DBG_V1_8814B) +#define BIT_CLEAR_HREG_DBG_V1_8814B(x) ((x) & (~BITS_HREG_DBG_V1_8814B)) +#define BIT_GET_HREG_DBG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_HREG_DBG_V1_8814B) & BIT_MASK_HREG_DBG_V1_8814B) +#define BIT_SET_HREG_DBG_V1_8814B(x, v) \ + (BIT_CLEAR_HREG_DBG_V1_8814B(x) | BIT_HREG_DBG_V1_8814B(v)) -/* 2 REG_RSV_CTRL_8814B */ -#define BIT_HREG_DBG_8814B BIT(23) #define BIT_WLMCUIOIF_8814B BIT(8) #define BIT_LOCK_ALL_EN_8814B BIT(7) #define BIT_R_DIS_PRST_8814B BIT(6) @@ -274,306 +278,298 @@ /* 2 REG_AFE_LDO_CTRL_8814B */ -#define BIT_SHIFT_LPLDH12_RSV_8814B 29 -#define BIT_MASK_LPLDH12_RSV_8814B 0x7 -#define BIT_LPLDH12_RSV_8814B(x) (((x) & BIT_MASK_LPLDH12_RSV_8814B) << BIT_SHIFT_LPLDH12_RSV_8814B) -#define BIT_GET_LPLDH12_RSV_8814B(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8814B) & BIT_MASK_LPLDH12_RSV_8814B) - - -#define BIT_LPLDH12_SLP_8814B BIT(28) - -#define BIT_SHIFT_LPLDH12_VADJ_8814B 24 -#define BIT_MASK_LPLDH12_VADJ_8814B 0xf -#define BIT_LPLDH12_VADJ_8814B(x) (((x) & BIT_MASK_LPLDH12_VADJ_8814B) << BIT_SHIFT_LPLDH12_VADJ_8814B) -#define BIT_GET_LPLDH12_VADJ_8814B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8814B) & BIT_MASK_LPLDH12_VADJ_8814B) - +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CPHY_LDO_CL_EN_8814B BIT(19) +#define BIT_CPHY_LDO_OK_8814B BIT(18) #define BIT_PCIE_CALIB_EN_8814B BIT(17) #define BIT_LDH12_EN_8814B BIT(16) +#define BIT_DATA_CPU_PWC_8814B BIT(15) #define BIT_WLBBOFF_BIG_PWC_EN_8814B BIT(14) #define BIT_WLBBOFF_SMALL_PWC_EN_8814B BIT(13) #define BIT_WLMACOFF_BIG_PWC_EN_8814B BIT(12) #define BIT_WLPON_PWC_EN_8814B BIT(11) -#define BIT_POW_REGU_P1_8814B BIT(10) -#define BIT_LDOV12W_EN_8814B BIT(8) -#define BIT_EX_XTAL_DRV_DIGI_8814B BIT(7) -#define BIT_EX_XTAL_DRV_USB_8814B BIT(6) -#define BIT_EX_XTAL_DRV_AFE_8814B BIT(5) -#define BIT_EX_XTAL_DRV_RF2_8814B BIT(4) -#define BIT_EX_XTAL_DRV_RF1_8814B BIT(3) -#define BIT_POW_REGU_P0_8814B BIT(2) /* 2 REG_NOT_VALID_8814B */ -#define BIT_POW_PLL_LDO_8814B BIT(0) - -/* 2 REG_AFE_CTRL1_8814B */ -#define BIT_AGPIO_GPE_8814B BIT(31) - -#define BIT_SHIFT_XTAL_CAP_XI_8814B 25 -#define BIT_MASK_XTAL_CAP_XI_8814B 0x3f -#define BIT_XTAL_CAP_XI_8814B(x) (((x) & BIT_MASK_XTAL_CAP_XI_8814B) << BIT_SHIFT_XTAL_CAP_XI_8814B) -#define BIT_GET_XTAL_CAP_XI_8814B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8814B) & BIT_MASK_XTAL_CAP_XI_8814B) - - - -#define BIT_SHIFT_XTAL_DRV_DIGI_8814B 23 -#define BIT_MASK_XTAL_DRV_DIGI_8814B 0x3 -#define BIT_XTAL_DRV_DIGI_8814B(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8814B) << BIT_SHIFT_XTAL_DRV_DIGI_8814B) -#define BIT_GET_XTAL_DRV_DIGI_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8814B) & BIT_MASK_XTAL_DRV_DIGI_8814B) - - -#define BIT_XTAL_DRV_USB_BIT1_8814B BIT(22) - -#define BIT_SHIFT_MAC_CLK_SEL_8814B 20 -#define BIT_MASK_MAC_CLK_SEL_8814B 0x3 -#define BIT_MAC_CLK_SEL_8814B(x) (((x) & BIT_MASK_MAC_CLK_SEL_8814B) << BIT_SHIFT_MAC_CLK_SEL_8814B) -#define BIT_GET_MAC_CLK_SEL_8814B(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8814B) & BIT_MASK_MAC_CLK_SEL_8814B) - - -#define BIT_XTAL_DRV_USB_BIT0_8814B BIT(19) - -#define BIT_SHIFT_XTAL_DRV_AFE_8814B 17 -#define BIT_MASK_XTAL_DRV_AFE_8814B 0x3 -#define BIT_XTAL_DRV_AFE_8814B(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8814B) << BIT_SHIFT_XTAL_DRV_AFE_8814B) -#define BIT_GET_XTAL_DRV_AFE_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8814B) & BIT_MASK_XTAL_DRV_AFE_8814B) +#define BIT_LDOV12W_EN_8814B BIT(8) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_XTAL_DRV_RF2_8814B 15 -#define BIT_MASK_XTAL_DRV_RF2_8814B 0x3 -#define BIT_XTAL_DRV_RF2_8814B(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8814B) << BIT_SHIFT_XTAL_DRV_RF2_8814B) -#define BIT_GET_XTAL_DRV_RF2_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8814B) & BIT_MASK_XTAL_DRV_RF2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_XTAL_DRV_RF1_8814B 13 -#define BIT_MASK_XTAL_DRV_RF1_8814B 0x3 -#define BIT_XTAL_DRV_RF1_8814B(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8814B) << BIT_SHIFT_XTAL_DRV_RF1_8814B) -#define BIT_GET_XTAL_DRV_RF1_8814B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8814B) & BIT_MASK_XTAL_DRV_RF1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_XTAL_DELAY_DIGI_8814B BIT(12) -#define BIT_XTAL_DELAY_USB_8814B BIT(11) -#define BIT_XTAL_DELAY_AFE_8814B BIT(10) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_XTAL_LDO_VREF_8814B 7 -#define BIT_MASK_XTAL_LDO_VREF_8814B 0x7 -#define BIT_XTAL_LDO_VREF_8814B(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8814B) << BIT_SHIFT_XTAL_LDO_VREF_8814B) -#define BIT_GET_XTAL_LDO_VREF_8814B(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8814B) & BIT_MASK_XTAL_LDO_VREF_8814B) +/* 2 REG_AFE_CTRL1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_XTAL_XQSEL_RF_8814B BIT(6) -#define BIT_XTAL_XQSEL_8814B BIT(5) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_XTAL_GMN_V2_8814B 3 -#define BIT_MASK_XTAL_GMN_V2_8814B 0x3 -#define BIT_XTAL_GMN_V2_8814B(x) (((x) & BIT_MASK_XTAL_GMN_V2_8814B) << BIT_SHIFT_XTAL_GMN_V2_8814B) -#define BIT_GET_XTAL_GMN_V2_8814B(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8814B) & BIT_MASK_XTAL_GMN_V2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_MAC_CLK_SEL_8814B 20 +#define BIT_MASK_MAC_CLK_SEL_8814B 0x3 +#define BIT_MAC_CLK_SEL_8814B(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_8814B) << BIT_SHIFT_MAC_CLK_SEL_8814B) +#define BITS_MAC_CLK_SEL_8814B \ + (BIT_MASK_MAC_CLK_SEL_8814B << BIT_SHIFT_MAC_CLK_SEL_8814B) +#define BIT_CLEAR_MAC_CLK_SEL_8814B(x) ((x) & (~BITS_MAC_CLK_SEL_8814B)) +#define BIT_GET_MAC_CLK_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_8814B) & BIT_MASK_MAC_CLK_SEL_8814B) +#define BIT_SET_MAC_CLK_SEL_8814B(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_8814B(x) | BIT_MAC_CLK_SEL_8814B(v)) -#define BIT_SHIFT_XTAL_GMP_V2_8814B 1 -#define BIT_MASK_XTAL_GMP_V2_8814B 0x3 -#define BIT_XTAL_GMP_V2_8814B(x) (((x) & BIT_MASK_XTAL_GMP_V2_8814B) << BIT_SHIFT_XTAL_GMP_V2_8814B) -#define BIT_GET_XTAL_GMP_V2_8814B(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8814B) & BIT_MASK_XTAL_GMP_V2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_XTAL_EN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_AFE_CTRL2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG_C3_V4_8814B 30 -#define BIT_MASK_REG_C3_V4_8814B 0x3 -#define BIT_REG_C3_V4_8814B(x) (((x) & BIT_MASK_REG_C3_V4_8814B) << BIT_SHIFT_REG_C3_V4_8814B) -#define BIT_GET_REG_C3_V4_8814B(x) (((x) >> BIT_SHIFT_REG_C3_V4_8814B) & BIT_MASK_REG_C3_V4_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_CP_BIT1_8814B BIT(29) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG_RS_V4_8814B 26 -#define BIT_MASK_REG_RS_V4_8814B 0x7 -#define BIT_REG_RS_V4_8814B(x) (((x) & BIT_MASK_REG_RS_V4_8814B) << BIT_SHIFT_REG_RS_V4_8814B) -#define BIT_GET_REG_RS_V4_8814B(x) (((x) >> BIT_SHIFT_REG_RS_V4_8814B) & BIT_MASK_REG_RS_V4_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG__CS_8814B 24 -#define BIT_MASK_REG__CS_8814B 0x3 -#define BIT_REG__CS_8814B(x) (((x) & BIT_MASK_REG__CS_8814B) << BIT_SHIFT_REG__CS_8814B) -#define BIT_GET_REG__CS_8814B(x) (((x) >> BIT_SHIFT_REG__CS_8814B) & BIT_MASK_REG__CS_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_ANAPARSW_POW_MAC_8814B */ -#define BIT_SHIFT_REG_CP_OFFSET_8814B 21 -#define BIT_MASK_REG_CP_OFFSET_8814B 0x7 -#define BIT_REG_CP_OFFSET_8814B(x) (((x) & BIT_MASK_REG_CP_OFFSET_8814B) << BIT_SHIFT_REG_CP_OFFSET_8814B) -#define BIT_GET_REG_CP_OFFSET_8814B(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8814B) & BIT_MASK_REG_CP_OFFSET_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CP_BIAS_8814B 18 -#define BIT_MASK_CP_BIAS_8814B 0x7 -#define BIT_CP_BIAS_8814B(x) (((x) & BIT_MASK_CP_BIAS_8814B) << BIT_SHIFT_CP_BIAS_8814B) -#define BIT_GET_CP_BIAS_8814B(x) (((x) >> BIT_SHIFT_CP_BIAS_8814B) & BIT_MASK_CP_BIAS_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_ENB_LDO_DIODE_L_8814B BIT(3) +#define BIT_POW_LDO15_8814B BIT(2) +#define BIT_POW_SW_8814B BIT(1) +#define BIT_POW_LDO14_8814B BIT(0) +/* 2 REG_ANAPARLDO_POW_MAC_8814B */ -#define BIT_REG_IDOUBLE_V2_8814B BIT(17) -#define BIT_EN_SYN_8814B BIT(16) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_MCCO_8814B 14 -#define BIT_MASK_MCCO_8814B 0x3 -#define BIT_MCCO_8814B(x) (((x) & BIT_MASK_MCCO_8814B) << BIT_SHIFT_MCCO_8814B) -#define BIT_GET_MCCO_8814B(x) (((x) >> BIT_SHIFT_MCCO_8814B) & BIT_MASK_MCCO_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG_LDO_SEL_8814B 12 -#define BIT_MASK_REG_LDO_SEL_8814B 0x3 -#define BIT_REG_LDO_SEL_8814B(x) (((x) & BIT_MASK_REG_LDO_SEL_8814B) << BIT_SHIFT_REG_LDO_SEL_8814B) -#define BIT_GET_REG_LDO_SEL_8814B(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8814B) & BIT_MASK_REG_LDO_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_KVCO_V2_8814B BIT(10) -#define BIT_AGPIO_GPO_8814B BIT(9) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_LDOE25_POW_L_8814B BIT(0) -#define BIT_SHIFT_AGPIO_DRV_8814B 7 -#define BIT_MASK_AGPIO_DRV_8814B 0x3 -#define BIT_AGPIO_DRV_8814B(x) (((x) & BIT_MASK_AGPIO_DRV_8814B) << BIT_SHIFT_AGPIO_DRV_8814B) -#define BIT_GET_AGPIO_DRV_8814B(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8814B) & BIT_MASK_AGPIO_DRV_8814B) +/* 2 REG_ANAPAR_POW_MAC_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_POW_PC_LDO3_8814B BIT(5) +#define BIT_POW_PC_LDO2_8814B BIT(4) +#define BIT_POW_PC_LDO1_8814B BIT(3) +#define BIT_POW_PC_LDO0_8814B BIT(2) +#define BIT_POW_PLL_V1_8814B BIT(1) +#define BIT_POW_POWER_CUT_8814B BIT(0) -#define BIT_SHIFT_XTAL_CAP_XO_8814B 1 -#define BIT_MASK_XTAL_CAP_XO_8814B 0x3f -#define BIT_XTAL_CAP_XO_8814B(x) (((x) & BIT_MASK_XTAL_CAP_XO_8814B) << BIT_SHIFT_XTAL_CAP_XO_8814B) -#define BIT_GET_XTAL_CAP_XO_8814B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8814B) & BIT_MASK_XTAL_CAP_XO_8814B) +/* 2 REG_ANAPAR_POW_XTAL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_POW_PLL_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_AFE_CTRL3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_8814B 7 -#define BIT_MASK_PS_8814B 0x7 -#define BIT_PS_8814B(x) (((x) & BIT_MASK_PS_8814B) << BIT_SHIFT_PS_8814B) -#define BIT_GET_PS_8814B(x) (((x) >> BIT_SHIFT_PS_8814B) & BIT_MASK_PS_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_PSEN_8814B BIT(6) -#define BIT_DOGENB_8814B BIT(5) -#define BIT_REG_MBIAS_8814B BIT(4) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_POW_XTAL_8814B BIT(1) +#define BIT_POW_BG_8814B BIT(0) -#define BIT_SHIFT_REG_R3_V4_8814B 1 -#define BIT_MASK_REG_R3_V4_8814B 0x7 -#define BIT_REG_R3_V4_8814B(x) (((x) & BIT_MASK_REG_R3_V4_8814B) << BIT_SHIFT_REG_R3_V4_8814B) -#define BIT_GET_REG_R3_V4_8814B(x) (((x) >> BIT_SHIFT_REG_R3_V4_8814B) & BIT_MASK_REG_R3_V4_8814B) +/* 2 REG_ANAPARLDO_MAC_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_CP_BIT0_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_EFUSE_CTRL_8814B */ #define BIT_EF_FLAG_8814B BIT(31) #define BIT_SHIFT_EF_PGPD_8814B 28 #define BIT_MASK_EF_PGPD_8814B 0x7 -#define BIT_EF_PGPD_8814B(x) (((x) & BIT_MASK_EF_PGPD_8814B) << BIT_SHIFT_EF_PGPD_8814B) -#define BIT_GET_EF_PGPD_8814B(x) (((x) >> BIT_SHIFT_EF_PGPD_8814B) & BIT_MASK_EF_PGPD_8814B) - - +#define BIT_EF_PGPD_8814B(x) \ + (((x) & BIT_MASK_EF_PGPD_8814B) << BIT_SHIFT_EF_PGPD_8814B) +#define BITS_EF_PGPD_8814B (BIT_MASK_EF_PGPD_8814B << BIT_SHIFT_EF_PGPD_8814B) +#define BIT_CLEAR_EF_PGPD_8814B(x) ((x) & (~BITS_EF_PGPD_8814B)) +#define BIT_GET_EF_PGPD_8814B(x) \ + (((x) >> BIT_SHIFT_EF_PGPD_8814B) & BIT_MASK_EF_PGPD_8814B) +#define BIT_SET_EF_PGPD_8814B(x, v) \ + (BIT_CLEAR_EF_PGPD_8814B(x) | BIT_EF_PGPD_8814B(v)) #define BIT_SHIFT_EF_RDT_8814B 24 #define BIT_MASK_EF_RDT_8814B 0xf -#define BIT_EF_RDT_8814B(x) (((x) & BIT_MASK_EF_RDT_8814B) << BIT_SHIFT_EF_RDT_8814B) -#define BIT_GET_EF_RDT_8814B(x) (((x) >> BIT_SHIFT_EF_RDT_8814B) & BIT_MASK_EF_RDT_8814B) - - +#define BIT_EF_RDT_8814B(x) \ + (((x) & BIT_MASK_EF_RDT_8814B) << BIT_SHIFT_EF_RDT_8814B) +#define BITS_EF_RDT_8814B (BIT_MASK_EF_RDT_8814B << BIT_SHIFT_EF_RDT_8814B) +#define BIT_CLEAR_EF_RDT_8814B(x) ((x) & (~BITS_EF_RDT_8814B)) +#define BIT_GET_EF_RDT_8814B(x) \ + (((x) >> BIT_SHIFT_EF_RDT_8814B) & BIT_MASK_EF_RDT_8814B) +#define BIT_SET_EF_RDT_8814B(x, v) \ + (BIT_CLEAR_EF_RDT_8814B(x) | BIT_EF_RDT_8814B(v)) #define BIT_SHIFT_EF_PGTS_8814B 20 #define BIT_MASK_EF_PGTS_8814B 0xf -#define BIT_EF_PGTS_8814B(x) (((x) & BIT_MASK_EF_PGTS_8814B) << BIT_SHIFT_EF_PGTS_8814B) -#define BIT_GET_EF_PGTS_8814B(x) (((x) >> BIT_SHIFT_EF_PGTS_8814B) & BIT_MASK_EF_PGTS_8814B) - +#define BIT_EF_PGTS_8814B(x) \ + (((x) & BIT_MASK_EF_PGTS_8814B) << BIT_SHIFT_EF_PGTS_8814B) +#define BITS_EF_PGTS_8814B (BIT_MASK_EF_PGTS_8814B << BIT_SHIFT_EF_PGTS_8814B) +#define BIT_CLEAR_EF_PGTS_8814B(x) ((x) & (~BITS_EF_PGTS_8814B)) +#define BIT_GET_EF_PGTS_8814B(x) \ + (((x) >> BIT_SHIFT_EF_PGTS_8814B) & BIT_MASK_EF_PGTS_8814B) +#define BIT_SET_EF_PGTS_8814B(x, v) \ + (BIT_CLEAR_EF_PGTS_8814B(x) | BIT_EF_PGTS_8814B(v)) #define BIT_EF_PDWN_8814B BIT(19) #define BIT_EF_ALDEN_8814B BIT(18) #define BIT_SHIFT_EF_ADDR_8814B 8 #define BIT_MASK_EF_ADDR_8814B 0x3ff -#define BIT_EF_ADDR_8814B(x) (((x) & BIT_MASK_EF_ADDR_8814B) << BIT_SHIFT_EF_ADDR_8814B) -#define BIT_GET_EF_ADDR_8814B(x) (((x) >> BIT_SHIFT_EF_ADDR_8814B) & BIT_MASK_EF_ADDR_8814B) - - +#define BIT_EF_ADDR_8814B(x) \ + (((x) & BIT_MASK_EF_ADDR_8814B) << BIT_SHIFT_EF_ADDR_8814B) +#define BITS_EF_ADDR_8814B (BIT_MASK_EF_ADDR_8814B << BIT_SHIFT_EF_ADDR_8814B) +#define BIT_CLEAR_EF_ADDR_8814B(x) ((x) & (~BITS_EF_ADDR_8814B)) +#define BIT_GET_EF_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_EF_ADDR_8814B) & BIT_MASK_EF_ADDR_8814B) +#define BIT_SET_EF_ADDR_8814B(x, v) \ + (BIT_CLEAR_EF_ADDR_8814B(x) | BIT_EF_ADDR_8814B(v)) #define BIT_SHIFT_EF_DATA_8814B 0 #define BIT_MASK_EF_DATA_8814B 0xff -#define BIT_EF_DATA_8814B(x) (((x) & BIT_MASK_EF_DATA_8814B) << BIT_SHIFT_EF_DATA_8814B) -#define BIT_GET_EF_DATA_8814B(x) (((x) >> BIT_SHIFT_EF_DATA_8814B) & BIT_MASK_EF_DATA_8814B) - - +#define BIT_EF_DATA_8814B(x) \ + (((x) & BIT_MASK_EF_DATA_8814B) << BIT_SHIFT_EF_DATA_8814B) +#define BITS_EF_DATA_8814B (BIT_MASK_EF_DATA_8814B << BIT_SHIFT_EF_DATA_8814B) +#define BIT_CLEAR_EF_DATA_8814B(x) ((x) & (~BITS_EF_DATA_8814B)) +#define BIT_GET_EF_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_EF_DATA_8814B) & BIT_MASK_EF_DATA_8814B) +#define BIT_SET_EF_DATA_8814B(x, v) \ + (BIT_CLEAR_EF_DATA_8814B(x) | BIT_EF_DATA_8814B(v)) /* 2 REG_LDO_EFUSE_CTRL_8814B */ -#define BIT_LDOE25_EN_8814B BIT(31) - -#define BIT_SHIFT_LDOE25_V12ADJ_L_8814B 27 -#define BIT_MASK_LDOE25_V12ADJ_L_8814B 0xf -#define BIT_LDOE25_V12ADJ_L_8814B(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8814B) << BIT_SHIFT_LDOE25_V12ADJ_L_8814B) -#define BIT_GET_LDOE25_V12ADJ_L_8814B(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8814B) & BIT_MASK_LDOE25_V12ADJ_L_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ #define BIT_EF_CRES_SEL_8814B BIT(26) #define BIT_SHIFT_EF_SCAN_START_V1_8814B 16 #define BIT_MASK_EF_SCAN_START_V1_8814B 0x3ff -#define BIT_EF_SCAN_START_V1_8814B(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8814B) << BIT_SHIFT_EF_SCAN_START_V1_8814B) -#define BIT_GET_EF_SCAN_START_V1_8814B(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8814B) & BIT_MASK_EF_SCAN_START_V1_8814B) - - +#define BIT_EF_SCAN_START_V1_8814B(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1_8814B) \ + << BIT_SHIFT_EF_SCAN_START_V1_8814B) +#define BITS_EF_SCAN_START_V1_8814B \ + (BIT_MASK_EF_SCAN_START_V1_8814B << BIT_SHIFT_EF_SCAN_START_V1_8814B) +#define BIT_CLEAR_EF_SCAN_START_V1_8814B(x) \ + ((x) & (~BITS_EF_SCAN_START_V1_8814B)) +#define BIT_GET_EF_SCAN_START_V1_8814B(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8814B) & \ + BIT_MASK_EF_SCAN_START_V1_8814B) +#define BIT_SET_EF_SCAN_START_V1_8814B(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1_8814B(x) | BIT_EF_SCAN_START_V1_8814B(v)) #define BIT_SHIFT_EF_SCAN_END_8814B 12 #define BIT_MASK_EF_SCAN_END_8814B 0xf -#define BIT_EF_SCAN_END_8814B(x) (((x) & BIT_MASK_EF_SCAN_END_8814B) << BIT_SHIFT_EF_SCAN_END_8814B) -#define BIT_GET_EF_SCAN_END_8814B(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8814B) & BIT_MASK_EF_SCAN_END_8814B) - +#define BIT_EF_SCAN_END_8814B(x) \ + (((x) & BIT_MASK_EF_SCAN_END_8814B) << BIT_SHIFT_EF_SCAN_END_8814B) +#define BITS_EF_SCAN_END_8814B \ + (BIT_MASK_EF_SCAN_END_8814B << BIT_SHIFT_EF_SCAN_END_8814B) +#define BIT_CLEAR_EF_SCAN_END_8814B(x) ((x) & (~BITS_EF_SCAN_END_8814B)) +#define BIT_GET_EF_SCAN_END_8814B(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END_8814B) & BIT_MASK_EF_SCAN_END_8814B) +#define BIT_SET_EF_SCAN_END_8814B(x, v) \ + (BIT_CLEAR_EF_SCAN_END_8814B(x) | BIT_EF_SCAN_END_8814B(v)) #define BIT_EF_PD_DIS_8814B BIT(11) #define BIT_SHIFT_EF_CELL_SEL_8814B 8 #define BIT_MASK_EF_CELL_SEL_8814B 0x3 -#define BIT_EF_CELL_SEL_8814B(x) (((x) & BIT_MASK_EF_CELL_SEL_8814B) << BIT_SHIFT_EF_CELL_SEL_8814B) -#define BIT_GET_EF_CELL_SEL_8814B(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8814B) & BIT_MASK_EF_CELL_SEL_8814B) - +#define BIT_EF_CELL_SEL_8814B(x) \ + (((x) & BIT_MASK_EF_CELL_SEL_8814B) << BIT_SHIFT_EF_CELL_SEL_8814B) +#define BITS_EF_CELL_SEL_8814B \ + (BIT_MASK_EF_CELL_SEL_8814B << BIT_SHIFT_EF_CELL_SEL_8814B) +#define BIT_CLEAR_EF_CELL_SEL_8814B(x) ((x) & (~BITS_EF_CELL_SEL_8814B)) +#define BIT_GET_EF_CELL_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL_8814B) & BIT_MASK_EF_CELL_SEL_8814B) +#define BIT_SET_EF_CELL_SEL_8814B(x, v) \ + (BIT_CLEAR_EF_CELL_SEL_8814B(x) | BIT_EF_CELL_SEL_8814B(v)) #define BIT_EF_TRPT_8814B BIT(7) #define BIT_SHIFT_EF_TTHD_8814B 0 #define BIT_MASK_EF_TTHD_8814B 0x7f -#define BIT_EF_TTHD_8814B(x) (((x) & BIT_MASK_EF_TTHD_8814B) << BIT_SHIFT_EF_TTHD_8814B) -#define BIT_GET_EF_TTHD_8814B(x) (((x) >> BIT_SHIFT_EF_TTHD_8814B) & BIT_MASK_EF_TTHD_8814B) - - +#define BIT_EF_TTHD_8814B(x) \ + (((x) & BIT_MASK_EF_TTHD_8814B) << BIT_SHIFT_EF_TTHD_8814B) +#define BITS_EF_TTHD_8814B (BIT_MASK_EF_TTHD_8814B << BIT_SHIFT_EF_TTHD_8814B) +#define BIT_CLEAR_EF_TTHD_8814B(x) ((x) & (~BITS_EF_TTHD_8814B)) +#define BIT_GET_EF_TTHD_8814B(x) \ + (((x) >> BIT_SHIFT_EF_TTHD_8814B) & BIT_MASK_EF_TTHD_8814B) +#define BIT_SET_EF_TTHD_8814B(x, v) \ + (BIT_CLEAR_EF_TTHD_8814B(x) | BIT_EF_TTHD_8814B(v)) /* 2 REG_PWR_OPTION_CTRL_8814B */ #define BIT_SHIFT_DBG_SEL_V1_8814B 16 #define BIT_MASK_DBG_SEL_V1_8814B 0xff -#define BIT_DBG_SEL_V1_8814B(x) (((x) & BIT_MASK_DBG_SEL_V1_8814B) << BIT_SHIFT_DBG_SEL_V1_8814B) -#define BIT_GET_DBG_SEL_V1_8814B(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8814B) & BIT_MASK_DBG_SEL_V1_8814B) - - +#define BIT_DBG_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_DBG_SEL_V1_8814B) << BIT_SHIFT_DBG_SEL_V1_8814B) +#define BITS_DBG_SEL_V1_8814B \ + (BIT_MASK_DBG_SEL_V1_8814B << BIT_SHIFT_DBG_SEL_V1_8814B) +#define BIT_CLEAR_DBG_SEL_V1_8814B(x) ((x) & (~BITS_DBG_SEL_V1_8814B)) +#define BIT_GET_DBG_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1_8814B) & BIT_MASK_DBG_SEL_V1_8814B) +#define BIT_SET_DBG_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_DBG_SEL_V1_8814B(x) | BIT_DBG_SEL_V1_8814B(v)) #define BIT_SHIFT_DBG_SEL_BYTE_8814B 14 #define BIT_MASK_DBG_SEL_BYTE_8814B 0x3 -#define BIT_DBG_SEL_BYTE_8814B(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8814B) << BIT_SHIFT_DBG_SEL_BYTE_8814B) -#define BIT_GET_DBG_SEL_BYTE_8814B(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8814B) & BIT_MASK_DBG_SEL_BYTE_8814B) - - - -#define BIT_SHIFT_STD_L1_V1_8814B 12 -#define BIT_MASK_STD_L1_V1_8814B 0x3 -#define BIT_STD_L1_V1_8814B(x) (((x) & BIT_MASK_STD_L1_V1_8814B) << BIT_SHIFT_STD_L1_V1_8814B) -#define BIT_GET_STD_L1_V1_8814B(x) (((x) >> BIT_SHIFT_STD_L1_V1_8814B) & BIT_MASK_STD_L1_V1_8814B) - +#define BIT_DBG_SEL_BYTE_8814B(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE_8814B) << BIT_SHIFT_DBG_SEL_BYTE_8814B) +#define BITS_DBG_SEL_BYTE_8814B \ + (BIT_MASK_DBG_SEL_BYTE_8814B << BIT_SHIFT_DBG_SEL_BYTE_8814B) +#define BIT_CLEAR_DBG_SEL_BYTE_8814B(x) ((x) & (~BITS_DBG_SEL_BYTE_8814B)) +#define BIT_GET_DBG_SEL_BYTE_8814B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8814B) & BIT_MASK_DBG_SEL_BYTE_8814B) +#define BIT_SET_DBG_SEL_BYTE_8814B(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE_8814B(x) | BIT_DBG_SEL_BYTE_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ #define BIT_SYSON_DBG_PAD_E2_8814B BIT(11) #define BIT_SYSON_LED_PAD_E2_8814B BIT(10) #define BIT_SYSON_GPEE_PAD_E2_8814B BIT(9) @@ -582,60 +578,110 @@ #define BIT_SHIFT_SYSON_SPS0WWV_WT_8814B 4 #define BIT_MASK_SYSON_SPS0WWV_WT_8814B 0x3 -#define BIT_SYSON_SPS0WWV_WT_8814B(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8814B) << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) -#define BIT_GET_SYSON_SPS0WWV_WT_8814B(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) & BIT_MASK_SYSON_SPS0WWV_WT_8814B) - - +#define BIT_SYSON_SPS0WWV_WT_8814B(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8814B) \ + << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) +#define BITS_SYSON_SPS0WWV_WT_8814B \ + (BIT_MASK_SYSON_SPS0WWV_WT_8814B << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) +#define BIT_CLEAR_SYSON_SPS0WWV_WT_8814B(x) \ + ((x) & (~BITS_SYSON_SPS0WWV_WT_8814B)) +#define BIT_GET_SYSON_SPS0WWV_WT_8814B(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) & \ + BIT_MASK_SYSON_SPS0WWV_WT_8814B) +#define BIT_SET_SYSON_SPS0WWV_WT_8814B(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT_8814B(x) | BIT_SYSON_SPS0WWV_WT_8814B(v)) #define BIT_SHIFT_SYSON_SPS0LDO_WT_8814B 2 #define BIT_MASK_SYSON_SPS0LDO_WT_8814B 0x3 -#define BIT_SYSON_SPS0LDO_WT_8814B(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8814B) << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) -#define BIT_GET_SYSON_SPS0LDO_WT_8814B(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) & BIT_MASK_SYSON_SPS0LDO_WT_8814B) - - +#define BIT_SYSON_SPS0LDO_WT_8814B(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8814B) \ + << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) +#define BITS_SYSON_SPS0LDO_WT_8814B \ + (BIT_MASK_SYSON_SPS0LDO_WT_8814B << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) +#define BIT_CLEAR_SYSON_SPS0LDO_WT_8814B(x) \ + ((x) & (~BITS_SYSON_SPS0LDO_WT_8814B)) +#define BIT_GET_SYSON_SPS0LDO_WT_8814B(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) & \ + BIT_MASK_SYSON_SPS0LDO_WT_8814B) +#define BIT_SET_SYSON_SPS0LDO_WT_8814B(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT_8814B(x) | BIT_SYSON_SPS0LDO_WT_8814B(v)) #define BIT_SHIFT_SYSON_RCLK_SCALE_8814B 0 #define BIT_MASK_SYSON_RCLK_SCALE_8814B 0x3 -#define BIT_SYSON_RCLK_SCALE_8814B(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8814B) << BIT_SHIFT_SYSON_RCLK_SCALE_8814B) -#define BIT_GET_SYSON_RCLK_SCALE_8814B(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8814B) & BIT_MASK_SYSON_RCLK_SCALE_8814B) - - +#define BIT_SYSON_RCLK_SCALE_8814B(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE_8814B) \ + << BIT_SHIFT_SYSON_RCLK_SCALE_8814B) +#define BITS_SYSON_RCLK_SCALE_8814B \ + (BIT_MASK_SYSON_RCLK_SCALE_8814B << BIT_SHIFT_SYSON_RCLK_SCALE_8814B) +#define BIT_CLEAR_SYSON_RCLK_SCALE_8814B(x) \ + ((x) & (~BITS_SYSON_RCLK_SCALE_8814B)) +#define BIT_GET_SYSON_RCLK_SCALE_8814B(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8814B) & \ + BIT_MASK_SYSON_RCLK_SCALE_8814B) +#define BIT_SET_SYSON_RCLK_SCALE_8814B(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE_8814B(x) | BIT_SYSON_RCLK_SCALE_8814B(v)) /* 2 REG_CAL_TIMER_8814B */ #define BIT_SHIFT_MATCH_CNT_8814B 8 #define BIT_MASK_MATCH_CNT_8814B 0xff -#define BIT_MATCH_CNT_8814B(x) (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B) -#define BIT_GET_MATCH_CNT_8814B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B) - - +#define BIT_MATCH_CNT_8814B(x) \ + (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B) +#define BITS_MATCH_CNT_8814B \ + (BIT_MASK_MATCH_CNT_8814B << BIT_SHIFT_MATCH_CNT_8814B) +#define BIT_CLEAR_MATCH_CNT_8814B(x) ((x) & (~BITS_MATCH_CNT_8814B)) +#define BIT_GET_MATCH_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B) +#define BIT_SET_MATCH_CNT_8814B(x, v) \ + (BIT_CLEAR_MATCH_CNT_8814B(x) | BIT_MATCH_CNT_8814B(v)) #define BIT_SHIFT_CAL_SCAL_8814B 0 #define BIT_MASK_CAL_SCAL_8814B 0xff -#define BIT_CAL_SCAL_8814B(x) (((x) & BIT_MASK_CAL_SCAL_8814B) << BIT_SHIFT_CAL_SCAL_8814B) -#define BIT_GET_CAL_SCAL_8814B(x) (((x) >> BIT_SHIFT_CAL_SCAL_8814B) & BIT_MASK_CAL_SCAL_8814B) - - +#define BIT_CAL_SCAL_8814B(x) \ + (((x) & BIT_MASK_CAL_SCAL_8814B) << BIT_SHIFT_CAL_SCAL_8814B) +#define BITS_CAL_SCAL_8814B \ + (BIT_MASK_CAL_SCAL_8814B << BIT_SHIFT_CAL_SCAL_8814B) +#define BIT_CLEAR_CAL_SCAL_8814B(x) ((x) & (~BITS_CAL_SCAL_8814B)) +#define BIT_GET_CAL_SCAL_8814B(x) \ + (((x) >> BIT_SHIFT_CAL_SCAL_8814B) & BIT_MASK_CAL_SCAL_8814B) +#define BIT_SET_CAL_SCAL_8814B(x, v) \ + (BIT_CLEAR_CAL_SCAL_8814B(x) | BIT_CAL_SCAL_8814B(v)) /* 2 REG_ACLK_MON_8814B */ #define BIT_SHIFT_RCLK_MON_8814B 5 #define BIT_MASK_RCLK_MON_8814B 0x7ff -#define BIT_RCLK_MON_8814B(x) (((x) & BIT_MASK_RCLK_MON_8814B) << BIT_SHIFT_RCLK_MON_8814B) -#define BIT_GET_RCLK_MON_8814B(x) (((x) >> BIT_SHIFT_RCLK_MON_8814B) & BIT_MASK_RCLK_MON_8814B) - +#define BIT_RCLK_MON_8814B(x) \ + (((x) & BIT_MASK_RCLK_MON_8814B) << BIT_SHIFT_RCLK_MON_8814B) +#define BITS_RCLK_MON_8814B \ + (BIT_MASK_RCLK_MON_8814B << BIT_SHIFT_RCLK_MON_8814B) +#define BIT_CLEAR_RCLK_MON_8814B(x) ((x) & (~BITS_RCLK_MON_8814B)) +#define BIT_GET_RCLK_MON_8814B(x) \ + (((x) >> BIT_SHIFT_RCLK_MON_8814B) & BIT_MASK_RCLK_MON_8814B) +#define BIT_SET_RCLK_MON_8814B(x, v) \ + (BIT_CLEAR_RCLK_MON_8814B(x) | BIT_RCLK_MON_8814B(v)) #define BIT_CAL_EN_8814B BIT(4) #define BIT_SHIFT_DPSTU_8814B 2 #define BIT_MASK_DPSTU_8814B 0x3 -#define BIT_DPSTU_8814B(x) (((x) & BIT_MASK_DPSTU_8814B) << BIT_SHIFT_DPSTU_8814B) -#define BIT_GET_DPSTU_8814B(x) (((x) >> BIT_SHIFT_DPSTU_8814B) & BIT_MASK_DPSTU_8814B) - +#define BIT_DPSTU_8814B(x) \ + (((x) & BIT_MASK_DPSTU_8814B) << BIT_SHIFT_DPSTU_8814B) +#define BITS_DPSTU_8814B (BIT_MASK_DPSTU_8814B << BIT_SHIFT_DPSTU_8814B) +#define BIT_CLEAR_DPSTU_8814B(x) ((x) & (~BITS_DPSTU_8814B)) +#define BIT_GET_DPSTU_8814B(x) \ + (((x) >> BIT_SHIFT_DPSTU_8814B) & BIT_MASK_DPSTU_8814B) +#define BIT_SET_DPSTU_8814B(x, v) \ + (BIT_CLEAR_DPSTU_8814B(x) | BIT_DPSTU_8814B(v)) #define BIT_SUS_16X_8814B BIT(1) /* 2 REG_GPIO_MUXCFG_8814B */ +#define BIT_EN_DATACPU_GPIO2_8814B BIT(24) +#define BIT_EN_DATACPU_GPIO_8814B BIT(23) +#define BIT_EN_DATACPU_UART_8814B BIT(22) +#define BIT_DATACPU_FSPI_EN_8814B BIT(21) +#define BIT_EN_GPIO8_UART_OUT_8814B BIT(20) #define BIT_FSPI_EN_8814B BIT(19) #define BIT_WL_RTS_EXT_32K_SEL_8814B BIT(18) #define BIT_WLGP_SPI_EN_8814B BIT(16) @@ -649,9 +695,14 @@ #define BIT_SHIFT_BTMODE_8814B 6 #define BIT_MASK_BTMODE_8814B 0x3 -#define BIT_BTMODE_8814B(x) (((x) & BIT_MASK_BTMODE_8814B) << BIT_SHIFT_BTMODE_8814B) -#define BIT_GET_BTMODE_8814B(x) (((x) >> BIT_SHIFT_BTMODE_8814B) & BIT_MASK_BTMODE_8814B) - +#define BIT_BTMODE_8814B(x) \ + (((x) & BIT_MASK_BTMODE_8814B) << BIT_SHIFT_BTMODE_8814B) +#define BITS_BTMODE_8814B (BIT_MASK_BTMODE_8814B << BIT_SHIFT_BTMODE_8814B) +#define BIT_CLEAR_BTMODE_8814B(x) ((x) & (~BITS_BTMODE_8814B)) +#define BIT_GET_BTMODE_8814B(x) \ + (((x) >> BIT_SHIFT_BTMODE_8814B) & BIT_MASK_BTMODE_8814B) +#define BIT_SET_BTMODE_8814B(x, v) \ + (BIT_CLEAR_BTMODE_8814B(x) | BIT_BTMODE_8814B(v)) #define BIT_ENBT_8814B BIT(5) #define BIT_EROM_EN_8814B BIT(4) @@ -660,48 +711,89 @@ #define BIT_SHIFT_GPIOSEL_8814B 0 #define BIT_MASK_GPIOSEL_8814B 0x3 -#define BIT_GPIOSEL_8814B(x) (((x) & BIT_MASK_GPIOSEL_8814B) << BIT_SHIFT_GPIOSEL_8814B) -#define BIT_GET_GPIOSEL_8814B(x) (((x) >> BIT_SHIFT_GPIOSEL_8814B) & BIT_MASK_GPIOSEL_8814B) - - +#define BIT_GPIOSEL_8814B(x) \ + (((x) & BIT_MASK_GPIOSEL_8814B) << BIT_SHIFT_GPIOSEL_8814B) +#define BITS_GPIOSEL_8814B (BIT_MASK_GPIOSEL_8814B << BIT_SHIFT_GPIOSEL_8814B) +#define BIT_CLEAR_GPIOSEL_8814B(x) ((x) & (~BITS_GPIOSEL_8814B)) +#define BIT_GET_GPIOSEL_8814B(x) \ + (((x) >> BIT_SHIFT_GPIOSEL_8814B) & BIT_MASK_GPIOSEL_8814B) +#define BIT_SET_GPIOSEL_8814B(x, v) \ + (BIT_CLEAR_GPIOSEL_8814B(x) | BIT_GPIOSEL_8814B(v)) /* 2 REG_GPIO_PIN_CTRL_8814B */ #define BIT_SHIFT_GPIO_MOD_7_TO_0_8814B 24 #define BIT_MASK_GPIO_MOD_7_TO_0_8814B 0xff -#define BIT_GPIO_MOD_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8814B) << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) -#define BIT_GET_GPIO_MOD_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) & BIT_MASK_GPIO_MOD_7_TO_0_8814B) - - +#define BIT_GPIO_MOD_7_TO_0_8814B(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8814B) \ + << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) +#define BITS_GPIO_MOD_7_TO_0_8814B \ + (BIT_MASK_GPIO_MOD_7_TO_0_8814B << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) +#define BIT_CLEAR_GPIO_MOD_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8814B)) +#define BIT_GET_GPIO_MOD_7_TO_0_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) & \ + BIT_MASK_GPIO_MOD_7_TO_0_8814B) +#define BIT_SET_GPIO_MOD_7_TO_0_8814B(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0_8814B(x) | BIT_GPIO_MOD_7_TO_0_8814B(v)) #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B 16 #define BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B 0xff -#define BIT_GPIO_IO_SEL_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) -#define BIT_GET_GPIO_IO_SEL_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B) - - +#define BIT_GPIO_IO_SEL_7_TO_0_8814B(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B) \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) +#define BITS_GPIO_IO_SEL_7_TO_0_8814B \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8814B(x) \ + ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8814B)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) & \ + BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B) +#define BIT_SET_GPIO_IO_SEL_7_TO_0_8814B(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8814B(x) | \ + BIT_GPIO_IO_SEL_7_TO_0_8814B(v)) #define BIT_SHIFT_GPIO_OUT_7_TO_0_8814B 8 #define BIT_MASK_GPIO_OUT_7_TO_0_8814B 0xff -#define BIT_GPIO_OUT_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8814B) << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) -#define BIT_GET_GPIO_OUT_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) & BIT_MASK_GPIO_OUT_7_TO_0_8814B) - - +#define BIT_GPIO_OUT_7_TO_0_8814B(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8814B) \ + << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) +#define BITS_GPIO_OUT_7_TO_0_8814B \ + (BIT_MASK_GPIO_OUT_7_TO_0_8814B << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) +#define BIT_CLEAR_GPIO_OUT_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8814B)) +#define BIT_GET_GPIO_OUT_7_TO_0_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) & \ + BIT_MASK_GPIO_OUT_7_TO_0_8814B) +#define BIT_SET_GPIO_OUT_7_TO_0_8814B(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0_8814B(x) | BIT_GPIO_OUT_7_TO_0_8814B(v)) #define BIT_SHIFT_GPIO_IN_7_TO_0_8814B 0 #define BIT_MASK_GPIO_IN_7_TO_0_8814B 0xff -#define BIT_GPIO_IN_7_TO_0_8814B(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8814B) << BIT_SHIFT_GPIO_IN_7_TO_0_8814B) -#define BIT_GET_GPIO_IN_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8814B) & BIT_MASK_GPIO_IN_7_TO_0_8814B) - - +#define BIT_GPIO_IN_7_TO_0_8814B(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0_8814B) \ + << BIT_SHIFT_GPIO_IN_7_TO_0_8814B) +#define BITS_GPIO_IN_7_TO_0_8814B \ + (BIT_MASK_GPIO_IN_7_TO_0_8814B << BIT_SHIFT_GPIO_IN_7_TO_0_8814B) +#define BIT_CLEAR_GPIO_IN_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8814B)) +#define BIT_GET_GPIO_IN_7_TO_0_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8814B) & \ + BIT_MASK_GPIO_IN_7_TO_0_8814B) +#define BIT_SET_GPIO_IN_7_TO_0_8814B(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0_8814B(x) | BIT_GPIO_IN_7_TO_0_8814B(v)) /* 2 REG_GPIO_INTM_8814B */ #define BIT_SHIFT_MUXDBG_SEL_8814B 30 #define BIT_MASK_MUXDBG_SEL_8814B 0x3 -#define BIT_MUXDBG_SEL_8814B(x) (((x) & BIT_MASK_MUXDBG_SEL_8814B) << BIT_SHIFT_MUXDBG_SEL_8814B) -#define BIT_GET_MUXDBG_SEL_8814B(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8814B) & BIT_MASK_MUXDBG_SEL_8814B) - +#define BIT_MUXDBG_SEL_8814B(x) \ + (((x) & BIT_MASK_MUXDBG_SEL_8814B) << BIT_SHIFT_MUXDBG_SEL_8814B) +#define BITS_MUXDBG_SEL_8814B \ + (BIT_MASK_MUXDBG_SEL_8814B << BIT_SHIFT_MUXDBG_SEL_8814B) +#define BIT_CLEAR_MUXDBG_SEL_8814B(x) ((x) & (~BITS_MUXDBG_SEL_8814B)) +#define BIT_GET_MUXDBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL_8814B) & BIT_MASK_MUXDBG_SEL_8814B) +#define BIT_SET_MUXDBG_SEL_8814B(x, v) \ + (BIT_CLEAR_MUXDBG_SEL_8814B(x) | BIT_MUXDBG_SEL_8814B(v)) #define BIT_EXTWOL_SEL_8814B BIT(17) #define BIT_EXTWOL_EN_8814B BIT(16) @@ -732,16 +824,20 @@ #define BIT_DPDT_WLBT_SEL_8814B BIT(24) #define BIT_DPDT_SEL_EN_8814B BIT(23) #define BIT_GPIO13_14_WL_CTRL_EN_8814B BIT(22) -#define BIT_GPIO13_14_WL_CTRL_EN_8814B BIT(22) #define BIT_LED2DIS_8814B BIT(21) #define BIT_LED2PL_8814B BIT(20) #define BIT_LED2SV_8814B BIT(19) #define BIT_SHIFT_LED2CM_8814B 16 #define BIT_MASK_LED2CM_8814B 0x7 -#define BIT_LED2CM_8814B(x) (((x) & BIT_MASK_LED2CM_8814B) << BIT_SHIFT_LED2CM_8814B) -#define BIT_GET_LED2CM_8814B(x) (((x) >> BIT_SHIFT_LED2CM_8814B) & BIT_MASK_LED2CM_8814B) - +#define BIT_LED2CM_8814B(x) \ + (((x) & BIT_MASK_LED2CM_8814B) << BIT_SHIFT_LED2CM_8814B) +#define BITS_LED2CM_8814B (BIT_MASK_LED2CM_8814B << BIT_SHIFT_LED2CM_8814B) +#define BIT_CLEAR_LED2CM_8814B(x) ((x) & (~BITS_LED2CM_8814B)) +#define BIT_GET_LED2CM_8814B(x) \ + (((x) >> BIT_SHIFT_LED2CM_8814B) & BIT_MASK_LED2CM_8814B) +#define BIT_SET_LED2CM_8814B(x, v) \ + (BIT_CLEAR_LED2CM_8814B(x) | BIT_LED2CM_8814B(v)) #define BIT_LED1DIS_8814B BIT(15) #define BIT_LED1PL_8814B BIT(12) @@ -749,27 +845,45 @@ #define BIT_SHIFT_LED1CM_8814B 8 #define BIT_MASK_LED1CM_8814B 0x7 -#define BIT_LED1CM_8814B(x) (((x) & BIT_MASK_LED1CM_8814B) << BIT_SHIFT_LED1CM_8814B) -#define BIT_GET_LED1CM_8814B(x) (((x) >> BIT_SHIFT_LED1CM_8814B) & BIT_MASK_LED1CM_8814B) - +#define BIT_LED1CM_8814B(x) \ + (((x) & BIT_MASK_LED1CM_8814B) << BIT_SHIFT_LED1CM_8814B) +#define BITS_LED1CM_8814B (BIT_MASK_LED1CM_8814B << BIT_SHIFT_LED1CM_8814B) +#define BIT_CLEAR_LED1CM_8814B(x) ((x) & (~BITS_LED1CM_8814B)) +#define BIT_GET_LED1CM_8814B(x) \ + (((x) >> BIT_SHIFT_LED1CM_8814B) & BIT_MASK_LED1CM_8814B) +#define BIT_SET_LED1CM_8814B(x, v) \ + (BIT_CLEAR_LED1CM_8814B(x) | BIT_LED1CM_8814B(v)) #define BIT_LED0DIS_8814B BIT(7) #define BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B 5 #define BIT_MASK_AFE_LDO_SWR_CHECK_8814B 0x3 -#define BIT_AFE_LDO_SWR_CHECK_8814B(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8814B) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) -#define BIT_GET_AFE_LDO_SWR_CHECK_8814B(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) & BIT_MASK_AFE_LDO_SWR_CHECK_8814B) - +#define BIT_AFE_LDO_SWR_CHECK_8814B(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8814B) \ + << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) +#define BITS_AFE_LDO_SWR_CHECK_8814B \ + (BIT_MASK_AFE_LDO_SWR_CHECK_8814B << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8814B(x) \ + ((x) & (~BITS_AFE_LDO_SWR_CHECK_8814B)) +#define BIT_GET_AFE_LDO_SWR_CHECK_8814B(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) & \ + BIT_MASK_AFE_LDO_SWR_CHECK_8814B) +#define BIT_SET_AFE_LDO_SWR_CHECK_8814B(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK_8814B(x) | BIT_AFE_LDO_SWR_CHECK_8814B(v)) #define BIT_LED0PL_8814B BIT(4) #define BIT_LED0SV_8814B BIT(3) #define BIT_SHIFT_LED0CM_8814B 0 #define BIT_MASK_LED0CM_8814B 0x7 -#define BIT_LED0CM_8814B(x) (((x) & BIT_MASK_LED0CM_8814B) << BIT_SHIFT_LED0CM_8814B) -#define BIT_GET_LED0CM_8814B(x) (((x) >> BIT_SHIFT_LED0CM_8814B) & BIT_MASK_LED0CM_8814B) - - +#define BIT_LED0CM_8814B(x) \ + (((x) & BIT_MASK_LED0CM_8814B) << BIT_SHIFT_LED0CM_8814B) +#define BITS_LED0CM_8814B (BIT_MASK_LED0CM_8814B << BIT_SHIFT_LED0CM_8814B) +#define BIT_CLEAR_LED0CM_8814B(x) ((x) & (~BITS_LED0CM_8814B)) +#define BIT_GET_LED0CM_8814B(x) \ + (((x) >> BIT_SHIFT_LED0CM_8814B) & BIT_MASK_LED0CM_8814B) +#define BIT_SET_LED0CM_8814B(x, v) \ + (BIT_CLEAR_LED0CM_8814B(x) | BIT_LED0CM_8814B(v)) /* 2 REG_FSIMR_8814B */ #define BIT_FS_PDNINT_EN_8814B BIT(31) @@ -829,6 +943,7 @@ #define BIT_FS_HCI_RES_INT_8814B BIT(10) #define BIT_FS_HCI_RESET_INT_8814B BIT(9) #define BIT_USB_SCSI_CMD_INT_8814B BIT(8) +#define BIT_FS_BTON_STS_UPDATE_INT_8814B BIT(7) #define BIT_ACT2RECOVERY_8814B BIT(6) #define BIT_GEN1GEN2_SWITCH_8814B BIT(5) #define BIT_HCI_TXDMA_REQ_HISR_8814B BIT(4) @@ -851,7 +966,7 @@ #define BIT_GPIO5_INT_EN_8814B BIT(21) #define BIT_GPIO4_INT_EN_8814B BIT(20) #define BIT_GPIO3_INT_EN_8814B BIT(19) -#define BIT_GPIO2_INT_EN_V1_8814B BIT(16) +#define BIT_GPIO2_INT_EN_V1_8814B BIT(18) #define BIT_GPIO1_INT_EN_8814B BIT(17) #define BIT_GPIO0_INT_EN_8814B BIT(16) #define BIT_PDNINT_EN_8814B BIT(7) @@ -873,7 +988,7 @@ #define BIT_GPIO5_INT_8814B BIT(21) #define BIT_GPIO4_INT_8814B BIT(20) #define BIT_GPIO3_INT_8814B BIT(19) -#define BIT_GPIO2_INT_V1_8814B BIT(16) +#define BIT_GPIO2_INT_V1_8814B BIT(18) #define BIT_GPIO1_INT_8814B BIT(17) #define BIT_GPIO0_INT_8814B BIT(16) #define BIT_PDNINT_8814B BIT(7) @@ -885,33 +1000,67 @@ #define BIT_SHIFT_GPIO_MOD_15_TO_8_8814B 24 #define BIT_MASK_GPIO_MOD_15_TO_8_8814B 0xff -#define BIT_GPIO_MOD_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8814B) << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) -#define BIT_GET_GPIO_MOD_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) & BIT_MASK_GPIO_MOD_15_TO_8_8814B) - - +#define BIT_GPIO_MOD_15_TO_8_8814B(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8814B) \ + << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) +#define BITS_GPIO_MOD_15_TO_8_8814B \ + (BIT_MASK_GPIO_MOD_15_TO_8_8814B << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) +#define BIT_CLEAR_GPIO_MOD_15_TO_8_8814B(x) \ + ((x) & (~BITS_GPIO_MOD_15_TO_8_8814B)) +#define BIT_GET_GPIO_MOD_15_TO_8_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) & \ + BIT_MASK_GPIO_MOD_15_TO_8_8814B) +#define BIT_SET_GPIO_MOD_15_TO_8_8814B(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8_8814B(x) | BIT_GPIO_MOD_15_TO_8_8814B(v)) #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B 16 #define BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B 0xff -#define BIT_GPIO_IO_SEL_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) -#define BIT_GET_GPIO_IO_SEL_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B) - - +#define BIT_GPIO_IO_SEL_15_TO_8_8814B(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B) \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) +#define BITS_GPIO_IO_SEL_15_TO_8_8814B \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8814B(x) \ + ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8814B)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) & \ + BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B) +#define BIT_SET_GPIO_IO_SEL_15_TO_8_8814B(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8814B(x) | \ + BIT_GPIO_IO_SEL_15_TO_8_8814B(v)) #define BIT_SHIFT_GPIO_OUT_15_TO_8_8814B 8 #define BIT_MASK_GPIO_OUT_15_TO_8_8814B 0xff -#define BIT_GPIO_OUT_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8814B) << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) -#define BIT_GET_GPIO_OUT_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) & BIT_MASK_GPIO_OUT_15_TO_8_8814B) - - +#define BIT_GPIO_OUT_15_TO_8_8814B(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8814B) \ + << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) +#define BITS_GPIO_OUT_15_TO_8_8814B \ + (BIT_MASK_GPIO_OUT_15_TO_8_8814B << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) +#define BIT_CLEAR_GPIO_OUT_15_TO_8_8814B(x) \ + ((x) & (~BITS_GPIO_OUT_15_TO_8_8814B)) +#define BIT_GET_GPIO_OUT_15_TO_8_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) & \ + BIT_MASK_GPIO_OUT_15_TO_8_8814B) +#define BIT_SET_GPIO_OUT_15_TO_8_8814B(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8_8814B(x) | BIT_GPIO_OUT_15_TO_8_8814B(v)) #define BIT_SHIFT_GPIO_IN_15_TO_8_8814B 0 #define BIT_MASK_GPIO_IN_15_TO_8_8814B 0xff -#define BIT_GPIO_IN_15_TO_8_8814B(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8814B) << BIT_SHIFT_GPIO_IN_15_TO_8_8814B) -#define BIT_GET_GPIO_IN_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8814B) & BIT_MASK_GPIO_IN_15_TO_8_8814B) - - +#define BIT_GPIO_IN_15_TO_8_8814B(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8_8814B) \ + << BIT_SHIFT_GPIO_IN_15_TO_8_8814B) +#define BITS_GPIO_IN_15_TO_8_8814B \ + (BIT_MASK_GPIO_IN_15_TO_8_8814B << BIT_SHIFT_GPIO_IN_15_TO_8_8814B) +#define BIT_CLEAR_GPIO_IN_15_TO_8_8814B(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8814B)) +#define BIT_GET_GPIO_IN_15_TO_8_8814B(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8814B) & \ + BIT_MASK_GPIO_IN_15_TO_8_8814B) +#define BIT_SET_GPIO_IN_15_TO_8_8814B(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8_8814B(x) | BIT_GPIO_IN_15_TO_8_8814B(v)) /* 2 REG_PAD_CTRL1_8814B */ +#define BIT_DATA_CPU_JTAG_8814B BIT(30) #define BIT_PAPE_WLBT_SEL_8814B BIT(29) #define BIT_LNAON_WLBT_SEL_8814B BIT(28) #define BIT_BTGP_GPG3_FEN_8814B BIT(26) @@ -926,24 +1075,25 @@ #define BIT_SHIFT_BTGP_GPIO_SL_8814B 16 #define BIT_MASK_BTGP_GPIO_SL_8814B 0x3 -#define BIT_BTGP_GPIO_SL_8814B(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8814B) << BIT_SHIFT_BTGP_GPIO_SL_8814B) -#define BIT_GET_BTGP_GPIO_SL_8814B(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8814B) & BIT_MASK_BTGP_GPIO_SL_8814B) - - +#define BIT_BTGP_GPIO_SL_8814B(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL_8814B) << BIT_SHIFT_BTGP_GPIO_SL_8814B) +#define BITS_BTGP_GPIO_SL_8814B \ + (BIT_MASK_BTGP_GPIO_SL_8814B << BIT_SHIFT_BTGP_GPIO_SL_8814B) +#define BIT_CLEAR_BTGP_GPIO_SL_8814B(x) ((x) & (~BITS_BTGP_GPIO_SL_8814B)) +#define BIT_GET_BTGP_GPIO_SL_8814B(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8814B) & BIT_MASK_BTGP_GPIO_SL_8814B) +#define BIT_SET_BTGP_GPIO_SL_8814B(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL_8814B(x) | BIT_BTGP_GPIO_SL_8814B(v)) + +#define BIT_WL_JTAG_8814B BIT(15) #define BIT_PAD_SDIO_SR_8814B BIT(14) #define BIT_GPIO14_OUTPUT_PL_8814B BIT(13) #define BIT_HOST_WAKE_PAD_PULL_EN_8814B BIT(12) #define BIT_HOST_WAKE_PAD_SL_8814B BIT(11) -#define BIT_PAD_LNAON_SR_8814B BIT(10) -#define BIT_PAD_LNAON_E2_8814B BIT(9) #define BIT_SW_LNAON_G_SEL_DATA_8814B BIT(8) #define BIT_SW_LNAON_A_SEL_DATA_8814B BIT(7) -#define BIT_PAD_PAPE_SR_8814B BIT(6) -#define BIT_PAD_PAPE_E2_8814B BIT(5) #define BIT_SW_PAPE_G_SEL_DATA_8814B BIT(4) #define BIT_SW_PAPE_A_SEL_DATA_8814B BIT(3) -#define BIT_PAD_DPDT_SR_8814B BIT(2) -#define BIT_PAD_DPDT_PAD_E2_8814B BIT(1) #define BIT_SW_DPDT_SEL_DATA_8814B BIT(0) /* 2 REG_WL_BT_PWR_CTRL_8814B */ @@ -953,9 +1103,12 @@ #define BIT_FEN_BTGPS_8814B BIT(28) #define BIT_BTCPU_BOOTSEL_8814B BIT(27) #define BIT_SPI_SPEEDUP_8814B BIT(26) +#define BIT_BT_SUS_8814B BIT(25) #define BIT_DEVWAKE_PAD_TYPE_SEL_8814B BIT(24) #define BIT_CLKREQ_PAD_TYPE_SEL_8814B BIT(23) #define BIT_ISO_BTPON2PP_8814B BIT(22) +#define BIT_BTCOEX_CMD_8814B BIT(21) +#define BIT_BT_UART_INTF_8814B BIT(20) #define BIT_BT_HWROF_EN_8814B BIT(19) #define BIT_BT_FUNC_EN_8814B BIT(18) #define BIT_BT_HWPDN_SL_8814B BIT(17) @@ -968,6 +1121,8 @@ #define BIT_BT_AFE_LDO_EN_8814B BIT(10) #define BIT_BT_AFE_PLL_EN_8814B BIT(9) #define BIT_BT_DIG_CLK_EN_8814B BIT(8) +#define BIT_UART_BRIDGE_8814B BIT(7) +#define BIT_OSC32K_CTRL_SEL_8814B BIT(6) #define BIT_WL_DRV_EXIST_IDX_8814B BIT(5) #define BIT_DOP_EHPAD_8814B BIT(4) #define BIT_WL_HWROF_EN_8814B BIT(3) @@ -976,13 +1131,22 @@ #define BIT_WL_HWPDN_EN_8814B BIT(0) /* 2 REG_SDM_DEBUG_8814B */ +#define BIT_BT_WAKE_DEV_EN_V1_8814B BIT(19) +#define BIT_BT_WAKE_HST_EN_V1_8814B BIT(18) +#define BIT_BT_WAKE_HST_PL_V1_8814B BIT(17) +#define BIT_BT_CLKREQ_EN_V1_8814B BIT(16) #define BIT_SHIFT_WLCLK_PHASE_8814B 0 #define BIT_MASK_WLCLK_PHASE_8814B 0x1f -#define BIT_WLCLK_PHASE_8814B(x) (((x) & BIT_MASK_WLCLK_PHASE_8814B) << BIT_SHIFT_WLCLK_PHASE_8814B) -#define BIT_GET_WLCLK_PHASE_8814B(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8814B) & BIT_MASK_WLCLK_PHASE_8814B) - - +#define BIT_WLCLK_PHASE_8814B(x) \ + (((x) & BIT_MASK_WLCLK_PHASE_8814B) << BIT_SHIFT_WLCLK_PHASE_8814B) +#define BITS_WLCLK_PHASE_8814B \ + (BIT_MASK_WLCLK_PHASE_8814B << BIT_SHIFT_WLCLK_PHASE_8814B) +#define BIT_CLEAR_WLCLK_PHASE_8814B(x) ((x) & (~BITS_WLCLK_PHASE_8814B)) +#define BIT_GET_WLCLK_PHASE_8814B(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE_8814B) & BIT_MASK_WLCLK_PHASE_8814B) +#define BIT_SET_WLCLK_PHASE_8814B(x, v) \ + (BIT_CLEAR_WLCLK_PHASE_8814B(x) | BIT_WLCLK_PHASE_8814B(v)) /* 2 REG_SYS_SDIO_CTRL_8814B */ #define BIT_DBG_GNT_WL_BT_8814B BIT(27) @@ -996,6 +1160,36 @@ #define BIT_PCIE_WAIT_TIMEOUT_EVENT_8814B BIT(10) #define BIT_PCIE_WAIT_TIME_8814B BIT(9) #define BIT_MPCIE_REFCLK_XTAL_SEL_8814B BIT(8) +#define BIT_BT_CLKREQ_EN_8814B BIT(6) + +#define BIT_SHIFT_USB_CKREF_CML_R_8814B 4 +#define BIT_MASK_USB_CKREF_CML_R_8814B 0x3 +#define BIT_USB_CKREF_CML_R_8814B(x) \ + (((x) & BIT_MASK_USB_CKREF_CML_R_8814B) \ + << BIT_SHIFT_USB_CKREF_CML_R_8814B) +#define BITS_USB_CKREF_CML_R_8814B \ + (BIT_MASK_USB_CKREF_CML_R_8814B << BIT_SHIFT_USB_CKREF_CML_R_8814B) +#define BIT_CLEAR_USB_CKREF_CML_R_8814B(x) ((x) & (~BITS_USB_CKREF_CML_R_8814B)) +#define BIT_GET_USB_CKREF_CML_R_8814B(x) \ + (((x) >> BIT_SHIFT_USB_CKREF_CML_R_8814B) & \ + BIT_MASK_USB_CKREF_CML_R_8814B) +#define BIT_SET_USB_CKREF_CML_R_8814B(x, v) \ + (BIT_CLEAR_USB_CKREF_CML_R_8814B(x) | BIT_USB_CKREF_CML_R_8814B(v)) + +#define BIT_SHIFT_USB_CKREF_D2S_I_8814B 2 +#define BIT_MASK_USB_CKREF_D2S_I_8814B 0x3 +#define BIT_USB_CKREF_D2S_I_8814B(x) \ + (((x) & BIT_MASK_USB_CKREF_D2S_I_8814B) \ + << BIT_SHIFT_USB_CKREF_D2S_I_8814B) +#define BITS_USB_CKREF_D2S_I_8814B \ + (BIT_MASK_USB_CKREF_D2S_I_8814B << BIT_SHIFT_USB_CKREF_D2S_I_8814B) +#define BIT_CLEAR_USB_CKREF_D2S_I_8814B(x) ((x) & (~BITS_USB_CKREF_D2S_I_8814B)) +#define BIT_GET_USB_CKREF_D2S_I_8814B(x) \ + (((x) >> BIT_SHIFT_USB_CKREF_D2S_I_8814B) & \ + BIT_MASK_USB_CKREF_D2S_I_8814B) +#define BIT_SET_USB_CKREF_D2S_I_8814B(x, v) \ + (BIT_CLEAR_USB_CKREF_D2S_I_8814B(x) | BIT_USB_CKREF_D2S_I_8814B(v)) + #define BIT_RES_USB_MASS_STORAGE_DESC_8814B BIT(1) #define BIT_USB_WAIT_TIME_8814B BIT(0) @@ -1003,10 +1197,17 @@ #define BIT_SHIFT_TSFT_SEL_8814B 29 #define BIT_MASK_TSFT_SEL_8814B 0x7 -#define BIT_TSFT_SEL_8814B(x) (((x) & BIT_MASK_TSFT_SEL_8814B) << BIT_SHIFT_TSFT_SEL_8814B) -#define BIT_GET_TSFT_SEL_8814B(x) (((x) >> BIT_SHIFT_TSFT_SEL_8814B) & BIT_MASK_TSFT_SEL_8814B) - - +#define BIT_TSFT_SEL_8814B(x) \ + (((x) & BIT_MASK_TSFT_SEL_8814B) << BIT_SHIFT_TSFT_SEL_8814B) +#define BITS_TSFT_SEL_8814B \ + (BIT_MASK_TSFT_SEL_8814B << BIT_SHIFT_TSFT_SEL_8814B) +#define BIT_CLEAR_TSFT_SEL_8814B(x) ((x) & (~BITS_TSFT_SEL_8814B)) +#define BIT_GET_TSFT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_8814B) & BIT_MASK_TSFT_SEL_8814B) +#define BIT_SET_TSFT_SEL_8814B(x, v) \ + (BIT_CLEAR_TSFT_SEL_8814B(x) | BIT_TSFT_SEL_8814B(v)) + +#define BIT_TSFT_BAND_SEL_8814B BIT(28) #define BIT_USB_HOST_PWR_OFF_EN_8814B BIT(12) #define BIT_SYM_LPS_BLOCK_EN_8814B BIT(11) #define BIT_USB_LPM_ACT_EN_8814B BIT(10) @@ -1015,9 +1216,15 @@ #define BIT_SHIFT_SDIO_PAD_E_8814B 5 #define BIT_MASK_SDIO_PAD_E_8814B 0x7 -#define BIT_SDIO_PAD_E_8814B(x) (((x) & BIT_MASK_SDIO_PAD_E_8814B) << BIT_SHIFT_SDIO_PAD_E_8814B) -#define BIT_GET_SDIO_PAD_E_8814B(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8814B) & BIT_MASK_SDIO_PAD_E_8814B) - +#define BIT_SDIO_PAD_E_8814B(x) \ + (((x) & BIT_MASK_SDIO_PAD_E_8814B) << BIT_SHIFT_SDIO_PAD_E_8814B) +#define BITS_SDIO_PAD_E_8814B \ + (BIT_MASK_SDIO_PAD_E_8814B << BIT_SHIFT_SDIO_PAD_E_8814B) +#define BIT_CLEAR_SDIO_PAD_E_8814B(x) ((x) & (~BITS_SDIO_PAD_E_8814B)) +#define BIT_GET_SDIO_PAD_E_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E_8814B) & BIT_MASK_SDIO_PAD_E_8814B) +#define BIT_SET_SDIO_PAD_E_8814B(x, v) \ + (BIT_CLEAR_SDIO_PAD_E_8814B(x) | BIT_SDIO_PAD_E_8814B(v)) #define BIT_USB_LPPLL_EN_8814B BIT(4) #define BIT_ROP_SW15_8814B BIT(2) @@ -1026,71 +1233,63 @@ /* 2 REG_AFE_CTRL4_8814B */ +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + /* 2 REG_LDO_SWR_CTRL_8814B */ #define BIT_ZCD_HW_AUTO_EN_8814B BIT(27) #define BIT_ZCD_REGSEL_8814B BIT(26) #define BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B 21 #define BIT_MASK_AUTO_ZCD_IN_CODE_8814B 0x1f -#define BIT_AUTO_ZCD_IN_CODE_8814B(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8814B) << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) -#define BIT_GET_AUTO_ZCD_IN_CODE_8814B(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) & BIT_MASK_AUTO_ZCD_IN_CODE_8814B) - - +#define BIT_AUTO_ZCD_IN_CODE_8814B(x) \ + (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8814B) \ + << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) +#define BITS_AUTO_ZCD_IN_CODE_8814B \ + (BIT_MASK_AUTO_ZCD_IN_CODE_8814B << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) +#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8814B(x) \ + ((x) & (~BITS_AUTO_ZCD_IN_CODE_8814B)) +#define BIT_GET_AUTO_ZCD_IN_CODE_8814B(x) \ + (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) & \ + BIT_MASK_AUTO_ZCD_IN_CODE_8814B) +#define BIT_SET_AUTO_ZCD_IN_CODE_8814B(x, v) \ + (BIT_CLEAR_AUTO_ZCD_IN_CODE_8814B(x) | BIT_AUTO_ZCD_IN_CODE_8814B(v)) #define BIT_SHIFT_ZCD_CODE_IN_L_8814B 16 #define BIT_MASK_ZCD_CODE_IN_L_8814B 0x1f -#define BIT_ZCD_CODE_IN_L_8814B(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8814B) << BIT_SHIFT_ZCD_CODE_IN_L_8814B) -#define BIT_GET_ZCD_CODE_IN_L_8814B(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8814B) & BIT_MASK_ZCD_CODE_IN_L_8814B) - - - -#define BIT_SHIFT_LDO_HV5_DUMMY_8814B 14 -#define BIT_MASK_LDO_HV5_DUMMY_8814B 0x3 -#define BIT_LDO_HV5_DUMMY_8814B(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8814B) << BIT_SHIFT_LDO_HV5_DUMMY_8814B) -#define BIT_GET_LDO_HV5_DUMMY_8814B(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8814B) & BIT_MASK_LDO_HV5_DUMMY_8814B) - - - -#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8814B 12 -#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8814B 0x3 -#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8814B(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8814B) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8814B) -#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8814B(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8814B) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8814B) - +#define BIT_ZCD_CODE_IN_L_8814B(x) \ + (((x) & BIT_MASK_ZCD_CODE_IN_L_8814B) << BIT_SHIFT_ZCD_CODE_IN_L_8814B) +#define BITS_ZCD_CODE_IN_L_8814B \ + (BIT_MASK_ZCD_CODE_IN_L_8814B << BIT_SHIFT_ZCD_CODE_IN_L_8814B) +#define BIT_CLEAR_ZCD_CODE_IN_L_8814B(x) ((x) & (~BITS_ZCD_CODE_IN_L_8814B)) +#define BIT_GET_ZCD_CODE_IN_L_8814B(x) \ + (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8814B) & BIT_MASK_ZCD_CODE_IN_L_8814B) +#define BIT_SET_ZCD_CODE_IN_L_8814B(x, v) \ + (BIT_CLEAR_ZCD_CODE_IN_L_8814B(x) | BIT_ZCD_CODE_IN_L_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8814B 10 -#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8814B 0x3 -#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8814B(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8814B) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8814B) -#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8814B(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8814B) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8814B) - - - -#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8814B 8 -#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8814B 0x3 -#define BIT_REG_LOAD33_BIT0_TO_BIT1_8814B(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8814B) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8814B) -#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8814B(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8814B) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8814B) - +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_BYPASS_L_8814B BIT(7) -#define BIT_REG_LDOF_L_8814B BIT(6) -#define BIT_REG_OCPS_L_8814B BIT(5) -#define BIT_ARENB_L_8814B BIT(3) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CFC_L_8814B 1 -#define BIT_MASK_CFC_L_8814B 0x3 -#define BIT_CFC_L_8814B(x) (((x) & BIT_MASK_CFC_L_8814B) << BIT_SHIFT_CFC_L_8814B) -#define BIT_GET_CFC_L_8814B(x) (((x) >> BIT_SHIFT_CFC_L_8814B) & BIT_MASK_CFC_L_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_REG_TYPE_L_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_MCUFW_CTRL_8814B */ #define BIT_SHIFT_RPWM_8814B 24 #define BIT_MASK_RPWM_8814B 0xff #define BIT_RPWM_8814B(x) (((x) & BIT_MASK_RPWM_8814B) << BIT_SHIFT_RPWM_8814B) -#define BIT_GET_RPWM_8814B(x) (((x) >> BIT_SHIFT_RPWM_8814B) & BIT_MASK_RPWM_8814B) - +#define BITS_RPWM_8814B (BIT_MASK_RPWM_8814B << BIT_SHIFT_RPWM_8814B) +#define BIT_CLEAR_RPWM_8814B(x) ((x) & (~BITS_RPWM_8814B)) +#define BIT_GET_RPWM_8814B(x) \ + (((x) >> BIT_SHIFT_RPWM_8814B) & BIT_MASK_RPWM_8814B) +#define BIT_SET_RPWM_8814B(x, v) (BIT_CLEAR_RPWM_8814B(x) | BIT_RPWM_8814B(v)) #define BIT_ANA_PORT_EN_8814B BIT(22) #define BIT_MAC_PORT_EN_8814B BIT(21) @@ -1099,18 +1298,29 @@ #define BIT_SHIFT_ROM_PGE_8814B 16 #define BIT_MASK_ROM_PGE_8814B 0x7 -#define BIT_ROM_PGE_8814B(x) (((x) & BIT_MASK_ROM_PGE_8814B) << BIT_SHIFT_ROM_PGE_8814B) -#define BIT_GET_ROM_PGE_8814B(x) (((x) >> BIT_SHIFT_ROM_PGE_8814B) & BIT_MASK_ROM_PGE_8814B) - +#define BIT_ROM_PGE_8814B(x) \ + (((x) & BIT_MASK_ROM_PGE_8814B) << BIT_SHIFT_ROM_PGE_8814B) +#define BITS_ROM_PGE_8814B (BIT_MASK_ROM_PGE_8814B << BIT_SHIFT_ROM_PGE_8814B) +#define BIT_CLEAR_ROM_PGE_8814B(x) ((x) & (~BITS_ROM_PGE_8814B)) +#define BIT_GET_ROM_PGE_8814B(x) \ + (((x) >> BIT_SHIFT_ROM_PGE_8814B) & BIT_MASK_ROM_PGE_8814B) +#define BIT_SET_ROM_PGE_8814B(x, v) \ + (BIT_CLEAR_ROM_PGE_8814B(x) | BIT_ROM_PGE_8814B(v)) #define BIT_FW_INIT_RDY_8814B BIT(15) #define BIT_FW_DW_RDY_8814B BIT(14) #define BIT_SHIFT_CPU_CLK_SEL_8814B 12 #define BIT_MASK_CPU_CLK_SEL_8814B 0x3 -#define BIT_CPU_CLK_SEL_8814B(x) (((x) & BIT_MASK_CPU_CLK_SEL_8814B) << BIT_SHIFT_CPU_CLK_SEL_8814B) -#define BIT_GET_CPU_CLK_SEL_8814B(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8814B) & BIT_MASK_CPU_CLK_SEL_8814B) - +#define BIT_CPU_CLK_SEL_8814B(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL_8814B) << BIT_SHIFT_CPU_CLK_SEL_8814B) +#define BITS_CPU_CLK_SEL_8814B \ + (BIT_MASK_CPU_CLK_SEL_8814B << BIT_SHIFT_CPU_CLK_SEL_8814B) +#define BIT_CLEAR_CPU_CLK_SEL_8814B(x) ((x) & (~BITS_CPU_CLK_SEL_8814B)) +#define BIT_GET_CPU_CLK_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL_8814B) & BIT_MASK_CPU_CLK_SEL_8814B) +#define BIT_SET_CPU_CLK_SEL_8814B(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL_8814B(x) | BIT_CPU_CLK_SEL_8814B(v)) #define BIT_CCLK_CHG_MASK_8814B BIT(11) #define BIT_EMEM__TXBUF_CHKSUM_OK_8814B BIT(10) @@ -1127,44 +1337,68 @@ /* 2 REG_MCU_TST_CFG_8814B */ -#define BIT_SHIFT_LBKTST_8814B 0 -#define BIT_MASK_LBKTST_8814B 0xffff -#define BIT_LBKTST_8814B(x) (((x) & BIT_MASK_LBKTST_8814B) << BIT_SHIFT_LBKTST_8814B) -#define BIT_GET_LBKTST_8814B(x) (((x) >> BIT_SHIFT_LBKTST_8814B) & BIT_MASK_LBKTST_8814B) - - +#define BIT_SHIFT_C2H_MSG_8814B 0 +#define BIT_MASK_C2H_MSG_8814B 0xffff +#define BIT_C2H_MSG_8814B(x) \ + (((x) & BIT_MASK_C2H_MSG_8814B) << BIT_SHIFT_C2H_MSG_8814B) +#define BITS_C2H_MSG_8814B (BIT_MASK_C2H_MSG_8814B << BIT_SHIFT_C2H_MSG_8814B) +#define BIT_CLEAR_C2H_MSG_8814B(x) ((x) & (~BITS_C2H_MSG_8814B)) +#define BIT_GET_C2H_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_C2H_MSG_8814B) & BIT_MASK_C2H_MSG_8814B) +#define BIT_SET_C2H_MSG_8814B(x, v) \ + (BIT_CLEAR_C2H_MSG_8814B(x) | BIT_C2H_MSG_8814B(v)) /* 2 REG_HMEBOX_E0_E1_8814B */ #define BIT_SHIFT_HOST_MSG_E1_8814B 16 #define BIT_MASK_HOST_MSG_E1_8814B 0xffff -#define BIT_HOST_MSG_E1_8814B(x) (((x) & BIT_MASK_HOST_MSG_E1_8814B) << BIT_SHIFT_HOST_MSG_E1_8814B) -#define BIT_GET_HOST_MSG_E1_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8814B) & BIT_MASK_HOST_MSG_E1_8814B) - - +#define BIT_HOST_MSG_E1_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_E1_8814B) << BIT_SHIFT_HOST_MSG_E1_8814B) +#define BITS_HOST_MSG_E1_8814B \ + (BIT_MASK_HOST_MSG_E1_8814B << BIT_SHIFT_HOST_MSG_E1_8814B) +#define BIT_CLEAR_HOST_MSG_E1_8814B(x) ((x) & (~BITS_HOST_MSG_E1_8814B)) +#define BIT_GET_HOST_MSG_E1_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1_8814B) & BIT_MASK_HOST_MSG_E1_8814B) +#define BIT_SET_HOST_MSG_E1_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_E1_8814B(x) | BIT_HOST_MSG_E1_8814B(v)) #define BIT_SHIFT_HOST_MSG_E0_8814B 0 #define BIT_MASK_HOST_MSG_E0_8814B 0xffff -#define BIT_HOST_MSG_E0_8814B(x) (((x) & BIT_MASK_HOST_MSG_E0_8814B) << BIT_SHIFT_HOST_MSG_E0_8814B) -#define BIT_GET_HOST_MSG_E0_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8814B) & BIT_MASK_HOST_MSG_E0_8814B) - - +#define BIT_HOST_MSG_E0_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_E0_8814B) << BIT_SHIFT_HOST_MSG_E0_8814B) +#define BITS_HOST_MSG_E0_8814B \ + (BIT_MASK_HOST_MSG_E0_8814B << BIT_SHIFT_HOST_MSG_E0_8814B) +#define BIT_CLEAR_HOST_MSG_E0_8814B(x) ((x) & (~BITS_HOST_MSG_E0_8814B)) +#define BIT_GET_HOST_MSG_E0_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0_8814B) & BIT_MASK_HOST_MSG_E0_8814B) +#define BIT_SET_HOST_MSG_E0_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_E0_8814B(x) | BIT_HOST_MSG_E0_8814B(v)) /* 2 REG_HMEBOX_E2_E3_8814B */ #define BIT_SHIFT_HOST_MSG_E3_8814B 16 #define BIT_MASK_HOST_MSG_E3_8814B 0xffff -#define BIT_HOST_MSG_E3_8814B(x) (((x) & BIT_MASK_HOST_MSG_E3_8814B) << BIT_SHIFT_HOST_MSG_E3_8814B) -#define BIT_GET_HOST_MSG_E3_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8814B) & BIT_MASK_HOST_MSG_E3_8814B) - - +#define BIT_HOST_MSG_E3_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_E3_8814B) << BIT_SHIFT_HOST_MSG_E3_8814B) +#define BITS_HOST_MSG_E3_8814B \ + (BIT_MASK_HOST_MSG_E3_8814B << BIT_SHIFT_HOST_MSG_E3_8814B) +#define BIT_CLEAR_HOST_MSG_E3_8814B(x) ((x) & (~BITS_HOST_MSG_E3_8814B)) +#define BIT_GET_HOST_MSG_E3_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3_8814B) & BIT_MASK_HOST_MSG_E3_8814B) +#define BIT_SET_HOST_MSG_E3_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_E3_8814B(x) | BIT_HOST_MSG_E3_8814B(v)) #define BIT_SHIFT_HOST_MSG_E2_8814B 0 #define BIT_MASK_HOST_MSG_E2_8814B 0xffff -#define BIT_HOST_MSG_E2_8814B(x) (((x) & BIT_MASK_HOST_MSG_E2_8814B) << BIT_SHIFT_HOST_MSG_E2_8814B) -#define BIT_GET_HOST_MSG_E2_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8814B) & BIT_MASK_HOST_MSG_E2_8814B) - - +#define BIT_HOST_MSG_E2_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_E2_8814B) << BIT_SHIFT_HOST_MSG_E2_8814B) +#define BITS_HOST_MSG_E2_8814B \ + (BIT_MASK_HOST_MSG_E2_8814B << BIT_SHIFT_HOST_MSG_E2_8814B) +#define BIT_CLEAR_HOST_MSG_E2_8814B(x) ((x) & (~BITS_HOST_MSG_E2_8814B)) +#define BIT_GET_HOST_MSG_E2_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2_8814B) & BIT_MASK_HOST_MSG_E2_8814B) +#define BIT_SET_HOST_MSG_E2_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_E2_8814B(x) | BIT_HOST_MSG_E2_8814B(v)) /* 2 REG_WLLPS_CTRL_8814B */ #define BIT_WLLPSOP_EABM_8814B BIT(31) @@ -1181,205 +1415,267 @@ #define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B 12 #define BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B 0xf -#define BIT_LPLDH12_VADJ_STEP_DN_8814B(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) -#define BIT_GET_LPLDH12_VADJ_STEP_DN_8814B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B) - - +#define BIT_LPLDH12_VADJ_STEP_DN_8814B(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B) \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) +#define BITS_LPLDH12_VADJ_STEP_DN_8814B \ + (BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) +#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8814B(x) \ + ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8814B)) +#define BIT_GET_LPLDH12_VADJ_STEP_DN_8814B(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) & \ + BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B) +#define BIT_SET_LPLDH12_VADJ_STEP_DN_8814B(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8814B(x) | \ + BIT_LPLDH12_VADJ_STEP_DN_8814B(v)) #define BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B 8 #define BIT_MASK_V15ADJ_L1_STEP_DN_8814B 0x7 -#define BIT_V15ADJ_L1_STEP_DN_8814B(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8814B) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) -#define BIT_GET_V15ADJ_L1_STEP_DN_8814B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) & BIT_MASK_V15ADJ_L1_STEP_DN_8814B) - +#define BIT_V15ADJ_L1_STEP_DN_8814B(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8814B) \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) +#define BITS_V15ADJ_L1_STEP_DN_8814B \ + (BIT_MASK_V15ADJ_L1_STEP_DN_8814B << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8814B(x) \ + ((x) & (~BITS_V15ADJ_L1_STEP_DN_8814B)) +#define BIT_GET_V15ADJ_L1_STEP_DN_8814B(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) & \ + BIT_MASK_V15ADJ_L1_STEP_DN_8814B) +#define BIT_SET_V15ADJ_L1_STEP_DN_8814B(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN_8814B(x) | BIT_V15ADJ_L1_STEP_DN_8814B(v)) #define BIT_REGU_32K_CLK_EN_8814B BIT(1) #define BIT_WL_LPS_EN_8814B BIT(0) /* 2 REG_AFE_CTRL5_8814B */ -#define BIT_BB_DBG_SEL_AFE_SDM_BIT0_8814B BIT(31) -#define BIT_ORDER_SDM_8814B BIT(30) -#define BIT_RFE_SEL_SDM_8814B BIT(29) - -#define BIT_SHIFT_REF_SEL_8814B 25 -#define BIT_MASK_REF_SEL_8814B 0xf -#define BIT_REF_SEL_8814B(x) (((x) & BIT_MASK_REF_SEL_8814B) << BIT_SHIFT_REF_SEL_8814B) -#define BIT_GET_REF_SEL_8814B(x) (((x) >> BIT_SHIFT_REF_SEL_8814B) & BIT_MASK_REF_SEL_8814B) - +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_F0F_SDM_8814B 12 -#define BIT_MASK_F0F_SDM_8814B 0x1fff -#define BIT_F0F_SDM_8814B(x) (((x) & BIT_MASK_F0F_SDM_8814B) << BIT_SHIFT_F0F_SDM_8814B) -#define BIT_GET_F0F_SDM_8814B(x) (((x) >> BIT_SHIFT_F0F_SDM_8814B) & BIT_MASK_F0F_SDM_8814B) - +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_F0N_SDM_8814B 9 -#define BIT_MASK_F0N_SDM_8814B 0x7 -#define BIT_F0N_SDM_8814B(x) (((x) & BIT_MASK_F0N_SDM_8814B) << BIT_SHIFT_F0N_SDM_8814B) -#define BIT_GET_F0N_SDM_8814B(x) (((x) >> BIT_SHIFT_F0N_SDM_8814B) & BIT_MASK_F0N_SDM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DIVN_SDM_8814B 3 -#define BIT_MASK_DIVN_SDM_8814B 0x3f -#define BIT_DIVN_SDM_8814B(x) (((x) & BIT_MASK_DIVN_SDM_8814B) << BIT_SHIFT_DIVN_SDM_8814B) -#define BIT_GET_DIVN_SDM_8814B(x) (((x) >> BIT_SHIFT_DIVN_SDM_8814B) & BIT_MASK_DIVN_SDM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_GPIO_DEBOUNCE_CTRL_8814B */ #define BIT_WLGP_DBC1EN_8814B BIT(15) #define BIT_SHIFT_WLGP_DBC1_8814B 8 #define BIT_MASK_WLGP_DBC1_8814B 0xf -#define BIT_WLGP_DBC1_8814B(x) (((x) & BIT_MASK_WLGP_DBC1_8814B) << BIT_SHIFT_WLGP_DBC1_8814B) -#define BIT_GET_WLGP_DBC1_8814B(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8814B) & BIT_MASK_WLGP_DBC1_8814B) - +#define BIT_WLGP_DBC1_8814B(x) \ + (((x) & BIT_MASK_WLGP_DBC1_8814B) << BIT_SHIFT_WLGP_DBC1_8814B) +#define BITS_WLGP_DBC1_8814B \ + (BIT_MASK_WLGP_DBC1_8814B << BIT_SHIFT_WLGP_DBC1_8814B) +#define BIT_CLEAR_WLGP_DBC1_8814B(x) ((x) & (~BITS_WLGP_DBC1_8814B)) +#define BIT_GET_WLGP_DBC1_8814B(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC1_8814B) & BIT_MASK_WLGP_DBC1_8814B) +#define BIT_SET_WLGP_DBC1_8814B(x, v) \ + (BIT_CLEAR_WLGP_DBC1_8814B(x) | BIT_WLGP_DBC1_8814B(v)) #define BIT_WLGP_DBC0EN_8814B BIT(7) #define BIT_SHIFT_WLGP_DBC0_8814B 0 #define BIT_MASK_WLGP_DBC0_8814B 0xf -#define BIT_WLGP_DBC0_8814B(x) (((x) & BIT_MASK_WLGP_DBC0_8814B) << BIT_SHIFT_WLGP_DBC0_8814B) -#define BIT_GET_WLGP_DBC0_8814B(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8814B) & BIT_MASK_WLGP_DBC0_8814B) +#define BIT_WLGP_DBC0_8814B(x) \ + (((x) & BIT_MASK_WLGP_DBC0_8814B) << BIT_SHIFT_WLGP_DBC0_8814B) +#define BITS_WLGP_DBC0_8814B \ + (BIT_MASK_WLGP_DBC0_8814B << BIT_SHIFT_WLGP_DBC0_8814B) +#define BIT_CLEAR_WLGP_DBC0_8814B(x) ((x) & (~BITS_WLGP_DBC0_8814B)) +#define BIT_GET_WLGP_DBC0_8814B(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC0_8814B) & BIT_MASK_WLGP_DBC0_8814B) +#define BIT_SET_WLGP_DBC0_8814B(x, v) \ + (BIT_CLEAR_WLGP_DBC0_8814B(x) | BIT_WLGP_DBC0_8814B(v)) - - -/* 2 REG_RPWM2_8814B */ +/* 2 REG_RPWM2_8814B */ #define BIT_SHIFT_RPWM2_8814B 16 #define BIT_MASK_RPWM2_8814B 0xffff -#define BIT_RPWM2_8814B(x) (((x) & BIT_MASK_RPWM2_8814B) << BIT_SHIFT_RPWM2_8814B) -#define BIT_GET_RPWM2_8814B(x) (((x) >> BIT_SHIFT_RPWM2_8814B) & BIT_MASK_RPWM2_8814B) - - +#define BIT_RPWM2_8814B(x) \ + (((x) & BIT_MASK_RPWM2_8814B) << BIT_SHIFT_RPWM2_8814B) +#define BITS_RPWM2_8814B (BIT_MASK_RPWM2_8814B << BIT_SHIFT_RPWM2_8814B) +#define BIT_CLEAR_RPWM2_8814B(x) ((x) & (~BITS_RPWM2_8814B)) +#define BIT_GET_RPWM2_8814B(x) \ + (((x) >> BIT_SHIFT_RPWM2_8814B) & BIT_MASK_RPWM2_8814B) +#define BIT_SET_RPWM2_8814B(x, v) \ + (BIT_CLEAR_RPWM2_8814B(x) | BIT_RPWM2_8814B(v)) /* 2 REG_SYSON_FSM_MON_8814B */ #define BIT_SHIFT_FSM_MON_SEL_8814B 24 #define BIT_MASK_FSM_MON_SEL_8814B 0x7 -#define BIT_FSM_MON_SEL_8814B(x) (((x) & BIT_MASK_FSM_MON_SEL_8814B) << BIT_SHIFT_FSM_MON_SEL_8814B) -#define BIT_GET_FSM_MON_SEL_8814B(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8814B) & BIT_MASK_FSM_MON_SEL_8814B) - +#define BIT_FSM_MON_SEL_8814B(x) \ + (((x) & BIT_MASK_FSM_MON_SEL_8814B) << BIT_SHIFT_FSM_MON_SEL_8814B) +#define BITS_FSM_MON_SEL_8814B \ + (BIT_MASK_FSM_MON_SEL_8814B << BIT_SHIFT_FSM_MON_SEL_8814B) +#define BIT_CLEAR_FSM_MON_SEL_8814B(x) ((x) & (~BITS_FSM_MON_SEL_8814B)) +#define BIT_GET_FSM_MON_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL_8814B) & BIT_MASK_FSM_MON_SEL_8814B) +#define BIT_SET_FSM_MON_SEL_8814B(x, v) \ + (BIT_CLEAR_FSM_MON_SEL_8814B(x) | BIT_FSM_MON_SEL_8814B(v)) #define BIT_DOP_ELDO_8814B BIT(23) #define BIT_FSM_MON_UPD_8814B BIT(15) #define BIT_SHIFT_FSM_PAR_8814B 0 #define BIT_MASK_FSM_PAR_8814B 0x7fff -#define BIT_FSM_PAR_8814B(x) (((x) & BIT_MASK_FSM_PAR_8814B) << BIT_SHIFT_FSM_PAR_8814B) -#define BIT_GET_FSM_PAR_8814B(x) (((x) >> BIT_SHIFT_FSM_PAR_8814B) & BIT_MASK_FSM_PAR_8814B) - - +#define BIT_FSM_PAR_8814B(x) \ + (((x) & BIT_MASK_FSM_PAR_8814B) << BIT_SHIFT_FSM_PAR_8814B) +#define BITS_FSM_PAR_8814B (BIT_MASK_FSM_PAR_8814B << BIT_SHIFT_FSM_PAR_8814B) +#define BIT_CLEAR_FSM_PAR_8814B(x) ((x) & (~BITS_FSM_PAR_8814B)) +#define BIT_GET_FSM_PAR_8814B(x) \ + (((x) >> BIT_SHIFT_FSM_PAR_8814B) & BIT_MASK_FSM_PAR_8814B) +#define BIT_SET_FSM_PAR_8814B(x, v) \ + (BIT_CLEAR_FSM_PAR_8814B(x) | BIT_FSM_PAR_8814B(v)) /* 2 REG_AFE_CTRL6_8814B */ -#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B 0 -#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8814B) - +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_PMC_DBG_CTRL1_8814B */ #define BIT_BT_INT_EN_8814B BIT(31) #define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B 16 #define BIT_MASK_RD_WR_WIFI_BT_INFO_8814B 0x7fff -#define BIT_RD_WR_WIFI_BT_INFO_8814B(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8814B) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) -#define BIT_GET_RD_WR_WIFI_BT_INFO_8814B(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) & BIT_MASK_RD_WR_WIFI_BT_INFO_8814B) - +#define BIT_RD_WR_WIFI_BT_INFO_8814B(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8814B) \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) +#define BITS_RD_WR_WIFI_BT_INFO_8814B \ + (BIT_MASK_RD_WR_WIFI_BT_INFO_8814B \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8814B(x) \ + ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8814B)) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) & \ + BIT_MASK_RD_WR_WIFI_BT_INFO_8814B) +#define BIT_SET_RD_WR_WIFI_BT_INFO_8814B(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8814B(x) | \ + BIT_RD_WR_WIFI_BT_INFO_8814B(v)) #define BIT_PMC_WR_OVF_8814B BIT(8) #define BIT_SHIFT_WLPMC_ERRINT_8814B 0 #define BIT_MASK_WLPMC_ERRINT_8814B 0xff -#define BIT_WLPMC_ERRINT_8814B(x) (((x) & BIT_MASK_WLPMC_ERRINT_8814B) << BIT_SHIFT_WLPMC_ERRINT_8814B) -#define BIT_GET_WLPMC_ERRINT_8814B(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8814B) & BIT_MASK_WLPMC_ERRINT_8814B) +#define BIT_WLPMC_ERRINT_8814B(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT_8814B) << BIT_SHIFT_WLPMC_ERRINT_8814B) +#define BITS_WLPMC_ERRINT_8814B \ + (BIT_MASK_WLPMC_ERRINT_8814B << BIT_SHIFT_WLPMC_ERRINT_8814B) +#define BIT_CLEAR_WLPMC_ERRINT_8814B(x) ((x) & (~BITS_WLPMC_ERRINT_8814B)) +#define BIT_GET_WLPMC_ERRINT_8814B(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT_8814B) & BIT_MASK_WLPMC_ERRINT_8814B) +#define BIT_SET_WLPMC_ERRINT_8814B(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT_8814B(x) | BIT_WLPMC_ERRINT_8814B(v)) +/* 2 REG_AFE_CTRL7_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_AFE_CTRL7_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SEL_V_8814B 30 -#define BIT_MASK_SEL_V_8814B 0x3 -#define BIT_SEL_V_8814B(x) (((x) & BIT_MASK_SEL_V_8814B) << BIT_SHIFT_SEL_V_8814B) -#define BIT_GET_SEL_V_8814B(x) (((x) >> BIT_SHIFT_SEL_V_8814B) & BIT_MASK_SEL_V_8814B) +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SEL_LDO_PC_8814B BIT(29) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CK_MON_SEL_8814B 26 -#define BIT_MASK_CK_MON_SEL_8814B 0x7 -#define BIT_CK_MON_SEL_8814B(x) (((x) & BIT_MASK_CK_MON_SEL_8814B) << BIT_SHIFT_CK_MON_SEL_8814B) -#define BIT_GET_CK_MON_SEL_8814B(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8814B) & BIT_MASK_CK_MON_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_CK_MON_EN_8814B BIT(25) -#define BIT_FREF_EDGE_8814B BIT(24) -#define BIT_CK320M_EN_8814B BIT(23) -#define BIT_CK_5M_EN_8814B BIT(22) -#define BIT_TESTEN_8814B BIT(21) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_HIMR0_8814B */ -#define BIT_TIMEOUT_INTERRUPT2_MASK_8814B BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_MASK_8814B BIT(30) -#define BIT_PSTIMEOUT_MSK_8814B BIT(29) +#define BIT_PSTIMER_2_MSK_8814B BIT(31) +#define BIT_PSTIMER_1_MSK_8814B BIT(30) +#define BIT_PSTIMER_0_MSK_8814B BIT(29) #define BIT_GTINT4_MSK_8814B BIT(28) #define BIT_GTINT3_MSK_8814B BIT(27) #define BIT_TXBCN0ERR_MSK_8814B BIT(26) #define BIT_TXBCN0OK_MSK_8814B BIT(25) #define BIT_TSF_BIT32_TOGGLE_MSK_8814B BIT(24) +#define BIT_TXDMA_START_INT_MSK_8814B BIT(23) +#define BIT_TXDMA_STOP_INT_MSK_8814B BIT(22) +#define BIT_HISR7_IND_MSK_8814B BIT(21) #define BIT_BCNDMAINT0_MSK_8814B BIT(20) +#define BIT_HISR6_IND_MSK_8814B BIT(19) +#define BIT_HISR5_IND_MSK_8814B BIT(18) +#define BIT_HISR4_IND_MSK_8814B BIT(17) #define BIT_BCNDERR0_MSK_8814B BIT(16) #define BIT_HSISR_IND_ON_INT_MSK_8814B BIT(15) -#define BIT_BCNDMAINT_E_MSK_8814B BIT(14) -#define BIT_CTWEND_MSK_8814B BIT(12) +#define BIT_HISR3_IND_MSK_8814B BIT(14) +#define BIT_HISR2_IND_MSK_8814B BIT(13) + +/* 2 REG_NOT_VALID_8814B */ #define BIT_HISR1_IND_MSK_8814B BIT(11) #define BIT_C2HCMD_MSK_8814B BIT(10) #define BIT_CPWM2_MSK_8814B BIT(9) #define BIT_CPWM_MSK_8814B BIT(8) -#define BIT_HIGHDOK_MSK_8814B BIT(7) -#define BIT_MGTDOK_MSK_8814B BIT(6) -#define BIT_BKDOK_MSK_8814B BIT(5) -#define BIT_BEDOK_MSK_8814B BIT(4) -#define BIT_VIDOK_MSK_8814B BIT(3) -#define BIT_VODOK_MSK_8814B BIT(2) +#define BIT_TXDMAOK_CHANNEL15_MSK_8814B BIT(7) +#define BIT_TXDMAOK_CHANNEL14_MSK_8814B BIT(6) +#define BIT_TXDMAOK_CHANNEL3_MSK_8814B BIT(5) +#define BIT_TXDMAOK_CHANNEL2_MSK_8814B BIT(4) +#define BIT_TXDMAOK_CHANNEL1_MSK_8814B BIT(3) +#define BIT_TXDMAOK_CHANNEL0_MSK_8814B BIT(2) #define BIT_RDU_MSK_8814B BIT(1) #define BIT_RXOK_MSK_8814B BIT(0) /* 2 REG_HISR0_8814B */ -#define BIT_TIMEOUT_INTERRUPT2_8814B BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_8814B BIT(30) -#define BIT_PSTIMEOUT_8814B BIT(29) +#define BIT_PSTIMER_2_8814B BIT(31) +#define BIT_PSTIMER_1_8814B BIT(30) +#define BIT_PSTIMER_0_8814B BIT(29) #define BIT_GTINT4_8814B BIT(28) #define BIT_GTINT3_8814B BIT(27) #define BIT_TXBCN0ERR_8814B BIT(26) #define BIT_TXBCN0OK_8814B BIT(25) #define BIT_TSF_BIT32_TOGGLE_8814B BIT(24) +#define BIT_TXDMA_START_INT_8814B BIT(23) +#define BIT_TXDMA_STOP_INT_8814B BIT(22) +#define BIT_HISR7_IND_8814B BIT(21) #define BIT_BCNDMAINT0_8814B BIT(20) +#define BIT_HISR6_IND_8814B BIT(19) +#define BIT_HISR5_IND_8814B BIT(18) +#define BIT_HISR4_IND_8814B BIT(17) #define BIT_BCNDERR0_8814B BIT(16) #define BIT_HSISR_IND_ON_INT_8814B BIT(15) -#define BIT_BCNDMAINT_E_8814B BIT(14) -#define BIT_CTWEND_8814B BIT(12) -#define BIT_HISR1_IND_INT_8814B BIT(11) +#define BIT_HISR3_IND_8814B BIT(14) +#define BIT_HISR2_IND_8814B BIT(13) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_HISR1_IND_8814B BIT(11) #define BIT_C2HCMD_8814B BIT(10) #define BIT_CPWM2_8814B BIT(9) #define BIT_CPWM_8814B BIT(8) -#define BIT_HIGHDOK_8814B BIT(7) -#define BIT_MGTDOK_8814B BIT(6) -#define BIT_BKDOK_8814B BIT(5) -#define BIT_BEDOK_8814B BIT(4) -#define BIT_VIDOK_8814B BIT(3) -#define BIT_VODOK_8814B BIT(2) +#define BIT_TXDMAOK_CHANNEL15_8814B BIT(7) +#define BIT_TXDMAOK_CHANNEL14_8814B BIT(6) +#define BIT_TXDMAOK_CHANNEL3_8814B BIT(5) +#define BIT_TXDMAOK_CHANNEL2_8814B BIT(4) +#define BIT_TXDMAOK_CHANNEL1_8814B BIT(3) +#define BIT_TXDMAOK_CHANNEL0_8814B BIT(2) #define BIT_RDU_8814B BIT(1) #define BIT_RXOK_8814B BIT(0) /* 2 REG_HIMR1_8814B */ +#define BIT_PRE_TX_ERR_INT_MSK_8814B BIT(31) #define BIT_TXFIFO_TH_INT_8814B BIT(30) #define BIT_BTON_STS_UPDATE_MASK_8814B BIT(29) -#define BIT_MCU_ERR_MASK_8814B BIT(28) #define BIT_BCNDMAINT7__MSK_8814B BIT(27) #define BIT_BCNDMAINT6__MSK_8814B BIT(26) #define BIT_BCNDMAINT5__MSK_8814B BIT(25) @@ -1394,22 +1690,23 @@ #define BIT_BCNDERR3_MSK_8814B BIT(16) #define BIT_BCNDERR2_MSK_8814B BIT(15) #define BIT_BCNDERR1_MSK_8814B BIT(14) -#define BIT_ATIMEND_E_MSK_8814B BIT(13) #define BIT_ATIMEND__MSK_8814B BIT(12) #define BIT_TXERR_MSK_8814B BIT(11) #define BIT_RXERR_MSK_8814B BIT(10) #define BIT_TXFOVW_MSK_8814B BIT(9) #define BIT_FOVW_MSK_8814B BIT(8) +#define BIT_CPU_MGQ_EARLY_INT_MSK_8814B BIT(6) #define BIT_CPU_MGQ_TXDONE_MSK_8814B BIT(5) -#define BIT_PS_TIMER_C_MSK_8814B BIT(4) -#define BIT_PS_TIMER_B_MSK_8814B BIT(3) -#define BIT_PS_TIMER_A_MSK_8814B BIT(2) +#define BIT_PSTIMER_5_MSK_8814B BIT(4) +#define BIT_PSTIMER_4_MSK_8814B BIT(3) +#define BIT_PSTIMER_3_MSK_8814B BIT(2) #define BIT_CPUMGQ_TX_TIMER_MSK_8814B BIT(1) +#define BIT_BB_STOPRX_INT_MSK_8814B BIT(0) /* 2 REG_HISR1_8814B */ +#define BIT_PRE_TX_ERR_INT_8814B BIT(31) #define BIT_TXFIFO_TH_INT_8814B BIT(30) #define BIT_BTON_STS_UPDATE_INT_8814B BIT(29) -#define BIT_MCU_ERR_8814B BIT(28) #define BIT_BCNDMAINT7_8814B BIT(27) #define BIT_BCNDMAINT6_8814B BIT(26) #define BIT_BCNDMAINT5_8814B BIT(25) @@ -1424,7 +1721,6 @@ #define BIT_BCNDERR3_8814B BIT(16) #define BIT_BCNDERR2_8814B BIT(15) #define BIT_BCNDERR1_8814B BIT(14) -#define BIT_ATIMEND_E_8814B BIT(13) #define BIT_ATIMEND_8814B BIT(12) #define BIT_TXERR_INT_8814B BIT(11) #define BIT_RXERR_INT_8814B BIT(10) @@ -1432,38 +1728,60 @@ #define BIT_FOVW_8814B BIT(8) /* 2 REG_NOT_VALID_8814B */ +#define BIT_CPU_MGQ_EARLY_INT_8814B BIT(6) #define BIT_CPU_MGQ_TXDONE_8814B BIT(5) -#define BIT_PS_TIMER_C_8814B BIT(4) -#define BIT_PS_TIMER_B_8814B BIT(3) -#define BIT_PS_TIMER_A_8814B BIT(2) +#define BIT_PSTIMER_5_8814B BIT(4) +#define BIT_PSTIMER_4_8814B BIT(3) +#define BIT_PSTIMER_3_8814B BIT(2) #define BIT_CPUMGQ_TX_TIMER_8814B BIT(1) +#define BIT_BB_STOPRX_INT_8814B BIT(0) /* 2 REG_DBG_PORT_SEL_8814B */ #define BIT_SHIFT_DEBUG_ST_8814B 0 #define BIT_MASK_DEBUG_ST_8814B 0xffffffffL -#define BIT_DEBUG_ST_8814B(x) (((x) & BIT_MASK_DEBUG_ST_8814B) << BIT_SHIFT_DEBUG_ST_8814B) -#define BIT_GET_DEBUG_ST_8814B(x) (((x) >> BIT_SHIFT_DEBUG_ST_8814B) & BIT_MASK_DEBUG_ST_8814B) - - +#define BIT_DEBUG_ST_8814B(x) \ + (((x) & BIT_MASK_DEBUG_ST_8814B) << BIT_SHIFT_DEBUG_ST_8814B) +#define BITS_DEBUG_ST_8814B \ + (BIT_MASK_DEBUG_ST_8814B << BIT_SHIFT_DEBUG_ST_8814B) +#define BIT_CLEAR_DEBUG_ST_8814B(x) ((x) & (~BITS_DEBUG_ST_8814B)) +#define BIT_GET_DEBUG_ST_8814B(x) \ + (((x) >> BIT_SHIFT_DEBUG_ST_8814B) & BIT_MASK_DEBUG_ST_8814B) +#define BIT_SET_DEBUG_ST_8814B(x, v) \ + (BIT_CLEAR_DEBUG_ST_8814B(x) | BIT_DEBUG_ST_8814B(v)) /* 2 REG_PAD_CTRL2_8814B */ #define BIT_USB3_USB2_TRANSITION_8814B BIT(20) #define BIT_SHIFT_USB23_SW_MODE_V1_8814B 18 #define BIT_MASK_USB23_SW_MODE_V1_8814B 0x3 -#define BIT_USB23_SW_MODE_V1_8814B(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8814B) << BIT_SHIFT_USB23_SW_MODE_V1_8814B) -#define BIT_GET_USB23_SW_MODE_V1_8814B(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8814B) & BIT_MASK_USB23_SW_MODE_V1_8814B) - +#define BIT_USB23_SW_MODE_V1_8814B(x) \ + (((x) & BIT_MASK_USB23_SW_MODE_V1_8814B) \ + << BIT_SHIFT_USB23_SW_MODE_V1_8814B) +#define BITS_USB23_SW_MODE_V1_8814B \ + (BIT_MASK_USB23_SW_MODE_V1_8814B << BIT_SHIFT_USB23_SW_MODE_V1_8814B) +#define BIT_CLEAR_USB23_SW_MODE_V1_8814B(x) \ + ((x) & (~BITS_USB23_SW_MODE_V1_8814B)) +#define BIT_GET_USB23_SW_MODE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8814B) & \ + BIT_MASK_USB23_SW_MODE_V1_8814B) +#define BIT_SET_USB23_SW_MODE_V1_8814B(x, v) \ + (BIT_CLEAR_USB23_SW_MODE_V1_8814B(x) | BIT_USB23_SW_MODE_V1_8814B(v)) #define BIT_NO_PDN_CHIPOFF_V1_8814B BIT(17) #define BIT_RSM_EN_V1_8814B BIT(16) #define BIT_SHIFT_MATCH_CNT_8814B 8 #define BIT_MASK_MATCH_CNT_8814B 0xff -#define BIT_MATCH_CNT_8814B(x) (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B) -#define BIT_GET_MATCH_CNT_8814B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B) - +#define BIT_MATCH_CNT_8814B(x) \ + (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B) +#define BITS_MATCH_CNT_8814B \ + (BIT_MASK_MATCH_CNT_8814B << BIT_SHIFT_MATCH_CNT_8814B) +#define BIT_CLEAR_MATCH_CNT_8814B(x) ((x) & (~BITS_MATCH_CNT_8814B)) +#define BIT_GET_MATCH_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B) +#define BIT_SET_MATCH_CNT_8814B(x, v) \ + (BIT_CLEAR_MATCH_CNT_8814B(x) | BIT_MATCH_CNT_8814B(v)) #define BIT_LD_B12V_EN_8814B BIT(7) #define BIT_EECS_IOSEL_V1_8814B BIT(6) @@ -1479,9 +1797,17 @@ #define BIT_SHIFT_EFUSE_BURN_GNT_8814B 24 #define BIT_MASK_EFUSE_BURN_GNT_8814B 0xff -#define BIT_EFUSE_BURN_GNT_8814B(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8814B) << BIT_SHIFT_EFUSE_BURN_GNT_8814B) -#define BIT_GET_EFUSE_BURN_GNT_8814B(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8814B) & BIT_MASK_EFUSE_BURN_GNT_8814B) - +#define BIT_EFUSE_BURN_GNT_8814B(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT_8814B) \ + << BIT_SHIFT_EFUSE_BURN_GNT_8814B) +#define BITS_EFUSE_BURN_GNT_8814B \ + (BIT_MASK_EFUSE_BURN_GNT_8814B << BIT_SHIFT_EFUSE_BURN_GNT_8814B) +#define BIT_CLEAR_EFUSE_BURN_GNT_8814B(x) ((x) & (~BITS_EFUSE_BURN_GNT_8814B)) +#define BIT_GET_EFUSE_BURN_GNT_8814B(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8814B) & \ + BIT_MASK_EFUSE_BURN_GNT_8814B) +#define BIT_SET_EFUSE_BURN_GNT_8814B(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT_8814B(x) | BIT_EFUSE_BURN_GNT_8814B(v)) #define BIT_STOP_WL_PMC_8814B BIT(9) #define BIT_STOP_SYM_PMC_8814B BIT(8) @@ -1493,101 +1819,130 @@ #define BIT_SHIFT_SYSON_REG_ARB_8814B 0 #define BIT_MASK_SYSON_REG_ARB_8814B 0x3 -#define BIT_SYSON_REG_ARB_8814B(x) (((x) & BIT_MASK_SYSON_REG_ARB_8814B) << BIT_SHIFT_SYSON_REG_ARB_8814B) -#define BIT_GET_SYSON_REG_ARB_8814B(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8814B) & BIT_MASK_SYSON_REG_ARB_8814B) - - - -/* 2 REG_BIST_CTRL_8814B */ -#define BIT_BIST_USB_DIS_8814B BIT(27) -#define BIT_BIST_PCI_DIS_8814B BIT(26) -#define BIT_BIST_BT_DIS_8814B BIT(25) -#define BIT_BIST_WL_DIS_8814B BIT(24) - -#define BIT_SHIFT_BIST_RPT_SEL_8814B 16 -#define BIT_MASK_BIST_RPT_SEL_8814B 0xf -#define BIT_BIST_RPT_SEL_8814B(x) (((x) & BIT_MASK_BIST_RPT_SEL_8814B) << BIT_SHIFT_BIST_RPT_SEL_8814B) -#define BIT_GET_BIST_RPT_SEL_8814B(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8814B) & BIT_MASK_BIST_RPT_SEL_8814B) - - -#define BIT_BIST_RESUME_PS_8814B BIT(4) -#define BIT_BIST_RESUME_8814B BIT(3) -#define BIT_BIST_NORMAL_8814B BIT(2) -#define BIT_BIST_RSTN_8814B BIT(1) -#define BIT_BIST_CLK_EN_8814B BIT(0) - -/* 2 REG_BIST_RPT_8814B */ - -#define BIT_SHIFT_MBIST_REPORT_8814B 0 -#define BIT_MASK_MBIST_REPORT_8814B 0xffffffffL -#define BIT_MBIST_REPORT_8814B(x) (((x) & BIT_MASK_MBIST_REPORT_8814B) << BIT_SHIFT_MBIST_REPORT_8814B) -#define BIT_GET_MBIST_REPORT_8814B(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8814B) & BIT_MASK_MBIST_REPORT_8814B) +#define BIT_SYSON_REG_ARB_8814B(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB_8814B) << BIT_SHIFT_SYSON_REG_ARB_8814B) +#define BITS_SYSON_REG_ARB_8814B \ + (BIT_MASK_SYSON_REG_ARB_8814B << BIT_SHIFT_SYSON_REG_ARB_8814B) +#define BIT_CLEAR_SYSON_REG_ARB_8814B(x) ((x) & (~BITS_SYSON_REG_ARB_8814B)) +#define BIT_GET_SYSON_REG_ARB_8814B(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB_8814B) & BIT_MASK_SYSON_REG_ARB_8814B) +#define BIT_SET_SYSON_REG_ARB_8814B(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB_8814B(x) | BIT_SYSON_REG_ARB_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_MEM_CTRL_8814B */ #define BIT_UMEM_RME_8814B BIT(31) #define BIT_SHIFT_BT_SPRAM_8814B 28 #define BIT_MASK_BT_SPRAM_8814B 0x3 -#define BIT_BT_SPRAM_8814B(x) (((x) & BIT_MASK_BT_SPRAM_8814B) << BIT_SHIFT_BT_SPRAM_8814B) -#define BIT_GET_BT_SPRAM_8814B(x) (((x) >> BIT_SHIFT_BT_SPRAM_8814B) & BIT_MASK_BT_SPRAM_8814B) - - +#define BIT_BT_SPRAM_8814B(x) \ + (((x) & BIT_MASK_BT_SPRAM_8814B) << BIT_SHIFT_BT_SPRAM_8814B) +#define BITS_BT_SPRAM_8814B \ + (BIT_MASK_BT_SPRAM_8814B << BIT_SHIFT_BT_SPRAM_8814B) +#define BIT_CLEAR_BT_SPRAM_8814B(x) ((x) & (~BITS_BT_SPRAM_8814B)) +#define BIT_GET_BT_SPRAM_8814B(x) \ + (((x) >> BIT_SHIFT_BT_SPRAM_8814B) & BIT_MASK_BT_SPRAM_8814B) +#define BIT_SET_BT_SPRAM_8814B(x, v) \ + (BIT_CLEAR_BT_SPRAM_8814B(x) | BIT_BT_SPRAM_8814B(v)) #define BIT_SHIFT_BT_ROM_8814B 24 #define BIT_MASK_BT_ROM_8814B 0xf -#define BIT_BT_ROM_8814B(x) (((x) & BIT_MASK_BT_ROM_8814B) << BIT_SHIFT_BT_ROM_8814B) -#define BIT_GET_BT_ROM_8814B(x) (((x) >> BIT_SHIFT_BT_ROM_8814B) & BIT_MASK_BT_ROM_8814B) - - +#define BIT_BT_ROM_8814B(x) \ + (((x) & BIT_MASK_BT_ROM_8814B) << BIT_SHIFT_BT_ROM_8814B) +#define BITS_BT_ROM_8814B (BIT_MASK_BT_ROM_8814B << BIT_SHIFT_BT_ROM_8814B) +#define BIT_CLEAR_BT_ROM_8814B(x) ((x) & (~BITS_BT_ROM_8814B)) +#define BIT_GET_BT_ROM_8814B(x) \ + (((x) >> BIT_SHIFT_BT_ROM_8814B) & BIT_MASK_BT_ROM_8814B) +#define BIT_SET_BT_ROM_8814B(x, v) \ + (BIT_CLEAR_BT_ROM_8814B(x) | BIT_BT_ROM_8814B(v)) #define BIT_SHIFT_PCI_DPRAM_8814B 10 #define BIT_MASK_PCI_DPRAM_8814B 0x3 -#define BIT_PCI_DPRAM_8814B(x) (((x) & BIT_MASK_PCI_DPRAM_8814B) << BIT_SHIFT_PCI_DPRAM_8814B) -#define BIT_GET_PCI_DPRAM_8814B(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8814B) & BIT_MASK_PCI_DPRAM_8814B) - - +#define BIT_PCI_DPRAM_8814B(x) \ + (((x) & BIT_MASK_PCI_DPRAM_8814B) << BIT_SHIFT_PCI_DPRAM_8814B) +#define BITS_PCI_DPRAM_8814B \ + (BIT_MASK_PCI_DPRAM_8814B << BIT_SHIFT_PCI_DPRAM_8814B) +#define BIT_CLEAR_PCI_DPRAM_8814B(x) ((x) & (~BITS_PCI_DPRAM_8814B)) +#define BIT_GET_PCI_DPRAM_8814B(x) \ + (((x) >> BIT_SHIFT_PCI_DPRAM_8814B) & BIT_MASK_PCI_DPRAM_8814B) +#define BIT_SET_PCI_DPRAM_8814B(x, v) \ + (BIT_CLEAR_PCI_DPRAM_8814B(x) | BIT_PCI_DPRAM_8814B(v)) #define BIT_SHIFT_PCI_SPRAM_8814B 8 #define BIT_MASK_PCI_SPRAM_8814B 0x3 -#define BIT_PCI_SPRAM_8814B(x) (((x) & BIT_MASK_PCI_SPRAM_8814B) << BIT_SHIFT_PCI_SPRAM_8814B) -#define BIT_GET_PCI_SPRAM_8814B(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8814B) & BIT_MASK_PCI_SPRAM_8814B) - - +#define BIT_PCI_SPRAM_8814B(x) \ + (((x) & BIT_MASK_PCI_SPRAM_8814B) << BIT_SHIFT_PCI_SPRAM_8814B) +#define BITS_PCI_SPRAM_8814B \ + (BIT_MASK_PCI_SPRAM_8814B << BIT_SHIFT_PCI_SPRAM_8814B) +#define BIT_CLEAR_PCI_SPRAM_8814B(x) ((x) & (~BITS_PCI_SPRAM_8814B)) +#define BIT_GET_PCI_SPRAM_8814B(x) \ + (((x) >> BIT_SHIFT_PCI_SPRAM_8814B) & BIT_MASK_PCI_SPRAM_8814B) +#define BIT_SET_PCI_SPRAM_8814B(x, v) \ + (BIT_CLEAR_PCI_SPRAM_8814B(x) | BIT_PCI_SPRAM_8814B(v)) #define BIT_SHIFT_USB_SPRAM_8814B 6 #define BIT_MASK_USB_SPRAM_8814B 0x3 -#define BIT_USB_SPRAM_8814B(x) (((x) & BIT_MASK_USB_SPRAM_8814B) << BIT_SHIFT_USB_SPRAM_8814B) -#define BIT_GET_USB_SPRAM_8814B(x) (((x) >> BIT_SHIFT_USB_SPRAM_8814B) & BIT_MASK_USB_SPRAM_8814B) - - +#define BIT_USB_SPRAM_8814B(x) \ + (((x) & BIT_MASK_USB_SPRAM_8814B) << BIT_SHIFT_USB_SPRAM_8814B) +#define BITS_USB_SPRAM_8814B \ + (BIT_MASK_USB_SPRAM_8814B << BIT_SHIFT_USB_SPRAM_8814B) +#define BIT_CLEAR_USB_SPRAM_8814B(x) ((x) & (~BITS_USB_SPRAM_8814B)) +#define BIT_GET_USB_SPRAM_8814B(x) \ + (((x) >> BIT_SHIFT_USB_SPRAM_8814B) & BIT_MASK_USB_SPRAM_8814B) +#define BIT_SET_USB_SPRAM_8814B(x, v) \ + (BIT_CLEAR_USB_SPRAM_8814B(x) | BIT_USB_SPRAM_8814B(v)) #define BIT_SHIFT_USB_SPRF_8814B 4 #define BIT_MASK_USB_SPRF_8814B 0x3 -#define BIT_USB_SPRF_8814B(x) (((x) & BIT_MASK_USB_SPRF_8814B) << BIT_SHIFT_USB_SPRF_8814B) -#define BIT_GET_USB_SPRF_8814B(x) (((x) >> BIT_SHIFT_USB_SPRF_8814B) & BIT_MASK_USB_SPRF_8814B) - - +#define BIT_USB_SPRF_8814B(x) \ + (((x) & BIT_MASK_USB_SPRF_8814B) << BIT_SHIFT_USB_SPRF_8814B) +#define BITS_USB_SPRF_8814B \ + (BIT_MASK_USB_SPRF_8814B << BIT_SHIFT_USB_SPRF_8814B) +#define BIT_CLEAR_USB_SPRF_8814B(x) ((x) & (~BITS_USB_SPRF_8814B)) +#define BIT_GET_USB_SPRF_8814B(x) \ + (((x) >> BIT_SHIFT_USB_SPRF_8814B) & BIT_MASK_USB_SPRF_8814B) +#define BIT_SET_USB_SPRF_8814B(x, v) \ + (BIT_CLEAR_USB_SPRF_8814B(x) | BIT_USB_SPRF_8814B(v)) #define BIT_SHIFT_MCU_ROM_8814B 0 #define BIT_MASK_MCU_ROM_8814B 0xf -#define BIT_MCU_ROM_8814B(x) (((x) & BIT_MASK_MCU_ROM_8814B) << BIT_SHIFT_MCU_ROM_8814B) -#define BIT_GET_MCU_ROM_8814B(x) (((x) >> BIT_SHIFT_MCU_ROM_8814B) & BIT_MASK_MCU_ROM_8814B) - - - -/* 2 REG_AFE_CTRL8_8814B */ -#define BIT_SYN_AGPIO_8814B BIT(20) -#define BIT_XTAL_LP_8814B BIT(4) -#define BIT_XTAL_GM_SEP_8814B BIT(3) - -#define BIT_SHIFT_XTAL_SEL_TOK_8814B 0 -#define BIT_MASK_XTAL_SEL_TOK_8814B 0x7 -#define BIT_XTAL_SEL_TOK_8814B(x) (((x) & BIT_MASK_XTAL_SEL_TOK_8814B) << BIT_SHIFT_XTAL_SEL_TOK_8814B) -#define BIT_GET_XTAL_SEL_TOK_8814B(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8814B) & BIT_MASK_XTAL_SEL_TOK_8814B) - - +#define BIT_MCU_ROM_8814B(x) \ + (((x) & BIT_MASK_MCU_ROM_8814B) << BIT_SHIFT_MCU_ROM_8814B) +#define BITS_MCU_ROM_8814B (BIT_MASK_MCU_ROM_8814B << BIT_SHIFT_MCU_ROM_8814B) +#define BIT_CLEAR_MCU_ROM_8814B(x) ((x) & (~BITS_MCU_ROM_8814B)) +#define BIT_GET_MCU_ROM_8814B(x) \ + (((x) >> BIT_SHIFT_MCU_ROM_8814B) & BIT_MASK_MCU_ROM_8814B) +#define BIT_SET_MCU_ROM_8814B(x, v) \ + (BIT_CLEAR_MCU_ROM_8814B(x) | BIT_MCU_ROM_8814B(v)) + +/* 2 REG_SYN_RFC_CTRL_8814B */ + +#define BIT_SHIFT_SYN_RF1_CTRL_8814B 8 +#define BIT_MASK_SYN_RF1_CTRL_8814B 0xff +#define BIT_SYN_RF1_CTRL_8814B(x) \ + (((x) & BIT_MASK_SYN_RF1_CTRL_8814B) << BIT_SHIFT_SYN_RF1_CTRL_8814B) +#define BITS_SYN_RF1_CTRL_8814B \ + (BIT_MASK_SYN_RF1_CTRL_8814B << BIT_SHIFT_SYN_RF1_CTRL_8814B) +#define BIT_CLEAR_SYN_RF1_CTRL_8814B(x) ((x) & (~BITS_SYN_RF1_CTRL_8814B)) +#define BIT_GET_SYN_RF1_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_SYN_RF1_CTRL_8814B) & BIT_MASK_SYN_RF1_CTRL_8814B) +#define BIT_SET_SYN_RF1_CTRL_8814B(x, v) \ + (BIT_CLEAR_SYN_RF1_CTRL_8814B(x) | BIT_SYN_RF1_CTRL_8814B(v)) + +#define BIT_SHIFT_SYN_RF0_CTRL_8814B 0 +#define BIT_MASK_SYN_RF0_CTRL_8814B 0xff +#define BIT_SYN_RF0_CTRL_8814B(x) \ + (((x) & BIT_MASK_SYN_RF0_CTRL_8814B) << BIT_SHIFT_SYN_RF0_CTRL_8814B) +#define BITS_SYN_RF0_CTRL_8814B \ + (BIT_MASK_SYN_RF0_CTRL_8814B << BIT_SHIFT_SYN_RF0_CTRL_8814B) +#define BIT_CLEAR_SYN_RF0_CTRL_8814B(x) ((x) & (~BITS_SYN_RF0_CTRL_8814B)) +#define BIT_GET_SYN_RF0_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_SYN_RF0_CTRL_8814B) & BIT_MASK_SYN_RF0_CTRL_8814B) +#define BIT_SET_SYN_RF0_CTRL_8814B(x, v) \ + (BIT_CLEAR_SYN_RF0_CTRL_8814B(x) | BIT_SYN_RF0_CTRL_8814B(v)) /* 2 REG_USB_SIE_INTF_8814B */ #define BIT_RD_SEL_8814B BIT(31) @@ -1597,68 +1952,160 @@ #define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B 16 #define BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B 0x1ff -#define BIT_USB_SIE_INTF_ADDR_V1_8814B(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) -#define BIT_GET_USB_SIE_INTF_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B) - - +#define BIT_USB_SIE_INTF_ADDR_V1_8814B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B) \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) +#define BITS_USB_SIE_INTF_ADDR_V1_8814B \ + (BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) +#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8814B(x) \ + ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8814B)) +#define BIT_GET_USB_SIE_INTF_ADDR_V1_8814B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) & \ + BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B) +#define BIT_SET_USB_SIE_INTF_ADDR_V1_8814B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8814B(x) | \ + BIT_USB_SIE_INTF_ADDR_V1_8814B(v)) #define BIT_SHIFT_USB_SIE_INTF_RD_8814B 8 #define BIT_MASK_USB_SIE_INTF_RD_8814B 0xff -#define BIT_USB_SIE_INTF_RD_8814B(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8814B) << BIT_SHIFT_USB_SIE_INTF_RD_8814B) -#define BIT_GET_USB_SIE_INTF_RD_8814B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8814B) & BIT_MASK_USB_SIE_INTF_RD_8814B) - - +#define BIT_USB_SIE_INTF_RD_8814B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_RD_8814B) \ + << BIT_SHIFT_USB_SIE_INTF_RD_8814B) +#define BITS_USB_SIE_INTF_RD_8814B \ + (BIT_MASK_USB_SIE_INTF_RD_8814B << BIT_SHIFT_USB_SIE_INTF_RD_8814B) +#define BIT_CLEAR_USB_SIE_INTF_RD_8814B(x) ((x) & (~BITS_USB_SIE_INTF_RD_8814B)) +#define BIT_GET_USB_SIE_INTF_RD_8814B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8814B) & \ + BIT_MASK_USB_SIE_INTF_RD_8814B) +#define BIT_SET_USB_SIE_INTF_RD_8814B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_RD_8814B(x) | BIT_USB_SIE_INTF_RD_8814B(v)) #define BIT_SHIFT_USB_SIE_INTF_WD_8814B 0 #define BIT_MASK_USB_SIE_INTF_WD_8814B 0xff -#define BIT_USB_SIE_INTF_WD_8814B(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8814B) << BIT_SHIFT_USB_SIE_INTF_WD_8814B) -#define BIT_GET_USB_SIE_INTF_WD_8814B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8814B) & BIT_MASK_USB_SIE_INTF_WD_8814B) +#define BIT_USB_SIE_INTF_WD_8814B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_WD_8814B) \ + << BIT_SHIFT_USB_SIE_INTF_WD_8814B) +#define BITS_USB_SIE_INTF_WD_8814B \ + (BIT_MASK_USB_SIE_INTF_WD_8814B << BIT_SHIFT_USB_SIE_INTF_WD_8814B) +#define BIT_CLEAR_USB_SIE_INTF_WD_8814B(x) ((x) & (~BITS_USB_SIE_INTF_WD_8814B)) +#define BIT_GET_USB_SIE_INTF_WD_8814B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8814B) & \ + BIT_MASK_USB_SIE_INTF_WD_8814B) +#define BIT_SET_USB_SIE_INTF_WD_8814B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_WD_8814B(x) | BIT_USB_SIE_INTF_WD_8814B(v)) +/* 2 REG_PCIE_MIO_INTF_8814B */ +#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B 16 +#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B 0x3 +#define BIT_PCIE_MIO_ADDR_PAGE_8814B(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B) \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B) +#define BITS_PCIE_MIO_ADDR_PAGE_8814B \ + (BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B) +#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8814B(x) \ + ((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8814B)) +#define BIT_GET_PCIE_MIO_ADDR_PAGE_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B) & \ + BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B) +#define BIT_SET_PCIE_MIO_ADDR_PAGE_8814B(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8814B(x) | \ + BIT_PCIE_MIO_ADDR_PAGE_8814B(v)) -/* 2 REG_PCIE_MIO_INTF_8814B */ #define BIT_PCIE_MIO_BYIOREG_8814B BIT(13) #define BIT_PCIE_MIO_RE_8814B BIT(12) #define BIT_SHIFT_PCIE_MIO_WE_8814B 8 #define BIT_MASK_PCIE_MIO_WE_8814B 0xf -#define BIT_PCIE_MIO_WE_8814B(x) (((x) & BIT_MASK_PCIE_MIO_WE_8814B) << BIT_SHIFT_PCIE_MIO_WE_8814B) -#define BIT_GET_PCIE_MIO_WE_8814B(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8814B) & BIT_MASK_PCIE_MIO_WE_8814B) - - +#define BIT_PCIE_MIO_WE_8814B(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE_8814B) << BIT_SHIFT_PCIE_MIO_WE_8814B) +#define BITS_PCIE_MIO_WE_8814B \ + (BIT_MASK_PCIE_MIO_WE_8814B << BIT_SHIFT_PCIE_MIO_WE_8814B) +#define BIT_CLEAR_PCIE_MIO_WE_8814B(x) ((x) & (~BITS_PCIE_MIO_WE_8814B)) +#define BIT_GET_PCIE_MIO_WE_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE_8814B) & BIT_MASK_PCIE_MIO_WE_8814B) +#define BIT_SET_PCIE_MIO_WE_8814B(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE_8814B(x) | BIT_PCIE_MIO_WE_8814B(v)) #define BIT_SHIFT_PCIE_MIO_ADDR_8814B 0 #define BIT_MASK_PCIE_MIO_ADDR_8814B 0xff -#define BIT_PCIE_MIO_ADDR_8814B(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8814B) << BIT_SHIFT_PCIE_MIO_ADDR_8814B) -#define BIT_GET_PCIE_MIO_ADDR_8814B(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8814B) & BIT_MASK_PCIE_MIO_ADDR_8814B) - - +#define BIT_PCIE_MIO_ADDR_8814B(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_8814B) << BIT_SHIFT_PCIE_MIO_ADDR_8814B) +#define BITS_PCIE_MIO_ADDR_8814B \ + (BIT_MASK_PCIE_MIO_ADDR_8814B << BIT_SHIFT_PCIE_MIO_ADDR_8814B) +#define BIT_CLEAR_PCIE_MIO_ADDR_8814B(x) ((x) & (~BITS_PCIE_MIO_ADDR_8814B)) +#define BIT_GET_PCIE_MIO_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8814B) & BIT_MASK_PCIE_MIO_ADDR_8814B) +#define BIT_SET_PCIE_MIO_ADDR_8814B(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_8814B(x) | BIT_PCIE_MIO_ADDR_8814B(v)) /* 2 REG_PCIE_MIO_INTD_8814B */ #define BIT_SHIFT_PCIE_MIO_DATA_8814B 0 #define BIT_MASK_PCIE_MIO_DATA_8814B 0xffffffffL -#define BIT_PCIE_MIO_DATA_8814B(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8814B) << BIT_SHIFT_PCIE_MIO_DATA_8814B) -#define BIT_GET_PCIE_MIO_DATA_8814B(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8814B) & BIT_MASK_PCIE_MIO_DATA_8814B) - - +#define BIT_PCIE_MIO_DATA_8814B(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA_8814B) << BIT_SHIFT_PCIE_MIO_DATA_8814B) +#define BITS_PCIE_MIO_DATA_8814B \ + (BIT_MASK_PCIE_MIO_DATA_8814B << BIT_SHIFT_PCIE_MIO_DATA_8814B) +#define BIT_CLEAR_PCIE_MIO_DATA_8814B(x) ((x) & (~BITS_PCIE_MIO_DATA_8814B)) +#define BIT_GET_PCIE_MIO_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8814B) & BIT_MASK_PCIE_MIO_DATA_8814B) +#define BIT_SET_PCIE_MIO_DATA_8814B(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA_8814B(x) | BIT_PCIE_MIO_DATA_8814B(v)) /* 2 REG_WLRF1_8814B */ #define BIT_SHIFT_WLRF1_CTRL_8814B 24 #define BIT_MASK_WLRF1_CTRL_8814B 0xff -#define BIT_WLRF1_CTRL_8814B(x) (((x) & BIT_MASK_WLRF1_CTRL_8814B) << BIT_SHIFT_WLRF1_CTRL_8814B) -#define BIT_GET_WLRF1_CTRL_8814B(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8814B) & BIT_MASK_WLRF1_CTRL_8814B) - - +#define BIT_WLRF1_CTRL_8814B(x) \ + (((x) & BIT_MASK_WLRF1_CTRL_8814B) << BIT_SHIFT_WLRF1_CTRL_8814B) +#define BITS_WLRF1_CTRL_8814B \ + (BIT_MASK_WLRF1_CTRL_8814B << BIT_SHIFT_WLRF1_CTRL_8814B) +#define BIT_CLEAR_WLRF1_CTRL_8814B(x) ((x) & (~BITS_WLRF1_CTRL_8814B)) +#define BIT_GET_WLRF1_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_WLRF1_CTRL_8814B) & BIT_MASK_WLRF1_CTRL_8814B) +#define BIT_SET_WLRF1_CTRL_8814B(x, v) \ + (BIT_CLEAR_WLRF1_CTRL_8814B(x) | BIT_WLRF1_CTRL_8814B(v)) + +#define BIT_SHIFT_WLRF2_CTRL_8814B 16 +#define BIT_MASK_WLRF2_CTRL_8814B 0xff +#define BIT_WLRF2_CTRL_8814B(x) \ + (((x) & BIT_MASK_WLRF2_CTRL_8814B) << BIT_SHIFT_WLRF2_CTRL_8814B) +#define BITS_WLRF2_CTRL_8814B \ + (BIT_MASK_WLRF2_CTRL_8814B << BIT_SHIFT_WLRF2_CTRL_8814B) +#define BIT_CLEAR_WLRF2_CTRL_8814B(x) ((x) & (~BITS_WLRF2_CTRL_8814B)) +#define BIT_GET_WLRF2_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_WLRF2_CTRL_8814B) & BIT_MASK_WLRF2_CTRL_8814B) +#define BIT_SET_WLRF2_CTRL_8814B(x, v) \ + (BIT_CLEAR_WLRF2_CTRL_8814B(x) | BIT_WLRF2_CTRL_8814B(v)) + +#define BIT_SHIFT_WLRF3_CTRL_8814B 8 +#define BIT_MASK_WLRF3_CTRL_8814B 0xff +#define BIT_WLRF3_CTRL_8814B(x) \ + (((x) & BIT_MASK_WLRF3_CTRL_8814B) << BIT_SHIFT_WLRF3_CTRL_8814B) +#define BITS_WLRF3_CTRL_8814B \ + (BIT_MASK_WLRF3_CTRL_8814B << BIT_SHIFT_WLRF3_CTRL_8814B) +#define BIT_CLEAR_WLRF3_CTRL_8814B(x) ((x) & (~BITS_WLRF3_CTRL_8814B)) +#define BIT_GET_WLRF3_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_WLRF3_CTRL_8814B) & BIT_MASK_WLRF3_CTRL_8814B) +#define BIT_SET_WLRF3_CTRL_8814B(x, v) \ + (BIT_CLEAR_WLRF3_CTRL_8814B(x) | BIT_WLRF3_CTRL_8814B(v)) /* 2 REG_SYS_CFG1_8814B */ #define BIT_SHIFT_TRP_ICFG_8814B 28 #define BIT_MASK_TRP_ICFG_8814B 0xf -#define BIT_TRP_ICFG_8814B(x) (((x) & BIT_MASK_TRP_ICFG_8814B) << BIT_SHIFT_TRP_ICFG_8814B) -#define BIT_GET_TRP_ICFG_8814B(x) (((x) >> BIT_SHIFT_TRP_ICFG_8814B) & BIT_MASK_TRP_ICFG_8814B) - +#define BIT_TRP_ICFG_8814B(x) \ + (((x) & BIT_MASK_TRP_ICFG_8814B) << BIT_SHIFT_TRP_ICFG_8814B) +#define BITS_TRP_ICFG_8814B \ + (BIT_MASK_TRP_ICFG_8814B << BIT_SHIFT_TRP_ICFG_8814B) +#define BIT_CLEAR_TRP_ICFG_8814B(x) ((x) & (~BITS_TRP_ICFG_8814B)) +#define BIT_GET_TRP_ICFG_8814B(x) \ + (((x) >> BIT_SHIFT_TRP_ICFG_8814B) & BIT_MASK_TRP_ICFG_8814B) +#define BIT_SET_TRP_ICFG_8814B(x, v) \ + (BIT_CLEAR_TRP_ICFG_8814B(x) | BIT_TRP_ICFG_8814B(v)) #define BIT_RF_TYPE_ID_8814B BIT(27) #define BIT_BD_HCI_SEL_8814B BIT(26) @@ -1670,16 +2117,27 @@ #define BIT_SHIFT_VENDOR_ID_8814B 16 #define BIT_MASK_VENDOR_ID_8814B 0xf -#define BIT_VENDOR_ID_8814B(x) (((x) & BIT_MASK_VENDOR_ID_8814B) << BIT_SHIFT_VENDOR_ID_8814B) -#define BIT_GET_VENDOR_ID_8814B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8814B) & BIT_MASK_VENDOR_ID_8814B) - - +#define BIT_VENDOR_ID_8814B(x) \ + (((x) & BIT_MASK_VENDOR_ID_8814B) << BIT_SHIFT_VENDOR_ID_8814B) +#define BITS_VENDOR_ID_8814B \ + (BIT_MASK_VENDOR_ID_8814B << BIT_SHIFT_VENDOR_ID_8814B) +#define BIT_CLEAR_VENDOR_ID_8814B(x) ((x) & (~BITS_VENDOR_ID_8814B)) +#define BIT_GET_VENDOR_ID_8814B(x) \ + (((x) >> BIT_SHIFT_VENDOR_ID_8814B) & BIT_MASK_VENDOR_ID_8814B) +#define BIT_SET_VENDOR_ID_8814B(x, v) \ + (BIT_CLEAR_VENDOR_ID_8814B(x) | BIT_VENDOR_ID_8814B(v)) #define BIT_SHIFT_CHIP_VER_8814B 12 #define BIT_MASK_CHIP_VER_8814B 0xf -#define BIT_CHIP_VER_8814B(x) (((x) & BIT_MASK_CHIP_VER_8814B) << BIT_SHIFT_CHIP_VER_8814B) -#define BIT_GET_CHIP_VER_8814B(x) (((x) >> BIT_SHIFT_CHIP_VER_8814B) & BIT_MASK_CHIP_VER_8814B) - +#define BIT_CHIP_VER_8814B(x) \ + (((x) & BIT_MASK_CHIP_VER_8814B) << BIT_SHIFT_CHIP_VER_8814B) +#define BITS_CHIP_VER_8814B \ + (BIT_MASK_CHIP_VER_8814B << BIT_SHIFT_CHIP_VER_8814B) +#define BIT_CLEAR_CHIP_VER_8814B(x) ((x) & (~BITS_CHIP_VER_8814B)) +#define BIT_GET_CHIP_VER_8814B(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_8814B) & BIT_MASK_CHIP_VER_8814B) +#define BIT_SET_CHIP_VER_8814B(x, v) \ + (BIT_CLEAR_CHIP_VER_8814B(x) | BIT_CHIP_VER_8814B(v)) #define BIT_BD_MAC3_8814B BIT(11) #define BIT_BD_MAC1_8814B BIT(10) @@ -1698,17 +2156,55 @@ #define BIT_SHIFT_RF_RL_ID_8814B 28 #define BIT_MASK_RF_RL_ID_8814B 0xf -#define BIT_RF_RL_ID_8814B(x) (((x) & BIT_MASK_RF_RL_ID_8814B) << BIT_SHIFT_RF_RL_ID_8814B) -#define BIT_GET_RF_RL_ID_8814B(x) (((x) >> BIT_SHIFT_RF_RL_ID_8814B) & BIT_MASK_RF_RL_ID_8814B) +#define BIT_RF_RL_ID_8814B(x) \ + (((x) & BIT_MASK_RF_RL_ID_8814B) << BIT_SHIFT_RF_RL_ID_8814B) +#define BITS_RF_RL_ID_8814B \ + (BIT_MASK_RF_RL_ID_8814B << BIT_SHIFT_RF_RL_ID_8814B) +#define BIT_CLEAR_RF_RL_ID_8814B(x) ((x) & (~BITS_RF_RL_ID_8814B)) +#define BIT_GET_RF_RL_ID_8814B(x) \ + (((x) >> BIT_SHIFT_RF_RL_ID_8814B) & BIT_MASK_RF_RL_ID_8814B) +#define BIT_SET_RF_RL_ID_8814B(x, v) \ + (BIT_CLEAR_RF_RL_ID_8814B(x) | BIT_RF_RL_ID_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_XTAL_SEL_8814B 25 +#define BIT_MASK_XTAL_SEL_8814B 0x3 +#define BIT_XTAL_SEL_8814B(x) \ + (((x) & BIT_MASK_XTAL_SEL_8814B) << BIT_SHIFT_XTAL_SEL_8814B) +#define BITS_XTAL_SEL_8814B \ + (BIT_MASK_XTAL_SEL_8814B << BIT_SHIFT_XTAL_SEL_8814B) +#define BIT_CLEAR_XTAL_SEL_8814B(x) ((x) & (~BITS_XTAL_SEL_8814B)) +#define BIT_GET_XTAL_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_8814B) & BIT_MASK_XTAL_SEL_8814B) +#define BIT_SET_XTAL_SEL_8814B(x, v) \ + (BIT_CLEAR_XTAL_SEL_8814B(x) | BIT_XTAL_SEL_8814B(v)) #define BIT_HPHY_ICFG_8814B BIT(19) #define BIT_SHIFT_SEL_0XC0_8814B 16 #define BIT_MASK_SEL_0XC0_8814B 0x3 -#define BIT_SEL_0XC0_8814B(x) (((x) & BIT_MASK_SEL_0XC0_8814B) << BIT_SHIFT_SEL_0XC0_8814B) -#define BIT_GET_SEL_0XC0_8814B(x) (((x) >> BIT_SHIFT_SEL_0XC0_8814B) & BIT_MASK_SEL_0XC0_8814B) - +#define BIT_SEL_0XC0_8814B(x) \ + (((x) & BIT_MASK_SEL_0XC0_8814B) << BIT_SHIFT_SEL_0XC0_8814B) +#define BITS_SEL_0XC0_8814B \ + (BIT_MASK_SEL_0XC0_8814B << BIT_SHIFT_SEL_0XC0_8814B) +#define BIT_CLEAR_SEL_0XC0_8814B(x) ((x) & (~BITS_SEL_0XC0_8814B)) +#define BIT_GET_SEL_0XC0_8814B(x) \ + (((x) >> BIT_SHIFT_SEL_0XC0_8814B) & BIT_MASK_SEL_0XC0_8814B) +#define BIT_SET_SEL_0XC0_8814B(x, v) \ + (BIT_CLEAR_SEL_0XC0_8814B(x) | BIT_SEL_0XC0_8814B(v)) + +#define BIT_SHIFT_HCI_SEL_V4_8814B 12 +#define BIT_MASK_HCI_SEL_V4_8814B 0x3 +#define BIT_HCI_SEL_V4_8814B(x) \ + (((x) & BIT_MASK_HCI_SEL_V4_8814B) << BIT_SHIFT_HCI_SEL_V4_8814B) +#define BITS_HCI_SEL_V4_8814B \ + (BIT_MASK_HCI_SEL_V4_8814B << BIT_SHIFT_HCI_SEL_V4_8814B) +#define BIT_CLEAR_HCI_SEL_V4_8814B(x) ((x) & (~BITS_HCI_SEL_V4_8814B)) +#define BIT_GET_HCI_SEL_V4_8814B(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V4_8814B) & BIT_MASK_HCI_SEL_V4_8814B) +#define BIT_SET_HCI_SEL_V4_8814B(x, v) \ + (BIT_CLEAR_HCI_SEL_V4_8814B(x) | BIT_HCI_SEL_V4_8814B(v)) #define BIT_USB_OPERATION_MODE_8814B BIT(10) #define BIT_BT_PDN_8814B BIT(9) @@ -1716,26 +2212,31 @@ #define BIT_WL_MODE_8814B BIT(7) #define BIT_PKG_SEL_HCI_8814B BIT(6) -#define BIT_SHIFT_HCI_SEL_8814B 4 -#define BIT_MASK_HCI_SEL_8814B 0x3 -#define BIT_HCI_SEL_8814B(x) (((x) & BIT_MASK_HCI_SEL_8814B) << BIT_SHIFT_HCI_SEL_8814B) -#define BIT_GET_HCI_SEL_8814B(x) (((x) >> BIT_SHIFT_HCI_SEL_8814B) & BIT_MASK_HCI_SEL_8814B) - - - -#define BIT_SHIFT_PAD_HCI_SEL_8814B 2 -#define BIT_MASK_PAD_HCI_SEL_8814B 0x3 -#define BIT_PAD_HCI_SEL_8814B(x) (((x) & BIT_MASK_PAD_HCI_SEL_8814B) << BIT_SHIFT_PAD_HCI_SEL_8814B) -#define BIT_GET_PAD_HCI_SEL_8814B(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_8814B) & BIT_MASK_PAD_HCI_SEL_8814B) - - +#define BIT_SHIFT_PAD_HCI_SEL_V2_8814B 3 +#define BIT_MASK_PAD_HCI_SEL_V2_8814B 0x3 +#define BIT_PAD_HCI_SEL_V2_8814B(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V2_8814B) \ + << BIT_SHIFT_PAD_HCI_SEL_V2_8814B) +#define BITS_PAD_HCI_SEL_V2_8814B \ + (BIT_MASK_PAD_HCI_SEL_V2_8814B << BIT_SHIFT_PAD_HCI_SEL_V2_8814B) +#define BIT_CLEAR_PAD_HCI_SEL_V2_8814B(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8814B)) +#define BIT_GET_PAD_HCI_SEL_V2_8814B(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8814B) & \ + BIT_MASK_PAD_HCI_SEL_V2_8814B) +#define BIT_SET_PAD_HCI_SEL_V2_8814B(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V2_8814B(x) | BIT_PAD_HCI_SEL_V2_8814B(v)) #define BIT_SHIFT_EFS_HCI_SEL_8814B 0 #define BIT_MASK_EFS_HCI_SEL_8814B 0x3 -#define BIT_EFS_HCI_SEL_8814B(x) (((x) & BIT_MASK_EFS_HCI_SEL_8814B) << BIT_SHIFT_EFS_HCI_SEL_8814B) -#define BIT_GET_EFS_HCI_SEL_8814B(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_8814B) & BIT_MASK_EFS_HCI_SEL_8814B) - - +#define BIT_EFS_HCI_SEL_8814B(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_8814B) << BIT_SHIFT_EFS_HCI_SEL_8814B) +#define BITS_EFS_HCI_SEL_8814B \ + (BIT_MASK_EFS_HCI_SEL_8814B << BIT_SHIFT_EFS_HCI_SEL_8814B) +#define BIT_CLEAR_EFS_HCI_SEL_8814B(x) ((x) & (~BITS_EFS_HCI_SEL_8814B)) +#define BIT_GET_EFS_HCI_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_8814B) & BIT_MASK_EFS_HCI_SEL_8814B) +#define BIT_SET_EFS_HCI_SEL_8814B(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_8814B(x) | BIT_EFS_HCI_SEL_8814B(v)) /* 2 REG_SYS_STATUS2_8814B */ #define BIT_SIO_ALDN_8814B BIT(19) @@ -1745,38 +2246,1214 @@ #define BIT_SHIFT_EPVID1_8814B 8 #define BIT_MASK_EPVID1_8814B 0xff -#define BIT_EPVID1_8814B(x) (((x) & BIT_MASK_EPVID1_8814B) << BIT_SHIFT_EPVID1_8814B) -#define BIT_GET_EPVID1_8814B(x) (((x) >> BIT_SHIFT_EPVID1_8814B) & BIT_MASK_EPVID1_8814B) - - +#define BIT_EPVID1_8814B(x) \ + (((x) & BIT_MASK_EPVID1_8814B) << BIT_SHIFT_EPVID1_8814B) +#define BITS_EPVID1_8814B (BIT_MASK_EPVID1_8814B << BIT_SHIFT_EPVID1_8814B) +#define BIT_CLEAR_EPVID1_8814B(x) ((x) & (~BITS_EPVID1_8814B)) +#define BIT_GET_EPVID1_8814B(x) \ + (((x) >> BIT_SHIFT_EPVID1_8814B) & BIT_MASK_EPVID1_8814B) +#define BIT_SET_EPVID1_8814B(x, v) \ + (BIT_CLEAR_EPVID1_8814B(x) | BIT_EPVID1_8814B(v)) #define BIT_SHIFT_EPVID0_8814B 0 #define BIT_MASK_EPVID0_8814B 0xff -#define BIT_EPVID0_8814B(x) (((x) & BIT_MASK_EPVID0_8814B) << BIT_SHIFT_EPVID0_8814B) -#define BIT_GET_EPVID0_8814B(x) (((x) >> BIT_SHIFT_EPVID0_8814B) & BIT_MASK_EPVID0_8814B) - - +#define BIT_EPVID0_8814B(x) \ + (((x) & BIT_MASK_EPVID0_8814B) << BIT_SHIFT_EPVID0_8814B) +#define BITS_EPVID0_8814B (BIT_MASK_EPVID0_8814B << BIT_SHIFT_EPVID0_8814B) +#define BIT_CLEAR_EPVID0_8814B(x) ((x) & (~BITS_EPVID0_8814B)) +#define BIT_GET_EPVID0_8814B(x) \ + (((x) >> BIT_SHIFT_EPVID0_8814B) & BIT_MASK_EPVID0_8814B) +#define BIT_SET_EPVID0_8814B(x, v) \ + (BIT_CLEAR_EPVID0_8814B(x) | BIT_EPVID0_8814B(v)) /* 2 REG_SYS_CFG2_8814B */ -#define BIT_HCI_SEL_EMBEDED_8814B BIT(8) +#define BIT_USB2_SEL_8814B BIT(31) +#define BIT_U3PHY_RST_V1_8814B BIT(30) +#define BIT_U3_TERM_DETECT_8814B BIT(29) #define BIT_SHIFT_HW_ID_8814B 0 #define BIT_MASK_HW_ID_8814B 0xff -#define BIT_HW_ID_8814B(x) (((x) & BIT_MASK_HW_ID_8814B) << BIT_SHIFT_HW_ID_8814B) -#define BIT_GET_HW_ID_8814B(x) (((x) >> BIT_SHIFT_HW_ID_8814B) & BIT_MASK_HW_ID_8814B) - +#define BIT_HW_ID_8814B(x) \ + (((x) & BIT_MASK_HW_ID_8814B) << BIT_SHIFT_HW_ID_8814B) +#define BITS_HW_ID_8814B (BIT_MASK_HW_ID_8814B << BIT_SHIFT_HW_ID_8814B) +#define BIT_CLEAR_HW_ID_8814B(x) ((x) & (~BITS_HW_ID_8814B)) +#define BIT_GET_HW_ID_8814B(x) \ + (((x) >> BIT_SHIFT_HW_ID_8814B) & BIT_MASK_HW_ID_8814B) +#define BIT_SET_HW_ID_8814B(x, v) \ + (BIT_CLEAR_HW_ID_8814B(x) | BIT_HW_ID_8814B(v)) - -/* 2 REG_SYS_CFG3_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_FEN_WLMAC_OFF_8814B BIT(31) #define BIT_PWC_MA33V_8814B BIT(15) #define BIT_PWC_MA12V_8814B BIT(14) #define BIT_PWC_MD12V_8814B BIT(13) #define BIT_PWC_PD12V_8814B BIT(12) #define BIT_PWC_UD12V_8814B BIT(11) +#define BIT_ISO_BB2PP_8814B BIT(7) +#define BIT_ISO_DENG2PP_8814B BIT(6) #define BIT_ISO_MA2MD_8814B BIT(1) #define BIT_ISO_MD2PP_8814B BIT(0) -/* 2 REG_SYS_CFG4_8814B */ +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_ANAPARSW_MAC_0_8814B */ +#define BIT_OCP_L_0_8814B BIT(31) +#define BIT_POWOCP_L_8814B BIT(30) + +#define BIT_SHIFT_CF_L_1_0_8814B 28 +#define BIT_MASK_CF_L_1_0_8814B 0x3 +#define BIT_CF_L_1_0_8814B(x) \ + (((x) & BIT_MASK_CF_L_1_0_8814B) << BIT_SHIFT_CF_L_1_0_8814B) +#define BITS_CF_L_1_0_8814B \ + (BIT_MASK_CF_L_1_0_8814B << BIT_SHIFT_CF_L_1_0_8814B) +#define BIT_CLEAR_CF_L_1_0_8814B(x) ((x) & (~BITS_CF_L_1_0_8814B)) +#define BIT_GET_CF_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_CF_L_1_0_8814B) & BIT_MASK_CF_L_1_0_8814B) +#define BIT_SET_CF_L_1_0_8814B(x, v) \ + (BIT_CLEAR_CF_L_1_0_8814B(x) | BIT_CF_L_1_0_8814B(v)) + +#define BIT_SHIFT_CFC_L_1_0_8814B 26 +#define BIT_MASK_CFC_L_1_0_8814B 0x3 +#define BIT_CFC_L_1_0_8814B(x) \ + (((x) & BIT_MASK_CFC_L_1_0_8814B) << BIT_SHIFT_CFC_L_1_0_8814B) +#define BITS_CFC_L_1_0_8814B \ + (BIT_MASK_CFC_L_1_0_8814B << BIT_SHIFT_CFC_L_1_0_8814B) +#define BIT_CLEAR_CFC_L_1_0_8814B(x) ((x) & (~BITS_CFC_L_1_0_8814B)) +#define BIT_GET_CFC_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_CFC_L_1_0_8814B) & BIT_MASK_CFC_L_1_0_8814B) +#define BIT_SET_CFC_L_1_0_8814B(x, v) \ + (BIT_CLEAR_CFC_L_1_0_8814B(x) | BIT_CFC_L_1_0_8814B(v)) + +#define BIT_SHIFT_R3_L_1_0_8814B 24 +#define BIT_MASK_R3_L_1_0_8814B 0x3 +#define BIT_R3_L_1_0_8814B(x) \ + (((x) & BIT_MASK_R3_L_1_0_8814B) << BIT_SHIFT_R3_L_1_0_8814B) +#define BITS_R3_L_1_0_8814B \ + (BIT_MASK_R3_L_1_0_8814B << BIT_SHIFT_R3_L_1_0_8814B) +#define BIT_CLEAR_R3_L_1_0_8814B(x) ((x) & (~BITS_R3_L_1_0_8814B)) +#define BIT_GET_R3_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_R3_L_1_0_8814B) & BIT_MASK_R3_L_1_0_8814B) +#define BIT_SET_R3_L_1_0_8814B(x, v) \ + (BIT_CLEAR_R3_L_1_0_8814B(x) | BIT_R3_L_1_0_8814B(v)) + +#define BIT_SHIFT_R2_L_1_0_8814B 22 +#define BIT_MASK_R2_L_1_0_8814B 0x3 +#define BIT_R2_L_1_0_8814B(x) \ + (((x) & BIT_MASK_R2_L_1_0_8814B) << BIT_SHIFT_R2_L_1_0_8814B) +#define BITS_R2_L_1_0_8814B \ + (BIT_MASK_R2_L_1_0_8814B << BIT_SHIFT_R2_L_1_0_8814B) +#define BIT_CLEAR_R2_L_1_0_8814B(x) ((x) & (~BITS_R2_L_1_0_8814B)) +#define BIT_GET_R2_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_R2_L_1_0_8814B) & BIT_MASK_R2_L_1_0_8814B) +#define BIT_SET_R2_L_1_0_8814B(x, v) \ + (BIT_CLEAR_R2_L_1_0_8814B(x) | BIT_R2_L_1_0_8814B(v)) + +#define BIT_SHIFT_R1_L_1_0_8814B 20 +#define BIT_MASK_R1_L_1_0_8814B 0x3 +#define BIT_R1_L_1_0_8814B(x) \ + (((x) & BIT_MASK_R1_L_1_0_8814B) << BIT_SHIFT_R1_L_1_0_8814B) +#define BITS_R1_L_1_0_8814B \ + (BIT_MASK_R1_L_1_0_8814B << BIT_SHIFT_R1_L_1_0_8814B) +#define BIT_CLEAR_R1_L_1_0_8814B(x) ((x) & (~BITS_R1_L_1_0_8814B)) +#define BIT_GET_R1_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_R1_L_1_0_8814B) & BIT_MASK_R1_L_1_0_8814B) +#define BIT_SET_R1_L_1_0_8814B(x, v) \ + (BIT_CLEAR_R1_L_1_0_8814B(x) | BIT_R1_L_1_0_8814B(v)) + +#define BIT_SHIFT_C3_L_1_0_8814B 18 +#define BIT_MASK_C3_L_1_0_8814B 0x3 +#define BIT_C3_L_1_0_8814B(x) \ + (((x) & BIT_MASK_C3_L_1_0_8814B) << BIT_SHIFT_C3_L_1_0_8814B) +#define BITS_C3_L_1_0_8814B \ + (BIT_MASK_C3_L_1_0_8814B << BIT_SHIFT_C3_L_1_0_8814B) +#define BIT_CLEAR_C3_L_1_0_8814B(x) ((x) & (~BITS_C3_L_1_0_8814B)) +#define BIT_GET_C3_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_C3_L_1_0_8814B) & BIT_MASK_C3_L_1_0_8814B) +#define BIT_SET_C3_L_1_0_8814B(x, v) \ + (BIT_CLEAR_C3_L_1_0_8814B(x) | BIT_C3_L_1_0_8814B(v)) + +#define BIT_SHIFT_C2_L_1_0_8814B 16 +#define BIT_MASK_C2_L_1_0_8814B 0x3 +#define BIT_C2_L_1_0_8814B(x) \ + (((x) & BIT_MASK_C2_L_1_0_8814B) << BIT_SHIFT_C2_L_1_0_8814B) +#define BITS_C2_L_1_0_8814B \ + (BIT_MASK_C2_L_1_0_8814B << BIT_SHIFT_C2_L_1_0_8814B) +#define BIT_CLEAR_C2_L_1_0_8814B(x) ((x) & (~BITS_C2_L_1_0_8814B)) +#define BIT_GET_C2_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_C2_L_1_0_8814B) & BIT_MASK_C2_L_1_0_8814B) +#define BIT_SET_C2_L_1_0_8814B(x, v) \ + (BIT_CLEAR_C2_L_1_0_8814B(x) | BIT_C2_L_1_0_8814B(v)) + +#define BIT_SHIFT_C1_L_1_0_8814B 14 +#define BIT_MASK_C1_L_1_0_8814B 0x3 +#define BIT_C1_L_1_0_8814B(x) \ + (((x) & BIT_MASK_C1_L_1_0_8814B) << BIT_SHIFT_C1_L_1_0_8814B) +#define BITS_C1_L_1_0_8814B \ + (BIT_MASK_C1_L_1_0_8814B << BIT_SHIFT_C1_L_1_0_8814B) +#define BIT_CLEAR_C1_L_1_0_8814B(x) ((x) & (~BITS_C1_L_1_0_8814B)) +#define BIT_GET_C1_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_C1_L_1_0_8814B) & BIT_MASK_C1_L_1_0_8814B) +#define BIT_SET_C1_L_1_0_8814B(x, v) \ + (BIT_CLEAR_C1_L_1_0_8814B(x) | BIT_C1_L_1_0_8814B(v)) + +#define BIT_REG_TYPE_L_V2_8814B BIT(13) +#define BIT_REG_PWM_L_8814B BIT(12) + +#define BIT_SHIFT_V15ADJ_L_2_0_8814B 9 +#define BIT_MASK_V15ADJ_L_2_0_8814B 0x7 +#define BIT_V15ADJ_L_2_0_8814B(x) \ + (((x) & BIT_MASK_V15ADJ_L_2_0_8814B) << BIT_SHIFT_V15ADJ_L_2_0_8814B) +#define BITS_V15ADJ_L_2_0_8814B \ + (BIT_MASK_V15ADJ_L_2_0_8814B << BIT_SHIFT_V15ADJ_L_2_0_8814B) +#define BIT_CLEAR_V15ADJ_L_2_0_8814B(x) ((x) & (~BITS_V15ADJ_L_2_0_8814B)) +#define BIT_GET_V15ADJ_L_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L_2_0_8814B) & BIT_MASK_V15ADJ_L_2_0_8814B) +#define BIT_SET_V15ADJ_L_2_0_8814B(x, v) \ + (BIT_CLEAR_V15ADJ_L_2_0_8814B(x) | BIT_V15ADJ_L_2_0_8814B(v)) + +#define BIT_SHIFT_IN_L_2_0_8814B 6 +#define BIT_MASK_IN_L_2_0_8814B 0x7 +#define BIT_IN_L_2_0_8814B(x) \ + (((x) & BIT_MASK_IN_L_2_0_8814B) << BIT_SHIFT_IN_L_2_0_8814B) +#define BITS_IN_L_2_0_8814B \ + (BIT_MASK_IN_L_2_0_8814B << BIT_SHIFT_IN_L_2_0_8814B) +#define BIT_CLEAR_IN_L_2_0_8814B(x) ((x) & (~BITS_IN_L_2_0_8814B)) +#define BIT_GET_IN_L_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_IN_L_2_0_8814B) & BIT_MASK_IN_L_2_0_8814B) +#define BIT_SET_IN_L_2_0_8814B(x, v) \ + (BIT_CLEAR_IN_L_2_0_8814B(x) | BIT_IN_L_2_0_8814B(v)) + +#define BIT_SHIFT_STD_L_1_0_8814B 4 +#define BIT_MASK_STD_L_1_0_8814B 0x3 +#define BIT_STD_L_1_0_8814B(x) \ + (((x) & BIT_MASK_STD_L_1_0_8814B) << BIT_SHIFT_STD_L_1_0_8814B) +#define BITS_STD_L_1_0_8814B \ + (BIT_MASK_STD_L_1_0_8814B << BIT_SHIFT_STD_L_1_0_8814B) +#define BIT_CLEAR_STD_L_1_0_8814B(x) ((x) & (~BITS_STD_L_1_0_8814B)) +#define BIT_GET_STD_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_STD_L_1_0_8814B) & BIT_MASK_STD_L_1_0_8814B) +#define BIT_SET_STD_L_1_0_8814B(x, v) \ + (BIT_CLEAR_STD_L_1_0_8814B(x) | BIT_STD_L_1_0_8814B(v)) + +#define BIT_SHIFT_VOL_L_3_0_8814B 0 +#define BIT_MASK_VOL_L_3_0_8814B 0xf +#define BIT_VOL_L_3_0_8814B(x) \ + (((x) & BIT_MASK_VOL_L_3_0_8814B) << BIT_SHIFT_VOL_L_3_0_8814B) +#define BITS_VOL_L_3_0_8814B \ + (BIT_MASK_VOL_L_3_0_8814B << BIT_SHIFT_VOL_L_3_0_8814B) +#define BIT_CLEAR_VOL_L_3_0_8814B(x) ((x) & (~BITS_VOL_L_3_0_8814B)) +#define BIT_GET_VOL_L_3_0_8814B(x) \ + (((x) >> BIT_SHIFT_VOL_L_3_0_8814B) & BIT_MASK_VOL_L_3_0_8814B) +#define BIT_SET_VOL_L_3_0_8814B(x, v) \ + (BIT_CLEAR_VOL_L_3_0_8814B(x) | BIT_VOL_L_3_0_8814B(v)) + +/* 2 REG_ANAPARSW_MAC_1_8814B */ + +#define BIT_SHIFT_REG_FREQ_L_V1_8814B 20 +#define BIT_MASK_REG_FREQ_L_V1_8814B 0x7 +#define BIT_REG_FREQ_L_V1_8814B(x) \ + (((x) & BIT_MASK_REG_FREQ_L_V1_8814B) << BIT_SHIFT_REG_FREQ_L_V1_8814B) +#define BITS_REG_FREQ_L_V1_8814B \ + (BIT_MASK_REG_FREQ_L_V1_8814B << BIT_SHIFT_REG_FREQ_L_V1_8814B) +#define BIT_CLEAR_REG_FREQ_L_V1_8814B(x) ((x) & (~BITS_REG_FREQ_L_V1_8814B)) +#define BIT_GET_REG_FREQ_L_V1_8814B(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_V1_8814B) & BIT_MASK_REG_FREQ_L_V1_8814B) +#define BIT_SET_REG_FREQ_L_V1_8814B(x, v) \ + (BIT_CLEAR_REG_FREQ_L_V1_8814B(x) | BIT_REG_FREQ_L_V1_8814B(v)) + +#define BIT_EN_DUTY_8814B BIT(19) + +#define BIT_SHIFT_REG_MOS_HALF_8814B 17 +#define BIT_MASK_REG_MOS_HALF_8814B 0x3 +#define BIT_REG_MOS_HALF_8814B(x) \ + (((x) & BIT_MASK_REG_MOS_HALF_8814B) << BIT_SHIFT_REG_MOS_HALF_8814B) +#define BITS_REG_MOS_HALF_8814B \ + (BIT_MASK_REG_MOS_HALF_8814B << BIT_SHIFT_REG_MOS_HALF_8814B) +#define BIT_CLEAR_REG_MOS_HALF_8814B(x) ((x) & (~BITS_REG_MOS_HALF_8814B)) +#define BIT_GET_REG_MOS_HALF_8814B(x) \ + (((x) >> BIT_SHIFT_REG_MOS_HALF_8814B) & BIT_MASK_REG_MOS_HALF_8814B) +#define BIT_SET_REG_MOS_HALF_8814B(x, v) \ + (BIT_CLEAR_REG_MOS_HALF_8814B(x) | BIT_REG_MOS_HALF_8814B(v)) + +#define BIT_EN_SP_8814B BIT(16) +#define BIT_REG_AUTO_L_V1_8814B BIT(15) +#define BIT_REG_LDOF_L_V2_8814B BIT(14) +#define BIT_REG_OCPS_L_V2_8814B BIT(13) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_ARENB_L_V1_8814B BIT(11) + +#define BIT_SHIFT_TBOX_L1_1_0_8814B 9 +#define BIT_MASK_TBOX_L1_1_0_8814B 0x3 +#define BIT_TBOX_L1_1_0_8814B(x) \ + (((x) & BIT_MASK_TBOX_L1_1_0_8814B) << BIT_SHIFT_TBOX_L1_1_0_8814B) +#define BITS_TBOX_L1_1_0_8814B \ + (BIT_MASK_TBOX_L1_1_0_8814B << BIT_SHIFT_TBOX_L1_1_0_8814B) +#define BIT_CLEAR_TBOX_L1_1_0_8814B(x) ((x) & (~BITS_TBOX_L1_1_0_8814B)) +#define BIT_GET_TBOX_L1_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_1_0_8814B) & BIT_MASK_TBOX_L1_1_0_8814B) +#define BIT_SET_TBOX_L1_1_0_8814B(x, v) \ + (BIT_CLEAR_TBOX_L1_1_0_8814B(x) | BIT_TBOX_L1_1_0_8814B(v)) + +#define BIT_SHIFT_REG_DELAY_L_1_0_8814B 7 +#define BIT_MASK_REG_DELAY_L_1_0_8814B 0x3 +#define BIT_REG_DELAY_L_1_0_8814B(x) \ + (((x) & BIT_MASK_REG_DELAY_L_1_0_8814B) \ + << BIT_SHIFT_REG_DELAY_L_1_0_8814B) +#define BITS_REG_DELAY_L_1_0_8814B \ + (BIT_MASK_REG_DELAY_L_1_0_8814B << BIT_SHIFT_REG_DELAY_L_1_0_8814B) +#define BIT_CLEAR_REG_DELAY_L_1_0_8814B(x) ((x) & (~BITS_REG_DELAY_L_1_0_8814B)) +#define BIT_GET_REG_DELAY_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_L_1_0_8814B) & \ + BIT_MASK_REG_DELAY_L_1_0_8814B) +#define BIT_SET_REG_DELAY_L_1_0_8814B(x, v) \ + (BIT_CLEAR_REG_DELAY_L_1_0_8814B(x) | BIT_REG_DELAY_L_1_0_8814B(v)) + +#define BIT_REG_CLAMP_D_L_8814B BIT(6) +#define BIT_REG_BYPASS_L_V1_8814B BIT(5) +#define BIT_REG_AUTOZCD_L_8814B BIT(4) +#define BIT_POW_ZCD_L_V1_8814B BIT(3) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_OCP_L_2_1_8814B 0 +#define BIT_MASK_OCP_L_2_1_8814B 0x3 +#define BIT_OCP_L_2_1_8814B(x) \ + (((x) & BIT_MASK_OCP_L_2_1_8814B) << BIT_SHIFT_OCP_L_2_1_8814B) +#define BITS_OCP_L_2_1_8814B \ + (BIT_MASK_OCP_L_2_1_8814B << BIT_SHIFT_OCP_L_2_1_8814B) +#define BIT_CLEAR_OCP_L_2_1_8814B(x) ((x) & (~BITS_OCP_L_2_1_8814B)) +#define BIT_GET_OCP_L_2_1_8814B(x) \ + (((x) >> BIT_SHIFT_OCP_L_2_1_8814B) & BIT_MASK_OCP_L_2_1_8814B) +#define BIT_SET_OCP_L_2_1_8814B(x, v) \ + (BIT_CLEAR_OCP_L_2_1_8814B(x) | BIT_OCP_L_2_1_8814B(v)) + +/* 2 REG_ANAPAR_MAC_0_8814B */ + +#define BIT_SHIFT_LPF_C2_1_0_8814B 30 +#define BIT_MASK_LPF_C2_1_0_8814B 0x3 +#define BIT_LPF_C2_1_0_8814B(x) \ + (((x) & BIT_MASK_LPF_C2_1_0_8814B) << BIT_SHIFT_LPF_C2_1_0_8814B) +#define BITS_LPF_C2_1_0_8814B \ + (BIT_MASK_LPF_C2_1_0_8814B << BIT_SHIFT_LPF_C2_1_0_8814B) +#define BIT_CLEAR_LPF_C2_1_0_8814B(x) ((x) & (~BITS_LPF_C2_1_0_8814B)) +#define BIT_GET_LPF_C2_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_C2_1_0_8814B) & BIT_MASK_LPF_C2_1_0_8814B) +#define BIT_SET_LPF_C2_1_0_8814B(x, v) \ + (BIT_CLEAR_LPF_C2_1_0_8814B(x) | BIT_LPF_C2_1_0_8814B(v)) + +#define BIT_SHIFT_LPF_C1_5_0_8814B 24 +#define BIT_MASK_LPF_C1_5_0_8814B 0x3f +#define BIT_LPF_C1_5_0_8814B(x) \ + (((x) & BIT_MASK_LPF_C1_5_0_8814B) << BIT_SHIFT_LPF_C1_5_0_8814B) +#define BITS_LPF_C1_5_0_8814B \ + (BIT_MASK_LPF_C1_5_0_8814B << BIT_SHIFT_LPF_C1_5_0_8814B) +#define BIT_CLEAR_LPF_C1_5_0_8814B(x) ((x) & (~BITS_LPF_C1_5_0_8814B)) +#define BIT_GET_LPF_C1_5_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_C1_5_0_8814B) & BIT_MASK_LPF_C1_5_0_8814B) +#define BIT_SET_LPF_C1_5_0_8814B(x, v) \ + (BIT_CLEAR_LPF_C1_5_0_8814B(x) | BIT_LPF_C1_5_0_8814B(v)) + +#define BIT_LPF_TIEL_8814B BIT(23) +#define BIT_LPF_TIEH_8814B BIT(22) + +#define BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B 20 +#define BIT_MASK_LOCKDET_VREF_L_1_0_8814B 0x3 +#define BIT_LOCKDET_VREF_L_1_0_8814B(x) \ + (((x) & BIT_MASK_LOCKDET_VREF_L_1_0_8814B) \ + << BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B) +#define BITS_LOCKDET_VREF_L_1_0_8814B \ + (BIT_MASK_LOCKDET_VREF_L_1_0_8814B \ + << BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B) +#define BIT_CLEAR_LOCKDET_VREF_L_1_0_8814B(x) \ + ((x) & (~BITS_LOCKDET_VREF_L_1_0_8814B)) +#define BIT_GET_LOCKDET_VREF_L_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B) & \ + BIT_MASK_LOCKDET_VREF_L_1_0_8814B) +#define BIT_SET_LOCKDET_VREF_L_1_0_8814B(x, v) \ + (BIT_CLEAR_LOCKDET_VREF_L_1_0_8814B(x) | \ + BIT_LOCKDET_VREF_L_1_0_8814B(v)) + +#define BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B 18 +#define BIT_MASK_LOCKDET_VREF_H_1_0_8814B 0x3 +#define BIT_LOCKDET_VREF_H_1_0_8814B(x) \ + (((x) & BIT_MASK_LOCKDET_VREF_H_1_0_8814B) \ + << BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B) +#define BITS_LOCKDET_VREF_H_1_0_8814B \ + (BIT_MASK_LOCKDET_VREF_H_1_0_8814B \ + << BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B) +#define BIT_CLEAR_LOCKDET_VREF_H_1_0_8814B(x) \ + ((x) & (~BITS_LOCKDET_VREF_H_1_0_8814B)) +#define BIT_GET_LOCKDET_VREF_H_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B) & \ + BIT_MASK_LOCKDET_VREF_H_1_0_8814B) +#define BIT_SET_LOCKDET_VREF_H_1_0_8814B(x, v) \ + (BIT_CLEAR_LOCKDET_VREF_H_1_0_8814B(x) | \ + BIT_LOCKDET_VREF_H_1_0_8814B(v)) + +#define BIT_SHIFT_LDO_SEL_1_0_8814B 16 +#define BIT_MASK_LDO_SEL_1_0_8814B 0x3 +#define BIT_LDO_SEL_1_0_8814B(x) \ + (((x) & BIT_MASK_LDO_SEL_1_0_8814B) << BIT_SHIFT_LDO_SEL_1_0_8814B) +#define BITS_LDO_SEL_1_0_8814B \ + (BIT_MASK_LDO_SEL_1_0_8814B << BIT_SHIFT_LDO_SEL_1_0_8814B) +#define BIT_CLEAR_LDO_SEL_1_0_8814B(x) ((x) & (~BITS_LDO_SEL_1_0_8814B)) +#define BIT_GET_LDO_SEL_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LDO_SEL_1_0_8814B) & BIT_MASK_LDO_SEL_1_0_8814B) +#define BIT_SET_LDO_SEL_1_0_8814B(x, v) \ + (BIT_CLEAR_LDO_SEL_1_0_8814B(x) | BIT_LDO_SEL_1_0_8814B(v)) + +#define BIT_SHIFT_IOFFSET_5_0_8814B 10 +#define BIT_MASK_IOFFSET_5_0_8814B 0x3f +#define BIT_IOFFSET_5_0_8814B(x) \ + (((x) & BIT_MASK_IOFFSET_5_0_8814B) << BIT_SHIFT_IOFFSET_5_0_8814B) +#define BITS_IOFFSET_5_0_8814B \ + (BIT_MASK_IOFFSET_5_0_8814B << BIT_SHIFT_IOFFSET_5_0_8814B) +#define BIT_CLEAR_IOFFSET_5_0_8814B(x) ((x) & (~BITS_IOFFSET_5_0_8814B)) +#define BIT_GET_IOFFSET_5_0_8814B(x) \ + (((x) >> BIT_SHIFT_IOFFSET_5_0_8814B) & BIT_MASK_IOFFSET_5_0_8814B) +#define BIT_SET_IOFFSET_5_0_8814B(x, v) \ + (BIT_CLEAR_IOFFSET_5_0_8814B(x) | BIT_IOFFSET_5_0_8814B(v)) + +#define BIT_CP_ICPX2_8814B BIT(9) + +#define BIT_SHIFT_CP_ICP_SEL_4_0_8814B 4 +#define BIT_MASK_CP_ICP_SEL_4_0_8814B 0x1f +#define BIT_CP_ICP_SEL_4_0_8814B(x) \ + (((x) & BIT_MASK_CP_ICP_SEL_4_0_8814B) \ + << BIT_SHIFT_CP_ICP_SEL_4_0_8814B) +#define BITS_CP_ICP_SEL_4_0_8814B \ + (BIT_MASK_CP_ICP_SEL_4_0_8814B << BIT_SHIFT_CP_ICP_SEL_4_0_8814B) +#define BIT_CLEAR_CP_ICP_SEL_4_0_8814B(x) ((x) & (~BITS_CP_ICP_SEL_4_0_8814B)) +#define BIT_GET_CP_ICP_SEL_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_CP_ICP_SEL_4_0_8814B) & \ + BIT_MASK_CP_ICP_SEL_4_0_8814B) +#define BIT_SET_CP_ICP_SEL_4_0_8814B(x, v) \ + (BIT_CLEAR_CP_ICP_SEL_4_0_8814B(x) | BIT_CP_ICP_SEL_4_0_8814B(v)) + +#define BIT_SHIFT_IB_PI_1_0_8814B 2 +#define BIT_MASK_IB_PI_1_0_8814B 0x3 +#define BIT_IB_PI_1_0_8814B(x) \ + (((x) & BIT_MASK_IB_PI_1_0_8814B) << BIT_SHIFT_IB_PI_1_0_8814B) +#define BITS_IB_PI_1_0_8814B \ + (BIT_MASK_IB_PI_1_0_8814B << BIT_SHIFT_IB_PI_1_0_8814B) +#define BIT_CLEAR_IB_PI_1_0_8814B(x) ((x) & (~BITS_IB_PI_1_0_8814B)) +#define BIT_GET_IB_PI_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_IB_PI_1_0_8814B) & BIT_MASK_IB_PI_1_0_8814B) +#define BIT_SET_IB_PI_1_0_8814B(x, v) \ + (BIT_CLEAR_IB_PI_1_0_8814B(x) | BIT_IB_PI_1_0_8814B(v)) + +#define BIT_SHIFT_LDO_VSEL_8814B 0 +#define BIT_MASK_LDO_VSEL_8814B 0x3 +#define BIT_LDO_VSEL_8814B(x) \ + (((x) & BIT_MASK_LDO_VSEL_8814B) << BIT_SHIFT_LDO_VSEL_8814B) +#define BITS_LDO_VSEL_8814B \ + (BIT_MASK_LDO_VSEL_8814B << BIT_SHIFT_LDO_VSEL_8814B) +#define BIT_CLEAR_LDO_VSEL_8814B(x) ((x) & (~BITS_LDO_VSEL_8814B)) +#define BIT_GET_LDO_VSEL_8814B(x) \ + (((x) >> BIT_SHIFT_LDO_VSEL_8814B) & BIT_MASK_LDO_VSEL_8814B) +#define BIT_SET_LDO_VSEL_8814B(x, v) \ + (BIT_CLEAR_LDO_VSEL_8814B(x) | BIT_LDO_VSEL_8814B(v)) + +/* 2 REG_ANAPAR_MAC_1_8814B */ + +#define BIT_SHIFT_CKX_USB_IB_SEL_8814B 29 +#define BIT_MASK_CKX_USB_IB_SEL_8814B 0x7 +#define BIT_CKX_USB_IB_SEL_8814B(x) \ + (((x) & BIT_MASK_CKX_USB_IB_SEL_8814B) \ + << BIT_SHIFT_CKX_USB_IB_SEL_8814B) +#define BITS_CKX_USB_IB_SEL_8814B \ + (BIT_MASK_CKX_USB_IB_SEL_8814B << BIT_SHIFT_CKX_USB_IB_SEL_8814B) +#define BIT_CLEAR_CKX_USB_IB_SEL_8814B(x) ((x) & (~BITS_CKX_USB_IB_SEL_8814B)) +#define BIT_GET_CKX_USB_IB_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_CKX_USB_IB_SEL_8814B) & \ + BIT_MASK_CKX_USB_IB_SEL_8814B) +#define BIT_SET_CKX_USB_IB_SEL_8814B(x, v) \ + (BIT_CLEAR_CKX_USB_IB_SEL_8814B(x) | BIT_CKX_USB_IB_SEL_8814B(v)) + +#define BIT_PFD_DN_GATED_8814B BIT(28) +#define BIT_PFD_UP_GATED_8814B BIT(27) +#define BIT_PFD_RESET_GATED_8814B BIT(26) + +#define BIT_SHIFT_PFD_OUT_DRV_1_0_8814B 24 +#define BIT_MASK_PFD_OUT_DRV_1_0_8814B 0x3 +#define BIT_PFD_OUT_DRV_1_0_8814B(x) \ + (((x) & BIT_MASK_PFD_OUT_DRV_1_0_8814B) \ + << BIT_SHIFT_PFD_OUT_DRV_1_0_8814B) +#define BITS_PFD_OUT_DRV_1_0_8814B \ + (BIT_MASK_PFD_OUT_DRV_1_0_8814B << BIT_SHIFT_PFD_OUT_DRV_1_0_8814B) +#define BIT_CLEAR_PFD_OUT_DRV_1_0_8814B(x) ((x) & (~BITS_PFD_OUT_DRV_1_0_8814B)) +#define BIT_GET_PFD_OUT_DRV_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_PFD_OUT_DRV_1_0_8814B) & \ + BIT_MASK_PFD_OUT_DRV_1_0_8814B) +#define BIT_SET_PFD_OUT_DRV_1_0_8814B(x, v) \ + (BIT_CLEAR_PFD_OUT_DRV_1_0_8814B(x) | BIT_PFD_OUT_DRV_1_0_8814B(v)) + +#define BIT_SHIFT_LPF_TIEMID_2_0_8814B 20 +#define BIT_MASK_LPF_TIEMID_2_0_8814B 0x7 +#define BIT_LPF_TIEMID_2_0_8814B(x) \ + (((x) & BIT_MASK_LPF_TIEMID_2_0_8814B) \ + << BIT_SHIFT_LPF_TIEMID_2_0_8814B) +#define BITS_LPF_TIEMID_2_0_8814B \ + (BIT_MASK_LPF_TIEMID_2_0_8814B << BIT_SHIFT_LPF_TIEMID_2_0_8814B) +#define BIT_CLEAR_LPF_TIEMID_2_0_8814B(x) ((x) & (~BITS_LPF_TIEMID_2_0_8814B)) +#define BIT_GET_LPF_TIEMID_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_TIEMID_2_0_8814B) & \ + BIT_MASK_LPF_TIEMID_2_0_8814B) +#define BIT_SET_LPF_TIEMID_2_0_8814B(x, v) \ + (BIT_CLEAR_LPF_TIEMID_2_0_8814B(x) | BIT_LPF_TIEMID_2_0_8814B(v)) + +#define BIT_SHIFT_LPF_R3_4_0_8814B 15 +#define BIT_MASK_LPF_R3_4_0_8814B 0x1f +#define BIT_LPF_R3_4_0_8814B(x) \ + (((x) & BIT_MASK_LPF_R3_4_0_8814B) << BIT_SHIFT_LPF_R3_4_0_8814B) +#define BITS_LPF_R3_4_0_8814B \ + (BIT_MASK_LPF_R3_4_0_8814B << BIT_SHIFT_LPF_R3_4_0_8814B) +#define BIT_CLEAR_LPF_R3_4_0_8814B(x) ((x) & (~BITS_LPF_R3_4_0_8814B)) +#define BIT_GET_LPF_R3_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_R3_4_0_8814B) & BIT_MASK_LPF_R3_4_0_8814B) +#define BIT_SET_LPF_R3_4_0_8814B(x, v) \ + (BIT_CLEAR_LPF_R3_4_0_8814B(x) | BIT_LPF_R3_4_0_8814B(v)) + +#define BIT_SHIFT_LPF_R2_4_0_8814B 10 +#define BIT_MASK_LPF_R2_4_0_8814B 0x1f +#define BIT_LPF_R2_4_0_8814B(x) \ + (((x) & BIT_MASK_LPF_R2_4_0_8814B) << BIT_SHIFT_LPF_R2_4_0_8814B) +#define BITS_LPF_R2_4_0_8814B \ + (BIT_MASK_LPF_R2_4_0_8814B << BIT_SHIFT_LPF_R2_4_0_8814B) +#define BIT_CLEAR_LPF_R2_4_0_8814B(x) ((x) & (~BITS_LPF_R2_4_0_8814B)) +#define BIT_GET_LPF_R2_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_R2_4_0_8814B) & BIT_MASK_LPF_R2_4_0_8814B) +#define BIT_SET_LPF_R2_4_0_8814B(x, v) \ + (BIT_CLEAR_LPF_R2_4_0_8814B(x) | BIT_LPF_R2_4_0_8814B(v)) + +#define BIT_SHIFT_LPF_C3_5_0_8814B 4 +#define BIT_MASK_LPF_C3_5_0_8814B 0x3f +#define BIT_LPF_C3_5_0_8814B(x) \ + (((x) & BIT_MASK_LPF_C3_5_0_8814B) << BIT_SHIFT_LPF_C3_5_0_8814B) +#define BITS_LPF_C3_5_0_8814B \ + (BIT_MASK_LPF_C3_5_0_8814B << BIT_SHIFT_LPF_C3_5_0_8814B) +#define BIT_CLEAR_LPF_C3_5_0_8814B(x) ((x) & (~BITS_LPF_C3_5_0_8814B)) +#define BIT_GET_LPF_C3_5_0_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_C3_5_0_8814B) & BIT_MASK_LPF_C3_5_0_8814B) +#define BIT_SET_LPF_C3_5_0_8814B(x, v) \ + (BIT_CLEAR_LPF_C3_5_0_8814B(x) | BIT_LPF_C3_5_0_8814B(v)) + +#define BIT_SHIFT_LPF_C2_5_2_8814B 0 +#define BIT_MASK_LPF_C2_5_2_8814B 0xf +#define BIT_LPF_C2_5_2_8814B(x) \ + (((x) & BIT_MASK_LPF_C2_5_2_8814B) << BIT_SHIFT_LPF_C2_5_2_8814B) +#define BITS_LPF_C2_5_2_8814B \ + (BIT_MASK_LPF_C2_5_2_8814B << BIT_SHIFT_LPF_C2_5_2_8814B) +#define BIT_CLEAR_LPF_C2_5_2_8814B(x) ((x) & (~BITS_LPF_C2_5_2_8814B)) +#define BIT_GET_LPF_C2_5_2_8814B(x) \ + (((x) >> BIT_SHIFT_LPF_C2_5_2_8814B) & BIT_MASK_LPF_C2_5_2_8814B) +#define BIT_SET_LPF_C2_5_2_8814B(x, v) \ + (BIT_CLEAR_LPF_C2_5_2_8814B(x) | BIT_LPF_C2_5_2_8814B(v)) + +/* 2 REG_ANAPAR_MAC_2_8814B */ +#define BIT_CK_PHASE_SEL_8814B BIT(31) +#define BIT_CK960M_EN_8814B BIT(30) +#define BIT_CK640M_EN_8814B BIT(29) +#define BIT_CK240M_EN_8814B BIT(28) + +#define BIT_SHIFT_CK_MON_SEL_2_0_8814B 25 +#define BIT_MASK_CK_MON_SEL_2_0_8814B 0x7 +#define BIT_CK_MON_SEL_2_0_8814B(x) \ + (((x) & BIT_MASK_CK_MON_SEL_2_0_8814B) \ + << BIT_SHIFT_CK_MON_SEL_2_0_8814B) +#define BITS_CK_MON_SEL_2_0_8814B \ + (BIT_MASK_CK_MON_SEL_2_0_8814B << BIT_SHIFT_CK_MON_SEL_2_0_8814B) +#define BIT_CLEAR_CK_MON_SEL_2_0_8814B(x) ((x) & (~BITS_CK_MON_SEL_2_0_8814B)) +#define BIT_GET_CK_MON_SEL_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_2_0_8814B) & \ + BIT_MASK_CK_MON_SEL_2_0_8814B) +#define BIT_SET_CK_MON_SEL_2_0_8814B(x, v) \ + (BIT_CLEAR_CK_MON_SEL_2_0_8814B(x) | BIT_CK_MON_SEL_2_0_8814B(v)) + +#define BIT_CK_MON_EN_V1_8814B BIT(24) +#define BIT_XTAL_SOURCE_SEL_8814B BIT(23) +#define BIT_XTAL_FREQ_SEL_8814B BIT(22) +#define BIT_XTAL_EDGE_SEL_8814B BIT(21) +#define BIT_XTAL_BUF_SEL_8814B BIT(20) + +#define BIT_SHIFT_VCO_CV_7_0_8814B 4 +#define BIT_MASK_VCO_CV_7_0_8814B 0xff +#define BIT_VCO_CV_7_0_8814B(x) \ + (((x) & BIT_MASK_VCO_CV_7_0_8814B) << BIT_SHIFT_VCO_CV_7_0_8814B) +#define BITS_VCO_CV_7_0_8814B \ + (BIT_MASK_VCO_CV_7_0_8814B << BIT_SHIFT_VCO_CV_7_0_8814B) +#define BIT_CLEAR_VCO_CV_7_0_8814B(x) ((x) & (~BITS_VCO_CV_7_0_8814B)) +#define BIT_GET_VCO_CV_7_0_8814B(x) \ + (((x) >> BIT_SHIFT_VCO_CV_7_0_8814B) & BIT_MASK_VCO_CV_7_0_8814B) +#define BIT_SET_VCO_CV_7_0_8814B(x, v) \ + (BIT_CLEAR_VCO_CV_7_0_8814B(x) | BIT_VCO_CV_7_0_8814B(v)) + +#define BIT_VCO_KVCO_8814B BIT(3) +#define BIT_SDM_EDGE_SEL_8814B BIT(2) +#define BIT_SDM_CK_SEL_8814B BIT(1) +#define BIT_SDM_CK_GATED_8814B BIT(0) + +/* 2 REG_ANAPAR_MAC_3_8814B */ + +#define BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B 28 +#define BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B 0x7 +#define BIT_LCK_WAIT_CYCLE_2_0_8814B(x) \ + (((x) & BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B) \ + << BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B) +#define BITS_LCK_WAIT_CYCLE_2_0_8814B \ + (BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B \ + << BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B) +#define BIT_CLEAR_LCK_WAIT_CYCLE_2_0_8814B(x) \ + ((x) & (~BITS_LCK_WAIT_CYCLE_2_0_8814B)) +#define BIT_GET_LCK_WAIT_CYCLE_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B) & \ + BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B) +#define BIT_SET_LCK_WAIT_CYCLE_2_0_8814B(x, v) \ + (BIT_CLEAR_LCK_WAIT_CYCLE_2_0_8814B(x) | \ + BIT_LCK_WAIT_CYCLE_2_0_8814B(v)) + +#define BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B 26 +#define BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B 0x3 +#define BIT_LCK_VCO_DIVISOR_1_0_8814B(x) \ + (((x) & BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B) \ + << BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B) +#define BITS_LCK_VCO_DIVISOR_1_0_8814B \ + (BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B \ + << BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B) +#define BIT_CLEAR_LCK_VCO_DIVISOR_1_0_8814B(x) \ + ((x) & (~BITS_LCK_VCO_DIVISOR_1_0_8814B)) +#define BIT_GET_LCK_VCO_DIVISOR_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B) & \ + BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B) +#define BIT_SET_LCK_VCO_DIVISOR_1_0_8814B(x, v) \ + (BIT_CLEAR_LCK_VCO_DIVISOR_1_0_8814B(x) | \ + BIT_LCK_VCO_DIVISOR_1_0_8814B(v)) + +#define BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B 24 +#define BIT_MASK_LCK_SEARCH_MODE_1_0_8814B 0x3 +#define BIT_LCK_SEARCH_MODE_1_0_8814B(x) \ + (((x) & BIT_MASK_LCK_SEARCH_MODE_1_0_8814B) \ + << BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B) +#define BITS_LCK_SEARCH_MODE_1_0_8814B \ + (BIT_MASK_LCK_SEARCH_MODE_1_0_8814B \ + << BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B) +#define BIT_CLEAR_LCK_SEARCH_MODE_1_0_8814B(x) \ + ((x) & (~BITS_LCK_SEARCH_MODE_1_0_8814B)) +#define BIT_GET_LCK_SEARCH_MODE_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B) & \ + BIT_MASK_LCK_SEARCH_MODE_1_0_8814B) +#define BIT_SET_LCK_SEARCH_MODE_1_0_8814B(x, v) \ + (BIT_CLEAR_LCK_SEARCH_MODE_1_0_8814B(x) | \ + BIT_LCK_SEARCH_MODE_1_0_8814B(v)) + +#define BIT_SHIFT_LS_CV_OFFSET_3_0_8814B 12 +#define BIT_MASK_LS_CV_OFFSET_3_0_8814B 0xf +#define BIT_LS_CV_OFFSET_3_0_8814B(x) \ + (((x) & BIT_MASK_LS_CV_OFFSET_3_0_8814B) \ + << BIT_SHIFT_LS_CV_OFFSET_3_0_8814B) +#define BITS_LS_CV_OFFSET_3_0_8814B \ + (BIT_MASK_LS_CV_OFFSET_3_0_8814B << BIT_SHIFT_LS_CV_OFFSET_3_0_8814B) +#define BIT_CLEAR_LS_CV_OFFSET_3_0_8814B(x) \ + ((x) & (~BITS_LS_CV_OFFSET_3_0_8814B)) +#define BIT_GET_LS_CV_OFFSET_3_0_8814B(x) \ + (((x) >> BIT_SHIFT_LS_CV_OFFSET_3_0_8814B) & \ + BIT_MASK_LS_CV_OFFSET_3_0_8814B) +#define BIT_SET_LS_CV_OFFSET_3_0_8814B(x, v) \ + (BIT_CLEAR_LS_CV_OFFSET_3_0_8814B(x) | BIT_LS_CV_OFFSET_3_0_8814B(v)) + +#define BIT_LS_EN_LC_CK40M_8814B BIT(11) +#define BIT_LS__CV_MANUAL_8814B BIT(10) +#define BIT_LS_PYPASS_PI_8814B BIT(9) +#define BIT_MBIASE_8814B BIT(4) + +/* 2 REG_ANAPAR_MAC_4_8814B */ +#define BIT_LS_TIE_MID_MODE_8814B BIT(28) + +#define BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B 26 +#define BIT_MASK_LS_SYNC_CYCLE_1_0_8814B 0x3 +#define BIT_LS_SYNC_CYCLE_1_0_8814B(x) \ + (((x) & BIT_MASK_LS_SYNC_CYCLE_1_0_8814B) \ + << BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B) +#define BITS_LS_SYNC_CYCLE_1_0_8814B \ + (BIT_MASK_LS_SYNC_CYCLE_1_0_8814B << BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B) +#define BIT_CLEAR_LS_SYNC_CYCLE_1_0_8814B(x) \ + ((x) & (~BITS_LS_SYNC_CYCLE_1_0_8814B)) +#define BIT_GET_LS_SYNC_CYCLE_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B) & \ + BIT_MASK_LS_SYNC_CYCLE_1_0_8814B) +#define BIT_SET_LS_SYNC_CYCLE_1_0_8814B(x, v) \ + (BIT_CLEAR_LS_SYNC_CYCLE_1_0_8814B(x) | BIT_LS_SYNC_CYCLE_1_0_8814B(v)) + +#define BIT_LS_SDM_ORDER_8814B BIT(25) +#define BIT_LS_RST_LC_CAL_8814B BIT(14) +#define BIT_LS_RSTB_8814B BIT(13) +#define BIT_LS_POW_LC_CAL_PREP_8814B BIT(11) + +#define BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B 0 +#define BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B 0x3 +#define BIT_LCK_XTAL_DIVISOR_1_0_8814B(x) \ + (((x) & BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B) \ + << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B) +#define BITS_LCK_XTAL_DIVISOR_1_0_8814B \ + (BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B \ + << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B) +#define BIT_CLEAR_LCK_XTAL_DIVISOR_1_0_8814B(x) \ + ((x) & (~BITS_LCK_XTAL_DIVISOR_1_0_8814B)) +#define BIT_GET_LCK_XTAL_DIVISOR_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B) & \ + BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B) +#define BIT_SET_LCK_XTAL_DIVISOR_1_0_8814B(x, v) \ + (BIT_CLEAR_LCK_XTAL_DIVISOR_1_0_8814B(x) | \ + BIT_LCK_XTAL_DIVISOR_1_0_8814B(v)) + +/* 2 REG_ANAPAR_MAC_5_8814B */ + +#define BIT_SHIFT_LS_XTAL_SEL_3_0_8814B 0 +#define BIT_MASK_LS_XTAL_SEL_3_0_8814B 0xf +#define BIT_LS_XTAL_SEL_3_0_8814B(x) \ + (((x) & BIT_MASK_LS_XTAL_SEL_3_0_8814B) \ + << BIT_SHIFT_LS_XTAL_SEL_3_0_8814B) +#define BITS_LS_XTAL_SEL_3_0_8814B \ + (BIT_MASK_LS_XTAL_SEL_3_0_8814B << BIT_SHIFT_LS_XTAL_SEL_3_0_8814B) +#define BIT_CLEAR_LS_XTAL_SEL_3_0_8814B(x) ((x) & (~BITS_LS_XTAL_SEL_3_0_8814B)) +#define BIT_GET_LS_XTAL_SEL_3_0_8814B(x) \ + (((x) >> BIT_SHIFT_LS_XTAL_SEL_3_0_8814B) & \ + BIT_MASK_LS_XTAL_SEL_3_0_8814B) +#define BIT_SET_LS_XTAL_SEL_3_0_8814B(x, v) \ + (BIT_CLEAR_LS_XTAL_SEL_3_0_8814B(x) | BIT_LS_XTAL_SEL_3_0_8814B(v)) + +/* 2 REG_ANAPAR_MAC_6_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_ANAPAR_MAC_7_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_ANAPAR_MAC_8_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_ANAPAR_XTAL_0_8814B */ +#define BIT_XTAL_DRV_RF1_0_8814B BIT(31) +#define BIT_XTAL_GATED_RF1N_8814B BIT(30) +#define BIT_XTAL_GATED_RF1P_8814B BIT(29) +#define BIT_XTAL_GM_SEP_V2_8814B BIT(28) + +#define BIT_SHIFT_XTAL_LDO_1_0_8814B 26 +#define BIT_MASK_XTAL_LDO_1_0_8814B 0x3 +#define BIT_XTAL_LDO_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_LDO_1_0_8814B) << BIT_SHIFT_XTAL_LDO_1_0_8814B) +#define BITS_XTAL_LDO_1_0_8814B \ + (BIT_MASK_XTAL_LDO_1_0_8814B << BIT_SHIFT_XTAL_LDO_1_0_8814B) +#define BIT_CLEAR_XTAL_LDO_1_0_8814B(x) ((x) & (~BITS_XTAL_LDO_1_0_8814B)) +#define BIT_GET_XTAL_LDO_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_1_0_8814B) & BIT_MASK_XTAL_LDO_1_0_8814B) +#define BIT_SET_XTAL_LDO_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_LDO_1_0_8814B(x) | BIT_XTAL_LDO_1_0_8814B(v)) + +#define BIT_XQSEL_V1_8814B BIT(25) +#define BIT_GATED_XTAL_OK0_8814B BIT(24) + +#define BIT_SHIFT_XTAL_SC_XO_6_0_8814B 17 +#define BIT_MASK_XTAL_SC_XO_6_0_8814B 0x7f +#define BIT_XTAL_SC_XO_6_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_SC_XO_6_0_8814B) \ + << BIT_SHIFT_XTAL_SC_XO_6_0_8814B) +#define BITS_XTAL_SC_XO_6_0_8814B \ + (BIT_MASK_XTAL_SC_XO_6_0_8814B << BIT_SHIFT_XTAL_SC_XO_6_0_8814B) +#define BIT_CLEAR_XTAL_SC_XO_6_0_8814B(x) ((x) & (~BITS_XTAL_SC_XO_6_0_8814B)) +#define BIT_GET_XTAL_SC_XO_6_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XO_6_0_8814B) & \ + BIT_MASK_XTAL_SC_XO_6_0_8814B) +#define BIT_SET_XTAL_SC_XO_6_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_SC_XO_6_0_8814B(x) | BIT_XTAL_SC_XO_6_0_8814B(v)) + +#define BIT_SHIFT_XTAL_SC_XI_6_0_8814B 10 +#define BIT_MASK_XTAL_SC_XI_6_0_8814B 0x7f +#define BIT_XTAL_SC_XI_6_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_SC_XI_6_0_8814B) \ + << BIT_SHIFT_XTAL_SC_XI_6_0_8814B) +#define BITS_XTAL_SC_XI_6_0_8814B \ + (BIT_MASK_XTAL_SC_XI_6_0_8814B << BIT_SHIFT_XTAL_SC_XI_6_0_8814B) +#define BIT_CLEAR_XTAL_SC_XI_6_0_8814B(x) ((x) & (~BITS_XTAL_SC_XI_6_0_8814B)) +#define BIT_GET_XTAL_SC_XI_6_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XI_6_0_8814B) & \ + BIT_MASK_XTAL_SC_XI_6_0_8814B) +#define BIT_SET_XTAL_SC_XI_6_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_SC_XI_6_0_8814B(x) | BIT_XTAL_SC_XI_6_0_8814B(v)) + +#define BIT_SHIFT_XTAL_GMN_4_0_8814B 5 +#define BIT_MASK_XTAL_GMN_4_0_8814B 0x1f +#define BIT_XTAL_GMN_4_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_GMN_4_0_8814B) << BIT_SHIFT_XTAL_GMN_4_0_8814B) +#define BITS_XTAL_GMN_4_0_8814B \ + (BIT_MASK_XTAL_GMN_4_0_8814B << BIT_SHIFT_XTAL_GMN_4_0_8814B) +#define BIT_CLEAR_XTAL_GMN_4_0_8814B(x) ((x) & (~BITS_XTAL_GMN_4_0_8814B)) +#define BIT_GET_XTAL_GMN_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_4_0_8814B) & BIT_MASK_XTAL_GMN_4_0_8814B) +#define BIT_SET_XTAL_GMN_4_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_GMN_4_0_8814B(x) | BIT_XTAL_GMN_4_0_8814B(v)) + +#define BIT_SHIFT_XTAL_GMP_4_0_8814B 0 +#define BIT_MASK_XTAL_GMP_4_0_8814B 0x1f +#define BIT_XTAL_GMP_4_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_GMP_4_0_8814B) << BIT_SHIFT_XTAL_GMP_4_0_8814B) +#define BITS_XTAL_GMP_4_0_8814B \ + (BIT_MASK_XTAL_GMP_4_0_8814B << BIT_SHIFT_XTAL_GMP_4_0_8814B) +#define BIT_CLEAR_XTAL_GMP_4_0_8814B(x) ((x) & (~BITS_XTAL_GMP_4_0_8814B)) +#define BIT_GET_XTAL_GMP_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_4_0_8814B) & BIT_MASK_XTAL_GMP_4_0_8814B) +#define BIT_SET_XTAL_GMP_4_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_GMP_4_0_8814B(x) | BIT_XTAL_GMP_4_0_8814B(v)) + +/* 2 REG_ANAPAR_XTAL_1_8814B */ + +#define BIT_SHIFT_XTAL_LDO_OK_1_0_8814B 30 +#define BIT_MASK_XTAL_LDO_OK_1_0_8814B 0x3 +#define BIT_XTAL_LDO_OK_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_LDO_OK_1_0_8814B) \ + << BIT_SHIFT_XTAL_LDO_OK_1_0_8814B) +#define BITS_XTAL_LDO_OK_1_0_8814B \ + (BIT_MASK_XTAL_LDO_OK_1_0_8814B << BIT_SHIFT_XTAL_LDO_OK_1_0_8814B) +#define BIT_CLEAR_XTAL_LDO_OK_1_0_8814B(x) ((x) & (~BITS_XTAL_LDO_OK_1_0_8814B)) +#define BIT_GET_XTAL_LDO_OK_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_OK_1_0_8814B) & \ + BIT_MASK_XTAL_LDO_OK_1_0_8814B) +#define BIT_SET_XTAL_LDO_OK_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_LDO_OK_1_0_8814B(x) | BIT_XTAL_LDO_OK_1_0_8814B(v)) + +#define BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B 27 +#define BIT_MASK_XTAL_XORES_SEL_2_0_8814B 0x7 +#define BIT_XTAL_XORES_SEL_2_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_XORES_SEL_2_0_8814B) \ + << BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B) +#define BITS_XTAL_XORES_SEL_2_0_8814B \ + (BIT_MASK_XTAL_XORES_SEL_2_0_8814B \ + << BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B) +#define BIT_CLEAR_XTAL_XORES_SEL_2_0_8814B(x) \ + ((x) & (~BITS_XTAL_XORES_SEL_2_0_8814B)) +#define BIT_GET_XTAL_XORES_SEL_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B) & \ + BIT_MASK_XTAL_XORES_SEL_2_0_8814B) +#define BIT_SET_XTAL_XORES_SEL_2_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_XORES_SEL_2_0_8814B(x) | \ + BIT_XTAL_XORES_SEL_2_0_8814B(v)) + +#define BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B 25 +#define BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B 0x3 +#define BIT_XTAL_AAC_PK_SEL_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B) \ + << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B) +#define BITS_XTAL_AAC_PK_SEL_1_0_8814B \ + (BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B \ + << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B) +#define BIT_CLEAR_XTAL_AAC_PK_SEL_1_0_8814B(x) \ + ((x) & (~BITS_XTAL_AAC_PK_SEL_1_0_8814B)) +#define BIT_GET_XTAL_AAC_PK_SEL_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B) & \ + BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B) +#define BIT_SET_XTAL_AAC_PK_SEL_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_AAC_PK_SEL_1_0_8814B(x) | \ + BIT_XTAL_AAC_PK_SEL_1_0_8814B(v)) + +#define BIT_EN_XTAL_AAC_PKDET_8814B BIT(24) +#define BIT_EN_XTAL_AAC_GM_8814B BIT(23) +#define BIT_XTAL_LPMODE_8814B BIT(22) + +#define BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B 19 +#define BIT_MASK_XTAL_SEL_TOK_2_0_8814B 0x7 +#define BIT_XTAL_SEL_TOK_2_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_2_0_8814B) \ + << BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B) +#define BITS_XTAL_SEL_TOK_2_0_8814B \ + (BIT_MASK_XTAL_SEL_TOK_2_0_8814B << BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B) +#define BIT_CLEAR_XTAL_SEL_TOK_2_0_8814B(x) \ + ((x) & (~BITS_XTAL_SEL_TOK_2_0_8814B)) +#define BIT_GET_XTAL_SEL_TOK_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B) & \ + BIT_MASK_XTAL_SEL_TOK_2_0_8814B) +#define BIT_SET_XTAL_SEL_TOK_2_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_2_0_8814B(x) | BIT_XTAL_SEL_TOK_2_0_8814B(v)) + +#define BIT_XQSEL_RF_AWAKE_V2_8814B BIT(18) +#define BIT_XQSEL_RF_INITIAL_V2_8814B BIT(17) +#define BIT_XTAL_DELAY_USB_V1_8814B BIT(16) +#define BIT_XTAL_DELAY_DIGI_V1_8814B BIT(15) +#define BIT_XTAL_DELAY_AFE_V1_8814B BIT(14) +#define BIT_XTAL_DRV_RF_LATCH_V3_8814B BIT(13) + +#define BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B 11 +#define BIT_MASK_XTAL_DRV_DIGI_1_0_8814B 0x3 +#define BIT_XTAL_DRV_DIGI_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_1_0_8814B) \ + << BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B) +#define BITS_XTAL_DRV_DIGI_1_0_8814B \ + (BIT_MASK_XTAL_DRV_DIGI_1_0_8814B << BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B) +#define BIT_CLEAR_XTAL_DRV_DIGI_1_0_8814B(x) \ + ((x) & (~BITS_XTAL_DRV_DIGI_1_0_8814B)) +#define BIT_GET_XTAL_DRV_DIGI_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B) & \ + BIT_MASK_XTAL_DRV_DIGI_1_0_8814B) +#define BIT_SET_XTAL_DRV_DIGI_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_1_0_8814B(x) | BIT_XTAL_DRV_DIGI_1_0_8814B(v)) + +#define BIT_XTAL_GATED_DIGIN_8814B BIT(10) +#define BIT_XTAL_GATED_DIGIP_8814B BIT(9) + +#define BIT_SHIFT_XTAL_DRV_USB_1_0_8814B 7 +#define BIT_MASK_XTAL_DRV_USB_1_0_8814B 0x3 +#define BIT_XTAL_DRV_USB_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_DRV_USB_1_0_8814B) \ + << BIT_SHIFT_XTAL_DRV_USB_1_0_8814B) +#define BITS_XTAL_DRV_USB_1_0_8814B \ + (BIT_MASK_XTAL_DRV_USB_1_0_8814B << BIT_SHIFT_XTAL_DRV_USB_1_0_8814B) +#define BIT_CLEAR_XTAL_DRV_USB_1_0_8814B(x) \ + ((x) & (~BITS_XTAL_DRV_USB_1_0_8814B)) +#define BIT_GET_XTAL_DRV_USB_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_USB_1_0_8814B) & \ + BIT_MASK_XTAL_DRV_USB_1_0_8814B) +#define BIT_SET_XTAL_DRV_USB_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_DRV_USB_1_0_8814B(x) | BIT_XTAL_DRV_USB_1_0_8814B(v)) + +#define BIT_XTAL_GATED_USBN_8814B BIT(6) +#define BIT_XTAL_GATED_USBP_8814B BIT(5) + +#define BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B 3 +#define BIT_MASK_XTAL_DRV_AFE_1_0_8814B 0x3 +#define BIT_XTAL_DRV_AFE_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_1_0_8814B) \ + << BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B) +#define BITS_XTAL_DRV_AFE_1_0_8814B \ + (BIT_MASK_XTAL_DRV_AFE_1_0_8814B << BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B) +#define BIT_CLEAR_XTAL_DRV_AFE_1_0_8814B(x) \ + ((x) & (~BITS_XTAL_DRV_AFE_1_0_8814B)) +#define BIT_GET_XTAL_DRV_AFE_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B) & \ + BIT_MASK_XTAL_DRV_AFE_1_0_8814B) +#define BIT_SET_XTAL_DRV_AFE_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_1_0_8814B(x) | BIT_XTAL_DRV_AFE_1_0_8814B(v)) + +#define BIT_XTAL_GATED_AFEN_8814B BIT(2) +#define BIT_XTAL_GATED_AFEP_8814B BIT(1) +#define BIT_XTAL_DRV_RF1_1_8814B BIT(0) + +/* 2 REG_ANAPAR_XTAL_2_8814B */ +#define BIT_XTAL_DRV_RF2_LATCH_8814B BIT(6) + +#define BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B 4 +#define BIT_MASK_XTAL_DRV_RF2_1_0_8814B 0x3 +#define BIT_XTAL_DRV_RF2_1_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_1_0_8814B) \ + << BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B) +#define BITS_XTAL_DRV_RF2_1_0_8814B \ + (BIT_MASK_XTAL_DRV_RF2_1_0_8814B << BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B) +#define BIT_CLEAR_XTAL_DRV_RF2_1_0_8814B(x) \ + ((x) & (~BITS_XTAL_DRV_RF2_1_0_8814B)) +#define BIT_GET_XTAL_DRV_RF2_1_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B) & \ + BIT_MASK_XTAL_DRV_RF2_1_0_8814B) +#define BIT_SET_XTAL_DRV_RF2_1_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_1_0_8814B(x) | BIT_XTAL_DRV_RF2_1_0_8814B(v)) + +#define BIT_XTAL_GATED_RF2N_8814B BIT(3) +#define BIT_XTAL_GATED_RF2P_8814B BIT(2) +#define BIT_XTAL_LDO_DI_8814B BIT(1) +#define BIT_XTAL_SEL_PWR_8814B BIT(0) + +/* 2 REG_ANAPAR_XTAL_AAC_8814B */ +#define BIT_EN_XTAL_AAC_TRIG_8814B BIT(28) +#define BIT_EN_XTAL_AAC_8814B BIT(27) +#define BIT_EN_XTAL_AAC_DIGI_8814B BIT(26) + +#define BIT_SHIFT_GM_MANUAL_4_0_8814B 21 +#define BIT_MASK_GM_MANUAL_4_0_8814B 0x1f +#define BIT_GM_MANUAL_4_0_8814B(x) \ + (((x) & BIT_MASK_GM_MANUAL_4_0_8814B) << BIT_SHIFT_GM_MANUAL_4_0_8814B) +#define BITS_GM_MANUAL_4_0_8814B \ + (BIT_MASK_GM_MANUAL_4_0_8814B << BIT_SHIFT_GM_MANUAL_4_0_8814B) +#define BIT_CLEAR_GM_MANUAL_4_0_8814B(x) ((x) & (~BITS_GM_MANUAL_4_0_8814B)) +#define BIT_GET_GM_MANUAL_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_GM_MANUAL_4_0_8814B) & BIT_MASK_GM_MANUAL_4_0_8814B) +#define BIT_SET_GM_MANUAL_4_0_8814B(x, v) \ + (BIT_CLEAR_GM_MANUAL_4_0_8814B(x) | BIT_GM_MANUAL_4_0_8814B(v)) + +#define BIT_SHIFT_GM_STUP_4_0_8814B 16 +#define BIT_MASK_GM_STUP_4_0_8814B 0x1f +#define BIT_GM_STUP_4_0_8814B(x) \ + (((x) & BIT_MASK_GM_STUP_4_0_8814B) << BIT_SHIFT_GM_STUP_4_0_8814B) +#define BITS_GM_STUP_4_0_8814B \ + (BIT_MASK_GM_STUP_4_0_8814B << BIT_SHIFT_GM_STUP_4_0_8814B) +#define BIT_CLEAR_GM_STUP_4_0_8814B(x) ((x) & (~BITS_GM_STUP_4_0_8814B)) +#define BIT_GET_GM_STUP_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_GM_STUP_4_0_8814B) & BIT_MASK_GM_STUP_4_0_8814B) +#define BIT_SET_GM_STUP_4_0_8814B(x, v) \ + (BIT_CLEAR_GM_STUP_4_0_8814B(x) | BIT_GM_STUP_4_0_8814B(v)) + +#define BIT_SHIFT_XTAL_CK_SET_2_0_8814B 13 +#define BIT_MASK_XTAL_CK_SET_2_0_8814B 0x7 +#define BIT_XTAL_CK_SET_2_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_CK_SET_2_0_8814B) \ + << BIT_SHIFT_XTAL_CK_SET_2_0_8814B) +#define BITS_XTAL_CK_SET_2_0_8814B \ + (BIT_MASK_XTAL_CK_SET_2_0_8814B << BIT_SHIFT_XTAL_CK_SET_2_0_8814B) +#define BIT_CLEAR_XTAL_CK_SET_2_0_8814B(x) ((x) & (~BITS_XTAL_CK_SET_2_0_8814B)) +#define BIT_GET_XTAL_CK_SET_2_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_CK_SET_2_0_8814B) & \ + BIT_MASK_XTAL_CK_SET_2_0_8814B) +#define BIT_SET_XTAL_CK_SET_2_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_CK_SET_2_0_8814B(x) | BIT_XTAL_CK_SET_2_0_8814B(v)) + +#define BIT_SHIFT_GM_INIT_4_0_8814B 8 +#define BIT_MASK_GM_INIT_4_0_8814B 0x1f +#define BIT_GM_INIT_4_0_8814B(x) \ + (((x) & BIT_MASK_GM_INIT_4_0_8814B) << BIT_SHIFT_GM_INIT_4_0_8814B) +#define BITS_GM_INIT_4_0_8814B \ + (BIT_MASK_GM_INIT_4_0_8814B << BIT_SHIFT_GM_INIT_4_0_8814B) +#define BIT_CLEAR_GM_INIT_4_0_8814B(x) ((x) & (~BITS_GM_INIT_4_0_8814B)) +#define BIT_GET_GM_INIT_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_GM_INIT_4_0_8814B) & BIT_MASK_GM_INIT_4_0_8814B) +#define BIT_SET_GM_INIT_4_0_8814B(x, v) \ + (BIT_CLEAR_GM_INIT_4_0_8814B(x) | BIT_GM_INIT_4_0_8814B(v)) + +#define BIT_GM_STEP_8814B BIT(7) + +#define BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B 2 +#define BIT_MASK_XAAC_GM_OFFSET_4_0_8814B 0x1f +#define BIT_XAAC_GM_OFFSET_4_0_8814B(x) \ + (((x) & BIT_MASK_XAAC_GM_OFFSET_4_0_8814B) \ + << BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B) +#define BITS_XAAC_GM_OFFSET_4_0_8814B \ + (BIT_MASK_XAAC_GM_OFFSET_4_0_8814B \ + << BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B) +#define BIT_CLEAR_XAAC_GM_OFFSET_4_0_8814B(x) \ + ((x) & (~BITS_XAAC_GM_OFFSET_4_0_8814B)) +#define BIT_GET_XAAC_GM_OFFSET_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B) & \ + BIT_MASK_XAAC_GM_OFFSET_4_0_8814B) +#define BIT_SET_XAAC_GM_OFFSET_4_0_8814B(x, v) \ + (BIT_CLEAR_XAAC_GM_OFFSET_4_0_8814B(x) | \ + BIT_XAAC_GM_OFFSET_4_0_8814B(v)) + +#define BIT_OFFSET_PLUS_8814B BIT(1) +#define BIT_RESET_N_8814B BIT(0) + +/* 2 REG_ANAPAR_XTAL_R_ONLY_8814B */ +#define BIT_XTAL_PKDET_OUT_8814B BIT(6) + +#define BIT_SHIFT_XTAL_GM_AAC_4_0_8814B 1 +#define BIT_MASK_XTAL_GM_AAC_4_0_8814B 0x1f +#define BIT_XTAL_GM_AAC_4_0_8814B(x) \ + (((x) & BIT_MASK_XTAL_GM_AAC_4_0_8814B) \ + << BIT_SHIFT_XTAL_GM_AAC_4_0_8814B) +#define BITS_XTAL_GM_AAC_4_0_8814B \ + (BIT_MASK_XTAL_GM_AAC_4_0_8814B << BIT_SHIFT_XTAL_GM_AAC_4_0_8814B) +#define BIT_CLEAR_XTAL_GM_AAC_4_0_8814B(x) ((x) & (~BITS_XTAL_GM_AAC_4_0_8814B)) +#define BIT_GET_XTAL_GM_AAC_4_0_8814B(x) \ + (((x) >> BIT_SHIFT_XTAL_GM_AAC_4_0_8814B) & \ + BIT_MASK_XTAL_GM_AAC_4_0_8814B) +#define BIT_SET_XTAL_GM_AAC_4_0_8814B(x, v) \ + (BIT_CLEAR_XTAL_GM_AAC_4_0_8814B(x) | BIT_XTAL_GM_AAC_4_0_8814B(v)) + +#define BIT_XAAC_READY_8814B BIT(0) + +/* 2 REG_CPHY_LDO_8814B */ + +#define BIT_SHIFT_CPHY_LDO_PD_8814B 12 +#define BIT_MASK_CPHY_LDO_PD_8814B 0x3 +#define BIT_CPHY_LDO_PD_8814B(x) \ + (((x) & BIT_MASK_CPHY_LDO_PD_8814B) << BIT_SHIFT_CPHY_LDO_PD_8814B) +#define BITS_CPHY_LDO_PD_8814B \ + (BIT_MASK_CPHY_LDO_PD_8814B << BIT_SHIFT_CPHY_LDO_PD_8814B) +#define BIT_CLEAR_CPHY_LDO_PD_8814B(x) ((x) & (~BITS_CPHY_LDO_PD_8814B)) +#define BIT_GET_CPHY_LDO_PD_8814B(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_PD_8814B) & BIT_MASK_CPHY_LDO_PD_8814B) +#define BIT_SET_CPHY_LDO_PD_8814B(x, v) \ + (BIT_CLEAR_CPHY_LDO_PD_8814B(x) | BIT_CPHY_LDO_PD_8814B(v)) + +#define BIT_SHIFT_CPHY_LDO_SR_8814B 10 +#define BIT_MASK_CPHY_LDO_SR_8814B 0x3 +#define BIT_CPHY_LDO_SR_8814B(x) \ + (((x) & BIT_MASK_CPHY_LDO_SR_8814B) << BIT_SHIFT_CPHY_LDO_SR_8814B) +#define BITS_CPHY_LDO_SR_8814B \ + (BIT_MASK_CPHY_LDO_SR_8814B << BIT_SHIFT_CPHY_LDO_SR_8814B) +#define BIT_CLEAR_CPHY_LDO_SR_8814B(x) ((x) & (~BITS_CPHY_LDO_SR_8814B)) +#define BIT_GET_CPHY_LDO_SR_8814B(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_SR_8814B) & BIT_MASK_CPHY_LDO_SR_8814B) +#define BIT_SET_CPHY_LDO_SR_8814B(x, v) \ + (BIT_CLEAR_CPHY_LDO_SR_8814B(x) | BIT_CPHY_LDO_SR_8814B(v)) + +#define BIT_SHIFT_CPHY_LDO_TUNEREF_8814B 8 +#define BIT_MASK_CPHY_LDO_TUNEREF_8814B 0x3 +#define BIT_CPHY_LDO_TUNEREF_8814B(x) \ + (((x) & BIT_MASK_CPHY_LDO_TUNEREF_8814B) \ + << BIT_SHIFT_CPHY_LDO_TUNEREF_8814B) +#define BITS_CPHY_LDO_TUNEREF_8814B \ + (BIT_MASK_CPHY_LDO_TUNEREF_8814B << BIT_SHIFT_CPHY_LDO_TUNEREF_8814B) +#define BIT_CLEAR_CPHY_LDO_TUNEREF_8814B(x) \ + ((x) & (~BITS_CPHY_LDO_TUNEREF_8814B)) +#define BIT_GET_CPHY_LDO_TUNEREF_8814B(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_TUNEREF_8814B) & \ + BIT_MASK_CPHY_LDO_TUNEREF_8814B) +#define BIT_SET_CPHY_LDO_TUNEREF_8814B(x, v) \ + (BIT_CLEAR_CPHY_LDO_TUNEREF_8814B(x) | BIT_CPHY_LDO_TUNEREF_8814B(v)) + +#define BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B 5 +#define BIT_MASK_CPHY_LDO_TUNE_VO_8814B 0x7 +#define BIT_CPHY_LDO_TUNE_VO_8814B(x) \ + (((x) & BIT_MASK_CPHY_LDO_TUNE_VO_8814B) \ + << BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B) +#define BITS_CPHY_LDO_TUNE_VO_8814B \ + (BIT_MASK_CPHY_LDO_TUNE_VO_8814B << BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B) +#define BIT_CLEAR_CPHY_LDO_TUNE_VO_8814B(x) \ + ((x) & (~BITS_CPHY_LDO_TUNE_VO_8814B)) +#define BIT_GET_CPHY_LDO_TUNE_VO_8814B(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B) & \ + BIT_MASK_CPHY_LDO_TUNE_VO_8814B) +#define BIT_SET_CPHY_LDO_TUNE_VO_8814B(x, v) \ + (BIT_CLEAR_CPHY_LDO_TUNE_VO_8814B(x) | BIT_CPHY_LDO_TUNE_VO_8814B(v)) + +#define BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B 2 +#define BIT_MASK_CPHY_LDO_OCP_VTH_8814B 0x7 +#define BIT_CPHY_LDO_OCP_VTH_8814B(x) \ + (((x) & BIT_MASK_CPHY_LDO_OCP_VTH_8814B) \ + << BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B) +#define BITS_CPHY_LDO_OCP_VTH_8814B \ + (BIT_MASK_CPHY_LDO_OCP_VTH_8814B << BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B) +#define BIT_CLEAR_CPHY_LDO_OCP_VTH_8814B(x) \ + ((x) & (~BITS_CPHY_LDO_OCP_VTH_8814B)) +#define BIT_GET_CPHY_LDO_OCP_VTH_8814B(x) \ + (((x) >> BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B) & \ + BIT_MASK_CPHY_LDO_OCP_VTH_8814B) +#define BIT_SET_CPHY_LDO_OCP_VTH_8814B(x, v) \ + (BIT_CLEAR_CPHY_LDO_OCP_VTH_8814B(x) | BIT_CPHY_LDO_OCP_VTH_8814B(v)) + +#define BIT_SHIFT_VREF_LDO_OK_8814B 0 +#define BIT_MASK_VREF_LDO_OK_8814B 0x3 +#define BIT_VREF_LDO_OK_8814B(x) \ + (((x) & BIT_MASK_VREF_LDO_OK_8814B) << BIT_SHIFT_VREF_LDO_OK_8814B) +#define BITS_VREF_LDO_OK_8814B \ + (BIT_MASK_VREF_LDO_OK_8814B << BIT_SHIFT_VREF_LDO_OK_8814B) +#define BIT_CLEAR_VREF_LDO_OK_8814B(x) ((x) & (~BITS_VREF_LDO_OK_8814B)) +#define BIT_GET_VREF_LDO_OK_8814B(x) \ + (((x) >> BIT_SHIFT_VREF_LDO_OK_8814B) & BIT_MASK_VREF_LDO_OK_8814B) +#define BIT_SET_VREF_LDO_OK_8814B(x, v) \ + (BIT_CLEAR_VREF_LDO_OK_8814B(x) | BIT_VREF_LDO_OK_8814B(v)) + +/* 2 REG_CPHY_BG_8814B */ + +#define BIT_SHIFT_BG_8814B 0 +#define BIT_MASK_BG_8814B 0x7 +#define BIT_BG_8814B(x) (((x) & BIT_MASK_BG_8814B) << BIT_SHIFT_BG_8814B) +#define BITS_BG_8814B (BIT_MASK_BG_8814B << BIT_SHIFT_BG_8814B) +#define BIT_CLEAR_BG_8814B(x) ((x) & (~BITS_BG_8814B)) +#define BIT_GET_BG_8814B(x) (((x) >> BIT_SHIFT_BG_8814B) & BIT_MASK_BG_8814B) +#define BIT_SET_BG_8814B(x, v) (BIT_CLEAR_BG_8814B(x) | BIT_BG_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_HIMR_4_8814B */ +#define BIT_TXBCN_OK_PORT4_8814B BIT(31) +#define BIT_TXBCN_OK_PORT3_8814B BIT(30) +#define BIT_TXBCN_OK_PORT2_8814B BIT(29) +#define BIT_TXBCN_OK_PORT1_8814B BIT(28) +#define BIT_TXBCN15OK_8814B BIT(23) +#define BIT_TXBCN14OK_8814B BIT(22) +#define BIT_TXBCN13OK_8814B BIT(21) +#define BIT_TXBCN12OK_8814B BIT(20) +#define BIT_TXBCN11OK_8814B BIT(19) +#define BIT_TXBCN10OK_8814B BIT(18) +#define BIT_TXBCN9OK_8814B BIT(17) +#define BIT_TXBCN8OK_8814B BIT(16) +#define BIT_BCNDERR_PORT4_8814B BIT(15) +#define BIT_BCNDERR_PORT3_8814B BIT(14) +#define BIT_BCNDERR_PORT2_8814B BIT(13) +#define BIT_BCNDERR_PORT1_8814B BIT(12) +#define BIT_TXBCN15ERR_8814B BIT(7) +#define BIT_TXBCN14ERR_8814B BIT(6) +#define BIT_TXBCN13ERR_8814B BIT(5) +#define BIT_TXBCN12ERR_8814B BIT(4) +#define BIT_TXBCN11ERR_8814B BIT(3) +#define BIT_TXBCN10ERR_8814B BIT(2) +#define BIT_TXBCN9ERR_8814B BIT(1) +#define BIT_TXBCN8ERR_8814B BIT(0) + +/* 2 REG_HISR_4_8814B */ +#define BIT_TXBCN_OK_PORT4_8814B BIT(31) +#define BIT_TXBCN_OK_PORT3_8814B BIT(30) +#define BIT_TXBCN_OK_PORT2_8814B BIT(29) +#define BIT_TXBCN_OK_PORT1_8814B BIT(28) +#define BIT_TXBCN15OK_8814B BIT(23) +#define BIT_TXBCN14OK_8814B BIT(22) +#define BIT_TXBCN13OK_8814B BIT(21) +#define BIT_TXBCN12OK_8814B BIT(20) +#define BIT_TXBCN11OK_8814B BIT(19) +#define BIT_TXBCN10OK_8814B BIT(18) +#define BIT_TXBCN9OK_8814B BIT(17) +#define BIT_TXBCN8OK_8814B BIT(16) +#define BIT_BCNDERR_PORT4_8814B BIT(15) +#define BIT_BCNDERR_PORT3_8814B BIT(14) +#define BIT_BCNDERR_PORT2_8814B BIT(13) +#define BIT_BCNDERR_PORT1_8814B BIT(12) +#define BIT_TXBCN15ERR_8814B BIT(7) +#define BIT_TXBCN14ERR_8814B BIT(6) +#define BIT_TXBCN13ERR_8814B BIT(5) +#define BIT_TXBCN12ERR_8814B BIT(4) +#define BIT_TXBCN11ERR_8814B BIT(3) +#define BIT_TXBCN10ERR_8814B BIT(2) +#define BIT_TXBCN9ERR_8814B BIT(1) +#define BIT_TXBCN8ERR_8814B BIT(0) + +/* 2 REG_HIMR_5_8814B */ +#define BIT_BCNDMAINT15_8814B BIT(23) +#define BIT_BCNDMAINT14_8814B BIT(22) +#define BIT_BCNDMAINT13_8814B BIT(21) +#define BIT_BCNDMAINT12_8814B BIT(20) +#define BIT_BCNDMAINT11_8814B BIT(19) +#define BIT_BCNDMAINT10_8814B BIT(18) +#define BIT_BCNDMAINT9_8814B BIT(17) +#define BIT_BCNDMAINT8_8814B BIT(16) +#define BIT_BCNDERR_PORT4_8814B BIT(15) +#define BIT_BCNDERR_PORT3_8814B BIT(14) +#define BIT_BCNDERR_PORT2_8814B BIT(13) +#define BIT_BCNDERR_PORT1_8814B BIT(12) +#define BIT_BCNDERR15_8814B BIT(7) +#define BIT_BCNDERR14_8814B BIT(6) +#define BIT_BCNDERR13_8814B BIT(5) +#define BIT_BCNDERR12_8814B BIT(4) +#define BIT_BCNDERR11_8814B BIT(3) +#define BIT_BCNDERR10_8814B BIT(2) +#define BIT_BCNDERR9_8814B BIT(1) +#define BIT_BCNDERR8_8814B BIT(0) + +/* 2 REG_HISR_5_8814B */ +#define BIT_BCNDMAINT15_8814B BIT(23) +#define BIT_BCNDMAINT14_8814B BIT(22) +#define BIT_BCNDMAINT13_8814B BIT(21) +#define BIT_BCNDMAINT12_8814B BIT(20) +#define BIT_BCNDMAINT11_8814B BIT(19) +#define BIT_BCNDMAINT10_8814B BIT(18) +#define BIT_BCNDMAINT9_8814B BIT(17) +#define BIT_BCNDMAINT8_8814B BIT(16) +#define BIT_BCNDERR_PORT4_8814B BIT(15) +#define BIT_BCNDERR_PORT3_8814B BIT(14) +#define BIT_BCNDERR_PORT2_8814B BIT(13) +#define BIT_BCNDERR_PORT1_8814B BIT(12) +#define BIT_BCNDERR15_8814B BIT(7) +#define BIT_BCNDERR14_8814B BIT(6) +#define BIT_BCNDERR13_8814B BIT(5) +#define BIT_BCNDERR12_8814B BIT(4) +#define BIT_BCNDERR11_8814B BIT(3) +#define BIT_BCNDERR10_8814B BIT(2) +#define BIT_BCNDERR9_8814B BIT(1) +#define BIT_BCNDERR8_8814B BIT(0) /* 2 REG_SYS_CFG5_8814B */ #define BIT_LPS_STATUS_8814B BIT(3) @@ -1784,6 +3461,48 @@ #define BIT_HCI_TXDMA_ALLOW_8814B BIT(1) #define BIT_FW_CTRL_HCI_TXDMA_EN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_HIMR_6_8814B */ +#define BIT_ATIMEND_PORT4_8814B BIT(31) +#define BIT_ATIMEND_PORT3_8814B BIT(30) +#define BIT_ATIMEND_PORT2_8814B BIT(29) +#define BIT_ATIMEND_PORT1_8814B BIT(28) +#define BIT_ATIMEND15_8814B BIT(23) +#define BIT_ATIMEND14_8814B BIT(22) +#define BIT_ATIMEND13_8814B BIT(21) +#define BIT_ATIMEND12_8814B BIT(20) +#define BIT_ATIMEND11_8814B BIT(19) +#define BIT_ATIMEND10_8814B BIT(18) +#define BIT_ATIMEND9_8814B BIT(17) +#define BIT_ATIMEND8_8814B BIT(16) +#define BIT_PS_TIMER_EARLY_INT_5_8814B BIT(5) +#define BIT_PS_TIMER_EARLY_INT_4_8814B BIT(4) +#define BIT_PS_TIMER_EARLY_INT_3_8814B BIT(3) +#define BIT_PS_TIMER_EARLY_INT_2_8814B BIT(2) +#define BIT_PS_TIMER_EARLY_INT_1_8814B BIT(1) +#define BIT_PS_TIMER_EARLY_INT_0_8814B BIT(0) + +/* 2 REG_HISR_6_8814B */ +#define BIT_ATIMEND_PORT4_8814B BIT(31) +#define BIT_ATIMEND_PORT3_8814B BIT(30) +#define BIT_ATIMEND_PORT2_8814B BIT(29) +#define BIT_ATIMEND_PORT1_8814B BIT(28) +#define BIT_ATIMEND15_8814B BIT(23) +#define BIT_ATIMEND14_8814B BIT(22) +#define BIT_ATIMEND13_8814B BIT(21) +#define BIT_ATIMEND12_8814B BIT(20) +#define BIT_ATIMEND11_8814B BIT(19) +#define BIT_ATIMEND10_8814B BIT(18) +#define BIT_ATIMEND9_8814B BIT(17) +#define BIT_ATIMEND8_8814B BIT(16) +#define BIT_PS_TIMER_EARLY_INT_5_8814B BIT(5) +#define BIT_PS_TIMER_EARLY_INT_4_8814B BIT(4) +#define BIT_PS_TIMER_EARLY_INT_3_8814B BIT(3) +#define BIT_PS_TIMER_EARLY_INT_2_8814B BIT(2) +#define BIT_PS_TIMER_EARLY_INT_1_8814B BIT(1) +#define BIT_PS_TIMER_EARLY_INT_0_8814B BIT(0) + /* 2 REG_CPU_DMEM_CON_8814B */ #define BIT_WDT_AUTO_MODE_8814B BIT(22) #define BIT_WDT_PLATFORM_EN_8814B BIT(21) @@ -1793,22 +3512,146 @@ #define BIT_MAC_PORT_IDLE_8814B BIT(17) #define BIT_WL_PLATFORM_RST_8814B BIT(16) #define BIT_WL_SECURITY_CLK_8814B BIT(15) +#define BIT_DDMA_EN_8814B BIT(8) #define BIT_SHIFT_CPU_DMEM_CON_8814B 0 #define BIT_MASK_CPU_DMEM_CON_8814B 0xff -#define BIT_CPU_DMEM_CON_8814B(x) (((x) & BIT_MASK_CPU_DMEM_CON_8814B) << BIT_SHIFT_CPU_DMEM_CON_8814B) -#define BIT_GET_CPU_DMEM_CON_8814B(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8814B) & BIT_MASK_CPU_DMEM_CON_8814B) - +#define BIT_CPU_DMEM_CON_8814B(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON_8814B) << BIT_SHIFT_CPU_DMEM_CON_8814B) +#define BITS_CPU_DMEM_CON_8814B \ + (BIT_MASK_CPU_DMEM_CON_8814B << BIT_SHIFT_CPU_DMEM_CON_8814B) +#define BIT_CLEAR_CPU_DMEM_CON_8814B(x) ((x) & (~BITS_CPU_DMEM_CON_8814B)) +#define BIT_GET_CPU_DMEM_CON_8814B(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON_8814B) & BIT_MASK_CPU_DMEM_CON_8814B) +#define BIT_SET_CPU_DMEM_CON_8814B(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON_8814B(x) | BIT_CPU_DMEM_CON_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_BOOT_REASON_8814B */ -#define BIT_SHIFT_BOOT_REASON_8814B 0 -#define BIT_MASK_BOOT_REASON_8814B 0x7 -#define BIT_BOOT_REASON_8814B(x) (((x) & BIT_MASK_BOOT_REASON_8814B) << BIT_SHIFT_BOOT_REASON_8814B) -#define BIT_GET_BOOT_REASON_8814B(x) (((x) >> BIT_SHIFT_BOOT_REASON_8814B) & BIT_MASK_BOOT_REASON_8814B) +#define BIT_SHIFT_BOOT_REASON_V1_8814B 0 +#define BIT_MASK_BOOT_REASON_V1_8814B 0x7 +#define BIT_BOOT_REASON_V1_8814B(x) \ + (((x) & BIT_MASK_BOOT_REASON_V1_8814B) \ + << BIT_SHIFT_BOOT_REASON_V1_8814B) +#define BITS_BOOT_REASON_V1_8814B \ + (BIT_MASK_BOOT_REASON_V1_8814B << BIT_SHIFT_BOOT_REASON_V1_8814B) +#define BIT_CLEAR_BOOT_REASON_V1_8814B(x) ((x) & (~BITS_BOOT_REASON_V1_8814B)) +#define BIT_GET_BOOT_REASON_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BOOT_REASON_V1_8814B) & \ + BIT_MASK_BOOT_REASON_V1_8814B) +#define BIT_SET_BOOT_REASON_V1_8814B(x, v) \ + (BIT_CLEAR_BOOT_REASON_V1_8814B(x) | BIT_BOOT_REASON_V1_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_DATA_CPU_CTL0_8814B */ +#define BIT_DATA_FW_READY_8814B BIT(31) +#define BIT_WDT_SYS_RST_8814B BIT(13) +#define BIT_WDT_ENABLE_8814B BIT(12) + +#define BIT_SHIFT_BOOT_SEL_8814B 6 +#define BIT_MASK_BOOT_SEL_8814B 0x3 +#define BIT_BOOT_SEL_8814B(x) \ + (((x) & BIT_MASK_BOOT_SEL_8814B) << BIT_SHIFT_BOOT_SEL_8814B) +#define BITS_BOOT_SEL_8814B \ + (BIT_MASK_BOOT_SEL_8814B << BIT_SHIFT_BOOT_SEL_8814B) +#define BIT_CLEAR_BOOT_SEL_8814B(x) ((x) & (~BITS_BOOT_SEL_8814B)) +#define BIT_GET_BOOT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_BOOT_SEL_8814B) & BIT_MASK_BOOT_SEL_8814B) +#define BIT_SET_BOOT_SEL_8814B(x, v) \ + (BIT_CLEAR_BOOT_SEL_8814B(x) | BIT_BOOT_SEL_8814B(v)) + +#define BIT_CLK_SEL_8814B BIT(4) +#define BIT_DATA_PLATFORM_RST_8814B BIT(1) +#define BIT_DATA_CPU_RST_8814B BIT(0) + +/* 2 REG_DATA_CPU_CTL1_8814B */ +#define BIT_HOST_INTERFACE_IO_PATH_8814B BIT(7) +#define BIT_EN_TXDMA_OFLD_8814B BIT(6) +#define BIT_EN_RXDMA_OFLD_8814B BIT(5) +#define BIT_EN_HCI_DMA_TX_8814B BIT(4) +#define BIT_EN_HCI_DMA_RX_8814B BIT(3) +#define BIT_EN_AXI_DMA_TX_8814B BIT(2) +#define BIT_EN_AXI_DMA_RX_8814B BIT(1) +#define BIT_EN_PKT_ENG_8814B BIT(0) + +/* 2 REG_TXDMA_STOP_HIMR_8814B */ + +#define BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B 0 +#define BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B 0x1ffff +#define BIT_NTH_TXDMA_STOP_INT_MSK_8814B(x) \ + (((x) & BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B) \ + << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B) +#define BITS_NTH_TXDMA_STOP_INT_MSK_8814B \ + (BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B \ + << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B) +#define BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK_8814B(x) \ + ((x) & (~BITS_NTH_TXDMA_STOP_INT_MSK_8814B)) +#define BIT_GET_NTH_TXDMA_STOP_INT_MSK_8814B(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B) & \ + BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B) +#define BIT_SET_NTH_TXDMA_STOP_INT_MSK_8814B(x, v) \ + (BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK_8814B(x) | \ + BIT_NTH_TXDMA_STOP_INT_MSK_8814B(v)) + +/* 2 REG_TXDMA_STOP_HISR_8814B */ + +#define BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B 0 +#define BIT_MASK_NTH_TXDMA_STOP_INT_8814B 0x1ffff +#define BIT_NTH_TXDMA_STOP_INT_8814B(x) \ + (((x) & BIT_MASK_NTH_TXDMA_STOP_INT_8814B) \ + << BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B) +#define BITS_NTH_TXDMA_STOP_INT_8814B \ + (BIT_MASK_NTH_TXDMA_STOP_INT_8814B \ + << BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B) +#define BIT_CLEAR_NTH_TXDMA_STOP_INT_8814B(x) \ + ((x) & (~BITS_NTH_TXDMA_STOP_INT_8814B)) +#define BIT_GET_NTH_TXDMA_STOP_INT_8814B(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B) & \ + BIT_MASK_NTH_TXDMA_STOP_INT_8814B) +#define BIT_SET_NTH_TXDMA_STOP_INT_8814B(x, v) \ + (BIT_CLEAR_NTH_TXDMA_STOP_INT_8814B(x) | \ + BIT_NTH_TXDMA_STOP_INT_8814B(v)) + +/* 2 REG_TXDMA_START_HIMR_8814B */ + +#define BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B 0 +#define BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B 0x1ffff +#define BIT_NTH_TXDMA_START_INT_MSK_8814B(x) \ + (((x) & BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B) \ + << BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B) +#define BITS_NTH_TXDMA_START_INT_MSK_8814B \ + (BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B \ + << BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B) +#define BIT_CLEAR_NTH_TXDMA_START_INT_MSK_8814B(x) \ + ((x) & (~BITS_NTH_TXDMA_START_INT_MSK_8814B)) +#define BIT_GET_NTH_TXDMA_START_INT_MSK_8814B(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B) & \ + BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B) +#define BIT_SET_NTH_TXDMA_START_INT_MSK_8814B(x, v) \ + (BIT_CLEAR_NTH_TXDMA_START_INT_MSK_8814B(x) | \ + BIT_NTH_TXDMA_START_INT_MSK_8814B(v)) + +/* 2 REG_TXDMA_START_HISR_8814B */ + +#define BIT_SHIFT_NTH_TXDMA_START_INT_8814B 0 +#define BIT_MASK_NTH_TXDMA_START_INT_8814B 0x1ffff +#define BIT_NTH_TXDMA_START_INT_8814B(x) \ + (((x) & BIT_MASK_NTH_TXDMA_START_INT_8814B) \ + << BIT_SHIFT_NTH_TXDMA_START_INT_8814B) +#define BITS_NTH_TXDMA_START_INT_8814B \ + (BIT_MASK_NTH_TXDMA_START_INT_8814B \ + << BIT_SHIFT_NTH_TXDMA_START_INT_8814B) +#define BIT_CLEAR_NTH_TXDMA_START_INT_8814B(x) \ + ((x) & (~BITS_NTH_TXDMA_START_INT_8814B)) +#define BIT_GET_NTH_TXDMA_START_INT_8814B(x) \ + (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_8814B) & \ + BIT_MASK_NTH_TXDMA_START_INT_8814B) +#define BIT_SET_NTH_TXDMA_START_INT_8814B(x, v) \ + (BIT_CLEAR_NTH_TXDMA_START_INT_8814B(x) | \ + BIT_NTH_TXDMA_START_INT_8814B(v)) /* 2 REG_NFCPAD_CTRL_8814B */ #define BIT_PAD_SHUTDW_8814B BIT(18) @@ -1821,30 +3664,48 @@ #define BIT_SHIFT_NFCPAD_IO_SEL_8814B 8 #define BIT_MASK_NFCPAD_IO_SEL_8814B 0xf -#define BIT_NFCPAD_IO_SEL_8814B(x) (((x) & BIT_MASK_NFCPAD_IO_SEL_8814B) << BIT_SHIFT_NFCPAD_IO_SEL_8814B) -#define BIT_GET_NFCPAD_IO_SEL_8814B(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8814B) & BIT_MASK_NFCPAD_IO_SEL_8814B) - - +#define BIT_NFCPAD_IO_SEL_8814B(x) \ + (((x) & BIT_MASK_NFCPAD_IO_SEL_8814B) << BIT_SHIFT_NFCPAD_IO_SEL_8814B) +#define BITS_NFCPAD_IO_SEL_8814B \ + (BIT_MASK_NFCPAD_IO_SEL_8814B << BIT_SHIFT_NFCPAD_IO_SEL_8814B) +#define BIT_CLEAR_NFCPAD_IO_SEL_8814B(x) ((x) & (~BITS_NFCPAD_IO_SEL_8814B)) +#define BIT_GET_NFCPAD_IO_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8814B) & BIT_MASK_NFCPAD_IO_SEL_8814B) +#define BIT_SET_NFCPAD_IO_SEL_8814B(x, v) \ + (BIT_CLEAR_NFCPAD_IO_SEL_8814B(x) | BIT_NFCPAD_IO_SEL_8814B(v)) #define BIT_SHIFT_NFCPAD_OUT_8814B 4 #define BIT_MASK_NFCPAD_OUT_8814B 0xf -#define BIT_NFCPAD_OUT_8814B(x) (((x) & BIT_MASK_NFCPAD_OUT_8814B) << BIT_SHIFT_NFCPAD_OUT_8814B) -#define BIT_GET_NFCPAD_OUT_8814B(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8814B) & BIT_MASK_NFCPAD_OUT_8814B) - - +#define BIT_NFCPAD_OUT_8814B(x) \ + (((x) & BIT_MASK_NFCPAD_OUT_8814B) << BIT_SHIFT_NFCPAD_OUT_8814B) +#define BITS_NFCPAD_OUT_8814B \ + (BIT_MASK_NFCPAD_OUT_8814B << BIT_SHIFT_NFCPAD_OUT_8814B) +#define BIT_CLEAR_NFCPAD_OUT_8814B(x) ((x) & (~BITS_NFCPAD_OUT_8814B)) +#define BIT_GET_NFCPAD_OUT_8814B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_OUT_8814B) & BIT_MASK_NFCPAD_OUT_8814B) +#define BIT_SET_NFCPAD_OUT_8814B(x, v) \ + (BIT_CLEAR_NFCPAD_OUT_8814B(x) | BIT_NFCPAD_OUT_8814B(v)) #define BIT_SHIFT_NFCPAD_IN_8814B 0 #define BIT_MASK_NFCPAD_IN_8814B 0xf -#define BIT_NFCPAD_IN_8814B(x) (((x) & BIT_MASK_NFCPAD_IN_8814B) << BIT_SHIFT_NFCPAD_IN_8814B) -#define BIT_GET_NFCPAD_IN_8814B(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8814B) & BIT_MASK_NFCPAD_IN_8814B) - +#define BIT_NFCPAD_IN_8814B(x) \ + (((x) & BIT_MASK_NFCPAD_IN_8814B) << BIT_SHIFT_NFCPAD_IN_8814B) +#define BITS_NFCPAD_IN_8814B \ + (BIT_MASK_NFCPAD_IN_8814B << BIT_SHIFT_NFCPAD_IN_8814B) +#define BIT_CLEAR_NFCPAD_IN_8814B(x) ((x) & (~BITS_NFCPAD_IN_8814B)) +#define BIT_GET_NFCPAD_IN_8814B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IN_8814B) & BIT_MASK_NFCPAD_IN_8814B) +#define BIT_SET_NFCPAD_IN_8814B(x, v) \ + (BIT_CLEAR_NFCPAD_IN_8814B(x) | BIT_NFCPAD_IN_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_HIMR2_8814B */ #define BIT_BCNDMAINT_P4_MSK_8814B BIT(31) #define BIT_BCNDMAINT_P3_MSK_8814B BIT(30) #define BIT_BCNDMAINT_P2_MSK_8814B BIT(29) #define BIT_BCNDMAINT_P1_MSK_8814B BIT(28) +#define BIT_SCH_PHY_TXOP_SIFS_INT_MSK_8814B BIT(23) #define BIT_ATIMEND7_MSK_8814B BIT(22) #define BIT_ATIMEND6_MSK_8814B BIT(21) #define BIT_ATIMEND5_MSK_8814B BIT(20) @@ -1872,6 +3733,7 @@ #define BIT_BCNDMAINT_P3_8814B BIT(30) #define BIT_BCNDMAINT_P2_8814B BIT(29) #define BIT_BCNDMAINT_P1_8814B BIT(28) +#define BIT_SCH_PHY_TXOP_SIFS_INT_8814B BIT(23) #define BIT_ATIMEND7_8814B BIT(22) #define BIT_ATIMEND6_8814B BIT(21) #define BIT_ATIMEND5_8814B BIT(20) @@ -1895,86 +3757,141 @@ #define BIT_TXBCN1ERR_8814B BIT(0) /* 2 REG_HIMR3_8814B */ +#define BIT_GTINT12_MSK_8814B BIT(24) +#define BIT_GTINT11_MSK_8814B BIT(23) +#define BIT_GTINT10_MSK_8814B BIT(22) +#define BIT_GTINT9_MSK_8814B BIT(21) +#define BIT_RX_DESC_BUF_FULL_MSK_8814B BIT(20) +#define BIT_CPHY_LDO_OCP_DET_INT_MSK_8814B BIT(19) #define BIT_WDT_PLATFORM_INT_MSK_8814B BIT(18) #define BIT_WDT_CPU_INT_MSK_8814B BIT(17) #define BIT_SETH2CDOK_MASK_8814B BIT(16) #define BIT_H2C_CMD_FULL_MASK_8814B BIT(15) -#define BIT_PWR_INT_127_MASK_8814B BIT(14) +#define BIT_PKT_TRANS_ERR_MASK_8814B BIT(14) #define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8814B BIT(13) #define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8814B BIT(12) #define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8814B BIT(11) #define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8814B BIT(10) #define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8814B BIT(9) -#define BIT_PWR_INT_127_MASK_V1_8814B BIT(8) -#define BIT_PWR_INT_126TO96_MASK_8814B BIT(7) +#define BIT_SEARCH_FAIL_MSK_8814B BIT(8) +#define BIT_PWR_INT_127TO96_MASK_8814B BIT(7) #define BIT_PWR_INT_95TO64_MASK_8814B BIT(6) #define BIT_PWR_INT_63TO32_MASK_8814B BIT(5) #define BIT_PWR_INT_31TO0_MASK_8814B BIT(4) +#define BIT_RX_DMA_STUCK_MSK_8814B BIT(3) +#define BIT_TX_DMA_STUCK_MSK_8814B BIT(2) #define BIT_DDMA0_LP_INT_MSK_8814B BIT(1) #define BIT_DDMA0_HP_INT_MSK_8814B BIT(0) /* 2 REG_HISR3_8814B */ +#define BIT_GTINT12_8814B BIT(24) +#define BIT_GTINT11_8814B BIT(23) +#define BIT_GTINT10_8814B BIT(22) +#define BIT_GTINT9_8814B BIT(21) +#define BIT_RX_DESC_BUF_FULL_8814B BIT(20) +#define BIT_CPHY_LDO_OCP_DET_INT_8814B BIT(19) #define BIT_WDT_PLATFORM_INT_8814B BIT(18) #define BIT_WDT_CPU_INT_8814B BIT(17) #define BIT_SETH2CDOK_8814B BIT(16) #define BIT_H2C_CMD_FULL_8814B BIT(15) -#define BIT_PWR_INT_127_8814B BIT(14) +#define BIT_PKT_TRANS_ERR_8814B BIT(14) #define BIT_TXSHORTCUT_TXDESUPDATEOK_8814B BIT(13) #define BIT_TXSHORTCUT_BKUPDATEOK_8814B BIT(12) #define BIT_TXSHORTCUT_BEUPDATEOK_8814B BIT(11) #define BIT_TXSHORTCUT_VIUPDATEOK_8814B BIT(10) #define BIT_TXSHORTCUT_VOUPDATEOK_8814B BIT(9) -#define BIT_PWR_INT_127_V1_8814B BIT(8) -#define BIT_PWR_INT_126TO96_8814B BIT(7) +#define BIT_SEARCH_FAIL_8814B BIT(8) +#define BIT_PWR_INT_127TO96_8814B BIT(7) #define BIT_PWR_INT_95TO64_8814B BIT(6) #define BIT_PWR_INT_63TO32_8814B BIT(5) #define BIT_PWR_INT_31TO0_8814B BIT(4) +#define BIT_RX_DMA_STUCK_8814B BIT(3) +#define BIT_TX_DMA_STUCK_8814B BIT(2) #define BIT_DDMA0_LP_INT_8814B BIT(1) #define BIT_DDMA0_HP_INT_8814B BIT(0) /* 2 REG_SW_MDIO_8814B */ #define BIT_DIS_TIMEOUT_IO_8814B BIT(24) -/* 2 REG_SW_FLUSH_8814B */ -#define BIT_FLUSH_HOLDN_EN_8814B BIT(25) -#define BIT_FLUSH_WR_EN_8814B BIT(24) -#define BIT_SW_FLASH_CONTROL_8814B BIT(23) -#define BIT_SW_FLASH_WEN_E_8814B BIT(19) -#define BIT_SW_FLASH_HOLDN_E_8814B BIT(18) -#define BIT_SW_FLASH_SO_E_8814B BIT(17) -#define BIT_SW_FLASH_SI_E_8814B BIT(16) -#define BIT_SW_FLASH_SK_O_8814B BIT(13) -#define BIT_SW_FLASH_CEN_O_8814B BIT(12) -#define BIT_SW_FLASH_WEN_O_8814B BIT(11) -#define BIT_SW_FLASH_HOLDN_O_8814B BIT(10) -#define BIT_SW_FLASH_SO_O_8814B BIT(9) -#define BIT_SW_FLASH_SI_O_8814B BIT(8) -#define BIT_SW_FLASH_WEN_I_8814B BIT(3) -#define BIT_SW_FLASH_HOLDN_I_8814B BIT(2) -#define BIT_SW_FLASH_SO_I_8814B BIT(1) -#define BIT_SW_FLASH_SI_I_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_HIMR_7_8814B */ +#define BIT_DATA_CPU_WDT_INT_MSK_8814B BIT(31) +#define BIT_OFLD_TXDMA_ERR_MSK_8814B BIT(30) +#define BIT_OFLD_TXDMA_FULL_MSK_8814B BIT(29) +#define BIT_OFLD_RXDMA_OVR_MSK_8814B BIT(28) +#define BIT_OFLD_RXDMA_ERR_MSK_8814B BIT(27) +#define BIT_OFLD_RXDMA_DES_UA_MSK_8814B BIT(26) +#define BIT_TXDMAOK_CHANNEL_16_MSK_8814B BIT(16) +#define BIT_TXDMAOK_CHANNEL_13_MSK_8814B BIT(13) +#define BIT_TXDMAOK_CHANNEL_12_MSK_8814B BIT(12) +#define BIT_TXDMAOK_CHANNEL_11_MSK_8814B BIT(11) +#define BIT_TXDMAOK_CHANNEL_10_MSK_8814B BIT(10) +#define BIT_TXDMAOK_CHANNEL_9_MSK_8814B BIT(9) +#define BIT_TXDMAOK_CHANNEL_8_MSK_8814B BIT(8) +#define BIT_TXDMAOK_CHANNEL_7_MSK_8814B BIT(7) +#define BIT_TXDMAOK_CHANNEL_6_MSK_8814B BIT(6) +#define BIT_TXDMAOK_CHANNEL_5_MSK_8814B BIT(5) +#define BIT_TXDMAOK_CHANNEL_4_MSK_8814B BIT(4) + +/* 2 REG_HISR_7_8814B */ +#define BIT_DATA_CPU_WDT_INT_8814B BIT(31) +#define BIT_OFLD_TXDMA_ERR_8814B BIT(30) +#define BIT_OFLD_TXDMA_FULL_8814B BIT(29) +#define BIT_OFLD_RXDMA_OVR_8814B BIT(28) +#define BIT_OFLD_RXDMA_ERR_8814B BIT(27) +#define BIT_OFLD_RXDMA_DES_UA_8814B BIT(26) +#define BIT_TXDMAOK_CHANNEL_16_8814B BIT(16) +#define BIT_TXDMAOK_CHANNEL_13_8814B BIT(13) +#define BIT_TXDMAOK_CHANNEL_12_8814B BIT(12) +#define BIT_TXDMAOK_CHANNEL_11_8814B BIT(11) +#define BIT_TXDMAOK_CHANNEL_10_8814B BIT(10) +#define BIT_TXDMAOK_CHANNEL_9_8814B BIT(9) +#define BIT_TXDMAOK_CHANNEL_8_8814B BIT(8) +#define BIT_TXDMAOK_CHANNEL_7_8814B BIT(7) +#define BIT_TXDMAOK_CHANNEL_6_8814B BIT(6) +#define BIT_TXDMAOK_CHANNEL_5_8814B BIT(5) +#define BIT_TXDMAOK_CHANNEL_4_8814B BIT(4) /* 2 REG_H2C_PKT_READADDR_8814B */ #define BIT_SHIFT_H2C_PKT_READADDR_8814B 0 #define BIT_MASK_H2C_PKT_READADDR_8814B 0x3ffff -#define BIT_H2C_PKT_READADDR_8814B(x) (((x) & BIT_MASK_H2C_PKT_READADDR_8814B) << BIT_SHIFT_H2C_PKT_READADDR_8814B) -#define BIT_GET_H2C_PKT_READADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8814B) & BIT_MASK_H2C_PKT_READADDR_8814B) - - +#define BIT_H2C_PKT_READADDR_8814B(x) \ + (((x) & BIT_MASK_H2C_PKT_READADDR_8814B) \ + << BIT_SHIFT_H2C_PKT_READADDR_8814B) +#define BITS_H2C_PKT_READADDR_8814B \ + (BIT_MASK_H2C_PKT_READADDR_8814B << BIT_SHIFT_H2C_PKT_READADDR_8814B) +#define BIT_CLEAR_H2C_PKT_READADDR_8814B(x) \ + ((x) & (~BITS_H2C_PKT_READADDR_8814B)) +#define BIT_GET_H2C_PKT_READADDR_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8814B) & \ + BIT_MASK_H2C_PKT_READADDR_8814B) +#define BIT_SET_H2C_PKT_READADDR_8814B(x, v) \ + (BIT_CLEAR_H2C_PKT_READADDR_8814B(x) | BIT_H2C_PKT_READADDR_8814B(v)) /* 2 REG_H2C_PKT_WRITEADDR_8814B */ #define BIT_SHIFT_H2C_PKT_WRITEADDR_8814B 0 #define BIT_MASK_H2C_PKT_WRITEADDR_8814B 0x3ffff -#define BIT_H2C_PKT_WRITEADDR_8814B(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8814B) << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) -#define BIT_GET_H2C_PKT_WRITEADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) & BIT_MASK_H2C_PKT_WRITEADDR_8814B) - - +#define BIT_H2C_PKT_WRITEADDR_8814B(x) \ + (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8814B) \ + << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) +#define BITS_H2C_PKT_WRITEADDR_8814B \ + (BIT_MASK_H2C_PKT_WRITEADDR_8814B << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) +#define BIT_CLEAR_H2C_PKT_WRITEADDR_8814B(x) \ + ((x) & (~BITS_H2C_PKT_WRITEADDR_8814B)) +#define BIT_GET_H2C_PKT_WRITEADDR_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) & \ + BIT_MASK_H2C_PKT_WRITEADDR_8814B) +#define BIT_SET_H2C_PKT_WRITEADDR_8814B(x, v) \ + (BIT_CLEAR_H2C_PKT_WRITEADDR_8814B(x) | BIT_H2C_PKT_WRITEADDR_8814B(v)) /* 2 REG_MEM_PWR_CRTL_8814B */ #define BIT_MEM_BB_SD_8814B BIT(17) #define BIT_MEM_BB_DS_8814B BIT(16) +#define BIT_MEM_DENG_LS_8814B BIT(13) +#define BIT_MEM_DENG_DS_8814B BIT(12) #define BIT_MEM_BT_DS_8814B BIT(10) #define BIT_MEM_SDIO_LS_8814B BIT(9) #define BIT_MEM_SDIO_DS_8814B BIT(8) @@ -1987,219 +3904,465 @@ #define BIT_MEM_WLMCU_LS_8814B BIT(1) #define BIT_MEM_WLMCU_DS_8814B BIT(0) +/* 2 REG_FW_DRV_HANDSHAKE_8814B */ + +#define BIT_SHIFT_FW_DRV_HANDSHAKE_8814B 0 +#define BIT_MASK_FW_DRV_HANDSHAKE_8814B 0xffffffffL +#define BIT_FW_DRV_HANDSHAKE_8814B(x) \ + (((x) & BIT_MASK_FW_DRV_HANDSHAKE_8814B) \ + << BIT_SHIFT_FW_DRV_HANDSHAKE_8814B) +#define BITS_FW_DRV_HANDSHAKE_8814B \ + (BIT_MASK_FW_DRV_HANDSHAKE_8814B << BIT_SHIFT_FW_DRV_HANDSHAKE_8814B) +#define BIT_CLEAR_FW_DRV_HANDSHAKE_8814B(x) \ + ((x) & (~BITS_FW_DRV_HANDSHAKE_8814B)) +#define BIT_GET_FW_DRV_HANDSHAKE_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DRV_HANDSHAKE_8814B) & \ + BIT_MASK_FW_DRV_HANDSHAKE_8814B) +#define BIT_SET_FW_DRV_HANDSHAKE_8814B(x, v) \ + (BIT_CLEAR_FW_DRV_HANDSHAKE_8814B(x) | BIT_FW_DRV_HANDSHAKE_8814B(v)) + /* 2 REG_FW_DBG0_8814B */ #define BIT_SHIFT_FW_DBG0_8814B 0 #define BIT_MASK_FW_DBG0_8814B 0xffffffffL -#define BIT_FW_DBG0_8814B(x) (((x) & BIT_MASK_FW_DBG0_8814B) << BIT_SHIFT_FW_DBG0_8814B) -#define BIT_GET_FW_DBG0_8814B(x) (((x) >> BIT_SHIFT_FW_DBG0_8814B) & BIT_MASK_FW_DBG0_8814B) - - +#define BIT_FW_DBG0_8814B(x) \ + (((x) & BIT_MASK_FW_DBG0_8814B) << BIT_SHIFT_FW_DBG0_8814B) +#define BITS_FW_DBG0_8814B (BIT_MASK_FW_DBG0_8814B << BIT_SHIFT_FW_DBG0_8814B) +#define BIT_CLEAR_FW_DBG0_8814B(x) ((x) & (~BITS_FW_DBG0_8814B)) +#define BIT_GET_FW_DBG0_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG0_8814B) & BIT_MASK_FW_DBG0_8814B) +#define BIT_SET_FW_DBG0_8814B(x, v) \ + (BIT_CLEAR_FW_DBG0_8814B(x) | BIT_FW_DBG0_8814B(v)) /* 2 REG_FW_DBG1_8814B */ #define BIT_SHIFT_FW_DBG1_8814B 0 #define BIT_MASK_FW_DBG1_8814B 0xffffffffL -#define BIT_FW_DBG1_8814B(x) (((x) & BIT_MASK_FW_DBG1_8814B) << BIT_SHIFT_FW_DBG1_8814B) -#define BIT_GET_FW_DBG1_8814B(x) (((x) >> BIT_SHIFT_FW_DBG1_8814B) & BIT_MASK_FW_DBG1_8814B) - - +#define BIT_FW_DBG1_8814B(x) \ + (((x) & BIT_MASK_FW_DBG1_8814B) << BIT_SHIFT_FW_DBG1_8814B) +#define BITS_FW_DBG1_8814B (BIT_MASK_FW_DBG1_8814B << BIT_SHIFT_FW_DBG1_8814B) +#define BIT_CLEAR_FW_DBG1_8814B(x) ((x) & (~BITS_FW_DBG1_8814B)) +#define BIT_GET_FW_DBG1_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG1_8814B) & BIT_MASK_FW_DBG1_8814B) +#define BIT_SET_FW_DBG1_8814B(x, v) \ + (BIT_CLEAR_FW_DBG1_8814B(x) | BIT_FW_DBG1_8814B(v)) /* 2 REG_FW_DBG2_8814B */ #define BIT_SHIFT_FW_DBG2_8814B 0 #define BIT_MASK_FW_DBG2_8814B 0xffffffffL -#define BIT_FW_DBG2_8814B(x) (((x) & BIT_MASK_FW_DBG2_8814B) << BIT_SHIFT_FW_DBG2_8814B) -#define BIT_GET_FW_DBG2_8814B(x) (((x) >> BIT_SHIFT_FW_DBG2_8814B) & BIT_MASK_FW_DBG2_8814B) - - +#define BIT_FW_DBG2_8814B(x) \ + (((x) & BIT_MASK_FW_DBG2_8814B) << BIT_SHIFT_FW_DBG2_8814B) +#define BITS_FW_DBG2_8814B (BIT_MASK_FW_DBG2_8814B << BIT_SHIFT_FW_DBG2_8814B) +#define BIT_CLEAR_FW_DBG2_8814B(x) ((x) & (~BITS_FW_DBG2_8814B)) +#define BIT_GET_FW_DBG2_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG2_8814B) & BIT_MASK_FW_DBG2_8814B) +#define BIT_SET_FW_DBG2_8814B(x, v) \ + (BIT_CLEAR_FW_DBG2_8814B(x) | BIT_FW_DBG2_8814B(v)) /* 2 REG_FW_DBG3_8814B */ #define BIT_SHIFT_FW_DBG3_8814B 0 #define BIT_MASK_FW_DBG3_8814B 0xffffffffL -#define BIT_FW_DBG3_8814B(x) (((x) & BIT_MASK_FW_DBG3_8814B) << BIT_SHIFT_FW_DBG3_8814B) -#define BIT_GET_FW_DBG3_8814B(x) (((x) >> BIT_SHIFT_FW_DBG3_8814B) & BIT_MASK_FW_DBG3_8814B) - - +#define BIT_FW_DBG3_8814B(x) \ + (((x) & BIT_MASK_FW_DBG3_8814B) << BIT_SHIFT_FW_DBG3_8814B) +#define BITS_FW_DBG3_8814B (BIT_MASK_FW_DBG3_8814B << BIT_SHIFT_FW_DBG3_8814B) +#define BIT_CLEAR_FW_DBG3_8814B(x) ((x) & (~BITS_FW_DBG3_8814B)) +#define BIT_GET_FW_DBG3_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG3_8814B) & BIT_MASK_FW_DBG3_8814B) +#define BIT_SET_FW_DBG3_8814B(x, v) \ + (BIT_CLEAR_FW_DBG3_8814B(x) | BIT_FW_DBG3_8814B(v)) /* 2 REG_FW_DBG4_8814B */ #define BIT_SHIFT_FW_DBG4_8814B 0 #define BIT_MASK_FW_DBG4_8814B 0xffffffffL -#define BIT_FW_DBG4_8814B(x) (((x) & BIT_MASK_FW_DBG4_8814B) << BIT_SHIFT_FW_DBG4_8814B) -#define BIT_GET_FW_DBG4_8814B(x) (((x) >> BIT_SHIFT_FW_DBG4_8814B) & BIT_MASK_FW_DBG4_8814B) - - +#define BIT_FW_DBG4_8814B(x) \ + (((x) & BIT_MASK_FW_DBG4_8814B) << BIT_SHIFT_FW_DBG4_8814B) +#define BITS_FW_DBG4_8814B (BIT_MASK_FW_DBG4_8814B << BIT_SHIFT_FW_DBG4_8814B) +#define BIT_CLEAR_FW_DBG4_8814B(x) ((x) & (~BITS_FW_DBG4_8814B)) +#define BIT_GET_FW_DBG4_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG4_8814B) & BIT_MASK_FW_DBG4_8814B) +#define BIT_SET_FW_DBG4_8814B(x, v) \ + (BIT_CLEAR_FW_DBG4_8814B(x) | BIT_FW_DBG4_8814B(v)) /* 2 REG_FW_DBG5_8814B */ #define BIT_SHIFT_FW_DBG5_8814B 0 #define BIT_MASK_FW_DBG5_8814B 0xffffffffL -#define BIT_FW_DBG5_8814B(x) (((x) & BIT_MASK_FW_DBG5_8814B) << BIT_SHIFT_FW_DBG5_8814B) -#define BIT_GET_FW_DBG5_8814B(x) (((x) >> BIT_SHIFT_FW_DBG5_8814B) & BIT_MASK_FW_DBG5_8814B) - - +#define BIT_FW_DBG5_8814B(x) \ + (((x) & BIT_MASK_FW_DBG5_8814B) << BIT_SHIFT_FW_DBG5_8814B) +#define BITS_FW_DBG5_8814B (BIT_MASK_FW_DBG5_8814B << BIT_SHIFT_FW_DBG5_8814B) +#define BIT_CLEAR_FW_DBG5_8814B(x) ((x) & (~BITS_FW_DBG5_8814B)) +#define BIT_GET_FW_DBG5_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG5_8814B) & BIT_MASK_FW_DBG5_8814B) +#define BIT_SET_FW_DBG5_8814B(x, v) \ + (BIT_CLEAR_FW_DBG5_8814B(x) | BIT_FW_DBG5_8814B(v)) /* 2 REG_FW_DBG6_8814B */ #define BIT_SHIFT_FW_DBG6_8814B 0 #define BIT_MASK_FW_DBG6_8814B 0xffffffffL -#define BIT_FW_DBG6_8814B(x) (((x) & BIT_MASK_FW_DBG6_8814B) << BIT_SHIFT_FW_DBG6_8814B) -#define BIT_GET_FW_DBG6_8814B(x) (((x) >> BIT_SHIFT_FW_DBG6_8814B) & BIT_MASK_FW_DBG6_8814B) - - +#define BIT_FW_DBG6_8814B(x) \ + (((x) & BIT_MASK_FW_DBG6_8814B) << BIT_SHIFT_FW_DBG6_8814B) +#define BITS_FW_DBG6_8814B (BIT_MASK_FW_DBG6_8814B << BIT_SHIFT_FW_DBG6_8814B) +#define BIT_CLEAR_FW_DBG6_8814B(x) ((x) & (~BITS_FW_DBG6_8814B)) +#define BIT_GET_FW_DBG6_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG6_8814B) & BIT_MASK_FW_DBG6_8814B) +#define BIT_SET_FW_DBG6_8814B(x, v) \ + (BIT_CLEAR_FW_DBG6_8814B(x) | BIT_FW_DBG6_8814B(v)) /* 2 REG_FW_DBG7_8814B */ #define BIT_SHIFT_FW_DBG7_8814B 0 #define BIT_MASK_FW_DBG7_8814B 0xffffffffL -#define BIT_FW_DBG7_8814B(x) (((x) & BIT_MASK_FW_DBG7_8814B) << BIT_SHIFT_FW_DBG7_8814B) -#define BIT_GET_FW_DBG7_8814B(x) (((x) >> BIT_SHIFT_FW_DBG7_8814B) & BIT_MASK_FW_DBG7_8814B) - - +#define BIT_FW_DBG7_8814B(x) \ + (((x) & BIT_MASK_FW_DBG7_8814B) << BIT_SHIFT_FW_DBG7_8814B) +#define BITS_FW_DBG7_8814B (BIT_MASK_FW_DBG7_8814B << BIT_SHIFT_FW_DBG7_8814B) +#define BIT_CLEAR_FW_DBG7_8814B(x) ((x) & (~BITS_FW_DBG7_8814B)) +#define BIT_GET_FW_DBG7_8814B(x) \ + (((x) >> BIT_SHIFT_FW_DBG7_8814B) & BIT_MASK_FW_DBG7_8814B) +#define BIT_SET_FW_DBG7_8814B(x, v) \ + (BIT_CLEAR_FW_DBG7_8814B(x) | BIT_FW_DBG7_8814B(v)) /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_CR_8814B */ - -#define BIT_SHIFT_LBMODE_8814B 24 -#define BIT_MASK_LBMODE_8814B 0x1f -#define BIT_LBMODE_8814B(x) (((x) & BIT_MASK_LBMODE_8814B) << BIT_SHIFT_LBMODE_8814B) -#define BIT_GET_LBMODE_8814B(x) (((x) >> BIT_SHIFT_LBMODE_8814B) & BIT_MASK_LBMODE_8814B) - +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NETYPE1_8814B 18 -#define BIT_MASK_NETYPE1_8814B 0x3 -#define BIT_NETYPE1_8814B(x) (((x) & BIT_MASK_NETYPE1_8814B) << BIT_SHIFT_NETYPE1_8814B) -#define BIT_GET_NETYPE1_8814B(x) (((x) >> BIT_SHIFT_NETYPE1_8814B) & BIT_MASK_NETYPE1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NETYPE0_8814B 16 -#define BIT_MASK_NETYPE0_8814B 0x3 -#define BIT_NETYPE0_8814B(x) (((x) & BIT_MASK_NETYPE0_8814B) << BIT_SHIFT_NETYPE0_8814B) -#define BIT_GET_NETYPE0_8814B(x) (((x) >> BIT_SHIFT_NETYPE0_8814B) & BIT_MASK_NETYPE0_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_I2C_MAILBOX_EN_8814B BIT(12) -#define BIT_SHCUT_EN_8814B BIT(11) -#define BIT_32K_CAL_TMR_EN_8814B BIT(10) -#define BIT_MAC_SEC_EN_8814B BIT(9) -#define BIT_ENSWBCN_8814B BIT(8) -#define BIT_MACRXEN_8814B BIT(7) -#define BIT_MACTXEN_8814B BIT(6) -#define BIT_SCHEDULE_EN_8814B BIT(5) -#define BIT_PROTOCOL_EN_8814B BIT(4) -#define BIT_RXDMA_EN_8814B BIT(3) -#define BIT_TXDMA_EN_8814B BIT(2) -#define BIT_HCI_RXDMA_EN_8814B BIT(1) -#define BIT_HCI_TXDMA_EN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PKT_BUFF_ACCESS_CTRL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B 0 -#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B 0xff -#define BIT_PKT_BUFF_ACCESS_CTRL_8814B(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) -#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8814B(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TSF_CLK_STATE_8814B */ -#define BIT_TSF_CLK_STABLE_8814B BIT(15) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TXDMA_PQ_MAP_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_HIQ_MAP_8814B 14 -#define BIT_MASK_TXDMA_HIQ_MAP_8814B 0x3 -#define BIT_TXDMA_HIQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8814B) << BIT_SHIFT_TXDMA_HIQ_MAP_8814B) -#define BIT_GET_TXDMA_HIQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8814B) & BIT_MASK_TXDMA_HIQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_MGQ_MAP_8814B 12 -#define BIT_MASK_TXDMA_MGQ_MAP_8814B 0x3 -#define BIT_TXDMA_MGQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8814B) << BIT_SHIFT_TXDMA_MGQ_MAP_8814B) -#define BIT_GET_TXDMA_MGQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8814B) & BIT_MASK_TXDMA_MGQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_BKQ_MAP_8814B 10 -#define BIT_MASK_TXDMA_BKQ_MAP_8814B 0x3 -#define BIT_TXDMA_BKQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8814B) << BIT_SHIFT_TXDMA_BKQ_MAP_8814B) -#define BIT_GET_TXDMA_BKQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8814B) & BIT_MASK_TXDMA_BKQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_BEQ_MAP_8814B 8 -#define BIT_MASK_TXDMA_BEQ_MAP_8814B 0x3 -#define BIT_TXDMA_BEQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8814B) << BIT_SHIFT_TXDMA_BEQ_MAP_8814B) -#define BIT_GET_TXDMA_BEQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8814B) & BIT_MASK_TXDMA_BEQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_VIQ_MAP_8814B 6 -#define BIT_MASK_TXDMA_VIQ_MAP_8814B 0x3 -#define BIT_TXDMA_VIQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8814B) << BIT_SHIFT_TXDMA_VIQ_MAP_8814B) -#define BIT_GET_TXDMA_VIQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8814B) & BIT_MASK_TXDMA_VIQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXDMA_VOQ_MAP_8814B 4 -#define BIT_MASK_TXDMA_VOQ_MAP_8814B 0x3 -#define BIT_TXDMA_VOQ_MAP_8814B(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8814B) << BIT_SHIFT_TXDMA_VOQ_MAP_8814B) -#define BIT_GET_TXDMA_VOQ_MAP_8814B(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8814B) & BIT_MASK_TXDMA_VOQ_MAP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_RXDMA_AGG_EN_8814B BIT(2) -#define BIT_RXSHFT_EN_8814B BIT(1) -#define BIT_RXDMA_ARBBW_EN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TRXFF_BNDY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_RXFFOVFL_RSV_V2_8814B 8 -#define BIT_MASK_RXFFOVFL_RSV_V2_8814B 0xf -#define BIT_RXFFOVFL_RSV_V2_8814B(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8814B) << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) -#define BIT_GET_RXFFOVFL_RSV_V2_8814B(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) & BIT_MASK_RXFFOVFL_RSV_V2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXPKTBUF_PGBNDY_8814B 0 -#define BIT_MASK_TXPKTBUF_PGBNDY_8814B 0xff -#define BIT_TXPKTBUF_PGBNDY_8814B(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8814B) << BIT_SHIFT_TXPKTBUF_PGBNDY_8814B) -#define BIT_GET_TXPKTBUF_PGBNDY_8814B(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8814B) & BIT_MASK_TXPKTBUF_PGBNDY_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PTA_I2C_MBOX_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_I2C_M_STATUS_8814B 8 -#define BIT_MASK_I2C_M_STATUS_8814B 0xf -#define BIT_I2C_M_STATUS_8814B(x) (((x) & BIT_MASK_I2C_M_STATUS_8814B) << BIT_SHIFT_I2C_M_STATUS_8814B) -#define BIT_GET_I2C_M_STATUS_8814B(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8814B) & BIT_MASK_I2C_M_STATUS_8814B) +/* 2 REG_CR_8814B */ +#define BIT_SHIFT_LBMODE_8814B 24 +#define BIT_MASK_LBMODE_8814B 0x1f +#define BIT_LBMODE_8814B(x) \ + (((x) & BIT_MASK_LBMODE_8814B) << BIT_SHIFT_LBMODE_8814B) +#define BITS_LBMODE_8814B (BIT_MASK_LBMODE_8814B << BIT_SHIFT_LBMODE_8814B) +#define BIT_CLEAR_LBMODE_8814B(x) ((x) & (~BITS_LBMODE_8814B)) +#define BIT_GET_LBMODE_8814B(x) \ + (((x) >> BIT_SHIFT_LBMODE_8814B) & BIT_MASK_LBMODE_8814B) +#define BIT_SET_LBMODE_8814B(x, v) \ + (BIT_CLEAR_LBMODE_8814B(x) | BIT_LBMODE_8814B(v)) +#define BIT_SHIFT_NETYPE1_8814B 18 +#define BIT_MASK_NETYPE1_8814B 0x3 +#define BIT_NETYPE1_8814B(x) \ + (((x) & BIT_MASK_NETYPE1_8814B) << BIT_SHIFT_NETYPE1_8814B) +#define BITS_NETYPE1_8814B (BIT_MASK_NETYPE1_8814B << BIT_SHIFT_NETYPE1_8814B) +#define BIT_CLEAR_NETYPE1_8814B(x) ((x) & (~BITS_NETYPE1_8814B)) +#define BIT_GET_NETYPE1_8814B(x) \ + (((x) >> BIT_SHIFT_NETYPE1_8814B) & BIT_MASK_NETYPE1_8814B) +#define BIT_SET_NETYPE1_8814B(x, v) \ + (BIT_CLEAR_NETYPE1_8814B(x) | BIT_NETYPE1_8814B(v)) -#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B 4 -#define BIT_MASK_I2C_M_BUS_GNT_FW_8814B 0x7 -#define BIT_I2C_M_BUS_GNT_FW_8814B(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8814B) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) -#define BIT_GET_I2C_M_BUS_GNT_FW_8814B(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) & BIT_MASK_I2C_M_BUS_GNT_FW_8814B) +#define BIT_SHIFT_NETYPE0_8814B 16 +#define BIT_MASK_NETYPE0_8814B 0x3 +#define BIT_NETYPE0_8814B(x) \ + (((x) & BIT_MASK_NETYPE0_8814B) << BIT_SHIFT_NETYPE0_8814B) +#define BITS_NETYPE0_8814B (BIT_MASK_NETYPE0_8814B << BIT_SHIFT_NETYPE0_8814B) +#define BIT_CLEAR_NETYPE0_8814B(x) ((x) & (~BITS_NETYPE0_8814B)) +#define BIT_GET_NETYPE0_8814B(x) \ + (((x) >> BIT_SHIFT_NETYPE0_8814B) & BIT_MASK_NETYPE0_8814B) +#define BIT_SET_NETYPE0_8814B(x, v) \ + (BIT_CLEAR_NETYPE0_8814B(x) | BIT_NETYPE0_8814B(v)) + +#define BIT_COUNTER_STS_EN_8814B BIT(13) +#define BIT_I2C_MAILBOX_EN_8814B BIT(12) +#define BIT_SHCUT_EN_8814B BIT(11) +#define BIT_32K_CAL_TMR_EN_8814B BIT(10) +#define BIT_MAC_SEC_EN_8814B BIT(9) +#define BIT_ENSWBCN_8814B BIT(8) +#define BIT_MACRXEN_8814B BIT(7) +#define BIT_MACTXEN_8814B BIT(6) +#define BIT_SCHEDULE_EN_8814B BIT(5) +#define BIT_PROTOCOL_EN_8814B BIT(4) +#define BIT_RXDMA_EN_8814B BIT(3) +#define BIT_TXDMA_EN_8814B BIT(2) +#define BIT_HCI_RXDMA_EN_8814B BIT(1) +#define BIT_HCI_TXDMA_EN_8814B BIT(0) + +/* 2 REG_PG_SIZE_8814B */ + +#define BIT_SHIFT_DBG_FIFO_SEL_8814B 16 +#define BIT_MASK_DBG_FIFO_SEL_8814B 0xff +#define BIT_DBG_FIFO_SEL_8814B(x) \ + (((x) & BIT_MASK_DBG_FIFO_SEL_8814B) << BIT_SHIFT_DBG_FIFO_SEL_8814B) +#define BITS_DBG_FIFO_SEL_8814B \ + (BIT_MASK_DBG_FIFO_SEL_8814B << BIT_SHIFT_DBG_FIFO_SEL_8814B) +#define BIT_CLEAR_DBG_FIFO_SEL_8814B(x) ((x) & (~BITS_DBG_FIFO_SEL_8814B)) +#define BIT_GET_DBG_FIFO_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_DBG_FIFO_SEL_8814B) & BIT_MASK_DBG_FIFO_SEL_8814B) +#define BIT_SET_DBG_FIFO_SEL_8814B(x, v) \ + (BIT_CLEAR_DBG_FIFO_SEL_8814B(x) | BIT_DBG_FIFO_SEL_8814B(v)) + +/* 2 REG_PKT_BUFF_ACCESS_CTRL_8814B */ + +#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B 0 +#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B 0xff +#define BIT_PKT_BUFF_ACCESS_CTRL_8814B(x) \ + (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B) \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) +#define BITS_PKT_BUFF_ACCESS_CTRL_8814B \ + (BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) +#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8814B(x) \ + ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8814B)) +#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) & \ + BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B) +#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8814B(x, v) \ + (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8814B(x) | \ + BIT_PKT_BUFF_ACCESS_CTRL_8814B(v)) + +/* 2 REG_TSF_CLK_STATE_8814B */ +#define BIT_TSF_CLK_STABLE_8814B BIT(15) + +/* 2 REG_TXDMA_PQ_MAP_8814B */ + +#define BIT_SHIFT_TXDMA_H2C_MAP_8814B 16 +#define BIT_MASK_TXDMA_H2C_MAP_8814B 0x3 +#define BIT_TXDMA_H2C_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_H2C_MAP_8814B) << BIT_SHIFT_TXDMA_H2C_MAP_8814B) +#define BITS_TXDMA_H2C_MAP_8814B \ + (BIT_MASK_TXDMA_H2C_MAP_8814B << BIT_SHIFT_TXDMA_H2C_MAP_8814B) +#define BIT_CLEAR_TXDMA_H2C_MAP_8814B(x) ((x) & (~BITS_TXDMA_H2C_MAP_8814B)) +#define BIT_GET_TXDMA_H2C_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8814B) & BIT_MASK_TXDMA_H2C_MAP_8814B) +#define BIT_SET_TXDMA_H2C_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_H2C_MAP_8814B(x) | BIT_TXDMA_H2C_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_HIQ_MAP_8814B 14 +#define BIT_MASK_TXDMA_HIQ_MAP_8814B 0x3 +#define BIT_TXDMA_HIQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_8814B) << BIT_SHIFT_TXDMA_HIQ_MAP_8814B) +#define BITS_TXDMA_HIQ_MAP_8814B \ + (BIT_MASK_TXDMA_HIQ_MAP_8814B << BIT_SHIFT_TXDMA_HIQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_HIQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8814B)) +#define BIT_GET_TXDMA_HIQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8814B) & BIT_MASK_TXDMA_HIQ_MAP_8814B) +#define BIT_SET_TXDMA_HIQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_8814B(x) | BIT_TXDMA_HIQ_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_MGQ_MAP_8814B 12 +#define BIT_MASK_TXDMA_MGQ_MAP_8814B 0x3 +#define BIT_TXDMA_MGQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_8814B) << BIT_SHIFT_TXDMA_MGQ_MAP_8814B) +#define BITS_TXDMA_MGQ_MAP_8814B \ + (BIT_MASK_TXDMA_MGQ_MAP_8814B << BIT_SHIFT_TXDMA_MGQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_MGQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8814B)) +#define BIT_GET_TXDMA_MGQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8814B) & BIT_MASK_TXDMA_MGQ_MAP_8814B) +#define BIT_SET_TXDMA_MGQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_8814B(x) | BIT_TXDMA_MGQ_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_BKQ_MAP_8814B 10 +#define BIT_MASK_TXDMA_BKQ_MAP_8814B 0x3 +#define BIT_TXDMA_BKQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_8814B) << BIT_SHIFT_TXDMA_BKQ_MAP_8814B) +#define BITS_TXDMA_BKQ_MAP_8814B \ + (BIT_MASK_TXDMA_BKQ_MAP_8814B << BIT_SHIFT_TXDMA_BKQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_BKQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8814B)) +#define BIT_GET_TXDMA_BKQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8814B) & BIT_MASK_TXDMA_BKQ_MAP_8814B) +#define BIT_SET_TXDMA_BKQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_8814B(x) | BIT_TXDMA_BKQ_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_BEQ_MAP_8814B 8 +#define BIT_MASK_TXDMA_BEQ_MAP_8814B 0x3 +#define BIT_TXDMA_BEQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_8814B) << BIT_SHIFT_TXDMA_BEQ_MAP_8814B) +#define BITS_TXDMA_BEQ_MAP_8814B \ + (BIT_MASK_TXDMA_BEQ_MAP_8814B << BIT_SHIFT_TXDMA_BEQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_BEQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8814B)) +#define BIT_GET_TXDMA_BEQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8814B) & BIT_MASK_TXDMA_BEQ_MAP_8814B) +#define BIT_SET_TXDMA_BEQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_8814B(x) | BIT_TXDMA_BEQ_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_VIQ_MAP_8814B 6 +#define BIT_MASK_TXDMA_VIQ_MAP_8814B 0x3 +#define BIT_TXDMA_VIQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_8814B) << BIT_SHIFT_TXDMA_VIQ_MAP_8814B) +#define BITS_TXDMA_VIQ_MAP_8814B \ + (BIT_MASK_TXDMA_VIQ_MAP_8814B << BIT_SHIFT_TXDMA_VIQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_VIQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8814B)) +#define BIT_GET_TXDMA_VIQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8814B) & BIT_MASK_TXDMA_VIQ_MAP_8814B) +#define BIT_SET_TXDMA_VIQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_8814B(x) | BIT_TXDMA_VIQ_MAP_8814B(v)) + +#define BIT_SHIFT_TXDMA_VOQ_MAP_8814B 4 +#define BIT_MASK_TXDMA_VOQ_MAP_8814B 0x3 +#define BIT_TXDMA_VOQ_MAP_8814B(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_8814B) << BIT_SHIFT_TXDMA_VOQ_MAP_8814B) +#define BITS_TXDMA_VOQ_MAP_8814B \ + (BIT_MASK_TXDMA_VOQ_MAP_8814B << BIT_SHIFT_TXDMA_VOQ_MAP_8814B) +#define BIT_CLEAR_TXDMA_VOQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8814B)) +#define BIT_GET_TXDMA_VOQ_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8814B) & BIT_MASK_TXDMA_VOQ_MAP_8814B) +#define BIT_SET_TXDMA_VOQ_MAP_8814B(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_8814B(x) | BIT_TXDMA_VOQ_MAP_8814B(v)) + +#define BIT_RXDMA_AGG_EN_8814B BIT(2) +#define BIT_RXSHFT_EN_8814B BIT(1) +#define BIT_RXDMA_ARBBW_EN_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_TRXFF_BNDY_8814B */ + +#define BIT_SHIFT_FWFFOVFL_RSV_8814B 16 +#define BIT_MASK_FWFFOVFL_RSV_8814B 0xf +#define BIT_FWFFOVFL_RSV_8814B(x) \ + (((x) & BIT_MASK_FWFFOVFL_RSV_8814B) << BIT_SHIFT_FWFFOVFL_RSV_8814B) +#define BITS_FWFFOVFL_RSV_8814B \ + (BIT_MASK_FWFFOVFL_RSV_8814B << BIT_SHIFT_FWFFOVFL_RSV_8814B) +#define BIT_CLEAR_FWFFOVFL_RSV_8814B(x) ((x) & (~BITS_FWFFOVFL_RSV_8814B)) +#define BIT_GET_FWFFOVFL_RSV_8814B(x) \ + (((x) >> BIT_SHIFT_FWFFOVFL_RSV_8814B) & BIT_MASK_FWFFOVFL_RSV_8814B) +#define BIT_SET_FWFFOVFL_RSV_8814B(x, v) \ + (BIT_CLEAR_FWFFOVFL_RSV_8814B(x) | BIT_FWFFOVFL_RSV_8814B(v)) + +#define BIT_SHIFT_RXFFOVFL_RSV_V2_8814B 8 +#define BIT_MASK_RXFFOVFL_RSV_V2_8814B 0xf +#define BIT_RXFFOVFL_RSV_V2_8814B(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8814B) \ + << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) +#define BITS_RXFFOVFL_RSV_V2_8814B \ + (BIT_MASK_RXFFOVFL_RSV_V2_8814B << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) +#define BIT_CLEAR_RXFFOVFL_RSV_V2_8814B(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8814B)) +#define BIT_GET_RXFFOVFL_RSV_V2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) & \ + BIT_MASK_RXFFOVFL_RSV_V2_8814B) +#define BIT_SET_RXFFOVFL_RSV_V2_8814B(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2_8814B(x) | BIT_RXFFOVFL_RSV_V2_8814B(v)) + +/* 2 REG_PTA_I2C_MBOX_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_I2C_M_STATUS_8814B 8 +#define BIT_MASK_I2C_M_STATUS_8814B 0xf +#define BIT_I2C_M_STATUS_8814B(x) \ + (((x) & BIT_MASK_I2C_M_STATUS_8814B) << BIT_SHIFT_I2C_M_STATUS_8814B) +#define BITS_I2C_M_STATUS_8814B \ + (BIT_MASK_I2C_M_STATUS_8814B << BIT_SHIFT_I2C_M_STATUS_8814B) +#define BIT_CLEAR_I2C_M_STATUS_8814B(x) ((x) & (~BITS_I2C_M_STATUS_8814B)) +#define BIT_GET_I2C_M_STATUS_8814B(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS_8814B) & BIT_MASK_I2C_M_STATUS_8814B) +#define BIT_SET_I2C_M_STATUS_8814B(x, v) \ + (BIT_CLEAR_I2C_M_STATUS_8814B(x) | BIT_I2C_M_STATUS_8814B(v)) +#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B 4 +#define BIT_MASK_I2C_M_BUS_GNT_FW_8814B 0x7 +#define BIT_I2C_M_BUS_GNT_FW_8814B(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8814B) \ + << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) +#define BITS_I2C_M_BUS_GNT_FW_8814B \ + (BIT_MASK_I2C_M_BUS_GNT_FW_8814B << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8814B(x) \ + ((x) & (~BITS_I2C_M_BUS_GNT_FW_8814B)) +#define BIT_GET_I2C_M_BUS_GNT_FW_8814B(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) & \ + BIT_MASK_I2C_M_BUS_GNT_FW_8814B) +#define BIT_SET_I2C_M_BUS_GNT_FW_8814B(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW_8814B(x) | BIT_I2C_M_BUS_GNT_FW_8814B(v)) #define BIT_I2C_M_GNT_FW_8814B BIT(3) #define BIT_SHIFT_I2C_M_SPEED_8814B 1 #define BIT_MASK_I2C_M_SPEED_8814B 0x3 -#define BIT_I2C_M_SPEED_8814B(x) (((x) & BIT_MASK_I2C_M_SPEED_8814B) << BIT_SHIFT_I2C_M_SPEED_8814B) -#define BIT_GET_I2C_M_SPEED_8814B(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8814B) & BIT_MASK_I2C_M_SPEED_8814B) - +#define BIT_I2C_M_SPEED_8814B(x) \ + (((x) & BIT_MASK_I2C_M_SPEED_8814B) << BIT_SHIFT_I2C_M_SPEED_8814B) +#define BITS_I2C_M_SPEED_8814B \ + (BIT_MASK_I2C_M_SPEED_8814B << BIT_SHIFT_I2C_M_SPEED_8814B) +#define BIT_CLEAR_I2C_M_SPEED_8814B(x) ((x) & (~BITS_I2C_M_SPEED_8814B)) +#define BIT_GET_I2C_M_SPEED_8814B(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED_8814B) & BIT_MASK_I2C_M_SPEED_8814B) +#define BIT_SET_I2C_M_SPEED_8814B(x, v) \ + (BIT_CLEAR_I2C_M_SPEED_8814B(x) | BIT_I2C_M_SPEED_8814B(v)) #define BIT_I2C_M_UNLOCK_8814B BIT(0) @@ -2209,12 +4372,20 @@ #define BIT_SHIFT_RXFF0_BNDY_V2_8814B 0 #define BIT_MASK_RXFF0_BNDY_V2_8814B 0x3ffff -#define BIT_RXFF0_BNDY_V2_8814B(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8814B) << BIT_SHIFT_RXFF0_BNDY_V2_8814B) -#define BIT_GET_RXFF0_BNDY_V2_8814B(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8814B) & BIT_MASK_RXFF0_BNDY_V2_8814B) - - +#define BIT_RXFF0_BNDY_V2_8814B(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2_8814B) << BIT_SHIFT_RXFF0_BNDY_V2_8814B) +#define BITS_RXFF0_BNDY_V2_8814B \ + (BIT_MASK_RXFF0_BNDY_V2_8814B << BIT_SHIFT_RXFF0_BNDY_V2_8814B) +#define BIT_CLEAR_RXFF0_BNDY_V2_8814B(x) ((x) & (~BITS_RXFF0_BNDY_V2_8814B)) +#define BIT_GET_RXFF0_BNDY_V2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8814B) & BIT_MASK_RXFF0_BNDY_V2_8814B) +#define BIT_SET_RXFF0_BNDY_V2_8814B(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2_8814B(x) | BIT_RXFF0_BNDY_V2_8814B(v)) /* 2 REG_FE1IMR_8814B */ +#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_EN_8814B BIT(31) +#define BIT_FWFF_FULL_INT_EN_8814B BIT(30) +#define BIT_BB_STOP_RX_INT_EN_8814B BIT(29) #define BIT_FS_RXDMA2_DONE_INT_EN_8814B BIT(28) #define BIT_FS_RXDONE3_INT_EN_8814B BIT(27) #define BIT_FS_RXDONE2_INT_EN_8814B BIT(26) @@ -2230,11 +4401,12 @@ #define BIT_FS_RXDONE_INT_EN_8814B BIT(16) #define BIT_FS_WWLAN_INT_EN_8814B BIT(15) #define BIT_FS_SOUND_DONE_INT_EN_8814B BIT(14) -#define BIT_FS_LP_STBY_INT_EN_8814B BIT(13) #define BIT_FS_TRL_MTR_INT_EN_8814B BIT(12) #define BIT_FS_BF1_PRETO_INT_EN_8814B BIT(11) #define BIT_FS_BF0_PRETO_INT_EN_8814B BIT(10) #define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8814B BIT(9) +#define BIT_PRETX_ERRHLD_INT_EN_8814B BIT(8) +#define BIT_FS_GTRD_INT_EN_8814B BIT(7) #define BIT_FS_LTE_COEX_EN_8814B BIT(6) #define BIT_FS_WLACTOFF_INT_EN_8814B BIT(5) #define BIT_FS_WLACTON_INT_EN_8814B BIT(4) @@ -2244,8 +4416,11 @@ #define BIT_FS_RPC_O_T_INT_EN_V1_8814B BIT(0) /* 2 REG_FE1ISR_8814B */ +#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_8814B BIT(31) +#define BIT_FWFF_FULL_INT_8814B BIT(30) +#define BIT_BB_STOP_RX_INT_8814B BIT(29) #define BIT_FS_RXDMA2_DONE_INT_8814B BIT(28) -#define BIT_FS_RXDONE3_INT_8814B BIT(27) +#define BIT_FS_RXDONE3_INT_INT_8814B BIT(27) #define BIT_FS_RXDONE2_INT_8814B BIT(26) #define BIT_FS_RX_BCN_P4_INT_8814B BIT(25) #define BIT_FS_RX_BCN_P3_INT_8814B BIT(24) @@ -2259,15 +4434,16 @@ #define BIT_FS_RXDONE_INT_8814B BIT(16) #define BIT_FS_WWLAN_INT_8814B BIT(15) #define BIT_FS_SOUND_DONE_INT_8814B BIT(14) -#define BIT_FS_LP_STBY_INT_8814B BIT(13) #define BIT_FS_TRL_MTR_INT_8814B BIT(12) #define BIT_FS_BF1_PRETO_INT_8814B BIT(11) #define BIT_FS_BF0_PRETO_INT_8814B BIT(10) #define BIT_FS_PTCL_RELEASE_MACID_INT_8814B BIT(9) +#define BIT_PRETX_ERRHLD_INT_8814B BIT(8) +#define BIT_SND_RDY_INT_8814B BIT(7) #define BIT_FS_LTE_COEX_INT_8814B BIT(6) #define BIT_FS_WLACTOFF_INT_8814B BIT(5) #define BIT_FS_WLACTON_INT_8814B BIT(4) -#define BIT_FS_BCN_RX_INT_INT_8814B BIT(3) +#define BIT_BT_CMD_INT_8814B BIT(3) #define BIT_FS_MAILBOX_TO_I2C_INT_8814B BIT(2) #define BIT_FS_TRPC_TO_INT_8814B BIT(1) #define BIT_FS_RPC_O_T_INT_8814B BIT(0) @@ -2279,10 +4455,15 @@ #define BIT_SHIFT_CPWM_MOD_8814B 24 #define BIT_MASK_CPWM_MOD_8814B 0x7f -#define BIT_CPWM_MOD_8814B(x) (((x) & BIT_MASK_CPWM_MOD_8814B) << BIT_SHIFT_CPWM_MOD_8814B) -#define BIT_GET_CPWM_MOD_8814B(x) (((x) >> BIT_SHIFT_CPWM_MOD_8814B) & BIT_MASK_CPWM_MOD_8814B) - - +#define BIT_CPWM_MOD_8814B(x) \ + (((x) & BIT_MASK_CPWM_MOD_8814B) << BIT_SHIFT_CPWM_MOD_8814B) +#define BITS_CPWM_MOD_8814B \ + (BIT_MASK_CPWM_MOD_8814B << BIT_SHIFT_CPWM_MOD_8814B) +#define BIT_CLEAR_CPWM_MOD_8814B(x) ((x) & (~BITS_CPWM_MOD_8814B)) +#define BIT_GET_CPWM_MOD_8814B(x) \ + (((x) >> BIT_SHIFT_CPWM_MOD_8814B) & BIT_MASK_CPWM_MOD_8814B) +#define BIT_SET_CPWM_MOD_8814B(x, v) \ + (BIT_CLEAR_CPWM_MOD_8814B(x) | BIT_CPWM_MOD_8814B(v)) /* 2 REG_FWIMR_8814B */ #define BIT_FS_TXBCNOK_MB7_INT_EN_8814B BIT(31) @@ -2305,8 +4486,7 @@ #define BIT_SIFS_OVERSPEC_INT_EN_8814B BIT(14) #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8814B BIT(13) #define BIT_FS_MGNTQFF_TO_INT_EN_8814B BIT(12) -#define BIT_FS_DDMA1_LP_INT_EN_8814B BIT(11) -#define BIT_FS_DDMA1_HP_INT_EN_8814B BIT(10) +#define BIT_FS_CPUMGQ_ERR_INT_EN_8814B BIT(11) #define BIT_FS_DDMA0_LP_INT_EN_8814B BIT(9) #define BIT_FS_DDMA0_HP_INT_EN_8814B BIT(8) #define BIT_FS_TRXRPT_INT_EN_8814B BIT(7) @@ -2339,8 +4519,8 @@ #define BIT_SIFS_OVERSPEC_INT_8814B BIT(14) #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8814B BIT(13) #define BIT_FS_MGNTQFF_TO_INT_8814B BIT(12) -#define BIT_FS_DDMA1_LP_INT_8814B BIT(11) -#define BIT_FS_DDMA1_HP_INT_8814B BIT(10) +#define BIT_FS_CPUMGQ_ERR_INT_8814B BIT(11) +#define BIT_FWCMD_PKTIN_INT_8814B BIT(10) #define BIT_FS_DDMA0_LP_INT_8814B BIT(9) #define BIT_FS_DDMA0_HP_INT_8814B BIT(8) #define BIT_FS_TRXRPT_INT_8814B BIT(7) @@ -2364,6 +4544,10 @@ #define BIT_FS_PS_TIMEOUT2_EN_8814B BIT(15) #define BIT_FS_PS_TIMEOUT1_EN_8814B BIT(14) #define BIT_FS_PS_TIMEOUT0_EN_8814B BIT(13) +#define BIT_FS_GTINT12_EN_8814B BIT(12) +#define BIT_FS_GTINT11_EN_8814B BIT(11) +#define BIT_FS_GTINT10_EN_8814B BIT(10) +#define BIT_FS_GTINT9_EN_8814B BIT(9) #define BIT_FS_GTINT8_EN_8814B BIT(8) #define BIT_FS_GTINT7_EN_8814B BIT(7) #define BIT_FS_GTINT6_EN_8814B BIT(6) @@ -2375,17 +4559,24 @@ #define BIT_FS_GTINT0_EN_8814B BIT(0) /* 2 REG_FTISR_8814B */ -#define BIT_PS_TIMER_C_EARLY__INT_8814B BIT(23) -#define BIT_PS_TIMER_B_EARLY__INT_8814B BIT(22) -#define BIT_PS_TIMER_A_EARLY__INT_8814B BIT(21) +#define BIT_PS_TIMER_5_EARLY__INT_8814B BIT(26) +#define BIT_PS_TIMER_4_EARLY__INT_8814B BIT(25) +#define BIT_PS_TIMER_3_EARLY__INT_8814B BIT(24) +#define BIT_PS_TIMER_2_EARLY__INT_8814B BIT(23) +#define BIT_PS_TIMER_1_EARLY__INT_8814B BIT(22) +#define BIT_PS_TIMER_0_EARLY__INT_8814B BIT(21) #define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8814B BIT(20) -#define BIT_PS_TIMER_C_INT_8814B BIT(19) -#define BIT_PS_TIMER_B_INT_8814B BIT(18) -#define BIT_PS_TIMER_A_INT_8814B BIT(17) +#define BIT_PS_TIMER_5_INT_8814B BIT(19) +#define BIT_PS_TIMER_4_INT_8814B BIT(18) +#define BIT_PS_TIMER_3_INT_8814B BIT(17) #define BIT_CPUMGQ_TX_TIMER_INT_8814B BIT(16) -#define BIT_FS_PS_TIMEOUT2_INT_8814B BIT(15) -#define BIT_FS_PS_TIMEOUT1_INT_8814B BIT(14) -#define BIT_FS_PS_TIMEOUT0_INT_8814B BIT(13) +#define BIT_PS_TIMER_2_INT_8814B BIT(15) +#define BIT_PS_TIMER_1_INT_8814B BIT(14) +#define BIT_PS_TIMER_0_INT_8814B BIT(13) +#define BIT_FS_GTINT12_INT_8814B BIT(12) +#define BIT_FS_GTINT11_INT_8814B BIT(11) +#define BIT_FS_GTINT10_INT_8814B BIT(10) +#define BIT_FS_GTINT9_INT_8814B BIT(9) #define BIT_FS_GTINT8_INT_8814B BIT(8) #define BIT_FS_GTINT7_INT_8814B BIT(7) #define BIT_FS_GTINT6_INT_8814B BIT(6) @@ -2400,9 +4591,17 @@ #define BIT_SHIFT_PKTBUF_WRITE_EN_8814B 24 #define BIT_MASK_PKTBUF_WRITE_EN_8814B 0xff -#define BIT_PKTBUF_WRITE_EN_8814B(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8814B) << BIT_SHIFT_PKTBUF_WRITE_EN_8814B) -#define BIT_GET_PKTBUF_WRITE_EN_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8814B) & BIT_MASK_PKTBUF_WRITE_EN_8814B) - +#define BIT_PKTBUF_WRITE_EN_8814B(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN_8814B) \ + << BIT_SHIFT_PKTBUF_WRITE_EN_8814B) +#define BITS_PKTBUF_WRITE_EN_8814B \ + (BIT_MASK_PKTBUF_WRITE_EN_8814B << BIT_SHIFT_PKTBUF_WRITE_EN_8814B) +#define BIT_CLEAR_PKTBUF_WRITE_EN_8814B(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8814B)) +#define BIT_GET_PKTBUF_WRITE_EN_8814B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8814B) & \ + BIT_MASK_PKTBUF_WRITE_EN_8814B) +#define BIT_SET_PKTBUF_WRITE_EN_8814B(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN_8814B(x) | BIT_PKTBUF_WRITE_EN_8814B(v)) #define BIT_TXRPTBUF_DBG_8814B BIT(23) @@ -2412,45 +4611,81 @@ #define BIT_SHIFT_PKTBUF_DBG_ADDR_8814B 0 #define BIT_MASK_PKTBUF_DBG_ADDR_8814B 0x1fff -#define BIT_PKTBUF_DBG_ADDR_8814B(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8814B) << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) -#define BIT_GET_PKTBUF_DBG_ADDR_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) & BIT_MASK_PKTBUF_DBG_ADDR_8814B) - - +#define BIT_PKTBUF_DBG_ADDR_8814B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8814B) \ + << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) +#define BITS_PKTBUF_DBG_ADDR_8814B \ + (BIT_MASK_PKTBUF_DBG_ADDR_8814B << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) +#define BIT_CLEAR_PKTBUF_DBG_ADDR_8814B(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8814B)) +#define BIT_GET_PKTBUF_DBG_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) & \ + BIT_MASK_PKTBUF_DBG_ADDR_8814B) +#define BIT_SET_PKTBUF_DBG_ADDR_8814B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR_8814B(x) | BIT_PKTBUF_DBG_ADDR_8814B(v)) /* 2 REG_PKTBUF_DBG_DATA_L_8814B */ #define BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B 0 #define BIT_MASK_PKTBUF_DBG_DATA_L_8814B 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_L_8814B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8814B) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) -#define BIT_GET_PKTBUF_DBG_DATA_L_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) & BIT_MASK_PKTBUF_DBG_DATA_L_8814B) - - +#define BIT_PKTBUF_DBG_DATA_L_8814B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8814B) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) +#define BITS_PKTBUF_DBG_DATA_L_8814B \ + (BIT_MASK_PKTBUF_DBG_DATA_L_8814B << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8814B(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_L_8814B)) +#define BIT_GET_PKTBUF_DBG_DATA_L_8814B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) & \ + BIT_MASK_PKTBUF_DBG_DATA_L_8814B) +#define BIT_SET_PKTBUF_DBG_DATA_L_8814B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L_8814B(x) | BIT_PKTBUF_DBG_DATA_L_8814B(v)) /* 2 REG_PKTBUF_DBG_DATA_H_8814B */ #define BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B 0 #define BIT_MASK_PKTBUF_DBG_DATA_H_8814B 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_H_8814B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8814B) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) -#define BIT_GET_PKTBUF_DBG_DATA_H_8814B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) & BIT_MASK_PKTBUF_DBG_DATA_H_8814B) - - +#define BIT_PKTBUF_DBG_DATA_H_8814B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8814B) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) +#define BITS_PKTBUF_DBG_DATA_H_8814B \ + (BIT_MASK_PKTBUF_DBG_DATA_H_8814B << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8814B(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_H_8814B)) +#define BIT_GET_PKTBUF_DBG_DATA_H_8814B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) & \ + BIT_MASK_PKTBUF_DBG_DATA_H_8814B) +#define BIT_SET_PKTBUF_DBG_DATA_H_8814B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H_8814B(x) | BIT_PKTBUF_DBG_DATA_H_8814B(v)) /* 2 REG_CPWM2_8814B */ #define BIT_SHIFT_L0S_TO_RCVY_NUM_8814B 16 #define BIT_MASK_L0S_TO_RCVY_NUM_8814B 0xff -#define BIT_L0S_TO_RCVY_NUM_8814B(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8814B) << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) -#define BIT_GET_L0S_TO_RCVY_NUM_8814B(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) & BIT_MASK_L0S_TO_RCVY_NUM_8814B) - +#define BIT_L0S_TO_RCVY_NUM_8814B(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8814B) \ + << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) +#define BITS_L0S_TO_RCVY_NUM_8814B \ + (BIT_MASK_L0S_TO_RCVY_NUM_8814B << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) +#define BIT_CLEAR_L0S_TO_RCVY_NUM_8814B(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8814B)) +#define BIT_GET_L0S_TO_RCVY_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) & \ + BIT_MASK_L0S_TO_RCVY_NUM_8814B) +#define BIT_SET_L0S_TO_RCVY_NUM_8814B(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM_8814B(x) | BIT_L0S_TO_RCVY_NUM_8814B(v)) #define BIT_CPWM2_TOGGLING_8814B BIT(15) #define BIT_SHIFT_CPWM2_MOD_8814B 0 #define BIT_MASK_CPWM2_MOD_8814B 0x7fff -#define BIT_CPWM2_MOD_8814B(x) (((x) & BIT_MASK_CPWM2_MOD_8814B) << BIT_SHIFT_CPWM2_MOD_8814B) -#define BIT_GET_CPWM2_MOD_8814B(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8814B) & BIT_MASK_CPWM2_MOD_8814B) - - +#define BIT_CPWM2_MOD_8814B(x) \ + (((x) & BIT_MASK_CPWM2_MOD_8814B) << BIT_SHIFT_CPWM2_MOD_8814B) +#define BITS_CPWM2_MOD_8814B \ + (BIT_MASK_CPWM2_MOD_8814B << BIT_SHIFT_CPWM2_MOD_8814B) +#define BIT_CLEAR_CPWM2_MOD_8814B(x) ((x) & (~BITS_CPWM2_MOD_8814B)) +#define BIT_GET_CPWM2_MOD_8814B(x) \ + (((x) >> BIT_SHIFT_CPWM2_MOD_8814B) & BIT_MASK_CPWM2_MOD_8814B) +#define BIT_SET_CPWM2_MOD_8814B(x, v) \ + (BIT_CLEAR_CPWM2_MOD_8814B(x) | BIT_CPWM2_MOD_8814B(v)) /* 2 REG_TC0_CTRL_8814B */ #define BIT_TC0INT_EN_8814B BIT(26) @@ -2459,10 +4694,14 @@ #define BIT_SHIFT_TC0DATA_8814B 0 #define BIT_MASK_TC0DATA_8814B 0xffffff -#define BIT_TC0DATA_8814B(x) (((x) & BIT_MASK_TC0DATA_8814B) << BIT_SHIFT_TC0DATA_8814B) -#define BIT_GET_TC0DATA_8814B(x) (((x) >> BIT_SHIFT_TC0DATA_8814B) & BIT_MASK_TC0DATA_8814B) - - +#define BIT_TC0DATA_8814B(x) \ + (((x) & BIT_MASK_TC0DATA_8814B) << BIT_SHIFT_TC0DATA_8814B) +#define BITS_TC0DATA_8814B (BIT_MASK_TC0DATA_8814B << BIT_SHIFT_TC0DATA_8814B) +#define BIT_CLEAR_TC0DATA_8814B(x) ((x) & (~BITS_TC0DATA_8814B)) +#define BIT_GET_TC0DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC0DATA_8814B) & BIT_MASK_TC0DATA_8814B) +#define BIT_SET_TC0DATA_8814B(x, v) \ + (BIT_CLEAR_TC0DATA_8814B(x) | BIT_TC0DATA_8814B(v)) /* 2 REG_TC1_CTRL_8814B */ #define BIT_TC1INT_EN_8814B BIT(26) @@ -2471,10 +4710,14 @@ #define BIT_SHIFT_TC1DATA_8814B 0 #define BIT_MASK_TC1DATA_8814B 0xffffff -#define BIT_TC1DATA_8814B(x) (((x) & BIT_MASK_TC1DATA_8814B) << BIT_SHIFT_TC1DATA_8814B) -#define BIT_GET_TC1DATA_8814B(x) (((x) >> BIT_SHIFT_TC1DATA_8814B) & BIT_MASK_TC1DATA_8814B) - - +#define BIT_TC1DATA_8814B(x) \ + (((x) & BIT_MASK_TC1DATA_8814B) << BIT_SHIFT_TC1DATA_8814B) +#define BITS_TC1DATA_8814B (BIT_MASK_TC1DATA_8814B << BIT_SHIFT_TC1DATA_8814B) +#define BIT_CLEAR_TC1DATA_8814B(x) ((x) & (~BITS_TC1DATA_8814B)) +#define BIT_GET_TC1DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC1DATA_8814B) & BIT_MASK_TC1DATA_8814B) +#define BIT_SET_TC1DATA_8814B(x, v) \ + (BIT_CLEAR_TC1DATA_8814B(x) | BIT_TC1DATA_8814B(v)) /* 2 REG_TC2_CTRL_8814B */ #define BIT_TC2INT_EN_8814B BIT(26) @@ -2483,10 +4726,14 @@ #define BIT_SHIFT_TC2DATA_8814B 0 #define BIT_MASK_TC2DATA_8814B 0xffffff -#define BIT_TC2DATA_8814B(x) (((x) & BIT_MASK_TC2DATA_8814B) << BIT_SHIFT_TC2DATA_8814B) -#define BIT_GET_TC2DATA_8814B(x) (((x) >> BIT_SHIFT_TC2DATA_8814B) & BIT_MASK_TC2DATA_8814B) - - +#define BIT_TC2DATA_8814B(x) \ + (((x) & BIT_MASK_TC2DATA_8814B) << BIT_SHIFT_TC2DATA_8814B) +#define BITS_TC2DATA_8814B (BIT_MASK_TC2DATA_8814B << BIT_SHIFT_TC2DATA_8814B) +#define BIT_CLEAR_TC2DATA_8814B(x) ((x) & (~BITS_TC2DATA_8814B)) +#define BIT_GET_TC2DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC2DATA_8814B) & BIT_MASK_TC2DATA_8814B) +#define BIT_SET_TC2DATA_8814B(x, v) \ + (BIT_CLEAR_TC2DATA_8814B(x) | BIT_TC2DATA_8814B(v)) /* 2 REG_TC3_CTRL_8814B */ #define BIT_TC3INT_EN_8814B BIT(26) @@ -2495,10 +4742,14 @@ #define BIT_SHIFT_TC3DATA_8814B 0 #define BIT_MASK_TC3DATA_8814B 0xffffff -#define BIT_TC3DATA_8814B(x) (((x) & BIT_MASK_TC3DATA_8814B) << BIT_SHIFT_TC3DATA_8814B) -#define BIT_GET_TC3DATA_8814B(x) (((x) >> BIT_SHIFT_TC3DATA_8814B) & BIT_MASK_TC3DATA_8814B) - - +#define BIT_TC3DATA_8814B(x) \ + (((x) & BIT_MASK_TC3DATA_8814B) << BIT_SHIFT_TC3DATA_8814B) +#define BITS_TC3DATA_8814B (BIT_MASK_TC3DATA_8814B << BIT_SHIFT_TC3DATA_8814B) +#define BIT_CLEAR_TC3DATA_8814B(x) ((x) & (~BITS_TC3DATA_8814B)) +#define BIT_GET_TC3DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC3DATA_8814B) & BIT_MASK_TC3DATA_8814B) +#define BIT_SET_TC3DATA_8814B(x, v) \ + (BIT_CLEAR_TC3DATA_8814B(x) | BIT_TC3DATA_8814B(v)) /* 2 REG_TC4_CTRL_8814B */ #define BIT_TC4INT_EN_8814B BIT(26) @@ -2507,19 +4758,28 @@ #define BIT_SHIFT_TC4DATA_8814B 0 #define BIT_MASK_TC4DATA_8814B 0xffffff -#define BIT_TC4DATA_8814B(x) (((x) & BIT_MASK_TC4DATA_8814B) << BIT_SHIFT_TC4DATA_8814B) -#define BIT_GET_TC4DATA_8814B(x) (((x) >> BIT_SHIFT_TC4DATA_8814B) & BIT_MASK_TC4DATA_8814B) - - +#define BIT_TC4DATA_8814B(x) \ + (((x) & BIT_MASK_TC4DATA_8814B) << BIT_SHIFT_TC4DATA_8814B) +#define BITS_TC4DATA_8814B (BIT_MASK_TC4DATA_8814B << BIT_SHIFT_TC4DATA_8814B) +#define BIT_CLEAR_TC4DATA_8814B(x) ((x) & (~BITS_TC4DATA_8814B)) +#define BIT_GET_TC4DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC4DATA_8814B) & BIT_MASK_TC4DATA_8814B) +#define BIT_SET_TC4DATA_8814B(x, v) \ + (BIT_CLEAR_TC4DATA_8814B(x) | BIT_TC4DATA_8814B(v)) /* 2 REG_TCUNIT_BASE_8814B */ #define BIT_SHIFT_TCUNIT_BASE_8814B 0 #define BIT_MASK_TCUNIT_BASE_8814B 0x3fff -#define BIT_TCUNIT_BASE_8814B(x) (((x) & BIT_MASK_TCUNIT_BASE_8814B) << BIT_SHIFT_TCUNIT_BASE_8814B) -#define BIT_GET_TCUNIT_BASE_8814B(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8814B) & BIT_MASK_TCUNIT_BASE_8814B) - - +#define BIT_TCUNIT_BASE_8814B(x) \ + (((x) & BIT_MASK_TCUNIT_BASE_8814B) << BIT_SHIFT_TCUNIT_BASE_8814B) +#define BITS_TCUNIT_BASE_8814B \ + (BIT_MASK_TCUNIT_BASE_8814B << BIT_SHIFT_TCUNIT_BASE_8814B) +#define BIT_CLEAR_TCUNIT_BASE_8814B(x) ((x) & (~BITS_TCUNIT_BASE_8814B)) +#define BIT_GET_TCUNIT_BASE_8814B(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE_8814B) & BIT_MASK_TCUNIT_BASE_8814B) +#define BIT_SET_TCUNIT_BASE_8814B(x, v) \ + (BIT_CLEAR_TCUNIT_BASE_8814B(x) | BIT_TCUNIT_BASE_8814B(v)) /* 2 REG_TC5_CTRL_8814B */ #define BIT_TC5INT_EN_8814B BIT(26) @@ -2528,10 +4788,14 @@ #define BIT_SHIFT_TC5DATA_8814B 0 #define BIT_MASK_TC5DATA_8814B 0xffffff -#define BIT_TC5DATA_8814B(x) (((x) & BIT_MASK_TC5DATA_8814B) << BIT_SHIFT_TC5DATA_8814B) -#define BIT_GET_TC5DATA_8814B(x) (((x) >> BIT_SHIFT_TC5DATA_8814B) & BIT_MASK_TC5DATA_8814B) - - +#define BIT_TC5DATA_8814B(x) \ + (((x) & BIT_MASK_TC5DATA_8814B) << BIT_SHIFT_TC5DATA_8814B) +#define BITS_TC5DATA_8814B (BIT_MASK_TC5DATA_8814B << BIT_SHIFT_TC5DATA_8814B) +#define BIT_CLEAR_TC5DATA_8814B(x) ((x) & (~BITS_TC5DATA_8814B)) +#define BIT_GET_TC5DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC5DATA_8814B) & BIT_MASK_TC5DATA_8814B) +#define BIT_SET_TC5DATA_8814B(x, v) \ + (BIT_CLEAR_TC5DATA_8814B(x) | BIT_TC5DATA_8814B(v)) /* 2 REG_TC6_CTRL_8814B */ #define BIT_TC6INT_EN_8814B BIT(26) @@ -2540,154 +4804,155 @@ #define BIT_SHIFT_TC6DATA_8814B 0 #define BIT_MASK_TC6DATA_8814B 0xffffff -#define BIT_TC6DATA_8814B(x) (((x) & BIT_MASK_TC6DATA_8814B) << BIT_SHIFT_TC6DATA_8814B) -#define BIT_GET_TC6DATA_8814B(x) (((x) >> BIT_SHIFT_TC6DATA_8814B) & BIT_MASK_TC6DATA_8814B) - - - -/* 2 REG_MBIST_FAIL_8814B */ - -#define BIT_SHIFT_8051_MBIST_FAIL_8814B 26 -#define BIT_MASK_8051_MBIST_FAIL_8814B 0x7 -#define BIT_8051_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8814B) << BIT_SHIFT_8051_MBIST_FAIL_8814B) -#define BIT_GET_8051_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8814B) & BIT_MASK_8051_MBIST_FAIL_8814B) - - - -#define BIT_SHIFT_USB_MBIST_FAIL_8814B 24 -#define BIT_MASK_USB_MBIST_FAIL_8814B 0x3 -#define BIT_USB_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8814B) << BIT_SHIFT_USB_MBIST_FAIL_8814B) -#define BIT_GET_USB_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8814B) & BIT_MASK_USB_MBIST_FAIL_8814B) - - - -#define BIT_SHIFT_PCIE_MBIST_FAIL_8814B 16 -#define BIT_MASK_PCIE_MBIST_FAIL_8814B 0x3f -#define BIT_PCIE_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8814B) << BIT_SHIFT_PCIE_MBIST_FAIL_8814B) -#define BIT_GET_PCIE_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8814B) & BIT_MASK_PCIE_MBIST_FAIL_8814B) - - - -#define BIT_SHIFT_MAC_MBIST_FAIL_8814B 0 -#define BIT_MASK_MAC_MBIST_FAIL_8814B 0xfff -#define BIT_MAC_MBIST_FAIL_8814B(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8814B) << BIT_SHIFT_MAC_MBIST_FAIL_8814B) -#define BIT_GET_MAC_MBIST_FAIL_8814B(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8814B) & BIT_MASK_MAC_MBIST_FAIL_8814B) - - - -/* 2 REG_MBIST_START_PAUSE_8814B */ - -#define BIT_SHIFT_8051_MBIST_START_PAUSE_8814B 26 -#define BIT_MASK_8051_MBIST_START_PAUSE_8814B 0x7 -#define BIT_8051_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8814B) << BIT_SHIFT_8051_MBIST_START_PAUSE_8814B) -#define BIT_GET_8051_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8814B) & BIT_MASK_8051_MBIST_START_PAUSE_8814B) - - - -#define BIT_SHIFT_USB_MBIST_START_PAUSE_8814B 24 -#define BIT_MASK_USB_MBIST_START_PAUSE_8814B 0x3 -#define BIT_USB_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8814B) << BIT_SHIFT_USB_MBIST_START_PAUSE_8814B) -#define BIT_GET_USB_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8814B) & BIT_MASK_USB_MBIST_START_PAUSE_8814B) - - - -#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8814B 16 -#define BIT_MASK_PCIE_MBIST_START_PAUSE_8814B 0x3f -#define BIT_PCIE_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8814B) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8814B) -#define BIT_GET_PCIE_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8814B) & BIT_MASK_PCIE_MBIST_START_PAUSE_8814B) - - - -#define BIT_SHIFT_MAC_MBIST_START_PAUSE_8814B 0 -#define BIT_MASK_MAC_MBIST_START_PAUSE_8814B 0xfff -#define BIT_MAC_MBIST_START_PAUSE_8814B(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8814B) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8814B) -#define BIT_GET_MAC_MBIST_START_PAUSE_8814B(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8814B) & BIT_MASK_MAC_MBIST_START_PAUSE_8814B) - - - -/* 2 REG_MBIST_DONE_8814B */ - -#define BIT_SHIFT_8051_MBIST_DONE_8814B 26 -#define BIT_MASK_8051_MBIST_DONE_8814B 0x7 -#define BIT_8051_MBIST_DONE_8814B(x) (((x) & BIT_MASK_8051_MBIST_DONE_8814B) << BIT_SHIFT_8051_MBIST_DONE_8814B) -#define BIT_GET_8051_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8814B) & BIT_MASK_8051_MBIST_DONE_8814B) - - +#define BIT_TC6DATA_8814B(x) \ + (((x) & BIT_MASK_TC6DATA_8814B) << BIT_SHIFT_TC6DATA_8814B) +#define BITS_TC6DATA_8814B (BIT_MASK_TC6DATA_8814B << BIT_SHIFT_TC6DATA_8814B) +#define BIT_CLEAR_TC6DATA_8814B(x) ((x) & (~BITS_TC6DATA_8814B)) +#define BIT_GET_TC6DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC6DATA_8814B) & BIT_MASK_TC6DATA_8814B) +#define BIT_SET_TC6DATA_8814B(x, v) \ + (BIT_CLEAR_TC6DATA_8814B(x) | BIT_TC6DATA_8814B(v)) -#define BIT_SHIFT_USB_MBIST_DONE_8814B 24 -#define BIT_MASK_USB_MBIST_DONE_8814B 0x3 -#define BIT_USB_MBIST_DONE_8814B(x) (((x) & BIT_MASK_USB_MBIST_DONE_8814B) << BIT_SHIFT_USB_MBIST_DONE_8814B) -#define BIT_GET_USB_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8814B) & BIT_MASK_USB_MBIST_DONE_8814B) - - - -#define BIT_SHIFT_PCIE_MBIST_DONE_8814B 16 -#define BIT_MASK_PCIE_MBIST_DONE_8814B 0x3f -#define BIT_PCIE_MBIST_DONE_8814B(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8814B) << BIT_SHIFT_PCIE_MBIST_DONE_8814B) -#define BIT_GET_PCIE_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8814B) & BIT_MASK_PCIE_MBIST_DONE_8814B) - - - -#define BIT_SHIFT_MAC_MBIST_DONE_8814B 0 -#define BIT_MASK_MAC_MBIST_DONE_8814B 0xfff -#define BIT_MAC_MBIST_DONE_8814B(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8814B) << BIT_SHIFT_MAC_MBIST_DONE_8814B) -#define BIT_GET_MAC_MBIST_DONE_8814B(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8814B) & BIT_MASK_MAC_MBIST_DONE_8814B) - - - -/* 2 REG_MBIST_FAIL_NRML_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_MBIST_FAIL_NRML_8814B 0 -#define BIT_MASK_MBIST_FAIL_NRML_8814B 0xffffffffL -#define BIT_MBIST_FAIL_NRML_8814B(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_8814B) << BIT_SHIFT_MBIST_FAIL_NRML_8814B) -#define BIT_GET_MBIST_FAIL_NRML_8814B(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8814B) & BIT_MASK_MBIST_FAIL_NRML_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_AES_DECRPT_DATA_8814B */ #define BIT_SHIFT_IPS_CFG_ADDR_8814B 0 #define BIT_MASK_IPS_CFG_ADDR_8814B 0xff -#define BIT_IPS_CFG_ADDR_8814B(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8814B) << BIT_SHIFT_IPS_CFG_ADDR_8814B) -#define BIT_GET_IPS_CFG_ADDR_8814B(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8814B) & BIT_MASK_IPS_CFG_ADDR_8814B) - - +#define BIT_IPS_CFG_ADDR_8814B(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR_8814B) << BIT_SHIFT_IPS_CFG_ADDR_8814B) +#define BITS_IPS_CFG_ADDR_8814B \ + (BIT_MASK_IPS_CFG_ADDR_8814B << BIT_SHIFT_IPS_CFG_ADDR_8814B) +#define BIT_CLEAR_IPS_CFG_ADDR_8814B(x) ((x) & (~BITS_IPS_CFG_ADDR_8814B)) +#define BIT_GET_IPS_CFG_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8814B) & BIT_MASK_IPS_CFG_ADDR_8814B) +#define BIT_SET_IPS_CFG_ADDR_8814B(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR_8814B(x) | BIT_IPS_CFG_ADDR_8814B(v)) /* 2 REG_AES_DECRPT_CFG_8814B */ #define BIT_SHIFT_IPS_CFG_DATA_8814B 0 #define BIT_MASK_IPS_CFG_DATA_8814B 0xffffffffL -#define BIT_IPS_CFG_DATA_8814B(x) (((x) & BIT_MASK_IPS_CFG_DATA_8814B) << BIT_SHIFT_IPS_CFG_DATA_8814B) -#define BIT_GET_IPS_CFG_DATA_8814B(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8814B) & BIT_MASK_IPS_CFG_DATA_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_IPS_CFG_DATA_8814B(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA_8814B) << BIT_SHIFT_IPS_CFG_DATA_8814B) +#define BITS_IPS_CFG_DATA_8814B \ + (BIT_MASK_IPS_CFG_DATA_8814B << BIT_SHIFT_IPS_CFG_DATA_8814B) +#define BIT_CLEAR_IPS_CFG_DATA_8814B(x) ((x) & (~BITS_IPS_CFG_DATA_8814B)) +#define BIT_GET_IPS_CFG_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA_8814B) & BIT_MASK_IPS_CFG_DATA_8814B) +#define BIT_SET_IPS_CFG_DATA_8814B(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA_8814B(x) | BIT_IPS_CFG_DATA_8814B(v)) + +/* 2 REG_HIOE_CTRL_8814B */ +#define BIT_HIOE_WRITE_REQ_8814B BIT(30) +#define BIT_HIOE_READ_REQ_8814B BIT(29) +#define BIT_INST_FORMAT_ERR_8814B BIT(25) +#define BIT_OP_TIMEOUT_ERR_8814B BIT(24) + +#define BIT_SHIFT_HIOE_OP_TIMEOUT_8814B 16 +#define BIT_MASK_HIOE_OP_TIMEOUT_8814B 0xff +#define BIT_HIOE_OP_TIMEOUT_8814B(x) \ + (((x) & BIT_MASK_HIOE_OP_TIMEOUT_8814B) \ + << BIT_SHIFT_HIOE_OP_TIMEOUT_8814B) +#define BITS_HIOE_OP_TIMEOUT_8814B \ + (BIT_MASK_HIOE_OP_TIMEOUT_8814B << BIT_SHIFT_HIOE_OP_TIMEOUT_8814B) +#define BIT_CLEAR_HIOE_OP_TIMEOUT_8814B(x) ((x) & (~BITS_HIOE_OP_TIMEOUT_8814B)) +#define BIT_GET_HIOE_OP_TIMEOUT_8814B(x) \ + (((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT_8814B) & \ + BIT_MASK_HIOE_OP_TIMEOUT_8814B) +#define BIT_SET_HIOE_OP_TIMEOUT_8814B(x, v) \ + (BIT_CLEAR_HIOE_OP_TIMEOUT_8814B(x) | BIT_HIOE_OP_TIMEOUT_8814B(v)) + +#define BIT_SHIFT_BITDATA_CHECKSUM_8814B 0 +#define BIT_MASK_BITDATA_CHECKSUM_8814B 0xffff +#define BIT_BITDATA_CHECKSUM_8814B(x) \ + (((x) & BIT_MASK_BITDATA_CHECKSUM_8814B) \ + << BIT_SHIFT_BITDATA_CHECKSUM_8814B) +#define BITS_BITDATA_CHECKSUM_8814B \ + (BIT_MASK_BITDATA_CHECKSUM_8814B << BIT_SHIFT_BITDATA_CHECKSUM_8814B) +#define BIT_CLEAR_BITDATA_CHECKSUM_8814B(x) \ + ((x) & (~BITS_BITDATA_CHECKSUM_8814B)) +#define BIT_GET_BITDATA_CHECKSUM_8814B(x) \ + (((x) >> BIT_SHIFT_BITDATA_CHECKSUM_8814B) & \ + BIT_MASK_BITDATA_CHECKSUM_8814B) +#define BIT_SET_BITDATA_CHECKSUM_8814B(x, v) \ + (BIT_CLEAR_BITDATA_CHECKSUM_8814B(x) | BIT_BITDATA_CHECKSUM_8814B(v)) + +/* 2 REG_HIOE_CFG_FILE_8814B */ + +#define BIT_SHIFT_TXBF_END_ADDR_8814B 16 +#define BIT_MASK_TXBF_END_ADDR_8814B 0xffff +#define BIT_TXBF_END_ADDR_8814B(x) \ + (((x) & BIT_MASK_TXBF_END_ADDR_8814B) << BIT_SHIFT_TXBF_END_ADDR_8814B) +#define BITS_TXBF_END_ADDR_8814B \ + (BIT_MASK_TXBF_END_ADDR_8814B << BIT_SHIFT_TXBF_END_ADDR_8814B) +#define BIT_CLEAR_TXBF_END_ADDR_8814B(x) ((x) & (~BITS_TXBF_END_ADDR_8814B)) +#define BIT_GET_TXBF_END_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_TXBF_END_ADDR_8814B) & BIT_MASK_TXBF_END_ADDR_8814B) +#define BIT_SET_TXBF_END_ADDR_8814B(x, v) \ + (BIT_CLEAR_TXBF_END_ADDR_8814B(x) | BIT_TXBF_END_ADDR_8814B(v)) + +#define BIT_SHIFT_TXBF_STR_ADDR_8814B 0 +#define BIT_MASK_TXBF_STR_ADDR_8814B 0xffff +#define BIT_TXBF_STR_ADDR_8814B(x) \ + (((x) & BIT_MASK_TXBF_STR_ADDR_8814B) << BIT_SHIFT_TXBF_STR_ADDR_8814B) +#define BITS_TXBF_STR_ADDR_8814B \ + (BIT_MASK_TXBF_STR_ADDR_8814B << BIT_SHIFT_TXBF_STR_ADDR_8814B) +#define BIT_CLEAR_TXBF_STR_ADDR_8814B(x) ((x) & (~BITS_TXBF_STR_ADDR_8814B)) +#define BIT_GET_TXBF_STR_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_TXBF_STR_ADDR_8814B) & BIT_MASK_TXBF_STR_ADDR_8814B) +#define BIT_SET_TXBF_STR_ADDR_8814B(x, v) \ + (BIT_CLEAR_TXBF_STR_ADDR_8814B(x) | BIT_TXBF_STR_ADDR_8814B(v)) /* 2 REG_TMETER_8814B */ #define BIT_TEMP_VALID_8814B BIT(31) #define BIT_SHIFT_TEMP_VALUE_8814B 24 #define BIT_MASK_TEMP_VALUE_8814B 0x3f -#define BIT_TEMP_VALUE_8814B(x) (((x) & BIT_MASK_TEMP_VALUE_8814B) << BIT_SHIFT_TEMP_VALUE_8814B) -#define BIT_GET_TEMP_VALUE_8814B(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8814B) & BIT_MASK_TEMP_VALUE_8814B) - - +#define BIT_TEMP_VALUE_8814B(x) \ + (((x) & BIT_MASK_TEMP_VALUE_8814B) << BIT_SHIFT_TEMP_VALUE_8814B) +#define BITS_TEMP_VALUE_8814B \ + (BIT_MASK_TEMP_VALUE_8814B << BIT_SHIFT_TEMP_VALUE_8814B) +#define BIT_CLEAR_TEMP_VALUE_8814B(x) ((x) & (~BITS_TEMP_VALUE_8814B)) +#define BIT_GET_TEMP_VALUE_8814B(x) \ + (((x) >> BIT_SHIFT_TEMP_VALUE_8814B) & BIT_MASK_TEMP_VALUE_8814B) +#define BIT_SET_TEMP_VALUE_8814B(x, v) \ + (BIT_CLEAR_TEMP_VALUE_8814B(x) | BIT_TEMP_VALUE_8814B(v)) #define BIT_SHIFT_REG_TMETER_TIMER_8814B 8 #define BIT_MASK_REG_TMETER_TIMER_8814B 0xfff -#define BIT_REG_TMETER_TIMER_8814B(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8814B) << BIT_SHIFT_REG_TMETER_TIMER_8814B) -#define BIT_GET_REG_TMETER_TIMER_8814B(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8814B) & BIT_MASK_REG_TMETER_TIMER_8814B) - - +#define BIT_REG_TMETER_TIMER_8814B(x) \ + (((x) & BIT_MASK_REG_TMETER_TIMER_8814B) \ + << BIT_SHIFT_REG_TMETER_TIMER_8814B) +#define BITS_REG_TMETER_TIMER_8814B \ + (BIT_MASK_REG_TMETER_TIMER_8814B << BIT_SHIFT_REG_TMETER_TIMER_8814B) +#define BIT_CLEAR_REG_TMETER_TIMER_8814B(x) \ + ((x) & (~BITS_REG_TMETER_TIMER_8814B)) +#define BIT_GET_REG_TMETER_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8814B) & \ + BIT_MASK_REG_TMETER_TIMER_8814B) +#define BIT_SET_REG_TMETER_TIMER_8814B(x, v) \ + (BIT_CLEAR_REG_TMETER_TIMER_8814B(x) | BIT_REG_TMETER_TIMER_8814B(v)) #define BIT_SHIFT_REG_TEMP_DELTA_8814B 2 #define BIT_MASK_REG_TEMP_DELTA_8814B 0x3f -#define BIT_REG_TEMP_DELTA_8814B(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8814B) << BIT_SHIFT_REG_TEMP_DELTA_8814B) -#define BIT_GET_REG_TEMP_DELTA_8814B(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8814B) & BIT_MASK_REG_TEMP_DELTA_8814B) - +#define BIT_REG_TEMP_DELTA_8814B(x) \ + (((x) & BIT_MASK_REG_TEMP_DELTA_8814B) \ + << BIT_SHIFT_REG_TEMP_DELTA_8814B) +#define BITS_REG_TEMP_DELTA_8814B \ + (BIT_MASK_REG_TEMP_DELTA_8814B << BIT_SHIFT_REG_TEMP_DELTA_8814B) +#define BIT_CLEAR_REG_TEMP_DELTA_8814B(x) ((x) & (~BITS_REG_TEMP_DELTA_8814B)) +#define BIT_GET_REG_TEMP_DELTA_8814B(x) \ + (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8814B) & \ + BIT_MASK_REG_TEMP_DELTA_8814B) +#define BIT_SET_REG_TEMP_DELTA_8814B(x, v) \ + (BIT_CLEAR_REG_TEMP_DELTA_8814B(x) | BIT_REG_TEMP_DELTA_8814B(v)) #define BIT_REG_TMETER_EN_8814B BIT(0) @@ -2695,16 +4960,33 @@ #define BIT_SHIFT_OSC_32K_CLKGEN_0_8814B 16 #define BIT_MASK_OSC_32K_CLKGEN_0_8814B 0xffff -#define BIT_OSC_32K_CLKGEN_0_8814B(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8814B) << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) -#define BIT_GET_OSC_32K_CLKGEN_0_8814B(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) & BIT_MASK_OSC_32K_CLKGEN_0_8814B) - - +#define BIT_OSC_32K_CLKGEN_0_8814B(x) \ + (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8814B) \ + << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) +#define BITS_OSC_32K_CLKGEN_0_8814B \ + (BIT_MASK_OSC_32K_CLKGEN_0_8814B << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) +#define BIT_CLEAR_OSC_32K_CLKGEN_0_8814B(x) \ + ((x) & (~BITS_OSC_32K_CLKGEN_0_8814B)) +#define BIT_GET_OSC_32K_CLKGEN_0_8814B(x) \ + (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) & \ + BIT_MASK_OSC_32K_CLKGEN_0_8814B) +#define BIT_SET_OSC_32K_CLKGEN_0_8814B(x, v) \ + (BIT_CLEAR_OSC_32K_CLKGEN_0_8814B(x) | BIT_OSC_32K_CLKGEN_0_8814B(v)) #define BIT_SHIFT_OSC_32K_RES_COMP_8814B 4 #define BIT_MASK_OSC_32K_RES_COMP_8814B 0x3 -#define BIT_OSC_32K_RES_COMP_8814B(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8814B) << BIT_SHIFT_OSC_32K_RES_COMP_8814B) -#define BIT_GET_OSC_32K_RES_COMP_8814B(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8814B) & BIT_MASK_OSC_32K_RES_COMP_8814B) - +#define BIT_OSC_32K_RES_COMP_8814B(x) \ + (((x) & BIT_MASK_OSC_32K_RES_COMP_8814B) \ + << BIT_SHIFT_OSC_32K_RES_COMP_8814B) +#define BITS_OSC_32K_RES_COMP_8814B \ + (BIT_MASK_OSC_32K_RES_COMP_8814B << BIT_SHIFT_OSC_32K_RES_COMP_8814B) +#define BIT_CLEAR_OSC_32K_RES_COMP_8814B(x) \ + ((x) & (~BITS_OSC_32K_RES_COMP_8814B)) +#define BIT_GET_OSC_32K_RES_COMP_8814B(x) \ + (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8814B) & \ + BIT_MASK_OSC_32K_RES_COMP_8814B) +#define BIT_SET_OSC_32K_RES_COMP_8814B(x, v) \ + (BIT_CLEAR_OSC_32K_RES_COMP_8814B(x) | BIT_OSC_32K_RES_COMP_8814B(v)) #define BIT_OSC_32K_OUT_SEL_8814B BIT(3) #define BIT_ISO_WL_2_OSC_32K_8814B BIT(1) @@ -2716,17 +4998,33 @@ #define BIT_SHIFT_CAL_32K_REG_ADDR_8814B 16 #define BIT_MASK_CAL_32K_REG_ADDR_8814B 0x3f -#define BIT_CAL_32K_REG_ADDR_8814B(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR_8814B) << BIT_SHIFT_CAL_32K_REG_ADDR_8814B) -#define BIT_GET_CAL_32K_REG_ADDR_8814B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8814B) & BIT_MASK_CAL_32K_REG_ADDR_8814B) - - +#define BIT_CAL_32K_REG_ADDR_8814B(x) \ + (((x) & BIT_MASK_CAL_32K_REG_ADDR_8814B) \ + << BIT_SHIFT_CAL_32K_REG_ADDR_8814B) +#define BITS_CAL_32K_REG_ADDR_8814B \ + (BIT_MASK_CAL_32K_REG_ADDR_8814B << BIT_SHIFT_CAL_32K_REG_ADDR_8814B) +#define BIT_CLEAR_CAL_32K_REG_ADDR_8814B(x) \ + ((x) & (~BITS_CAL_32K_REG_ADDR_8814B)) +#define BIT_GET_CAL_32K_REG_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8814B) & \ + BIT_MASK_CAL_32K_REG_ADDR_8814B) +#define BIT_SET_CAL_32K_REG_ADDR_8814B(x, v) \ + (BIT_CLEAR_CAL_32K_REG_ADDR_8814B(x) | BIT_CAL_32K_REG_ADDR_8814B(v)) #define BIT_SHIFT_CAL_32K_REG_DATA_8814B 0 #define BIT_MASK_CAL_32K_REG_DATA_8814B 0xffff -#define BIT_CAL_32K_REG_DATA_8814B(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8814B) << BIT_SHIFT_CAL_32K_REG_DATA_8814B) -#define BIT_GET_CAL_32K_REG_DATA_8814B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8814B) & BIT_MASK_CAL_32K_REG_DATA_8814B) - - +#define BIT_CAL_32K_REG_DATA_8814B(x) \ + (((x) & BIT_MASK_CAL_32K_REG_DATA_8814B) \ + << BIT_SHIFT_CAL_32K_REG_DATA_8814B) +#define BITS_CAL_32K_REG_DATA_8814B \ + (BIT_MASK_CAL_32K_REG_DATA_8814B << BIT_SHIFT_CAL_32K_REG_DATA_8814B) +#define BIT_CLEAR_CAL_32K_REG_DATA_8814B(x) \ + ((x) & (~BITS_CAL_32K_REG_DATA_8814B)) +#define BIT_GET_CAL_32K_REG_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8814B) & \ + BIT_MASK_CAL_32K_REG_DATA_8814B) +#define BIT_SET_CAL_32K_REG_DATA_8814B(x, v) \ + (BIT_CLEAR_CAL_32K_REG_DATA_8814B(x) | BIT_CAL_32K_REG_DATA_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -2734,95 +5032,183 @@ #define BIT_SHIFT_C2HEVT_MSG_V1_8814B 0 #define BIT_MASK_C2HEVT_MSG_V1_8814B 0xffffffffL -#define BIT_C2HEVT_MSG_V1_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_V1_8814B) << BIT_SHIFT_C2HEVT_MSG_V1_8814B) -#define BIT_GET_C2HEVT_MSG_V1_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8814B) & BIT_MASK_C2HEVT_MSG_V1_8814B) - - +#define BIT_C2HEVT_MSG_V1_8814B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_V1_8814B) << BIT_SHIFT_C2HEVT_MSG_V1_8814B) +#define BITS_C2HEVT_MSG_V1_8814B \ + (BIT_MASK_C2HEVT_MSG_V1_8814B << BIT_SHIFT_C2HEVT_MSG_V1_8814B) +#define BIT_CLEAR_C2HEVT_MSG_V1_8814B(x) ((x) & (~BITS_C2HEVT_MSG_V1_8814B)) +#define BIT_GET_C2HEVT_MSG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8814B) & BIT_MASK_C2HEVT_MSG_V1_8814B) +#define BIT_SET_C2HEVT_MSG_V1_8814B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_V1_8814B(x) | BIT_C2HEVT_MSG_V1_8814B(v)) /* 2 REG_C2HEVT_1_8814B */ #define BIT_SHIFT_C2HEVT_MSG_1_8814B 0 #define BIT_MASK_C2HEVT_MSG_1_8814B 0xffffffffL -#define BIT_C2HEVT_MSG_1_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_1_8814B) << BIT_SHIFT_C2HEVT_MSG_1_8814B) -#define BIT_GET_C2HEVT_MSG_1_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8814B) & BIT_MASK_C2HEVT_MSG_1_8814B) - - +#define BIT_C2HEVT_MSG_1_8814B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_1_8814B) << BIT_SHIFT_C2HEVT_MSG_1_8814B) +#define BITS_C2HEVT_MSG_1_8814B \ + (BIT_MASK_C2HEVT_MSG_1_8814B << BIT_SHIFT_C2HEVT_MSG_1_8814B) +#define BIT_CLEAR_C2HEVT_MSG_1_8814B(x) ((x) & (~BITS_C2HEVT_MSG_1_8814B)) +#define BIT_GET_C2HEVT_MSG_1_8814B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8814B) & BIT_MASK_C2HEVT_MSG_1_8814B) +#define BIT_SET_C2HEVT_MSG_1_8814B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_1_8814B(x) | BIT_C2HEVT_MSG_1_8814B(v)) /* 2 REG_C2HEVT_2_8814B */ #define BIT_SHIFT_C2HEVT_MSG_2_8814B 0 #define BIT_MASK_C2HEVT_MSG_2_8814B 0xffffffffL -#define BIT_C2HEVT_MSG_2_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_2_8814B) << BIT_SHIFT_C2HEVT_MSG_2_8814B) -#define BIT_GET_C2HEVT_MSG_2_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8814B) & BIT_MASK_C2HEVT_MSG_2_8814B) - - +#define BIT_C2HEVT_MSG_2_8814B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_2_8814B) << BIT_SHIFT_C2HEVT_MSG_2_8814B) +#define BITS_C2HEVT_MSG_2_8814B \ + (BIT_MASK_C2HEVT_MSG_2_8814B << BIT_SHIFT_C2HEVT_MSG_2_8814B) +#define BIT_CLEAR_C2HEVT_MSG_2_8814B(x) ((x) & (~BITS_C2HEVT_MSG_2_8814B)) +#define BIT_GET_C2HEVT_MSG_2_8814B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8814B) & BIT_MASK_C2HEVT_MSG_2_8814B) +#define BIT_SET_C2HEVT_MSG_2_8814B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_2_8814B(x) | BIT_C2HEVT_MSG_2_8814B(v)) /* 2 REG_C2HEVT_3_8814B */ #define BIT_SHIFT_C2HEVT_MSG_3_8814B 0 #define BIT_MASK_C2HEVT_MSG_3_8814B 0xffffffffL -#define BIT_C2HEVT_MSG_3_8814B(x) (((x) & BIT_MASK_C2HEVT_MSG_3_8814B) << BIT_SHIFT_C2HEVT_MSG_3_8814B) -#define BIT_GET_C2HEVT_MSG_3_8814B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8814B) & BIT_MASK_C2HEVT_MSG_3_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_C2HEVT_MSG_3_8814B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_3_8814B) << BIT_SHIFT_C2HEVT_MSG_3_8814B) +#define BITS_C2HEVT_MSG_3_8814B \ + (BIT_MASK_C2HEVT_MSG_3_8814B << BIT_SHIFT_C2HEVT_MSG_3_8814B) +#define BIT_CLEAR_C2HEVT_MSG_3_8814B(x) ((x) & (~BITS_C2HEVT_MSG_3_8814B)) +#define BIT_GET_C2HEVT_MSG_3_8814B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8814B) & BIT_MASK_C2HEVT_MSG_3_8814B) +#define BIT_SET_C2HEVT_MSG_3_8814B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_3_8814B(x) | BIT_C2HEVT_MSG_3_8814B(v)) + +/* 2 REG_RXDESC_BUFF_RPTR_8814B */ + +#define BIT_SHIFT_RXDESC_BUFF_RPTR_8814B 0 +#define BIT_MASK_RXDESC_BUFF_RPTR_8814B 0xffffffffL +#define BIT_RXDESC_BUFF_RPTR_8814B(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_RPTR_8814B) \ + << BIT_SHIFT_RXDESC_BUFF_RPTR_8814B) +#define BITS_RXDESC_BUFF_RPTR_8814B \ + (BIT_MASK_RXDESC_BUFF_RPTR_8814B << BIT_SHIFT_RXDESC_BUFF_RPTR_8814B) +#define BIT_CLEAR_RXDESC_BUFF_RPTR_8814B(x) \ + ((x) & (~BITS_RXDESC_BUFF_RPTR_8814B)) +#define BIT_GET_RXDESC_BUFF_RPTR_8814B(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_RPTR_8814B) & \ + BIT_MASK_RXDESC_BUFF_RPTR_8814B) +#define BIT_SET_RXDESC_BUFF_RPTR_8814B(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_RPTR_8814B(x) | BIT_RXDESC_BUFF_RPTR_8814B(v)) + +/* 2 REG_RXDESC_BUFF_WPTR_8814B */ + +#define BIT_SHIFT_RXDESC_BUFF_WPTR_8814B 0 +#define BIT_MASK_RXDESC_BUFF_WPTR_8814B 0xffffffffL +#define BIT_RXDESC_BUFF_WPTR_8814B(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_WPTR_8814B) \ + << BIT_SHIFT_RXDESC_BUFF_WPTR_8814B) +#define BITS_RXDESC_BUFF_WPTR_8814B \ + (BIT_MASK_RXDESC_BUFF_WPTR_8814B << BIT_SHIFT_RXDESC_BUFF_WPTR_8814B) +#define BIT_CLEAR_RXDESC_BUFF_WPTR_8814B(x) \ + ((x) & (~BITS_RXDESC_BUFF_WPTR_8814B)) +#define BIT_GET_RXDESC_BUFF_WPTR_8814B(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_WPTR_8814B) & \ + BIT_MASK_RXDESC_BUFF_WPTR_8814B) +#define BIT_SET_RXDESC_BUFF_WPTR_8814B(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_WPTR_8814B(x) | BIT_RXDESC_BUFF_WPTR_8814B(v)) /* 2 REG_SW_DEFINED_PAGE1_8814B */ #define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B 0 #define BIT_MASK_SW_DEFINED_PAGE1_V1_8814B 0xffffffffL -#define BIT_SW_DEFINED_PAGE1_V1_8814B(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8814B) << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) -#define BIT_GET_SW_DEFINED_PAGE1_V1_8814B(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) & BIT_MASK_SW_DEFINED_PAGE1_V1_8814B) - - +#define BIT_SW_DEFINED_PAGE1_V1_8814B(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8814B) \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) +#define BITS_SW_DEFINED_PAGE1_V1_8814B \ + (BIT_MASK_SW_DEFINED_PAGE1_V1_8814B \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) +#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8814B(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE1_V1_8814B)) +#define BIT_GET_SW_DEFINED_PAGE1_V1_8814B(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) & \ + BIT_MASK_SW_DEFINED_PAGE1_V1_8814B) +#define BIT_SET_SW_DEFINED_PAGE1_V1_8814B(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_V1_8814B(x) | \ + BIT_SW_DEFINED_PAGE1_V1_8814B(v)) /* 2 REG_SW_DEFINED_PAGE2_8814B */ #define BIT_SHIFT_SW_DEFINED_PAGE2_8814B 0 #define BIT_MASK_SW_DEFINED_PAGE2_8814B 0xffffffffL -#define BIT_SW_DEFINED_PAGE2_8814B(x) (((x) & BIT_MASK_SW_DEFINED_PAGE2_8814B) << BIT_SHIFT_SW_DEFINED_PAGE2_8814B) -#define BIT_GET_SW_DEFINED_PAGE2_8814B(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8814B) & BIT_MASK_SW_DEFINED_PAGE2_8814B) - - +#define BIT_SW_DEFINED_PAGE2_8814B(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE2_8814B) \ + << BIT_SHIFT_SW_DEFINED_PAGE2_8814B) +#define BITS_SW_DEFINED_PAGE2_8814B \ + (BIT_MASK_SW_DEFINED_PAGE2_8814B << BIT_SHIFT_SW_DEFINED_PAGE2_8814B) +#define BIT_CLEAR_SW_DEFINED_PAGE2_8814B(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE2_8814B)) +#define BIT_GET_SW_DEFINED_PAGE2_8814B(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8814B) & \ + BIT_MASK_SW_DEFINED_PAGE2_8814B) +#define BIT_SET_SW_DEFINED_PAGE2_8814B(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE2_8814B(x) | BIT_SW_DEFINED_PAGE2_8814B(v)) /* 2 REG_MCUTST_I_8814B */ #define BIT_SHIFT_MCUDMSG_I_8814B 0 #define BIT_MASK_MCUDMSG_I_8814B 0xffffffffL -#define BIT_MCUDMSG_I_8814B(x) (((x) & BIT_MASK_MCUDMSG_I_8814B) << BIT_SHIFT_MCUDMSG_I_8814B) -#define BIT_GET_MCUDMSG_I_8814B(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8814B) & BIT_MASK_MCUDMSG_I_8814B) - - +#define BIT_MCUDMSG_I_8814B(x) \ + (((x) & BIT_MASK_MCUDMSG_I_8814B) << BIT_SHIFT_MCUDMSG_I_8814B) +#define BITS_MCUDMSG_I_8814B \ + (BIT_MASK_MCUDMSG_I_8814B << BIT_SHIFT_MCUDMSG_I_8814B) +#define BIT_CLEAR_MCUDMSG_I_8814B(x) ((x) & (~BITS_MCUDMSG_I_8814B)) +#define BIT_GET_MCUDMSG_I_8814B(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_I_8814B) & BIT_MASK_MCUDMSG_I_8814B) +#define BIT_SET_MCUDMSG_I_8814B(x, v) \ + (BIT_CLEAR_MCUDMSG_I_8814B(x) | BIT_MCUDMSG_I_8814B(v)) /* 2 REG_MCUTST_II_8814B */ #define BIT_SHIFT_MCUDMSG_II_8814B 0 #define BIT_MASK_MCUDMSG_II_8814B 0xffffffffL -#define BIT_MCUDMSG_II_8814B(x) (((x) & BIT_MASK_MCUDMSG_II_8814B) << BIT_SHIFT_MCUDMSG_II_8814B) -#define BIT_GET_MCUDMSG_II_8814B(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8814B) & BIT_MASK_MCUDMSG_II_8814B) - - +#define BIT_MCUDMSG_II_8814B(x) \ + (((x) & BIT_MASK_MCUDMSG_II_8814B) << BIT_SHIFT_MCUDMSG_II_8814B) +#define BITS_MCUDMSG_II_8814B \ + (BIT_MASK_MCUDMSG_II_8814B << BIT_SHIFT_MCUDMSG_II_8814B) +#define BIT_CLEAR_MCUDMSG_II_8814B(x) ((x) & (~BITS_MCUDMSG_II_8814B)) +#define BIT_GET_MCUDMSG_II_8814B(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II_8814B) & BIT_MASK_MCUDMSG_II_8814B) +#define BIT_SET_MCUDMSG_II_8814B(x, v) \ + (BIT_CLEAR_MCUDMSG_II_8814B(x) | BIT_MCUDMSG_II_8814B(v)) /* 2 REG_FMETHR_8814B */ #define BIT_FMSG_INT_8814B BIT(31) #define BIT_SHIFT_FW_MSG_8814B 0 #define BIT_MASK_FW_MSG_8814B 0xffffffffL -#define BIT_FW_MSG_8814B(x) (((x) & BIT_MASK_FW_MSG_8814B) << BIT_SHIFT_FW_MSG_8814B) -#define BIT_GET_FW_MSG_8814B(x) (((x) >> BIT_SHIFT_FW_MSG_8814B) & BIT_MASK_FW_MSG_8814B) - - +#define BIT_FW_MSG_8814B(x) \ + (((x) & BIT_MASK_FW_MSG_8814B) << BIT_SHIFT_FW_MSG_8814B) +#define BITS_FW_MSG_8814B (BIT_MASK_FW_MSG_8814B << BIT_SHIFT_FW_MSG_8814B) +#define BIT_CLEAR_FW_MSG_8814B(x) ((x) & (~BITS_FW_MSG_8814B)) +#define BIT_GET_FW_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_FW_MSG_8814B) & BIT_MASK_FW_MSG_8814B) +#define BIT_SET_FW_MSG_8814B(x, v) \ + (BIT_CLEAR_FW_MSG_8814B(x) | BIT_FW_MSG_8814B(v)) /* 2 REG_HMETFR_8814B */ #define BIT_SHIFT_HRCV_MSG_8814B 24 #define BIT_MASK_HRCV_MSG_8814B 0xff -#define BIT_HRCV_MSG_8814B(x) (((x) & BIT_MASK_HRCV_MSG_8814B) << BIT_SHIFT_HRCV_MSG_8814B) -#define BIT_GET_HRCV_MSG_8814B(x) (((x) >> BIT_SHIFT_HRCV_MSG_8814B) & BIT_MASK_HRCV_MSG_8814B) - +#define BIT_HRCV_MSG_8814B(x) \ + (((x) & BIT_MASK_HRCV_MSG_8814B) << BIT_SHIFT_HRCV_MSG_8814B) +#define BITS_HRCV_MSG_8814B \ + (BIT_MASK_HRCV_MSG_8814B << BIT_SHIFT_HRCV_MSG_8814B) +#define BIT_CLEAR_HRCV_MSG_8814B(x) ((x) & (~BITS_HRCV_MSG_8814B)) +#define BIT_GET_HRCV_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_HRCV_MSG_8814B) & BIT_MASK_HRCV_MSG_8814B) +#define BIT_SET_HRCV_MSG_8814B(x, v) \ + (BIT_CLEAR_HRCV_MSG_8814B(x) | BIT_HRCV_MSG_8814B(v)) #define BIT_INT_BOX3_8814B BIT(3) #define BIT_INT_BOX2_8814B BIT(2) @@ -2833,91 +5219,113 @@ #define BIT_SHIFT_HOST_MSG_0_8814B 0 #define BIT_MASK_HOST_MSG_0_8814B 0xffffffffL -#define BIT_HOST_MSG_0_8814B(x) (((x) & BIT_MASK_HOST_MSG_0_8814B) << BIT_SHIFT_HOST_MSG_0_8814B) -#define BIT_GET_HOST_MSG_0_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8814B) & BIT_MASK_HOST_MSG_0_8814B) - - +#define BIT_HOST_MSG_0_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_0_8814B) << BIT_SHIFT_HOST_MSG_0_8814B) +#define BITS_HOST_MSG_0_8814B \ + (BIT_MASK_HOST_MSG_0_8814B << BIT_SHIFT_HOST_MSG_0_8814B) +#define BIT_CLEAR_HOST_MSG_0_8814B(x) ((x) & (~BITS_HOST_MSG_0_8814B)) +#define BIT_GET_HOST_MSG_0_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0_8814B) & BIT_MASK_HOST_MSG_0_8814B) +#define BIT_SET_HOST_MSG_0_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_0_8814B(x) | BIT_HOST_MSG_0_8814B(v)) /* 2 REG_HMEBOX1_8814B */ #define BIT_SHIFT_HOST_MSG_1_8814B 0 #define BIT_MASK_HOST_MSG_1_8814B 0xffffffffL -#define BIT_HOST_MSG_1_8814B(x) (((x) & BIT_MASK_HOST_MSG_1_8814B) << BIT_SHIFT_HOST_MSG_1_8814B) -#define BIT_GET_HOST_MSG_1_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8814B) & BIT_MASK_HOST_MSG_1_8814B) - - +#define BIT_HOST_MSG_1_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_1_8814B) << BIT_SHIFT_HOST_MSG_1_8814B) +#define BITS_HOST_MSG_1_8814B \ + (BIT_MASK_HOST_MSG_1_8814B << BIT_SHIFT_HOST_MSG_1_8814B) +#define BIT_CLEAR_HOST_MSG_1_8814B(x) ((x) & (~BITS_HOST_MSG_1_8814B)) +#define BIT_GET_HOST_MSG_1_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1_8814B) & BIT_MASK_HOST_MSG_1_8814B) +#define BIT_SET_HOST_MSG_1_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_1_8814B(x) | BIT_HOST_MSG_1_8814B(v)) /* 2 REG_HMEBOX2_8814B */ #define BIT_SHIFT_HOST_MSG_2_8814B 0 #define BIT_MASK_HOST_MSG_2_8814B 0xffffffffL -#define BIT_HOST_MSG_2_8814B(x) (((x) & BIT_MASK_HOST_MSG_2_8814B) << BIT_SHIFT_HOST_MSG_2_8814B) -#define BIT_GET_HOST_MSG_2_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8814B) & BIT_MASK_HOST_MSG_2_8814B) - - +#define BIT_HOST_MSG_2_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_2_8814B) << BIT_SHIFT_HOST_MSG_2_8814B) +#define BITS_HOST_MSG_2_8814B \ + (BIT_MASK_HOST_MSG_2_8814B << BIT_SHIFT_HOST_MSG_2_8814B) +#define BIT_CLEAR_HOST_MSG_2_8814B(x) ((x) & (~BITS_HOST_MSG_2_8814B)) +#define BIT_GET_HOST_MSG_2_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2_8814B) & BIT_MASK_HOST_MSG_2_8814B) +#define BIT_SET_HOST_MSG_2_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_2_8814B(x) | BIT_HOST_MSG_2_8814B(v)) /* 2 REG_HMEBOX3_8814B */ #define BIT_SHIFT_HOST_MSG_3_8814B 0 #define BIT_MASK_HOST_MSG_3_8814B 0xffffffffL -#define BIT_HOST_MSG_3_8814B(x) (((x) & BIT_MASK_HOST_MSG_3_8814B) << BIT_SHIFT_HOST_MSG_3_8814B) -#define BIT_GET_HOST_MSG_3_8814B(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8814B) & BIT_MASK_HOST_MSG_3_8814B) - - - -/* 2 REG_LLT_INIT_8814B */ - -#define BIT_SHIFT_LLTE_RWM_8814B 30 -#define BIT_MASK_LLTE_RWM_8814B 0x3 -#define BIT_LLTE_RWM_8814B(x) (((x) & BIT_MASK_LLTE_RWM_8814B) << BIT_SHIFT_LLTE_RWM_8814B) -#define BIT_GET_LLTE_RWM_8814B(x) (((x) >> BIT_SHIFT_LLTE_RWM_8814B) & BIT_MASK_LLTE_RWM_8814B) - - - -#define BIT_SHIFT_LLTINI_PDATA_V1_8814B 16 -#define BIT_MASK_LLTINI_PDATA_V1_8814B 0xfff -#define BIT_LLTINI_PDATA_V1_8814B(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8814B) << BIT_SHIFT_LLTINI_PDATA_V1_8814B) -#define BIT_GET_LLTINI_PDATA_V1_8814B(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8814B) & BIT_MASK_LLTINI_PDATA_V1_8814B) - - - -#define BIT_SHIFT_LLTINI_HDATA_V1_8814B 0 -#define BIT_MASK_LLTINI_HDATA_V1_8814B 0xfff -#define BIT_LLTINI_HDATA_V1_8814B(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8814B) << BIT_SHIFT_LLTINI_HDATA_V1_8814B) -#define BIT_GET_LLTINI_HDATA_V1_8814B(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8814B) & BIT_MASK_LLTINI_HDATA_V1_8814B) - - - -/* 2 REG_LLT_INIT_ADDR_8814B */ - -#define BIT_SHIFT_LLTINI_ADDR_V1_8814B 0 -#define BIT_MASK_LLTINI_ADDR_V1_8814B 0xfff -#define BIT_LLTINI_ADDR_V1_8814B(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8814B) << BIT_SHIFT_LLTINI_ADDR_V1_8814B) -#define BIT_GET_LLTINI_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8814B) & BIT_MASK_LLTINI_ADDR_V1_8814B) - +#define BIT_HOST_MSG_3_8814B(x) \ + (((x) & BIT_MASK_HOST_MSG_3_8814B) << BIT_SHIFT_HOST_MSG_3_8814B) +#define BITS_HOST_MSG_3_8814B \ + (BIT_MASK_HOST_MSG_3_8814B << BIT_SHIFT_HOST_MSG_3_8814B) +#define BIT_CLEAR_HOST_MSG_3_8814B(x) ((x) & (~BITS_HOST_MSG_3_8814B)) +#define BIT_GET_HOST_MSG_3_8814B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3_8814B) & BIT_MASK_HOST_MSG_3_8814B) +#define BIT_SET_HOST_MSG_3_8814B(x, v) \ + (BIT_CLEAR_HOST_MSG_3_8814B(x) | BIT_HOST_MSG_3_8814B(v)) + +/* 2 REG_RXDESC_BUFF_BNDY_8814B */ + +#define BIT_SHIFT_RXDESC_BUFF_BNDY_8814B 0 +#define BIT_MASK_RXDESC_BUFF_BNDY_8814B 0xffffffffL +#define BIT_RXDESC_BUFF_BNDY_8814B(x) \ + (((x) & BIT_MASK_RXDESC_BUFF_BNDY_8814B) \ + << BIT_SHIFT_RXDESC_BUFF_BNDY_8814B) +#define BITS_RXDESC_BUFF_BNDY_8814B \ + (BIT_MASK_RXDESC_BUFF_BNDY_8814B << BIT_SHIFT_RXDESC_BUFF_BNDY_8814B) +#define BIT_CLEAR_RXDESC_BUFF_BNDY_8814B(x) \ + ((x) & (~BITS_RXDESC_BUFF_BNDY_8814B)) +#define BIT_GET_RXDESC_BUFF_BNDY_8814B(x) \ + (((x) >> BIT_SHIFT_RXDESC_BUFF_BNDY_8814B) & \ + BIT_MASK_RXDESC_BUFF_BNDY_8814B) +#define BIT_SET_RXDESC_BUFF_BNDY_8814B(x, v) \ + (BIT_CLEAR_RXDESC_BUFF_BNDY_8814B(x) | BIT_RXDESC_BUFF_BNDY_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_BB_ACCESS_CTRL_8814B */ #define BIT_SHIFT_BB_WRITE_READ_8814B 30 #define BIT_MASK_BB_WRITE_READ_8814B 0x3 -#define BIT_BB_WRITE_READ_8814B(x) (((x) & BIT_MASK_BB_WRITE_READ_8814B) << BIT_SHIFT_BB_WRITE_READ_8814B) -#define BIT_GET_BB_WRITE_READ_8814B(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8814B) & BIT_MASK_BB_WRITE_READ_8814B) - - +#define BIT_BB_WRITE_READ_8814B(x) \ + (((x) & BIT_MASK_BB_WRITE_READ_8814B) << BIT_SHIFT_BB_WRITE_READ_8814B) +#define BITS_BB_WRITE_READ_8814B \ + (BIT_MASK_BB_WRITE_READ_8814B << BIT_SHIFT_BB_WRITE_READ_8814B) +#define BIT_CLEAR_BB_WRITE_READ_8814B(x) ((x) & (~BITS_BB_WRITE_READ_8814B)) +#define BIT_GET_BB_WRITE_READ_8814B(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ_8814B) & BIT_MASK_BB_WRITE_READ_8814B) +#define BIT_SET_BB_WRITE_READ_8814B(x, v) \ + (BIT_CLEAR_BB_WRITE_READ_8814B(x) | BIT_BB_WRITE_READ_8814B(v)) #define BIT_SHIFT_BB_WRITE_EN_8814B 12 #define BIT_MASK_BB_WRITE_EN_8814B 0xf -#define BIT_BB_WRITE_EN_8814B(x) (((x) & BIT_MASK_BB_WRITE_EN_8814B) << BIT_SHIFT_BB_WRITE_EN_8814B) -#define BIT_GET_BB_WRITE_EN_8814B(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8814B) & BIT_MASK_BB_WRITE_EN_8814B) - - +#define BIT_BB_WRITE_EN_8814B(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_8814B) << BIT_SHIFT_BB_WRITE_EN_8814B) +#define BITS_BB_WRITE_EN_8814B \ + (BIT_MASK_BB_WRITE_EN_8814B << BIT_SHIFT_BB_WRITE_EN_8814B) +#define BIT_CLEAR_BB_WRITE_EN_8814B(x) ((x) & (~BITS_BB_WRITE_EN_8814B)) +#define BIT_GET_BB_WRITE_EN_8814B(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_8814B) & BIT_MASK_BB_WRITE_EN_8814B) +#define BIT_SET_BB_WRITE_EN_8814B(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_8814B(x) | BIT_BB_WRITE_EN_8814B(v)) #define BIT_SHIFT_BB_ADDR_8814B 2 #define BIT_MASK_BB_ADDR_8814B 0x1ff -#define BIT_BB_ADDR_8814B(x) (((x) & BIT_MASK_BB_ADDR_8814B) << BIT_SHIFT_BB_ADDR_8814B) -#define BIT_GET_BB_ADDR_8814B(x) (((x) >> BIT_SHIFT_BB_ADDR_8814B) & BIT_MASK_BB_ADDR_8814B) - +#define BIT_BB_ADDR_8814B(x) \ + (((x) & BIT_MASK_BB_ADDR_8814B) << BIT_SHIFT_BB_ADDR_8814B) +#define BITS_BB_ADDR_8814B (BIT_MASK_BB_ADDR_8814B << BIT_SHIFT_BB_ADDR_8814B) +#define BIT_CLEAR_BB_ADDR_8814B(x) ((x) & (~BITS_BB_ADDR_8814B)) +#define BIT_GET_BB_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_8814B) & BIT_MASK_BB_ADDR_8814B) +#define BIT_SET_BB_ADDR_8814B(x, v) \ + (BIT_CLEAR_BB_ADDR_8814B(x) | BIT_BB_ADDR_8814B(v)) #define BIT_BB_ERRACC_8814B BIT(0) @@ -2925,112 +5333,229 @@ #define BIT_SHIFT_BB_DATA_8814B 0 #define BIT_MASK_BB_DATA_8814B 0xffffffffL -#define BIT_BB_DATA_8814B(x) (((x) & BIT_MASK_BB_DATA_8814B) << BIT_SHIFT_BB_DATA_8814B) -#define BIT_GET_BB_DATA_8814B(x) (((x) >> BIT_SHIFT_BB_DATA_8814B) & BIT_MASK_BB_DATA_8814B) - - +#define BIT_BB_DATA_8814B(x) \ + (((x) & BIT_MASK_BB_DATA_8814B) << BIT_SHIFT_BB_DATA_8814B) +#define BITS_BB_DATA_8814B (BIT_MASK_BB_DATA_8814B << BIT_SHIFT_BB_DATA_8814B) +#define BIT_CLEAR_BB_DATA_8814B(x) ((x) & (~BITS_BB_DATA_8814B)) +#define BIT_GET_BB_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_BB_DATA_8814B) & BIT_MASK_BB_DATA_8814B) +#define BIT_SET_BB_DATA_8814B(x, v) \ + (BIT_CLEAR_BB_DATA_8814B(x) | BIT_BB_DATA_8814B(v)) /* 2 REG_HMEBOX_E0_8814B */ #define BIT_SHIFT_HMEBOX_E0_8814B 0 #define BIT_MASK_HMEBOX_E0_8814B 0xffffffffL -#define BIT_HMEBOX_E0_8814B(x) (((x) & BIT_MASK_HMEBOX_E0_8814B) << BIT_SHIFT_HMEBOX_E0_8814B) -#define BIT_GET_HMEBOX_E0_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8814B) & BIT_MASK_HMEBOX_E0_8814B) - - +#define BIT_HMEBOX_E0_8814B(x) \ + (((x) & BIT_MASK_HMEBOX_E0_8814B) << BIT_SHIFT_HMEBOX_E0_8814B) +#define BITS_HMEBOX_E0_8814B \ + (BIT_MASK_HMEBOX_E0_8814B << BIT_SHIFT_HMEBOX_E0_8814B) +#define BIT_CLEAR_HMEBOX_E0_8814B(x) ((x) & (~BITS_HMEBOX_E0_8814B)) +#define BIT_GET_HMEBOX_E0_8814B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E0_8814B) & BIT_MASK_HMEBOX_E0_8814B) +#define BIT_SET_HMEBOX_E0_8814B(x, v) \ + (BIT_CLEAR_HMEBOX_E0_8814B(x) | BIT_HMEBOX_E0_8814B(v)) /* 2 REG_HMEBOX_E1_8814B */ #define BIT_SHIFT_HMEBOX_E1_8814B 0 #define BIT_MASK_HMEBOX_E1_8814B 0xffffffffL -#define BIT_HMEBOX_E1_8814B(x) (((x) & BIT_MASK_HMEBOX_E1_8814B) << BIT_SHIFT_HMEBOX_E1_8814B) -#define BIT_GET_HMEBOX_E1_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8814B) & BIT_MASK_HMEBOX_E1_8814B) - - +#define BIT_HMEBOX_E1_8814B(x) \ + (((x) & BIT_MASK_HMEBOX_E1_8814B) << BIT_SHIFT_HMEBOX_E1_8814B) +#define BITS_HMEBOX_E1_8814B \ + (BIT_MASK_HMEBOX_E1_8814B << BIT_SHIFT_HMEBOX_E1_8814B) +#define BIT_CLEAR_HMEBOX_E1_8814B(x) ((x) & (~BITS_HMEBOX_E1_8814B)) +#define BIT_GET_HMEBOX_E1_8814B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E1_8814B) & BIT_MASK_HMEBOX_E1_8814B) +#define BIT_SET_HMEBOX_E1_8814B(x, v) \ + (BIT_CLEAR_HMEBOX_E1_8814B(x) | BIT_HMEBOX_E1_8814B(v)) /* 2 REG_HMEBOX_E2_8814B */ #define BIT_SHIFT_HMEBOX_E2_8814B 0 #define BIT_MASK_HMEBOX_E2_8814B 0xffffffffL -#define BIT_HMEBOX_E2_8814B(x) (((x) & BIT_MASK_HMEBOX_E2_8814B) << BIT_SHIFT_HMEBOX_E2_8814B) -#define BIT_GET_HMEBOX_E2_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8814B) & BIT_MASK_HMEBOX_E2_8814B) - - +#define BIT_HMEBOX_E2_8814B(x) \ + (((x) & BIT_MASK_HMEBOX_E2_8814B) << BIT_SHIFT_HMEBOX_E2_8814B) +#define BITS_HMEBOX_E2_8814B \ + (BIT_MASK_HMEBOX_E2_8814B << BIT_SHIFT_HMEBOX_E2_8814B) +#define BIT_CLEAR_HMEBOX_E2_8814B(x) ((x) & (~BITS_HMEBOX_E2_8814B)) +#define BIT_GET_HMEBOX_E2_8814B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E2_8814B) & BIT_MASK_HMEBOX_E2_8814B) +#define BIT_SET_HMEBOX_E2_8814B(x, v) \ + (BIT_CLEAR_HMEBOX_E2_8814B(x) | BIT_HMEBOX_E2_8814B(v)) /* 2 REG_HMEBOX_E3_8814B */ #define BIT_SHIFT_HMEBOX_E3_8814B 0 #define BIT_MASK_HMEBOX_E3_8814B 0xffffffffL -#define BIT_HMEBOX_E3_8814B(x) (((x) & BIT_MASK_HMEBOX_E3_8814B) << BIT_SHIFT_HMEBOX_E3_8814B) -#define BIT_GET_HMEBOX_E3_8814B(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8814B) & BIT_MASK_HMEBOX_E3_8814B) - - +#define BIT_HMEBOX_E3_8814B(x) \ + (((x) & BIT_MASK_HMEBOX_E3_8814B) << BIT_SHIFT_HMEBOX_E3_8814B) +#define BITS_HMEBOX_E3_8814B \ + (BIT_MASK_HMEBOX_E3_8814B << BIT_SHIFT_HMEBOX_E3_8814B) +#define BIT_CLEAR_HMEBOX_E3_8814B(x) ((x) & (~BITS_HMEBOX_E3_8814B)) +#define BIT_GET_HMEBOX_E3_8814B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E3_8814B) & BIT_MASK_HMEBOX_E3_8814B) +#define BIT_SET_HMEBOX_E3_8814B(x, v) \ + (BIT_CLEAR_HMEBOX_E3_8814B(x) | BIT_HMEBOX_E3_8814B(v)) /* 2 REG_CR_EXT_8814B */ #define BIT_SHIFT_PHY_REQ_DELAY_8814B 24 #define BIT_MASK_PHY_REQ_DELAY_8814B 0xf -#define BIT_PHY_REQ_DELAY_8814B(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8814B) << BIT_SHIFT_PHY_REQ_DELAY_8814B) -#define BIT_GET_PHY_REQ_DELAY_8814B(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8814B) & BIT_MASK_PHY_REQ_DELAY_8814B) - - +#define BIT_PHY_REQ_DELAY_8814B(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY_8814B) << BIT_SHIFT_PHY_REQ_DELAY_8814B) +#define BITS_PHY_REQ_DELAY_8814B \ + (BIT_MASK_PHY_REQ_DELAY_8814B << BIT_SHIFT_PHY_REQ_DELAY_8814B) +#define BIT_CLEAR_PHY_REQ_DELAY_8814B(x) ((x) & (~BITS_PHY_REQ_DELAY_8814B)) +#define BIT_GET_PHY_REQ_DELAY_8814B(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8814B) & BIT_MASK_PHY_REQ_DELAY_8814B) +#define BIT_SET_PHY_REQ_DELAY_8814B(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY_8814B(x) | BIT_PHY_REQ_DELAY_8814B(v)) /* 2 REG_NOT_VALID_8814B */ +#define BIT_FW_FIFO_PTR_RST_8814B BIT(18) +#define BIT_PHY_FIFO_PTR_RST_8814B BIT(17) #define BIT_SPD_DOWN_8814B BIT(16) /* 2 REG_NOT_VALID_8814B */ #define BIT_SHIFT_NETYPE4_8814B 4 #define BIT_MASK_NETYPE4_8814B 0x3 -#define BIT_NETYPE4_8814B(x) (((x) & BIT_MASK_NETYPE4_8814B) << BIT_SHIFT_NETYPE4_8814B) -#define BIT_GET_NETYPE4_8814B(x) (((x) >> BIT_SHIFT_NETYPE4_8814B) & BIT_MASK_NETYPE4_8814B) - - +#define BIT_NETYPE4_8814B(x) \ + (((x) & BIT_MASK_NETYPE4_8814B) << BIT_SHIFT_NETYPE4_8814B) +#define BITS_NETYPE4_8814B (BIT_MASK_NETYPE4_8814B << BIT_SHIFT_NETYPE4_8814B) +#define BIT_CLEAR_NETYPE4_8814B(x) ((x) & (~BITS_NETYPE4_8814B)) +#define BIT_GET_NETYPE4_8814B(x) \ + (((x) >> BIT_SHIFT_NETYPE4_8814B) & BIT_MASK_NETYPE4_8814B) +#define BIT_SET_NETYPE4_8814B(x, v) \ + (BIT_CLEAR_NETYPE4_8814B(x) | BIT_NETYPE4_8814B(v)) #define BIT_SHIFT_NETYPE3_8814B 2 #define BIT_MASK_NETYPE3_8814B 0x3 -#define BIT_NETYPE3_8814B(x) (((x) & BIT_MASK_NETYPE3_8814B) << BIT_SHIFT_NETYPE3_8814B) -#define BIT_GET_NETYPE3_8814B(x) (((x) >> BIT_SHIFT_NETYPE3_8814B) & BIT_MASK_NETYPE3_8814B) - - +#define BIT_NETYPE3_8814B(x) \ + (((x) & BIT_MASK_NETYPE3_8814B) << BIT_SHIFT_NETYPE3_8814B) +#define BITS_NETYPE3_8814B (BIT_MASK_NETYPE3_8814B << BIT_SHIFT_NETYPE3_8814B) +#define BIT_CLEAR_NETYPE3_8814B(x) ((x) & (~BITS_NETYPE3_8814B)) +#define BIT_GET_NETYPE3_8814B(x) \ + (((x) >> BIT_SHIFT_NETYPE3_8814B) & BIT_MASK_NETYPE3_8814B) +#define BIT_SET_NETYPE3_8814B(x, v) \ + (BIT_CLEAR_NETYPE3_8814B(x) | BIT_NETYPE3_8814B(v)) #define BIT_SHIFT_NETYPE2_8814B 0 #define BIT_MASK_NETYPE2_8814B 0x3 -#define BIT_NETYPE2_8814B(x) (((x) & BIT_MASK_NETYPE2_8814B) << BIT_SHIFT_NETYPE2_8814B) -#define BIT_GET_NETYPE2_8814B(x) (((x) >> BIT_SHIFT_NETYPE2_8814B) & BIT_MASK_NETYPE2_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_NETYPE2_8814B(x) \ + (((x) & BIT_MASK_NETYPE2_8814B) << BIT_SHIFT_NETYPE2_8814B) +#define BITS_NETYPE2_8814B (BIT_MASK_NETYPE2_8814B << BIT_SHIFT_NETYPE2_8814B) +#define BIT_CLEAR_NETYPE2_8814B(x) ((x) & (~BITS_NETYPE2_8814B)) +#define BIT_GET_NETYPE2_8814B(x) \ + (((x) >> BIT_SHIFT_NETYPE2_8814B) & BIT_MASK_NETYPE2_8814B) +#define BIT_SET_NETYPE2_8814B(x, v) \ + (BIT_CLEAR_NETYPE2_8814B(x) | BIT_NETYPE2_8814B(v)) + +/* 2 REG_TC9_CTRL_8814B */ +#define BIT_TC9INT_EN_8814B BIT(26) +#define BIT_TC9MODE_8814B BIT(25) +#define BIT_TC9EN_8814B BIT(24) + +#define BIT_SHIFT_TC9DATA_8814B 0 +#define BIT_MASK_TC9DATA_8814B 0xffffff +#define BIT_TC9DATA_8814B(x) \ + (((x) & BIT_MASK_TC9DATA_8814B) << BIT_SHIFT_TC9DATA_8814B) +#define BITS_TC9DATA_8814B (BIT_MASK_TC9DATA_8814B << BIT_SHIFT_TC9DATA_8814B) +#define BIT_CLEAR_TC9DATA_8814B(x) ((x) & (~BITS_TC9DATA_8814B)) +#define BIT_GET_TC9DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC9DATA_8814B) & BIT_MASK_TC9DATA_8814B) +#define BIT_SET_TC9DATA_8814B(x, v) \ + (BIT_CLEAR_TC9DATA_8814B(x) | BIT_TC9DATA_8814B(v)) + +/* 2 REG_TC10_CTRL_8814B */ +#define BIT_TC10INT_EN_8814B BIT(26) +#define BIT_TC10MODE_8814B BIT(25) +#define BIT_TC10EN_8814B BIT(24) + +#define BIT_SHIFT_TC10DATA_8814B 0 +#define BIT_MASK_TC10DATA_8814B 0xffffff +#define BIT_TC10DATA_8814B(x) \ + (((x) & BIT_MASK_TC10DATA_8814B) << BIT_SHIFT_TC10DATA_8814B) +#define BITS_TC10DATA_8814B \ + (BIT_MASK_TC10DATA_8814B << BIT_SHIFT_TC10DATA_8814B) +#define BIT_CLEAR_TC10DATA_8814B(x) ((x) & (~BITS_TC10DATA_8814B)) +#define BIT_GET_TC10DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC10DATA_8814B) & BIT_MASK_TC10DATA_8814B) +#define BIT_SET_TC10DATA_8814B(x, v) \ + (BIT_CLEAR_TC10DATA_8814B(x) | BIT_TC10DATA_8814B(v)) + +/* 2 REG_TC11_CTRL_8814B */ +#define BIT_TC11INT_EN_8814B BIT(26) +#define BIT_TC11MODE_8814B BIT(25) +#define BIT_TC11EN_8814B BIT(24) + +#define BIT_SHIFT_TC11DATA_8814B 0 +#define BIT_MASK_TC11DATA_8814B 0xffffff +#define BIT_TC11DATA_8814B(x) \ + (((x) & BIT_MASK_TC11DATA_8814B) << BIT_SHIFT_TC11DATA_8814B) +#define BITS_TC11DATA_8814B \ + (BIT_MASK_TC11DATA_8814B << BIT_SHIFT_TC11DATA_8814B) +#define BIT_CLEAR_TC11DATA_8814B(x) ((x) & (~BITS_TC11DATA_8814B)) +#define BIT_GET_TC11DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC11DATA_8814B) & BIT_MASK_TC11DATA_8814B) +#define BIT_SET_TC11DATA_8814B(x, v) \ + (BIT_CLEAR_TC11DATA_8814B(x) | BIT_TC11DATA_8814B(v)) + +/* 2 REG_TC12_CTRL_8814B */ +#define BIT_TC12INT_EN_8814B BIT(26) +#define BIT_TC12MODE_8814B BIT(25) +#define BIT_TC12EN_8814B BIT(24) + +#define BIT_SHIFT_TC12DATA_8814B 0 +#define BIT_MASK_TC12DATA_8814B 0xffffff +#define BIT_TC12DATA_8814B(x) \ + (((x) & BIT_MASK_TC12DATA_8814B) << BIT_SHIFT_TC12DATA_8814B) +#define BITS_TC12DATA_8814B \ + (BIT_MASK_TC12DATA_8814B << BIT_SHIFT_TC12DATA_8814B) +#define BIT_CLEAR_TC12DATA_8814B(x) ((x) & (~BITS_TC12DATA_8814B)) +#define BIT_GET_TC12DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC12DATA_8814B) & BIT_MASK_TC12DATA_8814B) +#define BIT_SET_TC12DATA_8814B(x, v) \ + (BIT_CLEAR_TC12DATA_8814B(x) | BIT_TC12DATA_8814B(v)) /* 2 REG_FWFF_8814B */ #define BIT_SHIFT_PKTNUM_TH_V1_8814B 24 #define BIT_MASK_PKTNUM_TH_V1_8814B 0xff -#define BIT_PKTNUM_TH_V1_8814B(x) (((x) & BIT_MASK_PKTNUM_TH_V1_8814B) << BIT_SHIFT_PKTNUM_TH_V1_8814B) -#define BIT_GET_PKTNUM_TH_V1_8814B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8814B) & BIT_MASK_PKTNUM_TH_V1_8814B) - - +#define BIT_PKTNUM_TH_V1_8814B(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V1_8814B) << BIT_SHIFT_PKTNUM_TH_V1_8814B) +#define BITS_PKTNUM_TH_V1_8814B \ + (BIT_MASK_PKTNUM_TH_V1_8814B << BIT_SHIFT_PKTNUM_TH_V1_8814B) +#define BIT_CLEAR_PKTNUM_TH_V1_8814B(x) ((x) & (~BITS_PKTNUM_TH_V1_8814B)) +#define BIT_GET_PKTNUM_TH_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8814B) & BIT_MASK_PKTNUM_TH_V1_8814B) +#define BIT_SET_PKTNUM_TH_V1_8814B(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V1_8814B(x) | BIT_PKTNUM_TH_V1_8814B(v)) #define BIT_SHIFT_TIMER_TH_8814B 16 #define BIT_MASK_TIMER_TH_8814B 0xff -#define BIT_TIMER_TH_8814B(x) (((x) & BIT_MASK_TIMER_TH_8814B) << BIT_SHIFT_TIMER_TH_8814B) -#define BIT_GET_TIMER_TH_8814B(x) (((x) >> BIT_SHIFT_TIMER_TH_8814B) & BIT_MASK_TIMER_TH_8814B) - - +#define BIT_TIMER_TH_8814B(x) \ + (((x) & BIT_MASK_TIMER_TH_8814B) << BIT_SHIFT_TIMER_TH_8814B) +#define BITS_TIMER_TH_8814B \ + (BIT_MASK_TIMER_TH_8814B << BIT_SHIFT_TIMER_TH_8814B) +#define BIT_CLEAR_TIMER_TH_8814B(x) ((x) & (~BITS_TIMER_TH_8814B)) +#define BIT_GET_TIMER_TH_8814B(x) \ + (((x) >> BIT_SHIFT_TIMER_TH_8814B) & BIT_MASK_TIMER_TH_8814B) +#define BIT_SET_TIMER_TH_8814B(x, v) \ + (BIT_CLEAR_TIMER_TH_8814B(x) | BIT_TIMER_TH_8814B(v)) #define BIT_SHIFT_RXPKT1ENADDR_8814B 0 #define BIT_MASK_RXPKT1ENADDR_8814B 0xffff -#define BIT_RXPKT1ENADDR_8814B(x) (((x) & BIT_MASK_RXPKT1ENADDR_8814B) << BIT_SHIFT_RXPKT1ENADDR_8814B) -#define BIT_GET_RXPKT1ENADDR_8814B(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8814B) & BIT_MASK_RXPKT1ENADDR_8814B) - - +#define BIT_RXPKT1ENADDR_8814B(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR_8814B) << BIT_SHIFT_RXPKT1ENADDR_8814B) +#define BITS_RXPKT1ENADDR_8814B \ + (BIT_MASK_RXPKT1ENADDR_8814B << BIT_SHIFT_RXPKT1ENADDR_8814B) +#define BIT_CLEAR_RXPKT1ENADDR_8814B(x) ((x) & (~BITS_RXPKT1ENADDR_8814B)) +#define BIT_GET_RXPKT1ENADDR_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR_8814B) & BIT_MASK_RXPKT1ENADDR_8814B) +#define BIT_SET_RXPKT1ENADDR_8814B(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR_8814B(x) | BIT_RXPKT1ENADDR_8814B(v)) /* 2 REG_RXFF_PTR_V1_8814B */ @@ -3038,10 +5563,17 @@ #define BIT_SHIFT_RXFF0_RDPTR_V2_8814B 0 #define BIT_MASK_RXFF0_RDPTR_V2_8814B 0x3ffff -#define BIT_RXFF0_RDPTR_V2_8814B(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8814B) << BIT_SHIFT_RXFF0_RDPTR_V2_8814B) -#define BIT_GET_RXFF0_RDPTR_V2_8814B(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8814B) & BIT_MASK_RXFF0_RDPTR_V2_8814B) - - +#define BIT_RXFF0_RDPTR_V2_8814B(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2_8814B) \ + << BIT_SHIFT_RXFF0_RDPTR_V2_8814B) +#define BITS_RXFF0_RDPTR_V2_8814B \ + (BIT_MASK_RXFF0_RDPTR_V2_8814B << BIT_SHIFT_RXFF0_RDPTR_V2_8814B) +#define BIT_CLEAR_RXFF0_RDPTR_V2_8814B(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8814B)) +#define BIT_GET_RXFF0_RDPTR_V2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8814B) & \ + BIT_MASK_RXFF0_RDPTR_V2_8814B) +#define BIT_SET_RXFF0_RDPTR_V2_8814B(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2_8814B(x) | BIT_RXFF0_RDPTR_V2_8814B(v)) /* 2 REG_RXFF_WTR_V1_8814B */ @@ -3049,10 +5581,17 @@ #define BIT_SHIFT_RXFF0_WTPTR_V2_8814B 0 #define BIT_MASK_RXFF0_WTPTR_V2_8814B 0x3ffff -#define BIT_RXFF0_WTPTR_V2_8814B(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8814B) << BIT_SHIFT_RXFF0_WTPTR_V2_8814B) -#define BIT_GET_RXFF0_WTPTR_V2_8814B(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8814B) & BIT_MASK_RXFF0_WTPTR_V2_8814B) - - +#define BIT_RXFF0_WTPTR_V2_8814B(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2_8814B) \ + << BIT_SHIFT_RXFF0_WTPTR_V2_8814B) +#define BITS_RXFF0_WTPTR_V2_8814B \ + (BIT_MASK_RXFF0_WTPTR_V2_8814B << BIT_SHIFT_RXFF0_WTPTR_V2_8814B) +#define BIT_CLEAR_RXFF0_WTPTR_V2_8814B(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8814B)) +#define BIT_GET_RXFF0_WTPTR_V2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8814B) & \ + BIT_MASK_RXFF0_WTPTR_V2_8814B) +#define BIT_SET_RXFF0_WTPTR_V2_8814B(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2_8814B(x) | BIT_RXFF0_WTPTR_V2_8814B(v)) /* 2 REG_FE2IMR_8814B */ #define BIT__FE4ISR__IND_MSK_8814B BIT(29) @@ -3173,15 +5712,31 @@ #define BIT_FS_BCNERLY0_INT_8814B BIT(0) /* 2 REG_FE4IMR_8814B */ -#define BIT_FS_CLI3_TXPKTIN_INT_EN_8814B BIT(19) -#define BIT_FS_CLI2_TXPKTIN_INT_EN_8814B BIT(18) -#define BIT_FS_CLI1_TXPKTIN_INT_EN_8814B BIT(17) -#define BIT_FS_CLI0_TXPKTIN_INT_EN_8814B BIT(16) -#define BIT_FS_CLI3_RX_UMD0_INT_EN_8814B BIT(15) -#define BIT_FS_CLI3_RX_UMD1_INT_EN_8814B BIT(14) -#define BIT_FS_CLI3_RX_BMD0_INT_EN_8814B BIT(13) -#define BIT_FS_CLI3_RX_BMD1_INT_EN_8814B BIT(12) -#define BIT_FS_CLI2_RX_UMD0_INT_EN_8814B BIT(11) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_FS_CLI3_TXPKTIN_INT_EN_8814B BIT(19) +#define BIT_FS_CLI2_TXPKTIN_INT_EN_8814B BIT(18) +#define BIT_FS_CLI1_TXPKTIN_INT_EN_8814B BIT(17) +#define BIT_FS_CLI0_TXPKTIN_INT_EN_8814B BIT(16) +#define BIT_FS_CLI3_RX_UMD0_INT_EN_8814B BIT(15) +#define BIT_FS_CLI3_RX_UMD1_INT_EN_8814B BIT(14) +#define BIT_FS_CLI3_RX_BMD0_INT_EN_8814B BIT(13) +#define BIT_FS_CLI3_RX_BMD1_INT_EN_8814B BIT(12) +#define BIT_FS_CLI2_RX_UMD0_INT_EN_8814B BIT(11) #define BIT_FS_CLI2_RX_UMD1_INT_EN_8814B BIT(10) #define BIT_FS_CLI2_RX_BMD0_INT_EN_8814B BIT(9) #define BIT_FS_CLI2_RX_BMD1_INT_EN_8814B BIT(8) @@ -3195,6 +5750,25 @@ #define BIT_FS_CLI0_RX_BMD1_INT_EN_8814B BIT(0) /* 2 REG_FE4ISR_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_P2P_PWROFF_NOA2_ERLY_INT_8814B BIT(22) +#define BIT_P2P_PWROFF_NOA1_ERLY_INT_8814B BIT(21) +#define BIT_P2P_PWROFF_NOA0_ERLY_INT_8814B BIT(20) #define BIT_FS_CLI3_TXPKTIN_INT_8814B BIT(19) #define BIT_FS_CLI2_TXPKTIN_INT_8814B BIT(18) #define BIT_FS_CLI1_TXPKTIN_INT_8814B BIT(17) @@ -3224,8 +5798,7 @@ #define BIT_TXFTM_INT_EN_8814B BIT(26) #define BIT_FS_H2C_CMD_OK_INT_EN_8814B BIT(25) #define BIT_FS_H2C_CMD_FULL_INT_EN_8814B BIT(24) -#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8814B BIT(23) -#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8814B BIT(22) +#define BIT_FS_MACID_SEARCH_FAIL_INT_EN_8814B BIT(22) #define BIT_FS_MACID_PWRCHANGE3_INT_EN_8814B BIT(21) #define BIT_FS_MACID_PWRCHANGE2_INT_EN_8814B BIT(20) #define BIT_FS_MACID_PWRCHANGE1_INT_EN_8814B BIT(19) @@ -3257,8 +5830,7 @@ #define BIT_TXFTM_INT_8814B BIT(26) #define BIT_FS_H2C_CMD_OK_INT_8814B BIT(25) #define BIT_FS_H2C_CMD_FULL_INT_8814B BIT(24) -#define BIT_FS_MACID_PWRCHANGE5_INT_8814B BIT(23) -#define BIT_FS_MACID_PWRCHANGE4_INT_8814B BIT(22) +#define BIT_FS_MACID_SEARCH_FAIL_INT_8814B BIT(22) #define BIT_FS_MACID_PWRCHANGE3_INT_8814B BIT(21) #define BIT_FS_MACID_PWRCHANGE2_INT_8814B BIT(20) #define BIT_FS_MACID_PWRCHANGE1_INT_8814B BIT(19) @@ -3286,53 +5858,82 @@ #define BIT_SHIFT_MID_31TO0_8814B 0 #define BIT_MASK_MID_31TO0_8814B 0xffffffffL -#define BIT_MID_31TO0_8814B(x) (((x) & BIT_MASK_MID_31TO0_8814B) << BIT_SHIFT_MID_31TO0_8814B) -#define BIT_GET_MID_31TO0_8814B(x) (((x) >> BIT_SHIFT_MID_31TO0_8814B) & BIT_MASK_MID_31TO0_8814B) - - +#define BIT_MID_31TO0_8814B(x) \ + (((x) & BIT_MASK_MID_31TO0_8814B) << BIT_SHIFT_MID_31TO0_8814B) +#define BITS_MID_31TO0_8814B \ + (BIT_MASK_MID_31TO0_8814B << BIT_SHIFT_MID_31TO0_8814B) +#define BIT_CLEAR_MID_31TO0_8814B(x) ((x) & (~BITS_MID_31TO0_8814B)) +#define BIT_GET_MID_31TO0_8814B(x) \ + (((x) >> BIT_SHIFT_MID_31TO0_8814B) & BIT_MASK_MID_31TO0_8814B) +#define BIT_SET_MID_31TO0_8814B(x, v) \ + (BIT_CLEAR_MID_31TO0_8814B(x) | BIT_MID_31TO0_8814B(v)) /* 2 REG_SPWR1_8814B */ #define BIT_SHIFT_MID_63TO32_8814B 0 #define BIT_MASK_MID_63TO32_8814B 0xffffffffL -#define BIT_MID_63TO32_8814B(x) (((x) & BIT_MASK_MID_63TO32_8814B) << BIT_SHIFT_MID_63TO32_8814B) -#define BIT_GET_MID_63TO32_8814B(x) (((x) >> BIT_SHIFT_MID_63TO32_8814B) & BIT_MASK_MID_63TO32_8814B) - - +#define BIT_MID_63TO32_8814B(x) \ + (((x) & BIT_MASK_MID_63TO32_8814B) << BIT_SHIFT_MID_63TO32_8814B) +#define BITS_MID_63TO32_8814B \ + (BIT_MASK_MID_63TO32_8814B << BIT_SHIFT_MID_63TO32_8814B) +#define BIT_CLEAR_MID_63TO32_8814B(x) ((x) & (~BITS_MID_63TO32_8814B)) +#define BIT_GET_MID_63TO32_8814B(x) \ + (((x) >> BIT_SHIFT_MID_63TO32_8814B) & BIT_MASK_MID_63TO32_8814B) +#define BIT_SET_MID_63TO32_8814B(x, v) \ + (BIT_CLEAR_MID_63TO32_8814B(x) | BIT_MID_63TO32_8814B(v)) /* 2 REG_SPWR2_8814B */ #define BIT_SHIFT_MID_95O64_8814B 0 #define BIT_MASK_MID_95O64_8814B 0xffffffffL -#define BIT_MID_95O64_8814B(x) (((x) & BIT_MASK_MID_95O64_8814B) << BIT_SHIFT_MID_95O64_8814B) -#define BIT_GET_MID_95O64_8814B(x) (((x) >> BIT_SHIFT_MID_95O64_8814B) & BIT_MASK_MID_95O64_8814B) - - +#define BIT_MID_95O64_8814B(x) \ + (((x) & BIT_MASK_MID_95O64_8814B) << BIT_SHIFT_MID_95O64_8814B) +#define BITS_MID_95O64_8814B \ + (BIT_MASK_MID_95O64_8814B << BIT_SHIFT_MID_95O64_8814B) +#define BIT_CLEAR_MID_95O64_8814B(x) ((x) & (~BITS_MID_95O64_8814B)) +#define BIT_GET_MID_95O64_8814B(x) \ + (((x) >> BIT_SHIFT_MID_95O64_8814B) & BIT_MASK_MID_95O64_8814B) +#define BIT_SET_MID_95O64_8814B(x, v) \ + (BIT_CLEAR_MID_95O64_8814B(x) | BIT_MID_95O64_8814B(v)) /* 2 REG_SPWR3_8814B */ #define BIT_SHIFT_MID_127TO96_8814B 0 #define BIT_MASK_MID_127TO96_8814B 0xffffffffL -#define BIT_MID_127TO96_8814B(x) (((x) & BIT_MASK_MID_127TO96_8814B) << BIT_SHIFT_MID_127TO96_8814B) -#define BIT_GET_MID_127TO96_8814B(x) (((x) >> BIT_SHIFT_MID_127TO96_8814B) & BIT_MASK_MID_127TO96_8814B) - - +#define BIT_MID_127TO96_8814B(x) \ + (((x) & BIT_MASK_MID_127TO96_8814B) << BIT_SHIFT_MID_127TO96_8814B) +#define BITS_MID_127TO96_8814B \ + (BIT_MASK_MID_127TO96_8814B << BIT_SHIFT_MID_127TO96_8814B) +#define BIT_CLEAR_MID_127TO96_8814B(x) ((x) & (~BITS_MID_127TO96_8814B)) +#define BIT_GET_MID_127TO96_8814B(x) \ + (((x) >> BIT_SHIFT_MID_127TO96_8814B) & BIT_MASK_MID_127TO96_8814B) +#define BIT_SET_MID_127TO96_8814B(x, v) \ + (BIT_CLEAR_MID_127TO96_8814B(x) | BIT_MID_127TO96_8814B(v)) /* 2 REG_POWSEQ_8814B */ #define BIT_SHIFT_SEQNUM_MID_8814B 16 #define BIT_MASK_SEQNUM_MID_8814B 0xffff -#define BIT_SEQNUM_MID_8814B(x) (((x) & BIT_MASK_SEQNUM_MID_8814B) << BIT_SHIFT_SEQNUM_MID_8814B) -#define BIT_GET_SEQNUM_MID_8814B(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8814B) & BIT_MASK_SEQNUM_MID_8814B) - - +#define BIT_SEQNUM_MID_8814B(x) \ + (((x) & BIT_MASK_SEQNUM_MID_8814B) << BIT_SHIFT_SEQNUM_MID_8814B) +#define BITS_SEQNUM_MID_8814B \ + (BIT_MASK_SEQNUM_MID_8814B << BIT_SHIFT_SEQNUM_MID_8814B) +#define BIT_CLEAR_SEQNUM_MID_8814B(x) ((x) & (~BITS_SEQNUM_MID_8814B)) +#define BIT_GET_SEQNUM_MID_8814B(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID_8814B) & BIT_MASK_SEQNUM_MID_8814B) +#define BIT_SET_SEQNUM_MID_8814B(x, v) \ + (BIT_CLEAR_SEQNUM_MID_8814B(x) | BIT_SEQNUM_MID_8814B(v)) #define BIT_SHIFT_REF_MID_8814B 0 #define BIT_MASK_REF_MID_8814B 0x7f -#define BIT_REF_MID_8814B(x) (((x) & BIT_MASK_REF_MID_8814B) << BIT_SHIFT_REF_MID_8814B) -#define BIT_GET_REF_MID_8814B(x) (((x) >> BIT_SHIFT_REF_MID_8814B) & BIT_MASK_REF_MID_8814B) - - +#define BIT_REF_MID_8814B(x) \ + (((x) & BIT_MASK_REF_MID_8814B) << BIT_SHIFT_REF_MID_8814B) +#define BITS_REF_MID_8814B (BIT_MASK_REF_MID_8814B << BIT_SHIFT_REF_MID_8814B) +#define BIT_CLEAR_REF_MID_8814B(x) ((x) & (~BITS_REF_MID_8814B)) +#define BIT_GET_REF_MID_8814B(x) \ + (((x) >> BIT_SHIFT_REF_MID_8814B) & BIT_MASK_REF_MID_8814B) +#define BIT_SET_REF_MID_8814B(x, v) \ + (BIT_CLEAR_REF_MID_8814B(x) | BIT_REF_MID_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -3343,10 +5944,14 @@ #define BIT_SHIFT_TC7DATA_8814B 0 #define BIT_MASK_TC7DATA_8814B 0xffffff -#define BIT_TC7DATA_8814B(x) (((x) & BIT_MASK_TC7DATA_8814B) << BIT_SHIFT_TC7DATA_8814B) -#define BIT_GET_TC7DATA_8814B(x) (((x) >> BIT_SHIFT_TC7DATA_8814B) & BIT_MASK_TC7DATA_8814B) - - +#define BIT_TC7DATA_8814B(x) \ + (((x) & BIT_MASK_TC7DATA_8814B) << BIT_SHIFT_TC7DATA_8814B) +#define BITS_TC7DATA_8814B (BIT_MASK_TC7DATA_8814B << BIT_SHIFT_TC7DATA_8814B) +#define BIT_CLEAR_TC7DATA_8814B(x) ((x) & (~BITS_TC7DATA_8814B)) +#define BIT_GET_TC7DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC7DATA_8814B) & BIT_MASK_TC7DATA_8814B) +#define BIT_SET_TC7DATA_8814B(x, v) \ + (BIT_CLEAR_TC7DATA_8814B(x) | BIT_TC7DATA_8814B(v)) /* 2 REG_TC8_CTRL_V1_8814B */ #define BIT_TC8INT_EN_8814B BIT(26) @@ -3355,74 +5960,782 @@ #define BIT_SHIFT_TC8DATA_8814B 0 #define BIT_MASK_TC8DATA_8814B 0xffffff -#define BIT_TC8DATA_8814B(x) (((x) & BIT_MASK_TC8DATA_8814B) << BIT_SHIFT_TC8DATA_8814B) -#define BIT_GET_TC8DATA_8814B(x) (((x) >> BIT_SHIFT_TC8DATA_8814B) & BIT_MASK_TC8DATA_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_TC8DATA_8814B(x) \ + (((x) & BIT_MASK_TC8DATA_8814B) << BIT_SHIFT_TC8DATA_8814B) +#define BITS_TC8DATA_8814B (BIT_MASK_TC8DATA_8814B << BIT_SHIFT_TC8DATA_8814B) +#define BIT_CLEAR_TC8DATA_8814B(x) ((x) & (~BITS_TC8DATA_8814B)) +#define BIT_GET_TC8DATA_8814B(x) \ + (((x) >> BIT_SHIFT_TC8DATA_8814B) & BIT_MASK_TC8DATA_8814B) +#define BIT_SET_TC8DATA_8814B(x, v) \ + (BIT_CLEAR_TC8DATA_8814B(x) | BIT_TC8DATA_8814B(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL0_8814B */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B 24 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8814B \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8814B)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT2_8814B(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B 16 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8814B \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8814B)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT1_8814B(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B 8 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8814B \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8814B)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT0_8814B(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B 0xff +#define BIT_RX_BCN_TBTT_ITVL_PORT0_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B) +#define BITS_RX_BCN_TBTT_ITVL_PORT0_8814B \ + (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8814B(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8814B)) +#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B) +#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8814B(x) | \ + BIT_RX_BCN_TBTT_ITVL_PORT0_8814B(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL1_8814B */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8814B \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8814B)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT3_8814B(v)) + +/* 2 REG_FWIMR1_8814B */ +#define BIT_FS_ATIM_MB15_INT_EN_8814B BIT(31) +#define BIT_FS_ATIM_MB14_INT_EN_8814B BIT(30) +#define BIT_FS_ATIM_MB13_INT_EN_8814B BIT(29) +#define BIT_FS_ATIM_MB12_INT_EN_8814B BIT(28) +#define BIT_FS_ATIM_MB11_INT_EN_8814B BIT(27) +#define BIT_FS_ATIM_MB10_INT_EN_8814B BIT(26) +#define BIT_FS_ATIM_MB9_INT_EN_8814B BIT(25) +#define BIT_FS_ATIM_MB8_INT_EN_8814B BIT(24) +#define BIT_FS_TXBCNERR_MB15_INT_EN_8814B BIT(23) +#define BIT_FS_TXBCNERR_MB14_INT_EN_8814B BIT(22) +#define BIT_FS_TXBCNERR_MB13_INT_EN_8814B BIT(21) +#define BIT_FS_TXBCNERR_MB12_INT_EN_8814B BIT(20) +#define BIT_FS_TXBCNERR_MB11_INT_EN_8814B BIT(19) +#define BIT_FS_TXBCNERR_MB10_INT_EN_8814B BIT(18) +#define BIT_FS_TXBCNERR_MB9_INT_EN_8814B BIT(17) +#define BIT_FS_TXBCNERR_MB8_INT_EN_8814B BIT(16) +#define BIT_FS_TXBCNOK_MB15_INT_EN_8814B BIT(15) +#define BIT_FS_TXBCNOK_MB14_INT_EN_8814B BIT(14) +#define BIT_FS_TXBCNOK_MB13_INT_EN_8814B BIT(13) +#define BIT_FS_TXBCNOK_MB12_INT_EN_8814B BIT(12) +#define BIT_FS_TXBCNOK_MB11_INT_EN_8814B BIT(11) +#define BIT_FS_TXBCNOK_MB10_INT_EN_8814B BIT(10) +#define BIT_FS_TXBCNOK_MB9_INT_EN_8814B BIT(9) +#define BIT_FS_TXBCNOK_MB8_INT_EN_8814B BIT(8) +#define BIT_FS_BCNERLY0_MB15INT_EN_8814B BIT(7) +#define BIT_FS_BCNERLY0_MB14INT_EN_8814B BIT(6) +#define BIT_FS_BCNERLY0_MB13INT_EN_8814B BIT(5) +#define BIT_FS_BCNERLY0_MB12INT_EN_8814B BIT(4) +#define BIT_FS_BCNERLY0_MB11INT_EN_8814B BIT(3) +#define BIT_FS_BCNERLY0_MB10INT_EN_8814B BIT(2) +#define BIT_FS_BCNERLY0_MB9INT_EN_8814B BIT(1) +#define BIT_FS_BCNERLY0_MB8INT_EN_8814B BIT(0) + +/* 2 REG_FWISR1_8814B */ +#define BIT_FS_ATIM_MB15_INT_8814B BIT(31) +#define BIT_FS_ATIM_MB14_INT_8814B BIT(30) +#define BIT_FS_ATIM_MB13_INT_8814B BIT(29) +#define BIT_FS_ATIM_MB12_INT_8814B BIT(28) +#define BIT_FS_ATIM_MB11_INT_8814B BIT(27) +#define BIT_FS_ATIM_MB10_INT_8814B BIT(26) +#define BIT_FS_ATIM_MB9_INT_8814B BIT(25) +#define BIT_FS_ATIM_MB8_INT_8814B BIT(24) +#define BIT_FS_TXBCNERR_MB15_INT_8814B BIT(23) +#define BIT_FS_TXBCNERR_MB14_INT_8814B BIT(22) +#define BIT_FS_TXBCNERR_MB13_INT_8814B BIT(21) +#define BIT_FS_TXBCNERR_MB12_INT_8814B BIT(20) +#define BIT_FS_TXBCNERR_MB11_INT_8814B BIT(19) +#define BIT_FS_TXBCNERR_MB10_INT_8814B BIT(18) +#define BIT_FS_TXBCNERR_MB9_INT_8814B BIT(17) +#define BIT_FS_TXBCNERR_MB8_INT_8814B BIT(16) +#define BIT_FS_TXBCNOK_MB15_INT_8814B BIT(15) +#define BIT_FS_TXBCNOK_MB14_INT_8814B BIT(14) +#define BIT_FS_TXBCNOK_MB13_INT_8814B BIT(13) +#define BIT_FS_TXBCNOK_MB12_INT_8814B BIT(12) +#define BIT_FS_TXBCNOK_MB11_INT_8814B BIT(11) +#define BIT_FS_TXBCNOK_MB10_INT_8814B BIT(10) +#define BIT_FS_TXBCNOK_MB9_INT_8814B BIT(9) +#define BIT_FS_TXBCNOK_MB8_INT_8814B BIT(8) +#define BIT_FS_BCNERLY0_MB15INT_8814B BIT(7) +#define BIT_FS_BCNERLY0_MB14INT_8814B BIT(6) +#define BIT_FS_BCNERLY0_MB13INT_8814B BIT(5) +#define BIT_FS_BCNERLY0_MB12INT_8814B BIT(4) +#define BIT_FS_BCNERLY0_MB11INT_8814B BIT(3) +#define BIT_FS_BCNERLY0_MB10INT_8814B BIT(2) +#define BIT_FS_BCNERLY0_MB9INT_8814B BIT(1) +#define BIT_FS_BCNERLY0_MB8INT_8814B BIT(0) + +/* 2 REG_FWIMR2_8814B */ +#define BIT_FS_BCNDMA0_MB15_INT_EN_8814B BIT(15) +#define BIT_FS_BCNDMA0_MB14_INT_EN_8814B BIT(14) +#define BIT_FS_BCNDMA0_MB13_INT_EN_8814B BIT(13) +#define BIT_FS_BCNDMA0_MB12_INT_EN_8814B BIT(12) +#define BIT_FS_BCNDMA0_MB11_INT_EN_8814B BIT(11) +#define BIT_FS_BCNDMA0_MB10_INT_EN_8814B BIT(10) +#define BIT_FS_BCNDMA0_MB9_INT_EN_8814B BIT(9) +#define BIT_FS_BCNDMA0_MB8_INT_EN_8814B BIT(8) +#define BIT_FS_TBTT0_MB15INT_EN_8814B BIT(7) +#define BIT_FS_TBTT0_MB14INT_EN_8814B BIT(6) +#define BIT_FS_TBTT0_MB13INT_EN_8814B BIT(5) +#define BIT_FS_TBTT0_MB12INT_EN_8814B BIT(4) +#define BIT_FS_TBTT0_MB11INT_EN_8814B BIT(3) +#define BIT_FS_TBTT0_MB10INT_EN_8814B BIT(2) +#define BIT_FS_TBTT0_MB9INT_EN_8814B BIT(1) +#define BIT_FS_TBTT0_MB8INT_EN_8814B BIT(0) + +/* 2 REG_FWISR2_8814B */ +#define BIT_FS_BCNDMA0_MB15_INT_8814B BIT(15) +#define BIT_FS_BCNDMA0_MB14_INT_8814B BIT(14) +#define BIT_FS_BCNDMA0_MB13_INT_8814B BIT(13) +#define BIT_FS_BCNDMA0_MB12_INT_8814B BIT(12) +#define BIT_FS_BCNDMA0_MB11_INT_8814B BIT(11) +#define BIT_FS_BCNDMA0_MB10_INT_8814B BIT(10) +#define BIT_FS_BCNDMA0_MB9_INT_8814B BIT(9) +#define BIT_FS_BCNDMA0_MB8_INT_8814B BIT(8) +#define BIT_FS_TBTT0_MB15INT_8814B BIT(7) +#define BIT_FS_TBTT0_MB14INT_8814B BIT(6) +#define BIT_FS_TBTT0_MB13INT_8814B BIT(5) +#define BIT_FS_TBTT0_MB12INT_8814B BIT(4) +#define BIT_FS_TBTT0_MB11INT_8814B BIT(3) +#define BIT_FS_TBTT0_MB10INT_8814B BIT(2) +#define BIT_FS_TBTT0_MB9INT_8814B BIT(1) +#define BIT_FS_TBTT0_MB8INT_8814B BIT(0) + +/* 2 REG_FWIMR3_8814B */ /* 2 REG_NOT_VALID_8814B */ +#define BIT_FS_TXBCNOK_PORT4_INT_EN_8814B BIT(11) +#define BIT_FS_TXBCNOK_PORT3_INT_EN_8814B BIT(10) +#define BIT_FS_TXBCNOK_PORT2_INT_EN_8814B BIT(9) +#define BIT_FS_TXBCNOK_PORT1_INT_EN_8814B BIT(8) +#define BIT_FS_TXBCNERR_PORT4_INT_EN_8814B BIT(7) +#define BIT_FS_TXBCNERR_PORT3_INT_EN_8814B BIT(6) +#define BIT_FS_TXBCNERR_PORT2_INT_EN_8814B BIT(5) +#define BIT_FS_TXBCNERR_PORT1_INT_EN_8814B BIT(4) +#define BIT_FS_ATIM_PORT4_INT_EN_8814B BIT(3) +#define BIT_FS_ATIM_PORT3_INT_EN_8814B BIT(2) +#define BIT_FS_ATIM_PORT2_INT_EN_8814B BIT(1) +#define BIT_FS_ATIM_PORT1_INT_EN_8814B BIT(0) + +/* 2 REG_FWISR3_8814B */ +#define BIT_FS_TXBCNOK_PORT4_INT_8814B BIT(11) +#define BIT_FS_TXBCNOK_PORT3_INT_8814B BIT(10) +#define BIT_FS_TXBCNOK_PORT2_INT_8814B BIT(9) +#define BIT_FS_TXBCNOK_PORT1_INT_8814B BIT(8) +#define BIT_FS_TXBCNERR_PORT4_INT_8814B BIT(7) +#define BIT_FS_TXBCNERR_PORT3_INT_8814B BIT(6) +#define BIT_FS_TXBCNERR_PORT2_INT_8814B BIT(5) +#define BIT_FS_TXBCNERR_PORT1_INT_8814B BIT(4) +#define BIT_FS_ATIM_PORT4_INT_8814B BIT(3) +#define BIT_FS_ATIM_PORT3_INT_8814B BIT(2) +#define BIT_FS_ATIM_PORT2_INT_8814B BIT(1) +#define BIT_FS_ATIM_PORT1_INT_8814B BIT(0) + +/* 2 REG_SPEED_SENSOR_8814B */ +#define BIT_DSS_1_RST_N_8814B BIT(31) +#define BIT_DSS_1_SPEED_EN_8814B BIT(30) +#define BIT_DSS_1_WIRE_SEL_8814B BIT(29) +#define BIT_DSS_ENCLK_8814B BIT(28) + +#define BIT_SHIFT_DSS_1_RO_SEL_8814B 24 +#define BIT_MASK_DSS_1_RO_SEL_8814B 0x7 +#define BIT_DSS_1_RO_SEL_8814B(x) \ + (((x) & BIT_MASK_DSS_1_RO_SEL_8814B) << BIT_SHIFT_DSS_1_RO_SEL_8814B) +#define BITS_DSS_1_RO_SEL_8814B \ + (BIT_MASK_DSS_1_RO_SEL_8814B << BIT_SHIFT_DSS_1_RO_SEL_8814B) +#define BIT_CLEAR_DSS_1_RO_SEL_8814B(x) ((x) & (~BITS_DSS_1_RO_SEL_8814B)) +#define BIT_GET_DSS_1_RO_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_1_RO_SEL_8814B) & BIT_MASK_DSS_1_RO_SEL_8814B) +#define BIT_SET_DSS_1_RO_SEL_8814B(x, v) \ + (BIT_CLEAR_DSS_1_RO_SEL_8814B(x) | BIT_DSS_1_RO_SEL_8814B(v)) + +#define BIT_SHIFT_DSS_1_DATA_IN_8814B 0 +#define BIT_MASK_DSS_1_DATA_IN_8814B 0xfffff +#define BIT_DSS_1_DATA_IN_8814B(x) \ + (((x) & BIT_MASK_DSS_1_DATA_IN_8814B) << BIT_SHIFT_DSS_1_DATA_IN_8814B) +#define BITS_DSS_1_DATA_IN_8814B \ + (BIT_MASK_DSS_1_DATA_IN_8814B << BIT_SHIFT_DSS_1_DATA_IN_8814B) +#define BIT_CLEAR_DSS_1_DATA_IN_8814B(x) ((x) & (~BITS_DSS_1_DATA_IN_8814B)) +#define BIT_GET_DSS_1_DATA_IN_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_1_DATA_IN_8814B) & BIT_MASK_DSS_1_DATA_IN_8814B) +#define BIT_SET_DSS_1_DATA_IN_8814B(x, v) \ + (BIT_CLEAR_DSS_1_DATA_IN_8814B(x) | BIT_DSS_1_DATA_IN_8814B(v)) + +/* 2 REG_SPEED_SENSOR1_8814B */ +#define BIT_DSS_1_READY_8814B BIT(31) +#define BIT_DSS_1_WSORT_GO_8814B BIT(30) + +#define BIT_SHIFT_DSS_1_COUNT_OUT_8814B 0 +#define BIT_MASK_DSS_1_COUNT_OUT_8814B 0xfffff +#define BIT_DSS_1_COUNT_OUT_8814B(x) \ + (((x) & BIT_MASK_DSS_1_COUNT_OUT_8814B) \ + << BIT_SHIFT_DSS_1_COUNT_OUT_8814B) +#define BITS_DSS_1_COUNT_OUT_8814B \ + (BIT_MASK_DSS_1_COUNT_OUT_8814B << BIT_SHIFT_DSS_1_COUNT_OUT_8814B) +#define BIT_CLEAR_DSS_1_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8814B)) +#define BIT_GET_DSS_1_COUNT_OUT_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8814B) & \ + BIT_MASK_DSS_1_COUNT_OUT_8814B) +#define BIT_SET_DSS_1_COUNT_OUT_8814B(x, v) \ + (BIT_CLEAR_DSS_1_COUNT_OUT_8814B(x) | BIT_DSS_1_COUNT_OUT_8814B(v)) + +/* 2 REG_SPEED_SENSOR2_8814B */ +#define BIT_DSS_2_RST_N_8814B BIT(31) +#define BIT_DSS_2_SPEED_EN_8814B BIT(30) +#define BIT_DSS_2_WIRE_SEL_8814B BIT(29) +#define BIT_DSS_ENCLK_8814B BIT(28) + +#define BIT_SHIFT_DSS_2_RO_SEL_8814B 24 +#define BIT_MASK_DSS_2_RO_SEL_8814B 0x7 +#define BIT_DSS_2_RO_SEL_8814B(x) \ + (((x) & BIT_MASK_DSS_2_RO_SEL_8814B) << BIT_SHIFT_DSS_2_RO_SEL_8814B) +#define BITS_DSS_2_RO_SEL_8814B \ + (BIT_MASK_DSS_2_RO_SEL_8814B << BIT_SHIFT_DSS_2_RO_SEL_8814B) +#define BIT_CLEAR_DSS_2_RO_SEL_8814B(x) ((x) & (~BITS_DSS_2_RO_SEL_8814B)) +#define BIT_GET_DSS_2_RO_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_2_RO_SEL_8814B) & BIT_MASK_DSS_2_RO_SEL_8814B) +#define BIT_SET_DSS_2_RO_SEL_8814B(x, v) \ + (BIT_CLEAR_DSS_2_RO_SEL_8814B(x) | BIT_DSS_2_RO_SEL_8814B(v)) + +#define BIT_SHIFT_DSS_2_DATA_IN_8814B 0 +#define BIT_MASK_DSS_2_DATA_IN_8814B 0xfffff +#define BIT_DSS_2_DATA_IN_8814B(x) \ + (((x) & BIT_MASK_DSS_2_DATA_IN_8814B) << BIT_SHIFT_DSS_2_DATA_IN_8814B) +#define BITS_DSS_2_DATA_IN_8814B \ + (BIT_MASK_DSS_2_DATA_IN_8814B << BIT_SHIFT_DSS_2_DATA_IN_8814B) +#define BIT_CLEAR_DSS_2_DATA_IN_8814B(x) ((x) & (~BITS_DSS_2_DATA_IN_8814B)) +#define BIT_GET_DSS_2_DATA_IN_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_2_DATA_IN_8814B) & BIT_MASK_DSS_2_DATA_IN_8814B) +#define BIT_SET_DSS_2_DATA_IN_8814B(x, v) \ + (BIT_CLEAR_DSS_2_DATA_IN_8814B(x) | BIT_DSS_2_DATA_IN_8814B(v)) + +/* 2 REG_SPEED_SENSOR3_8814B */ +#define BIT_DSS_2_READY_8814B BIT(31) +#define BIT_DSS_2_WSORT_GO_8814B BIT(30) + +#define BIT_SHIFT_DSS_2_COUNT_OUT_8814B 0 +#define BIT_MASK_DSS_2_COUNT_OUT_8814B 0xfffff +#define BIT_DSS_2_COUNT_OUT_8814B(x) \ + (((x) & BIT_MASK_DSS_2_COUNT_OUT_8814B) \ + << BIT_SHIFT_DSS_2_COUNT_OUT_8814B) +#define BITS_DSS_2_COUNT_OUT_8814B \ + (BIT_MASK_DSS_2_COUNT_OUT_8814B << BIT_SHIFT_DSS_2_COUNT_OUT_8814B) +#define BIT_CLEAR_DSS_2_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8814B)) +#define BIT_GET_DSS_2_COUNT_OUT_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8814B) & \ + BIT_MASK_DSS_2_COUNT_OUT_8814B) +#define BIT_SET_DSS_2_COUNT_OUT_8814B(x, v) \ + (BIT_CLEAR_DSS_2_COUNT_OUT_8814B(x) | BIT_DSS_2_COUNT_OUT_8814B(v)) + +/* 2 REG_SPEED_SENSOR4_8814B */ +#define BIT_DSS_3_RST_N_8814B BIT(31) +#define BIT_DSS_3_SPEED_EN_8814B BIT(30) +#define BIT_DSS_3_WIRE_SEL_8814B BIT(29) +#define BIT_DSS_ENCLK_8814B BIT(28) + +#define BIT_SHIFT_DSS_3_RO_SEL_8814B 24 +#define BIT_MASK_DSS_3_RO_SEL_8814B 0x7 +#define BIT_DSS_3_RO_SEL_8814B(x) \ + (((x) & BIT_MASK_DSS_3_RO_SEL_8814B) << BIT_SHIFT_DSS_3_RO_SEL_8814B) +#define BITS_DSS_3_RO_SEL_8814B \ + (BIT_MASK_DSS_3_RO_SEL_8814B << BIT_SHIFT_DSS_3_RO_SEL_8814B) +#define BIT_CLEAR_DSS_3_RO_SEL_8814B(x) ((x) & (~BITS_DSS_3_RO_SEL_8814B)) +#define BIT_GET_DSS_3_RO_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_3_RO_SEL_8814B) & BIT_MASK_DSS_3_RO_SEL_8814B) +#define BIT_SET_DSS_3_RO_SEL_8814B(x, v) \ + (BIT_CLEAR_DSS_3_RO_SEL_8814B(x) | BIT_DSS_3_RO_SEL_8814B(v)) + +#define BIT_SHIFT_DSS_3_DATA_IN_8814B 0 +#define BIT_MASK_DSS_3_DATA_IN_8814B 0xfffff +#define BIT_DSS_3_DATA_IN_8814B(x) \ + (((x) & BIT_MASK_DSS_3_DATA_IN_8814B) << BIT_SHIFT_DSS_3_DATA_IN_8814B) +#define BITS_DSS_3_DATA_IN_8814B \ + (BIT_MASK_DSS_3_DATA_IN_8814B << BIT_SHIFT_DSS_3_DATA_IN_8814B) +#define BIT_CLEAR_DSS_3_DATA_IN_8814B(x) ((x) & (~BITS_DSS_3_DATA_IN_8814B)) +#define BIT_GET_DSS_3_DATA_IN_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_3_DATA_IN_8814B) & BIT_MASK_DSS_3_DATA_IN_8814B) +#define BIT_SET_DSS_3_DATA_IN_8814B(x, v) \ + (BIT_CLEAR_DSS_3_DATA_IN_8814B(x) | BIT_DSS_3_DATA_IN_8814B(v)) + +/* 2 REG_SPEED_SENSOR5_8814B */ +#define BIT_DSS_3_READY_8814B BIT(31) +#define BIT_DSS_3_WSORT_GO_8814B BIT(30) + +#define BIT_SHIFT_DSS_3_COUNT_OUT_8814B 0 +#define BIT_MASK_DSS_3_COUNT_OUT_8814B 0xfffff +#define BIT_DSS_3_COUNT_OUT_8814B(x) \ + (((x) & BIT_MASK_DSS_3_COUNT_OUT_8814B) \ + << BIT_SHIFT_DSS_3_COUNT_OUT_8814B) +#define BITS_DSS_3_COUNT_OUT_8814B \ + (BIT_MASK_DSS_3_COUNT_OUT_8814B << BIT_SHIFT_DSS_3_COUNT_OUT_8814B) +#define BIT_CLEAR_DSS_3_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8814B)) +#define BIT_GET_DSS_3_COUNT_OUT_8814B(x) \ + (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8814B) & \ + BIT_MASK_DSS_3_COUNT_OUT_8814B) +#define BIT_SET_DSS_3_COUNT_OUT_8814B(x, v) \ + (BIT_CLEAR_DSS_3_COUNT_OUT_8814B(x) | BIT_DSS_3_COUNT_OUT_8814B(v)) + +/* 2 REG_RXPKTBUF_1_MAX_ADDR_8814B */ + +#define BIT_SHIFT_RXPKTBUF_SIZE_8814B 30 +#define BIT_MASK_RXPKTBUF_SIZE_8814B 0x3 +#define BIT_RXPKTBUF_SIZE_8814B(x) \ + (((x) & BIT_MASK_RXPKTBUF_SIZE_8814B) << BIT_SHIFT_RXPKTBUF_SIZE_8814B) +#define BITS_RXPKTBUF_SIZE_8814B \ + (BIT_MASK_RXPKTBUF_SIZE_8814B << BIT_SHIFT_RXPKTBUF_SIZE_8814B) +#define BIT_CLEAR_RXPKTBUF_SIZE_8814B(x) ((x) & (~BITS_RXPKTBUF_SIZE_8814B)) +#define BIT_GET_RXPKTBUF_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_SIZE_8814B) & BIT_MASK_RXPKTBUF_SIZE_8814B) +#define BIT_SET_RXPKTBUF_SIZE_8814B(x, v) \ + (BIT_CLEAR_RXPKTBUF_SIZE_8814B(x) | BIT_RXPKTBUF_SIZE_8814B(v)) + +#define BIT_RXPKTBUF_DBG_SEL_8814B BIT(29) + +#define BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B 0 +#define BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B 0x3ffff +#define BIT_RXPKTBUF_1_MAX_ADDR_8814B(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B) \ + << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B) +#define BITS_RXPKTBUF_1_MAX_ADDR_8814B \ + (BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B \ + << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B) +#define BIT_CLEAR_RXPKTBUF_1_MAX_ADDR_8814B(x) \ + ((x) & (~BITS_RXPKTBUF_1_MAX_ADDR_8814B)) +#define BIT_GET_RXPKTBUF_1_MAX_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B) & \ + BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B) +#define BIT_SET_RXPKTBUF_1_MAX_ADDR_8814B(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_MAX_ADDR_8814B(x) | \ + BIT_RXPKTBUF_1_MAX_ADDR_8814B(v)) + +/* 2 REG_RXFWBUF_1_MAX_ADDR_8814B */ + +#define BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B 0 +#define BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B 0xffff +#define BIT_RXFWBUF_1_MAX_ADDR_8814B(x) \ + (((x) & BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B) \ + << BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B) +#define BITS_RXFWBUF_1_MAX_ADDR_8814B \ + (BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B \ + << BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B) +#define BIT_CLEAR_RXFWBUF_1_MAX_ADDR_8814B(x) \ + ((x) & (~BITS_RXFWBUF_1_MAX_ADDR_8814B)) +#define BIT_GET_RXFWBUF_1_MAX_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B) & \ + BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B) +#define BIT_SET_RXFWBUF_1_MAX_ADDR_8814B(x, v) \ + (BIT_CLEAR_RXFWBUF_1_MAX_ADDR_8814B(x) | \ + BIT_RXFWBUF_1_MAX_ADDR_8814B(v)) + +/* 2 REG_IO_WRAP_ERR_FLAG_V1_8814B */ +#define BIT_IO_WRAP_ERR_8814B BIT(0) + +/* 2 REG_RXPKTBUF_1_READ_8814B */ + +#define BIT_SHIFT_RXPKTBUF_1_READ_8814B 0 +#define BIT_MASK_RXPKTBUF_1_READ_8814B 0x3ffff +#define BIT_RXPKTBUF_1_READ_8814B(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_READ_8814B) \ + << BIT_SHIFT_RXPKTBUF_1_READ_8814B) +#define BITS_RXPKTBUF_1_READ_8814B \ + (BIT_MASK_RXPKTBUF_1_READ_8814B << BIT_SHIFT_RXPKTBUF_1_READ_8814B) +#define BIT_CLEAR_RXPKTBUF_1_READ_8814B(x) ((x) & (~BITS_RXPKTBUF_1_READ_8814B)) +#define BIT_GET_RXPKTBUF_1_READ_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_READ_8814B) & \ + BIT_MASK_RXPKTBUF_1_READ_8814B) +#define BIT_SET_RXPKTBUF_1_READ_8814B(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_READ_8814B(x) | BIT_RXPKTBUF_1_READ_8814B(v)) + +/* 2 REG_RXPKTBUF_1_WRITE_8814B */ + +#define BIT_SHIFT_RXPKTBUF_1_WRITE_8814B 0 +#define BIT_MASK_RXPKTBUF_1_WRITE_8814B 0x3ffff +#define BIT_RXPKTBUF_1_WRITE_8814B(x) \ + (((x) & BIT_MASK_RXPKTBUF_1_WRITE_8814B) \ + << BIT_SHIFT_RXPKTBUF_1_WRITE_8814B) +#define BITS_RXPKTBUF_1_WRITE_8814B \ + (BIT_MASK_RXPKTBUF_1_WRITE_8814B << BIT_SHIFT_RXPKTBUF_1_WRITE_8814B) +#define BIT_CLEAR_RXPKTBUF_1_WRITE_8814B(x) \ + ((x) & (~BITS_RXPKTBUF_1_WRITE_8814B)) +#define BIT_GET_RXPKTBUF_1_WRITE_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKTBUF_1_WRITE_8814B) & \ + BIT_MASK_RXPKTBUF_1_WRITE_8814B) +#define BIT_SET_RXPKTBUF_1_WRITE_8814B(x, v) \ + (BIT_CLEAR_RXPKTBUF_1_WRITE_8814B(x) | BIT_RXPKTBUF_1_WRITE_8814B(v)) + +/* 2 REG_BUFF_DBGUG_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_R_OQT_DBG_SEL_8814B 16 +#define BIT_MASK_R_OQT_DBG_SEL_8814B 0xff +#define BIT_R_OQT_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_OQT_DBG_SEL_8814B) << BIT_SHIFT_R_OQT_DBG_SEL_8814B) +#define BITS_R_OQT_DBG_SEL_8814B \ + (BIT_MASK_R_OQT_DBG_SEL_8814B << BIT_SHIFT_R_OQT_DBG_SEL_8814B) +#define BIT_CLEAR_R_OQT_DBG_SEL_8814B(x) ((x) & (~BITS_R_OQT_DBG_SEL_8814B)) +#define BIT_GET_R_OQT_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_OQT_DBG_SEL_8814B) & BIT_MASK_R_OQT_DBG_SEL_8814B) +#define BIT_SET_R_OQT_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_OQT_DBG_SEL_8814B(x) | BIT_R_OQT_DBG_SEL_8814B(v)) + +#define BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B 8 +#define BIT_MASK_R_TXPKTBF_DBG_SEL_8814B 0x7 +#define BIT_R_TXPKTBF_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_TXPKTBF_DBG_SEL_8814B) \ + << BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B) +#define BITS_R_TXPKTBF_DBG_SEL_8814B \ + (BIT_MASK_R_TXPKTBF_DBG_SEL_8814B << BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B) +#define BIT_CLEAR_R_TXPKTBF_DBG_SEL_8814B(x) \ + ((x) & (~BITS_R_TXPKTBF_DBG_SEL_8814B)) +#define BIT_GET_R_TXPKTBF_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B) & \ + BIT_MASK_R_TXPKTBF_DBG_SEL_8814B) +#define BIT_SET_R_TXPKTBF_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_TXPKTBF_DBG_SEL_8814B(x) | BIT_R_TXPKTBF_DBG_SEL_8814B(v)) + +#define BIT_SHIFT_R_RXPKT_DBG_SEL_8814B 6 +#define BIT_MASK_R_RXPKT_DBG_SEL_8814B 0x3 +#define BIT_R_RXPKT_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_RXPKT_DBG_SEL_8814B) \ + << BIT_SHIFT_R_RXPKT_DBG_SEL_8814B) +#define BITS_R_RXPKT_DBG_SEL_8814B \ + (BIT_MASK_R_RXPKT_DBG_SEL_8814B << BIT_SHIFT_R_RXPKT_DBG_SEL_8814B) +#define BIT_CLEAR_R_RXPKT_DBG_SEL_8814B(x) ((x) & (~BITS_R_RXPKT_DBG_SEL_8814B)) +#define BIT_GET_R_RXPKT_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_RXPKT_DBG_SEL_8814B) & \ + BIT_MASK_R_RXPKT_DBG_SEL_8814B) +#define BIT_SET_R_RXPKT_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_RXPKT_DBG_SEL_8814B(x) | BIT_R_RXPKT_DBG_SEL_8814B(v)) + +#define BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B 0 +#define BIT_MASK_R_RXPKTBF_DBG_SEL_8814B 0x3 +#define BIT_R_RXPKTBF_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_RXPKTBF_DBG_SEL_8814B) \ + << BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B) +#define BITS_R_RXPKTBF_DBG_SEL_8814B \ + (BIT_MASK_R_RXPKTBF_DBG_SEL_8814B << BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B) +#define BIT_CLEAR_R_RXPKTBF_DBG_SEL_8814B(x) \ + ((x) & (~BITS_R_RXPKTBF_DBG_SEL_8814B)) +#define BIT_GET_R_RXPKTBF_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B) & \ + BIT_MASK_R_RXPKTBF_DBG_SEL_8814B) +#define BIT_SET_R_RXPKTBF_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_RXPKTBF_DBG_SEL_8814B(x) | BIT_R_RXPKTBF_DBG_SEL_8814B(v)) + +/* 2 REG_RFE_CTRL_PAD_E2_8814B */ +#define BIT_RFE_CTRL_ANTSW_E2_8814B BIT(16) +#define BIT_RFE_CTRL_PIN15_E2_8814B BIT(15) +#define BIT_RFE_CTRL_PIN14_E2_8814B BIT(14) +#define BIT_RFE_CTRL_PIN13_E2_8814B BIT(13) +#define BIT_RFE_CTRL_PIN12_E2_8814B BIT(12) +#define BIT_RFE_CTRL_PIN11_E2_8814B BIT(11) +#define BIT_RFE_CTRL_PIN10_E2_8814B BIT(10) +#define BIT_RFE_CTRL_PIN9_E2_8814B BIT(9) +#define BIT_RFE_CTRL_PIN8_E2_8814B BIT(8) +#define BIT_RFE_CTRL_PIN7_E2_8814B BIT(7) +#define BIT_RFE_CTRL_PIN6_E2_8814B BIT(6) +#define BIT_RFE_CTRL_PIN5_E2_8814B BIT(5) +#define BIT_RFE_CTRL_PIN4_E2_8814B BIT(4) +#define BIT_RFE_CTRL_PIN3_E2_8814B BIT(3) +#define BIT_RFE_CTRL_PIN2_E2_8814B BIT(2) +#define BIT_RFE_CTRL_PIN1_E2_8814B BIT(1) +#define BIT_RFE_CTRL_PIN0_E2_8814B BIT(0) + +/* 2 REG_RFE_CTRL_PAD_SR_8814B */ +#define BIT_RFE_CTRL_ANTSW_SR_8814B BIT(16) +#define BIT_RFE_CTRL_PIN15_SR_8814B BIT(15) +#define BIT_RFE_CTRL_PIN14_SR_8814B BIT(14) +#define BIT_RFE_CTRL_PIN13_SR_8814B BIT(13) +#define BIT_RFE_CTRL_PIN12_SR_8814B BIT(12) +#define BIT_RFE_CTRL_PIN11_SR_8814B BIT(11) +#define BIT_RFE_CTRL_PIN10_SR_8814B BIT(10) +#define BIT_RFE_CTRL_PIN9_SR_8814B BIT(9) +#define BIT_RFE_CTRL_PIN8_SR_8814B BIT(8) +#define BIT_RFE_CTRL_PIN7_SR_8814B BIT(7) +#define BIT_RFE_CTRL_PIN6_SR_8814B BIT(6) +#define BIT_RFE_CTRL_PIN5_SR_8814B BIT(5) +#define BIT_RFE_CTRL_PIN4_SR_8814B BIT(4) +#define BIT_RFE_CTRL_PIN3_SR_8814B BIT(3) +#define BIT_RFE_CTRL_PIN2_SR_8814B BIT(2) +#define BIT_RFE_CTRL_PIN1_SR_8814B BIT(1) +#define BIT_RFE_CTRL_PIN0_SR_8814B BIT(0) /* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_H2C_PRIORITY_SEL_8814B */ + +#define BIT_SHIFT_H2C_PRIORITY_SEL_8814B 0 +#define BIT_MASK_H2C_PRIORITY_SEL_8814B 0x3 +#define BIT_H2C_PRIORITY_SEL_8814B(x) \ + (((x) & BIT_MASK_H2C_PRIORITY_SEL_8814B) \ + << BIT_SHIFT_H2C_PRIORITY_SEL_8814B) +#define BITS_H2C_PRIORITY_SEL_8814B \ + (BIT_MASK_H2C_PRIORITY_SEL_8814B << BIT_SHIFT_H2C_PRIORITY_SEL_8814B) +#define BIT_CLEAR_H2C_PRIORITY_SEL_8814B(x) \ + ((x) & (~BITS_H2C_PRIORITY_SEL_8814B)) +#define BIT_GET_H2C_PRIORITY_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_PRIORITY_SEL_8814B) & \ + BIT_MASK_H2C_PRIORITY_SEL_8814B) +#define BIT_SET_H2C_PRIORITY_SEL_8814B(x, v) \ + (BIT_CLEAR_H2C_PRIORITY_SEL_8814B(x) | BIT_H2C_PRIORITY_SEL_8814B(v)) + +/* 2 REG_COUNTER_CTRL_8814B */ + +#define BIT_SHIFT_COUNTER_BASE_8814B 16 +#define BIT_MASK_COUNTER_BASE_8814B 0x1fff +#define BIT_COUNTER_BASE_8814B(x) \ + (((x) & BIT_MASK_COUNTER_BASE_8814B) << BIT_SHIFT_COUNTER_BASE_8814B) +#define BITS_COUNTER_BASE_8814B \ + (BIT_MASK_COUNTER_BASE_8814B << BIT_SHIFT_COUNTER_BASE_8814B) +#define BIT_CLEAR_COUNTER_BASE_8814B(x) ((x) & (~BITS_COUNTER_BASE_8814B)) +#define BIT_GET_COUNTER_BASE_8814B(x) \ + (((x) >> BIT_SHIFT_COUNTER_BASE_8814B) & BIT_MASK_COUNTER_BASE_8814B) +#define BIT_SET_COUNTER_BASE_8814B(x, v) \ + (BIT_CLEAR_COUNTER_BASE_8814B(x) | BIT_COUNTER_BASE_8814B(v)) + +#define BIT_EN_RTS_REQ_8814B BIT(9) +#define BIT_EN_EDCA_REQ_8814B BIT(8) +#define BIT_EN_PTCL_REQ_8814B BIT(7) +#define BIT_EN_SCH_REQ_8814B BIT(6) +#define BIT_USB_COUNT_EN_8814B BIT(5) +#define BIT_PCIE_COUNT_EN_8814B BIT(4) +#define BIT_RQPN_COUNT_EN_8814B BIT(3) +#define BIT_RDE_COUNT_EN_8814B BIT(2) +#define BIT_TDE_COUNT_EN_8814B BIT(1) +#define BIT_DISABLE_COUNTER_8814B BIT(0) + +/* 2 REG_COUNTER_THRESHOLD_8814B */ +#define BIT_SEL_ALL_MACID_8814B BIT(31) + +#define BIT_SHIFT_COUNTER_MACID_8814B 24 +#define BIT_MASK_COUNTER_MACID_8814B 0x7f +#define BIT_COUNTER_MACID_8814B(x) \ + (((x) & BIT_MASK_COUNTER_MACID_8814B) << BIT_SHIFT_COUNTER_MACID_8814B) +#define BITS_COUNTER_MACID_8814B \ + (BIT_MASK_COUNTER_MACID_8814B << BIT_SHIFT_COUNTER_MACID_8814B) +#define BIT_CLEAR_COUNTER_MACID_8814B(x) ((x) & (~BITS_COUNTER_MACID_8814B)) +#define BIT_GET_COUNTER_MACID_8814B(x) \ + (((x) >> BIT_SHIFT_COUNTER_MACID_8814B) & BIT_MASK_COUNTER_MACID_8814B) +#define BIT_SET_COUNTER_MACID_8814B(x, v) \ + (BIT_CLEAR_COUNTER_MACID_8814B(x) | BIT_COUNTER_MACID_8814B(v)) + +#define BIT_SHIFT_AGG_VALUE2_8814B 16 +#define BIT_MASK_AGG_VALUE2_8814B 0x7f +#define BIT_AGG_VALUE2_8814B(x) \ + (((x) & BIT_MASK_AGG_VALUE2_8814B) << BIT_SHIFT_AGG_VALUE2_8814B) +#define BITS_AGG_VALUE2_8814B \ + (BIT_MASK_AGG_VALUE2_8814B << BIT_SHIFT_AGG_VALUE2_8814B) +#define BIT_CLEAR_AGG_VALUE2_8814B(x) ((x) & (~BITS_AGG_VALUE2_8814B)) +#define BIT_GET_AGG_VALUE2_8814B(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE2_8814B) & BIT_MASK_AGG_VALUE2_8814B) +#define BIT_SET_AGG_VALUE2_8814B(x, v) \ + (BIT_CLEAR_AGG_VALUE2_8814B(x) | BIT_AGG_VALUE2_8814B(v)) + +#define BIT_SHIFT_AGG_VALUE1_8814B 8 +#define BIT_MASK_AGG_VALUE1_8814B 0x7f +#define BIT_AGG_VALUE1_8814B(x) \ + (((x) & BIT_MASK_AGG_VALUE1_8814B) << BIT_SHIFT_AGG_VALUE1_8814B) +#define BITS_AGG_VALUE1_8814B \ + (BIT_MASK_AGG_VALUE1_8814B << BIT_SHIFT_AGG_VALUE1_8814B) +#define BIT_CLEAR_AGG_VALUE1_8814B(x) ((x) & (~BITS_AGG_VALUE1_8814B)) +#define BIT_GET_AGG_VALUE1_8814B(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE1_8814B) & BIT_MASK_AGG_VALUE1_8814B) +#define BIT_SET_AGG_VALUE1_8814B(x, v) \ + (BIT_CLEAR_AGG_VALUE1_8814B(x) | BIT_AGG_VALUE1_8814B(v)) + +#define BIT_SHIFT_AGG_VALUE0_8814B 0 +#define BIT_MASK_AGG_VALUE0_8814B 0x7f +#define BIT_AGG_VALUE0_8814B(x) \ + (((x) & BIT_MASK_AGG_VALUE0_8814B) << BIT_SHIFT_AGG_VALUE0_8814B) +#define BITS_AGG_VALUE0_8814B \ + (BIT_MASK_AGG_VALUE0_8814B << BIT_SHIFT_AGG_VALUE0_8814B) +#define BIT_CLEAR_AGG_VALUE0_8814B(x) ((x) & (~BITS_AGG_VALUE0_8814B)) +#define BIT_GET_AGG_VALUE0_8814B(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE0_8814B) & BIT_MASK_AGG_VALUE0_8814B) +#define BIT_SET_AGG_VALUE0_8814B(x, v) \ + (BIT_CLEAR_AGG_VALUE0_8814B(x) | BIT_AGG_VALUE0_8814B(v)) + +/* 2 REG_COUNTER_SET_8814B */ + +#define BIT_SHIFT_REQUEST_RESET_8814B 16 +#define BIT_MASK_REQUEST_RESET_8814B 0xffff +#define BIT_REQUEST_RESET_8814B(x) \ + (((x) & BIT_MASK_REQUEST_RESET_8814B) << BIT_SHIFT_REQUEST_RESET_8814B) +#define BITS_REQUEST_RESET_8814B \ + (BIT_MASK_REQUEST_RESET_8814B << BIT_SHIFT_REQUEST_RESET_8814B) +#define BIT_CLEAR_REQUEST_RESET_8814B(x) ((x) & (~BITS_REQUEST_RESET_8814B)) +#define BIT_GET_REQUEST_RESET_8814B(x) \ + (((x) >> BIT_SHIFT_REQUEST_RESET_8814B) & BIT_MASK_REQUEST_RESET_8814B) +#define BIT_SET_REQUEST_RESET_8814B(x, v) \ + (BIT_CLEAR_REQUEST_RESET_8814B(x) | BIT_REQUEST_RESET_8814B(v)) + +#define BIT_SHIFT_REQUEST_START_8814B 0 +#define BIT_MASK_REQUEST_START_8814B 0xffff +#define BIT_REQUEST_START_8814B(x) \ + (((x) & BIT_MASK_REQUEST_START_8814B) << BIT_SHIFT_REQUEST_START_8814B) +#define BITS_REQUEST_START_8814B \ + (BIT_MASK_REQUEST_START_8814B << BIT_SHIFT_REQUEST_START_8814B) +#define BIT_CLEAR_REQUEST_START_8814B(x) ((x) & (~BITS_REQUEST_START_8814B)) +#define BIT_GET_REQUEST_START_8814B(x) \ + (((x) >> BIT_SHIFT_REQUEST_START_8814B) & BIT_MASK_REQUEST_START_8814B) +#define BIT_SET_REQUEST_START_8814B(x, v) \ + (BIT_CLEAR_REQUEST_START_8814B(x) | BIT_REQUEST_START_8814B(v)) + +/* 2 REG_COUNTER_OVERFLOW_8814B */ + +#define BIT_SHIFT_CNT_OVF_REG_8814B 0 +#define BIT_MASK_CNT_OVF_REG_8814B 0xffff +#define BIT_CNT_OVF_REG_8814B(x) \ + (((x) & BIT_MASK_CNT_OVF_REG_8814B) << BIT_SHIFT_CNT_OVF_REG_8814B) +#define BITS_CNT_OVF_REG_8814B \ + (BIT_MASK_CNT_OVF_REG_8814B << BIT_SHIFT_CNT_OVF_REG_8814B) +#define BIT_CLEAR_CNT_OVF_REG_8814B(x) ((x) & (~BITS_CNT_OVF_REG_8814B)) +#define BIT_GET_CNT_OVF_REG_8814B(x) \ + (((x) >> BIT_SHIFT_CNT_OVF_REG_8814B) & BIT_MASK_CNT_OVF_REG_8814B) +#define BIT_SET_CNT_OVF_REG_8814B(x, v) \ + (BIT_CLEAR_CNT_OVF_REG_8814B(x) | BIT_CNT_OVF_REG_8814B(v)) + +/* 2 REG_TXDMA_LEN_THRESHOLD_8814B */ + +#define BIT_SHIFT_TDE_LEN_TH1_8814B 16 +#define BIT_MASK_TDE_LEN_TH1_8814B 0xffff +#define BIT_TDE_LEN_TH1_8814B(x) \ + (((x) & BIT_MASK_TDE_LEN_TH1_8814B) << BIT_SHIFT_TDE_LEN_TH1_8814B) +#define BITS_TDE_LEN_TH1_8814B \ + (BIT_MASK_TDE_LEN_TH1_8814B << BIT_SHIFT_TDE_LEN_TH1_8814B) +#define BIT_CLEAR_TDE_LEN_TH1_8814B(x) ((x) & (~BITS_TDE_LEN_TH1_8814B)) +#define BIT_GET_TDE_LEN_TH1_8814B(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH1_8814B) & BIT_MASK_TDE_LEN_TH1_8814B) +#define BIT_SET_TDE_LEN_TH1_8814B(x, v) \ + (BIT_CLEAR_TDE_LEN_TH1_8814B(x) | BIT_TDE_LEN_TH1_8814B(v)) + +#define BIT_SHIFT_TDE_LEN_TH0_8814B 0 +#define BIT_MASK_TDE_LEN_TH0_8814B 0xffff +#define BIT_TDE_LEN_TH0_8814B(x) \ + (((x) & BIT_MASK_TDE_LEN_TH0_8814B) << BIT_SHIFT_TDE_LEN_TH0_8814B) +#define BITS_TDE_LEN_TH0_8814B \ + (BIT_MASK_TDE_LEN_TH0_8814B << BIT_SHIFT_TDE_LEN_TH0_8814B) +#define BIT_CLEAR_TDE_LEN_TH0_8814B(x) ((x) & (~BITS_TDE_LEN_TH0_8814B)) +#define BIT_GET_TDE_LEN_TH0_8814B(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH0_8814B) & BIT_MASK_TDE_LEN_TH0_8814B) +#define BIT_SET_TDE_LEN_TH0_8814B(x, v) \ + (BIT_CLEAR_TDE_LEN_TH0_8814B(x) | BIT_TDE_LEN_TH0_8814B(v)) + +/* 2 REG_RXDMA_LEN_THRESHOLD_8814B */ + +#define BIT_SHIFT_RDE_LEN_TH1_8814B 16 +#define BIT_MASK_RDE_LEN_TH1_8814B 0xffff +#define BIT_RDE_LEN_TH1_8814B(x) \ + (((x) & BIT_MASK_RDE_LEN_TH1_8814B) << BIT_SHIFT_RDE_LEN_TH1_8814B) +#define BITS_RDE_LEN_TH1_8814B \ + (BIT_MASK_RDE_LEN_TH1_8814B << BIT_SHIFT_RDE_LEN_TH1_8814B) +#define BIT_CLEAR_RDE_LEN_TH1_8814B(x) ((x) & (~BITS_RDE_LEN_TH1_8814B)) +#define BIT_GET_RDE_LEN_TH1_8814B(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH1_8814B) & BIT_MASK_RDE_LEN_TH1_8814B) +#define BIT_SET_RDE_LEN_TH1_8814B(x, v) \ + (BIT_CLEAR_RDE_LEN_TH1_8814B(x) | BIT_RDE_LEN_TH1_8814B(v)) + +#define BIT_SHIFT_RDE_LEN_TH0_8814B 0 +#define BIT_MASK_RDE_LEN_TH0_8814B 0xffff +#define BIT_RDE_LEN_TH0_8814B(x) \ + (((x) & BIT_MASK_RDE_LEN_TH0_8814B) << BIT_SHIFT_RDE_LEN_TH0_8814B) +#define BITS_RDE_LEN_TH0_8814B \ + (BIT_MASK_RDE_LEN_TH0_8814B << BIT_SHIFT_RDE_LEN_TH0_8814B) +#define BIT_CLEAR_RDE_LEN_TH0_8814B(x) ((x) & (~BITS_RDE_LEN_TH0_8814B)) +#define BIT_GET_RDE_LEN_TH0_8814B(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH0_8814B) & BIT_MASK_RDE_LEN_TH0_8814B) +#define BIT_SET_RDE_LEN_TH0_8814B(x, v) \ + (BIT_CLEAR_RDE_LEN_TH0_8814B(x) | BIT_RDE_LEN_TH0_8814B(v)) + +/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8814B */ + +#define BIT_SHIFT_COUNT_INT_SEL_8814B 16 +#define BIT_MASK_COUNT_INT_SEL_8814B 0x3 +#define BIT_COUNT_INT_SEL_8814B(x) \ + (((x) & BIT_MASK_COUNT_INT_SEL_8814B) << BIT_SHIFT_COUNT_INT_SEL_8814B) +#define BITS_COUNT_INT_SEL_8814B \ + (BIT_MASK_COUNT_INT_SEL_8814B << BIT_SHIFT_COUNT_INT_SEL_8814B) +#define BIT_CLEAR_COUNT_INT_SEL_8814B(x) ((x) & (~BITS_COUNT_INT_SEL_8814B)) +#define BIT_GET_COUNT_INT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_COUNT_INT_SEL_8814B) & BIT_MASK_COUNT_INT_SEL_8814B) +#define BIT_SET_COUNT_INT_SEL_8814B(x, v) \ + (BIT_CLEAR_COUNT_INT_SEL_8814B(x) | BIT_COUNT_INT_SEL_8814B(v)) + +#define BIT_SHIFT_EXEC_TIME_TH_8814B 0 +#define BIT_MASK_EXEC_TIME_TH_8814B 0xffff +#define BIT_EXEC_TIME_TH_8814B(x) \ + (((x) & BIT_MASK_EXEC_TIME_TH_8814B) << BIT_SHIFT_EXEC_TIME_TH_8814B) +#define BITS_EXEC_TIME_TH_8814B \ + (BIT_MASK_EXEC_TIME_TH_8814B << BIT_SHIFT_EXEC_TIME_TH_8814B) +#define BIT_CLEAR_EXEC_TIME_TH_8814B(x) ((x) & (~BITS_EXEC_TIME_TH_8814B)) +#define BIT_GET_EXEC_TIME_TH_8814B(x) \ + (((x) >> BIT_SHIFT_EXEC_TIME_TH_8814B) & BIT_MASK_EXEC_TIME_TH_8814B) +#define BIT_SET_EXEC_TIME_TH_8814B(x, v) \ + (BIT_CLEAR_EXEC_TIME_TH_8814B(x) | BIT_EXEC_TIME_TH_8814B(v)) /* 2 REG_FT2IMR_8814B */ #define BIT_FS_CLI3_RX_UAPSDMD1_EN_8814B BIT(31) @@ -3488,426 +6801,1019 @@ #define BIT_SHIFT_FW_MSG2_8814B 0 #define BIT_MASK_FW_MSG2_8814B 0xffffffffL -#define BIT_FW_MSG2_8814B(x) (((x) & BIT_MASK_FW_MSG2_8814B) << BIT_SHIFT_FW_MSG2_8814B) -#define BIT_GET_FW_MSG2_8814B(x) (((x) >> BIT_SHIFT_FW_MSG2_8814B) & BIT_MASK_FW_MSG2_8814B) - - +#define BIT_FW_MSG2_8814B(x) \ + (((x) & BIT_MASK_FW_MSG2_8814B) << BIT_SHIFT_FW_MSG2_8814B) +#define BITS_FW_MSG2_8814B (BIT_MASK_FW_MSG2_8814B << BIT_SHIFT_FW_MSG2_8814B) +#define BIT_CLEAR_FW_MSG2_8814B(x) ((x) & (~BITS_FW_MSG2_8814B)) +#define BIT_GET_FW_MSG2_8814B(x) \ + (((x) >> BIT_SHIFT_FW_MSG2_8814B) & BIT_MASK_FW_MSG2_8814B) +#define BIT_SET_FW_MSG2_8814B(x, v) \ + (BIT_CLEAR_FW_MSG2_8814B(x) | BIT_FW_MSG2_8814B(v)) /* 2 REG_MSG3_8814B */ #define BIT_SHIFT_FW_MSG3_8814B 0 #define BIT_MASK_FW_MSG3_8814B 0xffffffffL -#define BIT_FW_MSG3_8814B(x) (((x) & BIT_MASK_FW_MSG3_8814B) << BIT_SHIFT_FW_MSG3_8814B) -#define BIT_GET_FW_MSG3_8814B(x) (((x) >> BIT_SHIFT_FW_MSG3_8814B) & BIT_MASK_FW_MSG3_8814B) - - +#define BIT_FW_MSG3_8814B(x) \ + (((x) & BIT_MASK_FW_MSG3_8814B) << BIT_SHIFT_FW_MSG3_8814B) +#define BITS_FW_MSG3_8814B (BIT_MASK_FW_MSG3_8814B << BIT_SHIFT_FW_MSG3_8814B) +#define BIT_CLEAR_FW_MSG3_8814B(x) ((x) & (~BITS_FW_MSG3_8814B)) +#define BIT_GET_FW_MSG3_8814B(x) \ + (((x) >> BIT_SHIFT_FW_MSG3_8814B) & BIT_MASK_FW_MSG3_8814B) +#define BIT_SET_FW_MSG3_8814B(x, v) \ + (BIT_CLEAR_FW_MSG3_8814B(x) | BIT_FW_MSG3_8814B(v)) /* 2 REG_MSG4_8814B */ #define BIT_SHIFT_FW_MSG4_8814B 0 #define BIT_MASK_FW_MSG4_8814B 0xffffffffL -#define BIT_FW_MSG4_8814B(x) (((x) & BIT_MASK_FW_MSG4_8814B) << BIT_SHIFT_FW_MSG4_8814B) -#define BIT_GET_FW_MSG4_8814B(x) (((x) >> BIT_SHIFT_FW_MSG4_8814B) & BIT_MASK_FW_MSG4_8814B) - - +#define BIT_FW_MSG4_8814B(x) \ + (((x) & BIT_MASK_FW_MSG4_8814B) << BIT_SHIFT_FW_MSG4_8814B) +#define BITS_FW_MSG4_8814B (BIT_MASK_FW_MSG4_8814B << BIT_SHIFT_FW_MSG4_8814B) +#define BIT_CLEAR_FW_MSG4_8814B(x) ((x) & (~BITS_FW_MSG4_8814B)) +#define BIT_GET_FW_MSG4_8814B(x) \ + (((x) >> BIT_SHIFT_FW_MSG4_8814B) & BIT_MASK_FW_MSG4_8814B) +#define BIT_SET_FW_MSG4_8814B(x, v) \ + (BIT_CLEAR_FW_MSG4_8814B(x) | BIT_FW_MSG4_8814B(v)) /* 2 REG_MSG5_8814B */ #define BIT_SHIFT_FW_MSG5_8814B 0 #define BIT_MASK_FW_MSG5_8814B 0xffffffffL -#define BIT_FW_MSG5_8814B(x) (((x) & BIT_MASK_FW_MSG5_8814B) << BIT_SHIFT_FW_MSG5_8814B) -#define BIT_GET_FW_MSG5_8814B(x) (((x) >> BIT_SHIFT_FW_MSG5_8814B) & BIT_MASK_FW_MSG5_8814B) - +#define BIT_FW_MSG5_8814B(x) \ + (((x) & BIT_MASK_FW_MSG5_8814B) << BIT_SHIFT_FW_MSG5_8814B) +#define BITS_FW_MSG5_8814B (BIT_MASK_FW_MSG5_8814B << BIT_SHIFT_FW_MSG5_8814B) +#define BIT_CLEAR_FW_MSG5_8814B(x) ((x) & (~BITS_FW_MSG5_8814B)) +#define BIT_GET_FW_MSG5_8814B(x) \ + (((x) >> BIT_SHIFT_FW_MSG5_8814B) & BIT_MASK_FW_MSG5_8814B) +#define BIT_SET_FW_MSG5_8814B(x, v) \ + (BIT_CLEAR_FW_MSG5_8814B(x) | BIT_FW_MSG5_8814B(v)) +/* 2 REG_BIST_RSTN0_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_CTRL_1_8814B */ +/* 2 REG_BIST_RSTN2_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8814B 16 -#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8814B 0xff -#define BIT_TX_OQT_HE_FREE_SPACE_V1_8814B(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8814B) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8814B) -#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8814B(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8814B) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8814B) +/* 2 REG_BIST_MODE_NRML0_8814B */ +/* 2 REG_BIST_MODE_NRML1_8814B */ +/* 2 REG_BIST_MODE_NRML2_8814B */ + +/* 2 REG_BIST_MODE_NRML3_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8814B 0 -#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8814B 0xff -#define BIT_TX_OQT_NL_FREE_SPACE_V1_8814B(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8814B) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8814B) -#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8814B(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8814B) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_CTRL_2_8814B */ -#define BIT_BCN_VALID_1_V1_8814B BIT(31) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_HEAD_1_V1_8814B 16 -#define BIT_MASK_BCN_HEAD_1_V1_8814B 0xfff -#define BIT_BCN_HEAD_1_V1_8814B(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8814B) << BIT_SHIFT_BCN_HEAD_1_V1_8814B) -#define BIT_GET_BCN_HEAD_1_V1_8814B(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8814B) & BIT_MASK_BCN_HEAD_1_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_BCN_VALID_V1_8814B BIT(15) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_HEAD_V1_8814B 0 -#define BIT_MASK_BCN_HEAD_V1_8814B 0xfff -#define BIT_BCN_HEAD_V1_8814B(x) (((x) & BIT_MASK_BCN_HEAD_V1_8814B) << BIT_SHIFT_BCN_HEAD_V1_8814B) -#define BIT_GET_BCN_HEAD_V1_8814B(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8814B) & BIT_MASK_BCN_HEAD_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_BIST_DONE_NRML_MAC_8814B */ -/* 2 REG_AUTO_LLT_V1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B 24 -#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8814B) +/* 2 REG_BIST_DONE_NRML1_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_BIST_DONE_DRF_MAC_8814B */ -#define BIT_SHIFT_LLT_FREE_PAGE_V1_8814B 8 -#define BIT_MASK_LLT_FREE_PAGE_V1_8814B 0xffff -#define BIT_LLT_FREE_PAGE_V1_8814B(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8814B) << BIT_SHIFT_LLT_FREE_PAGE_V1_8814B) -#define BIT_GET_LLT_FREE_PAGE_V1_8814B(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8814B) & BIT_MASK_LLT_FREE_PAGE_V1_8814B) +/* 2 REG_BIST_DONE_DRF_8814B */ +/* 2 REG_BIST_DONE_DRF1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BLK_DESC_NUM_8814B 4 -#define BIT_MASK_BLK_DESC_NUM_8814B 0xf -#define BIT_BLK_DESC_NUM_8814B(x) (((x) & BIT_MASK_BLK_DESC_NUM_8814B) << BIT_SHIFT_BLK_DESC_NUM_8814B) -#define BIT_GET_BLK_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8814B) & BIT_MASK_BLK_DESC_NUM_8814B) +/* 2 REG_BIST_FAIL_NRML_MAC_8814B */ +/* 2 REG_BIST_FAIL_NRML_8814B */ -#define BIT_R_BCN_HEAD_SEL_8814B BIT(3) -#define BIT_R_EN_BCN_SW_HEAD_SEL_8814B BIT(2) -#define BIT_LLT_DBG_SEL_8814B BIT(1) -#define BIT_AUTO_INIT_LLT_V1_8814B BIT(0) +/* 2 REG_BIST_FAIL_NRML1_8814B */ -/* 2 REG_TXDMA_OFFSET_CHK_8814B */ -#define BIT_EM_CHKSUM_FIN_8814B BIT(31) -#define BIT_EMN_PCIE_DMA_MOD_8814B BIT(30) -#define BIT_EN_TXQUE_CLR_8814B BIT(29) -#define BIT_EN_PCIE_FIFO_MODE_8814B BIT(28) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PG_UNDER_TH_V1_8814B 16 -#define BIT_MASK_PG_UNDER_TH_V1_8814B 0xfff -#define BIT_PG_UNDER_TH_V1_8814B(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8814B) << BIT_SHIFT_PG_UNDER_TH_V1_8814B) -#define BIT_GET_PG_UNDER_TH_V1_8814B(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8814B) & BIT_MASK_PG_UNDER_TH_V1_8814B) +/* 2 REG_BIST_FAIL_NRML_MAC_V1_8814B */ +/* 2 REG_BIST_FAIL_NRML_V1_8814B */ +/* 2 REG_BIST_FAIL_NRML1_V1_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SDIO_TXDESC_CHKSUM_EN_8814B BIT(13) -#define BIT_RST_RDPTR_8814B BIT(12) -#define BIT_RST_WRPTR_8814B BIT(11) -#define BIT_CHK_PG_TH_EN_8814B BIT(10) -#define BIT_DROP_DATA_EN_8814B BIT(9) -#define BIT_CHECK_OFFSET_EN_8814B BIT(8) -#define BIT_SHIFT_CHECK_OFFSET_8814B 0 -#define BIT_MASK_CHECK_OFFSET_8814B 0xff -#define BIT_CHECK_OFFSET_8814B(x) (((x) & BIT_MASK_CHECK_OFFSET_8814B) << BIT_SHIFT_CHECK_OFFSET_8814B) -#define BIT_GET_CHECK_OFFSET_8814B(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8814B) & BIT_MASK_CHECK_OFFSET_8814B) +/* 2 REG_BIST_MISR_DATAOUT_8814B */ +/* 2 REG_BIST_MISR_DATAOUT1_8814B */ +/* 2 REG_BIST_MISR_DATAOUT_CPU_8814B */ -/* 2 REG_TXDMA_STATUS_8814B */ -#define BIT_TXPKTBUF_REQ_ERR_8814B BIT(18) -#define BIT_HI_OQT_UDN_8814B BIT(17) -#define BIT_HI_OQT_OVF_8814B BIT(16) -#define BIT_PAYLOAD_CHKSUM_ERR_8814B BIT(15) -#define BIT_PAYLOAD_UDN_8814B BIT(14) -#define BIT_PAYLOAD_OVF_8814B BIT(13) -#define BIT_DSC_CHKSUM_FAIL_8814B BIT(12) -#define BIT_UNKNOWN_QSEL_8814B BIT(11) -#define BIT_EP_QSEL_DIFF_8814B BIT(10) -#define BIT_TX_OFFS_UNMATCH_8814B BIT(9) -#define BIT_TXOQT_UDN_8814B BIT(8) -#define BIT_TXOQT_OVF_8814B BIT(7) -#define BIT_TXDMA_SFF_UDN_8814B BIT(6) -#define BIT_TXDMA_SFF_OVF_8814B BIT(5) -#define BIT_LLT_NULL_PG_8814B BIT(4) -#define BIT_PAGE_UDN_8814B BIT(3) -#define BIT_PAGE_OVF_8814B BIT(2) -#define BIT_TXFF_PG_UDN_8814B BIT(1) -#define BIT_TXFF_PG_OVF_8814B BIT(0) +/* 2 REG_BIST_MISR_DATAOUT_CPU1_8814B */ -/* 2 REG_TX_DMA_DBG_8814B */ +/* 2 REG_BIST_MISR_DATAOUT_CPU2_8814B */ -/* 2 REG_TQPNT1_8814B */ +/* 2 REG_BIST_MISR_DATOUT_CPU3_8814B */ -#define BIT_SHIFT_HPQ_HIGH_TH_V1_8814B 16 -#define BIT_MASK_HPQ_HIGH_TH_V1_8814B 0xfff -#define BIT_HPQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8814B) << BIT_SHIFT_HPQ_HIGH_TH_V1_8814B) -#define BIT_GET_HPQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8814B) & BIT_MASK_HPQ_HIGH_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_HPQ_LOW_TH_V1_8814B 0 -#define BIT_MASK_HPQ_LOW_TH_V1_8814B 0xfff -#define BIT_HPQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8814B) << BIT_SHIFT_HPQ_LOW_TH_V1_8814B) -#define BIT_GET_HPQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8814B) & BIT_MASK_HPQ_LOW_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TQPNT2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NPQ_HIGH_TH_V1_8814B 16 -#define BIT_MASK_NPQ_HIGH_TH_V1_8814B 0xfff -#define BIT_NPQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8814B) << BIT_SHIFT_NPQ_HIGH_TH_V1_8814B) -#define BIT_GET_NPQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8814B) & BIT_MASK_NPQ_HIGH_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NPQ_LOW_TH_V1_8814B 0 -#define BIT_MASK_NPQ_LOW_TH_V1_8814B 0xfff -#define BIT_NPQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8814B) << BIT_SHIFT_NPQ_LOW_TH_V1_8814B) -#define BIT_GET_NPQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8814B) & BIT_MASK_NPQ_LOW_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TQPNT3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_LPQ_HIGH_TH_V1_8814B 16 -#define BIT_MASK_LPQ_HIGH_TH_V1_8814B 0xfff -#define BIT_LPQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8814B) << BIT_SHIFT_LPQ_HIGH_TH_V1_8814B) -#define BIT_GET_LPQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8814B) & BIT_MASK_LPQ_HIGH_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_LPQ_LOW_TH_V1_8814B 0 -#define BIT_MASK_LPQ_LOW_TH_V1_8814B 0xfff -#define BIT_LPQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8814B) << BIT_SHIFT_LPQ_LOW_TH_V1_8814B) -#define BIT_GET_LPQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8814B) & BIT_MASK_LPQ_LOW_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TQPNT4_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_EXQ_HIGH_TH_V1_8814B 16 -#define BIT_MASK_EXQ_HIGH_TH_V1_8814B 0xfff -#define BIT_EXQ_HIGH_TH_V1_8814B(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8814B) << BIT_SHIFT_EXQ_HIGH_TH_V1_8814B) -#define BIT_GET_EXQ_HIGH_TH_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8814B) & BIT_MASK_EXQ_HIGH_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_EXQ_LOW_TH_V1_8814B 0 -#define BIT_MASK_EXQ_LOW_TH_V1_8814B 0xfff -#define BIT_EXQ_LOW_TH_V1_8814B(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8814B) << BIT_SHIFT_EXQ_LOW_TH_V1_8814B) -#define BIT_GET_EXQ_LOW_TH_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8814B) & BIT_MASK_EXQ_LOW_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RQPN_CTRL_1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXPKTNUM_H_8814B 16 -#define BIT_MASK_TXPKTNUM_H_8814B 0xffff -#define BIT_TXPKTNUM_H_8814B(x) (((x) & BIT_MASK_TXPKTNUM_H_8814B) << BIT_SHIFT_TXPKTNUM_H_8814B) -#define BIT_GET_TXPKTNUM_H_8814B(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8814B) & BIT_MASK_TXPKTNUM_H_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXPKTNUM_V2_8814B 0 -#define BIT_MASK_TXPKTNUM_V2_8814B 0xffff -#define BIT_TXPKTNUM_V2_8814B(x) (((x) & BIT_MASK_TXPKTNUM_V2_8814B) << BIT_SHIFT_TXPKTNUM_V2_8814B) -#define BIT_GET_TXPKTNUM_V2_8814B(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8814B) & BIT_MASK_TXPKTNUM_V2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RQPN_CTRL_2_8814B */ -#define BIT_LD_RQPN_8814B BIT(31) -#define BIT_EXQ_PUBLIC_DIS_V1_8814B BIT(19) -#define BIT_NPQ_PUBLIC_DIS_V1_8814B BIT(18) -#define BIT_LPQ_PUBLIC_DIS_V1_8814B BIT(17) -#define BIT_HPQ_PUBLIC_DIS_V1_8814B BIT(16) -#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_8814B BIT(15) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8814B 0 -#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8814B 0xfff -#define BIT_SDIO_TXAGG_ALIGN_SIZE_8814B(x) (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8814B) << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8814B) -#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8814B(x) (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8814B) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_INFO_1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_HPQ_AVAL_PG_V1_8814B 16 -#define BIT_MASK_HPQ_AVAL_PG_V1_8814B 0xfff -#define BIT_HPQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8814B) << BIT_SHIFT_HPQ_AVAL_PG_V1_8814B) -#define BIT_GET_HPQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8814B) & BIT_MASK_HPQ_AVAL_PG_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_HPQ_V1_8814B 0 -#define BIT_MASK_HPQ_V1_8814B 0xfff -#define BIT_HPQ_V1_8814B(x) (((x) & BIT_MASK_HPQ_V1_8814B) << BIT_SHIFT_HPQ_V1_8814B) -#define BIT_GET_HPQ_V1_8814B(x) (((x) >> BIT_SHIFT_HPQ_V1_8814B) & BIT_MASK_HPQ_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_INFO_2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_LPQ_AVAL_PG_V1_8814B 16 -#define BIT_MASK_LPQ_AVAL_PG_V1_8814B 0xfff -#define BIT_LPQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8814B) << BIT_SHIFT_LPQ_AVAL_PG_V1_8814B) -#define BIT_GET_LPQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8814B) & BIT_MASK_LPQ_AVAL_PG_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_LPQ_V1_8814B 0 -#define BIT_MASK_LPQ_V1_8814B 0xfff -#define BIT_LPQ_V1_8814B(x) (((x) & BIT_MASK_LPQ_V1_8814B) << BIT_SHIFT_LPQ_V1_8814B) -#define BIT_GET_LPQ_V1_8814B(x) (((x) >> BIT_SHIFT_LPQ_V1_8814B) & BIT_MASK_LPQ_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_INFO_3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NPQ_AVAL_PG_V1_8814B 16 -#define BIT_MASK_NPQ_AVAL_PG_V1_8814B 0xfff -#define BIT_NPQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8814B) << BIT_SHIFT_NPQ_AVAL_PG_V1_8814B) -#define BIT_GET_NPQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8814B) & BIT_MASK_NPQ_AVAL_PG_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NPQ_V1_8814B 0 -#define BIT_MASK_NPQ_V1_8814B 0xfff -#define BIT_NPQ_V1_8814B(x) (((x) & BIT_MASK_NPQ_V1_8814B) << BIT_SHIFT_NPQ_V1_8814B) -#define BIT_GET_NPQ_V1_8814B(x) (((x) >> BIT_SHIFT_NPQ_V1_8814B) & BIT_MASK_NPQ_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_INFO_4_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_EXQ_AVAL_PG_V1_8814B 16 -#define BIT_MASK_EXQ_AVAL_PG_V1_8814B 0xfff -#define BIT_EXQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8814B) << BIT_SHIFT_EXQ_AVAL_PG_V1_8814B) -#define BIT_GET_EXQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8814B) & BIT_MASK_EXQ_AVAL_PG_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_EXQ_V1_8814B 0 -#define BIT_MASK_EXQ_V1_8814B 0xfff -#define BIT_EXQ_V1_8814B(x) (((x) & BIT_MASK_EXQ_V1_8814B) << BIT_SHIFT_EXQ_V1_8814B) -#define BIT_GET_EXQ_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_V1_8814B) & BIT_MASK_EXQ_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FIFOPAGE_INFO_5_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8814B 16 -#define BIT_MASK_PUBQ_AVAL_PG_V1_8814B 0xfff -#define BIT_PUBQ_AVAL_PG_V1_8814B(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8814B) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8814B) -#define BIT_GET_PUBQ_AVAL_PG_V1_8814B(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8814B) & BIT_MASK_PUBQ_AVAL_PG_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PUBQ_V1_8814B 0 -#define BIT_MASK_PUBQ_V1_8814B 0xfff -#define BIT_PUBQ_V1_8814B(x) (((x) & BIT_MASK_PUBQ_V1_8814B) << BIT_SHIFT_PUBQ_V1_8814B) -#define BIT_GET_PUBQ_V1_8814B(x) (((x) >> BIT_SHIFT_PUBQ_V1_8814B) & BIT_MASK_PUBQ_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_H2C_HEAD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_H2C_HEAD_8814B 0 -#define BIT_MASK_H2C_HEAD_8814B 0x3ffff -#define BIT_H2C_HEAD_8814B(x) (((x) & BIT_MASK_H2C_HEAD_8814B) << BIT_SHIFT_H2C_HEAD_8814B) -#define BIT_GET_H2C_HEAD_8814B(x) (((x) >> BIT_SHIFT_H2C_HEAD_8814B) & BIT_MASK_H2C_HEAD_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_H2C_TAIL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_H2C_TAIL_8814B 0 -#define BIT_MASK_H2C_TAIL_8814B 0x3ffff -#define BIT_H2C_TAIL_8814B(x) (((x) & BIT_MASK_H2C_TAIL_8814B) << BIT_SHIFT_H2C_TAIL_8814B) -#define BIT_GET_H2C_TAIL_8814B(x) (((x) >> BIT_SHIFT_H2C_TAIL_8814B) & BIT_MASK_H2C_TAIL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_H2C_READ_ADDR_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_H2C_READ_ADDR_8814B 0 -#define BIT_MASK_H2C_READ_ADDR_8814B 0x3ffff -#define BIT_H2C_READ_ADDR_8814B(x) (((x) & BIT_MASK_H2C_READ_ADDR_8814B) << BIT_SHIFT_H2C_READ_ADDR_8814B) -#define BIT_GET_H2C_READ_ADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8814B) & BIT_MASK_H2C_READ_ADDR_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_H2C_WR_ADDR_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_H2C_WR_ADDR_8814B 0 -#define BIT_MASK_H2C_WR_ADDR_8814B 0x3ffff -#define BIT_H2C_WR_ADDR_8814B(x) (((x) & BIT_MASK_H2C_WR_ADDR_8814B) << BIT_SHIFT_H2C_WR_ADDR_8814B) -#define BIT_GET_H2C_WR_ADDR_8814B(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8814B) & BIT_MASK_H2C_WR_ADDR_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_BCN_CTRL_0_8814B */ +#define BIT_BCN1_VALID_8814B BIT(31) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_H2C_INFO_8814B */ -#define BIT_H2C_SPACE_VLD_8814B BIT(3) -#define BIT_H2C_WR_ADDR_RST_8814B BIT(2) +#define BIT_SHIFT_BCN1_HEAD_8814B 16 +#define BIT_MASK_BCN1_HEAD_8814B 0xfff +#define BIT_BCN1_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN1_HEAD_8814B) << BIT_SHIFT_BCN1_HEAD_8814B) +#define BITS_BCN1_HEAD_8814B \ + (BIT_MASK_BCN1_HEAD_8814B << BIT_SHIFT_BCN1_HEAD_8814B) +#define BIT_CLEAR_BCN1_HEAD_8814B(x) ((x) & (~BITS_BCN1_HEAD_8814B)) +#define BIT_GET_BCN1_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN1_HEAD_8814B) & BIT_MASK_BCN1_HEAD_8814B) +#define BIT_SET_BCN1_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN1_HEAD_8814B(x) | BIT_BCN1_HEAD_8814B(v)) -#define BIT_SHIFT_H2C_LEN_SEL_8814B 0 -#define BIT_MASK_H2C_LEN_SEL_8814B 0x3 -#define BIT_H2C_LEN_SEL_8814B(x) (((x) & BIT_MASK_H2C_LEN_SEL_8814B) << BIT_SHIFT_H2C_LEN_SEL_8814B) -#define BIT_GET_H2C_LEN_SEL_8814B(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8814B) & BIT_MASK_H2C_LEN_SEL_8814B) +#define BIT_BCN0_VALID_8814B BIT(15) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_BCN0_HEAD_8814B 0 +#define BIT_MASK_BCN0_HEAD_8814B 0xfff +#define BIT_BCN0_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN0_HEAD_8814B) << BIT_SHIFT_BCN0_HEAD_8814B) +#define BITS_BCN0_HEAD_8814B \ + (BIT_MASK_BCN0_HEAD_8814B << BIT_SHIFT_BCN0_HEAD_8814B) +#define BIT_CLEAR_BCN0_HEAD_8814B(x) ((x) & (~BITS_BCN0_HEAD_8814B)) +#define BIT_GET_BCN0_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN0_HEAD_8814B) & BIT_MASK_BCN0_HEAD_8814B) +#define BIT_SET_BCN0_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN0_HEAD_8814B(x) | BIT_BCN0_HEAD_8814B(v)) + +/* 2 REG_BCN_CTRL_1_8814B */ +#define BIT_BCN3_VALID_8814B BIT(31) -/* 2 REG_RXDMA_AGG_PG_TH_8814B */ +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_BCN3_HEAD_8814B 16 +#define BIT_MASK_BCN3_HEAD_8814B 0xfff +#define BIT_BCN3_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN3_HEAD_8814B) << BIT_SHIFT_BCN3_HEAD_8814B) +#define BITS_BCN3_HEAD_8814B \ + (BIT_MASK_BCN3_HEAD_8814B << BIT_SHIFT_BCN3_HEAD_8814B) +#define BIT_CLEAR_BCN3_HEAD_8814B(x) ((x) & (~BITS_BCN3_HEAD_8814B)) +#define BIT_GET_BCN3_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN3_HEAD_8814B) & BIT_MASK_BCN3_HEAD_8814B) +#define BIT_SET_BCN3_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN3_HEAD_8814B(x) | BIT_BCN3_HEAD_8814B(v)) + +#define BIT_BCN2_VALID_8814B BIT(15) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_BCN2_HEAD_8814B 0 +#define BIT_MASK_BCN2_HEAD_8814B 0xfff +#define BIT_BCN2_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN2_HEAD_8814B) << BIT_SHIFT_BCN2_HEAD_8814B) +#define BITS_BCN2_HEAD_8814B \ + (BIT_MASK_BCN2_HEAD_8814B << BIT_SHIFT_BCN2_HEAD_8814B) +#define BIT_CLEAR_BCN2_HEAD_8814B(x) ((x) & (~BITS_BCN2_HEAD_8814B)) +#define BIT_GET_BCN2_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN2_HEAD_8814B) & BIT_MASK_BCN2_HEAD_8814B) +#define BIT_SET_BCN2_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN2_HEAD_8814B(x) | BIT_BCN2_HEAD_8814B(v)) + +/* 2 REG_AUTO_LLT_V1_8814B */ + +#define BIT_SHIFT_MAX_TX_PKT_V1_8814B 24 +#define BIT_MASK_MAX_TX_PKT_V1_8814B 0xff +#define BIT_MAX_TX_PKT_V1_8814B(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_V1_8814B) << BIT_SHIFT_MAX_TX_PKT_V1_8814B) +#define BITS_MAX_TX_PKT_V1_8814B \ + (BIT_MASK_MAX_TX_PKT_V1_8814B << BIT_SHIFT_MAX_TX_PKT_V1_8814B) +#define BIT_CLEAR_MAX_TX_PKT_V1_8814B(x) ((x) & (~BITS_MAX_TX_PKT_V1_8814B)) +#define BIT_GET_MAX_TX_PKT_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_V1_8814B) & BIT_MASK_MAX_TX_PKT_V1_8814B) +#define BIT_SET_MAX_TX_PKT_V1_8814B(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_V1_8814B(x) | BIT_MAX_TX_PKT_V1_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B 20 +#define BIT_MASK_R_BCN_HEAD_SEL_V1_8814B 0x7 +#define BIT_R_BCN_HEAD_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_R_BCN_HEAD_SEL_V1_8814B) \ + << BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B) +#define BITS_R_BCN_HEAD_SEL_V1_8814B \ + (BIT_MASK_R_BCN_HEAD_SEL_V1_8814B << BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B) +#define BIT_CLEAR_R_BCN_HEAD_SEL_V1_8814B(x) \ + ((x) & (~BITS_R_BCN_HEAD_SEL_V1_8814B)) +#define BIT_GET_R_BCN_HEAD_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B) & \ + BIT_MASK_R_BCN_HEAD_SEL_V1_8814B) +#define BIT_SET_R_BCN_HEAD_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_R_BCN_HEAD_SEL_V1_8814B(x) | BIT_R_BCN_HEAD_SEL_V1_8814B(v)) + +#define BIT_SHIFT_LLT_FREE_PAGE_V2_8814B 8 +#define BIT_MASK_LLT_FREE_PAGE_V2_8814B 0xfff +#define BIT_LLT_FREE_PAGE_V2_8814B(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V2_8814B) \ + << BIT_SHIFT_LLT_FREE_PAGE_V2_8814B) +#define BITS_LLT_FREE_PAGE_V2_8814B \ + (BIT_MASK_LLT_FREE_PAGE_V2_8814B << BIT_SHIFT_LLT_FREE_PAGE_V2_8814B) +#define BIT_CLEAR_LLT_FREE_PAGE_V2_8814B(x) \ + ((x) & (~BITS_LLT_FREE_PAGE_V2_8814B)) +#define BIT_GET_LLT_FREE_PAGE_V2_8814B(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2_8814B) & \ + BIT_MASK_LLT_FREE_PAGE_V2_8814B) +#define BIT_SET_LLT_FREE_PAGE_V2_8814B(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V2_8814B(x) | BIT_LLT_FREE_PAGE_V2_8814B(v)) + +#define BIT_SHIFT_BLK_DESC_NUM_8814B 4 +#define BIT_MASK_BLK_DESC_NUM_8814B 0xf +#define BIT_BLK_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM_8814B) << BIT_SHIFT_BLK_DESC_NUM_8814B) +#define BITS_BLK_DESC_NUM_8814B \ + (BIT_MASK_BLK_DESC_NUM_8814B << BIT_SHIFT_BLK_DESC_NUM_8814B) +#define BIT_CLEAR_BLK_DESC_NUM_8814B(x) ((x) & (~BITS_BLK_DESC_NUM_8814B)) +#define BIT_GET_BLK_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM_8814B) & BIT_MASK_BLK_DESC_NUM_8814B) +#define BIT_SET_BLK_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM_8814B(x) | BIT_BLK_DESC_NUM_8814B(v)) + +#define BIT_TDE_ERROR_STOP_8814B BIT(3) +#define BIT_R_EN_BCN_SW_HEAD_SEL_8814B BIT(2) +#define BIT_LLT_DBG_SEL_8814B BIT(1) +#define BIT_AUTO_INIT_LLT_V1_8814B BIT(0) + +/* 2 REG_TXDMA_OFFSET_CHK_8814B */ +#define BIT_EM_CHKSUM_FIN_8814B BIT(31) +#define BIT_EMN_PCIE_DMA_MOD_8814B BIT(30) +#define BIT_EN_TXQUE_CLR_8814B BIT(29) +#define BIT_EN_PCIE_FIFO_MODE_8814B BIT(28) + +#define BIT_SHIFT_PG_UNDER_TH_V1_8814B 16 +#define BIT_MASK_PG_UNDER_TH_V1_8814B 0xfff +#define BIT_PG_UNDER_TH_V1_8814B(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1_8814B) \ + << BIT_SHIFT_PG_UNDER_TH_V1_8814B) +#define BITS_PG_UNDER_TH_V1_8814B \ + (BIT_MASK_PG_UNDER_TH_V1_8814B << BIT_SHIFT_PG_UNDER_TH_V1_8814B) +#define BIT_CLEAR_PG_UNDER_TH_V1_8814B(x) ((x) & (~BITS_PG_UNDER_TH_V1_8814B)) +#define BIT_GET_PG_UNDER_TH_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8814B) & \ + BIT_MASK_PG_UNDER_TH_V1_8814B) +#define BIT_SET_PG_UNDER_TH_V1_8814B(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1_8814B(x) | BIT_PG_UNDER_TH_V1_8814B(v)) + +#define BIT_R_EN_RESET_RESTORE_H2C_8814B BIT(15) +#define BIT_SDIO_TDE_FINISH_8814B BIT(14) +#define BIT_SDIO_TXDESC_CHKSUM_EN_8814B BIT(13) +#define BIT_RST_RDPTR_8814B BIT(12) +#define BIT_RST_WRPTR_8814B BIT(11) +#define BIT_CHK_PG_TH_EN_8814B BIT(10) +#define BIT_DROP_DATA_EN_8814B BIT(9) +#define BIT_CHECK_OFFSET_EN_8814B BIT(8) + +#define BIT_SHIFT_CHECK_OFFSET_8814B 0 +#define BIT_MASK_CHECK_OFFSET_8814B 0xff +#define BIT_CHECK_OFFSET_8814B(x) \ + (((x) & BIT_MASK_CHECK_OFFSET_8814B) << BIT_SHIFT_CHECK_OFFSET_8814B) +#define BITS_CHECK_OFFSET_8814B \ + (BIT_MASK_CHECK_OFFSET_8814B << BIT_SHIFT_CHECK_OFFSET_8814B) +#define BIT_CLEAR_CHECK_OFFSET_8814B(x) ((x) & (~BITS_CHECK_OFFSET_8814B)) +#define BIT_GET_CHECK_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET_8814B) & BIT_MASK_CHECK_OFFSET_8814B) +#define BIT_SET_CHECK_OFFSET_8814B(x, v) \ + (BIT_CLEAR_CHECK_OFFSET_8814B(x) | BIT_CHECK_OFFSET_8814B(v)) + +/* 2 REG_TXDMA_STATUS_8814B */ +#define BIT_AMSDU_PKT_SIZE_ERR_8814B BIT(31) +#define BIT_AMSDU_EN_ERR_8814B BIT(30) +#define BIT_CHKSUM_AMSDU_EN_ERR_8814B BIT(29) +#define BIT_TXPKTBF_REQ_ERR_8814B BIT(28) +#define BIT_OQT_UDN_16_8814B BIT(27) +#define BIT_OQT_OVF_16_8814B BIT(26) +#define BIT_OQT_UDN_14_15_8814B BIT(25) +#define BIT_OQT_OVF_14_15_8814B BIT(24) +#define BIT_OQT_UDN_13_8814B BIT(23) +#define BIT_OQT_OVF_13_8814B BIT(22) +#define BIT_OQT_UDN_12_8814B BIT(21) +#define BIT_OQT_OVF_12_8814B BIT(20) +#define BIT_OQT_UDN_8_11_8814B BIT(19) +#define BIT_OQT_OVF_8_11_8814B BIT(18) +#define BIT_OQT_UDN_4_7_8814B BIT(17) +#define BIT_OQT_OVF_4_7_8814B BIT(16) +#define BIT_PAYLOAD_CHKSUM_ERR_8814B BIT(15) +#define BIT_PAYLOAD_UDN_8814B BIT(14) +#define BIT_PAYLOAD_OVF_8814B BIT(13) +#define BIT_DSC_CHKSUM_FAIL_8814B BIT(12) +#define BIT_EP_QSEL_DIFF_8814B BIT(10) +#define BIT_TX_OFFS_UNMATCH_8814B BIT(9) +#define BIT_TXOQT_UDN_0_3_8814B BIT(8) +#define BIT_TXOQT_OVF_0_3_8814B BIT(7) +#define BIT_TXDMA_SFF_UDN_8814B BIT(6) +#define BIT_TXDMA_SFF_OVF_8814B BIT(5) +#define BIT_LLT_NULL_PG_8814B BIT(4) +#define BIT_PAGE_UDN_8814B BIT(3) +#define BIT_PAGE_OVF_8814B BIT(2) +#define BIT_TXFF_PG_UDN_8814B BIT(1) +#define BIT_TXFF_PG_OVF_8814B BIT(0) + +/* 2 REG_TX_DMA_DBG_8814B */ -#define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8814B 24 -#define BIT_MASK_RXDMA_AGG_OLD_MOD_8814B 0xff -#define BIT_RXDMA_AGG_OLD_MOD_8814B(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD_8814B) << BIT_SHIFT_RXDMA_AGG_OLD_MOD_8814B) -#define BIT_GET_RXDMA_AGG_OLD_MOD_8814B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8814B) & BIT_MASK_RXDMA_AGG_OLD_MOD_8814B) +/* 2 REG_DMA_RQPN_INFO_PUB_8814B */ + +#define BIT_SHIFT_PUB_AVAL_PG_8814B 16 +#define BIT_MASK_PUB_AVAL_PG_8814B 0xfff +#define BIT_PUB_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_PUB_AVAL_PG_8814B) << BIT_SHIFT_PUB_AVAL_PG_8814B) +#define BITS_PUB_AVAL_PG_8814B \ + (BIT_MASK_PUB_AVAL_PG_8814B << BIT_SHIFT_PUB_AVAL_PG_8814B) +#define BIT_CLEAR_PUB_AVAL_PG_8814B(x) ((x) & (~BITS_PUB_AVAL_PG_8814B)) +#define BIT_GET_PUB_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_PUB_AVAL_PG_8814B) & BIT_MASK_PUB_AVAL_PG_8814B) +#define BIT_SET_PUB_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_PUB_AVAL_PG_8814B(x) | BIT_PUB_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_PUB_RSVD_PG_8814B 0 +#define BIT_MASK_PUB_RSVD_PG_8814B 0xfff +#define BIT_PUB_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_PUB_RSVD_PG_8814B) << BIT_SHIFT_PUB_RSVD_PG_8814B) +#define BITS_PUB_RSVD_PG_8814B \ + (BIT_MASK_PUB_RSVD_PG_8814B << BIT_SHIFT_PUB_RSVD_PG_8814B) +#define BIT_CLEAR_PUB_RSVD_PG_8814B(x) ((x) & (~BITS_PUB_RSVD_PG_8814B)) +#define BIT_GET_PUB_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_PUB_RSVD_PG_8814B) & BIT_MASK_PUB_RSVD_PG_8814B) +#define BIT_SET_PUB_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_PUB_RSVD_PG_8814B(x) | BIT_PUB_RSVD_PG_8814B(v)) + +/* 2 REG_RQPN_CTRL_2_V1_8814B */ +#define BIT_LD_RQPN_V1_8814B BIT(31) +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CH16_PUBLIC_DIS_8814B BIT(16) +#define BIT_CH15_PUBLIC_DIS_8814B BIT(15) +#define BIT_CH14_PUBLIC_DIS_8814B BIT(14) +#define BIT_CH13_PUBLIC_DIS_8814B BIT(13) +#define BIT_CH12_PUBLIC_DIS_8814B BIT(12) +#define BIT_CH11_PUBLIC_DIS_8814B BIT(11) +#define BIT_CH10_PUBLIC_DIS_8814B BIT(10) +#define BIT_CH9_PUBLIC_DIS_8814B BIT(9) +#define BIT_CH8_PUBLIC_DIS_8814B BIT(8) +#define BIT_CH7_PUBLIC_DIS_8814B BIT(7) +#define BIT_CH6_PUBLIC_DIS_8814B BIT(6) +#define BIT_CH5_PUBLIC_DIS_8814B BIT(5) +#define BIT_CH4_PUBLIC_DIS_8814B BIT(4) +#define BIT_CH3_PUBLIC_DIS_8814B BIT(3) +#define BIT_CH2_PUBLIC_DIS_8814B BIT(2) +#define BIT_CH1_PUBLIC_DIS_8814B BIT(1) +#define BIT_CH0_PUBLIC_DIS_8814B BIT(0) + +/* 2 REG_BCN_CTRL_2_8814B */ +#define BIT_BCN0_EXT_VALID_8814B BIT(31) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_BCN0_EXT_HEAD_8814B 16 +#define BIT_MASK_BCN0_EXT_HEAD_8814B 0xfff +#define BIT_BCN0_EXT_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN0_EXT_HEAD_8814B) << BIT_SHIFT_BCN0_EXT_HEAD_8814B) +#define BITS_BCN0_EXT_HEAD_8814B \ + (BIT_MASK_BCN0_EXT_HEAD_8814B << BIT_SHIFT_BCN0_EXT_HEAD_8814B) +#define BIT_CLEAR_BCN0_EXT_HEAD_8814B(x) ((x) & (~BITS_BCN0_EXT_HEAD_8814B)) +#define BIT_GET_BCN0_EXT_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN0_EXT_HEAD_8814B) & BIT_MASK_BCN0_EXT_HEAD_8814B) +#define BIT_SET_BCN0_EXT_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN0_EXT_HEAD_8814B(x) | BIT_BCN0_EXT_HEAD_8814B(v)) + +#define BIT_BCN4_VALID_8814B BIT(15) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_BCN4_HEAD_8814B 0 +#define BIT_MASK_BCN4_HEAD_8814B 0xfff +#define BIT_BCN4_HEAD_8814B(x) \ + (((x) & BIT_MASK_BCN4_HEAD_8814B) << BIT_SHIFT_BCN4_HEAD_8814B) +#define BITS_BCN4_HEAD_8814B \ + (BIT_MASK_BCN4_HEAD_8814B << BIT_SHIFT_BCN4_HEAD_8814B) +#define BIT_CLEAR_BCN4_HEAD_8814B(x) ((x) & (~BITS_BCN4_HEAD_8814B)) +#define BIT_GET_BCN4_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_BCN4_HEAD_8814B) & BIT_MASK_BCN4_HEAD_8814B) +#define BIT_SET_BCN4_HEAD_8814B(x, v) \ + (BIT_CLEAR_BCN4_HEAD_8814B(x) | BIT_BCN4_HEAD_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_TXPKTNUM_0_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH4_7_8814B 16 +#define BIT_MASK_TXPKTNUM_CH4_7_8814B 0xfff +#define BIT_TXPKTNUM_CH4_7_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH4_7_8814B) \ + << BIT_SHIFT_TXPKTNUM_CH4_7_8814B) +#define BITS_TXPKTNUM_CH4_7_8814B \ + (BIT_MASK_TXPKTNUM_CH4_7_8814B << BIT_SHIFT_TXPKTNUM_CH4_7_8814B) +#define BIT_CLEAR_TXPKTNUM_CH4_7_8814B(x) ((x) & (~BITS_TXPKTNUM_CH4_7_8814B)) +#define BIT_GET_TXPKTNUM_CH4_7_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH4_7_8814B) & \ + BIT_MASK_TXPKTNUM_CH4_7_8814B) +#define BIT_SET_TXPKTNUM_CH4_7_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH4_7_8814B(x) | BIT_TXPKTNUM_CH4_7_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH0_3_8814B 0 +#define BIT_MASK_TXPKTNUM_CH0_3_8814B 0xfff +#define BIT_TXPKTNUM_CH0_3_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH0_3_8814B) \ + << BIT_SHIFT_TXPKTNUM_CH0_3_8814B) +#define BITS_TXPKTNUM_CH0_3_8814B \ + (BIT_MASK_TXPKTNUM_CH0_3_8814B << BIT_SHIFT_TXPKTNUM_CH0_3_8814B) +#define BIT_CLEAR_TXPKTNUM_CH0_3_8814B(x) ((x) & (~BITS_TXPKTNUM_CH0_3_8814B)) +#define BIT_GET_TXPKTNUM_CH0_3_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH0_3_8814B) & \ + BIT_MASK_TXPKTNUM_CH0_3_8814B) +#define BIT_SET_TXPKTNUM_CH0_3_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH0_3_8814B(x) | BIT_TXPKTNUM_CH0_3_8814B(v)) + +/* 2 REG_TXPKTNUM_1_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH12_8814B 16 +#define BIT_MASK_TXPKTNUM_CH12_8814B 0xfff +#define BIT_TXPKTNUM_CH12_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH12_8814B) << BIT_SHIFT_TXPKTNUM_CH12_8814B) +#define BITS_TXPKTNUM_CH12_8814B \ + (BIT_MASK_TXPKTNUM_CH12_8814B << BIT_SHIFT_TXPKTNUM_CH12_8814B) +#define BIT_CLEAR_TXPKTNUM_CH12_8814B(x) ((x) & (~BITS_TXPKTNUM_CH12_8814B)) +#define BIT_GET_TXPKTNUM_CH12_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH12_8814B) & BIT_MASK_TXPKTNUM_CH12_8814B) +#define BIT_SET_TXPKTNUM_CH12_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH12_8814B(x) | BIT_TXPKTNUM_CH12_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH8_11_8814B 0 +#define BIT_MASK_TXPKTNUM_CH8_11_8814B 0xfff +#define BIT_TXPKTNUM_CH8_11_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH8_11_8814B) \ + << BIT_SHIFT_TXPKTNUM_CH8_11_8814B) +#define BITS_TXPKTNUM_CH8_11_8814B \ + (BIT_MASK_TXPKTNUM_CH8_11_8814B << BIT_SHIFT_TXPKTNUM_CH8_11_8814B) +#define BIT_CLEAR_TXPKTNUM_CH8_11_8814B(x) ((x) & (~BITS_TXPKTNUM_CH8_11_8814B)) +#define BIT_GET_TXPKTNUM_CH8_11_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH8_11_8814B) & \ + BIT_MASK_TXPKTNUM_CH8_11_8814B) +#define BIT_SET_TXPKTNUM_CH8_11_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH8_11_8814B(x) | BIT_TXPKTNUM_CH8_11_8814B(v)) + +/* 2 REG_TXPKTNUM_2_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH14_15_8814B 16 +#define BIT_MASK_TXPKTNUM_CH14_15_8814B 0xfff +#define BIT_TXPKTNUM_CH14_15_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH14_15_8814B) \ + << BIT_SHIFT_TXPKTNUM_CH14_15_8814B) +#define BITS_TXPKTNUM_CH14_15_8814B \ + (BIT_MASK_TXPKTNUM_CH14_15_8814B << BIT_SHIFT_TXPKTNUM_CH14_15_8814B) +#define BIT_CLEAR_TXPKTNUM_CH14_15_8814B(x) \ + ((x) & (~BITS_TXPKTNUM_CH14_15_8814B)) +#define BIT_GET_TXPKTNUM_CH14_15_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH14_15_8814B) & \ + BIT_MASK_TXPKTNUM_CH14_15_8814B) +#define BIT_SET_TXPKTNUM_CH14_15_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH14_15_8814B(x) | BIT_TXPKTNUM_CH14_15_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH13_8814B 0 +#define BIT_MASK_TXPKTNUM_CH13_8814B 0xfff +#define BIT_TXPKTNUM_CH13_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH13_8814B) << BIT_SHIFT_TXPKTNUM_CH13_8814B) +#define BITS_TXPKTNUM_CH13_8814B \ + (BIT_MASK_TXPKTNUM_CH13_8814B << BIT_SHIFT_TXPKTNUM_CH13_8814B) +#define BIT_CLEAR_TXPKTNUM_CH13_8814B(x) ((x) & (~BITS_TXPKTNUM_CH13_8814B)) +#define BIT_GET_TXPKTNUM_CH13_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH13_8814B) & BIT_MASK_TXPKTNUM_CH13_8814B) +#define BIT_SET_TXPKTNUM_CH13_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH13_8814B(x) | BIT_TXPKTNUM_CH13_8814B(v)) + +/* 2 REG_TXPKTNUM_3_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +#define BIT_SHIFT_TXPKTNUM_CH16_8814B 0 +#define BIT_MASK_TXPKTNUM_CH16_8814B 0xfff +#define BIT_TXPKTNUM_CH16_8814B(x) \ + (((x) & BIT_MASK_TXPKTNUM_CH16_8814B) << BIT_SHIFT_TXPKTNUM_CH16_8814B) +#define BITS_TXPKTNUM_CH16_8814B \ + (BIT_MASK_TXPKTNUM_CH16_8814B << BIT_SHIFT_TXPKTNUM_CH16_8814B) +#define BIT_CLEAR_TXPKTNUM_CH16_8814B(x) ((x) & (~BITS_TXPKTNUM_CH16_8814B)) +#define BIT_GET_TXPKTNUM_CH16_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_CH16_8814B) & BIT_MASK_TXPKTNUM_CH16_8814B) +#define BIT_SET_TXPKTNUM_CH16_8814B(x, v) \ + (BIT_CLEAR_TXPKTNUM_CH16_8814B(x) | BIT_TXPKTNUM_CH16_8814B(v)) + +/* 2 REG_TX_AGG_ALIGN_8814B */ + +#define BIT_SHIFT_HW_FLOW_CTL_EN_8814B 16 +#define BIT_MASK_HW_FLOW_CTL_EN_8814B 0xffff +#define BIT_HW_FLOW_CTL_EN_8814B(x) \ + (((x) & BIT_MASK_HW_FLOW_CTL_EN_8814B) \ + << BIT_SHIFT_HW_FLOW_CTL_EN_8814B) +#define BITS_HW_FLOW_CTL_EN_8814B \ + (BIT_MASK_HW_FLOW_CTL_EN_8814B << BIT_SHIFT_HW_FLOW_CTL_EN_8814B) +#define BIT_CLEAR_HW_FLOW_CTL_EN_8814B(x) ((x) & (~BITS_HW_FLOW_CTL_EN_8814B)) +#define BIT_GET_HW_FLOW_CTL_EN_8814B(x) \ + (((x) >> BIT_SHIFT_HW_FLOW_CTL_EN_8814B) & \ + BIT_MASK_HW_FLOW_CTL_EN_8814B) +#define BIT_SET_HW_FLOW_CTL_EN_8814B(x, v) \ + (BIT_CLEAR_HW_FLOW_CTL_EN_8814B(x) | BIT_HW_FLOW_CTL_EN_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_V1_8814B BIT(15) + +#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B 0 +#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B 0xfff +#define BIT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) \ + (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) +#define BITS_SDIO_TXAGG_ALIGN_SIZE_V1_8814B \ + (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) +#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) \ + ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) & \ + BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) +#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x, v) \ + (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) | \ + BIT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(v)) + +/* 2 REG_H2C_HEAD_8814B */ + +#define BIT_SHIFT_H2C_HEAD_V1_8814B 0 +#define BIT_MASK_H2C_HEAD_V1_8814B 0x7ffff +#define BIT_H2C_HEAD_V1_8814B(x) \ + (((x) & BIT_MASK_H2C_HEAD_V1_8814B) << BIT_SHIFT_H2C_HEAD_V1_8814B) +#define BITS_H2C_HEAD_V1_8814B \ + (BIT_MASK_H2C_HEAD_V1_8814B << BIT_SHIFT_H2C_HEAD_V1_8814B) +#define BIT_CLEAR_H2C_HEAD_V1_8814B(x) ((x) & (~BITS_H2C_HEAD_V1_8814B)) +#define BIT_GET_H2C_HEAD_V1_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_V1_8814B) & BIT_MASK_H2C_HEAD_V1_8814B) +#define BIT_SET_H2C_HEAD_V1_8814B(x, v) \ + (BIT_CLEAR_H2C_HEAD_V1_8814B(x) | BIT_H2C_HEAD_V1_8814B(v)) + +/* 2 REG_H2C_TAIL_8814B */ + +#define BIT_SHIFT_H2C_TAIL_V1_8814B 0 +#define BIT_MASK_H2C_TAIL_V1_8814B 0x7ffff +#define BIT_H2C_TAIL_V1_8814B(x) \ + (((x) & BIT_MASK_H2C_TAIL_V1_8814B) << BIT_SHIFT_H2C_TAIL_V1_8814B) +#define BITS_H2C_TAIL_V1_8814B \ + (BIT_MASK_H2C_TAIL_V1_8814B << BIT_SHIFT_H2C_TAIL_V1_8814B) +#define BIT_CLEAR_H2C_TAIL_V1_8814B(x) ((x) & (~BITS_H2C_TAIL_V1_8814B)) +#define BIT_GET_H2C_TAIL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_V1_8814B) & BIT_MASK_H2C_TAIL_V1_8814B) +#define BIT_SET_H2C_TAIL_V1_8814B(x, v) \ + (BIT_CLEAR_H2C_TAIL_V1_8814B(x) | BIT_H2C_TAIL_V1_8814B(v)) -#define BIT_SHIFT_PKT_NUM_WOL_8814B 16 -#define BIT_MASK_PKT_NUM_WOL_8814B 0xff -#define BIT_PKT_NUM_WOL_8814B(x) (((x) & BIT_MASK_PKT_NUM_WOL_8814B) << BIT_SHIFT_PKT_NUM_WOL_8814B) -#define BIT_GET_PKT_NUM_WOL_8814B(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8814B) & BIT_MASK_PKT_NUM_WOL_8814B) +/* 2 REG_H2C_READ_ADDR_8814B */ +#define BIT_SHIFT_H2C_READ_ADDR_V1_8814B 0 +#define BIT_MASK_H2C_READ_ADDR_V1_8814B 0x7ffff +#define BIT_H2C_READ_ADDR_V1_8814B(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_V1_8814B) \ + << BIT_SHIFT_H2C_READ_ADDR_V1_8814B) +#define BITS_H2C_READ_ADDR_V1_8814B \ + (BIT_MASK_H2C_READ_ADDR_V1_8814B << BIT_SHIFT_H2C_READ_ADDR_V1_8814B) +#define BIT_CLEAR_H2C_READ_ADDR_V1_8814B(x) \ + ((x) & (~BITS_H2C_READ_ADDR_V1_8814B)) +#define BIT_GET_H2C_READ_ADDR_V1_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_V1_8814B) & \ + BIT_MASK_H2C_READ_ADDR_V1_8814B) +#define BIT_SET_H2C_READ_ADDR_V1_8814B(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_V1_8814B(x) | BIT_H2C_READ_ADDR_V1_8814B(v)) +/* 2 REG_H2C_WR_ADDR_8814B */ -#define BIT_SHIFT_DMA_AGG_TO_8814B 8 -#define BIT_MASK_DMA_AGG_TO_8814B 0xf -#define BIT_DMA_AGG_TO_8814B(x) (((x) & BIT_MASK_DMA_AGG_TO_8814B) << BIT_SHIFT_DMA_AGG_TO_8814B) -#define BIT_GET_DMA_AGG_TO_8814B(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8814B) & BIT_MASK_DMA_AGG_TO_8814B) +#define BIT_SHIFT_H2C_WR_ADDR_V1_8814B 0 +#define BIT_MASK_H2C_WR_ADDR_V1_8814B 0x7ffff +#define BIT_H2C_WR_ADDR_V1_8814B(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_V1_8814B) \ + << BIT_SHIFT_H2C_WR_ADDR_V1_8814B) +#define BITS_H2C_WR_ADDR_V1_8814B \ + (BIT_MASK_H2C_WR_ADDR_V1_8814B << BIT_SHIFT_H2C_WR_ADDR_V1_8814B) +#define BIT_CLEAR_H2C_WR_ADDR_V1_8814B(x) ((x) & (~BITS_H2C_WR_ADDR_V1_8814B)) +#define BIT_GET_H2C_WR_ADDR_V1_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_V1_8814B) & \ + BIT_MASK_H2C_WR_ADDR_V1_8814B) +#define BIT_SET_H2C_WR_ADDR_V1_8814B(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_V1_8814B(x) | BIT_H2C_WR_ADDR_V1_8814B(v)) +/* 2 REG_H2C_INFO_8814B */ +#define BIT_H2C_SPACE_VLD_8814B BIT(3) +#define BIT_H2C_WR_ADDR_RST_8814B BIT(2) +#define BIT_SHIFT_H2C_LEN_SEL_8814B 0 +#define BIT_MASK_H2C_LEN_SEL_8814B 0x3 +#define BIT_H2C_LEN_SEL_8814B(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL_8814B) << BIT_SHIFT_H2C_LEN_SEL_8814B) +#define BITS_H2C_LEN_SEL_8814B \ + (BIT_MASK_H2C_LEN_SEL_8814B << BIT_SHIFT_H2C_LEN_SEL_8814B) +#define BIT_CLEAR_H2C_LEN_SEL_8814B(x) ((x) & (~BITS_H2C_LEN_SEL_8814B)) +#define BIT_GET_H2C_LEN_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL_8814B) & BIT_MASK_H2C_LEN_SEL_8814B) +#define BIT_SET_H2C_LEN_SEL_8814B(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL_8814B(x) | BIT_H2C_LEN_SEL_8814B(v)) + +/* 2 REG_DMA_OQT_0_8814B */ + +#define BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B 24 +#define BIT_MASK_TX_OQT_12_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_12_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_12_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B) +#define BITS_TX_OQT_12_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_12_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_12_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_12_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_12_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_12_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_12_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_12_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_12_FREE_SPACE_8814B(v)) + +#define BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B 16 +#define BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_8_11_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B) +#define BITS_TX_OQT_8_11_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_8_11_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_8_11_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_8_11_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_8_11_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_8_11_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_8_11_FREE_SPACE_8814B(v)) + +#define BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B 8 +#define BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_4_7_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B) +#define BITS_TX_OQT_4_7_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_4_7_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_4_7_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_4_7_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_4_7_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_4_7_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_4_7_FREE_SPACE_8814B(v)) + +#define BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B 0 +#define BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_0_3_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B) +#define BITS_TX_OQT_0_3_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_0_3_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_0_3_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_0_3_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_0_3_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_0_3_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_0_3_FREE_SPACE_8814B(v)) + +/* 2 REG_DMA_OQT_1_8814B */ -#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8814B 0 -#define BIT_MASK_RXDMA_AGG_PG_TH_V1_8814B 0xf -#define BIT_RXDMA_AGG_PG_TH_V1_8814B(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8814B) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8814B) -#define BIT_GET_RXDMA_AGG_PG_TH_V1_8814B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8814B) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B 16 +#define BIT_MASK_TX_OQT_16_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_16_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_16_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B) +#define BITS_TX_OQT_16_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_16_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_16_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_16_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_16_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_16_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_16_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_16_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_16_FREE_SPACE_8814B(v)) + +#define BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B 8 +#define BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_14_15_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B) +#define BITS_TX_OQT_14_15_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_14_15_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_14_15_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_14_15_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_14_15_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_14_15_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_14_15_FREE_SPACE_8814B(v)) + +#define BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B 0 +#define BIT_MASK_TX_OQT_13_FREE_SPACE_8814B 0xff +#define BIT_TX_OQT_13_FREE_SPACE_8814B(x) \ + (((x) & BIT_MASK_TX_OQT_13_FREE_SPACE_8814B) \ + << BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B) +#define BITS_TX_OQT_13_FREE_SPACE_8814B \ + (BIT_MASK_TX_OQT_13_FREE_SPACE_8814B \ + << BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B) +#define BIT_CLEAR_TX_OQT_13_FREE_SPACE_8814B(x) \ + ((x) & (~BITS_TX_OQT_13_FREE_SPACE_8814B)) +#define BIT_GET_TX_OQT_13_FREE_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B) & \ + BIT_MASK_TX_OQT_13_FREE_SPACE_8814B) +#define BIT_SET_TX_OQT_13_FREE_SPACE_8814B(x, v) \ + (BIT_CLEAR_TX_OQT_13_FREE_SPACE_8814B(x) | \ + BIT_TX_OQT_13_FREE_SPACE_8814B(v)) +/* 2 REG_RXDMA_AGG_PG_TH_8814B */ +#define BIT_DMA_STORE_8814B BIT(31) -/* 2 REG_RXPKT_NUM_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_EN_PRE_CALC_8814B BIT(29) +#define BIT_RXAGG_SW_EN_8814B BIT(28) +#define BIT_RXAGG_SW_TRIG_8814B BIT(27) -#define BIT_SHIFT_RXPKT_NUM_8814B 24 -#define BIT_MASK_RXPKT_NUM_8814B 0xff -#define BIT_RXPKT_NUM_8814B(x) (((x) & BIT_MASK_RXPKT_NUM_8814B) << BIT_SHIFT_RXPKT_NUM_8814B) -#define BIT_GET_RXPKT_NUM_8814B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8814B) & BIT_MASK_RXPKT_NUM_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_DMA_AGG_TO_V1_8814B 8 +#define BIT_MASK_DMA_AGG_TO_V1_8814B 0xff +#define BIT_DMA_AGG_TO_V1_8814B(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1_8814B) << BIT_SHIFT_DMA_AGG_TO_V1_8814B) +#define BITS_DMA_AGG_TO_V1_8814B \ + (BIT_MASK_DMA_AGG_TO_V1_8814B << BIT_SHIFT_DMA_AGG_TO_V1_8814B) +#define BIT_CLEAR_DMA_AGG_TO_V1_8814B(x) ((x) & (~BITS_DMA_AGG_TO_V1_8814B)) +#define BIT_GET_DMA_AGG_TO_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8814B) & BIT_MASK_DMA_AGG_TO_V1_8814B) +#define BIT_SET_DMA_AGG_TO_V1_8814B(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1_8814B(x) | BIT_DMA_AGG_TO_V1_8814B(v)) + +#define BIT_SHIFT_RXDMA_AGG_PG_TH_8814B 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_8814B 0xff +#define BIT_RXDMA_AGG_PG_TH_8814B(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8814B) \ + << BIT_SHIFT_RXDMA_AGG_PG_TH_8814B) +#define BITS_RXDMA_AGG_PG_TH_8814B \ + (BIT_MASK_RXDMA_AGG_PG_TH_8814B << BIT_SHIFT_RXDMA_AGG_PG_TH_8814B) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_8814B(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8814B)) +#define BIT_GET_RXDMA_AGG_PG_TH_8814B(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8814B) & \ + BIT_MASK_RXDMA_AGG_PG_TH_8814B) +#define BIT_SET_RXDMA_AGG_PG_TH_8814B(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_8814B(x) | BIT_RXDMA_AGG_PG_TH_8814B(v)) + +/* 2 REG_RXDMA_CTRL_8814B */ +/* 2 REG_NOT_VALID_8814B */ #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B 20 #define BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B 0xf -#define BIT_FW_UPD_RDPTR19_TO_16_8814B(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) -#define BIT_GET_FW_UPD_RDPTR19_TO_16_8814B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B) - +#define BIT_FW_UPD_RDPTR19_TO_16_8814B(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) +#define BITS_FW_UPD_RDPTR19_TO_16_8814B \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8814B(x) \ + ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8814B)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8814B(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B) +#define BIT_SET_FW_UPD_RDPTR19_TO_16_8814B(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8814B(x) | \ + BIT_FW_UPD_RDPTR19_TO_16_8814B(v)) #define BIT_RXDMA_REQ_8814B BIT(19) #define BIT_RW_RELEASE_EN_8814B BIT(18) @@ -3916,12 +7822,19 @@ #define BIT_SHIFT_FW_UPD_RDPTR_8814B 0 #define BIT_MASK_FW_UPD_RDPTR_8814B 0xffff -#define BIT_FW_UPD_RDPTR_8814B(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8814B) << BIT_SHIFT_FW_UPD_RDPTR_8814B) -#define BIT_GET_FW_UPD_RDPTR_8814B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8814B) & BIT_MASK_FW_UPD_RDPTR_8814B) - - +#define BIT_FW_UPD_RDPTR_8814B(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR_8814B) << BIT_SHIFT_FW_UPD_RDPTR_8814B) +#define BITS_FW_UPD_RDPTR_8814B \ + (BIT_MASK_FW_UPD_RDPTR_8814B << BIT_SHIFT_FW_UPD_RDPTR_8814B) +#define BIT_CLEAR_FW_UPD_RDPTR_8814B(x) ((x) & (~BITS_FW_UPD_RDPTR_8814B)) +#define BIT_GET_FW_UPD_RDPTR_8814B(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8814B) & BIT_MASK_FW_UPD_RDPTR_8814B) +#define BIT_SET_FW_UPD_RDPTR_8814B(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR_8814B(x) | BIT_FW_UPD_RDPTR_8814B(v)) /* 2 REG_RXDMA_STATUS_8814B */ + +/* 2 REG_NOT_VALID_8814B */ #define BIT_C2H_PKT_OVF_8814B BIT(7) #define BIT_AGG_CONFGI_ISSUE_8814B BIT(6) #define BIT_FW_POLL_ISSUE_8814B BIT(5) @@ -3934,40 +7847,70 @@ #define BIT_SHIFT_RDE_DEBUG_8814B 0 #define BIT_MASK_RDE_DEBUG_8814B 0xffffffffL -#define BIT_RDE_DEBUG_8814B(x) (((x) & BIT_MASK_RDE_DEBUG_8814B) << BIT_SHIFT_RDE_DEBUG_8814B) -#define BIT_GET_RDE_DEBUG_8814B(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8814B) & BIT_MASK_RDE_DEBUG_8814B) - - +#define BIT_RDE_DEBUG_8814B(x) \ + (((x) & BIT_MASK_RDE_DEBUG_8814B) << BIT_SHIFT_RDE_DEBUG_8814B) +#define BITS_RDE_DEBUG_8814B \ + (BIT_MASK_RDE_DEBUG_8814B << BIT_SHIFT_RDE_DEBUG_8814B) +#define BIT_CLEAR_RDE_DEBUG_8814B(x) ((x) & (~BITS_RDE_DEBUG_8814B)) +#define BIT_GET_RDE_DEBUG_8814B(x) \ + (((x) >> BIT_SHIFT_RDE_DEBUG_8814B) & BIT_MASK_RDE_DEBUG_8814B) +#define BIT_SET_RDE_DEBUG_8814B(x, v) \ + (BIT_CLEAR_RDE_DEBUG_8814B(x) | BIT_RDE_DEBUG_8814B(v)) /* 2 REG_RXDMA_MODE_8814B */ #define BIT_SHIFT_PKTNUM_TH_V2_8814B 24 #define BIT_MASK_PKTNUM_TH_V2_8814B 0x1f -#define BIT_PKTNUM_TH_V2_8814B(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8814B) << BIT_SHIFT_PKTNUM_TH_V2_8814B) -#define BIT_GET_PKTNUM_TH_V2_8814B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8814B) & BIT_MASK_PKTNUM_TH_V2_8814B) - +#define BIT_PKTNUM_TH_V2_8814B(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V2_8814B) << BIT_SHIFT_PKTNUM_TH_V2_8814B) +#define BITS_PKTNUM_TH_V2_8814B \ + (BIT_MASK_PKTNUM_TH_V2_8814B << BIT_SHIFT_PKTNUM_TH_V2_8814B) +#define BIT_CLEAR_PKTNUM_TH_V2_8814B(x) ((x) & (~BITS_PKTNUM_TH_V2_8814B)) +#define BIT_GET_PKTNUM_TH_V2_8814B(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8814B) & BIT_MASK_PKTNUM_TH_V2_8814B) +#define BIT_SET_PKTNUM_TH_V2_8814B(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V2_8814B(x) | BIT_PKTNUM_TH_V2_8814B(v)) #define BIT_TXBA_BREAK_USBAGG_8814B BIT(23) #define BIT_SHIFT_PKTLEN_PARA_8814B 16 #define BIT_MASK_PKTLEN_PARA_8814B 0x7 -#define BIT_PKTLEN_PARA_8814B(x) (((x) & BIT_MASK_PKTLEN_PARA_8814B) << BIT_SHIFT_PKTLEN_PARA_8814B) -#define BIT_GET_PKTLEN_PARA_8814B(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8814B) & BIT_MASK_PKTLEN_PARA_8814B) - - +#define BIT_PKTLEN_PARA_8814B(x) \ + (((x) & BIT_MASK_PKTLEN_PARA_8814B) << BIT_SHIFT_PKTLEN_PARA_8814B) +#define BITS_PKTLEN_PARA_8814B \ + (BIT_MASK_PKTLEN_PARA_8814B << BIT_SHIFT_PKTLEN_PARA_8814B) +#define BIT_CLEAR_PKTLEN_PARA_8814B(x) ((x) & (~BITS_PKTLEN_PARA_8814B)) +#define BIT_GET_PKTLEN_PARA_8814B(x) \ + (((x) >> BIT_SHIFT_PKTLEN_PARA_8814B) & BIT_MASK_PKTLEN_PARA_8814B) +#define BIT_SET_PKTLEN_PARA_8814B(x, v) \ + (BIT_CLEAR_PKTLEN_PARA_8814B(x) | BIT_PKTLEN_PARA_8814B(v)) + +#define BIT_RX_DBG_SEL_8814B BIT(7) +#define BIT_EN_SPD_8814B BIT(6) #define BIT_SHIFT_BURST_SIZE_8814B 4 #define BIT_MASK_BURST_SIZE_8814B 0x3 -#define BIT_BURST_SIZE_8814B(x) (((x) & BIT_MASK_BURST_SIZE_8814B) << BIT_SHIFT_BURST_SIZE_8814B) -#define BIT_GET_BURST_SIZE_8814B(x) (((x) >> BIT_SHIFT_BURST_SIZE_8814B) & BIT_MASK_BURST_SIZE_8814B) - - +#define BIT_BURST_SIZE_8814B(x) \ + (((x) & BIT_MASK_BURST_SIZE_8814B) << BIT_SHIFT_BURST_SIZE_8814B) +#define BITS_BURST_SIZE_8814B \ + (BIT_MASK_BURST_SIZE_8814B << BIT_SHIFT_BURST_SIZE_8814B) +#define BIT_CLEAR_BURST_SIZE_8814B(x) ((x) & (~BITS_BURST_SIZE_8814B)) +#define BIT_GET_BURST_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE_8814B) & BIT_MASK_BURST_SIZE_8814B) +#define BIT_SET_BURST_SIZE_8814B(x, v) \ + (BIT_CLEAR_BURST_SIZE_8814B(x) | BIT_BURST_SIZE_8814B(v)) #define BIT_SHIFT_BURST_CNT_8814B 2 #define BIT_MASK_BURST_CNT_8814B 0x3 -#define BIT_BURST_CNT_8814B(x) (((x) & BIT_MASK_BURST_CNT_8814B) << BIT_SHIFT_BURST_CNT_8814B) -#define BIT_GET_BURST_CNT_8814B(x) (((x) >> BIT_SHIFT_BURST_CNT_8814B) & BIT_MASK_BURST_CNT_8814B) - +#define BIT_BURST_CNT_8814B(x) \ + (((x) & BIT_MASK_BURST_CNT_8814B) << BIT_SHIFT_BURST_CNT_8814B) +#define BITS_BURST_CNT_8814B \ + (BIT_MASK_BURST_CNT_8814B << BIT_SHIFT_BURST_CNT_8814B) +#define BIT_CLEAR_BURST_CNT_8814B(x) ((x) & (~BITS_BURST_CNT_8814B)) +#define BIT_GET_BURST_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_BURST_CNT_8814B) & BIT_MASK_BURST_CNT_8814B) +#define BIT_SET_BURST_CNT_8814B(x, v) \ + (BIT_CLEAR_BURST_CNT_8814B(x) | BIT_BURST_CNT_8814B(v)) #define BIT_DMA_MODE_8814B BIT(1) @@ -3975,81 +7918,234 @@ #define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B 24 #define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B 0xf -#define BIT_R_C2H_STR_ADDR_16_TO_19_8814B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) -#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8814B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B) - +#define BIT_R_C2H_STR_ADDR_16_TO_19_8814B(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) +#define BITS_R_C2H_STR_ADDR_16_TO_19_8814B \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8814B(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8814B)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8814B(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8814B(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8814B(x) | \ + BIT_R_C2H_STR_ADDR_16_TO_19_8814B(v)) #define BIT_R_C2H_PKT_REQ_8814B BIT(16) #define BIT_SHIFT_R_C2H_STR_ADDR_8814B 0 #define BIT_MASK_R_C2H_STR_ADDR_8814B 0xffff -#define BIT_R_C2H_STR_ADDR_8814B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8814B) << BIT_SHIFT_R_C2H_STR_ADDR_8814B) -#define BIT_GET_R_C2H_STR_ADDR_8814B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8814B) & BIT_MASK_R_C2H_STR_ADDR_8814B) - - +#define BIT_R_C2H_STR_ADDR_8814B(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_8814B) \ + << BIT_SHIFT_R_C2H_STR_ADDR_8814B) +#define BITS_R_C2H_STR_ADDR_8814B \ + (BIT_MASK_R_C2H_STR_ADDR_8814B << BIT_SHIFT_R_C2H_STR_ADDR_8814B) +#define BIT_CLEAR_R_C2H_STR_ADDR_8814B(x) ((x) & (~BITS_R_C2H_STR_ADDR_8814B)) +#define BIT_GET_R_C2H_STR_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8814B) & \ + BIT_MASK_R_C2H_STR_ADDR_8814B) +#define BIT_SET_R_C2H_STR_ADDR_8814B(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_8814B(x) | BIT_R_C2H_STR_ADDR_8814B(v)) /* 2 REG_FWFF_C2H_8814B */ #define BIT_SHIFT_C2H_DMA_ADDR_8814B 0 #define BIT_MASK_C2H_DMA_ADDR_8814B 0x3ffff -#define BIT_C2H_DMA_ADDR_8814B(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8814B) << BIT_SHIFT_C2H_DMA_ADDR_8814B) -#define BIT_GET_C2H_DMA_ADDR_8814B(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8814B) & BIT_MASK_C2H_DMA_ADDR_8814B) - - +#define BIT_C2H_DMA_ADDR_8814B(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR_8814B) << BIT_SHIFT_C2H_DMA_ADDR_8814B) +#define BITS_C2H_DMA_ADDR_8814B \ + (BIT_MASK_C2H_DMA_ADDR_8814B << BIT_SHIFT_C2H_DMA_ADDR_8814B) +#define BIT_CLEAR_C2H_DMA_ADDR_8814B(x) ((x) & (~BITS_C2H_DMA_ADDR_8814B)) +#define BIT_GET_C2H_DMA_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8814B) & BIT_MASK_C2H_DMA_ADDR_8814B) +#define BIT_SET_C2H_DMA_ADDR_8814B(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR_8814B(x) | BIT_C2H_DMA_ADDR_8814B(v)) /* 2 REG_FWFF_CTRL_8814B */ #define BIT_FWFF_DMAPKT_REQ_8814B BIT(31) -#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8814B 16 -#define BIT_MASK_FWFF_DMA_PKT_NUM_8814B 0xff -#define BIT_FWFF_DMA_PKT_NUM_8814B(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8814B) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8814B) -#define BIT_GET_FWFF_DMA_PKT_NUM_8814B(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8814B) & BIT_MASK_FWFF_DMA_PKT_NUM_8814B) - - +#define BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B 16 +#define BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B 0x7fff +#define BIT_FWFF_DMA_PKT_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B) \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B) +#define BITS_FWFF_DMA_PKT_NUM_V1_8814B \ + (BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_V1_8814B(x) \ + ((x) & (~BITS_FWFF_DMA_PKT_NUM_V1_8814B)) +#define BIT_GET_FWFF_DMA_PKT_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B) & \ + BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B) +#define BIT_SET_FWFF_DMA_PKT_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_V1_8814B(x) | \ + BIT_FWFF_DMA_PKT_NUM_V1_8814B(v)) #define BIT_SHIFT_FWFF_STR_ADDR_8814B 0 #define BIT_MASK_FWFF_STR_ADDR_8814B 0xffff -#define BIT_FWFF_STR_ADDR_8814B(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8814B) << BIT_SHIFT_FWFF_STR_ADDR_8814B) -#define BIT_GET_FWFF_STR_ADDR_8814B(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8814B) & BIT_MASK_FWFF_STR_ADDR_8814B) - - +#define BIT_FWFF_STR_ADDR_8814B(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR_8814B) << BIT_SHIFT_FWFF_STR_ADDR_8814B) +#define BITS_FWFF_STR_ADDR_8814B \ + (BIT_MASK_FWFF_STR_ADDR_8814B << BIT_SHIFT_FWFF_STR_ADDR_8814B) +#define BIT_CLEAR_FWFF_STR_ADDR_8814B(x) ((x) & (~BITS_FWFF_STR_ADDR_8814B)) +#define BIT_GET_FWFF_STR_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8814B) & BIT_MASK_FWFF_STR_ADDR_8814B) +#define BIT_SET_FWFF_STR_ADDR_8814B(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR_8814B(x) | BIT_FWFF_STR_ADDR_8814B(v)) /* 2 REG_FWFF_PKT_INFO_8814B */ -#define BIT_SHIFT_FWFF_PKT_QUEUED_8814B 16 -#define BIT_MASK_FWFF_PKT_QUEUED_8814B 0xff -#define BIT_FWFF_PKT_QUEUED_8814B(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8814B) << BIT_SHIFT_FWFF_PKT_QUEUED_8814B) -#define BIT_GET_FWFF_PKT_QUEUED_8814B(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8814B) & BIT_MASK_FWFF_PKT_QUEUED_8814B) +#define BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B 16 +#define BIT_MASK_FWFF_PKT_READ_ADDR_8814B 0xffff +#define BIT_FWFF_PKT_READ_ADDR_8814B(x) \ + (((x) & BIT_MASK_FWFF_PKT_READ_ADDR_8814B) \ + << BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B) +#define BITS_FWFF_PKT_READ_ADDR_8814B \ + (BIT_MASK_FWFF_PKT_READ_ADDR_8814B \ + << BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B) +#define BIT_CLEAR_FWFF_PKT_READ_ADDR_8814B(x) \ + ((x) & (~BITS_FWFF_PKT_READ_ADDR_8814B)) +#define BIT_GET_FWFF_PKT_READ_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B) & \ + BIT_MASK_FWFF_PKT_READ_ADDR_8814B) +#define BIT_SET_FWFF_PKT_READ_ADDR_8814B(x, v) \ + (BIT_CLEAR_FWFF_PKT_READ_ADDR_8814B(x) | \ + BIT_FWFF_PKT_READ_ADDR_8814B(v)) + +#define BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B 0 +#define BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B 0xffff +#define BIT_FWFF_PKT_WRITE_ADDR_8814B(x) \ + (((x) & BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B) \ + << BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B) +#define BITS_FWFF_PKT_WRITE_ADDR_8814B \ + (BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B \ + << BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B) +#define BIT_CLEAR_FWFF_PKT_WRITE_ADDR_8814B(x) \ + ((x) & (~BITS_FWFF_PKT_WRITE_ADDR_8814B)) +#define BIT_GET_FWFF_PKT_WRITE_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B) & \ + BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B) +#define BIT_SET_FWFF_PKT_WRITE_ADDR_8814B(x, v) \ + (BIT_CLEAR_FWFF_PKT_WRITE_ADDR_8814B(x) | \ + BIT_FWFF_PKT_WRITE_ADDR_8814B(v)) + +/* 2 REG_FWFF_PKT_INFO2_8814B */ + +#define BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B 0 +#define BIT_MASK_FWFF_PKT_QUEUED_V1_8814B 0xffff +#define BIT_FWFF_PKT_QUEUED_V1_8814B(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_V1_8814B) \ + << BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B) +#define BITS_FWFF_PKT_QUEUED_V1_8814B \ + (BIT_MASK_FWFF_PKT_QUEUED_V1_8814B \ + << BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B) +#define BIT_CLEAR_FWFF_PKT_QUEUED_V1_8814B(x) \ + ((x) & (~BITS_FWFF_PKT_QUEUED_V1_8814B)) +#define BIT_GET_FWFF_PKT_QUEUED_V1_8814B(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B) & \ + BIT_MASK_FWFF_PKT_QUEUED_V1_8814B) +#define BIT_SET_FWFF_PKT_QUEUED_V1_8814B(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_V1_8814B(x) | \ + BIT_FWFF_PKT_QUEUED_V1_8814B(v)) + +/* 2 REG_RXPKTNUM_8814B */ + +#define BIT_SHIFT_PKT_NUM_WOL_V1_8814B 16 +#define BIT_MASK_PKT_NUM_WOL_V1_8814B 0xffff +#define BIT_PKT_NUM_WOL_V1_8814B(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_V1_8814B) \ + << BIT_SHIFT_PKT_NUM_WOL_V1_8814B) +#define BITS_PKT_NUM_WOL_V1_8814B \ + (BIT_MASK_PKT_NUM_WOL_V1_8814B << BIT_SHIFT_PKT_NUM_WOL_V1_8814B) +#define BIT_CLEAR_PKT_NUM_WOL_V1_8814B(x) ((x) & (~BITS_PKT_NUM_WOL_V1_8814B)) +#define BIT_GET_PKT_NUM_WOL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_V1_8814B) & \ + BIT_MASK_PKT_NUM_WOL_V1_8814B) +#define BIT_SET_PKT_NUM_WOL_V1_8814B(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_V1_8814B(x) | BIT_PKT_NUM_WOL_V1_8814B(v)) + +#define BIT_SHIFT_RXPKT_NUM_V1_8814B 0 +#define BIT_MASK_RXPKT_NUM_V1_8814B 0xffff +#define BIT_RXPKT_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_RXPKT_NUM_V1_8814B) << BIT_SHIFT_RXPKT_NUM_V1_8814B) +#define BITS_RXPKT_NUM_V1_8814B \ + (BIT_MASK_RXPKT_NUM_V1_8814B << BIT_SHIFT_RXPKT_NUM_V1_8814B) +#define BIT_CLEAR_RXPKT_NUM_V1_8814B(x) ((x) & (~BITS_RXPKT_NUM_V1_8814B)) +#define BIT_GET_RXPKT_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_V1_8814B) & BIT_MASK_RXPKT_NUM_V1_8814B) +#define BIT_SET_RXPKT_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_RXPKT_NUM_V1_8814B(x) | BIT_RXPKT_NUM_V1_8814B(v)) + +/* 2 REG_RXPKTNUM_TH_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_RXPKT_NUM_TH_8814B 0 +#define BIT_MASK_RXPKT_NUM_TH_8814B 0xff +#define BIT_RXPKT_NUM_TH_8814B(x) \ + (((x) & BIT_MASK_RXPKT_NUM_TH_8814B) << BIT_SHIFT_RXPKT_NUM_TH_8814B) +#define BITS_RXPKT_NUM_TH_8814B \ + (BIT_MASK_RXPKT_NUM_TH_8814B << BIT_SHIFT_RXPKT_NUM_TH_8814B) +#define BIT_CLEAR_RXPKT_NUM_TH_8814B(x) ((x) & (~BITS_RXPKT_NUM_TH_8814B)) +#define BIT_GET_RXPKT_NUM_TH_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_TH_8814B) & BIT_MASK_RXPKT_NUM_TH_8814B) +#define BIT_SET_RXPKT_NUM_TH_8814B(x, v) \ + (BIT_CLEAR_RXPKT_NUM_TH_8814B(x) | BIT_RXPKT_NUM_TH_8814B(v)) -#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8814B 0 -#define BIT_MASK_FWFF_PKT_STR_ADDR_8814B 0xffff -#define BIT_FWFF_PKT_STR_ADDR_8814B(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8814B) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8814B) -#define BIT_GET_FWFF_PKT_STR_ADDR_8814B(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8814B) & BIT_MASK_FWFF_PKT_STR_ADDR_8814B) +/* 2 REG_FW_UPD_RXDES_RDPTR_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B 0 +#define BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B 0x3ffff +#define BIT_FW_UPD_RXDES_RD_PTR_8814B(x) \ + (((x) & BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B) \ + << BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B) +#define BITS_FW_UPD_RXDES_RD_PTR_8814B \ + (BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B \ + << BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B) +#define BIT_CLEAR_FW_UPD_RXDES_RD_PTR_8814B(x) \ + ((x) & (~BITS_FW_UPD_RXDES_RD_PTR_8814B)) +#define BIT_GET_FW_UPD_RXDES_RD_PTR_8814B(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B) & \ + BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B) +#define BIT_SET_FW_UPD_RXDES_RD_PTR_8814B(x, v) \ + (BIT_CLEAR_FW_UPD_RXDES_RD_PTR_8814B(x) | \ + BIT_FW_UPD_RXDES_RD_PTR_8814B(v)) /* 2 REG_DDMA_CH0SA_8814B */ #define BIT_SHIFT_DDMACH0_SA_8814B 0 #define BIT_MASK_DDMACH0_SA_8814B 0xffffffffL -#define BIT_DDMACH0_SA_8814B(x) (((x) & BIT_MASK_DDMACH0_SA_8814B) << BIT_SHIFT_DDMACH0_SA_8814B) -#define BIT_GET_DDMACH0_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8814B) & BIT_MASK_DDMACH0_SA_8814B) - - +#define BIT_DDMACH0_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH0_SA_8814B) << BIT_SHIFT_DDMACH0_SA_8814B) +#define BITS_DDMACH0_SA_8814B \ + (BIT_MASK_DDMACH0_SA_8814B << BIT_SHIFT_DDMACH0_SA_8814B) +#define BIT_CLEAR_DDMACH0_SA_8814B(x) ((x) & (~BITS_DDMACH0_SA_8814B)) +#define BIT_GET_DDMACH0_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA_8814B) & BIT_MASK_DDMACH0_SA_8814B) +#define BIT_SET_DDMACH0_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH0_SA_8814B(x) | BIT_DDMACH0_SA_8814B(v)) /* 2 REG_DDMA_CH0DA_8814B */ #define BIT_SHIFT_DDMACH0_DA_8814B 0 #define BIT_MASK_DDMACH0_DA_8814B 0xffffffffL -#define BIT_DDMACH0_DA_8814B(x) (((x) & BIT_MASK_DDMACH0_DA_8814B) << BIT_SHIFT_DDMACH0_DA_8814B) -#define BIT_GET_DDMACH0_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8814B) & BIT_MASK_DDMACH0_DA_8814B) - - +#define BIT_DDMACH0_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH0_DA_8814B) << BIT_SHIFT_DDMACH0_DA_8814B) +#define BITS_DDMACH0_DA_8814B \ + (BIT_MASK_DDMACH0_DA_8814B << BIT_SHIFT_DDMACH0_DA_8814B) +#define BIT_CLEAR_DDMACH0_DA_8814B(x) ((x) & (~BITS_DDMACH0_DA_8814B)) +#define BIT_GET_DDMACH0_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA_8814B) & BIT_MASK_DDMACH0_DA_8814B) +#define BIT_SET_DDMACH0_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH0_DA_8814B(x) | BIT_DDMACH0_DA_8814B(v)) /* 2 REG_DDMA_CH0CTRL_8814B */ #define BIT_DDMACH0_OWN_8814B BIT(31) +#define BIT_DDMACH0_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH0_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH0_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH0_CHKSUM_STS_8814B BIT(27) @@ -4059,31 +8155,47 @@ #define BIT_SHIFT_DDMACH0_DLEN_8814B 0 #define BIT_MASK_DDMACH0_DLEN_8814B 0x3ffff -#define BIT_DDMACH0_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH0_DLEN_8814B) << BIT_SHIFT_DDMACH0_DLEN_8814B) -#define BIT_GET_DDMACH0_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8814B) & BIT_MASK_DDMACH0_DLEN_8814B) - - +#define BIT_DDMACH0_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN_8814B) << BIT_SHIFT_DDMACH0_DLEN_8814B) +#define BITS_DDMACH0_DLEN_8814B \ + (BIT_MASK_DDMACH0_DLEN_8814B << BIT_SHIFT_DDMACH0_DLEN_8814B) +#define BIT_CLEAR_DDMACH0_DLEN_8814B(x) ((x) & (~BITS_DDMACH0_DLEN_8814B)) +#define BIT_GET_DDMACH0_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN_8814B) & BIT_MASK_DDMACH0_DLEN_8814B) +#define BIT_SET_DDMACH0_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN_8814B(x) | BIT_DDMACH0_DLEN_8814B(v)) /* 2 REG_DDMA_CH1SA_8814B */ #define BIT_SHIFT_DDMACH1_SA_8814B 0 #define BIT_MASK_DDMACH1_SA_8814B 0xffffffffL -#define BIT_DDMACH1_SA_8814B(x) (((x) & BIT_MASK_DDMACH1_SA_8814B) << BIT_SHIFT_DDMACH1_SA_8814B) -#define BIT_GET_DDMACH1_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8814B) & BIT_MASK_DDMACH1_SA_8814B) - - +#define BIT_DDMACH1_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH1_SA_8814B) << BIT_SHIFT_DDMACH1_SA_8814B) +#define BITS_DDMACH1_SA_8814B \ + (BIT_MASK_DDMACH1_SA_8814B << BIT_SHIFT_DDMACH1_SA_8814B) +#define BIT_CLEAR_DDMACH1_SA_8814B(x) ((x) & (~BITS_DDMACH1_SA_8814B)) +#define BIT_GET_DDMACH1_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA_8814B) & BIT_MASK_DDMACH1_SA_8814B) +#define BIT_SET_DDMACH1_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH1_SA_8814B(x) | BIT_DDMACH1_SA_8814B(v)) /* 2 REG_DDMA_CH1DA_8814B */ #define BIT_SHIFT_DDMACH1_DA_8814B 0 #define BIT_MASK_DDMACH1_DA_8814B 0xffffffffL -#define BIT_DDMACH1_DA_8814B(x) (((x) & BIT_MASK_DDMACH1_DA_8814B) << BIT_SHIFT_DDMACH1_DA_8814B) -#define BIT_GET_DDMACH1_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8814B) & BIT_MASK_DDMACH1_DA_8814B) - - +#define BIT_DDMACH1_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH1_DA_8814B) << BIT_SHIFT_DDMACH1_DA_8814B) +#define BITS_DDMACH1_DA_8814B \ + (BIT_MASK_DDMACH1_DA_8814B << BIT_SHIFT_DDMACH1_DA_8814B) +#define BIT_CLEAR_DDMACH1_DA_8814B(x) ((x) & (~BITS_DDMACH1_DA_8814B)) +#define BIT_GET_DDMACH1_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA_8814B) & BIT_MASK_DDMACH1_DA_8814B) +#define BIT_SET_DDMACH1_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH1_DA_8814B(x) | BIT_DDMACH1_DA_8814B(v)) /* 2 REG_DDMA_CH1CTRL_8814B */ #define BIT_DDMACH1_OWN_8814B BIT(31) +#define BIT_DDMACH1_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH1_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH1_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH1_CHKSUM_STS_8814B BIT(27) @@ -4093,31 +8205,47 @@ #define BIT_SHIFT_DDMACH1_DLEN_8814B 0 #define BIT_MASK_DDMACH1_DLEN_8814B 0x3ffff -#define BIT_DDMACH1_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH1_DLEN_8814B) << BIT_SHIFT_DDMACH1_DLEN_8814B) -#define BIT_GET_DDMACH1_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8814B) & BIT_MASK_DDMACH1_DLEN_8814B) - - +#define BIT_DDMACH1_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN_8814B) << BIT_SHIFT_DDMACH1_DLEN_8814B) +#define BITS_DDMACH1_DLEN_8814B \ + (BIT_MASK_DDMACH1_DLEN_8814B << BIT_SHIFT_DDMACH1_DLEN_8814B) +#define BIT_CLEAR_DDMACH1_DLEN_8814B(x) ((x) & (~BITS_DDMACH1_DLEN_8814B)) +#define BIT_GET_DDMACH1_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN_8814B) & BIT_MASK_DDMACH1_DLEN_8814B) +#define BIT_SET_DDMACH1_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN_8814B(x) | BIT_DDMACH1_DLEN_8814B(v)) /* 2 REG_DDMA_CH2SA_8814B */ #define BIT_SHIFT_DDMACH2_SA_8814B 0 #define BIT_MASK_DDMACH2_SA_8814B 0xffffffffL -#define BIT_DDMACH2_SA_8814B(x) (((x) & BIT_MASK_DDMACH2_SA_8814B) << BIT_SHIFT_DDMACH2_SA_8814B) -#define BIT_GET_DDMACH2_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8814B) & BIT_MASK_DDMACH2_SA_8814B) - - +#define BIT_DDMACH2_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH2_SA_8814B) << BIT_SHIFT_DDMACH2_SA_8814B) +#define BITS_DDMACH2_SA_8814B \ + (BIT_MASK_DDMACH2_SA_8814B << BIT_SHIFT_DDMACH2_SA_8814B) +#define BIT_CLEAR_DDMACH2_SA_8814B(x) ((x) & (~BITS_DDMACH2_SA_8814B)) +#define BIT_GET_DDMACH2_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA_8814B) & BIT_MASK_DDMACH2_SA_8814B) +#define BIT_SET_DDMACH2_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH2_SA_8814B(x) | BIT_DDMACH2_SA_8814B(v)) /* 2 REG_DDMA_CH2DA_8814B */ #define BIT_SHIFT_DDMACH2_DA_8814B 0 #define BIT_MASK_DDMACH2_DA_8814B 0xffffffffL -#define BIT_DDMACH2_DA_8814B(x) (((x) & BIT_MASK_DDMACH2_DA_8814B) << BIT_SHIFT_DDMACH2_DA_8814B) -#define BIT_GET_DDMACH2_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8814B) & BIT_MASK_DDMACH2_DA_8814B) - - +#define BIT_DDMACH2_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH2_DA_8814B) << BIT_SHIFT_DDMACH2_DA_8814B) +#define BITS_DDMACH2_DA_8814B \ + (BIT_MASK_DDMACH2_DA_8814B << BIT_SHIFT_DDMACH2_DA_8814B) +#define BIT_CLEAR_DDMACH2_DA_8814B(x) ((x) & (~BITS_DDMACH2_DA_8814B)) +#define BIT_GET_DDMACH2_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA_8814B) & BIT_MASK_DDMACH2_DA_8814B) +#define BIT_SET_DDMACH2_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH2_DA_8814B(x) | BIT_DDMACH2_DA_8814B(v)) /* 2 REG_DDMA_CH2CTRL_8814B */ #define BIT_DDMACH2_OWN_8814B BIT(31) +#define BIT_DDMACH2_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH2_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH2_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH2_CHKSUM_STS_8814B BIT(27) @@ -4127,31 +8255,47 @@ #define BIT_SHIFT_DDMACH2_DLEN_8814B 0 #define BIT_MASK_DDMACH2_DLEN_8814B 0x3ffff -#define BIT_DDMACH2_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH2_DLEN_8814B) << BIT_SHIFT_DDMACH2_DLEN_8814B) -#define BIT_GET_DDMACH2_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8814B) & BIT_MASK_DDMACH2_DLEN_8814B) - - +#define BIT_DDMACH2_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN_8814B) << BIT_SHIFT_DDMACH2_DLEN_8814B) +#define BITS_DDMACH2_DLEN_8814B \ + (BIT_MASK_DDMACH2_DLEN_8814B << BIT_SHIFT_DDMACH2_DLEN_8814B) +#define BIT_CLEAR_DDMACH2_DLEN_8814B(x) ((x) & (~BITS_DDMACH2_DLEN_8814B)) +#define BIT_GET_DDMACH2_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN_8814B) & BIT_MASK_DDMACH2_DLEN_8814B) +#define BIT_SET_DDMACH2_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN_8814B(x) | BIT_DDMACH2_DLEN_8814B(v)) /* 2 REG_DDMA_CH3SA_8814B */ #define BIT_SHIFT_DDMACH3_SA_8814B 0 #define BIT_MASK_DDMACH3_SA_8814B 0xffffffffL -#define BIT_DDMACH3_SA_8814B(x) (((x) & BIT_MASK_DDMACH3_SA_8814B) << BIT_SHIFT_DDMACH3_SA_8814B) -#define BIT_GET_DDMACH3_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8814B) & BIT_MASK_DDMACH3_SA_8814B) - - +#define BIT_DDMACH3_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH3_SA_8814B) << BIT_SHIFT_DDMACH3_SA_8814B) +#define BITS_DDMACH3_SA_8814B \ + (BIT_MASK_DDMACH3_SA_8814B << BIT_SHIFT_DDMACH3_SA_8814B) +#define BIT_CLEAR_DDMACH3_SA_8814B(x) ((x) & (~BITS_DDMACH3_SA_8814B)) +#define BIT_GET_DDMACH3_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA_8814B) & BIT_MASK_DDMACH3_SA_8814B) +#define BIT_SET_DDMACH3_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH3_SA_8814B(x) | BIT_DDMACH3_SA_8814B(v)) /* 2 REG_DDMA_CH3DA_8814B */ #define BIT_SHIFT_DDMACH3_DA_8814B 0 #define BIT_MASK_DDMACH3_DA_8814B 0xffffffffL -#define BIT_DDMACH3_DA_8814B(x) (((x) & BIT_MASK_DDMACH3_DA_8814B) << BIT_SHIFT_DDMACH3_DA_8814B) -#define BIT_GET_DDMACH3_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8814B) & BIT_MASK_DDMACH3_DA_8814B) - - +#define BIT_DDMACH3_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH3_DA_8814B) << BIT_SHIFT_DDMACH3_DA_8814B) +#define BITS_DDMACH3_DA_8814B \ + (BIT_MASK_DDMACH3_DA_8814B << BIT_SHIFT_DDMACH3_DA_8814B) +#define BIT_CLEAR_DDMACH3_DA_8814B(x) ((x) & (~BITS_DDMACH3_DA_8814B)) +#define BIT_GET_DDMACH3_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA_8814B) & BIT_MASK_DDMACH3_DA_8814B) +#define BIT_SET_DDMACH3_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH3_DA_8814B(x) | BIT_DDMACH3_DA_8814B(v)) /* 2 REG_DDMA_CH3CTRL_8814B */ #define BIT_DDMACH3_OWN_8814B BIT(31) +#define BIT_DDMACH3_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH3_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH3_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH3_CHKSUM_STS_8814B BIT(27) @@ -4161,31 +8305,47 @@ #define BIT_SHIFT_DDMACH3_DLEN_8814B 0 #define BIT_MASK_DDMACH3_DLEN_8814B 0x3ffff -#define BIT_DDMACH3_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH3_DLEN_8814B) << BIT_SHIFT_DDMACH3_DLEN_8814B) -#define BIT_GET_DDMACH3_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8814B) & BIT_MASK_DDMACH3_DLEN_8814B) - - +#define BIT_DDMACH3_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN_8814B) << BIT_SHIFT_DDMACH3_DLEN_8814B) +#define BITS_DDMACH3_DLEN_8814B \ + (BIT_MASK_DDMACH3_DLEN_8814B << BIT_SHIFT_DDMACH3_DLEN_8814B) +#define BIT_CLEAR_DDMACH3_DLEN_8814B(x) ((x) & (~BITS_DDMACH3_DLEN_8814B)) +#define BIT_GET_DDMACH3_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN_8814B) & BIT_MASK_DDMACH3_DLEN_8814B) +#define BIT_SET_DDMACH3_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN_8814B(x) | BIT_DDMACH3_DLEN_8814B(v)) /* 2 REG_DDMA_CH4SA_8814B */ #define BIT_SHIFT_DDMACH4_SA_8814B 0 #define BIT_MASK_DDMACH4_SA_8814B 0xffffffffL -#define BIT_DDMACH4_SA_8814B(x) (((x) & BIT_MASK_DDMACH4_SA_8814B) << BIT_SHIFT_DDMACH4_SA_8814B) -#define BIT_GET_DDMACH4_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8814B) & BIT_MASK_DDMACH4_SA_8814B) - - +#define BIT_DDMACH4_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH4_SA_8814B) << BIT_SHIFT_DDMACH4_SA_8814B) +#define BITS_DDMACH4_SA_8814B \ + (BIT_MASK_DDMACH4_SA_8814B << BIT_SHIFT_DDMACH4_SA_8814B) +#define BIT_CLEAR_DDMACH4_SA_8814B(x) ((x) & (~BITS_DDMACH4_SA_8814B)) +#define BIT_GET_DDMACH4_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA_8814B) & BIT_MASK_DDMACH4_SA_8814B) +#define BIT_SET_DDMACH4_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH4_SA_8814B(x) | BIT_DDMACH4_SA_8814B(v)) /* 2 REG_DDMA_CH4DA_8814B */ #define BIT_SHIFT_DDMACH4_DA_8814B 0 #define BIT_MASK_DDMACH4_DA_8814B 0xffffffffL -#define BIT_DDMACH4_DA_8814B(x) (((x) & BIT_MASK_DDMACH4_DA_8814B) << BIT_SHIFT_DDMACH4_DA_8814B) -#define BIT_GET_DDMACH4_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8814B) & BIT_MASK_DDMACH4_DA_8814B) - - +#define BIT_DDMACH4_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH4_DA_8814B) << BIT_SHIFT_DDMACH4_DA_8814B) +#define BITS_DDMACH4_DA_8814B \ + (BIT_MASK_DDMACH4_DA_8814B << BIT_SHIFT_DDMACH4_DA_8814B) +#define BIT_CLEAR_DDMACH4_DA_8814B(x) ((x) & (~BITS_DDMACH4_DA_8814B)) +#define BIT_GET_DDMACH4_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA_8814B) & BIT_MASK_DDMACH4_DA_8814B) +#define BIT_SET_DDMACH4_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH4_DA_8814B(x) | BIT_DDMACH4_DA_8814B(v)) /* 2 REG_DDMA_CH4CTRL_8814B */ #define BIT_DDMACH4_OWN_8814B BIT(31) +#define BIT_DDMACH4_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH4_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH4_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH4_CHKSUM_STS_8814B BIT(27) @@ -4195,31 +8355,47 @@ #define BIT_SHIFT_DDMACH4_DLEN_8814B 0 #define BIT_MASK_DDMACH4_DLEN_8814B 0x3ffff -#define BIT_DDMACH4_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH4_DLEN_8814B) << BIT_SHIFT_DDMACH4_DLEN_8814B) -#define BIT_GET_DDMACH4_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8814B) & BIT_MASK_DDMACH4_DLEN_8814B) - - +#define BIT_DDMACH4_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN_8814B) << BIT_SHIFT_DDMACH4_DLEN_8814B) +#define BITS_DDMACH4_DLEN_8814B \ + (BIT_MASK_DDMACH4_DLEN_8814B << BIT_SHIFT_DDMACH4_DLEN_8814B) +#define BIT_CLEAR_DDMACH4_DLEN_8814B(x) ((x) & (~BITS_DDMACH4_DLEN_8814B)) +#define BIT_GET_DDMACH4_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN_8814B) & BIT_MASK_DDMACH4_DLEN_8814B) +#define BIT_SET_DDMACH4_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN_8814B(x) | BIT_DDMACH4_DLEN_8814B(v)) /* 2 REG_DDMA_CH5SA_8814B */ #define BIT_SHIFT_DDMACH5_SA_8814B 0 #define BIT_MASK_DDMACH5_SA_8814B 0xffffffffL -#define BIT_DDMACH5_SA_8814B(x) (((x) & BIT_MASK_DDMACH5_SA_8814B) << BIT_SHIFT_DDMACH5_SA_8814B) -#define BIT_GET_DDMACH5_SA_8814B(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8814B) & BIT_MASK_DDMACH5_SA_8814B) - - +#define BIT_DDMACH5_SA_8814B(x) \ + (((x) & BIT_MASK_DDMACH5_SA_8814B) << BIT_SHIFT_DDMACH5_SA_8814B) +#define BITS_DDMACH5_SA_8814B \ + (BIT_MASK_DDMACH5_SA_8814B << BIT_SHIFT_DDMACH5_SA_8814B) +#define BIT_CLEAR_DDMACH5_SA_8814B(x) ((x) & (~BITS_DDMACH5_SA_8814B)) +#define BIT_GET_DDMACH5_SA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA_8814B) & BIT_MASK_DDMACH5_SA_8814B) +#define BIT_SET_DDMACH5_SA_8814B(x, v) \ + (BIT_CLEAR_DDMACH5_SA_8814B(x) | BIT_DDMACH5_SA_8814B(v)) /* 2 REG_DDMA_CH5DA_8814B */ #define BIT_SHIFT_DDMACH5_DA_8814B 0 #define BIT_MASK_DDMACH5_DA_8814B 0xffffffffL -#define BIT_DDMACH5_DA_8814B(x) (((x) & BIT_MASK_DDMACH5_DA_8814B) << BIT_SHIFT_DDMACH5_DA_8814B) -#define BIT_GET_DDMACH5_DA_8814B(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8814B) & BIT_MASK_DDMACH5_DA_8814B) - - +#define BIT_DDMACH5_DA_8814B(x) \ + (((x) & BIT_MASK_DDMACH5_DA_8814B) << BIT_SHIFT_DDMACH5_DA_8814B) +#define BITS_DDMACH5_DA_8814B \ + (BIT_MASK_DDMACH5_DA_8814B << BIT_SHIFT_DDMACH5_DA_8814B) +#define BIT_CLEAR_DDMACH5_DA_8814B(x) ((x) & (~BITS_DDMACH5_DA_8814B)) +#define BIT_GET_DDMACH5_DA_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA_8814B) & BIT_MASK_DDMACH5_DA_8814B) +#define BIT_SET_DDMACH5_DA_8814B(x, v) \ + (BIT_CLEAR_DDMACH5_DA_8814B(x) | BIT_DDMACH5_DA_8814B(v)) /* 2 REG_DDMA_CH5CTRL_8814B */ #define BIT_DDMACH5_OWN_8814B BIT(31) +#define BIT_DDMACH5_IDMEM_ERR_8814B BIT(30) #define BIT_DDMACH5_CHKSUM_EN_8814B BIT(29) #define BIT_DDMACH5_DA_W_DISABLE_8814B BIT(28) #define BIT_DDMACH5_CHKSUM_STS_8814B BIT(27) @@ -4229,10 +8405,15 @@ #define BIT_SHIFT_DDMACH5_DLEN_8814B 0 #define BIT_MASK_DDMACH5_DLEN_8814B 0x3ffff -#define BIT_DDMACH5_DLEN_8814B(x) (((x) & BIT_MASK_DDMACH5_DLEN_8814B) << BIT_SHIFT_DDMACH5_DLEN_8814B) -#define BIT_GET_DDMACH5_DLEN_8814B(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8814B) & BIT_MASK_DDMACH5_DLEN_8814B) - - +#define BIT_DDMACH5_DLEN_8814B(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN_8814B) << BIT_SHIFT_DDMACH5_DLEN_8814B) +#define BITS_DDMACH5_DLEN_8814B \ + (BIT_MASK_DDMACH5_DLEN_8814B << BIT_SHIFT_DDMACH5_DLEN_8814B) +#define BIT_CLEAR_DDMACH5_DLEN_8814B(x) ((x) & (~BITS_DDMACH5_DLEN_8814B)) +#define BIT_GET_DDMACH5_DLEN_8814B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN_8814B) & BIT_MASK_DDMACH5_DLEN_8814B) +#define BIT_SET_DDMACH5_DLEN_8814B(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN_8814B(x) | BIT_DDMACH5_DLEN_8814B(v)) /* 2 REG_DDMA_INT_MSK_8814B */ #define BIT_DDMACH5_MSK_8814B BIT(5) @@ -4254,10 +8435,15 @@ #define BIT_SHIFT_IDDMA0_CHKSUM_8814B 0 #define BIT_MASK_IDDMA0_CHKSUM_8814B 0xffff -#define BIT_IDDMA0_CHKSUM_8814B(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8814B) << BIT_SHIFT_IDDMA0_CHKSUM_8814B) -#define BIT_GET_IDDMA0_CHKSUM_8814B(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8814B) & BIT_MASK_IDDMA0_CHKSUM_8814B) - - +#define BIT_IDDMA0_CHKSUM_8814B(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM_8814B) << BIT_SHIFT_IDDMA0_CHKSUM_8814B) +#define BITS_IDDMA0_CHKSUM_8814B \ + (BIT_MASK_IDDMA0_CHKSUM_8814B << BIT_SHIFT_IDDMA0_CHKSUM_8814B) +#define BIT_CLEAR_IDDMA0_CHKSUM_8814B(x) ((x) & (~BITS_IDDMA0_CHKSUM_8814B)) +#define BIT_GET_IDDMA0_CHKSUM_8814B(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8814B) & BIT_MASK_IDDMA0_CHKSUM_8814B) +#define BIT_SET_IDDMA0_CHKSUM_8814B(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM_8814B(x) | BIT_IDDMA0_CHKSUM_8814B(v)) /* 2 REG_DDMA_MONITOR_8814B */ #define BIT_IDDMA0_PERMU_UNDERFLOW_8814B BIT(14) @@ -4270,6 +8456,970 @@ #define BIT_CH1_ERR_8814B BIT(1) #define BIT_CH0_ERR_8814B BIT(0) +/* 2 REG_DMA_RQPN_INFO_0_8814B */ + +#define BIT_SHIFT_CH0_AVAL_PG_8814B 16 +#define BIT_MASK_CH0_AVAL_PG_8814B 0xfff +#define BIT_CH0_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH0_AVAL_PG_8814B) << BIT_SHIFT_CH0_AVAL_PG_8814B) +#define BITS_CH0_AVAL_PG_8814B \ + (BIT_MASK_CH0_AVAL_PG_8814B << BIT_SHIFT_CH0_AVAL_PG_8814B) +#define BIT_CLEAR_CH0_AVAL_PG_8814B(x) ((x) & (~BITS_CH0_AVAL_PG_8814B)) +#define BIT_GET_CH0_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH0_AVAL_PG_8814B) & BIT_MASK_CH0_AVAL_PG_8814B) +#define BIT_SET_CH0_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH0_AVAL_PG_8814B(x) | BIT_CH0_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH0_RSVD_PG_8814B 0 +#define BIT_MASK_CH0_RSVD_PG_8814B 0xfff +#define BIT_CH0_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH0_RSVD_PG_8814B) << BIT_SHIFT_CH0_RSVD_PG_8814B) +#define BITS_CH0_RSVD_PG_8814B \ + (BIT_MASK_CH0_RSVD_PG_8814B << BIT_SHIFT_CH0_RSVD_PG_8814B) +#define BIT_CLEAR_CH0_RSVD_PG_8814B(x) ((x) & (~BITS_CH0_RSVD_PG_8814B)) +#define BIT_GET_CH0_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH0_RSVD_PG_8814B) & BIT_MASK_CH0_RSVD_PG_8814B) +#define BIT_SET_CH0_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH0_RSVD_PG_8814B(x) | BIT_CH0_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_1_8814B */ + +#define BIT_SHIFT_CH1_AVAL_PG_8814B 16 +#define BIT_MASK_CH1_AVAL_PG_8814B 0xfff +#define BIT_CH1_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH1_AVAL_PG_8814B) << BIT_SHIFT_CH1_AVAL_PG_8814B) +#define BITS_CH1_AVAL_PG_8814B \ + (BIT_MASK_CH1_AVAL_PG_8814B << BIT_SHIFT_CH1_AVAL_PG_8814B) +#define BIT_CLEAR_CH1_AVAL_PG_8814B(x) ((x) & (~BITS_CH1_AVAL_PG_8814B)) +#define BIT_GET_CH1_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH1_AVAL_PG_8814B) & BIT_MASK_CH1_AVAL_PG_8814B) +#define BIT_SET_CH1_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH1_AVAL_PG_8814B(x) | BIT_CH1_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH1_RSVD_PG_8814B 0 +#define BIT_MASK_CH1_RSVD_PG_8814B 0xfff +#define BIT_CH1_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH1_RSVD_PG_8814B) << BIT_SHIFT_CH1_RSVD_PG_8814B) +#define BITS_CH1_RSVD_PG_8814B \ + (BIT_MASK_CH1_RSVD_PG_8814B << BIT_SHIFT_CH1_RSVD_PG_8814B) +#define BIT_CLEAR_CH1_RSVD_PG_8814B(x) ((x) & (~BITS_CH1_RSVD_PG_8814B)) +#define BIT_GET_CH1_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH1_RSVD_PG_8814B) & BIT_MASK_CH1_RSVD_PG_8814B) +#define BIT_SET_CH1_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH1_RSVD_PG_8814B(x) | BIT_CH1_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_2_8814B */ + +#define BIT_SHIFT_CH2_AVAL_PG_8814B 16 +#define BIT_MASK_CH2_AVAL_PG_8814B 0xfff +#define BIT_CH2_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH2_AVAL_PG_8814B) << BIT_SHIFT_CH2_AVAL_PG_8814B) +#define BITS_CH2_AVAL_PG_8814B \ + (BIT_MASK_CH2_AVAL_PG_8814B << BIT_SHIFT_CH2_AVAL_PG_8814B) +#define BIT_CLEAR_CH2_AVAL_PG_8814B(x) ((x) & (~BITS_CH2_AVAL_PG_8814B)) +#define BIT_GET_CH2_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH2_AVAL_PG_8814B) & BIT_MASK_CH2_AVAL_PG_8814B) +#define BIT_SET_CH2_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH2_AVAL_PG_8814B(x) | BIT_CH2_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH2_RSVD_PG_8814B 0 +#define BIT_MASK_CH2_RSVD_PG_8814B 0xfff +#define BIT_CH2_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH2_RSVD_PG_8814B) << BIT_SHIFT_CH2_RSVD_PG_8814B) +#define BITS_CH2_RSVD_PG_8814B \ + (BIT_MASK_CH2_RSVD_PG_8814B << BIT_SHIFT_CH2_RSVD_PG_8814B) +#define BIT_CLEAR_CH2_RSVD_PG_8814B(x) ((x) & (~BITS_CH2_RSVD_PG_8814B)) +#define BIT_GET_CH2_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH2_RSVD_PG_8814B) & BIT_MASK_CH2_RSVD_PG_8814B) +#define BIT_SET_CH2_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH2_RSVD_PG_8814B(x) | BIT_CH2_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_3_8814B */ + +#define BIT_SHIFT_CH3_AVAL_PG_8814B 16 +#define BIT_MASK_CH3_AVAL_PG_8814B 0xfff +#define BIT_CH3_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH3_AVAL_PG_8814B) << BIT_SHIFT_CH3_AVAL_PG_8814B) +#define BITS_CH3_AVAL_PG_8814B \ + (BIT_MASK_CH3_AVAL_PG_8814B << BIT_SHIFT_CH3_AVAL_PG_8814B) +#define BIT_CLEAR_CH3_AVAL_PG_8814B(x) ((x) & (~BITS_CH3_AVAL_PG_8814B)) +#define BIT_GET_CH3_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH3_AVAL_PG_8814B) & BIT_MASK_CH3_AVAL_PG_8814B) +#define BIT_SET_CH3_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH3_AVAL_PG_8814B(x) | BIT_CH3_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH3_RSVD_PG_8814B 0 +#define BIT_MASK_CH3_RSVD_PG_8814B 0xfff +#define BIT_CH3_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH3_RSVD_PG_8814B) << BIT_SHIFT_CH3_RSVD_PG_8814B) +#define BITS_CH3_RSVD_PG_8814B \ + (BIT_MASK_CH3_RSVD_PG_8814B << BIT_SHIFT_CH3_RSVD_PG_8814B) +#define BIT_CLEAR_CH3_RSVD_PG_8814B(x) ((x) & (~BITS_CH3_RSVD_PG_8814B)) +#define BIT_GET_CH3_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH3_RSVD_PG_8814B) & BIT_MASK_CH3_RSVD_PG_8814B) +#define BIT_SET_CH3_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH3_RSVD_PG_8814B(x) | BIT_CH3_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_4_8814B */ + +#define BIT_SHIFT_CH4_AVAL_PG_8814B 16 +#define BIT_MASK_CH4_AVAL_PG_8814B 0xfff +#define BIT_CH4_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH4_AVAL_PG_8814B) << BIT_SHIFT_CH4_AVAL_PG_8814B) +#define BITS_CH4_AVAL_PG_8814B \ + (BIT_MASK_CH4_AVAL_PG_8814B << BIT_SHIFT_CH4_AVAL_PG_8814B) +#define BIT_CLEAR_CH4_AVAL_PG_8814B(x) ((x) & (~BITS_CH4_AVAL_PG_8814B)) +#define BIT_GET_CH4_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH4_AVAL_PG_8814B) & BIT_MASK_CH4_AVAL_PG_8814B) +#define BIT_SET_CH4_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH4_AVAL_PG_8814B(x) | BIT_CH4_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH4_RSVD_PG_8814B 0 +#define BIT_MASK_CH4_RSVD_PG_8814B 0xfff +#define BIT_CH4_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH4_RSVD_PG_8814B) << BIT_SHIFT_CH4_RSVD_PG_8814B) +#define BITS_CH4_RSVD_PG_8814B \ + (BIT_MASK_CH4_RSVD_PG_8814B << BIT_SHIFT_CH4_RSVD_PG_8814B) +#define BIT_CLEAR_CH4_RSVD_PG_8814B(x) ((x) & (~BITS_CH4_RSVD_PG_8814B)) +#define BIT_GET_CH4_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH4_RSVD_PG_8814B) & BIT_MASK_CH4_RSVD_PG_8814B) +#define BIT_SET_CH4_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH4_RSVD_PG_8814B(x) | BIT_CH4_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_5_8814B */ + +#define BIT_SHIFT_CH5_AVAL_PG_8814B 16 +#define BIT_MASK_CH5_AVAL_PG_8814B 0xfff +#define BIT_CH5_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH5_AVAL_PG_8814B) << BIT_SHIFT_CH5_AVAL_PG_8814B) +#define BITS_CH5_AVAL_PG_8814B \ + (BIT_MASK_CH5_AVAL_PG_8814B << BIT_SHIFT_CH5_AVAL_PG_8814B) +#define BIT_CLEAR_CH5_AVAL_PG_8814B(x) ((x) & (~BITS_CH5_AVAL_PG_8814B)) +#define BIT_GET_CH5_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH5_AVAL_PG_8814B) & BIT_MASK_CH5_AVAL_PG_8814B) +#define BIT_SET_CH5_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH5_AVAL_PG_8814B(x) | BIT_CH5_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH5_RSVD_PG_8814B 0 +#define BIT_MASK_CH5_RSVD_PG_8814B 0xfff +#define BIT_CH5_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH5_RSVD_PG_8814B) << BIT_SHIFT_CH5_RSVD_PG_8814B) +#define BITS_CH5_RSVD_PG_8814B \ + (BIT_MASK_CH5_RSVD_PG_8814B << BIT_SHIFT_CH5_RSVD_PG_8814B) +#define BIT_CLEAR_CH5_RSVD_PG_8814B(x) ((x) & (~BITS_CH5_RSVD_PG_8814B)) +#define BIT_GET_CH5_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH5_RSVD_PG_8814B) & BIT_MASK_CH5_RSVD_PG_8814B) +#define BIT_SET_CH5_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH5_RSVD_PG_8814B(x) | BIT_CH5_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_6_8814B */ + +#define BIT_SHIFT_CH6_AVAL_PG_8814B 16 +#define BIT_MASK_CH6_AVAL_PG_8814B 0xfff +#define BIT_CH6_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH6_AVAL_PG_8814B) << BIT_SHIFT_CH6_AVAL_PG_8814B) +#define BITS_CH6_AVAL_PG_8814B \ + (BIT_MASK_CH6_AVAL_PG_8814B << BIT_SHIFT_CH6_AVAL_PG_8814B) +#define BIT_CLEAR_CH6_AVAL_PG_8814B(x) ((x) & (~BITS_CH6_AVAL_PG_8814B)) +#define BIT_GET_CH6_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH6_AVAL_PG_8814B) & BIT_MASK_CH6_AVAL_PG_8814B) +#define BIT_SET_CH6_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH6_AVAL_PG_8814B(x) | BIT_CH6_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH6_RSVD_PG_8814B 0 +#define BIT_MASK_CH6_RSVD_PG_8814B 0xfff +#define BIT_CH6_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH6_RSVD_PG_8814B) << BIT_SHIFT_CH6_RSVD_PG_8814B) +#define BITS_CH6_RSVD_PG_8814B \ + (BIT_MASK_CH6_RSVD_PG_8814B << BIT_SHIFT_CH6_RSVD_PG_8814B) +#define BIT_CLEAR_CH6_RSVD_PG_8814B(x) ((x) & (~BITS_CH6_RSVD_PG_8814B)) +#define BIT_GET_CH6_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH6_RSVD_PG_8814B) & BIT_MASK_CH6_RSVD_PG_8814B) +#define BIT_SET_CH6_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH6_RSVD_PG_8814B(x) | BIT_CH6_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_7_8814B */ + +#define BIT_SHIFT_CH7_AVAL_PG_8814B 16 +#define BIT_MASK_CH7_AVAL_PG_8814B 0xfff +#define BIT_CH7_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH7_AVAL_PG_8814B) << BIT_SHIFT_CH7_AVAL_PG_8814B) +#define BITS_CH7_AVAL_PG_8814B \ + (BIT_MASK_CH7_AVAL_PG_8814B << BIT_SHIFT_CH7_AVAL_PG_8814B) +#define BIT_CLEAR_CH7_AVAL_PG_8814B(x) ((x) & (~BITS_CH7_AVAL_PG_8814B)) +#define BIT_GET_CH7_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH7_AVAL_PG_8814B) & BIT_MASK_CH7_AVAL_PG_8814B) +#define BIT_SET_CH7_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH7_AVAL_PG_8814B(x) | BIT_CH7_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH7_RSVD_PG_8814B 0 +#define BIT_MASK_CH7_RSVD_PG_8814B 0xfff +#define BIT_CH7_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH7_RSVD_PG_8814B) << BIT_SHIFT_CH7_RSVD_PG_8814B) +#define BITS_CH7_RSVD_PG_8814B \ + (BIT_MASK_CH7_RSVD_PG_8814B << BIT_SHIFT_CH7_RSVD_PG_8814B) +#define BIT_CLEAR_CH7_RSVD_PG_8814B(x) ((x) & (~BITS_CH7_RSVD_PG_8814B)) +#define BIT_GET_CH7_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH7_RSVD_PG_8814B) & BIT_MASK_CH7_RSVD_PG_8814B) +#define BIT_SET_CH7_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH7_RSVD_PG_8814B(x) | BIT_CH7_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_8_8814B */ + +#define BIT_SHIFT_CH8_AVAL_PG_8814B 16 +#define BIT_MASK_CH8_AVAL_PG_8814B 0xfff +#define BIT_CH8_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH8_AVAL_PG_8814B) << BIT_SHIFT_CH8_AVAL_PG_8814B) +#define BITS_CH8_AVAL_PG_8814B \ + (BIT_MASK_CH8_AVAL_PG_8814B << BIT_SHIFT_CH8_AVAL_PG_8814B) +#define BIT_CLEAR_CH8_AVAL_PG_8814B(x) ((x) & (~BITS_CH8_AVAL_PG_8814B)) +#define BIT_GET_CH8_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH8_AVAL_PG_8814B) & BIT_MASK_CH8_AVAL_PG_8814B) +#define BIT_SET_CH8_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH8_AVAL_PG_8814B(x) | BIT_CH8_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH8_RSVD_PG_8814B 0 +#define BIT_MASK_CH8_RSVD_PG_8814B 0xfff +#define BIT_CH8_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH8_RSVD_PG_8814B) << BIT_SHIFT_CH8_RSVD_PG_8814B) +#define BITS_CH8_RSVD_PG_8814B \ + (BIT_MASK_CH8_RSVD_PG_8814B << BIT_SHIFT_CH8_RSVD_PG_8814B) +#define BIT_CLEAR_CH8_RSVD_PG_8814B(x) ((x) & (~BITS_CH8_RSVD_PG_8814B)) +#define BIT_GET_CH8_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH8_RSVD_PG_8814B) & BIT_MASK_CH8_RSVD_PG_8814B) +#define BIT_SET_CH8_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH8_RSVD_PG_8814B(x) | BIT_CH8_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_9_8814B */ + +#define BIT_SHIFT_CH9_AVAL_PG_8814B 16 +#define BIT_MASK_CH9_AVAL_PG_8814B 0xfff +#define BIT_CH9_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH9_AVAL_PG_8814B) << BIT_SHIFT_CH9_AVAL_PG_8814B) +#define BITS_CH9_AVAL_PG_8814B \ + (BIT_MASK_CH9_AVAL_PG_8814B << BIT_SHIFT_CH9_AVAL_PG_8814B) +#define BIT_CLEAR_CH9_AVAL_PG_8814B(x) ((x) & (~BITS_CH9_AVAL_PG_8814B)) +#define BIT_GET_CH9_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH9_AVAL_PG_8814B) & BIT_MASK_CH9_AVAL_PG_8814B) +#define BIT_SET_CH9_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH9_AVAL_PG_8814B(x) | BIT_CH9_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH9_RSVD_PG_8814B 0 +#define BIT_MASK_CH9_RSVD_PG_8814B 0xfff +#define BIT_CH9_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH9_RSVD_PG_8814B) << BIT_SHIFT_CH9_RSVD_PG_8814B) +#define BITS_CH9_RSVD_PG_8814B \ + (BIT_MASK_CH9_RSVD_PG_8814B << BIT_SHIFT_CH9_RSVD_PG_8814B) +#define BIT_CLEAR_CH9_RSVD_PG_8814B(x) ((x) & (~BITS_CH9_RSVD_PG_8814B)) +#define BIT_GET_CH9_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH9_RSVD_PG_8814B) & BIT_MASK_CH9_RSVD_PG_8814B) +#define BIT_SET_CH9_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH9_RSVD_PG_8814B(x) | BIT_CH9_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_10_8814B */ + +#define BIT_SHIFT_CH10_AVAL_PG_8814B 16 +#define BIT_MASK_CH10_AVAL_PG_8814B 0xfff +#define BIT_CH10_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH10_AVAL_PG_8814B) << BIT_SHIFT_CH10_AVAL_PG_8814B) +#define BITS_CH10_AVAL_PG_8814B \ + (BIT_MASK_CH10_AVAL_PG_8814B << BIT_SHIFT_CH10_AVAL_PG_8814B) +#define BIT_CLEAR_CH10_AVAL_PG_8814B(x) ((x) & (~BITS_CH10_AVAL_PG_8814B)) +#define BIT_GET_CH10_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH10_AVAL_PG_8814B) & BIT_MASK_CH10_AVAL_PG_8814B) +#define BIT_SET_CH10_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH10_AVAL_PG_8814B(x) | BIT_CH10_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH10_RSVD_PG_8814B 0 +#define BIT_MASK_CH10_RSVD_PG_8814B 0xfff +#define BIT_CH10_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH10_RSVD_PG_8814B) << BIT_SHIFT_CH10_RSVD_PG_8814B) +#define BITS_CH10_RSVD_PG_8814B \ + (BIT_MASK_CH10_RSVD_PG_8814B << BIT_SHIFT_CH10_RSVD_PG_8814B) +#define BIT_CLEAR_CH10_RSVD_PG_8814B(x) ((x) & (~BITS_CH10_RSVD_PG_8814B)) +#define BIT_GET_CH10_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH10_RSVD_PG_8814B) & BIT_MASK_CH10_RSVD_PG_8814B) +#define BIT_SET_CH10_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH10_RSVD_PG_8814B(x) | BIT_CH10_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_11_8814B */ + +#define BIT_SHIFT_CH11_AVAL_PG_8814B 16 +#define BIT_MASK_CH11_AVAL_PG_8814B 0xfff +#define BIT_CH11_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH11_AVAL_PG_8814B) << BIT_SHIFT_CH11_AVAL_PG_8814B) +#define BITS_CH11_AVAL_PG_8814B \ + (BIT_MASK_CH11_AVAL_PG_8814B << BIT_SHIFT_CH11_AVAL_PG_8814B) +#define BIT_CLEAR_CH11_AVAL_PG_8814B(x) ((x) & (~BITS_CH11_AVAL_PG_8814B)) +#define BIT_GET_CH11_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH11_AVAL_PG_8814B) & BIT_MASK_CH11_AVAL_PG_8814B) +#define BIT_SET_CH11_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH11_AVAL_PG_8814B(x) | BIT_CH11_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH11_RSVD_PG_8814B 0 +#define BIT_MASK_CH11_RSVD_PG_8814B 0xfff +#define BIT_CH11_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH11_RSVD_PG_8814B) << BIT_SHIFT_CH11_RSVD_PG_8814B) +#define BITS_CH11_RSVD_PG_8814B \ + (BIT_MASK_CH11_RSVD_PG_8814B << BIT_SHIFT_CH11_RSVD_PG_8814B) +#define BIT_CLEAR_CH11_RSVD_PG_8814B(x) ((x) & (~BITS_CH11_RSVD_PG_8814B)) +#define BIT_GET_CH11_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH11_RSVD_PG_8814B) & BIT_MASK_CH11_RSVD_PG_8814B) +#define BIT_SET_CH11_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH11_RSVD_PG_8814B(x) | BIT_CH11_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_12_8814B */ + +#define BIT_SHIFT_CH12_AVAL_PG_8814B 16 +#define BIT_MASK_CH12_AVAL_PG_8814B 0xfff +#define BIT_CH12_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH12_AVAL_PG_8814B) << BIT_SHIFT_CH12_AVAL_PG_8814B) +#define BITS_CH12_AVAL_PG_8814B \ + (BIT_MASK_CH12_AVAL_PG_8814B << BIT_SHIFT_CH12_AVAL_PG_8814B) +#define BIT_CLEAR_CH12_AVAL_PG_8814B(x) ((x) & (~BITS_CH12_AVAL_PG_8814B)) +#define BIT_GET_CH12_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH12_AVAL_PG_8814B) & BIT_MASK_CH12_AVAL_PG_8814B) +#define BIT_SET_CH12_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH12_AVAL_PG_8814B(x) | BIT_CH12_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH12_RSVD_PG_8814B 0 +#define BIT_MASK_CH12_RSVD_PG_8814B 0xfff +#define BIT_CH12_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH12_RSVD_PG_8814B) << BIT_SHIFT_CH12_RSVD_PG_8814B) +#define BITS_CH12_RSVD_PG_8814B \ + (BIT_MASK_CH12_RSVD_PG_8814B << BIT_SHIFT_CH12_RSVD_PG_8814B) +#define BIT_CLEAR_CH12_RSVD_PG_8814B(x) ((x) & (~BITS_CH12_RSVD_PG_8814B)) +#define BIT_GET_CH12_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH12_RSVD_PG_8814B) & BIT_MASK_CH12_RSVD_PG_8814B) +#define BIT_SET_CH12_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH12_RSVD_PG_8814B(x) | BIT_CH12_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_13_8814B */ + +#define BIT_SHIFT_CH13_AVAL_PG_8814B 16 +#define BIT_MASK_CH13_AVAL_PG_8814B 0xfff +#define BIT_CH13_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH13_AVAL_PG_8814B) << BIT_SHIFT_CH13_AVAL_PG_8814B) +#define BITS_CH13_AVAL_PG_8814B \ + (BIT_MASK_CH13_AVAL_PG_8814B << BIT_SHIFT_CH13_AVAL_PG_8814B) +#define BIT_CLEAR_CH13_AVAL_PG_8814B(x) ((x) & (~BITS_CH13_AVAL_PG_8814B)) +#define BIT_GET_CH13_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH13_AVAL_PG_8814B) & BIT_MASK_CH13_AVAL_PG_8814B) +#define BIT_SET_CH13_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH13_AVAL_PG_8814B(x) | BIT_CH13_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH13_RSVD_PG_8814B 0 +#define BIT_MASK_CH13_RSVD_PG_8814B 0xfff +#define BIT_CH13_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH13_RSVD_PG_8814B) << BIT_SHIFT_CH13_RSVD_PG_8814B) +#define BITS_CH13_RSVD_PG_8814B \ + (BIT_MASK_CH13_RSVD_PG_8814B << BIT_SHIFT_CH13_RSVD_PG_8814B) +#define BIT_CLEAR_CH13_RSVD_PG_8814B(x) ((x) & (~BITS_CH13_RSVD_PG_8814B)) +#define BIT_GET_CH13_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH13_RSVD_PG_8814B) & BIT_MASK_CH13_RSVD_PG_8814B) +#define BIT_SET_CH13_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH13_RSVD_PG_8814B(x) | BIT_CH13_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_14_8814B */ + +#define BIT_SHIFT_CH14_AVAL_PG_8814B 16 +#define BIT_MASK_CH14_AVAL_PG_8814B 0xfff +#define BIT_CH14_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH14_AVAL_PG_8814B) << BIT_SHIFT_CH14_AVAL_PG_8814B) +#define BITS_CH14_AVAL_PG_8814B \ + (BIT_MASK_CH14_AVAL_PG_8814B << BIT_SHIFT_CH14_AVAL_PG_8814B) +#define BIT_CLEAR_CH14_AVAL_PG_8814B(x) ((x) & (~BITS_CH14_AVAL_PG_8814B)) +#define BIT_GET_CH14_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH14_AVAL_PG_8814B) & BIT_MASK_CH14_AVAL_PG_8814B) +#define BIT_SET_CH14_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH14_AVAL_PG_8814B(x) | BIT_CH14_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH14_RSVD_PG_8814B 0 +#define BIT_MASK_CH14_RSVD_PG_8814B 0xfff +#define BIT_CH14_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH14_RSVD_PG_8814B) << BIT_SHIFT_CH14_RSVD_PG_8814B) +#define BITS_CH14_RSVD_PG_8814B \ + (BIT_MASK_CH14_RSVD_PG_8814B << BIT_SHIFT_CH14_RSVD_PG_8814B) +#define BIT_CLEAR_CH14_RSVD_PG_8814B(x) ((x) & (~BITS_CH14_RSVD_PG_8814B)) +#define BIT_GET_CH14_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH14_RSVD_PG_8814B) & BIT_MASK_CH14_RSVD_PG_8814B) +#define BIT_SET_CH14_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH14_RSVD_PG_8814B(x) | BIT_CH14_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_15_8814B */ + +#define BIT_SHIFT_CH15_AVAL_PG_8814B 16 +#define BIT_MASK_CH15_AVAL_PG_8814B 0xfff +#define BIT_CH15_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH15_AVAL_PG_8814B) << BIT_SHIFT_CH15_AVAL_PG_8814B) +#define BITS_CH15_AVAL_PG_8814B \ + (BIT_MASK_CH15_AVAL_PG_8814B << BIT_SHIFT_CH15_AVAL_PG_8814B) +#define BIT_CLEAR_CH15_AVAL_PG_8814B(x) ((x) & (~BITS_CH15_AVAL_PG_8814B)) +#define BIT_GET_CH15_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH15_AVAL_PG_8814B) & BIT_MASK_CH15_AVAL_PG_8814B) +#define BIT_SET_CH15_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH15_AVAL_PG_8814B(x) | BIT_CH15_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH15_RSVD_PG_8814B 0 +#define BIT_MASK_CH15_RSVD_PG_8814B 0xfff +#define BIT_CH15_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH15_RSVD_PG_8814B) << BIT_SHIFT_CH15_RSVD_PG_8814B) +#define BITS_CH15_RSVD_PG_8814B \ + (BIT_MASK_CH15_RSVD_PG_8814B << BIT_SHIFT_CH15_RSVD_PG_8814B) +#define BIT_CLEAR_CH15_RSVD_PG_8814B(x) ((x) & (~BITS_CH15_RSVD_PG_8814B)) +#define BIT_GET_CH15_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH15_RSVD_PG_8814B) & BIT_MASK_CH15_RSVD_PG_8814B) +#define BIT_SET_CH15_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH15_RSVD_PG_8814B(x) | BIT_CH15_RSVD_PG_8814B(v)) + +/* 2 REG_DMA_RQPN_INFO_16_8814B */ + +#define BIT_SHIFT_CH16_AVAL_PG_8814B 16 +#define BIT_MASK_CH16_AVAL_PG_8814B 0xfff +#define BIT_CH16_AVAL_PG_8814B(x) \ + (((x) & BIT_MASK_CH16_AVAL_PG_8814B) << BIT_SHIFT_CH16_AVAL_PG_8814B) +#define BITS_CH16_AVAL_PG_8814B \ + (BIT_MASK_CH16_AVAL_PG_8814B << BIT_SHIFT_CH16_AVAL_PG_8814B) +#define BIT_CLEAR_CH16_AVAL_PG_8814B(x) ((x) & (~BITS_CH16_AVAL_PG_8814B)) +#define BIT_GET_CH16_AVAL_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH16_AVAL_PG_8814B) & BIT_MASK_CH16_AVAL_PG_8814B) +#define BIT_SET_CH16_AVAL_PG_8814B(x, v) \ + (BIT_CLEAR_CH16_AVAL_PG_8814B(x) | BIT_CH16_AVAL_PG_8814B(v)) + +#define BIT_SHIFT_CH16_RSVD_PG_8814B 0 +#define BIT_MASK_CH16_RSVD_PG_8814B 0xfff +#define BIT_CH16_RSVD_PG_8814B(x) \ + (((x) & BIT_MASK_CH16_RSVD_PG_8814B) << BIT_SHIFT_CH16_RSVD_PG_8814B) +#define BITS_CH16_RSVD_PG_8814B \ + (BIT_MASK_CH16_RSVD_PG_8814B << BIT_SHIFT_CH16_RSVD_PG_8814B) +#define BIT_CLEAR_CH16_RSVD_PG_8814B(x) ((x) & (~BITS_CH16_RSVD_PG_8814B)) +#define BIT_GET_CH16_RSVD_PG_8814B(x) \ + (((x) >> BIT_SHIFT_CH16_RSVD_PG_8814B) & BIT_MASK_CH16_RSVD_PG_8814B) +#define BIT_SET_CH16_RSVD_PG_8814B(x, v) \ + (BIT_CLEAR_CH16_RSVD_PG_8814B(x) | BIT_CH16_RSVD_PG_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_HWAMSDU_CTL1_8814B */ + +#define BIT_SHIFT_HWAMSDU_PKTNUM_8814B 8 +#define BIT_MASK_HWAMSDU_PKTNUM_8814B 0x3f +#define BIT_HWAMSDU_PKTNUM_8814B(x) \ + (((x) & BIT_MASK_HWAMSDU_PKTNUM_8814B) \ + << BIT_SHIFT_HWAMSDU_PKTNUM_8814B) +#define BITS_HWAMSDU_PKTNUM_8814B \ + (BIT_MASK_HWAMSDU_PKTNUM_8814B << BIT_SHIFT_HWAMSDU_PKTNUM_8814B) +#define BIT_CLEAR_HWAMSDU_PKTNUM_8814B(x) ((x) & (~BITS_HWAMSDU_PKTNUM_8814B)) +#define BIT_GET_HWAMSDU_PKTNUM_8814B(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_PKTNUM_8814B) & \ + BIT_MASK_HWAMSDU_PKTNUM_8814B) +#define BIT_SET_HWAMSDU_PKTNUM_8814B(x, v) \ + (BIT_CLEAR_HWAMSDU_PKTNUM_8814B(x) | BIT_HWAMSDU_PKTNUM_8814B(v)) + +#define BIT_HWAMSDU_BUSY_8814B BIT(7) +#define BIT_SINGLE_AMSDU_8814B BIT(2) +#define BIT_HWAMSDU_PADDING_MODE_8814B BIT(1) +#define BIT_HWAMSDU_EN_8814B BIT(0) + +/* 2 REG_HWAMSDU_CTL2_8814B */ + +#define BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B 16 +#define BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B 0xffff +#define BIT_HWAMSDU_AMSDU_TIMEOUT_8814B(x) \ + (((x) & BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B) \ + << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B) +#define BITS_HWAMSDU_AMSDU_TIMEOUT_8814B \ + (BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B \ + << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B) +#define BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT_8814B(x) \ + ((x) & (~BITS_HWAMSDU_AMSDU_TIMEOUT_8814B)) +#define BIT_GET_HWAMSDU_AMSDU_TIMEOUT_8814B(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B) & \ + BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B) +#define BIT_SET_HWAMSDU_AMSDU_TIMEOUT_8814B(x, v) \ + (BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT_8814B(x) | \ + BIT_HWAMSDU_AMSDU_TIMEOUT_8814B(v)) + +#define BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B 0 +#define BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B 0xffff +#define BIT_HWAMSDU_MSDU_TIMEOUT_8814B(x) \ + (((x) & BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B) \ + << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B) +#define BITS_HWAMSDU_MSDU_TIMEOUT_8814B \ + (BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B \ + << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B) +#define BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT_8814B(x) \ + ((x) & (~BITS_HWAMSDU_MSDU_TIMEOUT_8814B)) +#define BIT_GET_HWAMSDU_MSDU_TIMEOUT_8814B(x) \ + (((x) >> BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B) & \ + BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B) +#define BIT_SET_HWAMSDU_MSDU_TIMEOUT_8814B(x, v) \ + (BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT_8814B(x) | \ + BIT_HWAMSDU_MSDU_TIMEOUT_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_0_8814B */ +#define BIT_CH0_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH0_HIGH_TH_8814B 16 +#define BIT_MASK_CH0_HIGH_TH_8814B 0xfff +#define BIT_CH0_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH0_HIGH_TH_8814B) << BIT_SHIFT_CH0_HIGH_TH_8814B) +#define BITS_CH0_HIGH_TH_8814B \ + (BIT_MASK_CH0_HIGH_TH_8814B << BIT_SHIFT_CH0_HIGH_TH_8814B) +#define BIT_CLEAR_CH0_HIGH_TH_8814B(x) ((x) & (~BITS_CH0_HIGH_TH_8814B)) +#define BIT_GET_CH0_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH0_HIGH_TH_8814B) & BIT_MASK_CH0_HIGH_TH_8814B) +#define BIT_SET_CH0_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH0_HIGH_TH_8814B(x) | BIT_CH0_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH0_LOW_TH_8814B 0 +#define BIT_MASK_CH0_LOW_TH_8814B 0xfff +#define BIT_CH0_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH0_LOW_TH_8814B) << BIT_SHIFT_CH0_LOW_TH_8814B) +#define BITS_CH0_LOW_TH_8814B \ + (BIT_MASK_CH0_LOW_TH_8814B << BIT_SHIFT_CH0_LOW_TH_8814B) +#define BIT_CLEAR_CH0_LOW_TH_8814B(x) ((x) & (~BITS_CH0_LOW_TH_8814B)) +#define BIT_GET_CH0_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH0_LOW_TH_8814B) & BIT_MASK_CH0_LOW_TH_8814B) +#define BIT_SET_CH0_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH0_LOW_TH_8814B(x) | BIT_CH0_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_1_8814B */ +#define BIT_CH1_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH1_HIGH_TH_8814B 16 +#define BIT_MASK_CH1_HIGH_TH_8814B 0xfff +#define BIT_CH1_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH1_HIGH_TH_8814B) << BIT_SHIFT_CH1_HIGH_TH_8814B) +#define BITS_CH1_HIGH_TH_8814B \ + (BIT_MASK_CH1_HIGH_TH_8814B << BIT_SHIFT_CH1_HIGH_TH_8814B) +#define BIT_CLEAR_CH1_HIGH_TH_8814B(x) ((x) & (~BITS_CH1_HIGH_TH_8814B)) +#define BIT_GET_CH1_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH1_HIGH_TH_8814B) & BIT_MASK_CH1_HIGH_TH_8814B) +#define BIT_SET_CH1_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH1_HIGH_TH_8814B(x) | BIT_CH1_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH1_LOW_TH_8814B 0 +#define BIT_MASK_CH1_LOW_TH_8814B 0xfff +#define BIT_CH1_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH1_LOW_TH_8814B) << BIT_SHIFT_CH1_LOW_TH_8814B) +#define BITS_CH1_LOW_TH_8814B \ + (BIT_MASK_CH1_LOW_TH_8814B << BIT_SHIFT_CH1_LOW_TH_8814B) +#define BIT_CLEAR_CH1_LOW_TH_8814B(x) ((x) & (~BITS_CH1_LOW_TH_8814B)) +#define BIT_GET_CH1_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH1_LOW_TH_8814B) & BIT_MASK_CH1_LOW_TH_8814B) +#define BIT_SET_CH1_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH1_LOW_TH_8814B(x) | BIT_CH1_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_2_8814B */ +#define BIT_CH2_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH2_HIGH_TH_8814B 16 +#define BIT_MASK_CH2_HIGH_TH_8814B 0xfff +#define BIT_CH2_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH2_HIGH_TH_8814B) << BIT_SHIFT_CH2_HIGH_TH_8814B) +#define BITS_CH2_HIGH_TH_8814B \ + (BIT_MASK_CH2_HIGH_TH_8814B << BIT_SHIFT_CH2_HIGH_TH_8814B) +#define BIT_CLEAR_CH2_HIGH_TH_8814B(x) ((x) & (~BITS_CH2_HIGH_TH_8814B)) +#define BIT_GET_CH2_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH2_HIGH_TH_8814B) & BIT_MASK_CH2_HIGH_TH_8814B) +#define BIT_SET_CH2_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH2_HIGH_TH_8814B(x) | BIT_CH2_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH2_LOW_TH_8814B 0 +#define BIT_MASK_CH2_LOW_TH_8814B 0xfff +#define BIT_CH2_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH2_LOW_TH_8814B) << BIT_SHIFT_CH2_LOW_TH_8814B) +#define BITS_CH2_LOW_TH_8814B \ + (BIT_MASK_CH2_LOW_TH_8814B << BIT_SHIFT_CH2_LOW_TH_8814B) +#define BIT_CLEAR_CH2_LOW_TH_8814B(x) ((x) & (~BITS_CH2_LOW_TH_8814B)) +#define BIT_GET_CH2_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH2_LOW_TH_8814B) & BIT_MASK_CH2_LOW_TH_8814B) +#define BIT_SET_CH2_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH2_LOW_TH_8814B(x) | BIT_CH2_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_3_8814B */ +#define BIT_CH3_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH3_HIGH_TH_8814B 16 +#define BIT_MASK_CH3_HIGH_TH_8814B 0xfff +#define BIT_CH3_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH3_HIGH_TH_8814B) << BIT_SHIFT_CH3_HIGH_TH_8814B) +#define BITS_CH3_HIGH_TH_8814B \ + (BIT_MASK_CH3_HIGH_TH_8814B << BIT_SHIFT_CH3_HIGH_TH_8814B) +#define BIT_CLEAR_CH3_HIGH_TH_8814B(x) ((x) & (~BITS_CH3_HIGH_TH_8814B)) +#define BIT_GET_CH3_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH3_HIGH_TH_8814B) & BIT_MASK_CH3_HIGH_TH_8814B) +#define BIT_SET_CH3_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH3_HIGH_TH_8814B(x) | BIT_CH3_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH3_LOW_TH_8814B 0 +#define BIT_MASK_CH3_LOW_TH_8814B 0xfff +#define BIT_CH3_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH3_LOW_TH_8814B) << BIT_SHIFT_CH3_LOW_TH_8814B) +#define BITS_CH3_LOW_TH_8814B \ + (BIT_MASK_CH3_LOW_TH_8814B << BIT_SHIFT_CH3_LOW_TH_8814B) +#define BIT_CLEAR_CH3_LOW_TH_8814B(x) ((x) & (~BITS_CH3_LOW_TH_8814B)) +#define BIT_GET_CH3_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH3_LOW_TH_8814B) & BIT_MASK_CH3_LOW_TH_8814B) +#define BIT_SET_CH3_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH3_LOW_TH_8814B(x) | BIT_CH3_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_4_8814B */ +#define BIT_CH4_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH4_HIGH_TH_8814B 16 +#define BIT_MASK_CH4_HIGH_TH_8814B 0xfff +#define BIT_CH4_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH4_HIGH_TH_8814B) << BIT_SHIFT_CH4_HIGH_TH_8814B) +#define BITS_CH4_HIGH_TH_8814B \ + (BIT_MASK_CH4_HIGH_TH_8814B << BIT_SHIFT_CH4_HIGH_TH_8814B) +#define BIT_CLEAR_CH4_HIGH_TH_8814B(x) ((x) & (~BITS_CH4_HIGH_TH_8814B)) +#define BIT_GET_CH4_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH4_HIGH_TH_8814B) & BIT_MASK_CH4_HIGH_TH_8814B) +#define BIT_SET_CH4_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH4_HIGH_TH_8814B(x) | BIT_CH4_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH4_LOW_TH_8814B 0 +#define BIT_MASK_CH4_LOW_TH_8814B 0xfff +#define BIT_CH4_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH4_LOW_TH_8814B) << BIT_SHIFT_CH4_LOW_TH_8814B) +#define BITS_CH4_LOW_TH_8814B \ + (BIT_MASK_CH4_LOW_TH_8814B << BIT_SHIFT_CH4_LOW_TH_8814B) +#define BIT_CLEAR_CH4_LOW_TH_8814B(x) ((x) & (~BITS_CH4_LOW_TH_8814B)) +#define BIT_GET_CH4_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH4_LOW_TH_8814B) & BIT_MASK_CH4_LOW_TH_8814B) +#define BIT_SET_CH4_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH4_LOW_TH_8814B(x) | BIT_CH4_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_5_8814B */ +#define BIT_CH5_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH5_HIGH_TH_8814B 16 +#define BIT_MASK_CH5_HIGH_TH_8814B 0xfff +#define BIT_CH5_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH5_HIGH_TH_8814B) << BIT_SHIFT_CH5_HIGH_TH_8814B) +#define BITS_CH5_HIGH_TH_8814B \ + (BIT_MASK_CH5_HIGH_TH_8814B << BIT_SHIFT_CH5_HIGH_TH_8814B) +#define BIT_CLEAR_CH5_HIGH_TH_8814B(x) ((x) & (~BITS_CH5_HIGH_TH_8814B)) +#define BIT_GET_CH5_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH5_HIGH_TH_8814B) & BIT_MASK_CH5_HIGH_TH_8814B) +#define BIT_SET_CH5_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH5_HIGH_TH_8814B(x) | BIT_CH5_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH5_LOW_TH_8814B 0 +#define BIT_MASK_CH5_LOW_TH_8814B 0xfff +#define BIT_CH5_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH5_LOW_TH_8814B) << BIT_SHIFT_CH5_LOW_TH_8814B) +#define BITS_CH5_LOW_TH_8814B \ + (BIT_MASK_CH5_LOW_TH_8814B << BIT_SHIFT_CH5_LOW_TH_8814B) +#define BIT_CLEAR_CH5_LOW_TH_8814B(x) ((x) & (~BITS_CH5_LOW_TH_8814B)) +#define BIT_GET_CH5_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH5_LOW_TH_8814B) & BIT_MASK_CH5_LOW_TH_8814B) +#define BIT_SET_CH5_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH5_LOW_TH_8814B(x) | BIT_CH5_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_6_8814B */ +#define BIT_CH6_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH6_HIGH_TH_8814B 16 +#define BIT_MASK_CH6_HIGH_TH_8814B 0xfff +#define BIT_CH6_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH6_HIGH_TH_8814B) << BIT_SHIFT_CH6_HIGH_TH_8814B) +#define BITS_CH6_HIGH_TH_8814B \ + (BIT_MASK_CH6_HIGH_TH_8814B << BIT_SHIFT_CH6_HIGH_TH_8814B) +#define BIT_CLEAR_CH6_HIGH_TH_8814B(x) ((x) & (~BITS_CH6_HIGH_TH_8814B)) +#define BIT_GET_CH6_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH6_HIGH_TH_8814B) & BIT_MASK_CH6_HIGH_TH_8814B) +#define BIT_SET_CH6_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH6_HIGH_TH_8814B(x) | BIT_CH6_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH6_LOW_TH_8814B 0 +#define BIT_MASK_CH6_LOW_TH_8814B 0xfff +#define BIT_CH6_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH6_LOW_TH_8814B) << BIT_SHIFT_CH6_LOW_TH_8814B) +#define BITS_CH6_LOW_TH_8814B \ + (BIT_MASK_CH6_LOW_TH_8814B << BIT_SHIFT_CH6_LOW_TH_8814B) +#define BIT_CLEAR_CH6_LOW_TH_8814B(x) ((x) & (~BITS_CH6_LOW_TH_8814B)) +#define BIT_GET_CH6_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH6_LOW_TH_8814B) & BIT_MASK_CH6_LOW_TH_8814B) +#define BIT_SET_CH6_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH6_LOW_TH_8814B(x) | BIT_CH6_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_7_8814B */ +#define BIT_CH7_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH7_HIGH_TH_8814B 16 +#define BIT_MASK_CH7_HIGH_TH_8814B 0xfff +#define BIT_CH7_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH7_HIGH_TH_8814B) << BIT_SHIFT_CH7_HIGH_TH_8814B) +#define BITS_CH7_HIGH_TH_8814B \ + (BIT_MASK_CH7_HIGH_TH_8814B << BIT_SHIFT_CH7_HIGH_TH_8814B) +#define BIT_CLEAR_CH7_HIGH_TH_8814B(x) ((x) & (~BITS_CH7_HIGH_TH_8814B)) +#define BIT_GET_CH7_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH7_HIGH_TH_8814B) & BIT_MASK_CH7_HIGH_TH_8814B) +#define BIT_SET_CH7_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH7_HIGH_TH_8814B(x) | BIT_CH7_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH7_LOW_TH_8814B 0 +#define BIT_MASK_CH7_LOW_TH_8814B 0xfff +#define BIT_CH7_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH7_LOW_TH_8814B) << BIT_SHIFT_CH7_LOW_TH_8814B) +#define BITS_CH7_LOW_TH_8814B \ + (BIT_MASK_CH7_LOW_TH_8814B << BIT_SHIFT_CH7_LOW_TH_8814B) +#define BIT_CLEAR_CH7_LOW_TH_8814B(x) ((x) & (~BITS_CH7_LOW_TH_8814B)) +#define BIT_GET_CH7_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH7_LOW_TH_8814B) & BIT_MASK_CH7_LOW_TH_8814B) +#define BIT_SET_CH7_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH7_LOW_TH_8814B(x) | BIT_CH7_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_8_8814B */ +#define BIT_CH8_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH8_HIGH_TH_8814B 16 +#define BIT_MASK_CH8_HIGH_TH_8814B 0xfff +#define BIT_CH8_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH8_HIGH_TH_8814B) << BIT_SHIFT_CH8_HIGH_TH_8814B) +#define BITS_CH8_HIGH_TH_8814B \ + (BIT_MASK_CH8_HIGH_TH_8814B << BIT_SHIFT_CH8_HIGH_TH_8814B) +#define BIT_CLEAR_CH8_HIGH_TH_8814B(x) ((x) & (~BITS_CH8_HIGH_TH_8814B)) +#define BIT_GET_CH8_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH8_HIGH_TH_8814B) & BIT_MASK_CH8_HIGH_TH_8814B) +#define BIT_SET_CH8_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH8_HIGH_TH_8814B(x) | BIT_CH8_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH8_LOW_TH_8814B 0 +#define BIT_MASK_CH8_LOW_TH_8814B 0xfff +#define BIT_CH8_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH8_LOW_TH_8814B) << BIT_SHIFT_CH8_LOW_TH_8814B) +#define BITS_CH8_LOW_TH_8814B \ + (BIT_MASK_CH8_LOW_TH_8814B << BIT_SHIFT_CH8_LOW_TH_8814B) +#define BIT_CLEAR_CH8_LOW_TH_8814B(x) ((x) & (~BITS_CH8_LOW_TH_8814B)) +#define BIT_GET_CH8_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH8_LOW_TH_8814B) & BIT_MASK_CH8_LOW_TH_8814B) +#define BIT_SET_CH8_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH8_LOW_TH_8814B(x) | BIT_CH8_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_9_8814B */ +#define BIT_CH9_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH9_HIGH_TH_8814B 16 +#define BIT_MASK_CH9_HIGH_TH_8814B 0xfff +#define BIT_CH9_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH9_HIGH_TH_8814B) << BIT_SHIFT_CH9_HIGH_TH_8814B) +#define BITS_CH9_HIGH_TH_8814B \ + (BIT_MASK_CH9_HIGH_TH_8814B << BIT_SHIFT_CH9_HIGH_TH_8814B) +#define BIT_CLEAR_CH9_HIGH_TH_8814B(x) ((x) & (~BITS_CH9_HIGH_TH_8814B)) +#define BIT_GET_CH9_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH9_HIGH_TH_8814B) & BIT_MASK_CH9_HIGH_TH_8814B) +#define BIT_SET_CH9_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH9_HIGH_TH_8814B(x) | BIT_CH9_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH9_LOW_TH_8814B 0 +#define BIT_MASK_CH9_LOW_TH_8814B 0xfff +#define BIT_CH9_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH9_LOW_TH_8814B) << BIT_SHIFT_CH9_LOW_TH_8814B) +#define BITS_CH9_LOW_TH_8814B \ + (BIT_MASK_CH9_LOW_TH_8814B << BIT_SHIFT_CH9_LOW_TH_8814B) +#define BIT_CLEAR_CH9_LOW_TH_8814B(x) ((x) & (~BITS_CH9_LOW_TH_8814B)) +#define BIT_GET_CH9_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH9_LOW_TH_8814B) & BIT_MASK_CH9_LOW_TH_8814B) +#define BIT_SET_CH9_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH9_LOW_TH_8814B(x) | BIT_CH9_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_10_8814B */ +#define BIT_CH10_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH10_HIGH_TH_8814B 16 +#define BIT_MASK_CH10_HIGH_TH_8814B 0xfff +#define BIT_CH10_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH10_HIGH_TH_8814B) << BIT_SHIFT_CH10_HIGH_TH_8814B) +#define BITS_CH10_HIGH_TH_8814B \ + (BIT_MASK_CH10_HIGH_TH_8814B << BIT_SHIFT_CH10_HIGH_TH_8814B) +#define BIT_CLEAR_CH10_HIGH_TH_8814B(x) ((x) & (~BITS_CH10_HIGH_TH_8814B)) +#define BIT_GET_CH10_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH10_HIGH_TH_8814B) & BIT_MASK_CH10_HIGH_TH_8814B) +#define BIT_SET_CH10_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH10_HIGH_TH_8814B(x) | BIT_CH10_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH10_LOW_TH_8814B 0 +#define BIT_MASK_CH10_LOW_TH_8814B 0xfff +#define BIT_CH10_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH10_LOW_TH_8814B) << BIT_SHIFT_CH10_LOW_TH_8814B) +#define BITS_CH10_LOW_TH_8814B \ + (BIT_MASK_CH10_LOW_TH_8814B << BIT_SHIFT_CH10_LOW_TH_8814B) +#define BIT_CLEAR_CH10_LOW_TH_8814B(x) ((x) & (~BITS_CH10_LOW_TH_8814B)) +#define BIT_GET_CH10_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH10_LOW_TH_8814B) & BIT_MASK_CH10_LOW_TH_8814B) +#define BIT_SET_CH10_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH10_LOW_TH_8814B(x) | BIT_CH10_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_11_8814B */ +#define BIT_CH11_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH11_HIGH_TH_8814B 16 +#define BIT_MASK_CH11_HIGH_TH_8814B 0xfff +#define BIT_CH11_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH11_HIGH_TH_8814B) << BIT_SHIFT_CH11_HIGH_TH_8814B) +#define BITS_CH11_HIGH_TH_8814B \ + (BIT_MASK_CH11_HIGH_TH_8814B << BIT_SHIFT_CH11_HIGH_TH_8814B) +#define BIT_CLEAR_CH11_HIGH_TH_8814B(x) ((x) & (~BITS_CH11_HIGH_TH_8814B)) +#define BIT_GET_CH11_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH11_HIGH_TH_8814B) & BIT_MASK_CH11_HIGH_TH_8814B) +#define BIT_SET_CH11_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH11_HIGH_TH_8814B(x) | BIT_CH11_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH11_LOW_TH_8814B 0 +#define BIT_MASK_CH11_LOW_TH_8814B 0xfff +#define BIT_CH11_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH11_LOW_TH_8814B) << BIT_SHIFT_CH11_LOW_TH_8814B) +#define BITS_CH11_LOW_TH_8814B \ + (BIT_MASK_CH11_LOW_TH_8814B << BIT_SHIFT_CH11_LOW_TH_8814B) +#define BIT_CLEAR_CH11_LOW_TH_8814B(x) ((x) & (~BITS_CH11_LOW_TH_8814B)) +#define BIT_GET_CH11_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH11_LOW_TH_8814B) & BIT_MASK_CH11_LOW_TH_8814B) +#define BIT_SET_CH11_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH11_LOW_TH_8814B(x) | BIT_CH11_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_12_8814B */ +#define BIT_CH12_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH12_HIGH_TH_8814B 16 +#define BIT_MASK_CH12_HIGH_TH_8814B 0xfff +#define BIT_CH12_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH12_HIGH_TH_8814B) << BIT_SHIFT_CH12_HIGH_TH_8814B) +#define BITS_CH12_HIGH_TH_8814B \ + (BIT_MASK_CH12_HIGH_TH_8814B << BIT_SHIFT_CH12_HIGH_TH_8814B) +#define BIT_CLEAR_CH12_HIGH_TH_8814B(x) ((x) & (~BITS_CH12_HIGH_TH_8814B)) +#define BIT_GET_CH12_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH12_HIGH_TH_8814B) & BIT_MASK_CH12_HIGH_TH_8814B) +#define BIT_SET_CH12_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH12_HIGH_TH_8814B(x) | BIT_CH12_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH12_LOW_TH_8814B 0 +#define BIT_MASK_CH12_LOW_TH_8814B 0xfff +#define BIT_CH12_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH12_LOW_TH_8814B) << BIT_SHIFT_CH12_LOW_TH_8814B) +#define BITS_CH12_LOW_TH_8814B \ + (BIT_MASK_CH12_LOW_TH_8814B << BIT_SHIFT_CH12_LOW_TH_8814B) +#define BIT_CLEAR_CH12_LOW_TH_8814B(x) ((x) & (~BITS_CH12_LOW_TH_8814B)) +#define BIT_GET_CH12_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH12_LOW_TH_8814B) & BIT_MASK_CH12_LOW_TH_8814B) +#define BIT_SET_CH12_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH12_LOW_TH_8814B(x) | BIT_CH12_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_13_8814B */ +#define BIT_CH13_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH13_HIGH_TH_8814B 16 +#define BIT_MASK_CH13_HIGH_TH_8814B 0xfff +#define BIT_CH13_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH13_HIGH_TH_8814B) << BIT_SHIFT_CH13_HIGH_TH_8814B) +#define BITS_CH13_HIGH_TH_8814B \ + (BIT_MASK_CH13_HIGH_TH_8814B << BIT_SHIFT_CH13_HIGH_TH_8814B) +#define BIT_CLEAR_CH13_HIGH_TH_8814B(x) ((x) & (~BITS_CH13_HIGH_TH_8814B)) +#define BIT_GET_CH13_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH13_HIGH_TH_8814B) & BIT_MASK_CH13_HIGH_TH_8814B) +#define BIT_SET_CH13_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH13_HIGH_TH_8814B(x) | BIT_CH13_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH13_LOW_TH_8814B 0 +#define BIT_MASK_CH13_LOW_TH_8814B 0xfff +#define BIT_CH13_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH13_LOW_TH_8814B) << BIT_SHIFT_CH13_LOW_TH_8814B) +#define BITS_CH13_LOW_TH_8814B \ + (BIT_MASK_CH13_LOW_TH_8814B << BIT_SHIFT_CH13_LOW_TH_8814B) +#define BIT_CLEAR_CH13_LOW_TH_8814B(x) ((x) & (~BITS_CH13_LOW_TH_8814B)) +#define BIT_GET_CH13_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH13_LOW_TH_8814B) & BIT_MASK_CH13_LOW_TH_8814B) +#define BIT_SET_CH13_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH13_LOW_TH_8814B(x) | BIT_CH13_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_14_8814B */ +#define BIT_CH14_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH14_HIGH_TH_8814B 16 +#define BIT_MASK_CH14_HIGH_TH_8814B 0xfff +#define BIT_CH14_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH14_HIGH_TH_8814B) << BIT_SHIFT_CH14_HIGH_TH_8814B) +#define BITS_CH14_HIGH_TH_8814B \ + (BIT_MASK_CH14_HIGH_TH_8814B << BIT_SHIFT_CH14_HIGH_TH_8814B) +#define BIT_CLEAR_CH14_HIGH_TH_8814B(x) ((x) & (~BITS_CH14_HIGH_TH_8814B)) +#define BIT_GET_CH14_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH14_HIGH_TH_8814B) & BIT_MASK_CH14_HIGH_TH_8814B) +#define BIT_SET_CH14_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH14_HIGH_TH_8814B(x) | BIT_CH14_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH14_LOW_TH_8814B 0 +#define BIT_MASK_CH14_LOW_TH_8814B 0xfff +#define BIT_CH14_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH14_LOW_TH_8814B) << BIT_SHIFT_CH14_LOW_TH_8814B) +#define BITS_CH14_LOW_TH_8814B \ + (BIT_MASK_CH14_LOW_TH_8814B << BIT_SHIFT_CH14_LOW_TH_8814B) +#define BIT_CLEAR_CH14_LOW_TH_8814B(x) ((x) & (~BITS_CH14_LOW_TH_8814B)) +#define BIT_GET_CH14_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH14_LOW_TH_8814B) & BIT_MASK_CH14_LOW_TH_8814B) +#define BIT_SET_CH14_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH14_LOW_TH_8814B(x) | BIT_CH14_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_15_8814B */ +#define BIT_CH15_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH15_HIGH_TH_8814B 16 +#define BIT_MASK_CH15_HIGH_TH_8814B 0xfff +#define BIT_CH15_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH15_HIGH_TH_8814B) << BIT_SHIFT_CH15_HIGH_TH_8814B) +#define BITS_CH15_HIGH_TH_8814B \ + (BIT_MASK_CH15_HIGH_TH_8814B << BIT_SHIFT_CH15_HIGH_TH_8814B) +#define BIT_CLEAR_CH15_HIGH_TH_8814B(x) ((x) & (~BITS_CH15_HIGH_TH_8814B)) +#define BIT_GET_CH15_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH15_HIGH_TH_8814B) & BIT_MASK_CH15_HIGH_TH_8814B) +#define BIT_SET_CH15_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH15_HIGH_TH_8814B(x) | BIT_CH15_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH15_LOW_TH_8814B 0 +#define BIT_MASK_CH15_LOW_TH_8814B 0xfff +#define BIT_CH15_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH15_LOW_TH_8814B) << BIT_SHIFT_CH15_LOW_TH_8814B) +#define BITS_CH15_LOW_TH_8814B \ + (BIT_MASK_CH15_LOW_TH_8814B << BIT_SHIFT_CH15_LOW_TH_8814B) +#define BIT_CLEAR_CH15_LOW_TH_8814B(x) ((x) & (~BITS_CH15_LOW_TH_8814B)) +#define BIT_GET_CH15_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH15_LOW_TH_8814B) & BIT_MASK_CH15_LOW_TH_8814B) +#define BIT_SET_CH15_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH15_LOW_TH_8814B(x) | BIT_CH15_LOW_TH_8814B(v)) + +/* 2 REG_TXPAGE_INT_CTRL_16_8814B */ +#define BIT_CH16_INT_EN_8814B BIT(31) + +#define BIT_SHIFT_CH16_HIGH_TH_8814B 16 +#define BIT_MASK_CH16_HIGH_TH_8814B 0xfff +#define BIT_CH16_HIGH_TH_8814B(x) \ + (((x) & BIT_MASK_CH16_HIGH_TH_8814B) << BIT_SHIFT_CH16_HIGH_TH_8814B) +#define BITS_CH16_HIGH_TH_8814B \ + (BIT_MASK_CH16_HIGH_TH_8814B << BIT_SHIFT_CH16_HIGH_TH_8814B) +#define BIT_CLEAR_CH16_HIGH_TH_8814B(x) ((x) & (~BITS_CH16_HIGH_TH_8814B)) +#define BIT_GET_CH16_HIGH_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH16_HIGH_TH_8814B) & BIT_MASK_CH16_HIGH_TH_8814B) +#define BIT_SET_CH16_HIGH_TH_8814B(x, v) \ + (BIT_CLEAR_CH16_HIGH_TH_8814B(x) | BIT_CH16_HIGH_TH_8814B(v)) + +#define BIT_SHIFT_CH16_LOW_TH_8814B 0 +#define BIT_MASK_CH16_LOW_TH_8814B 0xfff +#define BIT_CH16_LOW_TH_8814B(x) \ + (((x) & BIT_MASK_CH16_LOW_TH_8814B) << BIT_SHIFT_CH16_LOW_TH_8814B) +#define BITS_CH16_LOW_TH_8814B \ + (BIT_MASK_CH16_LOW_TH_8814B << BIT_SHIFT_CH16_LOW_TH_8814B) +#define BIT_CLEAR_CH16_LOW_TH_8814B(x) ((x) & (~BITS_CH16_LOW_TH_8814B)) +#define BIT_GET_CH16_LOW_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CH16_LOW_TH_8814B) & BIT_MASK_CH16_LOW_TH_8814B) +#define BIT_SET_CH16_LOW_TH_8814B(x, v) \ + (BIT_CLEAR_CH16_LOW_TH_8814B(x) | BIT_CH16_LOW_TH_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + /* 2 REG_NOT_VALID_8814B */ /* 2 REG_PCIE_CTRL_8814B */ @@ -4277,18 +9427,35 @@ #define BIT_SHIFT_PCIE_MAX_RXDMA_8814B 28 #define BIT_MASK_PCIE_MAX_RXDMA_8814B 0x7 -#define BIT_PCIE_MAX_RXDMA_8814B(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8814B) << BIT_SHIFT_PCIE_MAX_RXDMA_8814B) -#define BIT_GET_PCIE_MAX_RXDMA_8814B(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8814B) & BIT_MASK_PCIE_MAX_RXDMA_8814B) - +#define BIT_PCIE_MAX_RXDMA_8814B(x) \ + (((x) & BIT_MASK_PCIE_MAX_RXDMA_8814B) \ + << BIT_SHIFT_PCIE_MAX_RXDMA_8814B) +#define BITS_PCIE_MAX_RXDMA_8814B \ + (BIT_MASK_PCIE_MAX_RXDMA_8814B << BIT_SHIFT_PCIE_MAX_RXDMA_8814B) +#define BIT_CLEAR_PCIE_MAX_RXDMA_8814B(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8814B)) +#define BIT_GET_PCIE_MAX_RXDMA_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8814B) & \ + BIT_MASK_PCIE_MAX_RXDMA_8814B) +#define BIT_SET_PCIE_MAX_RXDMA_8814B(x, v) \ + (BIT_CLEAR_PCIE_MAX_RXDMA_8814B(x) | BIT_PCIE_MAX_RXDMA_8814B(v)) #define BIT_MULRW_8814B BIT(27) #define BIT_SHIFT_PCIE_MAX_TXDMA_8814B 24 #define BIT_MASK_PCIE_MAX_TXDMA_8814B 0x7 -#define BIT_PCIE_MAX_TXDMA_8814B(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8814B) << BIT_SHIFT_PCIE_MAX_TXDMA_8814B) -#define BIT_GET_PCIE_MAX_TXDMA_8814B(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8814B) & BIT_MASK_PCIE_MAX_TXDMA_8814B) - - +#define BIT_PCIE_MAX_TXDMA_8814B(x) \ + (((x) & BIT_MASK_PCIE_MAX_TXDMA_8814B) \ + << BIT_SHIFT_PCIE_MAX_TXDMA_8814B) +#define BITS_PCIE_MAX_TXDMA_8814B \ + (BIT_MASK_PCIE_MAX_TXDMA_8814B << BIT_SHIFT_PCIE_MAX_TXDMA_8814B) +#define BIT_CLEAR_PCIE_MAX_TXDMA_8814B(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8814B)) +#define BIT_GET_PCIE_MAX_TXDMA_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8814B) & \ + BIT_MASK_PCIE_MAX_TXDMA_8814B) +#define BIT_SET_PCIE_MAX_TXDMA_8814B(x, v) \ + (BIT_CLEAR_PCIE_MAX_TXDMA_8814B(x) | BIT_PCIE_MAX_TXDMA_8814B(v)) + +#define BIT_PWR_SCALE_START_PS_8814B BIT(23) #define BIT_EN_CPL_TIMEOUT_PS_8814B BIT(22) #define BIT_REG_TXDMA_FAIL_PS_8814B BIT(21) #define BIT_PCIE_RST_TRXDMA_INTF_8814B BIT(20) @@ -4296,2813 +9463,7677 @@ #define BIT_EN_ADV_CLKGATE_8814B BIT(18) #define BIT_PCIE_EN_SWENT_L23_8814B BIT(17) #define BIT_PCIE_EN_HWEXT_L1_8814B BIT(16) -#define BIT_RX_CLOSE_EN_8814B BIT(15) -#define BIT_STOP_BCNQ_8814B BIT(14) -#define BIT_STOP_MGQ_8814B BIT(13) -#define BIT_STOP_VOQ_8814B BIT(12) -#define BIT_STOP_VIQ_8814B BIT(11) -#define BIT_STOP_BEQ_8814B BIT(10) -#define BIT_STOP_BKQ_8814B BIT(9) -#define BIT_STOP_RXQ_8814B BIT(8) -#define BIT_STOP_HI7Q_8814B BIT(7) -#define BIT_STOP_HI6Q_8814B BIT(6) -#define BIT_STOP_HI5Q_8814B BIT(5) -#define BIT_STOP_HI4Q_8814B BIT(4) -#define BIT_STOP_HI3Q_8814B BIT(3) -#define BIT_STOP_HI2Q_8814B BIT(2) -#define BIT_STOP_HI1Q_8814B BIT(1) -#define BIT_STOP_HI0Q_8814B BIT(0) - -/* 2 REG_INT_MIG_8814B */ +#define BIT_STOP_P0_MPRT_BCNQ4_8814B BIT(6) +#define BIT_STOP_P0_MPRT_BCNQ3_8814B BIT(4) +#define BIT_STOP_P0_MPRT_BCNQ2_8814B BIT(2) +#define BIT_STOP_P0_MPRT_BCNQ1_8814B BIT(0) + +/* 2 REG_ACH_CTRL_8814B */ +#define BIT_STOP_P0HIQ19_8814B BIT(27) +#define BIT_STOP_P0HIQ18_8814B BIT(26) +#define BIT_STOP_P0HIQ17_8814B BIT(25) +#define BIT_STOP_P0HIQ16_8814B BIT(24) +#define BIT_RX_CLOSE_EN_V1_8814B BIT(21) +#define BIT_STOP_FWCMDQ_8814B BIT(20) +#define BIT_STOP_P0BCNQ_8814B BIT(18) +#define BIT_STOP_P0MGQ_8814B BIT(16) +#define BIT_STOP_ACH13_8814B BIT(15) +#define BIT_STOP_ACH12_8814B BIT(14) +#define BIT_STOP_ACH11_8814B BIT(13) +#define BIT_STOP_ACH10_8814B BIT(12) +#define BIT_STOP_ACH9_8814B BIT(11) +#define BIT_STOP_ACH8_8814B BIT(10) +#define BIT_STOP_ACH7_8814B BIT(9) +#define BIT_STOP_ACH6_8814B BIT(8) +#define BIT_STOP_ACH5_8814B BIT(7) +#define BIT_STOP_ACH4_8814B BIT(6) +#define BIT_STOP_ACH3_8814B BIT(5) +#define BIT_STOP_ACH2_8814B BIT(4) +#define BIT_STOP_ACH1_8814B BIT(3) +#define BIT_STOP_ACH0_8814B BIT(2) +#define BIT_STOP_P0RX_8814B BIT(0) + +/* 2 REG_HIQ_CTRL_8814B */ +#define BIT_STOP_P0HIQ15_8814B BIT(15) +#define BIT_STOP_P0HIQ14_8814B BIT(14) +#define BIT_STOP_P0HIQ13_8814B BIT(13) +#define BIT_STOP_P0HIQ12_8814B BIT(12) +#define BIT_STOP_P0HIQ11_8814B BIT(11) +#define BIT_STOP_P0HIQ10_8814B BIT(10) +#define BIT_STOP_P0HIQ9_8814B BIT(9) +#define BIT_STOP_P0HIQ8_8814B BIT(8) +#define BIT_STOP_P0HIQ7_8814B BIT(7) +#define BIT_STOP_P0HIQ6_8814B BIT(6) +#define BIT_STOP_P0HIQ5_8814B BIT(5) +#define BIT_STOP_P0HIQ4_8814B BIT(4) +#define BIT_STOP_P0HIQ3_8814B BIT(3) +#define BIT_STOP_P0HIQ2_8814B BIT(2) +#define BIT_STOP_P0HIQ1_8814B BIT(1) +#define BIT_STOP_P0HIQ0_8814B BIT(0) + +/* 2 REG_INT_MIG_V1_8814B */ #define BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B 28 #define BIT_MASK_TXTTIMER_MATCH_NUM_8814B 0xf -#define BIT_TXTTIMER_MATCH_NUM_8814B(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8814B) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) -#define BIT_GET_TXTTIMER_MATCH_NUM_8814B(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) & BIT_MASK_TXTTIMER_MATCH_NUM_8814B) - - +#define BIT_TXTTIMER_MATCH_NUM_8814B(x) \ + (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8814B) \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) +#define BITS_TXTTIMER_MATCH_NUM_8814B \ + (BIT_MASK_TXTTIMER_MATCH_NUM_8814B \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) +#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8814B(x) \ + ((x) & (~BITS_TXTTIMER_MATCH_NUM_8814B)) +#define BIT_GET_TXTTIMER_MATCH_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) & \ + BIT_MASK_TXTTIMER_MATCH_NUM_8814B) +#define BIT_SET_TXTTIMER_MATCH_NUM_8814B(x, v) \ + (BIT_CLEAR_TXTTIMER_MATCH_NUM_8814B(x) | \ + BIT_TXTTIMER_MATCH_NUM_8814B(v)) #define BIT_SHIFT_TXPKT_NUM_MATCH_8814B 24 #define BIT_MASK_TXPKT_NUM_MATCH_8814B 0xf -#define BIT_TXPKT_NUM_MATCH_8814B(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8814B) << BIT_SHIFT_TXPKT_NUM_MATCH_8814B) -#define BIT_GET_TXPKT_NUM_MATCH_8814B(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8814B) & BIT_MASK_TXPKT_NUM_MATCH_8814B) - - +#define BIT_TXPKT_NUM_MATCH_8814B(x) \ + (((x) & BIT_MASK_TXPKT_NUM_MATCH_8814B) \ + << BIT_SHIFT_TXPKT_NUM_MATCH_8814B) +#define BITS_TXPKT_NUM_MATCH_8814B \ + (BIT_MASK_TXPKT_NUM_MATCH_8814B << BIT_SHIFT_TXPKT_NUM_MATCH_8814B) +#define BIT_CLEAR_TXPKT_NUM_MATCH_8814B(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8814B)) +#define BIT_GET_TXPKT_NUM_MATCH_8814B(x) \ + (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8814B) & \ + BIT_MASK_TXPKT_NUM_MATCH_8814B) +#define BIT_SET_TXPKT_NUM_MATCH_8814B(x, v) \ + (BIT_CLEAR_TXPKT_NUM_MATCH_8814B(x) | BIT_TXPKT_NUM_MATCH_8814B(v)) #define BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B 20 #define BIT_MASK_RXTTIMER_MATCH_NUM_8814B 0xf -#define BIT_RXTTIMER_MATCH_NUM_8814B(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8814B) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) -#define BIT_GET_RXTTIMER_MATCH_NUM_8814B(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) & BIT_MASK_RXTTIMER_MATCH_NUM_8814B) - - +#define BIT_RXTTIMER_MATCH_NUM_8814B(x) \ + (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8814B) \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) +#define BITS_RXTTIMER_MATCH_NUM_8814B \ + (BIT_MASK_RXTTIMER_MATCH_NUM_8814B \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) +#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8814B(x) \ + ((x) & (~BITS_RXTTIMER_MATCH_NUM_8814B)) +#define BIT_GET_RXTTIMER_MATCH_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) & \ + BIT_MASK_RXTTIMER_MATCH_NUM_8814B) +#define BIT_SET_RXTTIMER_MATCH_NUM_8814B(x, v) \ + (BIT_CLEAR_RXTTIMER_MATCH_NUM_8814B(x) | \ + BIT_RXTTIMER_MATCH_NUM_8814B(v)) #define BIT_SHIFT_RXPKT_NUM_MATCH_8814B 16 #define BIT_MASK_RXPKT_NUM_MATCH_8814B 0xf -#define BIT_RXPKT_NUM_MATCH_8814B(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8814B) << BIT_SHIFT_RXPKT_NUM_MATCH_8814B) -#define BIT_GET_RXPKT_NUM_MATCH_8814B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8814B) & BIT_MASK_RXPKT_NUM_MATCH_8814B) - - +#define BIT_RXPKT_NUM_MATCH_8814B(x) \ + (((x) & BIT_MASK_RXPKT_NUM_MATCH_8814B) \ + << BIT_SHIFT_RXPKT_NUM_MATCH_8814B) +#define BITS_RXPKT_NUM_MATCH_8814B \ + (BIT_MASK_RXPKT_NUM_MATCH_8814B << BIT_SHIFT_RXPKT_NUM_MATCH_8814B) +#define BIT_CLEAR_RXPKT_NUM_MATCH_8814B(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8814B)) +#define BIT_GET_RXPKT_NUM_MATCH_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8814B) & \ + BIT_MASK_RXPKT_NUM_MATCH_8814B) +#define BIT_SET_RXPKT_NUM_MATCH_8814B(x, v) \ + (BIT_CLEAR_RXPKT_NUM_MATCH_8814B(x) | BIT_RXPKT_NUM_MATCH_8814B(v)) #define BIT_SHIFT_MIGRATE_TIMER_8814B 0 #define BIT_MASK_MIGRATE_TIMER_8814B 0xffff -#define BIT_MIGRATE_TIMER_8814B(x) (((x) & BIT_MASK_MIGRATE_TIMER_8814B) << BIT_SHIFT_MIGRATE_TIMER_8814B) -#define BIT_GET_MIGRATE_TIMER_8814B(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8814B) & BIT_MASK_MIGRATE_TIMER_8814B) - +#define BIT_MIGRATE_TIMER_8814B(x) \ + (((x) & BIT_MASK_MIGRATE_TIMER_8814B) << BIT_SHIFT_MIGRATE_TIMER_8814B) +#define BITS_MIGRATE_TIMER_8814B \ + (BIT_MASK_MIGRATE_TIMER_8814B << BIT_SHIFT_MIGRATE_TIMER_8814B) +#define BIT_CLEAR_MIGRATE_TIMER_8814B(x) ((x) & (~BITS_MIGRATE_TIMER_8814B)) +#define BIT_GET_MIGRATE_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_MIGRATE_TIMER_8814B) & BIT_MASK_MIGRATE_TIMER_8814B) +#define BIT_SET_MIGRATE_TIMER_8814B(x, v) \ + (BIT_CLEAR_MIGRATE_TIMER_8814B(x) | BIT_MIGRATE_TIMER_8814B(v)) + +/* 2 REG_P0MGQ_TXBD_DESA_L_8814B */ + +/* 2 REG_P0MGQ_TXBD_DESA_H_8814B */ + +/* 2 REG_ACH0_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH0_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH0_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH0_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH0_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH0_TXBD_DESA_L_8814B) +#define BITS_ACH0_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH0_TXBD_DESA_L_8814B << BIT_SHIFT_ACH0_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH0_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH0_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH0_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH0_TXBD_DESA_L_8814B) +#define BIT_SET_ACH0_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH0_TXBD_DESA_L_8814B(x) | BIT_ACH0_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH0_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH0_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH0_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH0_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH0_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH0_TXBD_DESA_H_8814B) +#define BITS_ACH0_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH0_TXBD_DESA_H_8814B << BIT_SHIFT_ACH0_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH0_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH0_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH0_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH0_TXBD_DESA_H_8814B) +#define BIT_SET_ACH0_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH0_TXBD_DESA_H_8814B(x) | BIT_ACH0_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH1_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH1_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH1_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH1_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH1_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH1_TXBD_DESA_L_8814B) +#define BITS_ACH1_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH1_TXBD_DESA_L_8814B << BIT_SHIFT_ACH1_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH1_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH1_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH1_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH1_TXBD_DESA_L_8814B) +#define BIT_SET_ACH1_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH1_TXBD_DESA_L_8814B(x) | BIT_ACH1_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH1_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH1_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH1_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH1_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH1_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH1_TXBD_DESA_H_8814B) +#define BITS_ACH1_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH1_TXBD_DESA_H_8814B << BIT_SHIFT_ACH1_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH1_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH1_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH1_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH1_TXBD_DESA_H_8814B) +#define BIT_SET_ACH1_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH1_TXBD_DESA_H_8814B(x) | BIT_ACH1_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH2_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH2_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH2_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH2_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH2_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH2_TXBD_DESA_L_8814B) +#define BITS_ACH2_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH2_TXBD_DESA_L_8814B << BIT_SHIFT_ACH2_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH2_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH2_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH2_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH2_TXBD_DESA_L_8814B) +#define BIT_SET_ACH2_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH2_TXBD_DESA_L_8814B(x) | BIT_ACH2_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH2_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH2_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH2_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH2_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH2_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH2_TXBD_DESA_H_8814B) +#define BITS_ACH2_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH2_TXBD_DESA_H_8814B << BIT_SHIFT_ACH2_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH2_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH2_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH2_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH2_TXBD_DESA_H_8814B) +#define BIT_SET_ACH2_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH2_TXBD_DESA_H_8814B(x) | BIT_ACH2_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH3_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH3_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH3_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH3_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH3_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH3_TXBD_DESA_L_8814B) +#define BITS_ACH3_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH3_TXBD_DESA_L_8814B << BIT_SHIFT_ACH3_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH3_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH3_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH3_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH3_TXBD_DESA_L_8814B) +#define BIT_SET_ACH3_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH3_TXBD_DESA_L_8814B(x) | BIT_ACH3_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH3_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH3_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH3_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH3_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH3_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH3_TXBD_DESA_H_8814B) +#define BITS_ACH3_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH3_TXBD_DESA_H_8814B << BIT_SHIFT_ACH3_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH3_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH3_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH3_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH3_TXBD_DESA_H_8814B) +#define BIT_SET_ACH3_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH3_TXBD_DESA_H_8814B(x) | BIT_ACH3_TXBD_DESA_H_8814B(v)) + +/* 2 REG_P0RXQ_RXBD_DESA_L_8814B */ + +#define BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B 0 +#define BIT_MASK_P0RXQ_RXBD_DESA_L_8814B 0xffffffffL +#define BIT_P0RXQ_RXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_P0RXQ_RXBD_DESA_L_8814B) \ + << BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B) +#define BITS_P0RXQ_RXBD_DESA_L_8814B \ + (BIT_MASK_P0RXQ_RXBD_DESA_L_8814B << BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B) +#define BIT_CLEAR_P0RXQ_RXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_P0RXQ_RXBD_DESA_L_8814B)) +#define BIT_GET_P0RXQ_RXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B) & \ + BIT_MASK_P0RXQ_RXBD_DESA_L_8814B) +#define BIT_SET_P0RXQ_RXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_P0RXQ_RXBD_DESA_L_8814B(x) | BIT_P0RXQ_RXBD_DESA_L_8814B(v)) + +/* 2 REG_P0RXQ_RXBD_DESA_H_8814B */ + +#define BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B 0 +#define BIT_MASK_P0RXQ_RXBD_DESA_H_8814B 0xffffffffL +#define BIT_P0RXQ_RXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_P0RXQ_RXBD_DESA_H_8814B) \ + << BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B) +#define BITS_P0RXQ_RXBD_DESA_H_8814B \ + (BIT_MASK_P0RXQ_RXBD_DESA_H_8814B << BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B) +#define BIT_CLEAR_P0RXQ_RXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_P0RXQ_RXBD_DESA_H_8814B)) +#define BIT_GET_P0RXQ_RXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B) & \ + BIT_MASK_P0RXQ_RXBD_DESA_H_8814B) +#define BIT_SET_P0RXQ_RXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_P0RXQ_RXBD_DESA_H_8814B(x) | BIT_P0RXQ_RXBD_DESA_H_8814B(v)) + +/* 2 REG_P0BCNQ_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B 0 +#define BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_P0BCNQ_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B) +#define BITS_P0BCNQ_TXBD_DESA_L_8814B \ + (BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B \ + << BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B) +#define BIT_CLEAR_P0BCNQ_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_P0BCNQ_TXBD_DESA_L_8814B)) +#define BIT_GET_P0BCNQ_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B) & \ + BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B) +#define BIT_SET_P0BCNQ_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_P0BCNQ_TXBD_DESA_L_8814B(x) | \ + BIT_P0BCNQ_TXBD_DESA_L_8814B(v)) + +/* 2 REG_P0BCNQ_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B 0 +#define BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_P0BCNQ_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B) +#define BITS_P0BCNQ_TXBD_DESA_H_8814B \ + (BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B \ + << BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B) +#define BIT_CLEAR_P0BCNQ_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_P0BCNQ_TXBD_DESA_H_8814B)) +#define BIT_GET_P0BCNQ_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B) & \ + BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B) +#define BIT_SET_P0BCNQ_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_P0BCNQ_TXBD_DESA_H_8814B(x) | \ + BIT_P0BCNQ_TXBD_DESA_H_8814B(v)) + +/* 2 REG_FWCMDQ_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B 0 +#define BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_FWCMDQ_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B) +#define BITS_FWCMDQ_TXBD_DESA_L_8814B \ + (BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B \ + << BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B) +#define BIT_CLEAR_FWCMDQ_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_FWCMDQ_TXBD_DESA_L_8814B)) +#define BIT_GET_FWCMDQ_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B) & \ + BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B) +#define BIT_SET_FWCMDQ_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_TXBD_DESA_L_8814B(x) | \ + BIT_FWCMDQ_TXBD_DESA_L_8814B(v)) + +/* 2 REG_FWCMDQ_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B 0 +#define BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_FWCMDQ_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B) +#define BITS_FWCMDQ_TXBD_DESA_H_8814B \ + (BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B \ + << BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B) +#define BIT_CLEAR_FWCMDQ_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_FWCMDQ_TXBD_DESA_H_8814B)) +#define BIT_GET_FWCMDQ_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B) & \ + BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B) +#define BIT_SET_FWCMDQ_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_TXBD_DESA_H_8814B(x) | \ + BIT_FWCMDQ_TXBD_DESA_H_8814B(v)) + +/* 2 REG_PCIE_HRPWM1_HCPWM1_DCPU_8814B */ + +#define BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B 16 +#define BIT_MASK_PCIE_HCPWM1_DCPU_8814B 0xff +#define BIT_PCIE_HCPWM1_DCPU_8814B(x) \ + (((x) & BIT_MASK_PCIE_HCPWM1_DCPU_8814B) \ + << BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B) +#define BITS_PCIE_HCPWM1_DCPU_8814B \ + (BIT_MASK_PCIE_HCPWM1_DCPU_8814B << BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B) +#define BIT_CLEAR_PCIE_HCPWM1_DCPU_8814B(x) \ + ((x) & (~BITS_PCIE_HCPWM1_DCPU_8814B)) +#define BIT_GET_PCIE_HCPWM1_DCPU_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B) & \ + BIT_MASK_PCIE_HCPWM1_DCPU_8814B) +#define BIT_SET_PCIE_HCPWM1_DCPU_8814B(x, v) \ + (BIT_CLEAR_PCIE_HCPWM1_DCPU_8814B(x) | BIT_PCIE_HCPWM1_DCPU_8814B(v)) + +#define BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B 8 +#define BIT_MASK_PCIE_HRPWM1_DCPU_8814B 0xff +#define BIT_PCIE_HRPWM1_DCPU_8814B(x) \ + (((x) & BIT_MASK_PCIE_HRPWM1_DCPU_8814B) \ + << BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B) +#define BITS_PCIE_HRPWM1_DCPU_8814B \ + (BIT_MASK_PCIE_HRPWM1_DCPU_8814B << BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B) +#define BIT_CLEAR_PCIE_HRPWM1_DCPU_8814B(x) \ + ((x) & (~BITS_PCIE_HRPWM1_DCPU_8814B)) +#define BIT_GET_PCIE_HRPWM1_DCPU_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B) & \ + BIT_MASK_PCIE_HRPWM1_DCPU_8814B) +#define BIT_SET_PCIE_HRPWM1_DCPU_8814B(x, v) \ + (BIT_CLEAR_PCIE_HRPWM1_DCPU_8814B(x) | BIT_PCIE_HRPWM1_DCPU_8814B(v)) + +/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0 +#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) +#define BITS_P0_MPRT_BCNQ_TXBD_DESA_L_8814B \ + (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) +#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)) +#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) & \ + BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) +#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) | \ + BIT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(v)) + +/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0 +#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) +#define BITS_P0_MPRT_BCNQ_TXBD_DESA_H_8814B \ + (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B \ + << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) +#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)) +#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) & \ + BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) +#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) | \ + BIT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(v)) + +/* 2 REG_P0_MPRT_BCNQ_TXRXBD_NUM_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BCNQ_TXBD_DESA_8814B */ +#define BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B 13 +#define BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B 0x3 +#define BIT_P0_MPRT_BCNQ_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B) \ + << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B) +#define BITS_P0_MPRT_BCNQ_DESC_MODE_8814B \ + (BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B \ + << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B) +#define BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0_MPRT_BCNQ_DESC_MODE_8814B)) +#define BIT_GET_P0_MPRT_BCNQ_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B) & \ + BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B) +#define BIT_SET_P0_MPRT_BCNQ_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE_8814B(x) | \ + BIT_P0_MPRT_BCNQ_DESC_MODE_8814B(v)) + +#define BIT_PCIE_P0MPRT_BCNQ4_FLAG_8814B BIT(11) +#define BIT_PCIE_P0MPRT_BCNQ3_FLAG_8814B BIT(10) +#define BIT_PCIE_P0MPRT_BCNQ2_FLAG_8814B BIT(9) +#define BIT_PCIE_P0MPRT_BCNQ1_FLAG_8814B BIT(8) +#define BIT_EPHY_CAL_DONE_8814B BIT(1) +#define BIT_RESET_APHY_8814B BIT(0) + +/* 2 REG_BD_RWPTR_CLR2_8814B */ -#define BIT_SHIFT_BCNQ_TXBD_DESA_8814B 0 -#define BIT_MASK_BCNQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_BCNQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8814B) << BIT_SHIFT_BCNQ_TXBD_DESA_8814B) -#define BIT_GET_BCNQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8814B) & BIT_MASK_BCNQ_TXBD_DESA_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_ACH7_HW_IDX_8814B BIT(21) +#define BIT_CLR_ACH6_HW_IDX_8814B BIT(20) +#define BIT_CLR_ACH5_HW_IDX_8814B BIT(19) +#define BIT_CLR_ACH4_HW_IDX_8814B BIT(18) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_ACH7_HOST_IDX_8814B BIT(5) +#define BIT_CLR_ACH6_HOST_IDX_8814B BIT(4) +#define BIT_CLR_ACH5_HOST_IDX_8814B BIT(3) +#define BIT_CLR_ACH4_HOST_IDX_8814B BIT(2) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_MGQ_TXBD_DESA_8814B */ +/* 2 REG_BD_RWPTR_CLR3_8814B */ -#define BIT_SHIFT_MGQ_TXBD_DESA_8814B 0 -#define BIT_MASK_MGQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_MGQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8814B) << BIT_SHIFT_MGQ_TXBD_DESA_8814B) -#define BIT_GET_MGQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8814B) & BIT_MASK_MGQ_TXBD_DESA_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_P0HI15Q_HW_IDX_8814B BIT(29) +#define BIT_CLR_P0HI14Q_HW_IDX_8814B BIT(28) +#define BIT_CLR_P0HI13Q_HW_IDX_8814B BIT(27) +#define BIT_CLR_P0HI12Q_HW_IDX_8814B BIT(26) +#define BIT_CLR_P0HI11Q_HW_IDX_8814B BIT(25) +#define BIT_CLR_P0HI10Q_HW_IDX_8814B BIT(24) +#define BIT_CLR_P0HI9Q_HW_IDX_8814B BIT(23) +#define BIT_CLR_P0HI8Q_HW_IDX_8814B BIT(22) +#define BIT_CLR_ACH13_HW_IDX_8814B BIT(21) +#define BIT_CLR_ACH12_HW_IDX_8814B BIT(20) +#define BIT_CLR_ACH11_HW_IDX_8814B BIT(19) +#define BIT_CLR_ACH10_HW_IDX_8814B BIT(18) +#define BIT_CLR_ACH9_HW_IDX_8814B BIT(17) +#define BIT_CLR_ACH8_HW_IDX_8814B BIT(16) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_P0HI15Q_HOST_IDX_8814B BIT(13) +#define BIT_CLR_P0HI14Q_HOST_IDX_8814B BIT(12) +#define BIT_CLR_P0HI13Q_HOST_IDX_8814B BIT(11) +#define BIT_CLR_P0HI12Q_HOST_IDX_8814B BIT(10) +#define BIT_CLR_P0HI11Q_HOST_IDX_8814B BIT(9) +#define BIT_CLR_P0HI10Q_HOST_IDX_8814B BIT(8) +#define BIT_CLR_P0HI9Q_HOST_IDX_8814B BIT(7) +#define BIT_CLR_P0HI8Q_HOST_IDX_8814B BIT(6) +#define BIT_CLR_ACH13_HOST_IDX_8814B BIT(5) +#define BIT_CLR_ACH12_HOST_IDX_8814B BIT(4) +#define BIT_CLR_ACH11_HOST_IDX_8814B BIT(3) +#define BIT_CLR_ACH10_HOST_IDX_8814B BIT(2) +#define BIT_CLR_ACH9_HOST_IDX_8814B BIT(1) +#define BIT_CLR_ACH8_HOST_IDX_8814B BIT(0) + +/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM_8814B */ +#define BIT_SYS_32_64_V1_8814B BIT(31) + +#define BIT_SHIFT_P0BCNQ_DESC_MODE_8814B 29 +#define BIT_MASK_P0BCNQ_DESC_MODE_8814B 0x3 +#define BIT_P0BCNQ_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0BCNQ_DESC_MODE_8814B) \ + << BIT_SHIFT_P0BCNQ_DESC_MODE_8814B) +#define BITS_P0BCNQ_DESC_MODE_8814B \ + (BIT_MASK_P0BCNQ_DESC_MODE_8814B << BIT_SHIFT_P0BCNQ_DESC_MODE_8814B) +#define BIT_CLEAR_P0BCNQ_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0BCNQ_DESC_MODE_8814B)) +#define BIT_GET_P0BCNQ_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0BCNQ_DESC_MODE_8814B) & \ + BIT_MASK_P0BCNQ_DESC_MODE_8814B) +#define BIT_SET_P0BCNQ_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0BCNQ_DESC_MODE_8814B(x) | BIT_P0BCNQ_DESC_MODE_8814B(v)) + +#define BIT_PCIE_P0BCNQ_FLAG_8814B BIT(28) + +#define BIT_SHIFT_P0RXQ_DESC_NUM_8814B 16 +#define BIT_MASK_P0RXQ_DESC_NUM_8814B 0xfff +#define BIT_P0RXQ_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0RXQ_DESC_NUM_8814B) \ + << BIT_SHIFT_P0RXQ_DESC_NUM_8814B) +#define BITS_P0RXQ_DESC_NUM_8814B \ + (BIT_MASK_P0RXQ_DESC_NUM_8814B << BIT_SHIFT_P0RXQ_DESC_NUM_8814B) +#define BIT_CLEAR_P0RXQ_DESC_NUM_8814B(x) ((x) & (~BITS_P0RXQ_DESC_NUM_8814B)) +#define BIT_GET_P0RXQ_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0RXQ_DESC_NUM_8814B) & \ + BIT_MASK_P0RXQ_DESC_NUM_8814B) +#define BIT_SET_P0RXQ_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0RXQ_DESC_NUM_8814B(x) | BIT_P0RXQ_DESC_NUM_8814B(v)) + +#define BIT_PCIE_P0MGQ_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0MGQ_DESC_MODE_8814B 12 +#define BIT_MASK_P0MGQ_DESC_MODE_8814B 0x3 +#define BIT_P0MGQ_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0MGQ_DESC_MODE_8814B) \ + << BIT_SHIFT_P0MGQ_DESC_MODE_8814B) +#define BITS_P0MGQ_DESC_MODE_8814B \ + (BIT_MASK_P0MGQ_DESC_MODE_8814B << BIT_SHIFT_P0MGQ_DESC_MODE_8814B) +#define BIT_CLEAR_P0MGQ_DESC_MODE_8814B(x) ((x) & (~BITS_P0MGQ_DESC_MODE_8814B)) +#define BIT_GET_P0MGQ_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0MGQ_DESC_MODE_8814B) & \ + BIT_MASK_P0MGQ_DESC_MODE_8814B) +#define BIT_SET_P0MGQ_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0MGQ_DESC_MODE_8814B(x) | BIT_P0MGQ_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0MGQ_DESC_NUM_8814B 0 +#define BIT_MASK_P0MGQ_DESC_NUM_8814B 0xfff +#define BIT_P0MGQ_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0MGQ_DESC_NUM_8814B) \ + << BIT_SHIFT_P0MGQ_DESC_NUM_8814B) +#define BITS_P0MGQ_DESC_NUM_8814B \ + (BIT_MASK_P0MGQ_DESC_NUM_8814B << BIT_SHIFT_P0MGQ_DESC_NUM_8814B) +#define BIT_CLEAR_P0MGQ_DESC_NUM_8814B(x) ((x) & (~BITS_P0MGQ_DESC_NUM_8814B)) +#define BIT_GET_P0MGQ_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0MGQ_DESC_NUM_8814B) & \ + BIT_MASK_P0MGQ_DESC_NUM_8814B) +#define BIT_SET_P0MGQ_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0MGQ_DESC_NUM_8814B(x) | BIT_P0MGQ_DESC_NUM_8814B(v)) + +/* 2 REG_CHNL_DMA_CFG_8814B */ +#define BIT_TXHCI_EN_8814B BIT(26) +#define BIT_TXHCI_IDLE_8814B BIT(25) +#define BIT_DMA_PRI_EN_8814B BIT(24) + +/* 2 REG_FWCMDQ_TXBD_NUM_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_PCIE_FWCMDQ_FLAG_8814B BIT(14) + +#define BIT_SHIFT_FWCMDQ_DESC_MODE_8814B 12 +#define BIT_MASK_FWCMDQ_DESC_MODE_8814B 0x3 +#define BIT_FWCMDQ_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_DESC_MODE_8814B) \ + << BIT_SHIFT_FWCMDQ_DESC_MODE_8814B) +#define BITS_FWCMDQ_DESC_MODE_8814B \ + (BIT_MASK_FWCMDQ_DESC_MODE_8814B << BIT_SHIFT_FWCMDQ_DESC_MODE_8814B) +#define BIT_CLEAR_FWCMDQ_DESC_MODE_8814B(x) \ + ((x) & (~BITS_FWCMDQ_DESC_MODE_8814B)) +#define BIT_GET_FWCMDQ_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_DESC_MODE_8814B) & \ + BIT_MASK_FWCMDQ_DESC_MODE_8814B) +#define BIT_SET_FWCMDQ_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_DESC_MODE_8814B(x) | BIT_FWCMDQ_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_FWCMDQ_DESC_NUM_8814B 0 +#define BIT_MASK_FWCMDQ_DESC_NUM_8814B 0xfff +#define BIT_FWCMDQ_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_DESC_NUM_8814B) \ + << BIT_SHIFT_FWCMDQ_DESC_NUM_8814B) +#define BITS_FWCMDQ_DESC_NUM_8814B \ + (BIT_MASK_FWCMDQ_DESC_NUM_8814B << BIT_SHIFT_FWCMDQ_DESC_NUM_8814B) +#define BIT_CLEAR_FWCMDQ_DESC_NUM_8814B(x) ((x) & (~BITS_FWCMDQ_DESC_NUM_8814B)) +#define BIT_GET_FWCMDQ_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_DESC_NUM_8814B) & \ + BIT_MASK_FWCMDQ_DESC_NUM_8814B) +#define BIT_SET_FWCMDQ_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_DESC_NUM_8814B(x) | BIT_FWCMDQ_DESC_NUM_8814B(v)) + +/* 2 REG_ACH0_ACH1_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH1_FLAG_V1_8814B BIT(30) + +#define BIT_SHIFT_ACH1_DESC_MODE_V1_8814B 28 +#define BIT_MASK_ACH1_DESC_MODE_V1_8814B 0x3 +#define BIT_ACH1_DESC_MODE_V1_8814B(x) \ + (((x) & BIT_MASK_ACH1_DESC_MODE_V1_8814B) \ + << BIT_SHIFT_ACH1_DESC_MODE_V1_8814B) +#define BITS_ACH1_DESC_MODE_V1_8814B \ + (BIT_MASK_ACH1_DESC_MODE_V1_8814B << BIT_SHIFT_ACH1_DESC_MODE_V1_8814B) +#define BIT_CLEAR_ACH1_DESC_MODE_V1_8814B(x) \ + ((x) & (~BITS_ACH1_DESC_MODE_V1_8814B)) +#define BIT_GET_ACH1_DESC_MODE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_DESC_MODE_V1_8814B) & \ + BIT_MASK_ACH1_DESC_MODE_V1_8814B) +#define BIT_SET_ACH1_DESC_MODE_V1_8814B(x, v) \ + (BIT_CLEAR_ACH1_DESC_MODE_V1_8814B(x) | BIT_ACH1_DESC_MODE_V1_8814B(v)) + +#define BIT_SHIFT_ACH1_DESC_NUM_V1_8814B 16 +#define BIT_MASK_ACH1_DESC_NUM_V1_8814B 0xfff +#define BIT_ACH1_DESC_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_ACH1_DESC_NUM_V1_8814B) \ + << BIT_SHIFT_ACH1_DESC_NUM_V1_8814B) +#define BITS_ACH1_DESC_NUM_V1_8814B \ + (BIT_MASK_ACH1_DESC_NUM_V1_8814B << BIT_SHIFT_ACH1_DESC_NUM_V1_8814B) +#define BIT_CLEAR_ACH1_DESC_NUM_V1_8814B(x) \ + ((x) & (~BITS_ACH1_DESC_NUM_V1_8814B)) +#define BIT_GET_ACH1_DESC_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_DESC_NUM_V1_8814B) & \ + BIT_MASK_ACH1_DESC_NUM_V1_8814B) +#define BIT_SET_ACH1_DESC_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_ACH1_DESC_NUM_V1_8814B(x) | BIT_ACH1_DESC_NUM_V1_8814B(v)) + +#define BIT_PCIE_ACH0_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH0_DESC_MODE_8814B 12 +#define BIT_MASK_ACH0_DESC_MODE_8814B 0x3 +#define BIT_ACH0_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH0_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH0_DESC_MODE_8814B) +#define BITS_ACH0_DESC_MODE_8814B \ + (BIT_MASK_ACH0_DESC_MODE_8814B << BIT_SHIFT_ACH0_DESC_MODE_8814B) +#define BIT_CLEAR_ACH0_DESC_MODE_8814B(x) ((x) & (~BITS_ACH0_DESC_MODE_8814B)) +#define BIT_GET_ACH0_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_DESC_MODE_8814B) & \ + BIT_MASK_ACH0_DESC_MODE_8814B) +#define BIT_SET_ACH0_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH0_DESC_MODE_8814B(x) | BIT_ACH0_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH0_DESC_NUM_8814B 0 +#define BIT_MASK_ACH0_DESC_NUM_8814B 0xfff +#define BIT_ACH0_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH0_DESC_NUM_8814B) << BIT_SHIFT_ACH0_DESC_NUM_8814B) +#define BITS_ACH0_DESC_NUM_8814B \ + (BIT_MASK_ACH0_DESC_NUM_8814B << BIT_SHIFT_ACH0_DESC_NUM_8814B) +#define BIT_CLEAR_ACH0_DESC_NUM_8814B(x) ((x) & (~BITS_ACH0_DESC_NUM_8814B)) +#define BIT_GET_ACH0_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_DESC_NUM_8814B) & BIT_MASK_ACH0_DESC_NUM_8814B) +#define BIT_SET_ACH0_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH0_DESC_NUM_8814B(x) | BIT_ACH0_DESC_NUM_8814B(v)) + +/* 2 REG_ACH2_ACH3_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH3_FLAG_V1_8814B BIT(30) + +#define BIT_SHIFT_ACH3_DESC_MODE_V1_8814B 28 +#define BIT_MASK_ACH3_DESC_MODE_V1_8814B 0x3 +#define BIT_ACH3_DESC_MODE_V1_8814B(x) \ + (((x) & BIT_MASK_ACH3_DESC_MODE_V1_8814B) \ + << BIT_SHIFT_ACH3_DESC_MODE_V1_8814B) +#define BITS_ACH3_DESC_MODE_V1_8814B \ + (BIT_MASK_ACH3_DESC_MODE_V1_8814B << BIT_SHIFT_ACH3_DESC_MODE_V1_8814B) +#define BIT_CLEAR_ACH3_DESC_MODE_V1_8814B(x) \ + ((x) & (~BITS_ACH3_DESC_MODE_V1_8814B)) +#define BIT_GET_ACH3_DESC_MODE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_DESC_MODE_V1_8814B) & \ + BIT_MASK_ACH3_DESC_MODE_V1_8814B) +#define BIT_SET_ACH3_DESC_MODE_V1_8814B(x, v) \ + (BIT_CLEAR_ACH3_DESC_MODE_V1_8814B(x) | BIT_ACH3_DESC_MODE_V1_8814B(v)) + +#define BIT_SHIFT_ACH3_DESC_NUM_V1_8814B 16 +#define BIT_MASK_ACH3_DESC_NUM_V1_8814B 0xfff +#define BIT_ACH3_DESC_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_ACH3_DESC_NUM_V1_8814B) \ + << BIT_SHIFT_ACH3_DESC_NUM_V1_8814B) +#define BITS_ACH3_DESC_NUM_V1_8814B \ + (BIT_MASK_ACH3_DESC_NUM_V1_8814B << BIT_SHIFT_ACH3_DESC_NUM_V1_8814B) +#define BIT_CLEAR_ACH3_DESC_NUM_V1_8814B(x) \ + ((x) & (~BITS_ACH3_DESC_NUM_V1_8814B)) +#define BIT_GET_ACH3_DESC_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_DESC_NUM_V1_8814B) & \ + BIT_MASK_ACH3_DESC_NUM_V1_8814B) +#define BIT_SET_ACH3_DESC_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_ACH3_DESC_NUM_V1_8814B(x) | BIT_ACH3_DESC_NUM_V1_8814B(v)) + +#define BIT_PCIE_ACH2_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH2_DESC_MODE_8814B 12 +#define BIT_MASK_ACH2_DESC_MODE_8814B 0x3 +#define BIT_ACH2_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH2_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH2_DESC_MODE_8814B) +#define BITS_ACH2_DESC_MODE_8814B \ + (BIT_MASK_ACH2_DESC_MODE_8814B << BIT_SHIFT_ACH2_DESC_MODE_8814B) +#define BIT_CLEAR_ACH2_DESC_MODE_8814B(x) ((x) & (~BITS_ACH2_DESC_MODE_8814B)) +#define BIT_GET_ACH2_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_DESC_MODE_8814B) & \ + BIT_MASK_ACH2_DESC_MODE_8814B) +#define BIT_SET_ACH2_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH2_DESC_MODE_8814B(x) | BIT_ACH2_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH2_DESC_NUM_8814B 0 +#define BIT_MASK_ACH2_DESC_NUM_8814B 0xfff +#define BIT_ACH2_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH2_DESC_NUM_8814B) << BIT_SHIFT_ACH2_DESC_NUM_8814B) +#define BITS_ACH2_DESC_NUM_8814B \ + (BIT_MASK_ACH2_DESC_NUM_8814B << BIT_SHIFT_ACH2_DESC_NUM_8814B) +#define BIT_CLEAR_ACH2_DESC_NUM_8814B(x) ((x) & (~BITS_ACH2_DESC_NUM_8814B)) +#define BIT_GET_ACH2_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_DESC_NUM_8814B) & BIT_MASK_ACH2_DESC_NUM_8814B) +#define BIT_SET_ACH2_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH2_DESC_NUM_8814B(x) | BIT_ACH2_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM_8814B */ +#define BIT_P0HI1Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI1Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI1Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI1Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI1Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI1Q_DESC_MODE_8814B) +#define BITS_P0HI1Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI1Q_DESC_MODE_8814B << BIT_SHIFT_P0HI1Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI1Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI1Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI1Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI1Q_DESC_MODE_8814B) +#define BIT_SET_P0HI1Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI1Q_DESC_MODE_8814B(x) | BIT_P0HI1Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI1Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI1Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI1Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI1Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI1Q_DESC_NUM_8814B) +#define BITS_P0HI1Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI1Q_DESC_NUM_8814B << BIT_SHIFT_P0HI1Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI1Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI1Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI1Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI1Q_DESC_NUM_8814B) +#define BIT_SET_P0HI1Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI1Q_DESC_NUM_8814B(x) | BIT_P0HI1Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI0Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI0Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI0Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI0Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI0Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI0Q_DESC_MODE_8814B) +#define BITS_P0HI0Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI0Q_DESC_MODE_8814B << BIT_SHIFT_P0HI0Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI0Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI0Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI0Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI0Q_DESC_MODE_8814B) +#define BIT_SET_P0HI0Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI0Q_DESC_MODE_8814B(x) | BIT_P0HI0Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI0Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI0Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI0Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI0Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI0Q_DESC_NUM_8814B) +#define BITS_P0HI0Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI0Q_DESC_NUM_8814B << BIT_SHIFT_P0HI0Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI0Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI0Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI0Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI0Q_DESC_NUM_8814B) +#define BIT_SET_P0HI0Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI0Q_DESC_NUM_8814B(x) | BIT_P0HI0Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM_8814B */ +#define BIT_P0HI3Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI3Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI3Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI3Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI3Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI3Q_DESC_MODE_8814B) +#define BITS_P0HI3Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI3Q_DESC_MODE_8814B << BIT_SHIFT_P0HI3Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI3Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI3Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI3Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI3Q_DESC_MODE_8814B) +#define BIT_SET_P0HI3Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI3Q_DESC_MODE_8814B(x) | BIT_P0HI3Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI3Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI3Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI3Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI3Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI3Q_DESC_NUM_8814B) +#define BITS_P0HI3Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI3Q_DESC_NUM_8814B << BIT_SHIFT_P0HI3Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI3Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI3Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI3Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI3Q_DESC_NUM_8814B) +#define BIT_SET_P0HI3Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI3Q_DESC_NUM_8814B(x) | BIT_P0HI3Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI2Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI2Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI2Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI2Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI2Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI2Q_DESC_MODE_8814B) +#define BITS_P0HI2Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI2Q_DESC_MODE_8814B << BIT_SHIFT_P0HI2Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI2Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI2Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI2Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI2Q_DESC_MODE_8814B) +#define BIT_SET_P0HI2Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI2Q_DESC_MODE_8814B(x) | BIT_P0HI2Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI2Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI2Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI2Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI2Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI2Q_DESC_NUM_8814B) +#define BITS_P0HI2Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI2Q_DESC_NUM_8814B << BIT_SHIFT_P0HI2Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI2Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI2Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI2Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI2Q_DESC_NUM_8814B) +#define BIT_SET_P0HI2Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI2Q_DESC_NUM_8814B(x) | BIT_P0HI2Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM_8814B */ +#define BIT_P0HI5Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI5Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI5Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI5Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI5Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI5Q_DESC_MODE_8814B) +#define BITS_P0HI5Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI5Q_DESC_MODE_8814B << BIT_SHIFT_P0HI5Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI5Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI5Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI5Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI5Q_DESC_MODE_8814B) +#define BIT_SET_P0HI5Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI5Q_DESC_MODE_8814B(x) | BIT_P0HI5Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI5Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI5Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI5Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI5Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI5Q_DESC_NUM_8814B) +#define BITS_P0HI5Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI5Q_DESC_NUM_8814B << BIT_SHIFT_P0HI5Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI5Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI5Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI5Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI5Q_DESC_NUM_8814B) +#define BIT_SET_P0HI5Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI5Q_DESC_NUM_8814B(x) | BIT_P0HI5Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI4Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI4Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI4Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI4Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI4Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI4Q_DESC_MODE_8814B) +#define BITS_P0HI4Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI4Q_DESC_MODE_8814B << BIT_SHIFT_P0HI4Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI4Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI4Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI4Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI4Q_DESC_MODE_8814B) +#define BIT_SET_P0HI4Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI4Q_DESC_MODE_8814B(x) | BIT_P0HI4Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI4Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI4Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI4Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI4Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI4Q_DESC_NUM_8814B) +#define BITS_P0HI4Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI4Q_DESC_NUM_8814B << BIT_SHIFT_P0HI4Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI4Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI4Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI4Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI4Q_DESC_NUM_8814B) +#define BIT_SET_P0HI4Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI4Q_DESC_NUM_8814B(x) | BIT_P0HI4Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM_8814B */ +#define BIT_P0HI7Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI7Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI7Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI7Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI7Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI7Q_DESC_MODE_8814B) +#define BITS_P0HI7Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI7Q_DESC_MODE_8814B << BIT_SHIFT_P0HI7Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI7Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI7Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI7Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI7Q_DESC_MODE_8814B) +#define BIT_SET_P0HI7Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI7Q_DESC_MODE_8814B(x) | BIT_P0HI7Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI7Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI7Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI7Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI7Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI7Q_DESC_NUM_8814B) +#define BITS_P0HI7Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI7Q_DESC_NUM_8814B << BIT_SHIFT_P0HI7Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI7Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI7Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI7Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI7Q_DESC_NUM_8814B) +#define BIT_SET_P0HI7Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI7Q_DESC_NUM_8814B(x) | BIT_P0HI7Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI6Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI6Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI6Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI6Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI6Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI6Q_DESC_MODE_8814B) +#define BITS_P0HI6Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI6Q_DESC_MODE_8814B << BIT_SHIFT_P0HI6Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI6Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI6Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI6Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI6Q_DESC_MODE_8814B) +#define BIT_SET_P0HI6Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI6Q_DESC_MODE_8814B(x) | BIT_P0HI6Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI6Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI6Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI6Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI6Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI6Q_DESC_NUM_8814B) +#define BITS_P0HI6Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI6Q_DESC_NUM_8814B << BIT_SHIFT_P0HI6Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI6Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI6Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI6Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI6Q_DESC_NUM_8814B) +#define BIT_SET_P0HI6Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI6Q_DESC_NUM_8814B(x) | BIT_P0HI6Q_DESC_NUM_8814B(v)) + +/* 2 REG_BD_RWPTR_CLR1_8814B */ -/* 2 REG_VOQ_TXBD_DESA_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_FWCMDQ_HW_IDX_8814B BIT(30) +#define BIT_CLR_P0HI7Q_HW_IDX_8814B BIT(29) +#define BIT_CLR_P0HI6Q_HW_IDX_8814B BIT(28) +#define BIT_CLR_P0HI5Q_HW_IDX_8814B BIT(27) +#define BIT_CLR_P0HI4Q_HW_IDX_8814B BIT(26) +#define BIT_CLR_P0HI3Q_HW_IDX_8814B BIT(25) +#define BIT_CLR_P0HI2Q_HW_IDX_8814B BIT(24) +#define BIT_CLR_P0HI1Q_HW_IDX_8814B BIT(23) +#define BIT_CLR_P0HI0Q_HW_IDX_8814B BIT(22) +#define BIT_CLR_ACH3_HW_IDX_8814B BIT(21) +#define BIT_CLR_ACH2_HW_IDX_8814B BIT(20) +#define BIT_CLR_ACH1_HW_IDX_8814B BIT(19) +#define BIT_CLR_ACH0_HW_IDX_8814B BIT(18) +#define BIT_CLR_P0MGQ_HW_IDX_8814B BIT(17) +#define BIT_CLR_P0RXQ_HW_IDX_8814B BIT(16) -#define BIT_SHIFT_VOQ_TXBD_DESA_8814B 0 -#define BIT_MASK_VOQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_VOQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8814B) << BIT_SHIFT_VOQ_TXBD_DESA_8814B) -#define BIT_GET_VOQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8814B) & BIT_MASK_VOQ_TXBD_DESA_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_PFWCMDQ_HOST_IDX_8814B BIT(14) +#define BIT_CLR_P0HI7Q_HOST_IDX_8814B BIT(13) +#define BIT_CLR_P0HI6Q_HOST_IDX_8814B BIT(12) +#define BIT_CLR_P0HI5Q_HOST_IDX_8814B BIT(11) +#define BIT_CLR_P0HI4Q_HOST_IDX_8814B BIT(10) +#define BIT_CLR_P0HI3Q_HOST_IDX_8814B BIT(9) +#define BIT_CLR_P0HI2Q_HOST_IDX_8814B BIT(8) +#define BIT_CLR_P0HI1Q_HOST_IDX_8814B BIT(7) +#define BIT_CLR_P0HI0Q_HOST_IDX_8814B BIT(6) +#define BIT_CLR_ACH3_HOST_IDX_8814B BIT(5) +#define BIT_CLR_ACH2_HOST_IDX_8814B BIT(4) +#define BIT_CLR_ACH1_HOST_IDX_8814B BIT(3) +#define BIT_CLR_ACH0_HOST_IDX_8814B BIT(2) +#define BIT_CLR_P0MGQ_HOST_IDX_8814B BIT(1) +#define BIT_CLR_P0RXQ_HOST_IDX_8814B BIT(0) +/* 2 REG_TSFTIMER_HCI_8814B */ +#define BIT_SHIFT_TSFT2_HCI_8814B 16 +#define BIT_MASK_TSFT2_HCI_8814B 0xffff +#define BIT_TSFT2_HCI_8814B(x) \ + (((x) & BIT_MASK_TSFT2_HCI_8814B) << BIT_SHIFT_TSFT2_HCI_8814B) +#define BITS_TSFT2_HCI_8814B \ + (BIT_MASK_TSFT2_HCI_8814B << BIT_SHIFT_TSFT2_HCI_8814B) +#define BIT_CLEAR_TSFT2_HCI_8814B(x) ((x) & (~BITS_TSFT2_HCI_8814B)) +#define BIT_GET_TSFT2_HCI_8814B(x) \ + (((x) >> BIT_SHIFT_TSFT2_HCI_8814B) & BIT_MASK_TSFT2_HCI_8814B) +#define BIT_SET_TSFT2_HCI_8814B(x, v) \ + (BIT_CLEAR_TSFT2_HCI_8814B(x) | BIT_TSFT2_HCI_8814B(v)) -/* 2 REG_VIQ_TXBD_DESA_8814B */ +#define BIT_SHIFT_TSFT1_HCI_8814B 0 +#define BIT_MASK_TSFT1_HCI_8814B 0xffff +#define BIT_TSFT1_HCI_8814B(x) \ + (((x) & BIT_MASK_TSFT1_HCI_8814B) << BIT_SHIFT_TSFT1_HCI_8814B) +#define BITS_TSFT1_HCI_8814B \ + (BIT_MASK_TSFT1_HCI_8814B << BIT_SHIFT_TSFT1_HCI_8814B) +#define BIT_CLEAR_TSFT1_HCI_8814B(x) ((x) & (~BITS_TSFT1_HCI_8814B)) +#define BIT_GET_TSFT1_HCI_8814B(x) \ + (((x) >> BIT_SHIFT_TSFT1_HCI_8814B) & BIT_MASK_TSFT1_HCI_8814B) +#define BIT_SET_TSFT1_HCI_8814B(x, v) \ + (BIT_CLEAR_TSFT1_HCI_8814B(x) | BIT_TSFT1_HCI_8814B(v)) + +/* 2 REG_ACH0_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH0_HW_IDX_8814B 16 +#define BIT_MASK_ACH0_HW_IDX_8814B 0xfff +#define BIT_ACH0_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH0_HW_IDX_8814B) << BIT_SHIFT_ACH0_HW_IDX_8814B) +#define BITS_ACH0_HW_IDX_8814B \ + (BIT_MASK_ACH0_HW_IDX_8814B << BIT_SHIFT_ACH0_HW_IDX_8814B) +#define BIT_CLEAR_ACH0_HW_IDX_8814B(x) ((x) & (~BITS_ACH0_HW_IDX_8814B)) +#define BIT_GET_ACH0_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_HW_IDX_8814B) & BIT_MASK_ACH0_HW_IDX_8814B) +#define BIT_SET_ACH0_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH0_HW_IDX_8814B(x) | BIT_ACH0_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH0_HOST_IDX_8814B 0 +#define BIT_MASK_ACH0_HOST_IDX_8814B 0xfff +#define BIT_ACH0_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH0_HOST_IDX_8814B) << BIT_SHIFT_ACH0_HOST_IDX_8814B) +#define BITS_ACH0_HOST_IDX_8814B \ + (BIT_MASK_ACH0_HOST_IDX_8814B << BIT_SHIFT_ACH0_HOST_IDX_8814B) +#define BIT_CLEAR_ACH0_HOST_IDX_8814B(x) ((x) & (~BITS_ACH0_HOST_IDX_8814B)) +#define BIT_GET_ACH0_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH0_HOST_IDX_8814B) & BIT_MASK_ACH0_HOST_IDX_8814B) +#define BIT_SET_ACH0_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH0_HOST_IDX_8814B(x) | BIT_ACH0_HOST_IDX_8814B(v)) + +/* 2 REG_ACH1_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH1_HW_IDX_8814B 16 +#define BIT_MASK_ACH1_HW_IDX_8814B 0xfff +#define BIT_ACH1_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH1_HW_IDX_8814B) << BIT_SHIFT_ACH1_HW_IDX_8814B) +#define BITS_ACH1_HW_IDX_8814B \ + (BIT_MASK_ACH1_HW_IDX_8814B << BIT_SHIFT_ACH1_HW_IDX_8814B) +#define BIT_CLEAR_ACH1_HW_IDX_8814B(x) ((x) & (~BITS_ACH1_HW_IDX_8814B)) +#define BIT_GET_ACH1_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_HW_IDX_8814B) & BIT_MASK_ACH1_HW_IDX_8814B) +#define BIT_SET_ACH1_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH1_HW_IDX_8814B(x) | BIT_ACH1_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH1_HOST_IDX_8814B 0 +#define BIT_MASK_ACH1_HOST_IDX_8814B 0xfff +#define BIT_ACH1_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH1_HOST_IDX_8814B) << BIT_SHIFT_ACH1_HOST_IDX_8814B) +#define BITS_ACH1_HOST_IDX_8814B \ + (BIT_MASK_ACH1_HOST_IDX_8814B << BIT_SHIFT_ACH1_HOST_IDX_8814B) +#define BIT_CLEAR_ACH1_HOST_IDX_8814B(x) ((x) & (~BITS_ACH1_HOST_IDX_8814B)) +#define BIT_GET_ACH1_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH1_HOST_IDX_8814B) & BIT_MASK_ACH1_HOST_IDX_8814B) +#define BIT_SET_ACH1_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH1_HOST_IDX_8814B(x) | BIT_ACH1_HOST_IDX_8814B(v)) + +/* 2 REG_ACH2_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH2_HW_IDX_8814B 16 +#define BIT_MASK_ACH2_HW_IDX_8814B 0xfff +#define BIT_ACH2_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH2_HW_IDX_8814B) << BIT_SHIFT_ACH2_HW_IDX_8814B) +#define BITS_ACH2_HW_IDX_8814B \ + (BIT_MASK_ACH2_HW_IDX_8814B << BIT_SHIFT_ACH2_HW_IDX_8814B) +#define BIT_CLEAR_ACH2_HW_IDX_8814B(x) ((x) & (~BITS_ACH2_HW_IDX_8814B)) +#define BIT_GET_ACH2_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_HW_IDX_8814B) & BIT_MASK_ACH2_HW_IDX_8814B) +#define BIT_SET_ACH2_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH2_HW_IDX_8814B(x) | BIT_ACH2_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH2_HOST_IDX_8814B 0 +#define BIT_MASK_ACH2_HOST_IDX_8814B 0xfff +#define BIT_ACH2_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH2_HOST_IDX_8814B) << BIT_SHIFT_ACH2_HOST_IDX_8814B) +#define BITS_ACH2_HOST_IDX_8814B \ + (BIT_MASK_ACH2_HOST_IDX_8814B << BIT_SHIFT_ACH2_HOST_IDX_8814B) +#define BIT_CLEAR_ACH2_HOST_IDX_8814B(x) ((x) & (~BITS_ACH2_HOST_IDX_8814B)) +#define BIT_GET_ACH2_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH2_HOST_IDX_8814B) & BIT_MASK_ACH2_HOST_IDX_8814B) +#define BIT_SET_ACH2_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH2_HOST_IDX_8814B(x) | BIT_ACH2_HOST_IDX_8814B(v)) + +/* 2 REG_ACH3_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH3_HW_IDX_8814B 16 +#define BIT_MASK_ACH3_HW_IDX_8814B 0xfff +#define BIT_ACH3_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH3_HW_IDX_8814B) << BIT_SHIFT_ACH3_HW_IDX_8814B) +#define BITS_ACH3_HW_IDX_8814B \ + (BIT_MASK_ACH3_HW_IDX_8814B << BIT_SHIFT_ACH3_HW_IDX_8814B) +#define BIT_CLEAR_ACH3_HW_IDX_8814B(x) ((x) & (~BITS_ACH3_HW_IDX_8814B)) +#define BIT_GET_ACH3_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_HW_IDX_8814B) & BIT_MASK_ACH3_HW_IDX_8814B) +#define BIT_SET_ACH3_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH3_HW_IDX_8814B(x) | BIT_ACH3_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH3_HOST_IDX_8814B 0 +#define BIT_MASK_ACH3_HOST_IDX_8814B 0xfff +#define BIT_ACH3_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH3_HOST_IDX_8814B) << BIT_SHIFT_ACH3_HOST_IDX_8814B) +#define BITS_ACH3_HOST_IDX_8814B \ + (BIT_MASK_ACH3_HOST_IDX_8814B << BIT_SHIFT_ACH3_HOST_IDX_8814B) +#define BIT_CLEAR_ACH3_HOST_IDX_8814B(x) ((x) & (~BITS_ACH3_HOST_IDX_8814B)) +#define BIT_GET_ACH3_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH3_HOST_IDX_8814B) & BIT_MASK_ACH3_HOST_IDX_8814B) +#define BIT_SET_ACH3_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH3_HOST_IDX_8814B(x) | BIT_ACH3_HOST_IDX_8814B(v)) + +/* 2 REG_P0MGQ_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0MGQ_HW_IDX_8814B 16 +#define BIT_MASK_P0MGQ_HW_IDX_8814B 0xfff +#define BIT_P0MGQ_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0MGQ_HW_IDX_8814B) << BIT_SHIFT_P0MGQ_HW_IDX_8814B) +#define BITS_P0MGQ_HW_IDX_8814B \ + (BIT_MASK_P0MGQ_HW_IDX_8814B << BIT_SHIFT_P0MGQ_HW_IDX_8814B) +#define BIT_CLEAR_P0MGQ_HW_IDX_8814B(x) ((x) & (~BITS_P0MGQ_HW_IDX_8814B)) +#define BIT_GET_P0MGQ_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0MGQ_HW_IDX_8814B) & BIT_MASK_P0MGQ_HW_IDX_8814B) +#define BIT_SET_P0MGQ_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0MGQ_HW_IDX_8814B(x) | BIT_P0MGQ_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0MGQ_HOST_IDX_8814B 0 +#define BIT_MASK_P0MGQ_HOST_IDX_8814B 0xfff +#define BIT_P0MGQ_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0MGQ_HOST_IDX_8814B) \ + << BIT_SHIFT_P0MGQ_HOST_IDX_8814B) +#define BITS_P0MGQ_HOST_IDX_8814B \ + (BIT_MASK_P0MGQ_HOST_IDX_8814B << BIT_SHIFT_P0MGQ_HOST_IDX_8814B) +#define BIT_CLEAR_P0MGQ_HOST_IDX_8814B(x) ((x) & (~BITS_P0MGQ_HOST_IDX_8814B)) +#define BIT_GET_P0MGQ_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0MGQ_HOST_IDX_8814B) & \ + BIT_MASK_P0MGQ_HOST_IDX_8814B) +#define BIT_SET_P0MGQ_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0MGQ_HOST_IDX_8814B(x) | BIT_P0MGQ_HOST_IDX_8814B(v)) + +/* 2 REG_P0RXQ_RXBD_IDX_8814B */ + +#define BIT_SHIFT_P0RXQ_HW_IDX_8814B 16 +#define BIT_MASK_P0RXQ_HW_IDX_8814B 0xfff +#define BIT_P0RXQ_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0RXQ_HW_IDX_8814B) << BIT_SHIFT_P0RXQ_HW_IDX_8814B) +#define BITS_P0RXQ_HW_IDX_8814B \ + (BIT_MASK_P0RXQ_HW_IDX_8814B << BIT_SHIFT_P0RXQ_HW_IDX_8814B) +#define BIT_CLEAR_P0RXQ_HW_IDX_8814B(x) ((x) & (~BITS_P0RXQ_HW_IDX_8814B)) +#define BIT_GET_P0RXQ_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0RXQ_HW_IDX_8814B) & BIT_MASK_P0RXQ_HW_IDX_8814B) +#define BIT_SET_P0RXQ_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0RXQ_HW_IDX_8814B(x) | BIT_P0RXQ_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0RXQ_HOST_IDX_8814B 0 +#define BIT_MASK_P0RXQ_HOST_IDX_8814B 0xfff +#define BIT_P0RXQ_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0RXQ_HOST_IDX_8814B) \ + << BIT_SHIFT_P0RXQ_HOST_IDX_8814B) +#define BITS_P0RXQ_HOST_IDX_8814B \ + (BIT_MASK_P0RXQ_HOST_IDX_8814B << BIT_SHIFT_P0RXQ_HOST_IDX_8814B) +#define BIT_CLEAR_P0RXQ_HOST_IDX_8814B(x) ((x) & (~BITS_P0RXQ_HOST_IDX_8814B)) +#define BIT_GET_P0RXQ_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0RXQ_HOST_IDX_8814B) & \ + BIT_MASK_P0RXQ_HOST_IDX_8814B) +#define BIT_SET_P0RXQ_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0RXQ_HOST_IDX_8814B(x) | BIT_P0RXQ_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI0Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI0Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI0Q_HW_IDX_8814B 0xfff +#define BIT_P0HI0Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI0Q_HW_IDX_8814B) << BIT_SHIFT_P0HI0Q_HW_IDX_8814B) +#define BITS_P0HI0Q_HW_IDX_8814B \ + (BIT_MASK_P0HI0Q_HW_IDX_8814B << BIT_SHIFT_P0HI0Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI0Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI0Q_HW_IDX_8814B)) +#define BIT_GET_P0HI0Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_HW_IDX_8814B) & BIT_MASK_P0HI0Q_HW_IDX_8814B) +#define BIT_SET_P0HI0Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI0Q_HW_IDX_8814B(x) | BIT_P0HI0Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI0Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI0Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI0Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI0Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI0Q_HOST_IDX_8814B) +#define BITS_P0HI0Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI0Q_HOST_IDX_8814B << BIT_SHIFT_P0HI0Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI0Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI0Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI0Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI0Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI0Q_HOST_IDX_8814B) +#define BIT_SET_P0HI0Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI0Q_HOST_IDX_8814B(x) | BIT_P0HI0Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI1Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI1Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI1Q_HW_IDX_8814B 0xfff +#define BIT_P0HI1Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI1Q_HW_IDX_8814B) << BIT_SHIFT_P0HI1Q_HW_IDX_8814B) +#define BITS_P0HI1Q_HW_IDX_8814B \ + (BIT_MASK_P0HI1Q_HW_IDX_8814B << BIT_SHIFT_P0HI1Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI1Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI1Q_HW_IDX_8814B)) +#define BIT_GET_P0HI1Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_HW_IDX_8814B) & BIT_MASK_P0HI1Q_HW_IDX_8814B) +#define BIT_SET_P0HI1Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI1Q_HW_IDX_8814B(x) | BIT_P0HI1Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI1Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI1Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI1Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI1Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI1Q_HOST_IDX_8814B) +#define BITS_P0HI1Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI1Q_HOST_IDX_8814B << BIT_SHIFT_P0HI1Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI1Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI1Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI1Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI1Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI1Q_HOST_IDX_8814B) +#define BIT_SET_P0HI1Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI1Q_HOST_IDX_8814B(x) | BIT_P0HI1Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI2Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI2Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI2Q_HW_IDX_8814B 0xfff +#define BIT_P0HI2Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI2Q_HW_IDX_8814B) << BIT_SHIFT_P0HI2Q_HW_IDX_8814B) +#define BITS_P0HI2Q_HW_IDX_8814B \ + (BIT_MASK_P0HI2Q_HW_IDX_8814B << BIT_SHIFT_P0HI2Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI2Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI2Q_HW_IDX_8814B)) +#define BIT_GET_P0HI2Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_HW_IDX_8814B) & BIT_MASK_P0HI2Q_HW_IDX_8814B) +#define BIT_SET_P0HI2Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI2Q_HW_IDX_8814B(x) | BIT_P0HI2Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI2Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI2Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI2Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI2Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI2Q_HOST_IDX_8814B) +#define BITS_P0HI2Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI2Q_HOST_IDX_8814B << BIT_SHIFT_P0HI2Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI2Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI2Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI2Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI2Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI2Q_HOST_IDX_8814B) +#define BIT_SET_P0HI2Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI2Q_HOST_IDX_8814B(x) | BIT_P0HI2Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI3Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI3Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI3Q_HW_IDX_8814B 0xfff +#define BIT_P0HI3Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI3Q_HW_IDX_8814B) << BIT_SHIFT_P0HI3Q_HW_IDX_8814B) +#define BITS_P0HI3Q_HW_IDX_8814B \ + (BIT_MASK_P0HI3Q_HW_IDX_8814B << BIT_SHIFT_P0HI3Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI3Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI3Q_HW_IDX_8814B)) +#define BIT_GET_P0HI3Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_HW_IDX_8814B) & BIT_MASK_P0HI3Q_HW_IDX_8814B) +#define BIT_SET_P0HI3Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI3Q_HW_IDX_8814B(x) | BIT_P0HI3Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI3Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI3Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI3Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI3Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI3Q_HOST_IDX_8814B) +#define BITS_P0HI3Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI3Q_HOST_IDX_8814B << BIT_SHIFT_P0HI3Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI3Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI3Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI3Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI3Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI3Q_HOST_IDX_8814B) +#define BIT_SET_P0HI3Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI3Q_HOST_IDX_8814B(x) | BIT_P0HI3Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI4Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI4Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI4Q_HW_IDX_8814B 0xfff +#define BIT_P0HI4Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI4Q_HW_IDX_8814B) << BIT_SHIFT_P0HI4Q_HW_IDX_8814B) +#define BITS_P0HI4Q_HW_IDX_8814B \ + (BIT_MASK_P0HI4Q_HW_IDX_8814B << BIT_SHIFT_P0HI4Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI4Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI4Q_HW_IDX_8814B)) +#define BIT_GET_P0HI4Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_HW_IDX_8814B) & BIT_MASK_P0HI4Q_HW_IDX_8814B) +#define BIT_SET_P0HI4Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI4Q_HW_IDX_8814B(x) | BIT_P0HI4Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI4Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI4Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI4Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI4Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI4Q_HOST_IDX_8814B) +#define BITS_P0HI4Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI4Q_HOST_IDX_8814B << BIT_SHIFT_P0HI4Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI4Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI4Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI4Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI4Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI4Q_HOST_IDX_8814B) +#define BIT_SET_P0HI4Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI4Q_HOST_IDX_8814B(x) | BIT_P0HI4Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI5Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI5Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI5Q_HW_IDX_8814B 0xfff +#define BIT_P0HI5Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI5Q_HW_IDX_8814B) << BIT_SHIFT_P0HI5Q_HW_IDX_8814B) +#define BITS_P0HI5Q_HW_IDX_8814B \ + (BIT_MASK_P0HI5Q_HW_IDX_8814B << BIT_SHIFT_P0HI5Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI5Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI5Q_HW_IDX_8814B)) +#define BIT_GET_P0HI5Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_HW_IDX_8814B) & BIT_MASK_P0HI5Q_HW_IDX_8814B) +#define BIT_SET_P0HI5Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI5Q_HW_IDX_8814B(x) | BIT_P0HI5Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI5Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI5Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI5Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI5Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI5Q_HOST_IDX_8814B) +#define BITS_P0HI5Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI5Q_HOST_IDX_8814B << BIT_SHIFT_P0HI5Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI5Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI5Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI5Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI5Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI5Q_HOST_IDX_8814B) +#define BIT_SET_P0HI5Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI5Q_HOST_IDX_8814B(x) | BIT_P0HI5Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI6Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI6Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI6Q_HW_IDX_8814B 0xfff +#define BIT_P0HI6Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI6Q_HW_IDX_8814B) << BIT_SHIFT_P0HI6Q_HW_IDX_8814B) +#define BITS_P0HI6Q_HW_IDX_8814B \ + (BIT_MASK_P0HI6Q_HW_IDX_8814B << BIT_SHIFT_P0HI6Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI6Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI6Q_HW_IDX_8814B)) +#define BIT_GET_P0HI6Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_HW_IDX_8814B) & BIT_MASK_P0HI6Q_HW_IDX_8814B) +#define BIT_SET_P0HI6Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI6Q_HW_IDX_8814B(x) | BIT_P0HI6Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI6Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI6Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI6Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI6Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI6Q_HOST_IDX_8814B) +#define BITS_P0HI6Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI6Q_HOST_IDX_8814B << BIT_SHIFT_P0HI6Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI6Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI6Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI6Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI6Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI6Q_HOST_IDX_8814B) +#define BIT_SET_P0HI6Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI6Q_HOST_IDX_8814B(x) | BIT_P0HI6Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI7Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI7Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI7Q_HW_IDX_8814B 0xfff +#define BIT_P0HI7Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI7Q_HW_IDX_8814B) << BIT_SHIFT_P0HI7Q_HW_IDX_8814B) +#define BITS_P0HI7Q_HW_IDX_8814B \ + (BIT_MASK_P0HI7Q_HW_IDX_8814B << BIT_SHIFT_P0HI7Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI7Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI7Q_HW_IDX_8814B)) +#define BIT_GET_P0HI7Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_HW_IDX_8814B) & BIT_MASK_P0HI7Q_HW_IDX_8814B) +#define BIT_SET_P0HI7Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI7Q_HW_IDX_8814B(x) | BIT_P0HI7Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI7Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI7Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI7Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI7Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI7Q_HOST_IDX_8814B) +#define BITS_P0HI7Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI7Q_HOST_IDX_8814B << BIT_SHIFT_P0HI7Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI7Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI7Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI7Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI7Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI7Q_HOST_IDX_8814B) +#define BIT_SET_P0HI7Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI7Q_HOST_IDX_8814B(x) | BIT_P0HI7Q_HOST_IDX_8814B(v)) + +/* 2 REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1_8814B */ +#define BIT_DIS_TXDMA_PRE_V1_8814B BIT(31) +#define BIT_DIS_RXDMA_PRE_V1_8814B BIT(30) + +#define BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B 28 +#define BIT_MASK_HPS_CLKR_PCIE_V1_8814B 0x3 +#define BIT_HPS_CLKR_PCIE_V1_8814B(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE_V1_8814B) \ + << BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B) +#define BITS_HPS_CLKR_PCIE_V1_8814B \ + (BIT_MASK_HPS_CLKR_PCIE_V1_8814B << BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B) +#define BIT_CLEAR_HPS_CLKR_PCIE_V1_8814B(x) \ + ((x) & (~BITS_HPS_CLKR_PCIE_V1_8814B)) +#define BIT_GET_HPS_CLKR_PCIE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B) & \ + BIT_MASK_HPS_CLKR_PCIE_V1_8814B) +#define BIT_SET_HPS_CLKR_PCIE_V1_8814B(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE_V1_8814B(x) | BIT_HPS_CLKR_PCIE_V1_8814B(v)) + +#define BIT_PCIE_INT_V1_8814B BIT(27) +#define BIT_TXFLAG_EXIT_L1_EN_V1_8814B BIT(26) +#define BIT_EN_RXDMA_ALIGN_V2_8814B BIT(25) +#define BIT_EN_TXDMA_ALIGN_V2_8814B BIT(24) + +#define BIT_SHIFT_PCIE_HCPWM_V1_8814B 16 +#define BIT_MASK_PCIE_HCPWM_V1_8814B 0xff +#define BIT_PCIE_HCPWM_V1_8814B(x) \ + (((x) & BIT_MASK_PCIE_HCPWM_V1_8814B) << BIT_SHIFT_PCIE_HCPWM_V1_8814B) +#define BITS_PCIE_HCPWM_V1_8814B \ + (BIT_MASK_PCIE_HCPWM_V1_8814B << BIT_SHIFT_PCIE_HCPWM_V1_8814B) +#define BIT_CLEAR_PCIE_HCPWM_V1_8814B(x) ((x) & (~BITS_PCIE_HCPWM_V1_8814B)) +#define BIT_GET_PCIE_HCPWM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM_V1_8814B) & BIT_MASK_PCIE_HCPWM_V1_8814B) +#define BIT_SET_PCIE_HCPWM_V1_8814B(x, v) \ + (BIT_CLEAR_PCIE_HCPWM_V1_8814B(x) | BIT_PCIE_HCPWM_V1_8814B(v)) + +#define BIT_SHIFT_PCIE_HRPWM_V1_8814B 8 +#define BIT_MASK_PCIE_HRPWM_V1_8814B 0xff +#define BIT_PCIE_HRPWM_V1_8814B(x) \ + (((x) & BIT_MASK_PCIE_HRPWM_V1_8814B) << BIT_SHIFT_PCIE_HRPWM_V1_8814B) +#define BITS_PCIE_HRPWM_V1_8814B \ + (BIT_MASK_PCIE_HRPWM_V1_8814B << BIT_SHIFT_PCIE_HRPWM_V1_8814B) +#define BIT_CLEAR_PCIE_HRPWM_V1_8814B(x) ((x) & (~BITS_PCIE_HRPWM_V1_8814B)) +#define BIT_GET_PCIE_HRPWM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM_V1_8814B) & BIT_MASK_PCIE_HRPWM_V1_8814B) +#define BIT_SET_PCIE_HRPWM_V1_8814B(x, v) \ + (BIT_CLEAR_PCIE_HRPWM_V1_8814B(x) | BIT_PCIE_HRPWM_V1_8814B(v)) -#define BIT_SHIFT_VIQ_TXBD_DESA_8814B 0 -#define BIT_MASK_VIQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_VIQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8814B) << BIT_SHIFT_VIQ_TXBD_DESA_8814B) -#define BIT_GET_VIQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8814B) & BIT_MASK_VIQ_TXBD_DESA_8814B) +#define BIT_SHIFT_DBG_SEL_8814B 0 +#define BIT_MASK_DBG_SEL_8814B 0xff +#define BIT_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_DBG_SEL_8814B) << BIT_SHIFT_DBG_SEL_8814B) +#define BITS_DBG_SEL_8814B (BIT_MASK_DBG_SEL_8814B << BIT_SHIFT_DBG_SEL_8814B) +#define BIT_CLEAR_DBG_SEL_8814B(x) ((x) & (~BITS_DBG_SEL_8814B)) +#define BIT_GET_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_8814B) & BIT_MASK_DBG_SEL_8814B) +#define BIT_SET_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_DBG_SEL_8814B(x) | BIT_DBG_SEL_8814B(v)) + +/* 2 REG_PCIE_HRPWM2_HCPWM2_V1_8814B */ + +#define BIT_SHIFT_PCIE_HCPWM2_V1_8814B 16 +#define BIT_MASK_PCIE_HCPWM2_V1_8814B 0xffff +#define BIT_PCIE_HCPWM2_V1_8814B(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2_V1_8814B) \ + << BIT_SHIFT_PCIE_HCPWM2_V1_8814B) +#define BITS_PCIE_HCPWM2_V1_8814B \ + (BIT_MASK_PCIE_HCPWM2_V1_8814B << BIT_SHIFT_PCIE_HCPWM2_V1_8814B) +#define BIT_CLEAR_PCIE_HCPWM2_V1_8814B(x) ((x) & (~BITS_PCIE_HCPWM2_V1_8814B)) +#define BIT_GET_PCIE_HCPWM2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2_V1_8814B) & \ + BIT_MASK_PCIE_HCPWM2_V1_8814B) +#define BIT_SET_PCIE_HCPWM2_V1_8814B(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2_V1_8814B(x) | BIT_PCIE_HCPWM2_V1_8814B(v)) +#define BIT_SHIFT_PCIE_HRPWM2_8814B 0 +#define BIT_MASK_PCIE_HRPWM2_8814B 0xffff +#define BIT_PCIE_HRPWM2_8814B(x) \ + (((x) & BIT_MASK_PCIE_HRPWM2_8814B) << BIT_SHIFT_PCIE_HRPWM2_8814B) +#define BITS_PCIE_HRPWM2_8814B \ + (BIT_MASK_PCIE_HRPWM2_8814B << BIT_SHIFT_PCIE_HRPWM2_8814B) +#define BIT_CLEAR_PCIE_HRPWM2_8814B(x) ((x) & (~BITS_PCIE_HRPWM2_8814B)) +#define BIT_GET_PCIE_HRPWM2_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM2_8814B) & BIT_MASK_PCIE_HRPWM2_8814B) +#define BIT_SET_PCIE_HRPWM2_8814B(x, v) \ + (BIT_CLEAR_PCIE_HRPWM2_8814B(x) | BIT_PCIE_HRPWM2_8814B(v)) +/* 2 REG_PCIE_H2C_MSG_V1_8814B */ -/* 2 REG_BEQ_TXBD_DESA_8814B */ +#define BIT_SHIFT_DRV2FW_INFO_8814B 0 +#define BIT_MASK_DRV2FW_INFO_8814B 0xffffffffL +#define BIT_DRV2FW_INFO_8814B(x) \ + (((x) & BIT_MASK_DRV2FW_INFO_8814B) << BIT_SHIFT_DRV2FW_INFO_8814B) +#define BITS_DRV2FW_INFO_8814B \ + (BIT_MASK_DRV2FW_INFO_8814B << BIT_SHIFT_DRV2FW_INFO_8814B) +#define BIT_CLEAR_DRV2FW_INFO_8814B(x) ((x) & (~BITS_DRV2FW_INFO_8814B)) +#define BIT_GET_DRV2FW_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO_8814B) & BIT_MASK_DRV2FW_INFO_8814B) +#define BIT_SET_DRV2FW_INFO_8814B(x, v) \ + (BIT_CLEAR_DRV2FW_INFO_8814B(x) | BIT_DRV2FW_INFO_8814B(v)) -#define BIT_SHIFT_BEQ_TXBD_DESA_8814B 0 -#define BIT_MASK_BEQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_BEQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8814B) << BIT_SHIFT_BEQ_TXBD_DESA_8814B) -#define BIT_GET_BEQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8814B) & BIT_MASK_BEQ_TXBD_DESA_8814B) +/* 2 REG_PCIE_C2H_MSG_V1_8814B */ +#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B 0 +#define BIT_MASK_HCI_PCIE_C2H_MSG_8814B 0xffffffffL +#define BIT_HCI_PCIE_C2H_MSG_8814B(x) \ + (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8814B) \ + << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) +#define BITS_HCI_PCIE_C2H_MSG_8814B \ + (BIT_MASK_HCI_PCIE_C2H_MSG_8814B << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) +#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8814B(x) \ + ((x) & (~BITS_HCI_PCIE_C2H_MSG_8814B)) +#define BIT_GET_HCI_PCIE_C2H_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) & \ + BIT_MASK_HCI_PCIE_C2H_MSG_8814B) +#define BIT_SET_HCI_PCIE_C2H_MSG_8814B(x, v) \ + (BIT_CLEAR_HCI_PCIE_C2H_MSG_8814B(x) | BIT_HCI_PCIE_C2H_MSG_8814B(v)) +/* 2 REG_DBI_WDATA_V1_8814B */ -/* 2 REG_BKQ_TXBD_DESA_8814B */ +#define BIT_SHIFT_DBI_WDATA_8814B 0 +#define BIT_MASK_DBI_WDATA_8814B 0xffffffffL +#define BIT_DBI_WDATA_8814B(x) \ + (((x) & BIT_MASK_DBI_WDATA_8814B) << BIT_SHIFT_DBI_WDATA_8814B) +#define BITS_DBI_WDATA_8814B \ + (BIT_MASK_DBI_WDATA_8814B << BIT_SHIFT_DBI_WDATA_8814B) +#define BIT_CLEAR_DBI_WDATA_8814B(x) ((x) & (~BITS_DBI_WDATA_8814B)) +#define BIT_GET_DBI_WDATA_8814B(x) \ + (((x) >> BIT_SHIFT_DBI_WDATA_8814B) & BIT_MASK_DBI_WDATA_8814B) +#define BIT_SET_DBI_WDATA_8814B(x, v) \ + (BIT_CLEAR_DBI_WDATA_8814B(x) | BIT_DBI_WDATA_8814B(v)) -#define BIT_SHIFT_BKQ_TXBD_DESA_8814B 0 -#define BIT_MASK_BKQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_BKQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8814B) << BIT_SHIFT_BKQ_TXBD_DESA_8814B) -#define BIT_GET_BKQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8814B) & BIT_MASK_BKQ_TXBD_DESA_8814B) +/* 2 REG_DBI_RDATA_V1_8814B */ +#define BIT_SHIFT_DBI_RDATA_8814B 0 +#define BIT_MASK_DBI_RDATA_8814B 0xffffffffL +#define BIT_DBI_RDATA_8814B(x) \ + (((x) & BIT_MASK_DBI_RDATA_8814B) << BIT_SHIFT_DBI_RDATA_8814B) +#define BITS_DBI_RDATA_8814B \ + (BIT_MASK_DBI_RDATA_8814B << BIT_SHIFT_DBI_RDATA_8814B) +#define BIT_CLEAR_DBI_RDATA_8814B(x) ((x) & (~BITS_DBI_RDATA_8814B)) +#define BIT_GET_DBI_RDATA_8814B(x) \ + (((x) >> BIT_SHIFT_DBI_RDATA_8814B) & BIT_MASK_DBI_RDATA_8814B) +#define BIT_SET_DBI_RDATA_8814B(x, v) \ + (BIT_CLEAR_DBI_RDATA_8814B(x) | BIT_DBI_RDATA_8814B(v)) +/* 2 REG_DBI_FLAG_V1_8814B */ -/* 2 REG_RXQ_RXBD_DESA_8814B */ +#define BIT_SHIFT_LOOPBACK_DBG_SEL_8814B 28 +#define BIT_MASK_LOOPBACK_DBG_SEL_8814B 0xf +#define BIT_LOOPBACK_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_LOOPBACK_DBG_SEL_8814B) \ + << BIT_SHIFT_LOOPBACK_DBG_SEL_8814B) +#define BITS_LOOPBACK_DBG_SEL_8814B \ + (BIT_MASK_LOOPBACK_DBG_SEL_8814B << BIT_SHIFT_LOOPBACK_DBG_SEL_8814B) +#define BIT_CLEAR_LOOPBACK_DBG_SEL_8814B(x) \ + ((x) & (~BITS_LOOPBACK_DBG_SEL_8814B)) +#define BIT_GET_LOOPBACK_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_LOOPBACK_DBG_SEL_8814B) & \ + BIT_MASK_LOOPBACK_DBG_SEL_8814B) +#define BIT_SET_LOOPBACK_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_LOOPBACK_DBG_SEL_8814B(x) | BIT_LOOPBACK_DBG_SEL_8814B(v)) -#define BIT_SHIFT_RXQ_RXBD_DESA_8814B 0 -#define BIT_MASK_RXQ_RXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_RXQ_RXBD_DESA_8814B(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8814B) << BIT_SHIFT_RXQ_RXBD_DESA_8814B) -#define BIT_GET_RXQ_RXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8814B) & BIT_MASK_RXQ_RXBD_DESA_8814B) +#define BIT_EN_STUCK_DBG_8814B BIT(26) +#define BIT_RX_STUCK_8814B BIT(25) +#define BIT_TX_STUCK_8814B BIT(24) +#define BIT_DBI_RFLAG_8814B BIT(17) +#define BIT_DBI_WFLAG_8814B BIT(16) +#define BIT_SHIFT_DBI_WREN_8814B 12 +#define BIT_MASK_DBI_WREN_8814B 0xf +#define BIT_DBI_WREN_8814B(x) \ + (((x) & BIT_MASK_DBI_WREN_8814B) << BIT_SHIFT_DBI_WREN_8814B) +#define BITS_DBI_WREN_8814B \ + (BIT_MASK_DBI_WREN_8814B << BIT_SHIFT_DBI_WREN_8814B) +#define BIT_CLEAR_DBI_WREN_8814B(x) ((x) & (~BITS_DBI_WREN_8814B)) +#define BIT_GET_DBI_WREN_8814B(x) \ + (((x) >> BIT_SHIFT_DBI_WREN_8814B) & BIT_MASK_DBI_WREN_8814B) +#define BIT_SET_DBI_WREN_8814B(x, v) \ + (BIT_CLEAR_DBI_WREN_8814B(x) | BIT_DBI_WREN_8814B(v)) +#define BIT_SHIFT_DBI_ADDR_8814B 0 +#define BIT_MASK_DBI_ADDR_8814B 0xfff +#define BIT_DBI_ADDR_8814B(x) \ + (((x) & BIT_MASK_DBI_ADDR_8814B) << BIT_SHIFT_DBI_ADDR_8814B) +#define BITS_DBI_ADDR_8814B \ + (BIT_MASK_DBI_ADDR_8814B << BIT_SHIFT_DBI_ADDR_8814B) +#define BIT_CLEAR_DBI_ADDR_8814B(x) ((x) & (~BITS_DBI_ADDR_8814B)) +#define BIT_GET_DBI_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_DBI_ADDR_8814B) & BIT_MASK_DBI_ADDR_8814B) +#define BIT_SET_DBI_ADDR_8814B(x, v) \ + (BIT_CLEAR_DBI_ADDR_8814B(x) | BIT_DBI_ADDR_8814B(v)) -/* 2 REG_HI0Q_TXBD_DESA_8814B */ +/* 2 REG_MDIO_V1_8814B */ -#define BIT_SHIFT_HI0Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI0Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI0Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8814B) << BIT_SHIFT_HI0Q_TXBD_DESA_8814B) -#define BIT_GET_HI0Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8814B) & BIT_MASK_HI0Q_TXBD_DESA_8814B) +#define BIT_SHIFT_MDIO_RDATA_8814B 16 +#define BIT_MASK_MDIO_RDATA_8814B 0xffff +#define BIT_MDIO_RDATA_8814B(x) \ + (((x) & BIT_MASK_MDIO_RDATA_8814B) << BIT_SHIFT_MDIO_RDATA_8814B) +#define BITS_MDIO_RDATA_8814B \ + (BIT_MASK_MDIO_RDATA_8814B << BIT_SHIFT_MDIO_RDATA_8814B) +#define BIT_CLEAR_MDIO_RDATA_8814B(x) ((x) & (~BITS_MDIO_RDATA_8814B)) +#define BIT_GET_MDIO_RDATA_8814B(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA_8814B) & BIT_MASK_MDIO_RDATA_8814B) +#define BIT_SET_MDIO_RDATA_8814B(x, v) \ + (BIT_CLEAR_MDIO_RDATA_8814B(x) | BIT_MDIO_RDATA_8814B(v)) +#define BIT_SHIFT_MDIO_WDATA_8814B 0 +#define BIT_MASK_MDIO_WDATA_8814B 0xffff +#define BIT_MDIO_WDATA_8814B(x) \ + (((x) & BIT_MASK_MDIO_WDATA_8814B) << BIT_SHIFT_MDIO_WDATA_8814B) +#define BITS_MDIO_WDATA_8814B \ + (BIT_MASK_MDIO_WDATA_8814B << BIT_SHIFT_MDIO_WDATA_8814B) +#define BIT_CLEAR_MDIO_WDATA_8814B(x) ((x) & (~BITS_MDIO_WDATA_8814B)) +#define BIT_GET_MDIO_WDATA_8814B(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA_8814B) & BIT_MASK_MDIO_WDATA_8814B) +#define BIT_SET_MDIO_WDATA_8814B(x, v) \ + (BIT_CLEAR_MDIO_WDATA_8814B(x) | BIT_MDIO_WDATA_8814B(v)) +/* 2 REG_PCIE_MIX_CFG_8814B */ -/* 2 REG_HI1Q_TXBD_DESA_8814B */ - -#define BIT_SHIFT_HI1Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI1Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI1Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8814B) << BIT_SHIFT_HI1Q_TXBD_DESA_8814B) -#define BIT_GET_HI1Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8814B) & BIT_MASK_HI1Q_TXBD_DESA_8814B) +#define BIT_SHIFT_MDIO_PHY_ADDR_8814B 24 +#define BIT_MASK_MDIO_PHY_ADDR_8814B 0x1f +#define BIT_MDIO_PHY_ADDR_8814B(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR_8814B) << BIT_SHIFT_MDIO_PHY_ADDR_8814B) +#define BITS_MDIO_PHY_ADDR_8814B \ + (BIT_MASK_MDIO_PHY_ADDR_8814B << BIT_SHIFT_MDIO_PHY_ADDR_8814B) +#define BIT_CLEAR_MDIO_PHY_ADDR_8814B(x) ((x) & (~BITS_MDIO_PHY_ADDR_8814B)) +#define BIT_GET_MDIO_PHY_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8814B) & BIT_MASK_MDIO_PHY_ADDR_8814B) +#define BIT_SET_MDIO_PHY_ADDR_8814B(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR_8814B(x) | BIT_MDIO_PHY_ADDR_8814B(v)) +#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B 10 +#define BIT_MASK_WATCH_DOG_RECORD_V1_8814B 0x3fff +#define BIT_WATCH_DOG_RECORD_V1_8814B(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8814B) \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) +#define BITS_WATCH_DOG_RECORD_V1_8814B \ + (BIT_MASK_WATCH_DOG_RECORD_V1_8814B \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8814B(x) \ + ((x) & (~BITS_WATCH_DOG_RECORD_V1_8814B)) +#define BIT_GET_WATCH_DOG_RECORD_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) & \ + BIT_MASK_WATCH_DOG_RECORD_V1_8814B) +#define BIT_SET_WATCH_DOG_RECORD_V1_8814B(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1_8814B(x) | \ + BIT_WATCH_DOG_RECORD_V1_8814B(v)) +#define BIT_R_IO_TIMEOUT_FLAG_V1_8814B BIT(9) +#define BIT_EN_WATCH_DOG_8814B BIT(8) +#define BIT_ECRC_EN_8814B BIT(7) +#define BIT_MDIO_RFLAG_8814B BIT(6) +#define BIT_MDIO_WFLAG_8814B BIT(5) + +#define BIT_SHIFT_MDIO_REG_ADDR_8814B 0 +#define BIT_MASK_MDIO_REG_ADDR_8814B 0x1f +#define BIT_MDIO_REG_ADDR_8814B(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_8814B) << BIT_SHIFT_MDIO_REG_ADDR_8814B) +#define BITS_MDIO_REG_ADDR_8814B \ + (BIT_MASK_MDIO_REG_ADDR_8814B << BIT_SHIFT_MDIO_REG_ADDR_8814B) +#define BIT_CLEAR_MDIO_REG_ADDR_8814B(x) ((x) & (~BITS_MDIO_REG_ADDR_8814B)) +#define BIT_GET_MDIO_REG_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_8814B) & BIT_MASK_MDIO_REG_ADDR_8814B) +#define BIT_SET_MDIO_REG_ADDR_8814B(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_8814B(x) | BIT_MDIO_REG_ADDR_8814B(v)) -/* 2 REG_HI2Q_TXBD_DESA_8814B */ +/* 2 REG_HCI_MIX_CFG_8814B */ +#define BIT_EN_ALIGN_MTU_8814B BIT(23) + +#define BIT_SHIFT_LATENCY_CONTROL_8814B 21 +#define BIT_MASK_LATENCY_CONTROL_8814B 0x3 +#define BIT_LATENCY_CONTROL_8814B(x) \ + (((x) & BIT_MASK_LATENCY_CONTROL_8814B) \ + << BIT_SHIFT_LATENCY_CONTROL_8814B) +#define BITS_LATENCY_CONTROL_8814B \ + (BIT_MASK_LATENCY_CONTROL_8814B << BIT_SHIFT_LATENCY_CONTROL_8814B) +#define BIT_CLEAR_LATENCY_CONTROL_8814B(x) ((x) & (~BITS_LATENCY_CONTROL_8814B)) +#define BIT_GET_LATENCY_CONTROL_8814B(x) \ + (((x) >> BIT_SHIFT_LATENCY_CONTROL_8814B) & \ + BIT_MASK_LATENCY_CONTROL_8814B) +#define BIT_SET_LATENCY_CONTROL_8814B(x, v) \ + (BIT_CLEAR_LATENCY_CONTROL_8814B(x) | BIT_LATENCY_CONTROL_8814B(v)) -#define BIT_SHIFT_HI2Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI2Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI2Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8814B) << BIT_SHIFT_HI2Q_TXBD_DESA_8814B) -#define BIT_GET_HI2Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8814B) & BIT_MASK_HI2Q_TXBD_DESA_8814B) +#define BIT_HOST_GEN2_SUPPORT_8814B BIT(20) +#define BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B 15 +#define BIT_MASK_TXDMA_ERR_FLAG_V1_8814B 0x1f +#define BIT_TXDMA_ERR_FLAG_V1_8814B(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_V1_8814B) \ + << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B) +#define BITS_TXDMA_ERR_FLAG_V1_8814B \ + (BIT_MASK_TXDMA_ERR_FLAG_V1_8814B << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B) +#define BIT_CLEAR_TXDMA_ERR_FLAG_V1_8814B(x) \ + ((x) & (~BITS_TXDMA_ERR_FLAG_V1_8814B)) +#define BIT_GET_TXDMA_ERR_FLAG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B) & \ + BIT_MASK_TXDMA_ERR_FLAG_V1_8814B) +#define BIT_SET_TXDMA_ERR_FLAG_V1_8814B(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_V1_8814B(x) | BIT_TXDMA_ERR_FLAG_V1_8814B(v)) +#define BIT_EPHY_RX50_EN_8814B BIT(11) -/* 2 REG_HI3Q_TXBD_DESA_8814B */ +#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B 8 +#define BIT_MASK_MSI_TIMEOUT_ID_V1_8814B 0x7 +#define BIT_MSI_TIMEOUT_ID_V1_8814B(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8814B) \ + << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) +#define BITS_MSI_TIMEOUT_ID_V1_8814B \ + (BIT_MASK_MSI_TIMEOUT_ID_V1_8814B << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8814B(x) \ + ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8814B)) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) & \ + BIT_MASK_MSI_TIMEOUT_ID_V1_8814B) +#define BIT_SET_MSI_TIMEOUT_ID_V1_8814B(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8814B(x) | BIT_MSI_TIMEOUT_ID_V1_8814B(v)) -#define BIT_SHIFT_HI3Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI3Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI3Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8814B) << BIT_SHIFT_HI3Q_TXBD_DESA_8814B) -#define BIT_GET_HI3Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8814B) & BIT_MASK_HI3Q_TXBD_DESA_8814B) +#define BIT_RADDR_RD_8814B BIT(7) +#define BIT_L0S_LINK_OFF_8814B BIT(4) +#define BIT_ACT_LINK_OFF_8814B BIT(3) +#define BIT_EN_SLOW_MAC_TX_8814B BIT(2) +#define BIT_EN_SLOW_MAC_RX_8814B BIT(1) +#define BIT_EN_SLOW_MAC_HW_8814B BIT(0) +/* 2 REG_STC_INT_CS_8814B(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */ +#define BIT_STC_INT_EN_8814B BIT(31) +#define BIT_SHIFT_STC_INT_FLAG_8814B 16 +#define BIT_MASK_STC_INT_FLAG_8814B 0xff +#define BIT_STC_INT_FLAG_8814B(x) \ + (((x) & BIT_MASK_STC_INT_FLAG_8814B) << BIT_SHIFT_STC_INT_FLAG_8814B) +#define BITS_STC_INT_FLAG_8814B \ + (BIT_MASK_STC_INT_FLAG_8814B << BIT_SHIFT_STC_INT_FLAG_8814B) +#define BIT_CLEAR_STC_INT_FLAG_8814B(x) ((x) & (~BITS_STC_INT_FLAG_8814B)) +#define BIT_GET_STC_INT_FLAG_8814B(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG_8814B) & BIT_MASK_STC_INT_FLAG_8814B) +#define BIT_SET_STC_INT_FLAG_8814B(x, v) \ + (BIT_CLEAR_STC_INT_FLAG_8814B(x) | BIT_STC_INT_FLAG_8814B(v)) -/* 2 REG_HI4Q_TXBD_DESA_8814B */ +#define BIT_SHIFT_STC_INT_IDX_8814B 8 +#define BIT_MASK_STC_INT_IDX_8814B 0x7 +#define BIT_STC_INT_IDX_8814B(x) \ + (((x) & BIT_MASK_STC_INT_IDX_8814B) << BIT_SHIFT_STC_INT_IDX_8814B) +#define BITS_STC_INT_IDX_8814B \ + (BIT_MASK_STC_INT_IDX_8814B << BIT_SHIFT_STC_INT_IDX_8814B) +#define BIT_CLEAR_STC_INT_IDX_8814B(x) ((x) & (~BITS_STC_INT_IDX_8814B)) +#define BIT_GET_STC_INT_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX_8814B) & BIT_MASK_STC_INT_IDX_8814B) +#define BIT_SET_STC_INT_IDX_8814B(x, v) \ + (BIT_CLEAR_STC_INT_IDX_8814B(x) | BIT_STC_INT_IDX_8814B(v)) -#define BIT_SHIFT_HI4Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI4Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI4Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8814B) << BIT_SHIFT_HI4Q_TXBD_DESA_8814B) -#define BIT_GET_HI4Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8814B) & BIT_MASK_HI4Q_TXBD_DESA_8814B) +#define BIT_SHIFT_STC_INT_REALTIME_CS_8814B 0 +#define BIT_MASK_STC_INT_REALTIME_CS_8814B 0x3f +#define BIT_STC_INT_REALTIME_CS_8814B(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS_8814B) \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8814B) +#define BITS_STC_INT_REALTIME_CS_8814B \ + (BIT_MASK_STC_INT_REALTIME_CS_8814B \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8814B) +#define BIT_CLEAR_STC_INT_REALTIME_CS_8814B(x) \ + ((x) & (~BITS_STC_INT_REALTIME_CS_8814B)) +#define BIT_GET_STC_INT_REALTIME_CS_8814B(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8814B) & \ + BIT_MASK_STC_INT_REALTIME_CS_8814B) +#define BIT_SET_STC_INT_REALTIME_CS_8814B(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS_8814B(x) | \ + BIT_STC_INT_REALTIME_CS_8814B(v)) +/* 2 REG_ST_INT_CFG_8814B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ +#define BIT_STC_INT_GRP_EN_8814B BIT(31) +#define BIT_SHIFT_STC_INT_EXPECT_LS_8814B 8 +#define BIT_MASK_STC_INT_EXPECT_LS_8814B 0x3f +#define BIT_STC_INT_EXPECT_LS_8814B(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS_8814B) \ + << BIT_SHIFT_STC_INT_EXPECT_LS_8814B) +#define BITS_STC_INT_EXPECT_LS_8814B \ + (BIT_MASK_STC_INT_EXPECT_LS_8814B << BIT_SHIFT_STC_INT_EXPECT_LS_8814B) +#define BIT_CLEAR_STC_INT_EXPECT_LS_8814B(x) \ + ((x) & (~BITS_STC_INT_EXPECT_LS_8814B)) +#define BIT_GET_STC_INT_EXPECT_LS_8814B(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8814B) & \ + BIT_MASK_STC_INT_EXPECT_LS_8814B) +#define BIT_SET_STC_INT_EXPECT_LS_8814B(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS_8814B(x) | BIT_STC_INT_EXPECT_LS_8814B(v)) -/* 2 REG_HI5Q_TXBD_DESA_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_HI5Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI5Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI5Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8814B) << BIT_SHIFT_HI5Q_TXBD_DESA_8814B) -#define BIT_GET_HI5Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8814B) & BIT_MASK_HI5Q_TXBD_DESA_8814B) +#define BIT_SHIFT_STC_INT_EXPECT_CS_8814B 0 +#define BIT_MASK_STC_INT_EXPECT_CS_8814B 0x3f +#define BIT_STC_INT_EXPECT_CS_8814B(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS_8814B) \ + << BIT_SHIFT_STC_INT_EXPECT_CS_8814B) +#define BITS_STC_INT_EXPECT_CS_8814B \ + (BIT_MASK_STC_INT_EXPECT_CS_8814B << BIT_SHIFT_STC_INT_EXPECT_CS_8814B) +#define BIT_CLEAR_STC_INT_EXPECT_CS_8814B(x) \ + ((x) & (~BITS_STC_INT_EXPECT_CS_8814B)) +#define BIT_GET_STC_INT_EXPECT_CS_8814B(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8814B) & \ + BIT_MASK_STC_INT_EXPECT_CS_8814B) +#define BIT_SET_STC_INT_EXPECT_CS_8814B(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS_8814B(x) | BIT_STC_INT_EXPECT_CS_8814B(v)) + +/* 2 REG_ACH4_ACH5_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH5_FLAG_8814B BIT(30) + +#define BIT_SHIFT_ACH5_DESC_MODE_8814B 28 +#define BIT_MASK_ACH5_DESC_MODE_8814B 0x3 +#define BIT_ACH5_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH5_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH5_DESC_MODE_8814B) +#define BITS_ACH5_DESC_MODE_8814B \ + (BIT_MASK_ACH5_DESC_MODE_8814B << BIT_SHIFT_ACH5_DESC_MODE_8814B) +#define BIT_CLEAR_ACH5_DESC_MODE_8814B(x) ((x) & (~BITS_ACH5_DESC_MODE_8814B)) +#define BIT_GET_ACH5_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_DESC_MODE_8814B) & \ + BIT_MASK_ACH5_DESC_MODE_8814B) +#define BIT_SET_ACH5_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH5_DESC_MODE_8814B(x) | BIT_ACH5_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH5_DESC_NUM_8814B 16 +#define BIT_MASK_ACH5_DESC_NUM_8814B 0xfff +#define BIT_ACH5_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH5_DESC_NUM_8814B) << BIT_SHIFT_ACH5_DESC_NUM_8814B) +#define BITS_ACH5_DESC_NUM_8814B \ + (BIT_MASK_ACH5_DESC_NUM_8814B << BIT_SHIFT_ACH5_DESC_NUM_8814B) +#define BIT_CLEAR_ACH5_DESC_NUM_8814B(x) ((x) & (~BITS_ACH5_DESC_NUM_8814B)) +#define BIT_GET_ACH5_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_DESC_NUM_8814B) & BIT_MASK_ACH5_DESC_NUM_8814B) +#define BIT_SET_ACH5_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH5_DESC_NUM_8814B(x) | BIT_ACH5_DESC_NUM_8814B(v)) + +#define BIT_PCIE_ACH4_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH4_DESC_MODE_8814B 12 +#define BIT_MASK_ACH4_DESC_MODE_8814B 0x3 +#define BIT_ACH4_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH4_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH4_DESC_MODE_8814B) +#define BITS_ACH4_DESC_MODE_8814B \ + (BIT_MASK_ACH4_DESC_MODE_8814B << BIT_SHIFT_ACH4_DESC_MODE_8814B) +#define BIT_CLEAR_ACH4_DESC_MODE_8814B(x) ((x) & (~BITS_ACH4_DESC_MODE_8814B)) +#define BIT_GET_ACH4_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_DESC_MODE_8814B) & \ + BIT_MASK_ACH4_DESC_MODE_8814B) +#define BIT_SET_ACH4_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH4_DESC_MODE_8814B(x) | BIT_ACH4_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH4_DESC_NUM_8814B 0 +#define BIT_MASK_ACH4_DESC_NUM_8814B 0xfff +#define BIT_ACH4_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH4_DESC_NUM_8814B) << BIT_SHIFT_ACH4_DESC_NUM_8814B) +#define BITS_ACH4_DESC_NUM_8814B \ + (BIT_MASK_ACH4_DESC_NUM_8814B << BIT_SHIFT_ACH4_DESC_NUM_8814B) +#define BIT_CLEAR_ACH4_DESC_NUM_8814B(x) ((x) & (~BITS_ACH4_DESC_NUM_8814B)) +#define BIT_GET_ACH4_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_DESC_NUM_8814B) & BIT_MASK_ACH4_DESC_NUM_8814B) +#define BIT_SET_ACH4_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH4_DESC_NUM_8814B(x) | BIT_ACH4_DESC_NUM_8814B(v)) + +/* 2 REG_FWCMDQ_TXBD_IDX_8814B */ + +#define BIT_SHIFT_FWCMDQ_HW_IDX_8814B 16 +#define BIT_MASK_FWCMDQ_HW_IDX_8814B 0xfff +#define BIT_FWCMDQ_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_HW_IDX_8814B) << BIT_SHIFT_FWCMDQ_HW_IDX_8814B) +#define BITS_FWCMDQ_HW_IDX_8814B \ + (BIT_MASK_FWCMDQ_HW_IDX_8814B << BIT_SHIFT_FWCMDQ_HW_IDX_8814B) +#define BIT_CLEAR_FWCMDQ_HW_IDX_8814B(x) ((x) & (~BITS_FWCMDQ_HW_IDX_8814B)) +#define BIT_GET_FWCMDQ_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HW_IDX_8814B) & BIT_MASK_FWCMDQ_HW_IDX_8814B) +#define BIT_SET_FWCMDQ_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_HW_IDX_8814B(x) | BIT_FWCMDQ_HW_IDX_8814B(v)) + +#define BIT_SHIFT_FWCMDQ_HOST_IDX_8814B 0 +#define BIT_MASK_FWCMDQ_HOST_IDX_8814B 0xfff +#define BIT_FWCMDQ_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_HOST_IDX_8814B) \ + << BIT_SHIFT_FWCMDQ_HOST_IDX_8814B) +#define BITS_FWCMDQ_HOST_IDX_8814B \ + (BIT_MASK_FWCMDQ_HOST_IDX_8814B << BIT_SHIFT_FWCMDQ_HOST_IDX_8814B) +#define BIT_CLEAR_FWCMDQ_HOST_IDX_8814B(x) ((x) & (~BITS_FWCMDQ_HOST_IDX_8814B)) +#define BIT_GET_FWCMDQ_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HOST_IDX_8814B) & \ + BIT_MASK_FWCMDQ_HOST_IDX_8814B) +#define BIT_SET_FWCMDQ_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_HOST_IDX_8814B(x) | BIT_FWCMDQ_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI8Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI8Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI8Q_HW_IDX_8814B 0xfff +#define BIT_P0HI8Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI8Q_HW_IDX_8814B) << BIT_SHIFT_P0HI8Q_HW_IDX_8814B) +#define BITS_P0HI8Q_HW_IDX_8814B \ + (BIT_MASK_P0HI8Q_HW_IDX_8814B << BIT_SHIFT_P0HI8Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI8Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI8Q_HW_IDX_8814B)) +#define BIT_GET_P0HI8Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_HW_IDX_8814B) & BIT_MASK_P0HI8Q_HW_IDX_8814B) +#define BIT_SET_P0HI8Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI8Q_HW_IDX_8814B(x) | BIT_P0HI8Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI8Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI8Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI8Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI8Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI8Q_HOST_IDX_8814B) +#define BITS_P0HI8Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI8Q_HOST_IDX_8814B << BIT_SHIFT_P0HI8Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI8Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI8Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI8Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI8Q_HOST_IDX_8814B) +#define BIT_SET_P0HI8Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI8Q_HOST_IDX_8814B(x) | BIT_P0HI8Q_HOST_IDX_8814B(v)) + +/* 2 REG_H2CQ_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B 0 +#define BIT_MASK_H2CQ_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_H2CQ_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B) +#define BITS_H2CQ_TXBD_DESA_L_8814B \ + (BIT_MASK_H2CQ_TXBD_DESA_L_8814B << BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B) +#define BIT_CLEAR_H2CQ_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_H2CQ_TXBD_DESA_L_8814B)) +#define BIT_GET_H2CQ_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B) & \ + BIT_MASK_H2CQ_TXBD_DESA_L_8814B) +#define BIT_SET_H2CQ_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_L_8814B(x) | BIT_H2CQ_TXBD_DESA_L_8814B(v)) + +/* 2 REG_H2CQ_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B 0 +#define BIT_MASK_H2CQ_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_H2CQ_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B) +#define BITS_H2CQ_TXBD_DESA_H_8814B \ + (BIT_MASK_H2CQ_TXBD_DESA_H_8814B << BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B) +#define BIT_CLEAR_H2CQ_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_H2CQ_TXBD_DESA_H_8814B)) +#define BIT_GET_H2CQ_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B) & \ + BIT_MASK_H2CQ_TXBD_DESA_H_8814B) +#define BIT_SET_H2CQ_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_H_8814B(x) | BIT_H2CQ_TXBD_DESA_H_8814B(v)) +/* 2 REG_H2CQ_TXBD_NUM_8814B */ +#define BIT_PCIE_H2CQ_FLAG_8814B BIT(14) +#define BIT_SHIFT_H2CQ_DESC_MODE_8814B 12 +#define BIT_MASK_H2CQ_DESC_MODE_8814B 0x3 +#define BIT_H2CQ_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE_8814B) \ + << BIT_SHIFT_H2CQ_DESC_MODE_8814B) +#define BITS_H2CQ_DESC_MODE_8814B \ + (BIT_MASK_H2CQ_DESC_MODE_8814B << BIT_SHIFT_H2CQ_DESC_MODE_8814B) +#define BIT_CLEAR_H2CQ_DESC_MODE_8814B(x) ((x) & (~BITS_H2CQ_DESC_MODE_8814B)) +#define BIT_GET_H2CQ_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8814B) & \ + BIT_MASK_H2CQ_DESC_MODE_8814B) +#define BIT_SET_H2CQ_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE_8814B(x) | BIT_H2CQ_DESC_MODE_8814B(v)) -/* 2 REG_HI6Q_TXBD_DESA_8814B */ +#define BIT_SHIFT_H2CQ_DESC_NUM_8814B 0 +#define BIT_MASK_H2CQ_DESC_NUM_8814B 0xfff +#define BIT_H2CQ_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM_8814B) << BIT_SHIFT_H2CQ_DESC_NUM_8814B) +#define BITS_H2CQ_DESC_NUM_8814B \ + (BIT_MASK_H2CQ_DESC_NUM_8814B << BIT_SHIFT_H2CQ_DESC_NUM_8814B) +#define BIT_CLEAR_H2CQ_DESC_NUM_8814B(x) ((x) & (~BITS_H2CQ_DESC_NUM_8814B)) +#define BIT_GET_H2CQ_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8814B) & BIT_MASK_H2CQ_DESC_NUM_8814B) +#define BIT_SET_H2CQ_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM_8814B(x) | BIT_H2CQ_DESC_NUM_8814B(v)) -#define BIT_SHIFT_HI6Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI6Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI6Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8814B) << BIT_SHIFT_HI6Q_TXBD_DESA_8814B) -#define BIT_GET_HI6Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8814B) & BIT_MASK_HI6Q_TXBD_DESA_8814B) +/* 2 REG_H2CQ_TXBD_IDX_8814B */ +#define BIT_SHIFT_H2CQ_HW_IDX_8814B 16 +#define BIT_MASK_H2CQ_HW_IDX_8814B 0xfff +#define BIT_H2CQ_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX_8814B) << BIT_SHIFT_H2CQ_HW_IDX_8814B) +#define BITS_H2CQ_HW_IDX_8814B \ + (BIT_MASK_H2CQ_HW_IDX_8814B << BIT_SHIFT_H2CQ_HW_IDX_8814B) +#define BIT_CLEAR_H2CQ_HW_IDX_8814B(x) ((x) & (~BITS_H2CQ_HW_IDX_8814B)) +#define BIT_GET_H2CQ_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8814B) & BIT_MASK_H2CQ_HW_IDX_8814B) +#define BIT_SET_H2CQ_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX_8814B(x) | BIT_H2CQ_HW_IDX_8814B(v)) +#define BIT_SHIFT_H2CQ_HOST_IDX_8814B 0 +#define BIT_MASK_H2CQ_HOST_IDX_8814B 0xfff +#define BIT_H2CQ_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX_8814B) << BIT_SHIFT_H2CQ_HOST_IDX_8814B) +#define BITS_H2CQ_HOST_IDX_8814B \ + (BIT_MASK_H2CQ_HOST_IDX_8814B << BIT_SHIFT_H2CQ_HOST_IDX_8814B) +#define BIT_CLEAR_H2CQ_HOST_IDX_8814B(x) ((x) & (~BITS_H2CQ_HOST_IDX_8814B)) +#define BIT_GET_H2CQ_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8814B) & BIT_MASK_H2CQ_HOST_IDX_8814B) +#define BIT_SET_H2CQ_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX_8814B(x) | BIT_H2CQ_HOST_IDX_8814B(v)) -/* 2 REG_HI7Q_TXBD_DESA_8814B */ +/* 2 REG_H2CQ_CSR_8814B[31:0] (H2CQ CONTROL AND STATUS) */ +#define BIT_H2CQ_FULL_8814B BIT(31) +#define BIT_CLR_H2CQ_HOST_IDX_8814B BIT(16) +#define BIT_CLR_H2CQ_HW_IDX_8814B BIT(8) +#define BIT_STOP_H2CQ_8814B BIT(0) + +/* 2 REG_P0HI9Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI9Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI9Q_HW_IDX_8814B 0xfff +#define BIT_P0HI9Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI9Q_HW_IDX_8814B) << BIT_SHIFT_P0HI9Q_HW_IDX_8814B) +#define BITS_P0HI9Q_HW_IDX_8814B \ + (BIT_MASK_P0HI9Q_HW_IDX_8814B << BIT_SHIFT_P0HI9Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI9Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI9Q_HW_IDX_8814B)) +#define BIT_GET_P0HI9Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_HW_IDX_8814B) & BIT_MASK_P0HI9Q_HW_IDX_8814B) +#define BIT_SET_P0HI9Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI9Q_HW_IDX_8814B(x) | BIT_P0HI9Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI9Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI9Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI9Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI9Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI9Q_HOST_IDX_8814B) +#define BITS_P0HI9Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI9Q_HOST_IDX_8814B << BIT_SHIFT_P0HI9Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI9Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI9Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI9Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI9Q_HOST_IDX_8814B) +#define BIT_SET_P0HI9Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI9Q_HOST_IDX_8814B(x) | BIT_P0HI9Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI10Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI10Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI10Q_HW_IDX_8814B 0xfff +#define BIT_P0HI10Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI10Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI10Q_HW_IDX_8814B) +#define BITS_P0HI10Q_HW_IDX_8814B \ + (BIT_MASK_P0HI10Q_HW_IDX_8814B << BIT_SHIFT_P0HI10Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI10Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI10Q_HW_IDX_8814B)) +#define BIT_GET_P0HI10Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI10Q_HW_IDX_8814B) +#define BIT_SET_P0HI10Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI10Q_HW_IDX_8814B(x) | BIT_P0HI10Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI10Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI10Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI10Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI10Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI10Q_HOST_IDX_8814B) +#define BITS_P0HI10Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI10Q_HOST_IDX_8814B << BIT_SHIFT_P0HI10Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI10Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI10Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI10Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI10Q_HOST_IDX_8814B) +#define BIT_SET_P0HI10Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI10Q_HOST_IDX_8814B(x) | BIT_P0HI10Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI11Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI11Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI11Q_HW_IDX_8814B 0xfff +#define BIT_P0HI11Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI11Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI11Q_HW_IDX_8814B) +#define BITS_P0HI11Q_HW_IDX_8814B \ + (BIT_MASK_P0HI11Q_HW_IDX_8814B << BIT_SHIFT_P0HI11Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI11Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI11Q_HW_IDX_8814B)) +#define BIT_GET_P0HI11Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI11Q_HW_IDX_8814B) +#define BIT_SET_P0HI11Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI11Q_HW_IDX_8814B(x) | BIT_P0HI11Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI11Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI11Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI11Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI11Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI11Q_HOST_IDX_8814B) +#define BITS_P0HI11Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI11Q_HOST_IDX_8814B << BIT_SHIFT_P0HI11Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI11Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI11Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI11Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI11Q_HOST_IDX_8814B) +#define BIT_SET_P0HI11Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI11Q_HOST_IDX_8814B(x) | BIT_P0HI11Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI12Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI12Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI12Q_HW_IDX_8814B 0xfff +#define BIT_P0HI12Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI12Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI12Q_HW_IDX_8814B) +#define BITS_P0HI12Q_HW_IDX_8814B \ + (BIT_MASK_P0HI12Q_HW_IDX_8814B << BIT_SHIFT_P0HI12Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI12Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI12Q_HW_IDX_8814B)) +#define BIT_GET_P0HI12Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI12Q_HW_IDX_8814B) +#define BIT_SET_P0HI12Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI12Q_HW_IDX_8814B(x) | BIT_P0HI12Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI12Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI12Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI12Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI12Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI12Q_HOST_IDX_8814B) +#define BITS_P0HI12Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI12Q_HOST_IDX_8814B << BIT_SHIFT_P0HI12Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI12Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI12Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI12Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI12Q_HOST_IDX_8814B) +#define BIT_SET_P0HI12Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI12Q_HOST_IDX_8814B(x) | BIT_P0HI12Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI13Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI13Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI13Q_HW_IDX_8814B 0xfff +#define BIT_P0HI13Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI13Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI13Q_HW_IDX_8814B) +#define BITS_P0HI13Q_HW_IDX_8814B \ + (BIT_MASK_P0HI13Q_HW_IDX_8814B << BIT_SHIFT_P0HI13Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI13Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI13Q_HW_IDX_8814B)) +#define BIT_GET_P0HI13Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI13Q_HW_IDX_8814B) +#define BIT_SET_P0HI13Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI13Q_HW_IDX_8814B(x) | BIT_P0HI13Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI13Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI13Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI13Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI13Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI13Q_HOST_IDX_8814B) +#define BITS_P0HI13Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI13Q_HOST_IDX_8814B << BIT_SHIFT_P0HI13Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI13Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI13Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI13Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI13Q_HOST_IDX_8814B) +#define BIT_SET_P0HI13Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI13Q_HOST_IDX_8814B(x) | BIT_P0HI13Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI14Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI14Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI14Q_HW_IDX_8814B 0xfff +#define BIT_P0HI14Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI14Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI14Q_HW_IDX_8814B) +#define BITS_P0HI14Q_HW_IDX_8814B \ + (BIT_MASK_P0HI14Q_HW_IDX_8814B << BIT_SHIFT_P0HI14Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI14Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI14Q_HW_IDX_8814B)) +#define BIT_GET_P0HI14Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI14Q_HW_IDX_8814B) +#define BIT_SET_P0HI14Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI14Q_HW_IDX_8814B(x) | BIT_P0HI14Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI14Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI14Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI14Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI14Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI14Q_HOST_IDX_8814B) +#define BITS_P0HI14Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI14Q_HOST_IDX_8814B << BIT_SHIFT_P0HI14Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI14Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI14Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI14Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI14Q_HOST_IDX_8814B) +#define BIT_SET_P0HI14Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI14Q_HOST_IDX_8814B(x) | BIT_P0HI14Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI15Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI15Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI15Q_HW_IDX_8814B 0xfff +#define BIT_P0HI15Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI15Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI15Q_HW_IDX_8814B) +#define BITS_P0HI15Q_HW_IDX_8814B \ + (BIT_MASK_P0HI15Q_HW_IDX_8814B << BIT_SHIFT_P0HI15Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI15Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI15Q_HW_IDX_8814B)) +#define BIT_GET_P0HI15Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI15Q_HW_IDX_8814B) +#define BIT_SET_P0HI15Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI15Q_HW_IDX_8814B(x) | BIT_P0HI15Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI15Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI15Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI15Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI15Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI15Q_HOST_IDX_8814B) +#define BITS_P0HI15Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI15Q_HOST_IDX_8814B << BIT_SHIFT_P0HI15Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI15Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI15Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI15Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI15Q_HOST_IDX_8814B) +#define BIT_SET_P0HI15Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI15Q_HOST_IDX_8814B(x) | BIT_P0HI15Q_HOST_IDX_8814B(v)) + +/* 2 REG_CHANGE_PCIE_SPEED_8814B */ -#define BIT_SHIFT_HI7Q_TXBD_DESA_8814B 0 -#define BIT_MASK_HI7Q_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_HI7Q_TXBD_DESA_8814B(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8814B) << BIT_SHIFT_HI7Q_TXBD_DESA_8814B) -#define BIT_GET_HI7Q_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8814B) & BIT_MASK_HI7Q_TXBD_DESA_8814B) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_RXDMA_ERR_CNT_8814B 8 +#define BIT_MASK_RXDMA_ERR_CNT_8814B 0xff +#define BIT_RXDMA_ERR_CNT_8814B(x) \ + (((x) & BIT_MASK_RXDMA_ERR_CNT_8814B) << BIT_SHIFT_RXDMA_ERR_CNT_8814B) +#define BITS_RXDMA_ERR_CNT_8814B \ + (BIT_MASK_RXDMA_ERR_CNT_8814B << BIT_SHIFT_RXDMA_ERR_CNT_8814B) +#define BIT_CLEAR_RXDMA_ERR_CNT_8814B(x) ((x) & (~BITS_RXDMA_ERR_CNT_8814B)) +#define BIT_GET_RXDMA_ERR_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_RXDMA_ERR_CNT_8814B) & BIT_MASK_RXDMA_ERR_CNT_8814B) +#define BIT_SET_RXDMA_ERR_CNT_8814B(x, v) \ + (BIT_CLEAR_RXDMA_ERR_CNT_8814B(x) | BIT_RXDMA_ERR_CNT_8814B(v)) + +#define BIT_TXDMA_ERR_HANDLE_REQ_8814B BIT(7) +#define BIT_TXDMA_ERROR_PS_8814B BIT(6) +#define BIT_EN_TXDMA_STUCK_ERR_HANDLE_8814B BIT(5) +#define BIT_EN_TXDMA_RTN_ERR_HANDLE_8814B BIT(4) +#define BIT_RXDMA_ERR_HANDLE_REQ_8814B BIT(3) +#define BIT_RXDMA_ERROR_PS_8814B BIT(2) +#define BIT_EN_RXDMA_STUCK_ERR_HANDLE_8814B BIT(1) +#define BIT_EN_RXDMA_RTN_ERR_HANDLE_8814B BIT(0) + +/* 2 REG_DEBUG_STATE1_8814B */ + +#define BIT_SHIFT_DEBUG_STATE1_8814B 0 +#define BIT_MASK_DEBUG_STATE1_8814B 0xffffffffL +#define BIT_DEBUG_STATE1_8814B(x) \ + (((x) & BIT_MASK_DEBUG_STATE1_8814B) << BIT_SHIFT_DEBUG_STATE1_8814B) +#define BITS_DEBUG_STATE1_8814B \ + (BIT_MASK_DEBUG_STATE1_8814B << BIT_SHIFT_DEBUG_STATE1_8814B) +#define BIT_CLEAR_DEBUG_STATE1_8814B(x) ((x) & (~BITS_DEBUG_STATE1_8814B)) +#define BIT_GET_DEBUG_STATE1_8814B(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE1_8814B) & BIT_MASK_DEBUG_STATE1_8814B) +#define BIT_SET_DEBUG_STATE1_8814B(x, v) \ + (BIT_CLEAR_DEBUG_STATE1_8814B(x) | BIT_DEBUG_STATE1_8814B(v)) + +/* 2 REG_DEBUG_STATE2_8814B */ + +#define BIT_SHIFT_DEBUG_STATE2_8814B 0 +#define BIT_MASK_DEBUG_STATE2_8814B 0xffffffffL +#define BIT_DEBUG_STATE2_8814B(x) \ + (((x) & BIT_MASK_DEBUG_STATE2_8814B) << BIT_SHIFT_DEBUG_STATE2_8814B) +#define BITS_DEBUG_STATE2_8814B \ + (BIT_MASK_DEBUG_STATE2_8814B << BIT_SHIFT_DEBUG_STATE2_8814B) +#define BIT_CLEAR_DEBUG_STATE2_8814B(x) ((x) & (~BITS_DEBUG_STATE2_8814B)) +#define BIT_GET_DEBUG_STATE2_8814B(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE2_8814B) & BIT_MASK_DEBUG_STATE2_8814B) +#define BIT_SET_DEBUG_STATE2_8814B(x, v) \ + (BIT_CLEAR_DEBUG_STATE2_8814B(x) | BIT_DEBUG_STATE2_8814B(v)) + +/* 2 REG_DEBUG_STATE3_8814B */ + +#define BIT_SHIFT_DEBUG_STATE3_8814B 0 +#define BIT_MASK_DEBUG_STATE3_8814B 0xffffffffL +#define BIT_DEBUG_STATE3_8814B(x) \ + (((x) & BIT_MASK_DEBUG_STATE3_8814B) << BIT_SHIFT_DEBUG_STATE3_8814B) +#define BITS_DEBUG_STATE3_8814B \ + (BIT_MASK_DEBUG_STATE3_8814B << BIT_SHIFT_DEBUG_STATE3_8814B) +#define BIT_CLEAR_DEBUG_STATE3_8814B(x) ((x) & (~BITS_DEBUG_STATE3_8814B)) +#define BIT_GET_DEBUG_STATE3_8814B(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE3_8814B) & BIT_MASK_DEBUG_STATE3_8814B) +#define BIT_SET_DEBUG_STATE3_8814B(x, v) \ + (BIT_CLEAR_DEBUG_STATE3_8814B(x) | BIT_DEBUG_STATE3_8814B(v)) + +/* 2 REG_ACH5_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH5_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH5_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH5_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH5_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH5_TXBD_DESA_L_8814B) +#define BITS_ACH5_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH5_TXBD_DESA_L_8814B << BIT_SHIFT_ACH5_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH5_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH5_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH5_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH5_TXBD_DESA_L_8814B) +#define BIT_SET_ACH5_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH5_TXBD_DESA_L_8814B(x) | BIT_ACH5_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH5_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH5_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH5_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH5_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH5_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH5_TXBD_DESA_H_8814B) +#define BITS_ACH5_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH5_TXBD_DESA_H_8814B << BIT_SHIFT_ACH5_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH5_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH5_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH5_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH5_TXBD_DESA_H_8814B) +#define BIT_SET_ACH5_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH5_TXBD_DESA_H_8814B(x) | BIT_ACH5_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH6_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH6_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH6_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH6_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH6_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH6_TXBD_DESA_L_8814B) +#define BITS_ACH6_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH6_TXBD_DESA_L_8814B << BIT_SHIFT_ACH6_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH6_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH6_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH6_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH6_TXBD_DESA_L_8814B) +#define BIT_SET_ACH6_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH6_TXBD_DESA_L_8814B(x) | BIT_ACH6_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH6_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH6_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH6_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH6_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH6_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH6_TXBD_DESA_H_8814B) +#define BITS_ACH6_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH6_TXBD_DESA_H_8814B << BIT_SHIFT_ACH6_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH6_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH6_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH6_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH6_TXBD_DESA_H_8814B) +#define BIT_SET_ACH6_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH6_TXBD_DESA_H_8814B(x) | BIT_ACH6_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH7_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH7_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH7_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH7_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH7_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH7_TXBD_DESA_L_8814B) +#define BITS_ACH7_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH7_TXBD_DESA_L_8814B << BIT_SHIFT_ACH7_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH7_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH7_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH7_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH7_TXBD_DESA_L_8814B) +#define BIT_SET_ACH7_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH7_TXBD_DESA_L_8814B(x) | BIT_ACH7_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH7_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH7_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH7_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH7_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH7_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH7_TXBD_DESA_H_8814B) +#define BITS_ACH7_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH7_TXBD_DESA_H_8814B << BIT_SHIFT_ACH7_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH7_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH7_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH7_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH7_TXBD_DESA_H_8814B) +#define BIT_SET_ACH7_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH7_TXBD_DESA_H_8814B(x) | BIT_ACH7_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH8_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH8_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH8_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH8_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH8_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH8_TXBD_DESA_L_8814B) +#define BITS_ACH8_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH8_TXBD_DESA_L_8814B << BIT_SHIFT_ACH8_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH8_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH8_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH8_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH8_TXBD_DESA_L_8814B) +#define BIT_SET_ACH8_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH8_TXBD_DESA_L_8814B(x) | BIT_ACH8_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH8_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH8_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH8_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH8_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH8_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH8_TXBD_DESA_H_8814B) +#define BITS_ACH8_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH8_TXBD_DESA_H_8814B << BIT_SHIFT_ACH8_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH8_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH8_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH8_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH8_TXBD_DESA_H_8814B) +#define BIT_SET_ACH8_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH8_TXBD_DESA_H_8814B(x) | BIT_ACH8_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH9_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH9_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH9_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH9_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH9_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH9_TXBD_DESA_L_8814B) +#define BITS_ACH9_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH9_TXBD_DESA_L_8814B << BIT_SHIFT_ACH9_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH9_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH9_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH9_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH9_TXBD_DESA_L_8814B) +#define BIT_SET_ACH9_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH9_TXBD_DESA_L_8814B(x) | BIT_ACH9_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH9_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH9_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH9_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH9_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH9_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH9_TXBD_DESA_H_8814B) +#define BITS_ACH9_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH9_TXBD_DESA_H_8814B << BIT_SHIFT_ACH9_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH9_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH9_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH9_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH9_TXBD_DESA_H_8814B) +#define BIT_SET_ACH9_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH9_TXBD_DESA_H_8814B(x) | BIT_ACH9_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH10_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH10_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH10_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH10_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH10_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH10_TXBD_DESA_L_8814B) +#define BITS_ACH10_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH10_TXBD_DESA_L_8814B << BIT_SHIFT_ACH10_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH10_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH10_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH10_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH10_TXBD_DESA_L_8814B) +#define BIT_SET_ACH10_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH10_TXBD_DESA_L_8814B(x) | BIT_ACH10_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH10_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH10_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH10_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH10_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH10_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH10_TXBD_DESA_H_8814B) +#define BITS_ACH10_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH10_TXBD_DESA_H_8814B << BIT_SHIFT_ACH10_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH10_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH10_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH10_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH10_TXBD_DESA_H_8814B) +#define BIT_SET_ACH10_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH10_TXBD_DESA_H_8814B(x) | BIT_ACH10_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH11_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH11_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH11_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH11_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH11_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH11_TXBD_DESA_L_8814B) +#define BITS_ACH11_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH11_TXBD_DESA_L_8814B << BIT_SHIFT_ACH11_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH11_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH11_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH11_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH11_TXBD_DESA_L_8814B) +#define BIT_SET_ACH11_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH11_TXBD_DESA_L_8814B(x) | BIT_ACH11_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH11_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH11_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH11_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH11_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH11_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH11_TXBD_DESA_H_8814B) +#define BITS_ACH11_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH11_TXBD_DESA_H_8814B << BIT_SHIFT_ACH11_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH11_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH11_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH11_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH11_TXBD_DESA_H_8814B) +#define BIT_SET_ACH11_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH11_TXBD_DESA_H_8814B(x) | BIT_ACH11_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH12_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH12_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH12_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH12_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH12_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH12_TXBD_DESA_L_8814B) +#define BITS_ACH12_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH12_TXBD_DESA_L_8814B << BIT_SHIFT_ACH12_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH12_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH12_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH12_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH12_TXBD_DESA_L_8814B) +#define BIT_SET_ACH12_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH12_TXBD_DESA_L_8814B(x) | BIT_ACH12_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH12_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH12_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH12_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH12_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH12_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH12_TXBD_DESA_H_8814B) +#define BITS_ACH12_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH12_TXBD_DESA_H_8814B << BIT_SHIFT_ACH12_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH12_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH12_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH12_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH12_TXBD_DESA_H_8814B) +#define BIT_SET_ACH12_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH12_TXBD_DESA_H_8814B(x) | BIT_ACH12_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH13_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH13_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH13_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH13_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH13_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH13_TXBD_DESA_L_8814B) +#define BITS_ACH13_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH13_TXBD_DESA_L_8814B << BIT_SHIFT_ACH13_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH13_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH13_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH13_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH13_TXBD_DESA_L_8814B) +#define BIT_SET_ACH13_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH13_TXBD_DESA_L_8814B(x) | BIT_ACH13_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH13_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH13_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH13_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH13_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH13_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH13_TXBD_DESA_H_8814B) +#define BITS_ACH13_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH13_TXBD_DESA_H_8814B << BIT_SHIFT_ACH13_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH13_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH13_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH13_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH13_TXBD_DESA_H_8814B) +#define BIT_SET_ACH13_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH13_TXBD_DESA_H_8814B(x) | BIT_ACH13_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI0Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI0Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI0Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B) +#define BITS_HI0Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI0Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI0Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI0Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI0Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI0Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI0Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_L_8814B(x) | BIT_HI0Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI0Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI0Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI0Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B) +#define BITS_HI0Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI0Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI0Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI0Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI0Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI0Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI0Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_H_8814B(x) | BIT_HI0Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI1Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI1Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI1Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B) +#define BITS_HI1Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI1Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI1Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI1Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI1Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI1Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI1Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_L_8814B(x) | BIT_HI1Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI1Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI1Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI1Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B) +#define BITS_HI1Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI1Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI1Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI1Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI1Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI1Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI1Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_H_8814B(x) | BIT_HI1Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI2Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI2Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI2Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B) +#define BITS_HI2Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI2Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI2Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI2Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI2Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI2Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI2Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_L_8814B(x) | BIT_HI2Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI2Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI2Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI2Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B) +#define BITS_HI2Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI2Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI2Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI2Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI2Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI2Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI2Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_H_8814B(x) | BIT_HI2Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI3Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI3Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI3Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B) +#define BITS_HI3Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI3Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI3Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI3Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI3Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI3Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI3Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_L_8814B(x) | BIT_HI3Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI3Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI3Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI3Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B) +#define BITS_HI3Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI3Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI3Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI3Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI3Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI3Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI3Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_H_8814B(x) | BIT_HI3Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI4Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI4Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI4Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B) +#define BITS_HI4Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI4Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI4Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI4Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI4Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI4Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI4Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_L_8814B(x) | BIT_HI4Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI4Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI4Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI4Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B) +#define BITS_HI4Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI4Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI4Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI4Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI4Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI4Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI4Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_H_8814B(x) | BIT_HI4Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI5Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI5Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI5Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B) +#define BITS_HI5Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI5Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI5Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI5Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI5Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI5Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI5Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_L_8814B(x) | BIT_HI5Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI5Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI5Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI5Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B) +#define BITS_HI5Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI5Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI5Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI5Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI5Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI5Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI5Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_H_8814B(x) | BIT_HI5Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI6Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI6Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI6Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B) +#define BITS_HI6Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI6Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI6Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI6Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI6Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI6Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI6Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_L_8814B(x) | BIT_HI6Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI6Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI6Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI6Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B) +#define BITS_HI6Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI6Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI6Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI6Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI6Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI6Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI6Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_H_8814B(x) | BIT_HI6Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI7Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI7Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI7Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B) +#define BITS_HI7Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI7Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI7Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI7Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI7Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI7Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI7Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_L_8814B(x) | BIT_HI7Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI7Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI7Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI7Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B) +#define BITS_HI7Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI7Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI7Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI7Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI7Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI7Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI7Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_H_8814B(x) | BIT_HI7Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_ACH8_ACH9_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH9_FLAG_8814B BIT(30) + +#define BIT_SHIFT_ACH9_DESC_MODE_8814B 28 +#define BIT_MASK_ACH9_DESC_MODE_8814B 0x3 +#define BIT_ACH9_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH9_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH9_DESC_MODE_8814B) +#define BITS_ACH9_DESC_MODE_8814B \ + (BIT_MASK_ACH9_DESC_MODE_8814B << BIT_SHIFT_ACH9_DESC_MODE_8814B) +#define BIT_CLEAR_ACH9_DESC_MODE_8814B(x) ((x) & (~BITS_ACH9_DESC_MODE_8814B)) +#define BIT_GET_ACH9_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_DESC_MODE_8814B) & \ + BIT_MASK_ACH9_DESC_MODE_8814B) +#define BIT_SET_ACH9_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH9_DESC_MODE_8814B(x) | BIT_ACH9_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH9_DESC_NUM_8814B 16 +#define BIT_MASK_ACH9_DESC_NUM_8814B 0xfff +#define BIT_ACH9_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH9_DESC_NUM_8814B) << BIT_SHIFT_ACH9_DESC_NUM_8814B) +#define BITS_ACH9_DESC_NUM_8814B \ + (BIT_MASK_ACH9_DESC_NUM_8814B << BIT_SHIFT_ACH9_DESC_NUM_8814B) +#define BIT_CLEAR_ACH9_DESC_NUM_8814B(x) ((x) & (~BITS_ACH9_DESC_NUM_8814B)) +#define BIT_GET_ACH9_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_DESC_NUM_8814B) & BIT_MASK_ACH9_DESC_NUM_8814B) +#define BIT_SET_ACH9_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH9_DESC_NUM_8814B(x) | BIT_ACH9_DESC_NUM_8814B(v)) + +#define BIT_PCIE_ACH8_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH8_DESC_MODE_8814B 12 +#define BIT_MASK_ACH8_DESC_MODE_8814B 0x3 +#define BIT_ACH8_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH8_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH8_DESC_MODE_8814B) +#define BITS_ACH8_DESC_MODE_8814B \ + (BIT_MASK_ACH8_DESC_MODE_8814B << BIT_SHIFT_ACH8_DESC_MODE_8814B) +#define BIT_CLEAR_ACH8_DESC_MODE_8814B(x) ((x) & (~BITS_ACH8_DESC_MODE_8814B)) +#define BIT_GET_ACH8_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_DESC_MODE_8814B) & \ + BIT_MASK_ACH8_DESC_MODE_8814B) +#define BIT_SET_ACH8_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH8_DESC_MODE_8814B(x) | BIT_ACH8_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH8_DESC_NUM_8814B 0 +#define BIT_MASK_ACH8_DESC_NUM_8814B 0xfff +#define BIT_ACH8_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH8_DESC_NUM_8814B) << BIT_SHIFT_ACH8_DESC_NUM_8814B) +#define BITS_ACH8_DESC_NUM_8814B \ + (BIT_MASK_ACH8_DESC_NUM_8814B << BIT_SHIFT_ACH8_DESC_NUM_8814B) +#define BIT_CLEAR_ACH8_DESC_NUM_8814B(x) ((x) & (~BITS_ACH8_DESC_NUM_8814B)) +#define BIT_GET_ACH8_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_DESC_NUM_8814B) & BIT_MASK_ACH8_DESC_NUM_8814B) +#define BIT_SET_ACH8_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH8_DESC_NUM_8814B(x) | BIT_ACH8_DESC_NUM_8814B(v)) + +/* 2 REG_ACH10_ACH11_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH11_FLAG_8814B BIT(30) + +#define BIT_SHIFT_ACH11_DESC_MODE_8814B 28 +#define BIT_MASK_ACH11_DESC_MODE_8814B 0x3 +#define BIT_ACH11_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH11_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH11_DESC_MODE_8814B) +#define BITS_ACH11_DESC_MODE_8814B \ + (BIT_MASK_ACH11_DESC_MODE_8814B << BIT_SHIFT_ACH11_DESC_MODE_8814B) +#define BIT_CLEAR_ACH11_DESC_MODE_8814B(x) ((x) & (~BITS_ACH11_DESC_MODE_8814B)) +#define BIT_GET_ACH11_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_DESC_MODE_8814B) & \ + BIT_MASK_ACH11_DESC_MODE_8814B) +#define BIT_SET_ACH11_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH11_DESC_MODE_8814B(x) | BIT_ACH11_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH11_DESC_NUM_8814B 16 +#define BIT_MASK_ACH11_DESC_NUM_8814B 0xfff +#define BIT_ACH11_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH11_DESC_NUM_8814B) \ + << BIT_SHIFT_ACH11_DESC_NUM_8814B) +#define BITS_ACH11_DESC_NUM_8814B \ + (BIT_MASK_ACH11_DESC_NUM_8814B << BIT_SHIFT_ACH11_DESC_NUM_8814B) +#define BIT_CLEAR_ACH11_DESC_NUM_8814B(x) ((x) & (~BITS_ACH11_DESC_NUM_8814B)) +#define BIT_GET_ACH11_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_DESC_NUM_8814B) & \ + BIT_MASK_ACH11_DESC_NUM_8814B) +#define BIT_SET_ACH11_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH11_DESC_NUM_8814B(x) | BIT_ACH11_DESC_NUM_8814B(v)) + +#define BIT_PCIE_ACH10_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH10_DESC_MODE_8814B 12 +#define BIT_MASK_ACH10_DESC_MODE_8814B 0x3 +#define BIT_ACH10_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH10_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH10_DESC_MODE_8814B) +#define BITS_ACH10_DESC_MODE_8814B \ + (BIT_MASK_ACH10_DESC_MODE_8814B << BIT_SHIFT_ACH10_DESC_MODE_8814B) +#define BIT_CLEAR_ACH10_DESC_MODE_8814B(x) ((x) & (~BITS_ACH10_DESC_MODE_8814B)) +#define BIT_GET_ACH10_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_DESC_MODE_8814B) & \ + BIT_MASK_ACH10_DESC_MODE_8814B) +#define BIT_SET_ACH10_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH10_DESC_MODE_8814B(x) | BIT_ACH10_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH10_DESC_NUM_8814B 0 +#define BIT_MASK_ACH10_DESC_NUM_8814B 0xfff +#define BIT_ACH10_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH10_DESC_NUM_8814B) \ + << BIT_SHIFT_ACH10_DESC_NUM_8814B) +#define BITS_ACH10_DESC_NUM_8814B \ + (BIT_MASK_ACH10_DESC_NUM_8814B << BIT_SHIFT_ACH10_DESC_NUM_8814B) +#define BIT_CLEAR_ACH10_DESC_NUM_8814B(x) ((x) & (~BITS_ACH10_DESC_NUM_8814B)) +#define BIT_GET_ACH10_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_DESC_NUM_8814B) & \ + BIT_MASK_ACH10_DESC_NUM_8814B) +#define BIT_SET_ACH10_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH10_DESC_NUM_8814B(x) | BIT_ACH10_DESC_NUM_8814B(v)) + +/* 2 REG_ACH12_ACH13_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH13_FLAG_8814B BIT(30) + +#define BIT_SHIFT_ACH13_DESC_MODE_8814B 28 +#define BIT_MASK_ACH13_DESC_MODE_8814B 0x3 +#define BIT_ACH13_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH13_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH13_DESC_MODE_8814B) +#define BITS_ACH13_DESC_MODE_8814B \ + (BIT_MASK_ACH13_DESC_MODE_8814B << BIT_SHIFT_ACH13_DESC_MODE_8814B) +#define BIT_CLEAR_ACH13_DESC_MODE_8814B(x) ((x) & (~BITS_ACH13_DESC_MODE_8814B)) +#define BIT_GET_ACH13_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_DESC_MODE_8814B) & \ + BIT_MASK_ACH13_DESC_MODE_8814B) +#define BIT_SET_ACH13_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH13_DESC_MODE_8814B(x) | BIT_ACH13_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH13_DESC_NUM_8814B 16 +#define BIT_MASK_ACH13_DESC_NUM_8814B 0xfff +#define BIT_ACH13_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH13_DESC_NUM_8814B) \ + << BIT_SHIFT_ACH13_DESC_NUM_8814B) +#define BITS_ACH13_DESC_NUM_8814B \ + (BIT_MASK_ACH13_DESC_NUM_8814B << BIT_SHIFT_ACH13_DESC_NUM_8814B) +#define BIT_CLEAR_ACH13_DESC_NUM_8814B(x) ((x) & (~BITS_ACH13_DESC_NUM_8814B)) +#define BIT_GET_ACH13_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_DESC_NUM_8814B) & \ + BIT_MASK_ACH13_DESC_NUM_8814B) +#define BIT_SET_ACH13_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH13_DESC_NUM_8814B(x) | BIT_ACH13_DESC_NUM_8814B(v)) + +#define BIT_PCIE_ACH12_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH12_DESC_MODE_8814B 12 +#define BIT_MASK_ACH12_DESC_MODE_8814B 0x3 +#define BIT_ACH12_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH12_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH12_DESC_MODE_8814B) +#define BITS_ACH12_DESC_MODE_8814B \ + (BIT_MASK_ACH12_DESC_MODE_8814B << BIT_SHIFT_ACH12_DESC_MODE_8814B) +#define BIT_CLEAR_ACH12_DESC_MODE_8814B(x) ((x) & (~BITS_ACH12_DESC_MODE_8814B)) +#define BIT_GET_ACH12_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_DESC_MODE_8814B) & \ + BIT_MASK_ACH12_DESC_MODE_8814B) +#define BIT_SET_ACH12_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH12_DESC_MODE_8814B(x) | BIT_ACH12_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH12_DESC_NUM_8814B 0 +#define BIT_MASK_ACH12_DESC_NUM_8814B 0xfff +#define BIT_ACH12_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH12_DESC_NUM_8814B) \ + << BIT_SHIFT_ACH12_DESC_NUM_8814B) +#define BITS_ACH12_DESC_NUM_8814B \ + (BIT_MASK_ACH12_DESC_NUM_8814B << BIT_SHIFT_ACH12_DESC_NUM_8814B) +#define BIT_CLEAR_ACH12_DESC_NUM_8814B(x) ((x) & (~BITS_ACH12_DESC_NUM_8814B)) +#define BIT_GET_ACH12_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_DESC_NUM_8814B) & \ + BIT_MASK_ACH12_DESC_NUM_8814B) +#define BIT_SET_ACH12_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH12_DESC_NUM_8814B(x) | BIT_ACH12_DESC_NUM_8814B(v)) + +/* 2 REG_OLD_DEHANG_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_OLD_DEHANG_8814B BIT(1) -/* 2 REG_MGQ_TXBD_NUM_8814B */ -#define BIT_PCIE_MGQ_FLAG_8814B BIT(14) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_MGQ_DESC_MODE_8814B 12 -#define BIT_MASK_MGQ_DESC_MODE_8814B 0x3 -#define BIT_MGQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8814B) << BIT_SHIFT_MGQ_DESC_MODE_8814B) -#define BIT_GET_MGQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8814B) & BIT_MASK_MGQ_DESC_MODE_8814B) +/* 2 REG_ACH4_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_ACH4_TXBD_DESA_L_8814B 0 +#define BIT_MASK_ACH4_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_ACH4_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_ACH4_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_ACH4_TXBD_DESA_L_8814B) +#define BITS_ACH4_TXBD_DESA_L_8814B \ + (BIT_MASK_ACH4_TXBD_DESA_L_8814B << BIT_SHIFT_ACH4_TXBD_DESA_L_8814B) +#define BIT_CLEAR_ACH4_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_ACH4_TXBD_DESA_L_8814B)) +#define BIT_GET_ACH4_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_L_8814B) & \ + BIT_MASK_ACH4_TXBD_DESA_L_8814B) +#define BIT_SET_ACH4_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_ACH4_TXBD_DESA_L_8814B(x) | BIT_ACH4_TXBD_DESA_L_8814B(v)) + +/* 2 REG_ACH4_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_ACH4_TXBD_DESA_H_8814B 0 +#define BIT_MASK_ACH4_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_ACH4_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_ACH4_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_ACH4_TXBD_DESA_H_8814B) +#define BITS_ACH4_TXBD_DESA_H_8814B \ + (BIT_MASK_ACH4_TXBD_DESA_H_8814B << BIT_SHIFT_ACH4_TXBD_DESA_H_8814B) +#define BIT_CLEAR_ACH4_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_ACH4_TXBD_DESA_H_8814B)) +#define BIT_GET_ACH4_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_H_8814B) & \ + BIT_MASK_ACH4_TXBD_DESA_H_8814B) +#define BIT_SET_ACH4_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_ACH4_TXBD_DESA_H_8814B(x) | BIT_ACH4_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI8Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI8Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI8Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI8Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B) +#define BITS_HI8Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI8Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI8Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI8Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI8Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI8Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI8Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI8Q_TXBD_DESA_L_8814B(x) | BIT_HI8Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI8Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI8Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI8Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI8Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B) +#define BITS_HI8Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI8Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI8Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI8Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI8Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI8Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI8Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI8Q_TXBD_DESA_H_8814B(x) | BIT_HI8Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI9Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI9Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI9Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI9Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B) +#define BITS_HI9Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI9Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI9Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI9Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI9Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI9Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI9Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI9Q_TXBD_DESA_L_8814B(x) | BIT_HI9Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI9Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI9Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI9Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI9Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B) +#define BITS_HI9Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI9Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI9Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI9Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI9Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI9Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI9Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI9Q_TXBD_DESA_H_8814B(x) | BIT_HI9Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI10Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI10Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI10Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI10Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B) +#define BITS_HI10Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI10Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI10Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI10Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI10Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI10Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI10Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI10Q_TXBD_DESA_L_8814B(x) | BIT_HI10Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI10Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI10Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI10Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI10Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B) +#define BITS_HI10Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI10Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI10Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI10Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI10Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI10Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI10Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI10Q_TXBD_DESA_H_8814B(x) | BIT_HI10Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI11Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI11Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI11Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI11Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B) +#define BITS_HI11Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI11Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI11Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI11Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI11Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI11Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI11Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI11Q_TXBD_DESA_L_8814B(x) | BIT_HI11Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI11Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI11Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI11Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI11Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B) +#define BITS_HI11Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI11Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI11Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI11Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI11Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI11Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI11Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI11Q_TXBD_DESA_H_8814B(x) | BIT_HI11Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI12Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI12Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI12Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI12Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B) +#define BITS_HI12Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI12Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI12Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI12Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI12Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI12Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI12Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI12Q_TXBD_DESA_L_8814B(x) | BIT_HI12Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI12Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI12Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI12Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI12Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B) +#define BITS_HI12Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI12Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI12Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI12Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI12Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI12Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI12Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI12Q_TXBD_DESA_H_8814B(x) | BIT_HI12Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI13Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI13Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI13Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI13Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B) +#define BITS_HI13Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI13Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI13Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI13Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI13Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI13Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI13Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI13Q_TXBD_DESA_L_8814B(x) | BIT_HI13Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI13Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI13Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI13Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI13Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B) +#define BITS_HI13Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI13Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI13Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI13Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI13Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI13Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI13Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI13Q_TXBD_DESA_H_8814B(x) | BIT_HI13Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI14Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI14Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI14Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI14Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B) +#define BITS_HI14Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI14Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI14Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI14Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI14Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI14Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI14Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI14Q_TXBD_DESA_L_8814B(x) | BIT_HI14Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI14Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI14Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI14Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI14Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B) +#define BITS_HI14Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI14Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI14Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI14Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI14Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI14Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI14Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI14Q_TXBD_DESA_H_8814B(x) | BIT_HI14Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI15Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI15Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI15Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI15Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B) +#define BITS_HI15Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI15Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI15Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI15Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI15Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI15Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI15Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI15Q_TXBD_DESA_L_8814B(x) | BIT_HI15Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI15Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI15Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI15Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI15Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B) +#define BITS_HI15Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI15Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI15Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI15Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI15Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI15Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI15Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI15Q_TXBD_DESA_H_8814B(x) | BIT_HI15Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI16Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI16Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI16Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI16Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B) +#define BITS_HI16Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI16Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI16Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI16Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI16Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI16Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI16Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI16Q_TXBD_DESA_L_8814B(x) | BIT_HI16Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI16Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI16Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI16Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI16Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B) +#define BITS_HI16Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI16Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI16Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI16Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI16Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI16Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI16Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI16Q_TXBD_DESA_H_8814B(x) | BIT_HI16Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI17Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI17Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI17Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI17Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B) +#define BITS_HI17Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI17Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI17Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI17Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI17Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI17Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI17Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI17Q_TXBD_DESA_L_8814B(x) | BIT_HI17Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI17Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI17Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI17Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI17Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B) +#define BITS_HI17Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI17Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI17Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI17Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI17Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI17Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI17Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI17Q_TXBD_DESA_H_8814B(x) | BIT_HI17Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI18Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI18Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI18Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI18Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B) +#define BITS_HI18Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI18Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI18Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI18Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI18Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI18Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI18Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI18Q_TXBD_DESA_L_8814B(x) | BIT_HI18Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI18Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI18Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI18Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI18Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B) +#define BITS_HI18Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI18Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI18Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI18Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI18Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI18Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI18Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI18Q_TXBD_DESA_H_8814B(x) | BIT_HI18Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_HI19Q_TXBD_DESA_L_8814B */ + +#define BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B 0 +#define BIT_MASK_HI19Q_TXBD_DESA_L_8814B 0xffffffffL +#define BIT_HI19Q_TXBD_DESA_L_8814B(x) \ + (((x) & BIT_MASK_HI19Q_TXBD_DESA_L_8814B) \ + << BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B) +#define BITS_HI19Q_TXBD_DESA_L_8814B \ + (BIT_MASK_HI19Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B) +#define BIT_CLEAR_HI19Q_TXBD_DESA_L_8814B(x) \ + ((x) & (~BITS_HI19Q_TXBD_DESA_L_8814B)) +#define BIT_GET_HI19Q_TXBD_DESA_L_8814B(x) \ + (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B) & \ + BIT_MASK_HI19Q_TXBD_DESA_L_8814B) +#define BIT_SET_HI19Q_TXBD_DESA_L_8814B(x, v) \ + (BIT_CLEAR_HI19Q_TXBD_DESA_L_8814B(x) | BIT_HI19Q_TXBD_DESA_L_8814B(v)) + +/* 2 REG_HI19Q_TXBD_DESA_H_8814B */ + +#define BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B 0 +#define BIT_MASK_HI19Q_TXBD_DESA_H_8814B 0xffffffffL +#define BIT_HI19Q_TXBD_DESA_H_8814B(x) \ + (((x) & BIT_MASK_HI19Q_TXBD_DESA_H_8814B) \ + << BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B) +#define BITS_HI19Q_TXBD_DESA_H_8814B \ + (BIT_MASK_HI19Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B) +#define BIT_CLEAR_HI19Q_TXBD_DESA_H_8814B(x) \ + ((x) & (~BITS_HI19Q_TXBD_DESA_H_8814B)) +#define BIT_GET_HI19Q_TXBD_DESA_H_8814B(x) \ + (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B) & \ + BIT_MASK_HI19Q_TXBD_DESA_H_8814B) +#define BIT_SET_HI19Q_TXBD_DESA_H_8814B(x, v) \ + (BIT_CLEAR_HI19Q_TXBD_DESA_H_8814B(x) | BIT_HI19Q_TXBD_DESA_H_8814B(v)) + +/* 2 REG_BD_RWPTR_CLR6_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_P0HI19Q_HW_IDX_8814B BIT(25) +#define BIT_CLR_P0HI18Q_HW_IDX_8814B BIT(24) +#define BIT_CLR_P0HI17Q_HW_IDX_8814B BIT(23) +#define BIT_CLR_P0HI16Q_HW_IDX_8814B BIT(22) +/* 2 REG_NOT_VALID_8814B */ +#define BIT_CLR_P0HI19Q_HOST_IDX_8814B BIT(9) +#define BIT_CLR_P0HI18Q_HOST_IDX_8814B BIT(8) +#define BIT_CLR_P0HI17Q_HOST_IDX_8814B BIT(7) +#define BIT_CLR_P0HI16Q_HOST_IDX_8814B BIT(6) -#define BIT_SHIFT_MGQ_DESC_NUM_8814B 0 -#define BIT_MASK_MGQ_DESC_NUM_8814B 0xfff -#define BIT_MGQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8814B) << BIT_SHIFT_MGQ_DESC_NUM_8814B) -#define BIT_GET_MGQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8814B) & BIT_MASK_MGQ_DESC_NUM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_P0HI16Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI16Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI16Q_HW_IDX_8814B 0xfff +#define BIT_P0HI16Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI16Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI16Q_HW_IDX_8814B) +#define BITS_P0HI16Q_HW_IDX_8814B \ + (BIT_MASK_P0HI16Q_HW_IDX_8814B << BIT_SHIFT_P0HI16Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI16Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI16Q_HW_IDX_8814B)) +#define BIT_GET_P0HI16Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI16Q_HW_IDX_8814B) +#define BIT_SET_P0HI16Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI16Q_HW_IDX_8814B(x) | BIT_P0HI16Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI16Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI16Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI16Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI16Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI16Q_HOST_IDX_8814B) +#define BITS_P0HI16Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI16Q_HOST_IDX_8814B << BIT_SHIFT_P0HI16Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI16Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI16Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI16Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI16Q_HOST_IDX_8814B) +#define BIT_SET_P0HI16Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI16Q_HOST_IDX_8814B(x) | BIT_P0HI16Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI17Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI17Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI17Q_HW_IDX_8814B 0xfff +#define BIT_P0HI17Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI17Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI17Q_HW_IDX_8814B) +#define BITS_P0HI17Q_HW_IDX_8814B \ + (BIT_MASK_P0HI17Q_HW_IDX_8814B << BIT_SHIFT_P0HI17Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI17Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI17Q_HW_IDX_8814B)) +#define BIT_GET_P0HI17Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI17Q_HW_IDX_8814B) +#define BIT_SET_P0HI17Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI17Q_HW_IDX_8814B(x) | BIT_P0HI17Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI17Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI17Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI17Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI17Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI17Q_HOST_IDX_8814B) +#define BITS_P0HI17Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI17Q_HOST_IDX_8814B << BIT_SHIFT_P0HI17Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI17Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI17Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI17Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI17Q_HOST_IDX_8814B) +#define BIT_SET_P0HI17Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI17Q_HOST_IDX_8814B(x) | BIT_P0HI17Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI18Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI18Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI18Q_HW_IDX_8814B 0xfff +#define BIT_P0HI18Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI18Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI18Q_HW_IDX_8814B) +#define BITS_P0HI18Q_HW_IDX_8814B \ + (BIT_MASK_P0HI18Q_HW_IDX_8814B << BIT_SHIFT_P0HI18Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI18Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI18Q_HW_IDX_8814B)) +#define BIT_GET_P0HI18Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI18Q_HW_IDX_8814B) +#define BIT_SET_P0HI18Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI18Q_HW_IDX_8814B(x) | BIT_P0HI18Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI18Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI18Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI18Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI18Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI18Q_HOST_IDX_8814B) +#define BITS_P0HI18Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI18Q_HOST_IDX_8814B << BIT_SHIFT_P0HI18Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI18Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI18Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI18Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI18Q_HOST_IDX_8814B) +#define BIT_SET_P0HI18Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI18Q_HOST_IDX_8814B(x) | BIT_P0HI18Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI19Q_TXBD_IDX_8814B */ + +#define BIT_SHIFT_P0HI19Q_HW_IDX_8814B 16 +#define BIT_MASK_P0HI19Q_HW_IDX_8814B 0xfff +#define BIT_P0HI19Q_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI19Q_HW_IDX_8814B) \ + << BIT_SHIFT_P0HI19Q_HW_IDX_8814B) +#define BITS_P0HI19Q_HW_IDX_8814B \ + (BIT_MASK_P0HI19Q_HW_IDX_8814B << BIT_SHIFT_P0HI19Q_HW_IDX_8814B) +#define BIT_CLEAR_P0HI19Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI19Q_HW_IDX_8814B)) +#define BIT_GET_P0HI19Q_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_HW_IDX_8814B) & \ + BIT_MASK_P0HI19Q_HW_IDX_8814B) +#define BIT_SET_P0HI19Q_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI19Q_HW_IDX_8814B(x) | BIT_P0HI19Q_HW_IDX_8814B(v)) + +#define BIT_SHIFT_P0HI19Q_HOST_IDX_8814B 0 +#define BIT_MASK_P0HI19Q_HOST_IDX_8814B 0xfff +#define BIT_P0HI19Q_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_P0HI19Q_HOST_IDX_8814B) \ + << BIT_SHIFT_P0HI19Q_HOST_IDX_8814B) +#define BITS_P0HI19Q_HOST_IDX_8814B \ + (BIT_MASK_P0HI19Q_HOST_IDX_8814B << BIT_SHIFT_P0HI19Q_HOST_IDX_8814B) +#define BIT_CLEAR_P0HI19Q_HOST_IDX_8814B(x) \ + ((x) & (~BITS_P0HI19Q_HOST_IDX_8814B)) +#define BIT_GET_P0HI19Q_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_HOST_IDX_8814B) & \ + BIT_MASK_P0HI19Q_HOST_IDX_8814B) +#define BIT_SET_P0HI19Q_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_P0HI19Q_HOST_IDX_8814B(x) | BIT_P0HI19Q_HOST_IDX_8814B(v)) + +/* 2 REG_P0HI16Q_HI17Q_TXBD_NUM_8814B */ +#define BIT_P0HI17Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI17Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI17Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI17Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI17Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI17Q_DESC_MODE_8814B) +#define BITS_P0HI17Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI17Q_DESC_MODE_8814B << BIT_SHIFT_P0HI17Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI17Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI17Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI17Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI17Q_DESC_MODE_8814B) +#define BIT_SET_P0HI17Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI17Q_DESC_MODE_8814B(x) | BIT_P0HI17Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI17Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI17Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI17Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI17Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI17Q_DESC_NUM_8814B) +#define BITS_P0HI17Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI17Q_DESC_NUM_8814B << BIT_SHIFT_P0HI17Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI17Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI17Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI17Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI17Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI17Q_DESC_NUM_8814B) +#define BIT_SET_P0HI17Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI17Q_DESC_NUM_8814B(x) | BIT_P0HI17Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI16Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI16Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI16Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI16Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI16Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI16Q_DESC_MODE_8814B) +#define BITS_P0HI16Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI16Q_DESC_MODE_8814B << BIT_SHIFT_P0HI16Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI16Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI16Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI16Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI16Q_DESC_MODE_8814B) +#define BIT_SET_P0HI16Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI16Q_DESC_MODE_8814B(x) | BIT_P0HI16Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI16Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI16Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI16Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI16Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI16Q_DESC_NUM_8814B) +#define BITS_P0HI16Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI16Q_DESC_NUM_8814B << BIT_SHIFT_P0HI16Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI16Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI16Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI16Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI16Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI16Q_DESC_NUM_8814B) +#define BIT_SET_P0HI16Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI16Q_DESC_NUM_8814B(x) | BIT_P0HI16Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI18Q_HI19Q_TXBD_NUM_8814B */ +#define BIT_P0HI19Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI19Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI19Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI19Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI19Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI19Q_DESC_MODE_8814B) +#define BITS_P0HI19Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI19Q_DESC_MODE_8814B << BIT_SHIFT_P0HI19Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI19Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI19Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI19Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI19Q_DESC_MODE_8814B) +#define BIT_SET_P0HI19Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI19Q_DESC_MODE_8814B(x) | BIT_P0HI19Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI19Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI19Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI19Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI19Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI19Q_DESC_NUM_8814B) +#define BITS_P0HI19Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI19Q_DESC_NUM_8814B << BIT_SHIFT_P0HI19Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI19Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI19Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI19Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI19Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI19Q_DESC_NUM_8814B) +#define BIT_SET_P0HI19Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI19Q_DESC_NUM_8814B(x) | BIT_P0HI19Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI18Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI18Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI18Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI18Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI18Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI18Q_DESC_MODE_8814B) +#define BITS_P0HI18Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI18Q_DESC_MODE_8814B << BIT_SHIFT_P0HI18Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI18Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI18Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI18Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI18Q_DESC_MODE_8814B) +#define BIT_SET_P0HI18Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI18Q_DESC_MODE_8814B(x) | BIT_P0HI18Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI18Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI18Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI18Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI18Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI18Q_DESC_NUM_8814B) +#define BITS_P0HI18Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI18Q_DESC_NUM_8814B << BIT_SHIFT_P0HI18Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI18Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI18Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI18Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI18Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI18Q_DESC_NUM_8814B) +#define BIT_SET_P0HI18Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI18Q_DESC_NUM_8814B(x) | BIT_P0HI18Q_DESC_NUM_8814B(v)) + +/* 2 REG_PCIE_HISR0_8814B */ +#define BIT_PSTIMER_2_8814B BIT(31) +#define BIT_PSTIMER_1_8814B BIT(30) +#define BIT_PSTIMER_0_8814B BIT(29) +#define BIT_GTINT4_8814B BIT(28) +#define BIT_GTINT3_8814B BIT(27) +#define BIT_TXBCN0ERR_8814B BIT(26) +#define BIT_TXBCN0OK_8814B BIT(25) +#define BIT_TSF_BIT32_TOGGLE_8814B BIT(24) +#define BIT_TXDMA_START_INT_8814B BIT(23) +#define BIT_TXDMA_STOP_INT_8814B BIT(22) +#define BIT_HISR7_IND_8814B BIT(21) +#define BIT_BCNDMAINT0_8814B BIT(20) +#define BIT_HISR6_IND_8814B BIT(19) +#define BIT_HISR5_IND_8814B BIT(18) +#define BIT_HISR4_IND_8814B BIT(17) +#define BIT_BCNDERR0_8814B BIT(16) +#define BIT_HSISR_IND_ON_INT_8814B BIT(15) +#define BIT_HISR3_IND_8814B BIT(14) +#define BIT_HISR2_IND_8814B BIT(13) +#define BIT_HISR1_IND_8814B BIT(11) +#define BIT_C2HCMD_8814B BIT(10) +#define BIT_CPWM2_8814B BIT(9) +#define BIT_CPWM_8814B BIT(8) +#define BIT_TXDMAOK_CHANNEL15_8814B BIT(7) +#define BIT_TXDMAOK_CHANNEL14_8814B BIT(6) +#define BIT_TXDMAOK_CHANNEL3_8814B BIT(5) +#define BIT_TXDMAOK_CHANNEL2_8814B BIT(4) +#define BIT_TXDMAOK_CHANNEL1_8814B BIT(3) +#define BIT_TXDMAOK_CHANNEL0_8814B BIT(2) +#define BIT_RDU_8814B BIT(1) +#define BIT_RXOK_8814B BIT(0) +/* 2 REG_PCIE_HISR1_8814B */ +#define BIT_PRE_TX_ERR_INT_8814B BIT(31) +#define BIT_TXFIFO_TH_INT_8814B BIT(30) +#define BIT_BTON_STS_UPDATE_INT_8814B BIT(29) +#define BIT_BCNDMAINT7_8814B BIT(27) +#define BIT_BCNDMAINT6_8814B BIT(26) +#define BIT_BCNDMAINT5_8814B BIT(25) +#define BIT_BCNDMAINT4_8814B BIT(24) +#define BIT_BCNDMAINT3_8814B BIT(23) +#define BIT_BCNDMAINT2_8814B BIT(22) +#define BIT_BCNDMAINT1_8814B BIT(21) +#define BIT_BCNDERR7_8814B BIT(20) +#define BIT_BCNDERR6_8814B BIT(19) +#define BIT_BCNDERR5_8814B BIT(18) +#define BIT_BCNDERR4_8814B BIT(17) +#define BIT_BCNDERR3_8814B BIT(16) +#define BIT_BCNDERR2_8814B BIT(15) +#define BIT_BCNDERR1_8814B BIT(14) +#define BIT_ATIMEND_8814B BIT(12) +#define BIT_TXERR_INT_8814B BIT(11) +#define BIT_RXERR_INT_8814B BIT(10) +#define BIT_TXFOVW_8814B BIT(9) +#define BIT_FOVW_8814B BIT(8) +#define BIT_CPU_MGQ_EARLY_INT_8814B BIT(6) +#define BIT_CPU_MGQ_TXDONE_8814B BIT(5) +#define BIT_PSTIMER_5_8814B BIT(4) +#define BIT_PSTIMER_4_8814B BIT(3) +#define BIT_PSTIMER_3_8814B BIT(2) +#define BIT_CPUMGQ_TX_TIMER_8814B BIT(1) +#define BIT_BB_STOPRX_INT_8814B BIT(0) + +/* 2 REG_P0HI8Q_HI9Q_TXBD_NUM_8814B */ +#define BIT_P0HI9Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI9Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI9Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI9Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI9Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI9Q_DESC_MODE_8814B) +#define BITS_P0HI9Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI9Q_DESC_MODE_8814B << BIT_SHIFT_P0HI9Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI9Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI9Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI9Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI9Q_DESC_MODE_8814B) +#define BIT_SET_P0HI9Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI9Q_DESC_MODE_8814B(x) | BIT_P0HI9Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI9Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI9Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI9Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI9Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI9Q_DESC_NUM_8814B) +#define BITS_P0HI9Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI9Q_DESC_NUM_8814B << BIT_SHIFT_P0HI9Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI9Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI9Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI9Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI9Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI9Q_DESC_NUM_8814B) +#define BIT_SET_P0HI9Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI9Q_DESC_NUM_8814B(x) | BIT_P0HI9Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI8Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI8Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI8Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI8Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI8Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI8Q_DESC_MODE_8814B) +#define BITS_P0HI8Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI8Q_DESC_MODE_8814B << BIT_SHIFT_P0HI8Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI8Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI8Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI8Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI8Q_DESC_MODE_8814B) +#define BIT_SET_P0HI8Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI8Q_DESC_MODE_8814B(x) | BIT_P0HI8Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI8Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI8Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI8Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI8Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI8Q_DESC_NUM_8814B) +#define BITS_P0HI8Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI8Q_DESC_NUM_8814B << BIT_SHIFT_P0HI8Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI8Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI8Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI8Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI8Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI8Q_DESC_NUM_8814B) +#define BIT_SET_P0HI8Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI8Q_DESC_NUM_8814B(x) | BIT_P0HI8Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI10Q_HI11Q_TXBD_NUM_8814B */ +#define BIT_P0HI11Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI11Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI11Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI11Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI11Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI11Q_DESC_MODE_8814B) +#define BITS_P0HI11Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI11Q_DESC_MODE_8814B << BIT_SHIFT_P0HI11Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI11Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI11Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI11Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI11Q_DESC_MODE_8814B) +#define BIT_SET_P0HI11Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI11Q_DESC_MODE_8814B(x) | BIT_P0HI11Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI11Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI11Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI11Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI11Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI11Q_DESC_NUM_8814B) +#define BITS_P0HI11Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI11Q_DESC_NUM_8814B << BIT_SHIFT_P0HI11Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI11Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI11Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI11Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI11Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI11Q_DESC_NUM_8814B) +#define BIT_SET_P0HI11Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI11Q_DESC_NUM_8814B(x) | BIT_P0HI11Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI10Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI10Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI10Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI10Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI10Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI10Q_DESC_MODE_8814B) +#define BITS_P0HI10Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI10Q_DESC_MODE_8814B << BIT_SHIFT_P0HI10Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI10Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI10Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI10Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI10Q_DESC_MODE_8814B) +#define BIT_SET_P0HI10Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI10Q_DESC_MODE_8814B(x) | BIT_P0HI10Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI10Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI10Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI10Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI10Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI10Q_DESC_NUM_8814B) +#define BITS_P0HI10Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI10Q_DESC_NUM_8814B << BIT_SHIFT_P0HI10Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI10Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI10Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI10Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI10Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI10Q_DESC_NUM_8814B) +#define BIT_SET_P0HI10Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI10Q_DESC_NUM_8814B(x) | BIT_P0HI10Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI12Q_HI13Q_TXBD_NUM_8814B */ +#define BIT_P0HI13Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI13Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI13Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI13Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI13Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI13Q_DESC_MODE_8814B) +#define BITS_P0HI13Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI13Q_DESC_MODE_8814B << BIT_SHIFT_P0HI13Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI13Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI13Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI13Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI13Q_DESC_MODE_8814B) +#define BIT_SET_P0HI13Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI13Q_DESC_MODE_8814B(x) | BIT_P0HI13Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI13Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI13Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI13Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI13Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI13Q_DESC_NUM_8814B) +#define BITS_P0HI13Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI13Q_DESC_NUM_8814B << BIT_SHIFT_P0HI13Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI13Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI13Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI13Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI13Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI13Q_DESC_NUM_8814B) +#define BIT_SET_P0HI13Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI13Q_DESC_NUM_8814B(x) | BIT_P0HI13Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI12Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI12Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI12Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI12Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI12Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI12Q_DESC_MODE_8814B) +#define BITS_P0HI12Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI12Q_DESC_MODE_8814B << BIT_SHIFT_P0HI12Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI12Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI12Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI12Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI12Q_DESC_MODE_8814B) +#define BIT_SET_P0HI12Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI12Q_DESC_MODE_8814B(x) | BIT_P0HI12Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI12Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI12Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI12Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI12Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI12Q_DESC_NUM_8814B) +#define BITS_P0HI12Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI12Q_DESC_NUM_8814B << BIT_SHIFT_P0HI12Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI12Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI12Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI12Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI12Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI12Q_DESC_NUM_8814B) +#define BIT_SET_P0HI12Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI12Q_DESC_NUM_8814B(x) | BIT_P0HI12Q_DESC_NUM_8814B(v)) + +/* 2 REG_P0HI14Q_HI15Q_TXBD_NUM_8814B */ +#define BIT_P0HI15Q_FLAG_8814B BIT(30) + +#define BIT_SHIFT_P0HI15Q_DESC_MODE_8814B 28 +#define BIT_MASK_P0HI15Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI15Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI15Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI15Q_DESC_MODE_8814B) +#define BITS_P0HI15Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI15Q_DESC_MODE_8814B << BIT_SHIFT_P0HI15Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI15Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI15Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI15Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI15Q_DESC_MODE_8814B) +#define BIT_SET_P0HI15Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI15Q_DESC_MODE_8814B(x) | BIT_P0HI15Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI15Q_DESC_NUM_8814B 16 +#define BIT_MASK_P0HI15Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI15Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI15Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI15Q_DESC_NUM_8814B) +#define BITS_P0HI15Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI15Q_DESC_NUM_8814B << BIT_SHIFT_P0HI15Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI15Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI15Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI15Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI15Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI15Q_DESC_NUM_8814B) +#define BIT_SET_P0HI15Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI15Q_DESC_NUM_8814B(x) | BIT_P0HI15Q_DESC_NUM_8814B(v)) + +#define BIT_P0HI14Q_FLAG_8814B BIT(14) + +#define BIT_SHIFT_P0HI14Q_DESC_MODE_8814B 12 +#define BIT_MASK_P0HI14Q_DESC_MODE_8814B 0x3 +#define BIT_P0HI14Q_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_P0HI14Q_DESC_MODE_8814B) \ + << BIT_SHIFT_P0HI14Q_DESC_MODE_8814B) +#define BITS_P0HI14Q_DESC_MODE_8814B \ + (BIT_MASK_P0HI14Q_DESC_MODE_8814B << BIT_SHIFT_P0HI14Q_DESC_MODE_8814B) +#define BIT_CLEAR_P0HI14Q_DESC_MODE_8814B(x) \ + ((x) & (~BITS_P0HI14Q_DESC_MODE_8814B)) +#define BIT_GET_P0HI14Q_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_DESC_MODE_8814B) & \ + BIT_MASK_P0HI14Q_DESC_MODE_8814B) +#define BIT_SET_P0HI14Q_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_P0HI14Q_DESC_MODE_8814B(x) | BIT_P0HI14Q_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_P0HI14Q_DESC_NUM_8814B 0 +#define BIT_MASK_P0HI14Q_DESC_NUM_8814B 0xfff +#define BIT_P0HI14Q_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_P0HI14Q_DESC_NUM_8814B) \ + << BIT_SHIFT_P0HI14Q_DESC_NUM_8814B) +#define BITS_P0HI14Q_DESC_NUM_8814B \ + (BIT_MASK_P0HI14Q_DESC_NUM_8814B << BIT_SHIFT_P0HI14Q_DESC_NUM_8814B) +#define BIT_CLEAR_P0HI14Q_DESC_NUM_8814B(x) \ + ((x) & (~BITS_P0HI14Q_DESC_NUM_8814B)) +#define BIT_GET_P0HI14Q_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_P0HI14Q_DESC_NUM_8814B) & \ + BIT_MASK_P0HI14Q_DESC_NUM_8814B) +#define BIT_SET_P0HI14Q_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_P0HI14Q_DESC_NUM_8814B(x) | BIT_P0HI14Q_DESC_NUM_8814B(v)) + +/* 2 REG_ACH6_ACH7_TXBD_NUM_8814B */ +#define BIT_PCIE_ACH7_FLAG_8814B BIT(30) + +#define BIT_SHIFT_ACH7_DESC_MODE_8814B 28 +#define BIT_MASK_ACH7_DESC_MODE_8814B 0x3 +#define BIT_ACH7_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH7_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH7_DESC_MODE_8814B) +#define BITS_ACH7_DESC_MODE_8814B \ + (BIT_MASK_ACH7_DESC_MODE_8814B << BIT_SHIFT_ACH7_DESC_MODE_8814B) +#define BIT_CLEAR_ACH7_DESC_MODE_8814B(x) ((x) & (~BITS_ACH7_DESC_MODE_8814B)) +#define BIT_GET_ACH7_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_DESC_MODE_8814B) & \ + BIT_MASK_ACH7_DESC_MODE_8814B) +#define BIT_SET_ACH7_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH7_DESC_MODE_8814B(x) | BIT_ACH7_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH7_DESC_NUM_8814B 16 +#define BIT_MASK_ACH7_DESC_NUM_8814B 0xfff +#define BIT_ACH7_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH7_DESC_NUM_8814B) << BIT_SHIFT_ACH7_DESC_NUM_8814B) +#define BITS_ACH7_DESC_NUM_8814B \ + (BIT_MASK_ACH7_DESC_NUM_8814B << BIT_SHIFT_ACH7_DESC_NUM_8814B) +#define BIT_CLEAR_ACH7_DESC_NUM_8814B(x) ((x) & (~BITS_ACH7_DESC_NUM_8814B)) +#define BIT_GET_ACH7_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_DESC_NUM_8814B) & BIT_MASK_ACH7_DESC_NUM_8814B) +#define BIT_SET_ACH7_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH7_DESC_NUM_8814B(x) | BIT_ACH7_DESC_NUM_8814B(v)) + +#define BIT_PCIE_ACH6_FLAG_8814B BIT(14) + +#define BIT_SHIFT_ACH6_DESC_MODE_8814B 12 +#define BIT_MASK_ACH6_DESC_MODE_8814B 0x3 +#define BIT_ACH6_DESC_MODE_8814B(x) \ + (((x) & BIT_MASK_ACH6_DESC_MODE_8814B) \ + << BIT_SHIFT_ACH6_DESC_MODE_8814B) +#define BITS_ACH6_DESC_MODE_8814B \ + (BIT_MASK_ACH6_DESC_MODE_8814B << BIT_SHIFT_ACH6_DESC_MODE_8814B) +#define BIT_CLEAR_ACH6_DESC_MODE_8814B(x) ((x) & (~BITS_ACH6_DESC_MODE_8814B)) +#define BIT_GET_ACH6_DESC_MODE_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_DESC_MODE_8814B) & \ + BIT_MASK_ACH6_DESC_MODE_8814B) +#define BIT_SET_ACH6_DESC_MODE_8814B(x, v) \ + (BIT_CLEAR_ACH6_DESC_MODE_8814B(x) | BIT_ACH6_DESC_MODE_8814B(v)) + +#define BIT_SHIFT_ACH6_DESC_NUM_8814B 0 +#define BIT_MASK_ACH6_DESC_NUM_8814B 0xfff +#define BIT_ACH6_DESC_NUM_8814B(x) \ + (((x) & BIT_MASK_ACH6_DESC_NUM_8814B) << BIT_SHIFT_ACH6_DESC_NUM_8814B) +#define BITS_ACH6_DESC_NUM_8814B \ + (BIT_MASK_ACH6_DESC_NUM_8814B << BIT_SHIFT_ACH6_DESC_NUM_8814B) +#define BIT_CLEAR_ACH6_DESC_NUM_8814B(x) ((x) & (~BITS_ACH6_DESC_NUM_8814B)) +#define BIT_GET_ACH6_DESC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_DESC_NUM_8814B) & BIT_MASK_ACH6_DESC_NUM_8814B) +#define BIT_SET_ACH6_DESC_NUM_8814B(x, v) \ + (BIT_CLEAR_ACH6_DESC_NUM_8814B(x) | BIT_ACH6_DESC_NUM_8814B(v)) + +/* 2 REG_ACH4_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH4_HW_IDX_8814B 16 +#define BIT_MASK_ACH4_HW_IDX_8814B 0xfff +#define BIT_ACH4_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH4_HW_IDX_8814B) << BIT_SHIFT_ACH4_HW_IDX_8814B) +#define BITS_ACH4_HW_IDX_8814B \ + (BIT_MASK_ACH4_HW_IDX_8814B << BIT_SHIFT_ACH4_HW_IDX_8814B) +#define BIT_CLEAR_ACH4_HW_IDX_8814B(x) ((x) & (~BITS_ACH4_HW_IDX_8814B)) +#define BIT_GET_ACH4_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_HW_IDX_8814B) & BIT_MASK_ACH4_HW_IDX_8814B) +#define BIT_SET_ACH4_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH4_HW_IDX_8814B(x) | BIT_ACH4_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH4_HOST_IDX_8814B 0 +#define BIT_MASK_ACH4_HOST_IDX_8814B 0xfff +#define BIT_ACH4_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH4_HOST_IDX_8814B) << BIT_SHIFT_ACH4_HOST_IDX_8814B) +#define BITS_ACH4_HOST_IDX_8814B \ + (BIT_MASK_ACH4_HOST_IDX_8814B << BIT_SHIFT_ACH4_HOST_IDX_8814B) +#define BIT_CLEAR_ACH4_HOST_IDX_8814B(x) ((x) & (~BITS_ACH4_HOST_IDX_8814B)) +#define BIT_GET_ACH4_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH4_HOST_IDX_8814B) & BIT_MASK_ACH4_HOST_IDX_8814B) +#define BIT_SET_ACH4_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH4_HOST_IDX_8814B(x) | BIT_ACH4_HOST_IDX_8814B(v)) + +/* 2 REG_ACH5_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH5_HW_IDX_8814B 16 +#define BIT_MASK_ACH5_HW_IDX_8814B 0xfff +#define BIT_ACH5_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH5_HW_IDX_8814B) << BIT_SHIFT_ACH5_HW_IDX_8814B) +#define BITS_ACH5_HW_IDX_8814B \ + (BIT_MASK_ACH5_HW_IDX_8814B << BIT_SHIFT_ACH5_HW_IDX_8814B) +#define BIT_CLEAR_ACH5_HW_IDX_8814B(x) ((x) & (~BITS_ACH5_HW_IDX_8814B)) +#define BIT_GET_ACH5_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_HW_IDX_8814B) & BIT_MASK_ACH5_HW_IDX_8814B) +#define BIT_SET_ACH5_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH5_HW_IDX_8814B(x) | BIT_ACH5_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH5_HOST_IDX_8814B 0 +#define BIT_MASK_ACH5_HOST_IDX_8814B 0xfff +#define BIT_ACH5_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH5_HOST_IDX_8814B) << BIT_SHIFT_ACH5_HOST_IDX_8814B) +#define BITS_ACH5_HOST_IDX_8814B \ + (BIT_MASK_ACH5_HOST_IDX_8814B << BIT_SHIFT_ACH5_HOST_IDX_8814B) +#define BIT_CLEAR_ACH5_HOST_IDX_8814B(x) ((x) & (~BITS_ACH5_HOST_IDX_8814B)) +#define BIT_GET_ACH5_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH5_HOST_IDX_8814B) & BIT_MASK_ACH5_HOST_IDX_8814B) +#define BIT_SET_ACH5_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH5_HOST_IDX_8814B(x) | BIT_ACH5_HOST_IDX_8814B(v)) + +/* 2 REG_ACH6_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH6_HW_IDX_8814B 16 +#define BIT_MASK_ACH6_HW_IDX_8814B 0xfff +#define BIT_ACH6_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH6_HW_IDX_8814B) << BIT_SHIFT_ACH6_HW_IDX_8814B) +#define BITS_ACH6_HW_IDX_8814B \ + (BIT_MASK_ACH6_HW_IDX_8814B << BIT_SHIFT_ACH6_HW_IDX_8814B) +#define BIT_CLEAR_ACH6_HW_IDX_8814B(x) ((x) & (~BITS_ACH6_HW_IDX_8814B)) +#define BIT_GET_ACH6_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_HW_IDX_8814B) & BIT_MASK_ACH6_HW_IDX_8814B) +#define BIT_SET_ACH6_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH6_HW_IDX_8814B(x) | BIT_ACH6_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH6_HOST_IDX_8814B 0 +#define BIT_MASK_ACH6_HOST_IDX_8814B 0xfff +#define BIT_ACH6_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH6_HOST_IDX_8814B) << BIT_SHIFT_ACH6_HOST_IDX_8814B) +#define BITS_ACH6_HOST_IDX_8814B \ + (BIT_MASK_ACH6_HOST_IDX_8814B << BIT_SHIFT_ACH6_HOST_IDX_8814B) +#define BIT_CLEAR_ACH6_HOST_IDX_8814B(x) ((x) & (~BITS_ACH6_HOST_IDX_8814B)) +#define BIT_GET_ACH6_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH6_HOST_IDX_8814B) & BIT_MASK_ACH6_HOST_IDX_8814B) +#define BIT_SET_ACH6_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH6_HOST_IDX_8814B(x) | BIT_ACH6_HOST_IDX_8814B(v)) + +/* 2 REG_ACH7_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH7_HW_IDX_8814B 16 +#define BIT_MASK_ACH7_HW_IDX_8814B 0xfff +#define BIT_ACH7_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH7_HW_IDX_8814B) << BIT_SHIFT_ACH7_HW_IDX_8814B) +#define BITS_ACH7_HW_IDX_8814B \ + (BIT_MASK_ACH7_HW_IDX_8814B << BIT_SHIFT_ACH7_HW_IDX_8814B) +#define BIT_CLEAR_ACH7_HW_IDX_8814B(x) ((x) & (~BITS_ACH7_HW_IDX_8814B)) +#define BIT_GET_ACH7_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_HW_IDX_8814B) & BIT_MASK_ACH7_HW_IDX_8814B) +#define BIT_SET_ACH7_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH7_HW_IDX_8814B(x) | BIT_ACH7_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH7_HOST_IDX_8814B 0 +#define BIT_MASK_ACH7_HOST_IDX_8814B 0xfff +#define BIT_ACH7_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH7_HOST_IDX_8814B) << BIT_SHIFT_ACH7_HOST_IDX_8814B) +#define BITS_ACH7_HOST_IDX_8814B \ + (BIT_MASK_ACH7_HOST_IDX_8814B << BIT_SHIFT_ACH7_HOST_IDX_8814B) +#define BIT_CLEAR_ACH7_HOST_IDX_8814B(x) ((x) & (~BITS_ACH7_HOST_IDX_8814B)) +#define BIT_GET_ACH7_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH7_HOST_IDX_8814B) & BIT_MASK_ACH7_HOST_IDX_8814B) +#define BIT_SET_ACH7_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH7_HOST_IDX_8814B(x) | BIT_ACH7_HOST_IDX_8814B(v)) + +/* 2 REG_ACH8_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH8_HW_IDX_8814B 16 +#define BIT_MASK_ACH8_HW_IDX_8814B 0xfff +#define BIT_ACH8_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH8_HW_IDX_8814B) << BIT_SHIFT_ACH8_HW_IDX_8814B) +#define BITS_ACH8_HW_IDX_8814B \ + (BIT_MASK_ACH8_HW_IDX_8814B << BIT_SHIFT_ACH8_HW_IDX_8814B) +#define BIT_CLEAR_ACH8_HW_IDX_8814B(x) ((x) & (~BITS_ACH8_HW_IDX_8814B)) +#define BIT_GET_ACH8_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_HW_IDX_8814B) & BIT_MASK_ACH8_HW_IDX_8814B) +#define BIT_SET_ACH8_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH8_HW_IDX_8814B(x) | BIT_ACH8_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH8_HOST_IDX_8814B 0 +#define BIT_MASK_ACH8_HOST_IDX_8814B 0xfff +#define BIT_ACH8_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH8_HOST_IDX_8814B) << BIT_SHIFT_ACH8_HOST_IDX_8814B) +#define BITS_ACH8_HOST_IDX_8814B \ + (BIT_MASK_ACH8_HOST_IDX_8814B << BIT_SHIFT_ACH8_HOST_IDX_8814B) +#define BIT_CLEAR_ACH8_HOST_IDX_8814B(x) ((x) & (~BITS_ACH8_HOST_IDX_8814B)) +#define BIT_GET_ACH8_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH8_HOST_IDX_8814B) & BIT_MASK_ACH8_HOST_IDX_8814B) +#define BIT_SET_ACH8_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH8_HOST_IDX_8814B(x) | BIT_ACH8_HOST_IDX_8814B(v)) + +/* 2 REG_ACH9_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH9_HW_IDX_8814B 16 +#define BIT_MASK_ACH9_HW_IDX_8814B 0xfff +#define BIT_ACH9_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH9_HW_IDX_8814B) << BIT_SHIFT_ACH9_HW_IDX_8814B) +#define BITS_ACH9_HW_IDX_8814B \ + (BIT_MASK_ACH9_HW_IDX_8814B << BIT_SHIFT_ACH9_HW_IDX_8814B) +#define BIT_CLEAR_ACH9_HW_IDX_8814B(x) ((x) & (~BITS_ACH9_HW_IDX_8814B)) +#define BIT_GET_ACH9_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_HW_IDX_8814B) & BIT_MASK_ACH9_HW_IDX_8814B) +#define BIT_SET_ACH9_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH9_HW_IDX_8814B(x) | BIT_ACH9_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH9_HOST_IDX_8814B 0 +#define BIT_MASK_ACH9_HOST_IDX_8814B 0xfff +#define BIT_ACH9_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH9_HOST_IDX_8814B) << BIT_SHIFT_ACH9_HOST_IDX_8814B) +#define BITS_ACH9_HOST_IDX_8814B \ + (BIT_MASK_ACH9_HOST_IDX_8814B << BIT_SHIFT_ACH9_HOST_IDX_8814B) +#define BIT_CLEAR_ACH9_HOST_IDX_8814B(x) ((x) & (~BITS_ACH9_HOST_IDX_8814B)) +#define BIT_GET_ACH9_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH9_HOST_IDX_8814B) & BIT_MASK_ACH9_HOST_IDX_8814B) +#define BIT_SET_ACH9_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH9_HOST_IDX_8814B(x) | BIT_ACH9_HOST_IDX_8814B(v)) + +/* 2 REG_ACH10_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH10_HW_IDX_8814B 16 +#define BIT_MASK_ACH10_HW_IDX_8814B 0xfff +#define BIT_ACH10_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH10_HW_IDX_8814B) << BIT_SHIFT_ACH10_HW_IDX_8814B) +#define BITS_ACH10_HW_IDX_8814B \ + (BIT_MASK_ACH10_HW_IDX_8814B << BIT_SHIFT_ACH10_HW_IDX_8814B) +#define BIT_CLEAR_ACH10_HW_IDX_8814B(x) ((x) & (~BITS_ACH10_HW_IDX_8814B)) +#define BIT_GET_ACH10_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_HW_IDX_8814B) & BIT_MASK_ACH10_HW_IDX_8814B) +#define BIT_SET_ACH10_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH10_HW_IDX_8814B(x) | BIT_ACH10_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH10_HOST_IDX_8814B 0 +#define BIT_MASK_ACH10_HOST_IDX_8814B 0xfff +#define BIT_ACH10_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH10_HOST_IDX_8814B) \ + << BIT_SHIFT_ACH10_HOST_IDX_8814B) +#define BITS_ACH10_HOST_IDX_8814B \ + (BIT_MASK_ACH10_HOST_IDX_8814B << BIT_SHIFT_ACH10_HOST_IDX_8814B) +#define BIT_CLEAR_ACH10_HOST_IDX_8814B(x) ((x) & (~BITS_ACH10_HOST_IDX_8814B)) +#define BIT_GET_ACH10_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH10_HOST_IDX_8814B) & \ + BIT_MASK_ACH10_HOST_IDX_8814B) +#define BIT_SET_ACH10_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH10_HOST_IDX_8814B(x) | BIT_ACH10_HOST_IDX_8814B(v)) + +/* 2 REG_ACH11_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH11_HW_IDX_8814B 16 +#define BIT_MASK_ACH11_HW_IDX_8814B 0xfff +#define BIT_ACH11_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH11_HW_IDX_8814B) << BIT_SHIFT_ACH11_HW_IDX_8814B) +#define BITS_ACH11_HW_IDX_8814B \ + (BIT_MASK_ACH11_HW_IDX_8814B << BIT_SHIFT_ACH11_HW_IDX_8814B) +#define BIT_CLEAR_ACH11_HW_IDX_8814B(x) ((x) & (~BITS_ACH11_HW_IDX_8814B)) +#define BIT_GET_ACH11_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_HW_IDX_8814B) & BIT_MASK_ACH11_HW_IDX_8814B) +#define BIT_SET_ACH11_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH11_HW_IDX_8814B(x) | BIT_ACH11_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH11_HOST_IDX_8814B 0 +#define BIT_MASK_ACH11_HOST_IDX_8814B 0xfff +#define BIT_ACH11_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH11_HOST_IDX_8814B) \ + << BIT_SHIFT_ACH11_HOST_IDX_8814B) +#define BITS_ACH11_HOST_IDX_8814B \ + (BIT_MASK_ACH11_HOST_IDX_8814B << BIT_SHIFT_ACH11_HOST_IDX_8814B) +#define BIT_CLEAR_ACH11_HOST_IDX_8814B(x) ((x) & (~BITS_ACH11_HOST_IDX_8814B)) +#define BIT_GET_ACH11_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH11_HOST_IDX_8814B) & \ + BIT_MASK_ACH11_HOST_IDX_8814B) +#define BIT_SET_ACH11_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH11_HOST_IDX_8814B(x) | BIT_ACH11_HOST_IDX_8814B(v)) + +/* 2 REG_ACH12_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH12_HW_IDX_8814B 16 +#define BIT_MASK_ACH12_HW_IDX_8814B 0xfff +#define BIT_ACH12_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH12_HW_IDX_8814B) << BIT_SHIFT_ACH12_HW_IDX_8814B) +#define BITS_ACH12_HW_IDX_8814B \ + (BIT_MASK_ACH12_HW_IDX_8814B << BIT_SHIFT_ACH12_HW_IDX_8814B) +#define BIT_CLEAR_ACH12_HW_IDX_8814B(x) ((x) & (~BITS_ACH12_HW_IDX_8814B)) +#define BIT_GET_ACH12_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_HW_IDX_8814B) & BIT_MASK_ACH12_HW_IDX_8814B) +#define BIT_SET_ACH12_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH12_HW_IDX_8814B(x) | BIT_ACH12_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH12_HOST_IDX_8814B 0 +#define BIT_MASK_ACH12_HOST_IDX_8814B 0xfff +#define BIT_ACH12_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH12_HOST_IDX_8814B) \ + << BIT_SHIFT_ACH12_HOST_IDX_8814B) +#define BITS_ACH12_HOST_IDX_8814B \ + (BIT_MASK_ACH12_HOST_IDX_8814B << BIT_SHIFT_ACH12_HOST_IDX_8814B) +#define BIT_CLEAR_ACH12_HOST_IDX_8814B(x) ((x) & (~BITS_ACH12_HOST_IDX_8814B)) +#define BIT_GET_ACH12_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH12_HOST_IDX_8814B) & \ + BIT_MASK_ACH12_HOST_IDX_8814B) +#define BIT_SET_ACH12_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH12_HOST_IDX_8814B(x) | BIT_ACH12_HOST_IDX_8814B(v)) + +/* 2 REG_ACH13_TXBD_IDX_8814B */ + +#define BIT_SHIFT_ACH13_HW_IDX_8814B 16 +#define BIT_MASK_ACH13_HW_IDX_8814B 0xfff +#define BIT_ACH13_HW_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH13_HW_IDX_8814B) << BIT_SHIFT_ACH13_HW_IDX_8814B) +#define BITS_ACH13_HW_IDX_8814B \ + (BIT_MASK_ACH13_HW_IDX_8814B << BIT_SHIFT_ACH13_HW_IDX_8814B) +#define BIT_CLEAR_ACH13_HW_IDX_8814B(x) ((x) & (~BITS_ACH13_HW_IDX_8814B)) +#define BIT_GET_ACH13_HW_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_HW_IDX_8814B) & BIT_MASK_ACH13_HW_IDX_8814B) +#define BIT_SET_ACH13_HW_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH13_HW_IDX_8814B(x) | BIT_ACH13_HW_IDX_8814B(v)) + +#define BIT_SHIFT_ACH13_HOST_IDX_8814B 0 +#define BIT_MASK_ACH13_HOST_IDX_8814B 0xfff +#define BIT_ACH13_HOST_IDX_8814B(x) \ + (((x) & BIT_MASK_ACH13_HOST_IDX_8814B) \ + << BIT_SHIFT_ACH13_HOST_IDX_8814B) +#define BITS_ACH13_HOST_IDX_8814B \ + (BIT_MASK_ACH13_HOST_IDX_8814B << BIT_SHIFT_ACH13_HOST_IDX_8814B) +#define BIT_CLEAR_ACH13_HOST_IDX_8814B(x) ((x) & (~BITS_ACH13_HOST_IDX_8814B)) +#define BIT_GET_ACH13_HOST_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_ACH13_HOST_IDX_8814B) & \ + BIT_MASK_ACH13_HOST_IDX_8814B) +#define BIT_SET_ACH13_HOST_IDX_8814B(x, v) \ + (BIT_CLEAR_ACH13_HOST_IDX_8814B(x) | BIT_ACH13_HOST_IDX_8814B(v)) + +/* 2 REG_AC_CHANNEL0_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL0_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL0_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL0_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B) +#define BITS_AC_CHANNEL0_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL0_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL0_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL0_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL0_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL0_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL0_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL0_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL0_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL1_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL1_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL1_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL1_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B) +#define BITS_AC_CHANNEL1_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL1_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL1_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL1_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL1_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL1_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL1_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL1_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL1_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL2_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL2_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL2_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL2_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B) +#define BITS_AC_CHANNEL2_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL2_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL2_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL2_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL2_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL2_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL2_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL2_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL2_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL3_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL3_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL3_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL3_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B) +#define BITS_AC_CHANNEL3_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL3_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL3_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL3_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL3_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL3_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL3_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL3_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL3_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL4_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL4_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL4_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL4_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B) +#define BITS_AC_CHANNEL4_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL4_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL4_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL4_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL4_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL4_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL4_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL4_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL4_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL5_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL5_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL5_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL5_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B) +#define BITS_AC_CHANNEL5_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL5_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL5_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL5_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL5_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL5_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL5_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL5_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL5_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL6_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL6_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL6_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL6_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B) +#define BITS_AC_CHANNEL6_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL6_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL6_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL6_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL6_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL6_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL6_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL6_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL6_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL7_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL7_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL7_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL7_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B) +#define BITS_AC_CHANNEL7_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL7_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL7_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL7_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL7_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL7_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL7_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL7_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL7_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL8_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL8_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL8_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL8_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B) +#define BITS_AC_CHANNEL8_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL8_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL8_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL8_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL8_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL8_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL8_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL8_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL8_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL9_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL9_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL9_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL9_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B) +#define BITS_AC_CHANNEL9_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL9_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL9_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL9_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL9_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL9_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL9_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL9_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL9_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL10_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL10_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL10_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL10_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B) +#define BITS_AC_CHANNEL10_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL10_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL10_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL10_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL10_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL10_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL10_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL10_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL10_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL11_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL11_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL11_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL11_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B) +#define BITS_AC_CHANNEL11_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL11_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL11_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL11_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL11_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL11_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL11_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL11_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL11_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL12_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL12_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL12_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL12_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B) +#define BITS_AC_CHANNEL12_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL12_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL12_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL12_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL12_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL12_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL12_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL12_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL12_WEIGHT_8814B(v)) + +/* 2 REG_AC_CHANNEL13_WEIGHT_8814B */ + +#define BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B 0 +#define BIT_MASK_AC_CHANNEL13_WEIGHT_8814B 0xff +#define BIT_AC_CHANNEL13_WEIGHT_8814B(x) \ + (((x) & BIT_MASK_AC_CHANNEL13_WEIGHT_8814B) \ + << BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B) +#define BITS_AC_CHANNEL13_WEIGHT_8814B \ + (BIT_MASK_AC_CHANNEL13_WEIGHT_8814B \ + << BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B) +#define BIT_CLEAR_AC_CHANNEL13_WEIGHT_8814B(x) \ + ((x) & (~BITS_AC_CHANNEL13_WEIGHT_8814B)) +#define BIT_GET_AC_CHANNEL13_WEIGHT_8814B(x) \ + (((x) >> BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B) & \ + BIT_MASK_AC_CHANNEL13_WEIGHT_8814B) +#define BIT_SET_AC_CHANNEL13_WEIGHT_8814B(x, v) \ + (BIT_CLEAR_AC_CHANNEL13_WEIGHT_8814B(x) | \ + BIT_AC_CHANNEL13_WEIGHT_8814B(v)) + +/* 2 REG_PCIE_HISR2_8814B */ +#define BIT_BCNDMAINT_P4_8814B BIT(31) +#define BIT_BCNDMAINT_P3_8814B BIT(30) +#define BIT_BCNDMAINT_P2_8814B BIT(29) +#define BIT_BCNDMAINT_P1_8814B BIT(28) +#define BIT_SCH_PHY_TXOP_SIFS_INT_8814B BIT(23) +#define BIT_ATIMEND7_8814B BIT(22) +#define BIT_ATIMEND6_8814B BIT(21) +#define BIT_ATIMEND5_8814B BIT(20) +#define BIT_ATIMEND4_8814B BIT(19) +#define BIT_ATIMEND3_8814B BIT(18) +#define BIT_ATIMEND2_8814B BIT(17) +#define BIT_ATIMEND1_8814B BIT(16) +#define BIT_TXBCN7OK_8814B BIT(14) +#define BIT_TXBCN6OK_8814B BIT(13) +#define BIT_TXBCN5OK_8814B BIT(12) +#define BIT_TXBCN4OK_8814B BIT(11) +#define BIT_TXBCN3OK_8814B BIT(10) +#define BIT_TXBCN2OK_8814B BIT(9) +#define BIT_TXBCN1OK_8814B BIT(8) +#define BIT_TXBCN7ERR_8814B BIT(6) +#define BIT_TXBCN6ERR_8814B BIT(5) +#define BIT_TXBCN5ERR_8814B BIT(4) +#define BIT_TXBCN4ERR_8814B BIT(3) +#define BIT_TXBCN3ERR_8814B BIT(2) +#define BIT_TXBCN2ERR_8814B BIT(1) +#define BIT_TXBCN1ERR_8814B BIT(0) -/* 2 REG_RX_RXBD_NUM_8814B */ -#define BIT_SYS_32_64_8814B BIT(15) +/* 2 REG_PCIE_HISR3_8814B */ +#define BIT_GTINT12_8814B BIT(24) +#define BIT_GTINT11_8814B BIT(23) +#define BIT_GTINT10_8814B BIT(22) +#define BIT_GTINT9_8814B BIT(21) +#define BIT_RX_DESC_BUF_FULL_8814B BIT(20) +#define BIT_CPHY_LDO_OCP_DET_INT_8814B BIT(19) +#define BIT_WDT_PLATFORM_INT_8814B BIT(18) +#define BIT_WDT_CPU_INT_8814B BIT(17) +#define BIT_SETH2CDOK_8814B BIT(16) +#define BIT_H2C_CMD_FULL_8814B BIT(15) +#define BIT_PKT_TRANS_ERR_8814B BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_8814B BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_8814B BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_8814B BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_8814B BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_8814B BIT(9) +#define BIT_SEARCH_FAIL_8814B BIT(8) +#define BIT_PWR_INT_127TO96_8814B BIT(7) +#define BIT_PWR_INT_95TO64_8814B BIT(6) +#define BIT_PWR_INT_63TO32_8814B BIT(5) +#define BIT_PWR_INT_31TO0_8814B BIT(4) +#define BIT_RX_DMA_STUCK_8814B BIT(3) +#define BIT_TX_DMA_STUCK_8814B BIT(2) +#define BIT_DDMA0_LP_INT_8814B BIT(1) +#define BIT_DDMA0_HP_INT_8814B BIT(0) -#define BIT_SHIFT_BCNQ_DESC_MODE_8814B 13 -#define BIT_MASK_BCNQ_DESC_MODE_8814B 0x3 -#define BIT_BCNQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8814B) << BIT_SHIFT_BCNQ_DESC_MODE_8814B) -#define BIT_GET_BCNQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8814B) & BIT_MASK_BCNQ_DESC_MODE_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_QUEUELIST_INFO0_8814B */ + +#define BIT_SHIFT_QINFO0_8814B 0 +#define BIT_MASK_QINFO0_8814B 0xffffffffL +#define BIT_QINFO0_8814B(x) \ + (((x) & BIT_MASK_QINFO0_8814B) << BIT_SHIFT_QINFO0_8814B) +#define BITS_QINFO0_8814B (BIT_MASK_QINFO0_8814B << BIT_SHIFT_QINFO0_8814B) +#define BIT_CLEAR_QINFO0_8814B(x) ((x) & (~BITS_QINFO0_8814B)) +#define BIT_GET_QINFO0_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO0_8814B) & BIT_MASK_QINFO0_8814B) +#define BIT_SET_QINFO0_8814B(x, v) \ + (BIT_CLEAR_QINFO0_8814B(x) | BIT_QINFO0_8814B(v)) + +/* 2 REG_QUEUELIST_INFO1_8814B */ + +#define BIT_SHIFT_QINFO1_8814B 0 +#define BIT_MASK_QINFO1_8814B 0xffffffffL +#define BIT_QINFO1_8814B(x) \ + (((x) & BIT_MASK_QINFO1_8814B) << BIT_SHIFT_QINFO1_8814B) +#define BITS_QINFO1_8814B (BIT_MASK_QINFO1_8814B << BIT_SHIFT_QINFO1_8814B) +#define BIT_CLEAR_QINFO1_8814B(x) ((x) & (~BITS_QINFO1_8814B)) +#define BIT_GET_QINFO1_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO1_8814B) & BIT_MASK_QINFO1_8814B) +#define BIT_SET_QINFO1_8814B(x, v) \ + (BIT_CLEAR_QINFO1_8814B(x) | BIT_QINFO1_8814B(v)) + +/* 2 REG_QUEUELIST_INFO2_8814B */ + +#define BIT_SHIFT_QINFO2_8814B 0 +#define BIT_MASK_QINFO2_8814B 0xffffffffL +#define BIT_QINFO2_8814B(x) \ + (((x) & BIT_MASK_QINFO2_8814B) << BIT_SHIFT_QINFO2_8814B) +#define BITS_QINFO2_8814B (BIT_MASK_QINFO2_8814B << BIT_SHIFT_QINFO2_8814B) +#define BIT_CLEAR_QINFO2_8814B(x) ((x) & (~BITS_QINFO2_8814B)) +#define BIT_GET_QINFO2_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO2_8814B) & BIT_MASK_QINFO2_8814B) +#define BIT_SET_QINFO2_8814B(x, v) \ + (BIT_CLEAR_QINFO2_8814B(x) | BIT_QINFO2_8814B(v)) + +/* 2 REG_QUEUELIST_INFO3_8814B */ + +#define BIT_SHIFT_QINFO3_8814B 0 +#define BIT_MASK_QINFO3_8814B 0xffffffffL +#define BIT_QINFO3_8814B(x) \ + (((x) & BIT_MASK_QINFO3_8814B) << BIT_SHIFT_QINFO3_8814B) +#define BITS_QINFO3_8814B (BIT_MASK_QINFO3_8814B << BIT_SHIFT_QINFO3_8814B) +#define BIT_CLEAR_QINFO3_8814B(x) ((x) & (~BITS_QINFO3_8814B)) +#define BIT_GET_QINFO3_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO3_8814B) & BIT_MASK_QINFO3_8814B) +#define BIT_SET_QINFO3_8814B(x, v) \ + (BIT_CLEAR_QINFO3_8814B(x) | BIT_QINFO3_8814B(v)) + +/* 2 REG_QUEUELIST_INFO_EMPTY_8814B */ +#define BIT_FWCMDQ_EMPTY_8814B BIT(31) +#define BIT_MGQ_CPU_EMPTY_V1_8814B BIT(30) +#define BIT_BCNQ_EMPTY_EXTP0_8814B BIT(29) +#define BIT_BCNQ_EMPTY_PORT4_8814B BIT(28) +#define BIT_BCNQ_EMPTY_PORT3_8814B BIT(27) +#define BIT_BCNQ_EMPTY_PORT2_8814B BIT(26) +#define BIT_BCNQ_EMPTY_PORT1_8814B BIT(25) +#define BIT_BCNQ_EMPTY_PORT0_8814B BIT(24) +#define BIT_HQQ_EMPTY_V1_8814B BIT(23) +#define BIT_MQQ_EMPTY_V2_8814B BIT(22) +#define BIT_S1_EMPTY_8814B BIT(21) +#define BIT_S0_EMPTY_8814B BIT(20) +#define BIT_AC19Q_EMPTY_8814B BIT(19) +#define BIT_AC18Q_EMPTY_8814B BIT(18) +#define BIT_AC17Q_EMPTY_8814B BIT(17) +#define BIT_AC16Q_EMPTY_8814B BIT(16) +#define BIT_AC15Q_EMPTY_8814B BIT(15) +#define BIT_AC14Q_EMPTY_8814B BIT(14) +#define BIT_AC13Q_EMPTY_8814B BIT(13) +#define BIT_AC12Q_EMPTY_8814B BIT(12) +#define BIT_AC11Q_EMPTY_8814B BIT(11) +#define BIT_AC10Q_EMPTY_8814B BIT(10) +#define BIT_AC9Q_EMPTY_8814B BIT(9) +#define BIT_AC8Q_EMPTY_8814B BIT(8) +#define BIT_AC7Q_EMPTY_8814B BIT(7) +#define BIT_AC6Q_EMPTY_8814B BIT(6) +#define BIT_AC5Q_EMPTY_8814B BIT(5) +#define BIT_AC4Q_EMPTY_8814B BIT(4) +#define BIT_AC3Q_EMPTY_8814B BIT(3) +#define BIT_AC2Q_EMPTY_8814B BIT(2) +#define BIT_AC1Q_EMPTY_8814B BIT(1) +#define BIT_AC0Q_EMPTY_8814B BIT(0) -#define BIT_PCIE_BCNQ_FLAG_8814B BIT(12) +/* 2 REG_QUEUELIST_ACQ_EN_8814B */ + +#define BIT_SHIFT_QINFO_CTRL_8814B 24 +#define BIT_MASK_QINFO_CTRL_8814B 0x3f +#define BIT_QINFO_CTRL_8814B(x) \ + (((x) & BIT_MASK_QINFO_CTRL_8814B) << BIT_SHIFT_QINFO_CTRL_8814B) +#define BITS_QINFO_CTRL_8814B \ + (BIT_MASK_QINFO_CTRL_8814B << BIT_SHIFT_QINFO_CTRL_8814B) +#define BIT_CLEAR_QINFO_CTRL_8814B(x) ((x) & (~BITS_QINFO_CTRL_8814B)) +#define BIT_GET_QINFO_CTRL_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO_CTRL_8814B) & BIT_MASK_QINFO_CTRL_8814B) +#define BIT_SET_QINFO_CTRL_8814B(x, v) \ + (BIT_CLEAR_QINFO_CTRL_8814B(x) | BIT_QINFO_CTRL_8814B(v)) + +#define BIT_SHIFT_QINFO_MODE_BAND_8814B 20 +#define BIT_MASK_QINFO_MODE_BAND_8814B 0x7 +#define BIT_QINFO_MODE_BAND_8814B(x) \ + (((x) & BIT_MASK_QINFO_MODE_BAND_8814B) \ + << BIT_SHIFT_QINFO_MODE_BAND_8814B) +#define BITS_QINFO_MODE_BAND_8814B \ + (BIT_MASK_QINFO_MODE_BAND_8814B << BIT_SHIFT_QINFO_MODE_BAND_8814B) +#define BIT_CLEAR_QINFO_MODE_BAND_8814B(x) ((x) & (~BITS_QINFO_MODE_BAND_8814B)) +#define BIT_GET_QINFO_MODE_BAND_8814B(x) \ + (((x) >> BIT_SHIFT_QINFO_MODE_BAND_8814B) & \ + BIT_MASK_QINFO_MODE_BAND_8814B) +#define BIT_SET_QINFO_MODE_BAND_8814B(x, v) \ + (BIT_CLEAR_QINFO_MODE_BAND_8814B(x) | BIT_QINFO_MODE_BAND_8814B(v)) + +#define BIT_ACQ19_ENABLE_8814B BIT(19) +#define BIT_ACQ18_ENABLE_8814B BIT(18) +#define BIT_ACQ17_ENABLE_8814B BIT(17) +#define BIT_ACQ16_ENABLE_8814B BIT(16) +#define BIT_ACQ15_ENABLE_8814B BIT(15) +#define BIT_ACQ14_ENABLE_8814B BIT(14) +#define BIT_ACQ13_ENABLE_8814B BIT(13) +#define BIT_ACQ12_ENABLE_8814B BIT(12) +#define BIT_ACQ11_ENABLE_8814B BIT(11) +#define BIT_ACQ10_ENABLE_8814B BIT(10) +#define BIT_ACQ9_ENABLE_8814B BIT(9) +#define BIT_ACQ8_ENABLE_8814B BIT(8) +#define BIT_ACQ7_ENABLE_8814B BIT(7) +#define BIT_ACQ6_ENABLE_8814B BIT(6) +#define BIT_ACQ5_ENABLE_8814B BIT(5) +#define BIT_ACQ4_ENABLE_8814B BIT(4) +#define BIT_ACQ3_ENABLE_8814B BIT(3) +#define BIT_ACQ2_ENABLE_8814B BIT(2) +#define BIT_ACQ1_ENABLE_8814B BIT(1) +#define BIT_ACQ0_ENABLE_8814B BIT(0) + +/* 2 REG_BCNQ_BDNY_V2_8814B */ + +#define BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B 28 +#define BIT_MASK_BCNQ_PGBNDY_WSEL_8814B 0x7 +#define BIT_BCNQ_PGBNDY_WSEL_8814B(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_WSEL_8814B) \ + << BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B) +#define BITS_BCNQ_PGBNDY_WSEL_8814B \ + (BIT_MASK_BCNQ_PGBNDY_WSEL_8814B << BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B) +#define BIT_CLEAR_BCNQ_PGBNDY_WSEL_8814B(x) \ + ((x) & (~BITS_BCNQ_PGBNDY_WSEL_8814B)) +#define BIT_GET_BCNQ_PGBNDY_WSEL_8814B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B) & \ + BIT_MASK_BCNQ_PGBNDY_WSEL_8814B) +#define BIT_SET_BCNQ_PGBNDY_WSEL_8814B(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_WSEL_8814B(x) | BIT_BCNQ_PGBNDY_WSEL_8814B(v)) + +#define BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B 12 +#define BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B 0xfff +#define BIT_BCNQ_PGBNDY_RCONTENT_8814B(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B) \ + << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B) +#define BITS_BCNQ_PGBNDY_RCONTENT_8814B \ + (BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B \ + << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B) +#define BIT_CLEAR_BCNQ_PGBNDY_RCONTENT_8814B(x) \ + ((x) & (~BITS_BCNQ_PGBNDY_RCONTENT_8814B)) +#define BIT_GET_BCNQ_PGBNDY_RCONTENT_8814B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B) & \ + BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B) +#define BIT_SET_BCNQ_PGBNDY_RCONTENT_8814B(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_RCONTENT_8814B(x) | \ + BIT_BCNQ_PGBNDY_RCONTENT_8814B(v)) + +#define BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B 0 +#define BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B 0xfff +#define BIT_BCNQ_PGBNDY_WCONTENT_8814B(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B) \ + << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B) +#define BITS_BCNQ_PGBNDY_WCONTENT_8814B \ + (BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B \ + << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B) +#define BIT_CLEAR_BCNQ_PGBNDY_WCONTENT_8814B(x) \ + ((x) & (~BITS_BCNQ_PGBNDY_WCONTENT_8814B)) +#define BIT_GET_BCNQ_PGBNDY_WCONTENT_8814B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B) & \ + BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B) +#define BIT_SET_BCNQ_PGBNDY_WCONTENT_8814B(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_WCONTENT_8814B(x) | \ + BIT_BCNQ_PGBNDY_WCONTENT_8814B(v)) -#define BIT_SHIFT_RXQ_DESC_NUM_8814B 0 -#define BIT_MASK_RXQ_DESC_NUM_8814B 0xfff -#define BIT_RXQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8814B) << BIT_SHIFT_RXQ_DESC_NUM_8814B) -#define BIT_GET_RXQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8814B) & BIT_MASK_RXQ_DESC_NUM_8814B) +/* 2 REG_CPU_MGQ_INFO_8814B */ +#define BIT_CPUMGT_CLR_V1_8814B BIT(30) +#define BIT_CPUMGT_POLL_8814B BIT(29) +#define BIT_BCN_EXT_POLL_8814B BIT(21) +#define BIT_BCN4_POLL_8814B BIT(20) +#define BIT_BCN3_POLL_8814B BIT(19) +#define BIT_BCN2_POLL_8814B BIT(18) +#define BIT_BCN1_POLL_V1_8814B BIT(17) +#define BIT_BCN_POLL_V1_8814B BIT(16) + +#define BIT_SHIFT_FREE_TAIL_PAGE_8814B 0 +#define BIT_MASK_FREE_TAIL_PAGE_8814B 0xfff +#define BIT_FREE_TAIL_PAGE_8814B(x) \ + (((x) & BIT_MASK_FREE_TAIL_PAGE_8814B) \ + << BIT_SHIFT_FREE_TAIL_PAGE_8814B) +#define BITS_FREE_TAIL_PAGE_8814B \ + (BIT_MASK_FREE_TAIL_PAGE_8814B << BIT_SHIFT_FREE_TAIL_PAGE_8814B) +#define BIT_CLEAR_FREE_TAIL_PAGE_8814B(x) ((x) & (~BITS_FREE_TAIL_PAGE_8814B)) +#define BIT_GET_FREE_TAIL_PAGE_8814B(x) \ + (((x) >> BIT_SHIFT_FREE_TAIL_PAGE_8814B) & \ + BIT_MASK_FREE_TAIL_PAGE_8814B) +#define BIT_SET_FREE_TAIL_PAGE_8814B(x, v) \ + (BIT_CLEAR_FREE_TAIL_PAGE_8814B(x) | BIT_FREE_TAIL_PAGE_8814B(v)) +/* 2 REG_FWHW_TXQ_CTRL_8814B */ +#define BIT_RTS_LIMIT_IN_OFDM_8814B BIT(23) +#define BIT_EN_RD_RESP_NAV_BK_8814B BIT(21) +#define BIT_EN_WR_FREE_TAIL_8814B BIT(20) +#define BIT_NOTXRPT_USERATE_EN_8814B BIT(19) +#define BIT_DIS_TXFAIL_RPT_8814B BIT(18) +#define BIT_FTM_TIMEOUT_BYPASS_8814B BIT(16) +#define BIT_EN_BCNQ_DL5_8814B BIT(13) +#define BIT_EN_BCNQ_DL4_8814B BIT(12) +#define BIT_EN_BCNQ_DL3_8814B BIT(11) +#define BIT_EN_BCNQ_DL2_8814B BIT(10) +#define BIT_EN_BCNQ_DL1_8814B BIT(9) +#define BIT_EN_BCNQ_DL0_8814B BIT(8) +#define BIT_EN_RTY_BK_8814B BIT(7) +#define BIT_EN_USE_INI_RAT_8814B BIT(6) +#define BIT_EN_RTS_NAV_BK_8814B BIT(5) +#define BIT_DIS_SSN_CHECK_8814B BIT(4) +#define BIT_MACID_MATCH_RTS_8814B BIT(3) +#define BIT_EN_BCN_TRXRPT_V1_8814B BIT(2) +#define BIT_EN_FTMRPT_V1_8814B BIT(1) +#define BIT_BMC_NAV_PROTECT_8814B BIT(0) +/* 2 REG_DATAFB_SEL_8814B */ +#define BIT_BROADCAST_RTY_EN_8814B BIT(3) +#define BIT_EN_RTY_BK_COD_8814B BIT(2) + +#define BIT_SHIFT__DATA_FALLBACK_SEL_8814B 0 +#define BIT_MASK__DATA_FALLBACK_SEL_8814B 0x3 +#define BIT__DATA_FALLBACK_SEL_8814B(x) \ + (((x) & BIT_MASK__DATA_FALLBACK_SEL_8814B) \ + << BIT_SHIFT__DATA_FALLBACK_SEL_8814B) +#define BITS__DATA_FALLBACK_SEL_8814B \ + (BIT_MASK__DATA_FALLBACK_SEL_8814B \ + << BIT_SHIFT__DATA_FALLBACK_SEL_8814B) +#define BIT_CLEAR__DATA_FALLBACK_SEL_8814B(x) \ + ((x) & (~BITS__DATA_FALLBACK_SEL_8814B)) +#define BIT_GET__DATA_FALLBACK_SEL_8814B(x) \ + (((x) >> BIT_SHIFT__DATA_FALLBACK_SEL_8814B) & \ + BIT_MASK__DATA_FALLBACK_SEL_8814B) +#define BIT_SET__DATA_FALLBACK_SEL_8814B(x, v) \ + (BIT_CLEAR__DATA_FALLBACK_SEL_8814B(x) | \ + BIT__DATA_FALLBACK_SEL_8814B(v)) + +/* 2 REG_TXBDNY_8814B */ + +#define BIT_SHIFT_TXBNDY_8814B 0 +#define BIT_MASK_TXBNDY_8814B 0xfff +#define BIT_TXBNDY_8814B(x) \ + (((x) & BIT_MASK_TXBNDY_8814B) << BIT_SHIFT_TXBNDY_8814B) +#define BITS_TXBNDY_8814B (BIT_MASK_TXBNDY_8814B << BIT_SHIFT_TXBNDY_8814B) +#define BIT_CLEAR_TXBNDY_8814B(x) ((x) & (~BITS_TXBNDY_8814B)) +#define BIT_GET_TXBNDY_8814B(x) \ + (((x) >> BIT_SHIFT_TXBNDY_8814B) & BIT_MASK_TXBNDY_8814B) +#define BIT_SET_TXBNDY_8814B(x, v) \ + (BIT_CLEAR_TXBNDY_8814B(x) | BIT_TXBNDY_8814B(v)) -/* 2 REG_VOQ_TXBD_NUM_8814B */ -#define BIT_PCIE_VOQ_FLAG_8814B BIT(14) +/* 2 REG_LIFETIME_EN_8814B */ +#define BIT_BT_INT_CPU_8814B BIT(7) +#define BIT_BT_INT_PTA_8814B BIT(6) +#define BIT_EN_CTRL_RTYBIT_8814B BIT(4) +#define BIT_LIFETIME_BK_EN_8814B BIT(3) +#define BIT_LIFETIME_BE_EN_8814B BIT(2) +#define BIT_LIFETIME_VI_EN_8814B BIT(1) +#define BIT_LIFETIME_VO_EN_8814B BIT(0) -#define BIT_SHIFT_VOQ_DESC_MODE_8814B 12 -#define BIT_MASK_VOQ_DESC_MODE_8814B 0x3 -#define BIT_VOQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8814B) << BIT_SHIFT_VOQ_DESC_MODE_8814B) -#define BIT_GET_VOQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8814B) & BIT_MASK_VOQ_DESC_MODE_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_SPEC_SIFS_8814B */ +#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B 8 +#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B 0xff +#define BIT_SPEC_SIFS_OFDM_PTCL_8814B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) +#define BITS_SPEC_SIFS_OFDM_PTCL_8814B \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8814B(x) \ + ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8814B)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8814B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) & \ + BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8814B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8814B(x) | \ + BIT_SPEC_SIFS_OFDM_PTCL_8814B(v)) -#define BIT_SHIFT_VOQ_DESC_NUM_8814B 0 -#define BIT_MASK_VOQ_DESC_NUM_8814B 0xfff -#define BIT_VOQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8814B) << BIT_SHIFT_VOQ_DESC_NUM_8814B) -#define BIT_GET_VOQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8814B) & BIT_MASK_VOQ_DESC_NUM_8814B) +#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B 0 +#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B 0xff +#define BIT_SPEC_SIFS_CCK_PTCL_8814B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B) \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) +#define BITS_SPEC_SIFS_CCK_PTCL_8814B \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8814B(x) \ + ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8814B)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8814B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) & \ + BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B) +#define BIT_SET_SPEC_SIFS_CCK_PTCL_8814B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8814B(x) | \ + BIT_SPEC_SIFS_CCK_PTCL_8814B(v)) +/* 2 REG_RETRY_LIMIT_8814B */ +#define BIT_SHIFT_SRL_8814B 8 +#define BIT_MASK_SRL_8814B 0x3f +#define BIT_SRL_8814B(x) (((x) & BIT_MASK_SRL_8814B) << BIT_SHIFT_SRL_8814B) +#define BITS_SRL_8814B (BIT_MASK_SRL_8814B << BIT_SHIFT_SRL_8814B) +#define BIT_CLEAR_SRL_8814B(x) ((x) & (~BITS_SRL_8814B)) +#define BIT_GET_SRL_8814B(x) (((x) >> BIT_SHIFT_SRL_8814B) & BIT_MASK_SRL_8814B) +#define BIT_SET_SRL_8814B(x, v) (BIT_CLEAR_SRL_8814B(x) | BIT_SRL_8814B(v)) -/* 2 REG_VIQ_TXBD_NUM_8814B */ -#define BIT_PCIE_VIQ_FLAG_8814B BIT(14) +#define BIT_SHIFT_LRL_8814B 0 +#define BIT_MASK_LRL_8814B 0x3f +#define BIT_LRL_8814B(x) (((x) & BIT_MASK_LRL_8814B) << BIT_SHIFT_LRL_8814B) +#define BITS_LRL_8814B (BIT_MASK_LRL_8814B << BIT_SHIFT_LRL_8814B) +#define BIT_CLEAR_LRL_8814B(x) ((x) & (~BITS_LRL_8814B)) +#define BIT_GET_LRL_8814B(x) (((x) >> BIT_SHIFT_LRL_8814B) & BIT_MASK_LRL_8814B) +#define BIT_SET_LRL_8814B(x, v) (BIT_CLEAR_LRL_8814B(x) | BIT_LRL_8814B(v)) -#define BIT_SHIFT_VIQ_DESC_MODE_8814B 12 -#define BIT_MASK_VIQ_DESC_MODE_8814B 0x3 -#define BIT_VIQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8814B) << BIT_SHIFT_VIQ_DESC_MODE_8814B) -#define BIT_GET_VIQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8814B) & BIT_MASK_VIQ_DESC_MODE_8814B) +/* 2 REG_TXBF_CTRL_8814B */ +#define BIT_ENABLE_NDPA_8814B BIT(31) +#define BIT_NDPA_PARA_8814B BIT(30) +#define BIT_PROP_TXBF_8814B BIT(29) +#define BIT_EN_NDPA_INT_8814B BIT(28) +#define BIT_TXBF1_80M_160M_8814B BIT(27) +#define BIT_TXBF1_40M_8814B BIT(26) +#define BIT_TXBF1_20M_8814B BIT(25) + +#define BIT_SHIFT_TXBF1_AID_8814B 16 +#define BIT_MASK_TXBF1_AID_8814B 0x1ff +#define BIT_TXBF1_AID_8814B(x) \ + (((x) & BIT_MASK_TXBF1_AID_8814B) << BIT_SHIFT_TXBF1_AID_8814B) +#define BITS_TXBF1_AID_8814B \ + (BIT_MASK_TXBF1_AID_8814B << BIT_SHIFT_TXBF1_AID_8814B) +#define BIT_CLEAR_TXBF1_AID_8814B(x) ((x) & (~BITS_TXBF1_AID_8814B)) +#define BIT_GET_TXBF1_AID_8814B(x) \ + (((x) >> BIT_SHIFT_TXBF1_AID_8814B) & BIT_MASK_TXBF1_AID_8814B) +#define BIT_SET_TXBF1_AID_8814B(x, v) \ + (BIT_CLEAR_TXBF1_AID_8814B(x) | BIT_TXBF1_AID_8814B(v)) +#define BIT_DIS_NDP_BFEN_8814B BIT(15) +#define BIT_TXBCN_NOBLOCK_NDP_8814B BIT(14) +#define BIT_TXBF0_80M_160M_8814B BIT(11) +#define BIT_TXBF0_40M_8814B BIT(10) +#define BIT_TXBF0_20M_8814B BIT(9) + +#define BIT_SHIFT_TXBF0_AID_8814B 0 +#define BIT_MASK_TXBF0_AID_8814B 0x1ff +#define BIT_TXBF0_AID_8814B(x) \ + (((x) & BIT_MASK_TXBF0_AID_8814B) << BIT_SHIFT_TXBF0_AID_8814B) +#define BITS_TXBF0_AID_8814B \ + (BIT_MASK_TXBF0_AID_8814B << BIT_SHIFT_TXBF0_AID_8814B) +#define BIT_CLEAR_TXBF0_AID_8814B(x) ((x) & (~BITS_TXBF0_AID_8814B)) +#define BIT_GET_TXBF0_AID_8814B(x) \ + (((x) >> BIT_SHIFT_TXBF0_AID_8814B) & BIT_MASK_TXBF0_AID_8814B) +#define BIT_SET_TXBF0_AID_8814B(x, v) \ + (BIT_CLEAR_TXBF0_AID_8814B(x) | BIT_TXBF0_AID_8814B(v)) +/* 2 REG_DARFRC_8814B */ -#define BIT_SHIFT_VIQ_DESC_NUM_8814B 0 -#define BIT_MASK_VIQ_DESC_NUM_8814B 0xfff -#define BIT_VIQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8814B) << BIT_SHIFT_VIQ_DESC_NUM_8814B) -#define BIT_GET_VIQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8814B) & BIT_MASK_VIQ_DESC_NUM_8814B) +#define BIT_SHIFT_DARF_RC4_V1_8814B 24 +#define BIT_MASK_DARF_RC4_V1_8814B 0x3f +#define BIT_DARF_RC4_V1_8814B(x) \ + (((x) & BIT_MASK_DARF_RC4_V1_8814B) << BIT_SHIFT_DARF_RC4_V1_8814B) +#define BITS_DARF_RC4_V1_8814B \ + (BIT_MASK_DARF_RC4_V1_8814B << BIT_SHIFT_DARF_RC4_V1_8814B) +#define BIT_CLEAR_DARF_RC4_V1_8814B(x) ((x) & (~BITS_DARF_RC4_V1_8814B)) +#define BIT_GET_DARF_RC4_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_V1_8814B) & BIT_MASK_DARF_RC4_V1_8814B) +#define BIT_SET_DARF_RC4_V1_8814B(x, v) \ + (BIT_CLEAR_DARF_RC4_V1_8814B(x) | BIT_DARF_RC4_V1_8814B(v)) + +#define BIT_SHIFT_DARF_RC3_V1_8814B 16 +#define BIT_MASK_DARF_RC3_V1_8814B 0x3f +#define BIT_DARF_RC3_V1_8814B(x) \ + (((x) & BIT_MASK_DARF_RC3_V1_8814B) << BIT_SHIFT_DARF_RC3_V1_8814B) +#define BITS_DARF_RC3_V1_8814B \ + (BIT_MASK_DARF_RC3_V1_8814B << BIT_SHIFT_DARF_RC3_V1_8814B) +#define BIT_CLEAR_DARF_RC3_V1_8814B(x) ((x) & (~BITS_DARF_RC3_V1_8814B)) +#define BIT_GET_DARF_RC3_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_V1_8814B) & BIT_MASK_DARF_RC3_V1_8814B) +#define BIT_SET_DARF_RC3_V1_8814B(x, v) \ + (BIT_CLEAR_DARF_RC3_V1_8814B(x) | BIT_DARF_RC3_V1_8814B(v)) + +#define BIT_SHIFT_DARF_RC2_V1_8814B 8 +#define BIT_MASK_DARF_RC2_V1_8814B 0x3f +#define BIT_DARF_RC2_V1_8814B(x) \ + (((x) & BIT_MASK_DARF_RC2_V1_8814B) << BIT_SHIFT_DARF_RC2_V1_8814B) +#define BITS_DARF_RC2_V1_8814B \ + (BIT_MASK_DARF_RC2_V1_8814B << BIT_SHIFT_DARF_RC2_V1_8814B) +#define BIT_CLEAR_DARF_RC2_V1_8814B(x) ((x) & (~BITS_DARF_RC2_V1_8814B)) +#define BIT_GET_DARF_RC2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_V1_8814B) & BIT_MASK_DARF_RC2_V1_8814B) +#define BIT_SET_DARF_RC2_V1_8814B(x, v) \ + (BIT_CLEAR_DARF_RC2_V1_8814B(x) | BIT_DARF_RC2_V1_8814B(v)) + +#define BIT_SHIFT_DARF_RC1_V1_8814B 0 +#define BIT_MASK_DARF_RC1_V1_8814B 0x3f +#define BIT_DARF_RC1_V1_8814B(x) \ + (((x) & BIT_MASK_DARF_RC1_V1_8814B) << BIT_SHIFT_DARF_RC1_V1_8814B) +#define BITS_DARF_RC1_V1_8814B \ + (BIT_MASK_DARF_RC1_V1_8814B << BIT_SHIFT_DARF_RC1_V1_8814B) +#define BIT_CLEAR_DARF_RC1_V1_8814B(x) ((x) & (~BITS_DARF_RC1_V1_8814B)) +#define BIT_GET_DARF_RC1_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_V1_8814B) & BIT_MASK_DARF_RC1_V1_8814B) +#define BIT_SET_DARF_RC1_V1_8814B(x, v) \ + (BIT_CLEAR_DARF_RC1_V1_8814B(x) | BIT_DARF_RC1_V1_8814B(v)) + +/* 2 REG_DARFRCH_8814B */ + +#define BIT_SHIFT_DARF_RC8_V2_8814B 24 +#define BIT_MASK_DARF_RC8_V2_8814B 0x3f +#define BIT_DARF_RC8_V2_8814B(x) \ + (((x) & BIT_MASK_DARF_RC8_V2_8814B) << BIT_SHIFT_DARF_RC8_V2_8814B) +#define BITS_DARF_RC8_V2_8814B \ + (BIT_MASK_DARF_RC8_V2_8814B << BIT_SHIFT_DARF_RC8_V2_8814B) +#define BIT_CLEAR_DARF_RC8_V2_8814B(x) ((x) & (~BITS_DARF_RC8_V2_8814B)) +#define BIT_GET_DARF_RC8_V2_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_V2_8814B) & BIT_MASK_DARF_RC8_V2_8814B) +#define BIT_SET_DARF_RC8_V2_8814B(x, v) \ + (BIT_CLEAR_DARF_RC8_V2_8814B(x) | BIT_DARF_RC8_V2_8814B(v)) + +#define BIT_SHIFT_DARF_RC7_V2_8814B 16 +#define BIT_MASK_DARF_RC7_V2_8814B 0x3f +#define BIT_DARF_RC7_V2_8814B(x) \ + (((x) & BIT_MASK_DARF_RC7_V2_8814B) << BIT_SHIFT_DARF_RC7_V2_8814B) +#define BITS_DARF_RC7_V2_8814B \ + (BIT_MASK_DARF_RC7_V2_8814B << BIT_SHIFT_DARF_RC7_V2_8814B) +#define BIT_CLEAR_DARF_RC7_V2_8814B(x) ((x) & (~BITS_DARF_RC7_V2_8814B)) +#define BIT_GET_DARF_RC7_V2_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_V2_8814B) & BIT_MASK_DARF_RC7_V2_8814B) +#define BIT_SET_DARF_RC7_V2_8814B(x, v) \ + (BIT_CLEAR_DARF_RC7_V2_8814B(x) | BIT_DARF_RC7_V2_8814B(v)) + +#define BIT_SHIFT_DARF_RC6_V2_8814B 8 +#define BIT_MASK_DARF_RC6_V2_8814B 0x3f +#define BIT_DARF_RC6_V2_8814B(x) \ + (((x) & BIT_MASK_DARF_RC6_V2_8814B) << BIT_SHIFT_DARF_RC6_V2_8814B) +#define BITS_DARF_RC6_V2_8814B \ + (BIT_MASK_DARF_RC6_V2_8814B << BIT_SHIFT_DARF_RC6_V2_8814B) +#define BIT_CLEAR_DARF_RC6_V2_8814B(x) ((x) & (~BITS_DARF_RC6_V2_8814B)) +#define BIT_GET_DARF_RC6_V2_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_V2_8814B) & BIT_MASK_DARF_RC6_V2_8814B) +#define BIT_SET_DARF_RC6_V2_8814B(x, v) \ + (BIT_CLEAR_DARF_RC6_V2_8814B(x) | BIT_DARF_RC6_V2_8814B(v)) + +#define BIT_SHIFT_DARF_RC5_V2_8814B 0 +#define BIT_MASK_DARF_RC5_V2_8814B 0x3f +#define BIT_DARF_RC5_V2_8814B(x) \ + (((x) & BIT_MASK_DARF_RC5_V2_8814B) << BIT_SHIFT_DARF_RC5_V2_8814B) +#define BITS_DARF_RC5_V2_8814B \ + (BIT_MASK_DARF_RC5_V2_8814B << BIT_SHIFT_DARF_RC5_V2_8814B) +#define BIT_CLEAR_DARF_RC5_V2_8814B(x) ((x) & (~BITS_DARF_RC5_V2_8814B)) +#define BIT_GET_DARF_RC5_V2_8814B(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_V2_8814B) & BIT_MASK_DARF_RC5_V2_8814B) +#define BIT_SET_DARF_RC5_V2_8814B(x, v) \ + (BIT_CLEAR_DARF_RC5_V2_8814B(x) | BIT_DARF_RC5_V2_8814B(v)) +/* 2 REG_RARFRC_8814B */ +#define BIT_SHIFT_RARF_RC4_8814B 24 +#define BIT_MASK_RARF_RC4_8814B 0x1f +#define BIT_RARF_RC4_8814B(x) \ + (((x) & BIT_MASK_RARF_RC4_8814B) << BIT_SHIFT_RARF_RC4_8814B) +#define BITS_RARF_RC4_8814B \ + (BIT_MASK_RARF_RC4_8814B << BIT_SHIFT_RARF_RC4_8814B) +#define BIT_CLEAR_RARF_RC4_8814B(x) ((x) & (~BITS_RARF_RC4_8814B)) +#define BIT_GET_RARF_RC4_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC4_8814B) & BIT_MASK_RARF_RC4_8814B) +#define BIT_SET_RARF_RC4_8814B(x, v) \ + (BIT_CLEAR_RARF_RC4_8814B(x) | BIT_RARF_RC4_8814B(v)) -/* 2 REG_BEQ_TXBD_NUM_8814B */ -#define BIT_PCIE_BEQ_FLAG_8814B BIT(14) +#define BIT_SHIFT_RARF_RC3_8814B 16 +#define BIT_MASK_RARF_RC3_8814B 0x1f +#define BIT_RARF_RC3_8814B(x) \ + (((x) & BIT_MASK_RARF_RC3_8814B) << BIT_SHIFT_RARF_RC3_8814B) +#define BITS_RARF_RC3_8814B \ + (BIT_MASK_RARF_RC3_8814B << BIT_SHIFT_RARF_RC3_8814B) +#define BIT_CLEAR_RARF_RC3_8814B(x) ((x) & (~BITS_RARF_RC3_8814B)) +#define BIT_GET_RARF_RC3_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC3_8814B) & BIT_MASK_RARF_RC3_8814B) +#define BIT_SET_RARF_RC3_8814B(x, v) \ + (BIT_CLEAR_RARF_RC3_8814B(x) | BIT_RARF_RC3_8814B(v)) -#define BIT_SHIFT_BEQ_DESC_MODE_8814B 12 -#define BIT_MASK_BEQ_DESC_MODE_8814B 0x3 -#define BIT_BEQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8814B) << BIT_SHIFT_BEQ_DESC_MODE_8814B) -#define BIT_GET_BEQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8814B) & BIT_MASK_BEQ_DESC_MODE_8814B) +#define BIT_SHIFT_RARF_RC2_8814B 8 +#define BIT_MASK_RARF_RC2_8814B 0x1f +#define BIT_RARF_RC2_8814B(x) \ + (((x) & BIT_MASK_RARF_RC2_8814B) << BIT_SHIFT_RARF_RC2_8814B) +#define BITS_RARF_RC2_8814B \ + (BIT_MASK_RARF_RC2_8814B << BIT_SHIFT_RARF_RC2_8814B) +#define BIT_CLEAR_RARF_RC2_8814B(x) ((x) & (~BITS_RARF_RC2_8814B)) +#define BIT_GET_RARF_RC2_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC2_8814B) & BIT_MASK_RARF_RC2_8814B) +#define BIT_SET_RARF_RC2_8814B(x, v) \ + (BIT_CLEAR_RARF_RC2_8814B(x) | BIT_RARF_RC2_8814B(v)) +#define BIT_SHIFT_RARF_RC1_8814B 0 +#define BIT_MASK_RARF_RC1_8814B 0x1f +#define BIT_RARF_RC1_8814B(x) \ + (((x) & BIT_MASK_RARF_RC1_8814B) << BIT_SHIFT_RARF_RC1_8814B) +#define BITS_RARF_RC1_8814B \ + (BIT_MASK_RARF_RC1_8814B << BIT_SHIFT_RARF_RC1_8814B) +#define BIT_CLEAR_RARF_RC1_8814B(x) ((x) & (~BITS_RARF_RC1_8814B)) +#define BIT_GET_RARF_RC1_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC1_8814B) & BIT_MASK_RARF_RC1_8814B) +#define BIT_SET_RARF_RC1_8814B(x, v) \ + (BIT_CLEAR_RARF_RC1_8814B(x) | BIT_RARF_RC1_8814B(v)) + +/* 2 REG_RARFRCH_8814B */ + +#define BIT_SHIFT_RARF_RC8_V1_8814B 24 +#define BIT_MASK_RARF_RC8_V1_8814B 0x1f +#define BIT_RARF_RC8_V1_8814B(x) \ + (((x) & BIT_MASK_RARF_RC8_V1_8814B) << BIT_SHIFT_RARF_RC8_V1_8814B) +#define BITS_RARF_RC8_V1_8814B \ + (BIT_MASK_RARF_RC8_V1_8814B << BIT_SHIFT_RARF_RC8_V1_8814B) +#define BIT_CLEAR_RARF_RC8_V1_8814B(x) ((x) & (~BITS_RARF_RC8_V1_8814B)) +#define BIT_GET_RARF_RC8_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_V1_8814B) & BIT_MASK_RARF_RC8_V1_8814B) +#define BIT_SET_RARF_RC8_V1_8814B(x, v) \ + (BIT_CLEAR_RARF_RC8_V1_8814B(x) | BIT_RARF_RC8_V1_8814B(v)) + +#define BIT_SHIFT_RARF_RC7_V1_8814B 16 +#define BIT_MASK_RARF_RC7_V1_8814B 0x1f +#define BIT_RARF_RC7_V1_8814B(x) \ + (((x) & BIT_MASK_RARF_RC7_V1_8814B) << BIT_SHIFT_RARF_RC7_V1_8814B) +#define BITS_RARF_RC7_V1_8814B \ + (BIT_MASK_RARF_RC7_V1_8814B << BIT_SHIFT_RARF_RC7_V1_8814B) +#define BIT_CLEAR_RARF_RC7_V1_8814B(x) ((x) & (~BITS_RARF_RC7_V1_8814B)) +#define BIT_GET_RARF_RC7_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_V1_8814B) & BIT_MASK_RARF_RC7_V1_8814B) +#define BIT_SET_RARF_RC7_V1_8814B(x, v) \ + (BIT_CLEAR_RARF_RC7_V1_8814B(x) | BIT_RARF_RC7_V1_8814B(v)) + +#define BIT_SHIFT_RARF_RC6_V1_8814B 8 +#define BIT_MASK_RARF_RC6_V1_8814B 0x1f +#define BIT_RARF_RC6_V1_8814B(x) \ + (((x) & BIT_MASK_RARF_RC6_V1_8814B) << BIT_SHIFT_RARF_RC6_V1_8814B) +#define BITS_RARF_RC6_V1_8814B \ + (BIT_MASK_RARF_RC6_V1_8814B << BIT_SHIFT_RARF_RC6_V1_8814B) +#define BIT_CLEAR_RARF_RC6_V1_8814B(x) ((x) & (~BITS_RARF_RC6_V1_8814B)) +#define BIT_GET_RARF_RC6_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_V1_8814B) & BIT_MASK_RARF_RC6_V1_8814B) +#define BIT_SET_RARF_RC6_V1_8814B(x, v) \ + (BIT_CLEAR_RARF_RC6_V1_8814B(x) | BIT_RARF_RC6_V1_8814B(v)) + +#define BIT_SHIFT_RARF_RC5_V1_8814B 0 +#define BIT_MASK_RARF_RC5_V1_8814B 0x1f +#define BIT_RARF_RC5_V1_8814B(x) \ + (((x) & BIT_MASK_RARF_RC5_V1_8814B) << BIT_SHIFT_RARF_RC5_V1_8814B) +#define BITS_RARF_RC5_V1_8814B \ + (BIT_MASK_RARF_RC5_V1_8814B << BIT_SHIFT_RARF_RC5_V1_8814B) +#define BIT_CLEAR_RARF_RC5_V1_8814B(x) ((x) & (~BITS_RARF_RC5_V1_8814B)) +#define BIT_GET_RARF_RC5_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_V1_8814B) & BIT_MASK_RARF_RC5_V1_8814B) +#define BIT_SET_RARF_RC5_V1_8814B(x, v) \ + (BIT_CLEAR_RARF_RC5_V1_8814B(x) | BIT_RARF_RC5_V1_8814B(v)) +/* 2 REG_RRSR_8814B */ -#define BIT_SHIFT_BEQ_DESC_NUM_8814B 0 -#define BIT_MASK_BEQ_DESC_NUM_8814B 0xfff -#define BIT_BEQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8814B) << BIT_SHIFT_BEQ_DESC_NUM_8814B) -#define BIT_GET_BEQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8814B) & BIT_MASK_BEQ_DESC_NUM_8814B) +#define BIT_SHIFT_RRSR_RSC_8814B 21 +#define BIT_MASK_RRSR_RSC_8814B 0x3 +#define BIT_RRSR_RSC_8814B(x) \ + (((x) & BIT_MASK_RRSR_RSC_8814B) << BIT_SHIFT_RRSR_RSC_8814B) +#define BITS_RRSR_RSC_8814B \ + (BIT_MASK_RRSR_RSC_8814B << BIT_SHIFT_RRSR_RSC_8814B) +#define BIT_CLEAR_RRSR_RSC_8814B(x) ((x) & (~BITS_RRSR_RSC_8814B)) +#define BIT_GET_RRSR_RSC_8814B(x) \ + (((x) >> BIT_SHIFT_RRSR_RSC_8814B) & BIT_MASK_RRSR_RSC_8814B) +#define BIT_SET_RRSR_RSC_8814B(x, v) \ + (BIT_CLEAR_RRSR_RSC_8814B(x) | BIT_RRSR_RSC_8814B(v)) +#define BIT_SHIFT_RRSC_BITMAP_8814B 0 +#define BIT_MASK_RRSC_BITMAP_8814B 0xfffff +#define BIT_RRSC_BITMAP_8814B(x) \ + (((x) & BIT_MASK_RRSC_BITMAP_8814B) << BIT_SHIFT_RRSC_BITMAP_8814B) +#define BITS_RRSC_BITMAP_8814B \ + (BIT_MASK_RRSC_BITMAP_8814B << BIT_SHIFT_RRSC_BITMAP_8814B) +#define BIT_CLEAR_RRSC_BITMAP_8814B(x) ((x) & (~BITS_RRSC_BITMAP_8814B)) +#define BIT_GET_RRSC_BITMAP_8814B(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP_8814B) & BIT_MASK_RRSC_BITMAP_8814B) +#define BIT_SET_RRSC_BITMAP_8814B(x, v) \ + (BIT_CLEAR_RRSC_BITMAP_8814B(x) | BIT_RRSC_BITMAP_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BKQ_TXBD_NUM_8814B */ -#define BIT_PCIE_BKQ_FLAG_8814B BIT(14) +/* 2 REG_ARFR0_8814B */ -#define BIT_SHIFT_BKQ_DESC_MODE_8814B 12 -#define BIT_MASK_BKQ_DESC_MODE_8814B 0x3 -#define BIT_BKQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8814B) << BIT_SHIFT_BKQ_DESC_MODE_8814B) -#define BIT_GET_BKQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8814B) & BIT_MASK_BKQ_DESC_MODE_8814B) +#define BIT_SHIFT_ARFRL0_8814B 0 +#define BIT_MASK_ARFRL0_8814B 0xffffffffL +#define BIT_ARFRL0_8814B(x) \ + (((x) & BIT_MASK_ARFRL0_8814B) << BIT_SHIFT_ARFRL0_8814B) +#define BITS_ARFRL0_8814B (BIT_MASK_ARFRL0_8814B << BIT_SHIFT_ARFRL0_8814B) +#define BIT_CLEAR_ARFRL0_8814B(x) ((x) & (~BITS_ARFRL0_8814B)) +#define BIT_GET_ARFRL0_8814B(x) \ + (((x) >> BIT_SHIFT_ARFRL0_8814B) & BIT_MASK_ARFRL0_8814B) +#define BIT_SET_ARFRL0_8814B(x, v) \ + (BIT_CLEAR_ARFRL0_8814B(x) | BIT_ARFRL0_8814B(v)) + +/* 2 REG_ARFRH0_8814B */ + +#define BIT_SHIFT_ARFRH0_8814B 0 +#define BIT_MASK_ARFRH0_8814B 0xffffffffL +#define BIT_ARFRH0_8814B(x) \ + (((x) & BIT_MASK_ARFRH0_8814B) << BIT_SHIFT_ARFRH0_8814B) +#define BITS_ARFRH0_8814B (BIT_MASK_ARFRH0_8814B << BIT_SHIFT_ARFRH0_8814B) +#define BIT_CLEAR_ARFRH0_8814B(x) ((x) & (~BITS_ARFRH0_8814B)) +#define BIT_GET_ARFRH0_8814B(x) \ + (((x) >> BIT_SHIFT_ARFRH0_8814B) & BIT_MASK_ARFRH0_8814B) +#define BIT_SET_ARFRH0_8814B(x, v) \ + (BIT_CLEAR_ARFRH0_8814B(x) | BIT_ARFRH0_8814B(v)) + +/* 2 REG_REG_ARFR_WT0_8814B */ + +#define BIT_SHIFT_RATE7_WEIGHTING_8814B 28 +#define BIT_MASK_RATE7_WEIGHTING_8814B 0xf +#define BIT_RATE7_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE7_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE7_WEIGHTING_8814B) +#define BITS_RATE7_WEIGHTING_8814B \ + (BIT_MASK_RATE7_WEIGHTING_8814B << BIT_SHIFT_RATE7_WEIGHTING_8814B) +#define BIT_CLEAR_RATE7_WEIGHTING_8814B(x) ((x) & (~BITS_RATE7_WEIGHTING_8814B)) +#define BIT_GET_RATE7_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE7_WEIGHTING_8814B) & \ + BIT_MASK_RATE7_WEIGHTING_8814B) +#define BIT_SET_RATE7_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE7_WEIGHTING_8814B(x) | BIT_RATE7_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE6_WEIGHTING_8814B 24 +#define BIT_MASK_RATE6_WEIGHTING_8814B 0xf +#define BIT_RATE6_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE6_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE6_WEIGHTING_8814B) +#define BITS_RATE6_WEIGHTING_8814B \ + (BIT_MASK_RATE6_WEIGHTING_8814B << BIT_SHIFT_RATE6_WEIGHTING_8814B) +#define BIT_CLEAR_RATE6_WEIGHTING_8814B(x) ((x) & (~BITS_RATE6_WEIGHTING_8814B)) +#define BIT_GET_RATE6_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE6_WEIGHTING_8814B) & \ + BIT_MASK_RATE6_WEIGHTING_8814B) +#define BIT_SET_RATE6_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE6_WEIGHTING_8814B(x) | BIT_RATE6_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE5_WEIGHTING_8814B 20 +#define BIT_MASK_RATE5_WEIGHTING_8814B 0xf +#define BIT_RATE5_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE5_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE5_WEIGHTING_8814B) +#define BITS_RATE5_WEIGHTING_8814B \ + (BIT_MASK_RATE5_WEIGHTING_8814B << BIT_SHIFT_RATE5_WEIGHTING_8814B) +#define BIT_CLEAR_RATE5_WEIGHTING_8814B(x) ((x) & (~BITS_RATE5_WEIGHTING_8814B)) +#define BIT_GET_RATE5_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE5_WEIGHTING_8814B) & \ + BIT_MASK_RATE5_WEIGHTING_8814B) +#define BIT_SET_RATE5_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE5_WEIGHTING_8814B(x) | BIT_RATE5_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE4_WEIGHTING_8814B 16 +#define BIT_MASK_RATE4_WEIGHTING_8814B 0xf +#define BIT_RATE4_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE4_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE4_WEIGHTING_8814B) +#define BITS_RATE4_WEIGHTING_8814B \ + (BIT_MASK_RATE4_WEIGHTING_8814B << BIT_SHIFT_RATE4_WEIGHTING_8814B) +#define BIT_CLEAR_RATE4_WEIGHTING_8814B(x) ((x) & (~BITS_RATE4_WEIGHTING_8814B)) +#define BIT_GET_RATE4_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE4_WEIGHTING_8814B) & \ + BIT_MASK_RATE4_WEIGHTING_8814B) +#define BIT_SET_RATE4_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE4_WEIGHTING_8814B(x) | BIT_RATE4_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE3_WEIGHTING_8814B 12 +#define BIT_MASK_RATE3_WEIGHTING_8814B 0xf +#define BIT_RATE3_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE3_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE3_WEIGHTING_8814B) +#define BITS_RATE3_WEIGHTING_8814B \ + (BIT_MASK_RATE3_WEIGHTING_8814B << BIT_SHIFT_RATE3_WEIGHTING_8814B) +#define BIT_CLEAR_RATE3_WEIGHTING_8814B(x) ((x) & (~BITS_RATE3_WEIGHTING_8814B)) +#define BIT_GET_RATE3_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE3_WEIGHTING_8814B) & \ + BIT_MASK_RATE3_WEIGHTING_8814B) +#define BIT_SET_RATE3_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE3_WEIGHTING_8814B(x) | BIT_RATE3_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE2_WEIGHTING_8814B 8 +#define BIT_MASK_RATE2_WEIGHTING_8814B 0xf +#define BIT_RATE2_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE2_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE2_WEIGHTING_8814B) +#define BITS_RATE2_WEIGHTING_8814B \ + (BIT_MASK_RATE2_WEIGHTING_8814B << BIT_SHIFT_RATE2_WEIGHTING_8814B) +#define BIT_CLEAR_RATE2_WEIGHTING_8814B(x) ((x) & (~BITS_RATE2_WEIGHTING_8814B)) +#define BIT_GET_RATE2_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE2_WEIGHTING_8814B) & \ + BIT_MASK_RATE2_WEIGHTING_8814B) +#define BIT_SET_RATE2_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE2_WEIGHTING_8814B(x) | BIT_RATE2_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE1_WEIGHTING_8814B 4 +#define BIT_MASK_RATE1_WEIGHTING_8814B 0xf +#define BIT_RATE1_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE1_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE1_WEIGHTING_8814B) +#define BITS_RATE1_WEIGHTING_8814B \ + (BIT_MASK_RATE1_WEIGHTING_8814B << BIT_SHIFT_RATE1_WEIGHTING_8814B) +#define BIT_CLEAR_RATE1_WEIGHTING_8814B(x) ((x) & (~BITS_RATE1_WEIGHTING_8814B)) +#define BIT_GET_RATE1_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE1_WEIGHTING_8814B) & \ + BIT_MASK_RATE1_WEIGHTING_8814B) +#define BIT_SET_RATE1_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE1_WEIGHTING_8814B(x) | BIT_RATE1_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE0_WEIGHTING_8814B 0 +#define BIT_MASK_RATE0_WEIGHTING_8814B 0xf +#define BIT_RATE0_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE0_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE0_WEIGHTING_8814B) +#define BITS_RATE0_WEIGHTING_8814B \ + (BIT_MASK_RATE0_WEIGHTING_8814B << BIT_SHIFT_RATE0_WEIGHTING_8814B) +#define BIT_CLEAR_RATE0_WEIGHTING_8814B(x) ((x) & (~BITS_RATE0_WEIGHTING_8814B)) +#define BIT_GET_RATE0_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE0_WEIGHTING_8814B) & \ + BIT_MASK_RATE0_WEIGHTING_8814B) +#define BIT_SET_RATE0_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE0_WEIGHTING_8814B(x) | BIT_RATE0_WEIGHTING_8814B(v)) + +/* 2 REG_REG_ARFR_WT1_8814B */ + +#define BIT_SHIFT_RATE15_WEIGHTING_8814B 28 +#define BIT_MASK_RATE15_WEIGHTING_8814B 0xf +#define BIT_RATE15_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE15_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE15_WEIGHTING_8814B) +#define BITS_RATE15_WEIGHTING_8814B \ + (BIT_MASK_RATE15_WEIGHTING_8814B << BIT_SHIFT_RATE15_WEIGHTING_8814B) +#define BIT_CLEAR_RATE15_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE15_WEIGHTING_8814B)) +#define BIT_GET_RATE15_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE15_WEIGHTING_8814B) & \ + BIT_MASK_RATE15_WEIGHTING_8814B) +#define BIT_SET_RATE15_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE15_WEIGHTING_8814B(x) | BIT_RATE15_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE14_WEIGHTING_8814B 24 +#define BIT_MASK_RATE14_WEIGHTING_8814B 0xf +#define BIT_RATE14_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE14_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE14_WEIGHTING_8814B) +#define BITS_RATE14_WEIGHTING_8814B \ + (BIT_MASK_RATE14_WEIGHTING_8814B << BIT_SHIFT_RATE14_WEIGHTING_8814B) +#define BIT_CLEAR_RATE14_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE14_WEIGHTING_8814B)) +#define BIT_GET_RATE14_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE14_WEIGHTING_8814B) & \ + BIT_MASK_RATE14_WEIGHTING_8814B) +#define BIT_SET_RATE14_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE14_WEIGHTING_8814B(x) | BIT_RATE14_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE13_WEIGHTING_8814B 20 +#define BIT_MASK_RATE13_WEIGHTING_8814B 0xf +#define BIT_RATE13_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE13_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE13_WEIGHTING_8814B) +#define BITS_RATE13_WEIGHTING_8814B \ + (BIT_MASK_RATE13_WEIGHTING_8814B << BIT_SHIFT_RATE13_WEIGHTING_8814B) +#define BIT_CLEAR_RATE13_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE13_WEIGHTING_8814B)) +#define BIT_GET_RATE13_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE13_WEIGHTING_8814B) & \ + BIT_MASK_RATE13_WEIGHTING_8814B) +#define BIT_SET_RATE13_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE13_WEIGHTING_8814B(x) | BIT_RATE13_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE12_WEIGHTING_8814B 16 +#define BIT_MASK_RATE12_WEIGHTING_8814B 0xf +#define BIT_RATE12_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE12_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE12_WEIGHTING_8814B) +#define BITS_RATE12_WEIGHTING_8814B \ + (BIT_MASK_RATE12_WEIGHTING_8814B << BIT_SHIFT_RATE12_WEIGHTING_8814B) +#define BIT_CLEAR_RATE12_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE12_WEIGHTING_8814B)) +#define BIT_GET_RATE12_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE12_WEIGHTING_8814B) & \ + BIT_MASK_RATE12_WEIGHTING_8814B) +#define BIT_SET_RATE12_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE12_WEIGHTING_8814B(x) | BIT_RATE12_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE11_WEIGHTING_8814B 12 +#define BIT_MASK_RATE11_WEIGHTING_8814B 0xf +#define BIT_RATE11_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE11_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE11_WEIGHTING_8814B) +#define BITS_RATE11_WEIGHTING_8814B \ + (BIT_MASK_RATE11_WEIGHTING_8814B << BIT_SHIFT_RATE11_WEIGHTING_8814B) +#define BIT_CLEAR_RATE11_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE11_WEIGHTING_8814B)) +#define BIT_GET_RATE11_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE11_WEIGHTING_8814B) & \ + BIT_MASK_RATE11_WEIGHTING_8814B) +#define BIT_SET_RATE11_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE11_WEIGHTING_8814B(x) | BIT_RATE11_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE10_WEIGHTING_8814B 8 +#define BIT_MASK_RATE10_WEIGHTING_8814B 0xf +#define BIT_RATE10_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE10_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE10_WEIGHTING_8814B) +#define BITS_RATE10_WEIGHTING_8814B \ + (BIT_MASK_RATE10_WEIGHTING_8814B << BIT_SHIFT_RATE10_WEIGHTING_8814B) +#define BIT_CLEAR_RATE10_WEIGHTING_8814B(x) \ + ((x) & (~BITS_RATE10_WEIGHTING_8814B)) +#define BIT_GET_RATE10_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE10_WEIGHTING_8814B) & \ + BIT_MASK_RATE10_WEIGHTING_8814B) +#define BIT_SET_RATE10_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE10_WEIGHTING_8814B(x) | BIT_RATE10_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE9_WEIGHTING_8814B 4 +#define BIT_MASK_RATE9_WEIGHTING_8814B 0xf +#define BIT_RATE9_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE9_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE9_WEIGHTING_8814B) +#define BITS_RATE9_WEIGHTING_8814B \ + (BIT_MASK_RATE9_WEIGHTING_8814B << BIT_SHIFT_RATE9_WEIGHTING_8814B) +#define BIT_CLEAR_RATE9_WEIGHTING_8814B(x) ((x) & (~BITS_RATE9_WEIGHTING_8814B)) +#define BIT_GET_RATE9_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE9_WEIGHTING_8814B) & \ + BIT_MASK_RATE9_WEIGHTING_8814B) +#define BIT_SET_RATE9_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE9_WEIGHTING_8814B(x) | BIT_RATE9_WEIGHTING_8814B(v)) + +#define BIT_SHIFT_RATE8_WEIGHTING_8814B 0 +#define BIT_MASK_RATE8_WEIGHTING_8814B 0xf +#define BIT_RATE8_WEIGHTING_8814B(x) \ + (((x) & BIT_MASK_RATE8_WEIGHTING_8814B) \ + << BIT_SHIFT_RATE8_WEIGHTING_8814B) +#define BITS_RATE8_WEIGHTING_8814B \ + (BIT_MASK_RATE8_WEIGHTING_8814B << BIT_SHIFT_RATE8_WEIGHTING_8814B) +#define BIT_CLEAR_RATE8_WEIGHTING_8814B(x) ((x) & (~BITS_RATE8_WEIGHTING_8814B)) +#define BIT_GET_RATE8_WEIGHTING_8814B(x) \ + (((x) >> BIT_SHIFT_RATE8_WEIGHTING_8814B) & \ + BIT_MASK_RATE8_WEIGHTING_8814B) +#define BIT_SET_RATE8_WEIGHTING_8814B(x, v) \ + (BIT_CLEAR_RATE8_WEIGHTING_8814B(x) | BIT_RATE8_WEIGHTING_8814B(v)) +/* 2 REG_CCK_CHECK_8814B */ +#define BIT_CHECK_CCK_EN_8814B BIT(7) +#define BIT_EN_BCN_PKT_REL_P0_8814B BIT(6) +#define BIT_BCN_PORT_SEL_8814B BIT(5) +#define BIT_MOREDATA_BYPASS_8814B BIT(4) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P0_8814B BIT(3) +#define BIT_EN_SET_MOREDATA_8814B BIT(2) +#define BIT__R_DIS_CLEAR_MACID_RELEASE_8814B BIT(1) +#define BIT__R_MACID_RELEASE_EN_8814B BIT(0) +/* 2 REG_AMPDU_MAX_TIME_V1_8814B */ -#define BIT_SHIFT_BKQ_DESC_NUM_8814B 0 -#define BIT_MASK_BKQ_DESC_NUM_8814B 0xfff -#define BIT_BKQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8814B) << BIT_SHIFT_BKQ_DESC_NUM_8814B) -#define BIT_GET_BKQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8814B) & BIT_MASK_BKQ_DESC_NUM_8814B) +#define BIT_SHIFT_AMPDU_MAX_TIME_8814B 0 +#define BIT_MASK_AMPDU_MAX_TIME_8814B 0xff +#define BIT_AMPDU_MAX_TIME_8814B(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME_8814B) \ + << BIT_SHIFT_AMPDU_MAX_TIME_8814B) +#define BITS_AMPDU_MAX_TIME_8814B \ + (BIT_MASK_AMPDU_MAX_TIME_8814B << BIT_SHIFT_AMPDU_MAX_TIME_8814B) +#define BIT_CLEAR_AMPDU_MAX_TIME_8814B(x) ((x) & (~BITS_AMPDU_MAX_TIME_8814B)) +#define BIT_GET_AMPDU_MAX_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8814B) & \ + BIT_MASK_AMPDU_MAX_TIME_8814B) +#define BIT_SET_AMPDU_MAX_TIME_8814B(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME_8814B(x) | BIT_AMPDU_MAX_TIME_8814B(v)) + +/* 2 REG_TAB_SEL_8814B */ + +#define BIT_SHIFT_RATE_SEL_8814B 0 +#define BIT_MASK_RATE_SEL_8814B 0xf +#define BIT_RATE_SEL_8814B(x) \ + (((x) & BIT_MASK_RATE_SEL_8814B) << BIT_SHIFT_RATE_SEL_8814B) +#define BITS_RATE_SEL_8814B \ + (BIT_MASK_RATE_SEL_8814B << BIT_SHIFT_RATE_SEL_8814B) +#define BIT_CLEAR_RATE_SEL_8814B(x) ((x) & (~BITS_RATE_SEL_8814B)) +#define BIT_GET_RATE_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_RATE_SEL_8814B) & BIT_MASK_RATE_SEL_8814B) +#define BIT_SET_RATE_SEL_8814B(x, v) \ + (BIT_CLEAR_RATE_SEL_8814B(x) | BIT_RATE_SEL_8814B(v)) + +/* 2 REG_BCN_INVALID_CTRL_8814B */ +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P4_8814B BIT(7) +#define BIT_EN_BCN_PKT_REL_P4_8814B BIT(6) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P3_8814B BIT(5) +#define BIT_EN_BCN_PKT_REL_P3_8814B BIT(4) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P2_8814B BIT(3) +#define BIT_EN_BCN_PKT_REL_P2_8814B BIT(2) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_P1_8814B BIT(1) +#define BIT_EN_BCN_PKT_REL_P1_8814B BIT(0) + +/* 2 REG_AMPDU_MAX_LENGTH_HT_8814B */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B 0xffff +#define BIT_AMPDU_MAX_LENGTH_HT_8814B(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B) +#define BITS_AMPDU_MAX_LENGTH_HT_8814B \ + (BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8814B(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_HT_8814B)) +#define BIT_GET_AMPDU_MAX_LENGTH_HT_8814B(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B) & \ + BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B) +#define BIT_SET_AMPDU_MAX_LENGTH_HT_8814B(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8814B(x) | \ + BIT_AMPDU_MAX_LENGTH_HT_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NDPA_RATE_8814B */ -/* 2 REG_HI0Q_TXBD_NUM_8814B */ -#define BIT_HI0Q_FLAG_8814B BIT(14) +#define BIT_SHIFT_R_NDPA_RATE_V1_8814B 0 +#define BIT_MASK_R_NDPA_RATE_V1_8814B 0xff +#define BIT_R_NDPA_RATE_V1_8814B(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1_8814B) \ + << BIT_SHIFT_R_NDPA_RATE_V1_8814B) +#define BITS_R_NDPA_RATE_V1_8814B \ + (BIT_MASK_R_NDPA_RATE_V1_8814B << BIT_SHIFT_R_NDPA_RATE_V1_8814B) +#define BIT_CLEAR_R_NDPA_RATE_V1_8814B(x) ((x) & (~BITS_R_NDPA_RATE_V1_8814B)) +#define BIT_GET_R_NDPA_RATE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8814B) & \ + BIT_MASK_R_NDPA_RATE_V1_8814B) +#define BIT_SET_R_NDPA_RATE_V1_8814B(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1_8814B(x) | BIT_R_NDPA_RATE_V1_8814B(v)) -#define BIT_SHIFT_HI0Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI0Q_DESC_MODE_8814B 0x3 -#define BIT_HI0Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8814B) << BIT_SHIFT_HI0Q_DESC_MODE_8814B) -#define BIT_GET_HI0Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8814B) & BIT_MASK_HI0Q_DESC_MODE_8814B) +/* 2 REG_TX_HANG_CTRL_8814B */ +#define BIT_EN_GNT_BT_AWAKE_8814B BIT(3) +#define BIT_EN_EOF_V1_8814B BIT(2) +#define BIT_DIS_OQT_BLOCK_8814B BIT(1) +#define BIT_SEARCH_QUEUE_EN_8814B BIT(0) +/* 2 REG_NDPA_OPT_CTRL_8814B */ +#define BIT_DIS_MACID_RELEASE_RTY_8814B BIT(5) +#define BIT_SHIFT_BW_SIGTA_8814B 3 +#define BIT_MASK_BW_SIGTA_8814B 0x3 +#define BIT_BW_SIGTA_8814B(x) \ + (((x) & BIT_MASK_BW_SIGTA_8814B) << BIT_SHIFT_BW_SIGTA_8814B) +#define BITS_BW_SIGTA_8814B \ + (BIT_MASK_BW_SIGTA_8814B << BIT_SHIFT_BW_SIGTA_8814B) +#define BIT_CLEAR_BW_SIGTA_8814B(x) ((x) & (~BITS_BW_SIGTA_8814B)) +#define BIT_GET_BW_SIGTA_8814B(x) \ + (((x) >> BIT_SHIFT_BW_SIGTA_8814B) & BIT_MASK_BW_SIGTA_8814B) +#define BIT_SET_BW_SIGTA_8814B(x, v) \ + (BIT_CLEAR_BW_SIGTA_8814B(x) | BIT_BW_SIGTA_8814B(v)) -#define BIT_SHIFT_HI0Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI0Q_DESC_NUM_8814B 0xfff -#define BIT_HI0Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8814B) << BIT_SHIFT_HI0Q_DESC_NUM_8814B) -#define BIT_GET_HI0Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8814B) & BIT_MASK_HI0Q_DESC_NUM_8814B) +#define BIT_EN_BAR_SIGTA_8814B BIT(2) +#define BIT_SHIFT_NDPA_BW_8814B 0 +#define BIT_MASK_NDPA_BW_8814B 0x3 +#define BIT_NDPA_BW_8814B(x) \ + (((x) & BIT_MASK_NDPA_BW_8814B) << BIT_SHIFT_NDPA_BW_8814B) +#define BITS_NDPA_BW_8814B (BIT_MASK_NDPA_BW_8814B << BIT_SHIFT_NDPA_BW_8814B) +#define BIT_CLEAR_NDPA_BW_8814B(x) ((x) & (~BITS_NDPA_BW_8814B)) +#define BIT_GET_NDPA_BW_8814B(x) \ + (((x) >> BIT_SHIFT_NDPA_BW_8814B) & BIT_MASK_NDPA_BW_8814B) +#define BIT_SET_NDPA_BW_8814B(x, v) \ + (BIT_CLEAR_NDPA_BW_8814B(x) | BIT_NDPA_BW_8814B(v)) + +/* 2 REG_AMPDU_MAX_LENGTH_VHT_8814B */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B 0x3ffff +#define BIT_AMPDU_MAX_LENGTH_VHT_8814B(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B) +#define BITS_AMPDU_MAX_LENGTH_VHT_8814B \ + (BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_8814B(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_8814B)) +#define BIT_GET_AMPDU_MAX_LENGTH_VHT_8814B(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B) & \ + BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B) +#define BIT_SET_AMPDU_MAX_LENGTH_VHT_8814B(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_8814B(x) | \ + BIT_AMPDU_MAX_LENGTH_VHT_8814B(v)) +/* 2 REG_RD_RESP_PKT_TH_8814B */ -/* 2 REG_HI1Q_TXBD_NUM_8814B */ -#define BIT_HI1Q_FLAG_8814B BIT(14) +#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B 0 +#define BIT_MASK_RD_RESP_PKT_TH_V1_8814B 0x3f +#define BIT_RD_RESP_PKT_TH_V1_8814B(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8814B) \ + << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) +#define BITS_RD_RESP_PKT_TH_V1_8814B \ + (BIT_MASK_RD_RESP_PKT_TH_V1_8814B << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8814B(x) \ + ((x) & (~BITS_RD_RESP_PKT_TH_V1_8814B)) +#define BIT_GET_RD_RESP_PKT_TH_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) & \ + BIT_MASK_RD_RESP_PKT_TH_V1_8814B) +#define BIT_SET_RD_RESP_PKT_TH_V1_8814B(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1_8814B(x) | BIT_RD_RESP_PKT_TH_V1_8814B(v)) + +/* 2 REG_NEW_EDCA_CTRL_V1_8814B */ + +#define BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B 9 +#define BIT_MASK_RANDOM_VALUE_SHIFT_8814B 0x7 +#define BIT_RANDOM_VALUE_SHIFT_8814B(x) \ + (((x) & BIT_MASK_RANDOM_VALUE_SHIFT_8814B) \ + << BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B) +#define BITS_RANDOM_VALUE_SHIFT_8814B \ + (BIT_MASK_RANDOM_VALUE_SHIFT_8814B \ + << BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B) +#define BIT_CLEAR_RANDOM_VALUE_SHIFT_8814B(x) \ + ((x) & (~BITS_RANDOM_VALUE_SHIFT_8814B)) +#define BIT_GET_RANDOM_VALUE_SHIFT_8814B(x) \ + (((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B) & \ + BIT_MASK_RANDOM_VALUE_SHIFT_8814B) +#define BIT_SET_RANDOM_VALUE_SHIFT_8814B(x, v) \ + (BIT_CLEAR_RANDOM_VALUE_SHIFT_8814B(x) | \ + BIT_RANDOM_VALUE_SHIFT_8814B(v)) + +#define BIT_ENABLE_NEW_EDCA_8814B BIT(8) + +#define BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B 0 +#define BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B 0xff +#define BIT_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) \ + (((x) & BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B) \ + << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B) +#define BITS_MEDIUM_HAS_IDKE_TRIGGER_8814B \ + (BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B \ + << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B) +#define BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) \ + ((x) & (~BITS_MEDIUM_HAS_IDKE_TRIGGER_8814B)) +#define BIT_GET_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) \ + (((x) >> BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B) & \ + BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B) +#define BIT_SET_MEDIUM_HAS_IDKE_TRIGGER_8814B(x, v) \ + (BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) | \ + BIT_MEDIUM_HAS_IDKE_TRIGGER_8814B(v)) + +/* 2 REG_ACQ_STOP_V2_8814B */ +#define BIT_AC19Q_STOP_8814B BIT(19) +#define BIT_AC18Q_STOP_8814B BIT(18) +#define BIT_AC17Q_STOP_8814B BIT(17) +#define BIT_AC16Q_STOP_8814B BIT(16) +#define BIT_AC15Q_STOP_8814B BIT(15) +#define BIT_AC14Q_STOP_8814B BIT(14) +#define BIT_AC13Q_STOP_8814B BIT(13) +#define BIT_AC12Q_STOP_8814B BIT(12) +#define BIT_AC11Q_STOP_8814B BIT(11) +#define BIT_AC10Q_STOP_8814B BIT(10) +#define BIT_AC9Q_STOP_8814B BIT(9) +#define BIT_AC8Q_STOP_8814B BIT(8) +#define BIT_AC7Q_STOP_8814B BIT(7) +#define BIT_AC6Q_STOP_8814B BIT(6) +#define BIT_AC5Q_STOP_8814B BIT(5) +#define BIT_AC4Q_STOP_8814B BIT(4) +#define BIT_AC3Q_STOP_8814B BIT(3) +#define BIT_AC2Q_STOP_8814B BIT(2) +#define BIT_AC1Q_STOP_8814B BIT(1) +#define BIT_AC0Q_STOP_8814B BIT(0) -#define BIT_SHIFT_HI1Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI1Q_DESC_MODE_8814B 0x3 -#define BIT_HI1Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8814B) << BIT_SHIFT_HI1Q_DESC_MODE_8814B) -#define BIT_GET_HI1Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8814B) & BIT_MASK_HI1Q_DESC_MODE_8814B) +/* 2 REG_WMAC_LBK_BUF_HD_V1_8814B */ +#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B 0 +#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B 0xfff +#define BIT_WMAC_LBK_BUF_HEAD_V1_8814B(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) +#define BITS_WMAC_LBK_BUF_HEAD_V1_8814B \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8814B(x) \ + ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8814B)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8814B(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8814B(x) | \ + BIT_WMAC_LBK_BUF_HEAD_V1_8814B(v)) +/* 2 REG_MGQ_BDNY_V1_8814B */ -#define BIT_SHIFT_HI1Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI1Q_DESC_NUM_8814B 0xfff -#define BIT_HI1Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8814B) << BIT_SHIFT_HI1Q_DESC_NUM_8814B) -#define BIT_GET_HI1Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8814B) & BIT_MASK_HI1Q_DESC_NUM_8814B) +#define BIT_SHIFT_MGQ_PGBNDY_V1_8814B 0 +#define BIT_MASK_MGQ_PGBNDY_V1_8814B 0xfff +#define BIT_MGQ_PGBNDY_V1_8814B(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1_8814B) << BIT_SHIFT_MGQ_PGBNDY_V1_8814B) +#define BITS_MGQ_PGBNDY_V1_8814B \ + (BIT_MASK_MGQ_PGBNDY_V1_8814B << BIT_SHIFT_MGQ_PGBNDY_V1_8814B) +#define BIT_CLEAR_MGQ_PGBNDY_V1_8814B(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8814B)) +#define BIT_GET_MGQ_PGBNDY_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8814B) & BIT_MASK_MGQ_PGBNDY_V1_8814B) +#define BIT_SET_MGQ_PGBNDY_V1_8814B(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1_8814B(x) | BIT_MGQ_PGBNDY_V1_8814B(v)) +/* 2 REG_TXRPT_CTRL_8814B */ +#define BIT_SHIFT_TRXRPT_TIMER_TH_8814B 24 +#define BIT_MASK_TRXRPT_TIMER_TH_8814B 0xff +#define BIT_TRXRPT_TIMER_TH_8814B(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH_8814B) \ + << BIT_SHIFT_TRXRPT_TIMER_TH_8814B) +#define BITS_TRXRPT_TIMER_TH_8814B \ + (BIT_MASK_TRXRPT_TIMER_TH_8814B << BIT_SHIFT_TRXRPT_TIMER_TH_8814B) +#define BIT_CLEAR_TRXRPT_TIMER_TH_8814B(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8814B)) +#define BIT_GET_TRXRPT_TIMER_TH_8814B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8814B) & \ + BIT_MASK_TRXRPT_TIMER_TH_8814B) +#define BIT_SET_TRXRPT_TIMER_TH_8814B(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH_8814B(x) | BIT_TRXRPT_TIMER_TH_8814B(v)) -/* 2 REG_HI2Q_TXBD_NUM_8814B */ -#define BIT_HI2Q_FLAG_8814B BIT(14) +#define BIT_SHIFT_TRXRPT_LEN_TH_8814B 16 +#define BIT_MASK_TRXRPT_LEN_TH_8814B 0xff +#define BIT_TRXRPT_LEN_TH_8814B(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH_8814B) << BIT_SHIFT_TRXRPT_LEN_TH_8814B) +#define BITS_TRXRPT_LEN_TH_8814B \ + (BIT_MASK_TRXRPT_LEN_TH_8814B << BIT_SHIFT_TRXRPT_LEN_TH_8814B) +#define BIT_CLEAR_TRXRPT_LEN_TH_8814B(x) ((x) & (~BITS_TRXRPT_LEN_TH_8814B)) +#define BIT_GET_TRXRPT_LEN_TH_8814B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8814B) & BIT_MASK_TRXRPT_LEN_TH_8814B) +#define BIT_SET_TRXRPT_LEN_TH_8814B(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH_8814B(x) | BIT_TRXRPT_LEN_TH_8814B(v)) -#define BIT_SHIFT_HI2Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI2Q_DESC_MODE_8814B 0x3 -#define BIT_HI2Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8814B) << BIT_SHIFT_HI2Q_DESC_MODE_8814B) -#define BIT_GET_HI2Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8814B) & BIT_MASK_HI2Q_DESC_MODE_8814B) +#define BIT_SHIFT_TRXRPT_READ_PTR_8814B 8 +#define BIT_MASK_TRXRPT_READ_PTR_8814B 0xff +#define BIT_TRXRPT_READ_PTR_8814B(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR_8814B) \ + << BIT_SHIFT_TRXRPT_READ_PTR_8814B) +#define BITS_TRXRPT_READ_PTR_8814B \ + (BIT_MASK_TRXRPT_READ_PTR_8814B << BIT_SHIFT_TRXRPT_READ_PTR_8814B) +#define BIT_CLEAR_TRXRPT_READ_PTR_8814B(x) ((x) & (~BITS_TRXRPT_READ_PTR_8814B)) +#define BIT_GET_TRXRPT_READ_PTR_8814B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8814B) & \ + BIT_MASK_TRXRPT_READ_PTR_8814B) +#define BIT_SET_TRXRPT_READ_PTR_8814B(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR_8814B(x) | BIT_TRXRPT_READ_PTR_8814B(v)) +#define BIT_SHIFT_TRXRPT_WRITE_PTR_8814B 0 +#define BIT_MASK_TRXRPT_WRITE_PTR_8814B 0xff +#define BIT_TRXRPT_WRITE_PTR_8814B(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8814B) \ + << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) +#define BITS_TRXRPT_WRITE_PTR_8814B \ + (BIT_MASK_TRXRPT_WRITE_PTR_8814B << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) +#define BIT_CLEAR_TRXRPT_WRITE_PTR_8814B(x) \ + ((x) & (~BITS_TRXRPT_WRITE_PTR_8814B)) +#define BIT_GET_TRXRPT_WRITE_PTR_8814B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) & \ + BIT_MASK_TRXRPT_WRITE_PTR_8814B) +#define BIT_SET_TRXRPT_WRITE_PTR_8814B(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR_8814B(x) | BIT_TRXRPT_WRITE_PTR_8814B(v)) +/* 2 REG_INIRTS_RATE_SEL_8814B */ +#define BIT_LEAG_RTS_BW_DUP_8814B BIT(5) -#define BIT_SHIFT_HI2Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI2Q_DESC_NUM_8814B 0xfff -#define BIT_HI2Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8814B) << BIT_SHIFT_HI2Q_DESC_NUM_8814B) -#define BIT_GET_HI2Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8814B) & BIT_MASK_HI2Q_DESC_NUM_8814B) +/* 2 REG_BASIC_CFEND_RATE_8814B */ +#define BIT_SHIFT_BASIC_CFEND_RATE_8814B 0 +#define BIT_MASK_BASIC_CFEND_RATE_8814B 0x1f +#define BIT_BASIC_CFEND_RATE_8814B(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE_8814B) \ + << BIT_SHIFT_BASIC_CFEND_RATE_8814B) +#define BITS_BASIC_CFEND_RATE_8814B \ + (BIT_MASK_BASIC_CFEND_RATE_8814B << BIT_SHIFT_BASIC_CFEND_RATE_8814B) +#define BIT_CLEAR_BASIC_CFEND_RATE_8814B(x) \ + ((x) & (~BITS_BASIC_CFEND_RATE_8814B)) +#define BIT_GET_BASIC_CFEND_RATE_8814B(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8814B) & \ + BIT_MASK_BASIC_CFEND_RATE_8814B) +#define BIT_SET_BASIC_CFEND_RATE_8814B(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE_8814B(x) | BIT_BASIC_CFEND_RATE_8814B(v)) +/* 2 REG_STBC_CFEND_RATE_8814B */ -/* 2 REG_HI3Q_TXBD_NUM_8814B */ -#define BIT_HI3Q_FLAG_8814B BIT(14) +#define BIT_SHIFT_STBC_CFEND_RATE_8814B 0 +#define BIT_MASK_STBC_CFEND_RATE_8814B 0x1f +#define BIT_STBC_CFEND_RATE_8814B(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE_8814B) \ + << BIT_SHIFT_STBC_CFEND_RATE_8814B) +#define BITS_STBC_CFEND_RATE_8814B \ + (BIT_MASK_STBC_CFEND_RATE_8814B << BIT_SHIFT_STBC_CFEND_RATE_8814B) +#define BIT_CLEAR_STBC_CFEND_RATE_8814B(x) ((x) & (~BITS_STBC_CFEND_RATE_8814B)) +#define BIT_GET_STBC_CFEND_RATE_8814B(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8814B) & \ + BIT_MASK_STBC_CFEND_RATE_8814B) +#define BIT_SET_STBC_CFEND_RATE_8814B(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE_8814B(x) | BIT_STBC_CFEND_RATE_8814B(v)) -#define BIT_SHIFT_HI3Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI3Q_DESC_MODE_8814B 0x3 -#define BIT_HI3Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8814B) << BIT_SHIFT_HI3Q_DESC_MODE_8814B) -#define BIT_GET_HI3Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8814B) & BIT_MASK_HI3Q_DESC_MODE_8814B) +/* 2 REG_DATA_SC_8814B */ +#define BIT_SHIFT_TXSC_40M_8814B 4 +#define BIT_MASK_TXSC_40M_8814B 0xf +#define BIT_TXSC_40M_8814B(x) \ + (((x) & BIT_MASK_TXSC_40M_8814B) << BIT_SHIFT_TXSC_40M_8814B) +#define BITS_TXSC_40M_8814B \ + (BIT_MASK_TXSC_40M_8814B << BIT_SHIFT_TXSC_40M_8814B) +#define BIT_CLEAR_TXSC_40M_8814B(x) ((x) & (~BITS_TXSC_40M_8814B)) +#define BIT_GET_TXSC_40M_8814B(x) \ + (((x) >> BIT_SHIFT_TXSC_40M_8814B) & BIT_MASK_TXSC_40M_8814B) +#define BIT_SET_TXSC_40M_8814B(x, v) \ + (BIT_CLEAR_TXSC_40M_8814B(x) | BIT_TXSC_40M_8814B(v)) +#define BIT_SHIFT_TXSC_20M_8814B 0 +#define BIT_MASK_TXSC_20M_8814B 0xf +#define BIT_TXSC_20M_8814B(x) \ + (((x) & BIT_MASK_TXSC_20M_8814B) << BIT_SHIFT_TXSC_20M_8814B) +#define BITS_TXSC_20M_8814B \ + (BIT_MASK_TXSC_20M_8814B << BIT_SHIFT_TXSC_20M_8814B) +#define BIT_CLEAR_TXSC_20M_8814B(x) ((x) & (~BITS_TXSC_20M_8814B)) +#define BIT_GET_TXSC_20M_8814B(x) \ + (((x) >> BIT_SHIFT_TXSC_20M_8814B) & BIT_MASK_TXSC_20M_8814B) +#define BIT_SET_TXSC_20M_8814B(x, v) \ + (BIT_CLEAR_TXSC_20M_8814B(x) | BIT_TXSC_20M_8814B(v)) + +/* 2 REG_MOREDATA_V1_8814B */ +#define BIT_MOREDATA_CTRL2_EN_V1_8814B BIT(3) +#define BIT_MOREDATA_CTRL1_EN_V1_8814B BIT(2) +#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8814B BIT(0) -#define BIT_SHIFT_HI3Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI3Q_DESC_NUM_8814B 0xfff -#define BIT_HI3Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8814B) << BIT_SHIFT_HI3Q_DESC_NUM_8814B) -#define BIT_GET_HI3Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8814B) & BIT_MASK_HI3Q_DESC_NUM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_DATA_SC1_8814B */ + +#define BIT_SHIFT_TXSC_160M_8814B 4 +#define BIT_MASK_TXSC_160M_8814B 0xf +#define BIT_TXSC_160M_8814B(x) \ + (((x) & BIT_MASK_TXSC_160M_8814B) << BIT_SHIFT_TXSC_160M_8814B) +#define BITS_TXSC_160M_8814B \ + (BIT_MASK_TXSC_160M_8814B << BIT_SHIFT_TXSC_160M_8814B) +#define BIT_CLEAR_TXSC_160M_8814B(x) ((x) & (~BITS_TXSC_160M_8814B)) +#define BIT_GET_TXSC_160M_8814B(x) \ + (((x) >> BIT_SHIFT_TXSC_160M_8814B) & BIT_MASK_TXSC_160M_8814B) +#define BIT_SET_TXSC_160M_8814B(x, v) \ + (BIT_CLEAR_TXSC_160M_8814B(x) | BIT_TXSC_160M_8814B(v)) + +#define BIT_SHIFT_TXSC_80M_8814B 0 +#define BIT_MASK_TXSC_80M_8814B 0xf +#define BIT_TXSC_80M_8814B(x) \ + (((x) & BIT_MASK_TXSC_80M_8814B) << BIT_SHIFT_TXSC_80M_8814B) +#define BITS_TXSC_80M_8814B \ + (BIT_MASK_TXSC_80M_8814B << BIT_SHIFT_TXSC_80M_8814B) +#define BIT_CLEAR_TXSC_80M_8814B(x) ((x) & (~BITS_TXSC_80M_8814B)) +#define BIT_GET_TXSC_80M_8814B(x) \ + (((x) >> BIT_SHIFT_TXSC_80M_8814B) & BIT_MASK_TXSC_80M_8814B) +#define BIT_SET_TXSC_80M_8814B(x, v) \ + (BIT_CLEAR_TXSC_80M_8814B(x) | BIT_TXSC_80M_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_HI4Q_TXBD_NUM_8814B */ -#define BIT_HI4Q_FLAG_8814B BIT(14) +/* 2 REG_TXRPT_START_OFFSET_8814B */ +#define BIT_RPTFIFO_RPTNUM_OPT_8814B BIT(31) + +#define BIT_SHIFT_MISSED_RPT_NUM_8814B 28 +#define BIT_MASK_MISSED_RPT_NUM_8814B 0x7 +#define BIT_MISSED_RPT_NUM_8814B(x) \ + (((x) & BIT_MASK_MISSED_RPT_NUM_8814B) \ + << BIT_SHIFT_MISSED_RPT_NUM_8814B) +#define BITS_MISSED_RPT_NUM_8814B \ + (BIT_MASK_MISSED_RPT_NUM_8814B << BIT_SHIFT_MISSED_RPT_NUM_8814B) +#define BIT_CLEAR_MISSED_RPT_NUM_8814B(x) ((x) & (~BITS_MISSED_RPT_NUM_8814B)) +#define BIT_GET_MISSED_RPT_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_MISSED_RPT_NUM_8814B) & \ + BIT_MASK_MISSED_RPT_NUM_8814B) +#define BIT_SET_MISSED_RPT_NUM_8814B(x, v) \ + (BIT_CLEAR_MISSED_RPT_NUM_8814B(x) | BIT_MISSED_RPT_NUM_8814B(v)) + +#define BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B 16 +#define BIT_MASK_MACID_CTRL_OFFSET_V1_8814B 0x1ff +#define BIT_MACID_CTRL_OFFSET_V1_8814B(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_V1_8814B) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B) +#define BITS_MACID_CTRL_OFFSET_V1_8814B \ + (BIT_MASK_MACID_CTRL_OFFSET_V1_8814B \ + << BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B) +#define BIT_CLEAR_MACID_CTRL_OFFSET_V1_8814B(x) \ + ((x) & (~BITS_MACID_CTRL_OFFSET_V1_8814B)) +#define BIT_GET_MACID_CTRL_OFFSET_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B) & \ + BIT_MASK_MACID_CTRL_OFFSET_V1_8814B) +#define BIT_SET_MACID_CTRL_OFFSET_V1_8814B(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_V1_8814B(x) | \ + BIT_MACID_CTRL_OFFSET_V1_8814B(v)) + +#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B 0 +#define BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B 0x1ff +#define BIT_AMPDU_TXRPT_OFFSET_V1_8814B(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B) +#define BITS_AMPDU_TXRPT_OFFSET_V1_8814B \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1_8814B(x) \ + ((x) & (~BITS_AMPDU_TXRPT_OFFSET_V1_8814B)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_V1_8814B(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B) +#define BIT_SET_AMPDU_TXRPT_OFFSET_V1_8814B(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1_8814B(x) | \ + BIT_AMPDU_TXRPT_OFFSET_V1_8814B(v)) -#define BIT_SHIFT_HI4Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI4Q_DESC_MODE_8814B 0x3 -#define BIT_HI4Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8814B) << BIT_SHIFT_HI4Q_DESC_MODE_8814B) -#define BIT_GET_HI4Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8814B) & BIT_MASK_HI4Q_DESC_MODE_8814B) - - - -#define BIT_SHIFT_HI4Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI4Q_DESC_NUM_8814B 0xfff -#define BIT_HI4Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8814B) << BIT_SHIFT_HI4Q_DESC_NUM_8814B) -#define BIT_GET_HI4Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8814B) & BIT_MASK_HI4Q_DESC_NUM_8814B) - - - -/* 2 REG_HI5Q_TXBD_NUM_8814B */ -#define BIT_HI5Q_FLAG_8814B BIT(14) - -#define BIT_SHIFT_HI5Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI5Q_DESC_MODE_8814B 0x3 -#define BIT_HI5Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8814B) << BIT_SHIFT_HI5Q_DESC_MODE_8814B) -#define BIT_GET_HI5Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8814B) & BIT_MASK_HI5Q_DESC_MODE_8814B) - - - -#define BIT_SHIFT_HI5Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI5Q_DESC_NUM_8814B 0xfff -#define BIT_HI5Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8814B) << BIT_SHIFT_HI5Q_DESC_NUM_8814B) -#define BIT_GET_HI5Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8814B) & BIT_MASK_HI5Q_DESC_NUM_8814B) - - - -/* 2 REG_HI6Q_TXBD_NUM_8814B */ -#define BIT_HI6Q_FLAG_8814B BIT(14) - -#define BIT_SHIFT_HI6Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI6Q_DESC_MODE_8814B 0x3 -#define BIT_HI6Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8814B) << BIT_SHIFT_HI6Q_DESC_MODE_8814B) -#define BIT_GET_HI6Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8814B) & BIT_MASK_HI6Q_DESC_MODE_8814B) - - - -#define BIT_SHIFT_HI6Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI6Q_DESC_NUM_8814B 0xfff -#define BIT_HI6Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8814B) << BIT_SHIFT_HI6Q_DESC_NUM_8814B) -#define BIT_GET_HI6Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8814B) & BIT_MASK_HI6Q_DESC_NUM_8814B) - - - -/* 2 REG_HI7Q_TXBD_NUM_8814B */ -#define BIT_HI7Q_FLAG_8814B BIT(14) - -#define BIT_SHIFT_HI7Q_DESC_MODE_8814B 12 -#define BIT_MASK_HI7Q_DESC_MODE_8814B 0x3 -#define BIT_HI7Q_DESC_MODE_8814B(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8814B) << BIT_SHIFT_HI7Q_DESC_MODE_8814B) -#define BIT_GET_HI7Q_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8814B) & BIT_MASK_HI7Q_DESC_MODE_8814B) - - - -#define BIT_SHIFT_HI7Q_DESC_NUM_8814B 0 -#define BIT_MASK_HI7Q_DESC_NUM_8814B 0xfff -#define BIT_HI7Q_DESC_NUM_8814B(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8814B) << BIT_SHIFT_HI7Q_DESC_NUM_8814B) -#define BIT_GET_HI7Q_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8814B) & BIT_MASK_HI7Q_DESC_NUM_8814B) - - - -/* 2 REG_TSFTIMER_HCI_8814B */ - -#define BIT_SHIFT_TSFT2_HCI_8814B 16 -#define BIT_MASK_TSFT2_HCI_8814B 0xffff -#define BIT_TSFT2_HCI_8814B(x) (((x) & BIT_MASK_TSFT2_HCI_8814B) << BIT_SHIFT_TSFT2_HCI_8814B) -#define BIT_GET_TSFT2_HCI_8814B(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8814B) & BIT_MASK_TSFT2_HCI_8814B) - - - -#define BIT_SHIFT_TSFT1_HCI_8814B 0 -#define BIT_MASK_TSFT1_HCI_8814B 0xffff -#define BIT_TSFT1_HCI_8814B(x) (((x) & BIT_MASK_TSFT1_HCI_8814B) << BIT_SHIFT_TSFT1_HCI_8814B) -#define BIT_GET_TSFT1_HCI_8814B(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8814B) & BIT_MASK_TSFT1_HCI_8814B) - - - -/* 2 REG_BD_RWPTR_CLR_8814B */ -#define BIT_CLR_HI7Q_HW_IDX_8814B BIT(29) -#define BIT_CLR_HI6Q_HW_IDX_8814B BIT(28) -#define BIT_CLR_HI5Q_HW_IDX_8814B BIT(27) -#define BIT_CLR_HI4Q_HW_IDX_8814B BIT(26) -#define BIT_CLR_HI3Q_HW_IDX_8814B BIT(25) -#define BIT_CLR_HI2Q_HW_IDX_8814B BIT(24) -#define BIT_CLR_HI1Q_HW_IDX_8814B BIT(23) -#define BIT_CLR_HI0Q_HW_IDX_8814B BIT(22) -#define BIT_CLR_BKQ_HW_IDX_8814B BIT(21) -#define BIT_CLR_BEQ_HW_IDX_8814B BIT(20) -#define BIT_CLR_VIQ_HW_IDX_8814B BIT(19) -#define BIT_CLR_VOQ_HW_IDX_8814B BIT(18) -#define BIT_CLR_MGQ_HW_IDX_8814B BIT(17) -#define BIT_CLR_RXQ_HW_IDX_8814B BIT(16) -#define BIT_CLR_HI7Q_HOST_IDX_8814B BIT(13) -#define BIT_CLR_HI6Q_HOST_IDX_8814B BIT(12) -#define BIT_CLR_HI5Q_HOST_IDX_8814B BIT(11) -#define BIT_CLR_HI4Q_HOST_IDX_8814B BIT(10) -#define BIT_CLR_HI3Q_HOST_IDX_8814B BIT(9) -#define BIT_CLR_HI2Q_HOST_IDX_8814B BIT(8) -#define BIT_CLR_HI1Q_HOST_IDX_8814B BIT(7) -#define BIT_CLR_HI0Q_HOST_IDX_8814B BIT(6) -#define BIT_CLR_BKQ_HOST_IDX_8814B BIT(5) -#define BIT_CLR_BEQ_HOST_IDX_8814B BIT(4) -#define BIT_CLR_VIQ_HOST_IDX_8814B BIT(3) -#define BIT_CLR_VOQ_HOST_IDX_8814B BIT(2) -#define BIT_CLR_MGQ_HOST_IDX_8814B BIT(1) -#define BIT_CLR_RXQ_HOST_IDX_8814B BIT(0) - -/* 2 REG_VOQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_VOQ_HW_IDX_8814B 16 -#define BIT_MASK_VOQ_HW_IDX_8814B 0xfff -#define BIT_VOQ_HW_IDX_8814B(x) (((x) & BIT_MASK_VOQ_HW_IDX_8814B) << BIT_SHIFT_VOQ_HW_IDX_8814B) -#define BIT_GET_VOQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8814B) & BIT_MASK_VOQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_VOQ_HOST_IDX_8814B 0 -#define BIT_MASK_VOQ_HOST_IDX_8814B 0xfff -#define BIT_VOQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8814B) << BIT_SHIFT_VOQ_HOST_IDX_8814B) -#define BIT_GET_VOQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8814B) & BIT_MASK_VOQ_HOST_IDX_8814B) - - - -/* 2 REG_VIQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_VIQ_HW_IDX_8814B 16 -#define BIT_MASK_VIQ_HW_IDX_8814B 0xfff -#define BIT_VIQ_HW_IDX_8814B(x) (((x) & BIT_MASK_VIQ_HW_IDX_8814B) << BIT_SHIFT_VIQ_HW_IDX_8814B) -#define BIT_GET_VIQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8814B) & BIT_MASK_VIQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_VIQ_HOST_IDX_8814B 0 -#define BIT_MASK_VIQ_HOST_IDX_8814B 0xfff -#define BIT_VIQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8814B) << BIT_SHIFT_VIQ_HOST_IDX_8814B) -#define BIT_GET_VIQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8814B) & BIT_MASK_VIQ_HOST_IDX_8814B) - - - -/* 2 REG_BEQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_BEQ_HW_IDX_8814B 16 -#define BIT_MASK_BEQ_HW_IDX_8814B 0xfff -#define BIT_BEQ_HW_IDX_8814B(x) (((x) & BIT_MASK_BEQ_HW_IDX_8814B) << BIT_SHIFT_BEQ_HW_IDX_8814B) -#define BIT_GET_BEQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8814B) & BIT_MASK_BEQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_BEQ_HOST_IDX_8814B 0 -#define BIT_MASK_BEQ_HOST_IDX_8814B 0xfff -#define BIT_BEQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8814B) << BIT_SHIFT_BEQ_HOST_IDX_8814B) -#define BIT_GET_BEQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8814B) & BIT_MASK_BEQ_HOST_IDX_8814B) - - - -/* 2 REG_BKQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_BKQ_HW_IDX_8814B 16 -#define BIT_MASK_BKQ_HW_IDX_8814B 0xfff -#define BIT_BKQ_HW_IDX_8814B(x) (((x) & BIT_MASK_BKQ_HW_IDX_8814B) << BIT_SHIFT_BKQ_HW_IDX_8814B) -#define BIT_GET_BKQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8814B) & BIT_MASK_BKQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_BKQ_HOST_IDX_8814B 0 -#define BIT_MASK_BKQ_HOST_IDX_8814B 0xfff -#define BIT_BKQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8814B) << BIT_SHIFT_BKQ_HOST_IDX_8814B) -#define BIT_GET_BKQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8814B) & BIT_MASK_BKQ_HOST_IDX_8814B) - - - -/* 2 REG_MGQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_MGQ_HW_IDX_8814B 16 -#define BIT_MASK_MGQ_HW_IDX_8814B 0xfff -#define BIT_MGQ_HW_IDX_8814B(x) (((x) & BIT_MASK_MGQ_HW_IDX_8814B) << BIT_SHIFT_MGQ_HW_IDX_8814B) -#define BIT_GET_MGQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8814B) & BIT_MASK_MGQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_MGQ_HOST_IDX_8814B 0 -#define BIT_MASK_MGQ_HOST_IDX_8814B 0xfff -#define BIT_MGQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8814B) << BIT_SHIFT_MGQ_HOST_IDX_8814B) -#define BIT_GET_MGQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8814B) & BIT_MASK_MGQ_HOST_IDX_8814B) - - - -/* 2 REG_RXQ_RXBD_IDX_8814B */ - -#define BIT_SHIFT_RXQ_HW_IDX_8814B 16 -#define BIT_MASK_RXQ_HW_IDX_8814B 0xfff -#define BIT_RXQ_HW_IDX_8814B(x) (((x) & BIT_MASK_RXQ_HW_IDX_8814B) << BIT_SHIFT_RXQ_HW_IDX_8814B) -#define BIT_GET_RXQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8814B) & BIT_MASK_RXQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_RXQ_HOST_IDX_8814B 0 -#define BIT_MASK_RXQ_HOST_IDX_8814B 0xfff -#define BIT_RXQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8814B) << BIT_SHIFT_RXQ_HOST_IDX_8814B) -#define BIT_GET_RXQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8814B) & BIT_MASK_RXQ_HOST_IDX_8814B) - - - -/* 2 REG_HI0Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI0Q_HW_IDX_8814B 16 -#define BIT_MASK_HI0Q_HW_IDX_8814B 0xfff -#define BIT_HI0Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8814B) << BIT_SHIFT_HI0Q_HW_IDX_8814B) -#define BIT_GET_HI0Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8814B) & BIT_MASK_HI0Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI0Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI0Q_HOST_IDX_8814B 0xfff -#define BIT_HI0Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8814B) << BIT_SHIFT_HI0Q_HOST_IDX_8814B) -#define BIT_GET_HI0Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8814B) & BIT_MASK_HI0Q_HOST_IDX_8814B) - - - -/* 2 REG_HI1Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI1Q_HW_IDX_8814B 16 -#define BIT_MASK_HI1Q_HW_IDX_8814B 0xfff -#define BIT_HI1Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8814B) << BIT_SHIFT_HI1Q_HW_IDX_8814B) -#define BIT_GET_HI1Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8814B) & BIT_MASK_HI1Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI1Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI1Q_HOST_IDX_8814B 0xfff -#define BIT_HI1Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8814B) << BIT_SHIFT_HI1Q_HOST_IDX_8814B) -#define BIT_GET_HI1Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8814B) & BIT_MASK_HI1Q_HOST_IDX_8814B) - - - -/* 2 REG_HI2Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI2Q_HW_IDX_8814B 16 -#define BIT_MASK_HI2Q_HW_IDX_8814B 0xfff -#define BIT_HI2Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8814B) << BIT_SHIFT_HI2Q_HW_IDX_8814B) -#define BIT_GET_HI2Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8814B) & BIT_MASK_HI2Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI2Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI2Q_HOST_IDX_8814B 0xfff -#define BIT_HI2Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8814B) << BIT_SHIFT_HI2Q_HOST_IDX_8814B) -#define BIT_GET_HI2Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8814B) & BIT_MASK_HI2Q_HOST_IDX_8814B) - - - -/* 2 REG_HI3Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI3Q_HW_IDX_8814B 16 -#define BIT_MASK_HI3Q_HW_IDX_8814B 0xfff -#define BIT_HI3Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8814B) << BIT_SHIFT_HI3Q_HW_IDX_8814B) -#define BIT_GET_HI3Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8814B) & BIT_MASK_HI3Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI3Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI3Q_HOST_IDX_8814B 0xfff -#define BIT_HI3Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8814B) << BIT_SHIFT_HI3Q_HOST_IDX_8814B) -#define BIT_GET_HI3Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8814B) & BIT_MASK_HI3Q_HOST_IDX_8814B) - - - -/* 2 REG_HI4Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI4Q_HW_IDX_8814B 16 -#define BIT_MASK_HI4Q_HW_IDX_8814B 0xfff -#define BIT_HI4Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8814B) << BIT_SHIFT_HI4Q_HW_IDX_8814B) -#define BIT_GET_HI4Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8814B) & BIT_MASK_HI4Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI4Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI4Q_HOST_IDX_8814B 0xfff -#define BIT_HI4Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8814B) << BIT_SHIFT_HI4Q_HOST_IDX_8814B) -#define BIT_GET_HI4Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8814B) & BIT_MASK_HI4Q_HOST_IDX_8814B) - - - -/* 2 REG_HI5Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI5Q_HW_IDX_8814B 16 -#define BIT_MASK_HI5Q_HW_IDX_8814B 0xfff -#define BIT_HI5Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8814B) << BIT_SHIFT_HI5Q_HW_IDX_8814B) -#define BIT_GET_HI5Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8814B) & BIT_MASK_HI5Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI5Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI5Q_HOST_IDX_8814B 0xfff -#define BIT_HI5Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8814B) << BIT_SHIFT_HI5Q_HOST_IDX_8814B) -#define BIT_GET_HI5Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8814B) & BIT_MASK_HI5Q_HOST_IDX_8814B) - - - -/* 2 REG_HI6Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI6Q_HW_IDX_8814B 16 -#define BIT_MASK_HI6Q_HW_IDX_8814B 0xfff -#define BIT_HI6Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8814B) << BIT_SHIFT_HI6Q_HW_IDX_8814B) -#define BIT_GET_HI6Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8814B) & BIT_MASK_HI6Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI6Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI6Q_HOST_IDX_8814B 0xfff -#define BIT_HI6Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8814B) << BIT_SHIFT_HI6Q_HOST_IDX_8814B) -#define BIT_GET_HI6Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8814B) & BIT_MASK_HI6Q_HOST_IDX_8814B) - - - -/* 2 REG_HI7Q_TXBD_IDX_8814B */ - -#define BIT_SHIFT_HI7Q_HW_IDX_8814B 16 -#define BIT_MASK_HI7Q_HW_IDX_8814B 0xfff -#define BIT_HI7Q_HW_IDX_8814B(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8814B) << BIT_SHIFT_HI7Q_HW_IDX_8814B) -#define BIT_GET_HI7Q_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8814B) & BIT_MASK_HI7Q_HW_IDX_8814B) - - - -#define BIT_SHIFT_HI7Q_HOST_IDX_8814B 0 -#define BIT_MASK_HI7Q_HOST_IDX_8814B 0xfff -#define BIT_HI7Q_HOST_IDX_8814B(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8814B) << BIT_SHIFT_HI7Q_HOST_IDX_8814B) -#define BIT_GET_HI7Q_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8814B) & BIT_MASK_HI7Q_HOST_IDX_8814B) - - - -/* 2 REG_DBG_SEL_V1_8814B */ - -#define BIT_SHIFT_DBG_SEL_8814B 0 -#define BIT_MASK_DBG_SEL_8814B 0xff -#define BIT_DBG_SEL_8814B(x) (((x) & BIT_MASK_DBG_SEL_8814B) << BIT_SHIFT_DBG_SEL_8814B) -#define BIT_GET_DBG_SEL_8814B(x) (((x) >> BIT_SHIFT_DBG_SEL_8814B) & BIT_MASK_DBG_SEL_8814B) - - - -/* 2 REG_PCIE_HRPWM1_V1_8814B */ - -#define BIT_SHIFT_PCIE_HRPWM_8814B 0 -#define BIT_MASK_PCIE_HRPWM_8814B 0xff -#define BIT_PCIE_HRPWM_8814B(x) (((x) & BIT_MASK_PCIE_HRPWM_8814B) << BIT_SHIFT_PCIE_HRPWM_8814B) -#define BIT_GET_PCIE_HRPWM_8814B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8814B) & BIT_MASK_PCIE_HRPWM_8814B) - - - -/* 2 REG_PCIE_HCPWM1_V1_8814B */ - -#define BIT_SHIFT_PCIE_HCPWM_8814B 0 -#define BIT_MASK_PCIE_HCPWM_8814B 0xff -#define BIT_PCIE_HCPWM_8814B(x) (((x) & BIT_MASK_PCIE_HCPWM_8814B) << BIT_SHIFT_PCIE_HCPWM_8814B) -#define BIT_GET_PCIE_HCPWM_8814B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8814B) & BIT_MASK_PCIE_HCPWM_8814B) - - - -/* 2 REG_PCIE_CTRL2_8814B */ -#define BIT_DIS_TXDMA_PRE_8814B BIT(7) -#define BIT_DIS_RXDMA_PRE_8814B BIT(6) - -#define BIT_SHIFT_HPS_CLKR_PCIE_8814B 4 -#define BIT_MASK_HPS_CLKR_PCIE_8814B 0x3 -#define BIT_HPS_CLKR_PCIE_8814B(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8814B) << BIT_SHIFT_HPS_CLKR_PCIE_8814B) -#define BIT_GET_HPS_CLKR_PCIE_8814B(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8814B) & BIT_MASK_HPS_CLKR_PCIE_8814B) - - -#define BIT_PCIE_INT_8814B BIT(3) -#define BIT_TXFLAG_EXIT_L1_EN_8814B BIT(2) -#define BIT_EN_RXDMA_ALIGN_8814B BIT(1) -#define BIT_EN_TXDMA_ALIGN_8814B BIT(0) - -/* 2 REG_PCIE_HRPWM2_V1_8814B */ - -#define BIT_SHIFT_PCIE_HRPWM2_8814B 0 -#define BIT_MASK_PCIE_HRPWM2_8814B 0xffff -#define BIT_PCIE_HRPWM2_8814B(x) (((x) & BIT_MASK_PCIE_HRPWM2_8814B) << BIT_SHIFT_PCIE_HRPWM2_8814B) -#define BIT_GET_PCIE_HRPWM2_8814B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8814B) & BIT_MASK_PCIE_HRPWM2_8814B) - - - -/* 2 REG_PCIE_HCPWM2_V1_8814B */ - -#define BIT_SHIFT_PCIE_HCPWM2_8814B 0 -#define BIT_MASK_PCIE_HCPWM2_8814B 0xffff -#define BIT_PCIE_HCPWM2_8814B(x) (((x) & BIT_MASK_PCIE_HCPWM2_8814B) << BIT_SHIFT_PCIE_HCPWM2_8814B) -#define BIT_GET_PCIE_HCPWM2_8814B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8814B) & BIT_MASK_PCIE_HCPWM2_8814B) - - - -/* 2 REG_PCIE_H2C_MSG_V1_8814B */ - -#define BIT_SHIFT_DRV2FW_INFO_8814B 0 -#define BIT_MASK_DRV2FW_INFO_8814B 0xffffffffL -#define BIT_DRV2FW_INFO_8814B(x) (((x) & BIT_MASK_DRV2FW_INFO_8814B) << BIT_SHIFT_DRV2FW_INFO_8814B) -#define BIT_GET_DRV2FW_INFO_8814B(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8814B) & BIT_MASK_DRV2FW_INFO_8814B) - - - -/* 2 REG_PCIE_C2H_MSG_V1_8814B */ - -#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B 0 -#define BIT_MASK_HCI_PCIE_C2H_MSG_8814B 0xffffffffL -#define BIT_HCI_PCIE_C2H_MSG_8814B(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8814B) << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) -#define BIT_GET_HCI_PCIE_C2H_MSG_8814B(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) & BIT_MASK_HCI_PCIE_C2H_MSG_8814B) - - - -/* 2 REG_DBI_WDATA_V1_8814B */ - -#define BIT_SHIFT_DBI_WDATA_8814B 0 -#define BIT_MASK_DBI_WDATA_8814B 0xffffffffL -#define BIT_DBI_WDATA_8814B(x) (((x) & BIT_MASK_DBI_WDATA_8814B) << BIT_SHIFT_DBI_WDATA_8814B) -#define BIT_GET_DBI_WDATA_8814B(x) (((x) >> BIT_SHIFT_DBI_WDATA_8814B) & BIT_MASK_DBI_WDATA_8814B) - - - -/* 2 REG_DBI_RDATA_V1_8814B */ - -#define BIT_SHIFT_DBI_RDATA_8814B 0 -#define BIT_MASK_DBI_RDATA_8814B 0xffffffffL -#define BIT_DBI_RDATA_8814B(x) (((x) & BIT_MASK_DBI_RDATA_8814B) << BIT_SHIFT_DBI_RDATA_8814B) -#define BIT_GET_DBI_RDATA_8814B(x) (((x) >> BIT_SHIFT_DBI_RDATA_8814B) & BIT_MASK_DBI_RDATA_8814B) - - - -/* 2 REG_DBI_FLAG_V1_8814B */ -#define BIT_EN_STUCK_DBG_8814B BIT(26) -#define BIT_RX_STUCK_8814B BIT(25) -#define BIT_TX_STUCK_8814B BIT(24) -#define BIT_DBI_RFLAG_8814B BIT(17) -#define BIT_DBI_WFLAG_8814B BIT(16) - -#define BIT_SHIFT_DBI_WREN_8814B 12 -#define BIT_MASK_DBI_WREN_8814B 0xf -#define BIT_DBI_WREN_8814B(x) (((x) & BIT_MASK_DBI_WREN_8814B) << BIT_SHIFT_DBI_WREN_8814B) -#define BIT_GET_DBI_WREN_8814B(x) (((x) >> BIT_SHIFT_DBI_WREN_8814B) & BIT_MASK_DBI_WREN_8814B) - - - -#define BIT_SHIFT_DBI_ADDR_8814B 0 -#define BIT_MASK_DBI_ADDR_8814B 0xfff -#define BIT_DBI_ADDR_8814B(x) (((x) & BIT_MASK_DBI_ADDR_8814B) << BIT_SHIFT_DBI_ADDR_8814B) -#define BIT_GET_DBI_ADDR_8814B(x) (((x) >> BIT_SHIFT_DBI_ADDR_8814B) & BIT_MASK_DBI_ADDR_8814B) - - - -/* 2 REG_MDIO_V1_8814B */ - -#define BIT_SHIFT_MDIO_RDATA_8814B 16 -#define BIT_MASK_MDIO_RDATA_8814B 0xffff -#define BIT_MDIO_RDATA_8814B(x) (((x) & BIT_MASK_MDIO_RDATA_8814B) << BIT_SHIFT_MDIO_RDATA_8814B) -#define BIT_GET_MDIO_RDATA_8814B(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8814B) & BIT_MASK_MDIO_RDATA_8814B) - - - -#define BIT_SHIFT_MDIO_WDATA_8814B 0 -#define BIT_MASK_MDIO_WDATA_8814B 0xffff -#define BIT_MDIO_WDATA_8814B(x) (((x) & BIT_MASK_MDIO_WDATA_8814B) << BIT_SHIFT_MDIO_WDATA_8814B) -#define BIT_GET_MDIO_WDATA_8814B(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8814B) & BIT_MASK_MDIO_WDATA_8814B) - - - -/* 2 REG_PCIE_MIX_CFG_8814B */ - -#define BIT_SHIFT_MDIO_PHY_ADDR_8814B 24 -#define BIT_MASK_MDIO_PHY_ADDR_8814B 0x1f -#define BIT_MDIO_PHY_ADDR_8814B(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8814B) << BIT_SHIFT_MDIO_PHY_ADDR_8814B) -#define BIT_GET_MDIO_PHY_ADDR_8814B(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8814B) & BIT_MASK_MDIO_PHY_ADDR_8814B) - - - -#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B 10 -#define BIT_MASK_WATCH_DOG_RECORD_V1_8814B 0x3fff -#define BIT_WATCH_DOG_RECORD_V1_8814B(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8814B) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) -#define BIT_GET_WATCH_DOG_RECORD_V1_8814B(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) & BIT_MASK_WATCH_DOG_RECORD_V1_8814B) - - -#define BIT_R_IO_TIMEOUT_FLAG_V1_8814B BIT(9) -#define BIT_EN_WATCH_DOG_8814B BIT(8) -#define BIT_ECRC_EN_V1_8814B BIT(7) -#define BIT_MDIO_RFLAG_V1_8814B BIT(6) -#define BIT_MDIO_WFLAG_V1_8814B BIT(5) - -#define BIT_SHIFT_MDIO_REG_ADDR_V1_8814B 0 -#define BIT_MASK_MDIO_REG_ADDR_V1_8814B 0x1f -#define BIT_MDIO_REG_ADDR_V1_8814B(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8814B) << BIT_SHIFT_MDIO_REG_ADDR_V1_8814B) -#define BIT_GET_MDIO_REG_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8814B) & BIT_MASK_MDIO_REG_ADDR_V1_8814B) - - - -/* 2 REG_HCI_MIX_CFG_8814B */ -#define BIT_HOST_GEN2_SUPPORT_8814B BIT(20) - -#define BIT_SHIFT_TXDMA_ERR_FLAG_8814B 16 -#define BIT_MASK_TXDMA_ERR_FLAG_8814B 0xf -#define BIT_TXDMA_ERR_FLAG_8814B(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8814B) << BIT_SHIFT_TXDMA_ERR_FLAG_8814B) -#define BIT_GET_TXDMA_ERR_FLAG_8814B(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8814B) & BIT_MASK_TXDMA_ERR_FLAG_8814B) - - - -#define BIT_SHIFT_EARLY_MODE_SEL_8814B 12 -#define BIT_MASK_EARLY_MODE_SEL_8814B 0xf -#define BIT_EARLY_MODE_SEL_8814B(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8814B) << BIT_SHIFT_EARLY_MODE_SEL_8814B) -#define BIT_GET_EARLY_MODE_SEL_8814B(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8814B) & BIT_MASK_EARLY_MODE_SEL_8814B) - - -#define BIT_EPHY_RX50_EN_8814B BIT(11) - -#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B 8 -#define BIT_MASK_MSI_TIMEOUT_ID_V1_8814B 0x7 -#define BIT_MSI_TIMEOUT_ID_V1_8814B(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8814B) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) -#define BIT_GET_MSI_TIMEOUT_ID_V1_8814B(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) & BIT_MASK_MSI_TIMEOUT_ID_V1_8814B) - - -#define BIT_RADDR_RD_8814B BIT(7) -#define BIT_EN_MUL_TAG_8814B BIT(6) -#define BIT_EN_EARLY_MODE_8814B BIT(5) -#define BIT_L0S_LINK_OFF_8814B BIT(4) -#define BIT_ACT_LINK_OFF_8814B BIT(3) -#define BIT_EN_SLOW_MAC_TX_8814B BIT(2) -#define BIT_EN_SLOW_MAC_RX_8814B BIT(1) - -/* 2 REG_STC_INT_CS_8814B(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */ -#define BIT_STC_INT_EN_8814B BIT(31) - -#define BIT_SHIFT_STC_INT_FLAG_8814B 16 -#define BIT_MASK_STC_INT_FLAG_8814B 0xff -#define BIT_STC_INT_FLAG_8814B(x) (((x) & BIT_MASK_STC_INT_FLAG_8814B) << BIT_SHIFT_STC_INT_FLAG_8814B) -#define BIT_GET_STC_INT_FLAG_8814B(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8814B) & BIT_MASK_STC_INT_FLAG_8814B) - - - -#define BIT_SHIFT_STC_INT_IDX_8814B 8 -#define BIT_MASK_STC_INT_IDX_8814B 0x7 -#define BIT_STC_INT_IDX_8814B(x) (((x) & BIT_MASK_STC_INT_IDX_8814B) << BIT_SHIFT_STC_INT_IDX_8814B) -#define BIT_GET_STC_INT_IDX_8814B(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8814B) & BIT_MASK_STC_INT_IDX_8814B) - - - -#define BIT_SHIFT_STC_INT_REALTIME_CS_8814B 0 -#define BIT_MASK_STC_INT_REALTIME_CS_8814B 0x3f -#define BIT_STC_INT_REALTIME_CS_8814B(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8814B) << BIT_SHIFT_STC_INT_REALTIME_CS_8814B) -#define BIT_GET_STC_INT_REALTIME_CS_8814B(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8814B) & BIT_MASK_STC_INT_REALTIME_CS_8814B) - - - -/* 2 REG_ST_INT_CFG_8814B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ -#define BIT_STC_INT_GRP_EN_8814B BIT(31) - -#define BIT_SHIFT_STC_INT_EXPECT_LS_8814B 8 -#define BIT_MASK_STC_INT_EXPECT_LS_8814B 0x3f -#define BIT_STC_INT_EXPECT_LS_8814B(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8814B) << BIT_SHIFT_STC_INT_EXPECT_LS_8814B) -#define BIT_GET_STC_INT_EXPECT_LS_8814B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8814B) & BIT_MASK_STC_INT_EXPECT_LS_8814B) - - - -#define BIT_SHIFT_STC_INT_EXPECT_CS_8814B 0 -#define BIT_MASK_STC_INT_EXPECT_CS_8814B 0x3f -#define BIT_STC_INT_EXPECT_CS_8814B(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8814B) << BIT_SHIFT_STC_INT_EXPECT_CS_8814B) -#define BIT_GET_STC_INT_EXPECT_CS_8814B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8814B) & BIT_MASK_STC_INT_EXPECT_CS_8814B) - - - -/* 2 REG_CMU_DLY_CTRL_8814B(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */ -#define BIT_CMU_DLY_EN_8814B BIT(31) -#define BIT_CMU_DLY_MODE_8814B BIT(30) - -#define BIT_SHIFT_CMU_DLY_PRE_DIV_8814B 0 -#define BIT_MASK_CMU_DLY_PRE_DIV_8814B 0xff -#define BIT_CMU_DLY_PRE_DIV_8814B(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8814B) << BIT_SHIFT_CMU_DLY_PRE_DIV_8814B) -#define BIT_GET_CMU_DLY_PRE_DIV_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8814B) & BIT_MASK_CMU_DLY_PRE_DIV_8814B) - - - -/* 2 REG_CMU_DLY_CFG_8814B(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ - -#define BIT_SHIFT_CMU_DLY_LTR_A2I_8814B 24 -#define BIT_MASK_CMU_DLY_LTR_A2I_8814B 0xff -#define BIT_CMU_DLY_LTR_A2I_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8814B) << BIT_SHIFT_CMU_DLY_LTR_A2I_8814B) -#define BIT_GET_CMU_DLY_LTR_A2I_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8814B) & BIT_MASK_CMU_DLY_LTR_A2I_8814B) - - - -#define BIT_SHIFT_CMU_DLY_LTR_I2A_8814B 16 -#define BIT_MASK_CMU_DLY_LTR_I2A_8814B 0xff -#define BIT_CMU_DLY_LTR_I2A_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8814B) << BIT_SHIFT_CMU_DLY_LTR_I2A_8814B) -#define BIT_GET_CMU_DLY_LTR_I2A_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8814B) & BIT_MASK_CMU_DLY_LTR_I2A_8814B) - - - -#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8814B 8 -#define BIT_MASK_CMU_DLY_LTR_IDLE_8814B 0xff -#define BIT_CMU_DLY_LTR_IDLE_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8814B) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8814B) -#define BIT_GET_CMU_DLY_LTR_IDLE_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8814B) & BIT_MASK_CMU_DLY_LTR_IDLE_8814B) - - - -#define BIT_SHIFT_CMU_DLY_LTR_ACT_8814B 0 -#define BIT_MASK_CMU_DLY_LTR_ACT_8814B 0xff -#define BIT_CMU_DLY_LTR_ACT_8814B(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8814B) << BIT_SHIFT_CMU_DLY_LTR_ACT_8814B) -#define BIT_GET_CMU_DLY_LTR_ACT_8814B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8814B) & BIT_MASK_CMU_DLY_LTR_ACT_8814B) - - - -/* 2 REG_H2CQ_TXBD_DESA_8814B */ - -#define BIT_SHIFT_H2CQ_TXBD_DESA_8814B 0 -#define BIT_MASK_H2CQ_TXBD_DESA_8814B 0xffffffffffffffffL -#define BIT_H2CQ_TXBD_DESA_8814B(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8814B) << BIT_SHIFT_H2CQ_TXBD_DESA_8814B) -#define BIT_GET_H2CQ_TXBD_DESA_8814B(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8814B) & BIT_MASK_H2CQ_TXBD_DESA_8814B) - - - -/* 2 REG_H2CQ_TXBD_NUM_8814B */ -#define BIT_PCIE_H2CQ_FLAG_8814B BIT(14) - -#define BIT_SHIFT_H2CQ_DESC_MODE_8814B 12 -#define BIT_MASK_H2CQ_DESC_MODE_8814B 0x3 -#define BIT_H2CQ_DESC_MODE_8814B(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8814B) << BIT_SHIFT_H2CQ_DESC_MODE_8814B) -#define BIT_GET_H2CQ_DESC_MODE_8814B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8814B) & BIT_MASK_H2CQ_DESC_MODE_8814B) - - - -#define BIT_SHIFT_H2CQ_DESC_NUM_8814B 0 -#define BIT_MASK_H2CQ_DESC_NUM_8814B 0xfff -#define BIT_H2CQ_DESC_NUM_8814B(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8814B) << BIT_SHIFT_H2CQ_DESC_NUM_8814B) -#define BIT_GET_H2CQ_DESC_NUM_8814B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8814B) & BIT_MASK_H2CQ_DESC_NUM_8814B) - - - -/* 2 REG_H2CQ_TXBD_IDX_8814B */ - -#define BIT_SHIFT_H2CQ_HW_IDX_8814B 16 -#define BIT_MASK_H2CQ_HW_IDX_8814B 0xfff -#define BIT_H2CQ_HW_IDX_8814B(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8814B) << BIT_SHIFT_H2CQ_HW_IDX_8814B) -#define BIT_GET_H2CQ_HW_IDX_8814B(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8814B) & BIT_MASK_H2CQ_HW_IDX_8814B) - - - -#define BIT_SHIFT_H2CQ_HOST_IDX_8814B 0 -#define BIT_MASK_H2CQ_HOST_IDX_8814B 0xfff -#define BIT_H2CQ_HOST_IDX_8814B(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8814B) << BIT_SHIFT_H2CQ_HOST_IDX_8814B) -#define BIT_GET_H2CQ_HOST_IDX_8814B(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8814B) & BIT_MASK_H2CQ_HOST_IDX_8814B) - - - -/* 2 REG_H2CQ_CSR_8814B[31:0] (H2CQ CONTROL AND STATUS) */ -#define BIT_H2CQ_FULL_8814B BIT(31) -#define BIT_CLR_H2CQ_HOST_IDX_8814B BIT(16) -#define BIT_CLR_H2CQ_HW_IDX_8814B BIT(8) - -/* 2 REG_Q0_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q0_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q0_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q0_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q0_V1_8814B) -#define BIT_GET_QUEUEMACID_Q0_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8814B) & BIT_MASK_QUEUEMACID_Q0_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q0_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q0_V1_8814B 0x3 -#define BIT_QUEUEAC_Q0_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8814B) << BIT_SHIFT_QUEUEAC_Q0_V1_8814B) -#define BIT_GET_QUEUEAC_Q0_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8814B) & BIT_MASK_QUEUEAC_Q0_V1_8814B) - - -#define BIT_TIDEMPTY_Q0_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q0_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q0_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q0_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q0_V2_8814B) -#define BIT_GET_TAIL_PKT_Q0_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8814B) & BIT_MASK_TAIL_PKT_Q0_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q0_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q0_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q0_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q0_V1_8814B) -#define BIT_GET_HEAD_PKT_Q0_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8814B) & BIT_MASK_HEAD_PKT_Q0_V1_8814B) - - - -/* 2 REG_Q1_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q1_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q1_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q1_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q1_V1_8814B) -#define BIT_GET_QUEUEMACID_Q1_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8814B) & BIT_MASK_QUEUEMACID_Q1_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q1_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q1_V1_8814B 0x3 -#define BIT_QUEUEAC_Q1_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8814B) << BIT_SHIFT_QUEUEAC_Q1_V1_8814B) -#define BIT_GET_QUEUEAC_Q1_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8814B) & BIT_MASK_QUEUEAC_Q1_V1_8814B) - - -#define BIT_TIDEMPTY_Q1_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q1_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q1_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q1_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q1_V2_8814B) -#define BIT_GET_TAIL_PKT_Q1_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8814B) & BIT_MASK_TAIL_PKT_Q1_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q1_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q1_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q1_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q1_V1_8814B) -#define BIT_GET_HEAD_PKT_Q1_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8814B) & BIT_MASK_HEAD_PKT_Q1_V1_8814B) - - - -/* 2 REG_Q2_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q2_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q2_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q2_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q2_V1_8814B) -#define BIT_GET_QUEUEMACID_Q2_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8814B) & BIT_MASK_QUEUEMACID_Q2_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q2_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q2_V1_8814B 0x3 -#define BIT_QUEUEAC_Q2_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8814B) << BIT_SHIFT_QUEUEAC_Q2_V1_8814B) -#define BIT_GET_QUEUEAC_Q2_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8814B) & BIT_MASK_QUEUEAC_Q2_V1_8814B) - - -#define BIT_TIDEMPTY_Q2_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q2_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q2_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q2_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q2_V2_8814B) -#define BIT_GET_TAIL_PKT_Q2_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8814B) & BIT_MASK_TAIL_PKT_Q2_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q2_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q2_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q2_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q2_V1_8814B) -#define BIT_GET_HEAD_PKT_Q2_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8814B) & BIT_MASK_HEAD_PKT_Q2_V1_8814B) - - - -/* 2 REG_Q3_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q3_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q3_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q3_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q3_V1_8814B) -#define BIT_GET_QUEUEMACID_Q3_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8814B) & BIT_MASK_QUEUEMACID_Q3_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q3_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q3_V1_8814B 0x3 -#define BIT_QUEUEAC_Q3_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8814B) << BIT_SHIFT_QUEUEAC_Q3_V1_8814B) -#define BIT_GET_QUEUEAC_Q3_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8814B) & BIT_MASK_QUEUEAC_Q3_V1_8814B) - - -#define BIT_TIDEMPTY_Q3_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q3_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q3_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q3_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q3_V2_8814B) -#define BIT_GET_TAIL_PKT_Q3_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8814B) & BIT_MASK_TAIL_PKT_Q3_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q3_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q3_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q3_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q3_V1_8814B) -#define BIT_GET_HEAD_PKT_Q3_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8814B) & BIT_MASK_HEAD_PKT_Q3_V1_8814B) - - - -/* 2 REG_MGQ_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_MGQ_V1_8814B 0x7f -#define BIT_QUEUEMACID_MGQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8814B) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8814B) -#define BIT_GET_QUEUEMACID_MGQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8814B) & BIT_MASK_QUEUEMACID_MGQ_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_MGQ_V1_8814B 23 -#define BIT_MASK_QUEUEAC_MGQ_V1_8814B 0x3 -#define BIT_QUEUEAC_MGQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8814B) << BIT_SHIFT_QUEUEAC_MGQ_V1_8814B) -#define BIT_GET_QUEUEAC_MGQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8814B) & BIT_MASK_QUEUEAC_MGQ_V1_8814B) - - -#define BIT_TIDEMPTY_MGQ_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_MGQ_V2_8814B 0x7ff -#define BIT_TAIL_PKT_MGQ_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8814B) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8814B) -#define BIT_GET_TAIL_PKT_MGQ_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8814B) & BIT_MASK_TAIL_PKT_MGQ_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_MGQ_V1_8814B 0x7ff -#define BIT_HEAD_PKT_MGQ_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8814B) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8814B) -#define BIT_GET_HEAD_PKT_MGQ_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8814B) & BIT_MASK_HEAD_PKT_MGQ_V1_8814B) - - - -/* 2 REG_HIQ_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_HIQ_V1_8814B 0x7f -#define BIT_QUEUEMACID_HIQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8814B) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8814B) -#define BIT_GET_QUEUEMACID_HIQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8814B) & BIT_MASK_QUEUEMACID_HIQ_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_HIQ_V1_8814B 23 -#define BIT_MASK_QUEUEAC_HIQ_V1_8814B 0x3 -#define BIT_QUEUEAC_HIQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8814B) << BIT_SHIFT_QUEUEAC_HIQ_V1_8814B) -#define BIT_GET_QUEUEAC_HIQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8814B) & BIT_MASK_QUEUEAC_HIQ_V1_8814B) - - -#define BIT_TIDEMPTY_HIQ_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_HIQ_V2_8814B 0x7ff -#define BIT_TAIL_PKT_HIQ_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8814B) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8814B) -#define BIT_GET_TAIL_PKT_HIQ_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8814B) & BIT_MASK_TAIL_PKT_HIQ_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_HIQ_V1_8814B 0x7ff -#define BIT_HEAD_PKT_HIQ_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8814B) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8814B) -#define BIT_GET_HEAD_PKT_HIQ_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8814B) & BIT_MASK_HEAD_PKT_HIQ_V1_8814B) - - - -/* 2 REG_BCNQ_INFO_8814B */ - -#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8814B 0 -#define BIT_MASK_BCNQ_HEAD_PG_V1_8814B 0xfff -#define BIT_BCNQ_HEAD_PG_V1_8814B(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8814B) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8814B) -#define BIT_GET_BCNQ_HEAD_PG_V1_8814B(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8814B) & BIT_MASK_BCNQ_HEAD_PG_V1_8814B) - - - -/* 2 REG_TXPKT_EMPTY_8814B */ -#define BIT_BCNQ_EMPTY_8814B BIT(11) -#define BIT_HQQ_EMPTY_8814B BIT(10) -#define BIT_MQQ_EMPTY_8814B BIT(9) -#define BIT_MGQ_CPU_EMPTY_8814B BIT(8) -#define BIT_AC7Q_EMPTY_8814B BIT(7) -#define BIT_AC6Q_EMPTY_8814B BIT(6) -#define BIT_AC5Q_EMPTY_8814B BIT(5) -#define BIT_AC4Q_EMPTY_8814B BIT(4) -#define BIT_AC3Q_EMPTY_8814B BIT(3) -#define BIT_AC2Q_EMPTY_8814B BIT(2) -#define BIT_AC1Q_EMPTY_8814B BIT(1) -#define BIT_AC0Q_EMPTY_8814B BIT(0) - -/* 2 REG_CPU_MGQ_INFO_8814B */ -#define BIT_BCN1_POLL_8814B BIT(30) -#define BIT_CPUMGT_POLL_8814B BIT(29) -#define BIT_BCN_POLL_8814B BIT(28) -#define BIT_CPUMGQ_FW_NUM_V1_8814B BIT(12) - -#define BIT_SHIFT_FW_FREE_TAIL_V1_8814B 0 -#define BIT_MASK_FW_FREE_TAIL_V1_8814B 0xfff -#define BIT_FW_FREE_TAIL_V1_8814B(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8814B) << BIT_SHIFT_FW_FREE_TAIL_V1_8814B) -#define BIT_GET_FW_FREE_TAIL_V1_8814B(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8814B) & BIT_MASK_FW_FREE_TAIL_V1_8814B) - - - -/* 2 REG_FWHW_TXQ_CTRL_8814B */ -#define BIT_RTS_LIMIT_IN_OFDM_8814B BIT(23) -#define BIT_EN_BCNQ_DL_8814B BIT(22) -#define BIT_EN_RD_RESP_NAV_BK_8814B BIT(21) -#define BIT_EN_WR_FREE_TAIL_8814B BIT(20) - -#define BIT_SHIFT_EN_QUEUE_RPT_8814B 8 -#define BIT_MASK_EN_QUEUE_RPT_8814B 0xff -#define BIT_EN_QUEUE_RPT_8814B(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8814B) << BIT_SHIFT_EN_QUEUE_RPT_8814B) -#define BIT_GET_EN_QUEUE_RPT_8814B(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8814B) & BIT_MASK_EN_QUEUE_RPT_8814B) - - -#define BIT_EN_RTY_BK_8814B BIT(7) -#define BIT_EN_USE_INI_RAT_8814B BIT(6) -#define BIT_EN_RTS_NAV_BK_8814B BIT(5) -#define BIT_DIS_SSN_CHECK_8814B BIT(4) -#define BIT_MACID_MATCH_RTS_8814B BIT(3) -#define BIT_EN_BCN_TRXRPT_V1_8814B BIT(2) -#define BIT_R_EN_FTMRPT_8814B BIT(1) -#define BIT_R_BMC_NAV_PROTECT_8814B BIT(0) - -/* 2 REG_DATAFB_SEL_8814B */ -#define BIT__R_EN_RTY_BK_COD_8814B BIT(2) - -#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8814B 0 -#define BIT_MASK__R_DATA_FALLBACK_SEL_8814B 0x3 -#define BIT__R_DATA_FALLBACK_SEL_8814B(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8814B) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8814B) -#define BIT_GET__R_DATA_FALLBACK_SEL_8814B(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8814B) & BIT_MASK__R_DATA_FALLBACK_SEL_8814B) - - - -/* 2 REG_BCNQ_BDNY_V1_8814B */ - -#define BIT_SHIFT_BCNQ_PGBNDY_V1_8814B 0 -#define BIT_MASK_BCNQ_PGBNDY_V1_8814B 0xfff -#define BIT_BCNQ_PGBNDY_V1_8814B(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8814B) << BIT_SHIFT_BCNQ_PGBNDY_V1_8814B) -#define BIT_GET_BCNQ_PGBNDY_V1_8814B(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8814B) & BIT_MASK_BCNQ_PGBNDY_V1_8814B) - - - -/* 2 REG_LIFETIME_EN_8814B */ -#define BIT_BT_INT_CPU_8814B BIT(7) -#define BIT_BT_INT_PTA_8814B BIT(6) -#define BIT_EN_CTRL_RTYBIT_8814B BIT(4) -#define BIT_LIFETIME_BK_EN_8814B BIT(3) -#define BIT_LIFETIME_BE_EN_8814B BIT(2) -#define BIT_LIFETIME_VI_EN_8814B BIT(1) -#define BIT_LIFETIME_VO_EN_8814B BIT(0) - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_SPEC_SIFS_8814B */ - -#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B 8 -#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B 0xff -#define BIT_SPEC_SIFS_OFDM_PTCL_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) -#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B) - - - -#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B 0 -#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B 0xff -#define BIT_SPEC_SIFS_CCK_PTCL_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) -#define BIT_GET_SPEC_SIFS_CCK_PTCL_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B) - - - -/* 2 REG_RETRY_LIMIT_8814B */ - -#define BIT_SHIFT_SRL_8814B 8 -#define BIT_MASK_SRL_8814B 0x3f -#define BIT_SRL_8814B(x) (((x) & BIT_MASK_SRL_8814B) << BIT_SHIFT_SRL_8814B) -#define BIT_GET_SRL_8814B(x) (((x) >> BIT_SHIFT_SRL_8814B) & BIT_MASK_SRL_8814B) - - - -#define BIT_SHIFT_LRL_8814B 0 -#define BIT_MASK_LRL_8814B 0x3f -#define BIT_LRL_8814B(x) (((x) & BIT_MASK_LRL_8814B) << BIT_SHIFT_LRL_8814B) -#define BIT_GET_LRL_8814B(x) (((x) >> BIT_SHIFT_LRL_8814B) & BIT_MASK_LRL_8814B) - - - -/* 2 REG_TXBF_CTRL_8814B */ -#define BIT_R_ENABLE_NDPA_8814B BIT(31) -#define BIT_USE_NDPA_PARAMETER_8814B BIT(30) -#define BIT_R_PROP_TXBF_8814B BIT(29) -#define BIT_R_EN_NDPA_INT_8814B BIT(28) -#define BIT_R_TXBF1_80M_8814B BIT(27) -#define BIT_R_TXBF1_40M_8814B BIT(26) -#define BIT_R_TXBF1_20M_8814B BIT(25) - -#define BIT_SHIFT_R_TXBF1_AID_8814B 16 -#define BIT_MASK_R_TXBF1_AID_8814B 0x1ff -#define BIT_R_TXBF1_AID_8814B(x) (((x) & BIT_MASK_R_TXBF1_AID_8814B) << BIT_SHIFT_R_TXBF1_AID_8814B) -#define BIT_GET_R_TXBF1_AID_8814B(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8814B) & BIT_MASK_R_TXBF1_AID_8814B) - - -#define BIT_DIS_NDP_BFEN_8814B BIT(15) -#define BIT_R_TXBCN_NOBLOCK_NDP_8814B BIT(14) -#define BIT_R_TXBF0_80M_8814B BIT(11) -#define BIT_R_TXBF0_40M_8814B BIT(10) -#define BIT_R_TXBF0_20M_8814B BIT(9) - -#define BIT_SHIFT_R_TXBF0_AID_8814B 0 -#define BIT_MASK_R_TXBF0_AID_8814B 0x1ff -#define BIT_R_TXBF0_AID_8814B(x) (((x) & BIT_MASK_R_TXBF0_AID_8814B) << BIT_SHIFT_R_TXBF0_AID_8814B) -#define BIT_GET_R_TXBF0_AID_8814B(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8814B) & BIT_MASK_R_TXBF0_AID_8814B) - - - -/* 2 REG_DARFRC_8814B */ - -#define BIT_SHIFT_DARF_RC8_8814B (56 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC8_8814B 0x1f -#define BIT_DARF_RC8_8814B(x) (((x) & BIT_MASK_DARF_RC8_8814B) << BIT_SHIFT_DARF_RC8_8814B) -#define BIT_GET_DARF_RC8_8814B(x) (((x) >> BIT_SHIFT_DARF_RC8_8814B) & BIT_MASK_DARF_RC8_8814B) - - - -#define BIT_SHIFT_DARF_RC7_8814B (48 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC7_8814B 0x1f -#define BIT_DARF_RC7_8814B(x) (((x) & BIT_MASK_DARF_RC7_8814B) << BIT_SHIFT_DARF_RC7_8814B) -#define BIT_GET_DARF_RC7_8814B(x) (((x) >> BIT_SHIFT_DARF_RC7_8814B) & BIT_MASK_DARF_RC7_8814B) - - - -#define BIT_SHIFT_DARF_RC6_8814B (40 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC6_8814B 0x1f -#define BIT_DARF_RC6_8814B(x) (((x) & BIT_MASK_DARF_RC6_8814B) << BIT_SHIFT_DARF_RC6_8814B) -#define BIT_GET_DARF_RC6_8814B(x) (((x) >> BIT_SHIFT_DARF_RC6_8814B) & BIT_MASK_DARF_RC6_8814B) - - - -#define BIT_SHIFT_DARF_RC5_8814B (32 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC5_8814B 0x1f -#define BIT_DARF_RC5_8814B(x) (((x) & BIT_MASK_DARF_RC5_8814B) << BIT_SHIFT_DARF_RC5_8814B) -#define BIT_GET_DARF_RC5_8814B(x) (((x) >> BIT_SHIFT_DARF_RC5_8814B) & BIT_MASK_DARF_RC5_8814B) - - - -#define BIT_SHIFT_DARF_RC4_8814B 24 -#define BIT_MASK_DARF_RC4_8814B 0x1f -#define BIT_DARF_RC4_8814B(x) (((x) & BIT_MASK_DARF_RC4_8814B) << BIT_SHIFT_DARF_RC4_8814B) -#define BIT_GET_DARF_RC4_8814B(x) (((x) >> BIT_SHIFT_DARF_RC4_8814B) & BIT_MASK_DARF_RC4_8814B) - - - -#define BIT_SHIFT_DARF_RC3_8814B 16 -#define BIT_MASK_DARF_RC3_8814B 0x1f -#define BIT_DARF_RC3_8814B(x) (((x) & BIT_MASK_DARF_RC3_8814B) << BIT_SHIFT_DARF_RC3_8814B) -#define BIT_GET_DARF_RC3_8814B(x) (((x) >> BIT_SHIFT_DARF_RC3_8814B) & BIT_MASK_DARF_RC3_8814B) - - - -#define BIT_SHIFT_DARF_RC2_8814B 8 -#define BIT_MASK_DARF_RC2_8814B 0x1f -#define BIT_DARF_RC2_8814B(x) (((x) & BIT_MASK_DARF_RC2_8814B) << BIT_SHIFT_DARF_RC2_8814B) -#define BIT_GET_DARF_RC2_8814B(x) (((x) >> BIT_SHIFT_DARF_RC2_8814B) & BIT_MASK_DARF_RC2_8814B) - - - -#define BIT_SHIFT_DARF_RC1_8814B 0 -#define BIT_MASK_DARF_RC1_8814B 0x1f -#define BIT_DARF_RC1_8814B(x) (((x) & BIT_MASK_DARF_RC1_8814B) << BIT_SHIFT_DARF_RC1_8814B) -#define BIT_GET_DARF_RC1_8814B(x) (((x) >> BIT_SHIFT_DARF_RC1_8814B) & BIT_MASK_DARF_RC1_8814B) - - - -/* 2 REG_RARFRC_8814B */ - -#define BIT_SHIFT_RARF_RC8_8814B (56 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC8_8814B 0x1f -#define BIT_RARF_RC8_8814B(x) (((x) & BIT_MASK_RARF_RC8_8814B) << BIT_SHIFT_RARF_RC8_8814B) -#define BIT_GET_RARF_RC8_8814B(x) (((x) >> BIT_SHIFT_RARF_RC8_8814B) & BIT_MASK_RARF_RC8_8814B) - - - -#define BIT_SHIFT_RARF_RC7_8814B (48 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC7_8814B 0x1f -#define BIT_RARF_RC7_8814B(x) (((x) & BIT_MASK_RARF_RC7_8814B) << BIT_SHIFT_RARF_RC7_8814B) -#define BIT_GET_RARF_RC7_8814B(x) (((x) >> BIT_SHIFT_RARF_RC7_8814B) & BIT_MASK_RARF_RC7_8814B) - - - -#define BIT_SHIFT_RARF_RC6_8814B (40 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC6_8814B 0x1f -#define BIT_RARF_RC6_8814B(x) (((x) & BIT_MASK_RARF_RC6_8814B) << BIT_SHIFT_RARF_RC6_8814B) -#define BIT_GET_RARF_RC6_8814B(x) (((x) >> BIT_SHIFT_RARF_RC6_8814B) & BIT_MASK_RARF_RC6_8814B) - - - -#define BIT_SHIFT_RARF_RC5_8814B (32 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC5_8814B 0x1f -#define BIT_RARF_RC5_8814B(x) (((x) & BIT_MASK_RARF_RC5_8814B) << BIT_SHIFT_RARF_RC5_8814B) -#define BIT_GET_RARF_RC5_8814B(x) (((x) >> BIT_SHIFT_RARF_RC5_8814B) & BIT_MASK_RARF_RC5_8814B) - - - -#define BIT_SHIFT_RARF_RC4_8814B 24 -#define BIT_MASK_RARF_RC4_8814B 0x1f -#define BIT_RARF_RC4_8814B(x) (((x) & BIT_MASK_RARF_RC4_8814B) << BIT_SHIFT_RARF_RC4_8814B) -#define BIT_GET_RARF_RC4_8814B(x) (((x) >> BIT_SHIFT_RARF_RC4_8814B) & BIT_MASK_RARF_RC4_8814B) - - - -#define BIT_SHIFT_RARF_RC3_8814B 16 -#define BIT_MASK_RARF_RC3_8814B 0x1f -#define BIT_RARF_RC3_8814B(x) (((x) & BIT_MASK_RARF_RC3_8814B) << BIT_SHIFT_RARF_RC3_8814B) -#define BIT_GET_RARF_RC3_8814B(x) (((x) >> BIT_SHIFT_RARF_RC3_8814B) & BIT_MASK_RARF_RC3_8814B) - - - -#define BIT_SHIFT_RARF_RC2_8814B 8 -#define BIT_MASK_RARF_RC2_8814B 0x1f -#define BIT_RARF_RC2_8814B(x) (((x) & BIT_MASK_RARF_RC2_8814B) << BIT_SHIFT_RARF_RC2_8814B) -#define BIT_GET_RARF_RC2_8814B(x) (((x) >> BIT_SHIFT_RARF_RC2_8814B) & BIT_MASK_RARF_RC2_8814B) - - - -#define BIT_SHIFT_RARF_RC1_8814B 0 -#define BIT_MASK_RARF_RC1_8814B 0x1f -#define BIT_RARF_RC1_8814B(x) (((x) & BIT_MASK_RARF_RC1_8814B) << BIT_SHIFT_RARF_RC1_8814B) -#define BIT_GET_RARF_RC1_8814B(x) (((x) >> BIT_SHIFT_RARF_RC1_8814B) & BIT_MASK_RARF_RC1_8814B) - - - -/* 2 REG_RRSR_8814B */ - -#define BIT_SHIFT_RRSR_RSC_8814B 21 -#define BIT_MASK_RRSR_RSC_8814B 0x3 -#define BIT_RRSR_RSC_8814B(x) (((x) & BIT_MASK_RRSR_RSC_8814B) << BIT_SHIFT_RRSR_RSC_8814B) -#define BIT_GET_RRSR_RSC_8814B(x) (((x) >> BIT_SHIFT_RRSR_RSC_8814B) & BIT_MASK_RRSR_RSC_8814B) - - -#define BIT_RRSR_BW_8814B BIT(20) - -#define BIT_SHIFT_RRSC_BITMAP_8814B 0 -#define BIT_MASK_RRSC_BITMAP_8814B 0xfffff -#define BIT_RRSC_BITMAP_8814B(x) (((x) & BIT_MASK_RRSC_BITMAP_8814B) << BIT_SHIFT_RRSC_BITMAP_8814B) -#define BIT_GET_RRSC_BITMAP_8814B(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8814B) & BIT_MASK_RRSC_BITMAP_8814B) - - - -/* 2 REG_ARFR0_8814B */ - -#define BIT_SHIFT_ARFR0_V1_8814B 0 -#define BIT_MASK_ARFR0_V1_8814B 0xffffffffffffffffL -#define BIT_ARFR0_V1_8814B(x) (((x) & BIT_MASK_ARFR0_V1_8814B) << BIT_SHIFT_ARFR0_V1_8814B) -#define BIT_GET_ARFR0_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR0_V1_8814B) & BIT_MASK_ARFR0_V1_8814B) - - - -/* 2 REG_ARFR1_V1_8814B */ - -#define BIT_SHIFT_ARFR1_V1_8814B 0 -#define BIT_MASK_ARFR1_V1_8814B 0xffffffffffffffffL -#define BIT_ARFR1_V1_8814B(x) (((x) & BIT_MASK_ARFR1_V1_8814B) << BIT_SHIFT_ARFR1_V1_8814B) -#define BIT_GET_ARFR1_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR1_V1_8814B) & BIT_MASK_ARFR1_V1_8814B) - - - -/* 2 REG_CCK_CHECK_8814B */ -#define BIT_CHECK_CCK_EN_8814B BIT(7) -#define BIT_EN_BCN_PKT_REL_8814B BIT(6) -#define BIT_BCN_PORT_SEL_8814B BIT(5) -#define BIT_MOREDATA_BYPASS_8814B BIT(4) -#define BIT_EN_CLR_CMD_REL_BCN_PKT_8814B BIT(3) -#define BIT_R_EN_SET_MOREDATA_8814B BIT(2) -#define BIT__R_DIS_CLEAR_MACID_RELEASE_8814B BIT(1) -#define BIT__R_MACID_RELEASE_EN_8814B BIT(0) - -/* 2 REG_AMPDU_MAX_TIME_V1_8814B */ - -#define BIT_SHIFT_AMPDU_MAX_TIME_8814B 0 -#define BIT_MASK_AMPDU_MAX_TIME_8814B 0xff -#define BIT_AMPDU_MAX_TIME_8814B(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8814B) << BIT_SHIFT_AMPDU_MAX_TIME_8814B) -#define BIT_GET_AMPDU_MAX_TIME_8814B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8814B) & BIT_MASK_AMPDU_MAX_TIME_8814B) - - - -/* 2 REG_BCNQ1_BDNY_V1_8814B */ - -#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8814B 0 -#define BIT_MASK_BCNQ1_PGBNDY_V1_8814B 0xfff -#define BIT_BCNQ1_PGBNDY_V1_8814B(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8814B) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8814B) -#define BIT_GET_BCNQ1_PGBNDY_V1_8814B(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8814B) & BIT_MASK_BCNQ1_PGBNDY_V1_8814B) - - - -/* 2 REG_AMPDU_MAX_LENGTH_8814B */ - -#define BIT_SHIFT_AMPDU_MAX_LENGTH_8814B 0 -#define BIT_MASK_AMPDU_MAX_LENGTH_8814B 0xffffffffL -#define BIT_AMPDU_MAX_LENGTH_8814B(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8814B) << BIT_SHIFT_AMPDU_MAX_LENGTH_8814B) -#define BIT_GET_AMPDU_MAX_LENGTH_8814B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8814B) & BIT_MASK_AMPDU_MAX_LENGTH_8814B) - - - -/* 2 REG_ACQ_STOP_8814B */ -#define BIT_AC7Q_STOP_8814B BIT(7) -#define BIT_AC6Q_STOP_8814B BIT(6) -#define BIT_AC5Q_STOP_8814B BIT(5) -#define BIT_AC4Q_STOP_8814B BIT(4) -#define BIT_AC3Q_STOP_8814B BIT(3) -#define BIT_AC2Q_STOP_8814B BIT(2) -#define BIT_AC1Q_STOP_8814B BIT(1) -#define BIT_AC0Q_STOP_8814B BIT(0) - -/* 2 REG_NDPA_RATE_8814B */ - -#define BIT_SHIFT_R_NDPA_RATE_V1_8814B 0 -#define BIT_MASK_R_NDPA_RATE_V1_8814B 0xff -#define BIT_R_NDPA_RATE_V1_8814B(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8814B) << BIT_SHIFT_R_NDPA_RATE_V1_8814B) -#define BIT_GET_R_NDPA_RATE_V1_8814B(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8814B) & BIT_MASK_R_NDPA_RATE_V1_8814B) - - - -/* 2 REG_TX_HANG_CTRL_8814B */ -#define BIT_R_EN_GNT_BT_AWAKE_8814B BIT(3) -#define BIT_EN_EOF_V1_8814B BIT(2) -#define BIT_DIS_OQT_BLOCK_8814B BIT(1) -#define BIT_SEARCH_QUEUE_EN_8814B BIT(0) - -/* 2 REG_NDPA_OPT_CTRL_8814B */ -#define BIT_R_DIS_MACID_RELEASE_RTY_8814B BIT(5) - -#define BIT_SHIFT_BW_SIGTA_8814B 3 -#define BIT_MASK_BW_SIGTA_8814B 0x3 -#define BIT_BW_SIGTA_8814B(x) (((x) & BIT_MASK_BW_SIGTA_8814B) << BIT_SHIFT_BW_SIGTA_8814B) -#define BIT_GET_BW_SIGTA_8814B(x) (((x) >> BIT_SHIFT_BW_SIGTA_8814B) & BIT_MASK_BW_SIGTA_8814B) - - -#define BIT_EN_BAR_SIGTA_8814B BIT(2) - -#define BIT_SHIFT_R_NDPA_BW_8814B 0 -#define BIT_MASK_R_NDPA_BW_8814B 0x3 -#define BIT_R_NDPA_BW_8814B(x) (((x) & BIT_MASK_R_NDPA_BW_8814B) << BIT_SHIFT_R_NDPA_BW_8814B) -#define BIT_GET_R_NDPA_BW_8814B(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8814B) & BIT_MASK_R_NDPA_BW_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_RD_RESP_PKT_TH_8814B */ - -#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B 0 -#define BIT_MASK_RD_RESP_PKT_TH_V1_8814B 0x3f -#define BIT_RD_RESP_PKT_TH_V1_8814B(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8814B) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) -#define BIT_GET_RD_RESP_PKT_TH_V1_8814B(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) & BIT_MASK_RD_RESP_PKT_TH_V1_8814B) - - - -/* 2 REG_CMDQ_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_CMDQ_V1_8814B 0x7f -#define BIT_QUEUEMACID_CMDQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8814B) << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8814B) -#define BIT_GET_QUEUEMACID_CMDQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8814B) & BIT_MASK_QUEUEMACID_CMDQ_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8814B 23 -#define BIT_MASK_QUEUEAC_CMDQ_V1_8814B 0x3 -#define BIT_QUEUEAC_CMDQ_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8814B) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8814B) -#define BIT_GET_QUEUEAC_CMDQ_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8814B) & BIT_MASK_QUEUEAC_CMDQ_V1_8814B) - - -#define BIT_TIDEMPTY_CMDQ_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_CMDQ_V2_8814B 0x7ff -#define BIT_TAIL_PKT_CMDQ_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8814B) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8814B) -#define BIT_GET_TAIL_PKT_CMDQ_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8814B) & BIT_MASK_TAIL_PKT_CMDQ_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_CMDQ_V1_8814B 0x7ff -#define BIT_HEAD_PKT_CMDQ_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8814B) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8814B) -#define BIT_GET_HEAD_PKT_CMDQ_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8814B) & BIT_MASK_HEAD_PKT_CMDQ_V1_8814B) - - - -/* 2 REG_Q4_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q4_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q4_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q4_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q4_V1_8814B) -#define BIT_GET_QUEUEMACID_Q4_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8814B) & BIT_MASK_QUEUEMACID_Q4_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q4_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q4_V1_8814B 0x3 -#define BIT_QUEUEAC_Q4_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8814B) << BIT_SHIFT_QUEUEAC_Q4_V1_8814B) -#define BIT_GET_QUEUEAC_Q4_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8814B) & BIT_MASK_QUEUEAC_Q4_V1_8814B) - - -#define BIT_TIDEMPTY_Q4_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q4_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q4_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q4_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q4_V2_8814B) -#define BIT_GET_TAIL_PKT_Q4_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8814B) & BIT_MASK_TAIL_PKT_Q4_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q4_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q4_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q4_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q4_V1_8814B) -#define BIT_GET_HEAD_PKT_Q4_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8814B) & BIT_MASK_HEAD_PKT_Q4_V1_8814B) - - - -/* 2 REG_Q5_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q5_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q5_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q5_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q5_V1_8814B) -#define BIT_GET_QUEUEMACID_Q5_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8814B) & BIT_MASK_QUEUEMACID_Q5_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q5_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q5_V1_8814B 0x3 -#define BIT_QUEUEAC_Q5_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8814B) << BIT_SHIFT_QUEUEAC_Q5_V1_8814B) -#define BIT_GET_QUEUEAC_Q5_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8814B) & BIT_MASK_QUEUEAC_Q5_V1_8814B) - - -#define BIT_TIDEMPTY_Q5_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q5_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q5_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q5_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q5_V2_8814B) -#define BIT_GET_TAIL_PKT_Q5_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8814B) & BIT_MASK_TAIL_PKT_Q5_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q5_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q5_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q5_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q5_V1_8814B) -#define BIT_GET_HEAD_PKT_Q5_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8814B) & BIT_MASK_HEAD_PKT_Q5_V1_8814B) - - - -/* 2 REG_Q6_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q6_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q6_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q6_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q6_V1_8814B) -#define BIT_GET_QUEUEMACID_Q6_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8814B) & BIT_MASK_QUEUEMACID_Q6_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q6_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q6_V1_8814B 0x3 -#define BIT_QUEUEAC_Q6_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8814B) << BIT_SHIFT_QUEUEAC_Q6_V1_8814B) -#define BIT_GET_QUEUEAC_Q6_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8814B) & BIT_MASK_QUEUEAC_Q6_V1_8814B) - - -#define BIT_TIDEMPTY_Q6_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q6_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q6_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q6_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q6_V2_8814B) -#define BIT_GET_TAIL_PKT_Q6_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8814B) & BIT_MASK_TAIL_PKT_Q6_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q6_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q6_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q6_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q6_V1_8814B) -#define BIT_GET_HEAD_PKT_Q6_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8814B) & BIT_MASK_HEAD_PKT_Q6_V1_8814B) - - - -/* 2 REG_Q7_INFO_8814B */ - -#define BIT_SHIFT_QUEUEMACID_Q7_V1_8814B 25 -#define BIT_MASK_QUEUEMACID_Q7_V1_8814B 0x7f -#define BIT_QUEUEMACID_Q7_V1_8814B(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8814B) << BIT_SHIFT_QUEUEMACID_Q7_V1_8814B) -#define BIT_GET_QUEUEMACID_Q7_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8814B) & BIT_MASK_QUEUEMACID_Q7_V1_8814B) - - - -#define BIT_SHIFT_QUEUEAC_Q7_V1_8814B 23 -#define BIT_MASK_QUEUEAC_Q7_V1_8814B 0x3 -#define BIT_QUEUEAC_Q7_V1_8814B(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8814B) << BIT_SHIFT_QUEUEAC_Q7_V1_8814B) -#define BIT_GET_QUEUEAC_Q7_V1_8814B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8814B) & BIT_MASK_QUEUEAC_Q7_V1_8814B) - - -#define BIT_TIDEMPTY_Q7_V1_8814B BIT(22) - -#define BIT_SHIFT_TAIL_PKT_Q7_V2_8814B 11 -#define BIT_MASK_TAIL_PKT_Q7_V2_8814B 0x7ff -#define BIT_TAIL_PKT_Q7_V2_8814B(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8814B) << BIT_SHIFT_TAIL_PKT_Q7_V2_8814B) -#define BIT_GET_TAIL_PKT_Q7_V2_8814B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8814B) & BIT_MASK_TAIL_PKT_Q7_V2_8814B) - - - -#define BIT_SHIFT_HEAD_PKT_Q7_V1_8814B 0 -#define BIT_MASK_HEAD_PKT_Q7_V1_8814B 0x7ff -#define BIT_HEAD_PKT_Q7_V1_8814B(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8814B) << BIT_SHIFT_HEAD_PKT_Q7_V1_8814B) -#define BIT_GET_HEAD_PKT_Q7_V1_8814B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8814B) & BIT_MASK_HEAD_PKT_Q7_V1_8814B) - - - -/* 2 REG_WMAC_LBK_BUF_HD_V1_8814B */ - -#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B 0 -#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B 0xfff -#define BIT_WMAC_LBK_BUF_HEAD_V1_8814B(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) -#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8814B(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B) - - - -/* 2 REG_MGQ_BDNY_V1_8814B */ - -#define BIT_SHIFT_MGQ_PGBNDY_V1_8814B 0 -#define BIT_MASK_MGQ_PGBNDY_V1_8814B 0xfff -#define BIT_MGQ_PGBNDY_V1_8814B(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8814B) << BIT_SHIFT_MGQ_PGBNDY_V1_8814B) -#define BIT_GET_MGQ_PGBNDY_V1_8814B(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8814B) & BIT_MASK_MGQ_PGBNDY_V1_8814B) - - - -/* 2 REG_TXRPT_CTRL_8814B */ - -#define BIT_SHIFT_TRXRPT_TIMER_TH_8814B 24 -#define BIT_MASK_TRXRPT_TIMER_TH_8814B 0xff -#define BIT_TRXRPT_TIMER_TH_8814B(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8814B) << BIT_SHIFT_TRXRPT_TIMER_TH_8814B) -#define BIT_GET_TRXRPT_TIMER_TH_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8814B) & BIT_MASK_TRXRPT_TIMER_TH_8814B) - - - -#define BIT_SHIFT_TRXRPT_LEN_TH_8814B 16 -#define BIT_MASK_TRXRPT_LEN_TH_8814B 0xff -#define BIT_TRXRPT_LEN_TH_8814B(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8814B) << BIT_SHIFT_TRXRPT_LEN_TH_8814B) -#define BIT_GET_TRXRPT_LEN_TH_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8814B) & BIT_MASK_TRXRPT_LEN_TH_8814B) - - - -#define BIT_SHIFT_TRXRPT_READ_PTR_8814B 8 -#define BIT_MASK_TRXRPT_READ_PTR_8814B 0xff -#define BIT_TRXRPT_READ_PTR_8814B(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8814B) << BIT_SHIFT_TRXRPT_READ_PTR_8814B) -#define BIT_GET_TRXRPT_READ_PTR_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8814B) & BIT_MASK_TRXRPT_READ_PTR_8814B) - - - -#define BIT_SHIFT_TRXRPT_WRITE_PTR_8814B 0 -#define BIT_MASK_TRXRPT_WRITE_PTR_8814B 0xff -#define BIT_TRXRPT_WRITE_PTR_8814B(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8814B) << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) -#define BIT_GET_TRXRPT_WRITE_PTR_8814B(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) & BIT_MASK_TRXRPT_WRITE_PTR_8814B) - - - -/* 2 REG_INIRTS_RATE_SEL_8814B */ -#define BIT_LEAG_RTS_BW_DUP_8814B BIT(5) - -/* 2 REG_BASIC_CFEND_RATE_8814B */ - -#define BIT_SHIFT_BASIC_CFEND_RATE_8814B 0 -#define BIT_MASK_BASIC_CFEND_RATE_8814B 0x1f -#define BIT_BASIC_CFEND_RATE_8814B(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8814B) << BIT_SHIFT_BASIC_CFEND_RATE_8814B) -#define BIT_GET_BASIC_CFEND_RATE_8814B(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8814B) & BIT_MASK_BASIC_CFEND_RATE_8814B) - - - -/* 2 REG_STBC_CFEND_RATE_8814B */ - -#define BIT_SHIFT_STBC_CFEND_RATE_8814B 0 -#define BIT_MASK_STBC_CFEND_RATE_8814B 0x1f -#define BIT_STBC_CFEND_RATE_8814B(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8814B) << BIT_SHIFT_STBC_CFEND_RATE_8814B) -#define BIT_GET_STBC_CFEND_RATE_8814B(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8814B) & BIT_MASK_STBC_CFEND_RATE_8814B) - - - -/* 2 REG_DATA_SC_8814B */ - -#define BIT_SHIFT_TXSC_40M_8814B 4 -#define BIT_MASK_TXSC_40M_8814B 0xf -#define BIT_TXSC_40M_8814B(x) (((x) & BIT_MASK_TXSC_40M_8814B) << BIT_SHIFT_TXSC_40M_8814B) -#define BIT_GET_TXSC_40M_8814B(x) (((x) >> BIT_SHIFT_TXSC_40M_8814B) & BIT_MASK_TXSC_40M_8814B) - - - -#define BIT_SHIFT_TXSC_20M_8814B 0 -#define BIT_MASK_TXSC_20M_8814B 0xf -#define BIT_TXSC_20M_8814B(x) (((x) & BIT_MASK_TXSC_20M_8814B) << BIT_SHIFT_TXSC_20M_8814B) -#define BIT_GET_TXSC_20M_8814B(x) (((x) >> BIT_SHIFT_TXSC_20M_8814B) & BIT_MASK_TXSC_20M_8814B) - - - -/* 2 REG_MACID_SLEEP3_8814B */ - -#define BIT_SHIFT_MACID127_96_PKTSLEEP_8814B 0 -#define BIT_MASK_MACID127_96_PKTSLEEP_8814B 0xffffffffL -#define BIT_MACID127_96_PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8814B) << BIT_SHIFT_MACID127_96_PKTSLEEP_8814B) -#define BIT_GET_MACID127_96_PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8814B) & BIT_MASK_MACID127_96_PKTSLEEP_8814B) - - - -/* 2 REG_MACID_SLEEP1_8814B */ - -#define BIT_SHIFT_MACID63_32_PKTSLEEP_8814B 0 -#define BIT_MASK_MACID63_32_PKTSLEEP_8814B 0xffffffffL -#define BIT_MACID63_32_PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8814B) << BIT_SHIFT_MACID63_32_PKTSLEEP_8814B) -#define BIT_GET_MACID63_32_PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8814B) & BIT_MASK_MACID63_32_PKTSLEEP_8814B) - - - -/* 2 REG_ARFR2_V1_8814B */ - -#define BIT_SHIFT_ARFR2_V1_8814B 0 -#define BIT_MASK_ARFR2_V1_8814B 0xffffffffffffffffL -#define BIT_ARFR2_V1_8814B(x) (((x) & BIT_MASK_ARFR2_V1_8814B) << BIT_SHIFT_ARFR2_V1_8814B) -#define BIT_GET_ARFR2_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR2_V1_8814B) & BIT_MASK_ARFR2_V1_8814B) - - - -/* 2 REG_ARFR3_V1_8814B */ - -#define BIT_SHIFT_ARFR3_V1_8814B 0 -#define BIT_MASK_ARFR3_V1_8814B 0xffffffffffffffffL -#define BIT_ARFR3_V1_8814B(x) (((x) & BIT_MASK_ARFR3_V1_8814B) << BIT_SHIFT_ARFR3_V1_8814B) -#define BIT_GET_ARFR3_V1_8814B(x) (((x) >> BIT_SHIFT_ARFR3_V1_8814B) & BIT_MASK_ARFR3_V1_8814B) - - - -/* 2 REG_ARFR4_8814B */ - -#define BIT_SHIFT_ARFR4_8814B 0 -#define BIT_MASK_ARFR4_8814B 0xffffffffffffffffL -#define BIT_ARFR4_8814B(x) (((x) & BIT_MASK_ARFR4_8814B) << BIT_SHIFT_ARFR4_8814B) -#define BIT_GET_ARFR4_8814B(x) (((x) >> BIT_SHIFT_ARFR4_8814B) & BIT_MASK_ARFR4_8814B) - - - -/* 2 REG_ARFR5_8814B */ - -#define BIT_SHIFT_ARFR5_8814B 0 -#define BIT_MASK_ARFR5_8814B 0xffffffffffffffffL -#define BIT_ARFR5_8814B(x) (((x) & BIT_MASK_ARFR5_8814B) << BIT_SHIFT_ARFR5_8814B) -#define BIT_GET_ARFR5_8814B(x) (((x) >> BIT_SHIFT_ARFR5_8814B) & BIT_MASK_ARFR5_8814B) - - - -/* 2 REG_TXRPT_START_OFFSET_8814B */ - -#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8814B 24 -#define BIT_MASK_R_MUTAB_TXRPT_OFFSET_8814B 0xff -#define BIT_R_MUTAB_TXRPT_OFFSET_8814B(x) (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8814B) << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8814B) -#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8814B(x) (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8814B) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8814B) - - -#define BIT__R_RPTFIFO_1K_8814B BIT(16) - -#define BIT_SHIFT_MACID_CTRL_OFFSET_8814B 8 -#define BIT_MASK_MACID_CTRL_OFFSET_8814B 0xff -#define BIT_MACID_CTRL_OFFSET_8814B(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8814B) << BIT_SHIFT_MACID_CTRL_OFFSET_8814B) -#define BIT_GET_MACID_CTRL_OFFSET_8814B(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8814B) & BIT_MASK_MACID_CTRL_OFFSET_8814B) - - - -#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8814B 0 -#define BIT_MASK_AMPDU_TXRPT_OFFSET_8814B 0xff -#define BIT_AMPDU_TXRPT_OFFSET_8814B(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8814B) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8814B) -#define BIT_GET_AMPDU_TXRPT_OFFSET_8814B(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8814B) & BIT_MASK_AMPDU_TXRPT_OFFSET_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_POWER_STAGE1_8814B */ -#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8814B BIT(31) -#define BIT_PTA_WL_PRI_MASK_BCNQ_8814B BIT(30) -#define BIT_PTA_WL_PRI_MASK_HIQ_8814B BIT(29) -#define BIT_PTA_WL_PRI_MASK_MGQ_8814B BIT(28) -#define BIT_PTA_WL_PRI_MASK_BK_8814B BIT(27) -#define BIT_PTA_WL_PRI_MASK_BE_8814B BIT(26) -#define BIT_PTA_WL_PRI_MASK_VI_8814B BIT(25) -#define BIT_PTA_WL_PRI_MASK_VO_8814B BIT(24) - -#define BIT_SHIFT_POWER_STAGE1_8814B 0 -#define BIT_MASK_POWER_STAGE1_8814B 0xffffff -#define BIT_POWER_STAGE1_8814B(x) (((x) & BIT_MASK_POWER_STAGE1_8814B) << BIT_SHIFT_POWER_STAGE1_8814B) -#define BIT_GET_POWER_STAGE1_8814B(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8814B) & BIT_MASK_POWER_STAGE1_8814B) - - - -/* 2 REG_POWER_STAGE2_8814B */ -#define BIT__R_CTRL_PKT_POW_ADJ_8814B BIT(24) - -#define BIT_SHIFT_POWER_STAGE2_8814B 0 -#define BIT_MASK_POWER_STAGE2_8814B 0xffffff -#define BIT_POWER_STAGE2_8814B(x) (((x) & BIT_MASK_POWER_STAGE2_8814B) << BIT_SHIFT_POWER_STAGE2_8814B) -#define BIT_GET_POWER_STAGE2_8814B(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8814B) & BIT_MASK_POWER_STAGE2_8814B) - - - -/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8814B */ - -#define BIT_SHIFT_PAD_NUM_THRES_8814B 24 -#define BIT_MASK_PAD_NUM_THRES_8814B 0x3f -#define BIT_PAD_NUM_THRES_8814B(x) (((x) & BIT_MASK_PAD_NUM_THRES_8814B) << BIT_SHIFT_PAD_NUM_THRES_8814B) -#define BIT_GET_PAD_NUM_THRES_8814B(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8814B) & BIT_MASK_PAD_NUM_THRES_8814B) - - -#define BIT_R_DMA_THIS_QUEUE_BK_8814B BIT(23) -#define BIT_R_DMA_THIS_QUEUE_BE_8814B BIT(22) -#define BIT_R_DMA_THIS_QUEUE_VI_8814B BIT(21) -#define BIT_R_DMA_THIS_QUEUE_VO_8814B BIT(20) - -#define BIT_SHIFT_R_TOTAL_LEN_TH_8814B 8 -#define BIT_MASK_R_TOTAL_LEN_TH_8814B 0xfff -#define BIT_R_TOTAL_LEN_TH_8814B(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8814B) << BIT_SHIFT_R_TOTAL_LEN_TH_8814B) -#define BIT_GET_R_TOTAL_LEN_TH_8814B(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8814B) & BIT_MASK_R_TOTAL_LEN_TH_8814B) - - -#define BIT_EN_NEW_EARLY_8814B BIT(7) -#define BIT_PRE_TX_CMD_8814B BIT(6) - -#define BIT_SHIFT_NUM_SCL_EN_8814B 4 -#define BIT_MASK_NUM_SCL_EN_8814B 0x3 -#define BIT_NUM_SCL_EN_8814B(x) (((x) & BIT_MASK_NUM_SCL_EN_8814B) << BIT_SHIFT_NUM_SCL_EN_8814B) -#define BIT_GET_NUM_SCL_EN_8814B(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8814B) & BIT_MASK_NUM_SCL_EN_8814B) - - -#define BIT_BK_EN_8814B BIT(3) -#define BIT_BE_EN_8814B BIT(2) -#define BIT_VI_EN_8814B BIT(1) -#define BIT_VO_EN_8814B BIT(0) - -/* 2 REG_PKT_LIFE_TIME_8814B */ - -#define BIT_SHIFT_PKT_LIFTIME_BEBK_8814B 16 -#define BIT_MASK_PKT_LIFTIME_BEBK_8814B 0xffff -#define BIT_PKT_LIFTIME_BEBK_8814B(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8814B) << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) -#define BIT_GET_PKT_LIFTIME_BEBK_8814B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) & BIT_MASK_PKT_LIFTIME_BEBK_8814B) - - - -#define BIT_SHIFT_PKT_LIFTIME_VOVI_8814B 0 -#define BIT_MASK_PKT_LIFTIME_VOVI_8814B 0xffff -#define BIT_PKT_LIFTIME_VOVI_8814B(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8814B) << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) -#define BIT_GET_PKT_LIFTIME_VOVI_8814B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) & BIT_MASK_PKT_LIFTIME_VOVI_8814B) - - - -/* 2 REG_STBC_SETTING_8814B */ - -#define BIT_SHIFT_CDEND_TXTIME_L_8814B 4 -#define BIT_MASK_CDEND_TXTIME_L_8814B 0xf -#define BIT_CDEND_TXTIME_L_8814B(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8814B) << BIT_SHIFT_CDEND_TXTIME_L_8814B) -#define BIT_GET_CDEND_TXTIME_L_8814B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8814B) & BIT_MASK_CDEND_TXTIME_L_8814B) - - - -#define BIT_SHIFT_NESS_8814B 2 -#define BIT_MASK_NESS_8814B 0x3 -#define BIT_NESS_8814B(x) (((x) & BIT_MASK_NESS_8814B) << BIT_SHIFT_NESS_8814B) -#define BIT_GET_NESS_8814B(x) (((x) >> BIT_SHIFT_NESS_8814B) & BIT_MASK_NESS_8814B) - - - -#define BIT_SHIFT_STBC_CFEND_8814B 0 -#define BIT_MASK_STBC_CFEND_8814B 0x3 -#define BIT_STBC_CFEND_8814B(x) (((x) & BIT_MASK_STBC_CFEND_8814B) << BIT_SHIFT_STBC_CFEND_8814B) -#define BIT_GET_STBC_CFEND_8814B(x) (((x) >> BIT_SHIFT_STBC_CFEND_8814B) & BIT_MASK_STBC_CFEND_8814B) - - - -/* 2 REG_STBC_SETTING2_8814B */ - -#define BIT_SHIFT_CDEND_TXTIME_H_8814B 0 -#define BIT_MASK_CDEND_TXTIME_H_8814B 0x1f -#define BIT_CDEND_TXTIME_H_8814B(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8814B) << BIT_SHIFT_CDEND_TXTIME_H_8814B) -#define BIT_GET_CDEND_TXTIME_H_8814B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8814B) & BIT_MASK_CDEND_TXTIME_H_8814B) - - - -/* 2 REG_QUEUE_CTRL_8814B */ -#define BIT_PTA_EDCCA_EN_8814B BIT(5) -#define BIT_PTA_WL_TX_EN_8814B BIT(4) -#define BIT_R_USE_DATA_BW_8814B BIT(3) -#define BIT_TRI_PKT_INT_MODE1_8814B BIT(2) -#define BIT_TRI_PKT_INT_MODE0_8814B BIT(1) -#define BIT_ACQ_MODE_SEL_8814B BIT(0) - -/* 2 REG_SINGLE_AMPDU_CTRL_8814B */ -#define BIT_EN_SINGLE_APMDU_8814B BIT(7) - -/* 2 REG_PROT_MODE_CTRL_8814B */ - -#define BIT_SHIFT_RTS_MAX_AGG_NUM_8814B 24 -#define BIT_MASK_RTS_MAX_AGG_NUM_8814B 0x3f -#define BIT_RTS_MAX_AGG_NUM_8814B(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8814B) << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) -#define BIT_GET_RTS_MAX_AGG_NUM_8814B(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) & BIT_MASK_RTS_MAX_AGG_NUM_8814B) - - - -#define BIT_SHIFT_MAX_AGG_NUM_8814B 16 -#define BIT_MASK_MAX_AGG_NUM_8814B 0x3f -#define BIT_MAX_AGG_NUM_8814B(x) (((x) & BIT_MASK_MAX_AGG_NUM_8814B) << BIT_SHIFT_MAX_AGG_NUM_8814B) -#define BIT_GET_MAX_AGG_NUM_8814B(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8814B) & BIT_MASK_MAX_AGG_NUM_8814B) - - - -#define BIT_SHIFT_RTS_TXTIME_TH_8814B 8 -#define BIT_MASK_RTS_TXTIME_TH_8814B 0xff -#define BIT_RTS_TXTIME_TH_8814B(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8814B) << BIT_SHIFT_RTS_TXTIME_TH_8814B) -#define BIT_GET_RTS_TXTIME_TH_8814B(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8814B) & BIT_MASK_RTS_TXTIME_TH_8814B) - - - -#define BIT_SHIFT_RTS_LEN_TH_8814B 0 -#define BIT_MASK_RTS_LEN_TH_8814B 0xff -#define BIT_RTS_LEN_TH_8814B(x) (((x) & BIT_MASK_RTS_LEN_TH_8814B) << BIT_SHIFT_RTS_LEN_TH_8814B) -#define BIT_GET_RTS_LEN_TH_8814B(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8814B) & BIT_MASK_RTS_LEN_TH_8814B) - - - -/* 2 REG_BAR_MODE_CTRL_8814B */ - -#define BIT_SHIFT_BAR_RTY_LMT_8814B 16 -#define BIT_MASK_BAR_RTY_LMT_8814B 0x3 -#define BIT_BAR_RTY_LMT_8814B(x) (((x) & BIT_MASK_BAR_RTY_LMT_8814B) << BIT_SHIFT_BAR_RTY_LMT_8814B) -#define BIT_GET_BAR_RTY_LMT_8814B(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8814B) & BIT_MASK_BAR_RTY_LMT_8814B) - - - -#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B 8 -#define BIT_MASK_BAR_PKT_TXTIME_TH_8814B 0xff -#define BIT_BAR_PKT_TXTIME_TH_8814B(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8814B) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) -#define BIT_GET_BAR_PKT_TXTIME_TH_8814B(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) & BIT_MASK_BAR_PKT_TXTIME_TH_8814B) - - -#define BIT_BAR_EN_V1_8814B BIT(6) - -#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B 0 -#define BIT_MASK_BAR_PKTNUM_TH_V1_8814B 0x3f -#define BIT_BAR_PKTNUM_TH_V1_8814B(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8814B) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) -#define BIT_GET_BAR_PKTNUM_TH_V1_8814B(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) & BIT_MASK_BAR_PKTNUM_TH_V1_8814B) - - - -/* 2 REG_RA_TRY_RATE_AGG_LMT_8814B */ - -#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B 0 -#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B 0x3f -#define BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) -#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8814B(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B) - - - -/* 2 REG_MACID_SLEEP2_8814B */ - -#define BIT_SHIFT_MACID95_64PKTSLEEP_8814B 0 -#define BIT_MASK_MACID95_64PKTSLEEP_8814B 0xffffffffL -#define BIT_MACID95_64PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8814B) << BIT_SHIFT_MACID95_64PKTSLEEP_8814B) -#define BIT_GET_MACID95_64PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8814B) & BIT_MASK_MACID95_64PKTSLEEP_8814B) - - - -/* 2 REG_MACID_SLEEP_8814B */ - -#define BIT_SHIFT_MACID31_0_PKTSLEEP_8814B 0 -#define BIT_MASK_MACID31_0_PKTSLEEP_8814B 0xffffffffL -#define BIT_MACID31_0_PKTSLEEP_8814B(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8814B) << BIT_SHIFT_MACID31_0_PKTSLEEP_8814B) -#define BIT_GET_MACID31_0_PKTSLEEP_8814B(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8814B) & BIT_MASK_MACID31_0_PKTSLEEP_8814B) - - - -/* 2 REG_HW_SEQ0_8814B */ - -#define BIT_SHIFT_HW_SSN_SEQ0_8814B 0 -#define BIT_MASK_HW_SSN_SEQ0_8814B 0xfff -#define BIT_HW_SSN_SEQ0_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8814B) << BIT_SHIFT_HW_SSN_SEQ0_8814B) -#define BIT_GET_HW_SSN_SEQ0_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8814B) & BIT_MASK_HW_SSN_SEQ0_8814B) - - - -/* 2 REG_HW_SEQ1_8814B */ - -#define BIT_SHIFT_HW_SSN_SEQ1_8814B 0 -#define BIT_MASK_HW_SSN_SEQ1_8814B 0xfff -#define BIT_HW_SSN_SEQ1_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8814B) << BIT_SHIFT_HW_SSN_SEQ1_8814B) -#define BIT_GET_HW_SSN_SEQ1_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8814B) & BIT_MASK_HW_SSN_SEQ1_8814B) - - - -/* 2 REG_HW_SEQ2_8814B */ - -#define BIT_SHIFT_HW_SSN_SEQ2_8814B 0 -#define BIT_MASK_HW_SSN_SEQ2_8814B 0xfff -#define BIT_HW_SSN_SEQ2_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8814B) << BIT_SHIFT_HW_SSN_SEQ2_8814B) -#define BIT_GET_HW_SSN_SEQ2_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8814B) & BIT_MASK_HW_SSN_SEQ2_8814B) - - - -/* 2 REG_HW_SEQ3_8814B */ - -#define BIT_SHIFT_HW_SSN_SEQ3_8814B 0 -#define BIT_MASK_HW_SSN_SEQ3_8814B 0xfff -#define BIT_HW_SSN_SEQ3_8814B(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8814B) << BIT_SHIFT_HW_SSN_SEQ3_8814B) -#define BIT_GET_HW_SSN_SEQ3_8814B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8814B) & BIT_MASK_HW_SSN_SEQ3_8814B) - - - -/* 2 REG_NULL_PKT_STATUS_V1_8814B */ - -#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8814B 2 -#define BIT_MASK_PTCL_TOTAL_PG_V2_8814B 0x3fff -#define BIT_PTCL_TOTAL_PG_V2_8814B(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8814B) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8814B) -#define BIT_GET_PTCL_TOTAL_PG_V2_8814B(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8814B) & BIT_MASK_PTCL_TOTAL_PG_V2_8814B) - - -#define BIT_TX_NULL_1_8814B BIT(1) -#define BIT_TX_NULL_0_8814B BIT(0) - -/* 2 REG_PTCL_ERR_STATUS_8814B */ -#define BIT_PTCL_RATE_TABLE_INVALID_8814B BIT(7) -#define BIT_FTM_T2R_ERROR_8814B BIT(6) -#define BIT_PTCL_ERR0_8814B BIT(5) -#define BIT_PTCL_ERR1_8814B BIT(4) -#define BIT_PTCL_ERR2_8814B BIT(3) -#define BIT_PTCL_ERR3_8814B BIT(2) -#define BIT_PTCL_ERR4_8814B BIT(1) -#define BIT_PTCL_ERR5_8814B BIT(0) - -/* 2 REG_NULL_PKT_STATUS_EXTEND_8814B */ -#define BIT_CLI3_TX_NULL_1_8814B BIT(7) -#define BIT_CLI3_TX_NULL_0_8814B BIT(6) -#define BIT_CLI2_TX_NULL_1_8814B BIT(5) -#define BIT_CLI2_TX_NULL_0_8814B BIT(4) -#define BIT_CLI1_TX_NULL_1_8814B BIT(3) -#define BIT_CLI1_TX_NULL_0_8814B BIT(2) -#define BIT_CLI0_TX_NULL_1_8814B BIT(1) -#define BIT_CLI0_TX_NULL_0_8814B BIT(0) - -/* 2 REG_VIDEO_ENHANCEMENT_FUN_8814B */ -#define BIT_VIDEO_JUST_DROP_8814B BIT(1) -#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8814B BIT(0) - -/* 2 REG_BT_POLLUTE_PKT_CNT_8814B */ - -#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8814B 0 -#define BIT_MASK_BT_POLLUTE_PKT_CNT_8814B 0xffff -#define BIT_BT_POLLUTE_PKT_CNT_8814B(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8814B) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8814B) -#define BIT_GET_BT_POLLUTE_PKT_CNT_8814B(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8814B) & BIT_MASK_BT_POLLUTE_PKT_CNT_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_PTCL_DBG_8814B */ - -#define BIT_SHIFT_PTCL_DBG_8814B 0 -#define BIT_MASK_PTCL_DBG_8814B 0xffffffffL -#define BIT_PTCL_DBG_8814B(x) (((x) & BIT_MASK_PTCL_DBG_8814B) << BIT_SHIFT_PTCL_DBG_8814B) -#define BIT_GET_PTCL_DBG_8814B(x) (((x) >> BIT_SHIFT_PTCL_DBG_8814B) & BIT_MASK_PTCL_DBG_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_CPUMGQ_TIMER_CTRL2_8814B */ - -#define BIT_SHIFT_TRI_HEAD_ADDR_8814B 16 -#define BIT_MASK_TRI_HEAD_ADDR_8814B 0xfff -#define BIT_TRI_HEAD_ADDR_8814B(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8814B) << BIT_SHIFT_TRI_HEAD_ADDR_8814B) -#define BIT_GET_TRI_HEAD_ADDR_8814B(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8814B) & BIT_MASK_TRI_HEAD_ADDR_8814B) - - -#define BIT_DROP_TH_EN_8814B BIT(8) - -#define BIT_SHIFT_DROP_TH_8814B 0 -#define BIT_MASK_DROP_TH_8814B 0xff -#define BIT_DROP_TH_8814B(x) (((x) & BIT_MASK_DROP_TH_8814B) << BIT_SHIFT_DROP_TH_8814B) -#define BIT_GET_DROP_TH_8814B(x) (((x) >> BIT_SHIFT_DROP_TH_8814B) & BIT_MASK_DROP_TH_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_DUMMY_PAGE4_V1_8814B */ - -/* 2 REG_MOREDATA_8814B */ -#define BIT_MOREDATA_CTRL2_EN_V1_8814B BIT(3) -#define BIT_MOREDATA_CTRL1_EN_V1_8814B BIT(2) -#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8814B BIT(0) - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_Q0_Q1_INFO_8814B */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) - -#define BIT_SHIFT_GTAB_ID_8814B 28 -#define BIT_MASK_GTAB_ID_8814B 0x7 -#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) -#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) - - - -#define BIT_SHIFT_AC1_PKT_INFO_8814B 16 -#define BIT_MASK_AC1_PKT_INFO_8814B 0xfff -#define BIT_AC1_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC1_PKT_INFO_8814B) << BIT_SHIFT_AC1_PKT_INFO_8814B) -#define BIT_GET_AC1_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8814B) & BIT_MASK_AC1_PKT_INFO_8814B) - - -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) - -#define BIT_SHIFT_GTAB_ID_V1_8814B 12 -#define BIT_MASK_GTAB_ID_V1_8814B 0x7 -#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) -#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) - - - -#define BIT_SHIFT_AC0_PKT_INFO_8814B 0 -#define BIT_MASK_AC0_PKT_INFO_8814B 0xfff -#define BIT_AC0_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC0_PKT_INFO_8814B) << BIT_SHIFT_AC0_PKT_INFO_8814B) -#define BIT_GET_AC0_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8814B) & BIT_MASK_AC0_PKT_INFO_8814B) - - - -/* 2 REG_Q2_Q3_INFO_8814B */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) - -#define BIT_SHIFT_GTAB_ID_8814B 28 -#define BIT_MASK_GTAB_ID_8814B 0x7 -#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) -#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) - - - -#define BIT_SHIFT_AC3_PKT_INFO_8814B 16 -#define BIT_MASK_AC3_PKT_INFO_8814B 0xfff -#define BIT_AC3_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC3_PKT_INFO_8814B) << BIT_SHIFT_AC3_PKT_INFO_8814B) -#define BIT_GET_AC3_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8814B) & BIT_MASK_AC3_PKT_INFO_8814B) - - -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) - -#define BIT_SHIFT_GTAB_ID_V1_8814B 12 -#define BIT_MASK_GTAB_ID_V1_8814B 0x7 -#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) -#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) - - - -#define BIT_SHIFT_AC2_PKT_INFO_8814B 0 -#define BIT_MASK_AC2_PKT_INFO_8814B 0xfff -#define BIT_AC2_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC2_PKT_INFO_8814B) << BIT_SHIFT_AC2_PKT_INFO_8814B) -#define BIT_GET_AC2_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8814B) & BIT_MASK_AC2_PKT_INFO_8814B) - - - -/* 2 REG_Q4_Q5_INFO_8814B */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) - -#define BIT_SHIFT_GTAB_ID_8814B 28 -#define BIT_MASK_GTAB_ID_8814B 0x7 -#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) -#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) - - - -#define BIT_SHIFT_AC5_PKT_INFO_8814B 16 -#define BIT_MASK_AC5_PKT_INFO_8814B 0xfff -#define BIT_AC5_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC5_PKT_INFO_8814B) << BIT_SHIFT_AC5_PKT_INFO_8814B) -#define BIT_GET_AC5_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8814B) & BIT_MASK_AC5_PKT_INFO_8814B) - - -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) - -#define BIT_SHIFT_GTAB_ID_V1_8814B 12 -#define BIT_MASK_GTAB_ID_V1_8814B 0x7 -#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) -#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) - - - -#define BIT_SHIFT_AC4_PKT_INFO_8814B 0 -#define BIT_MASK_AC4_PKT_INFO_8814B 0xfff -#define BIT_AC4_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC4_PKT_INFO_8814B) << BIT_SHIFT_AC4_PKT_INFO_8814B) -#define BIT_GET_AC4_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8814B) & BIT_MASK_AC4_PKT_INFO_8814B) - - - -/* 2 REG_Q6_Q7_INFO_8814B */ -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8814B BIT(31) - -#define BIT_SHIFT_GTAB_ID_8814B 28 -#define BIT_MASK_GTAB_ID_8814B 0x7 -#define BIT_GTAB_ID_8814B(x) (((x) & BIT_MASK_GTAB_ID_8814B) << BIT_SHIFT_GTAB_ID_8814B) -#define BIT_GET_GTAB_ID_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_8814B) & BIT_MASK_GTAB_ID_8814B) - - - -#define BIT_SHIFT_AC7_PKT_INFO_8814B 16 -#define BIT_MASK_AC7_PKT_INFO_8814B 0xfff -#define BIT_AC7_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC7_PKT_INFO_8814B) << BIT_SHIFT_AC7_PKT_INFO_8814B) -#define BIT_GET_AC7_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8814B) & BIT_MASK_AC7_PKT_INFO_8814B) - - -#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8814B BIT(15) - -#define BIT_SHIFT_GTAB_ID_V1_8814B 12 -#define BIT_MASK_GTAB_ID_V1_8814B 0x7 -#define BIT_GTAB_ID_V1_8814B(x) (((x) & BIT_MASK_GTAB_ID_V1_8814B) << BIT_SHIFT_GTAB_ID_V1_8814B) -#define BIT_GET_GTAB_ID_V1_8814B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8814B) & BIT_MASK_GTAB_ID_V1_8814B) - - - -#define BIT_SHIFT_AC6_PKT_INFO_8814B 0 -#define BIT_MASK_AC6_PKT_INFO_8814B 0xfff -#define BIT_AC6_PKT_INFO_8814B(x) (((x) & BIT_MASK_AC6_PKT_INFO_8814B) << BIT_SHIFT_AC6_PKT_INFO_8814B) -#define BIT_GET_AC6_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8814B) & BIT_MASK_AC6_PKT_INFO_8814B) - - - -/* 2 REG_MGQ_HIQ_INFO_8814B */ - -#define BIT_SHIFT_HIQ_PKT_INFO_8814B 16 -#define BIT_MASK_HIQ_PKT_INFO_8814B 0xfff -#define BIT_HIQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8814B) << BIT_SHIFT_HIQ_PKT_INFO_8814B) -#define BIT_GET_HIQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8814B) & BIT_MASK_HIQ_PKT_INFO_8814B) - - - -#define BIT_SHIFT_MGQ_PKT_INFO_8814B 0 -#define BIT_MASK_MGQ_PKT_INFO_8814B 0xfff -#define BIT_MGQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8814B) << BIT_SHIFT_MGQ_PKT_INFO_8814B) -#define BIT_GET_MGQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8814B) & BIT_MASK_MGQ_PKT_INFO_8814B) - - - -/* 2 REG_CMDQ_BCNQ_INFO_8814B */ - -#define BIT_SHIFT_CMDQ_PKT_INFO_8814B 16 -#define BIT_MASK_CMDQ_PKT_INFO_8814B 0xfff -#define BIT_CMDQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_8814B) << BIT_SHIFT_CMDQ_PKT_INFO_8814B) -#define BIT_GET_CMDQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8814B) & BIT_MASK_CMDQ_PKT_INFO_8814B) - - - -#define BIT_SHIFT_BCNQ_PKT_INFO_8814B 0 -#define BIT_MASK_BCNQ_PKT_INFO_8814B 0xfff -#define BIT_BCNQ_PKT_INFO_8814B(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8814B) << BIT_SHIFT_BCNQ_PKT_INFO_8814B) -#define BIT_GET_BCNQ_PKT_INFO_8814B(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8814B) & BIT_MASK_BCNQ_PKT_INFO_8814B) - - - -/* 2 REG_USEREG_SETTING_8814B */ -#define BIT_NDPA_USEREG_8814B BIT(21) - -#define BIT_SHIFT_RETRY_USEREG_8814B 19 -#define BIT_MASK_RETRY_USEREG_8814B 0x3 -#define BIT_RETRY_USEREG_8814B(x) (((x) & BIT_MASK_RETRY_USEREG_8814B) << BIT_SHIFT_RETRY_USEREG_8814B) -#define BIT_GET_RETRY_USEREG_8814B(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8814B) & BIT_MASK_RETRY_USEREG_8814B) - - - -#define BIT_SHIFT_TRYPKT_USEREG_8814B 17 -#define BIT_MASK_TRYPKT_USEREG_8814B 0x3 -#define BIT_TRYPKT_USEREG_8814B(x) (((x) & BIT_MASK_TRYPKT_USEREG_8814B) << BIT_SHIFT_TRYPKT_USEREG_8814B) -#define BIT_GET_TRYPKT_USEREG_8814B(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8814B) & BIT_MASK_TRYPKT_USEREG_8814B) - - -#define BIT_CTLPKT_USEREG_8814B BIT(16) - -/* 2 REG_AESIV_SETTING_8814B */ - -#define BIT_SHIFT_AESIV_OFFSET_8814B 0 -#define BIT_MASK_AESIV_OFFSET_8814B 0xfff -#define BIT_AESIV_OFFSET_8814B(x) (((x) & BIT_MASK_AESIV_OFFSET_8814B) << BIT_SHIFT_AESIV_OFFSET_8814B) -#define BIT_GET_AESIV_OFFSET_8814B(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8814B) & BIT_MASK_AESIV_OFFSET_8814B) - - - -/* 2 REG_BF0_TIME_SETTING_8814B */ -#define BIT_BF0_TIMER_SET_8814B BIT(31) -#define BIT_BF0_TIMER_CLR_8814B BIT(30) -#define BIT_BF0_UPDATE_EN_8814B BIT(29) -#define BIT_BF0_TIMER_EN_8814B BIT(28) - -#define BIT_SHIFT_BF0_PRETIME_OVER_8814B 16 -#define BIT_MASK_BF0_PRETIME_OVER_8814B 0xfff -#define BIT_BF0_PRETIME_OVER_8814B(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8814B) << BIT_SHIFT_BF0_PRETIME_OVER_8814B) -#define BIT_GET_BF0_PRETIME_OVER_8814B(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8814B) & BIT_MASK_BF0_PRETIME_OVER_8814B) - - - -#define BIT_SHIFT_BF0_LIFETIME_8814B 0 -#define BIT_MASK_BF0_LIFETIME_8814B 0xffff -#define BIT_BF0_LIFETIME_8814B(x) (((x) & BIT_MASK_BF0_LIFETIME_8814B) << BIT_SHIFT_BF0_LIFETIME_8814B) -#define BIT_GET_BF0_LIFETIME_8814B(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8814B) & BIT_MASK_BF0_LIFETIME_8814B) - - - -/* 2 REG_BF1_TIME_SETTING_8814B */ -#define BIT_BF1_TIMER_SET_8814B BIT(31) -#define BIT_BF1_TIMER_CLR_8814B BIT(30) -#define BIT_BF1_UPDATE_EN_8814B BIT(29) -#define BIT_BF1_TIMER_EN_8814B BIT(28) - -#define BIT_SHIFT_BF1_PRETIME_OVER_8814B 16 -#define BIT_MASK_BF1_PRETIME_OVER_8814B 0xfff -#define BIT_BF1_PRETIME_OVER_8814B(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8814B) << BIT_SHIFT_BF1_PRETIME_OVER_8814B) -#define BIT_GET_BF1_PRETIME_OVER_8814B(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8814B) & BIT_MASK_BF1_PRETIME_OVER_8814B) - - - -#define BIT_SHIFT_BF1_LIFETIME_8814B 0 -#define BIT_MASK_BF1_LIFETIME_8814B 0xffff -#define BIT_BF1_LIFETIME_8814B(x) (((x) & BIT_MASK_BF1_LIFETIME_8814B) << BIT_SHIFT_BF1_LIFETIME_8814B) -#define BIT_GET_BF1_LIFETIME_8814B(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8814B) & BIT_MASK_BF1_LIFETIME_8814B) - - - -/* 2 REG_BF_TIMEOUT_EN_8814B */ -#define BIT_EN_VHT_LDPC_8814B BIT(9) -#define BIT_EN_HT_LDPC_8814B BIT(8) -#define BIT_BF1_TIMEOUT_EN_8814B BIT(1) -#define BIT_BF0_TIMEOUT_EN_8814B BIT(0) - -/* 2 REG_MACID_RELEASE0_8814B */ - -#define BIT_SHIFT_MACID31_0_RELEASE_8814B 0 -#define BIT_MASK_MACID31_0_RELEASE_8814B 0xffffffffL -#define BIT_MACID31_0_RELEASE_8814B(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8814B) << BIT_SHIFT_MACID31_0_RELEASE_8814B) -#define BIT_GET_MACID31_0_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8814B) & BIT_MASK_MACID31_0_RELEASE_8814B) - - - -/* 2 REG_MACID_RELEASE1_8814B */ - -#define BIT_SHIFT_MACID63_32_RELEASE_8814B 0 -#define BIT_MASK_MACID63_32_RELEASE_8814B 0xffffffffL -#define BIT_MACID63_32_RELEASE_8814B(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8814B) << BIT_SHIFT_MACID63_32_RELEASE_8814B) -#define BIT_GET_MACID63_32_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8814B) & BIT_MASK_MACID63_32_RELEASE_8814B) - - - -/* 2 REG_MACID_RELEASE2_8814B */ - -#define BIT_SHIFT_MACID95_64_RELEASE_8814B 0 -#define BIT_MASK_MACID95_64_RELEASE_8814B 0xffffffffL -#define BIT_MACID95_64_RELEASE_8814B(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8814B) << BIT_SHIFT_MACID95_64_RELEASE_8814B) -#define BIT_GET_MACID95_64_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8814B) & BIT_MASK_MACID95_64_RELEASE_8814B) - - - -/* 2 REG_MACID_RELEASE3_8814B */ - -#define BIT_SHIFT_MACID127_96_RELEASE_8814B 0 -#define BIT_MASK_MACID127_96_RELEASE_8814B 0xffffffffL -#define BIT_MACID127_96_RELEASE_8814B(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8814B) << BIT_SHIFT_MACID127_96_RELEASE_8814B) -#define BIT_GET_MACID127_96_RELEASE_8814B(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8814B) & BIT_MASK_MACID127_96_RELEASE_8814B) - - - -/* 2 REG_MACID_RELEASE_SETTING_8814B */ -#define BIT_MACID_VALUE_8814B BIT(7) - -#define BIT_SHIFT_MACID_OFFSET_8814B 0 -#define BIT_MASK_MACID_OFFSET_8814B 0x7f -#define BIT_MACID_OFFSET_8814B(x) (((x) & BIT_MASK_MACID_OFFSET_8814B) << BIT_SHIFT_MACID_OFFSET_8814B) -#define BIT_GET_MACID_OFFSET_8814B(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8814B) & BIT_MASK_MACID_OFFSET_8814B) - - - -/* 2 REG_FAST_EDCA_VOVI_SETTING_8814B */ - -#define BIT_SHIFT_VI_FAST_EDCA_TO_8814B 24 -#define BIT_MASK_VI_FAST_EDCA_TO_8814B 0xff -#define BIT_VI_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8814B) << BIT_SHIFT_VI_FAST_EDCA_TO_8814B) -#define BIT_GET_VI_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8814B) & BIT_MASK_VI_FAST_EDCA_TO_8814B) - - -#define BIT_VI_THRESHOLD_SEL_8814B BIT(23) - -#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B 16 -#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B 0x7f -#define BIT_VI_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) -#define BIT_GET_VI_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B) - - - -#define BIT_SHIFT_VO_FAST_EDCA_TO_8814B 8 -#define BIT_MASK_VO_FAST_EDCA_TO_8814B 0xff -#define BIT_VO_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8814B) << BIT_SHIFT_VO_FAST_EDCA_TO_8814B) -#define BIT_GET_VO_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8814B) & BIT_MASK_VO_FAST_EDCA_TO_8814B) - - -#define BIT_VO_THRESHOLD_SEL_8814B BIT(7) - -#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B 0 -#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B 0x7f -#define BIT_VO_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) -#define BIT_GET_VO_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B) - - - -/* 2 REG_FAST_EDCA_BEBK_SETTING_8814B */ - -#define BIT_SHIFT_BK_FAST_EDCA_TO_8814B 24 -#define BIT_MASK_BK_FAST_EDCA_TO_8814B 0xff -#define BIT_BK_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8814B) << BIT_SHIFT_BK_FAST_EDCA_TO_8814B) -#define BIT_GET_BK_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8814B) & BIT_MASK_BK_FAST_EDCA_TO_8814B) - - -#define BIT_BK_THRESHOLD_SEL_8814B BIT(23) - -#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B 16 -#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B 0x7f -#define BIT_BK_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) -#define BIT_GET_BK_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B) - - - -#define BIT_SHIFT_BE_FAST_EDCA_TO_8814B 8 -#define BIT_MASK_BE_FAST_EDCA_TO_8814B 0xff -#define BIT_BE_FAST_EDCA_TO_8814B(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8814B) << BIT_SHIFT_BE_FAST_EDCA_TO_8814B) -#define BIT_GET_BE_FAST_EDCA_TO_8814B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8814B) & BIT_MASK_BE_FAST_EDCA_TO_8814B) - - -#define BIT_BE_THRESHOLD_SEL_8814B BIT(7) - -#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B 0 -#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B 0x7f -#define BIT_BE_FAST_EDCA_PKT_TH_8814B(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) -#define BIT_GET_BE_FAST_EDCA_PKT_TH_8814B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B) - - - -/* 2 REG_MACID_DROP0_8814B */ - -#define BIT_SHIFT_MACID31_0_DROP_8814B 0 -#define BIT_MASK_MACID31_0_DROP_8814B 0xffffffffL -#define BIT_MACID31_0_DROP_8814B(x) (((x) & BIT_MASK_MACID31_0_DROP_8814B) << BIT_SHIFT_MACID31_0_DROP_8814B) -#define BIT_GET_MACID31_0_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8814B) & BIT_MASK_MACID31_0_DROP_8814B) - - - -/* 2 REG_MACID_DROP1_8814B */ - -#define BIT_SHIFT_MACID63_32_DROP_8814B 0 -#define BIT_MASK_MACID63_32_DROP_8814B 0xffffffffL -#define BIT_MACID63_32_DROP_8814B(x) (((x) & BIT_MASK_MACID63_32_DROP_8814B) << BIT_SHIFT_MACID63_32_DROP_8814B) -#define BIT_GET_MACID63_32_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8814B) & BIT_MASK_MACID63_32_DROP_8814B) - - - -/* 2 REG_MACID_DROP2_8814B */ +/* 2 REG_POWER_STAGE1_8814B */ +#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8814B BIT(31) +#define BIT_PTA_WL_PRI_MASK_BCNQ_8814B BIT(30) +#define BIT_PTA_WL_PRI_MASK_HIQ_8814B BIT(29) +#define BIT_PTA_WL_PRI_MASK_MGQ_8814B BIT(28) +#define BIT_PTA_WL_PRI_MASK_BK_8814B BIT(27) +#define BIT_PTA_WL_PRI_MASK_BE_8814B BIT(26) +#define BIT_PTA_WL_PRI_MASK_VI_8814B BIT(25) +#define BIT_PTA_WL_PRI_MASK_VO_8814B BIT(24) -#define BIT_SHIFT_MACID95_64_DROP_8814B 0 -#define BIT_MASK_MACID95_64_DROP_8814B 0xffffffffL -#define BIT_MACID95_64_DROP_8814B(x) (((x) & BIT_MASK_MACID95_64_DROP_8814B) << BIT_SHIFT_MACID95_64_DROP_8814B) -#define BIT_GET_MACID95_64_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8814B) & BIT_MASK_MACID95_64_DROP_8814B) +#define BIT_SHIFT_POWER_STAGE1_8814B 0 +#define BIT_MASK_POWER_STAGE1_8814B 0xffffff +#define BIT_POWER_STAGE1_8814B(x) \ + (((x) & BIT_MASK_POWER_STAGE1_8814B) << BIT_SHIFT_POWER_STAGE1_8814B) +#define BITS_POWER_STAGE1_8814B \ + (BIT_MASK_POWER_STAGE1_8814B << BIT_SHIFT_POWER_STAGE1_8814B) +#define BIT_CLEAR_POWER_STAGE1_8814B(x) ((x) & (~BITS_POWER_STAGE1_8814B)) +#define BIT_GET_POWER_STAGE1_8814B(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1_8814B) & BIT_MASK_POWER_STAGE1_8814B) +#define BIT_SET_POWER_STAGE1_8814B(x, v) \ + (BIT_CLEAR_POWER_STAGE1_8814B(x) | BIT_POWER_STAGE1_8814B(v)) +/* 2 REG_POWER_STAGE2_8814B */ +#define BIT__CTRL_PKT_POW_ADJ_8814B BIT(24) +#define BIT_SHIFT_POWER_STAGE2_8814B 0 +#define BIT_MASK_POWER_STAGE2_8814B 0xffffff +#define BIT_POWER_STAGE2_8814B(x) \ + (((x) & BIT_MASK_POWER_STAGE2_8814B) << BIT_SHIFT_POWER_STAGE2_8814B) +#define BITS_POWER_STAGE2_8814B \ + (BIT_MASK_POWER_STAGE2_8814B << BIT_SHIFT_POWER_STAGE2_8814B) +#define BIT_CLEAR_POWER_STAGE2_8814B(x) ((x) & (~BITS_POWER_STAGE2_8814B)) +#define BIT_GET_POWER_STAGE2_8814B(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2_8814B) & BIT_MASK_POWER_STAGE2_8814B) +#define BIT_SET_POWER_STAGE2_8814B(x, v) \ + (BIT_CLEAR_POWER_STAGE2_8814B(x) | BIT_POWER_STAGE2_8814B(v)) -/* 2 REG_MACID_DROP3_8814B */ +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8814B */ +#define BIT_DMA_THIS_QUEUE_BK_8814B BIT(23) +#define BIT_DMA_THIS_QUEUE_BE_8814B BIT(22) +#define BIT_DMA_THIS_QUEUE_VI_8814B BIT(21) +#define BIT_DMA_THIS_QUEUE_VO_8814B BIT(20) + +#define BIT_SHIFT_TOTAL_LEN_TH_8814B 8 +#define BIT_MASK_TOTAL_LEN_TH_8814B 0xfff +#define BIT_TOTAL_LEN_TH_8814B(x) \ + (((x) & BIT_MASK_TOTAL_LEN_TH_8814B) << BIT_SHIFT_TOTAL_LEN_TH_8814B) +#define BITS_TOTAL_LEN_TH_8814B \ + (BIT_MASK_TOTAL_LEN_TH_8814B << BIT_SHIFT_TOTAL_LEN_TH_8814B) +#define BIT_CLEAR_TOTAL_LEN_TH_8814B(x) ((x) & (~BITS_TOTAL_LEN_TH_8814B)) +#define BIT_GET_TOTAL_LEN_TH_8814B(x) \ + (((x) >> BIT_SHIFT_TOTAL_LEN_TH_8814B) & BIT_MASK_TOTAL_LEN_TH_8814B) +#define BIT_SET_TOTAL_LEN_TH_8814B(x, v) \ + (BIT_CLEAR_TOTAL_LEN_TH_8814B(x) | BIT_TOTAL_LEN_TH_8814B(v)) -#define BIT_SHIFT_MACID127_96_DROP_8814B 0 -#define BIT_MASK_MACID127_96_DROP_8814B 0xffffffffL -#define BIT_MACID127_96_DROP_8814B(x) (((x) & BIT_MASK_MACID127_96_DROP_8814B) << BIT_SHIFT_MACID127_96_DROP_8814B) -#define BIT_GET_MACID127_96_DROP_8814B(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8814B) & BIT_MASK_MACID127_96_DROP_8814B) +#define BIT_PRE_TX_CMD_8814B BIT(6) +#define BIT_SHIFT_NUM_SCL_EN_8814B 4 +#define BIT_MASK_NUM_SCL_EN_8814B 0x3 +#define BIT_NUM_SCL_EN_8814B(x) \ + (((x) & BIT_MASK_NUM_SCL_EN_8814B) << BIT_SHIFT_NUM_SCL_EN_8814B) +#define BITS_NUM_SCL_EN_8814B \ + (BIT_MASK_NUM_SCL_EN_8814B << BIT_SHIFT_NUM_SCL_EN_8814B) +#define BIT_CLEAR_NUM_SCL_EN_8814B(x) ((x) & (~BITS_NUM_SCL_EN_8814B)) +#define BIT_GET_NUM_SCL_EN_8814B(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN_8814B) & BIT_MASK_NUM_SCL_EN_8814B) +#define BIT_SET_NUM_SCL_EN_8814B(x, v) \ + (BIT_CLEAR_NUM_SCL_EN_8814B(x) | BIT_NUM_SCL_EN_8814B(v)) +#define BIT_BK_EN_8814B BIT(3) +#define BIT_BE_EN_8814B BIT(2) +#define BIT_VI_EN_8814B BIT(1) +#define BIT_VO_EN_8814B BIT(0) -/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8814B */ +/* 2 REG_PKT_LIFE_TIME_8814B */ -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8814B 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8814B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_0_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8814B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8814B) +#define BIT_SHIFT_PKT_LIFTIME_BEBK_8814B 16 +#define BIT_MASK_PKT_LIFTIME_BEBK_8814B 0xffff +#define BIT_PKT_LIFTIME_BEBK_8814B(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8814B) \ + << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) +#define BITS_PKT_LIFTIME_BEBK_8814B \ + (BIT_MASK_PKT_LIFTIME_BEBK_8814B << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) +#define BIT_CLEAR_PKT_LIFTIME_BEBK_8814B(x) \ + ((x) & (~BITS_PKT_LIFTIME_BEBK_8814B)) +#define BIT_GET_PKT_LIFTIME_BEBK_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) & \ + BIT_MASK_PKT_LIFTIME_BEBK_8814B) +#define BIT_SET_PKT_LIFTIME_BEBK_8814B(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK_8814B(x) | BIT_PKT_LIFTIME_BEBK_8814B(v)) +#define BIT_SHIFT_PKT_LIFTIME_VOVI_8814B 0 +#define BIT_MASK_PKT_LIFTIME_VOVI_8814B 0xffff +#define BIT_PKT_LIFTIME_VOVI_8814B(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8814B) \ + << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) +#define BITS_PKT_LIFTIME_VOVI_8814B \ + (BIT_MASK_PKT_LIFTIME_VOVI_8814B << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) +#define BIT_CLEAR_PKT_LIFTIME_VOVI_8814B(x) \ + ((x) & (~BITS_PKT_LIFTIME_VOVI_8814B)) +#define BIT_GET_PKT_LIFTIME_VOVI_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) & \ + BIT_MASK_PKT_LIFTIME_VOVI_8814B) +#define BIT_SET_PKT_LIFTIME_VOVI_8814B(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI_8814B(x) | BIT_PKT_LIFTIME_VOVI_8814B(v)) +/* 2 REG_STBC_SETTING_8814B */ -/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8814B */ +#define BIT_SHIFT_CDEND_TXTIME_L_8814B 4 +#define BIT_MASK_CDEND_TXTIME_L_8814B 0xf +#define BIT_CDEND_TXTIME_L_8814B(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L_8814B) \ + << BIT_SHIFT_CDEND_TXTIME_L_8814B) +#define BITS_CDEND_TXTIME_L_8814B \ + (BIT_MASK_CDEND_TXTIME_L_8814B << BIT_SHIFT_CDEND_TXTIME_L_8814B) +#define BIT_CLEAR_CDEND_TXTIME_L_8814B(x) ((x) & (~BITS_CDEND_TXTIME_L_8814B)) +#define BIT_GET_CDEND_TXTIME_L_8814B(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8814B) & \ + BIT_MASK_CDEND_TXTIME_L_8814B) +#define BIT_SET_CDEND_TXTIME_L_8814B(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L_8814B(x) | BIT_CDEND_TXTIME_L_8814B(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8814B 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8814B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_1_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8814B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8814B) +#define BIT_SHIFT_NESS_8814B 2 +#define BIT_MASK_NESS_8814B 0x3 +#define BIT_NESS_8814B(x) (((x) & BIT_MASK_NESS_8814B) << BIT_SHIFT_NESS_8814B) +#define BITS_NESS_8814B (BIT_MASK_NESS_8814B << BIT_SHIFT_NESS_8814B) +#define BIT_CLEAR_NESS_8814B(x) ((x) & (~BITS_NESS_8814B)) +#define BIT_GET_NESS_8814B(x) \ + (((x) >> BIT_SHIFT_NESS_8814B) & BIT_MASK_NESS_8814B) +#define BIT_SET_NESS_8814B(x, v) (BIT_CLEAR_NESS_8814B(x) | BIT_NESS_8814B(v)) +#define BIT_SHIFT_STBC_CFEND_8814B 0 +#define BIT_MASK_STBC_CFEND_8814B 0x3 +#define BIT_STBC_CFEND_8814B(x) \ + (((x) & BIT_MASK_STBC_CFEND_8814B) << BIT_SHIFT_STBC_CFEND_8814B) +#define BITS_STBC_CFEND_8814B \ + (BIT_MASK_STBC_CFEND_8814B << BIT_SHIFT_STBC_CFEND_8814B) +#define BIT_CLEAR_STBC_CFEND_8814B(x) ((x) & (~BITS_STBC_CFEND_8814B)) +#define BIT_GET_STBC_CFEND_8814B(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_8814B) & BIT_MASK_STBC_CFEND_8814B) +#define BIT_SET_STBC_CFEND_8814B(x, v) \ + (BIT_CLEAR_STBC_CFEND_8814B(x) | BIT_STBC_CFEND_8814B(v)) +/* 2 REG_STBC_SETTING2_8814B */ -/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8814B */ +#define BIT_SHIFT_CDEND_TXTIME_H_8814B 0 +#define BIT_MASK_CDEND_TXTIME_H_8814B 0x1f +#define BIT_CDEND_TXTIME_H_8814B(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H_8814B) \ + << BIT_SHIFT_CDEND_TXTIME_H_8814B) +#define BITS_CDEND_TXTIME_H_8814B \ + (BIT_MASK_CDEND_TXTIME_H_8814B << BIT_SHIFT_CDEND_TXTIME_H_8814B) +#define BIT_CLEAR_CDEND_TXTIME_H_8814B(x) ((x) & (~BITS_CDEND_TXTIME_H_8814B)) +#define BIT_GET_CDEND_TXTIME_H_8814B(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8814B) & \ + BIT_MASK_CDEND_TXTIME_H_8814B) +#define BIT_SET_CDEND_TXTIME_H_8814B(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H_8814B(x) | BIT_CDEND_TXTIME_H_8814B(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8814B 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8814B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_2_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8814B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8814B) +/* 2 REG_QUEUE_CTRL_8814B */ +#define BIT_FORCE_RND_PRI_8814B BIT(6) +#define BIT_PTA_EDCCA_EN_8814B BIT(5) +#define BIT_PTA_WL_TX_EN_8814B BIT(4) +#define BIT_USE_DATA_BW_8814B BIT(3) +#define BIT_TRI_PKT_INT_MODE1_8814B BIT(2) +#define BIT_TRI_PKT_INT_MODE0_8814B BIT(1) +#define BIT_ACQ_MODE_SEL_8814B BIT(0) +/* 2 REG_SINGLE_AMPDU_CTRL_8814B */ +#define BIT_EN_SINGLE_APMDU_8814B BIT(7) +/* 2 REG_PROT_MODE_CTRL_8814B */ -/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8814B */ +#define BIT_SHIFT_RTS_MAX_AGG_NUM_8814B 24 +#define BIT_MASK_RTS_MAX_AGG_NUM_8814B 0x3f +#define BIT_RTS_MAX_AGG_NUM_8814B(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8814B) \ + << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) +#define BITS_RTS_MAX_AGG_NUM_8814B \ + (BIT_MASK_RTS_MAX_AGG_NUM_8814B << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) +#define BIT_CLEAR_RTS_MAX_AGG_NUM_8814B(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8814B)) +#define BIT_GET_RTS_MAX_AGG_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) & \ + BIT_MASK_RTS_MAX_AGG_NUM_8814B) +#define BIT_SET_RTS_MAX_AGG_NUM_8814B(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM_8814B(x) | BIT_RTS_MAX_AGG_NUM_8814B(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8814B 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8814B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_3_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8814B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8814B) +#define BIT_SHIFT_MAX_AGG_NUM_8814B 16 +#define BIT_MASK_MAX_AGG_NUM_8814B 0x3f +#define BIT_MAX_AGG_NUM_8814B(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM_8814B) << BIT_SHIFT_MAX_AGG_NUM_8814B) +#define BITS_MAX_AGG_NUM_8814B \ + (BIT_MASK_MAX_AGG_NUM_8814B << BIT_SHIFT_MAX_AGG_NUM_8814B) +#define BIT_CLEAR_MAX_AGG_NUM_8814B(x) ((x) & (~BITS_MAX_AGG_NUM_8814B)) +#define BIT_GET_MAX_AGG_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM_8814B) & BIT_MASK_MAX_AGG_NUM_8814B) +#define BIT_SET_MAX_AGG_NUM_8814B(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM_8814B(x) | BIT_MAX_AGG_NUM_8814B(v)) +#define BIT_SHIFT_RTS_TXTIME_TH_8814B 8 +#define BIT_MASK_RTS_TXTIME_TH_8814B 0xff +#define BIT_RTS_TXTIME_TH_8814B(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH_8814B) << BIT_SHIFT_RTS_TXTIME_TH_8814B) +#define BITS_RTS_TXTIME_TH_8814B \ + (BIT_MASK_RTS_TXTIME_TH_8814B << BIT_SHIFT_RTS_TXTIME_TH_8814B) +#define BIT_CLEAR_RTS_TXTIME_TH_8814B(x) ((x) & (~BITS_RTS_TXTIME_TH_8814B)) +#define BIT_GET_RTS_TXTIME_TH_8814B(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8814B) & BIT_MASK_RTS_TXTIME_TH_8814B) +#define BIT_SET_RTS_TXTIME_TH_8814B(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH_8814B(x) | BIT_RTS_TXTIME_TH_8814B(v)) +#define BIT_SHIFT_RTS_LEN_TH_8814B 0 +#define BIT_MASK_RTS_LEN_TH_8814B 0xff +#define BIT_RTS_LEN_TH_8814B(x) \ + (((x) & BIT_MASK_RTS_LEN_TH_8814B) << BIT_SHIFT_RTS_LEN_TH_8814B) +#define BITS_RTS_LEN_TH_8814B \ + (BIT_MASK_RTS_LEN_TH_8814B << BIT_SHIFT_RTS_LEN_TH_8814B) +#define BIT_CLEAR_RTS_LEN_TH_8814B(x) ((x) & (~BITS_RTS_LEN_TH_8814B)) +#define BIT_GET_RTS_LEN_TH_8814B(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH_8814B) & BIT_MASK_RTS_LEN_TH_8814B) +#define BIT_SET_RTS_LEN_TH_8814B(x, v) \ + (BIT_CLEAR_RTS_LEN_TH_8814B(x) | BIT_RTS_LEN_TH_8814B(v)) -/* 2 REG_MGG_FIFO_CRTL_8814B */ -#define BIT_R_MGG_FIFO_EN_8814B BIT(31) +/* 2 REG_BAR_MODE_CTRL_8814B */ -#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8814B 28 -#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8814B 0x7 -#define BIT_R_MGG_FIFO_PG_SIZE_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8814B) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8814B) -#define BIT_GET_R_MGG_FIFO_PG_SIZE_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8814B) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8814B) +#define BIT_SHIFT_BAR_RTY_LMT_8814B 16 +#define BIT_MASK_BAR_RTY_LMT_8814B 0x3 +#define BIT_BAR_RTY_LMT_8814B(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT_8814B) << BIT_SHIFT_BAR_RTY_LMT_8814B) +#define BITS_BAR_RTY_LMT_8814B \ + (BIT_MASK_BAR_RTY_LMT_8814B << BIT_SHIFT_BAR_RTY_LMT_8814B) +#define BIT_CLEAR_BAR_RTY_LMT_8814B(x) ((x) & (~BITS_BAR_RTY_LMT_8814B)) +#define BIT_GET_BAR_RTY_LMT_8814B(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT_8814B) & BIT_MASK_BAR_RTY_LMT_8814B) +#define BIT_SET_BAR_RTY_LMT_8814B(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT_8814B(x) | BIT_BAR_RTY_LMT_8814B(v)) +#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B 8 +#define BIT_MASK_BAR_PKT_TXTIME_TH_8814B 0xff +#define BIT_BAR_PKT_TXTIME_TH_8814B(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8814B) \ + << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) +#define BITS_BAR_PKT_TXTIME_TH_8814B \ + (BIT_MASK_BAR_PKT_TXTIME_TH_8814B << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8814B(x) \ + ((x) & (~BITS_BAR_PKT_TXTIME_TH_8814B)) +#define BIT_GET_BAR_PKT_TXTIME_TH_8814B(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) & \ + BIT_MASK_BAR_PKT_TXTIME_TH_8814B) +#define BIT_SET_BAR_PKT_TXTIME_TH_8814B(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH_8814B(x) | BIT_BAR_PKT_TXTIME_TH_8814B(v)) +#define BIT_BAR_EN_V1_8814B BIT(6) -#define BIT_SHIFT_R_MGG_FIFO_START_PG_8814B 16 -#define BIT_MASK_R_MGG_FIFO_START_PG_8814B 0xfff -#define BIT_R_MGG_FIFO_START_PG_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8814B) << BIT_SHIFT_R_MGG_FIFO_START_PG_8814B) -#define BIT_GET_R_MGG_FIFO_START_PG_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8814B) & BIT_MASK_R_MGG_FIFO_START_PG_8814B) +#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B 0 +#define BIT_MASK_BAR_PKTNUM_TH_V1_8814B 0x3f +#define BIT_BAR_PKTNUM_TH_V1_8814B(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8814B) \ + << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) +#define BITS_BAR_PKTNUM_TH_V1_8814B \ + (BIT_MASK_BAR_PKTNUM_TH_V1_8814B << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8814B(x) \ + ((x) & (~BITS_BAR_PKTNUM_TH_V1_8814B)) +#define BIT_GET_BAR_PKTNUM_TH_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) & \ + BIT_MASK_BAR_PKTNUM_TH_V1_8814B) +#define BIT_SET_BAR_PKTNUM_TH_V1_8814B(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1_8814B(x) | BIT_BAR_PKTNUM_TH_V1_8814B(v)) +/* 2 REG_RA_TRY_RATE_AGG_LMT_8814B */ +#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B 0 +#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B 0x3f +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) +#define BITS_RA_TRY_RATE_AGG_LMT_V1_8814B \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8814B(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8814B)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8814B(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8814B(x) | \ + BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(v)) + +/* 2 REG_MACID_SLEEP_CTRL_8814B */ + +#define BIT_SHIFT_DEBUG_PROTOCOL_8814B 24 +#define BIT_MASK_DEBUG_PROTOCOL_8814B 0xff +#define BIT_DEBUG_PROTOCOL_8814B(x) \ + (((x) & BIT_MASK_DEBUG_PROTOCOL_8814B) \ + << BIT_SHIFT_DEBUG_PROTOCOL_8814B) +#define BITS_DEBUG_PROTOCOL_8814B \ + (BIT_MASK_DEBUG_PROTOCOL_8814B << BIT_SHIFT_DEBUG_PROTOCOL_8814B) +#define BIT_CLEAR_DEBUG_PROTOCOL_8814B(x) ((x) & (~BITS_DEBUG_PROTOCOL_8814B)) +#define BIT_GET_DEBUG_PROTOCOL_8814B(x) \ + (((x) >> BIT_SHIFT_DEBUG_PROTOCOL_8814B) & \ + BIT_MASK_DEBUG_PROTOCOL_8814B) +#define BIT_SET_DEBUG_PROTOCOL_8814B(x, v) \ + (BIT_CLEAR_DEBUG_PROTOCOL_8814B(x) | BIT_DEBUG_PROTOCOL_8814B(v)) + +#define BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B 16 +#define BIT_MASK_BCNQ_PGBNDY_RSEL_8814B 0x7 +#define BIT_BCNQ_PGBNDY_RSEL_8814B(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_RSEL_8814B) \ + << BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B) +#define BITS_BCNQ_PGBNDY_RSEL_8814B \ + (BIT_MASK_BCNQ_PGBNDY_RSEL_8814B << BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B) +#define BIT_CLEAR_BCNQ_PGBNDY_RSEL_8814B(x) \ + ((x) & (~BITS_BCNQ_PGBNDY_RSEL_8814B)) +#define BIT_GET_BCNQ_PGBNDY_RSEL_8814B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B) & \ + BIT_MASK_BCNQ_PGBNDY_RSEL_8814B) +#define BIT_SET_BCNQ_PGBNDY_RSEL_8814B(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_RSEL_8814B(x) | BIT_BCNQ_PGBNDY_RSEL_8814B(v)) + +#define BIT_SHIFT_MACID_SLEEP_SEL_8814B 0 +#define BIT_MASK_MACID_SLEEP_SEL_8814B 0x7 +#define BIT_MACID_SLEEP_SEL_8814B(x) \ + (((x) & BIT_MASK_MACID_SLEEP_SEL_8814B) \ + << BIT_SHIFT_MACID_SLEEP_SEL_8814B) +#define BITS_MACID_SLEEP_SEL_8814B \ + (BIT_MASK_MACID_SLEEP_SEL_8814B << BIT_SHIFT_MACID_SLEEP_SEL_8814B) +#define BIT_CLEAR_MACID_SLEEP_SEL_8814B(x) ((x) & (~BITS_MACID_SLEEP_SEL_8814B)) +#define BIT_GET_MACID_SLEEP_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_SLEEP_SEL_8814B) & \ + BIT_MASK_MACID_SLEEP_SEL_8814B) +#define BIT_SET_MACID_SLEEP_SEL_8814B(x, v) \ + (BIT_CLEAR_MACID_SLEEP_SEL_8814B(x) | BIT_MACID_SLEEP_SEL_8814B(v)) + +/* 2 REG_MACID_SLEEP_INFO_8814B */ + +#define BIT_SHIFT_MACID_SLEEP_INFO_8814B 0 +#define BIT_MASK_MACID_SLEEP_INFO_8814B 0xffffffffL +#define BIT_MACID_SLEEP_INFO_8814B(x) \ + (((x) & BIT_MASK_MACID_SLEEP_INFO_8814B) \ + << BIT_SHIFT_MACID_SLEEP_INFO_8814B) +#define BITS_MACID_SLEEP_INFO_8814B \ + (BIT_MASK_MACID_SLEEP_INFO_8814B << BIT_SHIFT_MACID_SLEEP_INFO_8814B) +#define BIT_CLEAR_MACID_SLEEP_INFO_8814B(x) \ + ((x) & (~BITS_MACID_SLEEP_INFO_8814B)) +#define BIT_GET_MACID_SLEEP_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_SLEEP_INFO_8814B) & \ + BIT_MASK_MACID_SLEEP_INFO_8814B) +#define BIT_SET_MACID_SLEEP_INFO_8814B(x, v) \ + (BIT_CLEAR_MACID_SLEEP_INFO_8814B(x) | BIT_MACID_SLEEP_INFO_8814B(v)) -#define BIT_SHIFT_R_MGG_FIFO_SIZE_8814B 14 -#define BIT_MASK_R_MGG_FIFO_SIZE_8814B 0x3 -#define BIT_R_MGG_FIFO_SIZE_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8814B) << BIT_SHIFT_R_MGG_FIFO_SIZE_8814B) -#define BIT_GET_R_MGG_FIFO_SIZE_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8814B) & BIT_MASK_R_MGG_FIFO_SIZE_8814B) +/* 2 REG_HW_SEQ0_8814B */ +#define BIT_SHIFT_HW_SSN_SEQ0_8814B 0 +#define BIT_MASK_HW_SSN_SEQ0_8814B 0xfff +#define BIT_HW_SSN_SEQ0_8814B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0_8814B) << BIT_SHIFT_HW_SSN_SEQ0_8814B) +#define BITS_HW_SSN_SEQ0_8814B \ + (BIT_MASK_HW_SSN_SEQ0_8814B << BIT_SHIFT_HW_SSN_SEQ0_8814B) +#define BIT_CLEAR_HW_SSN_SEQ0_8814B(x) ((x) & (~BITS_HW_SSN_SEQ0_8814B)) +#define BIT_GET_HW_SSN_SEQ0_8814B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8814B) & BIT_MASK_HW_SSN_SEQ0_8814B) +#define BIT_SET_HW_SSN_SEQ0_8814B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0_8814B(x) | BIT_HW_SSN_SEQ0_8814B(v)) -#define BIT_R_MGG_FIFO_PAUSE_8814B BIT(13) +/* 2 REG_HW_SEQ1_8814B */ -#define BIT_SHIFT_R_MGG_FIFO_RPTR_8814B 8 -#define BIT_MASK_R_MGG_FIFO_RPTR_8814B 0x1f -#define BIT_R_MGG_FIFO_RPTR_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8814B) << BIT_SHIFT_R_MGG_FIFO_RPTR_8814B) -#define BIT_GET_R_MGG_FIFO_RPTR_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8814B) & BIT_MASK_R_MGG_FIFO_RPTR_8814B) +#define BIT_SHIFT_HW_SSN_SEQ1_8814B 0 +#define BIT_MASK_HW_SSN_SEQ1_8814B 0xfff +#define BIT_HW_SSN_SEQ1_8814B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1_8814B) << BIT_SHIFT_HW_SSN_SEQ1_8814B) +#define BITS_HW_SSN_SEQ1_8814B \ + (BIT_MASK_HW_SSN_SEQ1_8814B << BIT_SHIFT_HW_SSN_SEQ1_8814B) +#define BIT_CLEAR_HW_SSN_SEQ1_8814B(x) ((x) & (~BITS_HW_SSN_SEQ1_8814B)) +#define BIT_GET_HW_SSN_SEQ1_8814B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8814B) & BIT_MASK_HW_SSN_SEQ1_8814B) +#define BIT_SET_HW_SSN_SEQ1_8814B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1_8814B(x) | BIT_HW_SSN_SEQ1_8814B(v)) +/* 2 REG_HW_SEQ2_8814B */ -#define BIT_R_MGG_FIFO_OV_8814B BIT(7) -#define BIT_R_MGG_FIFO_WPTR_ERROR_8814B BIT(6) -#define BIT_R_EN_CPU_LIFETIME_8814B BIT(5) +#define BIT_SHIFT_HW_SSN_SEQ2_8814B 0 +#define BIT_MASK_HW_SSN_SEQ2_8814B 0xfff +#define BIT_HW_SSN_SEQ2_8814B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2_8814B) << BIT_SHIFT_HW_SSN_SEQ2_8814B) +#define BITS_HW_SSN_SEQ2_8814B \ + (BIT_MASK_HW_SSN_SEQ2_8814B << BIT_SHIFT_HW_SSN_SEQ2_8814B) +#define BIT_CLEAR_HW_SSN_SEQ2_8814B(x) ((x) & (~BITS_HW_SSN_SEQ2_8814B)) +#define BIT_GET_HW_SSN_SEQ2_8814B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8814B) & BIT_MASK_HW_SSN_SEQ2_8814B) +#define BIT_SET_HW_SSN_SEQ2_8814B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2_8814B(x) | BIT_HW_SSN_SEQ2_8814B(v)) -#define BIT_SHIFT_R_MGG_FIFO_WPTR_8814B 0 -#define BIT_MASK_R_MGG_FIFO_WPTR_8814B 0x1f -#define BIT_R_MGG_FIFO_WPTR_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8814B) << BIT_SHIFT_R_MGG_FIFO_WPTR_8814B) -#define BIT_GET_R_MGG_FIFO_WPTR_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8814B) & BIT_MASK_R_MGG_FIFO_WPTR_8814B) +/* 2 REG_HW_SEQ3_8814B */ +#define BIT_SHIFT_CSI_HWSEQ_SEL_8814B 12 +#define BIT_MASK_CSI_HWSEQ_SEL_8814B 0x3 +#define BIT_CSI_HWSEQ_SEL_8814B(x) \ + (((x) & BIT_MASK_CSI_HWSEQ_SEL_8814B) << BIT_SHIFT_CSI_HWSEQ_SEL_8814B) +#define BITS_CSI_HWSEQ_SEL_8814B \ + (BIT_MASK_CSI_HWSEQ_SEL_8814B << BIT_SHIFT_CSI_HWSEQ_SEL_8814B) +#define BIT_CLEAR_CSI_HWSEQ_SEL_8814B(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8814B)) +#define BIT_GET_CSI_HWSEQ_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8814B) & BIT_MASK_CSI_HWSEQ_SEL_8814B) +#define BIT_SET_CSI_HWSEQ_SEL_8814B(x, v) \ + (BIT_CLEAR_CSI_HWSEQ_SEL_8814B(x) | BIT_CSI_HWSEQ_SEL_8814B(v)) +#define BIT_SHIFT_HW_SSN_SEQ3_8814B 0 +#define BIT_MASK_HW_SSN_SEQ3_8814B 0xfff +#define BIT_HW_SSN_SEQ3_8814B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3_8814B) << BIT_SHIFT_HW_SSN_SEQ3_8814B) +#define BITS_HW_SSN_SEQ3_8814B \ + (BIT_MASK_HW_SSN_SEQ3_8814B << BIT_SHIFT_HW_SSN_SEQ3_8814B) +#define BIT_CLEAR_HW_SSN_SEQ3_8814B(x) ((x) & (~BITS_HW_SSN_SEQ3_8814B)) +#define BIT_GET_HW_SSN_SEQ3_8814B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8814B) & BIT_MASK_HW_SSN_SEQ3_8814B) +#define BIT_SET_HW_SSN_SEQ3_8814B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3_8814B(x) | BIT_HW_SSN_SEQ3_8814B(v)) -/* 2 REG_MGG_FIFO_INT_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8814B 16 -#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8814B 0xffff -#define BIT_R_MGG_FIFO_INT_FLAG_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8814B) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8814B) -#define BIT_GET_R_MGG_FIFO_INT_FLAG_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8814B) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8814B) +#define BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B 0 +#define BIT_MASK_PTCL_TOTAL_PG_V3_8814B 0x1fff +#define BIT_PTCL_TOTAL_PG_V3_8814B(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V3_8814B) \ + << BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B) +#define BITS_PTCL_TOTAL_PG_V3_8814B \ + (BIT_MASK_PTCL_TOTAL_PG_V3_8814B << BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B) +#define BIT_CLEAR_PTCL_TOTAL_PG_V3_8814B(x) \ + ((x) & (~BITS_PTCL_TOTAL_PG_V3_8814B)) +#define BIT_GET_PTCL_TOTAL_PG_V3_8814B(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B) & \ + BIT_MASK_PTCL_TOTAL_PG_V3_8814B) +#define BIT_SET_PTCL_TOTAL_PG_V3_8814B(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V3_8814B(x) | BIT_PTCL_TOTAL_PG_V3_8814B(v)) + +/* 2 REG_PTCL_ERR_STATUS_V1_8814B */ +#define BIT_MUARB_SEARCH_ERR_8814B BIT(14) +#define BIT_MU_BFEN_ERR_8814B BIT(12) +#define BIT_NDPA_DROPNULL_ERR_8814B BIT(11) +#define BIT_NDPA_DROPPKT_ERR_8814B BIT(10) +#define BIT_PTCL_PKYIN_ERR_8814B BIT(9) +#define BIT_PTCL_QSELCNL_ERR_8814B BIT(8) +#define BIT_PTCL_RATE_TABLE_INVALID_8814B BIT(7) +#define BIT_FTM_T2R_ERROR_8814B BIT(6) +#define BIT_TXTIMEOUT_ERR_8814B BIT(5) +#define BIT_NULLPAGE_ERR_8814B BIT(4) +#define BIT_CONTENTION_ERR_8814B BIT(3) +#define BIT_HEADNULL_ERR_8814B BIT(2) +#define BIT_OVERFLOW_ERR_8814B BIT(1) +#define BIT_QUEUE_INDEX_ERR_8814B BIT(0) + +/* 2 REG_NULL_PKT_STATUS_V2_8814B */ +#define BIT_HIQ_DROP_8814B BIT(7) +#define BIT_MGQ_DROP_8814B BIT(6) +#define BIT_TX_NULL_1_V1_8814B BIT(1) +#define BIT_TX_NULL_0_V1_8814B BIT(0) + +/* 2 REG_PRECNT_CTRL_8814B */ +#define BIT_EN_PRECNT_8814B BIT(11) + +#define BIT_SHIFT_PRECNT_TH_8814B 0 +#define BIT_MASK_PRECNT_TH_8814B 0x7ff +#define BIT_PRECNT_TH_8814B(x) \ + (((x) & BIT_MASK_PRECNT_TH_8814B) << BIT_SHIFT_PRECNT_TH_8814B) +#define BITS_PRECNT_TH_8814B \ + (BIT_MASK_PRECNT_TH_8814B << BIT_SHIFT_PRECNT_TH_8814B) +#define BIT_CLEAR_PRECNT_TH_8814B(x) ((x) & (~BITS_PRECNT_TH_8814B)) +#define BIT_GET_PRECNT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_PRECNT_TH_8814B) & BIT_MASK_PRECNT_TH_8814B) +#define BIT_SET_PRECNT_TH_8814B(x, v) \ + (BIT_CLEAR_PRECNT_TH_8814B(x) | BIT_PRECNT_TH_8814B(v)) + +/* 2 REG_NULL_PKT_STATUS_EXTEND_V1_8814B */ +#define BIT_CLI3_TX_NULL_1_V1_8814B BIT(7) +#define BIT_CLI3_TX_NULL_0_V1_8814B BIT(6) +#define BIT_CLI2_TX_NULL_1_V1_8814B BIT(5) +#define BIT_CLI2_TX_NULL_0_V1_8814B BIT(4) +#define BIT_CLI1_TX_NULL_1_V1_8814B BIT(3) +#define BIT_CLI1_TX_NULL_0_V1_8814B BIT(2) +#define BIT_CLI0_TX_NULL_1_V1_8814B BIT(1) +#define BIT_CLI0_TX_NULL_0_V1_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8814B 0 -#define BIT_MASK_R_MGG_FIFO_INT_MASK_8814B 0xffff -#define BIT_R_MGG_FIFO_INT_MASK_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8814B) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8814B) -#define BIT_GET_R_MGG_FIFO_INT_MASK_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8814B) & BIT_MASK_R_MGG_FIFO_INT_MASK_8814B) +/* 2 REG_PTCL_DBG_V1_8814B */ +#define BIT_SHIFT_PTCL_DBG_8814B 0 +#define BIT_MASK_PTCL_DBG_8814B 0xffffffffL +#define BIT_PTCL_DBG_8814B(x) \ + (((x) & BIT_MASK_PTCL_DBG_8814B) << BIT_SHIFT_PTCL_DBG_8814B) +#define BITS_PTCL_DBG_8814B \ + (BIT_MASK_PTCL_DBG_8814B << BIT_SHIFT_PTCL_DBG_8814B) +#define BIT_CLEAR_PTCL_DBG_8814B(x) ((x) & (~BITS_PTCL_DBG_8814B)) +#define BIT_GET_PTCL_DBG_8814B(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_8814B) & BIT_MASK_PTCL_DBG_8814B) +#define BIT_SET_PTCL_DBG_8814B(x, v) \ + (BIT_CLEAR_PTCL_DBG_8814B(x) | BIT_PTCL_DBG_8814B(v)) + +/* 2 REG_BT_POLLUTE_PKTCNT_8814B */ + +#define BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B 0 +#define BIT_MASK_BT_POLLUTE_PKTCNT_8814B 0xffff +#define BIT_BT_POLLUTE_PKTCNT_8814B(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKTCNT_8814B) \ + << BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B) +#define BITS_BT_POLLUTE_PKTCNT_8814B \ + (BIT_MASK_BT_POLLUTE_PKTCNT_8814B << BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B) +#define BIT_CLEAR_BT_POLLUTE_PKTCNT_8814B(x) \ + ((x) & (~BITS_BT_POLLUTE_PKTCNT_8814B)) +#define BIT_GET_BT_POLLUTE_PKTCNT_8814B(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B) & \ + BIT_MASK_BT_POLLUTE_PKTCNT_8814B) +#define BIT_SET_BT_POLLUTE_PKTCNT_8814B(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKTCNT_8814B(x) | BIT_BT_POLLUTE_PKTCNT_8814B(v)) +/* 2 REG_CPUMGQ_TIMER_CTRL2_8814B */ -/* 2 REG_MGG_FIFO_LIFETIME_8814B */ +#define BIT_SHIFT_TRI_HEAD_ADDR_8814B 16 +#define BIT_MASK_TRI_HEAD_ADDR_8814B 0xfff +#define BIT_TRI_HEAD_ADDR_8814B(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR_8814B) << BIT_SHIFT_TRI_HEAD_ADDR_8814B) +#define BITS_TRI_HEAD_ADDR_8814B \ + (BIT_MASK_TRI_HEAD_ADDR_8814B << BIT_SHIFT_TRI_HEAD_ADDR_8814B) +#define BIT_CLEAR_TRI_HEAD_ADDR_8814B(x) ((x) & (~BITS_TRI_HEAD_ADDR_8814B)) +#define BIT_GET_TRI_HEAD_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8814B) & BIT_MASK_TRI_HEAD_ADDR_8814B) +#define BIT_SET_TRI_HEAD_ADDR_8814B(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR_8814B(x) | BIT_TRI_HEAD_ADDR_8814B(v)) -#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8814B 16 -#define BIT_MASK_R_MGG_FIFO_LIFETIME_8814B 0xffff -#define BIT_R_MGG_FIFO_LIFETIME_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8814B) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8814B) -#define BIT_GET_R_MGG_FIFO_LIFETIME_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8814B) & BIT_MASK_R_MGG_FIFO_LIFETIME_8814B) +#define BIT_DROP_TH_EN_8814B BIT(8) +#define BIT_SHIFT_DROP_TH_8814B 0 +#define BIT_MASK_DROP_TH_8814B 0xff +#define BIT_DROP_TH_8814B(x) \ + (((x) & BIT_MASK_DROP_TH_8814B) << BIT_SHIFT_DROP_TH_8814B) +#define BITS_DROP_TH_8814B (BIT_MASK_DROP_TH_8814B << BIT_SHIFT_DROP_TH_8814B) +#define BIT_CLEAR_DROP_TH_8814B(x) ((x) & (~BITS_DROP_TH_8814B)) +#define BIT_GET_DROP_TH_8814B(x) \ + (((x) >> BIT_SHIFT_DROP_TH_8814B) & BIT_MASK_DROP_TH_8814B) +#define BIT_SET_DROP_TH_8814B(x, v) \ + (BIT_CLEAR_DROP_TH_8814B(x) | BIT_DROP_TH_8814B(v)) + +/* 2 REG_PTCL_DBG_OUT_8814B */ + +#define BIT_SHIFT_PTCL_DBG_OUT_8814B 0 +#define BIT_MASK_PTCL_DBG_OUT_8814B 0xffffffffL +#define BIT_PTCL_DBG_OUT_8814B(x) \ + (((x) & BIT_MASK_PTCL_DBG_OUT_8814B) << BIT_SHIFT_PTCL_DBG_OUT_8814B) +#define BITS_PTCL_DBG_OUT_8814B \ + (BIT_MASK_PTCL_DBG_OUT_8814B << BIT_SHIFT_PTCL_DBG_OUT_8814B) +#define BIT_CLEAR_PTCL_DBG_OUT_8814B(x) ((x) & (~BITS_PTCL_DBG_OUT_8814B)) +#define BIT_GET_PTCL_DBG_OUT_8814B(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_OUT_8814B) & BIT_MASK_PTCL_DBG_OUT_8814B) +#define BIT_SET_PTCL_DBG_OUT_8814B(x, v) \ + (BIT_CLEAR_PTCL_DBG_OUT_8814B(x) | BIT_PTCL_DBG_OUT_8814B(v)) +/* 2 REG_DUMMY_PAGE4_V1_8814B */ -#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8814B 0 -#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8814B 0xffff -#define BIT_R_MGG_FIFO_VALID_MAP_8814B(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8814B) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8814B) -#define BIT_GET_R_MGG_FIFO_VALID_MAP_8814B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8814B) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8814B) +/* 2 REG_DUMMY_PAGE4_1_8814B */ + +/* 2 REG_MU_OFFSET_8814B */ + +#define BIT_SHIFT_MU_RATETABLE_OFFSET_8814B 16 +#define BIT_MASK_MU_RATETABLE_OFFSET_8814B 0x1ff +#define BIT_MU_RATETABLE_OFFSET_8814B(x) \ + (((x) & BIT_MASK_MU_RATETABLE_OFFSET_8814B) \ + << BIT_SHIFT_MU_RATETABLE_OFFSET_8814B) +#define BITS_MU_RATETABLE_OFFSET_8814B \ + (BIT_MASK_MU_RATETABLE_OFFSET_8814B \ + << BIT_SHIFT_MU_RATETABLE_OFFSET_8814B) +#define BIT_CLEAR_MU_RATETABLE_OFFSET_8814B(x) \ + ((x) & (~BITS_MU_RATETABLE_OFFSET_8814B)) +#define BIT_GET_MU_RATETABLE_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_MU_RATETABLE_OFFSET_8814B) & \ + BIT_MASK_MU_RATETABLE_OFFSET_8814B) +#define BIT_SET_MU_RATETABLE_OFFSET_8814B(x, v) \ + (BIT_CLEAR_MU_RATETABLE_OFFSET_8814B(x) | \ + BIT_MU_RATETABLE_OFFSET_8814B(v)) + +#define BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B 0 +#define BIT_MASK_MU_SCORETABLE_OFFSET_8814B 0x1ff +#define BIT_MU_SCORETABLE_OFFSET_8814B(x) \ + (((x) & BIT_MASK_MU_SCORETABLE_OFFSET_8814B) \ + << BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B) +#define BITS_MU_SCORETABLE_OFFSET_8814B \ + (BIT_MASK_MU_SCORETABLE_OFFSET_8814B \ + << BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B) +#define BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x) \ + ((x) & (~BITS_MU_SCORETABLE_OFFSET_8814B)) +#define BIT_GET_MU_SCORETABLE_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B) & \ + BIT_MASK_MU_SCORETABLE_OFFSET_8814B) +#define BIT_SET_MU_SCORETABLE_OFFSET_8814B(x, v) \ + (BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x) | \ + BIT_MU_SCORETABLE_OFFSET_8814B(v)) +/* 2 REG_BF0_TIME_SETTING_8814B */ +#define BIT_BF0_TIMER_SET_8814B BIT(31) +#define BIT_BF0_TIMER_CLR_8814B BIT(30) +#define BIT_BF0_UPDATE_EN_8814B BIT(29) +#define BIT_BF0_TIMER_EN_8814B BIT(28) +#define BIT_SHIFT_BF0_PRETIME_OVER_8814B 16 +#define BIT_MASK_BF0_PRETIME_OVER_8814B 0xfff +#define BIT_BF0_PRETIME_OVER_8814B(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER_8814B) \ + << BIT_SHIFT_BF0_PRETIME_OVER_8814B) +#define BITS_BF0_PRETIME_OVER_8814B \ + (BIT_MASK_BF0_PRETIME_OVER_8814B << BIT_SHIFT_BF0_PRETIME_OVER_8814B) +#define BIT_CLEAR_BF0_PRETIME_OVER_8814B(x) \ + ((x) & (~BITS_BF0_PRETIME_OVER_8814B)) +#define BIT_GET_BF0_PRETIME_OVER_8814B(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8814B) & \ + BIT_MASK_BF0_PRETIME_OVER_8814B) +#define BIT_SET_BF0_PRETIME_OVER_8814B(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER_8814B(x) | BIT_BF0_PRETIME_OVER_8814B(v)) -/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B */ +#define BIT_SHIFT_BF0_LIFETIME_8814B 0 +#define BIT_MASK_BF0_LIFETIME_8814B 0xffff +#define BIT_BF0_LIFETIME_8814B(x) \ + (((x) & BIT_MASK_BF0_LIFETIME_8814B) << BIT_SHIFT_BF0_LIFETIME_8814B) +#define BITS_BF0_LIFETIME_8814B \ + (BIT_MASK_BF0_LIFETIME_8814B << BIT_SHIFT_BF0_LIFETIME_8814B) +#define BIT_CLEAR_BF0_LIFETIME_8814B(x) ((x) & (~BITS_BF0_LIFETIME_8814B)) +#define BIT_GET_BF0_LIFETIME_8814B(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME_8814B) & BIT_MASK_BF0_LIFETIME_8814B) +#define BIT_SET_BF0_LIFETIME_8814B(x, v) \ + (BIT_CLEAR_BF0_LIFETIME_8814B(x) | BIT_BF0_LIFETIME_8814B(v)) -#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B 0 -#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B 0x7f -#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B) +/* 2 REG_BF1_TIME_SETTING_8814B */ +#define BIT_BF1_TIMER_SET_8814B BIT(31) +#define BIT_BF1_TIMER_CLR_8814B BIT(30) +#define BIT_BF1_UPDATE_EN_8814B BIT(29) +#define BIT_BF1_TIMER_EN_8814B BIT(28) +#define BIT_SHIFT_BF1_PRETIME_OVER_8814B 16 +#define BIT_MASK_BF1_PRETIME_OVER_8814B 0xfff +#define BIT_BF1_PRETIME_OVER_8814B(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER_8814B) \ + << BIT_SHIFT_BF1_PRETIME_OVER_8814B) +#define BITS_BF1_PRETIME_OVER_8814B \ + (BIT_MASK_BF1_PRETIME_OVER_8814B << BIT_SHIFT_BF1_PRETIME_OVER_8814B) +#define BIT_CLEAR_BF1_PRETIME_OVER_8814B(x) \ + ((x) & (~BITS_BF1_PRETIME_OVER_8814B)) +#define BIT_GET_BF1_PRETIME_OVER_8814B(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8814B) & \ + BIT_MASK_BF1_PRETIME_OVER_8814B) +#define BIT_SET_BF1_PRETIME_OVER_8814B(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER_8814B(x) | BIT_BF1_PRETIME_OVER_8814B(v)) +#define BIT_SHIFT_BF1_LIFETIME_8814B 0 +#define BIT_MASK_BF1_LIFETIME_8814B 0xffff +#define BIT_BF1_LIFETIME_8814B(x) \ + (((x) & BIT_MASK_BF1_LIFETIME_8814B) << BIT_SHIFT_BF1_LIFETIME_8814B) +#define BITS_BF1_LIFETIME_8814B \ + (BIT_MASK_BF1_LIFETIME_8814B << BIT_SHIFT_BF1_LIFETIME_8814B) +#define BIT_CLEAR_BF1_LIFETIME_8814B(x) ((x) & (~BITS_BF1_LIFETIME_8814B)) +#define BIT_GET_BF1_LIFETIME_8814B(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME_8814B) & BIT_MASK_BF1_LIFETIME_8814B) +#define BIT_SET_BF1_LIFETIME_8814B(x, v) \ + (BIT_CLEAR_BF1_LIFETIME_8814B(x) | BIT_BF1_LIFETIME_8814B(v)) -/* 2 REG_MU_TX_CTL_8814B (NOT SUPPORT) */ -#define BIT_R_FORCE_P1_RATEDOWN_8814B BIT(11) +/* 2 REG_BF_TIMEOUT_EN_8814B */ +#define BIT_EN_VHT_LDPC_8814B BIT(9) +#define BIT_EN_HT_LDPC_8814B BIT(8) +#define BIT_BF1_TIMEOUT_EN_8814B BIT(1) +#define BIT_BF0_TIMEOUT_EN_8814B BIT(0) -#define BIT_SHIFT_R_MU_TAB_SEL_8814B 8 -#define BIT_MASK_R_MU_TAB_SEL_8814B 0x7 -#define BIT_R_MU_TAB_SEL_8814B(x) (((x) & BIT_MASK_R_MU_TAB_SEL_8814B) << BIT_SHIFT_R_MU_TAB_SEL_8814B) -#define BIT_GET_R_MU_TAB_SEL_8814B(x) (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8814B) & BIT_MASK_R_MU_TAB_SEL_8814B) +/* 2 REG_MACID_RELEASE_INFO_8814B */ + +#define BIT_SHIFT_MACID_RELEASE_INFO_8814B 0 +#define BIT_MASK_MACID_RELEASE_INFO_8814B 0xffffffffL +#define BIT_MACID_RELEASE_INFO_8814B(x) \ + (((x) & BIT_MASK_MACID_RELEASE_INFO_8814B) \ + << BIT_SHIFT_MACID_RELEASE_INFO_8814B) +#define BITS_MACID_RELEASE_INFO_8814B \ + (BIT_MASK_MACID_RELEASE_INFO_8814B \ + << BIT_SHIFT_MACID_RELEASE_INFO_8814B) +#define BIT_CLEAR_MACID_RELEASE_INFO_8814B(x) \ + ((x) & (~BITS_MACID_RELEASE_INFO_8814B)) +#define BIT_GET_MACID_RELEASE_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_INFO_8814B) & \ + BIT_MASK_MACID_RELEASE_INFO_8814B) +#define BIT_SET_MACID_RELEASE_INFO_8814B(x, v) \ + (BIT_CLEAR_MACID_RELEASE_INFO_8814B(x) | \ + BIT_MACID_RELEASE_INFO_8814B(v)) + +/* 2 REG_MACID_RELEASE_SUCCESS_INFO_8814B */ + +#define BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B 0 +#define BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B 0xffffffffL +#define BIT_MACID_RELEASE_SUCCESS_INFO_8814B(x) \ + (((x) & BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B) \ + << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B) +#define BITS_MACID_RELEASE_SUCCESS_INFO_8814B \ + (BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B \ + << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B) +#define BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO_8814B(x) \ + ((x) & (~BITS_MACID_RELEASE_SUCCESS_INFO_8814B)) +#define BIT_GET_MACID_RELEASE_SUCCESS_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B) & \ + BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B) +#define BIT_SET_MACID_RELEASE_SUCCESS_INFO_8814B(x, v) \ + (BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO_8814B(x) | \ + BIT_MACID_RELEASE_SUCCESS_INFO_8814B(v)) + +/* 2 REG_MACID_RELEASE_CTRL_8814B */ + +#define BIT_SHIFT_MACID_RELEASE_SEL_8814B 24 +#define BIT_MASK_MACID_RELEASE_SEL_8814B 0x7 +#define BIT_MACID_RELEASE_SEL_8814B(x) \ + (((x) & BIT_MASK_MACID_RELEASE_SEL_8814B) \ + << BIT_SHIFT_MACID_RELEASE_SEL_8814B) +#define BITS_MACID_RELEASE_SEL_8814B \ + (BIT_MASK_MACID_RELEASE_SEL_8814B << BIT_SHIFT_MACID_RELEASE_SEL_8814B) +#define BIT_CLEAR_MACID_RELEASE_SEL_8814B(x) \ + ((x) & (~BITS_MACID_RELEASE_SEL_8814B)) +#define BIT_GET_MACID_RELEASE_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_SEL_8814B) & \ + BIT_MASK_MACID_RELEASE_SEL_8814B) +#define BIT_SET_MACID_RELEASE_SEL_8814B(x, v) \ + (BIT_CLEAR_MACID_RELEASE_SEL_8814B(x) | BIT_MACID_RELEASE_SEL_8814B(v)) + +#define BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B 16 +#define BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B 0xff +#define BIT_MACID_RELEASE_CLEAR_OFFSET_8814B(x) \ + (((x) & BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B) \ + << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B) +#define BITS_MACID_RELEASE_CLEAR_OFFSET_8814B \ + (BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B \ + << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B) +#define BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET_8814B(x) \ + ((x) & (~BITS_MACID_RELEASE_CLEAR_OFFSET_8814B)) +#define BIT_GET_MACID_RELEASE_CLEAR_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B) & \ + BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B) +#define BIT_SET_MACID_RELEASE_CLEAR_OFFSET_8814B(x, v) \ + (BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET_8814B(x) | \ + BIT_MACID_RELEASE_CLEAR_OFFSET_8814B(v)) + +#define BIT_MACID_RELEASE_VALUE_8814B BIT(8) + +#define BIT_SHIFT_MACID_RELEASE_OFFSET_8814B 0 +#define BIT_MASK_MACID_RELEASE_OFFSET_8814B 0xff +#define BIT_MACID_RELEASE_OFFSET_8814B(x) \ + (((x) & BIT_MASK_MACID_RELEASE_OFFSET_8814B) \ + << BIT_SHIFT_MACID_RELEASE_OFFSET_8814B) +#define BITS_MACID_RELEASE_OFFSET_8814B \ + (BIT_MASK_MACID_RELEASE_OFFSET_8814B \ + << BIT_SHIFT_MACID_RELEASE_OFFSET_8814B) +#define BIT_CLEAR_MACID_RELEASE_OFFSET_8814B(x) \ + ((x) & (~BITS_MACID_RELEASE_OFFSET_8814B)) +#define BIT_GET_MACID_RELEASE_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_RELEASE_OFFSET_8814B) & \ + BIT_MASK_MACID_RELEASE_OFFSET_8814B) +#define BIT_SET_MACID_RELEASE_OFFSET_8814B(x, v) \ + (BIT_CLEAR_MACID_RELEASE_OFFSET_8814B(x) | \ + BIT_MACID_RELEASE_OFFSET_8814B(v)) +/* 2 REG_FAST_EDCA_VOVI_SETTING_8814B */ -#define BIT_R_EN_MU_MIMO_8814B BIT(7) -#define BIT_R_EN_REVERS_GTAB_8814B BIT(6) +#define BIT_SHIFT_VI_FAST_EDCA_TO_8814B 24 +#define BIT_MASK_VI_FAST_EDCA_TO_8814B 0xff +#define BIT_VI_FAST_EDCA_TO_8814B(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO_8814B) \ + << BIT_SHIFT_VI_FAST_EDCA_TO_8814B) +#define BITS_VI_FAST_EDCA_TO_8814B \ + (BIT_MASK_VI_FAST_EDCA_TO_8814B << BIT_SHIFT_VI_FAST_EDCA_TO_8814B) +#define BIT_CLEAR_VI_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8814B)) +#define BIT_GET_VI_FAST_EDCA_TO_8814B(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8814B) & \ + BIT_MASK_VI_FAST_EDCA_TO_8814B) +#define BIT_SET_VI_FAST_EDCA_TO_8814B(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO_8814B(x) | BIT_VI_FAST_EDCA_TO_8814B(v)) -#define BIT_SHIFT_R_MU_TABLE_VALID_8814B 0 -#define BIT_MASK_R_MU_TABLE_VALID_8814B 0x3f -#define BIT_R_MU_TABLE_VALID_8814B(x) (((x) & BIT_MASK_R_MU_TABLE_VALID_8814B) << BIT_SHIFT_R_MU_TABLE_VALID_8814B) -#define BIT_GET_R_MU_TABLE_VALID_8814B(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8814B) & BIT_MASK_R_MU_TABLE_VALID_8814B) +#define BIT_VI_THRESHOLD_SEL_8814B BIT(23) +#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B 16 +#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_VI_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B) \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) +#define BITS_VI_FAST_EDCA_PKT_TH_8814B \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8814B(x) \ + ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8814B)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) & \ + BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B) +#define BIT_SET_VI_FAST_EDCA_PKT_TH_8814B(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8814B(x) | \ + BIT_VI_FAST_EDCA_PKT_TH_8814B(v)) +#define BIT_SHIFT_VO_FAST_EDCA_TO_8814B 8 +#define BIT_MASK_VO_FAST_EDCA_TO_8814B 0xff +#define BIT_VO_FAST_EDCA_TO_8814B(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO_8814B) \ + << BIT_SHIFT_VO_FAST_EDCA_TO_8814B) +#define BITS_VO_FAST_EDCA_TO_8814B \ + (BIT_MASK_VO_FAST_EDCA_TO_8814B << BIT_SHIFT_VO_FAST_EDCA_TO_8814B) +#define BIT_CLEAR_VO_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8814B)) +#define BIT_GET_VO_FAST_EDCA_TO_8814B(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8814B) & \ + BIT_MASK_VO_FAST_EDCA_TO_8814B) +#define BIT_SET_VO_FAST_EDCA_TO_8814B(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO_8814B(x) | BIT_VO_FAST_EDCA_TO_8814B(v)) -/* 2 REG_MU_STA_GID_VLD_8814B (NOT SUPPORT) */ +#define BIT_VO_THRESHOLD_SEL_8814B BIT(7) -/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B 0 +#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_VO_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B) \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) +#define BITS_VO_FAST_EDCA_PKT_TH_8814B \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8814B(x) \ + ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8814B)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) & \ + BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B) +#define BIT_SET_VO_FAST_EDCA_PKT_TH_8814B(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8814B(x) | \ + BIT_VO_FAST_EDCA_PKT_TH_8814B(v)) -#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B 0 -#define BIT_MASK_R_MU_STA_GTAB_VALID_8814B 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) -#define BIT_GET_R_MU_STA_GTAB_VALID_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) +/* 2 REG_FAST_EDCA_BEBK_SETTING_8814B */ +#define BIT_SHIFT_BK_FAST_EDCA_TO_8814B 24 +#define BIT_MASK_BK_FAST_EDCA_TO_8814B 0xff +#define BIT_BK_FAST_EDCA_TO_8814B(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO_8814B) \ + << BIT_SHIFT_BK_FAST_EDCA_TO_8814B) +#define BITS_BK_FAST_EDCA_TO_8814B \ + (BIT_MASK_BK_FAST_EDCA_TO_8814B << BIT_SHIFT_BK_FAST_EDCA_TO_8814B) +#define BIT_CLEAR_BK_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8814B)) +#define BIT_GET_BK_FAST_EDCA_TO_8814B(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8814B) & \ + BIT_MASK_BK_FAST_EDCA_TO_8814B) +#define BIT_SET_BK_FAST_EDCA_TO_8814B(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO_8814B(x) | BIT_BK_FAST_EDCA_TO_8814B(v)) +#define BIT_BK_THRESHOLD_SEL_8814B BIT(23) -#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B 0 -#define BIT_MASK_R_MU_STA_GTAB_VALID_8814B 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) -#define BIT_GET_R_MU_STA_GTAB_VALID_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8814B) & BIT_MASK_R_MU_STA_GTAB_VALID_8814B) +#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B 16 +#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_BK_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B) \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) +#define BITS_BK_FAST_EDCA_PKT_TH_8814B \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8814B(x) \ + ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8814B)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) & \ + BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B) +#define BIT_SET_BK_FAST_EDCA_PKT_TH_8814B(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8814B(x) | \ + BIT_BK_FAST_EDCA_PKT_TH_8814B(v)) +#define BIT_SHIFT_BE_FAST_EDCA_TO_8814B 8 +#define BIT_MASK_BE_FAST_EDCA_TO_8814B 0xff +#define BIT_BE_FAST_EDCA_TO_8814B(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO_8814B) \ + << BIT_SHIFT_BE_FAST_EDCA_TO_8814B) +#define BITS_BE_FAST_EDCA_TO_8814B \ + (BIT_MASK_BE_FAST_EDCA_TO_8814B << BIT_SHIFT_BE_FAST_EDCA_TO_8814B) +#define BIT_CLEAR_BE_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8814B)) +#define BIT_GET_BE_FAST_EDCA_TO_8814B(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8814B) & \ + BIT_MASK_BE_FAST_EDCA_TO_8814B) +#define BIT_SET_BE_FAST_EDCA_TO_8814B(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO_8814B(x) | BIT_BE_FAST_EDCA_TO_8814B(v)) +#define BIT_BE_THRESHOLD_SEL_8814B BIT(7) -/* 2 REG_MU_STA_USER_POS_INFO_8814B (NOT SUPPORT) */ +#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B 0 +#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B 0x7f +#define BIT_BE_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B) \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) +#define BITS_BE_FAST_EDCA_PKT_TH_8814B \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8814B(x) \ + ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8814B)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) & \ + BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B) +#define BIT_SET_BE_FAST_EDCA_PKT_TH_8814B(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8814B(x) | \ + BIT_BE_FAST_EDCA_PKT_TH_8814B(v)) + +/* 2 REG_MACID_DROP_INFO_8814B */ + +#define BIT_SHIFT_MACID_DROP_INFO_8814B 0 +#define BIT_MASK_MACID_DROP_INFO_8814B 0xffffffffL +#define BIT_MACID_DROP_INFO_8814B(x) \ + (((x) & BIT_MASK_MACID_DROP_INFO_8814B) \ + << BIT_SHIFT_MACID_DROP_INFO_8814B) +#define BITS_MACID_DROP_INFO_8814B \ + (BIT_MASK_MACID_DROP_INFO_8814B << BIT_SHIFT_MACID_DROP_INFO_8814B) +#define BIT_CLEAR_MACID_DROP_INFO_8814B(x) ((x) & (~BITS_MACID_DROP_INFO_8814B)) +#define BIT_GET_MACID_DROP_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_DROP_INFO_8814B) & \ + BIT_MASK_MACID_DROP_INFO_8814B) +#define BIT_SET_MACID_DROP_INFO_8814B(x, v) \ + (BIT_CLEAR_MACID_DROP_INFO_8814B(x) | BIT_MACID_DROP_INFO_8814B(v)) + +/* 2 REG_MACID_DROP_CTRL_8814B */ + +#define BIT_SHIFT_MACID_DROP_SEL_8814B 0 +#define BIT_MASK_MACID_DROP_SEL_8814B 0x7 +#define BIT_MACID_DROP_SEL_8814B(x) \ + (((x) & BIT_MASK_MACID_DROP_SEL_8814B) \ + << BIT_SHIFT_MACID_DROP_SEL_8814B) +#define BITS_MACID_DROP_SEL_8814B \ + (BIT_MASK_MACID_DROP_SEL_8814B << BIT_SHIFT_MACID_DROP_SEL_8814B) +#define BIT_CLEAR_MACID_DROP_SEL_8814B(x) ((x) & (~BITS_MACID_DROP_SEL_8814B)) +#define BIT_GET_MACID_DROP_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_DROP_SEL_8814B) & \ + BIT_MASK_MACID_DROP_SEL_8814B) +#define BIT_SET_MACID_DROP_SEL_8814B(x, v) \ + (BIT_CLEAR_MACID_DROP_SEL_8814B(x) | BIT_MACID_DROP_SEL_8814B(v)) + +/* 2 REG_MGQ_FIFO_WRITE_POINTER_8814B */ +#define BIT_MGQ_FIFO_OV_8814B BIT(7) +#define BIT_MGQ_FIFO_WPTR_ERROR_8814B BIT(6) +#define BIT_EN_MGQ_FIFO_LIFETIME_8814B BIT(5) + +#define BIT_SHIFT_MGQ_FIFO_WPTR_8814B 0 +#define BIT_MASK_MGQ_FIFO_WPTR_8814B 0x1f +#define BIT_MGQ_FIFO_WPTR_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_WPTR_8814B) << BIT_SHIFT_MGQ_FIFO_WPTR_8814B) +#define BITS_MGQ_FIFO_WPTR_8814B \ + (BIT_MASK_MGQ_FIFO_WPTR_8814B << BIT_SHIFT_MGQ_FIFO_WPTR_8814B) +#define BIT_CLEAR_MGQ_FIFO_WPTR_8814B(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8814B)) +#define BIT_GET_MGQ_FIFO_WPTR_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8814B) & BIT_MASK_MGQ_FIFO_WPTR_8814B) +#define BIT_SET_MGQ_FIFO_WPTR_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_WPTR_8814B(x) | BIT_MGQ_FIFO_WPTR_8814B(v)) + +/* 2 REG_MGQ_FIFO_READ_POINTER_8814B */ + +#define BIT_SHIFT_MGQ_FIFO_SIZE_8814B 14 +#define BIT_MASK_MGQ_FIFO_SIZE_8814B 0x3 +#define BIT_MGQ_FIFO_SIZE_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_SIZE_8814B) << BIT_SHIFT_MGQ_FIFO_SIZE_8814B) +#define BITS_MGQ_FIFO_SIZE_8814B \ + (BIT_MASK_MGQ_FIFO_SIZE_8814B << BIT_SHIFT_MGQ_FIFO_SIZE_8814B) +#define BIT_CLEAR_MGQ_FIFO_SIZE_8814B(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8814B)) +#define BIT_GET_MGQ_FIFO_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8814B) & BIT_MASK_MGQ_FIFO_SIZE_8814B) +#define BIT_SET_MGQ_FIFO_SIZE_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_SIZE_8814B(x) | BIT_MGQ_FIFO_SIZE_8814B(v)) + +#define BIT_MGQ_FIFO_PAUSE_8814B BIT(13) + +#define BIT_SHIFT_MGQ_FIFO_RPTR_8814B 8 +#define BIT_MASK_MGQ_FIFO_RPTR_8814B 0x1f +#define BIT_MGQ_FIFO_RPTR_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_RPTR_8814B) << BIT_SHIFT_MGQ_FIFO_RPTR_8814B) +#define BITS_MGQ_FIFO_RPTR_8814B \ + (BIT_MASK_MGQ_FIFO_RPTR_8814B << BIT_SHIFT_MGQ_FIFO_RPTR_8814B) +#define BIT_CLEAR_MGQ_FIFO_RPTR_8814B(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8814B)) +#define BIT_GET_MGQ_FIFO_RPTR_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8814B) & BIT_MASK_MGQ_FIFO_RPTR_8814B) +#define BIT_SET_MGQ_FIFO_RPTR_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_RPTR_8814B(x) | BIT_MGQ_FIFO_RPTR_8814B(v)) + +/* 2 REG_MGQ_FIFO_ENABLE_8814B */ +#define BIT_MGQ_FIFO_EN_V1_8814B BIT(15) + +#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B 12 +#define BIT_MASK_MGQ_FIFO_PG_SIZE_8814B 0x7 +#define BIT_MGQ_FIFO_PG_SIZE_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8814B) \ + << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B) +#define BITS_MGQ_FIFO_PG_SIZE_8814B \ + (BIT_MASK_MGQ_FIFO_PG_SIZE_8814B << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B) +#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_PG_SIZE_8814B)) +#define BIT_GET_MGQ_FIFO_PG_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B) & \ + BIT_MASK_MGQ_FIFO_PG_SIZE_8814B) +#define BIT_SET_MGQ_FIFO_PG_SIZE_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PG_SIZE_8814B(x) | BIT_MGQ_FIFO_PG_SIZE_8814B(v)) + +#define BIT_SHIFT_MGQ_FIFO_START_PG_8814B 0 +#define BIT_MASK_MGQ_FIFO_START_PG_8814B 0xfff +#define BIT_MGQ_FIFO_START_PG_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_START_PG_8814B) \ + << BIT_SHIFT_MGQ_FIFO_START_PG_8814B) +#define BITS_MGQ_FIFO_START_PG_8814B \ + (BIT_MASK_MGQ_FIFO_START_PG_8814B << BIT_SHIFT_MGQ_FIFO_START_PG_8814B) +#define BIT_CLEAR_MGQ_FIFO_START_PG_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_START_PG_8814B)) +#define BIT_GET_MGQ_FIFO_START_PG_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8814B) & \ + BIT_MASK_MGQ_FIFO_START_PG_8814B) +#define BIT_SET_MGQ_FIFO_START_PG_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_START_PG_8814B(x) | BIT_MGQ_FIFO_START_PG_8814B(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8814B */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B 0xffff +#define BIT_MGQ_FIFO_REL_INT_MASK_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B) +#define BITS_MGQ_FIFO_REL_INT_MASK_8814B \ + (BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8814B)) +#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B) & \ + BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B) +#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8814B(x) | \ + BIT_MGQ_FIFO_REL_INT_MASK_8814B(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8814B */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B 0xffff +#define BIT_MGQ_FIFO_REL_INT_FLAG_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B) +#define BITS_MGQ_FIFO_REL_INT_FLAG_8814B \ + (BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8814B)) +#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B) & \ + BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B) +#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8814B(x) | \ + BIT_MGQ_FIFO_REL_INT_FLAG_8814B(v)) + +/* 2 REG_MGQ_FIFO_VALID_MAP_8814B */ + +#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B 0 +#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B 0xffff +#define BIT_MGQ_FIFO_PKT_VALID_MAP_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B) \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B) +#define BITS_MGQ_FIFO_PKT_VALID_MAP_8814B \ + (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B) +#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8814B)) +#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B) & \ + BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B) +#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8814B(x) | \ + BIT_MGQ_FIFO_PKT_VALID_MAP_8814B(v)) + +/* 2 REG_MGQ_FIFO_LIFETIME_8814B */ + +#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B 0 +#define BIT_MASK_MGQ_FIFO_LIFETIME_8814B 0xffff +#define BIT_MGQ_FIFO_LIFETIME_8814B(x) \ + (((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8814B) \ + << BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B) +#define BITS_MGQ_FIFO_LIFETIME_8814B \ + (BIT_MASK_MGQ_FIFO_LIFETIME_8814B << BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B) +#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8814B(x) \ + ((x) & (~BITS_MGQ_FIFO_LIFETIME_8814B)) +#define BIT_GET_MGQ_FIFO_LIFETIME_8814B(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B) & \ + BIT_MASK_MGQ_FIFO_LIFETIME_8814B) +#define BIT_SET_MGQ_FIFO_LIFETIME_8814B(x, v) \ + (BIT_CLEAR_MGQ_FIFO_LIFETIME_8814B(x) | BIT_MGQ_FIFO_LIFETIME_8814B(v)) /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B 0 -#define BIT_MASK_R_MU_STA_GTAB_POSITION_8814B 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) - - - -#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B 0 -#define BIT_MASK_R_MU_STA_GTAB_POSITION_8814B 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8814B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8814B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8814B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8814B) +/* 2 REG_PKT_TRANS_8814B */ + +#define BIT_SHIFT_IE_DESC_OFFSET_8814B 16 +#define BIT_MASK_IE_DESC_OFFSET_8814B 0x1ff +#define BIT_IE_DESC_OFFSET_8814B(x) \ + (((x) & BIT_MASK_IE_DESC_OFFSET_8814B) \ + << BIT_SHIFT_IE_DESC_OFFSET_8814B) +#define BITS_IE_DESC_OFFSET_8814B \ + (BIT_MASK_IE_DESC_OFFSET_8814B << BIT_SHIFT_IE_DESC_OFFSET_8814B) +#define BIT_CLEAR_IE_DESC_OFFSET_8814B(x) ((x) & (~BITS_IE_DESC_OFFSET_8814B)) +#define BIT_GET_IE_DESC_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_IE_DESC_OFFSET_8814B) & \ + BIT_MASK_IE_DESC_OFFSET_8814B) +#define BIT_SET_IE_DESC_OFFSET_8814B(x, v) \ + (BIT_CLEAR_IE_DESC_OFFSET_8814B(x) | BIT_IE_DESC_OFFSET_8814B(v)) + +#define BIT_DIS_FWCMD_PATH_ERRCHK_8814B BIT(13) +#define BIT_MAC_HDR_CONVERT_EN_8814B BIT(12) +#define BIT_TXDESC_TRANS_EN_8814B BIT(8) +#define BIT_PKT_TRANS_ERRINT_EN_8814B BIT(7) + +#define BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B 4 +#define BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B 0x3 +#define BIT_PKT_TRANS_ERR_MACID_SEL_8814B(x) \ + (((x) & BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B) \ + << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B) +#define BITS_PKT_TRANS_ERR_MACID_SEL_8814B \ + (BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B \ + << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B) +#define BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL_8814B(x) \ + ((x) & (~BITS_PKT_TRANS_ERR_MACID_SEL_8814B)) +#define BIT_GET_PKT_TRANS_ERR_MACID_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B) & \ + BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B) +#define BIT_SET_PKT_TRANS_ERR_MACID_SEL_8814B(x, v) \ + (BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL_8814B(x) | \ + BIT_PKT_TRANS_ERR_MACID_SEL_8814B(v)) + +#define BIT_PKT_TRANS_IEINIT_ERR_8814B BIT(3) +#define BIT_PKT_TRANS_IENUM_ERR_8814B BIT(2) +#define BIT_PKT_TRANS_IECNT_ERR1_8814B BIT(1) +#define BIT_PKT_TRANS_IECNT_ERR0_8814B BIT(0) + +/* 2 REG_SHCUT_LLC_ETH_TYPE0_8814B */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE1_8814B */ + +#define BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B 16 +#define BIT_MASK_SHCUT_MHDR_OFFSET_8814B 0x1ff +#define BIT_SHCUT_MHDR_OFFSET_8814B(x) \ + (((x) & BIT_MASK_SHCUT_MHDR_OFFSET_8814B) \ + << BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B) +#define BITS_SHCUT_MHDR_OFFSET_8814B \ + (BIT_MASK_SHCUT_MHDR_OFFSET_8814B << BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B) +#define BIT_CLEAR_SHCUT_MHDR_OFFSET_8814B(x) \ + ((x) & (~BITS_SHCUT_MHDR_OFFSET_8814B)) +#define BIT_GET_SHCUT_MHDR_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B) & \ + BIT_MASK_SHCUT_MHDR_OFFSET_8814B) +#define BIT_SET_SHCUT_MHDR_OFFSET_8814B(x, v) \ + (BIT_CLEAR_SHCUT_MHDR_OFFSET_8814B(x) | BIT_SHCUT_MHDR_OFFSET_8814B(v)) + +/* 2 REG_SHCUT_LLC_OUI0_8814B */ + +/* 2 REG_SHCUT_LLC_OUI1_8814B */ + +/* 2 REG_SHCUT_LLC_OUI2_8814B */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B 0 +#define BIT_MASK_PKT_TRANS_ERR_MACID_8814B 0xffffffffL +#define BIT_PKT_TRANS_ERR_MACID_8814B(x) \ + (((x) & BIT_MASK_PKT_TRANS_ERR_MACID_8814B) \ + << BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B) +#define BITS_PKT_TRANS_ERR_MACID_8814B \ + (BIT_MASK_PKT_TRANS_ERR_MACID_8814B \ + << BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B) +#define BIT_CLEAR_PKT_TRANS_ERR_MACID_8814B(x) \ + ((x) & (~BITS_PKT_TRANS_ERR_MACID_8814B)) +#define BIT_GET_PKT_TRANS_ERR_MACID_8814B(x) \ + (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B) & \ + BIT_MASK_PKT_TRANS_ERR_MACID_8814B) +#define BIT_SET_PKT_TRANS_ERR_MACID_8814B(x, v) \ + (BIT_CLEAR_PKT_TRANS_ERR_MACID_8814B(x) | \ + BIT_PKT_TRANS_ERR_MACID_8814B(v)) + +/* 2 REG_FWCMDQ_CTRL_8814B */ +#define BIT_FW_RELEASEPKT_POLLING_8814B BIT(31) + +#define BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B 16 +#define BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B 0xfff +#define BIT_FWCMDQ_RELEASE_HEAD_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B) \ + << BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B) +#define BITS_FWCMDQ_RELEASE_HEAD_8814B \ + (BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B \ + << BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B) +#define BIT_CLEAR_FWCMDQ_RELEASE_HEAD_8814B(x) \ + ((x) & (~BITS_FWCMDQ_RELEASE_HEAD_8814B)) +#define BIT_GET_FWCMDQ_RELEASE_HEAD_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B) & \ + BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B) +#define BIT_SET_FWCMDQ_RELEASE_HEAD_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_RELEASE_HEAD_8814B(x) | \ + BIT_FWCMDQ_RELEASE_HEAD_8814B(v)) + +#define BIT_FW_GETPKTT_POLLING_8814B BIT(15) + +#define BIT_SHIFT_FWCMDQ_H_8814B 0 +#define BIT_MASK_FWCMDQ_H_8814B 0xfff +#define BIT_FWCMDQ_H_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_H_8814B) << BIT_SHIFT_FWCMDQ_H_8814B) +#define BITS_FWCMDQ_H_8814B \ + (BIT_MASK_FWCMDQ_H_8814B << BIT_SHIFT_FWCMDQ_H_8814B) +#define BIT_CLEAR_FWCMDQ_H_8814B(x) ((x) & (~BITS_FWCMDQ_H_8814B)) +#define BIT_GET_FWCMDQ_H_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_H_8814B) & BIT_MASK_FWCMDQ_H_8814B) +#define BIT_SET_FWCMDQ_H_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_H_8814B(x) | BIT_FWCMDQ_H_8814B(v)) + +/* 2 REG_FWCMDQ_PAGE_8814B */ + +#define BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B 16 +#define BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B 0xfff +#define BIT_FWCMDQ_TOTAL_PAGE_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B) \ + << BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B) +#define BITS_FWCMDQ_TOTAL_PAGE_8814B \ + (BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B << BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B) +#define BIT_CLEAR_FWCMDQ_TOTAL_PAGE_8814B(x) \ + ((x) & (~BITS_FWCMDQ_TOTAL_PAGE_8814B)) +#define BIT_GET_FWCMDQ_TOTAL_PAGE_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B) & \ + BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B) +#define BIT_SET_FWCMDQ_TOTAL_PAGE_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_TOTAL_PAGE_8814B(x) | BIT_FWCMDQ_TOTAL_PAGE_8814B(v)) + +#define BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B 0 +#define BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B 0xfff +#define BIT_FWCMDQ_QUEUE_PAGE_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B) \ + << BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B) +#define BITS_FWCMDQ_QUEUE_PAGE_8814B \ + (BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B << BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B) +#define BIT_CLEAR_FWCMDQ_QUEUE_PAGE_8814B(x) \ + ((x) & (~BITS_FWCMDQ_QUEUE_PAGE_8814B)) +#define BIT_GET_FWCMDQ_QUEUE_PAGE_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B) & \ + BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B) +#define BIT_SET_FWCMDQ_QUEUE_PAGE_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_QUEUE_PAGE_8814B(x) | BIT_FWCMDQ_QUEUE_PAGE_8814B(v)) + +/* 2 REG_FWCMDQ_INFO_8814B */ +#define BIT_FWCMD_READY_8814B BIT(31) +#define BIT_FWCMDQ_OVERFLOW_8814B BIT(30) +#define BIT_FWCMDQ_UNDERFLOW_8814B BIT(29) +#define BIT_FWCMDQ_RELEASE_MISS_8814B BIT(28) + +#define BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B 16 +#define BIT_MASK_FWCMDQ_TOTAL_PKT_8814B 0xfff +#define BIT_FWCMDQ_TOTAL_PKT_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_TOTAL_PKT_8814B) \ + << BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B) +#define BITS_FWCMDQ_TOTAL_PKT_8814B \ + (BIT_MASK_FWCMDQ_TOTAL_PKT_8814B << BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B) +#define BIT_CLEAR_FWCMDQ_TOTAL_PKT_8814B(x) \ + ((x) & (~BITS_FWCMDQ_TOTAL_PKT_8814B)) +#define BIT_GET_FWCMDQ_TOTAL_PKT_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B) & \ + BIT_MASK_FWCMDQ_TOTAL_PKT_8814B) +#define BIT_SET_FWCMDQ_TOTAL_PKT_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_TOTAL_PKT_8814B(x) | BIT_FWCMDQ_TOTAL_PKT_8814B(v)) + +#define BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B 0 +#define BIT_MASK_FWCMDQ_QUEUE_PKT_8814B 0xfff +#define BIT_FWCMDQ_QUEUE_PKT_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_QUEUE_PKT_8814B) \ + << BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B) +#define BITS_FWCMDQ_QUEUE_PKT_8814B \ + (BIT_MASK_FWCMDQ_QUEUE_PKT_8814B << BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B) +#define BIT_CLEAR_FWCMDQ_QUEUE_PKT_8814B(x) \ + ((x) & (~BITS_FWCMDQ_QUEUE_PKT_8814B)) +#define BIT_GET_FWCMDQ_QUEUE_PKT_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B) & \ + BIT_MASK_FWCMDQ_QUEUE_PKT_8814B) +#define BIT_SET_FWCMDQ_QUEUE_PKT_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_QUEUE_PKT_8814B(x) | BIT_FWCMDQ_QUEUE_PKT_8814B(v)) + +/* 2 REG_FWCMDQ_HOLD_PKTNUM_8814B */ + +#define BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B 0 +#define BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B 0xfff +#define BIT_FWCMDQ_HOLD__PKTNUM_8814B(x) \ + (((x) & BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B) \ + << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B) +#define BITS_FWCMDQ_HOLD__PKTNUM_8814B \ + (BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B \ + << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B) +#define BIT_CLEAR_FWCMDQ_HOLD__PKTNUM_8814B(x) \ + ((x) & (~BITS_FWCMDQ_HOLD__PKTNUM_8814B)) +#define BIT_GET_FWCMDQ_HOLD__PKTNUM_8814B(x) \ + (((x) >> BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B) & \ + BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B) +#define BIT_SET_FWCMDQ_HOLD__PKTNUM_8814B(x, v) \ + (BIT_CLEAR_FWCMDQ_HOLD__PKTNUM_8814B(x) | \ + BIT_FWCMDQ_HOLD__PKTNUM_8814B(v)) + +/* 2 REG_MU_TX_CTRL_8814B */ +#define BIT_SEARCH_DONE_RDY_8814B BIT(31) +#define BIT_MU_EN_8814B BIT(30) +#define BIT_MU_SECONDARY_WAITMODE_EN_8814B BIT(29) +#define BIT_MU_BB_SCORE_EN_8814B BIT(28) +#define BIT_MU_SECONDARY_ANT_COUNT_EN_8814B BIT(27) +#define BIT_MUARB_SEARCH_ERR_EN_8814B BIT(26) + +#define BIT_SHIFT_DIS_SU_TXBF_8814B 16 +#define BIT_MASK_DIS_SU_TXBF_8814B 0x3f +#define BIT_DIS_SU_TXBF_8814B(x) \ + (((x) & BIT_MASK_DIS_SU_TXBF_8814B) << BIT_SHIFT_DIS_SU_TXBF_8814B) +#define BITS_DIS_SU_TXBF_8814B \ + (BIT_MASK_DIS_SU_TXBF_8814B << BIT_SHIFT_DIS_SU_TXBF_8814B) +#define BIT_CLEAR_DIS_SU_TXBF_8814B(x) ((x) & (~BITS_DIS_SU_TXBF_8814B)) +#define BIT_GET_DIS_SU_TXBF_8814B(x) \ + (((x) >> BIT_SHIFT_DIS_SU_TXBF_8814B) & BIT_MASK_DIS_SU_TXBF_8814B) +#define BIT_SET_DIS_SU_TXBF_8814B(x, v) \ + (BIT_CLEAR_DIS_SU_TXBF_8814B(x) | BIT_DIS_SU_TXBF_8814B(v)) + +#define BIT_SHIFT_MU_RL_8814B 12 +#define BIT_MASK_MU_RL_8814B 0xf +#define BIT_MU_RL_8814B(x) \ + (((x) & BIT_MASK_MU_RL_8814B) << BIT_SHIFT_MU_RL_8814B) +#define BITS_MU_RL_8814B (BIT_MASK_MU_RL_8814B << BIT_SHIFT_MU_RL_8814B) +#define BIT_CLEAR_MU_RL_8814B(x) ((x) & (~BITS_MU_RL_8814B)) +#define BIT_GET_MU_RL_8814B(x) \ + (((x) >> BIT_SHIFT_MU_RL_8814B) & BIT_MASK_MU_RL_8814B) +#define BIT_SET_MU_RL_8814B(x, v) \ + (BIT_CLEAR_MU_RL_8814B(x) | BIT_MU_RL_8814B(v)) + +#define BIT_SHIFT_MU_TAB_SEL_8814B 8 +#define BIT_MASK_MU_TAB_SEL_8814B 0xf +#define BIT_MU_TAB_SEL_8814B(x) \ + (((x) & BIT_MASK_MU_TAB_SEL_8814B) << BIT_SHIFT_MU_TAB_SEL_8814B) +#define BITS_MU_TAB_SEL_8814B \ + (BIT_MASK_MU_TAB_SEL_8814B << BIT_SHIFT_MU_TAB_SEL_8814B) +#define BIT_CLEAR_MU_TAB_SEL_8814B(x) ((x) & (~BITS_MU_TAB_SEL_8814B)) +#define BIT_GET_MU_TAB_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MU_TAB_SEL_8814B) & BIT_MASK_MU_TAB_SEL_8814B) +#define BIT_SET_MU_TAB_SEL_8814B(x, v) \ + (BIT_CLEAR_MU_TAB_SEL_8814B(x) | BIT_MU_TAB_SEL_8814B(v)) + +#define BIT_SHIFT_MU_TAB_VALID_8814B 0 +#define BIT_MASK_MU_TAB_VALID_8814B 0x3f +#define BIT_MU_TAB_VALID_8814B(x) \ + (((x) & BIT_MASK_MU_TAB_VALID_8814B) << BIT_SHIFT_MU_TAB_VALID_8814B) +#define BITS_MU_TAB_VALID_8814B \ + (BIT_MASK_MU_TAB_VALID_8814B << BIT_SHIFT_MU_TAB_VALID_8814B) +#define BIT_CLEAR_MU_TAB_VALID_8814B(x) ((x) & (~BITS_MU_TAB_VALID_8814B)) +#define BIT_GET_MU_TAB_VALID_8814B(x) \ + (((x) >> BIT_SHIFT_MU_TAB_VALID_8814B) & BIT_MASK_MU_TAB_VALID_8814B) +#define BIT_SET_MU_TAB_VALID_8814B(x, v) \ + (BIT_CLEAR_MU_TAB_VALID_8814B(x) | BIT_MU_TAB_VALID_8814B(v)) + +/* 2 REG_MU_STA_GID_VLD_8814B */ + +#define BIT_SHIFT_MU_STA_GTAB_VALID_8814B 0 +#define BIT_MASK_MU_STA_GTAB_VALID_8814B 0xffffffffL +#define BIT_MU_STA_GTAB_VALID_8814B(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_VALID_8814B) \ + << BIT_SHIFT_MU_STA_GTAB_VALID_8814B) +#define BITS_MU_STA_GTAB_VALID_8814B \ + (BIT_MASK_MU_STA_GTAB_VALID_8814B << BIT_SHIFT_MU_STA_GTAB_VALID_8814B) +#define BIT_CLEAR_MU_STA_GTAB_VALID_8814B(x) \ + ((x) & (~BITS_MU_STA_GTAB_VALID_8814B)) +#define BIT_GET_MU_STA_GTAB_VALID_8814B(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_VALID_8814B) & \ + BIT_MASK_MU_STA_GTAB_VALID_8814B) +#define BIT_SET_MU_STA_GTAB_VALID_8814B(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_VALID_8814B(x) | BIT_MU_STA_GTAB_VALID_8814B(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_8814B */ + +#define BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B 0 +#define BIT_MASK_MU_STA_GTAB_POSITION_L_8814B 0xffffffffL +#define BIT_MU_STA_GTAB_POSITION_L_8814B(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_POSITION_L_8814B) \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B) +#define BITS_MU_STA_GTAB_POSITION_L_8814B \ + (BIT_MASK_MU_STA_GTAB_POSITION_L_8814B \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B) +#define BIT_CLEAR_MU_STA_GTAB_POSITION_L_8814B(x) \ + ((x) & (~BITS_MU_STA_GTAB_POSITION_L_8814B)) +#define BIT_GET_MU_STA_GTAB_POSITION_L_8814B(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B) & \ + BIT_MASK_MU_STA_GTAB_POSITION_L_8814B) +#define BIT_SET_MU_STA_GTAB_POSITION_L_8814B(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_POSITION_L_8814B(x) | \ + BIT_MU_STA_GTAB_POSITION_L_8814B(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_H_8814B */ + +#define BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B 0 +#define BIT_MASK_MU_STA_GTAB_POSITION_H_8814B 0xffffffffL +#define BIT_MU_STA_GTAB_POSITION_H_8814B(x) \ + (((x) & BIT_MASK_MU_STA_GTAB_POSITION_H_8814B) \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B) +#define BITS_MU_STA_GTAB_POSITION_H_8814B \ + (BIT_MASK_MU_STA_GTAB_POSITION_H_8814B \ + << BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B) +#define BIT_CLEAR_MU_STA_GTAB_POSITION_H_8814B(x) \ + ((x) & (~BITS_MU_STA_GTAB_POSITION_H_8814B)) +#define BIT_GET_MU_STA_GTAB_POSITION_H_8814B(x) \ + (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B) & \ + BIT_MASK_MU_STA_GTAB_POSITION_H_8814B) +#define BIT_SET_MU_STA_GTAB_POSITION_H_8814B(x, v) \ + (BIT_CLEAR_MU_STA_GTAB_POSITION_H_8814B(x) | \ + BIT_MU_STA_GTAB_POSITION_H_8814B(v)) + +/* 2 REG_CHNL_INFO_CTRL_8814B */ +#define BIT_CHNL_REF_RXNAV_8814B BIT(7) +#define BIT_CHNL_REF_VBON_8814B BIT(6) +#define BIT_CHNL_REF_EDCA_8814B BIT(5) +#define BIT_CHNL_REF_CCA_8814B BIT(4) +#define BIT_RST_CHNL_BUSY_8814B BIT(3) +#define BIT_RST_CHNL_IDLE_8814B BIT(2) +#define BIT_CHNL_INFO_RST_8814B BIT(1) +#define BIT_ATM_AIRTIME_EN_8814B BIT(0) + +/* 2 REG_CHNL_IDLE_TIME_8814B */ + +#define BIT_SHIFT_CHNL_IDLE_TIME_8814B 0 +#define BIT_MASK_CHNL_IDLE_TIME_8814B 0xffffffffL +#define BIT_CHNL_IDLE_TIME_8814B(x) \ + (((x) & BIT_MASK_CHNL_IDLE_TIME_8814B) \ + << BIT_SHIFT_CHNL_IDLE_TIME_8814B) +#define BITS_CHNL_IDLE_TIME_8814B \ + (BIT_MASK_CHNL_IDLE_TIME_8814B << BIT_SHIFT_CHNL_IDLE_TIME_8814B) +#define BIT_CLEAR_CHNL_IDLE_TIME_8814B(x) ((x) & (~BITS_CHNL_IDLE_TIME_8814B)) +#define BIT_GET_CHNL_IDLE_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8814B) & \ + BIT_MASK_CHNL_IDLE_TIME_8814B) +#define BIT_SET_CHNL_IDLE_TIME_8814B(x, v) \ + (BIT_CLEAR_CHNL_IDLE_TIME_8814B(x) | BIT_CHNL_IDLE_TIME_8814B(v)) + +/* 2 REG_CHNL_BUSY_TIME_8814B */ + +#define BIT_SHIFT_CHNL_BUSY_TIME_8814B 0 +#define BIT_MASK_CHNL_BUSY_TIME_8814B 0xffffffffL +#define BIT_CHNL_BUSY_TIME_8814B(x) \ + (((x) & BIT_MASK_CHNL_BUSY_TIME_8814B) \ + << BIT_SHIFT_CHNL_BUSY_TIME_8814B) +#define BITS_CHNL_BUSY_TIME_8814B \ + (BIT_MASK_CHNL_BUSY_TIME_8814B << BIT_SHIFT_CHNL_BUSY_TIME_8814B) +#define BIT_CLEAR_CHNL_BUSY_TIME_8814B(x) ((x) & (~BITS_CHNL_BUSY_TIME_8814B)) +#define BIT_GET_CHNL_BUSY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8814B) & \ + BIT_MASK_CHNL_BUSY_TIME_8814B) +#define BIT_SET_CHNL_BUSY_TIME_8814B(x, v) \ + (BIT_CLEAR_CHNL_BUSY_TIME_8814B(x) | BIT_CHNL_BUSY_TIME_8814B(v)) + +/* 2 REG_MU_TRX_DBG_CNT_V1_8814B */ +#define BIT_FORCE_SND_STS_EN_8814B BIT(31) + +#define BIT_SHIFT_SND_STS_VALUE_8814B 24 +#define BIT_MASK_SND_STS_VALUE_8814B 0x3f +#define BIT_SND_STS_VALUE_8814B(x) \ + (((x) & BIT_MASK_SND_STS_VALUE_8814B) << BIT_SHIFT_SND_STS_VALUE_8814B) +#define BITS_SND_STS_VALUE_8814B \ + (BIT_MASK_SND_STS_VALUE_8814B << BIT_SHIFT_SND_STS_VALUE_8814B) +#define BIT_CLEAR_SND_STS_VALUE_8814B(x) ((x) & (~BITS_SND_STS_VALUE_8814B)) +#define BIT_GET_SND_STS_VALUE_8814B(x) \ + (((x) >> BIT_SHIFT_SND_STS_VALUE_8814B) & BIT_MASK_SND_STS_VALUE_8814B) +#define BIT_SET_SND_STS_VALUE_8814B(x, v) \ + (BIT_CLEAR_SND_STS_VALUE_8814B(x) | BIT_SND_STS_VALUE_8814B(v)) -/* 2 REG_MU_TRX_DBG_CNT_8814B (NOT SUPPORT) */ #define BIT_MU_DNGCNT_RST_8814B BIT(20) -#define BIT_SHIFT_MU_DBGCNT_SEL_8814B 16 -#define BIT_MASK_MU_DBGCNT_SEL_8814B 0xf -#define BIT_MU_DBGCNT_SEL_8814B(x) (((x) & BIT_MASK_MU_DBGCNT_SEL_8814B) << BIT_SHIFT_MU_DBGCNT_SEL_8814B) -#define BIT_GET_MU_DBGCNT_SEL_8814B(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8814B) & BIT_MASK_MU_DBGCNT_SEL_8814B) - - +#define BIT_SHIFT_MU_DNGCNT_SEL_8814B 16 +#define BIT_MASK_MU_DNGCNT_SEL_8814B 0xf +#define BIT_MU_DNGCNT_SEL_8814B(x) \ + (((x) & BIT_MASK_MU_DNGCNT_SEL_8814B) << BIT_SHIFT_MU_DNGCNT_SEL_8814B) +#define BITS_MU_DNGCNT_SEL_8814B \ + (BIT_MASK_MU_DNGCNT_SEL_8814B << BIT_SHIFT_MU_DNGCNT_SEL_8814B) +#define BIT_CLEAR_MU_DNGCNT_SEL_8814B(x) ((x) & (~BITS_MU_DNGCNT_SEL_8814B)) +#define BIT_GET_MU_DNGCNT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_SEL_8814B) & BIT_MASK_MU_DNGCNT_SEL_8814B) +#define BIT_SET_MU_DNGCNT_SEL_8814B(x, v) \ + (BIT_CLEAR_MU_DNGCNT_SEL_8814B(x) | BIT_MU_DNGCNT_SEL_8814B(v)) #define BIT_SHIFT_MU_DNGCNT_8814B 0 #define BIT_MASK_MU_DNGCNT_8814B 0xffff -#define BIT_MU_DNGCNT_8814B(x) (((x) & BIT_MASK_MU_DNGCNT_8814B) << BIT_SHIFT_MU_DNGCNT_8814B) -#define BIT_GET_MU_DNGCNT_8814B(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8814B) & BIT_MASK_MU_DNGCNT_8814B) - - +#define BIT_MU_DNGCNT_8814B(x) \ + (((x) & BIT_MASK_MU_DNGCNT_8814B) << BIT_SHIFT_MU_DNGCNT_8814B) +#define BITS_MU_DNGCNT_8814B \ + (BIT_MASK_MU_DNGCNT_8814B << BIT_SHIFT_MU_DNGCNT_8814B) +#define BIT_CLEAR_MU_DNGCNT_8814B(x) ((x) & (~BITS_MU_DNGCNT_8814B)) +#define BIT_GET_MU_DNGCNT_8814B(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_8814B) & BIT_MASK_MU_DNGCNT_8814B) +#define BIT_SET_MU_DNGCNT_8814B(x, v) \ + (BIT_CLEAR_MU_DNGCNT_8814B(x) | BIT_MU_DNGCNT_8814B(v)) + +/* 2 REG_SWPS_CTRL_8814B */ + +#define BIT_SHIFT_SWPS_RPT_LENGTH_8814B 8 +#define BIT_MASK_SWPS_RPT_LENGTH_8814B 0x7f +#define BIT_SWPS_RPT_LENGTH_8814B(x) \ + (((x) & BIT_MASK_SWPS_RPT_LENGTH_8814B) \ + << BIT_SHIFT_SWPS_RPT_LENGTH_8814B) +#define BITS_SWPS_RPT_LENGTH_8814B \ + (BIT_MASK_SWPS_RPT_LENGTH_8814B << BIT_SHIFT_SWPS_RPT_LENGTH_8814B) +#define BIT_CLEAR_SWPS_RPT_LENGTH_8814B(x) ((x) & (~BITS_SWPS_RPT_LENGTH_8814B)) +#define BIT_GET_SWPS_RPT_LENGTH_8814B(x) \ + (((x) >> BIT_SHIFT_SWPS_RPT_LENGTH_8814B) & \ + BIT_MASK_SWPS_RPT_LENGTH_8814B) +#define BIT_SET_SWPS_RPT_LENGTH_8814B(x, v) \ + (BIT_CLEAR_SWPS_RPT_LENGTH_8814B(x) | BIT_SWPS_RPT_LENGTH_8814B(v)) + +#define BIT_SHIFT_MACID_SWPS_EN_SEL_8814B 2 +#define BIT_MASK_MACID_SWPS_EN_SEL_8814B 0x3 +#define BIT_MACID_SWPS_EN_SEL_8814B(x) \ + (((x) & BIT_MASK_MACID_SWPS_EN_SEL_8814B) \ + << BIT_SHIFT_MACID_SWPS_EN_SEL_8814B) +#define BITS_MACID_SWPS_EN_SEL_8814B \ + (BIT_MASK_MACID_SWPS_EN_SEL_8814B << BIT_SHIFT_MACID_SWPS_EN_SEL_8814B) +#define BIT_CLEAR_MACID_SWPS_EN_SEL_8814B(x) \ + ((x) & (~BITS_MACID_SWPS_EN_SEL_8814B)) +#define BIT_GET_MACID_SWPS_EN_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_SWPS_EN_SEL_8814B) & \ + BIT_MASK_MACID_SWPS_EN_SEL_8814B) +#define BIT_SET_MACID_SWPS_EN_SEL_8814B(x, v) \ + (BIT_CLEAR_MACID_SWPS_EN_SEL_8814B(x) | BIT_MACID_SWPS_EN_SEL_8814B(v)) + +#define BIT_SWPS_MANUALL_POLLING_8814B BIT(1) +#define BIT_SWPS_EN_8814B BIT(0) + +/* 2 REG_SWPS_PKT_TH_8814B */ + +#define BIT_SHIFT_SWPS_PKT_TH_8814B 0 +#define BIT_MASK_SWPS_PKT_TH_8814B 0xffff +#define BIT_SWPS_PKT_TH_8814B(x) \ + (((x) & BIT_MASK_SWPS_PKT_TH_8814B) << BIT_SHIFT_SWPS_PKT_TH_8814B) +#define BITS_SWPS_PKT_TH_8814B \ + (BIT_MASK_SWPS_PKT_TH_8814B << BIT_SHIFT_SWPS_PKT_TH_8814B) +#define BIT_CLEAR_SWPS_PKT_TH_8814B(x) ((x) & (~BITS_SWPS_PKT_TH_8814B)) +#define BIT_GET_SWPS_PKT_TH_8814B(x) \ + (((x) >> BIT_SHIFT_SWPS_PKT_TH_8814B) & BIT_MASK_SWPS_PKT_TH_8814B) +#define BIT_SET_SWPS_PKT_TH_8814B(x, v) \ + (BIT_CLEAR_SWPS_PKT_TH_8814B(x) | BIT_SWPS_PKT_TH_8814B(v)) + +/* 2 REG_SWPS_TIME_TH_8814B */ + +#define BIT_SHIFT_SWPS_PSTIME_TH_8814B 16 +#define BIT_MASK_SWPS_PSTIME_TH_8814B 0xffff +#define BIT_SWPS_PSTIME_TH_8814B(x) \ + (((x) & BIT_MASK_SWPS_PSTIME_TH_8814B) \ + << BIT_SHIFT_SWPS_PSTIME_TH_8814B) +#define BITS_SWPS_PSTIME_TH_8814B \ + (BIT_MASK_SWPS_PSTIME_TH_8814B << BIT_SHIFT_SWPS_PSTIME_TH_8814B) +#define BIT_CLEAR_SWPS_PSTIME_TH_8814B(x) ((x) & (~BITS_SWPS_PSTIME_TH_8814B)) +#define BIT_GET_SWPS_PSTIME_TH_8814B(x) \ + (((x) >> BIT_SHIFT_SWPS_PSTIME_TH_8814B) & \ + BIT_MASK_SWPS_PSTIME_TH_8814B) +#define BIT_SET_SWPS_PSTIME_TH_8814B(x, v) \ + (BIT_CLEAR_SWPS_PSTIME_TH_8814B(x) | BIT_SWPS_PSTIME_TH_8814B(v)) + +#define BIT_SHIFT_SWPS_TIME_TH_8814B 0 +#define BIT_MASK_SWPS_TIME_TH_8814B 0xffff +#define BIT_SWPS_TIME_TH_8814B(x) \ + (((x) & BIT_MASK_SWPS_TIME_TH_8814B) << BIT_SHIFT_SWPS_TIME_TH_8814B) +#define BITS_SWPS_TIME_TH_8814B \ + (BIT_MASK_SWPS_TIME_TH_8814B << BIT_SHIFT_SWPS_TIME_TH_8814B) +#define BIT_CLEAR_SWPS_TIME_TH_8814B(x) ((x) & (~BITS_SWPS_TIME_TH_8814B)) +#define BIT_GET_SWPS_TIME_TH_8814B(x) \ + (((x) >> BIT_SHIFT_SWPS_TIME_TH_8814B) & BIT_MASK_SWPS_TIME_TH_8814B) +#define BIT_SET_SWPS_TIME_TH_8814B(x, v) \ + (BIT_CLEAR_SWPS_TIME_TH_8814B(x) | BIT_SWPS_TIME_TH_8814B(v)) + +/* 2 REG_MACID_SWPS_EN_8814B */ + +#define BIT_SHIFT_MACID_SWPS_EN_8814B 0 +#define BIT_MASK_MACID_SWPS_EN_8814B 0xffffffffL +#define BIT_MACID_SWPS_EN_8814B(x) \ + (((x) & BIT_MASK_MACID_SWPS_EN_8814B) << BIT_SHIFT_MACID_SWPS_EN_8814B) +#define BITS_MACID_SWPS_EN_8814B \ + (BIT_MASK_MACID_SWPS_EN_8814B << BIT_SHIFT_MACID_SWPS_EN_8814B) +#define BIT_CLEAR_MACID_SWPS_EN_8814B(x) ((x) & (~BITS_MACID_SWPS_EN_8814B)) +#define BIT_GET_MACID_SWPS_EN_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_SWPS_EN_8814B) & BIT_MASK_MACID_SWPS_EN_8814B) +#define BIT_SET_MACID_SWPS_EN_8814B(x, v) \ + (BIT_CLEAR_MACID_SWPS_EN_8814B(x) | BIT_MACID_SWPS_EN_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -7110,24 +17141,32 @@ #define BIT_SHIFT_TXOPLIMIT_8814B 16 #define BIT_MASK_TXOPLIMIT_8814B 0x7ff -#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) -#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) - - +#define BIT_TXOPLIMIT_8814B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BITS_TXOPLIMIT_8814B \ + (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B)) +#define BIT_GET_TXOPLIMIT_8814B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) +#define BIT_SET_TXOPLIMIT_8814B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v)) #define BIT_SHIFT_CW_8814B 8 #define BIT_MASK_CW_8814B 0xff #define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B) +#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B)) #define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) - - +#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v)) #define BIT_SHIFT_AIFS_8814B 0 #define BIT_MASK_AIFS_8814B 0xff #define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) -#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) - - +#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B) +#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B)) +#define BIT_GET_AIFS_8814B(x) \ + (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) +#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v)) /* 2 REG_EDCA_VI_PARAM_8814B */ @@ -7135,24 +17174,32 @@ #define BIT_SHIFT_TXOPLIMIT_8814B 16 #define BIT_MASK_TXOPLIMIT_8814B 0x7ff -#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) -#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) - - +#define BIT_TXOPLIMIT_8814B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BITS_TXOPLIMIT_8814B \ + (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B)) +#define BIT_GET_TXOPLIMIT_8814B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) +#define BIT_SET_TXOPLIMIT_8814B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v)) #define BIT_SHIFT_CW_8814B 8 #define BIT_MASK_CW_8814B 0xff #define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B) +#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B)) #define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) - - +#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v)) #define BIT_SHIFT_AIFS_8814B 0 #define BIT_MASK_AIFS_8814B 0xff #define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) -#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) - - +#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B) +#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B)) +#define BIT_GET_AIFS_8814B(x) \ + (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) +#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v)) /* 2 REG_EDCA_BE_PARAM_8814B */ @@ -7160,24 +17207,32 @@ #define BIT_SHIFT_TXOPLIMIT_8814B 16 #define BIT_MASK_TXOPLIMIT_8814B 0x7ff -#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) -#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) - - +#define BIT_TXOPLIMIT_8814B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BITS_TXOPLIMIT_8814B \ + (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B)) +#define BIT_GET_TXOPLIMIT_8814B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) +#define BIT_SET_TXOPLIMIT_8814B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v)) #define BIT_SHIFT_CW_8814B 8 #define BIT_MASK_CW_8814B 0xff #define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B) +#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B)) #define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) - - +#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v)) #define BIT_SHIFT_AIFS_8814B 0 #define BIT_MASK_AIFS_8814B 0xff #define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) -#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) - - +#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B) +#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B)) +#define BIT_GET_AIFS_8814B(x) \ + (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) +#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v)) /* 2 REG_EDCA_BK_PARAM_8814B */ @@ -7185,124 +17240,212 @@ #define BIT_SHIFT_TXOPLIMIT_8814B 16 #define BIT_MASK_TXOPLIMIT_8814B 0x7ff -#define BIT_TXOPLIMIT_8814B(x) (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) -#define BIT_GET_TXOPLIMIT_8814B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) - - +#define BIT_TXOPLIMIT_8814B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B) +#define BITS_TXOPLIMIT_8814B \ + (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B) +#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B)) +#define BIT_GET_TXOPLIMIT_8814B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B) +#define BIT_SET_TXOPLIMIT_8814B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v)) #define BIT_SHIFT_CW_8814B 8 #define BIT_MASK_CW_8814B 0xff #define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B) +#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B) +#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B)) #define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B) - - +#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v)) #define BIT_SHIFT_AIFS_8814B 0 #define BIT_MASK_AIFS_8814B 0xff #define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B) -#define BIT_GET_AIFS_8814B(x) (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) - - +#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B) +#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B)) +#define BIT_GET_AIFS_8814B(x) \ + (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B) +#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v)) /* 2 REG_BCNTCFG_8814B */ #define BIT_SHIFT_BCNCW_MAX_8814B 12 #define BIT_MASK_BCNCW_MAX_8814B 0xf -#define BIT_BCNCW_MAX_8814B(x) (((x) & BIT_MASK_BCNCW_MAX_8814B) << BIT_SHIFT_BCNCW_MAX_8814B) -#define BIT_GET_BCNCW_MAX_8814B(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8814B) & BIT_MASK_BCNCW_MAX_8814B) - - +#define BIT_BCNCW_MAX_8814B(x) \ + (((x) & BIT_MASK_BCNCW_MAX_8814B) << BIT_SHIFT_BCNCW_MAX_8814B) +#define BITS_BCNCW_MAX_8814B \ + (BIT_MASK_BCNCW_MAX_8814B << BIT_SHIFT_BCNCW_MAX_8814B) +#define BIT_CLEAR_BCNCW_MAX_8814B(x) ((x) & (~BITS_BCNCW_MAX_8814B)) +#define BIT_GET_BCNCW_MAX_8814B(x) \ + (((x) >> BIT_SHIFT_BCNCW_MAX_8814B) & BIT_MASK_BCNCW_MAX_8814B) +#define BIT_SET_BCNCW_MAX_8814B(x, v) \ + (BIT_CLEAR_BCNCW_MAX_8814B(x) | BIT_BCNCW_MAX_8814B(v)) #define BIT_SHIFT_BCNCW_MIN_8814B 8 #define BIT_MASK_BCNCW_MIN_8814B 0xf -#define BIT_BCNCW_MIN_8814B(x) (((x) & BIT_MASK_BCNCW_MIN_8814B) << BIT_SHIFT_BCNCW_MIN_8814B) -#define BIT_GET_BCNCW_MIN_8814B(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8814B) & BIT_MASK_BCNCW_MIN_8814B) - - +#define BIT_BCNCW_MIN_8814B(x) \ + (((x) & BIT_MASK_BCNCW_MIN_8814B) << BIT_SHIFT_BCNCW_MIN_8814B) +#define BITS_BCNCW_MIN_8814B \ + (BIT_MASK_BCNCW_MIN_8814B << BIT_SHIFT_BCNCW_MIN_8814B) +#define BIT_CLEAR_BCNCW_MIN_8814B(x) ((x) & (~BITS_BCNCW_MIN_8814B)) +#define BIT_GET_BCNCW_MIN_8814B(x) \ + (((x) >> BIT_SHIFT_BCNCW_MIN_8814B) & BIT_MASK_BCNCW_MIN_8814B) +#define BIT_SET_BCNCW_MIN_8814B(x, v) \ + (BIT_CLEAR_BCNCW_MIN_8814B(x) | BIT_BCNCW_MIN_8814B(v)) #define BIT_SHIFT_BCNIFS_8814B 0 #define BIT_MASK_BCNIFS_8814B 0xff -#define BIT_BCNIFS_8814B(x) (((x) & BIT_MASK_BCNIFS_8814B) << BIT_SHIFT_BCNIFS_8814B) -#define BIT_GET_BCNIFS_8814B(x) (((x) >> BIT_SHIFT_BCNIFS_8814B) & BIT_MASK_BCNIFS_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_BCNIFS_8814B(x) \ + (((x) & BIT_MASK_BCNIFS_8814B) << BIT_SHIFT_BCNIFS_8814B) +#define BITS_BCNIFS_8814B (BIT_MASK_BCNIFS_8814B << BIT_SHIFT_BCNIFS_8814B) +#define BIT_CLEAR_BCNIFS_8814B(x) ((x) & (~BITS_BCNIFS_8814B)) +#define BIT_GET_BCNIFS_8814B(x) \ + (((x) >> BIT_SHIFT_BCNIFS_8814B) & BIT_MASK_BCNIFS_8814B) +#define BIT_SET_BCNIFS_8814B(x, v) \ + (BIT_CLEAR_BCNIFS_8814B(x) | BIT_BCNIFS_8814B(v)) /* 2 REG_PIFS_8814B */ #define BIT_SHIFT_PIFS_8814B 0 #define BIT_MASK_PIFS_8814B 0xff #define BIT_PIFS_8814B(x) (((x) & BIT_MASK_PIFS_8814B) << BIT_SHIFT_PIFS_8814B) -#define BIT_GET_PIFS_8814B(x) (((x) >> BIT_SHIFT_PIFS_8814B) & BIT_MASK_PIFS_8814B) - - +#define BITS_PIFS_8814B (BIT_MASK_PIFS_8814B << BIT_SHIFT_PIFS_8814B) +#define BIT_CLEAR_PIFS_8814B(x) ((x) & (~BITS_PIFS_8814B)) +#define BIT_GET_PIFS_8814B(x) \ + (((x) >> BIT_SHIFT_PIFS_8814B) & BIT_MASK_PIFS_8814B) +#define BIT_SET_PIFS_8814B(x, v) (BIT_CLEAR_PIFS_8814B(x) | BIT_PIFS_8814B(v)) /* 2 REG_RDG_PIFS_8814B */ #define BIT_SHIFT_RDG_PIFS_8814B 0 #define BIT_MASK_RDG_PIFS_8814B 0xff -#define BIT_RDG_PIFS_8814B(x) (((x) & BIT_MASK_RDG_PIFS_8814B) << BIT_SHIFT_RDG_PIFS_8814B) -#define BIT_GET_RDG_PIFS_8814B(x) (((x) >> BIT_SHIFT_RDG_PIFS_8814B) & BIT_MASK_RDG_PIFS_8814B) - - +#define BIT_RDG_PIFS_8814B(x) \ + (((x) & BIT_MASK_RDG_PIFS_8814B) << BIT_SHIFT_RDG_PIFS_8814B) +#define BITS_RDG_PIFS_8814B \ + (BIT_MASK_RDG_PIFS_8814B << BIT_SHIFT_RDG_PIFS_8814B) +#define BIT_CLEAR_RDG_PIFS_8814B(x) ((x) & (~BITS_RDG_PIFS_8814B)) +#define BIT_GET_RDG_PIFS_8814B(x) \ + (((x) >> BIT_SHIFT_RDG_PIFS_8814B) & BIT_MASK_RDG_PIFS_8814B) +#define BIT_SET_RDG_PIFS_8814B(x, v) \ + (BIT_CLEAR_RDG_PIFS_8814B(x) | BIT_RDG_PIFS_8814B(v)) /* 2 REG_SIFS_8814B */ #define BIT_SHIFT_SIFS_OFDM_TRX_8814B 24 #define BIT_MASK_SIFS_OFDM_TRX_8814B 0xff -#define BIT_SIFS_OFDM_TRX_8814B(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8814B) << BIT_SHIFT_SIFS_OFDM_TRX_8814B) -#define BIT_GET_SIFS_OFDM_TRX_8814B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8814B) & BIT_MASK_SIFS_OFDM_TRX_8814B) - - +#define BIT_SIFS_OFDM_TRX_8814B(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX_8814B) << BIT_SHIFT_SIFS_OFDM_TRX_8814B) +#define BITS_SIFS_OFDM_TRX_8814B \ + (BIT_MASK_SIFS_OFDM_TRX_8814B << BIT_SHIFT_SIFS_OFDM_TRX_8814B) +#define BIT_CLEAR_SIFS_OFDM_TRX_8814B(x) ((x) & (~BITS_SIFS_OFDM_TRX_8814B)) +#define BIT_GET_SIFS_OFDM_TRX_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8814B) & BIT_MASK_SIFS_OFDM_TRX_8814B) +#define BIT_SET_SIFS_OFDM_TRX_8814B(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX_8814B(x) | BIT_SIFS_OFDM_TRX_8814B(v)) #define BIT_SHIFT_SIFS_CCK_TRX_8814B 16 #define BIT_MASK_SIFS_CCK_TRX_8814B 0xff -#define BIT_SIFS_CCK_TRX_8814B(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8814B) << BIT_SHIFT_SIFS_CCK_TRX_8814B) -#define BIT_GET_SIFS_CCK_TRX_8814B(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8814B) & BIT_MASK_SIFS_CCK_TRX_8814B) - - +#define BIT_SIFS_CCK_TRX_8814B(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX_8814B) << BIT_SHIFT_SIFS_CCK_TRX_8814B) +#define BITS_SIFS_CCK_TRX_8814B \ + (BIT_MASK_SIFS_CCK_TRX_8814B << BIT_SHIFT_SIFS_CCK_TRX_8814B) +#define BIT_CLEAR_SIFS_CCK_TRX_8814B(x) ((x) & (~BITS_SIFS_CCK_TRX_8814B)) +#define BIT_GET_SIFS_CCK_TRX_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8814B) & BIT_MASK_SIFS_CCK_TRX_8814B) +#define BIT_SET_SIFS_CCK_TRX_8814B(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX_8814B(x) | BIT_SIFS_CCK_TRX_8814B(v)) #define BIT_SHIFT_SIFS_OFDM_CTX_8814B 8 #define BIT_MASK_SIFS_OFDM_CTX_8814B 0xff -#define BIT_SIFS_OFDM_CTX_8814B(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8814B) << BIT_SHIFT_SIFS_OFDM_CTX_8814B) -#define BIT_GET_SIFS_OFDM_CTX_8814B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8814B) & BIT_MASK_SIFS_OFDM_CTX_8814B) - - +#define BIT_SIFS_OFDM_CTX_8814B(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX_8814B) << BIT_SHIFT_SIFS_OFDM_CTX_8814B) +#define BITS_SIFS_OFDM_CTX_8814B \ + (BIT_MASK_SIFS_OFDM_CTX_8814B << BIT_SHIFT_SIFS_OFDM_CTX_8814B) +#define BIT_CLEAR_SIFS_OFDM_CTX_8814B(x) ((x) & (~BITS_SIFS_OFDM_CTX_8814B)) +#define BIT_GET_SIFS_OFDM_CTX_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8814B) & BIT_MASK_SIFS_OFDM_CTX_8814B) +#define BIT_SET_SIFS_OFDM_CTX_8814B(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX_8814B(x) | BIT_SIFS_OFDM_CTX_8814B(v)) #define BIT_SHIFT_SIFS_CCK_CTX_8814B 0 #define BIT_MASK_SIFS_CCK_CTX_8814B 0xff -#define BIT_SIFS_CCK_CTX_8814B(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8814B) << BIT_SHIFT_SIFS_CCK_CTX_8814B) -#define BIT_GET_SIFS_CCK_CTX_8814B(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8814B) & BIT_MASK_SIFS_CCK_CTX_8814B) - - - -/* 2 REG_TSFTR_SYN_OFFSET_8814B */ - -#define BIT_SHIFT_TSFTR_SNC_OFFSET_8814B 0 -#define BIT_MASK_TSFTR_SNC_OFFSET_8814B 0xffff -#define BIT_TSFTR_SNC_OFFSET_8814B(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8814B) << BIT_SHIFT_TSFTR_SNC_OFFSET_8814B) -#define BIT_GET_TSFTR_SNC_OFFSET_8814B(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8814B) & BIT_MASK_TSFTR_SNC_OFFSET_8814B) +#define BIT_SIFS_CCK_CTX_8814B(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX_8814B) << BIT_SHIFT_SIFS_CCK_CTX_8814B) +#define BITS_SIFS_CCK_CTX_8814B \ + (BIT_MASK_SIFS_CCK_CTX_8814B << BIT_SHIFT_SIFS_CCK_CTX_8814B) +#define BIT_CLEAR_SIFS_CCK_CTX_8814B(x) ((x) & (~BITS_SIFS_CCK_CTX_8814B)) +#define BIT_GET_SIFS_CCK_CTX_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8814B) & BIT_MASK_SIFS_CCK_CTX_8814B) +#define BIT_SET_SIFS_CCK_CTX_8814B(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX_8814B(x) | BIT_SIFS_CCK_CTX_8814B(v)) + +/* 2 REG_FORCE_BCN_IFS_V1_8814B */ +#define BIT_SHIFT_FORCE_BCN_IFS_8814B 0 +#define BIT_MASK_FORCE_BCN_IFS_8814B 0xff +#define BIT_FORCE_BCN_IFS_8814B(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS_8814B) << BIT_SHIFT_FORCE_BCN_IFS_8814B) +#define BITS_FORCE_BCN_IFS_8814B \ + (BIT_MASK_FORCE_BCN_IFS_8814B << BIT_SHIFT_FORCE_BCN_IFS_8814B) +#define BIT_CLEAR_FORCE_BCN_IFS_8814B(x) ((x) & (~BITS_FORCE_BCN_IFS_8814B)) +#define BIT_GET_FORCE_BCN_IFS_8814B(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8814B) & BIT_MASK_FORCE_BCN_IFS_8814B) +#define BIT_SET_FORCE_BCN_IFS_8814B(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS_8814B(x) | BIT_FORCE_BCN_IFS_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_AGGR_BREAK_TIME_8814B */ #define BIT_SHIFT_AGGR_BK_TIME_8814B 0 #define BIT_MASK_AGGR_BK_TIME_8814B 0xff -#define BIT_AGGR_BK_TIME_8814B(x) (((x) & BIT_MASK_AGGR_BK_TIME_8814B) << BIT_SHIFT_AGGR_BK_TIME_8814B) -#define BIT_GET_AGGR_BK_TIME_8814B(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8814B) & BIT_MASK_AGGR_BK_TIME_8814B) - - +#define BIT_AGGR_BK_TIME_8814B(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME_8814B) << BIT_SHIFT_AGGR_BK_TIME_8814B) +#define BITS_AGGR_BK_TIME_8814B \ + (BIT_MASK_AGGR_BK_TIME_8814B << BIT_SHIFT_AGGR_BK_TIME_8814B) +#define BIT_CLEAR_AGGR_BK_TIME_8814B(x) ((x) & (~BITS_AGGR_BK_TIME_8814B)) +#define BIT_GET_AGGR_BK_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME_8814B) & BIT_MASK_AGGR_BK_TIME_8814B) +#define BIT_SET_AGGR_BK_TIME_8814B(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME_8814B(x) | BIT_AGGR_BK_TIME_8814B(v)) /* 2 REG_SLOT_8814B */ #define BIT_SHIFT_SLOT_8814B 0 #define BIT_MASK_SLOT_8814B 0xff #define BIT_SLOT_8814B(x) (((x) & BIT_MASK_SLOT_8814B) << BIT_SHIFT_SLOT_8814B) -#define BIT_GET_SLOT_8814B(x) (((x) >> BIT_SHIFT_SLOT_8814B) & BIT_MASK_SLOT_8814B) - - +#define BITS_SLOT_8814B (BIT_MASK_SLOT_8814B << BIT_SHIFT_SLOT_8814B) +#define BIT_CLEAR_SLOT_8814B(x) ((x) & (~BITS_SLOT_8814B)) +#define BIT_GET_SLOT_8814B(x) \ + (((x) >> BIT_SHIFT_SLOT_8814B) & BIT_MASK_SLOT_8814B) +#define BIT_SET_SLOT_8814B(x, v) (BIT_CLEAR_SLOT_8814B(x) | BIT_SLOT_8814B(v)) + +/* 2 REG_EDCA_CPUMGQ_PARAM_8814B */ + +#define BIT_SHIFT_CW_V1_8814B 8 +#define BIT_MASK_CW_V1_8814B 0xff +#define BIT_CW_V1_8814B(x) \ + (((x) & BIT_MASK_CW_V1_8814B) << BIT_SHIFT_CW_V1_8814B) +#define BITS_CW_V1_8814B (BIT_MASK_CW_V1_8814B << BIT_SHIFT_CW_V1_8814B) +#define BIT_CLEAR_CW_V1_8814B(x) ((x) & (~BITS_CW_V1_8814B)) +#define BIT_GET_CW_V1_8814B(x) \ + (((x) >> BIT_SHIFT_CW_V1_8814B) & BIT_MASK_CW_V1_8814B) +#define BIT_SET_CW_V1_8814B(x, v) \ + (BIT_CLEAR_CW_V1_8814B(x) | BIT_CW_V1_8814B(v)) + +#define BIT_SHIFT_AIFS_V1_8814B 0 +#define BIT_MASK_AIFS_V1_8814B 0xff +#define BIT_AIFS_V1_8814B(x) \ + (((x) & BIT_MASK_AIFS_V1_8814B) << BIT_SHIFT_AIFS_V1_8814B) +#define BITS_AIFS_V1_8814B (BIT_MASK_AIFS_V1_8814B << BIT_SHIFT_AIFS_V1_8814B) +#define BIT_CLEAR_AIFS_V1_8814B(x) ((x) & (~BITS_AIFS_V1_8814B)) +#define BIT_GET_AIFS_V1_8814B(x) \ + (((x) >> BIT_SHIFT_AIFS_V1_8814B) & BIT_MASK_AIFS_V1_8814B) +#define BIT_SET_AIFS_V1_8814B(x, v) \ + (BIT_CLEAR_AIFS_V1_8814B(x) | BIT_AIFS_V1_8814B(v)) + +/* 2 REG_CPUMGQ_PAUSE_8814B */ +#define BIT_MAC_STOP_CPUMGQ_V1_8814B BIT(0) /* 2 REG_NOT_VALID_8814B */ @@ -7314,9 +17457,15 @@ #define BIT_SHIFT_TXQ_NAV_MSK_8814B 8 #define BIT_MASK_TXQ_NAV_MSK_8814B 0xf -#define BIT_TXQ_NAV_MSK_8814B(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8814B) << BIT_SHIFT_TXQ_NAV_MSK_8814B) -#define BIT_GET_TXQ_NAV_MSK_8814B(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8814B) & BIT_MASK_TXQ_NAV_MSK_8814B) - +#define BIT_TXQ_NAV_MSK_8814B(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK_8814B) << BIT_SHIFT_TXQ_NAV_MSK_8814B) +#define BITS_TXQ_NAV_MSK_8814B \ + (BIT_MASK_TXQ_NAV_MSK_8814B << BIT_SHIFT_TXQ_NAV_MSK_8814B) +#define BIT_CLEAR_TXQ_NAV_MSK_8814B(x) ((x) & (~BITS_TXQ_NAV_MSK_8814B)) +#define BIT_GET_TXQ_NAV_MSK_8814B(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8814B) & BIT_MASK_TXQ_NAV_MSK_8814B) +#define BIT_SET_TXQ_NAV_MSK_8814B(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK_8814B(x) | BIT_TXQ_NAV_MSK_8814B(v)) #define BIT_DIS_CW_8814B BIT(7) #define BIT_NAV_END_TXOP_8814B BIT(6) @@ -7353,7 +17502,6 @@ #define BIT_EDCCA_MSK_CNTDOWN_EN_8814B BIT(11) #define BIT_DIS_TXOP_CFE_8814B BIT(10) #define BIT_DIS_LSIG_CFE_8814B BIT(9) -#define BIT_DIS_STBC_CFE_8814B BIT(8) #define BIT_BKQ_RD_INIT_EN_8814B BIT(7) #define BIT_BEQ_RD_INIT_EN_8814B BIT(6) #define BIT_VIQ_RD_INIT_EN_8814B BIT(5) @@ -7363,27 +17511,13 @@ #define BIT_VIQ_RD_RESP_EN_8814B BIT(1) #define BIT_VOQ_RD_RESP_EN_8814B BIT(0) -/* 2 REG_MBSSID_CTRL_8814B */ -#define BIT_MBID_BCNQ7_EN_8814B BIT(7) -#define BIT_MBID_BCNQ6_EN_8814B BIT(6) -#define BIT_MBID_BCNQ5_EN_8814B BIT(5) -#define BIT_MBID_BCNQ4_EN_8814B BIT(4) -#define BIT_MBID_BCNQ3_EN_8814B BIT(3) -#define BIT_MBID_BCNQ2_EN_8814B BIT(2) -#define BIT_MBID_BCNQ1_EN_8814B BIT(1) -#define BIT_MBID_BCNQ0_EN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2PPS_CTRL_8814B */ -#define BIT_P2P_CTW_ALLSTASLEEP_8814B BIT(7) -#define BIT_P2P_OFF_DISTX_EN_8814B BIT(6) -#define BIT_PWR_MGT_EN_8814B BIT(5) -#define BIT_P2P_NOA1_EN_8814B BIT(2) -#define BIT_P2P_NOA0_EN_8814B BIT(1) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_PKT_LIFETIME_CTRL_8814B */ #define BIT_EN_P2P_CTWND1_8814B BIT(23) #define BIT_EN_BKF_CLR_TXREQ_8814B BIT(22) -#define BIT_EN_TSFBIT32_RST_P2P_8814B BIT(21) #define BIT_EN_BCN_TX_BTCCA_8814B BIT(20) #define BIT_DIS_PKT_TX_ATIM_8814B BIT(19) #define BIT_DIS_BCN_DIS_CTN_8814B BIT(18) @@ -7392,379 +17526,1611 @@ #define BIT_SHIFT_CCA_FILTER_THRS_8814B 8 #define BIT_MASK_CCA_FILTER_THRS_8814B 0xff -#define BIT_CCA_FILTER_THRS_8814B(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8814B) << BIT_SHIFT_CCA_FILTER_THRS_8814B) -#define BIT_GET_CCA_FILTER_THRS_8814B(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8814B) & BIT_MASK_CCA_FILTER_THRS_8814B) - - +#define BIT_CCA_FILTER_THRS_8814B(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS_8814B) \ + << BIT_SHIFT_CCA_FILTER_THRS_8814B) +#define BITS_CCA_FILTER_THRS_8814B \ + (BIT_MASK_CCA_FILTER_THRS_8814B << BIT_SHIFT_CCA_FILTER_THRS_8814B) +#define BIT_CLEAR_CCA_FILTER_THRS_8814B(x) ((x) & (~BITS_CCA_FILTER_THRS_8814B)) +#define BIT_GET_CCA_FILTER_THRS_8814B(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8814B) & \ + BIT_MASK_CCA_FILTER_THRS_8814B) +#define BIT_SET_CCA_FILTER_THRS_8814B(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS_8814B(x) | BIT_CCA_FILTER_THRS_8814B(v)) #define BIT_SHIFT_EDCCA_THRS_8814B 0 #define BIT_MASK_EDCCA_THRS_8814B 0xff -#define BIT_EDCCA_THRS_8814B(x) (((x) & BIT_MASK_EDCCA_THRS_8814B) << BIT_SHIFT_EDCCA_THRS_8814B) -#define BIT_GET_EDCCA_THRS_8814B(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8814B) & BIT_MASK_EDCCA_THRS_8814B) +#define BIT_EDCCA_THRS_8814B(x) \ + (((x) & BIT_MASK_EDCCA_THRS_8814B) << BIT_SHIFT_EDCCA_THRS_8814B) +#define BITS_EDCCA_THRS_8814B \ + (BIT_MASK_EDCCA_THRS_8814B << BIT_SHIFT_EDCCA_THRS_8814B) +#define BIT_CLEAR_EDCCA_THRS_8814B(x) ((x) & (~BITS_EDCCA_THRS_8814B)) +#define BIT_GET_EDCCA_THRS_8814B(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS_8814B) & BIT_MASK_EDCCA_THRS_8814B) +#define BIT_SET_EDCCA_THRS_8814B(x, v) \ + (BIT_CLEAR_EDCCA_THRS_8814B(x) | BIT_EDCCA_THRS_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_TXOP_LIMIT_CTRL_8814B */ + +#define BIT_SHIFT_TXOP_TBTT_CNT_8814B 24 +#define BIT_MASK_TXOP_TBTT_CNT_8814B 0xff +#define BIT_TXOP_TBTT_CNT_8814B(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_8814B) << BIT_SHIFT_TXOP_TBTT_CNT_8814B) +#define BITS_TXOP_TBTT_CNT_8814B \ + (BIT_MASK_TXOP_TBTT_CNT_8814B << BIT_SHIFT_TXOP_TBTT_CNT_8814B) +#define BIT_CLEAR_TXOP_TBTT_CNT_8814B(x) ((x) & (~BITS_TXOP_TBTT_CNT_8814B)) +#define BIT_GET_TXOP_TBTT_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8814B) & BIT_MASK_TXOP_TBTT_CNT_8814B) +#define BIT_SET_TXOP_TBTT_CNT_8814B(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_8814B(x) | BIT_TXOP_TBTT_CNT_8814B(v)) + +#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B 20 +#define BIT_MASK_TXOP_TBTT_CNT_SEL_8814B 0xf +#define BIT_TXOP_TBTT_CNT_SEL_8814B(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8814B) \ + << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B) +#define BITS_TXOP_TBTT_CNT_SEL_8814B \ + (BIT_MASK_TXOP_TBTT_CNT_SEL_8814B << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B) +#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8814B(x) \ + ((x) & (~BITS_TXOP_TBTT_CNT_SEL_8814B)) +#define BIT_GET_TXOP_TBTT_CNT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B) & \ + BIT_MASK_TXOP_TBTT_CNT_SEL_8814B) +#define BIT_SET_TXOP_TBTT_CNT_SEL_8814B(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_SEL_8814B(x) | BIT_TXOP_TBTT_CNT_SEL_8814B(v)) + +#define BIT_SHIFT_TXOP_LMT_EN_8814B 16 +#define BIT_MASK_TXOP_LMT_EN_8814B 0xf +#define BIT_TXOP_LMT_EN_8814B(x) \ + (((x) & BIT_MASK_TXOP_LMT_EN_8814B) << BIT_SHIFT_TXOP_LMT_EN_8814B) +#define BITS_TXOP_LMT_EN_8814B \ + (BIT_MASK_TXOP_LMT_EN_8814B << BIT_SHIFT_TXOP_LMT_EN_8814B) +#define BIT_CLEAR_TXOP_LMT_EN_8814B(x) ((x) & (~BITS_TXOP_LMT_EN_8814B)) +#define BIT_GET_TXOP_LMT_EN_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_EN_8814B) & BIT_MASK_TXOP_LMT_EN_8814B) +#define BIT_SET_TXOP_LMT_EN_8814B(x, v) \ + (BIT_CLEAR_TXOP_LMT_EN_8814B(x) | BIT_TXOP_LMT_EN_8814B(v)) + +#define BIT_SHIFT_TXOP_LMT_TX_TIME_8814B 8 +#define BIT_MASK_TXOP_LMT_TX_TIME_8814B 0xff +#define BIT_TXOP_LMT_TX_TIME_8814B(x) \ + (((x) & BIT_MASK_TXOP_LMT_TX_TIME_8814B) \ + << BIT_SHIFT_TXOP_LMT_TX_TIME_8814B) +#define BITS_TXOP_LMT_TX_TIME_8814B \ + (BIT_MASK_TXOP_LMT_TX_TIME_8814B << BIT_SHIFT_TXOP_LMT_TX_TIME_8814B) +#define BIT_CLEAR_TXOP_LMT_TX_TIME_8814B(x) \ + ((x) & (~BITS_TXOP_LMT_TX_TIME_8814B)) +#define BIT_GET_TXOP_LMT_TX_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8814B) & \ + BIT_MASK_TXOP_LMT_TX_TIME_8814B) +#define BIT_SET_TXOP_LMT_TX_TIME_8814B(x, v) \ + (BIT_CLEAR_TXOP_LMT_TX_TIME_8814B(x) | BIT_TXOP_LMT_TX_TIME_8814B(v)) + +#define BIT_TXOP_CNT_TRIGGER_RESET_8814B BIT(7) + +#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B 0 +#define BIT_MASK_TXOP_LMT_PKT_NUM_8814B 0x3f +#define BIT_TXOP_LMT_PKT_NUM_8814B(x) \ + (((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8814B) \ + << BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B) +#define BITS_TXOP_LMT_PKT_NUM_8814B \ + (BIT_MASK_TXOP_LMT_PKT_NUM_8814B << BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B) +#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8814B(x) \ + ((x) & (~BITS_TXOP_LMT_PKT_NUM_8814B)) +#define BIT_GET_TXOP_LMT_PKT_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B) & \ + BIT_MASK_TXOP_LMT_PKT_NUM_8814B) +#define BIT_SET_TXOP_LMT_PKT_NUM_8814B(x, v) \ + (BIT_CLEAR_TXOP_LMT_PKT_NUM_8814B(x) | BIT_TXOP_LMT_PKT_NUM_8814B(v)) -/* 2 REG_P2PPS_SPEC_STATE_8814B */ -#define BIT_SPEC_POWER_STATE_8814B BIT(7) -#define BIT_SPEC_CTWINDOW_ON_8814B BIT(6) -#define BIT_SPEC_BEACON_AREA_ON_8814B BIT(5) -#define BIT_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4) -#define BIT_SPEC_NOA1_OFF_PERIOD_8814B BIT(3) -#define BIT_SPEC_FORCE_DOZE1_8814B BIT(2) -#define BIT_SPEC_NOA0_OFF_PERIOD_8814B BIT(1) -#define BIT_SPEC_FORCE_DOZE0_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BAR_TX_CTRL_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_P2PON_DIS_TXTIME_8814B 0 -#define BIT_MASK_P2PON_DIS_TXTIME_8814B 0xff -#define BIT_P2PON_DIS_TXTIME_8814B(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8814B) << BIT_SHIFT_P2PON_DIS_TXTIME_8814B) -#define BIT_GET_P2PON_DIS_TXTIME_8814B(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8814B) & BIT_MASK_P2PON_DIS_TXTIME_8814B) +/* 2 REG_CCA_TXEN_CNT_8814B */ +#define BIT_ENABLE_STOP_UPDATE_NAV_8814B BIT(21) +#define BIT_ENABLE_GEN_RANDON_SLOT_TX_8814B BIT(20) +#define BIT_ENABLE_RANDOM_SHIFT_TX_8814B BIT(19) +#define BIT_ENABLE_EDCA_REF_FUNCTION_8814B BIT(18) +#define BIT_CCA_TXEN_CNT_SWITCH_8814B BIT(17) +#define BIT_CCA_TXEN_CNT_EN_8814B BIT(16) + +#define BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B 8 +#define BIT_MASK_CCA_TXEN_BIG_CNT_8814B 0xff +#define BIT_CCA_TXEN_BIG_CNT_8814B(x) \ + (((x) & BIT_MASK_CCA_TXEN_BIG_CNT_8814B) \ + << BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B) +#define BITS_CCA_TXEN_BIG_CNT_8814B \ + (BIT_MASK_CCA_TXEN_BIG_CNT_8814B << BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B) +#define BIT_CLEAR_CCA_TXEN_BIG_CNT_8814B(x) \ + ((x) & (~BITS_CCA_TXEN_BIG_CNT_8814B)) +#define BIT_GET_CCA_TXEN_BIG_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B) & \ + BIT_MASK_CCA_TXEN_BIG_CNT_8814B) +#define BIT_SET_CCA_TXEN_BIG_CNT_8814B(x, v) \ + (BIT_CLEAR_CCA_TXEN_BIG_CNT_8814B(x) | BIT_CCA_TXEN_BIG_CNT_8814B(v)) + +#define BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B 0 +#define BIT_MASK_CCA_TXEN_SMALL_CNT_8814B 0xff +#define BIT_CCA_TXEN_SMALL_CNT_8814B(x) \ + (((x) & BIT_MASK_CCA_TXEN_SMALL_CNT_8814B) \ + << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B) +#define BITS_CCA_TXEN_SMALL_CNT_8814B \ + (BIT_MASK_CCA_TXEN_SMALL_CNT_8814B \ + << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B) +#define BIT_CLEAR_CCA_TXEN_SMALL_CNT_8814B(x) \ + ((x) & (~BITS_CCA_TXEN_SMALL_CNT_8814B)) +#define BIT_GET_CCA_TXEN_SMALL_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B) & \ + BIT_MASK_CCA_TXEN_SMALL_CNT_8814B) +#define BIT_SET_CCA_TXEN_SMALL_CNT_8814B(x, v) \ + (BIT_CLEAR_CCA_TXEN_SMALL_CNT_8814B(x) | \ + BIT_CCA_TXEN_SMALL_CNT_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_MAX_INTER_COLLISION_8814B */ + +#define BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B 24 +#define BIT_MASK_MAX_INTER_COLLISION_BK_8814B 0xff +#define BIT_MAX_INTER_COLLISION_BK_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BK_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B) +#define BITS_MAX_INTER_COLLISION_BK_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_BK_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_BK_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BK_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_BK_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_BK_8814B) +#define BIT_SET_MAX_INTER_COLLISION_BK_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BK_8814B(x) | \ + BIT_MAX_INTER_COLLISION_BK_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B 16 +#define BIT_MASK_MAX_INTER_COLLISION_BE_8814B 0xff +#define BIT_MAX_INTER_COLLISION_BE_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BE_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B) +#define BITS_MAX_INTER_COLLISION_BE_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_BE_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_BE_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BE_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_BE_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_BE_8814B) +#define BIT_SET_MAX_INTER_COLLISION_BE_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BE_8814B(x) | \ + BIT_MAX_INTER_COLLISION_BE_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B 8 +#define BIT_MASK_MAX_INTER_COLLISION_VI_8814B 0xff +#define BIT_MAX_INTER_COLLISION_VI_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VI_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B) +#define BITS_MAX_INTER_COLLISION_VI_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_VI_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_VI_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VI_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_VI_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_VI_8814B) +#define BIT_SET_MAX_INTER_COLLISION_VI_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VI_8814B(x) | \ + BIT_MAX_INTER_COLLISION_VI_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B 0 +#define BIT_MASK_MAX_INTER_COLLISION_VO_8814B 0xff +#define BIT_MAX_INTER_COLLISION_VO_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VO_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B) +#define BITS_MAX_INTER_COLLISION_VO_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_VO_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_VO_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VO_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_VO_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_VO_8814B) +#define BIT_SET_MAX_INTER_COLLISION_VO_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VO_8814B(x) | \ + BIT_MAX_INTER_COLLISION_VO_8814B(v)) + +/* 2 REG_MAX_INTER_COLLISION_CNT_8814B */ +#define BIT_MAX_INTER_COLLISION_EN_8814B BIT(16) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B 12 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BK_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B) +#define BITS_MAX_INTER_COLLISION_CNT_BK_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BK_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BK_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8814B(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BK_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B 8 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BE_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B) +#define BITS_MAX_INTER_COLLISION_CNT_BE_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BE_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BE_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8814B(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BE_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B 4 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VI_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B) +#define BITS_MAX_INTER_COLLISION_CNT_VI_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VI_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VI_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8814B(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VI_8814B(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B 0 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VO_8814B(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B) +#define BITS_MAX_INTER_COLLISION_CNT_VO_8814B \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8814B(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO_8814B)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VO_8814B(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VO_8814B(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8814B(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VO_8814B(v)) /* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ +/* 2 REG_RD_NAV_NXT_8814B */ + +#define BIT_SHIFT_RD_NAV_PROT_NXT_8814B 0 +#define BIT_MASK_RD_NAV_PROT_NXT_8814B 0xffff +#define BIT_RD_NAV_PROT_NXT_8814B(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT_8814B) \ + << BIT_SHIFT_RD_NAV_PROT_NXT_8814B) +#define BITS_RD_NAV_PROT_NXT_8814B \ + (BIT_MASK_RD_NAV_PROT_NXT_8814B << BIT_SHIFT_RD_NAV_PROT_NXT_8814B) +#define BIT_CLEAR_RD_NAV_PROT_NXT_8814B(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8814B)) +#define BIT_GET_RD_NAV_PROT_NXT_8814B(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8814B) & \ + BIT_MASK_RD_NAV_PROT_NXT_8814B) +#define BIT_SET_RD_NAV_PROT_NXT_8814B(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT_8814B(x) | BIT_RD_NAV_PROT_NXT_8814B(v)) + +/* 2 REG_NAV_PROT_LEN_8814B */ + +#define BIT_SHIFT_NAV_PROT_LEN_8814B 0 +#define BIT_MASK_NAV_PROT_LEN_8814B 0xffff +#define BIT_NAV_PROT_LEN_8814B(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN_8814B) << BIT_SHIFT_NAV_PROT_LEN_8814B) +#define BITS_NAV_PROT_LEN_8814B \ + (BIT_MASK_NAV_PROT_LEN_8814B << BIT_SHIFT_NAV_PROT_LEN_8814B) +#define BIT_CLEAR_NAV_PROT_LEN_8814B(x) ((x) & (~BITS_NAV_PROT_LEN_8814B)) +#define BIT_GET_NAV_PROT_LEN_8814B(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN_8814B) & BIT_MASK_NAV_PROT_LEN_8814B) +#define BIT_SET_NAV_PROT_LEN_8814B(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN_8814B(x) | BIT_NAV_PROT_LEN_8814B(v)) + +/* 2 REG_FTM_PTT_8814B */ + +#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B 22 +#define BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B 0x7 +#define BIT_FTM_PTT_TSF_R2T_SEL_8814B(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B) \ + << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B) +#define BITS_FTM_PTT_TSF_R2T_SEL_8814B \ + (BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B \ + << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B) +#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8814B(x) \ + ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL_8814B)) +#define BIT_GET_FTM_PTT_TSF_R2T_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B) & \ + BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B) +#define BIT_SET_FTM_PTT_TSF_R2T_SEL_8814B(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8814B(x) | \ + BIT_FTM_PTT_TSF_R2T_SEL_8814B(v)) + +#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B 19 +#define BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B 0x7 +#define BIT_FTM_PTT_TSF_T2R_SEL_8814B(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B) \ + << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B) +#define BITS_FTM_PTT_TSF_T2R_SEL_8814B \ + (BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B \ + << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B) +#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8814B(x) \ + ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL_8814B)) +#define BIT_GET_FTM_PTT_TSF_T2R_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B) & \ + BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B) +#define BIT_SET_FTM_PTT_TSF_T2R_SEL_8814B(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8814B(x) | \ + BIT_FTM_PTT_TSF_T2R_SEL_8814B(v)) + +#define BIT_SHIFT_FTM_PTT_TSF_SEL_8814B 16 +#define BIT_MASK_FTM_PTT_TSF_SEL_8814B 0x7 +#define BIT_FTM_PTT_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_SEL_8814B) \ + << BIT_SHIFT_FTM_PTT_TSF_SEL_8814B) +#define BITS_FTM_PTT_TSF_SEL_8814B \ + (BIT_MASK_FTM_PTT_TSF_SEL_8814B << BIT_SHIFT_FTM_PTT_TSF_SEL_8814B) +#define BIT_CLEAR_FTM_PTT_TSF_SEL_8814B(x) ((x) & (~BITS_FTM_PTT_TSF_SEL_8814B)) +#define BIT_GET_FTM_PTT_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL_8814B) & \ + BIT_MASK_FTM_PTT_TSF_SEL_8814B) +#define BIT_SET_FTM_PTT_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_SEL_8814B(x) | BIT_FTM_PTT_TSF_SEL_8814B(v)) + +#define BIT_SHIFT_FTM_PTT_VALUE_8814B 0 +#define BIT_MASK_FTM_PTT_VALUE_8814B 0xffff +#define BIT_FTM_PTT_VALUE_8814B(x) \ + (((x) & BIT_MASK_FTM_PTT_VALUE_8814B) << BIT_SHIFT_FTM_PTT_VALUE_8814B) +#define BITS_FTM_PTT_VALUE_8814B \ + (BIT_MASK_FTM_PTT_VALUE_8814B << BIT_SHIFT_FTM_PTT_VALUE_8814B) +#define BIT_CLEAR_FTM_PTT_VALUE_8814B(x) ((x) & (~BITS_FTM_PTT_VALUE_8814B)) +#define BIT_GET_FTM_PTT_VALUE_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_VALUE_8814B) & BIT_MASK_FTM_PTT_VALUE_8814B) +#define BIT_SET_FTM_PTT_VALUE_8814B(x, v) \ + (BIT_CLEAR_FTM_PTT_VALUE_8814B(x) | BIT_FTM_PTT_VALUE_8814B(v)) + +/* 2 REG_FTM_TSF_8814B */ + +#define BIT_SHIFT_FTM_T2_TSF_8814B 16 +#define BIT_MASK_FTM_T2_TSF_8814B 0xffff +#define BIT_FTM_T2_TSF_8814B(x) \ + (((x) & BIT_MASK_FTM_T2_TSF_8814B) << BIT_SHIFT_FTM_T2_TSF_8814B) +#define BITS_FTM_T2_TSF_8814B \ + (BIT_MASK_FTM_T2_TSF_8814B << BIT_SHIFT_FTM_T2_TSF_8814B) +#define BIT_CLEAR_FTM_T2_TSF_8814B(x) ((x) & (~BITS_FTM_T2_TSF_8814B)) +#define BIT_GET_FTM_T2_TSF_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_T2_TSF_8814B) & BIT_MASK_FTM_T2_TSF_8814B) +#define BIT_SET_FTM_T2_TSF_8814B(x, v) \ + (BIT_CLEAR_FTM_T2_TSF_8814B(x) | BIT_FTM_T2_TSF_8814B(v)) + +#define BIT_SHIFT_FTM_T1_TSF_8814B 0 +#define BIT_MASK_FTM_T1_TSF_8814B 0xffff +#define BIT_FTM_T1_TSF_8814B(x) \ + (((x) & BIT_MASK_FTM_T1_TSF_8814B) << BIT_SHIFT_FTM_T1_TSF_8814B) +#define BITS_FTM_T1_TSF_8814B \ + (BIT_MASK_FTM_T1_TSF_8814B << BIT_SHIFT_FTM_T1_TSF_8814B) +#define BIT_CLEAR_FTM_T1_TSF_8814B(x) ((x) & (~BITS_FTM_T1_TSF_8814B)) +#define BIT_GET_FTM_T1_TSF_8814B(x) \ + (((x) >> BIT_SHIFT_FTM_T1_TSF_8814B) & BIT_MASK_FTM_T1_TSF_8814B) +#define BIT_SET_FTM_T1_TSF_8814B(x, v) \ + (BIT_CLEAR_FTM_T1_TSF_8814B(x) | BIT_FTM_T1_TSF_8814B(v)) + /* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TBTT_PROHIBIT_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8814B 8 -#define BIT_MASK_TBTT_HOLD_TIME_AP_8814B 0xfff -#define BIT_TBTT_HOLD_TIME_AP_8814B(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8814B) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8814B) -#define BIT_GET_TBTT_HOLD_TIME_AP_8814B(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8814B) & BIT_MASK_TBTT_HOLD_TIME_AP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B 0 -#define BIT_MASK_TBTT_PROHIBIT_SETUP_8814B 0xf -#define BIT_TBTT_PROHIBIT_SETUP_8814B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8814B) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) -#define BIT_GET_TBTT_PROHIBIT_SETUP_8814B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) & BIT_MASK_TBTT_PROHIBIT_SETUP_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2PPS_STATE_8814B */ -#define BIT_POWER_STATE_8814B BIT(7) -#define BIT_CTWINDOW_ON_8814B BIT(6) -#define BIT_BEACON_AREA_ON_8814B BIT(5) -#define BIT_CTWIN_EARLY_DISTX_8814B BIT(4) -#define BIT_NOA1_OFF_PERIOD_8814B BIT(3) -#define BIT_FORCE_DOZE1_8814B BIT(2) -#define BIT_NOA0_OFF_PERIOD_8814B BIT(1) -#define BIT_FORCE_DOZE0_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RD_NAV_NXT_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_RD_NAV_PROT_NXT_8814B 0 -#define BIT_MASK_RD_NAV_PROT_NXT_8814B 0xffff -#define BIT_RD_NAV_PROT_NXT_8814B(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8814B) << BIT_SHIFT_RD_NAV_PROT_NXT_8814B) -#define BIT_GET_RD_NAV_PROT_NXT_8814B(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8814B) & BIT_MASK_RD_NAV_PROT_NXT_8814B) +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_HGQ_TIMEOUT_PERIOD_8814B */ + +#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B 0 +#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B 0xff +#define BIT_HGQ_TIMEOUT_PERIOD_8814B(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B) \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) +#define BITS_HGQ_TIMEOUT_PERIOD_8814B \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8814B(x) \ + ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8814B)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8814B(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) & \ + BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B) +#define BIT_SET_HGQ_TIMEOUT_PERIOD_8814B(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8814B(x) | \ + BIT_HGQ_TIMEOUT_PERIOD_8814B(v)) +/* 2 REG_TXCMD_TIMEOUT_PERIOD_8814B */ + +#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B 0 +#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B 0xff +#define BIT_TXCMD_TIMEOUT_PERIOD_8814B(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) +#define BITS_TXCMD_TIMEOUT_PERIOD_8814B \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8814B(x) \ + ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8814B)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8814B(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8814B(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8814B(x) | \ + BIT_TXCMD_TIMEOUT_PERIOD_8814B(v)) + +/* 2 REG_MISC_CTRL_8814B */ +#define BIT_DIS_SECONDARY_CCA_80M_8814B BIT(2) +#define BIT_DIS_SECONDARY_CCA_40M_8814B BIT(1) +#define BIT_DIS_SECONDARY_CCA_20M_8814B BIT(0) + +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NAV_PROT_LEN_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NAV_PROT_LEN_8814B 0 -#define BIT_MASK_NAV_PROT_LEN_8814B 0xffff -#define BIT_NAV_PROT_LEN_8814B(x) (((x) & BIT_MASK_NAV_PROT_LEN_8814B) << BIT_SHIFT_NAV_PROT_LEN_8814B) -#define BIT_GET_NAV_PROT_LEN_8814B(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8814B) & BIT_MASK_NAV_PROT_LEN_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BCN_CTRL_8814B */ -#define BIT_DIS_RX_BSSID_FIT_8814B BIT(6) -#define BIT_P0_EN_TXBCN_RPT_8814B BIT(5) -#define BIT_DIS_TSF_UDT_8814B BIT(4) -#define BIT_EN_BCN_FUNCTION_8814B BIT(3) -#define BIT_P0_EN_RXBCN_RPT_8814B BIT(2) -#define BIT_EN_P2P_CTWINDOW_8814B BIT(1) -#define BIT_EN_P2P_BCNQ_AREA_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BCN_CTRL_CLINT0_8814B */ -#define BIT_CLI0_DIS_RX_BSSID_FIT_8814B BIT(6) -#define BIT_CLI0_DIS_TSF_UDT_8814B BIT(4) -#define BIT_CLI0_EN_BCN_FUNCTION_8814B BIT(3) -#define BIT_CLI0_EN_RXBCN_RPT_8814B BIT(2) -#define BIT_CLI0_ENP2P_CTWINDOW_8814B BIT(1) -#define BIT_CLI0_ENP2P_BCNQ_AREA_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_MBID_NUM_8814B */ -#define BIT_EN_PRE_DL_BEACON_8814B BIT(3) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_MBID_BCN_NUM_8814B 0 -#define BIT_MASK_MBID_BCN_NUM_8814B 0x7 -#define BIT_MBID_BCN_NUM_8814B(x) (((x) & BIT_MASK_MBID_BCN_NUM_8814B) << BIT_SHIFT_MBID_BCN_NUM_8814B) -#define BIT_GET_MBID_BCN_NUM_8814B(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8814B) & BIT_MASK_MBID_BCN_NUM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DUAL_TSF_RST_8814B */ -#define BIT_FREECNT_RST_8814B BIT(5) -#define BIT_TSFTR_CLI3_RST_8814B BIT(4) -#define BIT_TSFTR_CLI2_RST_8814B BIT(3) -#define BIT_TSFTR_CLI1_RST_8814B BIT(2) -#define BIT_TSFTR_CLI0_RST_8814B BIT(1) -#define BIT_TSFTR_RST_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_MBSSID_BCN_SPACE_8814B */ +/* 2 REG_TXOP_MIN_8814B */ +#define BIT_HIQ_NAV_BREAK_EN_8814B BIT(15) +#define BIT_MGQ_NAV_BREAK_EN_8814B BIT(14) -#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8814B 28 -#define BIT_MASK_BCN_TIMER_SEL_FWRD_8814B 0x7 -#define BIT_BCN_TIMER_SEL_FWRD_8814B(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8814B) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8814B) -#define BIT_GET_BCN_TIMER_SEL_FWRD_8814B(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8814B) & BIT_MASK_BCN_TIMER_SEL_FWRD_8814B) +#define BIT_SHIFT_TXOP_MIN_8814B 0 +#define BIT_MASK_TXOP_MIN_8814B 0x3fff +#define BIT_TXOP_MIN_8814B(x) \ + (((x) & BIT_MASK_TXOP_MIN_8814B) << BIT_SHIFT_TXOP_MIN_8814B) +#define BITS_TXOP_MIN_8814B \ + (BIT_MASK_TXOP_MIN_8814B << BIT_SHIFT_TXOP_MIN_8814B) +#define BIT_CLEAR_TXOP_MIN_8814B(x) ((x) & (~BITS_TXOP_MIN_8814B)) +#define BIT_GET_TXOP_MIN_8814B(x) \ + (((x) >> BIT_SHIFT_TXOP_MIN_8814B) & BIT_MASK_TXOP_MIN_8814B) +#define BIT_SET_TXOP_MIN_8814B(x, v) \ + (BIT_CLEAR_TXOP_MIN_8814B(x) | BIT_TXOP_MIN_8814B(v)) +/* 2 REG_PRE_BKF_TIME_8814B */ +#define BIT_SHIFT_PRE_BKF_TIME_8814B 0 +#define BIT_MASK_PRE_BKF_TIME_8814B 0xff +#define BIT_PRE_BKF_TIME_8814B(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME_8814B) << BIT_SHIFT_PRE_BKF_TIME_8814B) +#define BITS_PRE_BKF_TIME_8814B \ + (BIT_MASK_PRE_BKF_TIME_8814B << BIT_SHIFT_PRE_BKF_TIME_8814B) +#define BIT_CLEAR_PRE_BKF_TIME_8814B(x) ((x) & (~BITS_PRE_BKF_TIME_8814B)) +#define BIT_GET_PRE_BKF_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME_8814B) & BIT_MASK_PRE_BKF_TIME_8814B) +#define BIT_SET_PRE_BKF_TIME_8814B(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME_8814B(x) | BIT_PRE_BKF_TIME_8814B(v)) -#define BIT_SHIFT_BCN_SPACE_CLINT0_8814B 16 -#define BIT_MASK_BCN_SPACE_CLINT0_8814B 0xfff -#define BIT_BCN_SPACE_CLINT0_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8814B) << BIT_SHIFT_BCN_SPACE_CLINT0_8814B) -#define BIT_GET_BCN_SPACE_CLINT0_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8814B) & BIT_MASK_BCN_SPACE_CLINT0_8814B) +/* 2 REG_CROSS_TXOP_CTRL_8814B */ +#define BIT_TBTT_RETRY_8814B BIT(4) +#define BIT_TXFAIL_BREACK_TXOP_EN_8814B BIT(3) +#define BIT_RTS_NAV_TXOP_8814B BIT(1) +#define BIT_NOT_CROSS_TXOP_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_SPACE0_8814B 0 -#define BIT_MASK_BCN_SPACE0_8814B 0xffff -#define BIT_BCN_SPACE0_8814B(x) (((x) & BIT_MASK_BCN_SPACE0_8814B) << BIT_SHIFT_BCN_SPACE0_8814B) -#define BIT_GET_BCN_SPACE0_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8814B) & BIT_MASK_BCN_SPACE0_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DRVERLYINT_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DRVERLYITV_8814B 0 -#define BIT_MASK_DRVERLYITV_8814B 0xff -#define BIT_DRVERLYITV_8814B(x) (((x) & BIT_MASK_DRVERLYITV_8814B) << BIT_SHIFT_DRVERLYITV_8814B) -#define BIT_GET_DRVERLYITV_8814B(x) (((x) >> BIT_SHIFT_DRVERLYITV_8814B) & BIT_MASK_DRVERLYITV_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BCNDMATIM_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCNDMATIM_8814B 0 -#define BIT_MASK_BCNDMATIM_8814B 0xff -#define BIT_BCNDMATIM_8814B(x) (((x) & BIT_MASK_BCNDMATIM_8814B) << BIT_SHIFT_BCNDMATIM_8814B) -#define BIT_GET_BCNDMATIM_8814B(x) (((x) >> BIT_SHIFT_BCNDMATIM_8814B) & BIT_MASK_BCNDMATIM_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_ATIMWND_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_ATIMWND0_8814B 0 -#define BIT_MASK_ATIMWND0_8814B 0xffff -#define BIT_ATIMWND0_8814B(x) (((x) & BIT_MASK_ATIMWND0_8814B) << BIT_SHIFT_ATIMWND0_8814B) -#define BIT_GET_ATIMWND0_8814B(x) (((x) >> BIT_SHIFT_ATIMWND0_8814B) & BIT_MASK_ATIMWND0_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_USTIME_TSF_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_USTIME_TSF_V1_8814B 0 -#define BIT_MASK_USTIME_TSF_V1_8814B 0xff -#define BIT_USTIME_TSF_V1_8814B(x) (((x) & BIT_MASK_USTIME_TSF_V1_8814B) << BIT_SHIFT_USTIME_TSF_V1_8814B) -#define BIT_GET_USTIME_TSF_V1_8814B(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8814B) & BIT_MASK_USTIME_TSF_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BCN_MAX_ERR_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_MAX_ERR_8814B 0 -#define BIT_MASK_BCN_MAX_ERR_8814B 0xff -#define BIT_BCN_MAX_ERR_8814B(x) (((x) & BIT_MASK_BCN_MAX_ERR_8814B) << BIT_SHIFT_BCN_MAX_ERR_8814B) -#define BIT_GET_BCN_MAX_ERR_8814B(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8814B) & BIT_MASK_BCN_MAX_ERR_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RXTSF_OFFSET_CCK_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CCK_RXTSF_OFFSET_8814B 0 -#define BIT_MASK_CCK_RXTSF_OFFSET_8814B 0xff -#define BIT_CCK_RXTSF_OFFSET_8814B(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8814B) << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) -#define BIT_GET_CCK_RXTSF_OFFSET_8814B(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) & BIT_MASK_CCK_RXTSF_OFFSET_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_ACMHWCTRL_8814B */ +#define BIT_BEQ_ACM_STATUS_8814B BIT(7) +#define BIT_VIQ_ACM_STATUS_8814B BIT(6) +#define BIT_VOQ_ACM_STATUS_8814B BIT(5) +#define BIT_BEQ_ACM_EN_8814B BIT(3) +#define BIT_VIQ_ACM_EN_8814B BIT(2) +#define BIT_VOQ_ACM_EN_8814B BIT(1) +#define BIT_ACMHWEN_8814B BIT(0) -/* 2 REG_RXTSF_OFFSET_OFDM_8814B */ +/* 2 REG_ACMRSTCTRL_8814B */ +#define BIT_BE_ACM_RESET_USED_TIME_8814B BIT(2) +#define BIT_VI_ACM_RESET_USED_TIME_8814B BIT(1) +#define BIT_VO_ACM_RESET_USED_TIME_8814B BIT(0) -#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B 0 -#define BIT_MASK_OFDM_RXTSF_OFFSET_8814B 0xff -#define BIT_OFDM_RXTSF_OFFSET_8814B(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8814B) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) -#define BIT_GET_OFDM_RXTSF_OFFSET_8814B(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) & BIT_MASK_OFDM_RXTSF_OFFSET_8814B) +/* 2 REG_ACMAVG_8814B */ +#define BIT_SHIFT_AVGPERIOD_8814B 0 +#define BIT_MASK_AVGPERIOD_8814B 0xffff +#define BIT_AVGPERIOD_8814B(x) \ + (((x) & BIT_MASK_AVGPERIOD_8814B) << BIT_SHIFT_AVGPERIOD_8814B) +#define BITS_AVGPERIOD_8814B \ + (BIT_MASK_AVGPERIOD_8814B << BIT_SHIFT_AVGPERIOD_8814B) +#define BIT_CLEAR_AVGPERIOD_8814B(x) ((x) & (~BITS_AVGPERIOD_8814B)) +#define BIT_GET_AVGPERIOD_8814B(x) \ + (((x) >> BIT_SHIFT_AVGPERIOD_8814B) & BIT_MASK_AVGPERIOD_8814B) +#define BIT_SET_AVGPERIOD_8814B(x, v) \ + (BIT_CLEAR_AVGPERIOD_8814B(x) | BIT_AVGPERIOD_8814B(v)) +/* 2 REG_VO_ADMTIME_8814B */ -/* 2 REG_TSFTR_8814B */ +#define BIT_SHIFT_VO_ADMITTED_TIME_8814B 0 +#define BIT_MASK_VO_ADMITTED_TIME_8814B 0xffff +#define BIT_VO_ADMITTED_TIME_8814B(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME_8814B) \ + << BIT_SHIFT_VO_ADMITTED_TIME_8814B) +#define BITS_VO_ADMITTED_TIME_8814B \ + (BIT_MASK_VO_ADMITTED_TIME_8814B << BIT_SHIFT_VO_ADMITTED_TIME_8814B) +#define BIT_CLEAR_VO_ADMITTED_TIME_8814B(x) \ + ((x) & (~BITS_VO_ADMITTED_TIME_8814B)) +#define BIT_GET_VO_ADMITTED_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8814B) & \ + BIT_MASK_VO_ADMITTED_TIME_8814B) +#define BIT_SET_VO_ADMITTED_TIME_8814B(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME_8814B(x) | BIT_VO_ADMITTED_TIME_8814B(v)) -#define BIT_SHIFT_TSF_TIMER_V1_8814B 0 -#define BIT_MASK_TSF_TIMER_V1_8814B 0xffffffffL -#define BIT_TSF_TIMER_V1_8814B(x) (((x) & BIT_MASK_TSF_TIMER_V1_8814B) << BIT_SHIFT_TSF_TIMER_V1_8814B) -#define BIT_GET_TSF_TIMER_V1_8814B(x) (((x) >> BIT_SHIFT_TSF_TIMER_V1_8814B) & BIT_MASK_TSF_TIMER_V1_8814B) +/* 2 REG_VI_ADMTIME_8814B */ +#define BIT_SHIFT_VI_ADMITTED_TIME_8814B 0 +#define BIT_MASK_VI_ADMITTED_TIME_8814B 0xffff +#define BIT_VI_ADMITTED_TIME_8814B(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME_8814B) \ + << BIT_SHIFT_VI_ADMITTED_TIME_8814B) +#define BITS_VI_ADMITTED_TIME_8814B \ + (BIT_MASK_VI_ADMITTED_TIME_8814B << BIT_SHIFT_VI_ADMITTED_TIME_8814B) +#define BIT_CLEAR_VI_ADMITTED_TIME_8814B(x) \ + ((x) & (~BITS_VI_ADMITTED_TIME_8814B)) +#define BIT_GET_VI_ADMITTED_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8814B) & \ + BIT_MASK_VI_ADMITTED_TIME_8814B) +#define BIT_SET_VI_ADMITTED_TIME_8814B(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME_8814B(x) | BIT_VI_ADMITTED_TIME_8814B(v)) +/* 2 REG_BE_ADMTIME_8814B */ -/* 2 REG_TSFTR_1_8814B */ +#define BIT_SHIFT_BE_ADMITTED_TIME_8814B 0 +#define BIT_MASK_BE_ADMITTED_TIME_8814B 0xffff +#define BIT_BE_ADMITTED_TIME_8814B(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME_8814B) \ + << BIT_SHIFT_BE_ADMITTED_TIME_8814B) +#define BITS_BE_ADMITTED_TIME_8814B \ + (BIT_MASK_BE_ADMITTED_TIME_8814B << BIT_SHIFT_BE_ADMITTED_TIME_8814B) +#define BIT_CLEAR_BE_ADMITTED_TIME_8814B(x) \ + ((x) & (~BITS_BE_ADMITTED_TIME_8814B)) +#define BIT_GET_BE_ADMITTED_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8814B) & \ + BIT_MASK_BE_ADMITTED_TIME_8814B) +#define BIT_SET_BE_ADMITTED_TIME_8814B(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME_8814B(x) | BIT_BE_ADMITTED_TIME_8814B(v)) + +/* 2 REG_MAC_HEADER_NAV_OFFSET_8814B */ + +#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B 0 +#define BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B 0xff +#define BIT_MAC_HEADER_NAV_OFFSET_8814B(x) \ + (((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B) \ + << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B) +#define BITS_MAC_HEADER_NAV_OFFSET_8814B \ + (BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B \ + << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B) +#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8814B(x) \ + ((x) & (~BITS_MAC_HEADER_NAV_OFFSET_8814B)) +#define BIT_GET_MAC_HEADER_NAV_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B) & \ + BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B) +#define BIT_SET_MAC_HEADER_NAV_OFFSET_8814B(x, v) \ + (BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8814B(x) | \ + BIT_MAC_HEADER_NAV_OFFSET_8814B(v)) + +/* 2 REG_DIS_NDPA_NAV_CHECK_8814B */ +#define BIT_DIS_NDPA_NAV_CHECK_8814B BIT(0) -#define BIT_SHIFT_TSF_TIMER_V2_8814B 0 -#define BIT_MASK_TSF_TIMER_V2_8814B 0xffffffffL -#define BIT_TSF_TIMER_V2_8814B(x) (((x) & BIT_MASK_TSF_TIMER_V2_8814B) << BIT_SHIFT_TSF_TIMER_V2_8814B) -#define BIT_GET_TSF_TIMER_V2_8814B(x) (((x) >> BIT_SHIFT_TSF_TIMER_V2_8814B) & BIT_MASK_TSF_TIMER_V2_8814B) +/* 2 REG_EDCA_RANDOM_GEN_8814B */ +#define BIT_SHIFT_RANDOM_GEN_8814B 0 +#define BIT_MASK_RANDOM_GEN_8814B 0xffffff +#define BIT_RANDOM_GEN_8814B(x) \ + (((x) & BIT_MASK_RANDOM_GEN_8814B) << BIT_SHIFT_RANDOM_GEN_8814B) +#define BITS_RANDOM_GEN_8814B \ + (BIT_MASK_RANDOM_GEN_8814B << BIT_SHIFT_RANDOM_GEN_8814B) +#define BIT_CLEAR_RANDOM_GEN_8814B(x) ((x) & (~BITS_RANDOM_GEN_8814B)) +#define BIT_GET_RANDOM_GEN_8814B(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN_8814B) & BIT_MASK_RANDOM_GEN_8814B) +#define BIT_SET_RANDOM_GEN_8814B(x, v) \ + (BIT_CLEAR_RANDOM_GEN_8814B(x) | BIT_RANDOM_GEN_8814B(v)) + +/* 2 REG_TXCMD_SEL_8814B */ +#define BIT_SHIFT_TXCMD_SEG_SEL_8814B 0 +#define BIT_MASK_TXCMD_SEG_SEL_8814B 0xf +#define BIT_TXCMD_SEG_SEL_8814B(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL_8814B) << BIT_SHIFT_TXCMD_SEG_SEL_8814B) +#define BITS_TXCMD_SEG_SEL_8814B \ + (BIT_MASK_TXCMD_SEG_SEL_8814B << BIT_SHIFT_TXCMD_SEG_SEL_8814B) +#define BIT_CLEAR_TXCMD_SEG_SEL_8814B(x) ((x) & (~BITS_TXCMD_SEG_SEL_8814B)) +#define BIT_GET_TXCMD_SEG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8814B) & BIT_MASK_TXCMD_SEG_SEL_8814B) +#define BIT_SET_TXCMD_SEG_SEL_8814B(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL_8814B(x) | BIT_TXCMD_SEG_SEL_8814B(v)) -/* 2 REG_FREERUN_CNT_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_FREERUN_CNT_V1_8814B 0 -#define BIT_MASK_FREERUN_CNT_V1_8814B 0xffffffffL -#define BIT_FREERUN_CNT_V1_8814B(x) (((x) & BIT_MASK_FREERUN_CNT_V1_8814B) << BIT_SHIFT_FREERUN_CNT_V1_8814B) -#define BIT_GET_FREERUN_CNT_V1_8814B(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8814B) & BIT_MASK_FREERUN_CNT_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_FREERUN_CNT_1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_FREERUN_CNT_V2_8814B 0 -#define BIT_MASK_FREERUN_CNT_V2_8814B 0xffffffffL -#define BIT_FREERUN_CNT_V2_8814B(x) (((x) & BIT_MASK_FREERUN_CNT_V2_8814B) << BIT_SHIFT_FREERUN_CNT_V2_8814B) -#define BIT_GET_FREERUN_CNT_V2_8814B(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8814B) & BIT_MASK_FREERUN_CNT_V2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_MU_DBG_INFO_8814B */ + +#define BIT_SHIFT_MU_DBG_INFO_8814B 0 +#define BIT_MASK_MU_DBG_INFO_8814B 0xffffffffL +#define BIT_MU_DBG_INFO_8814B(x) \ + (((x) & BIT_MASK_MU_DBG_INFO_8814B) << BIT_SHIFT_MU_DBG_INFO_8814B) +#define BITS_MU_DBG_INFO_8814B \ + (BIT_MASK_MU_DBG_INFO_8814B << BIT_SHIFT_MU_DBG_INFO_8814B) +#define BIT_CLEAR_MU_DBG_INFO_8814B(x) ((x) & (~BITS_MU_DBG_INFO_8814B)) +#define BIT_GET_MU_DBG_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_MU_DBG_INFO_8814B) & BIT_MASK_MU_DBG_INFO_8814B) +#define BIT_SET_MU_DBG_INFO_8814B(x, v) \ + (BIT_CLEAR_MU_DBG_INFO_8814B(x) | BIT_MU_DBG_INFO_8814B(v)) + +/* 2 REG_MU_DBG_INFO_1_8814B */ + +#define BIT_SHIFT_MU_DBG_INFO_1_8814B 0 +#define BIT_MASK_MU_DBG_INFO_1_8814B 0xffffffffL +#define BIT_MU_DBG_INFO_1_8814B(x) \ + (((x) & BIT_MASK_MU_DBG_INFO_1_8814B) << BIT_SHIFT_MU_DBG_INFO_1_8814B) +#define BITS_MU_DBG_INFO_1_8814B \ + (BIT_MASK_MU_DBG_INFO_1_8814B << BIT_SHIFT_MU_DBG_INFO_1_8814B) +#define BIT_CLEAR_MU_DBG_INFO_1_8814B(x) ((x) & (~BITS_MU_DBG_INFO_1_8814B)) +#define BIT_GET_MU_DBG_INFO_1_8814B(x) \ + (((x) >> BIT_SHIFT_MU_DBG_INFO_1_8814B) & BIT_MASK_MU_DBG_INFO_1_8814B) +#define BIT_SET_MU_DBG_INFO_1_8814B(x, v) \ + (BIT_CLEAR_MU_DBG_INFO_1_8814B(x) | BIT_MU_DBG_INFO_1_8814B(v)) + +/* 2 REG_SCH_DBG_SEL_8814B */ + +#define BIT_SHIFT_SCH_DBG_SEL_8814B 0 +#define BIT_MASK_SCH_DBG_SEL_8814B 0xff +#define BIT_SCH_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_SCH_DBG_SEL_8814B) << BIT_SHIFT_SCH_DBG_SEL_8814B) +#define BITS_SCH_DBG_SEL_8814B \ + (BIT_MASK_SCH_DBG_SEL_8814B << BIT_SHIFT_SCH_DBG_SEL_8814B) +#define BIT_CLEAR_SCH_DBG_SEL_8814B(x) ((x) & (~BITS_SCH_DBG_SEL_8814B)) +#define BIT_GET_SCH_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_SCH_DBG_SEL_8814B) & BIT_MASK_SCH_DBG_SEL_8814B) +#define BIT_SET_SCH_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_SCH_DBG_SEL_8814B(x) | BIT_SCH_DBG_SEL_8814B(v)) +/* 2 REG_SCHEDULER_RST_8814B */ +#define BIT_SCHEDULER_RST_V1_8814B BIT(0) -/* 2 REG_ATIMWND1_V1_8814B */ +/* 2 REG_MU_DBG_ERR_FLAG_8814B */ +#define BIT_BCN_PORTID_ERR_8814B BIT(2) + +#define BIT_SHIFT_MU_DBG_ERR_FLAG_8814B 0 +#define BIT_MASK_MU_DBG_ERR_FLAG_8814B 0x3 +#define BIT_MU_DBG_ERR_FLAG_8814B(x) \ + (((x) & BIT_MASK_MU_DBG_ERR_FLAG_8814B) \ + << BIT_SHIFT_MU_DBG_ERR_FLAG_8814B) +#define BITS_MU_DBG_ERR_FLAG_8814B \ + (BIT_MASK_MU_DBG_ERR_FLAG_8814B << BIT_SHIFT_MU_DBG_ERR_FLAG_8814B) +#define BIT_CLEAR_MU_DBG_ERR_FLAG_8814B(x) ((x) & (~BITS_MU_DBG_ERR_FLAG_8814B)) +#define BIT_GET_MU_DBG_ERR_FLAG_8814B(x) \ + (((x) >> BIT_SHIFT_MU_DBG_ERR_FLAG_8814B) & \ + BIT_MASK_MU_DBG_ERR_FLAG_8814B) +#define BIT_SET_MU_DBG_ERR_FLAG_8814B(x, v) \ + (BIT_CLEAR_MU_DBG_ERR_FLAG_8814B(x) | BIT_MU_DBG_ERR_FLAG_8814B(v)) + +/* 2 REG_TX_ERR_RECOVERY_RST_8814B */ + +#define BIT_SHIFT_ERR_RECOVER_CNT_8814B 4 +#define BIT_MASK_ERR_RECOVER_CNT_8814B 0xf +#define BIT_ERR_RECOVER_CNT_8814B(x) \ + (((x) & BIT_MASK_ERR_RECOVER_CNT_8814B) \ + << BIT_SHIFT_ERR_RECOVER_CNT_8814B) +#define BITS_ERR_RECOVER_CNT_8814B \ + (BIT_MASK_ERR_RECOVER_CNT_8814B << BIT_SHIFT_ERR_RECOVER_CNT_8814B) +#define BIT_CLEAR_ERR_RECOVER_CNT_8814B(x) ((x) & (~BITS_ERR_RECOVER_CNT_8814B)) +#define BIT_GET_ERR_RECOVER_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_ERR_RECOVER_CNT_8814B) & \ + BIT_MASK_ERR_RECOVER_CNT_8814B) +#define BIT_SET_ERR_RECOVER_CNT_8814B(x, v) \ + (BIT_CLEAR_ERR_RECOVER_CNT_8814B(x) | BIT_ERR_RECOVER_CNT_8814B(v)) + +#define BIT_RX_HANG_ERR_8814B BIT(2) +#define BIT_TX_HANG_ERR_8814B BIT(1) +#define BIT_TX_ERR_RECOVERY_RST_8814B BIT(0) + +/* 2 REG_SCH_DBG_VALUE_8814B */ + +#define BIT_SHIFT_SCH_DBG_VALUE_8814B 0 +#define BIT_MASK_SCH_DBG_VALUE_8814B 0xffffffffL +#define BIT_SCH_DBG_VALUE_8814B(x) \ + (((x) & BIT_MASK_SCH_DBG_VALUE_8814B) << BIT_SHIFT_SCH_DBG_VALUE_8814B) +#define BITS_SCH_DBG_VALUE_8814B \ + (BIT_MASK_SCH_DBG_VALUE_8814B << BIT_SHIFT_SCH_DBG_VALUE_8814B) +#define BIT_CLEAR_SCH_DBG_VALUE_8814B(x) ((x) & (~BITS_SCH_DBG_VALUE_8814B)) +#define BIT_GET_SCH_DBG_VALUE_8814B(x) \ + (((x) >> BIT_SHIFT_SCH_DBG_VALUE_8814B) & BIT_MASK_SCH_DBG_VALUE_8814B) +#define BIT_SET_SCH_DBG_VALUE_8814B(x, v) \ + (BIT_CLEAR_SCH_DBG_VALUE_8814B(x) | BIT_SCH_DBG_VALUE_8814B(v)) -#define BIT_SHIFT_ATIMWND1_V1_8814B 0 -#define BIT_MASK_ATIMWND1_V1_8814B 0xff -#define BIT_ATIMWND1_V1_8814B(x) (((x) & BIT_MASK_ATIMWND1_V1_8814B) << BIT_SHIFT_ATIMWND1_V1_8814B) -#define BIT_GET_ATIMWND1_V1_8814B(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8814B) & BIT_MASK_ATIMWND1_V1_8814B) +/* 2 REG_SCH_TXCMD_8814B */ +#define BIT_SHIFT_SCH_TXCMD_8814B 0 +#define BIT_MASK_SCH_TXCMD_8814B 0xffffffffL +#define BIT_SCH_TXCMD_8814B(x) \ + (((x) & BIT_MASK_SCH_TXCMD_8814B) << BIT_SHIFT_SCH_TXCMD_8814B) +#define BITS_SCH_TXCMD_8814B \ + (BIT_MASK_SCH_TXCMD_8814B << BIT_SHIFT_SCH_TXCMD_8814B) +#define BIT_CLEAR_SCH_TXCMD_8814B(x) ((x) & (~BITS_SCH_TXCMD_8814B)) +#define BIT_GET_SCH_TXCMD_8814B(x) \ + (((x) >> BIT_SHIFT_SCH_TXCMD_8814B) & BIT_MASK_SCH_TXCMD_8814B) +#define BIT_SET_SCH_TXCMD_8814B(x, v) \ + (BIT_CLEAR_SCH_TXCMD_8814B(x) | BIT_SCH_TXCMD_8814B(v)) +/* 2 REG_PAGE5_DUMMY_8814B */ -/* 2 REG_TBTT_PROHIBIT_INFRA_8814B */ +/* 2 REG_PORT_CTRL_SEL_8814B */ + +#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B 4 +#define BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B 0x7 +#define BIT_BCN_TIMER_SEL_FWRD_V1_8814B(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B) +#define BITS_BCN_TIMER_SEL_FWRD_V1_8814B \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1_8814B(x) \ + ((x) & (~BITS_BCN_TIMER_SEL_FWRD_V1_8814B)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B) +#define BIT_SET_BCN_TIMER_SEL_FWRD_V1_8814B(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1_8814B(x) | \ + BIT_BCN_TIMER_SEL_FWRD_V1_8814B(v)) + +#define BIT_SHIFT_PORT_CTRL_SEL_8814B 0 +#define BIT_MASK_PORT_CTRL_SEL_8814B 0x7 +#define BIT_PORT_CTRL_SEL_8814B(x) \ + (((x) & BIT_MASK_PORT_CTRL_SEL_8814B) << BIT_SHIFT_PORT_CTRL_SEL_8814B) +#define BITS_PORT_CTRL_SEL_8814B \ + (BIT_MASK_PORT_CTRL_SEL_8814B << BIT_SHIFT_PORT_CTRL_SEL_8814B) +#define BIT_CLEAR_PORT_CTRL_SEL_8814B(x) ((x) & (~BITS_PORT_CTRL_SEL_8814B)) +#define BIT_GET_PORT_CTRL_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PORT_CTRL_SEL_8814B) & BIT_MASK_PORT_CTRL_SEL_8814B) +#define BIT_SET_PORT_CTRL_SEL_8814B(x, v) \ + (BIT_CLEAR_PORT_CTRL_SEL_8814B(x) | BIT_PORT_CTRL_SEL_8814B(v)) + +/* 2 REG_PORT_CTRL_CFG_8814B */ +#define BIT_BCNERR_CNT_EN_V1_8814B BIT(11) +#define BIT_DIS_TRX_CAL_BCN_V1_8814B BIT(10) +#define BIT_DIS_TX_CAL_TBTT_V1_8814B BIT(9) +#define BIT_BCN_AGGRESSION_V1_8814B BIT(8) +#define BIT_TSFTR_RST_V1_8814B BIT(7) +#define BIT_DIS_RX_BSSID_FIT_8814B BIT(6) +#define BIT_EN_TXBCN_RPT_V1_8814B BIT(5) +#define BIT_DIS_TSF_UDT_8814B BIT(4) +#define BIT_EN_PORT_FUNCTION_8814B BIT(3) +#define BIT_EN_RXBCN_RPT_8814B BIT(2) +#define BIT_EN_P2P_CTWINDOW_8814B BIT(1) +#define BIT_EN_P2P_BCNQ_AREA_8814B BIT(0) -#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8814B 0 -#define BIT_MASK_TBTT_PROHIBIT_INFRA_8814B 0xff -#define BIT_TBTT_PROHIBIT_INFRA_8814B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8814B) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8814B) -#define BIT_GET_TBTT_PROHIBIT_INFRA_8814B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8814B) & BIT_MASK_TBTT_PROHIBIT_INFRA_8814B) +/* 2 REG_TBTT_PROHIBIT_CFG_8814B */ +#define BIT_MASK_PROHIBIT_8814B BIT(23) + +#define BIT_SHIFT_TBTT_HOLD_TIME_8814B 8 +#define BIT_MASK_TBTT_HOLD_TIME_8814B 0xfff +#define BIT_TBTT_HOLD_TIME_8814B(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_8814B) \ + << BIT_SHIFT_TBTT_HOLD_TIME_8814B) +#define BITS_TBTT_HOLD_TIME_8814B \ + (BIT_MASK_TBTT_HOLD_TIME_8814B << BIT_SHIFT_TBTT_HOLD_TIME_8814B) +#define BIT_CLEAR_TBTT_HOLD_TIME_8814B(x) ((x) & (~BITS_TBTT_HOLD_TIME_8814B)) +#define BIT_GET_TBTT_HOLD_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_8814B) & \ + BIT_MASK_TBTT_HOLD_TIME_8814B) +#define BIT_SET_TBTT_HOLD_TIME_8814B(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_8814B(x) | BIT_TBTT_HOLD_TIME_8814B(v)) +#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B 0 +#define BIT_MASK_TBTT_PROHIBIT_SETUP_8814B 0xf +#define BIT_TBTT_PROHIBIT_SETUP_8814B(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8814B) \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) +#define BITS_TBTT_PROHIBIT_SETUP_8814B \ + (BIT_MASK_TBTT_PROHIBIT_SETUP_8814B \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8814B(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8814B)) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8814B(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) & \ + BIT_MASK_TBTT_PROHIBIT_SETUP_8814B) +#define BIT_SET_TBTT_PROHIBIT_SETUP_8814B(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8814B(x) | \ + BIT_TBTT_PROHIBIT_SETUP_8814B(v)) + +/* 2 REG_DRVERLYINT_CFG_8814B */ +#define BIT_SHIFT_DRVERLYITV_8814B 0 +#define BIT_MASK_DRVERLYITV_8814B 0xff +#define BIT_DRVERLYITV_8814B(x) \ + (((x) & BIT_MASK_DRVERLYITV_8814B) << BIT_SHIFT_DRVERLYITV_8814B) +#define BITS_DRVERLYITV_8814B \ + (BIT_MASK_DRVERLYITV_8814B << BIT_SHIFT_DRVERLYITV_8814B) +#define BIT_CLEAR_DRVERLYITV_8814B(x) ((x) & (~BITS_DRVERLYITV_8814B)) +#define BIT_GET_DRVERLYITV_8814B(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV_8814B) & BIT_MASK_DRVERLYITV_8814B) +#define BIT_SET_DRVERLYITV_8814B(x, v) \ + (BIT_CLEAR_DRVERLYITV_8814B(x) | BIT_DRVERLYITV_8814B(v)) + +/* 2 REG_BCNDMATIM_CFG_8814B */ -/* 2 REG_CTWND_8814B */ +#define BIT_SHIFT_BCNDMATIM_8814B 0 +#define BIT_MASK_BCNDMATIM_8814B 0xff +#define BIT_BCNDMATIM_8814B(x) \ + (((x) & BIT_MASK_BCNDMATIM_8814B) << BIT_SHIFT_BCNDMATIM_8814B) +#define BITS_BCNDMATIM_8814B \ + (BIT_MASK_BCNDMATIM_8814B << BIT_SHIFT_BCNDMATIM_8814B) +#define BIT_CLEAR_BCNDMATIM_8814B(x) ((x) & (~BITS_BCNDMATIM_8814B)) +#define BIT_GET_BCNDMATIM_8814B(x) \ + (((x) >> BIT_SHIFT_BCNDMATIM_8814B) & BIT_MASK_BCNDMATIM_8814B) +#define BIT_SET_BCNDMATIM_8814B(x, v) \ + (BIT_CLEAR_BCNDMATIM_8814B(x) | BIT_BCNDMATIM_8814B(v)) + +/* 2 REG_CTWND_CFG_8814B */ #define BIT_SHIFT_CTWND_8814B 0 #define BIT_MASK_CTWND_8814B 0xff -#define BIT_CTWND_8814B(x) (((x) & BIT_MASK_CTWND_8814B) << BIT_SHIFT_CTWND_8814B) -#define BIT_GET_CTWND_8814B(x) (((x) >> BIT_SHIFT_CTWND_8814B) & BIT_MASK_CTWND_8814B) +#define BIT_CTWND_8814B(x) \ + (((x) & BIT_MASK_CTWND_8814B) << BIT_SHIFT_CTWND_8814B) +#define BITS_CTWND_8814B (BIT_MASK_CTWND_8814B << BIT_SHIFT_CTWND_8814B) +#define BIT_CLEAR_CTWND_8814B(x) ((x) & (~BITS_CTWND_8814B)) +#define BIT_GET_CTWND_8814B(x) \ + (((x) >> BIT_SHIFT_CTWND_8814B) & BIT_MASK_CTWND_8814B) +#define BIT_SET_CTWND_8814B(x, v) \ + (BIT_CLEAR_CTWND_8814B(x) | BIT_CTWND_8814B(v)) +/* 2 REG_BCNIVLCUNT_CFG_8814B */ - -/* 2 REG_BCNIVLCUNT_8814B */ +/* 2 REG_NOT_VALID_8814B */ #define BIT_SHIFT_BCNIVLCUNT_8814B 0 #define BIT_MASK_BCNIVLCUNT_8814B 0x7f -#define BIT_BCNIVLCUNT_8814B(x) (((x) & BIT_MASK_BCNIVLCUNT_8814B) << BIT_SHIFT_BCNIVLCUNT_8814B) -#define BIT_GET_BCNIVLCUNT_8814B(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8814B) & BIT_MASK_BCNIVLCUNT_8814B) +#define BIT_BCNIVLCUNT_8814B(x) \ + (((x) & BIT_MASK_BCNIVLCUNT_8814B) << BIT_SHIFT_BCNIVLCUNT_8814B) +#define BITS_BCNIVLCUNT_8814B \ + (BIT_MASK_BCNIVLCUNT_8814B << BIT_SHIFT_BCNIVLCUNT_8814B) +#define BIT_CLEAR_BCNIVLCUNT_8814B(x) ((x) & (~BITS_BCNIVLCUNT_8814B)) +#define BIT_GET_BCNIVLCUNT_8814B(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT_8814B) & BIT_MASK_BCNIVLCUNT_8814B) +#define BIT_SET_BCNIVLCUNT_8814B(x, v) \ + (BIT_CLEAR_BCNIVLCUNT_8814B(x) | BIT_BCNIVLCUNT_8814B(v)) + +/* 2 REG_EARLY_128US_CFG_8814B */ + +#define BIT_SHIFT_EARLY_128US_8814B 0 +#define BIT_MASK_EARLY_128US_8814B 0x7 +#define BIT_EARLY_128US_8814B(x) \ + (((x) & BIT_MASK_EARLY_128US_8814B) << BIT_SHIFT_EARLY_128US_8814B) +#define BITS_EARLY_128US_8814B \ + (BIT_MASK_EARLY_128US_8814B << BIT_SHIFT_EARLY_128US_8814B) +#define BIT_CLEAR_EARLY_128US_8814B(x) ((x) & (~BITS_EARLY_128US_8814B)) +#define BIT_GET_EARLY_128US_8814B(x) \ + (((x) >> BIT_SHIFT_EARLY_128US_8814B) & BIT_MASK_EARLY_128US_8814B) +#define BIT_SET_EARLY_128US_8814B(x, v) \ + (BIT_CLEAR_EARLY_128US_8814B(x) | BIT_EARLY_128US_8814B(v)) + +/* 2 REG_TSFTR_SYNC_OFFSET_CFG_8814B */ + +#define BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B 0 +#define BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B 0xffffff +#define BIT_TSFTR_SNC_OFFSET_V1_8814B(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B) \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B) +#define BITS_TSFTR_SNC_OFFSET_V1_8814B \ + (BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_V1_8814B(x) \ + ((x) & (~BITS_TSFTR_SNC_OFFSET_V1_8814B)) +#define BIT_GET_TSFTR_SNC_OFFSET_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B) & \ + BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B) +#define BIT_SET_TSFTR_SNC_OFFSET_V1_8814B(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_V1_8814B(x) | \ + BIT_TSFTR_SNC_OFFSET_V1_8814B(v)) + +/* 2 REG_TSFTR_SYNC_CTRL_CFG_8814B */ +#define BIT_SYNC_TSF_NOW_V1_8814B BIT(5) +#define BIT_SYNC_TSF_ONCE_8814B BIT(4) +#define BIT_SYNC_TSF_AUTO_8814B BIT(3) + +#define BIT_SHIFT_SYNC_PORT_SEL_8814B 0 +#define BIT_MASK_SYNC_PORT_SEL_8814B 0x7 +#define BIT_SYNC_PORT_SEL_8814B(x) \ + (((x) & BIT_MASK_SYNC_PORT_SEL_8814B) << BIT_SHIFT_SYNC_PORT_SEL_8814B) +#define BITS_SYNC_PORT_SEL_8814B \ + (BIT_MASK_SYNC_PORT_SEL_8814B << BIT_SHIFT_SYNC_PORT_SEL_8814B) +#define BIT_CLEAR_SYNC_PORT_SEL_8814B(x) ((x) & (~BITS_SYNC_PORT_SEL_8814B)) +#define BIT_GET_SYNC_PORT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_SYNC_PORT_SEL_8814B) & BIT_MASK_SYNC_PORT_SEL_8814B) +#define BIT_SET_SYNC_PORT_SEL_8814B(x, v) \ + (BIT_CLEAR_SYNC_PORT_SEL_8814B(x) | BIT_SYNC_PORT_SEL_8814B(v)) + +/* 2 REG_BCN_SPACE_CFG_8814B */ + +#define BIT_SHIFT_BCN_SPACE_8814B 0 +#define BIT_MASK_BCN_SPACE_8814B 0xffff +#define BIT_BCN_SPACE_8814B(x) \ + (((x) & BIT_MASK_BCN_SPACE_8814B) << BIT_SHIFT_BCN_SPACE_8814B) +#define BITS_BCN_SPACE_8814B \ + (BIT_MASK_BCN_SPACE_8814B << BIT_SHIFT_BCN_SPACE_8814B) +#define BIT_CLEAR_BCN_SPACE_8814B(x) ((x) & (~BITS_BCN_SPACE_8814B)) +#define BIT_GET_BCN_SPACE_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_8814B) & BIT_MASK_BCN_SPACE_8814B) +#define BIT_SET_BCN_SPACE_8814B(x, v) \ + (BIT_CLEAR_BCN_SPACE_8814B(x) | BIT_BCN_SPACE_8814B(v)) + +/* 2 REG_EARLY_INT_ADJUST_CFG_8814B */ + +#define BIT_SHIFT_EARLY_INT_ADJUST_8814B 0 +#define BIT_MASK_EARLY_INT_ADJUST_8814B 0xffff +#define BIT_EARLY_INT_ADJUST_8814B(x) \ + (((x) & BIT_MASK_EARLY_INT_ADJUST_8814B) \ + << BIT_SHIFT_EARLY_INT_ADJUST_8814B) +#define BITS_EARLY_INT_ADJUST_8814B \ + (BIT_MASK_EARLY_INT_ADJUST_8814B << BIT_SHIFT_EARLY_INT_ADJUST_8814B) +#define BIT_CLEAR_EARLY_INT_ADJUST_8814B(x) \ + ((x) & (~BITS_EARLY_INT_ADJUST_8814B)) +#define BIT_GET_EARLY_INT_ADJUST_8814B(x) \ + (((x) >> BIT_SHIFT_EARLY_INT_ADJUST_8814B) & \ + BIT_MASK_EARLY_INT_ADJUST_8814B) +#define BIT_SET_EARLY_INT_ADJUST_8814B(x, v) \ + (BIT_CLEAR_EARLY_INT_ADJUST_8814B(x) | BIT_EARLY_INT_ADJUST_8814B(v)) + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_NOT_VALID_8814B */ + +/* 2 REG_SW_TBTT_TSF_INFO_8814B */ + +#define BIT_SHIFT_SW_TBTT_TSF_INFO_8814B 0 +#define BIT_MASK_SW_TBTT_TSF_INFO_8814B 0xffffffffL +#define BIT_SW_TBTT_TSF_INFO_8814B(x) \ + (((x) & BIT_MASK_SW_TBTT_TSF_INFO_8814B) \ + << BIT_SHIFT_SW_TBTT_TSF_INFO_8814B) +#define BITS_SW_TBTT_TSF_INFO_8814B \ + (BIT_MASK_SW_TBTT_TSF_INFO_8814B << BIT_SHIFT_SW_TBTT_TSF_INFO_8814B) +#define BIT_CLEAR_SW_TBTT_TSF_INFO_8814B(x) \ + ((x) & (~BITS_SW_TBTT_TSF_INFO_8814B)) +#define BIT_GET_SW_TBTT_TSF_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_SW_TBTT_TSF_INFO_8814B) & \ + BIT_MASK_SW_TBTT_TSF_INFO_8814B) +#define BIT_SET_SW_TBTT_TSF_INFO_8814B(x, v) \ + (BIT_CLEAR_SW_TBTT_TSF_INFO_8814B(x) | BIT_SW_TBTT_TSF_INFO_8814B(v)) + +/* 2 REG_TSFTR_LOW_8814B */ + +#define BIT_SHIFT_TSF_TIMER_LOW_8814B 0 +#define BIT_MASK_TSF_TIMER_LOW_8814B 0xffffffffL +#define BIT_TSF_TIMER_LOW_8814B(x) \ + (((x) & BIT_MASK_TSF_TIMER_LOW_8814B) << BIT_SHIFT_TSF_TIMER_LOW_8814B) +#define BITS_TSF_TIMER_LOW_8814B \ + (BIT_MASK_TSF_TIMER_LOW_8814B << BIT_SHIFT_TSF_TIMER_LOW_8814B) +#define BIT_CLEAR_TSF_TIMER_LOW_8814B(x) ((x) & (~BITS_TSF_TIMER_LOW_8814B)) +#define BIT_GET_TSF_TIMER_LOW_8814B(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_LOW_8814B) & BIT_MASK_TSF_TIMER_LOW_8814B) +#define BIT_SET_TSF_TIMER_LOW_8814B(x, v) \ + (BIT_CLEAR_TSF_TIMER_LOW_8814B(x) | BIT_TSF_TIMER_LOW_8814B(v)) + +/* 2 REG_TSFTR_HIGH_8814B */ + +#define BIT_SHIFT_TSF_TIMER_HIGH_8814B 0 +#define BIT_MASK_TSF_TIMER_HIGH_8814B 0xffffffffL +#define BIT_TSF_TIMER_HIGH_8814B(x) \ + (((x) & BIT_MASK_TSF_TIMER_HIGH_8814B) \ + << BIT_SHIFT_TSF_TIMER_HIGH_8814B) +#define BITS_TSF_TIMER_HIGH_8814B \ + (BIT_MASK_TSF_TIMER_HIGH_8814B << BIT_SHIFT_TSF_TIMER_HIGH_8814B) +#define BIT_CLEAR_TSF_TIMER_HIGH_8814B(x) ((x) & (~BITS_TSF_TIMER_HIGH_8814B)) +#define BIT_GET_TSF_TIMER_HIGH_8814B(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_HIGH_8814B) & \ + BIT_MASK_TSF_TIMER_HIGH_8814B) +#define BIT_SET_TSF_TIMER_HIGH_8814B(x, v) \ + (BIT_CLEAR_TSF_TIMER_HIGH_8814B(x) | BIT_TSF_TIMER_HIGH_8814B(v)) + +/* 2 REG_BCN_ERR_CNT_MAC_8814B */ + +#define BIT_SHIFT_BCN_ERR_CNT_MAC_8814B 0 +#define BIT_MASK_BCN_ERR_CNT_MAC_8814B 0xff +#define BIT_BCN_ERR_CNT_MAC_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_MAC_8814B) \ + << BIT_SHIFT_BCN_ERR_CNT_MAC_8814B) +#define BITS_BCN_ERR_CNT_MAC_8814B \ + (BIT_MASK_BCN_ERR_CNT_MAC_8814B << BIT_SHIFT_BCN_ERR_CNT_MAC_8814B) +#define BIT_CLEAR_BCN_ERR_CNT_MAC_8814B(x) ((x) & (~BITS_BCN_ERR_CNT_MAC_8814B)) +#define BIT_GET_BCN_ERR_CNT_MAC_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_MAC_8814B) & \ + BIT_MASK_BCN_ERR_CNT_MAC_8814B) +#define BIT_SET_BCN_ERR_CNT_MAC_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_MAC_8814B(x) | BIT_BCN_ERR_CNT_MAC_8814B(v)) + +/* 2 REG_BCN_ERR_CNT_EDCCA_8814B */ + +#define BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B 0 +#define BIT_MASK_BCN_ERR_CNT_EDCCA_8814B 0xff +#define BIT_BCN_ERR_CNT_EDCCA_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_EDCCA_8814B) \ + << BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B) +#define BITS_BCN_ERR_CNT_EDCCA_8814B \ + (BIT_MASK_BCN_ERR_CNT_EDCCA_8814B << BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B) +#define BIT_CLEAR_BCN_ERR_CNT_EDCCA_8814B(x) \ + ((x) & (~BITS_BCN_ERR_CNT_EDCCA_8814B)) +#define BIT_GET_BCN_ERR_CNT_EDCCA_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B) & \ + BIT_MASK_BCN_ERR_CNT_EDCCA_8814B) +#define BIT_SET_BCN_ERR_CNT_EDCCA_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_EDCCA_8814B(x) | BIT_BCN_ERR_CNT_EDCCA_8814B(v)) + +/* 2 REG_BCN_ERR_CNT_CCA_8814B */ + +#define BIT_SHIFT_BCN_ERR_CNT_CCA_8814B 0 +#define BIT_MASK_BCN_ERR_CNT_CCA_8814B 0xff +#define BIT_BCN_ERR_CNT_CCA_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_CCA_8814B) \ + << BIT_SHIFT_BCN_ERR_CNT_CCA_8814B) +#define BITS_BCN_ERR_CNT_CCA_8814B \ + (BIT_MASK_BCN_ERR_CNT_CCA_8814B << BIT_SHIFT_BCN_ERR_CNT_CCA_8814B) +#define BIT_CLEAR_BCN_ERR_CNT_CCA_8814B(x) ((x) & (~BITS_BCN_ERR_CNT_CCA_8814B)) +#define BIT_GET_BCN_ERR_CNT_CCA_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_CCA_8814B) & \ + BIT_MASK_BCN_ERR_CNT_CCA_8814B) +#define BIT_SET_BCN_ERR_CNT_CCA_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_CCA_8814B(x) | BIT_BCN_ERR_CNT_CCA_8814B(v)) + +/* 2 REG_BCN_ERR_CNT_INVALID_8814B */ + +#define BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B 0 +#define BIT_MASK_BCN_ERR_CNT_INVALID_8814B 0xff +#define BIT_BCN_ERR_CNT_INVALID_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_INVALID_8814B) \ + << BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B) +#define BITS_BCN_ERR_CNT_INVALID_8814B \ + (BIT_MASK_BCN_ERR_CNT_INVALID_8814B \ + << BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B) +#define BIT_CLEAR_BCN_ERR_CNT_INVALID_8814B(x) \ + ((x) & (~BITS_BCN_ERR_CNT_INVALID_8814B)) +#define BIT_GET_BCN_ERR_CNT_INVALID_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B) & \ + BIT_MASK_BCN_ERR_CNT_INVALID_8814B) +#define BIT_SET_BCN_ERR_CNT_INVALID_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_INVALID_8814B(x) | \ + BIT_BCN_ERR_CNT_INVALID_8814B(v)) + +/* 2 REG_BCN_ERR_CNT_OTHERS_8814B */ + +#define BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B 0 +#define BIT_MASK_BCN_ERR_CNT_OTHERS_8814B 0xff +#define BIT_BCN_ERR_CNT_OTHERS_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_CNT_OTHERS_8814B) \ + << BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B) +#define BITS_BCN_ERR_CNT_OTHERS_8814B \ + (BIT_MASK_BCN_ERR_CNT_OTHERS_8814B \ + << BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B) +#define BIT_CLEAR_BCN_ERR_CNT_OTHERS_8814B(x) \ + ((x) & (~BITS_BCN_ERR_CNT_OTHERS_8814B)) +#define BIT_GET_BCN_ERR_CNT_OTHERS_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B) & \ + BIT_MASK_BCN_ERR_CNT_OTHERS_8814B) +#define BIT_SET_BCN_ERR_CNT_OTHERS_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_CNT_OTHERS_8814B(x) | \ + BIT_BCN_ERR_CNT_OTHERS_8814B(v)) + +/* 2 REG_RX_BCN_TIMER_8814B */ + +#define BIT_SHIFT_RX_BCN_TIMER_8814B 0 +#define BIT_MASK_RX_BCN_TIMER_8814B 0xffff +#define BIT_RX_BCN_TIMER_8814B(x) \ + (((x) & BIT_MASK_RX_BCN_TIMER_8814B) << BIT_SHIFT_RX_BCN_TIMER_8814B) +#define BITS_RX_BCN_TIMER_8814B \ + (BIT_MASK_RX_BCN_TIMER_8814B << BIT_SHIFT_RX_BCN_TIMER_8814B) +#define BIT_CLEAR_RX_BCN_TIMER_8814B(x) ((x) & (~BITS_RX_BCN_TIMER_8814B)) +#define BIT_GET_RX_BCN_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TIMER_8814B) & BIT_MASK_RX_BCN_TIMER_8814B) +#define BIT_SET_RX_BCN_TIMER_8814B(x, v) \ + (BIT_CLEAR_RX_BCN_TIMER_8814B(x) | BIT_RX_BCN_TIMER_8814B(v)) + +/* 2 REG_TBTT_CTN_AREA_V1_8814B */ + +#define BIT_SHIFT_TBTT_CTN_AREA_8814B 0 +#define BIT_MASK_TBTT_CTN_AREA_8814B 0xff +#define BIT_TBTT_CTN_AREA_8814B(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA_8814B) << BIT_SHIFT_TBTT_CTN_AREA_8814B) +#define BITS_TBTT_CTN_AREA_8814B \ + (BIT_MASK_TBTT_CTN_AREA_8814B << BIT_SHIFT_TBTT_CTN_AREA_8814B) +#define BIT_CLEAR_TBTT_CTN_AREA_8814B(x) ((x) & (~BITS_TBTT_CTN_AREA_8814B)) +#define BIT_GET_TBTT_CTN_AREA_8814B(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8814B) & BIT_MASK_TBTT_CTN_AREA_8814B) +#define BIT_SET_TBTT_CTN_AREA_8814B(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA_8814B(x) | BIT_TBTT_CTN_AREA_8814B(v)) + +/* 2 REG_BCN_MAX_ERR_V1_8814B */ + +#define BIT_SHIFT_BCN_MAX_ERR_8814B 0 +#define BIT_MASK_BCN_MAX_ERR_8814B 0xff +#define BIT_BCN_MAX_ERR_8814B(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR_8814B) << BIT_SHIFT_BCN_MAX_ERR_8814B) +#define BITS_BCN_MAX_ERR_8814B \ + (BIT_MASK_BCN_MAX_ERR_8814B << BIT_SHIFT_BCN_MAX_ERR_8814B) +#define BIT_CLEAR_BCN_MAX_ERR_8814B(x) ((x) & (~BITS_BCN_MAX_ERR_8814B)) +#define BIT_GET_BCN_MAX_ERR_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR_8814B) & BIT_MASK_BCN_MAX_ERR_8814B) +#define BIT_SET_BCN_MAX_ERR_8814B(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR_8814B(x) | BIT_BCN_MAX_ERR_8814B(v)) + +/* 2 REG_RXTSF_OFFSET_CCK_V1_8814B */ + +#define BIT_SHIFT_CCK_RXTSF_OFFSET_8814B 0 +#define BIT_MASK_CCK_RXTSF_OFFSET_8814B 0xff +#define BIT_CCK_RXTSF_OFFSET_8814B(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8814B) \ + << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) +#define BITS_CCK_RXTSF_OFFSET_8814B \ + (BIT_MASK_CCK_RXTSF_OFFSET_8814B << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) +#define BIT_CLEAR_CCK_RXTSF_OFFSET_8814B(x) \ + ((x) & (~BITS_CCK_RXTSF_OFFSET_8814B)) +#define BIT_GET_CCK_RXTSF_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) & \ + BIT_MASK_CCK_RXTSF_OFFSET_8814B) +#define BIT_SET_CCK_RXTSF_OFFSET_8814B(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET_8814B(x) | BIT_CCK_RXTSF_OFFSET_8814B(v)) + +/* 2 REG_RXTSF_OFFSET_OFDM_V1_8814B */ + +#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B 0 +#define BIT_MASK_OFDM_RXTSF_OFFSET_8814B 0xff +#define BIT_OFDM_RXTSF_OFFSET_8814B(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8814B) \ + << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) +#define BITS_OFDM_RXTSF_OFFSET_8814B \ + (BIT_MASK_OFDM_RXTSF_OFFSET_8814B << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8814B(x) \ + ((x) & (~BITS_OFDM_RXTSF_OFFSET_8814B)) +#define BIT_GET_OFDM_RXTSF_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) & \ + BIT_MASK_OFDM_RXTSF_OFFSET_8814B) +#define BIT_SET_OFDM_RXTSF_OFFSET_8814B(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET_8814B(x) | BIT_OFDM_RXTSF_OFFSET_8814B(v)) + +/* 2 REG_SUB_BCN_SPACE_8814B */ + +#define BIT_SHIFT_SUB_BCN_SPACE_V2_8814B 0 +#define BIT_MASK_SUB_BCN_SPACE_V2_8814B 0xff +#define BIT_SUB_BCN_SPACE_V2_8814B(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_V2_8814B) \ + << BIT_SHIFT_SUB_BCN_SPACE_V2_8814B) +#define BITS_SUB_BCN_SPACE_V2_8814B \ + (BIT_MASK_SUB_BCN_SPACE_V2_8814B << BIT_SHIFT_SUB_BCN_SPACE_V2_8814B) +#define BIT_CLEAR_SUB_BCN_SPACE_V2_8814B(x) \ + ((x) & (~BITS_SUB_BCN_SPACE_V2_8814B)) +#define BIT_GET_SUB_BCN_SPACE_V2_8814B(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V2_8814B) & \ + BIT_MASK_SUB_BCN_SPACE_V2_8814B) +#define BIT_SET_SUB_BCN_SPACE_V2_8814B(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_V2_8814B(x) | BIT_SUB_BCN_SPACE_V2_8814B(v)) + +/* 2 REG_MBID_NUM_V1_8814B */ + +#define BIT_SHIFT_BCN_ERR_PORT_SEL_8814B 4 +#define BIT_MASK_BCN_ERR_PORT_SEL_8814B 0xf +#define BIT_BCN_ERR_PORT_SEL_8814B(x) \ + (((x) & BIT_MASK_BCN_ERR_PORT_SEL_8814B) \ + << BIT_SHIFT_BCN_ERR_PORT_SEL_8814B) +#define BITS_BCN_ERR_PORT_SEL_8814B \ + (BIT_MASK_BCN_ERR_PORT_SEL_8814B << BIT_SHIFT_BCN_ERR_PORT_SEL_8814B) +#define BIT_CLEAR_BCN_ERR_PORT_SEL_8814B(x) \ + ((x) & (~BITS_BCN_ERR_PORT_SEL_8814B)) +#define BIT_GET_BCN_ERR_PORT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_BCN_ERR_PORT_SEL_8814B) & \ + BIT_MASK_BCN_ERR_PORT_SEL_8814B) +#define BIT_SET_BCN_ERR_PORT_SEL_8814B(x, v) \ + (BIT_CLEAR_BCN_ERR_PORT_SEL_8814B(x) | BIT_BCN_ERR_PORT_SEL_8814B(v)) + +#define BIT_SHIFT_MBID_BCN_NUM_V1_8814B 0 +#define BIT_MASK_MBID_BCN_NUM_V1_8814B 0xf +#define BIT_MBID_BCN_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_V1_8814B) \ + << BIT_SHIFT_MBID_BCN_NUM_V1_8814B) +#define BITS_MBID_BCN_NUM_V1_8814B \ + (BIT_MASK_MBID_BCN_NUM_V1_8814B << BIT_SHIFT_MBID_BCN_NUM_V1_8814B) +#define BIT_CLEAR_MBID_BCN_NUM_V1_8814B(x) ((x) & (~BITS_MBID_BCN_NUM_V1_8814B)) +#define BIT_GET_MBID_BCN_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_V1_8814B) & \ + BIT_MASK_MBID_BCN_NUM_V1_8814B) +#define BIT_SET_MBID_BCN_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_V1_8814B(x) | BIT_MBID_BCN_NUM_V1_8814B(v)) + +/* 2 REG_MBSSID_CTRL_V1_8814B */ +#define BIT_MBID_BCNQ15_EN_8814B BIT(15) +#define BIT_MBID_BCNQ14_EN_8814B BIT(14) +#define BIT_MBID_BCNQ13_EN_8814B BIT(13) +#define BIT_MBID_BCNQ12_EN_8814B BIT(12) +#define BIT_MBID_BCNQ11_EN_8814B BIT(11) +#define BIT_MBID_BCNQ10_EN_8814B BIT(10) +#define BIT_MBID_BCNQ9_EN_8814B BIT(9) +#define BIT_MBID_BCNQ8_EN_8814B BIT(8) +#define BIT_MBID_BCNQ7_EN_8814B BIT(7) +#define BIT_MBID_BCNQ6_EN_8814B BIT(6) +#define BIT_MBID_BCNQ5_EN_8814B BIT(5) +#define BIT_MBID_BCNQ4_EN_8814B BIT(4) +#define BIT_MBID_BCNQ3_EN_8814B BIT(3) +#define BIT_MBID_BCNQ2_EN_8814B BIT(2) +#define BIT_MBID_BCNQ1_EN_8814B BIT(1) +#define BIT_MBID_BCNQ0_EN_8814B BIT(0) +/* 2 REG_USTIME_TSF_V1_8814B */ +#define BIT_SHIFT_USTIME_TSF_V1_8814B 0 +#define BIT_MASK_USTIME_TSF_V1_8814B 0xff +#define BIT_USTIME_TSF_V1_8814B(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1_8814B) << BIT_SHIFT_USTIME_TSF_V1_8814B) +#define BITS_USTIME_TSF_V1_8814B \ + (BIT_MASK_USTIME_TSF_V1_8814B << BIT_SHIFT_USTIME_TSF_V1_8814B) +#define BIT_CLEAR_USTIME_TSF_V1_8814B(x) ((x) & (~BITS_USTIME_TSF_V1_8814B)) +#define BIT_GET_USTIME_TSF_V1_8814B(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1_8814B) & BIT_MASK_USTIME_TSF_V1_8814B) +#define BIT_SET_USTIME_TSF_V1_8814B(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1_8814B(x) | BIT_USTIME_TSF_V1_8814B(v)) + +/* 2 REG_BW_CFG_8814B */ +#define BIT_SLEEP_32K_EN_8814B BIT(3) +#define BIT_DIS_MARK_TSF_US_V1_8814B BIT(2) + +#define BIT_SHIFT_BW_CFG_8814B 0 +#define BIT_MASK_BW_CFG_8814B 0x3 +#define BIT_BW_CFG_8814B(x) \ + (((x) & BIT_MASK_BW_CFG_8814B) << BIT_SHIFT_BW_CFG_8814B) +#define BITS_BW_CFG_8814B (BIT_MASK_BW_CFG_8814B << BIT_SHIFT_BW_CFG_8814B) +#define BIT_CLEAR_BW_CFG_8814B(x) ((x) & (~BITS_BW_CFG_8814B)) +#define BIT_GET_BW_CFG_8814B(x) \ + (((x) >> BIT_SHIFT_BW_CFG_8814B) & BIT_MASK_BW_CFG_8814B) +#define BIT_SET_BW_CFG_8814B(x, v) \ + (BIT_CLEAR_BW_CFG_8814B(x) | BIT_BW_CFG_8814B(v)) + +/* 2 REG_ATIMWND_CFG_8814B */ + +#define BIT_SHIFT_ATIMWND_V1_8814B 0 +#define BIT_MASK_ATIMWND_V1_8814B 0xff +#define BIT_ATIMWND_V1_8814B(x) \ + (((x) & BIT_MASK_ATIMWND_V1_8814B) << BIT_SHIFT_ATIMWND_V1_8814B) +#define BITS_ATIMWND_V1_8814B \ + (BIT_MASK_ATIMWND_V1_8814B << BIT_SHIFT_ATIMWND_V1_8814B) +#define BIT_CLEAR_ATIMWND_V1_8814B(x) ((x) & (~BITS_ATIMWND_V1_8814B)) +#define BIT_GET_ATIMWND_V1_8814B(x) \ + (((x) >> BIT_SHIFT_ATIMWND_V1_8814B) & BIT_MASK_ATIMWND_V1_8814B) +#define BIT_SET_ATIMWND_V1_8814B(x, v) \ + (BIT_CLEAR_ATIMWND_V1_8814B(x) | BIT_ATIMWND_V1_8814B(v)) + +/* 2 REG_DTIM_COUNTER_CFG_8814B */ + +#define BIT_SHIFT_DTIM_COUNT_8814B 0 +#define BIT_MASK_DTIM_COUNT_8814B 0xff +#define BIT_DTIM_COUNT_8814B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_8814B) << BIT_SHIFT_DTIM_COUNT_8814B) +#define BITS_DTIM_COUNT_8814B \ + (BIT_MASK_DTIM_COUNT_8814B << BIT_SHIFT_DTIM_COUNT_8814B) +#define BIT_CLEAR_DTIM_COUNT_8814B(x) ((x) & (~BITS_DTIM_COUNT_8814B)) +#define BIT_GET_DTIM_COUNT_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_8814B) & BIT_MASK_DTIM_COUNT_8814B) +#define BIT_SET_DTIM_COUNT_8814B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_8814B(x) | BIT_DTIM_COUNT_8814B(v)) + +/* 2 REG_ATIM_DTIM_CTRL_SEL_8814B */ +#define BIT_DTIM_BYPASS_V1_8814B BIT(7) + +#define BIT_SHIFT_ATIM_DTIM_SEL_8814B 0 +#define BIT_MASK_ATIM_DTIM_SEL_8814B 0x1f +#define BIT_ATIM_DTIM_SEL_8814B(x) \ + (((x) & BIT_MASK_ATIM_DTIM_SEL_8814B) << BIT_SHIFT_ATIM_DTIM_SEL_8814B) +#define BITS_ATIM_DTIM_SEL_8814B \ + (BIT_MASK_ATIM_DTIM_SEL_8814B << BIT_SHIFT_ATIM_DTIM_SEL_8814B) +#define BIT_CLEAR_ATIM_DTIM_SEL_8814B(x) ((x) & (~BITS_ATIM_DTIM_SEL_8814B)) +#define BIT_GET_ATIM_DTIM_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_ATIM_DTIM_SEL_8814B) & BIT_MASK_ATIM_DTIM_SEL_8814B) +#define BIT_SET_ATIM_DTIM_SEL_8814B(x, v) \ + (BIT_CLEAR_ATIM_DTIM_SEL_8814B(x) | BIT_ATIM_DTIM_SEL_8814B(v)) + +/* 2 REG_ATIMUGT_V1_8814B */ -/* 2 REG_BCNDROPCTRL_8814B */ +#define BIT_SHIFT_ATIM_URGENT_8814B 0 +#define BIT_MASK_ATIM_URGENT_8814B 0xff +#define BIT_ATIM_URGENT_8814B(x) \ + (((x) & BIT_MASK_ATIM_URGENT_8814B) << BIT_SHIFT_ATIM_URGENT_8814B) +#define BITS_ATIM_URGENT_8814B \ + (BIT_MASK_ATIM_URGENT_8814B << BIT_SHIFT_ATIM_URGENT_8814B) +#define BIT_CLEAR_ATIM_URGENT_8814B(x) ((x) & (~BITS_ATIM_URGENT_8814B)) +#define BIT_GET_ATIM_URGENT_8814B(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_8814B) & BIT_MASK_ATIM_URGENT_8814B) +#define BIT_SET_ATIM_URGENT_8814B(x, v) \ + (BIT_CLEAR_ATIM_URGENT_8814B(x) | BIT_ATIM_URGENT_8814B(v)) + +/* 2 REG_BCNDROPCTRL_V1_8814B */ #define BIT_BEACON_DROP_EN_8814B BIT(7) #define BIT_SHIFT_BEACON_DROP_IVL_8814B 0 #define BIT_MASK_BEACON_DROP_IVL_8814B 0x7f -#define BIT_BEACON_DROP_IVL_8814B(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8814B) << BIT_SHIFT_BEACON_DROP_IVL_8814B) -#define BIT_GET_BEACON_DROP_IVL_8814B(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8814B) & BIT_MASK_BEACON_DROP_IVL_8814B) - - +#define BIT_BEACON_DROP_IVL_8814B(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL_8814B) \ + << BIT_SHIFT_BEACON_DROP_IVL_8814B) +#define BITS_BEACON_DROP_IVL_8814B \ + (BIT_MASK_BEACON_DROP_IVL_8814B << BIT_SHIFT_BEACON_DROP_IVL_8814B) +#define BIT_CLEAR_BEACON_DROP_IVL_8814B(x) ((x) & (~BITS_BEACON_DROP_IVL_8814B)) +#define BIT_GET_BEACON_DROP_IVL_8814B(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8814B) & \ + BIT_MASK_BEACON_DROP_IVL_8814B) +#define BIT_SET_BEACON_DROP_IVL_8814B(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL_8814B(x) | BIT_BEACON_DROP_IVL_8814B(v)) -/* 2 REG_HGQ_TIMEOUT_PERIOD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B 0 -#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B 0xff -#define BIT_HGQ_TIMEOUT_PERIOD_8814B(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) -#define BIT_GET_HGQ_TIMEOUT_PERIOD_8814B(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B) +/* 2 REG_DIS_ATIM_V1_8814B */ +#define BIT_DIS_ATIM_P4_8814B BIT(19) +#define BIT_DIS_ATIM_P3_8814B BIT(18) +#define BIT_DIS_ATIM_P2_8814B BIT(17) +#define BIT_DIS_ATIM_P1_8814B BIT(16) +#define BIT_DIS_ATIM_VAP15_8814B BIT(15) +#define BIT_DIS_ATIM_VAP14_8814B BIT(14) +#define BIT_DIS_ATIM_VAP13_8814B BIT(13) +#define BIT_DIS_ATIM_VAP12_8814B BIT(12) +#define BIT_DIS_ATIM_VAP11_8814B BIT(11) +#define BIT_DIS_ATIM_VAP10_8814B BIT(10) +#define BIT_DIS_ATIM_VAP9_8814B BIT(9) +#define BIT_DIS_ATIM_VAP8_8814B BIT(8) +#define BIT_DIS_ATIM_VAP7_8814B BIT(7) +#define BIT_DIS_ATIM_VAP6_8814B BIT(6) +#define BIT_DIS_ATIM_VAP5_8814B BIT(5) +#define BIT_DIS_ATIM_VAP4_8814B BIT(4) +#define BIT_DIS_ATIM_VAP3_8814B BIT(3) +#define BIT_DIS_ATIM_VAP2_8814B BIT(2) +#define BIT_DIS_ATIM_VAP1_8814B BIT(1) +#define BIT_DIS_ATIM_ROOT_P0_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_HIQ_NO_LMT_EN_V1_8814B */ +#define BIT_HIQ_NO_LMT_EN_P4_8814B BIT(19) +#define BIT_HIQ_NO_LMT_EN_P3_8814B BIT(18) +#define BIT_HIQ_NO_LMT_EN_P2_8814B BIT(17) +#define BIT_HIQ_NO_LMT_EN_P1_8814B BIT(16) +#define BIT_HIQ_NO_LMT_EN_VAP15_8814B BIT(15) +#define BIT_HIQ_NO_LMT_EN_VAP14_8814B BIT(14) +#define BIT_HIQ_NO_LMT_EN_VAP13_8814B BIT(13) +#define BIT_HIQ_NO_LMT_EN_VAP12_8814B BIT(12) +#define BIT_HIQ_NO_LMT_EN_VAP11_8814B BIT(11) +#define BIT_HIQ_NO_LMT_EN_VAP10_8814B BIT(10) +#define BIT_HIQ_NO_LMT_EN_VAP9_8814B BIT(9) +#define BIT_HIQ_NO_LMT_EN_VAP8_8814B BIT(8) +#define BIT_HIQ_NO_LMT_EN_VAP7_8814B BIT(7) +#define BIT_HIQ_NO_LMT_EN_VAP6_8814B BIT(6) +#define BIT_HIQ_NO_LMT_EN_VAP5_8814B BIT(5) +#define BIT_HIQ_NO_LMT_EN_VAP4_8814B BIT(4) +#define BIT_HIQ_NO_LMT_EN_VAP3_8814B BIT(3) +#define BIT_HIQ_NO_LMT_EN_VAP2_8814B BIT(2) +#define BIT_HIQ_NO_LMT_EN_VAP1_8814B BIT(1) +#define BIT_HIQ_NO_LMT_EN_ROOT_P0_8814B BIT(0) -/* 2 REG_TXCMD_TIMEOUT_PERIOD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B 0 -#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B 0xff -#define BIT_TXCMD_TIMEOUT_PERIOD_8814B(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) -#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8814B(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B) +/* 2 REG_P2PPS_CTRL_V1_8814B */ +#define BIT_P2P_PWR_RST1_V2_8814B BIT(15) +#define BIT_P2P_PWR_RST0_V2_8814B BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P_V1_8814B BIT(13) + +#define BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B 8 +#define BIT_MASK_NOA_UNIT0_SEL_V1_8814B 0x7 +#define BIT_NOA_UNIT0_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_V1_8814B) \ + << BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B) +#define BITS_NOA_UNIT0_SEL_V1_8814B \ + (BIT_MASK_NOA_UNIT0_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B) +#define BIT_CLEAR_NOA_UNIT0_SEL_V1_8814B(x) \ + ((x) & (~BITS_NOA_UNIT0_SEL_V1_8814B)) +#define BIT_GET_NOA_UNIT0_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B) & \ + BIT_MASK_NOA_UNIT0_SEL_V1_8814B) +#define BIT_SET_NOA_UNIT0_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_V1_8814B(x) | BIT_NOA_UNIT0_SEL_V1_8814B(v)) + +#define BIT_P2P_CTW_ALLSTASLEEP_V1_8814B BIT(7) +#define BIT_P2P_OFF_DISTX_EN_V1_8814B BIT(6) +#define BIT_PWR_MGT_EN_V1_8814B BIT(5) +#define BIT_P2P_NOA1_EN_V1_8814B BIT(2) +#define BIT_P2P_NOA0_EN_V1_8814B BIT(1) + +/* 2 REG_P2PPS_SPEC_STATE_V1_8814B */ +#define BIT_SPEC_POWER_STATE_8814B BIT(7) +#define BIT_SPEC_CTWINDOW_ON_8814B BIT(6) +#define BIT_SPEC_BEACON_AREA_ON_8814B BIT(5) +#define BIT_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4) +#define BIT_SPEC_NOA1_OFF_PERIOD_8814B BIT(3) +#define BIT_SPEC_FORCE_DOZE1_8814B BIT(2) +#define BIT_SPEC_NOA0_OFF_PERIOD_8814B BIT(1) +#define BIT_SPEC_FORCE_DOZE0_8814B BIT(0) +/* 2 REG_P2PPS_STATE_V1_8814B */ +#define BIT_POWER_STATE_8814B BIT(7) +#define BIT_CTWINDOW_ON_8814B BIT(6) +#define BIT_BEACON_AREA_ON_8814B BIT(5) +#define BIT_CTWIN_EARLY_DISTX_8814B BIT(4) +#define BIT_NOA1_OFF_PERIOD_8814B BIT(3) +#define BIT_FORCE_DOZE1_8814B BIT(2) +#define BIT_NOA0_OFF_PERIOD_8814B BIT(1) +#define BIT_FORCE_DOZE0_8814B BIT(0) +/* 2 REG_P2PPS1_CTRL_V1_8814B */ +#define BIT_P2P1_PWR_RST1_V2_8814B BIT(15) +#define BIT_P2P1_PWR_RST0_V2_8814B BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P1_V1_8814B BIT(13) + +#define BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B 8 +#define BIT_MASK_NOA_UNIT1_SEL_V1_8814B 0x7 +#define BIT_NOA_UNIT1_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_V1_8814B) \ + << BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B) +#define BITS_NOA_UNIT1_SEL_V1_8814B \ + (BIT_MASK_NOA_UNIT1_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B) +#define BIT_CLEAR_NOA_UNIT1_SEL_V1_8814B(x) \ + ((x) & (~BITS_NOA_UNIT1_SEL_V1_8814B)) +#define BIT_GET_NOA_UNIT1_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B) & \ + BIT_MASK_NOA_UNIT1_SEL_V1_8814B) +#define BIT_SET_NOA_UNIT1_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_V1_8814B(x) | BIT_NOA_UNIT1_SEL_V1_8814B(v)) + +#define BIT_P2P1_CTW_ALLSTASLEEP_V1_8814B BIT(7) +#define BIT_P2P1_OFF_DISTX_EN_8814B BIT(6) +#define BIT_P2P1_PWR_MGT_EN_V1_8814B BIT(5) +#define BIT_P2P1_NOA1_EN_V1_8814B BIT(2) +#define BIT_P2P1_NOA0_EN_V1_8814B BIT(1) -/* 2 REG_MISC_CTRL_8814B */ -#define BIT_DIS_TRX_CAL_BCN_8814B BIT(5) -#define BIT_DIS_TX_CAL_TBTT_8814B BIT(4) -#define BIT_EN_FREECNT_8814B BIT(3) -#define BIT_BCN_AGGRESSION_8814B BIT(2) - -#define BIT_SHIFT_DIS_SECONDARY_CCA_8814B 0 -#define BIT_MASK_DIS_SECONDARY_CCA_8814B 0x3 -#define BIT_DIS_SECONDARY_CCA_8814B(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8814B) << BIT_SHIFT_DIS_SECONDARY_CCA_8814B) -#define BIT_GET_DIS_SECONDARY_CCA_8814B(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8814B) & BIT_MASK_DIS_SECONDARY_CCA_8814B) - - - -/* 2 REG_BCN_CTRL_CLINT1_8814B */ -#define BIT_CLI1_DIS_RX_BSSID_FIT_8814B BIT(6) -#define BIT_CLI1_DIS_TSF_UDT_8814B BIT(4) -#define BIT_CLI1_EN_BCN_FUNCTION_8814B BIT(3) -#define BIT_CLI1_EN_RXBCN_RPT_8814B BIT(2) -#define BIT_CLI1_ENP2P_CTWINDOW_8814B BIT(1) -#define BIT_CLI1_ENP2P_BCNQ_AREA_8814B BIT(0) - -/* 2 REG_BCN_CTRL_CLINT2_8814B */ -#define BIT_CLI2_DIS_RX_BSSID_FIT_8814B BIT(6) -#define BIT_CLI2_DIS_TSF_UDT_8814B BIT(4) -#define BIT_CLI2_EN_BCN_FUNCTION_8814B BIT(3) -#define BIT_CLI2_EN_RXBCN_RPT_8814B BIT(2) -#define BIT_CLI2_ENP2P_CTWINDOW_8814B BIT(1) -#define BIT_CLI2_ENP2P_BCNQ_AREA_8814B BIT(0) - -/* 2 REG_BCN_CTRL_CLINT3_8814B */ -#define BIT_CLI3_DIS_RX_BSSID_FIT_8814B BIT(6) -#define BIT_CLI3_DIS_TSF_UDT_8814B BIT(4) -#define BIT_CLI3_EN_BCN_FUNCTION_8814B BIT(3) -#define BIT_CLI3_EN_RXBCN_RPT_8814B BIT(2) -#define BIT_CLI3_ENP2P_CTWINDOW_8814B BIT(1) -#define BIT_CLI3_ENP2P_BCNQ_AREA_8814B BIT(0) - -/* 2 REG_EXTEND_CTRL_8814B */ -#define BIT_EN_TSFBIT32_RST_P2P2_8814B BIT(5) -#define BIT_EN_TSFBIT32_RST_P2P1_8814B BIT(4) - -#define BIT_SHIFT_PORT_SEL_8814B 0 -#define BIT_MASK_PORT_SEL_8814B 0x7 -#define BIT_PORT_SEL_8814B(x) (((x) & BIT_MASK_PORT_SEL_8814B) << BIT_SHIFT_PORT_SEL_8814B) -#define BIT_GET_PORT_SEL_8814B(x) (((x) >> BIT_SHIFT_PORT_SEL_8814B) & BIT_MASK_PORT_SEL_8814B) - - - -/* 2 REG_P2PPS1_SPEC_STATE_8814B */ -#define BIT_P2P1_SPEC_POWER_STATE_8814B BIT(7) +/* 2 REG_P2PPS1_SPEC_STATE_V1_8814B */ +#define BIT_P2P1_SPEC_POWER_STATEP_8814B BIT(7) #define BIT_P2P1_SPEC_CTWINDOW_ON_8814B BIT(6) -#define BIT_P2P1_SPEC_BCN_AREA_ON_8814B BIT(5) +#define BIT_P2P1_SPEC_BEACON_AREA_ON_8814B BIT(5) #define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4) #define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8814B BIT(3) #define BIT_P2P1_SPEC_FORCE_DOZE1_8814B BIT(2) #define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8814B BIT(1) #define BIT_P2P1_SPEC_FORCE_DOZE0_8814B BIT(0) -/* 2 REG_P2PPS1_STATE_8814B */ +/* 2 REG_P2PPS1_STATE_V1_8814B */ #define BIT_P2P1_POWER_STATE_8814B BIT(7) #define BIT_P2P1_CTWINDOW_ON_8814B BIT(6) #define BIT_P2P1_BEACON_AREA_ON_8814B BIT(5) @@ -7774,17 +19140,43 @@ #define BIT_P2P1_NOA0_OFF_PERIOD_8814B BIT(1) #define BIT_P2P1_FORCE_DOZE0_8814B BIT(0) -/* 2 REG_P2PPS2_SPEC_STATE_8814B */ -#define BIT_P2P2_SPEC_POWER_STATE_8814B BIT(7) +/* 2 REG_P2PPS2_CTRL_V1_8814B */ +#define BIT_P2P2_PWR_RST1_V2_8814B BIT(15) +#define BIT_P2P2_PWR_RST0_V2_8814B BIT(14) +#define BIT_EN_TSFBIT32_RST_P2P2_V1_8814B BIT(13) + +#define BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B 8 +#define BIT_MASK_NOA_UNIT2_SEL_V1_8814B 0x7 +#define BIT_NOA_UNIT2_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_V1_8814B) \ + << BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B) +#define BITS_NOA_UNIT2_SEL_V1_8814B \ + (BIT_MASK_NOA_UNIT2_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B) +#define BIT_CLEAR_NOA_UNIT2_SEL_V1_8814B(x) \ + ((x) & (~BITS_NOA_UNIT2_SEL_V1_8814B)) +#define BIT_GET_NOA_UNIT2_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B) & \ + BIT_MASK_NOA_UNIT2_SEL_V1_8814B) +#define BIT_SET_NOA_UNIT2_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_V1_8814B(x) | BIT_NOA_UNIT2_SEL_V1_8814B(v)) + +#define BIT_P2P2_CTW_ALLSTASLEEP_V1_8814B BIT(7) +#define BIT_P2P2_OFF_DISTX_EN_V1_8814B BIT(6) +#define BIT_P2P2_PWR_MGT_EN_V1_8814B BIT(5) +#define BIT_P2P2_NOA1_EN_V1_8814B BIT(2) +#define BIT_P2P2_NOA0_EN_V1_8814B BIT(1) + +/* 2 REG_P2PPS2_SPEC_STATE_V1_8814B */ +#define BIT_P2P2_SPEC_POWER_STATEP_8814B BIT(7) #define BIT_P2P2_SPEC_CTWINDOW_ON_8814B BIT(6) -#define BIT_P2P2_SPEC_BCN_AREA_ON_8814B BIT(5) +#define BIT_P2P2_SPEC_BEACON_AREA_ON_8814B BIT(5) #define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4) #define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8814B BIT(3) #define BIT_P2P2_SPEC_FORCE_DOZE1_8814B BIT(2) #define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8814B BIT(1) #define BIT_P2P2_SPEC_FORCE_DOZE0_8814B BIT(0) -/* 2 REG_P2PPS2_STATE_8814B */ +/* 2 REG_P2PPS2_STATE_V1_8814B */ #define BIT_P2P2_POWER_STATE_8814B BIT(7) #define BIT_P2P2_CTWINDOW_ON_8814B BIT(6) #define BIT_P2P2_BEACON_AREA_ON_8814B BIT(5) @@ -7794,428 +19186,1037 @@ #define BIT_P2P2_NOA0_OFF_PERIOD_8814B BIT(1) #define BIT_P2P2_FORCE_DOZE0_8814B BIT(0) -/* 2 REG_PS_TIMER0_8814B */ - -#define BIT_SHIFT_PSTIMER0_INT_8814B 5 -#define BIT_MASK_PSTIMER0_INT_8814B 0x7ffffff -#define BIT_PSTIMER0_INT_8814B(x) (((x) & BIT_MASK_PSTIMER0_INT_8814B) << BIT_SHIFT_PSTIMER0_INT_8814B) -#define BIT_GET_PSTIMER0_INT_8814B(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8814B) & BIT_MASK_PSTIMER0_INT_8814B) - - - -/* 2 REG_PS_TIMER1_8814B */ - -#define BIT_SHIFT_PSTIMER1_INT_8814B 5 -#define BIT_MASK_PSTIMER1_INT_8814B 0x7ffffff -#define BIT_PSTIMER1_INT_8814B(x) (((x) & BIT_MASK_PSTIMER1_INT_8814B) << BIT_SHIFT_PSTIMER1_INT_8814B) -#define BIT_GET_PSTIMER1_INT_8814B(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8814B) & BIT_MASK_PSTIMER1_INT_8814B) - - - -/* 2 REG_PS_TIMER2_8814B */ - -#define BIT_SHIFT_PSTIMER2_INT_8814B 5 -#define BIT_MASK_PSTIMER2_INT_8814B 0x7ffffff -#define BIT_PSTIMER2_INT_8814B(x) (((x) & BIT_MASK_PSTIMER2_INT_8814B) << BIT_SHIFT_PSTIMER2_INT_8814B) -#define BIT_GET_PSTIMER2_INT_8814B(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8814B) & BIT_MASK_PSTIMER2_INT_8814B) - - - -/* 2 REG_TBTT_CTN_AREA_8814B */ - -#define BIT_SHIFT_TBTT_CTN_AREA_8814B 0 -#define BIT_MASK_TBTT_CTN_AREA_8814B 0xff -#define BIT_TBTT_CTN_AREA_8814B(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8814B) << BIT_SHIFT_TBTT_CTN_AREA_8814B) -#define BIT_GET_TBTT_CTN_AREA_8814B(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8814B) & BIT_MASK_TBTT_CTN_AREA_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_FORCE_BCN_IFS_8814B */ - -#define BIT_SHIFT_FORCE_BCN_IFS_8814B 0 -#define BIT_MASK_FORCE_BCN_IFS_8814B 0xff -#define BIT_FORCE_BCN_IFS_8814B(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8814B) << BIT_SHIFT_FORCE_BCN_IFS_8814B) -#define BIT_GET_FORCE_BCN_IFS_8814B(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8814B) & BIT_MASK_FORCE_BCN_IFS_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_TXOP_MIN_8814B */ - -#define BIT_SHIFT_TXOP_MIN_8814B 0 -#define BIT_MASK_TXOP_MIN_8814B 0x3fff -#define BIT_TXOP_MIN_8814B(x) (((x) & BIT_MASK_TXOP_MIN_8814B) << BIT_SHIFT_TXOP_MIN_8814B) -#define BIT_GET_TXOP_MIN_8814B(x) (((x) >> BIT_SHIFT_TXOP_MIN_8814B) & BIT_MASK_TXOP_MIN_8814B) - - - -/* 2 REG_PRE_BKF_TIME_8814B */ - -#define BIT_SHIFT_PRE_BKF_TIME_8814B 0 -#define BIT_MASK_PRE_BKF_TIME_8814B 0xff -#define BIT_PRE_BKF_TIME_8814B(x) (((x) & BIT_MASK_PRE_BKF_TIME_8814B) << BIT_SHIFT_PRE_BKF_TIME_8814B) -#define BIT_GET_PRE_BKF_TIME_8814B(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8814B) & BIT_MASK_PRE_BKF_TIME_8814B) - - - -/* 2 REG_CROSS_TXOP_CTRL_8814B */ -#define BIT_TXFAIL_BREACK_TXOP_EN_8814B BIT(3) -#define BIT_DTIM_BYPASS_8814B BIT(2) -#define BIT_RTS_NAV_TXOP_8814B BIT(1) -#define BIT_NOT_CROSS_TXOP_8814B BIT(0) - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_ATIMWND2_8814B */ - -#define BIT_SHIFT_ATIMWND2_8814B 0 -#define BIT_MASK_ATIMWND2_8814B 0xff -#define BIT_ATIMWND2_8814B(x) (((x) & BIT_MASK_ATIMWND2_8814B) << BIT_SHIFT_ATIMWND2_8814B) -#define BIT_GET_ATIMWND2_8814B(x) (((x) >> BIT_SHIFT_ATIMWND2_8814B) & BIT_MASK_ATIMWND2_8814B) - +/* 2 REG_P2PON_DIS_TXTIME_V1_8814B */ +#define BIT_SHIFT_P2PON_DIS_TXTIME_8814B 0 +#define BIT_MASK_P2PON_DIS_TXTIME_8814B 0xff +#define BIT_P2PON_DIS_TXTIME_8814B(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME_8814B) \ + << BIT_SHIFT_P2PON_DIS_TXTIME_8814B) +#define BITS_P2PON_DIS_TXTIME_8814B \ + (BIT_MASK_P2PON_DIS_TXTIME_8814B << BIT_SHIFT_P2PON_DIS_TXTIME_8814B) +#define BIT_CLEAR_P2PON_DIS_TXTIME_8814B(x) \ + ((x) & (~BITS_P2PON_DIS_TXTIME_8814B)) +#define BIT_GET_P2PON_DIS_TXTIME_8814B(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8814B) & \ + BIT_MASK_P2PON_DIS_TXTIME_8814B) +#define BIT_SET_P2PON_DIS_TXTIME_8814B(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME_8814B(x) | BIT_P2PON_DIS_TXTIME_8814B(v)) + +/* 2 REG_P2POFF_DIS_TXTIME_V1_8814B */ -/* 2 REG_ATIMWND3_8814B */ - -#define BIT_SHIFT_ATIMWND3_8814B 0 -#define BIT_MASK_ATIMWND3_8814B 0xff -#define BIT_ATIMWND3_8814B(x) (((x) & BIT_MASK_ATIMWND3_8814B) << BIT_SHIFT_ATIMWND3_8814B) -#define BIT_GET_ATIMWND3_8814B(x) (((x) >> BIT_SHIFT_ATIMWND3_8814B) & BIT_MASK_ATIMWND3_8814B) +#define BIT_SHIFT_P2POFF_DIS_TXTIME_8814B 0 +#define BIT_MASK_P2POFF_DIS_TXTIME_8814B 0xff +#define BIT_P2POFF_DIS_TXTIME_8814B(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8814B) \ + << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) +#define BITS_P2POFF_DIS_TXTIME_8814B \ + (BIT_MASK_P2POFF_DIS_TXTIME_8814B << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) +#define BIT_CLEAR_P2POFF_DIS_TXTIME_8814B(x) \ + ((x) & (~BITS_P2POFF_DIS_TXTIME_8814B)) +#define BIT_GET_P2POFF_DIS_TXTIME_8814B(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) & \ + BIT_MASK_P2POFF_DIS_TXTIME_8814B) +#define BIT_SET_P2POFF_DIS_TXTIME_8814B(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME_8814B(x) | BIT_P2POFF_DIS_TXTIME_8814B(v)) + +/* 2 REG_CHG_POWER_BCN_AREA_8814B */ +#define BIT_CHG_POWER_BCN_AREA_8814B BIT(0) + +/* 2 REG_NOA_SEL_8814B */ + +#define BIT_SHIFT_NOA_SEL_V1_8814B 0 +#define BIT_MASK_NOA_SEL_V1_8814B 0x7 +#define BIT_NOA_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_NOA_SEL_V1_8814B) << BIT_SHIFT_NOA_SEL_V1_8814B) +#define BITS_NOA_SEL_V1_8814B \ + (BIT_MASK_NOA_SEL_V1_8814B << BIT_SHIFT_NOA_SEL_V1_8814B) +#define BIT_CLEAR_NOA_SEL_V1_8814B(x) ((x) & (~BITS_NOA_SEL_V1_8814B)) +#define BIT_GET_NOA_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V1_8814B) & BIT_MASK_NOA_SEL_V1_8814B) +#define BIT_SET_NOA_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_NOA_SEL_V1_8814B(x) | BIT_NOA_SEL_V1_8814B(v)) + +/* 2 REG_NOA_PARAM_V1_8814B */ + +#define BIT_SHIFT_NOA_DURATION_8814B 0 +#define BIT_MASK_NOA_DURATION_8814B 0xffffffffL +#define BIT_NOA_DURATION_8814B(x) \ + (((x) & BIT_MASK_NOA_DURATION_8814B) << BIT_SHIFT_NOA_DURATION_8814B) +#define BITS_NOA_DURATION_8814B \ + (BIT_MASK_NOA_DURATION_8814B << BIT_SHIFT_NOA_DURATION_8814B) +#define BIT_CLEAR_NOA_DURATION_8814B(x) ((x) & (~BITS_NOA_DURATION_8814B)) +#define BIT_GET_NOA_DURATION_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_8814B) & BIT_MASK_NOA_DURATION_8814B) +#define BIT_SET_NOA_DURATION_8814B(x, v) \ + (BIT_CLEAR_NOA_DURATION_8814B(x) | BIT_NOA_DURATION_8814B(v)) + +/* 2 REG_NOA_PARAM_1_V1_8814B */ + +#define BIT_SHIFT_NOA_INTERVAL_8814B 0 +#define BIT_MASK_NOA_INTERVAL_8814B 0xffffffffL +#define BIT_NOA_INTERVAL_8814B(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_8814B) << BIT_SHIFT_NOA_INTERVAL_8814B) +#define BITS_NOA_INTERVAL_8814B \ + (BIT_MASK_NOA_INTERVAL_8814B << BIT_SHIFT_NOA_INTERVAL_8814B) +#define BIT_CLEAR_NOA_INTERVAL_8814B(x) ((x) & (~BITS_NOA_INTERVAL_8814B)) +#define BIT_GET_NOA_INTERVAL_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_8814B) & BIT_MASK_NOA_INTERVAL_8814B) +#define BIT_SET_NOA_INTERVAL_8814B(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_8814B(x) | BIT_NOA_INTERVAL_8814B(v)) + +/* 2 REG_NOA_PARAM_2_V1_8814B */ + +#define BIT_SHIFT_NOA_START_TIME_8814B 0 +#define BIT_MASK_NOA_START_TIME_8814B 0xffffffffL +#define BIT_NOA_START_TIME_8814B(x) \ + (((x) & BIT_MASK_NOA_START_TIME_8814B) \ + << BIT_SHIFT_NOA_START_TIME_8814B) +#define BITS_NOA_START_TIME_8814B \ + (BIT_MASK_NOA_START_TIME_8814B << BIT_SHIFT_NOA_START_TIME_8814B) +#define BIT_CLEAR_NOA_START_TIME_8814B(x) ((x) & (~BITS_NOA_START_TIME_8814B)) +#define BIT_GET_NOA_START_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_8814B) & \ + BIT_MASK_NOA_START_TIME_8814B) +#define BIT_SET_NOA_START_TIME_8814B(x, v) \ + (BIT_CLEAR_NOA_START_TIME_8814B(x) | BIT_NOA_START_TIME_8814B(v)) + +/* 2 REG_NOA_PARAM_3_V1_8814B */ + +#define BIT_SHIFT_NOA_COUNT_V2_8814B 0 +#define BIT_MASK_NOA_COUNT_V2_8814B 0xffffffffL +#define BIT_NOA_COUNT_V2_8814B(x) \ + (((x) & BIT_MASK_NOA_COUNT_V2_8814B) << BIT_SHIFT_NOA_COUNT_V2_8814B) +#define BITS_NOA_COUNT_V2_8814B \ + (BIT_MASK_NOA_COUNT_V2_8814B << BIT_SHIFT_NOA_COUNT_V2_8814B) +#define BIT_CLEAR_NOA_COUNT_V2_8814B(x) ((x) & (~BITS_NOA_COUNT_V2_8814B)) +#define BIT_GET_NOA_COUNT_V2_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_V2_8814B) & BIT_MASK_NOA_COUNT_V2_8814B) +#define BIT_SET_NOA_COUNT_V2_8814B(x, v) \ + (BIT_CLEAR_NOA_COUNT_V2_8814B(x) | BIT_NOA_COUNT_V2_8814B(v)) + +/* 2 REG_NOA_ON_ERLY_TIME_V1_8814B */ + +#define BIT_SHIFT__NOA_ON_ERLY_TIME_8814B 0 +#define BIT_MASK__NOA_ON_ERLY_TIME_8814B 0xff +#define BIT__NOA_ON_ERLY_TIME_8814B(x) \ + (((x) & BIT_MASK__NOA_ON_ERLY_TIME_8814B) \ + << BIT_SHIFT__NOA_ON_ERLY_TIME_8814B) +#define BITS__NOA_ON_ERLY_TIME_8814B \ + (BIT_MASK__NOA_ON_ERLY_TIME_8814B << BIT_SHIFT__NOA_ON_ERLY_TIME_8814B) +#define BIT_CLEAR__NOA_ON_ERLY_TIME_8814B(x) \ + ((x) & (~BITS__NOA_ON_ERLY_TIME_8814B)) +#define BIT_GET__NOA_ON_ERLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8814B) & \ + BIT_MASK__NOA_ON_ERLY_TIME_8814B) +#define BIT_SET__NOA_ON_ERLY_TIME_8814B(x, v) \ + (BIT_CLEAR__NOA_ON_ERLY_TIME_8814B(x) | BIT__NOA_ON_ERLY_TIME_8814B(v)) + +/* 2 REG_NOA_OFF_ERLY_TIME_V1_8814B */ + +#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B 0 +#define BIT_MASK__NOA_OFF_ERLY_TIME_8814B 0xff +#define BIT__NOA_OFF_ERLY_TIME_8814B(x) \ + (((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8814B) \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B) +#define BITS__NOA_OFF_ERLY_TIME_8814B \ + (BIT_MASK__NOA_OFF_ERLY_TIME_8814B \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B) +#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8814B(x) \ + ((x) & (~BITS__NOA_OFF_ERLY_TIME_8814B)) +#define BIT_GET__NOA_OFF_ERLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B) & \ + BIT_MASK__NOA_OFF_ERLY_TIME_8814B) +#define BIT_SET__NOA_OFF_ERLY_TIME_8814B(x, v) \ + (BIT_CLEAR__NOA_OFF_ERLY_TIME_8814B(x) | \ + BIT__NOA_OFF_ERLY_TIME_8814B(v)) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_ATIMWND4_8814B */ +/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL_8814B */ +#define BIT_P2PPS_NOA_STOP_TX_HANG_8814B BIT(31) +#define BIT_P2PPS_MACID_PAUSE_EN_8814B BIT(11) +#define BIT_P2PPS__MGQ_PAUSE_8814B BIT(10) +#define BIT_P2PPS__HIQ_PAUSE_8814B BIT(9) +#define BIT_P2PPS__BCNQ_PAUSE_8814B BIT(8) + +#define BIT_SHIFT_P2PPS_MACID_PAUSE_8814B 0 +#define BIT_MASK_P2PPS_MACID_PAUSE_8814B 0xff +#define BIT_P2PPS_MACID_PAUSE_8814B(x) \ + (((x) & BIT_MASK_P2PPS_MACID_PAUSE_8814B) \ + << BIT_SHIFT_P2PPS_MACID_PAUSE_8814B) +#define BITS_P2PPS_MACID_PAUSE_8814B \ + (BIT_MASK_P2PPS_MACID_PAUSE_8814B << BIT_SHIFT_P2PPS_MACID_PAUSE_8814B) +#define BIT_CLEAR_P2PPS_MACID_PAUSE_8814B(x) \ + ((x) & (~BITS_P2PPS_MACID_PAUSE_8814B)) +#define BIT_GET_P2PPS_MACID_PAUSE_8814B(x) \ + (((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE_8814B) & \ + BIT_MASK_P2PPS_MACID_PAUSE_8814B) +#define BIT_SET_P2PPS_MACID_PAUSE_8814B(x, v) \ + (BIT_CLEAR_P2PPS_MACID_PAUSE_8814B(x) | BIT_P2PPS_MACID_PAUSE_8814B(v)) + +/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8814B */ +#define BIT_P2PPS1_NOA_STOP_TX_HANG_8814B BIT(31) +#define BIT_P2PPS1_MACID_PAUSE_EN_8814B BIT(11) +#define BIT_P2PPS1__MGQ_PAUSE_8814B BIT(10) +#define BIT_P2PPS1__HIQ_PAUSE_8814B BIT(9) +#define BIT_P2PPS1__BCNQ_PAUSE_8814B BIT(8) + +#define BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B 0 +#define BIT_MASK_P2PPS1_MACID_PAUSE_8814B 0xff +#define BIT_P2PPS1_MACID_PAUSE_8814B(x) \ + (((x) & BIT_MASK_P2PPS1_MACID_PAUSE_8814B) \ + << BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B) +#define BITS_P2PPS1_MACID_PAUSE_8814B \ + (BIT_MASK_P2PPS1_MACID_PAUSE_8814B \ + << BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B) +#define BIT_CLEAR_P2PPS1_MACID_PAUSE_8814B(x) \ + ((x) & (~BITS_P2PPS1_MACID_PAUSE_8814B)) +#define BIT_GET_P2PPS1_MACID_PAUSE_8814B(x) \ + (((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B) & \ + BIT_MASK_P2PPS1_MACID_PAUSE_8814B) +#define BIT_SET_P2PPS1_MACID_PAUSE_8814B(x, v) \ + (BIT_CLEAR_P2PPS1_MACID_PAUSE_8814B(x) | \ + BIT_P2PPS1_MACID_PAUSE_8814B(v)) + +/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8814B */ +#define BIT_P2PPS2_NOA_STOP_TX_HANG_8814B BIT(31) +#define BIT_P2PPS2_MACID_PAUSE_EN_8814B BIT(11) +#define BIT_P2PPS2__MGQ_PAUSE_8814B BIT(10) +#define BIT_P2PPS2__HIQ_PAUSE_8814B BIT(9) +#define BIT_P2PPS2__BCNQ_PAUSE_8814B BIT(8) + +#define BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B 0 +#define BIT_MASK_P2PPS2_MACID_PAUSE_8814B 0xff +#define BIT_P2PPS2_MACID_PAUSE_8814B(x) \ + (((x) & BIT_MASK_P2PPS2_MACID_PAUSE_8814B) \ + << BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B) +#define BITS_P2PPS2_MACID_PAUSE_8814B \ + (BIT_MASK_P2PPS2_MACID_PAUSE_8814B \ + << BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B) +#define BIT_CLEAR_P2PPS2_MACID_PAUSE_8814B(x) \ + ((x) & (~BITS_P2PPS2_MACID_PAUSE_8814B)) +#define BIT_GET_P2PPS2_MACID_PAUSE_8814B(x) \ + (((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B) & \ + BIT_MASK_P2PPS2_MACID_PAUSE_8814B) +#define BIT_SET_P2PPS2_MACID_PAUSE_8814B(x, v) \ + (BIT_CLEAR_P2PPS2_MACID_PAUSE_8814B(x) | \ + BIT_P2PPS2_MACID_PAUSE_8814B(v)) + +/* 2 REG_RX_TBTT_SHIFT_8814B */ + +#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B 24 +#define BIT_MASK_RX_TBTT_SHIFT_SEL_8814B 0x7 +#define BIT_RX_TBTT_SHIFT_SEL_8814B(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_8814B) \ + << BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B) +#define BITS_RX_TBTT_SHIFT_SEL_8814B \ + (BIT_MASK_RX_TBTT_SHIFT_SEL_8814B << BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B) +#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_8814B(x) \ + ((x) & (~BITS_RX_TBTT_SHIFT_SEL_8814B)) +#define BIT_GET_RX_TBTT_SHIFT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B) & \ + BIT_MASK_RX_TBTT_SHIFT_SEL_8814B) +#define BIT_SET_RX_TBTT_SHIFT_SEL_8814B(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_SEL_8814B(x) | BIT_RX_TBTT_SHIFT_SEL_8814B(v)) + +#define BIT_RX_TBTT_SHIFT_RW_FLAG_8814B BIT(15) + +#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B 0 +#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B 0xfff +#define BIT_RX_TBTT_SHIFT_OFFSET_8814B(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B) \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B) +#define BITS_RX_TBTT_SHIFT_OFFSET_8814B \ + (BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B) +#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_8814B(x) \ + ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_8814B)) +#define BIT_GET_RX_TBTT_SHIFT_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B) & \ + BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B) +#define BIT_SET_RX_TBTT_SHIFT_OFFSET_8814B(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_8814B(x) | \ + BIT_RX_TBTT_SHIFT_OFFSET_8814B(v)) -#define BIT_SHIFT_ATIMWND4_8814B 0 -#define BIT_MASK_ATIMWND4_8814B 0xff -#define BIT_ATIMWND4_8814B(x) (((x) & BIT_MASK_ATIMWND4_8814B) << BIT_SHIFT_ATIMWND4_8814B) -#define BIT_GET_ATIMWND4_8814B(x) (((x) >> BIT_SHIFT_ATIMWND4_8814B) & BIT_MASK_ATIMWND4_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_FREERUN_CNT_LOW_8814B */ + +#define BIT_SHIFT_FREERUN_CNT_LOW_8814B 0 +#define BIT_MASK_FREERUN_CNT_LOW_8814B 0xffffffffL +#define BIT_FREERUN_CNT_LOW_8814B(x) \ + (((x) & BIT_MASK_FREERUN_CNT_LOW_8814B) \ + << BIT_SHIFT_FREERUN_CNT_LOW_8814B) +#define BITS_FREERUN_CNT_LOW_8814B \ + (BIT_MASK_FREERUN_CNT_LOW_8814B << BIT_SHIFT_FREERUN_CNT_LOW_8814B) +#define BIT_CLEAR_FREERUN_CNT_LOW_8814B(x) ((x) & (~BITS_FREERUN_CNT_LOW_8814B)) +#define BIT_GET_FREERUN_CNT_LOW_8814B(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_LOW_8814B) & \ + BIT_MASK_FREERUN_CNT_LOW_8814B) +#define BIT_SET_FREERUN_CNT_LOW_8814B(x, v) \ + (BIT_CLEAR_FREERUN_CNT_LOW_8814B(x) | BIT_FREERUN_CNT_LOW_8814B(v)) + +/* 2 REG_FREERUN_CNT_HIGH_8814B */ + +#define BIT_SHIFT_FREERUN_CNT_HIGH_8814B 0 +#define BIT_MASK_FREERUN_CNT_HIGH_8814B 0xffffffffL +#define BIT_FREERUN_CNT_HIGH_8814B(x) \ + (((x) & BIT_MASK_FREERUN_CNT_HIGH_8814B) \ + << BIT_SHIFT_FREERUN_CNT_HIGH_8814B) +#define BITS_FREERUN_CNT_HIGH_8814B \ + (BIT_MASK_FREERUN_CNT_HIGH_8814B << BIT_SHIFT_FREERUN_CNT_HIGH_8814B) +#define BIT_CLEAR_FREERUN_CNT_HIGH_8814B(x) \ + ((x) & (~BITS_FREERUN_CNT_HIGH_8814B)) +#define BIT_GET_FREERUN_CNT_HIGH_8814B(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_HIGH_8814B) & \ + BIT_MASK_FREERUN_CNT_HIGH_8814B) +#define BIT_SET_FREERUN_CNT_HIGH_8814B(x, v) \ + (BIT_CLEAR_FREERUN_CNT_HIGH_8814B(x) | BIT_FREERUN_CNT_HIGH_8814B(v)) + +/* 2 REG_CPUMGQ_TX_TIMER_V1_8814B */ +#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B 0xffffffffL +#define BIT_CPUMGQ_TX_TIMER_V1_8814B(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) +#define BITS_CPUMGQ_TX_TIMER_V1_8814B \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8814B(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8814B)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8814B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) & \ + BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B) +#define BIT_SET_CPUMGQ_TX_TIMER_V1_8814B(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8814B(x) | \ + BIT_CPUMGQ_TX_TIMER_V1_8814B(v)) + +/* 2 REG_PS_TIMER_0_8814B */ + +#define BIT_SHIFT_PS_TIMER_0_8814B 0 +#define BIT_MASK_PS_TIMER_0_8814B 0xffffffffL +#define BIT_PS_TIMER_0_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_0_8814B) << BIT_SHIFT_PS_TIMER_0_8814B) +#define BITS_PS_TIMER_0_8814B \ + (BIT_MASK_PS_TIMER_0_8814B << BIT_SHIFT_PS_TIMER_0_8814B) +#define BIT_CLEAR_PS_TIMER_0_8814B(x) ((x) & (~BITS_PS_TIMER_0_8814B)) +#define BIT_GET_PS_TIMER_0_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0_8814B) & BIT_MASK_PS_TIMER_0_8814B) +#define BIT_SET_PS_TIMER_0_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_0_8814B(x) | BIT_PS_TIMER_0_8814B(v)) + +/* 2 REG_PS_TIMER_1_8814B */ + +#define BIT_SHIFT_PS_TIMER_1_8814B 0 +#define BIT_MASK_PS_TIMER_1_8814B 0xffffffffL +#define BIT_PS_TIMER_1_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_1_8814B) << BIT_SHIFT_PS_TIMER_1_8814B) +#define BITS_PS_TIMER_1_8814B \ + (BIT_MASK_PS_TIMER_1_8814B << BIT_SHIFT_PS_TIMER_1_8814B) +#define BIT_CLEAR_PS_TIMER_1_8814B(x) ((x) & (~BITS_PS_TIMER_1_8814B)) +#define BIT_GET_PS_TIMER_1_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1_8814B) & BIT_MASK_PS_TIMER_1_8814B) +#define BIT_SET_PS_TIMER_1_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_1_8814B(x) | BIT_PS_TIMER_1_8814B(v)) + +/* 2 REG_PS_TIMER_2_8814B */ + +#define BIT_SHIFT_PS_TIMER_2_8814B 0 +#define BIT_MASK_PS_TIMER_2_8814B 0xffffffffL +#define BIT_PS_TIMER_2_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_2_8814B) << BIT_SHIFT_PS_TIMER_2_8814B) +#define BITS_PS_TIMER_2_8814B \ + (BIT_MASK_PS_TIMER_2_8814B << BIT_SHIFT_PS_TIMER_2_8814B) +#define BIT_CLEAR_PS_TIMER_2_8814B(x) ((x) & (~BITS_PS_TIMER_2_8814B)) +#define BIT_GET_PS_TIMER_2_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2_8814B) & BIT_MASK_PS_TIMER_2_8814B) +#define BIT_SET_PS_TIMER_2_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_2_8814B(x) | BIT_PS_TIMER_2_8814B(v)) + +/* 2 REG_PS_TIMER_3_8814B */ + +#define BIT_SHIFT_PS_TIMER_3_8814B 0 +#define BIT_MASK_PS_TIMER_3_8814B 0xffffffffL +#define BIT_PS_TIMER_3_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_3_8814B) << BIT_SHIFT_PS_TIMER_3_8814B) +#define BITS_PS_TIMER_3_8814B \ + (BIT_MASK_PS_TIMER_3_8814B << BIT_SHIFT_PS_TIMER_3_8814B) +#define BIT_CLEAR_PS_TIMER_3_8814B(x) ((x) & (~BITS_PS_TIMER_3_8814B)) +#define BIT_GET_PS_TIMER_3_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3_8814B) & BIT_MASK_PS_TIMER_3_8814B) +#define BIT_SET_PS_TIMER_3_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_3_8814B(x) | BIT_PS_TIMER_3_8814B(v)) + +/* 2 REG_PS_TIMER_4_8814B */ + +#define BIT_SHIFT_PS_TIMER_4_8814B 0 +#define BIT_MASK_PS_TIMER_4_8814B 0xffffffffL +#define BIT_PS_TIMER_4_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_4_8814B) << BIT_SHIFT_PS_TIMER_4_8814B) +#define BITS_PS_TIMER_4_8814B \ + (BIT_MASK_PS_TIMER_4_8814B << BIT_SHIFT_PS_TIMER_4_8814B) +#define BIT_CLEAR_PS_TIMER_4_8814B(x) ((x) & (~BITS_PS_TIMER_4_8814B)) +#define BIT_GET_PS_TIMER_4_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4_8814B) & BIT_MASK_PS_TIMER_4_8814B) +#define BIT_SET_PS_TIMER_4_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_4_8814B(x) | BIT_PS_TIMER_4_8814B(v)) + +/* 2 REG_PS_TIMER_5_8814B */ + +#define BIT_SHIFT_PS_TIMER_5_8814B 0 +#define BIT_MASK_PS_TIMER_5_8814B 0xffffffffL +#define BIT_PS_TIMER_5_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_5_8814B) << BIT_SHIFT_PS_TIMER_5_8814B) +#define BITS_PS_TIMER_5_8814B \ + (BIT_MASK_PS_TIMER_5_8814B << BIT_SHIFT_PS_TIMER_5_8814B) +#define BIT_CLEAR_PS_TIMER_5_8814B(x) ((x) & (~BITS_PS_TIMER_5_8814B)) +#define BIT_GET_PS_TIMER_5_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5_8814B) & BIT_MASK_PS_TIMER_5_8814B) +#define BIT_SET_PS_TIMER_5_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_5_8814B(x) | BIT_PS_TIMER_5_8814B(v)) + +/* 2 REG_PS_TIMER_01_CTRL_8814B */ + +#define BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B 24 +#define BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_1_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B) +#define BITS_PS_TIMER_1_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_1_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_1_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_1_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_1_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_1_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_1_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_1_EN_8814B BIT(23) + +#define BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B 16 +#define BIT_MASK_PS_TIMER_1_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_1_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_1_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B) +#define BITS_PS_TIMER_1_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_1_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_1_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_1_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_1_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_1_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_1_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_1_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_1_TSF_SEL_8814B(v)) + +#define BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B 8 +#define BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_0_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B) +#define BITS_PS_TIMER_0_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_0_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_0_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_0_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_0_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_0_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_0_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_0_EN_8814B BIT(7) + +#define BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B 0 +#define BIT_MASK_PS_TIMER_0_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_0_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_0_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B) +#define BITS_PS_TIMER_0_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_0_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_0_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_0_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_0_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_0_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_0_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_0_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_0_TSF_SEL_8814B(v)) + +/* 2 REG_PS_TIMER_23_CTRL_8814B */ + +#define BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B 24 +#define BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_3_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B) +#define BITS_PS_TIMER_3_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_3_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_3_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_3_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_3_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_3_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_3_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_3_EN_8814B BIT(23) + +#define BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B 16 +#define BIT_MASK_PS_TIMER_3_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_3_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_3_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B) +#define BITS_PS_TIMER_3_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_3_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_3_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_3_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_3_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_3_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_3_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_3_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_3_TSF_SEL_8814B(v)) + +#define BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B 8 +#define BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_2_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B) +#define BITS_PS_TIMER_2_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_2_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_2_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_2_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_2_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_2_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_2_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_2_EN_8814B BIT(7) + +#define BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B 0 +#define BIT_MASK_PS_TIMER_2_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_2_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_2_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B) +#define BITS_PS_TIMER_2_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_2_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_2_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_2_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_2_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_2_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_2_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_2_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_2_TSF_SEL_8814B(v)) + +/* 2 REG_PS_TIMER_45_CTRL_8814B */ + +#define BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B 24 +#define BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_5_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B) +#define BITS_PS_TIMER_5_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_5_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_5_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_5_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_5_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_5_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_5_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_5_EN_8814B BIT(23) + +#define BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B 16 +#define BIT_MASK_PS_TIMER_5_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_5_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_5_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B) +#define BITS_PS_TIMER_5_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_5_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_5_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_5_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_5_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_5_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_5_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_5_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_5_TSF_SEL_8814B(v)) + +#define BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B 8 +#define BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B 0xff +#define BIT_PS_TIMER_4_EARLY_TIME_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B) \ + << BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B) +#define BITS_PS_TIMER_4_EARLY_TIME_8814B \ + (BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B \ + << BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B) +#define BIT_CLEAR_PS_TIMER_4_EARLY_TIME_8814B(x) \ + ((x) & (~BITS_PS_TIMER_4_EARLY_TIME_8814B)) +#define BIT_GET_PS_TIMER_4_EARLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B) & \ + BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B) +#define BIT_SET_PS_TIMER_4_EARLY_TIME_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_4_EARLY_TIME_8814B(x) | \ + BIT_PS_TIMER_4_EARLY_TIME_8814B(v)) + +#define BIT_PS_TIMER_4_EN_8814B BIT(7) + +#define BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B 0 +#define BIT_MASK_PS_TIMER_4_TSF_SEL_8814B 0x7 +#define BIT_PS_TIMER_4_TSF_SEL_8814B(x) \ + (((x) & BIT_MASK_PS_TIMER_4_TSF_SEL_8814B) \ + << BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B) +#define BITS_PS_TIMER_4_TSF_SEL_8814B \ + (BIT_MASK_PS_TIMER_4_TSF_SEL_8814B \ + << BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B) +#define BIT_CLEAR_PS_TIMER_4_TSF_SEL_8814B(x) \ + ((x) & (~BITS_PS_TIMER_4_TSF_SEL_8814B)) +#define BIT_GET_PS_TIMER_4_TSF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B) & \ + BIT_MASK_PS_TIMER_4_TSF_SEL_8814B) +#define BIT_SET_PS_TIMER_4_TSF_SEL_8814B(x, v) \ + (BIT_CLEAR_PS_TIMER_4_TSF_SEL_8814B(x) | \ + BIT_PS_TIMER_4_TSF_SEL_8814B(v)) + +/* 2 REG_CPUMGQ_FREERUN_TIMER_CTRL_8814B */ +#define BIT_FREECNT_RST_V1_8814B BIT(23) +#define BIT_EN_FREECNT_V1_8814B BIT(16) + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B 8 +#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B 0xff +#define BIT_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B) +#define BITS_CPUMGQ_TX_TIMER_EARLY_V1_8814B \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_V1_8814B)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_V1_8814B(v)) + +#define BIT_CPUMGQ_TIMER_EN_V1_8814B BIT(7) +#define BIT_CPUMGQ_DROP_BY_HOLDTIME_8814B BIT(5) +#define BIT_CPUMGQ_TX_EN_V1_8814B BIT(4) + +#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B 0 +#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B 0x7 +#define BIT_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B) +#define BITS_CPUMGQ_TIMER_TSF_SEL_V1_8814B \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_V1_8814B)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) | \ + BIT_CPUMGQ_TIMER_TSF_SEL_V1_8814B(v)) + +/* 2 REG_CPUMGQ_PROHIBIT_8814B */ + +#define BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B 8 +#define BIT_MASK_CPUMGQ_HOLD_TIME_8814B 0xfff +#define BIT_CPUMGQ_HOLD_TIME_8814B(x) \ + (((x) & BIT_MASK_CPUMGQ_HOLD_TIME_8814B) \ + << BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B) +#define BITS_CPUMGQ_HOLD_TIME_8814B \ + (BIT_MASK_CPUMGQ_HOLD_TIME_8814B << BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B) +#define BIT_CLEAR_CPUMGQ_HOLD_TIME_8814B(x) \ + ((x) & (~BITS_CPUMGQ_HOLD_TIME_8814B)) +#define BIT_GET_CPUMGQ_HOLD_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B) & \ + BIT_MASK_CPUMGQ_HOLD_TIME_8814B) +#define BIT_SET_CPUMGQ_HOLD_TIME_8814B(x, v) \ + (BIT_CLEAR_CPUMGQ_HOLD_TIME_8814B(x) | BIT_CPUMGQ_HOLD_TIME_8814B(v)) + +#define BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B 0 +#define BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B 0xf +#define BIT_CPUMGQ_PROHIBIT_SETUP_8814B(x) \ + (((x) & BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B) \ + << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B) +#define BITS_CPUMGQ_PROHIBIT_SETUP_8814B \ + (BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B \ + << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B) +#define BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP_8814B(x) \ + ((x) & (~BITS_CPUMGQ_PROHIBIT_SETUP_8814B)) +#define BIT_GET_CPUMGQ_PROHIBIT_SETUP_8814B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B) & \ + BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B) +#define BIT_SET_CPUMGQ_PROHIBIT_SETUP_8814B(x, v) \ + (BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP_8814B(x) | \ + BIT_CPUMGQ_PROHIBIT_SETUP_8814B(v)) -/* 2 REG_ATIMWND5_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_ATIMWND5_8814B 0 -#define BIT_MASK_ATIMWND5_8814B 0xff -#define BIT_ATIMWND5_8814B(x) (((x) & BIT_MASK_ATIMWND5_8814B) << BIT_SHIFT_ATIMWND5_8814B) -#define BIT_GET_ATIMWND5_8814B(x) (((x) >> BIT_SHIFT_ATIMWND5_8814B) & BIT_MASK_ATIMWND5_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_TIMER_COMPARE_8814B */ +#define BIT_COMP_TRIGGER_8814B BIT(7) + +#define BIT_SHIFT_Y_COMP_8814B 4 +#define BIT_MASK_Y_COMP_8814B 0x7 +#define BIT_Y_COMP_8814B(x) \ + (((x) & BIT_MASK_Y_COMP_8814B) << BIT_SHIFT_Y_COMP_8814B) +#define BITS_Y_COMP_8814B (BIT_MASK_Y_COMP_8814B << BIT_SHIFT_Y_COMP_8814B) +#define BIT_CLEAR_Y_COMP_8814B(x) ((x) & (~BITS_Y_COMP_8814B)) +#define BIT_GET_Y_COMP_8814B(x) \ + (((x) >> BIT_SHIFT_Y_COMP_8814B) & BIT_MASK_Y_COMP_8814B) +#define BIT_SET_Y_COMP_8814B(x, v) \ + (BIT_CLEAR_Y_COMP_8814B(x) | BIT_Y_COMP_8814B(v)) + +#define BIT_X_COMP_Y_OVERFLOW_8814B BIT(3) + +#define BIT_SHIFT_X_COMP_8814B 0 +#define BIT_MASK_X_COMP_8814B 0x7 +#define BIT_X_COMP_8814B(x) \ + (((x) & BIT_MASK_X_COMP_8814B) << BIT_SHIFT_X_COMP_8814B) +#define BITS_X_COMP_8814B (BIT_MASK_X_COMP_8814B << BIT_SHIFT_X_COMP_8814B) +#define BIT_CLEAR_X_COMP_8814B(x) ((x) & (~BITS_X_COMP_8814B)) +#define BIT_GET_X_COMP_8814B(x) \ + (((x) >> BIT_SHIFT_X_COMP_8814B) & BIT_MASK_X_COMP_8814B) +#define BIT_SET_X_COMP_8814B(x, v) \ + (BIT_CLEAR_X_COMP_8814B(x) | BIT_X_COMP_8814B(v)) -/* 2 REG_ATIMWND6_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_ATIMWND6_8814B 0 -#define BIT_MASK_ATIMWND6_8814B 0xff -#define BIT_ATIMWND6_8814B(x) (((x) & BIT_MASK_ATIMWND6_8814B) << BIT_SHIFT_ATIMWND6_8814B) -#define BIT_GET_ATIMWND6_8814B(x) (((x) >> BIT_SHIFT_ATIMWND6_8814B) & BIT_MASK_ATIMWND6_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_TIMER_COMPARE_VALUE_LOW_8814B */ + +#define BIT_SHIFT_COMP_VALUE_LOW_8814B 0 +#define BIT_MASK_COMP_VALUE_LOW_8814B 0xffffffffL +#define BIT_COMP_VALUE_LOW_8814B(x) \ + (((x) & BIT_MASK_COMP_VALUE_LOW_8814B) \ + << BIT_SHIFT_COMP_VALUE_LOW_8814B) +#define BITS_COMP_VALUE_LOW_8814B \ + (BIT_MASK_COMP_VALUE_LOW_8814B << BIT_SHIFT_COMP_VALUE_LOW_8814B) +#define BIT_CLEAR_COMP_VALUE_LOW_8814B(x) ((x) & (~BITS_COMP_VALUE_LOW_8814B)) +#define BIT_GET_COMP_VALUE_LOW_8814B(x) \ + (((x) >> BIT_SHIFT_COMP_VALUE_LOW_8814B) & \ + BIT_MASK_COMP_VALUE_LOW_8814B) +#define BIT_SET_COMP_VALUE_LOW_8814B(x, v) \ + (BIT_CLEAR_COMP_VALUE_LOW_8814B(x) | BIT_COMP_VALUE_LOW_8814B(v)) + +/* 2 REG_TIMER_COMPARE_VALUE_HIGH_8814B */ + +#define BIT_SHIFT_COMP_VALUE_HIGH_8814B 0 +#define BIT_MASK_COMP_VALUE_HIGH_8814B 0xffffffffL +#define BIT_COMP_VALUE_HIGH_8814B(x) \ + (((x) & BIT_MASK_COMP_VALUE_HIGH_8814B) \ + << BIT_SHIFT_COMP_VALUE_HIGH_8814B) +#define BITS_COMP_VALUE_HIGH_8814B \ + (BIT_MASK_COMP_VALUE_HIGH_8814B << BIT_SHIFT_COMP_VALUE_HIGH_8814B) +#define BIT_CLEAR_COMP_VALUE_HIGH_8814B(x) ((x) & (~BITS_COMP_VALUE_HIGH_8814B)) +#define BIT_GET_COMP_VALUE_HIGH_8814B(x) \ + (((x) >> BIT_SHIFT_COMP_VALUE_HIGH_8814B) & \ + BIT_MASK_COMP_VALUE_HIGH_8814B) +#define BIT_SET_COMP_VALUE_HIGH_8814B(x, v) \ + (BIT_CLEAR_COMP_VALUE_HIGH_8814B(x) | BIT_COMP_VALUE_HIGH_8814B(v)) -/* 2 REG_ATIMWND7_8814B */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_ATIMWND7_8814B 0 -#define BIT_MASK_ATIMWND7_8814B 0xff -#define BIT_ATIMWND7_8814B(x) (((x) & BIT_MASK_ATIMWND7_8814B) << BIT_SHIFT_ATIMWND7_8814B) -#define BIT_GET_ATIMWND7_8814B(x) (((x) >> BIT_SHIFT_ATIMWND7_8814B) & BIT_MASK_ATIMWND7_8814B) +/* 2 REG_SCHEDULER_COUNTER_8814B */ + +#define BIT_SHIFT__SCHEDULER_COUNTER_8814B 16 +#define BIT_MASK__SCHEDULER_COUNTER_8814B 0xffff +#define BIT__SCHEDULER_COUNTER_8814B(x) \ + (((x) & BIT_MASK__SCHEDULER_COUNTER_8814B) \ + << BIT_SHIFT__SCHEDULER_COUNTER_8814B) +#define BITS__SCHEDULER_COUNTER_8814B \ + (BIT_MASK__SCHEDULER_COUNTER_8814B \ + << BIT_SHIFT__SCHEDULER_COUNTER_8814B) +#define BIT_CLEAR__SCHEDULER_COUNTER_8814B(x) \ + ((x) & (~BITS__SCHEDULER_COUNTER_8814B)) +#define BIT_GET__SCHEDULER_COUNTER_8814B(x) \ + (((x) >> BIT_SHIFT__SCHEDULER_COUNTER_8814B) & \ + BIT_MASK__SCHEDULER_COUNTER_8814B) +#define BIT_SET__SCHEDULER_COUNTER_8814B(x, v) \ + (BIT_CLEAR__SCHEDULER_COUNTER_8814B(x) | \ + BIT__SCHEDULER_COUNTER_8814B(v)) + +#define BIT__SCHEDULER_COUNTER_RST_8814B BIT(8) + +#define BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B 0 +#define BIT_MASK_SCHEDULER_COUNTER_SEL_8814B 0xff +#define BIT_SCHEDULER_COUNTER_SEL_8814B(x) \ + (((x) & BIT_MASK_SCHEDULER_COUNTER_SEL_8814B) \ + << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B) +#define BITS_SCHEDULER_COUNTER_SEL_8814B \ + (BIT_MASK_SCHEDULER_COUNTER_SEL_8814B \ + << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B) +#define BIT_CLEAR_SCHEDULER_COUNTER_SEL_8814B(x) \ + ((x) & (~BITS_SCHEDULER_COUNTER_SEL_8814B)) +#define BIT_GET_SCHEDULER_COUNTER_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL_8814B) & \ + BIT_MASK_SCHEDULER_COUNTER_SEL_8814B) +#define BIT_SET_SCHEDULER_COUNTER_SEL_8814B(x, v) \ + (BIT_CLEAR_SCHEDULER_COUNTER_SEL_8814B(x) | \ + BIT_SCHEDULER_COUNTER_SEL_8814B(v)) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_ATIMUGT_8814B */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_ATIM_URGENT_8814B 0 -#define BIT_MASK_ATIM_URGENT_8814B 0xff -#define BIT_ATIM_URGENT_8814B(x) (((x) & BIT_MASK_ATIM_URGENT_8814B) << BIT_SHIFT_ATIM_URGENT_8814B) -#define BIT_GET_ATIM_URGENT_8814B(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8814B) & BIT_MASK_ATIM_URGENT_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_HIQ_NO_LMT_EN_8814B */ -#define BIT_HIQ_NO_LMT_EN_VAP7_8814B BIT(7) -#define BIT_HIQ_NO_LMT_EN_VAP6_8814B BIT(6) -#define BIT_HIQ_NO_LMT_EN_VAP5_8814B BIT(5) -#define BIT_HIQ_NO_LMT_EN_VAP4_8814B BIT(4) -#define BIT_HIQ_NO_LMT_EN_VAP3_8814B BIT(3) -#define BIT_HIQ_NO_LMT_EN_VAP2_8814B BIT(2) -#define BIT_HIQ_NO_LMT_EN_VAP1_8814B BIT(1) -#define BIT_HIQ_NO_LMT_EN_ROOT_8814B BIT(0) +/* 2 REG_RSVD_8814B */ -/* 2 REG_DTIM_COUNTER_ROOT_8814B */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_DTIM_COUNT_ROOT_8814B 0 -#define BIT_MASK_DTIM_COUNT_ROOT_8814B 0xff -#define BIT_DTIM_COUNT_ROOT_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8814B) << BIT_SHIFT_DTIM_COUNT_ROOT_8814B) -#define BIT_GET_DTIM_COUNT_ROOT_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8814B) & BIT_MASK_DTIM_COUNT_ROOT_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_DTIM_COUNTER_VAP1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP1_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP1_8814B 0xff -#define BIT_DTIM_COUNT_VAP1_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8814B) << BIT_SHIFT_DTIM_COUNT_VAP1_8814B) -#define BIT_GET_DTIM_COUNT_VAP1_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8814B) & BIT_MASK_DTIM_COUNT_VAP1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP2_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP2_8814B 0xff -#define BIT_DTIM_COUNT_VAP2_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8814B) << BIT_SHIFT_DTIM_COUNT_VAP2_8814B) -#define BIT_GET_DTIM_COUNT_VAP2_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8814B) & BIT_MASK_DTIM_COUNT_VAP2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP3_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP3_8814B 0xff -#define BIT_DTIM_COUNT_VAP3_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8814B) << BIT_SHIFT_DTIM_COUNT_VAP3_8814B) -#define BIT_GET_DTIM_COUNT_VAP3_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8814B) & BIT_MASK_DTIM_COUNT_VAP3_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP4_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP4_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP4_8814B 0xff -#define BIT_DTIM_COUNT_VAP4_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8814B) << BIT_SHIFT_DTIM_COUNT_VAP4_8814B) -#define BIT_GET_DTIM_COUNT_VAP4_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8814B) & BIT_MASK_DTIM_COUNT_VAP4_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP5_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP5_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP5_8814B 0xff -#define BIT_DTIM_COUNT_VAP5_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8814B) << BIT_SHIFT_DTIM_COUNT_VAP5_8814B) -#define BIT_GET_DTIM_COUNT_VAP5_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8814B) & BIT_MASK_DTIM_COUNT_VAP5_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP6_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP6_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP6_8814B 0xff -#define BIT_DTIM_COUNT_VAP6_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8814B) << BIT_SHIFT_DTIM_COUNT_VAP6_8814B) -#define BIT_GET_DTIM_COUNT_VAP6_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8814B) & BIT_MASK_DTIM_COUNT_VAP6_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DTIM_COUNTER_VAP7_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_DTIM_COUNT_VAP7_8814B 0 -#define BIT_MASK_DTIM_COUNT_VAP7_8814B 0xff -#define BIT_DTIM_COUNT_VAP7_8814B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8814B) << BIT_SHIFT_DTIM_COUNT_VAP7_8814B) -#define BIT_GET_DTIM_COUNT_VAP7_8814B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8814B) & BIT_MASK_DTIM_COUNT_VAP7_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_DIS_ATIM_8814B */ -#define BIT_DIS_ATIM_VAP7_8814B BIT(7) -#define BIT_DIS_ATIM_VAP6_8814B BIT(6) -#define BIT_DIS_ATIM_VAP5_8814B BIT(5) -#define BIT_DIS_ATIM_VAP4_8814B BIT(4) -#define BIT_DIS_ATIM_VAP3_8814B BIT(3) -#define BIT_DIS_ATIM_VAP2_8814B BIT(2) -#define BIT_DIS_ATIM_VAP1_8814B BIT(1) -#define BIT_DIS_ATIM_ROOT_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_EARLY_128US_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TSFT_SEL_TIMER1_8814B 3 -#define BIT_MASK_TSFT_SEL_TIMER1_8814B 0x7 -#define BIT_TSFT_SEL_TIMER1_8814B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8814B) << BIT_SHIFT_TSFT_SEL_TIMER1_8814B) -#define BIT_GET_TSFT_SEL_TIMER1_8814B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8814B) & BIT_MASK_TSFT_SEL_TIMER1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_EARLY_128US_8814B 0 -#define BIT_MASK_EARLY_128US_8814B 0x7 -#define BIT_EARLY_128US_8814B(x) (((x) & BIT_MASK_EARLY_128US_8814B) << BIT_SHIFT_EARLY_128US_8814B) -#define BIT_GET_EARLY_128US_8814B(x) (((x) >> BIT_SHIFT_EARLY_128US_8814B) & BIT_MASK_EARLY_128US_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2PPS1_CTRL_8814B */ -#define BIT_P2P1_CTW_ALLSTASLEEP_8814B BIT(7) -#define BIT_P2P1_OFF_DISTX_EN_8814B BIT(6) -#define BIT_P2P1_PWR_MGT_EN_8814B BIT(5) -#define BIT_P2P1_NOA1_EN_8814B BIT(2) -#define BIT_P2P1_NOA0_EN_8814B BIT(1) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2PPS2_CTRL_8814B */ -#define BIT_P2P2_CTW_ALLSTASLEEP_8814B BIT(7) -#define BIT_P2P2_OFF_DISTX_EN_8814B BIT(6) -#define BIT_P2P2_PWR_MGT_EN_8814B BIT(5) -#define BIT_P2P2_NOA1_EN_8814B BIT(2) -#define BIT_P2P2_NOA0_EN_8814B BIT(1) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TIMER0_SRC_SEL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SYNC_CLI_SEL_8814B 4 -#define BIT_MASK_SYNC_CLI_SEL_8814B 0x7 -#define BIT_SYNC_CLI_SEL_8814B(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8814B) << BIT_SHIFT_SYNC_CLI_SEL_8814B) -#define BIT_GET_SYNC_CLI_SEL_8814B(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8814B) & BIT_MASK_SYNC_CLI_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TSFT_SEL_TIMER0_8814B 0 -#define BIT_MASK_TSFT_SEL_TIMER0_8814B 0x7 -#define BIT_TSFT_SEL_TIMER0_8814B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8814B) << BIT_SHIFT_TSFT_SEL_TIMER0_8814B) -#define BIT_GET_TSFT_SEL_TIMER0_8814B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8814B) & BIT_MASK_TSFT_SEL_TIMER0_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOA_UNIT_SEL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_UNIT2_SEL_8814B 8 -#define BIT_MASK_NOA_UNIT2_SEL_8814B 0x7 -#define BIT_NOA_UNIT2_SEL_8814B(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8814B) << BIT_SHIFT_NOA_UNIT2_SEL_8814B) -#define BIT_GET_NOA_UNIT2_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8814B) & BIT_MASK_NOA_UNIT2_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_UNIT1_SEL_8814B 4 -#define BIT_MASK_NOA_UNIT1_SEL_8814B 0x7 -#define BIT_NOA_UNIT1_SEL_8814B(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8814B) << BIT_SHIFT_NOA_UNIT1_SEL_8814B) -#define BIT_GET_NOA_UNIT1_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8814B) & BIT_MASK_NOA_UNIT1_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_UNIT0_SEL_8814B 0 -#define BIT_MASK_NOA_UNIT0_SEL_8814B 0x7 -#define BIT_NOA_UNIT0_SEL_8814B(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8814B) << BIT_SHIFT_NOA_UNIT0_SEL_8814B) -#define BIT_GET_NOA_UNIT0_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8814B) & BIT_MASK_NOA_UNIT0_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2POFF_DIS_TXTIME_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_P2POFF_DIS_TXTIME_8814B 0 -#define BIT_MASK_P2POFF_DIS_TXTIME_8814B 0xff -#define BIT_P2POFF_DIS_TXTIME_8814B(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8814B) << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) -#define BIT_GET_P2POFF_DIS_TXTIME_8814B(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) & BIT_MASK_P2POFF_DIS_TXTIME_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_MBSSID_BCN_SPACE2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_SPACE_CLINT2_8814B 16 -#define BIT_MASK_BCN_SPACE_CLINT2_8814B 0xfff -#define BIT_BCN_SPACE_CLINT2_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8814B) << BIT_SHIFT_BCN_SPACE_CLINT2_8814B) -#define BIT_GET_BCN_SPACE_CLINT2_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8814B) & BIT_MASK_BCN_SPACE_CLINT2_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_SPACE_CLINT1_8814B 0 -#define BIT_MASK_BCN_SPACE_CLINT1_8814B 0xfff -#define BIT_BCN_SPACE_CLINT1_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8814B) << BIT_SHIFT_BCN_SPACE_CLINT1_8814B) -#define BIT_GET_BCN_SPACE_CLINT1_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8814B) & BIT_MASK_BCN_SPACE_CLINT1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_MBSSID_BCN_SPACE3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SUB_BCN_SPACE_8814B 16 -#define BIT_MASK_SUB_BCN_SPACE_8814B 0xff -#define BIT_SUB_BCN_SPACE_8814B(x) (((x) & BIT_MASK_SUB_BCN_SPACE_8814B) << BIT_SHIFT_SUB_BCN_SPACE_8814B) -#define BIT_GET_SUB_BCN_SPACE_8814B(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8814B) & BIT_MASK_SUB_BCN_SPACE_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BCN_SPACE_CLINT3_8814B 0 -#define BIT_MASK_BCN_SPACE_CLINT3_8814B 0xfff -#define BIT_BCN_SPACE_CLINT3_8814B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8814B) << BIT_SHIFT_BCN_SPACE_CLINT3_8814B) -#define BIT_GET_BCN_SPACE_CLINT3_8814B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8814B) & BIT_MASK_BCN_SPACE_CLINT3_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_ACMHWCTRL_8814B */ -#define BIT_BEQ_ACM_STATUS_8814B BIT(7) -#define BIT_VIQ_ACM_STATUS_8814B BIT(6) -#define BIT_VOQ_ACM_STATUS_8814B BIT(5) -#define BIT_BEQ_ACM_EN_8814B BIT(3) -#define BIT_VIQ_ACM_EN_8814B BIT(2) -#define BIT_VOQ_ACM_EN_8814B BIT(1) -#define BIT_ACMHWEN_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_ACMRSTCTRL_8814B */ -#define BIT_BE_ACM_RESET_USED_TIME_8814B BIT(2) -#define BIT_VI_ACM_RESET_USED_TIME_8814B BIT(1) -#define BIT_VO_ACM_RESET_USED_TIME_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_ACMAVG_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_AVGPERIOD_8814B 0 -#define BIT_MASK_AVGPERIOD_8814B 0xffff -#define BIT_AVGPERIOD_8814B(x) (((x) & BIT_MASK_AVGPERIOD_8814B) << BIT_SHIFT_AVGPERIOD_8814B) -#define BIT_GET_AVGPERIOD_8814B(x) (((x) >> BIT_SHIFT_AVGPERIOD_8814B) & BIT_MASK_AVGPERIOD_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_VO_ADMTIME_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_VO_ADMITTED_TIME_8814B 0 -#define BIT_MASK_VO_ADMITTED_TIME_8814B 0xffff -#define BIT_VO_ADMITTED_TIME_8814B(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8814B) << BIT_SHIFT_VO_ADMITTED_TIME_8814B) -#define BIT_GET_VO_ADMITTED_TIME_8814B(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8814B) & BIT_MASK_VO_ADMITTED_TIME_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_VI_ADMTIME_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_VI_ADMITTED_TIME_8814B 0 -#define BIT_MASK_VI_ADMITTED_TIME_8814B 0xffff -#define BIT_VI_ADMITTED_TIME_8814B(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8814B) << BIT_SHIFT_VI_ADMITTED_TIME_8814B) -#define BIT_GET_VI_ADMITTED_TIME_8814B(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8814B) & BIT_MASK_VI_ADMITTED_TIME_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BE_ADMTIME_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_BE_ADMITTED_TIME_8814B 0 -#define BIT_MASK_BE_ADMITTED_TIME_8814B 0xffff -#define BIT_BE_ADMITTED_TIME_8814B(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8814B) << BIT_SHIFT_BE_ADMITTED_TIME_8814B) -#define BIT_GET_BE_ADMITTED_TIME_8814B(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8814B) & BIT_MASK_BE_ADMITTED_TIME_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_EDCA_RANDOM_GEN_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_RANDOM_GEN_8814B 0 -#define BIT_MASK_RANDOM_GEN_8814B 0xffffff -#define BIT_RANDOM_GEN_8814B(x) (((x) & BIT_MASK_RANDOM_GEN_8814B) << BIT_SHIFT_RANDOM_GEN_8814B) -#define BIT_GET_RANDOM_GEN_8814B(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8814B) & BIT_MASK_RANDOM_GEN_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_TXCMD_NOA_SEL_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_SEL_8814B 4 -#define BIT_MASK_NOA_SEL_8814B 0x7 -#define BIT_NOA_SEL_8814B(x) (((x) & BIT_MASK_NOA_SEL_8814B) << BIT_SHIFT_NOA_SEL_8814B) -#define BIT_GET_NOA_SEL_8814B(x) (((x) >> BIT_SHIFT_NOA_SEL_8814B) & BIT_MASK_NOA_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_TXCMD_SEG_SEL_8814B 0 -#define BIT_MASK_TXCMD_SEG_SEL_8814B 0xf -#define BIT_TXCMD_SEG_SEL_8814B(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8814B) << BIT_SHIFT_TXCMD_SEG_SEL_8814B) -#define BIT_GET_TXCMD_SEG_SEL_8814B(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8814B) & BIT_MASK_TXCMD_SEG_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ @@ -8225,53 +20226,41 @@ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOA_PARAM_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_DURATION_V1_8814B 0 -#define BIT_MASK_NOA_DURATION_V1_8814B 0xffffffffL -#define BIT_NOA_DURATION_V1_8814B(x) (((x) & BIT_MASK_NOA_DURATION_V1_8814B) << BIT_SHIFT_NOA_DURATION_V1_8814B) -#define BIT_GET_NOA_DURATION_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_DURATION_V1_8814B) & BIT_MASK_NOA_DURATION_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOA_PARAM_1_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_INTERVAL_V1_8814B 0 -#define BIT_MASK_NOA_INTERVAL_V1_8814B 0xffffffffL -#define BIT_NOA_INTERVAL_V1_8814B(x) (((x) & BIT_MASK_NOA_INTERVAL_V1_8814B) << BIT_SHIFT_NOA_INTERVAL_V1_8814B) -#define BIT_GET_NOA_INTERVAL_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8814B) & BIT_MASK_NOA_INTERVAL_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOA_PARAM_2_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_START_TIME_V1_8814B 0 -#define BIT_MASK_NOA_START_TIME_V1_8814B 0xffffffffL -#define BIT_NOA_START_TIME_V1_8814B(x) (((x) & BIT_MASK_NOA_START_TIME_V1_8814B) << BIT_SHIFT_NOA_START_TIME_V1_8814B) -#define BIT_GET_NOA_START_TIME_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8814B) & BIT_MASK_NOA_START_TIME_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_NOA_PARAM_3_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_NOA_COUNT_V1_8814B 0 -#define BIT_MASK_NOA_COUNT_V1_8814B 0xffffffffL -#define BIT_NOA_COUNT_V1_8814B(x) (((x) & BIT_MASK_NOA_COUNT_V1_8814B) << BIT_SHIFT_NOA_COUNT_V1_8814B) -#define BIT_GET_NOA_COUNT_V1_8814B(x) (((x) >> BIT_SHIFT_NOA_COUNT_V1_8814B) & BIT_MASK_NOA_COUNT_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_P2P_RST_8814B */ -#define BIT_P2P2_PWR_RST1_8814B BIT(5) -#define BIT_P2P2_PWR_RST0_8814B BIT(4) -#define BIT_P2P1_PWR_RST1_8814B BIT(3) -#define BIT_P2P1_PWR_RST0_8814B BIT(2) -#define BIT_P2P_PWR_RST1_V1_8814B BIT(1) -#define BIT_P2P_PWR_RST0_V1_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_SCHEDULER_RST_8814B */ -#define BIT_SYNC_CLI_8814B BIT(1) -#define BIT_SCHEDULER_RST_V1_8814B BIT(0) +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ @@ -8279,123 +20268,105 @@ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_SCH_TXCMD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_SCH_TXCMD_8814B 0 -#define BIT_MASK_SCH_TXCMD_8814B 0xffffffffL -#define BIT_SCH_TXCMD_8814B(x) (((x) & BIT_MASK_SCH_TXCMD_8814B) << BIT_SHIFT_SCH_TXCMD_8814B) -#define BIT_GET_SCH_TXCMD_8814B(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8814B) & BIT_MASK_SCH_TXCMD_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PAGE5_DUMMY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_CPUMGQ_TX_TIMER_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B 0 -#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B 0xffffffffL -#define BIT_CPUMGQ_TX_TIMER_V1_8814B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) -#define BIT_GET_CPUMGQ_TX_TIMER_V1_8814B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_A_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_A_V1_8814B 0 -#define BIT_MASK_PS_TIMER_A_V1_8814B 0xffffffffL -#define BIT_PS_TIMER_A_V1_8814B(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8814B) << BIT_SHIFT_PS_TIMER_A_V1_8814B) -#define BIT_GET_PS_TIMER_A_V1_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8814B) & BIT_MASK_PS_TIMER_A_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_B_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_B_V1_8814B 0 -#define BIT_MASK_PS_TIMER_B_V1_8814B 0xffffffffL -#define BIT_PS_TIMER_B_V1_8814B(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8814B) << BIT_SHIFT_PS_TIMER_B_V1_8814B) -#define BIT_GET_PS_TIMER_B_V1_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8814B) & BIT_MASK_PS_TIMER_B_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_C_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_C_V1_8814B 0 -#define BIT_MASK_PS_TIMER_C_V1_8814B 0xffffffffL -#define BIT_PS_TIMER_C_V1_8814B(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8814B) << BIT_SHIFT_PS_TIMER_C_V1_8814B) -#define BIT_GET_PS_TIMER_C_V1_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8814B) & BIT_MASK_PS_TIMER_C_V1_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8814B */ -#define BIT_CPUMGQ_TIMER_EN_8814B BIT(31) -#define BIT_CPUMGQ_TX_EN_8814B BIT(28) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8814B 24 -#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8814B 0x7 -#define BIT_CPUMGQ_TIMER_TSF_SEL_8814B(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8814B) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8814B) -#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8814B) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_PS_TIMER_C_EN_8814B BIT(23) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8814B 16 -#define BIT_MASK_PS_TIMER_C_TSF_SEL_8814B 0x7 -#define BIT_PS_TIMER_C_TSF_SEL_8814B(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8814B) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8814B) -#define BIT_GET_PS_TIMER_C_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8814B) & BIT_MASK_PS_TIMER_C_TSF_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_PS_TIMER_B_EN_8814B BIT(15) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8814B 8 -#define BIT_MASK_PS_TIMER_B_TSF_SEL_8814B 0x7 -#define BIT_PS_TIMER_B_TSF_SEL_8814B(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8814B) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8814B) -#define BIT_GET_PS_TIMER_B_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8814B) & BIT_MASK_PS_TIMER_B_TSF_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_PS_TIMER_A_EN_8814B BIT(7) +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8814B 0 -#define BIT_MASK_PS_TIMER_A_TSF_SEL_8814B 0x7 -#define BIT_PS_TIMER_A_TSF_SEL_8814B(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8814B) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8814B) -#define BIT_GET_PS_TIMER_A_TSF_SEL_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8814B) & BIT_MASK_PS_TIMER_A_TSF_SEL_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8814B 0 -#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8814B 0xff -#define BIT_CPUMGQ_TX_TIMER_EARLY_8814B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8814B) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8814B) -#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8814B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8814B) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_A_EARLY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_A_EARLY_8814B 0 -#define BIT_MASK_PS_TIMER_A_EARLY_8814B 0xff -#define BIT_PS_TIMER_A_EARLY_8814B(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8814B) << BIT_SHIFT_PS_TIMER_A_EARLY_8814B) -#define BIT_GET_PS_TIMER_A_EARLY_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8814B) & BIT_MASK_PS_TIMER_A_EARLY_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_B_EARLY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_B_EARLY_8814B 0 -#define BIT_MASK_PS_TIMER_B_EARLY_8814B 0xff -#define BIT_PS_TIMER_B_EARLY_8814B(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8814B) << BIT_SHIFT_PS_TIMER_B_EARLY_8814B) -#define BIT_GET_PS_TIMER_B_EARLY_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8814B) & BIT_MASK_PS_TIMER_B_EARLY_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_PS_TIMER_C_EARLY_8814B */ +/* 2 REG_NOT_VALID_8814B */ -#define BIT_SHIFT_PS_TIMER_C_EARLY_8814B 0 -#define BIT_MASK_PS_TIMER_C_EARLY_8814B 0xff -#define BIT_PS_TIMER_C_EARLY_8814B(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8814B) << BIT_SHIFT_PS_TIMER_C_EARLY_8814B) -#define BIT_GET_PS_TIMER_C_EARLY_8814B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8814B) & BIT_MASK_PS_TIMER_C_EARLY_8814B) +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ @@ -8423,120 +20394,128 @@ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ -/* 2 REG_RSVD_8814B */ +/* 2 REG_NOT_VALID_8814B */ /* 2 REG_NOT_VALID_8814B */ -/* 2 REG_BWOPMODE_8814B (BW OPERATION MODE REGISTER) */ +/* 2 REG_WMAC_CR_8814B (WMAC CR AND APSD CONTROL REGISTER) */ +#define BIT_IC_MACPHY_M_8814B BIT(0) /* 2 REG_WMAC_FWPKT_CR_8814B */ #define BIT_FWEN_8814B BIT(7) #define BIT_PHYSTS_PKT_CTRL_8814B BIT(6) +#define BIT_FWFULL_TO_RXFF_EN_8814B BIT(5) #define BIT_APPHDR_MIDSRCH_FAIL_8814B BIT(4) #define BIT_FWPARSING_EN_8814B BIT(3) #define BIT_SHIFT_APPEND_MHDR_LEN_8814B 0 #define BIT_MASK_APPEND_MHDR_LEN_8814B 0x7 -#define BIT_APPEND_MHDR_LEN_8814B(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8814B) << BIT_SHIFT_APPEND_MHDR_LEN_8814B) -#define BIT_GET_APPEND_MHDR_LEN_8814B(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8814B) & BIT_MASK_APPEND_MHDR_LEN_8814B) - - +#define BIT_APPEND_MHDR_LEN_8814B(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN_8814B) \ + << BIT_SHIFT_APPEND_MHDR_LEN_8814B) +#define BITS_APPEND_MHDR_LEN_8814B \ + (BIT_MASK_APPEND_MHDR_LEN_8814B << BIT_SHIFT_APPEND_MHDR_LEN_8814B) +#define BIT_CLEAR_APPEND_MHDR_LEN_8814B(x) ((x) & (~BITS_APPEND_MHDR_LEN_8814B)) +#define BIT_GET_APPEND_MHDR_LEN_8814B(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8814B) & \ + BIT_MASK_APPEND_MHDR_LEN_8814B) +#define BIT_SET_APPEND_MHDR_LEN_8814B(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN_8814B(x) | BIT_APPEND_MHDR_LEN_8814B(v)) /* 2 REG_FW_STS_FILTER_8814B */ #define BIT_DATA_FW_STS_FILTER_8814B BIT(2) #define BIT_CTRL_FW_STS_FILTER_8814B BIT(1) #define BIT_MGNT_FW_STS_FILTER_8814B BIT(0) -/* 2 REG_WMAC_CR_8814B (WMAC CR AND APSD CONTROL REGISTER) */ -#define BIT_IC_MACPHY_M_8814B BIT(0) +/* 2 REG_RSVD_8814B */ /* 2 REG_TCR_8814B (TRANSMISSION CONFIGURATION REGISTER) */ #define BIT_WMAC_EN_RTS_ADDR_8814B BIT(31) @@ -8545,9 +20524,10 @@ #define BIT_WMAC_NOTX_IN_RXNDP_8814B BIT(28) #define BIT_WMAC_EN_EOF_8814B BIT(27) #define BIT_WMAC_BF_SEL_8814B BIT(26) -#define BIT_WMAC_ANTMODE_SEL_8814B BIT(25) -#define BIT_WMAC_TCRPWRMGT_HWCTL_8814B BIT(24) +#define BIT_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(24) #define BIT_WMAC_SMOOTH_VAL_8814B BIT(23) +#define BIT_WMAC_EN_SCRAM_INC_8814B BIT(22) +#define BIT_UNDERFLOWEN_CMPLEN_SEL_8814B BIT(21) #define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8814B BIT(20) #define BIT_WMAC_TCR_EN_20MST_8814B BIT(19) #define BIT_WMAC_DIS_SIGTA_8814B BIT(18) @@ -8559,15 +20539,15 @@ #define BIT_WMAC_TCR_ERRSTEN_0_8814B BIT(12) #define BIT_WMAC_TCR_TXSK_PERPKT_8814B BIT(11) #define BIT_ICV_8814B BIT(10) -#define BIT_CFEND_FORMAT_8814B BIT(9) #define BIT_CRC_8814B BIT(8) -#define BIT_PWRBIT_OW_EN_8814B BIT(7) +#define BIT_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(7) #define BIT_PWR_ST_8814B BIT(6) #define BIT_WMAC_TCR_UPD_TIMIE_8814B BIT(5) #define BIT_WMAC_TCR_UPD_HGQMD_8814B BIT(4) #define BIT_VHTSIGA1_TXPS_8814B BIT(3) #define BIT_PAD_SEL_8814B BIT(2) #define BIT_DIS_GCLK_8814B BIT(1) +#define BIT_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(0) /* 2 REG_RCR_8814B (RECEIVE CONFIGURATION REGISTER) */ #define BIT_APP_FCS_8814B BIT(31) @@ -8577,16 +20557,18 @@ #define BIT_APP_BASSN_8814B BIT(27) #define BIT_VHT_DACK_8814B BIT(26) #define BIT_TCPOFLD_EN_8814B BIT(25) -#define BIT_ENMBID_8814B BIT(24) +#define BIT_ENADDRCAM_8814B BIT(24) #define BIT_LSIGEN_8814B BIT(23) #define BIT_MFBEN_8814B BIT(22) #define BIT_DISCHKPPDLLEN_8814B BIT(21) #define BIT_PKTCTL_DLEN_8814B BIT(20) +#define BIT_DISGCLK_8814B BIT(19) #define BIT_TIM_PARSER_EN_8814B BIT(18) #define BIT_BC_MD_EN_8814B BIT(17) #define BIT_UC_MD_EN_8814B BIT(16) #define BIT_RXSK_PERPKT_8814B BIT(15) #define BIT_HTC_LOC_CTRL_8814B BIT(14) +#define BIT_ACK_WITH_CBSSID_DATA_OPTION_8814B BIT(13) #define BIT_RPFM_CAM_ENABLE_8814B BIT(12) #define BIT_TA_BCN_8814B BIT(11) #define BIT_DISDECMYPKT_8814B BIT(10) @@ -8601,239 +20583,409 @@ #define BIT_APM_8814B BIT(1) #define BIT_AAP_8814B BIT(0) -/* 2 REG_RX_DRVINFO_SZ_8814B (RX DRIVER INFO SIZE REGISTER) */ -#define BIT_PHYSTS_PER_PKT_MODE_8814B BIT(7) - -#define BIT_SHIFT_DRVINFO_SZ_V1_8814B 0 -#define BIT_MASK_DRVINFO_SZ_V1_8814B 0xf -#define BIT_DRVINFO_SZ_V1_8814B(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8814B) << BIT_SHIFT_DRVINFO_SZ_V1_8814B) -#define BIT_GET_DRVINFO_SZ_V1_8814B(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8814B) & BIT_MASK_DRVINFO_SZ_V1_8814B) - - - -/* 2 REG_RX_DLK_TIME_8814B (RX DEADLOCK TIME REGISTER) */ - -#define BIT_SHIFT_RX_DLK_TIME_8814B 0 -#define BIT_MASK_RX_DLK_TIME_8814B 0xff -#define BIT_RX_DLK_TIME_8814B(x) (((x) & BIT_MASK_RX_DLK_TIME_8814B) << BIT_SHIFT_RX_DLK_TIME_8814B) -#define BIT_GET_RX_DLK_TIME_8814B(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8814B) & BIT_MASK_RX_DLK_TIME_8814B) - - - /* 2 REG_RX_PKT_LIMIT_8814B (RX PACKET LENGTH LIMIT REGISTER) */ #define BIT_SHIFT_RXPKTLMT_8814B 0 #define BIT_MASK_RXPKTLMT_8814B 0x3f -#define BIT_RXPKTLMT_8814B(x) (((x) & BIT_MASK_RXPKTLMT_8814B) << BIT_SHIFT_RXPKTLMT_8814B) -#define BIT_GET_RXPKTLMT_8814B(x) (((x) >> BIT_SHIFT_RXPKTLMT_8814B) & BIT_MASK_RXPKTLMT_8814B) - +#define BIT_RXPKTLMT_8814B(x) \ + (((x) & BIT_MASK_RXPKTLMT_8814B) << BIT_SHIFT_RXPKTLMT_8814B) +#define BITS_RXPKTLMT_8814B \ + (BIT_MASK_RXPKTLMT_8814B << BIT_SHIFT_RXPKTLMT_8814B) +#define BIT_CLEAR_RXPKTLMT_8814B(x) ((x) & (~BITS_RXPKTLMT_8814B)) +#define BIT_GET_RXPKTLMT_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKTLMT_8814B) & BIT_MASK_RXPKTLMT_8814B) +#define BIT_SET_RXPKTLMT_8814B(x, v) \ + (BIT_CLEAR_RXPKTLMT_8814B(x) | BIT_RXPKTLMT_8814B(v)) +/* 2 REG_RX_DLK_TIME_8814B (RX DEADLOCK TIME REGISTER) */ -/* 2 REG_MACID_8814B (MAC ID REGISTER) */ +#define BIT_SHIFT_RX_DLK_TIME_8814B 0 +#define BIT_MASK_RX_DLK_TIME_8814B 0xff +#define BIT_RX_DLK_TIME_8814B(x) \ + (((x) & BIT_MASK_RX_DLK_TIME_8814B) << BIT_SHIFT_RX_DLK_TIME_8814B) +#define BITS_RX_DLK_TIME_8814B \ + (BIT_MASK_RX_DLK_TIME_8814B << BIT_SHIFT_RX_DLK_TIME_8814B) +#define BIT_CLEAR_RX_DLK_TIME_8814B(x) ((x) & (~BITS_RX_DLK_TIME_8814B)) +#define BIT_GET_RX_DLK_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME_8814B) & BIT_MASK_RX_DLK_TIME_8814B) +#define BIT_SET_RX_DLK_TIME_8814B(x, v) \ + (BIT_CLEAR_RX_DLK_TIME_8814B(x) | BIT_RX_DLK_TIME_8814B(v)) -#define BIT_SHIFT_MACID_8814B 0 -#define BIT_MASK_MACID_8814B 0xffffffffffffL -#define BIT_MACID_8814B(x) (((x) & BIT_MASK_MACID_8814B) << BIT_SHIFT_MACID_8814B) -#define BIT_GET_MACID_8814B(x) (((x) >> BIT_SHIFT_MACID_8814B) & BIT_MASK_MACID_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RX_DRVINFO_SZ_8814B (RX DRIVER INFO SIZE REGISTER) */ +#define BIT_PHYSTS_PER_PKT_MODE_8814B BIT(7) +#define BIT_SHIFT_DRVINFO_SZ_V1_8814B 0 +#define BIT_MASK_DRVINFO_SZ_V1_8814B 0xf +#define BIT_DRVINFO_SZ_V1_8814B(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1_8814B) << BIT_SHIFT_DRVINFO_SZ_V1_8814B) +#define BITS_DRVINFO_SZ_V1_8814B \ + (BIT_MASK_DRVINFO_SZ_V1_8814B << BIT_SHIFT_DRVINFO_SZ_V1_8814B) +#define BIT_CLEAR_DRVINFO_SZ_V1_8814B(x) ((x) & (~BITS_DRVINFO_SZ_V1_8814B)) +#define BIT_GET_DRVINFO_SZ_V1_8814B(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8814B) & BIT_MASK_DRVINFO_SZ_V1_8814B) +#define BIT_SET_DRVINFO_SZ_V1_8814B(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1_8814B(x) | BIT_DRVINFO_SZ_V1_8814B(v)) + +/* 2 REG_MACID_8814B (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_V1_8814B 0 +#define BIT_MASK_MACID_V1_8814B 0xffffffffL +#define BIT_MACID_V1_8814B(x) \ + (((x) & BIT_MASK_MACID_V1_8814B) << BIT_SHIFT_MACID_V1_8814B) +#define BITS_MACID_V1_8814B \ + (BIT_MASK_MACID_V1_8814B << BIT_SHIFT_MACID_V1_8814B) +#define BIT_CLEAR_MACID_V1_8814B(x) ((x) & (~BITS_MACID_V1_8814B)) +#define BIT_GET_MACID_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_V1_8814B) & BIT_MASK_MACID_V1_8814B) +#define BIT_SET_MACID_V1_8814B(x, v) \ + (BIT_CLEAR_MACID_V1_8814B(x) | BIT_MACID_V1_8814B(v)) + +/* 2 REG_MACID_H_8814B (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_H_V1_8814B 0 +#define BIT_MASK_MACID_H_V1_8814B 0xffff +#define BIT_MACID_H_V1_8814B(x) \ + (((x) & BIT_MASK_MACID_H_V1_8814B) << BIT_SHIFT_MACID_H_V1_8814B) +#define BITS_MACID_H_V1_8814B \ + (BIT_MASK_MACID_H_V1_8814B << BIT_SHIFT_MACID_H_V1_8814B) +#define BIT_CLEAR_MACID_H_V1_8814B(x) ((x) & (~BITS_MACID_H_V1_8814B)) +#define BIT_GET_MACID_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID_H_V1_8814B) & BIT_MASK_MACID_H_V1_8814B) +#define BIT_SET_MACID_H_V1_8814B(x, v) \ + (BIT_CLEAR_MACID_H_V1_8814B(x) | BIT_MACID_H_V1_8814B(v)) /* 2 REG_BSSID_8814B (BSSID REGISTER) */ -#define BIT_SHIFT_BSSID_8814B 0 -#define BIT_MASK_BSSID_8814B 0xffffffffffffL -#define BIT_BSSID_8814B(x) (((x) & BIT_MASK_BSSID_8814B) << BIT_SHIFT_BSSID_8814B) -#define BIT_GET_BSSID_8814B(x) (((x) >> BIT_SHIFT_BSSID_8814B) & BIT_MASK_BSSID_8814B) - - - -/* 2 REG_MAR_8814B (MULTICAST ADDRESS REGISTER) */ - -#define BIT_SHIFT_MAR_8814B 0 -#define BIT_MASK_MAR_8814B 0xffffffffffffffffL -#define BIT_MAR_8814B(x) (((x) & BIT_MASK_MAR_8814B) << BIT_SHIFT_MAR_8814B) -#define BIT_GET_MAR_8814B(x) (((x) >> BIT_SHIFT_MAR_8814B) & BIT_MASK_MAR_8814B) - - - -/* 2 REG_MBIDCAMCFG_1_8814B (MBSSID CAM CONFIGURATION REGISTER) */ - -#define BIT_SHIFT_MBIDCAM_RWDATA_L_8814B 0 -#define BIT_MASK_MBIDCAM_RWDATA_L_8814B 0xffffffffL -#define BIT_MBIDCAM_RWDATA_L_8814B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8814B) << BIT_SHIFT_MBIDCAM_RWDATA_L_8814B) -#define BIT_GET_MBIDCAM_RWDATA_L_8814B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8814B) & BIT_MASK_MBIDCAM_RWDATA_L_8814B) - - +#define BIT_SHIFT_BSSID_V1_8814B 0 +#define BIT_MASK_BSSID_V1_8814B 0xffffffffL +#define BIT_BSSID_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID_V1_8814B) << BIT_SHIFT_BSSID_V1_8814B) +#define BITS_BSSID_V1_8814B \ + (BIT_MASK_BSSID_V1_8814B << BIT_SHIFT_BSSID_V1_8814B) +#define BIT_CLEAR_BSSID_V1_8814B(x) ((x) & (~BITS_BSSID_V1_8814B)) +#define BIT_GET_BSSID_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID_V1_8814B) & BIT_MASK_BSSID_V1_8814B) +#define BIT_SET_BSSID_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID_V1_8814B(x) | BIT_BSSID_V1_8814B(v)) -/* 2 REG_MBIDCAMCFG_2_8814B (MBSSID CAM CONFIGURATION REGISTER) */ -#define BIT_MBIDCAM_POLL_8814B BIT(31) -#define BIT_MBIDCAM_WT_EN_8814B BIT(30) - -#define BIT_SHIFT_MBIDCAM_ADDR_8814B 24 -#define BIT_MASK_MBIDCAM_ADDR_8814B 0x1f -#define BIT_MBIDCAM_ADDR_8814B(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8814B) << BIT_SHIFT_MBIDCAM_ADDR_8814B) -#define BIT_GET_MBIDCAM_ADDR_8814B(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8814B) & BIT_MASK_MBIDCAM_ADDR_8814B) - - -#define BIT_MBIDCAM_VALID_8814B BIT(23) -#define BIT_LSIC_TXOP_EN_8814B BIT(17) -#define BIT_CTS_EN_8814B BIT(16) - -#define BIT_SHIFT_MBIDCAM_RWDATA_H_8814B 0 -#define BIT_MASK_MBIDCAM_RWDATA_H_8814B 0xffff -#define BIT_MBIDCAM_RWDATA_H_8814B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8814B) << BIT_SHIFT_MBIDCAM_RWDATA_H_8814B) -#define BIT_GET_MBIDCAM_RWDATA_H_8814B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8814B) & BIT_MASK_MBIDCAM_RWDATA_H_8814B) - - - -/* 2 REG_ZLD_NUM_8814B */ - -#define BIT_SHIFT_ZLD_NUM_8814B 0 -#define BIT_MASK_ZLD_NUM_8814B 0xff -#define BIT_ZLD_NUM_8814B(x) (((x) & BIT_MASK_ZLD_NUM_8814B) << BIT_SHIFT_ZLD_NUM_8814B) -#define BIT_GET_ZLD_NUM_8814B(x) (((x) >> BIT_SHIFT_ZLD_NUM_8814B) & BIT_MASK_ZLD_NUM_8814B) +/* 2 REG_BSSID_H_8814B (BSSID REGISTER) */ +/* 2 REG_NOT_VALID_8814B */ +#define BIT_SHIFT_BSSID_H_V1_8814B 0 +#define BIT_MASK_BSSID_H_V1_8814B 0xffff +#define BIT_BSSID_H_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID_H_V1_8814B) << BIT_SHIFT_BSSID_H_V1_8814B) +#define BITS_BSSID_H_V1_8814B \ + (BIT_MASK_BSSID_H_V1_8814B << BIT_SHIFT_BSSID_H_V1_8814B) +#define BIT_CLEAR_BSSID_H_V1_8814B(x) ((x) & (~BITS_BSSID_H_V1_8814B)) +#define BIT_GET_BSSID_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID_H_V1_8814B) & BIT_MASK_BSSID_H_V1_8814B) +#define BIT_SET_BSSID_H_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID_H_V1_8814B(x) | BIT_BSSID_H_V1_8814B(v)) -/* 2 REG_UDF_THSD_8814B */ +/* 2 REG_MAR_8814B (MULTICAST ADDRESS REGISTER) */ -#define BIT_SHIFT_UDF_THSD_8814B 0 -#define BIT_MASK_UDF_THSD_8814B 0xff -#define BIT_UDF_THSD_8814B(x) (((x) & BIT_MASK_UDF_THSD_8814B) << BIT_SHIFT_UDF_THSD_8814B) -#define BIT_GET_UDF_THSD_8814B(x) (((x) >> BIT_SHIFT_UDF_THSD_8814B) & BIT_MASK_UDF_THSD_8814B) +#define BIT_SHIFT_MAR_V1_8814B 0 +#define BIT_MASK_MAR_V1_8814B 0xffffffffL +#define BIT_MAR_V1_8814B(x) \ + (((x) & BIT_MASK_MAR_V1_8814B) << BIT_SHIFT_MAR_V1_8814B) +#define BITS_MAR_V1_8814B (BIT_MASK_MAR_V1_8814B << BIT_SHIFT_MAR_V1_8814B) +#define BIT_CLEAR_MAR_V1_8814B(x) ((x) & (~BITS_MAR_V1_8814B)) +#define BIT_GET_MAR_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MAR_V1_8814B) & BIT_MASK_MAR_V1_8814B) +#define BIT_SET_MAR_V1_8814B(x, v) \ + (BIT_CLEAR_MAR_V1_8814B(x) | BIT_MAR_V1_8814B(v)) + +/* 2 REG_MAR_H_8814B (MULTICAST ADDRESS REGISTER) */ + +#define BIT_SHIFT_MAR_H_V1_8814B 0 +#define BIT_MASK_MAR_H_V1_8814B 0xffffffffL +#define BIT_MAR_H_V1_8814B(x) \ + (((x) & BIT_MASK_MAR_H_V1_8814B) << BIT_SHIFT_MAR_H_V1_8814B) +#define BITS_MAR_H_V1_8814B \ + (BIT_MASK_MAR_H_V1_8814B << BIT_SHIFT_MAR_H_V1_8814B) +#define BIT_CLEAR_MAR_H_V1_8814B(x) ((x) & (~BITS_MAR_H_V1_8814B)) +#define BIT_GET_MAR_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MAR_H_V1_8814B) & BIT_MASK_MAR_H_V1_8814B) +#define BIT_SET_MAR_H_V1_8814B(x, v) \ + (BIT_CLEAR_MAR_H_V1_8814B(x) | BIT_MAR_H_V1_8814B(v)) +/* 2 REG_RSVD_8814B */ +/* 2 REG_WMAC_DEBUG_SEL_8814B */ + +#define BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B 3 +#define BIT_MASK_WMAC_ARB_DBG_SEL_8814B 0x3 +#define BIT_WMAC_ARB_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_ARB_DBG_SEL_8814B) \ + << BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B) +#define BITS_WMAC_ARB_DBG_SEL_8814B \ + (BIT_MASK_WMAC_ARB_DBG_SEL_8814B << BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B) +#define BIT_CLEAR_WMAC_ARB_DBG_SEL_8814B(x) \ + ((x) & (~BITS_WMAC_ARB_DBG_SEL_8814B)) +#define BIT_GET_WMAC_ARB_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B) & \ + BIT_MASK_WMAC_ARB_DBG_SEL_8814B) +#define BIT_SET_WMAC_ARB_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_ARB_DBG_SEL_8814B(x) | BIT_WMAC_ARB_DBG_SEL_8814B(v)) + +#define BIT_WMAC_EXT_DBG_SEL_8814B BIT(2) + +#define BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B 0 +#define BIT_MASK_WMAC_MU_DBGSEL_V1_8814B 0x3 +#define BIT_WMAC_MU_DBGSEL_V1_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL_V1_8814B) \ + << BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B) +#define BITS_WMAC_MU_DBGSEL_V1_8814B \ + (BIT_MASK_WMAC_MU_DBGSEL_V1_8814B << BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B) +#define BIT_CLEAR_WMAC_MU_DBGSEL_V1_8814B(x) \ + ((x) & (~BITS_WMAC_MU_DBGSEL_V1_8814B)) +#define BIT_GET_WMAC_MU_DBGSEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B) & \ + BIT_MASK_WMAC_MU_DBGSEL_V1_8814B) +#define BIT_SET_WMAC_MU_DBGSEL_V1_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL_V1_8814B(x) | BIT_WMAC_MU_DBGSEL_V1_8814B(v)) /* 2 REG_WMAC_TCR_TSFT_OFS_8814B */ #define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B 0 #define BIT_MASK_WMAC_TCR_TSFT_OFS_8814B 0xffff -#define BIT_WMAC_TCR_TSFT_OFS_8814B(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8814B) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) -#define BIT_GET_WMAC_TCR_TSFT_OFS_8814B(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) & BIT_MASK_WMAC_TCR_TSFT_OFS_8814B) - +#define BIT_WMAC_TCR_TSFT_OFS_8814B(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8814B) \ + << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) +#define BITS_WMAC_TCR_TSFT_OFS_8814B \ + (BIT_MASK_WMAC_TCR_TSFT_OFS_8814B << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8814B(x) \ + ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8814B)) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) & \ + BIT_MASK_WMAC_TCR_TSFT_OFS_8814B) +#define BIT_SET_WMAC_TCR_TSFT_OFS_8814B(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8814B(x) | BIT_WMAC_TCR_TSFT_OFS_8814B(v)) +/* 2 REG_UDF_THSD_8814B */ +#define BIT_UDF_THSD_V1_8814B BIT(7) + +#define BIT_SHIFT_UDF_THSD_VALUE_8814B 0 +#define BIT_MASK_UDF_THSD_VALUE_8814B 0x7f +#define BIT_UDF_THSD_VALUE_8814B(x) \ + (((x) & BIT_MASK_UDF_THSD_VALUE_8814B) \ + << BIT_SHIFT_UDF_THSD_VALUE_8814B) +#define BITS_UDF_THSD_VALUE_8814B \ + (BIT_MASK_UDF_THSD_VALUE_8814B << BIT_SHIFT_UDF_THSD_VALUE_8814B) +#define BIT_CLEAR_UDF_THSD_VALUE_8814B(x) ((x) & (~BITS_UDF_THSD_VALUE_8814B)) +#define BIT_GET_UDF_THSD_VALUE_8814B(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_VALUE_8814B) & \ + BIT_MASK_UDF_THSD_VALUE_8814B) +#define BIT_SET_UDF_THSD_VALUE_8814B(x, v) \ + (BIT_CLEAR_UDF_THSD_VALUE_8814B(x) | BIT_UDF_THSD_VALUE_8814B(v)) -/* 2 REG_MCU_TEST_2_V1_8814B */ +/* 2 REG_ZLD_NUM_8814B */ -#define BIT_SHIFT_MCU_RSVD_2_V1_8814B 0 -#define BIT_MASK_MCU_RSVD_2_V1_8814B 0xffff -#define BIT_MCU_RSVD_2_V1_8814B(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8814B) << BIT_SHIFT_MCU_RSVD_2_V1_8814B) -#define BIT_GET_MCU_RSVD_2_V1_8814B(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8814B) & BIT_MASK_MCU_RSVD_2_V1_8814B) +#define BIT_SHIFT_ZLD_NUM_8814B 0 +#define BIT_MASK_ZLD_NUM_8814B 0xff +#define BIT_ZLD_NUM_8814B(x) \ + (((x) & BIT_MASK_ZLD_NUM_8814B) << BIT_SHIFT_ZLD_NUM_8814B) +#define BITS_ZLD_NUM_8814B (BIT_MASK_ZLD_NUM_8814B << BIT_SHIFT_ZLD_NUM_8814B) +#define BIT_CLEAR_ZLD_NUM_8814B(x) ((x) & (~BITS_ZLD_NUM_8814B)) +#define BIT_GET_ZLD_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_ZLD_NUM_8814B) & BIT_MASK_ZLD_NUM_8814B) +#define BIT_SET_ZLD_NUM_8814B(x, v) \ + (BIT_CLEAR_ZLD_NUM_8814B(x) | BIT_ZLD_NUM_8814B(v)) +/* 2 REG_STMP_THSD_8814B */ +#define BIT_SHIFT_STMP_THSD_8814B 0 +#define BIT_MASK_STMP_THSD_8814B 0xff +#define BIT_STMP_THSD_8814B(x) \ + (((x) & BIT_MASK_STMP_THSD_8814B) << BIT_SHIFT_STMP_THSD_8814B) +#define BITS_STMP_THSD_8814B \ + (BIT_MASK_STMP_THSD_8814B << BIT_SHIFT_STMP_THSD_8814B) +#define BIT_CLEAR_STMP_THSD_8814B(x) ((x) & (~BITS_STMP_THSD_8814B)) +#define BIT_GET_STMP_THSD_8814B(x) \ + (((x) >> BIT_SHIFT_STMP_THSD_8814B) & BIT_MASK_STMP_THSD_8814B) +#define BIT_SET_STMP_THSD_8814B(x, v) \ + (BIT_CLEAR_STMP_THSD_8814B(x) | BIT_STMP_THSD_8814B(v)) /* 2 REG_WMAC_TXTIMEOUT_8814B */ #define BIT_SHIFT_WMAC_TXTIMEOUT_8814B 0 #define BIT_MASK_WMAC_TXTIMEOUT_8814B 0xff -#define BIT_WMAC_TXTIMEOUT_8814B(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8814B) << BIT_SHIFT_WMAC_TXTIMEOUT_8814B) -#define BIT_GET_WMAC_TXTIMEOUT_8814B(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8814B) & BIT_MASK_WMAC_TXTIMEOUT_8814B) +#define BIT_WMAC_TXTIMEOUT_8814B(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT_8814B) \ + << BIT_SHIFT_WMAC_TXTIMEOUT_8814B) +#define BITS_WMAC_TXTIMEOUT_8814B \ + (BIT_MASK_WMAC_TXTIMEOUT_8814B << BIT_SHIFT_WMAC_TXTIMEOUT_8814B) +#define BIT_CLEAR_WMAC_TXTIMEOUT_8814B(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8814B)) +#define BIT_GET_WMAC_TXTIMEOUT_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8814B) & \ + BIT_MASK_WMAC_TXTIMEOUT_8814B) +#define BIT_SET_WMAC_TXTIMEOUT_8814B(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT_8814B(x) | BIT_WMAC_TXTIMEOUT_8814B(v)) +/* 2 REG_MCU_TEST_2_V1_8814B */ +#define BIT_SHIFT_MCU_RSVD_2_V1_8814B 0 +#define BIT_MASK_MCU_RSVD_2_V1_8814B 0xffff +#define BIT_MCU_RSVD_2_V1_8814B(x) \ + (((x) & BIT_MASK_MCU_RSVD_2_V1_8814B) << BIT_SHIFT_MCU_RSVD_2_V1_8814B) +#define BITS_MCU_RSVD_2_V1_8814B \ + (BIT_MASK_MCU_RSVD_2_V1_8814B << BIT_SHIFT_MCU_RSVD_2_V1_8814B) +#define BIT_CLEAR_MCU_RSVD_2_V1_8814B(x) ((x) & (~BITS_MCU_RSVD_2_V1_8814B)) +#define BIT_GET_MCU_RSVD_2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8814B) & BIT_MASK_MCU_RSVD_2_V1_8814B) +#define BIT_SET_MCU_RSVD_2_V1_8814B(x, v) \ + (BIT_CLEAR_MCU_RSVD_2_V1_8814B(x) | BIT_MCU_RSVD_2_V1_8814B(v)) -/* 2 REG_STMP_THSD_8814B */ +/* 2 REG_USTIME_EDCA_8814B (US TIME TUNING FOR EDCA REGISTER) */ -#define BIT_SHIFT_STMP_THSD_8814B 0 -#define BIT_MASK_STMP_THSD_8814B 0xff -#define BIT_STMP_THSD_8814B(x) (((x) & BIT_MASK_STMP_THSD_8814B) << BIT_SHIFT_STMP_THSD_8814B) -#define BIT_GET_STMP_THSD_8814B(x) (((x) >> BIT_SHIFT_STMP_THSD_8814B) & BIT_MASK_STMP_THSD_8814B) +#define BIT_SHIFT_USTIME_EDCA_8814B 0 +#define BIT_MASK_USTIME_EDCA_8814B 0xff +#define BIT_USTIME_EDCA_8814B(x) \ + (((x) & BIT_MASK_USTIME_EDCA_8814B) << BIT_SHIFT_USTIME_EDCA_8814B) +#define BITS_USTIME_EDCA_8814B \ + (BIT_MASK_USTIME_EDCA_8814B << BIT_SHIFT_USTIME_EDCA_8814B) +#define BIT_CLEAR_USTIME_EDCA_8814B(x) ((x) & (~BITS_USTIME_EDCA_8814B)) +#define BIT_GET_USTIME_EDCA_8814B(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_8814B) & BIT_MASK_USTIME_EDCA_8814B) +#define BIT_SET_USTIME_EDCA_8814B(x, v) \ + (BIT_CLEAR_USTIME_EDCA_8814B(x) | BIT_USTIME_EDCA_8814B(v)) +/* 2 REG_ACKTO_CCK_8814B (ACK TIMEOUT REGISTER FOR CCK RATE) */ +#define BIT_SHIFT_ACKTO_CCK_8814B 0 +#define BIT_MASK_ACKTO_CCK_8814B 0xff +#define BIT_ACKTO_CCK_8814B(x) \ + (((x) & BIT_MASK_ACKTO_CCK_8814B) << BIT_SHIFT_ACKTO_CCK_8814B) +#define BITS_ACKTO_CCK_8814B \ + (BIT_MASK_ACKTO_CCK_8814B << BIT_SHIFT_ACKTO_CCK_8814B) +#define BIT_CLEAR_ACKTO_CCK_8814B(x) ((x) & (~BITS_ACKTO_CCK_8814B)) +#define BIT_GET_ACKTO_CCK_8814B(x) \ + (((x) >> BIT_SHIFT_ACKTO_CCK_8814B) & BIT_MASK_ACKTO_CCK_8814B) +#define BIT_SET_ACKTO_CCK_8814B(x, v) \ + (BIT_CLEAR_ACKTO_CCK_8814B(x) | BIT_ACKTO_CCK_8814B(v)) /* 2 REG_MAC_SPEC_SIFS_8814B (SPECIFICATION SIFS REGISTER) */ #define BIT_SHIFT_SPEC_SIFS_OFDM_8814B 8 #define BIT_MASK_SPEC_SIFS_OFDM_8814B 0xff -#define BIT_SPEC_SIFS_OFDM_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8814B) << BIT_SHIFT_SPEC_SIFS_OFDM_8814B) -#define BIT_GET_SPEC_SIFS_OFDM_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8814B) & BIT_MASK_SPEC_SIFS_OFDM_8814B) - - +#define BIT_SPEC_SIFS_OFDM_8814B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_8814B) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_8814B) +#define BITS_SPEC_SIFS_OFDM_8814B \ + (BIT_MASK_SPEC_SIFS_OFDM_8814B << BIT_SHIFT_SPEC_SIFS_OFDM_8814B) +#define BIT_CLEAR_SPEC_SIFS_OFDM_8814B(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8814B)) +#define BIT_GET_SPEC_SIFS_OFDM_8814B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8814B) & \ + BIT_MASK_SPEC_SIFS_OFDM_8814B) +#define BIT_SET_SPEC_SIFS_OFDM_8814B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_8814B(x) | BIT_SPEC_SIFS_OFDM_8814B(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_8814B 0 #define BIT_MASK_SPEC_SIFS_CCK_8814B 0xff -#define BIT_SPEC_SIFS_CCK_8814B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8814B) << BIT_SHIFT_SPEC_SIFS_CCK_8814B) -#define BIT_GET_SPEC_SIFS_CCK_8814B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8814B) & BIT_MASK_SPEC_SIFS_CCK_8814B) - - - -/* 2 REG_ACKTO_CCK_8814B (ACK TIMEOUT REGISTER FOR CCK RATE) */ - -#define BIT_SHIFT_ACKTO_CCK_8814B 0 -#define BIT_MASK_ACKTO_CCK_8814B 0xff -#define BIT_ACKTO_CCK_8814B(x) (((x) & BIT_MASK_ACKTO_CCK_8814B) << BIT_SHIFT_ACKTO_CCK_8814B) -#define BIT_GET_ACKTO_CCK_8814B(x) (((x) >> BIT_SHIFT_ACKTO_CCK_8814B) & BIT_MASK_ACKTO_CCK_8814B) - - - -/* 2 REG_USTIME_EDCA_8814B (US TIME TUNING FOR EDCA REGISTER) */ +#define BIT_SPEC_SIFS_CCK_8814B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_8814B) << BIT_SHIFT_SPEC_SIFS_CCK_8814B) +#define BITS_SPEC_SIFS_CCK_8814B \ + (BIT_MASK_SPEC_SIFS_CCK_8814B << BIT_SHIFT_SPEC_SIFS_CCK_8814B) +#define BIT_CLEAR_SPEC_SIFS_CCK_8814B(x) ((x) & (~BITS_SPEC_SIFS_CCK_8814B)) +#define BIT_GET_SPEC_SIFS_CCK_8814B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8814B) & BIT_MASK_SPEC_SIFS_CCK_8814B) +#define BIT_SET_SPEC_SIFS_CCK_8814B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_8814B(x) | BIT_SPEC_SIFS_CCK_8814B(v)) -#define BIT_SHIFT_USTIME_EDCA_V1_8814B 0 -#define BIT_MASK_USTIME_EDCA_V1_8814B 0x1ff -#define BIT_USTIME_EDCA_V1_8814B(x) (((x) & BIT_MASK_USTIME_EDCA_V1_8814B) << BIT_SHIFT_USTIME_EDCA_V1_8814B) -#define BIT_GET_USTIME_EDCA_V1_8814B(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8814B) & BIT_MASK_USTIME_EDCA_V1_8814B) +/* 2 REG_RESP_SIFS_CCK_8814B (RESPONSE SIFS FOR CCK REGISTER) */ +#define BIT_SHIFT_SIFS_R2T_CCK_8814B 8 +#define BIT_MASK_SIFS_R2T_CCK_8814B 0xff +#define BIT_SIFS_R2T_CCK_8814B(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK_8814B) << BIT_SHIFT_SIFS_R2T_CCK_8814B) +#define BITS_SIFS_R2T_CCK_8814B \ + (BIT_MASK_SIFS_R2T_CCK_8814B << BIT_SHIFT_SIFS_R2T_CCK_8814B) +#define BIT_CLEAR_SIFS_R2T_CCK_8814B(x) ((x) & (~BITS_SIFS_R2T_CCK_8814B)) +#define BIT_GET_SIFS_R2T_CCK_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8814B) & BIT_MASK_SIFS_R2T_CCK_8814B) +#define BIT_SET_SIFS_R2T_CCK_8814B(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK_8814B(x) | BIT_SIFS_R2T_CCK_8814B(v)) +#define BIT_SHIFT_SIFS_T2T_CCK_8814B 0 +#define BIT_MASK_SIFS_T2T_CCK_8814B 0xff +#define BIT_SIFS_T2T_CCK_8814B(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK_8814B) << BIT_SHIFT_SIFS_T2T_CCK_8814B) +#define BITS_SIFS_T2T_CCK_8814B \ + (BIT_MASK_SIFS_T2T_CCK_8814B << BIT_SHIFT_SIFS_T2T_CCK_8814B) +#define BIT_CLEAR_SIFS_T2T_CCK_8814B(x) ((x) & (~BITS_SIFS_T2T_CCK_8814B)) +#define BIT_GET_SIFS_T2T_CCK_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8814B) & BIT_MASK_SIFS_T2T_CCK_8814B) +#define BIT_SET_SIFS_T2T_CCK_8814B(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK_8814B(x) | BIT_SIFS_T2T_CCK_8814B(v)) /* 2 REG_RESP_SIFS_OFDM_8814B (RESPONSE SIFS FOR OFDM REGISTER) */ #define BIT_SHIFT_SIFS_R2T_OFDM_8814B 8 #define BIT_MASK_SIFS_R2T_OFDM_8814B 0xff -#define BIT_SIFS_R2T_OFDM_8814B(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8814B) << BIT_SHIFT_SIFS_R2T_OFDM_8814B) -#define BIT_GET_SIFS_R2T_OFDM_8814B(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8814B) & BIT_MASK_SIFS_R2T_OFDM_8814B) - - +#define BIT_SIFS_R2T_OFDM_8814B(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM_8814B) << BIT_SHIFT_SIFS_R2T_OFDM_8814B) +#define BITS_SIFS_R2T_OFDM_8814B \ + (BIT_MASK_SIFS_R2T_OFDM_8814B << BIT_SHIFT_SIFS_R2T_OFDM_8814B) +#define BIT_CLEAR_SIFS_R2T_OFDM_8814B(x) ((x) & (~BITS_SIFS_R2T_OFDM_8814B)) +#define BIT_GET_SIFS_R2T_OFDM_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8814B) & BIT_MASK_SIFS_R2T_OFDM_8814B) +#define BIT_SET_SIFS_R2T_OFDM_8814B(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM_8814B(x) | BIT_SIFS_R2T_OFDM_8814B(v)) #define BIT_SHIFT_SIFS_T2T_OFDM_8814B 0 #define BIT_MASK_SIFS_T2T_OFDM_8814B 0xff -#define BIT_SIFS_T2T_OFDM_8814B(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8814B) << BIT_SHIFT_SIFS_T2T_OFDM_8814B) -#define BIT_GET_SIFS_T2T_OFDM_8814B(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8814B) & BIT_MASK_SIFS_T2T_OFDM_8814B) - - - -/* 2 REG_RESP_SIFS_CCK_8814B (RESPONSE SIFS FOR CCK REGISTER) */ - -#define BIT_SHIFT_SIFS_R2T_CCK_8814B 8 -#define BIT_MASK_SIFS_R2T_CCK_8814B 0xff -#define BIT_SIFS_R2T_CCK_8814B(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8814B) << BIT_SHIFT_SIFS_R2T_CCK_8814B) -#define BIT_GET_SIFS_R2T_CCK_8814B(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8814B) & BIT_MASK_SIFS_R2T_CCK_8814B) - +#define BIT_SIFS_T2T_OFDM_8814B(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM_8814B) << BIT_SHIFT_SIFS_T2T_OFDM_8814B) +#define BITS_SIFS_T2T_OFDM_8814B \ + (BIT_MASK_SIFS_T2T_OFDM_8814B << BIT_SHIFT_SIFS_T2T_OFDM_8814B) +#define BIT_CLEAR_SIFS_T2T_OFDM_8814B(x) ((x) & (~BITS_SIFS_T2T_OFDM_8814B)) +#define BIT_GET_SIFS_T2T_OFDM_8814B(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8814B) & BIT_MASK_SIFS_T2T_OFDM_8814B) +#define BIT_SET_SIFS_T2T_OFDM_8814B(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM_8814B(x) | BIT_SIFS_T2T_OFDM_8814B(v)) +/* 2 REG_ACKTO_8814B (ACK TIMEOUT REGISTER) */ -#define BIT_SHIFT_SIFS_T2T_CCK_8814B 0 -#define BIT_MASK_SIFS_T2T_CCK_8814B 0xff -#define BIT_SIFS_T2T_CCK_8814B(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8814B) << BIT_SHIFT_SIFS_T2T_CCK_8814B) -#define BIT_GET_SIFS_T2T_CCK_8814B(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8814B) & BIT_MASK_SIFS_T2T_CCK_8814B) +#define BIT_SHIFT_ACKTO_8814B 0 +#define BIT_MASK_ACKTO_8814B 0xff +#define BIT_ACKTO_8814B(x) \ + (((x) & BIT_MASK_ACKTO_8814B) << BIT_SHIFT_ACKTO_8814B) +#define BITS_ACKTO_8814B (BIT_MASK_ACKTO_8814B << BIT_SHIFT_ACKTO_8814B) +#define BIT_CLEAR_ACKTO_8814B(x) ((x) & (~BITS_ACKTO_8814B)) +#define BIT_GET_ACKTO_8814B(x) \ + (((x) >> BIT_SHIFT_ACKTO_8814B) & BIT_MASK_ACKTO_8814B) +#define BIT_SET_ACKTO_8814B(x, v) \ + (BIT_CLEAR_ACKTO_8814B(x) | BIT_ACKTO_8814B(v)) +/* 2 REG_CTS2TO_8814B (CTS2 TIMEOUT REGISTER) */ +#define BIT_SHIFT_CTS2TO_8814B 0 +#define BIT_MASK_CTS2TO_8814B 0xff +#define BIT_CTS2TO_8814B(x) \ + (((x) & BIT_MASK_CTS2TO_8814B) << BIT_SHIFT_CTS2TO_8814B) +#define BITS_CTS2TO_8814B (BIT_MASK_CTS2TO_8814B << BIT_SHIFT_CTS2TO_8814B) +#define BIT_CLEAR_CTS2TO_8814B(x) ((x) & (~BITS_CTS2TO_8814B)) +#define BIT_GET_CTS2TO_8814B(x) \ + (((x) >> BIT_SHIFT_CTS2TO_8814B) & BIT_MASK_CTS2TO_8814B) +#define BIT_SET_CTS2TO_8814B(x, v) \ + (BIT_CLEAR_CTS2TO_8814B(x) | BIT_CTS2TO_8814B(v)) /* 2 REG_EIFS_8814B (EIFS REGISTER) */ #define BIT_SHIFT_EIFS_8814B 0 #define BIT_MASK_EIFS_8814B 0xffff #define BIT_EIFS_8814B(x) (((x) & BIT_MASK_EIFS_8814B) << BIT_SHIFT_EIFS_8814B) -#define BIT_GET_EIFS_8814B(x) (((x) >> BIT_SHIFT_EIFS_8814B) & BIT_MASK_EIFS_8814B) - - - -/* 2 REG_CTS2TO_8814B (CTS2 TIMEOUT REGISTER) */ - -#define BIT_SHIFT_CTS2TO_8814B 0 -#define BIT_MASK_CTS2TO_8814B 0xff -#define BIT_CTS2TO_8814B(x) (((x) & BIT_MASK_CTS2TO_8814B) << BIT_SHIFT_CTS2TO_8814B) -#define BIT_GET_CTS2TO_8814B(x) (((x) >> BIT_SHIFT_CTS2TO_8814B) & BIT_MASK_CTS2TO_8814B) - +#define BITS_EIFS_8814B (BIT_MASK_EIFS_8814B << BIT_SHIFT_EIFS_8814B) +#define BIT_CLEAR_EIFS_8814B(x) ((x) & (~BITS_EIFS_8814B)) +#define BIT_GET_EIFS_8814B(x) \ + (((x) >> BIT_SHIFT_EIFS_8814B) & BIT_MASK_EIFS_8814B) +#define BIT_SET_EIFS_8814B(x, v) (BIT_CLEAR_EIFS_8814B(x) | BIT_EIFS_8814B(v)) - -/* 2 REG_ACKTO_8814B (ACK TIMEOUT REGISTER) */ - -#define BIT_SHIFT_ACKTO_8814B 0 -#define BIT_MASK_ACKTO_8814B 0xff -#define BIT_ACKTO_8814B(x) (((x) & BIT_MASK_ACKTO_8814B) << BIT_SHIFT_ACKTO_8814B) -#define BIT_GET_ACKTO_8814B(x) (((x) >> BIT_SHIFT_ACKTO_8814B) & BIT_MASK_ACKTO_8814B) - - - -/* 2 REG_RPFM_MAP0_8814B (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 0) */ +/* 2 REG_RPFM_MAP0_8814B */ #define BIT_MGT_RPFM15EN_8814B BIT(15) #define BIT_MGT_RPFM14EN_8814B BIT(14) #define BIT_MGT_RPFM13EN_8814B BIT(13) @@ -8851,7 +21003,7 @@ #define BIT_MGT_RPFM1EN_8814B BIT(1) #define BIT_MGT_RPFM0EN_8814B BIT(0) -/* 2 REG_RPFM_MAP1_8814B (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 1) */ +/* 2 REG_RPFM_MAP1_V1_8814B */ #define BIT_DATA_RPFM15EN_8814B BIT(15) #define BIT_DATA_RPFM14EN_8814B BIT(14) #define BIT_DATA_RPFM13EN_8814B BIT(13) @@ -8876,44 +21028,66 @@ #define BIT_SHIFT_RPFM_CAM_ADDR_8814B 0 #define BIT_MASK_RPFM_CAM_ADDR_8814B 0x7f -#define BIT_RPFM_CAM_ADDR_8814B(x) (((x) & BIT_MASK_RPFM_CAM_ADDR_8814B) << BIT_SHIFT_RPFM_CAM_ADDR_8814B) -#define BIT_GET_RPFM_CAM_ADDR_8814B(x) (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8814B) & BIT_MASK_RPFM_CAM_ADDR_8814B) - - +#define BIT_RPFM_CAM_ADDR_8814B(x) \ + (((x) & BIT_MASK_RPFM_CAM_ADDR_8814B) << BIT_SHIFT_RPFM_CAM_ADDR_8814B) +#define BITS_RPFM_CAM_ADDR_8814B \ + (BIT_MASK_RPFM_CAM_ADDR_8814B << BIT_SHIFT_RPFM_CAM_ADDR_8814B) +#define BIT_CLEAR_RPFM_CAM_ADDR_8814B(x) ((x) & (~BITS_RPFM_CAM_ADDR_8814B)) +#define BIT_GET_RPFM_CAM_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8814B) & BIT_MASK_RPFM_CAM_ADDR_8814B) +#define BIT_SET_RPFM_CAM_ADDR_8814B(x, v) \ + (BIT_CLEAR_RPFM_CAM_ADDR_8814B(x) | BIT_RPFM_CAM_ADDR_8814B(v)) /* 2 REG_RPFM_CAM_RWD_8814B (ACK TIMEOUT REGISTER) */ #define BIT_SHIFT_RPFM_CAM_RWD_8814B 0 #define BIT_MASK_RPFM_CAM_RWD_8814B 0xffffffffL -#define BIT_RPFM_CAM_RWD_8814B(x) (((x) & BIT_MASK_RPFM_CAM_RWD_8814B) << BIT_SHIFT_RPFM_CAM_RWD_8814B) -#define BIT_GET_RPFM_CAM_RWD_8814B(x) (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8814B) & BIT_MASK_RPFM_CAM_RWD_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_RPFM_CAM_RWD_8814B(x) \ + (((x) & BIT_MASK_RPFM_CAM_RWD_8814B) << BIT_SHIFT_RPFM_CAM_RWD_8814B) +#define BITS_RPFM_CAM_RWD_8814B \ + (BIT_MASK_RPFM_CAM_RWD_8814B << BIT_SHIFT_RPFM_CAM_RWD_8814B) +#define BIT_CLEAR_RPFM_CAM_RWD_8814B(x) ((x) & (~BITS_RPFM_CAM_RWD_8814B)) +#define BIT_GET_RPFM_CAM_RWD_8814B(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8814B) & BIT_MASK_RPFM_CAM_RWD_8814B) +#define BIT_SET_RPFM_CAM_RWD_8814B(x, v) \ + (BIT_CLEAR_RPFM_CAM_RWD_8814B(x) | BIT_RPFM_CAM_RWD_8814B(v)) /* 2 REG_NAV_CTRL_8814B (NAV CONTROL REGISTER) */ #define BIT_SHIFT_NAV_UPPER_8814B 16 #define BIT_MASK_NAV_UPPER_8814B 0xff -#define BIT_NAV_UPPER_8814B(x) (((x) & BIT_MASK_NAV_UPPER_8814B) << BIT_SHIFT_NAV_UPPER_8814B) -#define BIT_GET_NAV_UPPER_8814B(x) (((x) >> BIT_SHIFT_NAV_UPPER_8814B) & BIT_MASK_NAV_UPPER_8814B) - - +#define BIT_NAV_UPPER_8814B(x) \ + (((x) & BIT_MASK_NAV_UPPER_8814B) << BIT_SHIFT_NAV_UPPER_8814B) +#define BITS_NAV_UPPER_8814B \ + (BIT_MASK_NAV_UPPER_8814B << BIT_SHIFT_NAV_UPPER_8814B) +#define BIT_CLEAR_NAV_UPPER_8814B(x) ((x) & (~BITS_NAV_UPPER_8814B)) +#define BIT_GET_NAV_UPPER_8814B(x) \ + (((x) >> BIT_SHIFT_NAV_UPPER_8814B) & BIT_MASK_NAV_UPPER_8814B) +#define BIT_SET_NAV_UPPER_8814B(x, v) \ + (BIT_CLEAR_NAV_UPPER_8814B(x) | BIT_NAV_UPPER_8814B(v)) #define BIT_SHIFT_RXMYRTS_NAV_8814B 8 #define BIT_MASK_RXMYRTS_NAV_8814B 0xf -#define BIT_RXMYRTS_NAV_8814B(x) (((x) & BIT_MASK_RXMYRTS_NAV_8814B) << BIT_SHIFT_RXMYRTS_NAV_8814B) -#define BIT_GET_RXMYRTS_NAV_8814B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8814B) & BIT_MASK_RXMYRTS_NAV_8814B) - - +#define BIT_RXMYRTS_NAV_8814B(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_8814B) << BIT_SHIFT_RXMYRTS_NAV_8814B) +#define BITS_RXMYRTS_NAV_8814B \ + (BIT_MASK_RXMYRTS_NAV_8814B << BIT_SHIFT_RXMYRTS_NAV_8814B) +#define BIT_CLEAR_RXMYRTS_NAV_8814B(x) ((x) & (~BITS_RXMYRTS_NAV_8814B)) +#define BIT_GET_RXMYRTS_NAV_8814B(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_8814B) & BIT_MASK_RXMYRTS_NAV_8814B) +#define BIT_SET_RXMYRTS_NAV_8814B(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_8814B(x) | BIT_RXMYRTS_NAV_8814B(v)) #define BIT_SHIFT_RTSRST_8814B 0 #define BIT_MASK_RTSRST_8814B 0xff -#define BIT_RTSRST_8814B(x) (((x) & BIT_MASK_RTSRST_8814B) << BIT_SHIFT_RTSRST_8814B) -#define BIT_GET_RTSRST_8814B(x) (((x) >> BIT_SHIFT_RTSRST_8814B) & BIT_MASK_RTSRST_8814B) - - +#define BIT_RTSRST_8814B(x) \ + (((x) & BIT_MASK_RTSRST_8814B) << BIT_SHIFT_RTSRST_8814B) +#define BITS_RTSRST_8814B (BIT_MASK_RTSRST_8814B << BIT_SHIFT_RTSRST_8814B) +#define BIT_CLEAR_RTSRST_8814B(x) ((x) & (~BITS_RTSRST_8814B)) +#define BIT_GET_RTSRST_8814B(x) \ + (((x) >> BIT_SHIFT_RTSRST_8814B) & BIT_MASK_RTSRST_8814B) +#define BIT_SET_RTSRST_8814B(x, v) \ + (BIT_CLEAR_RTSRST_8814B(x) | BIT_RTSRST_8814B(v)) /* 2 REG_BACAMCMD_8814B (BLOCK ACK CAM COMMAND REGISTER) */ #define BIT_BACAM_POLL_8814B BIT(31) @@ -8922,87 +21096,149 @@ #define BIT_SHIFT_TXSBM_8814B 14 #define BIT_MASK_TXSBM_8814B 0x3 -#define BIT_TXSBM_8814B(x) (((x) & BIT_MASK_TXSBM_8814B) << BIT_SHIFT_TXSBM_8814B) -#define BIT_GET_TXSBM_8814B(x) (((x) >> BIT_SHIFT_TXSBM_8814B) & BIT_MASK_TXSBM_8814B) - - +#define BIT_TXSBM_8814B(x) \ + (((x) & BIT_MASK_TXSBM_8814B) << BIT_SHIFT_TXSBM_8814B) +#define BITS_TXSBM_8814B (BIT_MASK_TXSBM_8814B << BIT_SHIFT_TXSBM_8814B) +#define BIT_CLEAR_TXSBM_8814B(x) ((x) & (~BITS_TXSBM_8814B)) +#define BIT_GET_TXSBM_8814B(x) \ + (((x) >> BIT_SHIFT_TXSBM_8814B) & BIT_MASK_TXSBM_8814B) +#define BIT_SET_TXSBM_8814B(x, v) \ + (BIT_CLEAR_TXSBM_8814B(x) | BIT_TXSBM_8814B(v)) #define BIT_SHIFT_BACAM_ADDR_8814B 0 #define BIT_MASK_BACAM_ADDR_8814B 0x3f -#define BIT_BACAM_ADDR_8814B(x) (((x) & BIT_MASK_BACAM_ADDR_8814B) << BIT_SHIFT_BACAM_ADDR_8814B) -#define BIT_GET_BACAM_ADDR_8814B(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8814B) & BIT_MASK_BACAM_ADDR_8814B) - - +#define BIT_BACAM_ADDR_8814B(x) \ + (((x) & BIT_MASK_BACAM_ADDR_8814B) << BIT_SHIFT_BACAM_ADDR_8814B) +#define BITS_BACAM_ADDR_8814B \ + (BIT_MASK_BACAM_ADDR_8814B << BIT_SHIFT_BACAM_ADDR_8814B) +#define BIT_CLEAR_BACAM_ADDR_8814B(x) ((x) & (~BITS_BACAM_ADDR_8814B)) +#define BIT_GET_BACAM_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR_8814B) & BIT_MASK_BACAM_ADDR_8814B) +#define BIT_SET_BACAM_ADDR_8814B(x, v) \ + (BIT_CLEAR_BACAM_ADDR_8814B(x) | BIT_BACAM_ADDR_8814B(v)) /* 2 REG_BACAMCONTENT_8814B (BLOCK ACK CAM CONTENT REGISTER) */ -#define BIT_SHIFT_BA_CONTENT_H_8814B (32 & CPU_OPT_WIDTH) -#define BIT_MASK_BA_CONTENT_H_8814B 0xffffffffL -#define BIT_BA_CONTENT_H_8814B(x) (((x) & BIT_MASK_BA_CONTENT_H_8814B) << BIT_SHIFT_BA_CONTENT_H_8814B) -#define BIT_GET_BA_CONTENT_H_8814B(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8814B) & BIT_MASK_BA_CONTENT_H_8814B) - - - #define BIT_SHIFT_BA_CONTENT_L_8814B 0 #define BIT_MASK_BA_CONTENT_L_8814B 0xffffffffL -#define BIT_BA_CONTENT_L_8814B(x) (((x) & BIT_MASK_BA_CONTENT_L_8814B) << BIT_SHIFT_BA_CONTENT_L_8814B) -#define BIT_GET_BA_CONTENT_L_8814B(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8814B) & BIT_MASK_BA_CONTENT_L_8814B) - - - -/* 2 REG_WMAC_BITMAP_CTL_8814B */ -#define BIT_BITMAP_VO_8814B BIT(7) -#define BIT_BITMAP_VI_8814B BIT(6) -#define BIT_BITMAP_BE_8814B BIT(5) -#define BIT_BITMAP_BK_8814B BIT(4) - -#define BIT_SHIFT_BITMAP_CONDITION_8814B 2 -#define BIT_MASK_BITMAP_CONDITION_8814B 0x3 -#define BIT_BITMAP_CONDITION_8814B(x) (((x) & BIT_MASK_BITMAP_CONDITION_8814B) << BIT_SHIFT_BITMAP_CONDITION_8814B) -#define BIT_GET_BITMAP_CONDITION_8814B(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8814B) & BIT_MASK_BITMAP_CONDITION_8814B) - - -#define BIT_BITMAP_SSNBK_COUNTER_CLR_8814B BIT(1) -#define BIT_BITMAP_FORCE_8814B BIT(0) - -/* 2 REG_TX_RX_8814B STATUS */ - -#define BIT_SHIFT_RXPKT_TYPE_8814B 2 -#define BIT_MASK_RXPKT_TYPE_8814B 0x3f -#define BIT_RXPKT_TYPE_8814B(x) (((x) & BIT_MASK_RXPKT_TYPE_8814B) << BIT_SHIFT_RXPKT_TYPE_8814B) -#define BIT_GET_RXPKT_TYPE_8814B(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8814B) & BIT_MASK_RXPKT_TYPE_8814B) +#define BIT_BA_CONTENT_L_8814B(x) \ + (((x) & BIT_MASK_BA_CONTENT_L_8814B) << BIT_SHIFT_BA_CONTENT_L_8814B) +#define BITS_BA_CONTENT_L_8814B \ + (BIT_MASK_BA_CONTENT_L_8814B << BIT_SHIFT_BA_CONTENT_L_8814B) +#define BIT_CLEAR_BA_CONTENT_L_8814B(x) ((x) & (~BITS_BA_CONTENT_L_8814B)) +#define BIT_GET_BA_CONTENT_L_8814B(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L_8814B) & BIT_MASK_BA_CONTENT_L_8814B) +#define BIT_SET_BA_CONTENT_L_8814B(x, v) \ + (BIT_CLEAR_BA_CONTENT_L_8814B(x) | BIT_BA_CONTENT_L_8814B(v)) + +/* 2 REG_BACAMCONTENT_H_8814B (BLOCK ACK CAM CONTENT REGISTER) */ + +#define BIT_SHIFT_BA_CONTENT_H_8814B 0 +#define BIT_MASK_BA_CONTENT_H_8814B 0xffffffffL +#define BIT_BA_CONTENT_H_8814B(x) \ + (((x) & BIT_MASK_BA_CONTENT_H_8814B) << BIT_SHIFT_BA_CONTENT_H_8814B) +#define BITS_BA_CONTENT_H_8814B \ + (BIT_MASK_BA_CONTENT_H_8814B << BIT_SHIFT_BA_CONTENT_H_8814B) +#define BIT_CLEAR_BA_CONTENT_H_8814B(x) ((x) & (~BITS_BA_CONTENT_H_8814B)) +#define BIT_GET_BA_CONTENT_H_8814B(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_H_8814B) & BIT_MASK_BA_CONTENT_H_8814B) +#define BIT_SET_BA_CONTENT_H_8814B(x, v) \ + (BIT_CLEAR_BA_CONTENT_H_8814B(x) | BIT_BA_CONTENT_H_8814B(v)) +/* 2 REG_LBDLY_8814B (LOOPBACK DELAY REGISTER) */ -#define BIT_TXACT_IND_8814B BIT(1) -#define BIT_RXACT_IND_8814B BIT(0) +#define BIT_SHIFT_LBDLY_8814B 0 +#define BIT_MASK_LBDLY_8814B 0x1f +#define BIT_LBDLY_8814B(x) \ + (((x) & BIT_MASK_LBDLY_8814B) << BIT_SHIFT_LBDLY_8814B) +#define BITS_LBDLY_8814B (BIT_MASK_LBDLY_8814B << BIT_SHIFT_LBDLY_8814B) +#define BIT_CLEAR_LBDLY_8814B(x) ((x) & (~BITS_LBDLY_8814B)) +#define BIT_GET_LBDLY_8814B(x) \ + (((x) >> BIT_SHIFT_LBDLY_8814B) & BIT_MASK_LBDLY_8814B) +#define BIT_SET_LBDLY_8814B(x, v) \ + (BIT_CLEAR_LBDLY_8814B(x) | BIT_LBDLY_8814B(v)) /* 2 REG_WMAC_BACAM_RPMEN_8814B */ #define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B 2 #define BIT_MASK_BITMAP_SSNBK_COUNTER_8814B 0x3f -#define BIT_BITMAP_SSNBK_COUNTER_8814B(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8814B) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) -#define BIT_GET_BITMAP_SSNBK_COUNTER_8814B(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) & BIT_MASK_BITMAP_SSNBK_COUNTER_8814B) - +#define BIT_BITMAP_SSNBK_COUNTER_8814B(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8814B) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) +#define BITS_BITMAP_SSNBK_COUNTER_8814B \ + (BIT_MASK_BITMAP_SSNBK_COUNTER_8814B \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8814B(x) \ + ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8814B)) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8814B(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER_8814B) +#define BIT_SET_BITMAP_SSNBK_COUNTER_8814B(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8814B(x) | \ + BIT_BITMAP_SSNBK_COUNTER_8814B(v)) #define BIT_BITMAP_EN_8814B BIT(1) #define BIT_WMAC_BACAM_RPMEN_8814B BIT(0) -/* 2 REG_LBDLY_8814B (LOOPBACK DELAY REGISTER) */ +/* 2 REG_TX_RX_8814B STATUS */ -#define BIT_SHIFT_LBDLY_8814B 0 -#define BIT_MASK_LBDLY_8814B 0x1f -#define BIT_LBDLY_8814B(x) (((x) & BIT_MASK_LBDLY_8814B) << BIT_SHIFT_LBDLY_8814B) -#define BIT_GET_LBDLY_8814B(x) (((x) >> BIT_SHIFT_LBDLY_8814B) & BIT_MASK_LBDLY_8814B) +#define BIT_SHIFT_RXPKT_TYPE_8814B 2 +#define BIT_MASK_RXPKT_TYPE_8814B 0x3f +#define BIT_RXPKT_TYPE_8814B(x) \ + (((x) & BIT_MASK_RXPKT_TYPE_8814B) << BIT_SHIFT_RXPKT_TYPE_8814B) +#define BITS_RXPKT_TYPE_8814B \ + (BIT_MASK_RXPKT_TYPE_8814B << BIT_SHIFT_RXPKT_TYPE_8814B) +#define BIT_CLEAR_RXPKT_TYPE_8814B(x) ((x) & (~BITS_RXPKT_TYPE_8814B)) +#define BIT_GET_RXPKT_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE_8814B) & BIT_MASK_RXPKT_TYPE_8814B) +#define BIT_SET_RXPKT_TYPE_8814B(x, v) \ + (BIT_CLEAR_RXPKT_TYPE_8814B(x) | BIT_RXPKT_TYPE_8814B(v)) + +#define BIT_TXACT_IND_8814B BIT(1) +#define BIT_RXACT_IND_8814B BIT(0) +/* 2 REG_WMAC_BITMAP_CTL_8814B */ +#define BIT_BITMAP_VO_8814B BIT(7) +#define BIT_BITMAP_VI_8814B BIT(6) +#define BIT_BITMAP_BE_8814B BIT(5) +#define BIT_BITMAP_BK_8814B BIT(4) + +#define BIT_SHIFT_BITMAP_CONDITION_8814B 2 +#define BIT_MASK_BITMAP_CONDITION_8814B 0x3 +#define BIT_BITMAP_CONDITION_8814B(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION_8814B) \ + << BIT_SHIFT_BITMAP_CONDITION_8814B) +#define BITS_BITMAP_CONDITION_8814B \ + (BIT_MASK_BITMAP_CONDITION_8814B << BIT_SHIFT_BITMAP_CONDITION_8814B) +#define BIT_CLEAR_BITMAP_CONDITION_8814B(x) \ + ((x) & (~BITS_BITMAP_CONDITION_8814B)) +#define BIT_GET_BITMAP_CONDITION_8814B(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION_8814B) & \ + BIT_MASK_BITMAP_CONDITION_8814B) +#define BIT_SET_BITMAP_CONDITION_8814B(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION_8814B(x) | BIT_BITMAP_CONDITION_8814B(v)) +#define BIT_BITMAP_SSNBK_COUNTER_CLR_8814B BIT(1) +#define BIT_BITMAP_FORCE_8814B BIT(0) /* 2 REG_RXERR_RPT_8814B (RX ERROR REPORT REGISTER) */ #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B 28 #define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B 0xf -#define BIT_RXERR_RPT_SEL_V1_3_0_8814B(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) -#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8814B(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B) - +#define BIT_RXERR_RPT_SEL_V1_3_0_8814B(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) +#define BITS_RXERR_RPT_SEL_V1_3_0_8814B \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8814B(x) \ + ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8814B)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8814B(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8814B(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8814B(x) | \ + BIT_RXERR_RPT_SEL_V1_3_0_8814B(v)) #define BIT_RXERR_RPT_RST_8814B BIT(27) #define BIT_RXERR_RPT_SEL_V1_4_8814B BIT(26) @@ -9011,64 +21247,40 @@ #define BIT_SHIFT_UD_SUB_TYPE_8814B 18 #define BIT_MASK_UD_SUB_TYPE_8814B 0xf -#define BIT_UD_SUB_TYPE_8814B(x) (((x) & BIT_MASK_UD_SUB_TYPE_8814B) << BIT_SHIFT_UD_SUB_TYPE_8814B) -#define BIT_GET_UD_SUB_TYPE_8814B(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8814B) & BIT_MASK_UD_SUB_TYPE_8814B) - - +#define BIT_UD_SUB_TYPE_8814B(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE_8814B) << BIT_SHIFT_UD_SUB_TYPE_8814B) +#define BITS_UD_SUB_TYPE_8814B \ + (BIT_MASK_UD_SUB_TYPE_8814B << BIT_SHIFT_UD_SUB_TYPE_8814B) +#define BIT_CLEAR_UD_SUB_TYPE_8814B(x) ((x) & (~BITS_UD_SUB_TYPE_8814B)) +#define BIT_GET_UD_SUB_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE_8814B) & BIT_MASK_UD_SUB_TYPE_8814B) +#define BIT_SET_UD_SUB_TYPE_8814B(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE_8814B(x) | BIT_UD_SUB_TYPE_8814B(v)) #define BIT_SHIFT_UD_TYPE_8814B 16 #define BIT_MASK_UD_TYPE_8814B 0x3 -#define BIT_UD_TYPE_8814B(x) (((x) & BIT_MASK_UD_TYPE_8814B) << BIT_SHIFT_UD_TYPE_8814B) -#define BIT_GET_UD_TYPE_8814B(x) (((x) >> BIT_SHIFT_UD_TYPE_8814B) & BIT_MASK_UD_TYPE_8814B) - - +#define BIT_UD_TYPE_8814B(x) \ + (((x) & BIT_MASK_UD_TYPE_8814B) << BIT_SHIFT_UD_TYPE_8814B) +#define BITS_UD_TYPE_8814B (BIT_MASK_UD_TYPE_8814B << BIT_SHIFT_UD_TYPE_8814B) +#define BIT_CLEAR_UD_TYPE_8814B(x) ((x) & (~BITS_UD_TYPE_8814B)) +#define BIT_GET_UD_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_UD_TYPE_8814B) & BIT_MASK_UD_TYPE_8814B) +#define BIT_SET_UD_TYPE_8814B(x, v) \ + (BIT_CLEAR_UD_TYPE_8814B(x) | BIT_UD_TYPE_8814B(v)) #define BIT_SHIFT_RPT_COUNTER_8814B 0 #define BIT_MASK_RPT_COUNTER_8814B 0xffff -#define BIT_RPT_COUNTER_8814B(x) (((x) & BIT_MASK_RPT_COUNTER_8814B) << BIT_SHIFT_RPT_COUNTER_8814B) -#define BIT_GET_RPT_COUNTER_8814B(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8814B) & BIT_MASK_RPT_COUNTER_8814B) - - - -/* 2 REG_WMAC_TRXPTCL_CTL_8814B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ - -#define BIT_SHIFT_ACKBA_TYPSEL_8814B (60 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_TYPSEL_8814B 0xf -#define BIT_ACKBA_TYPSEL_8814B(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8814B) << BIT_SHIFT_ACKBA_TYPSEL_8814B) -#define BIT_GET_ACKBA_TYPSEL_8814B(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8814B) & BIT_MASK_ACKBA_TYPSEL_8814B) - - - -#define BIT_SHIFT_ACKBA_ACKPCHK_8814B (56 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_ACKPCHK_8814B 0xf -#define BIT_ACKBA_ACKPCHK_8814B(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8814B) << BIT_SHIFT_ACKBA_ACKPCHK_8814B) -#define BIT_GET_ACKBA_ACKPCHK_8814B(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8814B) & BIT_MASK_ACKBA_ACKPCHK_8814B) - - - -#define BIT_SHIFT_ACKBAR_TYPESEL_8814B (48 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_TYPESEL_8814B 0xff -#define BIT_ACKBAR_TYPESEL_8814B(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8814B) << BIT_SHIFT_ACKBAR_TYPESEL_8814B) -#define BIT_GET_ACKBAR_TYPESEL_8814B(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8814B) & BIT_MASK_ACKBAR_TYPESEL_8814B) - - - -#define BIT_SHIFT_ACKBAR_ACKPCHK_8814B (44 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_ACKPCHK_8814B 0xf -#define BIT_ACKBAR_ACKPCHK_8814B(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8814B) << BIT_SHIFT_ACKBAR_ACKPCHK_8814B) -#define BIT_GET_ACKBAR_ACKPCHK_8814B(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8814B) & BIT_MASK_ACKBAR_ACKPCHK_8814B) - - -#define BIT_RXBA_IGNOREA2_8814B BIT(42) -#define BIT_EN_SAVE_ALL_TXOPADDR_8814B BIT(41) -#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8814B BIT(40) -#define BIT_DIS_TXBA_AMPDUFCSERR_8814B BIT(39) -#define BIT_DIS_TXBA_RXBARINFULL_8814B BIT(38) -#define BIT_DIS_TXCFE_INFULL_8814B BIT(37) -#define BIT_DIS_TXCTS_INFULL_8814B BIT(36) -#define BIT_EN_TXACKBA_IN_TX_RDG_8814B BIT(35) -#define BIT_EN_TXACKBA_IN_TXOP_8814B BIT(34) -#define BIT_EN_TXCTS_IN_RXNAV_8814B BIT(33) +#define BIT_RPT_COUNTER_8814B(x) \ + (((x) & BIT_MASK_RPT_COUNTER_8814B) << BIT_SHIFT_RPT_COUNTER_8814B) +#define BITS_RPT_COUNTER_8814B \ + (BIT_MASK_RPT_COUNTER_8814B << BIT_SHIFT_RPT_COUNTER_8814B) +#define BIT_CLEAR_RPT_COUNTER_8814B(x) ((x) & (~BITS_RPT_COUNTER_8814B)) +#define BIT_GET_RPT_COUNTER_8814B(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER_8814B) & BIT_MASK_RPT_COUNTER_8814B) +#define BIT_SET_RPT_COUNTER_8814B(x, v) \ + (BIT_CLEAR_RPT_COUNTER_8814B(x) | BIT_RPT_COUNTER_8814B(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_8814B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ #define BIT_EN_TXCTS_INTXOP_8814B BIT(32) #define BIT_BLK_EDCA_BBSLP_8814B BIT(31) #define BIT_BLK_EDCA_BBSBY_8814B BIT(30) @@ -9081,9 +21293,15 @@ #define BIT_SHIFT_RESP_CHNBUSY_8814B 20 #define BIT_MASK_RESP_CHNBUSY_8814B 0x3 -#define BIT_RESP_CHNBUSY_8814B(x) (((x) & BIT_MASK_RESP_CHNBUSY_8814B) << BIT_SHIFT_RESP_CHNBUSY_8814B) -#define BIT_GET_RESP_CHNBUSY_8814B(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8814B) & BIT_MASK_RESP_CHNBUSY_8814B) - +#define BIT_RESP_CHNBUSY_8814B(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY_8814B) << BIT_SHIFT_RESP_CHNBUSY_8814B) +#define BITS_RESP_CHNBUSY_8814B \ + (BIT_MASK_RESP_CHNBUSY_8814B << BIT_SHIFT_RESP_CHNBUSY_8814B) +#define BIT_CLEAR_RESP_CHNBUSY_8814B(x) ((x) & (~BITS_RESP_CHNBUSY_8814B)) +#define BIT_GET_RESP_CHNBUSY_8814B(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY_8814B) & BIT_MASK_RESP_CHNBUSY_8814B) +#define BIT_SET_RESP_CHNBUSY_8814B(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY_8814B(x) | BIT_RESP_CHNBUSY_8814B(v)) #define BIT_RESP_DCTS_EN_8814B BIT(19) #define BIT_RESP_DCFE_EN_8814B BIT(18) @@ -9095,64 +21313,176 @@ #define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B 10 #define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B 0x7 -#define BIT_R_WMAC_SECOND_CCA_TIMER_8814B(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) -#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B) - - +#define BIT_R_WMAC_SECOND_CCA_TIMER_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) +#define BITS_R_WMAC_SECOND_CCA_TIMER_8814B \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8814B(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8814B)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8814B(x) | \ + BIT_R_WMAC_SECOND_CCA_TIMER_8814B(v)) #define BIT_SHIFT_RFMOD_8814B 7 #define BIT_MASK_RFMOD_8814B 0x3 -#define BIT_RFMOD_8814B(x) (((x) & BIT_MASK_RFMOD_8814B) << BIT_SHIFT_RFMOD_8814B) -#define BIT_GET_RFMOD_8814B(x) (((x) >> BIT_SHIFT_RFMOD_8814B) & BIT_MASK_RFMOD_8814B) - - +#define BIT_RFMOD_8814B(x) \ + (((x) & BIT_MASK_RFMOD_8814B) << BIT_SHIFT_RFMOD_8814B) +#define BITS_RFMOD_8814B (BIT_MASK_RFMOD_8814B << BIT_SHIFT_RFMOD_8814B) +#define BIT_CLEAR_RFMOD_8814B(x) ((x) & (~BITS_RFMOD_8814B)) +#define BIT_GET_RFMOD_8814B(x) \ + (((x) >> BIT_SHIFT_RFMOD_8814B) & BIT_MASK_RFMOD_8814B) +#define BIT_SET_RFMOD_8814B(x, v) \ + (BIT_CLEAR_RFMOD_8814B(x) | BIT_RFMOD_8814B(v)) #define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B 5 #define BIT_MASK_RESP_CTS_DYNBW_SEL_8814B 0x3 -#define BIT_RESP_CTS_DYNBW_SEL_8814B(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8814B) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) -#define BIT_GET_RESP_CTS_DYNBW_SEL_8814B(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) & BIT_MASK_RESP_CTS_DYNBW_SEL_8814B) - +#define BIT_RESP_CTS_DYNBW_SEL_8814B(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8814B) \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) +#define BITS_RESP_CTS_DYNBW_SEL_8814B \ + (BIT_MASK_RESP_CTS_DYNBW_SEL_8814B \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8814B(x) \ + ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8814B)) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) & \ + BIT_MASK_RESP_CTS_DYNBW_SEL_8814B) +#define BIT_SET_RESP_CTS_DYNBW_SEL_8814B(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8814B(x) | \ + BIT_RESP_CTS_DYNBW_SEL_8814B(v)) #define BIT_DLY_TX_WAIT_RXANTSEL_8814B BIT(4) #define BIT_TXRESP_BY_RXANTSEL_8814B BIT(3) #define BIT_SHIFT_ORIG_DCTS_CHK_8814B 0 #define BIT_MASK_ORIG_DCTS_CHK_8814B 0x3 -#define BIT_ORIG_DCTS_CHK_8814B(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8814B) << BIT_SHIFT_ORIG_DCTS_CHK_8814B) -#define BIT_GET_ORIG_DCTS_CHK_8814B(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8814B) & BIT_MASK_ORIG_DCTS_CHK_8814B) - - +#define BIT_ORIG_DCTS_CHK_8814B(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK_8814B) << BIT_SHIFT_ORIG_DCTS_CHK_8814B) +#define BITS_ORIG_DCTS_CHK_8814B \ + (BIT_MASK_ORIG_DCTS_CHK_8814B << BIT_SHIFT_ORIG_DCTS_CHK_8814B) +#define BIT_CLEAR_ORIG_DCTS_CHK_8814B(x) ((x) & (~BITS_ORIG_DCTS_CHK_8814B)) +#define BIT_GET_ORIG_DCTS_CHK_8814B(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8814B) & BIT_MASK_ORIG_DCTS_CHK_8814B) +#define BIT_SET_ORIG_DCTS_CHK_8814B(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK_8814B(x) | BIT_ORIG_DCTS_CHK_8814B(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_H_8814B */ + +#define BIT_SHIFT_ACKBA_TYPSEL_8814B 28 +#define BIT_MASK_ACKBA_TYPSEL_8814B 0xf +#define BIT_ACKBA_TYPSEL_8814B(x) \ + (((x) & BIT_MASK_ACKBA_TYPSEL_8814B) << BIT_SHIFT_ACKBA_TYPSEL_8814B) +#define BITS_ACKBA_TYPSEL_8814B \ + (BIT_MASK_ACKBA_TYPSEL_8814B << BIT_SHIFT_ACKBA_TYPSEL_8814B) +#define BIT_CLEAR_ACKBA_TYPSEL_8814B(x) ((x) & (~BITS_ACKBA_TYPSEL_8814B)) +#define BIT_GET_ACKBA_TYPSEL_8814B(x) \ + (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8814B) & BIT_MASK_ACKBA_TYPSEL_8814B) +#define BIT_SET_ACKBA_TYPSEL_8814B(x, v) \ + (BIT_CLEAR_ACKBA_TYPSEL_8814B(x) | BIT_ACKBA_TYPSEL_8814B(v)) + +#define BIT_SHIFT_ACKBA_ACKPCHK_8814B 24 +#define BIT_MASK_ACKBA_ACKPCHK_8814B 0xf +#define BIT_ACKBA_ACKPCHK_8814B(x) \ + (((x) & BIT_MASK_ACKBA_ACKPCHK_8814B) << BIT_SHIFT_ACKBA_ACKPCHK_8814B) +#define BITS_ACKBA_ACKPCHK_8814B \ + (BIT_MASK_ACKBA_ACKPCHK_8814B << BIT_SHIFT_ACKBA_ACKPCHK_8814B) +#define BIT_CLEAR_ACKBA_ACKPCHK_8814B(x) ((x) & (~BITS_ACKBA_ACKPCHK_8814B)) +#define BIT_GET_ACKBA_ACKPCHK_8814B(x) \ + (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8814B) & BIT_MASK_ACKBA_ACKPCHK_8814B) +#define BIT_SET_ACKBA_ACKPCHK_8814B(x, v) \ + (BIT_CLEAR_ACKBA_ACKPCHK_8814B(x) | BIT_ACKBA_ACKPCHK_8814B(v)) + +#define BIT_SHIFT_ACKBAR_TYPESEL_8814B 16 +#define BIT_MASK_ACKBAR_TYPESEL_8814B 0xff +#define BIT_ACKBAR_TYPESEL_8814B(x) \ + (((x) & BIT_MASK_ACKBAR_TYPESEL_8814B) \ + << BIT_SHIFT_ACKBAR_TYPESEL_8814B) +#define BITS_ACKBAR_TYPESEL_8814B \ + (BIT_MASK_ACKBAR_TYPESEL_8814B << BIT_SHIFT_ACKBAR_TYPESEL_8814B) +#define BIT_CLEAR_ACKBAR_TYPESEL_8814B(x) ((x) & (~BITS_ACKBAR_TYPESEL_8814B)) +#define BIT_GET_ACKBAR_TYPESEL_8814B(x) \ + (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8814B) & \ + BIT_MASK_ACKBAR_TYPESEL_8814B) +#define BIT_SET_ACKBAR_TYPESEL_8814B(x, v) \ + (BIT_CLEAR_ACKBAR_TYPESEL_8814B(x) | BIT_ACKBAR_TYPESEL_8814B(v)) + +#define BIT_SHIFT_ACKBAR_ACKPCHK_8814B 12 +#define BIT_MASK_ACKBAR_ACKPCHK_8814B 0xf +#define BIT_ACKBAR_ACKPCHK_8814B(x) \ + (((x) & BIT_MASK_ACKBAR_ACKPCHK_8814B) \ + << BIT_SHIFT_ACKBAR_ACKPCHK_8814B) +#define BITS_ACKBAR_ACKPCHK_8814B \ + (BIT_MASK_ACKBAR_ACKPCHK_8814B << BIT_SHIFT_ACKBAR_ACKPCHK_8814B) +#define BIT_CLEAR_ACKBAR_ACKPCHK_8814B(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8814B)) +#define BIT_GET_ACKBAR_ACKPCHK_8814B(x) \ + (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8814B) & \ + BIT_MASK_ACKBAR_ACKPCHK_8814B) +#define BIT_SET_ACKBAR_ACKPCHK_8814B(x, v) \ + (BIT_CLEAR_ACKBAR_ACKPCHK_8814B(x) | BIT_ACKBAR_ACKPCHK_8814B(v)) + +#define BIT_RXBA_IGNOREA2_V1_8814B BIT(10) +#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8814B BIT(9) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8814B BIT(8) +#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8814B BIT(7) +#define BIT_DIS_TXBA_RXBARINFULL_V1_8814B BIT(6) +#define BIT_DIS_TXCFE_INFULL_V1_8814B BIT(5) +#define BIT_DIS_TXCTS_INFULL_V1_8814B BIT(4) +#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8814B BIT(3) +#define BIT_EN_TXACKBA_IN_TXOP_V1_8814B BIT(2) +#define BIT_EN_TXCTS_IN_RXNAV_V1_8814B BIT(1) +#define BIT_EN_TXCTS_INTXOP_V1_8814B BIT(0) /* 2 REG_CAMCMD_8814B (CAM COMMAND REGISTER) */ #define BIT_SECCAM_POLLING_8814B BIT(31) #define BIT_SECCAM_CLR_8814B BIT(30) -#define BIT_MFBCAM_CLR_8814B BIT(29) #define BIT_SECCAM_WE_8814B BIT(16) #define BIT_SHIFT_SECCAM_ADDR_V2_8814B 0 #define BIT_MASK_SECCAM_ADDR_V2_8814B 0x3ff -#define BIT_SECCAM_ADDR_V2_8814B(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8814B) << BIT_SHIFT_SECCAM_ADDR_V2_8814B) -#define BIT_GET_SECCAM_ADDR_V2_8814B(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8814B) & BIT_MASK_SECCAM_ADDR_V2_8814B) - - +#define BIT_SECCAM_ADDR_V2_8814B(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2_8814B) \ + << BIT_SHIFT_SECCAM_ADDR_V2_8814B) +#define BITS_SECCAM_ADDR_V2_8814B \ + (BIT_MASK_SECCAM_ADDR_V2_8814B << BIT_SHIFT_SECCAM_ADDR_V2_8814B) +#define BIT_CLEAR_SECCAM_ADDR_V2_8814B(x) ((x) & (~BITS_SECCAM_ADDR_V2_8814B)) +#define BIT_GET_SECCAM_ADDR_V2_8814B(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8814B) & \ + BIT_MASK_SECCAM_ADDR_V2_8814B) +#define BIT_SET_SECCAM_ADDR_V2_8814B(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2_8814B(x) | BIT_SECCAM_ADDR_V2_8814B(v)) /* 2 REG_CAMWRITE_8814B (CAM WRITE REGISTER) */ #define BIT_SHIFT_CAMW_DATA_8814B 0 #define BIT_MASK_CAMW_DATA_8814B 0xffffffffL -#define BIT_CAMW_DATA_8814B(x) (((x) & BIT_MASK_CAMW_DATA_8814B) << BIT_SHIFT_CAMW_DATA_8814B) -#define BIT_GET_CAMW_DATA_8814B(x) (((x) >> BIT_SHIFT_CAMW_DATA_8814B) & BIT_MASK_CAMW_DATA_8814B) - - +#define BIT_CAMW_DATA_8814B(x) \ + (((x) & BIT_MASK_CAMW_DATA_8814B) << BIT_SHIFT_CAMW_DATA_8814B) +#define BITS_CAMW_DATA_8814B \ + (BIT_MASK_CAMW_DATA_8814B << BIT_SHIFT_CAMW_DATA_8814B) +#define BIT_CLEAR_CAMW_DATA_8814B(x) ((x) & (~BITS_CAMW_DATA_8814B)) +#define BIT_GET_CAMW_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_CAMW_DATA_8814B) & BIT_MASK_CAMW_DATA_8814B) +#define BIT_SET_CAMW_DATA_8814B(x, v) \ + (BIT_CLEAR_CAMW_DATA_8814B(x) | BIT_CAMW_DATA_8814B(v)) /* 2 REG_CAMREAD_8814B (CAM READ REGISTER) */ #define BIT_SHIFT_CAMR_DATA_8814B 0 #define BIT_MASK_CAMR_DATA_8814B 0xffffffffL -#define BIT_CAMR_DATA_8814B(x) (((x) & BIT_MASK_CAMR_DATA_8814B) << BIT_SHIFT_CAMR_DATA_8814B) -#define BIT_GET_CAMR_DATA_8814B(x) (((x) >> BIT_SHIFT_CAMR_DATA_8814B) & BIT_MASK_CAMR_DATA_8814B) - - +#define BIT_CAMR_DATA_8814B(x) \ + (((x) & BIT_MASK_CAMR_DATA_8814B) << BIT_SHIFT_CAMR_DATA_8814B) +#define BITS_CAMR_DATA_8814B \ + (BIT_MASK_CAMR_DATA_8814B << BIT_SHIFT_CAMR_DATA_8814B) +#define BIT_CLEAR_CAMR_DATA_8814B(x) ((x) & (~BITS_CAMR_DATA_8814B)) +#define BIT_GET_CAMR_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_CAMR_DATA_8814B) & BIT_MASK_CAMR_DATA_8814B) +#define BIT_SET_CAMR_DATA_8814B(x, v) \ + (BIT_CLEAR_CAMR_DATA_8814B(x) | BIT_CAMR_DATA_8814B(v)) /* 2 REG_CAMDBG_8814B (CAM DEBUG REGISTER) */ #define BIT_SECCAM_INFO_8814B BIT(31) @@ -9160,43 +21490,53 @@ #define BIT_SHIFT_CAMDBG_SEC_TYPE_8814B 12 #define BIT_MASK_CAMDBG_SEC_TYPE_8814B 0x7 -#define BIT_CAMDBG_SEC_TYPE_8814B(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8814B) << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) -#define BIT_GET_CAMDBG_SEC_TYPE_8814B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) & BIT_MASK_CAMDBG_SEC_TYPE_8814B) - +#define BIT_CAMDBG_SEC_TYPE_8814B(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8814B) \ + << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) +#define BITS_CAMDBG_SEC_TYPE_8814B \ + (BIT_MASK_CAMDBG_SEC_TYPE_8814B << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) +#define BIT_CLEAR_CAMDBG_SEC_TYPE_8814B(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8814B)) +#define BIT_GET_CAMDBG_SEC_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) & \ + BIT_MASK_CAMDBG_SEC_TYPE_8814B) +#define BIT_SET_CAMDBG_SEC_TYPE_8814B(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_8814B(x) | BIT_CAMDBG_SEC_TYPE_8814B(v)) #define BIT_CAMDBG_EXT_SECTYPE_8814B BIT(11) #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B 5 #define BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B 0x1f -#define BIT_CAMDBG_MIC_KEY_IDX_8814B(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) -#define BIT_GET_CAMDBG_MIC_KEY_IDX_8814B(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B) - - +#define BIT_CAMDBG_MIC_KEY_IDX_8814B(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) +#define BITS_CAMDBG_MIC_KEY_IDX_8814B \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8814B(x) \ + ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8814B)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_8814B(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8814B(x) | \ + BIT_CAMDBG_MIC_KEY_IDX_8814B(v)) #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B 0x1f -#define BIT_CAMDBG_SEC_KEY_IDX_8814B(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) -#define BIT_GET_CAMDBG_SEC_KEY_IDX_8814B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B) - - - -/* 2 REG_RXFILTER_ACTION_1_8814B */ - -#define BIT_SHIFT_RXFILTER_ACTION_1_8814B 0 -#define BIT_MASK_RXFILTER_ACTION_1_8814B 0xff -#define BIT_RXFILTER_ACTION_1_8814B(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8814B) << BIT_SHIFT_RXFILTER_ACTION_1_8814B) -#define BIT_GET_RXFILTER_ACTION_1_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8814B) & BIT_MASK_RXFILTER_ACTION_1_8814B) - - - -/* 2 REG_RXFILTER_CATEGORY_1_8814B */ - -#define BIT_SHIFT_RXFILTER_CATEGORY_1_8814B 0 -#define BIT_MASK_RXFILTER_CATEGORY_1_8814B 0xff -#define BIT_RXFILTER_CATEGORY_1_8814B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8814B) << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) -#define BIT_GET_RXFILTER_CATEGORY_1_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) & BIT_MASK_RXFILTER_CATEGORY_1_8814B) - - +#define BIT_CAMDBG_SEC_KEY_IDX_8814B(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) +#define BITS_CAMDBG_SEC_KEY_IDX_8814B \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8814B(x) \ + ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8814B)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_8814B(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8814B(x) | \ + BIT_CAMDBG_SEC_KEY_IDX_8814B(v)) /* 2 REG_SECCFG_8814B (SECURITY CONFIGURATION REGISTER) */ #define BIT_DIS_GCLK_WAPI_8814B BIT(15) @@ -9215,59 +21555,113 @@ #define BIT_RXUHUSEDK_8814B BIT(1) #define BIT_TXUHUSEDK_8814B BIT(0) -/* 2 REG_RXFILTER_ACTION_3_8814B */ - -#define BIT_SHIFT_RXFILTER_ACTION_3_8814B 0 -#define BIT_MASK_RXFILTER_ACTION_3_8814B 0xff -#define BIT_RXFILTER_ACTION_3_8814B(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8814B) << BIT_SHIFT_RXFILTER_ACTION_3_8814B) -#define BIT_GET_RXFILTER_ACTION_3_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8814B) & BIT_MASK_RXFILTER_ACTION_3_8814B) - +/* 2 REG_RXFILTER_CATEGORY_1_8814B */ +#define BIT_SHIFT_RXFILTER_CATEGORY_1_8814B 0 +#define BIT_MASK_RXFILTER_CATEGORY_1_8814B 0xff +#define BIT_RXFILTER_CATEGORY_1_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8814B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) +#define BITS_RXFILTER_CATEGORY_1_8814B \ + (BIT_MASK_RXFILTER_CATEGORY_1_8814B \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) +#define BIT_CLEAR_RXFILTER_CATEGORY_1_8814B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_1_8814B)) +#define BIT_GET_RXFILTER_CATEGORY_1_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) & \ + BIT_MASK_RXFILTER_CATEGORY_1_8814B) +#define BIT_SET_RXFILTER_CATEGORY_1_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1_8814B(x) | \ + BIT_RXFILTER_CATEGORY_1_8814B(v)) -/* 2 REG_RXFILTER_CATEGORY_3_8814B */ +/* 2 REG_RXFILTER_ACTION_1_8814B */ -#define BIT_SHIFT_RXFILTER_CATEGORY_3_8814B 0 -#define BIT_MASK_RXFILTER_CATEGORY_3_8814B 0xff -#define BIT_RXFILTER_CATEGORY_3_8814B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8814B) << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) -#define BIT_GET_RXFILTER_CATEGORY_3_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) & BIT_MASK_RXFILTER_CATEGORY_3_8814B) +#define BIT_SHIFT_RXFILTER_ACTION_1_8814B 0 +#define BIT_MASK_RXFILTER_ACTION_1_8814B 0xff +#define BIT_RXFILTER_ACTION_1_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1_8814B) \ + << BIT_SHIFT_RXFILTER_ACTION_1_8814B) +#define BITS_RXFILTER_ACTION_1_8814B \ + (BIT_MASK_RXFILTER_ACTION_1_8814B << BIT_SHIFT_RXFILTER_ACTION_1_8814B) +#define BIT_CLEAR_RXFILTER_ACTION_1_8814B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_1_8814B)) +#define BIT_GET_RXFILTER_ACTION_1_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8814B) & \ + BIT_MASK_RXFILTER_ACTION_1_8814B) +#define BIT_SET_RXFILTER_ACTION_1_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1_8814B(x) | BIT_RXFILTER_ACTION_1_8814B(v)) +/* 2 REG_RXFILTER_CATEGORY_2_8814B */ +#define BIT_SHIFT_RXFILTER_CATEGORY_2_8814B 0 +#define BIT_MASK_RXFILTER_CATEGORY_2_8814B 0xff +#define BIT_RXFILTER_CATEGORY_2_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8814B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) +#define BITS_RXFILTER_CATEGORY_2_8814B \ + (BIT_MASK_RXFILTER_CATEGORY_2_8814B \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) +#define BIT_CLEAR_RXFILTER_CATEGORY_2_8814B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_2_8814B)) +#define BIT_GET_RXFILTER_CATEGORY_2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) & \ + BIT_MASK_RXFILTER_CATEGORY_2_8814B) +#define BIT_SET_RXFILTER_CATEGORY_2_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2_8814B(x) | \ + BIT_RXFILTER_CATEGORY_2_8814B(v)) /* 2 REG_RXFILTER_ACTION_2_8814B */ #define BIT_SHIFT_RXFILTER_ACTION_2_8814B 0 #define BIT_MASK_RXFILTER_ACTION_2_8814B 0xff -#define BIT_RXFILTER_ACTION_2_8814B(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8814B) << BIT_SHIFT_RXFILTER_ACTION_2_8814B) -#define BIT_GET_RXFILTER_ACTION_2_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8814B) & BIT_MASK_RXFILTER_ACTION_2_8814B) - - +#define BIT_RXFILTER_ACTION_2_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2_8814B) \ + << BIT_SHIFT_RXFILTER_ACTION_2_8814B) +#define BITS_RXFILTER_ACTION_2_8814B \ + (BIT_MASK_RXFILTER_ACTION_2_8814B << BIT_SHIFT_RXFILTER_ACTION_2_8814B) +#define BIT_CLEAR_RXFILTER_ACTION_2_8814B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_2_8814B)) +#define BIT_GET_RXFILTER_ACTION_2_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8814B) & \ + BIT_MASK_RXFILTER_ACTION_2_8814B) +#define BIT_SET_RXFILTER_ACTION_2_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2_8814B(x) | BIT_RXFILTER_ACTION_2_8814B(v)) -/* 2 REG_RXFILTER_CATEGORY_2_8814B */ - -#define BIT_SHIFT_RXFILTER_CATEGORY_2_8814B 0 -#define BIT_MASK_RXFILTER_CATEGORY_2_8814B 0xff -#define BIT_RXFILTER_CATEGORY_2_8814B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8814B) << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) -#define BIT_GET_RXFILTER_CATEGORY_2_8814B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) & BIT_MASK_RXFILTER_CATEGORY_2_8814B) +/* 2 REG_RXFILTER_CATEGORY_3_8814B */ +#define BIT_SHIFT_RXFILTER_CATEGORY_3_8814B 0 +#define BIT_MASK_RXFILTER_CATEGORY_3_8814B 0xff +#define BIT_RXFILTER_CATEGORY_3_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8814B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) +#define BITS_RXFILTER_CATEGORY_3_8814B \ + (BIT_MASK_RXFILTER_CATEGORY_3_8814B \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) +#define BIT_CLEAR_RXFILTER_CATEGORY_3_8814B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_3_8814B)) +#define BIT_GET_RXFILTER_CATEGORY_3_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) & \ + BIT_MASK_RXFILTER_CATEGORY_3_8814B) +#define BIT_SET_RXFILTER_CATEGORY_3_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3_8814B(x) | \ + BIT_RXFILTER_CATEGORY_3_8814B(v)) +/* 2 REG_RXFILTER_ACTION_3_8814B */ -/* 2 REG_RXFLTMAP4_8814B (RX FILTER MAP GROUP 4) */ -#define BIT_CTRLFLT15EN_FW_8814B BIT(15) -#define BIT_CTRLFLT14EN_FW_8814B BIT(14) -#define BIT_CTRLFLT13EN_FW_8814B BIT(13) -#define BIT_CTRLFLT12EN_FW_8814B BIT(12) -#define BIT_CTRLFLT11EN_FW_8814B BIT(11) -#define BIT_CTRLFLT10EN_FW_8814B BIT(10) -#define BIT_CTRLFLT9EN_FW_8814B BIT(9) -#define BIT_CTRLFLT8EN_FW_8814B BIT(8) -#define BIT_CTRLFLT7EN_FW_8814B BIT(7) -#define BIT_CTRLFLT6EN_FW_8814B BIT(6) -#define BIT_CTRLFLT5EN_FW_8814B BIT(5) -#define BIT_CTRLFLT4EN_FW_8814B BIT(4) -#define BIT_CTRLFLT3EN_FW_8814B BIT(3) -#define BIT_CTRLFLT2EN_FW_8814B BIT(2) -#define BIT_CTRLFLT1EN_FW_8814B BIT(1) -#define BIT_CTRLFLT0EN_FW_8814B BIT(0) +#define BIT_SHIFT_RXFILTER_ACTION_3_8814B 0 +#define BIT_MASK_RXFILTER_ACTION_3_8814B 0xff +#define BIT_RXFILTER_ACTION_3_8814B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3_8814B) \ + << BIT_SHIFT_RXFILTER_ACTION_3_8814B) +#define BITS_RXFILTER_ACTION_3_8814B \ + (BIT_MASK_RXFILTER_ACTION_3_8814B << BIT_SHIFT_RXFILTER_ACTION_3_8814B) +#define BIT_CLEAR_RXFILTER_ACTION_3_8814B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_3_8814B)) +#define BIT_GET_RXFILTER_ACTION_3_8814B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8814B) & \ + BIT_MASK_RXFILTER_ACTION_3_8814B) +#define BIT_SET_RXFILTER_ACTION_3_8814B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3_8814B(x) | BIT_RXFILTER_ACTION_3_8814B(v)) /* 2 REG_RXFLTMAP3_8814B (RX FILTER MAP GROUP 3) */ #define BIT_MGTFLT15EN_FW_8814B BIT(15) @@ -9287,25 +21681,25 @@ #define BIT_MGTFLT1EN_FW_8814B BIT(1) #define BIT_MGTFLT0EN_FW_8814B BIT(0) -/* 2 REG_RXFLTMAP6_8814B (RX FILTER MAP GROUP 3) */ -#define BIT_ACTIONFLT15EN_FW_8814B BIT(15) -#define BIT_ACTIONFLT14EN_FW_8814B BIT(14) -#define BIT_ACTIONFLT13EN_FW_8814B BIT(13) -#define BIT_ACTIONFLT12EN_FW_8814B BIT(12) -#define BIT_ACTIONFLT11EN_FW_8814B BIT(11) -#define BIT_ACTIONFLT10EN_FW_8814B BIT(10) -#define BIT_ACTIONFLT9EN_FW_8814B BIT(9) -#define BIT_ACTIONFLT8EN_FW_8814B BIT(8) -#define BIT_ACTIONFLT7EN_FW_8814B BIT(7) -#define BIT_ACTIONFLT6EN_FW_8814B BIT(6) -#define BIT_ACTIONFLT5EN_FW_8814B BIT(5) -#define BIT_ACTIONFLT4EN_FW_8814B BIT(4) -#define BIT_ACTIONFLT3EN_FW_8814B BIT(3) -#define BIT_ACTIONFLT2EN_FW_8814B BIT(2) -#define BIT_ACTIONFLT1EN_FW_8814B BIT(1) -#define BIT_ACTIONFLT0EN_FW_8814B BIT(0) +/* 2 REG_RXFLTMAP4_8814B (RX FILTER MAP GROUP 4) */ +#define BIT_CTRLFLT15EN_FW_8814B BIT(15) +#define BIT_CTRLFLT14EN_FW_8814B BIT(14) +#define BIT_CTRLFLT13EN_FW_8814B BIT(13) +#define BIT_CTRLFLT12EN_FW_8814B BIT(12) +#define BIT_CTRLFLT11EN_FW_8814B BIT(11) +#define BIT_CTRLFLT10EN_FW_8814B BIT(10) +#define BIT_CTRLFLT9EN_FW_8814B BIT(9) +#define BIT_CTRLFLT8EN_FW_8814B BIT(8) +#define BIT_CTRLFLT7EN_FW_8814B BIT(7) +#define BIT_CTRLFLT6EN_FW_8814B BIT(6) +#define BIT_CTRLFLT5EN_FW_8814B BIT(5) +#define BIT_CTRLFLT4EN_FW_8814B BIT(4) +#define BIT_CTRLFLT3EN_FW_8814B BIT(3) +#define BIT_CTRLFLT2EN_FW_8814B BIT(2) +#define BIT_CTRLFLT1EN_FW_8814B BIT(1) +#define BIT_CTRLFLT0EN_FW_8814B BIT(0) -/* 2 REG_RXFLTMAP5_8814B (RX FILTER MAP GROUP 3) */ +/* 2 REG_RXFLTMAP5_8814B (RX FILTER MAP GROUP 5) */ #define BIT_DATAFLT15EN_FW_8814B BIT(15) #define BIT_DATAFLT14EN_FW_8814B BIT(14) #define BIT_DATAFLT13EN_FW_8814B BIT(13) @@ -9323,42 +21717,40 @@ #define BIT_DATAFLT1EN_FW_8814B BIT(1) #define BIT_DATAFLT0EN_FW_8814B BIT(0) -/* 2 REG_WMMPS_UAPSD_TID_8814B (WMM POWER SAVE UAPSD TID REGISTER) */ -#define BIT_WMMPS_UAPSD_TID7_8814B BIT(7) -#define BIT_WMMPS_UAPSD_TID6_8814B BIT(6) -#define BIT_WMMPS_UAPSD_TID5_8814B BIT(5) -#define BIT_WMMPS_UAPSD_TID4_8814B BIT(4) -#define BIT_WMMPS_UAPSD_TID3_8814B BIT(3) -#define BIT_WMMPS_UAPSD_TID2_8814B BIT(2) -#define BIT_WMMPS_UAPSD_TID1_8814B BIT(1) -#define BIT_WMMPS_UAPSD_TID0_8814B BIT(0) - -/* 2 REG_PS_RX_INFO_8814B (POWER SAVE RX INFORMATION REGISTER) */ - -#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B 5 -#define BIT_MASK_PORTSEL__PS_RX_INFO_8814B 0x7 -#define BIT_PORTSEL__PS_RX_INFO_8814B(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8814B) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) -#define BIT_GET_PORTSEL__PS_RX_INFO_8814B(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) & BIT_MASK_PORTSEL__PS_RX_INFO_8814B) - - -#define BIT_RXCTRLIN0_8814B BIT(4) -#define BIT_RXMGTIN0_8814B BIT(3) -#define BIT_RXDATAIN2_8814B BIT(2) -#define BIT_RXDATAIN1_8814B BIT(1) -#define BIT_RXDATAIN0_8814B BIT(0) - -/* 2 REG_NAN_RX_TSF_FILTER_8814B(NAN_RX_TSF_ADDRESS_FILTER) */ -#define BIT_CHK_TSF_TA_8814B BIT(2) -#define BIT_CHK_TSF_CBSSID_8814B BIT(1) -#define BIT_CHK_TSF_EN_8814B BIT(0) +/* 2 REG_RXFLTMAP6_8814B (RX FILTER MAP GROUP 6) */ +#define BIT_ACTIONFLT15EN_FW_8814B BIT(15) +#define BIT_ACTIONFLT14EN_FW_8814B BIT(14) +#define BIT_ACTIONFLT13EN_FW_8814B BIT(13) +#define BIT_ACTIONFLT12EN_FW_8814B BIT(12) +#define BIT_ACTIONFLT11EN_FW_8814B BIT(11) +#define BIT_ACTIONFLT10EN_FW_8814B BIT(10) +#define BIT_ACTIONFLT9EN_FW_8814B BIT(9) +#define BIT_ACTIONFLT8EN_FW_8814B BIT(8) +#define BIT_ACTIONFLT7EN_FW_8814B BIT(7) +#define BIT_ACTIONFLT6EN_FW_8814B BIT(6) +#define BIT_ACTIONFLT5EN_FW_8814B BIT(5) +#define BIT_ACTIONFLT4EN_FW_8814B BIT(4) +#define BIT_ACTIONFLT3EN_FW_8814B BIT(3) +#define BIT_ACTIONFLT2EN_FW_8814B BIT(2) +#define BIT_ACTIONFLT1EN_FW_8814B BIT(1) +#define BIT_ACTIONFLT0EN_FW_8814B BIT(0) /* 2 REG_WOW_CTRL_8814B (WAKE ON WLAN CONTROL REGISTER) */ #define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B 6 #define BIT_MASK_PSF_BSSIDSEL_B2B1_8814B 0x3 -#define BIT_PSF_BSSIDSEL_B2B1_8814B(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8814B) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) -#define BIT_GET_PSF_BSSIDSEL_B2B1_8814B(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) & BIT_MASK_PSF_BSSIDSEL_B2B1_8814B) - +#define BIT_PSF_BSSIDSEL_B2B1_8814B(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8814B) \ + << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) +#define BITS_PSF_BSSIDSEL_B2B1_8814B \ + (BIT_MASK_PSF_BSSIDSEL_B2B1_8814B << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8814B(x) \ + ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8814B)) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8814B(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) & \ + BIT_MASK_PSF_BSSIDSEL_B2B1_8814B) +#define BIT_SET_PSF_BSSIDSEL_B2B1_8814B(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8814B(x) | BIT_PSF_BSSIDSEL_B2B1_8814B(v)) #define BIT_WOWHCI_8814B BIT(5) #define BIT_PSF_BSSIDSEL_B0_8814B BIT(4) @@ -9367,22 +21759,47 @@ #define BIT_WOWEN_8814B BIT(1) #define BIT_FORCE_WAKEUP_8814B BIT(0) -/* 2 REG_LPNAV_CTRL_8814B (LOW POWER NAV CONTROL REGISTER) */ -#define BIT_LPNAV_EN_8814B BIT(31) - -#define BIT_SHIFT_LPNAV_EARLY_8814B 16 -#define BIT_MASK_LPNAV_EARLY_8814B 0x7fff -#define BIT_LPNAV_EARLY_8814B(x) (((x) & BIT_MASK_LPNAV_EARLY_8814B) << BIT_SHIFT_LPNAV_EARLY_8814B) -#define BIT_GET_LPNAV_EARLY_8814B(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8814B) & BIT_MASK_LPNAV_EARLY_8814B) +/* 2 REG_NAN_RX_TSF_FILTER_8814B(NAN_RX_TSF_ADDRESS_FILTER) */ +#define BIT_CHK_TSF_TA_8814B BIT(2) +#define BIT_CHK_TSF_CBSSID_8814B BIT(1) +#define BIT_CHK_TSF_EN_8814B BIT(0) +/* 2 REG_PS_RX_INFO_8814B (POWER SAVE RX INFORMATION REGISTER) */ +#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B 5 +#define BIT_MASK_PORTSEL__PS_RX_INFO_8814B 0x7 +#define BIT_PORTSEL__PS_RX_INFO_8814B(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8814B) \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) +#define BITS_PORTSEL__PS_RX_INFO_8814B \ + (BIT_MASK_PORTSEL__PS_RX_INFO_8814B \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8814B(x) \ + ((x) & (~BITS_PORTSEL__PS_RX_INFO_8814B)) +#define BIT_GET_PORTSEL__PS_RX_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) & \ + BIT_MASK_PORTSEL__PS_RX_INFO_8814B) +#define BIT_SET_PORTSEL__PS_RX_INFO_8814B(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO_8814B(x) | \ + BIT_PORTSEL__PS_RX_INFO_8814B(v)) -#define BIT_SHIFT_LPNAV_TH_8814B 0 -#define BIT_MASK_LPNAV_TH_8814B 0xffff -#define BIT_LPNAV_TH_8814B(x) (((x) & BIT_MASK_LPNAV_TH_8814B) << BIT_SHIFT_LPNAV_TH_8814B) -#define BIT_GET_LPNAV_TH_8814B(x) (((x) >> BIT_SHIFT_LPNAV_TH_8814B) & BIT_MASK_LPNAV_TH_8814B) +#define BIT_RXCTRLIN0_8814B BIT(4) +#define BIT_RXMGTIN0_8814B BIT(3) +#define BIT_RXDATAIN2_8814B BIT(2) +#define BIT_RXDATAIN1_8814B BIT(1) +#define BIT_RXDATAIN0_8814B BIT(0) +/* 2 REG_WMMPS_UAPSD_TID_8814B (WMM POWER SAVE UAPSD TID REGISTER) */ +#define BIT_WMMPS_UAPSD_TID7_8814B BIT(7) +#define BIT_WMMPS_UAPSD_TID6_8814B BIT(6) +#define BIT_WMMPS_UAPSD_TID5_8814B BIT(5) +#define BIT_WMMPS_UAPSD_TID4_8814B BIT(4) +#define BIT_WMMPS_UAPSD_TID3_8814B BIT(3) +#define BIT_WMMPS_UAPSD_TID2_8814B BIT(2) +#define BIT_WMMPS_UAPSD_TID1_8814B BIT(1) +#define BIT_WMMPS_UAPSD_TID0_8814B BIT(0) +/* 2 REG_LPNAV_CTRL_8814B (LOW POWER NAV CONTROL REGISTER) */ /* 2 REG_WKFMCAM_CMD_8814B (WAKEUP FRAME CAM COMMAND REGISTER) */ #define BIT_WKFCAM_POLLING_V1_8814B BIT(31) @@ -9391,44 +21808,46 @@ #define BIT_SHIFT_WKFCAM_ADDR_V2_8814B 8 #define BIT_MASK_WKFCAM_ADDR_V2_8814B 0xff -#define BIT_WKFCAM_ADDR_V2_8814B(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8814B) << BIT_SHIFT_WKFCAM_ADDR_V2_8814B) -#define BIT_GET_WKFCAM_ADDR_V2_8814B(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8814B) & BIT_MASK_WKFCAM_ADDR_V2_8814B) - - +#define BIT_WKFCAM_ADDR_V2_8814B(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2_8814B) \ + << BIT_SHIFT_WKFCAM_ADDR_V2_8814B) +#define BITS_WKFCAM_ADDR_V2_8814B \ + (BIT_MASK_WKFCAM_ADDR_V2_8814B << BIT_SHIFT_WKFCAM_ADDR_V2_8814B) +#define BIT_CLEAR_WKFCAM_ADDR_V2_8814B(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8814B)) +#define BIT_GET_WKFCAM_ADDR_V2_8814B(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8814B) & \ + BIT_MASK_WKFCAM_ADDR_V2_8814B) +#define BIT_SET_WKFCAM_ADDR_V2_8814B(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2_8814B(x) | BIT_WKFCAM_ADDR_V2_8814B(v)) #define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B 0 #define BIT_MASK_WKFCAM_CAM_NUM_V1_8814B 0xff -#define BIT_WKFCAM_CAM_NUM_V1_8814B(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8814B) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) -#define BIT_GET_WKFCAM_CAM_NUM_V1_8814B(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) & BIT_MASK_WKFCAM_CAM_NUM_V1_8814B) - - +#define BIT_WKFCAM_CAM_NUM_V1_8814B(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8814B) \ + << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) +#define BITS_WKFCAM_CAM_NUM_V1_8814B \ + (BIT_MASK_WKFCAM_CAM_NUM_V1_8814B << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8814B(x) \ + ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8814B)) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) & \ + BIT_MASK_WKFCAM_CAM_NUM_V1_8814B) +#define BIT_SET_WKFCAM_CAM_NUM_V1_8814B(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8814B(x) | BIT_WKFCAM_CAM_NUM_V1_8814B(v)) /* 2 REG_WKFMCAM_RWD_8814B (WAKEUP FRAME READ/WRITE DATA) */ #define BIT_SHIFT_WKFMCAM_RWD_8814B 0 #define BIT_MASK_WKFMCAM_RWD_8814B 0xffffffffL -#define BIT_WKFMCAM_RWD_8814B(x) (((x) & BIT_MASK_WKFMCAM_RWD_8814B) << BIT_SHIFT_WKFMCAM_RWD_8814B) -#define BIT_GET_WKFMCAM_RWD_8814B(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8814B) & BIT_MASK_WKFMCAM_RWD_8814B) - - - -/* 2 REG_RXFLTMAP1_8814B (RX FILTER MAP GROUP 1) */ -#define BIT_CTRLFLT15EN_8814B BIT(15) -#define BIT_CTRLFLT14EN_8814B BIT(14) -#define BIT_CTRLFLT13EN_8814B BIT(13) -#define BIT_CTRLFLT12EN_8814B BIT(12) -#define BIT_CTRLFLT11EN_8814B BIT(11) -#define BIT_CTRLFLT10EN_8814B BIT(10) -#define BIT_CTRLFLT9EN_8814B BIT(9) -#define BIT_CTRLFLT8EN_8814B BIT(8) -#define BIT_CTRLFLT7EN_8814B BIT(7) -#define BIT_CTRLFLT6EN_8814B BIT(6) -#define BIT_CTRLFLT5EN_8814B BIT(5) -#define BIT_CTRLFLT4EN_8814B BIT(4) -#define BIT_CTRLFLT3EN_8814B BIT(3) -#define BIT_CTRLFLT2EN_8814B BIT(2) -#define BIT_CTRLFLT1EN_8814B BIT(1) -#define BIT_CTRLFLT0EN_8814B BIT(0) +#define BIT_WKFMCAM_RWD_8814B(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD_8814B) << BIT_SHIFT_WKFMCAM_RWD_8814B) +#define BITS_WKFMCAM_RWD_8814B \ + (BIT_MASK_WKFMCAM_RWD_8814B << BIT_SHIFT_WKFMCAM_RWD_8814B) +#define BIT_CLEAR_WKFMCAM_RWD_8814B(x) ((x) & (~BITS_WKFMCAM_RWD_8814B)) +#define BIT_GET_WKFMCAM_RWD_8814B(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD_8814B) & BIT_MASK_WKFMCAM_RWD_8814B) +#define BIT_SET_WKFMCAM_RWD_8814B(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD_8814B(x) | BIT_WKFMCAM_RWD_8814B(v)) /* 2 REG_RXFLTMAP0_8814B (RX FILTER MAP GROUP 0) */ #define BIT_MGTFLT15EN_8814B BIT(15) @@ -9448,9 +21867,25 @@ #define BIT_MGTFLT1EN_8814B BIT(1) #define BIT_MGTFLT0EN_8814B BIT(0) -/* 2 REG_NOT_VALID_8814B */ +/* 2 REG_RXFLTMAP1_8814B (RX FILTER MAP GROUP 1) */ +#define BIT_CTRLFLT15EN_8814B BIT(15) +#define BIT_CTRLFLT14EN_8814B BIT(14) +#define BIT_CTRLFLT13EN_8814B BIT(13) +#define BIT_CTRLFLT12EN_8814B BIT(12) +#define BIT_CTRLFLT11EN_8814B BIT(11) +#define BIT_CTRLFLT10EN_8814B BIT(10) +#define BIT_CTRLFLT9EN_8814B BIT(9) +#define BIT_CTRLFLT8EN_8814B BIT(8) +#define BIT_CTRLFLT7EN_8814B BIT(7) +#define BIT_CTRLFLT6EN_8814B BIT(6) +#define BIT_CTRLFLT5EN_8814B BIT(5) +#define BIT_CTRLFLT4EN_8814B BIT(4) +#define BIT_CTRLFLT3EN_8814B BIT(3) +#define BIT_CTRLFLT2EN_8814B BIT(2) +#define BIT_CTRLFLT1EN_8814B BIT(1) +#define BIT_CTRLFLT0EN_8814B BIT(0) -/* 2 REG_RXFLTMAP_8814B (RX FILTER MAP GROUP 2) */ +/* 2 REG_RXFLTMAP2_8814B (RX FILTER MAP GROUP 2) */ #define BIT_DATAFLT15EN_8814B BIT(15) #define BIT_DATAFLT14EN_8814B BIT(14) #define BIT_DATAFLT13EN_8814B BIT(13) @@ -9468,93 +21903,146 @@ #define BIT_DATAFLT1EN_8814B BIT(1) #define BIT_DATAFLT0EN_8814B BIT(0) +/* 2 REG_RSVD_8814B */ + /* 2 REG_BCN_PSR_RPT_8814B (BEACON PARSER REPORT REGISTER) */ #define BIT_SHIFT_DTIM_CNT_8814B 24 #define BIT_MASK_DTIM_CNT_8814B 0xff -#define BIT_DTIM_CNT_8814B(x) (((x) & BIT_MASK_DTIM_CNT_8814B) << BIT_SHIFT_DTIM_CNT_8814B) -#define BIT_GET_DTIM_CNT_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT_8814B) & BIT_MASK_DTIM_CNT_8814B) - - +#define BIT_DTIM_CNT_8814B(x) \ + (((x) & BIT_MASK_DTIM_CNT_8814B) << BIT_SHIFT_DTIM_CNT_8814B) +#define BITS_DTIM_CNT_8814B \ + (BIT_MASK_DTIM_CNT_8814B << BIT_SHIFT_DTIM_CNT_8814B) +#define BIT_CLEAR_DTIM_CNT_8814B(x) ((x) & (~BITS_DTIM_CNT_8814B)) +#define BIT_GET_DTIM_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT_8814B) & BIT_MASK_DTIM_CNT_8814B) +#define BIT_SET_DTIM_CNT_8814B(x, v) \ + (BIT_CLEAR_DTIM_CNT_8814B(x) | BIT_DTIM_CNT_8814B(v)) #define BIT_SHIFT_DTIM_PERIOD_8814B 16 #define BIT_MASK_DTIM_PERIOD_8814B 0xff -#define BIT_DTIM_PERIOD_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD_8814B) << BIT_SHIFT_DTIM_PERIOD_8814B) -#define BIT_GET_DTIM_PERIOD_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8814B) & BIT_MASK_DTIM_PERIOD_8814B) - +#define BIT_DTIM_PERIOD_8814B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD_8814B) << BIT_SHIFT_DTIM_PERIOD_8814B) +#define BITS_DTIM_PERIOD_8814B \ + (BIT_MASK_DTIM_PERIOD_8814B << BIT_SHIFT_DTIM_PERIOD_8814B) +#define BIT_CLEAR_DTIM_PERIOD_8814B(x) ((x) & (~BITS_DTIM_PERIOD_8814B)) +#define BIT_GET_DTIM_PERIOD_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD_8814B) & BIT_MASK_DTIM_PERIOD_8814B) +#define BIT_SET_DTIM_PERIOD_8814B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD_8814B(x) | BIT_DTIM_PERIOD_8814B(v)) #define BIT_DTIM_8814B BIT(15) #define BIT_TIM_8814B BIT(14) +#define BIT_RPT_VALID_8814B BIT(13) #define BIT_SHIFT_PS_AID_0_8814B 0 #define BIT_MASK_PS_AID_0_8814B 0x7ff -#define BIT_PS_AID_0_8814B(x) (((x) & BIT_MASK_PS_AID_0_8814B) << BIT_SHIFT_PS_AID_0_8814B) -#define BIT_GET_PS_AID_0_8814B(x) (((x) >> BIT_SHIFT_PS_AID_0_8814B) & BIT_MASK_PS_AID_0_8814B) - - +#define BIT_PS_AID_0_8814B(x) \ + (((x) & BIT_MASK_PS_AID_0_8814B) << BIT_SHIFT_PS_AID_0_8814B) +#define BITS_PS_AID_0_8814B \ + (BIT_MASK_PS_AID_0_8814B << BIT_SHIFT_PS_AID_0_8814B) +#define BIT_CLEAR_PS_AID_0_8814B(x) ((x) & (~BITS_PS_AID_0_8814B)) +#define BIT_GET_PS_AID_0_8814B(x) \ + (((x) >> BIT_SHIFT_PS_AID_0_8814B) & BIT_MASK_PS_AID_0_8814B) +#define BIT_SET_PS_AID_0_8814B(x, v) \ + (BIT_CLEAR_PS_AID_0_8814B(x) | BIT_PS_AID_0_8814B(v)) -/* 2 REG_FLC_TRPC_8814B (TIMER OF FLC_RPC) */ -#define BIT_FLC_RPCT_V1_8814B BIT(7) -#define BIT_MODE_8814B BIT(6) +/* 2 REG_FLC_RPC_8814B (FW LPS CONDITION -- RX PKT COUNTER) */ -#define BIT_SHIFT_TRPCD_8814B 0 -#define BIT_MASK_TRPCD_8814B 0x3f -#define BIT_TRPCD_8814B(x) (((x) & BIT_MASK_TRPCD_8814B) << BIT_SHIFT_TRPCD_8814B) -#define BIT_GET_TRPCD_8814B(x) (((x) >> BIT_SHIFT_TRPCD_8814B) & BIT_MASK_TRPCD_8814B) +#define BIT_SHIFT_FLC_RPC_8814B 0 +#define BIT_MASK_FLC_RPC_8814B 0xff +#define BIT_FLC_RPC_8814B(x) \ + (((x) & BIT_MASK_FLC_RPC_8814B) << BIT_SHIFT_FLC_RPC_8814B) +#define BITS_FLC_RPC_8814B (BIT_MASK_FLC_RPC_8814B << BIT_SHIFT_FLC_RPC_8814B) +#define BIT_CLEAR_FLC_RPC_8814B(x) ((x) & (~BITS_FLC_RPC_8814B)) +#define BIT_GET_FLC_RPC_8814B(x) \ + (((x) >> BIT_SHIFT_FLC_RPC_8814B) & BIT_MASK_FLC_RPC_8814B) +#define BIT_SET_FLC_RPC_8814B(x, v) \ + (BIT_CLEAR_FLC_RPC_8814B(x) | BIT_FLC_RPC_8814B(v)) +/* 2 REG_FLC_RPCT_8814B (FLC_RPC THRESHOLD) */ +#define BIT_SHIFT_FLC_RPCT_8814B 0 +#define BIT_MASK_FLC_RPCT_8814B 0xff +#define BIT_FLC_RPCT_8814B(x) \ + (((x) & BIT_MASK_FLC_RPCT_8814B) << BIT_SHIFT_FLC_RPCT_8814B) +#define BITS_FLC_RPCT_8814B \ + (BIT_MASK_FLC_RPCT_8814B << BIT_SHIFT_FLC_RPCT_8814B) +#define BIT_CLEAR_FLC_RPCT_8814B(x) ((x) & (~BITS_FLC_RPCT_8814B)) +#define BIT_GET_FLC_RPCT_8814B(x) \ + (((x) >> BIT_SHIFT_FLC_RPCT_8814B) & BIT_MASK_FLC_RPCT_8814B) +#define BIT_SET_FLC_RPCT_8814B(x, v) \ + (BIT_CLEAR_FLC_RPCT_8814B(x) | BIT_FLC_RPCT_8814B(v)) /* 2 REG_FLC_PTS_8814B (PKT TYPE SELECTION OF FLC_RPC T) */ #define BIT_CMF_8814B BIT(2) #define BIT_CCF_8814B BIT(1) #define BIT_CDF_8814B BIT(0) -/* 2 REG_FLC_RPCT_8814B (FLC_RPC THRESHOLD) */ - -#define BIT_SHIFT_FLC_RPCT_8814B 0 -#define BIT_MASK_FLC_RPCT_8814B 0xff -#define BIT_FLC_RPCT_8814B(x) (((x) & BIT_MASK_FLC_RPCT_8814B) << BIT_SHIFT_FLC_RPCT_8814B) -#define BIT_GET_FLC_RPCT_8814B(x) (((x) >> BIT_SHIFT_FLC_RPCT_8814B) & BIT_MASK_FLC_RPCT_8814B) - - - -/* 2 REG_FLC_RPC_8814B (FW LPS CONDITION -- RX PKT COUNTER) */ - -#define BIT_SHIFT_FLC_RPC_8814B 0 -#define BIT_MASK_FLC_RPC_8814B 0xff -#define BIT_FLC_RPC_8814B(x) (((x) & BIT_MASK_FLC_RPC_8814B) << BIT_SHIFT_FLC_RPC_8814B) -#define BIT_GET_FLC_RPC_8814B(x) (((x) >> BIT_SHIFT_FLC_RPC_8814B) & BIT_MASK_FLC_RPC_8814B) - +/* 2 REG_FLC_TRPC_8814B (TIMER OF FLC_RPC) */ +#define BIT_FLC_RPCT_V1_8814B BIT(7) +#define BIT_MODE_8814B BIT(6) +#define BIT_SHIFT_TRPCD_8814B 0 +#define BIT_MASK_TRPCD_8814B 0x3f +#define BIT_TRPCD_8814B(x) \ + (((x) & BIT_MASK_TRPCD_8814B) << BIT_SHIFT_TRPCD_8814B) +#define BITS_TRPCD_8814B (BIT_MASK_TRPCD_8814B << BIT_SHIFT_TRPCD_8814B) +#define BIT_CLEAR_TRPCD_8814B(x) ((x) & (~BITS_TRPCD_8814B)) +#define BIT_GET_TRPCD_8814B(x) \ + (((x) >> BIT_SHIFT_TRPCD_8814B) & BIT_MASK_TRPCD_8814B) +#define BIT_SET_TRPCD_8814B(x, v) \ + (BIT_CLEAR_TRPCD_8814B(x) | BIT_TRPCD_8814B(v)) /* 2 REG_RXPKTMON_CTRL_8814B */ #define BIT_SHIFT_RXBKQPKT_SEQ_8814B 20 #define BIT_MASK_RXBKQPKT_SEQ_8814B 0xf -#define BIT_RXBKQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8814B) << BIT_SHIFT_RXBKQPKT_SEQ_8814B) -#define BIT_GET_RXBKQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8814B) & BIT_MASK_RXBKQPKT_SEQ_8814B) - - +#define BIT_RXBKQPKT_SEQ_8814B(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ_8814B) << BIT_SHIFT_RXBKQPKT_SEQ_8814B) +#define BITS_RXBKQPKT_SEQ_8814B \ + (BIT_MASK_RXBKQPKT_SEQ_8814B << BIT_SHIFT_RXBKQPKT_SEQ_8814B) +#define BIT_CLEAR_RXBKQPKT_SEQ_8814B(x) ((x) & (~BITS_RXBKQPKT_SEQ_8814B)) +#define BIT_GET_RXBKQPKT_SEQ_8814B(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8814B) & BIT_MASK_RXBKQPKT_SEQ_8814B) +#define BIT_SET_RXBKQPKT_SEQ_8814B(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ_8814B(x) | BIT_RXBKQPKT_SEQ_8814B(v)) #define BIT_SHIFT_RXBEQPKT_SEQ_8814B 16 #define BIT_MASK_RXBEQPKT_SEQ_8814B 0xf -#define BIT_RXBEQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8814B) << BIT_SHIFT_RXBEQPKT_SEQ_8814B) -#define BIT_GET_RXBEQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8814B) & BIT_MASK_RXBEQPKT_SEQ_8814B) - - +#define BIT_RXBEQPKT_SEQ_8814B(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ_8814B) << BIT_SHIFT_RXBEQPKT_SEQ_8814B) +#define BITS_RXBEQPKT_SEQ_8814B \ + (BIT_MASK_RXBEQPKT_SEQ_8814B << BIT_SHIFT_RXBEQPKT_SEQ_8814B) +#define BIT_CLEAR_RXBEQPKT_SEQ_8814B(x) ((x) & (~BITS_RXBEQPKT_SEQ_8814B)) +#define BIT_GET_RXBEQPKT_SEQ_8814B(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8814B) & BIT_MASK_RXBEQPKT_SEQ_8814B) +#define BIT_SET_RXBEQPKT_SEQ_8814B(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ_8814B(x) | BIT_RXBEQPKT_SEQ_8814B(v)) #define BIT_SHIFT_RXVIQPKT_SEQ_8814B 12 #define BIT_MASK_RXVIQPKT_SEQ_8814B 0xf -#define BIT_RXVIQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8814B) << BIT_SHIFT_RXVIQPKT_SEQ_8814B) -#define BIT_GET_RXVIQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8814B) & BIT_MASK_RXVIQPKT_SEQ_8814B) - - +#define BIT_RXVIQPKT_SEQ_8814B(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ_8814B) << BIT_SHIFT_RXVIQPKT_SEQ_8814B) +#define BITS_RXVIQPKT_SEQ_8814B \ + (BIT_MASK_RXVIQPKT_SEQ_8814B << BIT_SHIFT_RXVIQPKT_SEQ_8814B) +#define BIT_CLEAR_RXVIQPKT_SEQ_8814B(x) ((x) & (~BITS_RXVIQPKT_SEQ_8814B)) +#define BIT_GET_RXVIQPKT_SEQ_8814B(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8814B) & BIT_MASK_RXVIQPKT_SEQ_8814B) +#define BIT_SET_RXVIQPKT_SEQ_8814B(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ_8814B(x) | BIT_RXVIQPKT_SEQ_8814B(v)) #define BIT_SHIFT_RXVOQPKT_SEQ_8814B 8 #define BIT_MASK_RXVOQPKT_SEQ_8814B 0xf -#define BIT_RXVOQPKT_SEQ_8814B(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8814B) << BIT_SHIFT_RXVOQPKT_SEQ_8814B) -#define BIT_GET_RXVOQPKT_SEQ_8814B(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8814B) & BIT_MASK_RXVOQPKT_SEQ_8814B) - +#define BIT_RXVOQPKT_SEQ_8814B(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ_8814B) << BIT_SHIFT_RXVOQPKT_SEQ_8814B) +#define BITS_RXVOQPKT_SEQ_8814B \ + (BIT_MASK_RXVOQPKT_SEQ_8814B << BIT_SHIFT_RXVOQPKT_SEQ_8814B) +#define BIT_CLEAR_RXVOQPKT_SEQ_8814B(x) ((x) & (~BITS_RXVOQPKT_SEQ_8814B)) +#define BIT_GET_RXVOQPKT_SEQ_8814B(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8814B) & BIT_MASK_RXVOQPKT_SEQ_8814B) +#define BIT_SET_RXVOQPKT_SEQ_8814B(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ_8814B(x) | BIT_RXVOQPKT_SEQ_8814B(v)) #define BIT_RXBKQPKT_ERR_8814B BIT(7) #define BIT_RXBEQPKT_ERR_8814B BIT(6) @@ -9568,29 +22056,54 @@ #define BIT_SHIFT_STATE_SEL_8814B 24 #define BIT_MASK_STATE_SEL_8814B 0x1f -#define BIT_STATE_SEL_8814B(x) (((x) & BIT_MASK_STATE_SEL_8814B) << BIT_SHIFT_STATE_SEL_8814B) -#define BIT_GET_STATE_SEL_8814B(x) (((x) >> BIT_SHIFT_STATE_SEL_8814B) & BIT_MASK_STATE_SEL_8814B) - - +#define BIT_STATE_SEL_8814B(x) \ + (((x) & BIT_MASK_STATE_SEL_8814B) << BIT_SHIFT_STATE_SEL_8814B) +#define BITS_STATE_SEL_8814B \ + (BIT_MASK_STATE_SEL_8814B << BIT_SHIFT_STATE_SEL_8814B) +#define BIT_CLEAR_STATE_SEL_8814B(x) ((x) & (~BITS_STATE_SEL_8814B)) +#define BIT_GET_STATE_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_STATE_SEL_8814B) & BIT_MASK_STATE_SEL_8814B) +#define BIT_SET_STATE_SEL_8814B(x, v) \ + (BIT_CLEAR_STATE_SEL_8814B(x) | BIT_STATE_SEL_8814B(v)) #define BIT_SHIFT_STATE_INFO_8814B 8 #define BIT_MASK_STATE_INFO_8814B 0xff -#define BIT_STATE_INFO_8814B(x) (((x) & BIT_MASK_STATE_INFO_8814B) << BIT_SHIFT_STATE_INFO_8814B) -#define BIT_GET_STATE_INFO_8814B(x) (((x) >> BIT_SHIFT_STATE_INFO_8814B) & BIT_MASK_STATE_INFO_8814B) - +#define BIT_STATE_INFO_8814B(x) \ + (((x) & BIT_MASK_STATE_INFO_8814B) << BIT_SHIFT_STATE_INFO_8814B) +#define BITS_STATE_INFO_8814B \ + (BIT_MASK_STATE_INFO_8814B << BIT_SHIFT_STATE_INFO_8814B) +#define BIT_CLEAR_STATE_INFO_8814B(x) ((x) & (~BITS_STATE_INFO_8814B)) +#define BIT_GET_STATE_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_STATE_INFO_8814B) & BIT_MASK_STATE_INFO_8814B) +#define BIT_SET_STATE_INFO_8814B(x, v) \ + (BIT_CLEAR_STATE_INFO_8814B(x) | BIT_STATE_INFO_8814B(v)) #define BIT_UPD_NXT_STATE_8814B BIT(7) #define BIT_SHIFT_CUR_STATE_8814B 0 #define BIT_MASK_CUR_STATE_8814B 0x7f -#define BIT_CUR_STATE_8814B(x) (((x) & BIT_MASK_CUR_STATE_8814B) << BIT_SHIFT_CUR_STATE_8814B) -#define BIT_GET_CUR_STATE_8814B(x) (((x) >> BIT_SHIFT_CUR_STATE_8814B) & BIT_MASK_CUR_STATE_8814B) - - +#define BIT_CUR_STATE_8814B(x) \ + (((x) & BIT_MASK_CUR_STATE_8814B) << BIT_SHIFT_CUR_STATE_8814B) +#define BITS_CUR_STATE_8814B \ + (BIT_MASK_CUR_STATE_8814B << BIT_SHIFT_CUR_STATE_8814B) +#define BIT_CLEAR_CUR_STATE_8814B(x) ((x) & (~BITS_CUR_STATE_8814B)) +#define BIT_GET_CUR_STATE_8814B(x) \ + (((x) >> BIT_SHIFT_CUR_STATE_8814B) & BIT_MASK_CUR_STATE_8814B) +#define BIT_SET_CUR_STATE_8814B(x, v) \ + (BIT_CLEAR_CUR_STATE_8814B(x) | BIT_CUR_STATE_8814B(v)) /* 2 REG_ERROR_MON_8814B */ +#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC_8814B BIT(23) +#define BIT_CSI_CHKSUM_ERROR_8814B BIT(22) +#define BIT_MACRX_ERR_5_8814B BIT(21) +#define BIT_MACRX_ERR_4_8814B BIT(20) +#define BIT_MACRX_ERR_3_8814B BIT(19) +#define BIT_MACRX_ERR_2_8814B BIT(18) #define BIT_MACRX_ERR_1_8814B BIT(17) #define BIT_MACRX_ERR_0_8814B BIT(16) +#define BIT_WMAC_PRETX_ERRHDL_EN_8814B BIT(15) +#define BIT_MACTX_ERR_5_8814B BIT(5) +#define BIT_MACTX_ERR_4_8814B BIT(4) #define BIT_MACTX_ERR_3_8814B BIT(3) #define BIT_MACTX_ERR_2_8814B BIT(2) #define BIT_MACTX_ERR_1_8814B BIT(1) @@ -9598,147 +22111,271 @@ /* 2 REG_SEARCH_MACID_8814B */ #define BIT_EN_TXRPTBUF_CLK_8814B BIT(31) - -#define BIT_SHIFT_INFO_INDEX_OFFSET_8814B 16 -#define BIT_MASK_INFO_INDEX_OFFSET_8814B 0x1fff -#define BIT_INFO_INDEX_OFFSET_8814B(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8814B) << BIT_SHIFT_INFO_INDEX_OFFSET_8814B) -#define BIT_GET_INFO_INDEX_OFFSET_8814B(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8814B) & BIT_MASK_INFO_INDEX_OFFSET_8814B) - - #define BIT_WMAC_SRCH_FIFOFULL_8814B BIT(15) #define BIT_DIS_INFOSRCH_8814B BIT(14) #define BIT_DISABLE_B0_8814B BIT(13) #define BIT_SHIFT_INFO_ADDR_OFFSET_8814B 0 #define BIT_MASK_INFO_ADDR_OFFSET_8814B 0x1fff -#define BIT_INFO_ADDR_OFFSET_8814B(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8814B) << BIT_SHIFT_INFO_ADDR_OFFSET_8814B) -#define BIT_GET_INFO_ADDR_OFFSET_8814B(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8814B) & BIT_MASK_INFO_ADDR_OFFSET_8814B) - - +#define BIT_INFO_ADDR_OFFSET_8814B(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET_8814B) \ + << BIT_SHIFT_INFO_ADDR_OFFSET_8814B) +#define BITS_INFO_ADDR_OFFSET_8814B \ + (BIT_MASK_INFO_ADDR_OFFSET_8814B << BIT_SHIFT_INFO_ADDR_OFFSET_8814B) +#define BIT_CLEAR_INFO_ADDR_OFFSET_8814B(x) \ + ((x) & (~BITS_INFO_ADDR_OFFSET_8814B)) +#define BIT_GET_INFO_ADDR_OFFSET_8814B(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8814B) & \ + BIT_MASK_INFO_ADDR_OFFSET_8814B) +#define BIT_SET_INFO_ADDR_OFFSET_8814B(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET_8814B(x) | BIT_INFO_ADDR_OFFSET_8814B(v)) /* 2 REG_BT_COEX_TABLE_8814B (BT-COEXISTENCE CONTROL REGISTER) */ -#define BIT_PRI_MASK_RX_RESP_8814B BIT(126) -#define BIT_PRI_MASK_RXOFDM_8814B BIT(125) -#define BIT_PRI_MASK_RXCCK_8814B BIT(124) -#define BIT_SHIFT_PRI_MASK_TXAC_8814B (117 & CPU_OPT_WIDTH) +#define BIT_SHIFT_COEX_TABLE_1_8814B 0 +#define BIT_MASK_COEX_TABLE_1_8814B 0xffffffffL +#define BIT_COEX_TABLE_1_8814B(x) \ + (((x) & BIT_MASK_COEX_TABLE_1_8814B) << BIT_SHIFT_COEX_TABLE_1_8814B) +#define BITS_COEX_TABLE_1_8814B \ + (BIT_MASK_COEX_TABLE_1_8814B << BIT_SHIFT_COEX_TABLE_1_8814B) +#define BIT_CLEAR_COEX_TABLE_1_8814B(x) ((x) & (~BITS_COEX_TABLE_1_8814B)) +#define BIT_GET_COEX_TABLE_1_8814B(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1_8814B) & BIT_MASK_COEX_TABLE_1_8814B) +#define BIT_SET_COEX_TABLE_1_8814B(x, v) \ + (BIT_CLEAR_COEX_TABLE_1_8814B(x) | BIT_COEX_TABLE_1_8814B(v)) + +/* 2 REG_BT_COEX_TABLE2_8814B (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_COEX_TABLE_2_8814B 0 +#define BIT_MASK_COEX_TABLE_2_8814B 0xffffffffL +#define BIT_COEX_TABLE_2_8814B(x) \ + (((x) & BIT_MASK_COEX_TABLE_2_8814B) << BIT_SHIFT_COEX_TABLE_2_8814B) +#define BITS_COEX_TABLE_2_8814B \ + (BIT_MASK_COEX_TABLE_2_8814B << BIT_SHIFT_COEX_TABLE_2_8814B) +#define BIT_CLEAR_COEX_TABLE_2_8814B(x) ((x) & (~BITS_COEX_TABLE_2_8814B)) +#define BIT_GET_COEX_TABLE_2_8814B(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_2_8814B) & BIT_MASK_COEX_TABLE_2_8814B) +#define BIT_SET_COEX_TABLE_2_8814B(x, v) \ + (BIT_CLEAR_COEX_TABLE_2_8814B(x) | BIT_COEX_TABLE_2_8814B(v)) + +/* 2 REG_BT_COEX_BREAK_TABLE_8814B (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_BREAK_TABLE_2_8814B 16 +#define BIT_MASK_BREAK_TABLE_2_8814B 0xffff +#define BIT_BREAK_TABLE_2_8814B(x) \ + (((x) & BIT_MASK_BREAK_TABLE_2_8814B) << BIT_SHIFT_BREAK_TABLE_2_8814B) +#define BITS_BREAK_TABLE_2_8814B \ + (BIT_MASK_BREAK_TABLE_2_8814B << BIT_SHIFT_BREAK_TABLE_2_8814B) +#define BIT_CLEAR_BREAK_TABLE_2_8814B(x) ((x) & (~BITS_BREAK_TABLE_2_8814B)) +#define BIT_GET_BREAK_TABLE_2_8814B(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_2_8814B) & BIT_MASK_BREAK_TABLE_2_8814B) +#define BIT_SET_BREAK_TABLE_2_8814B(x, v) \ + (BIT_CLEAR_BREAK_TABLE_2_8814B(x) | BIT_BREAK_TABLE_2_8814B(v)) + +#define BIT_SHIFT_BREAK_TABLE_1_8814B 0 +#define BIT_MASK_BREAK_TABLE_1_8814B 0xffff +#define BIT_BREAK_TABLE_1_8814B(x) \ + (((x) & BIT_MASK_BREAK_TABLE_1_8814B) << BIT_SHIFT_BREAK_TABLE_1_8814B) +#define BITS_BREAK_TABLE_1_8814B \ + (BIT_MASK_BREAK_TABLE_1_8814B << BIT_SHIFT_BREAK_TABLE_1_8814B) +#define BIT_CLEAR_BREAK_TABLE_1_8814B(x) ((x) & (~BITS_BREAK_TABLE_1_8814B)) +#define BIT_GET_BREAK_TABLE_1_8814B(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_1_8814B) & BIT_MASK_BREAK_TABLE_1_8814B) +#define BIT_SET_BREAK_TABLE_1_8814B(x, v) \ + (BIT_CLEAR_BREAK_TABLE_1_8814B(x) | BIT_BREAK_TABLE_1_8814B(v)) + +/* 2 REG_BT_COEX_TABLE_H_8814B (BT-COEXISTENCE CONTROL REGISTER) */ +#define BIT_PRI_MASK_RX_RESP_V1_8814B BIT(30) +#define BIT_PRI_MASK_RXOFDM_V1_8814B BIT(29) +#define BIT_PRI_MASK_RXCCK_V1_8814B BIT(28) + +#define BIT_SHIFT_PRI_MASK_TXAC_8814B 21 #define BIT_MASK_PRI_MASK_TXAC_8814B 0x7f -#define BIT_PRI_MASK_TXAC_8814B(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8814B) << BIT_SHIFT_PRI_MASK_TXAC_8814B) -#define BIT_GET_PRI_MASK_TXAC_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8814B) & BIT_MASK_PRI_MASK_TXAC_8814B) - - - -#define BIT_SHIFT_PRI_MASK_NAV_8814B (109 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_TXAC_8814B(x) \ + (((x) & BIT_MASK_PRI_MASK_TXAC_8814B) << BIT_SHIFT_PRI_MASK_TXAC_8814B) +#define BITS_PRI_MASK_TXAC_8814B \ + (BIT_MASK_PRI_MASK_TXAC_8814B << BIT_SHIFT_PRI_MASK_TXAC_8814B) +#define BIT_CLEAR_PRI_MASK_TXAC_8814B(x) ((x) & (~BITS_PRI_MASK_TXAC_8814B)) +#define BIT_GET_PRI_MASK_TXAC_8814B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8814B) & BIT_MASK_PRI_MASK_TXAC_8814B) +#define BIT_SET_PRI_MASK_TXAC_8814B(x, v) \ + (BIT_CLEAR_PRI_MASK_TXAC_8814B(x) | BIT_PRI_MASK_TXAC_8814B(v)) + +#define BIT_SHIFT_PRI_MASK_NAV_8814B 13 #define BIT_MASK_PRI_MASK_NAV_8814B 0xff -#define BIT_PRI_MASK_NAV_8814B(x) (((x) & BIT_MASK_PRI_MASK_NAV_8814B) << BIT_SHIFT_PRI_MASK_NAV_8814B) -#define BIT_GET_PRI_MASK_NAV_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8814B) & BIT_MASK_PRI_MASK_NAV_8814B) - - -#define BIT_PRI_MASK_CCK_8814B BIT(108) -#define BIT_PRI_MASK_OFDM_8814B BIT(107) -#define BIT_PRI_MASK_RTY_8814B BIT(106) - -#define BIT_SHIFT_PRI_MASK_NUM_8814B (102 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_NAV_8814B(x) \ + (((x) & BIT_MASK_PRI_MASK_NAV_8814B) << BIT_SHIFT_PRI_MASK_NAV_8814B) +#define BITS_PRI_MASK_NAV_8814B \ + (BIT_MASK_PRI_MASK_NAV_8814B << BIT_SHIFT_PRI_MASK_NAV_8814B) +#define BIT_CLEAR_PRI_MASK_NAV_8814B(x) ((x) & (~BITS_PRI_MASK_NAV_8814B)) +#define BIT_GET_PRI_MASK_NAV_8814B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NAV_8814B) & BIT_MASK_PRI_MASK_NAV_8814B) +#define BIT_SET_PRI_MASK_NAV_8814B(x, v) \ + (BIT_CLEAR_PRI_MASK_NAV_8814B(x) | BIT_PRI_MASK_NAV_8814B(v)) + +#define BIT_PRI_MASK_CCK_V1_8814B BIT(12) +#define BIT_PRI_MASK_OFDM_V1_8814B BIT(11) +#define BIT_PRI_MASK_RTY_V1_8814B BIT(10) + +#define BIT_SHIFT_PRI_MASK_NUM_8814B 6 #define BIT_MASK_PRI_MASK_NUM_8814B 0xf -#define BIT_PRI_MASK_NUM_8814B(x) (((x) & BIT_MASK_PRI_MASK_NUM_8814B) << BIT_SHIFT_PRI_MASK_NUM_8814B) -#define BIT_GET_PRI_MASK_NUM_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8814B) & BIT_MASK_PRI_MASK_NUM_8814B) - - - -#define BIT_SHIFT_PRI_MASK_TYPE_8814B (98 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_NUM_8814B(x) \ + (((x) & BIT_MASK_PRI_MASK_NUM_8814B) << BIT_SHIFT_PRI_MASK_NUM_8814B) +#define BITS_PRI_MASK_NUM_8814B \ + (BIT_MASK_PRI_MASK_NUM_8814B << BIT_SHIFT_PRI_MASK_NUM_8814B) +#define BIT_CLEAR_PRI_MASK_NUM_8814B(x) ((x) & (~BITS_PRI_MASK_NUM_8814B)) +#define BIT_GET_PRI_MASK_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NUM_8814B) & BIT_MASK_PRI_MASK_NUM_8814B) +#define BIT_SET_PRI_MASK_NUM_8814B(x, v) \ + (BIT_CLEAR_PRI_MASK_NUM_8814B(x) | BIT_PRI_MASK_NUM_8814B(v)) + +#define BIT_SHIFT_PRI_MASK_TYPE_8814B 2 #define BIT_MASK_PRI_MASK_TYPE_8814B 0xf -#define BIT_PRI_MASK_TYPE_8814B(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8814B) << BIT_SHIFT_PRI_MASK_TYPE_8814B) -#define BIT_GET_PRI_MASK_TYPE_8814B(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8814B) & BIT_MASK_PRI_MASK_TYPE_8814B) - - -#define BIT_OOB_8814B BIT(97) -#define BIT_ANT_SEL_8814B BIT(96) - -#define BIT_SHIFT_BREAK_TABLE_2_8814B (80 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_2_8814B 0xffff -#define BIT_BREAK_TABLE_2_8814B(x) (((x) & BIT_MASK_BREAK_TABLE_2_8814B) << BIT_SHIFT_BREAK_TABLE_2_8814B) -#define BIT_GET_BREAK_TABLE_2_8814B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8814B) & BIT_MASK_BREAK_TABLE_2_8814B) - - - -#define BIT_SHIFT_BREAK_TABLE_1_8814B (64 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_1_8814B 0xffff -#define BIT_BREAK_TABLE_1_8814B(x) (((x) & BIT_MASK_BREAK_TABLE_1_8814B) << BIT_SHIFT_BREAK_TABLE_1_8814B) -#define BIT_GET_BREAK_TABLE_1_8814B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8814B) & BIT_MASK_BREAK_TABLE_1_8814B) - - - -#define BIT_SHIFT_COEX_TABLE_2_8814B (32 & CPU_OPT_WIDTH) -#define BIT_MASK_COEX_TABLE_2_8814B 0xffffffffL -#define BIT_COEX_TABLE_2_8814B(x) (((x) & BIT_MASK_COEX_TABLE_2_8814B) << BIT_SHIFT_COEX_TABLE_2_8814B) -#define BIT_GET_COEX_TABLE_2_8814B(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8814B) & BIT_MASK_COEX_TABLE_2_8814B) - - - -#define BIT_SHIFT_COEX_TABLE_1_8814B 0 -#define BIT_MASK_COEX_TABLE_1_8814B 0xffffffffL -#define BIT_COEX_TABLE_1_8814B(x) (((x) & BIT_MASK_COEX_TABLE_1_8814B) << BIT_SHIFT_COEX_TABLE_1_8814B) -#define BIT_GET_COEX_TABLE_1_8814B(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8814B) & BIT_MASK_COEX_TABLE_1_8814B) - - +#define BIT_PRI_MASK_TYPE_8814B(x) \ + (((x) & BIT_MASK_PRI_MASK_TYPE_8814B) << BIT_SHIFT_PRI_MASK_TYPE_8814B) +#define BITS_PRI_MASK_TYPE_8814B \ + (BIT_MASK_PRI_MASK_TYPE_8814B << BIT_SHIFT_PRI_MASK_TYPE_8814B) +#define BIT_CLEAR_PRI_MASK_TYPE_8814B(x) ((x) & (~BITS_PRI_MASK_TYPE_8814B)) +#define BIT_GET_PRI_MASK_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8814B) & BIT_MASK_PRI_MASK_TYPE_8814B) +#define BIT_SET_PRI_MASK_TYPE_8814B(x, v) \ + (BIT_CLEAR_PRI_MASK_TYPE_8814B(x) | BIT_PRI_MASK_TYPE_8814B(v)) + +#define BIT_OOB_V1_8814B BIT(1) +#define BIT_ANT_SEL_V1_8814B BIT(0) /* 2 REG_RXCMD_0_8814B */ #define BIT_RXCMD_EN_8814B BIT(31) #define BIT_SHIFT_RXCMD_INFO_8814B 0 #define BIT_MASK_RXCMD_INFO_8814B 0x7fffffffL -#define BIT_RXCMD_INFO_8814B(x) (((x) & BIT_MASK_RXCMD_INFO_8814B) << BIT_SHIFT_RXCMD_INFO_8814B) -#define BIT_GET_RXCMD_INFO_8814B(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8814B) & BIT_MASK_RXCMD_INFO_8814B) - - +#define BIT_RXCMD_INFO_8814B(x) \ + (((x) & BIT_MASK_RXCMD_INFO_8814B) << BIT_SHIFT_RXCMD_INFO_8814B) +#define BITS_RXCMD_INFO_8814B \ + (BIT_MASK_RXCMD_INFO_8814B << BIT_SHIFT_RXCMD_INFO_8814B) +#define BIT_CLEAR_RXCMD_INFO_8814B(x) ((x) & (~BITS_RXCMD_INFO_8814B)) +#define BIT_GET_RXCMD_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO_8814B) & BIT_MASK_RXCMD_INFO_8814B) +#define BIT_SET_RXCMD_INFO_8814B(x, v) \ + (BIT_CLEAR_RXCMD_INFO_8814B(x) | BIT_RXCMD_INFO_8814B(v)) /* 2 REG_RXCMD_1_8814B */ +#define BIT_SHIFT_CSI_RADDR_LATCH_8814B 24 +#define BIT_MASK_CSI_RADDR_LATCH_8814B 0xff +#define BIT_CSI_RADDR_LATCH_8814B(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH_8814B) \ + << BIT_SHIFT_CSI_RADDR_LATCH_8814B) +#define BITS_CSI_RADDR_LATCH_8814B \ + (BIT_MASK_CSI_RADDR_LATCH_8814B << BIT_SHIFT_CSI_RADDR_LATCH_8814B) +#define BIT_CLEAR_CSI_RADDR_LATCH_8814B(x) ((x) & (~BITS_CSI_RADDR_LATCH_8814B)) +#define BIT_GET_CSI_RADDR_LATCH_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_8814B) & \ + BIT_MASK_CSI_RADDR_LATCH_8814B) +#define BIT_SET_CSI_RADDR_LATCH_8814B(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH_8814B(x) | BIT_CSI_RADDR_LATCH_8814B(v)) + +#define BIT_SHIFT_CSI_WADDR_LATCH_8814B 16 +#define BIT_MASK_CSI_WADDR_LATCH_8814B 0xff +#define BIT_CSI_WADDR_LATCH_8814B(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH_8814B) \ + << BIT_SHIFT_CSI_WADDR_LATCH_8814B) +#define BITS_CSI_WADDR_LATCH_8814B \ + (BIT_MASK_CSI_WADDR_LATCH_8814B << BIT_SHIFT_CSI_WADDR_LATCH_8814B) +#define BIT_CLEAR_CSI_WADDR_LATCH_8814B(x) ((x) & (~BITS_CSI_WADDR_LATCH_8814B)) +#define BIT_GET_CSI_WADDR_LATCH_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_8814B) & \ + BIT_MASK_CSI_WADDR_LATCH_8814B) +#define BIT_SET_CSI_WADDR_LATCH_8814B(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH_8814B(x) | BIT_CSI_WADDR_LATCH_8814B(v)) + #define BIT_SHIFT_RXCMD_PRD_8814B 0 #define BIT_MASK_RXCMD_PRD_8814B 0xffff -#define BIT_RXCMD_PRD_8814B(x) (((x) & BIT_MASK_RXCMD_PRD_8814B) << BIT_SHIFT_RXCMD_PRD_8814B) -#define BIT_GET_RXCMD_PRD_8814B(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8814B) & BIT_MASK_RXCMD_PRD_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_RXCMD_PRD_8814B(x) \ + (((x) & BIT_MASK_RXCMD_PRD_8814B) << BIT_SHIFT_RXCMD_PRD_8814B) +#define BITS_RXCMD_PRD_8814B \ + (BIT_MASK_RXCMD_PRD_8814B << BIT_SHIFT_RXCMD_PRD_8814B) +#define BIT_CLEAR_RXCMD_PRD_8814B(x) ((x) & (~BITS_RXCMD_PRD_8814B)) +#define BIT_GET_RXCMD_PRD_8814B(x) \ + (((x) >> BIT_SHIFT_RXCMD_PRD_8814B) & BIT_MASK_RXCMD_PRD_8814B) +#define BIT_SET_RXCMD_PRD_8814B(x, v) \ + (BIT_CLEAR_RXCMD_PRD_8814B(x) | BIT_RXCMD_PRD_8814B(v)) /* 2 REG_WMAC_RESP_TXINFO_8814B (RESPONSE TXINFO REGISTER) */ #define BIT_SHIFT_WMAC_RESP_MFB_8814B 25 #define BIT_MASK_WMAC_RESP_MFB_8814B 0x7f -#define BIT_WMAC_RESP_MFB_8814B(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8814B) << BIT_SHIFT_WMAC_RESP_MFB_8814B) -#define BIT_GET_WMAC_RESP_MFB_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8814B) & BIT_MASK_WMAC_RESP_MFB_8814B) - - +#define BIT_WMAC_RESP_MFB_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB_8814B) << BIT_SHIFT_WMAC_RESP_MFB_8814B) +#define BITS_WMAC_RESP_MFB_8814B \ + (BIT_MASK_WMAC_RESP_MFB_8814B << BIT_SHIFT_WMAC_RESP_MFB_8814B) +#define BIT_CLEAR_WMAC_RESP_MFB_8814B(x) ((x) & (~BITS_WMAC_RESP_MFB_8814B)) +#define BIT_GET_WMAC_RESP_MFB_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8814B) & BIT_MASK_WMAC_RESP_MFB_8814B) +#define BIT_SET_WMAC_RESP_MFB_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB_8814B(x) | BIT_WMAC_RESP_MFB_8814B(v)) #define BIT_SHIFT_WMAC_ANTINF_SEL_8814B 23 #define BIT_MASK_WMAC_ANTINF_SEL_8814B 0x3 -#define BIT_WMAC_ANTINF_SEL_8814B(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8814B) << BIT_SHIFT_WMAC_ANTINF_SEL_8814B) -#define BIT_GET_WMAC_ANTINF_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8814B) & BIT_MASK_WMAC_ANTINF_SEL_8814B) - - +#define BIT_WMAC_ANTINF_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL_8814B) \ + << BIT_SHIFT_WMAC_ANTINF_SEL_8814B) +#define BITS_WMAC_ANTINF_SEL_8814B \ + (BIT_MASK_WMAC_ANTINF_SEL_8814B << BIT_SHIFT_WMAC_ANTINF_SEL_8814B) +#define BIT_CLEAR_WMAC_ANTINF_SEL_8814B(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8814B)) +#define BIT_GET_WMAC_ANTINF_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8814B) & \ + BIT_MASK_WMAC_ANTINF_SEL_8814B) +#define BIT_SET_WMAC_ANTINF_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL_8814B(x) | BIT_WMAC_ANTINF_SEL_8814B(v)) #define BIT_SHIFT_WMAC_ANTSEL_SEL_8814B 21 #define BIT_MASK_WMAC_ANTSEL_SEL_8814B 0x3 -#define BIT_WMAC_ANTSEL_SEL_8814B(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8814B) << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) -#define BIT_GET_WMAC_ANTSEL_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) & BIT_MASK_WMAC_ANTSEL_SEL_8814B) - - - -#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8814B 18 -#define BIT_MASK_R_WMAC_RESP_TXPOWER_8814B 0x7 -#define BIT_R_WMAC_RESP_TXPOWER_8814B(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8814B) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8814B) -#define BIT_GET_R_WMAC_RESP_TXPOWER_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8814B) & BIT_MASK_R_WMAC_RESP_TXPOWER_8814B) - - - -#define BIT_SHIFT_WMAC_RESP_TXANT_8814B 0 -#define BIT_MASK_WMAC_RESP_TXANT_8814B 0x3ffff -#define BIT_WMAC_RESP_TXANT_8814B(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8814B) << BIT_SHIFT_WMAC_RESP_TXANT_8814B) -#define BIT_GET_WMAC_RESP_TXANT_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8814B) & BIT_MASK_WMAC_RESP_TXANT_8814B) - - +#define BIT_WMAC_ANTSEL_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8814B) \ + << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) +#define BITS_WMAC_ANTSEL_SEL_8814B \ + (BIT_MASK_WMAC_ANTSEL_SEL_8814B << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) +#define BIT_CLEAR_WMAC_ANTSEL_SEL_8814B(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8814B)) +#define BIT_GET_WMAC_ANTSEL_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) & \ + BIT_MASK_WMAC_ANTSEL_SEL_8814B) +#define BIT_SET_WMAC_ANTSEL_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL_8814B(x) | BIT_WMAC_ANTSEL_SEL_8814B(v)) + +#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B 18 +#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B 0x3 +#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) +#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B \ + (BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) +#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) \ + ((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)) +#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) & \ + BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) +#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) | \ + BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(v)) + +#define BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B 6 +#define BIT_MASK_WMAC_RESP_TXANT_V1_8814B 0xfff +#define BIT_WMAC_RESP_TXANT_V1_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_V1_8814B) \ + << BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B) +#define BITS_WMAC_RESP_TXANT_V1_8814B \ + (BIT_MASK_WMAC_RESP_TXANT_V1_8814B \ + << BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B) +#define BIT_CLEAR_WMAC_RESP_TXANT_V1_8814B(x) \ + ((x) & (~BITS_WMAC_RESP_TXANT_V1_8814B)) +#define BIT_GET_WMAC_RESP_TXANT_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B) & \ + BIT_MASK_WMAC_RESP_TXANT_V1_8814B) +#define BIT_SET_WMAC_RESP_TXANT_V1_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_V1_8814B(x) | \ + BIT_WMAC_RESP_TXANT_V1_8814B(v)) /* 2 REG_BBPSF_CTRL_8814B */ #define BIT_CTL_IDLE_CLR_CSI_RPT_8814B BIT(31) @@ -9746,289 +22383,1021 @@ #define BIT_SHIFT_WMAC_CSI_RATE_8814B 24 #define BIT_MASK_WMAC_CSI_RATE_8814B 0x3f -#define BIT_WMAC_CSI_RATE_8814B(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8814B) << BIT_SHIFT_WMAC_CSI_RATE_8814B) -#define BIT_GET_WMAC_CSI_RATE_8814B(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8814B) & BIT_MASK_WMAC_CSI_RATE_8814B) - - +#define BIT_WMAC_CSI_RATE_8814B(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE_8814B) << BIT_SHIFT_WMAC_CSI_RATE_8814B) +#define BITS_WMAC_CSI_RATE_8814B \ + (BIT_MASK_WMAC_CSI_RATE_8814B << BIT_SHIFT_WMAC_CSI_RATE_8814B) +#define BIT_CLEAR_WMAC_CSI_RATE_8814B(x) ((x) & (~BITS_WMAC_CSI_RATE_8814B)) +#define BIT_GET_WMAC_CSI_RATE_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8814B) & BIT_MASK_WMAC_CSI_RATE_8814B) +#define BIT_SET_WMAC_CSI_RATE_8814B(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE_8814B(x) | BIT_WMAC_CSI_RATE_8814B(v)) #define BIT_SHIFT_WMAC_RESP_TXRATE_8814B 16 #define BIT_MASK_WMAC_RESP_TXRATE_8814B 0xff -#define BIT_WMAC_RESP_TXRATE_8814B(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8814B) << BIT_SHIFT_WMAC_RESP_TXRATE_8814B) -#define BIT_GET_WMAC_RESP_TXRATE_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8814B) & BIT_MASK_WMAC_RESP_TXRATE_8814B) - +#define BIT_WMAC_RESP_TXRATE_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE_8814B) \ + << BIT_SHIFT_WMAC_RESP_TXRATE_8814B) +#define BITS_WMAC_RESP_TXRATE_8814B \ + (BIT_MASK_WMAC_RESP_TXRATE_8814B << BIT_SHIFT_WMAC_RESP_TXRATE_8814B) +#define BIT_CLEAR_WMAC_RESP_TXRATE_8814B(x) \ + ((x) & (~BITS_WMAC_RESP_TXRATE_8814B)) +#define BIT_GET_WMAC_RESP_TXRATE_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8814B) & \ + BIT_MASK_WMAC_RESP_TXRATE_8814B) +#define BIT_SET_WMAC_RESP_TXRATE_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE_8814B(x) | BIT_WMAC_RESP_TXRATE_8814B(v)) #define BIT_CSI_FORCE_RATE_EN_8814B BIT(15) #define BIT_SHIFT_CSI_RSC_8814B 13 #define BIT_MASK_CSI_RSC_8814B 0x3 -#define BIT_CSI_RSC_8814B(x) (((x) & BIT_MASK_CSI_RSC_8814B) << BIT_SHIFT_CSI_RSC_8814B) -#define BIT_GET_CSI_RSC_8814B(x) (((x) >> BIT_SHIFT_CSI_RSC_8814B) & BIT_MASK_CSI_RSC_8814B) - +#define BIT_CSI_RSC_8814B(x) \ + (((x) & BIT_MASK_CSI_RSC_8814B) << BIT_SHIFT_CSI_RSC_8814B) +#define BITS_CSI_RSC_8814B (BIT_MASK_CSI_RSC_8814B << BIT_SHIFT_CSI_RSC_8814B) +#define BIT_CLEAR_CSI_RSC_8814B(x) ((x) & (~BITS_CSI_RSC_8814B)) +#define BIT_GET_CSI_RSC_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_RSC_8814B) & BIT_MASK_CSI_RSC_8814B) +#define BIT_SET_CSI_RSC_8814B(x, v) \ + (BIT_CLEAR_CSI_RSC_8814B(x) | BIT_CSI_RSC_8814B(v)) #define BIT_CSI_GID_SEL_8814B BIT(12) #define BIT_RDCSIMD_FLAG_TRIG_SEL_8814B BIT(11) -#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8814B BIT(10) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1_8814B BIT(10) #define BIT_NDPVLD_PROTECT_RDRDY_DIS_8814B BIT(9) #define BIT_RDCSI_EMPTY_APPZERO_8814B BIT(8) -#define BIT_BBPSF_MPDUCHKEN_8814B BIT(5) -#define BIT_BBPSF_MHCHKEN_8814B BIT(4) -#define BIT_BBPSF_ERRCHKEN_8814B BIT(3) - -#define BIT_SHIFT_BBPSF_ERRTHR_8814B 0 -#define BIT_MASK_BBPSF_ERRTHR_8814B 0x7 -#define BIT_BBPSF_ERRTHR_8814B(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8814B) << BIT_SHIFT_BBPSF_ERRTHR_8814B) -#define BIT_GET_BBPSF_ERRTHR_8814B(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8814B) & BIT_MASK_BBPSF_ERRTHR_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_CSI_RATE_FB_EN_8814B BIT(7) +#define BIT_RXFIFO_WRPTR_WO_CHKSUM_8814B BIT(6) /* 2 REG_P2P_RX_BCN_NOA_8814B (P2P RX BEACON NOA REGISTER) */ #define BIT_NOA_PARSER_EN_8814B BIT(15) -#define BIT_BSSID_SEL_8814B BIT(14) + +#define BIT_SHIFT_BSSID_SEL_V1_8814B 12 +#define BIT_MASK_BSSID_SEL_V1_8814B 0x7 +#define BIT_BSSID_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID_SEL_V1_8814B) << BIT_SHIFT_BSSID_SEL_V1_8814B) +#define BITS_BSSID_SEL_V1_8814B \ + (BIT_MASK_BSSID_SEL_V1_8814B << BIT_SHIFT_BSSID_SEL_V1_8814B) +#define BIT_CLEAR_BSSID_SEL_V1_8814B(x) ((x) & (~BITS_BSSID_SEL_V1_8814B)) +#define BIT_GET_BSSID_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID_SEL_V1_8814B) & BIT_MASK_BSSID_SEL_V1_8814B) +#define BIT_SET_BSSID_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID_SEL_V1_8814B(x) | BIT_BSSID_SEL_V1_8814B(v)) #define BIT_SHIFT_P2P_OUI_TYPE_8814B 0 #define BIT_MASK_P2P_OUI_TYPE_8814B 0xff -#define BIT_P2P_OUI_TYPE_8814B(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8814B) << BIT_SHIFT_P2P_OUI_TYPE_8814B) -#define BIT_GET_P2P_OUI_TYPE_8814B(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8814B) & BIT_MASK_P2P_OUI_TYPE_8814B) - +#define BIT_P2P_OUI_TYPE_8814B(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE_8814B) << BIT_SHIFT_P2P_OUI_TYPE_8814B) +#define BITS_P2P_OUI_TYPE_8814B \ + (BIT_MASK_P2P_OUI_TYPE_8814B << BIT_SHIFT_P2P_OUI_TYPE_8814B) +#define BIT_CLEAR_P2P_OUI_TYPE_8814B(x) ((x) & (~BITS_P2P_OUI_TYPE_8814B)) +#define BIT_GET_P2P_OUI_TYPE_8814B(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8814B) & BIT_MASK_P2P_OUI_TYPE_8814B) +#define BIT_SET_P2P_OUI_TYPE_8814B(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE_8814B(x) | BIT_P2P_OUI_TYPE_8814B(v)) +/* 2 REG_RSVD_8814B */ /* 2 REG_ASSOCIATED_BFMER0_INFO_8814B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ -#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B (48 & CPU_OPT_WIDTH) +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8814B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(v)) + +/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8814B */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B 16 #define BIT_MASK_R_WMAC_TXCSI_AID0_8814B 0x1ff -#define BIT_R_WMAC_TXCSI_AID0_8814B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8814B) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) -#define BIT_GET_R_WMAC_TXCSI_AID0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) & BIT_MASK_R_WMAC_TXCSI_AID0_8814B) - - - -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8814B 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8814B 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R0_8814B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8814B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8814B) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8814B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8814B) - - +#define BIT_R_WMAC_TXCSI_AID0_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8814B) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) +#define BITS_R_WMAC_TXCSI_AID0_8814B \ + (BIT_MASK_R_WMAC_TXCSI_AID0_8814B << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) +#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8814B(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID0_8814B)) +#define BIT_GET_R_WMAC_TXCSI_AID0_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) & \ + BIT_MASK_R_WMAC_TXCSI_AID0_8814B) +#define BIT_SET_R_WMAC_TXCSI_AID0_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID0_8814B(x) | BIT_R_WMAC_TXCSI_AID0_8814B(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(v)) /* 2 REG_ASSOCIATED_BFMER1_INFO_8814B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ -#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B (48 & CPU_OPT_WIDTH) +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8814B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(v)) + +/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8814B */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B 16 #define BIT_MASK_R_WMAC_TXCSI_AID1_8814B 0x1ff -#define BIT_R_WMAC_TXCSI_AID1_8814B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8814B) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) -#define BIT_GET_R_WMAC_TXCSI_AID1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) & BIT_MASK_R_WMAC_TXCSI_AID1_8814B) - - - -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8814B 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8814B 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R1_8814B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8814B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8814B) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8814B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8814B) - - - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ - -/* 2 REG_NOT_VALID_8814B */ +#define BIT_R_WMAC_TXCSI_AID1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8814B) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) +#define BITS_R_WMAC_TXCSI_AID1_8814B \ + (BIT_MASK_R_WMAC_TXCSI_AID1_8814B << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) +#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8814B(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID1_8814B)) +#define BIT_GET_R_WMAC_TXCSI_AID1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) & \ + BIT_MASK_R_WMAC_TXCSI_AID1_8814B) +#define BIT_SET_R_WMAC_TXCSI_AID1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID1_8814B(x) | BIT_R_WMAC_TXCSI_AID1_8814B(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW20_8814B (TX CSI REPORT PARAMETER REGISTER) */ #define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B 16 #define BIT_MASK_R_WMAC_BFINFO_20M_1_8814B 0xfff -#define BIT_R_WMAC_BFINFO_20M_1_8814B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8814B) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) -#define BIT_GET_R_WMAC_BFINFO_20M_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) & BIT_MASK_R_WMAC_BFINFO_20M_1_8814B) - - +#define BIT_R_WMAC_BFINFO_20M_1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8814B) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) +#define BITS_R_WMAC_BFINFO_20M_1_8814B \ + (BIT_MASK_R_WMAC_BFINFO_20M_1_8814B \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8814B(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8814B)) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) & \ + BIT_MASK_R_WMAC_BFINFO_20M_1_8814B) +#define BIT_SET_R_WMAC_BFINFO_20M_1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8814B(x) | \ + BIT_R_WMAC_BFINFO_20M_1_8814B(v)) #define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B 0 #define BIT_MASK_R_WMAC_BFINFO_20M_0_8814B 0xfff -#define BIT_R_WMAC_BFINFO_20M_0_8814B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8814B) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) -#define BIT_GET_R_WMAC_BFINFO_20M_0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) & BIT_MASK_R_WMAC_BFINFO_20M_0_8814B) - - +#define BIT_R_WMAC_BFINFO_20M_0_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8814B) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) +#define BITS_R_WMAC_BFINFO_20M_0_8814B \ + (BIT_MASK_R_WMAC_BFINFO_20M_0_8814B \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8814B(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8814B)) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) & \ + BIT_MASK_R_WMAC_BFINFO_20M_0_8814B) +#define BIT_SET_R_WMAC_BFINFO_20M_0_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8814B(x) | \ + BIT_R_WMAC_BFINFO_20M_0_8814B(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW40_8814B (TX CSI REPORT PARAMETER_BW40 REGISTER) */ -#define BIT_SHIFT_WMAC_RESP_ANTCD_8814B 0 -#define BIT_MASK_WMAC_RESP_ANTCD_8814B 0xf -#define BIT_WMAC_RESP_ANTCD_8814B(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8814B) << BIT_SHIFT_WMAC_RESP_ANTCD_8814B) -#define BIT_GET_WMAC_RESP_ANTCD_8814B(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8814B) & BIT_MASK_WMAC_RESP_ANTCD_8814B) - +#define BIT_SHIFT_WMAC_RESP_ANTD_8814B 12 +#define BIT_MASK_WMAC_RESP_ANTD_8814B 0xf +#define BIT_WMAC_RESP_ANTD_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTD_8814B) \ + << BIT_SHIFT_WMAC_RESP_ANTD_8814B) +#define BITS_WMAC_RESP_ANTD_8814B \ + (BIT_MASK_WMAC_RESP_ANTD_8814B << BIT_SHIFT_WMAC_RESP_ANTD_8814B) +#define BIT_CLEAR_WMAC_RESP_ANTD_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTD_8814B)) +#define BIT_GET_WMAC_RESP_ANTD_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTD_8814B) & \ + BIT_MASK_WMAC_RESP_ANTD_8814B) +#define BIT_SET_WMAC_RESP_ANTD_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTD_8814B(x) | BIT_WMAC_RESP_ANTD_8814B(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTC_8814B 8 +#define BIT_MASK_WMAC_RESP_ANTC_8814B 0xf +#define BIT_WMAC_RESP_ANTC_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTC_8814B) \ + << BIT_SHIFT_WMAC_RESP_ANTC_8814B) +#define BITS_WMAC_RESP_ANTC_8814B \ + (BIT_MASK_WMAC_RESP_ANTC_8814B << BIT_SHIFT_WMAC_RESP_ANTC_8814B) +#define BIT_CLEAR_WMAC_RESP_ANTC_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTC_8814B)) +#define BIT_GET_WMAC_RESP_ANTC_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTC_8814B) & \ + BIT_MASK_WMAC_RESP_ANTC_8814B) +#define BIT_SET_WMAC_RESP_ANTC_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTC_8814B(x) | BIT_WMAC_RESP_ANTC_8814B(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTB_8814B 4 +#define BIT_MASK_WMAC_RESP_ANTB_8814B 0xf +#define BIT_WMAC_RESP_ANTB_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTB_8814B) \ + << BIT_SHIFT_WMAC_RESP_ANTB_8814B) +#define BITS_WMAC_RESP_ANTB_8814B \ + (BIT_MASK_WMAC_RESP_ANTB_8814B << BIT_SHIFT_WMAC_RESP_ANTB_8814B) +#define BIT_CLEAR_WMAC_RESP_ANTB_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTB_8814B)) +#define BIT_GET_WMAC_RESP_ANTB_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTB_8814B) & \ + BIT_MASK_WMAC_RESP_ANTB_8814B) +#define BIT_SET_WMAC_RESP_ANTB_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTB_8814B(x) | BIT_WMAC_RESP_ANTB_8814B(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTA_8814B 0 +#define BIT_MASK_WMAC_RESP_ANTA_8814B 0xf +#define BIT_WMAC_RESP_ANTA_8814B(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTA_8814B) \ + << BIT_SHIFT_WMAC_RESP_ANTA_8814B) +#define BITS_WMAC_RESP_ANTA_8814B \ + (BIT_MASK_WMAC_RESP_ANTA_8814B << BIT_SHIFT_WMAC_RESP_ANTA_8814B) +#define BIT_CLEAR_WMAC_RESP_ANTA_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTA_8814B)) +#define BIT_GET_WMAC_RESP_ANTA_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTA_8814B) & \ + BIT_MASK_WMAC_RESP_ANTA_8814B) +#define BIT_SET_WMAC_RESP_ANTA_8814B(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTA_8814B(x) | BIT_WMAC_RESP_ANTA_8814B(v)) - -/* 2 REG_TX_CSI_RPT_PARAM_BW80_8814B (TX CSI REPORT PARAMETER_BW80 REGISTER) */ +/* 2 REG_RSVD_8814B */ /* 2 REG_BCN_PSR_RPT2_8814B (BEACON PARSER REPORT REGISTER2) */ #define BIT_SHIFT_DTIM_CNT2_8814B 24 #define BIT_MASK_DTIM_CNT2_8814B 0xff -#define BIT_DTIM_CNT2_8814B(x) (((x) & BIT_MASK_DTIM_CNT2_8814B) << BIT_SHIFT_DTIM_CNT2_8814B) -#define BIT_GET_DTIM_CNT2_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8814B) & BIT_MASK_DTIM_CNT2_8814B) - - +#define BIT_DTIM_CNT2_8814B(x) \ + (((x) & BIT_MASK_DTIM_CNT2_8814B) << BIT_SHIFT_DTIM_CNT2_8814B) +#define BITS_DTIM_CNT2_8814B \ + (BIT_MASK_DTIM_CNT2_8814B << BIT_SHIFT_DTIM_CNT2_8814B) +#define BIT_CLEAR_DTIM_CNT2_8814B(x) ((x) & (~BITS_DTIM_CNT2_8814B)) +#define BIT_GET_DTIM_CNT2_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT2_8814B) & BIT_MASK_DTIM_CNT2_8814B) +#define BIT_SET_DTIM_CNT2_8814B(x, v) \ + (BIT_CLEAR_DTIM_CNT2_8814B(x) | BIT_DTIM_CNT2_8814B(v)) #define BIT_SHIFT_DTIM_PERIOD2_8814B 16 #define BIT_MASK_DTIM_PERIOD2_8814B 0xff -#define BIT_DTIM_PERIOD2_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD2_8814B) << BIT_SHIFT_DTIM_PERIOD2_8814B) -#define BIT_GET_DTIM_PERIOD2_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8814B) & BIT_MASK_DTIM_PERIOD2_8814B) - +#define BIT_DTIM_PERIOD2_8814B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2_8814B) << BIT_SHIFT_DTIM_PERIOD2_8814B) +#define BITS_DTIM_PERIOD2_8814B \ + (BIT_MASK_DTIM_PERIOD2_8814B << BIT_SHIFT_DTIM_PERIOD2_8814B) +#define BIT_CLEAR_DTIM_PERIOD2_8814B(x) ((x) & (~BITS_DTIM_PERIOD2_8814B)) +#define BIT_GET_DTIM_PERIOD2_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2_8814B) & BIT_MASK_DTIM_PERIOD2_8814B) +#define BIT_SET_DTIM_PERIOD2_8814B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2_8814B(x) | BIT_DTIM_PERIOD2_8814B(v)) #define BIT_DTIM2_8814B BIT(15) #define BIT_TIM2_8814B BIT(14) +#define BIT_RPT_VALID_8814B BIT(13) #define BIT_SHIFT_PS_AID_2_8814B 0 #define BIT_MASK_PS_AID_2_8814B 0x7ff -#define BIT_PS_AID_2_8814B(x) (((x) & BIT_MASK_PS_AID_2_8814B) << BIT_SHIFT_PS_AID_2_8814B) -#define BIT_GET_PS_AID_2_8814B(x) (((x) >> BIT_SHIFT_PS_AID_2_8814B) & BIT_MASK_PS_AID_2_8814B) - - +#define BIT_PS_AID_2_8814B(x) \ + (((x) & BIT_MASK_PS_AID_2_8814B) << BIT_SHIFT_PS_AID_2_8814B) +#define BITS_PS_AID_2_8814B \ + (BIT_MASK_PS_AID_2_8814B << BIT_SHIFT_PS_AID_2_8814B) +#define BIT_CLEAR_PS_AID_2_8814B(x) ((x) & (~BITS_PS_AID_2_8814B)) +#define BIT_GET_PS_AID_2_8814B(x) \ + (((x) >> BIT_SHIFT_PS_AID_2_8814B) & BIT_MASK_PS_AID_2_8814B) +#define BIT_SET_PS_AID_2_8814B(x, v) \ + (BIT_CLEAR_PS_AID_2_8814B(x) | BIT_PS_AID_2_8814B(v)) /* 2 REG_BCN_PSR_RPT3_8814B (BEACON PARSER REPORT REGISTER3) */ #define BIT_SHIFT_DTIM_CNT3_8814B 24 #define BIT_MASK_DTIM_CNT3_8814B 0xff -#define BIT_DTIM_CNT3_8814B(x) (((x) & BIT_MASK_DTIM_CNT3_8814B) << BIT_SHIFT_DTIM_CNT3_8814B) -#define BIT_GET_DTIM_CNT3_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8814B) & BIT_MASK_DTIM_CNT3_8814B) - - +#define BIT_DTIM_CNT3_8814B(x) \ + (((x) & BIT_MASK_DTIM_CNT3_8814B) << BIT_SHIFT_DTIM_CNT3_8814B) +#define BITS_DTIM_CNT3_8814B \ + (BIT_MASK_DTIM_CNT3_8814B << BIT_SHIFT_DTIM_CNT3_8814B) +#define BIT_CLEAR_DTIM_CNT3_8814B(x) ((x) & (~BITS_DTIM_CNT3_8814B)) +#define BIT_GET_DTIM_CNT3_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT3_8814B) & BIT_MASK_DTIM_CNT3_8814B) +#define BIT_SET_DTIM_CNT3_8814B(x, v) \ + (BIT_CLEAR_DTIM_CNT3_8814B(x) | BIT_DTIM_CNT3_8814B(v)) #define BIT_SHIFT_DTIM_PERIOD3_8814B 16 #define BIT_MASK_DTIM_PERIOD3_8814B 0xff -#define BIT_DTIM_PERIOD3_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD3_8814B) << BIT_SHIFT_DTIM_PERIOD3_8814B) -#define BIT_GET_DTIM_PERIOD3_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8814B) & BIT_MASK_DTIM_PERIOD3_8814B) - +#define BIT_DTIM_PERIOD3_8814B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3_8814B) << BIT_SHIFT_DTIM_PERIOD3_8814B) +#define BITS_DTIM_PERIOD3_8814B \ + (BIT_MASK_DTIM_PERIOD3_8814B << BIT_SHIFT_DTIM_PERIOD3_8814B) +#define BIT_CLEAR_DTIM_PERIOD3_8814B(x) ((x) & (~BITS_DTIM_PERIOD3_8814B)) +#define BIT_GET_DTIM_PERIOD3_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3_8814B) & BIT_MASK_DTIM_PERIOD3_8814B) +#define BIT_SET_DTIM_PERIOD3_8814B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3_8814B(x) | BIT_DTIM_PERIOD3_8814B(v)) #define BIT_DTIM3_8814B BIT(15) #define BIT_TIM3_8814B BIT(14) +#define BIT_RPT_VALID_8814B BIT(13) #define BIT_SHIFT_PS_AID_3_8814B 0 #define BIT_MASK_PS_AID_3_8814B 0x7ff -#define BIT_PS_AID_3_8814B(x) (((x) & BIT_MASK_PS_AID_3_8814B) << BIT_SHIFT_PS_AID_3_8814B) -#define BIT_GET_PS_AID_3_8814B(x) (((x) >> BIT_SHIFT_PS_AID_3_8814B) & BIT_MASK_PS_AID_3_8814B) - - +#define BIT_PS_AID_3_8814B(x) \ + (((x) & BIT_MASK_PS_AID_3_8814B) << BIT_SHIFT_PS_AID_3_8814B) +#define BITS_PS_AID_3_8814B \ + (BIT_MASK_PS_AID_3_8814B << BIT_SHIFT_PS_AID_3_8814B) +#define BIT_CLEAR_PS_AID_3_8814B(x) ((x) & (~BITS_PS_AID_3_8814B)) +#define BIT_GET_PS_AID_3_8814B(x) \ + (((x) >> BIT_SHIFT_PS_AID_3_8814B) & BIT_MASK_PS_AID_3_8814B) +#define BIT_SET_PS_AID_3_8814B(x, v) \ + (BIT_CLEAR_PS_AID_3_8814B(x) | BIT_PS_AID_3_8814B(v)) /* 2 REG_BCN_PSR_RPT4_8814B (BEACON PARSER REPORT REGISTER4) */ #define BIT_SHIFT_DTIM_CNT4_8814B 24 #define BIT_MASK_DTIM_CNT4_8814B 0xff -#define BIT_DTIM_CNT4_8814B(x) (((x) & BIT_MASK_DTIM_CNT4_8814B) << BIT_SHIFT_DTIM_CNT4_8814B) -#define BIT_GET_DTIM_CNT4_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8814B) & BIT_MASK_DTIM_CNT4_8814B) - - +#define BIT_DTIM_CNT4_8814B(x) \ + (((x) & BIT_MASK_DTIM_CNT4_8814B) << BIT_SHIFT_DTIM_CNT4_8814B) +#define BITS_DTIM_CNT4_8814B \ + (BIT_MASK_DTIM_CNT4_8814B << BIT_SHIFT_DTIM_CNT4_8814B) +#define BIT_CLEAR_DTIM_CNT4_8814B(x) ((x) & (~BITS_DTIM_CNT4_8814B)) +#define BIT_GET_DTIM_CNT4_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT4_8814B) & BIT_MASK_DTIM_CNT4_8814B) +#define BIT_SET_DTIM_CNT4_8814B(x, v) \ + (BIT_CLEAR_DTIM_CNT4_8814B(x) | BIT_DTIM_CNT4_8814B(v)) #define BIT_SHIFT_DTIM_PERIOD4_8814B 16 #define BIT_MASK_DTIM_PERIOD4_8814B 0xff -#define BIT_DTIM_PERIOD4_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD4_8814B) << BIT_SHIFT_DTIM_PERIOD4_8814B) -#define BIT_GET_DTIM_PERIOD4_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8814B) & BIT_MASK_DTIM_PERIOD4_8814B) - +#define BIT_DTIM_PERIOD4_8814B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4_8814B) << BIT_SHIFT_DTIM_PERIOD4_8814B) +#define BITS_DTIM_PERIOD4_8814B \ + (BIT_MASK_DTIM_PERIOD4_8814B << BIT_SHIFT_DTIM_PERIOD4_8814B) +#define BIT_CLEAR_DTIM_PERIOD4_8814B(x) ((x) & (~BITS_DTIM_PERIOD4_8814B)) +#define BIT_GET_DTIM_PERIOD4_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4_8814B) & BIT_MASK_DTIM_PERIOD4_8814B) +#define BIT_SET_DTIM_PERIOD4_8814B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4_8814B(x) | BIT_DTIM_PERIOD4_8814B(v)) #define BIT_DTIM4_8814B BIT(15) #define BIT_TIM4_8814B BIT(14) +#define BIT_RPT_VALID_8814B BIT(13) #define BIT_SHIFT_PS_AID_4_8814B 0 #define BIT_MASK_PS_AID_4_8814B 0x7ff -#define BIT_PS_AID_4_8814B(x) (((x) & BIT_MASK_PS_AID_4_8814B) << BIT_SHIFT_PS_AID_4_8814B) -#define BIT_GET_PS_AID_4_8814B(x) (((x) >> BIT_SHIFT_PS_AID_4_8814B) & BIT_MASK_PS_AID_4_8814B) - - +#define BIT_PS_AID_4_8814B(x) \ + (((x) & BIT_MASK_PS_AID_4_8814B) << BIT_SHIFT_PS_AID_4_8814B) +#define BITS_PS_AID_4_8814B \ + (BIT_MASK_PS_AID_4_8814B << BIT_SHIFT_PS_AID_4_8814B) +#define BIT_CLEAR_PS_AID_4_8814B(x) ((x) & (~BITS_PS_AID_4_8814B)) +#define BIT_GET_PS_AID_4_8814B(x) \ + (((x) >> BIT_SHIFT_PS_AID_4_8814B) & BIT_MASK_PS_AID_4_8814B) +#define BIT_SET_PS_AID_4_8814B(x, v) \ + (BIT_CLEAR_PS_AID_4_8814B(x) | BIT_PS_AID_4_8814B(v)) /* 2 REG_A1_ADDR_MASK_8814B (A1 ADDR MASK REGISTER) */ #define BIT_SHIFT_A1_ADDR_MASK_8814B 0 #define BIT_MASK_A1_ADDR_MASK_8814B 0xffffffffL -#define BIT_A1_ADDR_MASK_8814B(x) (((x) & BIT_MASK_A1_ADDR_MASK_8814B) << BIT_SHIFT_A1_ADDR_MASK_8814B) -#define BIT_GET_A1_ADDR_MASK_8814B(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8814B) & BIT_MASK_A1_ADDR_MASK_8814B) - - +#define BIT_A1_ADDR_MASK_8814B(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK_8814B) << BIT_SHIFT_A1_ADDR_MASK_8814B) +#define BITS_A1_ADDR_MASK_8814B \ + (BIT_MASK_A1_ADDR_MASK_8814B << BIT_SHIFT_A1_ADDR_MASK_8814B) +#define BIT_CLEAR_A1_ADDR_MASK_8814B(x) ((x) & (~BITS_A1_ADDR_MASK_8814B)) +#define BIT_GET_A1_ADDR_MASK_8814B(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK_8814B) & BIT_MASK_A1_ADDR_MASK_8814B) +#define BIT_SET_A1_ADDR_MASK_8814B(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK_8814B(x) | BIT_A1_ADDR_MASK_8814B(v)) + +/* 2 REG_RXPSF_CTRL_8814B */ +#define BIT_RXGCK_FIFOTHR_EN_8814B BIT(28) + +#define BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B 26 +#define BIT_MASK_RXGCK_VHT_FIFOTHR_8814B 0x3 +#define BIT_RXGCK_VHT_FIFOTHR_8814B(x) \ + (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR_8814B) \ + << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B) +#define BITS_RXGCK_VHT_FIFOTHR_8814B \ + (BIT_MASK_RXGCK_VHT_FIFOTHR_8814B << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B) +#define BIT_CLEAR_RXGCK_VHT_FIFOTHR_8814B(x) \ + ((x) & (~BITS_RXGCK_VHT_FIFOTHR_8814B)) +#define BIT_GET_RXGCK_VHT_FIFOTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B) & \ + BIT_MASK_RXGCK_VHT_FIFOTHR_8814B) +#define BIT_SET_RXGCK_VHT_FIFOTHR_8814B(x, v) \ + (BIT_CLEAR_RXGCK_VHT_FIFOTHR_8814B(x) | BIT_RXGCK_VHT_FIFOTHR_8814B(v)) + +#define BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B 24 +#define BIT_MASK_RXGCK_HT_FIFOTHR_8814B 0x3 +#define BIT_RXGCK_HT_FIFOTHR_8814B(x) \ + (((x) & BIT_MASK_RXGCK_HT_FIFOTHR_8814B) \ + << BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B) +#define BITS_RXGCK_HT_FIFOTHR_8814B \ + (BIT_MASK_RXGCK_HT_FIFOTHR_8814B << BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B) +#define BIT_CLEAR_RXGCK_HT_FIFOTHR_8814B(x) \ + ((x) & (~BITS_RXGCK_HT_FIFOTHR_8814B)) +#define BIT_GET_RXGCK_HT_FIFOTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B) & \ + BIT_MASK_RXGCK_HT_FIFOTHR_8814B) +#define BIT_SET_RXGCK_HT_FIFOTHR_8814B(x, v) \ + (BIT_CLEAR_RXGCK_HT_FIFOTHR_8814B(x) | BIT_RXGCK_HT_FIFOTHR_8814B(v)) + +#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B 22 +#define BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B 0x3 +#define BIT_RXGCK_OFDM_FIFOTHR_8814B(x) \ + (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B) \ + << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B) +#define BITS_RXGCK_OFDM_FIFOTHR_8814B \ + (BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B \ + << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B) +#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8814B(x) \ + ((x) & (~BITS_RXGCK_OFDM_FIFOTHR_8814B)) +#define BIT_GET_RXGCK_OFDM_FIFOTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B) & \ + BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B) +#define BIT_SET_RXGCK_OFDM_FIFOTHR_8814B(x, v) \ + (BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8814B(x) | \ + BIT_RXGCK_OFDM_FIFOTHR_8814B(v)) + +#define BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B 20 +#define BIT_MASK_RXGCK_CCK_FIFOTHR_8814B 0x3 +#define BIT_RXGCK_CCK_FIFOTHR_8814B(x) \ + (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR_8814B) \ + << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B) +#define BITS_RXGCK_CCK_FIFOTHR_8814B \ + (BIT_MASK_RXGCK_CCK_FIFOTHR_8814B << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B) +#define BIT_CLEAR_RXGCK_CCK_FIFOTHR_8814B(x) \ + ((x) & (~BITS_RXGCK_CCK_FIFOTHR_8814B)) +#define BIT_GET_RXGCK_CCK_FIFOTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B) & \ + BIT_MASK_RXGCK_CCK_FIFOTHR_8814B) +#define BIT_SET_RXGCK_CCK_FIFOTHR_8814B(x, v) \ + (BIT_CLEAR_RXGCK_CCK_FIFOTHR_8814B(x) | BIT_RXGCK_CCK_FIFOTHR_8814B(v)) + +#define BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B 17 +#define BIT_MASK_RXGCK_ENTRY_DELAY_8814B 0x7 +#define BIT_RXGCK_ENTRY_DELAY_8814B(x) \ + (((x) & BIT_MASK_RXGCK_ENTRY_DELAY_8814B) \ + << BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B) +#define BITS_RXGCK_ENTRY_DELAY_8814B \ + (BIT_MASK_RXGCK_ENTRY_DELAY_8814B << BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B) +#define BIT_CLEAR_RXGCK_ENTRY_DELAY_8814B(x) \ + ((x) & (~BITS_RXGCK_ENTRY_DELAY_8814B)) +#define BIT_GET_RXGCK_ENTRY_DELAY_8814B(x) \ + (((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B) & \ + BIT_MASK_RXGCK_ENTRY_DELAY_8814B) +#define BIT_SET_RXGCK_ENTRY_DELAY_8814B(x, v) \ + (BIT_CLEAR_RXGCK_ENTRY_DELAY_8814B(x) | BIT_RXGCK_ENTRY_DELAY_8814B(v)) + +#define BIT_RXGCK_OFDMCCA_EN_8814B BIT(16) + +#define BIT_SHIFT_RXPSF_PKTLENTHR_8814B 13 +#define BIT_MASK_RXPSF_PKTLENTHR_8814B 0x7 +#define BIT_RXPSF_PKTLENTHR_8814B(x) \ + (((x) & BIT_MASK_RXPSF_PKTLENTHR_8814B) \ + << BIT_SHIFT_RXPSF_PKTLENTHR_8814B) +#define BITS_RXPSF_PKTLENTHR_8814B \ + (BIT_MASK_RXPSF_PKTLENTHR_8814B << BIT_SHIFT_RXPSF_PKTLENTHR_8814B) +#define BIT_CLEAR_RXPSF_PKTLENTHR_8814B(x) ((x) & (~BITS_RXPSF_PKTLENTHR_8814B)) +#define BIT_GET_RXPSF_PKTLENTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXPSF_PKTLENTHR_8814B) & \ + BIT_MASK_RXPSF_PKTLENTHR_8814B) +#define BIT_SET_RXPSF_PKTLENTHR_8814B(x, v) \ + (BIT_CLEAR_RXPSF_PKTLENTHR_8814B(x) | BIT_RXPSF_PKTLENTHR_8814B(v)) + +#define BIT_RXPSF_CTRLEN_8814B BIT(12) +#define BIT_RXPSF_VHTCHKEN_8814B BIT(11) +#define BIT_RXPSF_HTCHKEN_8814B BIT(10) +#define BIT_RXPSF_OFDMCHKEN_8814B BIT(9) +#define BIT_RXPSF_CCKCHKEN_8814B BIT(8) +#define BIT_RXPSF_OFDMRST_8814B BIT(7) +#define BIT_RXPSF_CCKRST_8814B BIT(6) +#define BIT_RXPSF_MHCHKEN_8814B BIT(5) +#define BIT_RXPSF_CONT_ERRCHKEN_8814B BIT(4) +#define BIT_RXPSF_ALL_ERRCHKEN_8814B BIT(3) + +#define BIT_SHIFT_RXPSF_ERRTHR_8814B 0 +#define BIT_MASK_RXPSF_ERRTHR_8814B 0x7 +#define BIT_RXPSF_ERRTHR_8814B(x) \ + (((x) & BIT_MASK_RXPSF_ERRTHR_8814B) << BIT_SHIFT_RXPSF_ERRTHR_8814B) +#define BITS_RXPSF_ERRTHR_8814B \ + (BIT_MASK_RXPSF_ERRTHR_8814B << BIT_SHIFT_RXPSF_ERRTHR_8814B) +#define BIT_CLEAR_RXPSF_ERRTHR_8814B(x) ((x) & (~BITS_RXPSF_ERRTHR_8814B)) +#define BIT_GET_RXPSF_ERRTHR_8814B(x) \ + (((x) >> BIT_SHIFT_RXPSF_ERRTHR_8814B) & BIT_MASK_RXPSF_ERRTHR_8814B) +#define BIT_SET_RXPSF_ERRTHR_8814B(x, v) \ + (BIT_CLEAR_RXPSF_ERRTHR_8814B(x) | BIT_RXPSF_ERRTHR_8814B(v)) + +/* 2 REG_RXPSF_TYPE_CTRL_8814B */ +#define BIT_RXPSF_DATA15EN_8814B BIT(31) +#define BIT_RXPSF_DATA14EN_8814B BIT(30) +#define BIT_RXPSF_DATA13EN_8814B BIT(29) +#define BIT_RXPSF_DATA12EN_8814B BIT(28) +#define BIT_RXPSF_DATA11EN_8814B BIT(27) +#define BIT_RXPSF_DATA10EN_8814B BIT(26) +#define BIT_RXPSF_DATA9EN_8814B BIT(25) +#define BIT_RXPSF_DATA8EN_8814B BIT(24) +#define BIT_RXPSF_DATA7EN_8814B BIT(23) +#define BIT_RXPSF_DATA6EN_8814B BIT(22) +#define BIT_RXPSF_DATA5EN_8814B BIT(21) +#define BIT_RXPSF_DATA4EN_8814B BIT(20) +#define BIT_RXPSF_DATA3EN_8814B BIT(19) +#define BIT_RXPSF_DATA2EN_8814B BIT(18) +#define BIT_RXPSF_DATA1EN_8814B BIT(17) +#define BIT_RXPSF_DATA0EN_8814B BIT(16) +#define BIT_RXPSF_MGT15EN_8814B BIT(15) +#define BIT_RXPSF_MGT14EN_8814B BIT(14) +#define BIT_RXPSF_MGT13EN_8814B BIT(13) +#define BIT_RXPSF_MGT12EN_8814B BIT(12) +#define BIT_RXPSF_MGT11EN_8814B BIT(11) +#define BIT_RXPSF_MGT10EN_8814B BIT(10) +#define BIT_RXPSF_MGT9EN_8814B BIT(9) +#define BIT_RXPSF_MGT8EN_8814B BIT(8) +#define BIT_RXPSF_MGT7EN_8814B BIT(7) +#define BIT_RXPSF_MGT6EN_8814B BIT(6) +#define BIT_RXPSF_MGT5EN_8814B BIT(5) +#define BIT_RXPSF_MGT4EN_8814B BIT(4) +#define BIT_RXPSF_MGT3EN_8814B BIT(3) +#define BIT_RXPSF_MGT2EN_8814B BIT(2) +#define BIT_RXPSF_MGT1EN_8814B BIT(1) +#define BIT_RXPSF_MGT0EN_8814B BIT(0) + +/* 2 REG_CAM_ACCESS_CTRL_8814B */ +#define BIT_INDIRECT_ERR_8814B BIT(6) +#define BIT_DIRECT_ERR_8814B BIT(5) +#define BIT_DIR_ACCESS_EN_RX_BA_8814B BIT(4) +#define BIT_DIR_ACCESS_EN_ADDRCAM_8814B BIT(3) +#define BIT_DIR_ACCESS_EN_KEY_8814B BIT(2) +#define BIT_DIR_ACCESS_EN_WOWLAN_8814B BIT(1) +#define BIT_DIR_ACCESS_EN_FW_FILTER_8814B BIT(0) + +/* 2 REG_CUT_AMSDU_CTRL_8814B */ +#define BIT__CUT_AMSDU_CHKLEN_EN_8814B BIT(31) +#define BIT_EN_CUT_AMSDU_8814B BIT(30) + +#define BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B 16 +#define BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B 0xff +#define BIT_CUT_AMSDU_CHKLEN_L_TH_8814B(x) \ + (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B) \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B) +#define BITS_CUT_AMSDU_CHKLEN_L_TH_8814B \ + (BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B) +#define BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH_8814B(x) \ + ((x) & (~BITS_CUT_AMSDU_CHKLEN_L_TH_8814B)) +#define BIT_GET_CUT_AMSDU_CHKLEN_L_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B) & \ + BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B) +#define BIT_SET_CUT_AMSDU_CHKLEN_L_TH_8814B(x, v) \ + (BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH_8814B(x) | \ + BIT_CUT_AMSDU_CHKLEN_L_TH_8814B(v)) + +#define BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B 0 +#define BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B 0xffff +#define BIT_CUT_AMSDU_CHKLEN_H_TH_8814B(x) \ + (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B) \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B) +#define BITS_CUT_AMSDU_CHKLEN_H_TH_8814B \ + (BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B \ + << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B) +#define BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH_8814B(x) \ + ((x) & (~BITS_CUT_AMSDU_CHKLEN_H_TH_8814B)) +#define BIT_GET_CUT_AMSDU_CHKLEN_H_TH_8814B(x) \ + (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B) & \ + BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B) +#define BIT_SET_CUT_AMSDU_CHKLEN_H_TH_8814B(x, v) \ + (BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH_8814B(x) | \ + BIT_CUT_AMSDU_CHKLEN_H_TH_8814B(v)) /* 2 REG_MACID2_8814B (MAC ID2 REGISTER) */ -#define BIT_SHIFT_MACID2_8814B 0 -#define BIT_MASK_MACID2_8814B 0xffffffffffffL -#define BIT_MACID2_8814B(x) (((x) & BIT_MASK_MACID2_8814B) << BIT_SHIFT_MACID2_8814B) -#define BIT_GET_MACID2_8814B(x) (((x) >> BIT_SHIFT_MACID2_8814B) & BIT_MASK_MACID2_8814B) - - +#define BIT_SHIFT_MACID2_V1_8814B 0 +#define BIT_MASK_MACID2_V1_8814B 0xffffffffL +#define BIT_MACID2_V1_8814B(x) \ + (((x) & BIT_MASK_MACID2_V1_8814B) << BIT_SHIFT_MACID2_V1_8814B) +#define BITS_MACID2_V1_8814B \ + (BIT_MASK_MACID2_V1_8814B << BIT_SHIFT_MACID2_V1_8814B) +#define BIT_CLEAR_MACID2_V1_8814B(x) ((x) & (~BITS_MACID2_V1_8814B)) +#define BIT_GET_MACID2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID2_V1_8814B) & BIT_MASK_MACID2_V1_8814B) +#define BIT_SET_MACID2_V1_8814B(x, v) \ + (BIT_CLEAR_MACID2_V1_8814B(x) | BIT_MACID2_V1_8814B(v)) + +/* 2 REG_MACID2_H_8814B (MAC ID2 REGISTER) */ + +#define BIT_SHIFT_MACID2_H_V1_8814B 0 +#define BIT_MASK_MACID2_H_V1_8814B 0xffff +#define BIT_MACID2_H_V1_8814B(x) \ + (((x) & BIT_MASK_MACID2_H_V1_8814B) << BIT_SHIFT_MACID2_H_V1_8814B) +#define BITS_MACID2_H_V1_8814B \ + (BIT_MASK_MACID2_H_V1_8814B << BIT_SHIFT_MACID2_H_V1_8814B) +#define BIT_CLEAR_MACID2_H_V1_8814B(x) ((x) & (~BITS_MACID2_H_V1_8814B)) +#define BIT_GET_MACID2_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID2_H_V1_8814B) & BIT_MASK_MACID2_H_V1_8814B) +#define BIT_SET_MACID2_H_V1_8814B(x, v) \ + (BIT_CLEAR_MACID2_H_V1_8814B(x) | BIT_MACID2_H_V1_8814B(v)) /* 2 REG_BSSID2_8814B (BSSID2 REGISTER) */ -#define BIT_SHIFT_BSSID2_8814B 0 -#define BIT_MASK_BSSID2_8814B 0xffffffffffffL -#define BIT_BSSID2_8814B(x) (((x) & BIT_MASK_BSSID2_8814B) << BIT_SHIFT_BSSID2_8814B) -#define BIT_GET_BSSID2_8814B(x) (((x) >> BIT_SHIFT_BSSID2_8814B) & BIT_MASK_BSSID2_8814B) - - +#define BIT_SHIFT_BSSID2_V1_8814B 0 +#define BIT_MASK_BSSID2_V1_8814B 0xffffffffL +#define BIT_BSSID2_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID2_V1_8814B) << BIT_SHIFT_BSSID2_V1_8814B) +#define BITS_BSSID2_V1_8814B \ + (BIT_MASK_BSSID2_V1_8814B << BIT_SHIFT_BSSID2_V1_8814B) +#define BIT_CLEAR_BSSID2_V1_8814B(x) ((x) & (~BITS_BSSID2_V1_8814B)) +#define BIT_GET_BSSID2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID2_V1_8814B) & BIT_MASK_BSSID2_V1_8814B) +#define BIT_SET_BSSID2_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID2_V1_8814B(x) | BIT_BSSID2_V1_8814B(v)) + +/* 2 REG_BSSID2_H_8814B (BSSID2 REGISTER) */ + +#define BIT_SHIFT_BSSID2_H_V1_8814B 0 +#define BIT_MASK_BSSID2_H_V1_8814B 0xffff +#define BIT_BSSID2_H_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID2_H_V1_8814B) << BIT_SHIFT_BSSID2_H_V1_8814B) +#define BITS_BSSID2_H_V1_8814B \ + (BIT_MASK_BSSID2_H_V1_8814B << BIT_SHIFT_BSSID2_H_V1_8814B) +#define BIT_CLEAR_BSSID2_H_V1_8814B(x) ((x) & (~BITS_BSSID2_H_V1_8814B)) +#define BIT_GET_BSSID2_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID2_H_V1_8814B) & BIT_MASK_BSSID2_H_V1_8814B) +#define BIT_SET_BSSID2_H_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID2_H_V1_8814B(x) | BIT_BSSID2_H_V1_8814B(v)) /* 2 REG_MACID3_8814B (MAC ID3 REGISTER) */ -#define BIT_SHIFT_MACID3_8814B 0 -#define BIT_MASK_MACID3_8814B 0xffffffffffffL -#define BIT_MACID3_8814B(x) (((x) & BIT_MASK_MACID3_8814B) << BIT_SHIFT_MACID3_8814B) -#define BIT_GET_MACID3_8814B(x) (((x) >> BIT_SHIFT_MACID3_8814B) & BIT_MASK_MACID3_8814B) - - +#define BIT_SHIFT_MACID3_V1_8814B 0 +#define BIT_MASK_MACID3_V1_8814B 0xffffffffL +#define BIT_MACID3_V1_8814B(x) \ + (((x) & BIT_MASK_MACID3_V1_8814B) << BIT_SHIFT_MACID3_V1_8814B) +#define BITS_MACID3_V1_8814B \ + (BIT_MASK_MACID3_V1_8814B << BIT_SHIFT_MACID3_V1_8814B) +#define BIT_CLEAR_MACID3_V1_8814B(x) ((x) & (~BITS_MACID3_V1_8814B)) +#define BIT_GET_MACID3_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID3_V1_8814B) & BIT_MASK_MACID3_V1_8814B) +#define BIT_SET_MACID3_V1_8814B(x, v) \ + (BIT_CLEAR_MACID3_V1_8814B(x) | BIT_MACID3_V1_8814B(v)) + +/* 2 REG_MACID3_H_8814B (MAC ID3 REGISTER) */ + +#define BIT_SHIFT_MACID3_H_V1_8814B 0 +#define BIT_MASK_MACID3_H_V1_8814B 0xffff +#define BIT_MACID3_H_V1_8814B(x) \ + (((x) & BIT_MASK_MACID3_H_V1_8814B) << BIT_SHIFT_MACID3_H_V1_8814B) +#define BITS_MACID3_H_V1_8814B \ + (BIT_MASK_MACID3_H_V1_8814B << BIT_SHIFT_MACID3_H_V1_8814B) +#define BIT_CLEAR_MACID3_H_V1_8814B(x) ((x) & (~BITS_MACID3_H_V1_8814B)) +#define BIT_GET_MACID3_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID3_H_V1_8814B) & BIT_MASK_MACID3_H_V1_8814B) +#define BIT_SET_MACID3_H_V1_8814B(x, v) \ + (BIT_CLEAR_MACID3_H_V1_8814B(x) | BIT_MACID3_H_V1_8814B(v)) /* 2 REG_BSSID3_8814B (BSSID3 REGISTER) */ -#define BIT_SHIFT_BSSID3_8814B 0 -#define BIT_MASK_BSSID3_8814B 0xffffffffffffL -#define BIT_BSSID3_8814B(x) (((x) & BIT_MASK_BSSID3_8814B) << BIT_SHIFT_BSSID3_8814B) -#define BIT_GET_BSSID3_8814B(x) (((x) >> BIT_SHIFT_BSSID3_8814B) & BIT_MASK_BSSID3_8814B) - - +#define BIT_SHIFT_BSSID3_V1_8814B 0 +#define BIT_MASK_BSSID3_V1_8814B 0xffffffffL +#define BIT_BSSID3_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID3_V1_8814B) << BIT_SHIFT_BSSID3_V1_8814B) +#define BITS_BSSID3_V1_8814B \ + (BIT_MASK_BSSID3_V1_8814B << BIT_SHIFT_BSSID3_V1_8814B) +#define BIT_CLEAR_BSSID3_V1_8814B(x) ((x) & (~BITS_BSSID3_V1_8814B)) +#define BIT_GET_BSSID3_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID3_V1_8814B) & BIT_MASK_BSSID3_V1_8814B) +#define BIT_SET_BSSID3_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID3_V1_8814B(x) | BIT_BSSID3_V1_8814B(v)) + +/* 2 REG_BSSID3_H_8814B (BSSID3 REGISTER) */ + +#define BIT_SHIFT_BSSID3_H_V1_8814B 0 +#define BIT_MASK_BSSID3_H_V1_8814B 0xffff +#define BIT_BSSID3_H_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID3_H_V1_8814B) << BIT_SHIFT_BSSID3_H_V1_8814B) +#define BITS_BSSID3_H_V1_8814B \ + (BIT_MASK_BSSID3_H_V1_8814B << BIT_SHIFT_BSSID3_H_V1_8814B) +#define BIT_CLEAR_BSSID3_H_V1_8814B(x) ((x) & (~BITS_BSSID3_H_V1_8814B)) +#define BIT_GET_BSSID3_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID3_H_V1_8814B) & BIT_MASK_BSSID3_H_V1_8814B) +#define BIT_SET_BSSID3_H_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID3_H_V1_8814B(x) | BIT_BSSID3_H_V1_8814B(v)) /* 2 REG_MACID4_8814B (MAC ID4 REGISTER) */ -#define BIT_SHIFT_MACID4_8814B 0 -#define BIT_MASK_MACID4_8814B 0xffffffffffffL -#define BIT_MACID4_8814B(x) (((x) & BIT_MASK_MACID4_8814B) << BIT_SHIFT_MACID4_8814B) -#define BIT_GET_MACID4_8814B(x) (((x) >> BIT_SHIFT_MACID4_8814B) & BIT_MASK_MACID4_8814B) - - +#define BIT_SHIFT_MACID4_V1_8814B 0 +#define BIT_MASK_MACID4_V1_8814B 0xffffffffL +#define BIT_MACID4_V1_8814B(x) \ + (((x) & BIT_MASK_MACID4_V1_8814B) << BIT_SHIFT_MACID4_V1_8814B) +#define BITS_MACID4_V1_8814B \ + (BIT_MASK_MACID4_V1_8814B << BIT_SHIFT_MACID4_V1_8814B) +#define BIT_CLEAR_MACID4_V1_8814B(x) ((x) & (~BITS_MACID4_V1_8814B)) +#define BIT_GET_MACID4_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID4_V1_8814B) & BIT_MASK_MACID4_V1_8814B) +#define BIT_SET_MACID4_V1_8814B(x, v) \ + (BIT_CLEAR_MACID4_V1_8814B(x) | BIT_MACID4_V1_8814B(v)) + +/* 2 REG_MACID4_H_8814B (MAC ID4 REGISTER) */ + +#define BIT_SHIFT_MACID4_H_V1_8814B 0 +#define BIT_MASK_MACID4_H_V1_8814B 0xffff +#define BIT_MACID4_H_V1_8814B(x) \ + (((x) & BIT_MASK_MACID4_H_V1_8814B) << BIT_SHIFT_MACID4_H_V1_8814B) +#define BITS_MACID4_H_V1_8814B \ + (BIT_MASK_MACID4_H_V1_8814B << BIT_SHIFT_MACID4_H_V1_8814B) +#define BIT_CLEAR_MACID4_H_V1_8814B(x) ((x) & (~BITS_MACID4_H_V1_8814B)) +#define BIT_GET_MACID4_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID4_H_V1_8814B) & BIT_MASK_MACID4_H_V1_8814B) +#define BIT_SET_MACID4_H_V1_8814B(x, v) \ + (BIT_CLEAR_MACID4_H_V1_8814B(x) | BIT_MACID4_H_V1_8814B(v)) /* 2 REG_BSSID4_8814B (BSSID4 REGISTER) */ -#define BIT_SHIFT_BSSID4_8814B 0 -#define BIT_MASK_BSSID4_8814B 0xffffffffffffL -#define BIT_BSSID4_8814B(x) (((x) & BIT_MASK_BSSID4_8814B) << BIT_SHIFT_BSSID4_8814B) -#define BIT_GET_BSSID4_8814B(x) (((x) >> BIT_SHIFT_BSSID4_8814B) & BIT_MASK_BSSID4_8814B) - - +#define BIT_SHIFT_BSSID4_V1_8814B 0 +#define BIT_MASK_BSSID4_V1_8814B 0xffffffffL +#define BIT_BSSID4_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID4_V1_8814B) << BIT_SHIFT_BSSID4_V1_8814B) +#define BITS_BSSID4_V1_8814B \ + (BIT_MASK_BSSID4_V1_8814B << BIT_SHIFT_BSSID4_V1_8814B) +#define BIT_CLEAR_BSSID4_V1_8814B(x) ((x) & (~BITS_BSSID4_V1_8814B)) +#define BIT_GET_BSSID4_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID4_V1_8814B) & BIT_MASK_BSSID4_V1_8814B) +#define BIT_SET_BSSID4_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID4_V1_8814B(x) | BIT_BSSID4_V1_8814B(v)) + +/* 2 REG_BSSID4_H_8814B (BSSID4 REGISTER) */ + +#define BIT_SHIFT_BSSID4_H_V1_8814B 0 +#define BIT_MASK_BSSID4_H_V1_8814B 0xffff +#define BIT_BSSID4_H_V1_8814B(x) \ + (((x) & BIT_MASK_BSSID4_H_V1_8814B) << BIT_SHIFT_BSSID4_H_V1_8814B) +#define BITS_BSSID4_H_V1_8814B \ + (BIT_MASK_BSSID4_H_V1_8814B << BIT_SHIFT_BSSID4_H_V1_8814B) +#define BIT_CLEAR_BSSID4_H_V1_8814B(x) ((x) & (~BITS_BSSID4_H_V1_8814B)) +#define BIT_GET_BSSID4_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID4_H_V1_8814B) & BIT_MASK_BSSID4_H_V1_8814B) +#define BIT_SET_BSSID4_H_V1_8814B(x, v) \ + (BIT_CLEAR_BSSID4_H_V1_8814B(x) | BIT_BSSID4_H_V1_8814B(v)) /* 2 REG_NOA_REPORT_8814B */ +#define BIT_SHIFT_NOA_RPT_8814B 0 +#define BIT_MASK_NOA_RPT_8814B 0xffffffffL +#define BIT_NOA_RPT_8814B(x) \ + (((x) & BIT_MASK_NOA_RPT_8814B) << BIT_SHIFT_NOA_RPT_8814B) +#define BITS_NOA_RPT_8814B (BIT_MASK_NOA_RPT_8814B << BIT_SHIFT_NOA_RPT_8814B) +#define BIT_CLEAR_NOA_RPT_8814B(x) ((x) & (~BITS_NOA_RPT_8814B)) +#define BIT_GET_NOA_RPT_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_RPT_8814B) & BIT_MASK_NOA_RPT_8814B) +#define BIT_SET_NOA_RPT_8814B(x, v) \ + (BIT_CLEAR_NOA_RPT_8814B(x) | BIT_NOA_RPT_8814B(v)) + +/* 2 REG_NOA_REPORT_1_8814B */ + +#define BIT_SHIFT_NOA_RPT_1_8814B 0 +#define BIT_MASK_NOA_RPT_1_8814B 0xffffffffL +#define BIT_NOA_RPT_1_8814B(x) \ + (((x) & BIT_MASK_NOA_RPT_1_8814B) << BIT_SHIFT_NOA_RPT_1_8814B) +#define BITS_NOA_RPT_1_8814B \ + (BIT_MASK_NOA_RPT_1_8814B << BIT_SHIFT_NOA_RPT_1_8814B) +#define BIT_CLEAR_NOA_RPT_1_8814B(x) ((x) & (~BITS_NOA_RPT_1_8814B)) +#define BIT_GET_NOA_RPT_1_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_RPT_1_8814B) & BIT_MASK_NOA_RPT_1_8814B) +#define BIT_SET_NOA_RPT_1_8814B(x, v) \ + (BIT_CLEAR_NOA_RPT_1_8814B(x) | BIT_NOA_RPT_1_8814B(v)) + +/* 2 REG_NOA_REPORT_2_8814B */ + +#define BIT_SHIFT_NOA_RPT_2_8814B 0 +#define BIT_MASK_NOA_RPT_2_8814B 0xffffffffL +#define BIT_NOA_RPT_2_8814B(x) \ + (((x) & BIT_MASK_NOA_RPT_2_8814B) << BIT_SHIFT_NOA_RPT_2_8814B) +#define BITS_NOA_RPT_2_8814B \ + (BIT_MASK_NOA_RPT_2_8814B << BIT_SHIFT_NOA_RPT_2_8814B) +#define BIT_CLEAR_NOA_RPT_2_8814B(x) ((x) & (~BITS_NOA_RPT_2_8814B)) +#define BIT_GET_NOA_RPT_2_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_RPT_2_8814B) & BIT_MASK_NOA_RPT_2_8814B) +#define BIT_SET_NOA_RPT_2_8814B(x, v) \ + (BIT_CLEAR_NOA_RPT_2_8814B(x) | BIT_NOA_RPT_2_8814B(v)) + +/* 2 REG_NOA_REPORT_3_8814B */ + +#define BIT_SHIFT_NOA_RPT_3_8814B 0 +#define BIT_MASK_NOA_RPT_3_8814B 0xff +#define BIT_NOA_RPT_3_8814B(x) \ + (((x) & BIT_MASK_NOA_RPT_3_8814B) << BIT_SHIFT_NOA_RPT_3_8814B) +#define BITS_NOA_RPT_3_8814B \ + (BIT_MASK_NOA_RPT_3_8814B << BIT_SHIFT_NOA_RPT_3_8814B) +#define BIT_CLEAR_NOA_RPT_3_8814B(x) ((x) & (~BITS_NOA_RPT_3_8814B)) +#define BIT_GET_NOA_RPT_3_8814B(x) \ + (((x) >> BIT_SHIFT_NOA_RPT_3_8814B) & BIT_MASK_NOA_RPT_3_8814B) +#define BIT_SET_NOA_RPT_3_8814B(x, v) \ + (BIT_CLEAR_NOA_RPT_3_8814B(x) | BIT_NOA_RPT_3_8814B(v)) + /* 2 REG_PWRBIT_SETTING_8814B */ -#define BIT_CLI3_PWRBIT_OW_EN_8814B BIT(7) -#define BIT_CLI3_PWR_ST_8814B BIT(6) -#define BIT_CLI2_PWRBIT_OW_EN_8814B BIT(5) -#define BIT_CLI2_PWR_ST_8814B BIT(4) -#define BIT_CLI1_PWRBIT_OW_EN_8814B BIT(3) -#define BIT_CLI1_PWR_ST_8814B BIT(2) -#define BIT_CLI0_PWRBIT_OW_EN_8814B BIT(1) -#define BIT_CLI0_PWR_ST_8814B BIT(0) - -/* 2 REG_WMAC_MU_BF_OPTION_8814B */ +#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(15) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(14) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(13) +#define BIT_CLI3_PWR_ST_V1_8814B BIT(12) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(11) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(10) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(9) +#define BIT_CLI2_PWR_ST_V1_8814B BIT(8) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(7) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(6) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(5) +#define BIT_CLI1_PWR_ST_V1_8814B BIT(4) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(3) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(2) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(1) +#define BIT_CLI0_PWR_ST_V1_8814B BIT(0) + +/* 2 REG_GENERAL_OPTION_8814B */ +#define BIT_FIX_MSDU_TAIL_WR_8814B BIT(12) +#define BIT_FIX_MSDU_SHIFT_8814B BIT(11) +#define BIT_RXFIFO_GNT_CUT_8814B BIT(8) +#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8814B BIT(5) +#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_8814B BIT(4) +#define BIT_PATTERN_MATCH_FIX_EN_8814B BIT(3) +#define BIT_TXSERV_FIELD_SEL_8814B BIT(2) +#define BIT_RXVHT_LEN_SEL_8814B BIT(1) +#define BIT_RXMIC_PROTECT_EN_8814B BIT(0) + +/* 2 REG_FWPHYFF_RCR_8814B */ +#define BIT_RCR2_AAMSDU_8814B BIT(25) +#define BIT_RCR2_CBSSID_BCN_8814B BIT(24) +#define BIT_RCR2_ACRC32_8814B BIT(23) +#define BIT_RCR2_TA_BCN_8814B BIT(22) +#define BIT_RCR2_CBSSID_DATA_8814B BIT(21) +#define BIT_RCR2_ADD3_8814B BIT(20) +#define BIT_RCR2_AB_8814B BIT(19) +#define BIT_RCR2_AM_8814B BIT(18) +#define BIT_RCR2_APM_8814B BIT(17) +#define BIT_RCR2_AAP_8814B BIT(16) +#define BIT_RCR1_AAMSDU_8814B BIT(9) +#define BIT_RCR1_CBSSID_BCN_8814B BIT(8) +#define BIT_RCR1_ACRC32_8814B BIT(7) +#define BIT_RCR1_TA_BCN_8814B BIT(6) +#define BIT_RCR1_CBSSID_DATA_8814B BIT(5) +#define BIT_RCR1_ADD3_8814B BIT(4) +#define BIT_RCR1_AB_8814B BIT(3) +#define BIT_RCR1_AM_8814B BIT(2) +#define BIT_RCR1_APM_8814B BIT(1) +#define BIT_RCR1_AAP_8814B BIT(0) + +/* 2 REG_ADDRCAM_WRITE_CONTENT_8814B */ + +#define BIT_SHIFT_ADDRCAM_WDATA_8814B 0 +#define BIT_MASK_ADDRCAM_WDATA_8814B 0xffffffffL +#define BIT_ADDRCAM_WDATA_8814B(x) \ + (((x) & BIT_MASK_ADDRCAM_WDATA_8814B) << BIT_SHIFT_ADDRCAM_WDATA_8814B) +#define BITS_ADDRCAM_WDATA_8814B \ + (BIT_MASK_ADDRCAM_WDATA_8814B << BIT_SHIFT_ADDRCAM_WDATA_8814B) +#define BIT_CLEAR_ADDRCAM_WDATA_8814B(x) ((x) & (~BITS_ADDRCAM_WDATA_8814B)) +#define BIT_GET_ADDRCAM_WDATA_8814B(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_WDATA_8814B) & BIT_MASK_ADDRCAM_WDATA_8814B) +#define BIT_SET_ADDRCAM_WDATA_8814B(x, v) \ + (BIT_CLEAR_ADDRCAM_WDATA_8814B(x) | BIT_ADDRCAM_WDATA_8814B(v)) + +/* 2 REG_ADDRCAM_READ_CONTENT_8814B */ + +#define BIT_SHIFT_ADDRCAM_RDATA_8814B 0 +#define BIT_MASK_ADDRCAM_RDATA_8814B 0xffffffffL +#define BIT_ADDRCAM_RDATA_8814B(x) \ + (((x) & BIT_MASK_ADDRCAM_RDATA_8814B) << BIT_SHIFT_ADDRCAM_RDATA_8814B) +#define BITS_ADDRCAM_RDATA_8814B \ + (BIT_MASK_ADDRCAM_RDATA_8814B << BIT_SHIFT_ADDRCAM_RDATA_8814B) +#define BIT_CLEAR_ADDRCAM_RDATA_8814B(x) ((x) & (~BITS_ADDRCAM_RDATA_8814B)) +#define BIT_GET_ADDRCAM_RDATA_8814B(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_RDATA_8814B) & BIT_MASK_ADDRCAM_RDATA_8814B) +#define BIT_SET_ADDRCAM_RDATA_8814B(x, v) \ + (BIT_CLEAR_ADDRCAM_RDATA_8814B(x) | BIT_ADDRCAM_RDATA_8814B(v)) + +/* 2 REG_ADDRCAM_CFG_8814B */ +#define BIT_ADDRCAM_POLL_8814B BIT(31) +#define BIT__ADDRCAM_WT_EN_8814B BIT(30) +#define BIT_CLRADDRCAM_8814B BIT(29) + +#define BIT_SHIFT__ADDRCAM_ADDR_8814B 8 +#define BIT_MASK__ADDRCAM_ADDR_8814B 0x3ff +#define BIT__ADDRCAM_ADDR_8814B(x) \ + (((x) & BIT_MASK__ADDRCAM_ADDR_8814B) << BIT_SHIFT__ADDRCAM_ADDR_8814B) +#define BITS__ADDRCAM_ADDR_8814B \ + (BIT_MASK__ADDRCAM_ADDR_8814B << BIT_SHIFT__ADDRCAM_ADDR_8814B) +#define BIT_CLEAR__ADDRCAM_ADDR_8814B(x) ((x) & (~BITS__ADDRCAM_ADDR_8814B)) +#define BIT_GET__ADDRCAM_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT__ADDRCAM_ADDR_8814B) & BIT_MASK__ADDRCAM_ADDR_8814B) +#define BIT_SET__ADDRCAM_ADDR_8814B(x, v) \ + (BIT_CLEAR__ADDRCAM_ADDR_8814B(x) | BIT__ADDRCAM_ADDR_8814B(v)) + +#define BIT_SHIFT_ADDRCAM_RANGE_8814B 0 +#define BIT_MASK_ADDRCAM_RANGE_8814B 0x7f +#define BIT_ADDRCAM_RANGE_8814B(x) \ + (((x) & BIT_MASK_ADDRCAM_RANGE_8814B) << BIT_SHIFT_ADDRCAM_RANGE_8814B) +#define BITS_ADDRCAM_RANGE_8814B \ + (BIT_MASK_ADDRCAM_RANGE_8814B << BIT_SHIFT_ADDRCAM_RANGE_8814B) +#define BIT_CLEAR_ADDRCAM_RANGE_8814B(x) ((x) & (~BITS_ADDRCAM_RANGE_8814B)) +#define BIT_GET_ADDRCAM_RANGE_8814B(x) \ + (((x) >> BIT_SHIFT_ADDRCAM_RANGE_8814B) & BIT_MASK_ADDRCAM_RANGE_8814B) +#define BIT_SET_ADDRCAM_RANGE_8814B(x, v) \ + (BIT_CLEAR_ADDRCAM_RANGE_8814B(x) | BIT_ADDRCAM_RANGE_8814B(v)) + +/* 2 REG_CSI_RRSR_8814B */ +#define BIT_CSI_LDPC_EN_8814B BIT(29) +#define BIT_CSI_STBC_EN_8814B BIT(28) + +#define BIT_SHIFT_CSI_RRSC_BITMAP_8814B 4 +#define BIT_MASK_CSI_RRSC_BITMAP_8814B 0xffffff +#define BIT_CSI_RRSC_BITMAP_8814B(x) \ + (((x) & BIT_MASK_CSI_RRSC_BITMAP_8814B) \ + << BIT_SHIFT_CSI_RRSC_BITMAP_8814B) +#define BITS_CSI_RRSC_BITMAP_8814B \ + (BIT_MASK_CSI_RRSC_BITMAP_8814B << BIT_SHIFT_CSI_RRSC_BITMAP_8814B) +#define BIT_CLEAR_CSI_RRSC_BITMAP_8814B(x) ((x) & (~BITS_CSI_RRSC_BITMAP_8814B)) +#define BIT_GET_CSI_RRSC_BITMAP_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_RRSC_BITMAP_8814B) & \ + BIT_MASK_CSI_RRSC_BITMAP_8814B) +#define BIT_SET_CSI_RRSC_BITMAP_8814B(x, v) \ + (BIT_CLEAR_CSI_RRSC_BITMAP_8814B(x) | BIT_CSI_RRSC_BITMAP_8814B(v)) + +#define BIT_SHIFT_OFDM_LEN_TH_8814B 0 +#define BIT_MASK_OFDM_LEN_TH_8814B 0xf +#define BIT_OFDM_LEN_TH_8814B(x) \ + (((x) & BIT_MASK_OFDM_LEN_TH_8814B) << BIT_SHIFT_OFDM_LEN_TH_8814B) +#define BITS_OFDM_LEN_TH_8814B \ + (BIT_MASK_OFDM_LEN_TH_8814B << BIT_SHIFT_OFDM_LEN_TH_8814B) +#define BIT_CLEAR_OFDM_LEN_TH_8814B(x) ((x) & (~BITS_OFDM_LEN_TH_8814B)) +#define BIT_GET_OFDM_LEN_TH_8814B(x) \ + (((x) >> BIT_SHIFT_OFDM_LEN_TH_8814B) & BIT_MASK_OFDM_LEN_TH_8814B) +#define BIT_SET_OFDM_LEN_TH_8814B(x, v) \ + (BIT_CLEAR_OFDM_LEN_TH_8814B(x) | BIT_OFDM_LEN_TH_8814B(v)) + +/* 2 REG_MU_BF_OPTION_8814B */ #define BIT_WMAC_RESP_NONSTA1_DIS_8814B BIT(7) #define BIT_WMAC_TXMU_ACKPOLICY_EN_8814B BIT(6) #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B 4 #define BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B 0x3 -#define BIT_WMAC_TXMU_ACKPOLICY_8814B(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) -#define BIT_GET_WMAC_TXMU_ACKPOLICY_8814B(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B) - - +#define BIT_WMAC_TXMU_ACKPOLICY_8814B(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B) \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) +#define BITS_WMAC_TXMU_ACKPOLICY_8814B \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8814B(x) \ + ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8814B)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) & \ + BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B) +#define BIT_SET_WMAC_TXMU_ACKPOLICY_8814B(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8814B(x) | \ + BIT_WMAC_TXMU_ACKPOLICY_8814B(v)) #define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B 1 #define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B 0x7 -#define BIT_WMAC_MU_BFEE_PORT_SEL_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) -#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B) - +#define BIT_WMAC_MU_BFEE_PORT_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) +#define BITS_WMAC_MU_BFEE_PORT_SEL_8814B \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8814B)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8814B(x) | \ + BIT_WMAC_MU_BFEE_PORT_SEL_8814B(v)) #define BIT_WMAC_MU_BFEE_DIS_8814B BIT(0) @@ -10036,37 +23405,42 @@ #define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B 0 #define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B 0xff -#define BIT_WMAC_PAUSE_BB_CLR_TH_8814B(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) -#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8814B(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B) - - - -/* 2 REG_WMAC_MU_ARB_8814B */ -#define BIT_WMAC_ARB_HW_ADAPT_EN_8814B BIT(7) -#define BIT_WMAC_ARB_SW_EN_8814B BIT(6) - -#define BIT_SHIFT_WMAC_ARB_SW_STATE_8814B 0 -#define BIT_MASK_WMAC_ARB_SW_STATE_8814B 0x3f -#define BIT_WMAC_ARB_SW_STATE_8814B(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8814B) << BIT_SHIFT_WMAC_ARB_SW_STATE_8814B) -#define BIT_GET_WMAC_ARB_SW_STATE_8814B(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8814B) & BIT_MASK_WMAC_ARB_SW_STATE_8814B) - - +#define BIT_WMAC_PAUSE_BB_CLR_TH_8814B(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) +#define BITS_WMAC_PAUSE_BB_CLR_TH_8814B \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8814B(x) \ + ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8814B)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8814B(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8814B(x) | \ + BIT_WMAC_PAUSE_BB_CLR_TH_8814B(v)) + +/* 2 REG_WMAC_MULBK_BUF_8814B */ + +#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B 0 +#define BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B 0xff +#define BIT_WMAC_MULBK_PAGE_SIZE_8814B(x) \ + (((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B) \ + << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B) +#define BITS_WMAC_MULBK_PAGE_SIZE_8814B \ + (BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B \ + << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B) +#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8814B(x) \ + ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE_8814B)) +#define BIT_GET_WMAC_MULBK_PAGE_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B) & \ + BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B) +#define BIT_SET_WMAC_MULBK_PAGE_SIZE_8814B(x, v) \ + (BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8814B(x) | \ + BIT_WMAC_MULBK_PAGE_SIZE_8814B(v)) /* 2 REG_WMAC_MU_OPTION_8814B */ - -#define BIT_SHIFT_WMAC_MU_DBGSEL_8814B 5 -#define BIT_MASK_WMAC_MU_DBGSEL_8814B 0x3 -#define BIT_WMAC_MU_DBGSEL_8814B(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8814B) << BIT_SHIFT_WMAC_MU_DBGSEL_8814B) -#define BIT_GET_WMAC_MU_DBGSEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8814B) & BIT_MASK_WMAC_MU_DBGSEL_8814B) - - - -#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8814B 0 -#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8814B 0x1f -#define BIT_WMAC_MU_CPRD_TIMEOUT_8814B(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8814B) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8814B) -#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8814B) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8814B) - - +#define BIT_NOCHK_BFPOLL_BMP_8814B BIT(7) /* 2 REG_WMAC_MU_BF_CTL_8814B */ #define BIT_WMAC_INVLD_BFPRT_CHK_8814B BIT(15) @@ -10074,33 +23448,66 @@ #define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B 12 #define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B 0x3 -#define BIT_WMAC_MU_BFRPTSEG_SEL_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) -#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B) - - +#define BIT_WMAC_MU_BFRPTSEG_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) +#define BITS_WMAC_MU_BFRPTSEG_SEL_8814B \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8814B)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8814B(x) | \ + BIT_WMAC_MU_BFRPTSEG_SEL_8814B(v)) #define BIT_SHIFT_WMAC_MU_BF_MYAID_8814B 0 #define BIT_MASK_WMAC_MU_BF_MYAID_8814B 0xfff -#define BIT_WMAC_MU_BF_MYAID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8814B) << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) -#define BIT_GET_WMAC_MU_BF_MYAID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) & BIT_MASK_WMAC_MU_BF_MYAID_8814B) - - - -/* 2 REG_WMAC_MU_BIT_BFRPT_PARA_8814B */ - -#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8814B 12 -#define BIT_MASK_BFRPT_PARA_USERID_SEL_8814B 0x7 -#define BIT_BFRPT_PARA_USERID_SEL_8814B(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8814B) << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8814B) -#define BIT_GET_BFRPT_PARA_USERID_SEL_8814B(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8814B) & BIT_MASK_BFRPT_PARA_USERID_SEL_8814B) - - - -#define BIT_SHIFT_BFRPT_PARA_8814B 0 -#define BIT_MASK_BFRPT_PARA_8814B 0xfff -#define BIT_BFRPT_PARA_8814B(x) (((x) & BIT_MASK_BFRPT_PARA_8814B) << BIT_SHIFT_BFRPT_PARA_8814B) -#define BIT_GET_BFRPT_PARA_8814B(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8814B) & BIT_MASK_BFRPT_PARA_8814B) - - +#define BIT_WMAC_MU_BF_MYAID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8814B) \ + << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) +#define BITS_WMAC_MU_BF_MYAID_8814B \ + (BIT_MASK_WMAC_MU_BF_MYAID_8814B << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BF_MYAID_8814B)) +#define BIT_GET_WMAC_MU_BF_MYAID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) & \ + BIT_MASK_WMAC_MU_BF_MYAID_8814B) +#define BIT_SET_WMAC_MU_BF_MYAID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID_8814B(x) | BIT_WMAC_MU_BF_MYAID_8814B(v)) + +/* 2 REG_WMAC_MU_BFRPT_PARA_8814B */ + +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B 13 +#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B 0x7 +#define BIT_BFRPT_PARA_USERID_SEL_V1_8814B(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B) +#define BITS_BFRPT_PARA_USERID_SEL_V1_8814B \ + (BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8814B(x) \ + ((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1_8814B)) +#define BIT_GET_BFRPT_PARA_USERID_SEL_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B) +#define BIT_SET_BFRPT_PARA_USERID_SEL_V1_8814B(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8814B(x) | \ + BIT_BFRPT_PARA_USERID_SEL_V1_8814B(v)) + +#define BIT_SHIFT_BFRPT_PARA_V1_8814B 0 +#define BIT_MASK_BFRPT_PARA_V1_8814B 0x1fff +#define BIT_BFRPT_PARA_V1_8814B(x) \ + (((x) & BIT_MASK_BFRPT_PARA_V1_8814B) << BIT_SHIFT_BFRPT_PARA_V1_8814B) +#define BITS_BFRPT_PARA_V1_8814B \ + (BIT_MASK_BFRPT_PARA_V1_8814B << BIT_SHIFT_BFRPT_PARA_V1_8814B) +#define BIT_CLEAR_BFRPT_PARA_V1_8814B(x) ((x) & (~BITS_BFRPT_PARA_V1_8814B)) +#define BIT_GET_BFRPT_PARA_V1_8814B(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_V1_8814B) & BIT_MASK_BFRPT_PARA_V1_8814B) +#define BIT_SET_BFRPT_PARA_V1_8814B(x, v) \ + (BIT_CLEAR_BFRPT_PARA_V1_8814B(x) | BIT_BFRPT_PARA_V1_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B */ #define BIT_STATUS_BFEE2_8814B BIT(10) @@ -10108,10 +23515,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE2_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE2_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE2_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) & BIT_MASK_WMAC_MU_BFEE2_AID_8814B) - - +#define BIT_WMAC_MU_BFEE2_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) +#define BITS_WMAC_MU_BFEE2_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE2_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE2_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE2_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE2_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE2_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID_8814B(x) | BIT_WMAC_MU_BFEE2_AID_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B */ #define BIT_STATUS_BFEE3_8814B BIT(10) @@ -10119,10 +23534,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE3_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE3_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE3_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) & BIT_MASK_WMAC_MU_BFEE3_AID_8814B) - - +#define BIT_WMAC_MU_BFEE3_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) +#define BITS_WMAC_MU_BFEE3_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE3_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE3_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE3_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE3_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE3_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID_8814B(x) | BIT_WMAC_MU_BFEE3_AID_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B */ #define BIT_STATUS_BFEE4_8814B BIT(10) @@ -10130,10 +23553,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE4_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE4_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE4_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) & BIT_MASK_WMAC_MU_BFEE4_AID_8814B) - - +#define BIT_WMAC_MU_BFEE4_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) +#define BITS_WMAC_MU_BFEE4_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE4_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE4_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE4_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE4_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE4_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID_8814B(x) | BIT_WMAC_MU_BFEE4_AID_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8814B */ #define BIT_BIT_STATUS_BFEE5_8814B BIT(10) @@ -10141,10 +23572,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE5_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE5_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE5_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) & BIT_MASK_WMAC_MU_BFEE5_AID_8814B) - - +#define BIT_WMAC_MU_BFEE5_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) +#define BITS_WMAC_MU_BFEE5_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE5_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE5_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE5_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE5_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE5_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID_8814B(x) | BIT_WMAC_MU_BFEE5_AID_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8814B */ #define BIT_STATUS_BFEE6_8814B BIT(10) @@ -10152,124 +23591,318 @@ #define BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE6_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE6_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE6_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) & BIT_MASK_WMAC_MU_BFEE6_AID_8814B) - - +#define BIT_WMAC_MU_BFEE6_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) +#define BITS_WMAC_MU_BFEE6_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE6_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE6_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE6_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE6_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE6_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID_8814B(x) | BIT_WMAC_MU_BFEE6_AID_8814B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B */ -#define BIT_BIT_STATUS_BFEE4_8814B BIT(10) +#define BIT_STATUS_BFEE7_8814B BIT(10) #define BIT_WMAC_MU_BFEE7_EN_8814B BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B 0 #define BIT_MASK_WMAC_MU_BFEE7_AID_8814B 0x1ff -#define BIT_WMAC_MU_BFEE7_AID_8814B(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8814B) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) -#define BIT_GET_WMAC_MU_BFEE7_AID_8814B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) & BIT_MASK_WMAC_MU_BFEE7_AID_8814B) - - +#define BIT_WMAC_MU_BFEE7_AID_8814B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8814B) \ + << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) +#define BITS_WMAC_MU_BFEE7_AID_8814B \ + (BIT_MASK_WMAC_MU_BFEE7_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8814B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE7_AID_8814B)) +#define BIT_GET_WMAC_MU_BFEE7_AID_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) & \ + BIT_MASK_WMAC_MU_BFEE7_AID_8814B) +#define BIT_SET_WMAC_MU_BFEE7_AID_8814B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID_8814B(x) | BIT_WMAC_MU_BFEE7_AID_8814B(v)) /* 2 REG_WMAC_BB_STOP_RX_COUNTER_8814B */ #define BIT_RST_ALL_COUNTER_8814B BIT(31) #define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B 16 #define BIT_MASK_ABORT_RX_VBON_COUNTER_8814B 0xff -#define BIT_ABORT_RX_VBON_COUNTER_8814B(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8814B) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) -#define BIT_GET_ABORT_RX_VBON_COUNTER_8814B(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) & BIT_MASK_ABORT_RX_VBON_COUNTER_8814B) - - +#define BIT_ABORT_RX_VBON_COUNTER_8814B(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8814B) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) +#define BITS_ABORT_RX_VBON_COUNTER_8814B \ + (BIT_MASK_ABORT_RX_VBON_COUNTER_8814B \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8814B(x) \ + ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8814B)) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8814B(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER_8814B) +#define BIT_SET_ABORT_RX_VBON_COUNTER_8814B(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8814B(x) | \ + BIT_ABORT_RX_VBON_COUNTER_8814B(v)) #define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B 8 #define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B 0xff -#define BIT_ABORT_RX_RDRDY_COUNTER_8814B(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) -#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8814B(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B) - - +#define BIT_ABORT_RX_RDRDY_COUNTER_8814B(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) +#define BITS_ABORT_RX_RDRDY_COUNTER_8814B \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8814B(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8814B)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8814B(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8814B(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8814B(x) | \ + BIT_ABORT_RX_RDRDY_COUNTER_8814B(v)) #define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B 0 #define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B 0xff -#define BIT_VBON_EARLY_FALLING_COUNTER_8814B(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) -#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8814B(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B) - - +#define BIT_VBON_EARLY_FALLING_COUNTER_8814B(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) +#define BITS_VBON_EARLY_FALLING_COUNTER_8814B \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8814B(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8814B)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8814B(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8814B(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8814B(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER_8814B(v)) /* 2 REG_WMAC_PLCP_MONITOR_8814B */ #define BIT_WMAC_PLCP_TRX_SEL_8814B BIT(31) #define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B 28 #define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B 0x7 -#define BIT_WMAC_PLCP_RDSIG_SEL_8814B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) -#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8814B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B) - - +#define BIT_WMAC_PLCP_RDSIG_SEL_8814B(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) +#define BITS_WMAC_PLCP_RDSIG_SEL_8814B \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8814B(x) \ + ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8814B)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) & \ + BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8814B(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8814B(x) | \ + BIT_WMAC_PLCP_RDSIG_SEL_8814B(v)) #define BIT_SHIFT_WMAC_RATE_IDX_8814B 24 #define BIT_MASK_WMAC_RATE_IDX_8814B 0xf -#define BIT_WMAC_RATE_IDX_8814B(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8814B) << BIT_SHIFT_WMAC_RATE_IDX_8814B) -#define BIT_GET_WMAC_RATE_IDX_8814B(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8814B) & BIT_MASK_WMAC_RATE_IDX_8814B) - - +#define BIT_WMAC_RATE_IDX_8814B(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX_8814B) << BIT_SHIFT_WMAC_RATE_IDX_8814B) +#define BITS_WMAC_RATE_IDX_8814B \ + (BIT_MASK_WMAC_RATE_IDX_8814B << BIT_SHIFT_WMAC_RATE_IDX_8814B) +#define BIT_CLEAR_WMAC_RATE_IDX_8814B(x) ((x) & (~BITS_WMAC_RATE_IDX_8814B)) +#define BIT_GET_WMAC_RATE_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8814B) & BIT_MASK_WMAC_RATE_IDX_8814B) +#define BIT_SET_WMAC_RATE_IDX_8814B(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX_8814B(x) | BIT_WMAC_RATE_IDX_8814B(v)) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8814B 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8814B 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8814B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) -#define BIT_GET_WMAC_PLCP_RDSIG_8814B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) - +#define BIT_WMAC_PLCP_RDSIG_8814B(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) +#define BITS_WMAC_PLCP_RDSIG_8814B \ + (BIT_MASK_WMAC_PLCP_RDSIG_8814B << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8814B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8814B)) +#define BIT_GET_WMAC_PLCP_RDSIG_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8814B) +#define BIT_SET_WMAC_PLCP_RDSIG_8814B(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8814B(x) | BIT_WMAC_PLCP_RDSIG_8814B(v)) + +/* 2 REG_WMAC_DEBUG_PORT_8814B */ + +#define BIT_SHIFT_WMAC_DEBUG_PORT_8814B 0 +#define BIT_MASK_WMAC_DEBUG_PORT_8814B 0xffffffffL +#define BIT_WMAC_DEBUG_PORT_8814B(x) \ + (((x) & BIT_MASK_WMAC_DEBUG_PORT_8814B) \ + << BIT_SHIFT_WMAC_DEBUG_PORT_8814B) +#define BITS_WMAC_DEBUG_PORT_8814B \ + (BIT_MASK_WMAC_DEBUG_PORT_8814B << BIT_SHIFT_WMAC_DEBUG_PORT_8814B) +#define BIT_CLEAR_WMAC_DEBUG_PORT_8814B(x) ((x) & (~BITS_WMAC_DEBUG_PORT_8814B)) +#define BIT_GET_WMAC_DEBUG_PORT_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_DEBUG_PORT_8814B) & \ + BIT_MASK_WMAC_DEBUG_PORT_8814B) +#define BIT_SET_WMAC_DEBUG_PORT_8814B(x, v) \ + (BIT_CLEAR_WMAC_DEBUG_PORT_8814B(x) | BIT_WMAC_DEBUG_PORT_8814B(v)) +/* 2 REG_RSVD_8814B */ -/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8814B */ -#define BIT_WMAC_MUTX_IDX_8814B BIT(24) +/* 2 REG_TRANSMIT_ADDRSS_0_8814B (TA0 REGISTER) */ -#define BIT_SHIFT_WMAC_PLCP_RDSIG_8814B 0 -#define BIT_MASK_WMAC_PLCP_RDSIG_8814B 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8814B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) -#define BIT_GET_WMAC_PLCP_RDSIG_8814B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) +#define BIT_SHIFT_TA0_V1_8814B 0 +#define BIT_MASK_TA0_V1_8814B 0xffffffffL +#define BIT_TA0_V1_8814B(x) \ + (((x) & BIT_MASK_TA0_V1_8814B) << BIT_SHIFT_TA0_V1_8814B) +#define BITS_TA0_V1_8814B (BIT_MASK_TA0_V1_8814B << BIT_SHIFT_TA0_V1_8814B) +#define BIT_CLEAR_TA0_V1_8814B(x) ((x) & (~BITS_TA0_V1_8814B)) +#define BIT_GET_TA0_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA0_V1_8814B) & BIT_MASK_TA0_V1_8814B) +#define BIT_SET_TA0_V1_8814B(x, v) \ + (BIT_CLEAR_TA0_V1_8814B(x) | BIT_TA0_V1_8814B(v)) + +/* 2 REG_TRANSMIT_ADDRSS_0_H_8814B (TA0 REGISTER) */ + +#define BIT_SHIFT_TA0_H_V1_8814B 0 +#define BIT_MASK_TA0_H_V1_8814B 0xffff +#define BIT_TA0_H_V1_8814B(x) \ + (((x) & BIT_MASK_TA0_H_V1_8814B) << BIT_SHIFT_TA0_H_V1_8814B) +#define BITS_TA0_H_V1_8814B \ + (BIT_MASK_TA0_H_V1_8814B << BIT_SHIFT_TA0_H_V1_8814B) +#define BIT_CLEAR_TA0_H_V1_8814B(x) ((x) & (~BITS_TA0_H_V1_8814B)) +#define BIT_GET_TA0_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA0_H_V1_8814B) & BIT_MASK_TA0_H_V1_8814B) +#define BIT_SET_TA0_H_V1_8814B(x, v) \ + (BIT_CLEAR_TA0_H_V1_8814B(x) | BIT_TA0_H_V1_8814B(v)) +/* 2 REG_TRANSMIT_ADDRSS_1_8814B (TA1 REGISTER) */ +#define BIT_SHIFT_TA1_V1_8814B 0 +#define BIT_MASK_TA1_V1_8814B 0xffffffffL +#define BIT_TA1_V1_8814B(x) \ + (((x) & BIT_MASK_TA1_V1_8814B) << BIT_SHIFT_TA1_V1_8814B) +#define BITS_TA1_V1_8814B (BIT_MASK_TA1_V1_8814B << BIT_SHIFT_TA1_V1_8814B) +#define BIT_CLEAR_TA1_V1_8814B(x) ((x) & (~BITS_TA1_V1_8814B)) +#define BIT_GET_TA1_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA1_V1_8814B) & BIT_MASK_TA1_V1_8814B) +#define BIT_SET_TA1_V1_8814B(x, v) \ + (BIT_CLEAR_TA1_V1_8814B(x) | BIT_TA1_V1_8814B(v)) + +/* 2 REG_TRANSMIT_ADDRSS_1_H_8814B (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_H_V1_8814B 0 +#define BIT_MASK_TA1_H_V1_8814B 0xffff +#define BIT_TA1_H_V1_8814B(x) \ + (((x) & BIT_MASK_TA1_H_V1_8814B) << BIT_SHIFT_TA1_H_V1_8814B) +#define BITS_TA1_H_V1_8814B \ + (BIT_MASK_TA1_H_V1_8814B << BIT_SHIFT_TA1_H_V1_8814B) +#define BIT_CLEAR_TA1_H_V1_8814B(x) ((x) & (~BITS_TA1_H_V1_8814B)) +#define BIT_GET_TA1_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA1_H_V1_8814B) & BIT_MASK_TA1_H_V1_8814B) +#define BIT_SET_TA1_H_V1_8814B(x, v) \ + (BIT_CLEAR_TA1_H_V1_8814B(x) | BIT_TA1_H_V1_8814B(v)) -/* 2 REG_TRANSMIT_ADDRSS_0_8814B (TA0 REGISTER) */ +/* 2 REG_TRANSMIT_ADDRSS_2_8814B (TA2 REGISTER) */ -#define BIT_SHIFT_TA0_8814B 0 -#define BIT_MASK_TA0_8814B 0xffffffffffffL -#define BIT_TA0_8814B(x) (((x) & BIT_MASK_TA0_8814B) << BIT_SHIFT_TA0_8814B) -#define BIT_GET_TA0_8814B(x) (((x) >> BIT_SHIFT_TA0_8814B) & BIT_MASK_TA0_8814B) +#define BIT_SHIFT_TA2_V1_8814B 0 +#define BIT_MASK_TA2_V1_8814B 0xffffffffL +#define BIT_TA2_V1_8814B(x) \ + (((x) & BIT_MASK_TA2_V1_8814B) << BIT_SHIFT_TA2_V1_8814B) +#define BITS_TA2_V1_8814B (BIT_MASK_TA2_V1_8814B << BIT_SHIFT_TA2_V1_8814B) +#define BIT_CLEAR_TA2_V1_8814B(x) ((x) & (~BITS_TA2_V1_8814B)) +#define BIT_GET_TA2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8814B) & BIT_MASK_TA2_V1_8814B) +#define BIT_SET_TA2_V1_8814B(x, v) \ + (BIT_CLEAR_TA2_V1_8814B(x) | BIT_TA2_V1_8814B(v)) + +/* 2 REG_TRANSMIT_ADDRSS_2_H_8814B (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_H_V1_8814B 0 +#define BIT_MASK_TA2_H_V1_8814B 0xffff +#define BIT_TA2_H_V1_8814B(x) \ + (((x) & BIT_MASK_TA2_H_V1_8814B) << BIT_SHIFT_TA2_H_V1_8814B) +#define BITS_TA2_H_V1_8814B \ + (BIT_MASK_TA2_H_V1_8814B << BIT_SHIFT_TA2_H_V1_8814B) +#define BIT_CLEAR_TA2_H_V1_8814B(x) ((x) & (~BITS_TA2_H_V1_8814B)) +#define BIT_GET_TA2_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA2_H_V1_8814B) & BIT_MASK_TA2_H_V1_8814B) +#define BIT_SET_TA2_H_V1_8814B(x, v) \ + (BIT_CLEAR_TA2_H_V1_8814B(x) | BIT_TA2_H_V1_8814B(v)) +/* 2 REG_TRANSMIT_ADDRSS_3_8814B (TA3 REGISTER) */ +#define BIT_SHIFT_TA2_V1_8814B 0 +#define BIT_MASK_TA2_V1_8814B 0xffffffffL +#define BIT_TA2_V1_8814B(x) \ + (((x) & BIT_MASK_TA2_V1_8814B) << BIT_SHIFT_TA2_V1_8814B) +#define BITS_TA2_V1_8814B (BIT_MASK_TA2_V1_8814B << BIT_SHIFT_TA2_V1_8814B) +#define BIT_CLEAR_TA2_V1_8814B(x) ((x) & (~BITS_TA2_V1_8814B)) +#define BIT_GET_TA2_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8814B) & BIT_MASK_TA2_V1_8814B) +#define BIT_SET_TA2_V1_8814B(x, v) \ + (BIT_CLEAR_TA2_V1_8814B(x) | BIT_TA2_V1_8814B(v)) + +/* 2 REG_TRANSMIT_ADDRSS_3_H_8814B (TA3 REGISTER) */ + +#define BIT_SHIFT_TA3_H_V1_8814B 0 +#define BIT_MASK_TA3_H_V1_8814B 0xffff +#define BIT_TA3_H_V1_8814B(x) \ + (((x) & BIT_MASK_TA3_H_V1_8814B) << BIT_SHIFT_TA3_H_V1_8814B) +#define BITS_TA3_H_V1_8814B \ + (BIT_MASK_TA3_H_V1_8814B << BIT_SHIFT_TA3_H_V1_8814B) +#define BIT_CLEAR_TA3_H_V1_8814B(x) ((x) & (~BITS_TA3_H_V1_8814B)) +#define BIT_GET_TA3_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA3_H_V1_8814B) & BIT_MASK_TA3_H_V1_8814B) +#define BIT_SET_TA3_H_V1_8814B(x, v) \ + (BIT_CLEAR_TA3_H_V1_8814B(x) | BIT_TA3_H_V1_8814B(v)) -/* 2 REG_TRANSMIT_ADDRSS_1_8814B (TA1 REGISTER) */ +/* 2 REG_TRANSMIT_ADDRSS_4_8814B (TA4 REGISTER) */ -#define BIT_SHIFT_TA1_8814B 0 -#define BIT_MASK_TA1_8814B 0xffffffffffffL -#define BIT_TA1_8814B(x) (((x) & BIT_MASK_TA1_8814B) << BIT_SHIFT_TA1_8814B) -#define BIT_GET_TA1_8814B(x) (((x) >> BIT_SHIFT_TA1_8814B) & BIT_MASK_TA1_8814B) +#define BIT_SHIFT_TA4_V1_8814B 0 +#define BIT_MASK_TA4_V1_8814B 0xffffffffL +#define BIT_TA4_V1_8814B(x) \ + (((x) & BIT_MASK_TA4_V1_8814B) << BIT_SHIFT_TA4_V1_8814B) +#define BITS_TA4_V1_8814B (BIT_MASK_TA4_V1_8814B << BIT_SHIFT_TA4_V1_8814B) +#define BIT_CLEAR_TA4_V1_8814B(x) ((x) & (~BITS_TA4_V1_8814B)) +#define BIT_GET_TA4_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA4_V1_8814B) & BIT_MASK_TA4_V1_8814B) +#define BIT_SET_TA4_V1_8814B(x, v) \ + (BIT_CLEAR_TA4_V1_8814B(x) | BIT_TA4_V1_8814B(v)) + +/* 2 REG_TRANSMIT_ADDRSS_4_H_8814B (TA4 REGISTER) */ + +#define BIT_SHIFT_TA4_H_V1_8814B 0 +#define BIT_MASK_TA4_H_V1_8814B 0xffff +#define BIT_TA4_H_V1_8814B(x) \ + (((x) & BIT_MASK_TA4_H_V1_8814B) << BIT_SHIFT_TA4_H_V1_8814B) +#define BITS_TA4_H_V1_8814B \ + (BIT_MASK_TA4_H_V1_8814B << BIT_SHIFT_TA4_H_V1_8814B) +#define BIT_CLEAR_TA4_H_V1_8814B(x) ((x) & (~BITS_TA4_H_V1_8814B)) +#define BIT_GET_TA4_H_V1_8814B(x) \ + (((x) >> BIT_SHIFT_TA4_H_V1_8814B) & BIT_MASK_TA4_H_V1_8814B) +#define BIT_SET_TA4_H_V1_8814B(x, v) \ + (BIT_CLEAR_TA4_H_V1_8814B(x) | BIT_TA4_H_V1_8814B(v)) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_TRANSMIT_ADDRSS_2_8814B (TA2 REGISTER) */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_TA2_8814B 0 -#define BIT_MASK_TA2_8814B 0xffffffffffffL -#define BIT_TA2_8814B(x) (((x) & BIT_MASK_TA2_8814B) << BIT_SHIFT_TA2_8814B) -#define BIT_GET_TA2_8814B(x) (((x) >> BIT_SHIFT_TA2_8814B) & BIT_MASK_TA2_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_TRANSMIT_ADDRSS_3_8814B (TA3 REGISTER) */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_TA3_8814B 0 -#define BIT_MASK_TA3_8814B 0xffffffffffffL -#define BIT_TA3_8814B(x) (((x) & BIT_MASK_TA3_8814B) << BIT_SHIFT_TA3_8814B) -#define BIT_GET_TA3_8814B(x) (((x) >> BIT_SHIFT_TA3_8814B) & BIT_MASK_TA3_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ -/* 2 REG_TRANSMIT_ADDRSS_4_8814B (TA4 REGISTER) */ +/* 2 REG_RSVD_8814B */ -#define BIT_SHIFT_TA4_8814B 0 -#define BIT_MASK_TA4_8814B 0xffffffffffffL -#define BIT_TA4_8814B(x) (((x) & BIT_MASK_TA4_8814B) << BIT_SHIFT_TA4_8814B) -#define BIT_GET_TA4_8814B(x) (((x) >> BIT_SHIFT_TA4_8814B) & BIT_MASK_TA4_8814B) +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ +/* 2 REG_RSVD_8814B */ /* 2 REG_NOT_VALID_8814B */ @@ -10277,62 +23910,98 @@ #define BIT_SHIFT_MACID1_0_8814B 0 #define BIT_MASK_MACID1_0_8814B 0xffffffffL -#define BIT_MACID1_0_8814B(x) (((x) & BIT_MASK_MACID1_0_8814B) << BIT_SHIFT_MACID1_0_8814B) -#define BIT_GET_MACID1_0_8814B(x) (((x) >> BIT_SHIFT_MACID1_0_8814B) & BIT_MASK_MACID1_0_8814B) - - +#define BIT_MACID1_0_8814B(x) \ + (((x) & BIT_MASK_MACID1_0_8814B) << BIT_SHIFT_MACID1_0_8814B) +#define BITS_MACID1_0_8814B \ + (BIT_MASK_MACID1_0_8814B << BIT_SHIFT_MACID1_0_8814B) +#define BIT_CLEAR_MACID1_0_8814B(x) ((x) & (~BITS_MACID1_0_8814B)) +#define BIT_GET_MACID1_0_8814B(x) \ + (((x) >> BIT_SHIFT_MACID1_0_8814B) & BIT_MASK_MACID1_0_8814B) +#define BIT_SET_MACID1_0_8814B(x, v) \ + (BIT_CLEAR_MACID1_0_8814B(x) | BIT_MACID1_0_8814B(v)) /* 2 REG_MACID1_1_8814B */ #define BIT_SHIFT_MACID1_1_8814B 0 #define BIT_MASK_MACID1_1_8814B 0xffff -#define BIT_MACID1_1_8814B(x) (((x) & BIT_MASK_MACID1_1_8814B) << BIT_SHIFT_MACID1_1_8814B) -#define BIT_GET_MACID1_1_8814B(x) (((x) >> BIT_SHIFT_MACID1_1_8814B) & BIT_MASK_MACID1_1_8814B) - - +#define BIT_MACID1_1_8814B(x) \ + (((x) & BIT_MASK_MACID1_1_8814B) << BIT_SHIFT_MACID1_1_8814B) +#define BITS_MACID1_1_8814B \ + (BIT_MASK_MACID1_1_8814B << BIT_SHIFT_MACID1_1_8814B) +#define BIT_CLEAR_MACID1_1_8814B(x) ((x) & (~BITS_MACID1_1_8814B)) +#define BIT_GET_MACID1_1_8814B(x) \ + (((x) >> BIT_SHIFT_MACID1_1_8814B) & BIT_MASK_MACID1_1_8814B) +#define BIT_SET_MACID1_1_8814B(x, v) \ + (BIT_CLEAR_MACID1_1_8814B(x) | BIT_MACID1_1_8814B(v)) /* 2 REG_BSSID1_8814B */ #define BIT_SHIFT_BSSID1_0_8814B 0 #define BIT_MASK_BSSID1_0_8814B 0xffffffffL -#define BIT_BSSID1_0_8814B(x) (((x) & BIT_MASK_BSSID1_0_8814B) << BIT_SHIFT_BSSID1_0_8814B) -#define BIT_GET_BSSID1_0_8814B(x) (((x) >> BIT_SHIFT_BSSID1_0_8814B) & BIT_MASK_BSSID1_0_8814B) - - +#define BIT_BSSID1_0_8814B(x) \ + (((x) & BIT_MASK_BSSID1_0_8814B) << BIT_SHIFT_BSSID1_0_8814B) +#define BITS_BSSID1_0_8814B \ + (BIT_MASK_BSSID1_0_8814B << BIT_SHIFT_BSSID1_0_8814B) +#define BIT_CLEAR_BSSID1_0_8814B(x) ((x) & (~BITS_BSSID1_0_8814B)) +#define BIT_GET_BSSID1_0_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID1_0_8814B) & BIT_MASK_BSSID1_0_8814B) +#define BIT_SET_BSSID1_0_8814B(x, v) \ + (BIT_CLEAR_BSSID1_0_8814B(x) | BIT_BSSID1_0_8814B(v)) /* 2 REG_BSSID1_1_8814B */ #define BIT_SHIFT_BSSID1_1_8814B 0 #define BIT_MASK_BSSID1_1_8814B 0xffff -#define BIT_BSSID1_1_8814B(x) (((x) & BIT_MASK_BSSID1_1_8814B) << BIT_SHIFT_BSSID1_1_8814B) -#define BIT_GET_BSSID1_1_8814B(x) (((x) >> BIT_SHIFT_BSSID1_1_8814B) & BIT_MASK_BSSID1_1_8814B) - - +#define BIT_BSSID1_1_8814B(x) \ + (((x) & BIT_MASK_BSSID1_1_8814B) << BIT_SHIFT_BSSID1_1_8814B) +#define BITS_BSSID1_1_8814B \ + (BIT_MASK_BSSID1_1_8814B << BIT_SHIFT_BSSID1_1_8814B) +#define BIT_CLEAR_BSSID1_1_8814B(x) ((x) & (~BITS_BSSID1_1_8814B)) +#define BIT_GET_BSSID1_1_8814B(x) \ + (((x) >> BIT_SHIFT_BSSID1_1_8814B) & BIT_MASK_BSSID1_1_8814B) +#define BIT_SET_BSSID1_1_8814B(x, v) \ + (BIT_CLEAR_BSSID1_1_8814B(x) | BIT_BSSID1_1_8814B(v)) /* 2 REG_BCN_PSR_RPT1_8814B */ #define BIT_SHIFT_DTIM_CNT1_8814B 24 #define BIT_MASK_DTIM_CNT1_8814B 0xff -#define BIT_DTIM_CNT1_8814B(x) (((x) & BIT_MASK_DTIM_CNT1_8814B) << BIT_SHIFT_DTIM_CNT1_8814B) -#define BIT_GET_DTIM_CNT1_8814B(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8814B) & BIT_MASK_DTIM_CNT1_8814B) - - +#define BIT_DTIM_CNT1_8814B(x) \ + (((x) & BIT_MASK_DTIM_CNT1_8814B) << BIT_SHIFT_DTIM_CNT1_8814B) +#define BITS_DTIM_CNT1_8814B \ + (BIT_MASK_DTIM_CNT1_8814B << BIT_SHIFT_DTIM_CNT1_8814B) +#define BIT_CLEAR_DTIM_CNT1_8814B(x) ((x) & (~BITS_DTIM_CNT1_8814B)) +#define BIT_GET_DTIM_CNT1_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT1_8814B) & BIT_MASK_DTIM_CNT1_8814B) +#define BIT_SET_DTIM_CNT1_8814B(x, v) \ + (BIT_CLEAR_DTIM_CNT1_8814B(x) | BIT_DTIM_CNT1_8814B(v)) #define BIT_SHIFT_DTIM_PERIOD1_8814B 16 #define BIT_MASK_DTIM_PERIOD1_8814B 0xff -#define BIT_DTIM_PERIOD1_8814B(x) (((x) & BIT_MASK_DTIM_PERIOD1_8814B) << BIT_SHIFT_DTIM_PERIOD1_8814B) -#define BIT_GET_DTIM_PERIOD1_8814B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8814B) & BIT_MASK_DTIM_PERIOD1_8814B) - +#define BIT_DTIM_PERIOD1_8814B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1_8814B) << BIT_SHIFT_DTIM_PERIOD1_8814B) +#define BITS_DTIM_PERIOD1_8814B \ + (BIT_MASK_DTIM_PERIOD1_8814B << BIT_SHIFT_DTIM_PERIOD1_8814B) +#define BIT_CLEAR_DTIM_PERIOD1_8814B(x) ((x) & (~BITS_DTIM_PERIOD1_8814B)) +#define BIT_GET_DTIM_PERIOD1_8814B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1_8814B) & BIT_MASK_DTIM_PERIOD1_8814B) +#define BIT_SET_DTIM_PERIOD1_8814B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1_8814B(x) | BIT_DTIM_PERIOD1_8814B(v)) #define BIT_DTIM1_8814B BIT(15) #define BIT_TIM1_8814B BIT(14) #define BIT_SHIFT_PS_AID_1_8814B 0 #define BIT_MASK_PS_AID_1_8814B 0x7ff -#define BIT_PS_AID_1_8814B(x) (((x) & BIT_MASK_PS_AID_1_8814B) << BIT_SHIFT_PS_AID_1_8814B) -#define BIT_GET_PS_AID_1_8814B(x) (((x) >> BIT_SHIFT_PS_AID_1_8814B) & BIT_MASK_PS_AID_1_8814B) - - +#define BIT_PS_AID_1_8814B(x) \ + (((x) & BIT_MASK_PS_AID_1_8814B) << BIT_SHIFT_PS_AID_1_8814B) +#define BITS_PS_AID_1_8814B \ + (BIT_MASK_PS_AID_1_8814B << BIT_SHIFT_PS_AID_1_8814B) +#define BIT_CLEAR_PS_AID_1_8814B(x) ((x) & (~BITS_PS_AID_1_8814B)) +#define BIT_GET_PS_AID_1_8814B(x) \ + (((x) >> BIT_SHIFT_PS_AID_1_8814B) & BIT_MASK_PS_AID_1_8814B) +#define BIT_SET_PS_AID_1_8814B(x, v) \ + (BIT_CLEAR_PS_AID_1_8814B(x) | BIT_PS_AID_1_8814B(v)) /* 2 REG_ASSOCIATED_BFMEE_SEL_8814B */ #define BIT_TXUSER_ID1_8814B BIT(25) @@ -10340,39 +24009,76 @@ #define BIT_SHIFT_AID1_8814B 16 #define BIT_MASK_AID1_8814B 0x1ff #define BIT_AID1_8814B(x) (((x) & BIT_MASK_AID1_8814B) << BIT_SHIFT_AID1_8814B) -#define BIT_GET_AID1_8814B(x) (((x) >> BIT_SHIFT_AID1_8814B) & BIT_MASK_AID1_8814B) - +#define BITS_AID1_8814B (BIT_MASK_AID1_8814B << BIT_SHIFT_AID1_8814B) +#define BIT_CLEAR_AID1_8814B(x) ((x) & (~BITS_AID1_8814B)) +#define BIT_GET_AID1_8814B(x) \ + (((x) >> BIT_SHIFT_AID1_8814B) & BIT_MASK_AID1_8814B) +#define BIT_SET_AID1_8814B(x, v) (BIT_CLEAR_AID1_8814B(x) | BIT_AID1_8814B(v)) #define BIT_TXUSER_ID0_8814B BIT(9) #define BIT_SHIFT_AID0_8814B 0 #define BIT_MASK_AID0_8814B 0x1ff #define BIT_AID0_8814B(x) (((x) & BIT_MASK_AID0_8814B) << BIT_SHIFT_AID0_8814B) -#define BIT_GET_AID0_8814B(x) (((x) >> BIT_SHIFT_AID0_8814B) & BIT_MASK_AID0_8814B) - - +#define BITS_AID0_8814B (BIT_MASK_AID0_8814B << BIT_SHIFT_AID0_8814B) +#define BIT_CLEAR_AID0_8814B(x) ((x) & (~BITS_AID0_8814B)) +#define BIT_GET_AID0_8814B(x) \ + (((x) >> BIT_SHIFT_AID0_8814B) & BIT_MASK_AID0_8814B) +#define BIT_SET_AID0_8814B(x, v) (BIT_CLEAR_AID0_8814B(x) | BIT_AID0_8814B(v)) /* 2 REG_SND_PTCL_CTRL_8814B */ #define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B 24 #define BIT_MASK_NDP_RX_STANDBY_TIMER_8814B 0xff -#define BIT_NDP_RX_STANDBY_TIMER_8814B(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8814B) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) -#define BIT_GET_NDP_RX_STANDBY_TIMER_8814B(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) & BIT_MASK_NDP_RX_STANDBY_TIMER_8814B) - - +#define BIT_NDP_RX_STANDBY_TIMER_8814B(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8814B) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) +#define BITS_NDP_RX_STANDBY_TIMER_8814B \ + (BIT_MASK_NDP_RX_STANDBY_TIMER_8814B \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8814B(x) \ + ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8814B)) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER_8814B) +#define BIT_SET_NDP_RX_STANDBY_TIMER_8814B(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8814B(x) | \ + BIT_NDP_RX_STANDBY_TIMER_8814B(v)) #define BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B 16 #define BIT_MASK_CSI_RPT_OFFSET_HT_8814B 0xff -#define BIT_CSI_RPT_OFFSET_HT_8814B(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8814B) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) -#define BIT_GET_CSI_RPT_OFFSET_HT_8814B(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) & BIT_MASK_CSI_RPT_OFFSET_HT_8814B) - - - -#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8814B 8 -#define BIT_MASK_R_WMAC_VHT_CATEGORY_8814B 0xff -#define BIT_R_WMAC_VHT_CATEGORY_8814B(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8814B) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8814B) -#define BIT_GET_R_WMAC_VHT_CATEGORY_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8814B) & BIT_MASK_R_WMAC_VHT_CATEGORY_8814B) - +#define BIT_CSI_RPT_OFFSET_HT_8814B(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8814B) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) +#define BITS_CSI_RPT_OFFSET_HT_8814B \ + (BIT_MASK_CSI_RPT_OFFSET_HT_8814B << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8814B(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_HT_8814B)) +#define BIT_GET_CSI_RPT_OFFSET_HT_8814B(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_8814B) +#define BIT_SET_CSI_RPT_OFFSET_HT_8814B(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_8814B(x) | BIT_CSI_RPT_OFFSET_HT_8814B(v)) + +#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8814B BIT(15) +#define BIT_R_WMAC_CSI_CHKSUM_DIS_8814B BIT(14) + +#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B 8 +#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B 0x3f +#define BIT_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) \ + (((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B) \ + << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B) +#define BITS_R_CSI_RPT_OFFSET_VHT_V1_8814B \ + (BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B \ + << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B) +#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) \ + ((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1_8814B)) +#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) \ + (((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B) & \ + BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B) +#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1_8814B(x, v) \ + (BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) | \ + BIT_R_CSI_RPT_OFFSET_VHT_V1_8814B(v)) #define BIT_R_WMAC_USE_NSTS_8814B BIT(7) #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8814B BIT(6) @@ -10384,6 +24090,27 @@ #define BIT_R_WMAC_VHT_NDPA_EN_8814B BIT(0) /* 2 REG_RX_CSI_RPT_INFO_8814B */ +#define BIT_WRITE_ENABLE_8814B BIT(31) +#define BIT_WMAC_CHECK_SOUNDING_SEQ_8814B BIT(30) + +#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B 1 +#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B 0xffffff +#define BIT_VHTHT_MIMO_CTRL_FIELD_8814B(x) \ + (((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B) \ + << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B) +#define BITS_VHTHT_MIMO_CTRL_FIELD_8814B \ + (BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B \ + << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B) +#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8814B(x) \ + ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD_8814B)) +#define BIT_GET_VHTHT_MIMO_CTRL_FIELD_8814B(x) \ + (((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B) & \ + BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B) +#define BIT_SET_VHTHT_MIMO_CTRL_FIELD_8814B(x, v) \ + (BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8814B(x) | \ + BIT_VHTHT_MIMO_CTRL_FIELD_8814B(v)) + +#define BIT_CSI_INTERRUPT_STATUS_8814B BIT(0) /* 2 REG_NS_ARP_CTRL_8814B */ #define BIT_R_WMAC_NSARP_RSPEN_8814B BIT(15) @@ -10392,24 +24119,54 @@ #define BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B 6 #define BIT_MASK_R_WMAC_NSARP_MODEN_8814B 0x3 -#define BIT_R_WMAC_NSARP_MODEN_8814B(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8814B) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) -#define BIT_GET_R_WMAC_NSARP_MODEN_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) & BIT_MASK_R_WMAC_NSARP_MODEN_8814B) - - +#define BIT_R_WMAC_NSARP_MODEN_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8814B) \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) +#define BITS_R_WMAC_NSARP_MODEN_8814B \ + (BIT_MASK_R_WMAC_NSARP_MODEN_8814B \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8814B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_MODEN_8814B)) +#define BIT_GET_R_WMAC_NSARP_MODEN_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) & \ + BIT_MASK_R_WMAC_NSARP_MODEN_8814B) +#define BIT_SET_R_WMAC_NSARP_MODEN_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN_8814B(x) | \ + BIT_R_WMAC_NSARP_MODEN_8814B(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B 4 #define BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B 0x3 -#define BIT_R_WMAC_NSARP_RSPFTP_8814B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) -#define BIT_GET_R_WMAC_NSARP_RSPFTP_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B) - - +#define BIT_R_WMAC_NSARP_RSPFTP_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) +#define BITS_R_WMAC_NSARP_RSPFTP_8814B \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8814B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8814B)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) & \ + BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B) +#define BIT_SET_R_WMAC_NSARP_RSPFTP_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8814B(x) | \ + BIT_R_WMAC_NSARP_RSPFTP_8814B(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B 0 #define BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B 0xf -#define BIT_R_WMAC_NSARP_RSPSEC_8814B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) -#define BIT_GET_R_WMAC_NSARP_RSPSEC_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B) - - +#define BIT_R_WMAC_NSARP_RSPSEC_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) +#define BITS_R_WMAC_NSARP_RSPSEC_8814B \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8814B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8814B)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) & \ + BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B) +#define BIT_SET_R_WMAC_NSARP_RSPSEC_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8814B(x) | \ + BIT_R_WMAC_NSARP_RSPSEC_8814B(v)) /* 2 REG_NS_ARP_INFO_8814B */ #define BIT_REQ_IS_MCNS_8814B BIT(23) @@ -10420,78 +24177,158 @@ #define BIT_SHIFT_EXPRSP_SECTYPE_8814B 16 #define BIT_MASK_EXPRSP_SECTYPE_8814B 0x7 -#define BIT_EXPRSP_SECTYPE_8814B(x) (((x) & BIT_MASK_EXPRSP_SECTYPE_8814B) << BIT_SHIFT_EXPRSP_SECTYPE_8814B) -#define BIT_GET_EXPRSP_SECTYPE_8814B(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8814B) & BIT_MASK_EXPRSP_SECTYPE_8814B) - - +#define BIT_EXPRSP_SECTYPE_8814B(x) \ + (((x) & BIT_MASK_EXPRSP_SECTYPE_8814B) \ + << BIT_SHIFT_EXPRSP_SECTYPE_8814B) +#define BITS_EXPRSP_SECTYPE_8814B \ + (BIT_MASK_EXPRSP_SECTYPE_8814B << BIT_SHIFT_EXPRSP_SECTYPE_8814B) +#define BIT_CLEAR_EXPRSP_SECTYPE_8814B(x) ((x) & (~BITS_EXPRSP_SECTYPE_8814B)) +#define BIT_GET_EXPRSP_SECTYPE_8814B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8814B) & \ + BIT_MASK_EXPRSP_SECTYPE_8814B) +#define BIT_SET_EXPRSP_SECTYPE_8814B(x, v) \ + (BIT_CLEAR_EXPRSP_SECTYPE_8814B(x) | BIT_EXPRSP_SECTYPE_8814B(v)) #define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B 8 #define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B 0xff -#define BIT_EXPRSP_CHKSM_7_TO_0_8814B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) -#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8814B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B) - - +#define BIT_EXPRSP_CHKSM_7_TO_0_8814B(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B) \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) +#define BITS_EXPRSP_CHKSM_7_TO_0_8814B \ + (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) +#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8814B(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8814B)) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8814B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) & \ + BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B) +#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8814B(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8814B(x) | \ + BIT_EXPRSP_CHKSM_7_TO_0_8814B(v)) #define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B 0 #define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B 0xff -#define BIT_EXPRSP_CHKSM_15_TO_8_8814B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) -#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8814B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B) - - +#define BIT_EXPRSP_CHKSM_15_TO_8_8814B(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B) \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) +#define BITS_EXPRSP_CHKSM_15_TO_8_8814B \ + (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) +#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8814B(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8814B)) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8814B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) & \ + BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B) +#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8814B(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8814B(x) | \ + BIT_EXPRSP_CHKSM_15_TO_8_8814B(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_V1_8814B */ #define BIT_SHIFT_WMAC_ARPIP_8814B 0 #define BIT_MASK_WMAC_ARPIP_8814B 0xffffffffL -#define BIT_WMAC_ARPIP_8814B(x) (((x) & BIT_MASK_WMAC_ARPIP_8814B) << BIT_SHIFT_WMAC_ARPIP_8814B) -#define BIT_GET_WMAC_ARPIP_8814B(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8814B) & BIT_MASK_WMAC_ARPIP_8814B) - - +#define BIT_WMAC_ARPIP_8814B(x) \ + (((x) & BIT_MASK_WMAC_ARPIP_8814B) << BIT_SHIFT_WMAC_ARPIP_8814B) +#define BITS_WMAC_ARPIP_8814B \ + (BIT_MASK_WMAC_ARPIP_8814B << BIT_SHIFT_WMAC_ARPIP_8814B) +#define BIT_CLEAR_WMAC_ARPIP_8814B(x) ((x) & (~BITS_WMAC_ARPIP_8814B)) +#define BIT_GET_WMAC_ARPIP_8814B(x) \ + (((x) >> BIT_SHIFT_WMAC_ARPIP_8814B) & BIT_MASK_WMAC_ARPIP_8814B) +#define BIT_SET_WMAC_ARPIP_8814B(x, v) \ + (BIT_CLEAR_WMAC_ARPIP_8814B(x) | BIT_WMAC_ARPIP_8814B(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_8814B */ #define BIT_SHIFT_BEAMFORMING_INFO_8814B 0 #define BIT_MASK_BEAMFORMING_INFO_8814B 0xffffffffL -#define BIT_BEAMFORMING_INFO_8814B(x) (((x) & BIT_MASK_BEAMFORMING_INFO_8814B) << BIT_SHIFT_BEAMFORMING_INFO_8814B) -#define BIT_GET_BEAMFORMING_INFO_8814B(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8814B) & BIT_MASK_BEAMFORMING_INFO_8814B) - - +#define BIT_BEAMFORMING_INFO_8814B(x) \ + (((x) & BIT_MASK_BEAMFORMING_INFO_8814B) \ + << BIT_SHIFT_BEAMFORMING_INFO_8814B) +#define BITS_BEAMFORMING_INFO_8814B \ + (BIT_MASK_BEAMFORMING_INFO_8814B << BIT_SHIFT_BEAMFORMING_INFO_8814B) +#define BIT_CLEAR_BEAMFORMING_INFO_8814B(x) \ + ((x) & (~BITS_BEAMFORMING_INFO_8814B)) +#define BIT_GET_BEAMFORMING_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8814B) & \ + BIT_MASK_BEAMFORMING_INFO_8814B) +#define BIT_SET_BEAMFORMING_INFO_8814B(x, v) \ + (BIT_CLEAR_BEAMFORMING_INFO_8814B(x) | BIT_BEAMFORMING_INFO_8814B(v)) /* 2 REG_IPV6_8814B */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_0_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B) - - +#define BIT_R_WMAC_IPV6_MYIPAD_0_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) +#define BITS_R_WMAC_IPV6_MYIPAD_0_8814B \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8814B(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8814B)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8814B(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_0_8814B(v)) /* 2 REG_IPV6_1_8814B */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_1_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B) - - +#define BIT_R_WMAC_IPV6_MYIPAD_1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) +#define BITS_R_WMAC_IPV6_MYIPAD_1_8814B \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8814B(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8814B)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8814B(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_1_8814B(v)) /* 2 REG_IPV6_2_8814B */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_2_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B) - - +#define BIT_R_WMAC_IPV6_MYIPAD_2_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) +#define BITS_R_WMAC_IPV6_MYIPAD_2_8814B \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8814B(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8814B)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8814B(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_2_8814B(v)) /* 2 REG_IPV6_3_8814B */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_3_8814B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B) - - +#define BIT_R_WMAC_IPV6_MYIPAD_3_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) +#define BITS_R_WMAC_IPV6_MYIPAD_3_8814B \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8814B(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8814B)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8814B(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_3_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -10505,17 +24342,37 @@ #define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B 4 #define BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B 0xf -#define BIT_R_WMAC_CTX_SUBTYPE_8814B(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) -#define BIT_GET_R_WMAC_CTX_SUBTYPE_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B) - - +#define BIT_R_WMAC_CTX_SUBTYPE_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B) \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) +#define BITS_R_WMAC_CTX_SUBTYPE_8814B \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8814B(x) \ + ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8814B)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) & \ + BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B) +#define BIT_SET_R_WMAC_CTX_SUBTYPE_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8814B(x) | \ + BIT_R_WMAC_CTX_SUBTYPE_8814B(v)) #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B 0 #define BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B 0xf -#define BIT_R_WMAC_RTX_SUBTYPE_8814B(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) -#define BIT_GET_R_WMAC_RTX_SUBTYPE_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B) - - +#define BIT_R_WMAC_RTX_SUBTYPE_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B) \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) +#define BITS_R_WMAC_RTX_SUBTYPE_8814B \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8814B(x) \ + ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8814B)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) & \ + BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B) +#define BIT_SET_R_WMAC_RTX_SUBTYPE_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8814B(x) | \ + BIT_R_WMAC_RTX_SUBTYPE_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -10531,10 +24388,14 @@ #define BIT_SHIFT_TIMER_8814B 0 #define BIT_MASK_TIMER_8814B 0xff -#define BIT_TIMER_8814B(x) (((x) & BIT_MASK_TIMER_8814B) << BIT_SHIFT_TIMER_8814B) -#define BIT_GET_TIMER_8814B(x) (((x) >> BIT_SHIFT_TIMER_8814B) & BIT_MASK_TIMER_8814B) - - +#define BIT_TIMER_8814B(x) \ + (((x) & BIT_MASK_TIMER_8814B) << BIT_SHIFT_TIMER_8814B) +#define BITS_TIMER_8814B (BIT_MASK_TIMER_8814B << BIT_SHIFT_TIMER_8814B) +#define BIT_CLEAR_TIMER_8814B(x) ((x) & (~BITS_TIMER_8814B)) +#define BIT_GET_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_TIMER_8814B) & BIT_MASK_TIMER_8814B) +#define BIT_SET_TIMER_8814B(x, v) \ + (BIT_CLEAR_TIMER_8814B(x) | BIT_TIMER_8814B(v)) /* 2 REG_BT_COEX_8814B */ #define BIT_R_GNT_BT_RFC_SW_8814B BIT(12) @@ -10545,26 +24406,43 @@ #define BIT_SHIFT_R_BT_CNT_THR_8814B 0 #define BIT_MASK_R_BT_CNT_THR_8814B 0xff -#define BIT_R_BT_CNT_THR_8814B(x) (((x) & BIT_MASK_R_BT_CNT_THR_8814B) << BIT_SHIFT_R_BT_CNT_THR_8814B) -#define BIT_GET_R_BT_CNT_THR_8814B(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8814B) & BIT_MASK_R_BT_CNT_THR_8814B) - - +#define BIT_R_BT_CNT_THR_8814B(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR_8814B) << BIT_SHIFT_R_BT_CNT_THR_8814B) +#define BITS_R_BT_CNT_THR_8814B \ + (BIT_MASK_R_BT_CNT_THR_8814B << BIT_SHIFT_R_BT_CNT_THR_8814B) +#define BIT_CLEAR_R_BT_CNT_THR_8814B(x) ((x) & (~BITS_R_BT_CNT_THR_8814B)) +#define BIT_GET_R_BT_CNT_THR_8814B(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR_8814B) & BIT_MASK_R_BT_CNT_THR_8814B) +#define BIT_SET_R_BT_CNT_THR_8814B(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR_8814B(x) | BIT_R_BT_CNT_THR_8814B(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_8814B */ #define BIT_SHIFT_RXMYRTS_NAV_V1_8814B 8 #define BIT_MASK_RXMYRTS_NAV_V1_8814B 0xff -#define BIT_RXMYRTS_NAV_V1_8814B(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8814B) << BIT_SHIFT_RXMYRTS_NAV_V1_8814B) -#define BIT_GET_RXMYRTS_NAV_V1_8814B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8814B) & BIT_MASK_RXMYRTS_NAV_V1_8814B) - - +#define BIT_RXMYRTS_NAV_V1_8814B(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1_8814B) \ + << BIT_SHIFT_RXMYRTS_NAV_V1_8814B) +#define BITS_RXMYRTS_NAV_V1_8814B \ + (BIT_MASK_RXMYRTS_NAV_V1_8814B << BIT_SHIFT_RXMYRTS_NAV_V1_8814B) +#define BIT_CLEAR_RXMYRTS_NAV_V1_8814B(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8814B)) +#define BIT_GET_RXMYRTS_NAV_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8814B) & \ + BIT_MASK_RXMYRTS_NAV_V1_8814B) +#define BIT_SET_RXMYRTS_NAV_V1_8814B(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1_8814B(x) | BIT_RXMYRTS_NAV_V1_8814B(v)) #define BIT_SHIFT_RTSRST_V1_8814B 0 #define BIT_MASK_RTSRST_V1_8814B 0xff -#define BIT_RTSRST_V1_8814B(x) (((x) & BIT_MASK_RTSRST_V1_8814B) << BIT_SHIFT_RTSRST_V1_8814B) -#define BIT_GET_RTSRST_V1_8814B(x) (((x) >> BIT_SHIFT_RTSRST_V1_8814B) & BIT_MASK_RTSRST_V1_8814B) - - +#define BIT_RTSRST_V1_8814B(x) \ + (((x) & BIT_MASK_RTSRST_V1_8814B) << BIT_SHIFT_RTSRST_V1_8814B) +#define BITS_RTSRST_V1_8814B \ + (BIT_MASK_RTSRST_V1_8814B << BIT_SHIFT_RTSRST_V1_8814B) +#define BIT_CLEAR_RTSRST_V1_8814B(x) ((x) & (~BITS_RTSRST_V1_8814B)) +#define BIT_GET_RTSRST_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RTSRST_V1_8814B) & BIT_MASK_RTSRST_V1_8814B) +#define BIT_SET_RTSRST_V1_8814B(x, v) \ + (BIT_CLEAR_RTSRST_V1_8814B(x) | BIT_RTSRST_V1_8814B(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_1_8814B */ #define BIT_WLRX_TER_BY_CTL_1_8814B BIT(11) @@ -10579,23 +24457,47 @@ #define BIT_SHIFT_BT_STAT_DELAY_8814B 12 #define BIT_MASK_BT_STAT_DELAY_8814B 0xf -#define BIT_BT_STAT_DELAY_8814B(x) (((x) & BIT_MASK_BT_STAT_DELAY_8814B) << BIT_SHIFT_BT_STAT_DELAY_8814B) -#define BIT_GET_BT_STAT_DELAY_8814B(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8814B) & BIT_MASK_BT_STAT_DELAY_8814B) - - +#define BIT_BT_STAT_DELAY_8814B(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY_8814B) << BIT_SHIFT_BT_STAT_DELAY_8814B) +#define BITS_BT_STAT_DELAY_8814B \ + (BIT_MASK_BT_STAT_DELAY_8814B << BIT_SHIFT_BT_STAT_DELAY_8814B) +#define BIT_CLEAR_BT_STAT_DELAY_8814B(x) ((x) & (~BITS_BT_STAT_DELAY_8814B)) +#define BIT_GET_BT_STAT_DELAY_8814B(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY_8814B) & BIT_MASK_BT_STAT_DELAY_8814B) +#define BIT_SET_BT_STAT_DELAY_8814B(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY_8814B(x) | BIT_BT_STAT_DELAY_8814B(v)) #define BIT_SHIFT_BT_TRX_INIT_DETECT_8814B 8 #define BIT_MASK_BT_TRX_INIT_DETECT_8814B 0xf -#define BIT_BT_TRX_INIT_DETECT_8814B(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8814B) << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) -#define BIT_GET_BT_TRX_INIT_DETECT_8814B(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) & BIT_MASK_BT_TRX_INIT_DETECT_8814B) - - +#define BIT_BT_TRX_INIT_DETECT_8814B(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8814B) \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) +#define BITS_BT_TRX_INIT_DETECT_8814B \ + (BIT_MASK_BT_TRX_INIT_DETECT_8814B \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) +#define BIT_CLEAR_BT_TRX_INIT_DETECT_8814B(x) \ + ((x) & (~BITS_BT_TRX_INIT_DETECT_8814B)) +#define BIT_GET_BT_TRX_INIT_DETECT_8814B(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) & \ + BIT_MASK_BT_TRX_INIT_DETECT_8814B) +#define BIT_SET_BT_TRX_INIT_DETECT_8814B(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT_8814B(x) | \ + BIT_BT_TRX_INIT_DETECT_8814B(v)) #define BIT_SHIFT_BT_PRI_DETECT_TO_8814B 4 #define BIT_MASK_BT_PRI_DETECT_TO_8814B 0xf -#define BIT_BT_PRI_DETECT_TO_8814B(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8814B) << BIT_SHIFT_BT_PRI_DETECT_TO_8814B) -#define BIT_GET_BT_PRI_DETECT_TO_8814B(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8814B) & BIT_MASK_BT_PRI_DETECT_TO_8814B) - +#define BIT_BT_PRI_DETECT_TO_8814B(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO_8814B) \ + << BIT_SHIFT_BT_PRI_DETECT_TO_8814B) +#define BITS_BT_PRI_DETECT_TO_8814B \ + (BIT_MASK_BT_PRI_DETECT_TO_8814B << BIT_SHIFT_BT_PRI_DETECT_TO_8814B) +#define BIT_CLEAR_BT_PRI_DETECT_TO_8814B(x) \ + ((x) & (~BITS_BT_PRI_DETECT_TO_8814B)) +#define BIT_GET_BT_PRI_DETECT_TO_8814B(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8814B) & \ + BIT_MASK_BT_PRI_DETECT_TO_8814B) +#define BIT_SET_BT_PRI_DETECT_TO_8814B(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO_8814B(x) | BIT_BT_PRI_DETECT_TO_8814B(v)) #define BIT_R_GRANTALL_WLMASK_8814B BIT(3) #define BIT_STATIS_BT_EN_8814B BIT(2) @@ -10606,55 +24508,103 @@ #define BIT_SHIFT_STATIS_BT_HI_RX_8814B 16 #define BIT_MASK_STATIS_BT_HI_RX_8814B 0xffff -#define BIT_STATIS_BT_HI_RX_8814B(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8814B) << BIT_SHIFT_STATIS_BT_HI_RX_8814B) -#define BIT_GET_STATIS_BT_HI_RX_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8814B) & BIT_MASK_STATIS_BT_HI_RX_8814B) - - +#define BIT_STATIS_BT_HI_RX_8814B(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX_8814B) \ + << BIT_SHIFT_STATIS_BT_HI_RX_8814B) +#define BITS_STATIS_BT_HI_RX_8814B \ + (BIT_MASK_STATIS_BT_HI_RX_8814B << BIT_SHIFT_STATIS_BT_HI_RX_8814B) +#define BIT_CLEAR_STATIS_BT_HI_RX_8814B(x) ((x) & (~BITS_STATIS_BT_HI_RX_8814B)) +#define BIT_GET_STATIS_BT_HI_RX_8814B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8814B) & \ + BIT_MASK_STATIS_BT_HI_RX_8814B) +#define BIT_SET_STATIS_BT_HI_RX_8814B(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX_8814B(x) | BIT_STATIS_BT_HI_RX_8814B(v)) #define BIT_SHIFT_STATIS_BT_HI_TX_8814B 0 #define BIT_MASK_STATIS_BT_HI_TX_8814B 0xffff -#define BIT_STATIS_BT_HI_TX_8814B(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8814B) << BIT_SHIFT_STATIS_BT_HI_TX_8814B) -#define BIT_GET_STATIS_BT_HI_TX_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8814B) & BIT_MASK_STATIS_BT_HI_TX_8814B) - - +#define BIT_STATIS_BT_HI_TX_8814B(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX_8814B) \ + << BIT_SHIFT_STATIS_BT_HI_TX_8814B) +#define BITS_STATIS_BT_HI_TX_8814B \ + (BIT_MASK_STATIS_BT_HI_TX_8814B << BIT_SHIFT_STATIS_BT_HI_TX_8814B) +#define BIT_CLEAR_STATIS_BT_HI_TX_8814B(x) ((x) & (~BITS_STATIS_BT_HI_TX_8814B)) +#define BIT_GET_STATIS_BT_HI_TX_8814B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8814B) & \ + BIT_MASK_STATIS_BT_HI_TX_8814B) +#define BIT_SET_STATIS_BT_HI_TX_8814B(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX_8814B(x) | BIT_STATIS_BT_HI_TX_8814B(v)) /* 2 REG_BT_ACT_STATISTICS_1_8814B */ #define BIT_SHIFT_STATIS_BT_LO_RX_1_8814B 16 #define BIT_MASK_STATIS_BT_LO_RX_1_8814B 0xffff -#define BIT_STATIS_BT_LO_RX_1_8814B(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8814B) << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) -#define BIT_GET_STATIS_BT_LO_RX_1_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) & BIT_MASK_STATIS_BT_LO_RX_1_8814B) - - +#define BIT_STATIS_BT_LO_RX_1_8814B(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8814B) \ + << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) +#define BITS_STATIS_BT_LO_RX_1_8814B \ + (BIT_MASK_STATIS_BT_LO_RX_1_8814B << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) +#define BIT_CLEAR_STATIS_BT_LO_RX_1_8814B(x) \ + ((x) & (~BITS_STATIS_BT_LO_RX_1_8814B)) +#define BIT_GET_STATIS_BT_LO_RX_1_8814B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) & \ + BIT_MASK_STATIS_BT_LO_RX_1_8814B) +#define BIT_SET_STATIS_BT_LO_RX_1_8814B(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_1_8814B(x) | BIT_STATIS_BT_LO_RX_1_8814B(v)) #define BIT_SHIFT_STATIS_BT_LO_TX_1_8814B 0 #define BIT_MASK_STATIS_BT_LO_TX_1_8814B 0xffff -#define BIT_STATIS_BT_LO_TX_1_8814B(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8814B) << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) -#define BIT_GET_STATIS_BT_LO_TX_1_8814B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) & BIT_MASK_STATIS_BT_LO_TX_1_8814B) - - +#define BIT_STATIS_BT_LO_TX_1_8814B(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8814B) \ + << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) +#define BITS_STATIS_BT_LO_TX_1_8814B \ + (BIT_MASK_STATIS_BT_LO_TX_1_8814B << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) +#define BIT_CLEAR_STATIS_BT_LO_TX_1_8814B(x) \ + ((x) & (~BITS_STATIS_BT_LO_TX_1_8814B)) +#define BIT_GET_STATIS_BT_LO_TX_1_8814B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) & \ + BIT_MASK_STATIS_BT_LO_TX_1_8814B) +#define BIT_SET_STATIS_BT_LO_TX_1_8814B(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_1_8814B(x) | BIT_STATIS_BT_LO_TX_1_8814B(v)) /* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8814B */ #define BIT_SHIFT_R_BT_CMD_RPT_8814B 16 #define BIT_MASK_R_BT_CMD_RPT_8814B 0xffff -#define BIT_R_BT_CMD_RPT_8814B(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8814B) << BIT_SHIFT_R_BT_CMD_RPT_8814B) -#define BIT_GET_R_BT_CMD_RPT_8814B(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8814B) & BIT_MASK_R_BT_CMD_RPT_8814B) - - +#define BIT_R_BT_CMD_RPT_8814B(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT_8814B) << BIT_SHIFT_R_BT_CMD_RPT_8814B) +#define BITS_R_BT_CMD_RPT_8814B \ + (BIT_MASK_R_BT_CMD_RPT_8814B << BIT_SHIFT_R_BT_CMD_RPT_8814B) +#define BIT_CLEAR_R_BT_CMD_RPT_8814B(x) ((x) & (~BITS_R_BT_CMD_RPT_8814B)) +#define BIT_GET_R_BT_CMD_RPT_8814B(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8814B) & BIT_MASK_R_BT_CMD_RPT_8814B) +#define BIT_SET_R_BT_CMD_RPT_8814B(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT_8814B(x) | BIT_R_BT_CMD_RPT_8814B(v)) #define BIT_SHIFT_R_RPT_FROM_BT_8814B 8 #define BIT_MASK_R_RPT_FROM_BT_8814B 0xff -#define BIT_R_RPT_FROM_BT_8814B(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8814B) << BIT_SHIFT_R_RPT_FROM_BT_8814B) -#define BIT_GET_R_RPT_FROM_BT_8814B(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8814B) & BIT_MASK_R_RPT_FROM_BT_8814B) - - +#define BIT_R_RPT_FROM_BT_8814B(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT_8814B) << BIT_SHIFT_R_RPT_FROM_BT_8814B) +#define BITS_R_RPT_FROM_BT_8814B \ + (BIT_MASK_R_RPT_FROM_BT_8814B << BIT_SHIFT_R_RPT_FROM_BT_8814B) +#define BIT_CLEAR_R_RPT_FROM_BT_8814B(x) ((x) & (~BITS_R_RPT_FROM_BT_8814B)) +#define BIT_GET_R_RPT_FROM_BT_8814B(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8814B) & BIT_MASK_R_RPT_FROM_BT_8814B) +#define BIT_SET_R_RPT_FROM_BT_8814B(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT_8814B(x) | BIT_R_RPT_FROM_BT_8814B(v)) #define BIT_SHIFT_BT_HID_ISR_SET_8814B 6 #define BIT_MASK_BT_HID_ISR_SET_8814B 0x3 -#define BIT_BT_HID_ISR_SET_8814B(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8814B) << BIT_SHIFT_BT_HID_ISR_SET_8814B) -#define BIT_GET_BT_HID_ISR_SET_8814B(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8814B) & BIT_MASK_BT_HID_ISR_SET_8814B) - +#define BIT_BT_HID_ISR_SET_8814B(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET_8814B) \ + << BIT_SHIFT_BT_HID_ISR_SET_8814B) +#define BITS_BT_HID_ISR_SET_8814B \ + (BIT_MASK_BT_HID_ISR_SET_8814B << BIT_SHIFT_BT_HID_ISR_SET_8814B) +#define BIT_CLEAR_BT_HID_ISR_SET_8814B(x) ((x) & (~BITS_BT_HID_ISR_SET_8814B)) +#define BIT_GET_BT_HID_ISR_SET_8814B(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8814B) & \ + BIT_MASK_BT_HID_ISR_SET_8814B) +#define BIT_SET_BT_HID_ISR_SET_8814B(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET_8814B(x) | BIT_BT_HID_ISR_SET_8814B(v)) #define BIT_TDMA_BT_START_NOTIFY_8814B BIT(5) #define BIT_ENABLE_TDMA_FW_MODE_8814B BIT(4) @@ -10667,31 +24617,54 @@ #define BIT_SHIFT_BT_PROFILE_8814B 24 #define BIT_MASK_BT_PROFILE_8814B 0xff -#define BIT_BT_PROFILE_8814B(x) (((x) & BIT_MASK_BT_PROFILE_8814B) << BIT_SHIFT_BT_PROFILE_8814B) -#define BIT_GET_BT_PROFILE_8814B(x) (((x) >> BIT_SHIFT_BT_PROFILE_8814B) & BIT_MASK_BT_PROFILE_8814B) - - +#define BIT_BT_PROFILE_8814B(x) \ + (((x) & BIT_MASK_BT_PROFILE_8814B) << BIT_SHIFT_BT_PROFILE_8814B) +#define BITS_BT_PROFILE_8814B \ + (BIT_MASK_BT_PROFILE_8814B << BIT_SHIFT_BT_PROFILE_8814B) +#define BIT_CLEAR_BT_PROFILE_8814B(x) ((x) & (~BITS_BT_PROFILE_8814B)) +#define BIT_GET_BT_PROFILE_8814B(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE_8814B) & BIT_MASK_BT_PROFILE_8814B) +#define BIT_SET_BT_PROFILE_8814B(x, v) \ + (BIT_CLEAR_BT_PROFILE_8814B(x) | BIT_BT_PROFILE_8814B(v)) #define BIT_SHIFT_BT_POWER_8814B 16 #define BIT_MASK_BT_POWER_8814B 0xff -#define BIT_BT_POWER_8814B(x) (((x) & BIT_MASK_BT_POWER_8814B) << BIT_SHIFT_BT_POWER_8814B) -#define BIT_GET_BT_POWER_8814B(x) (((x) >> BIT_SHIFT_BT_POWER_8814B) & BIT_MASK_BT_POWER_8814B) - - +#define BIT_BT_POWER_8814B(x) \ + (((x) & BIT_MASK_BT_POWER_8814B) << BIT_SHIFT_BT_POWER_8814B) +#define BITS_BT_POWER_8814B \ + (BIT_MASK_BT_POWER_8814B << BIT_SHIFT_BT_POWER_8814B) +#define BIT_CLEAR_BT_POWER_8814B(x) ((x) & (~BITS_BT_POWER_8814B)) +#define BIT_GET_BT_POWER_8814B(x) \ + (((x) >> BIT_SHIFT_BT_POWER_8814B) & BIT_MASK_BT_POWER_8814B) +#define BIT_SET_BT_POWER_8814B(x, v) \ + (BIT_CLEAR_BT_POWER_8814B(x) | BIT_BT_POWER_8814B(v)) #define BIT_SHIFT_BT_PREDECT_STATUS_8814B 8 #define BIT_MASK_BT_PREDECT_STATUS_8814B 0xff -#define BIT_BT_PREDECT_STATUS_8814B(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8814B) << BIT_SHIFT_BT_PREDECT_STATUS_8814B) -#define BIT_GET_BT_PREDECT_STATUS_8814B(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8814B) & BIT_MASK_BT_PREDECT_STATUS_8814B) - - +#define BIT_BT_PREDECT_STATUS_8814B(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS_8814B) \ + << BIT_SHIFT_BT_PREDECT_STATUS_8814B) +#define BITS_BT_PREDECT_STATUS_8814B \ + (BIT_MASK_BT_PREDECT_STATUS_8814B << BIT_SHIFT_BT_PREDECT_STATUS_8814B) +#define BIT_CLEAR_BT_PREDECT_STATUS_8814B(x) \ + ((x) & (~BITS_BT_PREDECT_STATUS_8814B)) +#define BIT_GET_BT_PREDECT_STATUS_8814B(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8814B) & \ + BIT_MASK_BT_PREDECT_STATUS_8814B) +#define BIT_SET_BT_PREDECT_STATUS_8814B(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS_8814B(x) | BIT_BT_PREDECT_STATUS_8814B(v)) #define BIT_SHIFT_BT_CMD_INFO_8814B 0 #define BIT_MASK_BT_CMD_INFO_8814B 0xff -#define BIT_BT_CMD_INFO_8814B(x) (((x) & BIT_MASK_BT_CMD_INFO_8814B) << BIT_SHIFT_BT_CMD_INFO_8814B) -#define BIT_GET_BT_CMD_INFO_8814B(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8814B) & BIT_MASK_BT_CMD_INFO_8814B) - - +#define BIT_BT_CMD_INFO_8814B(x) \ + (((x) & BIT_MASK_BT_CMD_INFO_8814B) << BIT_SHIFT_BT_CMD_INFO_8814B) +#define BITS_BT_CMD_INFO_8814B \ + (BIT_MASK_BT_CMD_INFO_8814B << BIT_SHIFT_BT_CMD_INFO_8814B) +#define BIT_CLEAR_BT_CMD_INFO_8814B(x) ((x) & (~BITS_BT_CMD_INFO_8814B)) +#define BIT_GET_BT_CMD_INFO_8814B(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO_8814B) & BIT_MASK_BT_CMD_INFO_8814B) +#define BIT_SET_BT_CMD_INFO_8814B(x, v) \ + (BIT_CLEAR_BT_CMD_INFO_8814B(x) | BIT_BT_CMD_INFO_8814B(v)) /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8814B */ #define BIT_EN_MAC_NULL_PKT_NOTIFY_8814B BIT(31) @@ -10705,41 +24678,67 @@ #define BIT_SHIFT_WLAN_RPT_DATA_8814B 16 #define BIT_MASK_WLAN_RPT_DATA_8814B 0xff -#define BIT_WLAN_RPT_DATA_8814B(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8814B) << BIT_SHIFT_WLAN_RPT_DATA_8814B) -#define BIT_GET_WLAN_RPT_DATA_8814B(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8814B) & BIT_MASK_WLAN_RPT_DATA_8814B) - - +#define BIT_WLAN_RPT_DATA_8814B(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA_8814B) << BIT_SHIFT_WLAN_RPT_DATA_8814B) +#define BITS_WLAN_RPT_DATA_8814B \ + (BIT_MASK_WLAN_RPT_DATA_8814B << BIT_SHIFT_WLAN_RPT_DATA_8814B) +#define BIT_CLEAR_WLAN_RPT_DATA_8814B(x) ((x) & (~BITS_WLAN_RPT_DATA_8814B)) +#define BIT_GET_WLAN_RPT_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8814B) & BIT_MASK_WLAN_RPT_DATA_8814B) +#define BIT_SET_WLAN_RPT_DATA_8814B(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA_8814B(x) | BIT_WLAN_RPT_DATA_8814B(v)) #define BIT_SHIFT_CMD_ID_8814B 8 #define BIT_MASK_CMD_ID_8814B 0xff -#define BIT_CMD_ID_8814B(x) (((x) & BIT_MASK_CMD_ID_8814B) << BIT_SHIFT_CMD_ID_8814B) -#define BIT_GET_CMD_ID_8814B(x) (((x) >> BIT_SHIFT_CMD_ID_8814B) & BIT_MASK_CMD_ID_8814B) - - +#define BIT_CMD_ID_8814B(x) \ + (((x) & BIT_MASK_CMD_ID_8814B) << BIT_SHIFT_CMD_ID_8814B) +#define BITS_CMD_ID_8814B (BIT_MASK_CMD_ID_8814B << BIT_SHIFT_CMD_ID_8814B) +#define BIT_CLEAR_CMD_ID_8814B(x) ((x) & (~BITS_CMD_ID_8814B)) +#define BIT_GET_CMD_ID_8814B(x) \ + (((x) >> BIT_SHIFT_CMD_ID_8814B) & BIT_MASK_CMD_ID_8814B) +#define BIT_SET_CMD_ID_8814B(x, v) \ + (BIT_CLEAR_CMD_ID_8814B(x) | BIT_CMD_ID_8814B(v)) #define BIT_SHIFT_BT_DATA_8814B 0 #define BIT_MASK_BT_DATA_8814B 0xff -#define BIT_BT_DATA_8814B(x) (((x) & BIT_MASK_BT_DATA_8814B) << BIT_SHIFT_BT_DATA_8814B) -#define BIT_GET_BT_DATA_8814B(x) (((x) >> BIT_SHIFT_BT_DATA_8814B) & BIT_MASK_BT_DATA_8814B) - - +#define BIT_BT_DATA_8814B(x) \ + (((x) & BIT_MASK_BT_DATA_8814B) << BIT_SHIFT_BT_DATA_8814B) +#define BITS_BT_DATA_8814B (BIT_MASK_BT_DATA_8814B << BIT_SHIFT_BT_DATA_8814B) +#define BIT_CLEAR_BT_DATA_8814B(x) ((x) & (~BITS_BT_DATA_8814B)) +#define BIT_GET_BT_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_BT_DATA_8814B) & BIT_MASK_BT_DATA_8814B) +#define BIT_SET_BT_DATA_8814B(x, v) \ + (BIT_CLEAR_BT_DATA_8814B(x) | BIT_BT_DATA_8814B(v)) /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8814B */ #define BIT_SHIFT_WLAN_RPT_TO_8814B 0 #define BIT_MASK_WLAN_RPT_TO_8814B 0xff -#define BIT_WLAN_RPT_TO_8814B(x) (((x) & BIT_MASK_WLAN_RPT_TO_8814B) << BIT_SHIFT_WLAN_RPT_TO_8814B) -#define BIT_GET_WLAN_RPT_TO_8814B(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8814B) & BIT_MASK_WLAN_RPT_TO_8814B) - - +#define BIT_WLAN_RPT_TO_8814B(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO_8814B) << BIT_SHIFT_WLAN_RPT_TO_8814B) +#define BITS_WLAN_RPT_TO_8814B \ + (BIT_MASK_WLAN_RPT_TO_8814B << BIT_SHIFT_WLAN_RPT_TO_8814B) +#define BIT_CLEAR_WLAN_RPT_TO_8814B(x) ((x) & (~BITS_WLAN_RPT_TO_8814B)) +#define BIT_GET_WLAN_RPT_TO_8814B(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO_8814B) & BIT_MASK_WLAN_RPT_TO_8814B) +#define BIT_SET_WLAN_RPT_TO_8814B(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO_8814B(x) | BIT_WLAN_RPT_TO_8814B(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8814B */ #define BIT_SHIFT_ISOLATION_CHK_0_8814B 1 #define BIT_MASK_ISOLATION_CHK_0_8814B 0x7fffff -#define BIT_ISOLATION_CHK_0_8814B(x) (((x) & BIT_MASK_ISOLATION_CHK_0_8814B) << BIT_SHIFT_ISOLATION_CHK_0_8814B) -#define BIT_GET_ISOLATION_CHK_0_8814B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8814B) & BIT_MASK_ISOLATION_CHK_0_8814B) - +#define BIT_ISOLATION_CHK_0_8814B(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_0_8814B) \ + << BIT_SHIFT_ISOLATION_CHK_0_8814B) +#define BITS_ISOLATION_CHK_0_8814B \ + (BIT_MASK_ISOLATION_CHK_0_8814B << BIT_SHIFT_ISOLATION_CHK_0_8814B) +#define BIT_CLEAR_ISOLATION_CHK_0_8814B(x) ((x) & (~BITS_ISOLATION_CHK_0_8814B)) +#define BIT_GET_ISOLATION_CHK_0_8814B(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8814B) & \ + BIT_MASK_ISOLATION_CHK_0_8814B) +#define BIT_SET_ISOLATION_CHK_0_8814B(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_0_8814B(x) | BIT_ISOLATION_CHK_0_8814B(v)) #define BIT_ISOLATION_EN_8814B BIT(0) @@ -10747,19 +24746,33 @@ #define BIT_SHIFT_ISOLATION_CHK_1_8814B 0 #define BIT_MASK_ISOLATION_CHK_1_8814B 0xffffffffL -#define BIT_ISOLATION_CHK_1_8814B(x) (((x) & BIT_MASK_ISOLATION_CHK_1_8814B) << BIT_SHIFT_ISOLATION_CHK_1_8814B) -#define BIT_GET_ISOLATION_CHK_1_8814B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8814B) & BIT_MASK_ISOLATION_CHK_1_8814B) - - +#define BIT_ISOLATION_CHK_1_8814B(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_1_8814B) \ + << BIT_SHIFT_ISOLATION_CHK_1_8814B) +#define BITS_ISOLATION_CHK_1_8814B \ + (BIT_MASK_ISOLATION_CHK_1_8814B << BIT_SHIFT_ISOLATION_CHK_1_8814B) +#define BIT_CLEAR_ISOLATION_CHK_1_8814B(x) ((x) & (~BITS_ISOLATION_CHK_1_8814B)) +#define BIT_GET_ISOLATION_CHK_1_8814B(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8814B) & \ + BIT_MASK_ISOLATION_CHK_1_8814B) +#define BIT_SET_ISOLATION_CHK_1_8814B(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_1_8814B(x) | BIT_ISOLATION_CHK_1_8814B(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8814B */ #define BIT_SHIFT_ISOLATION_CHK_2_8814B 0 #define BIT_MASK_ISOLATION_CHK_2_8814B 0xffffff -#define BIT_ISOLATION_CHK_2_8814B(x) (((x) & BIT_MASK_ISOLATION_CHK_2_8814B) << BIT_SHIFT_ISOLATION_CHK_2_8814B) -#define BIT_GET_ISOLATION_CHK_2_8814B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8814B) & BIT_MASK_ISOLATION_CHK_2_8814B) - - +#define BIT_ISOLATION_CHK_2_8814B(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_2_8814B) \ + << BIT_SHIFT_ISOLATION_CHK_2_8814B) +#define BITS_ISOLATION_CHK_2_8814B \ + (BIT_MASK_ISOLATION_CHK_2_8814B << BIT_SHIFT_ISOLATION_CHK_2_8814B) +#define BIT_CLEAR_ISOLATION_CHK_2_8814B(x) ((x) & (~BITS_ISOLATION_CHK_2_8814B)) +#define BIT_GET_ISOLATION_CHK_2_8814B(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8814B) & \ + BIT_MASK_ISOLATION_CHK_2_8814B) +#define BIT_SET_ISOLATION_CHK_2_8814B(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_2_8814B(x) | BIT_ISOLATION_CHK_2_8814B(v)) /* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8814B */ #define BIT_BT_HID_ISR_8814B BIT(7) @@ -10775,25 +24788,45 @@ #define BIT_SHIFT_BT_TIME_8814B 6 #define BIT_MASK_BT_TIME_8814B 0x3ffffff -#define BIT_BT_TIME_8814B(x) (((x) & BIT_MASK_BT_TIME_8814B) << BIT_SHIFT_BT_TIME_8814B) -#define BIT_GET_BT_TIME_8814B(x) (((x) >> BIT_SHIFT_BT_TIME_8814B) & BIT_MASK_BT_TIME_8814B) - - +#define BIT_BT_TIME_8814B(x) \ + (((x) & BIT_MASK_BT_TIME_8814B) << BIT_SHIFT_BT_TIME_8814B) +#define BITS_BT_TIME_8814B (BIT_MASK_BT_TIME_8814B << BIT_SHIFT_BT_TIME_8814B) +#define BIT_CLEAR_BT_TIME_8814B(x) ((x) & (~BITS_BT_TIME_8814B)) +#define BIT_GET_BT_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_BT_TIME_8814B) & BIT_MASK_BT_TIME_8814B) +#define BIT_SET_BT_TIME_8814B(x, v) \ + (BIT_CLEAR_BT_TIME_8814B(x) | BIT_BT_TIME_8814B(v)) #define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B 0 #define BIT_MASK_BT_RPT_SAMPLE_RATE_8814B 0x3f -#define BIT_BT_RPT_SAMPLE_RATE_8814B(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8814B) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) -#define BIT_GET_BT_RPT_SAMPLE_RATE_8814B(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) & BIT_MASK_BT_RPT_SAMPLE_RATE_8814B) - - +#define BIT_BT_RPT_SAMPLE_RATE_8814B(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8814B) \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) +#define BITS_BT_RPT_SAMPLE_RATE_8814B \ + (BIT_MASK_BT_RPT_SAMPLE_RATE_8814B \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8814B(x) \ + ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8814B)) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8814B(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) & \ + BIT_MASK_BT_RPT_SAMPLE_RATE_8814B) +#define BIT_SET_BT_RPT_SAMPLE_RATE_8814B(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8814B(x) | \ + BIT_BT_RPT_SAMPLE_RATE_8814B(v)) /* 2 REG_BT_ACT_REGISTER_8814B */ #define BIT_SHIFT_BT_EISR_EN_8814B 16 #define BIT_MASK_BT_EISR_EN_8814B 0xff -#define BIT_BT_EISR_EN_8814B(x) (((x) & BIT_MASK_BT_EISR_EN_8814B) << BIT_SHIFT_BT_EISR_EN_8814B) -#define BIT_GET_BT_EISR_EN_8814B(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8814B) & BIT_MASK_BT_EISR_EN_8814B) - +#define BIT_BT_EISR_EN_8814B(x) \ + (((x) & BIT_MASK_BT_EISR_EN_8814B) << BIT_SHIFT_BT_EISR_EN_8814B) +#define BITS_BT_EISR_EN_8814B \ + (BIT_MASK_BT_EISR_EN_8814B << BIT_SHIFT_BT_EISR_EN_8814B) +#define BIT_CLEAR_BT_EISR_EN_8814B(x) ((x) & (~BITS_BT_EISR_EN_8814B)) +#define BIT_GET_BT_EISR_EN_8814B(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN_8814B) & BIT_MASK_BT_EISR_EN_8814B) +#define BIT_SET_BT_EISR_EN_8814B(x, v) \ + (BIT_CLEAR_BT_EISR_EN_8814B(x) | BIT_BT_EISR_EN_8814B(v)) #define BIT_BT_ACT_FALLING_ISR_8814B BIT(10) #define BIT_BT_ACT_RISING_ISR_8814B BIT(9) @@ -10801,19 +24834,29 @@ #define BIT_SHIFT_BT_CH_8814B 0 #define BIT_MASK_BT_CH_8814B 0xff -#define BIT_BT_CH_8814B(x) (((x) & BIT_MASK_BT_CH_8814B) << BIT_SHIFT_BT_CH_8814B) -#define BIT_GET_BT_CH_8814B(x) (((x) >> BIT_SHIFT_BT_CH_8814B) & BIT_MASK_BT_CH_8814B) - - +#define BIT_BT_CH_8814B(x) \ + (((x) & BIT_MASK_BT_CH_8814B) << BIT_SHIFT_BT_CH_8814B) +#define BITS_BT_CH_8814B (BIT_MASK_BT_CH_8814B << BIT_SHIFT_BT_CH_8814B) +#define BIT_CLEAR_BT_CH_8814B(x) ((x) & (~BITS_BT_CH_8814B)) +#define BIT_GET_BT_CH_8814B(x) \ + (((x) >> BIT_SHIFT_BT_CH_8814B) & BIT_MASK_BT_CH_8814B) +#define BIT_SET_BT_CH_8814B(x, v) \ + (BIT_CLEAR_BT_CH_8814B(x) | BIT_BT_CH_8814B(v)) /* 2 REG_OBFF_CTRL_BASIC_8814B */ #define BIT_OBFF_EN_V1_8814B BIT(31) #define BIT_SHIFT_OBFF_STATE_V1_8814B 28 #define BIT_MASK_OBFF_STATE_V1_8814B 0x3 -#define BIT_OBFF_STATE_V1_8814B(x) (((x) & BIT_MASK_OBFF_STATE_V1_8814B) << BIT_SHIFT_OBFF_STATE_V1_8814B) -#define BIT_GET_OBFF_STATE_V1_8814B(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8814B) & BIT_MASK_OBFF_STATE_V1_8814B) - +#define BIT_OBFF_STATE_V1_8814B(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1_8814B) << BIT_SHIFT_OBFF_STATE_V1_8814B) +#define BITS_OBFF_STATE_V1_8814B \ + (BIT_MASK_OBFF_STATE_V1_8814B << BIT_SHIFT_OBFF_STATE_V1_8814B) +#define BIT_CLEAR_OBFF_STATE_V1_8814B(x) ((x) & (~BITS_OBFF_STATE_V1_8814B)) +#define BIT_GET_OBFF_STATE_V1_8814B(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1_8814B) & BIT_MASK_OBFF_STATE_V1_8814B) +#define BIT_SET_OBFF_STATE_V1_8814B(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1_8814B(x) | BIT_OBFF_STATE_V1_8814B(v)) #define BIT_OBFF_ACT_RXDMA_EN_8814B BIT(27) #define BIT_OBFF_BLOCK_INT_EN_8814B BIT(26) @@ -10822,30 +24865,51 @@ #define BIT_SHIFT_WAKE_MAX_PLS_8814B 20 #define BIT_MASK_WAKE_MAX_PLS_8814B 0x7 -#define BIT_WAKE_MAX_PLS_8814B(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8814B) << BIT_SHIFT_WAKE_MAX_PLS_8814B) -#define BIT_GET_WAKE_MAX_PLS_8814B(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8814B) & BIT_MASK_WAKE_MAX_PLS_8814B) - - +#define BIT_WAKE_MAX_PLS_8814B(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS_8814B) << BIT_SHIFT_WAKE_MAX_PLS_8814B) +#define BITS_WAKE_MAX_PLS_8814B \ + (BIT_MASK_WAKE_MAX_PLS_8814B << BIT_SHIFT_WAKE_MAX_PLS_8814B) +#define BIT_CLEAR_WAKE_MAX_PLS_8814B(x) ((x) & (~BITS_WAKE_MAX_PLS_8814B)) +#define BIT_GET_WAKE_MAX_PLS_8814B(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8814B) & BIT_MASK_WAKE_MAX_PLS_8814B) +#define BIT_SET_WAKE_MAX_PLS_8814B(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS_8814B(x) | BIT_WAKE_MAX_PLS_8814B(v)) #define BIT_SHIFT_WAKE_MIN_PLS_8814B 16 #define BIT_MASK_WAKE_MIN_PLS_8814B 0x7 -#define BIT_WAKE_MIN_PLS_8814B(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8814B) << BIT_SHIFT_WAKE_MIN_PLS_8814B) -#define BIT_GET_WAKE_MIN_PLS_8814B(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8814B) & BIT_MASK_WAKE_MIN_PLS_8814B) - - +#define BIT_WAKE_MIN_PLS_8814B(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS_8814B) << BIT_SHIFT_WAKE_MIN_PLS_8814B) +#define BITS_WAKE_MIN_PLS_8814B \ + (BIT_MASK_WAKE_MIN_PLS_8814B << BIT_SHIFT_WAKE_MIN_PLS_8814B) +#define BIT_CLEAR_WAKE_MIN_PLS_8814B(x) ((x) & (~BITS_WAKE_MIN_PLS_8814B)) +#define BIT_GET_WAKE_MIN_PLS_8814B(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8814B) & BIT_MASK_WAKE_MIN_PLS_8814B) +#define BIT_SET_WAKE_MIN_PLS_8814B(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS_8814B(x) | BIT_WAKE_MIN_PLS_8814B(v)) #define BIT_SHIFT_WAKE_MAX_F2F_8814B 12 #define BIT_MASK_WAKE_MAX_F2F_8814B 0x7 -#define BIT_WAKE_MAX_F2F_8814B(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8814B) << BIT_SHIFT_WAKE_MAX_F2F_8814B) -#define BIT_GET_WAKE_MAX_F2F_8814B(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8814B) & BIT_MASK_WAKE_MAX_F2F_8814B) - - +#define BIT_WAKE_MAX_F2F_8814B(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F_8814B) << BIT_SHIFT_WAKE_MAX_F2F_8814B) +#define BITS_WAKE_MAX_F2F_8814B \ + (BIT_MASK_WAKE_MAX_F2F_8814B << BIT_SHIFT_WAKE_MAX_F2F_8814B) +#define BIT_CLEAR_WAKE_MAX_F2F_8814B(x) ((x) & (~BITS_WAKE_MAX_F2F_8814B)) +#define BIT_GET_WAKE_MAX_F2F_8814B(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8814B) & BIT_MASK_WAKE_MAX_F2F_8814B) +#define BIT_SET_WAKE_MAX_F2F_8814B(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F_8814B(x) | BIT_WAKE_MAX_F2F_8814B(v)) #define BIT_SHIFT_WAKE_MIN_F2F_8814B 8 #define BIT_MASK_WAKE_MIN_F2F_8814B 0x7 -#define BIT_WAKE_MIN_F2F_8814B(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8814B) << BIT_SHIFT_WAKE_MIN_F2F_8814B) -#define BIT_GET_WAKE_MIN_F2F_8814B(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8814B) & BIT_MASK_WAKE_MIN_F2F_8814B) - +#define BIT_WAKE_MIN_F2F_8814B(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F_8814B) << BIT_SHIFT_WAKE_MIN_F2F_8814B) +#define BITS_WAKE_MIN_F2F_8814B \ + (BIT_MASK_WAKE_MIN_F2F_8814B << BIT_SHIFT_WAKE_MIN_F2F_8814B) +#define BIT_CLEAR_WAKE_MIN_F2F_8814B(x) ((x) & (~BITS_WAKE_MIN_F2F_8814B)) +#define BIT_GET_WAKE_MIN_F2F_8814B(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8814B) & BIT_MASK_WAKE_MIN_F2F_8814B) +#define BIT_SET_WAKE_MIN_F2F_8814B(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F_8814B(x) | BIT_WAKE_MIN_F2F_8814B(v)) #define BIT_APP_CPU_ACT_V1_8814B BIT(3) #define BIT_APP_OBFF_V1_8814B BIT(2) @@ -10856,31 +24920,65 @@ #define BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B 24 #define BIT_MASK_RX_HIGH_TIMER_IDX_8814B 0x7 -#define BIT_RX_HIGH_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8814B) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) -#define BIT_GET_RX_HIGH_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) & BIT_MASK_RX_HIGH_TIMER_IDX_8814B) - - +#define BIT_RX_HIGH_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8814B) \ + << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) +#define BITS_RX_HIGH_TIMER_IDX_8814B \ + (BIT_MASK_RX_HIGH_TIMER_IDX_8814B << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_RX_HIGH_TIMER_IDX_8814B)) +#define BIT_GET_RX_HIGH_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) & \ + BIT_MASK_RX_HIGH_TIMER_IDX_8814B) +#define BIT_SET_RX_HIGH_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX_8814B(x) | BIT_RX_HIGH_TIMER_IDX_8814B(v)) #define BIT_SHIFT_RX_MED_TIMER_IDX_8814B 16 #define BIT_MASK_RX_MED_TIMER_IDX_8814B 0x7 -#define BIT_RX_MED_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8814B) << BIT_SHIFT_RX_MED_TIMER_IDX_8814B) -#define BIT_GET_RX_MED_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8814B) & BIT_MASK_RX_MED_TIMER_IDX_8814B) - - +#define BIT_RX_MED_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX_8814B) \ + << BIT_SHIFT_RX_MED_TIMER_IDX_8814B) +#define BITS_RX_MED_TIMER_IDX_8814B \ + (BIT_MASK_RX_MED_TIMER_IDX_8814B << BIT_SHIFT_RX_MED_TIMER_IDX_8814B) +#define BIT_CLEAR_RX_MED_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_RX_MED_TIMER_IDX_8814B)) +#define BIT_GET_RX_MED_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8814B) & \ + BIT_MASK_RX_MED_TIMER_IDX_8814B) +#define BIT_SET_RX_MED_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX_8814B(x) | BIT_RX_MED_TIMER_IDX_8814B(v)) #define BIT_SHIFT_RX_LOW_TIMER_IDX_8814B 8 #define BIT_MASK_RX_LOW_TIMER_IDX_8814B 0x7 -#define BIT_RX_LOW_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8814B) << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) -#define BIT_GET_RX_LOW_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) & BIT_MASK_RX_LOW_TIMER_IDX_8814B) - - +#define BIT_RX_LOW_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8814B) \ + << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) +#define BITS_RX_LOW_TIMER_IDX_8814B \ + (BIT_MASK_RX_LOW_TIMER_IDX_8814B << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) +#define BIT_CLEAR_RX_LOW_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_RX_LOW_TIMER_IDX_8814B)) +#define BIT_GET_RX_LOW_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) & \ + BIT_MASK_RX_LOW_TIMER_IDX_8814B) +#define BIT_SET_RX_LOW_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX_8814B(x) | BIT_RX_LOW_TIMER_IDX_8814B(v)) #define BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B 0 #define BIT_MASK_OBFF_INT_TIMER_IDX_8814B 0x7 -#define BIT_OBFF_INT_TIMER_IDX_8814B(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8814B) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) -#define BIT_GET_OBFF_INT_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) & BIT_MASK_OBFF_INT_TIMER_IDX_8814B) - - +#define BIT_OBFF_INT_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8814B) \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) +#define BITS_OBFF_INT_TIMER_IDX_8814B \ + (BIT_MASK_OBFF_INT_TIMER_IDX_8814B \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_OBFF_INT_TIMER_IDX_8814B)) +#define BIT_GET_OBFF_INT_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) & \ + BIT_MASK_OBFF_INT_TIMER_IDX_8814B) +#define BIT_SET_OBFF_INT_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX_8814B(x) | \ + BIT_OBFF_INT_TIMER_IDX_8814B(v)) /* 2 REG_LTR_CTRL_BASIC_8814B */ #define BIT_LTR_EN_V1_8814B BIT(31) @@ -10896,180 +24994,340 @@ #define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B 20 #define BIT_MASK_HIGH_RATE_TRIG_SEL_8814B 0x3 -#define BIT_HIGH_RATE_TRIG_SEL_8814B(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8814B) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) -#define BIT_GET_HIGH_RATE_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) & BIT_MASK_HIGH_RATE_TRIG_SEL_8814B) - - +#define BIT_HIGH_RATE_TRIG_SEL_8814B(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8814B) \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) +#define BITS_HIGH_RATE_TRIG_SEL_8814B \ + (BIT_MASK_HIGH_RATE_TRIG_SEL_8814B \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8814B(x) \ + ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8814B)) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) & \ + BIT_MASK_HIGH_RATE_TRIG_SEL_8814B) +#define BIT_SET_HIGH_RATE_TRIG_SEL_8814B(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8814B(x) | \ + BIT_HIGH_RATE_TRIG_SEL_8814B(v)) #define BIT_SHIFT_MED_RATE_TRIG_SEL_8814B 18 #define BIT_MASK_MED_RATE_TRIG_SEL_8814B 0x3 -#define BIT_MED_RATE_TRIG_SEL_8814B(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8814B) << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) -#define BIT_GET_MED_RATE_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) & BIT_MASK_MED_RATE_TRIG_SEL_8814B) - - +#define BIT_MED_RATE_TRIG_SEL_8814B(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8814B) \ + << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) +#define BITS_MED_RATE_TRIG_SEL_8814B \ + (BIT_MASK_MED_RATE_TRIG_SEL_8814B << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) +#define BIT_CLEAR_MED_RATE_TRIG_SEL_8814B(x) \ + ((x) & (~BITS_MED_RATE_TRIG_SEL_8814B)) +#define BIT_GET_MED_RATE_TRIG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) & \ + BIT_MASK_MED_RATE_TRIG_SEL_8814B) +#define BIT_SET_MED_RATE_TRIG_SEL_8814B(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL_8814B(x) | BIT_MED_RATE_TRIG_SEL_8814B(v)) #define BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B 16 #define BIT_MASK_LOW_RATE_TRIG_SEL_8814B 0x3 -#define BIT_LOW_RATE_TRIG_SEL_8814B(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8814B) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) -#define BIT_GET_LOW_RATE_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) & BIT_MASK_LOW_RATE_TRIG_SEL_8814B) - - +#define BIT_LOW_RATE_TRIG_SEL_8814B(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8814B) \ + << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) +#define BITS_LOW_RATE_TRIG_SEL_8814B \ + (BIT_MASK_LOW_RATE_TRIG_SEL_8814B << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8814B(x) \ + ((x) & (~BITS_LOW_RATE_TRIG_SEL_8814B)) +#define BIT_GET_LOW_RATE_TRIG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) & \ + BIT_MASK_LOW_RATE_TRIG_SEL_8814B) +#define BIT_SET_LOW_RATE_TRIG_SEL_8814B(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL_8814B(x) | BIT_LOW_RATE_TRIG_SEL_8814B(v)) #define BIT_SHIFT_HIGH_RATE_BD_IDX_8814B 8 #define BIT_MASK_HIGH_RATE_BD_IDX_8814B 0x7f -#define BIT_HIGH_RATE_BD_IDX_8814B(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8814B) << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) -#define BIT_GET_HIGH_RATE_BD_IDX_8814B(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) & BIT_MASK_HIGH_RATE_BD_IDX_8814B) - - +#define BIT_HIGH_RATE_BD_IDX_8814B(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8814B) \ + << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) +#define BITS_HIGH_RATE_BD_IDX_8814B \ + (BIT_MASK_HIGH_RATE_BD_IDX_8814B << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) +#define BIT_CLEAR_HIGH_RATE_BD_IDX_8814B(x) \ + ((x) & (~BITS_HIGH_RATE_BD_IDX_8814B)) +#define BIT_GET_HIGH_RATE_BD_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) & \ + BIT_MASK_HIGH_RATE_BD_IDX_8814B) +#define BIT_SET_HIGH_RATE_BD_IDX_8814B(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX_8814B(x) | BIT_HIGH_RATE_BD_IDX_8814B(v)) #define BIT_SHIFT_LOW_RATE_BD_IDX_8814B 0 #define BIT_MASK_LOW_RATE_BD_IDX_8814B 0x7f -#define BIT_LOW_RATE_BD_IDX_8814B(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8814B) << BIT_SHIFT_LOW_RATE_BD_IDX_8814B) -#define BIT_GET_LOW_RATE_BD_IDX_8814B(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8814B) & BIT_MASK_LOW_RATE_BD_IDX_8814B) - - +#define BIT_LOW_RATE_BD_IDX_8814B(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX_8814B) \ + << BIT_SHIFT_LOW_RATE_BD_IDX_8814B) +#define BITS_LOW_RATE_BD_IDX_8814B \ + (BIT_MASK_LOW_RATE_BD_IDX_8814B << BIT_SHIFT_LOW_RATE_BD_IDX_8814B) +#define BIT_CLEAR_LOW_RATE_BD_IDX_8814B(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8814B)) +#define BIT_GET_LOW_RATE_BD_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8814B) & \ + BIT_MASK_LOW_RATE_BD_IDX_8814B) +#define BIT_SET_LOW_RATE_BD_IDX_8814B(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX_8814B(x) | BIT_LOW_RATE_BD_IDX_8814B(v)) /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8814B */ #define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B 24 #define BIT_MASK_RX_EMPTY_TIMER_IDX_8814B 0x7 -#define BIT_RX_EMPTY_TIMER_IDX_8814B(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8814B) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) -#define BIT_GET_RX_EMPTY_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) & BIT_MASK_RX_EMPTY_TIMER_IDX_8814B) - - +#define BIT_RX_EMPTY_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8814B) \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) +#define BITS_RX_EMPTY_TIMER_IDX_8814B \ + (BIT_MASK_RX_EMPTY_TIMER_IDX_8814B \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8814B)) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) & \ + BIT_MASK_RX_EMPTY_TIMER_IDX_8814B) +#define BIT_SET_RX_EMPTY_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8814B(x) | \ + BIT_RX_EMPTY_TIMER_IDX_8814B(v)) #define BIT_SHIFT_RX_AFULL_TH_IDX_8814B 20 #define BIT_MASK_RX_AFULL_TH_IDX_8814B 0x7 -#define BIT_RX_AFULL_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8814B) << BIT_SHIFT_RX_AFULL_TH_IDX_8814B) -#define BIT_GET_RX_AFULL_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8814B) & BIT_MASK_RX_AFULL_TH_IDX_8814B) - - +#define BIT_RX_AFULL_TH_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX_8814B) \ + << BIT_SHIFT_RX_AFULL_TH_IDX_8814B) +#define BITS_RX_AFULL_TH_IDX_8814B \ + (BIT_MASK_RX_AFULL_TH_IDX_8814B << BIT_SHIFT_RX_AFULL_TH_IDX_8814B) +#define BIT_CLEAR_RX_AFULL_TH_IDX_8814B(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8814B)) +#define BIT_GET_RX_AFULL_TH_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8814B) & \ + BIT_MASK_RX_AFULL_TH_IDX_8814B) +#define BIT_SET_RX_AFULL_TH_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX_8814B(x) | BIT_RX_AFULL_TH_IDX_8814B(v)) #define BIT_SHIFT_RX_HIGH_TH_IDX_8814B 16 #define BIT_MASK_RX_HIGH_TH_IDX_8814B 0x7 -#define BIT_RX_HIGH_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8814B) << BIT_SHIFT_RX_HIGH_TH_IDX_8814B) -#define BIT_GET_RX_HIGH_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8814B) & BIT_MASK_RX_HIGH_TH_IDX_8814B) - - +#define BIT_RX_HIGH_TH_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX_8814B) \ + << BIT_SHIFT_RX_HIGH_TH_IDX_8814B) +#define BITS_RX_HIGH_TH_IDX_8814B \ + (BIT_MASK_RX_HIGH_TH_IDX_8814B << BIT_SHIFT_RX_HIGH_TH_IDX_8814B) +#define BIT_CLEAR_RX_HIGH_TH_IDX_8814B(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8814B)) +#define BIT_GET_RX_HIGH_TH_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8814B) & \ + BIT_MASK_RX_HIGH_TH_IDX_8814B) +#define BIT_SET_RX_HIGH_TH_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX_8814B(x) | BIT_RX_HIGH_TH_IDX_8814B(v)) #define BIT_SHIFT_RX_MED_TH_IDX_8814B 12 #define BIT_MASK_RX_MED_TH_IDX_8814B 0x7 -#define BIT_RX_MED_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8814B) << BIT_SHIFT_RX_MED_TH_IDX_8814B) -#define BIT_GET_RX_MED_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8814B) & BIT_MASK_RX_MED_TH_IDX_8814B) - - +#define BIT_RX_MED_TH_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX_8814B) << BIT_SHIFT_RX_MED_TH_IDX_8814B) +#define BITS_RX_MED_TH_IDX_8814B \ + (BIT_MASK_RX_MED_TH_IDX_8814B << BIT_SHIFT_RX_MED_TH_IDX_8814B) +#define BIT_CLEAR_RX_MED_TH_IDX_8814B(x) ((x) & (~BITS_RX_MED_TH_IDX_8814B)) +#define BIT_GET_RX_MED_TH_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8814B) & BIT_MASK_RX_MED_TH_IDX_8814B) +#define BIT_SET_RX_MED_TH_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX_8814B(x) | BIT_RX_MED_TH_IDX_8814B(v)) #define BIT_SHIFT_RX_LOW_TH_IDX_8814B 8 #define BIT_MASK_RX_LOW_TH_IDX_8814B 0x7 -#define BIT_RX_LOW_TH_IDX_8814B(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8814B) << BIT_SHIFT_RX_LOW_TH_IDX_8814B) -#define BIT_GET_RX_LOW_TH_IDX_8814B(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8814B) & BIT_MASK_RX_LOW_TH_IDX_8814B) - - +#define BIT_RX_LOW_TH_IDX_8814B(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX_8814B) << BIT_SHIFT_RX_LOW_TH_IDX_8814B) +#define BITS_RX_LOW_TH_IDX_8814B \ + (BIT_MASK_RX_LOW_TH_IDX_8814B << BIT_SHIFT_RX_LOW_TH_IDX_8814B) +#define BIT_CLEAR_RX_LOW_TH_IDX_8814B(x) ((x) & (~BITS_RX_LOW_TH_IDX_8814B)) +#define BIT_GET_RX_LOW_TH_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8814B) & BIT_MASK_RX_LOW_TH_IDX_8814B) +#define BIT_SET_RX_LOW_TH_IDX_8814B(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX_8814B(x) | BIT_RX_LOW_TH_IDX_8814B(v)) #define BIT_SHIFT_LTR_SPACE_IDX_8814B 4 #define BIT_MASK_LTR_SPACE_IDX_8814B 0x3 -#define BIT_LTR_SPACE_IDX_8814B(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8814B) << BIT_SHIFT_LTR_SPACE_IDX_8814B) -#define BIT_GET_LTR_SPACE_IDX_8814B(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8814B) & BIT_MASK_LTR_SPACE_IDX_8814B) - - +#define BIT_LTR_SPACE_IDX_8814B(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX_8814B) << BIT_SHIFT_LTR_SPACE_IDX_8814B) +#define BITS_LTR_SPACE_IDX_8814B \ + (BIT_MASK_LTR_SPACE_IDX_8814B << BIT_SHIFT_LTR_SPACE_IDX_8814B) +#define BIT_CLEAR_LTR_SPACE_IDX_8814B(x) ((x) & (~BITS_LTR_SPACE_IDX_8814B)) +#define BIT_GET_LTR_SPACE_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8814B) & BIT_MASK_LTR_SPACE_IDX_8814B) +#define BIT_SET_LTR_SPACE_IDX_8814B(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX_8814B(x) | BIT_LTR_SPACE_IDX_8814B(v)) #define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B 0 #define BIT_MASK_LTR_IDLE_TIMER_IDX_8814B 0x7 -#define BIT_LTR_IDLE_TIMER_IDX_8814B(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8814B) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) -#define BIT_GET_LTR_IDLE_TIMER_IDX_8814B(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) & BIT_MASK_LTR_IDLE_TIMER_IDX_8814B) - - +#define BIT_LTR_IDLE_TIMER_IDX_8814B(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8814B) \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) +#define BITS_LTR_IDLE_TIMER_IDX_8814B \ + (BIT_MASK_LTR_IDLE_TIMER_IDX_8814B \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8814B(x) \ + ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8814B)) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8814B(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) & \ + BIT_MASK_LTR_IDLE_TIMER_IDX_8814B) +#define BIT_SET_LTR_IDLE_TIMER_IDX_8814B(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8814B(x) | \ + BIT_LTR_IDLE_TIMER_IDX_8814B(v)) /* 2 REG_LTR_IDLE_LATENCY_V1_8814B */ #define BIT_SHIFT_LTR_IDLE_L_8814B 0 #define BIT_MASK_LTR_IDLE_L_8814B 0xffffffffL -#define BIT_LTR_IDLE_L_8814B(x) (((x) & BIT_MASK_LTR_IDLE_L_8814B) << BIT_SHIFT_LTR_IDLE_L_8814B) -#define BIT_GET_LTR_IDLE_L_8814B(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8814B) & BIT_MASK_LTR_IDLE_L_8814B) - - +#define BIT_LTR_IDLE_L_8814B(x) \ + (((x) & BIT_MASK_LTR_IDLE_L_8814B) << BIT_SHIFT_LTR_IDLE_L_8814B) +#define BITS_LTR_IDLE_L_8814B \ + (BIT_MASK_LTR_IDLE_L_8814B << BIT_SHIFT_LTR_IDLE_L_8814B) +#define BIT_CLEAR_LTR_IDLE_L_8814B(x) ((x) & (~BITS_LTR_IDLE_L_8814B)) +#define BIT_GET_LTR_IDLE_L_8814B(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L_8814B) & BIT_MASK_LTR_IDLE_L_8814B) +#define BIT_SET_LTR_IDLE_L_8814B(x, v) \ + (BIT_CLEAR_LTR_IDLE_L_8814B(x) | BIT_LTR_IDLE_L_8814B(v)) /* 2 REG_LTR_ACTIVE_LATENCY_V1_8814B */ #define BIT_SHIFT_LTR_ACT_L_8814B 0 #define BIT_MASK_LTR_ACT_L_8814B 0xffffffffL -#define BIT_LTR_ACT_L_8814B(x) (((x) & BIT_MASK_LTR_ACT_L_8814B) << BIT_SHIFT_LTR_ACT_L_8814B) -#define BIT_GET_LTR_ACT_L_8814B(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8814B) & BIT_MASK_LTR_ACT_L_8814B) - - - -/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8814B */ - -#define BIT_SHIFT_TRAIN_STA_ADDR_0_8814B 0 -#define BIT_MASK_TRAIN_STA_ADDR_0_8814B 0xffffffffL -#define BIT_TRAIN_STA_ADDR_0_8814B(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8814B) << BIT_SHIFT_TRAIN_STA_ADDR_0_8814B) -#define BIT_GET_TRAIN_STA_ADDR_0_8814B(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8814B) & BIT_MASK_TRAIN_STA_ADDR_0_8814B) - - - -/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8814B */ +#define BIT_LTR_ACT_L_8814B(x) \ + (((x) & BIT_MASK_LTR_ACT_L_8814B) << BIT_SHIFT_LTR_ACT_L_8814B) +#define BITS_LTR_ACT_L_8814B \ + (BIT_MASK_LTR_ACT_L_8814B << BIT_SHIFT_LTR_ACT_L_8814B) +#define BIT_CLEAR_LTR_ACT_L_8814B(x) ((x) & (~BITS_LTR_ACT_L_8814B)) +#define BIT_GET_LTR_ACT_L_8814B(x) \ + (((x) >> BIT_SHIFT_LTR_ACT_L_8814B) & BIT_MASK_LTR_ACT_L_8814B) +#define BIT_SET_LTR_ACT_L_8814B(x, v) \ + (BIT_CLEAR_LTR_ACT_L_8814B(x) | BIT_LTR_ACT_L_8814B(v)) + +#define BIT_SHIFT_ANT_ADDR2_1_8814B 0 +#define BIT_MASK_ANT_ADDR2_1_8814B 0xffffffffL +#define BIT_ANT_ADDR2_1_8814B(x) \ + (((x) & BIT_MASK_ANT_ADDR2_1_8814B) << BIT_SHIFT_ANT_ADDR2_1_8814B) +#define BITS_ANT_ADDR2_1_8814B \ + (BIT_MASK_ANT_ADDR2_1_8814B << BIT_SHIFT_ANT_ADDR2_1_8814B) +#define BIT_CLEAR_ANT_ADDR2_1_8814B(x) ((x) & (~BITS_ANT_ADDR2_1_8814B)) +#define BIT_GET_ANT_ADDR2_1_8814B(x) \ + (((x) >> BIT_SHIFT_ANT_ADDR2_1_8814B) & BIT_MASK_ANT_ADDR2_1_8814B) +#define BIT_SET_ANT_ADDR2_1_8814B(x, v) \ + (BIT_CLEAR_ANT_ADDR2_1_8814B(x) | BIT_ANT_ADDR2_1_8814B(v)) + +/* 2 REG_SMART_ANT_CTRL_8814B */ +#define BIT_ANTTRN_SWITCH_8814B BIT(19) #define BIT_APPEND_MACID_IN_RESP_EN_1_8814B BIT(18) #define BIT_ADDR2_MATCH_EN_1_8814B BIT(17) #define BIT_ANTTRN_EN_1_8814B BIT(16) -#define BIT_SHIFT_TRAIN_STA_ADDR_1_8814B 0 -#define BIT_MASK_TRAIN_STA_ADDR_1_8814B 0xffff -#define BIT_TRAIN_STA_ADDR_1_8814B(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8814B) << BIT_SHIFT_TRAIN_STA_ADDR_1_8814B) -#define BIT_GET_TRAIN_STA_ADDR_1_8814B(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8814B) & BIT_MASK_TRAIN_STA_ADDR_1_8814B) - - - -/* 2 REG_WMAC_PKTCNT_RWD_8814B */ - -#define BIT_SHIFT_PKTCNT_BSSIDMAP_8814B 4 -#define BIT_MASK_PKTCNT_BSSIDMAP_8814B 0xf -#define BIT_PKTCNT_BSSIDMAP_8814B(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8814B) << BIT_SHIFT_PKTCNT_BSSIDMAP_8814B) -#define BIT_GET_PKTCNT_BSSIDMAP_8814B(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8814B) & BIT_MASK_PKTCNT_BSSIDMAP_8814B) - - -#define BIT_PKTCNT_CNTRST_8814B BIT(1) -#define BIT_PKTCNT_CNTEN_8814B BIT(0) - -/* 2 REG_WMAC_PKTCNT_CTRL_8814B */ -#define BIT_WMAC_PKTCNT_TRST_8814B BIT(9) -#define BIT_WMAC_PKTCNT_FEN_8814B BIT(8) - -#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8814B 0 -#define BIT_MASK_WMAC_PKTCNT_CFGAD_8814B 0xff -#define BIT_WMAC_PKTCNT_CFGAD_8814B(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8814B) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8814B) -#define BIT_GET_WMAC_PKTCNT_CFGAD_8814B(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8814B) & BIT_MASK_WMAC_PKTCNT_CFGAD_8814B) - - +#define BIT_SHIFT_ANT_ADDR2_2_8814B 0 +#define BIT_MASK_ANT_ADDR2_2_8814B 0xffff +#define BIT_ANT_ADDR2_2_8814B(x) \ + (((x) & BIT_MASK_ANT_ADDR2_2_8814B) << BIT_SHIFT_ANT_ADDR2_2_8814B) +#define BITS_ANT_ADDR2_2_8814B \ + (BIT_MASK_ANT_ADDR2_2_8814B << BIT_SHIFT_ANT_ADDR2_2_8814B) +#define BIT_CLEAR_ANT_ADDR2_2_8814B(x) ((x) & (~BITS_ANT_ADDR2_2_8814B)) +#define BIT_GET_ANT_ADDR2_2_8814B(x) \ + (((x) >> BIT_SHIFT_ANT_ADDR2_2_8814B) & BIT_MASK_ANT_ADDR2_2_8814B) +#define BIT_SET_ANT_ADDR2_2_8814B(x, v) \ + (BIT_CLEAR_ANT_ADDR2_2_8814B(x) | BIT_ANT_ADDR2_2_8814B(v)) + +/* 2 REG_CONTROL_FRAME_REPORT_8814B */ + +#define BIT_SHIFT_CONTROL_FRAME_REPORT_8814B 0 +#define BIT_MASK_CONTROL_FRAME_REPORT_8814B 0xffffffffL +#define BIT_CONTROL_FRAME_REPORT_8814B(x) \ + (((x) & BIT_MASK_CONTROL_FRAME_REPORT_8814B) \ + << BIT_SHIFT_CONTROL_FRAME_REPORT_8814B) +#define BITS_CONTROL_FRAME_REPORT_8814B \ + (BIT_MASK_CONTROL_FRAME_REPORT_8814B \ + << BIT_SHIFT_CONTROL_FRAME_REPORT_8814B) +#define BIT_CLEAR_CONTROL_FRAME_REPORT_8814B(x) \ + ((x) & (~BITS_CONTROL_FRAME_REPORT_8814B)) +#define BIT_GET_CONTROL_FRAME_REPORT_8814B(x) \ + (((x) >> BIT_SHIFT_CONTROL_FRAME_REPORT_8814B) & \ + BIT_MASK_CONTROL_FRAME_REPORT_8814B) +#define BIT_SET_CONTROL_FRAME_REPORT_8814B(x, v) \ + (BIT_CLEAR_CONTROL_FRAME_REPORT_8814B(x) | \ + BIT_CONTROL_FRAME_REPORT_8814B(v)) + +/* 2 REG_CONTROL_FRAME_CNT_CTRL_8814B */ +#define BIT_ALLCNTRST_8814B BIT(9) +#define BIT__ALLCNTEN_8814B BIT(8) + +#define BIT_SHIFT_ADDR_8814B 4 +#define BIT_MASK_ADDR_8814B 0xf +#define BIT_ADDR_8814B(x) (((x) & BIT_MASK_ADDR_8814B) << BIT_SHIFT_ADDR_8814B) +#define BITS_ADDR_8814B (BIT_MASK_ADDR_8814B << BIT_SHIFT_ADDR_8814B) +#define BIT_CLEAR_ADDR_8814B(x) ((x) & (~BITS_ADDR_8814B)) +#define BIT_GET_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_ADDR_8814B) & BIT_MASK_ADDR_8814B) +#define BIT_SET_ADDR_8814B(x, v) (BIT_CLEAR_ADDR_8814B(x) | BIT_ADDR_8814B(v)) + +#define BIT_SHIFT_CTRL_SEL_8814B 0 +#define BIT_MASK_CTRL_SEL_8814B 0xf +#define BIT_CTRL_SEL_8814B(x) \ + (((x) & BIT_MASK_CTRL_SEL_8814B) << BIT_SHIFT_CTRL_SEL_8814B) +#define BITS_CTRL_SEL_8814B \ + (BIT_MASK_CTRL_SEL_8814B << BIT_SHIFT_CTRL_SEL_8814B) +#define BIT_CLEAR_CTRL_SEL_8814B(x) ((x) & (~BITS_CTRL_SEL_8814B)) +#define BIT_GET_CTRL_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_CTRL_SEL_8814B) & BIT_MASK_CTRL_SEL_8814B) +#define BIT_SET_CTRL_SEL_8814B(x, v) \ + (BIT_CLEAR_CTRL_SEL_8814B(x) | BIT_CTRL_SEL_8814B(v)) /* 2 REG_IQ_DUMP_8814B */ -#define BIT_SHIFT_DUMP_OK_ADDR_8814B 15 -#define BIT_MASK_DUMP_OK_ADDR_8814B 0x1ffff -#define BIT_DUMP_OK_ADDR_8814B(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8814B) << BIT_SHIFT_DUMP_OK_ADDR_8814B) -#define BIT_GET_DUMP_OK_ADDR_8814B(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8814B) & BIT_MASK_DUMP_OK_ADDR_8814B) - - +#define BIT_SHIFT_DUMP_OK_ADDR_8814B 16 +#define BIT_MASK_DUMP_OK_ADDR_8814B 0xffff +#define BIT_DUMP_OK_ADDR_8814B(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR_8814B) << BIT_SHIFT_DUMP_OK_ADDR_8814B) +#define BITS_DUMP_OK_ADDR_8814B \ + (BIT_MASK_DUMP_OK_ADDR_8814B << BIT_SHIFT_DUMP_OK_ADDR_8814B) +#define BIT_CLEAR_DUMP_OK_ADDR_8814B(x) ((x) & (~BITS_DUMP_OK_ADDR_8814B)) +#define BIT_GET_DUMP_OK_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8814B) & BIT_MASK_DUMP_OK_ADDR_8814B) +#define BIT_SET_DUMP_OK_ADDR_8814B(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR_8814B(x) | BIT_DUMP_OK_ADDR_8814B(v)) #define BIT_SHIFT_R_TRIG_TIME_SEL_8814B 8 #define BIT_MASK_R_TRIG_TIME_SEL_8814B 0x7f -#define BIT_R_TRIG_TIME_SEL_8814B(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8814B) << BIT_SHIFT_R_TRIG_TIME_SEL_8814B) -#define BIT_GET_R_TRIG_TIME_SEL_8814B(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8814B) & BIT_MASK_R_TRIG_TIME_SEL_8814B) - - +#define BIT_R_TRIG_TIME_SEL_8814B(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL_8814B) \ + << BIT_SHIFT_R_TRIG_TIME_SEL_8814B) +#define BITS_R_TRIG_TIME_SEL_8814B \ + (BIT_MASK_R_TRIG_TIME_SEL_8814B << BIT_SHIFT_R_TRIG_TIME_SEL_8814B) +#define BIT_CLEAR_R_TRIG_TIME_SEL_8814B(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8814B)) +#define BIT_GET_R_TRIG_TIME_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8814B) & \ + BIT_MASK_R_TRIG_TIME_SEL_8814B) +#define BIT_SET_R_TRIG_TIME_SEL_8814B(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL_8814B(x) | BIT_R_TRIG_TIME_SEL_8814B(v)) #define BIT_SHIFT_R_MAC_TRIG_SEL_8814B 6 #define BIT_MASK_R_MAC_TRIG_SEL_8814B 0x3 -#define BIT_R_MAC_TRIG_SEL_8814B(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8814B) << BIT_SHIFT_R_MAC_TRIG_SEL_8814B) -#define BIT_GET_R_MAC_TRIG_SEL_8814B(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8814B) & BIT_MASK_R_MAC_TRIG_SEL_8814B) - +#define BIT_R_MAC_TRIG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL_8814B) \ + << BIT_SHIFT_R_MAC_TRIG_SEL_8814B) +#define BITS_R_MAC_TRIG_SEL_8814B \ + (BIT_MASK_R_MAC_TRIG_SEL_8814B << BIT_SHIFT_R_MAC_TRIG_SEL_8814B) +#define BIT_CLEAR_R_MAC_TRIG_SEL_8814B(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8814B)) +#define BIT_GET_R_MAC_TRIG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8814B) & \ + BIT_MASK_R_MAC_TRIG_SEL_8814B) +#define BIT_SET_R_MAC_TRIG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL_8814B(x) | BIT_R_MAC_TRIG_SEL_8814B(v)) #define BIT_MAC_TRIG_REG_8814B BIT(5) #define BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B 3 #define BIT_MASK_R_LEVEL_PULSE_SEL_8814B 0x3 -#define BIT_R_LEVEL_PULSE_SEL_8814B(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8814B) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) -#define BIT_GET_R_LEVEL_PULSE_SEL_8814B(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) & BIT_MASK_R_LEVEL_PULSE_SEL_8814B) - +#define BIT_R_LEVEL_PULSE_SEL_8814B(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8814B) \ + << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) +#define BITS_R_LEVEL_PULSE_SEL_8814B \ + (BIT_MASK_R_LEVEL_PULSE_SEL_8814B << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8814B(x) \ + ((x) & (~BITS_R_LEVEL_PULSE_SEL_8814B)) +#define BIT_GET_R_LEVEL_PULSE_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) & \ + BIT_MASK_R_LEVEL_PULSE_SEL_8814B) +#define BIT_SET_R_LEVEL_PULSE_SEL_8814B(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL_8814B(x) | BIT_R_LEVEL_PULSE_SEL_8814B(v)) #define BIT_EN_LA_MAC_8814B BIT(2) #define BIT_R_EN_IQDUMP_8814B BIT(1) @@ -11079,19 +25337,39 @@ #define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B 0 #define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC_1_8814B(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) -#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B) - - +#define BIT_R_WMAC_MASK_LA_MAC_1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) +#define BITS_R_WMAC_MASK_LA_MAC_1_8814B \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8814B(x) \ + ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8814B)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B) +#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8814B(x) | \ + BIT_R_WMAC_MASK_LA_MAC_1_8814B(v)) /* 2 REG_IQ_DUMP_2_8814B */ #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B 0 #define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC_2_8814B(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) -#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B) - - +#define BIT_R_WMAC_MATCH_REF_MAC_2_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) +#define BITS_R_WMAC_MATCH_REF_MAC_2_8814B \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8814B(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8814B)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8814B(x) | \ + BIT_R_WMAC_MATCH_REF_MAC_2_8814B(v)) /* 2 REG_WMAC_FTM_CTL_8814B */ #define BIT_RXFTM_TXACK_SC_8814B BIT(6) @@ -11107,25 +25385,46 @@ #define BIT_SHIFT_R_OFDM_LEN_8814B 26 #define BIT_MASK_R_OFDM_LEN_8814B 0x3f -#define BIT_R_OFDM_LEN_8814B(x) (((x) & BIT_MASK_R_OFDM_LEN_8814B) << BIT_SHIFT_R_OFDM_LEN_8814B) -#define BIT_GET_R_OFDM_LEN_8814B(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8814B) & BIT_MASK_R_OFDM_LEN_8814B) - - +#define BIT_R_OFDM_LEN_8814B(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_8814B) << BIT_SHIFT_R_OFDM_LEN_8814B) +#define BITS_R_OFDM_LEN_8814B \ + (BIT_MASK_R_OFDM_LEN_8814B << BIT_SHIFT_R_OFDM_LEN_8814B) +#define BIT_CLEAR_R_OFDM_LEN_8814B(x) ((x) & (~BITS_R_OFDM_LEN_8814B)) +#define BIT_GET_R_OFDM_LEN_8814B(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_8814B) & BIT_MASK_R_OFDM_LEN_8814B) +#define BIT_SET_R_OFDM_LEN_8814B(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_8814B(x) | BIT_R_OFDM_LEN_8814B(v)) #define BIT_SHIFT_R_CCK_LEN_8814B 0 #define BIT_MASK_R_CCK_LEN_8814B 0xffff -#define BIT_R_CCK_LEN_8814B(x) (((x) & BIT_MASK_R_CCK_LEN_8814B) << BIT_SHIFT_R_CCK_LEN_8814B) -#define BIT_GET_R_CCK_LEN_8814B(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8814B) & BIT_MASK_R_CCK_LEN_8814B) - - +#define BIT_R_CCK_LEN_8814B(x) \ + (((x) & BIT_MASK_R_CCK_LEN_8814B) << BIT_SHIFT_R_CCK_LEN_8814B) +#define BITS_R_CCK_LEN_8814B \ + (BIT_MASK_R_CCK_LEN_8814B << BIT_SHIFT_R_CCK_LEN_8814B) +#define BIT_CLEAR_R_CCK_LEN_8814B(x) ((x) & (~BITS_R_CCK_LEN_8814B)) +#define BIT_GET_R_CCK_LEN_8814B(x) \ + (((x) >> BIT_SHIFT_R_CCK_LEN_8814B) & BIT_MASK_R_CCK_LEN_8814B) +#define BIT_SET_R_CCK_LEN_8814B(x, v) \ + (BIT_CLEAR_R_CCK_LEN_8814B(x) | BIT_R_CCK_LEN_8814B(v)) /* 2 REG_WMAC_OPTION_FUNCTION_1_8814B */ #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B 24 #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B) - +#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) +#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8814B \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8814B)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) | \ + BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(v)) #define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8814B BIT(23) #define BIT_R_WMAC_RXRST_DLY_1_8814B BIT(22) @@ -11156,10 +25455,20 @@ #define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B 0 #define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B 0xffff -#define BIT_R_WMAC_RX_FIL_LEN_2_8814B(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) -#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B) - - +#define BIT_R_WMAC_RX_FIL_LEN_2_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B) \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) +#define BITS_R_WMAC_RX_FIL_LEN_2_8814B \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8814B(x) \ + ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8814B)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) & \ + BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B) +#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8814B(x) | \ + BIT_R_WMAC_RX_FIL_LEN_2_8814B(v)) /* 2 REG_RX_FILTER_FUNCTION_8814B */ #define BIT_R_WMAC_MHRDDY_LATCH_8814B BIT(14) @@ -11184,35 +25493,60 @@ #define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B 0 #define BIT_MASK_R_WMAC_TXNDP_SIGB_8814B 0x1fffff -#define BIT_R_WMAC_TXNDP_SIGB_8814B(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8814B) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) -#define BIT_GET_R_WMAC_TXNDP_SIGB_8814B(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) & BIT_MASK_R_WMAC_TXNDP_SIGB_8814B) - - +#define BIT_R_WMAC_TXNDP_SIGB_8814B(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8814B) \ + << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) +#define BITS_R_WMAC_TXNDP_SIGB_8814B \ + (BIT_MASK_R_WMAC_TXNDP_SIGB_8814B << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8814B(x) \ + ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8814B)) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8814B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) & \ + BIT_MASK_R_WMAC_TXNDP_SIGB_8814B) +#define BIT_SET_R_WMAC_TXNDP_SIGB_8814B(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8814B(x) | BIT_R_WMAC_TXNDP_SIGB_8814B(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8814B */ #define BIT_SHIFT_R_MAC_DBG_SHIFT_8814B 8 #define BIT_MASK_R_MAC_DBG_SHIFT_8814B 0x7 -#define BIT_R_MAC_DBG_SHIFT_8814B(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8814B) << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) -#define BIT_GET_R_MAC_DBG_SHIFT_8814B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) & BIT_MASK_R_MAC_DBG_SHIFT_8814B) - - +#define BIT_R_MAC_DBG_SHIFT_8814B(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8814B) \ + << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) +#define BITS_R_MAC_DBG_SHIFT_8814B \ + (BIT_MASK_R_MAC_DBG_SHIFT_8814B << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) +#define BIT_CLEAR_R_MAC_DBG_SHIFT_8814B(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8814B)) +#define BIT_GET_R_MAC_DBG_SHIFT_8814B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) & \ + BIT_MASK_R_MAC_DBG_SHIFT_8814B) +#define BIT_SET_R_MAC_DBG_SHIFT_8814B(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT_8814B(x) | BIT_R_MAC_DBG_SHIFT_8814B(v)) #define BIT_SHIFT_R_MAC_DBG_SEL_8814B 0 #define BIT_MASK_R_MAC_DBG_SEL_8814B 0x3 -#define BIT_R_MAC_DBG_SEL_8814B(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8814B) << BIT_SHIFT_R_MAC_DBG_SEL_8814B) -#define BIT_GET_R_MAC_DBG_SEL_8814B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8814B) & BIT_MASK_R_MAC_DBG_SEL_8814B) - - +#define BIT_R_MAC_DBG_SEL_8814B(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL_8814B) << BIT_SHIFT_R_MAC_DBG_SEL_8814B) +#define BITS_R_MAC_DBG_SEL_8814B \ + (BIT_MASK_R_MAC_DBG_SEL_8814B << BIT_SHIFT_R_MAC_DBG_SEL_8814B) +#define BIT_CLEAR_R_MAC_DBG_SEL_8814B(x) ((x) & (~BITS_R_MAC_DBG_SEL_8814B)) +#define BIT_GET_R_MAC_DBG_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8814B) & BIT_MASK_R_MAC_DBG_SEL_8814B) +#define BIT_SET_R_MAC_DBG_SEL_8814B(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL_8814B(x) | BIT_R_MAC_DBG_SEL_8814B(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8814B */ #define BIT_SHIFT_R_MAC_DEBUG_1_8814B 0 #define BIT_MASK_R_MAC_DEBUG_1_8814B 0xffffffffL -#define BIT_R_MAC_DEBUG_1_8814B(x) (((x) & BIT_MASK_R_MAC_DEBUG_1_8814B) << BIT_SHIFT_R_MAC_DEBUG_1_8814B) -#define BIT_GET_R_MAC_DEBUG_1_8814B(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8814B) & BIT_MASK_R_MAC_DEBUG_1_8814B) - - +#define BIT_R_MAC_DEBUG_1_8814B(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_1_8814B) << BIT_SHIFT_R_MAC_DEBUG_1_8814B) +#define BITS_R_MAC_DEBUG_1_8814B \ + (BIT_MASK_R_MAC_DEBUG_1_8814B << BIT_SHIFT_R_MAC_DEBUG_1_8814B) +#define BIT_CLEAR_R_MAC_DEBUG_1_8814B(x) ((x) & (~BITS_R_MAC_DEBUG_1_8814B)) +#define BIT_GET_R_MAC_DEBUG_1_8814B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8814B) & BIT_MASK_R_MAC_DEBUG_1_8814B) +#define BIT_SET_R_MAC_DEBUG_1_8814B(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_1_8814B(x) | BIT_R_MAC_DEBUG_1_8814B(v)) /* 2 REG_WSEC_OPTION_8814B */ #define BIT_RXDEC_BM_MGNT_8814B BIT(22) @@ -11235,35 +25569,69 @@ #define BIT_SHIFT_WRITE_BYTE_EN_V1_8814B 16 #define BIT_MASK_WRITE_BYTE_EN_V1_8814B 0xf -#define BIT_WRITE_BYTE_EN_V1_8814B(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8814B) << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) -#define BIT_GET_WRITE_BYTE_EN_V1_8814B(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) & BIT_MASK_WRITE_BYTE_EN_V1_8814B) - - +#define BIT_WRITE_BYTE_EN_V1_8814B(x) \ + (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8814B) \ + << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) +#define BITS_WRITE_BYTE_EN_V1_8814B \ + (BIT_MASK_WRITE_BYTE_EN_V1_8814B << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) +#define BIT_CLEAR_WRITE_BYTE_EN_V1_8814B(x) \ + ((x) & (~BITS_WRITE_BYTE_EN_V1_8814B)) +#define BIT_GET_WRITE_BYTE_EN_V1_8814B(x) \ + (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) & \ + BIT_MASK_WRITE_BYTE_EN_V1_8814B) +#define BIT_SET_WRITE_BYTE_EN_V1_8814B(x, v) \ + (BIT_CLEAR_WRITE_BYTE_EN_V1_8814B(x) | BIT_WRITE_BYTE_EN_V1_8814B(v)) #define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B 0 #define BIT_MASK_LTECOEX_REG_ADDR_V1_8814B 0xffff -#define BIT_LTECOEX_REG_ADDR_V1_8814B(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8814B) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) -#define BIT_GET_LTECOEX_REG_ADDR_V1_8814B(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) & BIT_MASK_LTECOEX_REG_ADDR_V1_8814B) - - +#define BIT_LTECOEX_REG_ADDR_V1_8814B(x) \ + (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8814B) \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) +#define BITS_LTECOEX_REG_ADDR_V1_8814B \ + (BIT_MASK_LTECOEX_REG_ADDR_V1_8814B \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) +#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8814B(x) \ + ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8814B)) +#define BIT_GET_LTECOEX_REG_ADDR_V1_8814B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) & \ + BIT_MASK_LTECOEX_REG_ADDR_V1_8814B) +#define BIT_SET_LTECOEX_REG_ADDR_V1_8814B(x, v) \ + (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8814B(x) | \ + BIT_LTECOEX_REG_ADDR_V1_8814B(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B */ #define BIT_SHIFT_LTECOEX_W_DATA_V1_8814B 0 #define BIT_MASK_LTECOEX_W_DATA_V1_8814B 0xffffffffL -#define BIT_LTECOEX_W_DATA_V1_8814B(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8814B) << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) -#define BIT_GET_LTECOEX_W_DATA_V1_8814B(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) & BIT_MASK_LTECOEX_W_DATA_V1_8814B) - - +#define BIT_LTECOEX_W_DATA_V1_8814B(x) \ + (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8814B) \ + << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) +#define BITS_LTECOEX_W_DATA_V1_8814B \ + (BIT_MASK_LTECOEX_W_DATA_V1_8814B << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) +#define BIT_CLEAR_LTECOEX_W_DATA_V1_8814B(x) \ + ((x) & (~BITS_LTECOEX_W_DATA_V1_8814B)) +#define BIT_GET_LTECOEX_W_DATA_V1_8814B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) & \ + BIT_MASK_LTECOEX_W_DATA_V1_8814B) +#define BIT_SET_LTECOEX_W_DATA_V1_8814B(x, v) \ + (BIT_CLEAR_LTECOEX_W_DATA_V1_8814B(x) | BIT_LTECOEX_W_DATA_V1_8814B(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B */ #define BIT_SHIFT_LTECOEX_R_DATA_V1_8814B 0 #define BIT_MASK_LTECOEX_R_DATA_V1_8814B 0xffffffffL -#define BIT_LTECOEX_R_DATA_V1_8814B(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8814B) << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) -#define BIT_GET_LTECOEX_R_DATA_V1_8814B(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) & BIT_MASK_LTECOEX_R_DATA_V1_8814B) - - +#define BIT_LTECOEX_R_DATA_V1_8814B(x) \ + (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8814B) \ + << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) +#define BITS_LTECOEX_R_DATA_V1_8814B \ + (BIT_MASK_LTECOEX_R_DATA_V1_8814B << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) +#define BIT_CLEAR_LTECOEX_R_DATA_V1_8814B(x) \ + ((x) & (~BITS_LTECOEX_R_DATA_V1_8814B)) +#define BIT_GET_LTECOEX_R_DATA_V1_8814B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) & \ + BIT_MASK_LTECOEX_R_DATA_V1_8814B) +#define BIT_SET_LTECOEX_R_DATA_V1_8814B(x, v) \ + (BIT_CLEAR_LTECOEX_R_DATA_V1_8814B(x) | BIT_LTECOEX_R_DATA_V1_8814B(v)) /* 2 REG_NOT_VALID_8814B */ @@ -11387,20 +25755,311 @@ /* 2 REG_NOT_VALID_8814B */ +/* 2 REG_PCIE_CFG_FORCE_LINK_L_8814B */ +#define BIT_PCIE_CFG_FORCE_EN_8814B BIT(7) + +/* 2 REG_PCIE_CFG_FORCE_LINK_H_8814B */ +#define BIT_PCIE_CFG_TRXACT_DIS_IDLE_TIMER_8814B BIT(6) + +#define BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B 0 +#define BIT_MASK_PCIE_CFG_LINK_STATE_8814B 0x3f +#define BIT_PCIE_CFG_LINK_STATE_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_LINK_STATE_8814B) \ + << BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B) +#define BITS_PCIE_CFG_LINK_STATE_8814B \ + (BIT_MASK_PCIE_CFG_LINK_STATE_8814B \ + << BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B) +#define BIT_CLEAR_PCIE_CFG_LINK_STATE_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_LINK_STATE_8814B)) +#define BIT_GET_PCIE_CFG_LINK_STATE_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B) & \ + BIT_MASK_PCIE_CFG_LINK_STATE_8814B) +#define BIT_SET_PCIE_CFG_LINK_STATE_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_LINK_STATE_8814B(x) | \ + BIT_PCIE_CFG_LINK_STATE_8814B(v)) + +/* 2 REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B */ + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0xff +#define BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) +#define BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B \ + (BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)) +#define BIT_GET_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) & \ + BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) +#define BIT_SET_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) | \ + BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(v)) + +/* 2 REG_PCIE_CFG_CX_NFTS_8814B */ + +#define BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B 0 +#define BIT_MASK_PCIE_CFG_CX_NFTS_8814B 0xff +#define BIT_PCIE_CFG_CX_NFTS_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_CX_NFTS_8814B) \ + << BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B) +#define BITS_PCIE_CFG_CX_NFTS_8814B \ + (BIT_MASK_PCIE_CFG_CX_NFTS_8814B << BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B) +#define BIT_CLEAR_PCIE_CFG_CX_NFTS_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_CX_NFTS_8814B)) +#define BIT_GET_PCIE_CFG_CX_NFTS_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B) & \ + BIT_MASK_PCIE_CFG_CX_NFTS_8814B) +#define BIT_SET_PCIE_CFG_CX_NFTS_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_CX_NFTS_8814B(x) | BIT_PCIE_CFG_CX_NFTS_8814B(v)) + +/* 2 REG_PCIE_CFG_DEFAULT_ENTR_LATENCY_8814B */ +#define BIT_PCIE_CFG_REAL_EN_L0S_8814B BIT(7) +#define BIT_PCIE_CFG_ENTER_ASPM_8814B BIT(6) + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B 3 +#define BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B 0x7 +#define BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) +#define BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B \ + (BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)) +#define BIT_GET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) & \ + BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) +#define BIT_SET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) | \ + BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(v)) + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B 0x7 +#define BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) +#define BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B \ + (BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)) +#define BIT_GET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) & \ + BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) +#define BIT_SET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) | \ + BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(v)) + +/* 2 REG_PCIE_CFG_L1_MISC_SEL_8814B */ +#define BIT_PCIE_CFG_L1_RIDLE_SEL_8814B BIT(6) +#define BIT_PCIE_CFG_L1_TIMEOUT_SEL_8814B BIT(5) +#define BIT_PCIE_CFG_L1_EIDLE_SEL_8814B BIT(4) + +#define BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B 0 +#define BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B 0xf +#define BIT_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B) \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B) +#define BITS_PCIE_CFG_DEFAULT_LINK_RATE_8814B \ + (BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B \ + << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B) +#define BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_DEFAULT_LINK_RATE_8814B)) +#define BIT_GET_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B) & \ + BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B) +#define BIT_SET_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) | \ + BIT_PCIE_CFG_DEFAULT_LINK_RATE_8814B(v)) + +/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF_8814B */ +#define BIT_PCIE_CFG_REAL_PTM_ENABLE_8814B BIT(6) +#define BIT_PCIE_CFG_REAL_EN_L1SUB_8814B BIT(5) + +#define BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B 0 +#define BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B 0x7 +#define BIT_PCIE_CFG_MAX_FUNC_NUM_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B) \ + << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B) +#define BITS_PCIE_CFG_MAX_FUNC_NUM_8814B \ + (BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B \ + << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B) +#define BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_MAX_FUNC_NUM_8814B)) +#define BIT_GET_PCIE_CFG_MAX_FUNC_NUM_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B) & \ + BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B) +#define BIT_SET_PCIE_CFG_MAX_FUNC_NUM_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM_8814B(x) | \ + BIT_PCIE_CFG_MAX_FUNC_NUM_8814B(v)) + +/* 2 REG_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B */ +#define BIT_PCIE_CFG_REAL_EN_64BITS_8814B BIT(5) +#define BIT_PCIE_CFG_REAL_EN_CLKREQ_8814B BIT(4) +#define BIT_PCIE_CFG_REAL_EN_L1_8814B BIT(3) +#define BIT_PCIE_CFG_WAKE_N_EN_8814B BIT(2) +#define BIT_PCIE_CFG_BYPASS_LTR_OPTION_8814B BIT(1) +#define BIT_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B BIT(0) + +/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY_8814B */ + +#define BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B 0 +#define BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B 0xff +#define BIT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) \ + << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) +#define BITS_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B \ + (BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B \ + << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) +#define BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)) +#define BIT_GET_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) & \ + BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) +#define BIT_SET_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) | \ + BIT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(v)) + +/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG_8814B */ +#define BIT_PCIE_CFG_BYPASS_L1_SUBSTATE_OPTION_8814B BIT(7) + +#define BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B 5 +#define BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B 0x3 +#define BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) \ + << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) +#define BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B \ + (BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B \ + << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) +#define BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)) +#define BIT_GET_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) & \ + BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) +#define BIT_SET_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) | \ + BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(v)) + +#define BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B 0 +#define BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B 0x1f +#define BIT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) \ + << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) +#define BITS_PCIE_CFG_UPDATE_FREQ_TIMER_8814B \ + (BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B \ + << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) +#define BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)) +#define BIT_GET_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) & \ + BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) +#define BIT_SET_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) | \ + BIT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(v)) + +/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B */ + +#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0 +#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0xff +#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) +#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B \ + (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) +#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)) +#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) & \ + BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) +#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) | \ + BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(v)) + +/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B */ +#define BIT_PCIE_CFG_DISABLE_FC_WATCHDOG_TIMER_8814B BIT(7) + +#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0 +#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0x7 +#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) +#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B \ + (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B \ + << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) +#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)) +#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) & \ + BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) +#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) | \ + BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(v)) + +/* 2 REG_PCIE_CFG_L1_UNIT_SEL_8814B */ + +#define BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B 0 +#define BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B 0xff +#define BIT_PCIE_CFG_L1_UNIT_SEL_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B) \ + << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B) +#define BITS_PCIE_CFG_L1_UNIT_SEL_8814B \ + (BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B \ + << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B) +#define BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_L1_UNIT_SEL_8814B)) +#define BIT_GET_PCIE_CFG_L1_UNIT_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B) & \ + BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B) +#define BIT_SET_PCIE_CFG_L1_UNIT_SEL_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL_8814B(x) | \ + BIT_PCIE_CFG_L1_UNIT_SEL_8814B(v)) + +/* 2 REG_PCIE_CFG_MIN_CLKREQ_SEL_8814B */ + +#define BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0 +#define BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0xf +#define BIT_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) \ + (((x) & BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B) \ + << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B) +#define BITS_PCIE_CFG_MIN_CLKREQ_SEL_8814B \ + (BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B \ + << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B) +#define BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) \ + ((x) & (~BITS_PCIE_CFG_MIN_CLKREQ_SEL_8814B)) +#define BIT_GET_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) \ + (((x) >> BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B) & \ + BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B) +#define BIT_SET_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x, v) \ + (BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) | \ + BIT_PCIE_CFG_MIN_CLKREQ_SEL_8814B(v)) + /* 2 REG_SDIO_TX_CTRL_8814B */ #define BIT_SHIFT_SDIO_INT_TIMEOUT_8814B 16 #define BIT_MASK_SDIO_INT_TIMEOUT_8814B 0xffff -#define BIT_SDIO_INT_TIMEOUT_8814B(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8814B) << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) -#define BIT_GET_SDIO_INT_TIMEOUT_8814B(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) & BIT_MASK_SDIO_INT_TIMEOUT_8814B) - +#define BIT_SDIO_INT_TIMEOUT_8814B(x) \ + (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8814B) \ + << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) +#define BITS_SDIO_INT_TIMEOUT_8814B \ + (BIT_MASK_SDIO_INT_TIMEOUT_8814B << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) +#define BIT_CLEAR_SDIO_INT_TIMEOUT_8814B(x) \ + ((x) & (~BITS_SDIO_INT_TIMEOUT_8814B)) +#define BIT_GET_SDIO_INT_TIMEOUT_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) & \ + BIT_MASK_SDIO_INT_TIMEOUT_8814B) +#define BIT_SET_SDIO_INT_TIMEOUT_8814B(x, v) \ + (BIT_CLEAR_SDIO_INT_TIMEOUT_8814B(x) | BIT_SDIO_INT_TIMEOUT_8814B(v)) #define BIT_IO_ERR_STATUS_8814B BIT(15) #define BIT_REPLY_ERRCRC_IN_DATA_8814B BIT(9) #define BIT_EN_CMD53_OVERLAP_8814B BIT(8) #define BIT_REPLY_ERR_IN_R5_8814B BIT(7) #define BIT_R18A_EN_8814B BIT(6) -#define BIT_INIT_CMD_EN_8814B BIT(5) +#define BIT_SDIO_CMD_FORCE_VLD_8814B BIT(5) +#define BIT_INIT_CMD_EN_8814B BIT(4) #define BIT_EN_RXDMA_MASK_INT_8814B BIT(2) #define BIT_EN_MASK_TIMER_8814B BIT(1) #define BIT_CMD_ERR_STOP_INT_EN_8814B BIT(0) @@ -11461,95 +26120,155 @@ #define BIT_SHIFT_RX_REQ_LEN_V1_8814B 0 #define BIT_MASK_RX_REQ_LEN_V1_8814B 0x3ffff -#define BIT_RX_REQ_LEN_V1_8814B(x) (((x) & BIT_MASK_RX_REQ_LEN_V1_8814B) << BIT_SHIFT_RX_REQ_LEN_V1_8814B) -#define BIT_GET_RX_REQ_LEN_V1_8814B(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8814B) & BIT_MASK_RX_REQ_LEN_V1_8814B) - - +#define BIT_RX_REQ_LEN_V1_8814B(x) \ + (((x) & BIT_MASK_RX_REQ_LEN_V1_8814B) << BIT_SHIFT_RX_REQ_LEN_V1_8814B) +#define BITS_RX_REQ_LEN_V1_8814B \ + (BIT_MASK_RX_REQ_LEN_V1_8814B << BIT_SHIFT_RX_REQ_LEN_V1_8814B) +#define BIT_CLEAR_RX_REQ_LEN_V1_8814B(x) ((x) & (~BITS_RX_REQ_LEN_V1_8814B)) +#define BIT_GET_RX_REQ_LEN_V1_8814B(x) \ + (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8814B) & BIT_MASK_RX_REQ_LEN_V1_8814B) +#define BIT_SET_RX_REQ_LEN_V1_8814B(x, v) \ + (BIT_CLEAR_RX_REQ_LEN_V1_8814B(x) | BIT_RX_REQ_LEN_V1_8814B(v)) /* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8814B */ #define BIT_SHIFT_FREE_TXPG_SEQ_8814B 0 #define BIT_MASK_FREE_TXPG_SEQ_8814B 0xff -#define BIT_FREE_TXPG_SEQ_8814B(x) (((x) & BIT_MASK_FREE_TXPG_SEQ_8814B) << BIT_SHIFT_FREE_TXPG_SEQ_8814B) -#define BIT_GET_FREE_TXPG_SEQ_8814B(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8814B) & BIT_MASK_FREE_TXPG_SEQ_8814B) - - +#define BIT_FREE_TXPG_SEQ_8814B(x) \ + (((x) & BIT_MASK_FREE_TXPG_SEQ_8814B) << BIT_SHIFT_FREE_TXPG_SEQ_8814B) +#define BITS_FREE_TXPG_SEQ_8814B \ + (BIT_MASK_FREE_TXPG_SEQ_8814B << BIT_SHIFT_FREE_TXPG_SEQ_8814B) +#define BIT_CLEAR_FREE_TXPG_SEQ_8814B(x) ((x) & (~BITS_FREE_TXPG_SEQ_8814B)) +#define BIT_GET_FREE_TXPG_SEQ_8814B(x) \ + (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8814B) & BIT_MASK_FREE_TXPG_SEQ_8814B) +#define BIT_SET_FREE_TXPG_SEQ_8814B(x, v) \ + (BIT_CLEAR_FREE_TXPG_SEQ_8814B(x) | BIT_FREE_TXPG_SEQ_8814B(v)) /* 2 REG_SDIO_FREE_TXPG_8814B */ #define BIT_SHIFT_MID_FREEPG_V1_8814B 16 #define BIT_MASK_MID_FREEPG_V1_8814B 0xfff -#define BIT_MID_FREEPG_V1_8814B(x) (((x) & BIT_MASK_MID_FREEPG_V1_8814B) << BIT_SHIFT_MID_FREEPG_V1_8814B) -#define BIT_GET_MID_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8814B) & BIT_MASK_MID_FREEPG_V1_8814B) - - +#define BIT_MID_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_MID_FREEPG_V1_8814B) << BIT_SHIFT_MID_FREEPG_V1_8814B) +#define BITS_MID_FREEPG_V1_8814B \ + (BIT_MASK_MID_FREEPG_V1_8814B << BIT_SHIFT_MID_FREEPG_V1_8814B) +#define BIT_CLEAR_MID_FREEPG_V1_8814B(x) ((x) & (~BITS_MID_FREEPG_V1_8814B)) +#define BIT_GET_MID_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_MID_FREEPG_V1_8814B) & BIT_MASK_MID_FREEPG_V1_8814B) +#define BIT_SET_MID_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_MID_FREEPG_V1_8814B(x) | BIT_MID_FREEPG_V1_8814B(v)) #define BIT_SHIFT_HIQ_FREEPG_V1_8814B 0 #define BIT_MASK_HIQ_FREEPG_V1_8814B 0xfff -#define BIT_HIQ_FREEPG_V1_8814B(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8814B) << BIT_SHIFT_HIQ_FREEPG_V1_8814B) -#define BIT_GET_HIQ_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8814B) & BIT_MASK_HIQ_FREEPG_V1_8814B) - - +#define BIT_HIQ_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_HIQ_FREEPG_V1_8814B) << BIT_SHIFT_HIQ_FREEPG_V1_8814B) +#define BITS_HIQ_FREEPG_V1_8814B \ + (BIT_MASK_HIQ_FREEPG_V1_8814B << BIT_SHIFT_HIQ_FREEPG_V1_8814B) +#define BIT_CLEAR_HIQ_FREEPG_V1_8814B(x) ((x) & (~BITS_HIQ_FREEPG_V1_8814B)) +#define BIT_GET_HIQ_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8814B) & BIT_MASK_HIQ_FREEPG_V1_8814B) +#define BIT_SET_HIQ_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_HIQ_FREEPG_V1_8814B(x) | BIT_HIQ_FREEPG_V1_8814B(v)) /* 2 REG_SDIO_FREE_TXPG2_8814B */ #define BIT_SHIFT_PUB_FREEPG_V1_8814B 16 #define BIT_MASK_PUB_FREEPG_V1_8814B 0xfff -#define BIT_PUB_FREEPG_V1_8814B(x) (((x) & BIT_MASK_PUB_FREEPG_V1_8814B) << BIT_SHIFT_PUB_FREEPG_V1_8814B) -#define BIT_GET_PUB_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8814B) & BIT_MASK_PUB_FREEPG_V1_8814B) - - +#define BIT_PUB_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_PUB_FREEPG_V1_8814B) << BIT_SHIFT_PUB_FREEPG_V1_8814B) +#define BITS_PUB_FREEPG_V1_8814B \ + (BIT_MASK_PUB_FREEPG_V1_8814B << BIT_SHIFT_PUB_FREEPG_V1_8814B) +#define BIT_CLEAR_PUB_FREEPG_V1_8814B(x) ((x) & (~BITS_PUB_FREEPG_V1_8814B)) +#define BIT_GET_PUB_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8814B) & BIT_MASK_PUB_FREEPG_V1_8814B) +#define BIT_SET_PUB_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_PUB_FREEPG_V1_8814B(x) | BIT_PUB_FREEPG_V1_8814B(v)) #define BIT_SHIFT_LOW_FREEPG_V1_8814B 0 #define BIT_MASK_LOW_FREEPG_V1_8814B 0xfff -#define BIT_LOW_FREEPG_V1_8814B(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8814B) << BIT_SHIFT_LOW_FREEPG_V1_8814B) -#define BIT_GET_LOW_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8814B) & BIT_MASK_LOW_FREEPG_V1_8814B) - - +#define BIT_LOW_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_LOW_FREEPG_V1_8814B) << BIT_SHIFT_LOW_FREEPG_V1_8814B) +#define BITS_LOW_FREEPG_V1_8814B \ + (BIT_MASK_LOW_FREEPG_V1_8814B << BIT_SHIFT_LOW_FREEPG_V1_8814B) +#define BIT_CLEAR_LOW_FREEPG_V1_8814B(x) ((x) & (~BITS_LOW_FREEPG_V1_8814B)) +#define BIT_GET_LOW_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8814B) & BIT_MASK_LOW_FREEPG_V1_8814B) +#define BIT_SET_LOW_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_LOW_FREEPG_V1_8814B(x) | BIT_LOW_FREEPG_V1_8814B(v)) /* 2 REG_SDIO_OQT_FREE_TXPG_V1_8814B */ #define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B 24 #define BIT_MASK_NOAC_OQT_FREEPG_V1_8814B 0xff -#define BIT_NOAC_OQT_FREEPG_V1_8814B(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8814B) << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) -#define BIT_GET_NOAC_OQT_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) & BIT_MASK_NOAC_OQT_FREEPG_V1_8814B) - - +#define BIT_NOAC_OQT_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8814B) \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) +#define BITS_NOAC_OQT_FREEPG_V1_8814B \ + (BIT_MASK_NOAC_OQT_FREEPG_V1_8814B \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) +#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8814B(x) \ + ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8814B)) +#define BIT_GET_NOAC_OQT_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) & \ + BIT_MASK_NOAC_OQT_FREEPG_V1_8814B) +#define BIT_SET_NOAC_OQT_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8814B(x) | \ + BIT_NOAC_OQT_FREEPG_V1_8814B(v)) #define BIT_SHIFT_AC_OQT_FREEPG_V1_8814B 16 #define BIT_MASK_AC_OQT_FREEPG_V1_8814B 0xff -#define BIT_AC_OQT_FREEPG_V1_8814B(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8814B) << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) -#define BIT_GET_AC_OQT_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) & BIT_MASK_AC_OQT_FREEPG_V1_8814B) - - +#define BIT_AC_OQT_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8814B) \ + << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) +#define BITS_AC_OQT_FREEPG_V1_8814B \ + (BIT_MASK_AC_OQT_FREEPG_V1_8814B << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) +#define BIT_CLEAR_AC_OQT_FREEPG_V1_8814B(x) \ + ((x) & (~BITS_AC_OQT_FREEPG_V1_8814B)) +#define BIT_GET_AC_OQT_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) & \ + BIT_MASK_AC_OQT_FREEPG_V1_8814B) +#define BIT_SET_AC_OQT_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_AC_OQT_FREEPG_V1_8814B(x) | BIT_AC_OQT_FREEPG_V1_8814B(v)) #define BIT_SHIFT_EXQ_FREEPG_V1_8814B 0 #define BIT_MASK_EXQ_FREEPG_V1_8814B 0xfff -#define BIT_EXQ_FREEPG_V1_8814B(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8814B) << BIT_SHIFT_EXQ_FREEPG_V1_8814B) -#define BIT_GET_EXQ_FREEPG_V1_8814B(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8814B) & BIT_MASK_EXQ_FREEPG_V1_8814B) - - +#define BIT_EXQ_FREEPG_V1_8814B(x) \ + (((x) & BIT_MASK_EXQ_FREEPG_V1_8814B) << BIT_SHIFT_EXQ_FREEPG_V1_8814B) +#define BITS_EXQ_FREEPG_V1_8814B \ + (BIT_MASK_EXQ_FREEPG_V1_8814B << BIT_SHIFT_EXQ_FREEPG_V1_8814B) +#define BIT_CLEAR_EXQ_FREEPG_V1_8814B(x) ((x) & (~BITS_EXQ_FREEPG_V1_8814B)) +#define BIT_GET_EXQ_FREEPG_V1_8814B(x) \ + (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8814B) & BIT_MASK_EXQ_FREEPG_V1_8814B) +#define BIT_SET_EXQ_FREEPG_V1_8814B(x, v) \ + (BIT_CLEAR_EXQ_FREEPG_V1_8814B(x) | BIT_EXQ_FREEPG_V1_8814B(v)) /* 2 REG_SDIO_HTSFR_INFO_8814B */ #define BIT_SHIFT_HTSFR1_8814B 16 #define BIT_MASK_HTSFR1_8814B 0xffff -#define BIT_HTSFR1_8814B(x) (((x) & BIT_MASK_HTSFR1_8814B) << BIT_SHIFT_HTSFR1_8814B) -#define BIT_GET_HTSFR1_8814B(x) (((x) >> BIT_SHIFT_HTSFR1_8814B) & BIT_MASK_HTSFR1_8814B) - - +#define BIT_HTSFR1_8814B(x) \ + (((x) & BIT_MASK_HTSFR1_8814B) << BIT_SHIFT_HTSFR1_8814B) +#define BITS_HTSFR1_8814B (BIT_MASK_HTSFR1_8814B << BIT_SHIFT_HTSFR1_8814B) +#define BIT_CLEAR_HTSFR1_8814B(x) ((x) & (~BITS_HTSFR1_8814B)) +#define BIT_GET_HTSFR1_8814B(x) \ + (((x) >> BIT_SHIFT_HTSFR1_8814B) & BIT_MASK_HTSFR1_8814B) +#define BIT_SET_HTSFR1_8814B(x, v) \ + (BIT_CLEAR_HTSFR1_8814B(x) | BIT_HTSFR1_8814B(v)) #define BIT_SHIFT_HTSFR0_8814B 0 #define BIT_MASK_HTSFR0_8814B 0xffff -#define BIT_HTSFR0_8814B(x) (((x) & BIT_MASK_HTSFR0_8814B) << BIT_SHIFT_HTSFR0_8814B) -#define BIT_GET_HTSFR0_8814B(x) (((x) >> BIT_SHIFT_HTSFR0_8814B) & BIT_MASK_HTSFR0_8814B) - - +#define BIT_HTSFR0_8814B(x) \ + (((x) & BIT_MASK_HTSFR0_8814B) << BIT_SHIFT_HTSFR0_8814B) +#define BITS_HTSFR0_8814B (BIT_MASK_HTSFR0_8814B << BIT_SHIFT_HTSFR0_8814B) +#define BIT_CLEAR_HTSFR0_8814B(x) ((x) & (~BITS_HTSFR0_8814B)) +#define BIT_GET_HTSFR0_8814B(x) \ + (((x) >> BIT_SHIFT_HTSFR0_8814B) & BIT_MASK_HTSFR0_8814B) +#define BIT_SET_HTSFR0_8814B(x, v) \ + (BIT_CLEAR_HTSFR0_8814B(x) | BIT_HTSFR0_8814B(v)) /* 2 REG_SDIO_HCPWM1_V2_8814B */ -#define BIT_TOGGLING_8814B BIT(7) -#define BIT_ACK_8814B BIT(6) -#define BIT_SYS_CLK_8814B BIT(0) +#define BIT_TOGGLE_8814B BIT(7) +#define BIT_CUR_PS_8814B BIT(0) /* 2 REG_SDIO_HCPWM2_V2_8814B */ @@ -11560,49 +26279,83 @@ #define BIT_SHIFT_INDIRECT_REG_SIZE_8814B 16 #define BIT_MASK_INDIRECT_REG_SIZE_8814B 0x3 -#define BIT_INDIRECT_REG_SIZE_8814B(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE_8814B) << BIT_SHIFT_INDIRECT_REG_SIZE_8814B) -#define BIT_GET_INDIRECT_REG_SIZE_8814B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8814B) & BIT_MASK_INDIRECT_REG_SIZE_8814B) - - +#define BIT_INDIRECT_REG_SIZE_8814B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_SIZE_8814B) \ + << BIT_SHIFT_INDIRECT_REG_SIZE_8814B) +#define BITS_INDIRECT_REG_SIZE_8814B \ + (BIT_MASK_INDIRECT_REG_SIZE_8814B << BIT_SHIFT_INDIRECT_REG_SIZE_8814B) +#define BIT_CLEAR_INDIRECT_REG_SIZE_8814B(x) \ + ((x) & (~BITS_INDIRECT_REG_SIZE_8814B)) +#define BIT_GET_INDIRECT_REG_SIZE_8814B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8814B) & \ + BIT_MASK_INDIRECT_REG_SIZE_8814B) +#define BIT_SET_INDIRECT_REG_SIZE_8814B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_SIZE_8814B(x) | BIT_INDIRECT_REG_SIZE_8814B(v)) #define BIT_SHIFT_INDIRECT_REG_ADDR_8814B 0 #define BIT_MASK_INDIRECT_REG_ADDR_8814B 0xffff -#define BIT_INDIRECT_REG_ADDR_8814B(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8814B) << BIT_SHIFT_INDIRECT_REG_ADDR_8814B) -#define BIT_GET_INDIRECT_REG_ADDR_8814B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8814B) & BIT_MASK_INDIRECT_REG_ADDR_8814B) - - +#define BIT_INDIRECT_REG_ADDR_8814B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_ADDR_8814B) \ + << BIT_SHIFT_INDIRECT_REG_ADDR_8814B) +#define BITS_INDIRECT_REG_ADDR_8814B \ + (BIT_MASK_INDIRECT_REG_ADDR_8814B << BIT_SHIFT_INDIRECT_REG_ADDR_8814B) +#define BIT_CLEAR_INDIRECT_REG_ADDR_8814B(x) \ + ((x) & (~BITS_INDIRECT_REG_ADDR_8814B)) +#define BIT_GET_INDIRECT_REG_ADDR_8814B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8814B) & \ + BIT_MASK_INDIRECT_REG_ADDR_8814B) +#define BIT_SET_INDIRECT_REG_ADDR_8814B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_ADDR_8814B(x) | BIT_INDIRECT_REG_ADDR_8814B(v)) /* 2 REG_SDIO_INDIRECT_REG_DATA_8814B */ #define BIT_SHIFT_INDIRECT_REG_DATA_8814B 0 #define BIT_MASK_INDIRECT_REG_DATA_8814B 0xffffffffL -#define BIT_INDIRECT_REG_DATA_8814B(x) (((x) & BIT_MASK_INDIRECT_REG_DATA_8814B) << BIT_SHIFT_INDIRECT_REG_DATA_8814B) -#define BIT_GET_INDIRECT_REG_DATA_8814B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8814B) & BIT_MASK_INDIRECT_REG_DATA_8814B) - - +#define BIT_INDIRECT_REG_DATA_8814B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_DATA_8814B) \ + << BIT_SHIFT_INDIRECT_REG_DATA_8814B) +#define BITS_INDIRECT_REG_DATA_8814B \ + (BIT_MASK_INDIRECT_REG_DATA_8814B << BIT_SHIFT_INDIRECT_REG_DATA_8814B) +#define BIT_CLEAR_INDIRECT_REG_DATA_8814B(x) \ + ((x) & (~BITS_INDIRECT_REG_DATA_8814B)) +#define BIT_GET_INDIRECT_REG_DATA_8814B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8814B) & \ + BIT_MASK_INDIRECT_REG_DATA_8814B) +#define BIT_SET_INDIRECT_REG_DATA_8814B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_DATA_8814B(x) | BIT_INDIRECT_REG_DATA_8814B(v)) /* 2 REG_SDIO_H2C_8814B */ #define BIT_SHIFT_SDIO_H2C_MSG_8814B 0 #define BIT_MASK_SDIO_H2C_MSG_8814B 0xffffffffL -#define BIT_SDIO_H2C_MSG_8814B(x) (((x) & BIT_MASK_SDIO_H2C_MSG_8814B) << BIT_SHIFT_SDIO_H2C_MSG_8814B) -#define BIT_GET_SDIO_H2C_MSG_8814B(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8814B) & BIT_MASK_SDIO_H2C_MSG_8814B) - - +#define BIT_SDIO_H2C_MSG_8814B(x) \ + (((x) & BIT_MASK_SDIO_H2C_MSG_8814B) << BIT_SHIFT_SDIO_H2C_MSG_8814B) +#define BITS_SDIO_H2C_MSG_8814B \ + (BIT_MASK_SDIO_H2C_MSG_8814B << BIT_SHIFT_SDIO_H2C_MSG_8814B) +#define BIT_CLEAR_SDIO_H2C_MSG_8814B(x) ((x) & (~BITS_SDIO_H2C_MSG_8814B)) +#define BIT_GET_SDIO_H2C_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8814B) & BIT_MASK_SDIO_H2C_MSG_8814B) +#define BIT_SET_SDIO_H2C_MSG_8814B(x, v) \ + (BIT_CLEAR_SDIO_H2C_MSG_8814B(x) | BIT_SDIO_H2C_MSG_8814B(v)) /* 2 REG_SDIO_C2H_8814B */ #define BIT_SHIFT_SDIO_C2H_MSG_8814B 0 #define BIT_MASK_SDIO_C2H_MSG_8814B 0xffffffffL -#define BIT_SDIO_C2H_MSG_8814B(x) (((x) & BIT_MASK_SDIO_C2H_MSG_8814B) << BIT_SHIFT_SDIO_C2H_MSG_8814B) -#define BIT_GET_SDIO_C2H_MSG_8814B(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8814B) & BIT_MASK_SDIO_C2H_MSG_8814B) - - +#define BIT_SDIO_C2H_MSG_8814B(x) \ + (((x) & BIT_MASK_SDIO_C2H_MSG_8814B) << BIT_SHIFT_SDIO_C2H_MSG_8814B) +#define BITS_SDIO_C2H_MSG_8814B \ + (BIT_MASK_SDIO_C2H_MSG_8814B << BIT_SHIFT_SDIO_C2H_MSG_8814B) +#define BIT_CLEAR_SDIO_C2H_MSG_8814B(x) ((x) & (~BITS_SDIO_C2H_MSG_8814B)) +#define BIT_GET_SDIO_C2H_MSG_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8814B) & BIT_MASK_SDIO_C2H_MSG_8814B) +#define BIT_SET_SDIO_C2H_MSG_8814B(x, v) \ + (BIT_CLEAR_SDIO_C2H_MSG_8814B(x) | BIT_SDIO_C2H_MSG_8814B(v)) /* 2 REG_SDIO_HRPWM1_8814B */ -#define BIT_TOGGLING_8814B BIT(7) +#define BIT_TOGGLE_8814B BIT(7) #define BIT_ACK_8814B BIT(6) -#define BIT_32K_PERMISSION_8814B BIT(0) +#define BIT_REQ_PS_8814B BIT(0) /* 2 REG_SDIO_HRPWM2_8814B */ @@ -11625,27 +26378,39 @@ #define BIT_SHIFT_CMDIN_2RESP_TIMER_8814B 0 #define BIT_MASK_CMDIN_2RESP_TIMER_8814B 0xffff -#define BIT_CMDIN_2RESP_TIMER_8814B(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8814B) << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) -#define BIT_GET_CMDIN_2RESP_TIMER_8814B(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) & BIT_MASK_CMDIN_2RESP_TIMER_8814B) - - +#define BIT_CMDIN_2RESP_TIMER_8814B(x) \ + (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8814B) \ + << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) +#define BITS_CMDIN_2RESP_TIMER_8814B \ + (BIT_MASK_CMDIN_2RESP_TIMER_8814B << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) +#define BIT_CLEAR_CMDIN_2RESP_TIMER_8814B(x) \ + ((x) & (~BITS_CMDIN_2RESP_TIMER_8814B)) +#define BIT_GET_CMDIN_2RESP_TIMER_8814B(x) \ + (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) & \ + BIT_MASK_CMDIN_2RESP_TIMER_8814B) +#define BIT_SET_CMDIN_2RESP_TIMER_8814B(x, v) \ + (BIT_CLEAR_CMDIN_2RESP_TIMER_8814B(x) | BIT_CMDIN_2RESP_TIMER_8814B(v)) /* 2 REG_SDIO_CMD_CRC_8814B */ #define BIT_SHIFT_SDIO_CMD_CRC_V1_8814B 0 #define BIT_MASK_SDIO_CMD_CRC_V1_8814B 0xff -#define BIT_SDIO_CMD_CRC_V1_8814B(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8814B) << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) -#define BIT_GET_SDIO_CMD_CRC_V1_8814B(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) & BIT_MASK_SDIO_CMD_CRC_V1_8814B) - - +#define BIT_SDIO_CMD_CRC_V1_8814B(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8814B) \ + << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) +#define BITS_SDIO_CMD_CRC_V1_8814B \ + (BIT_MASK_SDIO_CMD_CRC_V1_8814B << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) +#define BIT_CLEAR_SDIO_CMD_CRC_V1_8814B(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8814B)) +#define BIT_GET_SDIO_CMD_CRC_V1_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) & \ + BIT_MASK_SDIO_CMD_CRC_V1_8814B) +#define BIT_SET_SDIO_CMD_CRC_V1_8814B(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC_V1_8814B(x) | BIT_SDIO_CMD_CRC_V1_8814B(v)) /* 2 REG_SDIO_HSISR_8814B */ #define BIT_DRV_WLAN_INT_CLR_8814B BIT(1) #define BIT_DRV_WLAN_INT_8814B BIT(0) -/* 2 REG_SDIO_HSIMR_8814B */ -#define BIT_HISR_MASK_8814B BIT(0) - /* 2 REG_SDIO_ERR_RPT_8814B */ #define BIT_HR_FF_OVF_8814B BIT(6) #define BIT_HR_FF_UDN_8814B BIT(5) @@ -11659,28 +26424,53 @@ #define BIT_SHIFT_CMD_CRC_ERR_CNT_8814B 0 #define BIT_MASK_CMD_CRC_ERR_CNT_8814B 0xff -#define BIT_CMD_CRC_ERR_CNT_8814B(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8814B) << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) -#define BIT_GET_CMD_CRC_ERR_CNT_8814B(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) & BIT_MASK_CMD_CRC_ERR_CNT_8814B) - - +#define BIT_CMD_CRC_ERR_CNT_8814B(x) \ + (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8814B) \ + << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) +#define BITS_CMD_CRC_ERR_CNT_8814B \ + (BIT_MASK_CMD_CRC_ERR_CNT_8814B << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) +#define BIT_CLEAR_CMD_CRC_ERR_CNT_8814B(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8814B)) +#define BIT_GET_CMD_CRC_ERR_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) & \ + BIT_MASK_CMD_CRC_ERR_CNT_8814B) +#define BIT_SET_CMD_CRC_ERR_CNT_8814B(x, v) \ + (BIT_CLEAR_CMD_CRC_ERR_CNT_8814B(x) | BIT_CMD_CRC_ERR_CNT_8814B(v)) /* 2 REG_SDIO_DATA_ERRCNT_8814B */ #define BIT_SHIFT_DATA_CRC_ERR_CNT_8814B 0 #define BIT_MASK_DATA_CRC_ERR_CNT_8814B 0xff -#define BIT_DATA_CRC_ERR_CNT_8814B(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8814B) << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) -#define BIT_GET_DATA_CRC_ERR_CNT_8814B(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) & BIT_MASK_DATA_CRC_ERR_CNT_8814B) - - +#define BIT_DATA_CRC_ERR_CNT_8814B(x) \ + (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8814B) \ + << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) +#define BITS_DATA_CRC_ERR_CNT_8814B \ + (BIT_MASK_DATA_CRC_ERR_CNT_8814B << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) +#define BIT_CLEAR_DATA_CRC_ERR_CNT_8814B(x) \ + ((x) & (~BITS_DATA_CRC_ERR_CNT_8814B)) +#define BIT_GET_DATA_CRC_ERR_CNT_8814B(x) \ + (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) & \ + BIT_MASK_DATA_CRC_ERR_CNT_8814B) +#define BIT_SET_DATA_CRC_ERR_CNT_8814B(x, v) \ + (BIT_CLEAR_DATA_CRC_ERR_CNT_8814B(x) | BIT_DATA_CRC_ERR_CNT_8814B(v)) /* 2 REG_SDIO_CMD_ERR_CONTENT_8814B */ #define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B 0 #define BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B 0xffffffffffL -#define BIT_SDIO_CMD_ERR_CONTENT_8814B(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) -#define BIT_GET_SDIO_CMD_ERR_CONTENT_8814B(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B) - - +#define BIT_SDIO_CMD_ERR_CONTENT_8814B(x) \ + (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B) \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) +#define BITS_SDIO_CMD_ERR_CONTENT_8814B \ + (BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) +#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8814B(x) \ + ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8814B)) +#define BIT_GET_SDIO_CMD_ERR_CONTENT_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) & \ + BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B) +#define BIT_SET_SDIO_CMD_ERR_CONTENT_8814B(x, v) \ + (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8814B(x) | \ + BIT_SDIO_CMD_ERR_CONTENT_8814B(v)) /* 2 REG_SDIO_CRC_ERR_IDX_8814B */ #define BIT_D3_CRC_ERR_8814B BIT(4) @@ -11692,19 +26482,34 @@ /* 2 REG_SDIO_DATA_CRC_8814B */ #define BIT_SHIFT_SDIO_DATA_CRC_8814B 0 -#define BIT_MASK_SDIO_DATA_CRC_8814B 0xff -#define BIT_SDIO_DATA_CRC_8814B(x) (((x) & BIT_MASK_SDIO_DATA_CRC_8814B) << BIT_SHIFT_SDIO_DATA_CRC_8814B) -#define BIT_GET_SDIO_DATA_CRC_8814B(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8814B) & BIT_MASK_SDIO_DATA_CRC_8814B) - - +#define BIT_MASK_SDIO_DATA_CRC_8814B 0xffff +#define BIT_SDIO_DATA_CRC_8814B(x) \ + (((x) & BIT_MASK_SDIO_DATA_CRC_8814B) << BIT_SHIFT_SDIO_DATA_CRC_8814B) +#define BITS_SDIO_DATA_CRC_8814B \ + (BIT_MASK_SDIO_DATA_CRC_8814B << BIT_SHIFT_SDIO_DATA_CRC_8814B) +#define BIT_CLEAR_SDIO_DATA_CRC_8814B(x) ((x) & (~BITS_SDIO_DATA_CRC_8814B)) +#define BIT_GET_SDIO_DATA_CRC_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8814B) & BIT_MASK_SDIO_DATA_CRC_8814B) +#define BIT_SET_SDIO_DATA_CRC_8814B(x, v) \ + (BIT_CLEAR_SDIO_DATA_CRC_8814B(x) | BIT_SDIO_DATA_CRC_8814B(v)) /* 2 REG_SDIO_DATA_REPLY_TIME_8814B */ #define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B 0 #define BIT_MASK_SDIO_DATA_REPLY_TIME_8814B 0x7 -#define BIT_SDIO_DATA_REPLY_TIME_8814B(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8814B) << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) -#define BIT_GET_SDIO_DATA_REPLY_TIME_8814B(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) & BIT_MASK_SDIO_DATA_REPLY_TIME_8814B) - - +#define BIT_SDIO_DATA_REPLY_TIME_8814B(x) \ + (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8814B) \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) +#define BITS_SDIO_DATA_REPLY_TIME_8814B \ + (BIT_MASK_SDIO_DATA_REPLY_TIME_8814B \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) +#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8814B(x) \ + ((x) & (~BITS_SDIO_DATA_REPLY_TIME_8814B)) +#define BIT_GET_SDIO_DATA_REPLY_TIME_8814B(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) & \ + BIT_MASK_SDIO_DATA_REPLY_TIME_8814B) +#define BIT_SET_SDIO_DATA_REPLY_TIME_8814B(x, v) \ + (BIT_CLEAR_SDIO_DATA_REPLY_TIME_8814B(x) | \ + BIT_SDIO_DATA_REPLY_TIME_8814B(v)) #endif diff --git a/hal/halmac/halmac_bit_8821c.h b/hal/halmac/halmac_bit_8821c.h index 21a48dd..7538125 100644 --- a/hal/halmac/halmac_bit_8821c.h +++ b/hal/halmac/halmac_bit_8821c.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_BIT_8821C_H #define __INC_HALMAC_BIT_8821C_H @@ -91,16 +106,25 @@ #define BIT_SHIFT_VPDIDX_8821C 8 #define BIT_MASK_VPDIDX_8821C 0xff -#define BIT_VPDIDX_8821C(x) (((x) & BIT_MASK_VPDIDX_8821C) << BIT_SHIFT_VPDIDX_8821C) -#define BIT_GET_VPDIDX_8821C(x) (((x) >> BIT_SHIFT_VPDIDX_8821C) & BIT_MASK_VPDIDX_8821C) - - +#define BIT_VPDIDX_8821C(x) \ + (((x) & BIT_MASK_VPDIDX_8821C) << BIT_SHIFT_VPDIDX_8821C) +#define BITS_VPDIDX_8821C (BIT_MASK_VPDIDX_8821C << BIT_SHIFT_VPDIDX_8821C) +#define BIT_CLEAR_VPDIDX_8821C(x) ((x) & (~BITS_VPDIDX_8821C)) +#define BIT_GET_VPDIDX_8821C(x) \ + (((x) >> BIT_SHIFT_VPDIDX_8821C) & BIT_MASK_VPDIDX_8821C) +#define BIT_SET_VPDIDX_8821C(x, v) \ + (BIT_CLEAR_VPDIDX_8821C(x) | BIT_VPDIDX_8821C(v)) #define BIT_SHIFT_EEM1_0_8821C 6 #define BIT_MASK_EEM1_0_8821C 0x3 -#define BIT_EEM1_0_8821C(x) (((x) & BIT_MASK_EEM1_0_8821C) << BIT_SHIFT_EEM1_0_8821C) -#define BIT_GET_EEM1_0_8821C(x) (((x) >> BIT_SHIFT_EEM1_0_8821C) & BIT_MASK_EEM1_0_8821C) - +#define BIT_EEM1_0_8821C(x) \ + (((x) & BIT_MASK_EEM1_0_8821C) << BIT_SHIFT_EEM1_0_8821C) +#define BITS_EEM1_0_8821C (BIT_MASK_EEM1_0_8821C << BIT_SHIFT_EEM1_0_8821C) +#define BIT_CLEAR_EEM1_0_8821C(x) ((x) & (~BITS_EEM1_0_8821C)) +#define BIT_GET_EEM1_0_8821C(x) \ + (((x) >> BIT_SHIFT_EEM1_0_8821C) & BIT_MASK_EEM1_0_8821C) +#define BIT_SET_EEM1_0_8821C(x, v) \ + (BIT_CLEAR_EEM1_0_8821C(x) | BIT_EEM1_0_8821C(v)) #define BIT_AUTOLOAD_SUS_8821C BIT(5) #define BIT_EERPOMSEL_8821C BIT(4) @@ -113,10 +137,15 @@ #define BIT_SHIFT_VPD_DATA_8821C 0 #define BIT_MASK_VPD_DATA_8821C 0xffffffffL -#define BIT_VPD_DATA_8821C(x) (((x) & BIT_MASK_VPD_DATA_8821C) << BIT_SHIFT_VPD_DATA_8821C) -#define BIT_GET_VPD_DATA_8821C(x) (((x) >> BIT_SHIFT_VPD_DATA_8821C) & BIT_MASK_VPD_DATA_8821C) - - +#define BIT_VPD_DATA_8821C(x) \ + (((x) & BIT_MASK_VPD_DATA_8821C) << BIT_SHIFT_VPD_DATA_8821C) +#define BITS_VPD_DATA_8821C \ + (BIT_MASK_VPD_DATA_8821C << BIT_SHIFT_VPD_DATA_8821C) +#define BIT_CLEAR_VPD_DATA_8821C(x) ((x) & (~BITS_VPD_DATA_8821C)) +#define BIT_GET_VPD_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_VPD_DATA_8821C) & BIT_MASK_VPD_DATA_8821C) +#define BIT_SET_VPD_DATA_8821C(x, v) \ + (BIT_CLEAR_VPD_DATA_8821C(x) | BIT_VPD_DATA_8821C(v)) /* 2 REG_SYS_SWR_CTRL1_8821C */ #define BIT_C2_L_BIT0_8821C BIT(31) @@ -124,23 +153,37 @@ #define BIT_SHIFT_C1_L_8821C 29 #define BIT_MASK_C1_L_8821C 0x3 #define BIT_C1_L_8821C(x) (((x) & BIT_MASK_C1_L_8821C) << BIT_SHIFT_C1_L_8821C) -#define BIT_GET_C1_L_8821C(x) (((x) >> BIT_SHIFT_C1_L_8821C) & BIT_MASK_C1_L_8821C) - - +#define BITS_C1_L_8821C (BIT_MASK_C1_L_8821C << BIT_SHIFT_C1_L_8821C) +#define BIT_CLEAR_C1_L_8821C(x) ((x) & (~BITS_C1_L_8821C)) +#define BIT_GET_C1_L_8821C(x) \ + (((x) >> BIT_SHIFT_C1_L_8821C) & BIT_MASK_C1_L_8821C) +#define BIT_SET_C1_L_8821C(x, v) (BIT_CLEAR_C1_L_8821C(x) | BIT_C1_L_8821C(v)) #define BIT_SHIFT_REG_FREQ_L_8821C 25 #define BIT_MASK_REG_FREQ_L_8821C 0x7 -#define BIT_REG_FREQ_L_8821C(x) (((x) & BIT_MASK_REG_FREQ_L_8821C) << BIT_SHIFT_REG_FREQ_L_8821C) -#define BIT_GET_REG_FREQ_L_8821C(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8821C) & BIT_MASK_REG_FREQ_L_8821C) - +#define BIT_REG_FREQ_L_8821C(x) \ + (((x) & BIT_MASK_REG_FREQ_L_8821C) << BIT_SHIFT_REG_FREQ_L_8821C) +#define BITS_REG_FREQ_L_8821C \ + (BIT_MASK_REG_FREQ_L_8821C << BIT_SHIFT_REG_FREQ_L_8821C) +#define BIT_CLEAR_REG_FREQ_L_8821C(x) ((x) & (~BITS_REG_FREQ_L_8821C)) +#define BIT_GET_REG_FREQ_L_8821C(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_8821C) & BIT_MASK_REG_FREQ_L_8821C) +#define BIT_SET_REG_FREQ_L_8821C(x, v) \ + (BIT_CLEAR_REG_FREQ_L_8821C(x) | BIT_REG_FREQ_L_8821C(v)) #define BIT_REG_EN_DUTY_8821C BIT(24) #define BIT_SHIFT_REG_MODE_8821C 22 #define BIT_MASK_REG_MODE_8821C 0x3 -#define BIT_REG_MODE_8821C(x) (((x) & BIT_MASK_REG_MODE_8821C) << BIT_SHIFT_REG_MODE_8821C) -#define BIT_GET_REG_MODE_8821C(x) (((x) >> BIT_SHIFT_REG_MODE_8821C) & BIT_MASK_REG_MODE_8821C) - +#define BIT_REG_MODE_8821C(x) \ + (((x) & BIT_MASK_REG_MODE_8821C) << BIT_SHIFT_REG_MODE_8821C) +#define BITS_REG_MODE_8821C \ + (BIT_MASK_REG_MODE_8821C << BIT_SHIFT_REG_MODE_8821C) +#define BIT_CLEAR_REG_MODE_8821C(x) ((x) & (~BITS_REG_MODE_8821C)) +#define BIT_GET_REG_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_REG_MODE_8821C) & BIT_MASK_REG_MODE_8821C) +#define BIT_SET_REG_MODE_8821C(x, v) \ + (BIT_CLEAR_REG_MODE_8821C(x) | BIT_REG_MODE_8821C(v)) #define BIT_REG_EN_SP_8821C BIT(21) #define BIT_REG_AUTO_L_8821C BIT(20) @@ -149,16 +192,23 @@ #define BIT_SHIFT_OCP_L1_8821C 15 #define BIT_MASK_OCP_L1_8821C 0x7 -#define BIT_OCP_L1_8821C(x) (((x) & BIT_MASK_OCP_L1_8821C) << BIT_SHIFT_OCP_L1_8821C) -#define BIT_GET_OCP_L1_8821C(x) (((x) >> BIT_SHIFT_OCP_L1_8821C) & BIT_MASK_OCP_L1_8821C) - - +#define BIT_OCP_L1_8821C(x) \ + (((x) & BIT_MASK_OCP_L1_8821C) << BIT_SHIFT_OCP_L1_8821C) +#define BITS_OCP_L1_8821C (BIT_MASK_OCP_L1_8821C << BIT_SHIFT_OCP_L1_8821C) +#define BIT_CLEAR_OCP_L1_8821C(x) ((x) & (~BITS_OCP_L1_8821C)) +#define BIT_GET_OCP_L1_8821C(x) \ + (((x) >> BIT_SHIFT_OCP_L1_8821C) & BIT_MASK_OCP_L1_8821C) +#define BIT_SET_OCP_L1_8821C(x, v) \ + (BIT_CLEAR_OCP_L1_8821C(x) | BIT_OCP_L1_8821C(v)) #define BIT_SHIFT_CF_L_8821C 13 #define BIT_MASK_CF_L_8821C 0x3 #define BIT_CF_L_8821C(x) (((x) & BIT_MASK_CF_L_8821C) << BIT_SHIFT_CF_L_8821C) -#define BIT_GET_CF_L_8821C(x) (((x) >> BIT_SHIFT_CF_L_8821C) & BIT_MASK_CF_L_8821C) - +#define BITS_CF_L_8821C (BIT_MASK_CF_L_8821C << BIT_SHIFT_CF_L_8821C) +#define BIT_CLEAR_CF_L_8821C(x) ((x) & (~BITS_CF_L_8821C)) +#define BIT_GET_CF_L_8821C(x) \ + (((x) >> BIT_SHIFT_CF_L_8821C) & BIT_MASK_CF_L_8821C) +#define BIT_SET_CF_L_8821C(x, v) (BIT_CLEAR_CF_L_8821C(x) | BIT_CF_L_8821C(v)) #define BIT_SW18_FPWM_8821C BIT(11) #define BIT_SW18_SWEN_8821C BIT(9) @@ -172,37 +222,62 @@ #define BIT_SHIFT_REG_DELAY_8821C 28 #define BIT_MASK_REG_DELAY_8821C 0x3 -#define BIT_REG_DELAY_8821C(x) (((x) & BIT_MASK_REG_DELAY_8821C) << BIT_SHIFT_REG_DELAY_8821C) -#define BIT_GET_REG_DELAY_8821C(x) (((x) >> BIT_SHIFT_REG_DELAY_8821C) & BIT_MASK_REG_DELAY_8821C) - - +#define BIT_REG_DELAY_8821C(x) \ + (((x) & BIT_MASK_REG_DELAY_8821C) << BIT_SHIFT_REG_DELAY_8821C) +#define BITS_REG_DELAY_8821C \ + (BIT_MASK_REG_DELAY_8821C << BIT_SHIFT_REG_DELAY_8821C) +#define BIT_CLEAR_REG_DELAY_8821C(x) ((x) & (~BITS_REG_DELAY_8821C)) +#define BIT_GET_REG_DELAY_8821C(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_8821C) & BIT_MASK_REG_DELAY_8821C) +#define BIT_SET_REG_DELAY_8821C(x, v) \ + (BIT_CLEAR_REG_DELAY_8821C(x) | BIT_REG_DELAY_8821C(v)) #define BIT_SHIFT_V15ADJ_L1_V1_8821C 24 #define BIT_MASK_V15ADJ_L1_V1_8821C 0x7 -#define BIT_V15ADJ_L1_V1_8821C(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8821C) << BIT_SHIFT_V15ADJ_L1_V1_8821C) -#define BIT_GET_V15ADJ_L1_V1_8821C(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8821C) & BIT_MASK_V15ADJ_L1_V1_8821C) - - +#define BIT_V15ADJ_L1_V1_8821C(x) \ + (((x) & BIT_MASK_V15ADJ_L1_V1_8821C) << BIT_SHIFT_V15ADJ_L1_V1_8821C) +#define BITS_V15ADJ_L1_V1_8821C \ + (BIT_MASK_V15ADJ_L1_V1_8821C << BIT_SHIFT_V15ADJ_L1_V1_8821C) +#define BIT_CLEAR_V15ADJ_L1_V1_8821C(x) ((x) & (~BITS_V15ADJ_L1_V1_8821C)) +#define BIT_GET_V15ADJ_L1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8821C) & BIT_MASK_V15ADJ_L1_V1_8821C) +#define BIT_SET_V15ADJ_L1_V1_8821C(x, v) \ + (BIT_CLEAR_V15ADJ_L1_V1_8821C(x) | BIT_V15ADJ_L1_V1_8821C(v)) #define BIT_SHIFT_VOL_L1_V1_8821C 20 #define BIT_MASK_VOL_L1_V1_8821C 0xf -#define BIT_VOL_L1_V1_8821C(x) (((x) & BIT_MASK_VOL_L1_V1_8821C) << BIT_SHIFT_VOL_L1_V1_8821C) -#define BIT_GET_VOL_L1_V1_8821C(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8821C) & BIT_MASK_VOL_L1_V1_8821C) - - +#define BIT_VOL_L1_V1_8821C(x) \ + (((x) & BIT_MASK_VOL_L1_V1_8821C) << BIT_SHIFT_VOL_L1_V1_8821C) +#define BITS_VOL_L1_V1_8821C \ + (BIT_MASK_VOL_L1_V1_8821C << BIT_SHIFT_VOL_L1_V1_8821C) +#define BIT_CLEAR_VOL_L1_V1_8821C(x) ((x) & (~BITS_VOL_L1_V1_8821C)) +#define BIT_GET_VOL_L1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_VOL_L1_V1_8821C) & BIT_MASK_VOL_L1_V1_8821C) +#define BIT_SET_VOL_L1_V1_8821C(x, v) \ + (BIT_CLEAR_VOL_L1_V1_8821C(x) | BIT_VOL_L1_V1_8821C(v)) #define BIT_SHIFT_IN_L1_V1_8821C 17 #define BIT_MASK_IN_L1_V1_8821C 0x7 -#define BIT_IN_L1_V1_8821C(x) (((x) & BIT_MASK_IN_L1_V1_8821C) << BIT_SHIFT_IN_L1_V1_8821C) -#define BIT_GET_IN_L1_V1_8821C(x) (((x) >> BIT_SHIFT_IN_L1_V1_8821C) & BIT_MASK_IN_L1_V1_8821C) - - +#define BIT_IN_L1_V1_8821C(x) \ + (((x) & BIT_MASK_IN_L1_V1_8821C) << BIT_SHIFT_IN_L1_V1_8821C) +#define BITS_IN_L1_V1_8821C \ + (BIT_MASK_IN_L1_V1_8821C << BIT_SHIFT_IN_L1_V1_8821C) +#define BIT_CLEAR_IN_L1_V1_8821C(x) ((x) & (~BITS_IN_L1_V1_8821C)) +#define BIT_GET_IN_L1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_IN_L1_V1_8821C) & BIT_MASK_IN_L1_V1_8821C) +#define BIT_SET_IN_L1_V1_8821C(x, v) \ + (BIT_CLEAR_IN_L1_V1_8821C(x) | BIT_IN_L1_V1_8821C(v)) #define BIT_SHIFT_TBOX_L1_8821C 15 #define BIT_MASK_TBOX_L1_8821C 0x3 -#define BIT_TBOX_L1_8821C(x) (((x) & BIT_MASK_TBOX_L1_8821C) << BIT_SHIFT_TBOX_L1_8821C) -#define BIT_GET_TBOX_L1_8821C(x) (((x) >> BIT_SHIFT_TBOX_L1_8821C) & BIT_MASK_TBOX_L1_8821C) - +#define BIT_TBOX_L1_8821C(x) \ + (((x) & BIT_MASK_TBOX_L1_8821C) << BIT_SHIFT_TBOX_L1_8821C) +#define BITS_TBOX_L1_8821C (BIT_MASK_TBOX_L1_8821C << BIT_SHIFT_TBOX_L1_8821C) +#define BIT_CLEAR_TBOX_L1_8821C(x) ((x) & (~BITS_TBOX_L1_8821C)) +#define BIT_GET_TBOX_L1_8821C(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_8821C) & BIT_MASK_TBOX_L1_8821C) +#define BIT_SET_TBOX_L1_8821C(x, v) \ + (BIT_CLEAR_TBOX_L1_8821C(x) | BIT_TBOX_L1_8821C(v)) #define BIT_SW18_SEL_8821C BIT(13) @@ -212,29 +287,44 @@ #define BIT_SHIFT_R3_L_8821C 7 #define BIT_MASK_R3_L_8821C 0x3 #define BIT_R3_L_8821C(x) (((x) & BIT_MASK_R3_L_8821C) << BIT_SHIFT_R3_L_8821C) -#define BIT_GET_R3_L_8821C(x) (((x) >> BIT_SHIFT_R3_L_8821C) & BIT_MASK_R3_L_8821C) - - +#define BITS_R3_L_8821C (BIT_MASK_R3_L_8821C << BIT_SHIFT_R3_L_8821C) +#define BIT_CLEAR_R3_L_8821C(x) ((x) & (~BITS_R3_L_8821C)) +#define BIT_GET_R3_L_8821C(x) \ + (((x) >> BIT_SHIFT_R3_L_8821C) & BIT_MASK_R3_L_8821C) +#define BIT_SET_R3_L_8821C(x, v) (BIT_CLEAR_R3_L_8821C(x) | BIT_R3_L_8821C(v)) #define BIT_SHIFT_SW18_R2_8821C 5 #define BIT_MASK_SW18_R2_8821C 0x3 -#define BIT_SW18_R2_8821C(x) (((x) & BIT_MASK_SW18_R2_8821C) << BIT_SHIFT_SW18_R2_8821C) -#define BIT_GET_SW18_R2_8821C(x) (((x) >> BIT_SHIFT_SW18_R2_8821C) & BIT_MASK_SW18_R2_8821C) - - +#define BIT_SW18_R2_8821C(x) \ + (((x) & BIT_MASK_SW18_R2_8821C) << BIT_SHIFT_SW18_R2_8821C) +#define BITS_SW18_R2_8821C (BIT_MASK_SW18_R2_8821C << BIT_SHIFT_SW18_R2_8821C) +#define BIT_CLEAR_SW18_R2_8821C(x) ((x) & (~BITS_SW18_R2_8821C)) +#define BIT_GET_SW18_R2_8821C(x) \ + (((x) >> BIT_SHIFT_SW18_R2_8821C) & BIT_MASK_SW18_R2_8821C) +#define BIT_SET_SW18_R2_8821C(x, v) \ + (BIT_CLEAR_SW18_R2_8821C(x) | BIT_SW18_R2_8821C(v)) #define BIT_SHIFT_SW18_R1_8821C 3 #define BIT_MASK_SW18_R1_8821C 0x3 -#define BIT_SW18_R1_8821C(x) (((x) & BIT_MASK_SW18_R1_8821C) << BIT_SHIFT_SW18_R1_8821C) -#define BIT_GET_SW18_R1_8821C(x) (((x) >> BIT_SHIFT_SW18_R1_8821C) & BIT_MASK_SW18_R1_8821C) - - +#define BIT_SW18_R1_8821C(x) \ + (((x) & BIT_MASK_SW18_R1_8821C) << BIT_SHIFT_SW18_R1_8821C) +#define BITS_SW18_R1_8821C (BIT_MASK_SW18_R1_8821C << BIT_SHIFT_SW18_R1_8821C) +#define BIT_CLEAR_SW18_R1_8821C(x) ((x) & (~BITS_SW18_R1_8821C)) +#define BIT_GET_SW18_R1_8821C(x) \ + (((x) >> BIT_SHIFT_SW18_R1_8821C) & BIT_MASK_SW18_R1_8821C) +#define BIT_SET_SW18_R1_8821C(x, v) \ + (BIT_CLEAR_SW18_R1_8821C(x) | BIT_SW18_R1_8821C(v)) #define BIT_SHIFT_C3_L_C3_8821C 1 #define BIT_MASK_C3_L_C3_8821C 0x3 -#define BIT_C3_L_C3_8821C(x) (((x) & BIT_MASK_C3_L_C3_8821C) << BIT_SHIFT_C3_L_C3_8821C) -#define BIT_GET_C3_L_C3_8821C(x) (((x) >> BIT_SHIFT_C3_L_C3_8821C) & BIT_MASK_C3_L_C3_8821C) - +#define BIT_C3_L_C3_8821C(x) \ + (((x) & BIT_MASK_C3_L_C3_8821C) << BIT_SHIFT_C3_L_C3_8821C) +#define BITS_C3_L_C3_8821C (BIT_MASK_C3_L_C3_8821C << BIT_SHIFT_C3_L_C3_8821C) +#define BIT_CLEAR_C3_L_C3_8821C(x) ((x) & (~BITS_C3_L_C3_8821C)) +#define BIT_GET_C3_L_C3_8821C(x) \ + (((x) >> BIT_SHIFT_C3_L_C3_8821C) & BIT_MASK_C3_L_C3_8821C) +#define BIT_SET_C3_L_C3_8821C(x, v) \ + (BIT_CLEAR_C3_L_C3_8821C(x) | BIT_C3_L_C3_8821C(v)) #define BIT_C2_L_BIT1_8821C BIT(0) @@ -243,17 +333,27 @@ #define BIT_SHIFT_SPS18_OCP_TH_8821C 16 #define BIT_MASK_SPS18_OCP_TH_8821C 0x7fff -#define BIT_SPS18_OCP_TH_8821C(x) (((x) & BIT_MASK_SPS18_OCP_TH_8821C) << BIT_SHIFT_SPS18_OCP_TH_8821C) -#define BIT_GET_SPS18_OCP_TH_8821C(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8821C) & BIT_MASK_SPS18_OCP_TH_8821C) - - +#define BIT_SPS18_OCP_TH_8821C(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH_8821C) << BIT_SHIFT_SPS18_OCP_TH_8821C) +#define BITS_SPS18_OCP_TH_8821C \ + (BIT_MASK_SPS18_OCP_TH_8821C << BIT_SHIFT_SPS18_OCP_TH_8821C) +#define BIT_CLEAR_SPS18_OCP_TH_8821C(x) ((x) & (~BITS_SPS18_OCP_TH_8821C)) +#define BIT_GET_SPS18_OCP_TH_8821C(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH_8821C) & BIT_MASK_SPS18_OCP_TH_8821C) +#define BIT_SET_SPS18_OCP_TH_8821C(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH_8821C(x) | BIT_SPS18_OCP_TH_8821C(v)) #define BIT_SHIFT_OCP_WINDOW_8821C 0 #define BIT_MASK_OCP_WINDOW_8821C 0xffff -#define BIT_OCP_WINDOW_8821C(x) (((x) & BIT_MASK_OCP_WINDOW_8821C) << BIT_SHIFT_OCP_WINDOW_8821C) -#define BIT_GET_OCP_WINDOW_8821C(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8821C) & BIT_MASK_OCP_WINDOW_8821C) - - +#define BIT_OCP_WINDOW_8821C(x) \ + (((x) & BIT_MASK_OCP_WINDOW_8821C) << BIT_SHIFT_OCP_WINDOW_8821C) +#define BITS_OCP_WINDOW_8821C \ + (BIT_MASK_OCP_WINDOW_8821C << BIT_SHIFT_OCP_WINDOW_8821C) +#define BIT_CLEAR_OCP_WINDOW_8821C(x) ((x) & (~BITS_OCP_WINDOW_8821C)) +#define BIT_GET_OCP_WINDOW_8821C(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW_8821C) & BIT_MASK_OCP_WINDOW_8821C) +#define BIT_SET_OCP_WINDOW_8821C(x, v) \ + (BIT_CLEAR_OCP_WINDOW_8821C(x) | BIT_OCP_WINDOW_8821C(v)) /* 2 REG_RSV_CTRL_8821C */ #define BIT_HREG_DBG_8821C BIT(23) @@ -276,17 +376,29 @@ #define BIT_SHIFT_LPLDH12_RSV_8821C 29 #define BIT_MASK_LPLDH12_RSV_8821C 0x7 -#define BIT_LPLDH12_RSV_8821C(x) (((x) & BIT_MASK_LPLDH12_RSV_8821C) << BIT_SHIFT_LPLDH12_RSV_8821C) -#define BIT_GET_LPLDH12_RSV_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8821C) & BIT_MASK_LPLDH12_RSV_8821C) - +#define BIT_LPLDH12_RSV_8821C(x) \ + (((x) & BIT_MASK_LPLDH12_RSV_8821C) << BIT_SHIFT_LPLDH12_RSV_8821C) +#define BITS_LPLDH12_RSV_8821C \ + (BIT_MASK_LPLDH12_RSV_8821C << BIT_SHIFT_LPLDH12_RSV_8821C) +#define BIT_CLEAR_LPLDH12_RSV_8821C(x) ((x) & (~BITS_LPLDH12_RSV_8821C)) +#define BIT_GET_LPLDH12_RSV_8821C(x) \ + (((x) >> BIT_SHIFT_LPLDH12_RSV_8821C) & BIT_MASK_LPLDH12_RSV_8821C) +#define BIT_SET_LPLDH12_RSV_8821C(x, v) \ + (BIT_CLEAR_LPLDH12_RSV_8821C(x) | BIT_LPLDH12_RSV_8821C(v)) #define BIT_LPLDH12_SLP_8821C BIT(28) #define BIT_SHIFT_LPLDH12_VADJ_8821C 24 #define BIT_MASK_LPLDH12_VADJ_8821C 0xf -#define BIT_LPLDH12_VADJ_8821C(x) (((x) & BIT_MASK_LPLDH12_VADJ_8821C) << BIT_SHIFT_LPLDH12_VADJ_8821C) -#define BIT_GET_LPLDH12_VADJ_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8821C) & BIT_MASK_LPLDH12_VADJ_8821C) - +#define BIT_LPLDH12_VADJ_8821C(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_8821C) << BIT_SHIFT_LPLDH12_VADJ_8821C) +#define BITS_LPLDH12_VADJ_8821C \ + (BIT_MASK_LPLDH12_VADJ_8821C << BIT_SHIFT_LPLDH12_VADJ_8821C) +#define BIT_CLEAR_LPLDH12_VADJ_8821C(x) ((x) & (~BITS_LPLDH12_VADJ_8821C)) +#define BIT_GET_LPLDH12_VADJ_8821C(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_8821C) & BIT_MASK_LPLDH12_VADJ_8821C) +#define BIT_SET_LPLDH12_VADJ_8821C(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_8821C(x) | BIT_LPLDH12_VADJ_8821C(v)) #define BIT_PCIE_CALIB_EN_8821C BIT(17) #define BIT_LDH12_EN_8821C BIT(16) @@ -311,46 +423,79 @@ #define BIT_SHIFT_XTAL_CAP_XI_8821C 25 #define BIT_MASK_XTAL_CAP_XI_8821C 0x3f -#define BIT_XTAL_CAP_XI_8821C(x) (((x) & BIT_MASK_XTAL_CAP_XI_8821C) << BIT_SHIFT_XTAL_CAP_XI_8821C) -#define BIT_GET_XTAL_CAP_XI_8821C(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8821C) & BIT_MASK_XTAL_CAP_XI_8821C) - - +#define BIT_XTAL_CAP_XI_8821C(x) \ + (((x) & BIT_MASK_XTAL_CAP_XI_8821C) << BIT_SHIFT_XTAL_CAP_XI_8821C) +#define BITS_XTAL_CAP_XI_8821C \ + (BIT_MASK_XTAL_CAP_XI_8821C << BIT_SHIFT_XTAL_CAP_XI_8821C) +#define BIT_CLEAR_XTAL_CAP_XI_8821C(x) ((x) & (~BITS_XTAL_CAP_XI_8821C)) +#define BIT_GET_XTAL_CAP_XI_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XI_8821C) & BIT_MASK_XTAL_CAP_XI_8821C) +#define BIT_SET_XTAL_CAP_XI_8821C(x, v) \ + (BIT_CLEAR_XTAL_CAP_XI_8821C(x) | BIT_XTAL_CAP_XI_8821C(v)) #define BIT_SHIFT_XTAL_DRV_DIGI_8821C 23 #define BIT_MASK_XTAL_DRV_DIGI_8821C 0x3 -#define BIT_XTAL_DRV_DIGI_8821C(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8821C) << BIT_SHIFT_XTAL_DRV_DIGI_8821C) -#define BIT_GET_XTAL_DRV_DIGI_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8821C) & BIT_MASK_XTAL_DRV_DIGI_8821C) - +#define BIT_XTAL_DRV_DIGI_8821C(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_8821C) << BIT_SHIFT_XTAL_DRV_DIGI_8821C) +#define BITS_XTAL_DRV_DIGI_8821C \ + (BIT_MASK_XTAL_DRV_DIGI_8821C << BIT_SHIFT_XTAL_DRV_DIGI_8821C) +#define BIT_CLEAR_XTAL_DRV_DIGI_8821C(x) ((x) & (~BITS_XTAL_DRV_DIGI_8821C)) +#define BIT_GET_XTAL_DRV_DIGI_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8821C) & BIT_MASK_XTAL_DRV_DIGI_8821C) +#define BIT_SET_XTAL_DRV_DIGI_8821C(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_8821C(x) | BIT_XTAL_DRV_DIGI_8821C(v)) #define BIT_XTAL_DRV_USB_BIT1_8821C BIT(22) #define BIT_SHIFT_MAC_CLK_SEL_8821C 20 #define BIT_MASK_MAC_CLK_SEL_8821C 0x3 -#define BIT_MAC_CLK_SEL_8821C(x) (((x) & BIT_MASK_MAC_CLK_SEL_8821C) << BIT_SHIFT_MAC_CLK_SEL_8821C) -#define BIT_GET_MAC_CLK_SEL_8821C(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8821C) & BIT_MASK_MAC_CLK_SEL_8821C) - +#define BIT_MAC_CLK_SEL_8821C(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_8821C) << BIT_SHIFT_MAC_CLK_SEL_8821C) +#define BITS_MAC_CLK_SEL_8821C \ + (BIT_MASK_MAC_CLK_SEL_8821C << BIT_SHIFT_MAC_CLK_SEL_8821C) +#define BIT_CLEAR_MAC_CLK_SEL_8821C(x) ((x) & (~BITS_MAC_CLK_SEL_8821C)) +#define BIT_GET_MAC_CLK_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_8821C) & BIT_MASK_MAC_CLK_SEL_8821C) +#define BIT_SET_MAC_CLK_SEL_8821C(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_8821C(x) | BIT_MAC_CLK_SEL_8821C(v)) #define BIT_XTAL_DRV_USB_BIT0_8821C BIT(19) #define BIT_SHIFT_XTAL_DRV_AFE_8821C 17 #define BIT_MASK_XTAL_DRV_AFE_8821C 0x3 -#define BIT_XTAL_DRV_AFE_8821C(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8821C) << BIT_SHIFT_XTAL_DRV_AFE_8821C) -#define BIT_GET_XTAL_DRV_AFE_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8821C) & BIT_MASK_XTAL_DRV_AFE_8821C) - - +#define BIT_XTAL_DRV_AFE_8821C(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_8821C) << BIT_SHIFT_XTAL_DRV_AFE_8821C) +#define BITS_XTAL_DRV_AFE_8821C \ + (BIT_MASK_XTAL_DRV_AFE_8821C << BIT_SHIFT_XTAL_DRV_AFE_8821C) +#define BIT_CLEAR_XTAL_DRV_AFE_8821C(x) ((x) & (~BITS_XTAL_DRV_AFE_8821C)) +#define BIT_GET_XTAL_DRV_AFE_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8821C) & BIT_MASK_XTAL_DRV_AFE_8821C) +#define BIT_SET_XTAL_DRV_AFE_8821C(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_8821C(x) | BIT_XTAL_DRV_AFE_8821C(v)) #define BIT_SHIFT_XTAL_DRV_RF2_8821C 15 #define BIT_MASK_XTAL_DRV_RF2_8821C 0x3 -#define BIT_XTAL_DRV_RF2_8821C(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8821C) << BIT_SHIFT_XTAL_DRV_RF2_8821C) -#define BIT_GET_XTAL_DRV_RF2_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8821C) & BIT_MASK_XTAL_DRV_RF2_8821C) - - +#define BIT_XTAL_DRV_RF2_8821C(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_8821C) << BIT_SHIFT_XTAL_DRV_RF2_8821C) +#define BITS_XTAL_DRV_RF2_8821C \ + (BIT_MASK_XTAL_DRV_RF2_8821C << BIT_SHIFT_XTAL_DRV_RF2_8821C) +#define BIT_CLEAR_XTAL_DRV_RF2_8821C(x) ((x) & (~BITS_XTAL_DRV_RF2_8821C)) +#define BIT_GET_XTAL_DRV_RF2_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8821C) & BIT_MASK_XTAL_DRV_RF2_8821C) +#define BIT_SET_XTAL_DRV_RF2_8821C(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_8821C(x) | BIT_XTAL_DRV_RF2_8821C(v)) #define BIT_SHIFT_XTAL_DRV_RF1_8821C 13 #define BIT_MASK_XTAL_DRV_RF1_8821C 0x3 -#define BIT_XTAL_DRV_RF1_8821C(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8821C) << BIT_SHIFT_XTAL_DRV_RF1_8821C) -#define BIT_GET_XTAL_DRV_RF1_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8821C) & BIT_MASK_XTAL_DRV_RF1_8821C) - +#define BIT_XTAL_DRV_RF1_8821C(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF1_8821C) << BIT_SHIFT_XTAL_DRV_RF1_8821C) +#define BITS_XTAL_DRV_RF1_8821C \ + (BIT_MASK_XTAL_DRV_RF1_8821C << BIT_SHIFT_XTAL_DRV_RF1_8821C) +#define BIT_CLEAR_XTAL_DRV_RF1_8821C(x) ((x) & (~BITS_XTAL_DRV_RF1_8821C)) +#define BIT_GET_XTAL_DRV_RF1_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8821C) & BIT_MASK_XTAL_DRV_RF1_8821C) +#define BIT_SET_XTAL_DRV_RF1_8821C(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF1_8821C(x) | BIT_XTAL_DRV_RF1_8821C(v)) #define BIT_XTAL_DELAY_DIGI_8821C BIT(12) #define BIT_XTAL_DELAY_USB_8821C BIT(11) @@ -358,25 +503,42 @@ #define BIT_SHIFT_XTAL_LDO_VREF_8821C 7 #define BIT_MASK_XTAL_LDO_VREF_8821C 0x7 -#define BIT_XTAL_LDO_VREF_8821C(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8821C) << BIT_SHIFT_XTAL_LDO_VREF_8821C) -#define BIT_GET_XTAL_LDO_VREF_8821C(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8821C) & BIT_MASK_XTAL_LDO_VREF_8821C) - +#define BIT_XTAL_LDO_VREF_8821C(x) \ + (((x) & BIT_MASK_XTAL_LDO_VREF_8821C) << BIT_SHIFT_XTAL_LDO_VREF_8821C) +#define BITS_XTAL_LDO_VREF_8821C \ + (BIT_MASK_XTAL_LDO_VREF_8821C << BIT_SHIFT_XTAL_LDO_VREF_8821C) +#define BIT_CLEAR_XTAL_LDO_VREF_8821C(x) ((x) & (~BITS_XTAL_LDO_VREF_8821C)) +#define BIT_GET_XTAL_LDO_VREF_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8821C) & BIT_MASK_XTAL_LDO_VREF_8821C) +#define BIT_SET_XTAL_LDO_VREF_8821C(x, v) \ + (BIT_CLEAR_XTAL_LDO_VREF_8821C(x) | BIT_XTAL_LDO_VREF_8821C(v)) #define BIT_XTAL_XQSEL_RF_8821C BIT(6) #define BIT_XTAL_XQSEL_8821C BIT(5) #define BIT_SHIFT_XTAL_GMN_V2_8821C 3 #define BIT_MASK_XTAL_GMN_V2_8821C 0x3 -#define BIT_XTAL_GMN_V2_8821C(x) (((x) & BIT_MASK_XTAL_GMN_V2_8821C) << BIT_SHIFT_XTAL_GMN_V2_8821C) -#define BIT_GET_XTAL_GMN_V2_8821C(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8821C) & BIT_MASK_XTAL_GMN_V2_8821C) - - +#define BIT_XTAL_GMN_V2_8821C(x) \ + (((x) & BIT_MASK_XTAL_GMN_V2_8821C) << BIT_SHIFT_XTAL_GMN_V2_8821C) +#define BITS_XTAL_GMN_V2_8821C \ + (BIT_MASK_XTAL_GMN_V2_8821C << BIT_SHIFT_XTAL_GMN_V2_8821C) +#define BIT_CLEAR_XTAL_GMN_V2_8821C(x) ((x) & (~BITS_XTAL_GMN_V2_8821C)) +#define BIT_GET_XTAL_GMN_V2_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V2_8821C) & BIT_MASK_XTAL_GMN_V2_8821C) +#define BIT_SET_XTAL_GMN_V2_8821C(x, v) \ + (BIT_CLEAR_XTAL_GMN_V2_8821C(x) | BIT_XTAL_GMN_V2_8821C(v)) #define BIT_SHIFT_XTAL_GMP_V2_8821C 1 #define BIT_MASK_XTAL_GMP_V2_8821C 0x3 -#define BIT_XTAL_GMP_V2_8821C(x) (((x) & BIT_MASK_XTAL_GMP_V2_8821C) << BIT_SHIFT_XTAL_GMP_V2_8821C) -#define BIT_GET_XTAL_GMP_V2_8821C(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8821C) & BIT_MASK_XTAL_GMP_V2_8821C) - +#define BIT_XTAL_GMP_V2_8821C(x) \ + (((x) & BIT_MASK_XTAL_GMP_V2_8821C) << BIT_SHIFT_XTAL_GMP_V2_8821C) +#define BITS_XTAL_GMP_V2_8821C \ + (BIT_MASK_XTAL_GMP_V2_8821C << BIT_SHIFT_XTAL_GMP_V2_8821C) +#define BIT_CLEAR_XTAL_GMP_V2_8821C(x) ((x) & (~BITS_XTAL_GMP_V2_8821C)) +#define BIT_GET_XTAL_GMP_V2_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V2_8821C) & BIT_MASK_XTAL_GMP_V2_8821C) +#define BIT_SET_XTAL_GMP_V2_8821C(x, v) \ + (BIT_CLEAR_XTAL_GMP_V2_8821C(x) | BIT_XTAL_GMP_V2_8821C(v)) #define BIT_XTAL_EN_8821C BIT(0) @@ -384,38 +546,63 @@ #define BIT_SHIFT_REG_C3_V4_8821C 30 #define BIT_MASK_REG_C3_V4_8821C 0x3 -#define BIT_REG_C3_V4_8821C(x) (((x) & BIT_MASK_REG_C3_V4_8821C) << BIT_SHIFT_REG_C3_V4_8821C) -#define BIT_GET_REG_C3_V4_8821C(x) (((x) >> BIT_SHIFT_REG_C3_V4_8821C) & BIT_MASK_REG_C3_V4_8821C) - +#define BIT_REG_C3_V4_8821C(x) \ + (((x) & BIT_MASK_REG_C3_V4_8821C) << BIT_SHIFT_REG_C3_V4_8821C) +#define BITS_REG_C3_V4_8821C \ + (BIT_MASK_REG_C3_V4_8821C << BIT_SHIFT_REG_C3_V4_8821C) +#define BIT_CLEAR_REG_C3_V4_8821C(x) ((x) & (~BITS_REG_C3_V4_8821C)) +#define BIT_GET_REG_C3_V4_8821C(x) \ + (((x) >> BIT_SHIFT_REG_C3_V4_8821C) & BIT_MASK_REG_C3_V4_8821C) +#define BIT_SET_REG_C3_V4_8821C(x, v) \ + (BIT_CLEAR_REG_C3_V4_8821C(x) | BIT_REG_C3_V4_8821C(v)) #define BIT_REG_CP_BIT1_8821C BIT(29) #define BIT_SHIFT_REG_RS_V4_8821C 26 #define BIT_MASK_REG_RS_V4_8821C 0x7 -#define BIT_REG_RS_V4_8821C(x) (((x) & BIT_MASK_REG_RS_V4_8821C) << BIT_SHIFT_REG_RS_V4_8821C) -#define BIT_GET_REG_RS_V4_8821C(x) (((x) >> BIT_SHIFT_REG_RS_V4_8821C) & BIT_MASK_REG_RS_V4_8821C) - - +#define BIT_REG_RS_V4_8821C(x) \ + (((x) & BIT_MASK_REG_RS_V4_8821C) << BIT_SHIFT_REG_RS_V4_8821C) +#define BITS_REG_RS_V4_8821C \ + (BIT_MASK_REG_RS_V4_8821C << BIT_SHIFT_REG_RS_V4_8821C) +#define BIT_CLEAR_REG_RS_V4_8821C(x) ((x) & (~BITS_REG_RS_V4_8821C)) +#define BIT_GET_REG_RS_V4_8821C(x) \ + (((x) >> BIT_SHIFT_REG_RS_V4_8821C) & BIT_MASK_REG_RS_V4_8821C) +#define BIT_SET_REG_RS_V4_8821C(x, v) \ + (BIT_CLEAR_REG_RS_V4_8821C(x) | BIT_REG_RS_V4_8821C(v)) #define BIT_SHIFT_REG__CS_8821C 24 #define BIT_MASK_REG__CS_8821C 0x3 -#define BIT_REG__CS_8821C(x) (((x) & BIT_MASK_REG__CS_8821C) << BIT_SHIFT_REG__CS_8821C) -#define BIT_GET_REG__CS_8821C(x) (((x) >> BIT_SHIFT_REG__CS_8821C) & BIT_MASK_REG__CS_8821C) - - +#define BIT_REG__CS_8821C(x) \ + (((x) & BIT_MASK_REG__CS_8821C) << BIT_SHIFT_REG__CS_8821C) +#define BITS_REG__CS_8821C (BIT_MASK_REG__CS_8821C << BIT_SHIFT_REG__CS_8821C) +#define BIT_CLEAR_REG__CS_8821C(x) ((x) & (~BITS_REG__CS_8821C)) +#define BIT_GET_REG__CS_8821C(x) \ + (((x) >> BIT_SHIFT_REG__CS_8821C) & BIT_MASK_REG__CS_8821C) +#define BIT_SET_REG__CS_8821C(x, v) \ + (BIT_CLEAR_REG__CS_8821C(x) | BIT_REG__CS_8821C(v)) #define BIT_SHIFT_REG_CP_OFFSET_8821C 21 #define BIT_MASK_REG_CP_OFFSET_8821C 0x7 -#define BIT_REG_CP_OFFSET_8821C(x) (((x) & BIT_MASK_REG_CP_OFFSET_8821C) << BIT_SHIFT_REG_CP_OFFSET_8821C) -#define BIT_GET_REG_CP_OFFSET_8821C(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8821C) & BIT_MASK_REG_CP_OFFSET_8821C) - - +#define BIT_REG_CP_OFFSET_8821C(x) \ + (((x) & BIT_MASK_REG_CP_OFFSET_8821C) << BIT_SHIFT_REG_CP_OFFSET_8821C) +#define BITS_REG_CP_OFFSET_8821C \ + (BIT_MASK_REG_CP_OFFSET_8821C << BIT_SHIFT_REG_CP_OFFSET_8821C) +#define BIT_CLEAR_REG_CP_OFFSET_8821C(x) ((x) & (~BITS_REG_CP_OFFSET_8821C)) +#define BIT_GET_REG_CP_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_REG_CP_OFFSET_8821C) & BIT_MASK_REG_CP_OFFSET_8821C) +#define BIT_SET_REG_CP_OFFSET_8821C(x, v) \ + (BIT_CLEAR_REG_CP_OFFSET_8821C(x) | BIT_REG_CP_OFFSET_8821C(v)) #define BIT_SHIFT_CP_BIAS_8821C 18 #define BIT_MASK_CP_BIAS_8821C 0x7 -#define BIT_CP_BIAS_8821C(x) (((x) & BIT_MASK_CP_BIAS_8821C) << BIT_SHIFT_CP_BIAS_8821C) -#define BIT_GET_CP_BIAS_8821C(x) (((x) >> BIT_SHIFT_CP_BIAS_8821C) & BIT_MASK_CP_BIAS_8821C) - +#define BIT_CP_BIAS_8821C(x) \ + (((x) & BIT_MASK_CP_BIAS_8821C) << BIT_SHIFT_CP_BIAS_8821C) +#define BITS_CP_BIAS_8821C (BIT_MASK_CP_BIAS_8821C << BIT_SHIFT_CP_BIAS_8821C) +#define BIT_CLEAR_CP_BIAS_8821C(x) ((x) & (~BITS_CP_BIAS_8821C)) +#define BIT_GET_CP_BIAS_8821C(x) \ + (((x) >> BIT_SHIFT_CP_BIAS_8821C) & BIT_MASK_CP_BIAS_8821C) +#define BIT_SET_CP_BIAS_8821C(x, v) \ + (BIT_CLEAR_CP_BIAS_8821C(x) | BIT_CP_BIAS_8821C(v)) #define BIT_REG_IDOUBLE_V2_8821C BIT(17) #define BIT_EN_SYN_8821C BIT(16) @@ -423,31 +610,50 @@ #define BIT_SHIFT_MCCO_8821C 14 #define BIT_MASK_MCCO_8821C 0x3 #define BIT_MCCO_8821C(x) (((x) & BIT_MASK_MCCO_8821C) << BIT_SHIFT_MCCO_8821C) -#define BIT_GET_MCCO_8821C(x) (((x) >> BIT_SHIFT_MCCO_8821C) & BIT_MASK_MCCO_8821C) - - +#define BITS_MCCO_8821C (BIT_MASK_MCCO_8821C << BIT_SHIFT_MCCO_8821C) +#define BIT_CLEAR_MCCO_8821C(x) ((x) & (~BITS_MCCO_8821C)) +#define BIT_GET_MCCO_8821C(x) \ + (((x) >> BIT_SHIFT_MCCO_8821C) & BIT_MASK_MCCO_8821C) +#define BIT_SET_MCCO_8821C(x, v) (BIT_CLEAR_MCCO_8821C(x) | BIT_MCCO_8821C(v)) #define BIT_SHIFT_REG_LDO_SEL_8821C 12 #define BIT_MASK_REG_LDO_SEL_8821C 0x3 -#define BIT_REG_LDO_SEL_8821C(x) (((x) & BIT_MASK_REG_LDO_SEL_8821C) << BIT_SHIFT_REG_LDO_SEL_8821C) -#define BIT_GET_REG_LDO_SEL_8821C(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8821C) & BIT_MASK_REG_LDO_SEL_8821C) - +#define BIT_REG_LDO_SEL_8821C(x) \ + (((x) & BIT_MASK_REG_LDO_SEL_8821C) << BIT_SHIFT_REG_LDO_SEL_8821C) +#define BITS_REG_LDO_SEL_8821C \ + (BIT_MASK_REG_LDO_SEL_8821C << BIT_SHIFT_REG_LDO_SEL_8821C) +#define BIT_CLEAR_REG_LDO_SEL_8821C(x) ((x) & (~BITS_REG_LDO_SEL_8821C)) +#define BIT_GET_REG_LDO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_REG_LDO_SEL_8821C) & BIT_MASK_REG_LDO_SEL_8821C) +#define BIT_SET_REG_LDO_SEL_8821C(x, v) \ + (BIT_CLEAR_REG_LDO_SEL_8821C(x) | BIT_REG_LDO_SEL_8821C(v)) #define BIT_REG_KVCO_V2_8821C BIT(10) #define BIT_AGPIO_GPO_8821C BIT(9) #define BIT_SHIFT_AGPIO_DRV_8821C 7 #define BIT_MASK_AGPIO_DRV_8821C 0x3 -#define BIT_AGPIO_DRV_8821C(x) (((x) & BIT_MASK_AGPIO_DRV_8821C) << BIT_SHIFT_AGPIO_DRV_8821C) -#define BIT_GET_AGPIO_DRV_8821C(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8821C) & BIT_MASK_AGPIO_DRV_8821C) - - +#define BIT_AGPIO_DRV_8821C(x) \ + (((x) & BIT_MASK_AGPIO_DRV_8821C) << BIT_SHIFT_AGPIO_DRV_8821C) +#define BITS_AGPIO_DRV_8821C \ + (BIT_MASK_AGPIO_DRV_8821C << BIT_SHIFT_AGPIO_DRV_8821C) +#define BIT_CLEAR_AGPIO_DRV_8821C(x) ((x) & (~BITS_AGPIO_DRV_8821C)) +#define BIT_GET_AGPIO_DRV_8821C(x) \ + (((x) >> BIT_SHIFT_AGPIO_DRV_8821C) & BIT_MASK_AGPIO_DRV_8821C) +#define BIT_SET_AGPIO_DRV_8821C(x, v) \ + (BIT_CLEAR_AGPIO_DRV_8821C(x) | BIT_AGPIO_DRV_8821C(v)) #define BIT_SHIFT_XTAL_CAP_XO_8821C 1 #define BIT_MASK_XTAL_CAP_XO_8821C 0x3f -#define BIT_XTAL_CAP_XO_8821C(x) (((x) & BIT_MASK_XTAL_CAP_XO_8821C) << BIT_SHIFT_XTAL_CAP_XO_8821C) -#define BIT_GET_XTAL_CAP_XO_8821C(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8821C) & BIT_MASK_XTAL_CAP_XO_8821C) - +#define BIT_XTAL_CAP_XO_8821C(x) \ + (((x) & BIT_MASK_XTAL_CAP_XO_8821C) << BIT_SHIFT_XTAL_CAP_XO_8821C) +#define BITS_XTAL_CAP_XO_8821C \ + (BIT_MASK_XTAL_CAP_XO_8821C << BIT_SHIFT_XTAL_CAP_XO_8821C) +#define BIT_CLEAR_XTAL_CAP_XO_8821C(x) ((x) & (~BITS_XTAL_CAP_XO_8821C)) +#define BIT_GET_XTAL_CAP_XO_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XO_8821C) & BIT_MASK_XTAL_CAP_XO_8821C) +#define BIT_SET_XTAL_CAP_XO_8821C(x, v) \ + (BIT_CLEAR_XTAL_CAP_XO_8821C(x) | BIT_XTAL_CAP_XO_8821C(v)) #define BIT_POW_PLL_8821C BIT(0) @@ -456,8 +662,10 @@ #define BIT_SHIFT_PS_8821C 7 #define BIT_MASK_PS_8821C 0x7 #define BIT_PS_8821C(x) (((x) & BIT_MASK_PS_8821C) << BIT_SHIFT_PS_8821C) +#define BITS_PS_8821C (BIT_MASK_PS_8821C << BIT_SHIFT_PS_8821C) +#define BIT_CLEAR_PS_8821C(x) ((x) & (~BITS_PS_8821C)) #define BIT_GET_PS_8821C(x) (((x) >> BIT_SHIFT_PS_8821C) & BIT_MASK_PS_8821C) - +#define BIT_SET_PS_8821C(x, v) (BIT_CLEAR_PS_8821C(x) | BIT_PS_8821C(v)) #define BIT_PSEN_8821C BIT(6) #define BIT_DOGENB_8821C BIT(5) @@ -465,9 +673,15 @@ #define BIT_SHIFT_REG_R3_V4_8821C 1 #define BIT_MASK_REG_R3_V4_8821C 0x7 -#define BIT_REG_R3_V4_8821C(x) (((x) & BIT_MASK_REG_R3_V4_8821C) << BIT_SHIFT_REG_R3_V4_8821C) -#define BIT_GET_REG_R3_V4_8821C(x) (((x) >> BIT_SHIFT_REG_R3_V4_8821C) & BIT_MASK_REG_R3_V4_8821C) - +#define BIT_REG_R3_V4_8821C(x) \ + (((x) & BIT_MASK_REG_R3_V4_8821C) << BIT_SHIFT_REG_R3_V4_8821C) +#define BITS_REG_R3_V4_8821C \ + (BIT_MASK_REG_R3_V4_8821C << BIT_SHIFT_REG_R3_V4_8821C) +#define BIT_CLEAR_REG_R3_V4_8821C(x) ((x) & (~BITS_REG_R3_V4_8821C)) +#define BIT_GET_REG_R3_V4_8821C(x) \ + (((x) >> BIT_SHIFT_REG_R3_V4_8821C) & BIT_MASK_REG_R3_V4_8821C) +#define BIT_SET_REG_R3_V4_8821C(x, v) \ + (BIT_CLEAR_REG_R3_V4_8821C(x) | BIT_REG_R3_V4_8821C(v)) #define BIT_REG_CP_BIT0_8821C BIT(0) @@ -476,103 +690,172 @@ #define BIT_SHIFT_EF_PGPD_8821C 28 #define BIT_MASK_EF_PGPD_8821C 0x7 -#define BIT_EF_PGPD_8821C(x) (((x) & BIT_MASK_EF_PGPD_8821C) << BIT_SHIFT_EF_PGPD_8821C) -#define BIT_GET_EF_PGPD_8821C(x) (((x) >> BIT_SHIFT_EF_PGPD_8821C) & BIT_MASK_EF_PGPD_8821C) - - +#define BIT_EF_PGPD_8821C(x) \ + (((x) & BIT_MASK_EF_PGPD_8821C) << BIT_SHIFT_EF_PGPD_8821C) +#define BITS_EF_PGPD_8821C (BIT_MASK_EF_PGPD_8821C << BIT_SHIFT_EF_PGPD_8821C) +#define BIT_CLEAR_EF_PGPD_8821C(x) ((x) & (~BITS_EF_PGPD_8821C)) +#define BIT_GET_EF_PGPD_8821C(x) \ + (((x) >> BIT_SHIFT_EF_PGPD_8821C) & BIT_MASK_EF_PGPD_8821C) +#define BIT_SET_EF_PGPD_8821C(x, v) \ + (BIT_CLEAR_EF_PGPD_8821C(x) | BIT_EF_PGPD_8821C(v)) #define BIT_SHIFT_EF_RDT_8821C 24 #define BIT_MASK_EF_RDT_8821C 0xf -#define BIT_EF_RDT_8821C(x) (((x) & BIT_MASK_EF_RDT_8821C) << BIT_SHIFT_EF_RDT_8821C) -#define BIT_GET_EF_RDT_8821C(x) (((x) >> BIT_SHIFT_EF_RDT_8821C) & BIT_MASK_EF_RDT_8821C) - - +#define BIT_EF_RDT_8821C(x) \ + (((x) & BIT_MASK_EF_RDT_8821C) << BIT_SHIFT_EF_RDT_8821C) +#define BITS_EF_RDT_8821C (BIT_MASK_EF_RDT_8821C << BIT_SHIFT_EF_RDT_8821C) +#define BIT_CLEAR_EF_RDT_8821C(x) ((x) & (~BITS_EF_RDT_8821C)) +#define BIT_GET_EF_RDT_8821C(x) \ + (((x) >> BIT_SHIFT_EF_RDT_8821C) & BIT_MASK_EF_RDT_8821C) +#define BIT_SET_EF_RDT_8821C(x, v) \ + (BIT_CLEAR_EF_RDT_8821C(x) | BIT_EF_RDT_8821C(v)) #define BIT_SHIFT_EF_PGTS_8821C 20 #define BIT_MASK_EF_PGTS_8821C 0xf -#define BIT_EF_PGTS_8821C(x) (((x) & BIT_MASK_EF_PGTS_8821C) << BIT_SHIFT_EF_PGTS_8821C) -#define BIT_GET_EF_PGTS_8821C(x) (((x) >> BIT_SHIFT_EF_PGTS_8821C) & BIT_MASK_EF_PGTS_8821C) - +#define BIT_EF_PGTS_8821C(x) \ + (((x) & BIT_MASK_EF_PGTS_8821C) << BIT_SHIFT_EF_PGTS_8821C) +#define BITS_EF_PGTS_8821C (BIT_MASK_EF_PGTS_8821C << BIT_SHIFT_EF_PGTS_8821C) +#define BIT_CLEAR_EF_PGTS_8821C(x) ((x) & (~BITS_EF_PGTS_8821C)) +#define BIT_GET_EF_PGTS_8821C(x) \ + (((x) >> BIT_SHIFT_EF_PGTS_8821C) & BIT_MASK_EF_PGTS_8821C) +#define BIT_SET_EF_PGTS_8821C(x, v) \ + (BIT_CLEAR_EF_PGTS_8821C(x) | BIT_EF_PGTS_8821C(v)) #define BIT_EF_PDWN_8821C BIT(19) #define BIT_EF_ALDEN_8821C BIT(18) #define BIT_SHIFT_EF_ADDR_8821C 8 #define BIT_MASK_EF_ADDR_8821C 0x3ff -#define BIT_EF_ADDR_8821C(x) (((x) & BIT_MASK_EF_ADDR_8821C) << BIT_SHIFT_EF_ADDR_8821C) -#define BIT_GET_EF_ADDR_8821C(x) (((x) >> BIT_SHIFT_EF_ADDR_8821C) & BIT_MASK_EF_ADDR_8821C) - - +#define BIT_EF_ADDR_8821C(x) \ + (((x) & BIT_MASK_EF_ADDR_8821C) << BIT_SHIFT_EF_ADDR_8821C) +#define BITS_EF_ADDR_8821C (BIT_MASK_EF_ADDR_8821C << BIT_SHIFT_EF_ADDR_8821C) +#define BIT_CLEAR_EF_ADDR_8821C(x) ((x) & (~BITS_EF_ADDR_8821C)) +#define BIT_GET_EF_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_EF_ADDR_8821C) & BIT_MASK_EF_ADDR_8821C) +#define BIT_SET_EF_ADDR_8821C(x, v) \ + (BIT_CLEAR_EF_ADDR_8821C(x) | BIT_EF_ADDR_8821C(v)) #define BIT_SHIFT_EF_DATA_8821C 0 #define BIT_MASK_EF_DATA_8821C 0xff -#define BIT_EF_DATA_8821C(x) (((x) & BIT_MASK_EF_DATA_8821C) << BIT_SHIFT_EF_DATA_8821C) -#define BIT_GET_EF_DATA_8821C(x) (((x) >> BIT_SHIFT_EF_DATA_8821C) & BIT_MASK_EF_DATA_8821C) - - +#define BIT_EF_DATA_8821C(x) \ + (((x) & BIT_MASK_EF_DATA_8821C) << BIT_SHIFT_EF_DATA_8821C) +#define BITS_EF_DATA_8821C (BIT_MASK_EF_DATA_8821C << BIT_SHIFT_EF_DATA_8821C) +#define BIT_CLEAR_EF_DATA_8821C(x) ((x) & (~BITS_EF_DATA_8821C)) +#define BIT_GET_EF_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_EF_DATA_8821C) & BIT_MASK_EF_DATA_8821C) +#define BIT_SET_EF_DATA_8821C(x, v) \ + (BIT_CLEAR_EF_DATA_8821C(x) | BIT_EF_DATA_8821C(v)) /* 2 REG_LDO_EFUSE_CTRL_8821C */ #define BIT_LDOE25_EN_8821C BIT(31) #define BIT_SHIFT_LDOE25_V12ADJ_L_8821C 27 #define BIT_MASK_LDOE25_V12ADJ_L_8821C 0xf -#define BIT_LDOE25_V12ADJ_L_8821C(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8821C) << BIT_SHIFT_LDOE25_V12ADJ_L_8821C) -#define BIT_GET_LDOE25_V12ADJ_L_8821C(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8821C) & BIT_MASK_LDOE25_V12ADJ_L_8821C) - +#define BIT_LDOE25_V12ADJ_L_8821C(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L_8821C) \ + << BIT_SHIFT_LDOE25_V12ADJ_L_8821C) +#define BITS_LDOE25_V12ADJ_L_8821C \ + (BIT_MASK_LDOE25_V12ADJ_L_8821C << BIT_SHIFT_LDOE25_V12ADJ_L_8821C) +#define BIT_CLEAR_LDOE25_V12ADJ_L_8821C(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8821C)) +#define BIT_GET_LDOE25_V12ADJ_L_8821C(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8821C) & \ + BIT_MASK_LDOE25_V12ADJ_L_8821C) +#define BIT_SET_LDOE25_V12ADJ_L_8821C(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L_8821C(x) | BIT_LDOE25_V12ADJ_L_8821C(v)) #define BIT_EF_CRES_SEL_8821C BIT(26) #define BIT_SHIFT_EF_SCAN_START_V1_8821C 16 #define BIT_MASK_EF_SCAN_START_V1_8821C 0x3ff -#define BIT_EF_SCAN_START_V1_8821C(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8821C) << BIT_SHIFT_EF_SCAN_START_V1_8821C) -#define BIT_GET_EF_SCAN_START_V1_8821C(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8821C) & BIT_MASK_EF_SCAN_START_V1_8821C) - - +#define BIT_EF_SCAN_START_V1_8821C(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1_8821C) \ + << BIT_SHIFT_EF_SCAN_START_V1_8821C) +#define BITS_EF_SCAN_START_V1_8821C \ + (BIT_MASK_EF_SCAN_START_V1_8821C << BIT_SHIFT_EF_SCAN_START_V1_8821C) +#define BIT_CLEAR_EF_SCAN_START_V1_8821C(x) \ + ((x) & (~BITS_EF_SCAN_START_V1_8821C)) +#define BIT_GET_EF_SCAN_START_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8821C) & \ + BIT_MASK_EF_SCAN_START_V1_8821C) +#define BIT_SET_EF_SCAN_START_V1_8821C(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1_8821C(x) | BIT_EF_SCAN_START_V1_8821C(v)) #define BIT_SHIFT_EF_SCAN_END_8821C 12 #define BIT_MASK_EF_SCAN_END_8821C 0xf -#define BIT_EF_SCAN_END_8821C(x) (((x) & BIT_MASK_EF_SCAN_END_8821C) << BIT_SHIFT_EF_SCAN_END_8821C) -#define BIT_GET_EF_SCAN_END_8821C(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8821C) & BIT_MASK_EF_SCAN_END_8821C) - +#define BIT_EF_SCAN_END_8821C(x) \ + (((x) & BIT_MASK_EF_SCAN_END_8821C) << BIT_SHIFT_EF_SCAN_END_8821C) +#define BITS_EF_SCAN_END_8821C \ + (BIT_MASK_EF_SCAN_END_8821C << BIT_SHIFT_EF_SCAN_END_8821C) +#define BIT_CLEAR_EF_SCAN_END_8821C(x) ((x) & (~BITS_EF_SCAN_END_8821C)) +#define BIT_GET_EF_SCAN_END_8821C(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END_8821C) & BIT_MASK_EF_SCAN_END_8821C) +#define BIT_SET_EF_SCAN_END_8821C(x, v) \ + (BIT_CLEAR_EF_SCAN_END_8821C(x) | BIT_EF_SCAN_END_8821C(v)) #define BIT_EF_PD_DIS_8821C BIT(11) #define BIT_SHIFT_EF_CELL_SEL_8821C 8 #define BIT_MASK_EF_CELL_SEL_8821C 0x3 -#define BIT_EF_CELL_SEL_8821C(x) (((x) & BIT_MASK_EF_CELL_SEL_8821C) << BIT_SHIFT_EF_CELL_SEL_8821C) -#define BIT_GET_EF_CELL_SEL_8821C(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8821C) & BIT_MASK_EF_CELL_SEL_8821C) - +#define BIT_EF_CELL_SEL_8821C(x) \ + (((x) & BIT_MASK_EF_CELL_SEL_8821C) << BIT_SHIFT_EF_CELL_SEL_8821C) +#define BITS_EF_CELL_SEL_8821C \ + (BIT_MASK_EF_CELL_SEL_8821C << BIT_SHIFT_EF_CELL_SEL_8821C) +#define BIT_CLEAR_EF_CELL_SEL_8821C(x) ((x) & (~BITS_EF_CELL_SEL_8821C)) +#define BIT_GET_EF_CELL_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL_8821C) & BIT_MASK_EF_CELL_SEL_8821C) +#define BIT_SET_EF_CELL_SEL_8821C(x, v) \ + (BIT_CLEAR_EF_CELL_SEL_8821C(x) | BIT_EF_CELL_SEL_8821C(v)) #define BIT_EF_TRPT_8821C BIT(7) #define BIT_SHIFT_EF_TTHD_8821C 0 #define BIT_MASK_EF_TTHD_8821C 0x7f -#define BIT_EF_TTHD_8821C(x) (((x) & BIT_MASK_EF_TTHD_8821C) << BIT_SHIFT_EF_TTHD_8821C) -#define BIT_GET_EF_TTHD_8821C(x) (((x) >> BIT_SHIFT_EF_TTHD_8821C) & BIT_MASK_EF_TTHD_8821C) - - +#define BIT_EF_TTHD_8821C(x) \ + (((x) & BIT_MASK_EF_TTHD_8821C) << BIT_SHIFT_EF_TTHD_8821C) +#define BITS_EF_TTHD_8821C (BIT_MASK_EF_TTHD_8821C << BIT_SHIFT_EF_TTHD_8821C) +#define BIT_CLEAR_EF_TTHD_8821C(x) ((x) & (~BITS_EF_TTHD_8821C)) +#define BIT_GET_EF_TTHD_8821C(x) \ + (((x) >> BIT_SHIFT_EF_TTHD_8821C) & BIT_MASK_EF_TTHD_8821C) +#define BIT_SET_EF_TTHD_8821C(x, v) \ + (BIT_CLEAR_EF_TTHD_8821C(x) | BIT_EF_TTHD_8821C(v)) /* 2 REG_PWR_OPTION_CTRL_8821C */ #define BIT_SHIFT_DBG_SEL_V1_8821C 16 #define BIT_MASK_DBG_SEL_V1_8821C 0xff -#define BIT_DBG_SEL_V1_8821C(x) (((x) & BIT_MASK_DBG_SEL_V1_8821C) << BIT_SHIFT_DBG_SEL_V1_8821C) -#define BIT_GET_DBG_SEL_V1_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8821C) & BIT_MASK_DBG_SEL_V1_8821C) - - +#define BIT_DBG_SEL_V1_8821C(x) \ + (((x) & BIT_MASK_DBG_SEL_V1_8821C) << BIT_SHIFT_DBG_SEL_V1_8821C) +#define BITS_DBG_SEL_V1_8821C \ + (BIT_MASK_DBG_SEL_V1_8821C << BIT_SHIFT_DBG_SEL_V1_8821C) +#define BIT_CLEAR_DBG_SEL_V1_8821C(x) ((x) & (~BITS_DBG_SEL_V1_8821C)) +#define BIT_GET_DBG_SEL_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1_8821C) & BIT_MASK_DBG_SEL_V1_8821C) +#define BIT_SET_DBG_SEL_V1_8821C(x, v) \ + (BIT_CLEAR_DBG_SEL_V1_8821C(x) | BIT_DBG_SEL_V1_8821C(v)) #define BIT_SHIFT_DBG_SEL_BYTE_8821C 14 #define BIT_MASK_DBG_SEL_BYTE_8821C 0x3 -#define BIT_DBG_SEL_BYTE_8821C(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8821C) << BIT_SHIFT_DBG_SEL_BYTE_8821C) -#define BIT_GET_DBG_SEL_BYTE_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8821C) & BIT_MASK_DBG_SEL_BYTE_8821C) - - +#define BIT_DBG_SEL_BYTE_8821C(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE_8821C) << BIT_SHIFT_DBG_SEL_BYTE_8821C) +#define BITS_DBG_SEL_BYTE_8821C \ + (BIT_MASK_DBG_SEL_BYTE_8821C << BIT_SHIFT_DBG_SEL_BYTE_8821C) +#define BIT_CLEAR_DBG_SEL_BYTE_8821C(x) ((x) & (~BITS_DBG_SEL_BYTE_8821C)) +#define BIT_GET_DBG_SEL_BYTE_8821C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8821C) & BIT_MASK_DBG_SEL_BYTE_8821C) +#define BIT_SET_DBG_SEL_BYTE_8821C(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE_8821C(x) | BIT_DBG_SEL_BYTE_8821C(v)) #define BIT_SHIFT_STD_L1_V1_8821C 12 #define BIT_MASK_STD_L1_V1_8821C 0x3 -#define BIT_STD_L1_V1_8821C(x) (((x) & BIT_MASK_STD_L1_V1_8821C) << BIT_SHIFT_STD_L1_V1_8821C) -#define BIT_GET_STD_L1_V1_8821C(x) (((x) >> BIT_SHIFT_STD_L1_V1_8821C) & BIT_MASK_STD_L1_V1_8821C) - +#define BIT_STD_L1_V1_8821C(x) \ + (((x) & BIT_MASK_STD_L1_V1_8821C) << BIT_SHIFT_STD_L1_V1_8821C) +#define BITS_STD_L1_V1_8821C \ + (BIT_MASK_STD_L1_V1_8821C << BIT_SHIFT_STD_L1_V1_8821C) +#define BIT_CLEAR_STD_L1_V1_8821C(x) ((x) & (~BITS_STD_L1_V1_8821C)) +#define BIT_GET_STD_L1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_STD_L1_V1_8821C) & BIT_MASK_STD_L1_V1_8821C) +#define BIT_SET_STD_L1_V1_8821C(x, v) \ + (BIT_CLEAR_STD_L1_V1_8821C(x) | BIT_STD_L1_V1_8821C(v)) #define BIT_SYSON_DBG_PAD_E2_8821C BIT(11) #define BIT_SYSON_LED_PAD_E2_8821C BIT(10) @@ -582,56 +865,101 @@ #define BIT_SHIFT_SYSON_SPS0WWV_WT_8821C 4 #define BIT_MASK_SYSON_SPS0WWV_WT_8821C 0x3 -#define BIT_SYSON_SPS0WWV_WT_8821C(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8821C) << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) -#define BIT_GET_SYSON_SPS0WWV_WT_8821C(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) & BIT_MASK_SYSON_SPS0WWV_WT_8821C) - - +#define BIT_SYSON_SPS0WWV_WT_8821C(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8821C) \ + << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) +#define BITS_SYSON_SPS0WWV_WT_8821C \ + (BIT_MASK_SYSON_SPS0WWV_WT_8821C << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) +#define BIT_CLEAR_SYSON_SPS0WWV_WT_8821C(x) \ + ((x) & (~BITS_SYSON_SPS0WWV_WT_8821C)) +#define BIT_GET_SYSON_SPS0WWV_WT_8821C(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) & \ + BIT_MASK_SYSON_SPS0WWV_WT_8821C) +#define BIT_SET_SYSON_SPS0WWV_WT_8821C(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT_8821C(x) | BIT_SYSON_SPS0WWV_WT_8821C(v)) #define BIT_SHIFT_SYSON_SPS0LDO_WT_8821C 2 #define BIT_MASK_SYSON_SPS0LDO_WT_8821C 0x3 -#define BIT_SYSON_SPS0LDO_WT_8821C(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) -#define BIT_GET_SYSON_SPS0LDO_WT_8821C(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) - - +#define BIT_SYSON_SPS0LDO_WT_8821C(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) \ + << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) +#define BITS_SYSON_SPS0LDO_WT_8821C \ + (BIT_MASK_SYSON_SPS0LDO_WT_8821C << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) +#define BIT_CLEAR_SYSON_SPS0LDO_WT_8821C(x) \ + ((x) & (~BITS_SYSON_SPS0LDO_WT_8821C)) +#define BIT_GET_SYSON_SPS0LDO_WT_8821C(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) & \ + BIT_MASK_SYSON_SPS0LDO_WT_8821C) +#define BIT_SET_SYSON_SPS0LDO_WT_8821C(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT_8821C(x) | BIT_SYSON_SPS0LDO_WT_8821C(v)) #define BIT_SHIFT_SYSON_RCLK_SCALE_8821C 0 #define BIT_MASK_SYSON_RCLK_SCALE_8821C 0x3 -#define BIT_SYSON_RCLK_SCALE_8821C(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8821C) << BIT_SHIFT_SYSON_RCLK_SCALE_8821C) -#define BIT_GET_SYSON_RCLK_SCALE_8821C(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8821C) & BIT_MASK_SYSON_RCLK_SCALE_8821C) - - +#define BIT_SYSON_RCLK_SCALE_8821C(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE_8821C) \ + << BIT_SHIFT_SYSON_RCLK_SCALE_8821C) +#define BITS_SYSON_RCLK_SCALE_8821C \ + (BIT_MASK_SYSON_RCLK_SCALE_8821C << BIT_SHIFT_SYSON_RCLK_SCALE_8821C) +#define BIT_CLEAR_SYSON_RCLK_SCALE_8821C(x) \ + ((x) & (~BITS_SYSON_RCLK_SCALE_8821C)) +#define BIT_GET_SYSON_RCLK_SCALE_8821C(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8821C) & \ + BIT_MASK_SYSON_RCLK_SCALE_8821C) +#define BIT_SET_SYSON_RCLK_SCALE_8821C(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE_8821C(x) | BIT_SYSON_RCLK_SCALE_8821C(v)) /* 2 REG_CAL_TIMER_8821C */ #define BIT_SHIFT_MATCH_CNT_8821C 8 #define BIT_MASK_MATCH_CNT_8821C 0xff -#define BIT_MATCH_CNT_8821C(x) (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C) -#define BIT_GET_MATCH_CNT_8821C(x) (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) - - +#define BIT_MATCH_CNT_8821C(x) \ + (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C) +#define BITS_MATCH_CNT_8821C \ + (BIT_MASK_MATCH_CNT_8821C << BIT_SHIFT_MATCH_CNT_8821C) +#define BIT_CLEAR_MATCH_CNT_8821C(x) ((x) & (~BITS_MATCH_CNT_8821C)) +#define BIT_GET_MATCH_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) +#define BIT_SET_MATCH_CNT_8821C(x, v) \ + (BIT_CLEAR_MATCH_CNT_8821C(x) | BIT_MATCH_CNT_8821C(v)) #define BIT_SHIFT_CAL_SCAL_8821C 0 #define BIT_MASK_CAL_SCAL_8821C 0xff -#define BIT_CAL_SCAL_8821C(x) (((x) & BIT_MASK_CAL_SCAL_8821C) << BIT_SHIFT_CAL_SCAL_8821C) -#define BIT_GET_CAL_SCAL_8821C(x) (((x) >> BIT_SHIFT_CAL_SCAL_8821C) & BIT_MASK_CAL_SCAL_8821C) - - +#define BIT_CAL_SCAL_8821C(x) \ + (((x) & BIT_MASK_CAL_SCAL_8821C) << BIT_SHIFT_CAL_SCAL_8821C) +#define BITS_CAL_SCAL_8821C \ + (BIT_MASK_CAL_SCAL_8821C << BIT_SHIFT_CAL_SCAL_8821C) +#define BIT_CLEAR_CAL_SCAL_8821C(x) ((x) & (~BITS_CAL_SCAL_8821C)) +#define BIT_GET_CAL_SCAL_8821C(x) \ + (((x) >> BIT_SHIFT_CAL_SCAL_8821C) & BIT_MASK_CAL_SCAL_8821C) +#define BIT_SET_CAL_SCAL_8821C(x, v) \ + (BIT_CLEAR_CAL_SCAL_8821C(x) | BIT_CAL_SCAL_8821C(v)) /* 2 REG_ACLK_MON_8821C */ #define BIT_SHIFT_RCLK_MON_8821C 5 #define BIT_MASK_RCLK_MON_8821C 0x7ff -#define BIT_RCLK_MON_8821C(x) (((x) & BIT_MASK_RCLK_MON_8821C) << BIT_SHIFT_RCLK_MON_8821C) -#define BIT_GET_RCLK_MON_8821C(x) (((x) >> BIT_SHIFT_RCLK_MON_8821C) & BIT_MASK_RCLK_MON_8821C) - +#define BIT_RCLK_MON_8821C(x) \ + (((x) & BIT_MASK_RCLK_MON_8821C) << BIT_SHIFT_RCLK_MON_8821C) +#define BITS_RCLK_MON_8821C \ + (BIT_MASK_RCLK_MON_8821C << BIT_SHIFT_RCLK_MON_8821C) +#define BIT_CLEAR_RCLK_MON_8821C(x) ((x) & (~BITS_RCLK_MON_8821C)) +#define BIT_GET_RCLK_MON_8821C(x) \ + (((x) >> BIT_SHIFT_RCLK_MON_8821C) & BIT_MASK_RCLK_MON_8821C) +#define BIT_SET_RCLK_MON_8821C(x, v) \ + (BIT_CLEAR_RCLK_MON_8821C(x) | BIT_RCLK_MON_8821C(v)) #define BIT_CAL_EN_8821C BIT(4) #define BIT_SHIFT_DPSTU_8821C 2 #define BIT_MASK_DPSTU_8821C 0x3 -#define BIT_DPSTU_8821C(x) (((x) & BIT_MASK_DPSTU_8821C) << BIT_SHIFT_DPSTU_8821C) -#define BIT_GET_DPSTU_8821C(x) (((x) >> BIT_SHIFT_DPSTU_8821C) & BIT_MASK_DPSTU_8821C) - +#define BIT_DPSTU_8821C(x) \ + (((x) & BIT_MASK_DPSTU_8821C) << BIT_SHIFT_DPSTU_8821C) +#define BITS_DPSTU_8821C (BIT_MASK_DPSTU_8821C << BIT_SHIFT_DPSTU_8821C) +#define BIT_CLEAR_DPSTU_8821C(x) ((x) & (~BITS_DPSTU_8821C)) +#define BIT_GET_DPSTU_8821C(x) \ + (((x) >> BIT_SHIFT_DPSTU_8821C) & BIT_MASK_DPSTU_8821C) +#define BIT_SET_DPSTU_8821C(x, v) \ + (BIT_CLEAR_DPSTU_8821C(x) | BIT_DPSTU_8821C(v)) #define BIT_SUS_16X_8821C BIT(1) @@ -649,9 +977,14 @@ #define BIT_SHIFT_BTMODE_8821C 6 #define BIT_MASK_BTMODE_8821C 0x3 -#define BIT_BTMODE_8821C(x) (((x) & BIT_MASK_BTMODE_8821C) << BIT_SHIFT_BTMODE_8821C) -#define BIT_GET_BTMODE_8821C(x) (((x) >> BIT_SHIFT_BTMODE_8821C) & BIT_MASK_BTMODE_8821C) - +#define BIT_BTMODE_8821C(x) \ + (((x) & BIT_MASK_BTMODE_8821C) << BIT_SHIFT_BTMODE_8821C) +#define BITS_BTMODE_8821C (BIT_MASK_BTMODE_8821C << BIT_SHIFT_BTMODE_8821C) +#define BIT_CLEAR_BTMODE_8821C(x) ((x) & (~BITS_BTMODE_8821C)) +#define BIT_GET_BTMODE_8821C(x) \ + (((x) >> BIT_SHIFT_BTMODE_8821C) & BIT_MASK_BTMODE_8821C) +#define BIT_SET_BTMODE_8821C(x, v) \ + (BIT_CLEAR_BTMODE_8821C(x) | BIT_BTMODE_8821C(v)) #define BIT_ENBT_8821C BIT(5) #define BIT_EROM_EN_8821C BIT(4) @@ -660,48 +993,89 @@ #define BIT_SHIFT_GPIOSEL_8821C 0 #define BIT_MASK_GPIOSEL_8821C 0x3 -#define BIT_GPIOSEL_8821C(x) (((x) & BIT_MASK_GPIOSEL_8821C) << BIT_SHIFT_GPIOSEL_8821C) -#define BIT_GET_GPIOSEL_8821C(x) (((x) >> BIT_SHIFT_GPIOSEL_8821C) & BIT_MASK_GPIOSEL_8821C) - - +#define BIT_GPIOSEL_8821C(x) \ + (((x) & BIT_MASK_GPIOSEL_8821C) << BIT_SHIFT_GPIOSEL_8821C) +#define BITS_GPIOSEL_8821C (BIT_MASK_GPIOSEL_8821C << BIT_SHIFT_GPIOSEL_8821C) +#define BIT_CLEAR_GPIOSEL_8821C(x) ((x) & (~BITS_GPIOSEL_8821C)) +#define BIT_GET_GPIOSEL_8821C(x) \ + (((x) >> BIT_SHIFT_GPIOSEL_8821C) & BIT_MASK_GPIOSEL_8821C) +#define BIT_SET_GPIOSEL_8821C(x, v) \ + (BIT_CLEAR_GPIOSEL_8821C(x) | BIT_GPIOSEL_8821C(v)) /* 2 REG_GPIO_PIN_CTRL_8821C */ #define BIT_SHIFT_GPIO_MOD_7_TO_0_8821C 24 #define BIT_MASK_GPIO_MOD_7_TO_0_8821C 0xff -#define BIT_GPIO_MOD_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8821C) << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) -#define BIT_GET_GPIO_MOD_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) & BIT_MASK_GPIO_MOD_7_TO_0_8821C) - - +#define BIT_GPIO_MOD_7_TO_0_8821C(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8821C) \ + << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) +#define BITS_GPIO_MOD_7_TO_0_8821C \ + (BIT_MASK_GPIO_MOD_7_TO_0_8821C << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) +#define BIT_CLEAR_GPIO_MOD_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8821C)) +#define BIT_GET_GPIO_MOD_7_TO_0_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) & \ + BIT_MASK_GPIO_MOD_7_TO_0_8821C) +#define BIT_SET_GPIO_MOD_7_TO_0_8821C(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0_8821C(x) | BIT_GPIO_MOD_7_TO_0_8821C(v)) #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C 16 #define BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C 0xff -#define BIT_GPIO_IO_SEL_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) -#define BIT_GET_GPIO_IO_SEL_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) - - +#define BIT_GPIO_IO_SEL_7_TO_0_8821C(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) +#define BITS_GPIO_IO_SEL_7_TO_0_8821C \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8821C(x) \ + ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8821C)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) & \ + BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) +#define BIT_SET_GPIO_IO_SEL_7_TO_0_8821C(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8821C(x) | \ + BIT_GPIO_IO_SEL_7_TO_0_8821C(v)) #define BIT_SHIFT_GPIO_OUT_7_TO_0_8821C 8 #define BIT_MASK_GPIO_OUT_7_TO_0_8821C 0xff -#define BIT_GPIO_OUT_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) -#define BIT_GET_GPIO_OUT_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) - - +#define BIT_GPIO_OUT_7_TO_0_8821C(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) \ + << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) +#define BITS_GPIO_OUT_7_TO_0_8821C \ + (BIT_MASK_GPIO_OUT_7_TO_0_8821C << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) +#define BIT_CLEAR_GPIO_OUT_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8821C)) +#define BIT_GET_GPIO_OUT_7_TO_0_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) & \ + BIT_MASK_GPIO_OUT_7_TO_0_8821C) +#define BIT_SET_GPIO_OUT_7_TO_0_8821C(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0_8821C(x) | BIT_GPIO_OUT_7_TO_0_8821C(v)) #define BIT_SHIFT_GPIO_IN_7_TO_0_8821C 0 #define BIT_MASK_GPIO_IN_7_TO_0_8821C 0xff -#define BIT_GPIO_IN_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8821C) << BIT_SHIFT_GPIO_IN_7_TO_0_8821C) -#define BIT_GET_GPIO_IN_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8821C) & BIT_MASK_GPIO_IN_7_TO_0_8821C) - - +#define BIT_GPIO_IN_7_TO_0_8821C(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0_8821C) \ + << BIT_SHIFT_GPIO_IN_7_TO_0_8821C) +#define BITS_GPIO_IN_7_TO_0_8821C \ + (BIT_MASK_GPIO_IN_7_TO_0_8821C << BIT_SHIFT_GPIO_IN_7_TO_0_8821C) +#define BIT_CLEAR_GPIO_IN_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8821C)) +#define BIT_GET_GPIO_IN_7_TO_0_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8821C) & \ + BIT_MASK_GPIO_IN_7_TO_0_8821C) +#define BIT_SET_GPIO_IN_7_TO_0_8821C(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0_8821C(x) | BIT_GPIO_IN_7_TO_0_8821C(v)) /* 2 REG_GPIO_INTM_8821C */ #define BIT_SHIFT_MUXDBG_SEL_8821C 30 #define BIT_MASK_MUXDBG_SEL_8821C 0x3 -#define BIT_MUXDBG_SEL_8821C(x) (((x) & BIT_MASK_MUXDBG_SEL_8821C) << BIT_SHIFT_MUXDBG_SEL_8821C) -#define BIT_GET_MUXDBG_SEL_8821C(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8821C) & BIT_MASK_MUXDBG_SEL_8821C) - +#define BIT_MUXDBG_SEL_8821C(x) \ + (((x) & BIT_MASK_MUXDBG_SEL_8821C) << BIT_SHIFT_MUXDBG_SEL_8821C) +#define BITS_MUXDBG_SEL_8821C \ + (BIT_MASK_MUXDBG_SEL_8821C << BIT_SHIFT_MUXDBG_SEL_8821C) +#define BIT_CLEAR_MUXDBG_SEL_8821C(x) ((x) & (~BITS_MUXDBG_SEL_8821C)) +#define BIT_GET_MUXDBG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL_8821C) & BIT_MASK_MUXDBG_SEL_8821C) +#define BIT_SET_MUXDBG_SEL_8821C(x, v) \ + (BIT_CLEAR_MUXDBG_SEL_8821C(x) | BIT_MUXDBG_SEL_8821C(v)) #define BIT_EXTWOL_SEL_8821C BIT(17) #define BIT_EXTWOL_EN_8821C BIT(16) @@ -732,16 +1106,20 @@ #define BIT_DPDT_WLBT_SEL_8821C BIT(24) #define BIT_DPDT_SEL_EN_8821C BIT(23) #define BIT_GPIO13_14_WL_CTRL_EN_8821C BIT(22) -#define BIT_GPIO13_14_WL_CTRL_EN_8821C BIT(22) #define BIT_LED2DIS_8821C BIT(21) #define BIT_LED2PL_8821C BIT(20) #define BIT_LED2SV_8821C BIT(19) #define BIT_SHIFT_LED2CM_8821C 16 #define BIT_MASK_LED2CM_8821C 0x7 -#define BIT_LED2CM_8821C(x) (((x) & BIT_MASK_LED2CM_8821C) << BIT_SHIFT_LED2CM_8821C) -#define BIT_GET_LED2CM_8821C(x) (((x) >> BIT_SHIFT_LED2CM_8821C) & BIT_MASK_LED2CM_8821C) - +#define BIT_LED2CM_8821C(x) \ + (((x) & BIT_MASK_LED2CM_8821C) << BIT_SHIFT_LED2CM_8821C) +#define BITS_LED2CM_8821C (BIT_MASK_LED2CM_8821C << BIT_SHIFT_LED2CM_8821C) +#define BIT_CLEAR_LED2CM_8821C(x) ((x) & (~BITS_LED2CM_8821C)) +#define BIT_GET_LED2CM_8821C(x) \ + (((x) >> BIT_SHIFT_LED2CM_8821C) & BIT_MASK_LED2CM_8821C) +#define BIT_SET_LED2CM_8821C(x, v) \ + (BIT_CLEAR_LED2CM_8821C(x) | BIT_LED2CM_8821C(v)) #define BIT_LED1DIS_8821C BIT(15) #define BIT_LED1PL_8821C BIT(12) @@ -749,27 +1127,45 @@ #define BIT_SHIFT_LED1CM_8821C 8 #define BIT_MASK_LED1CM_8821C 0x7 -#define BIT_LED1CM_8821C(x) (((x) & BIT_MASK_LED1CM_8821C) << BIT_SHIFT_LED1CM_8821C) -#define BIT_GET_LED1CM_8821C(x) (((x) >> BIT_SHIFT_LED1CM_8821C) & BIT_MASK_LED1CM_8821C) - +#define BIT_LED1CM_8821C(x) \ + (((x) & BIT_MASK_LED1CM_8821C) << BIT_SHIFT_LED1CM_8821C) +#define BITS_LED1CM_8821C (BIT_MASK_LED1CM_8821C << BIT_SHIFT_LED1CM_8821C) +#define BIT_CLEAR_LED1CM_8821C(x) ((x) & (~BITS_LED1CM_8821C)) +#define BIT_GET_LED1CM_8821C(x) \ + (((x) >> BIT_SHIFT_LED1CM_8821C) & BIT_MASK_LED1CM_8821C) +#define BIT_SET_LED1CM_8821C(x, v) \ + (BIT_CLEAR_LED1CM_8821C(x) | BIT_LED1CM_8821C(v)) #define BIT_LED0DIS_8821C BIT(7) #define BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C 5 #define BIT_MASK_AFE_LDO_SWR_CHECK_8821C 0x3 -#define BIT_AFE_LDO_SWR_CHECK_8821C(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) -#define BIT_GET_AFE_LDO_SWR_CHECK_8821C(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) - +#define BIT_AFE_LDO_SWR_CHECK_8821C(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) \ + << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) +#define BITS_AFE_LDO_SWR_CHECK_8821C \ + (BIT_MASK_AFE_LDO_SWR_CHECK_8821C << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8821C(x) \ + ((x) & (~BITS_AFE_LDO_SWR_CHECK_8821C)) +#define BIT_GET_AFE_LDO_SWR_CHECK_8821C(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) & \ + BIT_MASK_AFE_LDO_SWR_CHECK_8821C) +#define BIT_SET_AFE_LDO_SWR_CHECK_8821C(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK_8821C(x) | BIT_AFE_LDO_SWR_CHECK_8821C(v)) #define BIT_LED0PL_8821C BIT(4) #define BIT_LED0SV_8821C BIT(3) #define BIT_SHIFT_LED0CM_8821C 0 #define BIT_MASK_LED0CM_8821C 0x7 -#define BIT_LED0CM_8821C(x) (((x) & BIT_MASK_LED0CM_8821C) << BIT_SHIFT_LED0CM_8821C) -#define BIT_GET_LED0CM_8821C(x) (((x) >> BIT_SHIFT_LED0CM_8821C) & BIT_MASK_LED0CM_8821C) - - +#define BIT_LED0CM_8821C(x) \ + (((x) & BIT_MASK_LED0CM_8821C) << BIT_SHIFT_LED0CM_8821C) +#define BITS_LED0CM_8821C (BIT_MASK_LED0CM_8821C << BIT_SHIFT_LED0CM_8821C) +#define BIT_CLEAR_LED0CM_8821C(x) ((x) & (~BITS_LED0CM_8821C)) +#define BIT_GET_LED0CM_8821C(x) \ + (((x) >> BIT_SHIFT_LED0CM_8821C) & BIT_MASK_LED0CM_8821C) +#define BIT_SET_LED0CM_8821C(x, v) \ + (BIT_CLEAR_LED0CM_8821C(x) | BIT_LED0CM_8821C(v)) /* 2 REG_FSIMR_8821C */ #define BIT_FS_PDNINT_EN_8821C BIT(31) @@ -851,7 +1247,7 @@ #define BIT_GPIO5_INT_EN_8821C BIT(21) #define BIT_GPIO4_INT_EN_8821C BIT(20) #define BIT_GPIO3_INT_EN_8821C BIT(19) -#define BIT_GPIO2_INT_EN_V1_8821C BIT(16) +#define BIT_GPIO2_INT_EN_V1_8821C BIT(18) #define BIT_GPIO1_INT_EN_8821C BIT(17) #define BIT_GPIO0_INT_EN_8821C BIT(16) #define BIT_PDNINT_EN_8821C BIT(7) @@ -873,7 +1269,7 @@ #define BIT_GPIO5_INT_8821C BIT(21) #define BIT_GPIO4_INT_8821C BIT(20) #define BIT_GPIO3_INT_8821C BIT(19) -#define BIT_GPIO2_INT_V1_8821C BIT(16) +#define BIT_GPIO2_INT_V1_8821C BIT(18) #define BIT_GPIO1_INT_8821C BIT(17) #define BIT_GPIO0_INT_8821C BIT(16) #define BIT_PDNINT_8821C BIT(7) @@ -885,31 +1281,64 @@ #define BIT_SHIFT_GPIO_MOD_15_TO_8_8821C 24 #define BIT_MASK_GPIO_MOD_15_TO_8_8821C 0xff -#define BIT_GPIO_MOD_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8821C) << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) -#define BIT_GET_GPIO_MOD_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) & BIT_MASK_GPIO_MOD_15_TO_8_8821C) - - +#define BIT_GPIO_MOD_15_TO_8_8821C(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8821C) \ + << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) +#define BITS_GPIO_MOD_15_TO_8_8821C \ + (BIT_MASK_GPIO_MOD_15_TO_8_8821C << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) +#define BIT_CLEAR_GPIO_MOD_15_TO_8_8821C(x) \ + ((x) & (~BITS_GPIO_MOD_15_TO_8_8821C)) +#define BIT_GET_GPIO_MOD_15_TO_8_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) & \ + BIT_MASK_GPIO_MOD_15_TO_8_8821C) +#define BIT_SET_GPIO_MOD_15_TO_8_8821C(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8_8821C(x) | BIT_GPIO_MOD_15_TO_8_8821C(v)) #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C 16 #define BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C 0xff -#define BIT_GPIO_IO_SEL_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) -#define BIT_GET_GPIO_IO_SEL_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) - - +#define BIT_GPIO_IO_SEL_15_TO_8_8821C(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) +#define BITS_GPIO_IO_SEL_15_TO_8_8821C \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8821C(x) \ + ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8821C)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) & \ + BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) +#define BIT_SET_GPIO_IO_SEL_15_TO_8_8821C(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8821C(x) | \ + BIT_GPIO_IO_SEL_15_TO_8_8821C(v)) #define BIT_SHIFT_GPIO_OUT_15_TO_8_8821C 8 #define BIT_MASK_GPIO_OUT_15_TO_8_8821C 0xff -#define BIT_GPIO_OUT_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) -#define BIT_GET_GPIO_OUT_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) - - +#define BIT_GPIO_OUT_15_TO_8_8821C(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) \ + << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) +#define BITS_GPIO_OUT_15_TO_8_8821C \ + (BIT_MASK_GPIO_OUT_15_TO_8_8821C << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) +#define BIT_CLEAR_GPIO_OUT_15_TO_8_8821C(x) \ + ((x) & (~BITS_GPIO_OUT_15_TO_8_8821C)) +#define BIT_GET_GPIO_OUT_15_TO_8_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) & \ + BIT_MASK_GPIO_OUT_15_TO_8_8821C) +#define BIT_SET_GPIO_OUT_15_TO_8_8821C(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8_8821C(x) | BIT_GPIO_OUT_15_TO_8_8821C(v)) #define BIT_SHIFT_GPIO_IN_15_TO_8_8821C 0 #define BIT_MASK_GPIO_IN_15_TO_8_8821C 0xff -#define BIT_GPIO_IN_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8821C) << BIT_SHIFT_GPIO_IN_15_TO_8_8821C) -#define BIT_GET_GPIO_IN_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8821C) & BIT_MASK_GPIO_IN_15_TO_8_8821C) - - +#define BIT_GPIO_IN_15_TO_8_8821C(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8_8821C) \ + << BIT_SHIFT_GPIO_IN_15_TO_8_8821C) +#define BITS_GPIO_IN_15_TO_8_8821C \ + (BIT_MASK_GPIO_IN_15_TO_8_8821C << BIT_SHIFT_GPIO_IN_15_TO_8_8821C) +#define BIT_CLEAR_GPIO_IN_15_TO_8_8821C(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8821C)) +#define BIT_GET_GPIO_IN_15_TO_8_8821C(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8821C) & \ + BIT_MASK_GPIO_IN_15_TO_8_8821C) +#define BIT_SET_GPIO_IN_15_TO_8_8821C(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8_8821C(x) | BIT_GPIO_IN_15_TO_8_8821C(v)) /* 2 REG_PAD_CTRL1_8821C */ #define BIT_PAPE_WLBT_SEL_8821C BIT(29) @@ -926,9 +1355,15 @@ #define BIT_SHIFT_BTGP_GPIO_SL_8821C 16 #define BIT_MASK_BTGP_GPIO_SL_8821C 0x3 -#define BIT_BTGP_GPIO_SL_8821C(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8821C) << BIT_SHIFT_BTGP_GPIO_SL_8821C) -#define BIT_GET_BTGP_GPIO_SL_8821C(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8821C) & BIT_MASK_BTGP_GPIO_SL_8821C) - +#define BIT_BTGP_GPIO_SL_8821C(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL_8821C) << BIT_SHIFT_BTGP_GPIO_SL_8821C) +#define BITS_BTGP_GPIO_SL_8821C \ + (BIT_MASK_BTGP_GPIO_SL_8821C << BIT_SHIFT_BTGP_GPIO_SL_8821C) +#define BIT_CLEAR_BTGP_GPIO_SL_8821C(x) ((x) & (~BITS_BTGP_GPIO_SL_8821C)) +#define BIT_GET_BTGP_GPIO_SL_8821C(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8821C) & BIT_MASK_BTGP_GPIO_SL_8821C) +#define BIT_SET_BTGP_GPIO_SL_8821C(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL_8821C(x) | BIT_BTGP_GPIO_SL_8821C(v)) #define BIT_PAD_SDIO_SR_8821C BIT(14) #define BIT_GPIO14_OUTPUT_PL_8821C BIT(13) @@ -979,10 +1414,15 @@ #define BIT_SHIFT_WLCLK_PHASE_8821C 0 #define BIT_MASK_WLCLK_PHASE_8821C 0x1f -#define BIT_WLCLK_PHASE_8821C(x) (((x) & BIT_MASK_WLCLK_PHASE_8821C) << BIT_SHIFT_WLCLK_PHASE_8821C) -#define BIT_GET_WLCLK_PHASE_8821C(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8821C) & BIT_MASK_WLCLK_PHASE_8821C) - - +#define BIT_WLCLK_PHASE_8821C(x) \ + (((x) & BIT_MASK_WLCLK_PHASE_8821C) << BIT_SHIFT_WLCLK_PHASE_8821C) +#define BITS_WLCLK_PHASE_8821C \ + (BIT_MASK_WLCLK_PHASE_8821C << BIT_SHIFT_WLCLK_PHASE_8821C) +#define BIT_CLEAR_WLCLK_PHASE_8821C(x) ((x) & (~BITS_WLCLK_PHASE_8821C)) +#define BIT_GET_WLCLK_PHASE_8821C(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE_8821C) & BIT_MASK_WLCLK_PHASE_8821C) +#define BIT_SET_WLCLK_PHASE_8821C(x, v) \ + (BIT_CLEAR_WLCLK_PHASE_8821C(x) | BIT_WLCLK_PHASE_8821C(v)) /* 2 REG_SYS_SDIO_CTRL_8821C */ #define BIT_DBG_GNT_WL_BT_8821C BIT(27) @@ -1003,10 +1443,17 @@ #define BIT_SHIFT_TSFT_SEL_8821C 29 #define BIT_MASK_TSFT_SEL_8821C 0x7 -#define BIT_TSFT_SEL_8821C(x) (((x) & BIT_MASK_TSFT_SEL_8821C) << BIT_SHIFT_TSFT_SEL_8821C) -#define BIT_GET_TSFT_SEL_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_8821C) & BIT_MASK_TSFT_SEL_8821C) - - +#define BIT_TSFT_SEL_8821C(x) \ + (((x) & BIT_MASK_TSFT_SEL_8821C) << BIT_SHIFT_TSFT_SEL_8821C) +#define BITS_TSFT_SEL_8821C \ + (BIT_MASK_TSFT_SEL_8821C << BIT_SHIFT_TSFT_SEL_8821C) +#define BIT_CLEAR_TSFT_SEL_8821C(x) ((x) & (~BITS_TSFT_SEL_8821C)) +#define BIT_GET_TSFT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_8821C) & BIT_MASK_TSFT_SEL_8821C) +#define BIT_SET_TSFT_SEL_8821C(x, v) \ + (BIT_CLEAR_TSFT_SEL_8821C(x) | BIT_TSFT_SEL_8821C(v)) + +#define BIT_SDIO_PAD_E5_8821C BIT(18) #define BIT_USB_HOST_PWR_OFF_EN_8821C BIT(12) #define BIT_SYM_LPS_BLOCK_EN_8821C BIT(11) #define BIT_USB_LPM_ACT_EN_8821C BIT(10) @@ -1015,9 +1462,15 @@ #define BIT_SHIFT_SDIO_PAD_E_8821C 5 #define BIT_MASK_SDIO_PAD_E_8821C 0x7 -#define BIT_SDIO_PAD_E_8821C(x) (((x) & BIT_MASK_SDIO_PAD_E_8821C) << BIT_SHIFT_SDIO_PAD_E_8821C) -#define BIT_GET_SDIO_PAD_E_8821C(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8821C) & BIT_MASK_SDIO_PAD_E_8821C) - +#define BIT_SDIO_PAD_E_8821C(x) \ + (((x) & BIT_MASK_SDIO_PAD_E_8821C) << BIT_SHIFT_SDIO_PAD_E_8821C) +#define BITS_SDIO_PAD_E_8821C \ + (BIT_MASK_SDIO_PAD_E_8821C << BIT_SHIFT_SDIO_PAD_E_8821C) +#define BIT_CLEAR_SDIO_PAD_E_8821C(x) ((x) & (~BITS_SDIO_PAD_E_8821C)) +#define BIT_GET_SDIO_PAD_E_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E_8821C) & BIT_MASK_SDIO_PAD_E_8821C) +#define BIT_SET_SDIO_PAD_E_8821C(x, v) \ + (BIT_CLEAR_SDIO_PAD_E_8821C(x) | BIT_SDIO_PAD_E_8821C(v)) #define BIT_USB_LPPLL_EN_8821C BIT(4) #define BIT_ROP_SW15_8821C BIT(2) @@ -1032,44 +1485,93 @@ #define BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C 21 #define BIT_MASK_AUTO_ZCD_IN_CODE_8821C 0x1f -#define BIT_AUTO_ZCD_IN_CODE_8821C(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C) << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) -#define BIT_GET_AUTO_ZCD_IN_CODE_8821C(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C) - - +#define BIT_AUTO_ZCD_IN_CODE_8821C(x) \ + (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C) \ + << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) +#define BITS_AUTO_ZCD_IN_CODE_8821C \ + (BIT_MASK_AUTO_ZCD_IN_CODE_8821C << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) +#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8821C(x) \ + ((x) & (~BITS_AUTO_ZCD_IN_CODE_8821C)) +#define BIT_GET_AUTO_ZCD_IN_CODE_8821C(x) \ + (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) & \ + BIT_MASK_AUTO_ZCD_IN_CODE_8821C) +#define BIT_SET_AUTO_ZCD_IN_CODE_8821C(x, v) \ + (BIT_CLEAR_AUTO_ZCD_IN_CODE_8821C(x) | BIT_AUTO_ZCD_IN_CODE_8821C(v)) #define BIT_SHIFT_ZCD_CODE_IN_L_8821C 16 #define BIT_MASK_ZCD_CODE_IN_L_8821C 0x1f -#define BIT_ZCD_CODE_IN_L_8821C(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8821C) << BIT_SHIFT_ZCD_CODE_IN_L_8821C) -#define BIT_GET_ZCD_CODE_IN_L_8821C(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8821C) & BIT_MASK_ZCD_CODE_IN_L_8821C) - - +#define BIT_ZCD_CODE_IN_L_8821C(x) \ + (((x) & BIT_MASK_ZCD_CODE_IN_L_8821C) << BIT_SHIFT_ZCD_CODE_IN_L_8821C) +#define BITS_ZCD_CODE_IN_L_8821C \ + (BIT_MASK_ZCD_CODE_IN_L_8821C << BIT_SHIFT_ZCD_CODE_IN_L_8821C) +#define BIT_CLEAR_ZCD_CODE_IN_L_8821C(x) ((x) & (~BITS_ZCD_CODE_IN_L_8821C)) +#define BIT_GET_ZCD_CODE_IN_L_8821C(x) \ + (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8821C) & BIT_MASK_ZCD_CODE_IN_L_8821C) +#define BIT_SET_ZCD_CODE_IN_L_8821C(x, v) \ + (BIT_CLEAR_ZCD_CODE_IN_L_8821C(x) | BIT_ZCD_CODE_IN_L_8821C(v)) #define BIT_SHIFT_LDO_HV5_DUMMY_8821C 14 #define BIT_MASK_LDO_HV5_DUMMY_8821C 0x3 -#define BIT_LDO_HV5_DUMMY_8821C(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8821C) << BIT_SHIFT_LDO_HV5_DUMMY_8821C) -#define BIT_GET_LDO_HV5_DUMMY_8821C(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8821C) & BIT_MASK_LDO_HV5_DUMMY_8821C) - - +#define BIT_LDO_HV5_DUMMY_8821C(x) \ + (((x) & BIT_MASK_LDO_HV5_DUMMY_8821C) << BIT_SHIFT_LDO_HV5_DUMMY_8821C) +#define BITS_LDO_HV5_DUMMY_8821C \ + (BIT_MASK_LDO_HV5_DUMMY_8821C << BIT_SHIFT_LDO_HV5_DUMMY_8821C) +#define BIT_CLEAR_LDO_HV5_DUMMY_8821C(x) ((x) & (~BITS_LDO_HV5_DUMMY_8821C)) +#define BIT_GET_LDO_HV5_DUMMY_8821C(x) \ + (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8821C) & BIT_MASK_LDO_HV5_DUMMY_8821C) +#define BIT_SET_LDO_HV5_DUMMY_8821C(x, v) \ + (BIT_CLEAR_LDO_HV5_DUMMY_8821C(x) | BIT_LDO_HV5_DUMMY_8821C(v)) #define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C 12 #define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C 0x3 -#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) -#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) - - +#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) \ + (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) +#define BITS_REG_VTUNE33_BIT0_TO_BIT1_8821C \ + (BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) +#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) \ + ((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1_8821C)) +#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) \ + (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) & \ + BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) +#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x, v) \ + (BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) | \ + BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(v)) #define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C 10 #define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C 0x3 -#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) -#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) - - +#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) \ + (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) +#define BITS_REG_STANDBY33_BIT0_TO_BIT1_8821C \ + (BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) +#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) \ + ((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1_8821C)) +#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) \ + (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) & \ + BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) +#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x, v) \ + (BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) | \ + BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(v)) #define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C 8 #define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C 0x3 -#define BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) -#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) - +#define BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(x) \ + (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) \ + << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) +#define BITS_REG_LOAD33_BIT0_TO_BIT1_8821C \ + (BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C \ + << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) +#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8821C(x) \ + ((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1_8821C)) +#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8821C(x) \ + (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) & \ + BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) +#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1_8821C(x, v) \ + (BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8821C(x) | \ + BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(v)) #define BIT_REG_BYPASS_L_8821C BIT(7) #define BIT_REG_LDOF_L_8821C BIT(6) @@ -1078,9 +1580,14 @@ #define BIT_SHIFT_CFC_L_8821C 1 #define BIT_MASK_CFC_L_8821C 0x3 -#define BIT_CFC_L_8821C(x) (((x) & BIT_MASK_CFC_L_8821C) << BIT_SHIFT_CFC_L_8821C) -#define BIT_GET_CFC_L_8821C(x) (((x) >> BIT_SHIFT_CFC_L_8821C) & BIT_MASK_CFC_L_8821C) - +#define BIT_CFC_L_8821C(x) \ + (((x) & BIT_MASK_CFC_L_8821C) << BIT_SHIFT_CFC_L_8821C) +#define BITS_CFC_L_8821C (BIT_MASK_CFC_L_8821C << BIT_SHIFT_CFC_L_8821C) +#define BIT_CLEAR_CFC_L_8821C(x) ((x) & (~BITS_CFC_L_8821C)) +#define BIT_GET_CFC_L_8821C(x) \ + (((x) >> BIT_SHIFT_CFC_L_8821C) & BIT_MASK_CFC_L_8821C) +#define BIT_SET_CFC_L_8821C(x, v) \ + (BIT_CLEAR_CFC_L_8821C(x) | BIT_CFC_L_8821C(v)) #define BIT_REG_TYPE_L_8821C BIT(0) @@ -1089,8 +1596,11 @@ #define BIT_SHIFT_RPWM_8821C 24 #define BIT_MASK_RPWM_8821C 0xff #define BIT_RPWM_8821C(x) (((x) & BIT_MASK_RPWM_8821C) << BIT_SHIFT_RPWM_8821C) -#define BIT_GET_RPWM_8821C(x) (((x) >> BIT_SHIFT_RPWM_8821C) & BIT_MASK_RPWM_8821C) - +#define BITS_RPWM_8821C (BIT_MASK_RPWM_8821C << BIT_SHIFT_RPWM_8821C) +#define BIT_CLEAR_RPWM_8821C(x) ((x) & (~BITS_RPWM_8821C)) +#define BIT_GET_RPWM_8821C(x) \ + (((x) >> BIT_SHIFT_RPWM_8821C) & BIT_MASK_RPWM_8821C) +#define BIT_SET_RPWM_8821C(x, v) (BIT_CLEAR_RPWM_8821C(x) | BIT_RPWM_8821C(v)) #define BIT_ANA_PORT_EN_8821C BIT(22) #define BIT_MAC_PORT_EN_8821C BIT(21) @@ -1099,18 +1609,29 @@ #define BIT_SHIFT_ROM_PGE_8821C 16 #define BIT_MASK_ROM_PGE_8821C 0x7 -#define BIT_ROM_PGE_8821C(x) (((x) & BIT_MASK_ROM_PGE_8821C) << BIT_SHIFT_ROM_PGE_8821C) -#define BIT_GET_ROM_PGE_8821C(x) (((x) >> BIT_SHIFT_ROM_PGE_8821C) & BIT_MASK_ROM_PGE_8821C) - +#define BIT_ROM_PGE_8821C(x) \ + (((x) & BIT_MASK_ROM_PGE_8821C) << BIT_SHIFT_ROM_PGE_8821C) +#define BITS_ROM_PGE_8821C (BIT_MASK_ROM_PGE_8821C << BIT_SHIFT_ROM_PGE_8821C) +#define BIT_CLEAR_ROM_PGE_8821C(x) ((x) & (~BITS_ROM_PGE_8821C)) +#define BIT_GET_ROM_PGE_8821C(x) \ + (((x) >> BIT_SHIFT_ROM_PGE_8821C) & BIT_MASK_ROM_PGE_8821C) +#define BIT_SET_ROM_PGE_8821C(x, v) \ + (BIT_CLEAR_ROM_PGE_8821C(x) | BIT_ROM_PGE_8821C(v)) #define BIT_FW_INIT_RDY_8821C BIT(15) #define BIT_FW_DW_RDY_8821C BIT(14) #define BIT_SHIFT_CPU_CLK_SEL_8821C 12 #define BIT_MASK_CPU_CLK_SEL_8821C 0x3 -#define BIT_CPU_CLK_SEL_8821C(x) (((x) & BIT_MASK_CPU_CLK_SEL_8821C) << BIT_SHIFT_CPU_CLK_SEL_8821C) -#define BIT_GET_CPU_CLK_SEL_8821C(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8821C) & BIT_MASK_CPU_CLK_SEL_8821C) - +#define BIT_CPU_CLK_SEL_8821C(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL_8821C) << BIT_SHIFT_CPU_CLK_SEL_8821C) +#define BITS_CPU_CLK_SEL_8821C \ + (BIT_MASK_CPU_CLK_SEL_8821C << BIT_SHIFT_CPU_CLK_SEL_8821C) +#define BIT_CLEAR_CPU_CLK_SEL_8821C(x) ((x) & (~BITS_CPU_CLK_SEL_8821C)) +#define BIT_GET_CPU_CLK_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL_8821C) & BIT_MASK_CPU_CLK_SEL_8821C) +#define BIT_SET_CPU_CLK_SEL_8821C(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL_8821C(x) | BIT_CPU_CLK_SEL_8821C(v)) #define BIT_CCLK_CHG_MASK_8821C BIT(11) #define BIT_EMEM__TXBUF_CHKSUM_OK_8821C BIT(10) @@ -1127,44 +1648,68 @@ /* 2 REG_MCU_TST_CFG_8821C */ -#define BIT_SHIFT_LBKTST_8821C 0 -#define BIT_MASK_LBKTST_8821C 0xffff -#define BIT_LBKTST_8821C(x) (((x) & BIT_MASK_LBKTST_8821C) << BIT_SHIFT_LBKTST_8821C) -#define BIT_GET_LBKTST_8821C(x) (((x) >> BIT_SHIFT_LBKTST_8821C) & BIT_MASK_LBKTST_8821C) - - +#define BIT_SHIFT_C2H_MSG_8821C 0 +#define BIT_MASK_C2H_MSG_8821C 0xffff +#define BIT_C2H_MSG_8821C(x) \ + (((x) & BIT_MASK_C2H_MSG_8821C) << BIT_SHIFT_C2H_MSG_8821C) +#define BITS_C2H_MSG_8821C (BIT_MASK_C2H_MSG_8821C << BIT_SHIFT_C2H_MSG_8821C) +#define BIT_CLEAR_C2H_MSG_8821C(x) ((x) & (~BITS_C2H_MSG_8821C)) +#define BIT_GET_C2H_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_C2H_MSG_8821C) & BIT_MASK_C2H_MSG_8821C) +#define BIT_SET_C2H_MSG_8821C(x, v) \ + (BIT_CLEAR_C2H_MSG_8821C(x) | BIT_C2H_MSG_8821C(v)) /* 2 REG_HMEBOX_E0_E1_8821C */ #define BIT_SHIFT_HOST_MSG_E1_8821C 16 #define BIT_MASK_HOST_MSG_E1_8821C 0xffff -#define BIT_HOST_MSG_E1_8821C(x) (((x) & BIT_MASK_HOST_MSG_E1_8821C) << BIT_SHIFT_HOST_MSG_E1_8821C) -#define BIT_GET_HOST_MSG_E1_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8821C) & BIT_MASK_HOST_MSG_E1_8821C) - - +#define BIT_HOST_MSG_E1_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_E1_8821C) << BIT_SHIFT_HOST_MSG_E1_8821C) +#define BITS_HOST_MSG_E1_8821C \ + (BIT_MASK_HOST_MSG_E1_8821C << BIT_SHIFT_HOST_MSG_E1_8821C) +#define BIT_CLEAR_HOST_MSG_E1_8821C(x) ((x) & (~BITS_HOST_MSG_E1_8821C)) +#define BIT_GET_HOST_MSG_E1_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1_8821C) & BIT_MASK_HOST_MSG_E1_8821C) +#define BIT_SET_HOST_MSG_E1_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_E1_8821C(x) | BIT_HOST_MSG_E1_8821C(v)) #define BIT_SHIFT_HOST_MSG_E0_8821C 0 #define BIT_MASK_HOST_MSG_E0_8821C 0xffff -#define BIT_HOST_MSG_E0_8821C(x) (((x) & BIT_MASK_HOST_MSG_E0_8821C) << BIT_SHIFT_HOST_MSG_E0_8821C) -#define BIT_GET_HOST_MSG_E0_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8821C) & BIT_MASK_HOST_MSG_E0_8821C) - - +#define BIT_HOST_MSG_E0_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_E0_8821C) << BIT_SHIFT_HOST_MSG_E0_8821C) +#define BITS_HOST_MSG_E0_8821C \ + (BIT_MASK_HOST_MSG_E0_8821C << BIT_SHIFT_HOST_MSG_E0_8821C) +#define BIT_CLEAR_HOST_MSG_E0_8821C(x) ((x) & (~BITS_HOST_MSG_E0_8821C)) +#define BIT_GET_HOST_MSG_E0_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0_8821C) & BIT_MASK_HOST_MSG_E0_8821C) +#define BIT_SET_HOST_MSG_E0_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_E0_8821C(x) | BIT_HOST_MSG_E0_8821C(v)) /* 2 REG_HMEBOX_E2_E3_8821C */ #define BIT_SHIFT_HOST_MSG_E3_8821C 16 #define BIT_MASK_HOST_MSG_E3_8821C 0xffff -#define BIT_HOST_MSG_E3_8821C(x) (((x) & BIT_MASK_HOST_MSG_E3_8821C) << BIT_SHIFT_HOST_MSG_E3_8821C) -#define BIT_GET_HOST_MSG_E3_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8821C) & BIT_MASK_HOST_MSG_E3_8821C) - - +#define BIT_HOST_MSG_E3_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_E3_8821C) << BIT_SHIFT_HOST_MSG_E3_8821C) +#define BITS_HOST_MSG_E3_8821C \ + (BIT_MASK_HOST_MSG_E3_8821C << BIT_SHIFT_HOST_MSG_E3_8821C) +#define BIT_CLEAR_HOST_MSG_E3_8821C(x) ((x) & (~BITS_HOST_MSG_E3_8821C)) +#define BIT_GET_HOST_MSG_E3_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3_8821C) & BIT_MASK_HOST_MSG_E3_8821C) +#define BIT_SET_HOST_MSG_E3_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_E3_8821C(x) | BIT_HOST_MSG_E3_8821C(v)) #define BIT_SHIFT_HOST_MSG_E2_8821C 0 #define BIT_MASK_HOST_MSG_E2_8821C 0xffff -#define BIT_HOST_MSG_E2_8821C(x) (((x) & BIT_MASK_HOST_MSG_E2_8821C) << BIT_SHIFT_HOST_MSG_E2_8821C) -#define BIT_GET_HOST_MSG_E2_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8821C) & BIT_MASK_HOST_MSG_E2_8821C) - - +#define BIT_HOST_MSG_E2_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_E2_8821C) << BIT_SHIFT_HOST_MSG_E2_8821C) +#define BITS_HOST_MSG_E2_8821C \ + (BIT_MASK_HOST_MSG_E2_8821C << BIT_SHIFT_HOST_MSG_E2_8821C) +#define BIT_CLEAR_HOST_MSG_E2_8821C(x) ((x) & (~BITS_HOST_MSG_E2_8821C)) +#define BIT_GET_HOST_MSG_E2_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2_8821C) & BIT_MASK_HOST_MSG_E2_8821C) +#define BIT_SET_HOST_MSG_E2_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_E2_8821C(x) | BIT_HOST_MSG_E2_8821C(v)) /* 2 REG_WLLPS_CTRL_8821C */ #define BIT_WLLPSOP_EABM_8821C BIT(31) @@ -1181,16 +1726,35 @@ #define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C 12 #define BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C 0xf -#define BIT_LPLDH12_VADJ_STEP_DN_8821C(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) -#define BIT_GET_LPLDH12_VADJ_STEP_DN_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) - - +#define BIT_LPLDH12_VADJ_STEP_DN_8821C(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) +#define BITS_LPLDH12_VADJ_STEP_DN_8821C \ + (BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) +#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8821C(x) \ + ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8821C)) +#define BIT_GET_LPLDH12_VADJ_STEP_DN_8821C(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) & \ + BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) +#define BIT_SET_LPLDH12_VADJ_STEP_DN_8821C(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8821C(x) | \ + BIT_LPLDH12_VADJ_STEP_DN_8821C(v)) #define BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C 8 #define BIT_MASK_V15ADJ_L1_STEP_DN_8821C 0x7 -#define BIT_V15ADJ_L1_STEP_DN_8821C(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) -#define BIT_GET_V15ADJ_L1_STEP_DN_8821C(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) - +#define BIT_V15ADJ_L1_STEP_DN_8821C(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) +#define BITS_V15ADJ_L1_STEP_DN_8821C \ + (BIT_MASK_V15ADJ_L1_STEP_DN_8821C << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8821C(x) \ + ((x) & (~BITS_V15ADJ_L1_STEP_DN_8821C)) +#define BIT_GET_V15ADJ_L1_STEP_DN_8821C(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) & \ + BIT_MASK_V15ADJ_L1_STEP_DN_8821C) +#define BIT_SET_V15ADJ_L1_STEP_DN_8821C(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN_8821C(x) | BIT_V15ADJ_L1_STEP_DN_8821C(v)) #define BIT_REGU_32K_CLK_EN_8821C BIT(1) #define BIT_WL_LPS_EN_8821C BIT(0) @@ -1202,119 +1766,198 @@ #define BIT_SHIFT_REF_SEL_8821C 25 #define BIT_MASK_REF_SEL_8821C 0xf -#define BIT_REF_SEL_8821C(x) (((x) & BIT_MASK_REF_SEL_8821C) << BIT_SHIFT_REF_SEL_8821C) -#define BIT_GET_REF_SEL_8821C(x) (((x) >> BIT_SHIFT_REF_SEL_8821C) & BIT_MASK_REF_SEL_8821C) - - +#define BIT_REF_SEL_8821C(x) \ + (((x) & BIT_MASK_REF_SEL_8821C) << BIT_SHIFT_REF_SEL_8821C) +#define BITS_REF_SEL_8821C (BIT_MASK_REF_SEL_8821C << BIT_SHIFT_REF_SEL_8821C) +#define BIT_CLEAR_REF_SEL_8821C(x) ((x) & (~BITS_REF_SEL_8821C)) +#define BIT_GET_REF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_REF_SEL_8821C) & BIT_MASK_REF_SEL_8821C) +#define BIT_SET_REF_SEL_8821C(x, v) \ + (BIT_CLEAR_REF_SEL_8821C(x) | BIT_REF_SEL_8821C(v)) #define BIT_SHIFT_F0F_SDM_8821C 12 #define BIT_MASK_F0F_SDM_8821C 0x1fff -#define BIT_F0F_SDM_8821C(x) (((x) & BIT_MASK_F0F_SDM_8821C) << BIT_SHIFT_F0F_SDM_8821C) -#define BIT_GET_F0F_SDM_8821C(x) (((x) >> BIT_SHIFT_F0F_SDM_8821C) & BIT_MASK_F0F_SDM_8821C) - - +#define BIT_F0F_SDM_8821C(x) \ + (((x) & BIT_MASK_F0F_SDM_8821C) << BIT_SHIFT_F0F_SDM_8821C) +#define BITS_F0F_SDM_8821C (BIT_MASK_F0F_SDM_8821C << BIT_SHIFT_F0F_SDM_8821C) +#define BIT_CLEAR_F0F_SDM_8821C(x) ((x) & (~BITS_F0F_SDM_8821C)) +#define BIT_GET_F0F_SDM_8821C(x) \ + (((x) >> BIT_SHIFT_F0F_SDM_8821C) & BIT_MASK_F0F_SDM_8821C) +#define BIT_SET_F0F_SDM_8821C(x, v) \ + (BIT_CLEAR_F0F_SDM_8821C(x) | BIT_F0F_SDM_8821C(v)) #define BIT_SHIFT_F0N_SDM_8821C 9 #define BIT_MASK_F0N_SDM_8821C 0x7 -#define BIT_F0N_SDM_8821C(x) (((x) & BIT_MASK_F0N_SDM_8821C) << BIT_SHIFT_F0N_SDM_8821C) -#define BIT_GET_F0N_SDM_8821C(x) (((x) >> BIT_SHIFT_F0N_SDM_8821C) & BIT_MASK_F0N_SDM_8821C) - - +#define BIT_F0N_SDM_8821C(x) \ + (((x) & BIT_MASK_F0N_SDM_8821C) << BIT_SHIFT_F0N_SDM_8821C) +#define BITS_F0N_SDM_8821C (BIT_MASK_F0N_SDM_8821C << BIT_SHIFT_F0N_SDM_8821C) +#define BIT_CLEAR_F0N_SDM_8821C(x) ((x) & (~BITS_F0N_SDM_8821C)) +#define BIT_GET_F0N_SDM_8821C(x) \ + (((x) >> BIT_SHIFT_F0N_SDM_8821C) & BIT_MASK_F0N_SDM_8821C) +#define BIT_SET_F0N_SDM_8821C(x, v) \ + (BIT_CLEAR_F0N_SDM_8821C(x) | BIT_F0N_SDM_8821C(v)) #define BIT_SHIFT_DIVN_SDM_8821C 3 #define BIT_MASK_DIVN_SDM_8821C 0x3f -#define BIT_DIVN_SDM_8821C(x) (((x) & BIT_MASK_DIVN_SDM_8821C) << BIT_SHIFT_DIVN_SDM_8821C) -#define BIT_GET_DIVN_SDM_8821C(x) (((x) >> BIT_SHIFT_DIVN_SDM_8821C) & BIT_MASK_DIVN_SDM_8821C) - - +#define BIT_DIVN_SDM_8821C(x) \ + (((x) & BIT_MASK_DIVN_SDM_8821C) << BIT_SHIFT_DIVN_SDM_8821C) +#define BITS_DIVN_SDM_8821C \ + (BIT_MASK_DIVN_SDM_8821C << BIT_SHIFT_DIVN_SDM_8821C) +#define BIT_CLEAR_DIVN_SDM_8821C(x) ((x) & (~BITS_DIVN_SDM_8821C)) +#define BIT_GET_DIVN_SDM_8821C(x) \ + (((x) >> BIT_SHIFT_DIVN_SDM_8821C) & BIT_MASK_DIVN_SDM_8821C) +#define BIT_SET_DIVN_SDM_8821C(x, v) \ + (BIT_CLEAR_DIVN_SDM_8821C(x) | BIT_DIVN_SDM_8821C(v)) /* 2 REG_GPIO_DEBOUNCE_CTRL_8821C */ #define BIT_WLGP_DBC1EN_8821C BIT(15) #define BIT_SHIFT_WLGP_DBC1_8821C 8 #define BIT_MASK_WLGP_DBC1_8821C 0xf -#define BIT_WLGP_DBC1_8821C(x) (((x) & BIT_MASK_WLGP_DBC1_8821C) << BIT_SHIFT_WLGP_DBC1_8821C) -#define BIT_GET_WLGP_DBC1_8821C(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8821C) & BIT_MASK_WLGP_DBC1_8821C) - +#define BIT_WLGP_DBC1_8821C(x) \ + (((x) & BIT_MASK_WLGP_DBC1_8821C) << BIT_SHIFT_WLGP_DBC1_8821C) +#define BITS_WLGP_DBC1_8821C \ + (BIT_MASK_WLGP_DBC1_8821C << BIT_SHIFT_WLGP_DBC1_8821C) +#define BIT_CLEAR_WLGP_DBC1_8821C(x) ((x) & (~BITS_WLGP_DBC1_8821C)) +#define BIT_GET_WLGP_DBC1_8821C(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC1_8821C) & BIT_MASK_WLGP_DBC1_8821C) +#define BIT_SET_WLGP_DBC1_8821C(x, v) \ + (BIT_CLEAR_WLGP_DBC1_8821C(x) | BIT_WLGP_DBC1_8821C(v)) #define BIT_WLGP_DBC0EN_8821C BIT(7) #define BIT_SHIFT_WLGP_DBC0_8821C 0 #define BIT_MASK_WLGP_DBC0_8821C 0xf -#define BIT_WLGP_DBC0_8821C(x) (((x) & BIT_MASK_WLGP_DBC0_8821C) << BIT_SHIFT_WLGP_DBC0_8821C) -#define BIT_GET_WLGP_DBC0_8821C(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8821C) & BIT_MASK_WLGP_DBC0_8821C) - - +#define BIT_WLGP_DBC0_8821C(x) \ + (((x) & BIT_MASK_WLGP_DBC0_8821C) << BIT_SHIFT_WLGP_DBC0_8821C) +#define BITS_WLGP_DBC0_8821C \ + (BIT_MASK_WLGP_DBC0_8821C << BIT_SHIFT_WLGP_DBC0_8821C) +#define BIT_CLEAR_WLGP_DBC0_8821C(x) ((x) & (~BITS_WLGP_DBC0_8821C)) +#define BIT_GET_WLGP_DBC0_8821C(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC0_8821C) & BIT_MASK_WLGP_DBC0_8821C) +#define BIT_SET_WLGP_DBC0_8821C(x, v) \ + (BIT_CLEAR_WLGP_DBC0_8821C(x) | BIT_WLGP_DBC0_8821C(v)) /* 2 REG_RPWM2_8821C */ #define BIT_SHIFT_RPWM2_8821C 16 #define BIT_MASK_RPWM2_8821C 0xffff -#define BIT_RPWM2_8821C(x) (((x) & BIT_MASK_RPWM2_8821C) << BIT_SHIFT_RPWM2_8821C) -#define BIT_GET_RPWM2_8821C(x) (((x) >> BIT_SHIFT_RPWM2_8821C) & BIT_MASK_RPWM2_8821C) - - +#define BIT_RPWM2_8821C(x) \ + (((x) & BIT_MASK_RPWM2_8821C) << BIT_SHIFT_RPWM2_8821C) +#define BITS_RPWM2_8821C (BIT_MASK_RPWM2_8821C << BIT_SHIFT_RPWM2_8821C) +#define BIT_CLEAR_RPWM2_8821C(x) ((x) & (~BITS_RPWM2_8821C)) +#define BIT_GET_RPWM2_8821C(x) \ + (((x) >> BIT_SHIFT_RPWM2_8821C) & BIT_MASK_RPWM2_8821C) +#define BIT_SET_RPWM2_8821C(x, v) \ + (BIT_CLEAR_RPWM2_8821C(x) | BIT_RPWM2_8821C(v)) /* 2 REG_SYSON_FSM_MON_8821C */ #define BIT_SHIFT_FSM_MON_SEL_8821C 24 #define BIT_MASK_FSM_MON_SEL_8821C 0x7 -#define BIT_FSM_MON_SEL_8821C(x) (((x) & BIT_MASK_FSM_MON_SEL_8821C) << BIT_SHIFT_FSM_MON_SEL_8821C) -#define BIT_GET_FSM_MON_SEL_8821C(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8821C) & BIT_MASK_FSM_MON_SEL_8821C) - +#define BIT_FSM_MON_SEL_8821C(x) \ + (((x) & BIT_MASK_FSM_MON_SEL_8821C) << BIT_SHIFT_FSM_MON_SEL_8821C) +#define BITS_FSM_MON_SEL_8821C \ + (BIT_MASK_FSM_MON_SEL_8821C << BIT_SHIFT_FSM_MON_SEL_8821C) +#define BIT_CLEAR_FSM_MON_SEL_8821C(x) ((x) & (~BITS_FSM_MON_SEL_8821C)) +#define BIT_GET_FSM_MON_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL_8821C) & BIT_MASK_FSM_MON_SEL_8821C) +#define BIT_SET_FSM_MON_SEL_8821C(x, v) \ + (BIT_CLEAR_FSM_MON_SEL_8821C(x) | BIT_FSM_MON_SEL_8821C(v)) #define BIT_DOP_ELDO_8821C BIT(23) #define BIT_FSM_MON_UPD_8821C BIT(15) #define BIT_SHIFT_FSM_PAR_8821C 0 #define BIT_MASK_FSM_PAR_8821C 0x7fff -#define BIT_FSM_PAR_8821C(x) (((x) & BIT_MASK_FSM_PAR_8821C) << BIT_SHIFT_FSM_PAR_8821C) -#define BIT_GET_FSM_PAR_8821C(x) (((x) >> BIT_SHIFT_FSM_PAR_8821C) & BIT_MASK_FSM_PAR_8821C) - - +#define BIT_FSM_PAR_8821C(x) \ + (((x) & BIT_MASK_FSM_PAR_8821C) << BIT_SHIFT_FSM_PAR_8821C) +#define BITS_FSM_PAR_8821C (BIT_MASK_FSM_PAR_8821C << BIT_SHIFT_FSM_PAR_8821C) +#define BIT_CLEAR_FSM_PAR_8821C(x) ((x) & (~BITS_FSM_PAR_8821C)) +#define BIT_GET_FSM_PAR_8821C(x) \ + (((x) >> BIT_SHIFT_FSM_PAR_8821C) & BIT_MASK_FSM_PAR_8821C) +#define BIT_SET_FSM_PAR_8821C(x, v) \ + (BIT_CLEAR_FSM_PAR_8821C(x) | BIT_FSM_PAR_8821C(v)) /* 2 REG_AFE_CTRL6_8821C */ #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0 #define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) - - +#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) +#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) \ + ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) | \ + BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(v)) /* 2 REG_PMC_DBG_CTRL1_8821C */ #define BIT_BT_INT_EN_8821C BIT(31) #define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C 16 #define BIT_MASK_RD_WR_WIFI_BT_INFO_8821C 0x7fff -#define BIT_RD_WR_WIFI_BT_INFO_8821C(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) -#define BIT_GET_RD_WR_WIFI_BT_INFO_8821C(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) - +#define BIT_RD_WR_WIFI_BT_INFO_8821C(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) +#define BITS_RD_WR_WIFI_BT_INFO_8821C \ + (BIT_MASK_RD_WR_WIFI_BT_INFO_8821C \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8821C(x) \ + ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8821C)) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) & \ + BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) +#define BIT_SET_RD_WR_WIFI_BT_INFO_8821C(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8821C(x) | \ + BIT_RD_WR_WIFI_BT_INFO_8821C(v)) #define BIT_PMC_WR_OVF_8821C BIT(8) #define BIT_SHIFT_WLPMC_ERRINT_8821C 0 #define BIT_MASK_WLPMC_ERRINT_8821C 0xff -#define BIT_WLPMC_ERRINT_8821C(x) (((x) & BIT_MASK_WLPMC_ERRINT_8821C) << BIT_SHIFT_WLPMC_ERRINT_8821C) -#define BIT_GET_WLPMC_ERRINT_8821C(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8821C) & BIT_MASK_WLPMC_ERRINT_8821C) - - +#define BIT_WLPMC_ERRINT_8821C(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT_8821C) << BIT_SHIFT_WLPMC_ERRINT_8821C) +#define BITS_WLPMC_ERRINT_8821C \ + (BIT_MASK_WLPMC_ERRINT_8821C << BIT_SHIFT_WLPMC_ERRINT_8821C) +#define BIT_CLEAR_WLPMC_ERRINT_8821C(x) ((x) & (~BITS_WLPMC_ERRINT_8821C)) +#define BIT_GET_WLPMC_ERRINT_8821C(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT_8821C) & BIT_MASK_WLPMC_ERRINT_8821C) +#define BIT_SET_WLPMC_ERRINT_8821C(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT_8821C(x) | BIT_WLPMC_ERRINT_8821C(v)) /* 2 REG_AFE_CTRL7_8821C */ #define BIT_SHIFT_SEL_V_8821C 30 #define BIT_MASK_SEL_V_8821C 0x3 -#define BIT_SEL_V_8821C(x) (((x) & BIT_MASK_SEL_V_8821C) << BIT_SHIFT_SEL_V_8821C) -#define BIT_GET_SEL_V_8821C(x) (((x) >> BIT_SHIFT_SEL_V_8821C) & BIT_MASK_SEL_V_8821C) - +#define BIT_SEL_V_8821C(x) \ + (((x) & BIT_MASK_SEL_V_8821C) << BIT_SHIFT_SEL_V_8821C) +#define BITS_SEL_V_8821C (BIT_MASK_SEL_V_8821C << BIT_SHIFT_SEL_V_8821C) +#define BIT_CLEAR_SEL_V_8821C(x) ((x) & (~BITS_SEL_V_8821C)) +#define BIT_GET_SEL_V_8821C(x) \ + (((x) >> BIT_SHIFT_SEL_V_8821C) & BIT_MASK_SEL_V_8821C) +#define BIT_SET_SEL_V_8821C(x, v) \ + (BIT_CLEAR_SEL_V_8821C(x) | BIT_SEL_V_8821C(v)) #define BIT_SEL_LDO_PC_8821C BIT(29) #define BIT_SHIFT_CK_MON_SEL_8821C 26 #define BIT_MASK_CK_MON_SEL_8821C 0x7 -#define BIT_CK_MON_SEL_8821C(x) (((x) & BIT_MASK_CK_MON_SEL_8821C) << BIT_SHIFT_CK_MON_SEL_8821C) -#define BIT_GET_CK_MON_SEL_8821C(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8821C) & BIT_MASK_CK_MON_SEL_8821C) - +#define BIT_CK_MON_SEL_8821C(x) \ + (((x) & BIT_MASK_CK_MON_SEL_8821C) << BIT_SHIFT_CK_MON_SEL_8821C) +#define BITS_CK_MON_SEL_8821C \ + (BIT_MASK_CK_MON_SEL_8821C << BIT_SHIFT_CK_MON_SEL_8821C) +#define BIT_CLEAR_CK_MON_SEL_8821C(x) ((x) & (~BITS_CK_MON_SEL_8821C)) +#define BIT_GET_CK_MON_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_8821C) & BIT_MASK_CK_MON_SEL_8821C) +#define BIT_SET_CK_MON_SEL_8821C(x, v) \ + (BIT_CLEAR_CK_MON_SEL_8821C(x) | BIT_CK_MON_SEL_8821C(v)) #define BIT_CK_MON_EN_8821C BIT(25) #define BIT_FREF_EDGE_8821C BIT(24) @@ -1350,8 +1993,8 @@ #define BIT_RXOK_MSK_8821C BIT(0) /* 2 REG_HISR0_8821C */ -#define BIT_TIMEOUT_INTERRUPT2_8821C BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_8821C BIT(30) +#define BIT_PSTIMEOUT2_8821C BIT(31) +#define BIT_PSTIMEOUT1_8821C BIT(30) #define BIT_PSTIMEOUT_8821C BIT(29) #define BIT_GTINT4_8821C BIT(28) #define BIT_GTINT3_8821C BIT(27) @@ -1442,28 +2085,48 @@ #define BIT_SHIFT_DEBUG_ST_8821C 0 #define BIT_MASK_DEBUG_ST_8821C 0xffffffffL -#define BIT_DEBUG_ST_8821C(x) (((x) & BIT_MASK_DEBUG_ST_8821C) << BIT_SHIFT_DEBUG_ST_8821C) -#define BIT_GET_DEBUG_ST_8821C(x) (((x) >> BIT_SHIFT_DEBUG_ST_8821C) & BIT_MASK_DEBUG_ST_8821C) - - +#define BIT_DEBUG_ST_8821C(x) \ + (((x) & BIT_MASK_DEBUG_ST_8821C) << BIT_SHIFT_DEBUG_ST_8821C) +#define BITS_DEBUG_ST_8821C \ + (BIT_MASK_DEBUG_ST_8821C << BIT_SHIFT_DEBUG_ST_8821C) +#define BIT_CLEAR_DEBUG_ST_8821C(x) ((x) & (~BITS_DEBUG_ST_8821C)) +#define BIT_GET_DEBUG_ST_8821C(x) \ + (((x) >> BIT_SHIFT_DEBUG_ST_8821C) & BIT_MASK_DEBUG_ST_8821C) +#define BIT_SET_DEBUG_ST_8821C(x, v) \ + (BIT_CLEAR_DEBUG_ST_8821C(x) | BIT_DEBUG_ST_8821C(v)) /* 2 REG_PAD_CTRL2_8821C */ #define BIT_USB3_USB2_TRANSITION_8821C BIT(20) #define BIT_SHIFT_USB23_SW_MODE_V1_8821C 18 #define BIT_MASK_USB23_SW_MODE_V1_8821C 0x3 -#define BIT_USB23_SW_MODE_V1_8821C(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8821C) << BIT_SHIFT_USB23_SW_MODE_V1_8821C) -#define BIT_GET_USB23_SW_MODE_V1_8821C(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8821C) & BIT_MASK_USB23_SW_MODE_V1_8821C) - +#define BIT_USB23_SW_MODE_V1_8821C(x) \ + (((x) & BIT_MASK_USB23_SW_MODE_V1_8821C) \ + << BIT_SHIFT_USB23_SW_MODE_V1_8821C) +#define BITS_USB23_SW_MODE_V1_8821C \ + (BIT_MASK_USB23_SW_MODE_V1_8821C << BIT_SHIFT_USB23_SW_MODE_V1_8821C) +#define BIT_CLEAR_USB23_SW_MODE_V1_8821C(x) \ + ((x) & (~BITS_USB23_SW_MODE_V1_8821C)) +#define BIT_GET_USB23_SW_MODE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8821C) & \ + BIT_MASK_USB23_SW_MODE_V1_8821C) +#define BIT_SET_USB23_SW_MODE_V1_8821C(x, v) \ + (BIT_CLEAR_USB23_SW_MODE_V1_8821C(x) | BIT_USB23_SW_MODE_V1_8821C(v)) #define BIT_NO_PDN_CHIPOFF_V1_8821C BIT(17) #define BIT_RSM_EN_V1_8821C BIT(16) #define BIT_SHIFT_MATCH_CNT_8821C 8 #define BIT_MASK_MATCH_CNT_8821C 0xff -#define BIT_MATCH_CNT_8821C(x) (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C) -#define BIT_GET_MATCH_CNT_8821C(x) (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) - +#define BIT_MATCH_CNT_8821C(x) \ + (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C) +#define BITS_MATCH_CNT_8821C \ + (BIT_MASK_MATCH_CNT_8821C << BIT_SHIFT_MATCH_CNT_8821C) +#define BIT_CLEAR_MATCH_CNT_8821C(x) ((x) & (~BITS_MATCH_CNT_8821C)) +#define BIT_GET_MATCH_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) +#define BIT_SET_MATCH_CNT_8821C(x, v) \ + (BIT_CLEAR_MATCH_CNT_8821C(x) | BIT_MATCH_CNT_8821C(v)) #define BIT_LD_B12V_EN_8821C BIT(7) #define BIT_EECS_IOSEL_V1_8821C BIT(6) @@ -1479,9 +2142,17 @@ #define BIT_SHIFT_EFUSE_BURN_GNT_8821C 24 #define BIT_MASK_EFUSE_BURN_GNT_8821C 0xff -#define BIT_EFUSE_BURN_GNT_8821C(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8821C) << BIT_SHIFT_EFUSE_BURN_GNT_8821C) -#define BIT_GET_EFUSE_BURN_GNT_8821C(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8821C) & BIT_MASK_EFUSE_BURN_GNT_8821C) - +#define BIT_EFUSE_BURN_GNT_8821C(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT_8821C) \ + << BIT_SHIFT_EFUSE_BURN_GNT_8821C) +#define BITS_EFUSE_BURN_GNT_8821C \ + (BIT_MASK_EFUSE_BURN_GNT_8821C << BIT_SHIFT_EFUSE_BURN_GNT_8821C) +#define BIT_CLEAR_EFUSE_BURN_GNT_8821C(x) ((x) & (~BITS_EFUSE_BURN_GNT_8821C)) +#define BIT_GET_EFUSE_BURN_GNT_8821C(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8821C) & \ + BIT_MASK_EFUSE_BURN_GNT_8821C) +#define BIT_SET_EFUSE_BURN_GNT_8821C(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT_8821C(x) | BIT_EFUSE_BURN_GNT_8821C(v)) #define BIT_STOP_WL_PMC_8821C BIT(9) #define BIT_STOP_SYM_PMC_8821C BIT(8) @@ -1493,10 +2164,15 @@ #define BIT_SHIFT_SYSON_REG_ARB_8821C 0 #define BIT_MASK_SYSON_REG_ARB_8821C 0x3 -#define BIT_SYSON_REG_ARB_8821C(x) (((x) & BIT_MASK_SYSON_REG_ARB_8821C) << BIT_SHIFT_SYSON_REG_ARB_8821C) -#define BIT_GET_SYSON_REG_ARB_8821C(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8821C) & BIT_MASK_SYSON_REG_ARB_8821C) - - +#define BIT_SYSON_REG_ARB_8821C(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB_8821C) << BIT_SHIFT_SYSON_REG_ARB_8821C) +#define BITS_SYSON_REG_ARB_8821C \ + (BIT_MASK_SYSON_REG_ARB_8821C << BIT_SHIFT_SYSON_REG_ARB_8821C) +#define BIT_CLEAR_SYSON_REG_ARB_8821C(x) ((x) & (~BITS_SYSON_REG_ARB_8821C)) +#define BIT_GET_SYSON_REG_ARB_8821C(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB_8821C) & BIT_MASK_SYSON_REG_ARB_8821C) +#define BIT_SET_SYSON_REG_ARB_8821C(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB_8821C(x) | BIT_SYSON_REG_ARB_8821C(v)) /* 2 REG_BIST_CTRL_8821C */ #define BIT_BIST_USB_DIS_8821C BIT(27) @@ -1506,9 +2182,15 @@ #define BIT_SHIFT_BIST_RPT_SEL_8821C 16 #define BIT_MASK_BIST_RPT_SEL_8821C 0xf -#define BIT_BIST_RPT_SEL_8821C(x) (((x) & BIT_MASK_BIST_RPT_SEL_8821C) << BIT_SHIFT_BIST_RPT_SEL_8821C) -#define BIT_GET_BIST_RPT_SEL_8821C(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8821C) & BIT_MASK_BIST_RPT_SEL_8821C) - +#define BIT_BIST_RPT_SEL_8821C(x) \ + (((x) & BIT_MASK_BIST_RPT_SEL_8821C) << BIT_SHIFT_BIST_RPT_SEL_8821C) +#define BITS_BIST_RPT_SEL_8821C \ + (BIT_MASK_BIST_RPT_SEL_8821C << BIT_SHIFT_BIST_RPT_SEL_8821C) +#define BIT_CLEAR_BIST_RPT_SEL_8821C(x) ((x) & (~BITS_BIST_RPT_SEL_8821C)) +#define BIT_GET_BIST_RPT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_BIST_RPT_SEL_8821C) & BIT_MASK_BIST_RPT_SEL_8821C) +#define BIT_SET_BIST_RPT_SEL_8821C(x, v) \ + (BIT_CLEAR_BIST_RPT_SEL_8821C(x) | BIT_BIST_RPT_SEL_8821C(v)) #define BIT_BIST_RESUME_PS_8821C BIT(4) #define BIT_BIST_RESUME_8821C BIT(3) @@ -1520,62 +2202,100 @@ #define BIT_SHIFT_MBIST_REPORT_8821C 0 #define BIT_MASK_MBIST_REPORT_8821C 0xffffffffL -#define BIT_MBIST_REPORT_8821C(x) (((x) & BIT_MASK_MBIST_REPORT_8821C) << BIT_SHIFT_MBIST_REPORT_8821C) -#define BIT_GET_MBIST_REPORT_8821C(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8821C) & BIT_MASK_MBIST_REPORT_8821C) - - +#define BIT_MBIST_REPORT_8821C(x) \ + (((x) & BIT_MASK_MBIST_REPORT_8821C) << BIT_SHIFT_MBIST_REPORT_8821C) +#define BITS_MBIST_REPORT_8821C \ + (BIT_MASK_MBIST_REPORT_8821C << BIT_SHIFT_MBIST_REPORT_8821C) +#define BIT_CLEAR_MBIST_REPORT_8821C(x) ((x) & (~BITS_MBIST_REPORT_8821C)) +#define BIT_GET_MBIST_REPORT_8821C(x) \ + (((x) >> BIT_SHIFT_MBIST_REPORT_8821C) & BIT_MASK_MBIST_REPORT_8821C) +#define BIT_SET_MBIST_REPORT_8821C(x, v) \ + (BIT_CLEAR_MBIST_REPORT_8821C(x) | BIT_MBIST_REPORT_8821C(v)) /* 2 REG_MEM_CTRL_8821C */ #define BIT_UMEM_RME_8821C BIT(31) #define BIT_SHIFT_BT_SPRAM_8821C 28 #define BIT_MASK_BT_SPRAM_8821C 0x3 -#define BIT_BT_SPRAM_8821C(x) (((x) & BIT_MASK_BT_SPRAM_8821C) << BIT_SHIFT_BT_SPRAM_8821C) -#define BIT_GET_BT_SPRAM_8821C(x) (((x) >> BIT_SHIFT_BT_SPRAM_8821C) & BIT_MASK_BT_SPRAM_8821C) - - +#define BIT_BT_SPRAM_8821C(x) \ + (((x) & BIT_MASK_BT_SPRAM_8821C) << BIT_SHIFT_BT_SPRAM_8821C) +#define BITS_BT_SPRAM_8821C \ + (BIT_MASK_BT_SPRAM_8821C << BIT_SHIFT_BT_SPRAM_8821C) +#define BIT_CLEAR_BT_SPRAM_8821C(x) ((x) & (~BITS_BT_SPRAM_8821C)) +#define BIT_GET_BT_SPRAM_8821C(x) \ + (((x) >> BIT_SHIFT_BT_SPRAM_8821C) & BIT_MASK_BT_SPRAM_8821C) +#define BIT_SET_BT_SPRAM_8821C(x, v) \ + (BIT_CLEAR_BT_SPRAM_8821C(x) | BIT_BT_SPRAM_8821C(v)) #define BIT_SHIFT_BT_ROM_8821C 24 #define BIT_MASK_BT_ROM_8821C 0xf -#define BIT_BT_ROM_8821C(x) (((x) & BIT_MASK_BT_ROM_8821C) << BIT_SHIFT_BT_ROM_8821C) -#define BIT_GET_BT_ROM_8821C(x) (((x) >> BIT_SHIFT_BT_ROM_8821C) & BIT_MASK_BT_ROM_8821C) - - +#define BIT_BT_ROM_8821C(x) \ + (((x) & BIT_MASK_BT_ROM_8821C) << BIT_SHIFT_BT_ROM_8821C) +#define BITS_BT_ROM_8821C (BIT_MASK_BT_ROM_8821C << BIT_SHIFT_BT_ROM_8821C) +#define BIT_CLEAR_BT_ROM_8821C(x) ((x) & (~BITS_BT_ROM_8821C)) +#define BIT_GET_BT_ROM_8821C(x) \ + (((x) >> BIT_SHIFT_BT_ROM_8821C) & BIT_MASK_BT_ROM_8821C) +#define BIT_SET_BT_ROM_8821C(x, v) \ + (BIT_CLEAR_BT_ROM_8821C(x) | BIT_BT_ROM_8821C(v)) #define BIT_SHIFT_PCI_DPRAM_8821C 10 #define BIT_MASK_PCI_DPRAM_8821C 0x3 -#define BIT_PCI_DPRAM_8821C(x) (((x) & BIT_MASK_PCI_DPRAM_8821C) << BIT_SHIFT_PCI_DPRAM_8821C) -#define BIT_GET_PCI_DPRAM_8821C(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8821C) & BIT_MASK_PCI_DPRAM_8821C) - - +#define BIT_PCI_DPRAM_8821C(x) \ + (((x) & BIT_MASK_PCI_DPRAM_8821C) << BIT_SHIFT_PCI_DPRAM_8821C) +#define BITS_PCI_DPRAM_8821C \ + (BIT_MASK_PCI_DPRAM_8821C << BIT_SHIFT_PCI_DPRAM_8821C) +#define BIT_CLEAR_PCI_DPRAM_8821C(x) ((x) & (~BITS_PCI_DPRAM_8821C)) +#define BIT_GET_PCI_DPRAM_8821C(x) \ + (((x) >> BIT_SHIFT_PCI_DPRAM_8821C) & BIT_MASK_PCI_DPRAM_8821C) +#define BIT_SET_PCI_DPRAM_8821C(x, v) \ + (BIT_CLEAR_PCI_DPRAM_8821C(x) | BIT_PCI_DPRAM_8821C(v)) #define BIT_SHIFT_PCI_SPRAM_8821C 8 #define BIT_MASK_PCI_SPRAM_8821C 0x3 -#define BIT_PCI_SPRAM_8821C(x) (((x) & BIT_MASK_PCI_SPRAM_8821C) << BIT_SHIFT_PCI_SPRAM_8821C) -#define BIT_GET_PCI_SPRAM_8821C(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8821C) & BIT_MASK_PCI_SPRAM_8821C) - - +#define BIT_PCI_SPRAM_8821C(x) \ + (((x) & BIT_MASK_PCI_SPRAM_8821C) << BIT_SHIFT_PCI_SPRAM_8821C) +#define BITS_PCI_SPRAM_8821C \ + (BIT_MASK_PCI_SPRAM_8821C << BIT_SHIFT_PCI_SPRAM_8821C) +#define BIT_CLEAR_PCI_SPRAM_8821C(x) ((x) & (~BITS_PCI_SPRAM_8821C)) +#define BIT_GET_PCI_SPRAM_8821C(x) \ + (((x) >> BIT_SHIFT_PCI_SPRAM_8821C) & BIT_MASK_PCI_SPRAM_8821C) +#define BIT_SET_PCI_SPRAM_8821C(x, v) \ + (BIT_CLEAR_PCI_SPRAM_8821C(x) | BIT_PCI_SPRAM_8821C(v)) #define BIT_SHIFT_USB_SPRAM_8821C 6 #define BIT_MASK_USB_SPRAM_8821C 0x3 -#define BIT_USB_SPRAM_8821C(x) (((x) & BIT_MASK_USB_SPRAM_8821C) << BIT_SHIFT_USB_SPRAM_8821C) -#define BIT_GET_USB_SPRAM_8821C(x) (((x) >> BIT_SHIFT_USB_SPRAM_8821C) & BIT_MASK_USB_SPRAM_8821C) - - +#define BIT_USB_SPRAM_8821C(x) \ + (((x) & BIT_MASK_USB_SPRAM_8821C) << BIT_SHIFT_USB_SPRAM_8821C) +#define BITS_USB_SPRAM_8821C \ + (BIT_MASK_USB_SPRAM_8821C << BIT_SHIFT_USB_SPRAM_8821C) +#define BIT_CLEAR_USB_SPRAM_8821C(x) ((x) & (~BITS_USB_SPRAM_8821C)) +#define BIT_GET_USB_SPRAM_8821C(x) \ + (((x) >> BIT_SHIFT_USB_SPRAM_8821C) & BIT_MASK_USB_SPRAM_8821C) +#define BIT_SET_USB_SPRAM_8821C(x, v) \ + (BIT_CLEAR_USB_SPRAM_8821C(x) | BIT_USB_SPRAM_8821C(v)) #define BIT_SHIFT_USB_SPRF_8821C 4 #define BIT_MASK_USB_SPRF_8821C 0x3 -#define BIT_USB_SPRF_8821C(x) (((x) & BIT_MASK_USB_SPRF_8821C) << BIT_SHIFT_USB_SPRF_8821C) -#define BIT_GET_USB_SPRF_8821C(x) (((x) >> BIT_SHIFT_USB_SPRF_8821C) & BIT_MASK_USB_SPRF_8821C) - - +#define BIT_USB_SPRF_8821C(x) \ + (((x) & BIT_MASK_USB_SPRF_8821C) << BIT_SHIFT_USB_SPRF_8821C) +#define BITS_USB_SPRF_8821C \ + (BIT_MASK_USB_SPRF_8821C << BIT_SHIFT_USB_SPRF_8821C) +#define BIT_CLEAR_USB_SPRF_8821C(x) ((x) & (~BITS_USB_SPRF_8821C)) +#define BIT_GET_USB_SPRF_8821C(x) \ + (((x) >> BIT_SHIFT_USB_SPRF_8821C) & BIT_MASK_USB_SPRF_8821C) +#define BIT_SET_USB_SPRF_8821C(x, v) \ + (BIT_CLEAR_USB_SPRF_8821C(x) | BIT_USB_SPRF_8821C(v)) #define BIT_SHIFT_MCU_ROM_8821C 0 #define BIT_MASK_MCU_ROM_8821C 0xf -#define BIT_MCU_ROM_8821C(x) (((x) & BIT_MASK_MCU_ROM_8821C) << BIT_SHIFT_MCU_ROM_8821C) -#define BIT_GET_MCU_ROM_8821C(x) (((x) >> BIT_SHIFT_MCU_ROM_8821C) & BIT_MASK_MCU_ROM_8821C) - - +#define BIT_MCU_ROM_8821C(x) \ + (((x) & BIT_MASK_MCU_ROM_8821C) << BIT_SHIFT_MCU_ROM_8821C) +#define BITS_MCU_ROM_8821C (BIT_MASK_MCU_ROM_8821C << BIT_SHIFT_MCU_ROM_8821C) +#define BIT_CLEAR_MCU_ROM_8821C(x) ((x) & (~BITS_MCU_ROM_8821C)) +#define BIT_GET_MCU_ROM_8821C(x) \ + (((x) >> BIT_SHIFT_MCU_ROM_8821C) & BIT_MASK_MCU_ROM_8821C) +#define BIT_SET_MCU_ROM_8821C(x, v) \ + (BIT_CLEAR_MCU_ROM_8821C(x) | BIT_MCU_ROM_8821C(v)) /* 2 REG_AFE_CTRL8_8821C */ #define BIT_SYN_AGPIO_8821C BIT(20) @@ -1584,10 +2304,15 @@ #define BIT_SHIFT_XTAL_SEL_TOK_8821C 0 #define BIT_MASK_XTAL_SEL_TOK_8821C 0x7 -#define BIT_XTAL_SEL_TOK_8821C(x) (((x) & BIT_MASK_XTAL_SEL_TOK_8821C) << BIT_SHIFT_XTAL_SEL_TOK_8821C) -#define BIT_GET_XTAL_SEL_TOK_8821C(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8821C) & BIT_MASK_XTAL_SEL_TOK_8821C) - - +#define BIT_XTAL_SEL_TOK_8821C(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_8821C) << BIT_SHIFT_XTAL_SEL_TOK_8821C) +#define BITS_XTAL_SEL_TOK_8821C \ + (BIT_MASK_XTAL_SEL_TOK_8821C << BIT_SHIFT_XTAL_SEL_TOK_8821C) +#define BIT_CLEAR_XTAL_SEL_TOK_8821C(x) ((x) & (~BITS_XTAL_SEL_TOK_8821C)) +#define BIT_GET_XTAL_SEL_TOK_8821C(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8821C) & BIT_MASK_XTAL_SEL_TOK_8821C) +#define BIT_SET_XTAL_SEL_TOK_8821C(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_8821C(x) | BIT_XTAL_SEL_TOK_8821C(v)) /* 2 REG_USB_SIE_INTF_8821C */ #define BIT_RD_SEL_8821C BIT(31) @@ -1597,68 +2322,136 @@ #define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C 16 #define BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C 0x1ff -#define BIT_USB_SIE_INTF_ADDR_V1_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) -#define BIT_GET_USB_SIE_INTF_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) - - +#define BIT_USB_SIE_INTF_ADDR_V1_8821C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) +#define BITS_USB_SIE_INTF_ADDR_V1_8821C \ + (BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) +#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8821C(x) \ + ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8821C)) +#define BIT_GET_USB_SIE_INTF_ADDR_V1_8821C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) & \ + BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) +#define BIT_SET_USB_SIE_INTF_ADDR_V1_8821C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8821C(x) | \ + BIT_USB_SIE_INTF_ADDR_V1_8821C(v)) #define BIT_SHIFT_USB_SIE_INTF_RD_8821C 8 #define BIT_MASK_USB_SIE_INTF_RD_8821C 0xff -#define BIT_USB_SIE_INTF_RD_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8821C) << BIT_SHIFT_USB_SIE_INTF_RD_8821C) -#define BIT_GET_USB_SIE_INTF_RD_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8821C) & BIT_MASK_USB_SIE_INTF_RD_8821C) - - +#define BIT_USB_SIE_INTF_RD_8821C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_RD_8821C) \ + << BIT_SHIFT_USB_SIE_INTF_RD_8821C) +#define BITS_USB_SIE_INTF_RD_8821C \ + (BIT_MASK_USB_SIE_INTF_RD_8821C << BIT_SHIFT_USB_SIE_INTF_RD_8821C) +#define BIT_CLEAR_USB_SIE_INTF_RD_8821C(x) ((x) & (~BITS_USB_SIE_INTF_RD_8821C)) +#define BIT_GET_USB_SIE_INTF_RD_8821C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8821C) & \ + BIT_MASK_USB_SIE_INTF_RD_8821C) +#define BIT_SET_USB_SIE_INTF_RD_8821C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_RD_8821C(x) | BIT_USB_SIE_INTF_RD_8821C(v)) #define BIT_SHIFT_USB_SIE_INTF_WD_8821C 0 #define BIT_MASK_USB_SIE_INTF_WD_8821C 0xff -#define BIT_USB_SIE_INTF_WD_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8821C) << BIT_SHIFT_USB_SIE_INTF_WD_8821C) -#define BIT_GET_USB_SIE_INTF_WD_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8821C) & BIT_MASK_USB_SIE_INTF_WD_8821C) +#define BIT_USB_SIE_INTF_WD_8821C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_WD_8821C) \ + << BIT_SHIFT_USB_SIE_INTF_WD_8821C) +#define BITS_USB_SIE_INTF_WD_8821C \ + (BIT_MASK_USB_SIE_INTF_WD_8821C << BIT_SHIFT_USB_SIE_INTF_WD_8821C) +#define BIT_CLEAR_USB_SIE_INTF_WD_8821C(x) ((x) & (~BITS_USB_SIE_INTF_WD_8821C)) +#define BIT_GET_USB_SIE_INTF_WD_8821C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8821C) & \ + BIT_MASK_USB_SIE_INTF_WD_8821C) +#define BIT_SET_USB_SIE_INTF_WD_8821C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_WD_8821C(x) | BIT_USB_SIE_INTF_WD_8821C(v)) +/* 2 REG_PCIE_MIO_INTF_8821C */ +#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C 16 +#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C 0x3 +#define BIT_PCIE_MIO_ADDR_PAGE_8821C(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C) \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C) +#define BITS_PCIE_MIO_ADDR_PAGE_8821C \ + (BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C) +#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8821C(x) \ + ((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8821C)) +#define BIT_GET_PCIE_MIO_ADDR_PAGE_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C) & \ + BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C) +#define BIT_SET_PCIE_MIO_ADDR_PAGE_8821C(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8821C(x) | \ + BIT_PCIE_MIO_ADDR_PAGE_8821C(v)) -/* 2 REG_PCIE_MIO_INTF_8821C */ #define BIT_PCIE_MIO_BYIOREG_8821C BIT(13) #define BIT_PCIE_MIO_RE_8821C BIT(12) #define BIT_SHIFT_PCIE_MIO_WE_8821C 8 #define BIT_MASK_PCIE_MIO_WE_8821C 0xf -#define BIT_PCIE_MIO_WE_8821C(x) (((x) & BIT_MASK_PCIE_MIO_WE_8821C) << BIT_SHIFT_PCIE_MIO_WE_8821C) -#define BIT_GET_PCIE_MIO_WE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8821C) & BIT_MASK_PCIE_MIO_WE_8821C) - - +#define BIT_PCIE_MIO_WE_8821C(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE_8821C) << BIT_SHIFT_PCIE_MIO_WE_8821C) +#define BITS_PCIE_MIO_WE_8821C \ + (BIT_MASK_PCIE_MIO_WE_8821C << BIT_SHIFT_PCIE_MIO_WE_8821C) +#define BIT_CLEAR_PCIE_MIO_WE_8821C(x) ((x) & (~BITS_PCIE_MIO_WE_8821C)) +#define BIT_GET_PCIE_MIO_WE_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE_8821C) & BIT_MASK_PCIE_MIO_WE_8821C) +#define BIT_SET_PCIE_MIO_WE_8821C(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE_8821C(x) | BIT_PCIE_MIO_WE_8821C(v)) #define BIT_SHIFT_PCIE_MIO_ADDR_8821C 0 #define BIT_MASK_PCIE_MIO_ADDR_8821C 0xff -#define BIT_PCIE_MIO_ADDR_8821C(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8821C) << BIT_SHIFT_PCIE_MIO_ADDR_8821C) -#define BIT_GET_PCIE_MIO_ADDR_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8821C) & BIT_MASK_PCIE_MIO_ADDR_8821C) - - +#define BIT_PCIE_MIO_ADDR_8821C(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_8821C) << BIT_SHIFT_PCIE_MIO_ADDR_8821C) +#define BITS_PCIE_MIO_ADDR_8821C \ + (BIT_MASK_PCIE_MIO_ADDR_8821C << BIT_SHIFT_PCIE_MIO_ADDR_8821C) +#define BIT_CLEAR_PCIE_MIO_ADDR_8821C(x) ((x) & (~BITS_PCIE_MIO_ADDR_8821C)) +#define BIT_GET_PCIE_MIO_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8821C) & BIT_MASK_PCIE_MIO_ADDR_8821C) +#define BIT_SET_PCIE_MIO_ADDR_8821C(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_8821C(x) | BIT_PCIE_MIO_ADDR_8821C(v)) /* 2 REG_PCIE_MIO_INTD_8821C */ #define BIT_SHIFT_PCIE_MIO_DATA_8821C 0 #define BIT_MASK_PCIE_MIO_DATA_8821C 0xffffffffL -#define BIT_PCIE_MIO_DATA_8821C(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8821C) << BIT_SHIFT_PCIE_MIO_DATA_8821C) -#define BIT_GET_PCIE_MIO_DATA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8821C) & BIT_MASK_PCIE_MIO_DATA_8821C) - - +#define BIT_PCIE_MIO_DATA_8821C(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA_8821C) << BIT_SHIFT_PCIE_MIO_DATA_8821C) +#define BITS_PCIE_MIO_DATA_8821C \ + (BIT_MASK_PCIE_MIO_DATA_8821C << BIT_SHIFT_PCIE_MIO_DATA_8821C) +#define BIT_CLEAR_PCIE_MIO_DATA_8821C(x) ((x) & (~BITS_PCIE_MIO_DATA_8821C)) +#define BIT_GET_PCIE_MIO_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8821C) & BIT_MASK_PCIE_MIO_DATA_8821C) +#define BIT_SET_PCIE_MIO_DATA_8821C(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA_8821C(x) | BIT_PCIE_MIO_DATA_8821C(v)) /* 2 REG_WLRF1_8821C */ #define BIT_SHIFT_WLRF1_CTRL_8821C 24 #define BIT_MASK_WLRF1_CTRL_8821C 0xff -#define BIT_WLRF1_CTRL_8821C(x) (((x) & BIT_MASK_WLRF1_CTRL_8821C) << BIT_SHIFT_WLRF1_CTRL_8821C) -#define BIT_GET_WLRF1_CTRL_8821C(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8821C) & BIT_MASK_WLRF1_CTRL_8821C) - - +#define BIT_WLRF1_CTRL_8821C(x) \ + (((x) & BIT_MASK_WLRF1_CTRL_8821C) << BIT_SHIFT_WLRF1_CTRL_8821C) +#define BITS_WLRF1_CTRL_8821C \ + (BIT_MASK_WLRF1_CTRL_8821C << BIT_SHIFT_WLRF1_CTRL_8821C) +#define BIT_CLEAR_WLRF1_CTRL_8821C(x) ((x) & (~BITS_WLRF1_CTRL_8821C)) +#define BIT_GET_WLRF1_CTRL_8821C(x) \ + (((x) >> BIT_SHIFT_WLRF1_CTRL_8821C) & BIT_MASK_WLRF1_CTRL_8821C) +#define BIT_SET_WLRF1_CTRL_8821C(x, v) \ + (BIT_CLEAR_WLRF1_CTRL_8821C(x) | BIT_WLRF1_CTRL_8821C(v)) /* 2 REG_SYS_CFG1_8821C */ #define BIT_SHIFT_TRP_ICFG_8821C 28 #define BIT_MASK_TRP_ICFG_8821C 0xf -#define BIT_TRP_ICFG_8821C(x) (((x) & BIT_MASK_TRP_ICFG_8821C) << BIT_SHIFT_TRP_ICFG_8821C) -#define BIT_GET_TRP_ICFG_8821C(x) (((x) >> BIT_SHIFT_TRP_ICFG_8821C) & BIT_MASK_TRP_ICFG_8821C) - +#define BIT_TRP_ICFG_8821C(x) \ + (((x) & BIT_MASK_TRP_ICFG_8821C) << BIT_SHIFT_TRP_ICFG_8821C) +#define BITS_TRP_ICFG_8821C \ + (BIT_MASK_TRP_ICFG_8821C << BIT_SHIFT_TRP_ICFG_8821C) +#define BIT_CLEAR_TRP_ICFG_8821C(x) ((x) & (~BITS_TRP_ICFG_8821C)) +#define BIT_GET_TRP_ICFG_8821C(x) \ + (((x) >> BIT_SHIFT_TRP_ICFG_8821C) & BIT_MASK_TRP_ICFG_8821C) +#define BIT_SET_TRP_ICFG_8821C(x, v) \ + (BIT_CLEAR_TRP_ICFG_8821C(x) | BIT_TRP_ICFG_8821C(v)) #define BIT_RF_TYPE_ID_8821C BIT(27) #define BIT_BD_HCI_SEL_8821C BIT(26) @@ -1670,16 +2463,27 @@ #define BIT_SHIFT_VENDOR_ID_8821C 16 #define BIT_MASK_VENDOR_ID_8821C 0xf -#define BIT_VENDOR_ID_8821C(x) (((x) & BIT_MASK_VENDOR_ID_8821C) << BIT_SHIFT_VENDOR_ID_8821C) -#define BIT_GET_VENDOR_ID_8821C(x) (((x) >> BIT_SHIFT_VENDOR_ID_8821C) & BIT_MASK_VENDOR_ID_8821C) - - +#define BIT_VENDOR_ID_8821C(x) \ + (((x) & BIT_MASK_VENDOR_ID_8821C) << BIT_SHIFT_VENDOR_ID_8821C) +#define BITS_VENDOR_ID_8821C \ + (BIT_MASK_VENDOR_ID_8821C << BIT_SHIFT_VENDOR_ID_8821C) +#define BIT_CLEAR_VENDOR_ID_8821C(x) ((x) & (~BITS_VENDOR_ID_8821C)) +#define BIT_GET_VENDOR_ID_8821C(x) \ + (((x) >> BIT_SHIFT_VENDOR_ID_8821C) & BIT_MASK_VENDOR_ID_8821C) +#define BIT_SET_VENDOR_ID_8821C(x, v) \ + (BIT_CLEAR_VENDOR_ID_8821C(x) | BIT_VENDOR_ID_8821C(v)) #define BIT_SHIFT_CHIP_VER_8821C 12 #define BIT_MASK_CHIP_VER_8821C 0xf -#define BIT_CHIP_VER_8821C(x) (((x) & BIT_MASK_CHIP_VER_8821C) << BIT_SHIFT_CHIP_VER_8821C) -#define BIT_GET_CHIP_VER_8821C(x) (((x) >> BIT_SHIFT_CHIP_VER_8821C) & BIT_MASK_CHIP_VER_8821C) - +#define BIT_CHIP_VER_8821C(x) \ + (((x) & BIT_MASK_CHIP_VER_8821C) << BIT_SHIFT_CHIP_VER_8821C) +#define BITS_CHIP_VER_8821C \ + (BIT_MASK_CHIP_VER_8821C << BIT_SHIFT_CHIP_VER_8821C) +#define BIT_CLEAR_CHIP_VER_8821C(x) ((x) & (~BITS_CHIP_VER_8821C)) +#define BIT_GET_CHIP_VER_8821C(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_8821C) & BIT_MASK_CHIP_VER_8821C) +#define BIT_SET_CHIP_VER_8821C(x, v) \ + (BIT_CLEAR_CHIP_VER_8821C(x) | BIT_CHIP_VER_8821C(v)) #define BIT_BD_MAC3_8821C BIT(11) #define BIT_BD_MAC1_8821C BIT(10) @@ -1698,17 +2502,41 @@ #define BIT_SHIFT_RF_RL_ID_8821C 28 #define BIT_MASK_RF_RL_ID_8821C 0xf -#define BIT_RF_RL_ID_8821C(x) (((x) & BIT_MASK_RF_RL_ID_8821C) << BIT_SHIFT_RF_RL_ID_8821C) -#define BIT_GET_RF_RL_ID_8821C(x) (((x) >> BIT_SHIFT_RF_RL_ID_8821C) & BIT_MASK_RF_RL_ID_8821C) - +#define BIT_RF_RL_ID_8821C(x) \ + (((x) & BIT_MASK_RF_RL_ID_8821C) << BIT_SHIFT_RF_RL_ID_8821C) +#define BITS_RF_RL_ID_8821C \ + (BIT_MASK_RF_RL_ID_8821C << BIT_SHIFT_RF_RL_ID_8821C) +#define BIT_CLEAR_RF_RL_ID_8821C(x) ((x) & (~BITS_RF_RL_ID_8821C)) +#define BIT_GET_RF_RL_ID_8821C(x) \ + (((x) >> BIT_SHIFT_RF_RL_ID_8821C) & BIT_MASK_RF_RL_ID_8821C) +#define BIT_SET_RF_RL_ID_8821C(x, v) \ + (BIT_CLEAR_RF_RL_ID_8821C(x) | BIT_RF_RL_ID_8821C(v)) #define BIT_HPHY_ICFG_8821C BIT(19) #define BIT_SHIFT_SEL_0XC0_8821C 16 #define BIT_MASK_SEL_0XC0_8821C 0x3 -#define BIT_SEL_0XC0_8821C(x) (((x) & BIT_MASK_SEL_0XC0_8821C) << BIT_SHIFT_SEL_0XC0_8821C) -#define BIT_GET_SEL_0XC0_8821C(x) (((x) >> BIT_SHIFT_SEL_0XC0_8821C) & BIT_MASK_SEL_0XC0_8821C) - +#define BIT_SEL_0XC0_8821C(x) \ + (((x) & BIT_MASK_SEL_0XC0_8821C) << BIT_SHIFT_SEL_0XC0_8821C) +#define BITS_SEL_0XC0_8821C \ + (BIT_MASK_SEL_0XC0_8821C << BIT_SHIFT_SEL_0XC0_8821C) +#define BIT_CLEAR_SEL_0XC0_8821C(x) ((x) & (~BITS_SEL_0XC0_8821C)) +#define BIT_GET_SEL_0XC0_8821C(x) \ + (((x) >> BIT_SHIFT_SEL_0XC0_8821C) & BIT_MASK_SEL_0XC0_8821C) +#define BIT_SET_SEL_0XC0_8821C(x, v) \ + (BIT_CLEAR_SEL_0XC0_8821C(x) | BIT_SEL_0XC0_8821C(v)) + +#define BIT_SHIFT_HCI_SEL_V4_8821C 12 +#define BIT_MASK_HCI_SEL_V4_8821C 0x3 +#define BIT_HCI_SEL_V4_8821C(x) \ + (((x) & BIT_MASK_HCI_SEL_V4_8821C) << BIT_SHIFT_HCI_SEL_V4_8821C) +#define BITS_HCI_SEL_V4_8821C \ + (BIT_MASK_HCI_SEL_V4_8821C << BIT_SHIFT_HCI_SEL_V4_8821C) +#define BIT_CLEAR_HCI_SEL_V4_8821C(x) ((x) & (~BITS_HCI_SEL_V4_8821C)) +#define BIT_GET_HCI_SEL_V4_8821C(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V4_8821C) & BIT_MASK_HCI_SEL_V4_8821C) +#define BIT_SET_HCI_SEL_V4_8821C(x, v) \ + (BIT_CLEAR_HCI_SEL_V4_8821C(x) | BIT_HCI_SEL_V4_8821C(v)) #define BIT_USB_OPERATION_MODE_8821C BIT(10) #define BIT_BT_PDN_8821C BIT(9) @@ -1716,26 +2544,31 @@ #define BIT_WL_MODE_8821C BIT(7) #define BIT_PKG_SEL_HCI_8821C BIT(6) -#define BIT_SHIFT_HCI_SEL_8821C 4 -#define BIT_MASK_HCI_SEL_8821C 0x3 -#define BIT_HCI_SEL_8821C(x) (((x) & BIT_MASK_HCI_SEL_8821C) << BIT_SHIFT_HCI_SEL_8821C) -#define BIT_GET_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_HCI_SEL_8821C) & BIT_MASK_HCI_SEL_8821C) - - - -#define BIT_SHIFT_PAD_HCI_SEL_8821C 2 -#define BIT_MASK_PAD_HCI_SEL_8821C 0x3 -#define BIT_PAD_HCI_SEL_8821C(x) (((x) & BIT_MASK_PAD_HCI_SEL_8821C) << BIT_SHIFT_PAD_HCI_SEL_8821C) -#define BIT_GET_PAD_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_8821C) & BIT_MASK_PAD_HCI_SEL_8821C) - - +#define BIT_SHIFT_PAD_HCI_SEL_V2_8821C 3 +#define BIT_MASK_PAD_HCI_SEL_V2_8821C 0x3 +#define BIT_PAD_HCI_SEL_V2_8821C(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V2_8821C) \ + << BIT_SHIFT_PAD_HCI_SEL_V2_8821C) +#define BITS_PAD_HCI_SEL_V2_8821C \ + (BIT_MASK_PAD_HCI_SEL_V2_8821C << BIT_SHIFT_PAD_HCI_SEL_V2_8821C) +#define BIT_CLEAR_PAD_HCI_SEL_V2_8821C(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8821C)) +#define BIT_GET_PAD_HCI_SEL_V2_8821C(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8821C) & \ + BIT_MASK_PAD_HCI_SEL_V2_8821C) +#define BIT_SET_PAD_HCI_SEL_V2_8821C(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V2_8821C(x) | BIT_PAD_HCI_SEL_V2_8821C(v)) #define BIT_SHIFT_EFS_HCI_SEL_8821C 0 #define BIT_MASK_EFS_HCI_SEL_8821C 0x3 -#define BIT_EFS_HCI_SEL_8821C(x) (((x) & BIT_MASK_EFS_HCI_SEL_8821C) << BIT_SHIFT_EFS_HCI_SEL_8821C) -#define BIT_GET_EFS_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_8821C) & BIT_MASK_EFS_HCI_SEL_8821C) - - +#define BIT_EFS_HCI_SEL_8821C(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_8821C) << BIT_SHIFT_EFS_HCI_SEL_8821C) +#define BITS_EFS_HCI_SEL_8821C \ + (BIT_MASK_EFS_HCI_SEL_8821C << BIT_SHIFT_EFS_HCI_SEL_8821C) +#define BIT_CLEAR_EFS_HCI_SEL_8821C(x) ((x) & (~BITS_EFS_HCI_SEL_8821C)) +#define BIT_GET_EFS_HCI_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_8821C) & BIT_MASK_EFS_HCI_SEL_8821C) +#define BIT_SET_EFS_HCI_SEL_8821C(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_8821C(x) | BIT_EFS_HCI_SEL_8821C(v)) /* 2 REG_SYS_STATUS2_8821C */ #define BIT_SIO_ALDN_8821C BIT(19) @@ -1745,70 +2578,161 @@ #define BIT_SHIFT_EPVID1_8821C 8 #define BIT_MASK_EPVID1_8821C 0xff -#define BIT_EPVID1_8821C(x) (((x) & BIT_MASK_EPVID1_8821C) << BIT_SHIFT_EPVID1_8821C) -#define BIT_GET_EPVID1_8821C(x) (((x) >> BIT_SHIFT_EPVID1_8821C) & BIT_MASK_EPVID1_8821C) - - +#define BIT_EPVID1_8821C(x) \ + (((x) & BIT_MASK_EPVID1_8821C) << BIT_SHIFT_EPVID1_8821C) +#define BITS_EPVID1_8821C (BIT_MASK_EPVID1_8821C << BIT_SHIFT_EPVID1_8821C) +#define BIT_CLEAR_EPVID1_8821C(x) ((x) & (~BITS_EPVID1_8821C)) +#define BIT_GET_EPVID1_8821C(x) \ + (((x) >> BIT_SHIFT_EPVID1_8821C) & BIT_MASK_EPVID1_8821C) +#define BIT_SET_EPVID1_8821C(x, v) \ + (BIT_CLEAR_EPVID1_8821C(x) | BIT_EPVID1_8821C(v)) #define BIT_SHIFT_EPVID0_8821C 0 #define BIT_MASK_EPVID0_8821C 0xff -#define BIT_EPVID0_8821C(x) (((x) & BIT_MASK_EPVID0_8821C) << BIT_SHIFT_EPVID0_8821C) -#define BIT_GET_EPVID0_8821C(x) (((x) >> BIT_SHIFT_EPVID0_8821C) & BIT_MASK_EPVID0_8821C) - - +#define BIT_EPVID0_8821C(x) \ + (((x) & BIT_MASK_EPVID0_8821C) << BIT_SHIFT_EPVID0_8821C) +#define BITS_EPVID0_8821C (BIT_MASK_EPVID0_8821C << BIT_SHIFT_EPVID0_8821C) +#define BIT_CLEAR_EPVID0_8821C(x) ((x) & (~BITS_EPVID0_8821C)) +#define BIT_GET_EPVID0_8821C(x) \ + (((x) >> BIT_SHIFT_EPVID0_8821C) & BIT_MASK_EPVID0_8821C) +#define BIT_SET_EPVID0_8821C(x, v) \ + (BIT_CLEAR_EPVID0_8821C(x) | BIT_EPVID0_8821C(v)) /* 2 REG_SYS_CFG2_8821C */ -#define BIT_HCI_SEL_EMBEDED_8821C BIT(8) +#define BIT_HCI_SEL_EMBEDDED_8821C BIT(8) #define BIT_SHIFT_HW_ID_8821C 0 #define BIT_MASK_HW_ID_8821C 0xff -#define BIT_HW_ID_8821C(x) (((x) & BIT_MASK_HW_ID_8821C) << BIT_SHIFT_HW_ID_8821C) -#define BIT_GET_HW_ID_8821C(x) (((x) >> BIT_SHIFT_HW_ID_8821C) & BIT_MASK_HW_ID_8821C) - - +#define BIT_HW_ID_8821C(x) \ + (((x) & BIT_MASK_HW_ID_8821C) << BIT_SHIFT_HW_ID_8821C) +#define BITS_HW_ID_8821C (BIT_MASK_HW_ID_8821C << BIT_SHIFT_HW_ID_8821C) +#define BIT_CLEAR_HW_ID_8821C(x) ((x) & (~BITS_HW_ID_8821C)) +#define BIT_GET_HW_ID_8821C(x) \ + (((x) >> BIT_SHIFT_HW_ID_8821C) & BIT_MASK_HW_ID_8821C) +#define BIT_SET_HW_ID_8821C(x, v) \ + (BIT_CLEAR_HW_ID_8821C(x) | BIT_HW_ID_8821C(v)) /* 2 REG_SYS_CFG3_8821C */ -#define BIT_PWC_MA33V_8821C BIT(15) -#define BIT_PWC_MA12V_8821C BIT(14) -#define BIT_PWC_MD12V_8821C BIT(13) -#define BIT_PWC_PD12V_8821C BIT(12) -#define BIT_PWC_UD12V_8821C BIT(11) -#define BIT_ISO_MA2MD_8821C BIT(1) -#define BIT_ISO_MD2PP_8821C BIT(0) -/* 2 REG_SYS_CFG4_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_SYS_CFG5_8821C */ -#define BIT_LPS_STATUS_8821C BIT(3) -#define BIT_HCI_TXDMA_BUSY_8821C BIT(2) -#define BIT_HCI_TXDMA_ALLOW_8821C BIT(1) -#define BIT_FW_CTRL_HCI_TXDMA_EN_8821C BIT(0) +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_CPU_DMEM_CON_8821C */ -#define BIT_WDT_AUTO_MODE_8821C BIT(22) -#define BIT_WDT_PLATFORM_EN_8821C BIT(21) -#define BIT_WDT_CPU_EN_8821C BIT(20) -#define BIT_WDT_OPT_IOWRAPPER_8821C BIT(19) -#define BIT_ANA_PORT_IDLE_8821C BIT(18) -#define BIT_MAC_PORT_IDLE_8821C BIT(17) -#define BIT_WL_PLATFORM_RST_8821C BIT(16) -#define BIT_WL_SECURITY_CLK_8821C BIT(15) +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_SYS_CFG5_8821C */ +#define BIT_LPS_STATUS_8821C BIT(3) +#define BIT_HCI_TXDMA_BUSY_8821C BIT(2) +#define BIT_HCI_TXDMA_ALLOW_8821C BIT(1) +#define BIT_FW_CTRL_HCI_TXDMA_EN_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_CPU_DMEM_CON_8821C */ +#define BIT_WDT_AUTO_MODE_8821C BIT(22) +#define BIT_WDT_PLATFORM_EN_8821C BIT(21) +#define BIT_WDT_CPU_EN_8821C BIT(20) +#define BIT_WDT_OPT_IOWRAPPER_8821C BIT(19) +#define BIT_ANA_PORT_IDLE_8821C BIT(18) +#define BIT_MAC_PORT_IDLE_8821C BIT(17) +#define BIT_WL_PLATFORM_RST_8821C BIT(16) +#define BIT_WL_SECURITY_CLK_8821C BIT(15) #define BIT_SHIFT_CPU_DMEM_CON_8821C 0 #define BIT_MASK_CPU_DMEM_CON_8821C 0xff -#define BIT_CPU_DMEM_CON_8821C(x) (((x) & BIT_MASK_CPU_DMEM_CON_8821C) << BIT_SHIFT_CPU_DMEM_CON_8821C) -#define BIT_GET_CPU_DMEM_CON_8821C(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8821C) & BIT_MASK_CPU_DMEM_CON_8821C) - +#define BIT_CPU_DMEM_CON_8821C(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON_8821C) << BIT_SHIFT_CPU_DMEM_CON_8821C) +#define BITS_CPU_DMEM_CON_8821C \ + (BIT_MASK_CPU_DMEM_CON_8821C << BIT_SHIFT_CPU_DMEM_CON_8821C) +#define BIT_CLEAR_CPU_DMEM_CON_8821C(x) ((x) & (~BITS_CPU_DMEM_CON_8821C)) +#define BIT_GET_CPU_DMEM_CON_8821C(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON_8821C) & BIT_MASK_CPU_DMEM_CON_8821C) +#define BIT_SET_CPU_DMEM_CON_8821C(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON_8821C(x) | BIT_CPU_DMEM_CON_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_BOOT_REASON_8821C */ -#define BIT_SHIFT_BOOT_REASON_8821C 0 -#define BIT_MASK_BOOT_REASON_8821C 0x7 -#define BIT_BOOT_REASON_8821C(x) (((x) & BIT_MASK_BOOT_REASON_8821C) << BIT_SHIFT_BOOT_REASON_8821C) -#define BIT_GET_BOOT_REASON_8821C(x) (((x) >> BIT_SHIFT_BOOT_REASON_8821C) & BIT_MASK_BOOT_REASON_8821C) +#define BIT_SHIFT_BOOT_REASON_V1_8821C 0 +#define BIT_MASK_BOOT_REASON_V1_8821C 0x7 +#define BIT_BOOT_REASON_V1_8821C(x) \ + (((x) & BIT_MASK_BOOT_REASON_V1_8821C) \ + << BIT_SHIFT_BOOT_REASON_V1_8821C) +#define BITS_BOOT_REASON_V1_8821C \ + (BIT_MASK_BOOT_REASON_V1_8821C << BIT_SHIFT_BOOT_REASON_V1_8821C) +#define BIT_CLEAR_BOOT_REASON_V1_8821C(x) ((x) & (~BITS_BOOT_REASON_V1_8821C)) +#define BIT_GET_BOOT_REASON_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BOOT_REASON_V1_8821C) & \ + BIT_MASK_BOOT_REASON_V1_8821C) +#define BIT_SET_BOOT_REASON_V1_8821C(x, v) \ + (BIT_CLEAR_BOOT_REASON_V1_8821C(x) | BIT_BOOT_REASON_V1_8821C(v)) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NFCPAD_CTRL_8821C */ #define BIT_PAD_SHUTDW_8821C BIT(18) @@ -1821,24 +2745,41 @@ #define BIT_SHIFT_NFCPAD_IO_SEL_8821C 8 #define BIT_MASK_NFCPAD_IO_SEL_8821C 0xf -#define BIT_NFCPAD_IO_SEL_8821C(x) (((x) & BIT_MASK_NFCPAD_IO_SEL_8821C) << BIT_SHIFT_NFCPAD_IO_SEL_8821C) -#define BIT_GET_NFCPAD_IO_SEL_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8821C) & BIT_MASK_NFCPAD_IO_SEL_8821C) - - +#define BIT_NFCPAD_IO_SEL_8821C(x) \ + (((x) & BIT_MASK_NFCPAD_IO_SEL_8821C) << BIT_SHIFT_NFCPAD_IO_SEL_8821C) +#define BITS_NFCPAD_IO_SEL_8821C \ + (BIT_MASK_NFCPAD_IO_SEL_8821C << BIT_SHIFT_NFCPAD_IO_SEL_8821C) +#define BIT_CLEAR_NFCPAD_IO_SEL_8821C(x) ((x) & (~BITS_NFCPAD_IO_SEL_8821C)) +#define BIT_GET_NFCPAD_IO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8821C) & BIT_MASK_NFCPAD_IO_SEL_8821C) +#define BIT_SET_NFCPAD_IO_SEL_8821C(x, v) \ + (BIT_CLEAR_NFCPAD_IO_SEL_8821C(x) | BIT_NFCPAD_IO_SEL_8821C(v)) #define BIT_SHIFT_NFCPAD_OUT_8821C 4 #define BIT_MASK_NFCPAD_OUT_8821C 0xf -#define BIT_NFCPAD_OUT_8821C(x) (((x) & BIT_MASK_NFCPAD_OUT_8821C) << BIT_SHIFT_NFCPAD_OUT_8821C) -#define BIT_GET_NFCPAD_OUT_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8821C) & BIT_MASK_NFCPAD_OUT_8821C) - - +#define BIT_NFCPAD_OUT_8821C(x) \ + (((x) & BIT_MASK_NFCPAD_OUT_8821C) << BIT_SHIFT_NFCPAD_OUT_8821C) +#define BITS_NFCPAD_OUT_8821C \ + (BIT_MASK_NFCPAD_OUT_8821C << BIT_SHIFT_NFCPAD_OUT_8821C) +#define BIT_CLEAR_NFCPAD_OUT_8821C(x) ((x) & (~BITS_NFCPAD_OUT_8821C)) +#define BIT_GET_NFCPAD_OUT_8821C(x) \ + (((x) >> BIT_SHIFT_NFCPAD_OUT_8821C) & BIT_MASK_NFCPAD_OUT_8821C) +#define BIT_SET_NFCPAD_OUT_8821C(x, v) \ + (BIT_CLEAR_NFCPAD_OUT_8821C(x) | BIT_NFCPAD_OUT_8821C(v)) #define BIT_SHIFT_NFCPAD_IN_8821C 0 #define BIT_MASK_NFCPAD_IN_8821C 0xf -#define BIT_NFCPAD_IN_8821C(x) (((x) & BIT_MASK_NFCPAD_IN_8821C) << BIT_SHIFT_NFCPAD_IN_8821C) -#define BIT_GET_NFCPAD_IN_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8821C) & BIT_MASK_NFCPAD_IN_8821C) - +#define BIT_NFCPAD_IN_8821C(x) \ + (((x) & BIT_MASK_NFCPAD_IN_8821C) << BIT_SHIFT_NFCPAD_IN_8821C) +#define BITS_NFCPAD_IN_8821C \ + (BIT_MASK_NFCPAD_IN_8821C << BIT_SHIFT_NFCPAD_IN_8821C) +#define BIT_CLEAR_NFCPAD_IN_8821C(x) ((x) & (~BITS_NFCPAD_IN_8821C)) +#define BIT_GET_NFCPAD_IN_8821C(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IN_8821C) & BIT_MASK_NFCPAD_IN_8821C) +#define BIT_SET_NFCPAD_IN_8821C(x, v) \ + (BIT_CLEAR_NFCPAD_IN_8821C(x) | BIT_NFCPAD_IN_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_HIMR2_8821C */ #define BIT_BCNDMAINT_P4_MSK_8821C BIT(31) @@ -1935,42 +2876,45 @@ /* 2 REG_SW_MDIO_8821C */ #define BIT_DIS_TIMEOUT_IO_8821C BIT(24) -/* 2 REG_SW_FLUSH_8821C */ -#define BIT_FLUSH_HOLDN_EN_8821C BIT(25) -#define BIT_FLUSH_WR_EN_8821C BIT(24) -#define BIT_SW_FLASH_CONTROL_8821C BIT(23) -#define BIT_SW_FLASH_WEN_E_8821C BIT(19) -#define BIT_SW_FLASH_HOLDN_E_8821C BIT(18) -#define BIT_SW_FLASH_SO_E_8821C BIT(17) -#define BIT_SW_FLASH_SI_E_8821C BIT(16) -#define BIT_SW_FLASH_SK_O_8821C BIT(13) -#define BIT_SW_FLASH_CEN_O_8821C BIT(12) -#define BIT_SW_FLASH_WEN_O_8821C BIT(11) -#define BIT_SW_FLASH_HOLDN_O_8821C BIT(10) -#define BIT_SW_FLASH_SO_O_8821C BIT(9) -#define BIT_SW_FLASH_SI_O_8821C BIT(8) -#define BIT_SW_FLASH_WEN_I_8821C BIT(3) -#define BIT_SW_FLASH_HOLDN_I_8821C BIT(2) -#define BIT_SW_FLASH_SO_I_8821C BIT(1) -#define BIT_SW_FLASH_SI_I_8821C BIT(0) +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_H2C_PKT_READADDR_8821C */ #define BIT_SHIFT_H2C_PKT_READADDR_8821C 0 #define BIT_MASK_H2C_PKT_READADDR_8821C 0x3ffff -#define BIT_H2C_PKT_READADDR_8821C(x) (((x) & BIT_MASK_H2C_PKT_READADDR_8821C) << BIT_SHIFT_H2C_PKT_READADDR_8821C) -#define BIT_GET_H2C_PKT_READADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8821C) & BIT_MASK_H2C_PKT_READADDR_8821C) - - +#define BIT_H2C_PKT_READADDR_8821C(x) \ + (((x) & BIT_MASK_H2C_PKT_READADDR_8821C) \ + << BIT_SHIFT_H2C_PKT_READADDR_8821C) +#define BITS_H2C_PKT_READADDR_8821C \ + (BIT_MASK_H2C_PKT_READADDR_8821C << BIT_SHIFT_H2C_PKT_READADDR_8821C) +#define BIT_CLEAR_H2C_PKT_READADDR_8821C(x) \ + ((x) & (~BITS_H2C_PKT_READADDR_8821C)) +#define BIT_GET_H2C_PKT_READADDR_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8821C) & \ + BIT_MASK_H2C_PKT_READADDR_8821C) +#define BIT_SET_H2C_PKT_READADDR_8821C(x, v) \ + (BIT_CLEAR_H2C_PKT_READADDR_8821C(x) | BIT_H2C_PKT_READADDR_8821C(v)) /* 2 REG_H2C_PKT_WRITEADDR_8821C */ #define BIT_SHIFT_H2C_PKT_WRITEADDR_8821C 0 #define BIT_MASK_H2C_PKT_WRITEADDR_8821C 0x3ffff -#define BIT_H2C_PKT_WRITEADDR_8821C(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8821C) << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) -#define BIT_GET_H2C_PKT_WRITEADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) & BIT_MASK_H2C_PKT_WRITEADDR_8821C) - - +#define BIT_H2C_PKT_WRITEADDR_8821C(x) \ + (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8821C) \ + << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) +#define BITS_H2C_PKT_WRITEADDR_8821C \ + (BIT_MASK_H2C_PKT_WRITEADDR_8821C << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) +#define BIT_CLEAR_H2C_PKT_WRITEADDR_8821C(x) \ + ((x) & (~BITS_H2C_PKT_WRITEADDR_8821C)) +#define BIT_GET_H2C_PKT_WRITEADDR_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) & \ + BIT_MASK_H2C_PKT_WRITEADDR_8821C) +#define BIT_SET_H2C_PKT_WRITEADDR_8821C(x, v) \ + (BIT_CLEAR_H2C_PKT_WRITEADDR_8821C(x) | BIT_H2C_PKT_WRITEADDR_8821C(v)) /* 2 REG_MEM_PWR_CRTL_8821C */ #define BIT_MEM_BB_SD_8821C BIT(17) @@ -1987,77 +2931,173 @@ #define BIT_MEM_WLMCU_LS_8821C BIT(1) #define BIT_MEM_WLMCU_DS_8821C BIT(0) -/* 2 REG_FW_DBG0_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG0_8821C 0 -#define BIT_MASK_FW_DBG0_8821C 0xffffffffL -#define BIT_FW_DBG0_8821C(x) (((x) & BIT_MASK_FW_DBG0_8821C) << BIT_SHIFT_FW_DBG0_8821C) -#define BIT_GET_FW_DBG0_8821C(x) (((x) >> BIT_SHIFT_FW_DBG0_8821C) & BIT_MASK_FW_DBG0_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG1_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG1_8821C 0 -#define BIT_MASK_FW_DBG1_8821C 0xffffffffL -#define BIT_FW_DBG1_8821C(x) (((x) & BIT_MASK_FW_DBG1_8821C) << BIT_SHIFT_FW_DBG1_8821C) -#define BIT_GET_FW_DBG1_8821C(x) (((x) >> BIT_SHIFT_FW_DBG1_8821C) & BIT_MASK_FW_DBG1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_FW_DBG6_8821C */ -/* 2 REG_FW_DBG2_8821C */ +#define BIT_SHIFT_FW_DBG6_8821C 0 +#define BIT_MASK_FW_DBG6_8821C 0xffffffffL +#define BIT_FW_DBG6_8821C(x) \ + (((x) & BIT_MASK_FW_DBG6_8821C) << BIT_SHIFT_FW_DBG6_8821C) +#define BITS_FW_DBG6_8821C (BIT_MASK_FW_DBG6_8821C << BIT_SHIFT_FW_DBG6_8821C) +#define BIT_CLEAR_FW_DBG6_8821C(x) ((x) & (~BITS_FW_DBG6_8821C)) +#define BIT_GET_FW_DBG6_8821C(x) \ + (((x) >> BIT_SHIFT_FW_DBG6_8821C) & BIT_MASK_FW_DBG6_8821C) +#define BIT_SET_FW_DBG6_8821C(x, v) \ + (BIT_CLEAR_FW_DBG6_8821C(x) | BIT_FW_DBG6_8821C(v)) -#define BIT_SHIFT_FW_DBG2_8821C 0 -#define BIT_MASK_FW_DBG2_8821C 0xffffffffL -#define BIT_FW_DBG2_8821C(x) (((x) & BIT_MASK_FW_DBG2_8821C) << BIT_SHIFT_FW_DBG2_8821C) -#define BIT_GET_FW_DBG2_8821C(x) (((x) >> BIT_SHIFT_FW_DBG2_8821C) & BIT_MASK_FW_DBG2_8821C) +/* 2 REG_FW_DBG7_8821C */ +#define BIT_SHIFT_FW_DBG7_8821C 0 +#define BIT_MASK_FW_DBG7_8821C 0xffffffffL +#define BIT_FW_DBG7_8821C(x) \ + (((x) & BIT_MASK_FW_DBG7_8821C) << BIT_SHIFT_FW_DBG7_8821C) +#define BITS_FW_DBG7_8821C (BIT_MASK_FW_DBG7_8821C << BIT_SHIFT_FW_DBG7_8821C) +#define BIT_CLEAR_FW_DBG7_8821C(x) ((x) & (~BITS_FW_DBG7_8821C)) +#define BIT_GET_FW_DBG7_8821C(x) \ + (((x) >> BIT_SHIFT_FW_DBG7_8821C) & BIT_MASK_FW_DBG7_8821C) +#define BIT_SET_FW_DBG7_8821C(x, v) \ + (BIT_CLEAR_FW_DBG7_8821C(x) | BIT_FW_DBG7_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG3_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG3_8821C 0 -#define BIT_MASK_FW_DBG3_8821C 0xffffffffL -#define BIT_FW_DBG3_8821C(x) (((x) & BIT_MASK_FW_DBG3_8821C) << BIT_SHIFT_FW_DBG3_8821C) -#define BIT_GET_FW_DBG3_8821C(x) (((x) >> BIT_SHIFT_FW_DBG3_8821C) & BIT_MASK_FW_DBG3_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG4_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG4_8821C 0 -#define BIT_MASK_FW_DBG4_8821C 0xffffffffL -#define BIT_FW_DBG4_8821C(x) (((x) & BIT_MASK_FW_DBG4_8821C) << BIT_SHIFT_FW_DBG4_8821C) -#define BIT_GET_FW_DBG4_8821C(x) (((x) >> BIT_SHIFT_FW_DBG4_8821C) & BIT_MASK_FW_DBG4_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG5_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG5_8821C 0 -#define BIT_MASK_FW_DBG5_8821C 0xffffffffL -#define BIT_FW_DBG5_8821C(x) (((x) & BIT_MASK_FW_DBG5_8821C) << BIT_SHIFT_FW_DBG5_8821C) -#define BIT_GET_FW_DBG5_8821C(x) (((x) >> BIT_SHIFT_FW_DBG5_8821C) & BIT_MASK_FW_DBG5_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG6_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG6_8821C 0 -#define BIT_MASK_FW_DBG6_8821C 0xffffffffL -#define BIT_FW_DBG6_8821C(x) (((x) & BIT_MASK_FW_DBG6_8821C) << BIT_SHIFT_FW_DBG6_8821C) -#define BIT_GET_FW_DBG6_8821C(x) (((x) >> BIT_SHIFT_FW_DBG6_8821C) & BIT_MASK_FW_DBG6_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FW_DBG7_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_FW_DBG7_8821C 0 -#define BIT_MASK_FW_DBG7_8821C 0xffffffffL -#define BIT_FW_DBG7_8821C(x) (((x) & BIT_MASK_FW_DBG7_8821C) << BIT_SHIFT_FW_DBG7_8821C) -#define BIT_GET_FW_DBG7_8821C(x) (((x) >> BIT_SHIFT_FW_DBG7_8821C) & BIT_MASK_FW_DBG7_8821C) +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -2065,24 +3105,38 @@ #define BIT_SHIFT_LBMODE_8821C 24 #define BIT_MASK_LBMODE_8821C 0x1f -#define BIT_LBMODE_8821C(x) (((x) & BIT_MASK_LBMODE_8821C) << BIT_SHIFT_LBMODE_8821C) -#define BIT_GET_LBMODE_8821C(x) (((x) >> BIT_SHIFT_LBMODE_8821C) & BIT_MASK_LBMODE_8821C) - - +#define BIT_LBMODE_8821C(x) \ + (((x) & BIT_MASK_LBMODE_8821C) << BIT_SHIFT_LBMODE_8821C) +#define BITS_LBMODE_8821C (BIT_MASK_LBMODE_8821C << BIT_SHIFT_LBMODE_8821C) +#define BIT_CLEAR_LBMODE_8821C(x) ((x) & (~BITS_LBMODE_8821C)) +#define BIT_GET_LBMODE_8821C(x) \ + (((x) >> BIT_SHIFT_LBMODE_8821C) & BIT_MASK_LBMODE_8821C) +#define BIT_SET_LBMODE_8821C(x, v) \ + (BIT_CLEAR_LBMODE_8821C(x) | BIT_LBMODE_8821C(v)) #define BIT_SHIFT_NETYPE1_8821C 18 #define BIT_MASK_NETYPE1_8821C 0x3 -#define BIT_NETYPE1_8821C(x) (((x) & BIT_MASK_NETYPE1_8821C) << BIT_SHIFT_NETYPE1_8821C) -#define BIT_GET_NETYPE1_8821C(x) (((x) >> BIT_SHIFT_NETYPE1_8821C) & BIT_MASK_NETYPE1_8821C) - - +#define BIT_NETYPE1_8821C(x) \ + (((x) & BIT_MASK_NETYPE1_8821C) << BIT_SHIFT_NETYPE1_8821C) +#define BITS_NETYPE1_8821C (BIT_MASK_NETYPE1_8821C << BIT_SHIFT_NETYPE1_8821C) +#define BIT_CLEAR_NETYPE1_8821C(x) ((x) & (~BITS_NETYPE1_8821C)) +#define BIT_GET_NETYPE1_8821C(x) \ + (((x) >> BIT_SHIFT_NETYPE1_8821C) & BIT_MASK_NETYPE1_8821C) +#define BIT_SET_NETYPE1_8821C(x, v) \ + (BIT_CLEAR_NETYPE1_8821C(x) | BIT_NETYPE1_8821C(v)) #define BIT_SHIFT_NETYPE0_8821C 16 #define BIT_MASK_NETYPE0_8821C 0x3 -#define BIT_NETYPE0_8821C(x) (((x) & BIT_MASK_NETYPE0_8821C) << BIT_SHIFT_NETYPE0_8821C) -#define BIT_GET_NETYPE0_8821C(x) (((x) >> BIT_SHIFT_NETYPE0_8821C) & BIT_MASK_NETYPE0_8821C) - - +#define BIT_NETYPE0_8821C(x) \ + (((x) & BIT_MASK_NETYPE0_8821C) << BIT_SHIFT_NETYPE0_8821C) +#define BITS_NETYPE0_8821C (BIT_MASK_NETYPE0_8821C << BIT_SHIFT_NETYPE0_8821C) +#define BIT_CLEAR_NETYPE0_8821C(x) ((x) & (~BITS_NETYPE0_8821C)) +#define BIT_GET_NETYPE0_8821C(x) \ + (((x) >> BIT_SHIFT_NETYPE0_8821C) & BIT_MASK_NETYPE0_8821C) +#define BIT_SET_NETYPE0_8821C(x, v) \ + (BIT_CLEAR_NETYPE0_8821C(x) | BIT_NETYPE0_8821C(v)) + +#define BIT_COUNTER_STS_EN_8821C BIT(13) #define BIT_I2C_MAILBOX_EN_8821C BIT(12) #define BIT_SHCUT_EN_8821C BIT(11) #define BIT_32K_CAL_TMR_EN_8821C BIT(10) @@ -2097,62 +3151,127 @@ #define BIT_HCI_RXDMA_EN_8821C BIT(1) #define BIT_HCI_TXDMA_EN_8821C BIT(0) -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_PG_SIZE_8821C */ + +#define BIT_SHIFT_DBG_FIFO_SEL_8821C 16 +#define BIT_MASK_DBG_FIFO_SEL_8821C 0xff +#define BIT_DBG_FIFO_SEL_8821C(x) \ + (((x) & BIT_MASK_DBG_FIFO_SEL_8821C) << BIT_SHIFT_DBG_FIFO_SEL_8821C) +#define BITS_DBG_FIFO_SEL_8821C \ + (BIT_MASK_DBG_FIFO_SEL_8821C << BIT_SHIFT_DBG_FIFO_SEL_8821C) +#define BIT_CLEAR_DBG_FIFO_SEL_8821C(x) ((x) & (~BITS_DBG_FIFO_SEL_8821C)) +#define BIT_GET_DBG_FIFO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_DBG_FIFO_SEL_8821C) & BIT_MASK_DBG_FIFO_SEL_8821C) +#define BIT_SET_DBG_FIFO_SEL_8821C(x, v) \ + (BIT_CLEAR_DBG_FIFO_SEL_8821C(x) | BIT_DBG_FIFO_SEL_8821C(v)) /* 2 REG_PKT_BUFF_ACCESS_CTRL_8821C */ #define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C 0 #define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C 0xff -#define BIT_PKT_BUFF_ACCESS_CTRL_8821C(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) -#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8821C(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) - - +#define BIT_PKT_BUFF_ACCESS_CTRL_8821C(x) \ + (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) +#define BITS_PKT_BUFF_ACCESS_CTRL_8821C \ + (BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) +#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8821C(x) \ + ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8821C)) +#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8821C(x) \ + (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) & \ + BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) +#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8821C(x, v) \ + (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8821C(x) | \ + BIT_PKT_BUFF_ACCESS_CTRL_8821C(v)) /* 2 REG_TSF_CLK_STATE_8821C */ #define BIT_TSF_CLK_STABLE_8821C BIT(15) /* 2 REG_TXDMA_PQ_MAP_8821C */ +#define BIT_SHIFT_TXDMA_H2C_MAP_8821C 16 +#define BIT_MASK_TXDMA_H2C_MAP_8821C 0x3 +#define BIT_TXDMA_H2C_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_H2C_MAP_8821C) << BIT_SHIFT_TXDMA_H2C_MAP_8821C) +#define BITS_TXDMA_H2C_MAP_8821C \ + (BIT_MASK_TXDMA_H2C_MAP_8821C << BIT_SHIFT_TXDMA_H2C_MAP_8821C) +#define BIT_CLEAR_TXDMA_H2C_MAP_8821C(x) ((x) & (~BITS_TXDMA_H2C_MAP_8821C)) +#define BIT_GET_TXDMA_H2C_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8821C) & BIT_MASK_TXDMA_H2C_MAP_8821C) +#define BIT_SET_TXDMA_H2C_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_H2C_MAP_8821C(x) | BIT_TXDMA_H2C_MAP_8821C(v)) + #define BIT_SHIFT_TXDMA_HIQ_MAP_8821C 14 #define BIT_MASK_TXDMA_HIQ_MAP_8821C 0x3 -#define BIT_TXDMA_HIQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8821C) << BIT_SHIFT_TXDMA_HIQ_MAP_8821C) -#define BIT_GET_TXDMA_HIQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8821C) & BIT_MASK_TXDMA_HIQ_MAP_8821C) - - +#define BIT_TXDMA_HIQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_8821C) << BIT_SHIFT_TXDMA_HIQ_MAP_8821C) +#define BITS_TXDMA_HIQ_MAP_8821C \ + (BIT_MASK_TXDMA_HIQ_MAP_8821C << BIT_SHIFT_TXDMA_HIQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_HIQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8821C)) +#define BIT_GET_TXDMA_HIQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8821C) & BIT_MASK_TXDMA_HIQ_MAP_8821C) +#define BIT_SET_TXDMA_HIQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_8821C(x) | BIT_TXDMA_HIQ_MAP_8821C(v)) #define BIT_SHIFT_TXDMA_MGQ_MAP_8821C 12 #define BIT_MASK_TXDMA_MGQ_MAP_8821C 0x3 -#define BIT_TXDMA_MGQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8821C) << BIT_SHIFT_TXDMA_MGQ_MAP_8821C) -#define BIT_GET_TXDMA_MGQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8821C) & BIT_MASK_TXDMA_MGQ_MAP_8821C) - - +#define BIT_TXDMA_MGQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_8821C) << BIT_SHIFT_TXDMA_MGQ_MAP_8821C) +#define BITS_TXDMA_MGQ_MAP_8821C \ + (BIT_MASK_TXDMA_MGQ_MAP_8821C << BIT_SHIFT_TXDMA_MGQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_MGQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8821C)) +#define BIT_GET_TXDMA_MGQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8821C) & BIT_MASK_TXDMA_MGQ_MAP_8821C) +#define BIT_SET_TXDMA_MGQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_8821C(x) | BIT_TXDMA_MGQ_MAP_8821C(v)) #define BIT_SHIFT_TXDMA_BKQ_MAP_8821C 10 #define BIT_MASK_TXDMA_BKQ_MAP_8821C 0x3 -#define BIT_TXDMA_BKQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8821C) << BIT_SHIFT_TXDMA_BKQ_MAP_8821C) -#define BIT_GET_TXDMA_BKQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8821C) & BIT_MASK_TXDMA_BKQ_MAP_8821C) - - +#define BIT_TXDMA_BKQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_8821C) << BIT_SHIFT_TXDMA_BKQ_MAP_8821C) +#define BITS_TXDMA_BKQ_MAP_8821C \ + (BIT_MASK_TXDMA_BKQ_MAP_8821C << BIT_SHIFT_TXDMA_BKQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_BKQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8821C)) +#define BIT_GET_TXDMA_BKQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8821C) & BIT_MASK_TXDMA_BKQ_MAP_8821C) +#define BIT_SET_TXDMA_BKQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_8821C(x) | BIT_TXDMA_BKQ_MAP_8821C(v)) #define BIT_SHIFT_TXDMA_BEQ_MAP_8821C 8 #define BIT_MASK_TXDMA_BEQ_MAP_8821C 0x3 -#define BIT_TXDMA_BEQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8821C) << BIT_SHIFT_TXDMA_BEQ_MAP_8821C) -#define BIT_GET_TXDMA_BEQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8821C) & BIT_MASK_TXDMA_BEQ_MAP_8821C) - - +#define BIT_TXDMA_BEQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_8821C) << BIT_SHIFT_TXDMA_BEQ_MAP_8821C) +#define BITS_TXDMA_BEQ_MAP_8821C \ + (BIT_MASK_TXDMA_BEQ_MAP_8821C << BIT_SHIFT_TXDMA_BEQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_BEQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8821C)) +#define BIT_GET_TXDMA_BEQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8821C) & BIT_MASK_TXDMA_BEQ_MAP_8821C) +#define BIT_SET_TXDMA_BEQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_8821C(x) | BIT_TXDMA_BEQ_MAP_8821C(v)) #define BIT_SHIFT_TXDMA_VIQ_MAP_8821C 6 #define BIT_MASK_TXDMA_VIQ_MAP_8821C 0x3 -#define BIT_TXDMA_VIQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8821C) << BIT_SHIFT_TXDMA_VIQ_MAP_8821C) -#define BIT_GET_TXDMA_VIQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8821C) & BIT_MASK_TXDMA_VIQ_MAP_8821C) - - +#define BIT_TXDMA_VIQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_8821C) << BIT_SHIFT_TXDMA_VIQ_MAP_8821C) +#define BITS_TXDMA_VIQ_MAP_8821C \ + (BIT_MASK_TXDMA_VIQ_MAP_8821C << BIT_SHIFT_TXDMA_VIQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_VIQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8821C)) +#define BIT_GET_TXDMA_VIQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8821C) & BIT_MASK_TXDMA_VIQ_MAP_8821C) +#define BIT_SET_TXDMA_VIQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_8821C(x) | BIT_TXDMA_VIQ_MAP_8821C(v)) #define BIT_SHIFT_TXDMA_VOQ_MAP_8821C 4 #define BIT_MASK_TXDMA_VOQ_MAP_8821C 0x3 -#define BIT_TXDMA_VOQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8821C) << BIT_SHIFT_TXDMA_VOQ_MAP_8821C) -#define BIT_GET_TXDMA_VOQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8821C) & BIT_MASK_TXDMA_VOQ_MAP_8821C) - +#define BIT_TXDMA_VOQ_MAP_8821C(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_8821C) << BIT_SHIFT_TXDMA_VOQ_MAP_8821C) +#define BITS_TXDMA_VOQ_MAP_8821C \ + (BIT_MASK_TXDMA_VOQ_MAP_8821C << BIT_SHIFT_TXDMA_VOQ_MAP_8821C) +#define BIT_CLEAR_TXDMA_VOQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8821C)) +#define BIT_GET_TXDMA_VOQ_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8821C) & BIT_MASK_TXDMA_VOQ_MAP_8821C) +#define BIT_SET_TXDMA_VOQ_MAP_8821C(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_8821C(x) | BIT_TXDMA_VOQ_MAP_8821C(v)) #define BIT_RXDMA_AGG_EN_8821C BIT(2) #define BIT_RXSHFT_EN_8821C BIT(1) @@ -2164,17 +3283,17 @@ #define BIT_SHIFT_RXFFOVFL_RSV_V2_8821C 8 #define BIT_MASK_RXFFOVFL_RSV_V2_8821C 0xf -#define BIT_RXFFOVFL_RSV_V2_8821C(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8821C) << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) -#define BIT_GET_RXFFOVFL_RSV_V2_8821C(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) & BIT_MASK_RXFFOVFL_RSV_V2_8821C) - - - -#define BIT_SHIFT_TXPKTBUF_PGBNDY_8821C 0 -#define BIT_MASK_TXPKTBUF_PGBNDY_8821C 0xff -#define BIT_TXPKTBUF_PGBNDY_8821C(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8821C) << BIT_SHIFT_TXPKTBUF_PGBNDY_8821C) -#define BIT_GET_TXPKTBUF_PGBNDY_8821C(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8821C) & BIT_MASK_TXPKTBUF_PGBNDY_8821C) - - +#define BIT_RXFFOVFL_RSV_V2_8821C(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8821C) \ + << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) +#define BITS_RXFFOVFL_RSV_V2_8821C \ + (BIT_MASK_RXFFOVFL_RSV_V2_8821C << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) +#define BIT_CLEAR_RXFFOVFL_RSV_V2_8821C(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8821C)) +#define BIT_GET_RXFFOVFL_RSV_V2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) & \ + BIT_MASK_RXFFOVFL_RSV_V2_8821C) +#define BIT_SET_RXFFOVFL_RSV_V2_8821C(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2_8821C(x) | BIT_RXFFOVFL_RSV_V2_8821C(v)) /* 2 REG_PTA_I2C_MBOX_8821C */ @@ -2182,24 +3301,44 @@ #define BIT_SHIFT_I2C_M_STATUS_8821C 8 #define BIT_MASK_I2C_M_STATUS_8821C 0xf -#define BIT_I2C_M_STATUS_8821C(x) (((x) & BIT_MASK_I2C_M_STATUS_8821C) << BIT_SHIFT_I2C_M_STATUS_8821C) -#define BIT_GET_I2C_M_STATUS_8821C(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8821C) & BIT_MASK_I2C_M_STATUS_8821C) - - +#define BIT_I2C_M_STATUS_8821C(x) \ + (((x) & BIT_MASK_I2C_M_STATUS_8821C) << BIT_SHIFT_I2C_M_STATUS_8821C) +#define BITS_I2C_M_STATUS_8821C \ + (BIT_MASK_I2C_M_STATUS_8821C << BIT_SHIFT_I2C_M_STATUS_8821C) +#define BIT_CLEAR_I2C_M_STATUS_8821C(x) ((x) & (~BITS_I2C_M_STATUS_8821C)) +#define BIT_GET_I2C_M_STATUS_8821C(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS_8821C) & BIT_MASK_I2C_M_STATUS_8821C) +#define BIT_SET_I2C_M_STATUS_8821C(x, v) \ + (BIT_CLEAR_I2C_M_STATUS_8821C(x) | BIT_I2C_M_STATUS_8821C(v)) #define BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C 4 #define BIT_MASK_I2C_M_BUS_GNT_FW_8821C 0x7 -#define BIT_I2C_M_BUS_GNT_FW_8821C(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) -#define BIT_GET_I2C_M_BUS_GNT_FW_8821C(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) - +#define BIT_I2C_M_BUS_GNT_FW_8821C(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) \ + << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) +#define BITS_I2C_M_BUS_GNT_FW_8821C \ + (BIT_MASK_I2C_M_BUS_GNT_FW_8821C << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8821C(x) \ + ((x) & (~BITS_I2C_M_BUS_GNT_FW_8821C)) +#define BIT_GET_I2C_M_BUS_GNT_FW_8821C(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) & \ + BIT_MASK_I2C_M_BUS_GNT_FW_8821C) +#define BIT_SET_I2C_M_BUS_GNT_FW_8821C(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW_8821C(x) | BIT_I2C_M_BUS_GNT_FW_8821C(v)) #define BIT_I2C_M_GNT_FW_8821C BIT(3) #define BIT_SHIFT_I2C_M_SPEED_8821C 1 #define BIT_MASK_I2C_M_SPEED_8821C 0x3 -#define BIT_I2C_M_SPEED_8821C(x) (((x) & BIT_MASK_I2C_M_SPEED_8821C) << BIT_SHIFT_I2C_M_SPEED_8821C) -#define BIT_GET_I2C_M_SPEED_8821C(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8821C) & BIT_MASK_I2C_M_SPEED_8821C) - +#define BIT_I2C_M_SPEED_8821C(x) \ + (((x) & BIT_MASK_I2C_M_SPEED_8821C) << BIT_SHIFT_I2C_M_SPEED_8821C) +#define BITS_I2C_M_SPEED_8821C \ + (BIT_MASK_I2C_M_SPEED_8821C << BIT_SHIFT_I2C_M_SPEED_8821C) +#define BIT_CLEAR_I2C_M_SPEED_8821C(x) ((x) & (~BITS_I2C_M_SPEED_8821C)) +#define BIT_GET_I2C_M_SPEED_8821C(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED_8821C) & BIT_MASK_I2C_M_SPEED_8821C) +#define BIT_SET_I2C_M_SPEED_8821C(x, v) \ + (BIT_CLEAR_I2C_M_SPEED_8821C(x) | BIT_I2C_M_SPEED_8821C(v)) #define BIT_I2C_M_UNLOCK_8821C BIT(0) @@ -2209,10 +3348,15 @@ #define BIT_SHIFT_RXFF0_BNDY_V2_8821C 0 #define BIT_MASK_RXFF0_BNDY_V2_8821C 0x3ffff -#define BIT_RXFF0_BNDY_V2_8821C(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8821C) << BIT_SHIFT_RXFF0_BNDY_V2_8821C) -#define BIT_GET_RXFF0_BNDY_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8821C) & BIT_MASK_RXFF0_BNDY_V2_8821C) - - +#define BIT_RXFF0_BNDY_V2_8821C(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2_8821C) << BIT_SHIFT_RXFF0_BNDY_V2_8821C) +#define BITS_RXFF0_BNDY_V2_8821C \ + (BIT_MASK_RXFF0_BNDY_V2_8821C << BIT_SHIFT_RXFF0_BNDY_V2_8821C) +#define BIT_CLEAR_RXFF0_BNDY_V2_8821C(x) ((x) & (~BITS_RXFF0_BNDY_V2_8821C)) +#define BIT_GET_RXFF0_BNDY_V2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8821C) & BIT_MASK_RXFF0_BNDY_V2_8821C) +#define BIT_SET_RXFF0_BNDY_V2_8821C(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2_8821C(x) | BIT_RXFF0_BNDY_V2_8821C(v)) /* 2 REG_FE1IMR_8821C */ #define BIT_FS_RXDMA2_DONE_INT_EN_8821C BIT(28) @@ -2279,10 +3423,15 @@ #define BIT_SHIFT_CPWM_MOD_8821C 24 #define BIT_MASK_CPWM_MOD_8821C 0x7f -#define BIT_CPWM_MOD_8821C(x) (((x) & BIT_MASK_CPWM_MOD_8821C) << BIT_SHIFT_CPWM_MOD_8821C) -#define BIT_GET_CPWM_MOD_8821C(x) (((x) >> BIT_SHIFT_CPWM_MOD_8821C) & BIT_MASK_CPWM_MOD_8821C) - - +#define BIT_CPWM_MOD_8821C(x) \ + (((x) & BIT_MASK_CPWM_MOD_8821C) << BIT_SHIFT_CPWM_MOD_8821C) +#define BITS_CPWM_MOD_8821C \ + (BIT_MASK_CPWM_MOD_8821C << BIT_SHIFT_CPWM_MOD_8821C) +#define BIT_CLEAR_CPWM_MOD_8821C(x) ((x) & (~BITS_CPWM_MOD_8821C)) +#define BIT_GET_CPWM_MOD_8821C(x) \ + (((x) >> BIT_SHIFT_CPWM_MOD_8821C) & BIT_MASK_CPWM_MOD_8821C) +#define BIT_SET_CPWM_MOD_8821C(x, v) \ + (BIT_CLEAR_CPWM_MOD_8821C(x) | BIT_CPWM_MOD_8821C(v)) /* 2 REG_FWIMR_8821C */ #define BIT_FS_TXBCNOK_MB7_INT_EN_8821C BIT(31) @@ -2400,9 +3549,17 @@ #define BIT_SHIFT_PKTBUF_WRITE_EN_8821C 24 #define BIT_MASK_PKTBUF_WRITE_EN_8821C 0xff -#define BIT_PKTBUF_WRITE_EN_8821C(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8821C) << BIT_SHIFT_PKTBUF_WRITE_EN_8821C) -#define BIT_GET_PKTBUF_WRITE_EN_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8821C) & BIT_MASK_PKTBUF_WRITE_EN_8821C) - +#define BIT_PKTBUF_WRITE_EN_8821C(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN_8821C) \ + << BIT_SHIFT_PKTBUF_WRITE_EN_8821C) +#define BITS_PKTBUF_WRITE_EN_8821C \ + (BIT_MASK_PKTBUF_WRITE_EN_8821C << BIT_SHIFT_PKTBUF_WRITE_EN_8821C) +#define BIT_CLEAR_PKTBUF_WRITE_EN_8821C(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8821C)) +#define BIT_GET_PKTBUF_WRITE_EN_8821C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8821C) & \ + BIT_MASK_PKTBUF_WRITE_EN_8821C) +#define BIT_SET_PKTBUF_WRITE_EN_8821C(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN_8821C(x) | BIT_PKTBUF_WRITE_EN_8821C(v)) #define BIT_TXRPTBUF_DBG_8821C BIT(23) @@ -2412,45 +3569,81 @@ #define BIT_SHIFT_PKTBUF_DBG_ADDR_8821C 0 #define BIT_MASK_PKTBUF_DBG_ADDR_8821C 0x1fff -#define BIT_PKTBUF_DBG_ADDR_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8821C) << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) -#define BIT_GET_PKTBUF_DBG_ADDR_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) & BIT_MASK_PKTBUF_DBG_ADDR_8821C) - - +#define BIT_PKTBUF_DBG_ADDR_8821C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8821C) \ + << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) +#define BITS_PKTBUF_DBG_ADDR_8821C \ + (BIT_MASK_PKTBUF_DBG_ADDR_8821C << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) +#define BIT_CLEAR_PKTBUF_DBG_ADDR_8821C(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8821C)) +#define BIT_GET_PKTBUF_DBG_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) & \ + BIT_MASK_PKTBUF_DBG_ADDR_8821C) +#define BIT_SET_PKTBUF_DBG_ADDR_8821C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR_8821C(x) | BIT_PKTBUF_DBG_ADDR_8821C(v)) /* 2 REG_PKTBUF_DBG_DATA_L_8821C */ #define BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C 0 #define BIT_MASK_PKTBUF_DBG_DATA_L_8821C 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_L_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) -#define BIT_GET_PKTBUF_DBG_DATA_L_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C) - - +#define BIT_PKTBUF_DBG_DATA_L_8821C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) +#define BITS_PKTBUF_DBG_DATA_L_8821C \ + (BIT_MASK_PKTBUF_DBG_DATA_L_8821C << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8821C(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_L_8821C)) +#define BIT_GET_PKTBUF_DBG_DATA_L_8821C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) & \ + BIT_MASK_PKTBUF_DBG_DATA_L_8821C) +#define BIT_SET_PKTBUF_DBG_DATA_L_8821C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L_8821C(x) | BIT_PKTBUF_DBG_DATA_L_8821C(v)) /* 2 REG_PKTBUF_DBG_DATA_H_8821C */ #define BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C 0 #define BIT_MASK_PKTBUF_DBG_DATA_H_8821C 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_H_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) -#define BIT_GET_PKTBUF_DBG_DATA_H_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C) - - +#define BIT_PKTBUF_DBG_DATA_H_8821C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) +#define BITS_PKTBUF_DBG_DATA_H_8821C \ + (BIT_MASK_PKTBUF_DBG_DATA_H_8821C << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8821C(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_H_8821C)) +#define BIT_GET_PKTBUF_DBG_DATA_H_8821C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) & \ + BIT_MASK_PKTBUF_DBG_DATA_H_8821C) +#define BIT_SET_PKTBUF_DBG_DATA_H_8821C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H_8821C(x) | BIT_PKTBUF_DBG_DATA_H_8821C(v)) /* 2 REG_CPWM2_8821C */ #define BIT_SHIFT_L0S_TO_RCVY_NUM_8821C 16 #define BIT_MASK_L0S_TO_RCVY_NUM_8821C 0xff -#define BIT_L0S_TO_RCVY_NUM_8821C(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) -#define BIT_GET_L0S_TO_RCVY_NUM_8821C(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) - +#define BIT_L0S_TO_RCVY_NUM_8821C(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) \ + << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) +#define BITS_L0S_TO_RCVY_NUM_8821C \ + (BIT_MASK_L0S_TO_RCVY_NUM_8821C << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) +#define BIT_CLEAR_L0S_TO_RCVY_NUM_8821C(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8821C)) +#define BIT_GET_L0S_TO_RCVY_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) & \ + BIT_MASK_L0S_TO_RCVY_NUM_8821C) +#define BIT_SET_L0S_TO_RCVY_NUM_8821C(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM_8821C(x) | BIT_L0S_TO_RCVY_NUM_8821C(v)) #define BIT_CPWM2_TOGGLING_8821C BIT(15) #define BIT_SHIFT_CPWM2_MOD_8821C 0 #define BIT_MASK_CPWM2_MOD_8821C 0x7fff -#define BIT_CPWM2_MOD_8821C(x) (((x) & BIT_MASK_CPWM2_MOD_8821C) << BIT_SHIFT_CPWM2_MOD_8821C) -#define BIT_GET_CPWM2_MOD_8821C(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8821C) & BIT_MASK_CPWM2_MOD_8821C) - - +#define BIT_CPWM2_MOD_8821C(x) \ + (((x) & BIT_MASK_CPWM2_MOD_8821C) << BIT_SHIFT_CPWM2_MOD_8821C) +#define BITS_CPWM2_MOD_8821C \ + (BIT_MASK_CPWM2_MOD_8821C << BIT_SHIFT_CPWM2_MOD_8821C) +#define BIT_CLEAR_CPWM2_MOD_8821C(x) ((x) & (~BITS_CPWM2_MOD_8821C)) +#define BIT_GET_CPWM2_MOD_8821C(x) \ + (((x) >> BIT_SHIFT_CPWM2_MOD_8821C) & BIT_MASK_CPWM2_MOD_8821C) +#define BIT_SET_CPWM2_MOD_8821C(x, v) \ + (BIT_CLEAR_CPWM2_MOD_8821C(x) | BIT_CPWM2_MOD_8821C(v)) /* 2 REG_TC0_CTRL_8821C */ #define BIT_TC0INT_EN_8821C BIT(26) @@ -2459,10 +3652,14 @@ #define BIT_SHIFT_TC0DATA_8821C 0 #define BIT_MASK_TC0DATA_8821C 0xffffff -#define BIT_TC0DATA_8821C(x) (((x) & BIT_MASK_TC0DATA_8821C) << BIT_SHIFT_TC0DATA_8821C) -#define BIT_GET_TC0DATA_8821C(x) (((x) >> BIT_SHIFT_TC0DATA_8821C) & BIT_MASK_TC0DATA_8821C) - - +#define BIT_TC0DATA_8821C(x) \ + (((x) & BIT_MASK_TC0DATA_8821C) << BIT_SHIFT_TC0DATA_8821C) +#define BITS_TC0DATA_8821C (BIT_MASK_TC0DATA_8821C << BIT_SHIFT_TC0DATA_8821C) +#define BIT_CLEAR_TC0DATA_8821C(x) ((x) & (~BITS_TC0DATA_8821C)) +#define BIT_GET_TC0DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC0DATA_8821C) & BIT_MASK_TC0DATA_8821C) +#define BIT_SET_TC0DATA_8821C(x, v) \ + (BIT_CLEAR_TC0DATA_8821C(x) | BIT_TC0DATA_8821C(v)) /* 2 REG_TC1_CTRL_8821C */ #define BIT_TC1INT_EN_8821C BIT(26) @@ -2471,10 +3668,14 @@ #define BIT_SHIFT_TC1DATA_8821C 0 #define BIT_MASK_TC1DATA_8821C 0xffffff -#define BIT_TC1DATA_8821C(x) (((x) & BIT_MASK_TC1DATA_8821C) << BIT_SHIFT_TC1DATA_8821C) -#define BIT_GET_TC1DATA_8821C(x) (((x) >> BIT_SHIFT_TC1DATA_8821C) & BIT_MASK_TC1DATA_8821C) - - +#define BIT_TC1DATA_8821C(x) \ + (((x) & BIT_MASK_TC1DATA_8821C) << BIT_SHIFT_TC1DATA_8821C) +#define BITS_TC1DATA_8821C (BIT_MASK_TC1DATA_8821C << BIT_SHIFT_TC1DATA_8821C) +#define BIT_CLEAR_TC1DATA_8821C(x) ((x) & (~BITS_TC1DATA_8821C)) +#define BIT_GET_TC1DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC1DATA_8821C) & BIT_MASK_TC1DATA_8821C) +#define BIT_SET_TC1DATA_8821C(x, v) \ + (BIT_CLEAR_TC1DATA_8821C(x) | BIT_TC1DATA_8821C(v)) /* 2 REG_TC2_CTRL_8821C */ #define BIT_TC2INT_EN_8821C BIT(26) @@ -2483,10 +3684,14 @@ #define BIT_SHIFT_TC2DATA_8821C 0 #define BIT_MASK_TC2DATA_8821C 0xffffff -#define BIT_TC2DATA_8821C(x) (((x) & BIT_MASK_TC2DATA_8821C) << BIT_SHIFT_TC2DATA_8821C) -#define BIT_GET_TC2DATA_8821C(x) (((x) >> BIT_SHIFT_TC2DATA_8821C) & BIT_MASK_TC2DATA_8821C) - - +#define BIT_TC2DATA_8821C(x) \ + (((x) & BIT_MASK_TC2DATA_8821C) << BIT_SHIFT_TC2DATA_8821C) +#define BITS_TC2DATA_8821C (BIT_MASK_TC2DATA_8821C << BIT_SHIFT_TC2DATA_8821C) +#define BIT_CLEAR_TC2DATA_8821C(x) ((x) & (~BITS_TC2DATA_8821C)) +#define BIT_GET_TC2DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC2DATA_8821C) & BIT_MASK_TC2DATA_8821C) +#define BIT_SET_TC2DATA_8821C(x, v) \ + (BIT_CLEAR_TC2DATA_8821C(x) | BIT_TC2DATA_8821C(v)) /* 2 REG_TC3_CTRL_8821C */ #define BIT_TC3INT_EN_8821C BIT(26) @@ -2495,10 +3700,14 @@ #define BIT_SHIFT_TC3DATA_8821C 0 #define BIT_MASK_TC3DATA_8821C 0xffffff -#define BIT_TC3DATA_8821C(x) (((x) & BIT_MASK_TC3DATA_8821C) << BIT_SHIFT_TC3DATA_8821C) -#define BIT_GET_TC3DATA_8821C(x) (((x) >> BIT_SHIFT_TC3DATA_8821C) & BIT_MASK_TC3DATA_8821C) - - +#define BIT_TC3DATA_8821C(x) \ + (((x) & BIT_MASK_TC3DATA_8821C) << BIT_SHIFT_TC3DATA_8821C) +#define BITS_TC3DATA_8821C (BIT_MASK_TC3DATA_8821C << BIT_SHIFT_TC3DATA_8821C) +#define BIT_CLEAR_TC3DATA_8821C(x) ((x) & (~BITS_TC3DATA_8821C)) +#define BIT_GET_TC3DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC3DATA_8821C) & BIT_MASK_TC3DATA_8821C) +#define BIT_SET_TC3DATA_8821C(x, v) \ + (BIT_CLEAR_TC3DATA_8821C(x) | BIT_TC3DATA_8821C(v)) /* 2 REG_TC4_CTRL_8821C */ #define BIT_TC4INT_EN_8821C BIT(26) @@ -2507,19 +3716,28 @@ #define BIT_SHIFT_TC4DATA_8821C 0 #define BIT_MASK_TC4DATA_8821C 0xffffff -#define BIT_TC4DATA_8821C(x) (((x) & BIT_MASK_TC4DATA_8821C) << BIT_SHIFT_TC4DATA_8821C) -#define BIT_GET_TC4DATA_8821C(x) (((x) >> BIT_SHIFT_TC4DATA_8821C) & BIT_MASK_TC4DATA_8821C) - - +#define BIT_TC4DATA_8821C(x) \ + (((x) & BIT_MASK_TC4DATA_8821C) << BIT_SHIFT_TC4DATA_8821C) +#define BITS_TC4DATA_8821C (BIT_MASK_TC4DATA_8821C << BIT_SHIFT_TC4DATA_8821C) +#define BIT_CLEAR_TC4DATA_8821C(x) ((x) & (~BITS_TC4DATA_8821C)) +#define BIT_GET_TC4DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC4DATA_8821C) & BIT_MASK_TC4DATA_8821C) +#define BIT_SET_TC4DATA_8821C(x, v) \ + (BIT_CLEAR_TC4DATA_8821C(x) | BIT_TC4DATA_8821C(v)) /* 2 REG_TCUNIT_BASE_8821C */ #define BIT_SHIFT_TCUNIT_BASE_8821C 0 #define BIT_MASK_TCUNIT_BASE_8821C 0x3fff -#define BIT_TCUNIT_BASE_8821C(x) (((x) & BIT_MASK_TCUNIT_BASE_8821C) << BIT_SHIFT_TCUNIT_BASE_8821C) -#define BIT_GET_TCUNIT_BASE_8821C(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8821C) & BIT_MASK_TCUNIT_BASE_8821C) - - +#define BIT_TCUNIT_BASE_8821C(x) \ + (((x) & BIT_MASK_TCUNIT_BASE_8821C) << BIT_SHIFT_TCUNIT_BASE_8821C) +#define BITS_TCUNIT_BASE_8821C \ + (BIT_MASK_TCUNIT_BASE_8821C << BIT_SHIFT_TCUNIT_BASE_8821C) +#define BIT_CLEAR_TCUNIT_BASE_8821C(x) ((x) & (~BITS_TCUNIT_BASE_8821C)) +#define BIT_GET_TCUNIT_BASE_8821C(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE_8821C) & BIT_MASK_TCUNIT_BASE_8821C) +#define BIT_SET_TCUNIT_BASE_8821C(x, v) \ + (BIT_CLEAR_TCUNIT_BASE_8821C(x) | BIT_TCUNIT_BASE_8821C(v)) /* 2 REG_TC5_CTRL_8821C */ #define BIT_TC5INT_EN_8821C BIT(26) @@ -2528,10 +3746,14 @@ #define BIT_SHIFT_TC5DATA_8821C 0 #define BIT_MASK_TC5DATA_8821C 0xffffff -#define BIT_TC5DATA_8821C(x) (((x) & BIT_MASK_TC5DATA_8821C) << BIT_SHIFT_TC5DATA_8821C) -#define BIT_GET_TC5DATA_8821C(x) (((x) >> BIT_SHIFT_TC5DATA_8821C) & BIT_MASK_TC5DATA_8821C) - - +#define BIT_TC5DATA_8821C(x) \ + (((x) & BIT_MASK_TC5DATA_8821C) << BIT_SHIFT_TC5DATA_8821C) +#define BITS_TC5DATA_8821C (BIT_MASK_TC5DATA_8821C << BIT_SHIFT_TC5DATA_8821C) +#define BIT_CLEAR_TC5DATA_8821C(x) ((x) & (~BITS_TC5DATA_8821C)) +#define BIT_GET_TC5DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC5DATA_8821C) & BIT_MASK_TC5DATA_8821C) +#define BIT_SET_TC5DATA_8821C(x, v) \ + (BIT_CLEAR_TC5DATA_8821C(x) | BIT_TC5DATA_8821C(v)) /* 2 REG_TC6_CTRL_8821C */ #define BIT_TC6INT_EN_8821C BIT(26) @@ -2540,127 +3762,267 @@ #define BIT_SHIFT_TC6DATA_8821C 0 #define BIT_MASK_TC6DATA_8821C 0xffffff -#define BIT_TC6DATA_8821C(x) (((x) & BIT_MASK_TC6DATA_8821C) << BIT_SHIFT_TC6DATA_8821C) -#define BIT_GET_TC6DATA_8821C(x) (((x) >> BIT_SHIFT_TC6DATA_8821C) & BIT_MASK_TC6DATA_8821C) - - - -/* 2 REG_MBIST_FAIL_8821C */ - -#define BIT_SHIFT_8051_MBIST_FAIL_8821C 26 -#define BIT_MASK_8051_MBIST_FAIL_8821C 0x7 -#define BIT_8051_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8821C) << BIT_SHIFT_8051_MBIST_FAIL_8821C) -#define BIT_GET_8051_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8821C) & BIT_MASK_8051_MBIST_FAIL_8821C) - - - -#define BIT_SHIFT_USB_MBIST_FAIL_8821C 24 -#define BIT_MASK_USB_MBIST_FAIL_8821C 0x3 -#define BIT_USB_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8821C) << BIT_SHIFT_USB_MBIST_FAIL_8821C) -#define BIT_GET_USB_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8821C) & BIT_MASK_USB_MBIST_FAIL_8821C) - - - -#define BIT_SHIFT_PCIE_MBIST_FAIL_8821C 16 -#define BIT_MASK_PCIE_MBIST_FAIL_8821C 0x3f -#define BIT_PCIE_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8821C) << BIT_SHIFT_PCIE_MBIST_FAIL_8821C) -#define BIT_GET_PCIE_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8821C) & BIT_MASK_PCIE_MBIST_FAIL_8821C) - - - -#define BIT_SHIFT_MAC_MBIST_FAIL_8821C 0 -#define BIT_MASK_MAC_MBIST_FAIL_8821C 0xfff -#define BIT_MAC_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8821C) << BIT_SHIFT_MAC_MBIST_FAIL_8821C) -#define BIT_GET_MAC_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8821C) & BIT_MASK_MAC_MBIST_FAIL_8821C) - - +#define BIT_TC6DATA_8821C(x) \ + (((x) & BIT_MASK_TC6DATA_8821C) << BIT_SHIFT_TC6DATA_8821C) +#define BITS_TC6DATA_8821C (BIT_MASK_TC6DATA_8821C << BIT_SHIFT_TC6DATA_8821C) +#define BIT_CLEAR_TC6DATA_8821C(x) ((x) & (~BITS_TC6DATA_8821C)) +#define BIT_GET_TC6DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC6DATA_8821C) & BIT_MASK_TC6DATA_8821C) +#define BIT_SET_TC6DATA_8821C(x, v) \ + (BIT_CLEAR_TC6DATA_8821C(x) | BIT_TC6DATA_8821C(v)) + +/* 2 REG_MBIST_DRF_FAIL_8821C */ + +#define BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C 26 +#define BIT_MASK_8051_MBIST_DRF_FAIL_8821C 0x3f +#define BIT_8051_MBIST_DRF_FAIL_8821C(x) \ + (((x) & BIT_MASK_8051_MBIST_DRF_FAIL_8821C) \ + << BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C) +#define BITS_8051_MBIST_DRF_FAIL_8821C \ + (BIT_MASK_8051_MBIST_DRF_FAIL_8821C \ + << BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C) +#define BIT_CLEAR_8051_MBIST_DRF_FAIL_8821C(x) \ + ((x) & (~BITS_8051_MBIST_DRF_FAIL_8821C)) +#define BIT_GET_8051_MBIST_DRF_FAIL_8821C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C) & \ + BIT_MASK_8051_MBIST_DRF_FAIL_8821C) +#define BIT_SET_8051_MBIST_DRF_FAIL_8821C(x, v) \ + (BIT_CLEAR_8051_MBIST_DRF_FAIL_8821C(x) | \ + BIT_8051_MBIST_DRF_FAIL_8821C(v)) + +#define BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C 24 +#define BIT_MASK_USB_MBIST_DRF_FAIL_8821C 0x3 +#define BIT_USB_MBIST_DRF_FAIL_8821C(x) \ + (((x) & BIT_MASK_USB_MBIST_DRF_FAIL_8821C) \ + << BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C) +#define BITS_USB_MBIST_DRF_FAIL_8821C \ + (BIT_MASK_USB_MBIST_DRF_FAIL_8821C \ + << BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C) +#define BIT_CLEAR_USB_MBIST_DRF_FAIL_8821C(x) \ + ((x) & (~BITS_USB_MBIST_DRF_FAIL_8821C)) +#define BIT_GET_USB_MBIST_DRF_FAIL_8821C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C) & \ + BIT_MASK_USB_MBIST_DRF_FAIL_8821C) +#define BIT_SET_USB_MBIST_DRF_FAIL_8821C(x, v) \ + (BIT_CLEAR_USB_MBIST_DRF_FAIL_8821C(x) | \ + BIT_USB_MBIST_DRF_FAIL_8821C(v)) + +#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C 18 +#define BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C 0x3f +#define BIT_PCIE_MBIST_DRF_FAIL_8821C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C) \ + << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C) +#define BITS_PCIE_MBIST_DRF_FAIL_8821C \ + (BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C \ + << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C) +#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8821C(x) \ + ((x) & (~BITS_PCIE_MBIST_DRF_FAIL_8821C)) +#define BIT_GET_PCIE_MBIST_DRF_FAIL_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C) & \ + BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C) +#define BIT_SET_PCIE_MBIST_DRF_FAIL_8821C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8821C(x) | \ + BIT_PCIE_MBIST_DRF_FAIL_8821C(v)) + +#define BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C 0 +#define BIT_MASK_MAC_MBIST_DRF_FAIL_8821C 0x3ffff +#define BIT_MAC_MBIST_DRF_FAIL_8821C(x) \ + (((x) & BIT_MASK_MAC_MBIST_DRF_FAIL_8821C) \ + << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C) +#define BITS_MAC_MBIST_DRF_FAIL_8821C \ + (BIT_MASK_MAC_MBIST_DRF_FAIL_8821C \ + << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C) +#define BIT_CLEAR_MAC_MBIST_DRF_FAIL_8821C(x) \ + ((x) & (~BITS_MAC_MBIST_DRF_FAIL_8821C)) +#define BIT_GET_MAC_MBIST_DRF_FAIL_8821C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C) & \ + BIT_MASK_MAC_MBIST_DRF_FAIL_8821C) +#define BIT_SET_MAC_MBIST_DRF_FAIL_8821C(x, v) \ + (BIT_CLEAR_MAC_MBIST_DRF_FAIL_8821C(x) | \ + BIT_MAC_MBIST_DRF_FAIL_8821C(v)) /* 2 REG_MBIST_START_PAUSE_8821C */ -#define BIT_SHIFT_8051_MBIST_START_PAUSE_8821C 26 -#define BIT_MASK_8051_MBIST_START_PAUSE_8821C 0x7 -#define BIT_8051_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8821C) << BIT_SHIFT_8051_MBIST_START_PAUSE_8821C) -#define BIT_GET_8051_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8821C) & BIT_MASK_8051_MBIST_START_PAUSE_8821C) - - - -#define BIT_SHIFT_USB_MBIST_START_PAUSE_8821C 24 -#define BIT_MASK_USB_MBIST_START_PAUSE_8821C 0x3 -#define BIT_USB_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8821C) << BIT_SHIFT_USB_MBIST_START_PAUSE_8821C) -#define BIT_GET_USB_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8821C) & BIT_MASK_USB_MBIST_START_PAUSE_8821C) - - - -#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C 16 -#define BIT_MASK_PCIE_MBIST_START_PAUSE_8821C 0x3f -#define BIT_PCIE_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8821C) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C) -#define BIT_GET_PCIE_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C) & BIT_MASK_PCIE_MBIST_START_PAUSE_8821C) - - - -#define BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C 0 -#define BIT_MASK_MAC_MBIST_START_PAUSE_8821C 0xfff -#define BIT_MAC_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8821C) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C) -#define BIT_GET_MAC_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C) & BIT_MASK_MAC_MBIST_START_PAUSE_8821C) - - +#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C 26 +#define BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C 0x3f +#define BIT_8051_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C) +#define BITS_8051_MBIST_START_PAUSE_V1_8821C \ + (BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C) +#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8821C(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE_V1_8821C)) +#define BIT_GET_8051_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C) & \ + BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C) +#define BIT_SET_8051_MBIST_START_PAUSE_V1_8821C(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8821C(x) | \ + BIT_8051_MBIST_START_PAUSE_V1_8821C(v)) + +#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C 24 +#define BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C 0x3 +#define BIT_USB_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C) +#define BITS_USB_MBIST_START_PAUSE_V1_8821C \ + (BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8821C(x) \ + ((x) & (~BITS_USB_MBIST_START_PAUSE_V1_8821C)) +#define BIT_GET_USB_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C) & \ + BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C) +#define BIT_SET_USB_MBIST_START_PAUSE_V1_8821C(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8821C(x) | \ + BIT_USB_MBIST_START_PAUSE_V1_8821C(v)) + +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C 18 +#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C 0x3f +#define BIT_PCIE_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C) +#define BITS_PCIE_MBIST_START_PAUSE_V1_8821C \ + (BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8821C(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1_8821C)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C) +#define BIT_SET_PCIE_MBIST_START_PAUSE_V1_8821C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8821C(x) | \ + BIT_PCIE_MBIST_START_PAUSE_V1_8821C(v)) + +#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C 0 +#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C 0x3ffff +#define BIT_MAC_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C) +#define BITS_MAC_MBIST_START_PAUSE_V1_8821C \ + (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8821C(x) \ + ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8821C)) +#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C) & \ + BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C) +#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8821C(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8821C(x) | \ + BIT_MAC_MBIST_START_PAUSE_V1_8821C(v)) /* 2 REG_MBIST_DONE_8821C */ -#define BIT_SHIFT_8051_MBIST_DONE_8821C 26 -#define BIT_MASK_8051_MBIST_DONE_8821C 0x7 -#define BIT_8051_MBIST_DONE_8821C(x) (((x) & BIT_MASK_8051_MBIST_DONE_8821C) << BIT_SHIFT_8051_MBIST_DONE_8821C) -#define BIT_GET_8051_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8821C) & BIT_MASK_8051_MBIST_DONE_8821C) - - - -#define BIT_SHIFT_USB_MBIST_DONE_8821C 24 -#define BIT_MASK_USB_MBIST_DONE_8821C 0x3 -#define BIT_USB_MBIST_DONE_8821C(x) (((x) & BIT_MASK_USB_MBIST_DONE_8821C) << BIT_SHIFT_USB_MBIST_DONE_8821C) -#define BIT_GET_USB_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8821C) & BIT_MASK_USB_MBIST_DONE_8821C) - - - -#define BIT_SHIFT_PCIE_MBIST_DONE_8821C 16 -#define BIT_MASK_PCIE_MBIST_DONE_8821C 0x3f -#define BIT_PCIE_MBIST_DONE_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8821C) << BIT_SHIFT_PCIE_MBIST_DONE_8821C) -#define BIT_GET_PCIE_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8821C) & BIT_MASK_PCIE_MBIST_DONE_8821C) - - - -#define BIT_SHIFT_MAC_MBIST_DONE_8821C 0 -#define BIT_MASK_MAC_MBIST_DONE_8821C 0xfff -#define BIT_MAC_MBIST_DONE_8821C(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8821C) << BIT_SHIFT_MAC_MBIST_DONE_8821C) -#define BIT_GET_MAC_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8821C) & BIT_MASK_MAC_MBIST_DONE_8821C) - - - -/* 2 REG_MBIST_FAIL_NRML_8821C */ - -#define BIT_SHIFT_MBIST_FAIL_NRML_8821C 0 -#define BIT_MASK_MBIST_FAIL_NRML_8821C 0xffffffffL -#define BIT_MBIST_FAIL_NRML_8821C(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_8821C) << BIT_SHIFT_MBIST_FAIL_NRML_8821C) -#define BIT_GET_MBIST_FAIL_NRML_8821C(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8821C) & BIT_MASK_MBIST_FAIL_NRML_8821C) - - +#define BIT_SHIFT_8051_MBIST_DONE_V1_8821C 26 +#define BIT_MASK_8051_MBIST_DONE_V1_8821C 0x3f +#define BIT_8051_MBIST_DONE_V1_8821C(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE_V1_8821C) \ + << BIT_SHIFT_8051_MBIST_DONE_V1_8821C) +#define BITS_8051_MBIST_DONE_V1_8821C \ + (BIT_MASK_8051_MBIST_DONE_V1_8821C \ + << BIT_SHIFT_8051_MBIST_DONE_V1_8821C) +#define BIT_CLEAR_8051_MBIST_DONE_V1_8821C(x) \ + ((x) & (~BITS_8051_MBIST_DONE_V1_8821C)) +#define BIT_GET_8051_MBIST_DONE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE_V1_8821C) & \ + BIT_MASK_8051_MBIST_DONE_V1_8821C) +#define BIT_SET_8051_MBIST_DONE_V1_8821C(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE_V1_8821C(x) | \ + BIT_8051_MBIST_DONE_V1_8821C(v)) + +#define BIT_SHIFT_USB_MBIST_DONE_V1_8821C 24 +#define BIT_MASK_USB_MBIST_DONE_V1_8821C 0x3 +#define BIT_USB_MBIST_DONE_V1_8821C(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE_V1_8821C) \ + << BIT_SHIFT_USB_MBIST_DONE_V1_8821C) +#define BITS_USB_MBIST_DONE_V1_8821C \ + (BIT_MASK_USB_MBIST_DONE_V1_8821C << BIT_SHIFT_USB_MBIST_DONE_V1_8821C) +#define BIT_CLEAR_USB_MBIST_DONE_V1_8821C(x) \ + ((x) & (~BITS_USB_MBIST_DONE_V1_8821C)) +#define BIT_GET_USB_MBIST_DONE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE_V1_8821C) & \ + BIT_MASK_USB_MBIST_DONE_V1_8821C) +#define BIT_SET_USB_MBIST_DONE_V1_8821C(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE_V1_8821C(x) | BIT_USB_MBIST_DONE_V1_8821C(v)) + +#define BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C 18 +#define BIT_MASK_PCIE_MBIST_DONE_V1_8821C 0x3f +#define BIT_PCIE_MBIST_DONE_V1_8821C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE_V1_8821C) \ + << BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C) +#define BITS_PCIE_MBIST_DONE_V1_8821C \ + (BIT_MASK_PCIE_MBIST_DONE_V1_8821C \ + << BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C) +#define BIT_CLEAR_PCIE_MBIST_DONE_V1_8821C(x) \ + ((x) & (~BITS_PCIE_MBIST_DONE_V1_8821C)) +#define BIT_GET_PCIE_MBIST_DONE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C) & \ + BIT_MASK_PCIE_MBIST_DONE_V1_8821C) +#define BIT_SET_PCIE_MBIST_DONE_V1_8821C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE_V1_8821C(x) | \ + BIT_PCIE_MBIST_DONE_V1_8821C(v)) + +#define BIT_SHIFT_MAC_MBIST_DONE_V1_8821C 0 +#define BIT_MASK_MAC_MBIST_DONE_V1_8821C 0x3ffff +#define BIT_MAC_MBIST_DONE_V1_8821C(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8821C) \ + << BIT_SHIFT_MAC_MBIST_DONE_V1_8821C) +#define BITS_MAC_MBIST_DONE_V1_8821C \ + (BIT_MASK_MAC_MBIST_DONE_V1_8821C << BIT_SHIFT_MAC_MBIST_DONE_V1_8821C) +#define BIT_CLEAR_MAC_MBIST_DONE_V1_8821C(x) \ + ((x) & (~BITS_MAC_MBIST_DONE_V1_8821C)) +#define BIT_GET_MAC_MBIST_DONE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8821C) & \ + BIT_MASK_MAC_MBIST_DONE_V1_8821C) +#define BIT_SET_MAC_MBIST_DONE_V1_8821C(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE_V1_8821C(x) | BIT_MAC_MBIST_DONE_V1_8821C(v)) + +/* 2 REG_MBIST_READ_BIST_RPT_8821C */ + +#define BIT_SHIFT_MBIST_READ_BIST_RPT_8821C 0 +#define BIT_MASK_MBIST_READ_BIST_RPT_8821C 0xffffffffL +#define BIT_MBIST_READ_BIST_RPT_8821C(x) \ + (((x) & BIT_MASK_MBIST_READ_BIST_RPT_8821C) \ + << BIT_SHIFT_MBIST_READ_BIST_RPT_8821C) +#define BITS_MBIST_READ_BIST_RPT_8821C \ + (BIT_MASK_MBIST_READ_BIST_RPT_8821C \ + << BIT_SHIFT_MBIST_READ_BIST_RPT_8821C) +#define BIT_CLEAR_MBIST_READ_BIST_RPT_8821C(x) \ + ((x) & (~BITS_MBIST_READ_BIST_RPT_8821C)) +#define BIT_GET_MBIST_READ_BIST_RPT_8821C(x) \ + (((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT_8821C) & \ + BIT_MASK_MBIST_READ_BIST_RPT_8821C) +#define BIT_SET_MBIST_READ_BIST_RPT_8821C(x, v) \ + (BIT_CLEAR_MBIST_READ_BIST_RPT_8821C(x) | \ + BIT_MBIST_READ_BIST_RPT_8821C(v)) /* 2 REG_AES_DECRPT_DATA_8821C */ #define BIT_SHIFT_IPS_CFG_ADDR_8821C 0 #define BIT_MASK_IPS_CFG_ADDR_8821C 0xff -#define BIT_IPS_CFG_ADDR_8821C(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8821C) << BIT_SHIFT_IPS_CFG_ADDR_8821C) -#define BIT_GET_IPS_CFG_ADDR_8821C(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8821C) & BIT_MASK_IPS_CFG_ADDR_8821C) - - +#define BIT_IPS_CFG_ADDR_8821C(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR_8821C) << BIT_SHIFT_IPS_CFG_ADDR_8821C) +#define BITS_IPS_CFG_ADDR_8821C \ + (BIT_MASK_IPS_CFG_ADDR_8821C << BIT_SHIFT_IPS_CFG_ADDR_8821C) +#define BIT_CLEAR_IPS_CFG_ADDR_8821C(x) ((x) & (~BITS_IPS_CFG_ADDR_8821C)) +#define BIT_GET_IPS_CFG_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8821C) & BIT_MASK_IPS_CFG_ADDR_8821C) +#define BIT_SET_IPS_CFG_ADDR_8821C(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR_8821C(x) | BIT_IPS_CFG_ADDR_8821C(v)) /* 2 REG_AES_DECRPT_CFG_8821C */ #define BIT_SHIFT_IPS_CFG_DATA_8821C 0 #define BIT_MASK_IPS_CFG_DATA_8821C 0xffffffffL -#define BIT_IPS_CFG_DATA_8821C(x) (((x) & BIT_MASK_IPS_CFG_DATA_8821C) << BIT_SHIFT_IPS_CFG_DATA_8821C) -#define BIT_GET_IPS_CFG_DATA_8821C(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8821C) & BIT_MASK_IPS_CFG_DATA_8821C) - - +#define BIT_IPS_CFG_DATA_8821C(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA_8821C) << BIT_SHIFT_IPS_CFG_DATA_8821C) +#define BITS_IPS_CFG_DATA_8821C \ + (BIT_MASK_IPS_CFG_DATA_8821C << BIT_SHIFT_IPS_CFG_DATA_8821C) +#define BIT_CLEAR_IPS_CFG_DATA_8821C(x) ((x) & (~BITS_IPS_CFG_DATA_8821C)) +#define BIT_GET_IPS_CFG_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA_8821C) & BIT_MASK_IPS_CFG_DATA_8821C) +#define BIT_SET_IPS_CFG_DATA_8821C(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA_8821C(x) | BIT_IPS_CFG_DATA_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -2671,23 +4033,44 @@ #define BIT_SHIFT_TEMP_VALUE_8821C 24 #define BIT_MASK_TEMP_VALUE_8821C 0x3f -#define BIT_TEMP_VALUE_8821C(x) (((x) & BIT_MASK_TEMP_VALUE_8821C) << BIT_SHIFT_TEMP_VALUE_8821C) -#define BIT_GET_TEMP_VALUE_8821C(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8821C) & BIT_MASK_TEMP_VALUE_8821C) - - +#define BIT_TEMP_VALUE_8821C(x) \ + (((x) & BIT_MASK_TEMP_VALUE_8821C) << BIT_SHIFT_TEMP_VALUE_8821C) +#define BITS_TEMP_VALUE_8821C \ + (BIT_MASK_TEMP_VALUE_8821C << BIT_SHIFT_TEMP_VALUE_8821C) +#define BIT_CLEAR_TEMP_VALUE_8821C(x) ((x) & (~BITS_TEMP_VALUE_8821C)) +#define BIT_GET_TEMP_VALUE_8821C(x) \ + (((x) >> BIT_SHIFT_TEMP_VALUE_8821C) & BIT_MASK_TEMP_VALUE_8821C) +#define BIT_SET_TEMP_VALUE_8821C(x, v) \ + (BIT_CLEAR_TEMP_VALUE_8821C(x) | BIT_TEMP_VALUE_8821C(v)) #define BIT_SHIFT_REG_TMETER_TIMER_8821C 8 #define BIT_MASK_REG_TMETER_TIMER_8821C 0xfff -#define BIT_REG_TMETER_TIMER_8821C(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8821C) << BIT_SHIFT_REG_TMETER_TIMER_8821C) -#define BIT_GET_REG_TMETER_TIMER_8821C(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8821C) & BIT_MASK_REG_TMETER_TIMER_8821C) - - +#define BIT_REG_TMETER_TIMER_8821C(x) \ + (((x) & BIT_MASK_REG_TMETER_TIMER_8821C) \ + << BIT_SHIFT_REG_TMETER_TIMER_8821C) +#define BITS_REG_TMETER_TIMER_8821C \ + (BIT_MASK_REG_TMETER_TIMER_8821C << BIT_SHIFT_REG_TMETER_TIMER_8821C) +#define BIT_CLEAR_REG_TMETER_TIMER_8821C(x) \ + ((x) & (~BITS_REG_TMETER_TIMER_8821C)) +#define BIT_GET_REG_TMETER_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8821C) & \ + BIT_MASK_REG_TMETER_TIMER_8821C) +#define BIT_SET_REG_TMETER_TIMER_8821C(x, v) \ + (BIT_CLEAR_REG_TMETER_TIMER_8821C(x) | BIT_REG_TMETER_TIMER_8821C(v)) #define BIT_SHIFT_REG_TEMP_DELTA_8821C 2 #define BIT_MASK_REG_TEMP_DELTA_8821C 0x3f -#define BIT_REG_TEMP_DELTA_8821C(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8821C) << BIT_SHIFT_REG_TEMP_DELTA_8821C) -#define BIT_GET_REG_TEMP_DELTA_8821C(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8821C) & BIT_MASK_REG_TEMP_DELTA_8821C) - +#define BIT_REG_TEMP_DELTA_8821C(x) \ + (((x) & BIT_MASK_REG_TEMP_DELTA_8821C) \ + << BIT_SHIFT_REG_TEMP_DELTA_8821C) +#define BITS_REG_TEMP_DELTA_8821C \ + (BIT_MASK_REG_TEMP_DELTA_8821C << BIT_SHIFT_REG_TEMP_DELTA_8821C) +#define BIT_CLEAR_REG_TEMP_DELTA_8821C(x) ((x) & (~BITS_REG_TEMP_DELTA_8821C)) +#define BIT_GET_REG_TEMP_DELTA_8821C(x) \ + (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8821C) & \ + BIT_MASK_REG_TEMP_DELTA_8821C) +#define BIT_SET_REG_TEMP_DELTA_8821C(x, v) \ + (BIT_CLEAR_REG_TEMP_DELTA_8821C(x) | BIT_REG_TEMP_DELTA_8821C(v)) #define BIT_REG_TMETER_EN_8821C BIT(0) @@ -2695,16 +4078,33 @@ #define BIT_SHIFT_OSC_32K_CLKGEN_0_8821C 16 #define BIT_MASK_OSC_32K_CLKGEN_0_8821C 0xffff -#define BIT_OSC_32K_CLKGEN_0_8821C(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8821C) << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) -#define BIT_GET_OSC_32K_CLKGEN_0_8821C(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) & BIT_MASK_OSC_32K_CLKGEN_0_8821C) - - +#define BIT_OSC_32K_CLKGEN_0_8821C(x) \ + (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8821C) \ + << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) +#define BITS_OSC_32K_CLKGEN_0_8821C \ + (BIT_MASK_OSC_32K_CLKGEN_0_8821C << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) +#define BIT_CLEAR_OSC_32K_CLKGEN_0_8821C(x) \ + ((x) & (~BITS_OSC_32K_CLKGEN_0_8821C)) +#define BIT_GET_OSC_32K_CLKGEN_0_8821C(x) \ + (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) & \ + BIT_MASK_OSC_32K_CLKGEN_0_8821C) +#define BIT_SET_OSC_32K_CLKGEN_0_8821C(x, v) \ + (BIT_CLEAR_OSC_32K_CLKGEN_0_8821C(x) | BIT_OSC_32K_CLKGEN_0_8821C(v)) #define BIT_SHIFT_OSC_32K_RES_COMP_8821C 4 #define BIT_MASK_OSC_32K_RES_COMP_8821C 0x3 -#define BIT_OSC_32K_RES_COMP_8821C(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8821C) << BIT_SHIFT_OSC_32K_RES_COMP_8821C) -#define BIT_GET_OSC_32K_RES_COMP_8821C(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8821C) & BIT_MASK_OSC_32K_RES_COMP_8821C) - +#define BIT_OSC_32K_RES_COMP_8821C(x) \ + (((x) & BIT_MASK_OSC_32K_RES_COMP_8821C) \ + << BIT_SHIFT_OSC_32K_RES_COMP_8821C) +#define BITS_OSC_32K_RES_COMP_8821C \ + (BIT_MASK_OSC_32K_RES_COMP_8821C << BIT_SHIFT_OSC_32K_RES_COMP_8821C) +#define BIT_CLEAR_OSC_32K_RES_COMP_8821C(x) \ + ((x) & (~BITS_OSC_32K_RES_COMP_8821C)) +#define BIT_GET_OSC_32K_RES_COMP_8821C(x) \ + (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8821C) & \ + BIT_MASK_OSC_32K_RES_COMP_8821C) +#define BIT_SET_OSC_32K_RES_COMP_8821C(x, v) \ + (BIT_CLEAR_OSC_32K_RES_COMP_8821C(x) | BIT_OSC_32K_RES_COMP_8821C(v)) #define BIT_OSC_32K_OUT_SEL_8821C BIT(3) #define BIT_ISO_WL_2_OSC_32K_8821C BIT(1) @@ -2716,17 +4116,33 @@ #define BIT_SHIFT_CAL_32K_REG_ADDR_8821C 16 #define BIT_MASK_CAL_32K_REG_ADDR_8821C 0x3f -#define BIT_CAL_32K_REG_ADDR_8821C(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR_8821C) << BIT_SHIFT_CAL_32K_REG_ADDR_8821C) -#define BIT_GET_CAL_32K_REG_ADDR_8821C(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8821C) & BIT_MASK_CAL_32K_REG_ADDR_8821C) - - +#define BIT_CAL_32K_REG_ADDR_8821C(x) \ + (((x) & BIT_MASK_CAL_32K_REG_ADDR_8821C) \ + << BIT_SHIFT_CAL_32K_REG_ADDR_8821C) +#define BITS_CAL_32K_REG_ADDR_8821C \ + (BIT_MASK_CAL_32K_REG_ADDR_8821C << BIT_SHIFT_CAL_32K_REG_ADDR_8821C) +#define BIT_CLEAR_CAL_32K_REG_ADDR_8821C(x) \ + ((x) & (~BITS_CAL_32K_REG_ADDR_8821C)) +#define BIT_GET_CAL_32K_REG_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8821C) & \ + BIT_MASK_CAL_32K_REG_ADDR_8821C) +#define BIT_SET_CAL_32K_REG_ADDR_8821C(x, v) \ + (BIT_CLEAR_CAL_32K_REG_ADDR_8821C(x) | BIT_CAL_32K_REG_ADDR_8821C(v)) #define BIT_SHIFT_CAL_32K_REG_DATA_8821C 0 #define BIT_MASK_CAL_32K_REG_DATA_8821C 0xffff -#define BIT_CAL_32K_REG_DATA_8821C(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8821C) << BIT_SHIFT_CAL_32K_REG_DATA_8821C) -#define BIT_GET_CAL_32K_REG_DATA_8821C(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8821C) & BIT_MASK_CAL_32K_REG_DATA_8821C) - - +#define BIT_CAL_32K_REG_DATA_8821C(x) \ + (((x) & BIT_MASK_CAL_32K_REG_DATA_8821C) \ + << BIT_SHIFT_CAL_32K_REG_DATA_8821C) +#define BITS_CAL_32K_REG_DATA_8821C \ + (BIT_MASK_CAL_32K_REG_DATA_8821C << BIT_SHIFT_CAL_32K_REG_DATA_8821C) +#define BIT_CLEAR_CAL_32K_REG_DATA_8821C(x) \ + ((x) & (~BITS_CAL_32K_REG_DATA_8821C)) +#define BIT_GET_CAL_32K_REG_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8821C) & \ + BIT_MASK_CAL_32K_REG_DATA_8821C) +#define BIT_SET_CAL_32K_REG_DATA_8821C(x, v) \ + (BIT_CLEAR_CAL_32K_REG_DATA_8821C(x) | BIT_CAL_32K_REG_DATA_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -2734,37 +4150,57 @@ #define BIT_SHIFT_C2HEVT_MSG_V1_8821C 0 #define BIT_MASK_C2HEVT_MSG_V1_8821C 0xffffffffL -#define BIT_C2HEVT_MSG_V1_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_V1_8821C) << BIT_SHIFT_C2HEVT_MSG_V1_8821C) -#define BIT_GET_C2HEVT_MSG_V1_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8821C) & BIT_MASK_C2HEVT_MSG_V1_8821C) - - +#define BIT_C2HEVT_MSG_V1_8821C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_V1_8821C) << BIT_SHIFT_C2HEVT_MSG_V1_8821C) +#define BITS_C2HEVT_MSG_V1_8821C \ + (BIT_MASK_C2HEVT_MSG_V1_8821C << BIT_SHIFT_C2HEVT_MSG_V1_8821C) +#define BIT_CLEAR_C2HEVT_MSG_V1_8821C(x) ((x) & (~BITS_C2HEVT_MSG_V1_8821C)) +#define BIT_GET_C2HEVT_MSG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8821C) & BIT_MASK_C2HEVT_MSG_V1_8821C) +#define BIT_SET_C2HEVT_MSG_V1_8821C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_V1_8821C(x) | BIT_C2HEVT_MSG_V1_8821C(v)) /* 2 REG_C2HEVT_1_8821C */ #define BIT_SHIFT_C2HEVT_MSG_1_8821C 0 #define BIT_MASK_C2HEVT_MSG_1_8821C 0xffffffffL -#define BIT_C2HEVT_MSG_1_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_1_8821C) << BIT_SHIFT_C2HEVT_MSG_1_8821C) -#define BIT_GET_C2HEVT_MSG_1_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8821C) & BIT_MASK_C2HEVT_MSG_1_8821C) - - +#define BIT_C2HEVT_MSG_1_8821C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_1_8821C) << BIT_SHIFT_C2HEVT_MSG_1_8821C) +#define BITS_C2HEVT_MSG_1_8821C \ + (BIT_MASK_C2HEVT_MSG_1_8821C << BIT_SHIFT_C2HEVT_MSG_1_8821C) +#define BIT_CLEAR_C2HEVT_MSG_1_8821C(x) ((x) & (~BITS_C2HEVT_MSG_1_8821C)) +#define BIT_GET_C2HEVT_MSG_1_8821C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8821C) & BIT_MASK_C2HEVT_MSG_1_8821C) +#define BIT_SET_C2HEVT_MSG_1_8821C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_1_8821C(x) | BIT_C2HEVT_MSG_1_8821C(v)) /* 2 REG_C2HEVT_2_8821C */ #define BIT_SHIFT_C2HEVT_MSG_2_8821C 0 #define BIT_MASK_C2HEVT_MSG_2_8821C 0xffffffffL -#define BIT_C2HEVT_MSG_2_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_2_8821C) << BIT_SHIFT_C2HEVT_MSG_2_8821C) -#define BIT_GET_C2HEVT_MSG_2_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8821C) & BIT_MASK_C2HEVT_MSG_2_8821C) - - +#define BIT_C2HEVT_MSG_2_8821C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_2_8821C) << BIT_SHIFT_C2HEVT_MSG_2_8821C) +#define BITS_C2HEVT_MSG_2_8821C \ + (BIT_MASK_C2HEVT_MSG_2_8821C << BIT_SHIFT_C2HEVT_MSG_2_8821C) +#define BIT_CLEAR_C2HEVT_MSG_2_8821C(x) ((x) & (~BITS_C2HEVT_MSG_2_8821C)) +#define BIT_GET_C2HEVT_MSG_2_8821C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8821C) & BIT_MASK_C2HEVT_MSG_2_8821C) +#define BIT_SET_C2HEVT_MSG_2_8821C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_2_8821C(x) | BIT_C2HEVT_MSG_2_8821C(v)) /* 2 REG_C2HEVT_3_8821C */ #define BIT_SHIFT_C2HEVT_MSG_3_8821C 0 #define BIT_MASK_C2HEVT_MSG_3_8821C 0xffffffffL -#define BIT_C2HEVT_MSG_3_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_3_8821C) << BIT_SHIFT_C2HEVT_MSG_3_8821C) -#define BIT_GET_C2HEVT_MSG_3_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8821C) & BIT_MASK_C2HEVT_MSG_3_8821C) - - +#define BIT_C2HEVT_MSG_3_8821C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_3_8821C) << BIT_SHIFT_C2HEVT_MSG_3_8821C) +#define BITS_C2HEVT_MSG_3_8821C \ + (BIT_MASK_C2HEVT_MSG_3_8821C << BIT_SHIFT_C2HEVT_MSG_3_8821C) +#define BIT_CLEAR_C2HEVT_MSG_3_8821C(x) ((x) & (~BITS_C2HEVT_MSG_3_8821C)) +#define BIT_GET_C2HEVT_MSG_3_8821C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8821C) & BIT_MASK_C2HEVT_MSG_3_8821C) +#define BIT_SET_C2HEVT_MSG_3_8821C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_3_8821C(x) | BIT_C2HEVT_MSG_3_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -2774,55 +4210,93 @@ #define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C 0 #define BIT_MASK_SW_DEFINED_PAGE1_V1_8821C 0xffffffffL -#define BIT_SW_DEFINED_PAGE1_V1_8821C(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) -#define BIT_GET_SW_DEFINED_PAGE1_V1_8821C(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) - - +#define BIT_SW_DEFINED_PAGE1_V1_8821C(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) +#define BITS_SW_DEFINED_PAGE1_V1_8821C \ + (BIT_MASK_SW_DEFINED_PAGE1_V1_8821C \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) +#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8821C(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE1_V1_8821C)) +#define BIT_GET_SW_DEFINED_PAGE1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) & \ + BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) +#define BIT_SET_SW_DEFINED_PAGE1_V1_8821C(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_V1_8821C(x) | \ + BIT_SW_DEFINED_PAGE1_V1_8821C(v)) /* 2 REG_SW_DEFINED_PAGE2_8821C */ #define BIT_SHIFT_SW_DEFINED_PAGE2_8821C 0 #define BIT_MASK_SW_DEFINED_PAGE2_8821C 0xffffffffL -#define BIT_SW_DEFINED_PAGE2_8821C(x) (((x) & BIT_MASK_SW_DEFINED_PAGE2_8821C) << BIT_SHIFT_SW_DEFINED_PAGE2_8821C) -#define BIT_GET_SW_DEFINED_PAGE2_8821C(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8821C) & BIT_MASK_SW_DEFINED_PAGE2_8821C) - - +#define BIT_SW_DEFINED_PAGE2_8821C(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE2_8821C) \ + << BIT_SHIFT_SW_DEFINED_PAGE2_8821C) +#define BITS_SW_DEFINED_PAGE2_8821C \ + (BIT_MASK_SW_DEFINED_PAGE2_8821C << BIT_SHIFT_SW_DEFINED_PAGE2_8821C) +#define BIT_CLEAR_SW_DEFINED_PAGE2_8821C(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE2_8821C)) +#define BIT_GET_SW_DEFINED_PAGE2_8821C(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8821C) & \ + BIT_MASK_SW_DEFINED_PAGE2_8821C) +#define BIT_SET_SW_DEFINED_PAGE2_8821C(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE2_8821C(x) | BIT_SW_DEFINED_PAGE2_8821C(v)) /* 2 REG_MCUTST_I_8821C */ #define BIT_SHIFT_MCUDMSG_I_8821C 0 #define BIT_MASK_MCUDMSG_I_8821C 0xffffffffL -#define BIT_MCUDMSG_I_8821C(x) (((x) & BIT_MASK_MCUDMSG_I_8821C) << BIT_SHIFT_MCUDMSG_I_8821C) -#define BIT_GET_MCUDMSG_I_8821C(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8821C) & BIT_MASK_MCUDMSG_I_8821C) - - +#define BIT_MCUDMSG_I_8821C(x) \ + (((x) & BIT_MASK_MCUDMSG_I_8821C) << BIT_SHIFT_MCUDMSG_I_8821C) +#define BITS_MCUDMSG_I_8821C \ + (BIT_MASK_MCUDMSG_I_8821C << BIT_SHIFT_MCUDMSG_I_8821C) +#define BIT_CLEAR_MCUDMSG_I_8821C(x) ((x) & (~BITS_MCUDMSG_I_8821C)) +#define BIT_GET_MCUDMSG_I_8821C(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_I_8821C) & BIT_MASK_MCUDMSG_I_8821C) +#define BIT_SET_MCUDMSG_I_8821C(x, v) \ + (BIT_CLEAR_MCUDMSG_I_8821C(x) | BIT_MCUDMSG_I_8821C(v)) /* 2 REG_MCUTST_II_8821C */ #define BIT_SHIFT_MCUDMSG_II_8821C 0 #define BIT_MASK_MCUDMSG_II_8821C 0xffffffffL -#define BIT_MCUDMSG_II_8821C(x) (((x) & BIT_MASK_MCUDMSG_II_8821C) << BIT_SHIFT_MCUDMSG_II_8821C) -#define BIT_GET_MCUDMSG_II_8821C(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8821C) & BIT_MASK_MCUDMSG_II_8821C) - - +#define BIT_MCUDMSG_II_8821C(x) \ + (((x) & BIT_MASK_MCUDMSG_II_8821C) << BIT_SHIFT_MCUDMSG_II_8821C) +#define BITS_MCUDMSG_II_8821C \ + (BIT_MASK_MCUDMSG_II_8821C << BIT_SHIFT_MCUDMSG_II_8821C) +#define BIT_CLEAR_MCUDMSG_II_8821C(x) ((x) & (~BITS_MCUDMSG_II_8821C)) +#define BIT_GET_MCUDMSG_II_8821C(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II_8821C) & BIT_MASK_MCUDMSG_II_8821C) +#define BIT_SET_MCUDMSG_II_8821C(x, v) \ + (BIT_CLEAR_MCUDMSG_II_8821C(x) | BIT_MCUDMSG_II_8821C(v)) /* 2 REG_FMETHR_8821C */ #define BIT_FMSG_INT_8821C BIT(31) #define BIT_SHIFT_FW_MSG_8821C 0 #define BIT_MASK_FW_MSG_8821C 0xffffffffL -#define BIT_FW_MSG_8821C(x) (((x) & BIT_MASK_FW_MSG_8821C) << BIT_SHIFT_FW_MSG_8821C) -#define BIT_GET_FW_MSG_8821C(x) (((x) >> BIT_SHIFT_FW_MSG_8821C) & BIT_MASK_FW_MSG_8821C) - - +#define BIT_FW_MSG_8821C(x) \ + (((x) & BIT_MASK_FW_MSG_8821C) << BIT_SHIFT_FW_MSG_8821C) +#define BITS_FW_MSG_8821C (BIT_MASK_FW_MSG_8821C << BIT_SHIFT_FW_MSG_8821C) +#define BIT_CLEAR_FW_MSG_8821C(x) ((x) & (~BITS_FW_MSG_8821C)) +#define BIT_GET_FW_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_8821C) & BIT_MASK_FW_MSG_8821C) +#define BIT_SET_FW_MSG_8821C(x, v) \ + (BIT_CLEAR_FW_MSG_8821C(x) | BIT_FW_MSG_8821C(v)) /* 2 REG_HMETFR_8821C */ #define BIT_SHIFT_HRCV_MSG_8821C 24 #define BIT_MASK_HRCV_MSG_8821C 0xff -#define BIT_HRCV_MSG_8821C(x) (((x) & BIT_MASK_HRCV_MSG_8821C) << BIT_SHIFT_HRCV_MSG_8821C) -#define BIT_GET_HRCV_MSG_8821C(x) (((x) >> BIT_SHIFT_HRCV_MSG_8821C) & BIT_MASK_HRCV_MSG_8821C) - +#define BIT_HRCV_MSG_8821C(x) \ + (((x) & BIT_MASK_HRCV_MSG_8821C) << BIT_SHIFT_HRCV_MSG_8821C) +#define BITS_HRCV_MSG_8821C \ + (BIT_MASK_HRCV_MSG_8821C << BIT_SHIFT_HRCV_MSG_8821C) +#define BIT_CLEAR_HRCV_MSG_8821C(x) ((x) & (~BITS_HRCV_MSG_8821C)) +#define BIT_GET_HRCV_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_HRCV_MSG_8821C) & BIT_MASK_HRCV_MSG_8821C) +#define BIT_SET_HRCV_MSG_8821C(x, v) \ + (BIT_CLEAR_HRCV_MSG_8821C(x) | BIT_HRCV_MSG_8821C(v)) #define BIT_INT_BOX3_8821C BIT(3) #define BIT_INT_BOX2_8821C BIT(2) @@ -2833,91 +4307,98 @@ #define BIT_SHIFT_HOST_MSG_0_8821C 0 #define BIT_MASK_HOST_MSG_0_8821C 0xffffffffL -#define BIT_HOST_MSG_0_8821C(x) (((x) & BIT_MASK_HOST_MSG_0_8821C) << BIT_SHIFT_HOST_MSG_0_8821C) -#define BIT_GET_HOST_MSG_0_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8821C) & BIT_MASK_HOST_MSG_0_8821C) - - +#define BIT_HOST_MSG_0_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_0_8821C) << BIT_SHIFT_HOST_MSG_0_8821C) +#define BITS_HOST_MSG_0_8821C \ + (BIT_MASK_HOST_MSG_0_8821C << BIT_SHIFT_HOST_MSG_0_8821C) +#define BIT_CLEAR_HOST_MSG_0_8821C(x) ((x) & (~BITS_HOST_MSG_0_8821C)) +#define BIT_GET_HOST_MSG_0_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0_8821C) & BIT_MASK_HOST_MSG_0_8821C) +#define BIT_SET_HOST_MSG_0_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_0_8821C(x) | BIT_HOST_MSG_0_8821C(v)) /* 2 REG_HMEBOX1_8821C */ #define BIT_SHIFT_HOST_MSG_1_8821C 0 #define BIT_MASK_HOST_MSG_1_8821C 0xffffffffL -#define BIT_HOST_MSG_1_8821C(x) (((x) & BIT_MASK_HOST_MSG_1_8821C) << BIT_SHIFT_HOST_MSG_1_8821C) -#define BIT_GET_HOST_MSG_1_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8821C) & BIT_MASK_HOST_MSG_1_8821C) - - +#define BIT_HOST_MSG_1_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_1_8821C) << BIT_SHIFT_HOST_MSG_1_8821C) +#define BITS_HOST_MSG_1_8821C \ + (BIT_MASK_HOST_MSG_1_8821C << BIT_SHIFT_HOST_MSG_1_8821C) +#define BIT_CLEAR_HOST_MSG_1_8821C(x) ((x) & (~BITS_HOST_MSG_1_8821C)) +#define BIT_GET_HOST_MSG_1_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1_8821C) & BIT_MASK_HOST_MSG_1_8821C) +#define BIT_SET_HOST_MSG_1_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_1_8821C(x) | BIT_HOST_MSG_1_8821C(v)) /* 2 REG_HMEBOX2_8821C */ #define BIT_SHIFT_HOST_MSG_2_8821C 0 #define BIT_MASK_HOST_MSG_2_8821C 0xffffffffL -#define BIT_HOST_MSG_2_8821C(x) (((x) & BIT_MASK_HOST_MSG_2_8821C) << BIT_SHIFT_HOST_MSG_2_8821C) -#define BIT_GET_HOST_MSG_2_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8821C) & BIT_MASK_HOST_MSG_2_8821C) - - +#define BIT_HOST_MSG_2_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_2_8821C) << BIT_SHIFT_HOST_MSG_2_8821C) +#define BITS_HOST_MSG_2_8821C \ + (BIT_MASK_HOST_MSG_2_8821C << BIT_SHIFT_HOST_MSG_2_8821C) +#define BIT_CLEAR_HOST_MSG_2_8821C(x) ((x) & (~BITS_HOST_MSG_2_8821C)) +#define BIT_GET_HOST_MSG_2_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2_8821C) & BIT_MASK_HOST_MSG_2_8821C) +#define BIT_SET_HOST_MSG_2_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_2_8821C(x) | BIT_HOST_MSG_2_8821C(v)) /* 2 REG_HMEBOX3_8821C */ #define BIT_SHIFT_HOST_MSG_3_8821C 0 #define BIT_MASK_HOST_MSG_3_8821C 0xffffffffL -#define BIT_HOST_MSG_3_8821C(x) (((x) & BIT_MASK_HOST_MSG_3_8821C) << BIT_SHIFT_HOST_MSG_3_8821C) -#define BIT_GET_HOST_MSG_3_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8821C) & BIT_MASK_HOST_MSG_3_8821C) - - - -/* 2 REG_LLT_INIT_8821C */ - -#define BIT_SHIFT_LLTE_RWM_8821C 30 -#define BIT_MASK_LLTE_RWM_8821C 0x3 -#define BIT_LLTE_RWM_8821C(x) (((x) & BIT_MASK_LLTE_RWM_8821C) << BIT_SHIFT_LLTE_RWM_8821C) -#define BIT_GET_LLTE_RWM_8821C(x) (((x) >> BIT_SHIFT_LLTE_RWM_8821C) & BIT_MASK_LLTE_RWM_8821C) - - - -#define BIT_SHIFT_LLTINI_PDATA_V1_8821C 16 -#define BIT_MASK_LLTINI_PDATA_V1_8821C 0xfff -#define BIT_LLTINI_PDATA_V1_8821C(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8821C) << BIT_SHIFT_LLTINI_PDATA_V1_8821C) -#define BIT_GET_LLTINI_PDATA_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8821C) & BIT_MASK_LLTINI_PDATA_V1_8821C) - - - -#define BIT_SHIFT_LLTINI_HDATA_V1_8821C 0 -#define BIT_MASK_LLTINI_HDATA_V1_8821C 0xfff -#define BIT_LLTINI_HDATA_V1_8821C(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8821C) << BIT_SHIFT_LLTINI_HDATA_V1_8821C) -#define BIT_GET_LLTINI_HDATA_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8821C) & BIT_MASK_LLTINI_HDATA_V1_8821C) - - - -/* 2 REG_LLT_INIT_ADDR_8821C */ - -#define BIT_SHIFT_LLTINI_ADDR_V1_8821C 0 -#define BIT_MASK_LLTINI_ADDR_V1_8821C 0xfff -#define BIT_LLTINI_ADDR_V1_8821C(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8821C) << BIT_SHIFT_LLTINI_ADDR_V1_8821C) -#define BIT_GET_LLTINI_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8821C) & BIT_MASK_LLTINI_ADDR_V1_8821C) +#define BIT_HOST_MSG_3_8821C(x) \ + (((x) & BIT_MASK_HOST_MSG_3_8821C) << BIT_SHIFT_HOST_MSG_3_8821C) +#define BITS_HOST_MSG_3_8821C \ + (BIT_MASK_HOST_MSG_3_8821C << BIT_SHIFT_HOST_MSG_3_8821C) +#define BIT_CLEAR_HOST_MSG_3_8821C(x) ((x) & (~BITS_HOST_MSG_3_8821C)) +#define BIT_GET_HOST_MSG_3_8821C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3_8821C) & BIT_MASK_HOST_MSG_3_8821C) +#define BIT_SET_HOST_MSG_3_8821C(x, v) \ + (BIT_CLEAR_HOST_MSG_3_8821C(x) | BIT_HOST_MSG_3_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_BB_ACCESS_CTRL_8821C */ #define BIT_SHIFT_BB_WRITE_READ_8821C 30 #define BIT_MASK_BB_WRITE_READ_8821C 0x3 -#define BIT_BB_WRITE_READ_8821C(x) (((x) & BIT_MASK_BB_WRITE_READ_8821C) << BIT_SHIFT_BB_WRITE_READ_8821C) -#define BIT_GET_BB_WRITE_READ_8821C(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8821C) & BIT_MASK_BB_WRITE_READ_8821C) - - +#define BIT_BB_WRITE_READ_8821C(x) \ + (((x) & BIT_MASK_BB_WRITE_READ_8821C) << BIT_SHIFT_BB_WRITE_READ_8821C) +#define BITS_BB_WRITE_READ_8821C \ + (BIT_MASK_BB_WRITE_READ_8821C << BIT_SHIFT_BB_WRITE_READ_8821C) +#define BIT_CLEAR_BB_WRITE_READ_8821C(x) ((x) & (~BITS_BB_WRITE_READ_8821C)) +#define BIT_GET_BB_WRITE_READ_8821C(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ_8821C) & BIT_MASK_BB_WRITE_READ_8821C) +#define BIT_SET_BB_WRITE_READ_8821C(x, v) \ + (BIT_CLEAR_BB_WRITE_READ_8821C(x) | BIT_BB_WRITE_READ_8821C(v)) #define BIT_SHIFT_BB_WRITE_EN_8821C 12 #define BIT_MASK_BB_WRITE_EN_8821C 0xf -#define BIT_BB_WRITE_EN_8821C(x) (((x) & BIT_MASK_BB_WRITE_EN_8821C) << BIT_SHIFT_BB_WRITE_EN_8821C) -#define BIT_GET_BB_WRITE_EN_8821C(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8821C) & BIT_MASK_BB_WRITE_EN_8821C) - - +#define BIT_BB_WRITE_EN_8821C(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_8821C) << BIT_SHIFT_BB_WRITE_EN_8821C) +#define BITS_BB_WRITE_EN_8821C \ + (BIT_MASK_BB_WRITE_EN_8821C << BIT_SHIFT_BB_WRITE_EN_8821C) +#define BIT_CLEAR_BB_WRITE_EN_8821C(x) ((x) & (~BITS_BB_WRITE_EN_8821C)) +#define BIT_GET_BB_WRITE_EN_8821C(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_8821C) & BIT_MASK_BB_WRITE_EN_8821C) +#define BIT_SET_BB_WRITE_EN_8821C(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_8821C(x) | BIT_BB_WRITE_EN_8821C(v)) #define BIT_SHIFT_BB_ADDR_8821C 2 #define BIT_MASK_BB_ADDR_8821C 0x1ff -#define BIT_BB_ADDR_8821C(x) (((x) & BIT_MASK_BB_ADDR_8821C) << BIT_SHIFT_BB_ADDR_8821C) -#define BIT_GET_BB_ADDR_8821C(x) (((x) >> BIT_SHIFT_BB_ADDR_8821C) & BIT_MASK_BB_ADDR_8821C) - +#define BIT_BB_ADDR_8821C(x) \ + (((x) & BIT_MASK_BB_ADDR_8821C) << BIT_SHIFT_BB_ADDR_8821C) +#define BITS_BB_ADDR_8821C (BIT_MASK_BB_ADDR_8821C << BIT_SHIFT_BB_ADDR_8821C) +#define BIT_CLEAR_BB_ADDR_8821C(x) ((x) & (~BITS_BB_ADDR_8821C)) +#define BIT_GET_BB_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_8821C) & BIT_MASK_BB_ADDR_8821C) +#define BIT_SET_BB_ADDR_8821C(x, v) \ + (BIT_CLEAR_BB_ADDR_8821C(x) | BIT_BB_ADDR_8821C(v)) #define BIT_BB_ERRACC_8821C BIT(0) @@ -2925,55 +4406,84 @@ #define BIT_SHIFT_BB_DATA_8821C 0 #define BIT_MASK_BB_DATA_8821C 0xffffffffL -#define BIT_BB_DATA_8821C(x) (((x) & BIT_MASK_BB_DATA_8821C) << BIT_SHIFT_BB_DATA_8821C) -#define BIT_GET_BB_DATA_8821C(x) (((x) >> BIT_SHIFT_BB_DATA_8821C) & BIT_MASK_BB_DATA_8821C) - - +#define BIT_BB_DATA_8821C(x) \ + (((x) & BIT_MASK_BB_DATA_8821C) << BIT_SHIFT_BB_DATA_8821C) +#define BITS_BB_DATA_8821C (BIT_MASK_BB_DATA_8821C << BIT_SHIFT_BB_DATA_8821C) +#define BIT_CLEAR_BB_DATA_8821C(x) ((x) & (~BITS_BB_DATA_8821C)) +#define BIT_GET_BB_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_BB_DATA_8821C) & BIT_MASK_BB_DATA_8821C) +#define BIT_SET_BB_DATA_8821C(x, v) \ + (BIT_CLEAR_BB_DATA_8821C(x) | BIT_BB_DATA_8821C(v)) /* 2 REG_HMEBOX_E0_8821C */ #define BIT_SHIFT_HMEBOX_E0_8821C 0 #define BIT_MASK_HMEBOX_E0_8821C 0xffffffffL -#define BIT_HMEBOX_E0_8821C(x) (((x) & BIT_MASK_HMEBOX_E0_8821C) << BIT_SHIFT_HMEBOX_E0_8821C) -#define BIT_GET_HMEBOX_E0_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8821C) & BIT_MASK_HMEBOX_E0_8821C) - - +#define BIT_HMEBOX_E0_8821C(x) \ + (((x) & BIT_MASK_HMEBOX_E0_8821C) << BIT_SHIFT_HMEBOX_E0_8821C) +#define BITS_HMEBOX_E0_8821C \ + (BIT_MASK_HMEBOX_E0_8821C << BIT_SHIFT_HMEBOX_E0_8821C) +#define BIT_CLEAR_HMEBOX_E0_8821C(x) ((x) & (~BITS_HMEBOX_E0_8821C)) +#define BIT_GET_HMEBOX_E0_8821C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E0_8821C) & BIT_MASK_HMEBOX_E0_8821C) +#define BIT_SET_HMEBOX_E0_8821C(x, v) \ + (BIT_CLEAR_HMEBOX_E0_8821C(x) | BIT_HMEBOX_E0_8821C(v)) /* 2 REG_HMEBOX_E1_8821C */ #define BIT_SHIFT_HMEBOX_E1_8821C 0 #define BIT_MASK_HMEBOX_E1_8821C 0xffffffffL -#define BIT_HMEBOX_E1_8821C(x) (((x) & BIT_MASK_HMEBOX_E1_8821C) << BIT_SHIFT_HMEBOX_E1_8821C) -#define BIT_GET_HMEBOX_E1_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8821C) & BIT_MASK_HMEBOX_E1_8821C) - - +#define BIT_HMEBOX_E1_8821C(x) \ + (((x) & BIT_MASK_HMEBOX_E1_8821C) << BIT_SHIFT_HMEBOX_E1_8821C) +#define BITS_HMEBOX_E1_8821C \ + (BIT_MASK_HMEBOX_E1_8821C << BIT_SHIFT_HMEBOX_E1_8821C) +#define BIT_CLEAR_HMEBOX_E1_8821C(x) ((x) & (~BITS_HMEBOX_E1_8821C)) +#define BIT_GET_HMEBOX_E1_8821C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E1_8821C) & BIT_MASK_HMEBOX_E1_8821C) +#define BIT_SET_HMEBOX_E1_8821C(x, v) \ + (BIT_CLEAR_HMEBOX_E1_8821C(x) | BIT_HMEBOX_E1_8821C(v)) /* 2 REG_HMEBOX_E2_8821C */ #define BIT_SHIFT_HMEBOX_E2_8821C 0 #define BIT_MASK_HMEBOX_E2_8821C 0xffffffffL -#define BIT_HMEBOX_E2_8821C(x) (((x) & BIT_MASK_HMEBOX_E2_8821C) << BIT_SHIFT_HMEBOX_E2_8821C) -#define BIT_GET_HMEBOX_E2_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8821C) & BIT_MASK_HMEBOX_E2_8821C) - - +#define BIT_HMEBOX_E2_8821C(x) \ + (((x) & BIT_MASK_HMEBOX_E2_8821C) << BIT_SHIFT_HMEBOX_E2_8821C) +#define BITS_HMEBOX_E2_8821C \ + (BIT_MASK_HMEBOX_E2_8821C << BIT_SHIFT_HMEBOX_E2_8821C) +#define BIT_CLEAR_HMEBOX_E2_8821C(x) ((x) & (~BITS_HMEBOX_E2_8821C)) +#define BIT_GET_HMEBOX_E2_8821C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E2_8821C) & BIT_MASK_HMEBOX_E2_8821C) +#define BIT_SET_HMEBOX_E2_8821C(x, v) \ + (BIT_CLEAR_HMEBOX_E2_8821C(x) | BIT_HMEBOX_E2_8821C(v)) /* 2 REG_HMEBOX_E3_8821C */ #define BIT_SHIFT_HMEBOX_E3_8821C 0 #define BIT_MASK_HMEBOX_E3_8821C 0xffffffffL -#define BIT_HMEBOX_E3_8821C(x) (((x) & BIT_MASK_HMEBOX_E3_8821C) << BIT_SHIFT_HMEBOX_E3_8821C) -#define BIT_GET_HMEBOX_E3_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8821C) & BIT_MASK_HMEBOX_E3_8821C) - - +#define BIT_HMEBOX_E3_8821C(x) \ + (((x) & BIT_MASK_HMEBOX_E3_8821C) << BIT_SHIFT_HMEBOX_E3_8821C) +#define BITS_HMEBOX_E3_8821C \ + (BIT_MASK_HMEBOX_E3_8821C << BIT_SHIFT_HMEBOX_E3_8821C) +#define BIT_CLEAR_HMEBOX_E3_8821C(x) ((x) & (~BITS_HMEBOX_E3_8821C)) +#define BIT_GET_HMEBOX_E3_8821C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E3_8821C) & BIT_MASK_HMEBOX_E3_8821C) +#define BIT_SET_HMEBOX_E3_8821C(x, v) \ + (BIT_CLEAR_HMEBOX_E3_8821C(x) | BIT_HMEBOX_E3_8821C(v)) /* 2 REG_CR_EXT_8821C */ #define BIT_SHIFT_PHY_REQ_DELAY_8821C 24 #define BIT_MASK_PHY_REQ_DELAY_8821C 0xf -#define BIT_PHY_REQ_DELAY_8821C(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8821C) << BIT_SHIFT_PHY_REQ_DELAY_8821C) -#define BIT_GET_PHY_REQ_DELAY_8821C(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8821C) & BIT_MASK_PHY_REQ_DELAY_8821C) - - +#define BIT_PHY_REQ_DELAY_8821C(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY_8821C) << BIT_SHIFT_PHY_REQ_DELAY_8821C) +#define BITS_PHY_REQ_DELAY_8821C \ + (BIT_MASK_PHY_REQ_DELAY_8821C << BIT_SHIFT_PHY_REQ_DELAY_8821C) +#define BIT_CLEAR_PHY_REQ_DELAY_8821C(x) ((x) & (~BITS_PHY_REQ_DELAY_8821C)) +#define BIT_GET_PHY_REQ_DELAY_8821C(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8821C) & BIT_MASK_PHY_REQ_DELAY_8821C) +#define BIT_SET_PHY_REQ_DELAY_8821C(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY_8821C(x) | BIT_PHY_REQ_DELAY_8821C(v)) /* 2 REG_NOT_VALID_8821C */ #define BIT_SPD_DOWN_8821C BIT(16) @@ -2982,24 +4492,36 @@ #define BIT_SHIFT_NETYPE4_8821C 4 #define BIT_MASK_NETYPE4_8821C 0x3 -#define BIT_NETYPE4_8821C(x) (((x) & BIT_MASK_NETYPE4_8821C) << BIT_SHIFT_NETYPE4_8821C) -#define BIT_GET_NETYPE4_8821C(x) (((x) >> BIT_SHIFT_NETYPE4_8821C) & BIT_MASK_NETYPE4_8821C) - - +#define BIT_NETYPE4_8821C(x) \ + (((x) & BIT_MASK_NETYPE4_8821C) << BIT_SHIFT_NETYPE4_8821C) +#define BITS_NETYPE4_8821C (BIT_MASK_NETYPE4_8821C << BIT_SHIFT_NETYPE4_8821C) +#define BIT_CLEAR_NETYPE4_8821C(x) ((x) & (~BITS_NETYPE4_8821C)) +#define BIT_GET_NETYPE4_8821C(x) \ + (((x) >> BIT_SHIFT_NETYPE4_8821C) & BIT_MASK_NETYPE4_8821C) +#define BIT_SET_NETYPE4_8821C(x, v) \ + (BIT_CLEAR_NETYPE4_8821C(x) | BIT_NETYPE4_8821C(v)) #define BIT_SHIFT_NETYPE3_8821C 2 #define BIT_MASK_NETYPE3_8821C 0x3 -#define BIT_NETYPE3_8821C(x) (((x) & BIT_MASK_NETYPE3_8821C) << BIT_SHIFT_NETYPE3_8821C) -#define BIT_GET_NETYPE3_8821C(x) (((x) >> BIT_SHIFT_NETYPE3_8821C) & BIT_MASK_NETYPE3_8821C) - - +#define BIT_NETYPE3_8821C(x) \ + (((x) & BIT_MASK_NETYPE3_8821C) << BIT_SHIFT_NETYPE3_8821C) +#define BITS_NETYPE3_8821C (BIT_MASK_NETYPE3_8821C << BIT_SHIFT_NETYPE3_8821C) +#define BIT_CLEAR_NETYPE3_8821C(x) ((x) & (~BITS_NETYPE3_8821C)) +#define BIT_GET_NETYPE3_8821C(x) \ + (((x) >> BIT_SHIFT_NETYPE3_8821C) & BIT_MASK_NETYPE3_8821C) +#define BIT_SET_NETYPE3_8821C(x, v) \ + (BIT_CLEAR_NETYPE3_8821C(x) | BIT_NETYPE3_8821C(v)) #define BIT_SHIFT_NETYPE2_8821C 0 #define BIT_MASK_NETYPE2_8821C 0x3 -#define BIT_NETYPE2_8821C(x) (((x) & BIT_MASK_NETYPE2_8821C) << BIT_SHIFT_NETYPE2_8821C) -#define BIT_GET_NETYPE2_8821C(x) (((x) >> BIT_SHIFT_NETYPE2_8821C) & BIT_MASK_NETYPE2_8821C) - - +#define BIT_NETYPE2_8821C(x) \ + (((x) & BIT_MASK_NETYPE2_8821C) << BIT_SHIFT_NETYPE2_8821C) +#define BITS_NETYPE2_8821C (BIT_MASK_NETYPE2_8821C << BIT_SHIFT_NETYPE2_8821C) +#define BIT_CLEAR_NETYPE2_8821C(x) ((x) & (~BITS_NETYPE2_8821C)) +#define BIT_GET_NETYPE2_8821C(x) \ + (((x) >> BIT_SHIFT_NETYPE2_8821C) & BIT_MASK_NETYPE2_8821C) +#define BIT_SET_NETYPE2_8821C(x, v) \ + (BIT_CLEAR_NETYPE2_8821C(x) | BIT_NETYPE2_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -3013,24 +4535,39 @@ #define BIT_SHIFT_PKTNUM_TH_V1_8821C 24 #define BIT_MASK_PKTNUM_TH_V1_8821C 0xff -#define BIT_PKTNUM_TH_V1_8821C(x) (((x) & BIT_MASK_PKTNUM_TH_V1_8821C) << BIT_SHIFT_PKTNUM_TH_V1_8821C) -#define BIT_GET_PKTNUM_TH_V1_8821C(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8821C) & BIT_MASK_PKTNUM_TH_V1_8821C) - - +#define BIT_PKTNUM_TH_V1_8821C(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V1_8821C) << BIT_SHIFT_PKTNUM_TH_V1_8821C) +#define BITS_PKTNUM_TH_V1_8821C \ + (BIT_MASK_PKTNUM_TH_V1_8821C << BIT_SHIFT_PKTNUM_TH_V1_8821C) +#define BIT_CLEAR_PKTNUM_TH_V1_8821C(x) ((x) & (~BITS_PKTNUM_TH_V1_8821C)) +#define BIT_GET_PKTNUM_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8821C) & BIT_MASK_PKTNUM_TH_V1_8821C) +#define BIT_SET_PKTNUM_TH_V1_8821C(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V1_8821C(x) | BIT_PKTNUM_TH_V1_8821C(v)) #define BIT_SHIFT_TIMER_TH_8821C 16 #define BIT_MASK_TIMER_TH_8821C 0xff -#define BIT_TIMER_TH_8821C(x) (((x) & BIT_MASK_TIMER_TH_8821C) << BIT_SHIFT_TIMER_TH_8821C) -#define BIT_GET_TIMER_TH_8821C(x) (((x) >> BIT_SHIFT_TIMER_TH_8821C) & BIT_MASK_TIMER_TH_8821C) - - +#define BIT_TIMER_TH_8821C(x) \ + (((x) & BIT_MASK_TIMER_TH_8821C) << BIT_SHIFT_TIMER_TH_8821C) +#define BITS_TIMER_TH_8821C \ + (BIT_MASK_TIMER_TH_8821C << BIT_SHIFT_TIMER_TH_8821C) +#define BIT_CLEAR_TIMER_TH_8821C(x) ((x) & (~BITS_TIMER_TH_8821C)) +#define BIT_GET_TIMER_TH_8821C(x) \ + (((x) >> BIT_SHIFT_TIMER_TH_8821C) & BIT_MASK_TIMER_TH_8821C) +#define BIT_SET_TIMER_TH_8821C(x, v) \ + (BIT_CLEAR_TIMER_TH_8821C(x) | BIT_TIMER_TH_8821C(v)) #define BIT_SHIFT_RXPKT1ENADDR_8821C 0 #define BIT_MASK_RXPKT1ENADDR_8821C 0xffff -#define BIT_RXPKT1ENADDR_8821C(x) (((x) & BIT_MASK_RXPKT1ENADDR_8821C) << BIT_SHIFT_RXPKT1ENADDR_8821C) -#define BIT_GET_RXPKT1ENADDR_8821C(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8821C) & BIT_MASK_RXPKT1ENADDR_8821C) - - +#define BIT_RXPKT1ENADDR_8821C(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR_8821C) << BIT_SHIFT_RXPKT1ENADDR_8821C) +#define BITS_RXPKT1ENADDR_8821C \ + (BIT_MASK_RXPKT1ENADDR_8821C << BIT_SHIFT_RXPKT1ENADDR_8821C) +#define BIT_CLEAR_RXPKT1ENADDR_8821C(x) ((x) & (~BITS_RXPKT1ENADDR_8821C)) +#define BIT_GET_RXPKT1ENADDR_8821C(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR_8821C) & BIT_MASK_RXPKT1ENADDR_8821C) +#define BIT_SET_RXPKT1ENADDR_8821C(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR_8821C(x) | BIT_RXPKT1ENADDR_8821C(v)) /* 2 REG_RXFF_PTR_V1_8821C */ @@ -3038,10 +4575,17 @@ #define BIT_SHIFT_RXFF0_RDPTR_V2_8821C 0 #define BIT_MASK_RXFF0_RDPTR_V2_8821C 0x3ffff -#define BIT_RXFF0_RDPTR_V2_8821C(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8821C) << BIT_SHIFT_RXFF0_RDPTR_V2_8821C) -#define BIT_GET_RXFF0_RDPTR_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8821C) & BIT_MASK_RXFF0_RDPTR_V2_8821C) - - +#define BIT_RXFF0_RDPTR_V2_8821C(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2_8821C) \ + << BIT_SHIFT_RXFF0_RDPTR_V2_8821C) +#define BITS_RXFF0_RDPTR_V2_8821C \ + (BIT_MASK_RXFF0_RDPTR_V2_8821C << BIT_SHIFT_RXFF0_RDPTR_V2_8821C) +#define BIT_CLEAR_RXFF0_RDPTR_V2_8821C(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8821C)) +#define BIT_GET_RXFF0_RDPTR_V2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8821C) & \ + BIT_MASK_RXFF0_RDPTR_V2_8821C) +#define BIT_SET_RXFF0_RDPTR_V2_8821C(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2_8821C(x) | BIT_RXFF0_RDPTR_V2_8821C(v)) /* 2 REG_RXFF_WTR_V1_8821C */ @@ -3049,10 +4593,17 @@ #define BIT_SHIFT_RXFF0_WTPTR_V2_8821C 0 #define BIT_MASK_RXFF0_WTPTR_V2_8821C 0x3ffff -#define BIT_RXFF0_WTPTR_V2_8821C(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8821C) << BIT_SHIFT_RXFF0_WTPTR_V2_8821C) -#define BIT_GET_RXFF0_WTPTR_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8821C) & BIT_MASK_RXFF0_WTPTR_V2_8821C) - - +#define BIT_RXFF0_WTPTR_V2_8821C(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2_8821C) \ + << BIT_SHIFT_RXFF0_WTPTR_V2_8821C) +#define BITS_RXFF0_WTPTR_V2_8821C \ + (BIT_MASK_RXFF0_WTPTR_V2_8821C << BIT_SHIFT_RXFF0_WTPTR_V2_8821C) +#define BIT_CLEAR_RXFF0_WTPTR_V2_8821C(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8821C)) +#define BIT_GET_RXFF0_WTPTR_V2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8821C) & \ + BIT_MASK_RXFF0_WTPTR_V2_8821C) +#define BIT_SET_RXFF0_WTPTR_V2_8821C(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2_8821C(x) | BIT_RXFF0_WTPTR_V2_8821C(v)) /* 2 REG_FE2IMR_8821C */ #define BIT__FE4ISR__IND_MSK_8821C BIT(29) @@ -3286,53 +4837,82 @@ #define BIT_SHIFT_MID_31TO0_8821C 0 #define BIT_MASK_MID_31TO0_8821C 0xffffffffL -#define BIT_MID_31TO0_8821C(x) (((x) & BIT_MASK_MID_31TO0_8821C) << BIT_SHIFT_MID_31TO0_8821C) -#define BIT_GET_MID_31TO0_8821C(x) (((x) >> BIT_SHIFT_MID_31TO0_8821C) & BIT_MASK_MID_31TO0_8821C) - - +#define BIT_MID_31TO0_8821C(x) \ + (((x) & BIT_MASK_MID_31TO0_8821C) << BIT_SHIFT_MID_31TO0_8821C) +#define BITS_MID_31TO0_8821C \ + (BIT_MASK_MID_31TO0_8821C << BIT_SHIFT_MID_31TO0_8821C) +#define BIT_CLEAR_MID_31TO0_8821C(x) ((x) & (~BITS_MID_31TO0_8821C)) +#define BIT_GET_MID_31TO0_8821C(x) \ + (((x) >> BIT_SHIFT_MID_31TO0_8821C) & BIT_MASK_MID_31TO0_8821C) +#define BIT_SET_MID_31TO0_8821C(x, v) \ + (BIT_CLEAR_MID_31TO0_8821C(x) | BIT_MID_31TO0_8821C(v)) /* 2 REG_SPWR1_8821C */ #define BIT_SHIFT_MID_63TO32_8821C 0 #define BIT_MASK_MID_63TO32_8821C 0xffffffffL -#define BIT_MID_63TO32_8821C(x) (((x) & BIT_MASK_MID_63TO32_8821C) << BIT_SHIFT_MID_63TO32_8821C) -#define BIT_GET_MID_63TO32_8821C(x) (((x) >> BIT_SHIFT_MID_63TO32_8821C) & BIT_MASK_MID_63TO32_8821C) - - +#define BIT_MID_63TO32_8821C(x) \ + (((x) & BIT_MASK_MID_63TO32_8821C) << BIT_SHIFT_MID_63TO32_8821C) +#define BITS_MID_63TO32_8821C \ + (BIT_MASK_MID_63TO32_8821C << BIT_SHIFT_MID_63TO32_8821C) +#define BIT_CLEAR_MID_63TO32_8821C(x) ((x) & (~BITS_MID_63TO32_8821C)) +#define BIT_GET_MID_63TO32_8821C(x) \ + (((x) >> BIT_SHIFT_MID_63TO32_8821C) & BIT_MASK_MID_63TO32_8821C) +#define BIT_SET_MID_63TO32_8821C(x, v) \ + (BIT_CLEAR_MID_63TO32_8821C(x) | BIT_MID_63TO32_8821C(v)) /* 2 REG_SPWR2_8821C */ #define BIT_SHIFT_MID_95O64_8821C 0 #define BIT_MASK_MID_95O64_8821C 0xffffffffL -#define BIT_MID_95O64_8821C(x) (((x) & BIT_MASK_MID_95O64_8821C) << BIT_SHIFT_MID_95O64_8821C) -#define BIT_GET_MID_95O64_8821C(x) (((x) >> BIT_SHIFT_MID_95O64_8821C) & BIT_MASK_MID_95O64_8821C) - - +#define BIT_MID_95O64_8821C(x) \ + (((x) & BIT_MASK_MID_95O64_8821C) << BIT_SHIFT_MID_95O64_8821C) +#define BITS_MID_95O64_8821C \ + (BIT_MASK_MID_95O64_8821C << BIT_SHIFT_MID_95O64_8821C) +#define BIT_CLEAR_MID_95O64_8821C(x) ((x) & (~BITS_MID_95O64_8821C)) +#define BIT_GET_MID_95O64_8821C(x) \ + (((x) >> BIT_SHIFT_MID_95O64_8821C) & BIT_MASK_MID_95O64_8821C) +#define BIT_SET_MID_95O64_8821C(x, v) \ + (BIT_CLEAR_MID_95O64_8821C(x) | BIT_MID_95O64_8821C(v)) /* 2 REG_SPWR3_8821C */ #define BIT_SHIFT_MID_127TO96_8821C 0 #define BIT_MASK_MID_127TO96_8821C 0xffffffffL -#define BIT_MID_127TO96_8821C(x) (((x) & BIT_MASK_MID_127TO96_8821C) << BIT_SHIFT_MID_127TO96_8821C) -#define BIT_GET_MID_127TO96_8821C(x) (((x) >> BIT_SHIFT_MID_127TO96_8821C) & BIT_MASK_MID_127TO96_8821C) - - +#define BIT_MID_127TO96_8821C(x) \ + (((x) & BIT_MASK_MID_127TO96_8821C) << BIT_SHIFT_MID_127TO96_8821C) +#define BITS_MID_127TO96_8821C \ + (BIT_MASK_MID_127TO96_8821C << BIT_SHIFT_MID_127TO96_8821C) +#define BIT_CLEAR_MID_127TO96_8821C(x) ((x) & (~BITS_MID_127TO96_8821C)) +#define BIT_GET_MID_127TO96_8821C(x) \ + (((x) >> BIT_SHIFT_MID_127TO96_8821C) & BIT_MASK_MID_127TO96_8821C) +#define BIT_SET_MID_127TO96_8821C(x, v) \ + (BIT_CLEAR_MID_127TO96_8821C(x) | BIT_MID_127TO96_8821C(v)) /* 2 REG_POWSEQ_8821C */ #define BIT_SHIFT_SEQNUM_MID_8821C 16 #define BIT_MASK_SEQNUM_MID_8821C 0xffff -#define BIT_SEQNUM_MID_8821C(x) (((x) & BIT_MASK_SEQNUM_MID_8821C) << BIT_SHIFT_SEQNUM_MID_8821C) -#define BIT_GET_SEQNUM_MID_8821C(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8821C) & BIT_MASK_SEQNUM_MID_8821C) - - +#define BIT_SEQNUM_MID_8821C(x) \ + (((x) & BIT_MASK_SEQNUM_MID_8821C) << BIT_SHIFT_SEQNUM_MID_8821C) +#define BITS_SEQNUM_MID_8821C \ + (BIT_MASK_SEQNUM_MID_8821C << BIT_SHIFT_SEQNUM_MID_8821C) +#define BIT_CLEAR_SEQNUM_MID_8821C(x) ((x) & (~BITS_SEQNUM_MID_8821C)) +#define BIT_GET_SEQNUM_MID_8821C(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID_8821C) & BIT_MASK_SEQNUM_MID_8821C) +#define BIT_SET_SEQNUM_MID_8821C(x, v) \ + (BIT_CLEAR_SEQNUM_MID_8821C(x) | BIT_SEQNUM_MID_8821C(v)) #define BIT_SHIFT_REF_MID_8821C 0 #define BIT_MASK_REF_MID_8821C 0x7f -#define BIT_REF_MID_8821C(x) (((x) & BIT_MASK_REF_MID_8821C) << BIT_SHIFT_REF_MID_8821C) -#define BIT_GET_REF_MID_8821C(x) (((x) >> BIT_SHIFT_REF_MID_8821C) & BIT_MASK_REF_MID_8821C) - - +#define BIT_REF_MID_8821C(x) \ + (((x) & BIT_MASK_REF_MID_8821C) << BIT_SHIFT_REF_MID_8821C) +#define BITS_REF_MID_8821C (BIT_MASK_REF_MID_8821C << BIT_SHIFT_REF_MID_8821C) +#define BIT_CLEAR_REF_MID_8821C(x) ((x) & (~BITS_REF_MID_8821C)) +#define BIT_GET_REF_MID_8821C(x) \ + (((x) >> BIT_SHIFT_REF_MID_8821C) & BIT_MASK_REF_MID_8821C) +#define BIT_SET_REF_MID_8821C(x, v) \ + (BIT_CLEAR_REF_MID_8821C(x) | BIT_REF_MID_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -3343,10 +4923,14 @@ #define BIT_SHIFT_TC7DATA_8821C 0 #define BIT_MASK_TC7DATA_8821C 0xffffff -#define BIT_TC7DATA_8821C(x) (((x) & BIT_MASK_TC7DATA_8821C) << BIT_SHIFT_TC7DATA_8821C) -#define BIT_GET_TC7DATA_8821C(x) (((x) >> BIT_SHIFT_TC7DATA_8821C) & BIT_MASK_TC7DATA_8821C) - - +#define BIT_TC7DATA_8821C(x) \ + (((x) & BIT_MASK_TC7DATA_8821C) << BIT_SHIFT_TC7DATA_8821C) +#define BITS_TC7DATA_8821C (BIT_MASK_TC7DATA_8821C << BIT_SHIFT_TC7DATA_8821C) +#define BIT_CLEAR_TC7DATA_8821C(x) ((x) & (~BITS_TC7DATA_8821C)) +#define BIT_GET_TC7DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC7DATA_8821C) & BIT_MASK_TC7DATA_8821C) +#define BIT_SET_TC7DATA_8821C(x, v) \ + (BIT_CLEAR_TC7DATA_8821C(x) | BIT_TC7DATA_8821C(v)) /* 2 REG_TC8_CTRL_V1_8821C */ #define BIT_TC8INT_EN_8821C BIT(26) @@ -3355,42 +4939,110 @@ #define BIT_SHIFT_TC8DATA_8821C 0 #define BIT_MASK_TC8DATA_8821C 0xffffff -#define BIT_TC8DATA_8821C(x) (((x) & BIT_MASK_TC8DATA_8821C) << BIT_SHIFT_TC8DATA_8821C) -#define BIT_GET_TC8DATA_8821C(x) (((x) >> BIT_SHIFT_TC8DATA_8821C) & BIT_MASK_TC8DATA_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_TC8DATA_8821C(x) \ + (((x) & BIT_MASK_TC8DATA_8821C) << BIT_SHIFT_TC8DATA_8821C) +#define BITS_TC8DATA_8821C (BIT_MASK_TC8DATA_8821C << BIT_SHIFT_TC8DATA_8821C) +#define BIT_CLEAR_TC8DATA_8821C(x) ((x) & (~BITS_TC8DATA_8821C)) +#define BIT_GET_TC8DATA_8821C(x) \ + (((x) >> BIT_SHIFT_TC8DATA_8821C) & BIT_MASK_TC8DATA_8821C) +#define BIT_SET_TC8DATA_8821C(x, v) \ + (BIT_CLEAR_TC8DATA_8821C(x) | BIT_TC8DATA_8821C(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL0_8821C */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C 24 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8821C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8821C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT2_8821C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C 16 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8821C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8821C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT1_8821C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C 8 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8821C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8821C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT0_8821C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C 0xff +#define BIT_RX_BCN_TBTT_ITVL_PORT0_8821C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C) +#define BITS_RX_BCN_TBTT_ITVL_PORT0_8821C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8821C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8821C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8821C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C) +#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8821C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8821C(x) | \ + BIT_RX_BCN_TBTT_ITVL_PORT0_8821C(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL1_8821C */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8821C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8821C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT3_8821C(v)) /* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_IO_WRAP_ERR_FLAG_8821C */ +#define BIT_IO_WRAP_ERR_8821C BIT(0) /* 2 REG_NOT_VALID_8821C */ @@ -3398,7 +5050,149 @@ /* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_SPEED_SENSOR_8821C */ +#define BIT_DSS_1_RST_N_8821C BIT(31) +#define BIT_DSS_1_SPEED_EN_8821C BIT(30) +#define BIT_DSS_1_WIRE_SEL_8821C BIT(29) +#define BIT_DSS_ENCLK_8821C BIT(28) + +#define BIT_SHIFT_DSS_1_RO_SEL_8821C 24 +#define BIT_MASK_DSS_1_RO_SEL_8821C 0x7 +#define BIT_DSS_1_RO_SEL_8821C(x) \ + (((x) & BIT_MASK_DSS_1_RO_SEL_8821C) << BIT_SHIFT_DSS_1_RO_SEL_8821C) +#define BITS_DSS_1_RO_SEL_8821C \ + (BIT_MASK_DSS_1_RO_SEL_8821C << BIT_SHIFT_DSS_1_RO_SEL_8821C) +#define BIT_CLEAR_DSS_1_RO_SEL_8821C(x) ((x) & (~BITS_DSS_1_RO_SEL_8821C)) +#define BIT_GET_DSS_1_RO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_1_RO_SEL_8821C) & BIT_MASK_DSS_1_RO_SEL_8821C) +#define BIT_SET_DSS_1_RO_SEL_8821C(x, v) \ + (BIT_CLEAR_DSS_1_RO_SEL_8821C(x) | BIT_DSS_1_RO_SEL_8821C(v)) + +#define BIT_SHIFT_DSS_1_DATA_IN_8821C 0 +#define BIT_MASK_DSS_1_DATA_IN_8821C 0xfffff +#define BIT_DSS_1_DATA_IN_8821C(x) \ + (((x) & BIT_MASK_DSS_1_DATA_IN_8821C) << BIT_SHIFT_DSS_1_DATA_IN_8821C) +#define BITS_DSS_1_DATA_IN_8821C \ + (BIT_MASK_DSS_1_DATA_IN_8821C << BIT_SHIFT_DSS_1_DATA_IN_8821C) +#define BIT_CLEAR_DSS_1_DATA_IN_8821C(x) ((x) & (~BITS_DSS_1_DATA_IN_8821C)) +#define BIT_GET_DSS_1_DATA_IN_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_1_DATA_IN_8821C) & BIT_MASK_DSS_1_DATA_IN_8821C) +#define BIT_SET_DSS_1_DATA_IN_8821C(x, v) \ + (BIT_CLEAR_DSS_1_DATA_IN_8821C(x) | BIT_DSS_1_DATA_IN_8821C(v)) + +/* 2 REG_SPEED_SENSOR1_8821C */ +#define BIT_DSS_1_READY_8821C BIT(31) +#define BIT_DSS_1_WSORT_GO_8821C BIT(30) + +#define BIT_SHIFT_DSS_1_COUNT_OUT_8821C 0 +#define BIT_MASK_DSS_1_COUNT_OUT_8821C 0xfffff +#define BIT_DSS_1_COUNT_OUT_8821C(x) \ + (((x) & BIT_MASK_DSS_1_COUNT_OUT_8821C) \ + << BIT_SHIFT_DSS_1_COUNT_OUT_8821C) +#define BITS_DSS_1_COUNT_OUT_8821C \ + (BIT_MASK_DSS_1_COUNT_OUT_8821C << BIT_SHIFT_DSS_1_COUNT_OUT_8821C) +#define BIT_CLEAR_DSS_1_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8821C)) +#define BIT_GET_DSS_1_COUNT_OUT_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8821C) & \ + BIT_MASK_DSS_1_COUNT_OUT_8821C) +#define BIT_SET_DSS_1_COUNT_OUT_8821C(x, v) \ + (BIT_CLEAR_DSS_1_COUNT_OUT_8821C(x) | BIT_DSS_1_COUNT_OUT_8821C(v)) + +/* 2 REG_SPEED_SENSOR2_8821C */ +#define BIT_DSS_2_RST_N_8821C BIT(31) +#define BIT_DSS_2_SPEED_EN_8821C BIT(30) +#define BIT_DSS_2_WIRE_SEL_8821C BIT(29) +#define BIT_DSS_ENCLK_8821C BIT(28) + +#define BIT_SHIFT_DSS_2_RO_SEL_8821C 24 +#define BIT_MASK_DSS_2_RO_SEL_8821C 0x7 +#define BIT_DSS_2_RO_SEL_8821C(x) \ + (((x) & BIT_MASK_DSS_2_RO_SEL_8821C) << BIT_SHIFT_DSS_2_RO_SEL_8821C) +#define BITS_DSS_2_RO_SEL_8821C \ + (BIT_MASK_DSS_2_RO_SEL_8821C << BIT_SHIFT_DSS_2_RO_SEL_8821C) +#define BIT_CLEAR_DSS_2_RO_SEL_8821C(x) ((x) & (~BITS_DSS_2_RO_SEL_8821C)) +#define BIT_GET_DSS_2_RO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_2_RO_SEL_8821C) & BIT_MASK_DSS_2_RO_SEL_8821C) +#define BIT_SET_DSS_2_RO_SEL_8821C(x, v) \ + (BIT_CLEAR_DSS_2_RO_SEL_8821C(x) | BIT_DSS_2_RO_SEL_8821C(v)) + +#define BIT_SHIFT_DSS_2_DATA_IN_8821C 0 +#define BIT_MASK_DSS_2_DATA_IN_8821C 0xfffff +#define BIT_DSS_2_DATA_IN_8821C(x) \ + (((x) & BIT_MASK_DSS_2_DATA_IN_8821C) << BIT_SHIFT_DSS_2_DATA_IN_8821C) +#define BITS_DSS_2_DATA_IN_8821C \ + (BIT_MASK_DSS_2_DATA_IN_8821C << BIT_SHIFT_DSS_2_DATA_IN_8821C) +#define BIT_CLEAR_DSS_2_DATA_IN_8821C(x) ((x) & (~BITS_DSS_2_DATA_IN_8821C)) +#define BIT_GET_DSS_2_DATA_IN_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_2_DATA_IN_8821C) & BIT_MASK_DSS_2_DATA_IN_8821C) +#define BIT_SET_DSS_2_DATA_IN_8821C(x, v) \ + (BIT_CLEAR_DSS_2_DATA_IN_8821C(x) | BIT_DSS_2_DATA_IN_8821C(v)) + +/* 2 REG_SPEED_SENSOR3_8821C */ +#define BIT_DSS_2_READY_8821C BIT(31) +#define BIT_DSS_2_WSORT_GO_8821C BIT(30) + +#define BIT_SHIFT_DSS_2_COUNT_OUT_8821C 0 +#define BIT_MASK_DSS_2_COUNT_OUT_8821C 0xfffff +#define BIT_DSS_2_COUNT_OUT_8821C(x) \ + (((x) & BIT_MASK_DSS_2_COUNT_OUT_8821C) \ + << BIT_SHIFT_DSS_2_COUNT_OUT_8821C) +#define BITS_DSS_2_COUNT_OUT_8821C \ + (BIT_MASK_DSS_2_COUNT_OUT_8821C << BIT_SHIFT_DSS_2_COUNT_OUT_8821C) +#define BIT_CLEAR_DSS_2_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8821C)) +#define BIT_GET_DSS_2_COUNT_OUT_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8821C) & \ + BIT_MASK_DSS_2_COUNT_OUT_8821C) +#define BIT_SET_DSS_2_COUNT_OUT_8821C(x, v) \ + (BIT_CLEAR_DSS_2_COUNT_OUT_8821C(x) | BIT_DSS_2_COUNT_OUT_8821C(v)) + +/* 2 REG_SPEED_SENSOR4_8821C */ +#define BIT_DSS_3_RST_N_8821C BIT(31) +#define BIT_DSS_3_SPEED_EN_8821C BIT(30) +#define BIT_DSS_3_WIRE_SEL_8821C BIT(29) +#define BIT_DSS_ENCLK_8821C BIT(28) + +#define BIT_SHIFT_DSS_3_RO_SEL_8821C 24 +#define BIT_MASK_DSS_3_RO_SEL_8821C 0x7 +#define BIT_DSS_3_RO_SEL_8821C(x) \ + (((x) & BIT_MASK_DSS_3_RO_SEL_8821C) << BIT_SHIFT_DSS_3_RO_SEL_8821C) +#define BITS_DSS_3_RO_SEL_8821C \ + (BIT_MASK_DSS_3_RO_SEL_8821C << BIT_SHIFT_DSS_3_RO_SEL_8821C) +#define BIT_CLEAR_DSS_3_RO_SEL_8821C(x) ((x) & (~BITS_DSS_3_RO_SEL_8821C)) +#define BIT_GET_DSS_3_RO_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_3_RO_SEL_8821C) & BIT_MASK_DSS_3_RO_SEL_8821C) +#define BIT_SET_DSS_3_RO_SEL_8821C(x, v) \ + (BIT_CLEAR_DSS_3_RO_SEL_8821C(x) | BIT_DSS_3_RO_SEL_8821C(v)) + +#define BIT_SHIFT_DSS_3_DATA_IN_8821C 0 +#define BIT_MASK_DSS_3_DATA_IN_8821C 0xfffff +#define BIT_DSS_3_DATA_IN_8821C(x) \ + (((x) & BIT_MASK_DSS_3_DATA_IN_8821C) << BIT_SHIFT_DSS_3_DATA_IN_8821C) +#define BITS_DSS_3_DATA_IN_8821C \ + (BIT_MASK_DSS_3_DATA_IN_8821C << BIT_SHIFT_DSS_3_DATA_IN_8821C) +#define BIT_CLEAR_DSS_3_DATA_IN_8821C(x) ((x) & (~BITS_DSS_3_DATA_IN_8821C)) +#define BIT_GET_DSS_3_DATA_IN_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_3_DATA_IN_8821C) & BIT_MASK_DSS_3_DATA_IN_8821C) +#define BIT_SET_DSS_3_DATA_IN_8821C(x, v) \ + (BIT_CLEAR_DSS_3_DATA_IN_8821C(x) | BIT_DSS_3_DATA_IN_8821C(v)) + +/* 2 REG_SPEED_SENSOR5_8821C */ +#define BIT_DSS_3_READY_8821C BIT(31) +#define BIT_DSS_3_WSORT_GO_8821C BIT(30) + +#define BIT_SHIFT_DSS_3_COUNT_OUT_8821C 0 +#define BIT_MASK_DSS_3_COUNT_OUT_8821C 0xfffff +#define BIT_DSS_3_COUNT_OUT_8821C(x) \ + (((x) & BIT_MASK_DSS_3_COUNT_OUT_8821C) \ + << BIT_SHIFT_DSS_3_COUNT_OUT_8821C) +#define BITS_DSS_3_COUNT_OUT_8821C \ + (BIT_MASK_DSS_3_COUNT_OUT_8821C << BIT_SHIFT_DSS_3_COUNT_OUT_8821C) +#define BIT_CLEAR_DSS_3_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8821C)) +#define BIT_GET_DSS_3_COUNT_OUT_8821C(x) \ + (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8821C) & \ + BIT_MASK_DSS_3_COUNT_OUT_8821C) +#define BIT_SET_DSS_3_COUNT_OUT_8821C(x, v) \ + (BIT_CLEAR_DSS_3_COUNT_OUT_8821C(x) | BIT_DSS_3_COUNT_OUT_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -3422,7 +5216,199 @@ /* 2 REG_NOT_VALID_8821C */ -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_COUNTER_CTRL_8821C */ + +#define BIT_SHIFT_COUNTER_BASE_8821C 16 +#define BIT_MASK_COUNTER_BASE_8821C 0x1fff +#define BIT_COUNTER_BASE_8821C(x) \ + (((x) & BIT_MASK_COUNTER_BASE_8821C) << BIT_SHIFT_COUNTER_BASE_8821C) +#define BITS_COUNTER_BASE_8821C \ + (BIT_MASK_COUNTER_BASE_8821C << BIT_SHIFT_COUNTER_BASE_8821C) +#define BIT_CLEAR_COUNTER_BASE_8821C(x) ((x) & (~BITS_COUNTER_BASE_8821C)) +#define BIT_GET_COUNTER_BASE_8821C(x) \ + (((x) >> BIT_SHIFT_COUNTER_BASE_8821C) & BIT_MASK_COUNTER_BASE_8821C) +#define BIT_SET_COUNTER_BASE_8821C(x, v) \ + (BIT_CLEAR_COUNTER_BASE_8821C(x) | BIT_COUNTER_BASE_8821C(v)) + +#define BIT_EN_RTS_REQ_8821C BIT(9) +#define BIT_EN_EDCA_REQ_8821C BIT(8) +#define BIT_EN_PTCL_REQ_8821C BIT(7) +#define BIT_EN_SCH_REQ_8821C BIT(6) +#define BIT_USB_COUNT_EN_8821C BIT(5) +#define BIT_PCIE_COUNT_EN_8821C BIT(4) +#define BIT_RQPN_COUNT_EN_8821C BIT(3) +#define BIT_RDE_COUNT_EN_8821C BIT(2) +#define BIT_TDE_COUNT_EN_8821C BIT(1) +#define BIT_DISABLE_COUNTER_8821C BIT(0) + +/* 2 REG_COUNTER_THRESHOLD_8821C */ +#define BIT_SEL_ALL_MACID_8821C BIT(31) + +#define BIT_SHIFT_COUNTER_MACID_8821C 24 +#define BIT_MASK_COUNTER_MACID_8821C 0x7f +#define BIT_COUNTER_MACID_8821C(x) \ + (((x) & BIT_MASK_COUNTER_MACID_8821C) << BIT_SHIFT_COUNTER_MACID_8821C) +#define BITS_COUNTER_MACID_8821C \ + (BIT_MASK_COUNTER_MACID_8821C << BIT_SHIFT_COUNTER_MACID_8821C) +#define BIT_CLEAR_COUNTER_MACID_8821C(x) ((x) & (~BITS_COUNTER_MACID_8821C)) +#define BIT_GET_COUNTER_MACID_8821C(x) \ + (((x) >> BIT_SHIFT_COUNTER_MACID_8821C) & BIT_MASK_COUNTER_MACID_8821C) +#define BIT_SET_COUNTER_MACID_8821C(x, v) \ + (BIT_CLEAR_COUNTER_MACID_8821C(x) | BIT_COUNTER_MACID_8821C(v)) + +#define BIT_SHIFT_AGG_VALUE2_8821C 16 +#define BIT_MASK_AGG_VALUE2_8821C 0x7f +#define BIT_AGG_VALUE2_8821C(x) \ + (((x) & BIT_MASK_AGG_VALUE2_8821C) << BIT_SHIFT_AGG_VALUE2_8821C) +#define BITS_AGG_VALUE2_8821C \ + (BIT_MASK_AGG_VALUE2_8821C << BIT_SHIFT_AGG_VALUE2_8821C) +#define BIT_CLEAR_AGG_VALUE2_8821C(x) ((x) & (~BITS_AGG_VALUE2_8821C)) +#define BIT_GET_AGG_VALUE2_8821C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE2_8821C) & BIT_MASK_AGG_VALUE2_8821C) +#define BIT_SET_AGG_VALUE2_8821C(x, v) \ + (BIT_CLEAR_AGG_VALUE2_8821C(x) | BIT_AGG_VALUE2_8821C(v)) + +#define BIT_SHIFT_AGG_VALUE1_8821C 8 +#define BIT_MASK_AGG_VALUE1_8821C 0x7f +#define BIT_AGG_VALUE1_8821C(x) \ + (((x) & BIT_MASK_AGG_VALUE1_8821C) << BIT_SHIFT_AGG_VALUE1_8821C) +#define BITS_AGG_VALUE1_8821C \ + (BIT_MASK_AGG_VALUE1_8821C << BIT_SHIFT_AGG_VALUE1_8821C) +#define BIT_CLEAR_AGG_VALUE1_8821C(x) ((x) & (~BITS_AGG_VALUE1_8821C)) +#define BIT_GET_AGG_VALUE1_8821C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE1_8821C) & BIT_MASK_AGG_VALUE1_8821C) +#define BIT_SET_AGG_VALUE1_8821C(x, v) \ + (BIT_CLEAR_AGG_VALUE1_8821C(x) | BIT_AGG_VALUE1_8821C(v)) + +#define BIT_SHIFT_AGG_VALUE0_8821C 0 +#define BIT_MASK_AGG_VALUE0_8821C 0x7f +#define BIT_AGG_VALUE0_8821C(x) \ + (((x) & BIT_MASK_AGG_VALUE0_8821C) << BIT_SHIFT_AGG_VALUE0_8821C) +#define BITS_AGG_VALUE0_8821C \ + (BIT_MASK_AGG_VALUE0_8821C << BIT_SHIFT_AGG_VALUE0_8821C) +#define BIT_CLEAR_AGG_VALUE0_8821C(x) ((x) & (~BITS_AGG_VALUE0_8821C)) +#define BIT_GET_AGG_VALUE0_8821C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE0_8821C) & BIT_MASK_AGG_VALUE0_8821C) +#define BIT_SET_AGG_VALUE0_8821C(x, v) \ + (BIT_CLEAR_AGG_VALUE0_8821C(x) | BIT_AGG_VALUE0_8821C(v)) + +/* 2 REG_COUNTER_SET_8821C */ + +#define BIT_SHIFT_REQUEST_RESET_8821C 16 +#define BIT_MASK_REQUEST_RESET_8821C 0xffff +#define BIT_REQUEST_RESET_8821C(x) \ + (((x) & BIT_MASK_REQUEST_RESET_8821C) << BIT_SHIFT_REQUEST_RESET_8821C) +#define BITS_REQUEST_RESET_8821C \ + (BIT_MASK_REQUEST_RESET_8821C << BIT_SHIFT_REQUEST_RESET_8821C) +#define BIT_CLEAR_REQUEST_RESET_8821C(x) ((x) & (~BITS_REQUEST_RESET_8821C)) +#define BIT_GET_REQUEST_RESET_8821C(x) \ + (((x) >> BIT_SHIFT_REQUEST_RESET_8821C) & BIT_MASK_REQUEST_RESET_8821C) +#define BIT_SET_REQUEST_RESET_8821C(x, v) \ + (BIT_CLEAR_REQUEST_RESET_8821C(x) | BIT_REQUEST_RESET_8821C(v)) + +#define BIT_SHIFT_REQUEST_START_8821C 0 +#define BIT_MASK_REQUEST_START_8821C 0xffff +#define BIT_REQUEST_START_8821C(x) \ + (((x) & BIT_MASK_REQUEST_START_8821C) << BIT_SHIFT_REQUEST_START_8821C) +#define BITS_REQUEST_START_8821C \ + (BIT_MASK_REQUEST_START_8821C << BIT_SHIFT_REQUEST_START_8821C) +#define BIT_CLEAR_REQUEST_START_8821C(x) ((x) & (~BITS_REQUEST_START_8821C)) +#define BIT_GET_REQUEST_START_8821C(x) \ + (((x) >> BIT_SHIFT_REQUEST_START_8821C) & BIT_MASK_REQUEST_START_8821C) +#define BIT_SET_REQUEST_START_8821C(x, v) \ + (BIT_CLEAR_REQUEST_START_8821C(x) | BIT_REQUEST_START_8821C(v)) + +/* 2 REG_COUNTER_OVERFLOW_8821C */ + +#define BIT_SHIFT_CNT_OVF_REG_8821C 0 +#define BIT_MASK_CNT_OVF_REG_8821C 0xffff +#define BIT_CNT_OVF_REG_8821C(x) \ + (((x) & BIT_MASK_CNT_OVF_REG_8821C) << BIT_SHIFT_CNT_OVF_REG_8821C) +#define BITS_CNT_OVF_REG_8821C \ + (BIT_MASK_CNT_OVF_REG_8821C << BIT_SHIFT_CNT_OVF_REG_8821C) +#define BIT_CLEAR_CNT_OVF_REG_8821C(x) ((x) & (~BITS_CNT_OVF_REG_8821C)) +#define BIT_GET_CNT_OVF_REG_8821C(x) \ + (((x) >> BIT_SHIFT_CNT_OVF_REG_8821C) & BIT_MASK_CNT_OVF_REG_8821C) +#define BIT_SET_CNT_OVF_REG_8821C(x, v) \ + (BIT_CLEAR_CNT_OVF_REG_8821C(x) | BIT_CNT_OVF_REG_8821C(v)) + +/* 2 REG_TXDMA_LEN_THRESHOLD_8821C */ + +#define BIT_SHIFT_TDE_LEN_TH1_8821C 16 +#define BIT_MASK_TDE_LEN_TH1_8821C 0xffff +#define BIT_TDE_LEN_TH1_8821C(x) \ + (((x) & BIT_MASK_TDE_LEN_TH1_8821C) << BIT_SHIFT_TDE_LEN_TH1_8821C) +#define BITS_TDE_LEN_TH1_8821C \ + (BIT_MASK_TDE_LEN_TH1_8821C << BIT_SHIFT_TDE_LEN_TH1_8821C) +#define BIT_CLEAR_TDE_LEN_TH1_8821C(x) ((x) & (~BITS_TDE_LEN_TH1_8821C)) +#define BIT_GET_TDE_LEN_TH1_8821C(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH1_8821C) & BIT_MASK_TDE_LEN_TH1_8821C) +#define BIT_SET_TDE_LEN_TH1_8821C(x, v) \ + (BIT_CLEAR_TDE_LEN_TH1_8821C(x) | BIT_TDE_LEN_TH1_8821C(v)) + +#define BIT_SHIFT_TDE_LEN_TH0_8821C 0 +#define BIT_MASK_TDE_LEN_TH0_8821C 0xffff +#define BIT_TDE_LEN_TH0_8821C(x) \ + (((x) & BIT_MASK_TDE_LEN_TH0_8821C) << BIT_SHIFT_TDE_LEN_TH0_8821C) +#define BITS_TDE_LEN_TH0_8821C \ + (BIT_MASK_TDE_LEN_TH0_8821C << BIT_SHIFT_TDE_LEN_TH0_8821C) +#define BIT_CLEAR_TDE_LEN_TH0_8821C(x) ((x) & (~BITS_TDE_LEN_TH0_8821C)) +#define BIT_GET_TDE_LEN_TH0_8821C(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH0_8821C) & BIT_MASK_TDE_LEN_TH0_8821C) +#define BIT_SET_TDE_LEN_TH0_8821C(x, v) \ + (BIT_CLEAR_TDE_LEN_TH0_8821C(x) | BIT_TDE_LEN_TH0_8821C(v)) + +/* 2 REG_RXDMA_LEN_THRESHOLD_8821C */ + +#define BIT_SHIFT_RDE_LEN_TH1_8821C 16 +#define BIT_MASK_RDE_LEN_TH1_8821C 0xffff +#define BIT_RDE_LEN_TH1_8821C(x) \ + (((x) & BIT_MASK_RDE_LEN_TH1_8821C) << BIT_SHIFT_RDE_LEN_TH1_8821C) +#define BITS_RDE_LEN_TH1_8821C \ + (BIT_MASK_RDE_LEN_TH1_8821C << BIT_SHIFT_RDE_LEN_TH1_8821C) +#define BIT_CLEAR_RDE_LEN_TH1_8821C(x) ((x) & (~BITS_RDE_LEN_TH1_8821C)) +#define BIT_GET_RDE_LEN_TH1_8821C(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH1_8821C) & BIT_MASK_RDE_LEN_TH1_8821C) +#define BIT_SET_RDE_LEN_TH1_8821C(x, v) \ + (BIT_CLEAR_RDE_LEN_TH1_8821C(x) | BIT_RDE_LEN_TH1_8821C(v)) + +#define BIT_SHIFT_RDE_LEN_TH0_8821C 0 +#define BIT_MASK_RDE_LEN_TH0_8821C 0xffff +#define BIT_RDE_LEN_TH0_8821C(x) \ + (((x) & BIT_MASK_RDE_LEN_TH0_8821C) << BIT_SHIFT_RDE_LEN_TH0_8821C) +#define BITS_RDE_LEN_TH0_8821C \ + (BIT_MASK_RDE_LEN_TH0_8821C << BIT_SHIFT_RDE_LEN_TH0_8821C) +#define BIT_CLEAR_RDE_LEN_TH0_8821C(x) ((x) & (~BITS_RDE_LEN_TH0_8821C)) +#define BIT_GET_RDE_LEN_TH0_8821C(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH0_8821C) & BIT_MASK_RDE_LEN_TH0_8821C) +#define BIT_SET_RDE_LEN_TH0_8821C(x, v) \ + (BIT_CLEAR_RDE_LEN_TH0_8821C(x) | BIT_RDE_LEN_TH0_8821C(v)) + +/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8821C */ + +#define BIT_SHIFT_COUNT_INT_SEL_8821C 16 +#define BIT_MASK_COUNT_INT_SEL_8821C 0x3 +#define BIT_COUNT_INT_SEL_8821C(x) \ + (((x) & BIT_MASK_COUNT_INT_SEL_8821C) << BIT_SHIFT_COUNT_INT_SEL_8821C) +#define BITS_COUNT_INT_SEL_8821C \ + (BIT_MASK_COUNT_INT_SEL_8821C << BIT_SHIFT_COUNT_INT_SEL_8821C) +#define BIT_CLEAR_COUNT_INT_SEL_8821C(x) ((x) & (~BITS_COUNT_INT_SEL_8821C)) +#define BIT_GET_COUNT_INT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_COUNT_INT_SEL_8821C) & BIT_MASK_COUNT_INT_SEL_8821C) +#define BIT_SET_COUNT_INT_SEL_8821C(x, v) \ + (BIT_CLEAR_COUNT_INT_SEL_8821C(x) | BIT_COUNT_INT_SEL_8821C(v)) + +#define BIT_SHIFT_EXEC_TIME_TH_8821C 0 +#define BIT_MASK_EXEC_TIME_TH_8821C 0xffff +#define BIT_EXEC_TIME_TH_8821C(x) \ + (((x) & BIT_MASK_EXEC_TIME_TH_8821C) << BIT_SHIFT_EXEC_TIME_TH_8821C) +#define BITS_EXEC_TIME_TH_8821C \ + (BIT_MASK_EXEC_TIME_TH_8821C << BIT_SHIFT_EXEC_TIME_TH_8821C) +#define BIT_CLEAR_EXEC_TIME_TH_8821C(x) ((x) & (~BITS_EXEC_TIME_TH_8821C)) +#define BIT_GET_EXEC_TIME_TH_8821C(x) \ + (((x) >> BIT_SHIFT_EXEC_TIME_TH_8821C) & BIT_MASK_EXEC_TIME_TH_8821C) +#define BIT_SET_EXEC_TIME_TH_8821C(x, v) \ + (BIT_CLEAR_EXEC_TIME_TH_8821C(x) | BIT_EXEC_TIME_TH_8821C(v)) /* 2 REG_FT2IMR_8821C */ #define BIT_FS_CLI3_RX_UAPSDMD1_EN_8821C BIT(31) @@ -3488,106 +5474,433 @@ #define BIT_SHIFT_FW_MSG2_8821C 0 #define BIT_MASK_FW_MSG2_8821C 0xffffffffL -#define BIT_FW_MSG2_8821C(x) (((x) & BIT_MASK_FW_MSG2_8821C) << BIT_SHIFT_FW_MSG2_8821C) -#define BIT_GET_FW_MSG2_8821C(x) (((x) >> BIT_SHIFT_FW_MSG2_8821C) & BIT_MASK_FW_MSG2_8821C) - - +#define BIT_FW_MSG2_8821C(x) \ + (((x) & BIT_MASK_FW_MSG2_8821C) << BIT_SHIFT_FW_MSG2_8821C) +#define BITS_FW_MSG2_8821C (BIT_MASK_FW_MSG2_8821C << BIT_SHIFT_FW_MSG2_8821C) +#define BIT_CLEAR_FW_MSG2_8821C(x) ((x) & (~BITS_FW_MSG2_8821C)) +#define BIT_GET_FW_MSG2_8821C(x) \ + (((x) >> BIT_SHIFT_FW_MSG2_8821C) & BIT_MASK_FW_MSG2_8821C) +#define BIT_SET_FW_MSG2_8821C(x, v) \ + (BIT_CLEAR_FW_MSG2_8821C(x) | BIT_FW_MSG2_8821C(v)) /* 2 REG_MSG3_8821C */ #define BIT_SHIFT_FW_MSG3_8821C 0 #define BIT_MASK_FW_MSG3_8821C 0xffffffffL -#define BIT_FW_MSG3_8821C(x) (((x) & BIT_MASK_FW_MSG3_8821C) << BIT_SHIFT_FW_MSG3_8821C) -#define BIT_GET_FW_MSG3_8821C(x) (((x) >> BIT_SHIFT_FW_MSG3_8821C) & BIT_MASK_FW_MSG3_8821C) - - +#define BIT_FW_MSG3_8821C(x) \ + (((x) & BIT_MASK_FW_MSG3_8821C) << BIT_SHIFT_FW_MSG3_8821C) +#define BITS_FW_MSG3_8821C (BIT_MASK_FW_MSG3_8821C << BIT_SHIFT_FW_MSG3_8821C) +#define BIT_CLEAR_FW_MSG3_8821C(x) ((x) & (~BITS_FW_MSG3_8821C)) +#define BIT_GET_FW_MSG3_8821C(x) \ + (((x) >> BIT_SHIFT_FW_MSG3_8821C) & BIT_MASK_FW_MSG3_8821C) +#define BIT_SET_FW_MSG3_8821C(x, v) \ + (BIT_CLEAR_FW_MSG3_8821C(x) | BIT_FW_MSG3_8821C(v)) /* 2 REG_MSG4_8821C */ #define BIT_SHIFT_FW_MSG4_8821C 0 #define BIT_MASK_FW_MSG4_8821C 0xffffffffL -#define BIT_FW_MSG4_8821C(x) (((x) & BIT_MASK_FW_MSG4_8821C) << BIT_SHIFT_FW_MSG4_8821C) -#define BIT_GET_FW_MSG4_8821C(x) (((x) >> BIT_SHIFT_FW_MSG4_8821C) & BIT_MASK_FW_MSG4_8821C) - - +#define BIT_FW_MSG4_8821C(x) \ + (((x) & BIT_MASK_FW_MSG4_8821C) << BIT_SHIFT_FW_MSG4_8821C) +#define BITS_FW_MSG4_8821C (BIT_MASK_FW_MSG4_8821C << BIT_SHIFT_FW_MSG4_8821C) +#define BIT_CLEAR_FW_MSG4_8821C(x) ((x) & (~BITS_FW_MSG4_8821C)) +#define BIT_GET_FW_MSG4_8821C(x) \ + (((x) >> BIT_SHIFT_FW_MSG4_8821C) & BIT_MASK_FW_MSG4_8821C) +#define BIT_SET_FW_MSG4_8821C(x, v) \ + (BIT_CLEAR_FW_MSG4_8821C(x) | BIT_FW_MSG4_8821C(v)) /* 2 REG_MSG5_8821C */ #define BIT_SHIFT_FW_MSG5_8821C 0 #define BIT_MASK_FW_MSG5_8821C 0xffffffffL -#define BIT_FW_MSG5_8821C(x) (((x) & BIT_MASK_FW_MSG5_8821C) << BIT_SHIFT_FW_MSG5_8821C) -#define BIT_GET_FW_MSG5_8821C(x) (((x) >> BIT_SHIFT_FW_MSG5_8821C) & BIT_MASK_FW_MSG5_8821C) +#define BIT_FW_MSG5_8821C(x) \ + (((x) & BIT_MASK_FW_MSG5_8821C) << BIT_SHIFT_FW_MSG5_8821C) +#define BITS_FW_MSG5_8821C (BIT_MASK_FW_MSG5_8821C << BIT_SHIFT_FW_MSG5_8821C) +#define BIT_CLEAR_FW_MSG5_8821C(x) ((x) & (~BITS_FW_MSG5_8821C)) +#define BIT_GET_FW_MSG5_8821C(x) \ + (((x) >> BIT_SHIFT_FW_MSG5_8821C) & BIT_MASK_FW_MSG5_8821C) +#define BIT_SET_FW_MSG5_8821C(x, v) \ + (BIT_CLEAR_FW_MSG5_8821C(x) | BIT_FW_MSG5_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FIFOPAGE_CTRL_1_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C 16 -#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C 0xff -#define BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) -#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8821C(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C 0 -#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C 0xff -#define BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) -#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8821C(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_FIFOPAGE_CTRL_2_8821C */ -#define BIT_BCN_VALID_1_V1_8821C BIT(31) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_BCN_HEAD_1_V1_8821C 16 -#define BIT_MASK_BCN_HEAD_1_V1_8821C 0xfff -#define BIT_BCN_HEAD_1_V1_8821C(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8821C) << BIT_SHIFT_BCN_HEAD_1_V1_8821C) -#define BIT_GET_BCN_HEAD_1_V1_8821C(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8821C) & BIT_MASK_BCN_HEAD_1_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_BCN_VALID_V1_8821C BIT(15) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_BCN_HEAD_V1_8821C 0 -#define BIT_MASK_BCN_HEAD_V1_8821C 0xfff -#define BIT_BCN_HEAD_V1_8821C(x) (((x) & BIT_MASK_BCN_HEAD_V1_8821C) << BIT_SHIFT_BCN_HEAD_V1_8821C) -#define BIT_GET_BCN_HEAD_V1_8821C(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8821C) & BIT_MASK_BCN_HEAD_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -/* 2 REG_AUTO_LLT_V1_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 24 -#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_LLT_FREE_PAGE_V1_8821C 8 -#define BIT_MASK_LLT_FREE_PAGE_V1_8821C 0xffff -#define BIT_LLT_FREE_PAGE_V1_8821C(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) -#define BIT_GET_LLT_FREE_PAGE_V1_8821C(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_BLK_DESC_NUM_8821C 4 -#define BIT_MASK_BLK_DESC_NUM_8821C 0xf -#define BIT_BLK_DESC_NUM_8821C(x) (((x) & BIT_MASK_BLK_DESC_NUM_8821C) << BIT_SHIFT_BLK_DESC_NUM_8821C) -#define BIT_GET_BLK_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8821C) & BIT_MASK_BLK_DESC_NUM_8821C) +/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_R_BCN_HEAD_SEL_8821C BIT(3) -#define BIT_R_EN_BCN_SW_HEAD_SEL_8821C BIT(2) +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_FIFOPAGE_CTRL_1_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C 16 +#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C 0xff +#define BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) +#define BITS_TX_OQT_HE_FREE_SPACE_V1_8821C \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8821C(x) \ + ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8821C)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) +#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8821C(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8821C(x) | \ + BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(v)) + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C 0 +#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C 0xff +#define BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) +#define BITS_TX_OQT_NL_FREE_SPACE_V1_8821C \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8821C(x) \ + ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8821C)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) +#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8821C(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8821C(x) | \ + BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(v)) + +/* 2 REG_FIFOPAGE_CTRL_2_8821C */ +#define BIT_BCN_VALID_1_V1_8821C BIT(31) + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_BCN_HEAD_1_V1_8821C 16 +#define BIT_MASK_BCN_HEAD_1_V1_8821C 0xfff +#define BIT_BCN_HEAD_1_V1_8821C(x) \ + (((x) & BIT_MASK_BCN_HEAD_1_V1_8821C) << BIT_SHIFT_BCN_HEAD_1_V1_8821C) +#define BITS_BCN_HEAD_1_V1_8821C \ + (BIT_MASK_BCN_HEAD_1_V1_8821C << BIT_SHIFT_BCN_HEAD_1_V1_8821C) +#define BIT_CLEAR_BCN_HEAD_1_V1_8821C(x) ((x) & (~BITS_BCN_HEAD_1_V1_8821C)) +#define BIT_GET_BCN_HEAD_1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8821C) & BIT_MASK_BCN_HEAD_1_V1_8821C) +#define BIT_SET_BCN_HEAD_1_V1_8821C(x, v) \ + (BIT_CLEAR_BCN_HEAD_1_V1_8821C(x) | BIT_BCN_HEAD_1_V1_8821C(v)) + +#define BIT_BCN_VALID_V1_8821C BIT(15) + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_BCN_HEAD_V1_8821C 0 +#define BIT_MASK_BCN_HEAD_V1_8821C 0xfff +#define BIT_BCN_HEAD_V1_8821C(x) \ + (((x) & BIT_MASK_BCN_HEAD_V1_8821C) << BIT_SHIFT_BCN_HEAD_V1_8821C) +#define BITS_BCN_HEAD_V1_8821C \ + (BIT_MASK_BCN_HEAD_V1_8821C << BIT_SHIFT_BCN_HEAD_V1_8821C) +#define BIT_CLEAR_BCN_HEAD_V1_8821C(x) ((x) & (~BITS_BCN_HEAD_V1_8821C)) +#define BIT_GET_BCN_HEAD_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_V1_8821C) & BIT_MASK_BCN_HEAD_V1_8821C) +#define BIT_SET_BCN_HEAD_V1_8821C(x, v) \ + (BIT_CLEAR_BCN_HEAD_V1_8821C(x) | BIT_BCN_HEAD_V1_8821C(v)) + +/* 2 REG_AUTO_LLT_V1_8821C */ + +#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 24 +#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 0xff +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) +#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C \ + (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) +#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) \ + ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) & \ + BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) +#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) | \ + BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(v)) + +#define BIT_SHIFT_LLT_FREE_PAGE_V1_8821C 8 +#define BIT_MASK_LLT_FREE_PAGE_V1_8821C 0xffff +#define BIT_LLT_FREE_PAGE_V1_8821C(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) \ + << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) +#define BITS_LLT_FREE_PAGE_V1_8821C \ + (BIT_MASK_LLT_FREE_PAGE_V1_8821C << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) +#define BIT_CLEAR_LLT_FREE_PAGE_V1_8821C(x) \ + ((x) & (~BITS_LLT_FREE_PAGE_V1_8821C)) +#define BIT_GET_LLT_FREE_PAGE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) & \ + BIT_MASK_LLT_FREE_PAGE_V1_8821C) +#define BIT_SET_LLT_FREE_PAGE_V1_8821C(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V1_8821C(x) | BIT_LLT_FREE_PAGE_V1_8821C(v)) + +#define BIT_SHIFT_BLK_DESC_NUM_8821C 4 +#define BIT_MASK_BLK_DESC_NUM_8821C 0xf +#define BIT_BLK_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM_8821C) << BIT_SHIFT_BLK_DESC_NUM_8821C) +#define BITS_BLK_DESC_NUM_8821C \ + (BIT_MASK_BLK_DESC_NUM_8821C << BIT_SHIFT_BLK_DESC_NUM_8821C) +#define BIT_CLEAR_BLK_DESC_NUM_8821C(x) ((x) & (~BITS_BLK_DESC_NUM_8821C)) +#define BIT_GET_BLK_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM_8821C) & BIT_MASK_BLK_DESC_NUM_8821C) +#define BIT_SET_BLK_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM_8821C(x) | BIT_BLK_DESC_NUM_8821C(v)) + +#define BIT_R_BCN_HEAD_SEL_8821C BIT(3) +#define BIT_R_EN_BCN_SW_HEAD_SEL_8821C BIT(2) #define BIT_LLT_DBG_SEL_8821C BIT(1) #define BIT_AUTO_INIT_LLT_V1_8821C BIT(0) @@ -3599,10 +5912,17 @@ #define BIT_SHIFT_PG_UNDER_TH_V1_8821C 16 #define BIT_MASK_PG_UNDER_TH_V1_8821C 0xfff -#define BIT_PG_UNDER_TH_V1_8821C(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8821C) << BIT_SHIFT_PG_UNDER_TH_V1_8821C) -#define BIT_GET_PG_UNDER_TH_V1_8821C(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8821C) & BIT_MASK_PG_UNDER_TH_V1_8821C) - - +#define BIT_PG_UNDER_TH_V1_8821C(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1_8821C) \ + << BIT_SHIFT_PG_UNDER_TH_V1_8821C) +#define BITS_PG_UNDER_TH_V1_8821C \ + (BIT_MASK_PG_UNDER_TH_V1_8821C << BIT_SHIFT_PG_UNDER_TH_V1_8821C) +#define BIT_CLEAR_PG_UNDER_TH_V1_8821C(x) ((x) & (~BITS_PG_UNDER_TH_V1_8821C)) +#define BIT_GET_PG_UNDER_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8821C) & \ + BIT_MASK_PG_UNDER_TH_V1_8821C) +#define BIT_SET_PG_UNDER_TH_V1_8821C(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1_8821C(x) | BIT_PG_UNDER_TH_V1_8821C(v)) /* 2 REG_NOT_VALID_8821C */ #define BIT_SDIO_TXDESC_CHKSUM_EN_8821C BIT(13) @@ -3614,10 +5934,15 @@ #define BIT_SHIFT_CHECK_OFFSET_8821C 0 #define BIT_MASK_CHECK_OFFSET_8821C 0xff -#define BIT_CHECK_OFFSET_8821C(x) (((x) & BIT_MASK_CHECK_OFFSET_8821C) << BIT_SHIFT_CHECK_OFFSET_8821C) -#define BIT_GET_CHECK_OFFSET_8821C(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8821C) & BIT_MASK_CHECK_OFFSET_8821C) - - +#define BIT_CHECK_OFFSET_8821C(x) \ + (((x) & BIT_MASK_CHECK_OFFSET_8821C) << BIT_SHIFT_CHECK_OFFSET_8821C) +#define BITS_CHECK_OFFSET_8821C \ + (BIT_MASK_CHECK_OFFSET_8821C << BIT_SHIFT_CHECK_OFFSET_8821C) +#define BIT_CLEAR_CHECK_OFFSET_8821C(x) ((x) & (~BITS_CHECK_OFFSET_8821C)) +#define BIT_GET_CHECK_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET_8821C) & BIT_MASK_CHECK_OFFSET_8821C) +#define BIT_SET_CHECK_OFFSET_8821C(x, v) \ + (BIT_CLEAR_CHECK_OFFSET_8821C(x) | BIT_CHECK_OFFSET_8821C(v)) /* 2 REG_TXDMA_STATUS_8821C */ #define BIT_TXPKTBUF_REQ_ERR_8821C BIT(18) @@ -3643,84 +5968,146 @@ /* 2 REG_TX_DMA_DBG_8821C */ /* 2 REG_TQPNT1_8821C */ +#define BIT_HPQ_INT_EN_8821C BIT(31) #define BIT_SHIFT_HPQ_HIGH_TH_V1_8821C 16 #define BIT_MASK_HPQ_HIGH_TH_V1_8821C 0xfff -#define BIT_HPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) -#define BIT_GET_HPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) & BIT_MASK_HPQ_HIGH_TH_V1_8821C) - - +#define BIT_HPQ_HIGH_TH_V1_8821C(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8821C) \ + << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) +#define BITS_HPQ_HIGH_TH_V1_8821C \ + (BIT_MASK_HPQ_HIGH_TH_V1_8821C << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) +#define BIT_CLEAR_HPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8821C)) +#define BIT_GET_HPQ_HIGH_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) & \ + BIT_MASK_HPQ_HIGH_TH_V1_8821C) +#define BIT_SET_HPQ_HIGH_TH_V1_8821C(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH_V1_8821C(x) | BIT_HPQ_HIGH_TH_V1_8821C(v)) #define BIT_SHIFT_HPQ_LOW_TH_V1_8821C 0 #define BIT_MASK_HPQ_LOW_TH_V1_8821C 0xfff -#define BIT_HPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8821C) << BIT_SHIFT_HPQ_LOW_TH_V1_8821C) -#define BIT_GET_HPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8821C) & BIT_MASK_HPQ_LOW_TH_V1_8821C) - - +#define BIT_HPQ_LOW_TH_V1_8821C(x) \ + (((x) & BIT_MASK_HPQ_LOW_TH_V1_8821C) << BIT_SHIFT_HPQ_LOW_TH_V1_8821C) +#define BITS_HPQ_LOW_TH_V1_8821C \ + (BIT_MASK_HPQ_LOW_TH_V1_8821C << BIT_SHIFT_HPQ_LOW_TH_V1_8821C) +#define BIT_CLEAR_HPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8821C)) +#define BIT_GET_HPQ_LOW_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8821C) & BIT_MASK_HPQ_LOW_TH_V1_8821C) +#define BIT_SET_HPQ_LOW_TH_V1_8821C(x, v) \ + (BIT_CLEAR_HPQ_LOW_TH_V1_8821C(x) | BIT_HPQ_LOW_TH_V1_8821C(v)) /* 2 REG_TQPNT2_8821C */ +#define BIT_NPQ_INT_EN_8821C BIT(31) #define BIT_SHIFT_NPQ_HIGH_TH_V1_8821C 16 #define BIT_MASK_NPQ_HIGH_TH_V1_8821C 0xfff -#define BIT_NPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) -#define BIT_GET_NPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) & BIT_MASK_NPQ_HIGH_TH_V1_8821C) - - +#define BIT_NPQ_HIGH_TH_V1_8821C(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8821C) \ + << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) +#define BITS_NPQ_HIGH_TH_V1_8821C \ + (BIT_MASK_NPQ_HIGH_TH_V1_8821C << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) +#define BIT_CLEAR_NPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8821C)) +#define BIT_GET_NPQ_HIGH_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) & \ + BIT_MASK_NPQ_HIGH_TH_V1_8821C) +#define BIT_SET_NPQ_HIGH_TH_V1_8821C(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH_V1_8821C(x) | BIT_NPQ_HIGH_TH_V1_8821C(v)) #define BIT_SHIFT_NPQ_LOW_TH_V1_8821C 0 #define BIT_MASK_NPQ_LOW_TH_V1_8821C 0xfff -#define BIT_NPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8821C) << BIT_SHIFT_NPQ_LOW_TH_V1_8821C) -#define BIT_GET_NPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8821C) & BIT_MASK_NPQ_LOW_TH_V1_8821C) - - +#define BIT_NPQ_LOW_TH_V1_8821C(x) \ + (((x) & BIT_MASK_NPQ_LOW_TH_V1_8821C) << BIT_SHIFT_NPQ_LOW_TH_V1_8821C) +#define BITS_NPQ_LOW_TH_V1_8821C \ + (BIT_MASK_NPQ_LOW_TH_V1_8821C << BIT_SHIFT_NPQ_LOW_TH_V1_8821C) +#define BIT_CLEAR_NPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8821C)) +#define BIT_GET_NPQ_LOW_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8821C) & BIT_MASK_NPQ_LOW_TH_V1_8821C) +#define BIT_SET_NPQ_LOW_TH_V1_8821C(x, v) \ + (BIT_CLEAR_NPQ_LOW_TH_V1_8821C(x) | BIT_NPQ_LOW_TH_V1_8821C(v)) /* 2 REG_TQPNT3_8821C */ +#define BIT_LPQ_INT_EN_8821C BIT(31) #define BIT_SHIFT_LPQ_HIGH_TH_V1_8821C 16 #define BIT_MASK_LPQ_HIGH_TH_V1_8821C 0xfff -#define BIT_LPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) -#define BIT_GET_LPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) & BIT_MASK_LPQ_HIGH_TH_V1_8821C) - - +#define BIT_LPQ_HIGH_TH_V1_8821C(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8821C) \ + << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) +#define BITS_LPQ_HIGH_TH_V1_8821C \ + (BIT_MASK_LPQ_HIGH_TH_V1_8821C << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) +#define BIT_CLEAR_LPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8821C)) +#define BIT_GET_LPQ_HIGH_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) & \ + BIT_MASK_LPQ_HIGH_TH_V1_8821C) +#define BIT_SET_LPQ_HIGH_TH_V1_8821C(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH_V1_8821C(x) | BIT_LPQ_HIGH_TH_V1_8821C(v)) #define BIT_SHIFT_LPQ_LOW_TH_V1_8821C 0 #define BIT_MASK_LPQ_LOW_TH_V1_8821C 0xfff -#define BIT_LPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8821C) << BIT_SHIFT_LPQ_LOW_TH_V1_8821C) -#define BIT_GET_LPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8821C) & BIT_MASK_LPQ_LOW_TH_V1_8821C) - - +#define BIT_LPQ_LOW_TH_V1_8821C(x) \ + (((x) & BIT_MASK_LPQ_LOW_TH_V1_8821C) << BIT_SHIFT_LPQ_LOW_TH_V1_8821C) +#define BITS_LPQ_LOW_TH_V1_8821C \ + (BIT_MASK_LPQ_LOW_TH_V1_8821C << BIT_SHIFT_LPQ_LOW_TH_V1_8821C) +#define BIT_CLEAR_LPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8821C)) +#define BIT_GET_LPQ_LOW_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8821C) & BIT_MASK_LPQ_LOW_TH_V1_8821C) +#define BIT_SET_LPQ_LOW_TH_V1_8821C(x, v) \ + (BIT_CLEAR_LPQ_LOW_TH_V1_8821C(x) | BIT_LPQ_LOW_TH_V1_8821C(v)) /* 2 REG_TQPNT4_8821C */ +#define BIT_EXQ_INT_EN_8821C BIT(31) #define BIT_SHIFT_EXQ_HIGH_TH_V1_8821C 16 #define BIT_MASK_EXQ_HIGH_TH_V1_8821C 0xfff -#define BIT_EXQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8821C) << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) -#define BIT_GET_EXQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) & BIT_MASK_EXQ_HIGH_TH_V1_8821C) - - +#define BIT_EXQ_HIGH_TH_V1_8821C(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8821C) \ + << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) +#define BITS_EXQ_HIGH_TH_V1_8821C \ + (BIT_MASK_EXQ_HIGH_TH_V1_8821C << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) +#define BIT_CLEAR_EXQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8821C)) +#define BIT_GET_EXQ_HIGH_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) & \ + BIT_MASK_EXQ_HIGH_TH_V1_8821C) +#define BIT_SET_EXQ_HIGH_TH_V1_8821C(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH_V1_8821C(x) | BIT_EXQ_HIGH_TH_V1_8821C(v)) #define BIT_SHIFT_EXQ_LOW_TH_V1_8821C 0 #define BIT_MASK_EXQ_LOW_TH_V1_8821C 0xfff -#define BIT_EXQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8821C) << BIT_SHIFT_EXQ_LOW_TH_V1_8821C) -#define BIT_GET_EXQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8821C) & BIT_MASK_EXQ_LOW_TH_V1_8821C) - - +#define BIT_EXQ_LOW_TH_V1_8821C(x) \ + (((x) & BIT_MASK_EXQ_LOW_TH_V1_8821C) << BIT_SHIFT_EXQ_LOW_TH_V1_8821C) +#define BITS_EXQ_LOW_TH_V1_8821C \ + (BIT_MASK_EXQ_LOW_TH_V1_8821C << BIT_SHIFT_EXQ_LOW_TH_V1_8821C) +#define BIT_CLEAR_EXQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8821C)) +#define BIT_GET_EXQ_LOW_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8821C) & BIT_MASK_EXQ_LOW_TH_V1_8821C) +#define BIT_SET_EXQ_LOW_TH_V1_8821C(x, v) \ + (BIT_CLEAR_EXQ_LOW_TH_V1_8821C(x) | BIT_EXQ_LOW_TH_V1_8821C(v)) /* 2 REG_RQPN_CTRL_1_8821C */ #define BIT_SHIFT_TXPKTNUM_H_8821C 16 #define BIT_MASK_TXPKTNUM_H_8821C 0xffff -#define BIT_TXPKTNUM_H_8821C(x) (((x) & BIT_MASK_TXPKTNUM_H_8821C) << BIT_SHIFT_TXPKTNUM_H_8821C) -#define BIT_GET_TXPKTNUM_H_8821C(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8821C) & BIT_MASK_TXPKTNUM_H_8821C) - - +#define BIT_TXPKTNUM_H_8821C(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_8821C) << BIT_SHIFT_TXPKTNUM_H_8821C) +#define BITS_TXPKTNUM_H_8821C \ + (BIT_MASK_TXPKTNUM_H_8821C << BIT_SHIFT_TXPKTNUM_H_8821C) +#define BIT_CLEAR_TXPKTNUM_H_8821C(x) ((x) & (~BITS_TXPKTNUM_H_8821C)) +#define BIT_GET_TXPKTNUM_H_8821C(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_8821C) & BIT_MASK_TXPKTNUM_H_8821C) +#define BIT_SET_TXPKTNUM_H_8821C(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_8821C(x) | BIT_TXPKTNUM_H_8821C(v)) #define BIT_SHIFT_TXPKTNUM_V2_8821C 0 #define BIT_MASK_TXPKTNUM_V2_8821C 0xffff -#define BIT_TXPKTNUM_V2_8821C(x) (((x) & BIT_MASK_TXPKTNUM_V2_8821C) << BIT_SHIFT_TXPKTNUM_V2_8821C) -#define BIT_GET_TXPKTNUM_V2_8821C(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8821C) & BIT_MASK_TXPKTNUM_V2_8821C) - - +#define BIT_TXPKTNUM_V2_8821C(x) \ + (((x) & BIT_MASK_TXPKTNUM_V2_8821C) << BIT_SHIFT_TXPKTNUM_V2_8821C) +#define BITS_TXPKTNUM_V2_8821C \ + (BIT_MASK_TXPKTNUM_V2_8821C << BIT_SHIFT_TXPKTNUM_V2_8821C) +#define BIT_CLEAR_TXPKTNUM_V2_8821C(x) ((x) & (~BITS_TXPKTNUM_V2_8821C)) +#define BIT_GET_TXPKTNUM_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V2_8821C) & BIT_MASK_TXPKTNUM_V2_8821C) +#define BIT_SET_TXPKTNUM_V2_8821C(x, v) \ + (BIT_CLEAR_TXPKTNUM_V2_8821C(x) | BIT_TXPKTNUM_V2_8821C(v)) /* 2 REG_RQPN_CTRL_2_8821C */ #define BIT_LD_RQPN_8821C BIT(31) @@ -3732,126 +6119,211 @@ #define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C 0 #define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C 0xfff -#define BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(x) (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) -#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8821C(x) (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) - - +#define BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(x) \ + (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) +#define BITS_SDIO_TXAGG_ALIGN_SIZE_8821C \ + (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) +#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8821C(x) \ + ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_8821C)) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) & \ + BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) +#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_8821C(x, v) \ + (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8821C(x) | \ + BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(v)) /* 2 REG_FIFOPAGE_INFO_1_8821C */ #define BIT_SHIFT_HPQ_AVAL_PG_V1_8821C 16 #define BIT_MASK_HPQ_AVAL_PG_V1_8821C 0xfff -#define BIT_HPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) -#define BIT_GET_HPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) & BIT_MASK_HPQ_AVAL_PG_V1_8821C) - - +#define BIT_HPQ_AVAL_PG_V1_8821C(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8821C) \ + << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) +#define BITS_HPQ_AVAL_PG_V1_8821C \ + (BIT_MASK_HPQ_AVAL_PG_V1_8821C << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) +#define BIT_CLEAR_HPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8821C)) +#define BIT_GET_HPQ_AVAL_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) & \ + BIT_MASK_HPQ_AVAL_PG_V1_8821C) +#define BIT_SET_HPQ_AVAL_PG_V1_8821C(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG_V1_8821C(x) | BIT_HPQ_AVAL_PG_V1_8821C(v)) #define BIT_SHIFT_HPQ_V1_8821C 0 #define BIT_MASK_HPQ_V1_8821C 0xfff -#define BIT_HPQ_V1_8821C(x) (((x) & BIT_MASK_HPQ_V1_8821C) << BIT_SHIFT_HPQ_V1_8821C) -#define BIT_GET_HPQ_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_V1_8821C) & BIT_MASK_HPQ_V1_8821C) - - +#define BIT_HPQ_V1_8821C(x) \ + (((x) & BIT_MASK_HPQ_V1_8821C) << BIT_SHIFT_HPQ_V1_8821C) +#define BITS_HPQ_V1_8821C (BIT_MASK_HPQ_V1_8821C << BIT_SHIFT_HPQ_V1_8821C) +#define BIT_CLEAR_HPQ_V1_8821C(x) ((x) & (~BITS_HPQ_V1_8821C)) +#define BIT_GET_HPQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HPQ_V1_8821C) & BIT_MASK_HPQ_V1_8821C) +#define BIT_SET_HPQ_V1_8821C(x, v) \ + (BIT_CLEAR_HPQ_V1_8821C(x) | BIT_HPQ_V1_8821C(v)) /* 2 REG_FIFOPAGE_INFO_2_8821C */ #define BIT_SHIFT_LPQ_AVAL_PG_V1_8821C 16 #define BIT_MASK_LPQ_AVAL_PG_V1_8821C 0xfff -#define BIT_LPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) -#define BIT_GET_LPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) & BIT_MASK_LPQ_AVAL_PG_V1_8821C) - - +#define BIT_LPQ_AVAL_PG_V1_8821C(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8821C) \ + << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) +#define BITS_LPQ_AVAL_PG_V1_8821C \ + (BIT_MASK_LPQ_AVAL_PG_V1_8821C << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) +#define BIT_CLEAR_LPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8821C)) +#define BIT_GET_LPQ_AVAL_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) & \ + BIT_MASK_LPQ_AVAL_PG_V1_8821C) +#define BIT_SET_LPQ_AVAL_PG_V1_8821C(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG_V1_8821C(x) | BIT_LPQ_AVAL_PG_V1_8821C(v)) #define BIT_SHIFT_LPQ_V1_8821C 0 #define BIT_MASK_LPQ_V1_8821C 0xfff -#define BIT_LPQ_V1_8821C(x) (((x) & BIT_MASK_LPQ_V1_8821C) << BIT_SHIFT_LPQ_V1_8821C) -#define BIT_GET_LPQ_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_V1_8821C) & BIT_MASK_LPQ_V1_8821C) - - +#define BIT_LPQ_V1_8821C(x) \ + (((x) & BIT_MASK_LPQ_V1_8821C) << BIT_SHIFT_LPQ_V1_8821C) +#define BITS_LPQ_V1_8821C (BIT_MASK_LPQ_V1_8821C << BIT_SHIFT_LPQ_V1_8821C) +#define BIT_CLEAR_LPQ_V1_8821C(x) ((x) & (~BITS_LPQ_V1_8821C)) +#define BIT_GET_LPQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LPQ_V1_8821C) & BIT_MASK_LPQ_V1_8821C) +#define BIT_SET_LPQ_V1_8821C(x, v) \ + (BIT_CLEAR_LPQ_V1_8821C(x) | BIT_LPQ_V1_8821C(v)) /* 2 REG_FIFOPAGE_INFO_3_8821C */ #define BIT_SHIFT_NPQ_AVAL_PG_V1_8821C 16 #define BIT_MASK_NPQ_AVAL_PG_V1_8821C 0xfff -#define BIT_NPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) -#define BIT_GET_NPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) & BIT_MASK_NPQ_AVAL_PG_V1_8821C) - - +#define BIT_NPQ_AVAL_PG_V1_8821C(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8821C) \ + << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) +#define BITS_NPQ_AVAL_PG_V1_8821C \ + (BIT_MASK_NPQ_AVAL_PG_V1_8821C << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) +#define BIT_CLEAR_NPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8821C)) +#define BIT_GET_NPQ_AVAL_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) & \ + BIT_MASK_NPQ_AVAL_PG_V1_8821C) +#define BIT_SET_NPQ_AVAL_PG_V1_8821C(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG_V1_8821C(x) | BIT_NPQ_AVAL_PG_V1_8821C(v)) #define BIT_SHIFT_NPQ_V1_8821C 0 #define BIT_MASK_NPQ_V1_8821C 0xfff -#define BIT_NPQ_V1_8821C(x) (((x) & BIT_MASK_NPQ_V1_8821C) << BIT_SHIFT_NPQ_V1_8821C) -#define BIT_GET_NPQ_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_V1_8821C) & BIT_MASK_NPQ_V1_8821C) - - +#define BIT_NPQ_V1_8821C(x) \ + (((x) & BIT_MASK_NPQ_V1_8821C) << BIT_SHIFT_NPQ_V1_8821C) +#define BITS_NPQ_V1_8821C (BIT_MASK_NPQ_V1_8821C << BIT_SHIFT_NPQ_V1_8821C) +#define BIT_CLEAR_NPQ_V1_8821C(x) ((x) & (~BITS_NPQ_V1_8821C)) +#define BIT_GET_NPQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NPQ_V1_8821C) & BIT_MASK_NPQ_V1_8821C) +#define BIT_SET_NPQ_V1_8821C(x, v) \ + (BIT_CLEAR_NPQ_V1_8821C(x) | BIT_NPQ_V1_8821C(v)) /* 2 REG_FIFOPAGE_INFO_4_8821C */ #define BIT_SHIFT_EXQ_AVAL_PG_V1_8821C 16 #define BIT_MASK_EXQ_AVAL_PG_V1_8821C 0xfff -#define BIT_EXQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8821C) << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) -#define BIT_GET_EXQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) & BIT_MASK_EXQ_AVAL_PG_V1_8821C) - - +#define BIT_EXQ_AVAL_PG_V1_8821C(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8821C) \ + << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) +#define BITS_EXQ_AVAL_PG_V1_8821C \ + (BIT_MASK_EXQ_AVAL_PG_V1_8821C << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) +#define BIT_CLEAR_EXQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8821C)) +#define BIT_GET_EXQ_AVAL_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) & \ + BIT_MASK_EXQ_AVAL_PG_V1_8821C) +#define BIT_SET_EXQ_AVAL_PG_V1_8821C(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG_V1_8821C(x) | BIT_EXQ_AVAL_PG_V1_8821C(v)) #define BIT_SHIFT_EXQ_V1_8821C 0 #define BIT_MASK_EXQ_V1_8821C 0xfff -#define BIT_EXQ_V1_8821C(x) (((x) & BIT_MASK_EXQ_V1_8821C) << BIT_SHIFT_EXQ_V1_8821C) -#define BIT_GET_EXQ_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_V1_8821C) & BIT_MASK_EXQ_V1_8821C) - - +#define BIT_EXQ_V1_8821C(x) \ + (((x) & BIT_MASK_EXQ_V1_8821C) << BIT_SHIFT_EXQ_V1_8821C) +#define BITS_EXQ_V1_8821C (BIT_MASK_EXQ_V1_8821C << BIT_SHIFT_EXQ_V1_8821C) +#define BIT_CLEAR_EXQ_V1_8821C(x) ((x) & (~BITS_EXQ_V1_8821C)) +#define BIT_GET_EXQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EXQ_V1_8821C) & BIT_MASK_EXQ_V1_8821C) +#define BIT_SET_EXQ_V1_8821C(x, v) \ + (BIT_CLEAR_EXQ_V1_8821C(x) | BIT_EXQ_V1_8821C(v)) /* 2 REG_FIFOPAGE_INFO_5_8821C */ #define BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C 16 #define BIT_MASK_PUBQ_AVAL_PG_V1_8821C 0xfff -#define BIT_PUBQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) -#define BIT_GET_PUBQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C) - - +#define BIT_PUBQ_AVAL_PG_V1_8821C(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C) \ + << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) +#define BITS_PUBQ_AVAL_PG_V1_8821C \ + (BIT_MASK_PUBQ_AVAL_PG_V1_8821C << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) +#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8821C)) +#define BIT_GET_PUBQ_AVAL_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) & \ + BIT_MASK_PUBQ_AVAL_PG_V1_8821C) +#define BIT_SET_PUBQ_AVAL_PG_V1_8821C(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG_V1_8821C(x) | BIT_PUBQ_AVAL_PG_V1_8821C(v)) #define BIT_SHIFT_PUBQ_V1_8821C 0 #define BIT_MASK_PUBQ_V1_8821C 0xfff -#define BIT_PUBQ_V1_8821C(x) (((x) & BIT_MASK_PUBQ_V1_8821C) << BIT_SHIFT_PUBQ_V1_8821C) -#define BIT_GET_PUBQ_V1_8821C(x) (((x) >> BIT_SHIFT_PUBQ_V1_8821C) & BIT_MASK_PUBQ_V1_8821C) - - +#define BIT_PUBQ_V1_8821C(x) \ + (((x) & BIT_MASK_PUBQ_V1_8821C) << BIT_SHIFT_PUBQ_V1_8821C) +#define BITS_PUBQ_V1_8821C (BIT_MASK_PUBQ_V1_8821C << BIT_SHIFT_PUBQ_V1_8821C) +#define BIT_CLEAR_PUBQ_V1_8821C(x) ((x) & (~BITS_PUBQ_V1_8821C)) +#define BIT_GET_PUBQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PUBQ_V1_8821C) & BIT_MASK_PUBQ_V1_8821C) +#define BIT_SET_PUBQ_V1_8821C(x, v) \ + (BIT_CLEAR_PUBQ_V1_8821C(x) | BIT_PUBQ_V1_8821C(v)) /* 2 REG_H2C_HEAD_8821C */ #define BIT_SHIFT_H2C_HEAD_8821C 0 #define BIT_MASK_H2C_HEAD_8821C 0x3ffff -#define BIT_H2C_HEAD_8821C(x) (((x) & BIT_MASK_H2C_HEAD_8821C) << BIT_SHIFT_H2C_HEAD_8821C) -#define BIT_GET_H2C_HEAD_8821C(x) (((x) >> BIT_SHIFT_H2C_HEAD_8821C) & BIT_MASK_H2C_HEAD_8821C) - - +#define BIT_H2C_HEAD_8821C(x) \ + (((x) & BIT_MASK_H2C_HEAD_8821C) << BIT_SHIFT_H2C_HEAD_8821C) +#define BITS_H2C_HEAD_8821C \ + (BIT_MASK_H2C_HEAD_8821C << BIT_SHIFT_H2C_HEAD_8821C) +#define BIT_CLEAR_H2C_HEAD_8821C(x) ((x) & (~BITS_H2C_HEAD_8821C)) +#define BIT_GET_H2C_HEAD_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_8821C) & BIT_MASK_H2C_HEAD_8821C) +#define BIT_SET_H2C_HEAD_8821C(x, v) \ + (BIT_CLEAR_H2C_HEAD_8821C(x) | BIT_H2C_HEAD_8821C(v)) /* 2 REG_H2C_TAIL_8821C */ #define BIT_SHIFT_H2C_TAIL_8821C 0 #define BIT_MASK_H2C_TAIL_8821C 0x3ffff -#define BIT_H2C_TAIL_8821C(x) (((x) & BIT_MASK_H2C_TAIL_8821C) << BIT_SHIFT_H2C_TAIL_8821C) -#define BIT_GET_H2C_TAIL_8821C(x) (((x) >> BIT_SHIFT_H2C_TAIL_8821C) & BIT_MASK_H2C_TAIL_8821C) - - +#define BIT_H2C_TAIL_8821C(x) \ + (((x) & BIT_MASK_H2C_TAIL_8821C) << BIT_SHIFT_H2C_TAIL_8821C) +#define BITS_H2C_TAIL_8821C \ + (BIT_MASK_H2C_TAIL_8821C << BIT_SHIFT_H2C_TAIL_8821C) +#define BIT_CLEAR_H2C_TAIL_8821C(x) ((x) & (~BITS_H2C_TAIL_8821C)) +#define BIT_GET_H2C_TAIL_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_8821C) & BIT_MASK_H2C_TAIL_8821C) +#define BIT_SET_H2C_TAIL_8821C(x, v) \ + (BIT_CLEAR_H2C_TAIL_8821C(x) | BIT_H2C_TAIL_8821C(v)) /* 2 REG_H2C_READ_ADDR_8821C */ #define BIT_SHIFT_H2C_READ_ADDR_8821C 0 #define BIT_MASK_H2C_READ_ADDR_8821C 0x3ffff -#define BIT_H2C_READ_ADDR_8821C(x) (((x) & BIT_MASK_H2C_READ_ADDR_8821C) << BIT_SHIFT_H2C_READ_ADDR_8821C) -#define BIT_GET_H2C_READ_ADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8821C) & BIT_MASK_H2C_READ_ADDR_8821C) - - +#define BIT_H2C_READ_ADDR_8821C(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_8821C) << BIT_SHIFT_H2C_READ_ADDR_8821C) +#define BITS_H2C_READ_ADDR_8821C \ + (BIT_MASK_H2C_READ_ADDR_8821C << BIT_SHIFT_H2C_READ_ADDR_8821C) +#define BIT_CLEAR_H2C_READ_ADDR_8821C(x) ((x) & (~BITS_H2C_READ_ADDR_8821C)) +#define BIT_GET_H2C_READ_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_8821C) & BIT_MASK_H2C_READ_ADDR_8821C) +#define BIT_SET_H2C_READ_ADDR_8821C(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_8821C(x) | BIT_H2C_READ_ADDR_8821C(v)) /* 2 REG_H2C_WR_ADDR_8821C */ #define BIT_SHIFT_H2C_WR_ADDR_8821C 0 #define BIT_MASK_H2C_WR_ADDR_8821C 0x3ffff -#define BIT_H2C_WR_ADDR_8821C(x) (((x) & BIT_MASK_H2C_WR_ADDR_8821C) << BIT_SHIFT_H2C_WR_ADDR_8821C) -#define BIT_GET_H2C_WR_ADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8821C) & BIT_MASK_H2C_WR_ADDR_8821C) - - +#define BIT_H2C_WR_ADDR_8821C(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_8821C) << BIT_SHIFT_H2C_WR_ADDR_8821C) +#define BITS_H2C_WR_ADDR_8821C \ + (BIT_MASK_H2C_WR_ADDR_8821C << BIT_SHIFT_H2C_WR_ADDR_8821C) +#define BIT_CLEAR_H2C_WR_ADDR_8821C(x) ((x) & (~BITS_H2C_WR_ADDR_8821C)) +#define BIT_GET_H2C_WR_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_8821C) & BIT_MASK_H2C_WR_ADDR_8821C) +#define BIT_SET_H2C_WR_ADDR_8821C(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_8821C(x) | BIT_H2C_WR_ADDR_8821C(v)) /* 2 REG_H2C_INFO_8821C */ #define BIT_H2C_SPACE_VLD_8821C BIT(3) @@ -3859,55 +6331,92 @@ #define BIT_SHIFT_H2C_LEN_SEL_8821C 0 #define BIT_MASK_H2C_LEN_SEL_8821C 0x3 -#define BIT_H2C_LEN_SEL_8821C(x) (((x) & BIT_MASK_H2C_LEN_SEL_8821C) << BIT_SHIFT_H2C_LEN_SEL_8821C) -#define BIT_GET_H2C_LEN_SEL_8821C(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8821C) & BIT_MASK_H2C_LEN_SEL_8821C) - - +#define BIT_H2C_LEN_SEL_8821C(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL_8821C) << BIT_SHIFT_H2C_LEN_SEL_8821C) +#define BITS_H2C_LEN_SEL_8821C \ + (BIT_MASK_H2C_LEN_SEL_8821C << BIT_SHIFT_H2C_LEN_SEL_8821C) +#define BIT_CLEAR_H2C_LEN_SEL_8821C(x) ((x) & (~BITS_H2C_LEN_SEL_8821C)) +#define BIT_GET_H2C_LEN_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL_8821C) & BIT_MASK_H2C_LEN_SEL_8821C) +#define BIT_SET_H2C_LEN_SEL_8821C(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL_8821C(x) | BIT_H2C_LEN_SEL_8821C(v)) /* 2 REG_RXDMA_AGG_PG_TH_8821C */ +#define BIT_USB_RXDMA_AGG_EN_8821C BIT(31) +#define BIT_EN_PRE_CALC_8821C BIT(29) +#define BIT_RXAGG_SW_EN_8821C BIT(28) +#define BIT_RXAGG_SW_TRIG_8821C BIT(27) -#define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C 24 -#define BIT_MASK_RXDMA_AGG_OLD_MOD_8821C 0xff -#define BIT_RXDMA_AGG_OLD_MOD_8821C(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD_8821C) << BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C) -#define BIT_GET_RXDMA_AGG_OLD_MOD_8821C(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C) & BIT_MASK_RXDMA_AGG_OLD_MOD_8821C) - - +/* 2 REG_NOT_VALID_8821C */ #define BIT_SHIFT_PKT_NUM_WOL_8821C 16 #define BIT_MASK_PKT_NUM_WOL_8821C 0xff -#define BIT_PKT_NUM_WOL_8821C(x) (((x) & BIT_MASK_PKT_NUM_WOL_8821C) << BIT_SHIFT_PKT_NUM_WOL_8821C) -#define BIT_GET_PKT_NUM_WOL_8821C(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8821C) & BIT_MASK_PKT_NUM_WOL_8821C) - - - -#define BIT_SHIFT_DMA_AGG_TO_8821C 8 -#define BIT_MASK_DMA_AGG_TO_8821C 0xf -#define BIT_DMA_AGG_TO_8821C(x) (((x) & BIT_MASK_DMA_AGG_TO_8821C) << BIT_SHIFT_DMA_AGG_TO_8821C) -#define BIT_GET_DMA_AGG_TO_8821C(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8821C) & BIT_MASK_DMA_AGG_TO_8821C) - - - -#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C 0 -#define BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C 0xf -#define BIT_RXDMA_AGG_PG_TH_V1_8821C(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C) -#define BIT_GET_RXDMA_AGG_PG_TH_V1_8821C(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C) - - +#define BIT_PKT_NUM_WOL_8821C(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_8821C) << BIT_SHIFT_PKT_NUM_WOL_8821C) +#define BITS_PKT_NUM_WOL_8821C \ + (BIT_MASK_PKT_NUM_WOL_8821C << BIT_SHIFT_PKT_NUM_WOL_8821C) +#define BIT_CLEAR_PKT_NUM_WOL_8821C(x) ((x) & (~BITS_PKT_NUM_WOL_8821C)) +#define BIT_GET_PKT_NUM_WOL_8821C(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_8821C) & BIT_MASK_PKT_NUM_WOL_8821C) +#define BIT_SET_PKT_NUM_WOL_8821C(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_8821C(x) | BIT_PKT_NUM_WOL_8821C(v)) + +#define BIT_SHIFT_DMA_AGG_TO_V1_8821C 8 +#define BIT_MASK_DMA_AGG_TO_V1_8821C 0xff +#define BIT_DMA_AGG_TO_V1_8821C(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1_8821C) << BIT_SHIFT_DMA_AGG_TO_V1_8821C) +#define BITS_DMA_AGG_TO_V1_8821C \ + (BIT_MASK_DMA_AGG_TO_V1_8821C << BIT_SHIFT_DMA_AGG_TO_V1_8821C) +#define BIT_CLEAR_DMA_AGG_TO_V1_8821C(x) ((x) & (~BITS_DMA_AGG_TO_V1_8821C)) +#define BIT_GET_DMA_AGG_TO_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8821C) & BIT_MASK_DMA_AGG_TO_V1_8821C) +#define BIT_SET_DMA_AGG_TO_V1_8821C(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1_8821C(x) | BIT_DMA_AGG_TO_V1_8821C(v)) + +#define BIT_SHIFT_RXDMA_AGG_PG_TH_8821C 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_8821C 0xff +#define BIT_RXDMA_AGG_PG_TH_8821C(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8821C) \ + << BIT_SHIFT_RXDMA_AGG_PG_TH_8821C) +#define BITS_RXDMA_AGG_PG_TH_8821C \ + (BIT_MASK_RXDMA_AGG_PG_TH_8821C << BIT_SHIFT_RXDMA_AGG_PG_TH_8821C) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_8821C(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8821C)) +#define BIT_GET_RXDMA_AGG_PG_TH_8821C(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8821C) & \ + BIT_MASK_RXDMA_AGG_PG_TH_8821C) +#define BIT_SET_RXDMA_AGG_PG_TH_8821C(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_8821C(x) | BIT_RXDMA_AGG_PG_TH_8821C(v)) /* 2 REG_RXPKT_NUM_8821C */ #define BIT_SHIFT_RXPKT_NUM_8821C 24 #define BIT_MASK_RXPKT_NUM_8821C 0xff -#define BIT_RXPKT_NUM_8821C(x) (((x) & BIT_MASK_RXPKT_NUM_8821C) << BIT_SHIFT_RXPKT_NUM_8821C) -#define BIT_GET_RXPKT_NUM_8821C(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8821C) & BIT_MASK_RXPKT_NUM_8821C) - - +#define BIT_RXPKT_NUM_8821C(x) \ + (((x) & BIT_MASK_RXPKT_NUM_8821C) << BIT_SHIFT_RXPKT_NUM_8821C) +#define BITS_RXPKT_NUM_8821C \ + (BIT_MASK_RXPKT_NUM_8821C << BIT_SHIFT_RXPKT_NUM_8821C) +#define BIT_CLEAR_RXPKT_NUM_8821C(x) ((x) & (~BITS_RXPKT_NUM_8821C)) +#define BIT_GET_RXPKT_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_8821C) & BIT_MASK_RXPKT_NUM_8821C) +#define BIT_SET_RXPKT_NUM_8821C(x, v) \ + (BIT_CLEAR_RXPKT_NUM_8821C(x) | BIT_RXPKT_NUM_8821C(v)) #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C 20 #define BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C 0xf -#define BIT_FW_UPD_RDPTR19_TO_16_8821C(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) -#define BIT_GET_FW_UPD_RDPTR19_TO_16_8821C(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) - +#define BIT_FW_UPD_RDPTR19_TO_16_8821C(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) +#define BITS_FW_UPD_RDPTR19_TO_16_8821C \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8821C(x) \ + ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8821C)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8821C(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) +#define BIT_SET_FW_UPD_RDPTR19_TO_16_8821C(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8821C(x) | \ + BIT_FW_UPD_RDPTR19_TO_16_8821C(v)) #define BIT_RXDMA_REQ_8821C BIT(19) #define BIT_RW_RELEASE_EN_8821C BIT(18) @@ -3916,10 +6425,15 @@ #define BIT_SHIFT_FW_UPD_RDPTR_8821C 0 #define BIT_MASK_FW_UPD_RDPTR_8821C 0xffff -#define BIT_FW_UPD_RDPTR_8821C(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8821C) << BIT_SHIFT_FW_UPD_RDPTR_8821C) -#define BIT_GET_FW_UPD_RDPTR_8821C(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8821C) & BIT_MASK_FW_UPD_RDPTR_8821C) - - +#define BIT_FW_UPD_RDPTR_8821C(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR_8821C) << BIT_SHIFT_FW_UPD_RDPTR_8821C) +#define BITS_FW_UPD_RDPTR_8821C \ + (BIT_MASK_FW_UPD_RDPTR_8821C << BIT_SHIFT_FW_UPD_RDPTR_8821C) +#define BIT_CLEAR_FW_UPD_RDPTR_8821C(x) ((x) & (~BITS_FW_UPD_RDPTR_8821C)) +#define BIT_GET_FW_UPD_RDPTR_8821C(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8821C) & BIT_MASK_FW_UPD_RDPTR_8821C) +#define BIT_SET_FW_UPD_RDPTR_8821C(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR_8821C(x) | BIT_FW_UPD_RDPTR_8821C(v)) /* 2 REG_RXDMA_STATUS_8821C */ #define BIT_C2H_PKT_OVF_8821C BIT(7) @@ -3934,40 +6448,67 @@ #define BIT_SHIFT_RDE_DEBUG_8821C 0 #define BIT_MASK_RDE_DEBUG_8821C 0xffffffffL -#define BIT_RDE_DEBUG_8821C(x) (((x) & BIT_MASK_RDE_DEBUG_8821C) << BIT_SHIFT_RDE_DEBUG_8821C) -#define BIT_GET_RDE_DEBUG_8821C(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8821C) & BIT_MASK_RDE_DEBUG_8821C) - - +#define BIT_RDE_DEBUG_8821C(x) \ + (((x) & BIT_MASK_RDE_DEBUG_8821C) << BIT_SHIFT_RDE_DEBUG_8821C) +#define BITS_RDE_DEBUG_8821C \ + (BIT_MASK_RDE_DEBUG_8821C << BIT_SHIFT_RDE_DEBUG_8821C) +#define BIT_CLEAR_RDE_DEBUG_8821C(x) ((x) & (~BITS_RDE_DEBUG_8821C)) +#define BIT_GET_RDE_DEBUG_8821C(x) \ + (((x) >> BIT_SHIFT_RDE_DEBUG_8821C) & BIT_MASK_RDE_DEBUG_8821C) +#define BIT_SET_RDE_DEBUG_8821C(x, v) \ + (BIT_CLEAR_RDE_DEBUG_8821C(x) | BIT_RDE_DEBUG_8821C(v)) /* 2 REG_RXDMA_MODE_8821C */ #define BIT_SHIFT_PKTNUM_TH_V2_8821C 24 #define BIT_MASK_PKTNUM_TH_V2_8821C 0x1f -#define BIT_PKTNUM_TH_V2_8821C(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8821C) << BIT_SHIFT_PKTNUM_TH_V2_8821C) -#define BIT_GET_PKTNUM_TH_V2_8821C(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8821C) & BIT_MASK_PKTNUM_TH_V2_8821C) - +#define BIT_PKTNUM_TH_V2_8821C(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V2_8821C) << BIT_SHIFT_PKTNUM_TH_V2_8821C) +#define BITS_PKTNUM_TH_V2_8821C \ + (BIT_MASK_PKTNUM_TH_V2_8821C << BIT_SHIFT_PKTNUM_TH_V2_8821C) +#define BIT_CLEAR_PKTNUM_TH_V2_8821C(x) ((x) & (~BITS_PKTNUM_TH_V2_8821C)) +#define BIT_GET_PKTNUM_TH_V2_8821C(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8821C) & BIT_MASK_PKTNUM_TH_V2_8821C) +#define BIT_SET_PKTNUM_TH_V2_8821C(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V2_8821C(x) | BIT_PKTNUM_TH_V2_8821C(v)) #define BIT_TXBA_BREAK_USBAGG_8821C BIT(23) #define BIT_SHIFT_PKTLEN_PARA_8821C 16 #define BIT_MASK_PKTLEN_PARA_8821C 0x7 -#define BIT_PKTLEN_PARA_8821C(x) (((x) & BIT_MASK_PKTLEN_PARA_8821C) << BIT_SHIFT_PKTLEN_PARA_8821C) -#define BIT_GET_PKTLEN_PARA_8821C(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8821C) & BIT_MASK_PKTLEN_PARA_8821C) - - +#define BIT_PKTLEN_PARA_8821C(x) \ + (((x) & BIT_MASK_PKTLEN_PARA_8821C) << BIT_SHIFT_PKTLEN_PARA_8821C) +#define BITS_PKTLEN_PARA_8821C \ + (BIT_MASK_PKTLEN_PARA_8821C << BIT_SHIFT_PKTLEN_PARA_8821C) +#define BIT_CLEAR_PKTLEN_PARA_8821C(x) ((x) & (~BITS_PKTLEN_PARA_8821C)) +#define BIT_GET_PKTLEN_PARA_8821C(x) \ + (((x) >> BIT_SHIFT_PKTLEN_PARA_8821C) & BIT_MASK_PKTLEN_PARA_8821C) +#define BIT_SET_PKTLEN_PARA_8821C(x, v) \ + (BIT_CLEAR_PKTLEN_PARA_8821C(x) | BIT_PKTLEN_PARA_8821C(v)) #define BIT_SHIFT_BURST_SIZE_8821C 4 #define BIT_MASK_BURST_SIZE_8821C 0x3 -#define BIT_BURST_SIZE_8821C(x) (((x) & BIT_MASK_BURST_SIZE_8821C) << BIT_SHIFT_BURST_SIZE_8821C) -#define BIT_GET_BURST_SIZE_8821C(x) (((x) >> BIT_SHIFT_BURST_SIZE_8821C) & BIT_MASK_BURST_SIZE_8821C) - - +#define BIT_BURST_SIZE_8821C(x) \ + (((x) & BIT_MASK_BURST_SIZE_8821C) << BIT_SHIFT_BURST_SIZE_8821C) +#define BITS_BURST_SIZE_8821C \ + (BIT_MASK_BURST_SIZE_8821C << BIT_SHIFT_BURST_SIZE_8821C) +#define BIT_CLEAR_BURST_SIZE_8821C(x) ((x) & (~BITS_BURST_SIZE_8821C)) +#define BIT_GET_BURST_SIZE_8821C(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE_8821C) & BIT_MASK_BURST_SIZE_8821C) +#define BIT_SET_BURST_SIZE_8821C(x, v) \ + (BIT_CLEAR_BURST_SIZE_8821C(x) | BIT_BURST_SIZE_8821C(v)) #define BIT_SHIFT_BURST_CNT_8821C 2 #define BIT_MASK_BURST_CNT_8821C 0x3 -#define BIT_BURST_CNT_8821C(x) (((x) & BIT_MASK_BURST_CNT_8821C) << BIT_SHIFT_BURST_CNT_8821C) -#define BIT_GET_BURST_CNT_8821C(x) (((x) >> BIT_SHIFT_BURST_CNT_8821C) & BIT_MASK_BURST_CNT_8821C) - +#define BIT_BURST_CNT_8821C(x) \ + (((x) & BIT_MASK_BURST_CNT_8821C) << BIT_SHIFT_BURST_CNT_8821C) +#define BITS_BURST_CNT_8821C \ + (BIT_MASK_BURST_CNT_8821C << BIT_SHIFT_BURST_CNT_8821C) +#define BIT_CLEAR_BURST_CNT_8821C(x) ((x) & (~BITS_BURST_CNT_8821C)) +#define BIT_GET_BURST_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_BURST_CNT_8821C) & BIT_MASK_BURST_CNT_8821C) +#define BIT_SET_BURST_CNT_8821C(x, v) \ + (BIT_CLEAR_BURST_CNT_8821C(x) | BIT_BURST_CNT_8821C(v)) #define BIT_DMA_MODE_8821C BIT(1) @@ -3975,81 +6516,143 @@ #define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C 24 #define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C 0xf -#define BIT_R_C2H_STR_ADDR_16_TO_19_8821C(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) -#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8821C(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) - +#define BIT_R_C2H_STR_ADDR_16_TO_19_8821C(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) +#define BITS_R_C2H_STR_ADDR_16_TO_19_8821C \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8821C(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8821C)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8821C(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8821C(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8821C(x) | \ + BIT_R_C2H_STR_ADDR_16_TO_19_8821C(v)) #define BIT_R_C2H_PKT_REQ_8821C BIT(16) #define BIT_SHIFT_R_C2H_STR_ADDR_8821C 0 #define BIT_MASK_R_C2H_STR_ADDR_8821C 0xffff -#define BIT_R_C2H_STR_ADDR_8821C(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8821C) << BIT_SHIFT_R_C2H_STR_ADDR_8821C) -#define BIT_GET_R_C2H_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8821C) & BIT_MASK_R_C2H_STR_ADDR_8821C) - - +#define BIT_R_C2H_STR_ADDR_8821C(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_8821C) \ + << BIT_SHIFT_R_C2H_STR_ADDR_8821C) +#define BITS_R_C2H_STR_ADDR_8821C \ + (BIT_MASK_R_C2H_STR_ADDR_8821C << BIT_SHIFT_R_C2H_STR_ADDR_8821C) +#define BIT_CLEAR_R_C2H_STR_ADDR_8821C(x) ((x) & (~BITS_R_C2H_STR_ADDR_8821C)) +#define BIT_GET_R_C2H_STR_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8821C) & \ + BIT_MASK_R_C2H_STR_ADDR_8821C) +#define BIT_SET_R_C2H_STR_ADDR_8821C(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_8821C(x) | BIT_R_C2H_STR_ADDR_8821C(v)) /* 2 REG_FWFF_C2H_8821C */ #define BIT_SHIFT_C2H_DMA_ADDR_8821C 0 #define BIT_MASK_C2H_DMA_ADDR_8821C 0x3ffff -#define BIT_C2H_DMA_ADDR_8821C(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8821C) << BIT_SHIFT_C2H_DMA_ADDR_8821C) -#define BIT_GET_C2H_DMA_ADDR_8821C(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8821C) & BIT_MASK_C2H_DMA_ADDR_8821C) - - +#define BIT_C2H_DMA_ADDR_8821C(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR_8821C) << BIT_SHIFT_C2H_DMA_ADDR_8821C) +#define BITS_C2H_DMA_ADDR_8821C \ + (BIT_MASK_C2H_DMA_ADDR_8821C << BIT_SHIFT_C2H_DMA_ADDR_8821C) +#define BIT_CLEAR_C2H_DMA_ADDR_8821C(x) ((x) & (~BITS_C2H_DMA_ADDR_8821C)) +#define BIT_GET_C2H_DMA_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8821C) & BIT_MASK_C2H_DMA_ADDR_8821C) +#define BIT_SET_C2H_DMA_ADDR_8821C(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR_8821C(x) | BIT_C2H_DMA_ADDR_8821C(v)) /* 2 REG_FWFF_CTRL_8821C */ #define BIT_FWFF_DMAPKT_REQ_8821C BIT(31) #define BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C 16 #define BIT_MASK_FWFF_DMA_PKT_NUM_8821C 0xff -#define BIT_FWFF_DMA_PKT_NUM_8821C(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) -#define BIT_GET_FWFF_DMA_PKT_NUM_8821C(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C) - - +#define BIT_FWFF_DMA_PKT_NUM_8821C(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C) \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) +#define BITS_FWFF_DMA_PKT_NUM_8821C \ + (BIT_MASK_FWFF_DMA_PKT_NUM_8821C << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8821C(x) \ + ((x) & (~BITS_FWFF_DMA_PKT_NUM_8821C)) +#define BIT_GET_FWFF_DMA_PKT_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) & \ + BIT_MASK_FWFF_DMA_PKT_NUM_8821C) +#define BIT_SET_FWFF_DMA_PKT_NUM_8821C(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_8821C(x) | BIT_FWFF_DMA_PKT_NUM_8821C(v)) #define BIT_SHIFT_FWFF_STR_ADDR_8821C 0 #define BIT_MASK_FWFF_STR_ADDR_8821C 0xffff -#define BIT_FWFF_STR_ADDR_8821C(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8821C) << BIT_SHIFT_FWFF_STR_ADDR_8821C) -#define BIT_GET_FWFF_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8821C) & BIT_MASK_FWFF_STR_ADDR_8821C) - - +#define BIT_FWFF_STR_ADDR_8821C(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR_8821C) << BIT_SHIFT_FWFF_STR_ADDR_8821C) +#define BITS_FWFF_STR_ADDR_8821C \ + (BIT_MASK_FWFF_STR_ADDR_8821C << BIT_SHIFT_FWFF_STR_ADDR_8821C) +#define BIT_CLEAR_FWFF_STR_ADDR_8821C(x) ((x) & (~BITS_FWFF_STR_ADDR_8821C)) +#define BIT_GET_FWFF_STR_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8821C) & BIT_MASK_FWFF_STR_ADDR_8821C) +#define BIT_SET_FWFF_STR_ADDR_8821C(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR_8821C(x) | BIT_FWFF_STR_ADDR_8821C(v)) /* 2 REG_FWFF_PKT_INFO_8821C */ #define BIT_SHIFT_FWFF_PKT_QUEUED_8821C 16 #define BIT_MASK_FWFF_PKT_QUEUED_8821C 0xff -#define BIT_FWFF_PKT_QUEUED_8821C(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8821C) << BIT_SHIFT_FWFF_PKT_QUEUED_8821C) -#define BIT_GET_FWFF_PKT_QUEUED_8821C(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8821C) & BIT_MASK_FWFF_PKT_QUEUED_8821C) - - +#define BIT_FWFF_PKT_QUEUED_8821C(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_8821C) \ + << BIT_SHIFT_FWFF_PKT_QUEUED_8821C) +#define BITS_FWFF_PKT_QUEUED_8821C \ + (BIT_MASK_FWFF_PKT_QUEUED_8821C << BIT_SHIFT_FWFF_PKT_QUEUED_8821C) +#define BIT_CLEAR_FWFF_PKT_QUEUED_8821C(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8821C)) +#define BIT_GET_FWFF_PKT_QUEUED_8821C(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8821C) & \ + BIT_MASK_FWFF_PKT_QUEUED_8821C) +#define BIT_SET_FWFF_PKT_QUEUED_8821C(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_8821C(x) | BIT_FWFF_PKT_QUEUED_8821C(v)) #define BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C 0 #define BIT_MASK_FWFF_PKT_STR_ADDR_8821C 0xffff -#define BIT_FWFF_PKT_STR_ADDR_8821C(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) -#define BIT_GET_FWFF_PKT_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) - - +#define BIT_FWFF_PKT_STR_ADDR_8821C(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) +#define BITS_FWFF_PKT_STR_ADDR_8821C \ + (BIT_MASK_FWFF_PKT_STR_ADDR_8821C << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8821C(x) \ + ((x) & (~BITS_FWFF_PKT_STR_ADDR_8821C)) +#define BIT_GET_FWFF_PKT_STR_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_8821C) +#define BIT_SET_FWFF_PKT_STR_ADDR_8821C(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_8821C(x) | BIT_FWFF_PKT_STR_ADDR_8821C(v)) /* 2 REG_DDMA_CH0SA_8821C */ #define BIT_SHIFT_DDMACH0_SA_8821C 0 #define BIT_MASK_DDMACH0_SA_8821C 0xffffffffL -#define BIT_DDMACH0_SA_8821C(x) (((x) & BIT_MASK_DDMACH0_SA_8821C) << BIT_SHIFT_DDMACH0_SA_8821C) -#define BIT_GET_DDMACH0_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8821C) & BIT_MASK_DDMACH0_SA_8821C) - - +#define BIT_DDMACH0_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH0_SA_8821C) << BIT_SHIFT_DDMACH0_SA_8821C) +#define BITS_DDMACH0_SA_8821C \ + (BIT_MASK_DDMACH0_SA_8821C << BIT_SHIFT_DDMACH0_SA_8821C) +#define BIT_CLEAR_DDMACH0_SA_8821C(x) ((x) & (~BITS_DDMACH0_SA_8821C)) +#define BIT_GET_DDMACH0_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA_8821C) & BIT_MASK_DDMACH0_SA_8821C) +#define BIT_SET_DDMACH0_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH0_SA_8821C(x) | BIT_DDMACH0_SA_8821C(v)) /* 2 REG_DDMA_CH0DA_8821C */ #define BIT_SHIFT_DDMACH0_DA_8821C 0 #define BIT_MASK_DDMACH0_DA_8821C 0xffffffffL -#define BIT_DDMACH0_DA_8821C(x) (((x) & BIT_MASK_DDMACH0_DA_8821C) << BIT_SHIFT_DDMACH0_DA_8821C) -#define BIT_GET_DDMACH0_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8821C) & BIT_MASK_DDMACH0_DA_8821C) - - +#define BIT_DDMACH0_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH0_DA_8821C) << BIT_SHIFT_DDMACH0_DA_8821C) +#define BITS_DDMACH0_DA_8821C \ + (BIT_MASK_DDMACH0_DA_8821C << BIT_SHIFT_DDMACH0_DA_8821C) +#define BIT_CLEAR_DDMACH0_DA_8821C(x) ((x) & (~BITS_DDMACH0_DA_8821C)) +#define BIT_GET_DDMACH0_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA_8821C) & BIT_MASK_DDMACH0_DA_8821C) +#define BIT_SET_DDMACH0_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH0_DA_8821C(x) | BIT_DDMACH0_DA_8821C(v)) /* 2 REG_DDMA_CH0CTRL_8821C */ #define BIT_DDMACH0_OWN_8821C BIT(31) +#define BIT_DDMACH0_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH0_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH0_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH0_CHKSUM_STS_8821C BIT(27) @@ -4059,31 +6662,47 @@ #define BIT_SHIFT_DDMACH0_DLEN_8821C 0 #define BIT_MASK_DDMACH0_DLEN_8821C 0x3ffff -#define BIT_DDMACH0_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH0_DLEN_8821C) << BIT_SHIFT_DDMACH0_DLEN_8821C) -#define BIT_GET_DDMACH0_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8821C) & BIT_MASK_DDMACH0_DLEN_8821C) - - +#define BIT_DDMACH0_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN_8821C) << BIT_SHIFT_DDMACH0_DLEN_8821C) +#define BITS_DDMACH0_DLEN_8821C \ + (BIT_MASK_DDMACH0_DLEN_8821C << BIT_SHIFT_DDMACH0_DLEN_8821C) +#define BIT_CLEAR_DDMACH0_DLEN_8821C(x) ((x) & (~BITS_DDMACH0_DLEN_8821C)) +#define BIT_GET_DDMACH0_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN_8821C) & BIT_MASK_DDMACH0_DLEN_8821C) +#define BIT_SET_DDMACH0_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN_8821C(x) | BIT_DDMACH0_DLEN_8821C(v)) /* 2 REG_DDMA_CH1SA_8821C */ #define BIT_SHIFT_DDMACH1_SA_8821C 0 #define BIT_MASK_DDMACH1_SA_8821C 0xffffffffL -#define BIT_DDMACH1_SA_8821C(x) (((x) & BIT_MASK_DDMACH1_SA_8821C) << BIT_SHIFT_DDMACH1_SA_8821C) -#define BIT_GET_DDMACH1_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8821C) & BIT_MASK_DDMACH1_SA_8821C) - - +#define BIT_DDMACH1_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH1_SA_8821C) << BIT_SHIFT_DDMACH1_SA_8821C) +#define BITS_DDMACH1_SA_8821C \ + (BIT_MASK_DDMACH1_SA_8821C << BIT_SHIFT_DDMACH1_SA_8821C) +#define BIT_CLEAR_DDMACH1_SA_8821C(x) ((x) & (~BITS_DDMACH1_SA_8821C)) +#define BIT_GET_DDMACH1_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA_8821C) & BIT_MASK_DDMACH1_SA_8821C) +#define BIT_SET_DDMACH1_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH1_SA_8821C(x) | BIT_DDMACH1_SA_8821C(v)) /* 2 REG_DDMA_CH1DA_8821C */ #define BIT_SHIFT_DDMACH1_DA_8821C 0 #define BIT_MASK_DDMACH1_DA_8821C 0xffffffffL -#define BIT_DDMACH1_DA_8821C(x) (((x) & BIT_MASK_DDMACH1_DA_8821C) << BIT_SHIFT_DDMACH1_DA_8821C) -#define BIT_GET_DDMACH1_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8821C) & BIT_MASK_DDMACH1_DA_8821C) - - +#define BIT_DDMACH1_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH1_DA_8821C) << BIT_SHIFT_DDMACH1_DA_8821C) +#define BITS_DDMACH1_DA_8821C \ + (BIT_MASK_DDMACH1_DA_8821C << BIT_SHIFT_DDMACH1_DA_8821C) +#define BIT_CLEAR_DDMACH1_DA_8821C(x) ((x) & (~BITS_DDMACH1_DA_8821C)) +#define BIT_GET_DDMACH1_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA_8821C) & BIT_MASK_DDMACH1_DA_8821C) +#define BIT_SET_DDMACH1_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH1_DA_8821C(x) | BIT_DDMACH1_DA_8821C(v)) /* 2 REG_DDMA_CH1CTRL_8821C */ #define BIT_DDMACH1_OWN_8821C BIT(31) +#define BIT_DDMACH1_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH1_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH1_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH1_CHKSUM_STS_8821C BIT(27) @@ -4093,31 +6712,47 @@ #define BIT_SHIFT_DDMACH1_DLEN_8821C 0 #define BIT_MASK_DDMACH1_DLEN_8821C 0x3ffff -#define BIT_DDMACH1_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH1_DLEN_8821C) << BIT_SHIFT_DDMACH1_DLEN_8821C) -#define BIT_GET_DDMACH1_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8821C) & BIT_MASK_DDMACH1_DLEN_8821C) - - +#define BIT_DDMACH1_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN_8821C) << BIT_SHIFT_DDMACH1_DLEN_8821C) +#define BITS_DDMACH1_DLEN_8821C \ + (BIT_MASK_DDMACH1_DLEN_8821C << BIT_SHIFT_DDMACH1_DLEN_8821C) +#define BIT_CLEAR_DDMACH1_DLEN_8821C(x) ((x) & (~BITS_DDMACH1_DLEN_8821C)) +#define BIT_GET_DDMACH1_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN_8821C) & BIT_MASK_DDMACH1_DLEN_8821C) +#define BIT_SET_DDMACH1_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN_8821C(x) | BIT_DDMACH1_DLEN_8821C(v)) /* 2 REG_DDMA_CH2SA_8821C */ #define BIT_SHIFT_DDMACH2_SA_8821C 0 #define BIT_MASK_DDMACH2_SA_8821C 0xffffffffL -#define BIT_DDMACH2_SA_8821C(x) (((x) & BIT_MASK_DDMACH2_SA_8821C) << BIT_SHIFT_DDMACH2_SA_8821C) -#define BIT_GET_DDMACH2_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8821C) & BIT_MASK_DDMACH2_SA_8821C) - - +#define BIT_DDMACH2_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH2_SA_8821C) << BIT_SHIFT_DDMACH2_SA_8821C) +#define BITS_DDMACH2_SA_8821C \ + (BIT_MASK_DDMACH2_SA_8821C << BIT_SHIFT_DDMACH2_SA_8821C) +#define BIT_CLEAR_DDMACH2_SA_8821C(x) ((x) & (~BITS_DDMACH2_SA_8821C)) +#define BIT_GET_DDMACH2_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA_8821C) & BIT_MASK_DDMACH2_SA_8821C) +#define BIT_SET_DDMACH2_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH2_SA_8821C(x) | BIT_DDMACH2_SA_8821C(v)) /* 2 REG_DDMA_CH2DA_8821C */ #define BIT_SHIFT_DDMACH2_DA_8821C 0 #define BIT_MASK_DDMACH2_DA_8821C 0xffffffffL -#define BIT_DDMACH2_DA_8821C(x) (((x) & BIT_MASK_DDMACH2_DA_8821C) << BIT_SHIFT_DDMACH2_DA_8821C) -#define BIT_GET_DDMACH2_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8821C) & BIT_MASK_DDMACH2_DA_8821C) - - +#define BIT_DDMACH2_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH2_DA_8821C) << BIT_SHIFT_DDMACH2_DA_8821C) +#define BITS_DDMACH2_DA_8821C \ + (BIT_MASK_DDMACH2_DA_8821C << BIT_SHIFT_DDMACH2_DA_8821C) +#define BIT_CLEAR_DDMACH2_DA_8821C(x) ((x) & (~BITS_DDMACH2_DA_8821C)) +#define BIT_GET_DDMACH2_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA_8821C) & BIT_MASK_DDMACH2_DA_8821C) +#define BIT_SET_DDMACH2_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH2_DA_8821C(x) | BIT_DDMACH2_DA_8821C(v)) /* 2 REG_DDMA_CH2CTRL_8821C */ #define BIT_DDMACH2_OWN_8821C BIT(31) +#define BIT_DDMACH2_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH2_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH2_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH2_CHKSUM_STS_8821C BIT(27) @@ -4127,31 +6762,47 @@ #define BIT_SHIFT_DDMACH2_DLEN_8821C 0 #define BIT_MASK_DDMACH2_DLEN_8821C 0x3ffff -#define BIT_DDMACH2_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH2_DLEN_8821C) << BIT_SHIFT_DDMACH2_DLEN_8821C) -#define BIT_GET_DDMACH2_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8821C) & BIT_MASK_DDMACH2_DLEN_8821C) - - +#define BIT_DDMACH2_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN_8821C) << BIT_SHIFT_DDMACH2_DLEN_8821C) +#define BITS_DDMACH2_DLEN_8821C \ + (BIT_MASK_DDMACH2_DLEN_8821C << BIT_SHIFT_DDMACH2_DLEN_8821C) +#define BIT_CLEAR_DDMACH2_DLEN_8821C(x) ((x) & (~BITS_DDMACH2_DLEN_8821C)) +#define BIT_GET_DDMACH2_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN_8821C) & BIT_MASK_DDMACH2_DLEN_8821C) +#define BIT_SET_DDMACH2_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN_8821C(x) | BIT_DDMACH2_DLEN_8821C(v)) /* 2 REG_DDMA_CH3SA_8821C */ #define BIT_SHIFT_DDMACH3_SA_8821C 0 #define BIT_MASK_DDMACH3_SA_8821C 0xffffffffL -#define BIT_DDMACH3_SA_8821C(x) (((x) & BIT_MASK_DDMACH3_SA_8821C) << BIT_SHIFT_DDMACH3_SA_8821C) -#define BIT_GET_DDMACH3_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8821C) & BIT_MASK_DDMACH3_SA_8821C) - - +#define BIT_DDMACH3_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH3_SA_8821C) << BIT_SHIFT_DDMACH3_SA_8821C) +#define BITS_DDMACH3_SA_8821C \ + (BIT_MASK_DDMACH3_SA_8821C << BIT_SHIFT_DDMACH3_SA_8821C) +#define BIT_CLEAR_DDMACH3_SA_8821C(x) ((x) & (~BITS_DDMACH3_SA_8821C)) +#define BIT_GET_DDMACH3_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA_8821C) & BIT_MASK_DDMACH3_SA_8821C) +#define BIT_SET_DDMACH3_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH3_SA_8821C(x) | BIT_DDMACH3_SA_8821C(v)) /* 2 REG_DDMA_CH3DA_8821C */ #define BIT_SHIFT_DDMACH3_DA_8821C 0 #define BIT_MASK_DDMACH3_DA_8821C 0xffffffffL -#define BIT_DDMACH3_DA_8821C(x) (((x) & BIT_MASK_DDMACH3_DA_8821C) << BIT_SHIFT_DDMACH3_DA_8821C) -#define BIT_GET_DDMACH3_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8821C) & BIT_MASK_DDMACH3_DA_8821C) - - +#define BIT_DDMACH3_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH3_DA_8821C) << BIT_SHIFT_DDMACH3_DA_8821C) +#define BITS_DDMACH3_DA_8821C \ + (BIT_MASK_DDMACH3_DA_8821C << BIT_SHIFT_DDMACH3_DA_8821C) +#define BIT_CLEAR_DDMACH3_DA_8821C(x) ((x) & (~BITS_DDMACH3_DA_8821C)) +#define BIT_GET_DDMACH3_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA_8821C) & BIT_MASK_DDMACH3_DA_8821C) +#define BIT_SET_DDMACH3_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH3_DA_8821C(x) | BIT_DDMACH3_DA_8821C(v)) /* 2 REG_DDMA_CH3CTRL_8821C */ #define BIT_DDMACH3_OWN_8821C BIT(31) +#define BIT_DDMACH3_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH3_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH3_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH3_CHKSUM_STS_8821C BIT(27) @@ -4161,31 +6812,47 @@ #define BIT_SHIFT_DDMACH3_DLEN_8821C 0 #define BIT_MASK_DDMACH3_DLEN_8821C 0x3ffff -#define BIT_DDMACH3_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH3_DLEN_8821C) << BIT_SHIFT_DDMACH3_DLEN_8821C) -#define BIT_GET_DDMACH3_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8821C) & BIT_MASK_DDMACH3_DLEN_8821C) - - +#define BIT_DDMACH3_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN_8821C) << BIT_SHIFT_DDMACH3_DLEN_8821C) +#define BITS_DDMACH3_DLEN_8821C \ + (BIT_MASK_DDMACH3_DLEN_8821C << BIT_SHIFT_DDMACH3_DLEN_8821C) +#define BIT_CLEAR_DDMACH3_DLEN_8821C(x) ((x) & (~BITS_DDMACH3_DLEN_8821C)) +#define BIT_GET_DDMACH3_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN_8821C) & BIT_MASK_DDMACH3_DLEN_8821C) +#define BIT_SET_DDMACH3_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN_8821C(x) | BIT_DDMACH3_DLEN_8821C(v)) /* 2 REG_DDMA_CH4SA_8821C */ #define BIT_SHIFT_DDMACH4_SA_8821C 0 #define BIT_MASK_DDMACH4_SA_8821C 0xffffffffL -#define BIT_DDMACH4_SA_8821C(x) (((x) & BIT_MASK_DDMACH4_SA_8821C) << BIT_SHIFT_DDMACH4_SA_8821C) -#define BIT_GET_DDMACH4_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8821C) & BIT_MASK_DDMACH4_SA_8821C) - - +#define BIT_DDMACH4_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH4_SA_8821C) << BIT_SHIFT_DDMACH4_SA_8821C) +#define BITS_DDMACH4_SA_8821C \ + (BIT_MASK_DDMACH4_SA_8821C << BIT_SHIFT_DDMACH4_SA_8821C) +#define BIT_CLEAR_DDMACH4_SA_8821C(x) ((x) & (~BITS_DDMACH4_SA_8821C)) +#define BIT_GET_DDMACH4_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA_8821C) & BIT_MASK_DDMACH4_SA_8821C) +#define BIT_SET_DDMACH4_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH4_SA_8821C(x) | BIT_DDMACH4_SA_8821C(v)) /* 2 REG_DDMA_CH4DA_8821C */ #define BIT_SHIFT_DDMACH4_DA_8821C 0 #define BIT_MASK_DDMACH4_DA_8821C 0xffffffffL -#define BIT_DDMACH4_DA_8821C(x) (((x) & BIT_MASK_DDMACH4_DA_8821C) << BIT_SHIFT_DDMACH4_DA_8821C) -#define BIT_GET_DDMACH4_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8821C) & BIT_MASK_DDMACH4_DA_8821C) - - +#define BIT_DDMACH4_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH4_DA_8821C) << BIT_SHIFT_DDMACH4_DA_8821C) +#define BITS_DDMACH4_DA_8821C \ + (BIT_MASK_DDMACH4_DA_8821C << BIT_SHIFT_DDMACH4_DA_8821C) +#define BIT_CLEAR_DDMACH4_DA_8821C(x) ((x) & (~BITS_DDMACH4_DA_8821C)) +#define BIT_GET_DDMACH4_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA_8821C) & BIT_MASK_DDMACH4_DA_8821C) +#define BIT_SET_DDMACH4_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH4_DA_8821C(x) | BIT_DDMACH4_DA_8821C(v)) /* 2 REG_DDMA_CH4CTRL_8821C */ #define BIT_DDMACH4_OWN_8821C BIT(31) +#define BIT_DDMACH4_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH4_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH4_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH4_CHKSUM_STS_8821C BIT(27) @@ -4195,31 +6862,47 @@ #define BIT_SHIFT_DDMACH4_DLEN_8821C 0 #define BIT_MASK_DDMACH4_DLEN_8821C 0x3ffff -#define BIT_DDMACH4_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH4_DLEN_8821C) << BIT_SHIFT_DDMACH4_DLEN_8821C) -#define BIT_GET_DDMACH4_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8821C) & BIT_MASK_DDMACH4_DLEN_8821C) - - +#define BIT_DDMACH4_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN_8821C) << BIT_SHIFT_DDMACH4_DLEN_8821C) +#define BITS_DDMACH4_DLEN_8821C \ + (BIT_MASK_DDMACH4_DLEN_8821C << BIT_SHIFT_DDMACH4_DLEN_8821C) +#define BIT_CLEAR_DDMACH4_DLEN_8821C(x) ((x) & (~BITS_DDMACH4_DLEN_8821C)) +#define BIT_GET_DDMACH4_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN_8821C) & BIT_MASK_DDMACH4_DLEN_8821C) +#define BIT_SET_DDMACH4_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN_8821C(x) | BIT_DDMACH4_DLEN_8821C(v)) /* 2 REG_DDMA_CH5SA_8821C */ #define BIT_SHIFT_DDMACH5_SA_8821C 0 #define BIT_MASK_DDMACH5_SA_8821C 0xffffffffL -#define BIT_DDMACH5_SA_8821C(x) (((x) & BIT_MASK_DDMACH5_SA_8821C) << BIT_SHIFT_DDMACH5_SA_8821C) -#define BIT_GET_DDMACH5_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8821C) & BIT_MASK_DDMACH5_SA_8821C) - - +#define BIT_DDMACH5_SA_8821C(x) \ + (((x) & BIT_MASK_DDMACH5_SA_8821C) << BIT_SHIFT_DDMACH5_SA_8821C) +#define BITS_DDMACH5_SA_8821C \ + (BIT_MASK_DDMACH5_SA_8821C << BIT_SHIFT_DDMACH5_SA_8821C) +#define BIT_CLEAR_DDMACH5_SA_8821C(x) ((x) & (~BITS_DDMACH5_SA_8821C)) +#define BIT_GET_DDMACH5_SA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA_8821C) & BIT_MASK_DDMACH5_SA_8821C) +#define BIT_SET_DDMACH5_SA_8821C(x, v) \ + (BIT_CLEAR_DDMACH5_SA_8821C(x) | BIT_DDMACH5_SA_8821C(v)) /* 2 REG_DDMA_CH5DA_8821C */ #define BIT_SHIFT_DDMACH5_DA_8821C 0 #define BIT_MASK_DDMACH5_DA_8821C 0xffffffffL -#define BIT_DDMACH5_DA_8821C(x) (((x) & BIT_MASK_DDMACH5_DA_8821C) << BIT_SHIFT_DDMACH5_DA_8821C) -#define BIT_GET_DDMACH5_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8821C) & BIT_MASK_DDMACH5_DA_8821C) - - +#define BIT_DDMACH5_DA_8821C(x) \ + (((x) & BIT_MASK_DDMACH5_DA_8821C) << BIT_SHIFT_DDMACH5_DA_8821C) +#define BITS_DDMACH5_DA_8821C \ + (BIT_MASK_DDMACH5_DA_8821C << BIT_SHIFT_DDMACH5_DA_8821C) +#define BIT_CLEAR_DDMACH5_DA_8821C(x) ((x) & (~BITS_DDMACH5_DA_8821C)) +#define BIT_GET_DDMACH5_DA_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA_8821C) & BIT_MASK_DDMACH5_DA_8821C) +#define BIT_SET_DDMACH5_DA_8821C(x, v) \ + (BIT_CLEAR_DDMACH5_DA_8821C(x) | BIT_DDMACH5_DA_8821C(v)) /* 2 REG_DDMA_CH5CTRL_8821C */ #define BIT_DDMACH5_OWN_8821C BIT(31) +#define BIT_DDMACH5_IDMEM_ERR_8821C BIT(30) #define BIT_DDMACH5_CHKSUM_EN_8821C BIT(29) #define BIT_DDMACH5_DA_W_DISABLE_8821C BIT(28) #define BIT_DDMACH5_CHKSUM_STS_8821C BIT(27) @@ -4229,10 +6912,15 @@ #define BIT_SHIFT_DDMACH5_DLEN_8821C 0 #define BIT_MASK_DDMACH5_DLEN_8821C 0x3ffff -#define BIT_DDMACH5_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH5_DLEN_8821C) << BIT_SHIFT_DDMACH5_DLEN_8821C) -#define BIT_GET_DDMACH5_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8821C) & BIT_MASK_DDMACH5_DLEN_8821C) - - +#define BIT_DDMACH5_DLEN_8821C(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN_8821C) << BIT_SHIFT_DDMACH5_DLEN_8821C) +#define BITS_DDMACH5_DLEN_8821C \ + (BIT_MASK_DDMACH5_DLEN_8821C << BIT_SHIFT_DDMACH5_DLEN_8821C) +#define BIT_CLEAR_DDMACH5_DLEN_8821C(x) ((x) & (~BITS_DDMACH5_DLEN_8821C)) +#define BIT_GET_DDMACH5_DLEN_8821C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN_8821C) & BIT_MASK_DDMACH5_DLEN_8821C) +#define BIT_SET_DDMACH5_DLEN_8821C(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN_8821C(x) | BIT_DDMACH5_DLEN_8821C(v)) /* 2 REG_DDMA_INT_MSK_8821C */ #define BIT_DDMACH5_MSK_8821C BIT(5) @@ -4254,10 +6942,15 @@ #define BIT_SHIFT_IDDMA0_CHKSUM_8821C 0 #define BIT_MASK_IDDMA0_CHKSUM_8821C 0xffff -#define BIT_IDDMA0_CHKSUM_8821C(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8821C) << BIT_SHIFT_IDDMA0_CHKSUM_8821C) -#define BIT_GET_IDDMA0_CHKSUM_8821C(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8821C) & BIT_MASK_IDDMA0_CHKSUM_8821C) - - +#define BIT_IDDMA0_CHKSUM_8821C(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM_8821C) << BIT_SHIFT_IDDMA0_CHKSUM_8821C) +#define BITS_IDDMA0_CHKSUM_8821C \ + (BIT_MASK_IDDMA0_CHKSUM_8821C << BIT_SHIFT_IDDMA0_CHKSUM_8821C) +#define BIT_CLEAR_IDDMA0_CHKSUM_8821C(x) ((x) & (~BITS_IDDMA0_CHKSUM_8821C)) +#define BIT_GET_IDDMA0_CHKSUM_8821C(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8821C) & BIT_MASK_IDDMA0_CHKSUM_8821C) +#define BIT_SET_IDDMA0_CHKSUM_8821C(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM_8821C(x) | BIT_IDDMA0_CHKSUM_8821C(v)) /* 2 REG_DDMA_MONITOR_8821C */ #define BIT_IDDMA0_PERMU_UNDERFLOW_8821C BIT(14) @@ -4277,17 +6970,33 @@ #define BIT_SHIFT_PCIE_MAX_RXDMA_8821C 28 #define BIT_MASK_PCIE_MAX_RXDMA_8821C 0x7 -#define BIT_PCIE_MAX_RXDMA_8821C(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8821C) << BIT_SHIFT_PCIE_MAX_RXDMA_8821C) -#define BIT_GET_PCIE_MAX_RXDMA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8821C) & BIT_MASK_PCIE_MAX_RXDMA_8821C) - +#define BIT_PCIE_MAX_RXDMA_8821C(x) \ + (((x) & BIT_MASK_PCIE_MAX_RXDMA_8821C) \ + << BIT_SHIFT_PCIE_MAX_RXDMA_8821C) +#define BITS_PCIE_MAX_RXDMA_8821C \ + (BIT_MASK_PCIE_MAX_RXDMA_8821C << BIT_SHIFT_PCIE_MAX_RXDMA_8821C) +#define BIT_CLEAR_PCIE_MAX_RXDMA_8821C(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8821C)) +#define BIT_GET_PCIE_MAX_RXDMA_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8821C) & \ + BIT_MASK_PCIE_MAX_RXDMA_8821C) +#define BIT_SET_PCIE_MAX_RXDMA_8821C(x, v) \ + (BIT_CLEAR_PCIE_MAX_RXDMA_8821C(x) | BIT_PCIE_MAX_RXDMA_8821C(v)) #define BIT_MULRW_8821C BIT(27) #define BIT_SHIFT_PCIE_MAX_TXDMA_8821C 24 #define BIT_MASK_PCIE_MAX_TXDMA_8821C 0x7 -#define BIT_PCIE_MAX_TXDMA_8821C(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8821C) << BIT_SHIFT_PCIE_MAX_TXDMA_8821C) -#define BIT_GET_PCIE_MAX_TXDMA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8821C) & BIT_MASK_PCIE_MAX_TXDMA_8821C) - +#define BIT_PCIE_MAX_TXDMA_8821C(x) \ + (((x) & BIT_MASK_PCIE_MAX_TXDMA_8821C) \ + << BIT_SHIFT_PCIE_MAX_TXDMA_8821C) +#define BITS_PCIE_MAX_TXDMA_8821C \ + (BIT_MASK_PCIE_MAX_TXDMA_8821C << BIT_SHIFT_PCIE_MAX_TXDMA_8821C) +#define BIT_CLEAR_PCIE_MAX_TXDMA_8821C(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8821C)) +#define BIT_GET_PCIE_MAX_TXDMA_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8821C) & \ + BIT_MASK_PCIE_MAX_TXDMA_8821C) +#define BIT_SET_PCIE_MAX_TXDMA_8821C(x, v) \ + (BIT_CLEAR_PCIE_MAX_TXDMA_8821C(x) | BIT_PCIE_MAX_TXDMA_8821C(v)) #define BIT_EN_CPL_TIMEOUT_PS_8821C BIT(22) #define BIT_REG_TXDMA_FAIL_PS_8821C BIT(21) @@ -4317,428 +7026,729 @@ #define BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C 28 #define BIT_MASK_TXTTIMER_MATCH_NUM_8821C 0xf -#define BIT_TXTTIMER_MATCH_NUM_8821C(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) -#define BIT_GET_TXTTIMER_MATCH_NUM_8821C(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C) - - +#define BIT_TXTTIMER_MATCH_NUM_8821C(x) \ + (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C) \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) +#define BITS_TXTTIMER_MATCH_NUM_8821C \ + (BIT_MASK_TXTTIMER_MATCH_NUM_8821C \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) +#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8821C(x) \ + ((x) & (~BITS_TXTTIMER_MATCH_NUM_8821C)) +#define BIT_GET_TXTTIMER_MATCH_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) & \ + BIT_MASK_TXTTIMER_MATCH_NUM_8821C) +#define BIT_SET_TXTTIMER_MATCH_NUM_8821C(x, v) \ + (BIT_CLEAR_TXTTIMER_MATCH_NUM_8821C(x) | \ + BIT_TXTTIMER_MATCH_NUM_8821C(v)) #define BIT_SHIFT_TXPKT_NUM_MATCH_8821C 24 #define BIT_MASK_TXPKT_NUM_MATCH_8821C 0xf -#define BIT_TXPKT_NUM_MATCH_8821C(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8821C) << BIT_SHIFT_TXPKT_NUM_MATCH_8821C) -#define BIT_GET_TXPKT_NUM_MATCH_8821C(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8821C) & BIT_MASK_TXPKT_NUM_MATCH_8821C) - - +#define BIT_TXPKT_NUM_MATCH_8821C(x) \ + (((x) & BIT_MASK_TXPKT_NUM_MATCH_8821C) \ + << BIT_SHIFT_TXPKT_NUM_MATCH_8821C) +#define BITS_TXPKT_NUM_MATCH_8821C \ + (BIT_MASK_TXPKT_NUM_MATCH_8821C << BIT_SHIFT_TXPKT_NUM_MATCH_8821C) +#define BIT_CLEAR_TXPKT_NUM_MATCH_8821C(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8821C)) +#define BIT_GET_TXPKT_NUM_MATCH_8821C(x) \ + (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8821C) & \ + BIT_MASK_TXPKT_NUM_MATCH_8821C) +#define BIT_SET_TXPKT_NUM_MATCH_8821C(x, v) \ + (BIT_CLEAR_TXPKT_NUM_MATCH_8821C(x) | BIT_TXPKT_NUM_MATCH_8821C(v)) #define BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C 20 #define BIT_MASK_RXTTIMER_MATCH_NUM_8821C 0xf -#define BIT_RXTTIMER_MATCH_NUM_8821C(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) -#define BIT_GET_RXTTIMER_MATCH_NUM_8821C(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) - - +#define BIT_RXTTIMER_MATCH_NUM_8821C(x) \ + (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) +#define BITS_RXTTIMER_MATCH_NUM_8821C \ + (BIT_MASK_RXTTIMER_MATCH_NUM_8821C \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) +#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8821C(x) \ + ((x) & (~BITS_RXTTIMER_MATCH_NUM_8821C)) +#define BIT_GET_RXTTIMER_MATCH_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) & \ + BIT_MASK_RXTTIMER_MATCH_NUM_8821C) +#define BIT_SET_RXTTIMER_MATCH_NUM_8821C(x, v) \ + (BIT_CLEAR_RXTTIMER_MATCH_NUM_8821C(x) | \ + BIT_RXTTIMER_MATCH_NUM_8821C(v)) #define BIT_SHIFT_RXPKT_NUM_MATCH_8821C 16 #define BIT_MASK_RXPKT_NUM_MATCH_8821C 0xf -#define BIT_RXPKT_NUM_MATCH_8821C(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8821C) << BIT_SHIFT_RXPKT_NUM_MATCH_8821C) -#define BIT_GET_RXPKT_NUM_MATCH_8821C(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8821C) & BIT_MASK_RXPKT_NUM_MATCH_8821C) - - +#define BIT_RXPKT_NUM_MATCH_8821C(x) \ + (((x) & BIT_MASK_RXPKT_NUM_MATCH_8821C) \ + << BIT_SHIFT_RXPKT_NUM_MATCH_8821C) +#define BITS_RXPKT_NUM_MATCH_8821C \ + (BIT_MASK_RXPKT_NUM_MATCH_8821C << BIT_SHIFT_RXPKT_NUM_MATCH_8821C) +#define BIT_CLEAR_RXPKT_NUM_MATCH_8821C(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8821C)) +#define BIT_GET_RXPKT_NUM_MATCH_8821C(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8821C) & \ + BIT_MASK_RXPKT_NUM_MATCH_8821C) +#define BIT_SET_RXPKT_NUM_MATCH_8821C(x, v) \ + (BIT_CLEAR_RXPKT_NUM_MATCH_8821C(x) | BIT_RXPKT_NUM_MATCH_8821C(v)) #define BIT_SHIFT_MIGRATE_TIMER_8821C 0 #define BIT_MASK_MIGRATE_TIMER_8821C 0xffff -#define BIT_MIGRATE_TIMER_8821C(x) (((x) & BIT_MASK_MIGRATE_TIMER_8821C) << BIT_SHIFT_MIGRATE_TIMER_8821C) -#define BIT_GET_MIGRATE_TIMER_8821C(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8821C) & BIT_MASK_MIGRATE_TIMER_8821C) - - +#define BIT_MIGRATE_TIMER_8821C(x) \ + (((x) & BIT_MASK_MIGRATE_TIMER_8821C) << BIT_SHIFT_MIGRATE_TIMER_8821C) +#define BITS_MIGRATE_TIMER_8821C \ + (BIT_MASK_MIGRATE_TIMER_8821C << BIT_SHIFT_MIGRATE_TIMER_8821C) +#define BIT_CLEAR_MIGRATE_TIMER_8821C(x) ((x) & (~BITS_MIGRATE_TIMER_8821C)) +#define BIT_GET_MIGRATE_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_MIGRATE_TIMER_8821C) & BIT_MASK_MIGRATE_TIMER_8821C) +#define BIT_SET_MIGRATE_TIMER_8821C(x, v) \ + (BIT_CLEAR_MIGRATE_TIMER_8821C(x) | BIT_MIGRATE_TIMER_8821C(v)) /* 2 REG_BCNQ_TXBD_DESA_8821C */ #define BIT_SHIFT_BCNQ_TXBD_DESA_8821C 0 #define BIT_MASK_BCNQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_BCNQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8821C) << BIT_SHIFT_BCNQ_TXBD_DESA_8821C) -#define BIT_GET_BCNQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8821C) & BIT_MASK_BCNQ_TXBD_DESA_8821C) - - +#define BIT_BCNQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_BCNQ_TXBD_DESA_8821C) \ + << BIT_SHIFT_BCNQ_TXBD_DESA_8821C) +#define BITS_BCNQ_TXBD_DESA_8821C \ + (BIT_MASK_BCNQ_TXBD_DESA_8821C << BIT_SHIFT_BCNQ_TXBD_DESA_8821C) +#define BIT_CLEAR_BCNQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8821C)) +#define BIT_GET_BCNQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8821C) & \ + BIT_MASK_BCNQ_TXBD_DESA_8821C) +#define BIT_SET_BCNQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_BCNQ_TXBD_DESA_8821C(x) | BIT_BCNQ_TXBD_DESA_8821C(v)) /* 2 REG_MGQ_TXBD_DESA_8821C */ #define BIT_SHIFT_MGQ_TXBD_DESA_8821C 0 #define BIT_MASK_MGQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_MGQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8821C) << BIT_SHIFT_MGQ_TXBD_DESA_8821C) -#define BIT_GET_MGQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8821C) & BIT_MASK_MGQ_TXBD_DESA_8821C) - - +#define BIT_MGQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_MGQ_TXBD_DESA_8821C) << BIT_SHIFT_MGQ_TXBD_DESA_8821C) +#define BITS_MGQ_TXBD_DESA_8821C \ + (BIT_MASK_MGQ_TXBD_DESA_8821C << BIT_SHIFT_MGQ_TXBD_DESA_8821C) +#define BIT_CLEAR_MGQ_TXBD_DESA_8821C(x) ((x) & (~BITS_MGQ_TXBD_DESA_8821C)) +#define BIT_GET_MGQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8821C) & BIT_MASK_MGQ_TXBD_DESA_8821C) +#define BIT_SET_MGQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_MGQ_TXBD_DESA_8821C(x) | BIT_MGQ_TXBD_DESA_8821C(v)) /* 2 REG_VOQ_TXBD_DESA_8821C */ #define BIT_SHIFT_VOQ_TXBD_DESA_8821C 0 #define BIT_MASK_VOQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_VOQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8821C) << BIT_SHIFT_VOQ_TXBD_DESA_8821C) -#define BIT_GET_VOQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8821C) & BIT_MASK_VOQ_TXBD_DESA_8821C) - - +#define BIT_VOQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_VOQ_TXBD_DESA_8821C) << BIT_SHIFT_VOQ_TXBD_DESA_8821C) +#define BITS_VOQ_TXBD_DESA_8821C \ + (BIT_MASK_VOQ_TXBD_DESA_8821C << BIT_SHIFT_VOQ_TXBD_DESA_8821C) +#define BIT_CLEAR_VOQ_TXBD_DESA_8821C(x) ((x) & (~BITS_VOQ_TXBD_DESA_8821C)) +#define BIT_GET_VOQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8821C) & BIT_MASK_VOQ_TXBD_DESA_8821C) +#define BIT_SET_VOQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_VOQ_TXBD_DESA_8821C(x) | BIT_VOQ_TXBD_DESA_8821C(v)) /* 2 REG_VIQ_TXBD_DESA_8821C */ #define BIT_SHIFT_VIQ_TXBD_DESA_8821C 0 #define BIT_MASK_VIQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_VIQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8821C) << BIT_SHIFT_VIQ_TXBD_DESA_8821C) -#define BIT_GET_VIQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8821C) & BIT_MASK_VIQ_TXBD_DESA_8821C) - - +#define BIT_VIQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_VIQ_TXBD_DESA_8821C) << BIT_SHIFT_VIQ_TXBD_DESA_8821C) +#define BITS_VIQ_TXBD_DESA_8821C \ + (BIT_MASK_VIQ_TXBD_DESA_8821C << BIT_SHIFT_VIQ_TXBD_DESA_8821C) +#define BIT_CLEAR_VIQ_TXBD_DESA_8821C(x) ((x) & (~BITS_VIQ_TXBD_DESA_8821C)) +#define BIT_GET_VIQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8821C) & BIT_MASK_VIQ_TXBD_DESA_8821C) +#define BIT_SET_VIQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_VIQ_TXBD_DESA_8821C(x) | BIT_VIQ_TXBD_DESA_8821C(v)) /* 2 REG_BEQ_TXBD_DESA_8821C */ #define BIT_SHIFT_BEQ_TXBD_DESA_8821C 0 #define BIT_MASK_BEQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_BEQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8821C) << BIT_SHIFT_BEQ_TXBD_DESA_8821C) -#define BIT_GET_BEQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8821C) & BIT_MASK_BEQ_TXBD_DESA_8821C) - - +#define BIT_BEQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_BEQ_TXBD_DESA_8821C) << BIT_SHIFT_BEQ_TXBD_DESA_8821C) +#define BITS_BEQ_TXBD_DESA_8821C \ + (BIT_MASK_BEQ_TXBD_DESA_8821C << BIT_SHIFT_BEQ_TXBD_DESA_8821C) +#define BIT_CLEAR_BEQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BEQ_TXBD_DESA_8821C)) +#define BIT_GET_BEQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8821C) & BIT_MASK_BEQ_TXBD_DESA_8821C) +#define BIT_SET_BEQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_BEQ_TXBD_DESA_8821C(x) | BIT_BEQ_TXBD_DESA_8821C(v)) /* 2 REG_BKQ_TXBD_DESA_8821C */ #define BIT_SHIFT_BKQ_TXBD_DESA_8821C 0 #define BIT_MASK_BKQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_BKQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8821C) << BIT_SHIFT_BKQ_TXBD_DESA_8821C) -#define BIT_GET_BKQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8821C) & BIT_MASK_BKQ_TXBD_DESA_8821C) - - +#define BIT_BKQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_BKQ_TXBD_DESA_8821C) << BIT_SHIFT_BKQ_TXBD_DESA_8821C) +#define BITS_BKQ_TXBD_DESA_8821C \ + (BIT_MASK_BKQ_TXBD_DESA_8821C << BIT_SHIFT_BKQ_TXBD_DESA_8821C) +#define BIT_CLEAR_BKQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BKQ_TXBD_DESA_8821C)) +#define BIT_GET_BKQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8821C) & BIT_MASK_BKQ_TXBD_DESA_8821C) +#define BIT_SET_BKQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_BKQ_TXBD_DESA_8821C(x) | BIT_BKQ_TXBD_DESA_8821C(v)) /* 2 REG_RXQ_RXBD_DESA_8821C */ #define BIT_SHIFT_RXQ_RXBD_DESA_8821C 0 #define BIT_MASK_RXQ_RXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_RXQ_RXBD_DESA_8821C(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8821C) << BIT_SHIFT_RXQ_RXBD_DESA_8821C) -#define BIT_GET_RXQ_RXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8821C) & BIT_MASK_RXQ_RXBD_DESA_8821C) - - +#define BIT_RXQ_RXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_RXQ_RXBD_DESA_8821C) << BIT_SHIFT_RXQ_RXBD_DESA_8821C) +#define BITS_RXQ_RXBD_DESA_8821C \ + (BIT_MASK_RXQ_RXBD_DESA_8821C << BIT_SHIFT_RXQ_RXBD_DESA_8821C) +#define BIT_CLEAR_RXQ_RXBD_DESA_8821C(x) ((x) & (~BITS_RXQ_RXBD_DESA_8821C)) +#define BIT_GET_RXQ_RXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8821C) & BIT_MASK_RXQ_RXBD_DESA_8821C) +#define BIT_SET_RXQ_RXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_RXQ_RXBD_DESA_8821C(x) | BIT_RXQ_RXBD_DESA_8821C(v)) /* 2 REG_HI0Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI0Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI0Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI0Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8821C) << BIT_SHIFT_HI0Q_TXBD_DESA_8821C) -#define BIT_GET_HI0Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8821C) & BIT_MASK_HI0Q_TXBD_DESA_8821C) - - +#define BIT_HI0Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_8821C) +#define BITS_HI0Q_TXBD_DESA_8821C \ + (BIT_MASK_HI0Q_TXBD_DESA_8821C << BIT_SHIFT_HI0Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI0Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8821C)) +#define BIT_GET_HI0Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI0Q_TXBD_DESA_8821C) +#define BIT_SET_HI0Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_8821C(x) | BIT_HI0Q_TXBD_DESA_8821C(v)) /* 2 REG_HI1Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI1Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI1Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI1Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8821C) << BIT_SHIFT_HI1Q_TXBD_DESA_8821C) -#define BIT_GET_HI1Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8821C) & BIT_MASK_HI1Q_TXBD_DESA_8821C) - - +#define BIT_HI1Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_8821C) +#define BITS_HI1Q_TXBD_DESA_8821C \ + (BIT_MASK_HI1Q_TXBD_DESA_8821C << BIT_SHIFT_HI1Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI1Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8821C)) +#define BIT_GET_HI1Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI1Q_TXBD_DESA_8821C) +#define BIT_SET_HI1Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_8821C(x) | BIT_HI1Q_TXBD_DESA_8821C(v)) /* 2 REG_HI2Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI2Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI2Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI2Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8821C) << BIT_SHIFT_HI2Q_TXBD_DESA_8821C) -#define BIT_GET_HI2Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8821C) & BIT_MASK_HI2Q_TXBD_DESA_8821C) - - +#define BIT_HI2Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_8821C) +#define BITS_HI2Q_TXBD_DESA_8821C \ + (BIT_MASK_HI2Q_TXBD_DESA_8821C << BIT_SHIFT_HI2Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI2Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8821C)) +#define BIT_GET_HI2Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI2Q_TXBD_DESA_8821C) +#define BIT_SET_HI2Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_8821C(x) | BIT_HI2Q_TXBD_DESA_8821C(v)) /* 2 REG_HI3Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI3Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI3Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI3Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8821C) << BIT_SHIFT_HI3Q_TXBD_DESA_8821C) -#define BIT_GET_HI3Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8821C) & BIT_MASK_HI3Q_TXBD_DESA_8821C) - - +#define BIT_HI3Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_8821C) +#define BITS_HI3Q_TXBD_DESA_8821C \ + (BIT_MASK_HI3Q_TXBD_DESA_8821C << BIT_SHIFT_HI3Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI3Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8821C)) +#define BIT_GET_HI3Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI3Q_TXBD_DESA_8821C) +#define BIT_SET_HI3Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_8821C(x) | BIT_HI3Q_TXBD_DESA_8821C(v)) /* 2 REG_HI4Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI4Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI4Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI4Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8821C) << BIT_SHIFT_HI4Q_TXBD_DESA_8821C) -#define BIT_GET_HI4Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8821C) & BIT_MASK_HI4Q_TXBD_DESA_8821C) - - +#define BIT_HI4Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_8821C) +#define BITS_HI4Q_TXBD_DESA_8821C \ + (BIT_MASK_HI4Q_TXBD_DESA_8821C << BIT_SHIFT_HI4Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI4Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8821C)) +#define BIT_GET_HI4Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI4Q_TXBD_DESA_8821C) +#define BIT_SET_HI4Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_8821C(x) | BIT_HI4Q_TXBD_DESA_8821C(v)) /* 2 REG_HI5Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI5Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI5Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI5Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8821C) << BIT_SHIFT_HI5Q_TXBD_DESA_8821C) -#define BIT_GET_HI5Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8821C) & BIT_MASK_HI5Q_TXBD_DESA_8821C) - - +#define BIT_HI5Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_8821C) +#define BITS_HI5Q_TXBD_DESA_8821C \ + (BIT_MASK_HI5Q_TXBD_DESA_8821C << BIT_SHIFT_HI5Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI5Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8821C)) +#define BIT_GET_HI5Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI5Q_TXBD_DESA_8821C) +#define BIT_SET_HI5Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_8821C(x) | BIT_HI5Q_TXBD_DESA_8821C(v)) /* 2 REG_HI6Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI6Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI6Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI6Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8821C) << BIT_SHIFT_HI6Q_TXBD_DESA_8821C) -#define BIT_GET_HI6Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8821C) & BIT_MASK_HI6Q_TXBD_DESA_8821C) - - +#define BIT_HI6Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_8821C) +#define BITS_HI6Q_TXBD_DESA_8821C \ + (BIT_MASK_HI6Q_TXBD_DESA_8821C << BIT_SHIFT_HI6Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI6Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8821C)) +#define BIT_GET_HI6Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI6Q_TXBD_DESA_8821C) +#define BIT_SET_HI6Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_8821C(x) | BIT_HI6Q_TXBD_DESA_8821C(v)) /* 2 REG_HI7Q_TXBD_DESA_8821C */ #define BIT_SHIFT_HI7Q_TXBD_DESA_8821C 0 #define BIT_MASK_HI7Q_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_HI7Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8821C) << BIT_SHIFT_HI7Q_TXBD_DESA_8821C) -#define BIT_GET_HI7Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8821C) & BIT_MASK_HI7Q_TXBD_DESA_8821C) - - +#define BIT_HI7Q_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_8821C) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_8821C) +#define BITS_HI7Q_TXBD_DESA_8821C \ + (BIT_MASK_HI7Q_TXBD_DESA_8821C << BIT_SHIFT_HI7Q_TXBD_DESA_8821C) +#define BIT_CLEAR_HI7Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8821C)) +#define BIT_GET_HI7Q_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8821C) & \ + BIT_MASK_HI7Q_TXBD_DESA_8821C) +#define BIT_SET_HI7Q_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_8821C(x) | BIT_HI7Q_TXBD_DESA_8821C(v)) /* 2 REG_MGQ_TXBD_NUM_8821C */ #define BIT_PCIE_MGQ_FLAG_8821C BIT(14) #define BIT_SHIFT_MGQ_DESC_MODE_8821C 12 #define BIT_MASK_MGQ_DESC_MODE_8821C 0x3 -#define BIT_MGQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8821C) << BIT_SHIFT_MGQ_DESC_MODE_8821C) -#define BIT_GET_MGQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8821C) & BIT_MASK_MGQ_DESC_MODE_8821C) - - +#define BIT_MGQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_MGQ_DESC_MODE_8821C) << BIT_SHIFT_MGQ_DESC_MODE_8821C) +#define BITS_MGQ_DESC_MODE_8821C \ + (BIT_MASK_MGQ_DESC_MODE_8821C << BIT_SHIFT_MGQ_DESC_MODE_8821C) +#define BIT_CLEAR_MGQ_DESC_MODE_8821C(x) ((x) & (~BITS_MGQ_DESC_MODE_8821C)) +#define BIT_GET_MGQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8821C) & BIT_MASK_MGQ_DESC_MODE_8821C) +#define BIT_SET_MGQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_MGQ_DESC_MODE_8821C(x) | BIT_MGQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_MGQ_DESC_NUM_8821C 0 #define BIT_MASK_MGQ_DESC_NUM_8821C 0xfff -#define BIT_MGQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8821C) << BIT_SHIFT_MGQ_DESC_NUM_8821C) -#define BIT_GET_MGQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8821C) & BIT_MASK_MGQ_DESC_NUM_8821C) - - +#define BIT_MGQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_MGQ_DESC_NUM_8821C) << BIT_SHIFT_MGQ_DESC_NUM_8821C) +#define BITS_MGQ_DESC_NUM_8821C \ + (BIT_MASK_MGQ_DESC_NUM_8821C << BIT_SHIFT_MGQ_DESC_NUM_8821C) +#define BIT_CLEAR_MGQ_DESC_NUM_8821C(x) ((x) & (~BITS_MGQ_DESC_NUM_8821C)) +#define BIT_GET_MGQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8821C) & BIT_MASK_MGQ_DESC_NUM_8821C) +#define BIT_SET_MGQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_MGQ_DESC_NUM_8821C(x) | BIT_MGQ_DESC_NUM_8821C(v)) /* 2 REG_RX_RXBD_NUM_8821C */ #define BIT_SYS_32_64_8821C BIT(15) #define BIT_SHIFT_BCNQ_DESC_MODE_8821C 13 #define BIT_MASK_BCNQ_DESC_MODE_8821C 0x3 -#define BIT_BCNQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8821C) << BIT_SHIFT_BCNQ_DESC_MODE_8821C) -#define BIT_GET_BCNQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8821C) & BIT_MASK_BCNQ_DESC_MODE_8821C) - +#define BIT_BCNQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_BCNQ_DESC_MODE_8821C) \ + << BIT_SHIFT_BCNQ_DESC_MODE_8821C) +#define BITS_BCNQ_DESC_MODE_8821C \ + (BIT_MASK_BCNQ_DESC_MODE_8821C << BIT_SHIFT_BCNQ_DESC_MODE_8821C) +#define BIT_CLEAR_BCNQ_DESC_MODE_8821C(x) ((x) & (~BITS_BCNQ_DESC_MODE_8821C)) +#define BIT_GET_BCNQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8821C) & \ + BIT_MASK_BCNQ_DESC_MODE_8821C) +#define BIT_SET_BCNQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_BCNQ_DESC_MODE_8821C(x) | BIT_BCNQ_DESC_MODE_8821C(v)) #define BIT_PCIE_BCNQ_FLAG_8821C BIT(12) #define BIT_SHIFT_RXQ_DESC_NUM_8821C 0 #define BIT_MASK_RXQ_DESC_NUM_8821C 0xfff -#define BIT_RXQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8821C) << BIT_SHIFT_RXQ_DESC_NUM_8821C) -#define BIT_GET_RXQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8821C) & BIT_MASK_RXQ_DESC_NUM_8821C) - - +#define BIT_RXQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_RXQ_DESC_NUM_8821C) << BIT_SHIFT_RXQ_DESC_NUM_8821C) +#define BITS_RXQ_DESC_NUM_8821C \ + (BIT_MASK_RXQ_DESC_NUM_8821C << BIT_SHIFT_RXQ_DESC_NUM_8821C) +#define BIT_CLEAR_RXQ_DESC_NUM_8821C(x) ((x) & (~BITS_RXQ_DESC_NUM_8821C)) +#define BIT_GET_RXQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8821C) & BIT_MASK_RXQ_DESC_NUM_8821C) +#define BIT_SET_RXQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_RXQ_DESC_NUM_8821C(x) | BIT_RXQ_DESC_NUM_8821C(v)) /* 2 REG_VOQ_TXBD_NUM_8821C */ #define BIT_PCIE_VOQ_FLAG_8821C BIT(14) #define BIT_SHIFT_VOQ_DESC_MODE_8821C 12 #define BIT_MASK_VOQ_DESC_MODE_8821C 0x3 -#define BIT_VOQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8821C) << BIT_SHIFT_VOQ_DESC_MODE_8821C) -#define BIT_GET_VOQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8821C) & BIT_MASK_VOQ_DESC_MODE_8821C) - - +#define BIT_VOQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_VOQ_DESC_MODE_8821C) << BIT_SHIFT_VOQ_DESC_MODE_8821C) +#define BITS_VOQ_DESC_MODE_8821C \ + (BIT_MASK_VOQ_DESC_MODE_8821C << BIT_SHIFT_VOQ_DESC_MODE_8821C) +#define BIT_CLEAR_VOQ_DESC_MODE_8821C(x) ((x) & (~BITS_VOQ_DESC_MODE_8821C)) +#define BIT_GET_VOQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8821C) & BIT_MASK_VOQ_DESC_MODE_8821C) +#define BIT_SET_VOQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_VOQ_DESC_MODE_8821C(x) | BIT_VOQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_VOQ_DESC_NUM_8821C 0 #define BIT_MASK_VOQ_DESC_NUM_8821C 0xfff -#define BIT_VOQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8821C) << BIT_SHIFT_VOQ_DESC_NUM_8821C) -#define BIT_GET_VOQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8821C) & BIT_MASK_VOQ_DESC_NUM_8821C) - - +#define BIT_VOQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_VOQ_DESC_NUM_8821C) << BIT_SHIFT_VOQ_DESC_NUM_8821C) +#define BITS_VOQ_DESC_NUM_8821C \ + (BIT_MASK_VOQ_DESC_NUM_8821C << BIT_SHIFT_VOQ_DESC_NUM_8821C) +#define BIT_CLEAR_VOQ_DESC_NUM_8821C(x) ((x) & (~BITS_VOQ_DESC_NUM_8821C)) +#define BIT_GET_VOQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8821C) & BIT_MASK_VOQ_DESC_NUM_8821C) +#define BIT_SET_VOQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_VOQ_DESC_NUM_8821C(x) | BIT_VOQ_DESC_NUM_8821C(v)) /* 2 REG_VIQ_TXBD_NUM_8821C */ #define BIT_PCIE_VIQ_FLAG_8821C BIT(14) #define BIT_SHIFT_VIQ_DESC_MODE_8821C 12 #define BIT_MASK_VIQ_DESC_MODE_8821C 0x3 -#define BIT_VIQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8821C) << BIT_SHIFT_VIQ_DESC_MODE_8821C) -#define BIT_GET_VIQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8821C) & BIT_MASK_VIQ_DESC_MODE_8821C) - - +#define BIT_VIQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_VIQ_DESC_MODE_8821C) << BIT_SHIFT_VIQ_DESC_MODE_8821C) +#define BITS_VIQ_DESC_MODE_8821C \ + (BIT_MASK_VIQ_DESC_MODE_8821C << BIT_SHIFT_VIQ_DESC_MODE_8821C) +#define BIT_CLEAR_VIQ_DESC_MODE_8821C(x) ((x) & (~BITS_VIQ_DESC_MODE_8821C)) +#define BIT_GET_VIQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8821C) & BIT_MASK_VIQ_DESC_MODE_8821C) +#define BIT_SET_VIQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_VIQ_DESC_MODE_8821C(x) | BIT_VIQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_VIQ_DESC_NUM_8821C 0 #define BIT_MASK_VIQ_DESC_NUM_8821C 0xfff -#define BIT_VIQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8821C) << BIT_SHIFT_VIQ_DESC_NUM_8821C) -#define BIT_GET_VIQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8821C) & BIT_MASK_VIQ_DESC_NUM_8821C) - - +#define BIT_VIQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_VIQ_DESC_NUM_8821C) << BIT_SHIFT_VIQ_DESC_NUM_8821C) +#define BITS_VIQ_DESC_NUM_8821C \ + (BIT_MASK_VIQ_DESC_NUM_8821C << BIT_SHIFT_VIQ_DESC_NUM_8821C) +#define BIT_CLEAR_VIQ_DESC_NUM_8821C(x) ((x) & (~BITS_VIQ_DESC_NUM_8821C)) +#define BIT_GET_VIQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8821C) & BIT_MASK_VIQ_DESC_NUM_8821C) +#define BIT_SET_VIQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_VIQ_DESC_NUM_8821C(x) | BIT_VIQ_DESC_NUM_8821C(v)) /* 2 REG_BEQ_TXBD_NUM_8821C */ #define BIT_PCIE_BEQ_FLAG_8821C BIT(14) #define BIT_SHIFT_BEQ_DESC_MODE_8821C 12 #define BIT_MASK_BEQ_DESC_MODE_8821C 0x3 -#define BIT_BEQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8821C) << BIT_SHIFT_BEQ_DESC_MODE_8821C) -#define BIT_GET_BEQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8821C) & BIT_MASK_BEQ_DESC_MODE_8821C) - - +#define BIT_BEQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_BEQ_DESC_MODE_8821C) << BIT_SHIFT_BEQ_DESC_MODE_8821C) +#define BITS_BEQ_DESC_MODE_8821C \ + (BIT_MASK_BEQ_DESC_MODE_8821C << BIT_SHIFT_BEQ_DESC_MODE_8821C) +#define BIT_CLEAR_BEQ_DESC_MODE_8821C(x) ((x) & (~BITS_BEQ_DESC_MODE_8821C)) +#define BIT_GET_BEQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8821C) & BIT_MASK_BEQ_DESC_MODE_8821C) +#define BIT_SET_BEQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_BEQ_DESC_MODE_8821C(x) | BIT_BEQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_BEQ_DESC_NUM_8821C 0 #define BIT_MASK_BEQ_DESC_NUM_8821C 0xfff -#define BIT_BEQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8821C) << BIT_SHIFT_BEQ_DESC_NUM_8821C) -#define BIT_GET_BEQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8821C) & BIT_MASK_BEQ_DESC_NUM_8821C) - - +#define BIT_BEQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_BEQ_DESC_NUM_8821C) << BIT_SHIFT_BEQ_DESC_NUM_8821C) +#define BITS_BEQ_DESC_NUM_8821C \ + (BIT_MASK_BEQ_DESC_NUM_8821C << BIT_SHIFT_BEQ_DESC_NUM_8821C) +#define BIT_CLEAR_BEQ_DESC_NUM_8821C(x) ((x) & (~BITS_BEQ_DESC_NUM_8821C)) +#define BIT_GET_BEQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8821C) & BIT_MASK_BEQ_DESC_NUM_8821C) +#define BIT_SET_BEQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_BEQ_DESC_NUM_8821C(x) | BIT_BEQ_DESC_NUM_8821C(v)) /* 2 REG_BKQ_TXBD_NUM_8821C */ #define BIT_PCIE_BKQ_FLAG_8821C BIT(14) #define BIT_SHIFT_BKQ_DESC_MODE_8821C 12 #define BIT_MASK_BKQ_DESC_MODE_8821C 0x3 -#define BIT_BKQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8821C) << BIT_SHIFT_BKQ_DESC_MODE_8821C) -#define BIT_GET_BKQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8821C) & BIT_MASK_BKQ_DESC_MODE_8821C) - - +#define BIT_BKQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_BKQ_DESC_MODE_8821C) << BIT_SHIFT_BKQ_DESC_MODE_8821C) +#define BITS_BKQ_DESC_MODE_8821C \ + (BIT_MASK_BKQ_DESC_MODE_8821C << BIT_SHIFT_BKQ_DESC_MODE_8821C) +#define BIT_CLEAR_BKQ_DESC_MODE_8821C(x) ((x) & (~BITS_BKQ_DESC_MODE_8821C)) +#define BIT_GET_BKQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8821C) & BIT_MASK_BKQ_DESC_MODE_8821C) +#define BIT_SET_BKQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_BKQ_DESC_MODE_8821C(x) | BIT_BKQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_BKQ_DESC_NUM_8821C 0 #define BIT_MASK_BKQ_DESC_NUM_8821C 0xfff -#define BIT_BKQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8821C) << BIT_SHIFT_BKQ_DESC_NUM_8821C) -#define BIT_GET_BKQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8821C) & BIT_MASK_BKQ_DESC_NUM_8821C) - - +#define BIT_BKQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_BKQ_DESC_NUM_8821C) << BIT_SHIFT_BKQ_DESC_NUM_8821C) +#define BITS_BKQ_DESC_NUM_8821C \ + (BIT_MASK_BKQ_DESC_NUM_8821C << BIT_SHIFT_BKQ_DESC_NUM_8821C) +#define BIT_CLEAR_BKQ_DESC_NUM_8821C(x) ((x) & (~BITS_BKQ_DESC_NUM_8821C)) +#define BIT_GET_BKQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8821C) & BIT_MASK_BKQ_DESC_NUM_8821C) +#define BIT_SET_BKQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_BKQ_DESC_NUM_8821C(x) | BIT_BKQ_DESC_NUM_8821C(v)) /* 2 REG_HI0Q_TXBD_NUM_8821C */ #define BIT_HI0Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI0Q_DESC_MODE_8821C 12 #define BIT_MASK_HI0Q_DESC_MODE_8821C 0x3 -#define BIT_HI0Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8821C) << BIT_SHIFT_HI0Q_DESC_MODE_8821C) -#define BIT_GET_HI0Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8821C) & BIT_MASK_HI0Q_DESC_MODE_8821C) - - +#define BIT_HI0Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI0Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI0Q_DESC_MODE_8821C) +#define BITS_HI0Q_DESC_MODE_8821C \ + (BIT_MASK_HI0Q_DESC_MODE_8821C << BIT_SHIFT_HI0Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI0Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI0Q_DESC_MODE_8821C)) +#define BIT_GET_HI0Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8821C) & \ + BIT_MASK_HI0Q_DESC_MODE_8821C) +#define BIT_SET_HI0Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI0Q_DESC_MODE_8821C(x) | BIT_HI0Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI0Q_DESC_NUM_8821C 0 #define BIT_MASK_HI0Q_DESC_NUM_8821C 0xfff -#define BIT_HI0Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8821C) << BIT_SHIFT_HI0Q_DESC_NUM_8821C) -#define BIT_GET_HI0Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8821C) & BIT_MASK_HI0Q_DESC_NUM_8821C) - - +#define BIT_HI0Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI0Q_DESC_NUM_8821C) << BIT_SHIFT_HI0Q_DESC_NUM_8821C) +#define BITS_HI0Q_DESC_NUM_8821C \ + (BIT_MASK_HI0Q_DESC_NUM_8821C << BIT_SHIFT_HI0Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI0Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI0Q_DESC_NUM_8821C)) +#define BIT_GET_HI0Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8821C) & BIT_MASK_HI0Q_DESC_NUM_8821C) +#define BIT_SET_HI0Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI0Q_DESC_NUM_8821C(x) | BIT_HI0Q_DESC_NUM_8821C(v)) /* 2 REG_HI1Q_TXBD_NUM_8821C */ #define BIT_HI1Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI1Q_DESC_MODE_8821C 12 #define BIT_MASK_HI1Q_DESC_MODE_8821C 0x3 -#define BIT_HI1Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8821C) << BIT_SHIFT_HI1Q_DESC_MODE_8821C) -#define BIT_GET_HI1Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8821C) & BIT_MASK_HI1Q_DESC_MODE_8821C) - - +#define BIT_HI1Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI1Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI1Q_DESC_MODE_8821C) +#define BITS_HI1Q_DESC_MODE_8821C \ + (BIT_MASK_HI1Q_DESC_MODE_8821C << BIT_SHIFT_HI1Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI1Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI1Q_DESC_MODE_8821C)) +#define BIT_GET_HI1Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8821C) & \ + BIT_MASK_HI1Q_DESC_MODE_8821C) +#define BIT_SET_HI1Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI1Q_DESC_MODE_8821C(x) | BIT_HI1Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI1Q_DESC_NUM_8821C 0 #define BIT_MASK_HI1Q_DESC_NUM_8821C 0xfff -#define BIT_HI1Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8821C) << BIT_SHIFT_HI1Q_DESC_NUM_8821C) -#define BIT_GET_HI1Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8821C) & BIT_MASK_HI1Q_DESC_NUM_8821C) - - +#define BIT_HI1Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI1Q_DESC_NUM_8821C) << BIT_SHIFT_HI1Q_DESC_NUM_8821C) +#define BITS_HI1Q_DESC_NUM_8821C \ + (BIT_MASK_HI1Q_DESC_NUM_8821C << BIT_SHIFT_HI1Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI1Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI1Q_DESC_NUM_8821C)) +#define BIT_GET_HI1Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8821C) & BIT_MASK_HI1Q_DESC_NUM_8821C) +#define BIT_SET_HI1Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI1Q_DESC_NUM_8821C(x) | BIT_HI1Q_DESC_NUM_8821C(v)) /* 2 REG_HI2Q_TXBD_NUM_8821C */ #define BIT_HI2Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI2Q_DESC_MODE_8821C 12 #define BIT_MASK_HI2Q_DESC_MODE_8821C 0x3 -#define BIT_HI2Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8821C) << BIT_SHIFT_HI2Q_DESC_MODE_8821C) -#define BIT_GET_HI2Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8821C) & BIT_MASK_HI2Q_DESC_MODE_8821C) - - +#define BIT_HI2Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI2Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI2Q_DESC_MODE_8821C) +#define BITS_HI2Q_DESC_MODE_8821C \ + (BIT_MASK_HI2Q_DESC_MODE_8821C << BIT_SHIFT_HI2Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI2Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI2Q_DESC_MODE_8821C)) +#define BIT_GET_HI2Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8821C) & \ + BIT_MASK_HI2Q_DESC_MODE_8821C) +#define BIT_SET_HI2Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI2Q_DESC_MODE_8821C(x) | BIT_HI2Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI2Q_DESC_NUM_8821C 0 #define BIT_MASK_HI2Q_DESC_NUM_8821C 0xfff -#define BIT_HI2Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8821C) << BIT_SHIFT_HI2Q_DESC_NUM_8821C) -#define BIT_GET_HI2Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8821C) & BIT_MASK_HI2Q_DESC_NUM_8821C) - - +#define BIT_HI2Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI2Q_DESC_NUM_8821C) << BIT_SHIFT_HI2Q_DESC_NUM_8821C) +#define BITS_HI2Q_DESC_NUM_8821C \ + (BIT_MASK_HI2Q_DESC_NUM_8821C << BIT_SHIFT_HI2Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI2Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI2Q_DESC_NUM_8821C)) +#define BIT_GET_HI2Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8821C) & BIT_MASK_HI2Q_DESC_NUM_8821C) +#define BIT_SET_HI2Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI2Q_DESC_NUM_8821C(x) | BIT_HI2Q_DESC_NUM_8821C(v)) /* 2 REG_HI3Q_TXBD_NUM_8821C */ #define BIT_HI3Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI3Q_DESC_MODE_8821C 12 #define BIT_MASK_HI3Q_DESC_MODE_8821C 0x3 -#define BIT_HI3Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8821C) << BIT_SHIFT_HI3Q_DESC_MODE_8821C) -#define BIT_GET_HI3Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8821C) & BIT_MASK_HI3Q_DESC_MODE_8821C) - - +#define BIT_HI3Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI3Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI3Q_DESC_MODE_8821C) +#define BITS_HI3Q_DESC_MODE_8821C \ + (BIT_MASK_HI3Q_DESC_MODE_8821C << BIT_SHIFT_HI3Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI3Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI3Q_DESC_MODE_8821C)) +#define BIT_GET_HI3Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8821C) & \ + BIT_MASK_HI3Q_DESC_MODE_8821C) +#define BIT_SET_HI3Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI3Q_DESC_MODE_8821C(x) | BIT_HI3Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI3Q_DESC_NUM_8821C 0 #define BIT_MASK_HI3Q_DESC_NUM_8821C 0xfff -#define BIT_HI3Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8821C) << BIT_SHIFT_HI3Q_DESC_NUM_8821C) -#define BIT_GET_HI3Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8821C) & BIT_MASK_HI3Q_DESC_NUM_8821C) - - +#define BIT_HI3Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI3Q_DESC_NUM_8821C) << BIT_SHIFT_HI3Q_DESC_NUM_8821C) +#define BITS_HI3Q_DESC_NUM_8821C \ + (BIT_MASK_HI3Q_DESC_NUM_8821C << BIT_SHIFT_HI3Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI3Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI3Q_DESC_NUM_8821C)) +#define BIT_GET_HI3Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8821C) & BIT_MASK_HI3Q_DESC_NUM_8821C) +#define BIT_SET_HI3Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI3Q_DESC_NUM_8821C(x) | BIT_HI3Q_DESC_NUM_8821C(v)) /* 2 REG_HI4Q_TXBD_NUM_8821C */ #define BIT_HI4Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI4Q_DESC_MODE_8821C 12 #define BIT_MASK_HI4Q_DESC_MODE_8821C 0x3 -#define BIT_HI4Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8821C) << BIT_SHIFT_HI4Q_DESC_MODE_8821C) -#define BIT_GET_HI4Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8821C) & BIT_MASK_HI4Q_DESC_MODE_8821C) - - +#define BIT_HI4Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI4Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI4Q_DESC_MODE_8821C) +#define BITS_HI4Q_DESC_MODE_8821C \ + (BIT_MASK_HI4Q_DESC_MODE_8821C << BIT_SHIFT_HI4Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI4Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI4Q_DESC_MODE_8821C)) +#define BIT_GET_HI4Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8821C) & \ + BIT_MASK_HI4Q_DESC_MODE_8821C) +#define BIT_SET_HI4Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI4Q_DESC_MODE_8821C(x) | BIT_HI4Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI4Q_DESC_NUM_8821C 0 #define BIT_MASK_HI4Q_DESC_NUM_8821C 0xfff -#define BIT_HI4Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8821C) << BIT_SHIFT_HI4Q_DESC_NUM_8821C) -#define BIT_GET_HI4Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8821C) & BIT_MASK_HI4Q_DESC_NUM_8821C) - - +#define BIT_HI4Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI4Q_DESC_NUM_8821C) << BIT_SHIFT_HI4Q_DESC_NUM_8821C) +#define BITS_HI4Q_DESC_NUM_8821C \ + (BIT_MASK_HI4Q_DESC_NUM_8821C << BIT_SHIFT_HI4Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI4Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI4Q_DESC_NUM_8821C)) +#define BIT_GET_HI4Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8821C) & BIT_MASK_HI4Q_DESC_NUM_8821C) +#define BIT_SET_HI4Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI4Q_DESC_NUM_8821C(x) | BIT_HI4Q_DESC_NUM_8821C(v)) /* 2 REG_HI5Q_TXBD_NUM_8821C */ #define BIT_HI5Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI5Q_DESC_MODE_8821C 12 #define BIT_MASK_HI5Q_DESC_MODE_8821C 0x3 -#define BIT_HI5Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8821C) << BIT_SHIFT_HI5Q_DESC_MODE_8821C) -#define BIT_GET_HI5Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8821C) & BIT_MASK_HI5Q_DESC_MODE_8821C) - - +#define BIT_HI5Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI5Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI5Q_DESC_MODE_8821C) +#define BITS_HI5Q_DESC_MODE_8821C \ + (BIT_MASK_HI5Q_DESC_MODE_8821C << BIT_SHIFT_HI5Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI5Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI5Q_DESC_MODE_8821C)) +#define BIT_GET_HI5Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8821C) & \ + BIT_MASK_HI5Q_DESC_MODE_8821C) +#define BIT_SET_HI5Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI5Q_DESC_MODE_8821C(x) | BIT_HI5Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI5Q_DESC_NUM_8821C 0 #define BIT_MASK_HI5Q_DESC_NUM_8821C 0xfff -#define BIT_HI5Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8821C) << BIT_SHIFT_HI5Q_DESC_NUM_8821C) -#define BIT_GET_HI5Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8821C) & BIT_MASK_HI5Q_DESC_NUM_8821C) - - +#define BIT_HI5Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI5Q_DESC_NUM_8821C) << BIT_SHIFT_HI5Q_DESC_NUM_8821C) +#define BITS_HI5Q_DESC_NUM_8821C \ + (BIT_MASK_HI5Q_DESC_NUM_8821C << BIT_SHIFT_HI5Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI5Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI5Q_DESC_NUM_8821C)) +#define BIT_GET_HI5Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8821C) & BIT_MASK_HI5Q_DESC_NUM_8821C) +#define BIT_SET_HI5Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI5Q_DESC_NUM_8821C(x) | BIT_HI5Q_DESC_NUM_8821C(v)) /* 2 REG_HI6Q_TXBD_NUM_8821C */ #define BIT_HI6Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI6Q_DESC_MODE_8821C 12 #define BIT_MASK_HI6Q_DESC_MODE_8821C 0x3 -#define BIT_HI6Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8821C) << BIT_SHIFT_HI6Q_DESC_MODE_8821C) -#define BIT_GET_HI6Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8821C) & BIT_MASK_HI6Q_DESC_MODE_8821C) - - +#define BIT_HI6Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI6Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI6Q_DESC_MODE_8821C) +#define BITS_HI6Q_DESC_MODE_8821C \ + (BIT_MASK_HI6Q_DESC_MODE_8821C << BIT_SHIFT_HI6Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI6Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI6Q_DESC_MODE_8821C)) +#define BIT_GET_HI6Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8821C) & \ + BIT_MASK_HI6Q_DESC_MODE_8821C) +#define BIT_SET_HI6Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI6Q_DESC_MODE_8821C(x) | BIT_HI6Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI6Q_DESC_NUM_8821C 0 #define BIT_MASK_HI6Q_DESC_NUM_8821C 0xfff -#define BIT_HI6Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8821C) << BIT_SHIFT_HI6Q_DESC_NUM_8821C) -#define BIT_GET_HI6Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8821C) & BIT_MASK_HI6Q_DESC_NUM_8821C) - - +#define BIT_HI6Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI6Q_DESC_NUM_8821C) << BIT_SHIFT_HI6Q_DESC_NUM_8821C) +#define BITS_HI6Q_DESC_NUM_8821C \ + (BIT_MASK_HI6Q_DESC_NUM_8821C << BIT_SHIFT_HI6Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI6Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI6Q_DESC_NUM_8821C)) +#define BIT_GET_HI6Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8821C) & BIT_MASK_HI6Q_DESC_NUM_8821C) +#define BIT_SET_HI6Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI6Q_DESC_NUM_8821C(x) | BIT_HI6Q_DESC_NUM_8821C(v)) /* 2 REG_HI7Q_TXBD_NUM_8821C */ #define BIT_HI7Q_FLAG_8821C BIT(14) #define BIT_SHIFT_HI7Q_DESC_MODE_8821C 12 #define BIT_MASK_HI7Q_DESC_MODE_8821C 0x3 -#define BIT_HI7Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8821C) << BIT_SHIFT_HI7Q_DESC_MODE_8821C) -#define BIT_GET_HI7Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8821C) & BIT_MASK_HI7Q_DESC_MODE_8821C) - - +#define BIT_HI7Q_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_HI7Q_DESC_MODE_8821C) \ + << BIT_SHIFT_HI7Q_DESC_MODE_8821C) +#define BITS_HI7Q_DESC_MODE_8821C \ + (BIT_MASK_HI7Q_DESC_MODE_8821C << BIT_SHIFT_HI7Q_DESC_MODE_8821C) +#define BIT_CLEAR_HI7Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI7Q_DESC_MODE_8821C)) +#define BIT_GET_HI7Q_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8821C) & \ + BIT_MASK_HI7Q_DESC_MODE_8821C) +#define BIT_SET_HI7Q_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_HI7Q_DESC_MODE_8821C(x) | BIT_HI7Q_DESC_MODE_8821C(v)) #define BIT_SHIFT_HI7Q_DESC_NUM_8821C 0 #define BIT_MASK_HI7Q_DESC_NUM_8821C 0xfff -#define BIT_HI7Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8821C) << BIT_SHIFT_HI7Q_DESC_NUM_8821C) -#define BIT_GET_HI7Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8821C) & BIT_MASK_HI7Q_DESC_NUM_8821C) - - +#define BIT_HI7Q_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_HI7Q_DESC_NUM_8821C) << BIT_SHIFT_HI7Q_DESC_NUM_8821C) +#define BITS_HI7Q_DESC_NUM_8821C \ + (BIT_MASK_HI7Q_DESC_NUM_8821C << BIT_SHIFT_HI7Q_DESC_NUM_8821C) +#define BIT_CLEAR_HI7Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI7Q_DESC_NUM_8821C)) +#define BIT_GET_HI7Q_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8821C) & BIT_MASK_HI7Q_DESC_NUM_8821C) +#define BIT_SET_HI7Q_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_HI7Q_DESC_NUM_8821C(x) | BIT_HI7Q_DESC_NUM_8821C(v)) /* 2 REG_TSFTIMER_HCI_8821C */ #define BIT_SHIFT_TSFT2_HCI_8821C 16 #define BIT_MASK_TSFT2_HCI_8821C 0xffff -#define BIT_TSFT2_HCI_8821C(x) (((x) & BIT_MASK_TSFT2_HCI_8821C) << BIT_SHIFT_TSFT2_HCI_8821C) -#define BIT_GET_TSFT2_HCI_8821C(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8821C) & BIT_MASK_TSFT2_HCI_8821C) - - +#define BIT_TSFT2_HCI_8821C(x) \ + (((x) & BIT_MASK_TSFT2_HCI_8821C) << BIT_SHIFT_TSFT2_HCI_8821C) +#define BITS_TSFT2_HCI_8821C \ + (BIT_MASK_TSFT2_HCI_8821C << BIT_SHIFT_TSFT2_HCI_8821C) +#define BIT_CLEAR_TSFT2_HCI_8821C(x) ((x) & (~BITS_TSFT2_HCI_8821C)) +#define BIT_GET_TSFT2_HCI_8821C(x) \ + (((x) >> BIT_SHIFT_TSFT2_HCI_8821C) & BIT_MASK_TSFT2_HCI_8821C) +#define BIT_SET_TSFT2_HCI_8821C(x, v) \ + (BIT_CLEAR_TSFT2_HCI_8821C(x) | BIT_TSFT2_HCI_8821C(v)) #define BIT_SHIFT_TSFT1_HCI_8821C 0 #define BIT_MASK_TSFT1_HCI_8821C 0xffff -#define BIT_TSFT1_HCI_8821C(x) (((x) & BIT_MASK_TSFT1_HCI_8821C) << BIT_SHIFT_TSFT1_HCI_8821C) -#define BIT_GET_TSFT1_HCI_8821C(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8821C) & BIT_MASK_TSFT1_HCI_8821C) - - +#define BIT_TSFT1_HCI_8821C(x) \ + (((x) & BIT_MASK_TSFT1_HCI_8821C) << BIT_SHIFT_TSFT1_HCI_8821C) +#define BITS_TSFT1_HCI_8821C \ + (BIT_MASK_TSFT1_HCI_8821C << BIT_SHIFT_TSFT1_HCI_8821C) +#define BIT_CLEAR_TSFT1_HCI_8821C(x) ((x) & (~BITS_TSFT1_HCI_8821C)) +#define BIT_GET_TSFT1_HCI_8821C(x) \ + (((x) >> BIT_SHIFT_TSFT1_HCI_8821C) & BIT_MASK_TSFT1_HCI_8821C) +#define BIT_SET_TSFT1_HCI_8821C(x, v) \ + (BIT_CLEAR_TSFT1_HCI_8821C(x) | BIT_TSFT1_HCI_8821C(v)) /* 2 REG_BD_RWPTR_CLR_8821C */ #define BIT_CLR_HI7Q_HW_IDX_8821C BIT(29) @@ -4774,252 +7784,406 @@ #define BIT_SHIFT_VOQ_HW_IDX_8821C 16 #define BIT_MASK_VOQ_HW_IDX_8821C 0xfff -#define BIT_VOQ_HW_IDX_8821C(x) (((x) & BIT_MASK_VOQ_HW_IDX_8821C) << BIT_SHIFT_VOQ_HW_IDX_8821C) -#define BIT_GET_VOQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8821C) & BIT_MASK_VOQ_HW_IDX_8821C) - - +#define BIT_VOQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_VOQ_HW_IDX_8821C) << BIT_SHIFT_VOQ_HW_IDX_8821C) +#define BITS_VOQ_HW_IDX_8821C \ + (BIT_MASK_VOQ_HW_IDX_8821C << BIT_SHIFT_VOQ_HW_IDX_8821C) +#define BIT_CLEAR_VOQ_HW_IDX_8821C(x) ((x) & (~BITS_VOQ_HW_IDX_8821C)) +#define BIT_GET_VOQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_VOQ_HW_IDX_8821C) & BIT_MASK_VOQ_HW_IDX_8821C) +#define BIT_SET_VOQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_VOQ_HW_IDX_8821C(x) | BIT_VOQ_HW_IDX_8821C(v)) #define BIT_SHIFT_VOQ_HOST_IDX_8821C 0 #define BIT_MASK_VOQ_HOST_IDX_8821C 0xfff -#define BIT_VOQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8821C) << BIT_SHIFT_VOQ_HOST_IDX_8821C) -#define BIT_GET_VOQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8821C) & BIT_MASK_VOQ_HOST_IDX_8821C) - - +#define BIT_VOQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_VOQ_HOST_IDX_8821C) << BIT_SHIFT_VOQ_HOST_IDX_8821C) +#define BITS_VOQ_HOST_IDX_8821C \ + (BIT_MASK_VOQ_HOST_IDX_8821C << BIT_SHIFT_VOQ_HOST_IDX_8821C) +#define BIT_CLEAR_VOQ_HOST_IDX_8821C(x) ((x) & (~BITS_VOQ_HOST_IDX_8821C)) +#define BIT_GET_VOQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8821C) & BIT_MASK_VOQ_HOST_IDX_8821C) +#define BIT_SET_VOQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_VOQ_HOST_IDX_8821C(x) | BIT_VOQ_HOST_IDX_8821C(v)) /* 2 REG_VIQ_TXBD_IDX_8821C */ #define BIT_SHIFT_VIQ_HW_IDX_8821C 16 #define BIT_MASK_VIQ_HW_IDX_8821C 0xfff -#define BIT_VIQ_HW_IDX_8821C(x) (((x) & BIT_MASK_VIQ_HW_IDX_8821C) << BIT_SHIFT_VIQ_HW_IDX_8821C) -#define BIT_GET_VIQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8821C) & BIT_MASK_VIQ_HW_IDX_8821C) - - +#define BIT_VIQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_VIQ_HW_IDX_8821C) << BIT_SHIFT_VIQ_HW_IDX_8821C) +#define BITS_VIQ_HW_IDX_8821C \ + (BIT_MASK_VIQ_HW_IDX_8821C << BIT_SHIFT_VIQ_HW_IDX_8821C) +#define BIT_CLEAR_VIQ_HW_IDX_8821C(x) ((x) & (~BITS_VIQ_HW_IDX_8821C)) +#define BIT_GET_VIQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_VIQ_HW_IDX_8821C) & BIT_MASK_VIQ_HW_IDX_8821C) +#define BIT_SET_VIQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_VIQ_HW_IDX_8821C(x) | BIT_VIQ_HW_IDX_8821C(v)) #define BIT_SHIFT_VIQ_HOST_IDX_8821C 0 #define BIT_MASK_VIQ_HOST_IDX_8821C 0xfff -#define BIT_VIQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8821C) << BIT_SHIFT_VIQ_HOST_IDX_8821C) -#define BIT_GET_VIQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8821C) & BIT_MASK_VIQ_HOST_IDX_8821C) - - +#define BIT_VIQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_VIQ_HOST_IDX_8821C) << BIT_SHIFT_VIQ_HOST_IDX_8821C) +#define BITS_VIQ_HOST_IDX_8821C \ + (BIT_MASK_VIQ_HOST_IDX_8821C << BIT_SHIFT_VIQ_HOST_IDX_8821C) +#define BIT_CLEAR_VIQ_HOST_IDX_8821C(x) ((x) & (~BITS_VIQ_HOST_IDX_8821C)) +#define BIT_GET_VIQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8821C) & BIT_MASK_VIQ_HOST_IDX_8821C) +#define BIT_SET_VIQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_VIQ_HOST_IDX_8821C(x) | BIT_VIQ_HOST_IDX_8821C(v)) /* 2 REG_BEQ_TXBD_IDX_8821C */ #define BIT_SHIFT_BEQ_HW_IDX_8821C 16 #define BIT_MASK_BEQ_HW_IDX_8821C 0xfff -#define BIT_BEQ_HW_IDX_8821C(x) (((x) & BIT_MASK_BEQ_HW_IDX_8821C) << BIT_SHIFT_BEQ_HW_IDX_8821C) -#define BIT_GET_BEQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8821C) & BIT_MASK_BEQ_HW_IDX_8821C) - - +#define BIT_BEQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_BEQ_HW_IDX_8821C) << BIT_SHIFT_BEQ_HW_IDX_8821C) +#define BITS_BEQ_HW_IDX_8821C \ + (BIT_MASK_BEQ_HW_IDX_8821C << BIT_SHIFT_BEQ_HW_IDX_8821C) +#define BIT_CLEAR_BEQ_HW_IDX_8821C(x) ((x) & (~BITS_BEQ_HW_IDX_8821C)) +#define BIT_GET_BEQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_BEQ_HW_IDX_8821C) & BIT_MASK_BEQ_HW_IDX_8821C) +#define BIT_SET_BEQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_BEQ_HW_IDX_8821C(x) | BIT_BEQ_HW_IDX_8821C(v)) #define BIT_SHIFT_BEQ_HOST_IDX_8821C 0 #define BIT_MASK_BEQ_HOST_IDX_8821C 0xfff -#define BIT_BEQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8821C) << BIT_SHIFT_BEQ_HOST_IDX_8821C) -#define BIT_GET_BEQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8821C) & BIT_MASK_BEQ_HOST_IDX_8821C) - - +#define BIT_BEQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_BEQ_HOST_IDX_8821C) << BIT_SHIFT_BEQ_HOST_IDX_8821C) +#define BITS_BEQ_HOST_IDX_8821C \ + (BIT_MASK_BEQ_HOST_IDX_8821C << BIT_SHIFT_BEQ_HOST_IDX_8821C) +#define BIT_CLEAR_BEQ_HOST_IDX_8821C(x) ((x) & (~BITS_BEQ_HOST_IDX_8821C)) +#define BIT_GET_BEQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8821C) & BIT_MASK_BEQ_HOST_IDX_8821C) +#define BIT_SET_BEQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_BEQ_HOST_IDX_8821C(x) | BIT_BEQ_HOST_IDX_8821C(v)) /* 2 REG_BKQ_TXBD_IDX_8821C */ #define BIT_SHIFT_BKQ_HW_IDX_8821C 16 #define BIT_MASK_BKQ_HW_IDX_8821C 0xfff -#define BIT_BKQ_HW_IDX_8821C(x) (((x) & BIT_MASK_BKQ_HW_IDX_8821C) << BIT_SHIFT_BKQ_HW_IDX_8821C) -#define BIT_GET_BKQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8821C) & BIT_MASK_BKQ_HW_IDX_8821C) - - +#define BIT_BKQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_BKQ_HW_IDX_8821C) << BIT_SHIFT_BKQ_HW_IDX_8821C) +#define BITS_BKQ_HW_IDX_8821C \ + (BIT_MASK_BKQ_HW_IDX_8821C << BIT_SHIFT_BKQ_HW_IDX_8821C) +#define BIT_CLEAR_BKQ_HW_IDX_8821C(x) ((x) & (~BITS_BKQ_HW_IDX_8821C)) +#define BIT_GET_BKQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_BKQ_HW_IDX_8821C) & BIT_MASK_BKQ_HW_IDX_8821C) +#define BIT_SET_BKQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_BKQ_HW_IDX_8821C(x) | BIT_BKQ_HW_IDX_8821C(v)) #define BIT_SHIFT_BKQ_HOST_IDX_8821C 0 #define BIT_MASK_BKQ_HOST_IDX_8821C 0xfff -#define BIT_BKQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8821C) << BIT_SHIFT_BKQ_HOST_IDX_8821C) -#define BIT_GET_BKQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8821C) & BIT_MASK_BKQ_HOST_IDX_8821C) - - +#define BIT_BKQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_BKQ_HOST_IDX_8821C) << BIT_SHIFT_BKQ_HOST_IDX_8821C) +#define BITS_BKQ_HOST_IDX_8821C \ + (BIT_MASK_BKQ_HOST_IDX_8821C << BIT_SHIFT_BKQ_HOST_IDX_8821C) +#define BIT_CLEAR_BKQ_HOST_IDX_8821C(x) ((x) & (~BITS_BKQ_HOST_IDX_8821C)) +#define BIT_GET_BKQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8821C) & BIT_MASK_BKQ_HOST_IDX_8821C) +#define BIT_SET_BKQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_BKQ_HOST_IDX_8821C(x) | BIT_BKQ_HOST_IDX_8821C(v)) /* 2 REG_MGQ_TXBD_IDX_8821C */ #define BIT_SHIFT_MGQ_HW_IDX_8821C 16 #define BIT_MASK_MGQ_HW_IDX_8821C 0xfff -#define BIT_MGQ_HW_IDX_8821C(x) (((x) & BIT_MASK_MGQ_HW_IDX_8821C) << BIT_SHIFT_MGQ_HW_IDX_8821C) -#define BIT_GET_MGQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8821C) & BIT_MASK_MGQ_HW_IDX_8821C) - - +#define BIT_MGQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_MGQ_HW_IDX_8821C) << BIT_SHIFT_MGQ_HW_IDX_8821C) +#define BITS_MGQ_HW_IDX_8821C \ + (BIT_MASK_MGQ_HW_IDX_8821C << BIT_SHIFT_MGQ_HW_IDX_8821C) +#define BIT_CLEAR_MGQ_HW_IDX_8821C(x) ((x) & (~BITS_MGQ_HW_IDX_8821C)) +#define BIT_GET_MGQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_HW_IDX_8821C) & BIT_MASK_MGQ_HW_IDX_8821C) +#define BIT_SET_MGQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_MGQ_HW_IDX_8821C(x) | BIT_MGQ_HW_IDX_8821C(v)) #define BIT_SHIFT_MGQ_HOST_IDX_8821C 0 #define BIT_MASK_MGQ_HOST_IDX_8821C 0xfff -#define BIT_MGQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8821C) << BIT_SHIFT_MGQ_HOST_IDX_8821C) -#define BIT_GET_MGQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8821C) & BIT_MASK_MGQ_HOST_IDX_8821C) - - +#define BIT_MGQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_MGQ_HOST_IDX_8821C) << BIT_SHIFT_MGQ_HOST_IDX_8821C) +#define BITS_MGQ_HOST_IDX_8821C \ + (BIT_MASK_MGQ_HOST_IDX_8821C << BIT_SHIFT_MGQ_HOST_IDX_8821C) +#define BIT_CLEAR_MGQ_HOST_IDX_8821C(x) ((x) & (~BITS_MGQ_HOST_IDX_8821C)) +#define BIT_GET_MGQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8821C) & BIT_MASK_MGQ_HOST_IDX_8821C) +#define BIT_SET_MGQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_MGQ_HOST_IDX_8821C(x) | BIT_MGQ_HOST_IDX_8821C(v)) /* 2 REG_RXQ_RXBD_IDX_8821C */ #define BIT_SHIFT_RXQ_HW_IDX_8821C 16 #define BIT_MASK_RXQ_HW_IDX_8821C 0xfff -#define BIT_RXQ_HW_IDX_8821C(x) (((x) & BIT_MASK_RXQ_HW_IDX_8821C) << BIT_SHIFT_RXQ_HW_IDX_8821C) -#define BIT_GET_RXQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8821C) & BIT_MASK_RXQ_HW_IDX_8821C) - - +#define BIT_RXQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_RXQ_HW_IDX_8821C) << BIT_SHIFT_RXQ_HW_IDX_8821C) +#define BITS_RXQ_HW_IDX_8821C \ + (BIT_MASK_RXQ_HW_IDX_8821C << BIT_SHIFT_RXQ_HW_IDX_8821C) +#define BIT_CLEAR_RXQ_HW_IDX_8821C(x) ((x) & (~BITS_RXQ_HW_IDX_8821C)) +#define BIT_GET_RXQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RXQ_HW_IDX_8821C) & BIT_MASK_RXQ_HW_IDX_8821C) +#define BIT_SET_RXQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_RXQ_HW_IDX_8821C(x) | BIT_RXQ_HW_IDX_8821C(v)) #define BIT_SHIFT_RXQ_HOST_IDX_8821C 0 #define BIT_MASK_RXQ_HOST_IDX_8821C 0xfff -#define BIT_RXQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8821C) << BIT_SHIFT_RXQ_HOST_IDX_8821C) -#define BIT_GET_RXQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8821C) & BIT_MASK_RXQ_HOST_IDX_8821C) - - +#define BIT_RXQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_RXQ_HOST_IDX_8821C) << BIT_SHIFT_RXQ_HOST_IDX_8821C) +#define BITS_RXQ_HOST_IDX_8821C \ + (BIT_MASK_RXQ_HOST_IDX_8821C << BIT_SHIFT_RXQ_HOST_IDX_8821C) +#define BIT_CLEAR_RXQ_HOST_IDX_8821C(x) ((x) & (~BITS_RXQ_HOST_IDX_8821C)) +#define BIT_GET_RXQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8821C) & BIT_MASK_RXQ_HOST_IDX_8821C) +#define BIT_SET_RXQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_RXQ_HOST_IDX_8821C(x) | BIT_RXQ_HOST_IDX_8821C(v)) /* 2 REG_HI0Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI0Q_HW_IDX_8821C 16 #define BIT_MASK_HI0Q_HW_IDX_8821C 0xfff -#define BIT_HI0Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8821C) << BIT_SHIFT_HI0Q_HW_IDX_8821C) -#define BIT_GET_HI0Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8821C) & BIT_MASK_HI0Q_HW_IDX_8821C) - - +#define BIT_HI0Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI0Q_HW_IDX_8821C) << BIT_SHIFT_HI0Q_HW_IDX_8821C) +#define BITS_HI0Q_HW_IDX_8821C \ + (BIT_MASK_HI0Q_HW_IDX_8821C << BIT_SHIFT_HI0Q_HW_IDX_8821C) +#define BIT_CLEAR_HI0Q_HW_IDX_8821C(x) ((x) & (~BITS_HI0Q_HW_IDX_8821C)) +#define BIT_GET_HI0Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8821C) & BIT_MASK_HI0Q_HW_IDX_8821C) +#define BIT_SET_HI0Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI0Q_HW_IDX_8821C(x) | BIT_HI0Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI0Q_HOST_IDX_8821C 0 #define BIT_MASK_HI0Q_HOST_IDX_8821C 0xfff -#define BIT_HI0Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8821C) << BIT_SHIFT_HI0Q_HOST_IDX_8821C) -#define BIT_GET_HI0Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8821C) & BIT_MASK_HI0Q_HOST_IDX_8821C) - - +#define BIT_HI0Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI0Q_HOST_IDX_8821C) << BIT_SHIFT_HI0Q_HOST_IDX_8821C) +#define BITS_HI0Q_HOST_IDX_8821C \ + (BIT_MASK_HI0Q_HOST_IDX_8821C << BIT_SHIFT_HI0Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI0Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI0Q_HOST_IDX_8821C)) +#define BIT_GET_HI0Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8821C) & BIT_MASK_HI0Q_HOST_IDX_8821C) +#define BIT_SET_HI0Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI0Q_HOST_IDX_8821C(x) | BIT_HI0Q_HOST_IDX_8821C(v)) /* 2 REG_HI1Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI1Q_HW_IDX_8821C 16 #define BIT_MASK_HI1Q_HW_IDX_8821C 0xfff -#define BIT_HI1Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8821C) << BIT_SHIFT_HI1Q_HW_IDX_8821C) -#define BIT_GET_HI1Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8821C) & BIT_MASK_HI1Q_HW_IDX_8821C) - - +#define BIT_HI1Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI1Q_HW_IDX_8821C) << BIT_SHIFT_HI1Q_HW_IDX_8821C) +#define BITS_HI1Q_HW_IDX_8821C \ + (BIT_MASK_HI1Q_HW_IDX_8821C << BIT_SHIFT_HI1Q_HW_IDX_8821C) +#define BIT_CLEAR_HI1Q_HW_IDX_8821C(x) ((x) & (~BITS_HI1Q_HW_IDX_8821C)) +#define BIT_GET_HI1Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8821C) & BIT_MASK_HI1Q_HW_IDX_8821C) +#define BIT_SET_HI1Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI1Q_HW_IDX_8821C(x) | BIT_HI1Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI1Q_HOST_IDX_8821C 0 #define BIT_MASK_HI1Q_HOST_IDX_8821C 0xfff -#define BIT_HI1Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8821C) << BIT_SHIFT_HI1Q_HOST_IDX_8821C) -#define BIT_GET_HI1Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8821C) & BIT_MASK_HI1Q_HOST_IDX_8821C) - - +#define BIT_HI1Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI1Q_HOST_IDX_8821C) << BIT_SHIFT_HI1Q_HOST_IDX_8821C) +#define BITS_HI1Q_HOST_IDX_8821C \ + (BIT_MASK_HI1Q_HOST_IDX_8821C << BIT_SHIFT_HI1Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI1Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI1Q_HOST_IDX_8821C)) +#define BIT_GET_HI1Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8821C) & BIT_MASK_HI1Q_HOST_IDX_8821C) +#define BIT_SET_HI1Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI1Q_HOST_IDX_8821C(x) | BIT_HI1Q_HOST_IDX_8821C(v)) /* 2 REG_HI2Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI2Q_HW_IDX_8821C 16 #define BIT_MASK_HI2Q_HW_IDX_8821C 0xfff -#define BIT_HI2Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8821C) << BIT_SHIFT_HI2Q_HW_IDX_8821C) -#define BIT_GET_HI2Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8821C) & BIT_MASK_HI2Q_HW_IDX_8821C) - - +#define BIT_HI2Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI2Q_HW_IDX_8821C) << BIT_SHIFT_HI2Q_HW_IDX_8821C) +#define BITS_HI2Q_HW_IDX_8821C \ + (BIT_MASK_HI2Q_HW_IDX_8821C << BIT_SHIFT_HI2Q_HW_IDX_8821C) +#define BIT_CLEAR_HI2Q_HW_IDX_8821C(x) ((x) & (~BITS_HI2Q_HW_IDX_8821C)) +#define BIT_GET_HI2Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8821C) & BIT_MASK_HI2Q_HW_IDX_8821C) +#define BIT_SET_HI2Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI2Q_HW_IDX_8821C(x) | BIT_HI2Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI2Q_HOST_IDX_8821C 0 #define BIT_MASK_HI2Q_HOST_IDX_8821C 0xfff -#define BIT_HI2Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8821C) << BIT_SHIFT_HI2Q_HOST_IDX_8821C) -#define BIT_GET_HI2Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8821C) & BIT_MASK_HI2Q_HOST_IDX_8821C) - - +#define BIT_HI2Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI2Q_HOST_IDX_8821C) << BIT_SHIFT_HI2Q_HOST_IDX_8821C) +#define BITS_HI2Q_HOST_IDX_8821C \ + (BIT_MASK_HI2Q_HOST_IDX_8821C << BIT_SHIFT_HI2Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI2Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI2Q_HOST_IDX_8821C)) +#define BIT_GET_HI2Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8821C) & BIT_MASK_HI2Q_HOST_IDX_8821C) +#define BIT_SET_HI2Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI2Q_HOST_IDX_8821C(x) | BIT_HI2Q_HOST_IDX_8821C(v)) /* 2 REG_HI3Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI3Q_HW_IDX_8821C 16 #define BIT_MASK_HI3Q_HW_IDX_8821C 0xfff -#define BIT_HI3Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8821C) << BIT_SHIFT_HI3Q_HW_IDX_8821C) -#define BIT_GET_HI3Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8821C) & BIT_MASK_HI3Q_HW_IDX_8821C) - - +#define BIT_HI3Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI3Q_HW_IDX_8821C) << BIT_SHIFT_HI3Q_HW_IDX_8821C) +#define BITS_HI3Q_HW_IDX_8821C \ + (BIT_MASK_HI3Q_HW_IDX_8821C << BIT_SHIFT_HI3Q_HW_IDX_8821C) +#define BIT_CLEAR_HI3Q_HW_IDX_8821C(x) ((x) & (~BITS_HI3Q_HW_IDX_8821C)) +#define BIT_GET_HI3Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8821C) & BIT_MASK_HI3Q_HW_IDX_8821C) +#define BIT_SET_HI3Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI3Q_HW_IDX_8821C(x) | BIT_HI3Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI3Q_HOST_IDX_8821C 0 #define BIT_MASK_HI3Q_HOST_IDX_8821C 0xfff -#define BIT_HI3Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8821C) << BIT_SHIFT_HI3Q_HOST_IDX_8821C) -#define BIT_GET_HI3Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8821C) & BIT_MASK_HI3Q_HOST_IDX_8821C) - - +#define BIT_HI3Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI3Q_HOST_IDX_8821C) << BIT_SHIFT_HI3Q_HOST_IDX_8821C) +#define BITS_HI3Q_HOST_IDX_8821C \ + (BIT_MASK_HI3Q_HOST_IDX_8821C << BIT_SHIFT_HI3Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI3Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI3Q_HOST_IDX_8821C)) +#define BIT_GET_HI3Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8821C) & BIT_MASK_HI3Q_HOST_IDX_8821C) +#define BIT_SET_HI3Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI3Q_HOST_IDX_8821C(x) | BIT_HI3Q_HOST_IDX_8821C(v)) /* 2 REG_HI4Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI4Q_HW_IDX_8821C 16 #define BIT_MASK_HI4Q_HW_IDX_8821C 0xfff -#define BIT_HI4Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8821C) << BIT_SHIFT_HI4Q_HW_IDX_8821C) -#define BIT_GET_HI4Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8821C) & BIT_MASK_HI4Q_HW_IDX_8821C) - - +#define BIT_HI4Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI4Q_HW_IDX_8821C) << BIT_SHIFT_HI4Q_HW_IDX_8821C) +#define BITS_HI4Q_HW_IDX_8821C \ + (BIT_MASK_HI4Q_HW_IDX_8821C << BIT_SHIFT_HI4Q_HW_IDX_8821C) +#define BIT_CLEAR_HI4Q_HW_IDX_8821C(x) ((x) & (~BITS_HI4Q_HW_IDX_8821C)) +#define BIT_GET_HI4Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8821C) & BIT_MASK_HI4Q_HW_IDX_8821C) +#define BIT_SET_HI4Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI4Q_HW_IDX_8821C(x) | BIT_HI4Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI4Q_HOST_IDX_8821C 0 #define BIT_MASK_HI4Q_HOST_IDX_8821C 0xfff -#define BIT_HI4Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8821C) << BIT_SHIFT_HI4Q_HOST_IDX_8821C) -#define BIT_GET_HI4Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8821C) & BIT_MASK_HI4Q_HOST_IDX_8821C) - - +#define BIT_HI4Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI4Q_HOST_IDX_8821C) << BIT_SHIFT_HI4Q_HOST_IDX_8821C) +#define BITS_HI4Q_HOST_IDX_8821C \ + (BIT_MASK_HI4Q_HOST_IDX_8821C << BIT_SHIFT_HI4Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI4Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI4Q_HOST_IDX_8821C)) +#define BIT_GET_HI4Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8821C) & BIT_MASK_HI4Q_HOST_IDX_8821C) +#define BIT_SET_HI4Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI4Q_HOST_IDX_8821C(x) | BIT_HI4Q_HOST_IDX_8821C(v)) /* 2 REG_HI5Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI5Q_HW_IDX_8821C 16 #define BIT_MASK_HI5Q_HW_IDX_8821C 0xfff -#define BIT_HI5Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8821C) << BIT_SHIFT_HI5Q_HW_IDX_8821C) -#define BIT_GET_HI5Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8821C) & BIT_MASK_HI5Q_HW_IDX_8821C) - - +#define BIT_HI5Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI5Q_HW_IDX_8821C) << BIT_SHIFT_HI5Q_HW_IDX_8821C) +#define BITS_HI5Q_HW_IDX_8821C \ + (BIT_MASK_HI5Q_HW_IDX_8821C << BIT_SHIFT_HI5Q_HW_IDX_8821C) +#define BIT_CLEAR_HI5Q_HW_IDX_8821C(x) ((x) & (~BITS_HI5Q_HW_IDX_8821C)) +#define BIT_GET_HI5Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8821C) & BIT_MASK_HI5Q_HW_IDX_8821C) +#define BIT_SET_HI5Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI5Q_HW_IDX_8821C(x) | BIT_HI5Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI5Q_HOST_IDX_8821C 0 #define BIT_MASK_HI5Q_HOST_IDX_8821C 0xfff -#define BIT_HI5Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8821C) << BIT_SHIFT_HI5Q_HOST_IDX_8821C) -#define BIT_GET_HI5Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8821C) & BIT_MASK_HI5Q_HOST_IDX_8821C) - - +#define BIT_HI5Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI5Q_HOST_IDX_8821C) << BIT_SHIFT_HI5Q_HOST_IDX_8821C) +#define BITS_HI5Q_HOST_IDX_8821C \ + (BIT_MASK_HI5Q_HOST_IDX_8821C << BIT_SHIFT_HI5Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI5Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI5Q_HOST_IDX_8821C)) +#define BIT_GET_HI5Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8821C) & BIT_MASK_HI5Q_HOST_IDX_8821C) +#define BIT_SET_HI5Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI5Q_HOST_IDX_8821C(x) | BIT_HI5Q_HOST_IDX_8821C(v)) /* 2 REG_HI6Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI6Q_HW_IDX_8821C 16 #define BIT_MASK_HI6Q_HW_IDX_8821C 0xfff -#define BIT_HI6Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8821C) << BIT_SHIFT_HI6Q_HW_IDX_8821C) -#define BIT_GET_HI6Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8821C) & BIT_MASK_HI6Q_HW_IDX_8821C) - - +#define BIT_HI6Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI6Q_HW_IDX_8821C) << BIT_SHIFT_HI6Q_HW_IDX_8821C) +#define BITS_HI6Q_HW_IDX_8821C \ + (BIT_MASK_HI6Q_HW_IDX_8821C << BIT_SHIFT_HI6Q_HW_IDX_8821C) +#define BIT_CLEAR_HI6Q_HW_IDX_8821C(x) ((x) & (~BITS_HI6Q_HW_IDX_8821C)) +#define BIT_GET_HI6Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8821C) & BIT_MASK_HI6Q_HW_IDX_8821C) +#define BIT_SET_HI6Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI6Q_HW_IDX_8821C(x) | BIT_HI6Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI6Q_HOST_IDX_8821C 0 #define BIT_MASK_HI6Q_HOST_IDX_8821C 0xfff -#define BIT_HI6Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8821C) << BIT_SHIFT_HI6Q_HOST_IDX_8821C) -#define BIT_GET_HI6Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8821C) & BIT_MASK_HI6Q_HOST_IDX_8821C) - - +#define BIT_HI6Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI6Q_HOST_IDX_8821C) << BIT_SHIFT_HI6Q_HOST_IDX_8821C) +#define BITS_HI6Q_HOST_IDX_8821C \ + (BIT_MASK_HI6Q_HOST_IDX_8821C << BIT_SHIFT_HI6Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI6Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI6Q_HOST_IDX_8821C)) +#define BIT_GET_HI6Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8821C) & BIT_MASK_HI6Q_HOST_IDX_8821C) +#define BIT_SET_HI6Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI6Q_HOST_IDX_8821C(x) | BIT_HI6Q_HOST_IDX_8821C(v)) /* 2 REG_HI7Q_TXBD_IDX_8821C */ #define BIT_SHIFT_HI7Q_HW_IDX_8821C 16 #define BIT_MASK_HI7Q_HW_IDX_8821C 0xfff -#define BIT_HI7Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8821C) << BIT_SHIFT_HI7Q_HW_IDX_8821C) -#define BIT_GET_HI7Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8821C) & BIT_MASK_HI7Q_HW_IDX_8821C) - - +#define BIT_HI7Q_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_HI7Q_HW_IDX_8821C) << BIT_SHIFT_HI7Q_HW_IDX_8821C) +#define BITS_HI7Q_HW_IDX_8821C \ + (BIT_MASK_HI7Q_HW_IDX_8821C << BIT_SHIFT_HI7Q_HW_IDX_8821C) +#define BIT_CLEAR_HI7Q_HW_IDX_8821C(x) ((x) & (~BITS_HI7Q_HW_IDX_8821C)) +#define BIT_GET_HI7Q_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8821C) & BIT_MASK_HI7Q_HW_IDX_8821C) +#define BIT_SET_HI7Q_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_HI7Q_HW_IDX_8821C(x) | BIT_HI7Q_HW_IDX_8821C(v)) #define BIT_SHIFT_HI7Q_HOST_IDX_8821C 0 #define BIT_MASK_HI7Q_HOST_IDX_8821C 0xfff -#define BIT_HI7Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8821C) << BIT_SHIFT_HI7Q_HOST_IDX_8821C) -#define BIT_GET_HI7Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8821C) & BIT_MASK_HI7Q_HOST_IDX_8821C) - - +#define BIT_HI7Q_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_HI7Q_HOST_IDX_8821C) << BIT_SHIFT_HI7Q_HOST_IDX_8821C) +#define BITS_HI7Q_HOST_IDX_8821C \ + (BIT_MASK_HI7Q_HOST_IDX_8821C << BIT_SHIFT_HI7Q_HOST_IDX_8821C) +#define BIT_CLEAR_HI7Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI7Q_HOST_IDX_8821C)) +#define BIT_GET_HI7Q_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8821C) & BIT_MASK_HI7Q_HOST_IDX_8821C) +#define BIT_SET_HI7Q_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_HI7Q_HOST_IDX_8821C(x) | BIT_HI7Q_HOST_IDX_8821C(v)) /* 2 REG_DBG_SEL_V1_8821C */ #define BIT_SHIFT_DBG_SEL_8821C 0 #define BIT_MASK_DBG_SEL_8821C 0xff -#define BIT_DBG_SEL_8821C(x) (((x) & BIT_MASK_DBG_SEL_8821C) << BIT_SHIFT_DBG_SEL_8821C) -#define BIT_GET_DBG_SEL_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_8821C) & BIT_MASK_DBG_SEL_8821C) - - +#define BIT_DBG_SEL_8821C(x) \ + (((x) & BIT_MASK_DBG_SEL_8821C) << BIT_SHIFT_DBG_SEL_8821C) +#define BITS_DBG_SEL_8821C (BIT_MASK_DBG_SEL_8821C << BIT_SHIFT_DBG_SEL_8821C) +#define BIT_CLEAR_DBG_SEL_8821C(x) ((x) & (~BITS_DBG_SEL_8821C)) +#define BIT_GET_DBG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_8821C) & BIT_MASK_DBG_SEL_8821C) +#define BIT_SET_DBG_SEL_8821C(x, v) \ + (BIT_CLEAR_DBG_SEL_8821C(x) | BIT_DBG_SEL_8821C(v)) /* 2 REG_PCIE_HRPWM1_V1_8821C */ #define BIT_SHIFT_PCIE_HRPWM_8821C 0 #define BIT_MASK_PCIE_HRPWM_8821C 0xff -#define BIT_PCIE_HRPWM_8821C(x) (((x) & BIT_MASK_PCIE_HRPWM_8821C) << BIT_SHIFT_PCIE_HRPWM_8821C) -#define BIT_GET_PCIE_HRPWM_8821C(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8821C) & BIT_MASK_PCIE_HRPWM_8821C) - - +#define BIT_PCIE_HRPWM_8821C(x) \ + (((x) & BIT_MASK_PCIE_HRPWM_8821C) << BIT_SHIFT_PCIE_HRPWM_8821C) +#define BITS_PCIE_HRPWM_8821C \ + (BIT_MASK_PCIE_HRPWM_8821C << BIT_SHIFT_PCIE_HRPWM_8821C) +#define BIT_CLEAR_PCIE_HRPWM_8821C(x) ((x) & (~BITS_PCIE_HRPWM_8821C)) +#define BIT_GET_PCIE_HRPWM_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM_8821C) & BIT_MASK_PCIE_HRPWM_8821C) +#define BIT_SET_PCIE_HRPWM_8821C(x, v) \ + (BIT_CLEAR_PCIE_HRPWM_8821C(x) | BIT_PCIE_HRPWM_8821C(v)) /* 2 REG_PCIE_HCPWM1_V1_8821C */ #define BIT_SHIFT_PCIE_HCPWM_8821C 0 #define BIT_MASK_PCIE_HCPWM_8821C 0xff -#define BIT_PCIE_HCPWM_8821C(x) (((x) & BIT_MASK_PCIE_HCPWM_8821C) << BIT_SHIFT_PCIE_HCPWM_8821C) -#define BIT_GET_PCIE_HCPWM_8821C(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8821C) & BIT_MASK_PCIE_HCPWM_8821C) - - +#define BIT_PCIE_HCPWM_8821C(x) \ + (((x) & BIT_MASK_PCIE_HCPWM_8821C) << BIT_SHIFT_PCIE_HCPWM_8821C) +#define BITS_PCIE_HCPWM_8821C \ + (BIT_MASK_PCIE_HCPWM_8821C << BIT_SHIFT_PCIE_HCPWM_8821C) +#define BIT_CLEAR_PCIE_HCPWM_8821C(x) ((x) & (~BITS_PCIE_HCPWM_8821C)) +#define BIT_GET_PCIE_HCPWM_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM_8821C) & BIT_MASK_PCIE_HCPWM_8821C) +#define BIT_SET_PCIE_HCPWM_8821C(x, v) \ + (BIT_CLEAR_PCIE_HCPWM_8821C(x) | BIT_PCIE_HCPWM_8821C(v)) /* 2 REG_PCIE_CTRL2_8821C */ #define BIT_DIS_TXDMA_PRE_8821C BIT(7) @@ -5027,9 +8191,15 @@ #define BIT_SHIFT_HPS_CLKR_PCIE_8821C 4 #define BIT_MASK_HPS_CLKR_PCIE_8821C 0x3 -#define BIT_HPS_CLKR_PCIE_8821C(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8821C) << BIT_SHIFT_HPS_CLKR_PCIE_8821C) -#define BIT_GET_HPS_CLKR_PCIE_8821C(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8821C) & BIT_MASK_HPS_CLKR_PCIE_8821C) - +#define BIT_HPS_CLKR_PCIE_8821C(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE_8821C) << BIT_SHIFT_HPS_CLKR_PCIE_8821C) +#define BITS_HPS_CLKR_PCIE_8821C \ + (BIT_MASK_HPS_CLKR_PCIE_8821C << BIT_SHIFT_HPS_CLKR_PCIE_8821C) +#define BIT_CLEAR_HPS_CLKR_PCIE_8821C(x) ((x) & (~BITS_HPS_CLKR_PCIE_8821C)) +#define BIT_GET_HPS_CLKR_PCIE_8821C(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8821C) & BIT_MASK_HPS_CLKR_PCIE_8821C) +#define BIT_SET_HPS_CLKR_PCIE_8821C(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE_8821C(x) | BIT_HPS_CLKR_PCIE_8821C(v)) #define BIT_PCIE_INT_8821C BIT(3) #define BIT_TXFLAG_EXIT_L1_EN_8821C BIT(2) @@ -5040,55 +8210,88 @@ #define BIT_SHIFT_PCIE_HRPWM2_8821C 0 #define BIT_MASK_PCIE_HRPWM2_8821C 0xffff -#define BIT_PCIE_HRPWM2_8821C(x) (((x) & BIT_MASK_PCIE_HRPWM2_8821C) << BIT_SHIFT_PCIE_HRPWM2_8821C) -#define BIT_GET_PCIE_HRPWM2_8821C(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8821C) & BIT_MASK_PCIE_HRPWM2_8821C) - - +#define BIT_PCIE_HRPWM2_8821C(x) \ + (((x) & BIT_MASK_PCIE_HRPWM2_8821C) << BIT_SHIFT_PCIE_HRPWM2_8821C) +#define BITS_PCIE_HRPWM2_8821C \ + (BIT_MASK_PCIE_HRPWM2_8821C << BIT_SHIFT_PCIE_HRPWM2_8821C) +#define BIT_CLEAR_PCIE_HRPWM2_8821C(x) ((x) & (~BITS_PCIE_HRPWM2_8821C)) +#define BIT_GET_PCIE_HRPWM2_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM2_8821C) & BIT_MASK_PCIE_HRPWM2_8821C) +#define BIT_SET_PCIE_HRPWM2_8821C(x, v) \ + (BIT_CLEAR_PCIE_HRPWM2_8821C(x) | BIT_PCIE_HRPWM2_8821C(v)) /* 2 REG_PCIE_HCPWM2_V1_8821C */ #define BIT_SHIFT_PCIE_HCPWM2_8821C 0 #define BIT_MASK_PCIE_HCPWM2_8821C 0xffff -#define BIT_PCIE_HCPWM2_8821C(x) (((x) & BIT_MASK_PCIE_HCPWM2_8821C) << BIT_SHIFT_PCIE_HCPWM2_8821C) -#define BIT_GET_PCIE_HCPWM2_8821C(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8821C) & BIT_MASK_PCIE_HCPWM2_8821C) - - +#define BIT_PCIE_HCPWM2_8821C(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2_8821C) << BIT_SHIFT_PCIE_HCPWM2_8821C) +#define BITS_PCIE_HCPWM2_8821C \ + (BIT_MASK_PCIE_HCPWM2_8821C << BIT_SHIFT_PCIE_HCPWM2_8821C) +#define BIT_CLEAR_PCIE_HCPWM2_8821C(x) ((x) & (~BITS_PCIE_HCPWM2_8821C)) +#define BIT_GET_PCIE_HCPWM2_8821C(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2_8821C) & BIT_MASK_PCIE_HCPWM2_8821C) +#define BIT_SET_PCIE_HCPWM2_8821C(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2_8821C(x) | BIT_PCIE_HCPWM2_8821C(v)) /* 2 REG_PCIE_H2C_MSG_V1_8821C */ #define BIT_SHIFT_DRV2FW_INFO_8821C 0 #define BIT_MASK_DRV2FW_INFO_8821C 0xffffffffL -#define BIT_DRV2FW_INFO_8821C(x) (((x) & BIT_MASK_DRV2FW_INFO_8821C) << BIT_SHIFT_DRV2FW_INFO_8821C) -#define BIT_GET_DRV2FW_INFO_8821C(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8821C) & BIT_MASK_DRV2FW_INFO_8821C) - - +#define BIT_DRV2FW_INFO_8821C(x) \ + (((x) & BIT_MASK_DRV2FW_INFO_8821C) << BIT_SHIFT_DRV2FW_INFO_8821C) +#define BITS_DRV2FW_INFO_8821C \ + (BIT_MASK_DRV2FW_INFO_8821C << BIT_SHIFT_DRV2FW_INFO_8821C) +#define BIT_CLEAR_DRV2FW_INFO_8821C(x) ((x) & (~BITS_DRV2FW_INFO_8821C)) +#define BIT_GET_DRV2FW_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO_8821C) & BIT_MASK_DRV2FW_INFO_8821C) +#define BIT_SET_DRV2FW_INFO_8821C(x, v) \ + (BIT_CLEAR_DRV2FW_INFO_8821C(x) | BIT_DRV2FW_INFO_8821C(v)) /* 2 REG_PCIE_C2H_MSG_V1_8821C */ #define BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C 0 #define BIT_MASK_HCI_PCIE_C2H_MSG_8821C 0xffffffffL -#define BIT_HCI_PCIE_C2H_MSG_8821C(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C) << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) -#define BIT_GET_HCI_PCIE_C2H_MSG_8821C(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C) - - +#define BIT_HCI_PCIE_C2H_MSG_8821C(x) \ + (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C) \ + << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) +#define BITS_HCI_PCIE_C2H_MSG_8821C \ + (BIT_MASK_HCI_PCIE_C2H_MSG_8821C << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) +#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8821C(x) \ + ((x) & (~BITS_HCI_PCIE_C2H_MSG_8821C)) +#define BIT_GET_HCI_PCIE_C2H_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) & \ + BIT_MASK_HCI_PCIE_C2H_MSG_8821C) +#define BIT_SET_HCI_PCIE_C2H_MSG_8821C(x, v) \ + (BIT_CLEAR_HCI_PCIE_C2H_MSG_8821C(x) | BIT_HCI_PCIE_C2H_MSG_8821C(v)) /* 2 REG_DBI_WDATA_V1_8821C */ #define BIT_SHIFT_DBI_WDATA_8821C 0 #define BIT_MASK_DBI_WDATA_8821C 0xffffffffL -#define BIT_DBI_WDATA_8821C(x) (((x) & BIT_MASK_DBI_WDATA_8821C) << BIT_SHIFT_DBI_WDATA_8821C) -#define BIT_GET_DBI_WDATA_8821C(x) (((x) >> BIT_SHIFT_DBI_WDATA_8821C) & BIT_MASK_DBI_WDATA_8821C) - - +#define BIT_DBI_WDATA_8821C(x) \ + (((x) & BIT_MASK_DBI_WDATA_8821C) << BIT_SHIFT_DBI_WDATA_8821C) +#define BITS_DBI_WDATA_8821C \ + (BIT_MASK_DBI_WDATA_8821C << BIT_SHIFT_DBI_WDATA_8821C) +#define BIT_CLEAR_DBI_WDATA_8821C(x) ((x) & (~BITS_DBI_WDATA_8821C)) +#define BIT_GET_DBI_WDATA_8821C(x) \ + (((x) >> BIT_SHIFT_DBI_WDATA_8821C) & BIT_MASK_DBI_WDATA_8821C) +#define BIT_SET_DBI_WDATA_8821C(x, v) \ + (BIT_CLEAR_DBI_WDATA_8821C(x) | BIT_DBI_WDATA_8821C(v)) /* 2 REG_DBI_RDATA_V1_8821C */ #define BIT_SHIFT_DBI_RDATA_8821C 0 #define BIT_MASK_DBI_RDATA_8821C 0xffffffffL -#define BIT_DBI_RDATA_8821C(x) (((x) & BIT_MASK_DBI_RDATA_8821C) << BIT_SHIFT_DBI_RDATA_8821C) -#define BIT_GET_DBI_RDATA_8821C(x) (((x) >> BIT_SHIFT_DBI_RDATA_8821C) & BIT_MASK_DBI_RDATA_8821C) - - +#define BIT_DBI_RDATA_8821C(x) \ + (((x) & BIT_MASK_DBI_RDATA_8821C) << BIT_SHIFT_DBI_RDATA_8821C) +#define BITS_DBI_RDATA_8821C \ + (BIT_MASK_DBI_RDATA_8821C << BIT_SHIFT_DBI_RDATA_8821C) +#define BIT_CLEAR_DBI_RDATA_8821C(x) ((x) & (~BITS_DBI_RDATA_8821C)) +#define BIT_GET_DBI_RDATA_8821C(x) \ + (((x) >> BIT_SHIFT_DBI_RDATA_8821C) & BIT_MASK_DBI_RDATA_8821C) +#define BIT_SET_DBI_RDATA_8821C(x, v) \ + (BIT_CLEAR_DBI_RDATA_8821C(x) | BIT_DBI_RDATA_8821C(v)) /* 2 REG_DBI_FLAG_V1_8821C */ #define BIT_EN_STUCK_DBG_8821C BIT(26) @@ -5099,48 +8302,84 @@ #define BIT_SHIFT_DBI_WREN_8821C 12 #define BIT_MASK_DBI_WREN_8821C 0xf -#define BIT_DBI_WREN_8821C(x) (((x) & BIT_MASK_DBI_WREN_8821C) << BIT_SHIFT_DBI_WREN_8821C) -#define BIT_GET_DBI_WREN_8821C(x) (((x) >> BIT_SHIFT_DBI_WREN_8821C) & BIT_MASK_DBI_WREN_8821C) - - +#define BIT_DBI_WREN_8821C(x) \ + (((x) & BIT_MASK_DBI_WREN_8821C) << BIT_SHIFT_DBI_WREN_8821C) +#define BITS_DBI_WREN_8821C \ + (BIT_MASK_DBI_WREN_8821C << BIT_SHIFT_DBI_WREN_8821C) +#define BIT_CLEAR_DBI_WREN_8821C(x) ((x) & (~BITS_DBI_WREN_8821C)) +#define BIT_GET_DBI_WREN_8821C(x) \ + (((x) >> BIT_SHIFT_DBI_WREN_8821C) & BIT_MASK_DBI_WREN_8821C) +#define BIT_SET_DBI_WREN_8821C(x, v) \ + (BIT_CLEAR_DBI_WREN_8821C(x) | BIT_DBI_WREN_8821C(v)) #define BIT_SHIFT_DBI_ADDR_8821C 0 #define BIT_MASK_DBI_ADDR_8821C 0xfff -#define BIT_DBI_ADDR_8821C(x) (((x) & BIT_MASK_DBI_ADDR_8821C) << BIT_SHIFT_DBI_ADDR_8821C) -#define BIT_GET_DBI_ADDR_8821C(x) (((x) >> BIT_SHIFT_DBI_ADDR_8821C) & BIT_MASK_DBI_ADDR_8821C) - - +#define BIT_DBI_ADDR_8821C(x) \ + (((x) & BIT_MASK_DBI_ADDR_8821C) << BIT_SHIFT_DBI_ADDR_8821C) +#define BITS_DBI_ADDR_8821C \ + (BIT_MASK_DBI_ADDR_8821C << BIT_SHIFT_DBI_ADDR_8821C) +#define BIT_CLEAR_DBI_ADDR_8821C(x) ((x) & (~BITS_DBI_ADDR_8821C)) +#define BIT_GET_DBI_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_DBI_ADDR_8821C) & BIT_MASK_DBI_ADDR_8821C) +#define BIT_SET_DBI_ADDR_8821C(x, v) \ + (BIT_CLEAR_DBI_ADDR_8821C(x) | BIT_DBI_ADDR_8821C(v)) /* 2 REG_MDIO_V1_8821C */ #define BIT_SHIFT_MDIO_RDATA_8821C 16 #define BIT_MASK_MDIO_RDATA_8821C 0xffff -#define BIT_MDIO_RDATA_8821C(x) (((x) & BIT_MASK_MDIO_RDATA_8821C) << BIT_SHIFT_MDIO_RDATA_8821C) -#define BIT_GET_MDIO_RDATA_8821C(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8821C) & BIT_MASK_MDIO_RDATA_8821C) - - +#define BIT_MDIO_RDATA_8821C(x) \ + (((x) & BIT_MASK_MDIO_RDATA_8821C) << BIT_SHIFT_MDIO_RDATA_8821C) +#define BITS_MDIO_RDATA_8821C \ + (BIT_MASK_MDIO_RDATA_8821C << BIT_SHIFT_MDIO_RDATA_8821C) +#define BIT_CLEAR_MDIO_RDATA_8821C(x) ((x) & (~BITS_MDIO_RDATA_8821C)) +#define BIT_GET_MDIO_RDATA_8821C(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA_8821C) & BIT_MASK_MDIO_RDATA_8821C) +#define BIT_SET_MDIO_RDATA_8821C(x, v) \ + (BIT_CLEAR_MDIO_RDATA_8821C(x) | BIT_MDIO_RDATA_8821C(v)) #define BIT_SHIFT_MDIO_WDATA_8821C 0 #define BIT_MASK_MDIO_WDATA_8821C 0xffff -#define BIT_MDIO_WDATA_8821C(x) (((x) & BIT_MASK_MDIO_WDATA_8821C) << BIT_SHIFT_MDIO_WDATA_8821C) -#define BIT_GET_MDIO_WDATA_8821C(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8821C) & BIT_MASK_MDIO_WDATA_8821C) - - +#define BIT_MDIO_WDATA_8821C(x) \ + (((x) & BIT_MASK_MDIO_WDATA_8821C) << BIT_SHIFT_MDIO_WDATA_8821C) +#define BITS_MDIO_WDATA_8821C \ + (BIT_MASK_MDIO_WDATA_8821C << BIT_SHIFT_MDIO_WDATA_8821C) +#define BIT_CLEAR_MDIO_WDATA_8821C(x) ((x) & (~BITS_MDIO_WDATA_8821C)) +#define BIT_GET_MDIO_WDATA_8821C(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA_8821C) & BIT_MASK_MDIO_WDATA_8821C) +#define BIT_SET_MDIO_WDATA_8821C(x, v) \ + (BIT_CLEAR_MDIO_WDATA_8821C(x) | BIT_MDIO_WDATA_8821C(v)) /* 2 REG_PCIE_MIX_CFG_8821C */ #define BIT_SHIFT_MDIO_PHY_ADDR_8821C 24 #define BIT_MASK_MDIO_PHY_ADDR_8821C 0x1f -#define BIT_MDIO_PHY_ADDR_8821C(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8821C) << BIT_SHIFT_MDIO_PHY_ADDR_8821C) -#define BIT_GET_MDIO_PHY_ADDR_8821C(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8821C) & BIT_MASK_MDIO_PHY_ADDR_8821C) - - +#define BIT_MDIO_PHY_ADDR_8821C(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR_8821C) << BIT_SHIFT_MDIO_PHY_ADDR_8821C) +#define BITS_MDIO_PHY_ADDR_8821C \ + (BIT_MASK_MDIO_PHY_ADDR_8821C << BIT_SHIFT_MDIO_PHY_ADDR_8821C) +#define BIT_CLEAR_MDIO_PHY_ADDR_8821C(x) ((x) & (~BITS_MDIO_PHY_ADDR_8821C)) +#define BIT_GET_MDIO_PHY_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8821C) & BIT_MASK_MDIO_PHY_ADDR_8821C) +#define BIT_SET_MDIO_PHY_ADDR_8821C(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR_8821C(x) | BIT_MDIO_PHY_ADDR_8821C(v)) #define BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C 10 #define BIT_MASK_WATCH_DOG_RECORD_V1_8821C 0x3fff -#define BIT_WATCH_DOG_RECORD_V1_8821C(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) -#define BIT_GET_WATCH_DOG_RECORD_V1_8821C(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) - +#define BIT_WATCH_DOG_RECORD_V1_8821C(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) +#define BITS_WATCH_DOG_RECORD_V1_8821C \ + (BIT_MASK_WATCH_DOG_RECORD_V1_8821C \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8821C(x) \ + ((x) & (~BITS_WATCH_DOG_RECORD_V1_8821C)) +#define BIT_GET_WATCH_DOG_RECORD_V1_8821C(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) & \ + BIT_MASK_WATCH_DOG_RECORD_V1_8821C) +#define BIT_SET_WATCH_DOG_RECORD_V1_8821C(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1_8821C(x) | \ + BIT_WATCH_DOG_RECORD_V1_8821C(v)) #define BIT_R_IO_TIMEOUT_FLAG_V1_8821C BIT(9) #define BIT_EN_WATCH_DOG_8821C BIT(8) @@ -5150,34 +8389,66 @@ #define BIT_SHIFT_MDIO_REG_ADDR_V1_8821C 0 #define BIT_MASK_MDIO_REG_ADDR_V1_8821C 0x1f -#define BIT_MDIO_REG_ADDR_V1_8821C(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8821C) << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) -#define BIT_GET_MDIO_REG_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) & BIT_MASK_MDIO_REG_ADDR_V1_8821C) - - +#define BIT_MDIO_REG_ADDR_V1_8821C(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8821C) \ + << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) +#define BITS_MDIO_REG_ADDR_V1_8821C \ + (BIT_MASK_MDIO_REG_ADDR_V1_8821C << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) +#define BIT_CLEAR_MDIO_REG_ADDR_V1_8821C(x) \ + ((x) & (~BITS_MDIO_REG_ADDR_V1_8821C)) +#define BIT_GET_MDIO_REG_ADDR_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) & \ + BIT_MASK_MDIO_REG_ADDR_V1_8821C) +#define BIT_SET_MDIO_REG_ADDR_V1_8821C(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_V1_8821C(x) | BIT_MDIO_REG_ADDR_V1_8821C(v)) /* 2 REG_HCI_MIX_CFG_8821C */ #define BIT_HOST_GEN2_SUPPORT_8821C BIT(20) #define BIT_SHIFT_TXDMA_ERR_FLAG_8821C 16 #define BIT_MASK_TXDMA_ERR_FLAG_8821C 0xf -#define BIT_TXDMA_ERR_FLAG_8821C(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8821C) << BIT_SHIFT_TXDMA_ERR_FLAG_8821C) -#define BIT_GET_TXDMA_ERR_FLAG_8821C(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8821C) & BIT_MASK_TXDMA_ERR_FLAG_8821C) - - +#define BIT_TXDMA_ERR_FLAG_8821C(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_8821C) \ + << BIT_SHIFT_TXDMA_ERR_FLAG_8821C) +#define BITS_TXDMA_ERR_FLAG_8821C \ + (BIT_MASK_TXDMA_ERR_FLAG_8821C << BIT_SHIFT_TXDMA_ERR_FLAG_8821C) +#define BIT_CLEAR_TXDMA_ERR_FLAG_8821C(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8821C)) +#define BIT_GET_TXDMA_ERR_FLAG_8821C(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8821C) & \ + BIT_MASK_TXDMA_ERR_FLAG_8821C) +#define BIT_SET_TXDMA_ERR_FLAG_8821C(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_8821C(x) | BIT_TXDMA_ERR_FLAG_8821C(v)) #define BIT_SHIFT_EARLY_MODE_SEL_8821C 12 #define BIT_MASK_EARLY_MODE_SEL_8821C 0xf -#define BIT_EARLY_MODE_SEL_8821C(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8821C) << BIT_SHIFT_EARLY_MODE_SEL_8821C) -#define BIT_GET_EARLY_MODE_SEL_8821C(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8821C) & BIT_MASK_EARLY_MODE_SEL_8821C) - +#define BIT_EARLY_MODE_SEL_8821C(x) \ + (((x) & BIT_MASK_EARLY_MODE_SEL_8821C) \ + << BIT_SHIFT_EARLY_MODE_SEL_8821C) +#define BITS_EARLY_MODE_SEL_8821C \ + (BIT_MASK_EARLY_MODE_SEL_8821C << BIT_SHIFT_EARLY_MODE_SEL_8821C) +#define BIT_CLEAR_EARLY_MODE_SEL_8821C(x) ((x) & (~BITS_EARLY_MODE_SEL_8821C)) +#define BIT_GET_EARLY_MODE_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8821C) & \ + BIT_MASK_EARLY_MODE_SEL_8821C) +#define BIT_SET_EARLY_MODE_SEL_8821C(x, v) \ + (BIT_CLEAR_EARLY_MODE_SEL_8821C(x) | BIT_EARLY_MODE_SEL_8821C(v)) #define BIT_EPHY_RX50_EN_8821C BIT(11) #define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C 8 #define BIT_MASK_MSI_TIMEOUT_ID_V1_8821C 0x7 -#define BIT_MSI_TIMEOUT_ID_V1_8821C(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) -#define BIT_GET_MSI_TIMEOUT_ID_V1_8821C(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) - +#define BIT_MSI_TIMEOUT_ID_V1_8821C(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) \ + << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) +#define BITS_MSI_TIMEOUT_ID_V1_8821C \ + (BIT_MASK_MSI_TIMEOUT_ID_V1_8821C << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8821C(x) \ + ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8821C)) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) & \ + BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) +#define BIT_SET_MSI_TIMEOUT_ID_V1_8821C(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8821C(x) | BIT_MSI_TIMEOUT_ID_V1_8821C(v)) #define BIT_RADDR_RD_8821C BIT(7) #define BIT_EN_MUL_TAG_8821C BIT(6) @@ -5192,41 +8463,77 @@ #define BIT_SHIFT_STC_INT_FLAG_8821C 16 #define BIT_MASK_STC_INT_FLAG_8821C 0xff -#define BIT_STC_INT_FLAG_8821C(x) (((x) & BIT_MASK_STC_INT_FLAG_8821C) << BIT_SHIFT_STC_INT_FLAG_8821C) -#define BIT_GET_STC_INT_FLAG_8821C(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8821C) & BIT_MASK_STC_INT_FLAG_8821C) - - +#define BIT_STC_INT_FLAG_8821C(x) \ + (((x) & BIT_MASK_STC_INT_FLAG_8821C) << BIT_SHIFT_STC_INT_FLAG_8821C) +#define BITS_STC_INT_FLAG_8821C \ + (BIT_MASK_STC_INT_FLAG_8821C << BIT_SHIFT_STC_INT_FLAG_8821C) +#define BIT_CLEAR_STC_INT_FLAG_8821C(x) ((x) & (~BITS_STC_INT_FLAG_8821C)) +#define BIT_GET_STC_INT_FLAG_8821C(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG_8821C) & BIT_MASK_STC_INT_FLAG_8821C) +#define BIT_SET_STC_INT_FLAG_8821C(x, v) \ + (BIT_CLEAR_STC_INT_FLAG_8821C(x) | BIT_STC_INT_FLAG_8821C(v)) #define BIT_SHIFT_STC_INT_IDX_8821C 8 #define BIT_MASK_STC_INT_IDX_8821C 0x7 -#define BIT_STC_INT_IDX_8821C(x) (((x) & BIT_MASK_STC_INT_IDX_8821C) << BIT_SHIFT_STC_INT_IDX_8821C) -#define BIT_GET_STC_INT_IDX_8821C(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8821C) & BIT_MASK_STC_INT_IDX_8821C) - - +#define BIT_STC_INT_IDX_8821C(x) \ + (((x) & BIT_MASK_STC_INT_IDX_8821C) << BIT_SHIFT_STC_INT_IDX_8821C) +#define BITS_STC_INT_IDX_8821C \ + (BIT_MASK_STC_INT_IDX_8821C << BIT_SHIFT_STC_INT_IDX_8821C) +#define BIT_CLEAR_STC_INT_IDX_8821C(x) ((x) & (~BITS_STC_INT_IDX_8821C)) +#define BIT_GET_STC_INT_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX_8821C) & BIT_MASK_STC_INT_IDX_8821C) +#define BIT_SET_STC_INT_IDX_8821C(x, v) \ + (BIT_CLEAR_STC_INT_IDX_8821C(x) | BIT_STC_INT_IDX_8821C(v)) #define BIT_SHIFT_STC_INT_REALTIME_CS_8821C 0 #define BIT_MASK_STC_INT_REALTIME_CS_8821C 0x3f -#define BIT_STC_INT_REALTIME_CS_8821C(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8821C) << BIT_SHIFT_STC_INT_REALTIME_CS_8821C) -#define BIT_GET_STC_INT_REALTIME_CS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8821C) & BIT_MASK_STC_INT_REALTIME_CS_8821C) - - +#define BIT_STC_INT_REALTIME_CS_8821C(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS_8821C) \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8821C) +#define BITS_STC_INT_REALTIME_CS_8821C \ + (BIT_MASK_STC_INT_REALTIME_CS_8821C \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8821C) +#define BIT_CLEAR_STC_INT_REALTIME_CS_8821C(x) \ + ((x) & (~BITS_STC_INT_REALTIME_CS_8821C)) +#define BIT_GET_STC_INT_REALTIME_CS_8821C(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8821C) & \ + BIT_MASK_STC_INT_REALTIME_CS_8821C) +#define BIT_SET_STC_INT_REALTIME_CS_8821C(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS_8821C(x) | \ + BIT_STC_INT_REALTIME_CS_8821C(v)) /* 2 REG_ST_INT_CFG_8821C(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ #define BIT_STC_INT_GRP_EN_8821C BIT(31) #define BIT_SHIFT_STC_INT_EXPECT_LS_8821C 8 #define BIT_MASK_STC_INT_EXPECT_LS_8821C 0x3f -#define BIT_STC_INT_EXPECT_LS_8821C(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8821C) << BIT_SHIFT_STC_INT_EXPECT_LS_8821C) -#define BIT_GET_STC_INT_EXPECT_LS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8821C) & BIT_MASK_STC_INT_EXPECT_LS_8821C) - - +#define BIT_STC_INT_EXPECT_LS_8821C(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS_8821C) \ + << BIT_SHIFT_STC_INT_EXPECT_LS_8821C) +#define BITS_STC_INT_EXPECT_LS_8821C \ + (BIT_MASK_STC_INT_EXPECT_LS_8821C << BIT_SHIFT_STC_INT_EXPECT_LS_8821C) +#define BIT_CLEAR_STC_INT_EXPECT_LS_8821C(x) \ + ((x) & (~BITS_STC_INT_EXPECT_LS_8821C)) +#define BIT_GET_STC_INT_EXPECT_LS_8821C(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8821C) & \ + BIT_MASK_STC_INT_EXPECT_LS_8821C) +#define BIT_SET_STC_INT_EXPECT_LS_8821C(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS_8821C(x) | BIT_STC_INT_EXPECT_LS_8821C(v)) #define BIT_SHIFT_STC_INT_EXPECT_CS_8821C 0 #define BIT_MASK_STC_INT_EXPECT_CS_8821C 0x3f -#define BIT_STC_INT_EXPECT_CS_8821C(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8821C) << BIT_SHIFT_STC_INT_EXPECT_CS_8821C) -#define BIT_GET_STC_INT_EXPECT_CS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8821C) & BIT_MASK_STC_INT_EXPECT_CS_8821C) - - +#define BIT_STC_INT_EXPECT_CS_8821C(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS_8821C) \ + << BIT_SHIFT_STC_INT_EXPECT_CS_8821C) +#define BITS_STC_INT_EXPECT_CS_8821C \ + (BIT_MASK_STC_INT_EXPECT_CS_8821C << BIT_SHIFT_STC_INT_EXPECT_CS_8821C) +#define BIT_CLEAR_STC_INT_EXPECT_CS_8821C(x) \ + ((x) & (~BITS_STC_INT_EXPECT_CS_8821C)) +#define BIT_GET_STC_INT_EXPECT_CS_8821C(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8821C) & \ + BIT_MASK_STC_INT_EXPECT_CS_8821C) +#define BIT_SET_STC_INT_EXPECT_CS_8821C(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS_8821C(x) | BIT_STC_INT_EXPECT_CS_8821C(v)) /* 2 REG_CMU_DLY_CTRL_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */ #define BIT_CMU_DLY_EN_8821C BIT(31) @@ -5234,282 +8541,529 @@ #define BIT_SHIFT_CMU_DLY_PRE_DIV_8821C 0 #define BIT_MASK_CMU_DLY_PRE_DIV_8821C 0xff -#define BIT_CMU_DLY_PRE_DIV_8821C(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8821C) << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) -#define BIT_GET_CMU_DLY_PRE_DIV_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) & BIT_MASK_CMU_DLY_PRE_DIV_8821C) - - +#define BIT_CMU_DLY_PRE_DIV_8821C(x) \ + (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8821C) \ + << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) +#define BITS_CMU_DLY_PRE_DIV_8821C \ + (BIT_MASK_CMU_DLY_PRE_DIV_8821C << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) +#define BIT_CLEAR_CMU_DLY_PRE_DIV_8821C(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8821C)) +#define BIT_GET_CMU_DLY_PRE_DIV_8821C(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) & \ + BIT_MASK_CMU_DLY_PRE_DIV_8821C) +#define BIT_SET_CMU_DLY_PRE_DIV_8821C(x, v) \ + (BIT_CLEAR_CMU_DLY_PRE_DIV_8821C(x) | BIT_CMU_DLY_PRE_DIV_8821C(v)) /* 2 REG_CMU_DLY_CFG_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ #define BIT_SHIFT_CMU_DLY_LTR_A2I_8821C 24 #define BIT_MASK_CMU_DLY_LTR_A2I_8821C 0xff -#define BIT_CMU_DLY_LTR_A2I_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8821C) << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) -#define BIT_GET_CMU_DLY_LTR_A2I_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) & BIT_MASK_CMU_DLY_LTR_A2I_8821C) - - +#define BIT_CMU_DLY_LTR_A2I_8821C(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8821C) \ + << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) +#define BITS_CMU_DLY_LTR_A2I_8821C \ + (BIT_MASK_CMU_DLY_LTR_A2I_8821C << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) +#define BIT_CLEAR_CMU_DLY_LTR_A2I_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8821C)) +#define BIT_GET_CMU_DLY_LTR_A2I_8821C(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) & \ + BIT_MASK_CMU_DLY_LTR_A2I_8821C) +#define BIT_SET_CMU_DLY_LTR_A2I_8821C(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_A2I_8821C(x) | BIT_CMU_DLY_LTR_A2I_8821C(v)) #define BIT_SHIFT_CMU_DLY_LTR_I2A_8821C 16 #define BIT_MASK_CMU_DLY_LTR_I2A_8821C 0xff -#define BIT_CMU_DLY_LTR_I2A_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) -#define BIT_GET_CMU_DLY_LTR_I2A_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) - - +#define BIT_CMU_DLY_LTR_I2A_8821C(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) \ + << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) +#define BITS_CMU_DLY_LTR_I2A_8821C \ + (BIT_MASK_CMU_DLY_LTR_I2A_8821C << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) +#define BIT_CLEAR_CMU_DLY_LTR_I2A_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8821C)) +#define BIT_GET_CMU_DLY_LTR_I2A_8821C(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) & \ + BIT_MASK_CMU_DLY_LTR_I2A_8821C) +#define BIT_SET_CMU_DLY_LTR_I2A_8821C(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_I2A_8821C(x) | BIT_CMU_DLY_LTR_I2A_8821C(v)) #define BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C 8 #define BIT_MASK_CMU_DLY_LTR_IDLE_8821C 0xff -#define BIT_CMU_DLY_LTR_IDLE_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) -#define BIT_GET_CMU_DLY_LTR_IDLE_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) - - +#define BIT_CMU_DLY_LTR_IDLE_8821C(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) \ + << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) +#define BITS_CMU_DLY_LTR_IDLE_8821C \ + (BIT_MASK_CMU_DLY_LTR_IDLE_8821C << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) +#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8821C(x) \ + ((x) & (~BITS_CMU_DLY_LTR_IDLE_8821C)) +#define BIT_GET_CMU_DLY_LTR_IDLE_8821C(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) & \ + BIT_MASK_CMU_DLY_LTR_IDLE_8821C) +#define BIT_SET_CMU_DLY_LTR_IDLE_8821C(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_IDLE_8821C(x) | BIT_CMU_DLY_LTR_IDLE_8821C(v)) #define BIT_SHIFT_CMU_DLY_LTR_ACT_8821C 0 #define BIT_MASK_CMU_DLY_LTR_ACT_8821C 0xff -#define BIT_CMU_DLY_LTR_ACT_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) -#define BIT_GET_CMU_DLY_LTR_ACT_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) - - +#define BIT_CMU_DLY_LTR_ACT_8821C(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) \ + << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) +#define BITS_CMU_DLY_LTR_ACT_8821C \ + (BIT_MASK_CMU_DLY_LTR_ACT_8821C << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) +#define BIT_CLEAR_CMU_DLY_LTR_ACT_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8821C)) +#define BIT_GET_CMU_DLY_LTR_ACT_8821C(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) & \ + BIT_MASK_CMU_DLY_LTR_ACT_8821C) +#define BIT_SET_CMU_DLY_LTR_ACT_8821C(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_ACT_8821C(x) | BIT_CMU_DLY_LTR_ACT_8821C(v)) /* 2 REG_H2CQ_TXBD_DESA_8821C */ #define BIT_SHIFT_H2CQ_TXBD_DESA_8821C 0 #define BIT_MASK_H2CQ_TXBD_DESA_8821C 0xffffffffffffffffL -#define BIT_H2CQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8821C) << BIT_SHIFT_H2CQ_TXBD_DESA_8821C) -#define BIT_GET_H2CQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8821C) & BIT_MASK_H2CQ_TXBD_DESA_8821C) - - +#define BIT_H2CQ_TXBD_DESA_8821C(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_8821C) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_8821C) +#define BITS_H2CQ_TXBD_DESA_8821C \ + (BIT_MASK_H2CQ_TXBD_DESA_8821C << BIT_SHIFT_H2CQ_TXBD_DESA_8821C) +#define BIT_CLEAR_H2CQ_TXBD_DESA_8821C(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8821C)) +#define BIT_GET_H2CQ_TXBD_DESA_8821C(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8821C) & \ + BIT_MASK_H2CQ_TXBD_DESA_8821C) +#define BIT_SET_H2CQ_TXBD_DESA_8821C(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_8821C(x) | BIT_H2CQ_TXBD_DESA_8821C(v)) /* 2 REG_H2CQ_TXBD_NUM_8821C */ #define BIT_PCIE_H2CQ_FLAG_8821C BIT(14) #define BIT_SHIFT_H2CQ_DESC_MODE_8821C 12 #define BIT_MASK_H2CQ_DESC_MODE_8821C 0x3 -#define BIT_H2CQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8821C) << BIT_SHIFT_H2CQ_DESC_MODE_8821C) -#define BIT_GET_H2CQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8821C) & BIT_MASK_H2CQ_DESC_MODE_8821C) - - +#define BIT_H2CQ_DESC_MODE_8821C(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE_8821C) \ + << BIT_SHIFT_H2CQ_DESC_MODE_8821C) +#define BITS_H2CQ_DESC_MODE_8821C \ + (BIT_MASK_H2CQ_DESC_MODE_8821C << BIT_SHIFT_H2CQ_DESC_MODE_8821C) +#define BIT_CLEAR_H2CQ_DESC_MODE_8821C(x) ((x) & (~BITS_H2CQ_DESC_MODE_8821C)) +#define BIT_GET_H2CQ_DESC_MODE_8821C(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8821C) & \ + BIT_MASK_H2CQ_DESC_MODE_8821C) +#define BIT_SET_H2CQ_DESC_MODE_8821C(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE_8821C(x) | BIT_H2CQ_DESC_MODE_8821C(v)) #define BIT_SHIFT_H2CQ_DESC_NUM_8821C 0 #define BIT_MASK_H2CQ_DESC_NUM_8821C 0xfff -#define BIT_H2CQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8821C) << BIT_SHIFT_H2CQ_DESC_NUM_8821C) -#define BIT_GET_H2CQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8821C) & BIT_MASK_H2CQ_DESC_NUM_8821C) - - +#define BIT_H2CQ_DESC_NUM_8821C(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM_8821C) << BIT_SHIFT_H2CQ_DESC_NUM_8821C) +#define BITS_H2CQ_DESC_NUM_8821C \ + (BIT_MASK_H2CQ_DESC_NUM_8821C << BIT_SHIFT_H2CQ_DESC_NUM_8821C) +#define BIT_CLEAR_H2CQ_DESC_NUM_8821C(x) ((x) & (~BITS_H2CQ_DESC_NUM_8821C)) +#define BIT_GET_H2CQ_DESC_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8821C) & BIT_MASK_H2CQ_DESC_NUM_8821C) +#define BIT_SET_H2CQ_DESC_NUM_8821C(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM_8821C(x) | BIT_H2CQ_DESC_NUM_8821C(v)) /* 2 REG_H2CQ_TXBD_IDX_8821C */ #define BIT_SHIFT_H2CQ_HW_IDX_8821C 16 #define BIT_MASK_H2CQ_HW_IDX_8821C 0xfff -#define BIT_H2CQ_HW_IDX_8821C(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8821C) << BIT_SHIFT_H2CQ_HW_IDX_8821C) -#define BIT_GET_H2CQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8821C) & BIT_MASK_H2CQ_HW_IDX_8821C) - - +#define BIT_H2CQ_HW_IDX_8821C(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX_8821C) << BIT_SHIFT_H2CQ_HW_IDX_8821C) +#define BITS_H2CQ_HW_IDX_8821C \ + (BIT_MASK_H2CQ_HW_IDX_8821C << BIT_SHIFT_H2CQ_HW_IDX_8821C) +#define BIT_CLEAR_H2CQ_HW_IDX_8821C(x) ((x) & (~BITS_H2CQ_HW_IDX_8821C)) +#define BIT_GET_H2CQ_HW_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8821C) & BIT_MASK_H2CQ_HW_IDX_8821C) +#define BIT_SET_H2CQ_HW_IDX_8821C(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX_8821C(x) | BIT_H2CQ_HW_IDX_8821C(v)) #define BIT_SHIFT_H2CQ_HOST_IDX_8821C 0 #define BIT_MASK_H2CQ_HOST_IDX_8821C 0xfff -#define BIT_H2CQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8821C) << BIT_SHIFT_H2CQ_HOST_IDX_8821C) -#define BIT_GET_H2CQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8821C) & BIT_MASK_H2CQ_HOST_IDX_8821C) - - +#define BIT_H2CQ_HOST_IDX_8821C(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX_8821C) << BIT_SHIFT_H2CQ_HOST_IDX_8821C) +#define BITS_H2CQ_HOST_IDX_8821C \ + (BIT_MASK_H2CQ_HOST_IDX_8821C << BIT_SHIFT_H2CQ_HOST_IDX_8821C) +#define BIT_CLEAR_H2CQ_HOST_IDX_8821C(x) ((x) & (~BITS_H2CQ_HOST_IDX_8821C)) +#define BIT_GET_H2CQ_HOST_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8821C) & BIT_MASK_H2CQ_HOST_IDX_8821C) +#define BIT_SET_H2CQ_HOST_IDX_8821C(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX_8821C(x) | BIT_H2CQ_HOST_IDX_8821C(v)) /* 2 REG_H2CQ_CSR_8821C[31:0] (H2CQ CONTROL AND STATUS) */ #define BIT_H2CQ_FULL_8821C BIT(31) #define BIT_CLR_H2CQ_HOST_IDX_8821C BIT(16) #define BIT_CLR_H2CQ_HW_IDX_8821C BIT(8) +#define BIT_STOP_H2CQ_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_Q0_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q0_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q0_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q0_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) -#define BIT_GET_QUEUEMACID_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) & BIT_MASK_QUEUEMACID_Q0_V1_8821C) - - +#define BIT_QUEUEMACID_Q0_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) +#define BITS_QUEUEMACID_Q0_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q0_V1_8821C << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q0_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q0_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q0_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q0_V1_8821C) +#define BIT_SET_QUEUEMACID_Q0_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q0_V1_8821C(x) | BIT_QUEUEMACID_Q0_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q0_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q0_V1_8821C 0x3 -#define BIT_QUEUEAC_Q0_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8821C) << BIT_SHIFT_QUEUEAC_Q0_V1_8821C) -#define BIT_GET_QUEUEAC_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8821C) & BIT_MASK_QUEUEAC_Q0_V1_8821C) - +#define BIT_QUEUEAC_Q0_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q0_V1_8821C) << BIT_SHIFT_QUEUEAC_Q0_V1_8821C) +#define BITS_QUEUEAC_Q0_V1_8821C \ + (BIT_MASK_QUEUEAC_Q0_V1_8821C << BIT_SHIFT_QUEUEAC_Q0_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q0_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8821C)) +#define BIT_GET_QUEUEAC_Q0_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8821C) & BIT_MASK_QUEUEAC_Q0_V1_8821C) +#define BIT_SET_QUEUEAC_Q0_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q0_V1_8821C(x) | BIT_QUEUEAC_Q0_V1_8821C(v)) #define BIT_TIDEMPTY_Q0_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q0_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q0_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q0_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) -#define BIT_GET_TAIL_PKT_Q0_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) & BIT_MASK_TAIL_PKT_Q0_V2_8821C) - - +#define BIT_TAIL_PKT_Q0_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) +#define BITS_TAIL_PKT_Q0_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q0_V2_8821C << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q0_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q0_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q0_V2_8821C) +#define BIT_SET_TAIL_PKT_Q0_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V2_8821C(x) | BIT_TAIL_PKT_Q0_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q0_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q0_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q0_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) -#define BIT_GET_HEAD_PKT_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) - - +#define BIT_HEAD_PKT_Q0_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) +#define BITS_HEAD_PKT_Q0_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q0_V1_8821C << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q0_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q0_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q0_V1_8821C) +#define BIT_SET_HEAD_PKT_Q0_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0_V1_8821C(x) | BIT_HEAD_PKT_Q0_V1_8821C(v)) /* 2 REG_Q1_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q1_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q1_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q1_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) -#define BIT_GET_QUEUEMACID_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) & BIT_MASK_QUEUEMACID_Q1_V1_8821C) - - +#define BIT_QUEUEMACID_Q1_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) +#define BITS_QUEUEMACID_Q1_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q1_V1_8821C << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q1_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q1_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q1_V1_8821C) +#define BIT_SET_QUEUEMACID_Q1_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q1_V1_8821C(x) | BIT_QUEUEMACID_Q1_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q1_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q1_V1_8821C 0x3 -#define BIT_QUEUEAC_Q1_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8821C) << BIT_SHIFT_QUEUEAC_Q1_V1_8821C) -#define BIT_GET_QUEUEAC_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8821C) & BIT_MASK_QUEUEAC_Q1_V1_8821C) - +#define BIT_QUEUEAC_Q1_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q1_V1_8821C) << BIT_SHIFT_QUEUEAC_Q1_V1_8821C) +#define BITS_QUEUEAC_Q1_V1_8821C \ + (BIT_MASK_QUEUEAC_Q1_V1_8821C << BIT_SHIFT_QUEUEAC_Q1_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q1_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8821C)) +#define BIT_GET_QUEUEAC_Q1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8821C) & BIT_MASK_QUEUEAC_Q1_V1_8821C) +#define BIT_SET_QUEUEAC_Q1_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q1_V1_8821C(x) | BIT_QUEUEAC_Q1_V1_8821C(v)) #define BIT_TIDEMPTY_Q1_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q1_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q1_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q1_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) -#define BIT_GET_TAIL_PKT_Q1_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) & BIT_MASK_TAIL_PKT_Q1_V2_8821C) - - +#define BIT_TAIL_PKT_Q1_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) +#define BITS_TAIL_PKT_Q1_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q1_V2_8821C << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q1_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q1_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q1_V2_8821C) +#define BIT_SET_TAIL_PKT_Q1_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V2_8821C(x) | BIT_TAIL_PKT_Q1_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q1_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q1_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q1_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) -#define BIT_GET_HEAD_PKT_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) - - +#define BIT_HEAD_PKT_Q1_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) +#define BITS_HEAD_PKT_Q1_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q1_V1_8821C << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q1_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q1_V1_8821C) +#define BIT_SET_HEAD_PKT_Q1_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1_V1_8821C(x) | BIT_HEAD_PKT_Q1_V1_8821C(v)) /* 2 REG_Q2_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q2_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q2_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q2_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) -#define BIT_GET_QUEUEMACID_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) & BIT_MASK_QUEUEMACID_Q2_V1_8821C) - - +#define BIT_QUEUEMACID_Q2_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) +#define BITS_QUEUEMACID_Q2_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q2_V1_8821C << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q2_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q2_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q2_V1_8821C) +#define BIT_SET_QUEUEMACID_Q2_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q2_V1_8821C(x) | BIT_QUEUEMACID_Q2_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q2_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q2_V1_8821C 0x3 -#define BIT_QUEUEAC_Q2_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8821C) << BIT_SHIFT_QUEUEAC_Q2_V1_8821C) -#define BIT_GET_QUEUEAC_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8821C) & BIT_MASK_QUEUEAC_Q2_V1_8821C) - +#define BIT_QUEUEAC_Q2_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q2_V1_8821C) << BIT_SHIFT_QUEUEAC_Q2_V1_8821C) +#define BITS_QUEUEAC_Q2_V1_8821C \ + (BIT_MASK_QUEUEAC_Q2_V1_8821C << BIT_SHIFT_QUEUEAC_Q2_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q2_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8821C)) +#define BIT_GET_QUEUEAC_Q2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8821C) & BIT_MASK_QUEUEAC_Q2_V1_8821C) +#define BIT_SET_QUEUEAC_Q2_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q2_V1_8821C(x) | BIT_QUEUEAC_Q2_V1_8821C(v)) #define BIT_TIDEMPTY_Q2_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q2_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q2_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q2_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) -#define BIT_GET_TAIL_PKT_Q2_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) & BIT_MASK_TAIL_PKT_Q2_V2_8821C) - - +#define BIT_TAIL_PKT_Q2_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) +#define BITS_TAIL_PKT_Q2_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q2_V2_8821C << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q2_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q2_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q2_V2_8821C) +#define BIT_SET_TAIL_PKT_Q2_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V2_8821C(x) | BIT_TAIL_PKT_Q2_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q2_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q2_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q2_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) -#define BIT_GET_HEAD_PKT_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) - - +#define BIT_HEAD_PKT_Q2_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) +#define BITS_HEAD_PKT_Q2_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q2_V1_8821C << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q2_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q2_V1_8821C) +#define BIT_SET_HEAD_PKT_Q2_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2_V1_8821C(x) | BIT_HEAD_PKT_Q2_V1_8821C(v)) /* 2 REG_Q3_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q3_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q3_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q3_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) -#define BIT_GET_QUEUEMACID_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) & BIT_MASK_QUEUEMACID_Q3_V1_8821C) - - +#define BIT_QUEUEMACID_Q3_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) +#define BITS_QUEUEMACID_Q3_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q3_V1_8821C << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q3_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q3_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q3_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q3_V1_8821C) +#define BIT_SET_QUEUEMACID_Q3_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q3_V1_8821C(x) | BIT_QUEUEMACID_Q3_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q3_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q3_V1_8821C 0x3 -#define BIT_QUEUEAC_Q3_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8821C) << BIT_SHIFT_QUEUEAC_Q3_V1_8821C) -#define BIT_GET_QUEUEAC_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8821C) & BIT_MASK_QUEUEAC_Q3_V1_8821C) - +#define BIT_QUEUEAC_Q3_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q3_V1_8821C) << BIT_SHIFT_QUEUEAC_Q3_V1_8821C) +#define BITS_QUEUEAC_Q3_V1_8821C \ + (BIT_MASK_QUEUEAC_Q3_V1_8821C << BIT_SHIFT_QUEUEAC_Q3_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q3_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8821C)) +#define BIT_GET_QUEUEAC_Q3_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8821C) & BIT_MASK_QUEUEAC_Q3_V1_8821C) +#define BIT_SET_QUEUEAC_Q3_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q3_V1_8821C(x) | BIT_QUEUEAC_Q3_V1_8821C(v)) #define BIT_TIDEMPTY_Q3_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q3_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q3_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q3_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) -#define BIT_GET_TAIL_PKT_Q3_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) & BIT_MASK_TAIL_PKT_Q3_V2_8821C) - - +#define BIT_TAIL_PKT_Q3_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) +#define BITS_TAIL_PKT_Q3_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q3_V2_8821C << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q3_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q3_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q3_V2_8821C) +#define BIT_SET_TAIL_PKT_Q3_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V2_8821C(x) | BIT_TAIL_PKT_Q3_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q3_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q3_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q3_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) -#define BIT_GET_HEAD_PKT_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) - - +#define BIT_HEAD_PKT_Q3_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) +#define BITS_HEAD_PKT_Q3_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q3_V1_8821C << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q3_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q3_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q3_V1_8821C) +#define BIT_SET_HEAD_PKT_Q3_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3_V1_8821C(x) | BIT_HEAD_PKT_Q3_V1_8821C(v)) /* 2 REG_MGQ_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C 25 #define BIT_MASK_QUEUEMACID_MGQ_V1_8821C 0x7f -#define BIT_QUEUEMACID_MGQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) -#define BIT_GET_QUEUEMACID_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C) - - +#define BIT_QUEUEMACID_MGQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) +#define BITS_QUEUEMACID_MGQ_V1_8821C \ + (BIT_MASK_QUEUEMACID_MGQ_V1_8821C << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_MGQ_V1_8821C)) +#define BIT_GET_QUEUEMACID_MGQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) & \ + BIT_MASK_QUEUEMACID_MGQ_V1_8821C) +#define BIT_SET_QUEUEMACID_MGQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_MGQ_V1_8821C(x) | BIT_QUEUEMACID_MGQ_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_MGQ_V1_8821C 23 #define BIT_MASK_QUEUEAC_MGQ_V1_8821C 0x3 -#define BIT_QUEUEAC_MGQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) -#define BIT_GET_QUEUEAC_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) - +#define BIT_QUEUEAC_MGQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) \ + << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) +#define BITS_QUEUEAC_MGQ_V1_8821C \ + (BIT_MASK_QUEUEAC_MGQ_V1_8821C << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) +#define BIT_CLEAR_QUEUEAC_MGQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8821C)) +#define BIT_GET_QUEUEAC_MGQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) & \ + BIT_MASK_QUEUEAC_MGQ_V1_8821C) +#define BIT_SET_QUEUEAC_MGQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_MGQ_V1_8821C(x) | BIT_QUEUEAC_MGQ_V1_8821C(v)) #define BIT_TIDEMPTY_MGQ_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C 11 #define BIT_MASK_TAIL_PKT_MGQ_V2_8821C 0x7ff -#define BIT_TAIL_PKT_MGQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) -#define BIT_GET_TAIL_PKT_MGQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C) - - +#define BIT_TAIL_PKT_MGQ_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) +#define BITS_TAIL_PKT_MGQ_V2_8821C \ + (BIT_MASK_TAIL_PKT_MGQ_V2_8821C << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8821C)) +#define BIT_GET_TAIL_PKT_MGQ_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) & \ + BIT_MASK_TAIL_PKT_MGQ_V2_8821C) +#define BIT_SET_TAIL_PKT_MGQ_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V2_8821C(x) | BIT_TAIL_PKT_MGQ_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C 0 #define BIT_MASK_HEAD_PKT_MGQ_V1_8821C 0x7ff -#define BIT_HEAD_PKT_MGQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) -#define BIT_GET_HEAD_PKT_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) - - +#define BIT_HEAD_PKT_MGQ_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) +#define BITS_HEAD_PKT_MGQ_V1_8821C \ + (BIT_MASK_HEAD_PKT_MGQ_V1_8821C << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8821C)) +#define BIT_GET_HEAD_PKT_MGQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) & \ + BIT_MASK_HEAD_PKT_MGQ_V1_8821C) +#define BIT_SET_HEAD_PKT_MGQ_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ_V1_8821C(x) | BIT_HEAD_PKT_MGQ_V1_8821C(v)) /* 2 REG_HIQ_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C 25 #define BIT_MASK_QUEUEMACID_HIQ_V1_8821C 0x7f -#define BIT_QUEUEMACID_HIQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) -#define BIT_GET_QUEUEMACID_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C) - - +#define BIT_QUEUEMACID_HIQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) +#define BITS_QUEUEMACID_HIQ_V1_8821C \ + (BIT_MASK_QUEUEMACID_HIQ_V1_8821C << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_HIQ_V1_8821C)) +#define BIT_GET_QUEUEMACID_HIQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) & \ + BIT_MASK_QUEUEMACID_HIQ_V1_8821C) +#define BIT_SET_QUEUEMACID_HIQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_HIQ_V1_8821C(x) | BIT_QUEUEMACID_HIQ_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_HIQ_V1_8821C 23 #define BIT_MASK_QUEUEAC_HIQ_V1_8821C 0x3 -#define BIT_QUEUEAC_HIQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) -#define BIT_GET_QUEUEAC_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) - +#define BIT_QUEUEAC_HIQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) \ + << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) +#define BITS_QUEUEAC_HIQ_V1_8821C \ + (BIT_MASK_QUEUEAC_HIQ_V1_8821C << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) +#define BIT_CLEAR_QUEUEAC_HIQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8821C)) +#define BIT_GET_QUEUEAC_HIQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) & \ + BIT_MASK_QUEUEAC_HIQ_V1_8821C) +#define BIT_SET_QUEUEAC_HIQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_HIQ_V1_8821C(x) | BIT_QUEUEAC_HIQ_V1_8821C(v)) #define BIT_TIDEMPTY_HIQ_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C 11 #define BIT_MASK_TAIL_PKT_HIQ_V2_8821C 0x7ff -#define BIT_TAIL_PKT_HIQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) -#define BIT_GET_TAIL_PKT_HIQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C) - - +#define BIT_TAIL_PKT_HIQ_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) +#define BITS_TAIL_PKT_HIQ_V2_8821C \ + (BIT_MASK_TAIL_PKT_HIQ_V2_8821C << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8821C)) +#define BIT_GET_TAIL_PKT_HIQ_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) & \ + BIT_MASK_TAIL_PKT_HIQ_V2_8821C) +#define BIT_SET_TAIL_PKT_HIQ_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V2_8821C(x) | BIT_TAIL_PKT_HIQ_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C 0 #define BIT_MASK_HEAD_PKT_HIQ_V1_8821C 0x7ff -#define BIT_HEAD_PKT_HIQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) -#define BIT_GET_HEAD_PKT_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) - - +#define BIT_HEAD_PKT_HIQ_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) +#define BITS_HEAD_PKT_HIQ_V1_8821C \ + (BIT_MASK_HEAD_PKT_HIQ_V1_8821C << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8821C)) +#define BIT_GET_HEAD_PKT_HIQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) & \ + BIT_MASK_HEAD_PKT_HIQ_V1_8821C) +#define BIT_SET_HEAD_PKT_HIQ_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ_V1_8821C(x) | BIT_HEAD_PKT_HIQ_V1_8821C(v)) /* 2 REG_BCNQ_INFO_8821C */ #define BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C 0 #define BIT_MASK_BCNQ_HEAD_PG_V1_8821C 0xfff -#define BIT_BCNQ_HEAD_PG_V1_8821C(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) -#define BIT_GET_BCNQ_HEAD_PG_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C) - - +#define BIT_BCNQ_HEAD_PG_V1_8821C(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C) \ + << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) +#define BITS_BCNQ_HEAD_PG_V1_8821C \ + (BIT_MASK_BCNQ_HEAD_PG_V1_8821C << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) +#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8821C(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8821C)) +#define BIT_GET_BCNQ_HEAD_PG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) & \ + BIT_MASK_BCNQ_HEAD_PG_V1_8821C) +#define BIT_SET_BCNQ_HEAD_PG_V1_8821C(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG_V1_8821C(x) | BIT_BCNQ_HEAD_PG_V1_8821C(v)) /* 2 REG_TXPKT_EMPTY_8821C */ #define BIT_BCNQ_EMPTY_8821C BIT(11) @@ -5533,10 +9087,17 @@ #define BIT_SHIFT_FW_FREE_TAIL_V1_8821C 0 #define BIT_MASK_FW_FREE_TAIL_V1_8821C 0xfff -#define BIT_FW_FREE_TAIL_V1_8821C(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8821C) << BIT_SHIFT_FW_FREE_TAIL_V1_8821C) -#define BIT_GET_FW_FREE_TAIL_V1_8821C(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8821C) & BIT_MASK_FW_FREE_TAIL_V1_8821C) - - +#define BIT_FW_FREE_TAIL_V1_8821C(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL_V1_8821C) \ + << BIT_SHIFT_FW_FREE_TAIL_V1_8821C) +#define BITS_FW_FREE_TAIL_V1_8821C \ + (BIT_MASK_FW_FREE_TAIL_V1_8821C << BIT_SHIFT_FW_FREE_TAIL_V1_8821C) +#define BIT_CLEAR_FW_FREE_TAIL_V1_8821C(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8821C)) +#define BIT_GET_FW_FREE_TAIL_V1_8821C(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8821C) & \ + BIT_MASK_FW_FREE_TAIL_V1_8821C) +#define BIT_SET_FW_FREE_TAIL_V1_8821C(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL_V1_8821C(x) | BIT_FW_FREE_TAIL_V1_8821C(v)) /* 2 REG_FWHW_TXQ_CTRL_8821C */ #define BIT_RTS_LIMIT_IN_OFDM_8821C BIT(23) @@ -5546,9 +9107,15 @@ #define BIT_SHIFT_EN_QUEUE_RPT_8821C 8 #define BIT_MASK_EN_QUEUE_RPT_8821C 0xff -#define BIT_EN_QUEUE_RPT_8821C(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8821C) << BIT_SHIFT_EN_QUEUE_RPT_8821C) -#define BIT_GET_EN_QUEUE_RPT_8821C(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8821C) & BIT_MASK_EN_QUEUE_RPT_8821C) - +#define BIT_EN_QUEUE_RPT_8821C(x) \ + (((x) & BIT_MASK_EN_QUEUE_RPT_8821C) << BIT_SHIFT_EN_QUEUE_RPT_8821C) +#define BITS_EN_QUEUE_RPT_8821C \ + (BIT_MASK_EN_QUEUE_RPT_8821C << BIT_SHIFT_EN_QUEUE_RPT_8821C) +#define BIT_CLEAR_EN_QUEUE_RPT_8821C(x) ((x) & (~BITS_EN_QUEUE_RPT_8821C)) +#define BIT_GET_EN_QUEUE_RPT_8821C(x) \ + (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8821C) & BIT_MASK_EN_QUEUE_RPT_8821C) +#define BIT_SET_EN_QUEUE_RPT_8821C(x, v) \ + (BIT_CLEAR_EN_QUEUE_RPT_8821C(x) | BIT_EN_QUEUE_RPT_8821C(v)) #define BIT_EN_RTY_BK_8821C BIT(7) #define BIT_EN_USE_INI_RAT_8821C BIT(6) @@ -5556,27 +9123,45 @@ #define BIT_DIS_SSN_CHECK_8821C BIT(4) #define BIT_MACID_MATCH_RTS_8821C BIT(3) #define BIT_EN_BCN_TRXRPT_V1_8821C BIT(2) -#define BIT_R_EN_FTMRPT_8821C BIT(1) +#define BIT_R_EN_FTMRPT_V1_8821C BIT(1) #define BIT_R_BMC_NAV_PROTECT_8821C BIT(0) /* 2 REG_DATAFB_SEL_8821C */ -#define BIT__R_EN_RTY_BK_COD_8821C BIT(2) +#define BIT_BROADCAST_RTY_EN_8821C BIT(3) +#define BIT_EN_RTY_BK_COD_8821C BIT(2) #define BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C 0 #define BIT_MASK__R_DATA_FALLBACK_SEL_8821C 0x3 -#define BIT__R_DATA_FALLBACK_SEL_8821C(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) -#define BIT_GET__R_DATA_FALLBACK_SEL_8821C(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C) - - +#define BIT__R_DATA_FALLBACK_SEL_8821C(x) \ + (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C) \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) +#define BITS__R_DATA_FALLBACK_SEL_8821C \ + (BIT_MASK__R_DATA_FALLBACK_SEL_8821C \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) +#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8821C(x) \ + ((x) & (~BITS__R_DATA_FALLBACK_SEL_8821C)) +#define BIT_GET__R_DATA_FALLBACK_SEL_8821C(x) \ + (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) & \ + BIT_MASK__R_DATA_FALLBACK_SEL_8821C) +#define BIT_SET__R_DATA_FALLBACK_SEL_8821C(x, v) \ + (BIT_CLEAR__R_DATA_FALLBACK_SEL_8821C(x) | \ + BIT__R_DATA_FALLBACK_SEL_8821C(v)) /* 2 REG_BCNQ_BDNY_V1_8821C */ #define BIT_SHIFT_BCNQ_PGBNDY_V1_8821C 0 #define BIT_MASK_BCNQ_PGBNDY_V1_8821C 0xfff -#define BIT_BCNQ_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8821C) << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) -#define BIT_GET_BCNQ_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) & BIT_MASK_BCNQ_PGBNDY_V1_8821C) - - +#define BIT_BCNQ_PGBNDY_V1_8821C(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8821C) \ + << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) +#define BITS_BCNQ_PGBNDY_V1_8821C \ + (BIT_MASK_BCNQ_PGBNDY_V1_8821C << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) +#define BIT_CLEAR_BCNQ_PGBNDY_V1_8821C(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8821C)) +#define BIT_GET_BCNQ_PGBNDY_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) & \ + BIT_MASK_BCNQ_PGBNDY_V1_8821C) +#define BIT_SET_BCNQ_PGBNDY_V1_8821C(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_V1_8821C(x) | BIT_BCNQ_PGBNDY_V1_8821C(v)) /* 2 REG_LIFETIME_EN_8821C */ #define BIT_BT_INT_CPU_8821C BIT(7) @@ -5593,33 +9178,55 @@ #define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C 8 #define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C 0xff -#define BIT_SPEC_SIFS_OFDM_PTCL_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) -#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) - - +#define BIT_SPEC_SIFS_OFDM_PTCL_8821C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) +#define BITS_SPEC_SIFS_OFDM_PTCL_8821C \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8821C(x) \ + ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8821C)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8821C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) & \ + BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8821C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8821C(x) | \ + BIT_SPEC_SIFS_OFDM_PTCL_8821C(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C 0 #define BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C 0xff -#define BIT_SPEC_SIFS_CCK_PTCL_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) -#define BIT_GET_SPEC_SIFS_CCK_PTCL_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) - - +#define BIT_SPEC_SIFS_CCK_PTCL_8821C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) +#define BITS_SPEC_SIFS_CCK_PTCL_8821C \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8821C(x) \ + ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8821C)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8821C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) & \ + BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) +#define BIT_SET_SPEC_SIFS_CCK_PTCL_8821C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8821C(x) | \ + BIT_SPEC_SIFS_CCK_PTCL_8821C(v)) /* 2 REG_RETRY_LIMIT_8821C */ #define BIT_SHIFT_SRL_8821C 8 #define BIT_MASK_SRL_8821C 0x3f #define BIT_SRL_8821C(x) (((x) & BIT_MASK_SRL_8821C) << BIT_SHIFT_SRL_8821C) +#define BITS_SRL_8821C (BIT_MASK_SRL_8821C << BIT_SHIFT_SRL_8821C) +#define BIT_CLEAR_SRL_8821C(x) ((x) & (~BITS_SRL_8821C)) #define BIT_GET_SRL_8821C(x) (((x) >> BIT_SHIFT_SRL_8821C) & BIT_MASK_SRL_8821C) - - +#define BIT_SET_SRL_8821C(x, v) (BIT_CLEAR_SRL_8821C(x) | BIT_SRL_8821C(v)) #define BIT_SHIFT_LRL_8821C 0 #define BIT_MASK_LRL_8821C 0x3f #define BIT_LRL_8821C(x) (((x) & BIT_MASK_LRL_8821C) << BIT_SHIFT_LRL_8821C) +#define BITS_LRL_8821C (BIT_MASK_LRL_8821C << BIT_SHIFT_LRL_8821C) +#define BIT_CLEAR_LRL_8821C(x) ((x) & (~BITS_LRL_8821C)) #define BIT_GET_LRL_8821C(x) (((x) >> BIT_SHIFT_LRL_8821C) & BIT_MASK_LRL_8821C) - - +#define BIT_SET_LRL_8821C(x, v) (BIT_CLEAR_LRL_8821C(x) | BIT_LRL_8821C(v)) /* 2 REG_TXBF_CTRL_8821C */ #define BIT_R_ENABLE_NDPA_8821C BIT(31) @@ -5632,9 +9239,15 @@ #define BIT_SHIFT_R_TXBF1_AID_8821C 16 #define BIT_MASK_R_TXBF1_AID_8821C 0x1ff -#define BIT_R_TXBF1_AID_8821C(x) (((x) & BIT_MASK_R_TXBF1_AID_8821C) << BIT_SHIFT_R_TXBF1_AID_8821C) -#define BIT_GET_R_TXBF1_AID_8821C(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8821C) & BIT_MASK_R_TXBF1_AID_8821C) - +#define BIT_R_TXBF1_AID_8821C(x) \ + (((x) & BIT_MASK_R_TXBF1_AID_8821C) << BIT_SHIFT_R_TXBF1_AID_8821C) +#define BITS_R_TXBF1_AID_8821C \ + (BIT_MASK_R_TXBF1_AID_8821C << BIT_SHIFT_R_TXBF1_AID_8821C) +#define BIT_CLEAR_R_TXBF1_AID_8821C(x) ((x) & (~BITS_R_TXBF1_AID_8821C)) +#define BIT_GET_R_TXBF1_AID_8821C(x) \ + (((x) >> BIT_SHIFT_R_TXBF1_AID_8821C) & BIT_MASK_R_TXBF1_AID_8821C) +#define BIT_SET_R_TXBF1_AID_8821C(x, v) \ + (BIT_CLEAR_R_TXBF1_AID_8821C(x) | BIT_R_TXBF1_AID_8821C(v)) #define BIT_DIS_NDP_BFEN_8821C BIT(15) #define BIT_R_TXBCN_NOBLOCK_NDP_8821C BIT(14) @@ -5644,161 +9257,295 @@ #define BIT_SHIFT_R_TXBF0_AID_8821C 0 #define BIT_MASK_R_TXBF0_AID_8821C 0x1ff -#define BIT_R_TXBF0_AID_8821C(x) (((x) & BIT_MASK_R_TXBF0_AID_8821C) << BIT_SHIFT_R_TXBF0_AID_8821C) -#define BIT_GET_R_TXBF0_AID_8821C(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8821C) & BIT_MASK_R_TXBF0_AID_8821C) - - +#define BIT_R_TXBF0_AID_8821C(x) \ + (((x) & BIT_MASK_R_TXBF0_AID_8821C) << BIT_SHIFT_R_TXBF0_AID_8821C) +#define BITS_R_TXBF0_AID_8821C \ + (BIT_MASK_R_TXBF0_AID_8821C << BIT_SHIFT_R_TXBF0_AID_8821C) +#define BIT_CLEAR_R_TXBF0_AID_8821C(x) ((x) & (~BITS_R_TXBF0_AID_8821C)) +#define BIT_GET_R_TXBF0_AID_8821C(x) \ + (((x) >> BIT_SHIFT_R_TXBF0_AID_8821C) & BIT_MASK_R_TXBF0_AID_8821C) +#define BIT_SET_R_TXBF0_AID_8821C(x, v) \ + (BIT_CLEAR_R_TXBF0_AID_8821C(x) | BIT_R_TXBF0_AID_8821C(v)) /* 2 REG_DARFRC_8821C */ -#define BIT_SHIFT_DARF_RC8_8821C (56 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC8_8821C 0x1f -#define BIT_DARF_RC8_8821C(x) (((x) & BIT_MASK_DARF_RC8_8821C) << BIT_SHIFT_DARF_RC8_8821C) -#define BIT_GET_DARF_RC8_8821C(x) (((x) >> BIT_SHIFT_DARF_RC8_8821C) & BIT_MASK_DARF_RC8_8821C) - - - -#define BIT_SHIFT_DARF_RC7_8821C (48 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC7_8821C 0x1f -#define BIT_DARF_RC7_8821C(x) (((x) & BIT_MASK_DARF_RC7_8821C) << BIT_SHIFT_DARF_RC7_8821C) -#define BIT_GET_DARF_RC7_8821C(x) (((x) >> BIT_SHIFT_DARF_RC7_8821C) & BIT_MASK_DARF_RC7_8821C) - - - -#define BIT_SHIFT_DARF_RC6_8821C (40 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC6_8821C 0x1f -#define BIT_DARF_RC6_8821C(x) (((x) & BIT_MASK_DARF_RC6_8821C) << BIT_SHIFT_DARF_RC6_8821C) -#define BIT_GET_DARF_RC6_8821C(x) (((x) >> BIT_SHIFT_DARF_RC6_8821C) & BIT_MASK_DARF_RC6_8821C) - - - -#define BIT_SHIFT_DARF_RC5_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_DARF_RC5_8821C 0x1f -#define BIT_DARF_RC5_8821C(x) (((x) & BIT_MASK_DARF_RC5_8821C) << BIT_SHIFT_DARF_RC5_8821C) -#define BIT_GET_DARF_RC5_8821C(x) (((x) >> BIT_SHIFT_DARF_RC5_8821C) & BIT_MASK_DARF_RC5_8821C) - - - #define BIT_SHIFT_DARF_RC4_8821C 24 #define BIT_MASK_DARF_RC4_8821C 0x1f -#define BIT_DARF_RC4_8821C(x) (((x) & BIT_MASK_DARF_RC4_8821C) << BIT_SHIFT_DARF_RC4_8821C) -#define BIT_GET_DARF_RC4_8821C(x) (((x) >> BIT_SHIFT_DARF_RC4_8821C) & BIT_MASK_DARF_RC4_8821C) - - +#define BIT_DARF_RC4_8821C(x) \ + (((x) & BIT_MASK_DARF_RC4_8821C) << BIT_SHIFT_DARF_RC4_8821C) +#define BITS_DARF_RC4_8821C \ + (BIT_MASK_DARF_RC4_8821C << BIT_SHIFT_DARF_RC4_8821C) +#define BIT_CLEAR_DARF_RC4_8821C(x) ((x) & (~BITS_DARF_RC4_8821C)) +#define BIT_GET_DARF_RC4_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_8821C) & BIT_MASK_DARF_RC4_8821C) +#define BIT_SET_DARF_RC4_8821C(x, v) \ + (BIT_CLEAR_DARF_RC4_8821C(x) | BIT_DARF_RC4_8821C(v)) #define BIT_SHIFT_DARF_RC3_8821C 16 #define BIT_MASK_DARF_RC3_8821C 0x1f -#define BIT_DARF_RC3_8821C(x) (((x) & BIT_MASK_DARF_RC3_8821C) << BIT_SHIFT_DARF_RC3_8821C) -#define BIT_GET_DARF_RC3_8821C(x) (((x) >> BIT_SHIFT_DARF_RC3_8821C) & BIT_MASK_DARF_RC3_8821C) - - +#define BIT_DARF_RC3_8821C(x) \ + (((x) & BIT_MASK_DARF_RC3_8821C) << BIT_SHIFT_DARF_RC3_8821C) +#define BITS_DARF_RC3_8821C \ + (BIT_MASK_DARF_RC3_8821C << BIT_SHIFT_DARF_RC3_8821C) +#define BIT_CLEAR_DARF_RC3_8821C(x) ((x) & (~BITS_DARF_RC3_8821C)) +#define BIT_GET_DARF_RC3_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_8821C) & BIT_MASK_DARF_RC3_8821C) +#define BIT_SET_DARF_RC3_8821C(x, v) \ + (BIT_CLEAR_DARF_RC3_8821C(x) | BIT_DARF_RC3_8821C(v)) #define BIT_SHIFT_DARF_RC2_8821C 8 #define BIT_MASK_DARF_RC2_8821C 0x1f -#define BIT_DARF_RC2_8821C(x) (((x) & BIT_MASK_DARF_RC2_8821C) << BIT_SHIFT_DARF_RC2_8821C) -#define BIT_GET_DARF_RC2_8821C(x) (((x) >> BIT_SHIFT_DARF_RC2_8821C) & BIT_MASK_DARF_RC2_8821C) - - +#define BIT_DARF_RC2_8821C(x) \ + (((x) & BIT_MASK_DARF_RC2_8821C) << BIT_SHIFT_DARF_RC2_8821C) +#define BITS_DARF_RC2_8821C \ + (BIT_MASK_DARF_RC2_8821C << BIT_SHIFT_DARF_RC2_8821C) +#define BIT_CLEAR_DARF_RC2_8821C(x) ((x) & (~BITS_DARF_RC2_8821C)) +#define BIT_GET_DARF_RC2_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_8821C) & BIT_MASK_DARF_RC2_8821C) +#define BIT_SET_DARF_RC2_8821C(x, v) \ + (BIT_CLEAR_DARF_RC2_8821C(x) | BIT_DARF_RC2_8821C(v)) #define BIT_SHIFT_DARF_RC1_8821C 0 #define BIT_MASK_DARF_RC1_8821C 0x1f -#define BIT_DARF_RC1_8821C(x) (((x) & BIT_MASK_DARF_RC1_8821C) << BIT_SHIFT_DARF_RC1_8821C) -#define BIT_GET_DARF_RC1_8821C(x) (((x) >> BIT_SHIFT_DARF_RC1_8821C) & BIT_MASK_DARF_RC1_8821C) - - +#define BIT_DARF_RC1_8821C(x) \ + (((x) & BIT_MASK_DARF_RC1_8821C) << BIT_SHIFT_DARF_RC1_8821C) +#define BITS_DARF_RC1_8821C \ + (BIT_MASK_DARF_RC1_8821C << BIT_SHIFT_DARF_RC1_8821C) +#define BIT_CLEAR_DARF_RC1_8821C(x) ((x) & (~BITS_DARF_RC1_8821C)) +#define BIT_GET_DARF_RC1_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_8821C) & BIT_MASK_DARF_RC1_8821C) +#define BIT_SET_DARF_RC1_8821C(x, v) \ + (BIT_CLEAR_DARF_RC1_8821C(x) | BIT_DARF_RC1_8821C(v)) + +/* 2 REG_DARFRCH_8821C */ + +#define BIT_SHIFT_DARF_RC8_V1_8821C 24 +#define BIT_MASK_DARF_RC8_V1_8821C 0x1f +#define BIT_DARF_RC8_V1_8821C(x) \ + (((x) & BIT_MASK_DARF_RC8_V1_8821C) << BIT_SHIFT_DARF_RC8_V1_8821C) +#define BITS_DARF_RC8_V1_8821C \ + (BIT_MASK_DARF_RC8_V1_8821C << BIT_SHIFT_DARF_RC8_V1_8821C) +#define BIT_CLEAR_DARF_RC8_V1_8821C(x) ((x) & (~BITS_DARF_RC8_V1_8821C)) +#define BIT_GET_DARF_RC8_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_V1_8821C) & BIT_MASK_DARF_RC8_V1_8821C) +#define BIT_SET_DARF_RC8_V1_8821C(x, v) \ + (BIT_CLEAR_DARF_RC8_V1_8821C(x) | BIT_DARF_RC8_V1_8821C(v)) + +#define BIT_SHIFT_DARF_RC7_V1_8821C 16 +#define BIT_MASK_DARF_RC7_V1_8821C 0x1f +#define BIT_DARF_RC7_V1_8821C(x) \ + (((x) & BIT_MASK_DARF_RC7_V1_8821C) << BIT_SHIFT_DARF_RC7_V1_8821C) +#define BITS_DARF_RC7_V1_8821C \ + (BIT_MASK_DARF_RC7_V1_8821C << BIT_SHIFT_DARF_RC7_V1_8821C) +#define BIT_CLEAR_DARF_RC7_V1_8821C(x) ((x) & (~BITS_DARF_RC7_V1_8821C)) +#define BIT_GET_DARF_RC7_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_V1_8821C) & BIT_MASK_DARF_RC7_V1_8821C) +#define BIT_SET_DARF_RC7_V1_8821C(x, v) \ + (BIT_CLEAR_DARF_RC7_V1_8821C(x) | BIT_DARF_RC7_V1_8821C(v)) + +#define BIT_SHIFT_DARF_RC6_V1_8821C 8 +#define BIT_MASK_DARF_RC6_V1_8821C 0x1f +#define BIT_DARF_RC6_V1_8821C(x) \ + (((x) & BIT_MASK_DARF_RC6_V1_8821C) << BIT_SHIFT_DARF_RC6_V1_8821C) +#define BITS_DARF_RC6_V1_8821C \ + (BIT_MASK_DARF_RC6_V1_8821C << BIT_SHIFT_DARF_RC6_V1_8821C) +#define BIT_CLEAR_DARF_RC6_V1_8821C(x) ((x) & (~BITS_DARF_RC6_V1_8821C)) +#define BIT_GET_DARF_RC6_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_V1_8821C) & BIT_MASK_DARF_RC6_V1_8821C) +#define BIT_SET_DARF_RC6_V1_8821C(x, v) \ + (BIT_CLEAR_DARF_RC6_V1_8821C(x) | BIT_DARF_RC6_V1_8821C(v)) + +#define BIT_SHIFT_DARF_RC5_V1_8821C 0 +#define BIT_MASK_DARF_RC5_V1_8821C 0x1f +#define BIT_DARF_RC5_V1_8821C(x) \ + (((x) & BIT_MASK_DARF_RC5_V1_8821C) << BIT_SHIFT_DARF_RC5_V1_8821C) +#define BITS_DARF_RC5_V1_8821C \ + (BIT_MASK_DARF_RC5_V1_8821C << BIT_SHIFT_DARF_RC5_V1_8821C) +#define BIT_CLEAR_DARF_RC5_V1_8821C(x) ((x) & (~BITS_DARF_RC5_V1_8821C)) +#define BIT_GET_DARF_RC5_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_V1_8821C) & BIT_MASK_DARF_RC5_V1_8821C) +#define BIT_SET_DARF_RC5_V1_8821C(x, v) \ + (BIT_CLEAR_DARF_RC5_V1_8821C(x) | BIT_DARF_RC5_V1_8821C(v)) /* 2 REG_RARFRC_8821C */ -#define BIT_SHIFT_RARF_RC8_8821C (56 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC8_8821C 0x1f -#define BIT_RARF_RC8_8821C(x) (((x) & BIT_MASK_RARF_RC8_8821C) << BIT_SHIFT_RARF_RC8_8821C) -#define BIT_GET_RARF_RC8_8821C(x) (((x) >> BIT_SHIFT_RARF_RC8_8821C) & BIT_MASK_RARF_RC8_8821C) - - - -#define BIT_SHIFT_RARF_RC7_8821C (48 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC7_8821C 0x1f -#define BIT_RARF_RC7_8821C(x) (((x) & BIT_MASK_RARF_RC7_8821C) << BIT_SHIFT_RARF_RC7_8821C) -#define BIT_GET_RARF_RC7_8821C(x) (((x) >> BIT_SHIFT_RARF_RC7_8821C) & BIT_MASK_RARF_RC7_8821C) - - - -#define BIT_SHIFT_RARF_RC6_8821C (40 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC6_8821C 0x1f -#define BIT_RARF_RC6_8821C(x) (((x) & BIT_MASK_RARF_RC6_8821C) << BIT_SHIFT_RARF_RC6_8821C) -#define BIT_GET_RARF_RC6_8821C(x) (((x) >> BIT_SHIFT_RARF_RC6_8821C) & BIT_MASK_RARF_RC6_8821C) - - - -#define BIT_SHIFT_RARF_RC5_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_RARF_RC5_8821C 0x1f -#define BIT_RARF_RC5_8821C(x) (((x) & BIT_MASK_RARF_RC5_8821C) << BIT_SHIFT_RARF_RC5_8821C) -#define BIT_GET_RARF_RC5_8821C(x) (((x) >> BIT_SHIFT_RARF_RC5_8821C) & BIT_MASK_RARF_RC5_8821C) - - - #define BIT_SHIFT_RARF_RC4_8821C 24 #define BIT_MASK_RARF_RC4_8821C 0x1f -#define BIT_RARF_RC4_8821C(x) (((x) & BIT_MASK_RARF_RC4_8821C) << BIT_SHIFT_RARF_RC4_8821C) -#define BIT_GET_RARF_RC4_8821C(x) (((x) >> BIT_SHIFT_RARF_RC4_8821C) & BIT_MASK_RARF_RC4_8821C) - - +#define BIT_RARF_RC4_8821C(x) \ + (((x) & BIT_MASK_RARF_RC4_8821C) << BIT_SHIFT_RARF_RC4_8821C) +#define BITS_RARF_RC4_8821C \ + (BIT_MASK_RARF_RC4_8821C << BIT_SHIFT_RARF_RC4_8821C) +#define BIT_CLEAR_RARF_RC4_8821C(x) ((x) & (~BITS_RARF_RC4_8821C)) +#define BIT_GET_RARF_RC4_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC4_8821C) & BIT_MASK_RARF_RC4_8821C) +#define BIT_SET_RARF_RC4_8821C(x, v) \ + (BIT_CLEAR_RARF_RC4_8821C(x) | BIT_RARF_RC4_8821C(v)) #define BIT_SHIFT_RARF_RC3_8821C 16 #define BIT_MASK_RARF_RC3_8821C 0x1f -#define BIT_RARF_RC3_8821C(x) (((x) & BIT_MASK_RARF_RC3_8821C) << BIT_SHIFT_RARF_RC3_8821C) -#define BIT_GET_RARF_RC3_8821C(x) (((x) >> BIT_SHIFT_RARF_RC3_8821C) & BIT_MASK_RARF_RC3_8821C) - - +#define BIT_RARF_RC3_8821C(x) \ + (((x) & BIT_MASK_RARF_RC3_8821C) << BIT_SHIFT_RARF_RC3_8821C) +#define BITS_RARF_RC3_8821C \ + (BIT_MASK_RARF_RC3_8821C << BIT_SHIFT_RARF_RC3_8821C) +#define BIT_CLEAR_RARF_RC3_8821C(x) ((x) & (~BITS_RARF_RC3_8821C)) +#define BIT_GET_RARF_RC3_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC3_8821C) & BIT_MASK_RARF_RC3_8821C) +#define BIT_SET_RARF_RC3_8821C(x, v) \ + (BIT_CLEAR_RARF_RC3_8821C(x) | BIT_RARF_RC3_8821C(v)) #define BIT_SHIFT_RARF_RC2_8821C 8 #define BIT_MASK_RARF_RC2_8821C 0x1f -#define BIT_RARF_RC2_8821C(x) (((x) & BIT_MASK_RARF_RC2_8821C) << BIT_SHIFT_RARF_RC2_8821C) -#define BIT_GET_RARF_RC2_8821C(x) (((x) >> BIT_SHIFT_RARF_RC2_8821C) & BIT_MASK_RARF_RC2_8821C) - - +#define BIT_RARF_RC2_8821C(x) \ + (((x) & BIT_MASK_RARF_RC2_8821C) << BIT_SHIFT_RARF_RC2_8821C) +#define BITS_RARF_RC2_8821C \ + (BIT_MASK_RARF_RC2_8821C << BIT_SHIFT_RARF_RC2_8821C) +#define BIT_CLEAR_RARF_RC2_8821C(x) ((x) & (~BITS_RARF_RC2_8821C)) +#define BIT_GET_RARF_RC2_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC2_8821C) & BIT_MASK_RARF_RC2_8821C) +#define BIT_SET_RARF_RC2_8821C(x, v) \ + (BIT_CLEAR_RARF_RC2_8821C(x) | BIT_RARF_RC2_8821C(v)) #define BIT_SHIFT_RARF_RC1_8821C 0 #define BIT_MASK_RARF_RC1_8821C 0x1f -#define BIT_RARF_RC1_8821C(x) (((x) & BIT_MASK_RARF_RC1_8821C) << BIT_SHIFT_RARF_RC1_8821C) -#define BIT_GET_RARF_RC1_8821C(x) (((x) >> BIT_SHIFT_RARF_RC1_8821C) & BIT_MASK_RARF_RC1_8821C) - - +#define BIT_RARF_RC1_8821C(x) \ + (((x) & BIT_MASK_RARF_RC1_8821C) << BIT_SHIFT_RARF_RC1_8821C) +#define BITS_RARF_RC1_8821C \ + (BIT_MASK_RARF_RC1_8821C << BIT_SHIFT_RARF_RC1_8821C) +#define BIT_CLEAR_RARF_RC1_8821C(x) ((x) & (~BITS_RARF_RC1_8821C)) +#define BIT_GET_RARF_RC1_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC1_8821C) & BIT_MASK_RARF_RC1_8821C) +#define BIT_SET_RARF_RC1_8821C(x, v) \ + (BIT_CLEAR_RARF_RC1_8821C(x) | BIT_RARF_RC1_8821C(v)) + +/* 2 REG_RARFRCH_8821C */ + +#define BIT_SHIFT_RARF_RC8_V1_8821C 24 +#define BIT_MASK_RARF_RC8_V1_8821C 0x1f +#define BIT_RARF_RC8_V1_8821C(x) \ + (((x) & BIT_MASK_RARF_RC8_V1_8821C) << BIT_SHIFT_RARF_RC8_V1_8821C) +#define BITS_RARF_RC8_V1_8821C \ + (BIT_MASK_RARF_RC8_V1_8821C << BIT_SHIFT_RARF_RC8_V1_8821C) +#define BIT_CLEAR_RARF_RC8_V1_8821C(x) ((x) & (~BITS_RARF_RC8_V1_8821C)) +#define BIT_GET_RARF_RC8_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_V1_8821C) & BIT_MASK_RARF_RC8_V1_8821C) +#define BIT_SET_RARF_RC8_V1_8821C(x, v) \ + (BIT_CLEAR_RARF_RC8_V1_8821C(x) | BIT_RARF_RC8_V1_8821C(v)) + +#define BIT_SHIFT_RARF_RC7_V1_8821C 16 +#define BIT_MASK_RARF_RC7_V1_8821C 0x1f +#define BIT_RARF_RC7_V1_8821C(x) \ + (((x) & BIT_MASK_RARF_RC7_V1_8821C) << BIT_SHIFT_RARF_RC7_V1_8821C) +#define BITS_RARF_RC7_V1_8821C \ + (BIT_MASK_RARF_RC7_V1_8821C << BIT_SHIFT_RARF_RC7_V1_8821C) +#define BIT_CLEAR_RARF_RC7_V1_8821C(x) ((x) & (~BITS_RARF_RC7_V1_8821C)) +#define BIT_GET_RARF_RC7_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_V1_8821C) & BIT_MASK_RARF_RC7_V1_8821C) +#define BIT_SET_RARF_RC7_V1_8821C(x, v) \ + (BIT_CLEAR_RARF_RC7_V1_8821C(x) | BIT_RARF_RC7_V1_8821C(v)) + +#define BIT_SHIFT_RARF_RC6_V1_8821C 8 +#define BIT_MASK_RARF_RC6_V1_8821C 0x1f +#define BIT_RARF_RC6_V1_8821C(x) \ + (((x) & BIT_MASK_RARF_RC6_V1_8821C) << BIT_SHIFT_RARF_RC6_V1_8821C) +#define BITS_RARF_RC6_V1_8821C \ + (BIT_MASK_RARF_RC6_V1_8821C << BIT_SHIFT_RARF_RC6_V1_8821C) +#define BIT_CLEAR_RARF_RC6_V1_8821C(x) ((x) & (~BITS_RARF_RC6_V1_8821C)) +#define BIT_GET_RARF_RC6_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_V1_8821C) & BIT_MASK_RARF_RC6_V1_8821C) +#define BIT_SET_RARF_RC6_V1_8821C(x, v) \ + (BIT_CLEAR_RARF_RC6_V1_8821C(x) | BIT_RARF_RC6_V1_8821C(v)) + +#define BIT_SHIFT_RARF_RC5_V1_8821C 0 +#define BIT_MASK_RARF_RC5_V1_8821C 0x1f +#define BIT_RARF_RC5_V1_8821C(x) \ + (((x) & BIT_MASK_RARF_RC5_V1_8821C) << BIT_SHIFT_RARF_RC5_V1_8821C) +#define BITS_RARF_RC5_V1_8821C \ + (BIT_MASK_RARF_RC5_V1_8821C << BIT_SHIFT_RARF_RC5_V1_8821C) +#define BIT_CLEAR_RARF_RC5_V1_8821C(x) ((x) & (~BITS_RARF_RC5_V1_8821C)) +#define BIT_GET_RARF_RC5_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_V1_8821C) & BIT_MASK_RARF_RC5_V1_8821C) +#define BIT_SET_RARF_RC5_V1_8821C(x, v) \ + (BIT_CLEAR_RARF_RC5_V1_8821C(x) | BIT_RARF_RC5_V1_8821C(v)) /* 2 REG_RRSR_8821C */ #define BIT_SHIFT_RRSR_RSC_8821C 21 #define BIT_MASK_RRSR_RSC_8821C 0x3 -#define BIT_RRSR_RSC_8821C(x) (((x) & BIT_MASK_RRSR_RSC_8821C) << BIT_SHIFT_RRSR_RSC_8821C) -#define BIT_GET_RRSR_RSC_8821C(x) (((x) >> BIT_SHIFT_RRSR_RSC_8821C) & BIT_MASK_RRSR_RSC_8821C) - - -#define BIT_RRSR_BW_8821C BIT(20) +#define BIT_RRSR_RSC_8821C(x) \ + (((x) & BIT_MASK_RRSR_RSC_8821C) << BIT_SHIFT_RRSR_RSC_8821C) +#define BITS_RRSR_RSC_8821C \ + (BIT_MASK_RRSR_RSC_8821C << BIT_SHIFT_RRSR_RSC_8821C) +#define BIT_CLEAR_RRSR_RSC_8821C(x) ((x) & (~BITS_RRSR_RSC_8821C)) +#define BIT_GET_RRSR_RSC_8821C(x) \ + (((x) >> BIT_SHIFT_RRSR_RSC_8821C) & BIT_MASK_RRSR_RSC_8821C) +#define BIT_SET_RRSR_RSC_8821C(x, v) \ + (BIT_CLEAR_RRSR_RSC_8821C(x) | BIT_RRSR_RSC_8821C(v)) #define BIT_SHIFT_RRSC_BITMAP_8821C 0 #define BIT_MASK_RRSC_BITMAP_8821C 0xfffff -#define BIT_RRSC_BITMAP_8821C(x) (((x) & BIT_MASK_RRSC_BITMAP_8821C) << BIT_SHIFT_RRSC_BITMAP_8821C) -#define BIT_GET_RRSC_BITMAP_8821C(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8821C) & BIT_MASK_RRSC_BITMAP_8821C) - +#define BIT_RRSC_BITMAP_8821C(x) \ + (((x) & BIT_MASK_RRSC_BITMAP_8821C) << BIT_SHIFT_RRSC_BITMAP_8821C) +#define BITS_RRSC_BITMAP_8821C \ + (BIT_MASK_RRSC_BITMAP_8821C << BIT_SHIFT_RRSC_BITMAP_8821C) +#define BIT_CLEAR_RRSC_BITMAP_8821C(x) ((x) & (~BITS_RRSC_BITMAP_8821C)) +#define BIT_GET_RRSC_BITMAP_8821C(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP_8821C) & BIT_MASK_RRSC_BITMAP_8821C) +#define BIT_SET_RRSC_BITMAP_8821C(x, v) \ + (BIT_CLEAR_RRSC_BITMAP_8821C(x) | BIT_RRSC_BITMAP_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_ARFR0_8821C */ -#define BIT_SHIFT_ARFR0_V1_8821C 0 -#define BIT_MASK_ARFR0_V1_8821C 0xffffffffffffffffL -#define BIT_ARFR0_V1_8821C(x) (((x) & BIT_MASK_ARFR0_V1_8821C) << BIT_SHIFT_ARFR0_V1_8821C) -#define BIT_GET_ARFR0_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR0_V1_8821C) & BIT_MASK_ARFR0_V1_8821C) - - +#define BIT_SHIFT_ARFRL0_8821C 0 +#define BIT_MASK_ARFRL0_8821C 0xffffffffL +#define BIT_ARFRL0_8821C(x) \ + (((x) & BIT_MASK_ARFRL0_8821C) << BIT_SHIFT_ARFRL0_8821C) +#define BITS_ARFRL0_8821C (BIT_MASK_ARFRL0_8821C << BIT_SHIFT_ARFRL0_8821C) +#define BIT_CLEAR_ARFRL0_8821C(x) ((x) & (~BITS_ARFRL0_8821C)) +#define BIT_GET_ARFRL0_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL0_8821C) & BIT_MASK_ARFRL0_8821C) +#define BIT_SET_ARFRL0_8821C(x, v) \ + (BIT_CLEAR_ARFRL0_8821C(x) | BIT_ARFRL0_8821C(v)) + +/* 2 REG_ARFRH0_8821C */ + +#define BIT_SHIFT_ARFRH0_8821C 0 +#define BIT_MASK_ARFRH0_8821C 0xffffffffL +#define BIT_ARFRH0_8821C(x) \ + (((x) & BIT_MASK_ARFRH0_8821C) << BIT_SHIFT_ARFRH0_8821C) +#define BITS_ARFRH0_8821C (BIT_MASK_ARFRH0_8821C << BIT_SHIFT_ARFRH0_8821C) +#define BIT_CLEAR_ARFRH0_8821C(x) ((x) & (~BITS_ARFRH0_8821C)) +#define BIT_GET_ARFRH0_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH0_8821C) & BIT_MASK_ARFRH0_8821C) +#define BIT_SET_ARFRH0_8821C(x, v) \ + (BIT_CLEAR_ARFRH0_8821C(x) | BIT_ARFRH0_8821C(v)) /* 2 REG_ARFR1_V1_8821C */ -#define BIT_SHIFT_ARFR1_V1_8821C 0 -#define BIT_MASK_ARFR1_V1_8821C 0xffffffffffffffffL -#define BIT_ARFR1_V1_8821C(x) (((x) & BIT_MASK_ARFR1_V1_8821C) << BIT_SHIFT_ARFR1_V1_8821C) -#define BIT_GET_ARFR1_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR1_V1_8821C) & BIT_MASK_ARFR1_V1_8821C) - - +#define BIT_SHIFT_ARFRL1_8821C 0 +#define BIT_MASK_ARFRL1_8821C 0xffffffffL +#define BIT_ARFRL1_8821C(x) \ + (((x) & BIT_MASK_ARFRL1_8821C) << BIT_SHIFT_ARFRL1_8821C) +#define BITS_ARFRL1_8821C (BIT_MASK_ARFRL1_8821C << BIT_SHIFT_ARFRL1_8821C) +#define BIT_CLEAR_ARFRL1_8821C(x) ((x) & (~BITS_ARFRL1_8821C)) +#define BIT_GET_ARFRL1_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL1_8821C) & BIT_MASK_ARFRL1_8821C) +#define BIT_SET_ARFRL1_8821C(x, v) \ + (BIT_CLEAR_ARFRL1_8821C(x) | BIT_ARFRL1_8821C(v)) + +/* 2 REG_ARFRH1_V1_8821C */ + +#define BIT_SHIFT_ARFRH1_8821C 0 +#define BIT_MASK_ARFRH1_8821C 0xffffffffL +#define BIT_ARFRH1_8821C(x) \ + (((x) & BIT_MASK_ARFRH1_8821C) << BIT_SHIFT_ARFRH1_8821C) +#define BITS_ARFRH1_8821C (BIT_MASK_ARFRH1_8821C << BIT_SHIFT_ARFRH1_8821C) +#define BIT_CLEAR_ARFRH1_8821C(x) ((x) & (~BITS_ARFRH1_8821C)) +#define BIT_GET_ARFRH1_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH1_8821C) & BIT_MASK_ARFRH1_8821C) +#define BIT_SET_ARFRH1_8821C(x, v) \ + (BIT_CLEAR_ARFRH1_8821C(x) | BIT_ARFRH1_8821C(v)) /* 2 REG_CCK_CHECK_8821C */ #define BIT_CHECK_CCK_EN_8821C BIT(7) @@ -5814,28 +9561,50 @@ #define BIT_SHIFT_AMPDU_MAX_TIME_8821C 0 #define BIT_MASK_AMPDU_MAX_TIME_8821C 0xff -#define BIT_AMPDU_MAX_TIME_8821C(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8821C) << BIT_SHIFT_AMPDU_MAX_TIME_8821C) -#define BIT_GET_AMPDU_MAX_TIME_8821C(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8821C) & BIT_MASK_AMPDU_MAX_TIME_8821C) - - +#define BIT_AMPDU_MAX_TIME_8821C(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME_8821C) \ + << BIT_SHIFT_AMPDU_MAX_TIME_8821C) +#define BITS_AMPDU_MAX_TIME_8821C \ + (BIT_MASK_AMPDU_MAX_TIME_8821C << BIT_SHIFT_AMPDU_MAX_TIME_8821C) +#define BIT_CLEAR_AMPDU_MAX_TIME_8821C(x) ((x) & (~BITS_AMPDU_MAX_TIME_8821C)) +#define BIT_GET_AMPDU_MAX_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8821C) & \ + BIT_MASK_AMPDU_MAX_TIME_8821C) +#define BIT_SET_AMPDU_MAX_TIME_8821C(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME_8821C(x) | BIT_AMPDU_MAX_TIME_8821C(v)) /* 2 REG_BCNQ1_BDNY_V1_8821C */ #define BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C 0 #define BIT_MASK_BCNQ1_PGBNDY_V1_8821C 0xfff -#define BIT_BCNQ1_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) -#define BIT_GET_BCNQ1_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C) - - +#define BIT_BCNQ1_PGBNDY_V1_8821C(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C) \ + << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) +#define BITS_BCNQ1_PGBNDY_V1_8821C \ + (BIT_MASK_BCNQ1_PGBNDY_V1_8821C << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) +#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8821C(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8821C)) +#define BIT_GET_BCNQ1_PGBNDY_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) & \ + BIT_MASK_BCNQ1_PGBNDY_V1_8821C) +#define BIT_SET_BCNQ1_PGBNDY_V1_8821C(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY_V1_8821C(x) | BIT_BCNQ1_PGBNDY_V1_8821C(v)) /* 2 REG_AMPDU_MAX_LENGTH_8821C */ #define BIT_SHIFT_AMPDU_MAX_LENGTH_8821C 0 #define BIT_MASK_AMPDU_MAX_LENGTH_8821C 0xffffffffL -#define BIT_AMPDU_MAX_LENGTH_8821C(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8821C) << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) -#define BIT_GET_AMPDU_MAX_LENGTH_8821C(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) & BIT_MASK_AMPDU_MAX_LENGTH_8821C) - - +#define BIT_AMPDU_MAX_LENGTH_8821C(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8821C) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) +#define BITS_AMPDU_MAX_LENGTH_8821C \ + (BIT_MASK_AMPDU_MAX_LENGTH_8821C << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_8821C(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_8821C)) +#define BIT_GET_AMPDU_MAX_LENGTH_8821C(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) & \ + BIT_MASK_AMPDU_MAX_LENGTH_8821C) +#define BIT_SET_AMPDU_MAX_LENGTH_8821C(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_8821C(x) | BIT_AMPDU_MAX_LENGTH_8821C(v)) /* 2 REG_ACQ_STOP_8821C */ #define BIT_AC7Q_STOP_8821C BIT(7) @@ -5851,10 +9620,17 @@ #define BIT_SHIFT_R_NDPA_RATE_V1_8821C 0 #define BIT_MASK_R_NDPA_RATE_V1_8821C 0xff -#define BIT_R_NDPA_RATE_V1_8821C(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8821C) << BIT_SHIFT_R_NDPA_RATE_V1_8821C) -#define BIT_GET_R_NDPA_RATE_V1_8821C(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8821C) & BIT_MASK_R_NDPA_RATE_V1_8821C) - - +#define BIT_R_NDPA_RATE_V1_8821C(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1_8821C) \ + << BIT_SHIFT_R_NDPA_RATE_V1_8821C) +#define BITS_R_NDPA_RATE_V1_8821C \ + (BIT_MASK_R_NDPA_RATE_V1_8821C << BIT_SHIFT_R_NDPA_RATE_V1_8821C) +#define BIT_CLEAR_R_NDPA_RATE_V1_8821C(x) ((x) & (~BITS_R_NDPA_RATE_V1_8821C)) +#define BIT_GET_R_NDPA_RATE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8821C) & \ + BIT_MASK_R_NDPA_RATE_V1_8821C) +#define BIT_SET_R_NDPA_RATE_V1_8821C(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1_8821C(x) | BIT_R_NDPA_RATE_V1_8821C(v)) /* 2 REG_TX_HANG_CTRL_8821C */ #define BIT_R_EN_GNT_BT_AWAKE_8821C BIT(3) @@ -5867,20 +9643,29 @@ #define BIT_SHIFT_BW_SIGTA_8821C 3 #define BIT_MASK_BW_SIGTA_8821C 0x3 -#define BIT_BW_SIGTA_8821C(x) (((x) & BIT_MASK_BW_SIGTA_8821C) << BIT_SHIFT_BW_SIGTA_8821C) -#define BIT_GET_BW_SIGTA_8821C(x) (((x) >> BIT_SHIFT_BW_SIGTA_8821C) & BIT_MASK_BW_SIGTA_8821C) - +#define BIT_BW_SIGTA_8821C(x) \ + (((x) & BIT_MASK_BW_SIGTA_8821C) << BIT_SHIFT_BW_SIGTA_8821C) +#define BITS_BW_SIGTA_8821C \ + (BIT_MASK_BW_SIGTA_8821C << BIT_SHIFT_BW_SIGTA_8821C) +#define BIT_CLEAR_BW_SIGTA_8821C(x) ((x) & (~BITS_BW_SIGTA_8821C)) +#define BIT_GET_BW_SIGTA_8821C(x) \ + (((x) >> BIT_SHIFT_BW_SIGTA_8821C) & BIT_MASK_BW_SIGTA_8821C) +#define BIT_SET_BW_SIGTA_8821C(x, v) \ + (BIT_CLEAR_BW_SIGTA_8821C(x) | BIT_BW_SIGTA_8821C(v)) #define BIT_EN_BAR_SIGTA_8821C BIT(2) #define BIT_SHIFT_R_NDPA_BW_8821C 0 #define BIT_MASK_R_NDPA_BW_8821C 0x3 -#define BIT_R_NDPA_BW_8821C(x) (((x) & BIT_MASK_R_NDPA_BW_8821C) << BIT_SHIFT_R_NDPA_BW_8821C) -#define BIT_GET_R_NDPA_BW_8821C(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8821C) & BIT_MASK_R_NDPA_BW_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_R_NDPA_BW_8821C(x) \ + (((x) & BIT_MASK_R_NDPA_BW_8821C) << BIT_SHIFT_R_NDPA_BW_8821C) +#define BITS_R_NDPA_BW_8821C \ + (BIT_MASK_R_NDPA_BW_8821C << BIT_SHIFT_R_NDPA_BW_8821C) +#define BIT_CLEAR_R_NDPA_BW_8821C(x) ((x) & (~BITS_R_NDPA_BW_8821C)) +#define BIT_GET_R_NDPA_BW_8821C(x) \ + (((x) >> BIT_SHIFT_R_NDPA_BW_8821C) & BIT_MASK_R_NDPA_BW_8821C) +#define BIT_SET_R_NDPA_BW_8821C(x, v) \ + (BIT_CLEAR_R_NDPA_BW_8821C(x) | BIT_R_NDPA_BW_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -5888,213 +9673,408 @@ #define BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C 0 #define BIT_MASK_RD_RESP_PKT_TH_V1_8821C 0x3f -#define BIT_RD_RESP_PKT_TH_V1_8821C(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) -#define BIT_GET_RD_RESP_PKT_TH_V1_8821C(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C) - - +#define BIT_RD_RESP_PKT_TH_V1_8821C(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C) \ + << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) +#define BITS_RD_RESP_PKT_TH_V1_8821C \ + (BIT_MASK_RD_RESP_PKT_TH_V1_8821C << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8821C(x) \ + ((x) & (~BITS_RD_RESP_PKT_TH_V1_8821C)) +#define BIT_GET_RD_RESP_PKT_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) & \ + BIT_MASK_RD_RESP_PKT_TH_V1_8821C) +#define BIT_SET_RD_RESP_PKT_TH_V1_8821C(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1_8821C(x) | BIT_RD_RESP_PKT_TH_V1_8821C(v)) /* 2 REG_CMDQ_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C 25 #define BIT_MASK_QUEUEMACID_CMDQ_V1_8821C 0x7f -#define BIT_QUEUEMACID_CMDQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) -#define BIT_GET_QUEUEMACID_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) - - +#define BIT_QUEUEMACID_CMDQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) +#define BITS_QUEUEMACID_CMDQ_V1_8821C \ + (BIT_MASK_QUEUEMACID_CMDQ_V1_8821C \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_CMDQ_V1_8821C)) +#define BIT_GET_QUEUEMACID_CMDQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) & \ + BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) +#define BIT_SET_QUEUEMACID_CMDQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_CMDQ_V1_8821C(x) | \ + BIT_QUEUEMACID_CMDQ_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C 23 #define BIT_MASK_QUEUEAC_CMDQ_V1_8821C 0x3 -#define BIT_QUEUEAC_CMDQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) -#define BIT_GET_QUEUEAC_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) - +#define BIT_QUEUEAC_CMDQ_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) \ + << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) +#define BITS_QUEUEAC_CMDQ_V1_8821C \ + (BIT_MASK_QUEUEAC_CMDQ_V1_8821C << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) +#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8821C)) +#define BIT_GET_QUEUEAC_CMDQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) & \ + BIT_MASK_QUEUEAC_CMDQ_V1_8821C) +#define BIT_SET_QUEUEAC_CMDQ_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_CMDQ_V1_8821C(x) | BIT_QUEUEAC_CMDQ_V1_8821C(v)) #define BIT_TIDEMPTY_CMDQ_V1_8821C BIT(22) -#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C 11 -#define BIT_MASK_TAIL_PKT_CMDQ_V2_8821C 0x7ff -#define BIT_TAIL_PKT_CMDQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C) -#define BIT_GET_TAIL_PKT_CMDQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C) & BIT_MASK_TAIL_PKT_CMDQ_V2_8821C) - - +#define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_Q4_V2_8821C 0x7ff +#define BIT_TAIL_PKT_Q4_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) +#define BITS_TAIL_PKT_Q4_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q4_V2_8821C << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8821C) +#define BIT_SET_TAIL_PKT_Q4_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) | BIT_TAIL_PKT_Q4_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C 0 #define BIT_MASK_HEAD_PKT_CMDQ_V1_8821C 0x7ff -#define BIT_HEAD_PKT_CMDQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) -#define BIT_GET_HEAD_PKT_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) - - +#define BIT_HEAD_PKT_CMDQ_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) +#define BITS_HEAD_PKT_CMDQ_V1_8821C \ + (BIT_MASK_HEAD_PKT_CMDQ_V1_8821C << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8821C(x) \ + ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8821C)) +#define BIT_GET_HEAD_PKT_CMDQ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) & \ + BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) +#define BIT_SET_HEAD_PKT_CMDQ_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8821C(x) | BIT_HEAD_PKT_CMDQ_V1_8821C(v)) /* 2 REG_Q4_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q4_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q4_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q4_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) -#define BIT_GET_QUEUEMACID_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) & BIT_MASK_QUEUEMACID_Q4_V1_8821C) - - +#define BIT_QUEUEMACID_Q4_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) +#define BITS_QUEUEMACID_Q4_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q4_V1_8821C << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q4_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q4_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q4_V1_8821C) +#define BIT_SET_QUEUEMACID_Q4_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q4_V1_8821C(x) | BIT_QUEUEMACID_Q4_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q4_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q4_V1_8821C 0x3 -#define BIT_QUEUEAC_Q4_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8821C) << BIT_SHIFT_QUEUEAC_Q4_V1_8821C) -#define BIT_GET_QUEUEAC_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8821C) & BIT_MASK_QUEUEAC_Q4_V1_8821C) - +#define BIT_QUEUEAC_Q4_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q4_V1_8821C) << BIT_SHIFT_QUEUEAC_Q4_V1_8821C) +#define BITS_QUEUEAC_Q4_V1_8821C \ + (BIT_MASK_QUEUEAC_Q4_V1_8821C << BIT_SHIFT_QUEUEAC_Q4_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q4_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8821C)) +#define BIT_GET_QUEUEAC_Q4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8821C) & BIT_MASK_QUEUEAC_Q4_V1_8821C) +#define BIT_SET_QUEUEAC_Q4_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q4_V1_8821C(x) | BIT_QUEUEAC_Q4_V1_8821C(v)) #define BIT_TIDEMPTY_Q4_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q4_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q4_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) -#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) - - +#define BIT_TAIL_PKT_Q4_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) +#define BITS_TAIL_PKT_Q4_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q4_V2_8821C << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8821C) +#define BIT_SET_TAIL_PKT_Q4_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) | BIT_TAIL_PKT_Q4_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q4_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q4_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q4_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) -#define BIT_GET_HEAD_PKT_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) - - +#define BIT_HEAD_PKT_Q4_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) +#define BITS_HEAD_PKT_Q4_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q4_V1_8821C << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q4_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q4_V1_8821C) +#define BIT_SET_HEAD_PKT_Q4_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4_V1_8821C(x) | BIT_HEAD_PKT_Q4_V1_8821C(v)) /* 2 REG_Q5_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q5_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q5_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q5_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) -#define BIT_GET_QUEUEMACID_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) & BIT_MASK_QUEUEMACID_Q5_V1_8821C) - - +#define BIT_QUEUEMACID_Q5_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) +#define BITS_QUEUEMACID_Q5_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q5_V1_8821C << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q5_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q5_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q5_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q5_V1_8821C) +#define BIT_SET_QUEUEMACID_Q5_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q5_V1_8821C(x) | BIT_QUEUEMACID_Q5_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q5_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q5_V1_8821C 0x3 -#define BIT_QUEUEAC_Q5_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8821C) << BIT_SHIFT_QUEUEAC_Q5_V1_8821C) -#define BIT_GET_QUEUEAC_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8821C) & BIT_MASK_QUEUEAC_Q5_V1_8821C) - +#define BIT_QUEUEAC_Q5_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q5_V1_8821C) << BIT_SHIFT_QUEUEAC_Q5_V1_8821C) +#define BITS_QUEUEAC_Q5_V1_8821C \ + (BIT_MASK_QUEUEAC_Q5_V1_8821C << BIT_SHIFT_QUEUEAC_Q5_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q5_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8821C)) +#define BIT_GET_QUEUEAC_Q5_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8821C) & BIT_MASK_QUEUEAC_Q5_V1_8821C) +#define BIT_SET_QUEUEAC_Q5_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q5_V1_8821C(x) | BIT_QUEUEAC_Q5_V1_8821C(v)) #define BIT_TIDEMPTY_Q5_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q5_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q5_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q5_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) -#define BIT_GET_TAIL_PKT_Q5_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) & BIT_MASK_TAIL_PKT_Q5_V2_8821C) - - +#define BIT_TAIL_PKT_Q5_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) +#define BITS_TAIL_PKT_Q5_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q5_V2_8821C << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q5_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q5_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q5_V2_8821C) +#define BIT_SET_TAIL_PKT_Q5_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V2_8821C(x) | BIT_TAIL_PKT_Q5_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q5_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q5_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q5_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) -#define BIT_GET_HEAD_PKT_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) - - +#define BIT_HEAD_PKT_Q5_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) +#define BITS_HEAD_PKT_Q5_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q5_V1_8821C << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q5_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q5_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q5_V1_8821C) +#define BIT_SET_HEAD_PKT_Q5_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5_V1_8821C(x) | BIT_HEAD_PKT_Q5_V1_8821C(v)) /* 2 REG_Q6_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q6_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q6_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q6_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) -#define BIT_GET_QUEUEMACID_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) & BIT_MASK_QUEUEMACID_Q6_V1_8821C) - - +#define BIT_QUEUEMACID_Q6_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) +#define BITS_QUEUEMACID_Q6_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q6_V1_8821C << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q6_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q6_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q6_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q6_V1_8821C) +#define BIT_SET_QUEUEMACID_Q6_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q6_V1_8821C(x) | BIT_QUEUEMACID_Q6_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q6_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q6_V1_8821C 0x3 -#define BIT_QUEUEAC_Q6_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8821C) << BIT_SHIFT_QUEUEAC_Q6_V1_8821C) -#define BIT_GET_QUEUEAC_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8821C) & BIT_MASK_QUEUEAC_Q6_V1_8821C) - +#define BIT_QUEUEAC_Q6_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q6_V1_8821C) << BIT_SHIFT_QUEUEAC_Q6_V1_8821C) +#define BITS_QUEUEAC_Q6_V1_8821C \ + (BIT_MASK_QUEUEAC_Q6_V1_8821C << BIT_SHIFT_QUEUEAC_Q6_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q6_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8821C)) +#define BIT_GET_QUEUEAC_Q6_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8821C) & BIT_MASK_QUEUEAC_Q6_V1_8821C) +#define BIT_SET_QUEUEAC_Q6_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q6_V1_8821C(x) | BIT_QUEUEAC_Q6_V1_8821C(v)) #define BIT_TIDEMPTY_Q6_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q6_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q6_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q6_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) -#define BIT_GET_TAIL_PKT_Q6_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) & BIT_MASK_TAIL_PKT_Q6_V2_8821C) - - +#define BIT_TAIL_PKT_Q6_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) +#define BITS_TAIL_PKT_Q6_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q6_V2_8821C << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q6_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q6_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q6_V2_8821C) +#define BIT_SET_TAIL_PKT_Q6_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V2_8821C(x) | BIT_TAIL_PKT_Q6_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q6_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q6_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q6_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) -#define BIT_GET_HEAD_PKT_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) - - +#define BIT_HEAD_PKT_Q6_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) +#define BITS_HEAD_PKT_Q6_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q6_V1_8821C << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q6_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q6_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q6_V1_8821C) +#define BIT_SET_HEAD_PKT_Q6_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6_V1_8821C(x) | BIT_HEAD_PKT_Q6_V1_8821C(v)) /* 2 REG_Q7_INFO_8821C */ #define BIT_SHIFT_QUEUEMACID_Q7_V1_8821C 25 #define BIT_MASK_QUEUEMACID_Q7_V1_8821C 0x7f -#define BIT_QUEUEMACID_Q7_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) -#define BIT_GET_QUEUEMACID_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) & BIT_MASK_QUEUEMACID_Q7_V1_8821C) - - +#define BIT_QUEUEMACID_Q7_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8821C) \ + << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) +#define BITS_QUEUEMACID_Q7_V1_8821C \ + (BIT_MASK_QUEUEMACID_Q7_V1_8821C << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) +#define BIT_CLEAR_QUEUEMACID_Q7_V1_8821C(x) \ + ((x) & (~BITS_QUEUEMACID_Q7_V1_8821C)) +#define BIT_GET_QUEUEMACID_Q7_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) & \ + BIT_MASK_QUEUEMACID_Q7_V1_8821C) +#define BIT_SET_QUEUEMACID_Q7_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q7_V1_8821C(x) | BIT_QUEUEMACID_Q7_V1_8821C(v)) #define BIT_SHIFT_QUEUEAC_Q7_V1_8821C 23 #define BIT_MASK_QUEUEAC_Q7_V1_8821C 0x3 -#define BIT_QUEUEAC_Q7_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8821C) << BIT_SHIFT_QUEUEAC_Q7_V1_8821C) -#define BIT_GET_QUEUEAC_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8821C) & BIT_MASK_QUEUEAC_Q7_V1_8821C) - +#define BIT_QUEUEAC_Q7_V1_8821C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q7_V1_8821C) << BIT_SHIFT_QUEUEAC_Q7_V1_8821C) +#define BITS_QUEUEAC_Q7_V1_8821C \ + (BIT_MASK_QUEUEAC_Q7_V1_8821C << BIT_SHIFT_QUEUEAC_Q7_V1_8821C) +#define BIT_CLEAR_QUEUEAC_Q7_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8821C)) +#define BIT_GET_QUEUEAC_Q7_V1_8821C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8821C) & BIT_MASK_QUEUEAC_Q7_V1_8821C) +#define BIT_SET_QUEUEAC_Q7_V1_8821C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q7_V1_8821C(x) | BIT_QUEUEAC_Q7_V1_8821C(v)) #define BIT_TIDEMPTY_Q7_V1_8821C BIT(22) #define BIT_SHIFT_TAIL_PKT_Q7_V2_8821C 11 #define BIT_MASK_TAIL_PKT_Q7_V2_8821C 0x7ff -#define BIT_TAIL_PKT_Q7_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) -#define BIT_GET_TAIL_PKT_Q7_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) & BIT_MASK_TAIL_PKT_Q7_V2_8821C) - - +#define BIT_TAIL_PKT_Q7_V2_8821C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8821C) \ + << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) +#define BITS_TAIL_PKT_Q7_V2_8821C \ + (BIT_MASK_TAIL_PKT_Q7_V2_8821C << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) +#define BIT_CLEAR_TAIL_PKT_Q7_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8821C)) +#define BIT_GET_TAIL_PKT_Q7_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) & \ + BIT_MASK_TAIL_PKT_Q7_V2_8821C) +#define BIT_SET_TAIL_PKT_Q7_V2_8821C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V2_8821C(x) | BIT_TAIL_PKT_Q7_V2_8821C(v)) #define BIT_SHIFT_HEAD_PKT_Q7_V1_8821C 0 #define BIT_MASK_HEAD_PKT_Q7_V1_8821C 0x7ff -#define BIT_HEAD_PKT_Q7_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) -#define BIT_GET_HEAD_PKT_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) - - +#define BIT_HEAD_PKT_Q7_V1_8821C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) \ + << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) +#define BITS_HEAD_PKT_Q7_V1_8821C \ + (BIT_MASK_HEAD_PKT_Q7_V1_8821C << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) +#define BIT_CLEAR_HEAD_PKT_Q7_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8821C)) +#define BIT_GET_HEAD_PKT_Q7_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) & \ + BIT_MASK_HEAD_PKT_Q7_V1_8821C) +#define BIT_SET_HEAD_PKT_Q7_V1_8821C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7_V1_8821C(x) | BIT_HEAD_PKT_Q7_V1_8821C(v)) /* 2 REG_WMAC_LBK_BUF_HD_V1_8821C */ #define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C 0 #define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C 0xfff -#define BIT_WMAC_LBK_BUF_HEAD_V1_8821C(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) -#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8821C(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) - - +#define BIT_WMAC_LBK_BUF_HEAD_V1_8821C(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) +#define BITS_WMAC_LBK_BUF_HEAD_V1_8821C \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8821C(x) \ + ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8821C)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8821C(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8821C(x) | \ + BIT_WMAC_LBK_BUF_HEAD_V1_8821C(v)) /* 2 REG_MGQ_BDNY_V1_8821C */ #define BIT_SHIFT_MGQ_PGBNDY_V1_8821C 0 #define BIT_MASK_MGQ_PGBNDY_V1_8821C 0xfff -#define BIT_MGQ_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8821C) << BIT_SHIFT_MGQ_PGBNDY_V1_8821C) -#define BIT_GET_MGQ_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8821C) & BIT_MASK_MGQ_PGBNDY_V1_8821C) - - +#define BIT_MGQ_PGBNDY_V1_8821C(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1_8821C) << BIT_SHIFT_MGQ_PGBNDY_V1_8821C) +#define BITS_MGQ_PGBNDY_V1_8821C \ + (BIT_MASK_MGQ_PGBNDY_V1_8821C << BIT_SHIFT_MGQ_PGBNDY_V1_8821C) +#define BIT_CLEAR_MGQ_PGBNDY_V1_8821C(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8821C)) +#define BIT_GET_MGQ_PGBNDY_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8821C) & BIT_MASK_MGQ_PGBNDY_V1_8821C) +#define BIT_SET_MGQ_PGBNDY_V1_8821C(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1_8821C(x) | BIT_MGQ_PGBNDY_V1_8821C(v)) /* 2 REG_TXRPT_CTRL_8821C */ #define BIT_SHIFT_TRXRPT_TIMER_TH_8821C 24 #define BIT_MASK_TRXRPT_TIMER_TH_8821C 0xff -#define BIT_TRXRPT_TIMER_TH_8821C(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8821C) << BIT_SHIFT_TRXRPT_TIMER_TH_8821C) -#define BIT_GET_TRXRPT_TIMER_TH_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8821C) & BIT_MASK_TRXRPT_TIMER_TH_8821C) - - +#define BIT_TRXRPT_TIMER_TH_8821C(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH_8821C) \ + << BIT_SHIFT_TRXRPT_TIMER_TH_8821C) +#define BITS_TRXRPT_TIMER_TH_8821C \ + (BIT_MASK_TRXRPT_TIMER_TH_8821C << BIT_SHIFT_TRXRPT_TIMER_TH_8821C) +#define BIT_CLEAR_TRXRPT_TIMER_TH_8821C(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8821C)) +#define BIT_GET_TRXRPT_TIMER_TH_8821C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8821C) & \ + BIT_MASK_TRXRPT_TIMER_TH_8821C) +#define BIT_SET_TRXRPT_TIMER_TH_8821C(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH_8821C(x) | BIT_TRXRPT_TIMER_TH_8821C(v)) #define BIT_SHIFT_TRXRPT_LEN_TH_8821C 16 #define BIT_MASK_TRXRPT_LEN_TH_8821C 0xff -#define BIT_TRXRPT_LEN_TH_8821C(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8821C) << BIT_SHIFT_TRXRPT_LEN_TH_8821C) -#define BIT_GET_TRXRPT_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8821C) & BIT_MASK_TRXRPT_LEN_TH_8821C) - - +#define BIT_TRXRPT_LEN_TH_8821C(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH_8821C) << BIT_SHIFT_TRXRPT_LEN_TH_8821C) +#define BITS_TRXRPT_LEN_TH_8821C \ + (BIT_MASK_TRXRPT_LEN_TH_8821C << BIT_SHIFT_TRXRPT_LEN_TH_8821C) +#define BIT_CLEAR_TRXRPT_LEN_TH_8821C(x) ((x) & (~BITS_TRXRPT_LEN_TH_8821C)) +#define BIT_GET_TRXRPT_LEN_TH_8821C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8821C) & BIT_MASK_TRXRPT_LEN_TH_8821C) +#define BIT_SET_TRXRPT_LEN_TH_8821C(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH_8821C(x) | BIT_TRXRPT_LEN_TH_8821C(v)) #define BIT_SHIFT_TRXRPT_READ_PTR_8821C 8 #define BIT_MASK_TRXRPT_READ_PTR_8821C 0xff -#define BIT_TRXRPT_READ_PTR_8821C(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8821C) << BIT_SHIFT_TRXRPT_READ_PTR_8821C) -#define BIT_GET_TRXRPT_READ_PTR_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8821C) & BIT_MASK_TRXRPT_READ_PTR_8821C) - - +#define BIT_TRXRPT_READ_PTR_8821C(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR_8821C) \ + << BIT_SHIFT_TRXRPT_READ_PTR_8821C) +#define BITS_TRXRPT_READ_PTR_8821C \ + (BIT_MASK_TRXRPT_READ_PTR_8821C << BIT_SHIFT_TRXRPT_READ_PTR_8821C) +#define BIT_CLEAR_TRXRPT_READ_PTR_8821C(x) ((x) & (~BITS_TRXRPT_READ_PTR_8821C)) +#define BIT_GET_TRXRPT_READ_PTR_8821C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8821C) & \ + BIT_MASK_TRXRPT_READ_PTR_8821C) +#define BIT_SET_TRXRPT_READ_PTR_8821C(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR_8821C(x) | BIT_TRXRPT_READ_PTR_8821C(v)) #define BIT_SHIFT_TRXRPT_WRITE_PTR_8821C 0 #define BIT_MASK_TRXRPT_WRITE_PTR_8821C 0xff -#define BIT_TRXRPT_WRITE_PTR_8821C(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) -#define BIT_GET_TRXRPT_WRITE_PTR_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) - - +#define BIT_TRXRPT_WRITE_PTR_8821C(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) \ + << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) +#define BITS_TRXRPT_WRITE_PTR_8821C \ + (BIT_MASK_TRXRPT_WRITE_PTR_8821C << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) +#define BIT_CLEAR_TRXRPT_WRITE_PTR_8821C(x) \ + ((x) & (~BITS_TRXRPT_WRITE_PTR_8821C)) +#define BIT_GET_TRXRPT_WRITE_PTR_8821C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) & \ + BIT_MASK_TRXRPT_WRITE_PTR_8821C) +#define BIT_SET_TRXRPT_WRITE_PTR_8821C(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR_8821C(x) | BIT_TRXRPT_WRITE_PTR_8821C(v)) /* 2 REG_INIRTS_RATE_SEL_8821C */ #define BIT_LEAG_RTS_BW_DUP_8821C BIT(5) @@ -6103,115 +10083,255 @@ #define BIT_SHIFT_BASIC_CFEND_RATE_8821C 0 #define BIT_MASK_BASIC_CFEND_RATE_8821C 0x1f -#define BIT_BASIC_CFEND_RATE_8821C(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8821C) << BIT_SHIFT_BASIC_CFEND_RATE_8821C) -#define BIT_GET_BASIC_CFEND_RATE_8821C(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8821C) & BIT_MASK_BASIC_CFEND_RATE_8821C) - - +#define BIT_BASIC_CFEND_RATE_8821C(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE_8821C) \ + << BIT_SHIFT_BASIC_CFEND_RATE_8821C) +#define BITS_BASIC_CFEND_RATE_8821C \ + (BIT_MASK_BASIC_CFEND_RATE_8821C << BIT_SHIFT_BASIC_CFEND_RATE_8821C) +#define BIT_CLEAR_BASIC_CFEND_RATE_8821C(x) \ + ((x) & (~BITS_BASIC_CFEND_RATE_8821C)) +#define BIT_GET_BASIC_CFEND_RATE_8821C(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8821C) & \ + BIT_MASK_BASIC_CFEND_RATE_8821C) +#define BIT_SET_BASIC_CFEND_RATE_8821C(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE_8821C(x) | BIT_BASIC_CFEND_RATE_8821C(v)) /* 2 REG_STBC_CFEND_RATE_8821C */ #define BIT_SHIFT_STBC_CFEND_RATE_8821C 0 #define BIT_MASK_STBC_CFEND_RATE_8821C 0x1f -#define BIT_STBC_CFEND_RATE_8821C(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8821C) << BIT_SHIFT_STBC_CFEND_RATE_8821C) -#define BIT_GET_STBC_CFEND_RATE_8821C(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8821C) & BIT_MASK_STBC_CFEND_RATE_8821C) - - +#define BIT_STBC_CFEND_RATE_8821C(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE_8821C) \ + << BIT_SHIFT_STBC_CFEND_RATE_8821C) +#define BITS_STBC_CFEND_RATE_8821C \ + (BIT_MASK_STBC_CFEND_RATE_8821C << BIT_SHIFT_STBC_CFEND_RATE_8821C) +#define BIT_CLEAR_STBC_CFEND_RATE_8821C(x) ((x) & (~BITS_STBC_CFEND_RATE_8821C)) +#define BIT_GET_STBC_CFEND_RATE_8821C(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8821C) & \ + BIT_MASK_STBC_CFEND_RATE_8821C) +#define BIT_SET_STBC_CFEND_RATE_8821C(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE_8821C(x) | BIT_STBC_CFEND_RATE_8821C(v)) /* 2 REG_DATA_SC_8821C */ #define BIT_SHIFT_TXSC_40M_8821C 4 #define BIT_MASK_TXSC_40M_8821C 0xf -#define BIT_TXSC_40M_8821C(x) (((x) & BIT_MASK_TXSC_40M_8821C) << BIT_SHIFT_TXSC_40M_8821C) -#define BIT_GET_TXSC_40M_8821C(x) (((x) >> BIT_SHIFT_TXSC_40M_8821C) & BIT_MASK_TXSC_40M_8821C) - - +#define BIT_TXSC_40M_8821C(x) \ + (((x) & BIT_MASK_TXSC_40M_8821C) << BIT_SHIFT_TXSC_40M_8821C) +#define BITS_TXSC_40M_8821C \ + (BIT_MASK_TXSC_40M_8821C << BIT_SHIFT_TXSC_40M_8821C) +#define BIT_CLEAR_TXSC_40M_8821C(x) ((x) & (~BITS_TXSC_40M_8821C)) +#define BIT_GET_TXSC_40M_8821C(x) \ + (((x) >> BIT_SHIFT_TXSC_40M_8821C) & BIT_MASK_TXSC_40M_8821C) +#define BIT_SET_TXSC_40M_8821C(x, v) \ + (BIT_CLEAR_TXSC_40M_8821C(x) | BIT_TXSC_40M_8821C(v)) #define BIT_SHIFT_TXSC_20M_8821C 0 #define BIT_MASK_TXSC_20M_8821C 0xf -#define BIT_TXSC_20M_8821C(x) (((x) & BIT_MASK_TXSC_20M_8821C) << BIT_SHIFT_TXSC_20M_8821C) -#define BIT_GET_TXSC_20M_8821C(x) (((x) >> BIT_SHIFT_TXSC_20M_8821C) & BIT_MASK_TXSC_20M_8821C) - - +#define BIT_TXSC_20M_8821C(x) \ + (((x) & BIT_MASK_TXSC_20M_8821C) << BIT_SHIFT_TXSC_20M_8821C) +#define BITS_TXSC_20M_8821C \ + (BIT_MASK_TXSC_20M_8821C << BIT_SHIFT_TXSC_20M_8821C) +#define BIT_CLEAR_TXSC_20M_8821C(x) ((x) & (~BITS_TXSC_20M_8821C)) +#define BIT_GET_TXSC_20M_8821C(x) \ + (((x) >> BIT_SHIFT_TXSC_20M_8821C) & BIT_MASK_TXSC_20M_8821C) +#define BIT_SET_TXSC_20M_8821C(x, v) \ + (BIT_CLEAR_TXSC_20M_8821C(x) | BIT_TXSC_20M_8821C(v)) /* 2 REG_MACID_SLEEP3_8821C */ #define BIT_SHIFT_MACID127_96_PKTSLEEP_8821C 0 #define BIT_MASK_MACID127_96_PKTSLEEP_8821C 0xffffffffL -#define BIT_MACID127_96_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8821C) << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) -#define BIT_GET_MACID127_96_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) & BIT_MASK_MACID127_96_PKTSLEEP_8821C) - - +#define BIT_MACID127_96_PKTSLEEP_8821C(x) \ + (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8821C) \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) +#define BITS_MACID127_96_PKTSLEEP_8821C \ + (BIT_MASK_MACID127_96_PKTSLEEP_8821C \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) +#define BIT_CLEAR_MACID127_96_PKTSLEEP_8821C(x) \ + ((x) & (~BITS_MACID127_96_PKTSLEEP_8821C)) +#define BIT_GET_MACID127_96_PKTSLEEP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) & \ + BIT_MASK_MACID127_96_PKTSLEEP_8821C) +#define BIT_SET_MACID127_96_PKTSLEEP_8821C(x, v) \ + (BIT_CLEAR_MACID127_96_PKTSLEEP_8821C(x) | \ + BIT_MACID127_96_PKTSLEEP_8821C(v)) /* 2 REG_MACID_SLEEP1_8821C */ #define BIT_SHIFT_MACID63_32_PKTSLEEP_8821C 0 #define BIT_MASK_MACID63_32_PKTSLEEP_8821C 0xffffffffL -#define BIT_MACID63_32_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8821C) << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) -#define BIT_GET_MACID63_32_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) & BIT_MASK_MACID63_32_PKTSLEEP_8821C) - - +#define BIT_MACID63_32_PKTSLEEP_8821C(x) \ + (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8821C) \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) +#define BITS_MACID63_32_PKTSLEEP_8821C \ + (BIT_MASK_MACID63_32_PKTSLEEP_8821C \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) +#define BIT_CLEAR_MACID63_32_PKTSLEEP_8821C(x) \ + ((x) & (~BITS_MACID63_32_PKTSLEEP_8821C)) +#define BIT_GET_MACID63_32_PKTSLEEP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) & \ + BIT_MASK_MACID63_32_PKTSLEEP_8821C) +#define BIT_SET_MACID63_32_PKTSLEEP_8821C(x, v) \ + (BIT_CLEAR_MACID63_32_PKTSLEEP_8821C(x) | \ + BIT_MACID63_32_PKTSLEEP_8821C(v)) /* 2 REG_ARFR2_V1_8821C */ -#define BIT_SHIFT_ARFR2_V1_8821C 0 -#define BIT_MASK_ARFR2_V1_8821C 0xffffffffffffffffL -#define BIT_ARFR2_V1_8821C(x) (((x) & BIT_MASK_ARFR2_V1_8821C) << BIT_SHIFT_ARFR2_V1_8821C) -#define BIT_GET_ARFR2_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR2_V1_8821C) & BIT_MASK_ARFR2_V1_8821C) - - +#define BIT_SHIFT_ARFRL2_8821C 0 +#define BIT_MASK_ARFRL2_8821C 0xffffffffL +#define BIT_ARFRL2_8821C(x) \ + (((x) & BIT_MASK_ARFRL2_8821C) << BIT_SHIFT_ARFRL2_8821C) +#define BITS_ARFRL2_8821C (BIT_MASK_ARFRL2_8821C << BIT_SHIFT_ARFRL2_8821C) +#define BIT_CLEAR_ARFRL2_8821C(x) ((x) & (~BITS_ARFRL2_8821C)) +#define BIT_GET_ARFRL2_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL2_8821C) & BIT_MASK_ARFRL2_8821C) +#define BIT_SET_ARFRL2_8821C(x, v) \ + (BIT_CLEAR_ARFRL2_8821C(x) | BIT_ARFRL2_8821C(v)) + +/* 2 REG_ARFRH2_V1_8821C */ + +#define BIT_SHIFT_ARFRH2_8821C 0 +#define BIT_MASK_ARFRH2_8821C 0xffffffffL +#define BIT_ARFRH2_8821C(x) \ + (((x) & BIT_MASK_ARFRH2_8821C) << BIT_SHIFT_ARFRH2_8821C) +#define BITS_ARFRH2_8821C (BIT_MASK_ARFRH2_8821C << BIT_SHIFT_ARFRH2_8821C) +#define BIT_CLEAR_ARFRH2_8821C(x) ((x) & (~BITS_ARFRH2_8821C)) +#define BIT_GET_ARFRH2_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH2_8821C) & BIT_MASK_ARFRH2_8821C) +#define BIT_SET_ARFRH2_8821C(x, v) \ + (BIT_CLEAR_ARFRH2_8821C(x) | BIT_ARFRH2_8821C(v)) /* 2 REG_ARFR3_V1_8821C */ -#define BIT_SHIFT_ARFR3_V1_8821C 0 -#define BIT_MASK_ARFR3_V1_8821C 0xffffffffffffffffL -#define BIT_ARFR3_V1_8821C(x) (((x) & BIT_MASK_ARFR3_V1_8821C) << BIT_SHIFT_ARFR3_V1_8821C) -#define BIT_GET_ARFR3_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR3_V1_8821C) & BIT_MASK_ARFR3_V1_8821C) - - +#define BIT_SHIFT_ARFRL3_8821C 0 +#define BIT_MASK_ARFRL3_8821C 0xffffffffL +#define BIT_ARFRL3_8821C(x) \ + (((x) & BIT_MASK_ARFRL3_8821C) << BIT_SHIFT_ARFRL3_8821C) +#define BITS_ARFRL3_8821C (BIT_MASK_ARFRL3_8821C << BIT_SHIFT_ARFRL3_8821C) +#define BIT_CLEAR_ARFRL3_8821C(x) ((x) & (~BITS_ARFRL3_8821C)) +#define BIT_GET_ARFRL3_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL3_8821C) & BIT_MASK_ARFRL3_8821C) +#define BIT_SET_ARFRL3_8821C(x, v) \ + (BIT_CLEAR_ARFRL3_8821C(x) | BIT_ARFRL3_8821C(v)) + +/* 2 REG_ARFRH3_V1_8821C */ + +#define BIT_SHIFT_ARFRH3_8821C 0 +#define BIT_MASK_ARFRH3_8821C 0xffffffffL +#define BIT_ARFRH3_8821C(x) \ + (((x) & BIT_MASK_ARFRH3_8821C) << BIT_SHIFT_ARFRH3_8821C) +#define BITS_ARFRH3_8821C (BIT_MASK_ARFRH3_8821C << BIT_SHIFT_ARFRH3_8821C) +#define BIT_CLEAR_ARFRH3_8821C(x) ((x) & (~BITS_ARFRH3_8821C)) +#define BIT_GET_ARFRH3_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH3_8821C) & BIT_MASK_ARFRH3_8821C) +#define BIT_SET_ARFRH3_8821C(x, v) \ + (BIT_CLEAR_ARFRH3_8821C(x) | BIT_ARFRH3_8821C(v)) /* 2 REG_ARFR4_8821C */ -#define BIT_SHIFT_ARFR4_8821C 0 -#define BIT_MASK_ARFR4_8821C 0xffffffffffffffffL -#define BIT_ARFR4_8821C(x) (((x) & BIT_MASK_ARFR4_8821C) << BIT_SHIFT_ARFR4_8821C) -#define BIT_GET_ARFR4_8821C(x) (((x) >> BIT_SHIFT_ARFR4_8821C) & BIT_MASK_ARFR4_8821C) - - +#define BIT_SHIFT_ARFRL4_8821C 0 +#define BIT_MASK_ARFRL4_8821C 0xffffffffL +#define BIT_ARFRL4_8821C(x) \ + (((x) & BIT_MASK_ARFRL4_8821C) << BIT_SHIFT_ARFRL4_8821C) +#define BITS_ARFRL4_8821C (BIT_MASK_ARFRL4_8821C << BIT_SHIFT_ARFRL4_8821C) +#define BIT_CLEAR_ARFRL4_8821C(x) ((x) & (~BITS_ARFRL4_8821C)) +#define BIT_GET_ARFRL4_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL4_8821C) & BIT_MASK_ARFRL4_8821C) +#define BIT_SET_ARFRL4_8821C(x, v) \ + (BIT_CLEAR_ARFRL4_8821C(x) | BIT_ARFRL4_8821C(v)) + +/* 2 REG_ARFRH4_8821C */ + +#define BIT_SHIFT_ARFRH4_8821C 0 +#define BIT_MASK_ARFRH4_8821C 0xffffffffL +#define BIT_ARFRH4_8821C(x) \ + (((x) & BIT_MASK_ARFRH4_8821C) << BIT_SHIFT_ARFRH4_8821C) +#define BITS_ARFRH4_8821C (BIT_MASK_ARFRH4_8821C << BIT_SHIFT_ARFRH4_8821C) +#define BIT_CLEAR_ARFRH4_8821C(x) ((x) & (~BITS_ARFRH4_8821C)) +#define BIT_GET_ARFRH4_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH4_8821C) & BIT_MASK_ARFRH4_8821C) +#define BIT_SET_ARFRH4_8821C(x, v) \ + (BIT_CLEAR_ARFRH4_8821C(x) | BIT_ARFRH4_8821C(v)) /* 2 REG_ARFR5_8821C */ -#define BIT_SHIFT_ARFR5_8821C 0 -#define BIT_MASK_ARFR5_8821C 0xffffffffffffffffL -#define BIT_ARFR5_8821C(x) (((x) & BIT_MASK_ARFR5_8821C) << BIT_SHIFT_ARFR5_8821C) -#define BIT_GET_ARFR5_8821C(x) (((x) >> BIT_SHIFT_ARFR5_8821C) & BIT_MASK_ARFR5_8821C) - - +#define BIT_SHIFT_ARFRL5_8821C 0 +#define BIT_MASK_ARFRL5_8821C 0xffffffffL +#define BIT_ARFRL5_8821C(x) \ + (((x) & BIT_MASK_ARFRL5_8821C) << BIT_SHIFT_ARFRL5_8821C) +#define BITS_ARFRL5_8821C (BIT_MASK_ARFRL5_8821C << BIT_SHIFT_ARFRL5_8821C) +#define BIT_CLEAR_ARFRL5_8821C(x) ((x) & (~BITS_ARFRL5_8821C)) +#define BIT_GET_ARFRL5_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRL5_8821C) & BIT_MASK_ARFRL5_8821C) +#define BIT_SET_ARFRL5_8821C(x, v) \ + (BIT_CLEAR_ARFRL5_8821C(x) | BIT_ARFRL5_8821C(v)) + +/* 2 REG_ARFRH5_8821C */ + +#define BIT_SHIFT_ARFRH5_8821C 0 +#define BIT_MASK_ARFRH5_8821C 0xffffffffL +#define BIT_ARFRH5_8821C(x) \ + (((x) & BIT_MASK_ARFRH5_8821C) << BIT_SHIFT_ARFRH5_8821C) +#define BITS_ARFRH5_8821C (BIT_MASK_ARFRH5_8821C << BIT_SHIFT_ARFRH5_8821C) +#define BIT_CLEAR_ARFRH5_8821C(x) ((x) & (~BITS_ARFRH5_8821C)) +#define BIT_GET_ARFRH5_8821C(x) \ + (((x) >> BIT_SHIFT_ARFRH5_8821C) & BIT_MASK_ARFRH5_8821C) +#define BIT_SET_ARFRH5_8821C(x, v) \ + (BIT_CLEAR_ARFRH5_8821C(x) | BIT_ARFRH5_8821C(v)) /* 2 REG_TXRPT_START_OFFSET_8821C */ #define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C 24 #define BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C 0xff -#define BIT_R_MUTAB_TXRPT_OFFSET_8821C(x) (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) -#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8821C(x) (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) - +#define BIT_R_MUTAB_TXRPT_OFFSET_8821C(x) \ + (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) \ + << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) +#define BITS_R_MUTAB_TXRPT_OFFSET_8821C \ + (BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C \ + << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) +#define BIT_CLEAR_R_MUTAB_TXRPT_OFFSET_8821C(x) \ + ((x) & (~BITS_R_MUTAB_TXRPT_OFFSET_8821C)) +#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) & \ + BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) +#define BIT_SET_R_MUTAB_TXRPT_OFFSET_8821C(x, v) \ + (BIT_CLEAR_R_MUTAB_TXRPT_OFFSET_8821C(x) | \ + BIT_R_MUTAB_TXRPT_OFFSET_8821C(v)) #define BIT__R_RPTFIFO_1K_8821C BIT(16) #define BIT_SHIFT_MACID_CTRL_OFFSET_8821C 8 #define BIT_MASK_MACID_CTRL_OFFSET_8821C 0xff -#define BIT_MACID_CTRL_OFFSET_8821C(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8821C) << BIT_SHIFT_MACID_CTRL_OFFSET_8821C) -#define BIT_GET_MACID_CTRL_OFFSET_8821C(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8821C) & BIT_MASK_MACID_CTRL_OFFSET_8821C) - - +#define BIT_MACID_CTRL_OFFSET_8821C(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_8821C) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_8821C) +#define BITS_MACID_CTRL_OFFSET_8821C \ + (BIT_MASK_MACID_CTRL_OFFSET_8821C << BIT_SHIFT_MACID_CTRL_OFFSET_8821C) +#define BIT_CLEAR_MACID_CTRL_OFFSET_8821C(x) \ + ((x) & (~BITS_MACID_CTRL_OFFSET_8821C)) +#define BIT_GET_MACID_CTRL_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8821C) & \ + BIT_MASK_MACID_CTRL_OFFSET_8821C) +#define BIT_SET_MACID_CTRL_OFFSET_8821C(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_8821C(x) | BIT_MACID_CTRL_OFFSET_8821C(v)) #define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C 0 #define BIT_MASK_AMPDU_TXRPT_OFFSET_8821C 0xff -#define BIT_AMPDU_TXRPT_OFFSET_8821C(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) -#define BIT_GET_AMPDU_TXRPT_OFFSET_8821C(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_AMPDU_TXRPT_OFFSET_8821C(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) +#define BITS_AMPDU_TXRPT_OFFSET_8821C \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_8821C \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8821C(x) \ + ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8821C)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) +#define BIT_SET_AMPDU_TXRPT_OFFSET_8821C(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8821C(x) | \ + BIT_AMPDU_TXRPT_OFFSET_8821C(v)) /* 2 REG_POWER_STAGE1_8821C */ #define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8821C BIT(31) @@ -6225,28 +10345,44 @@ #define BIT_SHIFT_POWER_STAGE1_8821C 0 #define BIT_MASK_POWER_STAGE1_8821C 0xffffff -#define BIT_POWER_STAGE1_8821C(x) (((x) & BIT_MASK_POWER_STAGE1_8821C) << BIT_SHIFT_POWER_STAGE1_8821C) -#define BIT_GET_POWER_STAGE1_8821C(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8821C) & BIT_MASK_POWER_STAGE1_8821C) - - +#define BIT_POWER_STAGE1_8821C(x) \ + (((x) & BIT_MASK_POWER_STAGE1_8821C) << BIT_SHIFT_POWER_STAGE1_8821C) +#define BITS_POWER_STAGE1_8821C \ + (BIT_MASK_POWER_STAGE1_8821C << BIT_SHIFT_POWER_STAGE1_8821C) +#define BIT_CLEAR_POWER_STAGE1_8821C(x) ((x) & (~BITS_POWER_STAGE1_8821C)) +#define BIT_GET_POWER_STAGE1_8821C(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1_8821C) & BIT_MASK_POWER_STAGE1_8821C) +#define BIT_SET_POWER_STAGE1_8821C(x, v) \ + (BIT_CLEAR_POWER_STAGE1_8821C(x) | BIT_POWER_STAGE1_8821C(v)) /* 2 REG_POWER_STAGE2_8821C */ #define BIT__R_CTRL_PKT_POW_ADJ_8821C BIT(24) #define BIT_SHIFT_POWER_STAGE2_8821C 0 #define BIT_MASK_POWER_STAGE2_8821C 0xffffff -#define BIT_POWER_STAGE2_8821C(x) (((x) & BIT_MASK_POWER_STAGE2_8821C) << BIT_SHIFT_POWER_STAGE2_8821C) -#define BIT_GET_POWER_STAGE2_8821C(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8821C) & BIT_MASK_POWER_STAGE2_8821C) - - +#define BIT_POWER_STAGE2_8821C(x) \ + (((x) & BIT_MASK_POWER_STAGE2_8821C) << BIT_SHIFT_POWER_STAGE2_8821C) +#define BITS_POWER_STAGE2_8821C \ + (BIT_MASK_POWER_STAGE2_8821C << BIT_SHIFT_POWER_STAGE2_8821C) +#define BIT_CLEAR_POWER_STAGE2_8821C(x) ((x) & (~BITS_POWER_STAGE2_8821C)) +#define BIT_GET_POWER_STAGE2_8821C(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2_8821C) & BIT_MASK_POWER_STAGE2_8821C) +#define BIT_SET_POWER_STAGE2_8821C(x, v) \ + (BIT_CLEAR_POWER_STAGE2_8821C(x) | BIT_POWER_STAGE2_8821C(v)) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8821C */ #define BIT_SHIFT_PAD_NUM_THRES_8821C 24 #define BIT_MASK_PAD_NUM_THRES_8821C 0x3f -#define BIT_PAD_NUM_THRES_8821C(x) (((x) & BIT_MASK_PAD_NUM_THRES_8821C) << BIT_SHIFT_PAD_NUM_THRES_8821C) -#define BIT_GET_PAD_NUM_THRES_8821C(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8821C) & BIT_MASK_PAD_NUM_THRES_8821C) - +#define BIT_PAD_NUM_THRES_8821C(x) \ + (((x) & BIT_MASK_PAD_NUM_THRES_8821C) << BIT_SHIFT_PAD_NUM_THRES_8821C) +#define BITS_PAD_NUM_THRES_8821C \ + (BIT_MASK_PAD_NUM_THRES_8821C << BIT_SHIFT_PAD_NUM_THRES_8821C) +#define BIT_CLEAR_PAD_NUM_THRES_8821C(x) ((x) & (~BITS_PAD_NUM_THRES_8821C)) +#define BIT_GET_PAD_NUM_THRES_8821C(x) \ + (((x) >> BIT_SHIFT_PAD_NUM_THRES_8821C) & BIT_MASK_PAD_NUM_THRES_8821C) +#define BIT_SET_PAD_NUM_THRES_8821C(x, v) \ + (BIT_CLEAR_PAD_NUM_THRES_8821C(x) | BIT_PAD_NUM_THRES_8821C(v)) #define BIT_R_DMA_THIS_QUEUE_BK_8821C BIT(23) #define BIT_R_DMA_THIS_QUEUE_BE_8821C BIT(22) @@ -6255,18 +10391,32 @@ #define BIT_SHIFT_R_TOTAL_LEN_TH_8821C 8 #define BIT_MASK_R_TOTAL_LEN_TH_8821C 0xfff -#define BIT_R_TOTAL_LEN_TH_8821C(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8821C) << BIT_SHIFT_R_TOTAL_LEN_TH_8821C) -#define BIT_GET_R_TOTAL_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8821C) & BIT_MASK_R_TOTAL_LEN_TH_8821C) - +#define BIT_R_TOTAL_LEN_TH_8821C(x) \ + (((x) & BIT_MASK_R_TOTAL_LEN_TH_8821C) \ + << BIT_SHIFT_R_TOTAL_LEN_TH_8821C) +#define BITS_R_TOTAL_LEN_TH_8821C \ + (BIT_MASK_R_TOTAL_LEN_TH_8821C << BIT_SHIFT_R_TOTAL_LEN_TH_8821C) +#define BIT_CLEAR_R_TOTAL_LEN_TH_8821C(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8821C)) +#define BIT_GET_R_TOTAL_LEN_TH_8821C(x) \ + (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8821C) & \ + BIT_MASK_R_TOTAL_LEN_TH_8821C) +#define BIT_SET_R_TOTAL_LEN_TH_8821C(x, v) \ + (BIT_CLEAR_R_TOTAL_LEN_TH_8821C(x) | BIT_R_TOTAL_LEN_TH_8821C(v)) #define BIT_EN_NEW_EARLY_8821C BIT(7) #define BIT_PRE_TX_CMD_8821C BIT(6) #define BIT_SHIFT_NUM_SCL_EN_8821C 4 #define BIT_MASK_NUM_SCL_EN_8821C 0x3 -#define BIT_NUM_SCL_EN_8821C(x) (((x) & BIT_MASK_NUM_SCL_EN_8821C) << BIT_SHIFT_NUM_SCL_EN_8821C) -#define BIT_GET_NUM_SCL_EN_8821C(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8821C) & BIT_MASK_NUM_SCL_EN_8821C) - +#define BIT_NUM_SCL_EN_8821C(x) \ + (((x) & BIT_MASK_NUM_SCL_EN_8821C) << BIT_SHIFT_NUM_SCL_EN_8821C) +#define BITS_NUM_SCL_EN_8821C \ + (BIT_MASK_NUM_SCL_EN_8821C << BIT_SHIFT_NUM_SCL_EN_8821C) +#define BIT_CLEAR_NUM_SCL_EN_8821C(x) ((x) & (~BITS_NUM_SCL_EN_8821C)) +#define BIT_GET_NUM_SCL_EN_8821C(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN_8821C) & BIT_MASK_NUM_SCL_EN_8821C) +#define BIT_SET_NUM_SCL_EN_8821C(x, v) \ + (BIT_CLEAR_NUM_SCL_EN_8821C(x) | BIT_NUM_SCL_EN_8821C(v)) #define BIT_BK_EN_8821C BIT(3) #define BIT_BE_EN_8821C BIT(2) @@ -6277,49 +10427,86 @@ #define BIT_SHIFT_PKT_LIFTIME_BEBK_8821C 16 #define BIT_MASK_PKT_LIFTIME_BEBK_8821C 0xffff -#define BIT_PKT_LIFTIME_BEBK_8821C(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8821C) << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) -#define BIT_GET_PKT_LIFTIME_BEBK_8821C(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) & BIT_MASK_PKT_LIFTIME_BEBK_8821C) - - +#define BIT_PKT_LIFTIME_BEBK_8821C(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8821C) \ + << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) +#define BITS_PKT_LIFTIME_BEBK_8821C \ + (BIT_MASK_PKT_LIFTIME_BEBK_8821C << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) +#define BIT_CLEAR_PKT_LIFTIME_BEBK_8821C(x) \ + ((x) & (~BITS_PKT_LIFTIME_BEBK_8821C)) +#define BIT_GET_PKT_LIFTIME_BEBK_8821C(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) & \ + BIT_MASK_PKT_LIFTIME_BEBK_8821C) +#define BIT_SET_PKT_LIFTIME_BEBK_8821C(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK_8821C(x) | BIT_PKT_LIFTIME_BEBK_8821C(v)) #define BIT_SHIFT_PKT_LIFTIME_VOVI_8821C 0 #define BIT_MASK_PKT_LIFTIME_VOVI_8821C 0xffff -#define BIT_PKT_LIFTIME_VOVI_8821C(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) -#define BIT_GET_PKT_LIFTIME_VOVI_8821C(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) - - +#define BIT_PKT_LIFTIME_VOVI_8821C(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) \ + << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) +#define BITS_PKT_LIFTIME_VOVI_8821C \ + (BIT_MASK_PKT_LIFTIME_VOVI_8821C << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) +#define BIT_CLEAR_PKT_LIFTIME_VOVI_8821C(x) \ + ((x) & (~BITS_PKT_LIFTIME_VOVI_8821C)) +#define BIT_GET_PKT_LIFTIME_VOVI_8821C(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) & \ + BIT_MASK_PKT_LIFTIME_VOVI_8821C) +#define BIT_SET_PKT_LIFTIME_VOVI_8821C(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI_8821C(x) | BIT_PKT_LIFTIME_VOVI_8821C(v)) /* 2 REG_STBC_SETTING_8821C */ #define BIT_SHIFT_CDEND_TXTIME_L_8821C 4 #define BIT_MASK_CDEND_TXTIME_L_8821C 0xf -#define BIT_CDEND_TXTIME_L_8821C(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8821C) << BIT_SHIFT_CDEND_TXTIME_L_8821C) -#define BIT_GET_CDEND_TXTIME_L_8821C(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8821C) & BIT_MASK_CDEND_TXTIME_L_8821C) - - +#define BIT_CDEND_TXTIME_L_8821C(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L_8821C) \ + << BIT_SHIFT_CDEND_TXTIME_L_8821C) +#define BITS_CDEND_TXTIME_L_8821C \ + (BIT_MASK_CDEND_TXTIME_L_8821C << BIT_SHIFT_CDEND_TXTIME_L_8821C) +#define BIT_CLEAR_CDEND_TXTIME_L_8821C(x) ((x) & (~BITS_CDEND_TXTIME_L_8821C)) +#define BIT_GET_CDEND_TXTIME_L_8821C(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8821C) & \ + BIT_MASK_CDEND_TXTIME_L_8821C) +#define BIT_SET_CDEND_TXTIME_L_8821C(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L_8821C(x) | BIT_CDEND_TXTIME_L_8821C(v)) #define BIT_SHIFT_NESS_8821C 2 #define BIT_MASK_NESS_8821C 0x3 #define BIT_NESS_8821C(x) (((x) & BIT_MASK_NESS_8821C) << BIT_SHIFT_NESS_8821C) -#define BIT_GET_NESS_8821C(x) (((x) >> BIT_SHIFT_NESS_8821C) & BIT_MASK_NESS_8821C) - - +#define BITS_NESS_8821C (BIT_MASK_NESS_8821C << BIT_SHIFT_NESS_8821C) +#define BIT_CLEAR_NESS_8821C(x) ((x) & (~BITS_NESS_8821C)) +#define BIT_GET_NESS_8821C(x) \ + (((x) >> BIT_SHIFT_NESS_8821C) & BIT_MASK_NESS_8821C) +#define BIT_SET_NESS_8821C(x, v) (BIT_CLEAR_NESS_8821C(x) | BIT_NESS_8821C(v)) #define BIT_SHIFT_STBC_CFEND_8821C 0 #define BIT_MASK_STBC_CFEND_8821C 0x3 -#define BIT_STBC_CFEND_8821C(x) (((x) & BIT_MASK_STBC_CFEND_8821C) << BIT_SHIFT_STBC_CFEND_8821C) -#define BIT_GET_STBC_CFEND_8821C(x) (((x) >> BIT_SHIFT_STBC_CFEND_8821C) & BIT_MASK_STBC_CFEND_8821C) - - +#define BIT_STBC_CFEND_8821C(x) \ + (((x) & BIT_MASK_STBC_CFEND_8821C) << BIT_SHIFT_STBC_CFEND_8821C) +#define BITS_STBC_CFEND_8821C \ + (BIT_MASK_STBC_CFEND_8821C << BIT_SHIFT_STBC_CFEND_8821C) +#define BIT_CLEAR_STBC_CFEND_8821C(x) ((x) & (~BITS_STBC_CFEND_8821C)) +#define BIT_GET_STBC_CFEND_8821C(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_8821C) & BIT_MASK_STBC_CFEND_8821C) +#define BIT_SET_STBC_CFEND_8821C(x, v) \ + (BIT_CLEAR_STBC_CFEND_8821C(x) | BIT_STBC_CFEND_8821C(v)) /* 2 REG_STBC_SETTING2_8821C */ #define BIT_SHIFT_CDEND_TXTIME_H_8821C 0 #define BIT_MASK_CDEND_TXTIME_H_8821C 0x1f -#define BIT_CDEND_TXTIME_H_8821C(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8821C) << BIT_SHIFT_CDEND_TXTIME_H_8821C) -#define BIT_GET_CDEND_TXTIME_H_8821C(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8821C) & BIT_MASK_CDEND_TXTIME_H_8821C) - - +#define BIT_CDEND_TXTIME_H_8821C(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H_8821C) \ + << BIT_SHIFT_CDEND_TXTIME_H_8821C) +#define BITS_CDEND_TXTIME_H_8821C \ + (BIT_MASK_CDEND_TXTIME_H_8821C << BIT_SHIFT_CDEND_TXTIME_H_8821C) +#define BIT_CLEAR_CDEND_TXTIME_H_8821C(x) ((x) & (~BITS_CDEND_TXTIME_H_8821C)) +#define BIT_GET_CDEND_TXTIME_H_8821C(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8821C) & \ + BIT_MASK_CDEND_TXTIME_H_8821C) +#define BIT_SET_CDEND_TXTIME_H_8821C(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H_8821C(x) | BIT_CDEND_TXTIME_H_8821C(v)) /* 2 REG_QUEUE_CTRL_8821C */ #define BIT_PTA_EDCCA_EN_8821C BIT(5) @@ -6336,126 +10523,241 @@ #define BIT_SHIFT_RTS_MAX_AGG_NUM_8821C 24 #define BIT_MASK_RTS_MAX_AGG_NUM_8821C 0x3f -#define BIT_RTS_MAX_AGG_NUM_8821C(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8821C) << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) -#define BIT_GET_RTS_MAX_AGG_NUM_8821C(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) & BIT_MASK_RTS_MAX_AGG_NUM_8821C) - - +#define BIT_RTS_MAX_AGG_NUM_8821C(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8821C) \ + << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) +#define BITS_RTS_MAX_AGG_NUM_8821C \ + (BIT_MASK_RTS_MAX_AGG_NUM_8821C << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) +#define BIT_CLEAR_RTS_MAX_AGG_NUM_8821C(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8821C)) +#define BIT_GET_RTS_MAX_AGG_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) & \ + BIT_MASK_RTS_MAX_AGG_NUM_8821C) +#define BIT_SET_RTS_MAX_AGG_NUM_8821C(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM_8821C(x) | BIT_RTS_MAX_AGG_NUM_8821C(v)) #define BIT_SHIFT_MAX_AGG_NUM_8821C 16 #define BIT_MASK_MAX_AGG_NUM_8821C 0x3f -#define BIT_MAX_AGG_NUM_8821C(x) (((x) & BIT_MASK_MAX_AGG_NUM_8821C) << BIT_SHIFT_MAX_AGG_NUM_8821C) -#define BIT_GET_MAX_AGG_NUM_8821C(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8821C) & BIT_MASK_MAX_AGG_NUM_8821C) - - +#define BIT_MAX_AGG_NUM_8821C(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM_8821C) << BIT_SHIFT_MAX_AGG_NUM_8821C) +#define BITS_MAX_AGG_NUM_8821C \ + (BIT_MASK_MAX_AGG_NUM_8821C << BIT_SHIFT_MAX_AGG_NUM_8821C) +#define BIT_CLEAR_MAX_AGG_NUM_8821C(x) ((x) & (~BITS_MAX_AGG_NUM_8821C)) +#define BIT_GET_MAX_AGG_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM_8821C) & BIT_MASK_MAX_AGG_NUM_8821C) +#define BIT_SET_MAX_AGG_NUM_8821C(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM_8821C(x) | BIT_MAX_AGG_NUM_8821C(v)) #define BIT_SHIFT_RTS_TXTIME_TH_8821C 8 #define BIT_MASK_RTS_TXTIME_TH_8821C 0xff -#define BIT_RTS_TXTIME_TH_8821C(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8821C) << BIT_SHIFT_RTS_TXTIME_TH_8821C) -#define BIT_GET_RTS_TXTIME_TH_8821C(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8821C) & BIT_MASK_RTS_TXTIME_TH_8821C) - - +#define BIT_RTS_TXTIME_TH_8821C(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH_8821C) << BIT_SHIFT_RTS_TXTIME_TH_8821C) +#define BITS_RTS_TXTIME_TH_8821C \ + (BIT_MASK_RTS_TXTIME_TH_8821C << BIT_SHIFT_RTS_TXTIME_TH_8821C) +#define BIT_CLEAR_RTS_TXTIME_TH_8821C(x) ((x) & (~BITS_RTS_TXTIME_TH_8821C)) +#define BIT_GET_RTS_TXTIME_TH_8821C(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8821C) & BIT_MASK_RTS_TXTIME_TH_8821C) +#define BIT_SET_RTS_TXTIME_TH_8821C(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH_8821C(x) | BIT_RTS_TXTIME_TH_8821C(v)) #define BIT_SHIFT_RTS_LEN_TH_8821C 0 #define BIT_MASK_RTS_LEN_TH_8821C 0xff -#define BIT_RTS_LEN_TH_8821C(x) (((x) & BIT_MASK_RTS_LEN_TH_8821C) << BIT_SHIFT_RTS_LEN_TH_8821C) -#define BIT_GET_RTS_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8821C) & BIT_MASK_RTS_LEN_TH_8821C) - - +#define BIT_RTS_LEN_TH_8821C(x) \ + (((x) & BIT_MASK_RTS_LEN_TH_8821C) << BIT_SHIFT_RTS_LEN_TH_8821C) +#define BITS_RTS_LEN_TH_8821C \ + (BIT_MASK_RTS_LEN_TH_8821C << BIT_SHIFT_RTS_LEN_TH_8821C) +#define BIT_CLEAR_RTS_LEN_TH_8821C(x) ((x) & (~BITS_RTS_LEN_TH_8821C)) +#define BIT_GET_RTS_LEN_TH_8821C(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH_8821C) & BIT_MASK_RTS_LEN_TH_8821C) +#define BIT_SET_RTS_LEN_TH_8821C(x, v) \ + (BIT_CLEAR_RTS_LEN_TH_8821C(x) | BIT_RTS_LEN_TH_8821C(v)) /* 2 REG_BAR_MODE_CTRL_8821C */ #define BIT_SHIFT_BAR_RTY_LMT_8821C 16 #define BIT_MASK_BAR_RTY_LMT_8821C 0x3 -#define BIT_BAR_RTY_LMT_8821C(x) (((x) & BIT_MASK_BAR_RTY_LMT_8821C) << BIT_SHIFT_BAR_RTY_LMT_8821C) -#define BIT_GET_BAR_RTY_LMT_8821C(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8821C) & BIT_MASK_BAR_RTY_LMT_8821C) - - +#define BIT_BAR_RTY_LMT_8821C(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT_8821C) << BIT_SHIFT_BAR_RTY_LMT_8821C) +#define BITS_BAR_RTY_LMT_8821C \ + (BIT_MASK_BAR_RTY_LMT_8821C << BIT_SHIFT_BAR_RTY_LMT_8821C) +#define BIT_CLEAR_BAR_RTY_LMT_8821C(x) ((x) & (~BITS_BAR_RTY_LMT_8821C)) +#define BIT_GET_BAR_RTY_LMT_8821C(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT_8821C) & BIT_MASK_BAR_RTY_LMT_8821C) +#define BIT_SET_BAR_RTY_LMT_8821C(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT_8821C(x) | BIT_BAR_RTY_LMT_8821C(v)) #define BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C 8 #define BIT_MASK_BAR_PKT_TXTIME_TH_8821C 0xff -#define BIT_BAR_PKT_TXTIME_TH_8821C(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) -#define BIT_GET_BAR_PKT_TXTIME_TH_8821C(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) - +#define BIT_BAR_PKT_TXTIME_TH_8821C(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) \ + << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) +#define BITS_BAR_PKT_TXTIME_TH_8821C \ + (BIT_MASK_BAR_PKT_TXTIME_TH_8821C << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8821C(x) \ + ((x) & (~BITS_BAR_PKT_TXTIME_TH_8821C)) +#define BIT_GET_BAR_PKT_TXTIME_TH_8821C(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) & \ + BIT_MASK_BAR_PKT_TXTIME_TH_8821C) +#define BIT_SET_BAR_PKT_TXTIME_TH_8821C(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH_8821C(x) | BIT_BAR_PKT_TXTIME_TH_8821C(v)) #define BIT_BAR_EN_V1_8821C BIT(6) #define BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C 0 #define BIT_MASK_BAR_PKTNUM_TH_V1_8821C 0x3f -#define BIT_BAR_PKTNUM_TH_V1_8821C(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) -#define BIT_GET_BAR_PKTNUM_TH_V1_8821C(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C) - - +#define BIT_BAR_PKTNUM_TH_V1_8821C(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C) \ + << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) +#define BITS_BAR_PKTNUM_TH_V1_8821C \ + (BIT_MASK_BAR_PKTNUM_TH_V1_8821C << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8821C(x) \ + ((x) & (~BITS_BAR_PKTNUM_TH_V1_8821C)) +#define BIT_GET_BAR_PKTNUM_TH_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) & \ + BIT_MASK_BAR_PKTNUM_TH_V1_8821C) +#define BIT_SET_BAR_PKTNUM_TH_V1_8821C(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1_8821C(x) | BIT_BAR_PKTNUM_TH_V1_8821C(v)) /* 2 REG_RA_TRY_RATE_AGG_LMT_8821C */ #define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C 0 #define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C 0x3f -#define BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) -#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8821C(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) - - +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) +#define BITS_RA_TRY_RATE_AGG_LMT_V1_8821C \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8821C(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8821C)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8821C(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8821C(x) | \ + BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(v)) /* 2 REG_MACID_SLEEP2_8821C */ #define BIT_SHIFT_MACID95_64PKTSLEEP_8821C 0 #define BIT_MASK_MACID95_64PKTSLEEP_8821C 0xffffffffL -#define BIT_MACID95_64PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8821C) << BIT_SHIFT_MACID95_64PKTSLEEP_8821C) -#define BIT_GET_MACID95_64PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8821C) & BIT_MASK_MACID95_64PKTSLEEP_8821C) - - +#define BIT_MACID95_64PKTSLEEP_8821C(x) \ + (((x) & BIT_MASK_MACID95_64PKTSLEEP_8821C) \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8821C) +#define BITS_MACID95_64PKTSLEEP_8821C \ + (BIT_MASK_MACID95_64PKTSLEEP_8821C \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8821C) +#define BIT_CLEAR_MACID95_64PKTSLEEP_8821C(x) \ + ((x) & (~BITS_MACID95_64PKTSLEEP_8821C)) +#define BIT_GET_MACID95_64PKTSLEEP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8821C) & \ + BIT_MASK_MACID95_64PKTSLEEP_8821C) +#define BIT_SET_MACID95_64PKTSLEEP_8821C(x, v) \ + (BIT_CLEAR_MACID95_64PKTSLEEP_8821C(x) | \ + BIT_MACID95_64PKTSLEEP_8821C(v)) /* 2 REG_MACID_SLEEP_8821C */ #define BIT_SHIFT_MACID31_0_PKTSLEEP_8821C 0 #define BIT_MASK_MACID31_0_PKTSLEEP_8821C 0xffffffffL -#define BIT_MACID31_0_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8821C) << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) -#define BIT_GET_MACID31_0_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) & BIT_MASK_MACID31_0_PKTSLEEP_8821C) - - +#define BIT_MACID31_0_PKTSLEEP_8821C(x) \ + (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8821C) \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) +#define BITS_MACID31_0_PKTSLEEP_8821C \ + (BIT_MASK_MACID31_0_PKTSLEEP_8821C \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) +#define BIT_CLEAR_MACID31_0_PKTSLEEP_8821C(x) \ + ((x) & (~BITS_MACID31_0_PKTSLEEP_8821C)) +#define BIT_GET_MACID31_0_PKTSLEEP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) & \ + BIT_MASK_MACID31_0_PKTSLEEP_8821C) +#define BIT_SET_MACID31_0_PKTSLEEP_8821C(x, v) \ + (BIT_CLEAR_MACID31_0_PKTSLEEP_8821C(x) | \ + BIT_MACID31_0_PKTSLEEP_8821C(v)) /* 2 REG_HW_SEQ0_8821C */ #define BIT_SHIFT_HW_SSN_SEQ0_8821C 0 #define BIT_MASK_HW_SSN_SEQ0_8821C 0xfff -#define BIT_HW_SSN_SEQ0_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8821C) << BIT_SHIFT_HW_SSN_SEQ0_8821C) -#define BIT_GET_HW_SSN_SEQ0_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8821C) & BIT_MASK_HW_SSN_SEQ0_8821C) - - +#define BIT_HW_SSN_SEQ0_8821C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0_8821C) << BIT_SHIFT_HW_SSN_SEQ0_8821C) +#define BITS_HW_SSN_SEQ0_8821C \ + (BIT_MASK_HW_SSN_SEQ0_8821C << BIT_SHIFT_HW_SSN_SEQ0_8821C) +#define BIT_CLEAR_HW_SSN_SEQ0_8821C(x) ((x) & (~BITS_HW_SSN_SEQ0_8821C)) +#define BIT_GET_HW_SSN_SEQ0_8821C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8821C) & BIT_MASK_HW_SSN_SEQ0_8821C) +#define BIT_SET_HW_SSN_SEQ0_8821C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0_8821C(x) | BIT_HW_SSN_SEQ0_8821C(v)) /* 2 REG_HW_SEQ1_8821C */ #define BIT_SHIFT_HW_SSN_SEQ1_8821C 0 #define BIT_MASK_HW_SSN_SEQ1_8821C 0xfff -#define BIT_HW_SSN_SEQ1_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8821C) << BIT_SHIFT_HW_SSN_SEQ1_8821C) -#define BIT_GET_HW_SSN_SEQ1_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8821C) & BIT_MASK_HW_SSN_SEQ1_8821C) - - +#define BIT_HW_SSN_SEQ1_8821C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1_8821C) << BIT_SHIFT_HW_SSN_SEQ1_8821C) +#define BITS_HW_SSN_SEQ1_8821C \ + (BIT_MASK_HW_SSN_SEQ1_8821C << BIT_SHIFT_HW_SSN_SEQ1_8821C) +#define BIT_CLEAR_HW_SSN_SEQ1_8821C(x) ((x) & (~BITS_HW_SSN_SEQ1_8821C)) +#define BIT_GET_HW_SSN_SEQ1_8821C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8821C) & BIT_MASK_HW_SSN_SEQ1_8821C) +#define BIT_SET_HW_SSN_SEQ1_8821C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1_8821C(x) | BIT_HW_SSN_SEQ1_8821C(v)) /* 2 REG_HW_SEQ2_8821C */ #define BIT_SHIFT_HW_SSN_SEQ2_8821C 0 #define BIT_MASK_HW_SSN_SEQ2_8821C 0xfff -#define BIT_HW_SSN_SEQ2_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8821C) << BIT_SHIFT_HW_SSN_SEQ2_8821C) -#define BIT_GET_HW_SSN_SEQ2_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8821C) & BIT_MASK_HW_SSN_SEQ2_8821C) - - +#define BIT_HW_SSN_SEQ2_8821C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2_8821C) << BIT_SHIFT_HW_SSN_SEQ2_8821C) +#define BITS_HW_SSN_SEQ2_8821C \ + (BIT_MASK_HW_SSN_SEQ2_8821C << BIT_SHIFT_HW_SSN_SEQ2_8821C) +#define BIT_CLEAR_HW_SSN_SEQ2_8821C(x) ((x) & (~BITS_HW_SSN_SEQ2_8821C)) +#define BIT_GET_HW_SSN_SEQ2_8821C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8821C) & BIT_MASK_HW_SSN_SEQ2_8821C) +#define BIT_SET_HW_SSN_SEQ2_8821C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2_8821C(x) | BIT_HW_SSN_SEQ2_8821C(v)) /* 2 REG_HW_SEQ3_8821C */ +#define BIT_SHIFT_CSI_HWSEQ_SEL_8821C 12 +#define BIT_MASK_CSI_HWSEQ_SEL_8821C 0x3 +#define BIT_CSI_HWSEQ_SEL_8821C(x) \ + (((x) & BIT_MASK_CSI_HWSEQ_SEL_8821C) << BIT_SHIFT_CSI_HWSEQ_SEL_8821C) +#define BITS_CSI_HWSEQ_SEL_8821C \ + (BIT_MASK_CSI_HWSEQ_SEL_8821C << BIT_SHIFT_CSI_HWSEQ_SEL_8821C) +#define BIT_CLEAR_CSI_HWSEQ_SEL_8821C(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8821C)) +#define BIT_GET_CSI_HWSEQ_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8821C) & BIT_MASK_CSI_HWSEQ_SEL_8821C) +#define BIT_SET_CSI_HWSEQ_SEL_8821C(x, v) \ + (BIT_CLEAR_CSI_HWSEQ_SEL_8821C(x) | BIT_CSI_HWSEQ_SEL_8821C(v)) + #define BIT_SHIFT_HW_SSN_SEQ3_8821C 0 #define BIT_MASK_HW_SSN_SEQ3_8821C 0xfff -#define BIT_HW_SSN_SEQ3_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8821C) << BIT_SHIFT_HW_SSN_SEQ3_8821C) -#define BIT_GET_HW_SSN_SEQ3_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8821C) & BIT_MASK_HW_SSN_SEQ3_8821C) - - +#define BIT_HW_SSN_SEQ3_8821C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3_8821C) << BIT_SHIFT_HW_SSN_SEQ3_8821C) +#define BITS_HW_SSN_SEQ3_8821C \ + (BIT_MASK_HW_SSN_SEQ3_8821C << BIT_SHIFT_HW_SSN_SEQ3_8821C) +#define BIT_CLEAR_HW_SSN_SEQ3_8821C(x) ((x) & (~BITS_HW_SSN_SEQ3_8821C)) +#define BIT_GET_HW_SSN_SEQ3_8821C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8821C) & BIT_MASK_HW_SSN_SEQ3_8821C) +#define BIT_SET_HW_SSN_SEQ3_8821C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3_8821C(x) | BIT_HW_SSN_SEQ3_8821C(v)) /* 2 REG_NULL_PKT_STATUS_V1_8821C */ #define BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C 2 #define BIT_MASK_PTCL_TOTAL_PG_V2_8821C 0x3fff -#define BIT_PTCL_TOTAL_PG_V2_8821C(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) -#define BIT_GET_PTCL_TOTAL_PG_V2_8821C(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) - +#define BIT_PTCL_TOTAL_PG_V2_8821C(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) \ + << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) +#define BITS_PTCL_TOTAL_PG_V2_8821C \ + (BIT_MASK_PTCL_TOTAL_PG_V2_8821C << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) +#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8821C(x) \ + ((x) & (~BITS_PTCL_TOTAL_PG_V2_8821C)) +#define BIT_GET_PTCL_TOTAL_PG_V2_8821C(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) & \ + BIT_MASK_PTCL_TOTAL_PG_V2_8821C) +#define BIT_SET_PTCL_TOTAL_PG_V2_8821C(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V2_8821C(x) | BIT_PTCL_TOTAL_PG_V2_8821C(v)) #define BIT_TX_NULL_1_8821C BIT(1) #define BIT_TX_NULL_0_8821C BIT(0) @@ -6481,17 +10783,46 @@ #define BIT_CLI0_TX_NULL_0_8821C BIT(0) /* 2 REG_VIDEO_ENHANCEMENT_FUN_8821C */ +#define BIT_HIQ_DROP_8821C BIT(7) +#define BIT_MGQ_DROP_8821C BIT(6) #define BIT_VIDEO_JUST_DROP_8821C BIT(1) #define BIT_VIDEO_ENHANCEMENT_FUN_EN_8821C BIT(0) +/* 2 REG_PRECNT_CTRL_8821C */ +#define BIT_EN_PRECNT_8821C BIT(11) + +#define BIT_SHIFT_PRECNT_TH_8821C 0 +#define BIT_MASK_PRECNT_TH_8821C 0x7ff +#define BIT_PRECNT_TH_8821C(x) \ + (((x) & BIT_MASK_PRECNT_TH_8821C) << BIT_SHIFT_PRECNT_TH_8821C) +#define BITS_PRECNT_TH_8821C \ + (BIT_MASK_PRECNT_TH_8821C << BIT_SHIFT_PRECNT_TH_8821C) +#define BIT_CLEAR_PRECNT_TH_8821C(x) ((x) & (~BITS_PRECNT_TH_8821C)) +#define BIT_GET_PRECNT_TH_8821C(x) \ + (((x) >> BIT_SHIFT_PRECNT_TH_8821C) & BIT_MASK_PRECNT_TH_8821C) +#define BIT_SET_PRECNT_TH_8821C(x, v) \ + (BIT_CLEAR_PRECNT_TH_8821C(x) | BIT_PRECNT_TH_8821C(v)) + +/* 2 REG_NOT_VALID_8821C */ + /* 2 REG_BT_POLLUTE_PKT_CNT_8821C */ #define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C 0 #define BIT_MASK_BT_POLLUTE_PKT_CNT_8821C 0xffff -#define BIT_BT_POLLUTE_PKT_CNT_8821C(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) -#define BIT_GET_BT_POLLUTE_PKT_CNT_8821C(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) - - +#define BIT_BT_POLLUTE_PKT_CNT_8821C(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) +#define BITS_BT_POLLUTE_PKT_CNT_8821C \ + (BIT_MASK_BT_POLLUTE_PKT_CNT_8821C \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) +#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8821C(x) \ + ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8821C)) +#define BIT_GET_BT_POLLUTE_PKT_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) & \ + BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) +#define BIT_SET_BT_POLLUTE_PKT_CNT_8821C(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8821C(x) | \ + BIT_BT_POLLUTE_PKT_CNT_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -6499,10 +10830,15 @@ #define BIT_SHIFT_PTCL_DBG_8821C 0 #define BIT_MASK_PTCL_DBG_8821C 0xffffffffL -#define BIT_PTCL_DBG_8821C(x) (((x) & BIT_MASK_PTCL_DBG_8821C) << BIT_SHIFT_PTCL_DBG_8821C) -#define BIT_GET_PTCL_DBG_8821C(x) (((x) >> BIT_SHIFT_PTCL_DBG_8821C) & BIT_MASK_PTCL_DBG_8821C) - - +#define BIT_PTCL_DBG_8821C(x) \ + (((x) & BIT_MASK_PTCL_DBG_8821C) << BIT_SHIFT_PTCL_DBG_8821C) +#define BITS_PTCL_DBG_8821C \ + (BIT_MASK_PTCL_DBG_8821C << BIT_SHIFT_PTCL_DBG_8821C) +#define BIT_CLEAR_PTCL_DBG_8821C(x) ((x) & (~BITS_PTCL_DBG_8821C)) +#define BIT_GET_PTCL_DBG_8821C(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_8821C) & BIT_MASK_PTCL_DBG_8821C) +#define BIT_SET_PTCL_DBG_8821C(x, v) \ + (BIT_CLEAR_PTCL_DBG_8821C(x) | BIT_PTCL_DBG_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -6510,18 +10846,28 @@ #define BIT_SHIFT_TRI_HEAD_ADDR_8821C 16 #define BIT_MASK_TRI_HEAD_ADDR_8821C 0xfff -#define BIT_TRI_HEAD_ADDR_8821C(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8821C) << BIT_SHIFT_TRI_HEAD_ADDR_8821C) -#define BIT_GET_TRI_HEAD_ADDR_8821C(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8821C) & BIT_MASK_TRI_HEAD_ADDR_8821C) - +#define BIT_TRI_HEAD_ADDR_8821C(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR_8821C) << BIT_SHIFT_TRI_HEAD_ADDR_8821C) +#define BITS_TRI_HEAD_ADDR_8821C \ + (BIT_MASK_TRI_HEAD_ADDR_8821C << BIT_SHIFT_TRI_HEAD_ADDR_8821C) +#define BIT_CLEAR_TRI_HEAD_ADDR_8821C(x) ((x) & (~BITS_TRI_HEAD_ADDR_8821C)) +#define BIT_GET_TRI_HEAD_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8821C) & BIT_MASK_TRI_HEAD_ADDR_8821C) +#define BIT_SET_TRI_HEAD_ADDR_8821C(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR_8821C(x) | BIT_TRI_HEAD_ADDR_8821C(v)) #define BIT_DROP_TH_EN_8821C BIT(8) #define BIT_SHIFT_DROP_TH_8821C 0 #define BIT_MASK_DROP_TH_8821C 0xff -#define BIT_DROP_TH_8821C(x) (((x) & BIT_MASK_DROP_TH_8821C) << BIT_SHIFT_DROP_TH_8821C) -#define BIT_GET_DROP_TH_8821C(x) (((x) >> BIT_SHIFT_DROP_TH_8821C) & BIT_MASK_DROP_TH_8821C) - - +#define BIT_DROP_TH_8821C(x) \ + (((x) & BIT_MASK_DROP_TH_8821C) << BIT_SHIFT_DROP_TH_8821C) +#define BITS_DROP_TH_8821C (BIT_MASK_DROP_TH_8821C << BIT_SHIFT_DROP_TH_8821C) +#define BIT_CLEAR_DROP_TH_8821C(x) ((x) & (~BITS_DROP_TH_8821C)) +#define BIT_GET_DROP_TH_8821C(x) \ + (((x) >> BIT_SHIFT_DROP_TH_8821C) & BIT_MASK_DROP_TH_8821C) +#define BIT_SET_DROP_TH_8821C(x, v) \ + (BIT_CLEAR_DROP_TH_8821C(x) | BIT_DROP_TH_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -6532,194 +10878,308 @@ #define BIT_MOREDATA_CTRL1_EN_V1_8821C BIT(2) #define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8821C BIT(0) -/* 2 REG_NOT_VALID_8821C */ - /* 2 REG_Q0_Q1_INFO_8821C */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) #define BIT_SHIFT_GTAB_ID_8821C 28 #define BIT_MASK_GTAB_ID_8821C 0x7 -#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) -#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) - - +#define BIT_GTAB_ID_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C)) +#define BIT_GET_GTAB_ID_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) +#define BIT_SET_GTAB_ID_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v)) #define BIT_SHIFT_AC1_PKT_INFO_8821C 16 #define BIT_MASK_AC1_PKT_INFO_8821C 0xfff -#define BIT_AC1_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC1_PKT_INFO_8821C) << BIT_SHIFT_AC1_PKT_INFO_8821C) -#define BIT_GET_AC1_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8821C) & BIT_MASK_AC1_PKT_INFO_8821C) - +#define BIT_AC1_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC1_PKT_INFO_8821C) << BIT_SHIFT_AC1_PKT_INFO_8821C) +#define BITS_AC1_PKT_INFO_8821C \ + (BIT_MASK_AC1_PKT_INFO_8821C << BIT_SHIFT_AC1_PKT_INFO_8821C) +#define BIT_CLEAR_AC1_PKT_INFO_8821C(x) ((x) & (~BITS_AC1_PKT_INFO_8821C)) +#define BIT_GET_AC1_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC1_PKT_INFO_8821C) & BIT_MASK_AC1_PKT_INFO_8821C) +#define BIT_SET_AC1_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC1_PKT_INFO_8821C(x) | BIT_AC1_PKT_INFO_8821C(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 #define BIT_MASK_GTAB_ID_V1_8821C 0x7 -#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) -#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) - - +#define BIT_GTAB_ID_V1_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BITS_GTAB_ID_V1_8821C \ + (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C)) +#define BIT_GET_GTAB_ID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) +#define BIT_SET_GTAB_ID_V1_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v)) #define BIT_SHIFT_AC0_PKT_INFO_8821C 0 #define BIT_MASK_AC0_PKT_INFO_8821C 0xfff -#define BIT_AC0_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC0_PKT_INFO_8821C) << BIT_SHIFT_AC0_PKT_INFO_8821C) -#define BIT_GET_AC0_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8821C) & BIT_MASK_AC0_PKT_INFO_8821C) - - +#define BIT_AC0_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC0_PKT_INFO_8821C) << BIT_SHIFT_AC0_PKT_INFO_8821C) +#define BITS_AC0_PKT_INFO_8821C \ + (BIT_MASK_AC0_PKT_INFO_8821C << BIT_SHIFT_AC0_PKT_INFO_8821C) +#define BIT_CLEAR_AC0_PKT_INFO_8821C(x) ((x) & (~BITS_AC0_PKT_INFO_8821C)) +#define BIT_GET_AC0_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC0_PKT_INFO_8821C) & BIT_MASK_AC0_PKT_INFO_8821C) +#define BIT_SET_AC0_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC0_PKT_INFO_8821C(x) | BIT_AC0_PKT_INFO_8821C(v)) /* 2 REG_Q2_Q3_INFO_8821C */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) #define BIT_SHIFT_GTAB_ID_8821C 28 #define BIT_MASK_GTAB_ID_8821C 0x7 -#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) -#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) - - +#define BIT_GTAB_ID_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C)) +#define BIT_GET_GTAB_ID_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) +#define BIT_SET_GTAB_ID_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v)) #define BIT_SHIFT_AC3_PKT_INFO_8821C 16 #define BIT_MASK_AC3_PKT_INFO_8821C 0xfff -#define BIT_AC3_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC3_PKT_INFO_8821C) << BIT_SHIFT_AC3_PKT_INFO_8821C) -#define BIT_GET_AC3_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8821C) & BIT_MASK_AC3_PKT_INFO_8821C) - +#define BIT_AC3_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC3_PKT_INFO_8821C) << BIT_SHIFT_AC3_PKT_INFO_8821C) +#define BITS_AC3_PKT_INFO_8821C \ + (BIT_MASK_AC3_PKT_INFO_8821C << BIT_SHIFT_AC3_PKT_INFO_8821C) +#define BIT_CLEAR_AC3_PKT_INFO_8821C(x) ((x) & (~BITS_AC3_PKT_INFO_8821C)) +#define BIT_GET_AC3_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC3_PKT_INFO_8821C) & BIT_MASK_AC3_PKT_INFO_8821C) +#define BIT_SET_AC3_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC3_PKT_INFO_8821C(x) | BIT_AC3_PKT_INFO_8821C(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 #define BIT_MASK_GTAB_ID_V1_8821C 0x7 -#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) -#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) - - +#define BIT_GTAB_ID_V1_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BITS_GTAB_ID_V1_8821C \ + (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C)) +#define BIT_GET_GTAB_ID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) +#define BIT_SET_GTAB_ID_V1_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v)) #define BIT_SHIFT_AC2_PKT_INFO_8821C 0 #define BIT_MASK_AC2_PKT_INFO_8821C 0xfff -#define BIT_AC2_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC2_PKT_INFO_8821C) << BIT_SHIFT_AC2_PKT_INFO_8821C) -#define BIT_GET_AC2_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8821C) & BIT_MASK_AC2_PKT_INFO_8821C) - - +#define BIT_AC2_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC2_PKT_INFO_8821C) << BIT_SHIFT_AC2_PKT_INFO_8821C) +#define BITS_AC2_PKT_INFO_8821C \ + (BIT_MASK_AC2_PKT_INFO_8821C << BIT_SHIFT_AC2_PKT_INFO_8821C) +#define BIT_CLEAR_AC2_PKT_INFO_8821C(x) ((x) & (~BITS_AC2_PKT_INFO_8821C)) +#define BIT_GET_AC2_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC2_PKT_INFO_8821C) & BIT_MASK_AC2_PKT_INFO_8821C) +#define BIT_SET_AC2_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC2_PKT_INFO_8821C(x) | BIT_AC2_PKT_INFO_8821C(v)) /* 2 REG_Q4_Q5_INFO_8821C */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) #define BIT_SHIFT_GTAB_ID_8821C 28 #define BIT_MASK_GTAB_ID_8821C 0x7 -#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) -#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) - - +#define BIT_GTAB_ID_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C)) +#define BIT_GET_GTAB_ID_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) +#define BIT_SET_GTAB_ID_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v)) #define BIT_SHIFT_AC5_PKT_INFO_8821C 16 #define BIT_MASK_AC5_PKT_INFO_8821C 0xfff -#define BIT_AC5_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC5_PKT_INFO_8821C) << BIT_SHIFT_AC5_PKT_INFO_8821C) -#define BIT_GET_AC5_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8821C) & BIT_MASK_AC5_PKT_INFO_8821C) - +#define BIT_AC5_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC5_PKT_INFO_8821C) << BIT_SHIFT_AC5_PKT_INFO_8821C) +#define BITS_AC5_PKT_INFO_8821C \ + (BIT_MASK_AC5_PKT_INFO_8821C << BIT_SHIFT_AC5_PKT_INFO_8821C) +#define BIT_CLEAR_AC5_PKT_INFO_8821C(x) ((x) & (~BITS_AC5_PKT_INFO_8821C)) +#define BIT_GET_AC5_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC5_PKT_INFO_8821C) & BIT_MASK_AC5_PKT_INFO_8821C) +#define BIT_SET_AC5_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC5_PKT_INFO_8821C(x) | BIT_AC5_PKT_INFO_8821C(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 #define BIT_MASK_GTAB_ID_V1_8821C 0x7 -#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) -#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) - - +#define BIT_GTAB_ID_V1_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BITS_GTAB_ID_V1_8821C \ + (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C)) +#define BIT_GET_GTAB_ID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) +#define BIT_SET_GTAB_ID_V1_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v)) #define BIT_SHIFT_AC4_PKT_INFO_8821C 0 #define BIT_MASK_AC4_PKT_INFO_8821C 0xfff -#define BIT_AC4_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC4_PKT_INFO_8821C) << BIT_SHIFT_AC4_PKT_INFO_8821C) -#define BIT_GET_AC4_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8821C) & BIT_MASK_AC4_PKT_INFO_8821C) - - +#define BIT_AC4_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC4_PKT_INFO_8821C) << BIT_SHIFT_AC4_PKT_INFO_8821C) +#define BITS_AC4_PKT_INFO_8821C \ + (BIT_MASK_AC4_PKT_INFO_8821C << BIT_SHIFT_AC4_PKT_INFO_8821C) +#define BIT_CLEAR_AC4_PKT_INFO_8821C(x) ((x) & (~BITS_AC4_PKT_INFO_8821C)) +#define BIT_GET_AC4_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC4_PKT_INFO_8821C) & BIT_MASK_AC4_PKT_INFO_8821C) +#define BIT_SET_AC4_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC4_PKT_INFO_8821C(x) | BIT_AC4_PKT_INFO_8821C(v)) /* 2 REG_Q6_Q7_INFO_8821C */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) #define BIT_SHIFT_GTAB_ID_8821C 28 #define BIT_MASK_GTAB_ID_8821C 0x7 -#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) -#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) - - +#define BIT_GTAB_ID_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C)) +#define BIT_GET_GTAB_ID_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) +#define BIT_SET_GTAB_ID_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v)) #define BIT_SHIFT_AC7_PKT_INFO_8821C 16 #define BIT_MASK_AC7_PKT_INFO_8821C 0xfff -#define BIT_AC7_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC7_PKT_INFO_8821C) << BIT_SHIFT_AC7_PKT_INFO_8821C) -#define BIT_GET_AC7_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8821C) & BIT_MASK_AC7_PKT_INFO_8821C) - +#define BIT_AC7_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC7_PKT_INFO_8821C) << BIT_SHIFT_AC7_PKT_INFO_8821C) +#define BITS_AC7_PKT_INFO_8821C \ + (BIT_MASK_AC7_PKT_INFO_8821C << BIT_SHIFT_AC7_PKT_INFO_8821C) +#define BIT_CLEAR_AC7_PKT_INFO_8821C(x) ((x) & (~BITS_AC7_PKT_INFO_8821C)) +#define BIT_GET_AC7_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC7_PKT_INFO_8821C) & BIT_MASK_AC7_PKT_INFO_8821C) +#define BIT_SET_AC7_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC7_PKT_INFO_8821C(x) | BIT_AC7_PKT_INFO_8821C(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8821C 12 #define BIT_MASK_GTAB_ID_V1_8821C 0x7 -#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) -#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) - - +#define BIT_GTAB_ID_V1_8821C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BITS_GTAB_ID_V1_8821C \ + (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C)) +#define BIT_GET_GTAB_ID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) +#define BIT_SET_GTAB_ID_V1_8821C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v)) #define BIT_SHIFT_AC6_PKT_INFO_8821C 0 #define BIT_MASK_AC6_PKT_INFO_8821C 0xfff -#define BIT_AC6_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC6_PKT_INFO_8821C) << BIT_SHIFT_AC6_PKT_INFO_8821C) -#define BIT_GET_AC6_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8821C) & BIT_MASK_AC6_PKT_INFO_8821C) - - +#define BIT_AC6_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_AC6_PKT_INFO_8821C) << BIT_SHIFT_AC6_PKT_INFO_8821C) +#define BITS_AC6_PKT_INFO_8821C \ + (BIT_MASK_AC6_PKT_INFO_8821C << BIT_SHIFT_AC6_PKT_INFO_8821C) +#define BIT_CLEAR_AC6_PKT_INFO_8821C(x) ((x) & (~BITS_AC6_PKT_INFO_8821C)) +#define BIT_GET_AC6_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_AC6_PKT_INFO_8821C) & BIT_MASK_AC6_PKT_INFO_8821C) +#define BIT_SET_AC6_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_AC6_PKT_INFO_8821C(x) | BIT_AC6_PKT_INFO_8821C(v)) /* 2 REG_MGQ_HIQ_INFO_8821C */ #define BIT_SHIFT_HIQ_PKT_INFO_8821C 16 #define BIT_MASK_HIQ_PKT_INFO_8821C 0xfff -#define BIT_HIQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8821C) << BIT_SHIFT_HIQ_PKT_INFO_8821C) -#define BIT_GET_HIQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8821C) & BIT_MASK_HIQ_PKT_INFO_8821C) - - +#define BIT_HIQ_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_HIQ_PKT_INFO_8821C) << BIT_SHIFT_HIQ_PKT_INFO_8821C) +#define BITS_HIQ_PKT_INFO_8821C \ + (BIT_MASK_HIQ_PKT_INFO_8821C << BIT_SHIFT_HIQ_PKT_INFO_8821C) +#define BIT_CLEAR_HIQ_PKT_INFO_8821C(x) ((x) & (~BITS_HIQ_PKT_INFO_8821C)) +#define BIT_GET_HIQ_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8821C) & BIT_MASK_HIQ_PKT_INFO_8821C) +#define BIT_SET_HIQ_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_HIQ_PKT_INFO_8821C(x) | BIT_HIQ_PKT_INFO_8821C(v)) #define BIT_SHIFT_MGQ_PKT_INFO_8821C 0 #define BIT_MASK_MGQ_PKT_INFO_8821C 0xfff -#define BIT_MGQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8821C) << BIT_SHIFT_MGQ_PKT_INFO_8821C) -#define BIT_GET_MGQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8821C) & BIT_MASK_MGQ_PKT_INFO_8821C) - - +#define BIT_MGQ_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_MGQ_PKT_INFO_8821C) << BIT_SHIFT_MGQ_PKT_INFO_8821C) +#define BITS_MGQ_PKT_INFO_8821C \ + (BIT_MASK_MGQ_PKT_INFO_8821C << BIT_SHIFT_MGQ_PKT_INFO_8821C) +#define BIT_CLEAR_MGQ_PKT_INFO_8821C(x) ((x) & (~BITS_MGQ_PKT_INFO_8821C)) +#define BIT_GET_MGQ_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8821C) & BIT_MASK_MGQ_PKT_INFO_8821C) +#define BIT_SET_MGQ_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_MGQ_PKT_INFO_8821C(x) | BIT_MGQ_PKT_INFO_8821C(v)) /* 2 REG_CMDQ_BCNQ_INFO_8821C */ #define BIT_SHIFT_CMDQ_PKT_INFO_8821C 16 #define BIT_MASK_CMDQ_PKT_INFO_8821C 0xfff -#define BIT_CMDQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_8821C) << BIT_SHIFT_CMDQ_PKT_INFO_8821C) -#define BIT_GET_CMDQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8821C) & BIT_MASK_CMDQ_PKT_INFO_8821C) - - +#define BIT_CMDQ_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO_8821C) << BIT_SHIFT_CMDQ_PKT_INFO_8821C) +#define BITS_CMDQ_PKT_INFO_8821C \ + (BIT_MASK_CMDQ_PKT_INFO_8821C << BIT_SHIFT_CMDQ_PKT_INFO_8821C) +#define BIT_CLEAR_CMDQ_PKT_INFO_8821C(x) ((x) & (~BITS_CMDQ_PKT_INFO_8821C)) +#define BIT_GET_CMDQ_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8821C) & BIT_MASK_CMDQ_PKT_INFO_8821C) +#define BIT_SET_CMDQ_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO_8821C(x) | BIT_CMDQ_PKT_INFO_8821C(v)) #define BIT_SHIFT_BCNQ_PKT_INFO_8821C 0 #define BIT_MASK_BCNQ_PKT_INFO_8821C 0xfff -#define BIT_BCNQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8821C) << BIT_SHIFT_BCNQ_PKT_INFO_8821C) -#define BIT_GET_BCNQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8821C) & BIT_MASK_BCNQ_PKT_INFO_8821C) - - +#define BIT_BCNQ_PKT_INFO_8821C(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO_8821C) << BIT_SHIFT_BCNQ_PKT_INFO_8821C) +#define BITS_BCNQ_PKT_INFO_8821C \ + (BIT_MASK_BCNQ_PKT_INFO_8821C << BIT_SHIFT_BCNQ_PKT_INFO_8821C) +#define BIT_CLEAR_BCNQ_PKT_INFO_8821C(x) ((x) & (~BITS_BCNQ_PKT_INFO_8821C)) +#define BIT_GET_BCNQ_PKT_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8821C) & BIT_MASK_BCNQ_PKT_INFO_8821C) +#define BIT_SET_BCNQ_PKT_INFO_8821C(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO_8821C(x) | BIT_BCNQ_PKT_INFO_8821C(v)) /* 2 REG_USEREG_SETTING_8821C */ #define BIT_NDPA_USEREG_8821C BIT(21) #define BIT_SHIFT_RETRY_USEREG_8821C 19 #define BIT_MASK_RETRY_USEREG_8821C 0x3 -#define BIT_RETRY_USEREG_8821C(x) (((x) & BIT_MASK_RETRY_USEREG_8821C) << BIT_SHIFT_RETRY_USEREG_8821C) -#define BIT_GET_RETRY_USEREG_8821C(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8821C) & BIT_MASK_RETRY_USEREG_8821C) - - +#define BIT_RETRY_USEREG_8821C(x) \ + (((x) & BIT_MASK_RETRY_USEREG_8821C) << BIT_SHIFT_RETRY_USEREG_8821C) +#define BITS_RETRY_USEREG_8821C \ + (BIT_MASK_RETRY_USEREG_8821C << BIT_SHIFT_RETRY_USEREG_8821C) +#define BIT_CLEAR_RETRY_USEREG_8821C(x) ((x) & (~BITS_RETRY_USEREG_8821C)) +#define BIT_GET_RETRY_USEREG_8821C(x) \ + (((x) >> BIT_SHIFT_RETRY_USEREG_8821C) & BIT_MASK_RETRY_USEREG_8821C) +#define BIT_SET_RETRY_USEREG_8821C(x, v) \ + (BIT_CLEAR_RETRY_USEREG_8821C(x) | BIT_RETRY_USEREG_8821C(v)) #define BIT_SHIFT_TRYPKT_USEREG_8821C 17 #define BIT_MASK_TRYPKT_USEREG_8821C 0x3 -#define BIT_TRYPKT_USEREG_8821C(x) (((x) & BIT_MASK_TRYPKT_USEREG_8821C) << BIT_SHIFT_TRYPKT_USEREG_8821C) -#define BIT_GET_TRYPKT_USEREG_8821C(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8821C) & BIT_MASK_TRYPKT_USEREG_8821C) - +#define BIT_TRYPKT_USEREG_8821C(x) \ + (((x) & BIT_MASK_TRYPKT_USEREG_8821C) << BIT_SHIFT_TRYPKT_USEREG_8821C) +#define BITS_TRYPKT_USEREG_8821C \ + (BIT_MASK_TRYPKT_USEREG_8821C << BIT_SHIFT_TRYPKT_USEREG_8821C) +#define BIT_CLEAR_TRYPKT_USEREG_8821C(x) ((x) & (~BITS_TRYPKT_USEREG_8821C)) +#define BIT_GET_TRYPKT_USEREG_8821C(x) \ + (((x) >> BIT_SHIFT_TRYPKT_USEREG_8821C) & BIT_MASK_TRYPKT_USEREG_8821C) +#define BIT_SET_TRYPKT_USEREG_8821C(x, v) \ + (BIT_CLEAR_TRYPKT_USEREG_8821C(x) | BIT_TRYPKT_USEREG_8821C(v)) #define BIT_CTLPKT_USEREG_8821C BIT(16) /* 2 REG_AESIV_SETTING_8821C */ #define BIT_SHIFT_AESIV_OFFSET_8821C 0 -#define BIT_MASK_AESIV_OFFSET_8821C 0xfff -#define BIT_AESIV_OFFSET_8821C(x) (((x) & BIT_MASK_AESIV_OFFSET_8821C) << BIT_SHIFT_AESIV_OFFSET_8821C) -#define BIT_GET_AESIV_OFFSET_8821C(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8821C) & BIT_MASK_AESIV_OFFSET_8821C) - - +#define BIT_MASK_AESIV_OFFSET_8821C 0xfff +#define BIT_AESIV_OFFSET_8821C(x) \ + (((x) & BIT_MASK_AESIV_OFFSET_8821C) << BIT_SHIFT_AESIV_OFFSET_8821C) +#define BITS_AESIV_OFFSET_8821C \ + (BIT_MASK_AESIV_OFFSET_8821C << BIT_SHIFT_AESIV_OFFSET_8821C) +#define BIT_CLEAR_AESIV_OFFSET_8821C(x) ((x) & (~BITS_AESIV_OFFSET_8821C)) +#define BIT_GET_AESIV_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_AESIV_OFFSET_8821C) & BIT_MASK_AESIV_OFFSET_8821C) +#define BIT_SET_AESIV_OFFSET_8821C(x, v) \ + (BIT_CLEAR_AESIV_OFFSET_8821C(x) | BIT_AESIV_OFFSET_8821C(v)) /* 2 REG_BF0_TIME_SETTING_8821C */ #define BIT_BF0_TIMER_SET_8821C BIT(31) @@ -6729,17 +11189,30 @@ #define BIT_SHIFT_BF0_PRETIME_OVER_8821C 16 #define BIT_MASK_BF0_PRETIME_OVER_8821C 0xfff -#define BIT_BF0_PRETIME_OVER_8821C(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8821C) << BIT_SHIFT_BF0_PRETIME_OVER_8821C) -#define BIT_GET_BF0_PRETIME_OVER_8821C(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8821C) & BIT_MASK_BF0_PRETIME_OVER_8821C) - - +#define BIT_BF0_PRETIME_OVER_8821C(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER_8821C) \ + << BIT_SHIFT_BF0_PRETIME_OVER_8821C) +#define BITS_BF0_PRETIME_OVER_8821C \ + (BIT_MASK_BF0_PRETIME_OVER_8821C << BIT_SHIFT_BF0_PRETIME_OVER_8821C) +#define BIT_CLEAR_BF0_PRETIME_OVER_8821C(x) \ + ((x) & (~BITS_BF0_PRETIME_OVER_8821C)) +#define BIT_GET_BF0_PRETIME_OVER_8821C(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8821C) & \ + BIT_MASK_BF0_PRETIME_OVER_8821C) +#define BIT_SET_BF0_PRETIME_OVER_8821C(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER_8821C(x) | BIT_BF0_PRETIME_OVER_8821C(v)) #define BIT_SHIFT_BF0_LIFETIME_8821C 0 #define BIT_MASK_BF0_LIFETIME_8821C 0xffff -#define BIT_BF0_LIFETIME_8821C(x) (((x) & BIT_MASK_BF0_LIFETIME_8821C) << BIT_SHIFT_BF0_LIFETIME_8821C) -#define BIT_GET_BF0_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8821C) & BIT_MASK_BF0_LIFETIME_8821C) - - +#define BIT_BF0_LIFETIME_8821C(x) \ + (((x) & BIT_MASK_BF0_LIFETIME_8821C) << BIT_SHIFT_BF0_LIFETIME_8821C) +#define BITS_BF0_LIFETIME_8821C \ + (BIT_MASK_BF0_LIFETIME_8821C << BIT_SHIFT_BF0_LIFETIME_8821C) +#define BIT_CLEAR_BF0_LIFETIME_8821C(x) ((x) & (~BITS_BF0_LIFETIME_8821C)) +#define BIT_GET_BF0_LIFETIME_8821C(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME_8821C) & BIT_MASK_BF0_LIFETIME_8821C) +#define BIT_SET_BF0_LIFETIME_8821C(x, v) \ + (BIT_CLEAR_BF0_LIFETIME_8821C(x) | BIT_BF0_LIFETIME_8821C(v)) /* 2 REG_BF1_TIME_SETTING_8821C */ #define BIT_BF1_TIMER_SET_8821C BIT(31) @@ -6749,17 +11222,30 @@ #define BIT_SHIFT_BF1_PRETIME_OVER_8821C 16 #define BIT_MASK_BF1_PRETIME_OVER_8821C 0xfff -#define BIT_BF1_PRETIME_OVER_8821C(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8821C) << BIT_SHIFT_BF1_PRETIME_OVER_8821C) -#define BIT_GET_BF1_PRETIME_OVER_8821C(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8821C) & BIT_MASK_BF1_PRETIME_OVER_8821C) - - +#define BIT_BF1_PRETIME_OVER_8821C(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER_8821C) \ + << BIT_SHIFT_BF1_PRETIME_OVER_8821C) +#define BITS_BF1_PRETIME_OVER_8821C \ + (BIT_MASK_BF1_PRETIME_OVER_8821C << BIT_SHIFT_BF1_PRETIME_OVER_8821C) +#define BIT_CLEAR_BF1_PRETIME_OVER_8821C(x) \ + ((x) & (~BITS_BF1_PRETIME_OVER_8821C)) +#define BIT_GET_BF1_PRETIME_OVER_8821C(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8821C) & \ + BIT_MASK_BF1_PRETIME_OVER_8821C) +#define BIT_SET_BF1_PRETIME_OVER_8821C(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER_8821C(x) | BIT_BF1_PRETIME_OVER_8821C(v)) #define BIT_SHIFT_BF1_LIFETIME_8821C 0 #define BIT_MASK_BF1_LIFETIME_8821C 0xffff -#define BIT_BF1_LIFETIME_8821C(x) (((x) & BIT_MASK_BF1_LIFETIME_8821C) << BIT_SHIFT_BF1_LIFETIME_8821C) -#define BIT_GET_BF1_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8821C) & BIT_MASK_BF1_LIFETIME_8821C) - - +#define BIT_BF1_LIFETIME_8821C(x) \ + (((x) & BIT_MASK_BF1_LIFETIME_8821C) << BIT_SHIFT_BF1_LIFETIME_8821C) +#define BITS_BF1_LIFETIME_8821C \ + (BIT_MASK_BF1_LIFETIME_8821C << BIT_SHIFT_BF1_LIFETIME_8821C) +#define BIT_CLEAR_BF1_LIFETIME_8821C(x) ((x) & (~BITS_BF1_LIFETIME_8821C)) +#define BIT_GET_BF1_LIFETIME_8821C(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME_8821C) & BIT_MASK_BF1_LIFETIME_8821C) +#define BIT_SET_BF1_LIFETIME_8821C(x, v) \ + (BIT_CLEAR_BF1_LIFETIME_8821C(x) | BIT_BF1_LIFETIME_8821C(v)) /* 2 REG_BF_TIMEOUT_EN_8821C */ #define BIT_EN_VHT_LDPC_8821C BIT(9) @@ -6771,338 +11257,680 @@ #define BIT_SHIFT_MACID31_0_RELEASE_8821C 0 #define BIT_MASK_MACID31_0_RELEASE_8821C 0xffffffffL -#define BIT_MACID31_0_RELEASE_8821C(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8821C) << BIT_SHIFT_MACID31_0_RELEASE_8821C) -#define BIT_GET_MACID31_0_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8821C) & BIT_MASK_MACID31_0_RELEASE_8821C) - - +#define BIT_MACID31_0_RELEASE_8821C(x) \ + (((x) & BIT_MASK_MACID31_0_RELEASE_8821C) \ + << BIT_SHIFT_MACID31_0_RELEASE_8821C) +#define BITS_MACID31_0_RELEASE_8821C \ + (BIT_MASK_MACID31_0_RELEASE_8821C << BIT_SHIFT_MACID31_0_RELEASE_8821C) +#define BIT_CLEAR_MACID31_0_RELEASE_8821C(x) \ + ((x) & (~BITS_MACID31_0_RELEASE_8821C)) +#define BIT_GET_MACID31_0_RELEASE_8821C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8821C) & \ + BIT_MASK_MACID31_0_RELEASE_8821C) +#define BIT_SET_MACID31_0_RELEASE_8821C(x, v) \ + (BIT_CLEAR_MACID31_0_RELEASE_8821C(x) | BIT_MACID31_0_RELEASE_8821C(v)) /* 2 REG_MACID_RELEASE1_8821C */ #define BIT_SHIFT_MACID63_32_RELEASE_8821C 0 #define BIT_MASK_MACID63_32_RELEASE_8821C 0xffffffffL -#define BIT_MACID63_32_RELEASE_8821C(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8821C) << BIT_SHIFT_MACID63_32_RELEASE_8821C) -#define BIT_GET_MACID63_32_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8821C) & BIT_MASK_MACID63_32_RELEASE_8821C) - - +#define BIT_MACID63_32_RELEASE_8821C(x) \ + (((x) & BIT_MASK_MACID63_32_RELEASE_8821C) \ + << BIT_SHIFT_MACID63_32_RELEASE_8821C) +#define BITS_MACID63_32_RELEASE_8821C \ + (BIT_MASK_MACID63_32_RELEASE_8821C \ + << BIT_SHIFT_MACID63_32_RELEASE_8821C) +#define BIT_CLEAR_MACID63_32_RELEASE_8821C(x) \ + ((x) & (~BITS_MACID63_32_RELEASE_8821C)) +#define BIT_GET_MACID63_32_RELEASE_8821C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8821C) & \ + BIT_MASK_MACID63_32_RELEASE_8821C) +#define BIT_SET_MACID63_32_RELEASE_8821C(x, v) \ + (BIT_CLEAR_MACID63_32_RELEASE_8821C(x) | \ + BIT_MACID63_32_RELEASE_8821C(v)) /* 2 REG_MACID_RELEASE2_8821C */ #define BIT_SHIFT_MACID95_64_RELEASE_8821C 0 #define BIT_MASK_MACID95_64_RELEASE_8821C 0xffffffffL -#define BIT_MACID95_64_RELEASE_8821C(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8821C) << BIT_SHIFT_MACID95_64_RELEASE_8821C) -#define BIT_GET_MACID95_64_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8821C) & BIT_MASK_MACID95_64_RELEASE_8821C) - - +#define BIT_MACID95_64_RELEASE_8821C(x) \ + (((x) & BIT_MASK_MACID95_64_RELEASE_8821C) \ + << BIT_SHIFT_MACID95_64_RELEASE_8821C) +#define BITS_MACID95_64_RELEASE_8821C \ + (BIT_MASK_MACID95_64_RELEASE_8821C \ + << BIT_SHIFT_MACID95_64_RELEASE_8821C) +#define BIT_CLEAR_MACID95_64_RELEASE_8821C(x) \ + ((x) & (~BITS_MACID95_64_RELEASE_8821C)) +#define BIT_GET_MACID95_64_RELEASE_8821C(x) \ + (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8821C) & \ + BIT_MASK_MACID95_64_RELEASE_8821C) +#define BIT_SET_MACID95_64_RELEASE_8821C(x, v) \ + (BIT_CLEAR_MACID95_64_RELEASE_8821C(x) | \ + BIT_MACID95_64_RELEASE_8821C(v)) /* 2 REG_MACID_RELEASE3_8821C */ #define BIT_SHIFT_MACID127_96_RELEASE_8821C 0 #define BIT_MASK_MACID127_96_RELEASE_8821C 0xffffffffL -#define BIT_MACID127_96_RELEASE_8821C(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8821C) << BIT_SHIFT_MACID127_96_RELEASE_8821C) -#define BIT_GET_MACID127_96_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8821C) & BIT_MASK_MACID127_96_RELEASE_8821C) - - +#define BIT_MACID127_96_RELEASE_8821C(x) \ + (((x) & BIT_MASK_MACID127_96_RELEASE_8821C) \ + << BIT_SHIFT_MACID127_96_RELEASE_8821C) +#define BITS_MACID127_96_RELEASE_8821C \ + (BIT_MASK_MACID127_96_RELEASE_8821C \ + << BIT_SHIFT_MACID127_96_RELEASE_8821C) +#define BIT_CLEAR_MACID127_96_RELEASE_8821C(x) \ + ((x) & (~BITS_MACID127_96_RELEASE_8821C)) +#define BIT_GET_MACID127_96_RELEASE_8821C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8821C) & \ + BIT_MASK_MACID127_96_RELEASE_8821C) +#define BIT_SET_MACID127_96_RELEASE_8821C(x, v) \ + (BIT_CLEAR_MACID127_96_RELEASE_8821C(x) | \ + BIT_MACID127_96_RELEASE_8821C(v)) /* 2 REG_MACID_RELEASE_SETTING_8821C */ #define BIT_MACID_VALUE_8821C BIT(7) #define BIT_SHIFT_MACID_OFFSET_8821C 0 #define BIT_MASK_MACID_OFFSET_8821C 0x7f -#define BIT_MACID_OFFSET_8821C(x) (((x) & BIT_MASK_MACID_OFFSET_8821C) << BIT_SHIFT_MACID_OFFSET_8821C) -#define BIT_GET_MACID_OFFSET_8821C(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8821C) & BIT_MASK_MACID_OFFSET_8821C) - - +#define BIT_MACID_OFFSET_8821C(x) \ + (((x) & BIT_MASK_MACID_OFFSET_8821C) << BIT_SHIFT_MACID_OFFSET_8821C) +#define BITS_MACID_OFFSET_8821C \ + (BIT_MASK_MACID_OFFSET_8821C << BIT_SHIFT_MACID_OFFSET_8821C) +#define BIT_CLEAR_MACID_OFFSET_8821C(x) ((x) & (~BITS_MACID_OFFSET_8821C)) +#define BIT_GET_MACID_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_MACID_OFFSET_8821C) & BIT_MASK_MACID_OFFSET_8821C) +#define BIT_SET_MACID_OFFSET_8821C(x, v) \ + (BIT_CLEAR_MACID_OFFSET_8821C(x) | BIT_MACID_OFFSET_8821C(v)) /* 2 REG_FAST_EDCA_VOVI_SETTING_8821C */ #define BIT_SHIFT_VI_FAST_EDCA_TO_8821C 24 #define BIT_MASK_VI_FAST_EDCA_TO_8821C 0xff -#define BIT_VI_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8821C) << BIT_SHIFT_VI_FAST_EDCA_TO_8821C) -#define BIT_GET_VI_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8821C) & BIT_MASK_VI_FAST_EDCA_TO_8821C) - +#define BIT_VI_FAST_EDCA_TO_8821C(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO_8821C) \ + << BIT_SHIFT_VI_FAST_EDCA_TO_8821C) +#define BITS_VI_FAST_EDCA_TO_8821C \ + (BIT_MASK_VI_FAST_EDCA_TO_8821C << BIT_SHIFT_VI_FAST_EDCA_TO_8821C) +#define BIT_CLEAR_VI_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8821C)) +#define BIT_GET_VI_FAST_EDCA_TO_8821C(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8821C) & \ + BIT_MASK_VI_FAST_EDCA_TO_8821C) +#define BIT_SET_VI_FAST_EDCA_TO_8821C(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO_8821C(x) | BIT_VI_FAST_EDCA_TO_8821C(v)) #define BIT_VI_THRESHOLD_SEL_8821C BIT(23) #define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C 16 #define BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C 0x7f -#define BIT_VI_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) -#define BIT_GET_VI_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) - - +#define BIT_VI_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) +#define BITS_VI_FAST_EDCA_PKT_TH_8821C \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8821C(x) \ + ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8821C)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) & \ + BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) +#define BIT_SET_VI_FAST_EDCA_PKT_TH_8821C(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8821C(x) | \ + BIT_VI_FAST_EDCA_PKT_TH_8821C(v)) #define BIT_SHIFT_VO_FAST_EDCA_TO_8821C 8 #define BIT_MASK_VO_FAST_EDCA_TO_8821C 0xff -#define BIT_VO_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8821C) << BIT_SHIFT_VO_FAST_EDCA_TO_8821C) -#define BIT_GET_VO_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8821C) & BIT_MASK_VO_FAST_EDCA_TO_8821C) - +#define BIT_VO_FAST_EDCA_TO_8821C(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO_8821C) \ + << BIT_SHIFT_VO_FAST_EDCA_TO_8821C) +#define BITS_VO_FAST_EDCA_TO_8821C \ + (BIT_MASK_VO_FAST_EDCA_TO_8821C << BIT_SHIFT_VO_FAST_EDCA_TO_8821C) +#define BIT_CLEAR_VO_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8821C)) +#define BIT_GET_VO_FAST_EDCA_TO_8821C(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8821C) & \ + BIT_MASK_VO_FAST_EDCA_TO_8821C) +#define BIT_SET_VO_FAST_EDCA_TO_8821C(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO_8821C(x) | BIT_VO_FAST_EDCA_TO_8821C(v)) #define BIT_VO_THRESHOLD_SEL_8821C BIT(7) #define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C 0 #define BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C 0x7f -#define BIT_VO_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) -#define BIT_GET_VO_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) - - +#define BIT_VO_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) +#define BITS_VO_FAST_EDCA_PKT_TH_8821C \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8821C(x) \ + ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8821C)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) & \ + BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) +#define BIT_SET_VO_FAST_EDCA_PKT_TH_8821C(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8821C(x) | \ + BIT_VO_FAST_EDCA_PKT_TH_8821C(v)) /* 2 REG_FAST_EDCA_BEBK_SETTING_8821C */ #define BIT_SHIFT_BK_FAST_EDCA_TO_8821C 24 #define BIT_MASK_BK_FAST_EDCA_TO_8821C 0xff -#define BIT_BK_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8821C) << BIT_SHIFT_BK_FAST_EDCA_TO_8821C) -#define BIT_GET_BK_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8821C) & BIT_MASK_BK_FAST_EDCA_TO_8821C) - +#define BIT_BK_FAST_EDCA_TO_8821C(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO_8821C) \ + << BIT_SHIFT_BK_FAST_EDCA_TO_8821C) +#define BITS_BK_FAST_EDCA_TO_8821C \ + (BIT_MASK_BK_FAST_EDCA_TO_8821C << BIT_SHIFT_BK_FAST_EDCA_TO_8821C) +#define BIT_CLEAR_BK_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8821C)) +#define BIT_GET_BK_FAST_EDCA_TO_8821C(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8821C) & \ + BIT_MASK_BK_FAST_EDCA_TO_8821C) +#define BIT_SET_BK_FAST_EDCA_TO_8821C(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO_8821C(x) | BIT_BK_FAST_EDCA_TO_8821C(v)) #define BIT_BK_THRESHOLD_SEL_8821C BIT(23) #define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C 16 #define BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C 0x7f -#define BIT_BK_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) -#define BIT_GET_BK_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) - - +#define BIT_BK_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) +#define BITS_BK_FAST_EDCA_PKT_TH_8821C \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8821C(x) \ + ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8821C)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) & \ + BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) +#define BIT_SET_BK_FAST_EDCA_PKT_TH_8821C(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8821C(x) | \ + BIT_BK_FAST_EDCA_PKT_TH_8821C(v)) #define BIT_SHIFT_BE_FAST_EDCA_TO_8821C 8 #define BIT_MASK_BE_FAST_EDCA_TO_8821C 0xff -#define BIT_BE_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8821C) << BIT_SHIFT_BE_FAST_EDCA_TO_8821C) -#define BIT_GET_BE_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8821C) & BIT_MASK_BE_FAST_EDCA_TO_8821C) - +#define BIT_BE_FAST_EDCA_TO_8821C(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO_8821C) \ + << BIT_SHIFT_BE_FAST_EDCA_TO_8821C) +#define BITS_BE_FAST_EDCA_TO_8821C \ + (BIT_MASK_BE_FAST_EDCA_TO_8821C << BIT_SHIFT_BE_FAST_EDCA_TO_8821C) +#define BIT_CLEAR_BE_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8821C)) +#define BIT_GET_BE_FAST_EDCA_TO_8821C(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8821C) & \ + BIT_MASK_BE_FAST_EDCA_TO_8821C) +#define BIT_SET_BE_FAST_EDCA_TO_8821C(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO_8821C(x) | BIT_BE_FAST_EDCA_TO_8821C(v)) #define BIT_BE_THRESHOLD_SEL_8821C BIT(7) #define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C 0 #define BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C 0x7f -#define BIT_BE_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) -#define BIT_GET_BE_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) - - +#define BIT_BE_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) +#define BITS_BE_FAST_EDCA_PKT_TH_8821C \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8821C(x) \ + ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8821C)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8821C(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) & \ + BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) +#define BIT_SET_BE_FAST_EDCA_PKT_TH_8821C(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8821C(x) | \ + BIT_BE_FAST_EDCA_PKT_TH_8821C(v)) /* 2 REG_MACID_DROP0_8821C */ #define BIT_SHIFT_MACID31_0_DROP_8821C 0 #define BIT_MASK_MACID31_0_DROP_8821C 0xffffffffL -#define BIT_MACID31_0_DROP_8821C(x) (((x) & BIT_MASK_MACID31_0_DROP_8821C) << BIT_SHIFT_MACID31_0_DROP_8821C) -#define BIT_GET_MACID31_0_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8821C) & BIT_MASK_MACID31_0_DROP_8821C) - - +#define BIT_MACID31_0_DROP_8821C(x) \ + (((x) & BIT_MASK_MACID31_0_DROP_8821C) \ + << BIT_SHIFT_MACID31_0_DROP_8821C) +#define BITS_MACID31_0_DROP_8821C \ + (BIT_MASK_MACID31_0_DROP_8821C << BIT_SHIFT_MACID31_0_DROP_8821C) +#define BIT_CLEAR_MACID31_0_DROP_8821C(x) ((x) & (~BITS_MACID31_0_DROP_8821C)) +#define BIT_GET_MACID31_0_DROP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_DROP_8821C) & \ + BIT_MASK_MACID31_0_DROP_8821C) +#define BIT_SET_MACID31_0_DROP_8821C(x, v) \ + (BIT_CLEAR_MACID31_0_DROP_8821C(x) | BIT_MACID31_0_DROP_8821C(v)) /* 2 REG_MACID_DROP1_8821C */ #define BIT_SHIFT_MACID63_32_DROP_8821C 0 #define BIT_MASK_MACID63_32_DROP_8821C 0xffffffffL -#define BIT_MACID63_32_DROP_8821C(x) (((x) & BIT_MASK_MACID63_32_DROP_8821C) << BIT_SHIFT_MACID63_32_DROP_8821C) -#define BIT_GET_MACID63_32_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8821C) & BIT_MASK_MACID63_32_DROP_8821C) - - +#define BIT_MACID63_32_DROP_8821C(x) \ + (((x) & BIT_MASK_MACID63_32_DROP_8821C) \ + << BIT_SHIFT_MACID63_32_DROP_8821C) +#define BITS_MACID63_32_DROP_8821C \ + (BIT_MASK_MACID63_32_DROP_8821C << BIT_SHIFT_MACID63_32_DROP_8821C) +#define BIT_CLEAR_MACID63_32_DROP_8821C(x) ((x) & (~BITS_MACID63_32_DROP_8821C)) +#define BIT_GET_MACID63_32_DROP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_DROP_8821C) & \ + BIT_MASK_MACID63_32_DROP_8821C) +#define BIT_SET_MACID63_32_DROP_8821C(x, v) \ + (BIT_CLEAR_MACID63_32_DROP_8821C(x) | BIT_MACID63_32_DROP_8821C(v)) /* 2 REG_MACID_DROP2_8821C */ #define BIT_SHIFT_MACID95_64_DROP_8821C 0 #define BIT_MASK_MACID95_64_DROP_8821C 0xffffffffL -#define BIT_MACID95_64_DROP_8821C(x) (((x) & BIT_MASK_MACID95_64_DROP_8821C) << BIT_SHIFT_MACID95_64_DROP_8821C) -#define BIT_GET_MACID95_64_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8821C) & BIT_MASK_MACID95_64_DROP_8821C) - - +#define BIT_MACID95_64_DROP_8821C(x) \ + (((x) & BIT_MASK_MACID95_64_DROP_8821C) \ + << BIT_SHIFT_MACID95_64_DROP_8821C) +#define BITS_MACID95_64_DROP_8821C \ + (BIT_MASK_MACID95_64_DROP_8821C << BIT_SHIFT_MACID95_64_DROP_8821C) +#define BIT_CLEAR_MACID95_64_DROP_8821C(x) ((x) & (~BITS_MACID95_64_DROP_8821C)) +#define BIT_GET_MACID95_64_DROP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID95_64_DROP_8821C) & \ + BIT_MASK_MACID95_64_DROP_8821C) +#define BIT_SET_MACID95_64_DROP_8821C(x, v) \ + (BIT_CLEAR_MACID95_64_DROP_8821C(x) | BIT_MACID95_64_DROP_8821C(v)) /* 2 REG_MACID_DROP3_8821C */ #define BIT_SHIFT_MACID127_96_DROP_8821C 0 #define BIT_MASK_MACID127_96_DROP_8821C 0xffffffffL -#define BIT_MACID127_96_DROP_8821C(x) (((x) & BIT_MASK_MACID127_96_DROP_8821C) << BIT_SHIFT_MACID127_96_DROP_8821C) -#define BIT_GET_MACID127_96_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8821C) & BIT_MASK_MACID127_96_DROP_8821C) - - +#define BIT_MACID127_96_DROP_8821C(x) \ + (((x) & BIT_MASK_MACID127_96_DROP_8821C) \ + << BIT_SHIFT_MACID127_96_DROP_8821C) +#define BITS_MACID127_96_DROP_8821C \ + (BIT_MASK_MACID127_96_DROP_8821C << BIT_SHIFT_MACID127_96_DROP_8821C) +#define BIT_CLEAR_MACID127_96_DROP_8821C(x) \ + ((x) & (~BITS_MACID127_96_DROP_8821C)) +#define BIT_GET_MACID127_96_DROP_8821C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_DROP_8821C) & \ + BIT_MASK_MACID127_96_DROP_8821C) +#define BIT_SET_MACID127_96_DROP_8821C(x, v) \ + (BIT_CLEAR_MACID127_96_DROP_8821C(x) | BIT_MACID127_96_DROP_8821C(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_0_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_0_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) - - +#define BIT_R_MACID_RELEASE_SUCCESS_0_8821C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) +#define BITS_R_MACID_RELEASE_SUCCESS_0_8821C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8821C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8821C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8821C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8821C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8821C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_0_8821C(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_1_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_1_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) - - +#define BIT_R_MACID_RELEASE_SUCCESS_1_8821C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) +#define BITS_R_MACID_RELEASE_SUCCESS_1_8821C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8821C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8821C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8821C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8821C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_1_8821C(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_2_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_2_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) - - +#define BIT_R_MACID_RELEASE_SUCCESS_2_8821C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) +#define BITS_R_MACID_RELEASE_SUCCESS_2_8821C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8821C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8821C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8821C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8821C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8821C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_2_8821C(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_3_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_3_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) - - - -/* 2 REG_MGG_FIFO_CRTL_8821C */ -#define BIT_R_MGG_FIFO_EN_8821C BIT(31) - -#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C 28 -#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C 0x7 -#define BIT_R_MGG_FIFO_PG_SIZE_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C) -#define BIT_GET_R_MGG_FIFO_PG_SIZE_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C) - - - -#define BIT_SHIFT_R_MGG_FIFO_START_PG_8821C 16 -#define BIT_MASK_R_MGG_FIFO_START_PG_8821C 0xfff -#define BIT_R_MGG_FIFO_START_PG_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8821C) << BIT_SHIFT_R_MGG_FIFO_START_PG_8821C) -#define BIT_GET_R_MGG_FIFO_START_PG_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8821C) & BIT_MASK_R_MGG_FIFO_START_PG_8821C) - - - -#define BIT_SHIFT_R_MGG_FIFO_SIZE_8821C 14 -#define BIT_MASK_R_MGG_FIFO_SIZE_8821C 0x3 -#define BIT_R_MGG_FIFO_SIZE_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8821C) << BIT_SHIFT_R_MGG_FIFO_SIZE_8821C) -#define BIT_GET_R_MGG_FIFO_SIZE_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8821C) & BIT_MASK_R_MGG_FIFO_SIZE_8821C) - - -#define BIT_R_MGG_FIFO_PAUSE_8821C BIT(13) - -#define BIT_SHIFT_R_MGG_FIFO_RPTR_8821C 8 -#define BIT_MASK_R_MGG_FIFO_RPTR_8821C 0x1f -#define BIT_R_MGG_FIFO_RPTR_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8821C) << BIT_SHIFT_R_MGG_FIFO_RPTR_8821C) -#define BIT_GET_R_MGG_FIFO_RPTR_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8821C) & BIT_MASK_R_MGG_FIFO_RPTR_8821C) - - -#define BIT_R_MGG_FIFO_OV_8821C BIT(7) -#define BIT_R_MGG_FIFO_WPTR_ERROR_8821C BIT(6) -#define BIT_R_EN_CPU_LIFETIME_8821C BIT(5) - -#define BIT_SHIFT_R_MGG_FIFO_WPTR_8821C 0 -#define BIT_MASK_R_MGG_FIFO_WPTR_8821C 0x1f -#define BIT_R_MGG_FIFO_WPTR_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8821C) << BIT_SHIFT_R_MGG_FIFO_WPTR_8821C) -#define BIT_GET_R_MGG_FIFO_WPTR_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8821C) & BIT_MASK_R_MGG_FIFO_WPTR_8821C) - - - -/* 2 REG_MGG_FIFO_INT_8821C */ - -#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C 16 -#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C 0xffff -#define BIT_R_MGG_FIFO_INT_FLAG_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C) -#define BIT_GET_R_MGG_FIFO_INT_FLAG_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C) - - - -#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C 0 -#define BIT_MASK_R_MGG_FIFO_INT_MASK_8821C 0xffff -#define BIT_R_MGG_FIFO_INT_MASK_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8821C) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C) -#define BIT_GET_R_MGG_FIFO_INT_MASK_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C) & BIT_MASK_R_MGG_FIFO_INT_MASK_8821C) - - - -/* 2 REG_MGG_FIFO_LIFETIME_8821C */ - -#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C 16 -#define BIT_MASK_R_MGG_FIFO_LIFETIME_8821C 0xffff -#define BIT_R_MGG_FIFO_LIFETIME_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8821C) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C) -#define BIT_GET_R_MGG_FIFO_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C) & BIT_MASK_R_MGG_FIFO_LIFETIME_8821C) - - - -#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C 0 -#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C 0xffff -#define BIT_R_MGG_FIFO_VALID_MAP_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C) -#define BIT_GET_R_MGG_FIFO_VALID_MAP_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C) - - +#define BIT_R_MACID_RELEASE_SUCCESS_3_8821C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) +#define BITS_R_MACID_RELEASE_SUCCESS_3_8821C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8821C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8821C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8821C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8821C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8821C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_3_8821C(v)) + +/* 2 REG_MGQ_FIFO_WRITE_POINTER_8821C */ +#define BIT_MGQ_FIFO_OV_8821C BIT(7) +#define BIT_MGQ_FIFO_WPTR_ERROR_8821C BIT(6) +#define BIT_EN_MGQ_FIFO_LIFETIME_8821C BIT(5) + +#define BIT_SHIFT_MGQ_FIFO_WPTR_8821C 0 +#define BIT_MASK_MGQ_FIFO_WPTR_8821C 0x1f +#define BIT_MGQ_FIFO_WPTR_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_WPTR_8821C) << BIT_SHIFT_MGQ_FIFO_WPTR_8821C) +#define BITS_MGQ_FIFO_WPTR_8821C \ + (BIT_MASK_MGQ_FIFO_WPTR_8821C << BIT_SHIFT_MGQ_FIFO_WPTR_8821C) +#define BIT_CLEAR_MGQ_FIFO_WPTR_8821C(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8821C)) +#define BIT_GET_MGQ_FIFO_WPTR_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8821C) & BIT_MASK_MGQ_FIFO_WPTR_8821C) +#define BIT_SET_MGQ_FIFO_WPTR_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_WPTR_8821C(x) | BIT_MGQ_FIFO_WPTR_8821C(v)) + +/* 2 REG_MGQ_FIFO_READ_POINTER_8821C */ + +#define BIT_SHIFT_MGQ_FIFO_SIZE_8821C 14 +#define BIT_MASK_MGQ_FIFO_SIZE_8821C 0x3 +#define BIT_MGQ_FIFO_SIZE_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_SIZE_8821C) << BIT_SHIFT_MGQ_FIFO_SIZE_8821C) +#define BITS_MGQ_FIFO_SIZE_8821C \ + (BIT_MASK_MGQ_FIFO_SIZE_8821C << BIT_SHIFT_MGQ_FIFO_SIZE_8821C) +#define BIT_CLEAR_MGQ_FIFO_SIZE_8821C(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8821C)) +#define BIT_GET_MGQ_FIFO_SIZE_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8821C) & BIT_MASK_MGQ_FIFO_SIZE_8821C) +#define BIT_SET_MGQ_FIFO_SIZE_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_SIZE_8821C(x) | BIT_MGQ_FIFO_SIZE_8821C(v)) + +#define BIT_MGQ_FIFO_PAUSE_8821C BIT(13) + +#define BIT_SHIFT_MGQ_FIFO_RPTR_8821C 8 +#define BIT_MASK_MGQ_FIFO_RPTR_8821C 0x1f +#define BIT_MGQ_FIFO_RPTR_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_RPTR_8821C) << BIT_SHIFT_MGQ_FIFO_RPTR_8821C) +#define BITS_MGQ_FIFO_RPTR_8821C \ + (BIT_MASK_MGQ_FIFO_RPTR_8821C << BIT_SHIFT_MGQ_FIFO_RPTR_8821C) +#define BIT_CLEAR_MGQ_FIFO_RPTR_8821C(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8821C)) +#define BIT_GET_MGQ_FIFO_RPTR_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8821C) & BIT_MASK_MGQ_FIFO_RPTR_8821C) +#define BIT_SET_MGQ_FIFO_RPTR_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_RPTR_8821C(x) | BIT_MGQ_FIFO_RPTR_8821C(v)) + +/* 2 REG_MGQ_FIFO_ENABLE_8821C */ +#define BIT_MGQ_FIFO_EN_8821C BIT(15) + +#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C 12 +#define BIT_MASK_MGQ_FIFO_PG_SIZE_8821C 0x7 +#define BIT_MGQ_FIFO_PG_SIZE_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8821C) \ + << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C) +#define BITS_MGQ_FIFO_PG_SIZE_8821C \ + (BIT_MASK_MGQ_FIFO_PG_SIZE_8821C << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C) +#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_PG_SIZE_8821C)) +#define BIT_GET_MGQ_FIFO_PG_SIZE_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C) & \ + BIT_MASK_MGQ_FIFO_PG_SIZE_8821C) +#define BIT_SET_MGQ_FIFO_PG_SIZE_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PG_SIZE_8821C(x) | BIT_MGQ_FIFO_PG_SIZE_8821C(v)) + +#define BIT_SHIFT_MGQ_FIFO_START_PG_8821C 0 +#define BIT_MASK_MGQ_FIFO_START_PG_8821C 0xfff +#define BIT_MGQ_FIFO_START_PG_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_START_PG_8821C) \ + << BIT_SHIFT_MGQ_FIFO_START_PG_8821C) +#define BITS_MGQ_FIFO_START_PG_8821C \ + (BIT_MASK_MGQ_FIFO_START_PG_8821C << BIT_SHIFT_MGQ_FIFO_START_PG_8821C) +#define BIT_CLEAR_MGQ_FIFO_START_PG_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_START_PG_8821C)) +#define BIT_GET_MGQ_FIFO_START_PG_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8821C) & \ + BIT_MASK_MGQ_FIFO_START_PG_8821C) +#define BIT_SET_MGQ_FIFO_START_PG_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_START_PG_8821C(x) | BIT_MGQ_FIFO_START_PG_8821C(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8821C */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C 0xffff +#define BIT_MGQ_FIFO_REL_INT_MASK_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C) +#define BITS_MGQ_FIFO_REL_INT_MASK_8821C \ + (BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8821C)) +#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C) & \ + BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C) +#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8821C(x) | \ + BIT_MGQ_FIFO_REL_INT_MASK_8821C(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C 0xffff +#define BIT_MGQ_FIFO_REL_INT_FLAG_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C) +#define BITS_MGQ_FIFO_REL_INT_FLAG_8821C \ + (BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8821C)) +#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C) & \ + BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C) +#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8821C(x) | \ + BIT_MGQ_FIFO_REL_INT_FLAG_8821C(v)) + +/* 2 REG_MGQ_FIFO_VALID_MAP_8821C */ + +#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C 0 +#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C 0xffff +#define BIT_MGQ_FIFO_PKT_VALID_MAP_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C) \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C) +#define BITS_MGQ_FIFO_PKT_VALID_MAP_8821C \ + (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C) +#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8821C)) +#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C) & \ + BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C) +#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8821C(x) | \ + BIT_MGQ_FIFO_PKT_VALID_MAP_8821C(v)) + +/* 2 REG_MGQ_FIFO_LIFETIME_8821C */ + +#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C 0 +#define BIT_MASK_MGQ_FIFO_LIFETIME_8821C 0xffff +#define BIT_MGQ_FIFO_LIFETIME_8821C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8821C) \ + << BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C) +#define BITS_MGQ_FIFO_LIFETIME_8821C \ + (BIT_MASK_MGQ_FIFO_LIFETIME_8821C << BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C) +#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8821C(x) \ + ((x) & (~BITS_MGQ_FIFO_LIFETIME_8821C)) +#define BIT_GET_MGQ_FIFO_LIFETIME_8821C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C) & \ + BIT_MASK_MGQ_FIFO_LIFETIME_8821C) +#define BIT_SET_MGQ_FIFO_LIFETIME_8821C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_LIFETIME_8821C(x) | BIT_MGQ_FIFO_LIFETIME_8821C(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x7f -#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) - +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) +#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(v)) + +/* 2 REG_SHCUT_SETTING_8821C */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE0_8821C */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE1_8821C */ + +/* 2 REG_SHCUT_LLC_OUI0_8821C */ + +/* 2 REG_SHCUT_LLC_OUI1_8821C */ + +/* 2 REG_SHCUT_LLC_OUI2_8821C */ + +/* 2 REG_MU_TX_CTL_8821C */ +#define BIT_R_MU_P1_WAIT_STATE_EN_8821C BIT(16) + +#define BIT_SHIFT_R_MU_RL_8821C 12 +#define BIT_MASK_R_MU_RL_8821C 0xf +#define BIT_R_MU_RL_8821C(x) \ + (((x) & BIT_MASK_R_MU_RL_8821C) << BIT_SHIFT_R_MU_RL_8821C) +#define BITS_R_MU_RL_8821C (BIT_MASK_R_MU_RL_8821C << BIT_SHIFT_R_MU_RL_8821C) +#define BIT_CLEAR_R_MU_RL_8821C(x) ((x) & (~BITS_R_MU_RL_8821C)) +#define BIT_GET_R_MU_RL_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_RL_8821C) & BIT_MASK_R_MU_RL_8821C) +#define BIT_SET_R_MU_RL_8821C(x, v) \ + (BIT_CLEAR_R_MU_RL_8821C(x) | BIT_R_MU_RL_8821C(v)) - -/* 2 REG_MU_TX_CTL_8821C (NOT SUPPORT) */ #define BIT_R_FORCE_P1_RATEDOWN_8821C BIT(11) #define BIT_SHIFT_R_MU_TAB_SEL_8821C 8 #define BIT_MASK_R_MU_TAB_SEL_8821C 0x7 -#define BIT_R_MU_TAB_SEL_8821C(x) (((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C) -#define BIT_GET_R_MU_TAB_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8821C) & BIT_MASK_R_MU_TAB_SEL_8821C) - +#define BIT_R_MU_TAB_SEL_8821C(x) \ + (((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C) +#define BITS_R_MU_TAB_SEL_8821C \ + (BIT_MASK_R_MU_TAB_SEL_8821C << BIT_SHIFT_R_MU_TAB_SEL_8821C) +#define BIT_CLEAR_R_MU_TAB_SEL_8821C(x) ((x) & (~BITS_R_MU_TAB_SEL_8821C)) +#define BIT_GET_R_MU_TAB_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8821C) & BIT_MASK_R_MU_TAB_SEL_8821C) +#define BIT_SET_R_MU_TAB_SEL_8821C(x, v) \ + (BIT_CLEAR_R_MU_TAB_SEL_8821C(x) | BIT_R_MU_TAB_SEL_8821C(v)) #define BIT_R_EN_MU_MIMO_8821C BIT(7) #define BIT_R_EN_REVERS_GTAB_8821C BIT(6) #define BIT_SHIFT_R_MU_TABLE_VALID_8821C 0 #define BIT_MASK_R_MU_TABLE_VALID_8821C 0x3f -#define BIT_R_MU_TABLE_VALID_8821C(x) (((x) & BIT_MASK_R_MU_TABLE_VALID_8821C) << BIT_SHIFT_R_MU_TABLE_VALID_8821C) -#define BIT_GET_R_MU_TABLE_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8821C) & BIT_MASK_R_MU_TABLE_VALID_8821C) - - - -/* 2 REG_MU_STA_GID_VLD_8821C (NOT SUPPORT) */ - -/* 2 REG_NOT_VALID_8821C */ - -#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C 0 -#define BIT_MASK_R_MU_STA_GTAB_VALID_8821C 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) -#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) - - +#define BIT_R_MU_TABLE_VALID_8821C(x) \ + (((x) & BIT_MASK_R_MU_TABLE_VALID_8821C) \ + << BIT_SHIFT_R_MU_TABLE_VALID_8821C) +#define BITS_R_MU_TABLE_VALID_8821C \ + (BIT_MASK_R_MU_TABLE_VALID_8821C << BIT_SHIFT_R_MU_TABLE_VALID_8821C) +#define BIT_CLEAR_R_MU_TABLE_VALID_8821C(x) \ + ((x) & (~BITS_R_MU_TABLE_VALID_8821C)) +#define BIT_GET_R_MU_TABLE_VALID_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8821C) & \ + BIT_MASK_R_MU_TABLE_VALID_8821C) +#define BIT_SET_R_MU_TABLE_VALID_8821C(x, v) \ + (BIT_CLEAR_R_MU_TABLE_VALID_8821C(x) | BIT_R_MU_TABLE_VALID_8821C(v)) + +/* 2 REG_MU_STA_GID_VLD_8821C */ #define BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C 0 #define BIT_MASK_R_MU_STA_GTAB_VALID_8821C 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) -#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) - - - -/* 2 REG_MU_STA_USER_POS_INFO_8821C (NOT SUPPORT) */ - -/* 2 REG_NOT_VALID_8821C */ - -#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C 0 -#define BIT_MASK_R_MU_STA_GTAB_POSITION_8821C 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) - - - -#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C 0 -#define BIT_MASK_R_MU_STA_GTAB_POSITION_8821C 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) - - - -/* 2 REG_MU_TRX_DBG_CNT_8821C (NOT SUPPORT) */ +#define BIT_R_MU_STA_GTAB_VALID_8821C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) +#define BITS_R_MU_STA_GTAB_VALID_8821C \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8821C \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8821C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8821C)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8821C) +#define BIT_SET_R_MU_STA_GTAB_VALID_8821C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8821C(x) | \ + BIT_R_MU_STA_GTAB_VALID_8821C(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_8821C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_L_8821C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C) +#define BITS_R_MU_STA_GTAB_POSITION_L_8821C \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8821C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_L_8821C)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_L_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C) +#define BIT_SET_R_MU_STA_GTAB_POSITION_L_8821C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8821C(x) | \ + BIT_R_MU_STA_GTAB_POSITION_L_8821C(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_H_8821C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_H_8821C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C) +#define BITS_R_MU_STA_GTAB_POSITION_H_8821C \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8821C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_H_8821C)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_H_8821C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C) +#define BIT_SET_R_MU_STA_GTAB_POSITION_H_8821C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8821C(x) | \ + BIT_R_MU_STA_GTAB_POSITION_H_8821C(v)) + +/* 2 REG_MU_TRX_DBG_CNT_8821C */ #define BIT_MU_DNGCNT_RST_8821C BIT(20) #define BIT_SHIFT_MU_DBGCNT_SEL_8821C 16 #define BIT_MASK_MU_DBGCNT_SEL_8821C 0xf -#define BIT_MU_DBGCNT_SEL_8821C(x) (((x) & BIT_MASK_MU_DBGCNT_SEL_8821C) << BIT_SHIFT_MU_DBGCNT_SEL_8821C) -#define BIT_GET_MU_DBGCNT_SEL_8821C(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8821C) & BIT_MASK_MU_DBGCNT_SEL_8821C) - - +#define BIT_MU_DBGCNT_SEL_8821C(x) \ + (((x) & BIT_MASK_MU_DBGCNT_SEL_8821C) << BIT_SHIFT_MU_DBGCNT_SEL_8821C) +#define BITS_MU_DBGCNT_SEL_8821C \ + (BIT_MASK_MU_DBGCNT_SEL_8821C << BIT_SHIFT_MU_DBGCNT_SEL_8821C) +#define BIT_CLEAR_MU_DBGCNT_SEL_8821C(x) ((x) & (~BITS_MU_DBGCNT_SEL_8821C)) +#define BIT_GET_MU_DBGCNT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8821C) & BIT_MASK_MU_DBGCNT_SEL_8821C) +#define BIT_SET_MU_DBGCNT_SEL_8821C(x, v) \ + (BIT_CLEAR_MU_DBGCNT_SEL_8821C(x) | BIT_MU_DBGCNT_SEL_8821C(v)) #define BIT_SHIFT_MU_DNGCNT_8821C 0 #define BIT_MASK_MU_DNGCNT_8821C 0xffff -#define BIT_MU_DNGCNT_8821C(x) (((x) & BIT_MASK_MU_DNGCNT_8821C) << BIT_SHIFT_MU_DNGCNT_8821C) -#define BIT_GET_MU_DNGCNT_8821C(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8821C) & BIT_MASK_MU_DNGCNT_8821C) - - +#define BIT_MU_DNGCNT_8821C(x) \ + (((x) & BIT_MASK_MU_DNGCNT_8821C) << BIT_SHIFT_MU_DNGCNT_8821C) +#define BITS_MU_DNGCNT_8821C \ + (BIT_MASK_MU_DNGCNT_8821C << BIT_SHIFT_MU_DNGCNT_8821C) +#define BIT_CLEAR_MU_DNGCNT_8821C(x) ((x) & (~BITS_MU_DNGCNT_8821C)) +#define BIT_GET_MU_DNGCNT_8821C(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_8821C) & BIT_MASK_MU_DNGCNT_8821C) +#define BIT_SET_MU_DNGCNT_8821C(x, v) \ + (BIT_CLEAR_MU_DNGCNT_8821C(x) | BIT_MU_DNGCNT_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7110,24 +11938,32 @@ #define BIT_SHIFT_TXOPLIMIT_8821C 16 #define BIT_MASK_TXOPLIMIT_8821C 0x7ff -#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) -#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) - - +#define BIT_TXOPLIMIT_8821C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BITS_TXOPLIMIT_8821C \ + (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C)) +#define BIT_GET_TXOPLIMIT_8821C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) +#define BIT_SET_TXOPLIMIT_8821C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v)) #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C) +#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C)) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) - - +#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v)) #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) -#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) - - +#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C) +#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C)) +#define BIT_GET_AIFS_8821C(x) \ + (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) +#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v)) /* 2 REG_EDCA_VI_PARAM_8821C */ @@ -7135,24 +11971,32 @@ #define BIT_SHIFT_TXOPLIMIT_8821C 16 #define BIT_MASK_TXOPLIMIT_8821C 0x7ff -#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) -#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) - - +#define BIT_TXOPLIMIT_8821C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BITS_TXOPLIMIT_8821C \ + (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C)) +#define BIT_GET_TXOPLIMIT_8821C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) +#define BIT_SET_TXOPLIMIT_8821C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v)) #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C) +#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C)) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) - - +#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v)) #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) -#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) - - +#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C) +#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C)) +#define BIT_GET_AIFS_8821C(x) \ + (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) +#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v)) /* 2 REG_EDCA_BE_PARAM_8821C */ @@ -7160,24 +12004,32 @@ #define BIT_SHIFT_TXOPLIMIT_8821C 16 #define BIT_MASK_TXOPLIMIT_8821C 0x7ff -#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) -#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) - - +#define BIT_TXOPLIMIT_8821C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BITS_TXOPLIMIT_8821C \ + (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C)) +#define BIT_GET_TXOPLIMIT_8821C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) +#define BIT_SET_TXOPLIMIT_8821C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v)) #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C) +#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C)) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) - - +#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v)) #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) -#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) - - +#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C) +#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C)) +#define BIT_GET_AIFS_8821C(x) \ + (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) +#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v)) /* 2 REG_EDCA_BK_PARAM_8821C */ @@ -7185,47 +12037,69 @@ #define BIT_SHIFT_TXOPLIMIT_8821C 16 #define BIT_MASK_TXOPLIMIT_8821C 0x7ff -#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) -#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) - - +#define BIT_TXOPLIMIT_8821C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BITS_TXOPLIMIT_8821C \ + (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C)) +#define BIT_GET_TXOPLIMIT_8821C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) +#define BIT_SET_TXOPLIMIT_8821C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v)) #define BIT_SHIFT_CW_8821C 8 #define BIT_MASK_CW_8821C 0xff #define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C) +#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C)) #define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) - - +#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v)) #define BIT_SHIFT_AIFS_8821C 0 #define BIT_MASK_AIFS_8821C 0xff #define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) -#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) - - +#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C) +#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C)) +#define BIT_GET_AIFS_8821C(x) \ + (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) +#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v)) /* 2 REG_BCNTCFG_8821C */ #define BIT_SHIFT_BCNCW_MAX_8821C 12 #define BIT_MASK_BCNCW_MAX_8821C 0xf -#define BIT_BCNCW_MAX_8821C(x) (((x) & BIT_MASK_BCNCW_MAX_8821C) << BIT_SHIFT_BCNCW_MAX_8821C) -#define BIT_GET_BCNCW_MAX_8821C(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8821C) & BIT_MASK_BCNCW_MAX_8821C) - - +#define BIT_BCNCW_MAX_8821C(x) \ + (((x) & BIT_MASK_BCNCW_MAX_8821C) << BIT_SHIFT_BCNCW_MAX_8821C) +#define BITS_BCNCW_MAX_8821C \ + (BIT_MASK_BCNCW_MAX_8821C << BIT_SHIFT_BCNCW_MAX_8821C) +#define BIT_CLEAR_BCNCW_MAX_8821C(x) ((x) & (~BITS_BCNCW_MAX_8821C)) +#define BIT_GET_BCNCW_MAX_8821C(x) \ + (((x) >> BIT_SHIFT_BCNCW_MAX_8821C) & BIT_MASK_BCNCW_MAX_8821C) +#define BIT_SET_BCNCW_MAX_8821C(x, v) \ + (BIT_CLEAR_BCNCW_MAX_8821C(x) | BIT_BCNCW_MAX_8821C(v)) #define BIT_SHIFT_BCNCW_MIN_8821C 8 #define BIT_MASK_BCNCW_MIN_8821C 0xf -#define BIT_BCNCW_MIN_8821C(x) (((x) & BIT_MASK_BCNCW_MIN_8821C) << BIT_SHIFT_BCNCW_MIN_8821C) -#define BIT_GET_BCNCW_MIN_8821C(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8821C) & BIT_MASK_BCNCW_MIN_8821C) - - +#define BIT_BCNCW_MIN_8821C(x) \ + (((x) & BIT_MASK_BCNCW_MIN_8821C) << BIT_SHIFT_BCNCW_MIN_8821C) +#define BITS_BCNCW_MIN_8821C \ + (BIT_MASK_BCNCW_MIN_8821C << BIT_SHIFT_BCNCW_MIN_8821C) +#define BIT_CLEAR_BCNCW_MIN_8821C(x) ((x) & (~BITS_BCNCW_MIN_8821C)) +#define BIT_GET_BCNCW_MIN_8821C(x) \ + (((x) >> BIT_SHIFT_BCNCW_MIN_8821C) & BIT_MASK_BCNCW_MIN_8821C) +#define BIT_SET_BCNCW_MIN_8821C(x, v) \ + (BIT_CLEAR_BCNCW_MIN_8821C(x) | BIT_BCNCW_MIN_8821C(v)) #define BIT_SHIFT_BCNIFS_8821C 0 #define BIT_MASK_BCNIFS_8821C 0xff -#define BIT_BCNIFS_8821C(x) (((x) & BIT_MASK_BCNIFS_8821C) << BIT_SHIFT_BCNIFS_8821C) -#define BIT_GET_BCNIFS_8821C(x) (((x) >> BIT_SHIFT_BCNIFS_8821C) & BIT_MASK_BCNIFS_8821C) - - +#define BIT_BCNIFS_8821C(x) \ + (((x) & BIT_MASK_BCNIFS_8821C) << BIT_SHIFT_BCNIFS_8821C) +#define BITS_BCNIFS_8821C (BIT_MASK_BCNIFS_8821C << BIT_SHIFT_BCNIFS_8821C) +#define BIT_CLEAR_BCNIFS_8821C(x) ((x) & (~BITS_BCNIFS_8821C)) +#define BIT_GET_BCNIFS_8821C(x) \ + (((x) >> BIT_SHIFT_BCNIFS_8821C) & BIT_MASK_BCNIFS_8821C) +#define BIT_SET_BCNIFS_8821C(x, v) \ + (BIT_CLEAR_BCNIFS_8821C(x) | BIT_BCNIFS_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7234,75 +12108,155 @@ #define BIT_SHIFT_PIFS_8821C 0 #define BIT_MASK_PIFS_8821C 0xff #define BIT_PIFS_8821C(x) (((x) & BIT_MASK_PIFS_8821C) << BIT_SHIFT_PIFS_8821C) -#define BIT_GET_PIFS_8821C(x) (((x) >> BIT_SHIFT_PIFS_8821C) & BIT_MASK_PIFS_8821C) - - +#define BITS_PIFS_8821C (BIT_MASK_PIFS_8821C << BIT_SHIFT_PIFS_8821C) +#define BIT_CLEAR_PIFS_8821C(x) ((x) & (~BITS_PIFS_8821C)) +#define BIT_GET_PIFS_8821C(x) \ + (((x) >> BIT_SHIFT_PIFS_8821C) & BIT_MASK_PIFS_8821C) +#define BIT_SET_PIFS_8821C(x, v) (BIT_CLEAR_PIFS_8821C(x) | BIT_PIFS_8821C(v)) /* 2 REG_RDG_PIFS_8821C */ #define BIT_SHIFT_RDG_PIFS_8821C 0 #define BIT_MASK_RDG_PIFS_8821C 0xff -#define BIT_RDG_PIFS_8821C(x) (((x) & BIT_MASK_RDG_PIFS_8821C) << BIT_SHIFT_RDG_PIFS_8821C) -#define BIT_GET_RDG_PIFS_8821C(x) (((x) >> BIT_SHIFT_RDG_PIFS_8821C) & BIT_MASK_RDG_PIFS_8821C) - - +#define BIT_RDG_PIFS_8821C(x) \ + (((x) & BIT_MASK_RDG_PIFS_8821C) << BIT_SHIFT_RDG_PIFS_8821C) +#define BITS_RDG_PIFS_8821C \ + (BIT_MASK_RDG_PIFS_8821C << BIT_SHIFT_RDG_PIFS_8821C) +#define BIT_CLEAR_RDG_PIFS_8821C(x) ((x) & (~BITS_RDG_PIFS_8821C)) +#define BIT_GET_RDG_PIFS_8821C(x) \ + (((x) >> BIT_SHIFT_RDG_PIFS_8821C) & BIT_MASK_RDG_PIFS_8821C) +#define BIT_SET_RDG_PIFS_8821C(x, v) \ + (BIT_CLEAR_RDG_PIFS_8821C(x) | BIT_RDG_PIFS_8821C(v)) /* 2 REG_SIFS_8821C */ #define BIT_SHIFT_SIFS_OFDM_TRX_8821C 24 #define BIT_MASK_SIFS_OFDM_TRX_8821C 0xff -#define BIT_SIFS_OFDM_TRX_8821C(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8821C) << BIT_SHIFT_SIFS_OFDM_TRX_8821C) -#define BIT_GET_SIFS_OFDM_TRX_8821C(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8821C) & BIT_MASK_SIFS_OFDM_TRX_8821C) - - +#define BIT_SIFS_OFDM_TRX_8821C(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX_8821C) << BIT_SHIFT_SIFS_OFDM_TRX_8821C) +#define BITS_SIFS_OFDM_TRX_8821C \ + (BIT_MASK_SIFS_OFDM_TRX_8821C << BIT_SHIFT_SIFS_OFDM_TRX_8821C) +#define BIT_CLEAR_SIFS_OFDM_TRX_8821C(x) ((x) & (~BITS_SIFS_OFDM_TRX_8821C)) +#define BIT_GET_SIFS_OFDM_TRX_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8821C) & BIT_MASK_SIFS_OFDM_TRX_8821C) +#define BIT_SET_SIFS_OFDM_TRX_8821C(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX_8821C(x) | BIT_SIFS_OFDM_TRX_8821C(v)) #define BIT_SHIFT_SIFS_CCK_TRX_8821C 16 #define BIT_MASK_SIFS_CCK_TRX_8821C 0xff -#define BIT_SIFS_CCK_TRX_8821C(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8821C) << BIT_SHIFT_SIFS_CCK_TRX_8821C) -#define BIT_GET_SIFS_CCK_TRX_8821C(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8821C) & BIT_MASK_SIFS_CCK_TRX_8821C) - - +#define BIT_SIFS_CCK_TRX_8821C(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX_8821C) << BIT_SHIFT_SIFS_CCK_TRX_8821C) +#define BITS_SIFS_CCK_TRX_8821C \ + (BIT_MASK_SIFS_CCK_TRX_8821C << BIT_SHIFT_SIFS_CCK_TRX_8821C) +#define BIT_CLEAR_SIFS_CCK_TRX_8821C(x) ((x) & (~BITS_SIFS_CCK_TRX_8821C)) +#define BIT_GET_SIFS_CCK_TRX_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8821C) & BIT_MASK_SIFS_CCK_TRX_8821C) +#define BIT_SET_SIFS_CCK_TRX_8821C(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX_8821C(x) | BIT_SIFS_CCK_TRX_8821C(v)) #define BIT_SHIFT_SIFS_OFDM_CTX_8821C 8 #define BIT_MASK_SIFS_OFDM_CTX_8821C 0xff -#define BIT_SIFS_OFDM_CTX_8821C(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8821C) << BIT_SHIFT_SIFS_OFDM_CTX_8821C) -#define BIT_GET_SIFS_OFDM_CTX_8821C(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8821C) & BIT_MASK_SIFS_OFDM_CTX_8821C) - - +#define BIT_SIFS_OFDM_CTX_8821C(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX_8821C) << BIT_SHIFT_SIFS_OFDM_CTX_8821C) +#define BITS_SIFS_OFDM_CTX_8821C \ + (BIT_MASK_SIFS_OFDM_CTX_8821C << BIT_SHIFT_SIFS_OFDM_CTX_8821C) +#define BIT_CLEAR_SIFS_OFDM_CTX_8821C(x) ((x) & (~BITS_SIFS_OFDM_CTX_8821C)) +#define BIT_GET_SIFS_OFDM_CTX_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8821C) & BIT_MASK_SIFS_OFDM_CTX_8821C) +#define BIT_SET_SIFS_OFDM_CTX_8821C(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX_8821C(x) | BIT_SIFS_OFDM_CTX_8821C(v)) #define BIT_SHIFT_SIFS_CCK_CTX_8821C 0 #define BIT_MASK_SIFS_CCK_CTX_8821C 0xff -#define BIT_SIFS_CCK_CTX_8821C(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8821C) << BIT_SHIFT_SIFS_CCK_CTX_8821C) -#define BIT_GET_SIFS_CCK_CTX_8821C(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8821C) & BIT_MASK_SIFS_CCK_CTX_8821C) - - +#define BIT_SIFS_CCK_CTX_8821C(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX_8821C) << BIT_SHIFT_SIFS_CCK_CTX_8821C) +#define BITS_SIFS_CCK_CTX_8821C \ + (BIT_MASK_SIFS_CCK_CTX_8821C << BIT_SHIFT_SIFS_CCK_CTX_8821C) +#define BIT_CLEAR_SIFS_CCK_CTX_8821C(x) ((x) & (~BITS_SIFS_CCK_CTX_8821C)) +#define BIT_GET_SIFS_CCK_CTX_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8821C) & BIT_MASK_SIFS_CCK_CTX_8821C) +#define BIT_SET_SIFS_CCK_CTX_8821C(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX_8821C(x) | BIT_SIFS_CCK_CTX_8821C(v)) /* 2 REG_TSFTR_SYN_OFFSET_8821C */ #define BIT_SHIFT_TSFTR_SNC_OFFSET_8821C 0 #define BIT_MASK_TSFTR_SNC_OFFSET_8821C 0xffff -#define BIT_TSFTR_SNC_OFFSET_8821C(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8821C) << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) -#define BIT_GET_TSFTR_SNC_OFFSET_8821C(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) & BIT_MASK_TSFTR_SNC_OFFSET_8821C) - - +#define BIT_TSFTR_SNC_OFFSET_8821C(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8821C) \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) +#define BITS_TSFTR_SNC_OFFSET_8821C \ + (BIT_MASK_TSFTR_SNC_OFFSET_8821C << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_8821C(x) \ + ((x) & (~BITS_TSFTR_SNC_OFFSET_8821C)) +#define BIT_GET_TSFTR_SNC_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) & \ + BIT_MASK_TSFTR_SNC_OFFSET_8821C) +#define BIT_SET_TSFTR_SNC_OFFSET_8821C(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_8821C(x) | BIT_TSFTR_SNC_OFFSET_8821C(v)) /* 2 REG_AGGR_BREAK_TIME_8821C */ #define BIT_SHIFT_AGGR_BK_TIME_8821C 0 #define BIT_MASK_AGGR_BK_TIME_8821C 0xff -#define BIT_AGGR_BK_TIME_8821C(x) (((x) & BIT_MASK_AGGR_BK_TIME_8821C) << BIT_SHIFT_AGGR_BK_TIME_8821C) -#define BIT_GET_AGGR_BK_TIME_8821C(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8821C) & BIT_MASK_AGGR_BK_TIME_8821C) - - +#define BIT_AGGR_BK_TIME_8821C(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME_8821C) << BIT_SHIFT_AGGR_BK_TIME_8821C) +#define BITS_AGGR_BK_TIME_8821C \ + (BIT_MASK_AGGR_BK_TIME_8821C << BIT_SHIFT_AGGR_BK_TIME_8821C) +#define BIT_CLEAR_AGGR_BK_TIME_8821C(x) ((x) & (~BITS_AGGR_BK_TIME_8821C)) +#define BIT_GET_AGGR_BK_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME_8821C) & BIT_MASK_AGGR_BK_TIME_8821C) +#define BIT_SET_AGGR_BK_TIME_8821C(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME_8821C(x) | BIT_AGGR_BK_TIME_8821C(v)) /* 2 REG_SLOT_8821C */ #define BIT_SHIFT_SLOT_8821C 0 #define BIT_MASK_SLOT_8821C 0xff #define BIT_SLOT_8821C(x) (((x) & BIT_MASK_SLOT_8821C) << BIT_SHIFT_SLOT_8821C) -#define BIT_GET_SLOT_8821C(x) (((x) >> BIT_SHIFT_SLOT_8821C) & BIT_MASK_SLOT_8821C) - +#define BITS_SLOT_8821C (BIT_MASK_SLOT_8821C << BIT_SHIFT_SLOT_8821C) +#define BIT_CLEAR_SLOT_8821C(x) ((x) & (~BITS_SLOT_8821C)) +#define BIT_GET_SLOT_8821C(x) \ + (((x) >> BIT_SHIFT_SLOT_8821C) & BIT_MASK_SLOT_8821C) +#define BIT_SET_SLOT_8821C(x, v) (BIT_CLEAR_SLOT_8821C(x) | BIT_SLOT_8821C(v)) + +/* 2 REG_NOA_ON_ERLY_TIME_8821C */ + +#define BIT_SHIFT__NOA_ON_ERLY_TIME_8821C 0 +#define BIT_MASK__NOA_ON_ERLY_TIME_8821C 0xff +#define BIT__NOA_ON_ERLY_TIME_8821C(x) \ + (((x) & BIT_MASK__NOA_ON_ERLY_TIME_8821C) \ + << BIT_SHIFT__NOA_ON_ERLY_TIME_8821C) +#define BITS__NOA_ON_ERLY_TIME_8821C \ + (BIT_MASK__NOA_ON_ERLY_TIME_8821C << BIT_SHIFT__NOA_ON_ERLY_TIME_8821C) +#define BIT_CLEAR__NOA_ON_ERLY_TIME_8821C(x) \ + ((x) & (~BITS__NOA_ON_ERLY_TIME_8821C)) +#define BIT_GET__NOA_ON_ERLY_TIME_8821C(x) \ + (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8821C) & \ + BIT_MASK__NOA_ON_ERLY_TIME_8821C) +#define BIT_SET__NOA_ON_ERLY_TIME_8821C(x, v) \ + (BIT_CLEAR__NOA_ON_ERLY_TIME_8821C(x) | BIT__NOA_ON_ERLY_TIME_8821C(v)) + +/* 2 REG_NOA_OFF_ERLY_TIME_8821C */ + +#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C 0 +#define BIT_MASK__NOA_OFF_ERLY_TIME_8821C 0xff +#define BIT__NOA_OFF_ERLY_TIME_8821C(x) \ + (((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8821C) \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C) +#define BITS__NOA_OFF_ERLY_TIME_8821C \ + (BIT_MASK__NOA_OFF_ERLY_TIME_8821C \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C) +#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8821C(x) \ + ((x) & (~BITS__NOA_OFF_ERLY_TIME_8821C)) +#define BIT_GET__NOA_OFF_ERLY_TIME_8821C(x) \ + (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C) & \ + BIT_MASK__NOA_OFF_ERLY_TIME_8821C) +#define BIT_SET__NOA_OFF_ERLY_TIME_8821C(x, v) \ + (BIT_CLEAR__NOA_OFF_ERLY_TIME_8821C(x) | \ + BIT__NOA_OFF_ERLY_TIME_8821C(v)) +/* 2 REG_NOT_VALID_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -7314,9 +12268,15 @@ #define BIT_SHIFT_TXQ_NAV_MSK_8821C 8 #define BIT_MASK_TXQ_NAV_MSK_8821C 0xf -#define BIT_TXQ_NAV_MSK_8821C(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8821C) << BIT_SHIFT_TXQ_NAV_MSK_8821C) -#define BIT_GET_TXQ_NAV_MSK_8821C(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8821C) & BIT_MASK_TXQ_NAV_MSK_8821C) - +#define BIT_TXQ_NAV_MSK_8821C(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK_8821C) << BIT_SHIFT_TXQ_NAV_MSK_8821C) +#define BITS_TXQ_NAV_MSK_8821C \ + (BIT_MASK_TXQ_NAV_MSK_8821C << BIT_SHIFT_TXQ_NAV_MSK_8821C) +#define BIT_CLEAR_TXQ_NAV_MSK_8821C(x) ((x) & (~BITS_TXQ_NAV_MSK_8821C)) +#define BIT_GET_TXQ_NAV_MSK_8821C(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8821C) & BIT_MASK_TXQ_NAV_MSK_8821C) +#define BIT_SET_TXQ_NAV_MSK_8821C(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK_8821C(x) | BIT_TXQ_NAV_MSK_8821C(v)) #define BIT_DIS_CW_8821C BIT(7) #define BIT_NAV_END_TXOP_8821C BIT(6) @@ -7392,17 +12352,29 @@ #define BIT_SHIFT_CCA_FILTER_THRS_8821C 8 #define BIT_MASK_CCA_FILTER_THRS_8821C 0xff -#define BIT_CCA_FILTER_THRS_8821C(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8821C) << BIT_SHIFT_CCA_FILTER_THRS_8821C) -#define BIT_GET_CCA_FILTER_THRS_8821C(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8821C) & BIT_MASK_CCA_FILTER_THRS_8821C) - - +#define BIT_CCA_FILTER_THRS_8821C(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS_8821C) \ + << BIT_SHIFT_CCA_FILTER_THRS_8821C) +#define BITS_CCA_FILTER_THRS_8821C \ + (BIT_MASK_CCA_FILTER_THRS_8821C << BIT_SHIFT_CCA_FILTER_THRS_8821C) +#define BIT_CLEAR_CCA_FILTER_THRS_8821C(x) ((x) & (~BITS_CCA_FILTER_THRS_8821C)) +#define BIT_GET_CCA_FILTER_THRS_8821C(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8821C) & \ + BIT_MASK_CCA_FILTER_THRS_8821C) +#define BIT_SET_CCA_FILTER_THRS_8821C(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS_8821C(x) | BIT_CCA_FILTER_THRS_8821C(v)) #define BIT_SHIFT_EDCCA_THRS_8821C 0 #define BIT_MASK_EDCCA_THRS_8821C 0xff -#define BIT_EDCCA_THRS_8821C(x) (((x) & BIT_MASK_EDCCA_THRS_8821C) << BIT_SHIFT_EDCCA_THRS_8821C) -#define BIT_GET_EDCCA_THRS_8821C(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8821C) & BIT_MASK_EDCCA_THRS_8821C) - - +#define BIT_EDCCA_THRS_8821C(x) \ + (((x) & BIT_MASK_EDCCA_THRS_8821C) << BIT_SHIFT_EDCCA_THRS_8821C) +#define BITS_EDCCA_THRS_8821C \ + (BIT_MASK_EDCCA_THRS_8821C << BIT_SHIFT_EDCCA_THRS_8821C) +#define BIT_CLEAR_EDCCA_THRS_8821C(x) ((x) & (~BITS_EDCCA_THRS_8821C)) +#define BIT_GET_EDCCA_THRS_8821C(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS_8821C) & BIT_MASK_EDCCA_THRS_8821C) +#define BIT_SET_EDCCA_THRS_8821C(x, v) \ + (BIT_CLEAR_EDCCA_THRS_8821C(x) | BIT_EDCCA_THRS_8821C(v)) /* 2 REG_P2PPS_SPEC_STATE_8821C */ #define BIT_SPEC_POWER_STATE_8821C BIT(7) @@ -7418,14 +12390,22 @@ /* 2 REG_BAR_TX_CTRL_8821C */ -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_P2PON_DIS_TXTIME_8821C */ #define BIT_SHIFT_P2PON_DIS_TXTIME_8821C 0 #define BIT_MASK_P2PON_DIS_TXTIME_8821C 0xff -#define BIT_P2PON_DIS_TXTIME_8821C(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8821C) << BIT_SHIFT_P2PON_DIS_TXTIME_8821C) -#define BIT_GET_P2PON_DIS_TXTIME_8821C(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8821C) & BIT_MASK_P2PON_DIS_TXTIME_8821C) - - +#define BIT_P2PON_DIS_TXTIME_8821C(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME_8821C) \ + << BIT_SHIFT_P2PON_DIS_TXTIME_8821C) +#define BITS_P2PON_DIS_TXTIME_8821C \ + (BIT_MASK_P2PON_DIS_TXTIME_8821C << BIT_SHIFT_P2PON_DIS_TXTIME_8821C) +#define BIT_CLEAR_P2PON_DIS_TXTIME_8821C(x) \ + ((x) & (~BITS_P2PON_DIS_TXTIME_8821C)) +#define BIT_GET_P2PON_DIS_TXTIME_8821C(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8821C) & \ + BIT_MASK_P2PON_DIS_TXTIME_8821C) +#define BIT_SET_P2PON_DIS_TXTIME_8821C(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME_8821C(x) | BIT_P2PON_DIS_TXTIME_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7441,17 +12421,35 @@ #define BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C 8 #define BIT_MASK_TBTT_HOLD_TIME_AP_8821C 0xfff -#define BIT_TBTT_HOLD_TIME_AP_8821C(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) -#define BIT_GET_TBTT_HOLD_TIME_AP_8821C(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C) - - +#define BIT_TBTT_HOLD_TIME_AP_8821C(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C) \ + << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) +#define BITS_TBTT_HOLD_TIME_AP_8821C \ + (BIT_MASK_TBTT_HOLD_TIME_AP_8821C << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) +#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8821C(x) \ + ((x) & (~BITS_TBTT_HOLD_TIME_AP_8821C)) +#define BIT_GET_TBTT_HOLD_TIME_AP_8821C(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) & \ + BIT_MASK_TBTT_HOLD_TIME_AP_8821C) +#define BIT_SET_TBTT_HOLD_TIME_AP_8821C(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_AP_8821C(x) | BIT_TBTT_HOLD_TIME_AP_8821C(v)) #define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C 0 #define BIT_MASK_TBTT_PROHIBIT_SETUP_8821C 0xf -#define BIT_TBTT_PROHIBIT_SETUP_8821C(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) -#define BIT_GET_TBTT_PROHIBIT_SETUP_8821C(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) - - +#define BIT_TBTT_PROHIBIT_SETUP_8821C(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) +#define BITS_TBTT_PROHIBIT_SETUP_8821C \ + (BIT_MASK_TBTT_PROHIBIT_SETUP_8821C \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8821C(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8821C)) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8821C(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) & \ + BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) +#define BIT_SET_TBTT_PROHIBIT_SETUP_8821C(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8821C(x) | \ + BIT_TBTT_PROHIBIT_SETUP_8821C(v)) /* 2 REG_P2PPS_STATE_8821C */ #define BIT_POWER_STATE_8821C BIT(7) @@ -7467,19 +12465,31 @@ #define BIT_SHIFT_RD_NAV_PROT_NXT_8821C 0 #define BIT_MASK_RD_NAV_PROT_NXT_8821C 0xffff -#define BIT_RD_NAV_PROT_NXT_8821C(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8821C) << BIT_SHIFT_RD_NAV_PROT_NXT_8821C) -#define BIT_GET_RD_NAV_PROT_NXT_8821C(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8821C) & BIT_MASK_RD_NAV_PROT_NXT_8821C) - - +#define BIT_RD_NAV_PROT_NXT_8821C(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT_8821C) \ + << BIT_SHIFT_RD_NAV_PROT_NXT_8821C) +#define BITS_RD_NAV_PROT_NXT_8821C \ + (BIT_MASK_RD_NAV_PROT_NXT_8821C << BIT_SHIFT_RD_NAV_PROT_NXT_8821C) +#define BIT_CLEAR_RD_NAV_PROT_NXT_8821C(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8821C)) +#define BIT_GET_RD_NAV_PROT_NXT_8821C(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8821C) & \ + BIT_MASK_RD_NAV_PROT_NXT_8821C) +#define BIT_SET_RD_NAV_PROT_NXT_8821C(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT_8821C(x) | BIT_RD_NAV_PROT_NXT_8821C(v)) /* 2 REG_NAV_PROT_LEN_8821C */ #define BIT_SHIFT_NAV_PROT_LEN_8821C 0 #define BIT_MASK_NAV_PROT_LEN_8821C 0xffff -#define BIT_NAV_PROT_LEN_8821C(x) (((x) & BIT_MASK_NAV_PROT_LEN_8821C) << BIT_SHIFT_NAV_PROT_LEN_8821C) -#define BIT_GET_NAV_PROT_LEN_8821C(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8821C) & BIT_MASK_NAV_PROT_LEN_8821C) - - +#define BIT_NAV_PROT_LEN_8821C(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN_8821C) << BIT_SHIFT_NAV_PROT_LEN_8821C) +#define BITS_NAV_PROT_LEN_8821C \ + (BIT_MASK_NAV_PROT_LEN_8821C << BIT_SHIFT_NAV_PROT_LEN_8821C) +#define BIT_CLEAR_NAV_PROT_LEN_8821C(x) ((x) & (~BITS_NAV_PROT_LEN_8821C)) +#define BIT_GET_NAV_PROT_LEN_8821C(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN_8821C) & BIT_MASK_NAV_PROT_LEN_8821C) +#define BIT_SET_NAV_PROT_LEN_8821C(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN_8821C(x) | BIT_NAV_PROT_LEN_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7507,10 +12517,15 @@ #define BIT_SHIFT_MBID_BCN_NUM_8821C 0 #define BIT_MASK_MBID_BCN_NUM_8821C 0x7 -#define BIT_MBID_BCN_NUM_8821C(x) (((x) & BIT_MASK_MBID_BCN_NUM_8821C) << BIT_SHIFT_MBID_BCN_NUM_8821C) -#define BIT_GET_MBID_BCN_NUM_8821C(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8821C) & BIT_MASK_MBID_BCN_NUM_8821C) - - +#define BIT_MBID_BCN_NUM_8821C(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_8821C) << BIT_SHIFT_MBID_BCN_NUM_8821C) +#define BITS_MBID_BCN_NUM_8821C \ + (BIT_MASK_MBID_BCN_NUM_8821C << BIT_SHIFT_MBID_BCN_NUM_8821C) +#define BIT_CLEAR_MBID_BCN_NUM_8821C(x) ((x) & (~BITS_MBID_BCN_NUM_8821C)) +#define BIT_GET_MBID_BCN_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_8821C) & BIT_MASK_MBID_BCN_NUM_8821C) +#define BIT_SET_MBID_BCN_NUM_8821C(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_8821C(x) | BIT_MBID_BCN_NUM_8821C(v)) /* 2 REG_DUAL_TSF_RST_8821C */ #define BIT_FREECNT_RST_8821C BIT(5) @@ -7524,189 +12539,329 @@ #define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C 28 #define BIT_MASK_BCN_TIMER_SEL_FWRD_8821C 0x7 -#define BIT_BCN_TIMER_SEL_FWRD_8821C(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) -#define BIT_GET_BCN_TIMER_SEL_FWRD_8821C(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) - - +#define BIT_BCN_TIMER_SEL_FWRD_8821C(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) +#define BITS_BCN_TIMER_SEL_FWRD_8821C \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_8821C \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8821C(x) \ + ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8821C)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) +#define BIT_SET_BCN_TIMER_SEL_FWRD_8821C(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8821C(x) | \ + BIT_BCN_TIMER_SEL_FWRD_8821C(v)) #define BIT_SHIFT_BCN_SPACE_CLINT0_8821C 16 #define BIT_MASK_BCN_SPACE_CLINT0_8821C 0xfff -#define BIT_BCN_SPACE_CLINT0_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8821C) << BIT_SHIFT_BCN_SPACE_CLINT0_8821C) -#define BIT_GET_BCN_SPACE_CLINT0_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8821C) & BIT_MASK_BCN_SPACE_CLINT0_8821C) - - +#define BIT_BCN_SPACE_CLINT0_8821C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT0_8821C) \ + << BIT_SHIFT_BCN_SPACE_CLINT0_8821C) +#define BITS_BCN_SPACE_CLINT0_8821C \ + (BIT_MASK_BCN_SPACE_CLINT0_8821C << BIT_SHIFT_BCN_SPACE_CLINT0_8821C) +#define BIT_CLEAR_BCN_SPACE_CLINT0_8821C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT0_8821C)) +#define BIT_GET_BCN_SPACE_CLINT0_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8821C) & \ + BIT_MASK_BCN_SPACE_CLINT0_8821C) +#define BIT_SET_BCN_SPACE_CLINT0_8821C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT0_8821C(x) | BIT_BCN_SPACE_CLINT0_8821C(v)) #define BIT_SHIFT_BCN_SPACE0_8821C 0 #define BIT_MASK_BCN_SPACE0_8821C 0xffff -#define BIT_BCN_SPACE0_8821C(x) (((x) & BIT_MASK_BCN_SPACE0_8821C) << BIT_SHIFT_BCN_SPACE0_8821C) -#define BIT_GET_BCN_SPACE0_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8821C) & BIT_MASK_BCN_SPACE0_8821C) - - +#define BIT_BCN_SPACE0_8821C(x) \ + (((x) & BIT_MASK_BCN_SPACE0_8821C) << BIT_SHIFT_BCN_SPACE0_8821C) +#define BITS_BCN_SPACE0_8821C \ + (BIT_MASK_BCN_SPACE0_8821C << BIT_SHIFT_BCN_SPACE0_8821C) +#define BIT_CLEAR_BCN_SPACE0_8821C(x) ((x) & (~BITS_BCN_SPACE0_8821C)) +#define BIT_GET_BCN_SPACE0_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE0_8821C) & BIT_MASK_BCN_SPACE0_8821C) +#define BIT_SET_BCN_SPACE0_8821C(x, v) \ + (BIT_CLEAR_BCN_SPACE0_8821C(x) | BIT_BCN_SPACE0_8821C(v)) /* 2 REG_DRVERLYINT_8821C */ #define BIT_SHIFT_DRVERLYITV_8821C 0 #define BIT_MASK_DRVERLYITV_8821C 0xff -#define BIT_DRVERLYITV_8821C(x) (((x) & BIT_MASK_DRVERLYITV_8821C) << BIT_SHIFT_DRVERLYITV_8821C) -#define BIT_GET_DRVERLYITV_8821C(x) (((x) >> BIT_SHIFT_DRVERLYITV_8821C) & BIT_MASK_DRVERLYITV_8821C) - - +#define BIT_DRVERLYITV_8821C(x) \ + (((x) & BIT_MASK_DRVERLYITV_8821C) << BIT_SHIFT_DRVERLYITV_8821C) +#define BITS_DRVERLYITV_8821C \ + (BIT_MASK_DRVERLYITV_8821C << BIT_SHIFT_DRVERLYITV_8821C) +#define BIT_CLEAR_DRVERLYITV_8821C(x) ((x) & (~BITS_DRVERLYITV_8821C)) +#define BIT_GET_DRVERLYITV_8821C(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV_8821C) & BIT_MASK_DRVERLYITV_8821C) +#define BIT_SET_DRVERLYITV_8821C(x, v) \ + (BIT_CLEAR_DRVERLYITV_8821C(x) | BIT_DRVERLYITV_8821C(v)) /* 2 REG_BCNDMATIM_8821C */ #define BIT_SHIFT_BCNDMATIM_8821C 0 #define BIT_MASK_BCNDMATIM_8821C 0xff -#define BIT_BCNDMATIM_8821C(x) (((x) & BIT_MASK_BCNDMATIM_8821C) << BIT_SHIFT_BCNDMATIM_8821C) -#define BIT_GET_BCNDMATIM_8821C(x) (((x) >> BIT_SHIFT_BCNDMATIM_8821C) & BIT_MASK_BCNDMATIM_8821C) - - +#define BIT_BCNDMATIM_8821C(x) \ + (((x) & BIT_MASK_BCNDMATIM_8821C) << BIT_SHIFT_BCNDMATIM_8821C) +#define BITS_BCNDMATIM_8821C \ + (BIT_MASK_BCNDMATIM_8821C << BIT_SHIFT_BCNDMATIM_8821C) +#define BIT_CLEAR_BCNDMATIM_8821C(x) ((x) & (~BITS_BCNDMATIM_8821C)) +#define BIT_GET_BCNDMATIM_8821C(x) \ + (((x) >> BIT_SHIFT_BCNDMATIM_8821C) & BIT_MASK_BCNDMATIM_8821C) +#define BIT_SET_BCNDMATIM_8821C(x, v) \ + (BIT_CLEAR_BCNDMATIM_8821C(x) | BIT_BCNDMATIM_8821C(v)) /* 2 REG_ATIMWND_8821C */ #define BIT_SHIFT_ATIMWND0_8821C 0 #define BIT_MASK_ATIMWND0_8821C 0xffff -#define BIT_ATIMWND0_8821C(x) (((x) & BIT_MASK_ATIMWND0_8821C) << BIT_SHIFT_ATIMWND0_8821C) -#define BIT_GET_ATIMWND0_8821C(x) (((x) >> BIT_SHIFT_ATIMWND0_8821C) & BIT_MASK_ATIMWND0_8821C) - - +#define BIT_ATIMWND0_8821C(x) \ + (((x) & BIT_MASK_ATIMWND0_8821C) << BIT_SHIFT_ATIMWND0_8821C) +#define BITS_ATIMWND0_8821C \ + (BIT_MASK_ATIMWND0_8821C << BIT_SHIFT_ATIMWND0_8821C) +#define BIT_CLEAR_ATIMWND0_8821C(x) ((x) & (~BITS_ATIMWND0_8821C)) +#define BIT_GET_ATIMWND0_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND0_8821C) & BIT_MASK_ATIMWND0_8821C) +#define BIT_SET_ATIMWND0_8821C(x, v) \ + (BIT_CLEAR_ATIMWND0_8821C(x) | BIT_ATIMWND0_8821C(v)) /* 2 REG_USTIME_TSF_8821C */ #define BIT_SHIFT_USTIME_TSF_V1_8821C 0 #define BIT_MASK_USTIME_TSF_V1_8821C 0xff -#define BIT_USTIME_TSF_V1_8821C(x) (((x) & BIT_MASK_USTIME_TSF_V1_8821C) << BIT_SHIFT_USTIME_TSF_V1_8821C) -#define BIT_GET_USTIME_TSF_V1_8821C(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8821C) & BIT_MASK_USTIME_TSF_V1_8821C) - - +#define BIT_USTIME_TSF_V1_8821C(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1_8821C) << BIT_SHIFT_USTIME_TSF_V1_8821C) +#define BITS_USTIME_TSF_V1_8821C \ + (BIT_MASK_USTIME_TSF_V1_8821C << BIT_SHIFT_USTIME_TSF_V1_8821C) +#define BIT_CLEAR_USTIME_TSF_V1_8821C(x) ((x) & (~BITS_USTIME_TSF_V1_8821C)) +#define BIT_GET_USTIME_TSF_V1_8821C(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1_8821C) & BIT_MASK_USTIME_TSF_V1_8821C) +#define BIT_SET_USTIME_TSF_V1_8821C(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1_8821C(x) | BIT_USTIME_TSF_V1_8821C(v)) /* 2 REG_BCN_MAX_ERR_8821C */ #define BIT_SHIFT_BCN_MAX_ERR_8821C 0 #define BIT_MASK_BCN_MAX_ERR_8821C 0xff -#define BIT_BCN_MAX_ERR_8821C(x) (((x) & BIT_MASK_BCN_MAX_ERR_8821C) << BIT_SHIFT_BCN_MAX_ERR_8821C) -#define BIT_GET_BCN_MAX_ERR_8821C(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8821C) & BIT_MASK_BCN_MAX_ERR_8821C) - - +#define BIT_BCN_MAX_ERR_8821C(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR_8821C) << BIT_SHIFT_BCN_MAX_ERR_8821C) +#define BITS_BCN_MAX_ERR_8821C \ + (BIT_MASK_BCN_MAX_ERR_8821C << BIT_SHIFT_BCN_MAX_ERR_8821C) +#define BIT_CLEAR_BCN_MAX_ERR_8821C(x) ((x) & (~BITS_BCN_MAX_ERR_8821C)) +#define BIT_GET_BCN_MAX_ERR_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR_8821C) & BIT_MASK_BCN_MAX_ERR_8821C) +#define BIT_SET_BCN_MAX_ERR_8821C(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR_8821C(x) | BIT_BCN_MAX_ERR_8821C(v)) /* 2 REG_RXTSF_OFFSET_CCK_8821C */ #define BIT_SHIFT_CCK_RXTSF_OFFSET_8821C 0 #define BIT_MASK_CCK_RXTSF_OFFSET_8821C 0xff -#define BIT_CCK_RXTSF_OFFSET_8821C(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8821C) << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) -#define BIT_GET_CCK_RXTSF_OFFSET_8821C(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) & BIT_MASK_CCK_RXTSF_OFFSET_8821C) - - +#define BIT_CCK_RXTSF_OFFSET_8821C(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8821C) \ + << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) +#define BITS_CCK_RXTSF_OFFSET_8821C \ + (BIT_MASK_CCK_RXTSF_OFFSET_8821C << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) +#define BIT_CLEAR_CCK_RXTSF_OFFSET_8821C(x) \ + ((x) & (~BITS_CCK_RXTSF_OFFSET_8821C)) +#define BIT_GET_CCK_RXTSF_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) & \ + BIT_MASK_CCK_RXTSF_OFFSET_8821C) +#define BIT_SET_CCK_RXTSF_OFFSET_8821C(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET_8821C(x) | BIT_CCK_RXTSF_OFFSET_8821C(v)) /* 2 REG_RXTSF_OFFSET_OFDM_8821C */ #define BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C 0 #define BIT_MASK_OFDM_RXTSF_OFFSET_8821C 0xff -#define BIT_OFDM_RXTSF_OFFSET_8821C(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) -#define BIT_GET_OFDM_RXTSF_OFFSET_8821C(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C) - - +#define BIT_OFDM_RXTSF_OFFSET_8821C(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C) \ + << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) +#define BITS_OFDM_RXTSF_OFFSET_8821C \ + (BIT_MASK_OFDM_RXTSF_OFFSET_8821C << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8821C(x) \ + ((x) & (~BITS_OFDM_RXTSF_OFFSET_8821C)) +#define BIT_GET_OFDM_RXTSF_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) & \ + BIT_MASK_OFDM_RXTSF_OFFSET_8821C) +#define BIT_SET_OFDM_RXTSF_OFFSET_8821C(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET_8821C(x) | BIT_OFDM_RXTSF_OFFSET_8821C(v)) /* 2 REG_TSFTR_8821C */ #define BIT_SHIFT_TSF_TIMER_V1_8821C 0 #define BIT_MASK_TSF_TIMER_V1_8821C 0xffffffffL -#define BIT_TSF_TIMER_V1_8821C(x) (((x) & BIT_MASK_TSF_TIMER_V1_8821C) << BIT_SHIFT_TSF_TIMER_V1_8821C) -#define BIT_GET_TSF_TIMER_V1_8821C(x) (((x) >> BIT_SHIFT_TSF_TIMER_V1_8821C) & BIT_MASK_TSF_TIMER_V1_8821C) - - +#define BIT_TSF_TIMER_V1_8821C(x) \ + (((x) & BIT_MASK_TSF_TIMER_V1_8821C) << BIT_SHIFT_TSF_TIMER_V1_8821C) +#define BITS_TSF_TIMER_V1_8821C \ + (BIT_MASK_TSF_TIMER_V1_8821C << BIT_SHIFT_TSF_TIMER_V1_8821C) +#define BIT_CLEAR_TSF_TIMER_V1_8821C(x) ((x) & (~BITS_TSF_TIMER_V1_8821C)) +#define BIT_GET_TSF_TIMER_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V1_8821C) & BIT_MASK_TSF_TIMER_V1_8821C) +#define BIT_SET_TSF_TIMER_V1_8821C(x, v) \ + (BIT_CLEAR_TSF_TIMER_V1_8821C(x) | BIT_TSF_TIMER_V1_8821C(v)) /* 2 REG_TSFTR_1_8821C */ #define BIT_SHIFT_TSF_TIMER_V2_8821C 0 #define BIT_MASK_TSF_TIMER_V2_8821C 0xffffffffL -#define BIT_TSF_TIMER_V2_8821C(x) (((x) & BIT_MASK_TSF_TIMER_V2_8821C) << BIT_SHIFT_TSF_TIMER_V2_8821C) -#define BIT_GET_TSF_TIMER_V2_8821C(x) (((x) >> BIT_SHIFT_TSF_TIMER_V2_8821C) & BIT_MASK_TSF_TIMER_V2_8821C) - - +#define BIT_TSF_TIMER_V2_8821C(x) \ + (((x) & BIT_MASK_TSF_TIMER_V2_8821C) << BIT_SHIFT_TSF_TIMER_V2_8821C) +#define BITS_TSF_TIMER_V2_8821C \ + (BIT_MASK_TSF_TIMER_V2_8821C << BIT_SHIFT_TSF_TIMER_V2_8821C) +#define BIT_CLEAR_TSF_TIMER_V2_8821C(x) ((x) & (~BITS_TSF_TIMER_V2_8821C)) +#define BIT_GET_TSF_TIMER_V2_8821C(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V2_8821C) & BIT_MASK_TSF_TIMER_V2_8821C) +#define BIT_SET_TSF_TIMER_V2_8821C(x, v) \ + (BIT_CLEAR_TSF_TIMER_V2_8821C(x) | BIT_TSF_TIMER_V2_8821C(v)) /* 2 REG_FREERUN_CNT_8821C */ #define BIT_SHIFT_FREERUN_CNT_V1_8821C 0 #define BIT_MASK_FREERUN_CNT_V1_8821C 0xffffffffL -#define BIT_FREERUN_CNT_V1_8821C(x) (((x) & BIT_MASK_FREERUN_CNT_V1_8821C) << BIT_SHIFT_FREERUN_CNT_V1_8821C) -#define BIT_GET_FREERUN_CNT_V1_8821C(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8821C) & BIT_MASK_FREERUN_CNT_V1_8821C) - - +#define BIT_FREERUN_CNT_V1_8821C(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V1_8821C) \ + << BIT_SHIFT_FREERUN_CNT_V1_8821C) +#define BITS_FREERUN_CNT_V1_8821C \ + (BIT_MASK_FREERUN_CNT_V1_8821C << BIT_SHIFT_FREERUN_CNT_V1_8821C) +#define BIT_CLEAR_FREERUN_CNT_V1_8821C(x) ((x) & (~BITS_FREERUN_CNT_V1_8821C)) +#define BIT_GET_FREERUN_CNT_V1_8821C(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8821C) & \ + BIT_MASK_FREERUN_CNT_V1_8821C) +#define BIT_SET_FREERUN_CNT_V1_8821C(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V1_8821C(x) | BIT_FREERUN_CNT_V1_8821C(v)) /* 2 REG_FREERUN_CNT_1_8821C */ #define BIT_SHIFT_FREERUN_CNT_V2_8821C 0 #define BIT_MASK_FREERUN_CNT_V2_8821C 0xffffffffL -#define BIT_FREERUN_CNT_V2_8821C(x) (((x) & BIT_MASK_FREERUN_CNT_V2_8821C) << BIT_SHIFT_FREERUN_CNT_V2_8821C) -#define BIT_GET_FREERUN_CNT_V2_8821C(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8821C) & BIT_MASK_FREERUN_CNT_V2_8821C) - - +#define BIT_FREERUN_CNT_V2_8821C(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V2_8821C) \ + << BIT_SHIFT_FREERUN_CNT_V2_8821C) +#define BITS_FREERUN_CNT_V2_8821C \ + (BIT_MASK_FREERUN_CNT_V2_8821C << BIT_SHIFT_FREERUN_CNT_V2_8821C) +#define BIT_CLEAR_FREERUN_CNT_V2_8821C(x) ((x) & (~BITS_FREERUN_CNT_V2_8821C)) +#define BIT_GET_FREERUN_CNT_V2_8821C(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8821C) & \ + BIT_MASK_FREERUN_CNT_V2_8821C) +#define BIT_SET_FREERUN_CNT_V2_8821C(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V2_8821C(x) | BIT_FREERUN_CNT_V2_8821C(v)) /* 2 REG_ATIMWND1_V1_8821C */ #define BIT_SHIFT_ATIMWND1_V1_8821C 0 #define BIT_MASK_ATIMWND1_V1_8821C 0xff -#define BIT_ATIMWND1_V1_8821C(x) (((x) & BIT_MASK_ATIMWND1_V1_8821C) << BIT_SHIFT_ATIMWND1_V1_8821C) -#define BIT_GET_ATIMWND1_V1_8821C(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8821C) & BIT_MASK_ATIMWND1_V1_8821C) - - +#define BIT_ATIMWND1_V1_8821C(x) \ + (((x) & BIT_MASK_ATIMWND1_V1_8821C) << BIT_SHIFT_ATIMWND1_V1_8821C) +#define BITS_ATIMWND1_V1_8821C \ + (BIT_MASK_ATIMWND1_V1_8821C << BIT_SHIFT_ATIMWND1_V1_8821C) +#define BIT_CLEAR_ATIMWND1_V1_8821C(x) ((x) & (~BITS_ATIMWND1_V1_8821C)) +#define BIT_GET_ATIMWND1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND1_V1_8821C) & BIT_MASK_ATIMWND1_V1_8821C) +#define BIT_SET_ATIMWND1_V1_8821C(x, v) \ + (BIT_CLEAR_ATIMWND1_V1_8821C(x) | BIT_ATIMWND1_V1_8821C(v)) /* 2 REG_TBTT_PROHIBIT_INFRA_8821C */ #define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C 0 #define BIT_MASK_TBTT_PROHIBIT_INFRA_8821C 0xff -#define BIT_TBTT_PROHIBIT_INFRA_8821C(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) -#define BIT_GET_TBTT_PROHIBIT_INFRA_8821C(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) - - +#define BIT_TBTT_PROHIBIT_INFRA_8821C(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) +#define BITS_TBTT_PROHIBIT_INFRA_8821C \ + (BIT_MASK_TBTT_PROHIBIT_INFRA_8821C \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) +#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8821C(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8821C)) +#define BIT_GET_TBTT_PROHIBIT_INFRA_8821C(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) & \ + BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) +#define BIT_SET_TBTT_PROHIBIT_INFRA_8821C(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8821C(x) | \ + BIT_TBTT_PROHIBIT_INFRA_8821C(v)) /* 2 REG_CTWND_8821C */ #define BIT_SHIFT_CTWND_8821C 0 #define BIT_MASK_CTWND_8821C 0xff -#define BIT_CTWND_8821C(x) (((x) & BIT_MASK_CTWND_8821C) << BIT_SHIFT_CTWND_8821C) -#define BIT_GET_CTWND_8821C(x) (((x) >> BIT_SHIFT_CTWND_8821C) & BIT_MASK_CTWND_8821C) - - +#define BIT_CTWND_8821C(x) \ + (((x) & BIT_MASK_CTWND_8821C) << BIT_SHIFT_CTWND_8821C) +#define BITS_CTWND_8821C (BIT_MASK_CTWND_8821C << BIT_SHIFT_CTWND_8821C) +#define BIT_CLEAR_CTWND_8821C(x) ((x) & (~BITS_CTWND_8821C)) +#define BIT_GET_CTWND_8821C(x) \ + (((x) >> BIT_SHIFT_CTWND_8821C) & BIT_MASK_CTWND_8821C) +#define BIT_SET_CTWND_8821C(x, v) \ + (BIT_CLEAR_CTWND_8821C(x) | BIT_CTWND_8821C(v)) /* 2 REG_BCNIVLCUNT_8821C */ #define BIT_SHIFT_BCNIVLCUNT_8821C 0 #define BIT_MASK_BCNIVLCUNT_8821C 0x7f -#define BIT_BCNIVLCUNT_8821C(x) (((x) & BIT_MASK_BCNIVLCUNT_8821C) << BIT_SHIFT_BCNIVLCUNT_8821C) -#define BIT_GET_BCNIVLCUNT_8821C(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8821C) & BIT_MASK_BCNIVLCUNT_8821C) - - +#define BIT_BCNIVLCUNT_8821C(x) \ + (((x) & BIT_MASK_BCNIVLCUNT_8821C) << BIT_SHIFT_BCNIVLCUNT_8821C) +#define BITS_BCNIVLCUNT_8821C \ + (BIT_MASK_BCNIVLCUNT_8821C << BIT_SHIFT_BCNIVLCUNT_8821C) +#define BIT_CLEAR_BCNIVLCUNT_8821C(x) ((x) & (~BITS_BCNIVLCUNT_8821C)) +#define BIT_GET_BCNIVLCUNT_8821C(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT_8821C) & BIT_MASK_BCNIVLCUNT_8821C) +#define BIT_SET_BCNIVLCUNT_8821C(x, v) \ + (BIT_CLEAR_BCNIVLCUNT_8821C(x) | BIT_BCNIVLCUNT_8821C(v)) /* 2 REG_BCNDROPCTRL_8821C */ #define BIT_BEACON_DROP_EN_8821C BIT(7) #define BIT_SHIFT_BEACON_DROP_IVL_8821C 0 #define BIT_MASK_BEACON_DROP_IVL_8821C 0x7f -#define BIT_BEACON_DROP_IVL_8821C(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8821C) << BIT_SHIFT_BEACON_DROP_IVL_8821C) -#define BIT_GET_BEACON_DROP_IVL_8821C(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8821C) & BIT_MASK_BEACON_DROP_IVL_8821C) - - +#define BIT_BEACON_DROP_IVL_8821C(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL_8821C) \ + << BIT_SHIFT_BEACON_DROP_IVL_8821C) +#define BITS_BEACON_DROP_IVL_8821C \ + (BIT_MASK_BEACON_DROP_IVL_8821C << BIT_SHIFT_BEACON_DROP_IVL_8821C) +#define BIT_CLEAR_BEACON_DROP_IVL_8821C(x) ((x) & (~BITS_BEACON_DROP_IVL_8821C)) +#define BIT_GET_BEACON_DROP_IVL_8821C(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8821C) & \ + BIT_MASK_BEACON_DROP_IVL_8821C) +#define BIT_SET_BEACON_DROP_IVL_8821C(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL_8821C(x) | BIT_BEACON_DROP_IVL_8821C(v)) /* 2 REG_HGQ_TIMEOUT_PERIOD_8821C */ #define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C 0 #define BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C 0xff -#define BIT_HGQ_TIMEOUT_PERIOD_8821C(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) -#define BIT_GET_HGQ_TIMEOUT_PERIOD_8821C(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) - - +#define BIT_HGQ_TIMEOUT_PERIOD_8821C(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) +#define BITS_HGQ_TIMEOUT_PERIOD_8821C \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8821C(x) \ + ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8821C)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8821C(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) & \ + BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) +#define BIT_SET_HGQ_TIMEOUT_PERIOD_8821C(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8821C(x) | \ + BIT_HGQ_TIMEOUT_PERIOD_8821C(v)) /* 2 REG_TXCMD_TIMEOUT_PERIOD_8821C */ #define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C 0 #define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C 0xff -#define BIT_TXCMD_TIMEOUT_PERIOD_8821C(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) -#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8821C(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) - - +#define BIT_TXCMD_TIMEOUT_PERIOD_8821C(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) +#define BITS_TXCMD_TIMEOUT_PERIOD_8821C \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8821C(x) \ + ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8821C)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8821C(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8821C(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8821C(x) | \ + BIT_TXCMD_TIMEOUT_PERIOD_8821C(v)) /* 2 REG_MISC_CTRL_8821C */ +#define BIT_AUTO_SYNC_BY_TBTT_8821C BIT(6) #define BIT_DIS_TRX_CAL_BCN_8821C BIT(5) #define BIT_DIS_TX_CAL_TBTT_8821C BIT(4) #define BIT_EN_FREECNT_8821C BIT(3) @@ -7714,10 +12869,18 @@ #define BIT_SHIFT_DIS_SECONDARY_CCA_8821C 0 #define BIT_MASK_DIS_SECONDARY_CCA_8821C 0x3 -#define BIT_DIS_SECONDARY_CCA_8821C(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8821C) << BIT_SHIFT_DIS_SECONDARY_CCA_8821C) -#define BIT_GET_DIS_SECONDARY_CCA_8821C(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8821C) & BIT_MASK_DIS_SECONDARY_CCA_8821C) - - +#define BIT_DIS_SECONDARY_CCA_8821C(x) \ + (((x) & BIT_MASK_DIS_SECONDARY_CCA_8821C) \ + << BIT_SHIFT_DIS_SECONDARY_CCA_8821C) +#define BITS_DIS_SECONDARY_CCA_8821C \ + (BIT_MASK_DIS_SECONDARY_CCA_8821C << BIT_SHIFT_DIS_SECONDARY_CCA_8821C) +#define BIT_CLEAR_DIS_SECONDARY_CCA_8821C(x) \ + ((x) & (~BITS_DIS_SECONDARY_CCA_8821C)) +#define BIT_GET_DIS_SECONDARY_CCA_8821C(x) \ + (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8821C) & \ + BIT_MASK_DIS_SECONDARY_CCA_8821C) +#define BIT_SET_DIS_SECONDARY_CCA_8821C(x, v) \ + (BIT_CLEAR_DIS_SECONDARY_CCA_8821C(x) | BIT_DIS_SECONDARY_CCA_8821C(v)) /* 2 REG_BCN_CTRL_CLINT1_8821C */ #define BIT_CLI1_DIS_RX_BSSID_FIT_8821C BIT(6) @@ -7749,10 +12912,15 @@ #define BIT_SHIFT_PORT_SEL_8821C 0 #define BIT_MASK_PORT_SEL_8821C 0x7 -#define BIT_PORT_SEL_8821C(x) (((x) & BIT_MASK_PORT_SEL_8821C) << BIT_SHIFT_PORT_SEL_8821C) -#define BIT_GET_PORT_SEL_8821C(x) (((x) >> BIT_SHIFT_PORT_SEL_8821C) & BIT_MASK_PORT_SEL_8821C) - - +#define BIT_PORT_SEL_8821C(x) \ + (((x) & BIT_MASK_PORT_SEL_8821C) << BIT_SHIFT_PORT_SEL_8821C) +#define BITS_PORT_SEL_8821C \ + (BIT_MASK_PORT_SEL_8821C << BIT_SHIFT_PORT_SEL_8821C) +#define BIT_CLEAR_PORT_SEL_8821C(x) ((x) & (~BITS_PORT_SEL_8821C)) +#define BIT_GET_PORT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_PORT_SEL_8821C) & BIT_MASK_PORT_SEL_8821C) +#define BIT_SET_PORT_SEL_8821C(x, v) \ + (BIT_CLEAR_PORT_SEL_8821C(x) | BIT_PORT_SEL_8821C(v)) /* 2 REG_P2PPS1_SPEC_STATE_8821C */ #define BIT_P2P1_SPEC_POWER_STATE_8821C BIT(7) @@ -7798,37 +12966,57 @@ #define BIT_SHIFT_PSTIMER0_INT_8821C 5 #define BIT_MASK_PSTIMER0_INT_8821C 0x7ffffff -#define BIT_PSTIMER0_INT_8821C(x) (((x) & BIT_MASK_PSTIMER0_INT_8821C) << BIT_SHIFT_PSTIMER0_INT_8821C) -#define BIT_GET_PSTIMER0_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8821C) & BIT_MASK_PSTIMER0_INT_8821C) - - +#define BIT_PSTIMER0_INT_8821C(x) \ + (((x) & BIT_MASK_PSTIMER0_INT_8821C) << BIT_SHIFT_PSTIMER0_INT_8821C) +#define BITS_PSTIMER0_INT_8821C \ + (BIT_MASK_PSTIMER0_INT_8821C << BIT_SHIFT_PSTIMER0_INT_8821C) +#define BIT_CLEAR_PSTIMER0_INT_8821C(x) ((x) & (~BITS_PSTIMER0_INT_8821C)) +#define BIT_GET_PSTIMER0_INT_8821C(x) \ + (((x) >> BIT_SHIFT_PSTIMER0_INT_8821C) & BIT_MASK_PSTIMER0_INT_8821C) +#define BIT_SET_PSTIMER0_INT_8821C(x, v) \ + (BIT_CLEAR_PSTIMER0_INT_8821C(x) | BIT_PSTIMER0_INT_8821C(v)) /* 2 REG_PS_TIMER1_8821C */ #define BIT_SHIFT_PSTIMER1_INT_8821C 5 #define BIT_MASK_PSTIMER1_INT_8821C 0x7ffffff -#define BIT_PSTIMER1_INT_8821C(x) (((x) & BIT_MASK_PSTIMER1_INT_8821C) << BIT_SHIFT_PSTIMER1_INT_8821C) -#define BIT_GET_PSTIMER1_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8821C) & BIT_MASK_PSTIMER1_INT_8821C) - - +#define BIT_PSTIMER1_INT_8821C(x) \ + (((x) & BIT_MASK_PSTIMER1_INT_8821C) << BIT_SHIFT_PSTIMER1_INT_8821C) +#define BITS_PSTIMER1_INT_8821C \ + (BIT_MASK_PSTIMER1_INT_8821C << BIT_SHIFT_PSTIMER1_INT_8821C) +#define BIT_CLEAR_PSTIMER1_INT_8821C(x) ((x) & (~BITS_PSTIMER1_INT_8821C)) +#define BIT_GET_PSTIMER1_INT_8821C(x) \ + (((x) >> BIT_SHIFT_PSTIMER1_INT_8821C) & BIT_MASK_PSTIMER1_INT_8821C) +#define BIT_SET_PSTIMER1_INT_8821C(x, v) \ + (BIT_CLEAR_PSTIMER1_INT_8821C(x) | BIT_PSTIMER1_INT_8821C(v)) /* 2 REG_PS_TIMER2_8821C */ #define BIT_SHIFT_PSTIMER2_INT_8821C 5 #define BIT_MASK_PSTIMER2_INT_8821C 0x7ffffff -#define BIT_PSTIMER2_INT_8821C(x) (((x) & BIT_MASK_PSTIMER2_INT_8821C) << BIT_SHIFT_PSTIMER2_INT_8821C) -#define BIT_GET_PSTIMER2_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8821C) & BIT_MASK_PSTIMER2_INT_8821C) - - +#define BIT_PSTIMER2_INT_8821C(x) \ + (((x) & BIT_MASK_PSTIMER2_INT_8821C) << BIT_SHIFT_PSTIMER2_INT_8821C) +#define BITS_PSTIMER2_INT_8821C \ + (BIT_MASK_PSTIMER2_INT_8821C << BIT_SHIFT_PSTIMER2_INT_8821C) +#define BIT_CLEAR_PSTIMER2_INT_8821C(x) ((x) & (~BITS_PSTIMER2_INT_8821C)) +#define BIT_GET_PSTIMER2_INT_8821C(x) \ + (((x) >> BIT_SHIFT_PSTIMER2_INT_8821C) & BIT_MASK_PSTIMER2_INT_8821C) +#define BIT_SET_PSTIMER2_INT_8821C(x, v) \ + (BIT_CLEAR_PSTIMER2_INT_8821C(x) | BIT_PSTIMER2_INT_8821C(v)) /* 2 REG_TBTT_CTN_AREA_8821C */ #define BIT_SHIFT_TBTT_CTN_AREA_8821C 0 #define BIT_MASK_TBTT_CTN_AREA_8821C 0xff -#define BIT_TBTT_CTN_AREA_8821C(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8821C) << BIT_SHIFT_TBTT_CTN_AREA_8821C) -#define BIT_GET_TBTT_CTN_AREA_8821C(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8821C) & BIT_MASK_TBTT_CTN_AREA_8821C) - - +#define BIT_TBTT_CTN_AREA_8821C(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA_8821C) << BIT_SHIFT_TBTT_CTN_AREA_8821C) +#define BITS_TBTT_CTN_AREA_8821C \ + (BIT_MASK_TBTT_CTN_AREA_8821C << BIT_SHIFT_TBTT_CTN_AREA_8821C) +#define BIT_CLEAR_TBTT_CTN_AREA_8821C(x) ((x) & (~BITS_TBTT_CTN_AREA_8821C)) +#define BIT_GET_TBTT_CTN_AREA_8821C(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8821C) & BIT_MASK_TBTT_CTN_AREA_8821C) +#define BIT_SET_TBTT_CTN_AREA_8821C(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA_8821C(x) | BIT_TBTT_CTN_AREA_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7836,10 +13024,15 @@ #define BIT_SHIFT_FORCE_BCN_IFS_8821C 0 #define BIT_MASK_FORCE_BCN_IFS_8821C 0xff -#define BIT_FORCE_BCN_IFS_8821C(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8821C) << BIT_SHIFT_FORCE_BCN_IFS_8821C) -#define BIT_GET_FORCE_BCN_IFS_8821C(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8821C) & BIT_MASK_FORCE_BCN_IFS_8821C) - - +#define BIT_FORCE_BCN_IFS_8821C(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS_8821C) << BIT_SHIFT_FORCE_BCN_IFS_8821C) +#define BITS_FORCE_BCN_IFS_8821C \ + (BIT_MASK_FORCE_BCN_IFS_8821C << BIT_SHIFT_FORCE_BCN_IFS_8821C) +#define BIT_CLEAR_FORCE_BCN_IFS_8821C(x) ((x) & (~BITS_FORCE_BCN_IFS_8821C)) +#define BIT_GET_FORCE_BCN_IFS_8821C(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8821C) & BIT_MASK_FORCE_BCN_IFS_8821C) +#define BIT_SET_FORCE_BCN_IFS_8821C(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS_8821C(x) | BIT_FORCE_BCN_IFS_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -7847,19 +13040,29 @@ #define BIT_SHIFT_TXOP_MIN_8821C 0 #define BIT_MASK_TXOP_MIN_8821C 0x3fff -#define BIT_TXOP_MIN_8821C(x) (((x) & BIT_MASK_TXOP_MIN_8821C) << BIT_SHIFT_TXOP_MIN_8821C) -#define BIT_GET_TXOP_MIN_8821C(x) (((x) >> BIT_SHIFT_TXOP_MIN_8821C) & BIT_MASK_TXOP_MIN_8821C) - - +#define BIT_TXOP_MIN_8821C(x) \ + (((x) & BIT_MASK_TXOP_MIN_8821C) << BIT_SHIFT_TXOP_MIN_8821C) +#define BITS_TXOP_MIN_8821C \ + (BIT_MASK_TXOP_MIN_8821C << BIT_SHIFT_TXOP_MIN_8821C) +#define BIT_CLEAR_TXOP_MIN_8821C(x) ((x) & (~BITS_TXOP_MIN_8821C)) +#define BIT_GET_TXOP_MIN_8821C(x) \ + (((x) >> BIT_SHIFT_TXOP_MIN_8821C) & BIT_MASK_TXOP_MIN_8821C) +#define BIT_SET_TXOP_MIN_8821C(x, v) \ + (BIT_CLEAR_TXOP_MIN_8821C(x) | BIT_TXOP_MIN_8821C(v)) /* 2 REG_PRE_BKF_TIME_8821C */ #define BIT_SHIFT_PRE_BKF_TIME_8821C 0 #define BIT_MASK_PRE_BKF_TIME_8821C 0xff -#define BIT_PRE_BKF_TIME_8821C(x) (((x) & BIT_MASK_PRE_BKF_TIME_8821C) << BIT_SHIFT_PRE_BKF_TIME_8821C) -#define BIT_GET_PRE_BKF_TIME_8821C(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8821C) & BIT_MASK_PRE_BKF_TIME_8821C) - - +#define BIT_PRE_BKF_TIME_8821C(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME_8821C) << BIT_SHIFT_PRE_BKF_TIME_8821C) +#define BITS_PRE_BKF_TIME_8821C \ + (BIT_MASK_PRE_BKF_TIME_8821C << BIT_SHIFT_PRE_BKF_TIME_8821C) +#define BIT_CLEAR_PRE_BKF_TIME_8821C(x) ((x) & (~BITS_PRE_BKF_TIME_8821C)) +#define BIT_GET_PRE_BKF_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME_8821C) & BIT_MASK_PRE_BKF_TIME_8821C) +#define BIT_SET_PRE_BKF_TIME_8821C(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME_8821C(x) | BIT_PRE_BKF_TIME_8821C(v)) /* 2 REG_CROSS_TXOP_CTRL_8821C */ #define BIT_TXFAIL_BREACK_TXOP_EN_8821C BIT(3) @@ -7877,64 +13080,99 @@ #define BIT_SHIFT_ATIMWND2_8821C 0 #define BIT_MASK_ATIMWND2_8821C 0xff -#define BIT_ATIMWND2_8821C(x) (((x) & BIT_MASK_ATIMWND2_8821C) << BIT_SHIFT_ATIMWND2_8821C) -#define BIT_GET_ATIMWND2_8821C(x) (((x) >> BIT_SHIFT_ATIMWND2_8821C) & BIT_MASK_ATIMWND2_8821C) - - +#define BIT_ATIMWND2_8821C(x) \ + (((x) & BIT_MASK_ATIMWND2_8821C) << BIT_SHIFT_ATIMWND2_8821C) +#define BITS_ATIMWND2_8821C \ + (BIT_MASK_ATIMWND2_8821C << BIT_SHIFT_ATIMWND2_8821C) +#define BIT_CLEAR_ATIMWND2_8821C(x) ((x) & (~BITS_ATIMWND2_8821C)) +#define BIT_GET_ATIMWND2_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND2_8821C) & BIT_MASK_ATIMWND2_8821C) +#define BIT_SET_ATIMWND2_8821C(x, v) \ + (BIT_CLEAR_ATIMWND2_8821C(x) | BIT_ATIMWND2_8821C(v)) /* 2 REG_ATIMWND3_8821C */ #define BIT_SHIFT_ATIMWND3_8821C 0 #define BIT_MASK_ATIMWND3_8821C 0xff -#define BIT_ATIMWND3_8821C(x) (((x) & BIT_MASK_ATIMWND3_8821C) << BIT_SHIFT_ATIMWND3_8821C) -#define BIT_GET_ATIMWND3_8821C(x) (((x) >> BIT_SHIFT_ATIMWND3_8821C) & BIT_MASK_ATIMWND3_8821C) - - +#define BIT_ATIMWND3_8821C(x) \ + (((x) & BIT_MASK_ATIMWND3_8821C) << BIT_SHIFT_ATIMWND3_8821C) +#define BITS_ATIMWND3_8821C \ + (BIT_MASK_ATIMWND3_8821C << BIT_SHIFT_ATIMWND3_8821C) +#define BIT_CLEAR_ATIMWND3_8821C(x) ((x) & (~BITS_ATIMWND3_8821C)) +#define BIT_GET_ATIMWND3_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND3_8821C) & BIT_MASK_ATIMWND3_8821C) +#define BIT_SET_ATIMWND3_8821C(x, v) \ + (BIT_CLEAR_ATIMWND3_8821C(x) | BIT_ATIMWND3_8821C(v)) /* 2 REG_ATIMWND4_8821C */ #define BIT_SHIFT_ATIMWND4_8821C 0 #define BIT_MASK_ATIMWND4_8821C 0xff -#define BIT_ATIMWND4_8821C(x) (((x) & BIT_MASK_ATIMWND4_8821C) << BIT_SHIFT_ATIMWND4_8821C) -#define BIT_GET_ATIMWND4_8821C(x) (((x) >> BIT_SHIFT_ATIMWND4_8821C) & BIT_MASK_ATIMWND4_8821C) - - +#define BIT_ATIMWND4_8821C(x) \ + (((x) & BIT_MASK_ATIMWND4_8821C) << BIT_SHIFT_ATIMWND4_8821C) +#define BITS_ATIMWND4_8821C \ + (BIT_MASK_ATIMWND4_8821C << BIT_SHIFT_ATIMWND4_8821C) +#define BIT_CLEAR_ATIMWND4_8821C(x) ((x) & (~BITS_ATIMWND4_8821C)) +#define BIT_GET_ATIMWND4_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND4_8821C) & BIT_MASK_ATIMWND4_8821C) +#define BIT_SET_ATIMWND4_8821C(x, v) \ + (BIT_CLEAR_ATIMWND4_8821C(x) | BIT_ATIMWND4_8821C(v)) /* 2 REG_ATIMWND5_8821C */ #define BIT_SHIFT_ATIMWND5_8821C 0 #define BIT_MASK_ATIMWND5_8821C 0xff -#define BIT_ATIMWND5_8821C(x) (((x) & BIT_MASK_ATIMWND5_8821C) << BIT_SHIFT_ATIMWND5_8821C) -#define BIT_GET_ATIMWND5_8821C(x) (((x) >> BIT_SHIFT_ATIMWND5_8821C) & BIT_MASK_ATIMWND5_8821C) - - +#define BIT_ATIMWND5_8821C(x) \ + (((x) & BIT_MASK_ATIMWND5_8821C) << BIT_SHIFT_ATIMWND5_8821C) +#define BITS_ATIMWND5_8821C \ + (BIT_MASK_ATIMWND5_8821C << BIT_SHIFT_ATIMWND5_8821C) +#define BIT_CLEAR_ATIMWND5_8821C(x) ((x) & (~BITS_ATIMWND5_8821C)) +#define BIT_GET_ATIMWND5_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND5_8821C) & BIT_MASK_ATIMWND5_8821C) +#define BIT_SET_ATIMWND5_8821C(x, v) \ + (BIT_CLEAR_ATIMWND5_8821C(x) | BIT_ATIMWND5_8821C(v)) /* 2 REG_ATIMWND6_8821C */ #define BIT_SHIFT_ATIMWND6_8821C 0 #define BIT_MASK_ATIMWND6_8821C 0xff -#define BIT_ATIMWND6_8821C(x) (((x) & BIT_MASK_ATIMWND6_8821C) << BIT_SHIFT_ATIMWND6_8821C) -#define BIT_GET_ATIMWND6_8821C(x) (((x) >> BIT_SHIFT_ATIMWND6_8821C) & BIT_MASK_ATIMWND6_8821C) - - +#define BIT_ATIMWND6_8821C(x) \ + (((x) & BIT_MASK_ATIMWND6_8821C) << BIT_SHIFT_ATIMWND6_8821C) +#define BITS_ATIMWND6_8821C \ + (BIT_MASK_ATIMWND6_8821C << BIT_SHIFT_ATIMWND6_8821C) +#define BIT_CLEAR_ATIMWND6_8821C(x) ((x) & (~BITS_ATIMWND6_8821C)) +#define BIT_GET_ATIMWND6_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND6_8821C) & BIT_MASK_ATIMWND6_8821C) +#define BIT_SET_ATIMWND6_8821C(x, v) \ + (BIT_CLEAR_ATIMWND6_8821C(x) | BIT_ATIMWND6_8821C(v)) /* 2 REG_ATIMWND7_8821C */ #define BIT_SHIFT_ATIMWND7_8821C 0 #define BIT_MASK_ATIMWND7_8821C 0xff -#define BIT_ATIMWND7_8821C(x) (((x) & BIT_MASK_ATIMWND7_8821C) << BIT_SHIFT_ATIMWND7_8821C) -#define BIT_GET_ATIMWND7_8821C(x) (((x) >> BIT_SHIFT_ATIMWND7_8821C) & BIT_MASK_ATIMWND7_8821C) - - +#define BIT_ATIMWND7_8821C(x) \ + (((x) & BIT_MASK_ATIMWND7_8821C) << BIT_SHIFT_ATIMWND7_8821C) +#define BITS_ATIMWND7_8821C \ + (BIT_MASK_ATIMWND7_8821C << BIT_SHIFT_ATIMWND7_8821C) +#define BIT_CLEAR_ATIMWND7_8821C(x) ((x) & (~BITS_ATIMWND7_8821C)) +#define BIT_GET_ATIMWND7_8821C(x) \ + (((x) >> BIT_SHIFT_ATIMWND7_8821C) & BIT_MASK_ATIMWND7_8821C) +#define BIT_SET_ATIMWND7_8821C(x, v) \ + (BIT_CLEAR_ATIMWND7_8821C(x) | BIT_ATIMWND7_8821C(v)) /* 2 REG_ATIMUGT_8821C */ #define BIT_SHIFT_ATIM_URGENT_8821C 0 #define BIT_MASK_ATIM_URGENT_8821C 0xff -#define BIT_ATIM_URGENT_8821C(x) (((x) & BIT_MASK_ATIM_URGENT_8821C) << BIT_SHIFT_ATIM_URGENT_8821C) -#define BIT_GET_ATIM_URGENT_8821C(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8821C) & BIT_MASK_ATIM_URGENT_8821C) - - +#define BIT_ATIM_URGENT_8821C(x) \ + (((x) & BIT_MASK_ATIM_URGENT_8821C) << BIT_SHIFT_ATIM_URGENT_8821C) +#define BITS_ATIM_URGENT_8821C \ + (BIT_MASK_ATIM_URGENT_8821C << BIT_SHIFT_ATIM_URGENT_8821C) +#define BIT_CLEAR_ATIM_URGENT_8821C(x) ((x) & (~BITS_ATIM_URGENT_8821C)) +#define BIT_GET_ATIM_URGENT_8821C(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_8821C) & BIT_MASK_ATIM_URGENT_8821C) +#define BIT_SET_ATIM_URGENT_8821C(x, v) \ + (BIT_CLEAR_ATIM_URGENT_8821C(x) | BIT_ATIM_URGENT_8821C(v)) /* 2 REG_HIQ_NO_LMT_EN_8821C */ #define BIT_HIQ_NO_LMT_EN_VAP7_8821C BIT(7) @@ -7950,73 +13188,129 @@ #define BIT_SHIFT_DTIM_COUNT_ROOT_8821C 0 #define BIT_MASK_DTIM_COUNT_ROOT_8821C 0xff -#define BIT_DTIM_COUNT_ROOT_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8821C) << BIT_SHIFT_DTIM_COUNT_ROOT_8821C) -#define BIT_GET_DTIM_COUNT_ROOT_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8821C) & BIT_MASK_DTIM_COUNT_ROOT_8821C) - - +#define BIT_DTIM_COUNT_ROOT_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_ROOT_8821C) \ + << BIT_SHIFT_DTIM_COUNT_ROOT_8821C) +#define BITS_DTIM_COUNT_ROOT_8821C \ + (BIT_MASK_DTIM_COUNT_ROOT_8821C << BIT_SHIFT_DTIM_COUNT_ROOT_8821C) +#define BIT_CLEAR_DTIM_COUNT_ROOT_8821C(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8821C)) +#define BIT_GET_DTIM_COUNT_ROOT_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8821C) & \ + BIT_MASK_DTIM_COUNT_ROOT_8821C) +#define BIT_SET_DTIM_COUNT_ROOT_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_ROOT_8821C(x) | BIT_DTIM_COUNT_ROOT_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP1_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP1_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP1_8821C 0xff -#define BIT_DTIM_COUNT_VAP1_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8821C) << BIT_SHIFT_DTIM_COUNT_VAP1_8821C) -#define BIT_GET_DTIM_COUNT_VAP1_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8821C) & BIT_MASK_DTIM_COUNT_VAP1_8821C) - - +#define BIT_DTIM_COUNT_VAP1_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP1_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP1_8821C) +#define BITS_DTIM_COUNT_VAP1_8821C \ + (BIT_MASK_DTIM_COUNT_VAP1_8821C << BIT_SHIFT_DTIM_COUNT_VAP1_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP1_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8821C)) +#define BIT_GET_DTIM_COUNT_VAP1_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP1_8821C) +#define BIT_SET_DTIM_COUNT_VAP1_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP1_8821C(x) | BIT_DTIM_COUNT_VAP1_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP2_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP2_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP2_8821C 0xff -#define BIT_DTIM_COUNT_VAP2_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8821C) << BIT_SHIFT_DTIM_COUNT_VAP2_8821C) -#define BIT_GET_DTIM_COUNT_VAP2_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8821C) & BIT_MASK_DTIM_COUNT_VAP2_8821C) - - +#define BIT_DTIM_COUNT_VAP2_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP2_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP2_8821C) +#define BITS_DTIM_COUNT_VAP2_8821C \ + (BIT_MASK_DTIM_COUNT_VAP2_8821C << BIT_SHIFT_DTIM_COUNT_VAP2_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP2_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8821C)) +#define BIT_GET_DTIM_COUNT_VAP2_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP2_8821C) +#define BIT_SET_DTIM_COUNT_VAP2_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP2_8821C(x) | BIT_DTIM_COUNT_VAP2_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP3_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP3_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP3_8821C 0xff -#define BIT_DTIM_COUNT_VAP3_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8821C) << BIT_SHIFT_DTIM_COUNT_VAP3_8821C) -#define BIT_GET_DTIM_COUNT_VAP3_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8821C) & BIT_MASK_DTIM_COUNT_VAP3_8821C) - - +#define BIT_DTIM_COUNT_VAP3_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP3_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP3_8821C) +#define BITS_DTIM_COUNT_VAP3_8821C \ + (BIT_MASK_DTIM_COUNT_VAP3_8821C << BIT_SHIFT_DTIM_COUNT_VAP3_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP3_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8821C)) +#define BIT_GET_DTIM_COUNT_VAP3_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP3_8821C) +#define BIT_SET_DTIM_COUNT_VAP3_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP3_8821C(x) | BIT_DTIM_COUNT_VAP3_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP4_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP4_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP4_8821C 0xff -#define BIT_DTIM_COUNT_VAP4_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8821C) << BIT_SHIFT_DTIM_COUNT_VAP4_8821C) -#define BIT_GET_DTIM_COUNT_VAP4_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8821C) & BIT_MASK_DTIM_COUNT_VAP4_8821C) - - +#define BIT_DTIM_COUNT_VAP4_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP4_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP4_8821C) +#define BITS_DTIM_COUNT_VAP4_8821C \ + (BIT_MASK_DTIM_COUNT_VAP4_8821C << BIT_SHIFT_DTIM_COUNT_VAP4_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP4_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8821C)) +#define BIT_GET_DTIM_COUNT_VAP4_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP4_8821C) +#define BIT_SET_DTIM_COUNT_VAP4_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP4_8821C(x) | BIT_DTIM_COUNT_VAP4_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP5_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP5_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP5_8821C 0xff -#define BIT_DTIM_COUNT_VAP5_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8821C) << BIT_SHIFT_DTIM_COUNT_VAP5_8821C) -#define BIT_GET_DTIM_COUNT_VAP5_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8821C) & BIT_MASK_DTIM_COUNT_VAP5_8821C) - - +#define BIT_DTIM_COUNT_VAP5_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP5_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP5_8821C) +#define BITS_DTIM_COUNT_VAP5_8821C \ + (BIT_MASK_DTIM_COUNT_VAP5_8821C << BIT_SHIFT_DTIM_COUNT_VAP5_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP5_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8821C)) +#define BIT_GET_DTIM_COUNT_VAP5_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP5_8821C) +#define BIT_SET_DTIM_COUNT_VAP5_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP5_8821C(x) | BIT_DTIM_COUNT_VAP5_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP6_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP6_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP6_8821C 0xff -#define BIT_DTIM_COUNT_VAP6_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8821C) << BIT_SHIFT_DTIM_COUNT_VAP6_8821C) -#define BIT_GET_DTIM_COUNT_VAP6_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8821C) & BIT_MASK_DTIM_COUNT_VAP6_8821C) - - +#define BIT_DTIM_COUNT_VAP6_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP6_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP6_8821C) +#define BITS_DTIM_COUNT_VAP6_8821C \ + (BIT_MASK_DTIM_COUNT_VAP6_8821C << BIT_SHIFT_DTIM_COUNT_VAP6_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP6_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8821C)) +#define BIT_GET_DTIM_COUNT_VAP6_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP6_8821C) +#define BIT_SET_DTIM_COUNT_VAP6_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP6_8821C(x) | BIT_DTIM_COUNT_VAP6_8821C(v)) /* 2 REG_DTIM_COUNTER_VAP7_8821C */ #define BIT_SHIFT_DTIM_COUNT_VAP7_8821C 0 #define BIT_MASK_DTIM_COUNT_VAP7_8821C 0xff -#define BIT_DTIM_COUNT_VAP7_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8821C) << BIT_SHIFT_DTIM_COUNT_VAP7_8821C) -#define BIT_GET_DTIM_COUNT_VAP7_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8821C) & BIT_MASK_DTIM_COUNT_VAP7_8821C) - - +#define BIT_DTIM_COUNT_VAP7_8821C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP7_8821C) \ + << BIT_SHIFT_DTIM_COUNT_VAP7_8821C) +#define BITS_DTIM_COUNT_VAP7_8821C \ + (BIT_MASK_DTIM_COUNT_VAP7_8821C << BIT_SHIFT_DTIM_COUNT_VAP7_8821C) +#define BIT_CLEAR_DTIM_COUNT_VAP7_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8821C)) +#define BIT_GET_DTIM_COUNT_VAP7_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8821C) & \ + BIT_MASK_DTIM_COUNT_VAP7_8821C) +#define BIT_SET_DTIM_COUNT_VAP7_8821C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP7_8821C(x) | BIT_DTIM_COUNT_VAP7_8821C(v)) /* 2 REG_DIS_ATIM_8821C */ #define BIT_DIS_ATIM_VAP7_8821C BIT(7) @@ -8032,17 +13326,29 @@ #define BIT_SHIFT_TSFT_SEL_TIMER1_8821C 3 #define BIT_MASK_TSFT_SEL_TIMER1_8821C 0x7 -#define BIT_TSFT_SEL_TIMER1_8821C(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8821C) << BIT_SHIFT_TSFT_SEL_TIMER1_8821C) -#define BIT_GET_TSFT_SEL_TIMER1_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8821C) & BIT_MASK_TSFT_SEL_TIMER1_8821C) - - +#define BIT_TSFT_SEL_TIMER1_8821C(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER1_8821C) \ + << BIT_SHIFT_TSFT_SEL_TIMER1_8821C) +#define BITS_TSFT_SEL_TIMER1_8821C \ + (BIT_MASK_TSFT_SEL_TIMER1_8821C << BIT_SHIFT_TSFT_SEL_TIMER1_8821C) +#define BIT_CLEAR_TSFT_SEL_TIMER1_8821C(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8821C)) +#define BIT_GET_TSFT_SEL_TIMER1_8821C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8821C) & \ + BIT_MASK_TSFT_SEL_TIMER1_8821C) +#define BIT_SET_TSFT_SEL_TIMER1_8821C(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER1_8821C(x) | BIT_TSFT_SEL_TIMER1_8821C(v)) #define BIT_SHIFT_EARLY_128US_8821C 0 #define BIT_MASK_EARLY_128US_8821C 0x7 -#define BIT_EARLY_128US_8821C(x) (((x) & BIT_MASK_EARLY_128US_8821C) << BIT_SHIFT_EARLY_128US_8821C) -#define BIT_GET_EARLY_128US_8821C(x) (((x) >> BIT_SHIFT_EARLY_128US_8821C) & BIT_MASK_EARLY_128US_8821C) - - +#define BIT_EARLY_128US_8821C(x) \ + (((x) & BIT_MASK_EARLY_128US_8821C) << BIT_SHIFT_EARLY_128US_8821C) +#define BITS_EARLY_128US_8821C \ + (BIT_MASK_EARLY_128US_8821C << BIT_SHIFT_EARLY_128US_8821C) +#define BIT_CLEAR_EARLY_128US_8821C(x) ((x) & (~BITS_EARLY_128US_8821C)) +#define BIT_GET_EARLY_128US_8821C(x) \ + (((x) >> BIT_SHIFT_EARLY_128US_8821C) & BIT_MASK_EARLY_128US_8821C) +#define BIT_SET_EARLY_128US_8821C(x, v) \ + (BIT_CLEAR_EARLY_128US_8821C(x) | BIT_EARLY_128US_8821C(v)) /* 2 REG_P2PPS1_CTRL_8821C */ #define BIT_P2P1_CTW_ALLSTASLEEP_8821C BIT(7) @@ -8062,81 +13368,145 @@ #define BIT_SHIFT_SYNC_CLI_SEL_8821C 4 #define BIT_MASK_SYNC_CLI_SEL_8821C 0x7 -#define BIT_SYNC_CLI_SEL_8821C(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8821C) << BIT_SHIFT_SYNC_CLI_SEL_8821C) -#define BIT_GET_SYNC_CLI_SEL_8821C(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8821C) & BIT_MASK_SYNC_CLI_SEL_8821C) - - +#define BIT_SYNC_CLI_SEL_8821C(x) \ + (((x) & BIT_MASK_SYNC_CLI_SEL_8821C) << BIT_SHIFT_SYNC_CLI_SEL_8821C) +#define BITS_SYNC_CLI_SEL_8821C \ + (BIT_MASK_SYNC_CLI_SEL_8821C << BIT_SHIFT_SYNC_CLI_SEL_8821C) +#define BIT_CLEAR_SYNC_CLI_SEL_8821C(x) ((x) & (~BITS_SYNC_CLI_SEL_8821C)) +#define BIT_GET_SYNC_CLI_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8821C) & BIT_MASK_SYNC_CLI_SEL_8821C) +#define BIT_SET_SYNC_CLI_SEL_8821C(x, v) \ + (BIT_CLEAR_SYNC_CLI_SEL_8821C(x) | BIT_SYNC_CLI_SEL_8821C(v)) #define BIT_SHIFT_TSFT_SEL_TIMER0_8821C 0 #define BIT_MASK_TSFT_SEL_TIMER0_8821C 0x7 -#define BIT_TSFT_SEL_TIMER0_8821C(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8821C) << BIT_SHIFT_TSFT_SEL_TIMER0_8821C) -#define BIT_GET_TSFT_SEL_TIMER0_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8821C) & BIT_MASK_TSFT_SEL_TIMER0_8821C) - - +#define BIT_TSFT_SEL_TIMER0_8821C(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER0_8821C) \ + << BIT_SHIFT_TSFT_SEL_TIMER0_8821C) +#define BITS_TSFT_SEL_TIMER0_8821C \ + (BIT_MASK_TSFT_SEL_TIMER0_8821C << BIT_SHIFT_TSFT_SEL_TIMER0_8821C) +#define BIT_CLEAR_TSFT_SEL_TIMER0_8821C(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8821C)) +#define BIT_GET_TSFT_SEL_TIMER0_8821C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8821C) & \ + BIT_MASK_TSFT_SEL_TIMER0_8821C) +#define BIT_SET_TSFT_SEL_TIMER0_8821C(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER0_8821C(x) | BIT_TSFT_SEL_TIMER0_8821C(v)) /* 2 REG_NOA_UNIT_SEL_8821C */ #define BIT_SHIFT_NOA_UNIT2_SEL_8821C 8 #define BIT_MASK_NOA_UNIT2_SEL_8821C 0x7 -#define BIT_NOA_UNIT2_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8821C) << BIT_SHIFT_NOA_UNIT2_SEL_8821C) -#define BIT_GET_NOA_UNIT2_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8821C) & BIT_MASK_NOA_UNIT2_SEL_8821C) - - +#define BIT_NOA_UNIT2_SEL_8821C(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_8821C) << BIT_SHIFT_NOA_UNIT2_SEL_8821C) +#define BITS_NOA_UNIT2_SEL_8821C \ + (BIT_MASK_NOA_UNIT2_SEL_8821C << BIT_SHIFT_NOA_UNIT2_SEL_8821C) +#define BIT_CLEAR_NOA_UNIT2_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT2_SEL_8821C)) +#define BIT_GET_NOA_UNIT2_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8821C) & BIT_MASK_NOA_UNIT2_SEL_8821C) +#define BIT_SET_NOA_UNIT2_SEL_8821C(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_8821C(x) | BIT_NOA_UNIT2_SEL_8821C(v)) #define BIT_SHIFT_NOA_UNIT1_SEL_8821C 4 #define BIT_MASK_NOA_UNIT1_SEL_8821C 0x7 -#define BIT_NOA_UNIT1_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8821C) << BIT_SHIFT_NOA_UNIT1_SEL_8821C) -#define BIT_GET_NOA_UNIT1_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8821C) & BIT_MASK_NOA_UNIT1_SEL_8821C) - - +#define BIT_NOA_UNIT1_SEL_8821C(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_8821C) << BIT_SHIFT_NOA_UNIT1_SEL_8821C) +#define BITS_NOA_UNIT1_SEL_8821C \ + (BIT_MASK_NOA_UNIT1_SEL_8821C << BIT_SHIFT_NOA_UNIT1_SEL_8821C) +#define BIT_CLEAR_NOA_UNIT1_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT1_SEL_8821C)) +#define BIT_GET_NOA_UNIT1_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8821C) & BIT_MASK_NOA_UNIT1_SEL_8821C) +#define BIT_SET_NOA_UNIT1_SEL_8821C(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_8821C(x) | BIT_NOA_UNIT1_SEL_8821C(v)) #define BIT_SHIFT_NOA_UNIT0_SEL_8821C 0 #define BIT_MASK_NOA_UNIT0_SEL_8821C 0x7 -#define BIT_NOA_UNIT0_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8821C) << BIT_SHIFT_NOA_UNIT0_SEL_8821C) -#define BIT_GET_NOA_UNIT0_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8821C) & BIT_MASK_NOA_UNIT0_SEL_8821C) - - +#define BIT_NOA_UNIT0_SEL_8821C(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_8821C) << BIT_SHIFT_NOA_UNIT0_SEL_8821C) +#define BITS_NOA_UNIT0_SEL_8821C \ + (BIT_MASK_NOA_UNIT0_SEL_8821C << BIT_SHIFT_NOA_UNIT0_SEL_8821C) +#define BIT_CLEAR_NOA_UNIT0_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT0_SEL_8821C)) +#define BIT_GET_NOA_UNIT0_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8821C) & BIT_MASK_NOA_UNIT0_SEL_8821C) +#define BIT_SET_NOA_UNIT0_SEL_8821C(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_8821C(x) | BIT_NOA_UNIT0_SEL_8821C(v)) /* 2 REG_P2POFF_DIS_TXTIME_8821C */ #define BIT_SHIFT_P2POFF_DIS_TXTIME_8821C 0 #define BIT_MASK_P2POFF_DIS_TXTIME_8821C 0xff -#define BIT_P2POFF_DIS_TXTIME_8821C(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8821C) << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) -#define BIT_GET_P2POFF_DIS_TXTIME_8821C(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) & BIT_MASK_P2POFF_DIS_TXTIME_8821C) - - +#define BIT_P2POFF_DIS_TXTIME_8821C(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8821C) \ + << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) +#define BITS_P2POFF_DIS_TXTIME_8821C \ + (BIT_MASK_P2POFF_DIS_TXTIME_8821C << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) +#define BIT_CLEAR_P2POFF_DIS_TXTIME_8821C(x) \ + ((x) & (~BITS_P2POFF_DIS_TXTIME_8821C)) +#define BIT_GET_P2POFF_DIS_TXTIME_8821C(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) & \ + BIT_MASK_P2POFF_DIS_TXTIME_8821C) +#define BIT_SET_P2POFF_DIS_TXTIME_8821C(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME_8821C(x) | BIT_P2POFF_DIS_TXTIME_8821C(v)) /* 2 REG_MBSSID_BCN_SPACE2_8821C */ #define BIT_SHIFT_BCN_SPACE_CLINT2_8821C 16 #define BIT_MASK_BCN_SPACE_CLINT2_8821C 0xfff -#define BIT_BCN_SPACE_CLINT2_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8821C) << BIT_SHIFT_BCN_SPACE_CLINT2_8821C) -#define BIT_GET_BCN_SPACE_CLINT2_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8821C) & BIT_MASK_BCN_SPACE_CLINT2_8821C) - - +#define BIT_BCN_SPACE_CLINT2_8821C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT2_8821C) \ + << BIT_SHIFT_BCN_SPACE_CLINT2_8821C) +#define BITS_BCN_SPACE_CLINT2_8821C \ + (BIT_MASK_BCN_SPACE_CLINT2_8821C << BIT_SHIFT_BCN_SPACE_CLINT2_8821C) +#define BIT_CLEAR_BCN_SPACE_CLINT2_8821C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT2_8821C)) +#define BIT_GET_BCN_SPACE_CLINT2_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8821C) & \ + BIT_MASK_BCN_SPACE_CLINT2_8821C) +#define BIT_SET_BCN_SPACE_CLINT2_8821C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT2_8821C(x) | BIT_BCN_SPACE_CLINT2_8821C(v)) #define BIT_SHIFT_BCN_SPACE_CLINT1_8821C 0 #define BIT_MASK_BCN_SPACE_CLINT1_8821C 0xfff -#define BIT_BCN_SPACE_CLINT1_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8821C) << BIT_SHIFT_BCN_SPACE_CLINT1_8821C) -#define BIT_GET_BCN_SPACE_CLINT1_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8821C) & BIT_MASK_BCN_SPACE_CLINT1_8821C) - - +#define BIT_BCN_SPACE_CLINT1_8821C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT1_8821C) \ + << BIT_SHIFT_BCN_SPACE_CLINT1_8821C) +#define BITS_BCN_SPACE_CLINT1_8821C \ + (BIT_MASK_BCN_SPACE_CLINT1_8821C << BIT_SHIFT_BCN_SPACE_CLINT1_8821C) +#define BIT_CLEAR_BCN_SPACE_CLINT1_8821C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT1_8821C)) +#define BIT_GET_BCN_SPACE_CLINT1_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8821C) & \ + BIT_MASK_BCN_SPACE_CLINT1_8821C) +#define BIT_SET_BCN_SPACE_CLINT1_8821C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT1_8821C(x) | BIT_BCN_SPACE_CLINT1_8821C(v)) /* 2 REG_MBSSID_BCN_SPACE3_8821C */ #define BIT_SHIFT_SUB_BCN_SPACE_8821C 16 #define BIT_MASK_SUB_BCN_SPACE_8821C 0xff -#define BIT_SUB_BCN_SPACE_8821C(x) (((x) & BIT_MASK_SUB_BCN_SPACE_8821C) << BIT_SHIFT_SUB_BCN_SPACE_8821C) -#define BIT_GET_SUB_BCN_SPACE_8821C(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8821C) & BIT_MASK_SUB_BCN_SPACE_8821C) - - +#define BIT_SUB_BCN_SPACE_8821C(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_8821C) << BIT_SHIFT_SUB_BCN_SPACE_8821C) +#define BITS_SUB_BCN_SPACE_8821C \ + (BIT_MASK_SUB_BCN_SPACE_8821C << BIT_SHIFT_SUB_BCN_SPACE_8821C) +#define BIT_CLEAR_SUB_BCN_SPACE_8821C(x) ((x) & (~BITS_SUB_BCN_SPACE_8821C)) +#define BIT_GET_SUB_BCN_SPACE_8821C(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8821C) & BIT_MASK_SUB_BCN_SPACE_8821C) +#define BIT_SET_SUB_BCN_SPACE_8821C(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_8821C(x) | BIT_SUB_BCN_SPACE_8821C(v)) #define BIT_SHIFT_BCN_SPACE_CLINT3_8821C 0 #define BIT_MASK_BCN_SPACE_CLINT3_8821C 0xfff -#define BIT_BCN_SPACE_CLINT3_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8821C) << BIT_SHIFT_BCN_SPACE_CLINT3_8821C) -#define BIT_GET_BCN_SPACE_CLINT3_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8821C) & BIT_MASK_BCN_SPACE_CLINT3_8821C) - - +#define BIT_BCN_SPACE_CLINT3_8821C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT3_8821C) \ + << BIT_SHIFT_BCN_SPACE_CLINT3_8821C) +#define BITS_BCN_SPACE_CLINT3_8821C \ + (BIT_MASK_BCN_SPACE_CLINT3_8821C << BIT_SHIFT_BCN_SPACE_CLINT3_8821C) +#define BIT_CLEAR_BCN_SPACE_CLINT3_8821C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT3_8821C)) +#define BIT_GET_BCN_SPACE_CLINT3_8821C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8821C) & \ + BIT_MASK_BCN_SPACE_CLINT3_8821C) +#define BIT_SET_BCN_SPACE_CLINT3_8821C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT3_8821C(x) | BIT_BCN_SPACE_CLINT3_8821C(v)) /* 2 REG_ACMHWCTRL_8821C */ #define BIT_BEQ_ACM_STATUS_8821C BIT(7) @@ -8156,37 +13526,66 @@ #define BIT_SHIFT_AVGPERIOD_8821C 0 #define BIT_MASK_AVGPERIOD_8821C 0xffff -#define BIT_AVGPERIOD_8821C(x) (((x) & BIT_MASK_AVGPERIOD_8821C) << BIT_SHIFT_AVGPERIOD_8821C) -#define BIT_GET_AVGPERIOD_8821C(x) (((x) >> BIT_SHIFT_AVGPERIOD_8821C) & BIT_MASK_AVGPERIOD_8821C) - - +#define BIT_AVGPERIOD_8821C(x) \ + (((x) & BIT_MASK_AVGPERIOD_8821C) << BIT_SHIFT_AVGPERIOD_8821C) +#define BITS_AVGPERIOD_8821C \ + (BIT_MASK_AVGPERIOD_8821C << BIT_SHIFT_AVGPERIOD_8821C) +#define BIT_CLEAR_AVGPERIOD_8821C(x) ((x) & (~BITS_AVGPERIOD_8821C)) +#define BIT_GET_AVGPERIOD_8821C(x) \ + (((x) >> BIT_SHIFT_AVGPERIOD_8821C) & BIT_MASK_AVGPERIOD_8821C) +#define BIT_SET_AVGPERIOD_8821C(x, v) \ + (BIT_CLEAR_AVGPERIOD_8821C(x) | BIT_AVGPERIOD_8821C(v)) /* 2 REG_VO_ADMTIME_8821C */ #define BIT_SHIFT_VO_ADMITTED_TIME_8821C 0 #define BIT_MASK_VO_ADMITTED_TIME_8821C 0xffff -#define BIT_VO_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8821C) << BIT_SHIFT_VO_ADMITTED_TIME_8821C) -#define BIT_GET_VO_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8821C) & BIT_MASK_VO_ADMITTED_TIME_8821C) - - +#define BIT_VO_ADMITTED_TIME_8821C(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME_8821C) \ + << BIT_SHIFT_VO_ADMITTED_TIME_8821C) +#define BITS_VO_ADMITTED_TIME_8821C \ + (BIT_MASK_VO_ADMITTED_TIME_8821C << BIT_SHIFT_VO_ADMITTED_TIME_8821C) +#define BIT_CLEAR_VO_ADMITTED_TIME_8821C(x) \ + ((x) & (~BITS_VO_ADMITTED_TIME_8821C)) +#define BIT_GET_VO_ADMITTED_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8821C) & \ + BIT_MASK_VO_ADMITTED_TIME_8821C) +#define BIT_SET_VO_ADMITTED_TIME_8821C(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME_8821C(x) | BIT_VO_ADMITTED_TIME_8821C(v)) /* 2 REG_VI_ADMTIME_8821C */ #define BIT_SHIFT_VI_ADMITTED_TIME_8821C 0 #define BIT_MASK_VI_ADMITTED_TIME_8821C 0xffff -#define BIT_VI_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8821C) << BIT_SHIFT_VI_ADMITTED_TIME_8821C) -#define BIT_GET_VI_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8821C) & BIT_MASK_VI_ADMITTED_TIME_8821C) - - +#define BIT_VI_ADMITTED_TIME_8821C(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME_8821C) \ + << BIT_SHIFT_VI_ADMITTED_TIME_8821C) +#define BITS_VI_ADMITTED_TIME_8821C \ + (BIT_MASK_VI_ADMITTED_TIME_8821C << BIT_SHIFT_VI_ADMITTED_TIME_8821C) +#define BIT_CLEAR_VI_ADMITTED_TIME_8821C(x) \ + ((x) & (~BITS_VI_ADMITTED_TIME_8821C)) +#define BIT_GET_VI_ADMITTED_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8821C) & \ + BIT_MASK_VI_ADMITTED_TIME_8821C) +#define BIT_SET_VI_ADMITTED_TIME_8821C(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME_8821C(x) | BIT_VI_ADMITTED_TIME_8821C(v)) /* 2 REG_BE_ADMTIME_8821C */ #define BIT_SHIFT_BE_ADMITTED_TIME_8821C 0 #define BIT_MASK_BE_ADMITTED_TIME_8821C 0xffff -#define BIT_BE_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8821C) << BIT_SHIFT_BE_ADMITTED_TIME_8821C) -#define BIT_GET_BE_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8821C) & BIT_MASK_BE_ADMITTED_TIME_8821C) - - +#define BIT_BE_ADMITTED_TIME_8821C(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME_8821C) \ + << BIT_SHIFT_BE_ADMITTED_TIME_8821C) +#define BITS_BE_ADMITTED_TIME_8821C \ + (BIT_MASK_BE_ADMITTED_TIME_8821C << BIT_SHIFT_BE_ADMITTED_TIME_8821C) +#define BIT_CLEAR_BE_ADMITTED_TIME_8821C(x) \ + ((x) & (~BITS_BE_ADMITTED_TIME_8821C)) +#define BIT_GET_BE_ADMITTED_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8821C) & \ + BIT_MASK_BE_ADMITTED_TIME_8821C) +#define BIT_SET_BE_ADMITTED_TIME_8821C(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME_8821C(x) | BIT_BE_ADMITTED_TIME_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -8196,26 +13595,41 @@ #define BIT_SHIFT_RANDOM_GEN_8821C 0 #define BIT_MASK_RANDOM_GEN_8821C 0xffffff -#define BIT_RANDOM_GEN_8821C(x) (((x) & BIT_MASK_RANDOM_GEN_8821C) << BIT_SHIFT_RANDOM_GEN_8821C) -#define BIT_GET_RANDOM_GEN_8821C(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8821C) & BIT_MASK_RANDOM_GEN_8821C) - - +#define BIT_RANDOM_GEN_8821C(x) \ + (((x) & BIT_MASK_RANDOM_GEN_8821C) << BIT_SHIFT_RANDOM_GEN_8821C) +#define BITS_RANDOM_GEN_8821C \ + (BIT_MASK_RANDOM_GEN_8821C << BIT_SHIFT_RANDOM_GEN_8821C) +#define BIT_CLEAR_RANDOM_GEN_8821C(x) ((x) & (~BITS_RANDOM_GEN_8821C)) +#define BIT_GET_RANDOM_GEN_8821C(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN_8821C) & BIT_MASK_RANDOM_GEN_8821C) +#define BIT_SET_RANDOM_GEN_8821C(x, v) \ + (BIT_CLEAR_RANDOM_GEN_8821C(x) | BIT_RANDOM_GEN_8821C(v)) /* 2 REG_TXCMD_NOA_SEL_8821C */ -#define BIT_SHIFT_NOA_SEL_8821C 4 -#define BIT_MASK_NOA_SEL_8821C 0x7 -#define BIT_NOA_SEL_8821C(x) (((x) & BIT_MASK_NOA_SEL_8821C) << BIT_SHIFT_NOA_SEL_8821C) -#define BIT_GET_NOA_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_SEL_8821C) & BIT_MASK_NOA_SEL_8821C) - - +#define BIT_SHIFT_NOA_SEL_V2_8821C 4 +#define BIT_MASK_NOA_SEL_V2_8821C 0x7 +#define BIT_NOA_SEL_V2_8821C(x) \ + (((x) & BIT_MASK_NOA_SEL_V2_8821C) << BIT_SHIFT_NOA_SEL_V2_8821C) +#define BITS_NOA_SEL_V2_8821C \ + (BIT_MASK_NOA_SEL_V2_8821C << BIT_SHIFT_NOA_SEL_V2_8821C) +#define BIT_CLEAR_NOA_SEL_V2_8821C(x) ((x) & (~BITS_NOA_SEL_V2_8821C)) +#define BIT_GET_NOA_SEL_V2_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V2_8821C) & BIT_MASK_NOA_SEL_V2_8821C) +#define BIT_SET_NOA_SEL_V2_8821C(x, v) \ + (BIT_CLEAR_NOA_SEL_V2_8821C(x) | BIT_NOA_SEL_V2_8821C(v)) #define BIT_SHIFT_TXCMD_SEG_SEL_8821C 0 #define BIT_MASK_TXCMD_SEG_SEL_8821C 0xf -#define BIT_TXCMD_SEG_SEL_8821C(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8821C) << BIT_SHIFT_TXCMD_SEG_SEL_8821C) -#define BIT_GET_TXCMD_SEG_SEL_8821C(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8821C) & BIT_MASK_TXCMD_SEG_SEL_8821C) - - +#define BIT_TXCMD_SEG_SEL_8821C(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL_8821C) << BIT_SHIFT_TXCMD_SEG_SEL_8821C) +#define BITS_TXCMD_SEG_SEL_8821C \ + (BIT_MASK_TXCMD_SEG_SEL_8821C << BIT_SHIFT_TXCMD_SEG_SEL_8821C) +#define BIT_CLEAR_TXCMD_SEG_SEL_8821C(x) ((x) & (~BITS_TXCMD_SEG_SEL_8821C)) +#define BIT_GET_TXCMD_SEG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8821C) & BIT_MASK_TXCMD_SEG_SEL_8821C) +#define BIT_SET_TXCMD_SEG_SEL_8821C(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL_8821C(x) | BIT_TXCMD_SEG_SEL_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -8229,37 +13643,64 @@ #define BIT_SHIFT_NOA_DURATION_V1_8821C 0 #define BIT_MASK_NOA_DURATION_V1_8821C 0xffffffffL -#define BIT_NOA_DURATION_V1_8821C(x) (((x) & BIT_MASK_NOA_DURATION_V1_8821C) << BIT_SHIFT_NOA_DURATION_V1_8821C) -#define BIT_GET_NOA_DURATION_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_DURATION_V1_8821C) & BIT_MASK_NOA_DURATION_V1_8821C) - - +#define BIT_NOA_DURATION_V1_8821C(x) \ + (((x) & BIT_MASK_NOA_DURATION_V1_8821C) \ + << BIT_SHIFT_NOA_DURATION_V1_8821C) +#define BITS_NOA_DURATION_V1_8821C \ + (BIT_MASK_NOA_DURATION_V1_8821C << BIT_SHIFT_NOA_DURATION_V1_8821C) +#define BIT_CLEAR_NOA_DURATION_V1_8821C(x) ((x) & (~BITS_NOA_DURATION_V1_8821C)) +#define BIT_GET_NOA_DURATION_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_V1_8821C) & \ + BIT_MASK_NOA_DURATION_V1_8821C) +#define BIT_SET_NOA_DURATION_V1_8821C(x, v) \ + (BIT_CLEAR_NOA_DURATION_V1_8821C(x) | BIT_NOA_DURATION_V1_8821C(v)) /* 2 REG_NOA_PARAM_1_8821C */ #define BIT_SHIFT_NOA_INTERVAL_V1_8821C 0 #define BIT_MASK_NOA_INTERVAL_V1_8821C 0xffffffffL -#define BIT_NOA_INTERVAL_V1_8821C(x) (((x) & BIT_MASK_NOA_INTERVAL_V1_8821C) << BIT_SHIFT_NOA_INTERVAL_V1_8821C) -#define BIT_GET_NOA_INTERVAL_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8821C) & BIT_MASK_NOA_INTERVAL_V1_8821C) - - +#define BIT_NOA_INTERVAL_V1_8821C(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_V1_8821C) \ + << BIT_SHIFT_NOA_INTERVAL_V1_8821C) +#define BITS_NOA_INTERVAL_V1_8821C \ + (BIT_MASK_NOA_INTERVAL_V1_8821C << BIT_SHIFT_NOA_INTERVAL_V1_8821C) +#define BIT_CLEAR_NOA_INTERVAL_V1_8821C(x) ((x) & (~BITS_NOA_INTERVAL_V1_8821C)) +#define BIT_GET_NOA_INTERVAL_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8821C) & \ + BIT_MASK_NOA_INTERVAL_V1_8821C) +#define BIT_SET_NOA_INTERVAL_V1_8821C(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_V1_8821C(x) | BIT_NOA_INTERVAL_V1_8821C(v)) /* 2 REG_NOA_PARAM_2_8821C */ #define BIT_SHIFT_NOA_START_TIME_V1_8821C 0 #define BIT_MASK_NOA_START_TIME_V1_8821C 0xffffffffL -#define BIT_NOA_START_TIME_V1_8821C(x) (((x) & BIT_MASK_NOA_START_TIME_V1_8821C) << BIT_SHIFT_NOA_START_TIME_V1_8821C) -#define BIT_GET_NOA_START_TIME_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8821C) & BIT_MASK_NOA_START_TIME_V1_8821C) - - +#define BIT_NOA_START_TIME_V1_8821C(x) \ + (((x) & BIT_MASK_NOA_START_TIME_V1_8821C) \ + << BIT_SHIFT_NOA_START_TIME_V1_8821C) +#define BITS_NOA_START_TIME_V1_8821C \ + (BIT_MASK_NOA_START_TIME_V1_8821C << BIT_SHIFT_NOA_START_TIME_V1_8821C) +#define BIT_CLEAR_NOA_START_TIME_V1_8821C(x) \ + ((x) & (~BITS_NOA_START_TIME_V1_8821C)) +#define BIT_GET_NOA_START_TIME_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8821C) & \ + BIT_MASK_NOA_START_TIME_V1_8821C) +#define BIT_SET_NOA_START_TIME_V1_8821C(x, v) \ + (BIT_CLEAR_NOA_START_TIME_V1_8821C(x) | BIT_NOA_START_TIME_V1_8821C(v)) /* 2 REG_NOA_PARAM_3_8821C */ #define BIT_SHIFT_NOA_COUNT_V1_8821C 0 #define BIT_MASK_NOA_COUNT_V1_8821C 0xffffffffL -#define BIT_NOA_COUNT_V1_8821C(x) (((x) & BIT_MASK_NOA_COUNT_V1_8821C) << BIT_SHIFT_NOA_COUNT_V1_8821C) -#define BIT_GET_NOA_COUNT_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_COUNT_V1_8821C) & BIT_MASK_NOA_COUNT_V1_8821C) - - +#define BIT_NOA_COUNT_V1_8821C(x) \ + (((x) & BIT_MASK_NOA_COUNT_V1_8821C) << BIT_SHIFT_NOA_COUNT_V1_8821C) +#define BITS_NOA_COUNT_V1_8821C \ + (BIT_MASK_NOA_COUNT_V1_8821C << BIT_SHIFT_NOA_COUNT_V1_8821C) +#define BIT_CLEAR_NOA_COUNT_V1_8821C(x) ((x) & (~BITS_NOA_COUNT_V1_8821C)) +#define BIT_GET_NOA_COUNT_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_V1_8821C) & BIT_MASK_NOA_COUNT_V1_8821C) +#define BIT_SET_NOA_COUNT_V1_8821C(x, v) \ + (BIT_CLEAR_NOA_COUNT_V1_8821C(x) | BIT_NOA_COUNT_V1_8821C(v)) /* 2 REG_P2P_RST_8821C */ #define BIT_P2P2_PWR_RST1_8821C BIT(5) @@ -8270,7 +13711,8 @@ #define BIT_P2P_PWR_RST0_V1_8821C BIT(0) /* 2 REG_SCHEDULER_RST_8821C */ -#define BIT_SYNC_CLI_8821C BIT(1) +#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8821C BIT(2) +#define BIT_SYNC_CLI_ONCE_BY_TBTT_8821C BIT(1) #define BIT_SCHEDULER_RST_V1_8821C BIT(0) /* 2 REG_NOT_VALID_8821C */ @@ -8283,48 +13725,79 @@ #define BIT_SHIFT_SCH_TXCMD_8821C 0 #define BIT_MASK_SCH_TXCMD_8821C 0xffffffffL -#define BIT_SCH_TXCMD_8821C(x) (((x) & BIT_MASK_SCH_TXCMD_8821C) << BIT_SHIFT_SCH_TXCMD_8821C) -#define BIT_GET_SCH_TXCMD_8821C(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8821C) & BIT_MASK_SCH_TXCMD_8821C) - - +#define BIT_SCH_TXCMD_8821C(x) \ + (((x) & BIT_MASK_SCH_TXCMD_8821C) << BIT_SHIFT_SCH_TXCMD_8821C) +#define BITS_SCH_TXCMD_8821C \ + (BIT_MASK_SCH_TXCMD_8821C << BIT_SHIFT_SCH_TXCMD_8821C) +#define BIT_CLEAR_SCH_TXCMD_8821C(x) ((x) & (~BITS_SCH_TXCMD_8821C)) +#define BIT_GET_SCH_TXCMD_8821C(x) \ + (((x) >> BIT_SHIFT_SCH_TXCMD_8821C) & BIT_MASK_SCH_TXCMD_8821C) +#define BIT_SET_SCH_TXCMD_8821C(x, v) \ + (BIT_CLEAR_SCH_TXCMD_8821C(x) | BIT_SCH_TXCMD_8821C(v)) /* 2 REG_PAGE5_DUMMY_8821C */ +#define BIT_ECO_TXOP_BREAK_FORCE_CFEND_8821C BIT(0) /* 2 REG_CPUMGQ_TX_TIMER_8821C */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C 0 #define BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C 0xffffffffL -#define BIT_CPUMGQ_TX_TIMER_V1_8821C(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) -#define BIT_GET_CPUMGQ_TX_TIMER_V1_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) - - +#define BIT_CPUMGQ_TX_TIMER_V1_8821C(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) +#define BITS_CPUMGQ_TX_TIMER_V1_8821C \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8821C(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8821C)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8821C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) & \ + BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) +#define BIT_SET_CPUMGQ_TX_TIMER_V1_8821C(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8821C(x) | \ + BIT_CPUMGQ_TX_TIMER_V1_8821C(v)) /* 2 REG_PS_TIMER_A_8821C */ #define BIT_SHIFT_PS_TIMER_A_V1_8821C 0 #define BIT_MASK_PS_TIMER_A_V1_8821C 0xffffffffL -#define BIT_PS_TIMER_A_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8821C) << BIT_SHIFT_PS_TIMER_A_V1_8821C) -#define BIT_GET_PS_TIMER_A_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8821C) & BIT_MASK_PS_TIMER_A_V1_8821C) - - +#define BIT_PS_TIMER_A_V1_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_V1_8821C) << BIT_SHIFT_PS_TIMER_A_V1_8821C) +#define BITS_PS_TIMER_A_V1_8821C \ + (BIT_MASK_PS_TIMER_A_V1_8821C << BIT_SHIFT_PS_TIMER_A_V1_8821C) +#define BIT_CLEAR_PS_TIMER_A_V1_8821C(x) ((x) & (~BITS_PS_TIMER_A_V1_8821C)) +#define BIT_GET_PS_TIMER_A_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8821C) & BIT_MASK_PS_TIMER_A_V1_8821C) +#define BIT_SET_PS_TIMER_A_V1_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_V1_8821C(x) | BIT_PS_TIMER_A_V1_8821C(v)) /* 2 REG_PS_TIMER_B_8821C */ #define BIT_SHIFT_PS_TIMER_B_V1_8821C 0 #define BIT_MASK_PS_TIMER_B_V1_8821C 0xffffffffL -#define BIT_PS_TIMER_B_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8821C) << BIT_SHIFT_PS_TIMER_B_V1_8821C) -#define BIT_GET_PS_TIMER_B_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8821C) & BIT_MASK_PS_TIMER_B_V1_8821C) - - +#define BIT_PS_TIMER_B_V1_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_V1_8821C) << BIT_SHIFT_PS_TIMER_B_V1_8821C) +#define BITS_PS_TIMER_B_V1_8821C \ + (BIT_MASK_PS_TIMER_B_V1_8821C << BIT_SHIFT_PS_TIMER_B_V1_8821C) +#define BIT_CLEAR_PS_TIMER_B_V1_8821C(x) ((x) & (~BITS_PS_TIMER_B_V1_8821C)) +#define BIT_GET_PS_TIMER_B_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8821C) & BIT_MASK_PS_TIMER_B_V1_8821C) +#define BIT_SET_PS_TIMER_B_V1_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_V1_8821C(x) | BIT_PS_TIMER_B_V1_8821C(v)) /* 2 REG_PS_TIMER_C_8821C */ #define BIT_SHIFT_PS_TIMER_C_V1_8821C 0 #define BIT_MASK_PS_TIMER_C_V1_8821C 0xffffffffL -#define BIT_PS_TIMER_C_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8821C) << BIT_SHIFT_PS_TIMER_C_V1_8821C) -#define BIT_GET_PS_TIMER_C_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8821C) & BIT_MASK_PS_TIMER_C_V1_8821C) - - +#define BIT_PS_TIMER_C_V1_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_V1_8821C) << BIT_SHIFT_PS_TIMER_C_V1_8821C) +#define BITS_PS_TIMER_C_V1_8821C \ + (BIT_MASK_PS_TIMER_C_V1_8821C << BIT_SHIFT_PS_TIMER_C_V1_8821C) +#define BIT_CLEAR_PS_TIMER_C_V1_8821C(x) ((x) & (~BITS_PS_TIMER_C_V1_8821C)) +#define BIT_GET_PS_TIMER_C_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8821C) & BIT_MASK_PS_TIMER_C_V1_8821C) +#define BIT_SET_PS_TIMER_C_V1_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_V1_8821C(x) | BIT_PS_TIMER_C_V1_8821C(v)) /* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C */ #define BIT_CPUMGQ_TIMER_EN_8821C BIT(31) @@ -8332,72 +13805,169 @@ #define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C 24 #define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C 0x7 -#define BIT_CPUMGQ_TIMER_TSF_SEL_8821C(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) -#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) - +#define BIT_CPUMGQ_TIMER_TSF_SEL_8821C(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) +#define BITS_CPUMGQ_TIMER_TSF_SEL_8821C \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8821C(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8821C)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8821C(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8821C(x) | \ + BIT_CPUMGQ_TIMER_TSF_SEL_8821C(v)) #define BIT_PS_TIMER_C_EN_8821C BIT(23) #define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C 16 #define BIT_MASK_PS_TIMER_C_TSF_SEL_8821C 0x7 -#define BIT_PS_TIMER_C_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) -#define BIT_GET_PS_TIMER_C_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) - +#define BIT_PS_TIMER_C_TSF_SEL_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) +#define BITS_PS_TIMER_C_TSF_SEL_8821C \ + (BIT_MASK_PS_TIMER_C_TSF_SEL_8821C \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) +#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8821C(x) \ + ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8821C)) +#define BIT_GET_PS_TIMER_C_TSF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) & \ + BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) +#define BIT_SET_PS_TIMER_C_TSF_SEL_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8821C(x) | \ + BIT_PS_TIMER_C_TSF_SEL_8821C(v)) #define BIT_PS_TIMER_B_EN_8821C BIT(15) #define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C 8 #define BIT_MASK_PS_TIMER_B_TSF_SEL_8821C 0x7 -#define BIT_PS_TIMER_B_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) -#define BIT_GET_PS_TIMER_B_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) - +#define BIT_PS_TIMER_B_TSF_SEL_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) +#define BITS_PS_TIMER_B_TSF_SEL_8821C \ + (BIT_MASK_PS_TIMER_B_TSF_SEL_8821C \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8821C(x) \ + ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8821C)) +#define BIT_GET_PS_TIMER_B_TSF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) & \ + BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) +#define BIT_SET_PS_TIMER_B_TSF_SEL_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8821C(x) | \ + BIT_PS_TIMER_B_TSF_SEL_8821C(v)) #define BIT_PS_TIMER_A_EN_8821C BIT(7) #define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C 0 #define BIT_MASK_PS_TIMER_A_TSF_SEL_8821C 0x7 -#define BIT_PS_TIMER_A_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) -#define BIT_GET_PS_TIMER_A_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) - - +#define BIT_PS_TIMER_A_TSF_SEL_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) +#define BITS_PS_TIMER_A_TSF_SEL_8821C \ + (BIT_MASK_PS_TIMER_A_TSF_SEL_8821C \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8821C(x) \ + ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8821C)) +#define BIT_GET_PS_TIMER_A_TSF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) & \ + BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) +#define BIT_SET_PS_TIMER_A_TSF_SEL_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8821C(x) | \ + BIT_PS_TIMER_A_TSF_SEL_8821C(v)) /* 2 REG_CPUMGQ_TX_TIMER_EARLY_8821C */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C 0 #define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C 0xff -#define BIT_CPUMGQ_TX_TIMER_EARLY_8821C(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) -#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) - - +#define BIT_CPUMGQ_TX_TIMER_EARLY_8821C(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) +#define BITS_CPUMGQ_TX_TIMER_EARLY_8821C \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8821C(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8821C)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8821C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8821C(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8821C(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_8821C(v)) /* 2 REG_PS_TIMER_A_EARLY_8821C */ #define BIT_SHIFT_PS_TIMER_A_EARLY_8821C 0 #define BIT_MASK_PS_TIMER_A_EARLY_8821C 0xff -#define BIT_PS_TIMER_A_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8821C) << BIT_SHIFT_PS_TIMER_A_EARLY_8821C) -#define BIT_GET_PS_TIMER_A_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8821C) & BIT_MASK_PS_TIMER_A_EARLY_8821C) - - +#define BIT_PS_TIMER_A_EARLY_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_EARLY_8821C) \ + << BIT_SHIFT_PS_TIMER_A_EARLY_8821C) +#define BITS_PS_TIMER_A_EARLY_8821C \ + (BIT_MASK_PS_TIMER_A_EARLY_8821C << BIT_SHIFT_PS_TIMER_A_EARLY_8821C) +#define BIT_CLEAR_PS_TIMER_A_EARLY_8821C(x) \ + ((x) & (~BITS_PS_TIMER_A_EARLY_8821C)) +#define BIT_GET_PS_TIMER_A_EARLY_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8821C) & \ + BIT_MASK_PS_TIMER_A_EARLY_8821C) +#define BIT_SET_PS_TIMER_A_EARLY_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_EARLY_8821C(x) | BIT_PS_TIMER_A_EARLY_8821C(v)) /* 2 REG_PS_TIMER_B_EARLY_8821C */ #define BIT_SHIFT_PS_TIMER_B_EARLY_8821C 0 #define BIT_MASK_PS_TIMER_B_EARLY_8821C 0xff -#define BIT_PS_TIMER_B_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8821C) << BIT_SHIFT_PS_TIMER_B_EARLY_8821C) -#define BIT_GET_PS_TIMER_B_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8821C) & BIT_MASK_PS_TIMER_B_EARLY_8821C) - - +#define BIT_PS_TIMER_B_EARLY_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_EARLY_8821C) \ + << BIT_SHIFT_PS_TIMER_B_EARLY_8821C) +#define BITS_PS_TIMER_B_EARLY_8821C \ + (BIT_MASK_PS_TIMER_B_EARLY_8821C << BIT_SHIFT_PS_TIMER_B_EARLY_8821C) +#define BIT_CLEAR_PS_TIMER_B_EARLY_8821C(x) \ + ((x) & (~BITS_PS_TIMER_B_EARLY_8821C)) +#define BIT_GET_PS_TIMER_B_EARLY_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8821C) & \ + BIT_MASK_PS_TIMER_B_EARLY_8821C) +#define BIT_SET_PS_TIMER_B_EARLY_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_EARLY_8821C(x) | BIT_PS_TIMER_B_EARLY_8821C(v)) /* 2 REG_PS_TIMER_C_EARLY_8821C */ #define BIT_SHIFT_PS_TIMER_C_EARLY_8821C 0 #define BIT_MASK_PS_TIMER_C_EARLY_8821C 0xff -#define BIT_PS_TIMER_C_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8821C) << BIT_SHIFT_PS_TIMER_C_EARLY_8821C) -#define BIT_GET_PS_TIMER_C_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8821C) & BIT_MASK_PS_TIMER_C_EARLY_8821C) +#define BIT_PS_TIMER_C_EARLY_8821C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_EARLY_8821C) \ + << BIT_SHIFT_PS_TIMER_C_EARLY_8821C) +#define BITS_PS_TIMER_C_EARLY_8821C \ + (BIT_MASK_PS_TIMER_C_EARLY_8821C << BIT_SHIFT_PS_TIMER_C_EARLY_8821C) +#define BIT_CLEAR_PS_TIMER_C_EARLY_8821C(x) \ + ((x) & (~BITS_PS_TIMER_C_EARLY_8821C)) +#define BIT_GET_PS_TIMER_C_EARLY_8821C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8821C) & \ + BIT_MASK_PS_TIMER_C_EARLY_8821C) +#define BIT_SET_PS_TIMER_C_EARLY_8821C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_EARLY_8821C(x) | BIT_PS_TIMER_C_EARLY_8821C(v)) + +/* 2 REG_CPUMGQ_PARAMETER_8821C */ +/* 2 REG_NOT_VALID_8821C */ +#define BIT_MAC_STOP_CPUMGQ_8821C BIT(16) +#define BIT_SHIFT_CW_8821C 8 +#define BIT_MASK_CW_8821C 0xff +#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C) +#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C)) +#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) +#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v)) -/* 2 REG_NOT_VALID_8821C */ +#define BIT_SHIFT_AIFS_8821C 0 +#define BIT_MASK_AIFS_8821C 0xff +#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) +#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C) +#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C)) +#define BIT_GET_AIFS_8821C(x) \ + (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) +#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -8515,28 +14085,36 @@ /* 2 REG_NOT_VALID_8821C */ -/* 2 REG_BWOPMODE_8821C (BW OPERATION MODE REGISTER) */ +/* 2 REG_WMAC_CR_8821C (WMAC CR AND APSD CONTROL REGISTER) */ +#define BIT_IC_MACPHY_M_8821C BIT(0) /* 2 REG_WMAC_FWPKT_CR_8821C */ #define BIT_FWEN_8821C BIT(7) #define BIT_PHYSTS_PKT_CTRL_8821C BIT(6) +#define BIT_FWFULL_TO_RXFF_EN_8821C BIT(5) #define BIT_APPHDR_MIDSRCH_FAIL_8821C BIT(4) #define BIT_FWPARSING_EN_8821C BIT(3) #define BIT_SHIFT_APPEND_MHDR_LEN_8821C 0 #define BIT_MASK_APPEND_MHDR_LEN_8821C 0x7 -#define BIT_APPEND_MHDR_LEN_8821C(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8821C) << BIT_SHIFT_APPEND_MHDR_LEN_8821C) -#define BIT_GET_APPEND_MHDR_LEN_8821C(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8821C) & BIT_MASK_APPEND_MHDR_LEN_8821C) - - +#define BIT_APPEND_MHDR_LEN_8821C(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN_8821C) \ + << BIT_SHIFT_APPEND_MHDR_LEN_8821C) +#define BITS_APPEND_MHDR_LEN_8821C \ + (BIT_MASK_APPEND_MHDR_LEN_8821C << BIT_SHIFT_APPEND_MHDR_LEN_8821C) +#define BIT_CLEAR_APPEND_MHDR_LEN_8821C(x) ((x) & (~BITS_APPEND_MHDR_LEN_8821C)) +#define BIT_GET_APPEND_MHDR_LEN_8821C(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8821C) & \ + BIT_MASK_APPEND_MHDR_LEN_8821C) +#define BIT_SET_APPEND_MHDR_LEN_8821C(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN_8821C(x) | BIT_APPEND_MHDR_LEN_8821C(v)) /* 2 REG_FW_STS_FILTER_8821C */ #define BIT_DATA_FW_STS_FILTER_8821C BIT(2) #define BIT_CTRL_FW_STS_FILTER_8821C BIT(1) #define BIT_MGNT_FW_STS_FILTER_8821C BIT(0) -/* 2 REG_WMAC_CR_8821C (WMAC CR AND APSD CONTROL REGISTER) */ -#define BIT_IC_MACPHY_M_8821C BIT(0) +/* 2 REG_RSVD_8821C */ /* 2 REG_TCR_8821C (TRANSMISSION CONFIGURATION REGISTER) */ #define BIT_WMAC_EN_RTS_ADDR_8821C BIT(31) @@ -8601,69 +14179,152 @@ #define BIT_APM_8821C BIT(1) #define BIT_AAP_8821C BIT(0) -/* 2 REG_RX_DRVINFO_SZ_8821C (RX DRIVER INFO SIZE REGISTER) */ -#define BIT_PHYSTS_PER_PKT_MODE_8821C BIT(7) - -#define BIT_SHIFT_DRVINFO_SZ_V1_8821C 0 -#define BIT_MASK_DRVINFO_SZ_V1_8821C 0xf -#define BIT_DRVINFO_SZ_V1_8821C(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8821C) << BIT_SHIFT_DRVINFO_SZ_V1_8821C) -#define BIT_GET_DRVINFO_SZ_V1_8821C(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8821C) & BIT_MASK_DRVINFO_SZ_V1_8821C) - - - -/* 2 REG_RX_DLK_TIME_8821C (RX DEADLOCK TIME REGISTER) */ - -#define BIT_SHIFT_RX_DLK_TIME_8821C 0 -#define BIT_MASK_RX_DLK_TIME_8821C 0xff -#define BIT_RX_DLK_TIME_8821C(x) (((x) & BIT_MASK_RX_DLK_TIME_8821C) << BIT_SHIFT_RX_DLK_TIME_8821C) -#define BIT_GET_RX_DLK_TIME_8821C(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8821C) & BIT_MASK_RX_DLK_TIME_8821C) - - - /* 2 REG_RX_PKT_LIMIT_8821C (RX PACKET LENGTH LIMIT REGISTER) */ #define BIT_SHIFT_RXPKTLMT_8821C 0 #define BIT_MASK_RXPKTLMT_8821C 0x3f -#define BIT_RXPKTLMT_8821C(x) (((x) & BIT_MASK_RXPKTLMT_8821C) << BIT_SHIFT_RXPKTLMT_8821C) -#define BIT_GET_RXPKTLMT_8821C(x) (((x) >> BIT_SHIFT_RXPKTLMT_8821C) & BIT_MASK_RXPKTLMT_8821C) - +#define BIT_RXPKTLMT_8821C(x) \ + (((x) & BIT_MASK_RXPKTLMT_8821C) << BIT_SHIFT_RXPKTLMT_8821C) +#define BITS_RXPKTLMT_8821C \ + (BIT_MASK_RXPKTLMT_8821C << BIT_SHIFT_RXPKTLMT_8821C) +#define BIT_CLEAR_RXPKTLMT_8821C(x) ((x) & (~BITS_RXPKTLMT_8821C)) +#define BIT_GET_RXPKTLMT_8821C(x) \ + (((x) >> BIT_SHIFT_RXPKTLMT_8821C) & BIT_MASK_RXPKTLMT_8821C) +#define BIT_SET_RXPKTLMT_8821C(x, v) \ + (BIT_CLEAR_RXPKTLMT_8821C(x) | BIT_RXPKTLMT_8821C(v)) +/* 2 REG_RX_DLK_TIME_8821C (RX DEADLOCK TIME REGISTER) */ -/* 2 REG_MACID_8821C (MAC ID REGISTER) */ +#define BIT_SHIFT_RX_DLK_TIME_8821C 0 +#define BIT_MASK_RX_DLK_TIME_8821C 0xff +#define BIT_RX_DLK_TIME_8821C(x) \ + (((x) & BIT_MASK_RX_DLK_TIME_8821C) << BIT_SHIFT_RX_DLK_TIME_8821C) +#define BITS_RX_DLK_TIME_8821C \ + (BIT_MASK_RX_DLK_TIME_8821C << BIT_SHIFT_RX_DLK_TIME_8821C) +#define BIT_CLEAR_RX_DLK_TIME_8821C(x) ((x) & (~BITS_RX_DLK_TIME_8821C)) +#define BIT_GET_RX_DLK_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME_8821C) & BIT_MASK_RX_DLK_TIME_8821C) +#define BIT_SET_RX_DLK_TIME_8821C(x, v) \ + (BIT_CLEAR_RX_DLK_TIME_8821C(x) | BIT_RX_DLK_TIME_8821C(v)) -#define BIT_SHIFT_MACID_8821C 0 -#define BIT_MASK_MACID_8821C 0xffffffffffffL -#define BIT_MACID_8821C(x) (((x) & BIT_MASK_MACID_8821C) << BIT_SHIFT_MACID_8821C) -#define BIT_GET_MACID_8821C(x) (((x) >> BIT_SHIFT_MACID_8821C) & BIT_MASK_MACID_8821C) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RX_DRVINFO_SZ_8821C (RX DRIVER INFO SIZE REGISTER) */ +#define BIT_PHYSTS_PER_PKT_MODE_8821C BIT(7) +#define BIT_SHIFT_DRVINFO_SZ_V1_8821C 0 +#define BIT_MASK_DRVINFO_SZ_V1_8821C 0xf +#define BIT_DRVINFO_SZ_V1_8821C(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1_8821C) << BIT_SHIFT_DRVINFO_SZ_V1_8821C) +#define BITS_DRVINFO_SZ_V1_8821C \ + (BIT_MASK_DRVINFO_SZ_V1_8821C << BIT_SHIFT_DRVINFO_SZ_V1_8821C) +#define BIT_CLEAR_DRVINFO_SZ_V1_8821C(x) ((x) & (~BITS_DRVINFO_SZ_V1_8821C)) +#define BIT_GET_DRVINFO_SZ_V1_8821C(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8821C) & BIT_MASK_DRVINFO_SZ_V1_8821C) +#define BIT_SET_DRVINFO_SZ_V1_8821C(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1_8821C(x) | BIT_DRVINFO_SZ_V1_8821C(v)) + +/* 2 REG_MACID_8821C (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_V1_8821C 0 +#define BIT_MASK_MACID_V1_8821C 0xffffffffL +#define BIT_MACID_V1_8821C(x) \ + (((x) & BIT_MASK_MACID_V1_8821C) << BIT_SHIFT_MACID_V1_8821C) +#define BITS_MACID_V1_8821C \ + (BIT_MASK_MACID_V1_8821C << BIT_SHIFT_MACID_V1_8821C) +#define BIT_CLEAR_MACID_V1_8821C(x) ((x) & (~BITS_MACID_V1_8821C)) +#define BIT_GET_MACID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID_V1_8821C) & BIT_MASK_MACID_V1_8821C) +#define BIT_SET_MACID_V1_8821C(x, v) \ + (BIT_CLEAR_MACID_V1_8821C(x) | BIT_MACID_V1_8821C(v)) + +/* 2 REG_MACID_H_8821C (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_H_V1_8821C 0 +#define BIT_MASK_MACID_H_V1_8821C 0xffff +#define BIT_MACID_H_V1_8821C(x) \ + (((x) & BIT_MASK_MACID_H_V1_8821C) << BIT_SHIFT_MACID_H_V1_8821C) +#define BITS_MACID_H_V1_8821C \ + (BIT_MASK_MACID_H_V1_8821C << BIT_SHIFT_MACID_H_V1_8821C) +#define BIT_CLEAR_MACID_H_V1_8821C(x) ((x) & (~BITS_MACID_H_V1_8821C)) +#define BIT_GET_MACID_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID_H_V1_8821C) & BIT_MASK_MACID_H_V1_8821C) +#define BIT_SET_MACID_H_V1_8821C(x, v) \ + (BIT_CLEAR_MACID_H_V1_8821C(x) | BIT_MACID_H_V1_8821C(v)) /* 2 REG_BSSID_8821C (BSSID REGISTER) */ -#define BIT_SHIFT_BSSID_8821C 0 -#define BIT_MASK_BSSID_8821C 0xffffffffffffL -#define BIT_BSSID_8821C(x) (((x) & BIT_MASK_BSSID_8821C) << BIT_SHIFT_BSSID_8821C) -#define BIT_GET_BSSID_8821C(x) (((x) >> BIT_SHIFT_BSSID_8821C) & BIT_MASK_BSSID_8821C) - +#define BIT_SHIFT_BSSID_V1_8821C 0 +#define BIT_MASK_BSSID_V1_8821C 0xffffffffL +#define BIT_BSSID_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID_V1_8821C) << BIT_SHIFT_BSSID_V1_8821C) +#define BITS_BSSID_V1_8821C \ + (BIT_MASK_BSSID_V1_8821C << BIT_SHIFT_BSSID_V1_8821C) +#define BIT_CLEAR_BSSID_V1_8821C(x) ((x) & (~BITS_BSSID_V1_8821C)) +#define BIT_GET_BSSID_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID_V1_8821C) & BIT_MASK_BSSID_V1_8821C) +#define BIT_SET_BSSID_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID_V1_8821C(x) | BIT_BSSID_V1_8821C(v)) +/* 2 REG_BSSID_H_8821C (BSSID REGISTER) */ -/* 2 REG_MAR_8821C (MULTICAST ADDRESS REGISTER) */ +/* 2 REG_NOT_VALID_8821C */ -#define BIT_SHIFT_MAR_8821C 0 -#define BIT_MASK_MAR_8821C 0xffffffffffffffffL -#define BIT_MAR_8821C(x) (((x) & BIT_MASK_MAR_8821C) << BIT_SHIFT_MAR_8821C) -#define BIT_GET_MAR_8821C(x) (((x) >> BIT_SHIFT_MAR_8821C) & BIT_MASK_MAR_8821C) +#define BIT_SHIFT_BSSID_H_V1_8821C 0 +#define BIT_MASK_BSSID_H_V1_8821C 0xffff +#define BIT_BSSID_H_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID_H_V1_8821C) << BIT_SHIFT_BSSID_H_V1_8821C) +#define BITS_BSSID_H_V1_8821C \ + (BIT_MASK_BSSID_H_V1_8821C << BIT_SHIFT_BSSID_H_V1_8821C) +#define BIT_CLEAR_BSSID_H_V1_8821C(x) ((x) & (~BITS_BSSID_H_V1_8821C)) +#define BIT_GET_BSSID_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID_H_V1_8821C) & BIT_MASK_BSSID_H_V1_8821C) +#define BIT_SET_BSSID_H_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID_H_V1_8821C(x) | BIT_BSSID_H_V1_8821C(v)) +/* 2 REG_MAR_8821C (MULTICAST ADDRESS REGISTER) */ +#define BIT_SHIFT_MAR_V1_8821C 0 +#define BIT_MASK_MAR_V1_8821C 0xffffffffL +#define BIT_MAR_V1_8821C(x) \ + (((x) & BIT_MASK_MAR_V1_8821C) << BIT_SHIFT_MAR_V1_8821C) +#define BITS_MAR_V1_8821C (BIT_MASK_MAR_V1_8821C << BIT_SHIFT_MAR_V1_8821C) +#define BIT_CLEAR_MAR_V1_8821C(x) ((x) & (~BITS_MAR_V1_8821C)) +#define BIT_GET_MAR_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MAR_V1_8821C) & BIT_MASK_MAR_V1_8821C) +#define BIT_SET_MAR_V1_8821C(x, v) \ + (BIT_CLEAR_MAR_V1_8821C(x) | BIT_MAR_V1_8821C(v)) + +/* 2 REG_MAR_H_8821C (MULTICAST ADDRESS REGISTER) */ + +#define BIT_SHIFT_MAR_H_V1_8821C 0 +#define BIT_MASK_MAR_H_V1_8821C 0xffffffffL +#define BIT_MAR_H_V1_8821C(x) \ + (((x) & BIT_MASK_MAR_H_V1_8821C) << BIT_SHIFT_MAR_H_V1_8821C) +#define BITS_MAR_H_V1_8821C \ + (BIT_MASK_MAR_H_V1_8821C << BIT_SHIFT_MAR_H_V1_8821C) +#define BIT_CLEAR_MAR_H_V1_8821C(x) ((x) & (~BITS_MAR_H_V1_8821C)) +#define BIT_GET_MAR_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MAR_H_V1_8821C) & BIT_MASK_MAR_H_V1_8821C) +#define BIT_SET_MAR_H_V1_8821C(x, v) \ + (BIT_CLEAR_MAR_H_V1_8821C(x) | BIT_MAR_H_V1_8821C(v)) /* 2 REG_MBIDCAMCFG_1_8821C (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_SHIFT_MBIDCAM_RWDATA_L_8821C 0 #define BIT_MASK_MBIDCAM_RWDATA_L_8821C 0xffffffffL -#define BIT_MBIDCAM_RWDATA_L_8821C(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8821C) << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) -#define BIT_GET_MBIDCAM_RWDATA_L_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) & BIT_MASK_MBIDCAM_RWDATA_L_8821C) - - +#define BIT_MBIDCAM_RWDATA_L_8821C(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8821C) \ + << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) +#define BITS_MBIDCAM_RWDATA_L_8821C \ + (BIT_MASK_MBIDCAM_RWDATA_L_8821C << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) +#define BIT_CLEAR_MBIDCAM_RWDATA_L_8821C(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_L_8821C)) +#define BIT_GET_MBIDCAM_RWDATA_L_8821C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) & \ + BIT_MASK_MBIDCAM_RWDATA_L_8821C) +#define BIT_SET_MBIDCAM_RWDATA_L_8821C(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_L_8821C(x) | BIT_MBIDCAM_RWDATA_L_8821C(v)) /* 2 REG_MBIDCAMCFG_2_8821C (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_MBIDCAM_POLL_8821C BIT(31) @@ -8671,9 +14332,15 @@ #define BIT_SHIFT_MBIDCAM_ADDR_8821C 24 #define BIT_MASK_MBIDCAM_ADDR_8821C 0x1f -#define BIT_MBIDCAM_ADDR_8821C(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8821C) << BIT_SHIFT_MBIDCAM_ADDR_8821C) -#define BIT_GET_MBIDCAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8821C) & BIT_MASK_MBIDCAM_ADDR_8821C) - +#define BIT_MBIDCAM_ADDR_8821C(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_8821C) << BIT_SHIFT_MBIDCAM_ADDR_8821C) +#define BITS_MBIDCAM_ADDR_8821C \ + (BIT_MASK_MBIDCAM_ADDR_8821C << BIT_SHIFT_MBIDCAM_ADDR_8821C) +#define BIT_CLEAR_MBIDCAM_ADDR_8821C(x) ((x) & (~BITS_MBIDCAM_ADDR_8821C)) +#define BIT_GET_MBIDCAM_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8821C) & BIT_MASK_MBIDCAM_ADDR_8821C) +#define BIT_SET_MBIDCAM_ADDR_8821C(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_8821C(x) | BIT_MBIDCAM_ADDR_8821C(v)) #define BIT_MBIDCAM_VALID_8821C BIT(23) #define BIT_LSIC_TXOP_EN_8821C BIT(17) @@ -8681,159 +14348,253 @@ #define BIT_SHIFT_MBIDCAM_RWDATA_H_8821C 0 #define BIT_MASK_MBIDCAM_RWDATA_H_8821C 0xffff -#define BIT_MBIDCAM_RWDATA_H_8821C(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8821C) << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) -#define BIT_GET_MBIDCAM_RWDATA_H_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) & BIT_MASK_MBIDCAM_RWDATA_H_8821C) - - - -/* 2 REG_ZLD_NUM_8821C */ - -#define BIT_SHIFT_ZLD_NUM_8821C 0 -#define BIT_MASK_ZLD_NUM_8821C 0xff -#define BIT_ZLD_NUM_8821C(x) (((x) & BIT_MASK_ZLD_NUM_8821C) << BIT_SHIFT_ZLD_NUM_8821C) -#define BIT_GET_ZLD_NUM_8821C(x) (((x) >> BIT_SHIFT_ZLD_NUM_8821C) & BIT_MASK_ZLD_NUM_8821C) - - - -/* 2 REG_UDF_THSD_8821C */ - -#define BIT_SHIFT_UDF_THSD_8821C 0 -#define BIT_MASK_UDF_THSD_8821C 0xff -#define BIT_UDF_THSD_8821C(x) (((x) & BIT_MASK_UDF_THSD_8821C) << BIT_SHIFT_UDF_THSD_8821C) -#define BIT_GET_UDF_THSD_8821C(x) (((x) >> BIT_SHIFT_UDF_THSD_8821C) & BIT_MASK_UDF_THSD_8821C) - - +#define BIT_MBIDCAM_RWDATA_H_8821C(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8821C) \ + << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) +#define BITS_MBIDCAM_RWDATA_H_8821C \ + (BIT_MASK_MBIDCAM_RWDATA_H_8821C << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) +#define BIT_CLEAR_MBIDCAM_RWDATA_H_8821C(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_H_8821C)) +#define BIT_GET_MBIDCAM_RWDATA_H_8821C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) & \ + BIT_MASK_MBIDCAM_RWDATA_H_8821C) +#define BIT_SET_MBIDCAM_RWDATA_H_8821C(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_H_8821C(x) | BIT_MBIDCAM_RWDATA_H_8821C(v)) /* 2 REG_WMAC_TCR_TSFT_OFS_8821C */ #define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C 0 #define BIT_MASK_WMAC_TCR_TSFT_OFS_8821C 0xffff -#define BIT_WMAC_TCR_TSFT_OFS_8821C(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) -#define BIT_GET_WMAC_TCR_TSFT_OFS_8821C(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) +#define BIT_WMAC_TCR_TSFT_OFS_8821C(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) \ + << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) +#define BITS_WMAC_TCR_TSFT_OFS_8821C \ + (BIT_MASK_WMAC_TCR_TSFT_OFS_8821C << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8821C(x) \ + ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8821C)) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) & \ + BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) +#define BIT_SET_WMAC_TCR_TSFT_OFS_8821C(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8821C(x) | BIT_WMAC_TCR_TSFT_OFS_8821C(v)) +/* 2 REG_UDF_THSD_8821C */ +#define BIT_SHIFT_UDF_THSD_8821C 0 +#define BIT_MASK_UDF_THSD_8821C 0xff +#define BIT_UDF_THSD_8821C(x) \ + (((x) & BIT_MASK_UDF_THSD_8821C) << BIT_SHIFT_UDF_THSD_8821C) +#define BITS_UDF_THSD_8821C \ + (BIT_MASK_UDF_THSD_8821C << BIT_SHIFT_UDF_THSD_8821C) +#define BIT_CLEAR_UDF_THSD_8821C(x) ((x) & (~BITS_UDF_THSD_8821C)) +#define BIT_GET_UDF_THSD_8821C(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_8821C) & BIT_MASK_UDF_THSD_8821C) +#define BIT_SET_UDF_THSD_8821C(x, v) \ + (BIT_CLEAR_UDF_THSD_8821C(x) | BIT_UDF_THSD_8821C(v)) -/* 2 REG_MCU_TEST_2_V1_8821C */ +/* 2 REG_ZLD_NUM_8821C */ -#define BIT_SHIFT_MCU_RSVD_2_V1_8821C 0 -#define BIT_MASK_MCU_RSVD_2_V1_8821C 0xffff -#define BIT_MCU_RSVD_2_V1_8821C(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8821C) << BIT_SHIFT_MCU_RSVD_2_V1_8821C) -#define BIT_GET_MCU_RSVD_2_V1_8821C(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8821C) & BIT_MASK_MCU_RSVD_2_V1_8821C) +#define BIT_SHIFT_ZLD_NUM_8821C 0 +#define BIT_MASK_ZLD_NUM_8821C 0xff +#define BIT_ZLD_NUM_8821C(x) \ + (((x) & BIT_MASK_ZLD_NUM_8821C) << BIT_SHIFT_ZLD_NUM_8821C) +#define BITS_ZLD_NUM_8821C (BIT_MASK_ZLD_NUM_8821C << BIT_SHIFT_ZLD_NUM_8821C) +#define BIT_CLEAR_ZLD_NUM_8821C(x) ((x) & (~BITS_ZLD_NUM_8821C)) +#define BIT_GET_ZLD_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_ZLD_NUM_8821C) & BIT_MASK_ZLD_NUM_8821C) +#define BIT_SET_ZLD_NUM_8821C(x, v) \ + (BIT_CLEAR_ZLD_NUM_8821C(x) | BIT_ZLD_NUM_8821C(v)) +/* 2 REG_STMP_THSD_8821C */ +#define BIT_SHIFT_STMP_THSD_8821C 0 +#define BIT_MASK_STMP_THSD_8821C 0xff +#define BIT_STMP_THSD_8821C(x) \ + (((x) & BIT_MASK_STMP_THSD_8821C) << BIT_SHIFT_STMP_THSD_8821C) +#define BITS_STMP_THSD_8821C \ + (BIT_MASK_STMP_THSD_8821C << BIT_SHIFT_STMP_THSD_8821C) +#define BIT_CLEAR_STMP_THSD_8821C(x) ((x) & (~BITS_STMP_THSD_8821C)) +#define BIT_GET_STMP_THSD_8821C(x) \ + (((x) >> BIT_SHIFT_STMP_THSD_8821C) & BIT_MASK_STMP_THSD_8821C) +#define BIT_SET_STMP_THSD_8821C(x, v) \ + (BIT_CLEAR_STMP_THSD_8821C(x) | BIT_STMP_THSD_8821C(v)) /* 2 REG_WMAC_TXTIMEOUT_8821C */ #define BIT_SHIFT_WMAC_TXTIMEOUT_8821C 0 #define BIT_MASK_WMAC_TXTIMEOUT_8821C 0xff -#define BIT_WMAC_TXTIMEOUT_8821C(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8821C) << BIT_SHIFT_WMAC_TXTIMEOUT_8821C) -#define BIT_GET_WMAC_TXTIMEOUT_8821C(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8821C) & BIT_MASK_WMAC_TXTIMEOUT_8821C) +#define BIT_WMAC_TXTIMEOUT_8821C(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT_8821C) \ + << BIT_SHIFT_WMAC_TXTIMEOUT_8821C) +#define BITS_WMAC_TXTIMEOUT_8821C \ + (BIT_MASK_WMAC_TXTIMEOUT_8821C << BIT_SHIFT_WMAC_TXTIMEOUT_8821C) +#define BIT_CLEAR_WMAC_TXTIMEOUT_8821C(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8821C)) +#define BIT_GET_WMAC_TXTIMEOUT_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8821C) & \ + BIT_MASK_WMAC_TXTIMEOUT_8821C) +#define BIT_SET_WMAC_TXTIMEOUT_8821C(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT_8821C(x) | BIT_WMAC_TXTIMEOUT_8821C(v)) +/* 2 REG_MCU_TEST_2_V1_8821C */ +#define BIT_SHIFT_MCU_RSVD_2_V1_8821C 0 +#define BIT_MASK_MCU_RSVD_2_V1_8821C 0xffff +#define BIT_MCU_RSVD_2_V1_8821C(x) \ + (((x) & BIT_MASK_MCU_RSVD_2_V1_8821C) << BIT_SHIFT_MCU_RSVD_2_V1_8821C) +#define BITS_MCU_RSVD_2_V1_8821C \ + (BIT_MASK_MCU_RSVD_2_V1_8821C << BIT_SHIFT_MCU_RSVD_2_V1_8821C) +#define BIT_CLEAR_MCU_RSVD_2_V1_8821C(x) ((x) & (~BITS_MCU_RSVD_2_V1_8821C)) +#define BIT_GET_MCU_RSVD_2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8821C) & BIT_MASK_MCU_RSVD_2_V1_8821C) +#define BIT_SET_MCU_RSVD_2_V1_8821C(x, v) \ + (BIT_CLEAR_MCU_RSVD_2_V1_8821C(x) | BIT_MCU_RSVD_2_V1_8821C(v)) -/* 2 REG_STMP_THSD_8821C */ +/* 2 REG_USTIME_EDCA_8821C (US TIME TUNING FOR EDCA REGISTER) */ -#define BIT_SHIFT_STMP_THSD_8821C 0 -#define BIT_MASK_STMP_THSD_8821C 0xff -#define BIT_STMP_THSD_8821C(x) (((x) & BIT_MASK_STMP_THSD_8821C) << BIT_SHIFT_STMP_THSD_8821C) -#define BIT_GET_STMP_THSD_8821C(x) (((x) >> BIT_SHIFT_STMP_THSD_8821C) & BIT_MASK_STMP_THSD_8821C) +#define BIT_SHIFT_USTIME_EDCA_8821C 0 +#define BIT_MASK_USTIME_EDCA_8821C 0xff +#define BIT_USTIME_EDCA_8821C(x) \ + (((x) & BIT_MASK_USTIME_EDCA_8821C) << BIT_SHIFT_USTIME_EDCA_8821C) +#define BITS_USTIME_EDCA_8821C \ + (BIT_MASK_USTIME_EDCA_8821C << BIT_SHIFT_USTIME_EDCA_8821C) +#define BIT_CLEAR_USTIME_EDCA_8821C(x) ((x) & (~BITS_USTIME_EDCA_8821C)) +#define BIT_GET_USTIME_EDCA_8821C(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_8821C) & BIT_MASK_USTIME_EDCA_8821C) +#define BIT_SET_USTIME_EDCA_8821C(x, v) \ + (BIT_CLEAR_USTIME_EDCA_8821C(x) | BIT_USTIME_EDCA_8821C(v)) +/* 2 REG_ACKTO_CCK_8821C (ACK TIMEOUT REGISTER FOR CCK RATE) */ +#define BIT_SHIFT_ACKTO_CCK_8821C 0 +#define BIT_MASK_ACKTO_CCK_8821C 0xff +#define BIT_ACKTO_CCK_8821C(x) \ + (((x) & BIT_MASK_ACKTO_CCK_8821C) << BIT_SHIFT_ACKTO_CCK_8821C) +#define BITS_ACKTO_CCK_8821C \ + (BIT_MASK_ACKTO_CCK_8821C << BIT_SHIFT_ACKTO_CCK_8821C) +#define BIT_CLEAR_ACKTO_CCK_8821C(x) ((x) & (~BITS_ACKTO_CCK_8821C)) +#define BIT_GET_ACKTO_CCK_8821C(x) \ + (((x) >> BIT_SHIFT_ACKTO_CCK_8821C) & BIT_MASK_ACKTO_CCK_8821C) +#define BIT_SET_ACKTO_CCK_8821C(x, v) \ + (BIT_CLEAR_ACKTO_CCK_8821C(x) | BIT_ACKTO_CCK_8821C(v)) /* 2 REG_MAC_SPEC_SIFS_8821C (SPECIFICATION SIFS REGISTER) */ #define BIT_SHIFT_SPEC_SIFS_OFDM_8821C 8 #define BIT_MASK_SPEC_SIFS_OFDM_8821C 0xff -#define BIT_SPEC_SIFS_OFDM_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8821C) << BIT_SHIFT_SPEC_SIFS_OFDM_8821C) -#define BIT_GET_SPEC_SIFS_OFDM_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8821C) & BIT_MASK_SPEC_SIFS_OFDM_8821C) - - +#define BIT_SPEC_SIFS_OFDM_8821C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_8821C) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_8821C) +#define BITS_SPEC_SIFS_OFDM_8821C \ + (BIT_MASK_SPEC_SIFS_OFDM_8821C << BIT_SHIFT_SPEC_SIFS_OFDM_8821C) +#define BIT_CLEAR_SPEC_SIFS_OFDM_8821C(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8821C)) +#define BIT_GET_SPEC_SIFS_OFDM_8821C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8821C) & \ + BIT_MASK_SPEC_SIFS_OFDM_8821C) +#define BIT_SET_SPEC_SIFS_OFDM_8821C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_8821C(x) | BIT_SPEC_SIFS_OFDM_8821C(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_8821C 0 #define BIT_MASK_SPEC_SIFS_CCK_8821C 0xff -#define BIT_SPEC_SIFS_CCK_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_8821C) -#define BIT_GET_SPEC_SIFS_CCK_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8821C) & BIT_MASK_SPEC_SIFS_CCK_8821C) +#define BIT_SPEC_SIFS_CCK_8821C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_8821C) +#define BITS_SPEC_SIFS_CCK_8821C \ + (BIT_MASK_SPEC_SIFS_CCK_8821C << BIT_SHIFT_SPEC_SIFS_CCK_8821C) +#define BIT_CLEAR_SPEC_SIFS_CCK_8821C(x) ((x) & (~BITS_SPEC_SIFS_CCK_8821C)) +#define BIT_GET_SPEC_SIFS_CCK_8821C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8821C) & BIT_MASK_SPEC_SIFS_CCK_8821C) +#define BIT_SET_SPEC_SIFS_CCK_8821C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_8821C(x) | BIT_SPEC_SIFS_CCK_8821C(v)) +/* 2 REG_RESP_SIFS_CCK_8821C (RESPONSE SIFS FOR CCK REGISTER) */ +#define BIT_SHIFT_SIFS_R2T_CCK_8821C 8 +#define BIT_MASK_SIFS_R2T_CCK_8821C 0xff +#define BIT_SIFS_R2T_CCK_8821C(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK_8821C) << BIT_SHIFT_SIFS_R2T_CCK_8821C) +#define BITS_SIFS_R2T_CCK_8821C \ + (BIT_MASK_SIFS_R2T_CCK_8821C << BIT_SHIFT_SIFS_R2T_CCK_8821C) +#define BIT_CLEAR_SIFS_R2T_CCK_8821C(x) ((x) & (~BITS_SIFS_R2T_CCK_8821C)) +#define BIT_GET_SIFS_R2T_CCK_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8821C) & BIT_MASK_SIFS_R2T_CCK_8821C) +#define BIT_SET_SIFS_R2T_CCK_8821C(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK_8821C(x) | BIT_SIFS_R2T_CCK_8821C(v)) -/* 2 REG_ACKTO_CCK_8821C (ACK TIMEOUT REGISTER FOR CCK RATE) */ - -#define BIT_SHIFT_ACKTO_CCK_8821C 0 -#define BIT_MASK_ACKTO_CCK_8821C 0xff -#define BIT_ACKTO_CCK_8821C(x) (((x) & BIT_MASK_ACKTO_CCK_8821C) << BIT_SHIFT_ACKTO_CCK_8821C) -#define BIT_GET_ACKTO_CCK_8821C(x) (((x) >> BIT_SHIFT_ACKTO_CCK_8821C) & BIT_MASK_ACKTO_CCK_8821C) - - - -/* 2 REG_USTIME_EDCA_8821C (US TIME TUNING FOR EDCA REGISTER) */ - -#define BIT_SHIFT_USTIME_EDCA_V1_8821C 0 -#define BIT_MASK_USTIME_EDCA_V1_8821C 0x1ff -#define BIT_USTIME_EDCA_V1_8821C(x) (((x) & BIT_MASK_USTIME_EDCA_V1_8821C) << BIT_SHIFT_USTIME_EDCA_V1_8821C) -#define BIT_GET_USTIME_EDCA_V1_8821C(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8821C) & BIT_MASK_USTIME_EDCA_V1_8821C) - - +#define BIT_SHIFT_SIFS_T2T_CCK_8821C 0 +#define BIT_MASK_SIFS_T2T_CCK_8821C 0xff +#define BIT_SIFS_T2T_CCK_8821C(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK_8821C) << BIT_SHIFT_SIFS_T2T_CCK_8821C) +#define BITS_SIFS_T2T_CCK_8821C \ + (BIT_MASK_SIFS_T2T_CCK_8821C << BIT_SHIFT_SIFS_T2T_CCK_8821C) +#define BIT_CLEAR_SIFS_T2T_CCK_8821C(x) ((x) & (~BITS_SIFS_T2T_CCK_8821C)) +#define BIT_GET_SIFS_T2T_CCK_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8821C) & BIT_MASK_SIFS_T2T_CCK_8821C) +#define BIT_SET_SIFS_T2T_CCK_8821C(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK_8821C(x) | BIT_SIFS_T2T_CCK_8821C(v)) /* 2 REG_RESP_SIFS_OFDM_8821C (RESPONSE SIFS FOR OFDM REGISTER) */ #define BIT_SHIFT_SIFS_R2T_OFDM_8821C 8 #define BIT_MASK_SIFS_R2T_OFDM_8821C 0xff -#define BIT_SIFS_R2T_OFDM_8821C(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8821C) << BIT_SHIFT_SIFS_R2T_OFDM_8821C) -#define BIT_GET_SIFS_R2T_OFDM_8821C(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8821C) & BIT_MASK_SIFS_R2T_OFDM_8821C) - - +#define BIT_SIFS_R2T_OFDM_8821C(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM_8821C) << BIT_SHIFT_SIFS_R2T_OFDM_8821C) +#define BITS_SIFS_R2T_OFDM_8821C \ + (BIT_MASK_SIFS_R2T_OFDM_8821C << BIT_SHIFT_SIFS_R2T_OFDM_8821C) +#define BIT_CLEAR_SIFS_R2T_OFDM_8821C(x) ((x) & (~BITS_SIFS_R2T_OFDM_8821C)) +#define BIT_GET_SIFS_R2T_OFDM_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8821C) & BIT_MASK_SIFS_R2T_OFDM_8821C) +#define BIT_SET_SIFS_R2T_OFDM_8821C(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM_8821C(x) | BIT_SIFS_R2T_OFDM_8821C(v)) #define BIT_SHIFT_SIFS_T2T_OFDM_8821C 0 #define BIT_MASK_SIFS_T2T_OFDM_8821C 0xff -#define BIT_SIFS_T2T_OFDM_8821C(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8821C) << BIT_SHIFT_SIFS_T2T_OFDM_8821C) -#define BIT_GET_SIFS_T2T_OFDM_8821C(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8821C) & BIT_MASK_SIFS_T2T_OFDM_8821C) - - - -/* 2 REG_RESP_SIFS_CCK_8821C (RESPONSE SIFS FOR CCK REGISTER) */ - -#define BIT_SHIFT_SIFS_R2T_CCK_8821C 8 -#define BIT_MASK_SIFS_R2T_CCK_8821C 0xff -#define BIT_SIFS_R2T_CCK_8821C(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8821C) << BIT_SHIFT_SIFS_R2T_CCK_8821C) -#define BIT_GET_SIFS_R2T_CCK_8821C(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8821C) & BIT_MASK_SIFS_R2T_CCK_8821C) - +#define BIT_SIFS_T2T_OFDM_8821C(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM_8821C) << BIT_SHIFT_SIFS_T2T_OFDM_8821C) +#define BITS_SIFS_T2T_OFDM_8821C \ + (BIT_MASK_SIFS_T2T_OFDM_8821C << BIT_SHIFT_SIFS_T2T_OFDM_8821C) +#define BIT_CLEAR_SIFS_T2T_OFDM_8821C(x) ((x) & (~BITS_SIFS_T2T_OFDM_8821C)) +#define BIT_GET_SIFS_T2T_OFDM_8821C(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8821C) & BIT_MASK_SIFS_T2T_OFDM_8821C) +#define BIT_SET_SIFS_T2T_OFDM_8821C(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM_8821C(x) | BIT_SIFS_T2T_OFDM_8821C(v)) +/* 2 REG_ACKTO_8821C (ACK TIMEOUT REGISTER) */ -#define BIT_SHIFT_SIFS_T2T_CCK_8821C 0 -#define BIT_MASK_SIFS_T2T_CCK_8821C 0xff -#define BIT_SIFS_T2T_CCK_8821C(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8821C) << BIT_SHIFT_SIFS_T2T_CCK_8821C) -#define BIT_GET_SIFS_T2T_CCK_8821C(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8821C) & BIT_MASK_SIFS_T2T_CCK_8821C) +#define BIT_SHIFT_ACKTO_8821C 0 +#define BIT_MASK_ACKTO_8821C 0xff +#define BIT_ACKTO_8821C(x) \ + (((x) & BIT_MASK_ACKTO_8821C) << BIT_SHIFT_ACKTO_8821C) +#define BITS_ACKTO_8821C (BIT_MASK_ACKTO_8821C << BIT_SHIFT_ACKTO_8821C) +#define BIT_CLEAR_ACKTO_8821C(x) ((x) & (~BITS_ACKTO_8821C)) +#define BIT_GET_ACKTO_8821C(x) \ + (((x) >> BIT_SHIFT_ACKTO_8821C) & BIT_MASK_ACKTO_8821C) +#define BIT_SET_ACKTO_8821C(x, v) \ + (BIT_CLEAR_ACKTO_8821C(x) | BIT_ACKTO_8821C(v)) +/* 2 REG_CTS2TO_8821C (CTS2 TIMEOUT REGISTER) */ +#define BIT_SHIFT_CTS2TO_8821C 0 +#define BIT_MASK_CTS2TO_8821C 0xff +#define BIT_CTS2TO_8821C(x) \ + (((x) & BIT_MASK_CTS2TO_8821C) << BIT_SHIFT_CTS2TO_8821C) +#define BITS_CTS2TO_8821C (BIT_MASK_CTS2TO_8821C << BIT_SHIFT_CTS2TO_8821C) +#define BIT_CLEAR_CTS2TO_8821C(x) ((x) & (~BITS_CTS2TO_8821C)) +#define BIT_GET_CTS2TO_8821C(x) \ + (((x) >> BIT_SHIFT_CTS2TO_8821C) & BIT_MASK_CTS2TO_8821C) +#define BIT_SET_CTS2TO_8821C(x, v) \ + (BIT_CLEAR_CTS2TO_8821C(x) | BIT_CTS2TO_8821C(v)) /* 2 REG_EIFS_8821C (EIFS REGISTER) */ #define BIT_SHIFT_EIFS_8821C 0 #define BIT_MASK_EIFS_8821C 0xffff #define BIT_EIFS_8821C(x) (((x) & BIT_MASK_EIFS_8821C) << BIT_SHIFT_EIFS_8821C) -#define BIT_GET_EIFS_8821C(x) (((x) >> BIT_SHIFT_EIFS_8821C) & BIT_MASK_EIFS_8821C) - - - -/* 2 REG_CTS2TO_8821C (CTS2 TIMEOUT REGISTER) */ - -#define BIT_SHIFT_CTS2TO_8821C 0 -#define BIT_MASK_CTS2TO_8821C 0xff -#define BIT_CTS2TO_8821C(x) (((x) & BIT_MASK_CTS2TO_8821C) << BIT_SHIFT_CTS2TO_8821C) -#define BIT_GET_CTS2TO_8821C(x) (((x) >> BIT_SHIFT_CTS2TO_8821C) & BIT_MASK_CTS2TO_8821C) - - - -/* 2 REG_ACKTO_8821C (ACK TIMEOUT REGISTER) */ - -#define BIT_SHIFT_ACKTO_8821C 0 -#define BIT_MASK_ACKTO_8821C 0xff -#define BIT_ACKTO_8821C(x) (((x) & BIT_MASK_ACKTO_8821C) << BIT_SHIFT_ACKTO_8821C) -#define BIT_GET_ACKTO_8821C(x) (((x) >> BIT_SHIFT_ACKTO_8821C) & BIT_MASK_ACKTO_8821C) +#define BITS_EIFS_8821C (BIT_MASK_EIFS_8821C << BIT_SHIFT_EIFS_8821C) +#define BIT_CLEAR_EIFS_8821C(x) ((x) & (~BITS_EIFS_8821C)) +#define BIT_GET_EIFS_8821C(x) \ + (((x) >> BIT_SHIFT_EIFS_8821C) & BIT_MASK_EIFS_8821C) +#define BIT_SET_EIFS_8821C(x, v) (BIT_CLEAR_EIFS_8821C(x) | BIT_EIFS_8821C(v)) - - -/* 2 REG_RPFM_MAP0_8821C (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 0) */ +/* 2 REG_RPFM_MAP0_8821C */ #define BIT_MGT_RPFM15EN_8821C BIT(15) #define BIT_MGT_RPFM14EN_8821C BIT(14) #define BIT_MGT_RPFM13EN_8821C BIT(13) @@ -8851,7 +14612,7 @@ #define BIT_MGT_RPFM1EN_8821C BIT(1) #define BIT_MGT_RPFM0EN_8821C BIT(0) -/* 2 REG_RPFM_MAP1_8821C (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 1) */ +/* 2 REG_RPFM_MAP1_V1_8821C */ #define BIT_DATA_RPFM15EN_8821C BIT(15) #define BIT_DATA_RPFM14EN_8821C BIT(14) #define BIT_DATA_RPFM13EN_8821C BIT(13) @@ -8876,44 +14637,66 @@ #define BIT_SHIFT_RPFM_CAM_ADDR_8821C 0 #define BIT_MASK_RPFM_CAM_ADDR_8821C 0x7f -#define BIT_RPFM_CAM_ADDR_8821C(x) (((x) & BIT_MASK_RPFM_CAM_ADDR_8821C) << BIT_SHIFT_RPFM_CAM_ADDR_8821C) -#define BIT_GET_RPFM_CAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8821C) & BIT_MASK_RPFM_CAM_ADDR_8821C) - - +#define BIT_RPFM_CAM_ADDR_8821C(x) \ + (((x) & BIT_MASK_RPFM_CAM_ADDR_8821C) << BIT_SHIFT_RPFM_CAM_ADDR_8821C) +#define BITS_RPFM_CAM_ADDR_8821C \ + (BIT_MASK_RPFM_CAM_ADDR_8821C << BIT_SHIFT_RPFM_CAM_ADDR_8821C) +#define BIT_CLEAR_RPFM_CAM_ADDR_8821C(x) ((x) & (~BITS_RPFM_CAM_ADDR_8821C)) +#define BIT_GET_RPFM_CAM_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8821C) & BIT_MASK_RPFM_CAM_ADDR_8821C) +#define BIT_SET_RPFM_CAM_ADDR_8821C(x, v) \ + (BIT_CLEAR_RPFM_CAM_ADDR_8821C(x) | BIT_RPFM_CAM_ADDR_8821C(v)) /* 2 REG_RPFM_CAM_RWD_8821C (ACK TIMEOUT REGISTER) */ #define BIT_SHIFT_RPFM_CAM_RWD_8821C 0 #define BIT_MASK_RPFM_CAM_RWD_8821C 0xffffffffL -#define BIT_RPFM_CAM_RWD_8821C(x) (((x) & BIT_MASK_RPFM_CAM_RWD_8821C) << BIT_SHIFT_RPFM_CAM_RWD_8821C) -#define BIT_GET_RPFM_CAM_RWD_8821C(x) (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8821C) & BIT_MASK_RPFM_CAM_RWD_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_RPFM_CAM_RWD_8821C(x) \ + (((x) & BIT_MASK_RPFM_CAM_RWD_8821C) << BIT_SHIFT_RPFM_CAM_RWD_8821C) +#define BITS_RPFM_CAM_RWD_8821C \ + (BIT_MASK_RPFM_CAM_RWD_8821C << BIT_SHIFT_RPFM_CAM_RWD_8821C) +#define BIT_CLEAR_RPFM_CAM_RWD_8821C(x) ((x) & (~BITS_RPFM_CAM_RWD_8821C)) +#define BIT_GET_RPFM_CAM_RWD_8821C(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8821C) & BIT_MASK_RPFM_CAM_RWD_8821C) +#define BIT_SET_RPFM_CAM_RWD_8821C(x, v) \ + (BIT_CLEAR_RPFM_CAM_RWD_8821C(x) | BIT_RPFM_CAM_RWD_8821C(v)) /* 2 REG_NAV_CTRL_8821C (NAV CONTROL REGISTER) */ #define BIT_SHIFT_NAV_UPPER_8821C 16 #define BIT_MASK_NAV_UPPER_8821C 0xff -#define BIT_NAV_UPPER_8821C(x) (((x) & BIT_MASK_NAV_UPPER_8821C) << BIT_SHIFT_NAV_UPPER_8821C) -#define BIT_GET_NAV_UPPER_8821C(x) (((x) >> BIT_SHIFT_NAV_UPPER_8821C) & BIT_MASK_NAV_UPPER_8821C) - - +#define BIT_NAV_UPPER_8821C(x) \ + (((x) & BIT_MASK_NAV_UPPER_8821C) << BIT_SHIFT_NAV_UPPER_8821C) +#define BITS_NAV_UPPER_8821C \ + (BIT_MASK_NAV_UPPER_8821C << BIT_SHIFT_NAV_UPPER_8821C) +#define BIT_CLEAR_NAV_UPPER_8821C(x) ((x) & (~BITS_NAV_UPPER_8821C)) +#define BIT_GET_NAV_UPPER_8821C(x) \ + (((x) >> BIT_SHIFT_NAV_UPPER_8821C) & BIT_MASK_NAV_UPPER_8821C) +#define BIT_SET_NAV_UPPER_8821C(x, v) \ + (BIT_CLEAR_NAV_UPPER_8821C(x) | BIT_NAV_UPPER_8821C(v)) #define BIT_SHIFT_RXMYRTS_NAV_8821C 8 #define BIT_MASK_RXMYRTS_NAV_8821C 0xf -#define BIT_RXMYRTS_NAV_8821C(x) (((x) & BIT_MASK_RXMYRTS_NAV_8821C) << BIT_SHIFT_RXMYRTS_NAV_8821C) -#define BIT_GET_RXMYRTS_NAV_8821C(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8821C) & BIT_MASK_RXMYRTS_NAV_8821C) - - +#define BIT_RXMYRTS_NAV_8821C(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_8821C) << BIT_SHIFT_RXMYRTS_NAV_8821C) +#define BITS_RXMYRTS_NAV_8821C \ + (BIT_MASK_RXMYRTS_NAV_8821C << BIT_SHIFT_RXMYRTS_NAV_8821C) +#define BIT_CLEAR_RXMYRTS_NAV_8821C(x) ((x) & (~BITS_RXMYRTS_NAV_8821C)) +#define BIT_GET_RXMYRTS_NAV_8821C(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_8821C) & BIT_MASK_RXMYRTS_NAV_8821C) +#define BIT_SET_RXMYRTS_NAV_8821C(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_8821C(x) | BIT_RXMYRTS_NAV_8821C(v)) #define BIT_SHIFT_RTSRST_8821C 0 #define BIT_MASK_RTSRST_8821C 0xff -#define BIT_RTSRST_8821C(x) (((x) & BIT_MASK_RTSRST_8821C) << BIT_SHIFT_RTSRST_8821C) -#define BIT_GET_RTSRST_8821C(x) (((x) >> BIT_SHIFT_RTSRST_8821C) & BIT_MASK_RTSRST_8821C) - - +#define BIT_RTSRST_8821C(x) \ + (((x) & BIT_MASK_RTSRST_8821C) << BIT_SHIFT_RTSRST_8821C) +#define BITS_RTSRST_8821C (BIT_MASK_RTSRST_8821C << BIT_SHIFT_RTSRST_8821C) +#define BIT_CLEAR_RTSRST_8821C(x) ((x) & (~BITS_RTSRST_8821C)) +#define BIT_GET_RTSRST_8821C(x) \ + (((x) >> BIT_SHIFT_RTSRST_8821C) & BIT_MASK_RTSRST_8821C) +#define BIT_SET_RTSRST_8821C(x, v) \ + (BIT_CLEAR_RTSRST_8821C(x) | BIT_RTSRST_8821C(v)) /* 2 REG_BACAMCMD_8821C (BLOCK ACK CAM COMMAND REGISTER) */ #define BIT_BACAM_POLL_8821C BIT(31) @@ -8922,87 +14705,149 @@ #define BIT_SHIFT_TXSBM_8821C 14 #define BIT_MASK_TXSBM_8821C 0x3 -#define BIT_TXSBM_8821C(x) (((x) & BIT_MASK_TXSBM_8821C) << BIT_SHIFT_TXSBM_8821C) -#define BIT_GET_TXSBM_8821C(x) (((x) >> BIT_SHIFT_TXSBM_8821C) & BIT_MASK_TXSBM_8821C) - - +#define BIT_TXSBM_8821C(x) \ + (((x) & BIT_MASK_TXSBM_8821C) << BIT_SHIFT_TXSBM_8821C) +#define BITS_TXSBM_8821C (BIT_MASK_TXSBM_8821C << BIT_SHIFT_TXSBM_8821C) +#define BIT_CLEAR_TXSBM_8821C(x) ((x) & (~BITS_TXSBM_8821C)) +#define BIT_GET_TXSBM_8821C(x) \ + (((x) >> BIT_SHIFT_TXSBM_8821C) & BIT_MASK_TXSBM_8821C) +#define BIT_SET_TXSBM_8821C(x, v) \ + (BIT_CLEAR_TXSBM_8821C(x) | BIT_TXSBM_8821C(v)) #define BIT_SHIFT_BACAM_ADDR_8821C 0 #define BIT_MASK_BACAM_ADDR_8821C 0x3f -#define BIT_BACAM_ADDR_8821C(x) (((x) & BIT_MASK_BACAM_ADDR_8821C) << BIT_SHIFT_BACAM_ADDR_8821C) -#define BIT_GET_BACAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8821C) & BIT_MASK_BACAM_ADDR_8821C) - - +#define BIT_BACAM_ADDR_8821C(x) \ + (((x) & BIT_MASK_BACAM_ADDR_8821C) << BIT_SHIFT_BACAM_ADDR_8821C) +#define BITS_BACAM_ADDR_8821C \ + (BIT_MASK_BACAM_ADDR_8821C << BIT_SHIFT_BACAM_ADDR_8821C) +#define BIT_CLEAR_BACAM_ADDR_8821C(x) ((x) & (~BITS_BACAM_ADDR_8821C)) +#define BIT_GET_BACAM_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR_8821C) & BIT_MASK_BACAM_ADDR_8821C) +#define BIT_SET_BACAM_ADDR_8821C(x, v) \ + (BIT_CLEAR_BACAM_ADDR_8821C(x) | BIT_BACAM_ADDR_8821C(v)) /* 2 REG_BACAMCONTENT_8821C (BLOCK ACK CAM CONTENT REGISTER) */ -#define BIT_SHIFT_BA_CONTENT_H_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_BA_CONTENT_H_8821C 0xffffffffL -#define BIT_BA_CONTENT_H_8821C(x) (((x) & BIT_MASK_BA_CONTENT_H_8821C) << BIT_SHIFT_BA_CONTENT_H_8821C) -#define BIT_GET_BA_CONTENT_H_8821C(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8821C) & BIT_MASK_BA_CONTENT_H_8821C) - - - #define BIT_SHIFT_BA_CONTENT_L_8821C 0 #define BIT_MASK_BA_CONTENT_L_8821C 0xffffffffL -#define BIT_BA_CONTENT_L_8821C(x) (((x) & BIT_MASK_BA_CONTENT_L_8821C) << BIT_SHIFT_BA_CONTENT_L_8821C) -#define BIT_GET_BA_CONTENT_L_8821C(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8821C) & BIT_MASK_BA_CONTENT_L_8821C) - - - -/* 2 REG_WMAC_BITMAP_CTL_8821C */ -#define BIT_BITMAP_VO_8821C BIT(7) -#define BIT_BITMAP_VI_8821C BIT(6) -#define BIT_BITMAP_BE_8821C BIT(5) -#define BIT_BITMAP_BK_8821C BIT(4) - -#define BIT_SHIFT_BITMAP_CONDITION_8821C 2 -#define BIT_MASK_BITMAP_CONDITION_8821C 0x3 -#define BIT_BITMAP_CONDITION_8821C(x) (((x) & BIT_MASK_BITMAP_CONDITION_8821C) << BIT_SHIFT_BITMAP_CONDITION_8821C) -#define BIT_GET_BITMAP_CONDITION_8821C(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8821C) & BIT_MASK_BITMAP_CONDITION_8821C) - - -#define BIT_BITMAP_SSNBK_COUNTER_CLR_8821C BIT(1) -#define BIT_BITMAP_FORCE_8821C BIT(0) - -/* 2 REG_TX_RX_8821C STATUS */ - -#define BIT_SHIFT_RXPKT_TYPE_8821C 2 -#define BIT_MASK_RXPKT_TYPE_8821C 0x3f -#define BIT_RXPKT_TYPE_8821C(x) (((x) & BIT_MASK_RXPKT_TYPE_8821C) << BIT_SHIFT_RXPKT_TYPE_8821C) -#define BIT_GET_RXPKT_TYPE_8821C(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8821C) & BIT_MASK_RXPKT_TYPE_8821C) +#define BIT_BA_CONTENT_L_8821C(x) \ + (((x) & BIT_MASK_BA_CONTENT_L_8821C) << BIT_SHIFT_BA_CONTENT_L_8821C) +#define BITS_BA_CONTENT_L_8821C \ + (BIT_MASK_BA_CONTENT_L_8821C << BIT_SHIFT_BA_CONTENT_L_8821C) +#define BIT_CLEAR_BA_CONTENT_L_8821C(x) ((x) & (~BITS_BA_CONTENT_L_8821C)) +#define BIT_GET_BA_CONTENT_L_8821C(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L_8821C) & BIT_MASK_BA_CONTENT_L_8821C) +#define BIT_SET_BA_CONTENT_L_8821C(x, v) \ + (BIT_CLEAR_BA_CONTENT_L_8821C(x) | BIT_BA_CONTENT_L_8821C(v)) + +/* 2 REG_BACAMCONTENT_H_8821C (BLOCK ACK CAM CONTENT REGISTER) */ + +#define BIT_SHIFT_BA_CONTENT_H_8821C 0 +#define BIT_MASK_BA_CONTENT_H_8821C 0xffffffffL +#define BIT_BA_CONTENT_H_8821C(x) \ + (((x) & BIT_MASK_BA_CONTENT_H_8821C) << BIT_SHIFT_BA_CONTENT_H_8821C) +#define BITS_BA_CONTENT_H_8821C \ + (BIT_MASK_BA_CONTENT_H_8821C << BIT_SHIFT_BA_CONTENT_H_8821C) +#define BIT_CLEAR_BA_CONTENT_H_8821C(x) ((x) & (~BITS_BA_CONTENT_H_8821C)) +#define BIT_GET_BA_CONTENT_H_8821C(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_H_8821C) & BIT_MASK_BA_CONTENT_H_8821C) +#define BIT_SET_BA_CONTENT_H_8821C(x, v) \ + (BIT_CLEAR_BA_CONTENT_H_8821C(x) | BIT_BA_CONTENT_H_8821C(v)) +/* 2 REG_LBDLY_8821C (LOOPBACK DELAY REGISTER) */ -#define BIT_TXACT_IND_8821C BIT(1) -#define BIT_RXACT_IND_8821C BIT(0) +#define BIT_SHIFT_LBDLY_8821C 0 +#define BIT_MASK_LBDLY_8821C 0x1f +#define BIT_LBDLY_8821C(x) \ + (((x) & BIT_MASK_LBDLY_8821C) << BIT_SHIFT_LBDLY_8821C) +#define BITS_LBDLY_8821C (BIT_MASK_LBDLY_8821C << BIT_SHIFT_LBDLY_8821C) +#define BIT_CLEAR_LBDLY_8821C(x) ((x) & (~BITS_LBDLY_8821C)) +#define BIT_GET_LBDLY_8821C(x) \ + (((x) >> BIT_SHIFT_LBDLY_8821C) & BIT_MASK_LBDLY_8821C) +#define BIT_SET_LBDLY_8821C(x, v) \ + (BIT_CLEAR_LBDLY_8821C(x) | BIT_LBDLY_8821C(v)) /* 2 REG_WMAC_BACAM_RPMEN_8821C */ #define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C 2 #define BIT_MASK_BITMAP_SSNBK_COUNTER_8821C 0x3f -#define BIT_BITMAP_SSNBK_COUNTER_8821C(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) -#define BIT_GET_BITMAP_SSNBK_COUNTER_8821C(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) - +#define BIT_BITMAP_SSNBK_COUNTER_8821C(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) +#define BITS_BITMAP_SSNBK_COUNTER_8821C \ + (BIT_MASK_BITMAP_SSNBK_COUNTER_8821C \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8821C(x) \ + ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8821C)) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8821C(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) +#define BIT_SET_BITMAP_SSNBK_COUNTER_8821C(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8821C(x) | \ + BIT_BITMAP_SSNBK_COUNTER_8821C(v)) #define BIT_BITMAP_EN_8821C BIT(1) #define BIT_WMAC_BACAM_RPMEN_8821C BIT(0) -/* 2 REG_LBDLY_8821C (LOOPBACK DELAY REGISTER) */ +/* 2 REG_TX_RX_8821C STATUS */ -#define BIT_SHIFT_LBDLY_8821C 0 -#define BIT_MASK_LBDLY_8821C 0x1f -#define BIT_LBDLY_8821C(x) (((x) & BIT_MASK_LBDLY_8821C) << BIT_SHIFT_LBDLY_8821C) -#define BIT_GET_LBDLY_8821C(x) (((x) >> BIT_SHIFT_LBDLY_8821C) & BIT_MASK_LBDLY_8821C) +#define BIT_SHIFT_RXPKT_TYPE_8821C 2 +#define BIT_MASK_RXPKT_TYPE_8821C 0x3f +#define BIT_RXPKT_TYPE_8821C(x) \ + (((x) & BIT_MASK_RXPKT_TYPE_8821C) << BIT_SHIFT_RXPKT_TYPE_8821C) +#define BITS_RXPKT_TYPE_8821C \ + (BIT_MASK_RXPKT_TYPE_8821C << BIT_SHIFT_RXPKT_TYPE_8821C) +#define BIT_CLEAR_RXPKT_TYPE_8821C(x) ((x) & (~BITS_RXPKT_TYPE_8821C)) +#define BIT_GET_RXPKT_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE_8821C) & BIT_MASK_RXPKT_TYPE_8821C) +#define BIT_SET_RXPKT_TYPE_8821C(x, v) \ + (BIT_CLEAR_RXPKT_TYPE_8821C(x) | BIT_RXPKT_TYPE_8821C(v)) + +#define BIT_TXACT_IND_8821C BIT(1) +#define BIT_RXACT_IND_8821C BIT(0) + +/* 2 REG_WMAC_BITMAP_CTL_8821C */ +#define BIT_BITMAP_VO_8821C BIT(7) +#define BIT_BITMAP_VI_8821C BIT(6) +#define BIT_BITMAP_BE_8821C BIT(5) +#define BIT_BITMAP_BK_8821C BIT(4) +#define BIT_SHIFT_BITMAP_CONDITION_8821C 2 +#define BIT_MASK_BITMAP_CONDITION_8821C 0x3 +#define BIT_BITMAP_CONDITION_8821C(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION_8821C) \ + << BIT_SHIFT_BITMAP_CONDITION_8821C) +#define BITS_BITMAP_CONDITION_8821C \ + (BIT_MASK_BITMAP_CONDITION_8821C << BIT_SHIFT_BITMAP_CONDITION_8821C) +#define BIT_CLEAR_BITMAP_CONDITION_8821C(x) \ + ((x) & (~BITS_BITMAP_CONDITION_8821C)) +#define BIT_GET_BITMAP_CONDITION_8821C(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION_8821C) & \ + BIT_MASK_BITMAP_CONDITION_8821C) +#define BIT_SET_BITMAP_CONDITION_8821C(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION_8821C(x) | BIT_BITMAP_CONDITION_8821C(v)) +#define BIT_BITMAP_SSNBK_COUNTER_CLR_8821C BIT(1) +#define BIT_BITMAP_FORCE_8821C BIT(0) /* 2 REG_RXERR_RPT_8821C (RX ERROR REPORT REGISTER) */ #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C 28 #define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C 0xf -#define BIT_RXERR_RPT_SEL_V1_3_0_8821C(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) -#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8821C(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) - +#define BIT_RXERR_RPT_SEL_V1_3_0_8821C(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) +#define BITS_RXERR_RPT_SEL_V1_3_0_8821C \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8821C(x) \ + ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8821C)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8821C(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8821C(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8821C(x) | \ + BIT_RXERR_RPT_SEL_V1_3_0_8821C(v)) #define BIT_RXERR_RPT_RST_8821C BIT(27) #define BIT_RXERR_RPT_SEL_V1_4_8821C BIT(26) @@ -9011,64 +14856,40 @@ #define BIT_SHIFT_UD_SUB_TYPE_8821C 18 #define BIT_MASK_UD_SUB_TYPE_8821C 0xf -#define BIT_UD_SUB_TYPE_8821C(x) (((x) & BIT_MASK_UD_SUB_TYPE_8821C) << BIT_SHIFT_UD_SUB_TYPE_8821C) -#define BIT_GET_UD_SUB_TYPE_8821C(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8821C) & BIT_MASK_UD_SUB_TYPE_8821C) - - +#define BIT_UD_SUB_TYPE_8821C(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE_8821C) << BIT_SHIFT_UD_SUB_TYPE_8821C) +#define BITS_UD_SUB_TYPE_8821C \ + (BIT_MASK_UD_SUB_TYPE_8821C << BIT_SHIFT_UD_SUB_TYPE_8821C) +#define BIT_CLEAR_UD_SUB_TYPE_8821C(x) ((x) & (~BITS_UD_SUB_TYPE_8821C)) +#define BIT_GET_UD_SUB_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE_8821C) & BIT_MASK_UD_SUB_TYPE_8821C) +#define BIT_SET_UD_SUB_TYPE_8821C(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE_8821C(x) | BIT_UD_SUB_TYPE_8821C(v)) #define BIT_SHIFT_UD_TYPE_8821C 16 #define BIT_MASK_UD_TYPE_8821C 0x3 -#define BIT_UD_TYPE_8821C(x) (((x) & BIT_MASK_UD_TYPE_8821C) << BIT_SHIFT_UD_TYPE_8821C) -#define BIT_GET_UD_TYPE_8821C(x) (((x) >> BIT_SHIFT_UD_TYPE_8821C) & BIT_MASK_UD_TYPE_8821C) - - +#define BIT_UD_TYPE_8821C(x) \ + (((x) & BIT_MASK_UD_TYPE_8821C) << BIT_SHIFT_UD_TYPE_8821C) +#define BITS_UD_TYPE_8821C (BIT_MASK_UD_TYPE_8821C << BIT_SHIFT_UD_TYPE_8821C) +#define BIT_CLEAR_UD_TYPE_8821C(x) ((x) & (~BITS_UD_TYPE_8821C)) +#define BIT_GET_UD_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_UD_TYPE_8821C) & BIT_MASK_UD_TYPE_8821C) +#define BIT_SET_UD_TYPE_8821C(x, v) \ + (BIT_CLEAR_UD_TYPE_8821C(x) | BIT_UD_TYPE_8821C(v)) #define BIT_SHIFT_RPT_COUNTER_8821C 0 #define BIT_MASK_RPT_COUNTER_8821C 0xffff -#define BIT_RPT_COUNTER_8821C(x) (((x) & BIT_MASK_RPT_COUNTER_8821C) << BIT_SHIFT_RPT_COUNTER_8821C) -#define BIT_GET_RPT_COUNTER_8821C(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8821C) & BIT_MASK_RPT_COUNTER_8821C) - - - -/* 2 REG_WMAC_TRXPTCL_CTL_8821C (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ - -#define BIT_SHIFT_ACKBA_TYPSEL_8821C (60 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_TYPSEL_8821C 0xf -#define BIT_ACKBA_TYPSEL_8821C(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8821C) << BIT_SHIFT_ACKBA_TYPSEL_8821C) -#define BIT_GET_ACKBA_TYPSEL_8821C(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8821C) & BIT_MASK_ACKBA_TYPSEL_8821C) - - - -#define BIT_SHIFT_ACKBA_ACKPCHK_8821C (56 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBA_ACKPCHK_8821C 0xf -#define BIT_ACKBA_ACKPCHK_8821C(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8821C) << BIT_SHIFT_ACKBA_ACKPCHK_8821C) -#define BIT_GET_ACKBA_ACKPCHK_8821C(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8821C) & BIT_MASK_ACKBA_ACKPCHK_8821C) - - - -#define BIT_SHIFT_ACKBAR_TYPESEL_8821C (48 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_TYPESEL_8821C 0xff -#define BIT_ACKBAR_TYPESEL_8821C(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8821C) << BIT_SHIFT_ACKBAR_TYPESEL_8821C) -#define BIT_GET_ACKBAR_TYPESEL_8821C(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8821C) & BIT_MASK_ACKBAR_TYPESEL_8821C) - - - -#define BIT_SHIFT_ACKBAR_ACKPCHK_8821C (44 & CPU_OPT_WIDTH) -#define BIT_MASK_ACKBAR_ACKPCHK_8821C 0xf -#define BIT_ACKBAR_ACKPCHK_8821C(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8821C) << BIT_SHIFT_ACKBAR_ACKPCHK_8821C) -#define BIT_GET_ACKBAR_ACKPCHK_8821C(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8821C) & BIT_MASK_ACKBAR_ACKPCHK_8821C) - - -#define BIT_RXBA_IGNOREA2_8821C BIT(42) -#define BIT_EN_SAVE_ALL_TXOPADDR_8821C BIT(41) -#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8821C BIT(40) -#define BIT_DIS_TXBA_AMPDUFCSERR_8821C BIT(39) -#define BIT_DIS_TXBA_RXBARINFULL_8821C BIT(38) -#define BIT_DIS_TXCFE_INFULL_8821C BIT(37) -#define BIT_DIS_TXCTS_INFULL_8821C BIT(36) -#define BIT_EN_TXACKBA_IN_TX_RDG_8821C BIT(35) -#define BIT_EN_TXACKBA_IN_TXOP_8821C BIT(34) -#define BIT_EN_TXCTS_IN_RXNAV_8821C BIT(33) +#define BIT_RPT_COUNTER_8821C(x) \ + (((x) & BIT_MASK_RPT_COUNTER_8821C) << BIT_SHIFT_RPT_COUNTER_8821C) +#define BITS_RPT_COUNTER_8821C \ + (BIT_MASK_RPT_COUNTER_8821C << BIT_SHIFT_RPT_COUNTER_8821C) +#define BIT_CLEAR_RPT_COUNTER_8821C(x) ((x) & (~BITS_RPT_COUNTER_8821C)) +#define BIT_GET_RPT_COUNTER_8821C(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER_8821C) & BIT_MASK_RPT_COUNTER_8821C) +#define BIT_SET_RPT_COUNTER_8821C(x, v) \ + (BIT_CLEAR_RPT_COUNTER_8821C(x) | BIT_RPT_COUNTER_8821C(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_8821C (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ #define BIT_EN_TXCTS_INTXOP_8821C BIT(32) #define BIT_BLK_EDCA_BBSLP_8821C BIT(31) #define BIT_BLK_EDCA_BBSBY_8821C BIT(30) @@ -9081,9 +14902,15 @@ #define BIT_SHIFT_RESP_CHNBUSY_8821C 20 #define BIT_MASK_RESP_CHNBUSY_8821C 0x3 -#define BIT_RESP_CHNBUSY_8821C(x) (((x) & BIT_MASK_RESP_CHNBUSY_8821C) << BIT_SHIFT_RESP_CHNBUSY_8821C) -#define BIT_GET_RESP_CHNBUSY_8821C(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8821C) & BIT_MASK_RESP_CHNBUSY_8821C) - +#define BIT_RESP_CHNBUSY_8821C(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY_8821C) << BIT_SHIFT_RESP_CHNBUSY_8821C) +#define BITS_RESP_CHNBUSY_8821C \ + (BIT_MASK_RESP_CHNBUSY_8821C << BIT_SHIFT_RESP_CHNBUSY_8821C) +#define BIT_CLEAR_RESP_CHNBUSY_8821C(x) ((x) & (~BITS_RESP_CHNBUSY_8821C)) +#define BIT_GET_RESP_CHNBUSY_8821C(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY_8821C) & BIT_MASK_RESP_CHNBUSY_8821C) +#define BIT_SET_RESP_CHNBUSY_8821C(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY_8821C(x) | BIT_RESP_CHNBUSY_8821C(v)) #define BIT_RESP_DCTS_EN_8821C BIT(19) #define BIT_RESP_DCFE_EN_8821C BIT(18) @@ -9095,33 +14922,129 @@ #define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C 10 #define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C 0x7 -#define BIT_R_WMAC_SECOND_CCA_TIMER_8821C(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) -#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) - - +#define BIT_R_WMAC_SECOND_CCA_TIMER_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) +#define BITS_R_WMAC_SECOND_CCA_TIMER_8821C \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8821C(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8821C)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8821C(x) | \ + BIT_R_WMAC_SECOND_CCA_TIMER_8821C(v)) #define BIT_SHIFT_RFMOD_8821C 7 #define BIT_MASK_RFMOD_8821C 0x3 -#define BIT_RFMOD_8821C(x) (((x) & BIT_MASK_RFMOD_8821C) << BIT_SHIFT_RFMOD_8821C) -#define BIT_GET_RFMOD_8821C(x) (((x) >> BIT_SHIFT_RFMOD_8821C) & BIT_MASK_RFMOD_8821C) - - +#define BIT_RFMOD_8821C(x) \ + (((x) & BIT_MASK_RFMOD_8821C) << BIT_SHIFT_RFMOD_8821C) +#define BITS_RFMOD_8821C (BIT_MASK_RFMOD_8821C << BIT_SHIFT_RFMOD_8821C) +#define BIT_CLEAR_RFMOD_8821C(x) ((x) & (~BITS_RFMOD_8821C)) +#define BIT_GET_RFMOD_8821C(x) \ + (((x) >> BIT_SHIFT_RFMOD_8821C) & BIT_MASK_RFMOD_8821C) +#define BIT_SET_RFMOD_8821C(x, v) \ + (BIT_CLEAR_RFMOD_8821C(x) | BIT_RFMOD_8821C(v)) #define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C 5 #define BIT_MASK_RESP_CTS_DYNBW_SEL_8821C 0x3 -#define BIT_RESP_CTS_DYNBW_SEL_8821C(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) -#define BIT_GET_RESP_CTS_DYNBW_SEL_8821C(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) - +#define BIT_RESP_CTS_DYNBW_SEL_8821C(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) +#define BITS_RESP_CTS_DYNBW_SEL_8821C \ + (BIT_MASK_RESP_CTS_DYNBW_SEL_8821C \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8821C(x) \ + ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8821C)) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) & \ + BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) +#define BIT_SET_RESP_CTS_DYNBW_SEL_8821C(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8821C(x) | \ + BIT_RESP_CTS_DYNBW_SEL_8821C(v)) #define BIT_DLY_TX_WAIT_RXANTSEL_8821C BIT(4) #define BIT_TXRESP_BY_RXANTSEL_8821C BIT(3) #define BIT_SHIFT_ORIG_DCTS_CHK_8821C 0 #define BIT_MASK_ORIG_DCTS_CHK_8821C 0x3 -#define BIT_ORIG_DCTS_CHK_8821C(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8821C) << BIT_SHIFT_ORIG_DCTS_CHK_8821C) -#define BIT_GET_ORIG_DCTS_CHK_8821C(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8821C) & BIT_MASK_ORIG_DCTS_CHK_8821C) - - +#define BIT_ORIG_DCTS_CHK_8821C(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK_8821C) << BIT_SHIFT_ORIG_DCTS_CHK_8821C) +#define BITS_ORIG_DCTS_CHK_8821C \ + (BIT_MASK_ORIG_DCTS_CHK_8821C << BIT_SHIFT_ORIG_DCTS_CHK_8821C) +#define BIT_CLEAR_ORIG_DCTS_CHK_8821C(x) ((x) & (~BITS_ORIG_DCTS_CHK_8821C)) +#define BIT_GET_ORIG_DCTS_CHK_8821C(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8821C) & BIT_MASK_ORIG_DCTS_CHK_8821C) +#define BIT_SET_ORIG_DCTS_CHK_8821C(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK_8821C(x) | BIT_ORIG_DCTS_CHK_8821C(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_H_8821C */ + +#define BIT_SHIFT_ACKBA_TYPSEL_8821C 28 +#define BIT_MASK_ACKBA_TYPSEL_8821C 0xf +#define BIT_ACKBA_TYPSEL_8821C(x) \ + (((x) & BIT_MASK_ACKBA_TYPSEL_8821C) << BIT_SHIFT_ACKBA_TYPSEL_8821C) +#define BITS_ACKBA_TYPSEL_8821C \ + (BIT_MASK_ACKBA_TYPSEL_8821C << BIT_SHIFT_ACKBA_TYPSEL_8821C) +#define BIT_CLEAR_ACKBA_TYPSEL_8821C(x) ((x) & (~BITS_ACKBA_TYPSEL_8821C)) +#define BIT_GET_ACKBA_TYPSEL_8821C(x) \ + (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8821C) & BIT_MASK_ACKBA_TYPSEL_8821C) +#define BIT_SET_ACKBA_TYPSEL_8821C(x, v) \ + (BIT_CLEAR_ACKBA_TYPSEL_8821C(x) | BIT_ACKBA_TYPSEL_8821C(v)) + +#define BIT_SHIFT_ACKBA_ACKPCHK_8821C 24 +#define BIT_MASK_ACKBA_ACKPCHK_8821C 0xf +#define BIT_ACKBA_ACKPCHK_8821C(x) \ + (((x) & BIT_MASK_ACKBA_ACKPCHK_8821C) << BIT_SHIFT_ACKBA_ACKPCHK_8821C) +#define BITS_ACKBA_ACKPCHK_8821C \ + (BIT_MASK_ACKBA_ACKPCHK_8821C << BIT_SHIFT_ACKBA_ACKPCHK_8821C) +#define BIT_CLEAR_ACKBA_ACKPCHK_8821C(x) ((x) & (~BITS_ACKBA_ACKPCHK_8821C)) +#define BIT_GET_ACKBA_ACKPCHK_8821C(x) \ + (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8821C) & BIT_MASK_ACKBA_ACKPCHK_8821C) +#define BIT_SET_ACKBA_ACKPCHK_8821C(x, v) \ + (BIT_CLEAR_ACKBA_ACKPCHK_8821C(x) | BIT_ACKBA_ACKPCHK_8821C(v)) + +#define BIT_SHIFT_ACKBAR_TYPESEL_8821C 16 +#define BIT_MASK_ACKBAR_TYPESEL_8821C 0xff +#define BIT_ACKBAR_TYPESEL_8821C(x) \ + (((x) & BIT_MASK_ACKBAR_TYPESEL_8821C) \ + << BIT_SHIFT_ACKBAR_TYPESEL_8821C) +#define BITS_ACKBAR_TYPESEL_8821C \ + (BIT_MASK_ACKBAR_TYPESEL_8821C << BIT_SHIFT_ACKBAR_TYPESEL_8821C) +#define BIT_CLEAR_ACKBAR_TYPESEL_8821C(x) ((x) & (~BITS_ACKBAR_TYPESEL_8821C)) +#define BIT_GET_ACKBAR_TYPESEL_8821C(x) \ + (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8821C) & \ + BIT_MASK_ACKBAR_TYPESEL_8821C) +#define BIT_SET_ACKBAR_TYPESEL_8821C(x, v) \ + (BIT_CLEAR_ACKBAR_TYPESEL_8821C(x) | BIT_ACKBAR_TYPESEL_8821C(v)) + +#define BIT_SHIFT_ACKBAR_ACKPCHK_8821C 12 +#define BIT_MASK_ACKBAR_ACKPCHK_8821C 0xf +#define BIT_ACKBAR_ACKPCHK_8821C(x) \ + (((x) & BIT_MASK_ACKBAR_ACKPCHK_8821C) \ + << BIT_SHIFT_ACKBAR_ACKPCHK_8821C) +#define BITS_ACKBAR_ACKPCHK_8821C \ + (BIT_MASK_ACKBAR_ACKPCHK_8821C << BIT_SHIFT_ACKBAR_ACKPCHK_8821C) +#define BIT_CLEAR_ACKBAR_ACKPCHK_8821C(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8821C)) +#define BIT_GET_ACKBAR_ACKPCHK_8821C(x) \ + (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8821C) & \ + BIT_MASK_ACKBAR_ACKPCHK_8821C) +#define BIT_SET_ACKBAR_ACKPCHK_8821C(x, v) \ + (BIT_CLEAR_ACKBAR_ACKPCHK_8821C(x) | BIT_ACKBAR_ACKPCHK_8821C(v)) + +#define BIT_RXBA_IGNOREA2_V1_8821C BIT(10) +#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8821C BIT(9) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8821C BIT(8) +#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8821C BIT(7) +#define BIT_DIS_TXBA_RXBARINFULL_V1_8821C BIT(6) +#define BIT_DIS_TXCFE_INFULL_V1_8821C BIT(5) +#define BIT_DIS_TXCTS_INFULL_V1_8821C BIT(4) +#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8821C BIT(3) +#define BIT_EN_TXACKBA_IN_TXOP_V1_8821C BIT(2) +#define BIT_EN_TXCTS_IN_RXNAV_V1_8821C BIT(1) +#define BIT_EN_TXCTS_INTXOP_V1_8821C BIT(0) /* 2 REG_CAMCMD_8821C (CAM COMMAND REGISTER) */ #define BIT_SECCAM_POLLING_8821C BIT(31) @@ -9131,28 +15054,45 @@ #define BIT_SHIFT_SECCAM_ADDR_V2_8821C 0 #define BIT_MASK_SECCAM_ADDR_V2_8821C 0x3ff -#define BIT_SECCAM_ADDR_V2_8821C(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8821C) << BIT_SHIFT_SECCAM_ADDR_V2_8821C) -#define BIT_GET_SECCAM_ADDR_V2_8821C(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8821C) & BIT_MASK_SECCAM_ADDR_V2_8821C) - - +#define BIT_SECCAM_ADDR_V2_8821C(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2_8821C) \ + << BIT_SHIFT_SECCAM_ADDR_V2_8821C) +#define BITS_SECCAM_ADDR_V2_8821C \ + (BIT_MASK_SECCAM_ADDR_V2_8821C << BIT_SHIFT_SECCAM_ADDR_V2_8821C) +#define BIT_CLEAR_SECCAM_ADDR_V2_8821C(x) ((x) & (~BITS_SECCAM_ADDR_V2_8821C)) +#define BIT_GET_SECCAM_ADDR_V2_8821C(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8821C) & \ + BIT_MASK_SECCAM_ADDR_V2_8821C) +#define BIT_SET_SECCAM_ADDR_V2_8821C(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2_8821C(x) | BIT_SECCAM_ADDR_V2_8821C(v)) /* 2 REG_CAMWRITE_8821C (CAM WRITE REGISTER) */ #define BIT_SHIFT_CAMW_DATA_8821C 0 #define BIT_MASK_CAMW_DATA_8821C 0xffffffffL -#define BIT_CAMW_DATA_8821C(x) (((x) & BIT_MASK_CAMW_DATA_8821C) << BIT_SHIFT_CAMW_DATA_8821C) -#define BIT_GET_CAMW_DATA_8821C(x) (((x) >> BIT_SHIFT_CAMW_DATA_8821C) & BIT_MASK_CAMW_DATA_8821C) - - +#define BIT_CAMW_DATA_8821C(x) \ + (((x) & BIT_MASK_CAMW_DATA_8821C) << BIT_SHIFT_CAMW_DATA_8821C) +#define BITS_CAMW_DATA_8821C \ + (BIT_MASK_CAMW_DATA_8821C << BIT_SHIFT_CAMW_DATA_8821C) +#define BIT_CLEAR_CAMW_DATA_8821C(x) ((x) & (~BITS_CAMW_DATA_8821C)) +#define BIT_GET_CAMW_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_CAMW_DATA_8821C) & BIT_MASK_CAMW_DATA_8821C) +#define BIT_SET_CAMW_DATA_8821C(x, v) \ + (BIT_CLEAR_CAMW_DATA_8821C(x) | BIT_CAMW_DATA_8821C(v)) /* 2 REG_CAMREAD_8821C (CAM READ REGISTER) */ #define BIT_SHIFT_CAMR_DATA_8821C 0 #define BIT_MASK_CAMR_DATA_8821C 0xffffffffL -#define BIT_CAMR_DATA_8821C(x) (((x) & BIT_MASK_CAMR_DATA_8821C) << BIT_SHIFT_CAMR_DATA_8821C) -#define BIT_GET_CAMR_DATA_8821C(x) (((x) >> BIT_SHIFT_CAMR_DATA_8821C) & BIT_MASK_CAMR_DATA_8821C) - - +#define BIT_CAMR_DATA_8821C(x) \ + (((x) & BIT_MASK_CAMR_DATA_8821C) << BIT_SHIFT_CAMR_DATA_8821C) +#define BITS_CAMR_DATA_8821C \ + (BIT_MASK_CAMR_DATA_8821C << BIT_SHIFT_CAMR_DATA_8821C) +#define BIT_CLEAR_CAMR_DATA_8821C(x) ((x) & (~BITS_CAMR_DATA_8821C)) +#define BIT_GET_CAMR_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_CAMR_DATA_8821C) & BIT_MASK_CAMR_DATA_8821C) +#define BIT_SET_CAMR_DATA_8821C(x, v) \ + (BIT_CLEAR_CAMR_DATA_8821C(x) | BIT_CAMR_DATA_8821C(v)) /* 2 REG_CAMDBG_8821C (CAM DEBUG REGISTER) */ #define BIT_SECCAM_INFO_8821C BIT(31) @@ -9160,43 +15100,53 @@ #define BIT_SHIFT_CAMDBG_SEC_TYPE_8821C 12 #define BIT_MASK_CAMDBG_SEC_TYPE_8821C 0x7 -#define BIT_CAMDBG_SEC_TYPE_8821C(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) -#define BIT_GET_CAMDBG_SEC_TYPE_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) - +#define BIT_CAMDBG_SEC_TYPE_8821C(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) \ + << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) +#define BITS_CAMDBG_SEC_TYPE_8821C \ + (BIT_MASK_CAMDBG_SEC_TYPE_8821C << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) +#define BIT_CLEAR_CAMDBG_SEC_TYPE_8821C(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8821C)) +#define BIT_GET_CAMDBG_SEC_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) & \ + BIT_MASK_CAMDBG_SEC_TYPE_8821C) +#define BIT_SET_CAMDBG_SEC_TYPE_8821C(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_8821C(x) | BIT_CAMDBG_SEC_TYPE_8821C(v)) #define BIT_CAMDBG_EXT_SECTYPE_8821C BIT(11) #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C 5 #define BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C 0x1f -#define BIT_CAMDBG_MIC_KEY_IDX_8821C(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) -#define BIT_GET_CAMDBG_MIC_KEY_IDX_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) - - +#define BIT_CAMDBG_MIC_KEY_IDX_8821C(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) +#define BITS_CAMDBG_MIC_KEY_IDX_8821C \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8821C(x) \ + ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8821C)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_8821C(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8821C(x) | \ + BIT_CAMDBG_MIC_KEY_IDX_8821C(v)) #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C 0x1f -#define BIT_CAMDBG_SEC_KEY_IDX_8821C(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) -#define BIT_GET_CAMDBG_SEC_KEY_IDX_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) - - - -/* 2 REG_RXFILTER_ACTION_1_8821C */ - -#define BIT_SHIFT_RXFILTER_ACTION_1_8821C 0 -#define BIT_MASK_RXFILTER_ACTION_1_8821C 0xff -#define BIT_RXFILTER_ACTION_1_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8821C) << BIT_SHIFT_RXFILTER_ACTION_1_8821C) -#define BIT_GET_RXFILTER_ACTION_1_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8821C) & BIT_MASK_RXFILTER_ACTION_1_8821C) - - - -/* 2 REG_RXFILTER_CATEGORY_1_8821C */ - -#define BIT_SHIFT_RXFILTER_CATEGORY_1_8821C 0 -#define BIT_MASK_RXFILTER_CATEGORY_1_8821C 0xff -#define BIT_RXFILTER_CATEGORY_1_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) -#define BIT_GET_RXFILTER_CATEGORY_1_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) & BIT_MASK_RXFILTER_CATEGORY_1_8821C) - - +#define BIT_CAMDBG_SEC_KEY_IDX_8821C(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) +#define BITS_CAMDBG_SEC_KEY_IDX_8821C \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8821C(x) \ + ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8821C)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_8821C(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8821C(x) | \ + BIT_CAMDBG_SEC_KEY_IDX_8821C(v)) /* 2 REG_SECCFG_8821C (SECURITY CONFIGURATION REGISTER) */ #define BIT_DIS_GCLK_WAPI_8821C BIT(15) @@ -9215,41 +15165,131 @@ #define BIT_RXUHUSEDK_8821C BIT(1) #define BIT_TXUHUSEDK_8821C BIT(0) -/* 2 REG_RXFILTER_ACTION_3_8821C */ - -#define BIT_SHIFT_RXFILTER_ACTION_3_8821C 0 -#define BIT_MASK_RXFILTER_ACTION_3_8821C 0xff -#define BIT_RXFILTER_ACTION_3_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8821C) << BIT_SHIFT_RXFILTER_ACTION_3_8821C) -#define BIT_GET_RXFILTER_ACTION_3_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8821C) & BIT_MASK_RXFILTER_ACTION_3_8821C) - +/* 2 REG_RXFILTER_CATEGORY_1_8821C */ +#define BIT_SHIFT_RXFILTER_CATEGORY_1_8821C 0 +#define BIT_MASK_RXFILTER_CATEGORY_1_8821C 0xff +#define BIT_RXFILTER_CATEGORY_1_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8821C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) +#define BITS_RXFILTER_CATEGORY_1_8821C \ + (BIT_MASK_RXFILTER_CATEGORY_1_8821C \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) +#define BIT_CLEAR_RXFILTER_CATEGORY_1_8821C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_1_8821C)) +#define BIT_GET_RXFILTER_CATEGORY_1_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) & \ + BIT_MASK_RXFILTER_CATEGORY_1_8821C) +#define BIT_SET_RXFILTER_CATEGORY_1_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1_8821C(x) | \ + BIT_RXFILTER_CATEGORY_1_8821C(v)) -/* 2 REG_RXFILTER_CATEGORY_3_8821C */ +/* 2 REG_RXFILTER_ACTION_1_8821C */ -#define BIT_SHIFT_RXFILTER_CATEGORY_3_8821C 0 -#define BIT_MASK_RXFILTER_CATEGORY_3_8821C 0xff -#define BIT_RXFILTER_CATEGORY_3_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) -#define BIT_GET_RXFILTER_CATEGORY_3_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) & BIT_MASK_RXFILTER_CATEGORY_3_8821C) +#define BIT_SHIFT_RXFILTER_ACTION_1_8821C 0 +#define BIT_MASK_RXFILTER_ACTION_1_8821C 0xff +#define BIT_RXFILTER_ACTION_1_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1_8821C) \ + << BIT_SHIFT_RXFILTER_ACTION_1_8821C) +#define BITS_RXFILTER_ACTION_1_8821C \ + (BIT_MASK_RXFILTER_ACTION_1_8821C << BIT_SHIFT_RXFILTER_ACTION_1_8821C) +#define BIT_CLEAR_RXFILTER_ACTION_1_8821C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_1_8821C)) +#define BIT_GET_RXFILTER_ACTION_1_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8821C) & \ + BIT_MASK_RXFILTER_ACTION_1_8821C) +#define BIT_SET_RXFILTER_ACTION_1_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1_8821C(x) | BIT_RXFILTER_ACTION_1_8821C(v)) +/* 2 REG_RXFILTER_CATEGORY_2_8821C */ +#define BIT_SHIFT_RXFILTER_CATEGORY_2_8821C 0 +#define BIT_MASK_RXFILTER_CATEGORY_2_8821C 0xff +#define BIT_RXFILTER_CATEGORY_2_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8821C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) +#define BITS_RXFILTER_CATEGORY_2_8821C \ + (BIT_MASK_RXFILTER_CATEGORY_2_8821C \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) +#define BIT_CLEAR_RXFILTER_CATEGORY_2_8821C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_2_8821C)) +#define BIT_GET_RXFILTER_CATEGORY_2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) & \ + BIT_MASK_RXFILTER_CATEGORY_2_8821C) +#define BIT_SET_RXFILTER_CATEGORY_2_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2_8821C(x) | \ + BIT_RXFILTER_CATEGORY_2_8821C(v)) /* 2 REG_RXFILTER_ACTION_2_8821C */ #define BIT_SHIFT_RXFILTER_ACTION_2_8821C 0 #define BIT_MASK_RXFILTER_ACTION_2_8821C 0xff -#define BIT_RXFILTER_ACTION_2_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8821C) << BIT_SHIFT_RXFILTER_ACTION_2_8821C) -#define BIT_GET_RXFILTER_ACTION_2_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8821C) & BIT_MASK_RXFILTER_ACTION_2_8821C) - +#define BIT_RXFILTER_ACTION_2_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2_8821C) \ + << BIT_SHIFT_RXFILTER_ACTION_2_8821C) +#define BITS_RXFILTER_ACTION_2_8821C \ + (BIT_MASK_RXFILTER_ACTION_2_8821C << BIT_SHIFT_RXFILTER_ACTION_2_8821C) +#define BIT_CLEAR_RXFILTER_ACTION_2_8821C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_2_8821C)) +#define BIT_GET_RXFILTER_ACTION_2_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8821C) & \ + BIT_MASK_RXFILTER_ACTION_2_8821C) +#define BIT_SET_RXFILTER_ACTION_2_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2_8821C(x) | BIT_RXFILTER_ACTION_2_8821C(v)) +/* 2 REG_RXFILTER_CATEGORY_3_8821C */ -/* 2 REG_RXFILTER_CATEGORY_2_8821C */ +#define BIT_SHIFT_RXFILTER_CATEGORY_3_8821C 0 +#define BIT_MASK_RXFILTER_CATEGORY_3_8821C 0xff +#define BIT_RXFILTER_CATEGORY_3_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8821C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) +#define BITS_RXFILTER_CATEGORY_3_8821C \ + (BIT_MASK_RXFILTER_CATEGORY_3_8821C \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) +#define BIT_CLEAR_RXFILTER_CATEGORY_3_8821C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_3_8821C)) +#define BIT_GET_RXFILTER_CATEGORY_3_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) & \ + BIT_MASK_RXFILTER_CATEGORY_3_8821C) +#define BIT_SET_RXFILTER_CATEGORY_3_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3_8821C(x) | \ + BIT_RXFILTER_CATEGORY_3_8821C(v)) -#define BIT_SHIFT_RXFILTER_CATEGORY_2_8821C 0 -#define BIT_MASK_RXFILTER_CATEGORY_2_8821C 0xff -#define BIT_RXFILTER_CATEGORY_2_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) -#define BIT_GET_RXFILTER_CATEGORY_2_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) & BIT_MASK_RXFILTER_CATEGORY_2_8821C) +/* 2 REG_RXFILTER_ACTION_3_8821C */ +#define BIT_SHIFT_RXFILTER_ACTION_3_8821C 0 +#define BIT_MASK_RXFILTER_ACTION_3_8821C 0xff +#define BIT_RXFILTER_ACTION_3_8821C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3_8821C) \ + << BIT_SHIFT_RXFILTER_ACTION_3_8821C) +#define BITS_RXFILTER_ACTION_3_8821C \ + (BIT_MASK_RXFILTER_ACTION_3_8821C << BIT_SHIFT_RXFILTER_ACTION_3_8821C) +#define BIT_CLEAR_RXFILTER_ACTION_3_8821C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_3_8821C)) +#define BIT_GET_RXFILTER_ACTION_3_8821C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8821C) & \ + BIT_MASK_RXFILTER_ACTION_3_8821C) +#define BIT_SET_RXFILTER_ACTION_3_8821C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3_8821C(x) | BIT_RXFILTER_ACTION_3_8821C(v)) +/* 2 REG_RXFLTMAP3_8821C (RX FILTER MAP GROUP 3) */ +#define BIT_MGTFLT15EN_FW_8821C BIT(15) +#define BIT_MGTFLT14EN_FW_8821C BIT(14) +#define BIT_MGTFLT13EN_FW_8821C BIT(13) +#define BIT_MGTFLT12EN_FW_8821C BIT(12) +#define BIT_MGTFLT11EN_FW_8821C BIT(11) +#define BIT_MGTFLT10EN_FW_8821C BIT(10) +#define BIT_MGTFLT9EN_FW_8821C BIT(9) +#define BIT_MGTFLT8EN_FW_8821C BIT(8) +#define BIT_MGTFLT7EN_FW_8821C BIT(7) +#define BIT_MGTFLT6EN_FW_8821C BIT(6) +#define BIT_MGTFLT5EN_FW_8821C BIT(5) +#define BIT_MGTFLT4EN_FW_8821C BIT(4) +#define BIT_MGTFLT3EN_FW_8821C BIT(3) +#define BIT_MGTFLT2EN_FW_8821C BIT(2) +#define BIT_MGTFLT1EN_FW_8821C BIT(1) +#define BIT_MGTFLT0EN_FW_8821C BIT(0) /* 2 REG_RXFLTMAP4_8821C (RX FILTER MAP GROUP 4) */ #define BIT_CTRLFLT15EN_FW_8821C BIT(15) @@ -9269,25 +15309,25 @@ #define BIT_CTRLFLT1EN_FW_8821C BIT(1) #define BIT_CTRLFLT0EN_FW_8821C BIT(0) -/* 2 REG_RXFLTMAP3_8821C (RX FILTER MAP GROUP 3) */ -#define BIT_MGTFLT15EN_FW_8821C BIT(15) -#define BIT_MGTFLT14EN_FW_8821C BIT(14) -#define BIT_MGTFLT13EN_FW_8821C BIT(13) -#define BIT_MGTFLT12EN_FW_8821C BIT(12) -#define BIT_MGTFLT11EN_FW_8821C BIT(11) -#define BIT_MGTFLT10EN_FW_8821C BIT(10) -#define BIT_MGTFLT9EN_FW_8821C BIT(9) -#define BIT_MGTFLT8EN_FW_8821C BIT(8) -#define BIT_MGTFLT7EN_FW_8821C BIT(7) -#define BIT_MGTFLT6EN_FW_8821C BIT(6) -#define BIT_MGTFLT5EN_FW_8821C BIT(5) -#define BIT_MGTFLT4EN_FW_8821C BIT(4) -#define BIT_MGTFLT3EN_FW_8821C BIT(3) -#define BIT_MGTFLT2EN_FW_8821C BIT(2) -#define BIT_MGTFLT1EN_FW_8821C BIT(1) -#define BIT_MGTFLT0EN_FW_8821C BIT(0) +/* 2 REG_RXFLTMAP5_8821C (RX FILTER MAP GROUP 5) */ +#define BIT_DATAFLT15EN_FW_8821C BIT(15) +#define BIT_DATAFLT14EN_FW_8821C BIT(14) +#define BIT_DATAFLT13EN_FW_8821C BIT(13) +#define BIT_DATAFLT12EN_FW_8821C BIT(12) +#define BIT_DATAFLT11EN_FW_8821C BIT(11) +#define BIT_DATAFLT10EN_FW_8821C BIT(10) +#define BIT_DATAFLT9EN_FW_8821C BIT(9) +#define BIT_DATAFLT8EN_FW_8821C BIT(8) +#define BIT_DATAFLT7EN_FW_8821C BIT(7) +#define BIT_DATAFLT6EN_FW_8821C BIT(6) +#define BIT_DATAFLT5EN_FW_8821C BIT(5) +#define BIT_DATAFLT4EN_FW_8821C BIT(4) +#define BIT_DATAFLT3EN_FW_8821C BIT(3) +#define BIT_DATAFLT2EN_FW_8821C BIT(2) +#define BIT_DATAFLT1EN_FW_8821C BIT(1) +#define BIT_DATAFLT0EN_FW_8821C BIT(0) -/* 2 REG_RXFLTMAP6_8821C (RX FILTER MAP GROUP 3) */ +/* 2 REG_RXFLTMAP6_8821C (RX FILTER MAP GROUP 6) */ #define BIT_ACTIONFLT15EN_FW_8821C BIT(15) #define BIT_ACTIONFLT14EN_FW_8821C BIT(14) #define BIT_ACTIONFLT13EN_FW_8821C BIT(13) @@ -9305,41 +15345,53 @@ #define BIT_ACTIONFLT1EN_FW_8821C BIT(1) #define BIT_ACTIONFLT0EN_FW_8821C BIT(0) -/* 2 REG_RXFLTMAP5_8821C (RX FILTER MAP GROUP 3) */ -#define BIT_DATAFLT15EN_FW_8821C BIT(15) -#define BIT_DATAFLT14EN_FW_8821C BIT(14) -#define BIT_DATAFLT13EN_FW_8821C BIT(13) -#define BIT_DATAFLT12EN_FW_8821C BIT(12) -#define BIT_DATAFLT11EN_FW_8821C BIT(11) -#define BIT_DATAFLT10EN_FW_8821C BIT(10) -#define BIT_DATAFLT9EN_FW_8821C BIT(9) -#define BIT_DATAFLT8EN_FW_8821C BIT(8) -#define BIT_DATAFLT7EN_FW_8821C BIT(7) -#define BIT_DATAFLT6EN_FW_8821C BIT(6) -#define BIT_DATAFLT5EN_FW_8821C BIT(5) -#define BIT_DATAFLT4EN_FW_8821C BIT(4) -#define BIT_DATAFLT3EN_FW_8821C BIT(3) -#define BIT_DATAFLT2EN_FW_8821C BIT(2) -#define BIT_DATAFLT1EN_FW_8821C BIT(1) -#define BIT_DATAFLT0EN_FW_8821C BIT(0) +/* 2 REG_WOW_CTRL_8821C (WAKE ON WLAN CONTROL REGISTER) */ -/* 2 REG_WMMPS_UAPSD_TID_8821C (WMM POWER SAVE UAPSD TID REGISTER) */ -#define BIT_WMMPS_UAPSD_TID7_8821C BIT(7) -#define BIT_WMMPS_UAPSD_TID6_8821C BIT(6) -#define BIT_WMMPS_UAPSD_TID5_8821C BIT(5) -#define BIT_WMMPS_UAPSD_TID4_8821C BIT(4) -#define BIT_WMMPS_UAPSD_TID3_8821C BIT(3) -#define BIT_WMMPS_UAPSD_TID2_8821C BIT(2) -#define BIT_WMMPS_UAPSD_TID1_8821C BIT(1) -#define BIT_WMMPS_UAPSD_TID0_8821C BIT(0) +#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C 6 +#define BIT_MASK_PSF_BSSIDSEL_B2B1_8821C 0x3 +#define BIT_PSF_BSSIDSEL_B2B1_8821C(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) \ + << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) +#define BITS_PSF_BSSIDSEL_B2B1_8821C \ + (BIT_MASK_PSF_BSSIDSEL_B2B1_8821C << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8821C(x) \ + ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8821C)) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8821C(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) & \ + BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) +#define BIT_SET_PSF_BSSIDSEL_B2B1_8821C(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8821C(x) | BIT_PSF_BSSIDSEL_B2B1_8821C(v)) + +#define BIT_WOWHCI_8821C BIT(5) +#define BIT_PSF_BSSIDSEL_B0_8821C BIT(4) +#define BIT_UWF_8821C BIT(3) +#define BIT_MAGIC_8821C BIT(2) +#define BIT_WOWEN_8821C BIT(1) +#define BIT_FORCE_WAKEUP_8821C BIT(0) + +/* 2 REG_NAN_RX_TSF_FILTER_8821C(NAN_RX_TSF_ADDRESS_FILTER) */ +#define BIT_CHK_TSF_TA_8821C BIT(2) +#define BIT_CHK_TSF_CBSSID_8821C BIT(1) +#define BIT_CHK_TSF_EN_8821C BIT(0) /* 2 REG_PS_RX_INFO_8821C (POWER SAVE RX INFORMATION REGISTER) */ #define BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C 5 #define BIT_MASK_PORTSEL__PS_RX_INFO_8821C 0x7 -#define BIT_PORTSEL__PS_RX_INFO_8821C(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) -#define BIT_GET_PORTSEL__PS_RX_INFO_8821C(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) - +#define BIT_PORTSEL__PS_RX_INFO_8821C(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) +#define BITS_PORTSEL__PS_RX_INFO_8821C \ + (BIT_MASK_PORTSEL__PS_RX_INFO_8821C \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8821C(x) \ + ((x) & (~BITS_PORTSEL__PS_RX_INFO_8821C)) +#define BIT_GET_PORTSEL__PS_RX_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) & \ + BIT_MASK_PORTSEL__PS_RX_INFO_8821C) +#define BIT_SET_PORTSEL__PS_RX_INFO_8821C(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO_8821C(x) | \ + BIT_PORTSEL__PS_RX_INFO_8821C(v)) #define BIT_RXCTRLIN0_8821C BIT(4) #define BIT_RXMGTIN0_8821C BIT(3) @@ -9347,42 +15399,42 @@ #define BIT_RXDATAIN1_8821C BIT(1) #define BIT_RXDATAIN0_8821C BIT(0) -/* 2 REG_NAN_RX_TSF_FILTER_8821C(NAN_RX_TSF_ADDRESS_FILTER) */ -#define BIT_CHK_TSF_TA_8821C BIT(2) -#define BIT_CHK_TSF_CBSSID_8821C BIT(1) -#define BIT_CHK_TSF_EN_8821C BIT(0) - -/* 2 REG_WOW_CTRL_8821C (WAKE ON WLAN CONTROL REGISTER) */ - -#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C 6 -#define BIT_MASK_PSF_BSSIDSEL_B2B1_8821C 0x3 -#define BIT_PSF_BSSIDSEL_B2B1_8821C(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) -#define BIT_GET_PSF_BSSIDSEL_B2B1_8821C(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) - - -#define BIT_WOWHCI_8821C BIT(5) -#define BIT_PSF_BSSIDSEL_B0_8821C BIT(4) -#define BIT_UWF_8821C BIT(3) -#define BIT_MAGIC_8821C BIT(2) -#define BIT_WOWEN_8821C BIT(1) -#define BIT_FORCE_WAKEUP_8821C BIT(0) +/* 2 REG_WMMPS_UAPSD_TID_8821C (WMM POWER SAVE UAPSD TID REGISTER) */ +#define BIT_WMMPS_UAPSD_TID7_8821C BIT(7) +#define BIT_WMMPS_UAPSD_TID6_8821C BIT(6) +#define BIT_WMMPS_UAPSD_TID5_8821C BIT(5) +#define BIT_WMMPS_UAPSD_TID4_8821C BIT(4) +#define BIT_WMMPS_UAPSD_TID3_8821C BIT(3) +#define BIT_WMMPS_UAPSD_TID2_8821C BIT(2) +#define BIT_WMMPS_UAPSD_TID1_8821C BIT(1) +#define BIT_WMMPS_UAPSD_TID0_8821C BIT(0) /* 2 REG_LPNAV_CTRL_8821C (LOW POWER NAV CONTROL REGISTER) */ #define BIT_LPNAV_EN_8821C BIT(31) #define BIT_SHIFT_LPNAV_EARLY_8821C 16 #define BIT_MASK_LPNAV_EARLY_8821C 0x7fff -#define BIT_LPNAV_EARLY_8821C(x) (((x) & BIT_MASK_LPNAV_EARLY_8821C) << BIT_SHIFT_LPNAV_EARLY_8821C) -#define BIT_GET_LPNAV_EARLY_8821C(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8821C) & BIT_MASK_LPNAV_EARLY_8821C) - - +#define BIT_LPNAV_EARLY_8821C(x) \ + (((x) & BIT_MASK_LPNAV_EARLY_8821C) << BIT_SHIFT_LPNAV_EARLY_8821C) +#define BITS_LPNAV_EARLY_8821C \ + (BIT_MASK_LPNAV_EARLY_8821C << BIT_SHIFT_LPNAV_EARLY_8821C) +#define BIT_CLEAR_LPNAV_EARLY_8821C(x) ((x) & (~BITS_LPNAV_EARLY_8821C)) +#define BIT_GET_LPNAV_EARLY_8821C(x) \ + (((x) >> BIT_SHIFT_LPNAV_EARLY_8821C) & BIT_MASK_LPNAV_EARLY_8821C) +#define BIT_SET_LPNAV_EARLY_8821C(x, v) \ + (BIT_CLEAR_LPNAV_EARLY_8821C(x) | BIT_LPNAV_EARLY_8821C(v)) #define BIT_SHIFT_LPNAV_TH_8821C 0 #define BIT_MASK_LPNAV_TH_8821C 0xffff -#define BIT_LPNAV_TH_8821C(x) (((x) & BIT_MASK_LPNAV_TH_8821C) << BIT_SHIFT_LPNAV_TH_8821C) -#define BIT_GET_LPNAV_TH_8821C(x) (((x) >> BIT_SHIFT_LPNAV_TH_8821C) & BIT_MASK_LPNAV_TH_8821C) - - +#define BIT_LPNAV_TH_8821C(x) \ + (((x) & BIT_MASK_LPNAV_TH_8821C) << BIT_SHIFT_LPNAV_TH_8821C) +#define BITS_LPNAV_TH_8821C \ + (BIT_MASK_LPNAV_TH_8821C << BIT_SHIFT_LPNAV_TH_8821C) +#define BIT_CLEAR_LPNAV_TH_8821C(x) ((x) & (~BITS_LPNAV_TH_8821C)) +#define BIT_GET_LPNAV_TH_8821C(x) \ + (((x) >> BIT_SHIFT_LPNAV_TH_8821C) & BIT_MASK_LPNAV_TH_8821C) +#define BIT_SET_LPNAV_TH_8821C(x, v) \ + (BIT_CLEAR_LPNAV_TH_8821C(x) | BIT_LPNAV_TH_8821C(v)) /* 2 REG_WKFMCAM_CMD_8821C (WAKEUP FRAME CAM COMMAND REGISTER) */ #define BIT_WKFCAM_POLLING_V1_8821C BIT(31) @@ -9391,44 +15443,46 @@ #define BIT_SHIFT_WKFCAM_ADDR_V2_8821C 8 #define BIT_MASK_WKFCAM_ADDR_V2_8821C 0xff -#define BIT_WKFCAM_ADDR_V2_8821C(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8821C) << BIT_SHIFT_WKFCAM_ADDR_V2_8821C) -#define BIT_GET_WKFCAM_ADDR_V2_8821C(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8821C) & BIT_MASK_WKFCAM_ADDR_V2_8821C) - - +#define BIT_WKFCAM_ADDR_V2_8821C(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2_8821C) \ + << BIT_SHIFT_WKFCAM_ADDR_V2_8821C) +#define BITS_WKFCAM_ADDR_V2_8821C \ + (BIT_MASK_WKFCAM_ADDR_V2_8821C << BIT_SHIFT_WKFCAM_ADDR_V2_8821C) +#define BIT_CLEAR_WKFCAM_ADDR_V2_8821C(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8821C)) +#define BIT_GET_WKFCAM_ADDR_V2_8821C(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8821C) & \ + BIT_MASK_WKFCAM_ADDR_V2_8821C) +#define BIT_SET_WKFCAM_ADDR_V2_8821C(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2_8821C(x) | BIT_WKFCAM_ADDR_V2_8821C(v)) #define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C 0 #define BIT_MASK_WKFCAM_CAM_NUM_V1_8821C 0xff -#define BIT_WKFCAM_CAM_NUM_V1_8821C(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) -#define BIT_GET_WKFCAM_CAM_NUM_V1_8821C(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) - - - -/* 2 REG_WKFMCAM_RWD_8821C (WAKEUP FRAME READ/WRITE DATA) */ - -#define BIT_SHIFT_WKFMCAM_RWD_8821C 0 -#define BIT_MASK_WKFMCAM_RWD_8821C 0xffffffffL -#define BIT_WKFMCAM_RWD_8821C(x) (((x) & BIT_MASK_WKFMCAM_RWD_8821C) << BIT_SHIFT_WKFMCAM_RWD_8821C) -#define BIT_GET_WKFMCAM_RWD_8821C(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8821C) & BIT_MASK_WKFMCAM_RWD_8821C) - - - -/* 2 REG_RXFLTMAP1_8821C (RX FILTER MAP GROUP 1) */ -#define BIT_CTRLFLT15EN_8821C BIT(15) -#define BIT_CTRLFLT14EN_8821C BIT(14) -#define BIT_CTRLFLT13EN_8821C BIT(13) -#define BIT_CTRLFLT12EN_8821C BIT(12) -#define BIT_CTRLFLT11EN_8821C BIT(11) -#define BIT_CTRLFLT10EN_8821C BIT(10) -#define BIT_CTRLFLT9EN_8821C BIT(9) -#define BIT_CTRLFLT8EN_8821C BIT(8) -#define BIT_CTRLFLT7EN_8821C BIT(7) -#define BIT_CTRLFLT6EN_8821C BIT(6) -#define BIT_CTRLFLT5EN_8821C BIT(5) -#define BIT_CTRLFLT4EN_8821C BIT(4) -#define BIT_CTRLFLT3EN_8821C BIT(3) -#define BIT_CTRLFLT2EN_8821C BIT(2) -#define BIT_CTRLFLT1EN_8821C BIT(1) -#define BIT_CTRLFLT0EN_8821C BIT(0) +#define BIT_WKFCAM_CAM_NUM_V1_8821C(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) \ + << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) +#define BITS_WKFCAM_CAM_NUM_V1_8821C \ + (BIT_MASK_WKFCAM_CAM_NUM_V1_8821C << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8821C(x) \ + ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8821C)) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8821C(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) & \ + BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) +#define BIT_SET_WKFCAM_CAM_NUM_V1_8821C(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8821C(x) | BIT_WKFCAM_CAM_NUM_V1_8821C(v)) + +/* 2 REG_WKFMCAM_RWD_8821C (WAKEUP FRAME READ/WRITE DATA) */ + +#define BIT_SHIFT_WKFMCAM_RWD_8821C 0 +#define BIT_MASK_WKFMCAM_RWD_8821C 0xffffffffL +#define BIT_WKFMCAM_RWD_8821C(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD_8821C) << BIT_SHIFT_WKFMCAM_RWD_8821C) +#define BITS_WKFMCAM_RWD_8821C \ + (BIT_MASK_WKFMCAM_RWD_8821C << BIT_SHIFT_WKFMCAM_RWD_8821C) +#define BIT_CLEAR_WKFMCAM_RWD_8821C(x) ((x) & (~BITS_WKFMCAM_RWD_8821C)) +#define BIT_GET_WKFMCAM_RWD_8821C(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD_8821C) & BIT_MASK_WKFMCAM_RWD_8821C) +#define BIT_SET_WKFMCAM_RWD_8821C(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD_8821C(x) | BIT_WKFMCAM_RWD_8821C(v)) /* 2 REG_RXFLTMAP0_8821C (RX FILTER MAP GROUP 0) */ #define BIT_MGTFLT15EN_8821C BIT(15) @@ -9448,9 +15502,25 @@ #define BIT_MGTFLT1EN_8821C BIT(1) #define BIT_MGTFLT0EN_8821C BIT(0) -/* 2 REG_NOT_VALID_8821C */ +/* 2 REG_RXFLTMAP1_8821C (RX FILTER MAP GROUP 1) */ +#define BIT_CTRLFLT15EN_8821C BIT(15) +#define BIT_CTRLFLT14EN_8821C BIT(14) +#define BIT_CTRLFLT13EN_8821C BIT(13) +#define BIT_CTRLFLT12EN_8821C BIT(12) +#define BIT_CTRLFLT11EN_8821C BIT(11) +#define BIT_CTRLFLT10EN_8821C BIT(10) +#define BIT_CTRLFLT9EN_8821C BIT(9) +#define BIT_CTRLFLT8EN_8821C BIT(8) +#define BIT_CTRLFLT7EN_8821C BIT(7) +#define BIT_CTRLFLT6EN_8821C BIT(6) +#define BIT_CTRLFLT5EN_8821C BIT(5) +#define BIT_CTRLFLT4EN_8821C BIT(4) +#define BIT_CTRLFLT3EN_8821C BIT(3) +#define BIT_CTRLFLT2EN_8821C BIT(2) +#define BIT_CTRLFLT1EN_8821C BIT(1) +#define BIT_CTRLFLT0EN_8821C BIT(0) -/* 2 REG_RXFLTMAP_8821C (RX FILTER MAP GROUP 2) */ +/* 2 REG_RXFLTMAP2_8821C (RX FILTER MAP GROUP 2) */ #define BIT_DATAFLT15EN_8821C BIT(15) #define BIT_DATAFLT14EN_8821C BIT(14) #define BIT_DATAFLT13EN_8821C BIT(13) @@ -9468,93 +15538,146 @@ #define BIT_DATAFLT1EN_8821C BIT(1) #define BIT_DATAFLT0EN_8821C BIT(0) +/* 2 REG_RSVD_8821C */ + /* 2 REG_BCN_PSR_RPT_8821C (BEACON PARSER REPORT REGISTER) */ #define BIT_SHIFT_DTIM_CNT_8821C 24 #define BIT_MASK_DTIM_CNT_8821C 0xff -#define BIT_DTIM_CNT_8821C(x) (((x) & BIT_MASK_DTIM_CNT_8821C) << BIT_SHIFT_DTIM_CNT_8821C) -#define BIT_GET_DTIM_CNT_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT_8821C) & BIT_MASK_DTIM_CNT_8821C) - - +#define BIT_DTIM_CNT_8821C(x) \ + (((x) & BIT_MASK_DTIM_CNT_8821C) << BIT_SHIFT_DTIM_CNT_8821C) +#define BITS_DTIM_CNT_8821C \ + (BIT_MASK_DTIM_CNT_8821C << BIT_SHIFT_DTIM_CNT_8821C) +#define BIT_CLEAR_DTIM_CNT_8821C(x) ((x) & (~BITS_DTIM_CNT_8821C)) +#define BIT_GET_DTIM_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT_8821C) & BIT_MASK_DTIM_CNT_8821C) +#define BIT_SET_DTIM_CNT_8821C(x, v) \ + (BIT_CLEAR_DTIM_CNT_8821C(x) | BIT_DTIM_CNT_8821C(v)) #define BIT_SHIFT_DTIM_PERIOD_8821C 16 #define BIT_MASK_DTIM_PERIOD_8821C 0xff -#define BIT_DTIM_PERIOD_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD_8821C) << BIT_SHIFT_DTIM_PERIOD_8821C) -#define BIT_GET_DTIM_PERIOD_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8821C) & BIT_MASK_DTIM_PERIOD_8821C) - +#define BIT_DTIM_PERIOD_8821C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD_8821C) << BIT_SHIFT_DTIM_PERIOD_8821C) +#define BITS_DTIM_PERIOD_8821C \ + (BIT_MASK_DTIM_PERIOD_8821C << BIT_SHIFT_DTIM_PERIOD_8821C) +#define BIT_CLEAR_DTIM_PERIOD_8821C(x) ((x) & (~BITS_DTIM_PERIOD_8821C)) +#define BIT_GET_DTIM_PERIOD_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD_8821C) & BIT_MASK_DTIM_PERIOD_8821C) +#define BIT_SET_DTIM_PERIOD_8821C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD_8821C(x) | BIT_DTIM_PERIOD_8821C(v)) #define BIT_DTIM_8821C BIT(15) #define BIT_TIM_8821C BIT(14) +#define BIT_RPT_VALID_8821C BIT(13) #define BIT_SHIFT_PS_AID_0_8821C 0 #define BIT_MASK_PS_AID_0_8821C 0x7ff -#define BIT_PS_AID_0_8821C(x) (((x) & BIT_MASK_PS_AID_0_8821C) << BIT_SHIFT_PS_AID_0_8821C) -#define BIT_GET_PS_AID_0_8821C(x) (((x) >> BIT_SHIFT_PS_AID_0_8821C) & BIT_MASK_PS_AID_0_8821C) +#define BIT_PS_AID_0_8821C(x) \ + (((x) & BIT_MASK_PS_AID_0_8821C) << BIT_SHIFT_PS_AID_0_8821C) +#define BITS_PS_AID_0_8821C \ + (BIT_MASK_PS_AID_0_8821C << BIT_SHIFT_PS_AID_0_8821C) +#define BIT_CLEAR_PS_AID_0_8821C(x) ((x) & (~BITS_PS_AID_0_8821C)) +#define BIT_GET_PS_AID_0_8821C(x) \ + (((x) >> BIT_SHIFT_PS_AID_0_8821C) & BIT_MASK_PS_AID_0_8821C) +#define BIT_SET_PS_AID_0_8821C(x, v) \ + (BIT_CLEAR_PS_AID_0_8821C(x) | BIT_PS_AID_0_8821C(v)) +/* 2 REG_FLC_RPC_8821C (FW LPS CONDITION -- RX PKT COUNTER) */ +#define BIT_SHIFT_FLC_RPC_8821C 0 +#define BIT_MASK_FLC_RPC_8821C 0xff +#define BIT_FLC_RPC_8821C(x) \ + (((x) & BIT_MASK_FLC_RPC_8821C) << BIT_SHIFT_FLC_RPC_8821C) +#define BITS_FLC_RPC_8821C (BIT_MASK_FLC_RPC_8821C << BIT_SHIFT_FLC_RPC_8821C) +#define BIT_CLEAR_FLC_RPC_8821C(x) ((x) & (~BITS_FLC_RPC_8821C)) +#define BIT_GET_FLC_RPC_8821C(x) \ + (((x) >> BIT_SHIFT_FLC_RPC_8821C) & BIT_MASK_FLC_RPC_8821C) +#define BIT_SET_FLC_RPC_8821C(x, v) \ + (BIT_CLEAR_FLC_RPC_8821C(x) | BIT_FLC_RPC_8821C(v)) -/* 2 REG_FLC_TRPC_8821C (TIMER OF FLC_RPC) */ -#define BIT_FLC_RPCT_V1_8821C BIT(7) -#define BIT_MODE_8821C BIT(6) - -#define BIT_SHIFT_TRPCD_8821C 0 -#define BIT_MASK_TRPCD_8821C 0x3f -#define BIT_TRPCD_8821C(x) (((x) & BIT_MASK_TRPCD_8821C) << BIT_SHIFT_TRPCD_8821C) -#define BIT_GET_TRPCD_8821C(x) (((x) >> BIT_SHIFT_TRPCD_8821C) & BIT_MASK_TRPCD_8821C) - +/* 2 REG_FLC_RPCT_8821C (FLC_RPC THRESHOLD) */ +#define BIT_SHIFT_FLC_RPCT_8821C 0 +#define BIT_MASK_FLC_RPCT_8821C 0xff +#define BIT_FLC_RPCT_8821C(x) \ + (((x) & BIT_MASK_FLC_RPCT_8821C) << BIT_SHIFT_FLC_RPCT_8821C) +#define BITS_FLC_RPCT_8821C \ + (BIT_MASK_FLC_RPCT_8821C << BIT_SHIFT_FLC_RPCT_8821C) +#define BIT_CLEAR_FLC_RPCT_8821C(x) ((x) & (~BITS_FLC_RPCT_8821C)) +#define BIT_GET_FLC_RPCT_8821C(x) \ + (((x) >> BIT_SHIFT_FLC_RPCT_8821C) & BIT_MASK_FLC_RPCT_8821C) +#define BIT_SET_FLC_RPCT_8821C(x, v) \ + (BIT_CLEAR_FLC_RPCT_8821C(x) | BIT_FLC_RPCT_8821C(v)) /* 2 REG_FLC_PTS_8821C (PKT TYPE SELECTION OF FLC_RPC T) */ #define BIT_CMF_8821C BIT(2) #define BIT_CCF_8821C BIT(1) #define BIT_CDF_8821C BIT(0) -/* 2 REG_FLC_RPCT_8821C (FLC_RPC THRESHOLD) */ - -#define BIT_SHIFT_FLC_RPCT_8821C 0 -#define BIT_MASK_FLC_RPCT_8821C 0xff -#define BIT_FLC_RPCT_8821C(x) (((x) & BIT_MASK_FLC_RPCT_8821C) << BIT_SHIFT_FLC_RPCT_8821C) -#define BIT_GET_FLC_RPCT_8821C(x) (((x) >> BIT_SHIFT_FLC_RPCT_8821C) & BIT_MASK_FLC_RPCT_8821C) - - - -/* 2 REG_FLC_RPC_8821C (FW LPS CONDITION -- RX PKT COUNTER) */ - -#define BIT_SHIFT_FLC_RPC_8821C 0 -#define BIT_MASK_FLC_RPC_8821C 0xff -#define BIT_FLC_RPC_8821C(x) (((x) & BIT_MASK_FLC_RPC_8821C) << BIT_SHIFT_FLC_RPC_8821C) -#define BIT_GET_FLC_RPC_8821C(x) (((x) >> BIT_SHIFT_FLC_RPC_8821C) & BIT_MASK_FLC_RPC_8821C) - +/* 2 REG_FLC_TRPC_8821C (TIMER OF FLC_RPC) */ +#define BIT_FLC_RPCT_V1_8821C BIT(7) +#define BIT_MODE_8821C BIT(6) +#define BIT_SHIFT_TRPCD_8821C 0 +#define BIT_MASK_TRPCD_8821C 0x3f +#define BIT_TRPCD_8821C(x) \ + (((x) & BIT_MASK_TRPCD_8821C) << BIT_SHIFT_TRPCD_8821C) +#define BITS_TRPCD_8821C (BIT_MASK_TRPCD_8821C << BIT_SHIFT_TRPCD_8821C) +#define BIT_CLEAR_TRPCD_8821C(x) ((x) & (~BITS_TRPCD_8821C)) +#define BIT_GET_TRPCD_8821C(x) \ + (((x) >> BIT_SHIFT_TRPCD_8821C) & BIT_MASK_TRPCD_8821C) +#define BIT_SET_TRPCD_8821C(x, v) \ + (BIT_CLEAR_TRPCD_8821C(x) | BIT_TRPCD_8821C(v)) /* 2 REG_RXPKTMON_CTRL_8821C */ #define BIT_SHIFT_RXBKQPKT_SEQ_8821C 20 #define BIT_MASK_RXBKQPKT_SEQ_8821C 0xf -#define BIT_RXBKQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8821C) << BIT_SHIFT_RXBKQPKT_SEQ_8821C) -#define BIT_GET_RXBKQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8821C) & BIT_MASK_RXBKQPKT_SEQ_8821C) - - +#define BIT_RXBKQPKT_SEQ_8821C(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ_8821C) << BIT_SHIFT_RXBKQPKT_SEQ_8821C) +#define BITS_RXBKQPKT_SEQ_8821C \ + (BIT_MASK_RXBKQPKT_SEQ_8821C << BIT_SHIFT_RXBKQPKT_SEQ_8821C) +#define BIT_CLEAR_RXBKQPKT_SEQ_8821C(x) ((x) & (~BITS_RXBKQPKT_SEQ_8821C)) +#define BIT_GET_RXBKQPKT_SEQ_8821C(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8821C) & BIT_MASK_RXBKQPKT_SEQ_8821C) +#define BIT_SET_RXBKQPKT_SEQ_8821C(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ_8821C(x) | BIT_RXBKQPKT_SEQ_8821C(v)) #define BIT_SHIFT_RXBEQPKT_SEQ_8821C 16 #define BIT_MASK_RXBEQPKT_SEQ_8821C 0xf -#define BIT_RXBEQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8821C) << BIT_SHIFT_RXBEQPKT_SEQ_8821C) -#define BIT_GET_RXBEQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8821C) & BIT_MASK_RXBEQPKT_SEQ_8821C) - - +#define BIT_RXBEQPKT_SEQ_8821C(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ_8821C) << BIT_SHIFT_RXBEQPKT_SEQ_8821C) +#define BITS_RXBEQPKT_SEQ_8821C \ + (BIT_MASK_RXBEQPKT_SEQ_8821C << BIT_SHIFT_RXBEQPKT_SEQ_8821C) +#define BIT_CLEAR_RXBEQPKT_SEQ_8821C(x) ((x) & (~BITS_RXBEQPKT_SEQ_8821C)) +#define BIT_GET_RXBEQPKT_SEQ_8821C(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8821C) & BIT_MASK_RXBEQPKT_SEQ_8821C) +#define BIT_SET_RXBEQPKT_SEQ_8821C(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ_8821C(x) | BIT_RXBEQPKT_SEQ_8821C(v)) #define BIT_SHIFT_RXVIQPKT_SEQ_8821C 12 #define BIT_MASK_RXVIQPKT_SEQ_8821C 0xf -#define BIT_RXVIQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8821C) << BIT_SHIFT_RXVIQPKT_SEQ_8821C) -#define BIT_GET_RXVIQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8821C) & BIT_MASK_RXVIQPKT_SEQ_8821C) - - +#define BIT_RXVIQPKT_SEQ_8821C(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ_8821C) << BIT_SHIFT_RXVIQPKT_SEQ_8821C) +#define BITS_RXVIQPKT_SEQ_8821C \ + (BIT_MASK_RXVIQPKT_SEQ_8821C << BIT_SHIFT_RXVIQPKT_SEQ_8821C) +#define BIT_CLEAR_RXVIQPKT_SEQ_8821C(x) ((x) & (~BITS_RXVIQPKT_SEQ_8821C)) +#define BIT_GET_RXVIQPKT_SEQ_8821C(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8821C) & BIT_MASK_RXVIQPKT_SEQ_8821C) +#define BIT_SET_RXVIQPKT_SEQ_8821C(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ_8821C(x) | BIT_RXVIQPKT_SEQ_8821C(v)) #define BIT_SHIFT_RXVOQPKT_SEQ_8821C 8 #define BIT_MASK_RXVOQPKT_SEQ_8821C 0xf -#define BIT_RXVOQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8821C) << BIT_SHIFT_RXVOQPKT_SEQ_8821C) -#define BIT_GET_RXVOQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8821C) & BIT_MASK_RXVOQPKT_SEQ_8821C) - +#define BIT_RXVOQPKT_SEQ_8821C(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ_8821C) << BIT_SHIFT_RXVOQPKT_SEQ_8821C) +#define BITS_RXVOQPKT_SEQ_8821C \ + (BIT_MASK_RXVOQPKT_SEQ_8821C << BIT_SHIFT_RXVOQPKT_SEQ_8821C) +#define BIT_CLEAR_RXVOQPKT_SEQ_8821C(x) ((x) & (~BITS_RXVOQPKT_SEQ_8821C)) +#define BIT_GET_RXVOQPKT_SEQ_8821C(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8821C) & BIT_MASK_RXVOQPKT_SEQ_8821C) +#define BIT_SET_RXVOQPKT_SEQ_8821C(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ_8821C(x) | BIT_RXVOQPKT_SEQ_8821C(v)) #define BIT_RXBKQPKT_ERR_8821C BIT(7) #define BIT_RXBEQPKT_ERR_8821C BIT(6) @@ -9568,25 +15691,41 @@ #define BIT_SHIFT_STATE_SEL_8821C 24 #define BIT_MASK_STATE_SEL_8821C 0x1f -#define BIT_STATE_SEL_8821C(x) (((x) & BIT_MASK_STATE_SEL_8821C) << BIT_SHIFT_STATE_SEL_8821C) -#define BIT_GET_STATE_SEL_8821C(x) (((x) >> BIT_SHIFT_STATE_SEL_8821C) & BIT_MASK_STATE_SEL_8821C) - - +#define BIT_STATE_SEL_8821C(x) \ + (((x) & BIT_MASK_STATE_SEL_8821C) << BIT_SHIFT_STATE_SEL_8821C) +#define BITS_STATE_SEL_8821C \ + (BIT_MASK_STATE_SEL_8821C << BIT_SHIFT_STATE_SEL_8821C) +#define BIT_CLEAR_STATE_SEL_8821C(x) ((x) & (~BITS_STATE_SEL_8821C)) +#define BIT_GET_STATE_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_STATE_SEL_8821C) & BIT_MASK_STATE_SEL_8821C) +#define BIT_SET_STATE_SEL_8821C(x, v) \ + (BIT_CLEAR_STATE_SEL_8821C(x) | BIT_STATE_SEL_8821C(v)) #define BIT_SHIFT_STATE_INFO_8821C 8 #define BIT_MASK_STATE_INFO_8821C 0xff -#define BIT_STATE_INFO_8821C(x) (((x) & BIT_MASK_STATE_INFO_8821C) << BIT_SHIFT_STATE_INFO_8821C) -#define BIT_GET_STATE_INFO_8821C(x) (((x) >> BIT_SHIFT_STATE_INFO_8821C) & BIT_MASK_STATE_INFO_8821C) - +#define BIT_STATE_INFO_8821C(x) \ + (((x) & BIT_MASK_STATE_INFO_8821C) << BIT_SHIFT_STATE_INFO_8821C) +#define BITS_STATE_INFO_8821C \ + (BIT_MASK_STATE_INFO_8821C << BIT_SHIFT_STATE_INFO_8821C) +#define BIT_CLEAR_STATE_INFO_8821C(x) ((x) & (~BITS_STATE_INFO_8821C)) +#define BIT_GET_STATE_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_STATE_INFO_8821C) & BIT_MASK_STATE_INFO_8821C) +#define BIT_SET_STATE_INFO_8821C(x, v) \ + (BIT_CLEAR_STATE_INFO_8821C(x) | BIT_STATE_INFO_8821C(v)) #define BIT_UPD_NXT_STATE_8821C BIT(7) #define BIT_SHIFT_CUR_STATE_8821C 0 #define BIT_MASK_CUR_STATE_8821C 0x7f -#define BIT_CUR_STATE_8821C(x) (((x) & BIT_MASK_CUR_STATE_8821C) << BIT_SHIFT_CUR_STATE_8821C) -#define BIT_GET_CUR_STATE_8821C(x) (((x) >> BIT_SHIFT_CUR_STATE_8821C) & BIT_MASK_CUR_STATE_8821C) - - +#define BIT_CUR_STATE_8821C(x) \ + (((x) & BIT_MASK_CUR_STATE_8821C) << BIT_SHIFT_CUR_STATE_8821C) +#define BITS_CUR_STATE_8821C \ + (BIT_MASK_CUR_STATE_8821C << BIT_SHIFT_CUR_STATE_8821C) +#define BIT_CLEAR_CUR_STATE_8821C(x) ((x) & (~BITS_CUR_STATE_8821C)) +#define BIT_GET_CUR_STATE_8821C(x) \ + (((x) >> BIT_SHIFT_CUR_STATE_8821C) & BIT_MASK_CUR_STATE_8821C) +#define BIT_SET_CUR_STATE_8821C(x, v) \ + (BIT_CLEAR_CUR_STATE_8821C(x) | BIT_CUR_STATE_8821C(v)) /* 2 REG_ERROR_MON_8821C */ #define BIT_MACRX_ERR_1_8821C BIT(17) @@ -9601,9 +15740,18 @@ #define BIT_SHIFT_INFO_INDEX_OFFSET_8821C 16 #define BIT_MASK_INFO_INDEX_OFFSET_8821C 0x1fff -#define BIT_INFO_INDEX_OFFSET_8821C(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8821C) << BIT_SHIFT_INFO_INDEX_OFFSET_8821C) -#define BIT_GET_INFO_INDEX_OFFSET_8821C(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8821C) & BIT_MASK_INFO_INDEX_OFFSET_8821C) - +#define BIT_INFO_INDEX_OFFSET_8821C(x) \ + (((x) & BIT_MASK_INFO_INDEX_OFFSET_8821C) \ + << BIT_SHIFT_INFO_INDEX_OFFSET_8821C) +#define BITS_INFO_INDEX_OFFSET_8821C \ + (BIT_MASK_INFO_INDEX_OFFSET_8821C << BIT_SHIFT_INFO_INDEX_OFFSET_8821C) +#define BIT_CLEAR_INFO_INDEX_OFFSET_8821C(x) \ + ((x) & (~BITS_INFO_INDEX_OFFSET_8821C)) +#define BIT_GET_INFO_INDEX_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8821C) & \ + BIT_MASK_INFO_INDEX_OFFSET_8821C) +#define BIT_SET_INFO_INDEX_OFFSET_8821C(x, v) \ + (BIT_CLEAR_INFO_INDEX_OFFSET_8821C(x) | BIT_INFO_INDEX_OFFSET_8821C(v)) #define BIT_WMAC_SRCH_FIFOFULL_8821C BIT(15) #define BIT_DIS_INFOSRCH_8821C BIT(14) @@ -9611,134 +15759,262 @@ #define BIT_SHIFT_INFO_ADDR_OFFSET_8821C 0 #define BIT_MASK_INFO_ADDR_OFFSET_8821C 0x1fff -#define BIT_INFO_ADDR_OFFSET_8821C(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8821C) << BIT_SHIFT_INFO_ADDR_OFFSET_8821C) -#define BIT_GET_INFO_ADDR_OFFSET_8821C(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8821C) & BIT_MASK_INFO_ADDR_OFFSET_8821C) - - +#define BIT_INFO_ADDR_OFFSET_8821C(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET_8821C) \ + << BIT_SHIFT_INFO_ADDR_OFFSET_8821C) +#define BITS_INFO_ADDR_OFFSET_8821C \ + (BIT_MASK_INFO_ADDR_OFFSET_8821C << BIT_SHIFT_INFO_ADDR_OFFSET_8821C) +#define BIT_CLEAR_INFO_ADDR_OFFSET_8821C(x) \ + ((x) & (~BITS_INFO_ADDR_OFFSET_8821C)) +#define BIT_GET_INFO_ADDR_OFFSET_8821C(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8821C) & \ + BIT_MASK_INFO_ADDR_OFFSET_8821C) +#define BIT_SET_INFO_ADDR_OFFSET_8821C(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET_8821C(x) | BIT_INFO_ADDR_OFFSET_8821C(v)) /* 2 REG_BT_COEX_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */ -#define BIT_PRI_MASK_RX_RESP_8821C BIT(126) -#define BIT_PRI_MASK_RXOFDM_8821C BIT(125) -#define BIT_PRI_MASK_RXCCK_8821C BIT(124) -#define BIT_SHIFT_PRI_MASK_TXAC_8821C (117 & CPU_OPT_WIDTH) +#define BIT_SHIFT_COEX_TABLE_1_8821C 0 +#define BIT_MASK_COEX_TABLE_1_8821C 0xffffffffL +#define BIT_COEX_TABLE_1_8821C(x) \ + (((x) & BIT_MASK_COEX_TABLE_1_8821C) << BIT_SHIFT_COEX_TABLE_1_8821C) +#define BITS_COEX_TABLE_1_8821C \ + (BIT_MASK_COEX_TABLE_1_8821C << BIT_SHIFT_COEX_TABLE_1_8821C) +#define BIT_CLEAR_COEX_TABLE_1_8821C(x) ((x) & (~BITS_COEX_TABLE_1_8821C)) +#define BIT_GET_COEX_TABLE_1_8821C(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1_8821C) & BIT_MASK_COEX_TABLE_1_8821C) +#define BIT_SET_COEX_TABLE_1_8821C(x, v) \ + (BIT_CLEAR_COEX_TABLE_1_8821C(x) | BIT_COEX_TABLE_1_8821C(v)) + +/* 2 REG_BT_COEX_TABLE2_8821C (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_COEX_TABLE_2_8821C 0 +#define BIT_MASK_COEX_TABLE_2_8821C 0xffffffffL +#define BIT_COEX_TABLE_2_8821C(x) \ + (((x) & BIT_MASK_COEX_TABLE_2_8821C) << BIT_SHIFT_COEX_TABLE_2_8821C) +#define BITS_COEX_TABLE_2_8821C \ + (BIT_MASK_COEX_TABLE_2_8821C << BIT_SHIFT_COEX_TABLE_2_8821C) +#define BIT_CLEAR_COEX_TABLE_2_8821C(x) ((x) & (~BITS_COEX_TABLE_2_8821C)) +#define BIT_GET_COEX_TABLE_2_8821C(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_2_8821C) & BIT_MASK_COEX_TABLE_2_8821C) +#define BIT_SET_COEX_TABLE_2_8821C(x, v) \ + (BIT_CLEAR_COEX_TABLE_2_8821C(x) | BIT_COEX_TABLE_2_8821C(v)) + +/* 2 REG_BT_COEX_BREAK_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_BREAK_TABLE_2_8821C 16 +#define BIT_MASK_BREAK_TABLE_2_8821C 0xffff +#define BIT_BREAK_TABLE_2_8821C(x) \ + (((x) & BIT_MASK_BREAK_TABLE_2_8821C) << BIT_SHIFT_BREAK_TABLE_2_8821C) +#define BITS_BREAK_TABLE_2_8821C \ + (BIT_MASK_BREAK_TABLE_2_8821C << BIT_SHIFT_BREAK_TABLE_2_8821C) +#define BIT_CLEAR_BREAK_TABLE_2_8821C(x) ((x) & (~BITS_BREAK_TABLE_2_8821C)) +#define BIT_GET_BREAK_TABLE_2_8821C(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_2_8821C) & BIT_MASK_BREAK_TABLE_2_8821C) +#define BIT_SET_BREAK_TABLE_2_8821C(x, v) \ + (BIT_CLEAR_BREAK_TABLE_2_8821C(x) | BIT_BREAK_TABLE_2_8821C(v)) + +#define BIT_SHIFT_BREAK_TABLE_1_8821C 0 +#define BIT_MASK_BREAK_TABLE_1_8821C 0xffff +#define BIT_BREAK_TABLE_1_8821C(x) \ + (((x) & BIT_MASK_BREAK_TABLE_1_8821C) << BIT_SHIFT_BREAK_TABLE_1_8821C) +#define BITS_BREAK_TABLE_1_8821C \ + (BIT_MASK_BREAK_TABLE_1_8821C << BIT_SHIFT_BREAK_TABLE_1_8821C) +#define BIT_CLEAR_BREAK_TABLE_1_8821C(x) ((x) & (~BITS_BREAK_TABLE_1_8821C)) +#define BIT_GET_BREAK_TABLE_1_8821C(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_1_8821C) & BIT_MASK_BREAK_TABLE_1_8821C) +#define BIT_SET_BREAK_TABLE_1_8821C(x, v) \ + (BIT_CLEAR_BREAK_TABLE_1_8821C(x) | BIT_BREAK_TABLE_1_8821C(v)) + +/* 2 REG_BT_COEX_TABLE_H_8821C (BT-COEXISTENCE CONTROL REGISTER) */ +#define BIT_PRI_MASK_RX_RESP_V1_8821C BIT(30) +#define BIT_PRI_MASK_RXOFDM_V1_8821C BIT(29) +#define BIT_PRI_MASK_RXCCK_V1_8821C BIT(28) + +#define BIT_SHIFT_PRI_MASK_TXAC_8821C 21 #define BIT_MASK_PRI_MASK_TXAC_8821C 0x7f -#define BIT_PRI_MASK_TXAC_8821C(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8821C) << BIT_SHIFT_PRI_MASK_TXAC_8821C) -#define BIT_GET_PRI_MASK_TXAC_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8821C) & BIT_MASK_PRI_MASK_TXAC_8821C) - - - -#define BIT_SHIFT_PRI_MASK_NAV_8821C (109 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_TXAC_8821C(x) \ + (((x) & BIT_MASK_PRI_MASK_TXAC_8821C) << BIT_SHIFT_PRI_MASK_TXAC_8821C) +#define BITS_PRI_MASK_TXAC_8821C \ + (BIT_MASK_PRI_MASK_TXAC_8821C << BIT_SHIFT_PRI_MASK_TXAC_8821C) +#define BIT_CLEAR_PRI_MASK_TXAC_8821C(x) ((x) & (~BITS_PRI_MASK_TXAC_8821C)) +#define BIT_GET_PRI_MASK_TXAC_8821C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8821C) & BIT_MASK_PRI_MASK_TXAC_8821C) +#define BIT_SET_PRI_MASK_TXAC_8821C(x, v) \ + (BIT_CLEAR_PRI_MASK_TXAC_8821C(x) | BIT_PRI_MASK_TXAC_8821C(v)) + +#define BIT_SHIFT_PRI_MASK_NAV_8821C 13 #define BIT_MASK_PRI_MASK_NAV_8821C 0xff -#define BIT_PRI_MASK_NAV_8821C(x) (((x) & BIT_MASK_PRI_MASK_NAV_8821C) << BIT_SHIFT_PRI_MASK_NAV_8821C) -#define BIT_GET_PRI_MASK_NAV_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8821C) & BIT_MASK_PRI_MASK_NAV_8821C) - - -#define BIT_PRI_MASK_CCK_8821C BIT(108) -#define BIT_PRI_MASK_OFDM_8821C BIT(107) -#define BIT_PRI_MASK_RTY_8821C BIT(106) - -#define BIT_SHIFT_PRI_MASK_NUM_8821C (102 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_NAV_8821C(x) \ + (((x) & BIT_MASK_PRI_MASK_NAV_8821C) << BIT_SHIFT_PRI_MASK_NAV_8821C) +#define BITS_PRI_MASK_NAV_8821C \ + (BIT_MASK_PRI_MASK_NAV_8821C << BIT_SHIFT_PRI_MASK_NAV_8821C) +#define BIT_CLEAR_PRI_MASK_NAV_8821C(x) ((x) & (~BITS_PRI_MASK_NAV_8821C)) +#define BIT_GET_PRI_MASK_NAV_8821C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NAV_8821C) & BIT_MASK_PRI_MASK_NAV_8821C) +#define BIT_SET_PRI_MASK_NAV_8821C(x, v) \ + (BIT_CLEAR_PRI_MASK_NAV_8821C(x) | BIT_PRI_MASK_NAV_8821C(v)) + +#define BIT_PRI_MASK_CCK_V1_8821C BIT(12) +#define BIT_PRI_MASK_OFDM_V1_8821C BIT(11) +#define BIT_PRI_MASK_RTY_V1_8821C BIT(10) + +#define BIT_SHIFT_PRI_MASK_NUM_8821C 6 #define BIT_MASK_PRI_MASK_NUM_8821C 0xf -#define BIT_PRI_MASK_NUM_8821C(x) (((x) & BIT_MASK_PRI_MASK_NUM_8821C) << BIT_SHIFT_PRI_MASK_NUM_8821C) -#define BIT_GET_PRI_MASK_NUM_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8821C) & BIT_MASK_PRI_MASK_NUM_8821C) - - - -#define BIT_SHIFT_PRI_MASK_TYPE_8821C (98 & CPU_OPT_WIDTH) +#define BIT_PRI_MASK_NUM_8821C(x) \ + (((x) & BIT_MASK_PRI_MASK_NUM_8821C) << BIT_SHIFT_PRI_MASK_NUM_8821C) +#define BITS_PRI_MASK_NUM_8821C \ + (BIT_MASK_PRI_MASK_NUM_8821C << BIT_SHIFT_PRI_MASK_NUM_8821C) +#define BIT_CLEAR_PRI_MASK_NUM_8821C(x) ((x) & (~BITS_PRI_MASK_NUM_8821C)) +#define BIT_GET_PRI_MASK_NUM_8821C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NUM_8821C) & BIT_MASK_PRI_MASK_NUM_8821C) +#define BIT_SET_PRI_MASK_NUM_8821C(x, v) \ + (BIT_CLEAR_PRI_MASK_NUM_8821C(x) | BIT_PRI_MASK_NUM_8821C(v)) + +#define BIT_SHIFT_PRI_MASK_TYPE_8821C 2 #define BIT_MASK_PRI_MASK_TYPE_8821C 0xf -#define BIT_PRI_MASK_TYPE_8821C(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8821C) << BIT_SHIFT_PRI_MASK_TYPE_8821C) -#define BIT_GET_PRI_MASK_TYPE_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8821C) & BIT_MASK_PRI_MASK_TYPE_8821C) - - -#define BIT_OOB_8821C BIT(97) -#define BIT_ANT_SEL_8821C BIT(96) - -#define BIT_SHIFT_BREAK_TABLE_2_8821C (80 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_2_8821C 0xffff -#define BIT_BREAK_TABLE_2_8821C(x) (((x) & BIT_MASK_BREAK_TABLE_2_8821C) << BIT_SHIFT_BREAK_TABLE_2_8821C) -#define BIT_GET_BREAK_TABLE_2_8821C(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8821C) & BIT_MASK_BREAK_TABLE_2_8821C) - - - -#define BIT_SHIFT_BREAK_TABLE_1_8821C (64 & CPU_OPT_WIDTH) -#define BIT_MASK_BREAK_TABLE_1_8821C 0xffff -#define BIT_BREAK_TABLE_1_8821C(x) (((x) & BIT_MASK_BREAK_TABLE_1_8821C) << BIT_SHIFT_BREAK_TABLE_1_8821C) -#define BIT_GET_BREAK_TABLE_1_8821C(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8821C) & BIT_MASK_BREAK_TABLE_1_8821C) - - - -#define BIT_SHIFT_COEX_TABLE_2_8821C (32 & CPU_OPT_WIDTH) -#define BIT_MASK_COEX_TABLE_2_8821C 0xffffffffL -#define BIT_COEX_TABLE_2_8821C(x) (((x) & BIT_MASK_COEX_TABLE_2_8821C) << BIT_SHIFT_COEX_TABLE_2_8821C) -#define BIT_GET_COEX_TABLE_2_8821C(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8821C) & BIT_MASK_COEX_TABLE_2_8821C) - - - -#define BIT_SHIFT_COEX_TABLE_1_8821C 0 -#define BIT_MASK_COEX_TABLE_1_8821C 0xffffffffL -#define BIT_COEX_TABLE_1_8821C(x) (((x) & BIT_MASK_COEX_TABLE_1_8821C) << BIT_SHIFT_COEX_TABLE_1_8821C) -#define BIT_GET_COEX_TABLE_1_8821C(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8821C) & BIT_MASK_COEX_TABLE_1_8821C) - - +#define BIT_PRI_MASK_TYPE_8821C(x) \ + (((x) & BIT_MASK_PRI_MASK_TYPE_8821C) << BIT_SHIFT_PRI_MASK_TYPE_8821C) +#define BITS_PRI_MASK_TYPE_8821C \ + (BIT_MASK_PRI_MASK_TYPE_8821C << BIT_SHIFT_PRI_MASK_TYPE_8821C) +#define BIT_CLEAR_PRI_MASK_TYPE_8821C(x) ((x) & (~BITS_PRI_MASK_TYPE_8821C)) +#define BIT_GET_PRI_MASK_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8821C) & BIT_MASK_PRI_MASK_TYPE_8821C) +#define BIT_SET_PRI_MASK_TYPE_8821C(x, v) \ + (BIT_CLEAR_PRI_MASK_TYPE_8821C(x) | BIT_PRI_MASK_TYPE_8821C(v)) + +#define BIT_OOB_V1_8821C BIT(1) +#define BIT_ANT_SEL_V1_8821C BIT(0) /* 2 REG_RXCMD_0_8821C */ #define BIT_RXCMD_EN_8821C BIT(31) #define BIT_SHIFT_RXCMD_INFO_8821C 0 #define BIT_MASK_RXCMD_INFO_8821C 0x7fffffffL -#define BIT_RXCMD_INFO_8821C(x) (((x) & BIT_MASK_RXCMD_INFO_8821C) << BIT_SHIFT_RXCMD_INFO_8821C) -#define BIT_GET_RXCMD_INFO_8821C(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8821C) & BIT_MASK_RXCMD_INFO_8821C) - - +#define BIT_RXCMD_INFO_8821C(x) \ + (((x) & BIT_MASK_RXCMD_INFO_8821C) << BIT_SHIFT_RXCMD_INFO_8821C) +#define BITS_RXCMD_INFO_8821C \ + (BIT_MASK_RXCMD_INFO_8821C << BIT_SHIFT_RXCMD_INFO_8821C) +#define BIT_CLEAR_RXCMD_INFO_8821C(x) ((x) & (~BITS_RXCMD_INFO_8821C)) +#define BIT_GET_RXCMD_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO_8821C) & BIT_MASK_RXCMD_INFO_8821C) +#define BIT_SET_RXCMD_INFO_8821C(x, v) \ + (BIT_CLEAR_RXCMD_INFO_8821C(x) | BIT_RXCMD_INFO_8821C(v)) /* 2 REG_RXCMD_1_8821C */ +#define BIT_SHIFT_CSI_RADDR_LATCH_8821C 24 +#define BIT_MASK_CSI_RADDR_LATCH_8821C 0xff +#define BIT_CSI_RADDR_LATCH_8821C(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH_8821C) \ + << BIT_SHIFT_CSI_RADDR_LATCH_8821C) +#define BITS_CSI_RADDR_LATCH_8821C \ + (BIT_MASK_CSI_RADDR_LATCH_8821C << BIT_SHIFT_CSI_RADDR_LATCH_8821C) +#define BIT_CLEAR_CSI_RADDR_LATCH_8821C(x) ((x) & (~BITS_CSI_RADDR_LATCH_8821C)) +#define BIT_GET_CSI_RADDR_LATCH_8821C(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_8821C) & \ + BIT_MASK_CSI_RADDR_LATCH_8821C) +#define BIT_SET_CSI_RADDR_LATCH_8821C(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH_8821C(x) | BIT_CSI_RADDR_LATCH_8821C(v)) + +#define BIT_SHIFT_CSI_WADDR_LATCH_8821C 16 +#define BIT_MASK_CSI_WADDR_LATCH_8821C 0xff +#define BIT_CSI_WADDR_LATCH_8821C(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH_8821C) \ + << BIT_SHIFT_CSI_WADDR_LATCH_8821C) +#define BITS_CSI_WADDR_LATCH_8821C \ + (BIT_MASK_CSI_WADDR_LATCH_8821C << BIT_SHIFT_CSI_WADDR_LATCH_8821C) +#define BIT_CLEAR_CSI_WADDR_LATCH_8821C(x) ((x) & (~BITS_CSI_WADDR_LATCH_8821C)) +#define BIT_GET_CSI_WADDR_LATCH_8821C(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_8821C) & \ + BIT_MASK_CSI_WADDR_LATCH_8821C) +#define BIT_SET_CSI_WADDR_LATCH_8821C(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH_8821C(x) | BIT_CSI_WADDR_LATCH_8821C(v)) + #define BIT_SHIFT_RXCMD_PRD_8821C 0 #define BIT_MASK_RXCMD_PRD_8821C 0xffff -#define BIT_RXCMD_PRD_8821C(x) (((x) & BIT_MASK_RXCMD_PRD_8821C) << BIT_SHIFT_RXCMD_PRD_8821C) -#define BIT_GET_RXCMD_PRD_8821C(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8821C) & BIT_MASK_RXCMD_PRD_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_RXCMD_PRD_8821C(x) \ + (((x) & BIT_MASK_RXCMD_PRD_8821C) << BIT_SHIFT_RXCMD_PRD_8821C) +#define BITS_RXCMD_PRD_8821C \ + (BIT_MASK_RXCMD_PRD_8821C << BIT_SHIFT_RXCMD_PRD_8821C) +#define BIT_CLEAR_RXCMD_PRD_8821C(x) ((x) & (~BITS_RXCMD_PRD_8821C)) +#define BIT_GET_RXCMD_PRD_8821C(x) \ + (((x) >> BIT_SHIFT_RXCMD_PRD_8821C) & BIT_MASK_RXCMD_PRD_8821C) +#define BIT_SET_RXCMD_PRD_8821C(x, v) \ + (BIT_CLEAR_RXCMD_PRD_8821C(x) | BIT_RXCMD_PRD_8821C(v)) /* 2 REG_WMAC_RESP_TXINFO_8821C (RESPONSE TXINFO REGISTER) */ #define BIT_SHIFT_WMAC_RESP_MFB_8821C 25 #define BIT_MASK_WMAC_RESP_MFB_8821C 0x7f -#define BIT_WMAC_RESP_MFB_8821C(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8821C) << BIT_SHIFT_WMAC_RESP_MFB_8821C) -#define BIT_GET_WMAC_RESP_MFB_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8821C) & BIT_MASK_WMAC_RESP_MFB_8821C) - - +#define BIT_WMAC_RESP_MFB_8821C(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB_8821C) << BIT_SHIFT_WMAC_RESP_MFB_8821C) +#define BITS_WMAC_RESP_MFB_8821C \ + (BIT_MASK_WMAC_RESP_MFB_8821C << BIT_SHIFT_WMAC_RESP_MFB_8821C) +#define BIT_CLEAR_WMAC_RESP_MFB_8821C(x) ((x) & (~BITS_WMAC_RESP_MFB_8821C)) +#define BIT_GET_WMAC_RESP_MFB_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8821C) & BIT_MASK_WMAC_RESP_MFB_8821C) +#define BIT_SET_WMAC_RESP_MFB_8821C(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB_8821C(x) | BIT_WMAC_RESP_MFB_8821C(v)) #define BIT_SHIFT_WMAC_ANTINF_SEL_8821C 23 #define BIT_MASK_WMAC_ANTINF_SEL_8821C 0x3 -#define BIT_WMAC_ANTINF_SEL_8821C(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8821C) << BIT_SHIFT_WMAC_ANTINF_SEL_8821C) -#define BIT_GET_WMAC_ANTINF_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8821C) & BIT_MASK_WMAC_ANTINF_SEL_8821C) - - +#define BIT_WMAC_ANTINF_SEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL_8821C) \ + << BIT_SHIFT_WMAC_ANTINF_SEL_8821C) +#define BITS_WMAC_ANTINF_SEL_8821C \ + (BIT_MASK_WMAC_ANTINF_SEL_8821C << BIT_SHIFT_WMAC_ANTINF_SEL_8821C) +#define BIT_CLEAR_WMAC_ANTINF_SEL_8821C(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8821C)) +#define BIT_GET_WMAC_ANTINF_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8821C) & \ + BIT_MASK_WMAC_ANTINF_SEL_8821C) +#define BIT_SET_WMAC_ANTINF_SEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL_8821C(x) | BIT_WMAC_ANTINF_SEL_8821C(v)) #define BIT_SHIFT_WMAC_ANTSEL_SEL_8821C 21 #define BIT_MASK_WMAC_ANTSEL_SEL_8821C 0x3 -#define BIT_WMAC_ANTSEL_SEL_8821C(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) -#define BIT_GET_WMAC_ANTSEL_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) - - +#define BIT_WMAC_ANTSEL_SEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) \ + << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) +#define BITS_WMAC_ANTSEL_SEL_8821C \ + (BIT_MASK_WMAC_ANTSEL_SEL_8821C << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) +#define BIT_CLEAR_WMAC_ANTSEL_SEL_8821C(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8821C)) +#define BIT_GET_WMAC_ANTSEL_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) & \ + BIT_MASK_WMAC_ANTSEL_SEL_8821C) +#define BIT_SET_WMAC_ANTSEL_SEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL_8821C(x) | BIT_WMAC_ANTSEL_SEL_8821C(v)) #define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C 18 #define BIT_MASK_R_WMAC_RESP_TXPOWER_8821C 0x7 -#define BIT_R_WMAC_RESP_TXPOWER_8821C(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) -#define BIT_GET_R_WMAC_RESP_TXPOWER_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) - - +#define BIT_R_WMAC_RESP_TXPOWER_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) +#define BITS_R_WMAC_RESP_TXPOWER_8821C \ + (BIT_MASK_R_WMAC_RESP_TXPOWER_8821C \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) +#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8821C(x) \ + ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8821C)) +#define BIT_GET_R_WMAC_RESP_TXPOWER_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) & \ + BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) +#define BIT_SET_R_WMAC_RESP_TXPOWER_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8821C(x) | \ + BIT_R_WMAC_RESP_TXPOWER_8821C(v)) #define BIT_SHIFT_WMAC_RESP_TXANT_8821C 0 #define BIT_MASK_WMAC_RESP_TXANT_8821C 0x3ffff -#define BIT_WMAC_RESP_TXANT_8821C(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8821C) << BIT_SHIFT_WMAC_RESP_TXANT_8821C) -#define BIT_GET_WMAC_RESP_TXANT_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8821C) & BIT_MASK_WMAC_RESP_TXANT_8821C) - - +#define BIT_WMAC_RESP_TXANT_8821C(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_8821C) \ + << BIT_SHIFT_WMAC_RESP_TXANT_8821C) +#define BITS_WMAC_RESP_TXANT_8821C \ + (BIT_MASK_WMAC_RESP_TXANT_8821C << BIT_SHIFT_WMAC_RESP_TXANT_8821C) +#define BIT_CLEAR_WMAC_RESP_TXANT_8821C(x) ((x) & (~BITS_WMAC_RESP_TXANT_8821C)) +#define BIT_GET_WMAC_RESP_TXANT_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8821C) & \ + BIT_MASK_WMAC_RESP_TXANT_8821C) +#define BIT_SET_WMAC_RESP_TXANT_8821C(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_8821C(x) | BIT_WMAC_RESP_TXANT_8821C(v)) /* 2 REG_BBPSF_CTRL_8821C */ #define BIT_CTL_IDLE_CLR_CSI_RPT_8821C BIT(31) @@ -9746,28 +16022,47 @@ #define BIT_SHIFT_WMAC_CSI_RATE_8821C 24 #define BIT_MASK_WMAC_CSI_RATE_8821C 0x3f -#define BIT_WMAC_CSI_RATE_8821C(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8821C) << BIT_SHIFT_WMAC_CSI_RATE_8821C) -#define BIT_GET_WMAC_CSI_RATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8821C) & BIT_MASK_WMAC_CSI_RATE_8821C) - - +#define BIT_WMAC_CSI_RATE_8821C(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE_8821C) << BIT_SHIFT_WMAC_CSI_RATE_8821C) +#define BITS_WMAC_CSI_RATE_8821C \ + (BIT_MASK_WMAC_CSI_RATE_8821C << BIT_SHIFT_WMAC_CSI_RATE_8821C) +#define BIT_CLEAR_WMAC_CSI_RATE_8821C(x) ((x) & (~BITS_WMAC_CSI_RATE_8821C)) +#define BIT_GET_WMAC_CSI_RATE_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8821C) & BIT_MASK_WMAC_CSI_RATE_8821C) +#define BIT_SET_WMAC_CSI_RATE_8821C(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE_8821C(x) | BIT_WMAC_CSI_RATE_8821C(v)) #define BIT_SHIFT_WMAC_RESP_TXRATE_8821C 16 #define BIT_MASK_WMAC_RESP_TXRATE_8821C 0xff -#define BIT_WMAC_RESP_TXRATE_8821C(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8821C) << BIT_SHIFT_WMAC_RESP_TXRATE_8821C) -#define BIT_GET_WMAC_RESP_TXRATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8821C) & BIT_MASK_WMAC_RESP_TXRATE_8821C) - +#define BIT_WMAC_RESP_TXRATE_8821C(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE_8821C) \ + << BIT_SHIFT_WMAC_RESP_TXRATE_8821C) +#define BITS_WMAC_RESP_TXRATE_8821C \ + (BIT_MASK_WMAC_RESP_TXRATE_8821C << BIT_SHIFT_WMAC_RESP_TXRATE_8821C) +#define BIT_CLEAR_WMAC_RESP_TXRATE_8821C(x) \ + ((x) & (~BITS_WMAC_RESP_TXRATE_8821C)) +#define BIT_GET_WMAC_RESP_TXRATE_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8821C) & \ + BIT_MASK_WMAC_RESP_TXRATE_8821C) +#define BIT_SET_WMAC_RESP_TXRATE_8821C(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE_8821C(x) | BIT_WMAC_RESP_TXRATE_8821C(v)) #define BIT_CSI_FORCE_RATE_EN_8821C BIT(15) #define BIT_SHIFT_CSI_RSC_8821C 13 #define BIT_MASK_CSI_RSC_8821C 0x3 -#define BIT_CSI_RSC_8821C(x) (((x) & BIT_MASK_CSI_RSC_8821C) << BIT_SHIFT_CSI_RSC_8821C) -#define BIT_GET_CSI_RSC_8821C(x) (((x) >> BIT_SHIFT_CSI_RSC_8821C) & BIT_MASK_CSI_RSC_8821C) - +#define BIT_CSI_RSC_8821C(x) \ + (((x) & BIT_MASK_CSI_RSC_8821C) << BIT_SHIFT_CSI_RSC_8821C) +#define BITS_CSI_RSC_8821C (BIT_MASK_CSI_RSC_8821C << BIT_SHIFT_CSI_RSC_8821C) +#define BIT_CLEAR_CSI_RSC_8821C(x) ((x) & (~BITS_CSI_RSC_8821C)) +#define BIT_GET_CSI_RSC_8821C(x) \ + (((x) >> BIT_SHIFT_CSI_RSC_8821C) & BIT_MASK_CSI_RSC_8821C) +#define BIT_SET_CSI_RSC_8821C(x, v) \ + (BIT_CLEAR_CSI_RSC_8821C(x) | BIT_CSI_RSC_8821C(v)) #define BIT_CSI_GID_SEL_8821C BIT(12) #define BIT_RDCSIMD_FLAG_TRIG_SEL_8821C BIT(11) -#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8821C BIT(10) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1_8821C BIT(10) #define BIT_NDPVLD_PROTECT_RDRDY_DIS_8821C BIT(9) #define BIT_RDCSI_EMPTY_APPZERO_8821C BIT(8) #define BIT_BBPSF_MPDUCHKEN_8821C BIT(5) @@ -9776,12 +16071,15 @@ #define BIT_SHIFT_BBPSF_ERRTHR_8821C 0 #define BIT_MASK_BBPSF_ERRTHR_8821C 0x7 -#define BIT_BBPSF_ERRTHR_8821C(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8821C) << BIT_SHIFT_BBPSF_ERRTHR_8821C) -#define BIT_GET_BBPSF_ERRTHR_8821C(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8821C) & BIT_MASK_BBPSF_ERRTHR_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_BBPSF_ERRTHR_8821C(x) \ + (((x) & BIT_MASK_BBPSF_ERRTHR_8821C) << BIT_SHIFT_BBPSF_ERRTHR_8821C) +#define BITS_BBPSF_ERRTHR_8821C \ + (BIT_MASK_BBPSF_ERRTHR_8821C << BIT_SHIFT_BBPSF_ERRTHR_8821C) +#define BIT_CLEAR_BBPSF_ERRTHR_8821C(x) ((x) & (~BITS_BBPSF_ERRTHR_8821C)) +#define BIT_GET_BBPSF_ERRTHR_8821C(x) \ + (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8821C) & BIT_MASK_BBPSF_ERRTHR_8821C) +#define BIT_SET_BBPSF_ERRTHR_8821C(x, v) \ + (BIT_CLEAR_BBPSF_ERRTHR_8821C(x) | BIT_BBPSF_ERRTHR_8821C(v)) /* 2 REG_P2P_RX_BCN_NOA_8821C (P2P RX BEACON NOA REGISTER) */ #define BIT_NOA_PARSER_EN_8821C BIT(15) @@ -9789,219 +16087,498 @@ #define BIT_SHIFT_P2P_OUI_TYPE_8821C 0 #define BIT_MASK_P2P_OUI_TYPE_8821C 0xff -#define BIT_P2P_OUI_TYPE_8821C(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8821C) << BIT_SHIFT_P2P_OUI_TYPE_8821C) -#define BIT_GET_P2P_OUI_TYPE_8821C(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8821C) & BIT_MASK_P2P_OUI_TYPE_8821C) - +#define BIT_P2P_OUI_TYPE_8821C(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE_8821C) << BIT_SHIFT_P2P_OUI_TYPE_8821C) +#define BITS_P2P_OUI_TYPE_8821C \ + (BIT_MASK_P2P_OUI_TYPE_8821C << BIT_SHIFT_P2P_OUI_TYPE_8821C) +#define BIT_CLEAR_P2P_OUI_TYPE_8821C(x) ((x) & (~BITS_P2P_OUI_TYPE_8821C)) +#define BIT_GET_P2P_OUI_TYPE_8821C(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8821C) & BIT_MASK_P2P_OUI_TYPE_8821C) +#define BIT_SET_P2P_OUI_TYPE_8821C(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE_8821C(x) | BIT_P2P_OUI_TYPE_8821C(v)) +/* 2 REG_RSVD_8821C */ /* 2 REG_ASSOCIATED_BFMER0_INFO_8821C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ -#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C (48 & CPU_OPT_WIDTH) +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8821C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(v)) + +/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8821C */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C 16 #define BIT_MASK_R_WMAC_TXCSI_AID0_8821C 0x1ff -#define BIT_R_WMAC_TXCSI_AID0_8821C(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) -#define BIT_GET_R_WMAC_TXCSI_AID0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C) - - - -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R0_8821C(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C) - - +#define BIT_R_WMAC_TXCSI_AID0_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) +#define BITS_R_WMAC_TXCSI_AID0_8821C \ + (BIT_MASK_R_WMAC_TXCSI_AID0_8821C << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) +#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8821C(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID0_8821C)) +#define BIT_GET_R_WMAC_TXCSI_AID0_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) & \ + BIT_MASK_R_WMAC_TXCSI_AID0_8821C) +#define BIT_SET_R_WMAC_TXCSI_AID0_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID0_8821C(x) | BIT_R_WMAC_TXCSI_AID0_8821C(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(v)) /* 2 REG_ASSOCIATED_BFMER1_INFO_8821C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ -#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C (48 & CPU_OPT_WIDTH) +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8821C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(v)) + +/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8821C */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C 16 #define BIT_MASK_R_WMAC_TXCSI_AID1_8821C 0x1ff -#define BIT_R_WMAC_TXCSI_AID1_8821C(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) -#define BIT_GET_R_WMAC_TXCSI_AID1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C) - - - -#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C 0 -#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R1_8821C(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C) - - - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ - -/* 2 REG_NOT_VALID_8821C */ +#define BIT_R_WMAC_TXCSI_AID1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) +#define BITS_R_WMAC_TXCSI_AID1_8821C \ + (BIT_MASK_R_WMAC_TXCSI_AID1_8821C << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) +#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8821C(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID1_8821C)) +#define BIT_GET_R_WMAC_TXCSI_AID1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) & \ + BIT_MASK_R_WMAC_TXCSI_AID1_8821C) +#define BIT_SET_R_WMAC_TXCSI_AID1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID1_8821C(x) | BIT_R_WMAC_TXCSI_AID1_8821C(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW20_8821C (TX CSI REPORT PARAMETER REGISTER) */ #define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C 16 #define BIT_MASK_R_WMAC_BFINFO_20M_1_8821C 0xfff -#define BIT_R_WMAC_BFINFO_20M_1_8821C(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) -#define BIT_GET_R_WMAC_BFINFO_20M_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) - - +#define BIT_R_WMAC_BFINFO_20M_1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) +#define BITS_R_WMAC_BFINFO_20M_1_8821C \ + (BIT_MASK_R_WMAC_BFINFO_20M_1_8821C \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8821C(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8821C)) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) & \ + BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) +#define BIT_SET_R_WMAC_BFINFO_20M_1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8821C(x) | \ + BIT_R_WMAC_BFINFO_20M_1_8821C(v)) #define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C 0 #define BIT_MASK_R_WMAC_BFINFO_20M_0_8821C 0xfff -#define BIT_R_WMAC_BFINFO_20M_0_8821C(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) -#define BIT_GET_R_WMAC_BFINFO_20M_0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) - - +#define BIT_R_WMAC_BFINFO_20M_0_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) +#define BITS_R_WMAC_BFINFO_20M_0_8821C \ + (BIT_MASK_R_WMAC_BFINFO_20M_0_8821C \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8821C(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8821C)) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) & \ + BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) +#define BIT_SET_R_WMAC_BFINFO_20M_0_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8821C(x) | \ + BIT_R_WMAC_BFINFO_20M_0_8821C(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW40_8821C (TX CSI REPORT PARAMETER_BW40 REGISTER) */ #define BIT_SHIFT_WMAC_RESP_ANTCD_8821C 0 #define BIT_MASK_WMAC_RESP_ANTCD_8821C 0xf -#define BIT_WMAC_RESP_ANTCD_8821C(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8821C) << BIT_SHIFT_WMAC_RESP_ANTCD_8821C) -#define BIT_GET_WMAC_RESP_ANTCD_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8821C) & BIT_MASK_WMAC_RESP_ANTCD_8821C) - +#define BIT_WMAC_RESP_ANTCD_8821C(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTCD_8821C) \ + << BIT_SHIFT_WMAC_RESP_ANTCD_8821C) +#define BITS_WMAC_RESP_ANTCD_8821C \ + (BIT_MASK_WMAC_RESP_ANTCD_8821C << BIT_SHIFT_WMAC_RESP_ANTCD_8821C) +#define BIT_CLEAR_WMAC_RESP_ANTCD_8821C(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8821C)) +#define BIT_GET_WMAC_RESP_ANTCD_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8821C) & \ + BIT_MASK_WMAC_RESP_ANTCD_8821C) +#define BIT_SET_WMAC_RESP_ANTCD_8821C(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTCD_8821C(x) | BIT_WMAC_RESP_ANTCD_8821C(v)) - -/* 2 REG_TX_CSI_RPT_PARAM_BW80_8821C (TX CSI REPORT PARAMETER_BW80 REGISTER) */ +/* 2 REG_RSVD_8821C */ /* 2 REG_BCN_PSR_RPT2_8821C (BEACON PARSER REPORT REGISTER2) */ #define BIT_SHIFT_DTIM_CNT2_8821C 24 #define BIT_MASK_DTIM_CNT2_8821C 0xff -#define BIT_DTIM_CNT2_8821C(x) (((x) & BIT_MASK_DTIM_CNT2_8821C) << BIT_SHIFT_DTIM_CNT2_8821C) -#define BIT_GET_DTIM_CNT2_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8821C) & BIT_MASK_DTIM_CNT2_8821C) - - +#define BIT_DTIM_CNT2_8821C(x) \ + (((x) & BIT_MASK_DTIM_CNT2_8821C) << BIT_SHIFT_DTIM_CNT2_8821C) +#define BITS_DTIM_CNT2_8821C \ + (BIT_MASK_DTIM_CNT2_8821C << BIT_SHIFT_DTIM_CNT2_8821C) +#define BIT_CLEAR_DTIM_CNT2_8821C(x) ((x) & (~BITS_DTIM_CNT2_8821C)) +#define BIT_GET_DTIM_CNT2_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT2_8821C) & BIT_MASK_DTIM_CNT2_8821C) +#define BIT_SET_DTIM_CNT2_8821C(x, v) \ + (BIT_CLEAR_DTIM_CNT2_8821C(x) | BIT_DTIM_CNT2_8821C(v)) #define BIT_SHIFT_DTIM_PERIOD2_8821C 16 #define BIT_MASK_DTIM_PERIOD2_8821C 0xff -#define BIT_DTIM_PERIOD2_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD2_8821C) << BIT_SHIFT_DTIM_PERIOD2_8821C) -#define BIT_GET_DTIM_PERIOD2_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8821C) & BIT_MASK_DTIM_PERIOD2_8821C) - +#define BIT_DTIM_PERIOD2_8821C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2_8821C) << BIT_SHIFT_DTIM_PERIOD2_8821C) +#define BITS_DTIM_PERIOD2_8821C \ + (BIT_MASK_DTIM_PERIOD2_8821C << BIT_SHIFT_DTIM_PERIOD2_8821C) +#define BIT_CLEAR_DTIM_PERIOD2_8821C(x) ((x) & (~BITS_DTIM_PERIOD2_8821C)) +#define BIT_GET_DTIM_PERIOD2_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2_8821C) & BIT_MASK_DTIM_PERIOD2_8821C) +#define BIT_SET_DTIM_PERIOD2_8821C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2_8821C(x) | BIT_DTIM_PERIOD2_8821C(v)) #define BIT_DTIM2_8821C BIT(15) #define BIT_TIM2_8821C BIT(14) #define BIT_SHIFT_PS_AID_2_8821C 0 #define BIT_MASK_PS_AID_2_8821C 0x7ff -#define BIT_PS_AID_2_8821C(x) (((x) & BIT_MASK_PS_AID_2_8821C) << BIT_SHIFT_PS_AID_2_8821C) -#define BIT_GET_PS_AID_2_8821C(x) (((x) >> BIT_SHIFT_PS_AID_2_8821C) & BIT_MASK_PS_AID_2_8821C) - - +#define BIT_PS_AID_2_8821C(x) \ + (((x) & BIT_MASK_PS_AID_2_8821C) << BIT_SHIFT_PS_AID_2_8821C) +#define BITS_PS_AID_2_8821C \ + (BIT_MASK_PS_AID_2_8821C << BIT_SHIFT_PS_AID_2_8821C) +#define BIT_CLEAR_PS_AID_2_8821C(x) ((x) & (~BITS_PS_AID_2_8821C)) +#define BIT_GET_PS_AID_2_8821C(x) \ + (((x) >> BIT_SHIFT_PS_AID_2_8821C) & BIT_MASK_PS_AID_2_8821C) +#define BIT_SET_PS_AID_2_8821C(x, v) \ + (BIT_CLEAR_PS_AID_2_8821C(x) | BIT_PS_AID_2_8821C(v)) /* 2 REG_BCN_PSR_RPT3_8821C (BEACON PARSER REPORT REGISTER3) */ #define BIT_SHIFT_DTIM_CNT3_8821C 24 #define BIT_MASK_DTIM_CNT3_8821C 0xff -#define BIT_DTIM_CNT3_8821C(x) (((x) & BIT_MASK_DTIM_CNT3_8821C) << BIT_SHIFT_DTIM_CNT3_8821C) -#define BIT_GET_DTIM_CNT3_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8821C) & BIT_MASK_DTIM_CNT3_8821C) - - +#define BIT_DTIM_CNT3_8821C(x) \ + (((x) & BIT_MASK_DTIM_CNT3_8821C) << BIT_SHIFT_DTIM_CNT3_8821C) +#define BITS_DTIM_CNT3_8821C \ + (BIT_MASK_DTIM_CNT3_8821C << BIT_SHIFT_DTIM_CNT3_8821C) +#define BIT_CLEAR_DTIM_CNT3_8821C(x) ((x) & (~BITS_DTIM_CNT3_8821C)) +#define BIT_GET_DTIM_CNT3_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT3_8821C) & BIT_MASK_DTIM_CNT3_8821C) +#define BIT_SET_DTIM_CNT3_8821C(x, v) \ + (BIT_CLEAR_DTIM_CNT3_8821C(x) | BIT_DTIM_CNT3_8821C(v)) #define BIT_SHIFT_DTIM_PERIOD3_8821C 16 #define BIT_MASK_DTIM_PERIOD3_8821C 0xff -#define BIT_DTIM_PERIOD3_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD3_8821C) << BIT_SHIFT_DTIM_PERIOD3_8821C) -#define BIT_GET_DTIM_PERIOD3_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8821C) & BIT_MASK_DTIM_PERIOD3_8821C) - +#define BIT_DTIM_PERIOD3_8821C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3_8821C) << BIT_SHIFT_DTIM_PERIOD3_8821C) +#define BITS_DTIM_PERIOD3_8821C \ + (BIT_MASK_DTIM_PERIOD3_8821C << BIT_SHIFT_DTIM_PERIOD3_8821C) +#define BIT_CLEAR_DTIM_PERIOD3_8821C(x) ((x) & (~BITS_DTIM_PERIOD3_8821C)) +#define BIT_GET_DTIM_PERIOD3_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3_8821C) & BIT_MASK_DTIM_PERIOD3_8821C) +#define BIT_SET_DTIM_PERIOD3_8821C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3_8821C(x) | BIT_DTIM_PERIOD3_8821C(v)) #define BIT_DTIM3_8821C BIT(15) #define BIT_TIM3_8821C BIT(14) #define BIT_SHIFT_PS_AID_3_8821C 0 #define BIT_MASK_PS_AID_3_8821C 0x7ff -#define BIT_PS_AID_3_8821C(x) (((x) & BIT_MASK_PS_AID_3_8821C) << BIT_SHIFT_PS_AID_3_8821C) -#define BIT_GET_PS_AID_3_8821C(x) (((x) >> BIT_SHIFT_PS_AID_3_8821C) & BIT_MASK_PS_AID_3_8821C) - - +#define BIT_PS_AID_3_8821C(x) \ + (((x) & BIT_MASK_PS_AID_3_8821C) << BIT_SHIFT_PS_AID_3_8821C) +#define BITS_PS_AID_3_8821C \ + (BIT_MASK_PS_AID_3_8821C << BIT_SHIFT_PS_AID_3_8821C) +#define BIT_CLEAR_PS_AID_3_8821C(x) ((x) & (~BITS_PS_AID_3_8821C)) +#define BIT_GET_PS_AID_3_8821C(x) \ + (((x) >> BIT_SHIFT_PS_AID_3_8821C) & BIT_MASK_PS_AID_3_8821C) +#define BIT_SET_PS_AID_3_8821C(x, v) \ + (BIT_CLEAR_PS_AID_3_8821C(x) | BIT_PS_AID_3_8821C(v)) /* 2 REG_BCN_PSR_RPT4_8821C (BEACON PARSER REPORT REGISTER4) */ #define BIT_SHIFT_DTIM_CNT4_8821C 24 #define BIT_MASK_DTIM_CNT4_8821C 0xff -#define BIT_DTIM_CNT4_8821C(x) (((x) & BIT_MASK_DTIM_CNT4_8821C) << BIT_SHIFT_DTIM_CNT4_8821C) -#define BIT_GET_DTIM_CNT4_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8821C) & BIT_MASK_DTIM_CNT4_8821C) - - +#define BIT_DTIM_CNT4_8821C(x) \ + (((x) & BIT_MASK_DTIM_CNT4_8821C) << BIT_SHIFT_DTIM_CNT4_8821C) +#define BITS_DTIM_CNT4_8821C \ + (BIT_MASK_DTIM_CNT4_8821C << BIT_SHIFT_DTIM_CNT4_8821C) +#define BIT_CLEAR_DTIM_CNT4_8821C(x) ((x) & (~BITS_DTIM_CNT4_8821C)) +#define BIT_GET_DTIM_CNT4_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT4_8821C) & BIT_MASK_DTIM_CNT4_8821C) +#define BIT_SET_DTIM_CNT4_8821C(x, v) \ + (BIT_CLEAR_DTIM_CNT4_8821C(x) | BIT_DTIM_CNT4_8821C(v)) #define BIT_SHIFT_DTIM_PERIOD4_8821C 16 #define BIT_MASK_DTIM_PERIOD4_8821C 0xff -#define BIT_DTIM_PERIOD4_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD4_8821C) << BIT_SHIFT_DTIM_PERIOD4_8821C) -#define BIT_GET_DTIM_PERIOD4_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8821C) & BIT_MASK_DTIM_PERIOD4_8821C) - +#define BIT_DTIM_PERIOD4_8821C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4_8821C) << BIT_SHIFT_DTIM_PERIOD4_8821C) +#define BITS_DTIM_PERIOD4_8821C \ + (BIT_MASK_DTIM_PERIOD4_8821C << BIT_SHIFT_DTIM_PERIOD4_8821C) +#define BIT_CLEAR_DTIM_PERIOD4_8821C(x) ((x) & (~BITS_DTIM_PERIOD4_8821C)) +#define BIT_GET_DTIM_PERIOD4_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4_8821C) & BIT_MASK_DTIM_PERIOD4_8821C) +#define BIT_SET_DTIM_PERIOD4_8821C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4_8821C(x) | BIT_DTIM_PERIOD4_8821C(v)) #define BIT_DTIM4_8821C BIT(15) #define BIT_TIM4_8821C BIT(14) #define BIT_SHIFT_PS_AID_4_8821C 0 #define BIT_MASK_PS_AID_4_8821C 0x7ff -#define BIT_PS_AID_4_8821C(x) (((x) & BIT_MASK_PS_AID_4_8821C) << BIT_SHIFT_PS_AID_4_8821C) -#define BIT_GET_PS_AID_4_8821C(x) (((x) >> BIT_SHIFT_PS_AID_4_8821C) & BIT_MASK_PS_AID_4_8821C) - - +#define BIT_PS_AID_4_8821C(x) \ + (((x) & BIT_MASK_PS_AID_4_8821C) << BIT_SHIFT_PS_AID_4_8821C) +#define BITS_PS_AID_4_8821C \ + (BIT_MASK_PS_AID_4_8821C << BIT_SHIFT_PS_AID_4_8821C) +#define BIT_CLEAR_PS_AID_4_8821C(x) ((x) & (~BITS_PS_AID_4_8821C)) +#define BIT_GET_PS_AID_4_8821C(x) \ + (((x) >> BIT_SHIFT_PS_AID_4_8821C) & BIT_MASK_PS_AID_4_8821C) +#define BIT_SET_PS_AID_4_8821C(x, v) \ + (BIT_CLEAR_PS_AID_4_8821C(x) | BIT_PS_AID_4_8821C(v)) /* 2 REG_A1_ADDR_MASK_8821C (A1 ADDR MASK REGISTER) */ #define BIT_SHIFT_A1_ADDR_MASK_8821C 0 #define BIT_MASK_A1_ADDR_MASK_8821C 0xffffffffL -#define BIT_A1_ADDR_MASK_8821C(x) (((x) & BIT_MASK_A1_ADDR_MASK_8821C) << BIT_SHIFT_A1_ADDR_MASK_8821C) -#define BIT_GET_A1_ADDR_MASK_8821C(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8821C) & BIT_MASK_A1_ADDR_MASK_8821C) +#define BIT_A1_ADDR_MASK_8821C(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK_8821C) << BIT_SHIFT_A1_ADDR_MASK_8821C) +#define BITS_A1_ADDR_MASK_8821C \ + (BIT_MASK_A1_ADDR_MASK_8821C << BIT_SHIFT_A1_ADDR_MASK_8821C) +#define BIT_CLEAR_A1_ADDR_MASK_8821C(x) ((x) & (~BITS_A1_ADDR_MASK_8821C)) +#define BIT_GET_A1_ADDR_MASK_8821C(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK_8821C) & BIT_MASK_A1_ADDR_MASK_8821C) +#define BIT_SET_A1_ADDR_MASK_8821C(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK_8821C(x) | BIT_A1_ADDR_MASK_8821C(v)) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ -/* 2 REG_MACID2_8821C (MAC ID2 REGISTER) */ +/* 2 REG_RSVD_8821C */ -#define BIT_SHIFT_MACID2_8821C 0 -#define BIT_MASK_MACID2_8821C 0xffffffffffffL -#define BIT_MACID2_8821C(x) (((x) & BIT_MASK_MACID2_8821C) << BIT_SHIFT_MACID2_8821C) -#define BIT_GET_MACID2_8821C(x) (((x) >> BIT_SHIFT_MACID2_8821C) & BIT_MASK_MACID2_8821C) +/* 2 REG_RSVD_8821C */ +/* 2 REG_MACID2_8821C (MAC ID2 REGISTER) */ +#define BIT_SHIFT_MACID2_V1_8821C 0 +#define BIT_MASK_MACID2_V1_8821C 0xffffffffL +#define BIT_MACID2_V1_8821C(x) \ + (((x) & BIT_MASK_MACID2_V1_8821C) << BIT_SHIFT_MACID2_V1_8821C) +#define BITS_MACID2_V1_8821C \ + (BIT_MASK_MACID2_V1_8821C << BIT_SHIFT_MACID2_V1_8821C) +#define BIT_CLEAR_MACID2_V1_8821C(x) ((x) & (~BITS_MACID2_V1_8821C)) +#define BIT_GET_MACID2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID2_V1_8821C) & BIT_MASK_MACID2_V1_8821C) +#define BIT_SET_MACID2_V1_8821C(x, v) \ + (BIT_CLEAR_MACID2_V1_8821C(x) | BIT_MACID2_V1_8821C(v)) + +/* 2 REG_MACID2_H_8821C (MAC ID2 REGISTER) */ + +#define BIT_SHIFT_MACID2_H_V1_8821C 0 +#define BIT_MASK_MACID2_H_V1_8821C 0xffff +#define BIT_MACID2_H_V1_8821C(x) \ + (((x) & BIT_MASK_MACID2_H_V1_8821C) << BIT_SHIFT_MACID2_H_V1_8821C) +#define BITS_MACID2_H_V1_8821C \ + (BIT_MASK_MACID2_H_V1_8821C << BIT_SHIFT_MACID2_H_V1_8821C) +#define BIT_CLEAR_MACID2_H_V1_8821C(x) ((x) & (~BITS_MACID2_H_V1_8821C)) +#define BIT_GET_MACID2_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID2_H_V1_8821C) & BIT_MASK_MACID2_H_V1_8821C) +#define BIT_SET_MACID2_H_V1_8821C(x, v) \ + (BIT_CLEAR_MACID2_H_V1_8821C(x) | BIT_MACID2_H_V1_8821C(v)) /* 2 REG_BSSID2_8821C (BSSID2 REGISTER) */ -#define BIT_SHIFT_BSSID2_8821C 0 -#define BIT_MASK_BSSID2_8821C 0xffffffffffffL -#define BIT_BSSID2_8821C(x) (((x) & BIT_MASK_BSSID2_8821C) << BIT_SHIFT_BSSID2_8821C) -#define BIT_GET_BSSID2_8821C(x) (((x) >> BIT_SHIFT_BSSID2_8821C) & BIT_MASK_BSSID2_8821C) - - +#define BIT_SHIFT_BSSID2_V1_8821C 0 +#define BIT_MASK_BSSID2_V1_8821C 0xffffffffL +#define BIT_BSSID2_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID2_V1_8821C) << BIT_SHIFT_BSSID2_V1_8821C) +#define BITS_BSSID2_V1_8821C \ + (BIT_MASK_BSSID2_V1_8821C << BIT_SHIFT_BSSID2_V1_8821C) +#define BIT_CLEAR_BSSID2_V1_8821C(x) ((x) & (~BITS_BSSID2_V1_8821C)) +#define BIT_GET_BSSID2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID2_V1_8821C) & BIT_MASK_BSSID2_V1_8821C) +#define BIT_SET_BSSID2_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID2_V1_8821C(x) | BIT_BSSID2_V1_8821C(v)) + +/* 2 REG_BSSID2_H_8821C (BSSID2 REGISTER) */ + +#define BIT_SHIFT_BSSID2_H_V1_8821C 0 +#define BIT_MASK_BSSID2_H_V1_8821C 0xffff +#define BIT_BSSID2_H_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID2_H_V1_8821C) << BIT_SHIFT_BSSID2_H_V1_8821C) +#define BITS_BSSID2_H_V1_8821C \ + (BIT_MASK_BSSID2_H_V1_8821C << BIT_SHIFT_BSSID2_H_V1_8821C) +#define BIT_CLEAR_BSSID2_H_V1_8821C(x) ((x) & (~BITS_BSSID2_H_V1_8821C)) +#define BIT_GET_BSSID2_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID2_H_V1_8821C) & BIT_MASK_BSSID2_H_V1_8821C) +#define BIT_SET_BSSID2_H_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID2_H_V1_8821C(x) | BIT_BSSID2_H_V1_8821C(v)) /* 2 REG_MACID3_8821C (MAC ID3 REGISTER) */ -#define BIT_SHIFT_MACID3_8821C 0 -#define BIT_MASK_MACID3_8821C 0xffffffffffffL -#define BIT_MACID3_8821C(x) (((x) & BIT_MASK_MACID3_8821C) << BIT_SHIFT_MACID3_8821C) -#define BIT_GET_MACID3_8821C(x) (((x) >> BIT_SHIFT_MACID3_8821C) & BIT_MASK_MACID3_8821C) - - +#define BIT_SHIFT_MACID3_V1_8821C 0 +#define BIT_MASK_MACID3_V1_8821C 0xffffffffL +#define BIT_MACID3_V1_8821C(x) \ + (((x) & BIT_MASK_MACID3_V1_8821C) << BIT_SHIFT_MACID3_V1_8821C) +#define BITS_MACID3_V1_8821C \ + (BIT_MASK_MACID3_V1_8821C << BIT_SHIFT_MACID3_V1_8821C) +#define BIT_CLEAR_MACID3_V1_8821C(x) ((x) & (~BITS_MACID3_V1_8821C)) +#define BIT_GET_MACID3_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID3_V1_8821C) & BIT_MASK_MACID3_V1_8821C) +#define BIT_SET_MACID3_V1_8821C(x, v) \ + (BIT_CLEAR_MACID3_V1_8821C(x) | BIT_MACID3_V1_8821C(v)) + +/* 2 REG_MACID3_H_8821C (MAC ID3 REGISTER) */ + +#define BIT_SHIFT_MACID3_H_V1_8821C 0 +#define BIT_MASK_MACID3_H_V1_8821C 0xffff +#define BIT_MACID3_H_V1_8821C(x) \ + (((x) & BIT_MASK_MACID3_H_V1_8821C) << BIT_SHIFT_MACID3_H_V1_8821C) +#define BITS_MACID3_H_V1_8821C \ + (BIT_MASK_MACID3_H_V1_8821C << BIT_SHIFT_MACID3_H_V1_8821C) +#define BIT_CLEAR_MACID3_H_V1_8821C(x) ((x) & (~BITS_MACID3_H_V1_8821C)) +#define BIT_GET_MACID3_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID3_H_V1_8821C) & BIT_MASK_MACID3_H_V1_8821C) +#define BIT_SET_MACID3_H_V1_8821C(x, v) \ + (BIT_CLEAR_MACID3_H_V1_8821C(x) | BIT_MACID3_H_V1_8821C(v)) /* 2 REG_BSSID3_8821C (BSSID3 REGISTER) */ -#define BIT_SHIFT_BSSID3_8821C 0 -#define BIT_MASK_BSSID3_8821C 0xffffffffffffL -#define BIT_BSSID3_8821C(x) (((x) & BIT_MASK_BSSID3_8821C) << BIT_SHIFT_BSSID3_8821C) -#define BIT_GET_BSSID3_8821C(x) (((x) >> BIT_SHIFT_BSSID3_8821C) & BIT_MASK_BSSID3_8821C) - - +#define BIT_SHIFT_BSSID3_V1_8821C 0 +#define BIT_MASK_BSSID3_V1_8821C 0xffffffffL +#define BIT_BSSID3_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID3_V1_8821C) << BIT_SHIFT_BSSID3_V1_8821C) +#define BITS_BSSID3_V1_8821C \ + (BIT_MASK_BSSID3_V1_8821C << BIT_SHIFT_BSSID3_V1_8821C) +#define BIT_CLEAR_BSSID3_V1_8821C(x) ((x) & (~BITS_BSSID3_V1_8821C)) +#define BIT_GET_BSSID3_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID3_V1_8821C) & BIT_MASK_BSSID3_V1_8821C) +#define BIT_SET_BSSID3_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID3_V1_8821C(x) | BIT_BSSID3_V1_8821C(v)) + +/* 2 REG_BSSID3_H_8821C (BSSID3 REGISTER) */ + +#define BIT_SHIFT_BSSID3_H_V1_8821C 0 +#define BIT_MASK_BSSID3_H_V1_8821C 0xffff +#define BIT_BSSID3_H_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID3_H_V1_8821C) << BIT_SHIFT_BSSID3_H_V1_8821C) +#define BITS_BSSID3_H_V1_8821C \ + (BIT_MASK_BSSID3_H_V1_8821C << BIT_SHIFT_BSSID3_H_V1_8821C) +#define BIT_CLEAR_BSSID3_H_V1_8821C(x) ((x) & (~BITS_BSSID3_H_V1_8821C)) +#define BIT_GET_BSSID3_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID3_H_V1_8821C) & BIT_MASK_BSSID3_H_V1_8821C) +#define BIT_SET_BSSID3_H_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID3_H_V1_8821C(x) | BIT_BSSID3_H_V1_8821C(v)) /* 2 REG_MACID4_8821C (MAC ID4 REGISTER) */ -#define BIT_SHIFT_MACID4_8821C 0 -#define BIT_MASK_MACID4_8821C 0xffffffffffffL -#define BIT_MACID4_8821C(x) (((x) & BIT_MASK_MACID4_8821C) << BIT_SHIFT_MACID4_8821C) -#define BIT_GET_MACID4_8821C(x) (((x) >> BIT_SHIFT_MACID4_8821C) & BIT_MASK_MACID4_8821C) - - +#define BIT_SHIFT_MACID4_V1_8821C 0 +#define BIT_MASK_MACID4_V1_8821C 0xffffffffL +#define BIT_MACID4_V1_8821C(x) \ + (((x) & BIT_MASK_MACID4_V1_8821C) << BIT_SHIFT_MACID4_V1_8821C) +#define BITS_MACID4_V1_8821C \ + (BIT_MASK_MACID4_V1_8821C << BIT_SHIFT_MACID4_V1_8821C) +#define BIT_CLEAR_MACID4_V1_8821C(x) ((x) & (~BITS_MACID4_V1_8821C)) +#define BIT_GET_MACID4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID4_V1_8821C) & BIT_MASK_MACID4_V1_8821C) +#define BIT_SET_MACID4_V1_8821C(x, v) \ + (BIT_CLEAR_MACID4_V1_8821C(x) | BIT_MACID4_V1_8821C(v)) + +/* 2 REG_MACID4_H_8821C (MAC ID4 REGISTER) */ + +#define BIT_SHIFT_MACID4_H_V1_8821C 0 +#define BIT_MASK_MACID4_H_V1_8821C 0xffff +#define BIT_MACID4_H_V1_8821C(x) \ + (((x) & BIT_MASK_MACID4_H_V1_8821C) << BIT_SHIFT_MACID4_H_V1_8821C) +#define BITS_MACID4_H_V1_8821C \ + (BIT_MASK_MACID4_H_V1_8821C << BIT_SHIFT_MACID4_H_V1_8821C) +#define BIT_CLEAR_MACID4_H_V1_8821C(x) ((x) & (~BITS_MACID4_H_V1_8821C)) +#define BIT_GET_MACID4_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID4_H_V1_8821C) & BIT_MASK_MACID4_H_V1_8821C) +#define BIT_SET_MACID4_H_V1_8821C(x, v) \ + (BIT_CLEAR_MACID4_H_V1_8821C(x) | BIT_MACID4_H_V1_8821C(v)) /* 2 REG_BSSID4_8821C (BSSID4 REGISTER) */ -#define BIT_SHIFT_BSSID4_8821C 0 -#define BIT_MASK_BSSID4_8821C 0xffffffffffffL -#define BIT_BSSID4_8821C(x) (((x) & BIT_MASK_BSSID4_8821C) << BIT_SHIFT_BSSID4_8821C) -#define BIT_GET_BSSID4_8821C(x) (((x) >> BIT_SHIFT_BSSID4_8821C) & BIT_MASK_BSSID4_8821C) +#define BIT_SHIFT_BSSID4_V1_8821C 0 +#define BIT_MASK_BSSID4_V1_8821C 0xffffffffL +#define BIT_BSSID4_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID4_V1_8821C) << BIT_SHIFT_BSSID4_V1_8821C) +#define BITS_BSSID4_V1_8821C \ + (BIT_MASK_BSSID4_V1_8821C << BIT_SHIFT_BSSID4_V1_8821C) +#define BIT_CLEAR_BSSID4_V1_8821C(x) ((x) & (~BITS_BSSID4_V1_8821C)) +#define BIT_GET_BSSID4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID4_V1_8821C) & BIT_MASK_BSSID4_V1_8821C) +#define BIT_SET_BSSID4_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID4_V1_8821C(x) | BIT_BSSID4_V1_8821C(v)) + +/* 2 REG_BSSID4_H_8821C (BSSID4 REGISTER) */ + +#define BIT_SHIFT_BSSID4_H_V1_8821C 0 +#define BIT_MASK_BSSID4_H_V1_8821C 0xffff +#define BIT_BSSID4_H_V1_8821C(x) \ + (((x) & BIT_MASK_BSSID4_H_V1_8821C) << BIT_SHIFT_BSSID4_H_V1_8821C) +#define BITS_BSSID4_H_V1_8821C \ + (BIT_MASK_BSSID4_H_V1_8821C << BIT_SHIFT_BSSID4_H_V1_8821C) +#define BIT_CLEAR_BSSID4_H_V1_8821C(x) ((x) & (~BITS_BSSID4_H_V1_8821C)) +#define BIT_GET_BSSID4_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID4_H_V1_8821C) & BIT_MASK_BSSID4_H_V1_8821C) +#define BIT_SET_BSSID4_H_V1_8821C(x, v) \ + (BIT_CLEAR_BSSID4_H_V1_8821C(x) | BIT_BSSID4_H_V1_8821C(v)) + +/* 2 REG_NOA_REPORT_8821C */ +/* 2 REG_NOA_REPORT_1_8821C */ +/* 2 REG_NOA_REPORT_2_8821C */ -/* 2 REG_NOA_REPORT_8821C */ +/* 2 REG_NOA_REPORT_3_8821C */ /* 2 REG_PWRBIT_SETTING_8821C */ #define BIT_CLI3_PWRBIT_OW_EN_8821C BIT(7) @@ -10013,22 +16590,55 @@ #define BIT_CLI0_PWRBIT_OW_EN_8821C BIT(1) #define BIT_CLI0_PWR_ST_8821C BIT(0) -/* 2 REG_WMAC_MU_BF_OPTION_8821C */ +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_MU_BF_OPTION_8821C */ #define BIT_WMAC_RESP_NONSTA1_DIS_8821C BIT(7) #define BIT_WMAC_TXMU_ACKPOLICY_EN_8821C BIT(6) #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C 4 #define BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C 0x3 -#define BIT_WMAC_TXMU_ACKPOLICY_8821C(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) -#define BIT_GET_WMAC_TXMU_ACKPOLICY_8821C(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) - - +#define BIT_WMAC_TXMU_ACKPOLICY_8821C(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) +#define BITS_WMAC_TXMU_ACKPOLICY_8821C \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8821C(x) \ + ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8821C)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) & \ + BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) +#define BIT_SET_WMAC_TXMU_ACKPOLICY_8821C(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8821C(x) | \ + BIT_WMAC_TXMU_ACKPOLICY_8821C(v)) #define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C 1 #define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C 0x7 -#define BIT_WMAC_MU_BFEE_PORT_SEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) -#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) - +#define BIT_WMAC_MU_BFEE_PORT_SEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) +#define BITS_WMAC_MU_BFEE_PORT_SEL_8821C \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8821C)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8821C(x) | \ + BIT_WMAC_MU_BFEE_PORT_SEL_8821C(v)) #define BIT_WMAC_MU_BFEE_DIS_8821C BIT(0) @@ -10036,10 +16646,20 @@ #define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C 0 #define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C 0xff -#define BIT_WMAC_PAUSE_BB_CLR_TH_8821C(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) -#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8821C(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) - - +#define BIT_WMAC_PAUSE_BB_CLR_TH_8821C(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) +#define BITS_WMAC_PAUSE_BB_CLR_TH_8821C \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8821C(x) \ + ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8821C)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8821C(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8821C(x) | \ + BIT_WMAC_PAUSE_BB_CLR_TH_8821C(v)) /* 2 REG_WMAC_MU_ARB_8821C */ #define BIT_WMAC_ARB_HW_ADAPT_EN_8821C BIT(7) @@ -10047,26 +16667,51 @@ #define BIT_SHIFT_WMAC_ARB_SW_STATE_8821C 0 #define BIT_MASK_WMAC_ARB_SW_STATE_8821C 0x3f -#define BIT_WMAC_ARB_SW_STATE_8821C(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8821C) << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) -#define BIT_GET_WMAC_ARB_SW_STATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) & BIT_MASK_WMAC_ARB_SW_STATE_8821C) - - +#define BIT_WMAC_ARB_SW_STATE_8821C(x) \ + (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8821C) \ + << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) +#define BITS_WMAC_ARB_SW_STATE_8821C \ + (BIT_MASK_WMAC_ARB_SW_STATE_8821C << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) +#define BIT_CLEAR_WMAC_ARB_SW_STATE_8821C(x) \ + ((x) & (~BITS_WMAC_ARB_SW_STATE_8821C)) +#define BIT_GET_WMAC_ARB_SW_STATE_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) & \ + BIT_MASK_WMAC_ARB_SW_STATE_8821C) +#define BIT_SET_WMAC_ARB_SW_STATE_8821C(x, v) \ + (BIT_CLEAR_WMAC_ARB_SW_STATE_8821C(x) | BIT_WMAC_ARB_SW_STATE_8821C(v)) /* 2 REG_WMAC_MU_OPTION_8821C */ #define BIT_SHIFT_WMAC_MU_DBGSEL_8821C 5 #define BIT_MASK_WMAC_MU_DBGSEL_8821C 0x3 -#define BIT_WMAC_MU_DBGSEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8821C) << BIT_SHIFT_WMAC_MU_DBGSEL_8821C) -#define BIT_GET_WMAC_MU_DBGSEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8821C) & BIT_MASK_WMAC_MU_DBGSEL_8821C) - - +#define BIT_WMAC_MU_DBGSEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL_8821C) \ + << BIT_SHIFT_WMAC_MU_DBGSEL_8821C) +#define BITS_WMAC_MU_DBGSEL_8821C \ + (BIT_MASK_WMAC_MU_DBGSEL_8821C << BIT_SHIFT_WMAC_MU_DBGSEL_8821C) +#define BIT_CLEAR_WMAC_MU_DBGSEL_8821C(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8821C)) +#define BIT_GET_WMAC_MU_DBGSEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8821C) & \ + BIT_MASK_WMAC_MU_DBGSEL_8821C) +#define BIT_SET_WMAC_MU_DBGSEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL_8821C(x) | BIT_WMAC_MU_DBGSEL_8821C(v)) #define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C 0 #define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C 0x1f -#define BIT_WMAC_MU_CPRD_TIMEOUT_8821C(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) -#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) - - +#define BIT_WMAC_MU_CPRD_TIMEOUT_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) +#define BITS_WMAC_MU_CPRD_TIMEOUT_8821C \ + (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) +#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8821C(x) \ + ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8821C)) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) & \ + BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) +#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8821C(x) | \ + BIT_WMAC_MU_CPRD_TIMEOUT_8821C(v)) /* 2 REG_WMAC_MU_BF_CTL_8821C */ #define BIT_WMAC_INVLD_BFPRT_CHK_8821C BIT(15) @@ -10074,33 +16719,66 @@ #define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C 12 #define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C 0x3 -#define BIT_WMAC_MU_BFRPTSEG_SEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) -#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) - - +#define BIT_WMAC_MU_BFRPTSEG_SEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) +#define BITS_WMAC_MU_BFRPTSEG_SEL_8821C \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8821C)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x) | \ + BIT_WMAC_MU_BFRPTSEG_SEL_8821C(v)) #define BIT_SHIFT_WMAC_MU_BF_MYAID_8821C 0 #define BIT_MASK_WMAC_MU_BF_MYAID_8821C 0xfff -#define BIT_WMAC_MU_BF_MYAID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8821C) << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) -#define BIT_GET_WMAC_MU_BF_MYAID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) & BIT_MASK_WMAC_MU_BF_MYAID_8821C) - - - -/* 2 REG_WMAC_MU_BIT_BFRPT_PARA_8821C */ +#define BIT_WMAC_MU_BF_MYAID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8821C) \ + << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) +#define BITS_WMAC_MU_BF_MYAID_8821C \ + (BIT_MASK_WMAC_MU_BF_MYAID_8821C << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BF_MYAID_8821C)) +#define BIT_GET_WMAC_MU_BF_MYAID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) & \ + BIT_MASK_WMAC_MU_BF_MYAID_8821C) +#define BIT_SET_WMAC_MU_BF_MYAID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x) | BIT_WMAC_MU_BF_MYAID_8821C(v)) + +/* 2 REG_WMAC_MU_BFRPT_PARA_8821C */ #define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C 12 #define BIT_MASK_BFRPT_PARA_USERID_SEL_8821C 0x7 -#define BIT_BFRPT_PARA_USERID_SEL_8821C(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) -#define BIT_GET_BFRPT_PARA_USERID_SEL_8821C(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) - - +#define BIT_BFRPT_PARA_USERID_SEL_8821C(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) +#define BITS_BFRPT_PARA_USERID_SEL_8821C \ + (BIT_MASK_BFRPT_PARA_USERID_SEL_8821C \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8821C(x) \ + ((x) & (~BITS_BFRPT_PARA_USERID_SEL_8821C)) +#define BIT_GET_BFRPT_PARA_USERID_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) +#define BIT_SET_BFRPT_PARA_USERID_SEL_8821C(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL_8821C(x) | \ + BIT_BFRPT_PARA_USERID_SEL_8821C(v)) #define BIT_SHIFT_BFRPT_PARA_8821C 0 #define BIT_MASK_BFRPT_PARA_8821C 0xfff -#define BIT_BFRPT_PARA_8821C(x) (((x) & BIT_MASK_BFRPT_PARA_8821C) << BIT_SHIFT_BFRPT_PARA_8821C) -#define BIT_GET_BFRPT_PARA_8821C(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8821C) & BIT_MASK_BFRPT_PARA_8821C) - - +#define BIT_BFRPT_PARA_8821C(x) \ + (((x) & BIT_MASK_BFRPT_PARA_8821C) << BIT_SHIFT_BFRPT_PARA_8821C) +#define BITS_BFRPT_PARA_8821C \ + (BIT_MASK_BFRPT_PARA_8821C << BIT_SHIFT_BFRPT_PARA_8821C) +#define BIT_CLEAR_BFRPT_PARA_8821C(x) ((x) & (~BITS_BFRPT_PARA_8821C)) +#define BIT_GET_BFRPT_PARA_8821C(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_8821C) & BIT_MASK_BFRPT_PARA_8821C) +#define BIT_SET_BFRPT_PARA_8821C(x, v) \ + (BIT_CLEAR_BFRPT_PARA_8821C(x) | BIT_BFRPT_PARA_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C */ #define BIT_STATUS_BFEE2_8821C BIT(10) @@ -10108,10 +16786,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE2_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE2_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE2_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C) - - +#define BIT_WMAC_MU_BFEE2_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) +#define BITS_WMAC_MU_BFEE2_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE2_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE2_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE2_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE2_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE2_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID_8821C(x) | BIT_WMAC_MU_BFEE2_AID_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C */ #define BIT_STATUS_BFEE3_8821C BIT(10) @@ -10119,10 +16805,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE3_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE3_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE3_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C) - - +#define BIT_WMAC_MU_BFEE3_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) +#define BITS_WMAC_MU_BFEE3_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE3_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE3_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE3_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE3_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE3_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID_8821C(x) | BIT_WMAC_MU_BFEE3_AID_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C */ #define BIT_STATUS_BFEE4_8821C BIT(10) @@ -10130,10 +16824,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE4_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE4_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE4_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C) - - +#define BIT_WMAC_MU_BFEE4_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) +#define BITS_WMAC_MU_BFEE4_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE4_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE4_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE4_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE4_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE4_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID_8821C(x) | BIT_WMAC_MU_BFEE4_AID_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C */ #define BIT_BIT_STATUS_BFEE5_8821C BIT(10) @@ -10141,10 +16843,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE5_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE5_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE5_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C) - - +#define BIT_WMAC_MU_BFEE5_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) +#define BITS_WMAC_MU_BFEE5_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE5_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE5_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE5_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE5_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE5_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID_8821C(x) | BIT_WMAC_MU_BFEE5_AID_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C */ #define BIT_STATUS_BFEE6_8821C BIT(10) @@ -10152,124 +16862,319 @@ #define BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE6_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE6_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE6_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C) - - +#define BIT_WMAC_MU_BFEE6_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) +#define BITS_WMAC_MU_BFEE6_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE6_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE6_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE6_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE6_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE6_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID_8821C(x) | BIT_WMAC_MU_BFEE6_AID_8821C(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C */ -#define BIT_BIT_STATUS_BFEE4_8821C BIT(10) +#define BIT_STATUS_BFEE7_8821C BIT(10) #define BIT_WMAC_MU_BFEE7_EN_8821C BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C 0 #define BIT_MASK_WMAC_MU_BFEE7_AID_8821C 0x1ff -#define BIT_WMAC_MU_BFEE7_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) -#define BIT_GET_WMAC_MU_BFEE7_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C) - - +#define BIT_WMAC_MU_BFEE7_AID_8821C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C) \ + << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) +#define BITS_WMAC_MU_BFEE7_AID_8821C \ + (BIT_MASK_WMAC_MU_BFEE7_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8821C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE7_AID_8821C)) +#define BIT_GET_WMAC_MU_BFEE7_AID_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) & \ + BIT_MASK_WMAC_MU_BFEE7_AID_8821C) +#define BIT_SET_WMAC_MU_BFEE7_AID_8821C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID_8821C(x) | BIT_WMAC_MU_BFEE7_AID_8821C(v)) /* 2 REG_WMAC_BB_STOP_RX_COUNTER_8821C */ #define BIT_RST_ALL_COUNTER_8821C BIT(31) #define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C 16 #define BIT_MASK_ABORT_RX_VBON_COUNTER_8821C 0xff -#define BIT_ABORT_RX_VBON_COUNTER_8821C(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) -#define BIT_GET_ABORT_RX_VBON_COUNTER_8821C(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) - - +#define BIT_ABORT_RX_VBON_COUNTER_8821C(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) +#define BITS_ABORT_RX_VBON_COUNTER_8821C \ + (BIT_MASK_ABORT_RX_VBON_COUNTER_8821C \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8821C(x) \ + ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8821C)) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8821C(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) +#define BIT_SET_ABORT_RX_VBON_COUNTER_8821C(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8821C(x) | \ + BIT_ABORT_RX_VBON_COUNTER_8821C(v)) #define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C 8 #define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C 0xff -#define BIT_ABORT_RX_RDRDY_COUNTER_8821C(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) -#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8821C(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) - - +#define BIT_ABORT_RX_RDRDY_COUNTER_8821C(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) +#define BITS_ABORT_RX_RDRDY_COUNTER_8821C \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8821C(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8821C)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8821C(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8821C(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8821C(x) | \ + BIT_ABORT_RX_RDRDY_COUNTER_8821C(v)) #define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C 0 #define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C 0xff -#define BIT_VBON_EARLY_FALLING_COUNTER_8821C(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) -#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8821C(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) - - +#define BIT_VBON_EARLY_FALLING_COUNTER_8821C(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) +#define BITS_VBON_EARLY_FALLING_COUNTER_8821C \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8821C(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8821C)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8821C(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8821C(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8821C(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER_8821C(v)) /* 2 REG_WMAC_PLCP_MONITOR_8821C */ #define BIT_WMAC_PLCP_TRX_SEL_8821C BIT(31) #define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C 28 #define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C 0x7 -#define BIT_WMAC_PLCP_RDSIG_SEL_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) -#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) - - +#define BIT_WMAC_PLCP_RDSIG_SEL_8821C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) +#define BITS_WMAC_PLCP_RDSIG_SEL_8821C \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8821C(x) \ + ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8821C)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8821C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8821C(x) | \ + BIT_WMAC_PLCP_RDSIG_SEL_8821C(v)) #define BIT_SHIFT_WMAC_RATE_IDX_8821C 24 #define BIT_MASK_WMAC_RATE_IDX_8821C 0xf -#define BIT_WMAC_RATE_IDX_8821C(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8821C) << BIT_SHIFT_WMAC_RATE_IDX_8821C) -#define BIT_GET_WMAC_RATE_IDX_8821C(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8821C) & BIT_MASK_WMAC_RATE_IDX_8821C) - - +#define BIT_WMAC_RATE_IDX_8821C(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX_8821C) << BIT_SHIFT_WMAC_RATE_IDX_8821C) +#define BITS_WMAC_RATE_IDX_8821C \ + (BIT_MASK_WMAC_RATE_IDX_8821C << BIT_SHIFT_WMAC_RATE_IDX_8821C) +#define BIT_CLEAR_WMAC_RATE_IDX_8821C(x) ((x) & (~BITS_WMAC_RATE_IDX_8821C)) +#define BIT_GET_WMAC_RATE_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8821C) & BIT_MASK_WMAC_RATE_IDX_8821C) +#define BIT_SET_WMAC_RATE_IDX_8821C(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX_8821C(x) | BIT_WMAC_RATE_IDX_8821C(v)) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) -#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) - - +#define BIT_WMAC_PLCP_RDSIG_8821C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BITS_WMAC_PLCP_RDSIG_8821C \ + (BIT_MASK_WMAC_PLCP_RDSIG_8821C << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8821C)) +#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8821C) +#define BIT_SET_WMAC_PLCP_RDSIG_8821C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) | BIT_WMAC_PLCP_RDSIG_8821C(v)) /* 2 REG_WMAC_PLCP_MONITOR_MUTX_8821C */ #define BIT_WMAC_MUTX_IDX_8821C BIT(24) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) -#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) - +#define BIT_WMAC_PLCP_RDSIG_8821C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BITS_WMAC_PLCP_RDSIG_8821C \ + (BIT_MASK_WMAC_PLCP_RDSIG_8821C << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8821C)) +#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8821C) +#define BIT_SET_WMAC_PLCP_RDSIG_8821C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) | BIT_WMAC_PLCP_RDSIG_8821C(v)) +/* 2 REG_RSVD_8821C */ /* 2 REG_TRANSMIT_ADDRSS_0_8821C (TA0 REGISTER) */ -#define BIT_SHIFT_TA0_8821C 0 -#define BIT_MASK_TA0_8821C 0xffffffffffffL -#define BIT_TA0_8821C(x) (((x) & BIT_MASK_TA0_8821C) << BIT_SHIFT_TA0_8821C) -#define BIT_GET_TA0_8821C(x) (((x) >> BIT_SHIFT_TA0_8821C) & BIT_MASK_TA0_8821C) +#define BIT_SHIFT_TA0_V1_8821C 0 +#define BIT_MASK_TA0_V1_8821C 0xffffffffL +#define BIT_TA0_V1_8821C(x) \ + (((x) & BIT_MASK_TA0_V1_8821C) << BIT_SHIFT_TA0_V1_8821C) +#define BITS_TA0_V1_8821C (BIT_MASK_TA0_V1_8821C << BIT_SHIFT_TA0_V1_8821C) +#define BIT_CLEAR_TA0_V1_8821C(x) ((x) & (~BITS_TA0_V1_8821C)) +#define BIT_GET_TA0_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA0_V1_8821C) & BIT_MASK_TA0_V1_8821C) +#define BIT_SET_TA0_V1_8821C(x, v) \ + (BIT_CLEAR_TA0_V1_8821C(x) | BIT_TA0_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_0_H_8821C (TA0 REGISTER) */ + +#define BIT_SHIFT_TA0_H_V1_8821C 0 +#define BIT_MASK_TA0_H_V1_8821C 0xffff +#define BIT_TA0_H_V1_8821C(x) \ + (((x) & BIT_MASK_TA0_H_V1_8821C) << BIT_SHIFT_TA0_H_V1_8821C) +#define BITS_TA0_H_V1_8821C \ + (BIT_MASK_TA0_H_V1_8821C << BIT_SHIFT_TA0_H_V1_8821C) +#define BIT_CLEAR_TA0_H_V1_8821C(x) ((x) & (~BITS_TA0_H_V1_8821C)) +#define BIT_GET_TA0_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA0_H_V1_8821C) & BIT_MASK_TA0_H_V1_8821C) +#define BIT_SET_TA0_H_V1_8821C(x, v) \ + (BIT_CLEAR_TA0_H_V1_8821C(x) | BIT_TA0_H_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_1_8821C (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_V1_8821C 0 +#define BIT_MASK_TA1_V1_8821C 0xffffffffL +#define BIT_TA1_V1_8821C(x) \ + (((x) & BIT_MASK_TA1_V1_8821C) << BIT_SHIFT_TA1_V1_8821C) +#define BITS_TA1_V1_8821C (BIT_MASK_TA1_V1_8821C << BIT_SHIFT_TA1_V1_8821C) +#define BIT_CLEAR_TA1_V1_8821C(x) ((x) & (~BITS_TA1_V1_8821C)) +#define BIT_GET_TA1_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA1_V1_8821C) & BIT_MASK_TA1_V1_8821C) +#define BIT_SET_TA1_V1_8821C(x, v) \ + (BIT_CLEAR_TA1_V1_8821C(x) | BIT_TA1_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_1_H_8821C (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_H_V1_8821C 0 +#define BIT_MASK_TA1_H_V1_8821C 0xffff +#define BIT_TA1_H_V1_8821C(x) \ + (((x) & BIT_MASK_TA1_H_V1_8821C) << BIT_SHIFT_TA1_H_V1_8821C) +#define BITS_TA1_H_V1_8821C \ + (BIT_MASK_TA1_H_V1_8821C << BIT_SHIFT_TA1_H_V1_8821C) +#define BIT_CLEAR_TA1_H_V1_8821C(x) ((x) & (~BITS_TA1_H_V1_8821C)) +#define BIT_GET_TA1_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA1_H_V1_8821C) & BIT_MASK_TA1_H_V1_8821C) +#define BIT_SET_TA1_H_V1_8821C(x, v) \ + (BIT_CLEAR_TA1_H_V1_8821C(x) | BIT_TA1_H_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_2_8821C (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_V1_8821C 0 +#define BIT_MASK_TA2_V1_8821C 0xffffffffL +#define BIT_TA2_V1_8821C(x) \ + (((x) & BIT_MASK_TA2_V1_8821C) << BIT_SHIFT_TA2_V1_8821C) +#define BITS_TA2_V1_8821C (BIT_MASK_TA2_V1_8821C << BIT_SHIFT_TA2_V1_8821C) +#define BIT_CLEAR_TA2_V1_8821C(x) ((x) & (~BITS_TA2_V1_8821C)) +#define BIT_GET_TA2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8821C) & BIT_MASK_TA2_V1_8821C) +#define BIT_SET_TA2_V1_8821C(x, v) \ + (BIT_CLEAR_TA2_V1_8821C(x) | BIT_TA2_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_2_H_8821C (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_H_V1_8821C 0 +#define BIT_MASK_TA2_H_V1_8821C 0xffff +#define BIT_TA2_H_V1_8821C(x) \ + (((x) & BIT_MASK_TA2_H_V1_8821C) << BIT_SHIFT_TA2_H_V1_8821C) +#define BITS_TA2_H_V1_8821C \ + (BIT_MASK_TA2_H_V1_8821C << BIT_SHIFT_TA2_H_V1_8821C) +#define BIT_CLEAR_TA2_H_V1_8821C(x) ((x) & (~BITS_TA2_H_V1_8821C)) +#define BIT_GET_TA2_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA2_H_V1_8821C) & BIT_MASK_TA2_H_V1_8821C) +#define BIT_SET_TA2_H_V1_8821C(x, v) \ + (BIT_CLEAR_TA2_H_V1_8821C(x) | BIT_TA2_H_V1_8821C(v)) +/* 2 REG_TRANSMIT_ADDRSS_3_8821C (TA3 REGISTER) */ +#define BIT_SHIFT_TA2_V1_8821C 0 +#define BIT_MASK_TA2_V1_8821C 0xffffffffL +#define BIT_TA2_V1_8821C(x) \ + (((x) & BIT_MASK_TA2_V1_8821C) << BIT_SHIFT_TA2_V1_8821C) +#define BITS_TA2_V1_8821C (BIT_MASK_TA2_V1_8821C << BIT_SHIFT_TA2_V1_8821C) +#define BIT_CLEAR_TA2_V1_8821C(x) ((x) & (~BITS_TA2_V1_8821C)) +#define BIT_GET_TA2_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8821C) & BIT_MASK_TA2_V1_8821C) +#define BIT_SET_TA2_V1_8821C(x, v) \ + (BIT_CLEAR_TA2_V1_8821C(x) | BIT_TA2_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_3_H_8821C (TA3 REGISTER) */ + +#define BIT_SHIFT_TA3_H_V1_8821C 0 +#define BIT_MASK_TA3_H_V1_8821C 0xffff +#define BIT_TA3_H_V1_8821C(x) \ + (((x) & BIT_MASK_TA3_H_V1_8821C) << BIT_SHIFT_TA3_H_V1_8821C) +#define BITS_TA3_H_V1_8821C \ + (BIT_MASK_TA3_H_V1_8821C << BIT_SHIFT_TA3_H_V1_8821C) +#define BIT_CLEAR_TA3_H_V1_8821C(x) ((x) & (~BITS_TA3_H_V1_8821C)) +#define BIT_GET_TA3_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA3_H_V1_8821C) & BIT_MASK_TA3_H_V1_8821C) +#define BIT_SET_TA3_H_V1_8821C(x, v) \ + (BIT_CLEAR_TA3_H_V1_8821C(x) | BIT_TA3_H_V1_8821C(v)) -/* 2 REG_TRANSMIT_ADDRSS_1_8821C (TA1 REGISTER) */ +/* 2 REG_TRANSMIT_ADDRSS_4_8821C (TA4 REGISTER) */ -#define BIT_SHIFT_TA1_8821C 0 -#define BIT_MASK_TA1_8821C 0xffffffffffffL -#define BIT_TA1_8821C(x) (((x) & BIT_MASK_TA1_8821C) << BIT_SHIFT_TA1_8821C) -#define BIT_GET_TA1_8821C(x) (((x) >> BIT_SHIFT_TA1_8821C) & BIT_MASK_TA1_8821C) +#define BIT_SHIFT_TA4_V1_8821C 0 +#define BIT_MASK_TA4_V1_8821C 0xffffffffL +#define BIT_TA4_V1_8821C(x) \ + (((x) & BIT_MASK_TA4_V1_8821C) << BIT_SHIFT_TA4_V1_8821C) +#define BITS_TA4_V1_8821C (BIT_MASK_TA4_V1_8821C << BIT_SHIFT_TA4_V1_8821C) +#define BIT_CLEAR_TA4_V1_8821C(x) ((x) & (~BITS_TA4_V1_8821C)) +#define BIT_GET_TA4_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA4_V1_8821C) & BIT_MASK_TA4_V1_8821C) +#define BIT_SET_TA4_V1_8821C(x, v) \ + (BIT_CLEAR_TA4_V1_8821C(x) | BIT_TA4_V1_8821C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_4_H_8821C (TA4 REGISTER) */ + +#define BIT_SHIFT_TA4_H_V1_8821C 0 +#define BIT_MASK_TA4_H_V1_8821C 0xffff +#define BIT_TA4_H_V1_8821C(x) \ + (((x) & BIT_MASK_TA4_H_V1_8821C) << BIT_SHIFT_TA4_H_V1_8821C) +#define BITS_TA4_H_V1_8821C \ + (BIT_MASK_TA4_H_V1_8821C << BIT_SHIFT_TA4_H_V1_8821C) +#define BIT_CLEAR_TA4_H_V1_8821C(x) ((x) & (~BITS_TA4_H_V1_8821C)) +#define BIT_GET_TA4_H_V1_8821C(x) \ + (((x) >> BIT_SHIFT_TA4_H_V1_8821C) & BIT_MASK_TA4_H_V1_8821C) +#define BIT_SET_TA4_H_V1_8821C(x, v) \ + (BIT_CLEAR_TA4_H_V1_8821C(x) | BIT_TA4_H_V1_8821C(v)) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ -/* 2 REG_TRANSMIT_ADDRSS_2_8821C (TA2 REGISTER) */ +/* 2 REG_RSVD_8821C */ -#define BIT_SHIFT_TA2_8821C 0 -#define BIT_MASK_TA2_8821C 0xffffffffffffL -#define BIT_TA2_8821C(x) (((x) & BIT_MASK_TA2_8821C) << BIT_SHIFT_TA2_8821C) -#define BIT_GET_TA2_8821C(x) (((x) >> BIT_SHIFT_TA2_8821C) & BIT_MASK_TA2_8821C) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ -/* 2 REG_TRANSMIT_ADDRSS_3_8821C (TA3 REGISTER) */ +/* 2 REG_RSVD_8821C */ -#define BIT_SHIFT_TA3_8821C 0 -#define BIT_MASK_TA3_8821C 0xffffffffffffL -#define BIT_TA3_8821C(x) (((x) & BIT_MASK_TA3_8821C) << BIT_SHIFT_TA3_8821C) -#define BIT_GET_TA3_8821C(x) (((x) >> BIT_SHIFT_TA3_8821C) & BIT_MASK_TA3_8821C) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ -/* 2 REG_TRANSMIT_ADDRSS_4_8821C (TA4 REGISTER) */ +/* 2 REG_RSVD_8821C */ -#define BIT_SHIFT_TA4_8821C 0 -#define BIT_MASK_TA4_8821C 0xffffffffffffL -#define BIT_TA4_8821C(x) (((x) & BIT_MASK_TA4_8821C) << BIT_SHIFT_TA4_8821C) -#define BIT_GET_TA4_8821C(x) (((x) >> BIT_SHIFT_TA4_8821C) & BIT_MASK_TA4_8821C) +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ +/* 2 REG_RSVD_8821C */ /* 2 REG_NOT_VALID_8821C */ @@ -10277,62 +17182,98 @@ #define BIT_SHIFT_MACID1_0_8821C 0 #define BIT_MASK_MACID1_0_8821C 0xffffffffL -#define BIT_MACID1_0_8821C(x) (((x) & BIT_MASK_MACID1_0_8821C) << BIT_SHIFT_MACID1_0_8821C) -#define BIT_GET_MACID1_0_8821C(x) (((x) >> BIT_SHIFT_MACID1_0_8821C) & BIT_MASK_MACID1_0_8821C) - - +#define BIT_MACID1_0_8821C(x) \ + (((x) & BIT_MASK_MACID1_0_8821C) << BIT_SHIFT_MACID1_0_8821C) +#define BITS_MACID1_0_8821C \ + (BIT_MASK_MACID1_0_8821C << BIT_SHIFT_MACID1_0_8821C) +#define BIT_CLEAR_MACID1_0_8821C(x) ((x) & (~BITS_MACID1_0_8821C)) +#define BIT_GET_MACID1_0_8821C(x) \ + (((x) >> BIT_SHIFT_MACID1_0_8821C) & BIT_MASK_MACID1_0_8821C) +#define BIT_SET_MACID1_0_8821C(x, v) \ + (BIT_CLEAR_MACID1_0_8821C(x) | BIT_MACID1_0_8821C(v)) /* 2 REG_MACID1_1_8821C */ #define BIT_SHIFT_MACID1_1_8821C 0 #define BIT_MASK_MACID1_1_8821C 0xffff -#define BIT_MACID1_1_8821C(x) (((x) & BIT_MASK_MACID1_1_8821C) << BIT_SHIFT_MACID1_1_8821C) -#define BIT_GET_MACID1_1_8821C(x) (((x) >> BIT_SHIFT_MACID1_1_8821C) & BIT_MASK_MACID1_1_8821C) - - +#define BIT_MACID1_1_8821C(x) \ + (((x) & BIT_MASK_MACID1_1_8821C) << BIT_SHIFT_MACID1_1_8821C) +#define BITS_MACID1_1_8821C \ + (BIT_MASK_MACID1_1_8821C << BIT_SHIFT_MACID1_1_8821C) +#define BIT_CLEAR_MACID1_1_8821C(x) ((x) & (~BITS_MACID1_1_8821C)) +#define BIT_GET_MACID1_1_8821C(x) \ + (((x) >> BIT_SHIFT_MACID1_1_8821C) & BIT_MASK_MACID1_1_8821C) +#define BIT_SET_MACID1_1_8821C(x, v) \ + (BIT_CLEAR_MACID1_1_8821C(x) | BIT_MACID1_1_8821C(v)) /* 2 REG_BSSID1_8821C */ #define BIT_SHIFT_BSSID1_0_8821C 0 #define BIT_MASK_BSSID1_0_8821C 0xffffffffL -#define BIT_BSSID1_0_8821C(x) (((x) & BIT_MASK_BSSID1_0_8821C) << BIT_SHIFT_BSSID1_0_8821C) -#define BIT_GET_BSSID1_0_8821C(x) (((x) >> BIT_SHIFT_BSSID1_0_8821C) & BIT_MASK_BSSID1_0_8821C) - - +#define BIT_BSSID1_0_8821C(x) \ + (((x) & BIT_MASK_BSSID1_0_8821C) << BIT_SHIFT_BSSID1_0_8821C) +#define BITS_BSSID1_0_8821C \ + (BIT_MASK_BSSID1_0_8821C << BIT_SHIFT_BSSID1_0_8821C) +#define BIT_CLEAR_BSSID1_0_8821C(x) ((x) & (~BITS_BSSID1_0_8821C)) +#define BIT_GET_BSSID1_0_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID1_0_8821C) & BIT_MASK_BSSID1_0_8821C) +#define BIT_SET_BSSID1_0_8821C(x, v) \ + (BIT_CLEAR_BSSID1_0_8821C(x) | BIT_BSSID1_0_8821C(v)) /* 2 REG_BSSID1_1_8821C */ #define BIT_SHIFT_BSSID1_1_8821C 0 #define BIT_MASK_BSSID1_1_8821C 0xffff -#define BIT_BSSID1_1_8821C(x) (((x) & BIT_MASK_BSSID1_1_8821C) << BIT_SHIFT_BSSID1_1_8821C) -#define BIT_GET_BSSID1_1_8821C(x) (((x) >> BIT_SHIFT_BSSID1_1_8821C) & BIT_MASK_BSSID1_1_8821C) - - +#define BIT_BSSID1_1_8821C(x) \ + (((x) & BIT_MASK_BSSID1_1_8821C) << BIT_SHIFT_BSSID1_1_8821C) +#define BITS_BSSID1_1_8821C \ + (BIT_MASK_BSSID1_1_8821C << BIT_SHIFT_BSSID1_1_8821C) +#define BIT_CLEAR_BSSID1_1_8821C(x) ((x) & (~BITS_BSSID1_1_8821C)) +#define BIT_GET_BSSID1_1_8821C(x) \ + (((x) >> BIT_SHIFT_BSSID1_1_8821C) & BIT_MASK_BSSID1_1_8821C) +#define BIT_SET_BSSID1_1_8821C(x, v) \ + (BIT_CLEAR_BSSID1_1_8821C(x) | BIT_BSSID1_1_8821C(v)) /* 2 REG_BCN_PSR_RPT1_8821C */ #define BIT_SHIFT_DTIM_CNT1_8821C 24 #define BIT_MASK_DTIM_CNT1_8821C 0xff -#define BIT_DTIM_CNT1_8821C(x) (((x) & BIT_MASK_DTIM_CNT1_8821C) << BIT_SHIFT_DTIM_CNT1_8821C) -#define BIT_GET_DTIM_CNT1_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8821C) & BIT_MASK_DTIM_CNT1_8821C) - - +#define BIT_DTIM_CNT1_8821C(x) \ + (((x) & BIT_MASK_DTIM_CNT1_8821C) << BIT_SHIFT_DTIM_CNT1_8821C) +#define BITS_DTIM_CNT1_8821C \ + (BIT_MASK_DTIM_CNT1_8821C << BIT_SHIFT_DTIM_CNT1_8821C) +#define BIT_CLEAR_DTIM_CNT1_8821C(x) ((x) & (~BITS_DTIM_CNT1_8821C)) +#define BIT_GET_DTIM_CNT1_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT1_8821C) & BIT_MASK_DTIM_CNT1_8821C) +#define BIT_SET_DTIM_CNT1_8821C(x, v) \ + (BIT_CLEAR_DTIM_CNT1_8821C(x) | BIT_DTIM_CNT1_8821C(v)) #define BIT_SHIFT_DTIM_PERIOD1_8821C 16 #define BIT_MASK_DTIM_PERIOD1_8821C 0xff -#define BIT_DTIM_PERIOD1_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD1_8821C) << BIT_SHIFT_DTIM_PERIOD1_8821C) -#define BIT_GET_DTIM_PERIOD1_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8821C) & BIT_MASK_DTIM_PERIOD1_8821C) - +#define BIT_DTIM_PERIOD1_8821C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1_8821C) << BIT_SHIFT_DTIM_PERIOD1_8821C) +#define BITS_DTIM_PERIOD1_8821C \ + (BIT_MASK_DTIM_PERIOD1_8821C << BIT_SHIFT_DTIM_PERIOD1_8821C) +#define BIT_CLEAR_DTIM_PERIOD1_8821C(x) ((x) & (~BITS_DTIM_PERIOD1_8821C)) +#define BIT_GET_DTIM_PERIOD1_8821C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1_8821C) & BIT_MASK_DTIM_PERIOD1_8821C) +#define BIT_SET_DTIM_PERIOD1_8821C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1_8821C(x) | BIT_DTIM_PERIOD1_8821C(v)) #define BIT_DTIM1_8821C BIT(15) #define BIT_TIM1_8821C BIT(14) #define BIT_SHIFT_PS_AID_1_8821C 0 #define BIT_MASK_PS_AID_1_8821C 0x7ff -#define BIT_PS_AID_1_8821C(x) (((x) & BIT_MASK_PS_AID_1_8821C) << BIT_SHIFT_PS_AID_1_8821C) -#define BIT_GET_PS_AID_1_8821C(x) (((x) >> BIT_SHIFT_PS_AID_1_8821C) & BIT_MASK_PS_AID_1_8821C) - - +#define BIT_PS_AID_1_8821C(x) \ + (((x) & BIT_MASK_PS_AID_1_8821C) << BIT_SHIFT_PS_AID_1_8821C) +#define BITS_PS_AID_1_8821C \ + (BIT_MASK_PS_AID_1_8821C << BIT_SHIFT_PS_AID_1_8821C) +#define BIT_CLEAR_PS_AID_1_8821C(x) ((x) & (~BITS_PS_AID_1_8821C)) +#define BIT_GET_PS_AID_1_8821C(x) \ + (((x) >> BIT_SHIFT_PS_AID_1_8821C) & BIT_MASK_PS_AID_1_8821C) +#define BIT_SET_PS_AID_1_8821C(x, v) \ + (BIT_CLEAR_PS_AID_1_8821C(x) | BIT_PS_AID_1_8821C(v)) /* 2 REG_ASSOCIATED_BFMEE_SEL_8821C */ #define BIT_TXUSER_ID1_8821C BIT(25) @@ -10340,39 +17281,73 @@ #define BIT_SHIFT_AID1_8821C 16 #define BIT_MASK_AID1_8821C 0x1ff #define BIT_AID1_8821C(x) (((x) & BIT_MASK_AID1_8821C) << BIT_SHIFT_AID1_8821C) -#define BIT_GET_AID1_8821C(x) (((x) >> BIT_SHIFT_AID1_8821C) & BIT_MASK_AID1_8821C) - +#define BITS_AID1_8821C (BIT_MASK_AID1_8821C << BIT_SHIFT_AID1_8821C) +#define BIT_CLEAR_AID1_8821C(x) ((x) & (~BITS_AID1_8821C)) +#define BIT_GET_AID1_8821C(x) \ + (((x) >> BIT_SHIFT_AID1_8821C) & BIT_MASK_AID1_8821C) +#define BIT_SET_AID1_8821C(x, v) (BIT_CLEAR_AID1_8821C(x) | BIT_AID1_8821C(v)) #define BIT_TXUSER_ID0_8821C BIT(9) #define BIT_SHIFT_AID0_8821C 0 #define BIT_MASK_AID0_8821C 0x1ff #define BIT_AID0_8821C(x) (((x) & BIT_MASK_AID0_8821C) << BIT_SHIFT_AID0_8821C) -#define BIT_GET_AID0_8821C(x) (((x) >> BIT_SHIFT_AID0_8821C) & BIT_MASK_AID0_8821C) - - +#define BITS_AID0_8821C (BIT_MASK_AID0_8821C << BIT_SHIFT_AID0_8821C) +#define BIT_CLEAR_AID0_8821C(x) ((x) & (~BITS_AID0_8821C)) +#define BIT_GET_AID0_8821C(x) \ + (((x) >> BIT_SHIFT_AID0_8821C) & BIT_MASK_AID0_8821C) +#define BIT_SET_AID0_8821C(x, v) (BIT_CLEAR_AID0_8821C(x) | BIT_AID0_8821C(v)) /* 2 REG_SND_PTCL_CTRL_8821C */ #define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C 24 #define BIT_MASK_NDP_RX_STANDBY_TIMER_8821C 0xff -#define BIT_NDP_RX_STANDBY_TIMER_8821C(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) -#define BIT_GET_NDP_RX_STANDBY_TIMER_8821C(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) - - +#define BIT_NDP_RX_STANDBY_TIMER_8821C(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) +#define BITS_NDP_RX_STANDBY_TIMER_8821C \ + (BIT_MASK_NDP_RX_STANDBY_TIMER_8821C \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8821C(x) \ + ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8821C)) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) +#define BIT_SET_NDP_RX_STANDBY_TIMER_8821C(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8821C(x) | \ + BIT_NDP_RX_STANDBY_TIMER_8821C(v)) #define BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C 16 #define BIT_MASK_CSI_RPT_OFFSET_HT_8821C 0xff -#define BIT_CSI_RPT_OFFSET_HT_8821C(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) -#define BIT_GET_CSI_RPT_OFFSET_HT_8821C(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) - - +#define BIT_CSI_RPT_OFFSET_HT_8821C(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) +#define BITS_CSI_RPT_OFFSET_HT_8821C \ + (BIT_MASK_CSI_RPT_OFFSET_HT_8821C << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8821C(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_HT_8821C)) +#define BIT_GET_CSI_RPT_OFFSET_HT_8821C(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_8821C) +#define BIT_SET_CSI_RPT_OFFSET_HT_8821C(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_8821C(x) | BIT_CSI_RPT_OFFSET_HT_8821C(v)) #define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C 8 #define BIT_MASK_R_WMAC_VHT_CATEGORY_8821C 0xff -#define BIT_R_WMAC_VHT_CATEGORY_8821C(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) -#define BIT_GET_R_WMAC_VHT_CATEGORY_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) - +#define BIT_R_WMAC_VHT_CATEGORY_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) \ + << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) +#define BITS_R_WMAC_VHT_CATEGORY_8821C \ + (BIT_MASK_R_WMAC_VHT_CATEGORY_8821C \ + << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) +#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_8821C(x) \ + ((x) & (~BITS_R_WMAC_VHT_CATEGORY_8821C)) +#define BIT_GET_R_WMAC_VHT_CATEGORY_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) & \ + BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) +#define BIT_SET_R_WMAC_VHT_CATEGORY_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_VHT_CATEGORY_8821C(x) | \ + BIT_R_WMAC_VHT_CATEGORY_8821C(v)) #define BIT_R_WMAC_USE_NSTS_8821C BIT(7) #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8821C BIT(6) @@ -10392,24 +17367,54 @@ #define BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C 6 #define BIT_MASK_R_WMAC_NSARP_MODEN_8821C 0x3 -#define BIT_R_WMAC_NSARP_MODEN_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) -#define BIT_GET_R_WMAC_NSARP_MODEN_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C) - - +#define BIT_R_WMAC_NSARP_MODEN_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C) \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) +#define BITS_R_WMAC_NSARP_MODEN_8821C \ + (BIT_MASK_R_WMAC_NSARP_MODEN_8821C \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8821C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_MODEN_8821C)) +#define BIT_GET_R_WMAC_NSARP_MODEN_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) & \ + BIT_MASK_R_WMAC_NSARP_MODEN_8821C) +#define BIT_SET_R_WMAC_NSARP_MODEN_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN_8821C(x) | \ + BIT_R_WMAC_NSARP_MODEN_8821C(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C 4 #define BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C 0x3 -#define BIT_R_WMAC_NSARP_RSPFTP_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) -#define BIT_GET_R_WMAC_NSARP_RSPFTP_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) - - +#define BIT_R_WMAC_NSARP_RSPFTP_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) +#define BITS_R_WMAC_NSARP_RSPFTP_8821C \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8821C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8821C)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) & \ + BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) +#define BIT_SET_R_WMAC_NSARP_RSPFTP_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8821C(x) | \ + BIT_R_WMAC_NSARP_RSPFTP_8821C(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C 0 #define BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C 0xf -#define BIT_R_WMAC_NSARP_RSPSEC_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) -#define BIT_GET_R_WMAC_NSARP_RSPSEC_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) - - +#define BIT_R_WMAC_NSARP_RSPSEC_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) +#define BITS_R_WMAC_NSARP_RSPSEC_8821C \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8821C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8821C)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) & \ + BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) +#define BIT_SET_R_WMAC_NSARP_RSPSEC_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8821C(x) | \ + BIT_R_WMAC_NSARP_RSPSEC_8821C(v)) /* 2 REG_NS_ARP_INFO_8821C */ #define BIT_REQ_IS_MCNS_8821C BIT(23) @@ -10420,78 +17425,158 @@ #define BIT_SHIFT_EXPRSP_SECTYPE_8821C 16 #define BIT_MASK_EXPRSP_SECTYPE_8821C 0x7 -#define BIT_EXPRSP_SECTYPE_8821C(x) (((x) & BIT_MASK_EXPRSP_SECTYPE_8821C) << BIT_SHIFT_EXPRSP_SECTYPE_8821C) -#define BIT_GET_EXPRSP_SECTYPE_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8821C) & BIT_MASK_EXPRSP_SECTYPE_8821C) - - +#define BIT_EXPRSP_SECTYPE_8821C(x) \ + (((x) & BIT_MASK_EXPRSP_SECTYPE_8821C) \ + << BIT_SHIFT_EXPRSP_SECTYPE_8821C) +#define BITS_EXPRSP_SECTYPE_8821C \ + (BIT_MASK_EXPRSP_SECTYPE_8821C << BIT_SHIFT_EXPRSP_SECTYPE_8821C) +#define BIT_CLEAR_EXPRSP_SECTYPE_8821C(x) ((x) & (~BITS_EXPRSP_SECTYPE_8821C)) +#define BIT_GET_EXPRSP_SECTYPE_8821C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8821C) & \ + BIT_MASK_EXPRSP_SECTYPE_8821C) +#define BIT_SET_EXPRSP_SECTYPE_8821C(x, v) \ + (BIT_CLEAR_EXPRSP_SECTYPE_8821C(x) | BIT_EXPRSP_SECTYPE_8821C(v)) #define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C 8 #define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C 0xff -#define BIT_EXPRSP_CHKSM_7_TO_0_8821C(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) -#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) - - +#define BIT_EXPRSP_CHKSM_7_TO_0_8821C(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) +#define BITS_EXPRSP_CHKSM_7_TO_0_8821C \ + (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) +#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8821C(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8821C)) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8821C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) & \ + BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) +#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8821C(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8821C(x) | \ + BIT_EXPRSP_CHKSM_7_TO_0_8821C(v)) #define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C 0 #define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C 0xff -#define BIT_EXPRSP_CHKSM_15_TO_8_8821C(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) -#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) - - +#define BIT_EXPRSP_CHKSM_15_TO_8_8821C(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) +#define BITS_EXPRSP_CHKSM_15_TO_8_8821C \ + (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) +#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8821C(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8821C)) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8821C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) & \ + BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) +#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8821C(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8821C(x) | \ + BIT_EXPRSP_CHKSM_15_TO_8_8821C(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_V1_8821C */ #define BIT_SHIFT_WMAC_ARPIP_8821C 0 #define BIT_MASK_WMAC_ARPIP_8821C 0xffffffffL -#define BIT_WMAC_ARPIP_8821C(x) (((x) & BIT_MASK_WMAC_ARPIP_8821C) << BIT_SHIFT_WMAC_ARPIP_8821C) -#define BIT_GET_WMAC_ARPIP_8821C(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8821C) & BIT_MASK_WMAC_ARPIP_8821C) - - +#define BIT_WMAC_ARPIP_8821C(x) \ + (((x) & BIT_MASK_WMAC_ARPIP_8821C) << BIT_SHIFT_WMAC_ARPIP_8821C) +#define BITS_WMAC_ARPIP_8821C \ + (BIT_MASK_WMAC_ARPIP_8821C << BIT_SHIFT_WMAC_ARPIP_8821C) +#define BIT_CLEAR_WMAC_ARPIP_8821C(x) ((x) & (~BITS_WMAC_ARPIP_8821C)) +#define BIT_GET_WMAC_ARPIP_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_ARPIP_8821C) & BIT_MASK_WMAC_ARPIP_8821C) +#define BIT_SET_WMAC_ARPIP_8821C(x, v) \ + (BIT_CLEAR_WMAC_ARPIP_8821C(x) | BIT_WMAC_ARPIP_8821C(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_8821C */ #define BIT_SHIFT_BEAMFORMING_INFO_8821C 0 #define BIT_MASK_BEAMFORMING_INFO_8821C 0xffffffffL -#define BIT_BEAMFORMING_INFO_8821C(x) (((x) & BIT_MASK_BEAMFORMING_INFO_8821C) << BIT_SHIFT_BEAMFORMING_INFO_8821C) -#define BIT_GET_BEAMFORMING_INFO_8821C(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8821C) & BIT_MASK_BEAMFORMING_INFO_8821C) - - +#define BIT_BEAMFORMING_INFO_8821C(x) \ + (((x) & BIT_MASK_BEAMFORMING_INFO_8821C) \ + << BIT_SHIFT_BEAMFORMING_INFO_8821C) +#define BITS_BEAMFORMING_INFO_8821C \ + (BIT_MASK_BEAMFORMING_INFO_8821C << BIT_SHIFT_BEAMFORMING_INFO_8821C) +#define BIT_CLEAR_BEAMFORMING_INFO_8821C(x) \ + ((x) & (~BITS_BEAMFORMING_INFO_8821C)) +#define BIT_GET_BEAMFORMING_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8821C) & \ + BIT_MASK_BEAMFORMING_INFO_8821C) +#define BIT_SET_BEAMFORMING_INFO_8821C(x, v) \ + (BIT_CLEAR_BEAMFORMING_INFO_8821C(x) | BIT_BEAMFORMING_INFO_8821C(v)) /* 2 REG_IPV6_8821C */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_0_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) - - +#define BIT_R_WMAC_IPV6_MYIPAD_0_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) +#define BITS_R_WMAC_IPV6_MYIPAD_0_8821C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8821C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8821C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8821C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_0_8821C(v)) /* 2 REG_IPV6_1_8821C */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_1_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) - - +#define BIT_R_WMAC_IPV6_MYIPAD_1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) +#define BITS_R_WMAC_IPV6_MYIPAD_1_8821C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8821C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8821C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8821C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_1_8821C(v)) /* 2 REG_IPV6_2_8821C */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_2_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) - - +#define BIT_R_WMAC_IPV6_MYIPAD_2_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) +#define BITS_R_WMAC_IPV6_MYIPAD_2_8821C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8821C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8821C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8821C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_2_8821C(v)) /* 2 REG_IPV6_3_8821C */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C 0xffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_3_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) - - +#define BIT_R_WMAC_IPV6_MYIPAD_3_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) +#define BITS_R_WMAC_IPV6_MYIPAD_3_8821C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8821C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8821C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8821C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_3_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -10505,17 +17590,37 @@ #define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C 4 #define BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C 0xf -#define BIT_R_WMAC_CTX_SUBTYPE_8821C(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) -#define BIT_GET_R_WMAC_CTX_SUBTYPE_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) - - +#define BIT_R_WMAC_CTX_SUBTYPE_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) +#define BITS_R_WMAC_CTX_SUBTYPE_8821C \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8821C(x) \ + ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8821C)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) & \ + BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) +#define BIT_SET_R_WMAC_CTX_SUBTYPE_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8821C(x) | \ + BIT_R_WMAC_CTX_SUBTYPE_8821C(v)) #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C 0 #define BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C 0xf -#define BIT_R_WMAC_RTX_SUBTYPE_8821C(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) -#define BIT_GET_R_WMAC_RTX_SUBTYPE_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) - - +#define BIT_R_WMAC_RTX_SUBTYPE_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) +#define BITS_R_WMAC_RTX_SUBTYPE_8821C \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8821C(x) \ + ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8821C)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) & \ + BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) +#define BIT_SET_R_WMAC_RTX_SUBTYPE_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8821C(x) | \ + BIT_R_WMAC_RTX_SUBTYPE_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -10531,10 +17636,14 @@ #define BIT_SHIFT_TIMER_8821C 0 #define BIT_MASK_TIMER_8821C 0xff -#define BIT_TIMER_8821C(x) (((x) & BIT_MASK_TIMER_8821C) << BIT_SHIFT_TIMER_8821C) -#define BIT_GET_TIMER_8821C(x) (((x) >> BIT_SHIFT_TIMER_8821C) & BIT_MASK_TIMER_8821C) - - +#define BIT_TIMER_8821C(x) \ + (((x) & BIT_MASK_TIMER_8821C) << BIT_SHIFT_TIMER_8821C) +#define BITS_TIMER_8821C (BIT_MASK_TIMER_8821C << BIT_SHIFT_TIMER_8821C) +#define BIT_CLEAR_TIMER_8821C(x) ((x) & (~BITS_TIMER_8821C)) +#define BIT_GET_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_TIMER_8821C) & BIT_MASK_TIMER_8821C) +#define BIT_SET_TIMER_8821C(x, v) \ + (BIT_CLEAR_TIMER_8821C(x) | BIT_TIMER_8821C(v)) /* 2 REG_BT_COEX_8821C */ #define BIT_R_GNT_BT_RFC_SW_8821C BIT(12) @@ -10545,26 +17654,43 @@ #define BIT_SHIFT_R_BT_CNT_THR_8821C 0 #define BIT_MASK_R_BT_CNT_THR_8821C 0xff -#define BIT_R_BT_CNT_THR_8821C(x) (((x) & BIT_MASK_R_BT_CNT_THR_8821C) << BIT_SHIFT_R_BT_CNT_THR_8821C) -#define BIT_GET_R_BT_CNT_THR_8821C(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8821C) & BIT_MASK_R_BT_CNT_THR_8821C) - - +#define BIT_R_BT_CNT_THR_8821C(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR_8821C) << BIT_SHIFT_R_BT_CNT_THR_8821C) +#define BITS_R_BT_CNT_THR_8821C \ + (BIT_MASK_R_BT_CNT_THR_8821C << BIT_SHIFT_R_BT_CNT_THR_8821C) +#define BIT_CLEAR_R_BT_CNT_THR_8821C(x) ((x) & (~BITS_R_BT_CNT_THR_8821C)) +#define BIT_GET_R_BT_CNT_THR_8821C(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR_8821C) & BIT_MASK_R_BT_CNT_THR_8821C) +#define BIT_SET_R_BT_CNT_THR_8821C(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR_8821C(x) | BIT_R_BT_CNT_THR_8821C(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_8821C */ #define BIT_SHIFT_RXMYRTS_NAV_V1_8821C 8 #define BIT_MASK_RXMYRTS_NAV_V1_8821C 0xff -#define BIT_RXMYRTS_NAV_V1_8821C(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8821C) << BIT_SHIFT_RXMYRTS_NAV_V1_8821C) -#define BIT_GET_RXMYRTS_NAV_V1_8821C(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8821C) & BIT_MASK_RXMYRTS_NAV_V1_8821C) - - +#define BIT_RXMYRTS_NAV_V1_8821C(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1_8821C) \ + << BIT_SHIFT_RXMYRTS_NAV_V1_8821C) +#define BITS_RXMYRTS_NAV_V1_8821C \ + (BIT_MASK_RXMYRTS_NAV_V1_8821C << BIT_SHIFT_RXMYRTS_NAV_V1_8821C) +#define BIT_CLEAR_RXMYRTS_NAV_V1_8821C(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8821C)) +#define BIT_GET_RXMYRTS_NAV_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8821C) & \ + BIT_MASK_RXMYRTS_NAV_V1_8821C) +#define BIT_SET_RXMYRTS_NAV_V1_8821C(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1_8821C(x) | BIT_RXMYRTS_NAV_V1_8821C(v)) #define BIT_SHIFT_RTSRST_V1_8821C 0 #define BIT_MASK_RTSRST_V1_8821C 0xff -#define BIT_RTSRST_V1_8821C(x) (((x) & BIT_MASK_RTSRST_V1_8821C) << BIT_SHIFT_RTSRST_V1_8821C) -#define BIT_GET_RTSRST_V1_8821C(x) (((x) >> BIT_SHIFT_RTSRST_V1_8821C) & BIT_MASK_RTSRST_V1_8821C) - - +#define BIT_RTSRST_V1_8821C(x) \ + (((x) & BIT_MASK_RTSRST_V1_8821C) << BIT_SHIFT_RTSRST_V1_8821C) +#define BITS_RTSRST_V1_8821C \ + (BIT_MASK_RTSRST_V1_8821C << BIT_SHIFT_RTSRST_V1_8821C) +#define BIT_CLEAR_RTSRST_V1_8821C(x) ((x) & (~BITS_RTSRST_V1_8821C)) +#define BIT_GET_RTSRST_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RTSRST_V1_8821C) & BIT_MASK_RTSRST_V1_8821C) +#define BIT_SET_RTSRST_V1_8821C(x, v) \ + (BIT_CLEAR_RTSRST_V1_8821C(x) | BIT_RTSRST_V1_8821C(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_1_8821C */ #define BIT_WLRX_TER_BY_CTL_1_8821C BIT(11) @@ -10579,23 +17705,47 @@ #define BIT_SHIFT_BT_STAT_DELAY_8821C 12 #define BIT_MASK_BT_STAT_DELAY_8821C 0xf -#define BIT_BT_STAT_DELAY_8821C(x) (((x) & BIT_MASK_BT_STAT_DELAY_8821C) << BIT_SHIFT_BT_STAT_DELAY_8821C) -#define BIT_GET_BT_STAT_DELAY_8821C(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8821C) & BIT_MASK_BT_STAT_DELAY_8821C) - - +#define BIT_BT_STAT_DELAY_8821C(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY_8821C) << BIT_SHIFT_BT_STAT_DELAY_8821C) +#define BITS_BT_STAT_DELAY_8821C \ + (BIT_MASK_BT_STAT_DELAY_8821C << BIT_SHIFT_BT_STAT_DELAY_8821C) +#define BIT_CLEAR_BT_STAT_DELAY_8821C(x) ((x) & (~BITS_BT_STAT_DELAY_8821C)) +#define BIT_GET_BT_STAT_DELAY_8821C(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY_8821C) & BIT_MASK_BT_STAT_DELAY_8821C) +#define BIT_SET_BT_STAT_DELAY_8821C(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY_8821C(x) | BIT_BT_STAT_DELAY_8821C(v)) #define BIT_SHIFT_BT_TRX_INIT_DETECT_8821C 8 #define BIT_MASK_BT_TRX_INIT_DETECT_8821C 0xf -#define BIT_BT_TRX_INIT_DETECT_8821C(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) -#define BIT_GET_BT_TRX_INIT_DETECT_8821C(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) - - +#define BIT_BT_TRX_INIT_DETECT_8821C(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) +#define BITS_BT_TRX_INIT_DETECT_8821C \ + (BIT_MASK_BT_TRX_INIT_DETECT_8821C \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) +#define BIT_CLEAR_BT_TRX_INIT_DETECT_8821C(x) \ + ((x) & (~BITS_BT_TRX_INIT_DETECT_8821C)) +#define BIT_GET_BT_TRX_INIT_DETECT_8821C(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) & \ + BIT_MASK_BT_TRX_INIT_DETECT_8821C) +#define BIT_SET_BT_TRX_INIT_DETECT_8821C(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT_8821C(x) | \ + BIT_BT_TRX_INIT_DETECT_8821C(v)) #define BIT_SHIFT_BT_PRI_DETECT_TO_8821C 4 #define BIT_MASK_BT_PRI_DETECT_TO_8821C 0xf -#define BIT_BT_PRI_DETECT_TO_8821C(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8821C) << BIT_SHIFT_BT_PRI_DETECT_TO_8821C) -#define BIT_GET_BT_PRI_DETECT_TO_8821C(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8821C) & BIT_MASK_BT_PRI_DETECT_TO_8821C) - +#define BIT_BT_PRI_DETECT_TO_8821C(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO_8821C) \ + << BIT_SHIFT_BT_PRI_DETECT_TO_8821C) +#define BITS_BT_PRI_DETECT_TO_8821C \ + (BIT_MASK_BT_PRI_DETECT_TO_8821C << BIT_SHIFT_BT_PRI_DETECT_TO_8821C) +#define BIT_CLEAR_BT_PRI_DETECT_TO_8821C(x) \ + ((x) & (~BITS_BT_PRI_DETECT_TO_8821C)) +#define BIT_GET_BT_PRI_DETECT_TO_8821C(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8821C) & \ + BIT_MASK_BT_PRI_DETECT_TO_8821C) +#define BIT_SET_BT_PRI_DETECT_TO_8821C(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO_8821C(x) | BIT_BT_PRI_DETECT_TO_8821C(v)) #define BIT_R_GRANTALL_WLMASK_8821C BIT(3) #define BIT_STATIS_BT_EN_8821C BIT(2) @@ -10606,55 +17756,103 @@ #define BIT_SHIFT_STATIS_BT_HI_RX_8821C 16 #define BIT_MASK_STATIS_BT_HI_RX_8821C 0xffff -#define BIT_STATIS_BT_HI_RX_8821C(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8821C) << BIT_SHIFT_STATIS_BT_HI_RX_8821C) -#define BIT_GET_STATIS_BT_HI_RX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8821C) & BIT_MASK_STATIS_BT_HI_RX_8821C) - - +#define BIT_STATIS_BT_HI_RX_8821C(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX_8821C) \ + << BIT_SHIFT_STATIS_BT_HI_RX_8821C) +#define BITS_STATIS_BT_HI_RX_8821C \ + (BIT_MASK_STATIS_BT_HI_RX_8821C << BIT_SHIFT_STATIS_BT_HI_RX_8821C) +#define BIT_CLEAR_STATIS_BT_HI_RX_8821C(x) ((x) & (~BITS_STATIS_BT_HI_RX_8821C)) +#define BIT_GET_STATIS_BT_HI_RX_8821C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8821C) & \ + BIT_MASK_STATIS_BT_HI_RX_8821C) +#define BIT_SET_STATIS_BT_HI_RX_8821C(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX_8821C(x) | BIT_STATIS_BT_HI_RX_8821C(v)) #define BIT_SHIFT_STATIS_BT_HI_TX_8821C 0 #define BIT_MASK_STATIS_BT_HI_TX_8821C 0xffff -#define BIT_STATIS_BT_HI_TX_8821C(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8821C) << BIT_SHIFT_STATIS_BT_HI_TX_8821C) -#define BIT_GET_STATIS_BT_HI_TX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8821C) & BIT_MASK_STATIS_BT_HI_TX_8821C) - - +#define BIT_STATIS_BT_HI_TX_8821C(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX_8821C) \ + << BIT_SHIFT_STATIS_BT_HI_TX_8821C) +#define BITS_STATIS_BT_HI_TX_8821C \ + (BIT_MASK_STATIS_BT_HI_TX_8821C << BIT_SHIFT_STATIS_BT_HI_TX_8821C) +#define BIT_CLEAR_STATIS_BT_HI_TX_8821C(x) ((x) & (~BITS_STATIS_BT_HI_TX_8821C)) +#define BIT_GET_STATIS_BT_HI_TX_8821C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8821C) & \ + BIT_MASK_STATIS_BT_HI_TX_8821C) +#define BIT_SET_STATIS_BT_HI_TX_8821C(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX_8821C(x) | BIT_STATIS_BT_HI_TX_8821C(v)) /* 2 REG_BT_ACT_STATISTICS_1_8821C */ #define BIT_SHIFT_STATIS_BT_LO_RX_1_8821C 16 #define BIT_MASK_STATIS_BT_LO_RX_1_8821C 0xffff -#define BIT_STATIS_BT_LO_RX_1_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8821C) << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) -#define BIT_GET_STATIS_BT_LO_RX_1_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) & BIT_MASK_STATIS_BT_LO_RX_1_8821C) - - +#define BIT_STATIS_BT_LO_RX_1_8821C(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8821C) \ + << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) +#define BITS_STATIS_BT_LO_RX_1_8821C \ + (BIT_MASK_STATIS_BT_LO_RX_1_8821C << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) +#define BIT_CLEAR_STATIS_BT_LO_RX_1_8821C(x) \ + ((x) & (~BITS_STATIS_BT_LO_RX_1_8821C)) +#define BIT_GET_STATIS_BT_LO_RX_1_8821C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) & \ + BIT_MASK_STATIS_BT_LO_RX_1_8821C) +#define BIT_SET_STATIS_BT_LO_RX_1_8821C(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_1_8821C(x) | BIT_STATIS_BT_LO_RX_1_8821C(v)) #define BIT_SHIFT_STATIS_BT_LO_TX_1_8821C 0 #define BIT_MASK_STATIS_BT_LO_TX_1_8821C 0xffff -#define BIT_STATIS_BT_LO_TX_1_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8821C) << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) -#define BIT_GET_STATIS_BT_LO_TX_1_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) & BIT_MASK_STATIS_BT_LO_TX_1_8821C) - - +#define BIT_STATIS_BT_LO_TX_1_8821C(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8821C) \ + << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) +#define BITS_STATIS_BT_LO_TX_1_8821C \ + (BIT_MASK_STATIS_BT_LO_TX_1_8821C << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) +#define BIT_CLEAR_STATIS_BT_LO_TX_1_8821C(x) \ + ((x) & (~BITS_STATIS_BT_LO_TX_1_8821C)) +#define BIT_GET_STATIS_BT_LO_TX_1_8821C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) & \ + BIT_MASK_STATIS_BT_LO_TX_1_8821C) +#define BIT_SET_STATIS_BT_LO_TX_1_8821C(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_1_8821C(x) | BIT_STATIS_BT_LO_TX_1_8821C(v)) /* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8821C */ #define BIT_SHIFT_R_BT_CMD_RPT_8821C 16 #define BIT_MASK_R_BT_CMD_RPT_8821C 0xffff -#define BIT_R_BT_CMD_RPT_8821C(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8821C) << BIT_SHIFT_R_BT_CMD_RPT_8821C) -#define BIT_GET_R_BT_CMD_RPT_8821C(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8821C) & BIT_MASK_R_BT_CMD_RPT_8821C) - - +#define BIT_R_BT_CMD_RPT_8821C(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT_8821C) << BIT_SHIFT_R_BT_CMD_RPT_8821C) +#define BITS_R_BT_CMD_RPT_8821C \ + (BIT_MASK_R_BT_CMD_RPT_8821C << BIT_SHIFT_R_BT_CMD_RPT_8821C) +#define BIT_CLEAR_R_BT_CMD_RPT_8821C(x) ((x) & (~BITS_R_BT_CMD_RPT_8821C)) +#define BIT_GET_R_BT_CMD_RPT_8821C(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8821C) & BIT_MASK_R_BT_CMD_RPT_8821C) +#define BIT_SET_R_BT_CMD_RPT_8821C(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT_8821C(x) | BIT_R_BT_CMD_RPT_8821C(v)) #define BIT_SHIFT_R_RPT_FROM_BT_8821C 8 #define BIT_MASK_R_RPT_FROM_BT_8821C 0xff -#define BIT_R_RPT_FROM_BT_8821C(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8821C) << BIT_SHIFT_R_RPT_FROM_BT_8821C) -#define BIT_GET_R_RPT_FROM_BT_8821C(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8821C) & BIT_MASK_R_RPT_FROM_BT_8821C) - - +#define BIT_R_RPT_FROM_BT_8821C(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT_8821C) << BIT_SHIFT_R_RPT_FROM_BT_8821C) +#define BITS_R_RPT_FROM_BT_8821C \ + (BIT_MASK_R_RPT_FROM_BT_8821C << BIT_SHIFT_R_RPT_FROM_BT_8821C) +#define BIT_CLEAR_R_RPT_FROM_BT_8821C(x) ((x) & (~BITS_R_RPT_FROM_BT_8821C)) +#define BIT_GET_R_RPT_FROM_BT_8821C(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8821C) & BIT_MASK_R_RPT_FROM_BT_8821C) +#define BIT_SET_R_RPT_FROM_BT_8821C(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT_8821C(x) | BIT_R_RPT_FROM_BT_8821C(v)) #define BIT_SHIFT_BT_HID_ISR_SET_8821C 6 #define BIT_MASK_BT_HID_ISR_SET_8821C 0x3 -#define BIT_BT_HID_ISR_SET_8821C(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8821C) << BIT_SHIFT_BT_HID_ISR_SET_8821C) -#define BIT_GET_BT_HID_ISR_SET_8821C(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8821C) & BIT_MASK_BT_HID_ISR_SET_8821C) - +#define BIT_BT_HID_ISR_SET_8821C(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET_8821C) \ + << BIT_SHIFT_BT_HID_ISR_SET_8821C) +#define BITS_BT_HID_ISR_SET_8821C \ + (BIT_MASK_BT_HID_ISR_SET_8821C << BIT_SHIFT_BT_HID_ISR_SET_8821C) +#define BIT_CLEAR_BT_HID_ISR_SET_8821C(x) ((x) & (~BITS_BT_HID_ISR_SET_8821C)) +#define BIT_GET_BT_HID_ISR_SET_8821C(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8821C) & \ + BIT_MASK_BT_HID_ISR_SET_8821C) +#define BIT_SET_BT_HID_ISR_SET_8821C(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET_8821C(x) | BIT_BT_HID_ISR_SET_8821C(v)) #define BIT_TDMA_BT_START_NOTIFY_8821C BIT(5) #define BIT_ENABLE_TDMA_FW_MODE_8821C BIT(4) @@ -10667,31 +17865,54 @@ #define BIT_SHIFT_BT_PROFILE_8821C 24 #define BIT_MASK_BT_PROFILE_8821C 0xff -#define BIT_BT_PROFILE_8821C(x) (((x) & BIT_MASK_BT_PROFILE_8821C) << BIT_SHIFT_BT_PROFILE_8821C) -#define BIT_GET_BT_PROFILE_8821C(x) (((x) >> BIT_SHIFT_BT_PROFILE_8821C) & BIT_MASK_BT_PROFILE_8821C) - - +#define BIT_BT_PROFILE_8821C(x) \ + (((x) & BIT_MASK_BT_PROFILE_8821C) << BIT_SHIFT_BT_PROFILE_8821C) +#define BITS_BT_PROFILE_8821C \ + (BIT_MASK_BT_PROFILE_8821C << BIT_SHIFT_BT_PROFILE_8821C) +#define BIT_CLEAR_BT_PROFILE_8821C(x) ((x) & (~BITS_BT_PROFILE_8821C)) +#define BIT_GET_BT_PROFILE_8821C(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE_8821C) & BIT_MASK_BT_PROFILE_8821C) +#define BIT_SET_BT_PROFILE_8821C(x, v) \ + (BIT_CLEAR_BT_PROFILE_8821C(x) | BIT_BT_PROFILE_8821C(v)) #define BIT_SHIFT_BT_POWER_8821C 16 #define BIT_MASK_BT_POWER_8821C 0xff -#define BIT_BT_POWER_8821C(x) (((x) & BIT_MASK_BT_POWER_8821C) << BIT_SHIFT_BT_POWER_8821C) -#define BIT_GET_BT_POWER_8821C(x) (((x) >> BIT_SHIFT_BT_POWER_8821C) & BIT_MASK_BT_POWER_8821C) - - +#define BIT_BT_POWER_8821C(x) \ + (((x) & BIT_MASK_BT_POWER_8821C) << BIT_SHIFT_BT_POWER_8821C) +#define BITS_BT_POWER_8821C \ + (BIT_MASK_BT_POWER_8821C << BIT_SHIFT_BT_POWER_8821C) +#define BIT_CLEAR_BT_POWER_8821C(x) ((x) & (~BITS_BT_POWER_8821C)) +#define BIT_GET_BT_POWER_8821C(x) \ + (((x) >> BIT_SHIFT_BT_POWER_8821C) & BIT_MASK_BT_POWER_8821C) +#define BIT_SET_BT_POWER_8821C(x, v) \ + (BIT_CLEAR_BT_POWER_8821C(x) | BIT_BT_POWER_8821C(v)) #define BIT_SHIFT_BT_PREDECT_STATUS_8821C 8 #define BIT_MASK_BT_PREDECT_STATUS_8821C 0xff -#define BIT_BT_PREDECT_STATUS_8821C(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8821C) << BIT_SHIFT_BT_PREDECT_STATUS_8821C) -#define BIT_GET_BT_PREDECT_STATUS_8821C(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8821C) & BIT_MASK_BT_PREDECT_STATUS_8821C) - - +#define BIT_BT_PREDECT_STATUS_8821C(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS_8821C) \ + << BIT_SHIFT_BT_PREDECT_STATUS_8821C) +#define BITS_BT_PREDECT_STATUS_8821C \ + (BIT_MASK_BT_PREDECT_STATUS_8821C << BIT_SHIFT_BT_PREDECT_STATUS_8821C) +#define BIT_CLEAR_BT_PREDECT_STATUS_8821C(x) \ + ((x) & (~BITS_BT_PREDECT_STATUS_8821C)) +#define BIT_GET_BT_PREDECT_STATUS_8821C(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8821C) & \ + BIT_MASK_BT_PREDECT_STATUS_8821C) +#define BIT_SET_BT_PREDECT_STATUS_8821C(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS_8821C(x) | BIT_BT_PREDECT_STATUS_8821C(v)) #define BIT_SHIFT_BT_CMD_INFO_8821C 0 #define BIT_MASK_BT_CMD_INFO_8821C 0xff -#define BIT_BT_CMD_INFO_8821C(x) (((x) & BIT_MASK_BT_CMD_INFO_8821C) << BIT_SHIFT_BT_CMD_INFO_8821C) -#define BIT_GET_BT_CMD_INFO_8821C(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8821C) & BIT_MASK_BT_CMD_INFO_8821C) - - +#define BIT_BT_CMD_INFO_8821C(x) \ + (((x) & BIT_MASK_BT_CMD_INFO_8821C) << BIT_SHIFT_BT_CMD_INFO_8821C) +#define BITS_BT_CMD_INFO_8821C \ + (BIT_MASK_BT_CMD_INFO_8821C << BIT_SHIFT_BT_CMD_INFO_8821C) +#define BIT_CLEAR_BT_CMD_INFO_8821C(x) ((x) & (~BITS_BT_CMD_INFO_8821C)) +#define BIT_GET_BT_CMD_INFO_8821C(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO_8821C) & BIT_MASK_BT_CMD_INFO_8821C) +#define BIT_SET_BT_CMD_INFO_8821C(x, v) \ + (BIT_CLEAR_BT_CMD_INFO_8821C(x) | BIT_BT_CMD_INFO_8821C(v)) /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8821C */ #define BIT_EN_MAC_NULL_PKT_NOTIFY_8821C BIT(31) @@ -10705,41 +17926,67 @@ #define BIT_SHIFT_WLAN_RPT_DATA_8821C 16 #define BIT_MASK_WLAN_RPT_DATA_8821C 0xff -#define BIT_WLAN_RPT_DATA_8821C(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8821C) << BIT_SHIFT_WLAN_RPT_DATA_8821C) -#define BIT_GET_WLAN_RPT_DATA_8821C(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8821C) & BIT_MASK_WLAN_RPT_DATA_8821C) - - +#define BIT_WLAN_RPT_DATA_8821C(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA_8821C) << BIT_SHIFT_WLAN_RPT_DATA_8821C) +#define BITS_WLAN_RPT_DATA_8821C \ + (BIT_MASK_WLAN_RPT_DATA_8821C << BIT_SHIFT_WLAN_RPT_DATA_8821C) +#define BIT_CLEAR_WLAN_RPT_DATA_8821C(x) ((x) & (~BITS_WLAN_RPT_DATA_8821C)) +#define BIT_GET_WLAN_RPT_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8821C) & BIT_MASK_WLAN_RPT_DATA_8821C) +#define BIT_SET_WLAN_RPT_DATA_8821C(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA_8821C(x) | BIT_WLAN_RPT_DATA_8821C(v)) #define BIT_SHIFT_CMD_ID_8821C 8 #define BIT_MASK_CMD_ID_8821C 0xff -#define BIT_CMD_ID_8821C(x) (((x) & BIT_MASK_CMD_ID_8821C) << BIT_SHIFT_CMD_ID_8821C) -#define BIT_GET_CMD_ID_8821C(x) (((x) >> BIT_SHIFT_CMD_ID_8821C) & BIT_MASK_CMD_ID_8821C) - - +#define BIT_CMD_ID_8821C(x) \ + (((x) & BIT_MASK_CMD_ID_8821C) << BIT_SHIFT_CMD_ID_8821C) +#define BITS_CMD_ID_8821C (BIT_MASK_CMD_ID_8821C << BIT_SHIFT_CMD_ID_8821C) +#define BIT_CLEAR_CMD_ID_8821C(x) ((x) & (~BITS_CMD_ID_8821C)) +#define BIT_GET_CMD_ID_8821C(x) \ + (((x) >> BIT_SHIFT_CMD_ID_8821C) & BIT_MASK_CMD_ID_8821C) +#define BIT_SET_CMD_ID_8821C(x, v) \ + (BIT_CLEAR_CMD_ID_8821C(x) | BIT_CMD_ID_8821C(v)) #define BIT_SHIFT_BT_DATA_8821C 0 #define BIT_MASK_BT_DATA_8821C 0xff -#define BIT_BT_DATA_8821C(x) (((x) & BIT_MASK_BT_DATA_8821C) << BIT_SHIFT_BT_DATA_8821C) -#define BIT_GET_BT_DATA_8821C(x) (((x) >> BIT_SHIFT_BT_DATA_8821C) & BIT_MASK_BT_DATA_8821C) - - +#define BIT_BT_DATA_8821C(x) \ + (((x) & BIT_MASK_BT_DATA_8821C) << BIT_SHIFT_BT_DATA_8821C) +#define BITS_BT_DATA_8821C (BIT_MASK_BT_DATA_8821C << BIT_SHIFT_BT_DATA_8821C) +#define BIT_CLEAR_BT_DATA_8821C(x) ((x) & (~BITS_BT_DATA_8821C)) +#define BIT_GET_BT_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_BT_DATA_8821C) & BIT_MASK_BT_DATA_8821C) +#define BIT_SET_BT_DATA_8821C(x, v) \ + (BIT_CLEAR_BT_DATA_8821C(x) | BIT_BT_DATA_8821C(v)) /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C */ #define BIT_SHIFT_WLAN_RPT_TO_8821C 0 #define BIT_MASK_WLAN_RPT_TO_8821C 0xff -#define BIT_WLAN_RPT_TO_8821C(x) (((x) & BIT_MASK_WLAN_RPT_TO_8821C) << BIT_SHIFT_WLAN_RPT_TO_8821C) -#define BIT_GET_WLAN_RPT_TO_8821C(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8821C) & BIT_MASK_WLAN_RPT_TO_8821C) - - +#define BIT_WLAN_RPT_TO_8821C(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO_8821C) << BIT_SHIFT_WLAN_RPT_TO_8821C) +#define BITS_WLAN_RPT_TO_8821C \ + (BIT_MASK_WLAN_RPT_TO_8821C << BIT_SHIFT_WLAN_RPT_TO_8821C) +#define BIT_CLEAR_WLAN_RPT_TO_8821C(x) ((x) & (~BITS_WLAN_RPT_TO_8821C)) +#define BIT_GET_WLAN_RPT_TO_8821C(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO_8821C) & BIT_MASK_WLAN_RPT_TO_8821C) +#define BIT_SET_WLAN_RPT_TO_8821C(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO_8821C(x) | BIT_WLAN_RPT_TO_8821C(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C */ #define BIT_SHIFT_ISOLATION_CHK_0_8821C 1 #define BIT_MASK_ISOLATION_CHK_0_8821C 0x7fffff -#define BIT_ISOLATION_CHK_0_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_0_8821C) << BIT_SHIFT_ISOLATION_CHK_0_8821C) -#define BIT_GET_ISOLATION_CHK_0_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8821C) & BIT_MASK_ISOLATION_CHK_0_8821C) - +#define BIT_ISOLATION_CHK_0_8821C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_0_8821C) \ + << BIT_SHIFT_ISOLATION_CHK_0_8821C) +#define BITS_ISOLATION_CHK_0_8821C \ + (BIT_MASK_ISOLATION_CHK_0_8821C << BIT_SHIFT_ISOLATION_CHK_0_8821C) +#define BIT_CLEAR_ISOLATION_CHK_0_8821C(x) ((x) & (~BITS_ISOLATION_CHK_0_8821C)) +#define BIT_GET_ISOLATION_CHK_0_8821C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8821C) & \ + BIT_MASK_ISOLATION_CHK_0_8821C) +#define BIT_SET_ISOLATION_CHK_0_8821C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_0_8821C(x) | BIT_ISOLATION_CHK_0_8821C(v)) #define BIT_ISOLATION_EN_8821C BIT(0) @@ -10747,19 +17994,33 @@ #define BIT_SHIFT_ISOLATION_CHK_1_8821C 0 #define BIT_MASK_ISOLATION_CHK_1_8821C 0xffffffffL -#define BIT_ISOLATION_CHK_1_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_1_8821C) << BIT_SHIFT_ISOLATION_CHK_1_8821C) -#define BIT_GET_ISOLATION_CHK_1_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8821C) & BIT_MASK_ISOLATION_CHK_1_8821C) - - +#define BIT_ISOLATION_CHK_1_8821C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_1_8821C) \ + << BIT_SHIFT_ISOLATION_CHK_1_8821C) +#define BITS_ISOLATION_CHK_1_8821C \ + (BIT_MASK_ISOLATION_CHK_1_8821C << BIT_SHIFT_ISOLATION_CHK_1_8821C) +#define BIT_CLEAR_ISOLATION_CHK_1_8821C(x) ((x) & (~BITS_ISOLATION_CHK_1_8821C)) +#define BIT_GET_ISOLATION_CHK_1_8821C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8821C) & \ + BIT_MASK_ISOLATION_CHK_1_8821C) +#define BIT_SET_ISOLATION_CHK_1_8821C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_1_8821C(x) | BIT_ISOLATION_CHK_1_8821C(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C */ #define BIT_SHIFT_ISOLATION_CHK_2_8821C 0 #define BIT_MASK_ISOLATION_CHK_2_8821C 0xffffff -#define BIT_ISOLATION_CHK_2_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_2_8821C) << BIT_SHIFT_ISOLATION_CHK_2_8821C) -#define BIT_GET_ISOLATION_CHK_2_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8821C) & BIT_MASK_ISOLATION_CHK_2_8821C) - - +#define BIT_ISOLATION_CHK_2_8821C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_2_8821C) \ + << BIT_SHIFT_ISOLATION_CHK_2_8821C) +#define BITS_ISOLATION_CHK_2_8821C \ + (BIT_MASK_ISOLATION_CHK_2_8821C << BIT_SHIFT_ISOLATION_CHK_2_8821C) +#define BIT_CLEAR_ISOLATION_CHK_2_8821C(x) ((x) & (~BITS_ISOLATION_CHK_2_8821C)) +#define BIT_GET_ISOLATION_CHK_2_8821C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8821C) & \ + BIT_MASK_ISOLATION_CHK_2_8821C) +#define BIT_SET_ISOLATION_CHK_2_8821C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_2_8821C(x) | BIT_ISOLATION_CHK_2_8821C(v)) /* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8821C */ #define BIT_BT_HID_ISR_8821C BIT(7) @@ -10775,25 +18036,45 @@ #define BIT_SHIFT_BT_TIME_8821C 6 #define BIT_MASK_BT_TIME_8821C 0x3ffffff -#define BIT_BT_TIME_8821C(x) (((x) & BIT_MASK_BT_TIME_8821C) << BIT_SHIFT_BT_TIME_8821C) -#define BIT_GET_BT_TIME_8821C(x) (((x) >> BIT_SHIFT_BT_TIME_8821C) & BIT_MASK_BT_TIME_8821C) - - +#define BIT_BT_TIME_8821C(x) \ + (((x) & BIT_MASK_BT_TIME_8821C) << BIT_SHIFT_BT_TIME_8821C) +#define BITS_BT_TIME_8821C (BIT_MASK_BT_TIME_8821C << BIT_SHIFT_BT_TIME_8821C) +#define BIT_CLEAR_BT_TIME_8821C(x) ((x) & (~BITS_BT_TIME_8821C)) +#define BIT_GET_BT_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_BT_TIME_8821C) & BIT_MASK_BT_TIME_8821C) +#define BIT_SET_BT_TIME_8821C(x, v) \ + (BIT_CLEAR_BT_TIME_8821C(x) | BIT_BT_TIME_8821C(v)) #define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C 0 #define BIT_MASK_BT_RPT_SAMPLE_RATE_8821C 0x3f -#define BIT_BT_RPT_SAMPLE_RATE_8821C(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) -#define BIT_GET_BT_RPT_SAMPLE_RATE_8821C(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) - - +#define BIT_BT_RPT_SAMPLE_RATE_8821C(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) +#define BITS_BT_RPT_SAMPLE_RATE_8821C \ + (BIT_MASK_BT_RPT_SAMPLE_RATE_8821C \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8821C(x) \ + ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8821C)) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8821C(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) & \ + BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) +#define BIT_SET_BT_RPT_SAMPLE_RATE_8821C(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8821C(x) | \ + BIT_BT_RPT_SAMPLE_RATE_8821C(v)) /* 2 REG_BT_ACT_REGISTER_8821C */ #define BIT_SHIFT_BT_EISR_EN_8821C 16 #define BIT_MASK_BT_EISR_EN_8821C 0xff -#define BIT_BT_EISR_EN_8821C(x) (((x) & BIT_MASK_BT_EISR_EN_8821C) << BIT_SHIFT_BT_EISR_EN_8821C) -#define BIT_GET_BT_EISR_EN_8821C(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8821C) & BIT_MASK_BT_EISR_EN_8821C) - +#define BIT_BT_EISR_EN_8821C(x) \ + (((x) & BIT_MASK_BT_EISR_EN_8821C) << BIT_SHIFT_BT_EISR_EN_8821C) +#define BITS_BT_EISR_EN_8821C \ + (BIT_MASK_BT_EISR_EN_8821C << BIT_SHIFT_BT_EISR_EN_8821C) +#define BIT_CLEAR_BT_EISR_EN_8821C(x) ((x) & (~BITS_BT_EISR_EN_8821C)) +#define BIT_GET_BT_EISR_EN_8821C(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN_8821C) & BIT_MASK_BT_EISR_EN_8821C) +#define BIT_SET_BT_EISR_EN_8821C(x, v) \ + (BIT_CLEAR_BT_EISR_EN_8821C(x) | BIT_BT_EISR_EN_8821C(v)) #define BIT_BT_ACT_FALLING_ISR_8821C BIT(10) #define BIT_BT_ACT_RISING_ISR_8821C BIT(9) @@ -10801,19 +18082,29 @@ #define BIT_SHIFT_BT_CH_8821C 0 #define BIT_MASK_BT_CH_8821C 0xff -#define BIT_BT_CH_8821C(x) (((x) & BIT_MASK_BT_CH_8821C) << BIT_SHIFT_BT_CH_8821C) -#define BIT_GET_BT_CH_8821C(x) (((x) >> BIT_SHIFT_BT_CH_8821C) & BIT_MASK_BT_CH_8821C) - - +#define BIT_BT_CH_8821C(x) \ + (((x) & BIT_MASK_BT_CH_8821C) << BIT_SHIFT_BT_CH_8821C) +#define BITS_BT_CH_8821C (BIT_MASK_BT_CH_8821C << BIT_SHIFT_BT_CH_8821C) +#define BIT_CLEAR_BT_CH_8821C(x) ((x) & (~BITS_BT_CH_8821C)) +#define BIT_GET_BT_CH_8821C(x) \ + (((x) >> BIT_SHIFT_BT_CH_8821C) & BIT_MASK_BT_CH_8821C) +#define BIT_SET_BT_CH_8821C(x, v) \ + (BIT_CLEAR_BT_CH_8821C(x) | BIT_BT_CH_8821C(v)) /* 2 REG_OBFF_CTRL_BASIC_8821C */ #define BIT_OBFF_EN_V1_8821C BIT(31) #define BIT_SHIFT_OBFF_STATE_V1_8821C 28 #define BIT_MASK_OBFF_STATE_V1_8821C 0x3 -#define BIT_OBFF_STATE_V1_8821C(x) (((x) & BIT_MASK_OBFF_STATE_V1_8821C) << BIT_SHIFT_OBFF_STATE_V1_8821C) -#define BIT_GET_OBFF_STATE_V1_8821C(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8821C) & BIT_MASK_OBFF_STATE_V1_8821C) - +#define BIT_OBFF_STATE_V1_8821C(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1_8821C) << BIT_SHIFT_OBFF_STATE_V1_8821C) +#define BITS_OBFF_STATE_V1_8821C \ + (BIT_MASK_OBFF_STATE_V1_8821C << BIT_SHIFT_OBFF_STATE_V1_8821C) +#define BIT_CLEAR_OBFF_STATE_V1_8821C(x) ((x) & (~BITS_OBFF_STATE_V1_8821C)) +#define BIT_GET_OBFF_STATE_V1_8821C(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1_8821C) & BIT_MASK_OBFF_STATE_V1_8821C) +#define BIT_SET_OBFF_STATE_V1_8821C(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1_8821C(x) | BIT_OBFF_STATE_V1_8821C(v)) #define BIT_OBFF_ACT_RXDMA_EN_8821C BIT(27) #define BIT_OBFF_BLOCK_INT_EN_8821C BIT(26) @@ -10822,30 +18113,51 @@ #define BIT_SHIFT_WAKE_MAX_PLS_8821C 20 #define BIT_MASK_WAKE_MAX_PLS_8821C 0x7 -#define BIT_WAKE_MAX_PLS_8821C(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8821C) << BIT_SHIFT_WAKE_MAX_PLS_8821C) -#define BIT_GET_WAKE_MAX_PLS_8821C(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8821C) & BIT_MASK_WAKE_MAX_PLS_8821C) - - +#define BIT_WAKE_MAX_PLS_8821C(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS_8821C) << BIT_SHIFT_WAKE_MAX_PLS_8821C) +#define BITS_WAKE_MAX_PLS_8821C \ + (BIT_MASK_WAKE_MAX_PLS_8821C << BIT_SHIFT_WAKE_MAX_PLS_8821C) +#define BIT_CLEAR_WAKE_MAX_PLS_8821C(x) ((x) & (~BITS_WAKE_MAX_PLS_8821C)) +#define BIT_GET_WAKE_MAX_PLS_8821C(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8821C) & BIT_MASK_WAKE_MAX_PLS_8821C) +#define BIT_SET_WAKE_MAX_PLS_8821C(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS_8821C(x) | BIT_WAKE_MAX_PLS_8821C(v)) #define BIT_SHIFT_WAKE_MIN_PLS_8821C 16 #define BIT_MASK_WAKE_MIN_PLS_8821C 0x7 -#define BIT_WAKE_MIN_PLS_8821C(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8821C) << BIT_SHIFT_WAKE_MIN_PLS_8821C) -#define BIT_GET_WAKE_MIN_PLS_8821C(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8821C) & BIT_MASK_WAKE_MIN_PLS_8821C) - - +#define BIT_WAKE_MIN_PLS_8821C(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS_8821C) << BIT_SHIFT_WAKE_MIN_PLS_8821C) +#define BITS_WAKE_MIN_PLS_8821C \ + (BIT_MASK_WAKE_MIN_PLS_8821C << BIT_SHIFT_WAKE_MIN_PLS_8821C) +#define BIT_CLEAR_WAKE_MIN_PLS_8821C(x) ((x) & (~BITS_WAKE_MIN_PLS_8821C)) +#define BIT_GET_WAKE_MIN_PLS_8821C(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8821C) & BIT_MASK_WAKE_MIN_PLS_8821C) +#define BIT_SET_WAKE_MIN_PLS_8821C(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS_8821C(x) | BIT_WAKE_MIN_PLS_8821C(v)) #define BIT_SHIFT_WAKE_MAX_F2F_8821C 12 #define BIT_MASK_WAKE_MAX_F2F_8821C 0x7 -#define BIT_WAKE_MAX_F2F_8821C(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8821C) << BIT_SHIFT_WAKE_MAX_F2F_8821C) -#define BIT_GET_WAKE_MAX_F2F_8821C(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8821C) & BIT_MASK_WAKE_MAX_F2F_8821C) - - +#define BIT_WAKE_MAX_F2F_8821C(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F_8821C) << BIT_SHIFT_WAKE_MAX_F2F_8821C) +#define BITS_WAKE_MAX_F2F_8821C \ + (BIT_MASK_WAKE_MAX_F2F_8821C << BIT_SHIFT_WAKE_MAX_F2F_8821C) +#define BIT_CLEAR_WAKE_MAX_F2F_8821C(x) ((x) & (~BITS_WAKE_MAX_F2F_8821C)) +#define BIT_GET_WAKE_MAX_F2F_8821C(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8821C) & BIT_MASK_WAKE_MAX_F2F_8821C) +#define BIT_SET_WAKE_MAX_F2F_8821C(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F_8821C(x) | BIT_WAKE_MAX_F2F_8821C(v)) #define BIT_SHIFT_WAKE_MIN_F2F_8821C 8 #define BIT_MASK_WAKE_MIN_F2F_8821C 0x7 -#define BIT_WAKE_MIN_F2F_8821C(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8821C) << BIT_SHIFT_WAKE_MIN_F2F_8821C) -#define BIT_GET_WAKE_MIN_F2F_8821C(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8821C) & BIT_MASK_WAKE_MIN_F2F_8821C) - +#define BIT_WAKE_MIN_F2F_8821C(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F_8821C) << BIT_SHIFT_WAKE_MIN_F2F_8821C) +#define BITS_WAKE_MIN_F2F_8821C \ + (BIT_MASK_WAKE_MIN_F2F_8821C << BIT_SHIFT_WAKE_MIN_F2F_8821C) +#define BIT_CLEAR_WAKE_MIN_F2F_8821C(x) ((x) & (~BITS_WAKE_MIN_F2F_8821C)) +#define BIT_GET_WAKE_MIN_F2F_8821C(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8821C) & BIT_MASK_WAKE_MIN_F2F_8821C) +#define BIT_SET_WAKE_MIN_F2F_8821C(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F_8821C(x) | BIT_WAKE_MIN_F2F_8821C(v)) #define BIT_APP_CPU_ACT_V1_8821C BIT(3) #define BIT_APP_OBFF_V1_8821C BIT(2) @@ -10856,31 +18168,65 @@ #define BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C 24 #define BIT_MASK_RX_HIGH_TIMER_IDX_8821C 0x7 -#define BIT_RX_HIGH_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) -#define BIT_GET_RX_HIGH_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C) - - +#define BIT_RX_HIGH_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C) \ + << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) +#define BITS_RX_HIGH_TIMER_IDX_8821C \ + (BIT_MASK_RX_HIGH_TIMER_IDX_8821C << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_RX_HIGH_TIMER_IDX_8821C)) +#define BIT_GET_RX_HIGH_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) & \ + BIT_MASK_RX_HIGH_TIMER_IDX_8821C) +#define BIT_SET_RX_HIGH_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX_8821C(x) | BIT_RX_HIGH_TIMER_IDX_8821C(v)) #define BIT_SHIFT_RX_MED_TIMER_IDX_8821C 16 #define BIT_MASK_RX_MED_TIMER_IDX_8821C 0x7 -#define BIT_RX_MED_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8821C) << BIT_SHIFT_RX_MED_TIMER_IDX_8821C) -#define BIT_GET_RX_MED_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8821C) & BIT_MASK_RX_MED_TIMER_IDX_8821C) - - +#define BIT_RX_MED_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX_8821C) \ + << BIT_SHIFT_RX_MED_TIMER_IDX_8821C) +#define BITS_RX_MED_TIMER_IDX_8821C \ + (BIT_MASK_RX_MED_TIMER_IDX_8821C << BIT_SHIFT_RX_MED_TIMER_IDX_8821C) +#define BIT_CLEAR_RX_MED_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_RX_MED_TIMER_IDX_8821C)) +#define BIT_GET_RX_MED_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8821C) & \ + BIT_MASK_RX_MED_TIMER_IDX_8821C) +#define BIT_SET_RX_MED_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX_8821C(x) | BIT_RX_MED_TIMER_IDX_8821C(v)) #define BIT_SHIFT_RX_LOW_TIMER_IDX_8821C 8 #define BIT_MASK_RX_LOW_TIMER_IDX_8821C 0x7 -#define BIT_RX_LOW_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) -#define BIT_GET_RX_LOW_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) - - +#define BIT_RX_LOW_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) \ + << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) +#define BITS_RX_LOW_TIMER_IDX_8821C \ + (BIT_MASK_RX_LOW_TIMER_IDX_8821C << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) +#define BIT_CLEAR_RX_LOW_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_RX_LOW_TIMER_IDX_8821C)) +#define BIT_GET_RX_LOW_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) & \ + BIT_MASK_RX_LOW_TIMER_IDX_8821C) +#define BIT_SET_RX_LOW_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX_8821C(x) | BIT_RX_LOW_TIMER_IDX_8821C(v)) #define BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C 0 #define BIT_MASK_OBFF_INT_TIMER_IDX_8821C 0x7 -#define BIT_OBFF_INT_TIMER_IDX_8821C(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) -#define BIT_GET_OBFF_INT_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) - - +#define BIT_OBFF_INT_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) +#define BITS_OBFF_INT_TIMER_IDX_8821C \ + (BIT_MASK_OBFF_INT_TIMER_IDX_8821C \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_OBFF_INT_TIMER_IDX_8821C)) +#define BIT_GET_OBFF_INT_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) & \ + BIT_MASK_OBFF_INT_TIMER_IDX_8821C) +#define BIT_SET_OBFF_INT_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX_8821C(x) | \ + BIT_OBFF_INT_TIMER_IDX_8821C(v)) /* 2 REG_LTR_CTRL_BASIC_8821C */ #define BIT_LTR_EN_V1_8821C BIT(31) @@ -10896,116 +18242,224 @@ #define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C 20 #define BIT_MASK_HIGH_RATE_TRIG_SEL_8821C 0x3 -#define BIT_HIGH_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) -#define BIT_GET_HIGH_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) - - +#define BIT_HIGH_RATE_TRIG_SEL_8821C(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) +#define BITS_HIGH_RATE_TRIG_SEL_8821C \ + (BIT_MASK_HIGH_RATE_TRIG_SEL_8821C \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8821C(x) \ + ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8821C)) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) & \ + BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) +#define BIT_SET_HIGH_RATE_TRIG_SEL_8821C(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8821C(x) | \ + BIT_HIGH_RATE_TRIG_SEL_8821C(v)) #define BIT_SHIFT_MED_RATE_TRIG_SEL_8821C 18 #define BIT_MASK_MED_RATE_TRIG_SEL_8821C 0x3 -#define BIT_MED_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) -#define BIT_GET_MED_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) - - +#define BIT_MED_RATE_TRIG_SEL_8821C(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) \ + << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) +#define BITS_MED_RATE_TRIG_SEL_8821C \ + (BIT_MASK_MED_RATE_TRIG_SEL_8821C << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) +#define BIT_CLEAR_MED_RATE_TRIG_SEL_8821C(x) \ + ((x) & (~BITS_MED_RATE_TRIG_SEL_8821C)) +#define BIT_GET_MED_RATE_TRIG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) & \ + BIT_MASK_MED_RATE_TRIG_SEL_8821C) +#define BIT_SET_MED_RATE_TRIG_SEL_8821C(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL_8821C(x) | BIT_MED_RATE_TRIG_SEL_8821C(v)) #define BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C 16 #define BIT_MASK_LOW_RATE_TRIG_SEL_8821C 0x3 -#define BIT_LOW_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) -#define BIT_GET_LOW_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) - - +#define BIT_LOW_RATE_TRIG_SEL_8821C(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) \ + << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) +#define BITS_LOW_RATE_TRIG_SEL_8821C \ + (BIT_MASK_LOW_RATE_TRIG_SEL_8821C << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8821C(x) \ + ((x) & (~BITS_LOW_RATE_TRIG_SEL_8821C)) +#define BIT_GET_LOW_RATE_TRIG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) & \ + BIT_MASK_LOW_RATE_TRIG_SEL_8821C) +#define BIT_SET_LOW_RATE_TRIG_SEL_8821C(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL_8821C(x) | BIT_LOW_RATE_TRIG_SEL_8821C(v)) #define BIT_SHIFT_HIGH_RATE_BD_IDX_8821C 8 #define BIT_MASK_HIGH_RATE_BD_IDX_8821C 0x7f -#define BIT_HIGH_RATE_BD_IDX_8821C(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) -#define BIT_GET_HIGH_RATE_BD_IDX_8821C(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) - - +#define BIT_HIGH_RATE_BD_IDX_8821C(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) \ + << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) +#define BITS_HIGH_RATE_BD_IDX_8821C \ + (BIT_MASK_HIGH_RATE_BD_IDX_8821C << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) +#define BIT_CLEAR_HIGH_RATE_BD_IDX_8821C(x) \ + ((x) & (~BITS_HIGH_RATE_BD_IDX_8821C)) +#define BIT_GET_HIGH_RATE_BD_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) & \ + BIT_MASK_HIGH_RATE_BD_IDX_8821C) +#define BIT_SET_HIGH_RATE_BD_IDX_8821C(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX_8821C(x) | BIT_HIGH_RATE_BD_IDX_8821C(v)) #define BIT_SHIFT_LOW_RATE_BD_IDX_8821C 0 #define BIT_MASK_LOW_RATE_BD_IDX_8821C 0x7f -#define BIT_LOW_RATE_BD_IDX_8821C(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8821C) << BIT_SHIFT_LOW_RATE_BD_IDX_8821C) -#define BIT_GET_LOW_RATE_BD_IDX_8821C(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8821C) & BIT_MASK_LOW_RATE_BD_IDX_8821C) - - +#define BIT_LOW_RATE_BD_IDX_8821C(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX_8821C) \ + << BIT_SHIFT_LOW_RATE_BD_IDX_8821C) +#define BITS_LOW_RATE_BD_IDX_8821C \ + (BIT_MASK_LOW_RATE_BD_IDX_8821C << BIT_SHIFT_LOW_RATE_BD_IDX_8821C) +#define BIT_CLEAR_LOW_RATE_BD_IDX_8821C(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8821C)) +#define BIT_GET_LOW_RATE_BD_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8821C) & \ + BIT_MASK_LOW_RATE_BD_IDX_8821C) +#define BIT_SET_LOW_RATE_BD_IDX_8821C(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX_8821C(x) | BIT_LOW_RATE_BD_IDX_8821C(v)) /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8821C */ #define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C 24 #define BIT_MASK_RX_EMPTY_TIMER_IDX_8821C 0x7 -#define BIT_RX_EMPTY_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) -#define BIT_GET_RX_EMPTY_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) - - +#define BIT_RX_EMPTY_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) +#define BITS_RX_EMPTY_TIMER_IDX_8821C \ + (BIT_MASK_RX_EMPTY_TIMER_IDX_8821C \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8821C)) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) & \ + BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) +#define BIT_SET_RX_EMPTY_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8821C(x) | \ + BIT_RX_EMPTY_TIMER_IDX_8821C(v)) #define BIT_SHIFT_RX_AFULL_TH_IDX_8821C 20 #define BIT_MASK_RX_AFULL_TH_IDX_8821C 0x7 -#define BIT_RX_AFULL_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8821C) << BIT_SHIFT_RX_AFULL_TH_IDX_8821C) -#define BIT_GET_RX_AFULL_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8821C) & BIT_MASK_RX_AFULL_TH_IDX_8821C) - - +#define BIT_RX_AFULL_TH_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX_8821C) \ + << BIT_SHIFT_RX_AFULL_TH_IDX_8821C) +#define BITS_RX_AFULL_TH_IDX_8821C \ + (BIT_MASK_RX_AFULL_TH_IDX_8821C << BIT_SHIFT_RX_AFULL_TH_IDX_8821C) +#define BIT_CLEAR_RX_AFULL_TH_IDX_8821C(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8821C)) +#define BIT_GET_RX_AFULL_TH_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8821C) & \ + BIT_MASK_RX_AFULL_TH_IDX_8821C) +#define BIT_SET_RX_AFULL_TH_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX_8821C(x) | BIT_RX_AFULL_TH_IDX_8821C(v)) #define BIT_SHIFT_RX_HIGH_TH_IDX_8821C 16 #define BIT_MASK_RX_HIGH_TH_IDX_8821C 0x7 -#define BIT_RX_HIGH_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8821C) << BIT_SHIFT_RX_HIGH_TH_IDX_8821C) -#define BIT_GET_RX_HIGH_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8821C) & BIT_MASK_RX_HIGH_TH_IDX_8821C) - - +#define BIT_RX_HIGH_TH_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX_8821C) \ + << BIT_SHIFT_RX_HIGH_TH_IDX_8821C) +#define BITS_RX_HIGH_TH_IDX_8821C \ + (BIT_MASK_RX_HIGH_TH_IDX_8821C << BIT_SHIFT_RX_HIGH_TH_IDX_8821C) +#define BIT_CLEAR_RX_HIGH_TH_IDX_8821C(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8821C)) +#define BIT_GET_RX_HIGH_TH_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8821C) & \ + BIT_MASK_RX_HIGH_TH_IDX_8821C) +#define BIT_SET_RX_HIGH_TH_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX_8821C(x) | BIT_RX_HIGH_TH_IDX_8821C(v)) #define BIT_SHIFT_RX_MED_TH_IDX_8821C 12 #define BIT_MASK_RX_MED_TH_IDX_8821C 0x7 -#define BIT_RX_MED_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8821C) << BIT_SHIFT_RX_MED_TH_IDX_8821C) -#define BIT_GET_RX_MED_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8821C) & BIT_MASK_RX_MED_TH_IDX_8821C) - - +#define BIT_RX_MED_TH_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX_8821C) << BIT_SHIFT_RX_MED_TH_IDX_8821C) +#define BITS_RX_MED_TH_IDX_8821C \ + (BIT_MASK_RX_MED_TH_IDX_8821C << BIT_SHIFT_RX_MED_TH_IDX_8821C) +#define BIT_CLEAR_RX_MED_TH_IDX_8821C(x) ((x) & (~BITS_RX_MED_TH_IDX_8821C)) +#define BIT_GET_RX_MED_TH_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8821C) & BIT_MASK_RX_MED_TH_IDX_8821C) +#define BIT_SET_RX_MED_TH_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX_8821C(x) | BIT_RX_MED_TH_IDX_8821C(v)) #define BIT_SHIFT_RX_LOW_TH_IDX_8821C 8 #define BIT_MASK_RX_LOW_TH_IDX_8821C 0x7 -#define BIT_RX_LOW_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8821C) << BIT_SHIFT_RX_LOW_TH_IDX_8821C) -#define BIT_GET_RX_LOW_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8821C) & BIT_MASK_RX_LOW_TH_IDX_8821C) - - +#define BIT_RX_LOW_TH_IDX_8821C(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX_8821C) << BIT_SHIFT_RX_LOW_TH_IDX_8821C) +#define BITS_RX_LOW_TH_IDX_8821C \ + (BIT_MASK_RX_LOW_TH_IDX_8821C << BIT_SHIFT_RX_LOW_TH_IDX_8821C) +#define BIT_CLEAR_RX_LOW_TH_IDX_8821C(x) ((x) & (~BITS_RX_LOW_TH_IDX_8821C)) +#define BIT_GET_RX_LOW_TH_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8821C) & BIT_MASK_RX_LOW_TH_IDX_8821C) +#define BIT_SET_RX_LOW_TH_IDX_8821C(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX_8821C(x) | BIT_RX_LOW_TH_IDX_8821C(v)) #define BIT_SHIFT_LTR_SPACE_IDX_8821C 4 #define BIT_MASK_LTR_SPACE_IDX_8821C 0x3 -#define BIT_LTR_SPACE_IDX_8821C(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8821C) << BIT_SHIFT_LTR_SPACE_IDX_8821C) -#define BIT_GET_LTR_SPACE_IDX_8821C(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8821C) & BIT_MASK_LTR_SPACE_IDX_8821C) - - +#define BIT_LTR_SPACE_IDX_8821C(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX_8821C) << BIT_SHIFT_LTR_SPACE_IDX_8821C) +#define BITS_LTR_SPACE_IDX_8821C \ + (BIT_MASK_LTR_SPACE_IDX_8821C << BIT_SHIFT_LTR_SPACE_IDX_8821C) +#define BIT_CLEAR_LTR_SPACE_IDX_8821C(x) ((x) & (~BITS_LTR_SPACE_IDX_8821C)) +#define BIT_GET_LTR_SPACE_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8821C) & BIT_MASK_LTR_SPACE_IDX_8821C) +#define BIT_SET_LTR_SPACE_IDX_8821C(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX_8821C(x) | BIT_LTR_SPACE_IDX_8821C(v)) #define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C 0 #define BIT_MASK_LTR_IDLE_TIMER_IDX_8821C 0x7 -#define BIT_LTR_IDLE_TIMER_IDX_8821C(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) -#define BIT_GET_LTR_IDLE_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) - - +#define BIT_LTR_IDLE_TIMER_IDX_8821C(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) +#define BITS_LTR_IDLE_TIMER_IDX_8821C \ + (BIT_MASK_LTR_IDLE_TIMER_IDX_8821C \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8821C(x) \ + ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8821C)) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8821C(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) & \ + BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) +#define BIT_SET_LTR_IDLE_TIMER_IDX_8821C(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8821C(x) | \ + BIT_LTR_IDLE_TIMER_IDX_8821C(v)) /* 2 REG_LTR_IDLE_LATENCY_V1_8821C */ #define BIT_SHIFT_LTR_IDLE_L_8821C 0 #define BIT_MASK_LTR_IDLE_L_8821C 0xffffffffL -#define BIT_LTR_IDLE_L_8821C(x) (((x) & BIT_MASK_LTR_IDLE_L_8821C) << BIT_SHIFT_LTR_IDLE_L_8821C) -#define BIT_GET_LTR_IDLE_L_8821C(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8821C) & BIT_MASK_LTR_IDLE_L_8821C) - - +#define BIT_LTR_IDLE_L_8821C(x) \ + (((x) & BIT_MASK_LTR_IDLE_L_8821C) << BIT_SHIFT_LTR_IDLE_L_8821C) +#define BITS_LTR_IDLE_L_8821C \ + (BIT_MASK_LTR_IDLE_L_8821C << BIT_SHIFT_LTR_IDLE_L_8821C) +#define BIT_CLEAR_LTR_IDLE_L_8821C(x) ((x) & (~BITS_LTR_IDLE_L_8821C)) +#define BIT_GET_LTR_IDLE_L_8821C(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L_8821C) & BIT_MASK_LTR_IDLE_L_8821C) +#define BIT_SET_LTR_IDLE_L_8821C(x, v) \ + (BIT_CLEAR_LTR_IDLE_L_8821C(x) | BIT_LTR_IDLE_L_8821C(v)) /* 2 REG_LTR_ACTIVE_LATENCY_V1_8821C */ #define BIT_SHIFT_LTR_ACT_L_8821C 0 #define BIT_MASK_LTR_ACT_L_8821C 0xffffffffL -#define BIT_LTR_ACT_L_8821C(x) (((x) & BIT_MASK_LTR_ACT_L_8821C) << BIT_SHIFT_LTR_ACT_L_8821C) -#define BIT_GET_LTR_ACT_L_8821C(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8821C) & BIT_MASK_LTR_ACT_L_8821C) - - +#define BIT_LTR_ACT_L_8821C(x) \ + (((x) & BIT_MASK_LTR_ACT_L_8821C) << BIT_SHIFT_LTR_ACT_L_8821C) +#define BITS_LTR_ACT_L_8821C \ + (BIT_MASK_LTR_ACT_L_8821C << BIT_SHIFT_LTR_ACT_L_8821C) +#define BIT_CLEAR_LTR_ACT_L_8821C(x) ((x) & (~BITS_LTR_ACT_L_8821C)) +#define BIT_GET_LTR_ACT_L_8821C(x) \ + (((x) >> BIT_SHIFT_LTR_ACT_L_8821C) & BIT_MASK_LTR_ACT_L_8821C) +#define BIT_SET_LTR_ACT_L_8821C(x, v) \ + (BIT_CLEAR_LTR_ACT_L_8821C(x) | BIT_LTR_ACT_L_8821C(v)) /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C */ #define BIT_SHIFT_TRAIN_STA_ADDR_0_8821C 0 #define BIT_MASK_TRAIN_STA_ADDR_0_8821C 0xffffffffL -#define BIT_TRAIN_STA_ADDR_0_8821C(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8821C) << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) -#define BIT_GET_TRAIN_STA_ADDR_0_8821C(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) & BIT_MASK_TRAIN_STA_ADDR_0_8821C) - - +#define BIT_TRAIN_STA_ADDR_0_8821C(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8821C) \ + << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) +#define BITS_TRAIN_STA_ADDR_0_8821C \ + (BIT_MASK_TRAIN_STA_ADDR_0_8821C << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) +#define BIT_CLEAR_TRAIN_STA_ADDR_0_8821C(x) \ + ((x) & (~BITS_TRAIN_STA_ADDR_0_8821C)) +#define BIT_GET_TRAIN_STA_ADDR_0_8821C(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) & \ + BIT_MASK_TRAIN_STA_ADDR_0_8821C) +#define BIT_SET_TRAIN_STA_ADDR_0_8821C(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_0_8821C(x) | BIT_TRAIN_STA_ADDR_0_8821C(v)) /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C */ #define BIT_APPEND_MACID_IN_RESP_EN_1_8821C BIT(18) @@ -11014,18 +18468,34 @@ #define BIT_SHIFT_TRAIN_STA_ADDR_1_8821C 0 #define BIT_MASK_TRAIN_STA_ADDR_1_8821C 0xffff -#define BIT_TRAIN_STA_ADDR_1_8821C(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8821C) << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) -#define BIT_GET_TRAIN_STA_ADDR_1_8821C(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) & BIT_MASK_TRAIN_STA_ADDR_1_8821C) - - +#define BIT_TRAIN_STA_ADDR_1_8821C(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8821C) \ + << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) +#define BITS_TRAIN_STA_ADDR_1_8821C \ + (BIT_MASK_TRAIN_STA_ADDR_1_8821C << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) +#define BIT_CLEAR_TRAIN_STA_ADDR_1_8821C(x) \ + ((x) & (~BITS_TRAIN_STA_ADDR_1_8821C)) +#define BIT_GET_TRAIN_STA_ADDR_1_8821C(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) & \ + BIT_MASK_TRAIN_STA_ADDR_1_8821C) +#define BIT_SET_TRAIN_STA_ADDR_1_8821C(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_1_8821C(x) | BIT_TRAIN_STA_ADDR_1_8821C(v)) /* 2 REG_WMAC_PKTCNT_RWD_8821C */ #define BIT_SHIFT_PKTCNT_BSSIDMAP_8821C 4 #define BIT_MASK_PKTCNT_BSSIDMAP_8821C 0xf -#define BIT_PKTCNT_BSSIDMAP_8821C(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) -#define BIT_GET_PKTCNT_BSSIDMAP_8821C(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) - +#define BIT_PKTCNT_BSSIDMAP_8821C(x) \ + (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) \ + << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) +#define BITS_PKTCNT_BSSIDMAP_8821C \ + (BIT_MASK_PKTCNT_BSSIDMAP_8821C << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) +#define BIT_CLEAR_PKTCNT_BSSIDMAP_8821C(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8821C)) +#define BIT_GET_PKTCNT_BSSIDMAP_8821C(x) \ + (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) & \ + BIT_MASK_PKTCNT_BSSIDMAP_8821C) +#define BIT_SET_PKTCNT_BSSIDMAP_8821C(x, v) \ + (BIT_CLEAR_PKTCNT_BSSIDMAP_8821C(x) | BIT_PKTCNT_BSSIDMAP_8821C(v)) #define BIT_PKTCNT_CNTRST_8821C BIT(1) #define BIT_PKTCNT_CNTEN_8821C BIT(0) @@ -11036,40 +18506,77 @@ #define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C 0 #define BIT_MASK_WMAC_PKTCNT_CFGAD_8821C 0xff -#define BIT_WMAC_PKTCNT_CFGAD_8821C(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) -#define BIT_GET_WMAC_PKTCNT_CFGAD_8821C(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) - - +#define BIT_WMAC_PKTCNT_CFGAD_8821C(x) \ + (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) \ + << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) +#define BITS_WMAC_PKTCNT_CFGAD_8821C \ + (BIT_MASK_WMAC_PKTCNT_CFGAD_8821C << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) +#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8821C(x) \ + ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8821C)) +#define BIT_GET_WMAC_PKTCNT_CFGAD_8821C(x) \ + (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) & \ + BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) +#define BIT_SET_WMAC_PKTCNT_CFGAD_8821C(x, v) \ + (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8821C(x) | BIT_WMAC_PKTCNT_CFGAD_8821C(v)) /* 2 REG_IQ_DUMP_8821C */ -#define BIT_SHIFT_DUMP_OK_ADDR_8821C 15 -#define BIT_MASK_DUMP_OK_ADDR_8821C 0x1ffff -#define BIT_DUMP_OK_ADDR_8821C(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8821C) << BIT_SHIFT_DUMP_OK_ADDR_8821C) -#define BIT_GET_DUMP_OK_ADDR_8821C(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8821C) & BIT_MASK_DUMP_OK_ADDR_8821C) - - +#define BIT_SHIFT_DUMP_OK_ADDR_8821C 16 +#define BIT_MASK_DUMP_OK_ADDR_8821C 0xffff +#define BIT_DUMP_OK_ADDR_8821C(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR_8821C) << BIT_SHIFT_DUMP_OK_ADDR_8821C) +#define BITS_DUMP_OK_ADDR_8821C \ + (BIT_MASK_DUMP_OK_ADDR_8821C << BIT_SHIFT_DUMP_OK_ADDR_8821C) +#define BIT_CLEAR_DUMP_OK_ADDR_8821C(x) ((x) & (~BITS_DUMP_OK_ADDR_8821C)) +#define BIT_GET_DUMP_OK_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8821C) & BIT_MASK_DUMP_OK_ADDR_8821C) +#define BIT_SET_DUMP_OK_ADDR_8821C(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR_8821C(x) | BIT_DUMP_OK_ADDR_8821C(v)) #define BIT_SHIFT_R_TRIG_TIME_SEL_8821C 8 #define BIT_MASK_R_TRIG_TIME_SEL_8821C 0x7f -#define BIT_R_TRIG_TIME_SEL_8821C(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8821C) << BIT_SHIFT_R_TRIG_TIME_SEL_8821C) -#define BIT_GET_R_TRIG_TIME_SEL_8821C(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8821C) & BIT_MASK_R_TRIG_TIME_SEL_8821C) - - +#define BIT_R_TRIG_TIME_SEL_8821C(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL_8821C) \ + << BIT_SHIFT_R_TRIG_TIME_SEL_8821C) +#define BITS_R_TRIG_TIME_SEL_8821C \ + (BIT_MASK_R_TRIG_TIME_SEL_8821C << BIT_SHIFT_R_TRIG_TIME_SEL_8821C) +#define BIT_CLEAR_R_TRIG_TIME_SEL_8821C(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8821C)) +#define BIT_GET_R_TRIG_TIME_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8821C) & \ + BIT_MASK_R_TRIG_TIME_SEL_8821C) +#define BIT_SET_R_TRIG_TIME_SEL_8821C(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL_8821C(x) | BIT_R_TRIG_TIME_SEL_8821C(v)) #define BIT_SHIFT_R_MAC_TRIG_SEL_8821C 6 #define BIT_MASK_R_MAC_TRIG_SEL_8821C 0x3 -#define BIT_R_MAC_TRIG_SEL_8821C(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8821C) << BIT_SHIFT_R_MAC_TRIG_SEL_8821C) -#define BIT_GET_R_MAC_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8821C) & BIT_MASK_R_MAC_TRIG_SEL_8821C) - +#define BIT_R_MAC_TRIG_SEL_8821C(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL_8821C) \ + << BIT_SHIFT_R_MAC_TRIG_SEL_8821C) +#define BITS_R_MAC_TRIG_SEL_8821C \ + (BIT_MASK_R_MAC_TRIG_SEL_8821C << BIT_SHIFT_R_MAC_TRIG_SEL_8821C) +#define BIT_CLEAR_R_MAC_TRIG_SEL_8821C(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8821C)) +#define BIT_GET_R_MAC_TRIG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8821C) & \ + BIT_MASK_R_MAC_TRIG_SEL_8821C) +#define BIT_SET_R_MAC_TRIG_SEL_8821C(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL_8821C(x) | BIT_R_MAC_TRIG_SEL_8821C(v)) #define BIT_MAC_TRIG_REG_8821C BIT(5) #define BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C 3 #define BIT_MASK_R_LEVEL_PULSE_SEL_8821C 0x3 -#define BIT_R_LEVEL_PULSE_SEL_8821C(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) -#define BIT_GET_R_LEVEL_PULSE_SEL_8821C(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) - +#define BIT_R_LEVEL_PULSE_SEL_8821C(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) \ + << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) +#define BITS_R_LEVEL_PULSE_SEL_8821C \ + (BIT_MASK_R_LEVEL_PULSE_SEL_8821C << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8821C(x) \ + ((x) & (~BITS_R_LEVEL_PULSE_SEL_8821C)) +#define BIT_GET_R_LEVEL_PULSE_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) & \ + BIT_MASK_R_LEVEL_PULSE_SEL_8821C) +#define BIT_SET_R_LEVEL_PULSE_SEL_8821C(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL_8821C(x) | BIT_R_LEVEL_PULSE_SEL_8821C(v)) #define BIT_EN_LA_MAC_8821C BIT(2) #define BIT_R_EN_IQDUMP_8821C BIT(1) @@ -11079,19 +18586,39 @@ #define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C 0 #define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC_1_8821C(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) -#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) - - +#define BIT_R_WMAC_MASK_LA_MAC_1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) +#define BITS_R_WMAC_MASK_LA_MAC_1_8821C \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8821C(x) \ + ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8821C)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) +#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8821C(x) | \ + BIT_R_WMAC_MASK_LA_MAC_1_8821C(v)) /* 2 REG_IQ_DUMP_2_8821C */ #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C 0 #define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC_2_8821C(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) -#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) - - +#define BIT_R_WMAC_MATCH_REF_MAC_2_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) +#define BITS_R_WMAC_MATCH_REF_MAC_2_8821C \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8821C(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8821C)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8821C(x) | \ + BIT_R_WMAC_MATCH_REF_MAC_2_8821C(v)) /* 2 REG_WMAC_FTM_CTL_8821C */ #define BIT_RXFTM_TXACK_SC_8821C BIT(6) @@ -11107,25 +18634,46 @@ #define BIT_SHIFT_R_OFDM_LEN_8821C 26 #define BIT_MASK_R_OFDM_LEN_8821C 0x3f -#define BIT_R_OFDM_LEN_8821C(x) (((x) & BIT_MASK_R_OFDM_LEN_8821C) << BIT_SHIFT_R_OFDM_LEN_8821C) -#define BIT_GET_R_OFDM_LEN_8821C(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8821C) & BIT_MASK_R_OFDM_LEN_8821C) - - +#define BIT_R_OFDM_LEN_8821C(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_8821C) << BIT_SHIFT_R_OFDM_LEN_8821C) +#define BITS_R_OFDM_LEN_8821C \ + (BIT_MASK_R_OFDM_LEN_8821C << BIT_SHIFT_R_OFDM_LEN_8821C) +#define BIT_CLEAR_R_OFDM_LEN_8821C(x) ((x) & (~BITS_R_OFDM_LEN_8821C)) +#define BIT_GET_R_OFDM_LEN_8821C(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_8821C) & BIT_MASK_R_OFDM_LEN_8821C) +#define BIT_SET_R_OFDM_LEN_8821C(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_8821C(x) | BIT_R_OFDM_LEN_8821C(v)) #define BIT_SHIFT_R_CCK_LEN_8821C 0 #define BIT_MASK_R_CCK_LEN_8821C 0xffff -#define BIT_R_CCK_LEN_8821C(x) (((x) & BIT_MASK_R_CCK_LEN_8821C) << BIT_SHIFT_R_CCK_LEN_8821C) -#define BIT_GET_R_CCK_LEN_8821C(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8821C) & BIT_MASK_R_CCK_LEN_8821C) - - +#define BIT_R_CCK_LEN_8821C(x) \ + (((x) & BIT_MASK_R_CCK_LEN_8821C) << BIT_SHIFT_R_CCK_LEN_8821C) +#define BITS_R_CCK_LEN_8821C \ + (BIT_MASK_R_CCK_LEN_8821C << BIT_SHIFT_R_CCK_LEN_8821C) +#define BIT_CLEAR_R_CCK_LEN_8821C(x) ((x) & (~BITS_R_CCK_LEN_8821C)) +#define BIT_GET_R_CCK_LEN_8821C(x) \ + (((x) >> BIT_SHIFT_R_CCK_LEN_8821C) & BIT_MASK_R_CCK_LEN_8821C) +#define BIT_SET_R_CCK_LEN_8821C(x, v) \ + (BIT_CLEAR_R_CCK_LEN_8821C(x) | BIT_R_CCK_LEN_8821C(v)) /* 2 REG_WMAC_OPTION_FUNCTION_1_8821C */ #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C 24 #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) - +#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) +#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8821C \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8821C)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) | \ + BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(v)) #define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8821C BIT(23) #define BIT_R_WMAC_RXRST_DLY_1_8821C BIT(22) @@ -11156,10 +18704,20 @@ #define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C 0 #define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C 0xffff -#define BIT_R_WMAC_RX_FIL_LEN_2_8821C(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) -#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) - - +#define BIT_R_WMAC_RX_FIL_LEN_2_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) +#define BITS_R_WMAC_RX_FIL_LEN_2_8821C \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8821C(x) \ + ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8821C)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) & \ + BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) +#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8821C(x) | \ + BIT_R_WMAC_RX_FIL_LEN_2_8821C(v)) /* 2 REG_RX_FILTER_FUNCTION_8821C */ #define BIT_R_WMAC_MHRDDY_LATCH_8821C BIT(14) @@ -11184,35 +18742,60 @@ #define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C 0 #define BIT_MASK_R_WMAC_TXNDP_SIGB_8821C 0x1fffff -#define BIT_R_WMAC_TXNDP_SIGB_8821C(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) -#define BIT_GET_R_WMAC_TXNDP_SIGB_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) - - +#define BIT_R_WMAC_TXNDP_SIGB_8821C(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) \ + << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) +#define BITS_R_WMAC_TXNDP_SIGB_8821C \ + (BIT_MASK_R_WMAC_TXNDP_SIGB_8821C << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8821C(x) \ + ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8821C)) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8821C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) & \ + BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) +#define BIT_SET_R_WMAC_TXNDP_SIGB_8821C(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8821C(x) | BIT_R_WMAC_TXNDP_SIGB_8821C(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8821C */ #define BIT_SHIFT_R_MAC_DBG_SHIFT_8821C 8 #define BIT_MASK_R_MAC_DBG_SHIFT_8821C 0x7 -#define BIT_R_MAC_DBG_SHIFT_8821C(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8821C) << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) -#define BIT_GET_R_MAC_DBG_SHIFT_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) & BIT_MASK_R_MAC_DBG_SHIFT_8821C) - - +#define BIT_R_MAC_DBG_SHIFT_8821C(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8821C) \ + << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) +#define BITS_R_MAC_DBG_SHIFT_8821C \ + (BIT_MASK_R_MAC_DBG_SHIFT_8821C << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) +#define BIT_CLEAR_R_MAC_DBG_SHIFT_8821C(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8821C)) +#define BIT_GET_R_MAC_DBG_SHIFT_8821C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) & \ + BIT_MASK_R_MAC_DBG_SHIFT_8821C) +#define BIT_SET_R_MAC_DBG_SHIFT_8821C(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT_8821C(x) | BIT_R_MAC_DBG_SHIFT_8821C(v)) #define BIT_SHIFT_R_MAC_DBG_SEL_8821C 0 #define BIT_MASK_R_MAC_DBG_SEL_8821C 0x3 -#define BIT_R_MAC_DBG_SEL_8821C(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8821C) << BIT_SHIFT_R_MAC_DBG_SEL_8821C) -#define BIT_GET_R_MAC_DBG_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8821C) & BIT_MASK_R_MAC_DBG_SEL_8821C) - - +#define BIT_R_MAC_DBG_SEL_8821C(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL_8821C) << BIT_SHIFT_R_MAC_DBG_SEL_8821C) +#define BITS_R_MAC_DBG_SEL_8821C \ + (BIT_MASK_R_MAC_DBG_SEL_8821C << BIT_SHIFT_R_MAC_DBG_SEL_8821C) +#define BIT_CLEAR_R_MAC_DBG_SEL_8821C(x) ((x) & (~BITS_R_MAC_DBG_SEL_8821C)) +#define BIT_GET_R_MAC_DBG_SEL_8821C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8821C) & BIT_MASK_R_MAC_DBG_SEL_8821C) +#define BIT_SET_R_MAC_DBG_SEL_8821C(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL_8821C(x) | BIT_R_MAC_DBG_SEL_8821C(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C */ #define BIT_SHIFT_R_MAC_DEBUG_1_8821C 0 #define BIT_MASK_R_MAC_DEBUG_1_8821C 0xffffffffL -#define BIT_R_MAC_DEBUG_1_8821C(x) (((x) & BIT_MASK_R_MAC_DEBUG_1_8821C) << BIT_SHIFT_R_MAC_DEBUG_1_8821C) -#define BIT_GET_R_MAC_DEBUG_1_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8821C) & BIT_MASK_R_MAC_DEBUG_1_8821C) - - +#define BIT_R_MAC_DEBUG_1_8821C(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_1_8821C) << BIT_SHIFT_R_MAC_DEBUG_1_8821C) +#define BITS_R_MAC_DEBUG_1_8821C \ + (BIT_MASK_R_MAC_DEBUG_1_8821C << BIT_SHIFT_R_MAC_DEBUG_1_8821C) +#define BIT_CLEAR_R_MAC_DEBUG_1_8821C(x) ((x) & (~BITS_R_MAC_DEBUG_1_8821C)) +#define BIT_GET_R_MAC_DEBUG_1_8821C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8821C) & BIT_MASK_R_MAC_DEBUG_1_8821C) +#define BIT_SET_R_MAC_DEBUG_1_8821C(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_1_8821C(x) | BIT_R_MAC_DEBUG_1_8821C(v)) /* 2 REG_WSEC_OPTION_8821C */ #define BIT_RXDEC_BM_MGNT_8821C BIT(22) @@ -11235,35 +18818,69 @@ #define BIT_SHIFT_WRITE_BYTE_EN_V1_8821C 16 #define BIT_MASK_WRITE_BYTE_EN_V1_8821C 0xf -#define BIT_WRITE_BYTE_EN_V1_8821C(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8821C) << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) -#define BIT_GET_WRITE_BYTE_EN_V1_8821C(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) & BIT_MASK_WRITE_BYTE_EN_V1_8821C) - - +#define BIT_WRITE_BYTE_EN_V1_8821C(x) \ + (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8821C) \ + << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) +#define BITS_WRITE_BYTE_EN_V1_8821C \ + (BIT_MASK_WRITE_BYTE_EN_V1_8821C << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) +#define BIT_CLEAR_WRITE_BYTE_EN_V1_8821C(x) \ + ((x) & (~BITS_WRITE_BYTE_EN_V1_8821C)) +#define BIT_GET_WRITE_BYTE_EN_V1_8821C(x) \ + (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) & \ + BIT_MASK_WRITE_BYTE_EN_V1_8821C) +#define BIT_SET_WRITE_BYTE_EN_V1_8821C(x, v) \ + (BIT_CLEAR_WRITE_BYTE_EN_V1_8821C(x) | BIT_WRITE_BYTE_EN_V1_8821C(v)) #define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C 0 #define BIT_MASK_LTECOEX_REG_ADDR_V1_8821C 0xffff -#define BIT_LTECOEX_REG_ADDR_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) -#define BIT_GET_LTECOEX_REG_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) - - +#define BIT_LTECOEX_REG_ADDR_V1_8821C(x) \ + (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) +#define BITS_LTECOEX_REG_ADDR_V1_8821C \ + (BIT_MASK_LTECOEX_REG_ADDR_V1_8821C \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) +#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8821C(x) \ + ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8821C)) +#define BIT_GET_LTECOEX_REG_ADDR_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) & \ + BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) +#define BIT_SET_LTECOEX_REG_ADDR_V1_8821C(x, v) \ + (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8821C(x) | \ + BIT_LTECOEX_REG_ADDR_V1_8821C(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C */ #define BIT_SHIFT_LTECOEX_W_DATA_V1_8821C 0 #define BIT_MASK_LTECOEX_W_DATA_V1_8821C 0xffffffffL -#define BIT_LTECOEX_W_DATA_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8821C) << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) -#define BIT_GET_LTECOEX_W_DATA_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) & BIT_MASK_LTECOEX_W_DATA_V1_8821C) - - +#define BIT_LTECOEX_W_DATA_V1_8821C(x) \ + (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8821C) \ + << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) +#define BITS_LTECOEX_W_DATA_V1_8821C \ + (BIT_MASK_LTECOEX_W_DATA_V1_8821C << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) +#define BIT_CLEAR_LTECOEX_W_DATA_V1_8821C(x) \ + ((x) & (~BITS_LTECOEX_W_DATA_V1_8821C)) +#define BIT_GET_LTECOEX_W_DATA_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) & \ + BIT_MASK_LTECOEX_W_DATA_V1_8821C) +#define BIT_SET_LTECOEX_W_DATA_V1_8821C(x, v) \ + (BIT_CLEAR_LTECOEX_W_DATA_V1_8821C(x) | BIT_LTECOEX_W_DATA_V1_8821C(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C */ #define BIT_SHIFT_LTECOEX_R_DATA_V1_8821C 0 #define BIT_MASK_LTECOEX_R_DATA_V1_8821C 0xffffffffL -#define BIT_LTECOEX_R_DATA_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8821C) << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) -#define BIT_GET_LTECOEX_R_DATA_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) & BIT_MASK_LTECOEX_R_DATA_V1_8821C) - - +#define BIT_LTECOEX_R_DATA_V1_8821C(x) \ + (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8821C) \ + << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) +#define BITS_LTECOEX_R_DATA_V1_8821C \ + (BIT_MASK_LTECOEX_R_DATA_V1_8821C << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) +#define BIT_CLEAR_LTECOEX_R_DATA_V1_8821C(x) \ + ((x) & (~BITS_LTECOEX_R_DATA_V1_8821C)) +#define BIT_GET_LTECOEX_R_DATA_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) & \ + BIT_MASK_LTECOEX_R_DATA_V1_8821C) +#define BIT_SET_LTECOEX_R_DATA_V1_8821C(x, v) \ + (BIT_CLEAR_LTECOEX_R_DATA_V1_8821C(x) | BIT_LTECOEX_R_DATA_V1_8821C(v)) /* 2 REG_NOT_VALID_8821C */ @@ -11391,16 +19008,26 @@ #define BIT_SHIFT_SDIO_INT_TIMEOUT_8821C 16 #define BIT_MASK_SDIO_INT_TIMEOUT_8821C 0xffff -#define BIT_SDIO_INT_TIMEOUT_8821C(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) -#define BIT_GET_SDIO_INT_TIMEOUT_8821C(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) - +#define BIT_SDIO_INT_TIMEOUT_8821C(x) \ + (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) \ + << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) +#define BITS_SDIO_INT_TIMEOUT_8821C \ + (BIT_MASK_SDIO_INT_TIMEOUT_8821C << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) +#define BIT_CLEAR_SDIO_INT_TIMEOUT_8821C(x) \ + ((x) & (~BITS_SDIO_INT_TIMEOUT_8821C)) +#define BIT_GET_SDIO_INT_TIMEOUT_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) & \ + BIT_MASK_SDIO_INT_TIMEOUT_8821C) +#define BIT_SET_SDIO_INT_TIMEOUT_8821C(x, v) \ + (BIT_CLEAR_SDIO_INT_TIMEOUT_8821C(x) | BIT_SDIO_INT_TIMEOUT_8821C(v)) #define BIT_IO_ERR_STATUS_8821C BIT(15) #define BIT_REPLY_ERRCRC_IN_DATA_8821C BIT(9) #define BIT_EN_CMD53_OVERLAP_8821C BIT(8) #define BIT_REPLY_ERR_IN_R5_8821C BIT(7) #define BIT_R18A_EN_8821C BIT(6) -#define BIT_INIT_CMD_EN_8821C BIT(5) +#define BIT_SDIO_CMD_FORCE_VLD_8821C BIT(5) +#define BIT_INIT_CMD_EN_8821C BIT(4) #define BIT_EN_RXDMA_MASK_INT_8821C BIT(2) #define BIT_EN_MASK_TIMER_8821C BIT(1) #define BIT_CMD_ERR_STOP_INT_EN_8821C BIT(0) @@ -11461,95 +19088,155 @@ #define BIT_SHIFT_RX_REQ_LEN_V1_8821C 0 #define BIT_MASK_RX_REQ_LEN_V1_8821C 0x3ffff -#define BIT_RX_REQ_LEN_V1_8821C(x) (((x) & BIT_MASK_RX_REQ_LEN_V1_8821C) << BIT_SHIFT_RX_REQ_LEN_V1_8821C) -#define BIT_GET_RX_REQ_LEN_V1_8821C(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8821C) & BIT_MASK_RX_REQ_LEN_V1_8821C) - - +#define BIT_RX_REQ_LEN_V1_8821C(x) \ + (((x) & BIT_MASK_RX_REQ_LEN_V1_8821C) << BIT_SHIFT_RX_REQ_LEN_V1_8821C) +#define BITS_RX_REQ_LEN_V1_8821C \ + (BIT_MASK_RX_REQ_LEN_V1_8821C << BIT_SHIFT_RX_REQ_LEN_V1_8821C) +#define BIT_CLEAR_RX_REQ_LEN_V1_8821C(x) ((x) & (~BITS_RX_REQ_LEN_V1_8821C)) +#define BIT_GET_RX_REQ_LEN_V1_8821C(x) \ + (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8821C) & BIT_MASK_RX_REQ_LEN_V1_8821C) +#define BIT_SET_RX_REQ_LEN_V1_8821C(x, v) \ + (BIT_CLEAR_RX_REQ_LEN_V1_8821C(x) | BIT_RX_REQ_LEN_V1_8821C(v)) /* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8821C */ #define BIT_SHIFT_FREE_TXPG_SEQ_8821C 0 #define BIT_MASK_FREE_TXPG_SEQ_8821C 0xff -#define BIT_FREE_TXPG_SEQ_8821C(x) (((x) & BIT_MASK_FREE_TXPG_SEQ_8821C) << BIT_SHIFT_FREE_TXPG_SEQ_8821C) -#define BIT_GET_FREE_TXPG_SEQ_8821C(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8821C) & BIT_MASK_FREE_TXPG_SEQ_8821C) - - +#define BIT_FREE_TXPG_SEQ_8821C(x) \ + (((x) & BIT_MASK_FREE_TXPG_SEQ_8821C) << BIT_SHIFT_FREE_TXPG_SEQ_8821C) +#define BITS_FREE_TXPG_SEQ_8821C \ + (BIT_MASK_FREE_TXPG_SEQ_8821C << BIT_SHIFT_FREE_TXPG_SEQ_8821C) +#define BIT_CLEAR_FREE_TXPG_SEQ_8821C(x) ((x) & (~BITS_FREE_TXPG_SEQ_8821C)) +#define BIT_GET_FREE_TXPG_SEQ_8821C(x) \ + (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8821C) & BIT_MASK_FREE_TXPG_SEQ_8821C) +#define BIT_SET_FREE_TXPG_SEQ_8821C(x, v) \ + (BIT_CLEAR_FREE_TXPG_SEQ_8821C(x) | BIT_FREE_TXPG_SEQ_8821C(v)) /* 2 REG_SDIO_FREE_TXPG_8821C */ #define BIT_SHIFT_MID_FREEPG_V1_8821C 16 #define BIT_MASK_MID_FREEPG_V1_8821C 0xfff -#define BIT_MID_FREEPG_V1_8821C(x) (((x) & BIT_MASK_MID_FREEPG_V1_8821C) << BIT_SHIFT_MID_FREEPG_V1_8821C) -#define BIT_GET_MID_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8821C) & BIT_MASK_MID_FREEPG_V1_8821C) - - +#define BIT_MID_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_MID_FREEPG_V1_8821C) << BIT_SHIFT_MID_FREEPG_V1_8821C) +#define BITS_MID_FREEPG_V1_8821C \ + (BIT_MASK_MID_FREEPG_V1_8821C << BIT_SHIFT_MID_FREEPG_V1_8821C) +#define BIT_CLEAR_MID_FREEPG_V1_8821C(x) ((x) & (~BITS_MID_FREEPG_V1_8821C)) +#define BIT_GET_MID_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_MID_FREEPG_V1_8821C) & BIT_MASK_MID_FREEPG_V1_8821C) +#define BIT_SET_MID_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_MID_FREEPG_V1_8821C(x) | BIT_MID_FREEPG_V1_8821C(v)) #define BIT_SHIFT_HIQ_FREEPG_V1_8821C 0 #define BIT_MASK_HIQ_FREEPG_V1_8821C 0xfff -#define BIT_HIQ_FREEPG_V1_8821C(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8821C) << BIT_SHIFT_HIQ_FREEPG_V1_8821C) -#define BIT_GET_HIQ_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8821C) & BIT_MASK_HIQ_FREEPG_V1_8821C) - - +#define BIT_HIQ_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_HIQ_FREEPG_V1_8821C) << BIT_SHIFT_HIQ_FREEPG_V1_8821C) +#define BITS_HIQ_FREEPG_V1_8821C \ + (BIT_MASK_HIQ_FREEPG_V1_8821C << BIT_SHIFT_HIQ_FREEPG_V1_8821C) +#define BIT_CLEAR_HIQ_FREEPG_V1_8821C(x) ((x) & (~BITS_HIQ_FREEPG_V1_8821C)) +#define BIT_GET_HIQ_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8821C) & BIT_MASK_HIQ_FREEPG_V1_8821C) +#define BIT_SET_HIQ_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_HIQ_FREEPG_V1_8821C(x) | BIT_HIQ_FREEPG_V1_8821C(v)) /* 2 REG_SDIO_FREE_TXPG2_8821C */ #define BIT_SHIFT_PUB_FREEPG_V1_8821C 16 #define BIT_MASK_PUB_FREEPG_V1_8821C 0xfff -#define BIT_PUB_FREEPG_V1_8821C(x) (((x) & BIT_MASK_PUB_FREEPG_V1_8821C) << BIT_SHIFT_PUB_FREEPG_V1_8821C) -#define BIT_GET_PUB_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8821C) & BIT_MASK_PUB_FREEPG_V1_8821C) - - +#define BIT_PUB_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_PUB_FREEPG_V1_8821C) << BIT_SHIFT_PUB_FREEPG_V1_8821C) +#define BITS_PUB_FREEPG_V1_8821C \ + (BIT_MASK_PUB_FREEPG_V1_8821C << BIT_SHIFT_PUB_FREEPG_V1_8821C) +#define BIT_CLEAR_PUB_FREEPG_V1_8821C(x) ((x) & (~BITS_PUB_FREEPG_V1_8821C)) +#define BIT_GET_PUB_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8821C) & BIT_MASK_PUB_FREEPG_V1_8821C) +#define BIT_SET_PUB_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_PUB_FREEPG_V1_8821C(x) | BIT_PUB_FREEPG_V1_8821C(v)) #define BIT_SHIFT_LOW_FREEPG_V1_8821C 0 #define BIT_MASK_LOW_FREEPG_V1_8821C 0xfff -#define BIT_LOW_FREEPG_V1_8821C(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8821C) << BIT_SHIFT_LOW_FREEPG_V1_8821C) -#define BIT_GET_LOW_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8821C) & BIT_MASK_LOW_FREEPG_V1_8821C) - - +#define BIT_LOW_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_LOW_FREEPG_V1_8821C) << BIT_SHIFT_LOW_FREEPG_V1_8821C) +#define BITS_LOW_FREEPG_V1_8821C \ + (BIT_MASK_LOW_FREEPG_V1_8821C << BIT_SHIFT_LOW_FREEPG_V1_8821C) +#define BIT_CLEAR_LOW_FREEPG_V1_8821C(x) ((x) & (~BITS_LOW_FREEPG_V1_8821C)) +#define BIT_GET_LOW_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8821C) & BIT_MASK_LOW_FREEPG_V1_8821C) +#define BIT_SET_LOW_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_LOW_FREEPG_V1_8821C(x) | BIT_LOW_FREEPG_V1_8821C(v)) /* 2 REG_SDIO_OQT_FREE_TXPG_V1_8821C */ #define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C 24 #define BIT_MASK_NOAC_OQT_FREEPG_V1_8821C 0xff -#define BIT_NOAC_OQT_FREEPG_V1_8821C(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) -#define BIT_GET_NOAC_OQT_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) - - +#define BIT_NOAC_OQT_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) +#define BITS_NOAC_OQT_FREEPG_V1_8821C \ + (BIT_MASK_NOAC_OQT_FREEPG_V1_8821C \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) +#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8821C(x) \ + ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8821C)) +#define BIT_GET_NOAC_OQT_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) & \ + BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) +#define BIT_SET_NOAC_OQT_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8821C(x) | \ + BIT_NOAC_OQT_FREEPG_V1_8821C(v)) #define BIT_SHIFT_AC_OQT_FREEPG_V1_8821C 16 #define BIT_MASK_AC_OQT_FREEPG_V1_8821C 0xff -#define BIT_AC_OQT_FREEPG_V1_8821C(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) -#define BIT_GET_AC_OQT_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) - - +#define BIT_AC_OQT_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) \ + << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) +#define BITS_AC_OQT_FREEPG_V1_8821C \ + (BIT_MASK_AC_OQT_FREEPG_V1_8821C << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) +#define BIT_CLEAR_AC_OQT_FREEPG_V1_8821C(x) \ + ((x) & (~BITS_AC_OQT_FREEPG_V1_8821C)) +#define BIT_GET_AC_OQT_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) & \ + BIT_MASK_AC_OQT_FREEPG_V1_8821C) +#define BIT_SET_AC_OQT_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_AC_OQT_FREEPG_V1_8821C(x) | BIT_AC_OQT_FREEPG_V1_8821C(v)) #define BIT_SHIFT_EXQ_FREEPG_V1_8821C 0 #define BIT_MASK_EXQ_FREEPG_V1_8821C 0xfff -#define BIT_EXQ_FREEPG_V1_8821C(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8821C) << BIT_SHIFT_EXQ_FREEPG_V1_8821C) -#define BIT_GET_EXQ_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8821C) & BIT_MASK_EXQ_FREEPG_V1_8821C) - - +#define BIT_EXQ_FREEPG_V1_8821C(x) \ + (((x) & BIT_MASK_EXQ_FREEPG_V1_8821C) << BIT_SHIFT_EXQ_FREEPG_V1_8821C) +#define BITS_EXQ_FREEPG_V1_8821C \ + (BIT_MASK_EXQ_FREEPG_V1_8821C << BIT_SHIFT_EXQ_FREEPG_V1_8821C) +#define BIT_CLEAR_EXQ_FREEPG_V1_8821C(x) ((x) & (~BITS_EXQ_FREEPG_V1_8821C)) +#define BIT_GET_EXQ_FREEPG_V1_8821C(x) \ + (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8821C) & BIT_MASK_EXQ_FREEPG_V1_8821C) +#define BIT_SET_EXQ_FREEPG_V1_8821C(x, v) \ + (BIT_CLEAR_EXQ_FREEPG_V1_8821C(x) | BIT_EXQ_FREEPG_V1_8821C(v)) /* 2 REG_SDIO_HTSFR_INFO_8821C */ #define BIT_SHIFT_HTSFR1_8821C 16 #define BIT_MASK_HTSFR1_8821C 0xffff -#define BIT_HTSFR1_8821C(x) (((x) & BIT_MASK_HTSFR1_8821C) << BIT_SHIFT_HTSFR1_8821C) -#define BIT_GET_HTSFR1_8821C(x) (((x) >> BIT_SHIFT_HTSFR1_8821C) & BIT_MASK_HTSFR1_8821C) - - +#define BIT_HTSFR1_8821C(x) \ + (((x) & BIT_MASK_HTSFR1_8821C) << BIT_SHIFT_HTSFR1_8821C) +#define BITS_HTSFR1_8821C (BIT_MASK_HTSFR1_8821C << BIT_SHIFT_HTSFR1_8821C) +#define BIT_CLEAR_HTSFR1_8821C(x) ((x) & (~BITS_HTSFR1_8821C)) +#define BIT_GET_HTSFR1_8821C(x) \ + (((x) >> BIT_SHIFT_HTSFR1_8821C) & BIT_MASK_HTSFR1_8821C) +#define BIT_SET_HTSFR1_8821C(x, v) \ + (BIT_CLEAR_HTSFR1_8821C(x) | BIT_HTSFR1_8821C(v)) #define BIT_SHIFT_HTSFR0_8821C 0 #define BIT_MASK_HTSFR0_8821C 0xffff -#define BIT_HTSFR0_8821C(x) (((x) & BIT_MASK_HTSFR0_8821C) << BIT_SHIFT_HTSFR0_8821C) -#define BIT_GET_HTSFR0_8821C(x) (((x) >> BIT_SHIFT_HTSFR0_8821C) & BIT_MASK_HTSFR0_8821C) - - +#define BIT_HTSFR0_8821C(x) \ + (((x) & BIT_MASK_HTSFR0_8821C) << BIT_SHIFT_HTSFR0_8821C) +#define BITS_HTSFR0_8821C (BIT_MASK_HTSFR0_8821C << BIT_SHIFT_HTSFR0_8821C) +#define BIT_CLEAR_HTSFR0_8821C(x) ((x) & (~BITS_HTSFR0_8821C)) +#define BIT_GET_HTSFR0_8821C(x) \ + (((x) >> BIT_SHIFT_HTSFR0_8821C) & BIT_MASK_HTSFR0_8821C) +#define BIT_SET_HTSFR0_8821C(x, v) \ + (BIT_CLEAR_HTSFR0_8821C(x) | BIT_HTSFR0_8821C(v)) /* 2 REG_SDIO_HCPWM1_V2_8821C */ -#define BIT_TOGGLING_8821C BIT(7) -#define BIT_ACK_8821C BIT(6) -#define BIT_SYS_CLK_8821C BIT(0) +#define BIT_TOGGLE_8821C BIT(7) +#define BIT_CUR_PS_8821C BIT(0) /* 2 REG_SDIO_HCPWM2_V2_8821C */ @@ -11560,49 +19247,83 @@ #define BIT_SHIFT_INDIRECT_REG_SIZE_8821C 16 #define BIT_MASK_INDIRECT_REG_SIZE_8821C 0x3 -#define BIT_INDIRECT_REG_SIZE_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE_8821C) << BIT_SHIFT_INDIRECT_REG_SIZE_8821C) -#define BIT_GET_INDIRECT_REG_SIZE_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8821C) & BIT_MASK_INDIRECT_REG_SIZE_8821C) - - +#define BIT_INDIRECT_REG_SIZE_8821C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_SIZE_8821C) \ + << BIT_SHIFT_INDIRECT_REG_SIZE_8821C) +#define BITS_INDIRECT_REG_SIZE_8821C \ + (BIT_MASK_INDIRECT_REG_SIZE_8821C << BIT_SHIFT_INDIRECT_REG_SIZE_8821C) +#define BIT_CLEAR_INDIRECT_REG_SIZE_8821C(x) \ + ((x) & (~BITS_INDIRECT_REG_SIZE_8821C)) +#define BIT_GET_INDIRECT_REG_SIZE_8821C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8821C) & \ + BIT_MASK_INDIRECT_REG_SIZE_8821C) +#define BIT_SET_INDIRECT_REG_SIZE_8821C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_SIZE_8821C(x) | BIT_INDIRECT_REG_SIZE_8821C(v)) #define BIT_SHIFT_INDIRECT_REG_ADDR_8821C 0 #define BIT_MASK_INDIRECT_REG_ADDR_8821C 0xffff -#define BIT_INDIRECT_REG_ADDR_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8821C) << BIT_SHIFT_INDIRECT_REG_ADDR_8821C) -#define BIT_GET_INDIRECT_REG_ADDR_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8821C) & BIT_MASK_INDIRECT_REG_ADDR_8821C) - - +#define BIT_INDIRECT_REG_ADDR_8821C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_ADDR_8821C) \ + << BIT_SHIFT_INDIRECT_REG_ADDR_8821C) +#define BITS_INDIRECT_REG_ADDR_8821C \ + (BIT_MASK_INDIRECT_REG_ADDR_8821C << BIT_SHIFT_INDIRECT_REG_ADDR_8821C) +#define BIT_CLEAR_INDIRECT_REG_ADDR_8821C(x) \ + ((x) & (~BITS_INDIRECT_REG_ADDR_8821C)) +#define BIT_GET_INDIRECT_REG_ADDR_8821C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8821C) & \ + BIT_MASK_INDIRECT_REG_ADDR_8821C) +#define BIT_SET_INDIRECT_REG_ADDR_8821C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_ADDR_8821C(x) | BIT_INDIRECT_REG_ADDR_8821C(v)) /* 2 REG_SDIO_INDIRECT_REG_DATA_8821C */ #define BIT_SHIFT_INDIRECT_REG_DATA_8821C 0 #define BIT_MASK_INDIRECT_REG_DATA_8821C 0xffffffffL -#define BIT_INDIRECT_REG_DATA_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_DATA_8821C) << BIT_SHIFT_INDIRECT_REG_DATA_8821C) -#define BIT_GET_INDIRECT_REG_DATA_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8821C) & BIT_MASK_INDIRECT_REG_DATA_8821C) - - +#define BIT_INDIRECT_REG_DATA_8821C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_DATA_8821C) \ + << BIT_SHIFT_INDIRECT_REG_DATA_8821C) +#define BITS_INDIRECT_REG_DATA_8821C \ + (BIT_MASK_INDIRECT_REG_DATA_8821C << BIT_SHIFT_INDIRECT_REG_DATA_8821C) +#define BIT_CLEAR_INDIRECT_REG_DATA_8821C(x) \ + ((x) & (~BITS_INDIRECT_REG_DATA_8821C)) +#define BIT_GET_INDIRECT_REG_DATA_8821C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8821C) & \ + BIT_MASK_INDIRECT_REG_DATA_8821C) +#define BIT_SET_INDIRECT_REG_DATA_8821C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_DATA_8821C(x) | BIT_INDIRECT_REG_DATA_8821C(v)) /* 2 REG_SDIO_H2C_8821C */ #define BIT_SHIFT_SDIO_H2C_MSG_8821C 0 #define BIT_MASK_SDIO_H2C_MSG_8821C 0xffffffffL -#define BIT_SDIO_H2C_MSG_8821C(x) (((x) & BIT_MASK_SDIO_H2C_MSG_8821C) << BIT_SHIFT_SDIO_H2C_MSG_8821C) -#define BIT_GET_SDIO_H2C_MSG_8821C(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8821C) & BIT_MASK_SDIO_H2C_MSG_8821C) - - +#define BIT_SDIO_H2C_MSG_8821C(x) \ + (((x) & BIT_MASK_SDIO_H2C_MSG_8821C) << BIT_SHIFT_SDIO_H2C_MSG_8821C) +#define BITS_SDIO_H2C_MSG_8821C \ + (BIT_MASK_SDIO_H2C_MSG_8821C << BIT_SHIFT_SDIO_H2C_MSG_8821C) +#define BIT_CLEAR_SDIO_H2C_MSG_8821C(x) ((x) & (~BITS_SDIO_H2C_MSG_8821C)) +#define BIT_GET_SDIO_H2C_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8821C) & BIT_MASK_SDIO_H2C_MSG_8821C) +#define BIT_SET_SDIO_H2C_MSG_8821C(x, v) \ + (BIT_CLEAR_SDIO_H2C_MSG_8821C(x) | BIT_SDIO_H2C_MSG_8821C(v)) /* 2 REG_SDIO_C2H_8821C */ #define BIT_SHIFT_SDIO_C2H_MSG_8821C 0 #define BIT_MASK_SDIO_C2H_MSG_8821C 0xffffffffL -#define BIT_SDIO_C2H_MSG_8821C(x) (((x) & BIT_MASK_SDIO_C2H_MSG_8821C) << BIT_SHIFT_SDIO_C2H_MSG_8821C) -#define BIT_GET_SDIO_C2H_MSG_8821C(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8821C) & BIT_MASK_SDIO_C2H_MSG_8821C) - - +#define BIT_SDIO_C2H_MSG_8821C(x) \ + (((x) & BIT_MASK_SDIO_C2H_MSG_8821C) << BIT_SHIFT_SDIO_C2H_MSG_8821C) +#define BITS_SDIO_C2H_MSG_8821C \ + (BIT_MASK_SDIO_C2H_MSG_8821C << BIT_SHIFT_SDIO_C2H_MSG_8821C) +#define BIT_CLEAR_SDIO_C2H_MSG_8821C(x) ((x) & (~BITS_SDIO_C2H_MSG_8821C)) +#define BIT_GET_SDIO_C2H_MSG_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8821C) & BIT_MASK_SDIO_C2H_MSG_8821C) +#define BIT_SET_SDIO_C2H_MSG_8821C(x, v) \ + (BIT_CLEAR_SDIO_C2H_MSG_8821C(x) | BIT_SDIO_C2H_MSG_8821C(v)) /* 2 REG_SDIO_HRPWM1_8821C */ -#define BIT_TOGGLING_8821C BIT(7) +#define BIT_TOGGLE_8821C BIT(7) #define BIT_ACK_8821C BIT(6) -#define BIT_32K_PERMISSION_8821C BIT(0) +#define BIT_REQ_PS_8821C BIT(0) /* 2 REG_SDIO_HRPWM2_8821C */ @@ -11625,27 +19346,39 @@ #define BIT_SHIFT_CMDIN_2RESP_TIMER_8821C 0 #define BIT_MASK_CMDIN_2RESP_TIMER_8821C 0xffff -#define BIT_CMDIN_2RESP_TIMER_8821C(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8821C) << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) -#define BIT_GET_CMDIN_2RESP_TIMER_8821C(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) & BIT_MASK_CMDIN_2RESP_TIMER_8821C) - - +#define BIT_CMDIN_2RESP_TIMER_8821C(x) \ + (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8821C) \ + << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) +#define BITS_CMDIN_2RESP_TIMER_8821C \ + (BIT_MASK_CMDIN_2RESP_TIMER_8821C << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) +#define BIT_CLEAR_CMDIN_2RESP_TIMER_8821C(x) \ + ((x) & (~BITS_CMDIN_2RESP_TIMER_8821C)) +#define BIT_GET_CMDIN_2RESP_TIMER_8821C(x) \ + (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) & \ + BIT_MASK_CMDIN_2RESP_TIMER_8821C) +#define BIT_SET_CMDIN_2RESP_TIMER_8821C(x, v) \ + (BIT_CLEAR_CMDIN_2RESP_TIMER_8821C(x) | BIT_CMDIN_2RESP_TIMER_8821C(v)) /* 2 REG_SDIO_CMD_CRC_8821C */ #define BIT_SHIFT_SDIO_CMD_CRC_V1_8821C 0 #define BIT_MASK_SDIO_CMD_CRC_V1_8821C 0xff -#define BIT_SDIO_CMD_CRC_V1_8821C(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8821C) << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) -#define BIT_GET_SDIO_CMD_CRC_V1_8821C(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) & BIT_MASK_SDIO_CMD_CRC_V1_8821C) - - +#define BIT_SDIO_CMD_CRC_V1_8821C(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8821C) \ + << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) +#define BITS_SDIO_CMD_CRC_V1_8821C \ + (BIT_MASK_SDIO_CMD_CRC_V1_8821C << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) +#define BIT_CLEAR_SDIO_CMD_CRC_V1_8821C(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8821C)) +#define BIT_GET_SDIO_CMD_CRC_V1_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) & \ + BIT_MASK_SDIO_CMD_CRC_V1_8821C) +#define BIT_SET_SDIO_CMD_CRC_V1_8821C(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC_V1_8821C(x) | BIT_SDIO_CMD_CRC_V1_8821C(v)) /* 2 REG_SDIO_HSISR_8821C */ #define BIT_DRV_WLAN_INT_CLR_8821C BIT(1) #define BIT_DRV_WLAN_INT_8821C BIT(0) -/* 2 REG_SDIO_HSIMR_8821C */ -#define BIT_HISR_MASK_8821C BIT(0) - /* 2 REG_SDIO_ERR_RPT_8821C */ #define BIT_HR_FF_OVF_8821C BIT(6) #define BIT_HR_FF_UDN_8821C BIT(5) @@ -11659,28 +19392,53 @@ #define BIT_SHIFT_CMD_CRC_ERR_CNT_8821C 0 #define BIT_MASK_CMD_CRC_ERR_CNT_8821C 0xff -#define BIT_CMD_CRC_ERR_CNT_8821C(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8821C) << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) -#define BIT_GET_CMD_CRC_ERR_CNT_8821C(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) & BIT_MASK_CMD_CRC_ERR_CNT_8821C) - - +#define BIT_CMD_CRC_ERR_CNT_8821C(x) \ + (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8821C) \ + << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) +#define BITS_CMD_CRC_ERR_CNT_8821C \ + (BIT_MASK_CMD_CRC_ERR_CNT_8821C << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) +#define BIT_CLEAR_CMD_CRC_ERR_CNT_8821C(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8821C)) +#define BIT_GET_CMD_CRC_ERR_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) & \ + BIT_MASK_CMD_CRC_ERR_CNT_8821C) +#define BIT_SET_CMD_CRC_ERR_CNT_8821C(x, v) \ + (BIT_CLEAR_CMD_CRC_ERR_CNT_8821C(x) | BIT_CMD_CRC_ERR_CNT_8821C(v)) /* 2 REG_SDIO_DATA_ERRCNT_8821C */ #define BIT_SHIFT_DATA_CRC_ERR_CNT_8821C 0 #define BIT_MASK_DATA_CRC_ERR_CNT_8821C 0xff -#define BIT_DATA_CRC_ERR_CNT_8821C(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8821C) << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) -#define BIT_GET_DATA_CRC_ERR_CNT_8821C(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) & BIT_MASK_DATA_CRC_ERR_CNT_8821C) - - +#define BIT_DATA_CRC_ERR_CNT_8821C(x) \ + (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8821C) \ + << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) +#define BITS_DATA_CRC_ERR_CNT_8821C \ + (BIT_MASK_DATA_CRC_ERR_CNT_8821C << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) +#define BIT_CLEAR_DATA_CRC_ERR_CNT_8821C(x) \ + ((x) & (~BITS_DATA_CRC_ERR_CNT_8821C)) +#define BIT_GET_DATA_CRC_ERR_CNT_8821C(x) \ + (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) & \ + BIT_MASK_DATA_CRC_ERR_CNT_8821C) +#define BIT_SET_DATA_CRC_ERR_CNT_8821C(x, v) \ + (BIT_CLEAR_DATA_CRC_ERR_CNT_8821C(x) | BIT_DATA_CRC_ERR_CNT_8821C(v)) /* 2 REG_SDIO_CMD_ERR_CONTENT_8821C */ #define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C 0 #define BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C 0xffffffffffL -#define BIT_SDIO_CMD_ERR_CONTENT_8821C(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) -#define BIT_GET_SDIO_CMD_ERR_CONTENT_8821C(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) - - +#define BIT_SDIO_CMD_ERR_CONTENT_8821C(x) \ + (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) +#define BITS_SDIO_CMD_ERR_CONTENT_8821C \ + (BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) +#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8821C(x) \ + ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8821C)) +#define BIT_GET_SDIO_CMD_ERR_CONTENT_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) & \ + BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) +#define BIT_SET_SDIO_CMD_ERR_CONTENT_8821C(x, v) \ + (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8821C(x) | \ + BIT_SDIO_CMD_ERR_CONTENT_8821C(v)) /* 2 REG_SDIO_CRC_ERR_IDX_8821C */ #define BIT_D3_CRC_ERR_8821C BIT(4) @@ -11692,19 +19450,34 @@ /* 2 REG_SDIO_DATA_CRC_8821C */ #define BIT_SHIFT_SDIO_DATA_CRC_8821C 0 -#define BIT_MASK_SDIO_DATA_CRC_8821C 0xff -#define BIT_SDIO_DATA_CRC_8821C(x) (((x) & BIT_MASK_SDIO_DATA_CRC_8821C) << BIT_SHIFT_SDIO_DATA_CRC_8821C) -#define BIT_GET_SDIO_DATA_CRC_8821C(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8821C) & BIT_MASK_SDIO_DATA_CRC_8821C) - - +#define BIT_MASK_SDIO_DATA_CRC_8821C 0xffff +#define BIT_SDIO_DATA_CRC_8821C(x) \ + (((x) & BIT_MASK_SDIO_DATA_CRC_8821C) << BIT_SHIFT_SDIO_DATA_CRC_8821C) +#define BITS_SDIO_DATA_CRC_8821C \ + (BIT_MASK_SDIO_DATA_CRC_8821C << BIT_SHIFT_SDIO_DATA_CRC_8821C) +#define BIT_CLEAR_SDIO_DATA_CRC_8821C(x) ((x) & (~BITS_SDIO_DATA_CRC_8821C)) +#define BIT_GET_SDIO_DATA_CRC_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8821C) & BIT_MASK_SDIO_DATA_CRC_8821C) +#define BIT_SET_SDIO_DATA_CRC_8821C(x, v) \ + (BIT_CLEAR_SDIO_DATA_CRC_8821C(x) | BIT_SDIO_DATA_CRC_8821C(v)) /* 2 REG_SDIO_DATA_REPLY_TIME_8821C */ #define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C 0 #define BIT_MASK_SDIO_DATA_REPLY_TIME_8821C 0x7 -#define BIT_SDIO_DATA_REPLY_TIME_8821C(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) -#define BIT_GET_SDIO_DATA_REPLY_TIME_8821C(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) - - +#define BIT_SDIO_DATA_REPLY_TIME_8821C(x) \ + (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) +#define BITS_SDIO_DATA_REPLY_TIME_8821C \ + (BIT_MASK_SDIO_DATA_REPLY_TIME_8821C \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) +#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8821C(x) \ + ((x) & (~BITS_SDIO_DATA_REPLY_TIME_8821C)) +#define BIT_GET_SDIO_DATA_REPLY_TIME_8821C(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) & \ + BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) +#define BIT_SET_SDIO_DATA_REPLY_TIME_8821C(x, v) \ + (BIT_CLEAR_SDIO_DATA_REPLY_TIME_8821C(x) | \ + BIT_SDIO_DATA_REPLY_TIME_8821C(v)) #endif diff --git a/hal/halmac/halmac_bit_8822b.h b/hal/halmac/halmac_bit_8822b.h index b31b935..0b29665 100644 --- a/hal/halmac/halmac_bit_8822b.h +++ b/hal/halmac/halmac_bit_8822b.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_BIT_8822B_H #define __INC_HALMAC_BIT_8822B_H @@ -91,16 +106,25 @@ #define BIT_SHIFT_VPDIDX_8822B 8 #define BIT_MASK_VPDIDX_8822B 0xff -#define BIT_VPDIDX_8822B(x) (((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B) -#define BIT_GET_VPDIDX_8822B(x) (((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B) - - +#define BIT_VPDIDX_8822B(x) \ + (((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B) +#define BITS_VPDIDX_8822B (BIT_MASK_VPDIDX_8822B << BIT_SHIFT_VPDIDX_8822B) +#define BIT_CLEAR_VPDIDX_8822B(x) ((x) & (~BITS_VPDIDX_8822B)) +#define BIT_GET_VPDIDX_8822B(x) \ + (((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B) +#define BIT_SET_VPDIDX_8822B(x, v) \ + (BIT_CLEAR_VPDIDX_8822B(x) | BIT_VPDIDX_8822B(v)) #define BIT_SHIFT_EEM1_0_8822B 6 #define BIT_MASK_EEM1_0_8822B 0x3 -#define BIT_EEM1_0_8822B(x) (((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B) -#define BIT_GET_EEM1_0_8822B(x) (((x) >> BIT_SHIFT_EEM1_0_8822B) & BIT_MASK_EEM1_0_8822B) - +#define BIT_EEM1_0_8822B(x) \ + (((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B) +#define BITS_EEM1_0_8822B (BIT_MASK_EEM1_0_8822B << BIT_SHIFT_EEM1_0_8822B) +#define BIT_CLEAR_EEM1_0_8822B(x) ((x) & (~BITS_EEM1_0_8822B)) +#define BIT_GET_EEM1_0_8822B(x) \ + (((x) >> BIT_SHIFT_EEM1_0_8822B) & BIT_MASK_EEM1_0_8822B) +#define BIT_SET_EEM1_0_8822B(x, v) \ + (BIT_CLEAR_EEM1_0_8822B(x) | BIT_EEM1_0_8822B(v)) #define BIT_AUTOLOAD_SUS_8822B BIT(5) #define BIT_EERPOMSEL_8822B BIT(4) @@ -113,10 +137,15 @@ #define BIT_SHIFT_VPD_DATA_8822B 0 #define BIT_MASK_VPD_DATA_8822B 0xffffffffL -#define BIT_VPD_DATA_8822B(x) (((x) & BIT_MASK_VPD_DATA_8822B) << BIT_SHIFT_VPD_DATA_8822B) -#define BIT_GET_VPD_DATA_8822B(x) (((x) >> BIT_SHIFT_VPD_DATA_8822B) & BIT_MASK_VPD_DATA_8822B) - - +#define BIT_VPD_DATA_8822B(x) \ + (((x) & BIT_MASK_VPD_DATA_8822B) << BIT_SHIFT_VPD_DATA_8822B) +#define BITS_VPD_DATA_8822B \ + (BIT_MASK_VPD_DATA_8822B << BIT_SHIFT_VPD_DATA_8822B) +#define BIT_CLEAR_VPD_DATA_8822B(x) ((x) & (~BITS_VPD_DATA_8822B)) +#define BIT_GET_VPD_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_VPD_DATA_8822B) & BIT_MASK_VPD_DATA_8822B) +#define BIT_SET_VPD_DATA_8822B(x, v) \ + (BIT_CLEAR_VPD_DATA_8822B(x) | BIT_VPD_DATA_8822B(v)) /* 2 REG_SYS_SWR_CTRL1_8822B */ #define BIT_C2_L_BIT0_8822B BIT(31) @@ -124,23 +153,37 @@ #define BIT_SHIFT_C1_L_8822B 29 #define BIT_MASK_C1_L_8822B 0x3 #define BIT_C1_L_8822B(x) (((x) & BIT_MASK_C1_L_8822B) << BIT_SHIFT_C1_L_8822B) -#define BIT_GET_C1_L_8822B(x) (((x) >> BIT_SHIFT_C1_L_8822B) & BIT_MASK_C1_L_8822B) - - +#define BITS_C1_L_8822B (BIT_MASK_C1_L_8822B << BIT_SHIFT_C1_L_8822B) +#define BIT_CLEAR_C1_L_8822B(x) ((x) & (~BITS_C1_L_8822B)) +#define BIT_GET_C1_L_8822B(x) \ + (((x) >> BIT_SHIFT_C1_L_8822B) & BIT_MASK_C1_L_8822B) +#define BIT_SET_C1_L_8822B(x, v) (BIT_CLEAR_C1_L_8822B(x) | BIT_C1_L_8822B(v)) #define BIT_SHIFT_REG_FREQ_L_8822B 25 #define BIT_MASK_REG_FREQ_L_8822B 0x7 -#define BIT_REG_FREQ_L_8822B(x) (((x) & BIT_MASK_REG_FREQ_L_8822B) << BIT_SHIFT_REG_FREQ_L_8822B) -#define BIT_GET_REG_FREQ_L_8822B(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8822B) & BIT_MASK_REG_FREQ_L_8822B) - +#define BIT_REG_FREQ_L_8822B(x) \ + (((x) & BIT_MASK_REG_FREQ_L_8822B) << BIT_SHIFT_REG_FREQ_L_8822B) +#define BITS_REG_FREQ_L_8822B \ + (BIT_MASK_REG_FREQ_L_8822B << BIT_SHIFT_REG_FREQ_L_8822B) +#define BIT_CLEAR_REG_FREQ_L_8822B(x) ((x) & (~BITS_REG_FREQ_L_8822B)) +#define BIT_GET_REG_FREQ_L_8822B(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_8822B) & BIT_MASK_REG_FREQ_L_8822B) +#define BIT_SET_REG_FREQ_L_8822B(x, v) \ + (BIT_CLEAR_REG_FREQ_L_8822B(x) | BIT_REG_FREQ_L_8822B(v)) #define BIT_REG_EN_DUTY_8822B BIT(24) #define BIT_SHIFT_REG_MODE_8822B 22 #define BIT_MASK_REG_MODE_8822B 0x3 -#define BIT_REG_MODE_8822B(x) (((x) & BIT_MASK_REG_MODE_8822B) << BIT_SHIFT_REG_MODE_8822B) -#define BIT_GET_REG_MODE_8822B(x) (((x) >> BIT_SHIFT_REG_MODE_8822B) & BIT_MASK_REG_MODE_8822B) - +#define BIT_REG_MODE_8822B(x) \ + (((x) & BIT_MASK_REG_MODE_8822B) << BIT_SHIFT_REG_MODE_8822B) +#define BITS_REG_MODE_8822B \ + (BIT_MASK_REG_MODE_8822B << BIT_SHIFT_REG_MODE_8822B) +#define BIT_CLEAR_REG_MODE_8822B(x) ((x) & (~BITS_REG_MODE_8822B)) +#define BIT_GET_REG_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_REG_MODE_8822B) & BIT_MASK_REG_MODE_8822B) +#define BIT_SET_REG_MODE_8822B(x, v) \ + (BIT_CLEAR_REG_MODE_8822B(x) | BIT_REG_MODE_8822B(v)) #define BIT_REG_EN_SP_8822B BIT(21) #define BIT_REG_AUTO_L_8822B BIT(20) @@ -149,16 +192,23 @@ #define BIT_SHIFT_OCP_L1_8822B 15 #define BIT_MASK_OCP_L1_8822B 0x7 -#define BIT_OCP_L1_8822B(x) (((x) & BIT_MASK_OCP_L1_8822B) << BIT_SHIFT_OCP_L1_8822B) -#define BIT_GET_OCP_L1_8822B(x) (((x) >> BIT_SHIFT_OCP_L1_8822B) & BIT_MASK_OCP_L1_8822B) - - +#define BIT_OCP_L1_8822B(x) \ + (((x) & BIT_MASK_OCP_L1_8822B) << BIT_SHIFT_OCP_L1_8822B) +#define BITS_OCP_L1_8822B (BIT_MASK_OCP_L1_8822B << BIT_SHIFT_OCP_L1_8822B) +#define BIT_CLEAR_OCP_L1_8822B(x) ((x) & (~BITS_OCP_L1_8822B)) +#define BIT_GET_OCP_L1_8822B(x) \ + (((x) >> BIT_SHIFT_OCP_L1_8822B) & BIT_MASK_OCP_L1_8822B) +#define BIT_SET_OCP_L1_8822B(x, v) \ + (BIT_CLEAR_OCP_L1_8822B(x) | BIT_OCP_L1_8822B(v)) #define BIT_SHIFT_CF_L_8822B 13 #define BIT_MASK_CF_L_8822B 0x3 #define BIT_CF_L_8822B(x) (((x) & BIT_MASK_CF_L_8822B) << BIT_SHIFT_CF_L_8822B) -#define BIT_GET_CF_L_8822B(x) (((x) >> BIT_SHIFT_CF_L_8822B) & BIT_MASK_CF_L_8822B) - +#define BITS_CF_L_8822B (BIT_MASK_CF_L_8822B << BIT_SHIFT_CF_L_8822B) +#define BIT_CLEAR_CF_L_8822B(x) ((x) & (~BITS_CF_L_8822B)) +#define BIT_GET_CF_L_8822B(x) \ + (((x) >> BIT_SHIFT_CF_L_8822B) & BIT_MASK_CF_L_8822B) +#define BIT_SET_CF_L_8822B(x, v) (BIT_CLEAR_CF_L_8822B(x) | BIT_CF_L_8822B(v)) #define BIT_SW18_FPWM_8822B BIT(11) #define BIT_SW18_SWEN_8822B BIT(9) @@ -172,37 +222,62 @@ #define BIT_SHIFT_REG_DELAY_8822B 28 #define BIT_MASK_REG_DELAY_8822B 0x3 -#define BIT_REG_DELAY_8822B(x) (((x) & BIT_MASK_REG_DELAY_8822B) << BIT_SHIFT_REG_DELAY_8822B) -#define BIT_GET_REG_DELAY_8822B(x) (((x) >> BIT_SHIFT_REG_DELAY_8822B) & BIT_MASK_REG_DELAY_8822B) - - +#define BIT_REG_DELAY_8822B(x) \ + (((x) & BIT_MASK_REG_DELAY_8822B) << BIT_SHIFT_REG_DELAY_8822B) +#define BITS_REG_DELAY_8822B \ + (BIT_MASK_REG_DELAY_8822B << BIT_SHIFT_REG_DELAY_8822B) +#define BIT_CLEAR_REG_DELAY_8822B(x) ((x) & (~BITS_REG_DELAY_8822B)) +#define BIT_GET_REG_DELAY_8822B(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_8822B) & BIT_MASK_REG_DELAY_8822B) +#define BIT_SET_REG_DELAY_8822B(x, v) \ + (BIT_CLEAR_REG_DELAY_8822B(x) | BIT_REG_DELAY_8822B(v)) #define BIT_SHIFT_V15ADJ_L1_V1_8822B 24 #define BIT_MASK_V15ADJ_L1_V1_8822B 0x7 -#define BIT_V15ADJ_L1_V1_8822B(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8822B) << BIT_SHIFT_V15ADJ_L1_V1_8822B) -#define BIT_GET_V15ADJ_L1_V1_8822B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8822B) & BIT_MASK_V15ADJ_L1_V1_8822B) - - +#define BIT_V15ADJ_L1_V1_8822B(x) \ + (((x) & BIT_MASK_V15ADJ_L1_V1_8822B) << BIT_SHIFT_V15ADJ_L1_V1_8822B) +#define BITS_V15ADJ_L1_V1_8822B \ + (BIT_MASK_V15ADJ_L1_V1_8822B << BIT_SHIFT_V15ADJ_L1_V1_8822B) +#define BIT_CLEAR_V15ADJ_L1_V1_8822B(x) ((x) & (~BITS_V15ADJ_L1_V1_8822B)) +#define BIT_GET_V15ADJ_L1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8822B) & BIT_MASK_V15ADJ_L1_V1_8822B) +#define BIT_SET_V15ADJ_L1_V1_8822B(x, v) \ + (BIT_CLEAR_V15ADJ_L1_V1_8822B(x) | BIT_V15ADJ_L1_V1_8822B(v)) #define BIT_SHIFT_VOL_L1_V1_8822B 20 #define BIT_MASK_VOL_L1_V1_8822B 0xf -#define BIT_VOL_L1_V1_8822B(x) (((x) & BIT_MASK_VOL_L1_V1_8822B) << BIT_SHIFT_VOL_L1_V1_8822B) -#define BIT_GET_VOL_L1_V1_8822B(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8822B) & BIT_MASK_VOL_L1_V1_8822B) - - +#define BIT_VOL_L1_V1_8822B(x) \ + (((x) & BIT_MASK_VOL_L1_V1_8822B) << BIT_SHIFT_VOL_L1_V1_8822B) +#define BITS_VOL_L1_V1_8822B \ + (BIT_MASK_VOL_L1_V1_8822B << BIT_SHIFT_VOL_L1_V1_8822B) +#define BIT_CLEAR_VOL_L1_V1_8822B(x) ((x) & (~BITS_VOL_L1_V1_8822B)) +#define BIT_GET_VOL_L1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_VOL_L1_V1_8822B) & BIT_MASK_VOL_L1_V1_8822B) +#define BIT_SET_VOL_L1_V1_8822B(x, v) \ + (BIT_CLEAR_VOL_L1_V1_8822B(x) | BIT_VOL_L1_V1_8822B(v)) #define BIT_SHIFT_IN_L1_V1_8822B 17 #define BIT_MASK_IN_L1_V1_8822B 0x7 -#define BIT_IN_L1_V1_8822B(x) (((x) & BIT_MASK_IN_L1_V1_8822B) << BIT_SHIFT_IN_L1_V1_8822B) -#define BIT_GET_IN_L1_V1_8822B(x) (((x) >> BIT_SHIFT_IN_L1_V1_8822B) & BIT_MASK_IN_L1_V1_8822B) - - +#define BIT_IN_L1_V1_8822B(x) \ + (((x) & BIT_MASK_IN_L1_V1_8822B) << BIT_SHIFT_IN_L1_V1_8822B) +#define BITS_IN_L1_V1_8822B \ + (BIT_MASK_IN_L1_V1_8822B << BIT_SHIFT_IN_L1_V1_8822B) +#define BIT_CLEAR_IN_L1_V1_8822B(x) ((x) & (~BITS_IN_L1_V1_8822B)) +#define BIT_GET_IN_L1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_IN_L1_V1_8822B) & BIT_MASK_IN_L1_V1_8822B) +#define BIT_SET_IN_L1_V1_8822B(x, v) \ + (BIT_CLEAR_IN_L1_V1_8822B(x) | BIT_IN_L1_V1_8822B(v)) #define BIT_SHIFT_TBOX_L1_8822B 15 #define BIT_MASK_TBOX_L1_8822B 0x3 -#define BIT_TBOX_L1_8822B(x) (((x) & BIT_MASK_TBOX_L1_8822B) << BIT_SHIFT_TBOX_L1_8822B) -#define BIT_GET_TBOX_L1_8822B(x) (((x) >> BIT_SHIFT_TBOX_L1_8822B) & BIT_MASK_TBOX_L1_8822B) - +#define BIT_TBOX_L1_8822B(x) \ + (((x) & BIT_MASK_TBOX_L1_8822B) << BIT_SHIFT_TBOX_L1_8822B) +#define BITS_TBOX_L1_8822B (BIT_MASK_TBOX_L1_8822B << BIT_SHIFT_TBOX_L1_8822B) +#define BIT_CLEAR_TBOX_L1_8822B(x) ((x) & (~BITS_TBOX_L1_8822B)) +#define BIT_GET_TBOX_L1_8822B(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_8822B) & BIT_MASK_TBOX_L1_8822B) +#define BIT_SET_TBOX_L1_8822B(x, v) \ + (BIT_CLEAR_TBOX_L1_8822B(x) | BIT_TBOX_L1_8822B(v)) #define BIT_SW18_SEL_8822B BIT(13) @@ -212,29 +287,44 @@ #define BIT_SHIFT_R3_L_8822B 7 #define BIT_MASK_R3_L_8822B 0x3 #define BIT_R3_L_8822B(x) (((x) & BIT_MASK_R3_L_8822B) << BIT_SHIFT_R3_L_8822B) -#define BIT_GET_R3_L_8822B(x) (((x) >> BIT_SHIFT_R3_L_8822B) & BIT_MASK_R3_L_8822B) - - +#define BITS_R3_L_8822B (BIT_MASK_R3_L_8822B << BIT_SHIFT_R3_L_8822B) +#define BIT_CLEAR_R3_L_8822B(x) ((x) & (~BITS_R3_L_8822B)) +#define BIT_GET_R3_L_8822B(x) \ + (((x) >> BIT_SHIFT_R3_L_8822B) & BIT_MASK_R3_L_8822B) +#define BIT_SET_R3_L_8822B(x, v) (BIT_CLEAR_R3_L_8822B(x) | BIT_R3_L_8822B(v)) #define BIT_SHIFT_SW18_R2_8822B 5 #define BIT_MASK_SW18_R2_8822B 0x3 -#define BIT_SW18_R2_8822B(x) (((x) & BIT_MASK_SW18_R2_8822B) << BIT_SHIFT_SW18_R2_8822B) -#define BIT_GET_SW18_R2_8822B(x) (((x) >> BIT_SHIFT_SW18_R2_8822B) & BIT_MASK_SW18_R2_8822B) - - +#define BIT_SW18_R2_8822B(x) \ + (((x) & BIT_MASK_SW18_R2_8822B) << BIT_SHIFT_SW18_R2_8822B) +#define BITS_SW18_R2_8822B (BIT_MASK_SW18_R2_8822B << BIT_SHIFT_SW18_R2_8822B) +#define BIT_CLEAR_SW18_R2_8822B(x) ((x) & (~BITS_SW18_R2_8822B)) +#define BIT_GET_SW18_R2_8822B(x) \ + (((x) >> BIT_SHIFT_SW18_R2_8822B) & BIT_MASK_SW18_R2_8822B) +#define BIT_SET_SW18_R2_8822B(x, v) \ + (BIT_CLEAR_SW18_R2_8822B(x) | BIT_SW18_R2_8822B(v)) #define BIT_SHIFT_SW18_R1_8822B 3 #define BIT_MASK_SW18_R1_8822B 0x3 -#define BIT_SW18_R1_8822B(x) (((x) & BIT_MASK_SW18_R1_8822B) << BIT_SHIFT_SW18_R1_8822B) -#define BIT_GET_SW18_R1_8822B(x) (((x) >> BIT_SHIFT_SW18_R1_8822B) & BIT_MASK_SW18_R1_8822B) - - +#define BIT_SW18_R1_8822B(x) \ + (((x) & BIT_MASK_SW18_R1_8822B) << BIT_SHIFT_SW18_R1_8822B) +#define BITS_SW18_R1_8822B (BIT_MASK_SW18_R1_8822B << BIT_SHIFT_SW18_R1_8822B) +#define BIT_CLEAR_SW18_R1_8822B(x) ((x) & (~BITS_SW18_R1_8822B)) +#define BIT_GET_SW18_R1_8822B(x) \ + (((x) >> BIT_SHIFT_SW18_R1_8822B) & BIT_MASK_SW18_R1_8822B) +#define BIT_SET_SW18_R1_8822B(x, v) \ + (BIT_CLEAR_SW18_R1_8822B(x) | BIT_SW18_R1_8822B(v)) #define BIT_SHIFT_C3_L_C3_8822B 1 #define BIT_MASK_C3_L_C3_8822B 0x3 -#define BIT_C3_L_C3_8822B(x) (((x) & BIT_MASK_C3_L_C3_8822B) << BIT_SHIFT_C3_L_C3_8822B) -#define BIT_GET_C3_L_C3_8822B(x) (((x) >> BIT_SHIFT_C3_L_C3_8822B) & BIT_MASK_C3_L_C3_8822B) - +#define BIT_C3_L_C3_8822B(x) \ + (((x) & BIT_MASK_C3_L_C3_8822B) << BIT_SHIFT_C3_L_C3_8822B) +#define BITS_C3_L_C3_8822B (BIT_MASK_C3_L_C3_8822B << BIT_SHIFT_C3_L_C3_8822B) +#define BIT_CLEAR_C3_L_C3_8822B(x) ((x) & (~BITS_C3_L_C3_8822B)) +#define BIT_GET_C3_L_C3_8822B(x) \ + (((x) >> BIT_SHIFT_C3_L_C3_8822B) & BIT_MASK_C3_L_C3_8822B) +#define BIT_SET_C3_L_C3_8822B(x, v) \ + (BIT_CLEAR_C3_L_C3_8822B(x) | BIT_C3_L_C3_8822B(v)) #define BIT_C2_L_BIT1_8822B BIT(0) @@ -243,17 +333,27 @@ #define BIT_SHIFT_SPS18_OCP_TH_8822B 16 #define BIT_MASK_SPS18_OCP_TH_8822B 0x7fff -#define BIT_SPS18_OCP_TH_8822B(x) (((x) & BIT_MASK_SPS18_OCP_TH_8822B) << BIT_SHIFT_SPS18_OCP_TH_8822B) -#define BIT_GET_SPS18_OCP_TH_8822B(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8822B) & BIT_MASK_SPS18_OCP_TH_8822B) - - +#define BIT_SPS18_OCP_TH_8822B(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH_8822B) << BIT_SHIFT_SPS18_OCP_TH_8822B) +#define BITS_SPS18_OCP_TH_8822B \ + (BIT_MASK_SPS18_OCP_TH_8822B << BIT_SHIFT_SPS18_OCP_TH_8822B) +#define BIT_CLEAR_SPS18_OCP_TH_8822B(x) ((x) & (~BITS_SPS18_OCP_TH_8822B)) +#define BIT_GET_SPS18_OCP_TH_8822B(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH_8822B) & BIT_MASK_SPS18_OCP_TH_8822B) +#define BIT_SET_SPS18_OCP_TH_8822B(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH_8822B(x) | BIT_SPS18_OCP_TH_8822B(v)) #define BIT_SHIFT_OCP_WINDOW_8822B 0 #define BIT_MASK_OCP_WINDOW_8822B 0xffff -#define BIT_OCP_WINDOW_8822B(x) (((x) & BIT_MASK_OCP_WINDOW_8822B) << BIT_SHIFT_OCP_WINDOW_8822B) -#define BIT_GET_OCP_WINDOW_8822B(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8822B) & BIT_MASK_OCP_WINDOW_8822B) - - +#define BIT_OCP_WINDOW_8822B(x) \ + (((x) & BIT_MASK_OCP_WINDOW_8822B) << BIT_SHIFT_OCP_WINDOW_8822B) +#define BITS_OCP_WINDOW_8822B \ + (BIT_MASK_OCP_WINDOW_8822B << BIT_SHIFT_OCP_WINDOW_8822B) +#define BIT_CLEAR_OCP_WINDOW_8822B(x) ((x) & (~BITS_OCP_WINDOW_8822B)) +#define BIT_GET_OCP_WINDOW_8822B(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW_8822B) & BIT_MASK_OCP_WINDOW_8822B) +#define BIT_SET_OCP_WINDOW_8822B(x, v) \ + (BIT_CLEAR_OCP_WINDOW_8822B(x) | BIT_OCP_WINDOW_8822B(v)) /* 2 REG_RSV_CTRL_8822B */ #define BIT_HREG_DBG_8822B BIT(23) @@ -276,17 +376,29 @@ #define BIT_SHIFT_LPLDH12_RSV_8822B 29 #define BIT_MASK_LPLDH12_RSV_8822B 0x7 -#define BIT_LPLDH12_RSV_8822B(x) (((x) & BIT_MASK_LPLDH12_RSV_8822B) << BIT_SHIFT_LPLDH12_RSV_8822B) -#define BIT_GET_LPLDH12_RSV_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8822B) & BIT_MASK_LPLDH12_RSV_8822B) - +#define BIT_LPLDH12_RSV_8822B(x) \ + (((x) & BIT_MASK_LPLDH12_RSV_8822B) << BIT_SHIFT_LPLDH12_RSV_8822B) +#define BITS_LPLDH12_RSV_8822B \ + (BIT_MASK_LPLDH12_RSV_8822B << BIT_SHIFT_LPLDH12_RSV_8822B) +#define BIT_CLEAR_LPLDH12_RSV_8822B(x) ((x) & (~BITS_LPLDH12_RSV_8822B)) +#define BIT_GET_LPLDH12_RSV_8822B(x) \ + (((x) >> BIT_SHIFT_LPLDH12_RSV_8822B) & BIT_MASK_LPLDH12_RSV_8822B) +#define BIT_SET_LPLDH12_RSV_8822B(x, v) \ + (BIT_CLEAR_LPLDH12_RSV_8822B(x) | BIT_LPLDH12_RSV_8822B(v)) #define BIT_LPLDH12_SLP_8822B BIT(28) #define BIT_SHIFT_LPLDH12_VADJ_8822B 24 #define BIT_MASK_LPLDH12_VADJ_8822B 0xf -#define BIT_LPLDH12_VADJ_8822B(x) (((x) & BIT_MASK_LPLDH12_VADJ_8822B) << BIT_SHIFT_LPLDH12_VADJ_8822B) -#define BIT_GET_LPLDH12_VADJ_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8822B) & BIT_MASK_LPLDH12_VADJ_8822B) - +#define BIT_LPLDH12_VADJ_8822B(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_8822B) << BIT_SHIFT_LPLDH12_VADJ_8822B) +#define BITS_LPLDH12_VADJ_8822B \ + (BIT_MASK_LPLDH12_VADJ_8822B << BIT_SHIFT_LPLDH12_VADJ_8822B) +#define BIT_CLEAR_LPLDH12_VADJ_8822B(x) ((x) & (~BITS_LPLDH12_VADJ_8822B)) +#define BIT_GET_LPLDH12_VADJ_8822B(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_8822B) & BIT_MASK_LPLDH12_VADJ_8822B) +#define BIT_SET_LPLDH12_VADJ_8822B(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_8822B(x) | BIT_LPLDH12_VADJ_8822B(v)) #define BIT_LDH12_EN_8822B BIT(16) #define BIT_WLBBOFF_BIG_PWC_EN_8822B BIT(14) @@ -310,46 +422,79 @@ #define BIT_SHIFT_XTAL_CAP_XI_8822B 25 #define BIT_MASK_XTAL_CAP_XI_8822B 0x3f -#define BIT_XTAL_CAP_XI_8822B(x) (((x) & BIT_MASK_XTAL_CAP_XI_8822B) << BIT_SHIFT_XTAL_CAP_XI_8822B) -#define BIT_GET_XTAL_CAP_XI_8822B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8822B) & BIT_MASK_XTAL_CAP_XI_8822B) - - +#define BIT_XTAL_CAP_XI_8822B(x) \ + (((x) & BIT_MASK_XTAL_CAP_XI_8822B) << BIT_SHIFT_XTAL_CAP_XI_8822B) +#define BITS_XTAL_CAP_XI_8822B \ + (BIT_MASK_XTAL_CAP_XI_8822B << BIT_SHIFT_XTAL_CAP_XI_8822B) +#define BIT_CLEAR_XTAL_CAP_XI_8822B(x) ((x) & (~BITS_XTAL_CAP_XI_8822B)) +#define BIT_GET_XTAL_CAP_XI_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XI_8822B) & BIT_MASK_XTAL_CAP_XI_8822B) +#define BIT_SET_XTAL_CAP_XI_8822B(x, v) \ + (BIT_CLEAR_XTAL_CAP_XI_8822B(x) | BIT_XTAL_CAP_XI_8822B(v)) #define BIT_SHIFT_XTAL_DRV_DIGI_8822B 23 #define BIT_MASK_XTAL_DRV_DIGI_8822B 0x3 -#define BIT_XTAL_DRV_DIGI_8822B(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8822B) << BIT_SHIFT_XTAL_DRV_DIGI_8822B) -#define BIT_GET_XTAL_DRV_DIGI_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8822B) & BIT_MASK_XTAL_DRV_DIGI_8822B) - +#define BIT_XTAL_DRV_DIGI_8822B(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_8822B) << BIT_SHIFT_XTAL_DRV_DIGI_8822B) +#define BITS_XTAL_DRV_DIGI_8822B \ + (BIT_MASK_XTAL_DRV_DIGI_8822B << BIT_SHIFT_XTAL_DRV_DIGI_8822B) +#define BIT_CLEAR_XTAL_DRV_DIGI_8822B(x) ((x) & (~BITS_XTAL_DRV_DIGI_8822B)) +#define BIT_GET_XTAL_DRV_DIGI_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8822B) & BIT_MASK_XTAL_DRV_DIGI_8822B) +#define BIT_SET_XTAL_DRV_DIGI_8822B(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_8822B(x) | BIT_XTAL_DRV_DIGI_8822B(v)) #define BIT_XTAL_DRV_USB_BIT1_8822B BIT(22) #define BIT_SHIFT_MAC_CLK_SEL_8822B 20 #define BIT_MASK_MAC_CLK_SEL_8822B 0x3 -#define BIT_MAC_CLK_SEL_8822B(x) (((x) & BIT_MASK_MAC_CLK_SEL_8822B) << BIT_SHIFT_MAC_CLK_SEL_8822B) -#define BIT_GET_MAC_CLK_SEL_8822B(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8822B) & BIT_MASK_MAC_CLK_SEL_8822B) - +#define BIT_MAC_CLK_SEL_8822B(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_8822B) << BIT_SHIFT_MAC_CLK_SEL_8822B) +#define BITS_MAC_CLK_SEL_8822B \ + (BIT_MASK_MAC_CLK_SEL_8822B << BIT_SHIFT_MAC_CLK_SEL_8822B) +#define BIT_CLEAR_MAC_CLK_SEL_8822B(x) ((x) & (~BITS_MAC_CLK_SEL_8822B)) +#define BIT_GET_MAC_CLK_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_8822B) & BIT_MASK_MAC_CLK_SEL_8822B) +#define BIT_SET_MAC_CLK_SEL_8822B(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_8822B(x) | BIT_MAC_CLK_SEL_8822B(v)) #define BIT_XTAL_DRV_USB_BIT0_8822B BIT(19) #define BIT_SHIFT_XTAL_DRV_AFE_8822B 17 #define BIT_MASK_XTAL_DRV_AFE_8822B 0x3 -#define BIT_XTAL_DRV_AFE_8822B(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8822B) << BIT_SHIFT_XTAL_DRV_AFE_8822B) -#define BIT_GET_XTAL_DRV_AFE_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8822B) & BIT_MASK_XTAL_DRV_AFE_8822B) - - +#define BIT_XTAL_DRV_AFE_8822B(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_8822B) << BIT_SHIFT_XTAL_DRV_AFE_8822B) +#define BITS_XTAL_DRV_AFE_8822B \ + (BIT_MASK_XTAL_DRV_AFE_8822B << BIT_SHIFT_XTAL_DRV_AFE_8822B) +#define BIT_CLEAR_XTAL_DRV_AFE_8822B(x) ((x) & (~BITS_XTAL_DRV_AFE_8822B)) +#define BIT_GET_XTAL_DRV_AFE_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8822B) & BIT_MASK_XTAL_DRV_AFE_8822B) +#define BIT_SET_XTAL_DRV_AFE_8822B(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_8822B(x) | BIT_XTAL_DRV_AFE_8822B(v)) #define BIT_SHIFT_XTAL_DRV_RF2_8822B 15 #define BIT_MASK_XTAL_DRV_RF2_8822B 0x3 -#define BIT_XTAL_DRV_RF2_8822B(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8822B) << BIT_SHIFT_XTAL_DRV_RF2_8822B) -#define BIT_GET_XTAL_DRV_RF2_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8822B) & BIT_MASK_XTAL_DRV_RF2_8822B) - - +#define BIT_XTAL_DRV_RF2_8822B(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_8822B) << BIT_SHIFT_XTAL_DRV_RF2_8822B) +#define BITS_XTAL_DRV_RF2_8822B \ + (BIT_MASK_XTAL_DRV_RF2_8822B << BIT_SHIFT_XTAL_DRV_RF2_8822B) +#define BIT_CLEAR_XTAL_DRV_RF2_8822B(x) ((x) & (~BITS_XTAL_DRV_RF2_8822B)) +#define BIT_GET_XTAL_DRV_RF2_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8822B) & BIT_MASK_XTAL_DRV_RF2_8822B) +#define BIT_SET_XTAL_DRV_RF2_8822B(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_8822B(x) | BIT_XTAL_DRV_RF2_8822B(v)) #define BIT_SHIFT_XTAL_DRV_RF1_8822B 13 #define BIT_MASK_XTAL_DRV_RF1_8822B 0x3 -#define BIT_XTAL_DRV_RF1_8822B(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8822B) << BIT_SHIFT_XTAL_DRV_RF1_8822B) -#define BIT_GET_XTAL_DRV_RF1_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822B) & BIT_MASK_XTAL_DRV_RF1_8822B) - +#define BIT_XTAL_DRV_RF1_8822B(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF1_8822B) << BIT_SHIFT_XTAL_DRV_RF1_8822B) +#define BITS_XTAL_DRV_RF1_8822B \ + (BIT_MASK_XTAL_DRV_RF1_8822B << BIT_SHIFT_XTAL_DRV_RF1_8822B) +#define BIT_CLEAR_XTAL_DRV_RF1_8822B(x) ((x) & (~BITS_XTAL_DRV_RF1_8822B)) +#define BIT_GET_XTAL_DRV_RF1_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822B) & BIT_MASK_XTAL_DRV_RF1_8822B) +#define BIT_SET_XTAL_DRV_RF1_8822B(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF1_8822B(x) | BIT_XTAL_DRV_RF1_8822B(v)) #define BIT_XTAL_DELAY_DIGI_8822B BIT(12) #define BIT_XTAL_DELAY_USB_8822B BIT(11) @@ -357,25 +502,42 @@ #define BIT_SHIFT_XTAL_LDO_VREF_8822B 7 #define BIT_MASK_XTAL_LDO_VREF_8822B 0x7 -#define BIT_XTAL_LDO_VREF_8822B(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8822B) << BIT_SHIFT_XTAL_LDO_VREF_8822B) -#define BIT_GET_XTAL_LDO_VREF_8822B(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8822B) & BIT_MASK_XTAL_LDO_VREF_8822B) - +#define BIT_XTAL_LDO_VREF_8822B(x) \ + (((x) & BIT_MASK_XTAL_LDO_VREF_8822B) << BIT_SHIFT_XTAL_LDO_VREF_8822B) +#define BITS_XTAL_LDO_VREF_8822B \ + (BIT_MASK_XTAL_LDO_VREF_8822B << BIT_SHIFT_XTAL_LDO_VREF_8822B) +#define BIT_CLEAR_XTAL_LDO_VREF_8822B(x) ((x) & (~BITS_XTAL_LDO_VREF_8822B)) +#define BIT_GET_XTAL_LDO_VREF_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8822B) & BIT_MASK_XTAL_LDO_VREF_8822B) +#define BIT_SET_XTAL_LDO_VREF_8822B(x, v) \ + (BIT_CLEAR_XTAL_LDO_VREF_8822B(x) | BIT_XTAL_LDO_VREF_8822B(v)) #define BIT_XTAL_XQSEL_RF_8822B BIT(6) #define BIT_XTAL_XQSEL_8822B BIT(5) #define BIT_SHIFT_XTAL_GMN_V2_8822B 3 #define BIT_MASK_XTAL_GMN_V2_8822B 0x3 -#define BIT_XTAL_GMN_V2_8822B(x) (((x) & BIT_MASK_XTAL_GMN_V2_8822B) << BIT_SHIFT_XTAL_GMN_V2_8822B) -#define BIT_GET_XTAL_GMN_V2_8822B(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8822B) & BIT_MASK_XTAL_GMN_V2_8822B) - - +#define BIT_XTAL_GMN_V2_8822B(x) \ + (((x) & BIT_MASK_XTAL_GMN_V2_8822B) << BIT_SHIFT_XTAL_GMN_V2_8822B) +#define BITS_XTAL_GMN_V2_8822B \ + (BIT_MASK_XTAL_GMN_V2_8822B << BIT_SHIFT_XTAL_GMN_V2_8822B) +#define BIT_CLEAR_XTAL_GMN_V2_8822B(x) ((x) & (~BITS_XTAL_GMN_V2_8822B)) +#define BIT_GET_XTAL_GMN_V2_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V2_8822B) & BIT_MASK_XTAL_GMN_V2_8822B) +#define BIT_SET_XTAL_GMN_V2_8822B(x, v) \ + (BIT_CLEAR_XTAL_GMN_V2_8822B(x) | BIT_XTAL_GMN_V2_8822B(v)) #define BIT_SHIFT_XTAL_GMP_V2_8822B 1 #define BIT_MASK_XTAL_GMP_V2_8822B 0x3 -#define BIT_XTAL_GMP_V2_8822B(x) (((x) & BIT_MASK_XTAL_GMP_V2_8822B) << BIT_SHIFT_XTAL_GMP_V2_8822B) -#define BIT_GET_XTAL_GMP_V2_8822B(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8822B) & BIT_MASK_XTAL_GMP_V2_8822B) - +#define BIT_XTAL_GMP_V2_8822B(x) \ + (((x) & BIT_MASK_XTAL_GMP_V2_8822B) << BIT_SHIFT_XTAL_GMP_V2_8822B) +#define BITS_XTAL_GMP_V2_8822B \ + (BIT_MASK_XTAL_GMP_V2_8822B << BIT_SHIFT_XTAL_GMP_V2_8822B) +#define BIT_CLEAR_XTAL_GMP_V2_8822B(x) ((x) & (~BITS_XTAL_GMP_V2_8822B)) +#define BIT_GET_XTAL_GMP_V2_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V2_8822B) & BIT_MASK_XTAL_GMP_V2_8822B) +#define BIT_SET_XTAL_GMP_V2_8822B(x, v) \ + (BIT_CLEAR_XTAL_GMP_V2_8822B(x) | BIT_XTAL_GMP_V2_8822B(v)) #define BIT_XTAL_EN_8822B BIT(0) @@ -383,38 +545,63 @@ #define BIT_SHIFT_REG_C3_V4_8822B 30 #define BIT_MASK_REG_C3_V4_8822B 0x3 -#define BIT_REG_C3_V4_8822B(x) (((x) & BIT_MASK_REG_C3_V4_8822B) << BIT_SHIFT_REG_C3_V4_8822B) -#define BIT_GET_REG_C3_V4_8822B(x) (((x) >> BIT_SHIFT_REG_C3_V4_8822B) & BIT_MASK_REG_C3_V4_8822B) - +#define BIT_REG_C3_V4_8822B(x) \ + (((x) & BIT_MASK_REG_C3_V4_8822B) << BIT_SHIFT_REG_C3_V4_8822B) +#define BITS_REG_C3_V4_8822B \ + (BIT_MASK_REG_C3_V4_8822B << BIT_SHIFT_REG_C3_V4_8822B) +#define BIT_CLEAR_REG_C3_V4_8822B(x) ((x) & (~BITS_REG_C3_V4_8822B)) +#define BIT_GET_REG_C3_V4_8822B(x) \ + (((x) >> BIT_SHIFT_REG_C3_V4_8822B) & BIT_MASK_REG_C3_V4_8822B) +#define BIT_SET_REG_C3_V4_8822B(x, v) \ + (BIT_CLEAR_REG_C3_V4_8822B(x) | BIT_REG_C3_V4_8822B(v)) #define BIT_REG_CP_BIT1_8822B BIT(29) #define BIT_SHIFT_REG_RS_V4_8822B 26 #define BIT_MASK_REG_RS_V4_8822B 0x7 -#define BIT_REG_RS_V4_8822B(x) (((x) & BIT_MASK_REG_RS_V4_8822B) << BIT_SHIFT_REG_RS_V4_8822B) -#define BIT_GET_REG_RS_V4_8822B(x) (((x) >> BIT_SHIFT_REG_RS_V4_8822B) & BIT_MASK_REG_RS_V4_8822B) - - +#define BIT_REG_RS_V4_8822B(x) \ + (((x) & BIT_MASK_REG_RS_V4_8822B) << BIT_SHIFT_REG_RS_V4_8822B) +#define BITS_REG_RS_V4_8822B \ + (BIT_MASK_REG_RS_V4_8822B << BIT_SHIFT_REG_RS_V4_8822B) +#define BIT_CLEAR_REG_RS_V4_8822B(x) ((x) & (~BITS_REG_RS_V4_8822B)) +#define BIT_GET_REG_RS_V4_8822B(x) \ + (((x) >> BIT_SHIFT_REG_RS_V4_8822B) & BIT_MASK_REG_RS_V4_8822B) +#define BIT_SET_REG_RS_V4_8822B(x, v) \ + (BIT_CLEAR_REG_RS_V4_8822B(x) | BIT_REG_RS_V4_8822B(v)) #define BIT_SHIFT_REG__CS_8822B 24 #define BIT_MASK_REG__CS_8822B 0x3 -#define BIT_REG__CS_8822B(x) (((x) & BIT_MASK_REG__CS_8822B) << BIT_SHIFT_REG__CS_8822B) -#define BIT_GET_REG__CS_8822B(x) (((x) >> BIT_SHIFT_REG__CS_8822B) & BIT_MASK_REG__CS_8822B) - - +#define BIT_REG__CS_8822B(x) \ + (((x) & BIT_MASK_REG__CS_8822B) << BIT_SHIFT_REG__CS_8822B) +#define BITS_REG__CS_8822B (BIT_MASK_REG__CS_8822B << BIT_SHIFT_REG__CS_8822B) +#define BIT_CLEAR_REG__CS_8822B(x) ((x) & (~BITS_REG__CS_8822B)) +#define BIT_GET_REG__CS_8822B(x) \ + (((x) >> BIT_SHIFT_REG__CS_8822B) & BIT_MASK_REG__CS_8822B) +#define BIT_SET_REG__CS_8822B(x, v) \ + (BIT_CLEAR_REG__CS_8822B(x) | BIT_REG__CS_8822B(v)) #define BIT_SHIFT_REG_CP_OFFSET_8822B 21 #define BIT_MASK_REG_CP_OFFSET_8822B 0x7 -#define BIT_REG_CP_OFFSET_8822B(x) (((x) & BIT_MASK_REG_CP_OFFSET_8822B) << BIT_SHIFT_REG_CP_OFFSET_8822B) -#define BIT_GET_REG_CP_OFFSET_8822B(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8822B) & BIT_MASK_REG_CP_OFFSET_8822B) - - +#define BIT_REG_CP_OFFSET_8822B(x) \ + (((x) & BIT_MASK_REG_CP_OFFSET_8822B) << BIT_SHIFT_REG_CP_OFFSET_8822B) +#define BITS_REG_CP_OFFSET_8822B \ + (BIT_MASK_REG_CP_OFFSET_8822B << BIT_SHIFT_REG_CP_OFFSET_8822B) +#define BIT_CLEAR_REG_CP_OFFSET_8822B(x) ((x) & (~BITS_REG_CP_OFFSET_8822B)) +#define BIT_GET_REG_CP_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_REG_CP_OFFSET_8822B) & BIT_MASK_REG_CP_OFFSET_8822B) +#define BIT_SET_REG_CP_OFFSET_8822B(x, v) \ + (BIT_CLEAR_REG_CP_OFFSET_8822B(x) | BIT_REG_CP_OFFSET_8822B(v)) #define BIT_SHIFT_CP_BIAS_8822B 18 #define BIT_MASK_CP_BIAS_8822B 0x7 -#define BIT_CP_BIAS_8822B(x) (((x) & BIT_MASK_CP_BIAS_8822B) << BIT_SHIFT_CP_BIAS_8822B) -#define BIT_GET_CP_BIAS_8822B(x) (((x) >> BIT_SHIFT_CP_BIAS_8822B) & BIT_MASK_CP_BIAS_8822B) - +#define BIT_CP_BIAS_8822B(x) \ + (((x) & BIT_MASK_CP_BIAS_8822B) << BIT_SHIFT_CP_BIAS_8822B) +#define BITS_CP_BIAS_8822B (BIT_MASK_CP_BIAS_8822B << BIT_SHIFT_CP_BIAS_8822B) +#define BIT_CLEAR_CP_BIAS_8822B(x) ((x) & (~BITS_CP_BIAS_8822B)) +#define BIT_GET_CP_BIAS_8822B(x) \ + (((x) >> BIT_SHIFT_CP_BIAS_8822B) & BIT_MASK_CP_BIAS_8822B) +#define BIT_SET_CP_BIAS_8822B(x, v) \ + (BIT_CLEAR_CP_BIAS_8822B(x) | BIT_CP_BIAS_8822B(v)) #define BIT_REG_IDOUBLE_V2_8822B BIT(17) #define BIT_EN_SYN_8822B BIT(16) @@ -422,31 +609,50 @@ #define BIT_SHIFT_MCCO_8822B 14 #define BIT_MASK_MCCO_8822B 0x3 #define BIT_MCCO_8822B(x) (((x) & BIT_MASK_MCCO_8822B) << BIT_SHIFT_MCCO_8822B) -#define BIT_GET_MCCO_8822B(x) (((x) >> BIT_SHIFT_MCCO_8822B) & BIT_MASK_MCCO_8822B) - - +#define BITS_MCCO_8822B (BIT_MASK_MCCO_8822B << BIT_SHIFT_MCCO_8822B) +#define BIT_CLEAR_MCCO_8822B(x) ((x) & (~BITS_MCCO_8822B)) +#define BIT_GET_MCCO_8822B(x) \ + (((x) >> BIT_SHIFT_MCCO_8822B) & BIT_MASK_MCCO_8822B) +#define BIT_SET_MCCO_8822B(x, v) (BIT_CLEAR_MCCO_8822B(x) | BIT_MCCO_8822B(v)) #define BIT_SHIFT_REG_LDO_SEL_8822B 12 #define BIT_MASK_REG_LDO_SEL_8822B 0x3 -#define BIT_REG_LDO_SEL_8822B(x) (((x) & BIT_MASK_REG_LDO_SEL_8822B) << BIT_SHIFT_REG_LDO_SEL_8822B) -#define BIT_GET_REG_LDO_SEL_8822B(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8822B) & BIT_MASK_REG_LDO_SEL_8822B) - +#define BIT_REG_LDO_SEL_8822B(x) \ + (((x) & BIT_MASK_REG_LDO_SEL_8822B) << BIT_SHIFT_REG_LDO_SEL_8822B) +#define BITS_REG_LDO_SEL_8822B \ + (BIT_MASK_REG_LDO_SEL_8822B << BIT_SHIFT_REG_LDO_SEL_8822B) +#define BIT_CLEAR_REG_LDO_SEL_8822B(x) ((x) & (~BITS_REG_LDO_SEL_8822B)) +#define BIT_GET_REG_LDO_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_REG_LDO_SEL_8822B) & BIT_MASK_REG_LDO_SEL_8822B) +#define BIT_SET_REG_LDO_SEL_8822B(x, v) \ + (BIT_CLEAR_REG_LDO_SEL_8822B(x) | BIT_REG_LDO_SEL_8822B(v)) #define BIT_REG_KVCO_V2_8822B BIT(10) #define BIT_AGPIO_GPO_8822B BIT(9) #define BIT_SHIFT_AGPIO_DRV_8822B 7 #define BIT_MASK_AGPIO_DRV_8822B 0x3 -#define BIT_AGPIO_DRV_8822B(x) (((x) & BIT_MASK_AGPIO_DRV_8822B) << BIT_SHIFT_AGPIO_DRV_8822B) -#define BIT_GET_AGPIO_DRV_8822B(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8822B) & BIT_MASK_AGPIO_DRV_8822B) - - +#define BIT_AGPIO_DRV_8822B(x) \ + (((x) & BIT_MASK_AGPIO_DRV_8822B) << BIT_SHIFT_AGPIO_DRV_8822B) +#define BITS_AGPIO_DRV_8822B \ + (BIT_MASK_AGPIO_DRV_8822B << BIT_SHIFT_AGPIO_DRV_8822B) +#define BIT_CLEAR_AGPIO_DRV_8822B(x) ((x) & (~BITS_AGPIO_DRV_8822B)) +#define BIT_GET_AGPIO_DRV_8822B(x) \ + (((x) >> BIT_SHIFT_AGPIO_DRV_8822B) & BIT_MASK_AGPIO_DRV_8822B) +#define BIT_SET_AGPIO_DRV_8822B(x, v) \ + (BIT_CLEAR_AGPIO_DRV_8822B(x) | BIT_AGPIO_DRV_8822B(v)) #define BIT_SHIFT_XTAL_CAP_XO_8822B 1 #define BIT_MASK_XTAL_CAP_XO_8822B 0x3f -#define BIT_XTAL_CAP_XO_8822B(x) (((x) & BIT_MASK_XTAL_CAP_XO_8822B) << BIT_SHIFT_XTAL_CAP_XO_8822B) -#define BIT_GET_XTAL_CAP_XO_8822B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8822B) & BIT_MASK_XTAL_CAP_XO_8822B) - +#define BIT_XTAL_CAP_XO_8822B(x) \ + (((x) & BIT_MASK_XTAL_CAP_XO_8822B) << BIT_SHIFT_XTAL_CAP_XO_8822B) +#define BITS_XTAL_CAP_XO_8822B \ + (BIT_MASK_XTAL_CAP_XO_8822B << BIT_SHIFT_XTAL_CAP_XO_8822B) +#define BIT_CLEAR_XTAL_CAP_XO_8822B(x) ((x) & (~BITS_XTAL_CAP_XO_8822B)) +#define BIT_GET_XTAL_CAP_XO_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_CAP_XO_8822B) & BIT_MASK_XTAL_CAP_XO_8822B) +#define BIT_SET_XTAL_CAP_XO_8822B(x, v) \ + (BIT_CLEAR_XTAL_CAP_XO_8822B(x) | BIT_XTAL_CAP_XO_8822B(v)) #define BIT_POW_PLL_8822B BIT(0) @@ -455,8 +661,10 @@ #define BIT_SHIFT_PS_8822B 7 #define BIT_MASK_PS_8822B 0x7 #define BIT_PS_8822B(x) (((x) & BIT_MASK_PS_8822B) << BIT_SHIFT_PS_8822B) +#define BITS_PS_8822B (BIT_MASK_PS_8822B << BIT_SHIFT_PS_8822B) +#define BIT_CLEAR_PS_8822B(x) ((x) & (~BITS_PS_8822B)) #define BIT_GET_PS_8822B(x) (((x) >> BIT_SHIFT_PS_8822B) & BIT_MASK_PS_8822B) - +#define BIT_SET_PS_8822B(x, v) (BIT_CLEAR_PS_8822B(x) | BIT_PS_8822B(v)) #define BIT_PSEN_8822B BIT(6) #define BIT_DOGENB_8822B BIT(5) @@ -464,9 +672,15 @@ #define BIT_SHIFT_REG_R3_V4_8822B 1 #define BIT_MASK_REG_R3_V4_8822B 0x7 -#define BIT_REG_R3_V4_8822B(x) (((x) & BIT_MASK_REG_R3_V4_8822B) << BIT_SHIFT_REG_R3_V4_8822B) -#define BIT_GET_REG_R3_V4_8822B(x) (((x) >> BIT_SHIFT_REG_R3_V4_8822B) & BIT_MASK_REG_R3_V4_8822B) - +#define BIT_REG_R3_V4_8822B(x) \ + (((x) & BIT_MASK_REG_R3_V4_8822B) << BIT_SHIFT_REG_R3_V4_8822B) +#define BITS_REG_R3_V4_8822B \ + (BIT_MASK_REG_R3_V4_8822B << BIT_SHIFT_REG_R3_V4_8822B) +#define BIT_CLEAR_REG_R3_V4_8822B(x) ((x) & (~BITS_REG_R3_V4_8822B)) +#define BIT_GET_REG_R3_V4_8822B(x) \ + (((x) >> BIT_SHIFT_REG_R3_V4_8822B) & BIT_MASK_REG_R3_V4_8822B) +#define BIT_SET_REG_R3_V4_8822B(x, v) \ + (BIT_CLEAR_REG_R3_V4_8822B(x) | BIT_REG_R3_V4_8822B(v)) #define BIT_REG_CP_BIT0_8822B BIT(0) @@ -475,103 +689,172 @@ #define BIT_SHIFT_EF_PGPD_8822B 28 #define BIT_MASK_EF_PGPD_8822B 0x7 -#define BIT_EF_PGPD_8822B(x) (((x) & BIT_MASK_EF_PGPD_8822B) << BIT_SHIFT_EF_PGPD_8822B) -#define BIT_GET_EF_PGPD_8822B(x) (((x) >> BIT_SHIFT_EF_PGPD_8822B) & BIT_MASK_EF_PGPD_8822B) - - +#define BIT_EF_PGPD_8822B(x) \ + (((x) & BIT_MASK_EF_PGPD_8822B) << BIT_SHIFT_EF_PGPD_8822B) +#define BITS_EF_PGPD_8822B (BIT_MASK_EF_PGPD_8822B << BIT_SHIFT_EF_PGPD_8822B) +#define BIT_CLEAR_EF_PGPD_8822B(x) ((x) & (~BITS_EF_PGPD_8822B)) +#define BIT_GET_EF_PGPD_8822B(x) \ + (((x) >> BIT_SHIFT_EF_PGPD_8822B) & BIT_MASK_EF_PGPD_8822B) +#define BIT_SET_EF_PGPD_8822B(x, v) \ + (BIT_CLEAR_EF_PGPD_8822B(x) | BIT_EF_PGPD_8822B(v)) #define BIT_SHIFT_EF_RDT_8822B 24 #define BIT_MASK_EF_RDT_8822B 0xf -#define BIT_EF_RDT_8822B(x) (((x) & BIT_MASK_EF_RDT_8822B) << BIT_SHIFT_EF_RDT_8822B) -#define BIT_GET_EF_RDT_8822B(x) (((x) >> BIT_SHIFT_EF_RDT_8822B) & BIT_MASK_EF_RDT_8822B) - - +#define BIT_EF_RDT_8822B(x) \ + (((x) & BIT_MASK_EF_RDT_8822B) << BIT_SHIFT_EF_RDT_8822B) +#define BITS_EF_RDT_8822B (BIT_MASK_EF_RDT_8822B << BIT_SHIFT_EF_RDT_8822B) +#define BIT_CLEAR_EF_RDT_8822B(x) ((x) & (~BITS_EF_RDT_8822B)) +#define BIT_GET_EF_RDT_8822B(x) \ + (((x) >> BIT_SHIFT_EF_RDT_8822B) & BIT_MASK_EF_RDT_8822B) +#define BIT_SET_EF_RDT_8822B(x, v) \ + (BIT_CLEAR_EF_RDT_8822B(x) | BIT_EF_RDT_8822B(v)) #define BIT_SHIFT_EF_PGTS_8822B 20 #define BIT_MASK_EF_PGTS_8822B 0xf -#define BIT_EF_PGTS_8822B(x) (((x) & BIT_MASK_EF_PGTS_8822B) << BIT_SHIFT_EF_PGTS_8822B) -#define BIT_GET_EF_PGTS_8822B(x) (((x) >> BIT_SHIFT_EF_PGTS_8822B) & BIT_MASK_EF_PGTS_8822B) - +#define BIT_EF_PGTS_8822B(x) \ + (((x) & BIT_MASK_EF_PGTS_8822B) << BIT_SHIFT_EF_PGTS_8822B) +#define BITS_EF_PGTS_8822B (BIT_MASK_EF_PGTS_8822B << BIT_SHIFT_EF_PGTS_8822B) +#define BIT_CLEAR_EF_PGTS_8822B(x) ((x) & (~BITS_EF_PGTS_8822B)) +#define BIT_GET_EF_PGTS_8822B(x) \ + (((x) >> BIT_SHIFT_EF_PGTS_8822B) & BIT_MASK_EF_PGTS_8822B) +#define BIT_SET_EF_PGTS_8822B(x, v) \ + (BIT_CLEAR_EF_PGTS_8822B(x) | BIT_EF_PGTS_8822B(v)) #define BIT_EF_PDWN_8822B BIT(19) #define BIT_EF_ALDEN_8822B BIT(18) #define BIT_SHIFT_EF_ADDR_8822B 8 #define BIT_MASK_EF_ADDR_8822B 0x3ff -#define BIT_EF_ADDR_8822B(x) (((x) & BIT_MASK_EF_ADDR_8822B) << BIT_SHIFT_EF_ADDR_8822B) -#define BIT_GET_EF_ADDR_8822B(x) (((x) >> BIT_SHIFT_EF_ADDR_8822B) & BIT_MASK_EF_ADDR_8822B) - - +#define BIT_EF_ADDR_8822B(x) \ + (((x) & BIT_MASK_EF_ADDR_8822B) << BIT_SHIFT_EF_ADDR_8822B) +#define BITS_EF_ADDR_8822B (BIT_MASK_EF_ADDR_8822B << BIT_SHIFT_EF_ADDR_8822B) +#define BIT_CLEAR_EF_ADDR_8822B(x) ((x) & (~BITS_EF_ADDR_8822B)) +#define BIT_GET_EF_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_EF_ADDR_8822B) & BIT_MASK_EF_ADDR_8822B) +#define BIT_SET_EF_ADDR_8822B(x, v) \ + (BIT_CLEAR_EF_ADDR_8822B(x) | BIT_EF_ADDR_8822B(v)) #define BIT_SHIFT_EF_DATA_8822B 0 #define BIT_MASK_EF_DATA_8822B 0xff -#define BIT_EF_DATA_8822B(x) (((x) & BIT_MASK_EF_DATA_8822B) << BIT_SHIFT_EF_DATA_8822B) -#define BIT_GET_EF_DATA_8822B(x) (((x) >> BIT_SHIFT_EF_DATA_8822B) & BIT_MASK_EF_DATA_8822B) - - +#define BIT_EF_DATA_8822B(x) \ + (((x) & BIT_MASK_EF_DATA_8822B) << BIT_SHIFT_EF_DATA_8822B) +#define BITS_EF_DATA_8822B (BIT_MASK_EF_DATA_8822B << BIT_SHIFT_EF_DATA_8822B) +#define BIT_CLEAR_EF_DATA_8822B(x) ((x) & (~BITS_EF_DATA_8822B)) +#define BIT_GET_EF_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_EF_DATA_8822B) & BIT_MASK_EF_DATA_8822B) +#define BIT_SET_EF_DATA_8822B(x, v) \ + (BIT_CLEAR_EF_DATA_8822B(x) | BIT_EF_DATA_8822B(v)) /* 2 REG_LDO_EFUSE_CTRL_8822B */ #define BIT_LDOE25_EN_8822B BIT(31) #define BIT_SHIFT_LDOE25_V12ADJ_L_8822B 27 #define BIT_MASK_LDOE25_V12ADJ_L_8822B 0xf -#define BIT_LDOE25_V12ADJ_L_8822B(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8822B) << BIT_SHIFT_LDOE25_V12ADJ_L_8822B) -#define BIT_GET_LDOE25_V12ADJ_L_8822B(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8822B) & BIT_MASK_LDOE25_V12ADJ_L_8822B) - +#define BIT_LDOE25_V12ADJ_L_8822B(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L_8822B) \ + << BIT_SHIFT_LDOE25_V12ADJ_L_8822B) +#define BITS_LDOE25_V12ADJ_L_8822B \ + (BIT_MASK_LDOE25_V12ADJ_L_8822B << BIT_SHIFT_LDOE25_V12ADJ_L_8822B) +#define BIT_CLEAR_LDOE25_V12ADJ_L_8822B(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8822B)) +#define BIT_GET_LDOE25_V12ADJ_L_8822B(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8822B) & \ + BIT_MASK_LDOE25_V12ADJ_L_8822B) +#define BIT_SET_LDOE25_V12ADJ_L_8822B(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L_8822B(x) | BIT_LDOE25_V12ADJ_L_8822B(v)) #define BIT_EF_CRES_SEL_8822B BIT(26) #define BIT_SHIFT_EF_SCAN_START_V1_8822B 16 #define BIT_MASK_EF_SCAN_START_V1_8822B 0x3ff -#define BIT_EF_SCAN_START_V1_8822B(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8822B) << BIT_SHIFT_EF_SCAN_START_V1_8822B) -#define BIT_GET_EF_SCAN_START_V1_8822B(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822B) & BIT_MASK_EF_SCAN_START_V1_8822B) - - +#define BIT_EF_SCAN_START_V1_8822B(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1_8822B) \ + << BIT_SHIFT_EF_SCAN_START_V1_8822B) +#define BITS_EF_SCAN_START_V1_8822B \ + (BIT_MASK_EF_SCAN_START_V1_8822B << BIT_SHIFT_EF_SCAN_START_V1_8822B) +#define BIT_CLEAR_EF_SCAN_START_V1_8822B(x) \ + ((x) & (~BITS_EF_SCAN_START_V1_8822B)) +#define BIT_GET_EF_SCAN_START_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822B) & \ + BIT_MASK_EF_SCAN_START_V1_8822B) +#define BIT_SET_EF_SCAN_START_V1_8822B(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1_8822B(x) | BIT_EF_SCAN_START_V1_8822B(v)) #define BIT_SHIFT_EF_SCAN_END_8822B 12 #define BIT_MASK_EF_SCAN_END_8822B 0xf -#define BIT_EF_SCAN_END_8822B(x) (((x) & BIT_MASK_EF_SCAN_END_8822B) << BIT_SHIFT_EF_SCAN_END_8822B) -#define BIT_GET_EF_SCAN_END_8822B(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8822B) & BIT_MASK_EF_SCAN_END_8822B) - +#define BIT_EF_SCAN_END_8822B(x) \ + (((x) & BIT_MASK_EF_SCAN_END_8822B) << BIT_SHIFT_EF_SCAN_END_8822B) +#define BITS_EF_SCAN_END_8822B \ + (BIT_MASK_EF_SCAN_END_8822B << BIT_SHIFT_EF_SCAN_END_8822B) +#define BIT_CLEAR_EF_SCAN_END_8822B(x) ((x) & (~BITS_EF_SCAN_END_8822B)) +#define BIT_GET_EF_SCAN_END_8822B(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END_8822B) & BIT_MASK_EF_SCAN_END_8822B) +#define BIT_SET_EF_SCAN_END_8822B(x, v) \ + (BIT_CLEAR_EF_SCAN_END_8822B(x) | BIT_EF_SCAN_END_8822B(v)) #define BIT_EF_PD_DIS_8822B BIT(11) #define BIT_SHIFT_EF_CELL_SEL_8822B 8 #define BIT_MASK_EF_CELL_SEL_8822B 0x3 -#define BIT_EF_CELL_SEL_8822B(x) (((x) & BIT_MASK_EF_CELL_SEL_8822B) << BIT_SHIFT_EF_CELL_SEL_8822B) -#define BIT_GET_EF_CELL_SEL_8822B(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8822B) & BIT_MASK_EF_CELL_SEL_8822B) - +#define BIT_EF_CELL_SEL_8822B(x) \ + (((x) & BIT_MASK_EF_CELL_SEL_8822B) << BIT_SHIFT_EF_CELL_SEL_8822B) +#define BITS_EF_CELL_SEL_8822B \ + (BIT_MASK_EF_CELL_SEL_8822B << BIT_SHIFT_EF_CELL_SEL_8822B) +#define BIT_CLEAR_EF_CELL_SEL_8822B(x) ((x) & (~BITS_EF_CELL_SEL_8822B)) +#define BIT_GET_EF_CELL_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL_8822B) & BIT_MASK_EF_CELL_SEL_8822B) +#define BIT_SET_EF_CELL_SEL_8822B(x, v) \ + (BIT_CLEAR_EF_CELL_SEL_8822B(x) | BIT_EF_CELL_SEL_8822B(v)) #define BIT_EF_TRPT_8822B BIT(7) #define BIT_SHIFT_EF_TTHD_8822B 0 #define BIT_MASK_EF_TTHD_8822B 0x7f -#define BIT_EF_TTHD_8822B(x) (((x) & BIT_MASK_EF_TTHD_8822B) << BIT_SHIFT_EF_TTHD_8822B) -#define BIT_GET_EF_TTHD_8822B(x) (((x) >> BIT_SHIFT_EF_TTHD_8822B) & BIT_MASK_EF_TTHD_8822B) - - +#define BIT_EF_TTHD_8822B(x) \ + (((x) & BIT_MASK_EF_TTHD_8822B) << BIT_SHIFT_EF_TTHD_8822B) +#define BITS_EF_TTHD_8822B (BIT_MASK_EF_TTHD_8822B << BIT_SHIFT_EF_TTHD_8822B) +#define BIT_CLEAR_EF_TTHD_8822B(x) ((x) & (~BITS_EF_TTHD_8822B)) +#define BIT_GET_EF_TTHD_8822B(x) \ + (((x) >> BIT_SHIFT_EF_TTHD_8822B) & BIT_MASK_EF_TTHD_8822B) +#define BIT_SET_EF_TTHD_8822B(x, v) \ + (BIT_CLEAR_EF_TTHD_8822B(x) | BIT_EF_TTHD_8822B(v)) /* 2 REG_PWR_OPTION_CTRL_8822B */ #define BIT_SHIFT_DBG_SEL_V1_8822B 16 #define BIT_MASK_DBG_SEL_V1_8822B 0xff -#define BIT_DBG_SEL_V1_8822B(x) (((x) & BIT_MASK_DBG_SEL_V1_8822B) << BIT_SHIFT_DBG_SEL_V1_8822B) -#define BIT_GET_DBG_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8822B) & BIT_MASK_DBG_SEL_V1_8822B) - - +#define BIT_DBG_SEL_V1_8822B(x) \ + (((x) & BIT_MASK_DBG_SEL_V1_8822B) << BIT_SHIFT_DBG_SEL_V1_8822B) +#define BITS_DBG_SEL_V1_8822B \ + (BIT_MASK_DBG_SEL_V1_8822B << BIT_SHIFT_DBG_SEL_V1_8822B) +#define BIT_CLEAR_DBG_SEL_V1_8822B(x) ((x) & (~BITS_DBG_SEL_V1_8822B)) +#define BIT_GET_DBG_SEL_V1_8822B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1_8822B) & BIT_MASK_DBG_SEL_V1_8822B) +#define BIT_SET_DBG_SEL_V1_8822B(x, v) \ + (BIT_CLEAR_DBG_SEL_V1_8822B(x) | BIT_DBG_SEL_V1_8822B(v)) #define BIT_SHIFT_DBG_SEL_BYTE_8822B 14 #define BIT_MASK_DBG_SEL_BYTE_8822B 0x3 -#define BIT_DBG_SEL_BYTE_8822B(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8822B) << BIT_SHIFT_DBG_SEL_BYTE_8822B) -#define BIT_GET_DBG_SEL_BYTE_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822B) & BIT_MASK_DBG_SEL_BYTE_8822B) - - +#define BIT_DBG_SEL_BYTE_8822B(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE_8822B) << BIT_SHIFT_DBG_SEL_BYTE_8822B) +#define BITS_DBG_SEL_BYTE_8822B \ + (BIT_MASK_DBG_SEL_BYTE_8822B << BIT_SHIFT_DBG_SEL_BYTE_8822B) +#define BIT_CLEAR_DBG_SEL_BYTE_8822B(x) ((x) & (~BITS_DBG_SEL_BYTE_8822B)) +#define BIT_GET_DBG_SEL_BYTE_8822B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822B) & BIT_MASK_DBG_SEL_BYTE_8822B) +#define BIT_SET_DBG_SEL_BYTE_8822B(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE_8822B(x) | BIT_DBG_SEL_BYTE_8822B(v)) #define BIT_SHIFT_STD_L1_V1_8822B 12 #define BIT_MASK_STD_L1_V1_8822B 0x3 -#define BIT_STD_L1_V1_8822B(x) (((x) & BIT_MASK_STD_L1_V1_8822B) << BIT_SHIFT_STD_L1_V1_8822B) -#define BIT_GET_STD_L1_V1_8822B(x) (((x) >> BIT_SHIFT_STD_L1_V1_8822B) & BIT_MASK_STD_L1_V1_8822B) - +#define BIT_STD_L1_V1_8822B(x) \ + (((x) & BIT_MASK_STD_L1_V1_8822B) << BIT_SHIFT_STD_L1_V1_8822B) +#define BITS_STD_L1_V1_8822B \ + (BIT_MASK_STD_L1_V1_8822B << BIT_SHIFT_STD_L1_V1_8822B) +#define BIT_CLEAR_STD_L1_V1_8822B(x) ((x) & (~BITS_STD_L1_V1_8822B)) +#define BIT_GET_STD_L1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_STD_L1_V1_8822B) & BIT_MASK_STD_L1_V1_8822B) +#define BIT_SET_STD_L1_V1_8822B(x, v) \ + (BIT_CLEAR_STD_L1_V1_8822B(x) | BIT_STD_L1_V1_8822B(v)) #define BIT_SYSON_DBG_PAD_E2_8822B BIT(11) #define BIT_SYSON_LED_PAD_E2_8822B BIT(10) @@ -581,56 +864,101 @@ #define BIT_SHIFT_SYSON_SPS0WWV_WT_8822B 4 #define BIT_MASK_SYSON_SPS0WWV_WT_8822B 0x3 -#define BIT_SYSON_SPS0WWV_WT_8822B(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822B) << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) -#define BIT_GET_SYSON_SPS0WWV_WT_8822B(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) & BIT_MASK_SYSON_SPS0WWV_WT_8822B) - - +#define BIT_SYSON_SPS0WWV_WT_8822B(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822B) \ + << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) +#define BITS_SYSON_SPS0WWV_WT_8822B \ + (BIT_MASK_SYSON_SPS0WWV_WT_8822B << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) +#define BIT_CLEAR_SYSON_SPS0WWV_WT_8822B(x) \ + ((x) & (~BITS_SYSON_SPS0WWV_WT_8822B)) +#define BIT_GET_SYSON_SPS0WWV_WT_8822B(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) & \ + BIT_MASK_SYSON_SPS0WWV_WT_8822B) +#define BIT_SET_SYSON_SPS0WWV_WT_8822B(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT_8822B(x) | BIT_SYSON_SPS0WWV_WT_8822B(v)) #define BIT_SHIFT_SYSON_SPS0LDO_WT_8822B 2 #define BIT_MASK_SYSON_SPS0LDO_WT_8822B 0x3 -#define BIT_SYSON_SPS0LDO_WT_8822B(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822B) << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) -#define BIT_GET_SYSON_SPS0LDO_WT_8822B(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) & BIT_MASK_SYSON_SPS0LDO_WT_8822B) - - +#define BIT_SYSON_SPS0LDO_WT_8822B(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822B) \ + << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) +#define BITS_SYSON_SPS0LDO_WT_8822B \ + (BIT_MASK_SYSON_SPS0LDO_WT_8822B << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) +#define BIT_CLEAR_SYSON_SPS0LDO_WT_8822B(x) \ + ((x) & (~BITS_SYSON_SPS0LDO_WT_8822B)) +#define BIT_GET_SYSON_SPS0LDO_WT_8822B(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) & \ + BIT_MASK_SYSON_SPS0LDO_WT_8822B) +#define BIT_SET_SYSON_SPS0LDO_WT_8822B(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT_8822B(x) | BIT_SYSON_SPS0LDO_WT_8822B(v)) #define BIT_SHIFT_SYSON_RCLK_SCALE_8822B 0 #define BIT_MASK_SYSON_RCLK_SCALE_8822B 0x3 -#define BIT_SYSON_RCLK_SCALE_8822B(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8822B) << BIT_SHIFT_SYSON_RCLK_SCALE_8822B) -#define BIT_GET_SYSON_RCLK_SCALE_8822B(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822B) & BIT_MASK_SYSON_RCLK_SCALE_8822B) - - +#define BIT_SYSON_RCLK_SCALE_8822B(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE_8822B) \ + << BIT_SHIFT_SYSON_RCLK_SCALE_8822B) +#define BITS_SYSON_RCLK_SCALE_8822B \ + (BIT_MASK_SYSON_RCLK_SCALE_8822B << BIT_SHIFT_SYSON_RCLK_SCALE_8822B) +#define BIT_CLEAR_SYSON_RCLK_SCALE_8822B(x) \ + ((x) & (~BITS_SYSON_RCLK_SCALE_8822B)) +#define BIT_GET_SYSON_RCLK_SCALE_8822B(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822B) & \ + BIT_MASK_SYSON_RCLK_SCALE_8822B) +#define BIT_SET_SYSON_RCLK_SCALE_8822B(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE_8822B(x) | BIT_SYSON_RCLK_SCALE_8822B(v)) /* 2 REG_CAL_TIMER_8822B */ #define BIT_SHIFT_MATCH_CNT_8822B 8 #define BIT_MASK_MATCH_CNT_8822B 0xff -#define BIT_MATCH_CNT_8822B(x) (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B) -#define BIT_GET_MATCH_CNT_8822B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B) - - +#define BIT_MATCH_CNT_8822B(x) \ + (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B) +#define BITS_MATCH_CNT_8822B \ + (BIT_MASK_MATCH_CNT_8822B << BIT_SHIFT_MATCH_CNT_8822B) +#define BIT_CLEAR_MATCH_CNT_8822B(x) ((x) & (~BITS_MATCH_CNT_8822B)) +#define BIT_GET_MATCH_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B) +#define BIT_SET_MATCH_CNT_8822B(x, v) \ + (BIT_CLEAR_MATCH_CNT_8822B(x) | BIT_MATCH_CNT_8822B(v)) #define BIT_SHIFT_CAL_SCAL_8822B 0 #define BIT_MASK_CAL_SCAL_8822B 0xff -#define BIT_CAL_SCAL_8822B(x) (((x) & BIT_MASK_CAL_SCAL_8822B) << BIT_SHIFT_CAL_SCAL_8822B) -#define BIT_GET_CAL_SCAL_8822B(x) (((x) >> BIT_SHIFT_CAL_SCAL_8822B) & BIT_MASK_CAL_SCAL_8822B) - - +#define BIT_CAL_SCAL_8822B(x) \ + (((x) & BIT_MASK_CAL_SCAL_8822B) << BIT_SHIFT_CAL_SCAL_8822B) +#define BITS_CAL_SCAL_8822B \ + (BIT_MASK_CAL_SCAL_8822B << BIT_SHIFT_CAL_SCAL_8822B) +#define BIT_CLEAR_CAL_SCAL_8822B(x) ((x) & (~BITS_CAL_SCAL_8822B)) +#define BIT_GET_CAL_SCAL_8822B(x) \ + (((x) >> BIT_SHIFT_CAL_SCAL_8822B) & BIT_MASK_CAL_SCAL_8822B) +#define BIT_SET_CAL_SCAL_8822B(x, v) \ + (BIT_CLEAR_CAL_SCAL_8822B(x) | BIT_CAL_SCAL_8822B(v)) /* 2 REG_ACLK_MON_8822B */ #define BIT_SHIFT_RCLK_MON_8822B 5 #define BIT_MASK_RCLK_MON_8822B 0x7ff -#define BIT_RCLK_MON_8822B(x) (((x) & BIT_MASK_RCLK_MON_8822B) << BIT_SHIFT_RCLK_MON_8822B) -#define BIT_GET_RCLK_MON_8822B(x) (((x) >> BIT_SHIFT_RCLK_MON_8822B) & BIT_MASK_RCLK_MON_8822B) - +#define BIT_RCLK_MON_8822B(x) \ + (((x) & BIT_MASK_RCLK_MON_8822B) << BIT_SHIFT_RCLK_MON_8822B) +#define BITS_RCLK_MON_8822B \ + (BIT_MASK_RCLK_MON_8822B << BIT_SHIFT_RCLK_MON_8822B) +#define BIT_CLEAR_RCLK_MON_8822B(x) ((x) & (~BITS_RCLK_MON_8822B)) +#define BIT_GET_RCLK_MON_8822B(x) \ + (((x) >> BIT_SHIFT_RCLK_MON_8822B) & BIT_MASK_RCLK_MON_8822B) +#define BIT_SET_RCLK_MON_8822B(x, v) \ + (BIT_CLEAR_RCLK_MON_8822B(x) | BIT_RCLK_MON_8822B(v)) #define BIT_CAL_EN_8822B BIT(4) #define BIT_SHIFT_DPSTU_8822B 2 #define BIT_MASK_DPSTU_8822B 0x3 -#define BIT_DPSTU_8822B(x) (((x) & BIT_MASK_DPSTU_8822B) << BIT_SHIFT_DPSTU_8822B) -#define BIT_GET_DPSTU_8822B(x) (((x) >> BIT_SHIFT_DPSTU_8822B) & BIT_MASK_DPSTU_8822B) - +#define BIT_DPSTU_8822B(x) \ + (((x) & BIT_MASK_DPSTU_8822B) << BIT_SHIFT_DPSTU_8822B) +#define BITS_DPSTU_8822B (BIT_MASK_DPSTU_8822B << BIT_SHIFT_DPSTU_8822B) +#define BIT_CLEAR_DPSTU_8822B(x) ((x) & (~BITS_DPSTU_8822B)) +#define BIT_GET_DPSTU_8822B(x) \ + (((x) >> BIT_SHIFT_DPSTU_8822B) & BIT_MASK_DPSTU_8822B) +#define BIT_SET_DPSTU_8822B(x, v) \ + (BIT_CLEAR_DPSTU_8822B(x) | BIT_DPSTU_8822B(v)) #define BIT_SUS_16X_8822B BIT(1) @@ -648,9 +976,14 @@ #define BIT_SHIFT_BTMODE_8822B 6 #define BIT_MASK_BTMODE_8822B 0x3 -#define BIT_BTMODE_8822B(x) (((x) & BIT_MASK_BTMODE_8822B) << BIT_SHIFT_BTMODE_8822B) -#define BIT_GET_BTMODE_8822B(x) (((x) >> BIT_SHIFT_BTMODE_8822B) & BIT_MASK_BTMODE_8822B) - +#define BIT_BTMODE_8822B(x) \ + (((x) & BIT_MASK_BTMODE_8822B) << BIT_SHIFT_BTMODE_8822B) +#define BITS_BTMODE_8822B (BIT_MASK_BTMODE_8822B << BIT_SHIFT_BTMODE_8822B) +#define BIT_CLEAR_BTMODE_8822B(x) ((x) & (~BITS_BTMODE_8822B)) +#define BIT_GET_BTMODE_8822B(x) \ + (((x) >> BIT_SHIFT_BTMODE_8822B) & BIT_MASK_BTMODE_8822B) +#define BIT_SET_BTMODE_8822B(x, v) \ + (BIT_CLEAR_BTMODE_8822B(x) | BIT_BTMODE_8822B(v)) #define BIT_ENBT_8822B BIT(5) #define BIT_EROM_EN_8822B BIT(4) @@ -659,48 +992,89 @@ #define BIT_SHIFT_GPIOSEL_8822B 0 #define BIT_MASK_GPIOSEL_8822B 0x3 -#define BIT_GPIOSEL_8822B(x) (((x) & BIT_MASK_GPIOSEL_8822B) << BIT_SHIFT_GPIOSEL_8822B) -#define BIT_GET_GPIOSEL_8822B(x) (((x) >> BIT_SHIFT_GPIOSEL_8822B) & BIT_MASK_GPIOSEL_8822B) - - +#define BIT_GPIOSEL_8822B(x) \ + (((x) & BIT_MASK_GPIOSEL_8822B) << BIT_SHIFT_GPIOSEL_8822B) +#define BITS_GPIOSEL_8822B (BIT_MASK_GPIOSEL_8822B << BIT_SHIFT_GPIOSEL_8822B) +#define BIT_CLEAR_GPIOSEL_8822B(x) ((x) & (~BITS_GPIOSEL_8822B)) +#define BIT_GET_GPIOSEL_8822B(x) \ + (((x) >> BIT_SHIFT_GPIOSEL_8822B) & BIT_MASK_GPIOSEL_8822B) +#define BIT_SET_GPIOSEL_8822B(x, v) \ + (BIT_CLEAR_GPIOSEL_8822B(x) | BIT_GPIOSEL_8822B(v)) /* 2 REG_GPIO_PIN_CTRL_8822B */ #define BIT_SHIFT_GPIO_MOD_7_TO_0_8822B 24 #define BIT_MASK_GPIO_MOD_7_TO_0_8822B 0xff -#define BIT_GPIO_MOD_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822B) << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) -#define BIT_GET_GPIO_MOD_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) & BIT_MASK_GPIO_MOD_7_TO_0_8822B) - - +#define BIT_GPIO_MOD_7_TO_0_8822B(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822B) \ + << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) +#define BITS_GPIO_MOD_7_TO_0_8822B \ + (BIT_MASK_GPIO_MOD_7_TO_0_8822B << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) +#define BIT_CLEAR_GPIO_MOD_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8822B)) +#define BIT_GET_GPIO_MOD_7_TO_0_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) & \ + BIT_MASK_GPIO_MOD_7_TO_0_8822B) +#define BIT_SET_GPIO_MOD_7_TO_0_8822B(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0_8822B(x) | BIT_GPIO_MOD_7_TO_0_8822B(v)) #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B 16 #define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B 0xff -#define BIT_GPIO_IO_SEL_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) -#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) - - +#define BIT_GPIO_IO_SEL_7_TO_0_8822B(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) +#define BITS_GPIO_IO_SEL_7_TO_0_8822B \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822B(x) \ + ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8822B)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) & \ + BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) +#define BIT_SET_GPIO_IO_SEL_7_TO_0_8822B(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822B(x) | \ + BIT_GPIO_IO_SEL_7_TO_0_8822B(v)) #define BIT_SHIFT_GPIO_OUT_7_TO_0_8822B 8 #define BIT_MASK_GPIO_OUT_7_TO_0_8822B 0xff -#define BIT_GPIO_OUT_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822B) << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) -#define BIT_GET_GPIO_OUT_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) & BIT_MASK_GPIO_OUT_7_TO_0_8822B) - - +#define BIT_GPIO_OUT_7_TO_0_8822B(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822B) \ + << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) +#define BITS_GPIO_OUT_7_TO_0_8822B \ + (BIT_MASK_GPIO_OUT_7_TO_0_8822B << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) +#define BIT_CLEAR_GPIO_OUT_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8822B)) +#define BIT_GET_GPIO_OUT_7_TO_0_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) & \ + BIT_MASK_GPIO_OUT_7_TO_0_8822B) +#define BIT_SET_GPIO_OUT_7_TO_0_8822B(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0_8822B(x) | BIT_GPIO_OUT_7_TO_0_8822B(v)) #define BIT_SHIFT_GPIO_IN_7_TO_0_8822B 0 #define BIT_MASK_GPIO_IN_7_TO_0_8822B 0xff -#define BIT_GPIO_IN_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8822B) << BIT_SHIFT_GPIO_IN_7_TO_0_8822B) -#define BIT_GET_GPIO_IN_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822B) & BIT_MASK_GPIO_IN_7_TO_0_8822B) - - +#define BIT_GPIO_IN_7_TO_0_8822B(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0_8822B) \ + << BIT_SHIFT_GPIO_IN_7_TO_0_8822B) +#define BITS_GPIO_IN_7_TO_0_8822B \ + (BIT_MASK_GPIO_IN_7_TO_0_8822B << BIT_SHIFT_GPIO_IN_7_TO_0_8822B) +#define BIT_CLEAR_GPIO_IN_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8822B)) +#define BIT_GET_GPIO_IN_7_TO_0_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822B) & \ + BIT_MASK_GPIO_IN_7_TO_0_8822B) +#define BIT_SET_GPIO_IN_7_TO_0_8822B(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0_8822B(x) | BIT_GPIO_IN_7_TO_0_8822B(v)) /* 2 REG_GPIO_INTM_8822B */ #define BIT_SHIFT_MUXDBG_SEL_8822B 30 #define BIT_MASK_MUXDBG_SEL_8822B 0x3 -#define BIT_MUXDBG_SEL_8822B(x) (((x) & BIT_MASK_MUXDBG_SEL_8822B) << BIT_SHIFT_MUXDBG_SEL_8822B) -#define BIT_GET_MUXDBG_SEL_8822B(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8822B) & BIT_MASK_MUXDBG_SEL_8822B) - +#define BIT_MUXDBG_SEL_8822B(x) \ + (((x) & BIT_MASK_MUXDBG_SEL_8822B) << BIT_SHIFT_MUXDBG_SEL_8822B) +#define BITS_MUXDBG_SEL_8822B \ + (BIT_MASK_MUXDBG_SEL_8822B << BIT_SHIFT_MUXDBG_SEL_8822B) +#define BIT_CLEAR_MUXDBG_SEL_8822B(x) ((x) & (~BITS_MUXDBG_SEL_8822B)) +#define BIT_GET_MUXDBG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL_8822B) & BIT_MASK_MUXDBG_SEL_8822B) +#define BIT_SET_MUXDBG_SEL_8822B(x, v) \ + (BIT_CLEAR_MUXDBG_SEL_8822B(x) | BIT_MUXDBG_SEL_8822B(v)) #define BIT_EXTWOL_SEL_8822B BIT(17) #define BIT_EXTWOL_EN_8822B BIT(16) @@ -738,9 +1112,14 @@ #define BIT_SHIFT_LED2CM_8822B 16 #define BIT_MASK_LED2CM_8822B 0x7 -#define BIT_LED2CM_8822B(x) (((x) & BIT_MASK_LED2CM_8822B) << BIT_SHIFT_LED2CM_8822B) -#define BIT_GET_LED2CM_8822B(x) (((x) >> BIT_SHIFT_LED2CM_8822B) & BIT_MASK_LED2CM_8822B) - +#define BIT_LED2CM_8822B(x) \ + (((x) & BIT_MASK_LED2CM_8822B) << BIT_SHIFT_LED2CM_8822B) +#define BITS_LED2CM_8822B (BIT_MASK_LED2CM_8822B << BIT_SHIFT_LED2CM_8822B) +#define BIT_CLEAR_LED2CM_8822B(x) ((x) & (~BITS_LED2CM_8822B)) +#define BIT_GET_LED2CM_8822B(x) \ + (((x) >> BIT_SHIFT_LED2CM_8822B) & BIT_MASK_LED2CM_8822B) +#define BIT_SET_LED2CM_8822B(x, v) \ + (BIT_CLEAR_LED2CM_8822B(x) | BIT_LED2CM_8822B(v)) #define BIT_LED1DIS_8822B BIT(15) #define BIT_LED1PL_8822B BIT(12) @@ -748,27 +1127,45 @@ #define BIT_SHIFT_LED1CM_8822B 8 #define BIT_MASK_LED1CM_8822B 0x7 -#define BIT_LED1CM_8822B(x) (((x) & BIT_MASK_LED1CM_8822B) << BIT_SHIFT_LED1CM_8822B) -#define BIT_GET_LED1CM_8822B(x) (((x) >> BIT_SHIFT_LED1CM_8822B) & BIT_MASK_LED1CM_8822B) - +#define BIT_LED1CM_8822B(x) \ + (((x) & BIT_MASK_LED1CM_8822B) << BIT_SHIFT_LED1CM_8822B) +#define BITS_LED1CM_8822B (BIT_MASK_LED1CM_8822B << BIT_SHIFT_LED1CM_8822B) +#define BIT_CLEAR_LED1CM_8822B(x) ((x) & (~BITS_LED1CM_8822B)) +#define BIT_GET_LED1CM_8822B(x) \ + (((x) >> BIT_SHIFT_LED1CM_8822B) & BIT_MASK_LED1CM_8822B) +#define BIT_SET_LED1CM_8822B(x, v) \ + (BIT_CLEAR_LED1CM_8822B(x) | BIT_LED1CM_8822B(v)) #define BIT_LED0DIS_8822B BIT(7) #define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B 5 #define BIT_MASK_AFE_LDO_SWR_CHECK_8822B 0x3 -#define BIT_AFE_LDO_SWR_CHECK_8822B(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) -#define BIT_GET_AFE_LDO_SWR_CHECK_8822B(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B) - +#define BIT_AFE_LDO_SWR_CHECK_8822B(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B) \ + << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) +#define BITS_AFE_LDO_SWR_CHECK_8822B \ + (BIT_MASK_AFE_LDO_SWR_CHECK_8822B << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8822B(x) \ + ((x) & (~BITS_AFE_LDO_SWR_CHECK_8822B)) +#define BIT_GET_AFE_LDO_SWR_CHECK_8822B(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) & \ + BIT_MASK_AFE_LDO_SWR_CHECK_8822B) +#define BIT_SET_AFE_LDO_SWR_CHECK_8822B(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK_8822B(x) | BIT_AFE_LDO_SWR_CHECK_8822B(v)) #define BIT_LED0PL_8822B BIT(4) #define BIT_LED0SV_8822B BIT(3) #define BIT_SHIFT_LED0CM_8822B 0 #define BIT_MASK_LED0CM_8822B 0x7 -#define BIT_LED0CM_8822B(x) (((x) & BIT_MASK_LED0CM_8822B) << BIT_SHIFT_LED0CM_8822B) -#define BIT_GET_LED0CM_8822B(x) (((x) >> BIT_SHIFT_LED0CM_8822B) & BIT_MASK_LED0CM_8822B) - - +#define BIT_LED0CM_8822B(x) \ + (((x) & BIT_MASK_LED0CM_8822B) << BIT_SHIFT_LED0CM_8822B) +#define BITS_LED0CM_8822B (BIT_MASK_LED0CM_8822B << BIT_SHIFT_LED0CM_8822B) +#define BIT_CLEAR_LED0CM_8822B(x) ((x) & (~BITS_LED0CM_8822B)) +#define BIT_GET_LED0CM_8822B(x) \ + (((x) >> BIT_SHIFT_LED0CM_8822B) & BIT_MASK_LED0CM_8822B) +#define BIT_SET_LED0CM_8822B(x, v) \ + (BIT_CLEAR_LED0CM_8822B(x) | BIT_LED0CM_8822B(v)) /* 2 REG_FSIMR_8822B */ #define BIT_FS_PDNINT_EN_8822B BIT(31) @@ -848,7 +1245,7 @@ #define BIT_GPIO5_INT_EN_8822B BIT(21) #define BIT_GPIO4_INT_EN_8822B BIT(20) #define BIT_GPIO3_INT_EN_8822B BIT(19) -#define BIT_GPIO2_INT_EN_V1_8822B BIT(16) +#define BIT_GPIO2_INT_EN_V1_8822B BIT(18) #define BIT_GPIO1_INT_EN_8822B BIT(17) #define BIT_GPIO0_INT_EN_8822B BIT(16) #define BIT_PDNINT_EN_8822B BIT(7) @@ -870,7 +1267,7 @@ #define BIT_GPIO5_INT_8822B BIT(21) #define BIT_GPIO4_INT_8822B BIT(20) #define BIT_GPIO3_INT_8822B BIT(19) -#define BIT_GPIO2_INT_V1_8822B BIT(16) +#define BIT_GPIO2_INT_V1_8822B BIT(18) #define BIT_GPIO1_INT_8822B BIT(17) #define BIT_GPIO0_INT_8822B BIT(16) #define BIT_PDNINT_8822B BIT(7) @@ -882,31 +1279,64 @@ #define BIT_SHIFT_GPIO_MOD_15_TO_8_8822B 24 #define BIT_MASK_GPIO_MOD_15_TO_8_8822B 0xff -#define BIT_GPIO_MOD_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822B) << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) -#define BIT_GET_GPIO_MOD_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) & BIT_MASK_GPIO_MOD_15_TO_8_8822B) - - +#define BIT_GPIO_MOD_15_TO_8_8822B(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822B) \ + << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) +#define BITS_GPIO_MOD_15_TO_8_8822B \ + (BIT_MASK_GPIO_MOD_15_TO_8_8822B << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) +#define BIT_CLEAR_GPIO_MOD_15_TO_8_8822B(x) \ + ((x) & (~BITS_GPIO_MOD_15_TO_8_8822B)) +#define BIT_GET_GPIO_MOD_15_TO_8_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) & \ + BIT_MASK_GPIO_MOD_15_TO_8_8822B) +#define BIT_SET_GPIO_MOD_15_TO_8_8822B(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8_8822B(x) | BIT_GPIO_MOD_15_TO_8_8822B(v)) #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B 16 #define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B 0xff -#define BIT_GPIO_IO_SEL_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) -#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) - - +#define BIT_GPIO_IO_SEL_15_TO_8_8822B(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) +#define BITS_GPIO_IO_SEL_15_TO_8_8822B \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822B(x) \ + ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8822B)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) & \ + BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) +#define BIT_SET_GPIO_IO_SEL_15_TO_8_8822B(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822B(x) | \ + BIT_GPIO_IO_SEL_15_TO_8_8822B(v)) #define BIT_SHIFT_GPIO_OUT_15_TO_8_8822B 8 #define BIT_MASK_GPIO_OUT_15_TO_8_8822B 0xff -#define BIT_GPIO_OUT_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822B) << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) -#define BIT_GET_GPIO_OUT_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) & BIT_MASK_GPIO_OUT_15_TO_8_8822B) - - +#define BIT_GPIO_OUT_15_TO_8_8822B(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822B) \ + << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) +#define BITS_GPIO_OUT_15_TO_8_8822B \ + (BIT_MASK_GPIO_OUT_15_TO_8_8822B << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) +#define BIT_CLEAR_GPIO_OUT_15_TO_8_8822B(x) \ + ((x) & (~BITS_GPIO_OUT_15_TO_8_8822B)) +#define BIT_GET_GPIO_OUT_15_TO_8_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) & \ + BIT_MASK_GPIO_OUT_15_TO_8_8822B) +#define BIT_SET_GPIO_OUT_15_TO_8_8822B(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8_8822B(x) | BIT_GPIO_OUT_15_TO_8_8822B(v)) #define BIT_SHIFT_GPIO_IN_15_TO_8_8822B 0 #define BIT_MASK_GPIO_IN_15_TO_8_8822B 0xff -#define BIT_GPIO_IN_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8822B) << BIT_SHIFT_GPIO_IN_15_TO_8_8822B) -#define BIT_GET_GPIO_IN_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822B) & BIT_MASK_GPIO_IN_15_TO_8_8822B) - - +#define BIT_GPIO_IN_15_TO_8_8822B(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8_8822B) \ + << BIT_SHIFT_GPIO_IN_15_TO_8_8822B) +#define BITS_GPIO_IN_15_TO_8_8822B \ + (BIT_MASK_GPIO_IN_15_TO_8_8822B << BIT_SHIFT_GPIO_IN_15_TO_8_8822B) +#define BIT_CLEAR_GPIO_IN_15_TO_8_8822B(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8822B)) +#define BIT_GET_GPIO_IN_15_TO_8_8822B(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822B) & \ + BIT_MASK_GPIO_IN_15_TO_8_8822B) +#define BIT_SET_GPIO_IN_15_TO_8_8822B(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8_8822B(x) | BIT_GPIO_IN_15_TO_8_8822B(v)) /* 2 REG_PAD_CTRL1_8822B */ #define BIT_PAPE_WLBT_SEL_8822B BIT(29) @@ -923,9 +1353,15 @@ #define BIT_SHIFT_BTGP_GPIO_SL_8822B 16 #define BIT_MASK_BTGP_GPIO_SL_8822B 0x3 -#define BIT_BTGP_GPIO_SL_8822B(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8822B) << BIT_SHIFT_BTGP_GPIO_SL_8822B) -#define BIT_GET_BTGP_GPIO_SL_8822B(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822B) & BIT_MASK_BTGP_GPIO_SL_8822B) - +#define BIT_BTGP_GPIO_SL_8822B(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL_8822B) << BIT_SHIFT_BTGP_GPIO_SL_8822B) +#define BITS_BTGP_GPIO_SL_8822B \ + (BIT_MASK_BTGP_GPIO_SL_8822B << BIT_SHIFT_BTGP_GPIO_SL_8822B) +#define BIT_CLEAR_BTGP_GPIO_SL_8822B(x) ((x) & (~BITS_BTGP_GPIO_SL_8822B)) +#define BIT_GET_BTGP_GPIO_SL_8822B(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822B) & BIT_MASK_BTGP_GPIO_SL_8822B) +#define BIT_SET_BTGP_GPIO_SL_8822B(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL_8822B(x) | BIT_BTGP_GPIO_SL_8822B(v)) #define BIT_PAD_SDIO_SR_8822B BIT(14) #define BIT_GPIO14_OUTPUT_PL_8822B BIT(13) @@ -976,10 +1412,15 @@ #define BIT_SHIFT_WLCLK_PHASE_8822B 0 #define BIT_MASK_WLCLK_PHASE_8822B 0x1f -#define BIT_WLCLK_PHASE_8822B(x) (((x) & BIT_MASK_WLCLK_PHASE_8822B) << BIT_SHIFT_WLCLK_PHASE_8822B) -#define BIT_GET_WLCLK_PHASE_8822B(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8822B) & BIT_MASK_WLCLK_PHASE_8822B) - - +#define BIT_WLCLK_PHASE_8822B(x) \ + (((x) & BIT_MASK_WLCLK_PHASE_8822B) << BIT_SHIFT_WLCLK_PHASE_8822B) +#define BITS_WLCLK_PHASE_8822B \ + (BIT_MASK_WLCLK_PHASE_8822B << BIT_SHIFT_WLCLK_PHASE_8822B) +#define BIT_CLEAR_WLCLK_PHASE_8822B(x) ((x) & (~BITS_WLCLK_PHASE_8822B)) +#define BIT_GET_WLCLK_PHASE_8822B(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE_8822B) & BIT_MASK_WLCLK_PHASE_8822B) +#define BIT_SET_WLCLK_PHASE_8822B(x, v) \ + (BIT_CLEAR_WLCLK_PHASE_8822B(x) | BIT_WLCLK_PHASE_8822B(v)) /* 2 REG_SYS_SDIO_CTRL_8822B */ #define BIT_DBG_GNT_WL_BT_8822B BIT(27) @@ -994,13 +1435,34 @@ #define BIT_PCIE_WAIT_TIME_8822B BIT(9) #define BIT_MPCIE_REFCLK_XTAL_SEL_8822B BIT(8) +#define BIT_SHIFT_SI_AUTHORIZATION_8822B 0 +#define BIT_MASK_SI_AUTHORIZATION_8822B 0xff +#define BIT_SI_AUTHORIZATION_8822B(x) \ + (((x) & BIT_MASK_SI_AUTHORIZATION_8822B) \ + << BIT_SHIFT_SI_AUTHORIZATION_8822B) +#define BITS_SI_AUTHORIZATION_8822B \ + (BIT_MASK_SI_AUTHORIZATION_8822B << BIT_SHIFT_SI_AUTHORIZATION_8822B) +#define BIT_CLEAR_SI_AUTHORIZATION_8822B(x) \ + ((x) & (~BITS_SI_AUTHORIZATION_8822B)) +#define BIT_GET_SI_AUTHORIZATION_8822B(x) \ + (((x) >> BIT_SHIFT_SI_AUTHORIZATION_8822B) & \ + BIT_MASK_SI_AUTHORIZATION_8822B) +#define BIT_SET_SI_AUTHORIZATION_8822B(x, v) \ + (BIT_CLEAR_SI_AUTHORIZATION_8822B(x) | BIT_SI_AUTHORIZATION_8822B(v)) + /* 2 REG_HCI_OPT_CTRL_8822B */ #define BIT_SHIFT_TSFT_SEL_8822B 29 #define BIT_MASK_TSFT_SEL_8822B 0x7 -#define BIT_TSFT_SEL_8822B(x) (((x) & BIT_MASK_TSFT_SEL_8822B) << BIT_SHIFT_TSFT_SEL_8822B) -#define BIT_GET_TSFT_SEL_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_8822B) & BIT_MASK_TSFT_SEL_8822B) - +#define BIT_TSFT_SEL_8822B(x) \ + (((x) & BIT_MASK_TSFT_SEL_8822B) << BIT_SHIFT_TSFT_SEL_8822B) +#define BITS_TSFT_SEL_8822B \ + (BIT_MASK_TSFT_SEL_8822B << BIT_SHIFT_TSFT_SEL_8822B) +#define BIT_CLEAR_TSFT_SEL_8822B(x) ((x) & (~BITS_TSFT_SEL_8822B)) +#define BIT_GET_TSFT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_8822B) & BIT_MASK_TSFT_SEL_8822B) +#define BIT_SET_TSFT_SEL_8822B(x, v) \ + (BIT_CLEAR_TSFT_SEL_8822B(x) | BIT_TSFT_SEL_8822B(v)) #define BIT_USB_HOST_PWR_OFF_EN_8822B BIT(12) #define BIT_SYM_LPS_BLOCK_EN_8822B BIT(11) @@ -1010,9 +1472,15 @@ #define BIT_SHIFT_SDIO_PAD_E_8822B 5 #define BIT_MASK_SDIO_PAD_E_8822B 0x7 -#define BIT_SDIO_PAD_E_8822B(x) (((x) & BIT_MASK_SDIO_PAD_E_8822B) << BIT_SHIFT_SDIO_PAD_E_8822B) -#define BIT_GET_SDIO_PAD_E_8822B(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8822B) & BIT_MASK_SDIO_PAD_E_8822B) - +#define BIT_SDIO_PAD_E_8822B(x) \ + (((x) & BIT_MASK_SDIO_PAD_E_8822B) << BIT_SHIFT_SDIO_PAD_E_8822B) +#define BITS_SDIO_PAD_E_8822B \ + (BIT_MASK_SDIO_PAD_E_8822B << BIT_SHIFT_SDIO_PAD_E_8822B) +#define BIT_CLEAR_SDIO_PAD_E_8822B(x) ((x) & (~BITS_SDIO_PAD_E_8822B)) +#define BIT_GET_SDIO_PAD_E_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E_8822B) & BIT_MASK_SDIO_PAD_E_8822B) +#define BIT_SET_SDIO_PAD_E_8822B(x, v) \ + (BIT_CLEAR_SDIO_PAD_E_8822B(x) | BIT_SDIO_PAD_E_8822B(v)) #define BIT_USB_LPPLL_EN_8822B BIT(4) #define BIT_ROP_SW15_8822B BIT(2) @@ -1027,44 +1495,93 @@ #define BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B 21 #define BIT_MASK_AUTO_ZCD_IN_CODE_8822B 0x1f -#define BIT_AUTO_ZCD_IN_CODE_8822B(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B) << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) -#define BIT_GET_AUTO_ZCD_IN_CODE_8822B(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B) - - +#define BIT_AUTO_ZCD_IN_CODE_8822B(x) \ + (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B) \ + << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) +#define BITS_AUTO_ZCD_IN_CODE_8822B \ + (BIT_MASK_AUTO_ZCD_IN_CODE_8822B << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) +#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8822B(x) \ + ((x) & (~BITS_AUTO_ZCD_IN_CODE_8822B)) +#define BIT_GET_AUTO_ZCD_IN_CODE_8822B(x) \ + (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) & \ + BIT_MASK_AUTO_ZCD_IN_CODE_8822B) +#define BIT_SET_AUTO_ZCD_IN_CODE_8822B(x, v) \ + (BIT_CLEAR_AUTO_ZCD_IN_CODE_8822B(x) | BIT_AUTO_ZCD_IN_CODE_8822B(v)) #define BIT_SHIFT_ZCD_CODE_IN_L_8822B 16 #define BIT_MASK_ZCD_CODE_IN_L_8822B 0x1f -#define BIT_ZCD_CODE_IN_L_8822B(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8822B) << BIT_SHIFT_ZCD_CODE_IN_L_8822B) -#define BIT_GET_ZCD_CODE_IN_L_8822B(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822B) & BIT_MASK_ZCD_CODE_IN_L_8822B) - - +#define BIT_ZCD_CODE_IN_L_8822B(x) \ + (((x) & BIT_MASK_ZCD_CODE_IN_L_8822B) << BIT_SHIFT_ZCD_CODE_IN_L_8822B) +#define BITS_ZCD_CODE_IN_L_8822B \ + (BIT_MASK_ZCD_CODE_IN_L_8822B << BIT_SHIFT_ZCD_CODE_IN_L_8822B) +#define BIT_CLEAR_ZCD_CODE_IN_L_8822B(x) ((x) & (~BITS_ZCD_CODE_IN_L_8822B)) +#define BIT_GET_ZCD_CODE_IN_L_8822B(x) \ + (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822B) & BIT_MASK_ZCD_CODE_IN_L_8822B) +#define BIT_SET_ZCD_CODE_IN_L_8822B(x, v) \ + (BIT_CLEAR_ZCD_CODE_IN_L_8822B(x) | BIT_ZCD_CODE_IN_L_8822B(v)) #define BIT_SHIFT_LDO_HV5_DUMMY_8822B 14 #define BIT_MASK_LDO_HV5_DUMMY_8822B 0x3 -#define BIT_LDO_HV5_DUMMY_8822B(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8822B) << BIT_SHIFT_LDO_HV5_DUMMY_8822B) -#define BIT_GET_LDO_HV5_DUMMY_8822B(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8822B) & BIT_MASK_LDO_HV5_DUMMY_8822B) - - +#define BIT_LDO_HV5_DUMMY_8822B(x) \ + (((x) & BIT_MASK_LDO_HV5_DUMMY_8822B) << BIT_SHIFT_LDO_HV5_DUMMY_8822B) +#define BITS_LDO_HV5_DUMMY_8822B \ + (BIT_MASK_LDO_HV5_DUMMY_8822B << BIT_SHIFT_LDO_HV5_DUMMY_8822B) +#define BIT_CLEAR_LDO_HV5_DUMMY_8822B(x) ((x) & (~BITS_LDO_HV5_DUMMY_8822B)) +#define BIT_GET_LDO_HV5_DUMMY_8822B(x) \ + (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8822B) & BIT_MASK_LDO_HV5_DUMMY_8822B) +#define BIT_SET_LDO_HV5_DUMMY_8822B(x, v) \ + (BIT_CLEAR_LDO_HV5_DUMMY_8822B(x) | BIT_LDO_HV5_DUMMY_8822B(v)) #define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B 12 #define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B 0x3 -#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) -#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) - - +#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) \ + (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) +#define BITS_REG_VTUNE33_BIT0_TO_BIT1_8822B \ + (BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B \ + << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) +#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) \ + ((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1_8822B)) +#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) \ + (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) & \ + BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) +#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x, v) \ + (BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) | \ + BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(v)) #define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B 10 #define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B 0x3 -#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) -#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) - - +#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) \ + (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) +#define BITS_REG_STANDBY33_BIT0_TO_BIT1_8822B \ + (BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B \ + << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) +#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) \ + ((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1_8822B)) +#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) \ + (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) & \ + BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) +#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x, v) \ + (BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) | \ + BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(v)) #define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B 8 #define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B 0x3 -#define BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) -#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) - +#define BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(x) \ + (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) \ + << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) +#define BITS_REG_LOAD33_BIT0_TO_BIT1_8822B \ + (BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B \ + << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) +#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8822B(x) \ + ((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1_8822B)) +#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8822B(x) \ + (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) & \ + BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) +#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1_8822B(x, v) \ + (BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8822B(x) | \ + BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(v)) #define BIT_REG_BYPASS_L_8822B BIT(7) #define BIT_REG_LDOF_L_8822B BIT(6) @@ -1073,9 +1590,14 @@ #define BIT_SHIFT_CFC_L_8822B 1 #define BIT_MASK_CFC_L_8822B 0x3 -#define BIT_CFC_L_8822B(x) (((x) & BIT_MASK_CFC_L_8822B) << BIT_SHIFT_CFC_L_8822B) -#define BIT_GET_CFC_L_8822B(x) (((x) >> BIT_SHIFT_CFC_L_8822B) & BIT_MASK_CFC_L_8822B) - +#define BIT_CFC_L_8822B(x) \ + (((x) & BIT_MASK_CFC_L_8822B) << BIT_SHIFT_CFC_L_8822B) +#define BITS_CFC_L_8822B (BIT_MASK_CFC_L_8822B << BIT_SHIFT_CFC_L_8822B) +#define BIT_CLEAR_CFC_L_8822B(x) ((x) & (~BITS_CFC_L_8822B)) +#define BIT_GET_CFC_L_8822B(x) \ + (((x) >> BIT_SHIFT_CFC_L_8822B) & BIT_MASK_CFC_L_8822B) +#define BIT_SET_CFC_L_8822B(x, v) \ + (BIT_CLEAR_CFC_L_8822B(x) | BIT_CFC_L_8822B(v)) #define BIT_REG_OCPS_L_V1_8822B BIT(0) @@ -1084,8 +1606,11 @@ #define BIT_SHIFT_RPWM_8822B 24 #define BIT_MASK_RPWM_8822B 0xff #define BIT_RPWM_8822B(x) (((x) & BIT_MASK_RPWM_8822B) << BIT_SHIFT_RPWM_8822B) -#define BIT_GET_RPWM_8822B(x) (((x) >> BIT_SHIFT_RPWM_8822B) & BIT_MASK_RPWM_8822B) - +#define BITS_RPWM_8822B (BIT_MASK_RPWM_8822B << BIT_SHIFT_RPWM_8822B) +#define BIT_CLEAR_RPWM_8822B(x) ((x) & (~BITS_RPWM_8822B)) +#define BIT_GET_RPWM_8822B(x) \ + (((x) >> BIT_SHIFT_RPWM_8822B) & BIT_MASK_RPWM_8822B) +#define BIT_SET_RPWM_8822B(x, v) (BIT_CLEAR_RPWM_8822B(x) | BIT_RPWM_8822B(v)) #define BIT_ANA_PORT_EN_8822B BIT(22) #define BIT_MAC_PORT_EN_8822B BIT(21) @@ -1094,18 +1619,29 @@ #define BIT_SHIFT_ROM_PGE_8822B 16 #define BIT_MASK_ROM_PGE_8822B 0x7 -#define BIT_ROM_PGE_8822B(x) (((x) & BIT_MASK_ROM_PGE_8822B) << BIT_SHIFT_ROM_PGE_8822B) -#define BIT_GET_ROM_PGE_8822B(x) (((x) >> BIT_SHIFT_ROM_PGE_8822B) & BIT_MASK_ROM_PGE_8822B) - +#define BIT_ROM_PGE_8822B(x) \ + (((x) & BIT_MASK_ROM_PGE_8822B) << BIT_SHIFT_ROM_PGE_8822B) +#define BITS_ROM_PGE_8822B (BIT_MASK_ROM_PGE_8822B << BIT_SHIFT_ROM_PGE_8822B) +#define BIT_CLEAR_ROM_PGE_8822B(x) ((x) & (~BITS_ROM_PGE_8822B)) +#define BIT_GET_ROM_PGE_8822B(x) \ + (((x) >> BIT_SHIFT_ROM_PGE_8822B) & BIT_MASK_ROM_PGE_8822B) +#define BIT_SET_ROM_PGE_8822B(x, v) \ + (BIT_CLEAR_ROM_PGE_8822B(x) | BIT_ROM_PGE_8822B(v)) #define BIT_FW_INIT_RDY_8822B BIT(15) #define BIT_FW_DW_RDY_8822B BIT(14) #define BIT_SHIFT_CPU_CLK_SEL_8822B 12 #define BIT_MASK_CPU_CLK_SEL_8822B 0x3 -#define BIT_CPU_CLK_SEL_8822B(x) (((x) & BIT_MASK_CPU_CLK_SEL_8822B) << BIT_SHIFT_CPU_CLK_SEL_8822B) -#define BIT_GET_CPU_CLK_SEL_8822B(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8822B) & BIT_MASK_CPU_CLK_SEL_8822B) - +#define BIT_CPU_CLK_SEL_8822B(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL_8822B) << BIT_SHIFT_CPU_CLK_SEL_8822B) +#define BITS_CPU_CLK_SEL_8822B \ + (BIT_MASK_CPU_CLK_SEL_8822B << BIT_SHIFT_CPU_CLK_SEL_8822B) +#define BIT_CLEAR_CPU_CLK_SEL_8822B(x) ((x) & (~BITS_CPU_CLK_SEL_8822B)) +#define BIT_GET_CPU_CLK_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL_8822B) & BIT_MASK_CPU_CLK_SEL_8822B) +#define BIT_SET_CPU_CLK_SEL_8822B(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL_8822B(x) | BIT_CPU_CLK_SEL_8822B(v)) #define BIT_CCLK_CHG_MASK_8822B BIT(11) #define BIT_EMEM__TXBUF_CHKSUM_OK_8822B BIT(10) @@ -1122,44 +1658,68 @@ /* 2 REG_MCU_TST_CFG_8822B */ -#define BIT_SHIFT_LBKTST_8822B 0 -#define BIT_MASK_LBKTST_8822B 0xffff -#define BIT_LBKTST_8822B(x) (((x) & BIT_MASK_LBKTST_8822B) << BIT_SHIFT_LBKTST_8822B) -#define BIT_GET_LBKTST_8822B(x) (((x) >> BIT_SHIFT_LBKTST_8822B) & BIT_MASK_LBKTST_8822B) - - +#define BIT_SHIFT_C2H_MSG_8822B 0 +#define BIT_MASK_C2H_MSG_8822B 0xffff +#define BIT_C2H_MSG_8822B(x) \ + (((x) & BIT_MASK_C2H_MSG_8822B) << BIT_SHIFT_C2H_MSG_8822B) +#define BITS_C2H_MSG_8822B (BIT_MASK_C2H_MSG_8822B << BIT_SHIFT_C2H_MSG_8822B) +#define BIT_CLEAR_C2H_MSG_8822B(x) ((x) & (~BITS_C2H_MSG_8822B)) +#define BIT_GET_C2H_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_C2H_MSG_8822B) & BIT_MASK_C2H_MSG_8822B) +#define BIT_SET_C2H_MSG_8822B(x, v) \ + (BIT_CLEAR_C2H_MSG_8822B(x) | BIT_C2H_MSG_8822B(v)) /* 2 REG_HMEBOX_E0_E1_8822B */ #define BIT_SHIFT_HOST_MSG_E1_8822B 16 #define BIT_MASK_HOST_MSG_E1_8822B 0xffff -#define BIT_HOST_MSG_E1_8822B(x) (((x) & BIT_MASK_HOST_MSG_E1_8822B) << BIT_SHIFT_HOST_MSG_E1_8822B) -#define BIT_GET_HOST_MSG_E1_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8822B) & BIT_MASK_HOST_MSG_E1_8822B) - - +#define BIT_HOST_MSG_E1_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_E1_8822B) << BIT_SHIFT_HOST_MSG_E1_8822B) +#define BITS_HOST_MSG_E1_8822B \ + (BIT_MASK_HOST_MSG_E1_8822B << BIT_SHIFT_HOST_MSG_E1_8822B) +#define BIT_CLEAR_HOST_MSG_E1_8822B(x) ((x) & (~BITS_HOST_MSG_E1_8822B)) +#define BIT_GET_HOST_MSG_E1_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1_8822B) & BIT_MASK_HOST_MSG_E1_8822B) +#define BIT_SET_HOST_MSG_E1_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_E1_8822B(x) | BIT_HOST_MSG_E1_8822B(v)) #define BIT_SHIFT_HOST_MSG_E0_8822B 0 #define BIT_MASK_HOST_MSG_E0_8822B 0xffff -#define BIT_HOST_MSG_E0_8822B(x) (((x) & BIT_MASK_HOST_MSG_E0_8822B) << BIT_SHIFT_HOST_MSG_E0_8822B) -#define BIT_GET_HOST_MSG_E0_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8822B) & BIT_MASK_HOST_MSG_E0_8822B) - - +#define BIT_HOST_MSG_E0_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_E0_8822B) << BIT_SHIFT_HOST_MSG_E0_8822B) +#define BITS_HOST_MSG_E0_8822B \ + (BIT_MASK_HOST_MSG_E0_8822B << BIT_SHIFT_HOST_MSG_E0_8822B) +#define BIT_CLEAR_HOST_MSG_E0_8822B(x) ((x) & (~BITS_HOST_MSG_E0_8822B)) +#define BIT_GET_HOST_MSG_E0_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0_8822B) & BIT_MASK_HOST_MSG_E0_8822B) +#define BIT_SET_HOST_MSG_E0_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_E0_8822B(x) | BIT_HOST_MSG_E0_8822B(v)) /* 2 REG_HMEBOX_E2_E3_8822B */ #define BIT_SHIFT_HOST_MSG_E3_8822B 16 #define BIT_MASK_HOST_MSG_E3_8822B 0xffff -#define BIT_HOST_MSG_E3_8822B(x) (((x) & BIT_MASK_HOST_MSG_E3_8822B) << BIT_SHIFT_HOST_MSG_E3_8822B) -#define BIT_GET_HOST_MSG_E3_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8822B) & BIT_MASK_HOST_MSG_E3_8822B) - - +#define BIT_HOST_MSG_E3_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_E3_8822B) << BIT_SHIFT_HOST_MSG_E3_8822B) +#define BITS_HOST_MSG_E3_8822B \ + (BIT_MASK_HOST_MSG_E3_8822B << BIT_SHIFT_HOST_MSG_E3_8822B) +#define BIT_CLEAR_HOST_MSG_E3_8822B(x) ((x) & (~BITS_HOST_MSG_E3_8822B)) +#define BIT_GET_HOST_MSG_E3_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3_8822B) & BIT_MASK_HOST_MSG_E3_8822B) +#define BIT_SET_HOST_MSG_E3_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_E3_8822B(x) | BIT_HOST_MSG_E3_8822B(v)) #define BIT_SHIFT_HOST_MSG_E2_8822B 0 #define BIT_MASK_HOST_MSG_E2_8822B 0xffff -#define BIT_HOST_MSG_E2_8822B(x) (((x) & BIT_MASK_HOST_MSG_E2_8822B) << BIT_SHIFT_HOST_MSG_E2_8822B) -#define BIT_GET_HOST_MSG_E2_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8822B) & BIT_MASK_HOST_MSG_E2_8822B) - - +#define BIT_HOST_MSG_E2_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_E2_8822B) << BIT_SHIFT_HOST_MSG_E2_8822B) +#define BITS_HOST_MSG_E2_8822B \ + (BIT_MASK_HOST_MSG_E2_8822B << BIT_SHIFT_HOST_MSG_E2_8822B) +#define BIT_CLEAR_HOST_MSG_E2_8822B(x) ((x) & (~BITS_HOST_MSG_E2_8822B)) +#define BIT_GET_HOST_MSG_E2_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2_8822B) & BIT_MASK_HOST_MSG_E2_8822B) +#define BIT_SET_HOST_MSG_E2_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_E2_8822B(x) | BIT_HOST_MSG_E2_8822B(v)) /* 2 REG_WLLPS_CTRL_8822B */ #define BIT_WLLPSOP_EABM_8822B BIT(31) @@ -1176,16 +1736,35 @@ #define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B 12 #define BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B 0xf -#define BIT_LPLDH12_VADJ_STEP_DN_8822B(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) -#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) - - +#define BIT_LPLDH12_VADJ_STEP_DN_8822B(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) +#define BITS_LPLDH12_VADJ_STEP_DN_8822B \ + (BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) +#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822B(x) \ + ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8822B)) +#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822B(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) & \ + BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) +#define BIT_SET_LPLDH12_VADJ_STEP_DN_8822B(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822B(x) | \ + BIT_LPLDH12_VADJ_STEP_DN_8822B(v)) #define BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B 8 #define BIT_MASK_V15ADJ_L1_STEP_DN_8822B 0x7 -#define BIT_V15ADJ_L1_STEP_DN_8822B(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) -#define BIT_GET_V15ADJ_L1_STEP_DN_8822B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B) - +#define BIT_V15ADJ_L1_STEP_DN_8822B(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B) \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) +#define BITS_V15ADJ_L1_STEP_DN_8822B \ + (BIT_MASK_V15ADJ_L1_STEP_DN_8822B << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8822B(x) \ + ((x) & (~BITS_V15ADJ_L1_STEP_DN_8822B)) +#define BIT_GET_V15ADJ_L1_STEP_DN_8822B(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) & \ + BIT_MASK_V15ADJ_L1_STEP_DN_8822B) +#define BIT_SET_V15ADJ_L1_STEP_DN_8822B(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN_8822B(x) | BIT_V15ADJ_L1_STEP_DN_8822B(v)) #define BIT_REGU_32K_CLK_EN_8822B BIT(1) #define BIT_WL_LPS_EN_8822B BIT(0) @@ -1197,119 +1776,198 @@ #define BIT_SHIFT_REF_SEL_8822B 25 #define BIT_MASK_REF_SEL_8822B 0xf -#define BIT_REF_SEL_8822B(x) (((x) & BIT_MASK_REF_SEL_8822B) << BIT_SHIFT_REF_SEL_8822B) -#define BIT_GET_REF_SEL_8822B(x) (((x) >> BIT_SHIFT_REF_SEL_8822B) & BIT_MASK_REF_SEL_8822B) - - +#define BIT_REF_SEL_8822B(x) \ + (((x) & BIT_MASK_REF_SEL_8822B) << BIT_SHIFT_REF_SEL_8822B) +#define BITS_REF_SEL_8822B (BIT_MASK_REF_SEL_8822B << BIT_SHIFT_REF_SEL_8822B) +#define BIT_CLEAR_REF_SEL_8822B(x) ((x) & (~BITS_REF_SEL_8822B)) +#define BIT_GET_REF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_REF_SEL_8822B) & BIT_MASK_REF_SEL_8822B) +#define BIT_SET_REF_SEL_8822B(x, v) \ + (BIT_CLEAR_REF_SEL_8822B(x) | BIT_REF_SEL_8822B(v)) #define BIT_SHIFT_F0F_SDM_8822B 12 #define BIT_MASK_F0F_SDM_8822B 0x1fff -#define BIT_F0F_SDM_8822B(x) (((x) & BIT_MASK_F0F_SDM_8822B) << BIT_SHIFT_F0F_SDM_8822B) -#define BIT_GET_F0F_SDM_8822B(x) (((x) >> BIT_SHIFT_F0F_SDM_8822B) & BIT_MASK_F0F_SDM_8822B) - - +#define BIT_F0F_SDM_8822B(x) \ + (((x) & BIT_MASK_F0F_SDM_8822B) << BIT_SHIFT_F0F_SDM_8822B) +#define BITS_F0F_SDM_8822B (BIT_MASK_F0F_SDM_8822B << BIT_SHIFT_F0F_SDM_8822B) +#define BIT_CLEAR_F0F_SDM_8822B(x) ((x) & (~BITS_F0F_SDM_8822B)) +#define BIT_GET_F0F_SDM_8822B(x) \ + (((x) >> BIT_SHIFT_F0F_SDM_8822B) & BIT_MASK_F0F_SDM_8822B) +#define BIT_SET_F0F_SDM_8822B(x, v) \ + (BIT_CLEAR_F0F_SDM_8822B(x) | BIT_F0F_SDM_8822B(v)) #define BIT_SHIFT_F0N_SDM_8822B 9 #define BIT_MASK_F0N_SDM_8822B 0x7 -#define BIT_F0N_SDM_8822B(x) (((x) & BIT_MASK_F0N_SDM_8822B) << BIT_SHIFT_F0N_SDM_8822B) -#define BIT_GET_F0N_SDM_8822B(x) (((x) >> BIT_SHIFT_F0N_SDM_8822B) & BIT_MASK_F0N_SDM_8822B) - - +#define BIT_F0N_SDM_8822B(x) \ + (((x) & BIT_MASK_F0N_SDM_8822B) << BIT_SHIFT_F0N_SDM_8822B) +#define BITS_F0N_SDM_8822B (BIT_MASK_F0N_SDM_8822B << BIT_SHIFT_F0N_SDM_8822B) +#define BIT_CLEAR_F0N_SDM_8822B(x) ((x) & (~BITS_F0N_SDM_8822B)) +#define BIT_GET_F0N_SDM_8822B(x) \ + (((x) >> BIT_SHIFT_F0N_SDM_8822B) & BIT_MASK_F0N_SDM_8822B) +#define BIT_SET_F0N_SDM_8822B(x, v) \ + (BIT_CLEAR_F0N_SDM_8822B(x) | BIT_F0N_SDM_8822B(v)) #define BIT_SHIFT_DIVN_SDM_8822B 3 #define BIT_MASK_DIVN_SDM_8822B 0x3f -#define BIT_DIVN_SDM_8822B(x) (((x) & BIT_MASK_DIVN_SDM_8822B) << BIT_SHIFT_DIVN_SDM_8822B) -#define BIT_GET_DIVN_SDM_8822B(x) (((x) >> BIT_SHIFT_DIVN_SDM_8822B) & BIT_MASK_DIVN_SDM_8822B) - - +#define BIT_DIVN_SDM_8822B(x) \ + (((x) & BIT_MASK_DIVN_SDM_8822B) << BIT_SHIFT_DIVN_SDM_8822B) +#define BITS_DIVN_SDM_8822B \ + (BIT_MASK_DIVN_SDM_8822B << BIT_SHIFT_DIVN_SDM_8822B) +#define BIT_CLEAR_DIVN_SDM_8822B(x) ((x) & (~BITS_DIVN_SDM_8822B)) +#define BIT_GET_DIVN_SDM_8822B(x) \ + (((x) >> BIT_SHIFT_DIVN_SDM_8822B) & BIT_MASK_DIVN_SDM_8822B) +#define BIT_SET_DIVN_SDM_8822B(x, v) \ + (BIT_CLEAR_DIVN_SDM_8822B(x) | BIT_DIVN_SDM_8822B(v)) /* 2 REG_GPIO_DEBOUNCE_CTRL_8822B */ #define BIT_WLGP_DBC1EN_8822B BIT(15) #define BIT_SHIFT_WLGP_DBC1_8822B 8 #define BIT_MASK_WLGP_DBC1_8822B 0xf -#define BIT_WLGP_DBC1_8822B(x) (((x) & BIT_MASK_WLGP_DBC1_8822B) << BIT_SHIFT_WLGP_DBC1_8822B) -#define BIT_GET_WLGP_DBC1_8822B(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8822B) & BIT_MASK_WLGP_DBC1_8822B) - +#define BIT_WLGP_DBC1_8822B(x) \ + (((x) & BIT_MASK_WLGP_DBC1_8822B) << BIT_SHIFT_WLGP_DBC1_8822B) +#define BITS_WLGP_DBC1_8822B \ + (BIT_MASK_WLGP_DBC1_8822B << BIT_SHIFT_WLGP_DBC1_8822B) +#define BIT_CLEAR_WLGP_DBC1_8822B(x) ((x) & (~BITS_WLGP_DBC1_8822B)) +#define BIT_GET_WLGP_DBC1_8822B(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC1_8822B) & BIT_MASK_WLGP_DBC1_8822B) +#define BIT_SET_WLGP_DBC1_8822B(x, v) \ + (BIT_CLEAR_WLGP_DBC1_8822B(x) | BIT_WLGP_DBC1_8822B(v)) #define BIT_WLGP_DBC0EN_8822B BIT(7) #define BIT_SHIFT_WLGP_DBC0_8822B 0 #define BIT_MASK_WLGP_DBC0_8822B 0xf -#define BIT_WLGP_DBC0_8822B(x) (((x) & BIT_MASK_WLGP_DBC0_8822B) << BIT_SHIFT_WLGP_DBC0_8822B) -#define BIT_GET_WLGP_DBC0_8822B(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8822B) & BIT_MASK_WLGP_DBC0_8822B) - - +#define BIT_WLGP_DBC0_8822B(x) \ + (((x) & BIT_MASK_WLGP_DBC0_8822B) << BIT_SHIFT_WLGP_DBC0_8822B) +#define BITS_WLGP_DBC0_8822B \ + (BIT_MASK_WLGP_DBC0_8822B << BIT_SHIFT_WLGP_DBC0_8822B) +#define BIT_CLEAR_WLGP_DBC0_8822B(x) ((x) & (~BITS_WLGP_DBC0_8822B)) +#define BIT_GET_WLGP_DBC0_8822B(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC0_8822B) & BIT_MASK_WLGP_DBC0_8822B) +#define BIT_SET_WLGP_DBC0_8822B(x, v) \ + (BIT_CLEAR_WLGP_DBC0_8822B(x) | BIT_WLGP_DBC0_8822B(v)) /* 2 REG_RPWM2_8822B */ #define BIT_SHIFT_RPWM2_8822B 16 #define BIT_MASK_RPWM2_8822B 0xffff -#define BIT_RPWM2_8822B(x) (((x) & BIT_MASK_RPWM2_8822B) << BIT_SHIFT_RPWM2_8822B) -#define BIT_GET_RPWM2_8822B(x) (((x) >> BIT_SHIFT_RPWM2_8822B) & BIT_MASK_RPWM2_8822B) - - +#define BIT_RPWM2_8822B(x) \ + (((x) & BIT_MASK_RPWM2_8822B) << BIT_SHIFT_RPWM2_8822B) +#define BITS_RPWM2_8822B (BIT_MASK_RPWM2_8822B << BIT_SHIFT_RPWM2_8822B) +#define BIT_CLEAR_RPWM2_8822B(x) ((x) & (~BITS_RPWM2_8822B)) +#define BIT_GET_RPWM2_8822B(x) \ + (((x) >> BIT_SHIFT_RPWM2_8822B) & BIT_MASK_RPWM2_8822B) +#define BIT_SET_RPWM2_8822B(x, v) \ + (BIT_CLEAR_RPWM2_8822B(x) | BIT_RPWM2_8822B(v)) /* 2 REG_SYSON_FSM_MON_8822B */ #define BIT_SHIFT_FSM_MON_SEL_8822B 24 #define BIT_MASK_FSM_MON_SEL_8822B 0x7 -#define BIT_FSM_MON_SEL_8822B(x) (((x) & BIT_MASK_FSM_MON_SEL_8822B) << BIT_SHIFT_FSM_MON_SEL_8822B) -#define BIT_GET_FSM_MON_SEL_8822B(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8822B) & BIT_MASK_FSM_MON_SEL_8822B) - +#define BIT_FSM_MON_SEL_8822B(x) \ + (((x) & BIT_MASK_FSM_MON_SEL_8822B) << BIT_SHIFT_FSM_MON_SEL_8822B) +#define BITS_FSM_MON_SEL_8822B \ + (BIT_MASK_FSM_MON_SEL_8822B << BIT_SHIFT_FSM_MON_SEL_8822B) +#define BIT_CLEAR_FSM_MON_SEL_8822B(x) ((x) & (~BITS_FSM_MON_SEL_8822B)) +#define BIT_GET_FSM_MON_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL_8822B) & BIT_MASK_FSM_MON_SEL_8822B) +#define BIT_SET_FSM_MON_SEL_8822B(x, v) \ + (BIT_CLEAR_FSM_MON_SEL_8822B(x) | BIT_FSM_MON_SEL_8822B(v)) #define BIT_DOP_ELDO_8822B BIT(23) #define BIT_FSM_MON_UPD_8822B BIT(15) #define BIT_SHIFT_FSM_PAR_8822B 0 #define BIT_MASK_FSM_PAR_8822B 0x7fff -#define BIT_FSM_PAR_8822B(x) (((x) & BIT_MASK_FSM_PAR_8822B) << BIT_SHIFT_FSM_PAR_8822B) -#define BIT_GET_FSM_PAR_8822B(x) (((x) >> BIT_SHIFT_FSM_PAR_8822B) & BIT_MASK_FSM_PAR_8822B) - - +#define BIT_FSM_PAR_8822B(x) \ + (((x) & BIT_MASK_FSM_PAR_8822B) << BIT_SHIFT_FSM_PAR_8822B) +#define BITS_FSM_PAR_8822B (BIT_MASK_FSM_PAR_8822B << BIT_SHIFT_FSM_PAR_8822B) +#define BIT_CLEAR_FSM_PAR_8822B(x) ((x) & (~BITS_FSM_PAR_8822B)) +#define BIT_GET_FSM_PAR_8822B(x) \ + (((x) >> BIT_SHIFT_FSM_PAR_8822B) & BIT_MASK_FSM_PAR_8822B) +#define BIT_SET_FSM_PAR_8822B(x, v) \ + (BIT_CLEAR_FSM_PAR_8822B(x) | BIT_FSM_PAR_8822B(v)) /* 2 REG_AFE_CTRL6_8822B */ #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0 #define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0x7 -#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) -#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) - - +#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) \ + (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) +#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B \ + (BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B \ + << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) +#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) \ + ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) \ + (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) & \ + BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) +#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x, v) \ + (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) | \ + BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(v)) /* 2 REG_PMC_DBG_CTRL1_8822B */ #define BIT_BT_INT_EN_8822B BIT(31) #define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B 16 #define BIT_MASK_RD_WR_WIFI_BT_INFO_8822B 0x7fff -#define BIT_RD_WR_WIFI_BT_INFO_8822B(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) -#define BIT_GET_RD_WR_WIFI_BT_INFO_8822B(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) - +#define BIT_RD_WR_WIFI_BT_INFO_8822B(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) +#define BITS_RD_WR_WIFI_BT_INFO_8822B \ + (BIT_MASK_RD_WR_WIFI_BT_INFO_8822B \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822B(x) \ + ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8822B)) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) & \ + BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) +#define BIT_SET_RD_WR_WIFI_BT_INFO_8822B(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822B(x) | \ + BIT_RD_WR_WIFI_BT_INFO_8822B(v)) #define BIT_PMC_WR_OVF_8822B BIT(8) #define BIT_SHIFT_WLPMC_ERRINT_8822B 0 #define BIT_MASK_WLPMC_ERRINT_8822B 0xff -#define BIT_WLPMC_ERRINT_8822B(x) (((x) & BIT_MASK_WLPMC_ERRINT_8822B) << BIT_SHIFT_WLPMC_ERRINT_8822B) -#define BIT_GET_WLPMC_ERRINT_8822B(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8822B) & BIT_MASK_WLPMC_ERRINT_8822B) - - +#define BIT_WLPMC_ERRINT_8822B(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT_8822B) << BIT_SHIFT_WLPMC_ERRINT_8822B) +#define BITS_WLPMC_ERRINT_8822B \ + (BIT_MASK_WLPMC_ERRINT_8822B << BIT_SHIFT_WLPMC_ERRINT_8822B) +#define BIT_CLEAR_WLPMC_ERRINT_8822B(x) ((x) & (~BITS_WLPMC_ERRINT_8822B)) +#define BIT_GET_WLPMC_ERRINT_8822B(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT_8822B) & BIT_MASK_WLPMC_ERRINT_8822B) +#define BIT_SET_WLPMC_ERRINT_8822B(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT_8822B(x) | BIT_WLPMC_ERRINT_8822B(v)) /* 2 REG_AFE_CTRL7_8822B */ #define BIT_SHIFT_SEL_V_8822B 30 #define BIT_MASK_SEL_V_8822B 0x3 -#define BIT_SEL_V_8822B(x) (((x) & BIT_MASK_SEL_V_8822B) << BIT_SHIFT_SEL_V_8822B) -#define BIT_GET_SEL_V_8822B(x) (((x) >> BIT_SHIFT_SEL_V_8822B) & BIT_MASK_SEL_V_8822B) - +#define BIT_SEL_V_8822B(x) \ + (((x) & BIT_MASK_SEL_V_8822B) << BIT_SHIFT_SEL_V_8822B) +#define BITS_SEL_V_8822B (BIT_MASK_SEL_V_8822B << BIT_SHIFT_SEL_V_8822B) +#define BIT_CLEAR_SEL_V_8822B(x) ((x) & (~BITS_SEL_V_8822B)) +#define BIT_GET_SEL_V_8822B(x) \ + (((x) >> BIT_SHIFT_SEL_V_8822B) & BIT_MASK_SEL_V_8822B) +#define BIT_SET_SEL_V_8822B(x, v) \ + (BIT_CLEAR_SEL_V_8822B(x) | BIT_SEL_V_8822B(v)) #define BIT_SEL_LDO_PC_8822B BIT(29) #define BIT_SHIFT_CK_MON_SEL_8822B 26 #define BIT_MASK_CK_MON_SEL_8822B 0x7 -#define BIT_CK_MON_SEL_8822B(x) (((x) & BIT_MASK_CK_MON_SEL_8822B) << BIT_SHIFT_CK_MON_SEL_8822B) -#define BIT_GET_CK_MON_SEL_8822B(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8822B) & BIT_MASK_CK_MON_SEL_8822B) - +#define BIT_CK_MON_SEL_8822B(x) \ + (((x) & BIT_MASK_CK_MON_SEL_8822B) << BIT_SHIFT_CK_MON_SEL_8822B) +#define BITS_CK_MON_SEL_8822B \ + (BIT_MASK_CK_MON_SEL_8822B << BIT_SHIFT_CK_MON_SEL_8822B) +#define BIT_CLEAR_CK_MON_SEL_8822B(x) ((x) & (~BITS_CK_MON_SEL_8822B)) +#define BIT_GET_CK_MON_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_CK_MON_SEL_8822B) & BIT_MASK_CK_MON_SEL_8822B) +#define BIT_SET_CK_MON_SEL_8822B(x, v) \ + (BIT_CLEAR_CK_MON_SEL_8822B(x) | BIT_CK_MON_SEL_8822B(v)) #define BIT_CK_MON_EN_8822B BIT(25) #define BIT_FREF_EDGE_8822B BIT(24) @@ -1329,8 +1987,8 @@ #define BIT_BCNDMAINT0_MSK_8822B BIT(20) #define BIT_BCNDERR0_MSK_8822B BIT(16) #define BIT_HSISR_IND_ON_INT_MSK_8822B BIT(15) -#define BIT_BCNDMAINT_E_MSK_8822B BIT(14) -#define BIT_CTWEND_MSK_8822B BIT(12) +#define BIT_HISR3_IND_INT_MSK_8822B BIT(14) +#define BIT_HISR2_IND_INT_MSK_8822B BIT(13) #define BIT_HISR1_IND_MSK_8822B BIT(11) #define BIT_C2HCMD_MSK_8822B BIT(10) #define BIT_CPWM2_MSK_8822B BIT(9) @@ -1345,8 +2003,8 @@ #define BIT_RXOK_MSK_8822B BIT(0) /* 2 REG_HISR0_8822B */ -#define BIT_TIMEOUT_INTERRUPT2_8822B BIT(31) -#define BIT_TIMEOUT_INTERRUTP1_8822B BIT(30) +#define BIT_PSTIMEOUT2_8822B BIT(31) +#define BIT_PSTIMEOUT1_8822B BIT(30) #define BIT_PSTIMEOUT_8822B BIT(29) #define BIT_GTINT4_8822B BIT(28) #define BIT_GTINT3_8822B BIT(27) @@ -1356,8 +2014,8 @@ #define BIT_BCNDMAINT0_8822B BIT(20) #define BIT_BCNDERR0_8822B BIT(16) #define BIT_HSISR_IND_ON_INT_8822B BIT(15) -#define BIT_BCNDMAINT_E_8822B BIT(14) -#define BIT_CTWEND_8822B BIT(12) +#define BIT_HISR3_IND_INT_8822B BIT(14) +#define BIT_HISR2_IND_INT_8822B BIT(13) #define BIT_HISR1_IND_INT_8822B BIT(11) #define BIT_C2HCMD_8822B BIT(10) #define BIT_CPWM2_8822B BIT(9) @@ -1374,7 +2032,6 @@ /* 2 REG_HIMR1_8822B */ #define BIT_TXFIFO_TH_INT_8822B BIT(30) #define BIT_BTON_STS_UPDATE_MASK_8822B BIT(29) -#define BIT_MCU_ERR_MASK_8822B BIT(28) #define BIT_BCNDMAINT7__MSK_8822B BIT(27) #define BIT_BCNDMAINT6__MSK_8822B BIT(26) #define BIT_BCNDMAINT5__MSK_8822B BIT(25) @@ -1389,8 +2046,7 @@ #define BIT_BCNDERR3_MSK_8822B BIT(16) #define BIT_BCNDERR2_MSK_8822B BIT(15) #define BIT_BCNDERR1_MSK_8822B BIT(14) -#define BIT_ATIMEND_E_MSK_8822B BIT(13) -#define BIT_ATIMEND__MSK_8822B BIT(12) +#define BIT_ATIMEND_E_V1_MSK_8822B BIT(12) #define BIT_TXERR_MSK_8822B BIT(11) #define BIT_RXERR_MSK_8822B BIT(10) #define BIT_TXFOVW_MSK_8822B BIT(9) @@ -1404,7 +2060,6 @@ /* 2 REG_HISR1_8822B */ #define BIT_TXFIFO_TH_INT_8822B BIT(30) #define BIT_BTON_STS_UPDATE_INT_8822B BIT(29) -#define BIT_MCU_ERR_8822B BIT(28) #define BIT_BCNDMAINT7_8822B BIT(27) #define BIT_BCNDMAINT6_8822B BIT(26) #define BIT_BCNDMAINT5_8822B BIT(25) @@ -1419,8 +2074,7 @@ #define BIT_BCNDERR3_8822B BIT(16) #define BIT_BCNDERR2_8822B BIT(15) #define BIT_BCNDERR1_8822B BIT(14) -#define BIT_ATIMEND_E_8822B BIT(13) -#define BIT_ATIMEND_8822B BIT(12) +#define BIT_ATIMEND_E_V1_INT_8822B BIT(12) #define BIT_TXERR_INT_8822B BIT(11) #define BIT_RXERR_INT_8822B BIT(10) #define BIT_TXFOVW_8822B BIT(9) @@ -1435,28 +2089,48 @@ #define BIT_SHIFT_DEBUG_ST_8822B 0 #define BIT_MASK_DEBUG_ST_8822B 0xffffffffL -#define BIT_DEBUG_ST_8822B(x) (((x) & BIT_MASK_DEBUG_ST_8822B) << BIT_SHIFT_DEBUG_ST_8822B) -#define BIT_GET_DEBUG_ST_8822B(x) (((x) >> BIT_SHIFT_DEBUG_ST_8822B) & BIT_MASK_DEBUG_ST_8822B) - - +#define BIT_DEBUG_ST_8822B(x) \ + (((x) & BIT_MASK_DEBUG_ST_8822B) << BIT_SHIFT_DEBUG_ST_8822B) +#define BITS_DEBUG_ST_8822B \ + (BIT_MASK_DEBUG_ST_8822B << BIT_SHIFT_DEBUG_ST_8822B) +#define BIT_CLEAR_DEBUG_ST_8822B(x) ((x) & (~BITS_DEBUG_ST_8822B)) +#define BIT_GET_DEBUG_ST_8822B(x) \ + (((x) >> BIT_SHIFT_DEBUG_ST_8822B) & BIT_MASK_DEBUG_ST_8822B) +#define BIT_SET_DEBUG_ST_8822B(x, v) \ + (BIT_CLEAR_DEBUG_ST_8822B(x) | BIT_DEBUG_ST_8822B(v)) /* 2 REG_PAD_CTRL2_8822B */ #define BIT_USB3_USB2_TRANSITION_8822B BIT(20) #define BIT_SHIFT_USB23_SW_MODE_V1_8822B 18 #define BIT_MASK_USB23_SW_MODE_V1_8822B 0x3 -#define BIT_USB23_SW_MODE_V1_8822B(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8822B) << BIT_SHIFT_USB23_SW_MODE_V1_8822B) -#define BIT_GET_USB23_SW_MODE_V1_8822B(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822B) & BIT_MASK_USB23_SW_MODE_V1_8822B) - +#define BIT_USB23_SW_MODE_V1_8822B(x) \ + (((x) & BIT_MASK_USB23_SW_MODE_V1_8822B) \ + << BIT_SHIFT_USB23_SW_MODE_V1_8822B) +#define BITS_USB23_SW_MODE_V1_8822B \ + (BIT_MASK_USB23_SW_MODE_V1_8822B << BIT_SHIFT_USB23_SW_MODE_V1_8822B) +#define BIT_CLEAR_USB23_SW_MODE_V1_8822B(x) \ + ((x) & (~BITS_USB23_SW_MODE_V1_8822B)) +#define BIT_GET_USB23_SW_MODE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822B) & \ + BIT_MASK_USB23_SW_MODE_V1_8822B) +#define BIT_SET_USB23_SW_MODE_V1_8822B(x, v) \ + (BIT_CLEAR_USB23_SW_MODE_V1_8822B(x) | BIT_USB23_SW_MODE_V1_8822B(v)) #define BIT_NO_PDN_CHIPOFF_V1_8822B BIT(17) #define BIT_RSM_EN_V1_8822B BIT(16) #define BIT_SHIFT_MATCH_CNT_8822B 8 #define BIT_MASK_MATCH_CNT_8822B 0xff -#define BIT_MATCH_CNT_8822B(x) (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B) -#define BIT_GET_MATCH_CNT_8822B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B) - +#define BIT_MATCH_CNT_8822B(x) \ + (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B) +#define BITS_MATCH_CNT_8822B \ + (BIT_MASK_MATCH_CNT_8822B << BIT_SHIFT_MATCH_CNT_8822B) +#define BIT_CLEAR_MATCH_CNT_8822B(x) ((x) & (~BITS_MATCH_CNT_8822B)) +#define BIT_GET_MATCH_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B) +#define BIT_SET_MATCH_CNT_8822B(x, v) \ + (BIT_CLEAR_MATCH_CNT_8822B(x) | BIT_MATCH_CNT_8822B(v)) #define BIT_LD_B12V_EN_8822B BIT(7) #define BIT_EECS_IOSEL_V1_8822B BIT(6) @@ -1472,9 +2146,17 @@ #define BIT_SHIFT_EFUSE_BURN_GNT_8822B 24 #define BIT_MASK_EFUSE_BURN_GNT_8822B 0xff -#define BIT_EFUSE_BURN_GNT_8822B(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8822B) << BIT_SHIFT_EFUSE_BURN_GNT_8822B) -#define BIT_GET_EFUSE_BURN_GNT_8822B(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822B) & BIT_MASK_EFUSE_BURN_GNT_8822B) - +#define BIT_EFUSE_BURN_GNT_8822B(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT_8822B) \ + << BIT_SHIFT_EFUSE_BURN_GNT_8822B) +#define BITS_EFUSE_BURN_GNT_8822B \ + (BIT_MASK_EFUSE_BURN_GNT_8822B << BIT_SHIFT_EFUSE_BURN_GNT_8822B) +#define BIT_CLEAR_EFUSE_BURN_GNT_8822B(x) ((x) & (~BITS_EFUSE_BURN_GNT_8822B)) +#define BIT_GET_EFUSE_BURN_GNT_8822B(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822B) & \ + BIT_MASK_EFUSE_BURN_GNT_8822B) +#define BIT_SET_EFUSE_BURN_GNT_8822B(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT_8822B(x) | BIT_EFUSE_BURN_GNT_8822B(v)) #define BIT_STOP_WL_PMC_8822B BIT(9) #define BIT_STOP_SYM_PMC_8822B BIT(8) @@ -1485,10 +2167,15 @@ #define BIT_SHIFT_SYSON_REG_ARB_8822B 0 #define BIT_MASK_SYSON_REG_ARB_8822B 0x3 -#define BIT_SYSON_REG_ARB_8822B(x) (((x) & BIT_MASK_SYSON_REG_ARB_8822B) << BIT_SHIFT_SYSON_REG_ARB_8822B) -#define BIT_GET_SYSON_REG_ARB_8822B(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8822B) & BIT_MASK_SYSON_REG_ARB_8822B) - - +#define BIT_SYSON_REG_ARB_8822B(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB_8822B) << BIT_SHIFT_SYSON_REG_ARB_8822B) +#define BITS_SYSON_REG_ARB_8822B \ + (BIT_MASK_SYSON_REG_ARB_8822B << BIT_SHIFT_SYSON_REG_ARB_8822B) +#define BIT_CLEAR_SYSON_REG_ARB_8822B(x) ((x) & (~BITS_SYSON_REG_ARB_8822B)) +#define BIT_GET_SYSON_REG_ARB_8822B(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB_8822B) & BIT_MASK_SYSON_REG_ARB_8822B) +#define BIT_SET_SYSON_REG_ARB_8822B(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB_8822B(x) | BIT_SYSON_REG_ARB_8822B(v)) /* 2 REG_BIST_CTRL_8822B */ #define BIT_BIST_USB_DIS_8822B BIT(27) @@ -1498,9 +2185,15 @@ #define BIT_SHIFT_BIST_RPT_SEL_8822B 16 #define BIT_MASK_BIST_RPT_SEL_8822B 0xf -#define BIT_BIST_RPT_SEL_8822B(x) (((x) & BIT_MASK_BIST_RPT_SEL_8822B) << BIT_SHIFT_BIST_RPT_SEL_8822B) -#define BIT_GET_BIST_RPT_SEL_8822B(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8822B) & BIT_MASK_BIST_RPT_SEL_8822B) - +#define BIT_BIST_RPT_SEL_8822B(x) \ + (((x) & BIT_MASK_BIST_RPT_SEL_8822B) << BIT_SHIFT_BIST_RPT_SEL_8822B) +#define BITS_BIST_RPT_SEL_8822B \ + (BIT_MASK_BIST_RPT_SEL_8822B << BIT_SHIFT_BIST_RPT_SEL_8822B) +#define BIT_CLEAR_BIST_RPT_SEL_8822B(x) ((x) & (~BITS_BIST_RPT_SEL_8822B)) +#define BIT_GET_BIST_RPT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_BIST_RPT_SEL_8822B) & BIT_MASK_BIST_RPT_SEL_8822B) +#define BIT_SET_BIST_RPT_SEL_8822B(x, v) \ + (BIT_CLEAR_BIST_RPT_SEL_8822B(x) | BIT_BIST_RPT_SEL_8822B(v)) #define BIT_BIST_RESUME_PS_8822B BIT(4) #define BIT_BIST_RESUME_8822B BIT(3) @@ -1512,62 +2205,100 @@ #define BIT_SHIFT_MBIST_REPORT_8822B 0 #define BIT_MASK_MBIST_REPORT_8822B 0xffffffffL -#define BIT_MBIST_REPORT_8822B(x) (((x) & BIT_MASK_MBIST_REPORT_8822B) << BIT_SHIFT_MBIST_REPORT_8822B) -#define BIT_GET_MBIST_REPORT_8822B(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8822B) & BIT_MASK_MBIST_REPORT_8822B) - - +#define BIT_MBIST_REPORT_8822B(x) \ + (((x) & BIT_MASK_MBIST_REPORT_8822B) << BIT_SHIFT_MBIST_REPORT_8822B) +#define BITS_MBIST_REPORT_8822B \ + (BIT_MASK_MBIST_REPORT_8822B << BIT_SHIFT_MBIST_REPORT_8822B) +#define BIT_CLEAR_MBIST_REPORT_8822B(x) ((x) & (~BITS_MBIST_REPORT_8822B)) +#define BIT_GET_MBIST_REPORT_8822B(x) \ + (((x) >> BIT_SHIFT_MBIST_REPORT_8822B) & BIT_MASK_MBIST_REPORT_8822B) +#define BIT_SET_MBIST_REPORT_8822B(x, v) \ + (BIT_CLEAR_MBIST_REPORT_8822B(x) | BIT_MBIST_REPORT_8822B(v)) /* 2 REG_MEM_CTRL_8822B */ #define BIT_UMEM_RME_8822B BIT(31) #define BIT_SHIFT_BT_SPRAM_8822B 28 #define BIT_MASK_BT_SPRAM_8822B 0x3 -#define BIT_BT_SPRAM_8822B(x) (((x) & BIT_MASK_BT_SPRAM_8822B) << BIT_SHIFT_BT_SPRAM_8822B) -#define BIT_GET_BT_SPRAM_8822B(x) (((x) >> BIT_SHIFT_BT_SPRAM_8822B) & BIT_MASK_BT_SPRAM_8822B) - - +#define BIT_BT_SPRAM_8822B(x) \ + (((x) & BIT_MASK_BT_SPRAM_8822B) << BIT_SHIFT_BT_SPRAM_8822B) +#define BITS_BT_SPRAM_8822B \ + (BIT_MASK_BT_SPRAM_8822B << BIT_SHIFT_BT_SPRAM_8822B) +#define BIT_CLEAR_BT_SPRAM_8822B(x) ((x) & (~BITS_BT_SPRAM_8822B)) +#define BIT_GET_BT_SPRAM_8822B(x) \ + (((x) >> BIT_SHIFT_BT_SPRAM_8822B) & BIT_MASK_BT_SPRAM_8822B) +#define BIT_SET_BT_SPRAM_8822B(x, v) \ + (BIT_CLEAR_BT_SPRAM_8822B(x) | BIT_BT_SPRAM_8822B(v)) #define BIT_SHIFT_BT_ROM_8822B 24 #define BIT_MASK_BT_ROM_8822B 0xf -#define BIT_BT_ROM_8822B(x) (((x) & BIT_MASK_BT_ROM_8822B) << BIT_SHIFT_BT_ROM_8822B) -#define BIT_GET_BT_ROM_8822B(x) (((x) >> BIT_SHIFT_BT_ROM_8822B) & BIT_MASK_BT_ROM_8822B) - - +#define BIT_BT_ROM_8822B(x) \ + (((x) & BIT_MASK_BT_ROM_8822B) << BIT_SHIFT_BT_ROM_8822B) +#define BITS_BT_ROM_8822B (BIT_MASK_BT_ROM_8822B << BIT_SHIFT_BT_ROM_8822B) +#define BIT_CLEAR_BT_ROM_8822B(x) ((x) & (~BITS_BT_ROM_8822B)) +#define BIT_GET_BT_ROM_8822B(x) \ + (((x) >> BIT_SHIFT_BT_ROM_8822B) & BIT_MASK_BT_ROM_8822B) +#define BIT_SET_BT_ROM_8822B(x, v) \ + (BIT_CLEAR_BT_ROM_8822B(x) | BIT_BT_ROM_8822B(v)) #define BIT_SHIFT_PCI_DPRAM_8822B 10 #define BIT_MASK_PCI_DPRAM_8822B 0x3 -#define BIT_PCI_DPRAM_8822B(x) (((x) & BIT_MASK_PCI_DPRAM_8822B) << BIT_SHIFT_PCI_DPRAM_8822B) -#define BIT_GET_PCI_DPRAM_8822B(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8822B) & BIT_MASK_PCI_DPRAM_8822B) - - +#define BIT_PCI_DPRAM_8822B(x) \ + (((x) & BIT_MASK_PCI_DPRAM_8822B) << BIT_SHIFT_PCI_DPRAM_8822B) +#define BITS_PCI_DPRAM_8822B \ + (BIT_MASK_PCI_DPRAM_8822B << BIT_SHIFT_PCI_DPRAM_8822B) +#define BIT_CLEAR_PCI_DPRAM_8822B(x) ((x) & (~BITS_PCI_DPRAM_8822B)) +#define BIT_GET_PCI_DPRAM_8822B(x) \ + (((x) >> BIT_SHIFT_PCI_DPRAM_8822B) & BIT_MASK_PCI_DPRAM_8822B) +#define BIT_SET_PCI_DPRAM_8822B(x, v) \ + (BIT_CLEAR_PCI_DPRAM_8822B(x) | BIT_PCI_DPRAM_8822B(v)) #define BIT_SHIFT_PCI_SPRAM_8822B 8 #define BIT_MASK_PCI_SPRAM_8822B 0x3 -#define BIT_PCI_SPRAM_8822B(x) (((x) & BIT_MASK_PCI_SPRAM_8822B) << BIT_SHIFT_PCI_SPRAM_8822B) -#define BIT_GET_PCI_SPRAM_8822B(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8822B) & BIT_MASK_PCI_SPRAM_8822B) - - +#define BIT_PCI_SPRAM_8822B(x) \ + (((x) & BIT_MASK_PCI_SPRAM_8822B) << BIT_SHIFT_PCI_SPRAM_8822B) +#define BITS_PCI_SPRAM_8822B \ + (BIT_MASK_PCI_SPRAM_8822B << BIT_SHIFT_PCI_SPRAM_8822B) +#define BIT_CLEAR_PCI_SPRAM_8822B(x) ((x) & (~BITS_PCI_SPRAM_8822B)) +#define BIT_GET_PCI_SPRAM_8822B(x) \ + (((x) >> BIT_SHIFT_PCI_SPRAM_8822B) & BIT_MASK_PCI_SPRAM_8822B) +#define BIT_SET_PCI_SPRAM_8822B(x, v) \ + (BIT_CLEAR_PCI_SPRAM_8822B(x) | BIT_PCI_SPRAM_8822B(v)) #define BIT_SHIFT_USB_SPRAM_8822B 6 #define BIT_MASK_USB_SPRAM_8822B 0x3 -#define BIT_USB_SPRAM_8822B(x) (((x) & BIT_MASK_USB_SPRAM_8822B) << BIT_SHIFT_USB_SPRAM_8822B) -#define BIT_GET_USB_SPRAM_8822B(x) (((x) >> BIT_SHIFT_USB_SPRAM_8822B) & BIT_MASK_USB_SPRAM_8822B) - - +#define BIT_USB_SPRAM_8822B(x) \ + (((x) & BIT_MASK_USB_SPRAM_8822B) << BIT_SHIFT_USB_SPRAM_8822B) +#define BITS_USB_SPRAM_8822B \ + (BIT_MASK_USB_SPRAM_8822B << BIT_SHIFT_USB_SPRAM_8822B) +#define BIT_CLEAR_USB_SPRAM_8822B(x) ((x) & (~BITS_USB_SPRAM_8822B)) +#define BIT_GET_USB_SPRAM_8822B(x) \ + (((x) >> BIT_SHIFT_USB_SPRAM_8822B) & BIT_MASK_USB_SPRAM_8822B) +#define BIT_SET_USB_SPRAM_8822B(x, v) \ + (BIT_CLEAR_USB_SPRAM_8822B(x) | BIT_USB_SPRAM_8822B(v)) #define BIT_SHIFT_USB_SPRF_8822B 4 #define BIT_MASK_USB_SPRF_8822B 0x3 -#define BIT_USB_SPRF_8822B(x) (((x) & BIT_MASK_USB_SPRF_8822B) << BIT_SHIFT_USB_SPRF_8822B) -#define BIT_GET_USB_SPRF_8822B(x) (((x) >> BIT_SHIFT_USB_SPRF_8822B) & BIT_MASK_USB_SPRF_8822B) - - +#define BIT_USB_SPRF_8822B(x) \ + (((x) & BIT_MASK_USB_SPRF_8822B) << BIT_SHIFT_USB_SPRF_8822B) +#define BITS_USB_SPRF_8822B \ + (BIT_MASK_USB_SPRF_8822B << BIT_SHIFT_USB_SPRF_8822B) +#define BIT_CLEAR_USB_SPRF_8822B(x) ((x) & (~BITS_USB_SPRF_8822B)) +#define BIT_GET_USB_SPRF_8822B(x) \ + (((x) >> BIT_SHIFT_USB_SPRF_8822B) & BIT_MASK_USB_SPRF_8822B) +#define BIT_SET_USB_SPRF_8822B(x, v) \ + (BIT_CLEAR_USB_SPRF_8822B(x) | BIT_USB_SPRF_8822B(v)) #define BIT_SHIFT_MCU_ROM_8822B 0 #define BIT_MASK_MCU_ROM_8822B 0xf -#define BIT_MCU_ROM_8822B(x) (((x) & BIT_MASK_MCU_ROM_8822B) << BIT_SHIFT_MCU_ROM_8822B) -#define BIT_GET_MCU_ROM_8822B(x) (((x) >> BIT_SHIFT_MCU_ROM_8822B) & BIT_MASK_MCU_ROM_8822B) - - +#define BIT_MCU_ROM_8822B(x) \ + (((x) & BIT_MASK_MCU_ROM_8822B) << BIT_SHIFT_MCU_ROM_8822B) +#define BITS_MCU_ROM_8822B (BIT_MASK_MCU_ROM_8822B << BIT_SHIFT_MCU_ROM_8822B) +#define BIT_CLEAR_MCU_ROM_8822B(x) ((x) & (~BITS_MCU_ROM_8822B)) +#define BIT_GET_MCU_ROM_8822B(x) \ + (((x) >> BIT_SHIFT_MCU_ROM_8822B) & BIT_MASK_MCU_ROM_8822B) +#define BIT_SET_MCU_ROM_8822B(x, v) \ + (BIT_CLEAR_MCU_ROM_8822B(x) | BIT_MCU_ROM_8822B(v)) /* 2 REG_AFE_CTRL8_8822B */ #define BIT_SYN_AGPIO_8822B BIT(20) @@ -1576,10 +2307,15 @@ #define BIT_SHIFT_XTAL_SEL_TOK_8822B 0 #define BIT_MASK_XTAL_SEL_TOK_8822B 0x7 -#define BIT_XTAL_SEL_TOK_8822B(x) (((x) & BIT_MASK_XTAL_SEL_TOK_8822B) << BIT_SHIFT_XTAL_SEL_TOK_8822B) -#define BIT_GET_XTAL_SEL_TOK_8822B(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8822B) & BIT_MASK_XTAL_SEL_TOK_8822B) - - +#define BIT_XTAL_SEL_TOK_8822B(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_8822B) << BIT_SHIFT_XTAL_SEL_TOK_8822B) +#define BITS_XTAL_SEL_TOK_8822B \ + (BIT_MASK_XTAL_SEL_TOK_8822B << BIT_SHIFT_XTAL_SEL_TOK_8822B) +#define BIT_CLEAR_XTAL_SEL_TOK_8822B(x) ((x) & (~BITS_XTAL_SEL_TOK_8822B)) +#define BIT_GET_XTAL_SEL_TOK_8822B(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8822B) & BIT_MASK_XTAL_SEL_TOK_8822B) +#define BIT_SET_XTAL_SEL_TOK_8822B(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_8822B(x) | BIT_XTAL_SEL_TOK_8822B(v)) /* 2 REG_USB_SIE_INTF_8822B */ #define BIT_RD_SEL_8822B BIT(31) @@ -1589,24 +2325,48 @@ #define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B 16 #define BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B 0x1ff -#define BIT_USB_SIE_INTF_ADDR_V1_8822B(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) -#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) - - +#define BIT_USB_SIE_INTF_ADDR_V1_8822B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) +#define BITS_USB_SIE_INTF_ADDR_V1_8822B \ + (BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) +#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822B(x) \ + ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8822B)) +#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) & \ + BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) +#define BIT_SET_USB_SIE_INTF_ADDR_V1_8822B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822B(x) | \ + BIT_USB_SIE_INTF_ADDR_V1_8822B(v)) #define BIT_SHIFT_USB_SIE_INTF_RD_8822B 8 #define BIT_MASK_USB_SIE_INTF_RD_8822B 0xff -#define BIT_USB_SIE_INTF_RD_8822B(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8822B) << BIT_SHIFT_USB_SIE_INTF_RD_8822B) -#define BIT_GET_USB_SIE_INTF_RD_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822B) & BIT_MASK_USB_SIE_INTF_RD_8822B) - - +#define BIT_USB_SIE_INTF_RD_8822B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_RD_8822B) \ + << BIT_SHIFT_USB_SIE_INTF_RD_8822B) +#define BITS_USB_SIE_INTF_RD_8822B \ + (BIT_MASK_USB_SIE_INTF_RD_8822B << BIT_SHIFT_USB_SIE_INTF_RD_8822B) +#define BIT_CLEAR_USB_SIE_INTF_RD_8822B(x) ((x) & (~BITS_USB_SIE_INTF_RD_8822B)) +#define BIT_GET_USB_SIE_INTF_RD_8822B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822B) & \ + BIT_MASK_USB_SIE_INTF_RD_8822B) +#define BIT_SET_USB_SIE_INTF_RD_8822B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_RD_8822B(x) | BIT_USB_SIE_INTF_RD_8822B(v)) #define BIT_SHIFT_USB_SIE_INTF_WD_8822B 0 #define BIT_MASK_USB_SIE_INTF_WD_8822B 0xff -#define BIT_USB_SIE_INTF_WD_8822B(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8822B) << BIT_SHIFT_USB_SIE_INTF_WD_8822B) -#define BIT_GET_USB_SIE_INTF_WD_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822B) & BIT_MASK_USB_SIE_INTF_WD_8822B) - - +#define BIT_USB_SIE_INTF_WD_8822B(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_WD_8822B) \ + << BIT_SHIFT_USB_SIE_INTF_WD_8822B) +#define BITS_USB_SIE_INTF_WD_8822B \ + (BIT_MASK_USB_SIE_INTF_WD_8822B << BIT_SHIFT_USB_SIE_INTF_WD_8822B) +#define BIT_CLEAR_USB_SIE_INTF_WD_8822B(x) ((x) & (~BITS_USB_SIE_INTF_WD_8822B)) +#define BIT_GET_USB_SIE_INTF_WD_8822B(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822B) & \ + BIT_MASK_USB_SIE_INTF_WD_8822B) +#define BIT_SET_USB_SIE_INTF_WD_8822B(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_WD_8822B(x) | BIT_USB_SIE_INTF_WD_8822B(v)) /* 2 REG_PCIE_MIO_INTF_8822B */ #define BIT_PCIE_MIO_BYIOREG_8822B BIT(13) @@ -1614,43 +2374,69 @@ #define BIT_SHIFT_PCIE_MIO_WE_8822B 8 #define BIT_MASK_PCIE_MIO_WE_8822B 0xf -#define BIT_PCIE_MIO_WE_8822B(x) (((x) & BIT_MASK_PCIE_MIO_WE_8822B) << BIT_SHIFT_PCIE_MIO_WE_8822B) -#define BIT_GET_PCIE_MIO_WE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8822B) & BIT_MASK_PCIE_MIO_WE_8822B) - - +#define BIT_PCIE_MIO_WE_8822B(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE_8822B) << BIT_SHIFT_PCIE_MIO_WE_8822B) +#define BITS_PCIE_MIO_WE_8822B \ + (BIT_MASK_PCIE_MIO_WE_8822B << BIT_SHIFT_PCIE_MIO_WE_8822B) +#define BIT_CLEAR_PCIE_MIO_WE_8822B(x) ((x) & (~BITS_PCIE_MIO_WE_8822B)) +#define BIT_GET_PCIE_MIO_WE_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE_8822B) & BIT_MASK_PCIE_MIO_WE_8822B) +#define BIT_SET_PCIE_MIO_WE_8822B(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE_8822B(x) | BIT_PCIE_MIO_WE_8822B(v)) #define BIT_SHIFT_PCIE_MIO_ADDR_8822B 0 #define BIT_MASK_PCIE_MIO_ADDR_8822B 0xff -#define BIT_PCIE_MIO_ADDR_8822B(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8822B) << BIT_SHIFT_PCIE_MIO_ADDR_8822B) -#define BIT_GET_PCIE_MIO_ADDR_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822B) & BIT_MASK_PCIE_MIO_ADDR_8822B) - - +#define BIT_PCIE_MIO_ADDR_8822B(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_8822B) << BIT_SHIFT_PCIE_MIO_ADDR_8822B) +#define BITS_PCIE_MIO_ADDR_8822B \ + (BIT_MASK_PCIE_MIO_ADDR_8822B << BIT_SHIFT_PCIE_MIO_ADDR_8822B) +#define BIT_CLEAR_PCIE_MIO_ADDR_8822B(x) ((x) & (~BITS_PCIE_MIO_ADDR_8822B)) +#define BIT_GET_PCIE_MIO_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822B) & BIT_MASK_PCIE_MIO_ADDR_8822B) +#define BIT_SET_PCIE_MIO_ADDR_8822B(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_8822B(x) | BIT_PCIE_MIO_ADDR_8822B(v)) /* 2 REG_PCIE_MIO_INTD_8822B */ #define BIT_SHIFT_PCIE_MIO_DATA_8822B 0 #define BIT_MASK_PCIE_MIO_DATA_8822B 0xffffffffL -#define BIT_PCIE_MIO_DATA_8822B(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8822B) << BIT_SHIFT_PCIE_MIO_DATA_8822B) -#define BIT_GET_PCIE_MIO_DATA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822B) & BIT_MASK_PCIE_MIO_DATA_8822B) - - +#define BIT_PCIE_MIO_DATA_8822B(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA_8822B) << BIT_SHIFT_PCIE_MIO_DATA_8822B) +#define BITS_PCIE_MIO_DATA_8822B \ + (BIT_MASK_PCIE_MIO_DATA_8822B << BIT_SHIFT_PCIE_MIO_DATA_8822B) +#define BIT_CLEAR_PCIE_MIO_DATA_8822B(x) ((x) & (~BITS_PCIE_MIO_DATA_8822B)) +#define BIT_GET_PCIE_MIO_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822B) & BIT_MASK_PCIE_MIO_DATA_8822B) +#define BIT_SET_PCIE_MIO_DATA_8822B(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA_8822B(x) | BIT_PCIE_MIO_DATA_8822B(v)) /* 2 REG_WLRF1_8822B */ #define BIT_SHIFT_WLRF1_CTRL_8822B 24 #define BIT_MASK_WLRF1_CTRL_8822B 0xff -#define BIT_WLRF1_CTRL_8822B(x) (((x) & BIT_MASK_WLRF1_CTRL_8822B) << BIT_SHIFT_WLRF1_CTRL_8822B) -#define BIT_GET_WLRF1_CTRL_8822B(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8822B) & BIT_MASK_WLRF1_CTRL_8822B) - - +#define BIT_WLRF1_CTRL_8822B(x) \ + (((x) & BIT_MASK_WLRF1_CTRL_8822B) << BIT_SHIFT_WLRF1_CTRL_8822B) +#define BITS_WLRF1_CTRL_8822B \ + (BIT_MASK_WLRF1_CTRL_8822B << BIT_SHIFT_WLRF1_CTRL_8822B) +#define BIT_CLEAR_WLRF1_CTRL_8822B(x) ((x) & (~BITS_WLRF1_CTRL_8822B)) +#define BIT_GET_WLRF1_CTRL_8822B(x) \ + (((x) >> BIT_SHIFT_WLRF1_CTRL_8822B) & BIT_MASK_WLRF1_CTRL_8822B) +#define BIT_SET_WLRF1_CTRL_8822B(x, v) \ + (BIT_CLEAR_WLRF1_CTRL_8822B(x) | BIT_WLRF1_CTRL_8822B(v)) /* 2 REG_SYS_CFG1_8822B */ #define BIT_SHIFT_TRP_ICFG_8822B 28 #define BIT_MASK_TRP_ICFG_8822B 0xf -#define BIT_TRP_ICFG_8822B(x) (((x) & BIT_MASK_TRP_ICFG_8822B) << BIT_SHIFT_TRP_ICFG_8822B) -#define BIT_GET_TRP_ICFG_8822B(x) (((x) >> BIT_SHIFT_TRP_ICFG_8822B) & BIT_MASK_TRP_ICFG_8822B) - +#define BIT_TRP_ICFG_8822B(x) \ + (((x) & BIT_MASK_TRP_ICFG_8822B) << BIT_SHIFT_TRP_ICFG_8822B) +#define BITS_TRP_ICFG_8822B \ + (BIT_MASK_TRP_ICFG_8822B << BIT_SHIFT_TRP_ICFG_8822B) +#define BIT_CLEAR_TRP_ICFG_8822B(x) ((x) & (~BITS_TRP_ICFG_8822B)) +#define BIT_GET_TRP_ICFG_8822B(x) \ + (((x) >> BIT_SHIFT_TRP_ICFG_8822B) & BIT_MASK_TRP_ICFG_8822B) +#define BIT_SET_TRP_ICFG_8822B(x, v) \ + (BIT_CLEAR_TRP_ICFG_8822B(x) | BIT_TRP_ICFG_8822B(v)) #define BIT_RF_TYPE_ID_8822B BIT(27) #define BIT_BD_HCI_SEL_8822B BIT(26) @@ -1662,16 +2448,27 @@ #define BIT_SHIFT_VENDOR_ID_8822B 16 #define BIT_MASK_VENDOR_ID_8822B 0xf -#define BIT_VENDOR_ID_8822B(x) (((x) & BIT_MASK_VENDOR_ID_8822B) << BIT_SHIFT_VENDOR_ID_8822B) -#define BIT_GET_VENDOR_ID_8822B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8822B) & BIT_MASK_VENDOR_ID_8822B) - - +#define BIT_VENDOR_ID_8822B(x) \ + (((x) & BIT_MASK_VENDOR_ID_8822B) << BIT_SHIFT_VENDOR_ID_8822B) +#define BITS_VENDOR_ID_8822B \ + (BIT_MASK_VENDOR_ID_8822B << BIT_SHIFT_VENDOR_ID_8822B) +#define BIT_CLEAR_VENDOR_ID_8822B(x) ((x) & (~BITS_VENDOR_ID_8822B)) +#define BIT_GET_VENDOR_ID_8822B(x) \ + (((x) >> BIT_SHIFT_VENDOR_ID_8822B) & BIT_MASK_VENDOR_ID_8822B) +#define BIT_SET_VENDOR_ID_8822B(x, v) \ + (BIT_CLEAR_VENDOR_ID_8822B(x) | BIT_VENDOR_ID_8822B(v)) #define BIT_SHIFT_CHIP_VER_8822B 12 #define BIT_MASK_CHIP_VER_8822B 0xf -#define BIT_CHIP_VER_8822B(x) (((x) & BIT_MASK_CHIP_VER_8822B) << BIT_SHIFT_CHIP_VER_8822B) -#define BIT_GET_CHIP_VER_8822B(x) (((x) >> BIT_SHIFT_CHIP_VER_8822B) & BIT_MASK_CHIP_VER_8822B) - +#define BIT_CHIP_VER_8822B(x) \ + (((x) & BIT_MASK_CHIP_VER_8822B) << BIT_SHIFT_CHIP_VER_8822B) +#define BITS_CHIP_VER_8822B \ + (BIT_MASK_CHIP_VER_8822B << BIT_SHIFT_CHIP_VER_8822B) +#define BIT_CLEAR_CHIP_VER_8822B(x) ((x) & (~BITS_CHIP_VER_8822B)) +#define BIT_GET_CHIP_VER_8822B(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_8822B) & BIT_MASK_CHIP_VER_8822B) +#define BIT_SET_CHIP_VER_8822B(x, v) \ + (BIT_CLEAR_CHIP_VER_8822B(x) | BIT_CHIP_VER_8822B(v)) #define BIT_BD_MAC3_8822B BIT(11) #define BIT_BD_MAC1_8822B BIT(10) @@ -1690,24 +2487,41 @@ #define BIT_SHIFT_RF_RL_ID_8822B 28 #define BIT_MASK_RF_RL_ID_8822B 0xf -#define BIT_RF_RL_ID_8822B(x) (((x) & BIT_MASK_RF_RL_ID_8822B) << BIT_SHIFT_RF_RL_ID_8822B) -#define BIT_GET_RF_RL_ID_8822B(x) (((x) >> BIT_SHIFT_RF_RL_ID_8822B) & BIT_MASK_RF_RL_ID_8822B) - +#define BIT_RF_RL_ID_8822B(x) \ + (((x) & BIT_MASK_RF_RL_ID_8822B) << BIT_SHIFT_RF_RL_ID_8822B) +#define BITS_RF_RL_ID_8822B \ + (BIT_MASK_RF_RL_ID_8822B << BIT_SHIFT_RF_RL_ID_8822B) +#define BIT_CLEAR_RF_RL_ID_8822B(x) ((x) & (~BITS_RF_RL_ID_8822B)) +#define BIT_GET_RF_RL_ID_8822B(x) \ + (((x) >> BIT_SHIFT_RF_RL_ID_8822B) & BIT_MASK_RF_RL_ID_8822B) +#define BIT_SET_RF_RL_ID_8822B(x, v) \ + (BIT_CLEAR_RF_RL_ID_8822B(x) | BIT_RF_RL_ID_8822B(v)) #define BIT_HPHY_ICFG_8822B BIT(19) #define BIT_SHIFT_SEL_0XC0_8822B 16 #define BIT_MASK_SEL_0XC0_8822B 0x3 -#define BIT_SEL_0XC0_8822B(x) (((x) & BIT_MASK_SEL_0XC0_8822B) << BIT_SHIFT_SEL_0XC0_8822B) -#define BIT_GET_SEL_0XC0_8822B(x) (((x) >> BIT_SHIFT_SEL_0XC0_8822B) & BIT_MASK_SEL_0XC0_8822B) - - +#define BIT_SEL_0XC0_8822B(x) \ + (((x) & BIT_MASK_SEL_0XC0_8822B) << BIT_SHIFT_SEL_0XC0_8822B) +#define BITS_SEL_0XC0_8822B \ + (BIT_MASK_SEL_0XC0_8822B << BIT_SHIFT_SEL_0XC0_8822B) +#define BIT_CLEAR_SEL_0XC0_8822B(x) ((x) & (~BITS_SEL_0XC0_8822B)) +#define BIT_GET_SEL_0XC0_8822B(x) \ + (((x) >> BIT_SHIFT_SEL_0XC0_8822B) & BIT_MASK_SEL_0XC0_8822B) +#define BIT_SET_SEL_0XC0_8822B(x, v) \ + (BIT_CLEAR_SEL_0XC0_8822B(x) | BIT_SEL_0XC0_8822B(v)) #define BIT_SHIFT_HCI_SEL_V3_8822B 12 #define BIT_MASK_HCI_SEL_V3_8822B 0x7 -#define BIT_HCI_SEL_V3_8822B(x) (((x) & BIT_MASK_HCI_SEL_V3_8822B) << BIT_SHIFT_HCI_SEL_V3_8822B) -#define BIT_GET_HCI_SEL_V3_8822B(x) (((x) >> BIT_SHIFT_HCI_SEL_V3_8822B) & BIT_MASK_HCI_SEL_V3_8822B) - +#define BIT_HCI_SEL_V3_8822B(x) \ + (((x) & BIT_MASK_HCI_SEL_V3_8822B) << BIT_SHIFT_HCI_SEL_V3_8822B) +#define BITS_HCI_SEL_V3_8822B \ + (BIT_MASK_HCI_SEL_V3_8822B << BIT_SHIFT_HCI_SEL_V3_8822B) +#define BIT_CLEAR_HCI_SEL_V3_8822B(x) ((x) & (~BITS_HCI_SEL_V3_8822B)) +#define BIT_GET_HCI_SEL_V3_8822B(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V3_8822B) & BIT_MASK_HCI_SEL_V3_8822B) +#define BIT_SET_HCI_SEL_V3_8822B(x, v) \ + (BIT_CLEAR_HCI_SEL_V3_8822B(x) | BIT_HCI_SEL_V3_8822B(v)) #define BIT_USB_OPERATION_MODE_8822B BIT(10) #define BIT_BT_PDN_8822B BIT(9) @@ -1717,17 +2531,31 @@ #define BIT_SHIFT_PAD_HCI_SEL_V1_8822B 3 #define BIT_MASK_PAD_HCI_SEL_V1_8822B 0x7 -#define BIT_PAD_HCI_SEL_V1_8822B(x) (((x) & BIT_MASK_PAD_HCI_SEL_V1_8822B) << BIT_SHIFT_PAD_HCI_SEL_V1_8822B) -#define BIT_GET_PAD_HCI_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1_8822B) & BIT_MASK_PAD_HCI_SEL_V1_8822B) - - +#define BIT_PAD_HCI_SEL_V1_8822B(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V1_8822B) \ + << BIT_SHIFT_PAD_HCI_SEL_V1_8822B) +#define BITS_PAD_HCI_SEL_V1_8822B \ + (BIT_MASK_PAD_HCI_SEL_V1_8822B << BIT_SHIFT_PAD_HCI_SEL_V1_8822B) +#define BIT_CLEAR_PAD_HCI_SEL_V1_8822B(x) ((x) & (~BITS_PAD_HCI_SEL_V1_8822B)) +#define BIT_GET_PAD_HCI_SEL_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1_8822B) & \ + BIT_MASK_PAD_HCI_SEL_V1_8822B) +#define BIT_SET_PAD_HCI_SEL_V1_8822B(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V1_8822B(x) | BIT_PAD_HCI_SEL_V1_8822B(v)) #define BIT_SHIFT_EFS_HCI_SEL_V1_8822B 0 #define BIT_MASK_EFS_HCI_SEL_V1_8822B 0x7 -#define BIT_EFS_HCI_SEL_V1_8822B(x) (((x) & BIT_MASK_EFS_HCI_SEL_V1_8822B) << BIT_SHIFT_EFS_HCI_SEL_V1_8822B) -#define BIT_GET_EFS_HCI_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822B) & BIT_MASK_EFS_HCI_SEL_V1_8822B) - - +#define BIT_EFS_HCI_SEL_V1_8822B(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_V1_8822B) \ + << BIT_SHIFT_EFS_HCI_SEL_V1_8822B) +#define BITS_EFS_HCI_SEL_V1_8822B \ + (BIT_MASK_EFS_HCI_SEL_V1_8822B << BIT_SHIFT_EFS_HCI_SEL_V1_8822B) +#define BIT_CLEAR_EFS_HCI_SEL_V1_8822B(x) ((x) & (~BITS_EFS_HCI_SEL_V1_8822B)) +#define BIT_GET_EFS_HCI_SEL_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822B) & \ + BIT_MASK_EFS_HCI_SEL_V1_8822B) +#define BIT_SET_EFS_HCI_SEL_V1_8822B(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_V1_8822B(x) | BIT_EFS_HCI_SEL_V1_8822B(v)) /* 2 REG_SYS_STATUS2_8822B */ #define BIT_SIO_ALDN_8822B BIT(19) @@ -1737,27 +2565,39 @@ #define BIT_SHIFT_EPVID1_8822B 8 #define BIT_MASK_EPVID1_8822B 0xff -#define BIT_EPVID1_8822B(x) (((x) & BIT_MASK_EPVID1_8822B) << BIT_SHIFT_EPVID1_8822B) -#define BIT_GET_EPVID1_8822B(x) (((x) >> BIT_SHIFT_EPVID1_8822B) & BIT_MASK_EPVID1_8822B) - - +#define BIT_EPVID1_8822B(x) \ + (((x) & BIT_MASK_EPVID1_8822B) << BIT_SHIFT_EPVID1_8822B) +#define BITS_EPVID1_8822B (BIT_MASK_EPVID1_8822B << BIT_SHIFT_EPVID1_8822B) +#define BIT_CLEAR_EPVID1_8822B(x) ((x) & (~BITS_EPVID1_8822B)) +#define BIT_GET_EPVID1_8822B(x) \ + (((x) >> BIT_SHIFT_EPVID1_8822B) & BIT_MASK_EPVID1_8822B) +#define BIT_SET_EPVID1_8822B(x, v) \ + (BIT_CLEAR_EPVID1_8822B(x) | BIT_EPVID1_8822B(v)) #define BIT_SHIFT_EPVID0_8822B 0 #define BIT_MASK_EPVID0_8822B 0xff -#define BIT_EPVID0_8822B(x) (((x) & BIT_MASK_EPVID0_8822B) << BIT_SHIFT_EPVID0_8822B) -#define BIT_GET_EPVID0_8822B(x) (((x) >> BIT_SHIFT_EPVID0_8822B) & BIT_MASK_EPVID0_8822B) - - +#define BIT_EPVID0_8822B(x) \ + (((x) & BIT_MASK_EPVID0_8822B) << BIT_SHIFT_EPVID0_8822B) +#define BITS_EPVID0_8822B (BIT_MASK_EPVID0_8822B << BIT_SHIFT_EPVID0_8822B) +#define BIT_CLEAR_EPVID0_8822B(x) ((x) & (~BITS_EPVID0_8822B)) +#define BIT_GET_EPVID0_8822B(x) \ + (((x) >> BIT_SHIFT_EPVID0_8822B) & BIT_MASK_EPVID0_8822B) +#define BIT_SET_EPVID0_8822B(x, v) \ + (BIT_CLEAR_EPVID0_8822B(x) | BIT_EPVID0_8822B(v)) /* 2 REG_SYS_CFG2_8822B */ -#define BIT_HCI_SEL_EMBEDED_8822B BIT(8) +#define BIT_HCI_SEL_EMBEDDED_8822B BIT(8) #define BIT_SHIFT_HW_ID_8822B 0 #define BIT_MASK_HW_ID_8822B 0xff -#define BIT_HW_ID_8822B(x) (((x) & BIT_MASK_HW_ID_8822B) << BIT_SHIFT_HW_ID_8822B) -#define BIT_GET_HW_ID_8822B(x) (((x) >> BIT_SHIFT_HW_ID_8822B) & BIT_MASK_HW_ID_8822B) - - +#define BIT_HW_ID_8822B(x) \ + (((x) & BIT_MASK_HW_ID_8822B) << BIT_SHIFT_HW_ID_8822B) +#define BITS_HW_ID_8822B (BIT_MASK_HW_ID_8822B << BIT_SHIFT_HW_ID_8822B) +#define BIT_CLEAR_HW_ID_8822B(x) ((x) & (~BITS_HW_ID_8822B)) +#define BIT_GET_HW_ID_8822B(x) \ + (((x) >> BIT_SHIFT_HW_ID_8822B) & BIT_MASK_HW_ID_8822B) +#define BIT_SET_HW_ID_8822B(x, v) \ + (BIT_CLEAR_HW_ID_8822B(x) | BIT_HW_ID_8822B(v)) /* 2 REG_SYS_CFG3_8822B */ #define BIT_PWC_MA33V_8822B BIT(15) @@ -1785,19 +2625,31 @@ #define BIT_SHIFT_CPU_DMEM_CON_8822B 0 #define BIT_MASK_CPU_DMEM_CON_8822B 0xff -#define BIT_CPU_DMEM_CON_8822B(x) (((x) & BIT_MASK_CPU_DMEM_CON_8822B) << BIT_SHIFT_CPU_DMEM_CON_8822B) -#define BIT_GET_CPU_DMEM_CON_8822B(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8822B) & BIT_MASK_CPU_DMEM_CON_8822B) - - +#define BIT_CPU_DMEM_CON_8822B(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON_8822B) << BIT_SHIFT_CPU_DMEM_CON_8822B) +#define BITS_CPU_DMEM_CON_8822B \ + (BIT_MASK_CPU_DMEM_CON_8822B << BIT_SHIFT_CPU_DMEM_CON_8822B) +#define BIT_CLEAR_CPU_DMEM_CON_8822B(x) ((x) & (~BITS_CPU_DMEM_CON_8822B)) +#define BIT_GET_CPU_DMEM_CON_8822B(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON_8822B) & BIT_MASK_CPU_DMEM_CON_8822B) +#define BIT_SET_CPU_DMEM_CON_8822B(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON_8822B(x) | BIT_CPU_DMEM_CON_8822B(v)) /* 2 REG_BOOT_REASON_8822B */ -#define BIT_SHIFT_BOOT_REASON_8822B 0 -#define BIT_MASK_BOOT_REASON_8822B 0x7 -#define BIT_BOOT_REASON_8822B(x) (((x) & BIT_MASK_BOOT_REASON_8822B) << BIT_SHIFT_BOOT_REASON_8822B) -#define BIT_GET_BOOT_REASON_8822B(x) (((x) >> BIT_SHIFT_BOOT_REASON_8822B) & BIT_MASK_BOOT_REASON_8822B) - - +#define BIT_SHIFT_BOOT_REASON_V1_8822B 0 +#define BIT_MASK_BOOT_REASON_V1_8822B 0x7 +#define BIT_BOOT_REASON_V1_8822B(x) \ + (((x) & BIT_MASK_BOOT_REASON_V1_8822B) \ + << BIT_SHIFT_BOOT_REASON_V1_8822B) +#define BITS_BOOT_REASON_V1_8822B \ + (BIT_MASK_BOOT_REASON_V1_8822B << BIT_SHIFT_BOOT_REASON_V1_8822B) +#define BIT_CLEAR_BOOT_REASON_V1_8822B(x) ((x) & (~BITS_BOOT_REASON_V1_8822B)) +#define BIT_GET_BOOT_REASON_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BOOT_REASON_V1_8822B) & \ + BIT_MASK_BOOT_REASON_V1_8822B) +#define BIT_SET_BOOT_REASON_V1_8822B(x, v) \ + (BIT_CLEAR_BOOT_REASON_V1_8822B(x) | BIT_BOOT_REASON_V1_8822B(v)) /* 2 REG_NFCPAD_CTRL_8822B */ #define BIT_PAD_SHUTDW_8822B BIT(18) @@ -1810,24 +2662,39 @@ #define BIT_SHIFT_NFCPAD_IO_SEL_8822B 8 #define BIT_MASK_NFCPAD_IO_SEL_8822B 0xf -#define BIT_NFCPAD_IO_SEL_8822B(x) (((x) & BIT_MASK_NFCPAD_IO_SEL_8822B) << BIT_SHIFT_NFCPAD_IO_SEL_8822B) -#define BIT_GET_NFCPAD_IO_SEL_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8822B) & BIT_MASK_NFCPAD_IO_SEL_8822B) - - +#define BIT_NFCPAD_IO_SEL_8822B(x) \ + (((x) & BIT_MASK_NFCPAD_IO_SEL_8822B) << BIT_SHIFT_NFCPAD_IO_SEL_8822B) +#define BITS_NFCPAD_IO_SEL_8822B \ + (BIT_MASK_NFCPAD_IO_SEL_8822B << BIT_SHIFT_NFCPAD_IO_SEL_8822B) +#define BIT_CLEAR_NFCPAD_IO_SEL_8822B(x) ((x) & (~BITS_NFCPAD_IO_SEL_8822B)) +#define BIT_GET_NFCPAD_IO_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8822B) & BIT_MASK_NFCPAD_IO_SEL_8822B) +#define BIT_SET_NFCPAD_IO_SEL_8822B(x, v) \ + (BIT_CLEAR_NFCPAD_IO_SEL_8822B(x) | BIT_NFCPAD_IO_SEL_8822B(v)) #define BIT_SHIFT_NFCPAD_OUT_8822B 4 #define BIT_MASK_NFCPAD_OUT_8822B 0xf -#define BIT_NFCPAD_OUT_8822B(x) (((x) & BIT_MASK_NFCPAD_OUT_8822B) << BIT_SHIFT_NFCPAD_OUT_8822B) -#define BIT_GET_NFCPAD_OUT_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8822B) & BIT_MASK_NFCPAD_OUT_8822B) - - +#define BIT_NFCPAD_OUT_8822B(x) \ + (((x) & BIT_MASK_NFCPAD_OUT_8822B) << BIT_SHIFT_NFCPAD_OUT_8822B) +#define BITS_NFCPAD_OUT_8822B \ + (BIT_MASK_NFCPAD_OUT_8822B << BIT_SHIFT_NFCPAD_OUT_8822B) +#define BIT_CLEAR_NFCPAD_OUT_8822B(x) ((x) & (~BITS_NFCPAD_OUT_8822B)) +#define BIT_GET_NFCPAD_OUT_8822B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_OUT_8822B) & BIT_MASK_NFCPAD_OUT_8822B) +#define BIT_SET_NFCPAD_OUT_8822B(x, v) \ + (BIT_CLEAR_NFCPAD_OUT_8822B(x) | BIT_NFCPAD_OUT_8822B(v)) #define BIT_SHIFT_NFCPAD_IN_8822B 0 #define BIT_MASK_NFCPAD_IN_8822B 0xf -#define BIT_NFCPAD_IN_8822B(x) (((x) & BIT_MASK_NFCPAD_IN_8822B) << BIT_SHIFT_NFCPAD_IN_8822B) -#define BIT_GET_NFCPAD_IN_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8822B) & BIT_MASK_NFCPAD_IN_8822B) - - +#define BIT_NFCPAD_IN_8822B(x) \ + (((x) & BIT_MASK_NFCPAD_IN_8822B) << BIT_SHIFT_NFCPAD_IN_8822B) +#define BITS_NFCPAD_IN_8822B \ + (BIT_MASK_NFCPAD_IN_8822B << BIT_SHIFT_NFCPAD_IN_8822B) +#define BIT_CLEAR_NFCPAD_IN_8822B(x) ((x) & (~BITS_NFCPAD_IN_8822B)) +#define BIT_GET_NFCPAD_IN_8822B(x) \ + (((x) >> BIT_SHIFT_NFCPAD_IN_8822B) & BIT_MASK_NFCPAD_IN_8822B) +#define BIT_SET_NFCPAD_IN_8822B(x, v) \ + (BIT_CLEAR_NFCPAD_IN_8822B(x) | BIT_NFCPAD_IN_8822B(v)) /* 2 REG_HIMR2_8822B */ #define BIT_BCNDMAINT_P4_MSK_8822B BIT(31) @@ -1947,19 +2814,35 @@ #define BIT_SHIFT_H2C_PKT_READADDR_8822B 0 #define BIT_MASK_H2C_PKT_READADDR_8822B 0x3ffff -#define BIT_H2C_PKT_READADDR_8822B(x) (((x) & BIT_MASK_H2C_PKT_READADDR_8822B) << BIT_SHIFT_H2C_PKT_READADDR_8822B) -#define BIT_GET_H2C_PKT_READADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822B) & BIT_MASK_H2C_PKT_READADDR_8822B) - - +#define BIT_H2C_PKT_READADDR_8822B(x) \ + (((x) & BIT_MASK_H2C_PKT_READADDR_8822B) \ + << BIT_SHIFT_H2C_PKT_READADDR_8822B) +#define BITS_H2C_PKT_READADDR_8822B \ + (BIT_MASK_H2C_PKT_READADDR_8822B << BIT_SHIFT_H2C_PKT_READADDR_8822B) +#define BIT_CLEAR_H2C_PKT_READADDR_8822B(x) \ + ((x) & (~BITS_H2C_PKT_READADDR_8822B)) +#define BIT_GET_H2C_PKT_READADDR_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822B) & \ + BIT_MASK_H2C_PKT_READADDR_8822B) +#define BIT_SET_H2C_PKT_READADDR_8822B(x, v) \ + (BIT_CLEAR_H2C_PKT_READADDR_8822B(x) | BIT_H2C_PKT_READADDR_8822B(v)) /* 2 REG_H2C_PKT_WRITEADDR_8822B */ #define BIT_SHIFT_H2C_PKT_WRITEADDR_8822B 0 #define BIT_MASK_H2C_PKT_WRITEADDR_8822B 0x3ffff -#define BIT_H2C_PKT_WRITEADDR_8822B(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822B) << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) -#define BIT_GET_H2C_PKT_WRITEADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) & BIT_MASK_H2C_PKT_WRITEADDR_8822B) - - +#define BIT_H2C_PKT_WRITEADDR_8822B(x) \ + (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822B) \ + << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) +#define BITS_H2C_PKT_WRITEADDR_8822B \ + (BIT_MASK_H2C_PKT_WRITEADDR_8822B << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) +#define BIT_CLEAR_H2C_PKT_WRITEADDR_8822B(x) \ + ((x) & (~BITS_H2C_PKT_WRITEADDR_8822B)) +#define BIT_GET_H2C_PKT_WRITEADDR_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) & \ + BIT_MASK_H2C_PKT_WRITEADDR_8822B) +#define BIT_SET_H2C_PKT_WRITEADDR_8822B(x, v) \ + (BIT_CLEAR_H2C_PKT_WRITEADDR_8822B(x) | BIT_H2C_PKT_WRITEADDR_8822B(v)) /* 2 REG_MEM_PWR_CRTL_8822B */ #define BIT_MEM_BB_SD_8822B BIT(17) @@ -1980,73 +2863,105 @@ #define BIT_SHIFT_FW_DBG0_8822B 0 #define BIT_MASK_FW_DBG0_8822B 0xffffffffL -#define BIT_FW_DBG0_8822B(x) (((x) & BIT_MASK_FW_DBG0_8822B) << BIT_SHIFT_FW_DBG0_8822B) -#define BIT_GET_FW_DBG0_8822B(x) (((x) >> BIT_SHIFT_FW_DBG0_8822B) & BIT_MASK_FW_DBG0_8822B) - - +#define BIT_FW_DBG0_8822B(x) \ + (((x) & BIT_MASK_FW_DBG0_8822B) << BIT_SHIFT_FW_DBG0_8822B) +#define BITS_FW_DBG0_8822B (BIT_MASK_FW_DBG0_8822B << BIT_SHIFT_FW_DBG0_8822B) +#define BIT_CLEAR_FW_DBG0_8822B(x) ((x) & (~BITS_FW_DBG0_8822B)) +#define BIT_GET_FW_DBG0_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG0_8822B) & BIT_MASK_FW_DBG0_8822B) +#define BIT_SET_FW_DBG0_8822B(x, v) \ + (BIT_CLEAR_FW_DBG0_8822B(x) | BIT_FW_DBG0_8822B(v)) /* 2 REG_FW_DBG1_8822B */ #define BIT_SHIFT_FW_DBG1_8822B 0 #define BIT_MASK_FW_DBG1_8822B 0xffffffffL -#define BIT_FW_DBG1_8822B(x) (((x) & BIT_MASK_FW_DBG1_8822B) << BIT_SHIFT_FW_DBG1_8822B) -#define BIT_GET_FW_DBG1_8822B(x) (((x) >> BIT_SHIFT_FW_DBG1_8822B) & BIT_MASK_FW_DBG1_8822B) - - +#define BIT_FW_DBG1_8822B(x) \ + (((x) & BIT_MASK_FW_DBG1_8822B) << BIT_SHIFT_FW_DBG1_8822B) +#define BITS_FW_DBG1_8822B (BIT_MASK_FW_DBG1_8822B << BIT_SHIFT_FW_DBG1_8822B) +#define BIT_CLEAR_FW_DBG1_8822B(x) ((x) & (~BITS_FW_DBG1_8822B)) +#define BIT_GET_FW_DBG1_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG1_8822B) & BIT_MASK_FW_DBG1_8822B) +#define BIT_SET_FW_DBG1_8822B(x, v) \ + (BIT_CLEAR_FW_DBG1_8822B(x) | BIT_FW_DBG1_8822B(v)) /* 2 REG_FW_DBG2_8822B */ #define BIT_SHIFT_FW_DBG2_8822B 0 #define BIT_MASK_FW_DBG2_8822B 0xffffffffL -#define BIT_FW_DBG2_8822B(x) (((x) & BIT_MASK_FW_DBG2_8822B) << BIT_SHIFT_FW_DBG2_8822B) -#define BIT_GET_FW_DBG2_8822B(x) (((x) >> BIT_SHIFT_FW_DBG2_8822B) & BIT_MASK_FW_DBG2_8822B) +#define BIT_FW_DBG2_8822B(x) \ + (((x) & BIT_MASK_FW_DBG2_8822B) << BIT_SHIFT_FW_DBG2_8822B) +#define BITS_FW_DBG2_8822B (BIT_MASK_FW_DBG2_8822B << BIT_SHIFT_FW_DBG2_8822B) +#define BIT_CLEAR_FW_DBG2_8822B(x) ((x) & (~BITS_FW_DBG2_8822B)) +#define BIT_GET_FW_DBG2_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG2_8822B) & BIT_MASK_FW_DBG2_8822B) +#define BIT_SET_FW_DBG2_8822B(x, v) \ + (BIT_CLEAR_FW_DBG2_8822B(x) | BIT_FW_DBG2_8822B(v)) - - -/* 2 REG_FW_DBG3_8822B */ +/* 2 REG_FW_DBG3_8822B */ #define BIT_SHIFT_FW_DBG3_8822B 0 #define BIT_MASK_FW_DBG3_8822B 0xffffffffL -#define BIT_FW_DBG3_8822B(x) (((x) & BIT_MASK_FW_DBG3_8822B) << BIT_SHIFT_FW_DBG3_8822B) -#define BIT_GET_FW_DBG3_8822B(x) (((x) >> BIT_SHIFT_FW_DBG3_8822B) & BIT_MASK_FW_DBG3_8822B) - - +#define BIT_FW_DBG3_8822B(x) \ + (((x) & BIT_MASK_FW_DBG3_8822B) << BIT_SHIFT_FW_DBG3_8822B) +#define BITS_FW_DBG3_8822B (BIT_MASK_FW_DBG3_8822B << BIT_SHIFT_FW_DBG3_8822B) +#define BIT_CLEAR_FW_DBG3_8822B(x) ((x) & (~BITS_FW_DBG3_8822B)) +#define BIT_GET_FW_DBG3_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG3_8822B) & BIT_MASK_FW_DBG3_8822B) +#define BIT_SET_FW_DBG3_8822B(x, v) \ + (BIT_CLEAR_FW_DBG3_8822B(x) | BIT_FW_DBG3_8822B(v)) /* 2 REG_FW_DBG4_8822B */ #define BIT_SHIFT_FW_DBG4_8822B 0 #define BIT_MASK_FW_DBG4_8822B 0xffffffffL -#define BIT_FW_DBG4_8822B(x) (((x) & BIT_MASK_FW_DBG4_8822B) << BIT_SHIFT_FW_DBG4_8822B) -#define BIT_GET_FW_DBG4_8822B(x) (((x) >> BIT_SHIFT_FW_DBG4_8822B) & BIT_MASK_FW_DBG4_8822B) - - +#define BIT_FW_DBG4_8822B(x) \ + (((x) & BIT_MASK_FW_DBG4_8822B) << BIT_SHIFT_FW_DBG4_8822B) +#define BITS_FW_DBG4_8822B (BIT_MASK_FW_DBG4_8822B << BIT_SHIFT_FW_DBG4_8822B) +#define BIT_CLEAR_FW_DBG4_8822B(x) ((x) & (~BITS_FW_DBG4_8822B)) +#define BIT_GET_FW_DBG4_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG4_8822B) & BIT_MASK_FW_DBG4_8822B) +#define BIT_SET_FW_DBG4_8822B(x, v) \ + (BIT_CLEAR_FW_DBG4_8822B(x) | BIT_FW_DBG4_8822B(v)) /* 2 REG_FW_DBG5_8822B */ #define BIT_SHIFT_FW_DBG5_8822B 0 #define BIT_MASK_FW_DBG5_8822B 0xffffffffL -#define BIT_FW_DBG5_8822B(x) (((x) & BIT_MASK_FW_DBG5_8822B) << BIT_SHIFT_FW_DBG5_8822B) -#define BIT_GET_FW_DBG5_8822B(x) (((x) >> BIT_SHIFT_FW_DBG5_8822B) & BIT_MASK_FW_DBG5_8822B) - - +#define BIT_FW_DBG5_8822B(x) \ + (((x) & BIT_MASK_FW_DBG5_8822B) << BIT_SHIFT_FW_DBG5_8822B) +#define BITS_FW_DBG5_8822B (BIT_MASK_FW_DBG5_8822B << BIT_SHIFT_FW_DBG5_8822B) +#define BIT_CLEAR_FW_DBG5_8822B(x) ((x) & (~BITS_FW_DBG5_8822B)) +#define BIT_GET_FW_DBG5_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG5_8822B) & BIT_MASK_FW_DBG5_8822B) +#define BIT_SET_FW_DBG5_8822B(x, v) \ + (BIT_CLEAR_FW_DBG5_8822B(x) | BIT_FW_DBG5_8822B(v)) /* 2 REG_FW_DBG6_8822B */ #define BIT_SHIFT_FW_DBG6_8822B 0 #define BIT_MASK_FW_DBG6_8822B 0xffffffffL -#define BIT_FW_DBG6_8822B(x) (((x) & BIT_MASK_FW_DBG6_8822B) << BIT_SHIFT_FW_DBG6_8822B) -#define BIT_GET_FW_DBG6_8822B(x) (((x) >> BIT_SHIFT_FW_DBG6_8822B) & BIT_MASK_FW_DBG6_8822B) - - +#define BIT_FW_DBG6_8822B(x) \ + (((x) & BIT_MASK_FW_DBG6_8822B) << BIT_SHIFT_FW_DBG6_8822B) +#define BITS_FW_DBG6_8822B (BIT_MASK_FW_DBG6_8822B << BIT_SHIFT_FW_DBG6_8822B) +#define BIT_CLEAR_FW_DBG6_8822B(x) ((x) & (~BITS_FW_DBG6_8822B)) +#define BIT_GET_FW_DBG6_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG6_8822B) & BIT_MASK_FW_DBG6_8822B) +#define BIT_SET_FW_DBG6_8822B(x, v) \ + (BIT_CLEAR_FW_DBG6_8822B(x) | BIT_FW_DBG6_8822B(v)) /* 2 REG_FW_DBG7_8822B */ #define BIT_SHIFT_FW_DBG7_8822B 0 #define BIT_MASK_FW_DBG7_8822B 0xffffffffL -#define BIT_FW_DBG7_8822B(x) (((x) & BIT_MASK_FW_DBG7_8822B) << BIT_SHIFT_FW_DBG7_8822B) -#define BIT_GET_FW_DBG7_8822B(x) (((x) >> BIT_SHIFT_FW_DBG7_8822B) & BIT_MASK_FW_DBG7_8822B) - - +#define BIT_FW_DBG7_8822B(x) \ + (((x) & BIT_MASK_FW_DBG7_8822B) << BIT_SHIFT_FW_DBG7_8822B) +#define BITS_FW_DBG7_8822B (BIT_MASK_FW_DBG7_8822B << BIT_SHIFT_FW_DBG7_8822B) +#define BIT_CLEAR_FW_DBG7_8822B(x) ((x) & (~BITS_FW_DBG7_8822B)) +#define BIT_GET_FW_DBG7_8822B(x) \ + (((x) >> BIT_SHIFT_FW_DBG7_8822B) & BIT_MASK_FW_DBG7_8822B) +#define BIT_SET_FW_DBG7_8822B(x, v) \ + (BIT_CLEAR_FW_DBG7_8822B(x) | BIT_FW_DBG7_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -2054,23 +2969,36 @@ #define BIT_SHIFT_LBMODE_8822B 24 #define BIT_MASK_LBMODE_8822B 0x1f -#define BIT_LBMODE_8822B(x) (((x) & BIT_MASK_LBMODE_8822B) << BIT_SHIFT_LBMODE_8822B) -#define BIT_GET_LBMODE_8822B(x) (((x) >> BIT_SHIFT_LBMODE_8822B) & BIT_MASK_LBMODE_8822B) - - +#define BIT_LBMODE_8822B(x) \ + (((x) & BIT_MASK_LBMODE_8822B) << BIT_SHIFT_LBMODE_8822B) +#define BITS_LBMODE_8822B (BIT_MASK_LBMODE_8822B << BIT_SHIFT_LBMODE_8822B) +#define BIT_CLEAR_LBMODE_8822B(x) ((x) & (~BITS_LBMODE_8822B)) +#define BIT_GET_LBMODE_8822B(x) \ + (((x) >> BIT_SHIFT_LBMODE_8822B) & BIT_MASK_LBMODE_8822B) +#define BIT_SET_LBMODE_8822B(x, v) \ + (BIT_CLEAR_LBMODE_8822B(x) | BIT_LBMODE_8822B(v)) #define BIT_SHIFT_NETYPE1_8822B 18 #define BIT_MASK_NETYPE1_8822B 0x3 -#define BIT_NETYPE1_8822B(x) (((x) & BIT_MASK_NETYPE1_8822B) << BIT_SHIFT_NETYPE1_8822B) -#define BIT_GET_NETYPE1_8822B(x) (((x) >> BIT_SHIFT_NETYPE1_8822B) & BIT_MASK_NETYPE1_8822B) - - +#define BIT_NETYPE1_8822B(x) \ + (((x) & BIT_MASK_NETYPE1_8822B) << BIT_SHIFT_NETYPE1_8822B) +#define BITS_NETYPE1_8822B (BIT_MASK_NETYPE1_8822B << BIT_SHIFT_NETYPE1_8822B) +#define BIT_CLEAR_NETYPE1_8822B(x) ((x) & (~BITS_NETYPE1_8822B)) +#define BIT_GET_NETYPE1_8822B(x) \ + (((x) >> BIT_SHIFT_NETYPE1_8822B) & BIT_MASK_NETYPE1_8822B) +#define BIT_SET_NETYPE1_8822B(x, v) \ + (BIT_CLEAR_NETYPE1_8822B(x) | BIT_NETYPE1_8822B(v)) #define BIT_SHIFT_NETYPE0_8822B 16 #define BIT_MASK_NETYPE0_8822B 0x3 -#define BIT_NETYPE0_8822B(x) (((x) & BIT_MASK_NETYPE0_8822B) << BIT_SHIFT_NETYPE0_8822B) -#define BIT_GET_NETYPE0_8822B(x) (((x) >> BIT_SHIFT_NETYPE0_8822B) & BIT_MASK_NETYPE0_8822B) - +#define BIT_NETYPE0_8822B(x) \ + (((x) & BIT_MASK_NETYPE0_8822B) << BIT_SHIFT_NETYPE0_8822B) +#define BITS_NETYPE0_8822B (BIT_MASK_NETYPE0_8822B << BIT_SHIFT_NETYPE0_8822B) +#define BIT_CLEAR_NETYPE0_8822B(x) ((x) & (~BITS_NETYPE0_8822B)) +#define BIT_GET_NETYPE0_8822B(x) \ + (((x) >> BIT_SHIFT_NETYPE0_8822B) & BIT_MASK_NETYPE0_8822B) +#define BIT_SET_NETYPE0_8822B(x, v) \ + (BIT_CLEAR_NETYPE0_8822B(x) | BIT_NETYPE0_8822B(v)) #define BIT_I2C_MAILBOX_EN_8822B BIT(12) #define BIT_SHCUT_EN_8822B BIT(11) @@ -2086,15 +3014,6 @@ #define BIT_HCI_RXDMA_EN_8822B BIT(1) #define BIT_HCI_TXDMA_EN_8822B BIT(0) -/* 2 REG_PKT_BUFF_ACCESS_CTRL_8822B */ - -#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B 0 -#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B 0xff -#define BIT_PKT_BUFF_ACCESS_CTRL_8822B(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B) -#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8822B(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822B) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822B) - - - /* 2 REG_TSF_CLK_STATE_8822B */ #define BIT_TSF_CLK_STABLE_8822B BIT(15) @@ -2102,44 +3021,75 @@ #define BIT_SHIFT_TXDMA_HIQ_MAP_8822B 14 #define BIT_MASK_TXDMA_HIQ_MAP_8822B 0x3 -#define BIT_TXDMA_HIQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8822B) << BIT_SHIFT_TXDMA_HIQ_MAP_8822B) -#define BIT_GET_TXDMA_HIQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822B) & BIT_MASK_TXDMA_HIQ_MAP_8822B) - - +#define BIT_TXDMA_HIQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_8822B) << BIT_SHIFT_TXDMA_HIQ_MAP_8822B) +#define BITS_TXDMA_HIQ_MAP_8822B \ + (BIT_MASK_TXDMA_HIQ_MAP_8822B << BIT_SHIFT_TXDMA_HIQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_HIQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8822B)) +#define BIT_GET_TXDMA_HIQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822B) & BIT_MASK_TXDMA_HIQ_MAP_8822B) +#define BIT_SET_TXDMA_HIQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_8822B(x) | BIT_TXDMA_HIQ_MAP_8822B(v)) #define BIT_SHIFT_TXDMA_MGQ_MAP_8822B 12 #define BIT_MASK_TXDMA_MGQ_MAP_8822B 0x3 -#define BIT_TXDMA_MGQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8822B) << BIT_SHIFT_TXDMA_MGQ_MAP_8822B) -#define BIT_GET_TXDMA_MGQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822B) & BIT_MASK_TXDMA_MGQ_MAP_8822B) - - +#define BIT_TXDMA_MGQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_8822B) << BIT_SHIFT_TXDMA_MGQ_MAP_8822B) +#define BITS_TXDMA_MGQ_MAP_8822B \ + (BIT_MASK_TXDMA_MGQ_MAP_8822B << BIT_SHIFT_TXDMA_MGQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_MGQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8822B)) +#define BIT_GET_TXDMA_MGQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822B) & BIT_MASK_TXDMA_MGQ_MAP_8822B) +#define BIT_SET_TXDMA_MGQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_8822B(x) | BIT_TXDMA_MGQ_MAP_8822B(v)) #define BIT_SHIFT_TXDMA_BKQ_MAP_8822B 10 #define BIT_MASK_TXDMA_BKQ_MAP_8822B 0x3 -#define BIT_TXDMA_BKQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8822B) << BIT_SHIFT_TXDMA_BKQ_MAP_8822B) -#define BIT_GET_TXDMA_BKQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822B) & BIT_MASK_TXDMA_BKQ_MAP_8822B) - - +#define BIT_TXDMA_BKQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_8822B) << BIT_SHIFT_TXDMA_BKQ_MAP_8822B) +#define BITS_TXDMA_BKQ_MAP_8822B \ + (BIT_MASK_TXDMA_BKQ_MAP_8822B << BIT_SHIFT_TXDMA_BKQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_BKQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8822B)) +#define BIT_GET_TXDMA_BKQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822B) & BIT_MASK_TXDMA_BKQ_MAP_8822B) +#define BIT_SET_TXDMA_BKQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_8822B(x) | BIT_TXDMA_BKQ_MAP_8822B(v)) #define BIT_SHIFT_TXDMA_BEQ_MAP_8822B 8 #define BIT_MASK_TXDMA_BEQ_MAP_8822B 0x3 -#define BIT_TXDMA_BEQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8822B) << BIT_SHIFT_TXDMA_BEQ_MAP_8822B) -#define BIT_GET_TXDMA_BEQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822B) & BIT_MASK_TXDMA_BEQ_MAP_8822B) - - +#define BIT_TXDMA_BEQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_8822B) << BIT_SHIFT_TXDMA_BEQ_MAP_8822B) +#define BITS_TXDMA_BEQ_MAP_8822B \ + (BIT_MASK_TXDMA_BEQ_MAP_8822B << BIT_SHIFT_TXDMA_BEQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_BEQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8822B)) +#define BIT_GET_TXDMA_BEQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822B) & BIT_MASK_TXDMA_BEQ_MAP_8822B) +#define BIT_SET_TXDMA_BEQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_8822B(x) | BIT_TXDMA_BEQ_MAP_8822B(v)) #define BIT_SHIFT_TXDMA_VIQ_MAP_8822B 6 #define BIT_MASK_TXDMA_VIQ_MAP_8822B 0x3 -#define BIT_TXDMA_VIQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8822B) << BIT_SHIFT_TXDMA_VIQ_MAP_8822B) -#define BIT_GET_TXDMA_VIQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822B) & BIT_MASK_TXDMA_VIQ_MAP_8822B) - - +#define BIT_TXDMA_VIQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_8822B) << BIT_SHIFT_TXDMA_VIQ_MAP_8822B) +#define BITS_TXDMA_VIQ_MAP_8822B \ + (BIT_MASK_TXDMA_VIQ_MAP_8822B << BIT_SHIFT_TXDMA_VIQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_VIQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8822B)) +#define BIT_GET_TXDMA_VIQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822B) & BIT_MASK_TXDMA_VIQ_MAP_8822B) +#define BIT_SET_TXDMA_VIQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_8822B(x) | BIT_TXDMA_VIQ_MAP_8822B(v)) #define BIT_SHIFT_TXDMA_VOQ_MAP_8822B 4 #define BIT_MASK_TXDMA_VOQ_MAP_8822B 0x3 -#define BIT_TXDMA_VOQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8822B) << BIT_SHIFT_TXDMA_VOQ_MAP_8822B) -#define BIT_GET_TXDMA_VOQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822B) & BIT_MASK_TXDMA_VOQ_MAP_8822B) - +#define BIT_TXDMA_VOQ_MAP_8822B(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_8822B) << BIT_SHIFT_TXDMA_VOQ_MAP_8822B) +#define BITS_TXDMA_VOQ_MAP_8822B \ + (BIT_MASK_TXDMA_VOQ_MAP_8822B << BIT_SHIFT_TXDMA_VOQ_MAP_8822B) +#define BIT_CLEAR_TXDMA_VOQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8822B)) +#define BIT_GET_TXDMA_VOQ_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822B) & BIT_MASK_TXDMA_VOQ_MAP_8822B) +#define BIT_SET_TXDMA_VOQ_MAP_8822B(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_8822B(x) | BIT_TXDMA_VOQ_MAP_8822B(v)) #define BIT_RXDMA_AGG_EN_8822B BIT(2) #define BIT_RXSHFT_EN_8822B BIT(1) @@ -2149,17 +3099,31 @@ #define BIT_SHIFT_RXFFOVFL_RSV_V2_8822B 8 #define BIT_MASK_RXFFOVFL_RSV_V2_8822B 0xf -#define BIT_RXFFOVFL_RSV_V2_8822B(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822B) << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) -#define BIT_GET_RXFFOVFL_RSV_V2_8822B(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) & BIT_MASK_RXFFOVFL_RSV_V2_8822B) - - +#define BIT_RXFFOVFL_RSV_V2_8822B(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822B) \ + << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) +#define BITS_RXFFOVFL_RSV_V2_8822B \ + (BIT_MASK_RXFFOVFL_RSV_V2_8822B << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) +#define BIT_CLEAR_RXFFOVFL_RSV_V2_8822B(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8822B)) +#define BIT_GET_RXFFOVFL_RSV_V2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) & \ + BIT_MASK_RXFFOVFL_RSV_V2_8822B) +#define BIT_SET_RXFFOVFL_RSV_V2_8822B(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2_8822B(x) | BIT_RXFFOVFL_RSV_V2_8822B(v)) #define BIT_SHIFT_TXPKTBUF_PGBNDY_8822B 0 #define BIT_MASK_TXPKTBUF_PGBNDY_8822B 0xff -#define BIT_TXPKTBUF_PGBNDY_8822B(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8822B) << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) -#define BIT_GET_TXPKTBUF_PGBNDY_8822B(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) & BIT_MASK_TXPKTBUF_PGBNDY_8822B) - - +#define BIT_TXPKTBUF_PGBNDY_8822B(x) \ + (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8822B) \ + << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) +#define BITS_TXPKTBUF_PGBNDY_8822B \ + (BIT_MASK_TXPKTBUF_PGBNDY_8822B << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) +#define BIT_CLEAR_TXPKTBUF_PGBNDY_8822B(x) ((x) & (~BITS_TXPKTBUF_PGBNDY_8822B)) +#define BIT_GET_TXPKTBUF_PGBNDY_8822B(x) \ + (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) & \ + BIT_MASK_TXPKTBUF_PGBNDY_8822B) +#define BIT_SET_TXPKTBUF_PGBNDY_8822B(x, v) \ + (BIT_CLEAR_TXPKTBUF_PGBNDY_8822B(x) | BIT_TXPKTBUF_PGBNDY_8822B(v)) /* 2 REG_PTA_I2C_MBOX_8822B */ @@ -2167,24 +3131,44 @@ #define BIT_SHIFT_I2C_M_STATUS_8822B 8 #define BIT_MASK_I2C_M_STATUS_8822B 0xf -#define BIT_I2C_M_STATUS_8822B(x) (((x) & BIT_MASK_I2C_M_STATUS_8822B) << BIT_SHIFT_I2C_M_STATUS_8822B) -#define BIT_GET_I2C_M_STATUS_8822B(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8822B) & BIT_MASK_I2C_M_STATUS_8822B) - - +#define BIT_I2C_M_STATUS_8822B(x) \ + (((x) & BIT_MASK_I2C_M_STATUS_8822B) << BIT_SHIFT_I2C_M_STATUS_8822B) +#define BITS_I2C_M_STATUS_8822B \ + (BIT_MASK_I2C_M_STATUS_8822B << BIT_SHIFT_I2C_M_STATUS_8822B) +#define BIT_CLEAR_I2C_M_STATUS_8822B(x) ((x) & (~BITS_I2C_M_STATUS_8822B)) +#define BIT_GET_I2C_M_STATUS_8822B(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS_8822B) & BIT_MASK_I2C_M_STATUS_8822B) +#define BIT_SET_I2C_M_STATUS_8822B(x, v) \ + (BIT_CLEAR_I2C_M_STATUS_8822B(x) | BIT_I2C_M_STATUS_8822B(v)) #define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B 4 #define BIT_MASK_I2C_M_BUS_GNT_FW_8822B 0x7 -#define BIT_I2C_M_BUS_GNT_FW_8822B(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) -#define BIT_GET_I2C_M_BUS_GNT_FW_8822B(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B) - +#define BIT_I2C_M_BUS_GNT_FW_8822B(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B) \ + << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) +#define BITS_I2C_M_BUS_GNT_FW_8822B \ + (BIT_MASK_I2C_M_BUS_GNT_FW_8822B << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8822B(x) \ + ((x) & (~BITS_I2C_M_BUS_GNT_FW_8822B)) +#define BIT_GET_I2C_M_BUS_GNT_FW_8822B(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) & \ + BIT_MASK_I2C_M_BUS_GNT_FW_8822B) +#define BIT_SET_I2C_M_BUS_GNT_FW_8822B(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW_8822B(x) | BIT_I2C_M_BUS_GNT_FW_8822B(v)) #define BIT_I2C_M_GNT_FW_8822B BIT(3) #define BIT_SHIFT_I2C_M_SPEED_8822B 1 #define BIT_MASK_I2C_M_SPEED_8822B 0x3 -#define BIT_I2C_M_SPEED_8822B(x) (((x) & BIT_MASK_I2C_M_SPEED_8822B) << BIT_SHIFT_I2C_M_SPEED_8822B) -#define BIT_GET_I2C_M_SPEED_8822B(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8822B) & BIT_MASK_I2C_M_SPEED_8822B) - +#define BIT_I2C_M_SPEED_8822B(x) \ + (((x) & BIT_MASK_I2C_M_SPEED_8822B) << BIT_SHIFT_I2C_M_SPEED_8822B) +#define BITS_I2C_M_SPEED_8822B \ + (BIT_MASK_I2C_M_SPEED_8822B << BIT_SHIFT_I2C_M_SPEED_8822B) +#define BIT_CLEAR_I2C_M_SPEED_8822B(x) ((x) & (~BITS_I2C_M_SPEED_8822B)) +#define BIT_GET_I2C_M_SPEED_8822B(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED_8822B) & BIT_MASK_I2C_M_SPEED_8822B) +#define BIT_SET_I2C_M_SPEED_8822B(x, v) \ + (BIT_CLEAR_I2C_M_SPEED_8822B(x) | BIT_I2C_M_SPEED_8822B(v)) #define BIT_I2C_M_UNLOCK_8822B BIT(0) @@ -2194,10 +3178,15 @@ #define BIT_SHIFT_RXFF0_BNDY_V2_8822B 0 #define BIT_MASK_RXFF0_BNDY_V2_8822B 0x3ffff -#define BIT_RXFF0_BNDY_V2_8822B(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8822B) << BIT_SHIFT_RXFF0_BNDY_V2_8822B) -#define BIT_GET_RXFF0_BNDY_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822B) & BIT_MASK_RXFF0_BNDY_V2_8822B) - - +#define BIT_RXFF0_BNDY_V2_8822B(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2_8822B) << BIT_SHIFT_RXFF0_BNDY_V2_8822B) +#define BITS_RXFF0_BNDY_V2_8822B \ + (BIT_MASK_RXFF0_BNDY_V2_8822B << BIT_SHIFT_RXFF0_BNDY_V2_8822B) +#define BIT_CLEAR_RXFF0_BNDY_V2_8822B(x) ((x) & (~BITS_RXFF0_BNDY_V2_8822B)) +#define BIT_GET_RXFF0_BNDY_V2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822B) & BIT_MASK_RXFF0_BNDY_V2_8822B) +#define BIT_SET_RXFF0_BNDY_V2_8822B(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2_8822B(x) | BIT_RXFF0_BNDY_V2_8822B(v)) /* 2 REG_FE1IMR_8822B */ #define BIT_FS_RXDMA2_DONE_INT_EN_8822B BIT(28) @@ -2264,10 +3253,15 @@ #define BIT_SHIFT_CPWM_MOD_8822B 24 #define BIT_MASK_CPWM_MOD_8822B 0x7f -#define BIT_CPWM_MOD_8822B(x) (((x) & BIT_MASK_CPWM_MOD_8822B) << BIT_SHIFT_CPWM_MOD_8822B) -#define BIT_GET_CPWM_MOD_8822B(x) (((x) >> BIT_SHIFT_CPWM_MOD_8822B) & BIT_MASK_CPWM_MOD_8822B) - - +#define BIT_CPWM_MOD_8822B(x) \ + (((x) & BIT_MASK_CPWM_MOD_8822B) << BIT_SHIFT_CPWM_MOD_8822B) +#define BITS_CPWM_MOD_8822B \ + (BIT_MASK_CPWM_MOD_8822B << BIT_SHIFT_CPWM_MOD_8822B) +#define BIT_CLEAR_CPWM_MOD_8822B(x) ((x) & (~BITS_CPWM_MOD_8822B)) +#define BIT_GET_CPWM_MOD_8822B(x) \ + (((x) >> BIT_SHIFT_CPWM_MOD_8822B) & BIT_MASK_CPWM_MOD_8822B) +#define BIT_SET_CPWM_MOD_8822B(x, v) \ + (BIT_CLEAR_CPWM_MOD_8822B(x) | BIT_CPWM_MOD_8822B(v)) /* 2 REG_FWIMR_8822B */ #define BIT_FS_TXBCNOK_MB7_INT_EN_8822B BIT(31) @@ -2290,8 +3284,7 @@ #define BIT_SIFS_OVERSPEC_INT_EN_8822B BIT(14) #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8822B BIT(13) #define BIT_FS_MGNTQFF_TO_INT_EN_8822B BIT(12) -#define BIT_FS_DDMA1_LP_INT_EN_8822B BIT(11) -#define BIT_FS_DDMA1_HP_INT_EN_8822B BIT(10) +#define BIT_FS_CPUMGQ_ERR_INT_EN_8822B BIT(11) #define BIT_FS_DDMA0_LP_INT_EN_8822B BIT(9) #define BIT_FS_DDMA0_HP_INT_EN_8822B BIT(8) #define BIT_FS_TRXRPT_INT_EN_8822B BIT(7) @@ -2324,8 +3317,7 @@ #define BIT_SIFS_OVERSPEC_INT_8822B BIT(14) #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8822B BIT(13) #define BIT_FS_MGNTQFF_TO_INT_8822B BIT(12) -#define BIT_FS_DDMA1_LP_INT_8822B BIT(11) -#define BIT_FS_DDMA1_HP_INT_8822B BIT(10) +#define BIT_FS_CPUMGQ_ERR_INT_8822B BIT(11) #define BIT_FS_DDMA0_LP_INT_8822B BIT(9) #define BIT_FS_DDMA0_HP_INT_8822B BIT(8) #define BIT_FS_TRXRPT_INT_8822B BIT(7) @@ -2385,9 +3377,17 @@ #define BIT_SHIFT_PKTBUF_WRITE_EN_8822B 24 #define BIT_MASK_PKTBUF_WRITE_EN_8822B 0xff -#define BIT_PKTBUF_WRITE_EN_8822B(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8822B) << BIT_SHIFT_PKTBUF_WRITE_EN_8822B) -#define BIT_GET_PKTBUF_WRITE_EN_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822B) & BIT_MASK_PKTBUF_WRITE_EN_8822B) - +#define BIT_PKTBUF_WRITE_EN_8822B(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN_8822B) \ + << BIT_SHIFT_PKTBUF_WRITE_EN_8822B) +#define BITS_PKTBUF_WRITE_EN_8822B \ + (BIT_MASK_PKTBUF_WRITE_EN_8822B << BIT_SHIFT_PKTBUF_WRITE_EN_8822B) +#define BIT_CLEAR_PKTBUF_WRITE_EN_8822B(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8822B)) +#define BIT_GET_PKTBUF_WRITE_EN_8822B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822B) & \ + BIT_MASK_PKTBUF_WRITE_EN_8822B) +#define BIT_SET_PKTBUF_WRITE_EN_8822B(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN_8822B(x) | BIT_PKTBUF_WRITE_EN_8822B(v)) #define BIT_TXRPTBUF_DBG_8822B BIT(23) @@ -2397,45 +3397,81 @@ #define BIT_SHIFT_PKTBUF_DBG_ADDR_8822B 0 #define BIT_MASK_PKTBUF_DBG_ADDR_8822B 0x1fff -#define BIT_PKTBUF_DBG_ADDR_8822B(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822B) << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) -#define BIT_GET_PKTBUF_DBG_ADDR_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) & BIT_MASK_PKTBUF_DBG_ADDR_8822B) - - +#define BIT_PKTBUF_DBG_ADDR_8822B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822B) \ + << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) +#define BITS_PKTBUF_DBG_ADDR_8822B \ + (BIT_MASK_PKTBUF_DBG_ADDR_8822B << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) +#define BIT_CLEAR_PKTBUF_DBG_ADDR_8822B(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8822B)) +#define BIT_GET_PKTBUF_DBG_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) & \ + BIT_MASK_PKTBUF_DBG_ADDR_8822B) +#define BIT_SET_PKTBUF_DBG_ADDR_8822B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR_8822B(x) | BIT_PKTBUF_DBG_ADDR_8822B(v)) /* 2 REG_PKTBUF_DBG_DATA_L_8822B */ #define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B 0 #define BIT_MASK_PKTBUF_DBG_DATA_L_8822B 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_L_8822B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) -#define BIT_GET_PKTBUF_DBG_DATA_L_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B) - - +#define BIT_PKTBUF_DBG_DATA_L_8822B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) +#define BITS_PKTBUF_DBG_DATA_L_8822B \ + (BIT_MASK_PKTBUF_DBG_DATA_L_8822B << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8822B(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_L_8822B)) +#define BIT_GET_PKTBUF_DBG_DATA_L_8822B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) & \ + BIT_MASK_PKTBUF_DBG_DATA_L_8822B) +#define BIT_SET_PKTBUF_DBG_DATA_L_8822B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L_8822B(x) | BIT_PKTBUF_DBG_DATA_L_8822B(v)) /* 2 REG_PKTBUF_DBG_DATA_H_8822B */ #define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B 0 #define BIT_MASK_PKTBUF_DBG_DATA_H_8822B 0xffffffffL -#define BIT_PKTBUF_DBG_DATA_H_8822B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) -#define BIT_GET_PKTBUF_DBG_DATA_H_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B) - - +#define BIT_PKTBUF_DBG_DATA_H_8822B(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) +#define BITS_PKTBUF_DBG_DATA_H_8822B \ + (BIT_MASK_PKTBUF_DBG_DATA_H_8822B << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8822B(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_H_8822B)) +#define BIT_GET_PKTBUF_DBG_DATA_H_8822B(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) & \ + BIT_MASK_PKTBUF_DBG_DATA_H_8822B) +#define BIT_SET_PKTBUF_DBG_DATA_H_8822B(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H_8822B(x) | BIT_PKTBUF_DBG_DATA_H_8822B(v)) /* 2 REG_CPWM2_8822B */ #define BIT_SHIFT_L0S_TO_RCVY_NUM_8822B 16 #define BIT_MASK_L0S_TO_RCVY_NUM_8822B 0xff -#define BIT_L0S_TO_RCVY_NUM_8822B(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822B) << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) -#define BIT_GET_L0S_TO_RCVY_NUM_8822B(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) & BIT_MASK_L0S_TO_RCVY_NUM_8822B) - +#define BIT_L0S_TO_RCVY_NUM_8822B(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822B) \ + << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) +#define BITS_L0S_TO_RCVY_NUM_8822B \ + (BIT_MASK_L0S_TO_RCVY_NUM_8822B << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) +#define BIT_CLEAR_L0S_TO_RCVY_NUM_8822B(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8822B)) +#define BIT_GET_L0S_TO_RCVY_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) & \ + BIT_MASK_L0S_TO_RCVY_NUM_8822B) +#define BIT_SET_L0S_TO_RCVY_NUM_8822B(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM_8822B(x) | BIT_L0S_TO_RCVY_NUM_8822B(v)) #define BIT_CPWM2_TOGGLING_8822B BIT(15) #define BIT_SHIFT_CPWM2_MOD_8822B 0 #define BIT_MASK_CPWM2_MOD_8822B 0x7fff -#define BIT_CPWM2_MOD_8822B(x) (((x) & BIT_MASK_CPWM2_MOD_8822B) << BIT_SHIFT_CPWM2_MOD_8822B) -#define BIT_GET_CPWM2_MOD_8822B(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8822B) & BIT_MASK_CPWM2_MOD_8822B) - - +#define BIT_CPWM2_MOD_8822B(x) \ + (((x) & BIT_MASK_CPWM2_MOD_8822B) << BIT_SHIFT_CPWM2_MOD_8822B) +#define BITS_CPWM2_MOD_8822B \ + (BIT_MASK_CPWM2_MOD_8822B << BIT_SHIFT_CPWM2_MOD_8822B) +#define BIT_CLEAR_CPWM2_MOD_8822B(x) ((x) & (~BITS_CPWM2_MOD_8822B)) +#define BIT_GET_CPWM2_MOD_8822B(x) \ + (((x) >> BIT_SHIFT_CPWM2_MOD_8822B) & BIT_MASK_CPWM2_MOD_8822B) +#define BIT_SET_CPWM2_MOD_8822B(x, v) \ + (BIT_CLEAR_CPWM2_MOD_8822B(x) | BIT_CPWM2_MOD_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -2446,10 +3482,14 @@ #define BIT_SHIFT_TC0DATA_8822B 0 #define BIT_MASK_TC0DATA_8822B 0xffffff -#define BIT_TC0DATA_8822B(x) (((x) & BIT_MASK_TC0DATA_8822B) << BIT_SHIFT_TC0DATA_8822B) -#define BIT_GET_TC0DATA_8822B(x) (((x) >> BIT_SHIFT_TC0DATA_8822B) & BIT_MASK_TC0DATA_8822B) - - +#define BIT_TC0DATA_8822B(x) \ + (((x) & BIT_MASK_TC0DATA_8822B) << BIT_SHIFT_TC0DATA_8822B) +#define BITS_TC0DATA_8822B (BIT_MASK_TC0DATA_8822B << BIT_SHIFT_TC0DATA_8822B) +#define BIT_CLEAR_TC0DATA_8822B(x) ((x) & (~BITS_TC0DATA_8822B)) +#define BIT_GET_TC0DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC0DATA_8822B) & BIT_MASK_TC0DATA_8822B) +#define BIT_SET_TC0DATA_8822B(x, v) \ + (BIT_CLEAR_TC0DATA_8822B(x) | BIT_TC0DATA_8822B(v)) /* 2 REG_TC1_CTRL_8822B */ #define BIT_TC1INT_EN_8822B BIT(26) @@ -2458,10 +3498,14 @@ #define BIT_SHIFT_TC1DATA_8822B 0 #define BIT_MASK_TC1DATA_8822B 0xffffff -#define BIT_TC1DATA_8822B(x) (((x) & BIT_MASK_TC1DATA_8822B) << BIT_SHIFT_TC1DATA_8822B) -#define BIT_GET_TC1DATA_8822B(x) (((x) >> BIT_SHIFT_TC1DATA_8822B) & BIT_MASK_TC1DATA_8822B) - - +#define BIT_TC1DATA_8822B(x) \ + (((x) & BIT_MASK_TC1DATA_8822B) << BIT_SHIFT_TC1DATA_8822B) +#define BITS_TC1DATA_8822B (BIT_MASK_TC1DATA_8822B << BIT_SHIFT_TC1DATA_8822B) +#define BIT_CLEAR_TC1DATA_8822B(x) ((x) & (~BITS_TC1DATA_8822B)) +#define BIT_GET_TC1DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC1DATA_8822B) & BIT_MASK_TC1DATA_8822B) +#define BIT_SET_TC1DATA_8822B(x, v) \ + (BIT_CLEAR_TC1DATA_8822B(x) | BIT_TC1DATA_8822B(v)) /* 2 REG_TC2_CTRL_8822B */ #define BIT_TC2INT_EN_8822B BIT(26) @@ -2470,10 +3514,14 @@ #define BIT_SHIFT_TC2DATA_8822B 0 #define BIT_MASK_TC2DATA_8822B 0xffffff -#define BIT_TC2DATA_8822B(x) (((x) & BIT_MASK_TC2DATA_8822B) << BIT_SHIFT_TC2DATA_8822B) -#define BIT_GET_TC2DATA_8822B(x) (((x) >> BIT_SHIFT_TC2DATA_8822B) & BIT_MASK_TC2DATA_8822B) - - +#define BIT_TC2DATA_8822B(x) \ + (((x) & BIT_MASK_TC2DATA_8822B) << BIT_SHIFT_TC2DATA_8822B) +#define BITS_TC2DATA_8822B (BIT_MASK_TC2DATA_8822B << BIT_SHIFT_TC2DATA_8822B) +#define BIT_CLEAR_TC2DATA_8822B(x) ((x) & (~BITS_TC2DATA_8822B)) +#define BIT_GET_TC2DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC2DATA_8822B) & BIT_MASK_TC2DATA_8822B) +#define BIT_SET_TC2DATA_8822B(x, v) \ + (BIT_CLEAR_TC2DATA_8822B(x) | BIT_TC2DATA_8822B(v)) /* 2 REG_TC3_CTRL_8822B */ #define BIT_TC3INT_EN_8822B BIT(26) @@ -2482,10 +3530,14 @@ #define BIT_SHIFT_TC3DATA_8822B 0 #define BIT_MASK_TC3DATA_8822B 0xffffff -#define BIT_TC3DATA_8822B(x) (((x) & BIT_MASK_TC3DATA_8822B) << BIT_SHIFT_TC3DATA_8822B) -#define BIT_GET_TC3DATA_8822B(x) (((x) >> BIT_SHIFT_TC3DATA_8822B) & BIT_MASK_TC3DATA_8822B) - - +#define BIT_TC3DATA_8822B(x) \ + (((x) & BIT_MASK_TC3DATA_8822B) << BIT_SHIFT_TC3DATA_8822B) +#define BITS_TC3DATA_8822B (BIT_MASK_TC3DATA_8822B << BIT_SHIFT_TC3DATA_8822B) +#define BIT_CLEAR_TC3DATA_8822B(x) ((x) & (~BITS_TC3DATA_8822B)) +#define BIT_GET_TC3DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC3DATA_8822B) & BIT_MASK_TC3DATA_8822B) +#define BIT_SET_TC3DATA_8822B(x, v) \ + (BIT_CLEAR_TC3DATA_8822B(x) | BIT_TC3DATA_8822B(v)) /* 2 REG_TC4_CTRL_8822B */ #define BIT_TC4INT_EN_8822B BIT(26) @@ -2494,19 +3546,28 @@ #define BIT_SHIFT_TC4DATA_8822B 0 #define BIT_MASK_TC4DATA_8822B 0xffffff -#define BIT_TC4DATA_8822B(x) (((x) & BIT_MASK_TC4DATA_8822B) << BIT_SHIFT_TC4DATA_8822B) -#define BIT_GET_TC4DATA_8822B(x) (((x) >> BIT_SHIFT_TC4DATA_8822B) & BIT_MASK_TC4DATA_8822B) - - +#define BIT_TC4DATA_8822B(x) \ + (((x) & BIT_MASK_TC4DATA_8822B) << BIT_SHIFT_TC4DATA_8822B) +#define BITS_TC4DATA_8822B (BIT_MASK_TC4DATA_8822B << BIT_SHIFT_TC4DATA_8822B) +#define BIT_CLEAR_TC4DATA_8822B(x) ((x) & (~BITS_TC4DATA_8822B)) +#define BIT_GET_TC4DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC4DATA_8822B) & BIT_MASK_TC4DATA_8822B) +#define BIT_SET_TC4DATA_8822B(x, v) \ + (BIT_CLEAR_TC4DATA_8822B(x) | BIT_TC4DATA_8822B(v)) /* 2 REG_TCUNIT_BASE_8822B */ #define BIT_SHIFT_TCUNIT_BASE_8822B 0 #define BIT_MASK_TCUNIT_BASE_8822B 0x3fff -#define BIT_TCUNIT_BASE_8822B(x) (((x) & BIT_MASK_TCUNIT_BASE_8822B) << BIT_SHIFT_TCUNIT_BASE_8822B) -#define BIT_GET_TCUNIT_BASE_8822B(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8822B) & BIT_MASK_TCUNIT_BASE_8822B) - - +#define BIT_TCUNIT_BASE_8822B(x) \ + (((x) & BIT_MASK_TCUNIT_BASE_8822B) << BIT_SHIFT_TCUNIT_BASE_8822B) +#define BITS_TCUNIT_BASE_8822B \ + (BIT_MASK_TCUNIT_BASE_8822B << BIT_SHIFT_TCUNIT_BASE_8822B) +#define BIT_CLEAR_TCUNIT_BASE_8822B(x) ((x) & (~BITS_TCUNIT_BASE_8822B)) +#define BIT_GET_TCUNIT_BASE_8822B(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE_8822B) & BIT_MASK_TCUNIT_BASE_8822B) +#define BIT_SET_TCUNIT_BASE_8822B(x, v) \ + (BIT_CLEAR_TCUNIT_BASE_8822B(x) | BIT_TCUNIT_BASE_8822B(v)) /* 2 REG_TC5_CTRL_8822B */ #define BIT_TC5INT_EN_8822B BIT(26) @@ -2515,10 +3576,14 @@ #define BIT_SHIFT_TC5DATA_8822B 0 #define BIT_MASK_TC5DATA_8822B 0xffffff -#define BIT_TC5DATA_8822B(x) (((x) & BIT_MASK_TC5DATA_8822B) << BIT_SHIFT_TC5DATA_8822B) -#define BIT_GET_TC5DATA_8822B(x) (((x) >> BIT_SHIFT_TC5DATA_8822B) & BIT_MASK_TC5DATA_8822B) - - +#define BIT_TC5DATA_8822B(x) \ + (((x) & BIT_MASK_TC5DATA_8822B) << BIT_SHIFT_TC5DATA_8822B) +#define BITS_TC5DATA_8822B (BIT_MASK_TC5DATA_8822B << BIT_SHIFT_TC5DATA_8822B) +#define BIT_CLEAR_TC5DATA_8822B(x) ((x) & (~BITS_TC5DATA_8822B)) +#define BIT_GET_TC5DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC5DATA_8822B) & BIT_MASK_TC5DATA_8822B) +#define BIT_SET_TC5DATA_8822B(x, v) \ + (BIT_CLEAR_TC5DATA_8822B(x) | BIT_TC5DATA_8822B(v)) /* 2 REG_TC6_CTRL_8822B */ #define BIT_TC6INT_EN_8822B BIT(26) @@ -2527,127 +3592,244 @@ #define BIT_SHIFT_TC6DATA_8822B 0 #define BIT_MASK_TC6DATA_8822B 0xffffff -#define BIT_TC6DATA_8822B(x) (((x) & BIT_MASK_TC6DATA_8822B) << BIT_SHIFT_TC6DATA_8822B) -#define BIT_GET_TC6DATA_8822B(x) (((x) >> BIT_SHIFT_TC6DATA_8822B) & BIT_MASK_TC6DATA_8822B) - - +#define BIT_TC6DATA_8822B(x) \ + (((x) & BIT_MASK_TC6DATA_8822B) << BIT_SHIFT_TC6DATA_8822B) +#define BITS_TC6DATA_8822B (BIT_MASK_TC6DATA_8822B << BIT_SHIFT_TC6DATA_8822B) +#define BIT_CLEAR_TC6DATA_8822B(x) ((x) & (~BITS_TC6DATA_8822B)) +#define BIT_GET_TC6DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC6DATA_8822B) & BIT_MASK_TC6DATA_8822B) +#define BIT_SET_TC6DATA_8822B(x, v) \ + (BIT_CLEAR_TC6DATA_8822B(x) | BIT_TC6DATA_8822B(v)) /* 2 REG_MBIST_FAIL_8822B */ #define BIT_SHIFT_8051_MBIST_FAIL_8822B 26 #define BIT_MASK_8051_MBIST_FAIL_8822B 0x7 -#define BIT_8051_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8822B) << BIT_SHIFT_8051_MBIST_FAIL_8822B) -#define BIT_GET_8051_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8822B) & BIT_MASK_8051_MBIST_FAIL_8822B) - - +#define BIT_8051_MBIST_FAIL_8822B(x) \ + (((x) & BIT_MASK_8051_MBIST_FAIL_8822B) \ + << BIT_SHIFT_8051_MBIST_FAIL_8822B) +#define BITS_8051_MBIST_FAIL_8822B \ + (BIT_MASK_8051_MBIST_FAIL_8822B << BIT_SHIFT_8051_MBIST_FAIL_8822B) +#define BIT_CLEAR_8051_MBIST_FAIL_8822B(x) ((x) & (~BITS_8051_MBIST_FAIL_8822B)) +#define BIT_GET_8051_MBIST_FAIL_8822B(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8822B) & \ + BIT_MASK_8051_MBIST_FAIL_8822B) +#define BIT_SET_8051_MBIST_FAIL_8822B(x, v) \ + (BIT_CLEAR_8051_MBIST_FAIL_8822B(x) | BIT_8051_MBIST_FAIL_8822B(v)) #define BIT_SHIFT_USB_MBIST_FAIL_8822B 24 #define BIT_MASK_USB_MBIST_FAIL_8822B 0x3 -#define BIT_USB_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8822B) << BIT_SHIFT_USB_MBIST_FAIL_8822B) -#define BIT_GET_USB_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8822B) & BIT_MASK_USB_MBIST_FAIL_8822B) - - +#define BIT_USB_MBIST_FAIL_8822B(x) \ + (((x) & BIT_MASK_USB_MBIST_FAIL_8822B) \ + << BIT_SHIFT_USB_MBIST_FAIL_8822B) +#define BITS_USB_MBIST_FAIL_8822B \ + (BIT_MASK_USB_MBIST_FAIL_8822B << BIT_SHIFT_USB_MBIST_FAIL_8822B) +#define BIT_CLEAR_USB_MBIST_FAIL_8822B(x) ((x) & (~BITS_USB_MBIST_FAIL_8822B)) +#define BIT_GET_USB_MBIST_FAIL_8822B(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8822B) & \ + BIT_MASK_USB_MBIST_FAIL_8822B) +#define BIT_SET_USB_MBIST_FAIL_8822B(x, v) \ + (BIT_CLEAR_USB_MBIST_FAIL_8822B(x) | BIT_USB_MBIST_FAIL_8822B(v)) #define BIT_SHIFT_PCIE_MBIST_FAIL_8822B 16 #define BIT_MASK_PCIE_MBIST_FAIL_8822B 0x3f -#define BIT_PCIE_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8822B) << BIT_SHIFT_PCIE_MBIST_FAIL_8822B) -#define BIT_GET_PCIE_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8822B) & BIT_MASK_PCIE_MBIST_FAIL_8822B) - - +#define BIT_PCIE_MBIST_FAIL_8822B(x) \ + (((x) & BIT_MASK_PCIE_MBIST_FAIL_8822B) \ + << BIT_SHIFT_PCIE_MBIST_FAIL_8822B) +#define BITS_PCIE_MBIST_FAIL_8822B \ + (BIT_MASK_PCIE_MBIST_FAIL_8822B << BIT_SHIFT_PCIE_MBIST_FAIL_8822B) +#define BIT_CLEAR_PCIE_MBIST_FAIL_8822B(x) ((x) & (~BITS_PCIE_MBIST_FAIL_8822B)) +#define BIT_GET_PCIE_MBIST_FAIL_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8822B) & \ + BIT_MASK_PCIE_MBIST_FAIL_8822B) +#define BIT_SET_PCIE_MBIST_FAIL_8822B(x, v) \ + (BIT_CLEAR_PCIE_MBIST_FAIL_8822B(x) | BIT_PCIE_MBIST_FAIL_8822B(v)) #define BIT_SHIFT_MAC_MBIST_FAIL_8822B 0 #define BIT_MASK_MAC_MBIST_FAIL_8822B 0xfff -#define BIT_MAC_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8822B) << BIT_SHIFT_MAC_MBIST_FAIL_8822B) -#define BIT_GET_MAC_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8822B) & BIT_MASK_MAC_MBIST_FAIL_8822B) - - +#define BIT_MAC_MBIST_FAIL_8822B(x) \ + (((x) & BIT_MASK_MAC_MBIST_FAIL_8822B) \ + << BIT_SHIFT_MAC_MBIST_FAIL_8822B) +#define BITS_MAC_MBIST_FAIL_8822B \ + (BIT_MASK_MAC_MBIST_FAIL_8822B << BIT_SHIFT_MAC_MBIST_FAIL_8822B) +#define BIT_CLEAR_MAC_MBIST_FAIL_8822B(x) ((x) & (~BITS_MAC_MBIST_FAIL_8822B)) +#define BIT_GET_MAC_MBIST_FAIL_8822B(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8822B) & \ + BIT_MASK_MAC_MBIST_FAIL_8822B) +#define BIT_SET_MAC_MBIST_FAIL_8822B(x, v) \ + (BIT_CLEAR_MAC_MBIST_FAIL_8822B(x) | BIT_MAC_MBIST_FAIL_8822B(v)) /* 2 REG_MBIST_START_PAUSE_8822B */ #define BIT_SHIFT_8051_MBIST_START_PAUSE_8822B 26 #define BIT_MASK_8051_MBIST_START_PAUSE_8822B 0x7 -#define BIT_8051_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8822B) << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) -#define BIT_GET_8051_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) & BIT_MASK_8051_MBIST_START_PAUSE_8822B) - - +#define BIT_8051_MBIST_START_PAUSE_8822B(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8822B) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) +#define BITS_8051_MBIST_START_PAUSE_8822B \ + (BIT_MASK_8051_MBIST_START_PAUSE_8822B \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) +#define BIT_CLEAR_8051_MBIST_START_PAUSE_8822B(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE_8822B)) +#define BIT_GET_8051_MBIST_START_PAUSE_8822B(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) & \ + BIT_MASK_8051_MBIST_START_PAUSE_8822B) +#define BIT_SET_8051_MBIST_START_PAUSE_8822B(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE_8822B(x) | \ + BIT_8051_MBIST_START_PAUSE_8822B(v)) #define BIT_SHIFT_USB_MBIST_START_PAUSE_8822B 24 #define BIT_MASK_USB_MBIST_START_PAUSE_8822B 0x3 -#define BIT_USB_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8822B) << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) -#define BIT_GET_USB_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) & BIT_MASK_USB_MBIST_START_PAUSE_8822B) - - +#define BIT_USB_MBIST_START_PAUSE_8822B(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8822B) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) +#define BITS_USB_MBIST_START_PAUSE_8822B \ + (BIT_MASK_USB_MBIST_START_PAUSE_8822B \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_8822B(x) \ + ((x) & (~BITS_USB_MBIST_START_PAUSE_8822B)) +#define BIT_GET_USB_MBIST_START_PAUSE_8822B(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) & \ + BIT_MASK_USB_MBIST_START_PAUSE_8822B) +#define BIT_SET_USB_MBIST_START_PAUSE_8822B(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE_8822B(x) | \ + BIT_USB_MBIST_START_PAUSE_8822B(v)) #define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B 16 #define BIT_MASK_PCIE_MBIST_START_PAUSE_8822B 0x3f -#define BIT_PCIE_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) -#define BIT_GET_PCIE_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) - - +#define BIT_PCIE_MBIST_START_PAUSE_8822B(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) +#define BITS_PCIE_MBIST_START_PAUSE_8822B \ + (BIT_MASK_PCIE_MBIST_START_PAUSE_8822B \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8822B(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE_8822B)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) +#define BIT_SET_PCIE_MBIST_START_PAUSE_8822B(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE_8822B(x) | \ + BIT_PCIE_MBIST_START_PAUSE_8822B(v)) #define BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B 0 #define BIT_MASK_MAC_MBIST_START_PAUSE_8822B 0xfff -#define BIT_MAC_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) -#define BIT_GET_MAC_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B) - - +#define BIT_MAC_MBIST_START_PAUSE_8822B(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) +#define BITS_MAC_MBIST_START_PAUSE_8822B \ + (BIT_MASK_MAC_MBIST_START_PAUSE_8822B \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE_8822B(x) \ + ((x) & (~BITS_MAC_MBIST_START_PAUSE_8822B)) +#define BIT_GET_MAC_MBIST_START_PAUSE_8822B(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) & \ + BIT_MASK_MAC_MBIST_START_PAUSE_8822B) +#define BIT_SET_MAC_MBIST_START_PAUSE_8822B(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE_8822B(x) | \ + BIT_MAC_MBIST_START_PAUSE_8822B(v)) /* 2 REG_MBIST_DONE_8822B */ #define BIT_SHIFT_8051_MBIST_DONE_8822B 26 #define BIT_MASK_8051_MBIST_DONE_8822B 0x7 -#define BIT_8051_MBIST_DONE_8822B(x) (((x) & BIT_MASK_8051_MBIST_DONE_8822B) << BIT_SHIFT_8051_MBIST_DONE_8822B) -#define BIT_GET_8051_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8822B) & BIT_MASK_8051_MBIST_DONE_8822B) - - +#define BIT_8051_MBIST_DONE_8822B(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE_8822B) \ + << BIT_SHIFT_8051_MBIST_DONE_8822B) +#define BITS_8051_MBIST_DONE_8822B \ + (BIT_MASK_8051_MBIST_DONE_8822B << BIT_SHIFT_8051_MBIST_DONE_8822B) +#define BIT_CLEAR_8051_MBIST_DONE_8822B(x) ((x) & (~BITS_8051_MBIST_DONE_8822B)) +#define BIT_GET_8051_MBIST_DONE_8822B(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE_8822B) & \ + BIT_MASK_8051_MBIST_DONE_8822B) +#define BIT_SET_8051_MBIST_DONE_8822B(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE_8822B(x) | BIT_8051_MBIST_DONE_8822B(v)) #define BIT_SHIFT_USB_MBIST_DONE_8822B 24 #define BIT_MASK_USB_MBIST_DONE_8822B 0x3 -#define BIT_USB_MBIST_DONE_8822B(x) (((x) & BIT_MASK_USB_MBIST_DONE_8822B) << BIT_SHIFT_USB_MBIST_DONE_8822B) -#define BIT_GET_USB_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8822B) & BIT_MASK_USB_MBIST_DONE_8822B) - - +#define BIT_USB_MBIST_DONE_8822B(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE_8822B) \ + << BIT_SHIFT_USB_MBIST_DONE_8822B) +#define BITS_USB_MBIST_DONE_8822B \ + (BIT_MASK_USB_MBIST_DONE_8822B << BIT_SHIFT_USB_MBIST_DONE_8822B) +#define BIT_CLEAR_USB_MBIST_DONE_8822B(x) ((x) & (~BITS_USB_MBIST_DONE_8822B)) +#define BIT_GET_USB_MBIST_DONE_8822B(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE_8822B) & \ + BIT_MASK_USB_MBIST_DONE_8822B) +#define BIT_SET_USB_MBIST_DONE_8822B(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE_8822B(x) | BIT_USB_MBIST_DONE_8822B(v)) #define BIT_SHIFT_PCIE_MBIST_DONE_8822B 16 #define BIT_MASK_PCIE_MBIST_DONE_8822B 0x3f -#define BIT_PCIE_MBIST_DONE_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8822B) << BIT_SHIFT_PCIE_MBIST_DONE_8822B) -#define BIT_GET_PCIE_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8822B) & BIT_MASK_PCIE_MBIST_DONE_8822B) - - +#define BIT_PCIE_MBIST_DONE_8822B(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE_8822B) \ + << BIT_SHIFT_PCIE_MBIST_DONE_8822B) +#define BITS_PCIE_MBIST_DONE_8822B \ + (BIT_MASK_PCIE_MBIST_DONE_8822B << BIT_SHIFT_PCIE_MBIST_DONE_8822B) +#define BIT_CLEAR_PCIE_MBIST_DONE_8822B(x) ((x) & (~BITS_PCIE_MBIST_DONE_8822B)) +#define BIT_GET_PCIE_MBIST_DONE_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8822B) & \ + BIT_MASK_PCIE_MBIST_DONE_8822B) +#define BIT_SET_PCIE_MBIST_DONE_8822B(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE_8822B(x) | BIT_PCIE_MBIST_DONE_8822B(v)) #define BIT_SHIFT_MAC_MBIST_DONE_8822B 0 #define BIT_MASK_MAC_MBIST_DONE_8822B 0xfff -#define BIT_MAC_MBIST_DONE_8822B(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8822B) << BIT_SHIFT_MAC_MBIST_DONE_8822B) -#define BIT_GET_MAC_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8822B) & BIT_MASK_MAC_MBIST_DONE_8822B) - - +#define BIT_MAC_MBIST_DONE_8822B(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE_8822B) \ + << BIT_SHIFT_MAC_MBIST_DONE_8822B) +#define BITS_MAC_MBIST_DONE_8822B \ + (BIT_MASK_MAC_MBIST_DONE_8822B << BIT_SHIFT_MAC_MBIST_DONE_8822B) +#define BIT_CLEAR_MAC_MBIST_DONE_8822B(x) ((x) & (~BITS_MAC_MBIST_DONE_8822B)) +#define BIT_GET_MAC_MBIST_DONE_8822B(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8822B) & \ + BIT_MASK_MAC_MBIST_DONE_8822B) +#define BIT_SET_MAC_MBIST_DONE_8822B(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE_8822B(x) | BIT_MAC_MBIST_DONE_8822B(v)) /* 2 REG_MBIST_FAIL_NRML_8822B */ #define BIT_SHIFT_MBIST_FAIL_NRML_8822B 0 #define BIT_MASK_MBIST_FAIL_NRML_8822B 0xffffffffL -#define BIT_MBIST_FAIL_NRML_8822B(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_8822B) << BIT_SHIFT_MBIST_FAIL_NRML_8822B) -#define BIT_GET_MBIST_FAIL_NRML_8822B(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8822B) & BIT_MASK_MBIST_FAIL_NRML_8822B) - - +#define BIT_MBIST_FAIL_NRML_8822B(x) \ + (((x) & BIT_MASK_MBIST_FAIL_NRML_8822B) \ + << BIT_SHIFT_MBIST_FAIL_NRML_8822B) +#define BITS_MBIST_FAIL_NRML_8822B \ + (BIT_MASK_MBIST_FAIL_NRML_8822B << BIT_SHIFT_MBIST_FAIL_NRML_8822B) +#define BIT_CLEAR_MBIST_FAIL_NRML_8822B(x) ((x) & (~BITS_MBIST_FAIL_NRML_8822B)) +#define BIT_GET_MBIST_FAIL_NRML_8822B(x) \ + (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8822B) & \ + BIT_MASK_MBIST_FAIL_NRML_8822B) +#define BIT_SET_MBIST_FAIL_NRML_8822B(x, v) \ + (BIT_CLEAR_MBIST_FAIL_NRML_8822B(x) | BIT_MBIST_FAIL_NRML_8822B(v)) /* 2 REG_AES_DECRPT_DATA_8822B */ #define BIT_SHIFT_IPS_CFG_ADDR_8822B 0 #define BIT_MASK_IPS_CFG_ADDR_8822B 0xff -#define BIT_IPS_CFG_ADDR_8822B(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8822B) << BIT_SHIFT_IPS_CFG_ADDR_8822B) -#define BIT_GET_IPS_CFG_ADDR_8822B(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822B) & BIT_MASK_IPS_CFG_ADDR_8822B) - - +#define BIT_IPS_CFG_ADDR_8822B(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR_8822B) << BIT_SHIFT_IPS_CFG_ADDR_8822B) +#define BITS_IPS_CFG_ADDR_8822B \ + (BIT_MASK_IPS_CFG_ADDR_8822B << BIT_SHIFT_IPS_CFG_ADDR_8822B) +#define BIT_CLEAR_IPS_CFG_ADDR_8822B(x) ((x) & (~BITS_IPS_CFG_ADDR_8822B)) +#define BIT_GET_IPS_CFG_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822B) & BIT_MASK_IPS_CFG_ADDR_8822B) +#define BIT_SET_IPS_CFG_ADDR_8822B(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR_8822B(x) | BIT_IPS_CFG_ADDR_8822B(v)) /* 2 REG_AES_DECRPT_CFG_8822B */ #define BIT_SHIFT_IPS_CFG_DATA_8822B 0 #define BIT_MASK_IPS_CFG_DATA_8822B 0xffffffffL -#define BIT_IPS_CFG_DATA_8822B(x) (((x) & BIT_MASK_IPS_CFG_DATA_8822B) << BIT_SHIFT_IPS_CFG_DATA_8822B) -#define BIT_GET_IPS_CFG_DATA_8822B(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8822B) & BIT_MASK_IPS_CFG_DATA_8822B) - - +#define BIT_IPS_CFG_DATA_8822B(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA_8822B) << BIT_SHIFT_IPS_CFG_DATA_8822B) +#define BITS_IPS_CFG_DATA_8822B \ + (BIT_MASK_IPS_CFG_DATA_8822B << BIT_SHIFT_IPS_CFG_DATA_8822B) +#define BIT_CLEAR_IPS_CFG_DATA_8822B(x) ((x) & (~BITS_IPS_CFG_DATA_8822B)) +#define BIT_GET_IPS_CFG_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA_8822B) & BIT_MASK_IPS_CFG_DATA_8822B) +#define BIT_SET_IPS_CFG_DATA_8822B(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA_8822B(x) | BIT_IPS_CFG_DATA_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -2658,23 +3840,44 @@ #define BIT_SHIFT_TEMP_VALUE_8822B 24 #define BIT_MASK_TEMP_VALUE_8822B 0x3f -#define BIT_TEMP_VALUE_8822B(x) (((x) & BIT_MASK_TEMP_VALUE_8822B) << BIT_SHIFT_TEMP_VALUE_8822B) -#define BIT_GET_TEMP_VALUE_8822B(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8822B) & BIT_MASK_TEMP_VALUE_8822B) - - +#define BIT_TEMP_VALUE_8822B(x) \ + (((x) & BIT_MASK_TEMP_VALUE_8822B) << BIT_SHIFT_TEMP_VALUE_8822B) +#define BITS_TEMP_VALUE_8822B \ + (BIT_MASK_TEMP_VALUE_8822B << BIT_SHIFT_TEMP_VALUE_8822B) +#define BIT_CLEAR_TEMP_VALUE_8822B(x) ((x) & (~BITS_TEMP_VALUE_8822B)) +#define BIT_GET_TEMP_VALUE_8822B(x) \ + (((x) >> BIT_SHIFT_TEMP_VALUE_8822B) & BIT_MASK_TEMP_VALUE_8822B) +#define BIT_SET_TEMP_VALUE_8822B(x, v) \ + (BIT_CLEAR_TEMP_VALUE_8822B(x) | BIT_TEMP_VALUE_8822B(v)) #define BIT_SHIFT_REG_TMETER_TIMER_8822B 8 #define BIT_MASK_REG_TMETER_TIMER_8822B 0xfff -#define BIT_REG_TMETER_TIMER_8822B(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8822B) << BIT_SHIFT_REG_TMETER_TIMER_8822B) -#define BIT_GET_REG_TMETER_TIMER_8822B(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822B) & BIT_MASK_REG_TMETER_TIMER_8822B) - - +#define BIT_REG_TMETER_TIMER_8822B(x) \ + (((x) & BIT_MASK_REG_TMETER_TIMER_8822B) \ + << BIT_SHIFT_REG_TMETER_TIMER_8822B) +#define BITS_REG_TMETER_TIMER_8822B \ + (BIT_MASK_REG_TMETER_TIMER_8822B << BIT_SHIFT_REG_TMETER_TIMER_8822B) +#define BIT_CLEAR_REG_TMETER_TIMER_8822B(x) \ + ((x) & (~BITS_REG_TMETER_TIMER_8822B)) +#define BIT_GET_REG_TMETER_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822B) & \ + BIT_MASK_REG_TMETER_TIMER_8822B) +#define BIT_SET_REG_TMETER_TIMER_8822B(x, v) \ + (BIT_CLEAR_REG_TMETER_TIMER_8822B(x) | BIT_REG_TMETER_TIMER_8822B(v)) #define BIT_SHIFT_REG_TEMP_DELTA_8822B 2 #define BIT_MASK_REG_TEMP_DELTA_8822B 0x3f -#define BIT_REG_TEMP_DELTA_8822B(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8822B) << BIT_SHIFT_REG_TEMP_DELTA_8822B) -#define BIT_GET_REG_TEMP_DELTA_8822B(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822B) & BIT_MASK_REG_TEMP_DELTA_8822B) - +#define BIT_REG_TEMP_DELTA_8822B(x) \ + (((x) & BIT_MASK_REG_TEMP_DELTA_8822B) \ + << BIT_SHIFT_REG_TEMP_DELTA_8822B) +#define BITS_REG_TEMP_DELTA_8822B \ + (BIT_MASK_REG_TEMP_DELTA_8822B << BIT_SHIFT_REG_TEMP_DELTA_8822B) +#define BIT_CLEAR_REG_TEMP_DELTA_8822B(x) ((x) & (~BITS_REG_TEMP_DELTA_8822B)) +#define BIT_GET_REG_TEMP_DELTA_8822B(x) \ + (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822B) & \ + BIT_MASK_REG_TEMP_DELTA_8822B) +#define BIT_SET_REG_TEMP_DELTA_8822B(x, v) \ + (BIT_CLEAR_REG_TEMP_DELTA_8822B(x) | BIT_REG_TEMP_DELTA_8822B(v)) #define BIT_REG_TMETER_EN_8822B BIT(0) @@ -2682,16 +3885,33 @@ #define BIT_SHIFT_OSC_32K_CLKGEN_0_8822B 16 #define BIT_MASK_OSC_32K_CLKGEN_0_8822B 0xffff -#define BIT_OSC_32K_CLKGEN_0_8822B(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822B) << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) -#define BIT_GET_OSC_32K_CLKGEN_0_8822B(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) & BIT_MASK_OSC_32K_CLKGEN_0_8822B) - - +#define BIT_OSC_32K_CLKGEN_0_8822B(x) \ + (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822B) \ + << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) +#define BITS_OSC_32K_CLKGEN_0_8822B \ + (BIT_MASK_OSC_32K_CLKGEN_0_8822B << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) +#define BIT_CLEAR_OSC_32K_CLKGEN_0_8822B(x) \ + ((x) & (~BITS_OSC_32K_CLKGEN_0_8822B)) +#define BIT_GET_OSC_32K_CLKGEN_0_8822B(x) \ + (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) & \ + BIT_MASK_OSC_32K_CLKGEN_0_8822B) +#define BIT_SET_OSC_32K_CLKGEN_0_8822B(x, v) \ + (BIT_CLEAR_OSC_32K_CLKGEN_0_8822B(x) | BIT_OSC_32K_CLKGEN_0_8822B(v)) #define BIT_SHIFT_OSC_32K_RES_COMP_8822B 4 #define BIT_MASK_OSC_32K_RES_COMP_8822B 0x3 -#define BIT_OSC_32K_RES_COMP_8822B(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8822B) << BIT_SHIFT_OSC_32K_RES_COMP_8822B) -#define BIT_GET_OSC_32K_RES_COMP_8822B(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822B) & BIT_MASK_OSC_32K_RES_COMP_8822B) - +#define BIT_OSC_32K_RES_COMP_8822B(x) \ + (((x) & BIT_MASK_OSC_32K_RES_COMP_8822B) \ + << BIT_SHIFT_OSC_32K_RES_COMP_8822B) +#define BITS_OSC_32K_RES_COMP_8822B \ + (BIT_MASK_OSC_32K_RES_COMP_8822B << BIT_SHIFT_OSC_32K_RES_COMP_8822B) +#define BIT_CLEAR_OSC_32K_RES_COMP_8822B(x) \ + ((x) & (~BITS_OSC_32K_RES_COMP_8822B)) +#define BIT_GET_OSC_32K_RES_COMP_8822B(x) \ + (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822B) & \ + BIT_MASK_OSC_32K_RES_COMP_8822B) +#define BIT_SET_OSC_32K_RES_COMP_8822B(x, v) \ + (BIT_CLEAR_OSC_32K_RES_COMP_8822B(x) | BIT_OSC_32K_RES_COMP_8822B(v)) #define BIT_OSC_32K_OUT_SEL_8822B BIT(3) #define BIT_ISO_WL_2_OSC_32K_8822B BIT(1) @@ -2703,73 +3923,164 @@ #define BIT_SHIFT_CAL_32K_REG_ADDR_8822B 16 #define BIT_MASK_CAL_32K_REG_ADDR_8822B 0x3f -#define BIT_CAL_32K_REG_ADDR_8822B(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR_8822B) << BIT_SHIFT_CAL_32K_REG_ADDR_8822B) -#define BIT_GET_CAL_32K_REG_ADDR_8822B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822B) & BIT_MASK_CAL_32K_REG_ADDR_8822B) - - +#define BIT_CAL_32K_REG_ADDR_8822B(x) \ + (((x) & BIT_MASK_CAL_32K_REG_ADDR_8822B) \ + << BIT_SHIFT_CAL_32K_REG_ADDR_8822B) +#define BITS_CAL_32K_REG_ADDR_8822B \ + (BIT_MASK_CAL_32K_REG_ADDR_8822B << BIT_SHIFT_CAL_32K_REG_ADDR_8822B) +#define BIT_CLEAR_CAL_32K_REG_ADDR_8822B(x) \ + ((x) & (~BITS_CAL_32K_REG_ADDR_8822B)) +#define BIT_GET_CAL_32K_REG_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822B) & \ + BIT_MASK_CAL_32K_REG_ADDR_8822B) +#define BIT_SET_CAL_32K_REG_ADDR_8822B(x, v) \ + (BIT_CLEAR_CAL_32K_REG_ADDR_8822B(x) | BIT_CAL_32K_REG_ADDR_8822B(v)) #define BIT_SHIFT_CAL_32K_REG_DATA_8822B 0 #define BIT_MASK_CAL_32K_REG_DATA_8822B 0xffff -#define BIT_CAL_32K_REG_DATA_8822B(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8822B) << BIT_SHIFT_CAL_32K_REG_DATA_8822B) -#define BIT_GET_CAL_32K_REG_DATA_8822B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822B) & BIT_MASK_CAL_32K_REG_DATA_8822B) - - +#define BIT_CAL_32K_REG_DATA_8822B(x) \ + (((x) & BIT_MASK_CAL_32K_REG_DATA_8822B) \ + << BIT_SHIFT_CAL_32K_REG_DATA_8822B) +#define BITS_CAL_32K_REG_DATA_8822B \ + (BIT_MASK_CAL_32K_REG_DATA_8822B << BIT_SHIFT_CAL_32K_REG_DATA_8822B) +#define BIT_CLEAR_CAL_32K_REG_DATA_8822B(x) \ + ((x) & (~BITS_CAL_32K_REG_DATA_8822B)) +#define BIT_GET_CAL_32K_REG_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822B) & \ + BIT_MASK_CAL_32K_REG_DATA_8822B) +#define BIT_SET_CAL_32K_REG_DATA_8822B(x, v) \ + (BIT_CLEAR_CAL_32K_REG_DATA_8822B(x) | BIT_CAL_32K_REG_DATA_8822B(v)) /* 2 REG_NOT_VALID_8822B */ /* 2 REG_C2HEVT_8822B */ -#define BIT_SHIFT_C2HEVT_MSG_8822B 0 -#define BIT_MASK_C2HEVT_MSG_8822B 0xffffffffffffffffffffffffffffffffL -#define BIT_C2HEVT_MSG_8822B(x) (((x) & BIT_MASK_C2HEVT_MSG_8822B) << BIT_SHIFT_C2HEVT_MSG_8822B) -#define BIT_GET_C2HEVT_MSG_8822B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_8822B) & BIT_MASK_C2HEVT_MSG_8822B) - - +#define BIT_SHIFT_C2HEVT_MSG_V1_8822B 0 +#define BIT_MASK_C2HEVT_MSG_V1_8822B 0xffffffffL +#define BIT_C2HEVT_MSG_V1_8822B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_V1_8822B) << BIT_SHIFT_C2HEVT_MSG_V1_8822B) +#define BITS_C2HEVT_MSG_V1_8822B \ + (BIT_MASK_C2HEVT_MSG_V1_8822B << BIT_SHIFT_C2HEVT_MSG_V1_8822B) +#define BIT_CLEAR_C2HEVT_MSG_V1_8822B(x) ((x) & (~BITS_C2HEVT_MSG_V1_8822B)) +#define BIT_GET_C2HEVT_MSG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8822B) & BIT_MASK_C2HEVT_MSG_V1_8822B) +#define BIT_SET_C2HEVT_MSG_V1_8822B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_V1_8822B(x) | BIT_C2HEVT_MSG_V1_8822B(v)) + +/* 2 REG_C2HEVT_1_8822B */ + +#define BIT_SHIFT_C2HEVT_MSG_1_8822B 0 +#define BIT_MASK_C2HEVT_MSG_1_8822B 0xffffffffL +#define BIT_C2HEVT_MSG_1_8822B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_1_8822B) << BIT_SHIFT_C2HEVT_MSG_1_8822B) +#define BITS_C2HEVT_MSG_1_8822B \ + (BIT_MASK_C2HEVT_MSG_1_8822B << BIT_SHIFT_C2HEVT_MSG_1_8822B) +#define BIT_CLEAR_C2HEVT_MSG_1_8822B(x) ((x) & (~BITS_C2HEVT_MSG_1_8822B)) +#define BIT_GET_C2HEVT_MSG_1_8822B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8822B) & BIT_MASK_C2HEVT_MSG_1_8822B) +#define BIT_SET_C2HEVT_MSG_1_8822B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_1_8822B(x) | BIT_C2HEVT_MSG_1_8822B(v)) + +/* 2 REG_C2HEVT_2_8822B */ + +#define BIT_SHIFT_C2HEVT_MSG_2_8822B 0 +#define BIT_MASK_C2HEVT_MSG_2_8822B 0xffffffffL +#define BIT_C2HEVT_MSG_2_8822B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_2_8822B) << BIT_SHIFT_C2HEVT_MSG_2_8822B) +#define BITS_C2HEVT_MSG_2_8822B \ + (BIT_MASK_C2HEVT_MSG_2_8822B << BIT_SHIFT_C2HEVT_MSG_2_8822B) +#define BIT_CLEAR_C2HEVT_MSG_2_8822B(x) ((x) & (~BITS_C2HEVT_MSG_2_8822B)) +#define BIT_GET_C2HEVT_MSG_2_8822B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8822B) & BIT_MASK_C2HEVT_MSG_2_8822B) +#define BIT_SET_C2HEVT_MSG_2_8822B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_2_8822B(x) | BIT_C2HEVT_MSG_2_8822B(v)) + +/* 2 REG_C2HEVT_3_8822B */ + +#define BIT_SHIFT_C2HEVT_MSG_3_8822B 0 +#define BIT_MASK_C2HEVT_MSG_3_8822B 0xffffffffL +#define BIT_C2HEVT_MSG_3_8822B(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_3_8822B) << BIT_SHIFT_C2HEVT_MSG_3_8822B) +#define BITS_C2HEVT_MSG_3_8822B \ + (BIT_MASK_C2HEVT_MSG_3_8822B << BIT_SHIFT_C2HEVT_MSG_3_8822B) +#define BIT_CLEAR_C2HEVT_MSG_3_8822B(x) ((x) & (~BITS_C2HEVT_MSG_3_8822B)) +#define BIT_GET_C2HEVT_MSG_3_8822B(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8822B) & BIT_MASK_C2HEVT_MSG_3_8822B) +#define BIT_SET_C2HEVT_MSG_3_8822B(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_3_8822B(x) | BIT_C2HEVT_MSG_3_8822B(v)) /* 2 REG_SW_DEFINED_PAGE1_8822B */ #define BIT_SHIFT_SW_DEFINED_PAGE1_8822B 0 #define BIT_MASK_SW_DEFINED_PAGE1_8822B 0xffffffffffffffffL -#define BIT_SW_DEFINED_PAGE1_8822B(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_8822B) << BIT_SHIFT_SW_DEFINED_PAGE1_8822B) -#define BIT_GET_SW_DEFINED_PAGE1_8822B(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8822B) & BIT_MASK_SW_DEFINED_PAGE1_8822B) - - +#define BIT_SW_DEFINED_PAGE1_8822B(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_8822B) \ + << BIT_SHIFT_SW_DEFINED_PAGE1_8822B) +#define BITS_SW_DEFINED_PAGE1_8822B \ + (BIT_MASK_SW_DEFINED_PAGE1_8822B << BIT_SHIFT_SW_DEFINED_PAGE1_8822B) +#define BIT_CLEAR_SW_DEFINED_PAGE1_8822B(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE1_8822B)) +#define BIT_GET_SW_DEFINED_PAGE1_8822B(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8822B) & \ + BIT_MASK_SW_DEFINED_PAGE1_8822B) +#define BIT_SET_SW_DEFINED_PAGE1_8822B(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_8822B(x) | BIT_SW_DEFINED_PAGE1_8822B(v)) /* 2 REG_MCUTST_I_8822B */ #define BIT_SHIFT_MCUDMSG_I_8822B 0 #define BIT_MASK_MCUDMSG_I_8822B 0xffffffffL -#define BIT_MCUDMSG_I_8822B(x) (((x) & BIT_MASK_MCUDMSG_I_8822B) << BIT_SHIFT_MCUDMSG_I_8822B) -#define BIT_GET_MCUDMSG_I_8822B(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8822B) & BIT_MASK_MCUDMSG_I_8822B) - - +#define BIT_MCUDMSG_I_8822B(x) \ + (((x) & BIT_MASK_MCUDMSG_I_8822B) << BIT_SHIFT_MCUDMSG_I_8822B) +#define BITS_MCUDMSG_I_8822B \ + (BIT_MASK_MCUDMSG_I_8822B << BIT_SHIFT_MCUDMSG_I_8822B) +#define BIT_CLEAR_MCUDMSG_I_8822B(x) ((x) & (~BITS_MCUDMSG_I_8822B)) +#define BIT_GET_MCUDMSG_I_8822B(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_I_8822B) & BIT_MASK_MCUDMSG_I_8822B) +#define BIT_SET_MCUDMSG_I_8822B(x, v) \ + (BIT_CLEAR_MCUDMSG_I_8822B(x) | BIT_MCUDMSG_I_8822B(v)) /* 2 REG_MCUTST_II_8822B */ #define BIT_SHIFT_MCUDMSG_II_8822B 0 #define BIT_MASK_MCUDMSG_II_8822B 0xffffffffL -#define BIT_MCUDMSG_II_8822B(x) (((x) & BIT_MASK_MCUDMSG_II_8822B) << BIT_SHIFT_MCUDMSG_II_8822B) -#define BIT_GET_MCUDMSG_II_8822B(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8822B) & BIT_MASK_MCUDMSG_II_8822B) - - +#define BIT_MCUDMSG_II_8822B(x) \ + (((x) & BIT_MASK_MCUDMSG_II_8822B) << BIT_SHIFT_MCUDMSG_II_8822B) +#define BITS_MCUDMSG_II_8822B \ + (BIT_MASK_MCUDMSG_II_8822B << BIT_SHIFT_MCUDMSG_II_8822B) +#define BIT_CLEAR_MCUDMSG_II_8822B(x) ((x) & (~BITS_MCUDMSG_II_8822B)) +#define BIT_GET_MCUDMSG_II_8822B(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II_8822B) & BIT_MASK_MCUDMSG_II_8822B) +#define BIT_SET_MCUDMSG_II_8822B(x, v) \ + (BIT_CLEAR_MCUDMSG_II_8822B(x) | BIT_MCUDMSG_II_8822B(v)) /* 2 REG_FMETHR_8822B */ #define BIT_FMSG_INT_8822B BIT(31) #define BIT_SHIFT_FW_MSG_8822B 0 #define BIT_MASK_FW_MSG_8822B 0xffffffffL -#define BIT_FW_MSG_8822B(x) (((x) & BIT_MASK_FW_MSG_8822B) << BIT_SHIFT_FW_MSG_8822B) -#define BIT_GET_FW_MSG_8822B(x) (((x) >> BIT_SHIFT_FW_MSG_8822B) & BIT_MASK_FW_MSG_8822B) - - +#define BIT_FW_MSG_8822B(x) \ + (((x) & BIT_MASK_FW_MSG_8822B) << BIT_SHIFT_FW_MSG_8822B) +#define BITS_FW_MSG_8822B (BIT_MASK_FW_MSG_8822B << BIT_SHIFT_FW_MSG_8822B) +#define BIT_CLEAR_FW_MSG_8822B(x) ((x) & (~BITS_FW_MSG_8822B)) +#define BIT_GET_FW_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_FW_MSG_8822B) & BIT_MASK_FW_MSG_8822B) +#define BIT_SET_FW_MSG_8822B(x, v) \ + (BIT_CLEAR_FW_MSG_8822B(x) | BIT_FW_MSG_8822B(v)) /* 2 REG_HMETFR_8822B */ #define BIT_SHIFT_HRCV_MSG_8822B 24 #define BIT_MASK_HRCV_MSG_8822B 0xff -#define BIT_HRCV_MSG_8822B(x) (((x) & BIT_MASK_HRCV_MSG_8822B) << BIT_SHIFT_HRCV_MSG_8822B) -#define BIT_GET_HRCV_MSG_8822B(x) (((x) >> BIT_SHIFT_HRCV_MSG_8822B) & BIT_MASK_HRCV_MSG_8822B) - +#define BIT_HRCV_MSG_8822B(x) \ + (((x) & BIT_MASK_HRCV_MSG_8822B) << BIT_SHIFT_HRCV_MSG_8822B) +#define BITS_HRCV_MSG_8822B \ + (BIT_MASK_HRCV_MSG_8822B << BIT_SHIFT_HRCV_MSG_8822B) +#define BIT_CLEAR_HRCV_MSG_8822B(x) ((x) & (~BITS_HRCV_MSG_8822B)) +#define BIT_GET_HRCV_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_HRCV_MSG_8822B) & BIT_MASK_HRCV_MSG_8822B) +#define BIT_SET_HRCV_MSG_8822B(x, v) \ + (BIT_CLEAR_HRCV_MSG_8822B(x) | BIT_HRCV_MSG_8822B(v)) #define BIT_INT_BOX3_8822B BIT(3) #define BIT_INT_BOX2_8822B BIT(2) @@ -2780,91 +4091,152 @@ #define BIT_SHIFT_HOST_MSG_0_8822B 0 #define BIT_MASK_HOST_MSG_0_8822B 0xffffffffL -#define BIT_HOST_MSG_0_8822B(x) (((x) & BIT_MASK_HOST_MSG_0_8822B) << BIT_SHIFT_HOST_MSG_0_8822B) -#define BIT_GET_HOST_MSG_0_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8822B) & BIT_MASK_HOST_MSG_0_8822B) - - +#define BIT_HOST_MSG_0_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_0_8822B) << BIT_SHIFT_HOST_MSG_0_8822B) +#define BITS_HOST_MSG_0_8822B \ + (BIT_MASK_HOST_MSG_0_8822B << BIT_SHIFT_HOST_MSG_0_8822B) +#define BIT_CLEAR_HOST_MSG_0_8822B(x) ((x) & (~BITS_HOST_MSG_0_8822B)) +#define BIT_GET_HOST_MSG_0_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0_8822B) & BIT_MASK_HOST_MSG_0_8822B) +#define BIT_SET_HOST_MSG_0_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_0_8822B(x) | BIT_HOST_MSG_0_8822B(v)) /* 2 REG_HMEBOX1_8822B */ #define BIT_SHIFT_HOST_MSG_1_8822B 0 #define BIT_MASK_HOST_MSG_1_8822B 0xffffffffL -#define BIT_HOST_MSG_1_8822B(x) (((x) & BIT_MASK_HOST_MSG_1_8822B) << BIT_SHIFT_HOST_MSG_1_8822B) -#define BIT_GET_HOST_MSG_1_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8822B) & BIT_MASK_HOST_MSG_1_8822B) - - +#define BIT_HOST_MSG_1_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_1_8822B) << BIT_SHIFT_HOST_MSG_1_8822B) +#define BITS_HOST_MSG_1_8822B \ + (BIT_MASK_HOST_MSG_1_8822B << BIT_SHIFT_HOST_MSG_1_8822B) +#define BIT_CLEAR_HOST_MSG_1_8822B(x) ((x) & (~BITS_HOST_MSG_1_8822B)) +#define BIT_GET_HOST_MSG_1_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1_8822B) & BIT_MASK_HOST_MSG_1_8822B) +#define BIT_SET_HOST_MSG_1_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_1_8822B(x) | BIT_HOST_MSG_1_8822B(v)) /* 2 REG_HMEBOX2_8822B */ #define BIT_SHIFT_HOST_MSG_2_8822B 0 #define BIT_MASK_HOST_MSG_2_8822B 0xffffffffL -#define BIT_HOST_MSG_2_8822B(x) (((x) & BIT_MASK_HOST_MSG_2_8822B) << BIT_SHIFT_HOST_MSG_2_8822B) -#define BIT_GET_HOST_MSG_2_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8822B) & BIT_MASK_HOST_MSG_2_8822B) - - +#define BIT_HOST_MSG_2_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_2_8822B) << BIT_SHIFT_HOST_MSG_2_8822B) +#define BITS_HOST_MSG_2_8822B \ + (BIT_MASK_HOST_MSG_2_8822B << BIT_SHIFT_HOST_MSG_2_8822B) +#define BIT_CLEAR_HOST_MSG_2_8822B(x) ((x) & (~BITS_HOST_MSG_2_8822B)) +#define BIT_GET_HOST_MSG_2_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2_8822B) & BIT_MASK_HOST_MSG_2_8822B) +#define BIT_SET_HOST_MSG_2_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_2_8822B(x) | BIT_HOST_MSG_2_8822B(v)) /* 2 REG_HMEBOX3_8822B */ #define BIT_SHIFT_HOST_MSG_3_8822B 0 #define BIT_MASK_HOST_MSG_3_8822B 0xffffffffL -#define BIT_HOST_MSG_3_8822B(x) (((x) & BIT_MASK_HOST_MSG_3_8822B) << BIT_SHIFT_HOST_MSG_3_8822B) -#define BIT_GET_HOST_MSG_3_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8822B) & BIT_MASK_HOST_MSG_3_8822B) - - +#define BIT_HOST_MSG_3_8822B(x) \ + (((x) & BIT_MASK_HOST_MSG_3_8822B) << BIT_SHIFT_HOST_MSG_3_8822B) +#define BITS_HOST_MSG_3_8822B \ + (BIT_MASK_HOST_MSG_3_8822B << BIT_SHIFT_HOST_MSG_3_8822B) +#define BIT_CLEAR_HOST_MSG_3_8822B(x) ((x) & (~BITS_HOST_MSG_3_8822B)) +#define BIT_GET_HOST_MSG_3_8822B(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3_8822B) & BIT_MASK_HOST_MSG_3_8822B) +#define BIT_SET_HOST_MSG_3_8822B(x, v) \ + (BIT_CLEAR_HOST_MSG_3_8822B(x) | BIT_HOST_MSG_3_8822B(v)) /* 2 REG_LLT_INIT_8822B */ #define BIT_SHIFT_LLTE_RWM_8822B 30 #define BIT_MASK_LLTE_RWM_8822B 0x3 -#define BIT_LLTE_RWM_8822B(x) (((x) & BIT_MASK_LLTE_RWM_8822B) << BIT_SHIFT_LLTE_RWM_8822B) -#define BIT_GET_LLTE_RWM_8822B(x) (((x) >> BIT_SHIFT_LLTE_RWM_8822B) & BIT_MASK_LLTE_RWM_8822B) - - +#define BIT_LLTE_RWM_8822B(x) \ + (((x) & BIT_MASK_LLTE_RWM_8822B) << BIT_SHIFT_LLTE_RWM_8822B) +#define BITS_LLTE_RWM_8822B \ + (BIT_MASK_LLTE_RWM_8822B << BIT_SHIFT_LLTE_RWM_8822B) +#define BIT_CLEAR_LLTE_RWM_8822B(x) ((x) & (~BITS_LLTE_RWM_8822B)) +#define BIT_GET_LLTE_RWM_8822B(x) \ + (((x) >> BIT_SHIFT_LLTE_RWM_8822B) & BIT_MASK_LLTE_RWM_8822B) +#define BIT_SET_LLTE_RWM_8822B(x, v) \ + (BIT_CLEAR_LLTE_RWM_8822B(x) | BIT_LLTE_RWM_8822B(v)) #define BIT_SHIFT_LLTINI_PDATA_V1_8822B 16 #define BIT_MASK_LLTINI_PDATA_V1_8822B 0xfff -#define BIT_LLTINI_PDATA_V1_8822B(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8822B) << BIT_SHIFT_LLTINI_PDATA_V1_8822B) -#define BIT_GET_LLTINI_PDATA_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8822B) & BIT_MASK_LLTINI_PDATA_V1_8822B) - - +#define BIT_LLTINI_PDATA_V1_8822B(x) \ + (((x) & BIT_MASK_LLTINI_PDATA_V1_8822B) \ + << BIT_SHIFT_LLTINI_PDATA_V1_8822B) +#define BITS_LLTINI_PDATA_V1_8822B \ + (BIT_MASK_LLTINI_PDATA_V1_8822B << BIT_SHIFT_LLTINI_PDATA_V1_8822B) +#define BIT_CLEAR_LLTINI_PDATA_V1_8822B(x) ((x) & (~BITS_LLTINI_PDATA_V1_8822B)) +#define BIT_GET_LLTINI_PDATA_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8822B) & \ + BIT_MASK_LLTINI_PDATA_V1_8822B) +#define BIT_SET_LLTINI_PDATA_V1_8822B(x, v) \ + (BIT_CLEAR_LLTINI_PDATA_V1_8822B(x) | BIT_LLTINI_PDATA_V1_8822B(v)) #define BIT_SHIFT_LLTINI_HDATA_V1_8822B 0 #define BIT_MASK_LLTINI_HDATA_V1_8822B 0xfff -#define BIT_LLTINI_HDATA_V1_8822B(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8822B) << BIT_SHIFT_LLTINI_HDATA_V1_8822B) -#define BIT_GET_LLTINI_HDATA_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8822B) & BIT_MASK_LLTINI_HDATA_V1_8822B) - - +#define BIT_LLTINI_HDATA_V1_8822B(x) \ + (((x) & BIT_MASK_LLTINI_HDATA_V1_8822B) \ + << BIT_SHIFT_LLTINI_HDATA_V1_8822B) +#define BITS_LLTINI_HDATA_V1_8822B \ + (BIT_MASK_LLTINI_HDATA_V1_8822B << BIT_SHIFT_LLTINI_HDATA_V1_8822B) +#define BIT_CLEAR_LLTINI_HDATA_V1_8822B(x) ((x) & (~BITS_LLTINI_HDATA_V1_8822B)) +#define BIT_GET_LLTINI_HDATA_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8822B) & \ + BIT_MASK_LLTINI_HDATA_V1_8822B) +#define BIT_SET_LLTINI_HDATA_V1_8822B(x, v) \ + (BIT_CLEAR_LLTINI_HDATA_V1_8822B(x) | BIT_LLTINI_HDATA_V1_8822B(v)) /* 2 REG_LLT_INIT_ADDR_8822B */ #define BIT_SHIFT_LLTINI_ADDR_V1_8822B 0 #define BIT_MASK_LLTINI_ADDR_V1_8822B 0xfff -#define BIT_LLTINI_ADDR_V1_8822B(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8822B) << BIT_SHIFT_LLTINI_ADDR_V1_8822B) -#define BIT_GET_LLTINI_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8822B) & BIT_MASK_LLTINI_ADDR_V1_8822B) - - +#define BIT_LLTINI_ADDR_V1_8822B(x) \ + (((x) & BIT_MASK_LLTINI_ADDR_V1_8822B) \ + << BIT_SHIFT_LLTINI_ADDR_V1_8822B) +#define BITS_LLTINI_ADDR_V1_8822B \ + (BIT_MASK_LLTINI_ADDR_V1_8822B << BIT_SHIFT_LLTINI_ADDR_V1_8822B) +#define BIT_CLEAR_LLTINI_ADDR_V1_8822B(x) ((x) & (~BITS_LLTINI_ADDR_V1_8822B)) +#define BIT_GET_LLTINI_ADDR_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8822B) & \ + BIT_MASK_LLTINI_ADDR_V1_8822B) +#define BIT_SET_LLTINI_ADDR_V1_8822B(x, v) \ + (BIT_CLEAR_LLTINI_ADDR_V1_8822B(x) | BIT_LLTINI_ADDR_V1_8822B(v)) /* 2 REG_BB_ACCESS_CTRL_8822B */ #define BIT_SHIFT_BB_WRITE_READ_8822B 30 #define BIT_MASK_BB_WRITE_READ_8822B 0x3 -#define BIT_BB_WRITE_READ_8822B(x) (((x) & BIT_MASK_BB_WRITE_READ_8822B) << BIT_SHIFT_BB_WRITE_READ_8822B) -#define BIT_GET_BB_WRITE_READ_8822B(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8822B) & BIT_MASK_BB_WRITE_READ_8822B) - - +#define BIT_BB_WRITE_READ_8822B(x) \ + (((x) & BIT_MASK_BB_WRITE_READ_8822B) << BIT_SHIFT_BB_WRITE_READ_8822B) +#define BITS_BB_WRITE_READ_8822B \ + (BIT_MASK_BB_WRITE_READ_8822B << BIT_SHIFT_BB_WRITE_READ_8822B) +#define BIT_CLEAR_BB_WRITE_READ_8822B(x) ((x) & (~BITS_BB_WRITE_READ_8822B)) +#define BIT_GET_BB_WRITE_READ_8822B(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ_8822B) & BIT_MASK_BB_WRITE_READ_8822B) +#define BIT_SET_BB_WRITE_READ_8822B(x, v) \ + (BIT_CLEAR_BB_WRITE_READ_8822B(x) | BIT_BB_WRITE_READ_8822B(v)) #define BIT_SHIFT_BB_WRITE_EN_8822B 12 #define BIT_MASK_BB_WRITE_EN_8822B 0xf -#define BIT_BB_WRITE_EN_8822B(x) (((x) & BIT_MASK_BB_WRITE_EN_8822B) << BIT_SHIFT_BB_WRITE_EN_8822B) -#define BIT_GET_BB_WRITE_EN_8822B(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8822B) & BIT_MASK_BB_WRITE_EN_8822B) - - +#define BIT_BB_WRITE_EN_8822B(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_8822B) << BIT_SHIFT_BB_WRITE_EN_8822B) +#define BITS_BB_WRITE_EN_8822B \ + (BIT_MASK_BB_WRITE_EN_8822B << BIT_SHIFT_BB_WRITE_EN_8822B) +#define BIT_CLEAR_BB_WRITE_EN_8822B(x) ((x) & (~BITS_BB_WRITE_EN_8822B)) +#define BIT_GET_BB_WRITE_EN_8822B(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_8822B) & BIT_MASK_BB_WRITE_EN_8822B) +#define BIT_SET_BB_WRITE_EN_8822B(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_8822B(x) | BIT_BB_WRITE_EN_8822B(v)) #define BIT_SHIFT_BB_ADDR_8822B 2 #define BIT_MASK_BB_ADDR_8822B 0x1ff -#define BIT_BB_ADDR_8822B(x) (((x) & BIT_MASK_BB_ADDR_8822B) << BIT_SHIFT_BB_ADDR_8822B) -#define BIT_GET_BB_ADDR_8822B(x) (((x) >> BIT_SHIFT_BB_ADDR_8822B) & BIT_MASK_BB_ADDR_8822B) - +#define BIT_BB_ADDR_8822B(x) \ + (((x) & BIT_MASK_BB_ADDR_8822B) << BIT_SHIFT_BB_ADDR_8822B) +#define BITS_BB_ADDR_8822B (BIT_MASK_BB_ADDR_8822B << BIT_SHIFT_BB_ADDR_8822B) +#define BIT_CLEAR_BB_ADDR_8822B(x) ((x) & (~BITS_BB_ADDR_8822B)) +#define BIT_GET_BB_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_8822B) & BIT_MASK_BB_ADDR_8822B) +#define BIT_SET_BB_ADDR_8822B(x, v) \ + (BIT_CLEAR_BB_ADDR_8822B(x) | BIT_BB_ADDR_8822B(v)) #define BIT_BB_ERRACC_8822B BIT(0) @@ -2872,46 +4244,70 @@ #define BIT_SHIFT_BB_DATA_8822B 0 #define BIT_MASK_BB_DATA_8822B 0xffffffffL -#define BIT_BB_DATA_8822B(x) (((x) & BIT_MASK_BB_DATA_8822B) << BIT_SHIFT_BB_DATA_8822B) -#define BIT_GET_BB_DATA_8822B(x) (((x) >> BIT_SHIFT_BB_DATA_8822B) & BIT_MASK_BB_DATA_8822B) - - +#define BIT_BB_DATA_8822B(x) \ + (((x) & BIT_MASK_BB_DATA_8822B) << BIT_SHIFT_BB_DATA_8822B) +#define BITS_BB_DATA_8822B (BIT_MASK_BB_DATA_8822B << BIT_SHIFT_BB_DATA_8822B) +#define BIT_CLEAR_BB_DATA_8822B(x) ((x) & (~BITS_BB_DATA_8822B)) +#define BIT_GET_BB_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_BB_DATA_8822B) & BIT_MASK_BB_DATA_8822B) +#define BIT_SET_BB_DATA_8822B(x, v) \ + (BIT_CLEAR_BB_DATA_8822B(x) | BIT_BB_DATA_8822B(v)) /* 2 REG_HMEBOX_E0_8822B */ #define BIT_SHIFT_HMEBOX_E0_8822B 0 #define BIT_MASK_HMEBOX_E0_8822B 0xffffffffL -#define BIT_HMEBOX_E0_8822B(x) (((x) & BIT_MASK_HMEBOX_E0_8822B) << BIT_SHIFT_HMEBOX_E0_8822B) -#define BIT_GET_HMEBOX_E0_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8822B) & BIT_MASK_HMEBOX_E0_8822B) - - +#define BIT_HMEBOX_E0_8822B(x) \ + (((x) & BIT_MASK_HMEBOX_E0_8822B) << BIT_SHIFT_HMEBOX_E0_8822B) +#define BITS_HMEBOX_E0_8822B \ + (BIT_MASK_HMEBOX_E0_8822B << BIT_SHIFT_HMEBOX_E0_8822B) +#define BIT_CLEAR_HMEBOX_E0_8822B(x) ((x) & (~BITS_HMEBOX_E0_8822B)) +#define BIT_GET_HMEBOX_E0_8822B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E0_8822B) & BIT_MASK_HMEBOX_E0_8822B) +#define BIT_SET_HMEBOX_E0_8822B(x, v) \ + (BIT_CLEAR_HMEBOX_E0_8822B(x) | BIT_HMEBOX_E0_8822B(v)) /* 2 REG_HMEBOX_E1_8822B */ #define BIT_SHIFT_HMEBOX_E1_8822B 0 #define BIT_MASK_HMEBOX_E1_8822B 0xffffffffL -#define BIT_HMEBOX_E1_8822B(x) (((x) & BIT_MASK_HMEBOX_E1_8822B) << BIT_SHIFT_HMEBOX_E1_8822B) -#define BIT_GET_HMEBOX_E1_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8822B) & BIT_MASK_HMEBOX_E1_8822B) - - +#define BIT_HMEBOX_E1_8822B(x) \ + (((x) & BIT_MASK_HMEBOX_E1_8822B) << BIT_SHIFT_HMEBOX_E1_8822B) +#define BITS_HMEBOX_E1_8822B \ + (BIT_MASK_HMEBOX_E1_8822B << BIT_SHIFT_HMEBOX_E1_8822B) +#define BIT_CLEAR_HMEBOX_E1_8822B(x) ((x) & (~BITS_HMEBOX_E1_8822B)) +#define BIT_GET_HMEBOX_E1_8822B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E1_8822B) & BIT_MASK_HMEBOX_E1_8822B) +#define BIT_SET_HMEBOX_E1_8822B(x, v) \ + (BIT_CLEAR_HMEBOX_E1_8822B(x) | BIT_HMEBOX_E1_8822B(v)) /* 2 REG_HMEBOX_E2_8822B */ #define BIT_SHIFT_HMEBOX_E2_8822B 0 #define BIT_MASK_HMEBOX_E2_8822B 0xffffffffL -#define BIT_HMEBOX_E2_8822B(x) (((x) & BIT_MASK_HMEBOX_E2_8822B) << BIT_SHIFT_HMEBOX_E2_8822B) -#define BIT_GET_HMEBOX_E2_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8822B) & BIT_MASK_HMEBOX_E2_8822B) - - +#define BIT_HMEBOX_E2_8822B(x) \ + (((x) & BIT_MASK_HMEBOX_E2_8822B) << BIT_SHIFT_HMEBOX_E2_8822B) +#define BITS_HMEBOX_E2_8822B \ + (BIT_MASK_HMEBOX_E2_8822B << BIT_SHIFT_HMEBOX_E2_8822B) +#define BIT_CLEAR_HMEBOX_E2_8822B(x) ((x) & (~BITS_HMEBOX_E2_8822B)) +#define BIT_GET_HMEBOX_E2_8822B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E2_8822B) & BIT_MASK_HMEBOX_E2_8822B) +#define BIT_SET_HMEBOX_E2_8822B(x, v) \ + (BIT_CLEAR_HMEBOX_E2_8822B(x) | BIT_HMEBOX_E2_8822B(v)) /* 2 REG_HMEBOX_E3_8822B */ #define BIT_SHIFT_HMEBOX_E3_8822B 0 #define BIT_MASK_HMEBOX_E3_8822B 0xffffffffL -#define BIT_HMEBOX_E3_8822B(x) (((x) & BIT_MASK_HMEBOX_E3_8822B) << BIT_SHIFT_HMEBOX_E3_8822B) -#define BIT_GET_HMEBOX_E3_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8822B) & BIT_MASK_HMEBOX_E3_8822B) - - +#define BIT_HMEBOX_E3_8822B(x) \ + (((x) & BIT_MASK_HMEBOX_E3_8822B) << BIT_SHIFT_HMEBOX_E3_8822B) +#define BITS_HMEBOX_E3_8822B \ + (BIT_MASK_HMEBOX_E3_8822B << BIT_SHIFT_HMEBOX_E3_8822B) +#define BIT_CLEAR_HMEBOX_E3_8822B(x) ((x) & (~BITS_HMEBOX_E3_8822B)) +#define BIT_GET_HMEBOX_E3_8822B(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E3_8822B) & BIT_MASK_HMEBOX_E3_8822B) +#define BIT_SET_HMEBOX_E3_8822B(x, v) \ + (BIT_CLEAR_HMEBOX_E3_8822B(x) | BIT_HMEBOX_E3_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -2919,55 +4315,88 @@ #define BIT_SHIFT_PHY_REQ_DELAY_8822B 24 #define BIT_MASK_PHY_REQ_DELAY_8822B 0xf -#define BIT_PHY_REQ_DELAY_8822B(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8822B) << BIT_SHIFT_PHY_REQ_DELAY_8822B) -#define BIT_GET_PHY_REQ_DELAY_8822B(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822B) & BIT_MASK_PHY_REQ_DELAY_8822B) - +#define BIT_PHY_REQ_DELAY_8822B(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY_8822B) << BIT_SHIFT_PHY_REQ_DELAY_8822B) +#define BITS_PHY_REQ_DELAY_8822B \ + (BIT_MASK_PHY_REQ_DELAY_8822B << BIT_SHIFT_PHY_REQ_DELAY_8822B) +#define BIT_CLEAR_PHY_REQ_DELAY_8822B(x) ((x) & (~BITS_PHY_REQ_DELAY_8822B)) +#define BIT_GET_PHY_REQ_DELAY_8822B(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822B) & BIT_MASK_PHY_REQ_DELAY_8822B) +#define BIT_SET_PHY_REQ_DELAY_8822B(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY_8822B(x) | BIT_PHY_REQ_DELAY_8822B(v)) #define BIT_SPD_DOWN_8822B BIT(16) #define BIT_SHIFT_NETYPE4_8822B 4 #define BIT_MASK_NETYPE4_8822B 0x3 -#define BIT_NETYPE4_8822B(x) (((x) & BIT_MASK_NETYPE4_8822B) << BIT_SHIFT_NETYPE4_8822B) -#define BIT_GET_NETYPE4_8822B(x) (((x) >> BIT_SHIFT_NETYPE4_8822B) & BIT_MASK_NETYPE4_8822B) - - +#define BIT_NETYPE4_8822B(x) \ + (((x) & BIT_MASK_NETYPE4_8822B) << BIT_SHIFT_NETYPE4_8822B) +#define BITS_NETYPE4_8822B (BIT_MASK_NETYPE4_8822B << BIT_SHIFT_NETYPE4_8822B) +#define BIT_CLEAR_NETYPE4_8822B(x) ((x) & (~BITS_NETYPE4_8822B)) +#define BIT_GET_NETYPE4_8822B(x) \ + (((x) >> BIT_SHIFT_NETYPE4_8822B) & BIT_MASK_NETYPE4_8822B) +#define BIT_SET_NETYPE4_8822B(x, v) \ + (BIT_CLEAR_NETYPE4_8822B(x) | BIT_NETYPE4_8822B(v)) #define BIT_SHIFT_NETYPE3_8822B 2 #define BIT_MASK_NETYPE3_8822B 0x3 -#define BIT_NETYPE3_8822B(x) (((x) & BIT_MASK_NETYPE3_8822B) << BIT_SHIFT_NETYPE3_8822B) -#define BIT_GET_NETYPE3_8822B(x) (((x) >> BIT_SHIFT_NETYPE3_8822B) & BIT_MASK_NETYPE3_8822B) - - +#define BIT_NETYPE3_8822B(x) \ + (((x) & BIT_MASK_NETYPE3_8822B) << BIT_SHIFT_NETYPE3_8822B) +#define BITS_NETYPE3_8822B (BIT_MASK_NETYPE3_8822B << BIT_SHIFT_NETYPE3_8822B) +#define BIT_CLEAR_NETYPE3_8822B(x) ((x) & (~BITS_NETYPE3_8822B)) +#define BIT_GET_NETYPE3_8822B(x) \ + (((x) >> BIT_SHIFT_NETYPE3_8822B) & BIT_MASK_NETYPE3_8822B) +#define BIT_SET_NETYPE3_8822B(x, v) \ + (BIT_CLEAR_NETYPE3_8822B(x) | BIT_NETYPE3_8822B(v)) #define BIT_SHIFT_NETYPE2_8822B 0 #define BIT_MASK_NETYPE2_8822B 0x3 -#define BIT_NETYPE2_8822B(x) (((x) & BIT_MASK_NETYPE2_8822B) << BIT_SHIFT_NETYPE2_8822B) -#define BIT_GET_NETYPE2_8822B(x) (((x) >> BIT_SHIFT_NETYPE2_8822B) & BIT_MASK_NETYPE2_8822B) - - +#define BIT_NETYPE2_8822B(x) \ + (((x) & BIT_MASK_NETYPE2_8822B) << BIT_SHIFT_NETYPE2_8822B) +#define BITS_NETYPE2_8822B (BIT_MASK_NETYPE2_8822B << BIT_SHIFT_NETYPE2_8822B) +#define BIT_CLEAR_NETYPE2_8822B(x) ((x) & (~BITS_NETYPE2_8822B)) +#define BIT_GET_NETYPE2_8822B(x) \ + (((x) >> BIT_SHIFT_NETYPE2_8822B) & BIT_MASK_NETYPE2_8822B) +#define BIT_SET_NETYPE2_8822B(x, v) \ + (BIT_CLEAR_NETYPE2_8822B(x) | BIT_NETYPE2_8822B(v)) /* 2 REG_FWFF_8822B */ #define BIT_SHIFT_PKTNUM_TH_V1_8822B 24 #define BIT_MASK_PKTNUM_TH_V1_8822B 0xff -#define BIT_PKTNUM_TH_V1_8822B(x) (((x) & BIT_MASK_PKTNUM_TH_V1_8822B) << BIT_SHIFT_PKTNUM_TH_V1_8822B) -#define BIT_GET_PKTNUM_TH_V1_8822B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822B) & BIT_MASK_PKTNUM_TH_V1_8822B) - - +#define BIT_PKTNUM_TH_V1_8822B(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V1_8822B) << BIT_SHIFT_PKTNUM_TH_V1_8822B) +#define BITS_PKTNUM_TH_V1_8822B \ + (BIT_MASK_PKTNUM_TH_V1_8822B << BIT_SHIFT_PKTNUM_TH_V1_8822B) +#define BIT_CLEAR_PKTNUM_TH_V1_8822B(x) ((x) & (~BITS_PKTNUM_TH_V1_8822B)) +#define BIT_GET_PKTNUM_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822B) & BIT_MASK_PKTNUM_TH_V1_8822B) +#define BIT_SET_PKTNUM_TH_V1_8822B(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V1_8822B(x) | BIT_PKTNUM_TH_V1_8822B(v)) #define BIT_SHIFT_TIMER_TH_8822B 16 #define BIT_MASK_TIMER_TH_8822B 0xff -#define BIT_TIMER_TH_8822B(x) (((x) & BIT_MASK_TIMER_TH_8822B) << BIT_SHIFT_TIMER_TH_8822B) -#define BIT_GET_TIMER_TH_8822B(x) (((x) >> BIT_SHIFT_TIMER_TH_8822B) & BIT_MASK_TIMER_TH_8822B) - - +#define BIT_TIMER_TH_8822B(x) \ + (((x) & BIT_MASK_TIMER_TH_8822B) << BIT_SHIFT_TIMER_TH_8822B) +#define BITS_TIMER_TH_8822B \ + (BIT_MASK_TIMER_TH_8822B << BIT_SHIFT_TIMER_TH_8822B) +#define BIT_CLEAR_TIMER_TH_8822B(x) ((x) & (~BITS_TIMER_TH_8822B)) +#define BIT_GET_TIMER_TH_8822B(x) \ + (((x) >> BIT_SHIFT_TIMER_TH_8822B) & BIT_MASK_TIMER_TH_8822B) +#define BIT_SET_TIMER_TH_8822B(x, v) \ + (BIT_CLEAR_TIMER_TH_8822B(x) | BIT_TIMER_TH_8822B(v)) #define BIT_SHIFT_RXPKT1ENADDR_8822B 0 #define BIT_MASK_RXPKT1ENADDR_8822B 0xffff -#define BIT_RXPKT1ENADDR_8822B(x) (((x) & BIT_MASK_RXPKT1ENADDR_8822B) << BIT_SHIFT_RXPKT1ENADDR_8822B) -#define BIT_GET_RXPKT1ENADDR_8822B(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8822B) & BIT_MASK_RXPKT1ENADDR_8822B) - - +#define BIT_RXPKT1ENADDR_8822B(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR_8822B) << BIT_SHIFT_RXPKT1ENADDR_8822B) +#define BITS_RXPKT1ENADDR_8822B \ + (BIT_MASK_RXPKT1ENADDR_8822B << BIT_SHIFT_RXPKT1ENADDR_8822B) +#define BIT_CLEAR_RXPKT1ENADDR_8822B(x) ((x) & (~BITS_RXPKT1ENADDR_8822B)) +#define BIT_GET_RXPKT1ENADDR_8822B(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR_8822B) & BIT_MASK_RXPKT1ENADDR_8822B) +#define BIT_SET_RXPKT1ENADDR_8822B(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR_8822B(x) | BIT_RXPKT1ENADDR_8822B(v)) /* 2 REG_RXFF_PTR_V1_8822B */ @@ -2975,10 +4404,17 @@ #define BIT_SHIFT_RXFF0_RDPTR_V2_8822B 0 #define BIT_MASK_RXFF0_RDPTR_V2_8822B 0x3ffff -#define BIT_RXFF0_RDPTR_V2_8822B(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8822B) << BIT_SHIFT_RXFF0_RDPTR_V2_8822B) -#define BIT_GET_RXFF0_RDPTR_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822B) & BIT_MASK_RXFF0_RDPTR_V2_8822B) - - +#define BIT_RXFF0_RDPTR_V2_8822B(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2_8822B) \ + << BIT_SHIFT_RXFF0_RDPTR_V2_8822B) +#define BITS_RXFF0_RDPTR_V2_8822B \ + (BIT_MASK_RXFF0_RDPTR_V2_8822B << BIT_SHIFT_RXFF0_RDPTR_V2_8822B) +#define BIT_CLEAR_RXFF0_RDPTR_V2_8822B(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8822B)) +#define BIT_GET_RXFF0_RDPTR_V2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822B) & \ + BIT_MASK_RXFF0_RDPTR_V2_8822B) +#define BIT_SET_RXFF0_RDPTR_V2_8822B(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2_8822B(x) | BIT_RXFF0_RDPTR_V2_8822B(v)) /* 2 REG_RXFF_WTR_V1_8822B */ @@ -2986,10 +4422,17 @@ #define BIT_SHIFT_RXFF0_WTPTR_V2_8822B 0 #define BIT_MASK_RXFF0_WTPTR_V2_8822B 0x3ffff -#define BIT_RXFF0_WTPTR_V2_8822B(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8822B) << BIT_SHIFT_RXFF0_WTPTR_V2_8822B) -#define BIT_GET_RXFF0_WTPTR_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822B) & BIT_MASK_RXFF0_WTPTR_V2_8822B) - - +#define BIT_RXFF0_WTPTR_V2_8822B(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2_8822B) \ + << BIT_SHIFT_RXFF0_WTPTR_V2_8822B) +#define BITS_RXFF0_WTPTR_V2_8822B \ + (BIT_MASK_RXFF0_WTPTR_V2_8822B << BIT_SHIFT_RXFF0_WTPTR_V2_8822B) +#define BIT_CLEAR_RXFF0_WTPTR_V2_8822B(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8822B)) +#define BIT_GET_RXFF0_WTPTR_V2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822B) & \ + BIT_MASK_RXFF0_WTPTR_V2_8822B) +#define BIT_SET_RXFF0_WTPTR_V2_8822B(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2_8822B(x) | BIT_RXFF0_WTPTR_V2_8822B(v)) /* 2 REG_FE2IMR_8822B */ #define BIT__FE4ISR__IND_MSK_8822B BIT(29) @@ -3223,53 +4666,82 @@ #define BIT_SHIFT_MID_31TO0_8822B 0 #define BIT_MASK_MID_31TO0_8822B 0xffffffffL -#define BIT_MID_31TO0_8822B(x) (((x) & BIT_MASK_MID_31TO0_8822B) << BIT_SHIFT_MID_31TO0_8822B) -#define BIT_GET_MID_31TO0_8822B(x) (((x) >> BIT_SHIFT_MID_31TO0_8822B) & BIT_MASK_MID_31TO0_8822B) - - +#define BIT_MID_31TO0_8822B(x) \ + (((x) & BIT_MASK_MID_31TO0_8822B) << BIT_SHIFT_MID_31TO0_8822B) +#define BITS_MID_31TO0_8822B \ + (BIT_MASK_MID_31TO0_8822B << BIT_SHIFT_MID_31TO0_8822B) +#define BIT_CLEAR_MID_31TO0_8822B(x) ((x) & (~BITS_MID_31TO0_8822B)) +#define BIT_GET_MID_31TO0_8822B(x) \ + (((x) >> BIT_SHIFT_MID_31TO0_8822B) & BIT_MASK_MID_31TO0_8822B) +#define BIT_SET_MID_31TO0_8822B(x, v) \ + (BIT_CLEAR_MID_31TO0_8822B(x) | BIT_MID_31TO0_8822B(v)) /* 2 REG_SPWR1_8822B */ #define BIT_SHIFT_MID_63TO32_8822B 0 #define BIT_MASK_MID_63TO32_8822B 0xffffffffL -#define BIT_MID_63TO32_8822B(x) (((x) & BIT_MASK_MID_63TO32_8822B) << BIT_SHIFT_MID_63TO32_8822B) -#define BIT_GET_MID_63TO32_8822B(x) (((x) >> BIT_SHIFT_MID_63TO32_8822B) & BIT_MASK_MID_63TO32_8822B) - - +#define BIT_MID_63TO32_8822B(x) \ + (((x) & BIT_MASK_MID_63TO32_8822B) << BIT_SHIFT_MID_63TO32_8822B) +#define BITS_MID_63TO32_8822B \ + (BIT_MASK_MID_63TO32_8822B << BIT_SHIFT_MID_63TO32_8822B) +#define BIT_CLEAR_MID_63TO32_8822B(x) ((x) & (~BITS_MID_63TO32_8822B)) +#define BIT_GET_MID_63TO32_8822B(x) \ + (((x) >> BIT_SHIFT_MID_63TO32_8822B) & BIT_MASK_MID_63TO32_8822B) +#define BIT_SET_MID_63TO32_8822B(x, v) \ + (BIT_CLEAR_MID_63TO32_8822B(x) | BIT_MID_63TO32_8822B(v)) /* 2 REG_SPWR2_8822B */ #define BIT_SHIFT_MID_95O64_8822B 0 #define BIT_MASK_MID_95O64_8822B 0xffffffffL -#define BIT_MID_95O64_8822B(x) (((x) & BIT_MASK_MID_95O64_8822B) << BIT_SHIFT_MID_95O64_8822B) -#define BIT_GET_MID_95O64_8822B(x) (((x) >> BIT_SHIFT_MID_95O64_8822B) & BIT_MASK_MID_95O64_8822B) - - +#define BIT_MID_95O64_8822B(x) \ + (((x) & BIT_MASK_MID_95O64_8822B) << BIT_SHIFT_MID_95O64_8822B) +#define BITS_MID_95O64_8822B \ + (BIT_MASK_MID_95O64_8822B << BIT_SHIFT_MID_95O64_8822B) +#define BIT_CLEAR_MID_95O64_8822B(x) ((x) & (~BITS_MID_95O64_8822B)) +#define BIT_GET_MID_95O64_8822B(x) \ + (((x) >> BIT_SHIFT_MID_95O64_8822B) & BIT_MASK_MID_95O64_8822B) +#define BIT_SET_MID_95O64_8822B(x, v) \ + (BIT_CLEAR_MID_95O64_8822B(x) | BIT_MID_95O64_8822B(v)) /* 2 REG_SPWR3_8822B */ #define BIT_SHIFT_MID_127TO96_8822B 0 #define BIT_MASK_MID_127TO96_8822B 0xffffffffL -#define BIT_MID_127TO96_8822B(x) (((x) & BIT_MASK_MID_127TO96_8822B) << BIT_SHIFT_MID_127TO96_8822B) -#define BIT_GET_MID_127TO96_8822B(x) (((x) >> BIT_SHIFT_MID_127TO96_8822B) & BIT_MASK_MID_127TO96_8822B) - - +#define BIT_MID_127TO96_8822B(x) \ + (((x) & BIT_MASK_MID_127TO96_8822B) << BIT_SHIFT_MID_127TO96_8822B) +#define BITS_MID_127TO96_8822B \ + (BIT_MASK_MID_127TO96_8822B << BIT_SHIFT_MID_127TO96_8822B) +#define BIT_CLEAR_MID_127TO96_8822B(x) ((x) & (~BITS_MID_127TO96_8822B)) +#define BIT_GET_MID_127TO96_8822B(x) \ + (((x) >> BIT_SHIFT_MID_127TO96_8822B) & BIT_MASK_MID_127TO96_8822B) +#define BIT_SET_MID_127TO96_8822B(x, v) \ + (BIT_CLEAR_MID_127TO96_8822B(x) | BIT_MID_127TO96_8822B(v)) /* 2 REG_POWSEQ_8822B */ #define BIT_SHIFT_SEQNUM_MID_8822B 16 #define BIT_MASK_SEQNUM_MID_8822B 0xffff -#define BIT_SEQNUM_MID_8822B(x) (((x) & BIT_MASK_SEQNUM_MID_8822B) << BIT_SHIFT_SEQNUM_MID_8822B) -#define BIT_GET_SEQNUM_MID_8822B(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8822B) & BIT_MASK_SEQNUM_MID_8822B) - - +#define BIT_SEQNUM_MID_8822B(x) \ + (((x) & BIT_MASK_SEQNUM_MID_8822B) << BIT_SHIFT_SEQNUM_MID_8822B) +#define BITS_SEQNUM_MID_8822B \ + (BIT_MASK_SEQNUM_MID_8822B << BIT_SHIFT_SEQNUM_MID_8822B) +#define BIT_CLEAR_SEQNUM_MID_8822B(x) ((x) & (~BITS_SEQNUM_MID_8822B)) +#define BIT_GET_SEQNUM_MID_8822B(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID_8822B) & BIT_MASK_SEQNUM_MID_8822B) +#define BIT_SET_SEQNUM_MID_8822B(x, v) \ + (BIT_CLEAR_SEQNUM_MID_8822B(x) | BIT_SEQNUM_MID_8822B(v)) #define BIT_SHIFT_REF_MID_8822B 0 #define BIT_MASK_REF_MID_8822B 0x7f -#define BIT_REF_MID_8822B(x) (((x) & BIT_MASK_REF_MID_8822B) << BIT_SHIFT_REF_MID_8822B) -#define BIT_GET_REF_MID_8822B(x) (((x) >> BIT_SHIFT_REF_MID_8822B) & BIT_MASK_REF_MID_8822B) - - +#define BIT_REF_MID_8822B(x) \ + (((x) & BIT_MASK_REF_MID_8822B) << BIT_SHIFT_REF_MID_8822B) +#define BITS_REF_MID_8822B (BIT_MASK_REF_MID_8822B << BIT_SHIFT_REF_MID_8822B) +#define BIT_CLEAR_REF_MID_8822B(x) ((x) & (~BITS_REF_MID_8822B)) +#define BIT_GET_REF_MID_8822B(x) \ + (((x) >> BIT_SHIFT_REF_MID_8822B) & BIT_MASK_REF_MID_8822B) +#define BIT_SET_REF_MID_8822B(x, v) \ + (BIT_CLEAR_REF_MID_8822B(x) | BIT_REF_MID_8822B(v)) /* 2 REG_TC7_CTRL_V1_8822B */ #define BIT_TC7INT_EN_8822B BIT(26) @@ -3278,10 +4750,14 @@ #define BIT_SHIFT_TC7DATA_8822B 0 #define BIT_MASK_TC7DATA_8822B 0xffffff -#define BIT_TC7DATA_8822B(x) (((x) & BIT_MASK_TC7DATA_8822B) << BIT_SHIFT_TC7DATA_8822B) -#define BIT_GET_TC7DATA_8822B(x) (((x) >> BIT_SHIFT_TC7DATA_8822B) & BIT_MASK_TC7DATA_8822B) - - +#define BIT_TC7DATA_8822B(x) \ + (((x) & BIT_MASK_TC7DATA_8822B) << BIT_SHIFT_TC7DATA_8822B) +#define BITS_TC7DATA_8822B (BIT_MASK_TC7DATA_8822B << BIT_SHIFT_TC7DATA_8822B) +#define BIT_CLEAR_TC7DATA_8822B(x) ((x) & (~BITS_TC7DATA_8822B)) +#define BIT_GET_TC7DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC7DATA_8822B) & BIT_MASK_TC7DATA_8822B) +#define BIT_SET_TC7DATA_8822B(x, v) \ + (BIT_CLEAR_TC7DATA_8822B(x) | BIT_TC7DATA_8822B(v)) /* 2 REG_TC8_CTRL_V1_8822B */ #define BIT_TC8INT_EN_8822B BIT(26) @@ -3290,10 +4766,14 @@ #define BIT_SHIFT_TC8DATA_8822B 0 #define BIT_MASK_TC8DATA_8822B 0xffffff -#define BIT_TC8DATA_8822B(x) (((x) & BIT_MASK_TC8DATA_8822B) << BIT_SHIFT_TC8DATA_8822B) -#define BIT_GET_TC8DATA_8822B(x) (((x) >> BIT_SHIFT_TC8DATA_8822B) & BIT_MASK_TC8DATA_8822B) - - +#define BIT_TC8DATA_8822B(x) \ + (((x) & BIT_MASK_TC8DATA_8822B) << BIT_SHIFT_TC8DATA_8822B) +#define BITS_TC8DATA_8822B (BIT_MASK_TC8DATA_8822B << BIT_SHIFT_TC8DATA_8822B) +#define BIT_CLEAR_TC8DATA_8822B(x) ((x) & (~BITS_TC8DATA_8822B)) +#define BIT_GET_TC8DATA_8822B(x) \ + (((x) >> BIT_SHIFT_TC8DATA_8822B) & BIT_MASK_TC8DATA_8822B) +#define BIT_SET_TC8DATA_8822B(x, v) \ + (BIT_CLEAR_TC8DATA_8822B(x) | BIT_TC8DATA_8822B(v)) /* 2 REG_FT2IMR_8822B */ #define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822B BIT(31) @@ -3355,37 +4835,53 @@ #define BIT_SHIFT_FW_MSG2_8822B 0 #define BIT_MASK_FW_MSG2_8822B 0xffffffffL -#define BIT_FW_MSG2_8822B(x) (((x) & BIT_MASK_FW_MSG2_8822B) << BIT_SHIFT_FW_MSG2_8822B) -#define BIT_GET_FW_MSG2_8822B(x) (((x) >> BIT_SHIFT_FW_MSG2_8822B) & BIT_MASK_FW_MSG2_8822B) - - +#define BIT_FW_MSG2_8822B(x) \ + (((x) & BIT_MASK_FW_MSG2_8822B) << BIT_SHIFT_FW_MSG2_8822B) +#define BITS_FW_MSG2_8822B (BIT_MASK_FW_MSG2_8822B << BIT_SHIFT_FW_MSG2_8822B) +#define BIT_CLEAR_FW_MSG2_8822B(x) ((x) & (~BITS_FW_MSG2_8822B)) +#define BIT_GET_FW_MSG2_8822B(x) \ + (((x) >> BIT_SHIFT_FW_MSG2_8822B) & BIT_MASK_FW_MSG2_8822B) +#define BIT_SET_FW_MSG2_8822B(x, v) \ + (BIT_CLEAR_FW_MSG2_8822B(x) | BIT_FW_MSG2_8822B(v)) /* 2 REG_MSG3_8822B */ #define BIT_SHIFT_FW_MSG3_8822B 0 #define BIT_MASK_FW_MSG3_8822B 0xffffffffL -#define BIT_FW_MSG3_8822B(x) (((x) & BIT_MASK_FW_MSG3_8822B) << BIT_SHIFT_FW_MSG3_8822B) -#define BIT_GET_FW_MSG3_8822B(x) (((x) >> BIT_SHIFT_FW_MSG3_8822B) & BIT_MASK_FW_MSG3_8822B) - - +#define BIT_FW_MSG3_8822B(x) \ + (((x) & BIT_MASK_FW_MSG3_8822B) << BIT_SHIFT_FW_MSG3_8822B) +#define BITS_FW_MSG3_8822B (BIT_MASK_FW_MSG3_8822B << BIT_SHIFT_FW_MSG3_8822B) +#define BIT_CLEAR_FW_MSG3_8822B(x) ((x) & (~BITS_FW_MSG3_8822B)) +#define BIT_GET_FW_MSG3_8822B(x) \ + (((x) >> BIT_SHIFT_FW_MSG3_8822B) & BIT_MASK_FW_MSG3_8822B) +#define BIT_SET_FW_MSG3_8822B(x, v) \ + (BIT_CLEAR_FW_MSG3_8822B(x) | BIT_FW_MSG3_8822B(v)) /* 2 REG_MSG4_8822B */ #define BIT_SHIFT_FW_MSG4_8822B 0 #define BIT_MASK_FW_MSG4_8822B 0xffffffffL -#define BIT_FW_MSG4_8822B(x) (((x) & BIT_MASK_FW_MSG4_8822B) << BIT_SHIFT_FW_MSG4_8822B) -#define BIT_GET_FW_MSG4_8822B(x) (((x) >> BIT_SHIFT_FW_MSG4_8822B) & BIT_MASK_FW_MSG4_8822B) - - +#define BIT_FW_MSG4_8822B(x) \ + (((x) & BIT_MASK_FW_MSG4_8822B) << BIT_SHIFT_FW_MSG4_8822B) +#define BITS_FW_MSG4_8822B (BIT_MASK_FW_MSG4_8822B << BIT_SHIFT_FW_MSG4_8822B) +#define BIT_CLEAR_FW_MSG4_8822B(x) ((x) & (~BITS_FW_MSG4_8822B)) +#define BIT_GET_FW_MSG4_8822B(x) \ + (((x) >> BIT_SHIFT_FW_MSG4_8822B) & BIT_MASK_FW_MSG4_8822B) +#define BIT_SET_FW_MSG4_8822B(x, v) \ + (BIT_CLEAR_FW_MSG4_8822B(x) | BIT_FW_MSG4_8822B(v)) /* 2 REG_MSG5_8822B */ #define BIT_SHIFT_FW_MSG5_8822B 0 #define BIT_MASK_FW_MSG5_8822B 0xffffffffL -#define BIT_FW_MSG5_8822B(x) (((x) & BIT_MASK_FW_MSG5_8822B) << BIT_SHIFT_FW_MSG5_8822B) -#define BIT_GET_FW_MSG5_8822B(x) (((x) >> BIT_SHIFT_FW_MSG5_8822B) & BIT_MASK_FW_MSG5_8822B) - - +#define BIT_FW_MSG5_8822B(x) \ + (((x) & BIT_MASK_FW_MSG5_8822B) << BIT_SHIFT_FW_MSG5_8822B) +#define BITS_FW_MSG5_8822B (BIT_MASK_FW_MSG5_8822B << BIT_SHIFT_FW_MSG5_8822B) +#define BIT_CLEAR_FW_MSG5_8822B(x) ((x) & (~BITS_FW_MSG5_8822B)) +#define BIT_GET_FW_MSG5_8822B(x) \ + (((x) >> BIT_SHIFT_FW_MSG5_8822B) & BIT_MASK_FW_MSG5_8822B) +#define BIT_SET_FW_MSG5_8822B(x, v) \ + (BIT_CLEAR_FW_MSG5_8822B(x) | BIT_FW_MSG5_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -3393,57 +4889,112 @@ #define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B 16 #define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B 0xff -#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) -#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822B(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) - - +#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) +#define BITS_TX_OQT_HE_FREE_SPACE_V1_8822B \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822B(x) \ + ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8822B)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) +#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8822B(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822B(x) | \ + BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(v)) #define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B 0 #define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B 0xff -#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) -#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822B(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) - - +#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) +#define BITS_TX_OQT_NL_FREE_SPACE_V1_8822B \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822B(x) \ + ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8822B)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) +#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8822B(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822B(x) | \ + BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(v)) /* 2 REG_FIFOPAGE_CTRL_2_8822B */ #define BIT_BCN_VALID_1_V1_8822B BIT(31) #define BIT_SHIFT_BCN_HEAD_1_V1_8822B 16 #define BIT_MASK_BCN_HEAD_1_V1_8822B 0xfff -#define BIT_BCN_HEAD_1_V1_8822B(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8822B) << BIT_SHIFT_BCN_HEAD_1_V1_8822B) -#define BIT_GET_BCN_HEAD_1_V1_8822B(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822B) & BIT_MASK_BCN_HEAD_1_V1_8822B) - +#define BIT_BCN_HEAD_1_V1_8822B(x) \ + (((x) & BIT_MASK_BCN_HEAD_1_V1_8822B) << BIT_SHIFT_BCN_HEAD_1_V1_8822B) +#define BITS_BCN_HEAD_1_V1_8822B \ + (BIT_MASK_BCN_HEAD_1_V1_8822B << BIT_SHIFT_BCN_HEAD_1_V1_8822B) +#define BIT_CLEAR_BCN_HEAD_1_V1_8822B(x) ((x) & (~BITS_BCN_HEAD_1_V1_8822B)) +#define BIT_GET_BCN_HEAD_1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822B) & BIT_MASK_BCN_HEAD_1_V1_8822B) +#define BIT_SET_BCN_HEAD_1_V1_8822B(x, v) \ + (BIT_CLEAR_BCN_HEAD_1_V1_8822B(x) | BIT_BCN_HEAD_1_V1_8822B(v)) #define BIT_BCN_VALID_V1_8822B BIT(15) #define BIT_SHIFT_BCN_HEAD_V1_8822B 0 #define BIT_MASK_BCN_HEAD_V1_8822B 0xfff -#define BIT_BCN_HEAD_V1_8822B(x) (((x) & BIT_MASK_BCN_HEAD_V1_8822B) << BIT_SHIFT_BCN_HEAD_V1_8822B) -#define BIT_GET_BCN_HEAD_V1_8822B(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8822B) & BIT_MASK_BCN_HEAD_V1_8822B) - - +#define BIT_BCN_HEAD_V1_8822B(x) \ + (((x) & BIT_MASK_BCN_HEAD_V1_8822B) << BIT_SHIFT_BCN_HEAD_V1_8822B) +#define BITS_BCN_HEAD_V1_8822B \ + (BIT_MASK_BCN_HEAD_V1_8822B << BIT_SHIFT_BCN_HEAD_V1_8822B) +#define BIT_CLEAR_BCN_HEAD_V1_8822B(x) ((x) & (~BITS_BCN_HEAD_V1_8822B)) +#define BIT_GET_BCN_HEAD_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_V1_8822B) & BIT_MASK_BCN_HEAD_V1_8822B) +#define BIT_SET_BCN_HEAD_V1_8822B(x, v) \ + (BIT_CLEAR_BCN_HEAD_V1_8822B(x) | BIT_BCN_HEAD_V1_8822B(v)) /* 2 REG_AUTO_LLT_V1_8822B */ #define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 24 #define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 0xff -#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) -#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) - - +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) +#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B \ + (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B \ + << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) +#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) \ + ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) & \ + BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) +#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) | \ + BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(v)) #define BIT_SHIFT_LLT_FREE_PAGE_V1_8822B 8 #define BIT_MASK_LLT_FREE_PAGE_V1_8822B 0xffff -#define BIT_LLT_FREE_PAGE_V1_8822B(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8822B) << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) -#define BIT_GET_LLT_FREE_PAGE_V1_8822B(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) & BIT_MASK_LLT_FREE_PAGE_V1_8822B) - - +#define BIT_LLT_FREE_PAGE_V1_8822B(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8822B) \ + << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) +#define BITS_LLT_FREE_PAGE_V1_8822B \ + (BIT_MASK_LLT_FREE_PAGE_V1_8822B << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) +#define BIT_CLEAR_LLT_FREE_PAGE_V1_8822B(x) \ + ((x) & (~BITS_LLT_FREE_PAGE_V1_8822B)) +#define BIT_GET_LLT_FREE_PAGE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) & \ + BIT_MASK_LLT_FREE_PAGE_V1_8822B) +#define BIT_SET_LLT_FREE_PAGE_V1_8822B(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V1_8822B(x) | BIT_LLT_FREE_PAGE_V1_8822B(v)) #define BIT_SHIFT_BLK_DESC_NUM_8822B 4 #define BIT_MASK_BLK_DESC_NUM_8822B 0xf -#define BIT_BLK_DESC_NUM_8822B(x) (((x) & BIT_MASK_BLK_DESC_NUM_8822B) << BIT_SHIFT_BLK_DESC_NUM_8822B) -#define BIT_GET_BLK_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8822B) & BIT_MASK_BLK_DESC_NUM_8822B) - +#define BIT_BLK_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM_8822B) << BIT_SHIFT_BLK_DESC_NUM_8822B) +#define BITS_BLK_DESC_NUM_8822B \ + (BIT_MASK_BLK_DESC_NUM_8822B << BIT_SHIFT_BLK_DESC_NUM_8822B) +#define BIT_CLEAR_BLK_DESC_NUM_8822B(x) ((x) & (~BITS_BLK_DESC_NUM_8822B)) +#define BIT_GET_BLK_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM_8822B) & BIT_MASK_BLK_DESC_NUM_8822B) +#define BIT_SET_BLK_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM_8822B(x) | BIT_BLK_DESC_NUM_8822B(v)) #define BIT_R_BCN_HEAD_SEL_8822B BIT(3) #define BIT_R_EN_BCN_SW_HEAD_SEL_8822B BIT(2) @@ -3458,9 +5009,17 @@ #define BIT_SHIFT_PG_UNDER_TH_V1_8822B 16 #define BIT_MASK_PG_UNDER_TH_V1_8822B 0xfff -#define BIT_PG_UNDER_TH_V1_8822B(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8822B) << BIT_SHIFT_PG_UNDER_TH_V1_8822B) -#define BIT_GET_PG_UNDER_TH_V1_8822B(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822B) & BIT_MASK_PG_UNDER_TH_V1_8822B) - +#define BIT_PG_UNDER_TH_V1_8822B(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1_8822B) \ + << BIT_SHIFT_PG_UNDER_TH_V1_8822B) +#define BITS_PG_UNDER_TH_V1_8822B \ + (BIT_MASK_PG_UNDER_TH_V1_8822B << BIT_SHIFT_PG_UNDER_TH_V1_8822B) +#define BIT_CLEAR_PG_UNDER_TH_V1_8822B(x) ((x) & (~BITS_PG_UNDER_TH_V1_8822B)) +#define BIT_GET_PG_UNDER_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822B) & \ + BIT_MASK_PG_UNDER_TH_V1_8822B) +#define BIT_SET_PG_UNDER_TH_V1_8822B(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1_8822B(x) | BIT_PG_UNDER_TH_V1_8822B(v)) #define BIT_RESTORE_H2C_ADDRESS_8822B BIT(15) #define BIT_SDIO_TXDESC_CHKSUM_EN_8822B BIT(13) @@ -3472,10 +5031,15 @@ #define BIT_SHIFT_CHECK_OFFSET_8822B 0 #define BIT_MASK_CHECK_OFFSET_8822B 0xff -#define BIT_CHECK_OFFSET_8822B(x) (((x) & BIT_MASK_CHECK_OFFSET_8822B) << BIT_SHIFT_CHECK_OFFSET_8822B) -#define BIT_GET_CHECK_OFFSET_8822B(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8822B) & BIT_MASK_CHECK_OFFSET_8822B) - - +#define BIT_CHECK_OFFSET_8822B(x) \ + (((x) & BIT_MASK_CHECK_OFFSET_8822B) << BIT_SHIFT_CHECK_OFFSET_8822B) +#define BITS_CHECK_OFFSET_8822B \ + (BIT_MASK_CHECK_OFFSET_8822B << BIT_SHIFT_CHECK_OFFSET_8822B) +#define BIT_CLEAR_CHECK_OFFSET_8822B(x) ((x) & (~BITS_CHECK_OFFSET_8822B)) +#define BIT_GET_CHECK_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET_8822B) & BIT_MASK_CHECK_OFFSET_8822B) +#define BIT_SET_CHECK_OFFSET_8822B(x, v) \ + (BIT_CLEAR_CHECK_OFFSET_8822B(x) | BIT_CHECK_OFFSET_8822B(v)) /* 2 REG_TXDMA_STATUS_8822B */ #define BIT_HI_OQT_UDN_8822B BIT(17) @@ -3503,81 +5067,139 @@ #define BIT_SHIFT_HPQ_HIGH_TH_V1_8822B 16 #define BIT_MASK_HPQ_HIGH_TH_V1_8822B 0xfff -#define BIT_HPQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822B) << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) -#define BIT_GET_HPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) & BIT_MASK_HPQ_HIGH_TH_V1_8822B) - - +#define BIT_HPQ_HIGH_TH_V1_8822B(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822B) \ + << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) +#define BITS_HPQ_HIGH_TH_V1_8822B \ + (BIT_MASK_HPQ_HIGH_TH_V1_8822B << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) +#define BIT_CLEAR_HPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8822B)) +#define BIT_GET_HPQ_HIGH_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) & \ + BIT_MASK_HPQ_HIGH_TH_V1_8822B) +#define BIT_SET_HPQ_HIGH_TH_V1_8822B(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH_V1_8822B(x) | BIT_HPQ_HIGH_TH_V1_8822B(v)) #define BIT_SHIFT_HPQ_LOW_TH_V1_8822B 0 #define BIT_MASK_HPQ_LOW_TH_V1_8822B 0xfff -#define BIT_HPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8822B) << BIT_SHIFT_HPQ_LOW_TH_V1_8822B) -#define BIT_GET_HPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822B) & BIT_MASK_HPQ_LOW_TH_V1_8822B) - - +#define BIT_HPQ_LOW_TH_V1_8822B(x) \ + (((x) & BIT_MASK_HPQ_LOW_TH_V1_8822B) << BIT_SHIFT_HPQ_LOW_TH_V1_8822B) +#define BITS_HPQ_LOW_TH_V1_8822B \ + (BIT_MASK_HPQ_LOW_TH_V1_8822B << BIT_SHIFT_HPQ_LOW_TH_V1_8822B) +#define BIT_CLEAR_HPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8822B)) +#define BIT_GET_HPQ_LOW_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822B) & BIT_MASK_HPQ_LOW_TH_V1_8822B) +#define BIT_SET_HPQ_LOW_TH_V1_8822B(x, v) \ + (BIT_CLEAR_HPQ_LOW_TH_V1_8822B(x) | BIT_HPQ_LOW_TH_V1_8822B(v)) /* 2 REG_TQPNT2_8822B */ #define BIT_SHIFT_NPQ_HIGH_TH_V1_8822B 16 #define BIT_MASK_NPQ_HIGH_TH_V1_8822B 0xfff -#define BIT_NPQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822B) << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) -#define BIT_GET_NPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) & BIT_MASK_NPQ_HIGH_TH_V1_8822B) - - +#define BIT_NPQ_HIGH_TH_V1_8822B(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822B) \ + << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) +#define BITS_NPQ_HIGH_TH_V1_8822B \ + (BIT_MASK_NPQ_HIGH_TH_V1_8822B << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) +#define BIT_CLEAR_NPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8822B)) +#define BIT_GET_NPQ_HIGH_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) & \ + BIT_MASK_NPQ_HIGH_TH_V1_8822B) +#define BIT_SET_NPQ_HIGH_TH_V1_8822B(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH_V1_8822B(x) | BIT_NPQ_HIGH_TH_V1_8822B(v)) #define BIT_SHIFT_NPQ_LOW_TH_V1_8822B 0 #define BIT_MASK_NPQ_LOW_TH_V1_8822B 0xfff -#define BIT_NPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8822B) << BIT_SHIFT_NPQ_LOW_TH_V1_8822B) -#define BIT_GET_NPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822B) & BIT_MASK_NPQ_LOW_TH_V1_8822B) - - +#define BIT_NPQ_LOW_TH_V1_8822B(x) \ + (((x) & BIT_MASK_NPQ_LOW_TH_V1_8822B) << BIT_SHIFT_NPQ_LOW_TH_V1_8822B) +#define BITS_NPQ_LOW_TH_V1_8822B \ + (BIT_MASK_NPQ_LOW_TH_V1_8822B << BIT_SHIFT_NPQ_LOW_TH_V1_8822B) +#define BIT_CLEAR_NPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8822B)) +#define BIT_GET_NPQ_LOW_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822B) & BIT_MASK_NPQ_LOW_TH_V1_8822B) +#define BIT_SET_NPQ_LOW_TH_V1_8822B(x, v) \ + (BIT_CLEAR_NPQ_LOW_TH_V1_8822B(x) | BIT_NPQ_LOW_TH_V1_8822B(v)) /* 2 REG_TQPNT3_8822B */ #define BIT_SHIFT_LPQ_HIGH_TH_V1_8822B 16 #define BIT_MASK_LPQ_HIGH_TH_V1_8822B 0xfff -#define BIT_LPQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822B) << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) -#define BIT_GET_LPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) & BIT_MASK_LPQ_HIGH_TH_V1_8822B) - - +#define BIT_LPQ_HIGH_TH_V1_8822B(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822B) \ + << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) +#define BITS_LPQ_HIGH_TH_V1_8822B \ + (BIT_MASK_LPQ_HIGH_TH_V1_8822B << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) +#define BIT_CLEAR_LPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8822B)) +#define BIT_GET_LPQ_HIGH_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) & \ + BIT_MASK_LPQ_HIGH_TH_V1_8822B) +#define BIT_SET_LPQ_HIGH_TH_V1_8822B(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH_V1_8822B(x) | BIT_LPQ_HIGH_TH_V1_8822B(v)) #define BIT_SHIFT_LPQ_LOW_TH_V1_8822B 0 #define BIT_MASK_LPQ_LOW_TH_V1_8822B 0xfff -#define BIT_LPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8822B) << BIT_SHIFT_LPQ_LOW_TH_V1_8822B) -#define BIT_GET_LPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822B) & BIT_MASK_LPQ_LOW_TH_V1_8822B) - - +#define BIT_LPQ_LOW_TH_V1_8822B(x) \ + (((x) & BIT_MASK_LPQ_LOW_TH_V1_8822B) << BIT_SHIFT_LPQ_LOW_TH_V1_8822B) +#define BITS_LPQ_LOW_TH_V1_8822B \ + (BIT_MASK_LPQ_LOW_TH_V1_8822B << BIT_SHIFT_LPQ_LOW_TH_V1_8822B) +#define BIT_CLEAR_LPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8822B)) +#define BIT_GET_LPQ_LOW_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822B) & BIT_MASK_LPQ_LOW_TH_V1_8822B) +#define BIT_SET_LPQ_LOW_TH_V1_8822B(x, v) \ + (BIT_CLEAR_LPQ_LOW_TH_V1_8822B(x) | BIT_LPQ_LOW_TH_V1_8822B(v)) /* 2 REG_TQPNT4_8822B */ #define BIT_SHIFT_EXQ_HIGH_TH_V1_8822B 16 #define BIT_MASK_EXQ_HIGH_TH_V1_8822B 0xfff -#define BIT_EXQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822B) << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) -#define BIT_GET_EXQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) & BIT_MASK_EXQ_HIGH_TH_V1_8822B) - - +#define BIT_EXQ_HIGH_TH_V1_8822B(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822B) \ + << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) +#define BITS_EXQ_HIGH_TH_V1_8822B \ + (BIT_MASK_EXQ_HIGH_TH_V1_8822B << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) +#define BIT_CLEAR_EXQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8822B)) +#define BIT_GET_EXQ_HIGH_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) & \ + BIT_MASK_EXQ_HIGH_TH_V1_8822B) +#define BIT_SET_EXQ_HIGH_TH_V1_8822B(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH_V1_8822B(x) | BIT_EXQ_HIGH_TH_V1_8822B(v)) #define BIT_SHIFT_EXQ_LOW_TH_V1_8822B 0 #define BIT_MASK_EXQ_LOW_TH_V1_8822B 0xfff -#define BIT_EXQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8822B) << BIT_SHIFT_EXQ_LOW_TH_V1_8822B) -#define BIT_GET_EXQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822B) & BIT_MASK_EXQ_LOW_TH_V1_8822B) - - +#define BIT_EXQ_LOW_TH_V1_8822B(x) \ + (((x) & BIT_MASK_EXQ_LOW_TH_V1_8822B) << BIT_SHIFT_EXQ_LOW_TH_V1_8822B) +#define BITS_EXQ_LOW_TH_V1_8822B \ + (BIT_MASK_EXQ_LOW_TH_V1_8822B << BIT_SHIFT_EXQ_LOW_TH_V1_8822B) +#define BIT_CLEAR_EXQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8822B)) +#define BIT_GET_EXQ_LOW_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822B) & BIT_MASK_EXQ_LOW_TH_V1_8822B) +#define BIT_SET_EXQ_LOW_TH_V1_8822B(x, v) \ + (BIT_CLEAR_EXQ_LOW_TH_V1_8822B(x) | BIT_EXQ_LOW_TH_V1_8822B(v)) /* 2 REG_RQPN_CTRL_1_8822B */ #define BIT_SHIFT_TXPKTNUM_H_8822B 16 #define BIT_MASK_TXPKTNUM_H_8822B 0xffff -#define BIT_TXPKTNUM_H_8822B(x) (((x) & BIT_MASK_TXPKTNUM_H_8822B) << BIT_SHIFT_TXPKTNUM_H_8822B) -#define BIT_GET_TXPKTNUM_H_8822B(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8822B) & BIT_MASK_TXPKTNUM_H_8822B) - - +#define BIT_TXPKTNUM_H_8822B(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_8822B) << BIT_SHIFT_TXPKTNUM_H_8822B) +#define BITS_TXPKTNUM_H_8822B \ + (BIT_MASK_TXPKTNUM_H_8822B << BIT_SHIFT_TXPKTNUM_H_8822B) +#define BIT_CLEAR_TXPKTNUM_H_8822B(x) ((x) & (~BITS_TXPKTNUM_H_8822B)) +#define BIT_GET_TXPKTNUM_H_8822B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_8822B) & BIT_MASK_TXPKTNUM_H_8822B) +#define BIT_SET_TXPKTNUM_H_8822B(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_8822B(x) | BIT_TXPKTNUM_H_8822B(v)) #define BIT_SHIFT_TXPKTNUM_V2_8822B 0 #define BIT_MASK_TXPKTNUM_V2_8822B 0xffff -#define BIT_TXPKTNUM_V2_8822B(x) (((x) & BIT_MASK_TXPKTNUM_V2_8822B) << BIT_SHIFT_TXPKTNUM_V2_8822B) -#define BIT_GET_TXPKTNUM_V2_8822B(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8822B) & BIT_MASK_TXPKTNUM_V2_8822B) - - +#define BIT_TXPKTNUM_V2_8822B(x) \ + (((x) & BIT_MASK_TXPKTNUM_V2_8822B) << BIT_SHIFT_TXPKTNUM_V2_8822B) +#define BITS_TXPKTNUM_V2_8822B \ + (BIT_MASK_TXPKTNUM_V2_8822B << BIT_SHIFT_TXPKTNUM_V2_8822B) +#define BIT_CLEAR_TXPKTNUM_V2_8822B(x) ((x) & (~BITS_TXPKTNUM_V2_8822B)) +#define BIT_GET_TXPKTNUM_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V2_8822B) & BIT_MASK_TXPKTNUM_V2_8822B) +#define BIT_SET_TXPKTNUM_V2_8822B(x, v) \ + (BIT_CLEAR_TXPKTNUM_V2_8822B(x) | BIT_TXPKTNUM_V2_8822B(v)) /* 2 REG_RQPN_CTRL_2_8822B */ #define BIT_LD_RQPN_8822B BIT(31) @@ -3590,117 +5212,192 @@ #define BIT_SHIFT_HPQ_AVAL_PG_V1_8822B 16 #define BIT_MASK_HPQ_AVAL_PG_V1_8822B 0xfff -#define BIT_HPQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822B) << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) -#define BIT_GET_HPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) & BIT_MASK_HPQ_AVAL_PG_V1_8822B) - - +#define BIT_HPQ_AVAL_PG_V1_8822B(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822B) \ + << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) +#define BITS_HPQ_AVAL_PG_V1_8822B \ + (BIT_MASK_HPQ_AVAL_PG_V1_8822B << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) +#define BIT_CLEAR_HPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8822B)) +#define BIT_GET_HPQ_AVAL_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) & \ + BIT_MASK_HPQ_AVAL_PG_V1_8822B) +#define BIT_SET_HPQ_AVAL_PG_V1_8822B(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG_V1_8822B(x) | BIT_HPQ_AVAL_PG_V1_8822B(v)) #define BIT_SHIFT_HPQ_V1_8822B 0 #define BIT_MASK_HPQ_V1_8822B 0xfff -#define BIT_HPQ_V1_8822B(x) (((x) & BIT_MASK_HPQ_V1_8822B) << BIT_SHIFT_HPQ_V1_8822B) -#define BIT_GET_HPQ_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_V1_8822B) & BIT_MASK_HPQ_V1_8822B) - - +#define BIT_HPQ_V1_8822B(x) \ + (((x) & BIT_MASK_HPQ_V1_8822B) << BIT_SHIFT_HPQ_V1_8822B) +#define BITS_HPQ_V1_8822B (BIT_MASK_HPQ_V1_8822B << BIT_SHIFT_HPQ_V1_8822B) +#define BIT_CLEAR_HPQ_V1_8822B(x) ((x) & (~BITS_HPQ_V1_8822B)) +#define BIT_GET_HPQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HPQ_V1_8822B) & BIT_MASK_HPQ_V1_8822B) +#define BIT_SET_HPQ_V1_8822B(x, v) \ + (BIT_CLEAR_HPQ_V1_8822B(x) | BIT_HPQ_V1_8822B(v)) /* 2 REG_FIFOPAGE_INFO_2_8822B */ #define BIT_SHIFT_LPQ_AVAL_PG_V1_8822B 16 #define BIT_MASK_LPQ_AVAL_PG_V1_8822B 0xfff -#define BIT_LPQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822B) << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) -#define BIT_GET_LPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) & BIT_MASK_LPQ_AVAL_PG_V1_8822B) - - +#define BIT_LPQ_AVAL_PG_V1_8822B(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822B) \ + << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) +#define BITS_LPQ_AVAL_PG_V1_8822B \ + (BIT_MASK_LPQ_AVAL_PG_V1_8822B << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) +#define BIT_CLEAR_LPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8822B)) +#define BIT_GET_LPQ_AVAL_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) & \ + BIT_MASK_LPQ_AVAL_PG_V1_8822B) +#define BIT_SET_LPQ_AVAL_PG_V1_8822B(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG_V1_8822B(x) | BIT_LPQ_AVAL_PG_V1_8822B(v)) #define BIT_SHIFT_LPQ_V1_8822B 0 #define BIT_MASK_LPQ_V1_8822B 0xfff -#define BIT_LPQ_V1_8822B(x) (((x) & BIT_MASK_LPQ_V1_8822B) << BIT_SHIFT_LPQ_V1_8822B) -#define BIT_GET_LPQ_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_V1_8822B) & BIT_MASK_LPQ_V1_8822B) - - +#define BIT_LPQ_V1_8822B(x) \ + (((x) & BIT_MASK_LPQ_V1_8822B) << BIT_SHIFT_LPQ_V1_8822B) +#define BITS_LPQ_V1_8822B (BIT_MASK_LPQ_V1_8822B << BIT_SHIFT_LPQ_V1_8822B) +#define BIT_CLEAR_LPQ_V1_8822B(x) ((x) & (~BITS_LPQ_V1_8822B)) +#define BIT_GET_LPQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LPQ_V1_8822B) & BIT_MASK_LPQ_V1_8822B) +#define BIT_SET_LPQ_V1_8822B(x, v) \ + (BIT_CLEAR_LPQ_V1_8822B(x) | BIT_LPQ_V1_8822B(v)) /* 2 REG_FIFOPAGE_INFO_3_8822B */ #define BIT_SHIFT_NPQ_AVAL_PG_V1_8822B 16 #define BIT_MASK_NPQ_AVAL_PG_V1_8822B 0xfff -#define BIT_NPQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822B) << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) -#define BIT_GET_NPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) & BIT_MASK_NPQ_AVAL_PG_V1_8822B) - - +#define BIT_NPQ_AVAL_PG_V1_8822B(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822B) \ + << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) +#define BITS_NPQ_AVAL_PG_V1_8822B \ + (BIT_MASK_NPQ_AVAL_PG_V1_8822B << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) +#define BIT_CLEAR_NPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8822B)) +#define BIT_GET_NPQ_AVAL_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) & \ + BIT_MASK_NPQ_AVAL_PG_V1_8822B) +#define BIT_SET_NPQ_AVAL_PG_V1_8822B(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG_V1_8822B(x) | BIT_NPQ_AVAL_PG_V1_8822B(v)) #define BIT_SHIFT_NPQ_V1_8822B 0 #define BIT_MASK_NPQ_V1_8822B 0xfff -#define BIT_NPQ_V1_8822B(x) (((x) & BIT_MASK_NPQ_V1_8822B) << BIT_SHIFT_NPQ_V1_8822B) -#define BIT_GET_NPQ_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_V1_8822B) & BIT_MASK_NPQ_V1_8822B) - - +#define BIT_NPQ_V1_8822B(x) \ + (((x) & BIT_MASK_NPQ_V1_8822B) << BIT_SHIFT_NPQ_V1_8822B) +#define BITS_NPQ_V1_8822B (BIT_MASK_NPQ_V1_8822B << BIT_SHIFT_NPQ_V1_8822B) +#define BIT_CLEAR_NPQ_V1_8822B(x) ((x) & (~BITS_NPQ_V1_8822B)) +#define BIT_GET_NPQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_NPQ_V1_8822B) & BIT_MASK_NPQ_V1_8822B) +#define BIT_SET_NPQ_V1_8822B(x, v) \ + (BIT_CLEAR_NPQ_V1_8822B(x) | BIT_NPQ_V1_8822B(v)) /* 2 REG_FIFOPAGE_INFO_4_8822B */ #define BIT_SHIFT_EXQ_AVAL_PG_V1_8822B 16 #define BIT_MASK_EXQ_AVAL_PG_V1_8822B 0xfff -#define BIT_EXQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822B) << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) -#define BIT_GET_EXQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) & BIT_MASK_EXQ_AVAL_PG_V1_8822B) - - +#define BIT_EXQ_AVAL_PG_V1_8822B(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822B) \ + << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) +#define BITS_EXQ_AVAL_PG_V1_8822B \ + (BIT_MASK_EXQ_AVAL_PG_V1_8822B << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) +#define BIT_CLEAR_EXQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8822B)) +#define BIT_GET_EXQ_AVAL_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) & \ + BIT_MASK_EXQ_AVAL_PG_V1_8822B) +#define BIT_SET_EXQ_AVAL_PG_V1_8822B(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG_V1_8822B(x) | BIT_EXQ_AVAL_PG_V1_8822B(v)) #define BIT_SHIFT_EXQ_V1_8822B 0 #define BIT_MASK_EXQ_V1_8822B 0xfff -#define BIT_EXQ_V1_8822B(x) (((x) & BIT_MASK_EXQ_V1_8822B) << BIT_SHIFT_EXQ_V1_8822B) -#define BIT_GET_EXQ_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_V1_8822B) & BIT_MASK_EXQ_V1_8822B) - - +#define BIT_EXQ_V1_8822B(x) \ + (((x) & BIT_MASK_EXQ_V1_8822B) << BIT_SHIFT_EXQ_V1_8822B) +#define BITS_EXQ_V1_8822B (BIT_MASK_EXQ_V1_8822B << BIT_SHIFT_EXQ_V1_8822B) +#define BIT_CLEAR_EXQ_V1_8822B(x) ((x) & (~BITS_EXQ_V1_8822B)) +#define BIT_GET_EXQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EXQ_V1_8822B) & BIT_MASK_EXQ_V1_8822B) +#define BIT_SET_EXQ_V1_8822B(x, v) \ + (BIT_CLEAR_EXQ_V1_8822B(x) | BIT_EXQ_V1_8822B(v)) /* 2 REG_FIFOPAGE_INFO_5_8822B */ #define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B 16 #define BIT_MASK_PUBQ_AVAL_PG_V1_8822B 0xfff -#define BIT_PUBQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) -#define BIT_GET_PUBQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B) - - +#define BIT_PUBQ_AVAL_PG_V1_8822B(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B) \ + << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) +#define BITS_PUBQ_AVAL_PG_V1_8822B \ + (BIT_MASK_PUBQ_AVAL_PG_V1_8822B << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) +#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8822B)) +#define BIT_GET_PUBQ_AVAL_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) & \ + BIT_MASK_PUBQ_AVAL_PG_V1_8822B) +#define BIT_SET_PUBQ_AVAL_PG_V1_8822B(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG_V1_8822B(x) | BIT_PUBQ_AVAL_PG_V1_8822B(v)) #define BIT_SHIFT_PUBQ_V1_8822B 0 #define BIT_MASK_PUBQ_V1_8822B 0xfff -#define BIT_PUBQ_V1_8822B(x) (((x) & BIT_MASK_PUBQ_V1_8822B) << BIT_SHIFT_PUBQ_V1_8822B) -#define BIT_GET_PUBQ_V1_8822B(x) (((x) >> BIT_SHIFT_PUBQ_V1_8822B) & BIT_MASK_PUBQ_V1_8822B) - - +#define BIT_PUBQ_V1_8822B(x) \ + (((x) & BIT_MASK_PUBQ_V1_8822B) << BIT_SHIFT_PUBQ_V1_8822B) +#define BITS_PUBQ_V1_8822B (BIT_MASK_PUBQ_V1_8822B << BIT_SHIFT_PUBQ_V1_8822B) +#define BIT_CLEAR_PUBQ_V1_8822B(x) ((x) & (~BITS_PUBQ_V1_8822B)) +#define BIT_GET_PUBQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PUBQ_V1_8822B) & BIT_MASK_PUBQ_V1_8822B) +#define BIT_SET_PUBQ_V1_8822B(x, v) \ + (BIT_CLEAR_PUBQ_V1_8822B(x) | BIT_PUBQ_V1_8822B(v)) /* 2 REG_H2C_HEAD_8822B */ #define BIT_SHIFT_H2C_HEAD_8822B 0 #define BIT_MASK_H2C_HEAD_8822B 0x3ffff -#define BIT_H2C_HEAD_8822B(x) (((x) & BIT_MASK_H2C_HEAD_8822B) << BIT_SHIFT_H2C_HEAD_8822B) -#define BIT_GET_H2C_HEAD_8822B(x) (((x) >> BIT_SHIFT_H2C_HEAD_8822B) & BIT_MASK_H2C_HEAD_8822B) - - +#define BIT_H2C_HEAD_8822B(x) \ + (((x) & BIT_MASK_H2C_HEAD_8822B) << BIT_SHIFT_H2C_HEAD_8822B) +#define BITS_H2C_HEAD_8822B \ + (BIT_MASK_H2C_HEAD_8822B << BIT_SHIFT_H2C_HEAD_8822B) +#define BIT_CLEAR_H2C_HEAD_8822B(x) ((x) & (~BITS_H2C_HEAD_8822B)) +#define BIT_GET_H2C_HEAD_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_8822B) & BIT_MASK_H2C_HEAD_8822B) +#define BIT_SET_H2C_HEAD_8822B(x, v) \ + (BIT_CLEAR_H2C_HEAD_8822B(x) | BIT_H2C_HEAD_8822B(v)) /* 2 REG_H2C_TAIL_8822B */ #define BIT_SHIFT_H2C_TAIL_8822B 0 #define BIT_MASK_H2C_TAIL_8822B 0x3ffff -#define BIT_H2C_TAIL_8822B(x) (((x) & BIT_MASK_H2C_TAIL_8822B) << BIT_SHIFT_H2C_TAIL_8822B) -#define BIT_GET_H2C_TAIL_8822B(x) (((x) >> BIT_SHIFT_H2C_TAIL_8822B) & BIT_MASK_H2C_TAIL_8822B) - - +#define BIT_H2C_TAIL_8822B(x) \ + (((x) & BIT_MASK_H2C_TAIL_8822B) << BIT_SHIFT_H2C_TAIL_8822B) +#define BITS_H2C_TAIL_8822B \ + (BIT_MASK_H2C_TAIL_8822B << BIT_SHIFT_H2C_TAIL_8822B) +#define BIT_CLEAR_H2C_TAIL_8822B(x) ((x) & (~BITS_H2C_TAIL_8822B)) +#define BIT_GET_H2C_TAIL_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_8822B) & BIT_MASK_H2C_TAIL_8822B) +#define BIT_SET_H2C_TAIL_8822B(x, v) \ + (BIT_CLEAR_H2C_TAIL_8822B(x) | BIT_H2C_TAIL_8822B(v)) /* 2 REG_H2C_READ_ADDR_8822B */ #define BIT_SHIFT_H2C_READ_ADDR_8822B 0 #define BIT_MASK_H2C_READ_ADDR_8822B 0x3ffff -#define BIT_H2C_READ_ADDR_8822B(x) (((x) & BIT_MASK_H2C_READ_ADDR_8822B) << BIT_SHIFT_H2C_READ_ADDR_8822B) -#define BIT_GET_H2C_READ_ADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8822B) & BIT_MASK_H2C_READ_ADDR_8822B) +#define BIT_H2C_READ_ADDR_8822B(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_8822B) << BIT_SHIFT_H2C_READ_ADDR_8822B) +#define BITS_H2C_READ_ADDR_8822B \ + (BIT_MASK_H2C_READ_ADDR_8822B << BIT_SHIFT_H2C_READ_ADDR_8822B) +#define BIT_CLEAR_H2C_READ_ADDR_8822B(x) ((x) & (~BITS_H2C_READ_ADDR_8822B)) +#define BIT_GET_H2C_READ_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_8822B) & BIT_MASK_H2C_READ_ADDR_8822B) +#define BIT_SET_H2C_READ_ADDR_8822B(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_8822B(x) | BIT_H2C_READ_ADDR_8822B(v)) - - -/* 2 REG_H2C_WR_ADDR_8822B */ +/* 2 REG_H2C_WR_ADDR_8822B */ #define BIT_SHIFT_H2C_WR_ADDR_8822B 0 #define BIT_MASK_H2C_WR_ADDR_8822B 0x3ffff -#define BIT_H2C_WR_ADDR_8822B(x) (((x) & BIT_MASK_H2C_WR_ADDR_8822B) << BIT_SHIFT_H2C_WR_ADDR_8822B) -#define BIT_GET_H2C_WR_ADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8822B) & BIT_MASK_H2C_WR_ADDR_8822B) - - +#define BIT_H2C_WR_ADDR_8822B(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_8822B) << BIT_SHIFT_H2C_WR_ADDR_8822B) +#define BITS_H2C_WR_ADDR_8822B \ + (BIT_MASK_H2C_WR_ADDR_8822B << BIT_SHIFT_H2C_WR_ADDR_8822B) +#define BIT_CLEAR_H2C_WR_ADDR_8822B(x) ((x) & (~BITS_H2C_WR_ADDR_8822B)) +#define BIT_GET_H2C_WR_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_8822B) & BIT_MASK_H2C_WR_ADDR_8822B) +#define BIT_SET_H2C_WR_ADDR_8822B(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_8822B(x) | BIT_H2C_WR_ADDR_8822B(v)) /* 2 REG_H2C_INFO_8822B */ #define BIT_H2C_SPACE_VLD_8822B BIT(3) @@ -3708,55 +5405,90 @@ #define BIT_SHIFT_H2C_LEN_SEL_8822B 0 #define BIT_MASK_H2C_LEN_SEL_8822B 0x3 -#define BIT_H2C_LEN_SEL_8822B(x) (((x) & BIT_MASK_H2C_LEN_SEL_8822B) << BIT_SHIFT_H2C_LEN_SEL_8822B) -#define BIT_GET_H2C_LEN_SEL_8822B(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8822B) & BIT_MASK_H2C_LEN_SEL_8822B) - - +#define BIT_H2C_LEN_SEL_8822B(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL_8822B) << BIT_SHIFT_H2C_LEN_SEL_8822B) +#define BITS_H2C_LEN_SEL_8822B \ + (BIT_MASK_H2C_LEN_SEL_8822B << BIT_SHIFT_H2C_LEN_SEL_8822B) +#define BIT_CLEAR_H2C_LEN_SEL_8822B(x) ((x) & (~BITS_H2C_LEN_SEL_8822B)) +#define BIT_GET_H2C_LEN_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL_8822B) & BIT_MASK_H2C_LEN_SEL_8822B) +#define BIT_SET_H2C_LEN_SEL_8822B(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL_8822B(x) | BIT_H2C_LEN_SEL_8822B(v)) /* 2 REG_RXDMA_AGG_PG_TH_8822B */ - -#define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B 24 -#define BIT_MASK_RXDMA_AGG_OLD_MOD_8822B 0xff -#define BIT_RXDMA_AGG_OLD_MOD_8822B(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD_8822B) << BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B) -#define BIT_GET_RXDMA_AGG_OLD_MOD_8822B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B) & BIT_MASK_RXDMA_AGG_OLD_MOD_8822B) - - +#define BIT_USB_RXDMA_AGG_EN_8822B BIT(31) +#define BIT_EN_PRE_CALC_8822B BIT(29) +#define BIT_RXAGG_SW_EN_8822B BIT(28) +#define BIT_RXAGG_SW_TRIG_8822B BIT(27) #define BIT_SHIFT_PKT_NUM_WOL_8822B 16 #define BIT_MASK_PKT_NUM_WOL_8822B 0xff -#define BIT_PKT_NUM_WOL_8822B(x) (((x) & BIT_MASK_PKT_NUM_WOL_8822B) << BIT_SHIFT_PKT_NUM_WOL_8822B) -#define BIT_GET_PKT_NUM_WOL_8822B(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8822B) & BIT_MASK_PKT_NUM_WOL_8822B) - - - -#define BIT_SHIFT_DMA_AGG_TO_8822B 8 -#define BIT_MASK_DMA_AGG_TO_8822B 0xf -#define BIT_DMA_AGG_TO_8822B(x) (((x) & BIT_MASK_DMA_AGG_TO_8822B) << BIT_SHIFT_DMA_AGG_TO_8822B) -#define BIT_GET_DMA_AGG_TO_8822B(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8822B) & BIT_MASK_DMA_AGG_TO_8822B) - - - -#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B 0 -#define BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B 0xf -#define BIT_RXDMA_AGG_PG_TH_V1_8822B(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B) -#define BIT_GET_RXDMA_AGG_PG_TH_V1_8822B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B) - - +#define BIT_PKT_NUM_WOL_8822B(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_8822B) << BIT_SHIFT_PKT_NUM_WOL_8822B) +#define BITS_PKT_NUM_WOL_8822B \ + (BIT_MASK_PKT_NUM_WOL_8822B << BIT_SHIFT_PKT_NUM_WOL_8822B) +#define BIT_CLEAR_PKT_NUM_WOL_8822B(x) ((x) & (~BITS_PKT_NUM_WOL_8822B)) +#define BIT_GET_PKT_NUM_WOL_8822B(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_8822B) & BIT_MASK_PKT_NUM_WOL_8822B) +#define BIT_SET_PKT_NUM_WOL_8822B(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_8822B(x) | BIT_PKT_NUM_WOL_8822B(v)) + +#define BIT_SHIFT_DMA_AGG_TO_V1_8822B 8 +#define BIT_MASK_DMA_AGG_TO_V1_8822B 0xff +#define BIT_DMA_AGG_TO_V1_8822B(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1_8822B) << BIT_SHIFT_DMA_AGG_TO_V1_8822B) +#define BITS_DMA_AGG_TO_V1_8822B \ + (BIT_MASK_DMA_AGG_TO_V1_8822B << BIT_SHIFT_DMA_AGG_TO_V1_8822B) +#define BIT_CLEAR_DMA_AGG_TO_V1_8822B(x) ((x) & (~BITS_DMA_AGG_TO_V1_8822B)) +#define BIT_GET_DMA_AGG_TO_V1_8822B(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8822B) & BIT_MASK_DMA_AGG_TO_V1_8822B) +#define BIT_SET_DMA_AGG_TO_V1_8822B(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1_8822B(x) | BIT_DMA_AGG_TO_V1_8822B(v)) + +#define BIT_SHIFT_RXDMA_AGG_PG_TH_8822B 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_8822B 0xff +#define BIT_RXDMA_AGG_PG_TH_8822B(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8822B) \ + << BIT_SHIFT_RXDMA_AGG_PG_TH_8822B) +#define BITS_RXDMA_AGG_PG_TH_8822B \ + (BIT_MASK_RXDMA_AGG_PG_TH_8822B << BIT_SHIFT_RXDMA_AGG_PG_TH_8822B) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_8822B(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8822B)) +#define BIT_GET_RXDMA_AGG_PG_TH_8822B(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8822B) & \ + BIT_MASK_RXDMA_AGG_PG_TH_8822B) +#define BIT_SET_RXDMA_AGG_PG_TH_8822B(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_8822B(x) | BIT_RXDMA_AGG_PG_TH_8822B(v)) /* 2 REG_RXPKT_NUM_8822B */ #define BIT_SHIFT_RXPKT_NUM_8822B 24 #define BIT_MASK_RXPKT_NUM_8822B 0xff -#define BIT_RXPKT_NUM_8822B(x) (((x) & BIT_MASK_RXPKT_NUM_8822B) << BIT_SHIFT_RXPKT_NUM_8822B) -#define BIT_GET_RXPKT_NUM_8822B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8822B) & BIT_MASK_RXPKT_NUM_8822B) - - +#define BIT_RXPKT_NUM_8822B(x) \ + (((x) & BIT_MASK_RXPKT_NUM_8822B) << BIT_SHIFT_RXPKT_NUM_8822B) +#define BITS_RXPKT_NUM_8822B \ + (BIT_MASK_RXPKT_NUM_8822B << BIT_SHIFT_RXPKT_NUM_8822B) +#define BIT_CLEAR_RXPKT_NUM_8822B(x) ((x) & (~BITS_RXPKT_NUM_8822B)) +#define BIT_GET_RXPKT_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_8822B) & BIT_MASK_RXPKT_NUM_8822B) +#define BIT_SET_RXPKT_NUM_8822B(x, v) \ + (BIT_CLEAR_RXPKT_NUM_8822B(x) | BIT_RXPKT_NUM_8822B(v)) #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B 20 #define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B 0xf -#define BIT_FW_UPD_RDPTR19_TO_16_8822B(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) -#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) - +#define BIT_FW_UPD_RDPTR19_TO_16_8822B(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) +#define BITS_FW_UPD_RDPTR19_TO_16_8822B \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822B(x) \ + ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8822B)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822B(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) +#define BIT_SET_FW_UPD_RDPTR19_TO_16_8822B(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822B(x) | \ + BIT_FW_UPD_RDPTR19_TO_16_8822B(v)) #define BIT_RXDMA_REQ_8822B BIT(19) #define BIT_RW_RELEASE_EN_8822B BIT(18) @@ -3765,10 +5497,15 @@ #define BIT_SHIFT_FW_UPD_RDPTR_8822B 0 #define BIT_MASK_FW_UPD_RDPTR_8822B 0xffff -#define BIT_FW_UPD_RDPTR_8822B(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8822B) << BIT_SHIFT_FW_UPD_RDPTR_8822B) -#define BIT_GET_FW_UPD_RDPTR_8822B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822B) & BIT_MASK_FW_UPD_RDPTR_8822B) - - +#define BIT_FW_UPD_RDPTR_8822B(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR_8822B) << BIT_SHIFT_FW_UPD_RDPTR_8822B) +#define BITS_FW_UPD_RDPTR_8822B \ + (BIT_MASK_FW_UPD_RDPTR_8822B << BIT_SHIFT_FW_UPD_RDPTR_8822B) +#define BIT_CLEAR_FW_UPD_RDPTR_8822B(x) ((x) & (~BITS_FW_UPD_RDPTR_8822B)) +#define BIT_GET_FW_UPD_RDPTR_8822B(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822B) & BIT_MASK_FW_UPD_RDPTR_8822B) +#define BIT_SET_FW_UPD_RDPTR_8822B(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR_8822B(x) | BIT_FW_UPD_RDPTR_8822B(v)) /* 2 REG_RXDMA_STATUS_8822B */ #define BIT_C2H_PKT_OVF_8822B BIT(7) @@ -3783,27 +5520,43 @@ #define BIT_SHIFT_RDE_DEBUG_8822B 0 #define BIT_MASK_RDE_DEBUG_8822B 0xffffffffL -#define BIT_RDE_DEBUG_8822B(x) (((x) & BIT_MASK_RDE_DEBUG_8822B) << BIT_SHIFT_RDE_DEBUG_8822B) -#define BIT_GET_RDE_DEBUG_8822B(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8822B) & BIT_MASK_RDE_DEBUG_8822B) - - +#define BIT_RDE_DEBUG_8822B(x) \ + (((x) & BIT_MASK_RDE_DEBUG_8822B) << BIT_SHIFT_RDE_DEBUG_8822B) +#define BITS_RDE_DEBUG_8822B \ + (BIT_MASK_RDE_DEBUG_8822B << BIT_SHIFT_RDE_DEBUG_8822B) +#define BIT_CLEAR_RDE_DEBUG_8822B(x) ((x) & (~BITS_RDE_DEBUG_8822B)) +#define BIT_GET_RDE_DEBUG_8822B(x) \ + (((x) >> BIT_SHIFT_RDE_DEBUG_8822B) & BIT_MASK_RDE_DEBUG_8822B) +#define BIT_SET_RDE_DEBUG_8822B(x, v) \ + (BIT_CLEAR_RDE_DEBUG_8822B(x) | BIT_RDE_DEBUG_8822B(v)) /* 2 REG_RXDMA_MODE_8822B */ #define BIT_SHIFT_PKTNUM_TH_V2_8822B 24 #define BIT_MASK_PKTNUM_TH_V2_8822B 0x1f -#define BIT_PKTNUM_TH_V2_8822B(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8822B) << BIT_SHIFT_PKTNUM_TH_V2_8822B) -#define BIT_GET_PKTNUM_TH_V2_8822B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822B) & BIT_MASK_PKTNUM_TH_V2_8822B) - +#define BIT_PKTNUM_TH_V2_8822B(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V2_8822B) << BIT_SHIFT_PKTNUM_TH_V2_8822B) +#define BITS_PKTNUM_TH_V2_8822B \ + (BIT_MASK_PKTNUM_TH_V2_8822B << BIT_SHIFT_PKTNUM_TH_V2_8822B) +#define BIT_CLEAR_PKTNUM_TH_V2_8822B(x) ((x) & (~BITS_PKTNUM_TH_V2_8822B)) +#define BIT_GET_PKTNUM_TH_V2_8822B(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822B) & BIT_MASK_PKTNUM_TH_V2_8822B) +#define BIT_SET_PKTNUM_TH_V2_8822B(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V2_8822B(x) | BIT_PKTNUM_TH_V2_8822B(v)) #define BIT_TXBA_BREAK_USBAGG_8822B BIT(23) #define BIT_SHIFT_PKTLEN_PARA_8822B 16 #define BIT_MASK_PKTLEN_PARA_8822B 0x7 -#define BIT_PKTLEN_PARA_8822B(x) (((x) & BIT_MASK_PKTLEN_PARA_8822B) << BIT_SHIFT_PKTLEN_PARA_8822B) -#define BIT_GET_PKTLEN_PARA_8822B(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8822B) & BIT_MASK_PKTLEN_PARA_8822B) - - +#define BIT_PKTLEN_PARA_8822B(x) \ + (((x) & BIT_MASK_PKTLEN_PARA_8822B) << BIT_SHIFT_PKTLEN_PARA_8822B) +#define BITS_PKTLEN_PARA_8822B \ + (BIT_MASK_PKTLEN_PARA_8822B << BIT_SHIFT_PKTLEN_PARA_8822B) +#define BIT_CLEAR_PKTLEN_PARA_8822B(x) ((x) & (~BITS_PKTLEN_PARA_8822B)) +#define BIT_GET_PKTLEN_PARA_8822B(x) \ + (((x) >> BIT_SHIFT_PKTLEN_PARA_8822B) & BIT_MASK_PKTLEN_PARA_8822B) +#define BIT_SET_PKTLEN_PARA_8822B(x, v) \ + (BIT_CLEAR_PKTLEN_PARA_8822B(x) | BIT_PKTLEN_PARA_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -3813,16 +5566,27 @@ #define BIT_SHIFT_BURST_SIZE_8822B 4 #define BIT_MASK_BURST_SIZE_8822B 0x3 -#define BIT_BURST_SIZE_8822B(x) (((x) & BIT_MASK_BURST_SIZE_8822B) << BIT_SHIFT_BURST_SIZE_8822B) -#define BIT_GET_BURST_SIZE_8822B(x) (((x) >> BIT_SHIFT_BURST_SIZE_8822B) & BIT_MASK_BURST_SIZE_8822B) - - +#define BIT_BURST_SIZE_8822B(x) \ + (((x) & BIT_MASK_BURST_SIZE_8822B) << BIT_SHIFT_BURST_SIZE_8822B) +#define BITS_BURST_SIZE_8822B \ + (BIT_MASK_BURST_SIZE_8822B << BIT_SHIFT_BURST_SIZE_8822B) +#define BIT_CLEAR_BURST_SIZE_8822B(x) ((x) & (~BITS_BURST_SIZE_8822B)) +#define BIT_GET_BURST_SIZE_8822B(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE_8822B) & BIT_MASK_BURST_SIZE_8822B) +#define BIT_SET_BURST_SIZE_8822B(x, v) \ + (BIT_CLEAR_BURST_SIZE_8822B(x) | BIT_BURST_SIZE_8822B(v)) #define BIT_SHIFT_BURST_CNT_8822B 2 #define BIT_MASK_BURST_CNT_8822B 0x3 -#define BIT_BURST_CNT_8822B(x) (((x) & BIT_MASK_BURST_CNT_8822B) << BIT_SHIFT_BURST_CNT_8822B) -#define BIT_GET_BURST_CNT_8822B(x) (((x) >> BIT_SHIFT_BURST_CNT_8822B) & BIT_MASK_BURST_CNT_8822B) - +#define BIT_BURST_CNT_8822B(x) \ + (((x) & BIT_MASK_BURST_CNT_8822B) << BIT_SHIFT_BURST_CNT_8822B) +#define BITS_BURST_CNT_8822B \ + (BIT_MASK_BURST_CNT_8822B << BIT_SHIFT_BURST_CNT_8822B) +#define BIT_CLEAR_BURST_CNT_8822B(x) ((x) & (~BITS_BURST_CNT_8822B)) +#define BIT_GET_BURST_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_BURST_CNT_8822B) & BIT_MASK_BURST_CNT_8822B) +#define BIT_SET_BURST_CNT_8822B(x, v) \ + (BIT_CLEAR_BURST_CNT_8822B(x) | BIT_BURST_CNT_8822B(v)) #define BIT_DMA_MODE_8822B BIT(1) @@ -3830,60 +5594,111 @@ #define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B 24 #define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B 0xf -#define BIT_R_C2H_STR_ADDR_16_TO_19_8822B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) -#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) - +#define BIT_R_C2H_STR_ADDR_16_TO_19_8822B(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) +#define BITS_R_C2H_STR_ADDR_16_TO_19_8822B \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822B(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8822B)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822B(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8822B(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822B(x) | \ + BIT_R_C2H_STR_ADDR_16_TO_19_8822B(v)) #define BIT_R_C2H_PKT_REQ_8822B BIT(16) #define BIT_SHIFT_R_C2H_STR_ADDR_8822B 0 #define BIT_MASK_R_C2H_STR_ADDR_8822B 0xffff -#define BIT_R_C2H_STR_ADDR_8822B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8822B) << BIT_SHIFT_R_C2H_STR_ADDR_8822B) -#define BIT_GET_R_C2H_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822B) & BIT_MASK_R_C2H_STR_ADDR_8822B) - - +#define BIT_R_C2H_STR_ADDR_8822B(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_8822B) \ + << BIT_SHIFT_R_C2H_STR_ADDR_8822B) +#define BITS_R_C2H_STR_ADDR_8822B \ + (BIT_MASK_R_C2H_STR_ADDR_8822B << BIT_SHIFT_R_C2H_STR_ADDR_8822B) +#define BIT_CLEAR_R_C2H_STR_ADDR_8822B(x) ((x) & (~BITS_R_C2H_STR_ADDR_8822B)) +#define BIT_GET_R_C2H_STR_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822B) & \ + BIT_MASK_R_C2H_STR_ADDR_8822B) +#define BIT_SET_R_C2H_STR_ADDR_8822B(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_8822B(x) | BIT_R_C2H_STR_ADDR_8822B(v)) /* 2 REG_FWFF_C2H_8822B */ #define BIT_SHIFT_C2H_DMA_ADDR_8822B 0 #define BIT_MASK_C2H_DMA_ADDR_8822B 0x3ffff -#define BIT_C2H_DMA_ADDR_8822B(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8822B) << BIT_SHIFT_C2H_DMA_ADDR_8822B) -#define BIT_GET_C2H_DMA_ADDR_8822B(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822B) & BIT_MASK_C2H_DMA_ADDR_8822B) - - +#define BIT_C2H_DMA_ADDR_8822B(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR_8822B) << BIT_SHIFT_C2H_DMA_ADDR_8822B) +#define BITS_C2H_DMA_ADDR_8822B \ + (BIT_MASK_C2H_DMA_ADDR_8822B << BIT_SHIFT_C2H_DMA_ADDR_8822B) +#define BIT_CLEAR_C2H_DMA_ADDR_8822B(x) ((x) & (~BITS_C2H_DMA_ADDR_8822B)) +#define BIT_GET_C2H_DMA_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822B) & BIT_MASK_C2H_DMA_ADDR_8822B) +#define BIT_SET_C2H_DMA_ADDR_8822B(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR_8822B(x) | BIT_C2H_DMA_ADDR_8822B(v)) /* 2 REG_FWFF_CTRL_8822B */ #define BIT_FWFF_DMAPKT_REQ_8822B BIT(31) #define BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B 16 #define BIT_MASK_FWFF_DMA_PKT_NUM_8822B 0xff -#define BIT_FWFF_DMA_PKT_NUM_8822B(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) -#define BIT_GET_FWFF_DMA_PKT_NUM_8822B(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B) - - +#define BIT_FWFF_DMA_PKT_NUM_8822B(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B) \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) +#define BITS_FWFF_DMA_PKT_NUM_8822B \ + (BIT_MASK_FWFF_DMA_PKT_NUM_8822B << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8822B(x) \ + ((x) & (~BITS_FWFF_DMA_PKT_NUM_8822B)) +#define BIT_GET_FWFF_DMA_PKT_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) & \ + BIT_MASK_FWFF_DMA_PKT_NUM_8822B) +#define BIT_SET_FWFF_DMA_PKT_NUM_8822B(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_8822B(x) | BIT_FWFF_DMA_PKT_NUM_8822B(v)) #define BIT_SHIFT_FWFF_STR_ADDR_8822B 0 #define BIT_MASK_FWFF_STR_ADDR_8822B 0xffff -#define BIT_FWFF_STR_ADDR_8822B(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8822B) << BIT_SHIFT_FWFF_STR_ADDR_8822B) -#define BIT_GET_FWFF_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822B) & BIT_MASK_FWFF_STR_ADDR_8822B) - - +#define BIT_FWFF_STR_ADDR_8822B(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR_8822B) << BIT_SHIFT_FWFF_STR_ADDR_8822B) +#define BITS_FWFF_STR_ADDR_8822B \ + (BIT_MASK_FWFF_STR_ADDR_8822B << BIT_SHIFT_FWFF_STR_ADDR_8822B) +#define BIT_CLEAR_FWFF_STR_ADDR_8822B(x) ((x) & (~BITS_FWFF_STR_ADDR_8822B)) +#define BIT_GET_FWFF_STR_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822B) & BIT_MASK_FWFF_STR_ADDR_8822B) +#define BIT_SET_FWFF_STR_ADDR_8822B(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR_8822B(x) | BIT_FWFF_STR_ADDR_8822B(v)) /* 2 REG_FWFF_PKT_INFO_8822B */ #define BIT_SHIFT_FWFF_PKT_QUEUED_8822B 16 #define BIT_MASK_FWFF_PKT_QUEUED_8822B 0xff -#define BIT_FWFF_PKT_QUEUED_8822B(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8822B) << BIT_SHIFT_FWFF_PKT_QUEUED_8822B) -#define BIT_GET_FWFF_PKT_QUEUED_8822B(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822B) & BIT_MASK_FWFF_PKT_QUEUED_8822B) - - +#define BIT_FWFF_PKT_QUEUED_8822B(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_8822B) \ + << BIT_SHIFT_FWFF_PKT_QUEUED_8822B) +#define BITS_FWFF_PKT_QUEUED_8822B \ + (BIT_MASK_FWFF_PKT_QUEUED_8822B << BIT_SHIFT_FWFF_PKT_QUEUED_8822B) +#define BIT_CLEAR_FWFF_PKT_QUEUED_8822B(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8822B)) +#define BIT_GET_FWFF_PKT_QUEUED_8822B(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822B) & \ + BIT_MASK_FWFF_PKT_QUEUED_8822B) +#define BIT_SET_FWFF_PKT_QUEUED_8822B(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_8822B(x) | BIT_FWFF_PKT_QUEUED_8822B(v)) #define BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B 0 #define BIT_MASK_FWFF_PKT_STR_ADDR_8822B 0xffff -#define BIT_FWFF_PKT_STR_ADDR_8822B(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) -#define BIT_GET_FWFF_PKT_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B) - - +#define BIT_FWFF_PKT_STR_ADDR_8822B(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) +#define BITS_FWFF_PKT_STR_ADDR_8822B \ + (BIT_MASK_FWFF_PKT_STR_ADDR_8822B << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8822B(x) \ + ((x) & (~BITS_FWFF_PKT_STR_ADDR_8822B)) +#define BIT_GET_FWFF_PKT_STR_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_8822B) +#define BIT_SET_FWFF_PKT_STR_ADDR_8822B(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_8822B(x) | BIT_FWFF_PKT_STR_ADDR_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -3891,22 +5706,33 @@ #define BIT_SHIFT_DDMACH0_SA_8822B 0 #define BIT_MASK_DDMACH0_SA_8822B 0xffffffffL -#define BIT_DDMACH0_SA_8822B(x) (((x) & BIT_MASK_DDMACH0_SA_8822B) << BIT_SHIFT_DDMACH0_SA_8822B) -#define BIT_GET_DDMACH0_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8822B) & BIT_MASK_DDMACH0_SA_8822B) - - +#define BIT_DDMACH0_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH0_SA_8822B) << BIT_SHIFT_DDMACH0_SA_8822B) +#define BITS_DDMACH0_SA_8822B \ + (BIT_MASK_DDMACH0_SA_8822B << BIT_SHIFT_DDMACH0_SA_8822B) +#define BIT_CLEAR_DDMACH0_SA_8822B(x) ((x) & (~BITS_DDMACH0_SA_8822B)) +#define BIT_GET_DDMACH0_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA_8822B) & BIT_MASK_DDMACH0_SA_8822B) +#define BIT_SET_DDMACH0_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH0_SA_8822B(x) | BIT_DDMACH0_SA_8822B(v)) /* 2 REG_DDMA_CH0DA_8822B */ #define BIT_SHIFT_DDMACH0_DA_8822B 0 #define BIT_MASK_DDMACH0_DA_8822B 0xffffffffL -#define BIT_DDMACH0_DA_8822B(x) (((x) & BIT_MASK_DDMACH0_DA_8822B) << BIT_SHIFT_DDMACH0_DA_8822B) -#define BIT_GET_DDMACH0_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8822B) & BIT_MASK_DDMACH0_DA_8822B) - - +#define BIT_DDMACH0_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH0_DA_8822B) << BIT_SHIFT_DDMACH0_DA_8822B) +#define BITS_DDMACH0_DA_8822B \ + (BIT_MASK_DDMACH0_DA_8822B << BIT_SHIFT_DDMACH0_DA_8822B) +#define BIT_CLEAR_DDMACH0_DA_8822B(x) ((x) & (~BITS_DDMACH0_DA_8822B)) +#define BIT_GET_DDMACH0_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA_8822B) & BIT_MASK_DDMACH0_DA_8822B) +#define BIT_SET_DDMACH0_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH0_DA_8822B(x) | BIT_DDMACH0_DA_8822B(v)) /* 2 REG_DDMA_CH0CTRL_8822B */ #define BIT_DDMACH0_OWN_8822B BIT(31) +#define BIT_DDMACH0_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH0_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH0_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH0_CHKSUM_STS_8822B BIT(27) @@ -3916,31 +5742,47 @@ #define BIT_SHIFT_DDMACH0_DLEN_8822B 0 #define BIT_MASK_DDMACH0_DLEN_8822B 0x3ffff -#define BIT_DDMACH0_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH0_DLEN_8822B) << BIT_SHIFT_DDMACH0_DLEN_8822B) -#define BIT_GET_DDMACH0_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8822B) & BIT_MASK_DDMACH0_DLEN_8822B) - - +#define BIT_DDMACH0_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN_8822B) << BIT_SHIFT_DDMACH0_DLEN_8822B) +#define BITS_DDMACH0_DLEN_8822B \ + (BIT_MASK_DDMACH0_DLEN_8822B << BIT_SHIFT_DDMACH0_DLEN_8822B) +#define BIT_CLEAR_DDMACH0_DLEN_8822B(x) ((x) & (~BITS_DDMACH0_DLEN_8822B)) +#define BIT_GET_DDMACH0_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN_8822B) & BIT_MASK_DDMACH0_DLEN_8822B) +#define BIT_SET_DDMACH0_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN_8822B(x) | BIT_DDMACH0_DLEN_8822B(v)) /* 2 REG_DDMA_CH1SA_8822B */ #define BIT_SHIFT_DDMACH1_SA_8822B 0 #define BIT_MASK_DDMACH1_SA_8822B 0xffffffffL -#define BIT_DDMACH1_SA_8822B(x) (((x) & BIT_MASK_DDMACH1_SA_8822B) << BIT_SHIFT_DDMACH1_SA_8822B) -#define BIT_GET_DDMACH1_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8822B) & BIT_MASK_DDMACH1_SA_8822B) - - +#define BIT_DDMACH1_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH1_SA_8822B) << BIT_SHIFT_DDMACH1_SA_8822B) +#define BITS_DDMACH1_SA_8822B \ + (BIT_MASK_DDMACH1_SA_8822B << BIT_SHIFT_DDMACH1_SA_8822B) +#define BIT_CLEAR_DDMACH1_SA_8822B(x) ((x) & (~BITS_DDMACH1_SA_8822B)) +#define BIT_GET_DDMACH1_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA_8822B) & BIT_MASK_DDMACH1_SA_8822B) +#define BIT_SET_DDMACH1_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH1_SA_8822B(x) | BIT_DDMACH1_SA_8822B(v)) /* 2 REG_DDMA_CH1DA_8822B */ #define BIT_SHIFT_DDMACH1_DA_8822B 0 #define BIT_MASK_DDMACH1_DA_8822B 0xffffffffL -#define BIT_DDMACH1_DA_8822B(x) (((x) & BIT_MASK_DDMACH1_DA_8822B) << BIT_SHIFT_DDMACH1_DA_8822B) -#define BIT_GET_DDMACH1_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8822B) & BIT_MASK_DDMACH1_DA_8822B) - - +#define BIT_DDMACH1_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH1_DA_8822B) << BIT_SHIFT_DDMACH1_DA_8822B) +#define BITS_DDMACH1_DA_8822B \ + (BIT_MASK_DDMACH1_DA_8822B << BIT_SHIFT_DDMACH1_DA_8822B) +#define BIT_CLEAR_DDMACH1_DA_8822B(x) ((x) & (~BITS_DDMACH1_DA_8822B)) +#define BIT_GET_DDMACH1_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA_8822B) & BIT_MASK_DDMACH1_DA_8822B) +#define BIT_SET_DDMACH1_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH1_DA_8822B(x) | BIT_DDMACH1_DA_8822B(v)) /* 2 REG_DDMA_CH1CTRL_8822B */ #define BIT_DDMACH1_OWN_8822B BIT(31) +#define BIT_DDMACH1_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH1_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH1_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH1_CHKSUM_STS_8822B BIT(27) @@ -3950,31 +5792,47 @@ #define BIT_SHIFT_DDMACH1_DLEN_8822B 0 #define BIT_MASK_DDMACH1_DLEN_8822B 0x3ffff -#define BIT_DDMACH1_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH1_DLEN_8822B) << BIT_SHIFT_DDMACH1_DLEN_8822B) -#define BIT_GET_DDMACH1_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8822B) & BIT_MASK_DDMACH1_DLEN_8822B) - - +#define BIT_DDMACH1_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN_8822B) << BIT_SHIFT_DDMACH1_DLEN_8822B) +#define BITS_DDMACH1_DLEN_8822B \ + (BIT_MASK_DDMACH1_DLEN_8822B << BIT_SHIFT_DDMACH1_DLEN_8822B) +#define BIT_CLEAR_DDMACH1_DLEN_8822B(x) ((x) & (~BITS_DDMACH1_DLEN_8822B)) +#define BIT_GET_DDMACH1_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN_8822B) & BIT_MASK_DDMACH1_DLEN_8822B) +#define BIT_SET_DDMACH1_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN_8822B(x) | BIT_DDMACH1_DLEN_8822B(v)) /* 2 REG_DDMA_CH2SA_8822B */ #define BIT_SHIFT_DDMACH2_SA_8822B 0 #define BIT_MASK_DDMACH2_SA_8822B 0xffffffffL -#define BIT_DDMACH2_SA_8822B(x) (((x) & BIT_MASK_DDMACH2_SA_8822B) << BIT_SHIFT_DDMACH2_SA_8822B) -#define BIT_GET_DDMACH2_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8822B) & BIT_MASK_DDMACH2_SA_8822B) - - +#define BIT_DDMACH2_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH2_SA_8822B) << BIT_SHIFT_DDMACH2_SA_8822B) +#define BITS_DDMACH2_SA_8822B \ + (BIT_MASK_DDMACH2_SA_8822B << BIT_SHIFT_DDMACH2_SA_8822B) +#define BIT_CLEAR_DDMACH2_SA_8822B(x) ((x) & (~BITS_DDMACH2_SA_8822B)) +#define BIT_GET_DDMACH2_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA_8822B) & BIT_MASK_DDMACH2_SA_8822B) +#define BIT_SET_DDMACH2_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH2_SA_8822B(x) | BIT_DDMACH2_SA_8822B(v)) /* 2 REG_DDMA_CH2DA_8822B */ #define BIT_SHIFT_DDMACH2_DA_8822B 0 #define BIT_MASK_DDMACH2_DA_8822B 0xffffffffL -#define BIT_DDMACH2_DA_8822B(x) (((x) & BIT_MASK_DDMACH2_DA_8822B) << BIT_SHIFT_DDMACH2_DA_8822B) -#define BIT_GET_DDMACH2_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8822B) & BIT_MASK_DDMACH2_DA_8822B) - - +#define BIT_DDMACH2_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH2_DA_8822B) << BIT_SHIFT_DDMACH2_DA_8822B) +#define BITS_DDMACH2_DA_8822B \ + (BIT_MASK_DDMACH2_DA_8822B << BIT_SHIFT_DDMACH2_DA_8822B) +#define BIT_CLEAR_DDMACH2_DA_8822B(x) ((x) & (~BITS_DDMACH2_DA_8822B)) +#define BIT_GET_DDMACH2_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA_8822B) & BIT_MASK_DDMACH2_DA_8822B) +#define BIT_SET_DDMACH2_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH2_DA_8822B(x) | BIT_DDMACH2_DA_8822B(v)) /* 2 REG_DDMA_CH2CTRL_8822B */ #define BIT_DDMACH2_OWN_8822B BIT(31) +#define BIT_DDMACH2_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH2_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH2_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH2_CHKSUM_STS_8822B BIT(27) @@ -3984,31 +5842,47 @@ #define BIT_SHIFT_DDMACH2_DLEN_8822B 0 #define BIT_MASK_DDMACH2_DLEN_8822B 0x3ffff -#define BIT_DDMACH2_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH2_DLEN_8822B) << BIT_SHIFT_DDMACH2_DLEN_8822B) -#define BIT_GET_DDMACH2_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8822B) & BIT_MASK_DDMACH2_DLEN_8822B) - - +#define BIT_DDMACH2_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN_8822B) << BIT_SHIFT_DDMACH2_DLEN_8822B) +#define BITS_DDMACH2_DLEN_8822B \ + (BIT_MASK_DDMACH2_DLEN_8822B << BIT_SHIFT_DDMACH2_DLEN_8822B) +#define BIT_CLEAR_DDMACH2_DLEN_8822B(x) ((x) & (~BITS_DDMACH2_DLEN_8822B)) +#define BIT_GET_DDMACH2_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN_8822B) & BIT_MASK_DDMACH2_DLEN_8822B) +#define BIT_SET_DDMACH2_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN_8822B(x) | BIT_DDMACH2_DLEN_8822B(v)) /* 2 REG_DDMA_CH3SA_8822B */ #define BIT_SHIFT_DDMACH3_SA_8822B 0 #define BIT_MASK_DDMACH3_SA_8822B 0xffffffffL -#define BIT_DDMACH3_SA_8822B(x) (((x) & BIT_MASK_DDMACH3_SA_8822B) << BIT_SHIFT_DDMACH3_SA_8822B) -#define BIT_GET_DDMACH3_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8822B) & BIT_MASK_DDMACH3_SA_8822B) - - +#define BIT_DDMACH3_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH3_SA_8822B) << BIT_SHIFT_DDMACH3_SA_8822B) +#define BITS_DDMACH3_SA_8822B \ + (BIT_MASK_DDMACH3_SA_8822B << BIT_SHIFT_DDMACH3_SA_8822B) +#define BIT_CLEAR_DDMACH3_SA_8822B(x) ((x) & (~BITS_DDMACH3_SA_8822B)) +#define BIT_GET_DDMACH3_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA_8822B) & BIT_MASK_DDMACH3_SA_8822B) +#define BIT_SET_DDMACH3_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH3_SA_8822B(x) | BIT_DDMACH3_SA_8822B(v)) /* 2 REG_DDMA_CH3DA_8822B */ #define BIT_SHIFT_DDMACH3_DA_8822B 0 #define BIT_MASK_DDMACH3_DA_8822B 0xffffffffL -#define BIT_DDMACH3_DA_8822B(x) (((x) & BIT_MASK_DDMACH3_DA_8822B) << BIT_SHIFT_DDMACH3_DA_8822B) -#define BIT_GET_DDMACH3_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8822B) & BIT_MASK_DDMACH3_DA_8822B) - - +#define BIT_DDMACH3_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH3_DA_8822B) << BIT_SHIFT_DDMACH3_DA_8822B) +#define BITS_DDMACH3_DA_8822B \ + (BIT_MASK_DDMACH3_DA_8822B << BIT_SHIFT_DDMACH3_DA_8822B) +#define BIT_CLEAR_DDMACH3_DA_8822B(x) ((x) & (~BITS_DDMACH3_DA_8822B)) +#define BIT_GET_DDMACH3_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA_8822B) & BIT_MASK_DDMACH3_DA_8822B) +#define BIT_SET_DDMACH3_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH3_DA_8822B(x) | BIT_DDMACH3_DA_8822B(v)) /* 2 REG_DDMA_CH3CTRL_8822B */ #define BIT_DDMACH3_OWN_8822B BIT(31) +#define BIT_DDMACH3_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH3_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH3_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH3_CHKSUM_STS_8822B BIT(27) @@ -4018,31 +5892,47 @@ #define BIT_SHIFT_DDMACH3_DLEN_8822B 0 #define BIT_MASK_DDMACH3_DLEN_8822B 0x3ffff -#define BIT_DDMACH3_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH3_DLEN_8822B) << BIT_SHIFT_DDMACH3_DLEN_8822B) -#define BIT_GET_DDMACH3_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8822B) & BIT_MASK_DDMACH3_DLEN_8822B) - - +#define BIT_DDMACH3_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN_8822B) << BIT_SHIFT_DDMACH3_DLEN_8822B) +#define BITS_DDMACH3_DLEN_8822B \ + (BIT_MASK_DDMACH3_DLEN_8822B << BIT_SHIFT_DDMACH3_DLEN_8822B) +#define BIT_CLEAR_DDMACH3_DLEN_8822B(x) ((x) & (~BITS_DDMACH3_DLEN_8822B)) +#define BIT_GET_DDMACH3_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN_8822B) & BIT_MASK_DDMACH3_DLEN_8822B) +#define BIT_SET_DDMACH3_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN_8822B(x) | BIT_DDMACH3_DLEN_8822B(v)) /* 2 REG_DDMA_CH4SA_8822B */ #define BIT_SHIFT_DDMACH4_SA_8822B 0 #define BIT_MASK_DDMACH4_SA_8822B 0xffffffffL -#define BIT_DDMACH4_SA_8822B(x) (((x) & BIT_MASK_DDMACH4_SA_8822B) << BIT_SHIFT_DDMACH4_SA_8822B) -#define BIT_GET_DDMACH4_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8822B) & BIT_MASK_DDMACH4_SA_8822B) - - +#define BIT_DDMACH4_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH4_SA_8822B) << BIT_SHIFT_DDMACH4_SA_8822B) +#define BITS_DDMACH4_SA_8822B \ + (BIT_MASK_DDMACH4_SA_8822B << BIT_SHIFT_DDMACH4_SA_8822B) +#define BIT_CLEAR_DDMACH4_SA_8822B(x) ((x) & (~BITS_DDMACH4_SA_8822B)) +#define BIT_GET_DDMACH4_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA_8822B) & BIT_MASK_DDMACH4_SA_8822B) +#define BIT_SET_DDMACH4_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH4_SA_8822B(x) | BIT_DDMACH4_SA_8822B(v)) /* 2 REG_DDMA_CH4DA_8822B */ #define BIT_SHIFT_DDMACH4_DA_8822B 0 #define BIT_MASK_DDMACH4_DA_8822B 0xffffffffL -#define BIT_DDMACH4_DA_8822B(x) (((x) & BIT_MASK_DDMACH4_DA_8822B) << BIT_SHIFT_DDMACH4_DA_8822B) -#define BIT_GET_DDMACH4_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8822B) & BIT_MASK_DDMACH4_DA_8822B) - - +#define BIT_DDMACH4_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH4_DA_8822B) << BIT_SHIFT_DDMACH4_DA_8822B) +#define BITS_DDMACH4_DA_8822B \ + (BIT_MASK_DDMACH4_DA_8822B << BIT_SHIFT_DDMACH4_DA_8822B) +#define BIT_CLEAR_DDMACH4_DA_8822B(x) ((x) & (~BITS_DDMACH4_DA_8822B)) +#define BIT_GET_DDMACH4_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA_8822B) & BIT_MASK_DDMACH4_DA_8822B) +#define BIT_SET_DDMACH4_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH4_DA_8822B(x) | BIT_DDMACH4_DA_8822B(v)) /* 2 REG_DDMA_CH4CTRL_8822B */ #define BIT_DDMACH4_OWN_8822B BIT(31) +#define BIT_DDMACH4_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH4_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH4_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH4_CHKSUM_STS_8822B BIT(27) @@ -4052,31 +5942,47 @@ #define BIT_SHIFT_DDMACH4_DLEN_8822B 0 #define BIT_MASK_DDMACH4_DLEN_8822B 0x3ffff -#define BIT_DDMACH4_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH4_DLEN_8822B) << BIT_SHIFT_DDMACH4_DLEN_8822B) -#define BIT_GET_DDMACH4_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8822B) & BIT_MASK_DDMACH4_DLEN_8822B) - - +#define BIT_DDMACH4_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN_8822B) << BIT_SHIFT_DDMACH4_DLEN_8822B) +#define BITS_DDMACH4_DLEN_8822B \ + (BIT_MASK_DDMACH4_DLEN_8822B << BIT_SHIFT_DDMACH4_DLEN_8822B) +#define BIT_CLEAR_DDMACH4_DLEN_8822B(x) ((x) & (~BITS_DDMACH4_DLEN_8822B)) +#define BIT_GET_DDMACH4_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN_8822B) & BIT_MASK_DDMACH4_DLEN_8822B) +#define BIT_SET_DDMACH4_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN_8822B(x) | BIT_DDMACH4_DLEN_8822B(v)) /* 2 REG_DDMA_CH5SA_8822B */ #define BIT_SHIFT_DDMACH5_SA_8822B 0 #define BIT_MASK_DDMACH5_SA_8822B 0xffffffffL -#define BIT_DDMACH5_SA_8822B(x) (((x) & BIT_MASK_DDMACH5_SA_8822B) << BIT_SHIFT_DDMACH5_SA_8822B) -#define BIT_GET_DDMACH5_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8822B) & BIT_MASK_DDMACH5_SA_8822B) - - +#define BIT_DDMACH5_SA_8822B(x) \ + (((x) & BIT_MASK_DDMACH5_SA_8822B) << BIT_SHIFT_DDMACH5_SA_8822B) +#define BITS_DDMACH5_SA_8822B \ + (BIT_MASK_DDMACH5_SA_8822B << BIT_SHIFT_DDMACH5_SA_8822B) +#define BIT_CLEAR_DDMACH5_SA_8822B(x) ((x) & (~BITS_DDMACH5_SA_8822B)) +#define BIT_GET_DDMACH5_SA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA_8822B) & BIT_MASK_DDMACH5_SA_8822B) +#define BIT_SET_DDMACH5_SA_8822B(x, v) \ + (BIT_CLEAR_DDMACH5_SA_8822B(x) | BIT_DDMACH5_SA_8822B(v)) /* 2 REG_DDMA_CH5DA_8822B */ #define BIT_SHIFT_DDMACH5_DA_8822B 0 #define BIT_MASK_DDMACH5_DA_8822B 0xffffffffL -#define BIT_DDMACH5_DA_8822B(x) (((x) & BIT_MASK_DDMACH5_DA_8822B) << BIT_SHIFT_DDMACH5_DA_8822B) -#define BIT_GET_DDMACH5_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8822B) & BIT_MASK_DDMACH5_DA_8822B) - - +#define BIT_DDMACH5_DA_8822B(x) \ + (((x) & BIT_MASK_DDMACH5_DA_8822B) << BIT_SHIFT_DDMACH5_DA_8822B) +#define BITS_DDMACH5_DA_8822B \ + (BIT_MASK_DDMACH5_DA_8822B << BIT_SHIFT_DDMACH5_DA_8822B) +#define BIT_CLEAR_DDMACH5_DA_8822B(x) ((x) & (~BITS_DDMACH5_DA_8822B)) +#define BIT_GET_DDMACH5_DA_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA_8822B) & BIT_MASK_DDMACH5_DA_8822B) +#define BIT_SET_DDMACH5_DA_8822B(x, v) \ + (BIT_CLEAR_DDMACH5_DA_8822B(x) | BIT_DDMACH5_DA_8822B(v)) /* 2 REG_REG_DDMA_CH5CTRL_8822B */ #define BIT_DDMACH5_OWN_8822B BIT(31) +#define BIT_DDMACH5_IDMEM_ERR_8822B BIT(30) #define BIT_DDMACH5_CHKSUM_EN_8822B BIT(29) #define BIT_DDMACH5_DA_W_DISABLE_8822B BIT(28) #define BIT_DDMACH5_CHKSUM_STS_8822B BIT(27) @@ -4086,10 +5992,15 @@ #define BIT_SHIFT_DDMACH5_DLEN_8822B 0 #define BIT_MASK_DDMACH5_DLEN_8822B 0x3ffff -#define BIT_DDMACH5_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH5_DLEN_8822B) << BIT_SHIFT_DDMACH5_DLEN_8822B) -#define BIT_GET_DDMACH5_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8822B) & BIT_MASK_DDMACH5_DLEN_8822B) - - +#define BIT_DDMACH5_DLEN_8822B(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN_8822B) << BIT_SHIFT_DDMACH5_DLEN_8822B) +#define BITS_DDMACH5_DLEN_8822B \ + (BIT_MASK_DDMACH5_DLEN_8822B << BIT_SHIFT_DDMACH5_DLEN_8822B) +#define BIT_CLEAR_DDMACH5_DLEN_8822B(x) ((x) & (~BITS_DDMACH5_DLEN_8822B)) +#define BIT_GET_DDMACH5_DLEN_8822B(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN_8822B) & BIT_MASK_DDMACH5_DLEN_8822B) +#define BIT_SET_DDMACH5_DLEN_8822B(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN_8822B(x) | BIT_DDMACH5_DLEN_8822B(v)) /* 2 REG_DDMA_INT_MSK_8822B */ #define BIT_DDMACH5_MSK_8822B BIT(5) @@ -4111,10 +6022,15 @@ #define BIT_SHIFT_IDDMA0_CHKSUM_8822B 0 #define BIT_MASK_IDDMA0_CHKSUM_8822B 0xffff -#define BIT_IDDMA0_CHKSUM_8822B(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8822B) << BIT_SHIFT_IDDMA0_CHKSUM_8822B) -#define BIT_GET_IDDMA0_CHKSUM_8822B(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822B) & BIT_MASK_IDDMA0_CHKSUM_8822B) - - +#define BIT_IDDMA0_CHKSUM_8822B(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM_8822B) << BIT_SHIFT_IDDMA0_CHKSUM_8822B) +#define BITS_IDDMA0_CHKSUM_8822B \ + (BIT_MASK_IDDMA0_CHKSUM_8822B << BIT_SHIFT_IDDMA0_CHKSUM_8822B) +#define BIT_CLEAR_IDDMA0_CHKSUM_8822B(x) ((x) & (~BITS_IDDMA0_CHKSUM_8822B)) +#define BIT_GET_IDDMA0_CHKSUM_8822B(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822B) & BIT_MASK_IDDMA0_CHKSUM_8822B) +#define BIT_SET_IDDMA0_CHKSUM_8822B(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM_8822B(x) | BIT_IDDMA0_CHKSUM_8822B(v)) /* 2 REG_DDMA_MONITOR_8822B */ #define BIT_IDDMA0_PERMU_UNDERFLOW_8822B BIT(14) @@ -4134,17 +6050,33 @@ #define BIT_SHIFT_PCIE_MAX_RXDMA_8822B 28 #define BIT_MASK_PCIE_MAX_RXDMA_8822B 0x7 -#define BIT_PCIE_MAX_RXDMA_8822B(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8822B) << BIT_SHIFT_PCIE_MAX_RXDMA_8822B) -#define BIT_GET_PCIE_MAX_RXDMA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822B) & BIT_MASK_PCIE_MAX_RXDMA_8822B) - +#define BIT_PCIE_MAX_RXDMA_8822B(x) \ + (((x) & BIT_MASK_PCIE_MAX_RXDMA_8822B) \ + << BIT_SHIFT_PCIE_MAX_RXDMA_8822B) +#define BITS_PCIE_MAX_RXDMA_8822B \ + (BIT_MASK_PCIE_MAX_RXDMA_8822B << BIT_SHIFT_PCIE_MAX_RXDMA_8822B) +#define BIT_CLEAR_PCIE_MAX_RXDMA_8822B(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8822B)) +#define BIT_GET_PCIE_MAX_RXDMA_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822B) & \ + BIT_MASK_PCIE_MAX_RXDMA_8822B) +#define BIT_SET_PCIE_MAX_RXDMA_8822B(x, v) \ + (BIT_CLEAR_PCIE_MAX_RXDMA_8822B(x) | BIT_PCIE_MAX_RXDMA_8822B(v)) #define BIT_MULRW_8822B BIT(27) #define BIT_SHIFT_PCIE_MAX_TXDMA_8822B 24 #define BIT_MASK_PCIE_MAX_TXDMA_8822B 0x7 -#define BIT_PCIE_MAX_TXDMA_8822B(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8822B) << BIT_SHIFT_PCIE_MAX_TXDMA_8822B) -#define BIT_GET_PCIE_MAX_TXDMA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822B) & BIT_MASK_PCIE_MAX_TXDMA_8822B) - +#define BIT_PCIE_MAX_TXDMA_8822B(x) \ + (((x) & BIT_MASK_PCIE_MAX_TXDMA_8822B) \ + << BIT_SHIFT_PCIE_MAX_TXDMA_8822B) +#define BITS_PCIE_MAX_TXDMA_8822B \ + (BIT_MASK_PCIE_MAX_TXDMA_8822B << BIT_SHIFT_PCIE_MAX_TXDMA_8822B) +#define BIT_CLEAR_PCIE_MAX_TXDMA_8822B(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8822B)) +#define BIT_GET_PCIE_MAX_TXDMA_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822B) & \ + BIT_MASK_PCIE_MAX_TXDMA_8822B) +#define BIT_SET_PCIE_MAX_TXDMA_8822B(x, v) \ + (BIT_CLEAR_PCIE_MAX_TXDMA_8822B(x) | BIT_PCIE_MAX_TXDMA_8822B(v)) #define BIT_EN_CPL_TIMEOUT_PS_8822B BIT(22) #define BIT_REG_TXDMA_FAIL_PS_8822B BIT(21) @@ -4174,428 +6106,729 @@ #define BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B 28 #define BIT_MASK_TXTTIMER_MATCH_NUM_8822B 0xf -#define BIT_TXTTIMER_MATCH_NUM_8822B(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) -#define BIT_GET_TXTTIMER_MATCH_NUM_8822B(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B) - - +#define BIT_TXTTIMER_MATCH_NUM_8822B(x) \ + (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B) \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) +#define BITS_TXTTIMER_MATCH_NUM_8822B \ + (BIT_MASK_TXTTIMER_MATCH_NUM_8822B \ + << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) +#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8822B(x) \ + ((x) & (~BITS_TXTTIMER_MATCH_NUM_8822B)) +#define BIT_GET_TXTTIMER_MATCH_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) & \ + BIT_MASK_TXTTIMER_MATCH_NUM_8822B) +#define BIT_SET_TXTTIMER_MATCH_NUM_8822B(x, v) \ + (BIT_CLEAR_TXTTIMER_MATCH_NUM_8822B(x) | \ + BIT_TXTTIMER_MATCH_NUM_8822B(v)) #define BIT_SHIFT_TXPKT_NUM_MATCH_8822B 24 #define BIT_MASK_TXPKT_NUM_MATCH_8822B 0xf -#define BIT_TXPKT_NUM_MATCH_8822B(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8822B) << BIT_SHIFT_TXPKT_NUM_MATCH_8822B) -#define BIT_GET_TXPKT_NUM_MATCH_8822B(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8822B) & BIT_MASK_TXPKT_NUM_MATCH_8822B) - - +#define BIT_TXPKT_NUM_MATCH_8822B(x) \ + (((x) & BIT_MASK_TXPKT_NUM_MATCH_8822B) \ + << BIT_SHIFT_TXPKT_NUM_MATCH_8822B) +#define BITS_TXPKT_NUM_MATCH_8822B \ + (BIT_MASK_TXPKT_NUM_MATCH_8822B << BIT_SHIFT_TXPKT_NUM_MATCH_8822B) +#define BIT_CLEAR_TXPKT_NUM_MATCH_8822B(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8822B)) +#define BIT_GET_TXPKT_NUM_MATCH_8822B(x) \ + (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8822B) & \ + BIT_MASK_TXPKT_NUM_MATCH_8822B) +#define BIT_SET_TXPKT_NUM_MATCH_8822B(x, v) \ + (BIT_CLEAR_TXPKT_NUM_MATCH_8822B(x) | BIT_TXPKT_NUM_MATCH_8822B(v)) #define BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B 20 #define BIT_MASK_RXTTIMER_MATCH_NUM_8822B 0xf -#define BIT_RXTTIMER_MATCH_NUM_8822B(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) -#define BIT_GET_RXTTIMER_MATCH_NUM_8822B(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B) - - +#define BIT_RXTTIMER_MATCH_NUM_8822B(x) \ + (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B) \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) +#define BITS_RXTTIMER_MATCH_NUM_8822B \ + (BIT_MASK_RXTTIMER_MATCH_NUM_8822B \ + << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) +#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8822B(x) \ + ((x) & (~BITS_RXTTIMER_MATCH_NUM_8822B)) +#define BIT_GET_RXTTIMER_MATCH_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) & \ + BIT_MASK_RXTTIMER_MATCH_NUM_8822B) +#define BIT_SET_RXTTIMER_MATCH_NUM_8822B(x, v) \ + (BIT_CLEAR_RXTTIMER_MATCH_NUM_8822B(x) | \ + BIT_RXTTIMER_MATCH_NUM_8822B(v)) #define BIT_SHIFT_RXPKT_NUM_MATCH_8822B 16 #define BIT_MASK_RXPKT_NUM_MATCH_8822B 0xf -#define BIT_RXPKT_NUM_MATCH_8822B(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8822B) << BIT_SHIFT_RXPKT_NUM_MATCH_8822B) -#define BIT_GET_RXPKT_NUM_MATCH_8822B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8822B) & BIT_MASK_RXPKT_NUM_MATCH_8822B) - - +#define BIT_RXPKT_NUM_MATCH_8822B(x) \ + (((x) & BIT_MASK_RXPKT_NUM_MATCH_8822B) \ + << BIT_SHIFT_RXPKT_NUM_MATCH_8822B) +#define BITS_RXPKT_NUM_MATCH_8822B \ + (BIT_MASK_RXPKT_NUM_MATCH_8822B << BIT_SHIFT_RXPKT_NUM_MATCH_8822B) +#define BIT_CLEAR_RXPKT_NUM_MATCH_8822B(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8822B)) +#define BIT_GET_RXPKT_NUM_MATCH_8822B(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8822B) & \ + BIT_MASK_RXPKT_NUM_MATCH_8822B) +#define BIT_SET_RXPKT_NUM_MATCH_8822B(x, v) \ + (BIT_CLEAR_RXPKT_NUM_MATCH_8822B(x) | BIT_RXPKT_NUM_MATCH_8822B(v)) #define BIT_SHIFT_MIGRATE_TIMER_8822B 0 #define BIT_MASK_MIGRATE_TIMER_8822B 0xffff -#define BIT_MIGRATE_TIMER_8822B(x) (((x) & BIT_MASK_MIGRATE_TIMER_8822B) << BIT_SHIFT_MIGRATE_TIMER_8822B) -#define BIT_GET_MIGRATE_TIMER_8822B(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8822B) & BIT_MASK_MIGRATE_TIMER_8822B) - - +#define BIT_MIGRATE_TIMER_8822B(x) \ + (((x) & BIT_MASK_MIGRATE_TIMER_8822B) << BIT_SHIFT_MIGRATE_TIMER_8822B) +#define BITS_MIGRATE_TIMER_8822B \ + (BIT_MASK_MIGRATE_TIMER_8822B << BIT_SHIFT_MIGRATE_TIMER_8822B) +#define BIT_CLEAR_MIGRATE_TIMER_8822B(x) ((x) & (~BITS_MIGRATE_TIMER_8822B)) +#define BIT_GET_MIGRATE_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_MIGRATE_TIMER_8822B) & BIT_MASK_MIGRATE_TIMER_8822B) +#define BIT_SET_MIGRATE_TIMER_8822B(x, v) \ + (BIT_CLEAR_MIGRATE_TIMER_8822B(x) | BIT_MIGRATE_TIMER_8822B(v)) /* 2 REG_BCNQ_TXBD_DESA_8822B */ #define BIT_SHIFT_BCNQ_TXBD_DESA_8822B 0 #define BIT_MASK_BCNQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_BCNQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8822B) << BIT_SHIFT_BCNQ_TXBD_DESA_8822B) -#define BIT_GET_BCNQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822B) & BIT_MASK_BCNQ_TXBD_DESA_8822B) - - +#define BIT_BCNQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_BCNQ_TXBD_DESA_8822B) \ + << BIT_SHIFT_BCNQ_TXBD_DESA_8822B) +#define BITS_BCNQ_TXBD_DESA_8822B \ + (BIT_MASK_BCNQ_TXBD_DESA_8822B << BIT_SHIFT_BCNQ_TXBD_DESA_8822B) +#define BIT_CLEAR_BCNQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8822B)) +#define BIT_GET_BCNQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822B) & \ + BIT_MASK_BCNQ_TXBD_DESA_8822B) +#define BIT_SET_BCNQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_BCNQ_TXBD_DESA_8822B(x) | BIT_BCNQ_TXBD_DESA_8822B(v)) /* 2 REG_MGQ_TXBD_DESA_8822B */ #define BIT_SHIFT_MGQ_TXBD_DESA_8822B 0 #define BIT_MASK_MGQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_MGQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8822B) << BIT_SHIFT_MGQ_TXBD_DESA_8822B) -#define BIT_GET_MGQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822B) & BIT_MASK_MGQ_TXBD_DESA_8822B) - - +#define BIT_MGQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_MGQ_TXBD_DESA_8822B) << BIT_SHIFT_MGQ_TXBD_DESA_8822B) +#define BITS_MGQ_TXBD_DESA_8822B \ + (BIT_MASK_MGQ_TXBD_DESA_8822B << BIT_SHIFT_MGQ_TXBD_DESA_8822B) +#define BIT_CLEAR_MGQ_TXBD_DESA_8822B(x) ((x) & (~BITS_MGQ_TXBD_DESA_8822B)) +#define BIT_GET_MGQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822B) & BIT_MASK_MGQ_TXBD_DESA_8822B) +#define BIT_SET_MGQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_MGQ_TXBD_DESA_8822B(x) | BIT_MGQ_TXBD_DESA_8822B(v)) /* 2 REG_VOQ_TXBD_DESA_8822B */ #define BIT_SHIFT_VOQ_TXBD_DESA_8822B 0 #define BIT_MASK_VOQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_VOQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8822B) << BIT_SHIFT_VOQ_TXBD_DESA_8822B) -#define BIT_GET_VOQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822B) & BIT_MASK_VOQ_TXBD_DESA_8822B) - - +#define BIT_VOQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_VOQ_TXBD_DESA_8822B) << BIT_SHIFT_VOQ_TXBD_DESA_8822B) +#define BITS_VOQ_TXBD_DESA_8822B \ + (BIT_MASK_VOQ_TXBD_DESA_8822B << BIT_SHIFT_VOQ_TXBD_DESA_8822B) +#define BIT_CLEAR_VOQ_TXBD_DESA_8822B(x) ((x) & (~BITS_VOQ_TXBD_DESA_8822B)) +#define BIT_GET_VOQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822B) & BIT_MASK_VOQ_TXBD_DESA_8822B) +#define BIT_SET_VOQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_VOQ_TXBD_DESA_8822B(x) | BIT_VOQ_TXBD_DESA_8822B(v)) /* 2 REG_VIQ_TXBD_DESA_8822B */ #define BIT_SHIFT_VIQ_TXBD_DESA_8822B 0 #define BIT_MASK_VIQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_VIQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8822B) << BIT_SHIFT_VIQ_TXBD_DESA_8822B) -#define BIT_GET_VIQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822B) & BIT_MASK_VIQ_TXBD_DESA_8822B) - - +#define BIT_VIQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_VIQ_TXBD_DESA_8822B) << BIT_SHIFT_VIQ_TXBD_DESA_8822B) +#define BITS_VIQ_TXBD_DESA_8822B \ + (BIT_MASK_VIQ_TXBD_DESA_8822B << BIT_SHIFT_VIQ_TXBD_DESA_8822B) +#define BIT_CLEAR_VIQ_TXBD_DESA_8822B(x) ((x) & (~BITS_VIQ_TXBD_DESA_8822B)) +#define BIT_GET_VIQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822B) & BIT_MASK_VIQ_TXBD_DESA_8822B) +#define BIT_SET_VIQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_VIQ_TXBD_DESA_8822B(x) | BIT_VIQ_TXBD_DESA_8822B(v)) /* 2 REG_BEQ_TXBD_DESA_8822B */ #define BIT_SHIFT_BEQ_TXBD_DESA_8822B 0 #define BIT_MASK_BEQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_BEQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8822B) << BIT_SHIFT_BEQ_TXBD_DESA_8822B) -#define BIT_GET_BEQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822B) & BIT_MASK_BEQ_TXBD_DESA_8822B) - - +#define BIT_BEQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_BEQ_TXBD_DESA_8822B) << BIT_SHIFT_BEQ_TXBD_DESA_8822B) +#define BITS_BEQ_TXBD_DESA_8822B \ + (BIT_MASK_BEQ_TXBD_DESA_8822B << BIT_SHIFT_BEQ_TXBD_DESA_8822B) +#define BIT_CLEAR_BEQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BEQ_TXBD_DESA_8822B)) +#define BIT_GET_BEQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822B) & BIT_MASK_BEQ_TXBD_DESA_8822B) +#define BIT_SET_BEQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_BEQ_TXBD_DESA_8822B(x) | BIT_BEQ_TXBD_DESA_8822B(v)) /* 2 REG_BKQ_TXBD_DESA_8822B */ #define BIT_SHIFT_BKQ_TXBD_DESA_8822B 0 #define BIT_MASK_BKQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_BKQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8822B) << BIT_SHIFT_BKQ_TXBD_DESA_8822B) -#define BIT_GET_BKQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822B) & BIT_MASK_BKQ_TXBD_DESA_8822B) - - +#define BIT_BKQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_BKQ_TXBD_DESA_8822B) << BIT_SHIFT_BKQ_TXBD_DESA_8822B) +#define BITS_BKQ_TXBD_DESA_8822B \ + (BIT_MASK_BKQ_TXBD_DESA_8822B << BIT_SHIFT_BKQ_TXBD_DESA_8822B) +#define BIT_CLEAR_BKQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BKQ_TXBD_DESA_8822B)) +#define BIT_GET_BKQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822B) & BIT_MASK_BKQ_TXBD_DESA_8822B) +#define BIT_SET_BKQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_BKQ_TXBD_DESA_8822B(x) | BIT_BKQ_TXBD_DESA_8822B(v)) /* 2 REG_RXQ_RXBD_DESA_8822B */ #define BIT_SHIFT_RXQ_RXBD_DESA_8822B 0 #define BIT_MASK_RXQ_RXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_RXQ_RXBD_DESA_8822B(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8822B) << BIT_SHIFT_RXQ_RXBD_DESA_8822B) -#define BIT_GET_RXQ_RXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822B) & BIT_MASK_RXQ_RXBD_DESA_8822B) - - +#define BIT_RXQ_RXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_RXQ_RXBD_DESA_8822B) << BIT_SHIFT_RXQ_RXBD_DESA_8822B) +#define BITS_RXQ_RXBD_DESA_8822B \ + (BIT_MASK_RXQ_RXBD_DESA_8822B << BIT_SHIFT_RXQ_RXBD_DESA_8822B) +#define BIT_CLEAR_RXQ_RXBD_DESA_8822B(x) ((x) & (~BITS_RXQ_RXBD_DESA_8822B)) +#define BIT_GET_RXQ_RXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822B) & BIT_MASK_RXQ_RXBD_DESA_8822B) +#define BIT_SET_RXQ_RXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_RXQ_RXBD_DESA_8822B(x) | BIT_RXQ_RXBD_DESA_8822B(v)) /* 2 REG_HI0Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI0Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI0Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI0Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8822B) << BIT_SHIFT_HI0Q_TXBD_DESA_8822B) -#define BIT_GET_HI0Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822B) & BIT_MASK_HI0Q_TXBD_DESA_8822B) - - +#define BIT_HI0Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_8822B) +#define BITS_HI0Q_TXBD_DESA_8822B \ + (BIT_MASK_HI0Q_TXBD_DESA_8822B << BIT_SHIFT_HI0Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI0Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8822B)) +#define BIT_GET_HI0Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI0Q_TXBD_DESA_8822B) +#define BIT_SET_HI0Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_8822B(x) | BIT_HI0Q_TXBD_DESA_8822B(v)) /* 2 REG_HI1Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI1Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI1Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI1Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8822B) << BIT_SHIFT_HI1Q_TXBD_DESA_8822B) -#define BIT_GET_HI1Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822B) & BIT_MASK_HI1Q_TXBD_DESA_8822B) - - +#define BIT_HI1Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_8822B) +#define BITS_HI1Q_TXBD_DESA_8822B \ + (BIT_MASK_HI1Q_TXBD_DESA_8822B << BIT_SHIFT_HI1Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI1Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8822B)) +#define BIT_GET_HI1Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI1Q_TXBD_DESA_8822B) +#define BIT_SET_HI1Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_8822B(x) | BIT_HI1Q_TXBD_DESA_8822B(v)) /* 2 REG_HI2Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI2Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI2Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI2Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8822B) << BIT_SHIFT_HI2Q_TXBD_DESA_8822B) -#define BIT_GET_HI2Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822B) & BIT_MASK_HI2Q_TXBD_DESA_8822B) - - +#define BIT_HI2Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_8822B) +#define BITS_HI2Q_TXBD_DESA_8822B \ + (BIT_MASK_HI2Q_TXBD_DESA_8822B << BIT_SHIFT_HI2Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI2Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8822B)) +#define BIT_GET_HI2Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI2Q_TXBD_DESA_8822B) +#define BIT_SET_HI2Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_8822B(x) | BIT_HI2Q_TXBD_DESA_8822B(v)) /* 2 REG_HI3Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI3Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI3Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI3Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8822B) << BIT_SHIFT_HI3Q_TXBD_DESA_8822B) -#define BIT_GET_HI3Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822B) & BIT_MASK_HI3Q_TXBD_DESA_8822B) - - +#define BIT_HI3Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_8822B) +#define BITS_HI3Q_TXBD_DESA_8822B \ + (BIT_MASK_HI3Q_TXBD_DESA_8822B << BIT_SHIFT_HI3Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI3Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8822B)) +#define BIT_GET_HI3Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI3Q_TXBD_DESA_8822B) +#define BIT_SET_HI3Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_8822B(x) | BIT_HI3Q_TXBD_DESA_8822B(v)) /* 2 REG_HI4Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI4Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI4Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI4Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8822B) << BIT_SHIFT_HI4Q_TXBD_DESA_8822B) -#define BIT_GET_HI4Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822B) & BIT_MASK_HI4Q_TXBD_DESA_8822B) - - +#define BIT_HI4Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_8822B) +#define BITS_HI4Q_TXBD_DESA_8822B \ + (BIT_MASK_HI4Q_TXBD_DESA_8822B << BIT_SHIFT_HI4Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI4Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8822B)) +#define BIT_GET_HI4Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI4Q_TXBD_DESA_8822B) +#define BIT_SET_HI4Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_8822B(x) | BIT_HI4Q_TXBD_DESA_8822B(v)) /* 2 REG_HI5Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI5Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI5Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI5Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8822B) << BIT_SHIFT_HI5Q_TXBD_DESA_8822B) -#define BIT_GET_HI5Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822B) & BIT_MASK_HI5Q_TXBD_DESA_8822B) - - +#define BIT_HI5Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_8822B) +#define BITS_HI5Q_TXBD_DESA_8822B \ + (BIT_MASK_HI5Q_TXBD_DESA_8822B << BIT_SHIFT_HI5Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI5Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8822B)) +#define BIT_GET_HI5Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI5Q_TXBD_DESA_8822B) +#define BIT_SET_HI5Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_8822B(x) | BIT_HI5Q_TXBD_DESA_8822B(v)) /* 2 REG_HI6Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI6Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI6Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI6Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8822B) << BIT_SHIFT_HI6Q_TXBD_DESA_8822B) -#define BIT_GET_HI6Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822B) & BIT_MASK_HI6Q_TXBD_DESA_8822B) - - +#define BIT_HI6Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_8822B) +#define BITS_HI6Q_TXBD_DESA_8822B \ + (BIT_MASK_HI6Q_TXBD_DESA_8822B << BIT_SHIFT_HI6Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI6Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8822B)) +#define BIT_GET_HI6Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI6Q_TXBD_DESA_8822B) +#define BIT_SET_HI6Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_8822B(x) | BIT_HI6Q_TXBD_DESA_8822B(v)) /* 2 REG_HI7Q_TXBD_DESA_8822B */ #define BIT_SHIFT_HI7Q_TXBD_DESA_8822B 0 #define BIT_MASK_HI7Q_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_HI7Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8822B) << BIT_SHIFT_HI7Q_TXBD_DESA_8822B) -#define BIT_GET_HI7Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822B) & BIT_MASK_HI7Q_TXBD_DESA_8822B) - - +#define BIT_HI7Q_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_8822B) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_8822B) +#define BITS_HI7Q_TXBD_DESA_8822B \ + (BIT_MASK_HI7Q_TXBD_DESA_8822B << BIT_SHIFT_HI7Q_TXBD_DESA_8822B) +#define BIT_CLEAR_HI7Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8822B)) +#define BIT_GET_HI7Q_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822B) & \ + BIT_MASK_HI7Q_TXBD_DESA_8822B) +#define BIT_SET_HI7Q_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_8822B(x) | BIT_HI7Q_TXBD_DESA_8822B(v)) /* 2 REG_MGQ_TXBD_NUM_8822B */ #define BIT_PCIE_MGQ_FLAG_8822B BIT(14) #define BIT_SHIFT_MGQ_DESC_MODE_8822B 12 #define BIT_MASK_MGQ_DESC_MODE_8822B 0x3 -#define BIT_MGQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8822B) << BIT_SHIFT_MGQ_DESC_MODE_8822B) -#define BIT_GET_MGQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822B) & BIT_MASK_MGQ_DESC_MODE_8822B) - - +#define BIT_MGQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_MGQ_DESC_MODE_8822B) << BIT_SHIFT_MGQ_DESC_MODE_8822B) +#define BITS_MGQ_DESC_MODE_8822B \ + (BIT_MASK_MGQ_DESC_MODE_8822B << BIT_SHIFT_MGQ_DESC_MODE_8822B) +#define BIT_CLEAR_MGQ_DESC_MODE_8822B(x) ((x) & (~BITS_MGQ_DESC_MODE_8822B)) +#define BIT_GET_MGQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822B) & BIT_MASK_MGQ_DESC_MODE_8822B) +#define BIT_SET_MGQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_MGQ_DESC_MODE_8822B(x) | BIT_MGQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_MGQ_DESC_NUM_8822B 0 #define BIT_MASK_MGQ_DESC_NUM_8822B 0xfff -#define BIT_MGQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8822B) << BIT_SHIFT_MGQ_DESC_NUM_8822B) -#define BIT_GET_MGQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822B) & BIT_MASK_MGQ_DESC_NUM_8822B) - - +#define BIT_MGQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_MGQ_DESC_NUM_8822B) << BIT_SHIFT_MGQ_DESC_NUM_8822B) +#define BITS_MGQ_DESC_NUM_8822B \ + (BIT_MASK_MGQ_DESC_NUM_8822B << BIT_SHIFT_MGQ_DESC_NUM_8822B) +#define BIT_CLEAR_MGQ_DESC_NUM_8822B(x) ((x) & (~BITS_MGQ_DESC_NUM_8822B)) +#define BIT_GET_MGQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822B) & BIT_MASK_MGQ_DESC_NUM_8822B) +#define BIT_SET_MGQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_MGQ_DESC_NUM_8822B(x) | BIT_MGQ_DESC_NUM_8822B(v)) /* 2 REG_RX_RXBD_NUM_8822B */ #define BIT_SYS_32_64_8822B BIT(15) #define BIT_SHIFT_BCNQ_DESC_MODE_8822B 13 #define BIT_MASK_BCNQ_DESC_MODE_8822B 0x3 -#define BIT_BCNQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8822B) << BIT_SHIFT_BCNQ_DESC_MODE_8822B) -#define BIT_GET_BCNQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822B) & BIT_MASK_BCNQ_DESC_MODE_8822B) - +#define BIT_BCNQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_BCNQ_DESC_MODE_8822B) \ + << BIT_SHIFT_BCNQ_DESC_MODE_8822B) +#define BITS_BCNQ_DESC_MODE_8822B \ + (BIT_MASK_BCNQ_DESC_MODE_8822B << BIT_SHIFT_BCNQ_DESC_MODE_8822B) +#define BIT_CLEAR_BCNQ_DESC_MODE_8822B(x) ((x) & (~BITS_BCNQ_DESC_MODE_8822B)) +#define BIT_GET_BCNQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822B) & \ + BIT_MASK_BCNQ_DESC_MODE_8822B) +#define BIT_SET_BCNQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_BCNQ_DESC_MODE_8822B(x) | BIT_BCNQ_DESC_MODE_8822B(v)) #define BIT_PCIE_BCNQ_FLAG_8822B BIT(12) #define BIT_SHIFT_RXQ_DESC_NUM_8822B 0 #define BIT_MASK_RXQ_DESC_NUM_8822B 0xfff -#define BIT_RXQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8822B) << BIT_SHIFT_RXQ_DESC_NUM_8822B) -#define BIT_GET_RXQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822B) & BIT_MASK_RXQ_DESC_NUM_8822B) - - +#define BIT_RXQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_RXQ_DESC_NUM_8822B) << BIT_SHIFT_RXQ_DESC_NUM_8822B) +#define BITS_RXQ_DESC_NUM_8822B \ + (BIT_MASK_RXQ_DESC_NUM_8822B << BIT_SHIFT_RXQ_DESC_NUM_8822B) +#define BIT_CLEAR_RXQ_DESC_NUM_8822B(x) ((x) & (~BITS_RXQ_DESC_NUM_8822B)) +#define BIT_GET_RXQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822B) & BIT_MASK_RXQ_DESC_NUM_8822B) +#define BIT_SET_RXQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_RXQ_DESC_NUM_8822B(x) | BIT_RXQ_DESC_NUM_8822B(v)) /* 2 REG_VOQ_TXBD_NUM_8822B */ #define BIT_PCIE_VOQ_FLAG_8822B BIT(14) #define BIT_SHIFT_VOQ_DESC_MODE_8822B 12 #define BIT_MASK_VOQ_DESC_MODE_8822B 0x3 -#define BIT_VOQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8822B) << BIT_SHIFT_VOQ_DESC_MODE_8822B) -#define BIT_GET_VOQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822B) & BIT_MASK_VOQ_DESC_MODE_8822B) - - +#define BIT_VOQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_VOQ_DESC_MODE_8822B) << BIT_SHIFT_VOQ_DESC_MODE_8822B) +#define BITS_VOQ_DESC_MODE_8822B \ + (BIT_MASK_VOQ_DESC_MODE_8822B << BIT_SHIFT_VOQ_DESC_MODE_8822B) +#define BIT_CLEAR_VOQ_DESC_MODE_8822B(x) ((x) & (~BITS_VOQ_DESC_MODE_8822B)) +#define BIT_GET_VOQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822B) & BIT_MASK_VOQ_DESC_MODE_8822B) +#define BIT_SET_VOQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_VOQ_DESC_MODE_8822B(x) | BIT_VOQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_VOQ_DESC_NUM_8822B 0 #define BIT_MASK_VOQ_DESC_NUM_8822B 0xfff -#define BIT_VOQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8822B) << BIT_SHIFT_VOQ_DESC_NUM_8822B) -#define BIT_GET_VOQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822B) & BIT_MASK_VOQ_DESC_NUM_8822B) - - +#define BIT_VOQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_VOQ_DESC_NUM_8822B) << BIT_SHIFT_VOQ_DESC_NUM_8822B) +#define BITS_VOQ_DESC_NUM_8822B \ + (BIT_MASK_VOQ_DESC_NUM_8822B << BIT_SHIFT_VOQ_DESC_NUM_8822B) +#define BIT_CLEAR_VOQ_DESC_NUM_8822B(x) ((x) & (~BITS_VOQ_DESC_NUM_8822B)) +#define BIT_GET_VOQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822B) & BIT_MASK_VOQ_DESC_NUM_8822B) +#define BIT_SET_VOQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_VOQ_DESC_NUM_8822B(x) | BIT_VOQ_DESC_NUM_8822B(v)) /* 2 REG_VIQ_TXBD_NUM_8822B */ #define BIT_PCIE_VIQ_FLAG_8822B BIT(14) #define BIT_SHIFT_VIQ_DESC_MODE_8822B 12 #define BIT_MASK_VIQ_DESC_MODE_8822B 0x3 -#define BIT_VIQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8822B) << BIT_SHIFT_VIQ_DESC_MODE_8822B) -#define BIT_GET_VIQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822B) & BIT_MASK_VIQ_DESC_MODE_8822B) - - +#define BIT_VIQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_VIQ_DESC_MODE_8822B) << BIT_SHIFT_VIQ_DESC_MODE_8822B) +#define BITS_VIQ_DESC_MODE_8822B \ + (BIT_MASK_VIQ_DESC_MODE_8822B << BIT_SHIFT_VIQ_DESC_MODE_8822B) +#define BIT_CLEAR_VIQ_DESC_MODE_8822B(x) ((x) & (~BITS_VIQ_DESC_MODE_8822B)) +#define BIT_GET_VIQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822B) & BIT_MASK_VIQ_DESC_MODE_8822B) +#define BIT_SET_VIQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_VIQ_DESC_MODE_8822B(x) | BIT_VIQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_VIQ_DESC_NUM_8822B 0 #define BIT_MASK_VIQ_DESC_NUM_8822B 0xfff -#define BIT_VIQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8822B) << BIT_SHIFT_VIQ_DESC_NUM_8822B) -#define BIT_GET_VIQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822B) & BIT_MASK_VIQ_DESC_NUM_8822B) - - +#define BIT_VIQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_VIQ_DESC_NUM_8822B) << BIT_SHIFT_VIQ_DESC_NUM_8822B) +#define BITS_VIQ_DESC_NUM_8822B \ + (BIT_MASK_VIQ_DESC_NUM_8822B << BIT_SHIFT_VIQ_DESC_NUM_8822B) +#define BIT_CLEAR_VIQ_DESC_NUM_8822B(x) ((x) & (~BITS_VIQ_DESC_NUM_8822B)) +#define BIT_GET_VIQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822B) & BIT_MASK_VIQ_DESC_NUM_8822B) +#define BIT_SET_VIQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_VIQ_DESC_NUM_8822B(x) | BIT_VIQ_DESC_NUM_8822B(v)) /* 2 REG_BEQ_TXBD_NUM_8822B */ #define BIT_PCIE_BEQ_FLAG_8822B BIT(14) #define BIT_SHIFT_BEQ_DESC_MODE_8822B 12 #define BIT_MASK_BEQ_DESC_MODE_8822B 0x3 -#define BIT_BEQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8822B) << BIT_SHIFT_BEQ_DESC_MODE_8822B) -#define BIT_GET_BEQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822B) & BIT_MASK_BEQ_DESC_MODE_8822B) - - +#define BIT_BEQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_BEQ_DESC_MODE_8822B) << BIT_SHIFT_BEQ_DESC_MODE_8822B) +#define BITS_BEQ_DESC_MODE_8822B \ + (BIT_MASK_BEQ_DESC_MODE_8822B << BIT_SHIFT_BEQ_DESC_MODE_8822B) +#define BIT_CLEAR_BEQ_DESC_MODE_8822B(x) ((x) & (~BITS_BEQ_DESC_MODE_8822B)) +#define BIT_GET_BEQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822B) & BIT_MASK_BEQ_DESC_MODE_8822B) +#define BIT_SET_BEQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_BEQ_DESC_MODE_8822B(x) | BIT_BEQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_BEQ_DESC_NUM_8822B 0 #define BIT_MASK_BEQ_DESC_NUM_8822B 0xfff -#define BIT_BEQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8822B) << BIT_SHIFT_BEQ_DESC_NUM_8822B) -#define BIT_GET_BEQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822B) & BIT_MASK_BEQ_DESC_NUM_8822B) - - +#define BIT_BEQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_BEQ_DESC_NUM_8822B) << BIT_SHIFT_BEQ_DESC_NUM_8822B) +#define BITS_BEQ_DESC_NUM_8822B \ + (BIT_MASK_BEQ_DESC_NUM_8822B << BIT_SHIFT_BEQ_DESC_NUM_8822B) +#define BIT_CLEAR_BEQ_DESC_NUM_8822B(x) ((x) & (~BITS_BEQ_DESC_NUM_8822B)) +#define BIT_GET_BEQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822B) & BIT_MASK_BEQ_DESC_NUM_8822B) +#define BIT_SET_BEQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_BEQ_DESC_NUM_8822B(x) | BIT_BEQ_DESC_NUM_8822B(v)) /* 2 REG_BKQ_TXBD_NUM_8822B */ #define BIT_PCIE_BKQ_FLAG_8822B BIT(14) #define BIT_SHIFT_BKQ_DESC_MODE_8822B 12 #define BIT_MASK_BKQ_DESC_MODE_8822B 0x3 -#define BIT_BKQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8822B) << BIT_SHIFT_BKQ_DESC_MODE_8822B) -#define BIT_GET_BKQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822B) & BIT_MASK_BKQ_DESC_MODE_8822B) - - +#define BIT_BKQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_BKQ_DESC_MODE_8822B) << BIT_SHIFT_BKQ_DESC_MODE_8822B) +#define BITS_BKQ_DESC_MODE_8822B \ + (BIT_MASK_BKQ_DESC_MODE_8822B << BIT_SHIFT_BKQ_DESC_MODE_8822B) +#define BIT_CLEAR_BKQ_DESC_MODE_8822B(x) ((x) & (~BITS_BKQ_DESC_MODE_8822B)) +#define BIT_GET_BKQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822B) & BIT_MASK_BKQ_DESC_MODE_8822B) +#define BIT_SET_BKQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_BKQ_DESC_MODE_8822B(x) | BIT_BKQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_BKQ_DESC_NUM_8822B 0 #define BIT_MASK_BKQ_DESC_NUM_8822B 0xfff -#define BIT_BKQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8822B) << BIT_SHIFT_BKQ_DESC_NUM_8822B) -#define BIT_GET_BKQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822B) & BIT_MASK_BKQ_DESC_NUM_8822B) - - +#define BIT_BKQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_BKQ_DESC_NUM_8822B) << BIT_SHIFT_BKQ_DESC_NUM_8822B) +#define BITS_BKQ_DESC_NUM_8822B \ + (BIT_MASK_BKQ_DESC_NUM_8822B << BIT_SHIFT_BKQ_DESC_NUM_8822B) +#define BIT_CLEAR_BKQ_DESC_NUM_8822B(x) ((x) & (~BITS_BKQ_DESC_NUM_8822B)) +#define BIT_GET_BKQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822B) & BIT_MASK_BKQ_DESC_NUM_8822B) +#define BIT_SET_BKQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_BKQ_DESC_NUM_8822B(x) | BIT_BKQ_DESC_NUM_8822B(v)) /* 2 REG_HI0Q_TXBD_NUM_8822B */ #define BIT_HI0Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI0Q_DESC_MODE_8822B 12 #define BIT_MASK_HI0Q_DESC_MODE_8822B 0x3 -#define BIT_HI0Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8822B) << BIT_SHIFT_HI0Q_DESC_MODE_8822B) -#define BIT_GET_HI0Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822B) & BIT_MASK_HI0Q_DESC_MODE_8822B) - - +#define BIT_HI0Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI0Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI0Q_DESC_MODE_8822B) +#define BITS_HI0Q_DESC_MODE_8822B \ + (BIT_MASK_HI0Q_DESC_MODE_8822B << BIT_SHIFT_HI0Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI0Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI0Q_DESC_MODE_8822B)) +#define BIT_GET_HI0Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822B) & \ + BIT_MASK_HI0Q_DESC_MODE_8822B) +#define BIT_SET_HI0Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI0Q_DESC_MODE_8822B(x) | BIT_HI0Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI0Q_DESC_NUM_8822B 0 #define BIT_MASK_HI0Q_DESC_NUM_8822B 0xfff -#define BIT_HI0Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8822B) << BIT_SHIFT_HI0Q_DESC_NUM_8822B) -#define BIT_GET_HI0Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822B) & BIT_MASK_HI0Q_DESC_NUM_8822B) - - +#define BIT_HI0Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI0Q_DESC_NUM_8822B) << BIT_SHIFT_HI0Q_DESC_NUM_8822B) +#define BITS_HI0Q_DESC_NUM_8822B \ + (BIT_MASK_HI0Q_DESC_NUM_8822B << BIT_SHIFT_HI0Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI0Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI0Q_DESC_NUM_8822B)) +#define BIT_GET_HI0Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822B) & BIT_MASK_HI0Q_DESC_NUM_8822B) +#define BIT_SET_HI0Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI0Q_DESC_NUM_8822B(x) | BIT_HI0Q_DESC_NUM_8822B(v)) /* 2 REG_HI1Q_TXBD_NUM_8822B */ #define BIT_HI1Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI1Q_DESC_MODE_8822B 12 #define BIT_MASK_HI1Q_DESC_MODE_8822B 0x3 -#define BIT_HI1Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8822B) << BIT_SHIFT_HI1Q_DESC_MODE_8822B) -#define BIT_GET_HI1Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822B) & BIT_MASK_HI1Q_DESC_MODE_8822B) - - +#define BIT_HI1Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI1Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI1Q_DESC_MODE_8822B) +#define BITS_HI1Q_DESC_MODE_8822B \ + (BIT_MASK_HI1Q_DESC_MODE_8822B << BIT_SHIFT_HI1Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI1Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI1Q_DESC_MODE_8822B)) +#define BIT_GET_HI1Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822B) & \ + BIT_MASK_HI1Q_DESC_MODE_8822B) +#define BIT_SET_HI1Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI1Q_DESC_MODE_8822B(x) | BIT_HI1Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI1Q_DESC_NUM_8822B 0 #define BIT_MASK_HI1Q_DESC_NUM_8822B 0xfff -#define BIT_HI1Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8822B) << BIT_SHIFT_HI1Q_DESC_NUM_8822B) -#define BIT_GET_HI1Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822B) & BIT_MASK_HI1Q_DESC_NUM_8822B) - - +#define BIT_HI1Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI1Q_DESC_NUM_8822B) << BIT_SHIFT_HI1Q_DESC_NUM_8822B) +#define BITS_HI1Q_DESC_NUM_8822B \ + (BIT_MASK_HI1Q_DESC_NUM_8822B << BIT_SHIFT_HI1Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI1Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI1Q_DESC_NUM_8822B)) +#define BIT_GET_HI1Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822B) & BIT_MASK_HI1Q_DESC_NUM_8822B) +#define BIT_SET_HI1Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI1Q_DESC_NUM_8822B(x) | BIT_HI1Q_DESC_NUM_8822B(v)) /* 2 REG_HI2Q_TXBD_NUM_8822B */ #define BIT_HI2Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI2Q_DESC_MODE_8822B 12 #define BIT_MASK_HI2Q_DESC_MODE_8822B 0x3 -#define BIT_HI2Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8822B) << BIT_SHIFT_HI2Q_DESC_MODE_8822B) -#define BIT_GET_HI2Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822B) & BIT_MASK_HI2Q_DESC_MODE_8822B) - - +#define BIT_HI2Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI2Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI2Q_DESC_MODE_8822B) +#define BITS_HI2Q_DESC_MODE_8822B \ + (BIT_MASK_HI2Q_DESC_MODE_8822B << BIT_SHIFT_HI2Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI2Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI2Q_DESC_MODE_8822B)) +#define BIT_GET_HI2Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822B) & \ + BIT_MASK_HI2Q_DESC_MODE_8822B) +#define BIT_SET_HI2Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI2Q_DESC_MODE_8822B(x) | BIT_HI2Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI2Q_DESC_NUM_8822B 0 #define BIT_MASK_HI2Q_DESC_NUM_8822B 0xfff -#define BIT_HI2Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8822B) << BIT_SHIFT_HI2Q_DESC_NUM_8822B) -#define BIT_GET_HI2Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822B) & BIT_MASK_HI2Q_DESC_NUM_8822B) - - +#define BIT_HI2Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI2Q_DESC_NUM_8822B) << BIT_SHIFT_HI2Q_DESC_NUM_8822B) +#define BITS_HI2Q_DESC_NUM_8822B \ + (BIT_MASK_HI2Q_DESC_NUM_8822B << BIT_SHIFT_HI2Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI2Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI2Q_DESC_NUM_8822B)) +#define BIT_GET_HI2Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822B) & BIT_MASK_HI2Q_DESC_NUM_8822B) +#define BIT_SET_HI2Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI2Q_DESC_NUM_8822B(x) | BIT_HI2Q_DESC_NUM_8822B(v)) /* 2 REG_HI3Q_TXBD_NUM_8822B */ #define BIT_HI3Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI3Q_DESC_MODE_8822B 12 #define BIT_MASK_HI3Q_DESC_MODE_8822B 0x3 -#define BIT_HI3Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8822B) << BIT_SHIFT_HI3Q_DESC_MODE_8822B) -#define BIT_GET_HI3Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822B) & BIT_MASK_HI3Q_DESC_MODE_8822B) - - +#define BIT_HI3Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI3Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI3Q_DESC_MODE_8822B) +#define BITS_HI3Q_DESC_MODE_8822B \ + (BIT_MASK_HI3Q_DESC_MODE_8822B << BIT_SHIFT_HI3Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI3Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI3Q_DESC_MODE_8822B)) +#define BIT_GET_HI3Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822B) & \ + BIT_MASK_HI3Q_DESC_MODE_8822B) +#define BIT_SET_HI3Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI3Q_DESC_MODE_8822B(x) | BIT_HI3Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI3Q_DESC_NUM_8822B 0 #define BIT_MASK_HI3Q_DESC_NUM_8822B 0xfff -#define BIT_HI3Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8822B) << BIT_SHIFT_HI3Q_DESC_NUM_8822B) -#define BIT_GET_HI3Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822B) & BIT_MASK_HI3Q_DESC_NUM_8822B) - - +#define BIT_HI3Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI3Q_DESC_NUM_8822B) << BIT_SHIFT_HI3Q_DESC_NUM_8822B) +#define BITS_HI3Q_DESC_NUM_8822B \ + (BIT_MASK_HI3Q_DESC_NUM_8822B << BIT_SHIFT_HI3Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI3Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI3Q_DESC_NUM_8822B)) +#define BIT_GET_HI3Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822B) & BIT_MASK_HI3Q_DESC_NUM_8822B) +#define BIT_SET_HI3Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI3Q_DESC_NUM_8822B(x) | BIT_HI3Q_DESC_NUM_8822B(v)) /* 2 REG_HI4Q_TXBD_NUM_8822B */ #define BIT_HI4Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI4Q_DESC_MODE_8822B 12 #define BIT_MASK_HI4Q_DESC_MODE_8822B 0x3 -#define BIT_HI4Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8822B) << BIT_SHIFT_HI4Q_DESC_MODE_8822B) -#define BIT_GET_HI4Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822B) & BIT_MASK_HI4Q_DESC_MODE_8822B) - - +#define BIT_HI4Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI4Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI4Q_DESC_MODE_8822B) +#define BITS_HI4Q_DESC_MODE_8822B \ + (BIT_MASK_HI4Q_DESC_MODE_8822B << BIT_SHIFT_HI4Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI4Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI4Q_DESC_MODE_8822B)) +#define BIT_GET_HI4Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822B) & \ + BIT_MASK_HI4Q_DESC_MODE_8822B) +#define BIT_SET_HI4Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI4Q_DESC_MODE_8822B(x) | BIT_HI4Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI4Q_DESC_NUM_8822B 0 #define BIT_MASK_HI4Q_DESC_NUM_8822B 0xfff -#define BIT_HI4Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8822B) << BIT_SHIFT_HI4Q_DESC_NUM_8822B) -#define BIT_GET_HI4Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822B) & BIT_MASK_HI4Q_DESC_NUM_8822B) - - +#define BIT_HI4Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI4Q_DESC_NUM_8822B) << BIT_SHIFT_HI4Q_DESC_NUM_8822B) +#define BITS_HI4Q_DESC_NUM_8822B \ + (BIT_MASK_HI4Q_DESC_NUM_8822B << BIT_SHIFT_HI4Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI4Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI4Q_DESC_NUM_8822B)) +#define BIT_GET_HI4Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822B) & BIT_MASK_HI4Q_DESC_NUM_8822B) +#define BIT_SET_HI4Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI4Q_DESC_NUM_8822B(x) | BIT_HI4Q_DESC_NUM_8822B(v)) /* 2 REG_HI5Q_TXBD_NUM_8822B */ #define BIT_HI5Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI5Q_DESC_MODE_8822B 12 #define BIT_MASK_HI5Q_DESC_MODE_8822B 0x3 -#define BIT_HI5Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8822B) << BIT_SHIFT_HI5Q_DESC_MODE_8822B) -#define BIT_GET_HI5Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822B) & BIT_MASK_HI5Q_DESC_MODE_8822B) - - +#define BIT_HI5Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI5Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI5Q_DESC_MODE_8822B) +#define BITS_HI5Q_DESC_MODE_8822B \ + (BIT_MASK_HI5Q_DESC_MODE_8822B << BIT_SHIFT_HI5Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI5Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI5Q_DESC_MODE_8822B)) +#define BIT_GET_HI5Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822B) & \ + BIT_MASK_HI5Q_DESC_MODE_8822B) +#define BIT_SET_HI5Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI5Q_DESC_MODE_8822B(x) | BIT_HI5Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI5Q_DESC_NUM_8822B 0 #define BIT_MASK_HI5Q_DESC_NUM_8822B 0xfff -#define BIT_HI5Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8822B) << BIT_SHIFT_HI5Q_DESC_NUM_8822B) -#define BIT_GET_HI5Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822B) & BIT_MASK_HI5Q_DESC_NUM_8822B) - - +#define BIT_HI5Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI5Q_DESC_NUM_8822B) << BIT_SHIFT_HI5Q_DESC_NUM_8822B) +#define BITS_HI5Q_DESC_NUM_8822B \ + (BIT_MASK_HI5Q_DESC_NUM_8822B << BIT_SHIFT_HI5Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI5Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI5Q_DESC_NUM_8822B)) +#define BIT_GET_HI5Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822B) & BIT_MASK_HI5Q_DESC_NUM_8822B) +#define BIT_SET_HI5Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI5Q_DESC_NUM_8822B(x) | BIT_HI5Q_DESC_NUM_8822B(v)) /* 2 REG_HI6Q_TXBD_NUM_8822B */ #define BIT_HI6Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI6Q_DESC_MODE_8822B 12 #define BIT_MASK_HI6Q_DESC_MODE_8822B 0x3 -#define BIT_HI6Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8822B) << BIT_SHIFT_HI6Q_DESC_MODE_8822B) -#define BIT_GET_HI6Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822B) & BIT_MASK_HI6Q_DESC_MODE_8822B) - - +#define BIT_HI6Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI6Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI6Q_DESC_MODE_8822B) +#define BITS_HI6Q_DESC_MODE_8822B \ + (BIT_MASK_HI6Q_DESC_MODE_8822B << BIT_SHIFT_HI6Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI6Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI6Q_DESC_MODE_8822B)) +#define BIT_GET_HI6Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822B) & \ + BIT_MASK_HI6Q_DESC_MODE_8822B) +#define BIT_SET_HI6Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI6Q_DESC_MODE_8822B(x) | BIT_HI6Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI6Q_DESC_NUM_8822B 0 #define BIT_MASK_HI6Q_DESC_NUM_8822B 0xfff -#define BIT_HI6Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8822B) << BIT_SHIFT_HI6Q_DESC_NUM_8822B) -#define BIT_GET_HI6Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822B) & BIT_MASK_HI6Q_DESC_NUM_8822B) - - +#define BIT_HI6Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI6Q_DESC_NUM_8822B) << BIT_SHIFT_HI6Q_DESC_NUM_8822B) +#define BITS_HI6Q_DESC_NUM_8822B \ + (BIT_MASK_HI6Q_DESC_NUM_8822B << BIT_SHIFT_HI6Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI6Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI6Q_DESC_NUM_8822B)) +#define BIT_GET_HI6Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822B) & BIT_MASK_HI6Q_DESC_NUM_8822B) +#define BIT_SET_HI6Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI6Q_DESC_NUM_8822B(x) | BIT_HI6Q_DESC_NUM_8822B(v)) /* 2 REG_HI7Q_TXBD_NUM_8822B */ #define BIT_HI7Q_FLAG_8822B BIT(14) #define BIT_SHIFT_HI7Q_DESC_MODE_8822B 12 #define BIT_MASK_HI7Q_DESC_MODE_8822B 0x3 -#define BIT_HI7Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8822B) << BIT_SHIFT_HI7Q_DESC_MODE_8822B) -#define BIT_GET_HI7Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822B) & BIT_MASK_HI7Q_DESC_MODE_8822B) - - +#define BIT_HI7Q_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_HI7Q_DESC_MODE_8822B) \ + << BIT_SHIFT_HI7Q_DESC_MODE_8822B) +#define BITS_HI7Q_DESC_MODE_8822B \ + (BIT_MASK_HI7Q_DESC_MODE_8822B << BIT_SHIFT_HI7Q_DESC_MODE_8822B) +#define BIT_CLEAR_HI7Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI7Q_DESC_MODE_8822B)) +#define BIT_GET_HI7Q_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822B) & \ + BIT_MASK_HI7Q_DESC_MODE_8822B) +#define BIT_SET_HI7Q_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_HI7Q_DESC_MODE_8822B(x) | BIT_HI7Q_DESC_MODE_8822B(v)) #define BIT_SHIFT_HI7Q_DESC_NUM_8822B 0 #define BIT_MASK_HI7Q_DESC_NUM_8822B 0xfff -#define BIT_HI7Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8822B) << BIT_SHIFT_HI7Q_DESC_NUM_8822B) -#define BIT_GET_HI7Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822B) & BIT_MASK_HI7Q_DESC_NUM_8822B) - - +#define BIT_HI7Q_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_HI7Q_DESC_NUM_8822B) << BIT_SHIFT_HI7Q_DESC_NUM_8822B) +#define BITS_HI7Q_DESC_NUM_8822B \ + (BIT_MASK_HI7Q_DESC_NUM_8822B << BIT_SHIFT_HI7Q_DESC_NUM_8822B) +#define BIT_CLEAR_HI7Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI7Q_DESC_NUM_8822B)) +#define BIT_GET_HI7Q_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822B) & BIT_MASK_HI7Q_DESC_NUM_8822B) +#define BIT_SET_HI7Q_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_HI7Q_DESC_NUM_8822B(x) | BIT_HI7Q_DESC_NUM_8822B(v)) /* 2 REG_TSFTIMER_HCI_8822B */ #define BIT_SHIFT_TSFT2_HCI_8822B 16 #define BIT_MASK_TSFT2_HCI_8822B 0xffff -#define BIT_TSFT2_HCI_8822B(x) (((x) & BIT_MASK_TSFT2_HCI_8822B) << BIT_SHIFT_TSFT2_HCI_8822B) -#define BIT_GET_TSFT2_HCI_8822B(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8822B) & BIT_MASK_TSFT2_HCI_8822B) - - +#define BIT_TSFT2_HCI_8822B(x) \ + (((x) & BIT_MASK_TSFT2_HCI_8822B) << BIT_SHIFT_TSFT2_HCI_8822B) +#define BITS_TSFT2_HCI_8822B \ + (BIT_MASK_TSFT2_HCI_8822B << BIT_SHIFT_TSFT2_HCI_8822B) +#define BIT_CLEAR_TSFT2_HCI_8822B(x) ((x) & (~BITS_TSFT2_HCI_8822B)) +#define BIT_GET_TSFT2_HCI_8822B(x) \ + (((x) >> BIT_SHIFT_TSFT2_HCI_8822B) & BIT_MASK_TSFT2_HCI_8822B) +#define BIT_SET_TSFT2_HCI_8822B(x, v) \ + (BIT_CLEAR_TSFT2_HCI_8822B(x) | BIT_TSFT2_HCI_8822B(v)) #define BIT_SHIFT_TSFT1_HCI_8822B 0 #define BIT_MASK_TSFT1_HCI_8822B 0xffff -#define BIT_TSFT1_HCI_8822B(x) (((x) & BIT_MASK_TSFT1_HCI_8822B) << BIT_SHIFT_TSFT1_HCI_8822B) -#define BIT_GET_TSFT1_HCI_8822B(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8822B) & BIT_MASK_TSFT1_HCI_8822B) - - +#define BIT_TSFT1_HCI_8822B(x) \ + (((x) & BIT_MASK_TSFT1_HCI_8822B) << BIT_SHIFT_TSFT1_HCI_8822B) +#define BITS_TSFT1_HCI_8822B \ + (BIT_MASK_TSFT1_HCI_8822B << BIT_SHIFT_TSFT1_HCI_8822B) +#define BIT_CLEAR_TSFT1_HCI_8822B(x) ((x) & (~BITS_TSFT1_HCI_8822B)) +#define BIT_GET_TSFT1_HCI_8822B(x) \ + (((x) >> BIT_SHIFT_TSFT1_HCI_8822B) & BIT_MASK_TSFT1_HCI_8822B) +#define BIT_SET_TSFT1_HCI_8822B(x, v) \ + (BIT_CLEAR_TSFT1_HCI_8822B(x) | BIT_TSFT1_HCI_8822B(v)) /* 2 REG_BD_RWPTR_CLR_8822B */ #define BIT_CLR_HI7Q_HW_IDX_8822B BIT(29) @@ -4631,252 +6864,406 @@ #define BIT_SHIFT_VOQ_HW_IDX_8822B 16 #define BIT_MASK_VOQ_HW_IDX_8822B 0xfff -#define BIT_VOQ_HW_IDX_8822B(x) (((x) & BIT_MASK_VOQ_HW_IDX_8822B) << BIT_SHIFT_VOQ_HW_IDX_8822B) -#define BIT_GET_VOQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8822B) & BIT_MASK_VOQ_HW_IDX_8822B) - - +#define BIT_VOQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_VOQ_HW_IDX_8822B) << BIT_SHIFT_VOQ_HW_IDX_8822B) +#define BITS_VOQ_HW_IDX_8822B \ + (BIT_MASK_VOQ_HW_IDX_8822B << BIT_SHIFT_VOQ_HW_IDX_8822B) +#define BIT_CLEAR_VOQ_HW_IDX_8822B(x) ((x) & (~BITS_VOQ_HW_IDX_8822B)) +#define BIT_GET_VOQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_VOQ_HW_IDX_8822B) & BIT_MASK_VOQ_HW_IDX_8822B) +#define BIT_SET_VOQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_VOQ_HW_IDX_8822B(x) | BIT_VOQ_HW_IDX_8822B(v)) #define BIT_SHIFT_VOQ_HOST_IDX_8822B 0 #define BIT_MASK_VOQ_HOST_IDX_8822B 0xfff -#define BIT_VOQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8822B) << BIT_SHIFT_VOQ_HOST_IDX_8822B) -#define BIT_GET_VOQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822B) & BIT_MASK_VOQ_HOST_IDX_8822B) - - +#define BIT_VOQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_VOQ_HOST_IDX_8822B) << BIT_SHIFT_VOQ_HOST_IDX_8822B) +#define BITS_VOQ_HOST_IDX_8822B \ + (BIT_MASK_VOQ_HOST_IDX_8822B << BIT_SHIFT_VOQ_HOST_IDX_8822B) +#define BIT_CLEAR_VOQ_HOST_IDX_8822B(x) ((x) & (~BITS_VOQ_HOST_IDX_8822B)) +#define BIT_GET_VOQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822B) & BIT_MASK_VOQ_HOST_IDX_8822B) +#define BIT_SET_VOQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_VOQ_HOST_IDX_8822B(x) | BIT_VOQ_HOST_IDX_8822B(v)) /* 2 REG_VIQ_TXBD_IDX_8822B */ #define BIT_SHIFT_VIQ_HW_IDX_8822B 16 #define BIT_MASK_VIQ_HW_IDX_8822B 0xfff -#define BIT_VIQ_HW_IDX_8822B(x) (((x) & BIT_MASK_VIQ_HW_IDX_8822B) << BIT_SHIFT_VIQ_HW_IDX_8822B) -#define BIT_GET_VIQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8822B) & BIT_MASK_VIQ_HW_IDX_8822B) - - +#define BIT_VIQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_VIQ_HW_IDX_8822B) << BIT_SHIFT_VIQ_HW_IDX_8822B) +#define BITS_VIQ_HW_IDX_8822B \ + (BIT_MASK_VIQ_HW_IDX_8822B << BIT_SHIFT_VIQ_HW_IDX_8822B) +#define BIT_CLEAR_VIQ_HW_IDX_8822B(x) ((x) & (~BITS_VIQ_HW_IDX_8822B)) +#define BIT_GET_VIQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_VIQ_HW_IDX_8822B) & BIT_MASK_VIQ_HW_IDX_8822B) +#define BIT_SET_VIQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_VIQ_HW_IDX_8822B(x) | BIT_VIQ_HW_IDX_8822B(v)) #define BIT_SHIFT_VIQ_HOST_IDX_8822B 0 #define BIT_MASK_VIQ_HOST_IDX_8822B 0xfff -#define BIT_VIQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8822B) << BIT_SHIFT_VIQ_HOST_IDX_8822B) -#define BIT_GET_VIQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822B) & BIT_MASK_VIQ_HOST_IDX_8822B) - - +#define BIT_VIQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_VIQ_HOST_IDX_8822B) << BIT_SHIFT_VIQ_HOST_IDX_8822B) +#define BITS_VIQ_HOST_IDX_8822B \ + (BIT_MASK_VIQ_HOST_IDX_8822B << BIT_SHIFT_VIQ_HOST_IDX_8822B) +#define BIT_CLEAR_VIQ_HOST_IDX_8822B(x) ((x) & (~BITS_VIQ_HOST_IDX_8822B)) +#define BIT_GET_VIQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822B) & BIT_MASK_VIQ_HOST_IDX_8822B) +#define BIT_SET_VIQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_VIQ_HOST_IDX_8822B(x) | BIT_VIQ_HOST_IDX_8822B(v)) /* 2 REG_BEQ_TXBD_IDX_8822B */ #define BIT_SHIFT_BEQ_HW_IDX_8822B 16 #define BIT_MASK_BEQ_HW_IDX_8822B 0xfff -#define BIT_BEQ_HW_IDX_8822B(x) (((x) & BIT_MASK_BEQ_HW_IDX_8822B) << BIT_SHIFT_BEQ_HW_IDX_8822B) -#define BIT_GET_BEQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8822B) & BIT_MASK_BEQ_HW_IDX_8822B) - - +#define BIT_BEQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_BEQ_HW_IDX_8822B) << BIT_SHIFT_BEQ_HW_IDX_8822B) +#define BITS_BEQ_HW_IDX_8822B \ + (BIT_MASK_BEQ_HW_IDX_8822B << BIT_SHIFT_BEQ_HW_IDX_8822B) +#define BIT_CLEAR_BEQ_HW_IDX_8822B(x) ((x) & (~BITS_BEQ_HW_IDX_8822B)) +#define BIT_GET_BEQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_BEQ_HW_IDX_8822B) & BIT_MASK_BEQ_HW_IDX_8822B) +#define BIT_SET_BEQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_BEQ_HW_IDX_8822B(x) | BIT_BEQ_HW_IDX_8822B(v)) #define BIT_SHIFT_BEQ_HOST_IDX_8822B 0 #define BIT_MASK_BEQ_HOST_IDX_8822B 0xfff -#define BIT_BEQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8822B) << BIT_SHIFT_BEQ_HOST_IDX_8822B) -#define BIT_GET_BEQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822B) & BIT_MASK_BEQ_HOST_IDX_8822B) - - +#define BIT_BEQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_BEQ_HOST_IDX_8822B) << BIT_SHIFT_BEQ_HOST_IDX_8822B) +#define BITS_BEQ_HOST_IDX_8822B \ + (BIT_MASK_BEQ_HOST_IDX_8822B << BIT_SHIFT_BEQ_HOST_IDX_8822B) +#define BIT_CLEAR_BEQ_HOST_IDX_8822B(x) ((x) & (~BITS_BEQ_HOST_IDX_8822B)) +#define BIT_GET_BEQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822B) & BIT_MASK_BEQ_HOST_IDX_8822B) +#define BIT_SET_BEQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_BEQ_HOST_IDX_8822B(x) | BIT_BEQ_HOST_IDX_8822B(v)) /* 2 REG_BKQ_TXBD_IDX_8822B */ #define BIT_SHIFT_BKQ_HW_IDX_8822B 16 #define BIT_MASK_BKQ_HW_IDX_8822B 0xfff -#define BIT_BKQ_HW_IDX_8822B(x) (((x) & BIT_MASK_BKQ_HW_IDX_8822B) << BIT_SHIFT_BKQ_HW_IDX_8822B) -#define BIT_GET_BKQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8822B) & BIT_MASK_BKQ_HW_IDX_8822B) - - +#define BIT_BKQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_BKQ_HW_IDX_8822B) << BIT_SHIFT_BKQ_HW_IDX_8822B) +#define BITS_BKQ_HW_IDX_8822B \ + (BIT_MASK_BKQ_HW_IDX_8822B << BIT_SHIFT_BKQ_HW_IDX_8822B) +#define BIT_CLEAR_BKQ_HW_IDX_8822B(x) ((x) & (~BITS_BKQ_HW_IDX_8822B)) +#define BIT_GET_BKQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_BKQ_HW_IDX_8822B) & BIT_MASK_BKQ_HW_IDX_8822B) +#define BIT_SET_BKQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_BKQ_HW_IDX_8822B(x) | BIT_BKQ_HW_IDX_8822B(v)) #define BIT_SHIFT_BKQ_HOST_IDX_8822B 0 #define BIT_MASK_BKQ_HOST_IDX_8822B 0xfff -#define BIT_BKQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8822B) << BIT_SHIFT_BKQ_HOST_IDX_8822B) -#define BIT_GET_BKQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822B) & BIT_MASK_BKQ_HOST_IDX_8822B) - - +#define BIT_BKQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_BKQ_HOST_IDX_8822B) << BIT_SHIFT_BKQ_HOST_IDX_8822B) +#define BITS_BKQ_HOST_IDX_8822B \ + (BIT_MASK_BKQ_HOST_IDX_8822B << BIT_SHIFT_BKQ_HOST_IDX_8822B) +#define BIT_CLEAR_BKQ_HOST_IDX_8822B(x) ((x) & (~BITS_BKQ_HOST_IDX_8822B)) +#define BIT_GET_BKQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822B) & BIT_MASK_BKQ_HOST_IDX_8822B) +#define BIT_SET_BKQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_BKQ_HOST_IDX_8822B(x) | BIT_BKQ_HOST_IDX_8822B(v)) /* 2 REG_MGQ_TXBD_IDX_8822B */ #define BIT_SHIFT_MGQ_HW_IDX_8822B 16 #define BIT_MASK_MGQ_HW_IDX_8822B 0xfff -#define BIT_MGQ_HW_IDX_8822B(x) (((x) & BIT_MASK_MGQ_HW_IDX_8822B) << BIT_SHIFT_MGQ_HW_IDX_8822B) -#define BIT_GET_MGQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8822B) & BIT_MASK_MGQ_HW_IDX_8822B) - - +#define BIT_MGQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_MGQ_HW_IDX_8822B) << BIT_SHIFT_MGQ_HW_IDX_8822B) +#define BITS_MGQ_HW_IDX_8822B \ + (BIT_MASK_MGQ_HW_IDX_8822B << BIT_SHIFT_MGQ_HW_IDX_8822B) +#define BIT_CLEAR_MGQ_HW_IDX_8822B(x) ((x) & (~BITS_MGQ_HW_IDX_8822B)) +#define BIT_GET_MGQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_HW_IDX_8822B) & BIT_MASK_MGQ_HW_IDX_8822B) +#define BIT_SET_MGQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_MGQ_HW_IDX_8822B(x) | BIT_MGQ_HW_IDX_8822B(v)) #define BIT_SHIFT_MGQ_HOST_IDX_8822B 0 #define BIT_MASK_MGQ_HOST_IDX_8822B 0xfff -#define BIT_MGQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8822B) << BIT_SHIFT_MGQ_HOST_IDX_8822B) -#define BIT_GET_MGQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822B) & BIT_MASK_MGQ_HOST_IDX_8822B) - - +#define BIT_MGQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_MGQ_HOST_IDX_8822B) << BIT_SHIFT_MGQ_HOST_IDX_8822B) +#define BITS_MGQ_HOST_IDX_8822B \ + (BIT_MASK_MGQ_HOST_IDX_8822B << BIT_SHIFT_MGQ_HOST_IDX_8822B) +#define BIT_CLEAR_MGQ_HOST_IDX_8822B(x) ((x) & (~BITS_MGQ_HOST_IDX_8822B)) +#define BIT_GET_MGQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822B) & BIT_MASK_MGQ_HOST_IDX_8822B) +#define BIT_SET_MGQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_MGQ_HOST_IDX_8822B(x) | BIT_MGQ_HOST_IDX_8822B(v)) /* 2 REG_RXQ_RXBD_IDX_8822B */ #define BIT_SHIFT_RXQ_HW_IDX_8822B 16 #define BIT_MASK_RXQ_HW_IDX_8822B 0xfff -#define BIT_RXQ_HW_IDX_8822B(x) (((x) & BIT_MASK_RXQ_HW_IDX_8822B) << BIT_SHIFT_RXQ_HW_IDX_8822B) -#define BIT_GET_RXQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8822B) & BIT_MASK_RXQ_HW_IDX_8822B) - - +#define BIT_RXQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_RXQ_HW_IDX_8822B) << BIT_SHIFT_RXQ_HW_IDX_8822B) +#define BITS_RXQ_HW_IDX_8822B \ + (BIT_MASK_RXQ_HW_IDX_8822B << BIT_SHIFT_RXQ_HW_IDX_8822B) +#define BIT_CLEAR_RXQ_HW_IDX_8822B(x) ((x) & (~BITS_RXQ_HW_IDX_8822B)) +#define BIT_GET_RXQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RXQ_HW_IDX_8822B) & BIT_MASK_RXQ_HW_IDX_8822B) +#define BIT_SET_RXQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_RXQ_HW_IDX_8822B(x) | BIT_RXQ_HW_IDX_8822B(v)) #define BIT_SHIFT_RXQ_HOST_IDX_8822B 0 #define BIT_MASK_RXQ_HOST_IDX_8822B 0xfff -#define BIT_RXQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8822B) << BIT_SHIFT_RXQ_HOST_IDX_8822B) -#define BIT_GET_RXQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822B) & BIT_MASK_RXQ_HOST_IDX_8822B) - - +#define BIT_RXQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_RXQ_HOST_IDX_8822B) << BIT_SHIFT_RXQ_HOST_IDX_8822B) +#define BITS_RXQ_HOST_IDX_8822B \ + (BIT_MASK_RXQ_HOST_IDX_8822B << BIT_SHIFT_RXQ_HOST_IDX_8822B) +#define BIT_CLEAR_RXQ_HOST_IDX_8822B(x) ((x) & (~BITS_RXQ_HOST_IDX_8822B)) +#define BIT_GET_RXQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822B) & BIT_MASK_RXQ_HOST_IDX_8822B) +#define BIT_SET_RXQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_RXQ_HOST_IDX_8822B(x) | BIT_RXQ_HOST_IDX_8822B(v)) /* 2 REG_HI0Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI0Q_HW_IDX_8822B 16 #define BIT_MASK_HI0Q_HW_IDX_8822B 0xfff -#define BIT_HI0Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8822B) << BIT_SHIFT_HI0Q_HW_IDX_8822B) -#define BIT_GET_HI0Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822B) & BIT_MASK_HI0Q_HW_IDX_8822B) - - +#define BIT_HI0Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI0Q_HW_IDX_8822B) << BIT_SHIFT_HI0Q_HW_IDX_8822B) +#define BITS_HI0Q_HW_IDX_8822B \ + (BIT_MASK_HI0Q_HW_IDX_8822B << BIT_SHIFT_HI0Q_HW_IDX_8822B) +#define BIT_CLEAR_HI0Q_HW_IDX_8822B(x) ((x) & (~BITS_HI0Q_HW_IDX_8822B)) +#define BIT_GET_HI0Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822B) & BIT_MASK_HI0Q_HW_IDX_8822B) +#define BIT_SET_HI0Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI0Q_HW_IDX_8822B(x) | BIT_HI0Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI0Q_HOST_IDX_8822B 0 #define BIT_MASK_HI0Q_HOST_IDX_8822B 0xfff -#define BIT_HI0Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8822B) << BIT_SHIFT_HI0Q_HOST_IDX_8822B) -#define BIT_GET_HI0Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822B) & BIT_MASK_HI0Q_HOST_IDX_8822B) - - +#define BIT_HI0Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI0Q_HOST_IDX_8822B) << BIT_SHIFT_HI0Q_HOST_IDX_8822B) +#define BITS_HI0Q_HOST_IDX_8822B \ + (BIT_MASK_HI0Q_HOST_IDX_8822B << BIT_SHIFT_HI0Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI0Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI0Q_HOST_IDX_8822B)) +#define BIT_GET_HI0Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822B) & BIT_MASK_HI0Q_HOST_IDX_8822B) +#define BIT_SET_HI0Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI0Q_HOST_IDX_8822B(x) | BIT_HI0Q_HOST_IDX_8822B(v)) /* 2 REG_HI1Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI1Q_HW_IDX_8822B 16 #define BIT_MASK_HI1Q_HW_IDX_8822B 0xfff -#define BIT_HI1Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8822B) << BIT_SHIFT_HI1Q_HW_IDX_8822B) -#define BIT_GET_HI1Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822B) & BIT_MASK_HI1Q_HW_IDX_8822B) - - +#define BIT_HI1Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI1Q_HW_IDX_8822B) << BIT_SHIFT_HI1Q_HW_IDX_8822B) +#define BITS_HI1Q_HW_IDX_8822B \ + (BIT_MASK_HI1Q_HW_IDX_8822B << BIT_SHIFT_HI1Q_HW_IDX_8822B) +#define BIT_CLEAR_HI1Q_HW_IDX_8822B(x) ((x) & (~BITS_HI1Q_HW_IDX_8822B)) +#define BIT_GET_HI1Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822B) & BIT_MASK_HI1Q_HW_IDX_8822B) +#define BIT_SET_HI1Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI1Q_HW_IDX_8822B(x) | BIT_HI1Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI1Q_HOST_IDX_8822B 0 #define BIT_MASK_HI1Q_HOST_IDX_8822B 0xfff -#define BIT_HI1Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8822B) << BIT_SHIFT_HI1Q_HOST_IDX_8822B) -#define BIT_GET_HI1Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822B) & BIT_MASK_HI1Q_HOST_IDX_8822B) - - +#define BIT_HI1Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI1Q_HOST_IDX_8822B) << BIT_SHIFT_HI1Q_HOST_IDX_8822B) +#define BITS_HI1Q_HOST_IDX_8822B \ + (BIT_MASK_HI1Q_HOST_IDX_8822B << BIT_SHIFT_HI1Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI1Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI1Q_HOST_IDX_8822B)) +#define BIT_GET_HI1Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822B) & BIT_MASK_HI1Q_HOST_IDX_8822B) +#define BIT_SET_HI1Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI1Q_HOST_IDX_8822B(x) | BIT_HI1Q_HOST_IDX_8822B(v)) /* 2 REG_HI2Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI2Q_HW_IDX_8822B 16 #define BIT_MASK_HI2Q_HW_IDX_8822B 0xfff -#define BIT_HI2Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8822B) << BIT_SHIFT_HI2Q_HW_IDX_8822B) -#define BIT_GET_HI2Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822B) & BIT_MASK_HI2Q_HW_IDX_8822B) - - +#define BIT_HI2Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI2Q_HW_IDX_8822B) << BIT_SHIFT_HI2Q_HW_IDX_8822B) +#define BITS_HI2Q_HW_IDX_8822B \ + (BIT_MASK_HI2Q_HW_IDX_8822B << BIT_SHIFT_HI2Q_HW_IDX_8822B) +#define BIT_CLEAR_HI2Q_HW_IDX_8822B(x) ((x) & (~BITS_HI2Q_HW_IDX_8822B)) +#define BIT_GET_HI2Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822B) & BIT_MASK_HI2Q_HW_IDX_8822B) +#define BIT_SET_HI2Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI2Q_HW_IDX_8822B(x) | BIT_HI2Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI2Q_HOST_IDX_8822B 0 #define BIT_MASK_HI2Q_HOST_IDX_8822B 0xfff -#define BIT_HI2Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8822B) << BIT_SHIFT_HI2Q_HOST_IDX_8822B) -#define BIT_GET_HI2Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822B) & BIT_MASK_HI2Q_HOST_IDX_8822B) - - +#define BIT_HI2Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI2Q_HOST_IDX_8822B) << BIT_SHIFT_HI2Q_HOST_IDX_8822B) +#define BITS_HI2Q_HOST_IDX_8822B \ + (BIT_MASK_HI2Q_HOST_IDX_8822B << BIT_SHIFT_HI2Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI2Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI2Q_HOST_IDX_8822B)) +#define BIT_GET_HI2Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822B) & BIT_MASK_HI2Q_HOST_IDX_8822B) +#define BIT_SET_HI2Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI2Q_HOST_IDX_8822B(x) | BIT_HI2Q_HOST_IDX_8822B(v)) /* 2 REG_HI3Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI3Q_HW_IDX_8822B 16 #define BIT_MASK_HI3Q_HW_IDX_8822B 0xfff -#define BIT_HI3Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8822B) << BIT_SHIFT_HI3Q_HW_IDX_8822B) -#define BIT_GET_HI3Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822B) & BIT_MASK_HI3Q_HW_IDX_8822B) - - +#define BIT_HI3Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI3Q_HW_IDX_8822B) << BIT_SHIFT_HI3Q_HW_IDX_8822B) +#define BITS_HI3Q_HW_IDX_8822B \ + (BIT_MASK_HI3Q_HW_IDX_8822B << BIT_SHIFT_HI3Q_HW_IDX_8822B) +#define BIT_CLEAR_HI3Q_HW_IDX_8822B(x) ((x) & (~BITS_HI3Q_HW_IDX_8822B)) +#define BIT_GET_HI3Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822B) & BIT_MASK_HI3Q_HW_IDX_8822B) +#define BIT_SET_HI3Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI3Q_HW_IDX_8822B(x) | BIT_HI3Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI3Q_HOST_IDX_8822B 0 #define BIT_MASK_HI3Q_HOST_IDX_8822B 0xfff -#define BIT_HI3Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8822B) << BIT_SHIFT_HI3Q_HOST_IDX_8822B) -#define BIT_GET_HI3Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822B) & BIT_MASK_HI3Q_HOST_IDX_8822B) - - +#define BIT_HI3Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI3Q_HOST_IDX_8822B) << BIT_SHIFT_HI3Q_HOST_IDX_8822B) +#define BITS_HI3Q_HOST_IDX_8822B \ + (BIT_MASK_HI3Q_HOST_IDX_8822B << BIT_SHIFT_HI3Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI3Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI3Q_HOST_IDX_8822B)) +#define BIT_GET_HI3Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822B) & BIT_MASK_HI3Q_HOST_IDX_8822B) +#define BIT_SET_HI3Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI3Q_HOST_IDX_8822B(x) | BIT_HI3Q_HOST_IDX_8822B(v)) /* 2 REG_HI4Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI4Q_HW_IDX_8822B 16 #define BIT_MASK_HI4Q_HW_IDX_8822B 0xfff -#define BIT_HI4Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8822B) << BIT_SHIFT_HI4Q_HW_IDX_8822B) -#define BIT_GET_HI4Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822B) & BIT_MASK_HI4Q_HW_IDX_8822B) - - +#define BIT_HI4Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI4Q_HW_IDX_8822B) << BIT_SHIFT_HI4Q_HW_IDX_8822B) +#define BITS_HI4Q_HW_IDX_8822B \ + (BIT_MASK_HI4Q_HW_IDX_8822B << BIT_SHIFT_HI4Q_HW_IDX_8822B) +#define BIT_CLEAR_HI4Q_HW_IDX_8822B(x) ((x) & (~BITS_HI4Q_HW_IDX_8822B)) +#define BIT_GET_HI4Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822B) & BIT_MASK_HI4Q_HW_IDX_8822B) +#define BIT_SET_HI4Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI4Q_HW_IDX_8822B(x) | BIT_HI4Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI4Q_HOST_IDX_8822B 0 #define BIT_MASK_HI4Q_HOST_IDX_8822B 0xfff -#define BIT_HI4Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8822B) << BIT_SHIFT_HI4Q_HOST_IDX_8822B) -#define BIT_GET_HI4Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822B) & BIT_MASK_HI4Q_HOST_IDX_8822B) - - +#define BIT_HI4Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI4Q_HOST_IDX_8822B) << BIT_SHIFT_HI4Q_HOST_IDX_8822B) +#define BITS_HI4Q_HOST_IDX_8822B \ + (BIT_MASK_HI4Q_HOST_IDX_8822B << BIT_SHIFT_HI4Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI4Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI4Q_HOST_IDX_8822B)) +#define BIT_GET_HI4Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822B) & BIT_MASK_HI4Q_HOST_IDX_8822B) +#define BIT_SET_HI4Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI4Q_HOST_IDX_8822B(x) | BIT_HI4Q_HOST_IDX_8822B(v)) /* 2 REG_HI5Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI5Q_HW_IDX_8822B 16 #define BIT_MASK_HI5Q_HW_IDX_8822B 0xfff -#define BIT_HI5Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8822B) << BIT_SHIFT_HI5Q_HW_IDX_8822B) -#define BIT_GET_HI5Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822B) & BIT_MASK_HI5Q_HW_IDX_8822B) - - +#define BIT_HI5Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI5Q_HW_IDX_8822B) << BIT_SHIFT_HI5Q_HW_IDX_8822B) +#define BITS_HI5Q_HW_IDX_8822B \ + (BIT_MASK_HI5Q_HW_IDX_8822B << BIT_SHIFT_HI5Q_HW_IDX_8822B) +#define BIT_CLEAR_HI5Q_HW_IDX_8822B(x) ((x) & (~BITS_HI5Q_HW_IDX_8822B)) +#define BIT_GET_HI5Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822B) & BIT_MASK_HI5Q_HW_IDX_8822B) +#define BIT_SET_HI5Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI5Q_HW_IDX_8822B(x) | BIT_HI5Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI5Q_HOST_IDX_8822B 0 #define BIT_MASK_HI5Q_HOST_IDX_8822B 0xfff -#define BIT_HI5Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8822B) << BIT_SHIFT_HI5Q_HOST_IDX_8822B) -#define BIT_GET_HI5Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822B) & BIT_MASK_HI5Q_HOST_IDX_8822B) - - +#define BIT_HI5Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI5Q_HOST_IDX_8822B) << BIT_SHIFT_HI5Q_HOST_IDX_8822B) +#define BITS_HI5Q_HOST_IDX_8822B \ + (BIT_MASK_HI5Q_HOST_IDX_8822B << BIT_SHIFT_HI5Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI5Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI5Q_HOST_IDX_8822B)) +#define BIT_GET_HI5Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822B) & BIT_MASK_HI5Q_HOST_IDX_8822B) +#define BIT_SET_HI5Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI5Q_HOST_IDX_8822B(x) | BIT_HI5Q_HOST_IDX_8822B(v)) /* 2 REG_HI6Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI6Q_HW_IDX_8822B 16 #define BIT_MASK_HI6Q_HW_IDX_8822B 0xfff -#define BIT_HI6Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8822B) << BIT_SHIFT_HI6Q_HW_IDX_8822B) -#define BIT_GET_HI6Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822B) & BIT_MASK_HI6Q_HW_IDX_8822B) - - +#define BIT_HI6Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI6Q_HW_IDX_8822B) << BIT_SHIFT_HI6Q_HW_IDX_8822B) +#define BITS_HI6Q_HW_IDX_8822B \ + (BIT_MASK_HI6Q_HW_IDX_8822B << BIT_SHIFT_HI6Q_HW_IDX_8822B) +#define BIT_CLEAR_HI6Q_HW_IDX_8822B(x) ((x) & (~BITS_HI6Q_HW_IDX_8822B)) +#define BIT_GET_HI6Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822B) & BIT_MASK_HI6Q_HW_IDX_8822B) +#define BIT_SET_HI6Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI6Q_HW_IDX_8822B(x) | BIT_HI6Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI6Q_HOST_IDX_8822B 0 #define BIT_MASK_HI6Q_HOST_IDX_8822B 0xfff -#define BIT_HI6Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8822B) << BIT_SHIFT_HI6Q_HOST_IDX_8822B) -#define BIT_GET_HI6Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822B) & BIT_MASK_HI6Q_HOST_IDX_8822B) - - +#define BIT_HI6Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI6Q_HOST_IDX_8822B) << BIT_SHIFT_HI6Q_HOST_IDX_8822B) +#define BITS_HI6Q_HOST_IDX_8822B \ + (BIT_MASK_HI6Q_HOST_IDX_8822B << BIT_SHIFT_HI6Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI6Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI6Q_HOST_IDX_8822B)) +#define BIT_GET_HI6Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822B) & BIT_MASK_HI6Q_HOST_IDX_8822B) +#define BIT_SET_HI6Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI6Q_HOST_IDX_8822B(x) | BIT_HI6Q_HOST_IDX_8822B(v)) /* 2 REG_HI7Q_TXBD_IDX_8822B */ #define BIT_SHIFT_HI7Q_HW_IDX_8822B 16 #define BIT_MASK_HI7Q_HW_IDX_8822B 0xfff -#define BIT_HI7Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8822B) << BIT_SHIFT_HI7Q_HW_IDX_8822B) -#define BIT_GET_HI7Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822B) & BIT_MASK_HI7Q_HW_IDX_8822B) - - +#define BIT_HI7Q_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_HI7Q_HW_IDX_8822B) << BIT_SHIFT_HI7Q_HW_IDX_8822B) +#define BITS_HI7Q_HW_IDX_8822B \ + (BIT_MASK_HI7Q_HW_IDX_8822B << BIT_SHIFT_HI7Q_HW_IDX_8822B) +#define BIT_CLEAR_HI7Q_HW_IDX_8822B(x) ((x) & (~BITS_HI7Q_HW_IDX_8822B)) +#define BIT_GET_HI7Q_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822B) & BIT_MASK_HI7Q_HW_IDX_8822B) +#define BIT_SET_HI7Q_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_HI7Q_HW_IDX_8822B(x) | BIT_HI7Q_HW_IDX_8822B(v)) #define BIT_SHIFT_HI7Q_HOST_IDX_8822B 0 #define BIT_MASK_HI7Q_HOST_IDX_8822B 0xfff -#define BIT_HI7Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8822B) << BIT_SHIFT_HI7Q_HOST_IDX_8822B) -#define BIT_GET_HI7Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822B) & BIT_MASK_HI7Q_HOST_IDX_8822B) - - +#define BIT_HI7Q_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_HI7Q_HOST_IDX_8822B) << BIT_SHIFT_HI7Q_HOST_IDX_8822B) +#define BITS_HI7Q_HOST_IDX_8822B \ + (BIT_MASK_HI7Q_HOST_IDX_8822B << BIT_SHIFT_HI7Q_HOST_IDX_8822B) +#define BIT_CLEAR_HI7Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI7Q_HOST_IDX_8822B)) +#define BIT_GET_HI7Q_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822B) & BIT_MASK_HI7Q_HOST_IDX_8822B) +#define BIT_SET_HI7Q_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_HI7Q_HOST_IDX_8822B(x) | BIT_HI7Q_HOST_IDX_8822B(v)) /* 2 REG_DBG_SEL_V1_8822B */ #define BIT_SHIFT_DBG_SEL_8822B 0 #define BIT_MASK_DBG_SEL_8822B 0xff -#define BIT_DBG_SEL_8822B(x) (((x) & BIT_MASK_DBG_SEL_8822B) << BIT_SHIFT_DBG_SEL_8822B) -#define BIT_GET_DBG_SEL_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_8822B) & BIT_MASK_DBG_SEL_8822B) - - +#define BIT_DBG_SEL_8822B(x) \ + (((x) & BIT_MASK_DBG_SEL_8822B) << BIT_SHIFT_DBG_SEL_8822B) +#define BITS_DBG_SEL_8822B (BIT_MASK_DBG_SEL_8822B << BIT_SHIFT_DBG_SEL_8822B) +#define BIT_CLEAR_DBG_SEL_8822B(x) ((x) & (~BITS_DBG_SEL_8822B)) +#define BIT_GET_DBG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_8822B) & BIT_MASK_DBG_SEL_8822B) +#define BIT_SET_DBG_SEL_8822B(x, v) \ + (BIT_CLEAR_DBG_SEL_8822B(x) | BIT_DBG_SEL_8822B(v)) /* 2 REG_PCIE_HRPWM1_V1_8822B */ #define BIT_SHIFT_PCIE_HRPWM_8822B 0 #define BIT_MASK_PCIE_HRPWM_8822B 0xff -#define BIT_PCIE_HRPWM_8822B(x) (((x) & BIT_MASK_PCIE_HRPWM_8822B) << BIT_SHIFT_PCIE_HRPWM_8822B) -#define BIT_GET_PCIE_HRPWM_8822B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8822B) & BIT_MASK_PCIE_HRPWM_8822B) - - +#define BIT_PCIE_HRPWM_8822B(x) \ + (((x) & BIT_MASK_PCIE_HRPWM_8822B) << BIT_SHIFT_PCIE_HRPWM_8822B) +#define BITS_PCIE_HRPWM_8822B \ + (BIT_MASK_PCIE_HRPWM_8822B << BIT_SHIFT_PCIE_HRPWM_8822B) +#define BIT_CLEAR_PCIE_HRPWM_8822B(x) ((x) & (~BITS_PCIE_HRPWM_8822B)) +#define BIT_GET_PCIE_HRPWM_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM_8822B) & BIT_MASK_PCIE_HRPWM_8822B) +#define BIT_SET_PCIE_HRPWM_8822B(x, v) \ + (BIT_CLEAR_PCIE_HRPWM_8822B(x) | BIT_PCIE_HRPWM_8822B(v)) /* 2 REG_PCIE_HCPWM1_V1_8822B */ #define BIT_SHIFT_PCIE_HCPWM_8822B 0 #define BIT_MASK_PCIE_HCPWM_8822B 0xff -#define BIT_PCIE_HCPWM_8822B(x) (((x) & BIT_MASK_PCIE_HCPWM_8822B) << BIT_SHIFT_PCIE_HCPWM_8822B) -#define BIT_GET_PCIE_HCPWM_8822B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8822B) & BIT_MASK_PCIE_HCPWM_8822B) - - +#define BIT_PCIE_HCPWM_8822B(x) \ + (((x) & BIT_MASK_PCIE_HCPWM_8822B) << BIT_SHIFT_PCIE_HCPWM_8822B) +#define BITS_PCIE_HCPWM_8822B \ + (BIT_MASK_PCIE_HCPWM_8822B << BIT_SHIFT_PCIE_HCPWM_8822B) +#define BIT_CLEAR_PCIE_HCPWM_8822B(x) ((x) & (~BITS_PCIE_HCPWM_8822B)) +#define BIT_GET_PCIE_HCPWM_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM_8822B) & BIT_MASK_PCIE_HCPWM_8822B) +#define BIT_SET_PCIE_HCPWM_8822B(x, v) \ + (BIT_CLEAR_PCIE_HCPWM_8822B(x) | BIT_PCIE_HCPWM_8822B(v)) /* 2 REG_PCIE_CTRL2_8822B */ #define BIT_DIS_TXDMA_PRE_8822B BIT(7) @@ -4884,9 +7271,15 @@ #define BIT_SHIFT_HPS_CLKR_PCIE_8822B 4 #define BIT_MASK_HPS_CLKR_PCIE_8822B 0x3 -#define BIT_HPS_CLKR_PCIE_8822B(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8822B) << BIT_SHIFT_HPS_CLKR_PCIE_8822B) -#define BIT_GET_HPS_CLKR_PCIE_8822B(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822B) & BIT_MASK_HPS_CLKR_PCIE_8822B) - +#define BIT_HPS_CLKR_PCIE_8822B(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE_8822B) << BIT_SHIFT_HPS_CLKR_PCIE_8822B) +#define BITS_HPS_CLKR_PCIE_8822B \ + (BIT_MASK_HPS_CLKR_PCIE_8822B << BIT_SHIFT_HPS_CLKR_PCIE_8822B) +#define BIT_CLEAR_HPS_CLKR_PCIE_8822B(x) ((x) & (~BITS_HPS_CLKR_PCIE_8822B)) +#define BIT_GET_HPS_CLKR_PCIE_8822B(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822B) & BIT_MASK_HPS_CLKR_PCIE_8822B) +#define BIT_SET_HPS_CLKR_PCIE_8822B(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE_8822B(x) | BIT_HPS_CLKR_PCIE_8822B(v)) #define BIT_PCIE_INT_8822B BIT(3) #define BIT_TXFLAG_EXIT_L1_EN_8822B BIT(2) @@ -4897,55 +7290,88 @@ #define BIT_SHIFT_PCIE_HRPWM2_8822B 0 #define BIT_MASK_PCIE_HRPWM2_8822B 0xffff -#define BIT_PCIE_HRPWM2_8822B(x) (((x) & BIT_MASK_PCIE_HRPWM2_8822B) << BIT_SHIFT_PCIE_HRPWM2_8822B) -#define BIT_GET_PCIE_HRPWM2_8822B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8822B) & BIT_MASK_PCIE_HRPWM2_8822B) - - +#define BIT_PCIE_HRPWM2_8822B(x) \ + (((x) & BIT_MASK_PCIE_HRPWM2_8822B) << BIT_SHIFT_PCIE_HRPWM2_8822B) +#define BITS_PCIE_HRPWM2_8822B \ + (BIT_MASK_PCIE_HRPWM2_8822B << BIT_SHIFT_PCIE_HRPWM2_8822B) +#define BIT_CLEAR_PCIE_HRPWM2_8822B(x) ((x) & (~BITS_PCIE_HRPWM2_8822B)) +#define BIT_GET_PCIE_HRPWM2_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM2_8822B) & BIT_MASK_PCIE_HRPWM2_8822B) +#define BIT_SET_PCIE_HRPWM2_8822B(x, v) \ + (BIT_CLEAR_PCIE_HRPWM2_8822B(x) | BIT_PCIE_HRPWM2_8822B(v)) /* 2 REG_PCIE_HCPWM2_V1_8822B */ #define BIT_SHIFT_PCIE_HCPWM2_8822B 0 #define BIT_MASK_PCIE_HCPWM2_8822B 0xffff -#define BIT_PCIE_HCPWM2_8822B(x) (((x) & BIT_MASK_PCIE_HCPWM2_8822B) << BIT_SHIFT_PCIE_HCPWM2_8822B) -#define BIT_GET_PCIE_HCPWM2_8822B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8822B) & BIT_MASK_PCIE_HCPWM2_8822B) - - +#define BIT_PCIE_HCPWM2_8822B(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2_8822B) << BIT_SHIFT_PCIE_HCPWM2_8822B) +#define BITS_PCIE_HCPWM2_8822B \ + (BIT_MASK_PCIE_HCPWM2_8822B << BIT_SHIFT_PCIE_HCPWM2_8822B) +#define BIT_CLEAR_PCIE_HCPWM2_8822B(x) ((x) & (~BITS_PCIE_HCPWM2_8822B)) +#define BIT_GET_PCIE_HCPWM2_8822B(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2_8822B) & BIT_MASK_PCIE_HCPWM2_8822B) +#define BIT_SET_PCIE_HCPWM2_8822B(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2_8822B(x) | BIT_PCIE_HCPWM2_8822B(v)) /* 2 REG_PCIE_H2C_MSG_V1_8822B */ #define BIT_SHIFT_DRV2FW_INFO_8822B 0 #define BIT_MASK_DRV2FW_INFO_8822B 0xffffffffL -#define BIT_DRV2FW_INFO_8822B(x) (((x) & BIT_MASK_DRV2FW_INFO_8822B) << BIT_SHIFT_DRV2FW_INFO_8822B) -#define BIT_GET_DRV2FW_INFO_8822B(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8822B) & BIT_MASK_DRV2FW_INFO_8822B) - - +#define BIT_DRV2FW_INFO_8822B(x) \ + (((x) & BIT_MASK_DRV2FW_INFO_8822B) << BIT_SHIFT_DRV2FW_INFO_8822B) +#define BITS_DRV2FW_INFO_8822B \ + (BIT_MASK_DRV2FW_INFO_8822B << BIT_SHIFT_DRV2FW_INFO_8822B) +#define BIT_CLEAR_DRV2FW_INFO_8822B(x) ((x) & (~BITS_DRV2FW_INFO_8822B)) +#define BIT_GET_DRV2FW_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO_8822B) & BIT_MASK_DRV2FW_INFO_8822B) +#define BIT_SET_DRV2FW_INFO_8822B(x, v) \ + (BIT_CLEAR_DRV2FW_INFO_8822B(x) | BIT_DRV2FW_INFO_8822B(v)) /* 2 REG_PCIE_C2H_MSG_V1_8822B */ #define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B 0 #define BIT_MASK_HCI_PCIE_C2H_MSG_8822B 0xffffffffL -#define BIT_HCI_PCIE_C2H_MSG_8822B(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B) << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) -#define BIT_GET_HCI_PCIE_C2H_MSG_8822B(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B) - - +#define BIT_HCI_PCIE_C2H_MSG_8822B(x) \ + (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B) \ + << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) +#define BITS_HCI_PCIE_C2H_MSG_8822B \ + (BIT_MASK_HCI_PCIE_C2H_MSG_8822B << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) +#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8822B(x) \ + ((x) & (~BITS_HCI_PCIE_C2H_MSG_8822B)) +#define BIT_GET_HCI_PCIE_C2H_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) & \ + BIT_MASK_HCI_PCIE_C2H_MSG_8822B) +#define BIT_SET_HCI_PCIE_C2H_MSG_8822B(x, v) \ + (BIT_CLEAR_HCI_PCIE_C2H_MSG_8822B(x) | BIT_HCI_PCIE_C2H_MSG_8822B(v)) /* 2 REG_DBI_WDATA_V1_8822B */ #define BIT_SHIFT_DBI_WDATA_8822B 0 #define BIT_MASK_DBI_WDATA_8822B 0xffffffffL -#define BIT_DBI_WDATA_8822B(x) (((x) & BIT_MASK_DBI_WDATA_8822B) << BIT_SHIFT_DBI_WDATA_8822B) -#define BIT_GET_DBI_WDATA_8822B(x) (((x) >> BIT_SHIFT_DBI_WDATA_8822B) & BIT_MASK_DBI_WDATA_8822B) - - +#define BIT_DBI_WDATA_8822B(x) \ + (((x) & BIT_MASK_DBI_WDATA_8822B) << BIT_SHIFT_DBI_WDATA_8822B) +#define BITS_DBI_WDATA_8822B \ + (BIT_MASK_DBI_WDATA_8822B << BIT_SHIFT_DBI_WDATA_8822B) +#define BIT_CLEAR_DBI_WDATA_8822B(x) ((x) & (~BITS_DBI_WDATA_8822B)) +#define BIT_GET_DBI_WDATA_8822B(x) \ + (((x) >> BIT_SHIFT_DBI_WDATA_8822B) & BIT_MASK_DBI_WDATA_8822B) +#define BIT_SET_DBI_WDATA_8822B(x, v) \ + (BIT_CLEAR_DBI_WDATA_8822B(x) | BIT_DBI_WDATA_8822B(v)) /* 2 REG_DBI_RDATA_V1_8822B */ #define BIT_SHIFT_DBI_RDATA_8822B 0 #define BIT_MASK_DBI_RDATA_8822B 0xffffffffL -#define BIT_DBI_RDATA_8822B(x) (((x) & BIT_MASK_DBI_RDATA_8822B) << BIT_SHIFT_DBI_RDATA_8822B) -#define BIT_GET_DBI_RDATA_8822B(x) (((x) >> BIT_SHIFT_DBI_RDATA_8822B) & BIT_MASK_DBI_RDATA_8822B) - - +#define BIT_DBI_RDATA_8822B(x) \ + (((x) & BIT_MASK_DBI_RDATA_8822B) << BIT_SHIFT_DBI_RDATA_8822B) +#define BITS_DBI_RDATA_8822B \ + (BIT_MASK_DBI_RDATA_8822B << BIT_SHIFT_DBI_RDATA_8822B) +#define BIT_CLEAR_DBI_RDATA_8822B(x) ((x) & (~BITS_DBI_RDATA_8822B)) +#define BIT_GET_DBI_RDATA_8822B(x) \ + (((x) >> BIT_SHIFT_DBI_RDATA_8822B) & BIT_MASK_DBI_RDATA_8822B) +#define BIT_SET_DBI_RDATA_8822B(x, v) \ + (BIT_CLEAR_DBI_RDATA_8822B(x) | BIT_DBI_RDATA_8822B(v)) /* 2 REG_DBI_FLAG_V1_8822B */ #define BIT_EN_STUCK_DBG_8822B BIT(26) @@ -4956,48 +7382,84 @@ #define BIT_SHIFT_DBI_WREN_8822B 12 #define BIT_MASK_DBI_WREN_8822B 0xf -#define BIT_DBI_WREN_8822B(x) (((x) & BIT_MASK_DBI_WREN_8822B) << BIT_SHIFT_DBI_WREN_8822B) -#define BIT_GET_DBI_WREN_8822B(x) (((x) >> BIT_SHIFT_DBI_WREN_8822B) & BIT_MASK_DBI_WREN_8822B) - - +#define BIT_DBI_WREN_8822B(x) \ + (((x) & BIT_MASK_DBI_WREN_8822B) << BIT_SHIFT_DBI_WREN_8822B) +#define BITS_DBI_WREN_8822B \ + (BIT_MASK_DBI_WREN_8822B << BIT_SHIFT_DBI_WREN_8822B) +#define BIT_CLEAR_DBI_WREN_8822B(x) ((x) & (~BITS_DBI_WREN_8822B)) +#define BIT_GET_DBI_WREN_8822B(x) \ + (((x) >> BIT_SHIFT_DBI_WREN_8822B) & BIT_MASK_DBI_WREN_8822B) +#define BIT_SET_DBI_WREN_8822B(x, v) \ + (BIT_CLEAR_DBI_WREN_8822B(x) | BIT_DBI_WREN_8822B(v)) #define BIT_SHIFT_DBI_ADDR_8822B 0 #define BIT_MASK_DBI_ADDR_8822B 0xfff -#define BIT_DBI_ADDR_8822B(x) (((x) & BIT_MASK_DBI_ADDR_8822B) << BIT_SHIFT_DBI_ADDR_8822B) -#define BIT_GET_DBI_ADDR_8822B(x) (((x) >> BIT_SHIFT_DBI_ADDR_8822B) & BIT_MASK_DBI_ADDR_8822B) - - +#define BIT_DBI_ADDR_8822B(x) \ + (((x) & BIT_MASK_DBI_ADDR_8822B) << BIT_SHIFT_DBI_ADDR_8822B) +#define BITS_DBI_ADDR_8822B \ + (BIT_MASK_DBI_ADDR_8822B << BIT_SHIFT_DBI_ADDR_8822B) +#define BIT_CLEAR_DBI_ADDR_8822B(x) ((x) & (~BITS_DBI_ADDR_8822B)) +#define BIT_GET_DBI_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_DBI_ADDR_8822B) & BIT_MASK_DBI_ADDR_8822B) +#define BIT_SET_DBI_ADDR_8822B(x, v) \ + (BIT_CLEAR_DBI_ADDR_8822B(x) | BIT_DBI_ADDR_8822B(v)) /* 2 REG_MDIO_V1_8822B */ #define BIT_SHIFT_MDIO_RDATA_8822B 16 #define BIT_MASK_MDIO_RDATA_8822B 0xffff -#define BIT_MDIO_RDATA_8822B(x) (((x) & BIT_MASK_MDIO_RDATA_8822B) << BIT_SHIFT_MDIO_RDATA_8822B) -#define BIT_GET_MDIO_RDATA_8822B(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8822B) & BIT_MASK_MDIO_RDATA_8822B) - - +#define BIT_MDIO_RDATA_8822B(x) \ + (((x) & BIT_MASK_MDIO_RDATA_8822B) << BIT_SHIFT_MDIO_RDATA_8822B) +#define BITS_MDIO_RDATA_8822B \ + (BIT_MASK_MDIO_RDATA_8822B << BIT_SHIFT_MDIO_RDATA_8822B) +#define BIT_CLEAR_MDIO_RDATA_8822B(x) ((x) & (~BITS_MDIO_RDATA_8822B)) +#define BIT_GET_MDIO_RDATA_8822B(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA_8822B) & BIT_MASK_MDIO_RDATA_8822B) +#define BIT_SET_MDIO_RDATA_8822B(x, v) \ + (BIT_CLEAR_MDIO_RDATA_8822B(x) | BIT_MDIO_RDATA_8822B(v)) #define BIT_SHIFT_MDIO_WDATA_8822B 0 #define BIT_MASK_MDIO_WDATA_8822B 0xffff -#define BIT_MDIO_WDATA_8822B(x) (((x) & BIT_MASK_MDIO_WDATA_8822B) << BIT_SHIFT_MDIO_WDATA_8822B) -#define BIT_GET_MDIO_WDATA_8822B(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8822B) & BIT_MASK_MDIO_WDATA_8822B) - - +#define BIT_MDIO_WDATA_8822B(x) \ + (((x) & BIT_MASK_MDIO_WDATA_8822B) << BIT_SHIFT_MDIO_WDATA_8822B) +#define BITS_MDIO_WDATA_8822B \ + (BIT_MASK_MDIO_WDATA_8822B << BIT_SHIFT_MDIO_WDATA_8822B) +#define BIT_CLEAR_MDIO_WDATA_8822B(x) ((x) & (~BITS_MDIO_WDATA_8822B)) +#define BIT_GET_MDIO_WDATA_8822B(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA_8822B) & BIT_MASK_MDIO_WDATA_8822B) +#define BIT_SET_MDIO_WDATA_8822B(x, v) \ + (BIT_CLEAR_MDIO_WDATA_8822B(x) | BIT_MDIO_WDATA_8822B(v)) /* 2 REG_PCIE_MIX_CFG_8822B */ #define BIT_SHIFT_MDIO_PHY_ADDR_8822B 24 #define BIT_MASK_MDIO_PHY_ADDR_8822B 0x1f -#define BIT_MDIO_PHY_ADDR_8822B(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8822B) << BIT_SHIFT_MDIO_PHY_ADDR_8822B) -#define BIT_GET_MDIO_PHY_ADDR_8822B(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822B) & BIT_MASK_MDIO_PHY_ADDR_8822B) - - +#define BIT_MDIO_PHY_ADDR_8822B(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR_8822B) << BIT_SHIFT_MDIO_PHY_ADDR_8822B) +#define BITS_MDIO_PHY_ADDR_8822B \ + (BIT_MASK_MDIO_PHY_ADDR_8822B << BIT_SHIFT_MDIO_PHY_ADDR_8822B) +#define BIT_CLEAR_MDIO_PHY_ADDR_8822B(x) ((x) & (~BITS_MDIO_PHY_ADDR_8822B)) +#define BIT_GET_MDIO_PHY_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822B) & BIT_MASK_MDIO_PHY_ADDR_8822B) +#define BIT_SET_MDIO_PHY_ADDR_8822B(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR_8822B(x) | BIT_MDIO_PHY_ADDR_8822B(v)) #define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B 10 #define BIT_MASK_WATCH_DOG_RECORD_V1_8822B 0x3fff -#define BIT_WATCH_DOG_RECORD_V1_8822B(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) -#define BIT_GET_WATCH_DOG_RECORD_V1_8822B(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B) - +#define BIT_WATCH_DOG_RECORD_V1_8822B(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B) \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) +#define BITS_WATCH_DOG_RECORD_V1_8822B \ + (BIT_MASK_WATCH_DOG_RECORD_V1_8822B \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8822B(x) \ + ((x) & (~BITS_WATCH_DOG_RECORD_V1_8822B)) +#define BIT_GET_WATCH_DOG_RECORD_V1_8822B(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) & \ + BIT_MASK_WATCH_DOG_RECORD_V1_8822B) +#define BIT_SET_WATCH_DOG_RECORD_V1_8822B(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1_8822B(x) | \ + BIT_WATCH_DOG_RECORD_V1_8822B(v)) #define BIT_R_IO_TIMEOUT_FLAG_V1_8822B BIT(9) #define BIT_EN_WATCH_DOG_8822B BIT(8) @@ -5007,34 +7469,66 @@ #define BIT_SHIFT_MDIO_REG_ADDR_V1_8822B 0 #define BIT_MASK_MDIO_REG_ADDR_V1_8822B 0x1f -#define BIT_MDIO_REG_ADDR_V1_8822B(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822B) << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) -#define BIT_GET_MDIO_REG_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) & BIT_MASK_MDIO_REG_ADDR_V1_8822B) - - +#define BIT_MDIO_REG_ADDR_V1_8822B(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822B) \ + << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) +#define BITS_MDIO_REG_ADDR_V1_8822B \ + (BIT_MASK_MDIO_REG_ADDR_V1_8822B << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) +#define BIT_CLEAR_MDIO_REG_ADDR_V1_8822B(x) \ + ((x) & (~BITS_MDIO_REG_ADDR_V1_8822B)) +#define BIT_GET_MDIO_REG_ADDR_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) & \ + BIT_MASK_MDIO_REG_ADDR_V1_8822B) +#define BIT_SET_MDIO_REG_ADDR_V1_8822B(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_V1_8822B(x) | BIT_MDIO_REG_ADDR_V1_8822B(v)) /* 2 REG_HCI_MIX_CFG_8822B */ #define BIT_HOST_GEN2_SUPPORT_8822B BIT(20) #define BIT_SHIFT_TXDMA_ERR_FLAG_8822B 16 #define BIT_MASK_TXDMA_ERR_FLAG_8822B 0xf -#define BIT_TXDMA_ERR_FLAG_8822B(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8822B) << BIT_SHIFT_TXDMA_ERR_FLAG_8822B) -#define BIT_GET_TXDMA_ERR_FLAG_8822B(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8822B) & BIT_MASK_TXDMA_ERR_FLAG_8822B) - - +#define BIT_TXDMA_ERR_FLAG_8822B(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_8822B) \ + << BIT_SHIFT_TXDMA_ERR_FLAG_8822B) +#define BITS_TXDMA_ERR_FLAG_8822B \ + (BIT_MASK_TXDMA_ERR_FLAG_8822B << BIT_SHIFT_TXDMA_ERR_FLAG_8822B) +#define BIT_CLEAR_TXDMA_ERR_FLAG_8822B(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8822B)) +#define BIT_GET_TXDMA_ERR_FLAG_8822B(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8822B) & \ + BIT_MASK_TXDMA_ERR_FLAG_8822B) +#define BIT_SET_TXDMA_ERR_FLAG_8822B(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_8822B(x) | BIT_TXDMA_ERR_FLAG_8822B(v)) #define BIT_SHIFT_EARLY_MODE_SEL_8822B 12 #define BIT_MASK_EARLY_MODE_SEL_8822B 0xf -#define BIT_EARLY_MODE_SEL_8822B(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8822B) << BIT_SHIFT_EARLY_MODE_SEL_8822B) -#define BIT_GET_EARLY_MODE_SEL_8822B(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8822B) & BIT_MASK_EARLY_MODE_SEL_8822B) - +#define BIT_EARLY_MODE_SEL_8822B(x) \ + (((x) & BIT_MASK_EARLY_MODE_SEL_8822B) \ + << BIT_SHIFT_EARLY_MODE_SEL_8822B) +#define BITS_EARLY_MODE_SEL_8822B \ + (BIT_MASK_EARLY_MODE_SEL_8822B << BIT_SHIFT_EARLY_MODE_SEL_8822B) +#define BIT_CLEAR_EARLY_MODE_SEL_8822B(x) ((x) & (~BITS_EARLY_MODE_SEL_8822B)) +#define BIT_GET_EARLY_MODE_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8822B) & \ + BIT_MASK_EARLY_MODE_SEL_8822B) +#define BIT_SET_EARLY_MODE_SEL_8822B(x, v) \ + (BIT_CLEAR_EARLY_MODE_SEL_8822B(x) | BIT_EARLY_MODE_SEL_8822B(v)) #define BIT_EPHY_RX50_EN_8822B BIT(11) #define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B 8 #define BIT_MASK_MSI_TIMEOUT_ID_V1_8822B 0x7 -#define BIT_MSI_TIMEOUT_ID_V1_8822B(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) -#define BIT_GET_MSI_TIMEOUT_ID_V1_8822B(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) - +#define BIT_MSI_TIMEOUT_ID_V1_8822B(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) \ + << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) +#define BITS_MSI_TIMEOUT_ID_V1_8822B \ + (BIT_MASK_MSI_TIMEOUT_ID_V1_8822B << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822B(x) \ + ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8822B)) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) & \ + BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) +#define BIT_SET_MSI_TIMEOUT_ID_V1_8822B(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822B(x) | BIT_MSI_TIMEOUT_ID_V1_8822B(v)) #define BIT_RADDR_RD_8822B BIT(7) #define BIT_EN_MUL_TAG_8822B BIT(6) @@ -5049,41 +7543,77 @@ #define BIT_SHIFT_STC_INT_FLAG_8822B 16 #define BIT_MASK_STC_INT_FLAG_8822B 0xff -#define BIT_STC_INT_FLAG_8822B(x) (((x) & BIT_MASK_STC_INT_FLAG_8822B) << BIT_SHIFT_STC_INT_FLAG_8822B) -#define BIT_GET_STC_INT_FLAG_8822B(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8822B) & BIT_MASK_STC_INT_FLAG_8822B) - - +#define BIT_STC_INT_FLAG_8822B(x) \ + (((x) & BIT_MASK_STC_INT_FLAG_8822B) << BIT_SHIFT_STC_INT_FLAG_8822B) +#define BITS_STC_INT_FLAG_8822B \ + (BIT_MASK_STC_INT_FLAG_8822B << BIT_SHIFT_STC_INT_FLAG_8822B) +#define BIT_CLEAR_STC_INT_FLAG_8822B(x) ((x) & (~BITS_STC_INT_FLAG_8822B)) +#define BIT_GET_STC_INT_FLAG_8822B(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG_8822B) & BIT_MASK_STC_INT_FLAG_8822B) +#define BIT_SET_STC_INT_FLAG_8822B(x, v) \ + (BIT_CLEAR_STC_INT_FLAG_8822B(x) | BIT_STC_INT_FLAG_8822B(v)) #define BIT_SHIFT_STC_INT_IDX_8822B 8 #define BIT_MASK_STC_INT_IDX_8822B 0x7 -#define BIT_STC_INT_IDX_8822B(x) (((x) & BIT_MASK_STC_INT_IDX_8822B) << BIT_SHIFT_STC_INT_IDX_8822B) -#define BIT_GET_STC_INT_IDX_8822B(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8822B) & BIT_MASK_STC_INT_IDX_8822B) - - +#define BIT_STC_INT_IDX_8822B(x) \ + (((x) & BIT_MASK_STC_INT_IDX_8822B) << BIT_SHIFT_STC_INT_IDX_8822B) +#define BITS_STC_INT_IDX_8822B \ + (BIT_MASK_STC_INT_IDX_8822B << BIT_SHIFT_STC_INT_IDX_8822B) +#define BIT_CLEAR_STC_INT_IDX_8822B(x) ((x) & (~BITS_STC_INT_IDX_8822B)) +#define BIT_GET_STC_INT_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX_8822B) & BIT_MASK_STC_INT_IDX_8822B) +#define BIT_SET_STC_INT_IDX_8822B(x, v) \ + (BIT_CLEAR_STC_INT_IDX_8822B(x) | BIT_STC_INT_IDX_8822B(v)) #define BIT_SHIFT_STC_INT_REALTIME_CS_8822B 0 #define BIT_MASK_STC_INT_REALTIME_CS_8822B 0x3f -#define BIT_STC_INT_REALTIME_CS_8822B(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8822B) << BIT_SHIFT_STC_INT_REALTIME_CS_8822B) -#define BIT_GET_STC_INT_REALTIME_CS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822B) & BIT_MASK_STC_INT_REALTIME_CS_8822B) - - +#define BIT_STC_INT_REALTIME_CS_8822B(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS_8822B) \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8822B) +#define BITS_STC_INT_REALTIME_CS_8822B \ + (BIT_MASK_STC_INT_REALTIME_CS_8822B \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8822B) +#define BIT_CLEAR_STC_INT_REALTIME_CS_8822B(x) \ + ((x) & (~BITS_STC_INT_REALTIME_CS_8822B)) +#define BIT_GET_STC_INT_REALTIME_CS_8822B(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822B) & \ + BIT_MASK_STC_INT_REALTIME_CS_8822B) +#define BIT_SET_STC_INT_REALTIME_CS_8822B(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS_8822B(x) | \ + BIT_STC_INT_REALTIME_CS_8822B(v)) /* 2 REG_ST_INT_CFG_8822B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ #define BIT_STC_INT_GRP_EN_8822B BIT(31) #define BIT_SHIFT_STC_INT_EXPECT_LS_8822B 8 #define BIT_MASK_STC_INT_EXPECT_LS_8822B 0x3f -#define BIT_STC_INT_EXPECT_LS_8822B(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8822B) << BIT_SHIFT_STC_INT_EXPECT_LS_8822B) -#define BIT_GET_STC_INT_EXPECT_LS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822B) & BIT_MASK_STC_INT_EXPECT_LS_8822B) - - +#define BIT_STC_INT_EXPECT_LS_8822B(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS_8822B) \ + << BIT_SHIFT_STC_INT_EXPECT_LS_8822B) +#define BITS_STC_INT_EXPECT_LS_8822B \ + (BIT_MASK_STC_INT_EXPECT_LS_8822B << BIT_SHIFT_STC_INT_EXPECT_LS_8822B) +#define BIT_CLEAR_STC_INT_EXPECT_LS_8822B(x) \ + ((x) & (~BITS_STC_INT_EXPECT_LS_8822B)) +#define BIT_GET_STC_INT_EXPECT_LS_8822B(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822B) & \ + BIT_MASK_STC_INT_EXPECT_LS_8822B) +#define BIT_SET_STC_INT_EXPECT_LS_8822B(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS_8822B(x) | BIT_STC_INT_EXPECT_LS_8822B(v)) #define BIT_SHIFT_STC_INT_EXPECT_CS_8822B 0 #define BIT_MASK_STC_INT_EXPECT_CS_8822B 0x3f -#define BIT_STC_INT_EXPECT_CS_8822B(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8822B) << BIT_SHIFT_STC_INT_EXPECT_CS_8822B) -#define BIT_GET_STC_INT_EXPECT_CS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822B) & BIT_MASK_STC_INT_EXPECT_CS_8822B) - - +#define BIT_STC_INT_EXPECT_CS_8822B(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS_8822B) \ + << BIT_SHIFT_STC_INT_EXPECT_CS_8822B) +#define BITS_STC_INT_EXPECT_CS_8822B \ + (BIT_MASK_STC_INT_EXPECT_CS_8822B << BIT_SHIFT_STC_INT_EXPECT_CS_8822B) +#define BIT_CLEAR_STC_INT_EXPECT_CS_8822B(x) \ + ((x) & (~BITS_STC_INT_EXPECT_CS_8822B)) +#define BIT_GET_STC_INT_EXPECT_CS_8822B(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822B) & \ + BIT_MASK_STC_INT_EXPECT_CS_8822B) +#define BIT_SET_STC_INT_EXPECT_CS_8822B(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS_8822B(x) | BIT_STC_INT_EXPECT_CS_8822B(v)) /* 2 REG_CMU_DLY_CTRL_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */ #define BIT_CMU_DLY_EN_8822B BIT(31) @@ -5091,104 +7621,206 @@ #define BIT_SHIFT_CMU_DLY_PRE_DIV_8822B 0 #define BIT_MASK_CMU_DLY_PRE_DIV_8822B 0xff -#define BIT_CMU_DLY_PRE_DIV_8822B(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8822B) << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) -#define BIT_GET_CMU_DLY_PRE_DIV_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) & BIT_MASK_CMU_DLY_PRE_DIV_8822B) - - +#define BIT_CMU_DLY_PRE_DIV_8822B(x) \ + (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8822B) \ + << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) +#define BITS_CMU_DLY_PRE_DIV_8822B \ + (BIT_MASK_CMU_DLY_PRE_DIV_8822B << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) +#define BIT_CLEAR_CMU_DLY_PRE_DIV_8822B(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8822B)) +#define BIT_GET_CMU_DLY_PRE_DIV_8822B(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) & \ + BIT_MASK_CMU_DLY_PRE_DIV_8822B) +#define BIT_SET_CMU_DLY_PRE_DIV_8822B(x, v) \ + (BIT_CLEAR_CMU_DLY_PRE_DIV_8822B(x) | BIT_CMU_DLY_PRE_DIV_8822B(v)) /* 2 REG_CMU_DLY_CFG_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ #define BIT_SHIFT_CMU_DLY_LTR_A2I_8822B 24 #define BIT_MASK_CMU_DLY_LTR_A2I_8822B 0xff -#define BIT_CMU_DLY_LTR_A2I_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8822B) << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) -#define BIT_GET_CMU_DLY_LTR_A2I_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) & BIT_MASK_CMU_DLY_LTR_A2I_8822B) - - +#define BIT_CMU_DLY_LTR_A2I_8822B(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8822B) \ + << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) +#define BITS_CMU_DLY_LTR_A2I_8822B \ + (BIT_MASK_CMU_DLY_LTR_A2I_8822B << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) +#define BIT_CLEAR_CMU_DLY_LTR_A2I_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8822B)) +#define BIT_GET_CMU_DLY_LTR_A2I_8822B(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) & \ + BIT_MASK_CMU_DLY_LTR_A2I_8822B) +#define BIT_SET_CMU_DLY_LTR_A2I_8822B(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_A2I_8822B(x) | BIT_CMU_DLY_LTR_A2I_8822B(v)) #define BIT_SHIFT_CMU_DLY_LTR_I2A_8822B 16 #define BIT_MASK_CMU_DLY_LTR_I2A_8822B 0xff -#define BIT_CMU_DLY_LTR_I2A_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8822B) << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) -#define BIT_GET_CMU_DLY_LTR_I2A_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) & BIT_MASK_CMU_DLY_LTR_I2A_8822B) - - +#define BIT_CMU_DLY_LTR_I2A_8822B(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8822B) \ + << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) +#define BITS_CMU_DLY_LTR_I2A_8822B \ + (BIT_MASK_CMU_DLY_LTR_I2A_8822B << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) +#define BIT_CLEAR_CMU_DLY_LTR_I2A_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8822B)) +#define BIT_GET_CMU_DLY_LTR_I2A_8822B(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) & \ + BIT_MASK_CMU_DLY_LTR_I2A_8822B) +#define BIT_SET_CMU_DLY_LTR_I2A_8822B(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_I2A_8822B(x) | BIT_CMU_DLY_LTR_I2A_8822B(v)) #define BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B 8 #define BIT_MASK_CMU_DLY_LTR_IDLE_8822B 0xff -#define BIT_CMU_DLY_LTR_IDLE_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) -#define BIT_GET_CMU_DLY_LTR_IDLE_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B) - - +#define BIT_CMU_DLY_LTR_IDLE_8822B(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B) \ + << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) +#define BITS_CMU_DLY_LTR_IDLE_8822B \ + (BIT_MASK_CMU_DLY_LTR_IDLE_8822B << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) +#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8822B(x) \ + ((x) & (~BITS_CMU_DLY_LTR_IDLE_8822B)) +#define BIT_GET_CMU_DLY_LTR_IDLE_8822B(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) & \ + BIT_MASK_CMU_DLY_LTR_IDLE_8822B) +#define BIT_SET_CMU_DLY_LTR_IDLE_8822B(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_IDLE_8822B(x) | BIT_CMU_DLY_LTR_IDLE_8822B(v)) #define BIT_SHIFT_CMU_DLY_LTR_ACT_8822B 0 #define BIT_MASK_CMU_DLY_LTR_ACT_8822B 0xff -#define BIT_CMU_DLY_LTR_ACT_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8822B) << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) -#define BIT_GET_CMU_DLY_LTR_ACT_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) & BIT_MASK_CMU_DLY_LTR_ACT_8822B) - - +#define BIT_CMU_DLY_LTR_ACT_8822B(x) \ + (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8822B) \ + << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) +#define BITS_CMU_DLY_LTR_ACT_8822B \ + (BIT_MASK_CMU_DLY_LTR_ACT_8822B << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) +#define BIT_CLEAR_CMU_DLY_LTR_ACT_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8822B)) +#define BIT_GET_CMU_DLY_LTR_ACT_8822B(x) \ + (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) & \ + BIT_MASK_CMU_DLY_LTR_ACT_8822B) +#define BIT_SET_CMU_DLY_LTR_ACT_8822B(x, v) \ + (BIT_CLEAR_CMU_DLY_LTR_ACT_8822B(x) | BIT_CMU_DLY_LTR_ACT_8822B(v)) /* 2 REG_H2CQ_TXBD_DESA_8822B */ #define BIT_SHIFT_H2CQ_TXBD_DESA_8822B 0 #define BIT_MASK_H2CQ_TXBD_DESA_8822B 0xffffffffffffffffL -#define BIT_H2CQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8822B) << BIT_SHIFT_H2CQ_TXBD_DESA_8822B) -#define BIT_GET_H2CQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822B) & BIT_MASK_H2CQ_TXBD_DESA_8822B) - - +#define BIT_H2CQ_TXBD_DESA_8822B(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_8822B) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_8822B) +#define BITS_H2CQ_TXBD_DESA_8822B \ + (BIT_MASK_H2CQ_TXBD_DESA_8822B << BIT_SHIFT_H2CQ_TXBD_DESA_8822B) +#define BIT_CLEAR_H2CQ_TXBD_DESA_8822B(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8822B)) +#define BIT_GET_H2CQ_TXBD_DESA_8822B(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822B) & \ + BIT_MASK_H2CQ_TXBD_DESA_8822B) +#define BIT_SET_H2CQ_TXBD_DESA_8822B(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_8822B(x) | BIT_H2CQ_TXBD_DESA_8822B(v)) /* 2 REG_H2CQ_TXBD_NUM_8822B */ #define BIT_PCIE_H2CQ_FLAG_8822B BIT(14) #define BIT_SHIFT_H2CQ_DESC_MODE_8822B 12 #define BIT_MASK_H2CQ_DESC_MODE_8822B 0x3 -#define BIT_H2CQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8822B) << BIT_SHIFT_H2CQ_DESC_MODE_8822B) -#define BIT_GET_H2CQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822B) & BIT_MASK_H2CQ_DESC_MODE_8822B) - - +#define BIT_H2CQ_DESC_MODE_8822B(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE_8822B) \ + << BIT_SHIFT_H2CQ_DESC_MODE_8822B) +#define BITS_H2CQ_DESC_MODE_8822B \ + (BIT_MASK_H2CQ_DESC_MODE_8822B << BIT_SHIFT_H2CQ_DESC_MODE_8822B) +#define BIT_CLEAR_H2CQ_DESC_MODE_8822B(x) ((x) & (~BITS_H2CQ_DESC_MODE_8822B)) +#define BIT_GET_H2CQ_DESC_MODE_8822B(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822B) & \ + BIT_MASK_H2CQ_DESC_MODE_8822B) +#define BIT_SET_H2CQ_DESC_MODE_8822B(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE_8822B(x) | BIT_H2CQ_DESC_MODE_8822B(v)) #define BIT_SHIFT_H2CQ_DESC_NUM_8822B 0 #define BIT_MASK_H2CQ_DESC_NUM_8822B 0xfff -#define BIT_H2CQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8822B) << BIT_SHIFT_H2CQ_DESC_NUM_8822B) -#define BIT_GET_H2CQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822B) & BIT_MASK_H2CQ_DESC_NUM_8822B) - - +#define BIT_H2CQ_DESC_NUM_8822B(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM_8822B) << BIT_SHIFT_H2CQ_DESC_NUM_8822B) +#define BITS_H2CQ_DESC_NUM_8822B \ + (BIT_MASK_H2CQ_DESC_NUM_8822B << BIT_SHIFT_H2CQ_DESC_NUM_8822B) +#define BIT_CLEAR_H2CQ_DESC_NUM_8822B(x) ((x) & (~BITS_H2CQ_DESC_NUM_8822B)) +#define BIT_GET_H2CQ_DESC_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822B) & BIT_MASK_H2CQ_DESC_NUM_8822B) +#define BIT_SET_H2CQ_DESC_NUM_8822B(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM_8822B(x) | BIT_H2CQ_DESC_NUM_8822B(v)) /* 2 REG_H2CQ_TXBD_IDX_8822B */ #define BIT_SHIFT_H2CQ_HW_IDX_8822B 16 #define BIT_MASK_H2CQ_HW_IDX_8822B 0xfff -#define BIT_H2CQ_HW_IDX_8822B(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8822B) << BIT_SHIFT_H2CQ_HW_IDX_8822B) -#define BIT_GET_H2CQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822B) & BIT_MASK_H2CQ_HW_IDX_8822B) - - +#define BIT_H2CQ_HW_IDX_8822B(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX_8822B) << BIT_SHIFT_H2CQ_HW_IDX_8822B) +#define BITS_H2CQ_HW_IDX_8822B \ + (BIT_MASK_H2CQ_HW_IDX_8822B << BIT_SHIFT_H2CQ_HW_IDX_8822B) +#define BIT_CLEAR_H2CQ_HW_IDX_8822B(x) ((x) & (~BITS_H2CQ_HW_IDX_8822B)) +#define BIT_GET_H2CQ_HW_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822B) & BIT_MASK_H2CQ_HW_IDX_8822B) +#define BIT_SET_H2CQ_HW_IDX_8822B(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX_8822B(x) | BIT_H2CQ_HW_IDX_8822B(v)) #define BIT_SHIFT_H2CQ_HOST_IDX_8822B 0 #define BIT_MASK_H2CQ_HOST_IDX_8822B 0xfff -#define BIT_H2CQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8822B) << BIT_SHIFT_H2CQ_HOST_IDX_8822B) -#define BIT_GET_H2CQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822B) & BIT_MASK_H2CQ_HOST_IDX_8822B) - - +#define BIT_H2CQ_HOST_IDX_8822B(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX_8822B) << BIT_SHIFT_H2CQ_HOST_IDX_8822B) +#define BITS_H2CQ_HOST_IDX_8822B \ + (BIT_MASK_H2CQ_HOST_IDX_8822B << BIT_SHIFT_H2CQ_HOST_IDX_8822B) +#define BIT_CLEAR_H2CQ_HOST_IDX_8822B(x) ((x) & (~BITS_H2CQ_HOST_IDX_8822B)) +#define BIT_GET_H2CQ_HOST_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822B) & BIT_MASK_H2CQ_HOST_IDX_8822B) +#define BIT_SET_H2CQ_HOST_IDX_8822B(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX_8822B(x) | BIT_H2CQ_HOST_IDX_8822B(v)) /* 2 REG_H2CQ_CSR_8822B[31:0] (H2CQ CONTROL AND STATUS) */ #define BIT_H2CQ_FULL_8822B BIT(31) #define BIT_CLR_H2CQ_HOST_IDX_8822B BIT(16) #define BIT_CLR_H2CQ_HW_IDX_8822B BIT(8) +#define BIT_STOP_H2CQ_8822B BIT(0) /* 2 REG_CHANGE_PCIE_SPEED_8822B */ #define BIT_CHANGE_PCIE_SPEED_8822B BIT(18) #define BIT_SHIFT_GEN1_GEN2_8822B 16 #define BIT_MASK_GEN1_GEN2_8822B 0x3 -#define BIT_GEN1_GEN2_8822B(x) (((x) & BIT_MASK_GEN1_GEN2_8822B) << BIT_SHIFT_GEN1_GEN2_8822B) -#define BIT_GET_GEN1_GEN2_8822B(x) (((x) >> BIT_SHIFT_GEN1_GEN2_8822B) & BIT_MASK_GEN1_GEN2_8822B) - - +#define BIT_GEN1_GEN2_8822B(x) \ + (((x) & BIT_MASK_GEN1_GEN2_8822B) << BIT_SHIFT_GEN1_GEN2_8822B) +#define BITS_GEN1_GEN2_8822B \ + (BIT_MASK_GEN1_GEN2_8822B << BIT_SHIFT_GEN1_GEN2_8822B) +#define BIT_CLEAR_GEN1_GEN2_8822B(x) ((x) & (~BITS_GEN1_GEN2_8822B)) +#define BIT_GET_GEN1_GEN2_8822B(x) \ + (((x) >> BIT_SHIFT_GEN1_GEN2_8822B) & BIT_MASK_GEN1_GEN2_8822B) +#define BIT_SET_GEN1_GEN2_8822B(x, v) \ + (BIT_CLEAR_GEN1_GEN2_8822B(x) | BIT_GEN1_GEN2_8822B(v)) + +#define BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B 8 +#define BIT_MASK_RXDMA_ERROR_COUNTER_8822B 0xff +#define BIT_RXDMA_ERROR_COUNTER_8822B(x) \ + (((x) & BIT_MASK_RXDMA_ERROR_COUNTER_8822B) \ + << BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B) +#define BITS_RXDMA_ERROR_COUNTER_8822B \ + (BIT_MASK_RXDMA_ERROR_COUNTER_8822B \ + << BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B) +#define BIT_CLEAR_RXDMA_ERROR_COUNTER_8822B(x) \ + ((x) & (~BITS_RXDMA_ERROR_COUNTER_8822B)) +#define BIT_GET_RXDMA_ERROR_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B) & \ + BIT_MASK_RXDMA_ERROR_COUNTER_8822B) +#define BIT_SET_RXDMA_ERROR_COUNTER_8822B(x, v) \ + (BIT_CLEAR_RXDMA_ERROR_COUNTER_8822B(x) | \ + BIT_RXDMA_ERROR_COUNTER_8822B(v)) + +#define BIT_TXDMA_ERROR_HANDLE_STATUS_8822B BIT(7) +#define BIT_TXDMA_ERROR_PULSE_8822B BIT(6) +#define BIT_TXDMA_STUCK_ERROR_HANDLE_ENABLE_8822B BIT(5) +#define BIT_TXDMA_RETURN_ERROR_ENABLE_8822B BIT(4) +#define BIT_RXDMA_ERROR_HANDLE_STATUS_8822B BIT(3) #define BIT_SHIFT_AUTO_HANG_RELEASE_8822B 0 #define BIT_MASK_AUTO_HANG_RELEASE_8822B 0x7 -#define BIT_AUTO_HANG_RELEASE_8822B(x) (((x) & BIT_MASK_AUTO_HANG_RELEASE_8822B) << BIT_SHIFT_AUTO_HANG_RELEASE_8822B) -#define BIT_GET_AUTO_HANG_RELEASE_8822B(x) (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE_8822B) & BIT_MASK_AUTO_HANG_RELEASE_8822B) - - +#define BIT_AUTO_HANG_RELEASE_8822B(x) \ + (((x) & BIT_MASK_AUTO_HANG_RELEASE_8822B) \ + << BIT_SHIFT_AUTO_HANG_RELEASE_8822B) +#define BITS_AUTO_HANG_RELEASE_8822B \ + (BIT_MASK_AUTO_HANG_RELEASE_8822B << BIT_SHIFT_AUTO_HANG_RELEASE_8822B) +#define BIT_CLEAR_AUTO_HANG_RELEASE_8822B(x) \ + ((x) & (~BITS_AUTO_HANG_RELEASE_8822B)) +#define BIT_GET_AUTO_HANG_RELEASE_8822B(x) \ + (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE_8822B) & \ + BIT_MASK_AUTO_HANG_RELEASE_8822B) +#define BIT_SET_AUTO_HANG_RELEASE_8822B(x, v) \ + (BIT_CLEAR_AUTO_HANG_RELEASE_8822B(x) | BIT_AUTO_HANG_RELEASE_8822B(v)) /* 2 REG_OLD_DEHANG_8822B */ #define BIT_OLD_DEHANG_8822B BIT(1) @@ -5197,196 +7829,375 @@ #define BIT_SHIFT_QUEUEMACID_Q0_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q0_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q0_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) -#define BIT_GET_QUEUEMACID_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) & BIT_MASK_QUEUEMACID_Q0_V1_8822B) - - +#define BIT_QUEUEMACID_Q0_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) +#define BITS_QUEUEMACID_Q0_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q0_V1_8822B << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q0_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q0_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q0_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q0_V1_8822B) +#define BIT_SET_QUEUEMACID_Q0_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q0_V1_8822B(x) | BIT_QUEUEMACID_Q0_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q0_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q0_V1_8822B 0x3 -#define BIT_QUEUEAC_Q0_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8822B) << BIT_SHIFT_QUEUEAC_Q0_V1_8822B) -#define BIT_GET_QUEUEAC_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822B) & BIT_MASK_QUEUEAC_Q0_V1_8822B) - +#define BIT_QUEUEAC_Q0_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q0_V1_8822B) << BIT_SHIFT_QUEUEAC_Q0_V1_8822B) +#define BITS_QUEUEAC_Q0_V1_8822B \ + (BIT_MASK_QUEUEAC_Q0_V1_8822B << BIT_SHIFT_QUEUEAC_Q0_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q0_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8822B)) +#define BIT_GET_QUEUEAC_Q0_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822B) & BIT_MASK_QUEUEAC_Q0_V1_8822B) +#define BIT_SET_QUEUEAC_Q0_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q0_V1_8822B(x) | BIT_QUEUEAC_Q0_V1_8822B(v)) #define BIT_TIDEMPTY_Q0_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q0_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q0_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q0_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) -#define BIT_GET_TAIL_PKT_Q0_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) & BIT_MASK_TAIL_PKT_Q0_V2_8822B) - - +#define BIT_TAIL_PKT_Q0_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) +#define BITS_TAIL_PKT_Q0_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q0_V2_8822B << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q0_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q0_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q0_V2_8822B) +#define BIT_SET_TAIL_PKT_Q0_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V2_8822B(x) | BIT_TAIL_PKT_Q0_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q0_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q0_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q0_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) -#define BIT_GET_HEAD_PKT_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) & BIT_MASK_HEAD_PKT_Q0_V1_8822B) - - +#define BIT_HEAD_PKT_Q0_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) +#define BITS_HEAD_PKT_Q0_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q0_V1_8822B << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q0_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q0_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q0_V1_8822B) +#define BIT_SET_HEAD_PKT_Q0_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0_V1_8822B(x) | BIT_HEAD_PKT_Q0_V1_8822B(v)) /* 2 REG_Q1_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q1_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q1_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q1_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) -#define BIT_GET_QUEUEMACID_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) & BIT_MASK_QUEUEMACID_Q1_V1_8822B) - - +#define BIT_QUEUEMACID_Q1_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) +#define BITS_QUEUEMACID_Q1_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q1_V1_8822B << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q1_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q1_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q1_V1_8822B) +#define BIT_SET_QUEUEMACID_Q1_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q1_V1_8822B(x) | BIT_QUEUEMACID_Q1_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q1_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q1_V1_8822B 0x3 -#define BIT_QUEUEAC_Q1_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8822B) << BIT_SHIFT_QUEUEAC_Q1_V1_8822B) -#define BIT_GET_QUEUEAC_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822B) & BIT_MASK_QUEUEAC_Q1_V1_8822B) - +#define BIT_QUEUEAC_Q1_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q1_V1_8822B) << BIT_SHIFT_QUEUEAC_Q1_V1_8822B) +#define BITS_QUEUEAC_Q1_V1_8822B \ + (BIT_MASK_QUEUEAC_Q1_V1_8822B << BIT_SHIFT_QUEUEAC_Q1_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q1_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8822B)) +#define BIT_GET_QUEUEAC_Q1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822B) & BIT_MASK_QUEUEAC_Q1_V1_8822B) +#define BIT_SET_QUEUEAC_Q1_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q1_V1_8822B(x) | BIT_QUEUEAC_Q1_V1_8822B(v)) #define BIT_TIDEMPTY_Q1_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q1_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q1_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q1_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) -#define BIT_GET_TAIL_PKT_Q1_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) & BIT_MASK_TAIL_PKT_Q1_V2_8822B) - - +#define BIT_TAIL_PKT_Q1_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) +#define BITS_TAIL_PKT_Q1_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q1_V2_8822B << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q1_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q1_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q1_V2_8822B) +#define BIT_SET_TAIL_PKT_Q1_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V2_8822B(x) | BIT_TAIL_PKT_Q1_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q1_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q1_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q1_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) -#define BIT_GET_HEAD_PKT_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) & BIT_MASK_HEAD_PKT_Q1_V1_8822B) - - +#define BIT_HEAD_PKT_Q1_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) +#define BITS_HEAD_PKT_Q1_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q1_V1_8822B << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q1_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q1_V1_8822B) +#define BIT_SET_HEAD_PKT_Q1_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1_V1_8822B(x) | BIT_HEAD_PKT_Q1_V1_8822B(v)) /* 2 REG_Q2_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q2_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q2_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q2_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) -#define BIT_GET_QUEUEMACID_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) & BIT_MASK_QUEUEMACID_Q2_V1_8822B) - - +#define BIT_QUEUEMACID_Q2_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) +#define BITS_QUEUEMACID_Q2_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q2_V1_8822B << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q2_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q2_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q2_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q2_V1_8822B) +#define BIT_SET_QUEUEMACID_Q2_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q2_V1_8822B(x) | BIT_QUEUEMACID_Q2_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q2_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q2_V1_8822B 0x3 -#define BIT_QUEUEAC_Q2_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8822B) << BIT_SHIFT_QUEUEAC_Q2_V1_8822B) -#define BIT_GET_QUEUEAC_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822B) & BIT_MASK_QUEUEAC_Q2_V1_8822B) - +#define BIT_QUEUEAC_Q2_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q2_V1_8822B) << BIT_SHIFT_QUEUEAC_Q2_V1_8822B) +#define BITS_QUEUEAC_Q2_V1_8822B \ + (BIT_MASK_QUEUEAC_Q2_V1_8822B << BIT_SHIFT_QUEUEAC_Q2_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q2_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8822B)) +#define BIT_GET_QUEUEAC_Q2_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822B) & BIT_MASK_QUEUEAC_Q2_V1_8822B) +#define BIT_SET_QUEUEAC_Q2_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q2_V1_8822B(x) | BIT_QUEUEAC_Q2_V1_8822B(v)) #define BIT_TIDEMPTY_Q2_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q2_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q2_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q2_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) -#define BIT_GET_TAIL_PKT_Q2_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) & BIT_MASK_TAIL_PKT_Q2_V2_8822B) - - +#define BIT_TAIL_PKT_Q2_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) +#define BITS_TAIL_PKT_Q2_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q2_V2_8822B << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q2_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q2_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q2_V2_8822B) +#define BIT_SET_TAIL_PKT_Q2_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V2_8822B(x) | BIT_TAIL_PKT_Q2_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q2_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q2_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q2_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) -#define BIT_GET_HEAD_PKT_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) & BIT_MASK_HEAD_PKT_Q2_V1_8822B) - - +#define BIT_HEAD_PKT_Q2_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) +#define BITS_HEAD_PKT_Q2_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q2_V1_8822B << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q2_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q2_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q2_V1_8822B) +#define BIT_SET_HEAD_PKT_Q2_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2_V1_8822B(x) | BIT_HEAD_PKT_Q2_V1_8822B(v)) /* 2 REG_Q3_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q3_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q3_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q3_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) -#define BIT_GET_QUEUEMACID_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) & BIT_MASK_QUEUEMACID_Q3_V1_8822B) - - +#define BIT_QUEUEMACID_Q3_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) +#define BITS_QUEUEMACID_Q3_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q3_V1_8822B << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q3_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q3_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q3_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q3_V1_8822B) +#define BIT_SET_QUEUEMACID_Q3_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q3_V1_8822B(x) | BIT_QUEUEMACID_Q3_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q3_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q3_V1_8822B 0x3 -#define BIT_QUEUEAC_Q3_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8822B) << BIT_SHIFT_QUEUEAC_Q3_V1_8822B) -#define BIT_GET_QUEUEAC_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822B) & BIT_MASK_QUEUEAC_Q3_V1_8822B) - +#define BIT_QUEUEAC_Q3_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q3_V1_8822B) << BIT_SHIFT_QUEUEAC_Q3_V1_8822B) +#define BITS_QUEUEAC_Q3_V1_8822B \ + (BIT_MASK_QUEUEAC_Q3_V1_8822B << BIT_SHIFT_QUEUEAC_Q3_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q3_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8822B)) +#define BIT_GET_QUEUEAC_Q3_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822B) & BIT_MASK_QUEUEAC_Q3_V1_8822B) +#define BIT_SET_QUEUEAC_Q3_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q3_V1_8822B(x) | BIT_QUEUEAC_Q3_V1_8822B(v)) #define BIT_TIDEMPTY_Q3_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q3_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q3_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q3_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) -#define BIT_GET_TAIL_PKT_Q3_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) & BIT_MASK_TAIL_PKT_Q3_V2_8822B) - - +#define BIT_TAIL_PKT_Q3_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) +#define BITS_TAIL_PKT_Q3_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q3_V2_8822B << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q3_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q3_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q3_V2_8822B) +#define BIT_SET_TAIL_PKT_Q3_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V2_8822B(x) | BIT_TAIL_PKT_Q3_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q3_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q3_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q3_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) -#define BIT_GET_HEAD_PKT_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) & BIT_MASK_HEAD_PKT_Q3_V1_8822B) - - +#define BIT_HEAD_PKT_Q3_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) +#define BITS_HEAD_PKT_Q3_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q3_V1_8822B << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q3_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q3_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q3_V1_8822B) +#define BIT_SET_HEAD_PKT_Q3_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3_V1_8822B(x) | BIT_HEAD_PKT_Q3_V1_8822B(v)) /* 2 REG_MGQ_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B 25 #define BIT_MASK_QUEUEMACID_MGQ_V1_8822B 0x7f -#define BIT_QUEUEMACID_MGQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) -#define BIT_GET_QUEUEMACID_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B) - - +#define BIT_QUEUEMACID_MGQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) +#define BITS_QUEUEMACID_MGQ_V1_8822B \ + (BIT_MASK_QUEUEMACID_MGQ_V1_8822B << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_MGQ_V1_8822B)) +#define BIT_GET_QUEUEMACID_MGQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) & \ + BIT_MASK_QUEUEMACID_MGQ_V1_8822B) +#define BIT_SET_QUEUEMACID_MGQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_MGQ_V1_8822B(x) | BIT_QUEUEMACID_MGQ_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_MGQ_V1_8822B 23 #define BIT_MASK_QUEUEAC_MGQ_V1_8822B 0x3 -#define BIT_QUEUEAC_MGQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822B) << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) -#define BIT_GET_QUEUEAC_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) & BIT_MASK_QUEUEAC_MGQ_V1_8822B) - +#define BIT_QUEUEAC_MGQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822B) \ + << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) +#define BITS_QUEUEAC_MGQ_V1_8822B \ + (BIT_MASK_QUEUEAC_MGQ_V1_8822B << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) +#define BIT_CLEAR_QUEUEAC_MGQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8822B)) +#define BIT_GET_QUEUEAC_MGQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) & \ + BIT_MASK_QUEUEAC_MGQ_V1_8822B) +#define BIT_SET_QUEUEAC_MGQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_MGQ_V1_8822B(x) | BIT_QUEUEAC_MGQ_V1_8822B(v)) #define BIT_TIDEMPTY_MGQ_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B 11 #define BIT_MASK_TAIL_PKT_MGQ_V2_8822B 0x7ff -#define BIT_TAIL_PKT_MGQ_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) -#define BIT_GET_TAIL_PKT_MGQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B) - - +#define BIT_TAIL_PKT_MGQ_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) +#define BITS_TAIL_PKT_MGQ_V2_8822B \ + (BIT_MASK_TAIL_PKT_MGQ_V2_8822B << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8822B)) +#define BIT_GET_TAIL_PKT_MGQ_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) & \ + BIT_MASK_TAIL_PKT_MGQ_V2_8822B) +#define BIT_SET_TAIL_PKT_MGQ_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V2_8822B(x) | BIT_TAIL_PKT_MGQ_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B 0 #define BIT_MASK_HEAD_PKT_MGQ_V1_8822B 0x7ff -#define BIT_HEAD_PKT_MGQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) -#define BIT_GET_HEAD_PKT_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B) - - +#define BIT_HEAD_PKT_MGQ_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) +#define BITS_HEAD_PKT_MGQ_V1_8822B \ + (BIT_MASK_HEAD_PKT_MGQ_V1_8822B << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8822B)) +#define BIT_GET_HEAD_PKT_MGQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) & \ + BIT_MASK_HEAD_PKT_MGQ_V1_8822B) +#define BIT_SET_HEAD_PKT_MGQ_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ_V1_8822B(x) | BIT_HEAD_PKT_MGQ_V1_8822B(v)) /* 2 REG_HIQ_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B 25 #define BIT_MASK_QUEUEMACID_HIQ_V1_8822B 0x7f -#define BIT_QUEUEMACID_HIQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) -#define BIT_GET_QUEUEMACID_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B) - - +#define BIT_QUEUEMACID_HIQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) +#define BITS_QUEUEMACID_HIQ_V1_8822B \ + (BIT_MASK_QUEUEMACID_HIQ_V1_8822B << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_HIQ_V1_8822B)) +#define BIT_GET_QUEUEMACID_HIQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) & \ + BIT_MASK_QUEUEMACID_HIQ_V1_8822B) +#define BIT_SET_QUEUEMACID_HIQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_HIQ_V1_8822B(x) | BIT_QUEUEMACID_HIQ_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_HIQ_V1_8822B 23 #define BIT_MASK_QUEUEAC_HIQ_V1_8822B 0x3 -#define BIT_QUEUEAC_HIQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822B) << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) -#define BIT_GET_QUEUEAC_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) & BIT_MASK_QUEUEAC_HIQ_V1_8822B) - +#define BIT_QUEUEAC_HIQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822B) \ + << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) +#define BITS_QUEUEAC_HIQ_V1_8822B \ + (BIT_MASK_QUEUEAC_HIQ_V1_8822B << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) +#define BIT_CLEAR_QUEUEAC_HIQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8822B)) +#define BIT_GET_QUEUEAC_HIQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) & \ + BIT_MASK_QUEUEAC_HIQ_V1_8822B) +#define BIT_SET_QUEUEAC_HIQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_HIQ_V1_8822B(x) | BIT_QUEUEAC_HIQ_V1_8822B(v)) #define BIT_TIDEMPTY_HIQ_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B 11 #define BIT_MASK_TAIL_PKT_HIQ_V2_8822B 0x7ff -#define BIT_TAIL_PKT_HIQ_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) -#define BIT_GET_TAIL_PKT_HIQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B) - - +#define BIT_TAIL_PKT_HIQ_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) +#define BITS_TAIL_PKT_HIQ_V2_8822B \ + (BIT_MASK_TAIL_PKT_HIQ_V2_8822B << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8822B)) +#define BIT_GET_TAIL_PKT_HIQ_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) & \ + BIT_MASK_TAIL_PKT_HIQ_V2_8822B) +#define BIT_SET_TAIL_PKT_HIQ_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V2_8822B(x) | BIT_TAIL_PKT_HIQ_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B 0 #define BIT_MASK_HEAD_PKT_HIQ_V1_8822B 0x7ff -#define BIT_HEAD_PKT_HIQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) -#define BIT_GET_HEAD_PKT_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B) - - +#define BIT_HEAD_PKT_HIQ_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) +#define BITS_HEAD_PKT_HIQ_V1_8822B \ + (BIT_MASK_HEAD_PKT_HIQ_V1_8822B << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8822B)) +#define BIT_GET_HEAD_PKT_HIQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) & \ + BIT_MASK_HEAD_PKT_HIQ_V1_8822B) +#define BIT_SET_HEAD_PKT_HIQ_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ_V1_8822B(x) | BIT_HEAD_PKT_HIQ_V1_8822B(v)) /* 2 REG_BCNQ_INFO_8822B */ #define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B 0 #define BIT_MASK_BCNQ_HEAD_PG_V1_8822B 0xfff -#define BIT_BCNQ_HEAD_PG_V1_8822B(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) -#define BIT_GET_BCNQ_HEAD_PG_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B) - - +#define BIT_BCNQ_HEAD_PG_V1_8822B(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B) \ + << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) +#define BITS_BCNQ_HEAD_PG_V1_8822B \ + (BIT_MASK_BCNQ_HEAD_PG_V1_8822B << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) +#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8822B(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8822B)) +#define BIT_GET_BCNQ_HEAD_PG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) & \ + BIT_MASK_BCNQ_HEAD_PG_V1_8822B) +#define BIT_SET_BCNQ_HEAD_PG_V1_8822B(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG_V1_8822B(x) | BIT_BCNQ_HEAD_PG_V1_8822B(v)) /* 2 REG_TXPKT_EMPTY_8822B */ #define BIT_BCNQ_EMPTY_8822B BIT(11) @@ -5410,10 +8221,17 @@ #define BIT_SHIFT_FW_FREE_TAIL_V1_8822B 0 #define BIT_MASK_FW_FREE_TAIL_V1_8822B 0xfff -#define BIT_FW_FREE_TAIL_V1_8822B(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8822B) << BIT_SHIFT_FW_FREE_TAIL_V1_8822B) -#define BIT_GET_FW_FREE_TAIL_V1_8822B(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822B) & BIT_MASK_FW_FREE_TAIL_V1_8822B) - - +#define BIT_FW_FREE_TAIL_V1_8822B(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL_V1_8822B) \ + << BIT_SHIFT_FW_FREE_TAIL_V1_8822B) +#define BITS_FW_FREE_TAIL_V1_8822B \ + (BIT_MASK_FW_FREE_TAIL_V1_8822B << BIT_SHIFT_FW_FREE_TAIL_V1_8822B) +#define BIT_CLEAR_FW_FREE_TAIL_V1_8822B(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8822B)) +#define BIT_GET_FW_FREE_TAIL_V1_8822B(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822B) & \ + BIT_MASK_FW_FREE_TAIL_V1_8822B) +#define BIT_SET_FW_FREE_TAIL_V1_8822B(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL_V1_8822B(x) | BIT_FW_FREE_TAIL_V1_8822B(v)) /* 2 REG_FWHW_TXQ_CTRL_8822B */ #define BIT_RTS_LIMIT_IN_OFDM_8822B BIT(23) @@ -5423,9 +8241,15 @@ #define BIT_SHIFT_EN_QUEUE_RPT_8822B 8 #define BIT_MASK_EN_QUEUE_RPT_8822B 0xff -#define BIT_EN_QUEUE_RPT_8822B(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8822B) << BIT_SHIFT_EN_QUEUE_RPT_8822B) -#define BIT_GET_EN_QUEUE_RPT_8822B(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822B) & BIT_MASK_EN_QUEUE_RPT_8822B) - +#define BIT_EN_QUEUE_RPT_8822B(x) \ + (((x) & BIT_MASK_EN_QUEUE_RPT_8822B) << BIT_SHIFT_EN_QUEUE_RPT_8822B) +#define BITS_EN_QUEUE_RPT_8822B \ + (BIT_MASK_EN_QUEUE_RPT_8822B << BIT_SHIFT_EN_QUEUE_RPT_8822B) +#define BIT_CLEAR_EN_QUEUE_RPT_8822B(x) ((x) & (~BITS_EN_QUEUE_RPT_8822B)) +#define BIT_GET_EN_QUEUE_RPT_8822B(x) \ + (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822B) & BIT_MASK_EN_QUEUE_RPT_8822B) +#define BIT_SET_EN_QUEUE_RPT_8822B(x, v) \ + (BIT_CLEAR_EN_QUEUE_RPT_8822B(x) | BIT_EN_QUEUE_RPT_8822B(v)) #define BIT_EN_RTY_BK_8822B BIT(7) #define BIT_EN_USE_INI_RAT_8822B BIT(6) @@ -5437,23 +8261,39 @@ #define BIT_EN_FTMRPT_8822B BIT(0) /* 2 REG_DATAFB_SEL_8822B */ -#define BIT__R_EN_RTY_BK_COD_8822B BIT(2) #define BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B 0 #define BIT_MASK__R_DATA_FALLBACK_SEL_8822B 0x3 -#define BIT__R_DATA_FALLBACK_SEL_8822B(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) -#define BIT_GET__R_DATA_FALLBACK_SEL_8822B(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B) - - +#define BIT__R_DATA_FALLBACK_SEL_8822B(x) \ + (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B) \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) +#define BITS__R_DATA_FALLBACK_SEL_8822B \ + (BIT_MASK__R_DATA_FALLBACK_SEL_8822B \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) +#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8822B(x) \ + ((x) & (~BITS__R_DATA_FALLBACK_SEL_8822B)) +#define BIT_GET__R_DATA_FALLBACK_SEL_8822B(x) \ + (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) & \ + BIT_MASK__R_DATA_FALLBACK_SEL_8822B) +#define BIT_SET__R_DATA_FALLBACK_SEL_8822B(x, v) \ + (BIT_CLEAR__R_DATA_FALLBACK_SEL_8822B(x) | \ + BIT__R_DATA_FALLBACK_SEL_8822B(v)) /* 2 REG_BCNQ_BDNY_V1_8822B */ #define BIT_SHIFT_BCNQ_PGBNDY_V1_8822B 0 #define BIT_MASK_BCNQ_PGBNDY_V1_8822B 0xfff -#define BIT_BCNQ_PGBNDY_V1_8822B(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822B) << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) -#define BIT_GET_BCNQ_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) & BIT_MASK_BCNQ_PGBNDY_V1_8822B) - - +#define BIT_BCNQ_PGBNDY_V1_8822B(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822B) \ + << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) +#define BITS_BCNQ_PGBNDY_V1_8822B \ + (BIT_MASK_BCNQ_PGBNDY_V1_8822B << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) +#define BIT_CLEAR_BCNQ_PGBNDY_V1_8822B(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8822B)) +#define BIT_GET_BCNQ_PGBNDY_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) & \ + BIT_MASK_BCNQ_PGBNDY_V1_8822B) +#define BIT_SET_BCNQ_PGBNDY_V1_8822B(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_V1_8822B(x) | BIT_BCNQ_PGBNDY_V1_8822B(v)) /* 2 REG_LIFETIME_EN_8822B */ #define BIT_BT_INT_CPU_8822B BIT(7) @@ -5468,33 +8308,55 @@ #define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B 8 #define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B 0xff -#define BIT_SPEC_SIFS_OFDM_PTCL_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) -#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) - - +#define BIT_SPEC_SIFS_OFDM_PTCL_8822B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) +#define BITS_SPEC_SIFS_OFDM_PTCL_8822B \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822B(x) \ + ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8822B)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) & \ + BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8822B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822B(x) | \ + BIT_SPEC_SIFS_OFDM_PTCL_8822B(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B 0 #define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B 0xff -#define BIT_SPEC_SIFS_CCK_PTCL_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) -#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) - - +#define BIT_SPEC_SIFS_CCK_PTCL_8822B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) +#define BITS_SPEC_SIFS_CCK_PTCL_8822B \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822B(x) \ + ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8822B)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) & \ + BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) +#define BIT_SET_SPEC_SIFS_CCK_PTCL_8822B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822B(x) | \ + BIT_SPEC_SIFS_CCK_PTCL_8822B(v)) /* 2 REG_RETRY_LIMIT_8822B */ #define BIT_SHIFT_SRL_8822B 8 #define BIT_MASK_SRL_8822B 0x3f #define BIT_SRL_8822B(x) (((x) & BIT_MASK_SRL_8822B) << BIT_SHIFT_SRL_8822B) +#define BITS_SRL_8822B (BIT_MASK_SRL_8822B << BIT_SHIFT_SRL_8822B) +#define BIT_CLEAR_SRL_8822B(x) ((x) & (~BITS_SRL_8822B)) #define BIT_GET_SRL_8822B(x) (((x) >> BIT_SHIFT_SRL_8822B) & BIT_MASK_SRL_8822B) - - +#define BIT_SET_SRL_8822B(x, v) (BIT_CLEAR_SRL_8822B(x) | BIT_SRL_8822B(v)) #define BIT_SHIFT_LRL_8822B 0 #define BIT_MASK_LRL_8822B 0x3f #define BIT_LRL_8822B(x) (((x) & BIT_MASK_LRL_8822B) << BIT_SHIFT_LRL_8822B) +#define BITS_LRL_8822B (BIT_MASK_LRL_8822B << BIT_SHIFT_LRL_8822B) +#define BIT_CLEAR_LRL_8822B(x) ((x) & (~BITS_LRL_8822B)) #define BIT_GET_LRL_8822B(x) (((x) >> BIT_SHIFT_LRL_8822B) & BIT_MASK_LRL_8822B) - - +#define BIT_SET_LRL_8822B(x, v) (BIT_CLEAR_LRL_8822B(x) | BIT_LRL_8822B(v)) /* 2 REG_TXBF_CTRL_8822B */ #define BIT_R_ENABLE_NDPA_8822B BIT(31) @@ -5507,9 +8369,15 @@ #define BIT_SHIFT_R_TXBF1_AID_8822B 16 #define BIT_MASK_R_TXBF1_AID_8822B 0x1ff -#define BIT_R_TXBF1_AID_8822B(x) (((x) & BIT_MASK_R_TXBF1_AID_8822B) << BIT_SHIFT_R_TXBF1_AID_8822B) -#define BIT_GET_R_TXBF1_AID_8822B(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8822B) & BIT_MASK_R_TXBF1_AID_8822B) - +#define BIT_R_TXBF1_AID_8822B(x) \ + (((x) & BIT_MASK_R_TXBF1_AID_8822B) << BIT_SHIFT_R_TXBF1_AID_8822B) +#define BITS_R_TXBF1_AID_8822B \ + (BIT_MASK_R_TXBF1_AID_8822B << BIT_SHIFT_R_TXBF1_AID_8822B) +#define BIT_CLEAR_R_TXBF1_AID_8822B(x) ((x) & (~BITS_R_TXBF1_AID_8822B)) +#define BIT_GET_R_TXBF1_AID_8822B(x) \ + (((x) >> BIT_SHIFT_R_TXBF1_AID_8822B) & BIT_MASK_R_TXBF1_AID_8822B) +#define BIT_SET_R_TXBF1_AID_8822B(x, v) \ + (BIT_CLEAR_R_TXBF1_AID_8822B(x) | BIT_R_TXBF1_AID_8822B(v)) #define BIT_DIS_NDP_BFEN_8822B BIT(15) #define BIT_R_TXBCN_NOBLOCK_NDP_8822B BIT(14) @@ -5519,161 +8387,267 @@ #define BIT_SHIFT_R_TXBF0_AID_8822B 0 #define BIT_MASK_R_TXBF0_AID_8822B 0x1ff -#define BIT_R_TXBF0_AID_8822B(x) (((x) & BIT_MASK_R_TXBF0_AID_8822B) << BIT_SHIFT_R_TXBF0_AID_8822B) -#define BIT_GET_R_TXBF0_AID_8822B(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8822B) & BIT_MASK_R_TXBF0_AID_8822B) - - +#define BIT_R_TXBF0_AID_8822B(x) \ + (((x) & BIT_MASK_R_TXBF0_AID_8822B) << BIT_SHIFT_R_TXBF0_AID_8822B) +#define BITS_R_TXBF0_AID_8822B \ + (BIT_MASK_R_TXBF0_AID_8822B << BIT_SHIFT_R_TXBF0_AID_8822B) +#define BIT_CLEAR_R_TXBF0_AID_8822B(x) ((x) & (~BITS_R_TXBF0_AID_8822B)) +#define BIT_GET_R_TXBF0_AID_8822B(x) \ + (((x) >> BIT_SHIFT_R_TXBF0_AID_8822B) & BIT_MASK_R_TXBF0_AID_8822B) +#define BIT_SET_R_TXBF0_AID_8822B(x, v) \ + (BIT_CLEAR_R_TXBF0_AID_8822B(x) | BIT_R_TXBF0_AID_8822B(v)) /* 2 REG_DARFRC_8822B */ #define BIT_SHIFT_DARF_RC8_8822B (56 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC8_8822B 0x1f -#define BIT_DARF_RC8_8822B(x) (((x) & BIT_MASK_DARF_RC8_8822B) << BIT_SHIFT_DARF_RC8_8822B) -#define BIT_GET_DARF_RC8_8822B(x) (((x) >> BIT_SHIFT_DARF_RC8_8822B) & BIT_MASK_DARF_RC8_8822B) - - +#define BIT_DARF_RC8_8822B(x) \ + (((x) & BIT_MASK_DARF_RC8_8822B) << BIT_SHIFT_DARF_RC8_8822B) +#define BITS_DARF_RC8_8822B \ + (BIT_MASK_DARF_RC8_8822B << BIT_SHIFT_DARF_RC8_8822B) +#define BIT_CLEAR_DARF_RC8_8822B(x) ((x) & (~BITS_DARF_RC8_8822B)) +#define BIT_GET_DARF_RC8_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_8822B) & BIT_MASK_DARF_RC8_8822B) +#define BIT_SET_DARF_RC8_8822B(x, v) \ + (BIT_CLEAR_DARF_RC8_8822B(x) | BIT_DARF_RC8_8822B(v)) #define BIT_SHIFT_DARF_RC7_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC7_8822B 0x1f -#define BIT_DARF_RC7_8822B(x) (((x) & BIT_MASK_DARF_RC7_8822B) << BIT_SHIFT_DARF_RC7_8822B) -#define BIT_GET_DARF_RC7_8822B(x) (((x) >> BIT_SHIFT_DARF_RC7_8822B) & BIT_MASK_DARF_RC7_8822B) - - +#define BIT_DARF_RC7_8822B(x) \ + (((x) & BIT_MASK_DARF_RC7_8822B) << BIT_SHIFT_DARF_RC7_8822B) +#define BITS_DARF_RC7_8822B \ + (BIT_MASK_DARF_RC7_8822B << BIT_SHIFT_DARF_RC7_8822B) +#define BIT_CLEAR_DARF_RC7_8822B(x) ((x) & (~BITS_DARF_RC7_8822B)) +#define BIT_GET_DARF_RC7_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_8822B) & BIT_MASK_DARF_RC7_8822B) +#define BIT_SET_DARF_RC7_8822B(x, v) \ + (BIT_CLEAR_DARF_RC7_8822B(x) | BIT_DARF_RC7_8822B(v)) #define BIT_SHIFT_DARF_RC6_8822B (40 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC6_8822B 0x1f -#define BIT_DARF_RC6_8822B(x) (((x) & BIT_MASK_DARF_RC6_8822B) << BIT_SHIFT_DARF_RC6_8822B) -#define BIT_GET_DARF_RC6_8822B(x) (((x) >> BIT_SHIFT_DARF_RC6_8822B) & BIT_MASK_DARF_RC6_8822B) - - +#define BIT_DARF_RC6_8822B(x) \ + (((x) & BIT_MASK_DARF_RC6_8822B) << BIT_SHIFT_DARF_RC6_8822B) +#define BITS_DARF_RC6_8822B \ + (BIT_MASK_DARF_RC6_8822B << BIT_SHIFT_DARF_RC6_8822B) +#define BIT_CLEAR_DARF_RC6_8822B(x) ((x) & (~BITS_DARF_RC6_8822B)) +#define BIT_GET_DARF_RC6_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_8822B) & BIT_MASK_DARF_RC6_8822B) +#define BIT_SET_DARF_RC6_8822B(x, v) \ + (BIT_CLEAR_DARF_RC6_8822B(x) | BIT_DARF_RC6_8822B(v)) #define BIT_SHIFT_DARF_RC5_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_DARF_RC5_8822B 0x1f -#define BIT_DARF_RC5_8822B(x) (((x) & BIT_MASK_DARF_RC5_8822B) << BIT_SHIFT_DARF_RC5_8822B) -#define BIT_GET_DARF_RC5_8822B(x) (((x) >> BIT_SHIFT_DARF_RC5_8822B) & BIT_MASK_DARF_RC5_8822B) - - +#define BIT_DARF_RC5_8822B(x) \ + (((x) & BIT_MASK_DARF_RC5_8822B) << BIT_SHIFT_DARF_RC5_8822B) +#define BITS_DARF_RC5_8822B \ + (BIT_MASK_DARF_RC5_8822B << BIT_SHIFT_DARF_RC5_8822B) +#define BIT_CLEAR_DARF_RC5_8822B(x) ((x) & (~BITS_DARF_RC5_8822B)) +#define BIT_GET_DARF_RC5_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_8822B) & BIT_MASK_DARF_RC5_8822B) +#define BIT_SET_DARF_RC5_8822B(x, v) \ + (BIT_CLEAR_DARF_RC5_8822B(x) | BIT_DARF_RC5_8822B(v)) #define BIT_SHIFT_DARF_RC4_8822B 24 #define BIT_MASK_DARF_RC4_8822B 0x1f -#define BIT_DARF_RC4_8822B(x) (((x) & BIT_MASK_DARF_RC4_8822B) << BIT_SHIFT_DARF_RC4_8822B) -#define BIT_GET_DARF_RC4_8822B(x) (((x) >> BIT_SHIFT_DARF_RC4_8822B) & BIT_MASK_DARF_RC4_8822B) - - +#define BIT_DARF_RC4_8822B(x) \ + (((x) & BIT_MASK_DARF_RC4_8822B) << BIT_SHIFT_DARF_RC4_8822B) +#define BITS_DARF_RC4_8822B \ + (BIT_MASK_DARF_RC4_8822B << BIT_SHIFT_DARF_RC4_8822B) +#define BIT_CLEAR_DARF_RC4_8822B(x) ((x) & (~BITS_DARF_RC4_8822B)) +#define BIT_GET_DARF_RC4_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_8822B) & BIT_MASK_DARF_RC4_8822B) +#define BIT_SET_DARF_RC4_8822B(x, v) \ + (BIT_CLEAR_DARF_RC4_8822B(x) | BIT_DARF_RC4_8822B(v)) #define BIT_SHIFT_DARF_RC3_8822B 16 #define BIT_MASK_DARF_RC3_8822B 0x1f -#define BIT_DARF_RC3_8822B(x) (((x) & BIT_MASK_DARF_RC3_8822B) << BIT_SHIFT_DARF_RC3_8822B) -#define BIT_GET_DARF_RC3_8822B(x) (((x) >> BIT_SHIFT_DARF_RC3_8822B) & BIT_MASK_DARF_RC3_8822B) - - +#define BIT_DARF_RC3_8822B(x) \ + (((x) & BIT_MASK_DARF_RC3_8822B) << BIT_SHIFT_DARF_RC3_8822B) +#define BITS_DARF_RC3_8822B \ + (BIT_MASK_DARF_RC3_8822B << BIT_SHIFT_DARF_RC3_8822B) +#define BIT_CLEAR_DARF_RC3_8822B(x) ((x) & (~BITS_DARF_RC3_8822B)) +#define BIT_GET_DARF_RC3_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_8822B) & BIT_MASK_DARF_RC3_8822B) +#define BIT_SET_DARF_RC3_8822B(x, v) \ + (BIT_CLEAR_DARF_RC3_8822B(x) | BIT_DARF_RC3_8822B(v)) #define BIT_SHIFT_DARF_RC2_8822B 8 #define BIT_MASK_DARF_RC2_8822B 0x1f -#define BIT_DARF_RC2_8822B(x) (((x) & BIT_MASK_DARF_RC2_8822B) << BIT_SHIFT_DARF_RC2_8822B) -#define BIT_GET_DARF_RC2_8822B(x) (((x) >> BIT_SHIFT_DARF_RC2_8822B) & BIT_MASK_DARF_RC2_8822B) - - +#define BIT_DARF_RC2_8822B(x) \ + (((x) & BIT_MASK_DARF_RC2_8822B) << BIT_SHIFT_DARF_RC2_8822B) +#define BITS_DARF_RC2_8822B \ + (BIT_MASK_DARF_RC2_8822B << BIT_SHIFT_DARF_RC2_8822B) +#define BIT_CLEAR_DARF_RC2_8822B(x) ((x) & (~BITS_DARF_RC2_8822B)) +#define BIT_GET_DARF_RC2_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_8822B) & BIT_MASK_DARF_RC2_8822B) +#define BIT_SET_DARF_RC2_8822B(x, v) \ + (BIT_CLEAR_DARF_RC2_8822B(x) | BIT_DARF_RC2_8822B(v)) #define BIT_SHIFT_DARF_RC1_8822B 0 #define BIT_MASK_DARF_RC1_8822B 0x1f -#define BIT_DARF_RC1_8822B(x) (((x) & BIT_MASK_DARF_RC1_8822B) << BIT_SHIFT_DARF_RC1_8822B) -#define BIT_GET_DARF_RC1_8822B(x) (((x) >> BIT_SHIFT_DARF_RC1_8822B) & BIT_MASK_DARF_RC1_8822B) - - +#define BIT_DARF_RC1_8822B(x) \ + (((x) & BIT_MASK_DARF_RC1_8822B) << BIT_SHIFT_DARF_RC1_8822B) +#define BITS_DARF_RC1_8822B \ + (BIT_MASK_DARF_RC1_8822B << BIT_SHIFT_DARF_RC1_8822B) +#define BIT_CLEAR_DARF_RC1_8822B(x) ((x) & (~BITS_DARF_RC1_8822B)) +#define BIT_GET_DARF_RC1_8822B(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_8822B) & BIT_MASK_DARF_RC1_8822B) +#define BIT_SET_DARF_RC1_8822B(x, v) \ + (BIT_CLEAR_DARF_RC1_8822B(x) | BIT_DARF_RC1_8822B(v)) /* 2 REG_RARFRC_8822B */ #define BIT_SHIFT_RARF_RC8_8822B (56 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC8_8822B 0x1f -#define BIT_RARF_RC8_8822B(x) (((x) & BIT_MASK_RARF_RC8_8822B) << BIT_SHIFT_RARF_RC8_8822B) -#define BIT_GET_RARF_RC8_8822B(x) (((x) >> BIT_SHIFT_RARF_RC8_8822B) & BIT_MASK_RARF_RC8_8822B) - - +#define BIT_RARF_RC8_8822B(x) \ + (((x) & BIT_MASK_RARF_RC8_8822B) << BIT_SHIFT_RARF_RC8_8822B) +#define BITS_RARF_RC8_8822B \ + (BIT_MASK_RARF_RC8_8822B << BIT_SHIFT_RARF_RC8_8822B) +#define BIT_CLEAR_RARF_RC8_8822B(x) ((x) & (~BITS_RARF_RC8_8822B)) +#define BIT_GET_RARF_RC8_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_8822B) & BIT_MASK_RARF_RC8_8822B) +#define BIT_SET_RARF_RC8_8822B(x, v) \ + (BIT_CLEAR_RARF_RC8_8822B(x) | BIT_RARF_RC8_8822B(v)) #define BIT_SHIFT_RARF_RC7_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC7_8822B 0x1f -#define BIT_RARF_RC7_8822B(x) (((x) & BIT_MASK_RARF_RC7_8822B) << BIT_SHIFT_RARF_RC7_8822B) -#define BIT_GET_RARF_RC7_8822B(x) (((x) >> BIT_SHIFT_RARF_RC7_8822B) & BIT_MASK_RARF_RC7_8822B) - - +#define BIT_RARF_RC7_8822B(x) \ + (((x) & BIT_MASK_RARF_RC7_8822B) << BIT_SHIFT_RARF_RC7_8822B) +#define BITS_RARF_RC7_8822B \ + (BIT_MASK_RARF_RC7_8822B << BIT_SHIFT_RARF_RC7_8822B) +#define BIT_CLEAR_RARF_RC7_8822B(x) ((x) & (~BITS_RARF_RC7_8822B)) +#define BIT_GET_RARF_RC7_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_8822B) & BIT_MASK_RARF_RC7_8822B) +#define BIT_SET_RARF_RC7_8822B(x, v) \ + (BIT_CLEAR_RARF_RC7_8822B(x) | BIT_RARF_RC7_8822B(v)) #define BIT_SHIFT_RARF_RC6_8822B (40 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC6_8822B 0x1f -#define BIT_RARF_RC6_8822B(x) (((x) & BIT_MASK_RARF_RC6_8822B) << BIT_SHIFT_RARF_RC6_8822B) -#define BIT_GET_RARF_RC6_8822B(x) (((x) >> BIT_SHIFT_RARF_RC6_8822B) & BIT_MASK_RARF_RC6_8822B) - - +#define BIT_RARF_RC6_8822B(x) \ + (((x) & BIT_MASK_RARF_RC6_8822B) << BIT_SHIFT_RARF_RC6_8822B) +#define BITS_RARF_RC6_8822B \ + (BIT_MASK_RARF_RC6_8822B << BIT_SHIFT_RARF_RC6_8822B) +#define BIT_CLEAR_RARF_RC6_8822B(x) ((x) & (~BITS_RARF_RC6_8822B)) +#define BIT_GET_RARF_RC6_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_8822B) & BIT_MASK_RARF_RC6_8822B) +#define BIT_SET_RARF_RC6_8822B(x, v) \ + (BIT_CLEAR_RARF_RC6_8822B(x) | BIT_RARF_RC6_8822B(v)) #define BIT_SHIFT_RARF_RC5_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_RARF_RC5_8822B 0x1f -#define BIT_RARF_RC5_8822B(x) (((x) & BIT_MASK_RARF_RC5_8822B) << BIT_SHIFT_RARF_RC5_8822B) -#define BIT_GET_RARF_RC5_8822B(x) (((x) >> BIT_SHIFT_RARF_RC5_8822B) & BIT_MASK_RARF_RC5_8822B) - - +#define BIT_RARF_RC5_8822B(x) \ + (((x) & BIT_MASK_RARF_RC5_8822B) << BIT_SHIFT_RARF_RC5_8822B) +#define BITS_RARF_RC5_8822B \ + (BIT_MASK_RARF_RC5_8822B << BIT_SHIFT_RARF_RC5_8822B) +#define BIT_CLEAR_RARF_RC5_8822B(x) ((x) & (~BITS_RARF_RC5_8822B)) +#define BIT_GET_RARF_RC5_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_8822B) & BIT_MASK_RARF_RC5_8822B) +#define BIT_SET_RARF_RC5_8822B(x, v) \ + (BIT_CLEAR_RARF_RC5_8822B(x) | BIT_RARF_RC5_8822B(v)) #define BIT_SHIFT_RARF_RC4_8822B 24 #define BIT_MASK_RARF_RC4_8822B 0x1f -#define BIT_RARF_RC4_8822B(x) (((x) & BIT_MASK_RARF_RC4_8822B) << BIT_SHIFT_RARF_RC4_8822B) -#define BIT_GET_RARF_RC4_8822B(x) (((x) >> BIT_SHIFT_RARF_RC4_8822B) & BIT_MASK_RARF_RC4_8822B) - - +#define BIT_RARF_RC4_8822B(x) \ + (((x) & BIT_MASK_RARF_RC4_8822B) << BIT_SHIFT_RARF_RC4_8822B) +#define BITS_RARF_RC4_8822B \ + (BIT_MASK_RARF_RC4_8822B << BIT_SHIFT_RARF_RC4_8822B) +#define BIT_CLEAR_RARF_RC4_8822B(x) ((x) & (~BITS_RARF_RC4_8822B)) +#define BIT_GET_RARF_RC4_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC4_8822B) & BIT_MASK_RARF_RC4_8822B) +#define BIT_SET_RARF_RC4_8822B(x, v) \ + (BIT_CLEAR_RARF_RC4_8822B(x) | BIT_RARF_RC4_8822B(v)) #define BIT_SHIFT_RARF_RC3_8822B 16 #define BIT_MASK_RARF_RC3_8822B 0x1f -#define BIT_RARF_RC3_8822B(x) (((x) & BIT_MASK_RARF_RC3_8822B) << BIT_SHIFT_RARF_RC3_8822B) -#define BIT_GET_RARF_RC3_8822B(x) (((x) >> BIT_SHIFT_RARF_RC3_8822B) & BIT_MASK_RARF_RC3_8822B) - - +#define BIT_RARF_RC3_8822B(x) \ + (((x) & BIT_MASK_RARF_RC3_8822B) << BIT_SHIFT_RARF_RC3_8822B) +#define BITS_RARF_RC3_8822B \ + (BIT_MASK_RARF_RC3_8822B << BIT_SHIFT_RARF_RC3_8822B) +#define BIT_CLEAR_RARF_RC3_8822B(x) ((x) & (~BITS_RARF_RC3_8822B)) +#define BIT_GET_RARF_RC3_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC3_8822B) & BIT_MASK_RARF_RC3_8822B) +#define BIT_SET_RARF_RC3_8822B(x, v) \ + (BIT_CLEAR_RARF_RC3_8822B(x) | BIT_RARF_RC3_8822B(v)) #define BIT_SHIFT_RARF_RC2_8822B 8 #define BIT_MASK_RARF_RC2_8822B 0x1f -#define BIT_RARF_RC2_8822B(x) (((x) & BIT_MASK_RARF_RC2_8822B) << BIT_SHIFT_RARF_RC2_8822B) -#define BIT_GET_RARF_RC2_8822B(x) (((x) >> BIT_SHIFT_RARF_RC2_8822B) & BIT_MASK_RARF_RC2_8822B) - - +#define BIT_RARF_RC2_8822B(x) \ + (((x) & BIT_MASK_RARF_RC2_8822B) << BIT_SHIFT_RARF_RC2_8822B) +#define BITS_RARF_RC2_8822B \ + (BIT_MASK_RARF_RC2_8822B << BIT_SHIFT_RARF_RC2_8822B) +#define BIT_CLEAR_RARF_RC2_8822B(x) ((x) & (~BITS_RARF_RC2_8822B)) +#define BIT_GET_RARF_RC2_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC2_8822B) & BIT_MASK_RARF_RC2_8822B) +#define BIT_SET_RARF_RC2_8822B(x, v) \ + (BIT_CLEAR_RARF_RC2_8822B(x) | BIT_RARF_RC2_8822B(v)) #define BIT_SHIFT_RARF_RC1_8822B 0 #define BIT_MASK_RARF_RC1_8822B 0x1f -#define BIT_RARF_RC1_8822B(x) (((x) & BIT_MASK_RARF_RC1_8822B) << BIT_SHIFT_RARF_RC1_8822B) -#define BIT_GET_RARF_RC1_8822B(x) (((x) >> BIT_SHIFT_RARF_RC1_8822B) & BIT_MASK_RARF_RC1_8822B) - - +#define BIT_RARF_RC1_8822B(x) \ + (((x) & BIT_MASK_RARF_RC1_8822B) << BIT_SHIFT_RARF_RC1_8822B) +#define BITS_RARF_RC1_8822B \ + (BIT_MASK_RARF_RC1_8822B << BIT_SHIFT_RARF_RC1_8822B) +#define BIT_CLEAR_RARF_RC1_8822B(x) ((x) & (~BITS_RARF_RC1_8822B)) +#define BIT_GET_RARF_RC1_8822B(x) \ + (((x) >> BIT_SHIFT_RARF_RC1_8822B) & BIT_MASK_RARF_RC1_8822B) +#define BIT_SET_RARF_RC1_8822B(x, v) \ + (BIT_CLEAR_RARF_RC1_8822B(x) | BIT_RARF_RC1_8822B(v)) /* 2 REG_RRSR_8822B */ #define BIT_SHIFT_RRSR_RSC_8822B 21 #define BIT_MASK_RRSR_RSC_8822B 0x3 -#define BIT_RRSR_RSC_8822B(x) (((x) & BIT_MASK_RRSR_RSC_8822B) << BIT_SHIFT_RRSR_RSC_8822B) -#define BIT_GET_RRSR_RSC_8822B(x) (((x) >> BIT_SHIFT_RRSR_RSC_8822B) & BIT_MASK_RRSR_RSC_8822B) - +#define BIT_RRSR_RSC_8822B(x) \ + (((x) & BIT_MASK_RRSR_RSC_8822B) << BIT_SHIFT_RRSR_RSC_8822B) +#define BITS_RRSR_RSC_8822B \ + (BIT_MASK_RRSR_RSC_8822B << BIT_SHIFT_RRSR_RSC_8822B) +#define BIT_CLEAR_RRSR_RSC_8822B(x) ((x) & (~BITS_RRSR_RSC_8822B)) +#define BIT_GET_RRSR_RSC_8822B(x) \ + (((x) >> BIT_SHIFT_RRSR_RSC_8822B) & BIT_MASK_RRSR_RSC_8822B) +#define BIT_SET_RRSR_RSC_8822B(x, v) \ + (BIT_CLEAR_RRSR_RSC_8822B(x) | BIT_RRSR_RSC_8822B(v)) #define BIT_RRSR_BW_8822B BIT(20) #define BIT_SHIFT_RRSC_BITMAP_8822B 0 #define BIT_MASK_RRSC_BITMAP_8822B 0xfffff -#define BIT_RRSC_BITMAP_8822B(x) (((x) & BIT_MASK_RRSC_BITMAP_8822B) << BIT_SHIFT_RRSC_BITMAP_8822B) -#define BIT_GET_RRSC_BITMAP_8822B(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8822B) & BIT_MASK_RRSC_BITMAP_8822B) - - +#define BIT_RRSC_BITMAP_8822B(x) \ + (((x) & BIT_MASK_RRSC_BITMAP_8822B) << BIT_SHIFT_RRSC_BITMAP_8822B) +#define BITS_RRSC_BITMAP_8822B \ + (BIT_MASK_RRSC_BITMAP_8822B << BIT_SHIFT_RRSC_BITMAP_8822B) +#define BIT_CLEAR_RRSC_BITMAP_8822B(x) ((x) & (~BITS_RRSC_BITMAP_8822B)) +#define BIT_GET_RRSC_BITMAP_8822B(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP_8822B) & BIT_MASK_RRSC_BITMAP_8822B) +#define BIT_SET_RRSC_BITMAP_8822B(x, v) \ + (BIT_CLEAR_RRSC_BITMAP_8822B(x) | BIT_RRSC_BITMAP_8822B(v)) /* 2 REG_ARFR0_8822B */ #define BIT_SHIFT_ARFR0_V1_8822B 0 #define BIT_MASK_ARFR0_V1_8822B 0xffffffffffffffffL -#define BIT_ARFR0_V1_8822B(x) (((x) & BIT_MASK_ARFR0_V1_8822B) << BIT_SHIFT_ARFR0_V1_8822B) -#define BIT_GET_ARFR0_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR0_V1_8822B) & BIT_MASK_ARFR0_V1_8822B) - - +#define BIT_ARFR0_V1_8822B(x) \ + (((x) & BIT_MASK_ARFR0_V1_8822B) << BIT_SHIFT_ARFR0_V1_8822B) +#define BITS_ARFR0_V1_8822B \ + (BIT_MASK_ARFR0_V1_8822B << BIT_SHIFT_ARFR0_V1_8822B) +#define BIT_CLEAR_ARFR0_V1_8822B(x) ((x) & (~BITS_ARFR0_V1_8822B)) +#define BIT_GET_ARFR0_V1_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR0_V1_8822B) & BIT_MASK_ARFR0_V1_8822B) +#define BIT_SET_ARFR0_V1_8822B(x, v) \ + (BIT_CLEAR_ARFR0_V1_8822B(x) | BIT_ARFR0_V1_8822B(v)) /* 2 REG_ARFR1_V1_8822B */ #define BIT_SHIFT_ARFR1_V1_8822B 0 #define BIT_MASK_ARFR1_V1_8822B 0xffffffffffffffffL -#define BIT_ARFR1_V1_8822B(x) (((x) & BIT_MASK_ARFR1_V1_8822B) << BIT_SHIFT_ARFR1_V1_8822B) -#define BIT_GET_ARFR1_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR1_V1_8822B) & BIT_MASK_ARFR1_V1_8822B) - - +#define BIT_ARFR1_V1_8822B(x) \ + (((x) & BIT_MASK_ARFR1_V1_8822B) << BIT_SHIFT_ARFR1_V1_8822B) +#define BITS_ARFR1_V1_8822B \ + (BIT_MASK_ARFR1_V1_8822B << BIT_SHIFT_ARFR1_V1_8822B) +#define BIT_CLEAR_ARFR1_V1_8822B(x) ((x) & (~BITS_ARFR1_V1_8822B)) +#define BIT_GET_ARFR1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR1_V1_8822B) & BIT_MASK_ARFR1_V1_8822B) +#define BIT_SET_ARFR1_V1_8822B(x, v) \ + (BIT_CLEAR_ARFR1_V1_8822B(x) | BIT_ARFR1_V1_8822B(v)) /* 2 REG_CCK_CHECK_8822B */ #define BIT_CHECK_CCK_EN_8822B BIT(7) @@ -5689,28 +8663,50 @@ #define BIT_SHIFT_AMPDU_MAX_TIME_8822B 0 #define BIT_MASK_AMPDU_MAX_TIME_8822B 0xff -#define BIT_AMPDU_MAX_TIME_8822B(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8822B) << BIT_SHIFT_AMPDU_MAX_TIME_8822B) -#define BIT_GET_AMPDU_MAX_TIME_8822B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822B) & BIT_MASK_AMPDU_MAX_TIME_8822B) - - +#define BIT_AMPDU_MAX_TIME_8822B(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME_8822B) \ + << BIT_SHIFT_AMPDU_MAX_TIME_8822B) +#define BITS_AMPDU_MAX_TIME_8822B \ + (BIT_MASK_AMPDU_MAX_TIME_8822B << BIT_SHIFT_AMPDU_MAX_TIME_8822B) +#define BIT_CLEAR_AMPDU_MAX_TIME_8822B(x) ((x) & (~BITS_AMPDU_MAX_TIME_8822B)) +#define BIT_GET_AMPDU_MAX_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822B) & \ + BIT_MASK_AMPDU_MAX_TIME_8822B) +#define BIT_SET_AMPDU_MAX_TIME_8822B(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME_8822B(x) | BIT_AMPDU_MAX_TIME_8822B(v)) /* 2 REG_BCNQ1_BDNY_V1_8822B */ #define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B 0 #define BIT_MASK_BCNQ1_PGBNDY_V1_8822B 0xfff -#define BIT_BCNQ1_PGBNDY_V1_8822B(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) -#define BIT_GET_BCNQ1_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B) - - +#define BIT_BCNQ1_PGBNDY_V1_8822B(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B) \ + << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) +#define BITS_BCNQ1_PGBNDY_V1_8822B \ + (BIT_MASK_BCNQ1_PGBNDY_V1_8822B << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) +#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8822B(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8822B)) +#define BIT_GET_BCNQ1_PGBNDY_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) & \ + BIT_MASK_BCNQ1_PGBNDY_V1_8822B) +#define BIT_SET_BCNQ1_PGBNDY_V1_8822B(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY_V1_8822B(x) | BIT_BCNQ1_PGBNDY_V1_8822B(v)) /* 2 REG_AMPDU_MAX_LENGTH_8822B */ #define BIT_SHIFT_AMPDU_MAX_LENGTH_8822B 0 #define BIT_MASK_AMPDU_MAX_LENGTH_8822B 0xffffffffL -#define BIT_AMPDU_MAX_LENGTH_8822B(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8822B) << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) -#define BIT_GET_AMPDU_MAX_LENGTH_8822B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) & BIT_MASK_AMPDU_MAX_LENGTH_8822B) - - +#define BIT_AMPDU_MAX_LENGTH_8822B(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8822B) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) +#define BITS_AMPDU_MAX_LENGTH_8822B \ + (BIT_MASK_AMPDU_MAX_LENGTH_8822B << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_8822B(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_8822B)) +#define BIT_GET_AMPDU_MAX_LENGTH_8822B(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) & \ + BIT_MASK_AMPDU_MAX_LENGTH_8822B) +#define BIT_SET_AMPDU_MAX_LENGTH_8822B(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_8822B(x) | BIT_AMPDU_MAX_LENGTH_8822B(v)) /* 2 REG_ACQ_STOP_8822B */ #define BIT_AC7Q_STOP_8822B BIT(7) @@ -5726,10 +8722,17 @@ #define BIT_SHIFT_R_NDPA_RATE_V1_8822B 0 #define BIT_MASK_R_NDPA_RATE_V1_8822B 0xff -#define BIT_R_NDPA_RATE_V1_8822B(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8822B) << BIT_SHIFT_R_NDPA_RATE_V1_8822B) -#define BIT_GET_R_NDPA_RATE_V1_8822B(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822B) & BIT_MASK_R_NDPA_RATE_V1_8822B) - - +#define BIT_R_NDPA_RATE_V1_8822B(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1_8822B) \ + << BIT_SHIFT_R_NDPA_RATE_V1_8822B) +#define BITS_R_NDPA_RATE_V1_8822B \ + (BIT_MASK_R_NDPA_RATE_V1_8822B << BIT_SHIFT_R_NDPA_RATE_V1_8822B) +#define BIT_CLEAR_R_NDPA_RATE_V1_8822B(x) ((x) & (~BITS_R_NDPA_RATE_V1_8822B)) +#define BIT_GET_R_NDPA_RATE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822B) & \ + BIT_MASK_R_NDPA_RATE_V1_8822B) +#define BIT_SET_R_NDPA_RATE_V1_8822B(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1_8822B(x) | BIT_R_NDPA_RATE_V1_8822B(v)) /* 2 REG_TX_HANG_CTRL_8822B */ #define BIT_R_EN_GNT_BT_AWAKE_8822B BIT(3) @@ -5742,230 +8745,437 @@ #define BIT_SHIFT_BW_SIGTA_8822B 3 #define BIT_MASK_BW_SIGTA_8822B 0x3 -#define BIT_BW_SIGTA_8822B(x) (((x) & BIT_MASK_BW_SIGTA_8822B) << BIT_SHIFT_BW_SIGTA_8822B) -#define BIT_GET_BW_SIGTA_8822B(x) (((x) >> BIT_SHIFT_BW_SIGTA_8822B) & BIT_MASK_BW_SIGTA_8822B) - +#define BIT_BW_SIGTA_8822B(x) \ + (((x) & BIT_MASK_BW_SIGTA_8822B) << BIT_SHIFT_BW_SIGTA_8822B) +#define BITS_BW_SIGTA_8822B \ + (BIT_MASK_BW_SIGTA_8822B << BIT_SHIFT_BW_SIGTA_8822B) +#define BIT_CLEAR_BW_SIGTA_8822B(x) ((x) & (~BITS_BW_SIGTA_8822B)) +#define BIT_GET_BW_SIGTA_8822B(x) \ + (((x) >> BIT_SHIFT_BW_SIGTA_8822B) & BIT_MASK_BW_SIGTA_8822B) +#define BIT_SET_BW_SIGTA_8822B(x, v) \ + (BIT_CLEAR_BW_SIGTA_8822B(x) | BIT_BW_SIGTA_8822B(v)) #define BIT_EN_BAR_SIGTA_8822B BIT(2) #define BIT_SHIFT_R_NDPA_BW_8822B 0 #define BIT_MASK_R_NDPA_BW_8822B 0x3 -#define BIT_R_NDPA_BW_8822B(x) (((x) & BIT_MASK_R_NDPA_BW_8822B) << BIT_SHIFT_R_NDPA_BW_8822B) -#define BIT_GET_R_NDPA_BW_8822B(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8822B) & BIT_MASK_R_NDPA_BW_8822B) - - +#define BIT_R_NDPA_BW_8822B(x) \ + (((x) & BIT_MASK_R_NDPA_BW_8822B) << BIT_SHIFT_R_NDPA_BW_8822B) +#define BITS_R_NDPA_BW_8822B \ + (BIT_MASK_R_NDPA_BW_8822B << BIT_SHIFT_R_NDPA_BW_8822B) +#define BIT_CLEAR_R_NDPA_BW_8822B(x) ((x) & (~BITS_R_NDPA_BW_8822B)) +#define BIT_GET_R_NDPA_BW_8822B(x) \ + (((x) >> BIT_SHIFT_R_NDPA_BW_8822B) & BIT_MASK_R_NDPA_BW_8822B) +#define BIT_SET_R_NDPA_BW_8822B(x, v) \ + (BIT_CLEAR_R_NDPA_BW_8822B(x) | BIT_R_NDPA_BW_8822B(v)) /* 2 REG_RD_RESP_PKT_TH_8822B */ #define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B 0 #define BIT_MASK_RD_RESP_PKT_TH_V1_8822B 0x3f -#define BIT_RD_RESP_PKT_TH_V1_8822B(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) -#define BIT_GET_RD_RESP_PKT_TH_V1_8822B(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B) - - +#define BIT_RD_RESP_PKT_TH_V1_8822B(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B) \ + << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) +#define BITS_RD_RESP_PKT_TH_V1_8822B \ + (BIT_MASK_RD_RESP_PKT_TH_V1_8822B << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8822B(x) \ + ((x) & (~BITS_RD_RESP_PKT_TH_V1_8822B)) +#define BIT_GET_RD_RESP_PKT_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) & \ + BIT_MASK_RD_RESP_PKT_TH_V1_8822B) +#define BIT_SET_RD_RESP_PKT_TH_V1_8822B(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1_8822B(x) | BIT_RD_RESP_PKT_TH_V1_8822B(v)) /* 2 REG_CMDQ_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B 25 #define BIT_MASK_QUEUEMACID_CMDQ_V1_8822B 0x7f -#define BIT_QUEUEMACID_CMDQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) -#define BIT_GET_QUEUEMACID_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) - - +#define BIT_QUEUEMACID_CMDQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) +#define BITS_QUEUEMACID_CMDQ_V1_8822B \ + (BIT_MASK_QUEUEMACID_CMDQ_V1_8822B \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_CMDQ_V1_8822B)) +#define BIT_GET_QUEUEMACID_CMDQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) & \ + BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) +#define BIT_SET_QUEUEMACID_CMDQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822B(x) | \ + BIT_QUEUEMACID_CMDQ_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B 23 #define BIT_MASK_QUEUEAC_CMDQ_V1_8822B 0x3 -#define BIT_QUEUEAC_CMDQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) -#define BIT_GET_QUEUEAC_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B) - +#define BIT_QUEUEAC_CMDQ_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B) \ + << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) +#define BITS_QUEUEAC_CMDQ_V1_8822B \ + (BIT_MASK_QUEUEAC_CMDQ_V1_8822B << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) +#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8822B)) +#define BIT_GET_QUEUEAC_CMDQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) & \ + BIT_MASK_QUEUEAC_CMDQ_V1_8822B) +#define BIT_SET_QUEUEAC_CMDQ_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_CMDQ_V1_8822B(x) | BIT_QUEUEAC_CMDQ_V1_8822B(v)) #define BIT_TIDEMPTY_CMDQ_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B 11 #define BIT_MASK_TAIL_PKT_CMDQ_V2_8822B 0x7ff -#define BIT_TAIL_PKT_CMDQ_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) -#define BIT_GET_TAIL_PKT_CMDQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) - - +#define BIT_TAIL_PKT_CMDQ_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) +#define BITS_TAIL_PKT_CMDQ_V2_8822B \ + (BIT_MASK_TAIL_PKT_CMDQ_V2_8822B << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8822B(x) \ + ((x) & (~BITS_TAIL_PKT_CMDQ_V2_8822B)) +#define BIT_GET_TAIL_PKT_CMDQ_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) & \ + BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) +#define BIT_SET_TAIL_PKT_CMDQ_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_CMDQ_V2_8822B(x) | BIT_TAIL_PKT_CMDQ_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B 0 #define BIT_MASK_HEAD_PKT_CMDQ_V1_8822B 0x7ff -#define BIT_HEAD_PKT_CMDQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) -#define BIT_GET_HEAD_PKT_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) - - +#define BIT_HEAD_PKT_CMDQ_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) +#define BITS_HEAD_PKT_CMDQ_V1_8822B \ + (BIT_MASK_HEAD_PKT_CMDQ_V1_8822B << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822B(x) \ + ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8822B)) +#define BIT_GET_HEAD_PKT_CMDQ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) & \ + BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) +#define BIT_SET_HEAD_PKT_CMDQ_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822B(x) | BIT_HEAD_PKT_CMDQ_V1_8822B(v)) /* 2 REG_Q4_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q4_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q4_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q4_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) -#define BIT_GET_QUEUEMACID_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) & BIT_MASK_QUEUEMACID_Q4_V1_8822B) - - +#define BIT_QUEUEMACID_Q4_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) +#define BITS_QUEUEMACID_Q4_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q4_V1_8822B << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q4_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q4_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q4_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q4_V1_8822B) +#define BIT_SET_QUEUEMACID_Q4_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q4_V1_8822B(x) | BIT_QUEUEMACID_Q4_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q4_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q4_V1_8822B 0x3 -#define BIT_QUEUEAC_Q4_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8822B) << BIT_SHIFT_QUEUEAC_Q4_V1_8822B) -#define BIT_GET_QUEUEAC_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822B) & BIT_MASK_QUEUEAC_Q4_V1_8822B) - +#define BIT_QUEUEAC_Q4_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q4_V1_8822B) << BIT_SHIFT_QUEUEAC_Q4_V1_8822B) +#define BITS_QUEUEAC_Q4_V1_8822B \ + (BIT_MASK_QUEUEAC_Q4_V1_8822B << BIT_SHIFT_QUEUEAC_Q4_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q4_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8822B)) +#define BIT_GET_QUEUEAC_Q4_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822B) & BIT_MASK_QUEUEAC_Q4_V1_8822B) +#define BIT_SET_QUEUEAC_Q4_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q4_V1_8822B(x) | BIT_QUEUEAC_Q4_V1_8822B(v)) #define BIT_TIDEMPTY_Q4_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q4_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q4_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q4_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) -#define BIT_GET_TAIL_PKT_Q4_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) & BIT_MASK_TAIL_PKT_Q4_V2_8822B) - - +#define BIT_TAIL_PKT_Q4_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) +#define BITS_TAIL_PKT_Q4_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q4_V2_8822B << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q4_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8822B) +#define BIT_SET_TAIL_PKT_Q4_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8822B(x) | BIT_TAIL_PKT_Q4_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q4_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q4_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q4_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) -#define BIT_GET_HEAD_PKT_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) & BIT_MASK_HEAD_PKT_Q4_V1_8822B) - - +#define BIT_HEAD_PKT_Q4_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) +#define BITS_HEAD_PKT_Q4_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q4_V1_8822B << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q4_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q4_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q4_V1_8822B) +#define BIT_SET_HEAD_PKT_Q4_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4_V1_8822B(x) | BIT_HEAD_PKT_Q4_V1_8822B(v)) /* 2 REG_Q5_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q5_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q5_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q5_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) -#define BIT_GET_QUEUEMACID_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) & BIT_MASK_QUEUEMACID_Q5_V1_8822B) - - +#define BIT_QUEUEMACID_Q5_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) +#define BITS_QUEUEMACID_Q5_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q5_V1_8822B << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q5_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q5_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q5_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q5_V1_8822B) +#define BIT_SET_QUEUEMACID_Q5_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q5_V1_8822B(x) | BIT_QUEUEMACID_Q5_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q5_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q5_V1_8822B 0x3 -#define BIT_QUEUEAC_Q5_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8822B) << BIT_SHIFT_QUEUEAC_Q5_V1_8822B) -#define BIT_GET_QUEUEAC_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822B) & BIT_MASK_QUEUEAC_Q5_V1_8822B) - +#define BIT_QUEUEAC_Q5_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q5_V1_8822B) << BIT_SHIFT_QUEUEAC_Q5_V1_8822B) +#define BITS_QUEUEAC_Q5_V1_8822B \ + (BIT_MASK_QUEUEAC_Q5_V1_8822B << BIT_SHIFT_QUEUEAC_Q5_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q5_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8822B)) +#define BIT_GET_QUEUEAC_Q5_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822B) & BIT_MASK_QUEUEAC_Q5_V1_8822B) +#define BIT_SET_QUEUEAC_Q5_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q5_V1_8822B(x) | BIT_QUEUEAC_Q5_V1_8822B(v)) #define BIT_TIDEMPTY_Q5_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q5_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q5_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q5_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) -#define BIT_GET_TAIL_PKT_Q5_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) & BIT_MASK_TAIL_PKT_Q5_V2_8822B) - - +#define BIT_TAIL_PKT_Q5_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) +#define BITS_TAIL_PKT_Q5_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q5_V2_8822B << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q5_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q5_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q5_V2_8822B) +#define BIT_SET_TAIL_PKT_Q5_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V2_8822B(x) | BIT_TAIL_PKT_Q5_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q5_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q5_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q5_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) -#define BIT_GET_HEAD_PKT_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) & BIT_MASK_HEAD_PKT_Q5_V1_8822B) - - +#define BIT_HEAD_PKT_Q5_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) +#define BITS_HEAD_PKT_Q5_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q5_V1_8822B << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q5_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q5_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q5_V1_8822B) +#define BIT_SET_HEAD_PKT_Q5_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5_V1_8822B(x) | BIT_HEAD_PKT_Q5_V1_8822B(v)) /* 2 REG_Q6_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q6_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q6_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q6_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) -#define BIT_GET_QUEUEMACID_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) & BIT_MASK_QUEUEMACID_Q6_V1_8822B) - - +#define BIT_QUEUEMACID_Q6_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) +#define BITS_QUEUEMACID_Q6_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q6_V1_8822B << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q6_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q6_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q6_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q6_V1_8822B) +#define BIT_SET_QUEUEMACID_Q6_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q6_V1_8822B(x) | BIT_QUEUEMACID_Q6_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q6_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q6_V1_8822B 0x3 -#define BIT_QUEUEAC_Q6_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8822B) << BIT_SHIFT_QUEUEAC_Q6_V1_8822B) -#define BIT_GET_QUEUEAC_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822B) & BIT_MASK_QUEUEAC_Q6_V1_8822B) - +#define BIT_QUEUEAC_Q6_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q6_V1_8822B) << BIT_SHIFT_QUEUEAC_Q6_V1_8822B) +#define BITS_QUEUEAC_Q6_V1_8822B \ + (BIT_MASK_QUEUEAC_Q6_V1_8822B << BIT_SHIFT_QUEUEAC_Q6_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q6_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8822B)) +#define BIT_GET_QUEUEAC_Q6_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822B) & BIT_MASK_QUEUEAC_Q6_V1_8822B) +#define BIT_SET_QUEUEAC_Q6_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q6_V1_8822B(x) | BIT_QUEUEAC_Q6_V1_8822B(v)) #define BIT_TIDEMPTY_Q6_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q6_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q6_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q6_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) -#define BIT_GET_TAIL_PKT_Q6_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) & BIT_MASK_TAIL_PKT_Q6_V2_8822B) - - +#define BIT_TAIL_PKT_Q6_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) +#define BITS_TAIL_PKT_Q6_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q6_V2_8822B << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q6_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q6_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q6_V2_8822B) +#define BIT_SET_TAIL_PKT_Q6_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V2_8822B(x) | BIT_TAIL_PKT_Q6_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q6_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q6_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q6_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) -#define BIT_GET_HEAD_PKT_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) & BIT_MASK_HEAD_PKT_Q6_V1_8822B) - - +#define BIT_HEAD_PKT_Q6_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) +#define BITS_HEAD_PKT_Q6_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q6_V1_8822B << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q6_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q6_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q6_V1_8822B) +#define BIT_SET_HEAD_PKT_Q6_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6_V1_8822B(x) | BIT_HEAD_PKT_Q6_V1_8822B(v)) /* 2 REG_Q7_INFO_8822B */ #define BIT_SHIFT_QUEUEMACID_Q7_V1_8822B 25 #define BIT_MASK_QUEUEMACID_Q7_V1_8822B 0x7f -#define BIT_QUEUEMACID_Q7_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) -#define BIT_GET_QUEUEMACID_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) & BIT_MASK_QUEUEMACID_Q7_V1_8822B) - - +#define BIT_QUEUEMACID_Q7_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822B) \ + << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) +#define BITS_QUEUEMACID_Q7_V1_8822B \ + (BIT_MASK_QUEUEMACID_Q7_V1_8822B << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) +#define BIT_CLEAR_QUEUEMACID_Q7_V1_8822B(x) \ + ((x) & (~BITS_QUEUEMACID_Q7_V1_8822B)) +#define BIT_GET_QUEUEMACID_Q7_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) & \ + BIT_MASK_QUEUEMACID_Q7_V1_8822B) +#define BIT_SET_QUEUEMACID_Q7_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q7_V1_8822B(x) | BIT_QUEUEMACID_Q7_V1_8822B(v)) #define BIT_SHIFT_QUEUEAC_Q7_V1_8822B 23 #define BIT_MASK_QUEUEAC_Q7_V1_8822B 0x3 -#define BIT_QUEUEAC_Q7_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8822B) << BIT_SHIFT_QUEUEAC_Q7_V1_8822B) -#define BIT_GET_QUEUEAC_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822B) & BIT_MASK_QUEUEAC_Q7_V1_8822B) - +#define BIT_QUEUEAC_Q7_V1_8822B(x) \ + (((x) & BIT_MASK_QUEUEAC_Q7_V1_8822B) << BIT_SHIFT_QUEUEAC_Q7_V1_8822B) +#define BITS_QUEUEAC_Q7_V1_8822B \ + (BIT_MASK_QUEUEAC_Q7_V1_8822B << BIT_SHIFT_QUEUEAC_Q7_V1_8822B) +#define BIT_CLEAR_QUEUEAC_Q7_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8822B)) +#define BIT_GET_QUEUEAC_Q7_V1_8822B(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822B) & BIT_MASK_QUEUEAC_Q7_V1_8822B) +#define BIT_SET_QUEUEAC_Q7_V1_8822B(x, v) \ + (BIT_CLEAR_QUEUEAC_Q7_V1_8822B(x) | BIT_QUEUEAC_Q7_V1_8822B(v)) #define BIT_TIDEMPTY_Q7_V1_8822B BIT(22) #define BIT_SHIFT_TAIL_PKT_Q7_V2_8822B 11 #define BIT_MASK_TAIL_PKT_Q7_V2_8822B 0x7ff -#define BIT_TAIL_PKT_Q7_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) -#define BIT_GET_TAIL_PKT_Q7_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) & BIT_MASK_TAIL_PKT_Q7_V2_8822B) - - +#define BIT_TAIL_PKT_Q7_V2_8822B(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822B) \ + << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) +#define BITS_TAIL_PKT_Q7_V2_8822B \ + (BIT_MASK_TAIL_PKT_Q7_V2_8822B << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) +#define BIT_CLEAR_TAIL_PKT_Q7_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8822B)) +#define BIT_GET_TAIL_PKT_Q7_V2_8822B(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) & \ + BIT_MASK_TAIL_PKT_Q7_V2_8822B) +#define BIT_SET_TAIL_PKT_Q7_V2_8822B(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V2_8822B(x) | BIT_TAIL_PKT_Q7_V2_8822B(v)) #define BIT_SHIFT_HEAD_PKT_Q7_V1_8822B 0 #define BIT_MASK_HEAD_PKT_Q7_V1_8822B 0x7ff -#define BIT_HEAD_PKT_Q7_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) -#define BIT_GET_HEAD_PKT_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) & BIT_MASK_HEAD_PKT_Q7_V1_8822B) - - +#define BIT_HEAD_PKT_Q7_V1_8822B(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822B) \ + << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) +#define BITS_HEAD_PKT_Q7_V1_8822B \ + (BIT_MASK_HEAD_PKT_Q7_V1_8822B << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) +#define BIT_CLEAR_HEAD_PKT_Q7_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8822B)) +#define BIT_GET_HEAD_PKT_Q7_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) & \ + BIT_MASK_HEAD_PKT_Q7_V1_8822B) +#define BIT_SET_HEAD_PKT_Q7_V1_8822B(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7_V1_8822B(x) | BIT_HEAD_PKT_Q7_V1_8822B(v)) /* 2 REG_WMAC_LBK_BUF_HD_V1_8822B */ #define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B 0 #define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B 0xfff -#define BIT_WMAC_LBK_BUF_HEAD_V1_8822B(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) -#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822B(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) - - +#define BIT_WMAC_LBK_BUF_HEAD_V1_8822B(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) +#define BITS_WMAC_LBK_BUF_HEAD_V1_8822B \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822B(x) \ + ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8822B)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8822B(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822B(x) | \ + BIT_WMAC_LBK_BUF_HEAD_V1_8822B(v)) /* 2 REG_MGQ_BDNY_V1_8822B */ #define BIT_SHIFT_MGQ_PGBNDY_V1_8822B 0 #define BIT_MASK_MGQ_PGBNDY_V1_8822B 0xfff -#define BIT_MGQ_PGBNDY_V1_8822B(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8822B) << BIT_SHIFT_MGQ_PGBNDY_V1_8822B) -#define BIT_GET_MGQ_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822B) & BIT_MASK_MGQ_PGBNDY_V1_8822B) - - +#define BIT_MGQ_PGBNDY_V1_8822B(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1_8822B) << BIT_SHIFT_MGQ_PGBNDY_V1_8822B) +#define BITS_MGQ_PGBNDY_V1_8822B \ + (BIT_MASK_MGQ_PGBNDY_V1_8822B << BIT_SHIFT_MGQ_PGBNDY_V1_8822B) +#define BIT_CLEAR_MGQ_PGBNDY_V1_8822B(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8822B)) +#define BIT_GET_MGQ_PGBNDY_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822B) & BIT_MASK_MGQ_PGBNDY_V1_8822B) +#define BIT_SET_MGQ_PGBNDY_V1_8822B(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1_8822B(x) | BIT_MGQ_PGBNDY_V1_8822B(v)) /* 2 REG_TXRPT_CTRL_8822B */ #define BIT_SHIFT_TRXRPT_TIMER_TH_8822B 24 #define BIT_MASK_TRXRPT_TIMER_TH_8822B 0xff -#define BIT_TRXRPT_TIMER_TH_8822B(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8822B) << BIT_SHIFT_TRXRPT_TIMER_TH_8822B) -#define BIT_GET_TRXRPT_TIMER_TH_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822B) & BIT_MASK_TRXRPT_TIMER_TH_8822B) - - +#define BIT_TRXRPT_TIMER_TH_8822B(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH_8822B) \ + << BIT_SHIFT_TRXRPT_TIMER_TH_8822B) +#define BITS_TRXRPT_TIMER_TH_8822B \ + (BIT_MASK_TRXRPT_TIMER_TH_8822B << BIT_SHIFT_TRXRPT_TIMER_TH_8822B) +#define BIT_CLEAR_TRXRPT_TIMER_TH_8822B(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8822B)) +#define BIT_GET_TRXRPT_TIMER_TH_8822B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822B) & \ + BIT_MASK_TRXRPT_TIMER_TH_8822B) +#define BIT_SET_TRXRPT_TIMER_TH_8822B(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH_8822B(x) | BIT_TRXRPT_TIMER_TH_8822B(v)) #define BIT_SHIFT_TRXRPT_LEN_TH_8822B 16 #define BIT_MASK_TRXRPT_LEN_TH_8822B 0xff -#define BIT_TRXRPT_LEN_TH_8822B(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8822B) << BIT_SHIFT_TRXRPT_LEN_TH_8822B) -#define BIT_GET_TRXRPT_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822B) & BIT_MASK_TRXRPT_LEN_TH_8822B) - - +#define BIT_TRXRPT_LEN_TH_8822B(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH_8822B) << BIT_SHIFT_TRXRPT_LEN_TH_8822B) +#define BITS_TRXRPT_LEN_TH_8822B \ + (BIT_MASK_TRXRPT_LEN_TH_8822B << BIT_SHIFT_TRXRPT_LEN_TH_8822B) +#define BIT_CLEAR_TRXRPT_LEN_TH_8822B(x) ((x) & (~BITS_TRXRPT_LEN_TH_8822B)) +#define BIT_GET_TRXRPT_LEN_TH_8822B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822B) & BIT_MASK_TRXRPT_LEN_TH_8822B) +#define BIT_SET_TRXRPT_LEN_TH_8822B(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH_8822B(x) | BIT_TRXRPT_LEN_TH_8822B(v)) #define BIT_SHIFT_TRXRPT_READ_PTR_8822B 8 #define BIT_MASK_TRXRPT_READ_PTR_8822B 0xff -#define BIT_TRXRPT_READ_PTR_8822B(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8822B) << BIT_SHIFT_TRXRPT_READ_PTR_8822B) -#define BIT_GET_TRXRPT_READ_PTR_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822B) & BIT_MASK_TRXRPT_READ_PTR_8822B) - - +#define BIT_TRXRPT_READ_PTR_8822B(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR_8822B) \ + << BIT_SHIFT_TRXRPT_READ_PTR_8822B) +#define BITS_TRXRPT_READ_PTR_8822B \ + (BIT_MASK_TRXRPT_READ_PTR_8822B << BIT_SHIFT_TRXRPT_READ_PTR_8822B) +#define BIT_CLEAR_TRXRPT_READ_PTR_8822B(x) ((x) & (~BITS_TRXRPT_READ_PTR_8822B)) +#define BIT_GET_TRXRPT_READ_PTR_8822B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822B) & \ + BIT_MASK_TRXRPT_READ_PTR_8822B) +#define BIT_SET_TRXRPT_READ_PTR_8822B(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR_8822B(x) | BIT_TRXRPT_READ_PTR_8822B(v)) #define BIT_SHIFT_TRXRPT_WRITE_PTR_8822B 0 #define BIT_MASK_TRXRPT_WRITE_PTR_8822B 0xff -#define BIT_TRXRPT_WRITE_PTR_8822B(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822B) << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) -#define BIT_GET_TRXRPT_WRITE_PTR_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) & BIT_MASK_TRXRPT_WRITE_PTR_8822B) - - +#define BIT_TRXRPT_WRITE_PTR_8822B(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822B) \ + << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) +#define BITS_TRXRPT_WRITE_PTR_8822B \ + (BIT_MASK_TRXRPT_WRITE_PTR_8822B << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) +#define BIT_CLEAR_TRXRPT_WRITE_PTR_8822B(x) \ + ((x) & (~BITS_TRXRPT_WRITE_PTR_8822B)) +#define BIT_GET_TRXRPT_WRITE_PTR_8822B(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) & \ + BIT_MASK_TRXRPT_WRITE_PTR_8822B) +#define BIT_SET_TRXRPT_WRITE_PTR_8822B(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR_8822B(x) | BIT_TRXRPT_WRITE_PTR_8822B(v)) /* 2 REG_INIRTS_RATE_SEL_8822B */ #define BIT_LEAG_RTS_BW_DUP_8822B BIT(5) @@ -5974,113 +9184,205 @@ #define BIT_SHIFT_BASIC_CFEND_RATE_8822B 0 #define BIT_MASK_BASIC_CFEND_RATE_8822B 0x1f -#define BIT_BASIC_CFEND_RATE_8822B(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8822B) << BIT_SHIFT_BASIC_CFEND_RATE_8822B) -#define BIT_GET_BASIC_CFEND_RATE_8822B(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822B) & BIT_MASK_BASIC_CFEND_RATE_8822B) - - +#define BIT_BASIC_CFEND_RATE_8822B(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE_8822B) \ + << BIT_SHIFT_BASIC_CFEND_RATE_8822B) +#define BITS_BASIC_CFEND_RATE_8822B \ + (BIT_MASK_BASIC_CFEND_RATE_8822B << BIT_SHIFT_BASIC_CFEND_RATE_8822B) +#define BIT_CLEAR_BASIC_CFEND_RATE_8822B(x) \ + ((x) & (~BITS_BASIC_CFEND_RATE_8822B)) +#define BIT_GET_BASIC_CFEND_RATE_8822B(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822B) & \ + BIT_MASK_BASIC_CFEND_RATE_8822B) +#define BIT_SET_BASIC_CFEND_RATE_8822B(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE_8822B(x) | BIT_BASIC_CFEND_RATE_8822B(v)) /* 2 REG_STBC_CFEND_RATE_8822B */ #define BIT_SHIFT_STBC_CFEND_RATE_8822B 0 #define BIT_MASK_STBC_CFEND_RATE_8822B 0x1f -#define BIT_STBC_CFEND_RATE_8822B(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8822B) << BIT_SHIFT_STBC_CFEND_RATE_8822B) -#define BIT_GET_STBC_CFEND_RATE_8822B(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822B) & BIT_MASK_STBC_CFEND_RATE_8822B) - - +#define BIT_STBC_CFEND_RATE_8822B(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE_8822B) \ + << BIT_SHIFT_STBC_CFEND_RATE_8822B) +#define BITS_STBC_CFEND_RATE_8822B \ + (BIT_MASK_STBC_CFEND_RATE_8822B << BIT_SHIFT_STBC_CFEND_RATE_8822B) +#define BIT_CLEAR_STBC_CFEND_RATE_8822B(x) ((x) & (~BITS_STBC_CFEND_RATE_8822B)) +#define BIT_GET_STBC_CFEND_RATE_8822B(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822B) & \ + BIT_MASK_STBC_CFEND_RATE_8822B) +#define BIT_SET_STBC_CFEND_RATE_8822B(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE_8822B(x) | BIT_STBC_CFEND_RATE_8822B(v)) /* 2 REG_DATA_SC_8822B */ #define BIT_SHIFT_TXSC_40M_8822B 4 #define BIT_MASK_TXSC_40M_8822B 0xf -#define BIT_TXSC_40M_8822B(x) (((x) & BIT_MASK_TXSC_40M_8822B) << BIT_SHIFT_TXSC_40M_8822B) -#define BIT_GET_TXSC_40M_8822B(x) (((x) >> BIT_SHIFT_TXSC_40M_8822B) & BIT_MASK_TXSC_40M_8822B) - - +#define BIT_TXSC_40M_8822B(x) \ + (((x) & BIT_MASK_TXSC_40M_8822B) << BIT_SHIFT_TXSC_40M_8822B) +#define BITS_TXSC_40M_8822B \ + (BIT_MASK_TXSC_40M_8822B << BIT_SHIFT_TXSC_40M_8822B) +#define BIT_CLEAR_TXSC_40M_8822B(x) ((x) & (~BITS_TXSC_40M_8822B)) +#define BIT_GET_TXSC_40M_8822B(x) \ + (((x) >> BIT_SHIFT_TXSC_40M_8822B) & BIT_MASK_TXSC_40M_8822B) +#define BIT_SET_TXSC_40M_8822B(x, v) \ + (BIT_CLEAR_TXSC_40M_8822B(x) | BIT_TXSC_40M_8822B(v)) #define BIT_SHIFT_TXSC_20M_8822B 0 #define BIT_MASK_TXSC_20M_8822B 0xf -#define BIT_TXSC_20M_8822B(x) (((x) & BIT_MASK_TXSC_20M_8822B) << BIT_SHIFT_TXSC_20M_8822B) -#define BIT_GET_TXSC_20M_8822B(x) (((x) >> BIT_SHIFT_TXSC_20M_8822B) & BIT_MASK_TXSC_20M_8822B) - - +#define BIT_TXSC_20M_8822B(x) \ + (((x) & BIT_MASK_TXSC_20M_8822B) << BIT_SHIFT_TXSC_20M_8822B) +#define BITS_TXSC_20M_8822B \ + (BIT_MASK_TXSC_20M_8822B << BIT_SHIFT_TXSC_20M_8822B) +#define BIT_CLEAR_TXSC_20M_8822B(x) ((x) & (~BITS_TXSC_20M_8822B)) +#define BIT_GET_TXSC_20M_8822B(x) \ + (((x) >> BIT_SHIFT_TXSC_20M_8822B) & BIT_MASK_TXSC_20M_8822B) +#define BIT_SET_TXSC_20M_8822B(x, v) \ + (BIT_CLEAR_TXSC_20M_8822B(x) | BIT_TXSC_20M_8822B(v)) /* 2 REG_MACID_SLEEP3_8822B */ #define BIT_SHIFT_MACID127_96_PKTSLEEP_8822B 0 #define BIT_MASK_MACID127_96_PKTSLEEP_8822B 0xffffffffL -#define BIT_MACID127_96_PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822B) << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) -#define BIT_GET_MACID127_96_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) & BIT_MASK_MACID127_96_PKTSLEEP_8822B) - - +#define BIT_MACID127_96_PKTSLEEP_8822B(x) \ + (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822B) \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) +#define BITS_MACID127_96_PKTSLEEP_8822B \ + (BIT_MASK_MACID127_96_PKTSLEEP_8822B \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) +#define BIT_CLEAR_MACID127_96_PKTSLEEP_8822B(x) \ + ((x) & (~BITS_MACID127_96_PKTSLEEP_8822B)) +#define BIT_GET_MACID127_96_PKTSLEEP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) & \ + BIT_MASK_MACID127_96_PKTSLEEP_8822B) +#define BIT_SET_MACID127_96_PKTSLEEP_8822B(x, v) \ + (BIT_CLEAR_MACID127_96_PKTSLEEP_8822B(x) | \ + BIT_MACID127_96_PKTSLEEP_8822B(v)) /* 2 REG_MACID_SLEEP1_8822B */ #define BIT_SHIFT_MACID63_32_PKTSLEEP_8822B 0 #define BIT_MASK_MACID63_32_PKTSLEEP_8822B 0xffffffffL -#define BIT_MACID63_32_PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822B) << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) -#define BIT_GET_MACID63_32_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) & BIT_MASK_MACID63_32_PKTSLEEP_8822B) - - +#define BIT_MACID63_32_PKTSLEEP_8822B(x) \ + (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822B) \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) +#define BITS_MACID63_32_PKTSLEEP_8822B \ + (BIT_MASK_MACID63_32_PKTSLEEP_8822B \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) +#define BIT_CLEAR_MACID63_32_PKTSLEEP_8822B(x) \ + ((x) & (~BITS_MACID63_32_PKTSLEEP_8822B)) +#define BIT_GET_MACID63_32_PKTSLEEP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) & \ + BIT_MASK_MACID63_32_PKTSLEEP_8822B) +#define BIT_SET_MACID63_32_PKTSLEEP_8822B(x, v) \ + (BIT_CLEAR_MACID63_32_PKTSLEEP_8822B(x) | \ + BIT_MACID63_32_PKTSLEEP_8822B(v)) /* 2 REG_ARFR2_V1_8822B */ #define BIT_SHIFT_ARFR2_V1_8822B 0 #define BIT_MASK_ARFR2_V1_8822B 0xffffffffffffffffL -#define BIT_ARFR2_V1_8822B(x) (((x) & BIT_MASK_ARFR2_V1_8822B) << BIT_SHIFT_ARFR2_V1_8822B) -#define BIT_GET_ARFR2_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR2_V1_8822B) & BIT_MASK_ARFR2_V1_8822B) - - +#define BIT_ARFR2_V1_8822B(x) \ + (((x) & BIT_MASK_ARFR2_V1_8822B) << BIT_SHIFT_ARFR2_V1_8822B) +#define BITS_ARFR2_V1_8822B \ + (BIT_MASK_ARFR2_V1_8822B << BIT_SHIFT_ARFR2_V1_8822B) +#define BIT_CLEAR_ARFR2_V1_8822B(x) ((x) & (~BITS_ARFR2_V1_8822B)) +#define BIT_GET_ARFR2_V1_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR2_V1_8822B) & BIT_MASK_ARFR2_V1_8822B) +#define BIT_SET_ARFR2_V1_8822B(x, v) \ + (BIT_CLEAR_ARFR2_V1_8822B(x) | BIT_ARFR2_V1_8822B(v)) /* 2 REG_ARFR3_V1_8822B */ #define BIT_SHIFT_ARFR3_V1_8822B 0 #define BIT_MASK_ARFR3_V1_8822B 0xffffffffffffffffL -#define BIT_ARFR3_V1_8822B(x) (((x) & BIT_MASK_ARFR3_V1_8822B) << BIT_SHIFT_ARFR3_V1_8822B) -#define BIT_GET_ARFR3_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR3_V1_8822B) & BIT_MASK_ARFR3_V1_8822B) - - +#define BIT_ARFR3_V1_8822B(x) \ + (((x) & BIT_MASK_ARFR3_V1_8822B) << BIT_SHIFT_ARFR3_V1_8822B) +#define BITS_ARFR3_V1_8822B \ + (BIT_MASK_ARFR3_V1_8822B << BIT_SHIFT_ARFR3_V1_8822B) +#define BIT_CLEAR_ARFR3_V1_8822B(x) ((x) & (~BITS_ARFR3_V1_8822B)) +#define BIT_GET_ARFR3_V1_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR3_V1_8822B) & BIT_MASK_ARFR3_V1_8822B) +#define BIT_SET_ARFR3_V1_8822B(x, v) \ + (BIT_CLEAR_ARFR3_V1_8822B(x) | BIT_ARFR3_V1_8822B(v)) /* 2 REG_ARFR4_8822B */ #define BIT_SHIFT_ARFR4_8822B 0 #define BIT_MASK_ARFR4_8822B 0xffffffffffffffffL -#define BIT_ARFR4_8822B(x) (((x) & BIT_MASK_ARFR4_8822B) << BIT_SHIFT_ARFR4_8822B) -#define BIT_GET_ARFR4_8822B(x) (((x) >> BIT_SHIFT_ARFR4_8822B) & BIT_MASK_ARFR4_8822B) - - +#define BIT_ARFR4_8822B(x) \ + (((x) & BIT_MASK_ARFR4_8822B) << BIT_SHIFT_ARFR4_8822B) +#define BITS_ARFR4_8822B (BIT_MASK_ARFR4_8822B << BIT_SHIFT_ARFR4_8822B) +#define BIT_CLEAR_ARFR4_8822B(x) ((x) & (~BITS_ARFR4_8822B)) +#define BIT_GET_ARFR4_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR4_8822B) & BIT_MASK_ARFR4_8822B) +#define BIT_SET_ARFR4_8822B(x, v) \ + (BIT_CLEAR_ARFR4_8822B(x) | BIT_ARFR4_8822B(v)) /* 2 REG_ARFR5_8822B */ #define BIT_SHIFT_ARFR5_8822B 0 #define BIT_MASK_ARFR5_8822B 0xffffffffffffffffL -#define BIT_ARFR5_8822B(x) (((x) & BIT_MASK_ARFR5_8822B) << BIT_SHIFT_ARFR5_8822B) -#define BIT_GET_ARFR5_8822B(x) (((x) >> BIT_SHIFT_ARFR5_8822B) & BIT_MASK_ARFR5_8822B) - - +#define BIT_ARFR5_8822B(x) \ + (((x) & BIT_MASK_ARFR5_8822B) << BIT_SHIFT_ARFR5_8822B) +#define BITS_ARFR5_8822B (BIT_MASK_ARFR5_8822B << BIT_SHIFT_ARFR5_8822B) +#define BIT_CLEAR_ARFR5_8822B(x) ((x) & (~BITS_ARFR5_8822B)) +#define BIT_GET_ARFR5_8822B(x) \ + (((x) >> BIT_SHIFT_ARFR5_8822B) & BIT_MASK_ARFR5_8822B) +#define BIT_SET_ARFR5_8822B(x, v) \ + (BIT_CLEAR_ARFR5_8822B(x) | BIT_ARFR5_8822B(v)) /* 2 REG_TXRPT_START_OFFSET_8822B */ #define BIT_SHIFT_MACID_MURATE_OFFSET_8822B 24 #define BIT_MASK_MACID_MURATE_OFFSET_8822B 0xff -#define BIT_MACID_MURATE_OFFSET_8822B(x) (((x) & BIT_MASK_MACID_MURATE_OFFSET_8822B) << BIT_SHIFT_MACID_MURATE_OFFSET_8822B) -#define BIT_GET_MACID_MURATE_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822B) & BIT_MASK_MACID_MURATE_OFFSET_8822B) - +#define BIT_MACID_MURATE_OFFSET_8822B(x) \ + (((x) & BIT_MASK_MACID_MURATE_OFFSET_8822B) \ + << BIT_SHIFT_MACID_MURATE_OFFSET_8822B) +#define BITS_MACID_MURATE_OFFSET_8822B \ + (BIT_MASK_MACID_MURATE_OFFSET_8822B \ + << BIT_SHIFT_MACID_MURATE_OFFSET_8822B) +#define BIT_CLEAR_MACID_MURATE_OFFSET_8822B(x) \ + ((x) & (~BITS_MACID_MURATE_OFFSET_8822B)) +#define BIT_GET_MACID_MURATE_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822B) & \ + BIT_MASK_MACID_MURATE_OFFSET_8822B) +#define BIT_SET_MACID_MURATE_OFFSET_8822B(x, v) \ + (BIT_CLEAR_MACID_MURATE_OFFSET_8822B(x) | \ + BIT_MACID_MURATE_OFFSET_8822B(v)) #define BIT_RPTFIFO_SIZE_OPT_8822B BIT(16) #define BIT_SHIFT_MACID_CTRL_OFFSET_8822B 8 #define BIT_MASK_MACID_CTRL_OFFSET_8822B 0xff -#define BIT_MACID_CTRL_OFFSET_8822B(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8822B) << BIT_SHIFT_MACID_CTRL_OFFSET_8822B) -#define BIT_GET_MACID_CTRL_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822B) & BIT_MASK_MACID_CTRL_OFFSET_8822B) - - +#define BIT_MACID_CTRL_OFFSET_8822B(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_8822B) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_8822B) +#define BITS_MACID_CTRL_OFFSET_8822B \ + (BIT_MASK_MACID_CTRL_OFFSET_8822B << BIT_SHIFT_MACID_CTRL_OFFSET_8822B) +#define BIT_CLEAR_MACID_CTRL_OFFSET_8822B(x) \ + ((x) & (~BITS_MACID_CTRL_OFFSET_8822B)) +#define BIT_GET_MACID_CTRL_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822B) & \ + BIT_MASK_MACID_CTRL_OFFSET_8822B) +#define BIT_SET_MACID_CTRL_OFFSET_8822B(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_8822B(x) | BIT_MACID_CTRL_OFFSET_8822B(v)) #define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B 0 #define BIT_MASK_AMPDU_TXRPT_OFFSET_8822B 0xff -#define BIT_AMPDU_TXRPT_OFFSET_8822B(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) -#define BIT_GET_AMPDU_TXRPT_OFFSET_8822B(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) - - +#define BIT_AMPDU_TXRPT_OFFSET_8822B(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) +#define BITS_AMPDU_TXRPT_OFFSET_8822B \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_8822B \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822B(x) \ + ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8822B)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) +#define BIT_SET_AMPDU_TXRPT_OFFSET_8822B(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822B(x) | \ + BIT_AMPDU_TXRPT_OFFSET_8822B(v)) /* 2 REG_POWER_STAGE1_8822B */ #define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822B BIT(31) @@ -6094,28 +9396,44 @@ #define BIT_SHIFT_POWER_STAGE1_8822B 0 #define BIT_MASK_POWER_STAGE1_8822B 0xffffff -#define BIT_POWER_STAGE1_8822B(x) (((x) & BIT_MASK_POWER_STAGE1_8822B) << BIT_SHIFT_POWER_STAGE1_8822B) -#define BIT_GET_POWER_STAGE1_8822B(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8822B) & BIT_MASK_POWER_STAGE1_8822B) - - +#define BIT_POWER_STAGE1_8822B(x) \ + (((x) & BIT_MASK_POWER_STAGE1_8822B) << BIT_SHIFT_POWER_STAGE1_8822B) +#define BITS_POWER_STAGE1_8822B \ + (BIT_MASK_POWER_STAGE1_8822B << BIT_SHIFT_POWER_STAGE1_8822B) +#define BIT_CLEAR_POWER_STAGE1_8822B(x) ((x) & (~BITS_POWER_STAGE1_8822B)) +#define BIT_GET_POWER_STAGE1_8822B(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1_8822B) & BIT_MASK_POWER_STAGE1_8822B) +#define BIT_SET_POWER_STAGE1_8822B(x, v) \ + (BIT_CLEAR_POWER_STAGE1_8822B(x) | BIT_POWER_STAGE1_8822B(v)) /* 2 REG_POWER_STAGE2_8822B */ #define BIT__R_CTRL_PKT_POW_ADJ_8822B BIT(24) #define BIT_SHIFT_POWER_STAGE2_8822B 0 #define BIT_MASK_POWER_STAGE2_8822B 0xffffff -#define BIT_POWER_STAGE2_8822B(x) (((x) & BIT_MASK_POWER_STAGE2_8822B) << BIT_SHIFT_POWER_STAGE2_8822B) -#define BIT_GET_POWER_STAGE2_8822B(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8822B) & BIT_MASK_POWER_STAGE2_8822B) - - +#define BIT_POWER_STAGE2_8822B(x) \ + (((x) & BIT_MASK_POWER_STAGE2_8822B) << BIT_SHIFT_POWER_STAGE2_8822B) +#define BITS_POWER_STAGE2_8822B \ + (BIT_MASK_POWER_STAGE2_8822B << BIT_SHIFT_POWER_STAGE2_8822B) +#define BIT_CLEAR_POWER_STAGE2_8822B(x) ((x) & (~BITS_POWER_STAGE2_8822B)) +#define BIT_GET_POWER_STAGE2_8822B(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2_8822B) & BIT_MASK_POWER_STAGE2_8822B) +#define BIT_SET_POWER_STAGE2_8822B(x, v) \ + (BIT_CLEAR_POWER_STAGE2_8822B(x) | BIT_POWER_STAGE2_8822B(v)) /* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822B */ #define BIT_SHIFT_PAD_NUM_THRES_8822B 24 #define BIT_MASK_PAD_NUM_THRES_8822B 0x3f -#define BIT_PAD_NUM_THRES_8822B(x) (((x) & BIT_MASK_PAD_NUM_THRES_8822B) << BIT_SHIFT_PAD_NUM_THRES_8822B) -#define BIT_GET_PAD_NUM_THRES_8822B(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8822B) & BIT_MASK_PAD_NUM_THRES_8822B) - +#define BIT_PAD_NUM_THRES_8822B(x) \ + (((x) & BIT_MASK_PAD_NUM_THRES_8822B) << BIT_SHIFT_PAD_NUM_THRES_8822B) +#define BITS_PAD_NUM_THRES_8822B \ + (BIT_MASK_PAD_NUM_THRES_8822B << BIT_SHIFT_PAD_NUM_THRES_8822B) +#define BIT_CLEAR_PAD_NUM_THRES_8822B(x) ((x) & (~BITS_PAD_NUM_THRES_8822B)) +#define BIT_GET_PAD_NUM_THRES_8822B(x) \ + (((x) >> BIT_SHIFT_PAD_NUM_THRES_8822B) & BIT_MASK_PAD_NUM_THRES_8822B) +#define BIT_SET_PAD_NUM_THRES_8822B(x, v) \ + (BIT_CLEAR_PAD_NUM_THRES_8822B(x) | BIT_PAD_NUM_THRES_8822B(v)) #define BIT_R_DMA_THIS_QUEUE_BK_8822B BIT(23) #define BIT_R_DMA_THIS_QUEUE_BE_8822B BIT(22) @@ -6124,18 +9442,32 @@ #define BIT_SHIFT_R_TOTAL_LEN_TH_8822B 8 #define BIT_MASK_R_TOTAL_LEN_TH_8822B 0xfff -#define BIT_R_TOTAL_LEN_TH_8822B(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8822B) << BIT_SHIFT_R_TOTAL_LEN_TH_8822B) -#define BIT_GET_R_TOTAL_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822B) & BIT_MASK_R_TOTAL_LEN_TH_8822B) - +#define BIT_R_TOTAL_LEN_TH_8822B(x) \ + (((x) & BIT_MASK_R_TOTAL_LEN_TH_8822B) \ + << BIT_SHIFT_R_TOTAL_LEN_TH_8822B) +#define BITS_R_TOTAL_LEN_TH_8822B \ + (BIT_MASK_R_TOTAL_LEN_TH_8822B << BIT_SHIFT_R_TOTAL_LEN_TH_8822B) +#define BIT_CLEAR_R_TOTAL_LEN_TH_8822B(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8822B)) +#define BIT_GET_R_TOTAL_LEN_TH_8822B(x) \ + (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822B) & \ + BIT_MASK_R_TOTAL_LEN_TH_8822B) +#define BIT_SET_R_TOTAL_LEN_TH_8822B(x, v) \ + (BIT_CLEAR_R_TOTAL_LEN_TH_8822B(x) | BIT_R_TOTAL_LEN_TH_8822B(v)) #define BIT_EN_NEW_EARLY_8822B BIT(7) #define BIT_PRE_TX_CMD_8822B BIT(6) #define BIT_SHIFT_NUM_SCL_EN_8822B 4 #define BIT_MASK_NUM_SCL_EN_8822B 0x3 -#define BIT_NUM_SCL_EN_8822B(x) (((x) & BIT_MASK_NUM_SCL_EN_8822B) << BIT_SHIFT_NUM_SCL_EN_8822B) -#define BIT_GET_NUM_SCL_EN_8822B(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8822B) & BIT_MASK_NUM_SCL_EN_8822B) - +#define BIT_NUM_SCL_EN_8822B(x) \ + (((x) & BIT_MASK_NUM_SCL_EN_8822B) << BIT_SHIFT_NUM_SCL_EN_8822B) +#define BITS_NUM_SCL_EN_8822B \ + (BIT_MASK_NUM_SCL_EN_8822B << BIT_SHIFT_NUM_SCL_EN_8822B) +#define BIT_CLEAR_NUM_SCL_EN_8822B(x) ((x) & (~BITS_NUM_SCL_EN_8822B)) +#define BIT_GET_NUM_SCL_EN_8822B(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN_8822B) & BIT_MASK_NUM_SCL_EN_8822B) +#define BIT_SET_NUM_SCL_EN_8822B(x, v) \ + (BIT_CLEAR_NUM_SCL_EN_8822B(x) | BIT_NUM_SCL_EN_8822B(v)) #define BIT_BK_EN_8822B BIT(3) #define BIT_BE_EN_8822B BIT(2) @@ -6146,49 +9478,86 @@ #define BIT_SHIFT_PKT_LIFTIME_BEBK_8822B 16 #define BIT_MASK_PKT_LIFTIME_BEBK_8822B 0xffff -#define BIT_PKT_LIFTIME_BEBK_8822B(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822B) << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) -#define BIT_GET_PKT_LIFTIME_BEBK_8822B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) & BIT_MASK_PKT_LIFTIME_BEBK_8822B) - - +#define BIT_PKT_LIFTIME_BEBK_8822B(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822B) \ + << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) +#define BITS_PKT_LIFTIME_BEBK_8822B \ + (BIT_MASK_PKT_LIFTIME_BEBK_8822B << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) +#define BIT_CLEAR_PKT_LIFTIME_BEBK_8822B(x) \ + ((x) & (~BITS_PKT_LIFTIME_BEBK_8822B)) +#define BIT_GET_PKT_LIFTIME_BEBK_8822B(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) & \ + BIT_MASK_PKT_LIFTIME_BEBK_8822B) +#define BIT_SET_PKT_LIFTIME_BEBK_8822B(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK_8822B(x) | BIT_PKT_LIFTIME_BEBK_8822B(v)) #define BIT_SHIFT_PKT_LIFTIME_VOVI_8822B 0 #define BIT_MASK_PKT_LIFTIME_VOVI_8822B 0xffff -#define BIT_PKT_LIFTIME_VOVI_8822B(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822B) << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) -#define BIT_GET_PKT_LIFTIME_VOVI_8822B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) & BIT_MASK_PKT_LIFTIME_VOVI_8822B) - - +#define BIT_PKT_LIFTIME_VOVI_8822B(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822B) \ + << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) +#define BITS_PKT_LIFTIME_VOVI_8822B \ + (BIT_MASK_PKT_LIFTIME_VOVI_8822B << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) +#define BIT_CLEAR_PKT_LIFTIME_VOVI_8822B(x) \ + ((x) & (~BITS_PKT_LIFTIME_VOVI_8822B)) +#define BIT_GET_PKT_LIFTIME_VOVI_8822B(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) & \ + BIT_MASK_PKT_LIFTIME_VOVI_8822B) +#define BIT_SET_PKT_LIFTIME_VOVI_8822B(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI_8822B(x) | BIT_PKT_LIFTIME_VOVI_8822B(v)) /* 2 REG_STBC_SETTING_8822B */ #define BIT_SHIFT_CDEND_TXTIME_L_8822B 4 #define BIT_MASK_CDEND_TXTIME_L_8822B 0xf -#define BIT_CDEND_TXTIME_L_8822B(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8822B) << BIT_SHIFT_CDEND_TXTIME_L_8822B) -#define BIT_GET_CDEND_TXTIME_L_8822B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822B) & BIT_MASK_CDEND_TXTIME_L_8822B) - - +#define BIT_CDEND_TXTIME_L_8822B(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L_8822B) \ + << BIT_SHIFT_CDEND_TXTIME_L_8822B) +#define BITS_CDEND_TXTIME_L_8822B \ + (BIT_MASK_CDEND_TXTIME_L_8822B << BIT_SHIFT_CDEND_TXTIME_L_8822B) +#define BIT_CLEAR_CDEND_TXTIME_L_8822B(x) ((x) & (~BITS_CDEND_TXTIME_L_8822B)) +#define BIT_GET_CDEND_TXTIME_L_8822B(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822B) & \ + BIT_MASK_CDEND_TXTIME_L_8822B) +#define BIT_SET_CDEND_TXTIME_L_8822B(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L_8822B(x) | BIT_CDEND_TXTIME_L_8822B(v)) #define BIT_SHIFT_NESS_8822B 2 #define BIT_MASK_NESS_8822B 0x3 #define BIT_NESS_8822B(x) (((x) & BIT_MASK_NESS_8822B) << BIT_SHIFT_NESS_8822B) -#define BIT_GET_NESS_8822B(x) (((x) >> BIT_SHIFT_NESS_8822B) & BIT_MASK_NESS_8822B) - - +#define BITS_NESS_8822B (BIT_MASK_NESS_8822B << BIT_SHIFT_NESS_8822B) +#define BIT_CLEAR_NESS_8822B(x) ((x) & (~BITS_NESS_8822B)) +#define BIT_GET_NESS_8822B(x) \ + (((x) >> BIT_SHIFT_NESS_8822B) & BIT_MASK_NESS_8822B) +#define BIT_SET_NESS_8822B(x, v) (BIT_CLEAR_NESS_8822B(x) | BIT_NESS_8822B(v)) #define BIT_SHIFT_STBC_CFEND_8822B 0 #define BIT_MASK_STBC_CFEND_8822B 0x3 -#define BIT_STBC_CFEND_8822B(x) (((x) & BIT_MASK_STBC_CFEND_8822B) << BIT_SHIFT_STBC_CFEND_8822B) -#define BIT_GET_STBC_CFEND_8822B(x) (((x) >> BIT_SHIFT_STBC_CFEND_8822B) & BIT_MASK_STBC_CFEND_8822B) - - +#define BIT_STBC_CFEND_8822B(x) \ + (((x) & BIT_MASK_STBC_CFEND_8822B) << BIT_SHIFT_STBC_CFEND_8822B) +#define BITS_STBC_CFEND_8822B \ + (BIT_MASK_STBC_CFEND_8822B << BIT_SHIFT_STBC_CFEND_8822B) +#define BIT_CLEAR_STBC_CFEND_8822B(x) ((x) & (~BITS_STBC_CFEND_8822B)) +#define BIT_GET_STBC_CFEND_8822B(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_8822B) & BIT_MASK_STBC_CFEND_8822B) +#define BIT_SET_STBC_CFEND_8822B(x, v) \ + (BIT_CLEAR_STBC_CFEND_8822B(x) | BIT_STBC_CFEND_8822B(v)) /* 2 REG_STBC_SETTING2_8822B */ #define BIT_SHIFT_CDEND_TXTIME_H_8822B 0 #define BIT_MASK_CDEND_TXTIME_H_8822B 0x1f -#define BIT_CDEND_TXTIME_H_8822B(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8822B) << BIT_SHIFT_CDEND_TXTIME_H_8822B) -#define BIT_GET_CDEND_TXTIME_H_8822B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822B) & BIT_MASK_CDEND_TXTIME_H_8822B) - - +#define BIT_CDEND_TXTIME_H_8822B(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H_8822B) \ + << BIT_SHIFT_CDEND_TXTIME_H_8822B) +#define BITS_CDEND_TXTIME_H_8822B \ + (BIT_MASK_CDEND_TXTIME_H_8822B << BIT_SHIFT_CDEND_TXTIME_H_8822B) +#define BIT_CLEAR_CDEND_TXTIME_H_8822B(x) ((x) & (~BITS_CDEND_TXTIME_H_8822B)) +#define BIT_GET_CDEND_TXTIME_H_8822B(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822B) & \ + BIT_MASK_CDEND_TXTIME_H_8822B) +#define BIT_SET_CDEND_TXTIME_H_8822B(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H_8822B(x) | BIT_CDEND_TXTIME_H_8822B(v)) /* 2 REG_QUEUE_CTRL_8822B */ #define BIT_PTA_EDCCA_EN_8822B BIT(5) @@ -6205,126 +9574,229 @@ #define BIT_SHIFT_RTS_MAX_AGG_NUM_8822B 24 #define BIT_MASK_RTS_MAX_AGG_NUM_8822B 0x3f -#define BIT_RTS_MAX_AGG_NUM_8822B(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822B) << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) -#define BIT_GET_RTS_MAX_AGG_NUM_8822B(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) & BIT_MASK_RTS_MAX_AGG_NUM_8822B) - - +#define BIT_RTS_MAX_AGG_NUM_8822B(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822B) \ + << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) +#define BITS_RTS_MAX_AGG_NUM_8822B \ + (BIT_MASK_RTS_MAX_AGG_NUM_8822B << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) +#define BIT_CLEAR_RTS_MAX_AGG_NUM_8822B(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8822B)) +#define BIT_GET_RTS_MAX_AGG_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) & \ + BIT_MASK_RTS_MAX_AGG_NUM_8822B) +#define BIT_SET_RTS_MAX_AGG_NUM_8822B(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM_8822B(x) | BIT_RTS_MAX_AGG_NUM_8822B(v)) #define BIT_SHIFT_MAX_AGG_NUM_8822B 16 #define BIT_MASK_MAX_AGG_NUM_8822B 0x3f -#define BIT_MAX_AGG_NUM_8822B(x) (((x) & BIT_MASK_MAX_AGG_NUM_8822B) << BIT_SHIFT_MAX_AGG_NUM_8822B) -#define BIT_GET_MAX_AGG_NUM_8822B(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8822B) & BIT_MASK_MAX_AGG_NUM_8822B) - - +#define BIT_MAX_AGG_NUM_8822B(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM_8822B) << BIT_SHIFT_MAX_AGG_NUM_8822B) +#define BITS_MAX_AGG_NUM_8822B \ + (BIT_MASK_MAX_AGG_NUM_8822B << BIT_SHIFT_MAX_AGG_NUM_8822B) +#define BIT_CLEAR_MAX_AGG_NUM_8822B(x) ((x) & (~BITS_MAX_AGG_NUM_8822B)) +#define BIT_GET_MAX_AGG_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM_8822B) & BIT_MASK_MAX_AGG_NUM_8822B) +#define BIT_SET_MAX_AGG_NUM_8822B(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM_8822B(x) | BIT_MAX_AGG_NUM_8822B(v)) #define BIT_SHIFT_RTS_TXTIME_TH_8822B 8 #define BIT_MASK_RTS_TXTIME_TH_8822B 0xff -#define BIT_RTS_TXTIME_TH_8822B(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8822B) << BIT_SHIFT_RTS_TXTIME_TH_8822B) -#define BIT_GET_RTS_TXTIME_TH_8822B(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822B) & BIT_MASK_RTS_TXTIME_TH_8822B) - - +#define BIT_RTS_TXTIME_TH_8822B(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH_8822B) << BIT_SHIFT_RTS_TXTIME_TH_8822B) +#define BITS_RTS_TXTIME_TH_8822B \ + (BIT_MASK_RTS_TXTIME_TH_8822B << BIT_SHIFT_RTS_TXTIME_TH_8822B) +#define BIT_CLEAR_RTS_TXTIME_TH_8822B(x) ((x) & (~BITS_RTS_TXTIME_TH_8822B)) +#define BIT_GET_RTS_TXTIME_TH_8822B(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822B) & BIT_MASK_RTS_TXTIME_TH_8822B) +#define BIT_SET_RTS_TXTIME_TH_8822B(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH_8822B(x) | BIT_RTS_TXTIME_TH_8822B(v)) #define BIT_SHIFT_RTS_LEN_TH_8822B 0 #define BIT_MASK_RTS_LEN_TH_8822B 0xff -#define BIT_RTS_LEN_TH_8822B(x) (((x) & BIT_MASK_RTS_LEN_TH_8822B) << BIT_SHIFT_RTS_LEN_TH_8822B) -#define BIT_GET_RTS_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8822B) & BIT_MASK_RTS_LEN_TH_8822B) - - +#define BIT_RTS_LEN_TH_8822B(x) \ + (((x) & BIT_MASK_RTS_LEN_TH_8822B) << BIT_SHIFT_RTS_LEN_TH_8822B) +#define BITS_RTS_LEN_TH_8822B \ + (BIT_MASK_RTS_LEN_TH_8822B << BIT_SHIFT_RTS_LEN_TH_8822B) +#define BIT_CLEAR_RTS_LEN_TH_8822B(x) ((x) & (~BITS_RTS_LEN_TH_8822B)) +#define BIT_GET_RTS_LEN_TH_8822B(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH_8822B) & BIT_MASK_RTS_LEN_TH_8822B) +#define BIT_SET_RTS_LEN_TH_8822B(x, v) \ + (BIT_CLEAR_RTS_LEN_TH_8822B(x) | BIT_RTS_LEN_TH_8822B(v)) /* 2 REG_BAR_MODE_CTRL_8822B */ #define BIT_SHIFT_BAR_RTY_LMT_8822B 16 #define BIT_MASK_BAR_RTY_LMT_8822B 0x3 -#define BIT_BAR_RTY_LMT_8822B(x) (((x) & BIT_MASK_BAR_RTY_LMT_8822B) << BIT_SHIFT_BAR_RTY_LMT_8822B) -#define BIT_GET_BAR_RTY_LMT_8822B(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8822B) & BIT_MASK_BAR_RTY_LMT_8822B) - - +#define BIT_BAR_RTY_LMT_8822B(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT_8822B) << BIT_SHIFT_BAR_RTY_LMT_8822B) +#define BITS_BAR_RTY_LMT_8822B \ + (BIT_MASK_BAR_RTY_LMT_8822B << BIT_SHIFT_BAR_RTY_LMT_8822B) +#define BIT_CLEAR_BAR_RTY_LMT_8822B(x) ((x) & (~BITS_BAR_RTY_LMT_8822B)) +#define BIT_GET_BAR_RTY_LMT_8822B(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT_8822B) & BIT_MASK_BAR_RTY_LMT_8822B) +#define BIT_SET_BAR_RTY_LMT_8822B(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT_8822B(x) | BIT_BAR_RTY_LMT_8822B(v)) #define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B 8 #define BIT_MASK_BAR_PKT_TXTIME_TH_8822B 0xff -#define BIT_BAR_PKT_TXTIME_TH_8822B(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) -#define BIT_GET_BAR_PKT_TXTIME_TH_8822B(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B) - +#define BIT_BAR_PKT_TXTIME_TH_8822B(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B) \ + << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) +#define BITS_BAR_PKT_TXTIME_TH_8822B \ + (BIT_MASK_BAR_PKT_TXTIME_TH_8822B << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8822B(x) \ + ((x) & (~BITS_BAR_PKT_TXTIME_TH_8822B)) +#define BIT_GET_BAR_PKT_TXTIME_TH_8822B(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) & \ + BIT_MASK_BAR_PKT_TXTIME_TH_8822B) +#define BIT_SET_BAR_PKT_TXTIME_TH_8822B(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH_8822B(x) | BIT_BAR_PKT_TXTIME_TH_8822B(v)) #define BIT_BAR_EN_V1_8822B BIT(6) #define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B 0 #define BIT_MASK_BAR_PKTNUM_TH_V1_8822B 0x3f -#define BIT_BAR_PKTNUM_TH_V1_8822B(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) -#define BIT_GET_BAR_PKTNUM_TH_V1_8822B(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B) - - +#define BIT_BAR_PKTNUM_TH_V1_8822B(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B) \ + << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) +#define BITS_BAR_PKTNUM_TH_V1_8822B \ + (BIT_MASK_BAR_PKTNUM_TH_V1_8822B << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8822B(x) \ + ((x) & (~BITS_BAR_PKTNUM_TH_V1_8822B)) +#define BIT_GET_BAR_PKTNUM_TH_V1_8822B(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) & \ + BIT_MASK_BAR_PKTNUM_TH_V1_8822B) +#define BIT_SET_BAR_PKTNUM_TH_V1_8822B(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1_8822B(x) | BIT_BAR_PKTNUM_TH_V1_8822B(v)) /* 2 REG_RA_TRY_RATE_AGG_LMT_8822B */ #define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B 0 #define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B 0x3f -#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) -#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822B(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) - - +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) +#define BITS_RA_TRY_RATE_AGG_LMT_V1_8822B \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822B(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8822B)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822B(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8822B(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822B(x) | \ + BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(v)) /* 2 REG_MACID_SLEEP2_8822B */ #define BIT_SHIFT_MACID95_64PKTSLEEP_8822B 0 #define BIT_MASK_MACID95_64PKTSLEEP_8822B 0xffffffffL -#define BIT_MACID95_64PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8822B) << BIT_SHIFT_MACID95_64PKTSLEEP_8822B) -#define BIT_GET_MACID95_64PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822B) & BIT_MASK_MACID95_64PKTSLEEP_8822B) - - +#define BIT_MACID95_64PKTSLEEP_8822B(x) \ + (((x) & BIT_MASK_MACID95_64PKTSLEEP_8822B) \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8822B) +#define BITS_MACID95_64PKTSLEEP_8822B \ + (BIT_MASK_MACID95_64PKTSLEEP_8822B \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8822B) +#define BIT_CLEAR_MACID95_64PKTSLEEP_8822B(x) \ + ((x) & (~BITS_MACID95_64PKTSLEEP_8822B)) +#define BIT_GET_MACID95_64PKTSLEEP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822B) & \ + BIT_MASK_MACID95_64PKTSLEEP_8822B) +#define BIT_SET_MACID95_64PKTSLEEP_8822B(x, v) \ + (BIT_CLEAR_MACID95_64PKTSLEEP_8822B(x) | \ + BIT_MACID95_64PKTSLEEP_8822B(v)) /* 2 REG_MACID_SLEEP_8822B */ #define BIT_SHIFT_MACID31_0_PKTSLEEP_8822B 0 #define BIT_MASK_MACID31_0_PKTSLEEP_8822B 0xffffffffL -#define BIT_MACID31_0_PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822B) << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) -#define BIT_GET_MACID31_0_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) & BIT_MASK_MACID31_0_PKTSLEEP_8822B) - - +#define BIT_MACID31_0_PKTSLEEP_8822B(x) \ + (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822B) \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) +#define BITS_MACID31_0_PKTSLEEP_8822B \ + (BIT_MASK_MACID31_0_PKTSLEEP_8822B \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) +#define BIT_CLEAR_MACID31_0_PKTSLEEP_8822B(x) \ + ((x) & (~BITS_MACID31_0_PKTSLEEP_8822B)) +#define BIT_GET_MACID31_0_PKTSLEEP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) & \ + BIT_MASK_MACID31_0_PKTSLEEP_8822B) +#define BIT_SET_MACID31_0_PKTSLEEP_8822B(x, v) \ + (BIT_CLEAR_MACID31_0_PKTSLEEP_8822B(x) | \ + BIT_MACID31_0_PKTSLEEP_8822B(v)) /* 2 REG_HW_SEQ0_8822B */ #define BIT_SHIFT_HW_SSN_SEQ0_8822B 0 #define BIT_MASK_HW_SSN_SEQ0_8822B 0xfff -#define BIT_HW_SSN_SEQ0_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8822B) << BIT_SHIFT_HW_SSN_SEQ0_8822B) -#define BIT_GET_HW_SSN_SEQ0_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822B) & BIT_MASK_HW_SSN_SEQ0_8822B) - - +#define BIT_HW_SSN_SEQ0_8822B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0_8822B) << BIT_SHIFT_HW_SSN_SEQ0_8822B) +#define BITS_HW_SSN_SEQ0_8822B \ + (BIT_MASK_HW_SSN_SEQ0_8822B << BIT_SHIFT_HW_SSN_SEQ0_8822B) +#define BIT_CLEAR_HW_SSN_SEQ0_8822B(x) ((x) & (~BITS_HW_SSN_SEQ0_8822B)) +#define BIT_GET_HW_SSN_SEQ0_8822B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822B) & BIT_MASK_HW_SSN_SEQ0_8822B) +#define BIT_SET_HW_SSN_SEQ0_8822B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0_8822B(x) | BIT_HW_SSN_SEQ0_8822B(v)) /* 2 REG_HW_SEQ1_8822B */ #define BIT_SHIFT_HW_SSN_SEQ1_8822B 0 #define BIT_MASK_HW_SSN_SEQ1_8822B 0xfff -#define BIT_HW_SSN_SEQ1_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8822B) << BIT_SHIFT_HW_SSN_SEQ1_8822B) -#define BIT_GET_HW_SSN_SEQ1_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822B) & BIT_MASK_HW_SSN_SEQ1_8822B) - - +#define BIT_HW_SSN_SEQ1_8822B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1_8822B) << BIT_SHIFT_HW_SSN_SEQ1_8822B) +#define BITS_HW_SSN_SEQ1_8822B \ + (BIT_MASK_HW_SSN_SEQ1_8822B << BIT_SHIFT_HW_SSN_SEQ1_8822B) +#define BIT_CLEAR_HW_SSN_SEQ1_8822B(x) ((x) & (~BITS_HW_SSN_SEQ1_8822B)) +#define BIT_GET_HW_SSN_SEQ1_8822B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822B) & BIT_MASK_HW_SSN_SEQ1_8822B) +#define BIT_SET_HW_SSN_SEQ1_8822B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1_8822B(x) | BIT_HW_SSN_SEQ1_8822B(v)) /* 2 REG_HW_SEQ2_8822B */ #define BIT_SHIFT_HW_SSN_SEQ2_8822B 0 #define BIT_MASK_HW_SSN_SEQ2_8822B 0xfff -#define BIT_HW_SSN_SEQ2_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8822B) << BIT_SHIFT_HW_SSN_SEQ2_8822B) -#define BIT_GET_HW_SSN_SEQ2_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822B) & BIT_MASK_HW_SSN_SEQ2_8822B) - - +#define BIT_HW_SSN_SEQ2_8822B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2_8822B) << BIT_SHIFT_HW_SSN_SEQ2_8822B) +#define BITS_HW_SSN_SEQ2_8822B \ + (BIT_MASK_HW_SSN_SEQ2_8822B << BIT_SHIFT_HW_SSN_SEQ2_8822B) +#define BIT_CLEAR_HW_SSN_SEQ2_8822B(x) ((x) & (~BITS_HW_SSN_SEQ2_8822B)) +#define BIT_GET_HW_SSN_SEQ2_8822B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822B) & BIT_MASK_HW_SSN_SEQ2_8822B) +#define BIT_SET_HW_SSN_SEQ2_8822B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2_8822B(x) | BIT_HW_SSN_SEQ2_8822B(v)) /* 2 REG_HW_SEQ3_8822B */ #define BIT_SHIFT_HW_SSN_SEQ3_8822B 0 #define BIT_MASK_HW_SSN_SEQ3_8822B 0xfff -#define BIT_HW_SSN_SEQ3_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8822B) << BIT_SHIFT_HW_SSN_SEQ3_8822B) -#define BIT_GET_HW_SSN_SEQ3_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822B) & BIT_MASK_HW_SSN_SEQ3_8822B) - - +#define BIT_HW_SSN_SEQ3_8822B(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3_8822B) << BIT_SHIFT_HW_SSN_SEQ3_8822B) +#define BITS_HW_SSN_SEQ3_8822B \ + (BIT_MASK_HW_SSN_SEQ3_8822B << BIT_SHIFT_HW_SSN_SEQ3_8822B) +#define BIT_CLEAR_HW_SSN_SEQ3_8822B(x) ((x) & (~BITS_HW_SSN_SEQ3_8822B)) +#define BIT_GET_HW_SSN_SEQ3_8822B(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822B) & BIT_MASK_HW_SSN_SEQ3_8822B) +#define BIT_SET_HW_SSN_SEQ3_8822B(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3_8822B(x) | BIT_HW_SSN_SEQ3_8822B(v)) /* 2 REG_NULL_PKT_STATUS_V1_8822B */ #define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B 2 #define BIT_MASK_PTCL_TOTAL_PG_V2_8822B 0x3fff -#define BIT_PTCL_TOTAL_PG_V2_8822B(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) -#define BIT_GET_PTCL_TOTAL_PG_V2_8822B(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B) - +#define BIT_PTCL_TOTAL_PG_V2_8822B(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B) \ + << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) +#define BITS_PTCL_TOTAL_PG_V2_8822B \ + (BIT_MASK_PTCL_TOTAL_PG_V2_8822B << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) +#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8822B(x) \ + ((x) & (~BITS_PTCL_TOTAL_PG_V2_8822B)) +#define BIT_GET_PTCL_TOTAL_PG_V2_8822B(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) & \ + BIT_MASK_PTCL_TOTAL_PG_V2_8822B) +#define BIT_SET_PTCL_TOTAL_PG_V2_8822B(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V2_8822B(x) | BIT_PTCL_TOTAL_PG_V2_8822B(v)) #define BIT_TX_NULL_1_8822B BIT(1) #define BIT_TX_NULL_0_8822B BIT(0) @@ -6357,10 +9829,20 @@ #define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B 0 #define BIT_MASK_BT_POLLUTE_PKT_CNT_8822B 0xffff -#define BIT_BT_POLLUTE_PKT_CNT_8822B(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) -#define BIT_GET_BT_POLLUTE_PKT_CNT_8822B(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) - - +#define BIT_BT_POLLUTE_PKT_CNT_8822B(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) +#define BITS_BT_POLLUTE_PKT_CNT_8822B \ + (BIT_MASK_BT_POLLUTE_PKT_CNT_8822B \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) +#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822B(x) \ + ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8822B)) +#define BIT_GET_BT_POLLUTE_PKT_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) & \ + BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) +#define BIT_SET_BT_POLLUTE_PKT_CNT_8822B(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822B(x) | \ + BIT_BT_POLLUTE_PKT_CNT_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -6368,10 +9850,15 @@ #define BIT_SHIFT_PTCL_DBG_8822B 0 #define BIT_MASK_PTCL_DBG_8822B 0xffffffffL -#define BIT_PTCL_DBG_8822B(x) (((x) & BIT_MASK_PTCL_DBG_8822B) << BIT_SHIFT_PTCL_DBG_8822B) -#define BIT_GET_PTCL_DBG_8822B(x) (((x) >> BIT_SHIFT_PTCL_DBG_8822B) & BIT_MASK_PTCL_DBG_8822B) - - +#define BIT_PTCL_DBG_8822B(x) \ + (((x) & BIT_MASK_PTCL_DBG_8822B) << BIT_SHIFT_PTCL_DBG_8822B) +#define BITS_PTCL_DBG_8822B \ + (BIT_MASK_PTCL_DBG_8822B << BIT_SHIFT_PTCL_DBG_8822B) +#define BIT_CLEAR_PTCL_DBG_8822B(x) ((x) & (~BITS_PTCL_DBG_8822B)) +#define BIT_GET_PTCL_DBG_8822B(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_8822B) & BIT_MASK_PTCL_DBG_8822B) +#define BIT_SET_PTCL_DBG_8822B(x, v) \ + (BIT_CLEAR_PTCL_DBG_8822B(x) | BIT_PTCL_DBG_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -6379,18 +9866,28 @@ #define BIT_SHIFT_TRI_HEAD_ADDR_8822B 16 #define BIT_MASK_TRI_HEAD_ADDR_8822B 0xfff -#define BIT_TRI_HEAD_ADDR_8822B(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8822B) << BIT_SHIFT_TRI_HEAD_ADDR_8822B) -#define BIT_GET_TRI_HEAD_ADDR_8822B(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822B) & BIT_MASK_TRI_HEAD_ADDR_8822B) - +#define BIT_TRI_HEAD_ADDR_8822B(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR_8822B) << BIT_SHIFT_TRI_HEAD_ADDR_8822B) +#define BITS_TRI_HEAD_ADDR_8822B \ + (BIT_MASK_TRI_HEAD_ADDR_8822B << BIT_SHIFT_TRI_HEAD_ADDR_8822B) +#define BIT_CLEAR_TRI_HEAD_ADDR_8822B(x) ((x) & (~BITS_TRI_HEAD_ADDR_8822B)) +#define BIT_GET_TRI_HEAD_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822B) & BIT_MASK_TRI_HEAD_ADDR_8822B) +#define BIT_SET_TRI_HEAD_ADDR_8822B(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR_8822B(x) | BIT_TRI_HEAD_ADDR_8822B(v)) #define BIT_DROP_TH_EN_8822B BIT(8) #define BIT_SHIFT_DROP_TH_8822B 0 #define BIT_MASK_DROP_TH_8822B 0xff -#define BIT_DROP_TH_8822B(x) (((x) & BIT_MASK_DROP_TH_8822B) << BIT_SHIFT_DROP_TH_8822B) -#define BIT_GET_DROP_TH_8822B(x) (((x) >> BIT_SHIFT_DROP_TH_8822B) & BIT_MASK_DROP_TH_8822B) - - +#define BIT_DROP_TH_8822B(x) \ + (((x) & BIT_MASK_DROP_TH_8822B) << BIT_SHIFT_DROP_TH_8822B) +#define BITS_DROP_TH_8822B (BIT_MASK_DROP_TH_8822B << BIT_SHIFT_DROP_TH_8822B) +#define BIT_CLEAR_DROP_TH_8822B(x) ((x) & (~BITS_DROP_TH_8822B)) +#define BIT_GET_DROP_TH_8822B(x) \ + (((x) >> BIT_SHIFT_DROP_TH_8822B) & BIT_MASK_DROP_TH_8822B) +#define BIT_SET_DROP_TH_8822B(x, v) \ + (BIT_CLEAR_DROP_TH_8822B(x) | BIT_DROP_TH_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -6410,176 +9907,287 @@ #define BIT_SHIFT_GTAB_ID_8822B 28 #define BIT_MASK_GTAB_ID_8822B 0x7 -#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) -#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) - - +#define BIT_GTAB_ID_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) +#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B) +#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B)) +#define BIT_GET_GTAB_ID_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) +#define BIT_SET_GTAB_ID_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v)) #define BIT_SHIFT_AC1_PKT_INFO_8822B 16 #define BIT_MASK_AC1_PKT_INFO_8822B 0xfff -#define BIT_AC1_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC1_PKT_INFO_8822B) << BIT_SHIFT_AC1_PKT_INFO_8822B) -#define BIT_GET_AC1_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8822B) & BIT_MASK_AC1_PKT_INFO_8822B) - +#define BIT_AC1_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC1_PKT_INFO_8822B) << BIT_SHIFT_AC1_PKT_INFO_8822B) +#define BITS_AC1_PKT_INFO_8822B \ + (BIT_MASK_AC1_PKT_INFO_8822B << BIT_SHIFT_AC1_PKT_INFO_8822B) +#define BIT_CLEAR_AC1_PKT_INFO_8822B(x) ((x) & (~BITS_AC1_PKT_INFO_8822B)) +#define BIT_GET_AC1_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC1_PKT_INFO_8822B) & BIT_MASK_AC1_PKT_INFO_8822B) +#define BIT_SET_AC1_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC1_PKT_INFO_8822B(x) | BIT_AC1_PKT_INFO_8822B(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 #define BIT_MASK_GTAB_ID_V1_8822B 0x7 -#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) -#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) - - +#define BIT_GTAB_ID_V1_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BITS_GTAB_ID_V1_8822B \ + (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B)) +#define BIT_GET_GTAB_ID_V1_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) +#define BIT_SET_GTAB_ID_V1_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v)) #define BIT_SHIFT_AC0_PKT_INFO_8822B 0 #define BIT_MASK_AC0_PKT_INFO_8822B 0xfff -#define BIT_AC0_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC0_PKT_INFO_8822B) << BIT_SHIFT_AC0_PKT_INFO_8822B) -#define BIT_GET_AC0_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8822B) & BIT_MASK_AC0_PKT_INFO_8822B) - - +#define BIT_AC0_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC0_PKT_INFO_8822B) << BIT_SHIFT_AC0_PKT_INFO_8822B) +#define BITS_AC0_PKT_INFO_8822B \ + (BIT_MASK_AC0_PKT_INFO_8822B << BIT_SHIFT_AC0_PKT_INFO_8822B) +#define BIT_CLEAR_AC0_PKT_INFO_8822B(x) ((x) & (~BITS_AC0_PKT_INFO_8822B)) +#define BIT_GET_AC0_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC0_PKT_INFO_8822B) & BIT_MASK_AC0_PKT_INFO_8822B) +#define BIT_SET_AC0_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC0_PKT_INFO_8822B(x) | BIT_AC0_PKT_INFO_8822B(v)) /* 2 REG_Q2_Q3_INFO_8822B */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31) #define BIT_SHIFT_GTAB_ID_8822B 28 #define BIT_MASK_GTAB_ID_8822B 0x7 -#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) -#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) - - +#define BIT_GTAB_ID_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) +#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B) +#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B)) +#define BIT_GET_GTAB_ID_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) +#define BIT_SET_GTAB_ID_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v)) #define BIT_SHIFT_AC3_PKT_INFO_8822B 16 #define BIT_MASK_AC3_PKT_INFO_8822B 0xfff -#define BIT_AC3_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC3_PKT_INFO_8822B) << BIT_SHIFT_AC3_PKT_INFO_8822B) -#define BIT_GET_AC3_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8822B) & BIT_MASK_AC3_PKT_INFO_8822B) - +#define BIT_AC3_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC3_PKT_INFO_8822B) << BIT_SHIFT_AC3_PKT_INFO_8822B) +#define BITS_AC3_PKT_INFO_8822B \ + (BIT_MASK_AC3_PKT_INFO_8822B << BIT_SHIFT_AC3_PKT_INFO_8822B) +#define BIT_CLEAR_AC3_PKT_INFO_8822B(x) ((x) & (~BITS_AC3_PKT_INFO_8822B)) +#define BIT_GET_AC3_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC3_PKT_INFO_8822B) & BIT_MASK_AC3_PKT_INFO_8822B) +#define BIT_SET_AC3_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC3_PKT_INFO_8822B(x) | BIT_AC3_PKT_INFO_8822B(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 #define BIT_MASK_GTAB_ID_V1_8822B 0x7 -#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) -#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) - - +#define BIT_GTAB_ID_V1_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BITS_GTAB_ID_V1_8822B \ + (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B)) +#define BIT_GET_GTAB_ID_V1_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) +#define BIT_SET_GTAB_ID_V1_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v)) #define BIT_SHIFT_AC2_PKT_INFO_8822B 0 #define BIT_MASK_AC2_PKT_INFO_8822B 0xfff -#define BIT_AC2_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC2_PKT_INFO_8822B) << BIT_SHIFT_AC2_PKT_INFO_8822B) -#define BIT_GET_AC2_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8822B) & BIT_MASK_AC2_PKT_INFO_8822B) - - +#define BIT_AC2_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC2_PKT_INFO_8822B) << BIT_SHIFT_AC2_PKT_INFO_8822B) +#define BITS_AC2_PKT_INFO_8822B \ + (BIT_MASK_AC2_PKT_INFO_8822B << BIT_SHIFT_AC2_PKT_INFO_8822B) +#define BIT_CLEAR_AC2_PKT_INFO_8822B(x) ((x) & (~BITS_AC2_PKT_INFO_8822B)) +#define BIT_GET_AC2_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC2_PKT_INFO_8822B) & BIT_MASK_AC2_PKT_INFO_8822B) +#define BIT_SET_AC2_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC2_PKT_INFO_8822B(x) | BIT_AC2_PKT_INFO_8822B(v)) /* 2 REG_Q4_Q5_INFO_8822B */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31) #define BIT_SHIFT_GTAB_ID_8822B 28 #define BIT_MASK_GTAB_ID_8822B 0x7 -#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) -#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) - - +#define BIT_GTAB_ID_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) +#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B) +#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B)) +#define BIT_GET_GTAB_ID_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) +#define BIT_SET_GTAB_ID_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v)) #define BIT_SHIFT_AC5_PKT_INFO_8822B 16 #define BIT_MASK_AC5_PKT_INFO_8822B 0xfff -#define BIT_AC5_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC5_PKT_INFO_8822B) << BIT_SHIFT_AC5_PKT_INFO_8822B) -#define BIT_GET_AC5_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8822B) & BIT_MASK_AC5_PKT_INFO_8822B) - +#define BIT_AC5_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC5_PKT_INFO_8822B) << BIT_SHIFT_AC5_PKT_INFO_8822B) +#define BITS_AC5_PKT_INFO_8822B \ + (BIT_MASK_AC5_PKT_INFO_8822B << BIT_SHIFT_AC5_PKT_INFO_8822B) +#define BIT_CLEAR_AC5_PKT_INFO_8822B(x) ((x) & (~BITS_AC5_PKT_INFO_8822B)) +#define BIT_GET_AC5_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC5_PKT_INFO_8822B) & BIT_MASK_AC5_PKT_INFO_8822B) +#define BIT_SET_AC5_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC5_PKT_INFO_8822B(x) | BIT_AC5_PKT_INFO_8822B(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 #define BIT_MASK_GTAB_ID_V1_8822B 0x7 -#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) -#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) - - +#define BIT_GTAB_ID_V1_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BITS_GTAB_ID_V1_8822B \ + (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B)) +#define BIT_GET_GTAB_ID_V1_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) +#define BIT_SET_GTAB_ID_V1_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v)) #define BIT_SHIFT_AC4_PKT_INFO_8822B 0 #define BIT_MASK_AC4_PKT_INFO_8822B 0xfff -#define BIT_AC4_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC4_PKT_INFO_8822B) << BIT_SHIFT_AC4_PKT_INFO_8822B) -#define BIT_GET_AC4_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8822B) & BIT_MASK_AC4_PKT_INFO_8822B) - - +#define BIT_AC4_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC4_PKT_INFO_8822B) << BIT_SHIFT_AC4_PKT_INFO_8822B) +#define BITS_AC4_PKT_INFO_8822B \ + (BIT_MASK_AC4_PKT_INFO_8822B << BIT_SHIFT_AC4_PKT_INFO_8822B) +#define BIT_CLEAR_AC4_PKT_INFO_8822B(x) ((x) & (~BITS_AC4_PKT_INFO_8822B)) +#define BIT_GET_AC4_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC4_PKT_INFO_8822B) & BIT_MASK_AC4_PKT_INFO_8822B) +#define BIT_SET_AC4_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC4_PKT_INFO_8822B(x) | BIT_AC4_PKT_INFO_8822B(v)) /* 2 REG_Q6_Q7_INFO_8822B */ #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31) #define BIT_SHIFT_GTAB_ID_8822B 28 #define BIT_MASK_GTAB_ID_8822B 0x7 -#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) -#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) - - +#define BIT_GTAB_ID_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B) +#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B) +#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B)) +#define BIT_GET_GTAB_ID_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B) +#define BIT_SET_GTAB_ID_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v)) #define BIT_SHIFT_AC7_PKT_INFO_8822B 16 #define BIT_MASK_AC7_PKT_INFO_8822B 0xfff -#define BIT_AC7_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC7_PKT_INFO_8822B) << BIT_SHIFT_AC7_PKT_INFO_8822B) -#define BIT_GET_AC7_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8822B) & BIT_MASK_AC7_PKT_INFO_8822B) - +#define BIT_AC7_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC7_PKT_INFO_8822B) << BIT_SHIFT_AC7_PKT_INFO_8822B) +#define BITS_AC7_PKT_INFO_8822B \ + (BIT_MASK_AC7_PKT_INFO_8822B << BIT_SHIFT_AC7_PKT_INFO_8822B) +#define BIT_CLEAR_AC7_PKT_INFO_8822B(x) ((x) & (~BITS_AC7_PKT_INFO_8822B)) +#define BIT_GET_AC7_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC7_PKT_INFO_8822B) & BIT_MASK_AC7_PKT_INFO_8822B) +#define BIT_SET_AC7_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC7_PKT_INFO_8822B(x) | BIT_AC7_PKT_INFO_8822B(v)) #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15) #define BIT_SHIFT_GTAB_ID_V1_8822B 12 #define BIT_MASK_GTAB_ID_V1_8822B 0x7 -#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) -#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) - - +#define BIT_GTAB_ID_V1_8822B(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BITS_GTAB_ID_V1_8822B \ + (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B) +#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B)) +#define BIT_GET_GTAB_ID_V1_8822B(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B) +#define BIT_SET_GTAB_ID_V1_8822B(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v)) #define BIT_SHIFT_AC6_PKT_INFO_8822B 0 #define BIT_MASK_AC6_PKT_INFO_8822B 0xfff -#define BIT_AC6_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC6_PKT_INFO_8822B) << BIT_SHIFT_AC6_PKT_INFO_8822B) -#define BIT_GET_AC6_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8822B) & BIT_MASK_AC6_PKT_INFO_8822B) - - +#define BIT_AC6_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_AC6_PKT_INFO_8822B) << BIT_SHIFT_AC6_PKT_INFO_8822B) +#define BITS_AC6_PKT_INFO_8822B \ + (BIT_MASK_AC6_PKT_INFO_8822B << BIT_SHIFT_AC6_PKT_INFO_8822B) +#define BIT_CLEAR_AC6_PKT_INFO_8822B(x) ((x) & (~BITS_AC6_PKT_INFO_8822B)) +#define BIT_GET_AC6_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_AC6_PKT_INFO_8822B) & BIT_MASK_AC6_PKT_INFO_8822B) +#define BIT_SET_AC6_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_AC6_PKT_INFO_8822B(x) | BIT_AC6_PKT_INFO_8822B(v)) /* 2 REG_MGQ_HIQ_INFO_8822B */ #define BIT_SHIFT_HIQ_PKT_INFO_8822B 16 #define BIT_MASK_HIQ_PKT_INFO_8822B 0xfff -#define BIT_HIQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8822B) << BIT_SHIFT_HIQ_PKT_INFO_8822B) -#define BIT_GET_HIQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822B) & BIT_MASK_HIQ_PKT_INFO_8822B) - - +#define BIT_HIQ_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_HIQ_PKT_INFO_8822B) << BIT_SHIFT_HIQ_PKT_INFO_8822B) +#define BITS_HIQ_PKT_INFO_8822B \ + (BIT_MASK_HIQ_PKT_INFO_8822B << BIT_SHIFT_HIQ_PKT_INFO_8822B) +#define BIT_CLEAR_HIQ_PKT_INFO_8822B(x) ((x) & (~BITS_HIQ_PKT_INFO_8822B)) +#define BIT_GET_HIQ_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822B) & BIT_MASK_HIQ_PKT_INFO_8822B) +#define BIT_SET_HIQ_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_HIQ_PKT_INFO_8822B(x) | BIT_HIQ_PKT_INFO_8822B(v)) #define BIT_SHIFT_MGQ_PKT_INFO_8822B 0 #define BIT_MASK_MGQ_PKT_INFO_8822B 0xfff -#define BIT_MGQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8822B) << BIT_SHIFT_MGQ_PKT_INFO_8822B) -#define BIT_GET_MGQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822B) & BIT_MASK_MGQ_PKT_INFO_8822B) - - +#define BIT_MGQ_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_MGQ_PKT_INFO_8822B) << BIT_SHIFT_MGQ_PKT_INFO_8822B) +#define BITS_MGQ_PKT_INFO_8822B \ + (BIT_MASK_MGQ_PKT_INFO_8822B << BIT_SHIFT_MGQ_PKT_INFO_8822B) +#define BIT_CLEAR_MGQ_PKT_INFO_8822B(x) ((x) & (~BITS_MGQ_PKT_INFO_8822B)) +#define BIT_GET_MGQ_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822B) & BIT_MASK_MGQ_PKT_INFO_8822B) +#define BIT_SET_MGQ_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_MGQ_PKT_INFO_8822B(x) | BIT_MGQ_PKT_INFO_8822B(v)) /* 2 REG_CMDQ_BCNQ_INFO_8822B */ #define BIT_SHIFT_CMDQ_PKT_INFO_8822B 16 #define BIT_MASK_CMDQ_PKT_INFO_8822B 0xfff -#define BIT_CMDQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_8822B) << BIT_SHIFT_CMDQ_PKT_INFO_8822B) -#define BIT_GET_CMDQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822B) & BIT_MASK_CMDQ_PKT_INFO_8822B) - - +#define BIT_CMDQ_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO_8822B) << BIT_SHIFT_CMDQ_PKT_INFO_8822B) +#define BITS_CMDQ_PKT_INFO_8822B \ + (BIT_MASK_CMDQ_PKT_INFO_8822B << BIT_SHIFT_CMDQ_PKT_INFO_8822B) +#define BIT_CLEAR_CMDQ_PKT_INFO_8822B(x) ((x) & (~BITS_CMDQ_PKT_INFO_8822B)) +#define BIT_GET_CMDQ_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822B) & BIT_MASK_CMDQ_PKT_INFO_8822B) +#define BIT_SET_CMDQ_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO_8822B(x) | BIT_CMDQ_PKT_INFO_8822B(v)) #define BIT_SHIFT_BCNQ_PKT_INFO_8822B 0 #define BIT_MASK_BCNQ_PKT_INFO_8822B 0xfff -#define BIT_BCNQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8822B) << BIT_SHIFT_BCNQ_PKT_INFO_8822B) -#define BIT_GET_BCNQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822B) & BIT_MASK_BCNQ_PKT_INFO_8822B) - - +#define BIT_BCNQ_PKT_INFO_8822B(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO_8822B) << BIT_SHIFT_BCNQ_PKT_INFO_8822B) +#define BITS_BCNQ_PKT_INFO_8822B \ + (BIT_MASK_BCNQ_PKT_INFO_8822B << BIT_SHIFT_BCNQ_PKT_INFO_8822B) +#define BIT_CLEAR_BCNQ_PKT_INFO_8822B(x) ((x) & (~BITS_BCNQ_PKT_INFO_8822B)) +#define BIT_GET_BCNQ_PKT_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822B) & BIT_MASK_BCNQ_PKT_INFO_8822B) +#define BIT_SET_BCNQ_PKT_INFO_8822B(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO_8822B(x) | BIT_BCNQ_PKT_INFO_8822B(v)) /* 2 REG_USEREG_SETTING_8822B */ #define BIT_NDPA_USEREG_8822B BIT(21) #define BIT_SHIFT_RETRY_USEREG_8822B 19 #define BIT_MASK_RETRY_USEREG_8822B 0x3 -#define BIT_RETRY_USEREG_8822B(x) (((x) & BIT_MASK_RETRY_USEREG_8822B) << BIT_SHIFT_RETRY_USEREG_8822B) -#define BIT_GET_RETRY_USEREG_8822B(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8822B) & BIT_MASK_RETRY_USEREG_8822B) - - +#define BIT_RETRY_USEREG_8822B(x) \ + (((x) & BIT_MASK_RETRY_USEREG_8822B) << BIT_SHIFT_RETRY_USEREG_8822B) +#define BITS_RETRY_USEREG_8822B \ + (BIT_MASK_RETRY_USEREG_8822B << BIT_SHIFT_RETRY_USEREG_8822B) +#define BIT_CLEAR_RETRY_USEREG_8822B(x) ((x) & (~BITS_RETRY_USEREG_8822B)) +#define BIT_GET_RETRY_USEREG_8822B(x) \ + (((x) >> BIT_SHIFT_RETRY_USEREG_8822B) & BIT_MASK_RETRY_USEREG_8822B) +#define BIT_SET_RETRY_USEREG_8822B(x, v) \ + (BIT_CLEAR_RETRY_USEREG_8822B(x) | BIT_RETRY_USEREG_8822B(v)) #define BIT_SHIFT_TRYPKT_USEREG_8822B 17 #define BIT_MASK_TRYPKT_USEREG_8822B 0x3 -#define BIT_TRYPKT_USEREG_8822B(x) (((x) & BIT_MASK_TRYPKT_USEREG_8822B) << BIT_SHIFT_TRYPKT_USEREG_8822B) -#define BIT_GET_TRYPKT_USEREG_8822B(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8822B) & BIT_MASK_TRYPKT_USEREG_8822B) - +#define BIT_TRYPKT_USEREG_8822B(x) \ + (((x) & BIT_MASK_TRYPKT_USEREG_8822B) << BIT_SHIFT_TRYPKT_USEREG_8822B) +#define BITS_TRYPKT_USEREG_8822B \ + (BIT_MASK_TRYPKT_USEREG_8822B << BIT_SHIFT_TRYPKT_USEREG_8822B) +#define BIT_CLEAR_TRYPKT_USEREG_8822B(x) ((x) & (~BITS_TRYPKT_USEREG_8822B)) +#define BIT_GET_TRYPKT_USEREG_8822B(x) \ + (((x) >> BIT_SHIFT_TRYPKT_USEREG_8822B) & BIT_MASK_TRYPKT_USEREG_8822B) +#define BIT_SET_TRYPKT_USEREG_8822B(x, v) \ + (BIT_CLEAR_TRYPKT_USEREG_8822B(x) | BIT_TRYPKT_USEREG_8822B(v)) #define BIT_CTLPKT_USEREG_8822B BIT(16) @@ -6587,10 +10195,15 @@ #define BIT_SHIFT_AESIV_OFFSET_8822B 0 #define BIT_MASK_AESIV_OFFSET_8822B 0xfff -#define BIT_AESIV_OFFSET_8822B(x) (((x) & BIT_MASK_AESIV_OFFSET_8822B) << BIT_SHIFT_AESIV_OFFSET_8822B) -#define BIT_GET_AESIV_OFFSET_8822B(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8822B) & BIT_MASK_AESIV_OFFSET_8822B) - - +#define BIT_AESIV_OFFSET_8822B(x) \ + (((x) & BIT_MASK_AESIV_OFFSET_8822B) << BIT_SHIFT_AESIV_OFFSET_8822B) +#define BITS_AESIV_OFFSET_8822B \ + (BIT_MASK_AESIV_OFFSET_8822B << BIT_SHIFT_AESIV_OFFSET_8822B) +#define BIT_CLEAR_AESIV_OFFSET_8822B(x) ((x) & (~BITS_AESIV_OFFSET_8822B)) +#define BIT_GET_AESIV_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_AESIV_OFFSET_8822B) & BIT_MASK_AESIV_OFFSET_8822B) +#define BIT_SET_AESIV_OFFSET_8822B(x, v) \ + (BIT_CLEAR_AESIV_OFFSET_8822B(x) | BIT_AESIV_OFFSET_8822B(v)) /* 2 REG_BF0_TIME_SETTING_8822B */ #define BIT_BF0_TIMER_SET_8822B BIT(31) @@ -6600,17 +10213,30 @@ #define BIT_SHIFT_BF0_PRETIME_OVER_8822B 16 #define BIT_MASK_BF0_PRETIME_OVER_8822B 0xfff -#define BIT_BF0_PRETIME_OVER_8822B(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8822B) << BIT_SHIFT_BF0_PRETIME_OVER_8822B) -#define BIT_GET_BF0_PRETIME_OVER_8822B(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822B) & BIT_MASK_BF0_PRETIME_OVER_8822B) - - +#define BIT_BF0_PRETIME_OVER_8822B(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER_8822B) \ + << BIT_SHIFT_BF0_PRETIME_OVER_8822B) +#define BITS_BF0_PRETIME_OVER_8822B \ + (BIT_MASK_BF0_PRETIME_OVER_8822B << BIT_SHIFT_BF0_PRETIME_OVER_8822B) +#define BIT_CLEAR_BF0_PRETIME_OVER_8822B(x) \ + ((x) & (~BITS_BF0_PRETIME_OVER_8822B)) +#define BIT_GET_BF0_PRETIME_OVER_8822B(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822B) & \ + BIT_MASK_BF0_PRETIME_OVER_8822B) +#define BIT_SET_BF0_PRETIME_OVER_8822B(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER_8822B(x) | BIT_BF0_PRETIME_OVER_8822B(v)) #define BIT_SHIFT_BF0_LIFETIME_8822B 0 #define BIT_MASK_BF0_LIFETIME_8822B 0xffff -#define BIT_BF0_LIFETIME_8822B(x) (((x) & BIT_MASK_BF0_LIFETIME_8822B) << BIT_SHIFT_BF0_LIFETIME_8822B) -#define BIT_GET_BF0_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8822B) & BIT_MASK_BF0_LIFETIME_8822B) - - +#define BIT_BF0_LIFETIME_8822B(x) \ + (((x) & BIT_MASK_BF0_LIFETIME_8822B) << BIT_SHIFT_BF0_LIFETIME_8822B) +#define BITS_BF0_LIFETIME_8822B \ + (BIT_MASK_BF0_LIFETIME_8822B << BIT_SHIFT_BF0_LIFETIME_8822B) +#define BIT_CLEAR_BF0_LIFETIME_8822B(x) ((x) & (~BITS_BF0_LIFETIME_8822B)) +#define BIT_GET_BF0_LIFETIME_8822B(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME_8822B) & BIT_MASK_BF0_LIFETIME_8822B) +#define BIT_SET_BF0_LIFETIME_8822B(x, v) \ + (BIT_CLEAR_BF0_LIFETIME_8822B(x) | BIT_BF0_LIFETIME_8822B(v)) /* 2 REG_BF1_TIME_SETTING_8822B */ #define BIT_BF1_TIMER_SET_8822B BIT(31) @@ -6620,17 +10246,30 @@ #define BIT_SHIFT_BF1_PRETIME_OVER_8822B 16 #define BIT_MASK_BF1_PRETIME_OVER_8822B 0xfff -#define BIT_BF1_PRETIME_OVER_8822B(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8822B) << BIT_SHIFT_BF1_PRETIME_OVER_8822B) -#define BIT_GET_BF1_PRETIME_OVER_8822B(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822B) & BIT_MASK_BF1_PRETIME_OVER_8822B) - - +#define BIT_BF1_PRETIME_OVER_8822B(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER_8822B) \ + << BIT_SHIFT_BF1_PRETIME_OVER_8822B) +#define BITS_BF1_PRETIME_OVER_8822B \ + (BIT_MASK_BF1_PRETIME_OVER_8822B << BIT_SHIFT_BF1_PRETIME_OVER_8822B) +#define BIT_CLEAR_BF1_PRETIME_OVER_8822B(x) \ + ((x) & (~BITS_BF1_PRETIME_OVER_8822B)) +#define BIT_GET_BF1_PRETIME_OVER_8822B(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822B) & \ + BIT_MASK_BF1_PRETIME_OVER_8822B) +#define BIT_SET_BF1_PRETIME_OVER_8822B(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER_8822B(x) | BIT_BF1_PRETIME_OVER_8822B(v)) #define BIT_SHIFT_BF1_LIFETIME_8822B 0 #define BIT_MASK_BF1_LIFETIME_8822B 0xffff -#define BIT_BF1_LIFETIME_8822B(x) (((x) & BIT_MASK_BF1_LIFETIME_8822B) << BIT_SHIFT_BF1_LIFETIME_8822B) -#define BIT_GET_BF1_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8822B) & BIT_MASK_BF1_LIFETIME_8822B) - - +#define BIT_BF1_LIFETIME_8822B(x) \ + (((x) & BIT_MASK_BF1_LIFETIME_8822B) << BIT_SHIFT_BF1_LIFETIME_8822B) +#define BITS_BF1_LIFETIME_8822B \ + (BIT_MASK_BF1_LIFETIME_8822B << BIT_SHIFT_BF1_LIFETIME_8822B) +#define BIT_CLEAR_BF1_LIFETIME_8822B(x) ((x) & (~BITS_BF1_LIFETIME_8822B)) +#define BIT_GET_BF1_LIFETIME_8822B(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME_8822B) & BIT_MASK_BF1_LIFETIME_8822B) +#define BIT_SET_BF1_LIFETIME_8822B(x, v) \ + (BIT_CLEAR_BF1_LIFETIME_8822B(x) | BIT_BF1_LIFETIME_8822B(v)) /* 2 REG_BF_TIMEOUT_EN_8822B */ #define BIT_EN_VHT_LDPC_8822B BIT(9) @@ -6642,214 +10281,434 @@ #define BIT_SHIFT_MACID31_0_RELEASE_8822B 0 #define BIT_MASK_MACID31_0_RELEASE_8822B 0xffffffffL -#define BIT_MACID31_0_RELEASE_8822B(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8822B) << BIT_SHIFT_MACID31_0_RELEASE_8822B) -#define BIT_GET_MACID31_0_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822B) & BIT_MASK_MACID31_0_RELEASE_8822B) - - +#define BIT_MACID31_0_RELEASE_8822B(x) \ + (((x) & BIT_MASK_MACID31_0_RELEASE_8822B) \ + << BIT_SHIFT_MACID31_0_RELEASE_8822B) +#define BITS_MACID31_0_RELEASE_8822B \ + (BIT_MASK_MACID31_0_RELEASE_8822B << BIT_SHIFT_MACID31_0_RELEASE_8822B) +#define BIT_CLEAR_MACID31_0_RELEASE_8822B(x) \ + ((x) & (~BITS_MACID31_0_RELEASE_8822B)) +#define BIT_GET_MACID31_0_RELEASE_8822B(x) \ + (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822B) & \ + BIT_MASK_MACID31_0_RELEASE_8822B) +#define BIT_SET_MACID31_0_RELEASE_8822B(x, v) \ + (BIT_CLEAR_MACID31_0_RELEASE_8822B(x) | BIT_MACID31_0_RELEASE_8822B(v)) /* 2 REG_MACID_RELEASE1_8822B */ #define BIT_SHIFT_MACID63_32_RELEASE_8822B 0 #define BIT_MASK_MACID63_32_RELEASE_8822B 0xffffffffL -#define BIT_MACID63_32_RELEASE_8822B(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8822B) << BIT_SHIFT_MACID63_32_RELEASE_8822B) -#define BIT_GET_MACID63_32_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822B) & BIT_MASK_MACID63_32_RELEASE_8822B) - - +#define BIT_MACID63_32_RELEASE_8822B(x) \ + (((x) & BIT_MASK_MACID63_32_RELEASE_8822B) \ + << BIT_SHIFT_MACID63_32_RELEASE_8822B) +#define BITS_MACID63_32_RELEASE_8822B \ + (BIT_MASK_MACID63_32_RELEASE_8822B \ + << BIT_SHIFT_MACID63_32_RELEASE_8822B) +#define BIT_CLEAR_MACID63_32_RELEASE_8822B(x) \ + ((x) & (~BITS_MACID63_32_RELEASE_8822B)) +#define BIT_GET_MACID63_32_RELEASE_8822B(x) \ + (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822B) & \ + BIT_MASK_MACID63_32_RELEASE_8822B) +#define BIT_SET_MACID63_32_RELEASE_8822B(x, v) \ + (BIT_CLEAR_MACID63_32_RELEASE_8822B(x) | \ + BIT_MACID63_32_RELEASE_8822B(v)) /* 2 REG_MACID_RELEASE2_8822B */ #define BIT_SHIFT_MACID95_64_RELEASE_8822B 0 #define BIT_MASK_MACID95_64_RELEASE_8822B 0xffffffffL -#define BIT_MACID95_64_RELEASE_8822B(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8822B) << BIT_SHIFT_MACID95_64_RELEASE_8822B) -#define BIT_GET_MACID95_64_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822B) & BIT_MASK_MACID95_64_RELEASE_8822B) - - +#define BIT_MACID95_64_RELEASE_8822B(x) \ + (((x) & BIT_MASK_MACID95_64_RELEASE_8822B) \ + << BIT_SHIFT_MACID95_64_RELEASE_8822B) +#define BITS_MACID95_64_RELEASE_8822B \ + (BIT_MASK_MACID95_64_RELEASE_8822B \ + << BIT_SHIFT_MACID95_64_RELEASE_8822B) +#define BIT_CLEAR_MACID95_64_RELEASE_8822B(x) \ + ((x) & (~BITS_MACID95_64_RELEASE_8822B)) +#define BIT_GET_MACID95_64_RELEASE_8822B(x) \ + (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822B) & \ + BIT_MASK_MACID95_64_RELEASE_8822B) +#define BIT_SET_MACID95_64_RELEASE_8822B(x, v) \ + (BIT_CLEAR_MACID95_64_RELEASE_8822B(x) | \ + BIT_MACID95_64_RELEASE_8822B(v)) /* 2 REG_MACID_RELEASE3_8822B */ #define BIT_SHIFT_MACID127_96_RELEASE_8822B 0 #define BIT_MASK_MACID127_96_RELEASE_8822B 0xffffffffL -#define BIT_MACID127_96_RELEASE_8822B(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8822B) << BIT_SHIFT_MACID127_96_RELEASE_8822B) -#define BIT_GET_MACID127_96_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822B) & BIT_MASK_MACID127_96_RELEASE_8822B) - - +#define BIT_MACID127_96_RELEASE_8822B(x) \ + (((x) & BIT_MASK_MACID127_96_RELEASE_8822B) \ + << BIT_SHIFT_MACID127_96_RELEASE_8822B) +#define BITS_MACID127_96_RELEASE_8822B \ + (BIT_MASK_MACID127_96_RELEASE_8822B \ + << BIT_SHIFT_MACID127_96_RELEASE_8822B) +#define BIT_CLEAR_MACID127_96_RELEASE_8822B(x) \ + ((x) & (~BITS_MACID127_96_RELEASE_8822B)) +#define BIT_GET_MACID127_96_RELEASE_8822B(x) \ + (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822B) & \ + BIT_MASK_MACID127_96_RELEASE_8822B) +#define BIT_SET_MACID127_96_RELEASE_8822B(x, v) \ + (BIT_CLEAR_MACID127_96_RELEASE_8822B(x) | \ + BIT_MACID127_96_RELEASE_8822B(v)) /* 2 REG_MACID_RELEASE_SETTING_8822B */ #define BIT_MACID_VALUE_8822B BIT(7) #define BIT_SHIFT_MACID_OFFSET_8822B 0 #define BIT_MASK_MACID_OFFSET_8822B 0x7f -#define BIT_MACID_OFFSET_8822B(x) (((x) & BIT_MASK_MACID_OFFSET_8822B) << BIT_SHIFT_MACID_OFFSET_8822B) -#define BIT_GET_MACID_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8822B) & BIT_MASK_MACID_OFFSET_8822B) - - +#define BIT_MACID_OFFSET_8822B(x) \ + (((x) & BIT_MASK_MACID_OFFSET_8822B) << BIT_SHIFT_MACID_OFFSET_8822B) +#define BITS_MACID_OFFSET_8822B \ + (BIT_MASK_MACID_OFFSET_8822B << BIT_SHIFT_MACID_OFFSET_8822B) +#define BIT_CLEAR_MACID_OFFSET_8822B(x) ((x) & (~BITS_MACID_OFFSET_8822B)) +#define BIT_GET_MACID_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_MACID_OFFSET_8822B) & BIT_MASK_MACID_OFFSET_8822B) +#define BIT_SET_MACID_OFFSET_8822B(x, v) \ + (BIT_CLEAR_MACID_OFFSET_8822B(x) | BIT_MACID_OFFSET_8822B(v)) /* 2 REG_FAST_EDCA_VOVI_SETTING_8822B */ #define BIT_SHIFT_VI_FAST_EDCA_TO_8822B 24 #define BIT_MASK_VI_FAST_EDCA_TO_8822B 0xff -#define BIT_VI_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8822B) << BIT_SHIFT_VI_FAST_EDCA_TO_8822B) -#define BIT_GET_VI_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822B) & BIT_MASK_VI_FAST_EDCA_TO_8822B) - +#define BIT_VI_FAST_EDCA_TO_8822B(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO_8822B) \ + << BIT_SHIFT_VI_FAST_EDCA_TO_8822B) +#define BITS_VI_FAST_EDCA_TO_8822B \ + (BIT_MASK_VI_FAST_EDCA_TO_8822B << BIT_SHIFT_VI_FAST_EDCA_TO_8822B) +#define BIT_CLEAR_VI_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8822B)) +#define BIT_GET_VI_FAST_EDCA_TO_8822B(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822B) & \ + BIT_MASK_VI_FAST_EDCA_TO_8822B) +#define BIT_SET_VI_FAST_EDCA_TO_8822B(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO_8822B(x) | BIT_VI_FAST_EDCA_TO_8822B(v)) #define BIT_VI_THRESHOLD_SEL_8822B BIT(23) #define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B 16 #define BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B 0x7f -#define BIT_VI_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) -#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) - - +#define BIT_VI_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) +#define BITS_VI_FAST_EDCA_PKT_TH_8822B \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822B(x) \ + ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8822B)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) & \ + BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) +#define BIT_SET_VI_FAST_EDCA_PKT_TH_8822B(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822B(x) | \ + BIT_VI_FAST_EDCA_PKT_TH_8822B(v)) #define BIT_SHIFT_VO_FAST_EDCA_TO_8822B 8 #define BIT_MASK_VO_FAST_EDCA_TO_8822B 0xff -#define BIT_VO_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8822B) << BIT_SHIFT_VO_FAST_EDCA_TO_8822B) -#define BIT_GET_VO_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822B) & BIT_MASK_VO_FAST_EDCA_TO_8822B) - +#define BIT_VO_FAST_EDCA_TO_8822B(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO_8822B) \ + << BIT_SHIFT_VO_FAST_EDCA_TO_8822B) +#define BITS_VO_FAST_EDCA_TO_8822B \ + (BIT_MASK_VO_FAST_EDCA_TO_8822B << BIT_SHIFT_VO_FAST_EDCA_TO_8822B) +#define BIT_CLEAR_VO_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8822B)) +#define BIT_GET_VO_FAST_EDCA_TO_8822B(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822B) & \ + BIT_MASK_VO_FAST_EDCA_TO_8822B) +#define BIT_SET_VO_FAST_EDCA_TO_8822B(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO_8822B(x) | BIT_VO_FAST_EDCA_TO_8822B(v)) #define BIT_VO_THRESHOLD_SEL_8822B BIT(7) #define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B 0 #define BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B 0x7f -#define BIT_VO_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) -#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) - - +#define BIT_VO_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) +#define BITS_VO_FAST_EDCA_PKT_TH_8822B \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822B(x) \ + ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8822B)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) & \ + BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) +#define BIT_SET_VO_FAST_EDCA_PKT_TH_8822B(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822B(x) | \ + BIT_VO_FAST_EDCA_PKT_TH_8822B(v)) /* 2 REG_FAST_EDCA_BEBK_SETTING_8822B */ #define BIT_SHIFT_BK_FAST_EDCA_TO_8822B 24 #define BIT_MASK_BK_FAST_EDCA_TO_8822B 0xff -#define BIT_BK_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8822B) << BIT_SHIFT_BK_FAST_EDCA_TO_8822B) -#define BIT_GET_BK_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822B) & BIT_MASK_BK_FAST_EDCA_TO_8822B) - +#define BIT_BK_FAST_EDCA_TO_8822B(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO_8822B) \ + << BIT_SHIFT_BK_FAST_EDCA_TO_8822B) +#define BITS_BK_FAST_EDCA_TO_8822B \ + (BIT_MASK_BK_FAST_EDCA_TO_8822B << BIT_SHIFT_BK_FAST_EDCA_TO_8822B) +#define BIT_CLEAR_BK_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8822B)) +#define BIT_GET_BK_FAST_EDCA_TO_8822B(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822B) & \ + BIT_MASK_BK_FAST_EDCA_TO_8822B) +#define BIT_SET_BK_FAST_EDCA_TO_8822B(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO_8822B(x) | BIT_BK_FAST_EDCA_TO_8822B(v)) #define BIT_BK_THRESHOLD_SEL_8822B BIT(23) #define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B 16 #define BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B 0x7f -#define BIT_BK_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) -#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) - - +#define BIT_BK_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) +#define BITS_BK_FAST_EDCA_PKT_TH_8822B \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822B(x) \ + ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8822B)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) & \ + BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) +#define BIT_SET_BK_FAST_EDCA_PKT_TH_8822B(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822B(x) | \ + BIT_BK_FAST_EDCA_PKT_TH_8822B(v)) #define BIT_SHIFT_BE_FAST_EDCA_TO_8822B 8 #define BIT_MASK_BE_FAST_EDCA_TO_8822B 0xff -#define BIT_BE_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8822B) << BIT_SHIFT_BE_FAST_EDCA_TO_8822B) -#define BIT_GET_BE_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822B) & BIT_MASK_BE_FAST_EDCA_TO_8822B) - +#define BIT_BE_FAST_EDCA_TO_8822B(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO_8822B) \ + << BIT_SHIFT_BE_FAST_EDCA_TO_8822B) +#define BITS_BE_FAST_EDCA_TO_8822B \ + (BIT_MASK_BE_FAST_EDCA_TO_8822B << BIT_SHIFT_BE_FAST_EDCA_TO_8822B) +#define BIT_CLEAR_BE_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8822B)) +#define BIT_GET_BE_FAST_EDCA_TO_8822B(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822B) & \ + BIT_MASK_BE_FAST_EDCA_TO_8822B) +#define BIT_SET_BE_FAST_EDCA_TO_8822B(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO_8822B(x) | BIT_BE_FAST_EDCA_TO_8822B(v)) #define BIT_BE_THRESHOLD_SEL_8822B BIT(7) #define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B 0 #define BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B 0x7f -#define BIT_BE_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) -#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) - - +#define BIT_BE_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) +#define BITS_BE_FAST_EDCA_PKT_TH_8822B \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822B(x) \ + ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8822B)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822B(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) & \ + BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) +#define BIT_SET_BE_FAST_EDCA_PKT_TH_8822B(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822B(x) | \ + BIT_BE_FAST_EDCA_PKT_TH_8822B(v)) /* 2 REG_MACID_DROP0_8822B */ #define BIT_SHIFT_MACID31_0_DROP_8822B 0 #define BIT_MASK_MACID31_0_DROP_8822B 0xffffffffL -#define BIT_MACID31_0_DROP_8822B(x) (((x) & BIT_MASK_MACID31_0_DROP_8822B) << BIT_SHIFT_MACID31_0_DROP_8822B) -#define BIT_GET_MACID31_0_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8822B) & BIT_MASK_MACID31_0_DROP_8822B) - - +#define BIT_MACID31_0_DROP_8822B(x) \ + (((x) & BIT_MASK_MACID31_0_DROP_8822B) \ + << BIT_SHIFT_MACID31_0_DROP_8822B) +#define BITS_MACID31_0_DROP_8822B \ + (BIT_MASK_MACID31_0_DROP_8822B << BIT_SHIFT_MACID31_0_DROP_8822B) +#define BIT_CLEAR_MACID31_0_DROP_8822B(x) ((x) & (~BITS_MACID31_0_DROP_8822B)) +#define BIT_GET_MACID31_0_DROP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID31_0_DROP_8822B) & \ + BIT_MASK_MACID31_0_DROP_8822B) +#define BIT_SET_MACID31_0_DROP_8822B(x, v) \ + (BIT_CLEAR_MACID31_0_DROP_8822B(x) | BIT_MACID31_0_DROP_8822B(v)) /* 2 REG_MACID_DROP1_8822B */ #define BIT_SHIFT_MACID63_32_DROP_8822B 0 #define BIT_MASK_MACID63_32_DROP_8822B 0xffffffffL -#define BIT_MACID63_32_DROP_8822B(x) (((x) & BIT_MASK_MACID63_32_DROP_8822B) << BIT_SHIFT_MACID63_32_DROP_8822B) -#define BIT_GET_MACID63_32_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8822B) & BIT_MASK_MACID63_32_DROP_8822B) - - +#define BIT_MACID63_32_DROP_8822B(x) \ + (((x) & BIT_MASK_MACID63_32_DROP_8822B) \ + << BIT_SHIFT_MACID63_32_DROP_8822B) +#define BITS_MACID63_32_DROP_8822B \ + (BIT_MASK_MACID63_32_DROP_8822B << BIT_SHIFT_MACID63_32_DROP_8822B) +#define BIT_CLEAR_MACID63_32_DROP_8822B(x) ((x) & (~BITS_MACID63_32_DROP_8822B)) +#define BIT_GET_MACID63_32_DROP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID63_32_DROP_8822B) & \ + BIT_MASK_MACID63_32_DROP_8822B) +#define BIT_SET_MACID63_32_DROP_8822B(x, v) \ + (BIT_CLEAR_MACID63_32_DROP_8822B(x) | BIT_MACID63_32_DROP_8822B(v)) /* 2 REG_MACID_DROP2_8822B */ #define BIT_SHIFT_MACID95_64_DROP_8822B 0 #define BIT_MASK_MACID95_64_DROP_8822B 0xffffffffL -#define BIT_MACID95_64_DROP_8822B(x) (((x) & BIT_MASK_MACID95_64_DROP_8822B) << BIT_SHIFT_MACID95_64_DROP_8822B) -#define BIT_GET_MACID95_64_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8822B) & BIT_MASK_MACID95_64_DROP_8822B) - - +#define BIT_MACID95_64_DROP_8822B(x) \ + (((x) & BIT_MASK_MACID95_64_DROP_8822B) \ + << BIT_SHIFT_MACID95_64_DROP_8822B) +#define BITS_MACID95_64_DROP_8822B \ + (BIT_MASK_MACID95_64_DROP_8822B << BIT_SHIFT_MACID95_64_DROP_8822B) +#define BIT_CLEAR_MACID95_64_DROP_8822B(x) ((x) & (~BITS_MACID95_64_DROP_8822B)) +#define BIT_GET_MACID95_64_DROP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID95_64_DROP_8822B) & \ + BIT_MASK_MACID95_64_DROP_8822B) +#define BIT_SET_MACID95_64_DROP_8822B(x, v) \ + (BIT_CLEAR_MACID95_64_DROP_8822B(x) | BIT_MACID95_64_DROP_8822B(v)) /* 2 REG_MACID_DROP3_8822B */ #define BIT_SHIFT_MACID127_96_DROP_8822B 0 #define BIT_MASK_MACID127_96_DROP_8822B 0xffffffffL -#define BIT_MACID127_96_DROP_8822B(x) (((x) & BIT_MASK_MACID127_96_DROP_8822B) << BIT_SHIFT_MACID127_96_DROP_8822B) -#define BIT_GET_MACID127_96_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8822B) & BIT_MASK_MACID127_96_DROP_8822B) - - +#define BIT_MACID127_96_DROP_8822B(x) \ + (((x) & BIT_MASK_MACID127_96_DROP_8822B) \ + << BIT_SHIFT_MACID127_96_DROP_8822B) +#define BITS_MACID127_96_DROP_8822B \ + (BIT_MASK_MACID127_96_DROP_8822B << BIT_SHIFT_MACID127_96_DROP_8822B) +#define BIT_CLEAR_MACID127_96_DROP_8822B(x) \ + ((x) & (~BITS_MACID127_96_DROP_8822B)) +#define BIT_GET_MACID127_96_DROP_8822B(x) \ + (((x) >> BIT_SHIFT_MACID127_96_DROP_8822B) & \ + BIT_MASK_MACID127_96_DROP_8822B) +#define BIT_SET_MACID127_96_DROP_8822B(x, v) \ + (BIT_CLEAR_MACID127_96_DROP_8822B(x) | BIT_MACID127_96_DROP_8822B(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_0_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) - - +#define BIT_R_MACID_RELEASE_SUCCESS_0_8822B(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) +#define BITS_R_MACID_RELEASE_SUCCESS_0_8822B \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822B(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8822B)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822B(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8822B(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822B(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_0_8822B(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_1_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) - - +#define BIT_R_MACID_RELEASE_SUCCESS_1_8822B(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) +#define BITS_R_MACID_RELEASE_SUCCESS_1_8822B \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822B(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8822B)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822B(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8822B(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822B(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_1_8822B(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_2_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) - - +#define BIT_R_MACID_RELEASE_SUCCESS_2_8822B(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) +#define BITS_R_MACID_RELEASE_SUCCESS_2_8822B \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822B(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8822B)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822B(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8822B(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822B(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_2_8822B(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B 0xffffffffL -#define BIT_R_MACID_RELEASE_SUCCESS_3_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) - - +#define BIT_R_MACID_RELEASE_SUCCESS_3_8822B(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) +#define BITS_R_MACID_RELEASE_SUCCESS_3_8822B \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822B(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8822B)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822B(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8822B(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822B(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_3_8822B(v)) /* 2 REG_MGG_FIFO_CRTL_8822B */ #define BIT_R_MGG_FIFO_EN_8822B BIT(31) #define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B 28 #define BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B 0x7 -#define BIT_R_MGG_FIFO_PG_SIZE_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) -#define BIT_GET_R_MGG_FIFO_PG_SIZE_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) - - +#define BIT_R_MGG_FIFO_PG_SIZE_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) +#define BITS_R_MGG_FIFO_PG_SIZE_8822B \ + (BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B \ + << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) +#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8822B)) +#define BIT_GET_R_MGG_FIFO_PG_SIZE_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) & \ + BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) +#define BIT_SET_R_MGG_FIFO_PG_SIZE_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8822B(x) | \ + BIT_R_MGG_FIFO_PG_SIZE_8822B(v)) #define BIT_SHIFT_R_MGG_FIFO_START_PG_8822B 16 #define BIT_MASK_R_MGG_FIFO_START_PG_8822B 0xfff -#define BIT_R_MGG_FIFO_START_PG_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8822B) << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) -#define BIT_GET_R_MGG_FIFO_START_PG_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) & BIT_MASK_R_MGG_FIFO_START_PG_8822B) - - +#define BIT_R_MGG_FIFO_START_PG_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) +#define BITS_R_MGG_FIFO_START_PG_8822B \ + (BIT_MASK_R_MGG_FIFO_START_PG_8822B \ + << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) +#define BIT_CLEAR_R_MGG_FIFO_START_PG_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_START_PG_8822B)) +#define BIT_GET_R_MGG_FIFO_START_PG_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) & \ + BIT_MASK_R_MGG_FIFO_START_PG_8822B) +#define BIT_SET_R_MGG_FIFO_START_PG_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_START_PG_8822B(x) | \ + BIT_R_MGG_FIFO_START_PG_8822B(v)) #define BIT_SHIFT_R_MGG_FIFO_SIZE_8822B 14 #define BIT_MASK_R_MGG_FIFO_SIZE_8822B 0x3 -#define BIT_R_MGG_FIFO_SIZE_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8822B) << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) -#define BIT_GET_R_MGG_FIFO_SIZE_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) & BIT_MASK_R_MGG_FIFO_SIZE_8822B) - +#define BIT_R_MGG_FIFO_SIZE_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) +#define BITS_R_MGG_FIFO_SIZE_8822B \ + (BIT_MASK_R_MGG_FIFO_SIZE_8822B << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) +#define BIT_CLEAR_R_MGG_FIFO_SIZE_8822B(x) ((x) & (~BITS_R_MGG_FIFO_SIZE_8822B)) +#define BIT_GET_R_MGG_FIFO_SIZE_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) & \ + BIT_MASK_R_MGG_FIFO_SIZE_8822B) +#define BIT_SET_R_MGG_FIFO_SIZE_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_SIZE_8822B(x) | BIT_R_MGG_FIFO_SIZE_8822B(v)) #define BIT_R_MGG_FIFO_PAUSE_8822B BIT(13) #define BIT_SHIFT_R_MGG_FIFO_RPTR_8822B 8 #define BIT_MASK_R_MGG_FIFO_RPTR_8822B 0x1f -#define BIT_R_MGG_FIFO_RPTR_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8822B) << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) -#define BIT_GET_R_MGG_FIFO_RPTR_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) & BIT_MASK_R_MGG_FIFO_RPTR_8822B) - +#define BIT_R_MGG_FIFO_RPTR_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) +#define BITS_R_MGG_FIFO_RPTR_8822B \ + (BIT_MASK_R_MGG_FIFO_RPTR_8822B << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) +#define BIT_CLEAR_R_MGG_FIFO_RPTR_8822B(x) ((x) & (~BITS_R_MGG_FIFO_RPTR_8822B)) +#define BIT_GET_R_MGG_FIFO_RPTR_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) & \ + BIT_MASK_R_MGG_FIFO_RPTR_8822B) +#define BIT_SET_R_MGG_FIFO_RPTR_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_RPTR_8822B(x) | BIT_R_MGG_FIFO_RPTR_8822B(v)) #define BIT_R_MGG_FIFO_OV_8822B BIT(7) #define BIT_R_MGG_FIFO_WPTR_ERROR_8822B BIT(6) @@ -6857,70 +10716,305 @@ #define BIT_SHIFT_R_MGG_FIFO_WPTR_8822B 0 #define BIT_MASK_R_MGG_FIFO_WPTR_8822B 0x1f -#define BIT_R_MGG_FIFO_WPTR_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8822B) << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) -#define BIT_GET_R_MGG_FIFO_WPTR_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) & BIT_MASK_R_MGG_FIFO_WPTR_8822B) - - +#define BIT_R_MGG_FIFO_WPTR_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) +#define BITS_R_MGG_FIFO_WPTR_8822B \ + (BIT_MASK_R_MGG_FIFO_WPTR_8822B << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) +#define BIT_CLEAR_R_MGG_FIFO_WPTR_8822B(x) ((x) & (~BITS_R_MGG_FIFO_WPTR_8822B)) +#define BIT_GET_R_MGG_FIFO_WPTR_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) & \ + BIT_MASK_R_MGG_FIFO_WPTR_8822B) +#define BIT_SET_R_MGG_FIFO_WPTR_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_WPTR_8822B(x) | BIT_R_MGG_FIFO_WPTR_8822B(v)) /* 2 REG_MGG_FIFO_INT_8822B */ #define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B 16 #define BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B 0xffff -#define BIT_R_MGG_FIFO_INT_FLAG_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) -#define BIT_GET_R_MGG_FIFO_INT_FLAG_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) - - +#define BIT_R_MGG_FIFO_INT_FLAG_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) +#define BITS_R_MGG_FIFO_INT_FLAG_8822B \ + (BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B \ + << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) +#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8822B)) +#define BIT_GET_R_MGG_FIFO_INT_FLAG_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) & \ + BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) +#define BIT_SET_R_MGG_FIFO_INT_FLAG_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8822B(x) | \ + BIT_R_MGG_FIFO_INT_FLAG_8822B(v)) #define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B 0 #define BIT_MASK_R_MGG_FIFO_INT_MASK_8822B 0xffff -#define BIT_R_MGG_FIFO_INT_MASK_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) -#define BIT_GET_R_MGG_FIFO_INT_MASK_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) - - +#define BIT_R_MGG_FIFO_INT_MASK_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) +#define BITS_R_MGG_FIFO_INT_MASK_8822B \ + (BIT_MASK_R_MGG_FIFO_INT_MASK_8822B \ + << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) +#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_INT_MASK_8822B)) +#define BIT_GET_R_MGG_FIFO_INT_MASK_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) & \ + BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) +#define BIT_SET_R_MGG_FIFO_INT_MASK_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_INT_MASK_8822B(x) | \ + BIT_R_MGG_FIFO_INT_MASK_8822B(v)) /* 2 REG_MGG_FIFO_LIFETIME_8822B */ #define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B 16 #define BIT_MASK_R_MGG_FIFO_LIFETIME_8822B 0xffff -#define BIT_R_MGG_FIFO_LIFETIME_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) -#define BIT_GET_R_MGG_FIFO_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) - - +#define BIT_R_MGG_FIFO_LIFETIME_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) +#define BITS_R_MGG_FIFO_LIFETIME_8822B \ + (BIT_MASK_R_MGG_FIFO_LIFETIME_8822B \ + << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) +#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_LIFETIME_8822B)) +#define BIT_GET_R_MGG_FIFO_LIFETIME_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) & \ + BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) +#define BIT_SET_R_MGG_FIFO_LIFETIME_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_LIFETIME_8822B(x) | \ + BIT_R_MGG_FIFO_LIFETIME_8822B(v)) #define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B 0 #define BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B 0xffff -#define BIT_R_MGG_FIFO_VALID_MAP_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) -#define BIT_GET_R_MGG_FIFO_VALID_MAP_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) - - +#define BIT_R_MGG_FIFO_VALID_MAP_8822B(x) \ + (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) \ + << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) +#define BITS_R_MGG_FIFO_VALID_MAP_8822B \ + (BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B \ + << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) +#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8822B(x) \ + ((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8822B)) +#define BIT_GET_R_MGG_FIFO_VALID_MAP_8822B(x) \ + (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) & \ + BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) +#define BIT_SET_R_MGG_FIFO_VALID_MAP_8822B(x, v) \ + (BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8822B(x) | \ + BIT_R_MGG_FIFO_VALID_MAP_8822B(v)) /* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B */ #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x7f -#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) -#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) +#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(v)) + +/* 2 REG_SHCUT_SETTING_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE0_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE1_8822B */ +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_SHCUT_LLC_OUI0_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_SHCUT_LLC_OUI1_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_SHCUT_LLC_OUI2_8822B */ + +/* 2 REG_NOT_VALID_8822B */ -/* 2 REG_MACID_SHCUT_OFFSET_8822B */ +/* 2 REG_NOT_VALID_8822B */ -#define BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B 0 -#define BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B 0xff -#define BIT_MACID_SHCUT_OFFSET_V1_8822B(x) (((x) & BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B) << BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B) -#define BIT_GET_MACID_SHCUT_OFFSET_V1_8822B(x) (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B) & BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B) +/* 2 REG_NOT_VALID_8822B */ +/* 2 REG_SHCUT_LLC_OUI3_8822B */ +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +/* 2 REG_NOT_VALID_8822B */ /* 2 REG_MU_TX_CTL_8822B */ #define BIT_R_EN_REVERS_GTAB_8822B BIT(6) #define BIT_SHIFT_R_MU_TABLE_VALID_8822B 0 #define BIT_MASK_R_MU_TABLE_VALID_8822B 0x3f -#define BIT_R_MU_TABLE_VALID_8822B(x) (((x) & BIT_MASK_R_MU_TABLE_VALID_8822B) << BIT_SHIFT_R_MU_TABLE_VALID_8822B) -#define BIT_GET_R_MU_TABLE_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) & BIT_MASK_R_MU_TABLE_VALID_8822B) +#define BIT_R_MU_TABLE_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_TABLE_VALID_8822B) \ + << BIT_SHIFT_R_MU_TABLE_VALID_8822B) +#define BITS_R_MU_TABLE_VALID_8822B \ + (BIT_MASK_R_MU_TABLE_VALID_8822B << BIT_SHIFT_R_MU_TABLE_VALID_8822B) +#define BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_TABLE_VALID_8822B)) +#define BIT_GET_R_MU_TABLE_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) & \ + BIT_MASK_R_MU_TABLE_VALID_8822B) +#define BIT_SET_R_MU_TABLE_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) | BIT_R_MU_TABLE_VALID_8822B(v)) +/* 2 REG_MU_STA_GID_VLD_8822B */ +/* 2 REG_NOT_VALID_8822B */ + +#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BITS_R_MU_STA_GTAB_VALID_8822B \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8822B) +#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \ + BIT_R_MU_STA_GTAB_VALID_8822B(v)) + +#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BITS_R_MU_STA_GTAB_VALID_8822B \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8822B) +#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \ + BIT_R_MU_STA_GTAB_VALID_8822B(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_8822B */ + +/* 2 REG_NOT_VALID_8822B */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BITS_R_MU_STA_GTAB_POSITION_8822B \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \ + BIT_R_MU_STA_GTAB_POSITION_8822B(v)) + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BITS_R_MU_STA_GTAB_POSITION_8822B \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \ + BIT_R_MU_STA_GTAB_POSITION_8822B(v)) + +/* 2 REG_MU_TRX_DBG_CNT_8822B */ +#define BIT_MU_DNGCNT_RST_8822B BIT(20) + +#define BIT_SHIFT_MU_DBGCNT_SEL_8822B 16 +#define BIT_MASK_MU_DBGCNT_SEL_8822B 0xf +#define BIT_MU_DBGCNT_SEL_8822B(x) \ + (((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B) +#define BITS_MU_DBGCNT_SEL_8822B \ + (BIT_MASK_MU_DBGCNT_SEL_8822B << BIT_SHIFT_MU_DBGCNT_SEL_8822B) +#define BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) ((x) & (~BITS_MU_DBGCNT_SEL_8822B)) +#define BIT_GET_MU_DBGCNT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B) +#define BIT_SET_MU_DBGCNT_SEL_8822B(x, v) \ + (BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) | BIT_MU_DBGCNT_SEL_8822B(v)) + +#define BIT_SHIFT_MU_DNGCNT_8822B 0 +#define BIT_MASK_MU_DNGCNT_8822B 0xffff +#define BIT_MU_DNGCNT_8822B(x) \ + (((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B) +#define BITS_MU_DNGCNT_8822B \ + (BIT_MASK_MU_DNGCNT_8822B << BIT_SHIFT_MU_DNGCNT_8822B) +#define BIT_CLEAR_MU_DNGCNT_8822B(x) ((x) & (~BITS_MU_DNGCNT_8822B)) +#define BIT_GET_MU_DNGCNT_8822B(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B) +#define BIT_SET_MU_DNGCNT_8822B(x, v) \ + (BIT_CLEAR_MU_DNGCNT_8822B(x) | BIT_MU_DNGCNT_8822B(v)) + +/* 2 REG_MU_TX_CTL_8822B */ +#define BIT_R_EN_REVERS_GTAB_8822B BIT(6) + +#define BIT_SHIFT_R_MU_TABLE_VALID_8822B 0 +#define BIT_MASK_R_MU_TABLE_VALID_8822B 0x3f +#define BIT_R_MU_TABLE_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_TABLE_VALID_8822B) \ + << BIT_SHIFT_R_MU_TABLE_VALID_8822B) +#define BITS_R_MU_TABLE_VALID_8822B \ + (BIT_MASK_R_MU_TABLE_VALID_8822B << BIT_SHIFT_R_MU_TABLE_VALID_8822B) +#define BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_TABLE_VALID_8822B)) +#define BIT_GET_R_MU_TABLE_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) & \ + BIT_MASK_R_MU_TABLE_VALID_8822B) +#define BIT_SET_R_MU_TABLE_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) | BIT_R_MU_TABLE_VALID_8822B(v)) /* 2 REG_MU_STA_GID_VLD_8822B */ @@ -6928,17 +11022,37 @@ #define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0 #define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) -#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) - - +#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BITS_R_MU_STA_GTAB_VALID_8822B \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8822B) +#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \ + BIT_R_MU_STA_GTAB_VALID_8822B(v)) #define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0 #define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL -#define BIT_R_MU_STA_GTAB_VALID_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) -#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) - - +#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BITS_R_MU_STA_GTAB_VALID_8822B \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8822B) +#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \ + BIT_R_MU_STA_GTAB_VALID_8822B(v)) /* 2 REG_MU_STA_USER_POS_INFO_8822B */ @@ -6946,34 +11060,64 @@ #define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0 #define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) - - +#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BITS_R_MU_STA_GTAB_POSITION_8822B \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \ + BIT_R_MU_STA_GTAB_POSITION_8822B(v)) #define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0 #define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL -#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) -#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) - - +#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BITS_R_MU_STA_GTAB_POSITION_8822B \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) +#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \ + BIT_R_MU_STA_GTAB_POSITION_8822B(v)) /* 2 REG_MU_TRX_DBG_CNT_8822B */ #define BIT_MU_DNGCNT_RST_8822B BIT(20) #define BIT_SHIFT_MU_DBGCNT_SEL_8822B 16 #define BIT_MASK_MU_DBGCNT_SEL_8822B 0xf -#define BIT_MU_DBGCNT_SEL_8822B(x) (((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B) -#define BIT_GET_MU_DBGCNT_SEL_8822B(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B) - - +#define BIT_MU_DBGCNT_SEL_8822B(x) \ + (((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B) +#define BITS_MU_DBGCNT_SEL_8822B \ + (BIT_MASK_MU_DBGCNT_SEL_8822B << BIT_SHIFT_MU_DBGCNT_SEL_8822B) +#define BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) ((x) & (~BITS_MU_DBGCNT_SEL_8822B)) +#define BIT_GET_MU_DBGCNT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B) +#define BIT_SET_MU_DBGCNT_SEL_8822B(x, v) \ + (BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) | BIT_MU_DBGCNT_SEL_8822B(v)) #define BIT_SHIFT_MU_DNGCNT_8822B 0 #define BIT_MASK_MU_DNGCNT_8822B 0xffff -#define BIT_MU_DNGCNT_8822B(x) (((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B) -#define BIT_GET_MU_DNGCNT_8822B(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B) - - +#define BIT_MU_DNGCNT_8822B(x) \ + (((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B) +#define BITS_MU_DNGCNT_8822B \ + (BIT_MASK_MU_DNGCNT_8822B << BIT_SHIFT_MU_DNGCNT_8822B) +#define BIT_CLEAR_MU_DNGCNT_8822B(x) ((x) & (~BITS_MU_DNGCNT_8822B)) +#define BIT_GET_MU_DNGCNT_8822B(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B) +#define BIT_SET_MU_DNGCNT_8822B(x, v) \ + (BIT_CLEAR_MU_DNGCNT_8822B(x) | BIT_MU_DNGCNT_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -6981,24 +11125,32 @@ #define BIT_SHIFT_TXOPLIMIT_8822B 16 #define BIT_MASK_TXOPLIMIT_8822B 0x7ff -#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) -#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) - - +#define BIT_TXOPLIMIT_8822B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) +#define BITS_TXOPLIMIT_8822B \ + (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B) +#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B)) +#define BIT_GET_TXOPLIMIT_8822B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) +#define BIT_SET_TXOPLIMIT_8822B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v)) #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) +#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B) +#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B)) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) - - +#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v)) #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) -#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) - - +#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B) +#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B)) +#define BIT_GET_AIFS_8822B(x) \ + (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) +#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v)) /* 2 REG_EDCA_VI_PARAM_8822B */ @@ -7006,24 +11158,32 @@ #define BIT_SHIFT_TXOPLIMIT_8822B 16 #define BIT_MASK_TXOPLIMIT_8822B 0x7ff -#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) -#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) - - +#define BIT_TXOPLIMIT_8822B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) +#define BITS_TXOPLIMIT_8822B \ + (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B) +#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B)) +#define BIT_GET_TXOPLIMIT_8822B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) +#define BIT_SET_TXOPLIMIT_8822B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v)) #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) +#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B) +#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B)) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) - - +#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v)) #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) -#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) - - +#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B) +#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B)) +#define BIT_GET_AIFS_8822B(x) \ + (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) +#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v)) /* 2 REG_EDCA_BE_PARAM_8822B */ @@ -7031,24 +11191,32 @@ #define BIT_SHIFT_TXOPLIMIT_8822B 16 #define BIT_MASK_TXOPLIMIT_8822B 0x7ff -#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) -#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) - - +#define BIT_TXOPLIMIT_8822B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) +#define BITS_TXOPLIMIT_8822B \ + (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B) +#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B)) +#define BIT_GET_TXOPLIMIT_8822B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) +#define BIT_SET_TXOPLIMIT_8822B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v)) #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) +#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B) +#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B)) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) - - +#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v)) #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) -#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) - - +#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B) +#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B)) +#define BIT_GET_AIFS_8822B(x) \ + (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) +#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v)) /* 2 REG_EDCA_BK_PARAM_8822B */ @@ -7056,122 +11224,186 @@ #define BIT_SHIFT_TXOPLIMIT_8822B 16 #define BIT_MASK_TXOPLIMIT_8822B 0x7ff -#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) -#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) - - +#define BIT_TXOPLIMIT_8822B(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B) +#define BITS_TXOPLIMIT_8822B \ + (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B) +#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B)) +#define BIT_GET_TXOPLIMIT_8822B(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B) +#define BIT_SET_TXOPLIMIT_8822B(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v)) #define BIT_SHIFT_CW_8822B 8 #define BIT_MASK_CW_8822B 0xff #define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) +#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B) +#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B)) #define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) - - +#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v)) #define BIT_SHIFT_AIFS_8822B 0 #define BIT_MASK_AIFS_8822B 0xff #define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) -#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) - - +#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B) +#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B)) +#define BIT_GET_AIFS_8822B(x) \ + (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) +#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v)) /* 2 REG_BCNTCFG_8822B */ #define BIT_SHIFT_BCNCW_MAX_8822B 12 #define BIT_MASK_BCNCW_MAX_8822B 0xf -#define BIT_BCNCW_MAX_8822B(x) (((x) & BIT_MASK_BCNCW_MAX_8822B) << BIT_SHIFT_BCNCW_MAX_8822B) -#define BIT_GET_BCNCW_MAX_8822B(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8822B) & BIT_MASK_BCNCW_MAX_8822B) - - +#define BIT_BCNCW_MAX_8822B(x) \ + (((x) & BIT_MASK_BCNCW_MAX_8822B) << BIT_SHIFT_BCNCW_MAX_8822B) +#define BITS_BCNCW_MAX_8822B \ + (BIT_MASK_BCNCW_MAX_8822B << BIT_SHIFT_BCNCW_MAX_8822B) +#define BIT_CLEAR_BCNCW_MAX_8822B(x) ((x) & (~BITS_BCNCW_MAX_8822B)) +#define BIT_GET_BCNCW_MAX_8822B(x) \ + (((x) >> BIT_SHIFT_BCNCW_MAX_8822B) & BIT_MASK_BCNCW_MAX_8822B) +#define BIT_SET_BCNCW_MAX_8822B(x, v) \ + (BIT_CLEAR_BCNCW_MAX_8822B(x) | BIT_BCNCW_MAX_8822B(v)) #define BIT_SHIFT_BCNCW_MIN_8822B 8 #define BIT_MASK_BCNCW_MIN_8822B 0xf -#define BIT_BCNCW_MIN_8822B(x) (((x) & BIT_MASK_BCNCW_MIN_8822B) << BIT_SHIFT_BCNCW_MIN_8822B) -#define BIT_GET_BCNCW_MIN_8822B(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8822B) & BIT_MASK_BCNCW_MIN_8822B) - - +#define BIT_BCNCW_MIN_8822B(x) \ + (((x) & BIT_MASK_BCNCW_MIN_8822B) << BIT_SHIFT_BCNCW_MIN_8822B) +#define BITS_BCNCW_MIN_8822B \ + (BIT_MASK_BCNCW_MIN_8822B << BIT_SHIFT_BCNCW_MIN_8822B) +#define BIT_CLEAR_BCNCW_MIN_8822B(x) ((x) & (~BITS_BCNCW_MIN_8822B)) +#define BIT_GET_BCNCW_MIN_8822B(x) \ + (((x) >> BIT_SHIFT_BCNCW_MIN_8822B) & BIT_MASK_BCNCW_MIN_8822B) +#define BIT_SET_BCNCW_MIN_8822B(x, v) \ + (BIT_CLEAR_BCNCW_MIN_8822B(x) | BIT_BCNCW_MIN_8822B(v)) #define BIT_SHIFT_BCNIFS_8822B 0 #define BIT_MASK_BCNIFS_8822B 0xff -#define BIT_BCNIFS_8822B(x) (((x) & BIT_MASK_BCNIFS_8822B) << BIT_SHIFT_BCNIFS_8822B) -#define BIT_GET_BCNIFS_8822B(x) (((x) >> BIT_SHIFT_BCNIFS_8822B) & BIT_MASK_BCNIFS_8822B) - - +#define BIT_BCNIFS_8822B(x) \ + (((x) & BIT_MASK_BCNIFS_8822B) << BIT_SHIFT_BCNIFS_8822B) +#define BITS_BCNIFS_8822B (BIT_MASK_BCNIFS_8822B << BIT_SHIFT_BCNIFS_8822B) +#define BIT_CLEAR_BCNIFS_8822B(x) ((x) & (~BITS_BCNIFS_8822B)) +#define BIT_GET_BCNIFS_8822B(x) \ + (((x) >> BIT_SHIFT_BCNIFS_8822B) & BIT_MASK_BCNIFS_8822B) +#define BIT_SET_BCNIFS_8822B(x, v) \ + (BIT_CLEAR_BCNIFS_8822B(x) | BIT_BCNIFS_8822B(v)) /* 2 REG_PIFS_8822B */ #define BIT_SHIFT_PIFS_8822B 0 #define BIT_MASK_PIFS_8822B 0xff #define BIT_PIFS_8822B(x) (((x) & BIT_MASK_PIFS_8822B) << BIT_SHIFT_PIFS_8822B) -#define BIT_GET_PIFS_8822B(x) (((x) >> BIT_SHIFT_PIFS_8822B) & BIT_MASK_PIFS_8822B) - - +#define BITS_PIFS_8822B (BIT_MASK_PIFS_8822B << BIT_SHIFT_PIFS_8822B) +#define BIT_CLEAR_PIFS_8822B(x) ((x) & (~BITS_PIFS_8822B)) +#define BIT_GET_PIFS_8822B(x) \ + (((x) >> BIT_SHIFT_PIFS_8822B) & BIT_MASK_PIFS_8822B) +#define BIT_SET_PIFS_8822B(x, v) (BIT_CLEAR_PIFS_8822B(x) | BIT_PIFS_8822B(v)) /* 2 REG_RDG_PIFS_8822B */ #define BIT_SHIFT_RDG_PIFS_8822B 0 #define BIT_MASK_RDG_PIFS_8822B 0xff -#define BIT_RDG_PIFS_8822B(x) (((x) & BIT_MASK_RDG_PIFS_8822B) << BIT_SHIFT_RDG_PIFS_8822B) -#define BIT_GET_RDG_PIFS_8822B(x) (((x) >> BIT_SHIFT_RDG_PIFS_8822B) & BIT_MASK_RDG_PIFS_8822B) - - +#define BIT_RDG_PIFS_8822B(x) \ + (((x) & BIT_MASK_RDG_PIFS_8822B) << BIT_SHIFT_RDG_PIFS_8822B) +#define BITS_RDG_PIFS_8822B \ + (BIT_MASK_RDG_PIFS_8822B << BIT_SHIFT_RDG_PIFS_8822B) +#define BIT_CLEAR_RDG_PIFS_8822B(x) ((x) & (~BITS_RDG_PIFS_8822B)) +#define BIT_GET_RDG_PIFS_8822B(x) \ + (((x) >> BIT_SHIFT_RDG_PIFS_8822B) & BIT_MASK_RDG_PIFS_8822B) +#define BIT_SET_RDG_PIFS_8822B(x, v) \ + (BIT_CLEAR_RDG_PIFS_8822B(x) | BIT_RDG_PIFS_8822B(v)) /* 2 REG_SIFS_8822B */ #define BIT_SHIFT_SIFS_OFDM_TRX_8822B 24 #define BIT_MASK_SIFS_OFDM_TRX_8822B 0xff -#define BIT_SIFS_OFDM_TRX_8822B(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8822B) << BIT_SHIFT_SIFS_OFDM_TRX_8822B) -#define BIT_GET_SIFS_OFDM_TRX_8822B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822B) & BIT_MASK_SIFS_OFDM_TRX_8822B) - - +#define BIT_SIFS_OFDM_TRX_8822B(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX_8822B) << BIT_SHIFT_SIFS_OFDM_TRX_8822B) +#define BITS_SIFS_OFDM_TRX_8822B \ + (BIT_MASK_SIFS_OFDM_TRX_8822B << BIT_SHIFT_SIFS_OFDM_TRX_8822B) +#define BIT_CLEAR_SIFS_OFDM_TRX_8822B(x) ((x) & (~BITS_SIFS_OFDM_TRX_8822B)) +#define BIT_GET_SIFS_OFDM_TRX_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822B) & BIT_MASK_SIFS_OFDM_TRX_8822B) +#define BIT_SET_SIFS_OFDM_TRX_8822B(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX_8822B(x) | BIT_SIFS_OFDM_TRX_8822B(v)) #define BIT_SHIFT_SIFS_CCK_TRX_8822B 16 #define BIT_MASK_SIFS_CCK_TRX_8822B 0xff -#define BIT_SIFS_CCK_TRX_8822B(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8822B) << BIT_SHIFT_SIFS_CCK_TRX_8822B) -#define BIT_GET_SIFS_CCK_TRX_8822B(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822B) & BIT_MASK_SIFS_CCK_TRX_8822B) - - +#define BIT_SIFS_CCK_TRX_8822B(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX_8822B) << BIT_SHIFT_SIFS_CCK_TRX_8822B) +#define BITS_SIFS_CCK_TRX_8822B \ + (BIT_MASK_SIFS_CCK_TRX_8822B << BIT_SHIFT_SIFS_CCK_TRX_8822B) +#define BIT_CLEAR_SIFS_CCK_TRX_8822B(x) ((x) & (~BITS_SIFS_CCK_TRX_8822B)) +#define BIT_GET_SIFS_CCK_TRX_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822B) & BIT_MASK_SIFS_CCK_TRX_8822B) +#define BIT_SET_SIFS_CCK_TRX_8822B(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX_8822B(x) | BIT_SIFS_CCK_TRX_8822B(v)) #define BIT_SHIFT_SIFS_OFDM_CTX_8822B 8 #define BIT_MASK_SIFS_OFDM_CTX_8822B 0xff -#define BIT_SIFS_OFDM_CTX_8822B(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8822B) << BIT_SHIFT_SIFS_OFDM_CTX_8822B) -#define BIT_GET_SIFS_OFDM_CTX_8822B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822B) & BIT_MASK_SIFS_OFDM_CTX_8822B) - - +#define BIT_SIFS_OFDM_CTX_8822B(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX_8822B) << BIT_SHIFT_SIFS_OFDM_CTX_8822B) +#define BITS_SIFS_OFDM_CTX_8822B \ + (BIT_MASK_SIFS_OFDM_CTX_8822B << BIT_SHIFT_SIFS_OFDM_CTX_8822B) +#define BIT_CLEAR_SIFS_OFDM_CTX_8822B(x) ((x) & (~BITS_SIFS_OFDM_CTX_8822B)) +#define BIT_GET_SIFS_OFDM_CTX_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822B) & BIT_MASK_SIFS_OFDM_CTX_8822B) +#define BIT_SET_SIFS_OFDM_CTX_8822B(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX_8822B(x) | BIT_SIFS_OFDM_CTX_8822B(v)) #define BIT_SHIFT_SIFS_CCK_CTX_8822B 0 #define BIT_MASK_SIFS_CCK_CTX_8822B 0xff -#define BIT_SIFS_CCK_CTX_8822B(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8822B) << BIT_SHIFT_SIFS_CCK_CTX_8822B) -#define BIT_GET_SIFS_CCK_CTX_8822B(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822B) & BIT_MASK_SIFS_CCK_CTX_8822B) - - +#define BIT_SIFS_CCK_CTX_8822B(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX_8822B) << BIT_SHIFT_SIFS_CCK_CTX_8822B) +#define BITS_SIFS_CCK_CTX_8822B \ + (BIT_MASK_SIFS_CCK_CTX_8822B << BIT_SHIFT_SIFS_CCK_CTX_8822B) +#define BIT_CLEAR_SIFS_CCK_CTX_8822B(x) ((x) & (~BITS_SIFS_CCK_CTX_8822B)) +#define BIT_GET_SIFS_CCK_CTX_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822B) & BIT_MASK_SIFS_CCK_CTX_8822B) +#define BIT_SET_SIFS_CCK_CTX_8822B(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX_8822B(x) | BIT_SIFS_CCK_CTX_8822B(v)) /* 2 REG_TSFTR_SYN_OFFSET_8822B */ #define BIT_SHIFT_TSFTR_SNC_OFFSET_8822B 0 #define BIT_MASK_TSFTR_SNC_OFFSET_8822B 0xffff -#define BIT_TSFTR_SNC_OFFSET_8822B(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822B) << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) -#define BIT_GET_TSFTR_SNC_OFFSET_8822B(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) & BIT_MASK_TSFTR_SNC_OFFSET_8822B) - - +#define BIT_TSFTR_SNC_OFFSET_8822B(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822B) \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) +#define BITS_TSFTR_SNC_OFFSET_8822B \ + (BIT_MASK_TSFTR_SNC_OFFSET_8822B << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_8822B(x) \ + ((x) & (~BITS_TSFTR_SNC_OFFSET_8822B)) +#define BIT_GET_TSFTR_SNC_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) & \ + BIT_MASK_TSFTR_SNC_OFFSET_8822B) +#define BIT_SET_TSFTR_SNC_OFFSET_8822B(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_8822B(x) | BIT_TSFTR_SNC_OFFSET_8822B(v)) /* 2 REG_AGGR_BREAK_TIME_8822B */ #define BIT_SHIFT_AGGR_BK_TIME_8822B 0 #define BIT_MASK_AGGR_BK_TIME_8822B 0xff -#define BIT_AGGR_BK_TIME_8822B(x) (((x) & BIT_MASK_AGGR_BK_TIME_8822B) << BIT_SHIFT_AGGR_BK_TIME_8822B) -#define BIT_GET_AGGR_BK_TIME_8822B(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8822B) & BIT_MASK_AGGR_BK_TIME_8822B) - - +#define BIT_AGGR_BK_TIME_8822B(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME_8822B) << BIT_SHIFT_AGGR_BK_TIME_8822B) +#define BITS_AGGR_BK_TIME_8822B \ + (BIT_MASK_AGGR_BK_TIME_8822B << BIT_SHIFT_AGGR_BK_TIME_8822B) +#define BIT_CLEAR_AGGR_BK_TIME_8822B(x) ((x) & (~BITS_AGGR_BK_TIME_8822B)) +#define BIT_GET_AGGR_BK_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME_8822B) & BIT_MASK_AGGR_BK_TIME_8822B) +#define BIT_SET_AGGR_BK_TIME_8822B(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME_8822B(x) | BIT_AGGR_BK_TIME_8822B(v)) /* 2 REG_SLOT_8822B */ #define BIT_SHIFT_SLOT_8822B 0 #define BIT_MASK_SLOT_8822B 0xff #define BIT_SLOT_8822B(x) (((x) & BIT_MASK_SLOT_8822B) << BIT_SHIFT_SLOT_8822B) -#define BIT_GET_SLOT_8822B(x) (((x) >> BIT_SHIFT_SLOT_8822B) & BIT_MASK_SLOT_8822B) - - +#define BITS_SLOT_8822B (BIT_MASK_SLOT_8822B << BIT_SHIFT_SLOT_8822B) +#define BIT_CLEAR_SLOT_8822B(x) ((x) & (~BITS_SLOT_8822B)) +#define BIT_GET_SLOT_8822B(x) \ + (((x) >> BIT_SHIFT_SLOT_8822B) & BIT_MASK_SLOT_8822B) +#define BIT_SET_SLOT_8822B(x, v) (BIT_CLEAR_SLOT_8822B(x) | BIT_SLOT_8822B(v)) /* 2 REG_TX_PTCL_CTRL_8822B */ #define BIT_DIS_EDCCA_8822B BIT(15) @@ -7181,9 +11413,15 @@ #define BIT_SHIFT_TXQ_NAV_MSK_8822B 8 #define BIT_MASK_TXQ_NAV_MSK_8822B 0xf -#define BIT_TXQ_NAV_MSK_8822B(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8822B) << BIT_SHIFT_TXQ_NAV_MSK_8822B) -#define BIT_GET_TXQ_NAV_MSK_8822B(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822B) & BIT_MASK_TXQ_NAV_MSK_8822B) - +#define BIT_TXQ_NAV_MSK_8822B(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK_8822B) << BIT_SHIFT_TXQ_NAV_MSK_8822B) +#define BITS_TXQ_NAV_MSK_8822B \ + (BIT_MASK_TXQ_NAV_MSK_8822B << BIT_SHIFT_TXQ_NAV_MSK_8822B) +#define BIT_CLEAR_TXQ_NAV_MSK_8822B(x) ((x) & (~BITS_TXQ_NAV_MSK_8822B)) +#define BIT_GET_TXQ_NAV_MSK_8822B(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822B) & BIT_MASK_TXQ_NAV_MSK_8822B) +#define BIT_SET_TXQ_NAV_MSK_8822B(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK_8822B(x) | BIT_TXQ_NAV_MSK_8822B(v)) #define BIT_DIS_CW_8822B BIT(7) #define BIT_NAV_END_TXOP_8822B BIT(6) @@ -7259,17 +11497,29 @@ #define BIT_SHIFT_CCA_FILTER_THRS_8822B 8 #define BIT_MASK_CCA_FILTER_THRS_8822B 0xff -#define BIT_CCA_FILTER_THRS_8822B(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8822B) << BIT_SHIFT_CCA_FILTER_THRS_8822B) -#define BIT_GET_CCA_FILTER_THRS_8822B(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822B) & BIT_MASK_CCA_FILTER_THRS_8822B) - - +#define BIT_CCA_FILTER_THRS_8822B(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS_8822B) \ + << BIT_SHIFT_CCA_FILTER_THRS_8822B) +#define BITS_CCA_FILTER_THRS_8822B \ + (BIT_MASK_CCA_FILTER_THRS_8822B << BIT_SHIFT_CCA_FILTER_THRS_8822B) +#define BIT_CLEAR_CCA_FILTER_THRS_8822B(x) ((x) & (~BITS_CCA_FILTER_THRS_8822B)) +#define BIT_GET_CCA_FILTER_THRS_8822B(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822B) & \ + BIT_MASK_CCA_FILTER_THRS_8822B) +#define BIT_SET_CCA_FILTER_THRS_8822B(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS_8822B(x) | BIT_CCA_FILTER_THRS_8822B(v)) #define BIT_SHIFT_EDCCA_THRS_8822B 0 #define BIT_MASK_EDCCA_THRS_8822B 0xff -#define BIT_EDCCA_THRS_8822B(x) (((x) & BIT_MASK_EDCCA_THRS_8822B) << BIT_SHIFT_EDCCA_THRS_8822B) -#define BIT_GET_EDCCA_THRS_8822B(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8822B) & BIT_MASK_EDCCA_THRS_8822B) - - +#define BIT_EDCCA_THRS_8822B(x) \ + (((x) & BIT_MASK_EDCCA_THRS_8822B) << BIT_SHIFT_EDCCA_THRS_8822B) +#define BITS_EDCCA_THRS_8822B \ + (BIT_MASK_EDCCA_THRS_8822B << BIT_SHIFT_EDCCA_THRS_8822B) +#define BIT_CLEAR_EDCCA_THRS_8822B(x) ((x) & (~BITS_EDCCA_THRS_8822B)) +#define BIT_GET_EDCCA_THRS_8822B(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS_8822B) & BIT_MASK_EDCCA_THRS_8822B) +#define BIT_SET_EDCCA_THRS_8822B(x, v) \ + (BIT_CLEAR_EDCCA_THRS_8822B(x) | BIT_EDCCA_THRS_8822B(v)) /* 2 REG_P2PPS_SPEC_STATE_8822B */ #define BIT_SPEC_POWER_STATE_8822B BIT(7) @@ -7281,93 +11531,240 @@ #define BIT_SPEC_NOA0_OFF_PERIOD_8822B BIT(1) #define BIT_SPEC_FORCE_DOZE0_8822B BIT(0) +/* 2 REG_TXOP_LIMIT_CTRL_8822B */ + +#define BIT_SHIFT_TXOP_TBTT_CNT_8822B 24 +#define BIT_MASK_TXOP_TBTT_CNT_8822B 0xff +#define BIT_TXOP_TBTT_CNT_8822B(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_8822B) << BIT_SHIFT_TXOP_TBTT_CNT_8822B) +#define BITS_TXOP_TBTT_CNT_8822B \ + (BIT_MASK_TXOP_TBTT_CNT_8822B << BIT_SHIFT_TXOP_TBTT_CNT_8822B) +#define BIT_CLEAR_TXOP_TBTT_CNT_8822B(x) ((x) & (~BITS_TXOP_TBTT_CNT_8822B)) +#define BIT_GET_TXOP_TBTT_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8822B) & BIT_MASK_TXOP_TBTT_CNT_8822B) +#define BIT_SET_TXOP_TBTT_CNT_8822B(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_8822B(x) | BIT_TXOP_TBTT_CNT_8822B(v)) + +#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B 20 +#define BIT_MASK_TXOP_TBTT_CNT_SEL_8822B 0xf +#define BIT_TXOP_TBTT_CNT_SEL_8822B(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8822B) \ + << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B) +#define BITS_TXOP_TBTT_CNT_SEL_8822B \ + (BIT_MASK_TXOP_TBTT_CNT_SEL_8822B << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B) +#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822B(x) \ + ((x) & (~BITS_TXOP_TBTT_CNT_SEL_8822B)) +#define BIT_GET_TXOP_TBTT_CNT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B) & \ + BIT_MASK_TXOP_TBTT_CNT_SEL_8822B) +#define BIT_SET_TXOP_TBTT_CNT_SEL_8822B(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822B(x) | BIT_TXOP_TBTT_CNT_SEL_8822B(v)) + +#define BIT_SHIFT_TXOP_LMT_EN_8822B 16 +#define BIT_MASK_TXOP_LMT_EN_8822B 0xf +#define BIT_TXOP_LMT_EN_8822B(x) \ + (((x) & BIT_MASK_TXOP_LMT_EN_8822B) << BIT_SHIFT_TXOP_LMT_EN_8822B) +#define BITS_TXOP_LMT_EN_8822B \ + (BIT_MASK_TXOP_LMT_EN_8822B << BIT_SHIFT_TXOP_LMT_EN_8822B) +#define BIT_CLEAR_TXOP_LMT_EN_8822B(x) ((x) & (~BITS_TXOP_LMT_EN_8822B)) +#define BIT_GET_TXOP_LMT_EN_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_EN_8822B) & BIT_MASK_TXOP_LMT_EN_8822B) +#define BIT_SET_TXOP_LMT_EN_8822B(x, v) \ + (BIT_CLEAR_TXOP_LMT_EN_8822B(x) | BIT_TXOP_LMT_EN_8822B(v)) + +#define BIT_SHIFT_TXOP_LMT_TX_TIME_8822B 8 +#define BIT_MASK_TXOP_LMT_TX_TIME_8822B 0xff +#define BIT_TXOP_LMT_TX_TIME_8822B(x) \ + (((x) & BIT_MASK_TXOP_LMT_TX_TIME_8822B) \ + << BIT_SHIFT_TXOP_LMT_TX_TIME_8822B) +#define BITS_TXOP_LMT_TX_TIME_8822B \ + (BIT_MASK_TXOP_LMT_TX_TIME_8822B << BIT_SHIFT_TXOP_LMT_TX_TIME_8822B) +#define BIT_CLEAR_TXOP_LMT_TX_TIME_8822B(x) \ + ((x) & (~BITS_TXOP_LMT_TX_TIME_8822B)) +#define BIT_GET_TXOP_LMT_TX_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8822B) & \ + BIT_MASK_TXOP_LMT_TX_TIME_8822B) +#define BIT_SET_TXOP_LMT_TX_TIME_8822B(x, v) \ + (BIT_CLEAR_TXOP_LMT_TX_TIME_8822B(x) | BIT_TXOP_LMT_TX_TIME_8822B(v)) + +#define BIT_TXOP_CNT_TRIGGER_RESET_8822B BIT(7) + +#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B 0 +#define BIT_MASK_TXOP_LMT_PKT_NUM_8822B 0x3f +#define BIT_TXOP_LMT_PKT_NUM_8822B(x) \ + (((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8822B) \ + << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B) +#define BITS_TXOP_LMT_PKT_NUM_8822B \ + (BIT_MASK_TXOP_LMT_PKT_NUM_8822B << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B) +#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8822B(x) \ + ((x) & (~BITS_TXOP_LMT_PKT_NUM_8822B)) +#define BIT_GET_TXOP_LMT_PKT_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B) & \ + BIT_MASK_TXOP_LMT_PKT_NUM_8822B) +#define BIT_SET_TXOP_LMT_PKT_NUM_8822B(x, v) \ + (BIT_CLEAR_TXOP_LMT_PKT_NUM_8822B(x) | BIT_TXOP_LMT_PKT_NUM_8822B(v)) + /* 2 REG_BAR_TX_CTRL_8822B */ -/* 2 REG_NOT_VALID_8822B */ +/* 2 REG_P2PON_DIS_TXTIME_8822B */ #define BIT_SHIFT_P2PON_DIS_TXTIME_8822B 0 #define BIT_MASK_P2PON_DIS_TXTIME_8822B 0xff -#define BIT_P2PON_DIS_TXTIME_8822B(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8822B) << BIT_SHIFT_P2PON_DIS_TXTIME_8822B) -#define BIT_GET_P2PON_DIS_TXTIME_8822B(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822B) & BIT_MASK_P2PON_DIS_TXTIME_8822B) - - +#define BIT_P2PON_DIS_TXTIME_8822B(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME_8822B) \ + << BIT_SHIFT_P2PON_DIS_TXTIME_8822B) +#define BITS_P2PON_DIS_TXTIME_8822B \ + (BIT_MASK_P2PON_DIS_TXTIME_8822B << BIT_SHIFT_P2PON_DIS_TXTIME_8822B) +#define BIT_CLEAR_P2PON_DIS_TXTIME_8822B(x) \ + ((x) & (~BITS_P2PON_DIS_TXTIME_8822B)) +#define BIT_GET_P2PON_DIS_TXTIME_8822B(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822B) & \ + BIT_MASK_P2PON_DIS_TXTIME_8822B) +#define BIT_SET_P2PON_DIS_TXTIME_8822B(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME_8822B(x) | BIT_P2PON_DIS_TXTIME_8822B(v)) /* 2 REG_QUEUE_INCOL_THR_8822B */ #define BIT_SHIFT_BK_QUEUE_THR_8822B 24 #define BIT_MASK_BK_QUEUE_THR_8822B 0xff -#define BIT_BK_QUEUE_THR_8822B(x) (((x) & BIT_MASK_BK_QUEUE_THR_8822B) << BIT_SHIFT_BK_QUEUE_THR_8822B) -#define BIT_GET_BK_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_BK_QUEUE_THR_8822B) & BIT_MASK_BK_QUEUE_THR_8822B) - - +#define BIT_BK_QUEUE_THR_8822B(x) \ + (((x) & BIT_MASK_BK_QUEUE_THR_8822B) << BIT_SHIFT_BK_QUEUE_THR_8822B) +#define BITS_BK_QUEUE_THR_8822B \ + (BIT_MASK_BK_QUEUE_THR_8822B << BIT_SHIFT_BK_QUEUE_THR_8822B) +#define BIT_CLEAR_BK_QUEUE_THR_8822B(x) ((x) & (~BITS_BK_QUEUE_THR_8822B)) +#define BIT_GET_BK_QUEUE_THR_8822B(x) \ + (((x) >> BIT_SHIFT_BK_QUEUE_THR_8822B) & BIT_MASK_BK_QUEUE_THR_8822B) +#define BIT_SET_BK_QUEUE_THR_8822B(x, v) \ + (BIT_CLEAR_BK_QUEUE_THR_8822B(x) | BIT_BK_QUEUE_THR_8822B(v)) #define BIT_SHIFT_BE_QUEUE_THR_8822B 16 #define BIT_MASK_BE_QUEUE_THR_8822B 0xff -#define BIT_BE_QUEUE_THR_8822B(x) (((x) & BIT_MASK_BE_QUEUE_THR_8822B) << BIT_SHIFT_BE_QUEUE_THR_8822B) -#define BIT_GET_BE_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_BE_QUEUE_THR_8822B) & BIT_MASK_BE_QUEUE_THR_8822B) - - +#define BIT_BE_QUEUE_THR_8822B(x) \ + (((x) & BIT_MASK_BE_QUEUE_THR_8822B) << BIT_SHIFT_BE_QUEUE_THR_8822B) +#define BITS_BE_QUEUE_THR_8822B \ + (BIT_MASK_BE_QUEUE_THR_8822B << BIT_SHIFT_BE_QUEUE_THR_8822B) +#define BIT_CLEAR_BE_QUEUE_THR_8822B(x) ((x) & (~BITS_BE_QUEUE_THR_8822B)) +#define BIT_GET_BE_QUEUE_THR_8822B(x) \ + (((x) >> BIT_SHIFT_BE_QUEUE_THR_8822B) & BIT_MASK_BE_QUEUE_THR_8822B) +#define BIT_SET_BE_QUEUE_THR_8822B(x, v) \ + (BIT_CLEAR_BE_QUEUE_THR_8822B(x) | BIT_BE_QUEUE_THR_8822B(v)) #define BIT_SHIFT_VI_QUEUE_THR_8822B 8 #define BIT_MASK_VI_QUEUE_THR_8822B 0xff -#define BIT_VI_QUEUE_THR_8822B(x) (((x) & BIT_MASK_VI_QUEUE_THR_8822B) << BIT_SHIFT_VI_QUEUE_THR_8822B) -#define BIT_GET_VI_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_VI_QUEUE_THR_8822B) & BIT_MASK_VI_QUEUE_THR_8822B) - - +#define BIT_VI_QUEUE_THR_8822B(x) \ + (((x) & BIT_MASK_VI_QUEUE_THR_8822B) << BIT_SHIFT_VI_QUEUE_THR_8822B) +#define BITS_VI_QUEUE_THR_8822B \ + (BIT_MASK_VI_QUEUE_THR_8822B << BIT_SHIFT_VI_QUEUE_THR_8822B) +#define BIT_CLEAR_VI_QUEUE_THR_8822B(x) ((x) & (~BITS_VI_QUEUE_THR_8822B)) +#define BIT_GET_VI_QUEUE_THR_8822B(x) \ + (((x) >> BIT_SHIFT_VI_QUEUE_THR_8822B) & BIT_MASK_VI_QUEUE_THR_8822B) +#define BIT_SET_VI_QUEUE_THR_8822B(x, v) \ + (BIT_CLEAR_VI_QUEUE_THR_8822B(x) | BIT_VI_QUEUE_THR_8822B(v)) #define BIT_SHIFT_VO_QUEUE_THR_8822B 0 #define BIT_MASK_VO_QUEUE_THR_8822B 0xff -#define BIT_VO_QUEUE_THR_8822B(x) (((x) & BIT_MASK_VO_QUEUE_THR_8822B) << BIT_SHIFT_VO_QUEUE_THR_8822B) -#define BIT_GET_VO_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_VO_QUEUE_THR_8822B) & BIT_MASK_VO_QUEUE_THR_8822B) - - +#define BIT_VO_QUEUE_THR_8822B(x) \ + (((x) & BIT_MASK_VO_QUEUE_THR_8822B) << BIT_SHIFT_VO_QUEUE_THR_8822B) +#define BITS_VO_QUEUE_THR_8822B \ + (BIT_MASK_VO_QUEUE_THR_8822B << BIT_SHIFT_VO_QUEUE_THR_8822B) +#define BIT_CLEAR_VO_QUEUE_THR_8822B(x) ((x) & (~BITS_VO_QUEUE_THR_8822B)) +#define BIT_GET_VO_QUEUE_THR_8822B(x) \ + (((x) >> BIT_SHIFT_VO_QUEUE_THR_8822B) & BIT_MASK_VO_QUEUE_THR_8822B) +#define BIT_SET_VO_QUEUE_THR_8822B(x, v) \ + (BIT_CLEAR_VO_QUEUE_THR_8822B(x) | BIT_VO_QUEUE_THR_8822B(v)) /* 2 REG_QUEUE_INCOL_EN_8822B */ #define BIT_QUEUE_INCOL_EN_8822B BIT(16) #define BIT_SHIFT_BE_TRIGGER_NUM_8822B 12 #define BIT_MASK_BE_TRIGGER_NUM_8822B 0xf -#define BIT_BE_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_BE_TRIGGER_NUM_8822B) << BIT_SHIFT_BE_TRIGGER_NUM_8822B) -#define BIT_GET_BE_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_8822B) & BIT_MASK_BE_TRIGGER_NUM_8822B) - - +#define BIT_BE_TRIGGER_NUM_8822B(x) \ + (((x) & BIT_MASK_BE_TRIGGER_NUM_8822B) \ + << BIT_SHIFT_BE_TRIGGER_NUM_8822B) +#define BITS_BE_TRIGGER_NUM_8822B \ + (BIT_MASK_BE_TRIGGER_NUM_8822B << BIT_SHIFT_BE_TRIGGER_NUM_8822B) +#define BIT_CLEAR_BE_TRIGGER_NUM_8822B(x) ((x) & (~BITS_BE_TRIGGER_NUM_8822B)) +#define BIT_GET_BE_TRIGGER_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_8822B) & \ + BIT_MASK_BE_TRIGGER_NUM_8822B) +#define BIT_SET_BE_TRIGGER_NUM_8822B(x, v) \ + (BIT_CLEAR_BE_TRIGGER_NUM_8822B(x) | BIT_BE_TRIGGER_NUM_8822B(v)) #define BIT_SHIFT_BK_TRIGGER_NUM_8822B 8 #define BIT_MASK_BK_TRIGGER_NUM_8822B 0xf -#define BIT_BK_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_BK_TRIGGER_NUM_8822B) << BIT_SHIFT_BK_TRIGGER_NUM_8822B) -#define BIT_GET_BK_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_8822B) & BIT_MASK_BK_TRIGGER_NUM_8822B) - - +#define BIT_BK_TRIGGER_NUM_8822B(x) \ + (((x) & BIT_MASK_BK_TRIGGER_NUM_8822B) \ + << BIT_SHIFT_BK_TRIGGER_NUM_8822B) +#define BITS_BK_TRIGGER_NUM_8822B \ + (BIT_MASK_BK_TRIGGER_NUM_8822B << BIT_SHIFT_BK_TRIGGER_NUM_8822B) +#define BIT_CLEAR_BK_TRIGGER_NUM_8822B(x) ((x) & (~BITS_BK_TRIGGER_NUM_8822B)) +#define BIT_GET_BK_TRIGGER_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_8822B) & \ + BIT_MASK_BK_TRIGGER_NUM_8822B) +#define BIT_SET_BK_TRIGGER_NUM_8822B(x, v) \ + (BIT_CLEAR_BK_TRIGGER_NUM_8822B(x) | BIT_BK_TRIGGER_NUM_8822B(v)) #define BIT_SHIFT_VI_TRIGGER_NUM_8822B 4 #define BIT_MASK_VI_TRIGGER_NUM_8822B 0xf -#define BIT_VI_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_VI_TRIGGER_NUM_8822B) << BIT_SHIFT_VI_TRIGGER_NUM_8822B) -#define BIT_GET_VI_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8822B) & BIT_MASK_VI_TRIGGER_NUM_8822B) - - +#define BIT_VI_TRIGGER_NUM_8822B(x) \ + (((x) & BIT_MASK_VI_TRIGGER_NUM_8822B) \ + << BIT_SHIFT_VI_TRIGGER_NUM_8822B) +#define BITS_VI_TRIGGER_NUM_8822B \ + (BIT_MASK_VI_TRIGGER_NUM_8822B << BIT_SHIFT_VI_TRIGGER_NUM_8822B) +#define BIT_CLEAR_VI_TRIGGER_NUM_8822B(x) ((x) & (~BITS_VI_TRIGGER_NUM_8822B)) +#define BIT_GET_VI_TRIGGER_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8822B) & \ + BIT_MASK_VI_TRIGGER_NUM_8822B) +#define BIT_SET_VI_TRIGGER_NUM_8822B(x, v) \ + (BIT_CLEAR_VI_TRIGGER_NUM_8822B(x) | BIT_VI_TRIGGER_NUM_8822B(v)) #define BIT_SHIFT_VO_TRIGGER_NUM_8822B 0 #define BIT_MASK_VO_TRIGGER_NUM_8822B 0xf -#define BIT_VO_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_VO_TRIGGER_NUM_8822B) << BIT_SHIFT_VO_TRIGGER_NUM_8822B) -#define BIT_GET_VO_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8822B) & BIT_MASK_VO_TRIGGER_NUM_8822B) - - +#define BIT_VO_TRIGGER_NUM_8822B(x) \ + (((x) & BIT_MASK_VO_TRIGGER_NUM_8822B) \ + << BIT_SHIFT_VO_TRIGGER_NUM_8822B) +#define BITS_VO_TRIGGER_NUM_8822B \ + (BIT_MASK_VO_TRIGGER_NUM_8822B << BIT_SHIFT_VO_TRIGGER_NUM_8822B) +#define BIT_CLEAR_VO_TRIGGER_NUM_8822B(x) ((x) & (~BITS_VO_TRIGGER_NUM_8822B)) +#define BIT_GET_VO_TRIGGER_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8822B) & \ + BIT_MASK_VO_TRIGGER_NUM_8822B) +#define BIT_SET_VO_TRIGGER_NUM_8822B(x, v) \ + (BIT_CLEAR_VO_TRIGGER_NUM_8822B(x) | BIT_VO_TRIGGER_NUM_8822B(v)) /* 2 REG_TBTT_PROHIBIT_8822B */ #define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B 8 #define BIT_MASK_TBTT_HOLD_TIME_AP_8822B 0xfff -#define BIT_TBTT_HOLD_TIME_AP_8822B(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) -#define BIT_GET_TBTT_HOLD_TIME_AP_8822B(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B) - - +#define BIT_TBTT_HOLD_TIME_AP_8822B(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B) \ + << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) +#define BITS_TBTT_HOLD_TIME_AP_8822B \ + (BIT_MASK_TBTT_HOLD_TIME_AP_8822B << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) +#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8822B(x) \ + ((x) & (~BITS_TBTT_HOLD_TIME_AP_8822B)) +#define BIT_GET_TBTT_HOLD_TIME_AP_8822B(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) & \ + BIT_MASK_TBTT_HOLD_TIME_AP_8822B) +#define BIT_SET_TBTT_HOLD_TIME_AP_8822B(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_AP_8822B(x) | BIT_TBTT_HOLD_TIME_AP_8822B(v)) #define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B 0 #define BIT_MASK_TBTT_PROHIBIT_SETUP_8822B 0xf -#define BIT_TBTT_PROHIBIT_SETUP_8822B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) -#define BIT_GET_TBTT_PROHIBIT_SETUP_8822B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) - - +#define BIT_TBTT_PROHIBIT_SETUP_8822B(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) +#define BITS_TBTT_PROHIBIT_SETUP_8822B \ + (BIT_MASK_TBTT_PROHIBIT_SETUP_8822B \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822B(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8822B)) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8822B(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) & \ + BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) +#define BIT_SET_TBTT_PROHIBIT_SETUP_8822B(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822B(x) | \ + BIT_TBTT_PROHIBIT_SETUP_8822B(v)) /* 2 REG_P2PPS_STATE_8822B */ #define BIT_POWER_STATE_8822B BIT(7) @@ -7383,19 +11780,31 @@ #define BIT_SHIFT_RD_NAV_PROT_NXT_8822B 0 #define BIT_MASK_RD_NAV_PROT_NXT_8822B 0xffff -#define BIT_RD_NAV_PROT_NXT_8822B(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8822B) << BIT_SHIFT_RD_NAV_PROT_NXT_8822B) -#define BIT_GET_RD_NAV_PROT_NXT_8822B(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822B) & BIT_MASK_RD_NAV_PROT_NXT_8822B) - - +#define BIT_RD_NAV_PROT_NXT_8822B(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT_8822B) \ + << BIT_SHIFT_RD_NAV_PROT_NXT_8822B) +#define BITS_RD_NAV_PROT_NXT_8822B \ + (BIT_MASK_RD_NAV_PROT_NXT_8822B << BIT_SHIFT_RD_NAV_PROT_NXT_8822B) +#define BIT_CLEAR_RD_NAV_PROT_NXT_8822B(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8822B)) +#define BIT_GET_RD_NAV_PROT_NXT_8822B(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822B) & \ + BIT_MASK_RD_NAV_PROT_NXT_8822B) +#define BIT_SET_RD_NAV_PROT_NXT_8822B(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT_8822B(x) | BIT_RD_NAV_PROT_NXT_8822B(v)) /* 2 REG_NAV_PROT_LEN_8822B */ #define BIT_SHIFT_NAV_PROT_LEN_8822B 0 #define BIT_MASK_NAV_PROT_LEN_8822B 0xffff -#define BIT_NAV_PROT_LEN_8822B(x) (((x) & BIT_MASK_NAV_PROT_LEN_8822B) << BIT_SHIFT_NAV_PROT_LEN_8822B) -#define BIT_GET_NAV_PROT_LEN_8822B(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8822B) & BIT_MASK_NAV_PROT_LEN_8822B) - - +#define BIT_NAV_PROT_LEN_8822B(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN_8822B) << BIT_SHIFT_NAV_PROT_LEN_8822B) +#define BITS_NAV_PROT_LEN_8822B \ + (BIT_MASK_NAV_PROT_LEN_8822B << BIT_SHIFT_NAV_PROT_LEN_8822B) +#define BIT_CLEAR_NAV_PROT_LEN_8822B(x) ((x) & (~BITS_NAV_PROT_LEN_8822B)) +#define BIT_GET_NAV_PROT_LEN_8822B(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN_8822B) & BIT_MASK_NAV_PROT_LEN_8822B) +#define BIT_SET_NAV_PROT_LEN_8822B(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN_8822B(x) | BIT_NAV_PROT_LEN_8822B(v)) /* 2 REG_BCN_CTRL_8822B */ #define BIT_DIS_RX_BSSID_FIT_8822B BIT(6) @@ -7419,10 +11828,15 @@ #define BIT_SHIFT_MBID_BCN_NUM_8822B 0 #define BIT_MASK_MBID_BCN_NUM_8822B 0x7 -#define BIT_MBID_BCN_NUM_8822B(x) (((x) & BIT_MASK_MBID_BCN_NUM_8822B) << BIT_SHIFT_MBID_BCN_NUM_8822B) -#define BIT_GET_MBID_BCN_NUM_8822B(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8822B) & BIT_MASK_MBID_BCN_NUM_8822B) - - +#define BIT_MBID_BCN_NUM_8822B(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_8822B) << BIT_SHIFT_MBID_BCN_NUM_8822B) +#define BITS_MBID_BCN_NUM_8822B \ + (BIT_MASK_MBID_BCN_NUM_8822B << BIT_SHIFT_MBID_BCN_NUM_8822B) +#define BIT_CLEAR_MBID_BCN_NUM_8822B(x) ((x) & (~BITS_MBID_BCN_NUM_8822B)) +#define BIT_GET_MBID_BCN_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_8822B) & BIT_MASK_MBID_BCN_NUM_8822B) +#define BIT_SET_MBID_BCN_NUM_8822B(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_8822B(x) | BIT_MBID_BCN_NUM_8822B(v)) /* 2 REG_DUAL_TSF_RST_8822B */ #define BIT_FREECNT_RST_8822B BIT(5) @@ -7436,171 +11850,297 @@ #define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B 28 #define BIT_MASK_BCN_TIMER_SEL_FWRD_8822B 0x7 -#define BIT_BCN_TIMER_SEL_FWRD_8822B(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) -#define BIT_GET_BCN_TIMER_SEL_FWRD_8822B(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) - - +#define BIT_BCN_TIMER_SEL_FWRD_8822B(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) +#define BITS_BCN_TIMER_SEL_FWRD_8822B \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_8822B \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822B(x) \ + ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8822B)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) +#define BIT_SET_BCN_TIMER_SEL_FWRD_8822B(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822B(x) | \ + BIT_BCN_TIMER_SEL_FWRD_8822B(v)) #define BIT_SHIFT_BCN_SPACE_CLINT0_8822B 16 #define BIT_MASK_BCN_SPACE_CLINT0_8822B 0xfff -#define BIT_BCN_SPACE_CLINT0_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8822B) << BIT_SHIFT_BCN_SPACE_CLINT0_8822B) -#define BIT_GET_BCN_SPACE_CLINT0_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822B) & BIT_MASK_BCN_SPACE_CLINT0_8822B) - - +#define BIT_BCN_SPACE_CLINT0_8822B(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT0_8822B) \ + << BIT_SHIFT_BCN_SPACE_CLINT0_8822B) +#define BITS_BCN_SPACE_CLINT0_8822B \ + (BIT_MASK_BCN_SPACE_CLINT0_8822B << BIT_SHIFT_BCN_SPACE_CLINT0_8822B) +#define BIT_CLEAR_BCN_SPACE_CLINT0_8822B(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT0_8822B)) +#define BIT_GET_BCN_SPACE_CLINT0_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822B) & \ + BIT_MASK_BCN_SPACE_CLINT0_8822B) +#define BIT_SET_BCN_SPACE_CLINT0_8822B(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT0_8822B(x) | BIT_BCN_SPACE_CLINT0_8822B(v)) #define BIT_SHIFT_BCN_SPACE0_8822B 0 #define BIT_MASK_BCN_SPACE0_8822B 0xffff -#define BIT_BCN_SPACE0_8822B(x) (((x) & BIT_MASK_BCN_SPACE0_8822B) << BIT_SHIFT_BCN_SPACE0_8822B) -#define BIT_GET_BCN_SPACE0_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8822B) & BIT_MASK_BCN_SPACE0_8822B) - - +#define BIT_BCN_SPACE0_8822B(x) \ + (((x) & BIT_MASK_BCN_SPACE0_8822B) << BIT_SHIFT_BCN_SPACE0_8822B) +#define BITS_BCN_SPACE0_8822B \ + (BIT_MASK_BCN_SPACE0_8822B << BIT_SHIFT_BCN_SPACE0_8822B) +#define BIT_CLEAR_BCN_SPACE0_8822B(x) ((x) & (~BITS_BCN_SPACE0_8822B)) +#define BIT_GET_BCN_SPACE0_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE0_8822B) & BIT_MASK_BCN_SPACE0_8822B) +#define BIT_SET_BCN_SPACE0_8822B(x, v) \ + (BIT_CLEAR_BCN_SPACE0_8822B(x) | BIT_BCN_SPACE0_8822B(v)) /* 2 REG_DRVERLYINT_8822B */ #define BIT_SHIFT_DRVERLYITV_8822B 0 #define BIT_MASK_DRVERLYITV_8822B 0xff -#define BIT_DRVERLYITV_8822B(x) (((x) & BIT_MASK_DRVERLYITV_8822B) << BIT_SHIFT_DRVERLYITV_8822B) -#define BIT_GET_DRVERLYITV_8822B(x) (((x) >> BIT_SHIFT_DRVERLYITV_8822B) & BIT_MASK_DRVERLYITV_8822B) - - +#define BIT_DRVERLYITV_8822B(x) \ + (((x) & BIT_MASK_DRVERLYITV_8822B) << BIT_SHIFT_DRVERLYITV_8822B) +#define BITS_DRVERLYITV_8822B \ + (BIT_MASK_DRVERLYITV_8822B << BIT_SHIFT_DRVERLYITV_8822B) +#define BIT_CLEAR_DRVERLYITV_8822B(x) ((x) & (~BITS_DRVERLYITV_8822B)) +#define BIT_GET_DRVERLYITV_8822B(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV_8822B) & BIT_MASK_DRVERLYITV_8822B) +#define BIT_SET_DRVERLYITV_8822B(x, v) \ + (BIT_CLEAR_DRVERLYITV_8822B(x) | BIT_DRVERLYITV_8822B(v)) /* 2 REG_BCNDMATIM_8822B */ #define BIT_SHIFT_BCNDMATIM_8822B 0 #define BIT_MASK_BCNDMATIM_8822B 0xff -#define BIT_BCNDMATIM_8822B(x) (((x) & BIT_MASK_BCNDMATIM_8822B) << BIT_SHIFT_BCNDMATIM_8822B) -#define BIT_GET_BCNDMATIM_8822B(x) (((x) >> BIT_SHIFT_BCNDMATIM_8822B) & BIT_MASK_BCNDMATIM_8822B) - - +#define BIT_BCNDMATIM_8822B(x) \ + (((x) & BIT_MASK_BCNDMATIM_8822B) << BIT_SHIFT_BCNDMATIM_8822B) +#define BITS_BCNDMATIM_8822B \ + (BIT_MASK_BCNDMATIM_8822B << BIT_SHIFT_BCNDMATIM_8822B) +#define BIT_CLEAR_BCNDMATIM_8822B(x) ((x) & (~BITS_BCNDMATIM_8822B)) +#define BIT_GET_BCNDMATIM_8822B(x) \ + (((x) >> BIT_SHIFT_BCNDMATIM_8822B) & BIT_MASK_BCNDMATIM_8822B) +#define BIT_SET_BCNDMATIM_8822B(x, v) \ + (BIT_CLEAR_BCNDMATIM_8822B(x) | BIT_BCNDMATIM_8822B(v)) /* 2 REG_ATIMWND_8822B */ #define BIT_SHIFT_ATIMWND0_8822B 0 #define BIT_MASK_ATIMWND0_8822B 0xffff -#define BIT_ATIMWND0_8822B(x) (((x) & BIT_MASK_ATIMWND0_8822B) << BIT_SHIFT_ATIMWND0_8822B) -#define BIT_GET_ATIMWND0_8822B(x) (((x) >> BIT_SHIFT_ATIMWND0_8822B) & BIT_MASK_ATIMWND0_8822B) - - +#define BIT_ATIMWND0_8822B(x) \ + (((x) & BIT_MASK_ATIMWND0_8822B) << BIT_SHIFT_ATIMWND0_8822B) +#define BITS_ATIMWND0_8822B \ + (BIT_MASK_ATIMWND0_8822B << BIT_SHIFT_ATIMWND0_8822B) +#define BIT_CLEAR_ATIMWND0_8822B(x) ((x) & (~BITS_ATIMWND0_8822B)) +#define BIT_GET_ATIMWND0_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND0_8822B) & BIT_MASK_ATIMWND0_8822B) +#define BIT_SET_ATIMWND0_8822B(x, v) \ + (BIT_CLEAR_ATIMWND0_8822B(x) | BIT_ATIMWND0_8822B(v)) /* 2 REG_USTIME_TSF_8822B */ #define BIT_SHIFT_USTIME_TSF_V1_8822B 0 #define BIT_MASK_USTIME_TSF_V1_8822B 0xff -#define BIT_USTIME_TSF_V1_8822B(x) (((x) & BIT_MASK_USTIME_TSF_V1_8822B) << BIT_SHIFT_USTIME_TSF_V1_8822B) -#define BIT_GET_USTIME_TSF_V1_8822B(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8822B) & BIT_MASK_USTIME_TSF_V1_8822B) - - +#define BIT_USTIME_TSF_V1_8822B(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1_8822B) << BIT_SHIFT_USTIME_TSF_V1_8822B) +#define BITS_USTIME_TSF_V1_8822B \ + (BIT_MASK_USTIME_TSF_V1_8822B << BIT_SHIFT_USTIME_TSF_V1_8822B) +#define BIT_CLEAR_USTIME_TSF_V1_8822B(x) ((x) & (~BITS_USTIME_TSF_V1_8822B)) +#define BIT_GET_USTIME_TSF_V1_8822B(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1_8822B) & BIT_MASK_USTIME_TSF_V1_8822B) +#define BIT_SET_USTIME_TSF_V1_8822B(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1_8822B(x) | BIT_USTIME_TSF_V1_8822B(v)) /* 2 REG_BCN_MAX_ERR_8822B */ #define BIT_SHIFT_BCN_MAX_ERR_8822B 0 #define BIT_MASK_BCN_MAX_ERR_8822B 0xff -#define BIT_BCN_MAX_ERR_8822B(x) (((x) & BIT_MASK_BCN_MAX_ERR_8822B) << BIT_SHIFT_BCN_MAX_ERR_8822B) -#define BIT_GET_BCN_MAX_ERR_8822B(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8822B) & BIT_MASK_BCN_MAX_ERR_8822B) - - +#define BIT_BCN_MAX_ERR_8822B(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR_8822B) << BIT_SHIFT_BCN_MAX_ERR_8822B) +#define BITS_BCN_MAX_ERR_8822B \ + (BIT_MASK_BCN_MAX_ERR_8822B << BIT_SHIFT_BCN_MAX_ERR_8822B) +#define BIT_CLEAR_BCN_MAX_ERR_8822B(x) ((x) & (~BITS_BCN_MAX_ERR_8822B)) +#define BIT_GET_BCN_MAX_ERR_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR_8822B) & BIT_MASK_BCN_MAX_ERR_8822B) +#define BIT_SET_BCN_MAX_ERR_8822B(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR_8822B(x) | BIT_BCN_MAX_ERR_8822B(v)) /* 2 REG_RXTSF_OFFSET_CCK_8822B */ #define BIT_SHIFT_CCK_RXTSF_OFFSET_8822B 0 #define BIT_MASK_CCK_RXTSF_OFFSET_8822B 0xff -#define BIT_CCK_RXTSF_OFFSET_8822B(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822B) << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) -#define BIT_GET_CCK_RXTSF_OFFSET_8822B(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) & BIT_MASK_CCK_RXTSF_OFFSET_8822B) - - +#define BIT_CCK_RXTSF_OFFSET_8822B(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822B) \ + << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) +#define BITS_CCK_RXTSF_OFFSET_8822B \ + (BIT_MASK_CCK_RXTSF_OFFSET_8822B << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) +#define BIT_CLEAR_CCK_RXTSF_OFFSET_8822B(x) \ + ((x) & (~BITS_CCK_RXTSF_OFFSET_8822B)) +#define BIT_GET_CCK_RXTSF_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) & \ + BIT_MASK_CCK_RXTSF_OFFSET_8822B) +#define BIT_SET_CCK_RXTSF_OFFSET_8822B(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET_8822B(x) | BIT_CCK_RXTSF_OFFSET_8822B(v)) /* 2 REG_RXTSF_OFFSET_OFDM_8822B */ #define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B 0 #define BIT_MASK_OFDM_RXTSF_OFFSET_8822B 0xff -#define BIT_OFDM_RXTSF_OFFSET_8822B(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) -#define BIT_GET_OFDM_RXTSF_OFFSET_8822B(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B) - - +#define BIT_OFDM_RXTSF_OFFSET_8822B(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B) \ + << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) +#define BITS_OFDM_RXTSF_OFFSET_8822B \ + (BIT_MASK_OFDM_RXTSF_OFFSET_8822B << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8822B(x) \ + ((x) & (~BITS_OFDM_RXTSF_OFFSET_8822B)) +#define BIT_GET_OFDM_RXTSF_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) & \ + BIT_MASK_OFDM_RXTSF_OFFSET_8822B) +#define BIT_SET_OFDM_RXTSF_OFFSET_8822B(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET_8822B(x) | BIT_OFDM_RXTSF_OFFSET_8822B(v)) /* 2 REG_TSFTR_8822B */ #define BIT_SHIFT_TSF_TIMER_8822B 0 #define BIT_MASK_TSF_TIMER_8822B 0xffffffffffffffffL -#define BIT_TSF_TIMER_8822B(x) (((x) & BIT_MASK_TSF_TIMER_8822B) << BIT_SHIFT_TSF_TIMER_8822B) -#define BIT_GET_TSF_TIMER_8822B(x) (((x) >> BIT_SHIFT_TSF_TIMER_8822B) & BIT_MASK_TSF_TIMER_8822B) - - +#define BIT_TSF_TIMER_8822B(x) \ + (((x) & BIT_MASK_TSF_TIMER_8822B) << BIT_SHIFT_TSF_TIMER_8822B) +#define BITS_TSF_TIMER_8822B \ + (BIT_MASK_TSF_TIMER_8822B << BIT_SHIFT_TSF_TIMER_8822B) +#define BIT_CLEAR_TSF_TIMER_8822B(x) ((x) & (~BITS_TSF_TIMER_8822B)) +#define BIT_GET_TSF_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_8822B) & BIT_MASK_TSF_TIMER_8822B) +#define BIT_SET_TSF_TIMER_8822B(x, v) \ + (BIT_CLEAR_TSF_TIMER_8822B(x) | BIT_TSF_TIMER_8822B(v)) /* 2 REG_FREERUN_CNT_8822B */ #define BIT_SHIFT_FREERUN_CNT_8822B 0 #define BIT_MASK_FREERUN_CNT_8822B 0xffffffffffffffffL -#define BIT_FREERUN_CNT_8822B(x) (((x) & BIT_MASK_FREERUN_CNT_8822B) << BIT_SHIFT_FREERUN_CNT_8822B) -#define BIT_GET_FREERUN_CNT_8822B(x) (((x) >> BIT_SHIFT_FREERUN_CNT_8822B) & BIT_MASK_FREERUN_CNT_8822B) - - +#define BIT_FREERUN_CNT_8822B(x) \ + (((x) & BIT_MASK_FREERUN_CNT_8822B) << BIT_SHIFT_FREERUN_CNT_8822B) +#define BITS_FREERUN_CNT_8822B \ + (BIT_MASK_FREERUN_CNT_8822B << BIT_SHIFT_FREERUN_CNT_8822B) +#define BIT_CLEAR_FREERUN_CNT_8822B(x) ((x) & (~BITS_FREERUN_CNT_8822B)) +#define BIT_GET_FREERUN_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_8822B) & BIT_MASK_FREERUN_CNT_8822B) +#define BIT_SET_FREERUN_CNT_8822B(x, v) \ + (BIT_CLEAR_FREERUN_CNT_8822B(x) | BIT_FREERUN_CNT_8822B(v)) /* 2 REG_ATIMWND1_V1_8822B */ #define BIT_SHIFT_ATIMWND1_V1_8822B 0 #define BIT_MASK_ATIMWND1_V1_8822B 0xff -#define BIT_ATIMWND1_V1_8822B(x) (((x) & BIT_MASK_ATIMWND1_V1_8822B) << BIT_SHIFT_ATIMWND1_V1_8822B) -#define BIT_GET_ATIMWND1_V1_8822B(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8822B) & BIT_MASK_ATIMWND1_V1_8822B) - - +#define BIT_ATIMWND1_V1_8822B(x) \ + (((x) & BIT_MASK_ATIMWND1_V1_8822B) << BIT_SHIFT_ATIMWND1_V1_8822B) +#define BITS_ATIMWND1_V1_8822B \ + (BIT_MASK_ATIMWND1_V1_8822B << BIT_SHIFT_ATIMWND1_V1_8822B) +#define BIT_CLEAR_ATIMWND1_V1_8822B(x) ((x) & (~BITS_ATIMWND1_V1_8822B)) +#define BIT_GET_ATIMWND1_V1_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND1_V1_8822B) & BIT_MASK_ATIMWND1_V1_8822B) +#define BIT_SET_ATIMWND1_V1_8822B(x, v) \ + (BIT_CLEAR_ATIMWND1_V1_8822B(x) | BIT_ATIMWND1_V1_8822B(v)) /* 2 REG_TBTT_PROHIBIT_INFRA_8822B */ #define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B 0 #define BIT_MASK_TBTT_PROHIBIT_INFRA_8822B 0xff -#define BIT_TBTT_PROHIBIT_INFRA_8822B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) -#define BIT_GET_TBTT_PROHIBIT_INFRA_8822B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) - - +#define BIT_TBTT_PROHIBIT_INFRA_8822B(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) +#define BITS_TBTT_PROHIBIT_INFRA_8822B \ + (BIT_MASK_TBTT_PROHIBIT_INFRA_8822B \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) +#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822B(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8822B)) +#define BIT_GET_TBTT_PROHIBIT_INFRA_8822B(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) & \ + BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) +#define BIT_SET_TBTT_PROHIBIT_INFRA_8822B(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822B(x) | \ + BIT_TBTT_PROHIBIT_INFRA_8822B(v)) /* 2 REG_CTWND_8822B */ #define BIT_SHIFT_CTWND_8822B 0 #define BIT_MASK_CTWND_8822B 0xff -#define BIT_CTWND_8822B(x) (((x) & BIT_MASK_CTWND_8822B) << BIT_SHIFT_CTWND_8822B) -#define BIT_GET_CTWND_8822B(x) (((x) >> BIT_SHIFT_CTWND_8822B) & BIT_MASK_CTWND_8822B) - - +#define BIT_CTWND_8822B(x) \ + (((x) & BIT_MASK_CTWND_8822B) << BIT_SHIFT_CTWND_8822B) +#define BITS_CTWND_8822B (BIT_MASK_CTWND_8822B << BIT_SHIFT_CTWND_8822B) +#define BIT_CLEAR_CTWND_8822B(x) ((x) & (~BITS_CTWND_8822B)) +#define BIT_GET_CTWND_8822B(x) \ + (((x) >> BIT_SHIFT_CTWND_8822B) & BIT_MASK_CTWND_8822B) +#define BIT_SET_CTWND_8822B(x, v) \ + (BIT_CLEAR_CTWND_8822B(x) | BIT_CTWND_8822B(v)) /* 2 REG_BCNIVLCUNT_8822B */ #define BIT_SHIFT_BCNIVLCUNT_8822B 0 #define BIT_MASK_BCNIVLCUNT_8822B 0x7f -#define BIT_BCNIVLCUNT_8822B(x) (((x) & BIT_MASK_BCNIVLCUNT_8822B) << BIT_SHIFT_BCNIVLCUNT_8822B) -#define BIT_GET_BCNIVLCUNT_8822B(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8822B) & BIT_MASK_BCNIVLCUNT_8822B) - - +#define BIT_BCNIVLCUNT_8822B(x) \ + (((x) & BIT_MASK_BCNIVLCUNT_8822B) << BIT_SHIFT_BCNIVLCUNT_8822B) +#define BITS_BCNIVLCUNT_8822B \ + (BIT_MASK_BCNIVLCUNT_8822B << BIT_SHIFT_BCNIVLCUNT_8822B) +#define BIT_CLEAR_BCNIVLCUNT_8822B(x) ((x) & (~BITS_BCNIVLCUNT_8822B)) +#define BIT_GET_BCNIVLCUNT_8822B(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT_8822B) & BIT_MASK_BCNIVLCUNT_8822B) +#define BIT_SET_BCNIVLCUNT_8822B(x, v) \ + (BIT_CLEAR_BCNIVLCUNT_8822B(x) | BIT_BCNIVLCUNT_8822B(v)) /* 2 REG_BCNDROPCTRL_8822B */ #define BIT_BEACON_DROP_EN_8822B BIT(7) #define BIT_SHIFT_BEACON_DROP_IVL_8822B 0 #define BIT_MASK_BEACON_DROP_IVL_8822B 0x7f -#define BIT_BEACON_DROP_IVL_8822B(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8822B) << BIT_SHIFT_BEACON_DROP_IVL_8822B) -#define BIT_GET_BEACON_DROP_IVL_8822B(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822B) & BIT_MASK_BEACON_DROP_IVL_8822B) - - +#define BIT_BEACON_DROP_IVL_8822B(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL_8822B) \ + << BIT_SHIFT_BEACON_DROP_IVL_8822B) +#define BITS_BEACON_DROP_IVL_8822B \ + (BIT_MASK_BEACON_DROP_IVL_8822B << BIT_SHIFT_BEACON_DROP_IVL_8822B) +#define BIT_CLEAR_BEACON_DROP_IVL_8822B(x) ((x) & (~BITS_BEACON_DROP_IVL_8822B)) +#define BIT_GET_BEACON_DROP_IVL_8822B(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822B) & \ + BIT_MASK_BEACON_DROP_IVL_8822B) +#define BIT_SET_BEACON_DROP_IVL_8822B(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL_8822B(x) | BIT_BEACON_DROP_IVL_8822B(v)) /* 2 REG_HGQ_TIMEOUT_PERIOD_8822B */ #define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B 0 #define BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B 0xff -#define BIT_HGQ_TIMEOUT_PERIOD_8822B(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) -#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822B(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) - - +#define BIT_HGQ_TIMEOUT_PERIOD_8822B(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) +#define BITS_HGQ_TIMEOUT_PERIOD_8822B \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822B(x) \ + ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8822B)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822B(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) & \ + BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) +#define BIT_SET_HGQ_TIMEOUT_PERIOD_8822B(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822B(x) | \ + BIT_HGQ_TIMEOUT_PERIOD_8822B(v)) /* 2 REG_TXCMD_TIMEOUT_PERIOD_8822B */ #define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B 0 #define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B 0xff -#define BIT_TXCMD_TIMEOUT_PERIOD_8822B(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) -#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822B(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) - - +#define BIT_TXCMD_TIMEOUT_PERIOD_8822B(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) +#define BITS_TXCMD_TIMEOUT_PERIOD_8822B \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822B(x) \ + ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8822B)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822B(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8822B(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822B(x) | \ + BIT_TXCMD_TIMEOUT_PERIOD_8822B(v)) /* 2 REG_MISC_CTRL_8822B */ +#define BIT_AUTO_SYNC_BY_TBTT_8822B BIT(6) #define BIT_DIS_TRX_CAL_BCN_8822B BIT(5) #define BIT_DIS_TX_CAL_TBTT_8822B BIT(4) #define BIT_EN_FREECNT_8822B BIT(3) @@ -7608,10 +12148,18 @@ #define BIT_SHIFT_DIS_SECONDARY_CCA_8822B 0 #define BIT_MASK_DIS_SECONDARY_CCA_8822B 0x3 -#define BIT_DIS_SECONDARY_CCA_8822B(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8822B) << BIT_SHIFT_DIS_SECONDARY_CCA_8822B) -#define BIT_GET_DIS_SECONDARY_CCA_8822B(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822B) & BIT_MASK_DIS_SECONDARY_CCA_8822B) - - +#define BIT_DIS_SECONDARY_CCA_8822B(x) \ + (((x) & BIT_MASK_DIS_SECONDARY_CCA_8822B) \ + << BIT_SHIFT_DIS_SECONDARY_CCA_8822B) +#define BITS_DIS_SECONDARY_CCA_8822B \ + (BIT_MASK_DIS_SECONDARY_CCA_8822B << BIT_SHIFT_DIS_SECONDARY_CCA_8822B) +#define BIT_CLEAR_DIS_SECONDARY_CCA_8822B(x) \ + ((x) & (~BITS_DIS_SECONDARY_CCA_8822B)) +#define BIT_GET_DIS_SECONDARY_CCA_8822B(x) \ + (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822B) & \ + BIT_MASK_DIS_SECONDARY_CCA_8822B) +#define BIT_SET_DIS_SECONDARY_CCA_8822B(x, v) \ + (BIT_CLEAR_DIS_SECONDARY_CCA_8822B(x) | BIT_DIS_SECONDARY_CCA_8822B(v)) /* 2 REG_BCN_CTRL_CLINT1_8822B */ #define BIT_CLI1_DIS_RX_BSSID_FIT_8822B BIT(6) @@ -7643,10 +12191,15 @@ #define BIT_SHIFT_PORT_SEL_8822B 0 #define BIT_MASK_PORT_SEL_8822B 0x7 -#define BIT_PORT_SEL_8822B(x) (((x) & BIT_MASK_PORT_SEL_8822B) << BIT_SHIFT_PORT_SEL_8822B) -#define BIT_GET_PORT_SEL_8822B(x) (((x) >> BIT_SHIFT_PORT_SEL_8822B) & BIT_MASK_PORT_SEL_8822B) - - +#define BIT_PORT_SEL_8822B(x) \ + (((x) & BIT_MASK_PORT_SEL_8822B) << BIT_SHIFT_PORT_SEL_8822B) +#define BITS_PORT_SEL_8822B \ + (BIT_MASK_PORT_SEL_8822B << BIT_SHIFT_PORT_SEL_8822B) +#define BIT_CLEAR_PORT_SEL_8822B(x) ((x) & (~BITS_PORT_SEL_8822B)) +#define BIT_GET_PORT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_PORT_SEL_8822B) & BIT_MASK_PORT_SEL_8822B) +#define BIT_SET_PORT_SEL_8822B(x, v) \ + (BIT_CLEAR_PORT_SEL_8822B(x) | BIT_PORT_SEL_8822B(v)) /* 2 REG_P2PPS1_SPEC_STATE_8822B */ #define BIT_P2P1_SPEC_POWER_STATE_8822B BIT(7) @@ -7692,64 +12245,99 @@ #define BIT_SHIFT_PSTIMER0_INT_8822B 5 #define BIT_MASK_PSTIMER0_INT_8822B 0x7ffffff -#define BIT_PSTIMER0_INT_8822B(x) (((x) & BIT_MASK_PSTIMER0_INT_8822B) << BIT_SHIFT_PSTIMER0_INT_8822B) -#define BIT_GET_PSTIMER0_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8822B) & BIT_MASK_PSTIMER0_INT_8822B) - - +#define BIT_PSTIMER0_INT_8822B(x) \ + (((x) & BIT_MASK_PSTIMER0_INT_8822B) << BIT_SHIFT_PSTIMER0_INT_8822B) +#define BITS_PSTIMER0_INT_8822B \ + (BIT_MASK_PSTIMER0_INT_8822B << BIT_SHIFT_PSTIMER0_INT_8822B) +#define BIT_CLEAR_PSTIMER0_INT_8822B(x) ((x) & (~BITS_PSTIMER0_INT_8822B)) +#define BIT_GET_PSTIMER0_INT_8822B(x) \ + (((x) >> BIT_SHIFT_PSTIMER0_INT_8822B) & BIT_MASK_PSTIMER0_INT_8822B) +#define BIT_SET_PSTIMER0_INT_8822B(x, v) \ + (BIT_CLEAR_PSTIMER0_INT_8822B(x) | BIT_PSTIMER0_INT_8822B(v)) /* 2 REG_PS_TIMER1_8822B */ #define BIT_SHIFT_PSTIMER1_INT_8822B 5 #define BIT_MASK_PSTIMER1_INT_8822B 0x7ffffff -#define BIT_PSTIMER1_INT_8822B(x) (((x) & BIT_MASK_PSTIMER1_INT_8822B) << BIT_SHIFT_PSTIMER1_INT_8822B) -#define BIT_GET_PSTIMER1_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8822B) & BIT_MASK_PSTIMER1_INT_8822B) - - +#define BIT_PSTIMER1_INT_8822B(x) \ + (((x) & BIT_MASK_PSTIMER1_INT_8822B) << BIT_SHIFT_PSTIMER1_INT_8822B) +#define BITS_PSTIMER1_INT_8822B \ + (BIT_MASK_PSTIMER1_INT_8822B << BIT_SHIFT_PSTIMER1_INT_8822B) +#define BIT_CLEAR_PSTIMER1_INT_8822B(x) ((x) & (~BITS_PSTIMER1_INT_8822B)) +#define BIT_GET_PSTIMER1_INT_8822B(x) \ + (((x) >> BIT_SHIFT_PSTIMER1_INT_8822B) & BIT_MASK_PSTIMER1_INT_8822B) +#define BIT_SET_PSTIMER1_INT_8822B(x, v) \ + (BIT_CLEAR_PSTIMER1_INT_8822B(x) | BIT_PSTIMER1_INT_8822B(v)) /* 2 REG_PS_TIMER2_8822B */ #define BIT_SHIFT_PSTIMER2_INT_8822B 5 #define BIT_MASK_PSTIMER2_INT_8822B 0x7ffffff -#define BIT_PSTIMER2_INT_8822B(x) (((x) & BIT_MASK_PSTIMER2_INT_8822B) << BIT_SHIFT_PSTIMER2_INT_8822B) -#define BIT_GET_PSTIMER2_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8822B) & BIT_MASK_PSTIMER2_INT_8822B) - - +#define BIT_PSTIMER2_INT_8822B(x) \ + (((x) & BIT_MASK_PSTIMER2_INT_8822B) << BIT_SHIFT_PSTIMER2_INT_8822B) +#define BITS_PSTIMER2_INT_8822B \ + (BIT_MASK_PSTIMER2_INT_8822B << BIT_SHIFT_PSTIMER2_INT_8822B) +#define BIT_CLEAR_PSTIMER2_INT_8822B(x) ((x) & (~BITS_PSTIMER2_INT_8822B)) +#define BIT_GET_PSTIMER2_INT_8822B(x) \ + (((x) >> BIT_SHIFT_PSTIMER2_INT_8822B) & BIT_MASK_PSTIMER2_INT_8822B) +#define BIT_SET_PSTIMER2_INT_8822B(x, v) \ + (BIT_CLEAR_PSTIMER2_INT_8822B(x) | BIT_PSTIMER2_INT_8822B(v)) /* 2 REG_TBTT_CTN_AREA_8822B */ #define BIT_SHIFT_TBTT_CTN_AREA_8822B 0 #define BIT_MASK_TBTT_CTN_AREA_8822B 0xff -#define BIT_TBTT_CTN_AREA_8822B(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8822B) << BIT_SHIFT_TBTT_CTN_AREA_8822B) -#define BIT_GET_TBTT_CTN_AREA_8822B(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822B) & BIT_MASK_TBTT_CTN_AREA_8822B) - - +#define BIT_TBTT_CTN_AREA_8822B(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA_8822B) << BIT_SHIFT_TBTT_CTN_AREA_8822B) +#define BITS_TBTT_CTN_AREA_8822B \ + (BIT_MASK_TBTT_CTN_AREA_8822B << BIT_SHIFT_TBTT_CTN_AREA_8822B) +#define BIT_CLEAR_TBTT_CTN_AREA_8822B(x) ((x) & (~BITS_TBTT_CTN_AREA_8822B)) +#define BIT_GET_TBTT_CTN_AREA_8822B(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822B) & BIT_MASK_TBTT_CTN_AREA_8822B) +#define BIT_SET_TBTT_CTN_AREA_8822B(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA_8822B(x) | BIT_TBTT_CTN_AREA_8822B(v)) /* 2 REG_FORCE_BCN_IFS_8822B */ #define BIT_SHIFT_FORCE_BCN_IFS_8822B 0 #define BIT_MASK_FORCE_BCN_IFS_8822B 0xff -#define BIT_FORCE_BCN_IFS_8822B(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8822B) << BIT_SHIFT_FORCE_BCN_IFS_8822B) -#define BIT_GET_FORCE_BCN_IFS_8822B(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822B) & BIT_MASK_FORCE_BCN_IFS_8822B) - - +#define BIT_FORCE_BCN_IFS_8822B(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS_8822B) << BIT_SHIFT_FORCE_BCN_IFS_8822B) +#define BITS_FORCE_BCN_IFS_8822B \ + (BIT_MASK_FORCE_BCN_IFS_8822B << BIT_SHIFT_FORCE_BCN_IFS_8822B) +#define BIT_CLEAR_FORCE_BCN_IFS_8822B(x) ((x) & (~BITS_FORCE_BCN_IFS_8822B)) +#define BIT_GET_FORCE_BCN_IFS_8822B(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822B) & BIT_MASK_FORCE_BCN_IFS_8822B) +#define BIT_SET_FORCE_BCN_IFS_8822B(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS_8822B(x) | BIT_FORCE_BCN_IFS_8822B(v)) /* 2 REG_TXOP_MIN_8822B */ #define BIT_SHIFT_TXOP_MIN_8822B 0 #define BIT_MASK_TXOP_MIN_8822B 0x3fff -#define BIT_TXOP_MIN_8822B(x) (((x) & BIT_MASK_TXOP_MIN_8822B) << BIT_SHIFT_TXOP_MIN_8822B) -#define BIT_GET_TXOP_MIN_8822B(x) (((x) >> BIT_SHIFT_TXOP_MIN_8822B) & BIT_MASK_TXOP_MIN_8822B) - - +#define BIT_TXOP_MIN_8822B(x) \ + (((x) & BIT_MASK_TXOP_MIN_8822B) << BIT_SHIFT_TXOP_MIN_8822B) +#define BITS_TXOP_MIN_8822B \ + (BIT_MASK_TXOP_MIN_8822B << BIT_SHIFT_TXOP_MIN_8822B) +#define BIT_CLEAR_TXOP_MIN_8822B(x) ((x) & (~BITS_TXOP_MIN_8822B)) +#define BIT_GET_TXOP_MIN_8822B(x) \ + (((x) >> BIT_SHIFT_TXOP_MIN_8822B) & BIT_MASK_TXOP_MIN_8822B) +#define BIT_SET_TXOP_MIN_8822B(x, v) \ + (BIT_CLEAR_TXOP_MIN_8822B(x) | BIT_TXOP_MIN_8822B(v)) /* 2 REG_PRE_BKF_TIME_8822B */ #define BIT_SHIFT_PRE_BKF_TIME_8822B 0 #define BIT_MASK_PRE_BKF_TIME_8822B 0xff -#define BIT_PRE_BKF_TIME_8822B(x) (((x) & BIT_MASK_PRE_BKF_TIME_8822B) << BIT_SHIFT_PRE_BKF_TIME_8822B) -#define BIT_GET_PRE_BKF_TIME_8822B(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8822B) & BIT_MASK_PRE_BKF_TIME_8822B) - - +#define BIT_PRE_BKF_TIME_8822B(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME_8822B) << BIT_SHIFT_PRE_BKF_TIME_8822B) +#define BITS_PRE_BKF_TIME_8822B \ + (BIT_MASK_PRE_BKF_TIME_8822B << BIT_SHIFT_PRE_BKF_TIME_8822B) +#define BIT_CLEAR_PRE_BKF_TIME_8822B(x) ((x) & (~BITS_PRE_BKF_TIME_8822B)) +#define BIT_GET_PRE_BKF_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME_8822B) & BIT_MASK_PRE_BKF_TIME_8822B) +#define BIT_SET_PRE_BKF_TIME_8822B(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME_8822B(x) | BIT_PRE_BKF_TIME_8822B(v)) /* 2 REG_CROSS_TXOP_CTRL_8822B */ #define BIT_DTIM_BYPASS_8822B BIT(2) @@ -7760,64 +12348,99 @@ #define BIT_SHIFT_ATIMWND2_8822B 0 #define BIT_MASK_ATIMWND2_8822B 0xff -#define BIT_ATIMWND2_8822B(x) (((x) & BIT_MASK_ATIMWND2_8822B) << BIT_SHIFT_ATIMWND2_8822B) -#define BIT_GET_ATIMWND2_8822B(x) (((x) >> BIT_SHIFT_ATIMWND2_8822B) & BIT_MASK_ATIMWND2_8822B) - - +#define BIT_ATIMWND2_8822B(x) \ + (((x) & BIT_MASK_ATIMWND2_8822B) << BIT_SHIFT_ATIMWND2_8822B) +#define BITS_ATIMWND2_8822B \ + (BIT_MASK_ATIMWND2_8822B << BIT_SHIFT_ATIMWND2_8822B) +#define BIT_CLEAR_ATIMWND2_8822B(x) ((x) & (~BITS_ATIMWND2_8822B)) +#define BIT_GET_ATIMWND2_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND2_8822B) & BIT_MASK_ATIMWND2_8822B) +#define BIT_SET_ATIMWND2_8822B(x, v) \ + (BIT_CLEAR_ATIMWND2_8822B(x) | BIT_ATIMWND2_8822B(v)) /* 2 REG_ATIMWND3_8822B */ #define BIT_SHIFT_ATIMWND3_8822B 0 #define BIT_MASK_ATIMWND3_8822B 0xff -#define BIT_ATIMWND3_8822B(x) (((x) & BIT_MASK_ATIMWND3_8822B) << BIT_SHIFT_ATIMWND3_8822B) -#define BIT_GET_ATIMWND3_8822B(x) (((x) >> BIT_SHIFT_ATIMWND3_8822B) & BIT_MASK_ATIMWND3_8822B) - - +#define BIT_ATIMWND3_8822B(x) \ + (((x) & BIT_MASK_ATIMWND3_8822B) << BIT_SHIFT_ATIMWND3_8822B) +#define BITS_ATIMWND3_8822B \ + (BIT_MASK_ATIMWND3_8822B << BIT_SHIFT_ATIMWND3_8822B) +#define BIT_CLEAR_ATIMWND3_8822B(x) ((x) & (~BITS_ATIMWND3_8822B)) +#define BIT_GET_ATIMWND3_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND3_8822B) & BIT_MASK_ATIMWND3_8822B) +#define BIT_SET_ATIMWND3_8822B(x, v) \ + (BIT_CLEAR_ATIMWND3_8822B(x) | BIT_ATIMWND3_8822B(v)) /* 2 REG_ATIMWND4_8822B */ #define BIT_SHIFT_ATIMWND4_8822B 0 #define BIT_MASK_ATIMWND4_8822B 0xff -#define BIT_ATIMWND4_8822B(x) (((x) & BIT_MASK_ATIMWND4_8822B) << BIT_SHIFT_ATIMWND4_8822B) -#define BIT_GET_ATIMWND4_8822B(x) (((x) >> BIT_SHIFT_ATIMWND4_8822B) & BIT_MASK_ATIMWND4_8822B) - - +#define BIT_ATIMWND4_8822B(x) \ + (((x) & BIT_MASK_ATIMWND4_8822B) << BIT_SHIFT_ATIMWND4_8822B) +#define BITS_ATIMWND4_8822B \ + (BIT_MASK_ATIMWND4_8822B << BIT_SHIFT_ATIMWND4_8822B) +#define BIT_CLEAR_ATIMWND4_8822B(x) ((x) & (~BITS_ATIMWND4_8822B)) +#define BIT_GET_ATIMWND4_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND4_8822B) & BIT_MASK_ATIMWND4_8822B) +#define BIT_SET_ATIMWND4_8822B(x, v) \ + (BIT_CLEAR_ATIMWND4_8822B(x) | BIT_ATIMWND4_8822B(v)) /* 2 REG_ATIMWND5_8822B */ #define BIT_SHIFT_ATIMWND5_8822B 0 #define BIT_MASK_ATIMWND5_8822B 0xff -#define BIT_ATIMWND5_8822B(x) (((x) & BIT_MASK_ATIMWND5_8822B) << BIT_SHIFT_ATIMWND5_8822B) -#define BIT_GET_ATIMWND5_8822B(x) (((x) >> BIT_SHIFT_ATIMWND5_8822B) & BIT_MASK_ATIMWND5_8822B) - - +#define BIT_ATIMWND5_8822B(x) \ + (((x) & BIT_MASK_ATIMWND5_8822B) << BIT_SHIFT_ATIMWND5_8822B) +#define BITS_ATIMWND5_8822B \ + (BIT_MASK_ATIMWND5_8822B << BIT_SHIFT_ATIMWND5_8822B) +#define BIT_CLEAR_ATIMWND5_8822B(x) ((x) & (~BITS_ATIMWND5_8822B)) +#define BIT_GET_ATIMWND5_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND5_8822B) & BIT_MASK_ATIMWND5_8822B) +#define BIT_SET_ATIMWND5_8822B(x, v) \ + (BIT_CLEAR_ATIMWND5_8822B(x) | BIT_ATIMWND5_8822B(v)) /* 2 REG_ATIMWND6_8822B */ #define BIT_SHIFT_ATIMWND6_8822B 0 #define BIT_MASK_ATIMWND6_8822B 0xff -#define BIT_ATIMWND6_8822B(x) (((x) & BIT_MASK_ATIMWND6_8822B) << BIT_SHIFT_ATIMWND6_8822B) -#define BIT_GET_ATIMWND6_8822B(x) (((x) >> BIT_SHIFT_ATIMWND6_8822B) & BIT_MASK_ATIMWND6_8822B) - - +#define BIT_ATIMWND6_8822B(x) \ + (((x) & BIT_MASK_ATIMWND6_8822B) << BIT_SHIFT_ATIMWND6_8822B) +#define BITS_ATIMWND6_8822B \ + (BIT_MASK_ATIMWND6_8822B << BIT_SHIFT_ATIMWND6_8822B) +#define BIT_CLEAR_ATIMWND6_8822B(x) ((x) & (~BITS_ATIMWND6_8822B)) +#define BIT_GET_ATIMWND6_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND6_8822B) & BIT_MASK_ATIMWND6_8822B) +#define BIT_SET_ATIMWND6_8822B(x, v) \ + (BIT_CLEAR_ATIMWND6_8822B(x) | BIT_ATIMWND6_8822B(v)) /* 2 REG_ATIMWND7_8822B */ #define BIT_SHIFT_ATIMWND7_8822B 0 #define BIT_MASK_ATIMWND7_8822B 0xff -#define BIT_ATIMWND7_8822B(x) (((x) & BIT_MASK_ATIMWND7_8822B) << BIT_SHIFT_ATIMWND7_8822B) -#define BIT_GET_ATIMWND7_8822B(x) (((x) >> BIT_SHIFT_ATIMWND7_8822B) & BIT_MASK_ATIMWND7_8822B) - - +#define BIT_ATIMWND7_8822B(x) \ + (((x) & BIT_MASK_ATIMWND7_8822B) << BIT_SHIFT_ATIMWND7_8822B) +#define BITS_ATIMWND7_8822B \ + (BIT_MASK_ATIMWND7_8822B << BIT_SHIFT_ATIMWND7_8822B) +#define BIT_CLEAR_ATIMWND7_8822B(x) ((x) & (~BITS_ATIMWND7_8822B)) +#define BIT_GET_ATIMWND7_8822B(x) \ + (((x) >> BIT_SHIFT_ATIMWND7_8822B) & BIT_MASK_ATIMWND7_8822B) +#define BIT_SET_ATIMWND7_8822B(x, v) \ + (BIT_CLEAR_ATIMWND7_8822B(x) | BIT_ATIMWND7_8822B(v)) /* 2 REG_ATIMUGT_8822B */ #define BIT_SHIFT_ATIM_URGENT_8822B 0 #define BIT_MASK_ATIM_URGENT_8822B 0xff -#define BIT_ATIM_URGENT_8822B(x) (((x) & BIT_MASK_ATIM_URGENT_8822B) << BIT_SHIFT_ATIM_URGENT_8822B) -#define BIT_GET_ATIM_URGENT_8822B(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8822B) & BIT_MASK_ATIM_URGENT_8822B) - - +#define BIT_ATIM_URGENT_8822B(x) \ + (((x) & BIT_MASK_ATIM_URGENT_8822B) << BIT_SHIFT_ATIM_URGENT_8822B) +#define BITS_ATIM_URGENT_8822B \ + (BIT_MASK_ATIM_URGENT_8822B << BIT_SHIFT_ATIM_URGENT_8822B) +#define BIT_CLEAR_ATIM_URGENT_8822B(x) ((x) & (~BITS_ATIM_URGENT_8822B)) +#define BIT_GET_ATIM_URGENT_8822B(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_8822B) & BIT_MASK_ATIM_URGENT_8822B) +#define BIT_SET_ATIM_URGENT_8822B(x, v) \ + (BIT_CLEAR_ATIM_URGENT_8822B(x) | BIT_ATIM_URGENT_8822B(v)) /* 2 REG_HIQ_NO_LMT_EN_8822B */ #define BIT_HIQ_NO_LMT_EN_VAP7_8822B BIT(7) @@ -7833,73 +12456,129 @@ #define BIT_SHIFT_DTIM_COUNT_ROOT_8822B 0 #define BIT_MASK_DTIM_COUNT_ROOT_8822B 0xff -#define BIT_DTIM_COUNT_ROOT_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8822B) << BIT_SHIFT_DTIM_COUNT_ROOT_8822B) -#define BIT_GET_DTIM_COUNT_ROOT_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822B) & BIT_MASK_DTIM_COUNT_ROOT_8822B) - - +#define BIT_DTIM_COUNT_ROOT_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_ROOT_8822B) \ + << BIT_SHIFT_DTIM_COUNT_ROOT_8822B) +#define BITS_DTIM_COUNT_ROOT_8822B \ + (BIT_MASK_DTIM_COUNT_ROOT_8822B << BIT_SHIFT_DTIM_COUNT_ROOT_8822B) +#define BIT_CLEAR_DTIM_COUNT_ROOT_8822B(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8822B)) +#define BIT_GET_DTIM_COUNT_ROOT_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822B) & \ + BIT_MASK_DTIM_COUNT_ROOT_8822B) +#define BIT_SET_DTIM_COUNT_ROOT_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_ROOT_8822B(x) | BIT_DTIM_COUNT_ROOT_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP1_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP1_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP1_8822B 0xff -#define BIT_DTIM_COUNT_VAP1_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8822B) << BIT_SHIFT_DTIM_COUNT_VAP1_8822B) -#define BIT_GET_DTIM_COUNT_VAP1_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822B) & BIT_MASK_DTIM_COUNT_VAP1_8822B) - - +#define BIT_DTIM_COUNT_VAP1_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP1_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP1_8822B) +#define BITS_DTIM_COUNT_VAP1_8822B \ + (BIT_MASK_DTIM_COUNT_VAP1_8822B << BIT_SHIFT_DTIM_COUNT_VAP1_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP1_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8822B)) +#define BIT_GET_DTIM_COUNT_VAP1_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP1_8822B) +#define BIT_SET_DTIM_COUNT_VAP1_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP1_8822B(x) | BIT_DTIM_COUNT_VAP1_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP2_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP2_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP2_8822B 0xff -#define BIT_DTIM_COUNT_VAP2_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8822B) << BIT_SHIFT_DTIM_COUNT_VAP2_8822B) -#define BIT_GET_DTIM_COUNT_VAP2_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822B) & BIT_MASK_DTIM_COUNT_VAP2_8822B) - - +#define BIT_DTIM_COUNT_VAP2_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP2_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP2_8822B) +#define BITS_DTIM_COUNT_VAP2_8822B \ + (BIT_MASK_DTIM_COUNT_VAP2_8822B << BIT_SHIFT_DTIM_COUNT_VAP2_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP2_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8822B)) +#define BIT_GET_DTIM_COUNT_VAP2_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP2_8822B) +#define BIT_SET_DTIM_COUNT_VAP2_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP2_8822B(x) | BIT_DTIM_COUNT_VAP2_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP3_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP3_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP3_8822B 0xff -#define BIT_DTIM_COUNT_VAP3_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8822B) << BIT_SHIFT_DTIM_COUNT_VAP3_8822B) -#define BIT_GET_DTIM_COUNT_VAP3_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822B) & BIT_MASK_DTIM_COUNT_VAP3_8822B) - - +#define BIT_DTIM_COUNT_VAP3_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP3_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP3_8822B) +#define BITS_DTIM_COUNT_VAP3_8822B \ + (BIT_MASK_DTIM_COUNT_VAP3_8822B << BIT_SHIFT_DTIM_COUNT_VAP3_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP3_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8822B)) +#define BIT_GET_DTIM_COUNT_VAP3_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP3_8822B) +#define BIT_SET_DTIM_COUNT_VAP3_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP3_8822B(x) | BIT_DTIM_COUNT_VAP3_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP4_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP4_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP4_8822B 0xff -#define BIT_DTIM_COUNT_VAP4_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8822B) << BIT_SHIFT_DTIM_COUNT_VAP4_8822B) -#define BIT_GET_DTIM_COUNT_VAP4_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822B) & BIT_MASK_DTIM_COUNT_VAP4_8822B) - - +#define BIT_DTIM_COUNT_VAP4_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP4_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP4_8822B) +#define BITS_DTIM_COUNT_VAP4_8822B \ + (BIT_MASK_DTIM_COUNT_VAP4_8822B << BIT_SHIFT_DTIM_COUNT_VAP4_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP4_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8822B)) +#define BIT_GET_DTIM_COUNT_VAP4_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP4_8822B) +#define BIT_SET_DTIM_COUNT_VAP4_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP4_8822B(x) | BIT_DTIM_COUNT_VAP4_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP5_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP5_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP5_8822B 0xff -#define BIT_DTIM_COUNT_VAP5_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8822B) << BIT_SHIFT_DTIM_COUNT_VAP5_8822B) -#define BIT_GET_DTIM_COUNT_VAP5_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822B) & BIT_MASK_DTIM_COUNT_VAP5_8822B) - - +#define BIT_DTIM_COUNT_VAP5_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP5_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP5_8822B) +#define BITS_DTIM_COUNT_VAP5_8822B \ + (BIT_MASK_DTIM_COUNT_VAP5_8822B << BIT_SHIFT_DTIM_COUNT_VAP5_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP5_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8822B)) +#define BIT_GET_DTIM_COUNT_VAP5_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP5_8822B) +#define BIT_SET_DTIM_COUNT_VAP5_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP5_8822B(x) | BIT_DTIM_COUNT_VAP5_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP6_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP6_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP6_8822B 0xff -#define BIT_DTIM_COUNT_VAP6_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8822B) << BIT_SHIFT_DTIM_COUNT_VAP6_8822B) -#define BIT_GET_DTIM_COUNT_VAP6_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822B) & BIT_MASK_DTIM_COUNT_VAP6_8822B) - - +#define BIT_DTIM_COUNT_VAP6_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP6_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP6_8822B) +#define BITS_DTIM_COUNT_VAP6_8822B \ + (BIT_MASK_DTIM_COUNT_VAP6_8822B << BIT_SHIFT_DTIM_COUNT_VAP6_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP6_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8822B)) +#define BIT_GET_DTIM_COUNT_VAP6_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP6_8822B) +#define BIT_SET_DTIM_COUNT_VAP6_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP6_8822B(x) | BIT_DTIM_COUNT_VAP6_8822B(v)) /* 2 REG_DTIM_COUNTER_VAP7_8822B */ #define BIT_SHIFT_DTIM_COUNT_VAP7_8822B 0 #define BIT_MASK_DTIM_COUNT_VAP7_8822B 0xff -#define BIT_DTIM_COUNT_VAP7_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8822B) << BIT_SHIFT_DTIM_COUNT_VAP7_8822B) -#define BIT_GET_DTIM_COUNT_VAP7_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822B) & BIT_MASK_DTIM_COUNT_VAP7_8822B) - - +#define BIT_DTIM_COUNT_VAP7_8822B(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP7_8822B) \ + << BIT_SHIFT_DTIM_COUNT_VAP7_8822B) +#define BITS_DTIM_COUNT_VAP7_8822B \ + (BIT_MASK_DTIM_COUNT_VAP7_8822B << BIT_SHIFT_DTIM_COUNT_VAP7_8822B) +#define BIT_CLEAR_DTIM_COUNT_VAP7_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8822B)) +#define BIT_GET_DTIM_COUNT_VAP7_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822B) & \ + BIT_MASK_DTIM_COUNT_VAP7_8822B) +#define BIT_SET_DTIM_COUNT_VAP7_8822B(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP7_8822B(x) | BIT_DTIM_COUNT_VAP7_8822B(v)) /* 2 REG_DIS_ATIM_8822B */ #define BIT_DIS_ATIM_VAP7_8822B BIT(7) @@ -7915,17 +12594,29 @@ #define BIT_SHIFT_TSFT_SEL_TIMER1_8822B 3 #define BIT_MASK_TSFT_SEL_TIMER1_8822B 0x7 -#define BIT_TSFT_SEL_TIMER1_8822B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8822B) << BIT_SHIFT_TSFT_SEL_TIMER1_8822B) -#define BIT_GET_TSFT_SEL_TIMER1_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822B) & BIT_MASK_TSFT_SEL_TIMER1_8822B) - - +#define BIT_TSFT_SEL_TIMER1_8822B(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER1_8822B) \ + << BIT_SHIFT_TSFT_SEL_TIMER1_8822B) +#define BITS_TSFT_SEL_TIMER1_8822B \ + (BIT_MASK_TSFT_SEL_TIMER1_8822B << BIT_SHIFT_TSFT_SEL_TIMER1_8822B) +#define BIT_CLEAR_TSFT_SEL_TIMER1_8822B(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8822B)) +#define BIT_GET_TSFT_SEL_TIMER1_8822B(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822B) & \ + BIT_MASK_TSFT_SEL_TIMER1_8822B) +#define BIT_SET_TSFT_SEL_TIMER1_8822B(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER1_8822B(x) | BIT_TSFT_SEL_TIMER1_8822B(v)) #define BIT_SHIFT_EARLY_128US_8822B 0 #define BIT_MASK_EARLY_128US_8822B 0x7 -#define BIT_EARLY_128US_8822B(x) (((x) & BIT_MASK_EARLY_128US_8822B) << BIT_SHIFT_EARLY_128US_8822B) -#define BIT_GET_EARLY_128US_8822B(x) (((x) >> BIT_SHIFT_EARLY_128US_8822B) & BIT_MASK_EARLY_128US_8822B) - - +#define BIT_EARLY_128US_8822B(x) \ + (((x) & BIT_MASK_EARLY_128US_8822B) << BIT_SHIFT_EARLY_128US_8822B) +#define BITS_EARLY_128US_8822B \ + (BIT_MASK_EARLY_128US_8822B << BIT_SHIFT_EARLY_128US_8822B) +#define BIT_CLEAR_EARLY_128US_8822B(x) ((x) & (~BITS_EARLY_128US_8822B)) +#define BIT_GET_EARLY_128US_8822B(x) \ + (((x) >> BIT_SHIFT_EARLY_128US_8822B) & BIT_MASK_EARLY_128US_8822B) +#define BIT_SET_EARLY_128US_8822B(x, v) \ + (BIT_CLEAR_EARLY_128US_8822B(x) | BIT_EARLY_128US_8822B(v)) /* 2 REG_P2PPS1_CTRL_8822B */ #define BIT_P2P1_CTW_ALLSTASLEEP_8822B BIT(7) @@ -7945,81 +12636,145 @@ #define BIT_SHIFT_SYNC_CLI_SEL_8822B 4 #define BIT_MASK_SYNC_CLI_SEL_8822B 0x7 -#define BIT_SYNC_CLI_SEL_8822B(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8822B) << BIT_SHIFT_SYNC_CLI_SEL_8822B) -#define BIT_GET_SYNC_CLI_SEL_8822B(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822B) & BIT_MASK_SYNC_CLI_SEL_8822B) - - +#define BIT_SYNC_CLI_SEL_8822B(x) \ + (((x) & BIT_MASK_SYNC_CLI_SEL_8822B) << BIT_SHIFT_SYNC_CLI_SEL_8822B) +#define BITS_SYNC_CLI_SEL_8822B \ + (BIT_MASK_SYNC_CLI_SEL_8822B << BIT_SHIFT_SYNC_CLI_SEL_8822B) +#define BIT_CLEAR_SYNC_CLI_SEL_8822B(x) ((x) & (~BITS_SYNC_CLI_SEL_8822B)) +#define BIT_GET_SYNC_CLI_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822B) & BIT_MASK_SYNC_CLI_SEL_8822B) +#define BIT_SET_SYNC_CLI_SEL_8822B(x, v) \ + (BIT_CLEAR_SYNC_CLI_SEL_8822B(x) | BIT_SYNC_CLI_SEL_8822B(v)) #define BIT_SHIFT_TSFT_SEL_TIMER0_8822B 0 #define BIT_MASK_TSFT_SEL_TIMER0_8822B 0x7 -#define BIT_TSFT_SEL_TIMER0_8822B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8822B) << BIT_SHIFT_TSFT_SEL_TIMER0_8822B) -#define BIT_GET_TSFT_SEL_TIMER0_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822B) & BIT_MASK_TSFT_SEL_TIMER0_8822B) - - +#define BIT_TSFT_SEL_TIMER0_8822B(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER0_8822B) \ + << BIT_SHIFT_TSFT_SEL_TIMER0_8822B) +#define BITS_TSFT_SEL_TIMER0_8822B \ + (BIT_MASK_TSFT_SEL_TIMER0_8822B << BIT_SHIFT_TSFT_SEL_TIMER0_8822B) +#define BIT_CLEAR_TSFT_SEL_TIMER0_8822B(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8822B)) +#define BIT_GET_TSFT_SEL_TIMER0_8822B(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822B) & \ + BIT_MASK_TSFT_SEL_TIMER0_8822B) +#define BIT_SET_TSFT_SEL_TIMER0_8822B(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER0_8822B(x) | BIT_TSFT_SEL_TIMER0_8822B(v)) /* 2 REG_NOA_UNIT_SEL_8822B */ #define BIT_SHIFT_NOA_UNIT2_SEL_8822B 8 #define BIT_MASK_NOA_UNIT2_SEL_8822B 0x7 -#define BIT_NOA_UNIT2_SEL_8822B(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8822B) << BIT_SHIFT_NOA_UNIT2_SEL_8822B) -#define BIT_GET_NOA_UNIT2_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822B) & BIT_MASK_NOA_UNIT2_SEL_8822B) - - +#define BIT_NOA_UNIT2_SEL_8822B(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_8822B) << BIT_SHIFT_NOA_UNIT2_SEL_8822B) +#define BITS_NOA_UNIT2_SEL_8822B \ + (BIT_MASK_NOA_UNIT2_SEL_8822B << BIT_SHIFT_NOA_UNIT2_SEL_8822B) +#define BIT_CLEAR_NOA_UNIT2_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT2_SEL_8822B)) +#define BIT_GET_NOA_UNIT2_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822B) & BIT_MASK_NOA_UNIT2_SEL_8822B) +#define BIT_SET_NOA_UNIT2_SEL_8822B(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_8822B(x) | BIT_NOA_UNIT2_SEL_8822B(v)) #define BIT_SHIFT_NOA_UNIT1_SEL_8822B 4 #define BIT_MASK_NOA_UNIT1_SEL_8822B 0x7 -#define BIT_NOA_UNIT1_SEL_8822B(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8822B) << BIT_SHIFT_NOA_UNIT1_SEL_8822B) -#define BIT_GET_NOA_UNIT1_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822B) & BIT_MASK_NOA_UNIT1_SEL_8822B) - - +#define BIT_NOA_UNIT1_SEL_8822B(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_8822B) << BIT_SHIFT_NOA_UNIT1_SEL_8822B) +#define BITS_NOA_UNIT1_SEL_8822B \ + (BIT_MASK_NOA_UNIT1_SEL_8822B << BIT_SHIFT_NOA_UNIT1_SEL_8822B) +#define BIT_CLEAR_NOA_UNIT1_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT1_SEL_8822B)) +#define BIT_GET_NOA_UNIT1_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822B) & BIT_MASK_NOA_UNIT1_SEL_8822B) +#define BIT_SET_NOA_UNIT1_SEL_8822B(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_8822B(x) | BIT_NOA_UNIT1_SEL_8822B(v)) #define BIT_SHIFT_NOA_UNIT0_SEL_8822B 0 #define BIT_MASK_NOA_UNIT0_SEL_8822B 0x7 -#define BIT_NOA_UNIT0_SEL_8822B(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8822B) << BIT_SHIFT_NOA_UNIT0_SEL_8822B) -#define BIT_GET_NOA_UNIT0_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822B) & BIT_MASK_NOA_UNIT0_SEL_8822B) - - +#define BIT_NOA_UNIT0_SEL_8822B(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_8822B) << BIT_SHIFT_NOA_UNIT0_SEL_8822B) +#define BITS_NOA_UNIT0_SEL_8822B \ + (BIT_MASK_NOA_UNIT0_SEL_8822B << BIT_SHIFT_NOA_UNIT0_SEL_8822B) +#define BIT_CLEAR_NOA_UNIT0_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT0_SEL_8822B)) +#define BIT_GET_NOA_UNIT0_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822B) & BIT_MASK_NOA_UNIT0_SEL_8822B) +#define BIT_SET_NOA_UNIT0_SEL_8822B(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_8822B(x) | BIT_NOA_UNIT0_SEL_8822B(v)) /* 2 REG_P2POFF_DIS_TXTIME_8822B */ #define BIT_SHIFT_P2POFF_DIS_TXTIME_8822B 0 #define BIT_MASK_P2POFF_DIS_TXTIME_8822B 0xff -#define BIT_P2POFF_DIS_TXTIME_8822B(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822B) << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) -#define BIT_GET_P2POFF_DIS_TXTIME_8822B(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) & BIT_MASK_P2POFF_DIS_TXTIME_8822B) - - +#define BIT_P2POFF_DIS_TXTIME_8822B(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822B) \ + << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) +#define BITS_P2POFF_DIS_TXTIME_8822B \ + (BIT_MASK_P2POFF_DIS_TXTIME_8822B << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) +#define BIT_CLEAR_P2POFF_DIS_TXTIME_8822B(x) \ + ((x) & (~BITS_P2POFF_DIS_TXTIME_8822B)) +#define BIT_GET_P2POFF_DIS_TXTIME_8822B(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) & \ + BIT_MASK_P2POFF_DIS_TXTIME_8822B) +#define BIT_SET_P2POFF_DIS_TXTIME_8822B(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME_8822B(x) | BIT_P2POFF_DIS_TXTIME_8822B(v)) /* 2 REG_MBSSID_BCN_SPACE2_8822B */ #define BIT_SHIFT_BCN_SPACE_CLINT2_8822B 16 #define BIT_MASK_BCN_SPACE_CLINT2_8822B 0xfff -#define BIT_BCN_SPACE_CLINT2_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8822B) << BIT_SHIFT_BCN_SPACE_CLINT2_8822B) -#define BIT_GET_BCN_SPACE_CLINT2_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822B) & BIT_MASK_BCN_SPACE_CLINT2_8822B) - - +#define BIT_BCN_SPACE_CLINT2_8822B(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT2_8822B) \ + << BIT_SHIFT_BCN_SPACE_CLINT2_8822B) +#define BITS_BCN_SPACE_CLINT2_8822B \ + (BIT_MASK_BCN_SPACE_CLINT2_8822B << BIT_SHIFT_BCN_SPACE_CLINT2_8822B) +#define BIT_CLEAR_BCN_SPACE_CLINT2_8822B(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT2_8822B)) +#define BIT_GET_BCN_SPACE_CLINT2_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822B) & \ + BIT_MASK_BCN_SPACE_CLINT2_8822B) +#define BIT_SET_BCN_SPACE_CLINT2_8822B(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT2_8822B(x) | BIT_BCN_SPACE_CLINT2_8822B(v)) #define BIT_SHIFT_BCN_SPACE_CLINT1_8822B 0 #define BIT_MASK_BCN_SPACE_CLINT1_8822B 0xfff -#define BIT_BCN_SPACE_CLINT1_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8822B) << BIT_SHIFT_BCN_SPACE_CLINT1_8822B) -#define BIT_GET_BCN_SPACE_CLINT1_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822B) & BIT_MASK_BCN_SPACE_CLINT1_8822B) - - +#define BIT_BCN_SPACE_CLINT1_8822B(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT1_8822B) \ + << BIT_SHIFT_BCN_SPACE_CLINT1_8822B) +#define BITS_BCN_SPACE_CLINT1_8822B \ + (BIT_MASK_BCN_SPACE_CLINT1_8822B << BIT_SHIFT_BCN_SPACE_CLINT1_8822B) +#define BIT_CLEAR_BCN_SPACE_CLINT1_8822B(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT1_8822B)) +#define BIT_GET_BCN_SPACE_CLINT1_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822B) & \ + BIT_MASK_BCN_SPACE_CLINT1_8822B) +#define BIT_SET_BCN_SPACE_CLINT1_8822B(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT1_8822B(x) | BIT_BCN_SPACE_CLINT1_8822B(v)) /* 2 REG_MBSSID_BCN_SPACE3_8822B */ #define BIT_SHIFT_SUB_BCN_SPACE_8822B 16 #define BIT_MASK_SUB_BCN_SPACE_8822B 0xff -#define BIT_SUB_BCN_SPACE_8822B(x) (((x) & BIT_MASK_SUB_BCN_SPACE_8822B) << BIT_SHIFT_SUB_BCN_SPACE_8822B) -#define BIT_GET_SUB_BCN_SPACE_8822B(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822B) & BIT_MASK_SUB_BCN_SPACE_8822B) - - +#define BIT_SUB_BCN_SPACE_8822B(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_8822B) << BIT_SHIFT_SUB_BCN_SPACE_8822B) +#define BITS_SUB_BCN_SPACE_8822B \ + (BIT_MASK_SUB_BCN_SPACE_8822B << BIT_SHIFT_SUB_BCN_SPACE_8822B) +#define BIT_CLEAR_SUB_BCN_SPACE_8822B(x) ((x) & (~BITS_SUB_BCN_SPACE_8822B)) +#define BIT_GET_SUB_BCN_SPACE_8822B(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822B) & BIT_MASK_SUB_BCN_SPACE_8822B) +#define BIT_SET_SUB_BCN_SPACE_8822B(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_8822B(x) | BIT_SUB_BCN_SPACE_8822B(v)) #define BIT_SHIFT_BCN_SPACE_CLINT3_8822B 0 #define BIT_MASK_BCN_SPACE_CLINT3_8822B 0xfff -#define BIT_BCN_SPACE_CLINT3_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8822B) << BIT_SHIFT_BCN_SPACE_CLINT3_8822B) -#define BIT_GET_BCN_SPACE_CLINT3_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822B) & BIT_MASK_BCN_SPACE_CLINT3_8822B) - - +#define BIT_BCN_SPACE_CLINT3_8822B(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT3_8822B) \ + << BIT_SHIFT_BCN_SPACE_CLINT3_8822B) +#define BITS_BCN_SPACE_CLINT3_8822B \ + (BIT_MASK_BCN_SPACE_CLINT3_8822B << BIT_SHIFT_BCN_SPACE_CLINT3_8822B) +#define BIT_CLEAR_BCN_SPACE_CLINT3_8822B(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT3_8822B)) +#define BIT_GET_BCN_SPACE_CLINT3_8822B(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822B) & \ + BIT_MASK_BCN_SPACE_CLINT3_8822B) +#define BIT_SET_BCN_SPACE_CLINT3_8822B(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT3_8822B(x) | BIT_BCN_SPACE_CLINT3_8822B(v)) /* 2 REG_ACMHWCTRL_8822B */ #define BIT_BEQ_ACM_STATUS_8822B BIT(7) @@ -8039,92 +12794,158 @@ #define BIT_SHIFT_AVGPERIOD_8822B 0 #define BIT_MASK_AVGPERIOD_8822B 0xffff -#define BIT_AVGPERIOD_8822B(x) (((x) & BIT_MASK_AVGPERIOD_8822B) << BIT_SHIFT_AVGPERIOD_8822B) -#define BIT_GET_AVGPERIOD_8822B(x) (((x) >> BIT_SHIFT_AVGPERIOD_8822B) & BIT_MASK_AVGPERIOD_8822B) - - +#define BIT_AVGPERIOD_8822B(x) \ + (((x) & BIT_MASK_AVGPERIOD_8822B) << BIT_SHIFT_AVGPERIOD_8822B) +#define BITS_AVGPERIOD_8822B \ + (BIT_MASK_AVGPERIOD_8822B << BIT_SHIFT_AVGPERIOD_8822B) +#define BIT_CLEAR_AVGPERIOD_8822B(x) ((x) & (~BITS_AVGPERIOD_8822B)) +#define BIT_GET_AVGPERIOD_8822B(x) \ + (((x) >> BIT_SHIFT_AVGPERIOD_8822B) & BIT_MASK_AVGPERIOD_8822B) +#define BIT_SET_AVGPERIOD_8822B(x, v) \ + (BIT_CLEAR_AVGPERIOD_8822B(x) | BIT_AVGPERIOD_8822B(v)) /* 2 REG_VO_ADMTIME_8822B */ #define BIT_SHIFT_VO_ADMITTED_TIME_8822B 0 #define BIT_MASK_VO_ADMITTED_TIME_8822B 0xffff -#define BIT_VO_ADMITTED_TIME_8822B(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8822B) << BIT_SHIFT_VO_ADMITTED_TIME_8822B) -#define BIT_GET_VO_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822B) & BIT_MASK_VO_ADMITTED_TIME_8822B) - - +#define BIT_VO_ADMITTED_TIME_8822B(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME_8822B) \ + << BIT_SHIFT_VO_ADMITTED_TIME_8822B) +#define BITS_VO_ADMITTED_TIME_8822B \ + (BIT_MASK_VO_ADMITTED_TIME_8822B << BIT_SHIFT_VO_ADMITTED_TIME_8822B) +#define BIT_CLEAR_VO_ADMITTED_TIME_8822B(x) \ + ((x) & (~BITS_VO_ADMITTED_TIME_8822B)) +#define BIT_GET_VO_ADMITTED_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822B) & \ + BIT_MASK_VO_ADMITTED_TIME_8822B) +#define BIT_SET_VO_ADMITTED_TIME_8822B(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME_8822B(x) | BIT_VO_ADMITTED_TIME_8822B(v)) /* 2 REG_VI_ADMTIME_8822B */ #define BIT_SHIFT_VI_ADMITTED_TIME_8822B 0 #define BIT_MASK_VI_ADMITTED_TIME_8822B 0xffff -#define BIT_VI_ADMITTED_TIME_8822B(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8822B) << BIT_SHIFT_VI_ADMITTED_TIME_8822B) -#define BIT_GET_VI_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822B) & BIT_MASK_VI_ADMITTED_TIME_8822B) - - +#define BIT_VI_ADMITTED_TIME_8822B(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME_8822B) \ + << BIT_SHIFT_VI_ADMITTED_TIME_8822B) +#define BITS_VI_ADMITTED_TIME_8822B \ + (BIT_MASK_VI_ADMITTED_TIME_8822B << BIT_SHIFT_VI_ADMITTED_TIME_8822B) +#define BIT_CLEAR_VI_ADMITTED_TIME_8822B(x) \ + ((x) & (~BITS_VI_ADMITTED_TIME_8822B)) +#define BIT_GET_VI_ADMITTED_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822B) & \ + BIT_MASK_VI_ADMITTED_TIME_8822B) +#define BIT_SET_VI_ADMITTED_TIME_8822B(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME_8822B(x) | BIT_VI_ADMITTED_TIME_8822B(v)) /* 2 REG_BE_ADMTIME_8822B */ #define BIT_SHIFT_BE_ADMITTED_TIME_8822B 0 #define BIT_MASK_BE_ADMITTED_TIME_8822B 0xffff -#define BIT_BE_ADMITTED_TIME_8822B(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8822B) << BIT_SHIFT_BE_ADMITTED_TIME_8822B) -#define BIT_GET_BE_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822B) & BIT_MASK_BE_ADMITTED_TIME_8822B) - - +#define BIT_BE_ADMITTED_TIME_8822B(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME_8822B) \ + << BIT_SHIFT_BE_ADMITTED_TIME_8822B) +#define BITS_BE_ADMITTED_TIME_8822B \ + (BIT_MASK_BE_ADMITTED_TIME_8822B << BIT_SHIFT_BE_ADMITTED_TIME_8822B) +#define BIT_CLEAR_BE_ADMITTED_TIME_8822B(x) \ + ((x) & (~BITS_BE_ADMITTED_TIME_8822B)) +#define BIT_GET_BE_ADMITTED_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822B) & \ + BIT_MASK_BE_ADMITTED_TIME_8822B) +#define BIT_SET_BE_ADMITTED_TIME_8822B(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME_8822B(x) | BIT_BE_ADMITTED_TIME_8822B(v)) /* 2 REG_EDCA_RANDOM_GEN_8822B */ #define BIT_SHIFT_RANDOM_GEN_8822B 0 #define BIT_MASK_RANDOM_GEN_8822B 0xffffff -#define BIT_RANDOM_GEN_8822B(x) (((x) & BIT_MASK_RANDOM_GEN_8822B) << BIT_SHIFT_RANDOM_GEN_8822B) -#define BIT_GET_RANDOM_GEN_8822B(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8822B) & BIT_MASK_RANDOM_GEN_8822B) - - +#define BIT_RANDOM_GEN_8822B(x) \ + (((x) & BIT_MASK_RANDOM_GEN_8822B) << BIT_SHIFT_RANDOM_GEN_8822B) +#define BITS_RANDOM_GEN_8822B \ + (BIT_MASK_RANDOM_GEN_8822B << BIT_SHIFT_RANDOM_GEN_8822B) +#define BIT_CLEAR_RANDOM_GEN_8822B(x) ((x) & (~BITS_RANDOM_GEN_8822B)) +#define BIT_GET_RANDOM_GEN_8822B(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN_8822B) & BIT_MASK_RANDOM_GEN_8822B) +#define BIT_SET_RANDOM_GEN_8822B(x, v) \ + (BIT_CLEAR_RANDOM_GEN_8822B(x) | BIT_RANDOM_GEN_8822B(v)) /* 2 REG_TXCMD_NOA_SEL_8822B */ -#define BIT_SHIFT_NOA_SEL_8822B 4 -#define BIT_MASK_NOA_SEL_8822B 0x7 -#define BIT_NOA_SEL_8822B(x) (((x) & BIT_MASK_NOA_SEL_8822B) << BIT_SHIFT_NOA_SEL_8822B) -#define BIT_GET_NOA_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_SEL_8822B) & BIT_MASK_NOA_SEL_8822B) - - +#define BIT_SHIFT_NOA_SEL_V2_8822B 4 +#define BIT_MASK_NOA_SEL_V2_8822B 0x7 +#define BIT_NOA_SEL_V2_8822B(x) \ + (((x) & BIT_MASK_NOA_SEL_V2_8822B) << BIT_SHIFT_NOA_SEL_V2_8822B) +#define BITS_NOA_SEL_V2_8822B \ + (BIT_MASK_NOA_SEL_V2_8822B << BIT_SHIFT_NOA_SEL_V2_8822B) +#define BIT_CLEAR_NOA_SEL_V2_8822B(x) ((x) & (~BITS_NOA_SEL_V2_8822B)) +#define BIT_GET_NOA_SEL_V2_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V2_8822B) & BIT_MASK_NOA_SEL_V2_8822B) +#define BIT_SET_NOA_SEL_V2_8822B(x, v) \ + (BIT_CLEAR_NOA_SEL_V2_8822B(x) | BIT_NOA_SEL_V2_8822B(v)) #define BIT_SHIFT_TXCMD_SEG_SEL_8822B 0 #define BIT_MASK_TXCMD_SEG_SEL_8822B 0xf -#define BIT_TXCMD_SEG_SEL_8822B(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8822B) << BIT_SHIFT_TXCMD_SEG_SEL_8822B) -#define BIT_GET_TXCMD_SEG_SEL_8822B(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822B) & BIT_MASK_TXCMD_SEG_SEL_8822B) - - +#define BIT_TXCMD_SEG_SEL_8822B(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL_8822B) << BIT_SHIFT_TXCMD_SEG_SEL_8822B) +#define BITS_TXCMD_SEG_SEL_8822B \ + (BIT_MASK_TXCMD_SEG_SEL_8822B << BIT_SHIFT_TXCMD_SEG_SEL_8822B) +#define BIT_CLEAR_TXCMD_SEG_SEL_8822B(x) ((x) & (~BITS_TXCMD_SEG_SEL_8822B)) +#define BIT_GET_TXCMD_SEG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822B) & BIT_MASK_TXCMD_SEG_SEL_8822B) +#define BIT_SET_TXCMD_SEG_SEL_8822B(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL_8822B(x) | BIT_TXCMD_SEG_SEL_8822B(v)) /* 2 REG_NOA_PARAM_8822B */ #define BIT_SHIFT_NOA_COUNT_8822B (96 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_COUNT_8822B 0xff -#define BIT_NOA_COUNT_8822B(x) (((x) & BIT_MASK_NOA_COUNT_8822B) << BIT_SHIFT_NOA_COUNT_8822B) -#define BIT_GET_NOA_COUNT_8822B(x) (((x) >> BIT_SHIFT_NOA_COUNT_8822B) & BIT_MASK_NOA_COUNT_8822B) - - +#define BIT_NOA_COUNT_8822B(x) \ + (((x) & BIT_MASK_NOA_COUNT_8822B) << BIT_SHIFT_NOA_COUNT_8822B) +#define BITS_NOA_COUNT_8822B \ + (BIT_MASK_NOA_COUNT_8822B << BIT_SHIFT_NOA_COUNT_8822B) +#define BIT_CLEAR_NOA_COUNT_8822B(x) ((x) & (~BITS_NOA_COUNT_8822B)) +#define BIT_GET_NOA_COUNT_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_8822B) & BIT_MASK_NOA_COUNT_8822B) +#define BIT_SET_NOA_COUNT_8822B(x, v) \ + (BIT_CLEAR_NOA_COUNT_8822B(x) | BIT_NOA_COUNT_8822B(v)) #define BIT_SHIFT_NOA_START_TIME_8822B (64 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_START_TIME_8822B 0xffffffffL -#define BIT_NOA_START_TIME_8822B(x) (((x) & BIT_MASK_NOA_START_TIME_8822B) << BIT_SHIFT_NOA_START_TIME_8822B) -#define BIT_GET_NOA_START_TIME_8822B(x) (((x) >> BIT_SHIFT_NOA_START_TIME_8822B) & BIT_MASK_NOA_START_TIME_8822B) - - +#define BIT_NOA_START_TIME_8822B(x) \ + (((x) & BIT_MASK_NOA_START_TIME_8822B) \ + << BIT_SHIFT_NOA_START_TIME_8822B) +#define BITS_NOA_START_TIME_8822B \ + (BIT_MASK_NOA_START_TIME_8822B << BIT_SHIFT_NOA_START_TIME_8822B) +#define BIT_CLEAR_NOA_START_TIME_8822B(x) ((x) & (~BITS_NOA_START_TIME_8822B)) +#define BIT_GET_NOA_START_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_8822B) & \ + BIT_MASK_NOA_START_TIME_8822B) +#define BIT_SET_NOA_START_TIME_8822B(x, v) \ + (BIT_CLEAR_NOA_START_TIME_8822B(x) | BIT_NOA_START_TIME_8822B(v)) #define BIT_SHIFT_NOA_INTERVAL_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_NOA_INTERVAL_8822B 0xffffffffL -#define BIT_NOA_INTERVAL_8822B(x) (((x) & BIT_MASK_NOA_INTERVAL_8822B) << BIT_SHIFT_NOA_INTERVAL_8822B) -#define BIT_GET_NOA_INTERVAL_8822B(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_8822B) & BIT_MASK_NOA_INTERVAL_8822B) - - +#define BIT_NOA_INTERVAL_8822B(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_8822B) << BIT_SHIFT_NOA_INTERVAL_8822B) +#define BITS_NOA_INTERVAL_8822B \ + (BIT_MASK_NOA_INTERVAL_8822B << BIT_SHIFT_NOA_INTERVAL_8822B) +#define BIT_CLEAR_NOA_INTERVAL_8822B(x) ((x) & (~BITS_NOA_INTERVAL_8822B)) +#define BIT_GET_NOA_INTERVAL_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_8822B) & BIT_MASK_NOA_INTERVAL_8822B) +#define BIT_SET_NOA_INTERVAL_8822B(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_8822B(x) | BIT_NOA_INTERVAL_8822B(v)) #define BIT_SHIFT_NOA_DURATION_8822B 0 #define BIT_MASK_NOA_DURATION_8822B 0xffffffffL -#define BIT_NOA_DURATION_8822B(x) (((x) & BIT_MASK_NOA_DURATION_8822B) << BIT_SHIFT_NOA_DURATION_8822B) -#define BIT_GET_NOA_DURATION_8822B(x) (((x) >> BIT_SHIFT_NOA_DURATION_8822B) & BIT_MASK_NOA_DURATION_8822B) - - +#define BIT_NOA_DURATION_8822B(x) \ + (((x) & BIT_MASK_NOA_DURATION_8822B) << BIT_SHIFT_NOA_DURATION_8822B) +#define BITS_NOA_DURATION_8822B \ + (BIT_MASK_NOA_DURATION_8822B << BIT_SHIFT_NOA_DURATION_8822B) +#define BIT_CLEAR_NOA_DURATION_8822B(x) ((x) & (~BITS_NOA_DURATION_8822B)) +#define BIT_GET_NOA_DURATION_8822B(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_8822B) & BIT_MASK_NOA_DURATION_8822B) +#define BIT_SET_NOA_DURATION_8822B(x, v) \ + (BIT_CLEAR_NOA_DURATION_8822B(x) | BIT_NOA_DURATION_8822B(v)) /* 2 REG_P2P_RST_8822B */ #define BIT_P2P2_PWR_RST1_8822B BIT(5) @@ -8135,17 +12956,23 @@ #define BIT_P2P_PWR_RST0_V1_8822B BIT(0) /* 2 REG_SCHEDULER_RST_8822B */ -#define BIT_SYNC_CLI_8822B BIT(1) +#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8822B BIT(2) +#define BIT_SYNC_CLI_ONCE_BY_TBTT_8822B BIT(1) #define BIT_SCHEDULER_RST_V1_8822B BIT(0) /* 2 REG_SCH_TXCMD_8822B */ #define BIT_SHIFT_SCH_TXCMD_8822B 0 #define BIT_MASK_SCH_TXCMD_8822B 0xffffffffL -#define BIT_SCH_TXCMD_8822B(x) (((x) & BIT_MASK_SCH_TXCMD_8822B) << BIT_SHIFT_SCH_TXCMD_8822B) -#define BIT_GET_SCH_TXCMD_8822B(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8822B) & BIT_MASK_SCH_TXCMD_8822B) - - +#define BIT_SCH_TXCMD_8822B(x) \ + (((x) & BIT_MASK_SCH_TXCMD_8822B) << BIT_SHIFT_SCH_TXCMD_8822B) +#define BITS_SCH_TXCMD_8822B \ + (BIT_MASK_SCH_TXCMD_8822B << BIT_SHIFT_SCH_TXCMD_8822B) +#define BIT_CLEAR_SCH_TXCMD_8822B(x) ((x) & (~BITS_SCH_TXCMD_8822B)) +#define BIT_GET_SCH_TXCMD_8822B(x) \ + (((x) >> BIT_SHIFT_SCH_TXCMD_8822B) & BIT_MASK_SCH_TXCMD_8822B) +#define BIT_SET_SCH_TXCMD_8822B(x, v) \ + (BIT_CLEAR_SCH_TXCMD_8822B(x) | BIT_SCH_TXCMD_8822B(v)) /* 2 REG_PAGE5_DUMMY_8822B */ @@ -8153,37 +12980,62 @@ #define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B 0 #define BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B 0xffffffffL -#define BIT_CPUMGQ_TX_TIMER_V1_8822B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) -#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) - - +#define BIT_CPUMGQ_TX_TIMER_V1_8822B(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) +#define BITS_CPUMGQ_TX_TIMER_V1_8822B \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822B(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8822B)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) & \ + BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) +#define BIT_SET_CPUMGQ_TX_TIMER_V1_8822B(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822B(x) | \ + BIT_CPUMGQ_TX_TIMER_V1_8822B(v)) /* 2 REG_PS_TIMER_A_8822B */ #define BIT_SHIFT_PS_TIMER_A_V1_8822B 0 #define BIT_MASK_PS_TIMER_A_V1_8822B 0xffffffffL -#define BIT_PS_TIMER_A_V1_8822B(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8822B) << BIT_SHIFT_PS_TIMER_A_V1_8822B) -#define BIT_GET_PS_TIMER_A_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822B) & BIT_MASK_PS_TIMER_A_V1_8822B) - - +#define BIT_PS_TIMER_A_V1_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_A_V1_8822B) << BIT_SHIFT_PS_TIMER_A_V1_8822B) +#define BITS_PS_TIMER_A_V1_8822B \ + (BIT_MASK_PS_TIMER_A_V1_8822B << BIT_SHIFT_PS_TIMER_A_V1_8822B) +#define BIT_CLEAR_PS_TIMER_A_V1_8822B(x) ((x) & (~BITS_PS_TIMER_A_V1_8822B)) +#define BIT_GET_PS_TIMER_A_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822B) & BIT_MASK_PS_TIMER_A_V1_8822B) +#define BIT_SET_PS_TIMER_A_V1_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_A_V1_8822B(x) | BIT_PS_TIMER_A_V1_8822B(v)) /* 2 REG_PS_TIMER_B_8822B */ #define BIT_SHIFT_PS_TIMER_B_V1_8822B 0 #define BIT_MASK_PS_TIMER_B_V1_8822B 0xffffffffL -#define BIT_PS_TIMER_B_V1_8822B(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8822B) << BIT_SHIFT_PS_TIMER_B_V1_8822B) -#define BIT_GET_PS_TIMER_B_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822B) & BIT_MASK_PS_TIMER_B_V1_8822B) - - +#define BIT_PS_TIMER_B_V1_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_B_V1_8822B) << BIT_SHIFT_PS_TIMER_B_V1_8822B) +#define BITS_PS_TIMER_B_V1_8822B \ + (BIT_MASK_PS_TIMER_B_V1_8822B << BIT_SHIFT_PS_TIMER_B_V1_8822B) +#define BIT_CLEAR_PS_TIMER_B_V1_8822B(x) ((x) & (~BITS_PS_TIMER_B_V1_8822B)) +#define BIT_GET_PS_TIMER_B_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822B) & BIT_MASK_PS_TIMER_B_V1_8822B) +#define BIT_SET_PS_TIMER_B_V1_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_B_V1_8822B(x) | BIT_PS_TIMER_B_V1_8822B(v)) /* 2 REG_PS_TIMER_C_8822B */ #define BIT_SHIFT_PS_TIMER_C_V1_8822B 0 #define BIT_MASK_PS_TIMER_C_V1_8822B 0xffffffffL -#define BIT_PS_TIMER_C_V1_8822B(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8822B) << BIT_SHIFT_PS_TIMER_C_V1_8822B) -#define BIT_GET_PS_TIMER_C_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822B) & BIT_MASK_PS_TIMER_C_V1_8822B) - - +#define BIT_PS_TIMER_C_V1_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_C_V1_8822B) << BIT_SHIFT_PS_TIMER_C_V1_8822B) +#define BITS_PS_TIMER_C_V1_8822B \ + (BIT_MASK_PS_TIMER_C_V1_8822B << BIT_SHIFT_PS_TIMER_C_V1_8822B) +#define BIT_CLEAR_PS_TIMER_C_V1_8822B(x) ((x) & (~BITS_PS_TIMER_C_V1_8822B)) +#define BIT_GET_PS_TIMER_C_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822B) & BIT_MASK_PS_TIMER_C_V1_8822B) +#define BIT_SET_PS_TIMER_C_V1_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_C_V1_8822B(x) | BIT_PS_TIMER_C_V1_8822B(v)) /* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B */ #define BIT_CPUMGQ_TIMER_EN_8822B BIT(31) @@ -8191,70 +13043,169 @@ #define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B 24 #define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B 0x7 -#define BIT_CPUMGQ_TIMER_TSF_SEL_8822B(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) -#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) - +#define BIT_CPUMGQ_TIMER_TSF_SEL_8822B(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) +#define BITS_CPUMGQ_TIMER_TSF_SEL_8822B \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822B(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8822B)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8822B(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822B(x) | \ + BIT_CPUMGQ_TIMER_TSF_SEL_8822B(v)) #define BIT_PS_TIMER_C_EN_8822B BIT(23) #define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B 16 #define BIT_MASK_PS_TIMER_C_TSF_SEL_8822B 0x7 -#define BIT_PS_TIMER_C_TSF_SEL_8822B(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) -#define BIT_GET_PS_TIMER_C_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) - +#define BIT_PS_TIMER_C_TSF_SEL_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) +#define BITS_PS_TIMER_C_TSF_SEL_8822B \ + (BIT_MASK_PS_TIMER_C_TSF_SEL_8822B \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) +#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822B(x) \ + ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8822B)) +#define BIT_GET_PS_TIMER_C_TSF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) & \ + BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) +#define BIT_SET_PS_TIMER_C_TSF_SEL_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822B(x) | \ + BIT_PS_TIMER_C_TSF_SEL_8822B(v)) #define BIT_PS_TIMER_B_EN_8822B BIT(15) #define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B 8 #define BIT_MASK_PS_TIMER_B_TSF_SEL_8822B 0x7 -#define BIT_PS_TIMER_B_TSF_SEL_8822B(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) -#define BIT_GET_PS_TIMER_B_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) - +#define BIT_PS_TIMER_B_TSF_SEL_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) +#define BITS_PS_TIMER_B_TSF_SEL_8822B \ + (BIT_MASK_PS_TIMER_B_TSF_SEL_8822B \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822B(x) \ + ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8822B)) +#define BIT_GET_PS_TIMER_B_TSF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) & \ + BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) +#define BIT_SET_PS_TIMER_B_TSF_SEL_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822B(x) | \ + BIT_PS_TIMER_B_TSF_SEL_8822B(v)) #define BIT_PS_TIMER_A_EN_8822B BIT(7) #define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B 0 #define BIT_MASK_PS_TIMER_A_TSF_SEL_8822B 0x7 -#define BIT_PS_TIMER_A_TSF_SEL_8822B(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) -#define BIT_GET_PS_TIMER_A_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) - - +#define BIT_PS_TIMER_A_TSF_SEL_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) +#define BITS_PS_TIMER_A_TSF_SEL_8822B \ + (BIT_MASK_PS_TIMER_A_TSF_SEL_8822B \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822B(x) \ + ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8822B)) +#define BIT_GET_PS_TIMER_A_TSF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) & \ + BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) +#define BIT_SET_PS_TIMER_A_TSF_SEL_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822B(x) | \ + BIT_PS_TIMER_A_TSF_SEL_8822B(v)) /* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822B */ #define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B 0 #define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B 0xff -#define BIT_CPUMGQ_TX_TIMER_EARLY_8822B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) -#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) - - +#define BIT_CPUMGQ_TX_TIMER_EARLY_8822B(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) +#define BITS_CPUMGQ_TX_TIMER_EARLY_8822B \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822B(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8822B)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822B(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8822B(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822B(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_8822B(v)) /* 2 REG_PS_TIMER_A_EARLY_8822B */ #define BIT_SHIFT_PS_TIMER_A_EARLY_8822B 0 #define BIT_MASK_PS_TIMER_A_EARLY_8822B 0xff -#define BIT_PS_TIMER_A_EARLY_8822B(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8822B) << BIT_SHIFT_PS_TIMER_A_EARLY_8822B) -#define BIT_GET_PS_TIMER_A_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822B) & BIT_MASK_PS_TIMER_A_EARLY_8822B) - - +#define BIT_PS_TIMER_A_EARLY_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_A_EARLY_8822B) \ + << BIT_SHIFT_PS_TIMER_A_EARLY_8822B) +#define BITS_PS_TIMER_A_EARLY_8822B \ + (BIT_MASK_PS_TIMER_A_EARLY_8822B << BIT_SHIFT_PS_TIMER_A_EARLY_8822B) +#define BIT_CLEAR_PS_TIMER_A_EARLY_8822B(x) \ + ((x) & (~BITS_PS_TIMER_A_EARLY_8822B)) +#define BIT_GET_PS_TIMER_A_EARLY_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822B) & \ + BIT_MASK_PS_TIMER_A_EARLY_8822B) +#define BIT_SET_PS_TIMER_A_EARLY_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_A_EARLY_8822B(x) | BIT_PS_TIMER_A_EARLY_8822B(v)) /* 2 REG_PS_TIMER_B_EARLY_8822B */ #define BIT_SHIFT_PS_TIMER_B_EARLY_8822B 0 #define BIT_MASK_PS_TIMER_B_EARLY_8822B 0xff -#define BIT_PS_TIMER_B_EARLY_8822B(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8822B) << BIT_SHIFT_PS_TIMER_B_EARLY_8822B) -#define BIT_GET_PS_TIMER_B_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822B) & BIT_MASK_PS_TIMER_B_EARLY_8822B) - - +#define BIT_PS_TIMER_B_EARLY_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_B_EARLY_8822B) \ + << BIT_SHIFT_PS_TIMER_B_EARLY_8822B) +#define BITS_PS_TIMER_B_EARLY_8822B \ + (BIT_MASK_PS_TIMER_B_EARLY_8822B << BIT_SHIFT_PS_TIMER_B_EARLY_8822B) +#define BIT_CLEAR_PS_TIMER_B_EARLY_8822B(x) \ + ((x) & (~BITS_PS_TIMER_B_EARLY_8822B)) +#define BIT_GET_PS_TIMER_B_EARLY_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822B) & \ + BIT_MASK_PS_TIMER_B_EARLY_8822B) +#define BIT_SET_PS_TIMER_B_EARLY_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_B_EARLY_8822B(x) | BIT_PS_TIMER_B_EARLY_8822B(v)) /* 2 REG_PS_TIMER_C_EARLY_8822B */ #define BIT_SHIFT_PS_TIMER_C_EARLY_8822B 0 #define BIT_MASK_PS_TIMER_C_EARLY_8822B 0xff -#define BIT_PS_TIMER_C_EARLY_8822B(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8822B) << BIT_SHIFT_PS_TIMER_C_EARLY_8822B) -#define BIT_GET_PS_TIMER_C_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822B) & BIT_MASK_PS_TIMER_C_EARLY_8822B) +#define BIT_PS_TIMER_C_EARLY_8822B(x) \ + (((x) & BIT_MASK_PS_TIMER_C_EARLY_8822B) \ + << BIT_SHIFT_PS_TIMER_C_EARLY_8822B) +#define BITS_PS_TIMER_C_EARLY_8822B \ + (BIT_MASK_PS_TIMER_C_EARLY_8822B << BIT_SHIFT_PS_TIMER_C_EARLY_8822B) +#define BIT_CLEAR_PS_TIMER_C_EARLY_8822B(x) \ + ((x) & (~BITS_PS_TIMER_C_EARLY_8822B)) +#define BIT_GET_PS_TIMER_C_EARLY_8822B(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822B) & \ + BIT_MASK_PS_TIMER_C_EARLY_8822B) +#define BIT_SET_PS_TIMER_C_EARLY_8822B(x, v) \ + (BIT_CLEAR_PS_TIMER_C_EARLY_8822B(x) | BIT_PS_TIMER_C_EARLY_8822B(v)) + +/* 2 REG_CPUMGQ_PARAMETER_8822B */ +/* 2 REG_NOT_VALID_8822B */ +#define BIT_MAC_STOP_CPUMGQ_8822B BIT(16) + +#define BIT_SHIFT_CW_8822B 8 +#define BIT_MASK_CW_8822B 0xff +#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B) +#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B) +#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B)) +#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B) +#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v)) +#define BIT_SHIFT_AIFS_8822B 0 +#define BIT_MASK_AIFS_8822B 0xff +#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B) +#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B) +#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B)) +#define BIT_GET_AIFS_8822B(x) \ + (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B) +#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -8268,10 +13219,17 @@ #define BIT_SHIFT_APPEND_MHDR_LEN_8822B 0 #define BIT_MASK_APPEND_MHDR_LEN_8822B 0x7 -#define BIT_APPEND_MHDR_LEN_8822B(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8822B) << BIT_SHIFT_APPEND_MHDR_LEN_8822B) -#define BIT_GET_APPEND_MHDR_LEN_8822B(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822B) & BIT_MASK_APPEND_MHDR_LEN_8822B) - - +#define BIT_APPEND_MHDR_LEN_8822B(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN_8822B) \ + << BIT_SHIFT_APPEND_MHDR_LEN_8822B) +#define BITS_APPEND_MHDR_LEN_8822B \ + (BIT_MASK_APPEND_MHDR_LEN_8822B << BIT_SHIFT_APPEND_MHDR_LEN_8822B) +#define BIT_CLEAR_APPEND_MHDR_LEN_8822B(x) ((x) & (~BITS_APPEND_MHDR_LEN_8822B)) +#define BIT_GET_APPEND_MHDR_LEN_8822B(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822B) & \ + BIT_MASK_APPEND_MHDR_LEN_8822B) +#define BIT_SET_APPEND_MHDR_LEN_8822B(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN_8822B(x) | BIT_APPEND_MHDR_LEN_8822B(v)) /* 2 REG_WMAC_CR_8822B (WMAC CR AND APSD CONTROL REGISTER) */ #define BIT_IC_MACPHY_M_8822B BIT(0) @@ -8344,64 +13302,96 @@ #define BIT_SHIFT_DRVINFO_SZ_V1_8822B 0 #define BIT_MASK_DRVINFO_SZ_V1_8822B 0xf -#define BIT_DRVINFO_SZ_V1_8822B(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8822B) << BIT_SHIFT_DRVINFO_SZ_V1_8822B) -#define BIT_GET_DRVINFO_SZ_V1_8822B(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822B) & BIT_MASK_DRVINFO_SZ_V1_8822B) - - +#define BIT_DRVINFO_SZ_V1_8822B(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1_8822B) << BIT_SHIFT_DRVINFO_SZ_V1_8822B) +#define BITS_DRVINFO_SZ_V1_8822B \ + (BIT_MASK_DRVINFO_SZ_V1_8822B << BIT_SHIFT_DRVINFO_SZ_V1_8822B) +#define BIT_CLEAR_DRVINFO_SZ_V1_8822B(x) ((x) & (~BITS_DRVINFO_SZ_V1_8822B)) +#define BIT_GET_DRVINFO_SZ_V1_8822B(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822B) & BIT_MASK_DRVINFO_SZ_V1_8822B) +#define BIT_SET_DRVINFO_SZ_V1_8822B(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1_8822B(x) | BIT_DRVINFO_SZ_V1_8822B(v)) /* 2 REG_RX_DLK_TIME_8822B (RX DEADLOCK TIME REGISTER) */ #define BIT_SHIFT_RX_DLK_TIME_8822B 0 #define BIT_MASK_RX_DLK_TIME_8822B 0xff -#define BIT_RX_DLK_TIME_8822B(x) (((x) & BIT_MASK_RX_DLK_TIME_8822B) << BIT_SHIFT_RX_DLK_TIME_8822B) -#define BIT_GET_RX_DLK_TIME_8822B(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8822B) & BIT_MASK_RX_DLK_TIME_8822B) - - +#define BIT_RX_DLK_TIME_8822B(x) \ + (((x) & BIT_MASK_RX_DLK_TIME_8822B) << BIT_SHIFT_RX_DLK_TIME_8822B) +#define BITS_RX_DLK_TIME_8822B \ + (BIT_MASK_RX_DLK_TIME_8822B << BIT_SHIFT_RX_DLK_TIME_8822B) +#define BIT_CLEAR_RX_DLK_TIME_8822B(x) ((x) & (~BITS_RX_DLK_TIME_8822B)) +#define BIT_GET_RX_DLK_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME_8822B) & BIT_MASK_RX_DLK_TIME_8822B) +#define BIT_SET_RX_DLK_TIME_8822B(x, v) \ + (BIT_CLEAR_RX_DLK_TIME_8822B(x) | BIT_RX_DLK_TIME_8822B(v)) /* 2 REG_RX_PKT_LIMIT_8822B (RX PACKET LENGTH LIMIT REGISTER) */ #define BIT_SHIFT_RXPKTLMT_8822B 0 #define BIT_MASK_RXPKTLMT_8822B 0x3f -#define BIT_RXPKTLMT_8822B(x) (((x) & BIT_MASK_RXPKTLMT_8822B) << BIT_SHIFT_RXPKTLMT_8822B) -#define BIT_GET_RXPKTLMT_8822B(x) (((x) >> BIT_SHIFT_RXPKTLMT_8822B) & BIT_MASK_RXPKTLMT_8822B) - - +#define BIT_RXPKTLMT_8822B(x) \ + (((x) & BIT_MASK_RXPKTLMT_8822B) << BIT_SHIFT_RXPKTLMT_8822B) +#define BITS_RXPKTLMT_8822B \ + (BIT_MASK_RXPKTLMT_8822B << BIT_SHIFT_RXPKTLMT_8822B) +#define BIT_CLEAR_RXPKTLMT_8822B(x) ((x) & (~BITS_RXPKTLMT_8822B)) +#define BIT_GET_RXPKTLMT_8822B(x) \ + (((x) >> BIT_SHIFT_RXPKTLMT_8822B) & BIT_MASK_RXPKTLMT_8822B) +#define BIT_SET_RXPKTLMT_8822B(x, v) \ + (BIT_CLEAR_RXPKTLMT_8822B(x) | BIT_RXPKTLMT_8822B(v)) /* 2 REG_MACID_8822B (MAC ID REGISTER) */ #define BIT_SHIFT_MACID_8822B 0 #define BIT_MASK_MACID_8822B 0xffffffffffffL -#define BIT_MACID_8822B(x) (((x) & BIT_MASK_MACID_8822B) << BIT_SHIFT_MACID_8822B) -#define BIT_GET_MACID_8822B(x) (((x) >> BIT_SHIFT_MACID_8822B) & BIT_MASK_MACID_8822B) - - +#define BIT_MACID_8822B(x) \ + (((x) & BIT_MASK_MACID_8822B) << BIT_SHIFT_MACID_8822B) +#define BITS_MACID_8822B (BIT_MASK_MACID_8822B << BIT_SHIFT_MACID_8822B) +#define BIT_CLEAR_MACID_8822B(x) ((x) & (~BITS_MACID_8822B)) +#define BIT_GET_MACID_8822B(x) \ + (((x) >> BIT_SHIFT_MACID_8822B) & BIT_MASK_MACID_8822B) +#define BIT_SET_MACID_8822B(x, v) \ + (BIT_CLEAR_MACID_8822B(x) | BIT_MACID_8822B(v)) /* 2 REG_BSSID_8822B (BSSID REGISTER) */ #define BIT_SHIFT_BSSID_8822B 0 #define BIT_MASK_BSSID_8822B 0xffffffffffffL -#define BIT_BSSID_8822B(x) (((x) & BIT_MASK_BSSID_8822B) << BIT_SHIFT_BSSID_8822B) -#define BIT_GET_BSSID_8822B(x) (((x) >> BIT_SHIFT_BSSID_8822B) & BIT_MASK_BSSID_8822B) - - +#define BIT_BSSID_8822B(x) \ + (((x) & BIT_MASK_BSSID_8822B) << BIT_SHIFT_BSSID_8822B) +#define BITS_BSSID_8822B (BIT_MASK_BSSID_8822B << BIT_SHIFT_BSSID_8822B) +#define BIT_CLEAR_BSSID_8822B(x) ((x) & (~BITS_BSSID_8822B)) +#define BIT_GET_BSSID_8822B(x) \ + (((x) >> BIT_SHIFT_BSSID_8822B) & BIT_MASK_BSSID_8822B) +#define BIT_SET_BSSID_8822B(x, v) \ + (BIT_CLEAR_BSSID_8822B(x) | BIT_BSSID_8822B(v)) /* 2 REG_MAR_8822B (MULTICAST ADDRESS REGISTER) */ #define BIT_SHIFT_MAR_8822B 0 #define BIT_MASK_MAR_8822B 0xffffffffffffffffL #define BIT_MAR_8822B(x) (((x) & BIT_MASK_MAR_8822B) << BIT_SHIFT_MAR_8822B) +#define BITS_MAR_8822B (BIT_MASK_MAR_8822B << BIT_SHIFT_MAR_8822B) +#define BIT_CLEAR_MAR_8822B(x) ((x) & (~BITS_MAR_8822B)) #define BIT_GET_MAR_8822B(x) (((x) >> BIT_SHIFT_MAR_8822B) & BIT_MASK_MAR_8822B) - - +#define BIT_SET_MAR_8822B(x, v) (BIT_CLEAR_MAR_8822B(x) | BIT_MAR_8822B(v)) /* 2 REG_MBIDCAMCFG_1_8822B (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_SHIFT_MBIDCAM_RWDATA_L_8822B 0 #define BIT_MASK_MBIDCAM_RWDATA_L_8822B 0xffffffffL -#define BIT_MBIDCAM_RWDATA_L_8822B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822B) << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) -#define BIT_GET_MBIDCAM_RWDATA_L_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) & BIT_MASK_MBIDCAM_RWDATA_L_8822B) - - +#define BIT_MBIDCAM_RWDATA_L_8822B(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822B) \ + << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) +#define BITS_MBIDCAM_RWDATA_L_8822B \ + (BIT_MASK_MBIDCAM_RWDATA_L_8822B << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) +#define BIT_CLEAR_MBIDCAM_RWDATA_L_8822B(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_L_8822B)) +#define BIT_GET_MBIDCAM_RWDATA_L_8822B(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) & \ + BIT_MASK_MBIDCAM_RWDATA_L_8822B) +#define BIT_SET_MBIDCAM_RWDATA_L_8822B(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_L_8822B(x) | BIT_MBIDCAM_RWDATA_L_8822B(v)) /* 2 REG_MBIDCAMCFG_2_8822B (MBSSID CAM CONFIGURATION REGISTER) */ #define BIT_MBIDCAM_POLL_8822B BIT(31) @@ -8409,9 +13399,15 @@ #define BIT_SHIFT_MBIDCAM_ADDR_8822B 24 #define BIT_MASK_MBIDCAM_ADDR_8822B 0x1f -#define BIT_MBIDCAM_ADDR_8822B(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8822B) << BIT_SHIFT_MBIDCAM_ADDR_8822B) -#define BIT_GET_MBIDCAM_ADDR_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8822B) & BIT_MASK_MBIDCAM_ADDR_8822B) - +#define BIT_MBIDCAM_ADDR_8822B(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_8822B) << BIT_SHIFT_MBIDCAM_ADDR_8822B) +#define BITS_MBIDCAM_ADDR_8822B \ + (BIT_MASK_MBIDCAM_ADDR_8822B << BIT_SHIFT_MBIDCAM_ADDR_8822B) +#define BIT_CLEAR_MBIDCAM_ADDR_8822B(x) ((x) & (~BITS_MBIDCAM_ADDR_8822B)) +#define BIT_GET_MBIDCAM_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8822B) & BIT_MASK_MBIDCAM_ADDR_8822B) +#define BIT_SET_MBIDCAM_ADDR_8822B(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_8822B(x) | BIT_MBIDCAM_ADDR_8822B(v)) #define BIT_MBIDCAM_VALID_8822B BIT(23) #define BIT_LSIC_TXOP_EN_8822B BIT(17) @@ -8419,171 +13415,276 @@ #define BIT_SHIFT_MBIDCAM_RWDATA_H_8822B 0 #define BIT_MASK_MBIDCAM_RWDATA_H_8822B 0xffff -#define BIT_MBIDCAM_RWDATA_H_8822B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822B) << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) -#define BIT_GET_MBIDCAM_RWDATA_H_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) & BIT_MASK_MBIDCAM_RWDATA_H_8822B) - - +#define BIT_MBIDCAM_RWDATA_H_8822B(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822B) \ + << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) +#define BITS_MBIDCAM_RWDATA_H_8822B \ + (BIT_MASK_MBIDCAM_RWDATA_H_8822B << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) +#define BIT_CLEAR_MBIDCAM_RWDATA_H_8822B(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_H_8822B)) +#define BIT_GET_MBIDCAM_RWDATA_H_8822B(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) & \ + BIT_MASK_MBIDCAM_RWDATA_H_8822B) +#define BIT_SET_MBIDCAM_RWDATA_H_8822B(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_H_8822B(x) | BIT_MBIDCAM_RWDATA_H_8822B(v)) /* 2 REG_ZLD_NUM_8822B */ #define BIT_SHIFT_ZLD_NUM_8822B 0 #define BIT_MASK_ZLD_NUM_8822B 0xff -#define BIT_ZLD_NUM_8822B(x) (((x) & BIT_MASK_ZLD_NUM_8822B) << BIT_SHIFT_ZLD_NUM_8822B) -#define BIT_GET_ZLD_NUM_8822B(x) (((x) >> BIT_SHIFT_ZLD_NUM_8822B) & BIT_MASK_ZLD_NUM_8822B) - - +#define BIT_ZLD_NUM_8822B(x) \ + (((x) & BIT_MASK_ZLD_NUM_8822B) << BIT_SHIFT_ZLD_NUM_8822B) +#define BITS_ZLD_NUM_8822B (BIT_MASK_ZLD_NUM_8822B << BIT_SHIFT_ZLD_NUM_8822B) +#define BIT_CLEAR_ZLD_NUM_8822B(x) ((x) & (~BITS_ZLD_NUM_8822B)) +#define BIT_GET_ZLD_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_ZLD_NUM_8822B) & BIT_MASK_ZLD_NUM_8822B) +#define BIT_SET_ZLD_NUM_8822B(x, v) \ + (BIT_CLEAR_ZLD_NUM_8822B(x) | BIT_ZLD_NUM_8822B(v)) /* 2 REG_UDF_THSD_8822B */ #define BIT_SHIFT_UDF_THSD_8822B 0 #define BIT_MASK_UDF_THSD_8822B 0xff -#define BIT_UDF_THSD_8822B(x) (((x) & BIT_MASK_UDF_THSD_8822B) << BIT_SHIFT_UDF_THSD_8822B) -#define BIT_GET_UDF_THSD_8822B(x) (((x) >> BIT_SHIFT_UDF_THSD_8822B) & BIT_MASK_UDF_THSD_8822B) - - +#define BIT_UDF_THSD_8822B(x) \ + (((x) & BIT_MASK_UDF_THSD_8822B) << BIT_SHIFT_UDF_THSD_8822B) +#define BITS_UDF_THSD_8822B \ + (BIT_MASK_UDF_THSD_8822B << BIT_SHIFT_UDF_THSD_8822B) +#define BIT_CLEAR_UDF_THSD_8822B(x) ((x) & (~BITS_UDF_THSD_8822B)) +#define BIT_GET_UDF_THSD_8822B(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_8822B) & BIT_MASK_UDF_THSD_8822B) +#define BIT_SET_UDF_THSD_8822B(x, v) \ + (BIT_CLEAR_UDF_THSD_8822B(x) | BIT_UDF_THSD_8822B(v)) /* 2 REG_WMAC_TCR_TSFT_OFS_8822B */ #define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B 0 #define BIT_MASK_WMAC_TCR_TSFT_OFS_8822B 0xffff -#define BIT_WMAC_TCR_TSFT_OFS_8822B(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) -#define BIT_GET_WMAC_TCR_TSFT_OFS_8822B(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) - - +#define BIT_WMAC_TCR_TSFT_OFS_8822B(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) \ + << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) +#define BITS_WMAC_TCR_TSFT_OFS_8822B \ + (BIT_MASK_WMAC_TCR_TSFT_OFS_8822B << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822B(x) \ + ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8822B)) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) & \ + BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) +#define BIT_SET_WMAC_TCR_TSFT_OFS_8822B(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822B(x) | BIT_WMAC_TCR_TSFT_OFS_8822B(v)) /* 2 REG_MCU_TEST_2_V1_8822B */ #define BIT_SHIFT_MCU_RSVD_2_V1_8822B 0 #define BIT_MASK_MCU_RSVD_2_V1_8822B 0xffff -#define BIT_MCU_RSVD_2_V1_8822B(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8822B) << BIT_SHIFT_MCU_RSVD_2_V1_8822B) -#define BIT_GET_MCU_RSVD_2_V1_8822B(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8822B) & BIT_MASK_MCU_RSVD_2_V1_8822B) - - +#define BIT_MCU_RSVD_2_V1_8822B(x) \ + (((x) & BIT_MASK_MCU_RSVD_2_V1_8822B) << BIT_SHIFT_MCU_RSVD_2_V1_8822B) +#define BITS_MCU_RSVD_2_V1_8822B \ + (BIT_MASK_MCU_RSVD_2_V1_8822B << BIT_SHIFT_MCU_RSVD_2_V1_8822B) +#define BIT_CLEAR_MCU_RSVD_2_V1_8822B(x) ((x) & (~BITS_MCU_RSVD_2_V1_8822B)) +#define BIT_GET_MCU_RSVD_2_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8822B) & BIT_MASK_MCU_RSVD_2_V1_8822B) +#define BIT_SET_MCU_RSVD_2_V1_8822B(x, v) \ + (BIT_CLEAR_MCU_RSVD_2_V1_8822B(x) | BIT_MCU_RSVD_2_V1_8822B(v)) /* 2 REG_WMAC_TXTIMEOUT_8822B */ #define BIT_SHIFT_WMAC_TXTIMEOUT_8822B 0 #define BIT_MASK_WMAC_TXTIMEOUT_8822B 0xff -#define BIT_WMAC_TXTIMEOUT_8822B(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8822B) << BIT_SHIFT_WMAC_TXTIMEOUT_8822B) -#define BIT_GET_WMAC_TXTIMEOUT_8822B(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822B) & BIT_MASK_WMAC_TXTIMEOUT_8822B) - - +#define BIT_WMAC_TXTIMEOUT_8822B(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT_8822B) \ + << BIT_SHIFT_WMAC_TXTIMEOUT_8822B) +#define BITS_WMAC_TXTIMEOUT_8822B \ + (BIT_MASK_WMAC_TXTIMEOUT_8822B << BIT_SHIFT_WMAC_TXTIMEOUT_8822B) +#define BIT_CLEAR_WMAC_TXTIMEOUT_8822B(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8822B)) +#define BIT_GET_WMAC_TXTIMEOUT_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822B) & \ + BIT_MASK_WMAC_TXTIMEOUT_8822B) +#define BIT_SET_WMAC_TXTIMEOUT_8822B(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT_8822B(x) | BIT_WMAC_TXTIMEOUT_8822B(v)) /* 2 REG_STMP_THSD_8822B */ #define BIT_SHIFT_STMP_THSD_8822B 0 #define BIT_MASK_STMP_THSD_8822B 0xff -#define BIT_STMP_THSD_8822B(x) (((x) & BIT_MASK_STMP_THSD_8822B) << BIT_SHIFT_STMP_THSD_8822B) -#define BIT_GET_STMP_THSD_8822B(x) (((x) >> BIT_SHIFT_STMP_THSD_8822B) & BIT_MASK_STMP_THSD_8822B) - - +#define BIT_STMP_THSD_8822B(x) \ + (((x) & BIT_MASK_STMP_THSD_8822B) << BIT_SHIFT_STMP_THSD_8822B) +#define BITS_STMP_THSD_8822B \ + (BIT_MASK_STMP_THSD_8822B << BIT_SHIFT_STMP_THSD_8822B) +#define BIT_CLEAR_STMP_THSD_8822B(x) ((x) & (~BITS_STMP_THSD_8822B)) +#define BIT_GET_STMP_THSD_8822B(x) \ + (((x) >> BIT_SHIFT_STMP_THSD_8822B) & BIT_MASK_STMP_THSD_8822B) +#define BIT_SET_STMP_THSD_8822B(x, v) \ + (BIT_CLEAR_STMP_THSD_8822B(x) | BIT_STMP_THSD_8822B(v)) /* 2 REG_MAC_SPEC_SIFS_8822B (SPECIFICATION SIFS REGISTER) */ #define BIT_SHIFT_SPEC_SIFS_OFDM_8822B 8 #define BIT_MASK_SPEC_SIFS_OFDM_8822B 0xff -#define BIT_SPEC_SIFS_OFDM_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8822B) << BIT_SHIFT_SPEC_SIFS_OFDM_8822B) -#define BIT_GET_SPEC_SIFS_OFDM_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822B) & BIT_MASK_SPEC_SIFS_OFDM_8822B) - - +#define BIT_SPEC_SIFS_OFDM_8822B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_8822B) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_8822B) +#define BITS_SPEC_SIFS_OFDM_8822B \ + (BIT_MASK_SPEC_SIFS_OFDM_8822B << BIT_SHIFT_SPEC_SIFS_OFDM_8822B) +#define BIT_CLEAR_SPEC_SIFS_OFDM_8822B(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8822B)) +#define BIT_GET_SPEC_SIFS_OFDM_8822B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822B) & \ + BIT_MASK_SPEC_SIFS_OFDM_8822B) +#define BIT_SET_SPEC_SIFS_OFDM_8822B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_8822B(x) | BIT_SPEC_SIFS_OFDM_8822B(v)) #define BIT_SHIFT_SPEC_SIFS_CCK_8822B 0 #define BIT_MASK_SPEC_SIFS_CCK_8822B 0xff -#define BIT_SPEC_SIFS_CCK_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_8822B) -#define BIT_GET_SPEC_SIFS_CCK_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822B) & BIT_MASK_SPEC_SIFS_CCK_8822B) - - +#define BIT_SPEC_SIFS_CCK_8822B(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_8822B) +#define BITS_SPEC_SIFS_CCK_8822B \ + (BIT_MASK_SPEC_SIFS_CCK_8822B << BIT_SHIFT_SPEC_SIFS_CCK_8822B) +#define BIT_CLEAR_SPEC_SIFS_CCK_8822B(x) ((x) & (~BITS_SPEC_SIFS_CCK_8822B)) +#define BIT_GET_SPEC_SIFS_CCK_8822B(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822B) & BIT_MASK_SPEC_SIFS_CCK_8822B) +#define BIT_SET_SPEC_SIFS_CCK_8822B(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_8822B(x) | BIT_SPEC_SIFS_CCK_8822B(v)) /* 2 REG_USTIME_EDCA_8822B (US TIME TUNING FOR EDCA REGISTER) */ #define BIT_SHIFT_USTIME_EDCA_V1_8822B 0 #define BIT_MASK_USTIME_EDCA_V1_8822B 0x1ff -#define BIT_USTIME_EDCA_V1_8822B(x) (((x) & BIT_MASK_USTIME_EDCA_V1_8822B) << BIT_SHIFT_USTIME_EDCA_V1_8822B) -#define BIT_GET_USTIME_EDCA_V1_8822B(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8822B) & BIT_MASK_USTIME_EDCA_V1_8822B) - - +#define BIT_USTIME_EDCA_V1_8822B(x) \ + (((x) & BIT_MASK_USTIME_EDCA_V1_8822B) \ + << BIT_SHIFT_USTIME_EDCA_V1_8822B) +#define BITS_USTIME_EDCA_V1_8822B \ + (BIT_MASK_USTIME_EDCA_V1_8822B << BIT_SHIFT_USTIME_EDCA_V1_8822B) +#define BIT_CLEAR_USTIME_EDCA_V1_8822B(x) ((x) & (~BITS_USTIME_EDCA_V1_8822B)) +#define BIT_GET_USTIME_EDCA_V1_8822B(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8822B) & \ + BIT_MASK_USTIME_EDCA_V1_8822B) +#define BIT_SET_USTIME_EDCA_V1_8822B(x, v) \ + (BIT_CLEAR_USTIME_EDCA_V1_8822B(x) | BIT_USTIME_EDCA_V1_8822B(v)) /* 2 REG_RESP_SIFS_OFDM_8822B (RESPONSE SIFS FOR OFDM REGISTER) */ #define BIT_SHIFT_SIFS_R2T_OFDM_8822B 8 #define BIT_MASK_SIFS_R2T_OFDM_8822B 0xff -#define BIT_SIFS_R2T_OFDM_8822B(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8822B) << BIT_SHIFT_SIFS_R2T_OFDM_8822B) -#define BIT_GET_SIFS_R2T_OFDM_8822B(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822B) & BIT_MASK_SIFS_R2T_OFDM_8822B) - - +#define BIT_SIFS_R2T_OFDM_8822B(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM_8822B) << BIT_SHIFT_SIFS_R2T_OFDM_8822B) +#define BITS_SIFS_R2T_OFDM_8822B \ + (BIT_MASK_SIFS_R2T_OFDM_8822B << BIT_SHIFT_SIFS_R2T_OFDM_8822B) +#define BIT_CLEAR_SIFS_R2T_OFDM_8822B(x) ((x) & (~BITS_SIFS_R2T_OFDM_8822B)) +#define BIT_GET_SIFS_R2T_OFDM_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822B) & BIT_MASK_SIFS_R2T_OFDM_8822B) +#define BIT_SET_SIFS_R2T_OFDM_8822B(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM_8822B(x) | BIT_SIFS_R2T_OFDM_8822B(v)) #define BIT_SHIFT_SIFS_T2T_OFDM_8822B 0 #define BIT_MASK_SIFS_T2T_OFDM_8822B 0xff -#define BIT_SIFS_T2T_OFDM_8822B(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8822B) << BIT_SHIFT_SIFS_T2T_OFDM_8822B) -#define BIT_GET_SIFS_T2T_OFDM_8822B(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822B) & BIT_MASK_SIFS_T2T_OFDM_8822B) - - +#define BIT_SIFS_T2T_OFDM_8822B(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM_8822B) << BIT_SHIFT_SIFS_T2T_OFDM_8822B) +#define BITS_SIFS_T2T_OFDM_8822B \ + (BIT_MASK_SIFS_T2T_OFDM_8822B << BIT_SHIFT_SIFS_T2T_OFDM_8822B) +#define BIT_CLEAR_SIFS_T2T_OFDM_8822B(x) ((x) & (~BITS_SIFS_T2T_OFDM_8822B)) +#define BIT_GET_SIFS_T2T_OFDM_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822B) & BIT_MASK_SIFS_T2T_OFDM_8822B) +#define BIT_SET_SIFS_T2T_OFDM_8822B(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM_8822B(x) | BIT_SIFS_T2T_OFDM_8822B(v)) /* 2 REG_RESP_SIFS_CCK_8822B (RESPONSE SIFS FOR CCK REGISTER) */ #define BIT_SHIFT_SIFS_R2T_CCK_8822B 8 #define BIT_MASK_SIFS_R2T_CCK_8822B 0xff -#define BIT_SIFS_R2T_CCK_8822B(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8822B) << BIT_SHIFT_SIFS_R2T_CCK_8822B) -#define BIT_GET_SIFS_R2T_CCK_8822B(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822B) & BIT_MASK_SIFS_R2T_CCK_8822B) - - +#define BIT_SIFS_R2T_CCK_8822B(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK_8822B) << BIT_SHIFT_SIFS_R2T_CCK_8822B) +#define BITS_SIFS_R2T_CCK_8822B \ + (BIT_MASK_SIFS_R2T_CCK_8822B << BIT_SHIFT_SIFS_R2T_CCK_8822B) +#define BIT_CLEAR_SIFS_R2T_CCK_8822B(x) ((x) & (~BITS_SIFS_R2T_CCK_8822B)) +#define BIT_GET_SIFS_R2T_CCK_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822B) & BIT_MASK_SIFS_R2T_CCK_8822B) +#define BIT_SET_SIFS_R2T_CCK_8822B(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK_8822B(x) | BIT_SIFS_R2T_CCK_8822B(v)) #define BIT_SHIFT_SIFS_T2T_CCK_8822B 0 #define BIT_MASK_SIFS_T2T_CCK_8822B 0xff -#define BIT_SIFS_T2T_CCK_8822B(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8822B) << BIT_SHIFT_SIFS_T2T_CCK_8822B) -#define BIT_GET_SIFS_T2T_CCK_8822B(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822B) & BIT_MASK_SIFS_T2T_CCK_8822B) - - +#define BIT_SIFS_T2T_CCK_8822B(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK_8822B) << BIT_SHIFT_SIFS_T2T_CCK_8822B) +#define BITS_SIFS_T2T_CCK_8822B \ + (BIT_MASK_SIFS_T2T_CCK_8822B << BIT_SHIFT_SIFS_T2T_CCK_8822B) +#define BIT_CLEAR_SIFS_T2T_CCK_8822B(x) ((x) & (~BITS_SIFS_T2T_CCK_8822B)) +#define BIT_GET_SIFS_T2T_CCK_8822B(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822B) & BIT_MASK_SIFS_T2T_CCK_8822B) +#define BIT_SET_SIFS_T2T_CCK_8822B(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK_8822B(x) | BIT_SIFS_T2T_CCK_8822B(v)) /* 2 REG_EIFS_8822B (EIFS REGISTER) */ #define BIT_SHIFT_EIFS_8822B 0 #define BIT_MASK_EIFS_8822B 0xffff #define BIT_EIFS_8822B(x) (((x) & BIT_MASK_EIFS_8822B) << BIT_SHIFT_EIFS_8822B) -#define BIT_GET_EIFS_8822B(x) (((x) >> BIT_SHIFT_EIFS_8822B) & BIT_MASK_EIFS_8822B) - - +#define BITS_EIFS_8822B (BIT_MASK_EIFS_8822B << BIT_SHIFT_EIFS_8822B) +#define BIT_CLEAR_EIFS_8822B(x) ((x) & (~BITS_EIFS_8822B)) +#define BIT_GET_EIFS_8822B(x) \ + (((x) >> BIT_SHIFT_EIFS_8822B) & BIT_MASK_EIFS_8822B) +#define BIT_SET_EIFS_8822B(x, v) (BIT_CLEAR_EIFS_8822B(x) | BIT_EIFS_8822B(v)) /* 2 REG_CTS2TO_8822B (CTS2 TIMEOUT REGISTER) */ #define BIT_SHIFT_CTS2TO_8822B 0 #define BIT_MASK_CTS2TO_8822B 0xff -#define BIT_CTS2TO_8822B(x) (((x) & BIT_MASK_CTS2TO_8822B) << BIT_SHIFT_CTS2TO_8822B) -#define BIT_GET_CTS2TO_8822B(x) (((x) >> BIT_SHIFT_CTS2TO_8822B) & BIT_MASK_CTS2TO_8822B) - - +#define BIT_CTS2TO_8822B(x) \ + (((x) & BIT_MASK_CTS2TO_8822B) << BIT_SHIFT_CTS2TO_8822B) +#define BITS_CTS2TO_8822B (BIT_MASK_CTS2TO_8822B << BIT_SHIFT_CTS2TO_8822B) +#define BIT_CLEAR_CTS2TO_8822B(x) ((x) & (~BITS_CTS2TO_8822B)) +#define BIT_GET_CTS2TO_8822B(x) \ + (((x) >> BIT_SHIFT_CTS2TO_8822B) & BIT_MASK_CTS2TO_8822B) +#define BIT_SET_CTS2TO_8822B(x, v) \ + (BIT_CLEAR_CTS2TO_8822B(x) | BIT_CTS2TO_8822B(v)) /* 2 REG_ACKTO_8822B (ACK TIMEOUT REGISTER) */ #define BIT_SHIFT_ACKTO_8822B 0 #define BIT_MASK_ACKTO_8822B 0xff -#define BIT_ACKTO_8822B(x) (((x) & BIT_MASK_ACKTO_8822B) << BIT_SHIFT_ACKTO_8822B) -#define BIT_GET_ACKTO_8822B(x) (((x) >> BIT_SHIFT_ACKTO_8822B) & BIT_MASK_ACKTO_8822B) - - +#define BIT_ACKTO_8822B(x) \ + (((x) & BIT_MASK_ACKTO_8822B) << BIT_SHIFT_ACKTO_8822B) +#define BITS_ACKTO_8822B (BIT_MASK_ACKTO_8822B << BIT_SHIFT_ACKTO_8822B) +#define BIT_CLEAR_ACKTO_8822B(x) ((x) & (~BITS_ACKTO_8822B)) +#define BIT_GET_ACKTO_8822B(x) \ + (((x) >> BIT_SHIFT_ACKTO_8822B) & BIT_MASK_ACKTO_8822B) +#define BIT_SET_ACKTO_8822B(x, v) \ + (BIT_CLEAR_ACKTO_8822B(x) | BIT_ACKTO_8822B(v)) /* 2 REG_NAV_CTRL_8822B (NAV CONTROL REGISTER) */ #define BIT_SHIFT_NAV_UPPER_8822B 16 #define BIT_MASK_NAV_UPPER_8822B 0xff -#define BIT_NAV_UPPER_8822B(x) (((x) & BIT_MASK_NAV_UPPER_8822B) << BIT_SHIFT_NAV_UPPER_8822B) -#define BIT_GET_NAV_UPPER_8822B(x) (((x) >> BIT_SHIFT_NAV_UPPER_8822B) & BIT_MASK_NAV_UPPER_8822B) - - +#define BIT_NAV_UPPER_8822B(x) \ + (((x) & BIT_MASK_NAV_UPPER_8822B) << BIT_SHIFT_NAV_UPPER_8822B) +#define BITS_NAV_UPPER_8822B \ + (BIT_MASK_NAV_UPPER_8822B << BIT_SHIFT_NAV_UPPER_8822B) +#define BIT_CLEAR_NAV_UPPER_8822B(x) ((x) & (~BITS_NAV_UPPER_8822B)) +#define BIT_GET_NAV_UPPER_8822B(x) \ + (((x) >> BIT_SHIFT_NAV_UPPER_8822B) & BIT_MASK_NAV_UPPER_8822B) +#define BIT_SET_NAV_UPPER_8822B(x, v) \ + (BIT_CLEAR_NAV_UPPER_8822B(x) | BIT_NAV_UPPER_8822B(v)) #define BIT_SHIFT_RXMYRTS_NAV_8822B 8 #define BIT_MASK_RXMYRTS_NAV_8822B 0xf -#define BIT_RXMYRTS_NAV_8822B(x) (((x) & BIT_MASK_RXMYRTS_NAV_8822B) << BIT_SHIFT_RXMYRTS_NAV_8822B) -#define BIT_GET_RXMYRTS_NAV_8822B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8822B) & BIT_MASK_RXMYRTS_NAV_8822B) - - +#define BIT_RXMYRTS_NAV_8822B(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_8822B) << BIT_SHIFT_RXMYRTS_NAV_8822B) +#define BITS_RXMYRTS_NAV_8822B \ + (BIT_MASK_RXMYRTS_NAV_8822B << BIT_SHIFT_RXMYRTS_NAV_8822B) +#define BIT_CLEAR_RXMYRTS_NAV_8822B(x) ((x) & (~BITS_RXMYRTS_NAV_8822B)) +#define BIT_GET_RXMYRTS_NAV_8822B(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_8822B) & BIT_MASK_RXMYRTS_NAV_8822B) +#define BIT_SET_RXMYRTS_NAV_8822B(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_8822B(x) | BIT_RXMYRTS_NAV_8822B(v)) #define BIT_SHIFT_RTSRST_8822B 0 #define BIT_MASK_RTSRST_8822B 0xff -#define BIT_RTSRST_8822B(x) (((x) & BIT_MASK_RTSRST_8822B) << BIT_SHIFT_RTSRST_8822B) -#define BIT_GET_RTSRST_8822B(x) (((x) >> BIT_SHIFT_RTSRST_8822B) & BIT_MASK_RTSRST_8822B) - - +#define BIT_RTSRST_8822B(x) \ + (((x) & BIT_MASK_RTSRST_8822B) << BIT_SHIFT_RTSRST_8822B) +#define BITS_RTSRST_8822B (BIT_MASK_RTSRST_8822B << BIT_SHIFT_RTSRST_8822B) +#define BIT_CLEAR_RTSRST_8822B(x) ((x) & (~BITS_RTSRST_8822B)) +#define BIT_GET_RTSRST_8822B(x) \ + (((x) >> BIT_SHIFT_RTSRST_8822B) & BIT_MASK_RTSRST_8822B) +#define BIT_SET_RTSRST_8822B(x, v) \ + (BIT_CLEAR_RTSRST_8822B(x) | BIT_RTSRST_8822B(v)) /* 2 REG_BACAMCMD_8822B (BLOCK ACK CAM COMMAND REGISTER) */ #define BIT_BACAM_POLL_8822B BIT(31) @@ -8592,33 +13693,52 @@ #define BIT_SHIFT_TXSBM_8822B 14 #define BIT_MASK_TXSBM_8822B 0x3 -#define BIT_TXSBM_8822B(x) (((x) & BIT_MASK_TXSBM_8822B) << BIT_SHIFT_TXSBM_8822B) -#define BIT_GET_TXSBM_8822B(x) (((x) >> BIT_SHIFT_TXSBM_8822B) & BIT_MASK_TXSBM_8822B) - - +#define BIT_TXSBM_8822B(x) \ + (((x) & BIT_MASK_TXSBM_8822B) << BIT_SHIFT_TXSBM_8822B) +#define BITS_TXSBM_8822B (BIT_MASK_TXSBM_8822B << BIT_SHIFT_TXSBM_8822B) +#define BIT_CLEAR_TXSBM_8822B(x) ((x) & (~BITS_TXSBM_8822B)) +#define BIT_GET_TXSBM_8822B(x) \ + (((x) >> BIT_SHIFT_TXSBM_8822B) & BIT_MASK_TXSBM_8822B) +#define BIT_SET_TXSBM_8822B(x, v) \ + (BIT_CLEAR_TXSBM_8822B(x) | BIT_TXSBM_8822B(v)) #define BIT_SHIFT_BACAM_ADDR_8822B 0 #define BIT_MASK_BACAM_ADDR_8822B 0x3f -#define BIT_BACAM_ADDR_8822B(x) (((x) & BIT_MASK_BACAM_ADDR_8822B) << BIT_SHIFT_BACAM_ADDR_8822B) -#define BIT_GET_BACAM_ADDR_8822B(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8822B) & BIT_MASK_BACAM_ADDR_8822B) - - +#define BIT_BACAM_ADDR_8822B(x) \ + (((x) & BIT_MASK_BACAM_ADDR_8822B) << BIT_SHIFT_BACAM_ADDR_8822B) +#define BITS_BACAM_ADDR_8822B \ + (BIT_MASK_BACAM_ADDR_8822B << BIT_SHIFT_BACAM_ADDR_8822B) +#define BIT_CLEAR_BACAM_ADDR_8822B(x) ((x) & (~BITS_BACAM_ADDR_8822B)) +#define BIT_GET_BACAM_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR_8822B) & BIT_MASK_BACAM_ADDR_8822B) +#define BIT_SET_BACAM_ADDR_8822B(x, v) \ + (BIT_CLEAR_BACAM_ADDR_8822B(x) | BIT_BACAM_ADDR_8822B(v)) /* 2 REG_BACAMCONTENT_8822B (BLOCK ACK CAM CONTENT REGISTER) */ #define BIT_SHIFT_BA_CONTENT_H_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_BA_CONTENT_H_8822B 0xffffffffL -#define BIT_BA_CONTENT_H_8822B(x) (((x) & BIT_MASK_BA_CONTENT_H_8822B) << BIT_SHIFT_BA_CONTENT_H_8822B) -#define BIT_GET_BA_CONTENT_H_8822B(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8822B) & BIT_MASK_BA_CONTENT_H_8822B) - - +#define BIT_BA_CONTENT_H_8822B(x) \ + (((x) & BIT_MASK_BA_CONTENT_H_8822B) << BIT_SHIFT_BA_CONTENT_H_8822B) +#define BITS_BA_CONTENT_H_8822B \ + (BIT_MASK_BA_CONTENT_H_8822B << BIT_SHIFT_BA_CONTENT_H_8822B) +#define BIT_CLEAR_BA_CONTENT_H_8822B(x) ((x) & (~BITS_BA_CONTENT_H_8822B)) +#define BIT_GET_BA_CONTENT_H_8822B(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_H_8822B) & BIT_MASK_BA_CONTENT_H_8822B) +#define BIT_SET_BA_CONTENT_H_8822B(x, v) \ + (BIT_CLEAR_BA_CONTENT_H_8822B(x) | BIT_BA_CONTENT_H_8822B(v)) #define BIT_SHIFT_BA_CONTENT_L_8822B 0 #define BIT_MASK_BA_CONTENT_L_8822B 0xffffffffL -#define BIT_BA_CONTENT_L_8822B(x) (((x) & BIT_MASK_BA_CONTENT_L_8822B) << BIT_SHIFT_BA_CONTENT_L_8822B) -#define BIT_GET_BA_CONTENT_L_8822B(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8822B) & BIT_MASK_BA_CONTENT_L_8822B) - - +#define BIT_BA_CONTENT_L_8822B(x) \ + (((x) & BIT_MASK_BA_CONTENT_L_8822B) << BIT_SHIFT_BA_CONTENT_L_8822B) +#define BITS_BA_CONTENT_L_8822B \ + (BIT_MASK_BA_CONTENT_L_8822B << BIT_SHIFT_BA_CONTENT_L_8822B) +#define BIT_CLEAR_BA_CONTENT_L_8822B(x) ((x) & (~BITS_BA_CONTENT_L_8822B)) +#define BIT_GET_BA_CONTENT_L_8822B(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L_8822B) & BIT_MASK_BA_CONTENT_L_8822B) +#define BIT_SET_BA_CONTENT_L_8822B(x, v) \ + (BIT_CLEAR_BA_CONTENT_L_8822B(x) | BIT_BA_CONTENT_L_8822B(v)) /* 2 REG_WMAC_BITMAP_CTL_8822B */ #define BIT_BITMAP_VO_8822B BIT(7) @@ -8628,9 +13748,18 @@ #define BIT_SHIFT_BITMAP_CONDITION_8822B 2 #define BIT_MASK_BITMAP_CONDITION_8822B 0x3 -#define BIT_BITMAP_CONDITION_8822B(x) (((x) & BIT_MASK_BITMAP_CONDITION_8822B) << BIT_SHIFT_BITMAP_CONDITION_8822B) -#define BIT_GET_BITMAP_CONDITION_8822B(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8822B) & BIT_MASK_BITMAP_CONDITION_8822B) - +#define BIT_BITMAP_CONDITION_8822B(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION_8822B) \ + << BIT_SHIFT_BITMAP_CONDITION_8822B) +#define BITS_BITMAP_CONDITION_8822B \ + (BIT_MASK_BITMAP_CONDITION_8822B << BIT_SHIFT_BITMAP_CONDITION_8822B) +#define BIT_CLEAR_BITMAP_CONDITION_8822B(x) \ + ((x) & (~BITS_BITMAP_CONDITION_8822B)) +#define BIT_GET_BITMAP_CONDITION_8822B(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION_8822B) & \ + BIT_MASK_BITMAP_CONDITION_8822B) +#define BIT_SET_BITMAP_CONDITION_8822B(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION_8822B(x) | BIT_BITMAP_CONDITION_8822B(v)) #define BIT_BITMAP_SSNBK_COUNTER_CLR_8822B BIT(1) #define BIT_BITMAP_FORCE_8822B BIT(0) @@ -8639,9 +13768,15 @@ #define BIT_SHIFT_RXPKT_TYPE_8822B 2 #define BIT_MASK_RXPKT_TYPE_8822B 0x3f -#define BIT_RXPKT_TYPE_8822B(x) (((x) & BIT_MASK_RXPKT_TYPE_8822B) << BIT_SHIFT_RXPKT_TYPE_8822B) -#define BIT_GET_RXPKT_TYPE_8822B(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8822B) & BIT_MASK_RXPKT_TYPE_8822B) - +#define BIT_RXPKT_TYPE_8822B(x) \ + (((x) & BIT_MASK_RXPKT_TYPE_8822B) << BIT_SHIFT_RXPKT_TYPE_8822B) +#define BITS_RXPKT_TYPE_8822B \ + (BIT_MASK_RXPKT_TYPE_8822B << BIT_SHIFT_RXPKT_TYPE_8822B) +#define BIT_CLEAR_RXPKT_TYPE_8822B(x) ((x) & (~BITS_RXPKT_TYPE_8822B)) +#define BIT_GET_RXPKT_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE_8822B) & BIT_MASK_RXPKT_TYPE_8822B) +#define BIT_SET_RXPKT_TYPE_8822B(x, v) \ + (BIT_CLEAR_RXPKT_TYPE_8822B(x) | BIT_RXPKT_TYPE_8822B(v)) #define BIT_TXACT_IND_8822B BIT(1) #define BIT_RXACT_IND_8822B BIT(0) @@ -8650,9 +13785,20 @@ #define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B 2 #define BIT_MASK_BITMAP_SSNBK_COUNTER_8822B 0x3f -#define BIT_BITMAP_SSNBK_COUNTER_8822B(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) -#define BIT_GET_BITMAP_SSNBK_COUNTER_8822B(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) - +#define BIT_BITMAP_SSNBK_COUNTER_8822B(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) +#define BITS_BITMAP_SSNBK_COUNTER_8822B \ + (BIT_MASK_BITMAP_SSNBK_COUNTER_8822B \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822B(x) \ + ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8822B)) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) +#define BIT_SET_BITMAP_SSNBK_COUNTER_8822B(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822B(x) | \ + BIT_BITMAP_SSNBK_COUNTER_8822B(v)) #define BIT_BITMAP_EN_8822B BIT(1) #define BIT_WMAC_BACAM_RPMEN_8822B BIT(0) @@ -8661,18 +13807,33 @@ #define BIT_SHIFT_LBDLY_8822B 0 #define BIT_MASK_LBDLY_8822B 0x1f -#define BIT_LBDLY_8822B(x) (((x) & BIT_MASK_LBDLY_8822B) << BIT_SHIFT_LBDLY_8822B) -#define BIT_GET_LBDLY_8822B(x) (((x) >> BIT_SHIFT_LBDLY_8822B) & BIT_MASK_LBDLY_8822B) - - +#define BIT_LBDLY_8822B(x) \ + (((x) & BIT_MASK_LBDLY_8822B) << BIT_SHIFT_LBDLY_8822B) +#define BITS_LBDLY_8822B (BIT_MASK_LBDLY_8822B << BIT_SHIFT_LBDLY_8822B) +#define BIT_CLEAR_LBDLY_8822B(x) ((x) & (~BITS_LBDLY_8822B)) +#define BIT_GET_LBDLY_8822B(x) \ + (((x) >> BIT_SHIFT_LBDLY_8822B) & BIT_MASK_LBDLY_8822B) +#define BIT_SET_LBDLY_8822B(x, v) \ + (BIT_CLEAR_LBDLY_8822B(x) | BIT_LBDLY_8822B(v)) /* 2 REG_RXERR_RPT_8822B (RX ERROR REPORT REGISTER) */ #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B 28 #define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B 0xf -#define BIT_RXERR_RPT_SEL_V1_3_0_8822B(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) -#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822B(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) - +#define BIT_RXERR_RPT_SEL_V1_3_0_8822B(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) +#define BITS_RXERR_RPT_SEL_V1_3_0_8822B \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822B(x) \ + ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8822B)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822B(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8822B(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822B(x) | \ + BIT_RXERR_RPT_SEL_V1_3_0_8822B(v)) #define BIT_RXERR_RPT_RST_8822B BIT(27) #define BIT_RXERR_RPT_SEL_V1_4_8822B BIT(26) @@ -8681,53 +13842,92 @@ #define BIT_SHIFT_UD_SUB_TYPE_8822B 18 #define BIT_MASK_UD_SUB_TYPE_8822B 0xf -#define BIT_UD_SUB_TYPE_8822B(x) (((x) & BIT_MASK_UD_SUB_TYPE_8822B) << BIT_SHIFT_UD_SUB_TYPE_8822B) -#define BIT_GET_UD_SUB_TYPE_8822B(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8822B) & BIT_MASK_UD_SUB_TYPE_8822B) - - +#define BIT_UD_SUB_TYPE_8822B(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE_8822B) << BIT_SHIFT_UD_SUB_TYPE_8822B) +#define BITS_UD_SUB_TYPE_8822B \ + (BIT_MASK_UD_SUB_TYPE_8822B << BIT_SHIFT_UD_SUB_TYPE_8822B) +#define BIT_CLEAR_UD_SUB_TYPE_8822B(x) ((x) & (~BITS_UD_SUB_TYPE_8822B)) +#define BIT_GET_UD_SUB_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE_8822B) & BIT_MASK_UD_SUB_TYPE_8822B) +#define BIT_SET_UD_SUB_TYPE_8822B(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE_8822B(x) | BIT_UD_SUB_TYPE_8822B(v)) #define BIT_SHIFT_UD_TYPE_8822B 16 #define BIT_MASK_UD_TYPE_8822B 0x3 -#define BIT_UD_TYPE_8822B(x) (((x) & BIT_MASK_UD_TYPE_8822B) << BIT_SHIFT_UD_TYPE_8822B) -#define BIT_GET_UD_TYPE_8822B(x) (((x) >> BIT_SHIFT_UD_TYPE_8822B) & BIT_MASK_UD_TYPE_8822B) - - +#define BIT_UD_TYPE_8822B(x) \ + (((x) & BIT_MASK_UD_TYPE_8822B) << BIT_SHIFT_UD_TYPE_8822B) +#define BITS_UD_TYPE_8822B (BIT_MASK_UD_TYPE_8822B << BIT_SHIFT_UD_TYPE_8822B) +#define BIT_CLEAR_UD_TYPE_8822B(x) ((x) & (~BITS_UD_TYPE_8822B)) +#define BIT_GET_UD_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_UD_TYPE_8822B) & BIT_MASK_UD_TYPE_8822B) +#define BIT_SET_UD_TYPE_8822B(x, v) \ + (BIT_CLEAR_UD_TYPE_8822B(x) | BIT_UD_TYPE_8822B(v)) #define BIT_SHIFT_RPT_COUNTER_8822B 0 #define BIT_MASK_RPT_COUNTER_8822B 0xffff -#define BIT_RPT_COUNTER_8822B(x) (((x) & BIT_MASK_RPT_COUNTER_8822B) << BIT_SHIFT_RPT_COUNTER_8822B) -#define BIT_GET_RPT_COUNTER_8822B(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8822B) & BIT_MASK_RPT_COUNTER_8822B) - - +#define BIT_RPT_COUNTER_8822B(x) \ + (((x) & BIT_MASK_RPT_COUNTER_8822B) << BIT_SHIFT_RPT_COUNTER_8822B) +#define BITS_RPT_COUNTER_8822B \ + (BIT_MASK_RPT_COUNTER_8822B << BIT_SHIFT_RPT_COUNTER_8822B) +#define BIT_CLEAR_RPT_COUNTER_8822B(x) ((x) & (~BITS_RPT_COUNTER_8822B)) +#define BIT_GET_RPT_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER_8822B) & BIT_MASK_RPT_COUNTER_8822B) +#define BIT_SET_RPT_COUNTER_8822B(x, v) \ + (BIT_CLEAR_RPT_COUNTER_8822B(x) | BIT_RPT_COUNTER_8822B(v)) /* 2 REG_WMAC_TRXPTCL_CTL_8822B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ #define BIT_SHIFT_ACKBA_TYPSEL_8822B (60 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBA_TYPSEL_8822B 0xf -#define BIT_ACKBA_TYPSEL_8822B(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8822B) << BIT_SHIFT_ACKBA_TYPSEL_8822B) -#define BIT_GET_ACKBA_TYPSEL_8822B(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822B) & BIT_MASK_ACKBA_TYPSEL_8822B) - - +#define BIT_ACKBA_TYPSEL_8822B(x) \ + (((x) & BIT_MASK_ACKBA_TYPSEL_8822B) << BIT_SHIFT_ACKBA_TYPSEL_8822B) +#define BITS_ACKBA_TYPSEL_8822B \ + (BIT_MASK_ACKBA_TYPSEL_8822B << BIT_SHIFT_ACKBA_TYPSEL_8822B) +#define BIT_CLEAR_ACKBA_TYPSEL_8822B(x) ((x) & (~BITS_ACKBA_TYPSEL_8822B)) +#define BIT_GET_ACKBA_TYPSEL_8822B(x) \ + (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822B) & BIT_MASK_ACKBA_TYPSEL_8822B) +#define BIT_SET_ACKBA_TYPSEL_8822B(x, v) \ + (BIT_CLEAR_ACKBA_TYPSEL_8822B(x) | BIT_ACKBA_TYPSEL_8822B(v)) #define BIT_SHIFT_ACKBA_ACKPCHK_8822B (56 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBA_ACKPCHK_8822B 0xf -#define BIT_ACKBA_ACKPCHK_8822B(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8822B) << BIT_SHIFT_ACKBA_ACKPCHK_8822B) -#define BIT_GET_ACKBA_ACKPCHK_8822B(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822B) & BIT_MASK_ACKBA_ACKPCHK_8822B) - - +#define BIT_ACKBA_ACKPCHK_8822B(x) \ + (((x) & BIT_MASK_ACKBA_ACKPCHK_8822B) << BIT_SHIFT_ACKBA_ACKPCHK_8822B) +#define BITS_ACKBA_ACKPCHK_8822B \ + (BIT_MASK_ACKBA_ACKPCHK_8822B << BIT_SHIFT_ACKBA_ACKPCHK_8822B) +#define BIT_CLEAR_ACKBA_ACKPCHK_8822B(x) ((x) & (~BITS_ACKBA_ACKPCHK_8822B)) +#define BIT_GET_ACKBA_ACKPCHK_8822B(x) \ + (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822B) & BIT_MASK_ACKBA_ACKPCHK_8822B) +#define BIT_SET_ACKBA_ACKPCHK_8822B(x, v) \ + (BIT_CLEAR_ACKBA_ACKPCHK_8822B(x) | BIT_ACKBA_ACKPCHK_8822B(v)) #define BIT_SHIFT_ACKBAR_TYPESEL_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_TYPESEL_8822B 0xff -#define BIT_ACKBAR_TYPESEL_8822B(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8822B) << BIT_SHIFT_ACKBAR_TYPESEL_8822B) -#define BIT_GET_ACKBAR_TYPESEL_8822B(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822B) & BIT_MASK_ACKBAR_TYPESEL_8822B) - - +#define BIT_ACKBAR_TYPESEL_8822B(x) \ + (((x) & BIT_MASK_ACKBAR_TYPESEL_8822B) \ + << BIT_SHIFT_ACKBAR_TYPESEL_8822B) +#define BITS_ACKBAR_TYPESEL_8822B \ + (BIT_MASK_ACKBAR_TYPESEL_8822B << BIT_SHIFT_ACKBAR_TYPESEL_8822B) +#define BIT_CLEAR_ACKBAR_TYPESEL_8822B(x) ((x) & (~BITS_ACKBAR_TYPESEL_8822B)) +#define BIT_GET_ACKBAR_TYPESEL_8822B(x) \ + (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822B) & \ + BIT_MASK_ACKBAR_TYPESEL_8822B) +#define BIT_SET_ACKBAR_TYPESEL_8822B(x, v) \ + (BIT_CLEAR_ACKBAR_TYPESEL_8822B(x) | BIT_ACKBAR_TYPESEL_8822B(v)) #define BIT_SHIFT_ACKBAR_ACKPCHK_8822B (44 & CPU_OPT_WIDTH) #define BIT_MASK_ACKBAR_ACKPCHK_8822B 0xf -#define BIT_ACKBAR_ACKPCHK_8822B(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8822B) << BIT_SHIFT_ACKBAR_ACKPCHK_8822B) -#define BIT_GET_ACKBAR_ACKPCHK_8822B(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822B) & BIT_MASK_ACKBAR_ACKPCHK_8822B) - +#define BIT_ACKBAR_ACKPCHK_8822B(x) \ + (((x) & BIT_MASK_ACKBAR_ACKPCHK_8822B) \ + << BIT_SHIFT_ACKBAR_ACKPCHK_8822B) +#define BITS_ACKBAR_ACKPCHK_8822B \ + (BIT_MASK_ACKBAR_ACKPCHK_8822B << BIT_SHIFT_ACKBAR_ACKPCHK_8822B) +#define BIT_CLEAR_ACKBAR_ACKPCHK_8822B(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8822B)) +#define BIT_GET_ACKBAR_ACKPCHK_8822B(x) \ + (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822B) & \ + BIT_MASK_ACKBAR_ACKPCHK_8822B) +#define BIT_SET_ACKBAR_ACKPCHK_8822B(x, v) \ + (BIT_CLEAR_ACKBAR_ACKPCHK_8822B(x) | BIT_ACKBAR_ACKPCHK_8822B(v)) #define BIT_RXBA_IGNOREA2_8822B BIT(42) #define BIT_EN_SAVE_ALL_TXOPADDR_8822B BIT(41) @@ -8751,9 +13951,15 @@ #define BIT_SHIFT_RESP_CHNBUSY_8822B 20 #define BIT_MASK_RESP_CHNBUSY_8822B 0x3 -#define BIT_RESP_CHNBUSY_8822B(x) (((x) & BIT_MASK_RESP_CHNBUSY_8822B) << BIT_SHIFT_RESP_CHNBUSY_8822B) -#define BIT_GET_RESP_CHNBUSY_8822B(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8822B) & BIT_MASK_RESP_CHNBUSY_8822B) - +#define BIT_RESP_CHNBUSY_8822B(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY_8822B) << BIT_SHIFT_RESP_CHNBUSY_8822B) +#define BITS_RESP_CHNBUSY_8822B \ + (BIT_MASK_RESP_CHNBUSY_8822B << BIT_SHIFT_RESP_CHNBUSY_8822B) +#define BIT_CLEAR_RESP_CHNBUSY_8822B(x) ((x) & (~BITS_RESP_CHNBUSY_8822B)) +#define BIT_GET_RESP_CHNBUSY_8822B(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY_8822B) & BIT_MASK_RESP_CHNBUSY_8822B) +#define BIT_SET_RESP_CHNBUSY_8822B(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY_8822B(x) | BIT_RESP_CHNBUSY_8822B(v)) #define BIT_RESP_DCTS_EN_8822B BIT(19) #define BIT_RESP_DCFE_EN_8822B BIT(18) @@ -8765,33 +13971,63 @@ #define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B 10 #define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B 0x7 -#define BIT_R_WMAC_SECOND_CCA_TIMER_8822B(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) -#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) - - +#define BIT_R_WMAC_SECOND_CCA_TIMER_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) +#define BITS_R_WMAC_SECOND_CCA_TIMER_8822B \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822B(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8822B)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822B(x) | \ + BIT_R_WMAC_SECOND_CCA_TIMER_8822B(v)) #define BIT_SHIFT_RFMOD_8822B 7 #define BIT_MASK_RFMOD_8822B 0x3 -#define BIT_RFMOD_8822B(x) (((x) & BIT_MASK_RFMOD_8822B) << BIT_SHIFT_RFMOD_8822B) -#define BIT_GET_RFMOD_8822B(x) (((x) >> BIT_SHIFT_RFMOD_8822B) & BIT_MASK_RFMOD_8822B) - - +#define BIT_RFMOD_8822B(x) \ + (((x) & BIT_MASK_RFMOD_8822B) << BIT_SHIFT_RFMOD_8822B) +#define BITS_RFMOD_8822B (BIT_MASK_RFMOD_8822B << BIT_SHIFT_RFMOD_8822B) +#define BIT_CLEAR_RFMOD_8822B(x) ((x) & (~BITS_RFMOD_8822B)) +#define BIT_GET_RFMOD_8822B(x) \ + (((x) >> BIT_SHIFT_RFMOD_8822B) & BIT_MASK_RFMOD_8822B) +#define BIT_SET_RFMOD_8822B(x, v) \ + (BIT_CLEAR_RFMOD_8822B(x) | BIT_RFMOD_8822B(v)) #define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B 5 #define BIT_MASK_RESP_CTS_DYNBW_SEL_8822B 0x3 -#define BIT_RESP_CTS_DYNBW_SEL_8822B(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) -#define BIT_GET_RESP_CTS_DYNBW_SEL_8822B(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) - +#define BIT_RESP_CTS_DYNBW_SEL_8822B(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) +#define BITS_RESP_CTS_DYNBW_SEL_8822B \ + (BIT_MASK_RESP_CTS_DYNBW_SEL_8822B \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822B(x) \ + ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8822B)) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) & \ + BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) +#define BIT_SET_RESP_CTS_DYNBW_SEL_8822B(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822B(x) | \ + BIT_RESP_CTS_DYNBW_SEL_8822B(v)) #define BIT_DLY_TX_WAIT_RXANTSEL_8822B BIT(4) #define BIT_TXRESP_BY_RXANTSEL_8822B BIT(3) #define BIT_SHIFT_ORIG_DCTS_CHK_8822B 0 #define BIT_MASK_ORIG_DCTS_CHK_8822B 0x3 -#define BIT_ORIG_DCTS_CHK_8822B(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8822B) << BIT_SHIFT_ORIG_DCTS_CHK_8822B) -#define BIT_GET_ORIG_DCTS_CHK_8822B(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822B) & BIT_MASK_ORIG_DCTS_CHK_8822B) - - +#define BIT_ORIG_DCTS_CHK_8822B(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK_8822B) << BIT_SHIFT_ORIG_DCTS_CHK_8822B) +#define BITS_ORIG_DCTS_CHK_8822B \ + (BIT_MASK_ORIG_DCTS_CHK_8822B << BIT_SHIFT_ORIG_DCTS_CHK_8822B) +#define BIT_CLEAR_ORIG_DCTS_CHK_8822B(x) ((x) & (~BITS_ORIG_DCTS_CHK_8822B)) +#define BIT_GET_ORIG_DCTS_CHK_8822B(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822B) & BIT_MASK_ORIG_DCTS_CHK_8822B) +#define BIT_SET_ORIG_DCTS_CHK_8822B(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK_8822B(x) | BIT_ORIG_DCTS_CHK_8822B(v)) /* 2 REG_CAMCMD_8822B (CAM COMMAND REGISTER) */ #define BIT_SECCAM_POLLING_8822B BIT(31) @@ -8801,28 +14037,45 @@ #define BIT_SHIFT_SECCAM_ADDR_V2_8822B 0 #define BIT_MASK_SECCAM_ADDR_V2_8822B 0x3ff -#define BIT_SECCAM_ADDR_V2_8822B(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8822B) << BIT_SHIFT_SECCAM_ADDR_V2_8822B) -#define BIT_GET_SECCAM_ADDR_V2_8822B(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822B) & BIT_MASK_SECCAM_ADDR_V2_8822B) - - +#define BIT_SECCAM_ADDR_V2_8822B(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2_8822B) \ + << BIT_SHIFT_SECCAM_ADDR_V2_8822B) +#define BITS_SECCAM_ADDR_V2_8822B \ + (BIT_MASK_SECCAM_ADDR_V2_8822B << BIT_SHIFT_SECCAM_ADDR_V2_8822B) +#define BIT_CLEAR_SECCAM_ADDR_V2_8822B(x) ((x) & (~BITS_SECCAM_ADDR_V2_8822B)) +#define BIT_GET_SECCAM_ADDR_V2_8822B(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822B) & \ + BIT_MASK_SECCAM_ADDR_V2_8822B) +#define BIT_SET_SECCAM_ADDR_V2_8822B(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2_8822B(x) | BIT_SECCAM_ADDR_V2_8822B(v)) /* 2 REG_CAMWRITE_8822B (CAM WRITE REGISTER) */ #define BIT_SHIFT_CAMW_DATA_8822B 0 #define BIT_MASK_CAMW_DATA_8822B 0xffffffffL -#define BIT_CAMW_DATA_8822B(x) (((x) & BIT_MASK_CAMW_DATA_8822B) << BIT_SHIFT_CAMW_DATA_8822B) -#define BIT_GET_CAMW_DATA_8822B(x) (((x) >> BIT_SHIFT_CAMW_DATA_8822B) & BIT_MASK_CAMW_DATA_8822B) - - +#define BIT_CAMW_DATA_8822B(x) \ + (((x) & BIT_MASK_CAMW_DATA_8822B) << BIT_SHIFT_CAMW_DATA_8822B) +#define BITS_CAMW_DATA_8822B \ + (BIT_MASK_CAMW_DATA_8822B << BIT_SHIFT_CAMW_DATA_8822B) +#define BIT_CLEAR_CAMW_DATA_8822B(x) ((x) & (~BITS_CAMW_DATA_8822B)) +#define BIT_GET_CAMW_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_CAMW_DATA_8822B) & BIT_MASK_CAMW_DATA_8822B) +#define BIT_SET_CAMW_DATA_8822B(x, v) \ + (BIT_CLEAR_CAMW_DATA_8822B(x) | BIT_CAMW_DATA_8822B(v)) /* 2 REG_CAMREAD_8822B (CAM READ REGISTER) */ #define BIT_SHIFT_CAMR_DATA_8822B 0 #define BIT_MASK_CAMR_DATA_8822B 0xffffffffL -#define BIT_CAMR_DATA_8822B(x) (((x) & BIT_MASK_CAMR_DATA_8822B) << BIT_SHIFT_CAMR_DATA_8822B) -#define BIT_GET_CAMR_DATA_8822B(x) (((x) >> BIT_SHIFT_CAMR_DATA_8822B) & BIT_MASK_CAMR_DATA_8822B) - - +#define BIT_CAMR_DATA_8822B(x) \ + (((x) & BIT_MASK_CAMR_DATA_8822B) << BIT_SHIFT_CAMR_DATA_8822B) +#define BITS_CAMR_DATA_8822B \ + (BIT_MASK_CAMR_DATA_8822B << BIT_SHIFT_CAMR_DATA_8822B) +#define BIT_CLEAR_CAMR_DATA_8822B(x) ((x) & (~BITS_CAMR_DATA_8822B)) +#define BIT_GET_CAMR_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_CAMR_DATA_8822B) & BIT_MASK_CAMR_DATA_8822B) +#define BIT_SET_CAMR_DATA_8822B(x, v) \ + (BIT_CLEAR_CAMR_DATA_8822B(x) | BIT_CAMR_DATA_8822B(v)) /* 2 REG_CAMDBG_8822B (CAM DEBUG REGISTER) */ #define BIT_SECCAM_INFO_8822B BIT(31) @@ -8830,43 +14083,89 @@ #define BIT_SHIFT_CAMDBG_SEC_TYPE_8822B 12 #define BIT_MASK_CAMDBG_SEC_TYPE_8822B 0x7 -#define BIT_CAMDBG_SEC_TYPE_8822B(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822B) << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) -#define BIT_GET_CAMDBG_SEC_TYPE_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) & BIT_MASK_CAMDBG_SEC_TYPE_8822B) - +#define BIT_CAMDBG_SEC_TYPE_8822B(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822B) \ + << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) +#define BITS_CAMDBG_SEC_TYPE_8822B \ + (BIT_MASK_CAMDBG_SEC_TYPE_8822B << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) +#define BIT_CLEAR_CAMDBG_SEC_TYPE_8822B(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8822B)) +#define BIT_GET_CAMDBG_SEC_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) & \ + BIT_MASK_CAMDBG_SEC_TYPE_8822B) +#define BIT_SET_CAMDBG_SEC_TYPE_8822B(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_8822B(x) | BIT_CAMDBG_SEC_TYPE_8822B(v)) #define BIT_CAMDBG_EXT_SECTYPE_8822B BIT(11) #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B 5 #define BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B 0x1f -#define BIT_CAMDBG_MIC_KEY_IDX_8822B(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) -#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) - - +#define BIT_CAMDBG_MIC_KEY_IDX_8822B(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) +#define BITS_CAMDBG_MIC_KEY_IDX_8822B \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822B(x) \ + ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8822B)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_8822B(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822B(x) | \ + BIT_CAMDBG_MIC_KEY_IDX_8822B(v)) #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B 0 #define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B 0x1f -#define BIT_CAMDBG_SEC_KEY_IDX_8822B(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) -#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) - - +#define BIT_CAMDBG_SEC_KEY_IDX_8822B(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) +#define BITS_CAMDBG_SEC_KEY_IDX_8822B \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822B(x) \ + ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8822B)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_8822B(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822B(x) | \ + BIT_CAMDBG_SEC_KEY_IDX_8822B(v)) /* 2 REG_RXFILTER_ACTION_1_8822B */ #define BIT_SHIFT_RXFILTER_ACTION_1_8822B 0 #define BIT_MASK_RXFILTER_ACTION_1_8822B 0xff -#define BIT_RXFILTER_ACTION_1_8822B(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8822B) << BIT_SHIFT_RXFILTER_ACTION_1_8822B) -#define BIT_GET_RXFILTER_ACTION_1_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822B) & BIT_MASK_RXFILTER_ACTION_1_8822B) - - +#define BIT_RXFILTER_ACTION_1_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1_8822B) \ + << BIT_SHIFT_RXFILTER_ACTION_1_8822B) +#define BITS_RXFILTER_ACTION_1_8822B \ + (BIT_MASK_RXFILTER_ACTION_1_8822B << BIT_SHIFT_RXFILTER_ACTION_1_8822B) +#define BIT_CLEAR_RXFILTER_ACTION_1_8822B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_1_8822B)) +#define BIT_GET_RXFILTER_ACTION_1_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822B) & \ + BIT_MASK_RXFILTER_ACTION_1_8822B) +#define BIT_SET_RXFILTER_ACTION_1_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1_8822B(x) | BIT_RXFILTER_ACTION_1_8822B(v)) /* 2 REG_RXFILTER_CATEGORY_1_8822B */ #define BIT_SHIFT_RXFILTER_CATEGORY_1_8822B 0 #define BIT_MASK_RXFILTER_CATEGORY_1_8822B 0xff -#define BIT_RXFILTER_CATEGORY_1_8822B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822B) << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) -#define BIT_GET_RXFILTER_CATEGORY_1_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) & BIT_MASK_RXFILTER_CATEGORY_1_8822B) - - +#define BIT_RXFILTER_CATEGORY_1_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) +#define BITS_RXFILTER_CATEGORY_1_8822B \ + (BIT_MASK_RXFILTER_CATEGORY_1_8822B \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) +#define BIT_CLEAR_RXFILTER_CATEGORY_1_8822B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_1_8822B)) +#define BIT_GET_RXFILTER_CATEGORY_1_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) & \ + BIT_MASK_RXFILTER_CATEGORY_1_8822B) +#define BIT_SET_RXFILTER_CATEGORY_1_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1_8822B(x) | \ + BIT_RXFILTER_CATEGORY_1_8822B(v)) /* 2 REG_SECCFG_8822B (SECURITY CONFIGURATION REGISTER) */ #define BIT_DIS_GCLK_WAPI_8822B BIT(15) @@ -8889,37 +14188,73 @@ #define BIT_SHIFT_RXFILTER_ACTION_3_8822B 0 #define BIT_MASK_RXFILTER_ACTION_3_8822B 0xff -#define BIT_RXFILTER_ACTION_3_8822B(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8822B) << BIT_SHIFT_RXFILTER_ACTION_3_8822B) -#define BIT_GET_RXFILTER_ACTION_3_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822B) & BIT_MASK_RXFILTER_ACTION_3_8822B) - - +#define BIT_RXFILTER_ACTION_3_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3_8822B) \ + << BIT_SHIFT_RXFILTER_ACTION_3_8822B) +#define BITS_RXFILTER_ACTION_3_8822B \ + (BIT_MASK_RXFILTER_ACTION_3_8822B << BIT_SHIFT_RXFILTER_ACTION_3_8822B) +#define BIT_CLEAR_RXFILTER_ACTION_3_8822B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_3_8822B)) +#define BIT_GET_RXFILTER_ACTION_3_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822B) & \ + BIT_MASK_RXFILTER_ACTION_3_8822B) +#define BIT_SET_RXFILTER_ACTION_3_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3_8822B(x) | BIT_RXFILTER_ACTION_3_8822B(v)) /* 2 REG_RXFILTER_CATEGORY_3_8822B */ #define BIT_SHIFT_RXFILTER_CATEGORY_3_8822B 0 #define BIT_MASK_RXFILTER_CATEGORY_3_8822B 0xff -#define BIT_RXFILTER_CATEGORY_3_8822B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822B) << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) -#define BIT_GET_RXFILTER_CATEGORY_3_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) & BIT_MASK_RXFILTER_CATEGORY_3_8822B) - - +#define BIT_RXFILTER_CATEGORY_3_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) +#define BITS_RXFILTER_CATEGORY_3_8822B \ + (BIT_MASK_RXFILTER_CATEGORY_3_8822B \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) +#define BIT_CLEAR_RXFILTER_CATEGORY_3_8822B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_3_8822B)) +#define BIT_GET_RXFILTER_CATEGORY_3_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) & \ + BIT_MASK_RXFILTER_CATEGORY_3_8822B) +#define BIT_SET_RXFILTER_CATEGORY_3_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3_8822B(x) | \ + BIT_RXFILTER_CATEGORY_3_8822B(v)) /* 2 REG_RXFILTER_ACTION_2_8822B */ #define BIT_SHIFT_RXFILTER_ACTION_2_8822B 0 #define BIT_MASK_RXFILTER_ACTION_2_8822B 0xff -#define BIT_RXFILTER_ACTION_2_8822B(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8822B) << BIT_SHIFT_RXFILTER_ACTION_2_8822B) -#define BIT_GET_RXFILTER_ACTION_2_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822B) & BIT_MASK_RXFILTER_ACTION_2_8822B) - - +#define BIT_RXFILTER_ACTION_2_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2_8822B) \ + << BIT_SHIFT_RXFILTER_ACTION_2_8822B) +#define BITS_RXFILTER_ACTION_2_8822B \ + (BIT_MASK_RXFILTER_ACTION_2_8822B << BIT_SHIFT_RXFILTER_ACTION_2_8822B) +#define BIT_CLEAR_RXFILTER_ACTION_2_8822B(x) \ + ((x) & (~BITS_RXFILTER_ACTION_2_8822B)) +#define BIT_GET_RXFILTER_ACTION_2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822B) & \ + BIT_MASK_RXFILTER_ACTION_2_8822B) +#define BIT_SET_RXFILTER_ACTION_2_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2_8822B(x) | BIT_RXFILTER_ACTION_2_8822B(v)) /* 2 REG_RXFILTER_CATEGORY_2_8822B */ #define BIT_SHIFT_RXFILTER_CATEGORY_2_8822B 0 #define BIT_MASK_RXFILTER_CATEGORY_2_8822B 0xff -#define BIT_RXFILTER_CATEGORY_2_8822B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822B) << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) -#define BIT_GET_RXFILTER_CATEGORY_2_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) & BIT_MASK_RXFILTER_CATEGORY_2_8822B) - - +#define BIT_RXFILTER_CATEGORY_2_8822B(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822B) \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) +#define BITS_RXFILTER_CATEGORY_2_8822B \ + (BIT_MASK_RXFILTER_CATEGORY_2_8822B \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) +#define BIT_CLEAR_RXFILTER_CATEGORY_2_8822B(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_2_8822B)) +#define BIT_GET_RXFILTER_CATEGORY_2_8822B(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) & \ + BIT_MASK_RXFILTER_CATEGORY_2_8822B) +#define BIT_SET_RXFILTER_CATEGORY_2_8822B(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2_8822B(x) | \ + BIT_RXFILTER_CATEGORY_2_8822B(v)) /* 2 REG_RXFLTMAP4_8822B (RX FILTER MAP GROUP 4) */ #define BIT_CTRLFLT15EN_FW_8822B BIT(15) @@ -8957,7 +14292,7 @@ #define BIT_MGTFLT1EN_FW_8822B BIT(1) #define BIT_MGTFLT0EN_FW_8822B BIT(0) -/* 2 REG_RXFLTMAP6_8822B (RX FILTER MAP GROUP 3) */ +/* 2 REG_RXFLTMAP6_8822B (RX FILTER MAP GROUP 6) */ #define BIT_ACTIONFLT15EN_FW_8822B BIT(15) #define BIT_ACTIONFLT14EN_FW_8822B BIT(14) #define BIT_ACTIONFLT13EN_FW_8822B BIT(13) @@ -8975,7 +14310,7 @@ #define BIT_ACTIONFLT1EN_FW_8822B BIT(1) #define BIT_ACTIONFLT0EN_FW_8822B BIT(0) -/* 2 REG_RXFLTMAP5_8822B (RX FILTER MAP GROUP 3) */ +/* 2 REG_RXFLTMAP5_8822B (RX FILTER MAP GROUP 5) */ #define BIT_DATAFLT15EN_FW_8822B BIT(15) #define BIT_DATAFLT14EN_FW_8822B BIT(14) #define BIT_DATAFLT13EN_FW_8822B BIT(13) @@ -9007,9 +14342,20 @@ #define BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B 5 #define BIT_MASK_PORTSEL__PS_RX_INFO_8822B 0x7 -#define BIT_PORTSEL__PS_RX_INFO_8822B(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) -#define BIT_GET_PORTSEL__PS_RX_INFO_8822B(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B) - +#define BIT_PORTSEL__PS_RX_INFO_8822B(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B) \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) +#define BITS_PORTSEL__PS_RX_INFO_8822B \ + (BIT_MASK_PORTSEL__PS_RX_INFO_8822B \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8822B(x) \ + ((x) & (~BITS_PORTSEL__PS_RX_INFO_8822B)) +#define BIT_GET_PORTSEL__PS_RX_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) & \ + BIT_MASK_PORTSEL__PS_RX_INFO_8822B) +#define BIT_SET_PORTSEL__PS_RX_INFO_8822B(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO_8822B(x) | \ + BIT_PORTSEL__PS_RX_INFO_8822B(v)) #define BIT_RXCTRLIN0_8822B BIT(4) #define BIT_RXMGTIN0_8822B BIT(3) @@ -9026,9 +14372,18 @@ #define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B 6 #define BIT_MASK_PSF_BSSIDSEL_B2B1_8822B 0x3 -#define BIT_PSF_BSSIDSEL_B2B1_8822B(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) -#define BIT_GET_PSF_BSSIDSEL_B2B1_8822B(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) - +#define BIT_PSF_BSSIDSEL_B2B1_8822B(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) \ + << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) +#define BITS_PSF_BSSIDSEL_B2B1_8822B \ + (BIT_MASK_PSF_BSSIDSEL_B2B1_8822B << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822B(x) \ + ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8822B)) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8822B(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) & \ + BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) +#define BIT_SET_PSF_BSSIDSEL_B2B1_8822B(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822B(x) | BIT_PSF_BSSIDSEL_B2B1_8822B(v)) #define BIT_WOWHCI_8822B BIT(5) #define BIT_PSF_BSSIDSEL_B0_8822B BIT(4) @@ -9042,17 +14397,27 @@ #define BIT_SHIFT_LPNAV_EARLY_8822B 16 #define BIT_MASK_LPNAV_EARLY_8822B 0x7fff -#define BIT_LPNAV_EARLY_8822B(x) (((x) & BIT_MASK_LPNAV_EARLY_8822B) << BIT_SHIFT_LPNAV_EARLY_8822B) -#define BIT_GET_LPNAV_EARLY_8822B(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8822B) & BIT_MASK_LPNAV_EARLY_8822B) - - +#define BIT_LPNAV_EARLY_8822B(x) \ + (((x) & BIT_MASK_LPNAV_EARLY_8822B) << BIT_SHIFT_LPNAV_EARLY_8822B) +#define BITS_LPNAV_EARLY_8822B \ + (BIT_MASK_LPNAV_EARLY_8822B << BIT_SHIFT_LPNAV_EARLY_8822B) +#define BIT_CLEAR_LPNAV_EARLY_8822B(x) ((x) & (~BITS_LPNAV_EARLY_8822B)) +#define BIT_GET_LPNAV_EARLY_8822B(x) \ + (((x) >> BIT_SHIFT_LPNAV_EARLY_8822B) & BIT_MASK_LPNAV_EARLY_8822B) +#define BIT_SET_LPNAV_EARLY_8822B(x, v) \ + (BIT_CLEAR_LPNAV_EARLY_8822B(x) | BIT_LPNAV_EARLY_8822B(v)) #define BIT_SHIFT_LPNAV_TH_8822B 0 #define BIT_MASK_LPNAV_TH_8822B 0xffff -#define BIT_LPNAV_TH_8822B(x) (((x) & BIT_MASK_LPNAV_TH_8822B) << BIT_SHIFT_LPNAV_TH_8822B) -#define BIT_GET_LPNAV_TH_8822B(x) (((x) >> BIT_SHIFT_LPNAV_TH_8822B) & BIT_MASK_LPNAV_TH_8822B) - - +#define BIT_LPNAV_TH_8822B(x) \ + (((x) & BIT_MASK_LPNAV_TH_8822B) << BIT_SHIFT_LPNAV_TH_8822B) +#define BITS_LPNAV_TH_8822B \ + (BIT_MASK_LPNAV_TH_8822B << BIT_SHIFT_LPNAV_TH_8822B) +#define BIT_CLEAR_LPNAV_TH_8822B(x) ((x) & (~BITS_LPNAV_TH_8822B)) +#define BIT_GET_LPNAV_TH_8822B(x) \ + (((x) >> BIT_SHIFT_LPNAV_TH_8822B) & BIT_MASK_LPNAV_TH_8822B) +#define BIT_SET_LPNAV_TH_8822B(x, v) \ + (BIT_CLEAR_LPNAV_TH_8822B(x) | BIT_LPNAV_TH_8822B(v)) /* 2 REG_WKFMCAM_CMD_8822B (WAKEUP FRAME CAM COMMAND REGISTER) */ #define BIT_WKFCAM_POLLING_V1_8822B BIT(31) @@ -9061,26 +14426,46 @@ #define BIT_SHIFT_WKFCAM_ADDR_V2_8822B 8 #define BIT_MASK_WKFCAM_ADDR_V2_8822B 0xff -#define BIT_WKFCAM_ADDR_V2_8822B(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8822B) << BIT_SHIFT_WKFCAM_ADDR_V2_8822B) -#define BIT_GET_WKFCAM_ADDR_V2_8822B(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822B) & BIT_MASK_WKFCAM_ADDR_V2_8822B) - - +#define BIT_WKFCAM_ADDR_V2_8822B(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2_8822B) \ + << BIT_SHIFT_WKFCAM_ADDR_V2_8822B) +#define BITS_WKFCAM_ADDR_V2_8822B \ + (BIT_MASK_WKFCAM_ADDR_V2_8822B << BIT_SHIFT_WKFCAM_ADDR_V2_8822B) +#define BIT_CLEAR_WKFCAM_ADDR_V2_8822B(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8822B)) +#define BIT_GET_WKFCAM_ADDR_V2_8822B(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822B) & \ + BIT_MASK_WKFCAM_ADDR_V2_8822B) +#define BIT_SET_WKFCAM_ADDR_V2_8822B(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2_8822B(x) | BIT_WKFCAM_ADDR_V2_8822B(v)) #define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B 0 #define BIT_MASK_WKFCAM_CAM_NUM_V1_8822B 0xff -#define BIT_WKFCAM_CAM_NUM_V1_8822B(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) -#define BIT_GET_WKFCAM_CAM_NUM_V1_8822B(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) - - +#define BIT_WKFCAM_CAM_NUM_V1_8822B(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) \ + << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) +#define BITS_WKFCAM_CAM_NUM_V1_8822B \ + (BIT_MASK_WKFCAM_CAM_NUM_V1_8822B << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822B(x) \ + ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8822B)) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8822B(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) & \ + BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) +#define BIT_SET_WKFCAM_CAM_NUM_V1_8822B(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822B(x) | BIT_WKFCAM_CAM_NUM_V1_8822B(v)) /* 2 REG_WKFMCAM_RWD_8822B (WAKEUP FRAME READ/WRITE DATA) */ #define BIT_SHIFT_WKFMCAM_RWD_8822B 0 #define BIT_MASK_WKFMCAM_RWD_8822B 0xffffffffL -#define BIT_WKFMCAM_RWD_8822B(x) (((x) & BIT_MASK_WKFMCAM_RWD_8822B) << BIT_SHIFT_WKFMCAM_RWD_8822B) -#define BIT_GET_WKFMCAM_RWD_8822B(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8822B) & BIT_MASK_WKFMCAM_RWD_8822B) - - +#define BIT_WKFMCAM_RWD_8822B(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD_8822B) << BIT_SHIFT_WKFMCAM_RWD_8822B) +#define BITS_WKFMCAM_RWD_8822B \ + (BIT_MASK_WKFMCAM_RWD_8822B << BIT_SHIFT_WKFMCAM_RWD_8822B) +#define BIT_CLEAR_WKFMCAM_RWD_8822B(x) ((x) & (~BITS_WKFMCAM_RWD_8822B)) +#define BIT_GET_WKFMCAM_RWD_8822B(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD_8822B) & BIT_MASK_WKFMCAM_RWD_8822B) +#define BIT_SET_WKFMCAM_RWD_8822B(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD_8822B(x) | BIT_WKFMCAM_RWD_8822B(v)) /* 2 REG_RXFLTMAP1_8822B (RX FILTER MAP GROUP 1) */ #define BIT_CTRLFLT15EN_8822B BIT(15) @@ -9120,7 +14505,7 @@ /* 2 REG_NOT_VALID_8822B */ -/* 2 REG_RXFLTMAP_8822B (RX FILTER MAP GROUP 2) */ +/* 2 REG_RXFLTMAP2_8822B (RX FILTER MAP GROUP 2) */ #define BIT_DATAFLT15EN_8822B BIT(15) #define BIT_DATAFLT14EN_8822B BIT(14) #define BIT_DATAFLT13EN_8822B BIT(13) @@ -9142,26 +14527,42 @@ #define BIT_SHIFT_DTIM_CNT_8822B 24 #define BIT_MASK_DTIM_CNT_8822B 0xff -#define BIT_DTIM_CNT_8822B(x) (((x) & BIT_MASK_DTIM_CNT_8822B) << BIT_SHIFT_DTIM_CNT_8822B) -#define BIT_GET_DTIM_CNT_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT_8822B) & BIT_MASK_DTIM_CNT_8822B) - - +#define BIT_DTIM_CNT_8822B(x) \ + (((x) & BIT_MASK_DTIM_CNT_8822B) << BIT_SHIFT_DTIM_CNT_8822B) +#define BITS_DTIM_CNT_8822B \ + (BIT_MASK_DTIM_CNT_8822B << BIT_SHIFT_DTIM_CNT_8822B) +#define BIT_CLEAR_DTIM_CNT_8822B(x) ((x) & (~BITS_DTIM_CNT_8822B)) +#define BIT_GET_DTIM_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT_8822B) & BIT_MASK_DTIM_CNT_8822B) +#define BIT_SET_DTIM_CNT_8822B(x, v) \ + (BIT_CLEAR_DTIM_CNT_8822B(x) | BIT_DTIM_CNT_8822B(v)) #define BIT_SHIFT_DTIM_PERIOD_8822B 16 #define BIT_MASK_DTIM_PERIOD_8822B 0xff -#define BIT_DTIM_PERIOD_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD_8822B) << BIT_SHIFT_DTIM_PERIOD_8822B) -#define BIT_GET_DTIM_PERIOD_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8822B) & BIT_MASK_DTIM_PERIOD_8822B) - +#define BIT_DTIM_PERIOD_8822B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD_8822B) << BIT_SHIFT_DTIM_PERIOD_8822B) +#define BITS_DTIM_PERIOD_8822B \ + (BIT_MASK_DTIM_PERIOD_8822B << BIT_SHIFT_DTIM_PERIOD_8822B) +#define BIT_CLEAR_DTIM_PERIOD_8822B(x) ((x) & (~BITS_DTIM_PERIOD_8822B)) +#define BIT_GET_DTIM_PERIOD_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD_8822B) & BIT_MASK_DTIM_PERIOD_8822B) +#define BIT_SET_DTIM_PERIOD_8822B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD_8822B(x) | BIT_DTIM_PERIOD_8822B(v)) #define BIT_DTIM_8822B BIT(15) #define BIT_TIM_8822B BIT(14) #define BIT_SHIFT_PS_AID_0_8822B 0 #define BIT_MASK_PS_AID_0_8822B 0x7ff -#define BIT_PS_AID_0_8822B(x) (((x) & BIT_MASK_PS_AID_0_8822B) << BIT_SHIFT_PS_AID_0_8822B) -#define BIT_GET_PS_AID_0_8822B(x) (((x) >> BIT_SHIFT_PS_AID_0_8822B) & BIT_MASK_PS_AID_0_8822B) - - +#define BIT_PS_AID_0_8822B(x) \ + (((x) & BIT_MASK_PS_AID_0_8822B) << BIT_SHIFT_PS_AID_0_8822B) +#define BITS_PS_AID_0_8822B \ + (BIT_MASK_PS_AID_0_8822B << BIT_SHIFT_PS_AID_0_8822B) +#define BIT_CLEAR_PS_AID_0_8822B(x) ((x) & (~BITS_PS_AID_0_8822B)) +#define BIT_GET_PS_AID_0_8822B(x) \ + (((x) >> BIT_SHIFT_PS_AID_0_8822B) & BIT_MASK_PS_AID_0_8822B) +#define BIT_SET_PS_AID_0_8822B(x, v) \ + (BIT_CLEAR_PS_AID_0_8822B(x) | BIT_PS_AID_0_8822B(v)) /* 2 REG_FLC_TRPC_8822B (TIMER OF FLC_RPC) */ #define BIT_FLC_RPCT_V1_8822B BIT(7) @@ -9169,10 +14570,14 @@ #define BIT_SHIFT_TRPCD_8822B 0 #define BIT_MASK_TRPCD_8822B 0x3f -#define BIT_TRPCD_8822B(x) (((x) & BIT_MASK_TRPCD_8822B) << BIT_SHIFT_TRPCD_8822B) -#define BIT_GET_TRPCD_8822B(x) (((x) >> BIT_SHIFT_TRPCD_8822B) & BIT_MASK_TRPCD_8822B) - - +#define BIT_TRPCD_8822B(x) \ + (((x) & BIT_MASK_TRPCD_8822B) << BIT_SHIFT_TRPCD_8822B) +#define BITS_TRPCD_8822B (BIT_MASK_TRPCD_8822B << BIT_SHIFT_TRPCD_8822B) +#define BIT_CLEAR_TRPCD_8822B(x) ((x) & (~BITS_TRPCD_8822B)) +#define BIT_GET_TRPCD_8822B(x) \ + (((x) >> BIT_SHIFT_TRPCD_8822B) & BIT_MASK_TRPCD_8822B) +#define BIT_SET_TRPCD_8822B(x, v) \ + (BIT_CLEAR_TRPCD_8822B(x) | BIT_TRPCD_8822B(v)) /* 2 REG_FLC_PTS_8822B (PKT TYPE SELECTION OF FLC_RPC T) */ #define BIT_CMF_8822B BIT(2) @@ -9183,48 +14588,78 @@ #define BIT_SHIFT_FLC_RPCT_8822B 0 #define BIT_MASK_FLC_RPCT_8822B 0xff -#define BIT_FLC_RPCT_8822B(x) (((x) & BIT_MASK_FLC_RPCT_8822B) << BIT_SHIFT_FLC_RPCT_8822B) -#define BIT_GET_FLC_RPCT_8822B(x) (((x) >> BIT_SHIFT_FLC_RPCT_8822B) & BIT_MASK_FLC_RPCT_8822B) - - +#define BIT_FLC_RPCT_8822B(x) \ + (((x) & BIT_MASK_FLC_RPCT_8822B) << BIT_SHIFT_FLC_RPCT_8822B) +#define BITS_FLC_RPCT_8822B \ + (BIT_MASK_FLC_RPCT_8822B << BIT_SHIFT_FLC_RPCT_8822B) +#define BIT_CLEAR_FLC_RPCT_8822B(x) ((x) & (~BITS_FLC_RPCT_8822B)) +#define BIT_GET_FLC_RPCT_8822B(x) \ + (((x) >> BIT_SHIFT_FLC_RPCT_8822B) & BIT_MASK_FLC_RPCT_8822B) +#define BIT_SET_FLC_RPCT_8822B(x, v) \ + (BIT_CLEAR_FLC_RPCT_8822B(x) | BIT_FLC_RPCT_8822B(v)) /* 2 REG_FLC_RPC_8822B (FW LPS CONDITION -- RX PKT COUNTER) */ #define BIT_SHIFT_FLC_RPC_8822B 0 #define BIT_MASK_FLC_RPC_8822B 0xff -#define BIT_FLC_RPC_8822B(x) (((x) & BIT_MASK_FLC_RPC_8822B) << BIT_SHIFT_FLC_RPC_8822B) -#define BIT_GET_FLC_RPC_8822B(x) (((x) >> BIT_SHIFT_FLC_RPC_8822B) & BIT_MASK_FLC_RPC_8822B) - - +#define BIT_FLC_RPC_8822B(x) \ + (((x) & BIT_MASK_FLC_RPC_8822B) << BIT_SHIFT_FLC_RPC_8822B) +#define BITS_FLC_RPC_8822B (BIT_MASK_FLC_RPC_8822B << BIT_SHIFT_FLC_RPC_8822B) +#define BIT_CLEAR_FLC_RPC_8822B(x) ((x) & (~BITS_FLC_RPC_8822B)) +#define BIT_GET_FLC_RPC_8822B(x) \ + (((x) >> BIT_SHIFT_FLC_RPC_8822B) & BIT_MASK_FLC_RPC_8822B) +#define BIT_SET_FLC_RPC_8822B(x, v) \ + (BIT_CLEAR_FLC_RPC_8822B(x) | BIT_FLC_RPC_8822B(v)) /* 2 REG_RXPKTMON_CTRL_8822B */ #define BIT_SHIFT_RXBKQPKT_SEQ_8822B 20 #define BIT_MASK_RXBKQPKT_SEQ_8822B 0xf -#define BIT_RXBKQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8822B) << BIT_SHIFT_RXBKQPKT_SEQ_8822B) -#define BIT_GET_RXBKQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822B) & BIT_MASK_RXBKQPKT_SEQ_8822B) - - +#define BIT_RXBKQPKT_SEQ_8822B(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ_8822B) << BIT_SHIFT_RXBKQPKT_SEQ_8822B) +#define BITS_RXBKQPKT_SEQ_8822B \ + (BIT_MASK_RXBKQPKT_SEQ_8822B << BIT_SHIFT_RXBKQPKT_SEQ_8822B) +#define BIT_CLEAR_RXBKQPKT_SEQ_8822B(x) ((x) & (~BITS_RXBKQPKT_SEQ_8822B)) +#define BIT_GET_RXBKQPKT_SEQ_8822B(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822B) & BIT_MASK_RXBKQPKT_SEQ_8822B) +#define BIT_SET_RXBKQPKT_SEQ_8822B(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ_8822B(x) | BIT_RXBKQPKT_SEQ_8822B(v)) #define BIT_SHIFT_RXBEQPKT_SEQ_8822B 16 #define BIT_MASK_RXBEQPKT_SEQ_8822B 0xf -#define BIT_RXBEQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8822B) << BIT_SHIFT_RXBEQPKT_SEQ_8822B) -#define BIT_GET_RXBEQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822B) & BIT_MASK_RXBEQPKT_SEQ_8822B) - - +#define BIT_RXBEQPKT_SEQ_8822B(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ_8822B) << BIT_SHIFT_RXBEQPKT_SEQ_8822B) +#define BITS_RXBEQPKT_SEQ_8822B \ + (BIT_MASK_RXBEQPKT_SEQ_8822B << BIT_SHIFT_RXBEQPKT_SEQ_8822B) +#define BIT_CLEAR_RXBEQPKT_SEQ_8822B(x) ((x) & (~BITS_RXBEQPKT_SEQ_8822B)) +#define BIT_GET_RXBEQPKT_SEQ_8822B(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822B) & BIT_MASK_RXBEQPKT_SEQ_8822B) +#define BIT_SET_RXBEQPKT_SEQ_8822B(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ_8822B(x) | BIT_RXBEQPKT_SEQ_8822B(v)) #define BIT_SHIFT_RXVIQPKT_SEQ_8822B 12 #define BIT_MASK_RXVIQPKT_SEQ_8822B 0xf -#define BIT_RXVIQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8822B) << BIT_SHIFT_RXVIQPKT_SEQ_8822B) -#define BIT_GET_RXVIQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822B) & BIT_MASK_RXVIQPKT_SEQ_8822B) - - +#define BIT_RXVIQPKT_SEQ_8822B(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ_8822B) << BIT_SHIFT_RXVIQPKT_SEQ_8822B) +#define BITS_RXVIQPKT_SEQ_8822B \ + (BIT_MASK_RXVIQPKT_SEQ_8822B << BIT_SHIFT_RXVIQPKT_SEQ_8822B) +#define BIT_CLEAR_RXVIQPKT_SEQ_8822B(x) ((x) & (~BITS_RXVIQPKT_SEQ_8822B)) +#define BIT_GET_RXVIQPKT_SEQ_8822B(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822B) & BIT_MASK_RXVIQPKT_SEQ_8822B) +#define BIT_SET_RXVIQPKT_SEQ_8822B(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ_8822B(x) | BIT_RXVIQPKT_SEQ_8822B(v)) #define BIT_SHIFT_RXVOQPKT_SEQ_8822B 8 #define BIT_MASK_RXVOQPKT_SEQ_8822B 0xf -#define BIT_RXVOQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8822B) << BIT_SHIFT_RXVOQPKT_SEQ_8822B) -#define BIT_GET_RXVOQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822B) & BIT_MASK_RXVOQPKT_SEQ_8822B) - +#define BIT_RXVOQPKT_SEQ_8822B(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ_8822B) << BIT_SHIFT_RXVOQPKT_SEQ_8822B) +#define BITS_RXVOQPKT_SEQ_8822B \ + (BIT_MASK_RXVOQPKT_SEQ_8822B << BIT_SHIFT_RXVOQPKT_SEQ_8822B) +#define BIT_CLEAR_RXVOQPKT_SEQ_8822B(x) ((x) & (~BITS_RXVOQPKT_SEQ_8822B)) +#define BIT_GET_RXVOQPKT_SEQ_8822B(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822B) & BIT_MASK_RXVOQPKT_SEQ_8822B) +#define BIT_SET_RXVOQPKT_SEQ_8822B(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ_8822B(x) | BIT_RXVOQPKT_SEQ_8822B(v)) #define BIT_RXBKQPKT_ERR_8822B BIT(7) #define BIT_RXBEQPKT_ERR_8822B BIT(6) @@ -9238,25 +14673,41 @@ #define BIT_SHIFT_STATE_SEL_8822B 24 #define BIT_MASK_STATE_SEL_8822B 0x1f -#define BIT_STATE_SEL_8822B(x) (((x) & BIT_MASK_STATE_SEL_8822B) << BIT_SHIFT_STATE_SEL_8822B) -#define BIT_GET_STATE_SEL_8822B(x) (((x) >> BIT_SHIFT_STATE_SEL_8822B) & BIT_MASK_STATE_SEL_8822B) - - +#define BIT_STATE_SEL_8822B(x) \ + (((x) & BIT_MASK_STATE_SEL_8822B) << BIT_SHIFT_STATE_SEL_8822B) +#define BITS_STATE_SEL_8822B \ + (BIT_MASK_STATE_SEL_8822B << BIT_SHIFT_STATE_SEL_8822B) +#define BIT_CLEAR_STATE_SEL_8822B(x) ((x) & (~BITS_STATE_SEL_8822B)) +#define BIT_GET_STATE_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_STATE_SEL_8822B) & BIT_MASK_STATE_SEL_8822B) +#define BIT_SET_STATE_SEL_8822B(x, v) \ + (BIT_CLEAR_STATE_SEL_8822B(x) | BIT_STATE_SEL_8822B(v)) #define BIT_SHIFT_STATE_INFO_8822B 8 #define BIT_MASK_STATE_INFO_8822B 0xff -#define BIT_STATE_INFO_8822B(x) (((x) & BIT_MASK_STATE_INFO_8822B) << BIT_SHIFT_STATE_INFO_8822B) -#define BIT_GET_STATE_INFO_8822B(x) (((x) >> BIT_SHIFT_STATE_INFO_8822B) & BIT_MASK_STATE_INFO_8822B) - +#define BIT_STATE_INFO_8822B(x) \ + (((x) & BIT_MASK_STATE_INFO_8822B) << BIT_SHIFT_STATE_INFO_8822B) +#define BITS_STATE_INFO_8822B \ + (BIT_MASK_STATE_INFO_8822B << BIT_SHIFT_STATE_INFO_8822B) +#define BIT_CLEAR_STATE_INFO_8822B(x) ((x) & (~BITS_STATE_INFO_8822B)) +#define BIT_GET_STATE_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_STATE_INFO_8822B) & BIT_MASK_STATE_INFO_8822B) +#define BIT_SET_STATE_INFO_8822B(x, v) \ + (BIT_CLEAR_STATE_INFO_8822B(x) | BIT_STATE_INFO_8822B(v)) #define BIT_UPD_NXT_STATE_8822B BIT(7) #define BIT_SHIFT_CUR_STATE_8822B 0 #define BIT_MASK_CUR_STATE_8822B 0x7f -#define BIT_CUR_STATE_8822B(x) (((x) & BIT_MASK_CUR_STATE_8822B) << BIT_SHIFT_CUR_STATE_8822B) -#define BIT_GET_CUR_STATE_8822B(x) (((x) >> BIT_SHIFT_CUR_STATE_8822B) & BIT_MASK_CUR_STATE_8822B) - - +#define BIT_CUR_STATE_8822B(x) \ + (((x) & BIT_MASK_CUR_STATE_8822B) << BIT_SHIFT_CUR_STATE_8822B) +#define BITS_CUR_STATE_8822B \ + (BIT_MASK_CUR_STATE_8822B << BIT_SHIFT_CUR_STATE_8822B) +#define BIT_CLEAR_CUR_STATE_8822B(x) ((x) & (~BITS_CUR_STATE_8822B)) +#define BIT_GET_CUR_STATE_8822B(x) \ + (((x) >> BIT_SHIFT_CUR_STATE_8822B) & BIT_MASK_CUR_STATE_8822B) +#define BIT_SET_CUR_STATE_8822B(x, v) \ + (BIT_CLEAR_CUR_STATE_8822B(x) | BIT_CUR_STATE_8822B(v)) /* 2 REG_ERROR_MON_8822B */ #define BIT_MACRX_ERR_1_8822B BIT(17) @@ -9271,9 +14722,18 @@ #define BIT_SHIFT_INFO_INDEX_OFFSET_8822B 16 #define BIT_MASK_INFO_INDEX_OFFSET_8822B 0x1fff -#define BIT_INFO_INDEX_OFFSET_8822B(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8822B) << BIT_SHIFT_INFO_INDEX_OFFSET_8822B) -#define BIT_GET_INFO_INDEX_OFFSET_8822B(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822B) & BIT_MASK_INFO_INDEX_OFFSET_8822B) - +#define BIT_INFO_INDEX_OFFSET_8822B(x) \ + (((x) & BIT_MASK_INFO_INDEX_OFFSET_8822B) \ + << BIT_SHIFT_INFO_INDEX_OFFSET_8822B) +#define BITS_INFO_INDEX_OFFSET_8822B \ + (BIT_MASK_INFO_INDEX_OFFSET_8822B << BIT_SHIFT_INFO_INDEX_OFFSET_8822B) +#define BIT_CLEAR_INFO_INDEX_OFFSET_8822B(x) \ + ((x) & (~BITS_INFO_INDEX_OFFSET_8822B)) +#define BIT_GET_INFO_INDEX_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822B) & \ + BIT_MASK_INFO_INDEX_OFFSET_8822B) +#define BIT_SET_INFO_INDEX_OFFSET_8822B(x, v) \ + (BIT_CLEAR_INFO_INDEX_OFFSET_8822B(x) | BIT_INFO_INDEX_OFFSET_8822B(v)) #define BIT_WMAC_SRCH_FIFOFULL_8822B BIT(15) #define BIT_DIS_INFOSRCH_8822B BIT(14) @@ -9281,10 +14741,18 @@ #define BIT_SHIFT_INFO_ADDR_OFFSET_8822B 0 #define BIT_MASK_INFO_ADDR_OFFSET_8822B 0x1fff -#define BIT_INFO_ADDR_OFFSET_8822B(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8822B) << BIT_SHIFT_INFO_ADDR_OFFSET_8822B) -#define BIT_GET_INFO_ADDR_OFFSET_8822B(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822B) & BIT_MASK_INFO_ADDR_OFFSET_8822B) - - +#define BIT_INFO_ADDR_OFFSET_8822B(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET_8822B) \ + << BIT_SHIFT_INFO_ADDR_OFFSET_8822B) +#define BITS_INFO_ADDR_OFFSET_8822B \ + (BIT_MASK_INFO_ADDR_OFFSET_8822B << BIT_SHIFT_INFO_ADDR_OFFSET_8822B) +#define BIT_CLEAR_INFO_ADDR_OFFSET_8822B(x) \ + ((x) & (~BITS_INFO_ADDR_OFFSET_8822B)) +#define BIT_GET_INFO_ADDR_OFFSET_8822B(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822B) & \ + BIT_MASK_INFO_ADDR_OFFSET_8822B) +#define BIT_SET_INFO_ADDR_OFFSET_8822B(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET_8822B(x) | BIT_INFO_ADDR_OFFSET_8822B(v)) /* 2 REG_BT_COEX_TABLE_8822B (BT-COEXISTENCE CONTROL REGISTER) */ #define BIT_PRI_MASK_RX_RESP_8822B BIT(126) @@ -9293,16 +14761,27 @@ #define BIT_SHIFT_PRI_MASK_TXAC_8822B (117 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_TXAC_8822B 0x7f -#define BIT_PRI_MASK_TXAC_8822B(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8822B) << BIT_SHIFT_PRI_MASK_TXAC_8822B) -#define BIT_GET_PRI_MASK_TXAC_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822B) & BIT_MASK_PRI_MASK_TXAC_8822B) - - +#define BIT_PRI_MASK_TXAC_8822B(x) \ + (((x) & BIT_MASK_PRI_MASK_TXAC_8822B) << BIT_SHIFT_PRI_MASK_TXAC_8822B) +#define BITS_PRI_MASK_TXAC_8822B \ + (BIT_MASK_PRI_MASK_TXAC_8822B << BIT_SHIFT_PRI_MASK_TXAC_8822B) +#define BIT_CLEAR_PRI_MASK_TXAC_8822B(x) ((x) & (~BITS_PRI_MASK_TXAC_8822B)) +#define BIT_GET_PRI_MASK_TXAC_8822B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822B) & BIT_MASK_PRI_MASK_TXAC_8822B) +#define BIT_SET_PRI_MASK_TXAC_8822B(x, v) \ + (BIT_CLEAR_PRI_MASK_TXAC_8822B(x) | BIT_PRI_MASK_TXAC_8822B(v)) #define BIT_SHIFT_PRI_MASK_NAV_8822B (109 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_NAV_8822B 0xff -#define BIT_PRI_MASK_NAV_8822B(x) (((x) & BIT_MASK_PRI_MASK_NAV_8822B) << BIT_SHIFT_PRI_MASK_NAV_8822B) -#define BIT_GET_PRI_MASK_NAV_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8822B) & BIT_MASK_PRI_MASK_NAV_8822B) - +#define BIT_PRI_MASK_NAV_8822B(x) \ + (((x) & BIT_MASK_PRI_MASK_NAV_8822B) << BIT_SHIFT_PRI_MASK_NAV_8822B) +#define BITS_PRI_MASK_NAV_8822B \ + (BIT_MASK_PRI_MASK_NAV_8822B << BIT_SHIFT_PRI_MASK_NAV_8822B) +#define BIT_CLEAR_PRI_MASK_NAV_8822B(x) ((x) & (~BITS_PRI_MASK_NAV_8822B)) +#define BIT_GET_PRI_MASK_NAV_8822B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NAV_8822B) & BIT_MASK_PRI_MASK_NAV_8822B) +#define BIT_SET_PRI_MASK_NAV_8822B(x, v) \ + (BIT_CLEAR_PRI_MASK_NAV_8822B(x) | BIT_PRI_MASK_NAV_8822B(v)) #define BIT_PRI_MASK_CCK_8822B BIT(108) #define BIT_PRI_MASK_OFDM_8822B BIT(107) @@ -9310,66 +14789,107 @@ #define BIT_SHIFT_PRI_MASK_NUM_8822B (102 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_NUM_8822B 0xf -#define BIT_PRI_MASK_NUM_8822B(x) (((x) & BIT_MASK_PRI_MASK_NUM_8822B) << BIT_SHIFT_PRI_MASK_NUM_8822B) -#define BIT_GET_PRI_MASK_NUM_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8822B) & BIT_MASK_PRI_MASK_NUM_8822B) - - +#define BIT_PRI_MASK_NUM_8822B(x) \ + (((x) & BIT_MASK_PRI_MASK_NUM_8822B) << BIT_SHIFT_PRI_MASK_NUM_8822B) +#define BITS_PRI_MASK_NUM_8822B \ + (BIT_MASK_PRI_MASK_NUM_8822B << BIT_SHIFT_PRI_MASK_NUM_8822B) +#define BIT_CLEAR_PRI_MASK_NUM_8822B(x) ((x) & (~BITS_PRI_MASK_NUM_8822B)) +#define BIT_GET_PRI_MASK_NUM_8822B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NUM_8822B) & BIT_MASK_PRI_MASK_NUM_8822B) +#define BIT_SET_PRI_MASK_NUM_8822B(x, v) \ + (BIT_CLEAR_PRI_MASK_NUM_8822B(x) | BIT_PRI_MASK_NUM_8822B(v)) #define BIT_SHIFT_PRI_MASK_TYPE_8822B (98 & CPU_OPT_WIDTH) #define BIT_MASK_PRI_MASK_TYPE_8822B 0xf -#define BIT_PRI_MASK_TYPE_8822B(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8822B) << BIT_SHIFT_PRI_MASK_TYPE_8822B) -#define BIT_GET_PRI_MASK_TYPE_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822B) & BIT_MASK_PRI_MASK_TYPE_8822B) - +#define BIT_PRI_MASK_TYPE_8822B(x) \ + (((x) & BIT_MASK_PRI_MASK_TYPE_8822B) << BIT_SHIFT_PRI_MASK_TYPE_8822B) +#define BITS_PRI_MASK_TYPE_8822B \ + (BIT_MASK_PRI_MASK_TYPE_8822B << BIT_SHIFT_PRI_MASK_TYPE_8822B) +#define BIT_CLEAR_PRI_MASK_TYPE_8822B(x) ((x) & (~BITS_PRI_MASK_TYPE_8822B)) +#define BIT_GET_PRI_MASK_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822B) & BIT_MASK_PRI_MASK_TYPE_8822B) +#define BIT_SET_PRI_MASK_TYPE_8822B(x, v) \ + (BIT_CLEAR_PRI_MASK_TYPE_8822B(x) | BIT_PRI_MASK_TYPE_8822B(v)) #define BIT_OOB_8822B BIT(97) #define BIT_ANT_SEL_8822B BIT(96) #define BIT_SHIFT_BREAK_TABLE_2_8822B (80 & CPU_OPT_WIDTH) #define BIT_MASK_BREAK_TABLE_2_8822B 0xffff -#define BIT_BREAK_TABLE_2_8822B(x) (((x) & BIT_MASK_BREAK_TABLE_2_8822B) << BIT_SHIFT_BREAK_TABLE_2_8822B) -#define BIT_GET_BREAK_TABLE_2_8822B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8822B) & BIT_MASK_BREAK_TABLE_2_8822B) - - +#define BIT_BREAK_TABLE_2_8822B(x) \ + (((x) & BIT_MASK_BREAK_TABLE_2_8822B) << BIT_SHIFT_BREAK_TABLE_2_8822B) +#define BITS_BREAK_TABLE_2_8822B \ + (BIT_MASK_BREAK_TABLE_2_8822B << BIT_SHIFT_BREAK_TABLE_2_8822B) +#define BIT_CLEAR_BREAK_TABLE_2_8822B(x) ((x) & (~BITS_BREAK_TABLE_2_8822B)) +#define BIT_GET_BREAK_TABLE_2_8822B(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_2_8822B) & BIT_MASK_BREAK_TABLE_2_8822B) +#define BIT_SET_BREAK_TABLE_2_8822B(x, v) \ + (BIT_CLEAR_BREAK_TABLE_2_8822B(x) | BIT_BREAK_TABLE_2_8822B(v)) #define BIT_SHIFT_BREAK_TABLE_1_8822B (64 & CPU_OPT_WIDTH) #define BIT_MASK_BREAK_TABLE_1_8822B 0xffff -#define BIT_BREAK_TABLE_1_8822B(x) (((x) & BIT_MASK_BREAK_TABLE_1_8822B) << BIT_SHIFT_BREAK_TABLE_1_8822B) -#define BIT_GET_BREAK_TABLE_1_8822B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8822B) & BIT_MASK_BREAK_TABLE_1_8822B) - - +#define BIT_BREAK_TABLE_1_8822B(x) \ + (((x) & BIT_MASK_BREAK_TABLE_1_8822B) << BIT_SHIFT_BREAK_TABLE_1_8822B) +#define BITS_BREAK_TABLE_1_8822B \ + (BIT_MASK_BREAK_TABLE_1_8822B << BIT_SHIFT_BREAK_TABLE_1_8822B) +#define BIT_CLEAR_BREAK_TABLE_1_8822B(x) ((x) & (~BITS_BREAK_TABLE_1_8822B)) +#define BIT_GET_BREAK_TABLE_1_8822B(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_1_8822B) & BIT_MASK_BREAK_TABLE_1_8822B) +#define BIT_SET_BREAK_TABLE_1_8822B(x, v) \ + (BIT_CLEAR_BREAK_TABLE_1_8822B(x) | BIT_BREAK_TABLE_1_8822B(v)) #define BIT_SHIFT_COEX_TABLE_2_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_COEX_TABLE_2_8822B 0xffffffffL -#define BIT_COEX_TABLE_2_8822B(x) (((x) & BIT_MASK_COEX_TABLE_2_8822B) << BIT_SHIFT_COEX_TABLE_2_8822B) -#define BIT_GET_COEX_TABLE_2_8822B(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8822B) & BIT_MASK_COEX_TABLE_2_8822B) - - +#define BIT_COEX_TABLE_2_8822B(x) \ + (((x) & BIT_MASK_COEX_TABLE_2_8822B) << BIT_SHIFT_COEX_TABLE_2_8822B) +#define BITS_COEX_TABLE_2_8822B \ + (BIT_MASK_COEX_TABLE_2_8822B << BIT_SHIFT_COEX_TABLE_2_8822B) +#define BIT_CLEAR_COEX_TABLE_2_8822B(x) ((x) & (~BITS_COEX_TABLE_2_8822B)) +#define BIT_GET_COEX_TABLE_2_8822B(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_2_8822B) & BIT_MASK_COEX_TABLE_2_8822B) +#define BIT_SET_COEX_TABLE_2_8822B(x, v) \ + (BIT_CLEAR_COEX_TABLE_2_8822B(x) | BIT_COEX_TABLE_2_8822B(v)) #define BIT_SHIFT_COEX_TABLE_1_8822B 0 #define BIT_MASK_COEX_TABLE_1_8822B 0xffffffffL -#define BIT_COEX_TABLE_1_8822B(x) (((x) & BIT_MASK_COEX_TABLE_1_8822B) << BIT_SHIFT_COEX_TABLE_1_8822B) -#define BIT_GET_COEX_TABLE_1_8822B(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8822B) & BIT_MASK_COEX_TABLE_1_8822B) - - +#define BIT_COEX_TABLE_1_8822B(x) \ + (((x) & BIT_MASK_COEX_TABLE_1_8822B) << BIT_SHIFT_COEX_TABLE_1_8822B) +#define BITS_COEX_TABLE_1_8822B \ + (BIT_MASK_COEX_TABLE_1_8822B << BIT_SHIFT_COEX_TABLE_1_8822B) +#define BIT_CLEAR_COEX_TABLE_1_8822B(x) ((x) & (~BITS_COEX_TABLE_1_8822B)) +#define BIT_GET_COEX_TABLE_1_8822B(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1_8822B) & BIT_MASK_COEX_TABLE_1_8822B) +#define BIT_SET_COEX_TABLE_1_8822B(x, v) \ + (BIT_CLEAR_COEX_TABLE_1_8822B(x) | BIT_COEX_TABLE_1_8822B(v)) /* 2 REG_RXCMD_0_8822B */ #define BIT_RXCMD_EN_8822B BIT(31) #define BIT_SHIFT_RXCMD_INFO_8822B 0 #define BIT_MASK_RXCMD_INFO_8822B 0x7fffffffL -#define BIT_RXCMD_INFO_8822B(x) (((x) & BIT_MASK_RXCMD_INFO_8822B) << BIT_SHIFT_RXCMD_INFO_8822B) -#define BIT_GET_RXCMD_INFO_8822B(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8822B) & BIT_MASK_RXCMD_INFO_8822B) - - +#define BIT_RXCMD_INFO_8822B(x) \ + (((x) & BIT_MASK_RXCMD_INFO_8822B) << BIT_SHIFT_RXCMD_INFO_8822B) +#define BITS_RXCMD_INFO_8822B \ + (BIT_MASK_RXCMD_INFO_8822B << BIT_SHIFT_RXCMD_INFO_8822B) +#define BIT_CLEAR_RXCMD_INFO_8822B(x) ((x) & (~BITS_RXCMD_INFO_8822B)) +#define BIT_GET_RXCMD_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO_8822B) & BIT_MASK_RXCMD_INFO_8822B) +#define BIT_SET_RXCMD_INFO_8822B(x, v) \ + (BIT_CLEAR_RXCMD_INFO_8822B(x) | BIT_RXCMD_INFO_8822B(v)) /* 2 REG_RXCMD_1_8822B */ #define BIT_SHIFT_RXCMD_PRD_8822B 0 #define BIT_MASK_RXCMD_PRD_8822B 0xffff -#define BIT_RXCMD_PRD_8822B(x) (((x) & BIT_MASK_RXCMD_PRD_8822B) << BIT_SHIFT_RXCMD_PRD_8822B) -#define BIT_GET_RXCMD_PRD_8822B(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8822B) & BIT_MASK_RXCMD_PRD_8822B) - - +#define BIT_RXCMD_PRD_8822B(x) \ + (((x) & BIT_MASK_RXCMD_PRD_8822B) << BIT_SHIFT_RXCMD_PRD_8822B) +#define BITS_RXCMD_PRD_8822B \ + (BIT_MASK_RXCMD_PRD_8822B << BIT_SHIFT_RXCMD_PRD_8822B) +#define BIT_CLEAR_RXCMD_PRD_8822B(x) ((x) & (~BITS_RXCMD_PRD_8822B)) +#define BIT_GET_RXCMD_PRD_8822B(x) \ + (((x) >> BIT_SHIFT_RXCMD_PRD_8822B) & BIT_MASK_RXCMD_PRD_8822B) +#define BIT_SET_RXCMD_PRD_8822B(x, v) \ + (BIT_CLEAR_RXCMD_PRD_8822B(x) | BIT_RXCMD_PRD_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -9377,38 +14897,74 @@ #define BIT_SHIFT_WMAC_RESP_MFB_8822B 25 #define BIT_MASK_WMAC_RESP_MFB_8822B 0x7f -#define BIT_WMAC_RESP_MFB_8822B(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8822B) << BIT_SHIFT_WMAC_RESP_MFB_8822B) -#define BIT_GET_WMAC_RESP_MFB_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822B) & BIT_MASK_WMAC_RESP_MFB_8822B) - - +#define BIT_WMAC_RESP_MFB_8822B(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB_8822B) << BIT_SHIFT_WMAC_RESP_MFB_8822B) +#define BITS_WMAC_RESP_MFB_8822B \ + (BIT_MASK_WMAC_RESP_MFB_8822B << BIT_SHIFT_WMAC_RESP_MFB_8822B) +#define BIT_CLEAR_WMAC_RESP_MFB_8822B(x) ((x) & (~BITS_WMAC_RESP_MFB_8822B)) +#define BIT_GET_WMAC_RESP_MFB_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822B) & BIT_MASK_WMAC_RESP_MFB_8822B) +#define BIT_SET_WMAC_RESP_MFB_8822B(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB_8822B(x) | BIT_WMAC_RESP_MFB_8822B(v)) #define BIT_SHIFT_WMAC_ANTINF_SEL_8822B 23 #define BIT_MASK_WMAC_ANTINF_SEL_8822B 0x3 -#define BIT_WMAC_ANTINF_SEL_8822B(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8822B) << BIT_SHIFT_WMAC_ANTINF_SEL_8822B) -#define BIT_GET_WMAC_ANTINF_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822B) & BIT_MASK_WMAC_ANTINF_SEL_8822B) - - +#define BIT_WMAC_ANTINF_SEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL_8822B) \ + << BIT_SHIFT_WMAC_ANTINF_SEL_8822B) +#define BITS_WMAC_ANTINF_SEL_8822B \ + (BIT_MASK_WMAC_ANTINF_SEL_8822B << BIT_SHIFT_WMAC_ANTINF_SEL_8822B) +#define BIT_CLEAR_WMAC_ANTINF_SEL_8822B(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8822B)) +#define BIT_GET_WMAC_ANTINF_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822B) & \ + BIT_MASK_WMAC_ANTINF_SEL_8822B) +#define BIT_SET_WMAC_ANTINF_SEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL_8822B(x) | BIT_WMAC_ANTINF_SEL_8822B(v)) #define BIT_SHIFT_WMAC_ANTSEL_SEL_8822B 21 #define BIT_MASK_WMAC_ANTSEL_SEL_8822B 0x3 -#define BIT_WMAC_ANTSEL_SEL_8822B(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822B) << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) -#define BIT_GET_WMAC_ANTSEL_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) & BIT_MASK_WMAC_ANTSEL_SEL_8822B) - - +#define BIT_WMAC_ANTSEL_SEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822B) \ + << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) +#define BITS_WMAC_ANTSEL_SEL_8822B \ + (BIT_MASK_WMAC_ANTSEL_SEL_8822B << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) +#define BIT_CLEAR_WMAC_ANTSEL_SEL_8822B(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8822B)) +#define BIT_GET_WMAC_ANTSEL_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) & \ + BIT_MASK_WMAC_ANTSEL_SEL_8822B) +#define BIT_SET_WMAC_ANTSEL_SEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL_8822B(x) | BIT_WMAC_ANTSEL_SEL_8822B(v)) #define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B 18 #define BIT_MASK_R_WMAC_RESP_TXPOWER_8822B 0x7 -#define BIT_R_WMAC_RESP_TXPOWER_8822B(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) -#define BIT_GET_R_WMAC_RESP_TXPOWER_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) - - +#define BIT_R_WMAC_RESP_TXPOWER_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) +#define BITS_R_WMAC_RESP_TXPOWER_8822B \ + (BIT_MASK_R_WMAC_RESP_TXPOWER_8822B \ + << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) +#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8822B(x) \ + ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8822B)) +#define BIT_GET_R_WMAC_RESP_TXPOWER_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) & \ + BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) +#define BIT_SET_R_WMAC_RESP_TXPOWER_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8822B(x) | \ + BIT_R_WMAC_RESP_TXPOWER_8822B(v)) #define BIT_SHIFT_WMAC_RESP_TXANT_8822B 0 #define BIT_MASK_WMAC_RESP_TXANT_8822B 0x3ffff -#define BIT_WMAC_RESP_TXANT_8822B(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8822B) << BIT_SHIFT_WMAC_RESP_TXANT_8822B) -#define BIT_GET_WMAC_RESP_TXANT_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8822B) & BIT_MASK_WMAC_RESP_TXANT_8822B) - - +#define BIT_WMAC_RESP_TXANT_8822B(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_8822B) \ + << BIT_SHIFT_WMAC_RESP_TXANT_8822B) +#define BITS_WMAC_RESP_TXANT_8822B \ + (BIT_MASK_WMAC_RESP_TXANT_8822B << BIT_SHIFT_WMAC_RESP_TXANT_8822B) +#define BIT_CLEAR_WMAC_RESP_TXANT_8822B(x) ((x) & (~BITS_WMAC_RESP_TXANT_8822B)) +#define BIT_GET_WMAC_RESP_TXANT_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8822B) & \ + BIT_MASK_WMAC_RESP_TXANT_8822B) +#define BIT_SET_WMAC_RESP_TXANT_8822B(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_8822B(x) | BIT_WMAC_RESP_TXANT_8822B(v)) /* 2 REG_BBPSF_CTRL_8822B */ #define BIT_CTL_IDLE_CLR_CSI_RPT_8822B BIT(31) @@ -9416,16 +14972,30 @@ #define BIT_SHIFT_WMAC_CSI_RATE_8822B 24 #define BIT_MASK_WMAC_CSI_RATE_8822B 0x3f -#define BIT_WMAC_CSI_RATE_8822B(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8822B) << BIT_SHIFT_WMAC_CSI_RATE_8822B) -#define BIT_GET_WMAC_CSI_RATE_8822B(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822B) & BIT_MASK_WMAC_CSI_RATE_8822B) - - +#define BIT_WMAC_CSI_RATE_8822B(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE_8822B) << BIT_SHIFT_WMAC_CSI_RATE_8822B) +#define BITS_WMAC_CSI_RATE_8822B \ + (BIT_MASK_WMAC_CSI_RATE_8822B << BIT_SHIFT_WMAC_CSI_RATE_8822B) +#define BIT_CLEAR_WMAC_CSI_RATE_8822B(x) ((x) & (~BITS_WMAC_CSI_RATE_8822B)) +#define BIT_GET_WMAC_CSI_RATE_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822B) & BIT_MASK_WMAC_CSI_RATE_8822B) +#define BIT_SET_WMAC_CSI_RATE_8822B(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE_8822B(x) | BIT_WMAC_CSI_RATE_8822B(v)) #define BIT_SHIFT_WMAC_RESP_TXRATE_8822B 16 #define BIT_MASK_WMAC_RESP_TXRATE_8822B 0xff -#define BIT_WMAC_RESP_TXRATE_8822B(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8822B) << BIT_SHIFT_WMAC_RESP_TXRATE_8822B) -#define BIT_GET_WMAC_RESP_TXRATE_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822B) & BIT_MASK_WMAC_RESP_TXRATE_8822B) - +#define BIT_WMAC_RESP_TXRATE_8822B(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE_8822B) \ + << BIT_SHIFT_WMAC_RESP_TXRATE_8822B) +#define BITS_WMAC_RESP_TXRATE_8822B \ + (BIT_MASK_WMAC_RESP_TXRATE_8822B << BIT_SHIFT_WMAC_RESP_TXRATE_8822B) +#define BIT_CLEAR_WMAC_RESP_TXRATE_8822B(x) \ + ((x) & (~BITS_WMAC_RESP_TXRATE_8822B)) +#define BIT_GET_WMAC_RESP_TXRATE_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822B) & \ + BIT_MASK_WMAC_RESP_TXRATE_8822B) +#define BIT_SET_WMAC_RESP_TXRATE_8822B(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE_8822B(x) | BIT_WMAC_RESP_TXRATE_8822B(v)) #define BIT_BBPSF_MPDUCHKEN_8822B BIT(5) #define BIT_BBPSF_MHCHKEN_8822B BIT(4) @@ -9433,10 +15003,15 @@ #define BIT_SHIFT_BBPSF_ERRTHR_8822B 0 #define BIT_MASK_BBPSF_ERRTHR_8822B 0x7 -#define BIT_BBPSF_ERRTHR_8822B(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8822B) << BIT_SHIFT_BBPSF_ERRTHR_8822B) -#define BIT_GET_BBPSF_ERRTHR_8822B(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8822B) & BIT_MASK_BBPSF_ERRTHR_8822B) - - +#define BIT_BBPSF_ERRTHR_8822B(x) \ + (((x) & BIT_MASK_BBPSF_ERRTHR_8822B) << BIT_SHIFT_BBPSF_ERRTHR_8822B) +#define BITS_BBPSF_ERRTHR_8822B \ + (BIT_MASK_BBPSF_ERRTHR_8822B << BIT_SHIFT_BBPSF_ERRTHR_8822B) +#define BIT_CLEAR_BBPSF_ERRTHR_8822B(x) ((x) & (~BITS_BBPSF_ERRTHR_8822B)) +#define BIT_GET_BBPSF_ERRTHR_8822B(x) \ + (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8822B) & BIT_MASK_BBPSF_ERRTHR_8822B) +#define BIT_SET_BBPSF_ERRTHR_8822B(x, v) \ + (BIT_CLEAR_BBPSF_ERRTHR_8822B(x) | BIT_BBPSF_ERRTHR_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -9446,67 +15021,135 @@ #define BIT_SHIFT_P2P_OUI_TYPE_8822B 0 #define BIT_MASK_P2P_OUI_TYPE_8822B 0xff -#define BIT_P2P_OUI_TYPE_8822B(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8822B) << BIT_SHIFT_P2P_OUI_TYPE_8822B) -#define BIT_GET_P2P_OUI_TYPE_8822B(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822B) & BIT_MASK_P2P_OUI_TYPE_8822B) - - +#define BIT_P2P_OUI_TYPE_8822B(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE_8822B) << BIT_SHIFT_P2P_OUI_TYPE_8822B) +#define BITS_P2P_OUI_TYPE_8822B \ + (BIT_MASK_P2P_OUI_TYPE_8822B << BIT_SHIFT_P2P_OUI_TYPE_8822B) +#define BIT_CLEAR_P2P_OUI_TYPE_8822B(x) ((x) & (~BITS_P2P_OUI_TYPE_8822B)) +#define BIT_GET_P2P_OUI_TYPE_8822B(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822B) & BIT_MASK_P2P_OUI_TYPE_8822B) +#define BIT_SET_P2P_OUI_TYPE_8822B(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE_8822B(x) | BIT_P2P_OUI_TYPE_8822B(v)) /* 2 REG_ASSOCIATED_BFMER0_INFO_8822B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_TXCSI_AID0_8822B 0x1ff -#define BIT_R_WMAC_TXCSI_AID0_8822B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) -#define BIT_GET_R_WMAC_TXCSI_AID0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B) - - +#define BIT_R_WMAC_TXCSI_AID0_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) +#define BITS_R_WMAC_TXCSI_AID0_8822B \ + (BIT_MASK_R_WMAC_TXCSI_AID0_8822B << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) +#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8822B(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID0_8822B)) +#define BIT_GET_R_WMAC_TXCSI_AID0_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) & \ + BIT_MASK_R_WMAC_TXCSI_AID0_8822B) +#define BIT_SET_R_WMAC_TXCSI_AID0_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID0_8822B(x) | BIT_R_WMAC_TXCSI_AID0_8822B(v)) #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) - - +#define BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_8822B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8822B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8822B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8822B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(v)) /* 2 REG_ASSOCIATED_BFMER1_INFO_8822B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ #define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_TXCSI_AID1_8822B 0x1ff -#define BIT_R_WMAC_TXCSI_AID1_8822B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) -#define BIT_GET_R_WMAC_TXCSI_AID1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B) - - +#define BIT_R_WMAC_TXCSI_AID1_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) +#define BITS_R_WMAC_TXCSI_AID1_8822B \ + (BIT_MASK_R_WMAC_TXCSI_AID1_8822B << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) +#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8822B(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID1_8822B)) +#define BIT_GET_R_WMAC_TXCSI_AID1_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) & \ + BIT_MASK_R_WMAC_TXCSI_AID1_8822B) +#define BIT_SET_R_WMAC_TXCSI_AID1_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID1_8822B(x) | BIT_R_WMAC_TXCSI_AID1_8822B(v)) #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B 0 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B 0xffffffffffffL -#define BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) -#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) - - +#define BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_8822B \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8822B(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8822B)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8822B(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW20_8822B (TX CSI REPORT PARAMETER REGISTER) */ #define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B 16 #define BIT_MASK_R_WMAC_BFINFO_20M_1_8822B 0xfff -#define BIT_R_WMAC_BFINFO_20M_1_8822B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) -#define BIT_GET_R_WMAC_BFINFO_20M_1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) - - +#define BIT_R_WMAC_BFINFO_20M_1_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) +#define BITS_R_WMAC_BFINFO_20M_1_8822B \ + (BIT_MASK_R_WMAC_BFINFO_20M_1_8822B \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822B(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8822B)) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) & \ + BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) +#define BIT_SET_R_WMAC_BFINFO_20M_1_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822B(x) | \ + BIT_R_WMAC_BFINFO_20M_1_8822B(v)) #define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B 0 #define BIT_MASK_R_WMAC_BFINFO_20M_0_8822B 0xfff -#define BIT_R_WMAC_BFINFO_20M_0_8822B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) -#define BIT_GET_R_WMAC_BFINFO_20M_0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) - - +#define BIT_R_WMAC_BFINFO_20M_0_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) +#define BITS_R_WMAC_BFINFO_20M_0_8822B \ + (BIT_MASK_R_WMAC_BFINFO_20M_0_8822B \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822B(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8822B)) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) & \ + BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) +#define BIT_SET_R_WMAC_BFINFO_20M_0_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822B(x) | \ + BIT_R_WMAC_BFINFO_20M_0_8822B(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW40_8822B (TX CSI REPORT PARAMETER_BW40 REGISTER) */ #define BIT_SHIFT_WMAC_RESP_ANTCD_8822B 0 #define BIT_MASK_WMAC_RESP_ANTCD_8822B 0xf -#define BIT_WMAC_RESP_ANTCD_8822B(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8822B) << BIT_SHIFT_WMAC_RESP_ANTCD_8822B) -#define BIT_GET_WMAC_RESP_ANTCD_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8822B) & BIT_MASK_WMAC_RESP_ANTCD_8822B) - - +#define BIT_WMAC_RESP_ANTCD_8822B(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTCD_8822B) \ + << BIT_SHIFT_WMAC_RESP_ANTCD_8822B) +#define BITS_WMAC_RESP_ANTCD_8822B \ + (BIT_MASK_WMAC_RESP_ANTCD_8822B << BIT_SHIFT_WMAC_RESP_ANTCD_8822B) +#define BIT_CLEAR_WMAC_RESP_ANTCD_8822B(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8822B)) +#define BIT_GET_WMAC_RESP_ANTCD_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8822B) & \ + BIT_MASK_WMAC_RESP_ANTCD_8822B) +#define BIT_SET_WMAC_RESP_ANTCD_8822B(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTCD_8822B(x) | BIT_WMAC_RESP_ANTCD_8822B(v)) /* 2 REG_TX_CSI_RPT_PARAM_BW80_8822B (TX CSI REPORT PARAMETER_BW80 REGISTER) */ @@ -9514,139 +15157,216 @@ #define BIT_SHIFT_DTIM_CNT2_8822B 24 #define BIT_MASK_DTIM_CNT2_8822B 0xff -#define BIT_DTIM_CNT2_8822B(x) (((x) & BIT_MASK_DTIM_CNT2_8822B) << BIT_SHIFT_DTIM_CNT2_8822B) -#define BIT_GET_DTIM_CNT2_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8822B) & BIT_MASK_DTIM_CNT2_8822B) - - +#define BIT_DTIM_CNT2_8822B(x) \ + (((x) & BIT_MASK_DTIM_CNT2_8822B) << BIT_SHIFT_DTIM_CNT2_8822B) +#define BITS_DTIM_CNT2_8822B \ + (BIT_MASK_DTIM_CNT2_8822B << BIT_SHIFT_DTIM_CNT2_8822B) +#define BIT_CLEAR_DTIM_CNT2_8822B(x) ((x) & (~BITS_DTIM_CNT2_8822B)) +#define BIT_GET_DTIM_CNT2_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT2_8822B) & BIT_MASK_DTIM_CNT2_8822B) +#define BIT_SET_DTIM_CNT2_8822B(x, v) \ + (BIT_CLEAR_DTIM_CNT2_8822B(x) | BIT_DTIM_CNT2_8822B(v)) #define BIT_SHIFT_DTIM_PERIOD2_8822B 16 #define BIT_MASK_DTIM_PERIOD2_8822B 0xff -#define BIT_DTIM_PERIOD2_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD2_8822B) << BIT_SHIFT_DTIM_PERIOD2_8822B) -#define BIT_GET_DTIM_PERIOD2_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8822B) & BIT_MASK_DTIM_PERIOD2_8822B) - +#define BIT_DTIM_PERIOD2_8822B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2_8822B) << BIT_SHIFT_DTIM_PERIOD2_8822B) +#define BITS_DTIM_PERIOD2_8822B \ + (BIT_MASK_DTIM_PERIOD2_8822B << BIT_SHIFT_DTIM_PERIOD2_8822B) +#define BIT_CLEAR_DTIM_PERIOD2_8822B(x) ((x) & (~BITS_DTIM_PERIOD2_8822B)) +#define BIT_GET_DTIM_PERIOD2_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2_8822B) & BIT_MASK_DTIM_PERIOD2_8822B) +#define BIT_SET_DTIM_PERIOD2_8822B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2_8822B(x) | BIT_DTIM_PERIOD2_8822B(v)) #define BIT_DTIM2_8822B BIT(15) #define BIT_TIM2_8822B BIT(14) #define BIT_SHIFT_PS_AID_2_8822B 0 #define BIT_MASK_PS_AID_2_8822B 0x7ff -#define BIT_PS_AID_2_8822B(x) (((x) & BIT_MASK_PS_AID_2_8822B) << BIT_SHIFT_PS_AID_2_8822B) -#define BIT_GET_PS_AID_2_8822B(x) (((x) >> BIT_SHIFT_PS_AID_2_8822B) & BIT_MASK_PS_AID_2_8822B) - - +#define BIT_PS_AID_2_8822B(x) \ + (((x) & BIT_MASK_PS_AID_2_8822B) << BIT_SHIFT_PS_AID_2_8822B) +#define BITS_PS_AID_2_8822B \ + (BIT_MASK_PS_AID_2_8822B << BIT_SHIFT_PS_AID_2_8822B) +#define BIT_CLEAR_PS_AID_2_8822B(x) ((x) & (~BITS_PS_AID_2_8822B)) +#define BIT_GET_PS_AID_2_8822B(x) \ + (((x) >> BIT_SHIFT_PS_AID_2_8822B) & BIT_MASK_PS_AID_2_8822B) +#define BIT_SET_PS_AID_2_8822B(x, v) \ + (BIT_CLEAR_PS_AID_2_8822B(x) | BIT_PS_AID_2_8822B(v)) /* 2 REG_BCN_PSR_RPT3_8822B (BEACON PARSER REPORT REGISTER3) */ #define BIT_SHIFT_DTIM_CNT3_8822B 24 #define BIT_MASK_DTIM_CNT3_8822B 0xff -#define BIT_DTIM_CNT3_8822B(x) (((x) & BIT_MASK_DTIM_CNT3_8822B) << BIT_SHIFT_DTIM_CNT3_8822B) -#define BIT_GET_DTIM_CNT3_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8822B) & BIT_MASK_DTIM_CNT3_8822B) - - +#define BIT_DTIM_CNT3_8822B(x) \ + (((x) & BIT_MASK_DTIM_CNT3_8822B) << BIT_SHIFT_DTIM_CNT3_8822B) +#define BITS_DTIM_CNT3_8822B \ + (BIT_MASK_DTIM_CNT3_8822B << BIT_SHIFT_DTIM_CNT3_8822B) +#define BIT_CLEAR_DTIM_CNT3_8822B(x) ((x) & (~BITS_DTIM_CNT3_8822B)) +#define BIT_GET_DTIM_CNT3_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT3_8822B) & BIT_MASK_DTIM_CNT3_8822B) +#define BIT_SET_DTIM_CNT3_8822B(x, v) \ + (BIT_CLEAR_DTIM_CNT3_8822B(x) | BIT_DTIM_CNT3_8822B(v)) #define BIT_SHIFT_DTIM_PERIOD3_8822B 16 #define BIT_MASK_DTIM_PERIOD3_8822B 0xff -#define BIT_DTIM_PERIOD3_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD3_8822B) << BIT_SHIFT_DTIM_PERIOD3_8822B) -#define BIT_GET_DTIM_PERIOD3_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8822B) & BIT_MASK_DTIM_PERIOD3_8822B) - +#define BIT_DTIM_PERIOD3_8822B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3_8822B) << BIT_SHIFT_DTIM_PERIOD3_8822B) +#define BITS_DTIM_PERIOD3_8822B \ + (BIT_MASK_DTIM_PERIOD3_8822B << BIT_SHIFT_DTIM_PERIOD3_8822B) +#define BIT_CLEAR_DTIM_PERIOD3_8822B(x) ((x) & (~BITS_DTIM_PERIOD3_8822B)) +#define BIT_GET_DTIM_PERIOD3_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3_8822B) & BIT_MASK_DTIM_PERIOD3_8822B) +#define BIT_SET_DTIM_PERIOD3_8822B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3_8822B(x) | BIT_DTIM_PERIOD3_8822B(v)) #define BIT_DTIM3_8822B BIT(15) #define BIT_TIM3_8822B BIT(14) #define BIT_SHIFT_PS_AID_3_8822B 0 #define BIT_MASK_PS_AID_3_8822B 0x7ff -#define BIT_PS_AID_3_8822B(x) (((x) & BIT_MASK_PS_AID_3_8822B) << BIT_SHIFT_PS_AID_3_8822B) -#define BIT_GET_PS_AID_3_8822B(x) (((x) >> BIT_SHIFT_PS_AID_3_8822B) & BIT_MASK_PS_AID_3_8822B) - - +#define BIT_PS_AID_3_8822B(x) \ + (((x) & BIT_MASK_PS_AID_3_8822B) << BIT_SHIFT_PS_AID_3_8822B) +#define BITS_PS_AID_3_8822B \ + (BIT_MASK_PS_AID_3_8822B << BIT_SHIFT_PS_AID_3_8822B) +#define BIT_CLEAR_PS_AID_3_8822B(x) ((x) & (~BITS_PS_AID_3_8822B)) +#define BIT_GET_PS_AID_3_8822B(x) \ + (((x) >> BIT_SHIFT_PS_AID_3_8822B) & BIT_MASK_PS_AID_3_8822B) +#define BIT_SET_PS_AID_3_8822B(x, v) \ + (BIT_CLEAR_PS_AID_3_8822B(x) | BIT_PS_AID_3_8822B(v)) /* 2 REG_BCN_PSR_RPT4_8822B (BEACON PARSER REPORT REGISTER4) */ #define BIT_SHIFT_DTIM_CNT4_8822B 24 #define BIT_MASK_DTIM_CNT4_8822B 0xff -#define BIT_DTIM_CNT4_8822B(x) (((x) & BIT_MASK_DTIM_CNT4_8822B) << BIT_SHIFT_DTIM_CNT4_8822B) -#define BIT_GET_DTIM_CNT4_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8822B) & BIT_MASK_DTIM_CNT4_8822B) - - +#define BIT_DTIM_CNT4_8822B(x) \ + (((x) & BIT_MASK_DTIM_CNT4_8822B) << BIT_SHIFT_DTIM_CNT4_8822B) +#define BITS_DTIM_CNT4_8822B \ + (BIT_MASK_DTIM_CNT4_8822B << BIT_SHIFT_DTIM_CNT4_8822B) +#define BIT_CLEAR_DTIM_CNT4_8822B(x) ((x) & (~BITS_DTIM_CNT4_8822B)) +#define BIT_GET_DTIM_CNT4_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT4_8822B) & BIT_MASK_DTIM_CNT4_8822B) +#define BIT_SET_DTIM_CNT4_8822B(x, v) \ + (BIT_CLEAR_DTIM_CNT4_8822B(x) | BIT_DTIM_CNT4_8822B(v)) #define BIT_SHIFT_DTIM_PERIOD4_8822B 16 #define BIT_MASK_DTIM_PERIOD4_8822B 0xff -#define BIT_DTIM_PERIOD4_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD4_8822B) << BIT_SHIFT_DTIM_PERIOD4_8822B) -#define BIT_GET_DTIM_PERIOD4_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8822B) & BIT_MASK_DTIM_PERIOD4_8822B) - +#define BIT_DTIM_PERIOD4_8822B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4_8822B) << BIT_SHIFT_DTIM_PERIOD4_8822B) +#define BITS_DTIM_PERIOD4_8822B \ + (BIT_MASK_DTIM_PERIOD4_8822B << BIT_SHIFT_DTIM_PERIOD4_8822B) +#define BIT_CLEAR_DTIM_PERIOD4_8822B(x) ((x) & (~BITS_DTIM_PERIOD4_8822B)) +#define BIT_GET_DTIM_PERIOD4_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4_8822B) & BIT_MASK_DTIM_PERIOD4_8822B) +#define BIT_SET_DTIM_PERIOD4_8822B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4_8822B(x) | BIT_DTIM_PERIOD4_8822B(v)) #define BIT_DTIM4_8822B BIT(15) #define BIT_TIM4_8822B BIT(14) #define BIT_SHIFT_PS_AID_4_8822B 0 #define BIT_MASK_PS_AID_4_8822B 0x7ff -#define BIT_PS_AID_4_8822B(x) (((x) & BIT_MASK_PS_AID_4_8822B) << BIT_SHIFT_PS_AID_4_8822B) -#define BIT_GET_PS_AID_4_8822B(x) (((x) >> BIT_SHIFT_PS_AID_4_8822B) & BIT_MASK_PS_AID_4_8822B) - - +#define BIT_PS_AID_4_8822B(x) \ + (((x) & BIT_MASK_PS_AID_4_8822B) << BIT_SHIFT_PS_AID_4_8822B) +#define BITS_PS_AID_4_8822B \ + (BIT_MASK_PS_AID_4_8822B << BIT_SHIFT_PS_AID_4_8822B) +#define BIT_CLEAR_PS_AID_4_8822B(x) ((x) & (~BITS_PS_AID_4_8822B)) +#define BIT_GET_PS_AID_4_8822B(x) \ + (((x) >> BIT_SHIFT_PS_AID_4_8822B) & BIT_MASK_PS_AID_4_8822B) +#define BIT_SET_PS_AID_4_8822B(x, v) \ + (BIT_CLEAR_PS_AID_4_8822B(x) | BIT_PS_AID_4_8822B(v)) /* 2 REG_A1_ADDR_MASK_8822B (A1 ADDR MASK REGISTER) */ #define BIT_SHIFT_A1_ADDR_MASK_8822B 0 #define BIT_MASK_A1_ADDR_MASK_8822B 0xffffffffL -#define BIT_A1_ADDR_MASK_8822B(x) (((x) & BIT_MASK_A1_ADDR_MASK_8822B) << BIT_SHIFT_A1_ADDR_MASK_8822B) -#define BIT_GET_A1_ADDR_MASK_8822B(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8822B) & BIT_MASK_A1_ADDR_MASK_8822B) - - +#define BIT_A1_ADDR_MASK_8822B(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK_8822B) << BIT_SHIFT_A1_ADDR_MASK_8822B) +#define BITS_A1_ADDR_MASK_8822B \ + (BIT_MASK_A1_ADDR_MASK_8822B << BIT_SHIFT_A1_ADDR_MASK_8822B) +#define BIT_CLEAR_A1_ADDR_MASK_8822B(x) ((x) & (~BITS_A1_ADDR_MASK_8822B)) +#define BIT_GET_A1_ADDR_MASK_8822B(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK_8822B) & BIT_MASK_A1_ADDR_MASK_8822B) +#define BIT_SET_A1_ADDR_MASK_8822B(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK_8822B(x) | BIT_A1_ADDR_MASK_8822B(v)) /* 2 REG_MACID2_8822B (MAC ID2 REGISTER) */ #define BIT_SHIFT_MACID2_8822B 0 #define BIT_MASK_MACID2_8822B 0xffffffffffffL -#define BIT_MACID2_8822B(x) (((x) & BIT_MASK_MACID2_8822B) << BIT_SHIFT_MACID2_8822B) -#define BIT_GET_MACID2_8822B(x) (((x) >> BIT_SHIFT_MACID2_8822B) & BIT_MASK_MACID2_8822B) - - +#define BIT_MACID2_8822B(x) \ + (((x) & BIT_MASK_MACID2_8822B) << BIT_SHIFT_MACID2_8822B) +#define BITS_MACID2_8822B (BIT_MASK_MACID2_8822B << BIT_SHIFT_MACID2_8822B) +#define BIT_CLEAR_MACID2_8822B(x) ((x) & (~BITS_MACID2_8822B)) +#define BIT_GET_MACID2_8822B(x) \ + (((x) >> BIT_SHIFT_MACID2_8822B) & BIT_MASK_MACID2_8822B) +#define BIT_SET_MACID2_8822B(x, v) \ + (BIT_CLEAR_MACID2_8822B(x) | BIT_MACID2_8822B(v)) /* 2 REG_BSSID2_8822B (BSSID2 REGISTER) */ #define BIT_SHIFT_BSSID2_8822B 0 #define BIT_MASK_BSSID2_8822B 0xffffffffffffL -#define BIT_BSSID2_8822B(x) (((x) & BIT_MASK_BSSID2_8822B) << BIT_SHIFT_BSSID2_8822B) -#define BIT_GET_BSSID2_8822B(x) (((x) >> BIT_SHIFT_BSSID2_8822B) & BIT_MASK_BSSID2_8822B) - - +#define BIT_BSSID2_8822B(x) \ + (((x) & BIT_MASK_BSSID2_8822B) << BIT_SHIFT_BSSID2_8822B) +#define BITS_BSSID2_8822B (BIT_MASK_BSSID2_8822B << BIT_SHIFT_BSSID2_8822B) +#define BIT_CLEAR_BSSID2_8822B(x) ((x) & (~BITS_BSSID2_8822B)) +#define BIT_GET_BSSID2_8822B(x) \ + (((x) >> BIT_SHIFT_BSSID2_8822B) & BIT_MASK_BSSID2_8822B) +#define BIT_SET_BSSID2_8822B(x, v) \ + (BIT_CLEAR_BSSID2_8822B(x) | BIT_BSSID2_8822B(v)) /* 2 REG_MACID3_8822B (MAC ID3 REGISTER) */ #define BIT_SHIFT_MACID3_8822B 0 #define BIT_MASK_MACID3_8822B 0xffffffffffffL -#define BIT_MACID3_8822B(x) (((x) & BIT_MASK_MACID3_8822B) << BIT_SHIFT_MACID3_8822B) -#define BIT_GET_MACID3_8822B(x) (((x) >> BIT_SHIFT_MACID3_8822B) & BIT_MASK_MACID3_8822B) - - +#define BIT_MACID3_8822B(x) \ + (((x) & BIT_MASK_MACID3_8822B) << BIT_SHIFT_MACID3_8822B) +#define BITS_MACID3_8822B (BIT_MASK_MACID3_8822B << BIT_SHIFT_MACID3_8822B) +#define BIT_CLEAR_MACID3_8822B(x) ((x) & (~BITS_MACID3_8822B)) +#define BIT_GET_MACID3_8822B(x) \ + (((x) >> BIT_SHIFT_MACID3_8822B) & BIT_MASK_MACID3_8822B) +#define BIT_SET_MACID3_8822B(x, v) \ + (BIT_CLEAR_MACID3_8822B(x) | BIT_MACID3_8822B(v)) /* 2 REG_BSSID3_8822B (BSSID3 REGISTER) */ #define BIT_SHIFT_BSSID3_8822B 0 #define BIT_MASK_BSSID3_8822B 0xffffffffffffL -#define BIT_BSSID3_8822B(x) (((x) & BIT_MASK_BSSID3_8822B) << BIT_SHIFT_BSSID3_8822B) -#define BIT_GET_BSSID3_8822B(x) (((x) >> BIT_SHIFT_BSSID3_8822B) & BIT_MASK_BSSID3_8822B) - - +#define BIT_BSSID3_8822B(x) \ + (((x) & BIT_MASK_BSSID3_8822B) << BIT_SHIFT_BSSID3_8822B) +#define BITS_BSSID3_8822B (BIT_MASK_BSSID3_8822B << BIT_SHIFT_BSSID3_8822B) +#define BIT_CLEAR_BSSID3_8822B(x) ((x) & (~BITS_BSSID3_8822B)) +#define BIT_GET_BSSID3_8822B(x) \ + (((x) >> BIT_SHIFT_BSSID3_8822B) & BIT_MASK_BSSID3_8822B) +#define BIT_SET_BSSID3_8822B(x, v) \ + (BIT_CLEAR_BSSID3_8822B(x) | BIT_BSSID3_8822B(v)) /* 2 REG_MACID4_8822B (MAC ID4 REGISTER) */ #define BIT_SHIFT_MACID4_8822B 0 #define BIT_MASK_MACID4_8822B 0xffffffffffffL -#define BIT_MACID4_8822B(x) (((x) & BIT_MASK_MACID4_8822B) << BIT_SHIFT_MACID4_8822B) -#define BIT_GET_MACID4_8822B(x) (((x) >> BIT_SHIFT_MACID4_8822B) & BIT_MASK_MACID4_8822B) - - +#define BIT_MACID4_8822B(x) \ + (((x) & BIT_MASK_MACID4_8822B) << BIT_SHIFT_MACID4_8822B) +#define BITS_MACID4_8822B (BIT_MASK_MACID4_8822B << BIT_SHIFT_MACID4_8822B) +#define BIT_CLEAR_MACID4_8822B(x) ((x) & (~BITS_MACID4_8822B)) +#define BIT_GET_MACID4_8822B(x) \ + (((x) >> BIT_SHIFT_MACID4_8822B) & BIT_MASK_MACID4_8822B) +#define BIT_SET_MACID4_8822B(x, v) \ + (BIT_CLEAR_MACID4_8822B(x) | BIT_MACID4_8822B(v)) /* 2 REG_BSSID4_8822B (BSSID4 REGISTER) */ #define BIT_SHIFT_BSSID4_8822B 0 #define BIT_MASK_BSSID4_8822B 0xffffffffffffL -#define BIT_BSSID4_8822B(x) (((x) & BIT_MASK_BSSID4_8822B) << BIT_SHIFT_BSSID4_8822B) -#define BIT_GET_BSSID4_8822B(x) (((x) >> BIT_SHIFT_BSSID4_8822B) & BIT_MASK_BSSID4_8822B) - - +#define BIT_BSSID4_8822B(x) \ + (((x) & BIT_MASK_BSSID4_8822B) << BIT_SHIFT_BSSID4_8822B) +#define BITS_BSSID4_8822B (BIT_MASK_BSSID4_8822B << BIT_SHIFT_BSSID4_8822B) +#define BIT_CLEAR_BSSID4_8822B(x) ((x) & (~BITS_BSSID4_8822B)) +#define BIT_GET_BSSID4_8822B(x) \ + (((x) >> BIT_SHIFT_BSSID4_8822B) & BIT_MASK_BSSID4_8822B) +#define BIT_SET_BSSID4_8822B(x, v) \ + (BIT_CLEAR_BSSID4_8822B(x) | BIT_BSSID4_8822B(v)) /* 2 REG_NOA_REPORT_8822B */ @@ -9666,16 +15386,37 @@ #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B 4 #define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B 0x3 -#define BIT_WMAC_TXMU_ACKPOLICY_8822B(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) -#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822B(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) - - +#define BIT_WMAC_TXMU_ACKPOLICY_8822B(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) +#define BITS_WMAC_TXMU_ACKPOLICY_8822B \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822B(x) \ + ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8822B)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) & \ + BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) +#define BIT_SET_WMAC_TXMU_ACKPOLICY_8822B(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822B(x) | \ + BIT_WMAC_TXMU_ACKPOLICY_8822B(v)) #define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B 1 #define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B 0x7 -#define BIT_WMAC_MU_BFEE_PORT_SEL_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) -#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) - +#define BIT_WMAC_MU_BFEE_PORT_SEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) +#define BITS_WMAC_MU_BFEE_PORT_SEL_8822B \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8822B)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822B(x) | \ + BIT_WMAC_MU_BFEE_PORT_SEL_8822B(v)) #define BIT_WMAC_MU_BFEE_DIS_8822B BIT(0) @@ -9683,10 +15424,20 @@ #define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B 0 #define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B 0xff -#define BIT_WMAC_PAUSE_BB_CLR_TH_8822B(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) -#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822B(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) - - +#define BIT_WMAC_PAUSE_BB_CLR_TH_8822B(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) +#define BITS_WMAC_PAUSE_BB_CLR_TH_8822B \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822B(x) \ + ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8822B)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8822B(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822B(x) | \ + BIT_WMAC_PAUSE_BB_CLR_TH_8822B(v)) /* 2 REG_WMAC_MU_ARB_8822B */ #define BIT_WMAC_ARB_HW_ADAPT_EN_8822B BIT(7) @@ -9694,26 +15445,51 @@ #define BIT_SHIFT_WMAC_ARB_SW_STATE_8822B 0 #define BIT_MASK_WMAC_ARB_SW_STATE_8822B 0x3f -#define BIT_WMAC_ARB_SW_STATE_8822B(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8822B) << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) -#define BIT_GET_WMAC_ARB_SW_STATE_8822B(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) & BIT_MASK_WMAC_ARB_SW_STATE_8822B) - - +#define BIT_WMAC_ARB_SW_STATE_8822B(x) \ + (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8822B) \ + << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) +#define BITS_WMAC_ARB_SW_STATE_8822B \ + (BIT_MASK_WMAC_ARB_SW_STATE_8822B << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) +#define BIT_CLEAR_WMAC_ARB_SW_STATE_8822B(x) \ + ((x) & (~BITS_WMAC_ARB_SW_STATE_8822B)) +#define BIT_GET_WMAC_ARB_SW_STATE_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) & \ + BIT_MASK_WMAC_ARB_SW_STATE_8822B) +#define BIT_SET_WMAC_ARB_SW_STATE_8822B(x, v) \ + (BIT_CLEAR_WMAC_ARB_SW_STATE_8822B(x) | BIT_WMAC_ARB_SW_STATE_8822B(v)) /* 2 REG_WMAC_MU_OPTION_8822B */ #define BIT_SHIFT_WMAC_MU_DBGSEL_8822B 5 #define BIT_MASK_WMAC_MU_DBGSEL_8822B 0x3 -#define BIT_WMAC_MU_DBGSEL_8822B(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8822B) << BIT_SHIFT_WMAC_MU_DBGSEL_8822B) -#define BIT_GET_WMAC_MU_DBGSEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8822B) & BIT_MASK_WMAC_MU_DBGSEL_8822B) - - +#define BIT_WMAC_MU_DBGSEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_DBGSEL_8822B) \ + << BIT_SHIFT_WMAC_MU_DBGSEL_8822B) +#define BITS_WMAC_MU_DBGSEL_8822B \ + (BIT_MASK_WMAC_MU_DBGSEL_8822B << BIT_SHIFT_WMAC_MU_DBGSEL_8822B) +#define BIT_CLEAR_WMAC_MU_DBGSEL_8822B(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8822B)) +#define BIT_GET_WMAC_MU_DBGSEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8822B) & \ + BIT_MASK_WMAC_MU_DBGSEL_8822B) +#define BIT_SET_WMAC_MU_DBGSEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_DBGSEL_8822B(x) | BIT_WMAC_MU_DBGSEL_8822B(v)) #define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B 0 #define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B 0x1f -#define BIT_WMAC_MU_CPRD_TIMEOUT_8822B(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) -#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) - - +#define BIT_WMAC_MU_CPRD_TIMEOUT_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) +#define BITS_WMAC_MU_CPRD_TIMEOUT_8822B \ + (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B \ + << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) +#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8822B(x) \ + ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8822B)) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) & \ + BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) +#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8822B(x) | \ + BIT_WMAC_MU_CPRD_TIMEOUT_8822B(v)) /* 2 REG_WMAC_MU_BF_CTL_8822B */ #define BIT_WMAC_INVLD_BFPRT_CHK_8822B BIT(15) @@ -9721,33 +15497,66 @@ #define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B 12 #define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B 0x3 -#define BIT_WMAC_MU_BFRPTSEG_SEL_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) -#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) - - +#define BIT_WMAC_MU_BFRPTSEG_SEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) +#define BITS_WMAC_MU_BFRPTSEG_SEL_8822B \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822B)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x) | \ + BIT_WMAC_MU_BFRPTSEG_SEL_8822B(v)) #define BIT_SHIFT_WMAC_MU_BF_MYAID_8822B 0 #define BIT_MASK_WMAC_MU_BF_MYAID_8822B 0xfff -#define BIT_WMAC_MU_BF_MYAID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822B) << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) -#define BIT_GET_WMAC_MU_BF_MYAID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) & BIT_MASK_WMAC_MU_BF_MYAID_8822B) - - +#define BIT_WMAC_MU_BF_MYAID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822B) \ + << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) +#define BITS_WMAC_MU_BF_MYAID_8822B \ + (BIT_MASK_WMAC_MU_BF_MYAID_8822B << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BF_MYAID_8822B)) +#define BIT_GET_WMAC_MU_BF_MYAID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) & \ + BIT_MASK_WMAC_MU_BF_MYAID_8822B) +#define BIT_SET_WMAC_MU_BF_MYAID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x) | BIT_WMAC_MU_BF_MYAID_8822B(v)) /* 2 REG_WMAC_MU_BFRPT_PARA_8822B */ #define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B 12 #define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B 0x7 -#define BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(x) (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) -#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL_8822B(x) (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) - - +#define BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(x) \ + (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) \ + << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) +#define BITS_BIT_BFRPT_PARA_USERID_SEL_8822B \ + (BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B \ + << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) +#define BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL_8822B(x) \ + ((x) & (~BITS_BIT_BFRPT_PARA_USERID_SEL_8822B)) +#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) & \ + BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) +#define BIT_SET_BIT_BFRPT_PARA_USERID_SEL_8822B(x, v) \ + (BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL_8822B(x) | \ + BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(v)) #define BIT_SHIFT_BFRPT_PARA_8822B 0 #define BIT_MASK_BFRPT_PARA_8822B 0xfff -#define BIT_BFRPT_PARA_8822B(x) (((x) & BIT_MASK_BFRPT_PARA_8822B) << BIT_SHIFT_BFRPT_PARA_8822B) -#define BIT_GET_BFRPT_PARA_8822B(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8822B) & BIT_MASK_BFRPT_PARA_8822B) - - +#define BIT_BFRPT_PARA_8822B(x) \ + (((x) & BIT_MASK_BFRPT_PARA_8822B) << BIT_SHIFT_BFRPT_PARA_8822B) +#define BITS_BFRPT_PARA_8822B \ + (BIT_MASK_BFRPT_PARA_8822B << BIT_SHIFT_BFRPT_PARA_8822B) +#define BIT_CLEAR_BFRPT_PARA_8822B(x) ((x) & (~BITS_BFRPT_PARA_8822B)) +#define BIT_GET_BFRPT_PARA_8822B(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_8822B) & BIT_MASK_BFRPT_PARA_8822B) +#define BIT_SET_BFRPT_PARA_8822B(x, v) \ + (BIT_CLEAR_BFRPT_PARA_8822B(x) | BIT_BFRPT_PARA_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B */ #define BIT_STATUS_BFEE2_8822B BIT(10) @@ -9755,21 +15564,37 @@ #define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B 0 #define BIT_MASK_WMAC_MU_BFEE2_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE2_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE2_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B) - - +#define BIT_WMAC_MU_BFEE2_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) +#define BITS_WMAC_MU_BFEE2_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE2_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE2_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE2_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE2_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE2_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID_8822B(x) | BIT_WMAC_MU_BFEE2_AID_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B */ #define BIT_STATUS_BFEE3_8822B BIT(10) #define BIT_WMAC_MU_BFEE3_EN_8822B BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B 0 -#define BIT_MASK_WMAC_MU_BFEE3_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE3_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE3_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B) - - +#define BIT_MASK_WMAC_MU_BFEE3_AID_8822B 0x1ff +#define BIT_WMAC_MU_BFEE3_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) +#define BITS_WMAC_MU_BFEE3_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE3_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE3_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE3_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE3_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE3_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID_8822B(x) | BIT_WMAC_MU_BFEE3_AID_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B */ #define BIT_STATUS_BFEE4_8822B BIT(10) @@ -9777,10 +15602,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B 0 #define BIT_MASK_WMAC_MU_BFEE4_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE4_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE4_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B) - - +#define BIT_WMAC_MU_BFEE4_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) +#define BITS_WMAC_MU_BFEE4_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE4_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE4_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE4_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE4_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE4_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID_8822B(x) | BIT_WMAC_MU_BFEE4_AID_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B */ #define BIT_STATUS_BFEE5_8822B BIT(10) @@ -9788,10 +15621,18 @@ #define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B 0 #define BIT_MASK_WMAC_MU_BFEE5_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE5_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE5_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B) - - +#define BIT_WMAC_MU_BFEE5_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) +#define BITS_WMAC_MU_BFEE5_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE5_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE5_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE5_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE5_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE5_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID_8822B(x) | BIT_WMAC_MU_BFEE5_AID_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B */ #define BIT_STATUS_BFEE6_8822B BIT(10) @@ -9799,124 +15640,204 @@ #define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B 0 #define BIT_MASK_WMAC_MU_BFEE6_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE6_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE6_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B) - - +#define BIT_WMAC_MU_BFEE6_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) +#define BITS_WMAC_MU_BFEE6_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE6_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE6_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE6_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE6_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE6_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID_8822B(x) | BIT_WMAC_MU_BFEE6_AID_8822B(v)) /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B */ -#define BIT_BIT_STATUS_BFEE4_8822B BIT(10) +#define BIT_STATUS_BFEE7_8822B BIT(10) #define BIT_WMAC_MU_BFEE7_EN_8822B BIT(9) #define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B 0 #define BIT_MASK_WMAC_MU_BFEE7_AID_8822B 0x1ff -#define BIT_WMAC_MU_BFEE7_AID_8822B(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) -#define BIT_GET_WMAC_MU_BFEE7_AID_8822B(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B) - - +#define BIT_WMAC_MU_BFEE7_AID_8822B(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B) \ + << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) +#define BITS_WMAC_MU_BFEE7_AID_8822B \ + (BIT_MASK_WMAC_MU_BFEE7_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8822B(x) \ + ((x) & (~BITS_WMAC_MU_BFEE7_AID_8822B)) +#define BIT_GET_WMAC_MU_BFEE7_AID_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) & \ + BIT_MASK_WMAC_MU_BFEE7_AID_8822B) +#define BIT_SET_WMAC_MU_BFEE7_AID_8822B(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID_8822B(x) | BIT_WMAC_MU_BFEE7_AID_8822B(v)) /* 2 REG_NOT_VALID_8822B */ #define BIT_RST_ALL_COUNTER_8822B BIT(31) #define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B 16 #define BIT_MASK_ABORT_RX_VBON_COUNTER_8822B 0xff -#define BIT_ABORT_RX_VBON_COUNTER_8822B(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) -#define BIT_GET_ABORT_RX_VBON_COUNTER_8822B(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) - - +#define BIT_ABORT_RX_VBON_COUNTER_8822B(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) +#define BITS_ABORT_RX_VBON_COUNTER_8822B \ + (BIT_MASK_ABORT_RX_VBON_COUNTER_8822B \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822B(x) \ + ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8822B)) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) +#define BIT_SET_ABORT_RX_VBON_COUNTER_8822B(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822B(x) | \ + BIT_ABORT_RX_VBON_COUNTER_8822B(v)) #define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B 8 #define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B 0xff -#define BIT_ABORT_RX_RDRDY_COUNTER_8822B(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) -#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822B(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) - - +#define BIT_ABORT_RX_RDRDY_COUNTER_8822B(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) +#define BITS_ABORT_RX_RDRDY_COUNTER_8822B \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822B(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8822B)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8822B(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822B(x) | \ + BIT_ABORT_RX_RDRDY_COUNTER_8822B(v)) #define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B 0 #define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B 0xff -#define BIT_VBON_EARLY_FALLING_COUNTER_8822B(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) -#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822B(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) - - +#define BIT_VBON_EARLY_FALLING_COUNTER_8822B(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) +#define BITS_VBON_EARLY_FALLING_COUNTER_8822B \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822B(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8822B)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822B(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8822B(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822B(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER_8822B(v)) /* 2 REG_NOT_VALID_8822B */ #define BIT_WMAC_PLCP_TRX_SEL_8822B BIT(31) #define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B 28 #define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B 0x7 -#define BIT_WMAC_PLCP_RDSIG_SEL_8822B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) -#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) - - +#define BIT_WMAC_PLCP_RDSIG_SEL_8822B(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) +#define BITS_WMAC_PLCP_RDSIG_SEL_8822B \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822B(x) \ + ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8822B)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) & \ + BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8822B(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822B(x) | \ + BIT_WMAC_PLCP_RDSIG_SEL_8822B(v)) #define BIT_SHIFT_WMAC_RATE_IDX_8822B 24 #define BIT_MASK_WMAC_RATE_IDX_8822B 0xf -#define BIT_WMAC_RATE_IDX_8822B(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8822B) << BIT_SHIFT_WMAC_RATE_IDX_8822B) -#define BIT_GET_WMAC_RATE_IDX_8822B(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822B) & BIT_MASK_WMAC_RATE_IDX_8822B) - - +#define BIT_WMAC_RATE_IDX_8822B(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX_8822B) << BIT_SHIFT_WMAC_RATE_IDX_8822B) +#define BITS_WMAC_RATE_IDX_8822B \ + (BIT_MASK_WMAC_RATE_IDX_8822B << BIT_SHIFT_WMAC_RATE_IDX_8822B) +#define BIT_CLEAR_WMAC_RATE_IDX_8822B(x) ((x) & (~BITS_WMAC_RATE_IDX_8822B)) +#define BIT_GET_WMAC_RATE_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822B) & BIT_MASK_WMAC_RATE_IDX_8822B) +#define BIT_SET_WMAC_RATE_IDX_8822B(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX_8822B(x) | BIT_WMAC_RATE_IDX_8822B(v)) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8822B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) -#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) - - +#define BIT_WMAC_PLCP_RDSIG_8822B(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) +#define BITS_WMAC_PLCP_RDSIG_8822B \ + (BIT_MASK_WMAC_PLCP_RDSIG_8822B << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822B)) +#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8822B) +#define BIT_SET_WMAC_PLCP_RDSIG_8822B(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) | BIT_WMAC_PLCP_RDSIG_8822B(v)) /* 2 REG_NOT_VALID_8822B */ #define BIT_WMAC_MUTX_IDX_8822B BIT(24) #define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0 #define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff -#define BIT_WMAC_PLCP_RDSIG_8822B(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) -#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) - - +#define BIT_WMAC_PLCP_RDSIG_8822B(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) +#define BITS_WMAC_PLCP_RDSIG_8822B \ + (BIT_MASK_WMAC_PLCP_RDSIG_8822B << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822B)) +#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8822B) +#define BIT_SET_WMAC_PLCP_RDSIG_8822B(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) | BIT_WMAC_PLCP_RDSIG_8822B(v)) /* 2 REG_TRANSMIT_ADDRSS_0_8822B (TA0 REGISTER) */ #define BIT_SHIFT_TA0_8822B 0 #define BIT_MASK_TA0_8822B 0xffffffffffffL #define BIT_TA0_8822B(x) (((x) & BIT_MASK_TA0_8822B) << BIT_SHIFT_TA0_8822B) +#define BITS_TA0_8822B (BIT_MASK_TA0_8822B << BIT_SHIFT_TA0_8822B) +#define BIT_CLEAR_TA0_8822B(x) ((x) & (~BITS_TA0_8822B)) #define BIT_GET_TA0_8822B(x) (((x) >> BIT_SHIFT_TA0_8822B) & BIT_MASK_TA0_8822B) - - +#define BIT_SET_TA0_8822B(x, v) (BIT_CLEAR_TA0_8822B(x) | BIT_TA0_8822B(v)) /* 2 REG_TRANSMIT_ADDRSS_1_8822B (TA1 REGISTER) */ #define BIT_SHIFT_TA1_8822B 0 #define BIT_MASK_TA1_8822B 0xffffffffffffL #define BIT_TA1_8822B(x) (((x) & BIT_MASK_TA1_8822B) << BIT_SHIFT_TA1_8822B) +#define BITS_TA1_8822B (BIT_MASK_TA1_8822B << BIT_SHIFT_TA1_8822B) +#define BIT_CLEAR_TA1_8822B(x) ((x) & (~BITS_TA1_8822B)) #define BIT_GET_TA1_8822B(x) (((x) >> BIT_SHIFT_TA1_8822B) & BIT_MASK_TA1_8822B) - - +#define BIT_SET_TA1_8822B(x, v) (BIT_CLEAR_TA1_8822B(x) | BIT_TA1_8822B(v)) /* 2 REG_TRANSMIT_ADDRSS_2_8822B (TA2 REGISTER) */ #define BIT_SHIFT_TA2_8822B 0 #define BIT_MASK_TA2_8822B 0xffffffffffffL #define BIT_TA2_8822B(x) (((x) & BIT_MASK_TA2_8822B) << BIT_SHIFT_TA2_8822B) +#define BITS_TA2_8822B (BIT_MASK_TA2_8822B << BIT_SHIFT_TA2_8822B) +#define BIT_CLEAR_TA2_8822B(x) ((x) & (~BITS_TA2_8822B)) #define BIT_GET_TA2_8822B(x) (((x) >> BIT_SHIFT_TA2_8822B) & BIT_MASK_TA2_8822B) - - +#define BIT_SET_TA2_8822B(x, v) (BIT_CLEAR_TA2_8822B(x) | BIT_TA2_8822B(v)) /* 2 REG_TRANSMIT_ADDRSS_3_8822B (TA3 REGISTER) */ #define BIT_SHIFT_TA3_8822B 0 #define BIT_MASK_TA3_8822B 0xffffffffffffL #define BIT_TA3_8822B(x) (((x) & BIT_MASK_TA3_8822B) << BIT_SHIFT_TA3_8822B) +#define BITS_TA3_8822B (BIT_MASK_TA3_8822B << BIT_SHIFT_TA3_8822B) +#define BIT_CLEAR_TA3_8822B(x) ((x) & (~BITS_TA3_8822B)) #define BIT_GET_TA3_8822B(x) (((x) >> BIT_SHIFT_TA3_8822B) & BIT_MASK_TA3_8822B) - - +#define BIT_SET_TA3_8822B(x, v) (BIT_CLEAR_TA3_8822B(x) | BIT_TA3_8822B(v)) /* 2 REG_TRANSMIT_ADDRSS_4_8822B (TA4 REGISTER) */ #define BIT_SHIFT_TA4_8822B 0 #define BIT_MASK_TA4_8822B 0xffffffffffffL #define BIT_TA4_8822B(x) (((x) & BIT_MASK_TA4_8822B) << BIT_SHIFT_TA4_8822B) +#define BITS_TA4_8822B (BIT_MASK_TA4_8822B << BIT_SHIFT_TA4_8822B) +#define BIT_CLEAR_TA4_8822B(x) ((x) & (~BITS_TA4_8822B)) #define BIT_GET_TA4_8822B(x) (((x) >> BIT_SHIFT_TA4_8822B) & BIT_MASK_TA4_8822B) - - +#define BIT_SET_TA4_8822B(x, v) (BIT_CLEAR_TA4_8822B(x) | BIT_TA4_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -9924,44 +15845,68 @@ #define BIT_SHIFT_MACID1_8822B 0 #define BIT_MASK_MACID1_8822B 0xffffffffffffL -#define BIT_MACID1_8822B(x) (((x) & BIT_MASK_MACID1_8822B) << BIT_SHIFT_MACID1_8822B) -#define BIT_GET_MACID1_8822B(x) (((x) >> BIT_SHIFT_MACID1_8822B) & BIT_MASK_MACID1_8822B) - - +#define BIT_MACID1_8822B(x) \ + (((x) & BIT_MASK_MACID1_8822B) << BIT_SHIFT_MACID1_8822B) +#define BITS_MACID1_8822B (BIT_MASK_MACID1_8822B << BIT_SHIFT_MACID1_8822B) +#define BIT_CLEAR_MACID1_8822B(x) ((x) & (~BITS_MACID1_8822B)) +#define BIT_GET_MACID1_8822B(x) \ + (((x) >> BIT_SHIFT_MACID1_8822B) & BIT_MASK_MACID1_8822B) +#define BIT_SET_MACID1_8822B(x, v) \ + (BIT_CLEAR_MACID1_8822B(x) | BIT_MACID1_8822B(v)) /* 2 REG_BSSID1_8822B */ #define BIT_SHIFT_BSSID1_8822B 0 #define BIT_MASK_BSSID1_8822B 0xffffffffffffL -#define BIT_BSSID1_8822B(x) (((x) & BIT_MASK_BSSID1_8822B) << BIT_SHIFT_BSSID1_8822B) -#define BIT_GET_BSSID1_8822B(x) (((x) >> BIT_SHIFT_BSSID1_8822B) & BIT_MASK_BSSID1_8822B) - - +#define BIT_BSSID1_8822B(x) \ + (((x) & BIT_MASK_BSSID1_8822B) << BIT_SHIFT_BSSID1_8822B) +#define BITS_BSSID1_8822B (BIT_MASK_BSSID1_8822B << BIT_SHIFT_BSSID1_8822B) +#define BIT_CLEAR_BSSID1_8822B(x) ((x) & (~BITS_BSSID1_8822B)) +#define BIT_GET_BSSID1_8822B(x) \ + (((x) >> BIT_SHIFT_BSSID1_8822B) & BIT_MASK_BSSID1_8822B) +#define BIT_SET_BSSID1_8822B(x, v) \ + (BIT_CLEAR_BSSID1_8822B(x) | BIT_BSSID1_8822B(v)) /* 2 REG_BCN_PSR_RPT1_8822B */ #define BIT_SHIFT_DTIM_CNT1_8822B 24 #define BIT_MASK_DTIM_CNT1_8822B 0xff -#define BIT_DTIM_CNT1_8822B(x) (((x) & BIT_MASK_DTIM_CNT1_8822B) << BIT_SHIFT_DTIM_CNT1_8822B) -#define BIT_GET_DTIM_CNT1_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8822B) & BIT_MASK_DTIM_CNT1_8822B) - - +#define BIT_DTIM_CNT1_8822B(x) \ + (((x) & BIT_MASK_DTIM_CNT1_8822B) << BIT_SHIFT_DTIM_CNT1_8822B) +#define BITS_DTIM_CNT1_8822B \ + (BIT_MASK_DTIM_CNT1_8822B << BIT_SHIFT_DTIM_CNT1_8822B) +#define BIT_CLEAR_DTIM_CNT1_8822B(x) ((x) & (~BITS_DTIM_CNT1_8822B)) +#define BIT_GET_DTIM_CNT1_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT1_8822B) & BIT_MASK_DTIM_CNT1_8822B) +#define BIT_SET_DTIM_CNT1_8822B(x, v) \ + (BIT_CLEAR_DTIM_CNT1_8822B(x) | BIT_DTIM_CNT1_8822B(v)) #define BIT_SHIFT_DTIM_PERIOD1_8822B 16 #define BIT_MASK_DTIM_PERIOD1_8822B 0xff -#define BIT_DTIM_PERIOD1_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD1_8822B) << BIT_SHIFT_DTIM_PERIOD1_8822B) -#define BIT_GET_DTIM_PERIOD1_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8822B) & BIT_MASK_DTIM_PERIOD1_8822B) - +#define BIT_DTIM_PERIOD1_8822B(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1_8822B) << BIT_SHIFT_DTIM_PERIOD1_8822B) +#define BITS_DTIM_PERIOD1_8822B \ + (BIT_MASK_DTIM_PERIOD1_8822B << BIT_SHIFT_DTIM_PERIOD1_8822B) +#define BIT_CLEAR_DTIM_PERIOD1_8822B(x) ((x) & (~BITS_DTIM_PERIOD1_8822B)) +#define BIT_GET_DTIM_PERIOD1_8822B(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1_8822B) & BIT_MASK_DTIM_PERIOD1_8822B) +#define BIT_SET_DTIM_PERIOD1_8822B(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1_8822B(x) | BIT_DTIM_PERIOD1_8822B(v)) #define BIT_DTIM1_8822B BIT(15) #define BIT_TIM1_8822B BIT(14) #define BIT_SHIFT_PS_AID_1_8822B 0 #define BIT_MASK_PS_AID_1_8822B 0x7ff -#define BIT_PS_AID_1_8822B(x) (((x) & BIT_MASK_PS_AID_1_8822B) << BIT_SHIFT_PS_AID_1_8822B) -#define BIT_GET_PS_AID_1_8822B(x) (((x) >> BIT_SHIFT_PS_AID_1_8822B) & BIT_MASK_PS_AID_1_8822B) - - +#define BIT_PS_AID_1_8822B(x) \ + (((x) & BIT_MASK_PS_AID_1_8822B) << BIT_SHIFT_PS_AID_1_8822B) +#define BITS_PS_AID_1_8822B \ + (BIT_MASK_PS_AID_1_8822B << BIT_SHIFT_PS_AID_1_8822B) +#define BIT_CLEAR_PS_AID_1_8822B(x) ((x) & (~BITS_PS_AID_1_8822B)) +#define BIT_GET_PS_AID_1_8822B(x) \ + (((x) >> BIT_SHIFT_PS_AID_1_8822B) & BIT_MASK_PS_AID_1_8822B) +#define BIT_SET_PS_AID_1_8822B(x, v) \ + (BIT_CLEAR_PS_AID_1_8822B(x) | BIT_PS_AID_1_8822B(v)) /* 2 REG_ASSOCIATED_BFMEE_SEL_8822B */ #define BIT_TXUSER_ID1_8822B BIT(25) @@ -9969,39 +15914,78 @@ #define BIT_SHIFT_AID1_8822B 16 #define BIT_MASK_AID1_8822B 0x1ff #define BIT_AID1_8822B(x) (((x) & BIT_MASK_AID1_8822B) << BIT_SHIFT_AID1_8822B) -#define BIT_GET_AID1_8822B(x) (((x) >> BIT_SHIFT_AID1_8822B) & BIT_MASK_AID1_8822B) - +#define BITS_AID1_8822B (BIT_MASK_AID1_8822B << BIT_SHIFT_AID1_8822B) +#define BIT_CLEAR_AID1_8822B(x) ((x) & (~BITS_AID1_8822B)) +#define BIT_GET_AID1_8822B(x) \ + (((x) >> BIT_SHIFT_AID1_8822B) & BIT_MASK_AID1_8822B) +#define BIT_SET_AID1_8822B(x, v) (BIT_CLEAR_AID1_8822B(x) | BIT_AID1_8822B(v)) #define BIT_TXUSER_ID0_8822B BIT(9) #define BIT_SHIFT_AID0_8822B 0 #define BIT_MASK_AID0_8822B 0x1ff #define BIT_AID0_8822B(x) (((x) & BIT_MASK_AID0_8822B) << BIT_SHIFT_AID0_8822B) -#define BIT_GET_AID0_8822B(x) (((x) >> BIT_SHIFT_AID0_8822B) & BIT_MASK_AID0_8822B) - - +#define BITS_AID0_8822B (BIT_MASK_AID0_8822B << BIT_SHIFT_AID0_8822B) +#define BIT_CLEAR_AID0_8822B(x) ((x) & (~BITS_AID0_8822B)) +#define BIT_GET_AID0_8822B(x) \ + (((x) >> BIT_SHIFT_AID0_8822B) & BIT_MASK_AID0_8822B) +#define BIT_SET_AID0_8822B(x, v) (BIT_CLEAR_AID0_8822B(x) | BIT_AID0_8822B(v)) /* 2 REG_SND_PTCL_CTRL_8822B */ #define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B 24 #define BIT_MASK_NDP_RX_STANDBY_TIMER_8822B 0xff -#define BIT_NDP_RX_STANDBY_TIMER_8822B(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) -#define BIT_GET_NDP_RX_STANDBY_TIMER_8822B(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) - - - -#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B 16 -#define BIT_MASK_CSI_RPT_OFFSET_HT_8822B 0xff -#define BIT_CSI_RPT_OFFSET_HT_8822B(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8822B) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B) -#define BIT_GET_CSI_RPT_OFFSET_HT_8822B(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B) & BIT_MASK_CSI_RPT_OFFSET_HT_8822B) - - - -#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B 8 -#define BIT_MASK_R_WMAC_VHT_CATEGORY_8822B 0xff -#define BIT_R_WMAC_VHT_CATEGORY_8822B(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8822B) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B) -#define BIT_GET_R_WMAC_VHT_CATEGORY_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B) & BIT_MASK_R_WMAC_VHT_CATEGORY_8822B) - +#define BIT_NDP_RX_STANDBY_TIMER_8822B(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) +#define BITS_NDP_RX_STANDBY_TIMER_8822B \ + (BIT_MASK_NDP_RX_STANDBY_TIMER_8822B \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822B(x) \ + ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8822B)) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) +#define BIT_SET_NDP_RX_STANDBY_TIMER_8822B(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822B(x) | \ + BIT_NDP_RX_STANDBY_TIMER_8822B(v)) + +#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B 16 +#define BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B 0x3f +#define BIT_CSI_RPT_OFFSET_HT_V1_8822B(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B) +#define BITS_CSI_RPT_OFFSET_HT_V1_8822B \ + (BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822B(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1_8822B)) +#define BIT_GET_CSI_RPT_OFFSET_HT_V1_8822B(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B) +#define BIT_SET_CSI_RPT_OFFSET_HT_V1_8822B(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822B(x) | \ + BIT_CSI_RPT_OFFSET_HT_V1_8822B(v)) + +#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8822B BIT(15) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8822B BIT(14) + +#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B 8 +#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B 0x3f +#define BIT_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) \ + (((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B) \ + << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B) +#define BITS_R_CSI_RPT_OFFSET_VHT_V1_8822B \ + (BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B \ + << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B) +#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) \ + ((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1_8822B)) +#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) \ + (((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B) & \ + BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B) +#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1_8822B(x, v) \ + (BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) | \ + BIT_R_CSI_RPT_OFFSET_VHT_V1_8822B(v)) #define BIT_R_WMAC_USE_NSTS_8822B BIT(7) #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822B BIT(6) @@ -10021,24 +16005,54 @@ #define BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B 6 #define BIT_MASK_R_WMAC_NSARP_MODEN_8822B 0x3 -#define BIT_R_WMAC_NSARP_MODEN_8822B(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) -#define BIT_GET_R_WMAC_NSARP_MODEN_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B) - - +#define BIT_R_WMAC_NSARP_MODEN_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B) \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) +#define BITS_R_WMAC_NSARP_MODEN_8822B \ + (BIT_MASK_R_WMAC_NSARP_MODEN_8822B \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8822B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_MODEN_8822B)) +#define BIT_GET_R_WMAC_NSARP_MODEN_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) & \ + BIT_MASK_R_WMAC_NSARP_MODEN_8822B) +#define BIT_SET_R_WMAC_NSARP_MODEN_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN_8822B(x) | \ + BIT_R_WMAC_NSARP_MODEN_8822B(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B 4 #define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B 0x3 -#define BIT_R_WMAC_NSARP_RSPFTP_8822B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) -#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) - - +#define BIT_R_WMAC_NSARP_RSPFTP_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) +#define BITS_R_WMAC_NSARP_RSPFTP_8822B \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8822B)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) & \ + BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) +#define BIT_SET_R_WMAC_NSARP_RSPFTP_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822B(x) | \ + BIT_R_WMAC_NSARP_RSPFTP_8822B(v)) #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B 0 #define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B 0xf -#define BIT_R_WMAC_NSARP_RSPSEC_8822B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) -#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) - - +#define BIT_R_WMAC_NSARP_RSPSEC_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) +#define BITS_R_WMAC_NSARP_RSPSEC_8822B \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822B(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8822B)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) & \ + BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) +#define BIT_SET_R_WMAC_NSARP_RSPSEC_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822B(x) | \ + BIT_R_WMAC_NSARP_RSPSEC_8822B(v)) /* 2 REG_NS_ARP_INFO_8822B */ #define BIT_REQ_IS_MCNS_8822B BIT(23) @@ -10049,51 +16063,101 @@ #define BIT_SHIFT_EXPRSP_SECTYPE_8822B 16 #define BIT_MASK_EXPRSP_SECTYPE_8822B 0x7 -#define BIT_EXPRSP_SECTYPE_8822B(x) (((x) & BIT_MASK_EXPRSP_SECTYPE_8822B) << BIT_SHIFT_EXPRSP_SECTYPE_8822B) -#define BIT_GET_EXPRSP_SECTYPE_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822B) & BIT_MASK_EXPRSP_SECTYPE_8822B) - - +#define BIT_EXPRSP_SECTYPE_8822B(x) \ + (((x) & BIT_MASK_EXPRSP_SECTYPE_8822B) \ + << BIT_SHIFT_EXPRSP_SECTYPE_8822B) +#define BITS_EXPRSP_SECTYPE_8822B \ + (BIT_MASK_EXPRSP_SECTYPE_8822B << BIT_SHIFT_EXPRSP_SECTYPE_8822B) +#define BIT_CLEAR_EXPRSP_SECTYPE_8822B(x) ((x) & (~BITS_EXPRSP_SECTYPE_8822B)) +#define BIT_GET_EXPRSP_SECTYPE_8822B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822B) & \ + BIT_MASK_EXPRSP_SECTYPE_8822B) +#define BIT_SET_EXPRSP_SECTYPE_8822B(x, v) \ + (BIT_CLEAR_EXPRSP_SECTYPE_8822B(x) | BIT_EXPRSP_SECTYPE_8822B(v)) #define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B 8 #define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B 0xff -#define BIT_EXPRSP_CHKSM_7_TO_0_8822B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) -#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) - - +#define BIT_EXPRSP_CHKSM_7_TO_0_8822B(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) +#define BITS_EXPRSP_CHKSM_7_TO_0_8822B \ + (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) +#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822B(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8822B)) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) & \ + BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) +#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8822B(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822B(x) | \ + BIT_EXPRSP_CHKSM_7_TO_0_8822B(v)) #define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B 0 #define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B 0xff -#define BIT_EXPRSP_CHKSM_15_TO_8_8822B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) -#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) - - +#define BIT_EXPRSP_CHKSM_15_TO_8_8822B(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) +#define BITS_EXPRSP_CHKSM_15_TO_8_8822B \ + (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) +#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822B(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8822B)) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822B(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) & \ + BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) +#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8822B(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822B(x) | \ + BIT_EXPRSP_CHKSM_15_TO_8_8822B(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822B */ #define BIT_SHIFT_WMAC_ARPIP_8822B 0 #define BIT_MASK_WMAC_ARPIP_8822B 0xffffffffL -#define BIT_WMAC_ARPIP_8822B(x) (((x) & BIT_MASK_WMAC_ARPIP_8822B) << BIT_SHIFT_WMAC_ARPIP_8822B) -#define BIT_GET_WMAC_ARPIP_8822B(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8822B) & BIT_MASK_WMAC_ARPIP_8822B) - - +#define BIT_WMAC_ARPIP_8822B(x) \ + (((x) & BIT_MASK_WMAC_ARPIP_8822B) << BIT_SHIFT_WMAC_ARPIP_8822B) +#define BITS_WMAC_ARPIP_8822B \ + (BIT_MASK_WMAC_ARPIP_8822B << BIT_SHIFT_WMAC_ARPIP_8822B) +#define BIT_CLEAR_WMAC_ARPIP_8822B(x) ((x) & (~BITS_WMAC_ARPIP_8822B)) +#define BIT_GET_WMAC_ARPIP_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_ARPIP_8822B) & BIT_MASK_WMAC_ARPIP_8822B) +#define BIT_SET_WMAC_ARPIP_8822B(x, v) \ + (BIT_CLEAR_WMAC_ARPIP_8822B(x) | BIT_WMAC_ARPIP_8822B(v)) /* 2 REG_BEAMFORMING_INFO_NSARP_8822B */ #define BIT_SHIFT_BEAMFORMING_INFO_8822B 0 #define BIT_MASK_BEAMFORMING_INFO_8822B 0xffffffffL -#define BIT_BEAMFORMING_INFO_8822B(x) (((x) & BIT_MASK_BEAMFORMING_INFO_8822B) << BIT_SHIFT_BEAMFORMING_INFO_8822B) -#define BIT_GET_BEAMFORMING_INFO_8822B(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8822B) & BIT_MASK_BEAMFORMING_INFO_8822B) - - +#define BIT_BEAMFORMING_INFO_8822B(x) \ + (((x) & BIT_MASK_BEAMFORMING_INFO_8822B) \ + << BIT_SHIFT_BEAMFORMING_INFO_8822B) +#define BITS_BEAMFORMING_INFO_8822B \ + (BIT_MASK_BEAMFORMING_INFO_8822B << BIT_SHIFT_BEAMFORMING_INFO_8822B) +#define BIT_CLEAR_BEAMFORMING_INFO_8822B(x) \ + ((x) & (~BITS_BEAMFORMING_INFO_8822B)) +#define BIT_GET_BEAMFORMING_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8822B) & \ + BIT_MASK_BEAMFORMING_INFO_8822B) +#define BIT_SET_BEAMFORMING_INFO_8822B(x, v) \ + (BIT_CLEAR_BEAMFORMING_INFO_8822B(x) | BIT_BEAMFORMING_INFO_8822B(v)) /* 2 REG_NOT_VALID_8822B */ #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B 0 #define BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B 0xffffffffffffffffffffffffffffffffL -#define BIT_R_WMAC_IPV6_MYIPAD_8822B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) -#define BIT_GET_R_WMAC_IPV6_MYIPAD_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) - - +#define BIT_R_WMAC_IPV6_MYIPAD_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) +#define BITS_R_WMAC_IPV6_MYIPAD_8822B \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_8822B(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_8822B)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_8822B(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_8822B(v)) /* 2 REG_RSVD_0X740_8822B */ @@ -10101,17 +16165,37 @@ #define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B 4 #define BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B 0xf -#define BIT_R_WMAC_CTX_SUBTYPE_8822B(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) -#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) - - +#define BIT_R_WMAC_CTX_SUBTYPE_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) +#define BITS_R_WMAC_CTX_SUBTYPE_8822B \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822B(x) \ + ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8822B)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) & \ + BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) +#define BIT_SET_R_WMAC_CTX_SUBTYPE_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822B(x) | \ + BIT_R_WMAC_CTX_SUBTYPE_8822B(v)) #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B 0 #define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B 0xf -#define BIT_R_WMAC_RTX_SUBTYPE_8822B(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) -#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) - - +#define BIT_R_WMAC_RTX_SUBTYPE_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) +#define BITS_R_WMAC_RTX_SUBTYPE_8822B \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822B(x) \ + ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8822B)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) & \ + BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) +#define BIT_SET_R_WMAC_RTX_SUBTYPE_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822B(x) | \ + BIT_R_WMAC_RTX_SUBTYPE_8822B(v)) /* 2 REG_WMAC_SWAES_CFG_8822B */ @@ -10121,10 +16205,14 @@ #define BIT_SHIFT_TIMER_8822B 0 #define BIT_MASK_TIMER_8822B 0xff -#define BIT_TIMER_8822B(x) (((x) & BIT_MASK_TIMER_8822B) << BIT_SHIFT_TIMER_8822B) -#define BIT_GET_TIMER_8822B(x) (((x) >> BIT_SHIFT_TIMER_8822B) & BIT_MASK_TIMER_8822B) - - +#define BIT_TIMER_8822B(x) \ + (((x) & BIT_MASK_TIMER_8822B) << BIT_SHIFT_TIMER_8822B) +#define BITS_TIMER_8822B (BIT_MASK_TIMER_8822B << BIT_SHIFT_TIMER_8822B) +#define BIT_CLEAR_TIMER_8822B(x) ((x) & (~BITS_TIMER_8822B)) +#define BIT_GET_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_TIMER_8822B) & BIT_MASK_TIMER_8822B) +#define BIT_SET_TIMER_8822B(x, v) \ + (BIT_CLEAR_TIMER_8822B(x) | BIT_TIMER_8822B(v)) /* 2 REG_BT_COEX_8822B */ #define BIT_R_GNT_BT_RFC_SW_8822B BIT(12) @@ -10135,10 +16223,15 @@ #define BIT_SHIFT_R_BT_CNT_THR_8822B 0 #define BIT_MASK_R_BT_CNT_THR_8822B 0xff -#define BIT_R_BT_CNT_THR_8822B(x) (((x) & BIT_MASK_R_BT_CNT_THR_8822B) << BIT_SHIFT_R_BT_CNT_THR_8822B) -#define BIT_GET_R_BT_CNT_THR_8822B(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8822B) & BIT_MASK_R_BT_CNT_THR_8822B) - - +#define BIT_R_BT_CNT_THR_8822B(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR_8822B) << BIT_SHIFT_R_BT_CNT_THR_8822B) +#define BITS_R_BT_CNT_THR_8822B \ + (BIT_MASK_R_BT_CNT_THR_8822B << BIT_SHIFT_R_BT_CNT_THR_8822B) +#define BIT_CLEAR_R_BT_CNT_THR_8822B(x) ((x) & (~BITS_R_BT_CNT_THR_8822B)) +#define BIT_GET_R_BT_CNT_THR_8822B(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR_8822B) & BIT_MASK_R_BT_CNT_THR_8822B) +#define BIT_SET_R_BT_CNT_THR_8822B(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR_8822B(x) | BIT_R_BT_CNT_THR_8822B(v)) /* 2 REG_WLAN_ACT_MASK_CTRL_8822B */ #define BIT_WLRX_TER_BY_CTL_8822B BIT(43) @@ -10151,39 +16244,75 @@ #define BIT_SHIFT_RXMYRTS_NAV_V1_8822B 8 #define BIT_MASK_RXMYRTS_NAV_V1_8822B 0xff -#define BIT_RXMYRTS_NAV_V1_8822B(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8822B) << BIT_SHIFT_RXMYRTS_NAV_V1_8822B) -#define BIT_GET_RXMYRTS_NAV_V1_8822B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822B) & BIT_MASK_RXMYRTS_NAV_V1_8822B) - - +#define BIT_RXMYRTS_NAV_V1_8822B(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1_8822B) \ + << BIT_SHIFT_RXMYRTS_NAV_V1_8822B) +#define BITS_RXMYRTS_NAV_V1_8822B \ + (BIT_MASK_RXMYRTS_NAV_V1_8822B << BIT_SHIFT_RXMYRTS_NAV_V1_8822B) +#define BIT_CLEAR_RXMYRTS_NAV_V1_8822B(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8822B)) +#define BIT_GET_RXMYRTS_NAV_V1_8822B(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822B) & \ + BIT_MASK_RXMYRTS_NAV_V1_8822B) +#define BIT_SET_RXMYRTS_NAV_V1_8822B(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1_8822B(x) | BIT_RXMYRTS_NAV_V1_8822B(v)) #define BIT_SHIFT_RTSRST_V1_8822B 0 #define BIT_MASK_RTSRST_V1_8822B 0xff -#define BIT_RTSRST_V1_8822B(x) (((x) & BIT_MASK_RTSRST_V1_8822B) << BIT_SHIFT_RTSRST_V1_8822B) -#define BIT_GET_RTSRST_V1_8822B(x) (((x) >> BIT_SHIFT_RTSRST_V1_8822B) & BIT_MASK_RTSRST_V1_8822B) - - +#define BIT_RTSRST_V1_8822B(x) \ + (((x) & BIT_MASK_RTSRST_V1_8822B) << BIT_SHIFT_RTSRST_V1_8822B) +#define BITS_RTSRST_V1_8822B \ + (BIT_MASK_RTSRST_V1_8822B << BIT_SHIFT_RTSRST_V1_8822B) +#define BIT_CLEAR_RTSRST_V1_8822B(x) ((x) & (~BITS_RTSRST_V1_8822B)) +#define BIT_GET_RTSRST_V1_8822B(x) \ + (((x) >> BIT_SHIFT_RTSRST_V1_8822B) & BIT_MASK_RTSRST_V1_8822B) +#define BIT_SET_RTSRST_V1_8822B(x, v) \ + (BIT_CLEAR_RTSRST_V1_8822B(x) | BIT_RTSRST_V1_8822B(v)) /* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822B */ #define BIT_SHIFT_BT_STAT_DELAY_8822B 12 #define BIT_MASK_BT_STAT_DELAY_8822B 0xf -#define BIT_BT_STAT_DELAY_8822B(x) (((x) & BIT_MASK_BT_STAT_DELAY_8822B) << BIT_SHIFT_BT_STAT_DELAY_8822B) -#define BIT_GET_BT_STAT_DELAY_8822B(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8822B) & BIT_MASK_BT_STAT_DELAY_8822B) - - +#define BIT_BT_STAT_DELAY_8822B(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY_8822B) << BIT_SHIFT_BT_STAT_DELAY_8822B) +#define BITS_BT_STAT_DELAY_8822B \ + (BIT_MASK_BT_STAT_DELAY_8822B << BIT_SHIFT_BT_STAT_DELAY_8822B) +#define BIT_CLEAR_BT_STAT_DELAY_8822B(x) ((x) & (~BITS_BT_STAT_DELAY_8822B)) +#define BIT_GET_BT_STAT_DELAY_8822B(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY_8822B) & BIT_MASK_BT_STAT_DELAY_8822B) +#define BIT_SET_BT_STAT_DELAY_8822B(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY_8822B(x) | BIT_BT_STAT_DELAY_8822B(v)) #define BIT_SHIFT_BT_TRX_INIT_DETECT_8822B 8 #define BIT_MASK_BT_TRX_INIT_DETECT_8822B 0xf -#define BIT_BT_TRX_INIT_DETECT_8822B(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822B) << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) -#define BIT_GET_BT_TRX_INIT_DETECT_8822B(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) & BIT_MASK_BT_TRX_INIT_DETECT_8822B) - - +#define BIT_BT_TRX_INIT_DETECT_8822B(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822B) \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) +#define BITS_BT_TRX_INIT_DETECT_8822B \ + (BIT_MASK_BT_TRX_INIT_DETECT_8822B \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) +#define BIT_CLEAR_BT_TRX_INIT_DETECT_8822B(x) \ + ((x) & (~BITS_BT_TRX_INIT_DETECT_8822B)) +#define BIT_GET_BT_TRX_INIT_DETECT_8822B(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) & \ + BIT_MASK_BT_TRX_INIT_DETECT_8822B) +#define BIT_SET_BT_TRX_INIT_DETECT_8822B(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT_8822B(x) | \ + BIT_BT_TRX_INIT_DETECT_8822B(v)) #define BIT_SHIFT_BT_PRI_DETECT_TO_8822B 4 #define BIT_MASK_BT_PRI_DETECT_TO_8822B 0xf -#define BIT_BT_PRI_DETECT_TO_8822B(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8822B) << BIT_SHIFT_BT_PRI_DETECT_TO_8822B) -#define BIT_GET_BT_PRI_DETECT_TO_8822B(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822B) & BIT_MASK_BT_PRI_DETECT_TO_8822B) - +#define BIT_BT_PRI_DETECT_TO_8822B(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO_8822B) \ + << BIT_SHIFT_BT_PRI_DETECT_TO_8822B) +#define BITS_BT_PRI_DETECT_TO_8822B \ + (BIT_MASK_BT_PRI_DETECT_TO_8822B << BIT_SHIFT_BT_PRI_DETECT_TO_8822B) +#define BIT_CLEAR_BT_PRI_DETECT_TO_8822B(x) \ + ((x) & (~BITS_BT_PRI_DETECT_TO_8822B)) +#define BIT_GET_BT_PRI_DETECT_TO_8822B(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822B) & \ + BIT_MASK_BT_PRI_DETECT_TO_8822B) +#define BIT_SET_BT_PRI_DETECT_TO_8822B(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO_8822B(x) | BIT_BT_PRI_DETECT_TO_8822B(v)) #define BIT_R_GRANTALL_WLMASK_8822B BIT(3) #define BIT_STATIS_BT_EN_8822B BIT(2) @@ -10194,53 +16323,99 @@ #define BIT_SHIFT_STATIS_BT_LO_RX_8822B (48 & CPU_OPT_WIDTH) #define BIT_MASK_STATIS_BT_LO_RX_8822B 0xffff -#define BIT_STATIS_BT_LO_RX_8822B(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_8822B) << BIT_SHIFT_STATIS_BT_LO_RX_8822B) -#define BIT_GET_STATIS_BT_LO_RX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8822B) & BIT_MASK_STATIS_BT_LO_RX_8822B) - - +#define BIT_STATIS_BT_LO_RX_8822B(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_8822B) \ + << BIT_SHIFT_STATIS_BT_LO_RX_8822B) +#define BITS_STATIS_BT_LO_RX_8822B \ + (BIT_MASK_STATIS_BT_LO_RX_8822B << BIT_SHIFT_STATIS_BT_LO_RX_8822B) +#define BIT_CLEAR_STATIS_BT_LO_RX_8822B(x) ((x) & (~BITS_STATIS_BT_LO_RX_8822B)) +#define BIT_GET_STATIS_BT_LO_RX_8822B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8822B) & \ + BIT_MASK_STATIS_BT_LO_RX_8822B) +#define BIT_SET_STATIS_BT_LO_RX_8822B(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_8822B(x) | BIT_STATIS_BT_LO_RX_8822B(v)) #define BIT_SHIFT_STATIS_BT_LO_TX_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_STATIS_BT_LO_TX_8822B 0xffff -#define BIT_STATIS_BT_LO_TX_8822B(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_8822B) << BIT_SHIFT_STATIS_BT_LO_TX_8822B) -#define BIT_GET_STATIS_BT_LO_TX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8822B) & BIT_MASK_STATIS_BT_LO_TX_8822B) - - +#define BIT_STATIS_BT_LO_TX_8822B(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_8822B) \ + << BIT_SHIFT_STATIS_BT_LO_TX_8822B) +#define BITS_STATIS_BT_LO_TX_8822B \ + (BIT_MASK_STATIS_BT_LO_TX_8822B << BIT_SHIFT_STATIS_BT_LO_TX_8822B) +#define BIT_CLEAR_STATIS_BT_LO_TX_8822B(x) ((x) & (~BITS_STATIS_BT_LO_TX_8822B)) +#define BIT_GET_STATIS_BT_LO_TX_8822B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8822B) & \ + BIT_MASK_STATIS_BT_LO_TX_8822B) +#define BIT_SET_STATIS_BT_LO_TX_8822B(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_8822B(x) | BIT_STATIS_BT_LO_TX_8822B(v)) #define BIT_SHIFT_STATIS_BT_HI_RX_8822B 16 #define BIT_MASK_STATIS_BT_HI_RX_8822B 0xffff -#define BIT_STATIS_BT_HI_RX_8822B(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8822B) << BIT_SHIFT_STATIS_BT_HI_RX_8822B) -#define BIT_GET_STATIS_BT_HI_RX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822B) & BIT_MASK_STATIS_BT_HI_RX_8822B) - - +#define BIT_STATIS_BT_HI_RX_8822B(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX_8822B) \ + << BIT_SHIFT_STATIS_BT_HI_RX_8822B) +#define BITS_STATIS_BT_HI_RX_8822B \ + (BIT_MASK_STATIS_BT_HI_RX_8822B << BIT_SHIFT_STATIS_BT_HI_RX_8822B) +#define BIT_CLEAR_STATIS_BT_HI_RX_8822B(x) ((x) & (~BITS_STATIS_BT_HI_RX_8822B)) +#define BIT_GET_STATIS_BT_HI_RX_8822B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822B) & \ + BIT_MASK_STATIS_BT_HI_RX_8822B) +#define BIT_SET_STATIS_BT_HI_RX_8822B(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX_8822B(x) | BIT_STATIS_BT_HI_RX_8822B(v)) #define BIT_SHIFT_STATIS_BT_HI_TX_8822B 0 #define BIT_MASK_STATIS_BT_HI_TX_8822B 0xffff -#define BIT_STATIS_BT_HI_TX_8822B(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8822B) << BIT_SHIFT_STATIS_BT_HI_TX_8822B) -#define BIT_GET_STATIS_BT_HI_TX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822B) & BIT_MASK_STATIS_BT_HI_TX_8822B) - - +#define BIT_STATIS_BT_HI_TX_8822B(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX_8822B) \ + << BIT_SHIFT_STATIS_BT_HI_TX_8822B) +#define BITS_STATIS_BT_HI_TX_8822B \ + (BIT_MASK_STATIS_BT_HI_TX_8822B << BIT_SHIFT_STATIS_BT_HI_TX_8822B) +#define BIT_CLEAR_STATIS_BT_HI_TX_8822B(x) ((x) & (~BITS_STATIS_BT_HI_TX_8822B)) +#define BIT_GET_STATIS_BT_HI_TX_8822B(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822B) & \ + BIT_MASK_STATIS_BT_HI_TX_8822B) +#define BIT_SET_STATIS_BT_HI_TX_8822B(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX_8822B(x) | BIT_STATIS_BT_HI_TX_8822B(v)) /* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822B */ #define BIT_SHIFT_R_BT_CMD_RPT_8822B 16 #define BIT_MASK_R_BT_CMD_RPT_8822B 0xffff -#define BIT_R_BT_CMD_RPT_8822B(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8822B) << BIT_SHIFT_R_BT_CMD_RPT_8822B) -#define BIT_GET_R_BT_CMD_RPT_8822B(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822B) & BIT_MASK_R_BT_CMD_RPT_8822B) - - +#define BIT_R_BT_CMD_RPT_8822B(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT_8822B) << BIT_SHIFT_R_BT_CMD_RPT_8822B) +#define BITS_R_BT_CMD_RPT_8822B \ + (BIT_MASK_R_BT_CMD_RPT_8822B << BIT_SHIFT_R_BT_CMD_RPT_8822B) +#define BIT_CLEAR_R_BT_CMD_RPT_8822B(x) ((x) & (~BITS_R_BT_CMD_RPT_8822B)) +#define BIT_GET_R_BT_CMD_RPT_8822B(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822B) & BIT_MASK_R_BT_CMD_RPT_8822B) +#define BIT_SET_R_BT_CMD_RPT_8822B(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT_8822B(x) | BIT_R_BT_CMD_RPT_8822B(v)) #define BIT_SHIFT_R_RPT_FROM_BT_8822B 8 #define BIT_MASK_R_RPT_FROM_BT_8822B 0xff -#define BIT_R_RPT_FROM_BT_8822B(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8822B) << BIT_SHIFT_R_RPT_FROM_BT_8822B) -#define BIT_GET_R_RPT_FROM_BT_8822B(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822B) & BIT_MASK_R_RPT_FROM_BT_8822B) - - +#define BIT_R_RPT_FROM_BT_8822B(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT_8822B) << BIT_SHIFT_R_RPT_FROM_BT_8822B) +#define BITS_R_RPT_FROM_BT_8822B \ + (BIT_MASK_R_RPT_FROM_BT_8822B << BIT_SHIFT_R_RPT_FROM_BT_8822B) +#define BIT_CLEAR_R_RPT_FROM_BT_8822B(x) ((x) & (~BITS_R_RPT_FROM_BT_8822B)) +#define BIT_GET_R_RPT_FROM_BT_8822B(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822B) & BIT_MASK_R_RPT_FROM_BT_8822B) +#define BIT_SET_R_RPT_FROM_BT_8822B(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT_8822B(x) | BIT_R_RPT_FROM_BT_8822B(v)) #define BIT_SHIFT_BT_HID_ISR_SET_8822B 6 #define BIT_MASK_BT_HID_ISR_SET_8822B 0x3 -#define BIT_BT_HID_ISR_SET_8822B(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8822B) << BIT_SHIFT_BT_HID_ISR_SET_8822B) -#define BIT_GET_BT_HID_ISR_SET_8822B(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822B) & BIT_MASK_BT_HID_ISR_SET_8822B) - +#define BIT_BT_HID_ISR_SET_8822B(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET_8822B) \ + << BIT_SHIFT_BT_HID_ISR_SET_8822B) +#define BITS_BT_HID_ISR_SET_8822B \ + (BIT_MASK_BT_HID_ISR_SET_8822B << BIT_SHIFT_BT_HID_ISR_SET_8822B) +#define BIT_CLEAR_BT_HID_ISR_SET_8822B(x) ((x) & (~BITS_BT_HID_ISR_SET_8822B)) +#define BIT_GET_BT_HID_ISR_SET_8822B(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822B) & \ + BIT_MASK_BT_HID_ISR_SET_8822B) +#define BIT_SET_BT_HID_ISR_SET_8822B(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET_8822B(x) | BIT_BT_HID_ISR_SET_8822B(v)) #define BIT_TDMA_BT_START_NOTIFY_8822B BIT(5) #define BIT_ENABLE_TDMA_FW_MODE_8822B BIT(4) @@ -10253,31 +16428,54 @@ #define BIT_SHIFT_BT_PROFILE_8822B 24 #define BIT_MASK_BT_PROFILE_8822B 0xff -#define BIT_BT_PROFILE_8822B(x) (((x) & BIT_MASK_BT_PROFILE_8822B) << BIT_SHIFT_BT_PROFILE_8822B) -#define BIT_GET_BT_PROFILE_8822B(x) (((x) >> BIT_SHIFT_BT_PROFILE_8822B) & BIT_MASK_BT_PROFILE_8822B) - - +#define BIT_BT_PROFILE_8822B(x) \ + (((x) & BIT_MASK_BT_PROFILE_8822B) << BIT_SHIFT_BT_PROFILE_8822B) +#define BITS_BT_PROFILE_8822B \ + (BIT_MASK_BT_PROFILE_8822B << BIT_SHIFT_BT_PROFILE_8822B) +#define BIT_CLEAR_BT_PROFILE_8822B(x) ((x) & (~BITS_BT_PROFILE_8822B)) +#define BIT_GET_BT_PROFILE_8822B(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE_8822B) & BIT_MASK_BT_PROFILE_8822B) +#define BIT_SET_BT_PROFILE_8822B(x, v) \ + (BIT_CLEAR_BT_PROFILE_8822B(x) | BIT_BT_PROFILE_8822B(v)) #define BIT_SHIFT_BT_POWER_8822B 16 #define BIT_MASK_BT_POWER_8822B 0xff -#define BIT_BT_POWER_8822B(x) (((x) & BIT_MASK_BT_POWER_8822B) << BIT_SHIFT_BT_POWER_8822B) -#define BIT_GET_BT_POWER_8822B(x) (((x) >> BIT_SHIFT_BT_POWER_8822B) & BIT_MASK_BT_POWER_8822B) - - +#define BIT_BT_POWER_8822B(x) \ + (((x) & BIT_MASK_BT_POWER_8822B) << BIT_SHIFT_BT_POWER_8822B) +#define BITS_BT_POWER_8822B \ + (BIT_MASK_BT_POWER_8822B << BIT_SHIFT_BT_POWER_8822B) +#define BIT_CLEAR_BT_POWER_8822B(x) ((x) & (~BITS_BT_POWER_8822B)) +#define BIT_GET_BT_POWER_8822B(x) \ + (((x) >> BIT_SHIFT_BT_POWER_8822B) & BIT_MASK_BT_POWER_8822B) +#define BIT_SET_BT_POWER_8822B(x, v) \ + (BIT_CLEAR_BT_POWER_8822B(x) | BIT_BT_POWER_8822B(v)) #define BIT_SHIFT_BT_PREDECT_STATUS_8822B 8 #define BIT_MASK_BT_PREDECT_STATUS_8822B 0xff -#define BIT_BT_PREDECT_STATUS_8822B(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8822B) << BIT_SHIFT_BT_PREDECT_STATUS_8822B) -#define BIT_GET_BT_PREDECT_STATUS_8822B(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822B) & BIT_MASK_BT_PREDECT_STATUS_8822B) - - +#define BIT_BT_PREDECT_STATUS_8822B(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS_8822B) \ + << BIT_SHIFT_BT_PREDECT_STATUS_8822B) +#define BITS_BT_PREDECT_STATUS_8822B \ + (BIT_MASK_BT_PREDECT_STATUS_8822B << BIT_SHIFT_BT_PREDECT_STATUS_8822B) +#define BIT_CLEAR_BT_PREDECT_STATUS_8822B(x) \ + ((x) & (~BITS_BT_PREDECT_STATUS_8822B)) +#define BIT_GET_BT_PREDECT_STATUS_8822B(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822B) & \ + BIT_MASK_BT_PREDECT_STATUS_8822B) +#define BIT_SET_BT_PREDECT_STATUS_8822B(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS_8822B(x) | BIT_BT_PREDECT_STATUS_8822B(v)) #define BIT_SHIFT_BT_CMD_INFO_8822B 0 #define BIT_MASK_BT_CMD_INFO_8822B 0xff -#define BIT_BT_CMD_INFO_8822B(x) (((x) & BIT_MASK_BT_CMD_INFO_8822B) << BIT_SHIFT_BT_CMD_INFO_8822B) -#define BIT_GET_BT_CMD_INFO_8822B(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8822B) & BIT_MASK_BT_CMD_INFO_8822B) - - +#define BIT_BT_CMD_INFO_8822B(x) \ + (((x) & BIT_MASK_BT_CMD_INFO_8822B) << BIT_SHIFT_BT_CMD_INFO_8822B) +#define BITS_BT_CMD_INFO_8822B \ + (BIT_MASK_BT_CMD_INFO_8822B << BIT_SHIFT_BT_CMD_INFO_8822B) +#define BIT_CLEAR_BT_CMD_INFO_8822B(x) ((x) & (~BITS_BT_CMD_INFO_8822B)) +#define BIT_GET_BT_CMD_INFO_8822B(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO_8822B) & BIT_MASK_BT_CMD_INFO_8822B) +#define BIT_SET_BT_CMD_INFO_8822B(x, v) \ + (BIT_CLEAR_BT_CMD_INFO_8822B(x) | BIT_BT_CMD_INFO_8822B(v)) /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822B */ #define BIT_EN_MAC_NULL_PKT_NOTIFY_8822B BIT(31) @@ -10291,41 +16489,65 @@ #define BIT_SHIFT_WLAN_RPT_DATA_8822B 16 #define BIT_MASK_WLAN_RPT_DATA_8822B 0xff -#define BIT_WLAN_RPT_DATA_8822B(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8822B) << BIT_SHIFT_WLAN_RPT_DATA_8822B) -#define BIT_GET_WLAN_RPT_DATA_8822B(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822B) & BIT_MASK_WLAN_RPT_DATA_8822B) - - +#define BIT_WLAN_RPT_DATA_8822B(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA_8822B) << BIT_SHIFT_WLAN_RPT_DATA_8822B) +#define BITS_WLAN_RPT_DATA_8822B \ + (BIT_MASK_WLAN_RPT_DATA_8822B << BIT_SHIFT_WLAN_RPT_DATA_8822B) +#define BIT_CLEAR_WLAN_RPT_DATA_8822B(x) ((x) & (~BITS_WLAN_RPT_DATA_8822B)) +#define BIT_GET_WLAN_RPT_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822B) & BIT_MASK_WLAN_RPT_DATA_8822B) +#define BIT_SET_WLAN_RPT_DATA_8822B(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA_8822B(x) | BIT_WLAN_RPT_DATA_8822B(v)) #define BIT_SHIFT_CMD_ID_8822B 8 #define BIT_MASK_CMD_ID_8822B 0xff -#define BIT_CMD_ID_8822B(x) (((x) & BIT_MASK_CMD_ID_8822B) << BIT_SHIFT_CMD_ID_8822B) -#define BIT_GET_CMD_ID_8822B(x) (((x) >> BIT_SHIFT_CMD_ID_8822B) & BIT_MASK_CMD_ID_8822B) - - +#define BIT_CMD_ID_8822B(x) \ + (((x) & BIT_MASK_CMD_ID_8822B) << BIT_SHIFT_CMD_ID_8822B) +#define BITS_CMD_ID_8822B (BIT_MASK_CMD_ID_8822B << BIT_SHIFT_CMD_ID_8822B) +#define BIT_CLEAR_CMD_ID_8822B(x) ((x) & (~BITS_CMD_ID_8822B)) +#define BIT_GET_CMD_ID_8822B(x) \ + (((x) >> BIT_SHIFT_CMD_ID_8822B) & BIT_MASK_CMD_ID_8822B) +#define BIT_SET_CMD_ID_8822B(x, v) \ + (BIT_CLEAR_CMD_ID_8822B(x) | BIT_CMD_ID_8822B(v)) #define BIT_SHIFT_BT_DATA_8822B 0 #define BIT_MASK_BT_DATA_8822B 0xff -#define BIT_BT_DATA_8822B(x) (((x) & BIT_MASK_BT_DATA_8822B) << BIT_SHIFT_BT_DATA_8822B) -#define BIT_GET_BT_DATA_8822B(x) (((x) >> BIT_SHIFT_BT_DATA_8822B) & BIT_MASK_BT_DATA_8822B) - - +#define BIT_BT_DATA_8822B(x) \ + (((x) & BIT_MASK_BT_DATA_8822B) << BIT_SHIFT_BT_DATA_8822B) +#define BITS_BT_DATA_8822B (BIT_MASK_BT_DATA_8822B << BIT_SHIFT_BT_DATA_8822B) +#define BIT_CLEAR_BT_DATA_8822B(x) ((x) & (~BITS_BT_DATA_8822B)) +#define BIT_GET_BT_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_BT_DATA_8822B) & BIT_MASK_BT_DATA_8822B) +#define BIT_SET_BT_DATA_8822B(x, v) \ + (BIT_CLEAR_BT_DATA_8822B(x) | BIT_BT_DATA_8822B(v)) /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B */ #define BIT_SHIFT_WLAN_RPT_TO_8822B 0 #define BIT_MASK_WLAN_RPT_TO_8822B 0xff -#define BIT_WLAN_RPT_TO_8822B(x) (((x) & BIT_MASK_WLAN_RPT_TO_8822B) << BIT_SHIFT_WLAN_RPT_TO_8822B) -#define BIT_GET_WLAN_RPT_TO_8822B(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8822B) & BIT_MASK_WLAN_RPT_TO_8822B) - - +#define BIT_WLAN_RPT_TO_8822B(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO_8822B) << BIT_SHIFT_WLAN_RPT_TO_8822B) +#define BITS_WLAN_RPT_TO_8822B \ + (BIT_MASK_WLAN_RPT_TO_8822B << BIT_SHIFT_WLAN_RPT_TO_8822B) +#define BIT_CLEAR_WLAN_RPT_TO_8822B(x) ((x) & (~BITS_WLAN_RPT_TO_8822B)) +#define BIT_GET_WLAN_RPT_TO_8822B(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO_8822B) & BIT_MASK_WLAN_RPT_TO_8822B) +#define BIT_SET_WLAN_RPT_TO_8822B(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO_8822B(x) | BIT_WLAN_RPT_TO_8822B(v)) /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B */ #define BIT_SHIFT_ISOLATION_CHK_8822B 1 #define BIT_MASK_ISOLATION_CHK_8822B 0x7fffffffffffffffffffL -#define BIT_ISOLATION_CHK_8822B(x) (((x) & BIT_MASK_ISOLATION_CHK_8822B) << BIT_SHIFT_ISOLATION_CHK_8822B) -#define BIT_GET_ISOLATION_CHK_8822B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_8822B) & BIT_MASK_ISOLATION_CHK_8822B) - +#define BIT_ISOLATION_CHK_8822B(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_8822B) << BIT_SHIFT_ISOLATION_CHK_8822B) +#define BITS_ISOLATION_CHK_8822B \ + (BIT_MASK_ISOLATION_CHK_8822B << BIT_SHIFT_ISOLATION_CHK_8822B) +#define BIT_CLEAR_ISOLATION_CHK_8822B(x) ((x) & (~BITS_ISOLATION_CHK_8822B)) +#define BIT_GET_ISOLATION_CHK_8822B(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_8822B) & BIT_MASK_ISOLATION_CHK_8822B) +#define BIT_SET_ISOLATION_CHK_8822B(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_8822B(x) | BIT_ISOLATION_CHK_8822B(v)) #define BIT_ISOLATION_EN_8822B BIT(0) @@ -10343,25 +16565,45 @@ #define BIT_SHIFT_BT_TIME_8822B 6 #define BIT_MASK_BT_TIME_8822B 0x3ffffff -#define BIT_BT_TIME_8822B(x) (((x) & BIT_MASK_BT_TIME_8822B) << BIT_SHIFT_BT_TIME_8822B) -#define BIT_GET_BT_TIME_8822B(x) (((x) >> BIT_SHIFT_BT_TIME_8822B) & BIT_MASK_BT_TIME_8822B) - - +#define BIT_BT_TIME_8822B(x) \ + (((x) & BIT_MASK_BT_TIME_8822B) << BIT_SHIFT_BT_TIME_8822B) +#define BITS_BT_TIME_8822B (BIT_MASK_BT_TIME_8822B << BIT_SHIFT_BT_TIME_8822B) +#define BIT_CLEAR_BT_TIME_8822B(x) ((x) & (~BITS_BT_TIME_8822B)) +#define BIT_GET_BT_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_BT_TIME_8822B) & BIT_MASK_BT_TIME_8822B) +#define BIT_SET_BT_TIME_8822B(x, v) \ + (BIT_CLEAR_BT_TIME_8822B(x) | BIT_BT_TIME_8822B(v)) #define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B 0 #define BIT_MASK_BT_RPT_SAMPLE_RATE_8822B 0x3f -#define BIT_BT_RPT_SAMPLE_RATE_8822B(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) -#define BIT_GET_BT_RPT_SAMPLE_RATE_8822B(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) - - +#define BIT_BT_RPT_SAMPLE_RATE_8822B(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) +#define BITS_BT_RPT_SAMPLE_RATE_8822B \ + (BIT_MASK_BT_RPT_SAMPLE_RATE_8822B \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822B(x) \ + ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8822B)) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8822B(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) & \ + BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) +#define BIT_SET_BT_RPT_SAMPLE_RATE_8822B(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822B(x) | \ + BIT_BT_RPT_SAMPLE_RATE_8822B(v)) /* 2 REG_BT_ACT_REGISTER_8822B */ #define BIT_SHIFT_BT_EISR_EN_8822B 16 #define BIT_MASK_BT_EISR_EN_8822B 0xff -#define BIT_BT_EISR_EN_8822B(x) (((x) & BIT_MASK_BT_EISR_EN_8822B) << BIT_SHIFT_BT_EISR_EN_8822B) -#define BIT_GET_BT_EISR_EN_8822B(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8822B) & BIT_MASK_BT_EISR_EN_8822B) - +#define BIT_BT_EISR_EN_8822B(x) \ + (((x) & BIT_MASK_BT_EISR_EN_8822B) << BIT_SHIFT_BT_EISR_EN_8822B) +#define BITS_BT_EISR_EN_8822B \ + (BIT_MASK_BT_EISR_EN_8822B << BIT_SHIFT_BT_EISR_EN_8822B) +#define BIT_CLEAR_BT_EISR_EN_8822B(x) ((x) & (~BITS_BT_EISR_EN_8822B)) +#define BIT_GET_BT_EISR_EN_8822B(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN_8822B) & BIT_MASK_BT_EISR_EN_8822B) +#define BIT_SET_BT_EISR_EN_8822B(x, v) \ + (BIT_CLEAR_BT_EISR_EN_8822B(x) | BIT_BT_EISR_EN_8822B(v)) #define BIT_BT_ACT_FALLING_ISR_8822B BIT(10) #define BIT_BT_ACT_RISING_ISR_8822B BIT(9) @@ -10369,19 +16611,29 @@ #define BIT_SHIFT_BT_CH_8822B 0 #define BIT_MASK_BT_CH_8822B 0xff -#define BIT_BT_CH_8822B(x) (((x) & BIT_MASK_BT_CH_8822B) << BIT_SHIFT_BT_CH_8822B) -#define BIT_GET_BT_CH_8822B(x) (((x) >> BIT_SHIFT_BT_CH_8822B) & BIT_MASK_BT_CH_8822B) - - +#define BIT_BT_CH_8822B(x) \ + (((x) & BIT_MASK_BT_CH_8822B) << BIT_SHIFT_BT_CH_8822B) +#define BITS_BT_CH_8822B (BIT_MASK_BT_CH_8822B << BIT_SHIFT_BT_CH_8822B) +#define BIT_CLEAR_BT_CH_8822B(x) ((x) & (~BITS_BT_CH_8822B)) +#define BIT_GET_BT_CH_8822B(x) \ + (((x) >> BIT_SHIFT_BT_CH_8822B) & BIT_MASK_BT_CH_8822B) +#define BIT_SET_BT_CH_8822B(x, v) \ + (BIT_CLEAR_BT_CH_8822B(x) | BIT_BT_CH_8822B(v)) /* 2 REG_OBFF_CTRL_BASIC_8822B */ #define BIT_OBFF_EN_V1_8822B BIT(31) #define BIT_SHIFT_OBFF_STATE_V1_8822B 28 #define BIT_MASK_OBFF_STATE_V1_8822B 0x3 -#define BIT_OBFF_STATE_V1_8822B(x) (((x) & BIT_MASK_OBFF_STATE_V1_8822B) << BIT_SHIFT_OBFF_STATE_V1_8822B) -#define BIT_GET_OBFF_STATE_V1_8822B(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8822B) & BIT_MASK_OBFF_STATE_V1_8822B) - +#define BIT_OBFF_STATE_V1_8822B(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1_8822B) << BIT_SHIFT_OBFF_STATE_V1_8822B) +#define BITS_OBFF_STATE_V1_8822B \ + (BIT_MASK_OBFF_STATE_V1_8822B << BIT_SHIFT_OBFF_STATE_V1_8822B) +#define BIT_CLEAR_OBFF_STATE_V1_8822B(x) ((x) & (~BITS_OBFF_STATE_V1_8822B)) +#define BIT_GET_OBFF_STATE_V1_8822B(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1_8822B) & BIT_MASK_OBFF_STATE_V1_8822B) +#define BIT_SET_OBFF_STATE_V1_8822B(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1_8822B(x) | BIT_OBFF_STATE_V1_8822B(v)) #define BIT_OBFF_ACT_RXDMA_EN_8822B BIT(27) #define BIT_OBFF_BLOCK_INT_EN_8822B BIT(26) @@ -10390,30 +16642,51 @@ #define BIT_SHIFT_WAKE_MAX_PLS_8822B 20 #define BIT_MASK_WAKE_MAX_PLS_8822B 0x7 -#define BIT_WAKE_MAX_PLS_8822B(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8822B) << BIT_SHIFT_WAKE_MAX_PLS_8822B) -#define BIT_GET_WAKE_MAX_PLS_8822B(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822B) & BIT_MASK_WAKE_MAX_PLS_8822B) - - +#define BIT_WAKE_MAX_PLS_8822B(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS_8822B) << BIT_SHIFT_WAKE_MAX_PLS_8822B) +#define BITS_WAKE_MAX_PLS_8822B \ + (BIT_MASK_WAKE_MAX_PLS_8822B << BIT_SHIFT_WAKE_MAX_PLS_8822B) +#define BIT_CLEAR_WAKE_MAX_PLS_8822B(x) ((x) & (~BITS_WAKE_MAX_PLS_8822B)) +#define BIT_GET_WAKE_MAX_PLS_8822B(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822B) & BIT_MASK_WAKE_MAX_PLS_8822B) +#define BIT_SET_WAKE_MAX_PLS_8822B(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS_8822B(x) | BIT_WAKE_MAX_PLS_8822B(v)) #define BIT_SHIFT_WAKE_MIN_PLS_8822B 16 #define BIT_MASK_WAKE_MIN_PLS_8822B 0x7 -#define BIT_WAKE_MIN_PLS_8822B(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8822B) << BIT_SHIFT_WAKE_MIN_PLS_8822B) -#define BIT_GET_WAKE_MIN_PLS_8822B(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822B) & BIT_MASK_WAKE_MIN_PLS_8822B) - - +#define BIT_WAKE_MIN_PLS_8822B(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS_8822B) << BIT_SHIFT_WAKE_MIN_PLS_8822B) +#define BITS_WAKE_MIN_PLS_8822B \ + (BIT_MASK_WAKE_MIN_PLS_8822B << BIT_SHIFT_WAKE_MIN_PLS_8822B) +#define BIT_CLEAR_WAKE_MIN_PLS_8822B(x) ((x) & (~BITS_WAKE_MIN_PLS_8822B)) +#define BIT_GET_WAKE_MIN_PLS_8822B(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822B) & BIT_MASK_WAKE_MIN_PLS_8822B) +#define BIT_SET_WAKE_MIN_PLS_8822B(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS_8822B(x) | BIT_WAKE_MIN_PLS_8822B(v)) #define BIT_SHIFT_WAKE_MAX_F2F_8822B 12 #define BIT_MASK_WAKE_MAX_F2F_8822B 0x7 -#define BIT_WAKE_MAX_F2F_8822B(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8822B) << BIT_SHIFT_WAKE_MAX_F2F_8822B) -#define BIT_GET_WAKE_MAX_F2F_8822B(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822B) & BIT_MASK_WAKE_MAX_F2F_8822B) - - +#define BIT_WAKE_MAX_F2F_8822B(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F_8822B) << BIT_SHIFT_WAKE_MAX_F2F_8822B) +#define BITS_WAKE_MAX_F2F_8822B \ + (BIT_MASK_WAKE_MAX_F2F_8822B << BIT_SHIFT_WAKE_MAX_F2F_8822B) +#define BIT_CLEAR_WAKE_MAX_F2F_8822B(x) ((x) & (~BITS_WAKE_MAX_F2F_8822B)) +#define BIT_GET_WAKE_MAX_F2F_8822B(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822B) & BIT_MASK_WAKE_MAX_F2F_8822B) +#define BIT_SET_WAKE_MAX_F2F_8822B(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F_8822B(x) | BIT_WAKE_MAX_F2F_8822B(v)) #define BIT_SHIFT_WAKE_MIN_F2F_8822B 8 #define BIT_MASK_WAKE_MIN_F2F_8822B 0x7 -#define BIT_WAKE_MIN_F2F_8822B(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8822B) << BIT_SHIFT_WAKE_MIN_F2F_8822B) -#define BIT_GET_WAKE_MIN_F2F_8822B(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822B) & BIT_MASK_WAKE_MIN_F2F_8822B) - +#define BIT_WAKE_MIN_F2F_8822B(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F_8822B) << BIT_SHIFT_WAKE_MIN_F2F_8822B) +#define BITS_WAKE_MIN_F2F_8822B \ + (BIT_MASK_WAKE_MIN_F2F_8822B << BIT_SHIFT_WAKE_MIN_F2F_8822B) +#define BIT_CLEAR_WAKE_MIN_F2F_8822B(x) ((x) & (~BITS_WAKE_MIN_F2F_8822B)) +#define BIT_GET_WAKE_MIN_F2F_8822B(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822B) & BIT_MASK_WAKE_MIN_F2F_8822B) +#define BIT_SET_WAKE_MIN_F2F_8822B(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F_8822B(x) | BIT_WAKE_MIN_F2F_8822B(v)) #define BIT_APP_CPU_ACT_V1_8822B BIT(3) #define BIT_APP_OBFF_V1_8822B BIT(2) @@ -10424,31 +16697,65 @@ #define BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B 24 #define BIT_MASK_RX_HIGH_TIMER_IDX_8822B 0x7 -#define BIT_RX_HIGH_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) -#define BIT_GET_RX_HIGH_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B) - - +#define BIT_RX_HIGH_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B) \ + << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) +#define BITS_RX_HIGH_TIMER_IDX_8822B \ + (BIT_MASK_RX_HIGH_TIMER_IDX_8822B << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_RX_HIGH_TIMER_IDX_8822B)) +#define BIT_GET_RX_HIGH_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) & \ + BIT_MASK_RX_HIGH_TIMER_IDX_8822B) +#define BIT_SET_RX_HIGH_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX_8822B(x) | BIT_RX_HIGH_TIMER_IDX_8822B(v)) #define BIT_SHIFT_RX_MED_TIMER_IDX_8822B 16 #define BIT_MASK_RX_MED_TIMER_IDX_8822B 0x7 -#define BIT_RX_MED_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8822B) << BIT_SHIFT_RX_MED_TIMER_IDX_8822B) -#define BIT_GET_RX_MED_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822B) & BIT_MASK_RX_MED_TIMER_IDX_8822B) - - +#define BIT_RX_MED_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX_8822B) \ + << BIT_SHIFT_RX_MED_TIMER_IDX_8822B) +#define BITS_RX_MED_TIMER_IDX_8822B \ + (BIT_MASK_RX_MED_TIMER_IDX_8822B << BIT_SHIFT_RX_MED_TIMER_IDX_8822B) +#define BIT_CLEAR_RX_MED_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_RX_MED_TIMER_IDX_8822B)) +#define BIT_GET_RX_MED_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822B) & \ + BIT_MASK_RX_MED_TIMER_IDX_8822B) +#define BIT_SET_RX_MED_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX_8822B(x) | BIT_RX_MED_TIMER_IDX_8822B(v)) #define BIT_SHIFT_RX_LOW_TIMER_IDX_8822B 8 #define BIT_MASK_RX_LOW_TIMER_IDX_8822B 0x7 -#define BIT_RX_LOW_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822B) << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) -#define BIT_GET_RX_LOW_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) & BIT_MASK_RX_LOW_TIMER_IDX_8822B) - - +#define BIT_RX_LOW_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822B) \ + << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) +#define BITS_RX_LOW_TIMER_IDX_8822B \ + (BIT_MASK_RX_LOW_TIMER_IDX_8822B << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) +#define BIT_CLEAR_RX_LOW_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_RX_LOW_TIMER_IDX_8822B)) +#define BIT_GET_RX_LOW_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) & \ + BIT_MASK_RX_LOW_TIMER_IDX_8822B) +#define BIT_SET_RX_LOW_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX_8822B(x) | BIT_RX_LOW_TIMER_IDX_8822B(v)) #define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B 0 #define BIT_MASK_OBFF_INT_TIMER_IDX_8822B 0x7 -#define BIT_OBFF_INT_TIMER_IDX_8822B(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) -#define BIT_GET_OBFF_INT_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B) - - +#define BIT_OBFF_INT_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B) \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) +#define BITS_OBFF_INT_TIMER_IDX_8822B \ + (BIT_MASK_OBFF_INT_TIMER_IDX_8822B \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_OBFF_INT_TIMER_IDX_8822B)) +#define BIT_GET_OBFF_INT_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) & \ + BIT_MASK_OBFF_INT_TIMER_IDX_8822B) +#define BIT_SET_OBFF_INT_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX_8822B(x) | \ + BIT_OBFF_INT_TIMER_IDX_8822B(v)) /* 2 REG_LTR_CTRL_BASIC_8822B */ #define BIT_LTR_EN_V1_8822B BIT(31) @@ -10464,107 +16771,207 @@ #define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B 20 #define BIT_MASK_HIGH_RATE_TRIG_SEL_8822B 0x3 -#define BIT_HIGH_RATE_TRIG_SEL_8822B(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) -#define BIT_GET_HIGH_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) - - +#define BIT_HIGH_RATE_TRIG_SEL_8822B(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) +#define BITS_HIGH_RATE_TRIG_SEL_8822B \ + (BIT_MASK_HIGH_RATE_TRIG_SEL_8822B \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822B(x) \ + ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8822B)) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) & \ + BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) +#define BIT_SET_HIGH_RATE_TRIG_SEL_8822B(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822B(x) | \ + BIT_HIGH_RATE_TRIG_SEL_8822B(v)) #define BIT_SHIFT_MED_RATE_TRIG_SEL_8822B 18 #define BIT_MASK_MED_RATE_TRIG_SEL_8822B 0x3 -#define BIT_MED_RATE_TRIG_SEL_8822B(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822B) << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) -#define BIT_GET_MED_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) & BIT_MASK_MED_RATE_TRIG_SEL_8822B) - - +#define BIT_MED_RATE_TRIG_SEL_8822B(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822B) \ + << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) +#define BITS_MED_RATE_TRIG_SEL_8822B \ + (BIT_MASK_MED_RATE_TRIG_SEL_8822B << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) +#define BIT_CLEAR_MED_RATE_TRIG_SEL_8822B(x) \ + ((x) & (~BITS_MED_RATE_TRIG_SEL_8822B)) +#define BIT_GET_MED_RATE_TRIG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) & \ + BIT_MASK_MED_RATE_TRIG_SEL_8822B) +#define BIT_SET_MED_RATE_TRIG_SEL_8822B(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL_8822B(x) | BIT_MED_RATE_TRIG_SEL_8822B(v)) #define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B 16 #define BIT_MASK_LOW_RATE_TRIG_SEL_8822B 0x3 -#define BIT_LOW_RATE_TRIG_SEL_8822B(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) -#define BIT_GET_LOW_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B) - - +#define BIT_LOW_RATE_TRIG_SEL_8822B(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B) \ + << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) +#define BITS_LOW_RATE_TRIG_SEL_8822B \ + (BIT_MASK_LOW_RATE_TRIG_SEL_8822B << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8822B(x) \ + ((x) & (~BITS_LOW_RATE_TRIG_SEL_8822B)) +#define BIT_GET_LOW_RATE_TRIG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) & \ + BIT_MASK_LOW_RATE_TRIG_SEL_8822B) +#define BIT_SET_LOW_RATE_TRIG_SEL_8822B(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL_8822B(x) | BIT_LOW_RATE_TRIG_SEL_8822B(v)) #define BIT_SHIFT_HIGH_RATE_BD_IDX_8822B 8 #define BIT_MASK_HIGH_RATE_BD_IDX_8822B 0x7f -#define BIT_HIGH_RATE_BD_IDX_8822B(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822B) << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) -#define BIT_GET_HIGH_RATE_BD_IDX_8822B(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) & BIT_MASK_HIGH_RATE_BD_IDX_8822B) - - +#define BIT_HIGH_RATE_BD_IDX_8822B(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822B) \ + << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) +#define BITS_HIGH_RATE_BD_IDX_8822B \ + (BIT_MASK_HIGH_RATE_BD_IDX_8822B << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) +#define BIT_CLEAR_HIGH_RATE_BD_IDX_8822B(x) \ + ((x) & (~BITS_HIGH_RATE_BD_IDX_8822B)) +#define BIT_GET_HIGH_RATE_BD_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) & \ + BIT_MASK_HIGH_RATE_BD_IDX_8822B) +#define BIT_SET_HIGH_RATE_BD_IDX_8822B(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX_8822B(x) | BIT_HIGH_RATE_BD_IDX_8822B(v)) #define BIT_SHIFT_LOW_RATE_BD_IDX_8822B 0 #define BIT_MASK_LOW_RATE_BD_IDX_8822B 0x7f -#define BIT_LOW_RATE_BD_IDX_8822B(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8822B) << BIT_SHIFT_LOW_RATE_BD_IDX_8822B) -#define BIT_GET_LOW_RATE_BD_IDX_8822B(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822B) & BIT_MASK_LOW_RATE_BD_IDX_8822B) - - +#define BIT_LOW_RATE_BD_IDX_8822B(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX_8822B) \ + << BIT_SHIFT_LOW_RATE_BD_IDX_8822B) +#define BITS_LOW_RATE_BD_IDX_8822B \ + (BIT_MASK_LOW_RATE_BD_IDX_8822B << BIT_SHIFT_LOW_RATE_BD_IDX_8822B) +#define BIT_CLEAR_LOW_RATE_BD_IDX_8822B(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8822B)) +#define BIT_GET_LOW_RATE_BD_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822B) & \ + BIT_MASK_LOW_RATE_BD_IDX_8822B) +#define BIT_SET_LOW_RATE_BD_IDX_8822B(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX_8822B(x) | BIT_LOW_RATE_BD_IDX_8822B(v)) /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822B */ #define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B 24 #define BIT_MASK_RX_EMPTY_TIMER_IDX_8822B 0x7 -#define BIT_RX_EMPTY_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) -#define BIT_GET_RX_EMPTY_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) - - +#define BIT_RX_EMPTY_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) +#define BITS_RX_EMPTY_TIMER_IDX_8822B \ + (BIT_MASK_RX_EMPTY_TIMER_IDX_8822B \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8822B)) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) & \ + BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) +#define BIT_SET_RX_EMPTY_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822B(x) | \ + BIT_RX_EMPTY_TIMER_IDX_8822B(v)) #define BIT_SHIFT_RX_AFULL_TH_IDX_8822B 20 #define BIT_MASK_RX_AFULL_TH_IDX_8822B 0x7 -#define BIT_RX_AFULL_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8822B) << BIT_SHIFT_RX_AFULL_TH_IDX_8822B) -#define BIT_GET_RX_AFULL_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822B) & BIT_MASK_RX_AFULL_TH_IDX_8822B) - - +#define BIT_RX_AFULL_TH_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX_8822B) \ + << BIT_SHIFT_RX_AFULL_TH_IDX_8822B) +#define BITS_RX_AFULL_TH_IDX_8822B \ + (BIT_MASK_RX_AFULL_TH_IDX_8822B << BIT_SHIFT_RX_AFULL_TH_IDX_8822B) +#define BIT_CLEAR_RX_AFULL_TH_IDX_8822B(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8822B)) +#define BIT_GET_RX_AFULL_TH_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822B) & \ + BIT_MASK_RX_AFULL_TH_IDX_8822B) +#define BIT_SET_RX_AFULL_TH_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX_8822B(x) | BIT_RX_AFULL_TH_IDX_8822B(v)) #define BIT_SHIFT_RX_HIGH_TH_IDX_8822B 16 #define BIT_MASK_RX_HIGH_TH_IDX_8822B 0x7 -#define BIT_RX_HIGH_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8822B) << BIT_SHIFT_RX_HIGH_TH_IDX_8822B) -#define BIT_GET_RX_HIGH_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822B) & BIT_MASK_RX_HIGH_TH_IDX_8822B) - - +#define BIT_RX_HIGH_TH_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX_8822B) \ + << BIT_SHIFT_RX_HIGH_TH_IDX_8822B) +#define BITS_RX_HIGH_TH_IDX_8822B \ + (BIT_MASK_RX_HIGH_TH_IDX_8822B << BIT_SHIFT_RX_HIGH_TH_IDX_8822B) +#define BIT_CLEAR_RX_HIGH_TH_IDX_8822B(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8822B)) +#define BIT_GET_RX_HIGH_TH_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822B) & \ + BIT_MASK_RX_HIGH_TH_IDX_8822B) +#define BIT_SET_RX_HIGH_TH_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX_8822B(x) | BIT_RX_HIGH_TH_IDX_8822B(v)) #define BIT_SHIFT_RX_MED_TH_IDX_8822B 12 #define BIT_MASK_RX_MED_TH_IDX_8822B 0x7 -#define BIT_RX_MED_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8822B) << BIT_SHIFT_RX_MED_TH_IDX_8822B) -#define BIT_GET_RX_MED_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822B) & BIT_MASK_RX_MED_TH_IDX_8822B) - - +#define BIT_RX_MED_TH_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX_8822B) << BIT_SHIFT_RX_MED_TH_IDX_8822B) +#define BITS_RX_MED_TH_IDX_8822B \ + (BIT_MASK_RX_MED_TH_IDX_8822B << BIT_SHIFT_RX_MED_TH_IDX_8822B) +#define BIT_CLEAR_RX_MED_TH_IDX_8822B(x) ((x) & (~BITS_RX_MED_TH_IDX_8822B)) +#define BIT_GET_RX_MED_TH_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822B) & BIT_MASK_RX_MED_TH_IDX_8822B) +#define BIT_SET_RX_MED_TH_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX_8822B(x) | BIT_RX_MED_TH_IDX_8822B(v)) #define BIT_SHIFT_RX_LOW_TH_IDX_8822B 8 #define BIT_MASK_RX_LOW_TH_IDX_8822B 0x7 -#define BIT_RX_LOW_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8822B) << BIT_SHIFT_RX_LOW_TH_IDX_8822B) -#define BIT_GET_RX_LOW_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822B) & BIT_MASK_RX_LOW_TH_IDX_8822B) - - +#define BIT_RX_LOW_TH_IDX_8822B(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX_8822B) << BIT_SHIFT_RX_LOW_TH_IDX_8822B) +#define BITS_RX_LOW_TH_IDX_8822B \ + (BIT_MASK_RX_LOW_TH_IDX_8822B << BIT_SHIFT_RX_LOW_TH_IDX_8822B) +#define BIT_CLEAR_RX_LOW_TH_IDX_8822B(x) ((x) & (~BITS_RX_LOW_TH_IDX_8822B)) +#define BIT_GET_RX_LOW_TH_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822B) & BIT_MASK_RX_LOW_TH_IDX_8822B) +#define BIT_SET_RX_LOW_TH_IDX_8822B(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX_8822B(x) | BIT_RX_LOW_TH_IDX_8822B(v)) #define BIT_SHIFT_LTR_SPACE_IDX_8822B 4 #define BIT_MASK_LTR_SPACE_IDX_8822B 0x3 -#define BIT_LTR_SPACE_IDX_8822B(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8822B) << BIT_SHIFT_LTR_SPACE_IDX_8822B) -#define BIT_GET_LTR_SPACE_IDX_8822B(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822B) & BIT_MASK_LTR_SPACE_IDX_8822B) - - +#define BIT_LTR_SPACE_IDX_8822B(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX_8822B) << BIT_SHIFT_LTR_SPACE_IDX_8822B) +#define BITS_LTR_SPACE_IDX_8822B \ + (BIT_MASK_LTR_SPACE_IDX_8822B << BIT_SHIFT_LTR_SPACE_IDX_8822B) +#define BIT_CLEAR_LTR_SPACE_IDX_8822B(x) ((x) & (~BITS_LTR_SPACE_IDX_8822B)) +#define BIT_GET_LTR_SPACE_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822B) & BIT_MASK_LTR_SPACE_IDX_8822B) +#define BIT_SET_LTR_SPACE_IDX_8822B(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX_8822B(x) | BIT_LTR_SPACE_IDX_8822B(v)) #define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B 0 #define BIT_MASK_LTR_IDLE_TIMER_IDX_8822B 0x7 -#define BIT_LTR_IDLE_TIMER_IDX_8822B(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) -#define BIT_GET_LTR_IDLE_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) - - +#define BIT_LTR_IDLE_TIMER_IDX_8822B(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) +#define BITS_LTR_IDLE_TIMER_IDX_8822B \ + (BIT_MASK_LTR_IDLE_TIMER_IDX_8822B \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822B(x) \ + ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8822B)) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8822B(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) & \ + BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) +#define BIT_SET_LTR_IDLE_TIMER_IDX_8822B(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822B(x) | \ + BIT_LTR_IDLE_TIMER_IDX_8822B(v)) /* 2 REG_LTR_IDLE_LATENCY_V1_8822B */ #define BIT_SHIFT_LTR_IDLE_L_8822B 0 #define BIT_MASK_LTR_IDLE_L_8822B 0xffffffffL -#define BIT_LTR_IDLE_L_8822B(x) (((x) & BIT_MASK_LTR_IDLE_L_8822B) << BIT_SHIFT_LTR_IDLE_L_8822B) -#define BIT_GET_LTR_IDLE_L_8822B(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8822B) & BIT_MASK_LTR_IDLE_L_8822B) - - +#define BIT_LTR_IDLE_L_8822B(x) \ + (((x) & BIT_MASK_LTR_IDLE_L_8822B) << BIT_SHIFT_LTR_IDLE_L_8822B) +#define BITS_LTR_IDLE_L_8822B \ + (BIT_MASK_LTR_IDLE_L_8822B << BIT_SHIFT_LTR_IDLE_L_8822B) +#define BIT_CLEAR_LTR_IDLE_L_8822B(x) ((x) & (~BITS_LTR_IDLE_L_8822B)) +#define BIT_GET_LTR_IDLE_L_8822B(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L_8822B) & BIT_MASK_LTR_IDLE_L_8822B) +#define BIT_SET_LTR_IDLE_L_8822B(x, v) \ + (BIT_CLEAR_LTR_IDLE_L_8822B(x) | BIT_LTR_IDLE_L_8822B(v)) /* 2 REG_LTR_ACTIVE_LATENCY_V1_8822B */ #define BIT_SHIFT_LTR_ACT_L_8822B 0 #define BIT_MASK_LTR_ACT_L_8822B 0xffffffffL -#define BIT_LTR_ACT_L_8822B(x) (((x) & BIT_MASK_LTR_ACT_L_8822B) << BIT_SHIFT_LTR_ACT_L_8822B) -#define BIT_GET_LTR_ACT_L_8822B(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8822B) & BIT_MASK_LTR_ACT_L_8822B) - - +#define BIT_LTR_ACT_L_8822B(x) \ + (((x) & BIT_MASK_LTR_ACT_L_8822B) << BIT_SHIFT_LTR_ACT_L_8822B) +#define BITS_LTR_ACT_L_8822B \ + (BIT_MASK_LTR_ACT_L_8822B << BIT_SHIFT_LTR_ACT_L_8822B) +#define BIT_CLEAR_LTR_ACT_L_8822B(x) ((x) & (~BITS_LTR_ACT_L_8822B)) +#define BIT_GET_LTR_ACT_L_8822B(x) \ + (((x) >> BIT_SHIFT_LTR_ACT_L_8822B) & BIT_MASK_LTR_ACT_L_8822B) +#define BIT_SET_LTR_ACT_L_8822B(x, v) \ + (BIT_CLEAR_LTR_ACT_L_8822B(x) | BIT_LTR_ACT_L_8822B(v)) /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B */ #define BIT_APPEND_MACID_IN_RESP_EN_8822B BIT(50) @@ -10573,10 +16980,17 @@ #define BIT_SHIFT_TRAIN_STA_ADDR_8822B 0 #define BIT_MASK_TRAIN_STA_ADDR_8822B 0xffffffffffffL -#define BIT_TRAIN_STA_ADDR_8822B(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_8822B) << BIT_SHIFT_TRAIN_STA_ADDR_8822B) -#define BIT_GET_TRAIN_STA_ADDR_8822B(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8822B) & BIT_MASK_TRAIN_STA_ADDR_8822B) - - +#define BIT_TRAIN_STA_ADDR_8822B(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_8822B) \ + << BIT_SHIFT_TRAIN_STA_ADDR_8822B) +#define BITS_TRAIN_STA_ADDR_8822B \ + (BIT_MASK_TRAIN_STA_ADDR_8822B << BIT_SHIFT_TRAIN_STA_ADDR_8822B) +#define BIT_CLEAR_TRAIN_STA_ADDR_8822B(x) ((x) & (~BITS_TRAIN_STA_ADDR_8822B)) +#define BIT_GET_TRAIN_STA_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8822B) & \ + BIT_MASK_TRAIN_STA_ADDR_8822B) +#define BIT_SET_TRAIN_STA_ADDR_8822B(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_8822B(x) | BIT_TRAIN_STA_ADDR_8822B(v)) /* 2 REG_RSVD_0X7B4_8822B */ @@ -10584,9 +16998,17 @@ #define BIT_SHIFT_PKTCNT_BSSIDMAP_8822B 4 #define BIT_MASK_PKTCNT_BSSIDMAP_8822B 0xf -#define BIT_PKTCNT_BSSIDMAP_8822B(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822B) << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) -#define BIT_GET_PKTCNT_BSSIDMAP_8822B(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) & BIT_MASK_PKTCNT_BSSIDMAP_8822B) - +#define BIT_PKTCNT_BSSIDMAP_8822B(x) \ + (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822B) \ + << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) +#define BITS_PKTCNT_BSSIDMAP_8822B \ + (BIT_MASK_PKTCNT_BSSIDMAP_8822B << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) +#define BIT_CLEAR_PKTCNT_BSSIDMAP_8822B(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8822B)) +#define BIT_GET_PKTCNT_BSSIDMAP_8822B(x) \ + (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) & \ + BIT_MASK_PKTCNT_BSSIDMAP_8822B) +#define BIT_SET_PKTCNT_BSSIDMAP_8822B(x, v) \ + (BIT_CLEAR_PKTCNT_BSSIDMAP_8822B(x) | BIT_PKTCNT_BSSIDMAP_8822B(v)) #define BIT_PKTCNT_CNTRST_8822B BIT(1) #define BIT_PKTCNT_CNTEN_8822B BIT(0) @@ -10597,54 +17019,111 @@ #define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B 0 #define BIT_MASK_WMAC_PKTCNT_CFGAD_8822B 0xff -#define BIT_WMAC_PKTCNT_CFGAD_8822B(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) -#define BIT_GET_WMAC_PKTCNT_CFGAD_8822B(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) - - +#define BIT_WMAC_PKTCNT_CFGAD_8822B(x) \ + (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) \ + << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) +#define BITS_WMAC_PKTCNT_CFGAD_8822B \ + (BIT_MASK_WMAC_PKTCNT_CFGAD_8822B << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) +#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822B(x) \ + ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8822B)) +#define BIT_GET_WMAC_PKTCNT_CFGAD_8822B(x) \ + (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) & \ + BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) +#define BIT_SET_WMAC_PKTCNT_CFGAD_8822B(x, v) \ + (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822B(x) | BIT_WMAC_PKTCNT_CFGAD_8822B(v)) /* 2 REG_IQ_DUMP_8822B */ #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B (64 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B 0xffffffffL -#define BIT_R_WMAC_MATCH_REF_MAC_8822B(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) -#define BIT_GET_R_WMAC_MATCH_REF_MAC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) - - +#define BIT_R_WMAC_MATCH_REF_MAC_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) +#define BITS_R_WMAC_MATCH_REF_MAC_8822B \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8822B(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8822B)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8822B(x) | \ + BIT_R_WMAC_MATCH_REF_MAC_8822B(v)) #define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_MASK_LA_MAC_8822B 0xffffffffL -#define BIT_R_WMAC_MASK_LA_MAC_8822B(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) -#define BIT_GET_R_WMAC_MASK_LA_MAC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) - - - -#define BIT_SHIFT_DUMP_OK_ADDR_8822B 15 -#define BIT_MASK_DUMP_OK_ADDR_8822B 0x1ffff -#define BIT_DUMP_OK_ADDR_8822B(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8822B) << BIT_SHIFT_DUMP_OK_ADDR_8822B) -#define BIT_GET_DUMP_OK_ADDR_8822B(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822B) & BIT_MASK_DUMP_OK_ADDR_8822B) - - +#define BIT_R_WMAC_MASK_LA_MAC_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) +#define BITS_R_WMAC_MASK_LA_MAC_8822B \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_8822B \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8822B(x) \ + ((x) & (~BITS_R_WMAC_MASK_LA_MAC_8822B)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) +#define BIT_SET_R_WMAC_MASK_LA_MAC_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_8822B(x) | \ + BIT_R_WMAC_MASK_LA_MAC_8822B(v)) + +#define BIT_SHIFT_DUMP_OK_ADDR_8822B 16 +#define BIT_MASK_DUMP_OK_ADDR_8822B 0xffff +#define BIT_DUMP_OK_ADDR_8822B(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR_8822B) << BIT_SHIFT_DUMP_OK_ADDR_8822B) +#define BITS_DUMP_OK_ADDR_8822B \ + (BIT_MASK_DUMP_OK_ADDR_8822B << BIT_SHIFT_DUMP_OK_ADDR_8822B) +#define BIT_CLEAR_DUMP_OK_ADDR_8822B(x) ((x) & (~BITS_DUMP_OK_ADDR_8822B)) +#define BIT_GET_DUMP_OK_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822B) & BIT_MASK_DUMP_OK_ADDR_8822B) +#define BIT_SET_DUMP_OK_ADDR_8822B(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR_8822B(x) | BIT_DUMP_OK_ADDR_8822B(v)) #define BIT_SHIFT_R_TRIG_TIME_SEL_8822B 8 #define BIT_MASK_R_TRIG_TIME_SEL_8822B 0x7f -#define BIT_R_TRIG_TIME_SEL_8822B(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8822B) << BIT_SHIFT_R_TRIG_TIME_SEL_8822B) -#define BIT_GET_R_TRIG_TIME_SEL_8822B(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822B) & BIT_MASK_R_TRIG_TIME_SEL_8822B) - - +#define BIT_R_TRIG_TIME_SEL_8822B(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL_8822B) \ + << BIT_SHIFT_R_TRIG_TIME_SEL_8822B) +#define BITS_R_TRIG_TIME_SEL_8822B \ + (BIT_MASK_R_TRIG_TIME_SEL_8822B << BIT_SHIFT_R_TRIG_TIME_SEL_8822B) +#define BIT_CLEAR_R_TRIG_TIME_SEL_8822B(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8822B)) +#define BIT_GET_R_TRIG_TIME_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822B) & \ + BIT_MASK_R_TRIG_TIME_SEL_8822B) +#define BIT_SET_R_TRIG_TIME_SEL_8822B(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL_8822B(x) | BIT_R_TRIG_TIME_SEL_8822B(v)) #define BIT_SHIFT_R_MAC_TRIG_SEL_8822B 6 #define BIT_MASK_R_MAC_TRIG_SEL_8822B 0x3 -#define BIT_R_MAC_TRIG_SEL_8822B(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8822B) << BIT_SHIFT_R_MAC_TRIG_SEL_8822B) -#define BIT_GET_R_MAC_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822B) & BIT_MASK_R_MAC_TRIG_SEL_8822B) - +#define BIT_R_MAC_TRIG_SEL_8822B(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL_8822B) \ + << BIT_SHIFT_R_MAC_TRIG_SEL_8822B) +#define BITS_R_MAC_TRIG_SEL_8822B \ + (BIT_MASK_R_MAC_TRIG_SEL_8822B << BIT_SHIFT_R_MAC_TRIG_SEL_8822B) +#define BIT_CLEAR_R_MAC_TRIG_SEL_8822B(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8822B)) +#define BIT_GET_R_MAC_TRIG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822B) & \ + BIT_MASK_R_MAC_TRIG_SEL_8822B) +#define BIT_SET_R_MAC_TRIG_SEL_8822B(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL_8822B(x) | BIT_R_MAC_TRIG_SEL_8822B(v)) #define BIT_MAC_TRIG_REG_8822B BIT(5) #define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B 3 #define BIT_MASK_R_LEVEL_PULSE_SEL_8822B 0x3 -#define BIT_R_LEVEL_PULSE_SEL_8822B(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) -#define BIT_GET_R_LEVEL_PULSE_SEL_8822B(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B) - +#define BIT_R_LEVEL_PULSE_SEL_8822B(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B) \ + << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) +#define BITS_R_LEVEL_PULSE_SEL_8822B \ + (BIT_MASK_R_LEVEL_PULSE_SEL_8822B << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8822B(x) \ + ((x) & (~BITS_R_LEVEL_PULSE_SEL_8822B)) +#define BIT_GET_R_LEVEL_PULSE_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) & \ + BIT_MASK_R_LEVEL_PULSE_SEL_8822B) +#define BIT_SET_R_LEVEL_PULSE_SEL_8822B(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL_8822B(x) | BIT_R_LEVEL_PULSE_SEL_8822B(v)) #define BIT_EN_LA_MAC_8822B BIT(2) #define BIT_R_EN_IQDUMP_8822B BIT(1) @@ -10664,16 +17143,35 @@ #define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B (64 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_RX_FIL_LEN_8822B 0xffff -#define BIT_R_WMAC_RX_FIL_LEN_8822B(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) -#define BIT_GET_R_WMAC_RX_FIL_LEN_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) - - +#define BIT_R_WMAC_RX_FIL_LEN_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) +#define BITS_R_WMAC_RX_FIL_LEN_8822B \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_8822B << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8822B(x) \ + ((x) & (~BITS_R_WMAC_RX_FIL_LEN_8822B)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) & \ + BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) +#define BIT_SET_R_WMAC_RX_FIL_LEN_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_8822B(x) | BIT_R_WMAC_RX_FIL_LEN_8822B(v)) #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B (56 & CPU_OPT_WIDTH) #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B 0xff -#define BIT_R_WMAC_RXFIFO_FULL_TH_8822B(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) -#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) - +#define BIT_R_WMAC_RXFIFO_FULL_TH_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) +#define BITS_R_WMAC_RXFIFO_FULL_TH_8822B \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8822B(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8822B)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8822B(x) | \ + BIT_R_WMAC_RXFIFO_FULL_TH_8822B(v)) #define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8822B BIT(55) #define BIT_R_WMAC_RXRST_DLY_8822B BIT(54) @@ -10702,17 +17200,27 @@ #define BIT_SHIFT_R_OFDM_LEN_8822B 26 #define BIT_MASK_R_OFDM_LEN_8822B 0x3f -#define BIT_R_OFDM_LEN_8822B(x) (((x) & BIT_MASK_R_OFDM_LEN_8822B) << BIT_SHIFT_R_OFDM_LEN_8822B) -#define BIT_GET_R_OFDM_LEN_8822B(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8822B) & BIT_MASK_R_OFDM_LEN_8822B) - - +#define BIT_R_OFDM_LEN_8822B(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_8822B) << BIT_SHIFT_R_OFDM_LEN_8822B) +#define BITS_R_OFDM_LEN_8822B \ + (BIT_MASK_R_OFDM_LEN_8822B << BIT_SHIFT_R_OFDM_LEN_8822B) +#define BIT_CLEAR_R_OFDM_LEN_8822B(x) ((x) & (~BITS_R_OFDM_LEN_8822B)) +#define BIT_GET_R_OFDM_LEN_8822B(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_8822B) & BIT_MASK_R_OFDM_LEN_8822B) +#define BIT_SET_R_OFDM_LEN_8822B(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_8822B(x) | BIT_R_OFDM_LEN_8822B(v)) #define BIT_SHIFT_R_CCK_LEN_8822B 0 #define BIT_MASK_R_CCK_LEN_8822B 0xffff -#define BIT_R_CCK_LEN_8822B(x) (((x) & BIT_MASK_R_CCK_LEN_8822B) << BIT_SHIFT_R_CCK_LEN_8822B) -#define BIT_GET_R_CCK_LEN_8822B(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8822B) & BIT_MASK_R_CCK_LEN_8822B) - - +#define BIT_R_CCK_LEN_8822B(x) \ + (((x) & BIT_MASK_R_CCK_LEN_8822B) << BIT_SHIFT_R_CCK_LEN_8822B) +#define BITS_R_CCK_LEN_8822B \ + (BIT_MASK_R_CCK_LEN_8822B << BIT_SHIFT_R_CCK_LEN_8822B) +#define BIT_CLEAR_R_CCK_LEN_8822B(x) ((x) & (~BITS_R_CCK_LEN_8822B)) +#define BIT_GET_R_CCK_LEN_8822B(x) \ + (((x) >> BIT_SHIFT_R_CCK_LEN_8822B) & BIT_MASK_R_CCK_LEN_8822B) +#define BIT_SET_R_CCK_LEN_8822B(x, v) \ + (BIT_CLEAR_R_CCK_LEN_8822B(x) | BIT_R_CCK_LEN_8822B(v)) /* 2 REG_RX_FILTER_FUNCTION_8822B */ #define BIT_R_WMAC_MHRDDY_LATCH_8822B BIT(14) @@ -10735,39 +17243,64 @@ #define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B 0 #define BIT_MASK_R_WMAC_TXNDP_SIGB_8822B 0x1fffff -#define BIT_R_WMAC_TXNDP_SIGB_8822B(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) -#define BIT_GET_R_WMAC_TXNDP_SIGB_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) - - +#define BIT_R_WMAC_TXNDP_SIGB_8822B(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) \ + << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) +#define BITS_R_WMAC_TXNDP_SIGB_8822B \ + (BIT_MASK_R_WMAC_TXNDP_SIGB_8822B << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822B(x) \ + ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8822B)) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8822B(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) & \ + BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) +#define BIT_SET_R_WMAC_TXNDP_SIGB_8822B(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822B(x) | BIT_R_WMAC_TXNDP_SIGB_8822B(v)) /* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822B */ #define BIT_SHIFT_R_MAC_DEBUG_8822B (32 & CPU_OPT_WIDTH) #define BIT_MASK_R_MAC_DEBUG_8822B 0xffffffffL -#define BIT_R_MAC_DEBUG_8822B(x) (((x) & BIT_MASK_R_MAC_DEBUG_8822B) << BIT_SHIFT_R_MAC_DEBUG_8822B) -#define BIT_GET_R_MAC_DEBUG_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_8822B) & BIT_MASK_R_MAC_DEBUG_8822B) - - +#define BIT_R_MAC_DEBUG_8822B(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_8822B) << BIT_SHIFT_R_MAC_DEBUG_8822B) +#define BITS_R_MAC_DEBUG_8822B \ + (BIT_MASK_R_MAC_DEBUG_8822B << BIT_SHIFT_R_MAC_DEBUG_8822B) +#define BIT_CLEAR_R_MAC_DEBUG_8822B(x) ((x) & (~BITS_R_MAC_DEBUG_8822B)) +#define BIT_GET_R_MAC_DEBUG_8822B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_8822B) & BIT_MASK_R_MAC_DEBUG_8822B) +#define BIT_SET_R_MAC_DEBUG_8822B(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_8822B(x) | BIT_R_MAC_DEBUG_8822B(v)) #define BIT_SHIFT_R_MAC_DBG_SHIFT_8822B 8 #define BIT_MASK_R_MAC_DBG_SHIFT_8822B 0x7 -#define BIT_R_MAC_DBG_SHIFT_8822B(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822B) << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) -#define BIT_GET_R_MAC_DBG_SHIFT_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) & BIT_MASK_R_MAC_DBG_SHIFT_8822B) - - +#define BIT_R_MAC_DBG_SHIFT_8822B(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822B) \ + << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) +#define BITS_R_MAC_DBG_SHIFT_8822B \ + (BIT_MASK_R_MAC_DBG_SHIFT_8822B << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) +#define BIT_CLEAR_R_MAC_DBG_SHIFT_8822B(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8822B)) +#define BIT_GET_R_MAC_DBG_SHIFT_8822B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) & \ + BIT_MASK_R_MAC_DBG_SHIFT_8822B) +#define BIT_SET_R_MAC_DBG_SHIFT_8822B(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT_8822B(x) | BIT_R_MAC_DBG_SHIFT_8822B(v)) #define BIT_SHIFT_R_MAC_DBG_SEL_8822B 0 #define BIT_MASK_R_MAC_DBG_SEL_8822B 0x3 -#define BIT_R_MAC_DBG_SEL_8822B(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8822B) << BIT_SHIFT_R_MAC_DBG_SEL_8822B) -#define BIT_GET_R_MAC_DBG_SEL_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822B) & BIT_MASK_R_MAC_DBG_SEL_8822B) - - +#define BIT_R_MAC_DBG_SEL_8822B(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL_8822B) << BIT_SHIFT_R_MAC_DBG_SEL_8822B) +#define BITS_R_MAC_DBG_SEL_8822B \ + (BIT_MASK_R_MAC_DBG_SEL_8822B << BIT_SHIFT_R_MAC_DBG_SEL_8822B) +#define BIT_CLEAR_R_MAC_DBG_SEL_8822B(x) ((x) & (~BITS_R_MAC_DBG_SEL_8822B)) +#define BIT_GET_R_MAC_DBG_SEL_8822B(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822B) & BIT_MASK_R_MAC_DBG_SEL_8822B) +#define BIT_SET_R_MAC_DBG_SEL_8822B(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL_8822B(x) | BIT_R_MAC_DBG_SEL_8822B(v)) /* 2 REG_RTS_ADDRESS_0_8822B */ /* 2 REG_RTS_ADDRESS_1_8822B */ -/* 2 REG__RPFM_MAP1_8822B (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 1 */ +/* 2 REG_RPFM_MAP1_8822B */ #define BIT_DATA_RPFM15EN_8822B BIT(15) #define BIT_DATA_RPFM14EN_8822B BIT(14) #define BIT_DATA_RPFM13EN_8822B BIT(13) @@ -10792,35 +17325,69 @@ #define BIT_SHIFT_WRITE_BYTE_EN_V1_8822B 16 #define BIT_MASK_WRITE_BYTE_EN_V1_8822B 0xf -#define BIT_WRITE_BYTE_EN_V1_8822B(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822B) << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) -#define BIT_GET_WRITE_BYTE_EN_V1_8822B(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) & BIT_MASK_WRITE_BYTE_EN_V1_8822B) - - +#define BIT_WRITE_BYTE_EN_V1_8822B(x) \ + (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822B) \ + << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) +#define BITS_WRITE_BYTE_EN_V1_8822B \ + (BIT_MASK_WRITE_BYTE_EN_V1_8822B << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) +#define BIT_CLEAR_WRITE_BYTE_EN_V1_8822B(x) \ + ((x) & (~BITS_WRITE_BYTE_EN_V1_8822B)) +#define BIT_GET_WRITE_BYTE_EN_V1_8822B(x) \ + (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) & \ + BIT_MASK_WRITE_BYTE_EN_V1_8822B) +#define BIT_SET_WRITE_BYTE_EN_V1_8822B(x, v) \ + (BIT_CLEAR_WRITE_BYTE_EN_V1_8822B(x) | BIT_WRITE_BYTE_EN_V1_8822B(v)) #define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B 0 #define BIT_MASK_LTECOEX_REG_ADDR_V1_8822B 0xffff -#define BIT_LTECOEX_REG_ADDR_V1_8822B(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) -#define BIT_GET_LTECOEX_REG_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) - - +#define BIT_LTECOEX_REG_ADDR_V1_8822B(x) \ + (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) +#define BITS_LTECOEX_REG_ADDR_V1_8822B \ + (BIT_MASK_LTECOEX_REG_ADDR_V1_8822B \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) +#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822B(x) \ + ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8822B)) +#define BIT_GET_LTECOEX_REG_ADDR_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) & \ + BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) +#define BIT_SET_LTECOEX_REG_ADDR_V1_8822B(x, v) \ + (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822B(x) | \ + BIT_LTECOEX_REG_ADDR_V1_8822B(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B */ #define BIT_SHIFT_LTECOEX_W_DATA_V1_8822B 0 #define BIT_MASK_LTECOEX_W_DATA_V1_8822B 0xffffffffL -#define BIT_LTECOEX_W_DATA_V1_8822B(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822B) << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) -#define BIT_GET_LTECOEX_W_DATA_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) & BIT_MASK_LTECOEX_W_DATA_V1_8822B) - - +#define BIT_LTECOEX_W_DATA_V1_8822B(x) \ + (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822B) \ + << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) +#define BITS_LTECOEX_W_DATA_V1_8822B \ + (BIT_MASK_LTECOEX_W_DATA_V1_8822B << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) +#define BIT_CLEAR_LTECOEX_W_DATA_V1_8822B(x) \ + ((x) & (~BITS_LTECOEX_W_DATA_V1_8822B)) +#define BIT_GET_LTECOEX_W_DATA_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) & \ + BIT_MASK_LTECOEX_W_DATA_V1_8822B) +#define BIT_SET_LTECOEX_W_DATA_V1_8822B(x, v) \ + (BIT_CLEAR_LTECOEX_W_DATA_V1_8822B(x) | BIT_LTECOEX_W_DATA_V1_8822B(v)) /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B */ #define BIT_SHIFT_LTECOEX_R_DATA_V1_8822B 0 #define BIT_MASK_LTECOEX_R_DATA_V1_8822B 0xffffffffL -#define BIT_LTECOEX_R_DATA_V1_8822B(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822B) << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) -#define BIT_GET_LTECOEX_R_DATA_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) & BIT_MASK_LTECOEX_R_DATA_V1_8822B) - - +#define BIT_LTECOEX_R_DATA_V1_8822B(x) \ + (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822B) \ + << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) +#define BITS_LTECOEX_R_DATA_V1_8822B \ + (BIT_MASK_LTECOEX_R_DATA_V1_8822B << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) +#define BIT_CLEAR_LTECOEX_R_DATA_V1_8822B(x) \ + ((x) & (~BITS_LTECOEX_R_DATA_V1_8822B)) +#define BIT_GET_LTECOEX_R_DATA_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) & \ + BIT_MASK_LTECOEX_R_DATA_V1_8822B) +#define BIT_SET_LTECOEX_R_DATA_V1_8822B(x, v) \ + (BIT_CLEAR_LTECOEX_R_DATA_V1_8822B(x) | BIT_LTECOEX_R_DATA_V1_8822B(v)) /* 2 REG_NOT_VALID_8822B */ @@ -10828,16 +17395,26 @@ #define BIT_SHIFT_SDIO_INT_TIMEOUT_8822B 16 #define BIT_MASK_SDIO_INT_TIMEOUT_8822B 0xffff -#define BIT_SDIO_INT_TIMEOUT_8822B(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822B) << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) -#define BIT_GET_SDIO_INT_TIMEOUT_8822B(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) & BIT_MASK_SDIO_INT_TIMEOUT_8822B) - +#define BIT_SDIO_INT_TIMEOUT_8822B(x) \ + (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822B) \ + << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) +#define BITS_SDIO_INT_TIMEOUT_8822B \ + (BIT_MASK_SDIO_INT_TIMEOUT_8822B << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) +#define BIT_CLEAR_SDIO_INT_TIMEOUT_8822B(x) \ + ((x) & (~BITS_SDIO_INT_TIMEOUT_8822B)) +#define BIT_GET_SDIO_INT_TIMEOUT_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) & \ + BIT_MASK_SDIO_INT_TIMEOUT_8822B) +#define BIT_SET_SDIO_INT_TIMEOUT_8822B(x, v) \ + (BIT_CLEAR_SDIO_INT_TIMEOUT_8822B(x) | BIT_SDIO_INT_TIMEOUT_8822B(v)) #define BIT_IO_ERR_STATUS_8822B BIT(15) #define BIT_REPLY_ERRCRC_IN_DATA_8822B BIT(9) #define BIT_EN_CMD53_OVERLAP_8822B BIT(8) #define BIT_REPLY_ERR_IN_R5_8822B BIT(7) #define BIT_R18A_EN_8822B BIT(6) -#define BIT_INIT_CMD_EN_8822B BIT(5) +#define BIT_SDIO_CMD_FORCE_VLD_8822B BIT(5) +#define BIT_INIT_CMD_EN_8822B BIT(4) #define BIT_EN_RXDMA_MASK_INT_8822B BIT(2) #define BIT_EN_MASK_TIMER_8822B BIT(1) #define BIT_CMD_ERR_STOP_INT_EN_8822B BIT(0) @@ -10898,95 +17475,155 @@ #define BIT_SHIFT_RX_REQ_LEN_V1_8822B 0 #define BIT_MASK_RX_REQ_LEN_V1_8822B 0x3ffff -#define BIT_RX_REQ_LEN_V1_8822B(x) (((x) & BIT_MASK_RX_REQ_LEN_V1_8822B) << BIT_SHIFT_RX_REQ_LEN_V1_8822B) -#define BIT_GET_RX_REQ_LEN_V1_8822B(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822B) & BIT_MASK_RX_REQ_LEN_V1_8822B) - - +#define BIT_RX_REQ_LEN_V1_8822B(x) \ + (((x) & BIT_MASK_RX_REQ_LEN_V1_8822B) << BIT_SHIFT_RX_REQ_LEN_V1_8822B) +#define BITS_RX_REQ_LEN_V1_8822B \ + (BIT_MASK_RX_REQ_LEN_V1_8822B << BIT_SHIFT_RX_REQ_LEN_V1_8822B) +#define BIT_CLEAR_RX_REQ_LEN_V1_8822B(x) ((x) & (~BITS_RX_REQ_LEN_V1_8822B)) +#define BIT_GET_RX_REQ_LEN_V1_8822B(x) \ + (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822B) & BIT_MASK_RX_REQ_LEN_V1_8822B) +#define BIT_SET_RX_REQ_LEN_V1_8822B(x, v) \ + (BIT_CLEAR_RX_REQ_LEN_V1_8822B(x) | BIT_RX_REQ_LEN_V1_8822B(v)) /* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822B */ #define BIT_SHIFT_FREE_TXPG_SEQ_8822B 0 #define BIT_MASK_FREE_TXPG_SEQ_8822B 0xff -#define BIT_FREE_TXPG_SEQ_8822B(x) (((x) & BIT_MASK_FREE_TXPG_SEQ_8822B) << BIT_SHIFT_FREE_TXPG_SEQ_8822B) -#define BIT_GET_FREE_TXPG_SEQ_8822B(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822B) & BIT_MASK_FREE_TXPG_SEQ_8822B) - - +#define BIT_FREE_TXPG_SEQ_8822B(x) \ + (((x) & BIT_MASK_FREE_TXPG_SEQ_8822B) << BIT_SHIFT_FREE_TXPG_SEQ_8822B) +#define BITS_FREE_TXPG_SEQ_8822B \ + (BIT_MASK_FREE_TXPG_SEQ_8822B << BIT_SHIFT_FREE_TXPG_SEQ_8822B) +#define BIT_CLEAR_FREE_TXPG_SEQ_8822B(x) ((x) & (~BITS_FREE_TXPG_SEQ_8822B)) +#define BIT_GET_FREE_TXPG_SEQ_8822B(x) \ + (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822B) & BIT_MASK_FREE_TXPG_SEQ_8822B) +#define BIT_SET_FREE_TXPG_SEQ_8822B(x, v) \ + (BIT_CLEAR_FREE_TXPG_SEQ_8822B(x) | BIT_FREE_TXPG_SEQ_8822B(v)) /* 2 REG_SDIO_FREE_TXPG_8822B */ #define BIT_SHIFT_MID_FREEPG_V1_8822B 16 #define BIT_MASK_MID_FREEPG_V1_8822B 0xfff -#define BIT_MID_FREEPG_V1_8822B(x) (((x) & BIT_MASK_MID_FREEPG_V1_8822B) << BIT_SHIFT_MID_FREEPG_V1_8822B) -#define BIT_GET_MID_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8822B) & BIT_MASK_MID_FREEPG_V1_8822B) - - +#define BIT_MID_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_MID_FREEPG_V1_8822B) << BIT_SHIFT_MID_FREEPG_V1_8822B) +#define BITS_MID_FREEPG_V1_8822B \ + (BIT_MASK_MID_FREEPG_V1_8822B << BIT_SHIFT_MID_FREEPG_V1_8822B) +#define BIT_CLEAR_MID_FREEPG_V1_8822B(x) ((x) & (~BITS_MID_FREEPG_V1_8822B)) +#define BIT_GET_MID_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_MID_FREEPG_V1_8822B) & BIT_MASK_MID_FREEPG_V1_8822B) +#define BIT_SET_MID_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_MID_FREEPG_V1_8822B(x) | BIT_MID_FREEPG_V1_8822B(v)) #define BIT_SHIFT_HIQ_FREEPG_V1_8822B 0 #define BIT_MASK_HIQ_FREEPG_V1_8822B 0xfff -#define BIT_HIQ_FREEPG_V1_8822B(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8822B) << BIT_SHIFT_HIQ_FREEPG_V1_8822B) -#define BIT_GET_HIQ_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822B) & BIT_MASK_HIQ_FREEPG_V1_8822B) - - +#define BIT_HIQ_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_HIQ_FREEPG_V1_8822B) << BIT_SHIFT_HIQ_FREEPG_V1_8822B) +#define BITS_HIQ_FREEPG_V1_8822B \ + (BIT_MASK_HIQ_FREEPG_V1_8822B << BIT_SHIFT_HIQ_FREEPG_V1_8822B) +#define BIT_CLEAR_HIQ_FREEPG_V1_8822B(x) ((x) & (~BITS_HIQ_FREEPG_V1_8822B)) +#define BIT_GET_HIQ_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822B) & BIT_MASK_HIQ_FREEPG_V1_8822B) +#define BIT_SET_HIQ_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_HIQ_FREEPG_V1_8822B(x) | BIT_HIQ_FREEPG_V1_8822B(v)) /* 2 REG_SDIO_FREE_TXPG2_8822B */ #define BIT_SHIFT_PUB_FREEPG_V1_8822B 16 #define BIT_MASK_PUB_FREEPG_V1_8822B 0xfff -#define BIT_PUB_FREEPG_V1_8822B(x) (((x) & BIT_MASK_PUB_FREEPG_V1_8822B) << BIT_SHIFT_PUB_FREEPG_V1_8822B) -#define BIT_GET_PUB_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822B) & BIT_MASK_PUB_FREEPG_V1_8822B) - - +#define BIT_PUB_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_PUB_FREEPG_V1_8822B) << BIT_SHIFT_PUB_FREEPG_V1_8822B) +#define BITS_PUB_FREEPG_V1_8822B \ + (BIT_MASK_PUB_FREEPG_V1_8822B << BIT_SHIFT_PUB_FREEPG_V1_8822B) +#define BIT_CLEAR_PUB_FREEPG_V1_8822B(x) ((x) & (~BITS_PUB_FREEPG_V1_8822B)) +#define BIT_GET_PUB_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822B) & BIT_MASK_PUB_FREEPG_V1_8822B) +#define BIT_SET_PUB_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_PUB_FREEPG_V1_8822B(x) | BIT_PUB_FREEPG_V1_8822B(v)) #define BIT_SHIFT_LOW_FREEPG_V1_8822B 0 #define BIT_MASK_LOW_FREEPG_V1_8822B 0xfff -#define BIT_LOW_FREEPG_V1_8822B(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8822B) << BIT_SHIFT_LOW_FREEPG_V1_8822B) -#define BIT_GET_LOW_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822B) & BIT_MASK_LOW_FREEPG_V1_8822B) - - +#define BIT_LOW_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_LOW_FREEPG_V1_8822B) << BIT_SHIFT_LOW_FREEPG_V1_8822B) +#define BITS_LOW_FREEPG_V1_8822B \ + (BIT_MASK_LOW_FREEPG_V1_8822B << BIT_SHIFT_LOW_FREEPG_V1_8822B) +#define BIT_CLEAR_LOW_FREEPG_V1_8822B(x) ((x) & (~BITS_LOW_FREEPG_V1_8822B)) +#define BIT_GET_LOW_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822B) & BIT_MASK_LOW_FREEPG_V1_8822B) +#define BIT_SET_LOW_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_LOW_FREEPG_V1_8822B(x) | BIT_LOW_FREEPG_V1_8822B(v)) /* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822B */ #define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B 24 #define BIT_MASK_NOAC_OQT_FREEPG_V1_8822B 0xff -#define BIT_NOAC_OQT_FREEPG_V1_8822B(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) -#define BIT_GET_NOAC_OQT_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) - - +#define BIT_NOAC_OQT_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) +#define BITS_NOAC_OQT_FREEPG_V1_8822B \ + (BIT_MASK_NOAC_OQT_FREEPG_V1_8822B \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) +#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822B(x) \ + ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8822B)) +#define BIT_GET_NOAC_OQT_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) & \ + BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) +#define BIT_SET_NOAC_OQT_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822B(x) | \ + BIT_NOAC_OQT_FREEPG_V1_8822B(v)) #define BIT_SHIFT_AC_OQT_FREEPG_V1_8822B 16 #define BIT_MASK_AC_OQT_FREEPG_V1_8822B 0xff -#define BIT_AC_OQT_FREEPG_V1_8822B(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822B) << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) -#define BIT_GET_AC_OQT_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) & BIT_MASK_AC_OQT_FREEPG_V1_8822B) - - +#define BIT_AC_OQT_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822B) \ + << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) +#define BITS_AC_OQT_FREEPG_V1_8822B \ + (BIT_MASK_AC_OQT_FREEPG_V1_8822B << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) +#define BIT_CLEAR_AC_OQT_FREEPG_V1_8822B(x) \ + ((x) & (~BITS_AC_OQT_FREEPG_V1_8822B)) +#define BIT_GET_AC_OQT_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) & \ + BIT_MASK_AC_OQT_FREEPG_V1_8822B) +#define BIT_SET_AC_OQT_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_AC_OQT_FREEPG_V1_8822B(x) | BIT_AC_OQT_FREEPG_V1_8822B(v)) #define BIT_SHIFT_EXQ_FREEPG_V1_8822B 0 #define BIT_MASK_EXQ_FREEPG_V1_8822B 0xfff -#define BIT_EXQ_FREEPG_V1_8822B(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8822B) << BIT_SHIFT_EXQ_FREEPG_V1_8822B) -#define BIT_GET_EXQ_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822B) & BIT_MASK_EXQ_FREEPG_V1_8822B) - - +#define BIT_EXQ_FREEPG_V1_8822B(x) \ + (((x) & BIT_MASK_EXQ_FREEPG_V1_8822B) << BIT_SHIFT_EXQ_FREEPG_V1_8822B) +#define BITS_EXQ_FREEPG_V1_8822B \ + (BIT_MASK_EXQ_FREEPG_V1_8822B << BIT_SHIFT_EXQ_FREEPG_V1_8822B) +#define BIT_CLEAR_EXQ_FREEPG_V1_8822B(x) ((x) & (~BITS_EXQ_FREEPG_V1_8822B)) +#define BIT_GET_EXQ_FREEPG_V1_8822B(x) \ + (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822B) & BIT_MASK_EXQ_FREEPG_V1_8822B) +#define BIT_SET_EXQ_FREEPG_V1_8822B(x, v) \ + (BIT_CLEAR_EXQ_FREEPG_V1_8822B(x) | BIT_EXQ_FREEPG_V1_8822B(v)) /* 2 REG_SDIO_HTSFR_INFO_8822B */ #define BIT_SHIFT_HTSFR1_8822B 16 #define BIT_MASK_HTSFR1_8822B 0xffff -#define BIT_HTSFR1_8822B(x) (((x) & BIT_MASK_HTSFR1_8822B) << BIT_SHIFT_HTSFR1_8822B) -#define BIT_GET_HTSFR1_8822B(x) (((x) >> BIT_SHIFT_HTSFR1_8822B) & BIT_MASK_HTSFR1_8822B) - - +#define BIT_HTSFR1_8822B(x) \ + (((x) & BIT_MASK_HTSFR1_8822B) << BIT_SHIFT_HTSFR1_8822B) +#define BITS_HTSFR1_8822B (BIT_MASK_HTSFR1_8822B << BIT_SHIFT_HTSFR1_8822B) +#define BIT_CLEAR_HTSFR1_8822B(x) ((x) & (~BITS_HTSFR1_8822B)) +#define BIT_GET_HTSFR1_8822B(x) \ + (((x) >> BIT_SHIFT_HTSFR1_8822B) & BIT_MASK_HTSFR1_8822B) +#define BIT_SET_HTSFR1_8822B(x, v) \ + (BIT_CLEAR_HTSFR1_8822B(x) | BIT_HTSFR1_8822B(v)) #define BIT_SHIFT_HTSFR0_8822B 0 #define BIT_MASK_HTSFR0_8822B 0xffff -#define BIT_HTSFR0_8822B(x) (((x) & BIT_MASK_HTSFR0_8822B) << BIT_SHIFT_HTSFR0_8822B) -#define BIT_GET_HTSFR0_8822B(x) (((x) >> BIT_SHIFT_HTSFR0_8822B) & BIT_MASK_HTSFR0_8822B) - - +#define BIT_HTSFR0_8822B(x) \ + (((x) & BIT_MASK_HTSFR0_8822B) << BIT_SHIFT_HTSFR0_8822B) +#define BITS_HTSFR0_8822B (BIT_MASK_HTSFR0_8822B << BIT_SHIFT_HTSFR0_8822B) +#define BIT_CLEAR_HTSFR0_8822B(x) ((x) & (~BITS_HTSFR0_8822B)) +#define BIT_GET_HTSFR0_8822B(x) \ + (((x) >> BIT_SHIFT_HTSFR0_8822B) & BIT_MASK_HTSFR0_8822B) +#define BIT_SET_HTSFR0_8822B(x, v) \ + (BIT_CLEAR_HTSFR0_8822B(x) | BIT_HTSFR0_8822B(v)) /* 2 REG_SDIO_HCPWM1_V2_8822B */ -#define BIT_TOGGLING_8822B BIT(7) -#define BIT_ACK_8822B BIT(6) -#define BIT_SYS_CLK_8822B BIT(0) +#define BIT_TOGGLE_8822B BIT(7) +#define BIT_CUR_PS_8822B BIT(0) /* 2 REG_SDIO_HCPWM2_V2_8822B */ @@ -10997,49 +17634,83 @@ #define BIT_SHIFT_INDIRECT_REG_SIZE_8822B 16 #define BIT_MASK_INDIRECT_REG_SIZE_8822B 0x3 -#define BIT_INDIRECT_REG_SIZE_8822B(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE_8822B) << BIT_SHIFT_INDIRECT_REG_SIZE_8822B) -#define BIT_GET_INDIRECT_REG_SIZE_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822B) & BIT_MASK_INDIRECT_REG_SIZE_8822B) - - +#define BIT_INDIRECT_REG_SIZE_8822B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_SIZE_8822B) \ + << BIT_SHIFT_INDIRECT_REG_SIZE_8822B) +#define BITS_INDIRECT_REG_SIZE_8822B \ + (BIT_MASK_INDIRECT_REG_SIZE_8822B << BIT_SHIFT_INDIRECT_REG_SIZE_8822B) +#define BIT_CLEAR_INDIRECT_REG_SIZE_8822B(x) \ + ((x) & (~BITS_INDIRECT_REG_SIZE_8822B)) +#define BIT_GET_INDIRECT_REG_SIZE_8822B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822B) & \ + BIT_MASK_INDIRECT_REG_SIZE_8822B) +#define BIT_SET_INDIRECT_REG_SIZE_8822B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_SIZE_8822B(x) | BIT_INDIRECT_REG_SIZE_8822B(v)) #define BIT_SHIFT_INDIRECT_REG_ADDR_8822B 0 #define BIT_MASK_INDIRECT_REG_ADDR_8822B 0xffff -#define BIT_INDIRECT_REG_ADDR_8822B(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8822B) << BIT_SHIFT_INDIRECT_REG_ADDR_8822B) -#define BIT_GET_INDIRECT_REG_ADDR_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822B) & BIT_MASK_INDIRECT_REG_ADDR_8822B) - - +#define BIT_INDIRECT_REG_ADDR_8822B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_ADDR_8822B) \ + << BIT_SHIFT_INDIRECT_REG_ADDR_8822B) +#define BITS_INDIRECT_REG_ADDR_8822B \ + (BIT_MASK_INDIRECT_REG_ADDR_8822B << BIT_SHIFT_INDIRECT_REG_ADDR_8822B) +#define BIT_CLEAR_INDIRECT_REG_ADDR_8822B(x) \ + ((x) & (~BITS_INDIRECT_REG_ADDR_8822B)) +#define BIT_GET_INDIRECT_REG_ADDR_8822B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822B) & \ + BIT_MASK_INDIRECT_REG_ADDR_8822B) +#define BIT_SET_INDIRECT_REG_ADDR_8822B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_ADDR_8822B(x) | BIT_INDIRECT_REG_ADDR_8822B(v)) /* 2 REG_SDIO_INDIRECT_REG_DATA_8822B */ #define BIT_SHIFT_INDIRECT_REG_DATA_8822B 0 #define BIT_MASK_INDIRECT_REG_DATA_8822B 0xffffffffL -#define BIT_INDIRECT_REG_DATA_8822B(x) (((x) & BIT_MASK_INDIRECT_REG_DATA_8822B) << BIT_SHIFT_INDIRECT_REG_DATA_8822B) -#define BIT_GET_INDIRECT_REG_DATA_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822B) & BIT_MASK_INDIRECT_REG_DATA_8822B) - - +#define BIT_INDIRECT_REG_DATA_8822B(x) \ + (((x) & BIT_MASK_INDIRECT_REG_DATA_8822B) \ + << BIT_SHIFT_INDIRECT_REG_DATA_8822B) +#define BITS_INDIRECT_REG_DATA_8822B \ + (BIT_MASK_INDIRECT_REG_DATA_8822B << BIT_SHIFT_INDIRECT_REG_DATA_8822B) +#define BIT_CLEAR_INDIRECT_REG_DATA_8822B(x) \ + ((x) & (~BITS_INDIRECT_REG_DATA_8822B)) +#define BIT_GET_INDIRECT_REG_DATA_8822B(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822B) & \ + BIT_MASK_INDIRECT_REG_DATA_8822B) +#define BIT_SET_INDIRECT_REG_DATA_8822B(x, v) \ + (BIT_CLEAR_INDIRECT_REG_DATA_8822B(x) | BIT_INDIRECT_REG_DATA_8822B(v)) /* 2 REG_SDIO_H2C_8822B */ #define BIT_SHIFT_SDIO_H2C_MSG_8822B 0 #define BIT_MASK_SDIO_H2C_MSG_8822B 0xffffffffL -#define BIT_SDIO_H2C_MSG_8822B(x) (((x) & BIT_MASK_SDIO_H2C_MSG_8822B) << BIT_SHIFT_SDIO_H2C_MSG_8822B) -#define BIT_GET_SDIO_H2C_MSG_8822B(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822B) & BIT_MASK_SDIO_H2C_MSG_8822B) - - +#define BIT_SDIO_H2C_MSG_8822B(x) \ + (((x) & BIT_MASK_SDIO_H2C_MSG_8822B) << BIT_SHIFT_SDIO_H2C_MSG_8822B) +#define BITS_SDIO_H2C_MSG_8822B \ + (BIT_MASK_SDIO_H2C_MSG_8822B << BIT_SHIFT_SDIO_H2C_MSG_8822B) +#define BIT_CLEAR_SDIO_H2C_MSG_8822B(x) ((x) & (~BITS_SDIO_H2C_MSG_8822B)) +#define BIT_GET_SDIO_H2C_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822B) & BIT_MASK_SDIO_H2C_MSG_8822B) +#define BIT_SET_SDIO_H2C_MSG_8822B(x, v) \ + (BIT_CLEAR_SDIO_H2C_MSG_8822B(x) | BIT_SDIO_H2C_MSG_8822B(v)) /* 2 REG_SDIO_C2H_8822B */ #define BIT_SHIFT_SDIO_C2H_MSG_8822B 0 #define BIT_MASK_SDIO_C2H_MSG_8822B 0xffffffffL -#define BIT_SDIO_C2H_MSG_8822B(x) (((x) & BIT_MASK_SDIO_C2H_MSG_8822B) << BIT_SHIFT_SDIO_C2H_MSG_8822B) -#define BIT_GET_SDIO_C2H_MSG_8822B(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822B) & BIT_MASK_SDIO_C2H_MSG_8822B) - - +#define BIT_SDIO_C2H_MSG_8822B(x) \ + (((x) & BIT_MASK_SDIO_C2H_MSG_8822B) << BIT_SHIFT_SDIO_C2H_MSG_8822B) +#define BITS_SDIO_C2H_MSG_8822B \ + (BIT_MASK_SDIO_C2H_MSG_8822B << BIT_SHIFT_SDIO_C2H_MSG_8822B) +#define BIT_CLEAR_SDIO_C2H_MSG_8822B(x) ((x) & (~BITS_SDIO_C2H_MSG_8822B)) +#define BIT_GET_SDIO_C2H_MSG_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822B) & BIT_MASK_SDIO_C2H_MSG_8822B) +#define BIT_SET_SDIO_C2H_MSG_8822B(x, v) \ + (BIT_CLEAR_SDIO_C2H_MSG_8822B(x) | BIT_SDIO_C2H_MSG_8822B(v)) /* 2 REG_SDIO_HRPWM1_8822B */ -#define BIT_TOGGLING_8822B BIT(7) +#define BIT_TOGGLE_8822B BIT(7) #define BIT_ACK_8822B BIT(6) -#define BIT_32K_PERMISSION_8822B BIT(0) +#define BIT_REQ_PS_8822B BIT(0) /* 2 REG_SDIO_HRPWM2_8822B */ @@ -11062,27 +17733,39 @@ #define BIT_SHIFT_CMDIN_2RESP_TIMER_8822B 0 #define BIT_MASK_CMDIN_2RESP_TIMER_8822B 0xffff -#define BIT_CMDIN_2RESP_TIMER_8822B(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822B) << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) -#define BIT_GET_CMDIN_2RESP_TIMER_8822B(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) & BIT_MASK_CMDIN_2RESP_TIMER_8822B) - - +#define BIT_CMDIN_2RESP_TIMER_8822B(x) \ + (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822B) \ + << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) +#define BITS_CMDIN_2RESP_TIMER_8822B \ + (BIT_MASK_CMDIN_2RESP_TIMER_8822B << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) +#define BIT_CLEAR_CMDIN_2RESP_TIMER_8822B(x) \ + ((x) & (~BITS_CMDIN_2RESP_TIMER_8822B)) +#define BIT_GET_CMDIN_2RESP_TIMER_8822B(x) \ + (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) & \ + BIT_MASK_CMDIN_2RESP_TIMER_8822B) +#define BIT_SET_CMDIN_2RESP_TIMER_8822B(x, v) \ + (BIT_CLEAR_CMDIN_2RESP_TIMER_8822B(x) | BIT_CMDIN_2RESP_TIMER_8822B(v)) /* 2 REG_SDIO_CMD_CRC_8822B */ #define BIT_SHIFT_SDIO_CMD_CRC_V1_8822B 0 #define BIT_MASK_SDIO_CMD_CRC_V1_8822B 0xff -#define BIT_SDIO_CMD_CRC_V1_8822B(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822B) << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) -#define BIT_GET_SDIO_CMD_CRC_V1_8822B(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) & BIT_MASK_SDIO_CMD_CRC_V1_8822B) - - +#define BIT_SDIO_CMD_CRC_V1_8822B(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822B) \ + << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) +#define BITS_SDIO_CMD_CRC_V1_8822B \ + (BIT_MASK_SDIO_CMD_CRC_V1_8822B << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) +#define BIT_CLEAR_SDIO_CMD_CRC_V1_8822B(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8822B)) +#define BIT_GET_SDIO_CMD_CRC_V1_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) & \ + BIT_MASK_SDIO_CMD_CRC_V1_8822B) +#define BIT_SET_SDIO_CMD_CRC_V1_8822B(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC_V1_8822B(x) | BIT_SDIO_CMD_CRC_V1_8822B(v)) /* 2 REG_SDIO_HSISR_8822B */ #define BIT_DRV_WLAN_INT_CLR_8822B BIT(1) #define BIT_DRV_WLAN_INT_8822B BIT(0) -/* 2 REG_SDIO_HSIMR_8822B */ -#define BIT_HISR_MASK_8822B BIT(0) - /* 2 REG_SDIO_ERR_RPT_8822B */ #define BIT_HR_FF_OVF_8822B BIT(6) #define BIT_HR_FF_UDN_8822B BIT(5) @@ -11096,28 +17779,53 @@ #define BIT_SHIFT_CMD_CRC_ERR_CNT_8822B 0 #define BIT_MASK_CMD_CRC_ERR_CNT_8822B 0xff -#define BIT_CMD_CRC_ERR_CNT_8822B(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822B) << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) -#define BIT_GET_CMD_CRC_ERR_CNT_8822B(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) & BIT_MASK_CMD_CRC_ERR_CNT_8822B) - - +#define BIT_CMD_CRC_ERR_CNT_8822B(x) \ + (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822B) \ + << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) +#define BITS_CMD_CRC_ERR_CNT_8822B \ + (BIT_MASK_CMD_CRC_ERR_CNT_8822B << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) +#define BIT_CLEAR_CMD_CRC_ERR_CNT_8822B(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8822B)) +#define BIT_GET_CMD_CRC_ERR_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) & \ + BIT_MASK_CMD_CRC_ERR_CNT_8822B) +#define BIT_SET_CMD_CRC_ERR_CNT_8822B(x, v) \ + (BIT_CLEAR_CMD_CRC_ERR_CNT_8822B(x) | BIT_CMD_CRC_ERR_CNT_8822B(v)) /* 2 REG_SDIO_DATA_ERRCNT_8822B */ #define BIT_SHIFT_DATA_CRC_ERR_CNT_8822B 0 #define BIT_MASK_DATA_CRC_ERR_CNT_8822B 0xff -#define BIT_DATA_CRC_ERR_CNT_8822B(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822B) << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) -#define BIT_GET_DATA_CRC_ERR_CNT_8822B(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) & BIT_MASK_DATA_CRC_ERR_CNT_8822B) - - +#define BIT_DATA_CRC_ERR_CNT_8822B(x) \ + (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822B) \ + << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) +#define BITS_DATA_CRC_ERR_CNT_8822B \ + (BIT_MASK_DATA_CRC_ERR_CNT_8822B << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) +#define BIT_CLEAR_DATA_CRC_ERR_CNT_8822B(x) \ + ((x) & (~BITS_DATA_CRC_ERR_CNT_8822B)) +#define BIT_GET_DATA_CRC_ERR_CNT_8822B(x) \ + (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) & \ + BIT_MASK_DATA_CRC_ERR_CNT_8822B) +#define BIT_SET_DATA_CRC_ERR_CNT_8822B(x, v) \ + (BIT_CLEAR_DATA_CRC_ERR_CNT_8822B(x) | BIT_DATA_CRC_ERR_CNT_8822B(v)) /* 2 REG_SDIO_CMD_ERR_CONTENT_8822B */ #define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B 0 #define BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B 0xffffffffffL -#define BIT_SDIO_CMD_ERR_CONTENT_8822B(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) -#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822B(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) - - +#define BIT_SDIO_CMD_ERR_CONTENT_8822B(x) \ + (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) +#define BITS_SDIO_CMD_ERR_CONTENT_8822B \ + (BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) +#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822B(x) \ + ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8822B)) +#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) & \ + BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) +#define BIT_SET_SDIO_CMD_ERR_CONTENT_8822B(x, v) \ + (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822B(x) | \ + BIT_SDIO_CMD_ERR_CONTENT_8822B(v)) /* 2 REG_SDIO_CRC_ERR_IDX_8822B */ #define BIT_D3_CRC_ERR_8822B BIT(4) @@ -11129,19 +17837,34 @@ /* 2 REG_SDIO_DATA_CRC_8822B */ #define BIT_SHIFT_SDIO_DATA_CRC_8822B 0 -#define BIT_MASK_SDIO_DATA_CRC_8822B 0xff -#define BIT_SDIO_DATA_CRC_8822B(x) (((x) & BIT_MASK_SDIO_DATA_CRC_8822B) << BIT_SHIFT_SDIO_DATA_CRC_8822B) -#define BIT_GET_SDIO_DATA_CRC_8822B(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822B) & BIT_MASK_SDIO_DATA_CRC_8822B) - - +#define BIT_MASK_SDIO_DATA_CRC_8822B 0xffff +#define BIT_SDIO_DATA_CRC_8822B(x) \ + (((x) & BIT_MASK_SDIO_DATA_CRC_8822B) << BIT_SHIFT_SDIO_DATA_CRC_8822B) +#define BITS_SDIO_DATA_CRC_8822B \ + (BIT_MASK_SDIO_DATA_CRC_8822B << BIT_SHIFT_SDIO_DATA_CRC_8822B) +#define BIT_CLEAR_SDIO_DATA_CRC_8822B(x) ((x) & (~BITS_SDIO_DATA_CRC_8822B)) +#define BIT_GET_SDIO_DATA_CRC_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822B) & BIT_MASK_SDIO_DATA_CRC_8822B) +#define BIT_SET_SDIO_DATA_CRC_8822B(x, v) \ + (BIT_CLEAR_SDIO_DATA_CRC_8822B(x) | BIT_SDIO_DATA_CRC_8822B(v)) /* 2 REG_SDIO_DATA_REPLY_TIME_8822B */ #define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B 0 #define BIT_MASK_SDIO_DATA_REPLY_TIME_8822B 0x7 -#define BIT_SDIO_DATA_REPLY_TIME_8822B(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) -#define BIT_GET_SDIO_DATA_REPLY_TIME_8822B(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) - - +#define BIT_SDIO_DATA_REPLY_TIME_8822B(x) \ + (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) +#define BITS_SDIO_DATA_REPLY_TIME_8822B \ + (BIT_MASK_SDIO_DATA_REPLY_TIME_8822B \ + << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) +#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8822B(x) \ + ((x) & (~BITS_SDIO_DATA_REPLY_TIME_8822B)) +#define BIT_GET_SDIO_DATA_REPLY_TIME_8822B(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) & \ + BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) +#define BIT_SET_SDIO_DATA_REPLY_TIME_8822B(x, v) \ + (BIT_CLEAR_SDIO_DATA_REPLY_TIME_8822B(x) | \ + BIT_SDIO_DATA_REPLY_TIME_8822B(v)) #endif diff --git a/hal/halmac/halmac_bit_8822c.h b/hal/halmac/halmac_bit_8822c.h new file mode 100644 index 0000000..7557a39 --- /dev/null +++ b/hal/halmac/halmac_bit_8822c.h @@ -0,0 +1,21838 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __INC_HALMAC_BIT_8822C_H +#define __INC_HALMAC_BIT_8822C_H + +#define CPU_OPT_WIDTH 0x1F + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SYS_ISO_CTRL_8822C */ +#define BIT_PWC_EV12V_8822C BIT(15) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_PA33V_EN_8822C BIT(13) +#define BIT_PA12V_EN_8822C BIT(12) +#define BIT_UA33V_EN_8822C BIT(11) +#define BIT_UA12V_EN_8822C BIT(10) +#define BIT_ISO_RFDIO_8822C BIT(9) +#define BIT_ISO_EB2CORE_8822C BIT(8) +#define BIT_ISO_DIOE_8822C BIT(7) +#define BIT_ISO_WLPON2PP_8822C BIT(6) +#define BIT_ISO_IP2MAC_WA2PP_8822C BIT(5) +#define BIT_ISO_PD2CORE_8822C BIT(4) +#define BIT_ISO_PA2PCIE_8822C BIT(3) +#define BIT_ISO_UD2CORE_8822C BIT(2) +#define BIT_ISO_UA2USB_8822C BIT(1) +#define BIT_ISO_WD2PP_8822C BIT(0) + +/* 2 REG_SYS_FUNC_EN_8822C */ +#define BIT_FEN_MREGEN_8822C BIT(15) +#define BIT_FEN_HWPDN_8822C BIT(14) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_FEN_ELDR_8822C BIT(12) +#define BIT_FEN_DCORE_8822C BIT(11) +#define BIT_FEN_CPUEN_8822C BIT(10) +#define BIT_FEN_DIOE_8822C BIT(9) +#define BIT_FEN_PCIED_8822C BIT(8) +#define BIT_FEN_PPLL_8822C BIT(7) +#define BIT_FEN_PCIEA_8822C BIT(6) +#define BIT_FEN_DIO_PCIE_8822C BIT(5) +#define BIT_FEN_USBD_8822C BIT(4) +#define BIT_FEN_UPLL_8822C BIT(3) +#define BIT_FEN_USBA_8822C BIT(2) +#define BIT_FEN_BB_GLB_RSTN_8822C BIT(1) +#define BIT_FEN_BBRSTB_8822C BIT(0) + +/* 2 REG_SYS_PW_CTRL_8822C */ +#define BIT_SOP_EABM_8822C BIT(31) +#define BIT_SOP_ACKF_8822C BIT(30) +#define BIT_SOP_ERCK_8822C BIT(29) +#define BIT_SOP_ESWR_8822C BIT(28) +#define BIT_SOP_PWMM_8822C BIT(27) +#define BIT_SOP_EECK_8822C BIT(26) +#define BIT_SOP_ANA_CLK_DIVISION_2_8822C BIT(25) +#define BIT_SOP_EXTL_8822C BIT(24) +#define BIT_SYM_OP_RING_12M_8822C BIT(22) +#define BIT_ROP_SWPR_8822C BIT(21) +#define BIT_DIS_HW_LPLDM_8822C BIT(20) +#define BIT_OPT_SWRST_WLMCU_8822C BIT(19) +#define BIT_RDY_SYSPWR_8822C BIT(17) +#define BIT_EN_WLON_8822C BIT(16) +#define BIT_APDM_HPDN_8822C BIT(15) +#define BIT_AFSM_PCIE_SUS_EN_8822C BIT(12) +#define BIT_AFSM_WLSUS_EN_8822C BIT(11) +#define BIT_APFM_SWLPS_8822C BIT(10) +#define BIT_APFM_OFFMAC_8822C BIT(9) +#define BIT_APFN_ONMAC_8822C BIT(8) +#define BIT_CHIP_PDN_EN_8822C BIT(7) +#define BIT_RDY_MACDIS_8822C BIT(6) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_PFM_WOWL_8822C BIT(3) +#define BIT_PFM_LDKP_8822C BIT(2) +#define BIT_WL_HCI_ALD_8822C BIT(1) +#define BIT_PFM_LDALL_8822C BIT(0) + +/* 2 REG_SYS_CLK_CTRL_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_CPU_CLK_EN_8822C BIT(14) +#define BIT_SYMREG_CLK_EN_8822C BIT(13) +#define BIT_HCI_CLK_EN_8822C BIT(12) +#define BIT_MAC_CLK_EN_8822C BIT(11) +#define BIT_SEC_CLK_EN_8822C BIT(10) +#define BIT_PHY_SSC_RSTB_8822C BIT(9) +#define BIT_EXT_32K_EN_8822C BIT(8) +#define BIT_WL_CLK_TEST_8822C BIT(7) +#define BIT_OP_SPS_PWM_EN_8822C BIT(6) +#define BIT_LOADER_CLK_EN_8822C BIT(5) +#define BIT_MACSLP_8822C BIT(4) +#define BIT_WAKEPAD_EN_8822C BIT(3) +#define BIT_ROMD16V_EN_8822C BIT(2) +#define BIT_ANA_CLK_DIVISION_2_8822C BIT(1) +#define BIT_CNTD16V_EN_8822C BIT(0) + +/* 2 REG_SYS_EEPROM_CTRL_8822C */ + +#define BIT_SHIFT_VPDIDX_8822C 8 +#define BIT_MASK_VPDIDX_8822C 0xff +#define BIT_VPDIDX_8822C(x) \ + (((x) & BIT_MASK_VPDIDX_8822C) << BIT_SHIFT_VPDIDX_8822C) +#define BITS_VPDIDX_8822C (BIT_MASK_VPDIDX_8822C << BIT_SHIFT_VPDIDX_8822C) +#define BIT_CLEAR_VPDIDX_8822C(x) ((x) & (~BITS_VPDIDX_8822C)) +#define BIT_GET_VPDIDX_8822C(x) \ + (((x) >> BIT_SHIFT_VPDIDX_8822C) & BIT_MASK_VPDIDX_8822C) +#define BIT_SET_VPDIDX_8822C(x, v) \ + (BIT_CLEAR_VPDIDX_8822C(x) | BIT_VPDIDX_8822C(v)) + +#define BIT_SHIFT_EEM1_0_8822C 6 +#define BIT_MASK_EEM1_0_8822C 0x3 +#define BIT_EEM1_0_8822C(x) \ + (((x) & BIT_MASK_EEM1_0_8822C) << BIT_SHIFT_EEM1_0_8822C) +#define BITS_EEM1_0_8822C (BIT_MASK_EEM1_0_8822C << BIT_SHIFT_EEM1_0_8822C) +#define BIT_CLEAR_EEM1_0_8822C(x) ((x) & (~BITS_EEM1_0_8822C)) +#define BIT_GET_EEM1_0_8822C(x) \ + (((x) >> BIT_SHIFT_EEM1_0_8822C) & BIT_MASK_EEM1_0_8822C) +#define BIT_SET_EEM1_0_8822C(x, v) \ + (BIT_CLEAR_EEM1_0_8822C(x) | BIT_EEM1_0_8822C(v)) + +#define BIT_AUTOLOAD_SUS_8822C BIT(5) +#define BIT_EERPOMSEL_8822C BIT(4) +#define BIT_EECS_V1_8822C BIT(3) +#define BIT_EESK_V1_8822C BIT(2) +#define BIT_EEDI_V1_8822C BIT(1) +#define BIT_EEDO_V1_8822C BIT(0) + +/* 2 REG_EE_VPD_8822C */ + +#define BIT_SHIFT_VPD_DATA_8822C 0 +#define BIT_MASK_VPD_DATA_8822C 0xffffffffL +#define BIT_VPD_DATA_8822C(x) \ + (((x) & BIT_MASK_VPD_DATA_8822C) << BIT_SHIFT_VPD_DATA_8822C) +#define BITS_VPD_DATA_8822C \ + (BIT_MASK_VPD_DATA_8822C << BIT_SHIFT_VPD_DATA_8822C) +#define BIT_CLEAR_VPD_DATA_8822C(x) ((x) & (~BITS_VPD_DATA_8822C)) +#define BIT_GET_VPD_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_VPD_DATA_8822C) & BIT_MASK_VPD_DATA_8822C) +#define BIT_SET_VPD_DATA_8822C(x, v) \ + (BIT_CLEAR_VPD_DATA_8822C(x) | BIT_VPD_DATA_8822C(v)) + +/* 2 REG_SYS_SWR_CTRL1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_HW_AUTO_CTRL_EXT_SWR_8822C BIT(9) +#define BIT_USE_INTERNAL_SWR_AND_LDO_8822C BIT(8) +#define BIT_MAC_ID_EN_8822C BIT(7) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SYS_SWR_CTRL2_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_SW18_SEL_8822C BIT(13) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_SW18_SD_8822C BIT(10) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SYS_SWR_CTRL3_8822C */ +#define BIT_SPS18_OCP_DIS_8822C BIT(31) + +#define BIT_SHIFT_SPS18_OCP_TH_8822C 16 +#define BIT_MASK_SPS18_OCP_TH_8822C 0x7fff +#define BIT_SPS18_OCP_TH_8822C(x) \ + (((x) & BIT_MASK_SPS18_OCP_TH_8822C) << BIT_SHIFT_SPS18_OCP_TH_8822C) +#define BITS_SPS18_OCP_TH_8822C \ + (BIT_MASK_SPS18_OCP_TH_8822C << BIT_SHIFT_SPS18_OCP_TH_8822C) +#define BIT_CLEAR_SPS18_OCP_TH_8822C(x) ((x) & (~BITS_SPS18_OCP_TH_8822C)) +#define BIT_GET_SPS18_OCP_TH_8822C(x) \ + (((x) >> BIT_SHIFT_SPS18_OCP_TH_8822C) & BIT_MASK_SPS18_OCP_TH_8822C) +#define BIT_SET_SPS18_OCP_TH_8822C(x, v) \ + (BIT_CLEAR_SPS18_OCP_TH_8822C(x) | BIT_SPS18_OCP_TH_8822C(v)) + +#define BIT_SHIFT_OCP_WINDOW_8822C 0 +#define BIT_MASK_OCP_WINDOW_8822C 0xffff +#define BIT_OCP_WINDOW_8822C(x) \ + (((x) & BIT_MASK_OCP_WINDOW_8822C) << BIT_SHIFT_OCP_WINDOW_8822C) +#define BITS_OCP_WINDOW_8822C \ + (BIT_MASK_OCP_WINDOW_8822C << BIT_SHIFT_OCP_WINDOW_8822C) +#define BIT_CLEAR_OCP_WINDOW_8822C(x) ((x) & (~BITS_OCP_WINDOW_8822C)) +#define BIT_GET_OCP_WINDOW_8822C(x) \ + (((x) >> BIT_SHIFT_OCP_WINDOW_8822C) & BIT_MASK_OCP_WINDOW_8822C) +#define BIT_SET_OCP_WINDOW_8822C(x, v) \ + (BIT_CLEAR_OCP_WINDOW_8822C(x) | BIT_OCP_WINDOW_8822C(v)) + +/* 2 REG_RSV_CTRL_8822C */ +#define BIT_HREG_DBG_8822C BIT(23) +#define BIT_WLMCUIOIF_8822C BIT(8) +#define BIT_LOCK_ALL_EN_8822C BIT(7) +#define BIT_R_DIS_PRST_8822C BIT(6) +#define BIT_WLOCK_1C_B6_8822C BIT(5) +#define BIT_WLOCK_40_8822C BIT(4) +#define BIT_WLOCK_08_8822C BIT(3) +#define BIT_WLOCK_04_8822C BIT(2) +#define BIT_WLOCK_00_8822C BIT(1) +#define BIT_WLOCK_ALL_8822C BIT(0) + +/* 2 REG_RF_CTRL_8822C */ +#define BIT_RF_SDMRSTB_8822C BIT(2) +#define BIT_RF_RSTB_8822C BIT(1) +#define BIT_RF_EN_8822C BIT(0) + +/* 2 REG_AFE_LDO_CTRL_8822C */ +#define BIT_R_SYM_WLBBOFF1_P4_EN_8822C BIT(9) +#define BIT_R_SYM_WLBBOFF1_P3_EN_8822C BIT(8) +#define BIT_R_SYM_WLBBOFF1_P2_EN_8822C BIT(7) +#define BIT_R_SYM_WLBBOFF1_P1_EN_8822C BIT(6) +#define BIT_R_SYM_WLBBOFF_P4_EN_8822C BIT(4) +#define BIT_R_SYM_WLBBOFF_P3_EN_8822C BIT(3) +#define BIT_R_SYM_WLBBOFF_P2_EN_8822C BIT(2) +#define BIT_R_SYM_WLBBOFF_P1_EN_8822C BIT(1) +#define BIT_R_SYM_WLBBOFF_EN_8822C BIT(0) + +/* 2 REG_AFE_CTRL1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_MAC_CLK_SEL_8822C 20 +#define BIT_MASK_MAC_CLK_SEL_8822C 0x3 +#define BIT_MAC_CLK_SEL_8822C(x) \ + (((x) & BIT_MASK_MAC_CLK_SEL_8822C) << BIT_SHIFT_MAC_CLK_SEL_8822C) +#define BITS_MAC_CLK_SEL_8822C \ + (BIT_MASK_MAC_CLK_SEL_8822C << BIT_SHIFT_MAC_CLK_SEL_8822C) +#define BIT_CLEAR_MAC_CLK_SEL_8822C(x) ((x) & (~BITS_MAC_CLK_SEL_8822C)) +#define BIT_GET_MAC_CLK_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_MAC_CLK_SEL_8822C) & BIT_MASK_MAC_CLK_SEL_8822C) +#define BIT_SET_MAC_CLK_SEL_8822C(x, v) \ + (BIT_CLEAR_MAC_CLK_SEL_8822C(x) | BIT_MAC_CLK_SEL_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ANAPARSW_POW_MAC_8822C */ +#define BIT_POW_LDO15_8822C BIT(2) +#define BIT_POW_SW_8822C BIT(1) +#define BIT_POW_LDO14_8822C BIT(0) + +/* 2 REG_ANAPARLDO_POW_MAC_8822C */ +#define BIT_LDOE25_POW_L_8822C BIT(0) + +/* 2 REG_ANAPAR_POW_MAC_8822C */ +#define BIT_DUMMY_V4_8822C BIT(7) +#define BIT_DUMMY_V3_8822C BIT(6) +#define BIT_DUMMY_V2_8822C BIT(5) +#define BIT_DUMMY_V1_8822C BIT(4) +#define BIT_POW_PC_LDO_PORT1_8822C BIT(3) +#define BIT_POW_PC_LDO_PORT0_8822C BIT(2) +#define BIT_POW_PLL_V1_8822C BIT(1) +#define BIT_POW_POWER_CUT_POW_LDO_8822C BIT(0) + +/* 2 REG_ANAPAR_POW_XTAL_8822C */ +#define BIT_POW_XTAL_8822C BIT(1) +#define BIT_POW_BG_8822C BIT(0) + +/* 2 REG_ANAPARLDO_MAC_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_REG_STANDBY_L_8822C BIT(19) +#define BIT_PD_REGU_L_8822C BIT(18) +#define BIT_EN_PC_BT_L_8822C BIT(17) + +#define BIT_SHIFT_REG_LDOADJ_L_8822C 13 +#define BIT_MASK_REG_LDOADJ_L_8822C 0xf +#define BIT_REG_LDOADJ_L_8822C(x) \ + (((x) & BIT_MASK_REG_LDOADJ_L_8822C) << BIT_SHIFT_REG_LDOADJ_L_8822C) +#define BITS_REG_LDOADJ_L_8822C \ + (BIT_MASK_REG_LDOADJ_L_8822C << BIT_SHIFT_REG_LDOADJ_L_8822C) +#define BIT_CLEAR_REG_LDOADJ_L_8822C(x) ((x) & (~BITS_REG_LDOADJ_L_8822C)) +#define BIT_GET_REG_LDOADJ_L_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LDOADJ_L_8822C) & BIT_MASK_REG_LDOADJ_L_8822C) +#define BIT_SET_REG_LDOADJ_L_8822C(x, v) \ + (BIT_CLEAR_REG_LDOADJ_L_8822C(x) | BIT_REG_LDOADJ_L_8822C(v)) + +#define BIT_CK12M_EN_8822C BIT(11) +#define BIT_CK12M_SEL_8822C BIT(10) +#define BIT_EN_25_L_8822C BIT(9) +#define BIT_EN_SLEEP_8822C BIT(8) + +#define BIT_SHIFT_LDOH12_V12ADJ_L_8822C 4 +#define BIT_MASK_LDOH12_V12ADJ_L_8822C 0xf +#define BIT_LDOH12_V12ADJ_L_8822C(x) \ + (((x) & BIT_MASK_LDOH12_V12ADJ_L_8822C) \ + << BIT_SHIFT_LDOH12_V12ADJ_L_8822C) +#define BITS_LDOH12_V12ADJ_L_8822C \ + (BIT_MASK_LDOH12_V12ADJ_L_8822C << BIT_SHIFT_LDOH12_V12ADJ_L_8822C) +#define BIT_CLEAR_LDOH12_V12ADJ_L_8822C(x) ((x) & (~BITS_LDOH12_V12ADJ_L_8822C)) +#define BIT_GET_LDOH12_V12ADJ_L_8822C(x) \ + (((x) >> BIT_SHIFT_LDOH12_V12ADJ_L_8822C) & \ + BIT_MASK_LDOH12_V12ADJ_L_8822C) +#define BIT_SET_LDOH12_V12ADJ_L_8822C(x, v) \ + (BIT_CLEAR_LDOH12_V12ADJ_L_8822C(x) | BIT_LDOH12_V12ADJ_L_8822C(v)) + +#define BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C 0 +#define BIT_MASK_LDOE25_V12ADJ_L_V1_8822C 0xf +#define BIT_LDOE25_V12ADJ_L_V1_8822C(x) \ + (((x) & BIT_MASK_LDOE25_V12ADJ_L_V1_8822C) \ + << BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C) +#define BITS_LDOE25_V12ADJ_L_V1_8822C \ + (BIT_MASK_LDOE25_V12ADJ_L_V1_8822C \ + << BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C) +#define BIT_CLEAR_LDOE25_V12ADJ_L_V1_8822C(x) \ + ((x) & (~BITS_LDOE25_V12ADJ_L_V1_8822C)) +#define BIT_GET_LDOE25_V12ADJ_L_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C) & \ + BIT_MASK_LDOE25_V12ADJ_L_V1_8822C) +#define BIT_SET_LDOE25_V12ADJ_L_V1_8822C(x, v) \ + (BIT_CLEAR_LDOE25_V12ADJ_L_V1_8822C(x) | \ + BIT_LDOE25_V12ADJ_L_V1_8822C(v)) + +/* 2 REG_EFUSE_CTRL_8822C */ +#define BIT_EF_FLAG_8822C BIT(31) + +#define BIT_SHIFT_EF_PGPD_8822C 28 +#define BIT_MASK_EF_PGPD_8822C 0x7 +#define BIT_EF_PGPD_8822C(x) \ + (((x) & BIT_MASK_EF_PGPD_8822C) << BIT_SHIFT_EF_PGPD_8822C) +#define BITS_EF_PGPD_8822C (BIT_MASK_EF_PGPD_8822C << BIT_SHIFT_EF_PGPD_8822C) +#define BIT_CLEAR_EF_PGPD_8822C(x) ((x) & (~BITS_EF_PGPD_8822C)) +#define BIT_GET_EF_PGPD_8822C(x) \ + (((x) >> BIT_SHIFT_EF_PGPD_8822C) & BIT_MASK_EF_PGPD_8822C) +#define BIT_SET_EF_PGPD_8822C(x, v) \ + (BIT_CLEAR_EF_PGPD_8822C(x) | BIT_EF_PGPD_8822C(v)) + +#define BIT_SHIFT_EF_RDT_8822C 24 +#define BIT_MASK_EF_RDT_8822C 0xf +#define BIT_EF_RDT_8822C(x) \ + (((x) & BIT_MASK_EF_RDT_8822C) << BIT_SHIFT_EF_RDT_8822C) +#define BITS_EF_RDT_8822C (BIT_MASK_EF_RDT_8822C << BIT_SHIFT_EF_RDT_8822C) +#define BIT_CLEAR_EF_RDT_8822C(x) ((x) & (~BITS_EF_RDT_8822C)) +#define BIT_GET_EF_RDT_8822C(x) \ + (((x) >> BIT_SHIFT_EF_RDT_8822C) & BIT_MASK_EF_RDT_8822C) +#define BIT_SET_EF_RDT_8822C(x, v) \ + (BIT_CLEAR_EF_RDT_8822C(x) | BIT_EF_RDT_8822C(v)) + +#define BIT_SHIFT_EF_PGTS_8822C 20 +#define BIT_MASK_EF_PGTS_8822C 0xf +#define BIT_EF_PGTS_8822C(x) \ + (((x) & BIT_MASK_EF_PGTS_8822C) << BIT_SHIFT_EF_PGTS_8822C) +#define BITS_EF_PGTS_8822C (BIT_MASK_EF_PGTS_8822C << BIT_SHIFT_EF_PGTS_8822C) +#define BIT_CLEAR_EF_PGTS_8822C(x) ((x) & (~BITS_EF_PGTS_8822C)) +#define BIT_GET_EF_PGTS_8822C(x) \ + (((x) >> BIT_SHIFT_EF_PGTS_8822C) & BIT_MASK_EF_PGTS_8822C) +#define BIT_SET_EF_PGTS_8822C(x, v) \ + (BIT_CLEAR_EF_PGTS_8822C(x) | BIT_EF_PGTS_8822C(v)) + +#define BIT_EF_PDWN_8822C BIT(19) +#define BIT_EF_ALDEN_8822C BIT(18) + +#define BIT_SHIFT_EF_ADDR_8822C 8 +#define BIT_MASK_EF_ADDR_8822C 0x3ff +#define BIT_EF_ADDR_8822C(x) \ + (((x) & BIT_MASK_EF_ADDR_8822C) << BIT_SHIFT_EF_ADDR_8822C) +#define BITS_EF_ADDR_8822C (BIT_MASK_EF_ADDR_8822C << BIT_SHIFT_EF_ADDR_8822C) +#define BIT_CLEAR_EF_ADDR_8822C(x) ((x) & (~BITS_EF_ADDR_8822C)) +#define BIT_GET_EF_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_EF_ADDR_8822C) & BIT_MASK_EF_ADDR_8822C) +#define BIT_SET_EF_ADDR_8822C(x, v) \ + (BIT_CLEAR_EF_ADDR_8822C(x) | BIT_EF_ADDR_8822C(v)) + +#define BIT_SHIFT_EF_DATA_8822C 0 +#define BIT_MASK_EF_DATA_8822C 0xff +#define BIT_EF_DATA_8822C(x) \ + (((x) & BIT_MASK_EF_DATA_8822C) << BIT_SHIFT_EF_DATA_8822C) +#define BITS_EF_DATA_8822C (BIT_MASK_EF_DATA_8822C << BIT_SHIFT_EF_DATA_8822C) +#define BIT_CLEAR_EF_DATA_8822C(x) ((x) & (~BITS_EF_DATA_8822C)) +#define BIT_GET_EF_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_EF_DATA_8822C) & BIT_MASK_EF_DATA_8822C) +#define BIT_SET_EF_DATA_8822C(x, v) \ + (BIT_CLEAR_EF_DATA_8822C(x) | BIT_EF_DATA_8822C(v)) + +/* 2 REG_LDO_EFUSE_CTRL_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_EF_CRES_SEL_8822C BIT(26) + +#define BIT_SHIFT_EF_SCAN_START_V1_8822C 16 +#define BIT_MASK_EF_SCAN_START_V1_8822C 0x3ff +#define BIT_EF_SCAN_START_V1_8822C(x) \ + (((x) & BIT_MASK_EF_SCAN_START_V1_8822C) \ + << BIT_SHIFT_EF_SCAN_START_V1_8822C) +#define BITS_EF_SCAN_START_V1_8822C \ + (BIT_MASK_EF_SCAN_START_V1_8822C << BIT_SHIFT_EF_SCAN_START_V1_8822C) +#define BIT_CLEAR_EF_SCAN_START_V1_8822C(x) \ + ((x) & (~BITS_EF_SCAN_START_V1_8822C)) +#define BIT_GET_EF_SCAN_START_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822C) & \ + BIT_MASK_EF_SCAN_START_V1_8822C) +#define BIT_SET_EF_SCAN_START_V1_8822C(x, v) \ + (BIT_CLEAR_EF_SCAN_START_V1_8822C(x) | BIT_EF_SCAN_START_V1_8822C(v)) + +#define BIT_SHIFT_EF_SCAN_END_8822C 12 +#define BIT_MASK_EF_SCAN_END_8822C 0xf +#define BIT_EF_SCAN_END_8822C(x) \ + (((x) & BIT_MASK_EF_SCAN_END_8822C) << BIT_SHIFT_EF_SCAN_END_8822C) +#define BITS_EF_SCAN_END_8822C \ + (BIT_MASK_EF_SCAN_END_8822C << BIT_SHIFT_EF_SCAN_END_8822C) +#define BIT_CLEAR_EF_SCAN_END_8822C(x) ((x) & (~BITS_EF_SCAN_END_8822C)) +#define BIT_GET_EF_SCAN_END_8822C(x) \ + (((x) >> BIT_SHIFT_EF_SCAN_END_8822C) & BIT_MASK_EF_SCAN_END_8822C) +#define BIT_SET_EF_SCAN_END_8822C(x, v) \ + (BIT_CLEAR_EF_SCAN_END_8822C(x) | BIT_EF_SCAN_END_8822C(v)) + +#define BIT_EF_PD_DIS_8822C BIT(11) + +#define BIT_SHIFT_EF_CELL_SEL_8822C 8 +#define BIT_MASK_EF_CELL_SEL_8822C 0x3 +#define BIT_EF_CELL_SEL_8822C(x) \ + (((x) & BIT_MASK_EF_CELL_SEL_8822C) << BIT_SHIFT_EF_CELL_SEL_8822C) +#define BITS_EF_CELL_SEL_8822C \ + (BIT_MASK_EF_CELL_SEL_8822C << BIT_SHIFT_EF_CELL_SEL_8822C) +#define BIT_CLEAR_EF_CELL_SEL_8822C(x) ((x) & (~BITS_EF_CELL_SEL_8822C)) +#define BIT_GET_EF_CELL_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_EF_CELL_SEL_8822C) & BIT_MASK_EF_CELL_SEL_8822C) +#define BIT_SET_EF_CELL_SEL_8822C(x, v) \ + (BIT_CLEAR_EF_CELL_SEL_8822C(x) | BIT_EF_CELL_SEL_8822C(v)) + +#define BIT_EF_TRPT_8822C BIT(7) + +#define BIT_SHIFT_EF_TTHD_8822C 0 +#define BIT_MASK_EF_TTHD_8822C 0x7f +#define BIT_EF_TTHD_8822C(x) \ + (((x) & BIT_MASK_EF_TTHD_8822C) << BIT_SHIFT_EF_TTHD_8822C) +#define BITS_EF_TTHD_8822C (BIT_MASK_EF_TTHD_8822C << BIT_SHIFT_EF_TTHD_8822C) +#define BIT_CLEAR_EF_TTHD_8822C(x) ((x) & (~BITS_EF_TTHD_8822C)) +#define BIT_GET_EF_TTHD_8822C(x) \ + (((x) >> BIT_SHIFT_EF_TTHD_8822C) & BIT_MASK_EF_TTHD_8822C) +#define BIT_SET_EF_TTHD_8822C(x, v) \ + (BIT_CLEAR_EF_TTHD_8822C(x) | BIT_EF_TTHD_8822C(v)) + +/* 2 REG_PWR_OPTION_CTRL_8822C */ + +#define BIT_SHIFT_DBG_SEL_V1_8822C 16 +#define BIT_MASK_DBG_SEL_V1_8822C 0xff +#define BIT_DBG_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_DBG_SEL_V1_8822C) << BIT_SHIFT_DBG_SEL_V1_8822C) +#define BITS_DBG_SEL_V1_8822C \ + (BIT_MASK_DBG_SEL_V1_8822C << BIT_SHIFT_DBG_SEL_V1_8822C) +#define BIT_CLEAR_DBG_SEL_V1_8822C(x) ((x) & (~BITS_DBG_SEL_V1_8822C)) +#define BIT_GET_DBG_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_V1_8822C) & BIT_MASK_DBG_SEL_V1_8822C) +#define BIT_SET_DBG_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_DBG_SEL_V1_8822C(x) | BIT_DBG_SEL_V1_8822C(v)) + +#define BIT_SHIFT_DBG_SEL_BYTE_8822C 14 +#define BIT_MASK_DBG_SEL_BYTE_8822C 0x3 +#define BIT_DBG_SEL_BYTE_8822C(x) \ + (((x) & BIT_MASK_DBG_SEL_BYTE_8822C) << BIT_SHIFT_DBG_SEL_BYTE_8822C) +#define BITS_DBG_SEL_BYTE_8822C \ + (BIT_MASK_DBG_SEL_BYTE_8822C << BIT_SHIFT_DBG_SEL_BYTE_8822C) +#define BIT_CLEAR_DBG_SEL_BYTE_8822C(x) ((x) & (~BITS_DBG_SEL_BYTE_8822C)) +#define BIT_GET_DBG_SEL_BYTE_8822C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822C) & BIT_MASK_DBG_SEL_BYTE_8822C) +#define BIT_SET_DBG_SEL_BYTE_8822C(x, v) \ + (BIT_CLEAR_DBG_SEL_BYTE_8822C(x) | BIT_DBG_SEL_BYTE_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_SYSON_DBG_PAD_E2_8822C BIT(11) +#define BIT_SYSON_LED_PAD_E2_8822C BIT(10) +#define BIT_SYSON_GPEE_PAD_E2_8822C BIT(9) +#define BIT_SYSON_PCI_PAD_E2_8822C BIT(8) +#define BIT_AUTO_SW_LDO_VOL_EN_8822C BIT(7) + +#define BIT_SHIFT_SYSON_SPS0WWV_WT_8822C 4 +#define BIT_MASK_SYSON_SPS0WWV_WT_8822C 0x3 +#define BIT_SYSON_SPS0WWV_WT_8822C(x) \ + (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822C) \ + << BIT_SHIFT_SYSON_SPS0WWV_WT_8822C) +#define BITS_SYSON_SPS0WWV_WT_8822C \ + (BIT_MASK_SYSON_SPS0WWV_WT_8822C << BIT_SHIFT_SYSON_SPS0WWV_WT_8822C) +#define BIT_CLEAR_SYSON_SPS0WWV_WT_8822C(x) \ + ((x) & (~BITS_SYSON_SPS0WWV_WT_8822C)) +#define BIT_GET_SYSON_SPS0WWV_WT_8822C(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822C) & \ + BIT_MASK_SYSON_SPS0WWV_WT_8822C) +#define BIT_SET_SYSON_SPS0WWV_WT_8822C(x, v) \ + (BIT_CLEAR_SYSON_SPS0WWV_WT_8822C(x) | BIT_SYSON_SPS0WWV_WT_8822C(v)) + +#define BIT_SHIFT_SYSON_SPS0LDO_WT_8822C 2 +#define BIT_MASK_SYSON_SPS0LDO_WT_8822C 0x3 +#define BIT_SYSON_SPS0LDO_WT_8822C(x) \ + (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822C) \ + << BIT_SHIFT_SYSON_SPS0LDO_WT_8822C) +#define BITS_SYSON_SPS0LDO_WT_8822C \ + (BIT_MASK_SYSON_SPS0LDO_WT_8822C << BIT_SHIFT_SYSON_SPS0LDO_WT_8822C) +#define BIT_CLEAR_SYSON_SPS0LDO_WT_8822C(x) \ + ((x) & (~BITS_SYSON_SPS0LDO_WT_8822C)) +#define BIT_GET_SYSON_SPS0LDO_WT_8822C(x) \ + (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822C) & \ + BIT_MASK_SYSON_SPS0LDO_WT_8822C) +#define BIT_SET_SYSON_SPS0LDO_WT_8822C(x, v) \ + (BIT_CLEAR_SYSON_SPS0LDO_WT_8822C(x) | BIT_SYSON_SPS0LDO_WT_8822C(v)) + +#define BIT_SHIFT_SYSON_RCLK_SCALE_8822C 0 +#define BIT_MASK_SYSON_RCLK_SCALE_8822C 0x3 +#define BIT_SYSON_RCLK_SCALE_8822C(x) \ + (((x) & BIT_MASK_SYSON_RCLK_SCALE_8822C) \ + << BIT_SHIFT_SYSON_RCLK_SCALE_8822C) +#define BITS_SYSON_RCLK_SCALE_8822C \ + (BIT_MASK_SYSON_RCLK_SCALE_8822C << BIT_SHIFT_SYSON_RCLK_SCALE_8822C) +#define BIT_CLEAR_SYSON_RCLK_SCALE_8822C(x) \ + ((x) & (~BITS_SYSON_RCLK_SCALE_8822C)) +#define BIT_GET_SYSON_RCLK_SCALE_8822C(x) \ + (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822C) & \ + BIT_MASK_SYSON_RCLK_SCALE_8822C) +#define BIT_SET_SYSON_RCLK_SCALE_8822C(x, v) \ + (BIT_CLEAR_SYSON_RCLK_SCALE_8822C(x) | BIT_SYSON_RCLK_SCALE_8822C(v)) + +/* 2 REG_CAL_TIMER_8822C */ + +#define BIT_SHIFT_MATCH_CNT_8822C 8 +#define BIT_MASK_MATCH_CNT_8822C 0xff +#define BIT_MATCH_CNT_8822C(x) \ + (((x) & BIT_MASK_MATCH_CNT_8822C) << BIT_SHIFT_MATCH_CNT_8822C) +#define BITS_MATCH_CNT_8822C \ + (BIT_MASK_MATCH_CNT_8822C << BIT_SHIFT_MATCH_CNT_8822C) +#define BIT_CLEAR_MATCH_CNT_8822C(x) ((x) & (~BITS_MATCH_CNT_8822C)) +#define BIT_GET_MATCH_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8822C) & BIT_MASK_MATCH_CNT_8822C) +#define BIT_SET_MATCH_CNT_8822C(x, v) \ + (BIT_CLEAR_MATCH_CNT_8822C(x) | BIT_MATCH_CNT_8822C(v)) + +#define BIT_SHIFT_CAL_SCAL_8822C 0 +#define BIT_MASK_CAL_SCAL_8822C 0xff +#define BIT_CAL_SCAL_8822C(x) \ + (((x) & BIT_MASK_CAL_SCAL_8822C) << BIT_SHIFT_CAL_SCAL_8822C) +#define BITS_CAL_SCAL_8822C \ + (BIT_MASK_CAL_SCAL_8822C << BIT_SHIFT_CAL_SCAL_8822C) +#define BIT_CLEAR_CAL_SCAL_8822C(x) ((x) & (~BITS_CAL_SCAL_8822C)) +#define BIT_GET_CAL_SCAL_8822C(x) \ + (((x) >> BIT_SHIFT_CAL_SCAL_8822C) & BIT_MASK_CAL_SCAL_8822C) +#define BIT_SET_CAL_SCAL_8822C(x, v) \ + (BIT_CLEAR_CAL_SCAL_8822C(x) | BIT_CAL_SCAL_8822C(v)) + +/* 2 REG_ACLK_MON_8822C */ + +#define BIT_SHIFT_RCLK_MON_8822C 5 +#define BIT_MASK_RCLK_MON_8822C 0x7ff +#define BIT_RCLK_MON_8822C(x) \ + (((x) & BIT_MASK_RCLK_MON_8822C) << BIT_SHIFT_RCLK_MON_8822C) +#define BITS_RCLK_MON_8822C \ + (BIT_MASK_RCLK_MON_8822C << BIT_SHIFT_RCLK_MON_8822C) +#define BIT_CLEAR_RCLK_MON_8822C(x) ((x) & (~BITS_RCLK_MON_8822C)) +#define BIT_GET_RCLK_MON_8822C(x) \ + (((x) >> BIT_SHIFT_RCLK_MON_8822C) & BIT_MASK_RCLK_MON_8822C) +#define BIT_SET_RCLK_MON_8822C(x, v) \ + (BIT_CLEAR_RCLK_MON_8822C(x) | BIT_RCLK_MON_8822C(v)) + +#define BIT_CAL_EN_8822C BIT(4) + +#define BIT_SHIFT_DPSTU_8822C 2 +#define BIT_MASK_DPSTU_8822C 0x3 +#define BIT_DPSTU_8822C(x) \ + (((x) & BIT_MASK_DPSTU_8822C) << BIT_SHIFT_DPSTU_8822C) +#define BITS_DPSTU_8822C (BIT_MASK_DPSTU_8822C << BIT_SHIFT_DPSTU_8822C) +#define BIT_CLEAR_DPSTU_8822C(x) ((x) & (~BITS_DPSTU_8822C)) +#define BIT_GET_DPSTU_8822C(x) \ + (((x) >> BIT_SHIFT_DPSTU_8822C) & BIT_MASK_DPSTU_8822C) +#define BIT_SET_DPSTU_8822C(x, v) \ + (BIT_CLEAR_DPSTU_8822C(x) | BIT_DPSTU_8822C(v)) + +#define BIT_SUS_16X_8822C BIT(1) + +/* 2 REG_GPIO_MUXCFG_2_8822C */ +#define BIT_SOUT_GPIO8_8822C BIT(7) +#define BIT_SOUT_GPIO5_8822C BIT(6) +#define BIT_RFE_CTRL_5_GPIO14_V1_8822C BIT(5) +#define BIT_RFE_CTRL_10_GPIO13_V1_8822C BIT(4) +#define BIT_RFE_CTRL_11_GPIO4_V1_8822C BIT(3) +#define BIT_RFE_CTRL_5_GPIO14_8822C BIT(2) +#define BIT_RFE_CTRL_10_GPIO13_8822C BIT(1) +#define BIT_RFE_CTRL_11_GPIO4_8822C BIT(0) + +/* 2 REG_GPIO_MUXCFG_8822C */ +#define BIT_RFE_CTRL_3_GPIO12_8822C BIT(31) +#define BIT_BT_RFE_CTRL_5_GPIO12_8822C BIT(30) +#define BIT_S0_TRSW_GPIO12_8822C BIT(29) +#define BIT_RFE_CTRL_9_GPIO13_8822C BIT(28) +#define BIT_RFE_CTRL_9_GPIO12_8822C BIT(27) +#define BIT_RFE_CTRL_8_GPIO4_8822C BIT(26) +#define BIT_BT_RFE_CTRL_1_GPIO13_8822C BIT(25) +#define BIT_BT_RFE_CTRL_1_GPIO12_8822C BIT(24) +#define BIT_BT_RFE_CTRL_0_GPIO4_8822C BIT(23) +#define BIT_ANTSW_GPIO13_8822C BIT(22) +#define BIT_ANTSW_GPIO12_8822C BIT(21) +#define BIT_ANTSWB_GPIO4_8822C BIT(20) +#define BIT_FSPI_EN_8822C BIT(19) +#define BIT_WL_RTS_EXT_32K_SEL_8822C BIT(18) +#define BIT_WLBT_DPDT_SEL_EN_8822C BIT(17) +#define BIT_WLBT_LNAON_SEL_EN_8822C BIT(16) +#define BIT_SIC_LBK_8822C BIT(15) +#define BIT_ENHTP_8822C BIT(14) +#define BIT_BT_AOD_GPIO3_8822C BIT(13) +#define BIT_ENSIC_8822C BIT(12) +#define BIT_SIC_SWRST_8822C BIT(11) +#define BIT_PO_WIFI_PTA_PINS_8822C BIT(10) +#define BIT_PO_BT_PTA_PINS_8822C BIT(9) +#define BIT_ENUART_8822C BIT(8) + +#define BIT_SHIFT_BTMODE_8822C 6 +#define BIT_MASK_BTMODE_8822C 0x3 +#define BIT_BTMODE_8822C(x) \ + (((x) & BIT_MASK_BTMODE_8822C) << BIT_SHIFT_BTMODE_8822C) +#define BITS_BTMODE_8822C (BIT_MASK_BTMODE_8822C << BIT_SHIFT_BTMODE_8822C) +#define BIT_CLEAR_BTMODE_8822C(x) ((x) & (~BITS_BTMODE_8822C)) +#define BIT_GET_BTMODE_8822C(x) \ + (((x) >> BIT_SHIFT_BTMODE_8822C) & BIT_MASK_BTMODE_8822C) +#define BIT_SET_BTMODE_8822C(x, v) \ + (BIT_CLEAR_BTMODE_8822C(x) | BIT_BTMODE_8822C(v)) + +#define BIT_ENBT_8822C BIT(5) +#define BIT_EROM_EN_8822C BIT(4) +#define BIT_WLRFE_6_7_EN_8822C BIT(3) +#define BIT_WLRFE_4_5_EN_8822C BIT(2) + +#define BIT_SHIFT_GPIOSEL_8822C 0 +#define BIT_MASK_GPIOSEL_8822C 0x3 +#define BIT_GPIOSEL_8822C(x) \ + (((x) & BIT_MASK_GPIOSEL_8822C) << BIT_SHIFT_GPIOSEL_8822C) +#define BITS_GPIOSEL_8822C (BIT_MASK_GPIOSEL_8822C << BIT_SHIFT_GPIOSEL_8822C) +#define BIT_CLEAR_GPIOSEL_8822C(x) ((x) & (~BITS_GPIOSEL_8822C)) +#define BIT_GET_GPIOSEL_8822C(x) \ + (((x) >> BIT_SHIFT_GPIOSEL_8822C) & BIT_MASK_GPIOSEL_8822C) +#define BIT_SET_GPIOSEL_8822C(x, v) \ + (BIT_CLEAR_GPIOSEL_8822C(x) | BIT_GPIOSEL_8822C(v)) + +/* 2 REG_GPIO_PIN_CTRL_8822C */ + +#define BIT_SHIFT_GPIO_MOD_7_TO_0_8822C 24 +#define BIT_MASK_GPIO_MOD_7_TO_0_8822C 0xff +#define BIT_GPIO_MOD_7_TO_0_8822C(x) \ + (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822C) \ + << BIT_SHIFT_GPIO_MOD_7_TO_0_8822C) +#define BITS_GPIO_MOD_7_TO_0_8822C \ + (BIT_MASK_GPIO_MOD_7_TO_0_8822C << BIT_SHIFT_GPIO_MOD_7_TO_0_8822C) +#define BIT_CLEAR_GPIO_MOD_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8822C)) +#define BIT_GET_GPIO_MOD_7_TO_0_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822C) & \ + BIT_MASK_GPIO_MOD_7_TO_0_8822C) +#define BIT_SET_GPIO_MOD_7_TO_0_8822C(x, v) \ + (BIT_CLEAR_GPIO_MOD_7_TO_0_8822C(x) | BIT_GPIO_MOD_7_TO_0_8822C(v)) + +#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C 16 +#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C 0xff +#define BIT_GPIO_IO_SEL_7_TO_0_8822C(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C) \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C) +#define BITS_GPIO_IO_SEL_7_TO_0_8822C \ + (BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C \ + << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C) +#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822C(x) \ + ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8822C)) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C) & \ + BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C) +#define BIT_SET_GPIO_IO_SEL_7_TO_0_8822C(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822C(x) | \ + BIT_GPIO_IO_SEL_7_TO_0_8822C(v)) + +#define BIT_SHIFT_GPIO_OUT_7_TO_0_8822C 8 +#define BIT_MASK_GPIO_OUT_7_TO_0_8822C 0xff +#define BIT_GPIO_OUT_7_TO_0_8822C(x) \ + (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822C) \ + << BIT_SHIFT_GPIO_OUT_7_TO_0_8822C) +#define BITS_GPIO_OUT_7_TO_0_8822C \ + (BIT_MASK_GPIO_OUT_7_TO_0_8822C << BIT_SHIFT_GPIO_OUT_7_TO_0_8822C) +#define BIT_CLEAR_GPIO_OUT_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8822C)) +#define BIT_GET_GPIO_OUT_7_TO_0_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822C) & \ + BIT_MASK_GPIO_OUT_7_TO_0_8822C) +#define BIT_SET_GPIO_OUT_7_TO_0_8822C(x, v) \ + (BIT_CLEAR_GPIO_OUT_7_TO_0_8822C(x) | BIT_GPIO_OUT_7_TO_0_8822C(v)) + +#define BIT_SHIFT_GPIO_IN_7_TO_0_8822C 0 +#define BIT_MASK_GPIO_IN_7_TO_0_8822C 0xff +#define BIT_GPIO_IN_7_TO_0_8822C(x) \ + (((x) & BIT_MASK_GPIO_IN_7_TO_0_8822C) \ + << BIT_SHIFT_GPIO_IN_7_TO_0_8822C) +#define BITS_GPIO_IN_7_TO_0_8822C \ + (BIT_MASK_GPIO_IN_7_TO_0_8822C << BIT_SHIFT_GPIO_IN_7_TO_0_8822C) +#define BIT_CLEAR_GPIO_IN_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8822C)) +#define BIT_GET_GPIO_IN_7_TO_0_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822C) & \ + BIT_MASK_GPIO_IN_7_TO_0_8822C) +#define BIT_SET_GPIO_IN_7_TO_0_8822C(x, v) \ + (BIT_CLEAR_GPIO_IN_7_TO_0_8822C(x) | BIT_GPIO_IN_7_TO_0_8822C(v)) + +/* 2 REG_GPIO_INTM_8822C */ + +#define BIT_SHIFT_MUXDBG_SEL_8822C 30 +#define BIT_MASK_MUXDBG_SEL_8822C 0x3 +#define BIT_MUXDBG_SEL_8822C(x) \ + (((x) & BIT_MASK_MUXDBG_SEL_8822C) << BIT_SHIFT_MUXDBG_SEL_8822C) +#define BITS_MUXDBG_SEL_8822C \ + (BIT_MASK_MUXDBG_SEL_8822C << BIT_SHIFT_MUXDBG_SEL_8822C) +#define BIT_CLEAR_MUXDBG_SEL_8822C(x) ((x) & (~BITS_MUXDBG_SEL_8822C)) +#define BIT_GET_MUXDBG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_MUXDBG_SEL_8822C) & BIT_MASK_MUXDBG_SEL_8822C) +#define BIT_SET_MUXDBG_SEL_8822C(x, v) \ + (BIT_CLEAR_MUXDBG_SEL_8822C(x) | BIT_MUXDBG_SEL_8822C(v)) + +#define BIT_EXTWOL_SEL_8822C BIT(17) +#define BIT_EXTWOL_EN_8822C BIT(16) +#define BIT_GPIOF_INT_MD_8822C BIT(15) +#define BIT_GPIOE_INT_MD_8822C BIT(14) +#define BIT_GPIOD_INT_MD_8822C BIT(13) +#define BIT_GPIOF_INT_MD_8822C BIT(15) +#define BIT_GPIOE_INT_MD_8822C BIT(14) +#define BIT_GPIOD_INT_MD_8822C BIT(13) +#define BIT_GPIOC_INT_MD_8822C BIT(12) +#define BIT_GPIOB_INT_MD_8822C BIT(11) +#define BIT_GPIOA_INT_MD_8822C BIT(10) +#define BIT_GPIO9_INT_MD_8822C BIT(9) +#define BIT_GPIO8_INT_MD_8822C BIT(8) +#define BIT_GPIO7_INT_MD_8822C BIT(7) +#define BIT_GPIO6_INT_MD_8822C BIT(6) +#define BIT_GPIO5_INT_MD_8822C BIT(5) +#define BIT_GPIO4_INT_MD_8822C BIT(4) +#define BIT_GPIO3_INT_MD_8822C BIT(3) +#define BIT_GPIO2_INT_MD_8822C BIT(2) +#define BIT_GPIO1_INT_MD_8822C BIT(1) +#define BIT_GPIO0_INT_MD_8822C BIT(0) + +/* 2 REG_LED_CFG_8822C */ +#define BIT_MAILBOX_1WIRE_GPIO_CFG_8822C BIT(31) +#define BIT_BT_RF_GPIO_CFG_8822C BIT(30) +#define BIT_BT_SDIO_INT_GPIO_CFG_8822C BIT(29) +#define BIT_MAILBOX_3WIRE_GPIO_CFG_8822C BIT(28) +#define BIT_WLBT_PAPE_SEL_EN_8822C BIT(27) +#define BIT_LNAON_SEL_EN_8822C BIT(26) +#define BIT_PAPE_SEL_EN_8822C BIT(25) +#define BIT_DPDT_WLBT_SEL_8822C BIT(24) +#define BIT_DPDT_SEL_EN_8822C BIT(23) +#define BIT_GPIO13_14_WL_CTRL_EN_8822C BIT(22) +#define BIT_LED2DIS_8822C BIT(21) +#define BIT_LED2PL_8822C BIT(20) +#define BIT_LED2SV_8822C BIT(19) + +#define BIT_SHIFT_LED2CM_8822C 16 +#define BIT_MASK_LED2CM_8822C 0x7 +#define BIT_LED2CM_8822C(x) \ + (((x) & BIT_MASK_LED2CM_8822C) << BIT_SHIFT_LED2CM_8822C) +#define BITS_LED2CM_8822C (BIT_MASK_LED2CM_8822C << BIT_SHIFT_LED2CM_8822C) +#define BIT_CLEAR_LED2CM_8822C(x) ((x) & (~BITS_LED2CM_8822C)) +#define BIT_GET_LED2CM_8822C(x) \ + (((x) >> BIT_SHIFT_LED2CM_8822C) & BIT_MASK_LED2CM_8822C) +#define BIT_SET_LED2CM_8822C(x, v) \ + (BIT_CLEAR_LED2CM_8822C(x) | BIT_LED2CM_8822C(v)) + +#define BIT_LED1DIS_8822C BIT(15) +#define BIT_LED1PL_8822C BIT(12) +#define BIT_LED1SV_8822C BIT(11) + +#define BIT_SHIFT_LED1CM_8822C 8 +#define BIT_MASK_LED1CM_8822C 0x7 +#define BIT_LED1CM_8822C(x) \ + (((x) & BIT_MASK_LED1CM_8822C) << BIT_SHIFT_LED1CM_8822C) +#define BITS_LED1CM_8822C (BIT_MASK_LED1CM_8822C << BIT_SHIFT_LED1CM_8822C) +#define BIT_CLEAR_LED1CM_8822C(x) ((x) & (~BITS_LED1CM_8822C)) +#define BIT_GET_LED1CM_8822C(x) \ + (((x) >> BIT_SHIFT_LED1CM_8822C) & BIT_MASK_LED1CM_8822C) +#define BIT_SET_LED1CM_8822C(x, v) \ + (BIT_CLEAR_LED1CM_8822C(x) | BIT_LED1CM_8822C(v)) + +#define BIT_LED0DIS_8822C BIT(7) + +#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C 5 +#define BIT_MASK_AFE_LDO_SWR_CHECK_8822C 0x3 +#define BIT_AFE_LDO_SWR_CHECK_8822C(x) \ + (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822C) \ + << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C) +#define BITS_AFE_LDO_SWR_CHECK_8822C \ + (BIT_MASK_AFE_LDO_SWR_CHECK_8822C << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C) +#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8822C(x) \ + ((x) & (~BITS_AFE_LDO_SWR_CHECK_8822C)) +#define BIT_GET_AFE_LDO_SWR_CHECK_8822C(x) \ + (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C) & \ + BIT_MASK_AFE_LDO_SWR_CHECK_8822C) +#define BIT_SET_AFE_LDO_SWR_CHECK_8822C(x, v) \ + (BIT_CLEAR_AFE_LDO_SWR_CHECK_8822C(x) | BIT_AFE_LDO_SWR_CHECK_8822C(v)) + +#define BIT_LED0PL_8822C BIT(4) +#define BIT_LED0SV_8822C BIT(3) + +#define BIT_SHIFT_LED0CM_8822C 0 +#define BIT_MASK_LED0CM_8822C 0x7 +#define BIT_LED0CM_8822C(x) \ + (((x) & BIT_MASK_LED0CM_8822C) << BIT_SHIFT_LED0CM_8822C) +#define BITS_LED0CM_8822C (BIT_MASK_LED0CM_8822C << BIT_SHIFT_LED0CM_8822C) +#define BIT_CLEAR_LED0CM_8822C(x) ((x) & (~BITS_LED0CM_8822C)) +#define BIT_GET_LED0CM_8822C(x) \ + (((x) >> BIT_SHIFT_LED0CM_8822C) & BIT_MASK_LED0CM_8822C) +#define BIT_SET_LED0CM_8822C(x, v) \ + (BIT_CLEAR_LED0CM_8822C(x) | BIT_LED0CM_8822C(v)) + +/* 2 REG_FSIMR_8822C */ +#define BIT_FS_PDNINT_EN_8822C BIT(31) +#define BIT_FS_SPS_OCP_INT_EN_8822C BIT(29) +#define BIT_FS_PWMERR_INT_EN_8822C BIT(28) +#define BIT_FS_GPIOF_INT_EN_8822C BIT(27) +#define BIT_FS_GPIOE_INT_EN_8822C BIT(26) +#define BIT_FS_GPIOD_INT_EN_8822C BIT(25) +#define BIT_FS_GPIOC_INT_EN_8822C BIT(24) +#define BIT_FS_GPIOB_INT_EN_8822C BIT(23) +#define BIT_FS_GPIOA_INT_EN_8822C BIT(22) +#define BIT_FS_GPIO9_INT_EN_8822C BIT(21) +#define BIT_FS_GPIO8_INT_EN_8822C BIT(20) +#define BIT_FS_GPIO7_INT_EN_8822C BIT(19) +#define BIT_FS_GPIO6_INT_EN_8822C BIT(18) +#define BIT_FS_GPIO5_INT_EN_8822C BIT(17) +#define BIT_FS_GPIO4_INT_EN_8822C BIT(16) +#define BIT_FS_GPIO3_INT_EN_8822C BIT(15) +#define BIT_FS_GPIO2_INT_EN_8822C BIT(14) +#define BIT_FS_GPIO1_INT_EN_8822C BIT(13) +#define BIT_FS_GPIO0_INT_EN_8822C BIT(12) +#define BIT_FS_HCI_SUS_EN_8822C BIT(11) +#define BIT_FS_HCI_RES_EN_8822C BIT(10) +#define BIT_FS_HCI_RESET_EN_8822C BIT(9) +#define BIT_USB_SCSI_CMD_EN_8822C BIT(8) +#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8822C BIT(7) +#define BIT_ACT2RECOVERY_INT_EN_V1_8822C BIT(6) +#define BIT_GEN1GEN2_SWITCH_8822C BIT(5) +#define BIT_HCI_TXDMA_REQ_HIMR_8822C BIT(4) +#define BIT_FS_32K_LEAVE_SETTING_MAK_8822C BIT(3) +#define BIT_FS_32K_ENTER_SETTING_MAK_8822C BIT(2) +#define BIT_FS_USB_LPMRSM_MSK_8822C BIT(1) +#define BIT_FS_USB_LPMINT_MSK_8822C BIT(0) + +/* 2 REG_FSISR_8822C */ +#define BIT_FS_PDNINT_8822C BIT(31) +#define BIT_FS_SPS_OCP_INT_8822C BIT(29) +#define BIT_FS_PWMERR_INT_8822C BIT(28) +#define BIT_FS_GPIOF_INT_8822C BIT(27) +#define BIT_FS_GPIOE_INT_8822C BIT(26) +#define BIT_FS_GPIOD_INT_8822C BIT(25) +#define BIT_FS_GPIOC_INT_8822C BIT(24) +#define BIT_FS_GPIOB_INT_8822C BIT(23) +#define BIT_FS_GPIOA_INT_8822C BIT(22) +#define BIT_FS_GPIO9_INT_8822C BIT(21) +#define BIT_FS_GPIO8_INT_8822C BIT(20) +#define BIT_FS_GPIO7_INT_8822C BIT(19) +#define BIT_FS_GPIO6_INT_8822C BIT(18) +#define BIT_FS_GPIO5_INT_8822C BIT(17) +#define BIT_FS_GPIO4_INT_8822C BIT(16) +#define BIT_FS_GPIO3_INT_8822C BIT(15) +#define BIT_FS_GPIO2_INT_8822C BIT(14) +#define BIT_FS_GPIO1_INT_8822C BIT(13) +#define BIT_FS_GPIO0_INT_8822C BIT(12) +#define BIT_FS_HCI_SUS_INT_8822C BIT(11) +#define BIT_FS_HCI_RES_INT_8822C BIT(10) +#define BIT_FS_HCI_RESET_INT_8822C BIT(9) +#define BIT_USB_SCSI_CMD_INT_8822C BIT(8) +#define BIT_ACT2RECOVERY_8822C BIT(6) +#define BIT_GEN1GEN2_SWITCH_8822C BIT(5) +#define BIT_HCI_TXDMA_REQ_HISR_8822C BIT(4) +#define BIT_FS_32K_LEAVE_SETTING_INT_8822C BIT(3) +#define BIT_FS_32K_ENTER_SETTING_INT_8822C BIT(2) +#define BIT_FS_USB_LPMRSM_INT_8822C BIT(1) +#define BIT_FS_USB_LPMINT_INT_8822C BIT(0) + +/* 2 REG_HSIMR_8822C */ +#define BIT_GPIOF_INT_EN_8822C BIT(31) +#define BIT_GPIOE_INT_EN_8822C BIT(30) +#define BIT_GPIOD_INT_EN_8822C BIT(29) +#define BIT_GPIOC_INT_EN_8822C BIT(28) +#define BIT_GPIOB_INT_EN_8822C BIT(27) +#define BIT_GPIOA_INT_EN_8822C BIT(26) +#define BIT_GPIO9_INT_EN_8822C BIT(25) +#define BIT_GPIO8_INT_EN_8822C BIT(24) +#define BIT_GPIO7_INT_EN_8822C BIT(23) +#define BIT_GPIO6_INT_EN_8822C BIT(22) +#define BIT_GPIO5_INT_EN_8822C BIT(21) +#define BIT_GPIO4_INT_EN_8822C BIT(20) +#define BIT_GPIO3_INT_EN_8822C BIT(19) +#define BIT_GPIO2_INT_EN_V1_8822C BIT(18) +#define BIT_GPIO1_INT_EN_8822C BIT(17) +#define BIT_GPIO0_INT_EN_8822C BIT(16) +#define BIT_PDNINT_EN_8822C BIT(7) +#define BIT_RON_INT_EN_8822C BIT(6) +#define BIT_SPS_OCP_INT_EN_8822C BIT(5) +#define BIT_GPIO15_0_INT_EN_8822C BIT(0) + +/* 2 REG_HSISR_8822C */ +#define BIT_GPIOF_INT_8822C BIT(31) +#define BIT_GPIOE_INT_8822C BIT(30) +#define BIT_GPIOD_INT_8822C BIT(29) +#define BIT_GPIOC_INT_8822C BIT(28) +#define BIT_GPIOB_INT_8822C BIT(27) +#define BIT_GPIOA_INT_8822C BIT(26) +#define BIT_GPIO9_INT_8822C BIT(25) +#define BIT_GPIO8_INT_8822C BIT(24) +#define BIT_GPIO7_INT_8822C BIT(23) +#define BIT_GPIO6_INT_8822C BIT(22) +#define BIT_GPIO5_INT_8822C BIT(21) +#define BIT_GPIO4_INT_8822C BIT(20) +#define BIT_GPIO3_INT_8822C BIT(19) +#define BIT_GPIO2_INT_V1_8822C BIT(18) +#define BIT_GPIO1_INT_8822C BIT(17) +#define BIT_GPIO0_INT_8822C BIT(16) +#define BIT_PDNINT_8822C BIT(7) +#define BIT_RON_INT_8822C BIT(6) +#define BIT_SPS_OCP_INT_8822C BIT(5) +#define BIT_GPIO15_0_INT_8822C BIT(0) + +/* 2 REG_GPIO_EXT_CTRL_8822C */ + +#define BIT_SHIFT_GPIO_MOD_15_TO_8_8822C 24 +#define BIT_MASK_GPIO_MOD_15_TO_8_8822C 0xff +#define BIT_GPIO_MOD_15_TO_8_8822C(x) \ + (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822C) \ + << BIT_SHIFT_GPIO_MOD_15_TO_8_8822C) +#define BITS_GPIO_MOD_15_TO_8_8822C \ + (BIT_MASK_GPIO_MOD_15_TO_8_8822C << BIT_SHIFT_GPIO_MOD_15_TO_8_8822C) +#define BIT_CLEAR_GPIO_MOD_15_TO_8_8822C(x) \ + ((x) & (~BITS_GPIO_MOD_15_TO_8_8822C)) +#define BIT_GET_GPIO_MOD_15_TO_8_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822C) & \ + BIT_MASK_GPIO_MOD_15_TO_8_8822C) +#define BIT_SET_GPIO_MOD_15_TO_8_8822C(x, v) \ + (BIT_CLEAR_GPIO_MOD_15_TO_8_8822C(x) | BIT_GPIO_MOD_15_TO_8_8822C(v)) + +#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C 16 +#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C 0xff +#define BIT_GPIO_IO_SEL_15_TO_8_8822C(x) \ + (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C) \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C) +#define BITS_GPIO_IO_SEL_15_TO_8_8822C \ + (BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C \ + << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C) +#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822C(x) \ + ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8822C)) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C) & \ + BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C) +#define BIT_SET_GPIO_IO_SEL_15_TO_8_8822C(x, v) \ + (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822C(x) | \ + BIT_GPIO_IO_SEL_15_TO_8_8822C(v)) + +#define BIT_SHIFT_GPIO_OUT_15_TO_8_8822C 8 +#define BIT_MASK_GPIO_OUT_15_TO_8_8822C 0xff +#define BIT_GPIO_OUT_15_TO_8_8822C(x) \ + (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822C) \ + << BIT_SHIFT_GPIO_OUT_15_TO_8_8822C) +#define BITS_GPIO_OUT_15_TO_8_8822C \ + (BIT_MASK_GPIO_OUT_15_TO_8_8822C << BIT_SHIFT_GPIO_OUT_15_TO_8_8822C) +#define BIT_CLEAR_GPIO_OUT_15_TO_8_8822C(x) \ + ((x) & (~BITS_GPIO_OUT_15_TO_8_8822C)) +#define BIT_GET_GPIO_OUT_15_TO_8_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822C) & \ + BIT_MASK_GPIO_OUT_15_TO_8_8822C) +#define BIT_SET_GPIO_OUT_15_TO_8_8822C(x, v) \ + (BIT_CLEAR_GPIO_OUT_15_TO_8_8822C(x) | BIT_GPIO_OUT_15_TO_8_8822C(v)) + +#define BIT_SHIFT_GPIO_IN_15_TO_8_8822C 0 +#define BIT_MASK_GPIO_IN_15_TO_8_8822C 0xff +#define BIT_GPIO_IN_15_TO_8_8822C(x) \ + (((x) & BIT_MASK_GPIO_IN_15_TO_8_8822C) \ + << BIT_SHIFT_GPIO_IN_15_TO_8_8822C) +#define BITS_GPIO_IN_15_TO_8_8822C \ + (BIT_MASK_GPIO_IN_15_TO_8_8822C << BIT_SHIFT_GPIO_IN_15_TO_8_8822C) +#define BIT_CLEAR_GPIO_IN_15_TO_8_8822C(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8822C)) +#define BIT_GET_GPIO_IN_15_TO_8_8822C(x) \ + (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822C) & \ + BIT_MASK_GPIO_IN_15_TO_8_8822C) +#define BIT_SET_GPIO_IN_15_TO_8_8822C(x, v) \ + (BIT_CLEAR_GPIO_IN_15_TO_8_8822C(x) | BIT_GPIO_IN_15_TO_8_8822C(v)) + +/* 2 REG_PAD_CTRL1_8822C */ +#define BIT_PAPE_WLBT_SEL_8822C BIT(29) +#define BIT_LNAON_WLBT_SEL_8822C BIT(28) +#define BIT_BT_BQB_GPIO_SEL_8822C BIT(27) +#define BIT_BTGP_GPG3_FEN_8822C BIT(26) +#define BIT_BTGP_GPG2_FEN_8822C BIT(25) +#define BIT_BTGP_JTAG_EN_8822C BIT(24) +#define BIT_XTAL_CLK_EXTARNAL_EN_8822C BIT(23) +#define BIT_BTGP_UART0_EN_8822C BIT(22) +#define BIT_BTGP_UART1_EN_8822C BIT(21) +#define BIT_BTGP_SPI_EN_8822C BIT(20) +#define BIT_BTGP_GPIO_E2_8822C BIT(19) +#define BIT_BTGP_GPIO_EN_8822C BIT(18) + +#define BIT_SHIFT_BTGP_GPIO_SL_8822C 16 +#define BIT_MASK_BTGP_GPIO_SL_8822C 0x3 +#define BIT_BTGP_GPIO_SL_8822C(x) \ + (((x) & BIT_MASK_BTGP_GPIO_SL_8822C) << BIT_SHIFT_BTGP_GPIO_SL_8822C) +#define BITS_BTGP_GPIO_SL_8822C \ + (BIT_MASK_BTGP_GPIO_SL_8822C << BIT_SHIFT_BTGP_GPIO_SL_8822C) +#define BIT_CLEAR_BTGP_GPIO_SL_8822C(x) ((x) & (~BITS_BTGP_GPIO_SL_8822C)) +#define BIT_GET_BTGP_GPIO_SL_8822C(x) \ + (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822C) & BIT_MASK_BTGP_GPIO_SL_8822C) +#define BIT_SET_BTGP_GPIO_SL_8822C(x, v) \ + (BIT_CLEAR_BTGP_GPIO_SL_8822C(x) | BIT_BTGP_GPIO_SL_8822C(v)) + +#define BIT_PAD_SDIO_SR_8822C BIT(14) +#define BIT_GPIO14_OUTPUT_PL_8822C BIT(13) +#define BIT_HOST_WAKE_PAD_PULL_EN_8822C BIT(12) +#define BIT_HOST_WAKE_PAD_SL_8822C BIT(11) +#define BIT_PAD_LNAON_SR_8822C BIT(10) +#define BIT_PAD_LNAON_E2_8822C BIT(9) +#define BIT_SW_LNAON_G_SEL_DATA_8822C BIT(8) +#define BIT_SW_LNAON_A_SEL_DATA_8822C BIT(7) +#define BIT_PAD_PAPE_SR_8822C BIT(6) +#define BIT_PAD_PAPE_E2_8822C BIT(5) +#define BIT_SW_PAPE_G_SEL_DATA_8822C BIT(4) +#define BIT_SW_PAPE_A_SEL_DATA_8822C BIT(3) +#define BIT_PAD_DPDT_SR_8822C BIT(2) +#define BIT_PAD_DPDT_PAD_E2_8822C BIT(1) +#define BIT_SW_DPDT_SEL_DATA_8822C BIT(0) + +/* 2 REG_WL_BT_PWR_CTRL_8822C */ +#define BIT_ISO_BD2PP_8822C BIT(31) +#define BIT_LDOV12B_EN_8822C BIT(30) +#define BIT_CKEN_BTGPS_8822C BIT(29) +#define BIT_FEN_BTGPS_8822C BIT(28) +#define BIT_BTCPU_BOOTSEL_8822C BIT(27) +#define BIT_SPI_SPEEDUP_8822C BIT(26) +#define BIT_BT_LDO_MODE_8822C BIT(25) +#define BIT_DEVWAKE_PAD_TYPE_SEL_8822C BIT(24) +#define BIT_CLKREQ_PAD_TYPE_SEL_8822C BIT(23) +#define BIT_ISO_BTPON2PP_8822C BIT(22) +#define BIT_BT_HWROF_EN_8822C BIT(19) +#define BIT_BT_FUNC_EN_8822C BIT(18) +#define BIT_BT_HWPDN_SL_8822C BIT(17) +#define BIT_BT_DISN_EN_8822C BIT(16) +#define BIT_BT_PDN_PULL_EN_8822C BIT(15) +#define BIT_WL_PDN_PULL_EN_8822C BIT(14) +#define BIT_EXTERNAL_REQUEST_PL_8822C BIT(13) +#define BIT_GPIO0_2_3_PULL_LOW_EN_8822C BIT(12) +#define BIT_ISO_BA2PP_8822C BIT(11) +#define BIT_BT_AFE_LDO_EN_8822C BIT(10) +#define BIT_BT_AFE_PLL_EN_8822C BIT(9) +#define BIT_BT_DIG_CLK_EN_8822C BIT(8) +#define BIT_WLAN_32K_SEL_8822C BIT(6) +#define BIT_WL_DRV_EXIST_IDX_8822C BIT(5) +#define BIT_DOP_EHPAD_8822C BIT(4) +#define BIT_WL_HWROF_EN_8822C BIT(3) +#define BIT_WL_FUNC_EN_8822C BIT(2) +#define BIT_WL_HWPDN_SL_8822C BIT(1) +#define BIT_WL_HWPDN_EN_8822C BIT(0) + +/* 2 REG_SDM_DEBUG_8822C */ +#define BIT_GPIO_IE_V18_8822C BIT(10) +#define BIT_PCIE_IE_V18_8822C BIT(9) +#define BIT_UART_IE_V18_8822C BIT(8) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_WLCLK_PHASE_8822C 0 +#define BIT_MASK_WLCLK_PHASE_8822C 0x1f +#define BIT_WLCLK_PHASE_8822C(x) \ + (((x) & BIT_MASK_WLCLK_PHASE_8822C) << BIT_SHIFT_WLCLK_PHASE_8822C) +#define BITS_WLCLK_PHASE_8822C \ + (BIT_MASK_WLCLK_PHASE_8822C << BIT_SHIFT_WLCLK_PHASE_8822C) +#define BIT_CLEAR_WLCLK_PHASE_8822C(x) ((x) & (~BITS_WLCLK_PHASE_8822C)) +#define BIT_GET_WLCLK_PHASE_8822C(x) \ + (((x) >> BIT_SHIFT_WLCLK_PHASE_8822C) & BIT_MASK_WLCLK_PHASE_8822C) +#define BIT_SET_WLCLK_PHASE_8822C(x, v) \ + (BIT_CLEAR_WLCLK_PHASE_8822C(x) | BIT_WLCLK_PHASE_8822C(v)) + +/* 2 REG_SYS_SDIO_CTRL_8822C */ +#define BIT_DBG_GNT_WL_BT_8822C BIT(27) +#define BIT_LTE_MUX_CTRL_PATH_8822C BIT(26) +#define BIT_LTE_COEX_UART_8822C BIT(25) +#define BIT_3W_LTE_WL_GPIO_8822C BIT(24) +#define BIT_SDIO_INT_POLARITY_8822C BIT(19) +#define BIT_SDIO_INT_8822C BIT(18) +#define BIT_SDIO_OFF_EN_8822C BIT(17) +#define BIT_SDIO_ON_EN_8822C BIT(16) +#define BIT_PCIE_FORCE_PWR_NGAT_8822C BIT(13) +#define BIT_PCIE_CALIB_EN_V1_8822C BIT(12) +#define BIT_PAGE3_AUXCLK_GATE_8822C BIT(11) +#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8822C BIT(10) +#define BIT_PCIE_WAIT_TIME_8822C BIT(9) +#define BIT_MPCIE_REFCLK_XTAL_SEL_8822C BIT(8) +#define BIT_BT_CTRL_USB_PWR_BACKDOOR_8822C BIT(5) +#define BIT_USB_D_STATE_HOLD_8822C BIT(4) +#define BIT_REG_FORCE_DP_8822C BIT(3) +#define BIT_REG_DP_MODE_8822C BIT(2) +#define BIT_RES_USB_MASS_STORAGE_DESC_8822C BIT(1) +#define BIT_USB_WAIT_TIME_8822C BIT(0) + +/* 2 REG_HCI_OPT_CTRL_8822C */ + +#define BIT_SHIFT_TSFT_SEL_8822C 29 +#define BIT_MASK_TSFT_SEL_8822C 0x7 +#define BIT_TSFT_SEL_8822C(x) \ + (((x) & BIT_MASK_TSFT_SEL_8822C) << BIT_SHIFT_TSFT_SEL_8822C) +#define BITS_TSFT_SEL_8822C \ + (BIT_MASK_TSFT_SEL_8822C << BIT_SHIFT_TSFT_SEL_8822C) +#define BIT_CLEAR_TSFT_SEL_8822C(x) ((x) & (~BITS_TSFT_SEL_8822C)) +#define BIT_GET_TSFT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_8822C) & BIT_MASK_TSFT_SEL_8822C) +#define BIT_SET_TSFT_SEL_8822C(x, v) \ + (BIT_CLEAR_TSFT_SEL_8822C(x) | BIT_TSFT_SEL_8822C(v)) + +#define BIT_SDIO_PAD_E5_8822C BIT(18) +#define BIT_USB_HOST_PWR_OFF_EN_8822C BIT(12) +#define BIT_SYM_LPS_BLOCK_EN_8822C BIT(11) +#define BIT_USB_LPM_ACT_EN_8822C BIT(10) +#define BIT_USB_LPM_NY_8822C BIT(9) +#define BIT_USB_SUS_DIS_8822C BIT(8) + +#define BIT_SHIFT_SDIO_PAD_E_8822C 5 +#define BIT_MASK_SDIO_PAD_E_8822C 0x7 +#define BIT_SDIO_PAD_E_8822C(x) \ + (((x) & BIT_MASK_SDIO_PAD_E_8822C) << BIT_SHIFT_SDIO_PAD_E_8822C) +#define BITS_SDIO_PAD_E_8822C \ + (BIT_MASK_SDIO_PAD_E_8822C << BIT_SHIFT_SDIO_PAD_E_8822C) +#define BIT_CLEAR_SDIO_PAD_E_8822C(x) ((x) & (~BITS_SDIO_PAD_E_8822C)) +#define BIT_GET_SDIO_PAD_E_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_PAD_E_8822C) & BIT_MASK_SDIO_PAD_E_8822C) +#define BIT_SET_SDIO_PAD_E_8822C(x, v) \ + (BIT_CLEAR_SDIO_PAD_E_8822C(x) | BIT_SDIO_PAD_E_8822C(v)) + +#define BIT_USB_LPPLL_EN_8822C BIT(4) +#define BIT_USB1_1_USB2_0_DECISION_8822C BIT(3) +#define BIT_ROP_SW15_8822C BIT(2) +#define BIT_PCI_CKRDY_OPT_8822C BIT(1) +#define BIT_PCI_VAUX_EN_8822C BIT(0) + +/* 2 REG_HCI_BG_CTRL_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_IBX_EN_VALUE_8822C BIT(9) +#define BIT_IB_EN_VALUE_8822C BIT(8) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_FORCED_IB_EN_8822C BIT(4) +#define BIT_EN_REGBG_8822C BIT(3) +#define BIT_REG_BG_LPF_8822C BIT(2) + +#define BIT_SHIFT_REG_BG_8822C 0 +#define BIT_MASK_REG_BG_8822C 0x3 +#define BIT_REG_BG_8822C(x) \ + (((x) & BIT_MASK_REG_BG_8822C) << BIT_SHIFT_REG_BG_8822C) +#define BITS_REG_BG_8822C (BIT_MASK_REG_BG_8822C << BIT_SHIFT_REG_BG_8822C) +#define BIT_CLEAR_REG_BG_8822C(x) ((x) & (~BITS_REG_BG_8822C)) +#define BIT_GET_REG_BG_8822C(x) \ + (((x) >> BIT_SHIFT_REG_BG_8822C) & BIT_MASK_REG_BG_8822C) +#define BIT_SET_REG_BG_8822C(x, v) \ + (BIT_CLEAR_REG_BG_8822C(x) | BIT_REG_BG_8822C(v)) + +/* 2 REG_HCI_LDO_CTRL_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_EN_LW_PWR_8822C BIT(6) +#define BIT_EN_REGU_8822C BIT(5) +#define BIT_EN_PC_8822C BIT(4) + +#define BIT_SHIFT_REG_VADJ_8822C 0 +#define BIT_MASK_REG_VADJ_8822C 0xf +#define BIT_REG_VADJ_8822C(x) \ + (((x) & BIT_MASK_REG_VADJ_8822C) << BIT_SHIFT_REG_VADJ_8822C) +#define BITS_REG_VADJ_8822C \ + (BIT_MASK_REG_VADJ_8822C << BIT_SHIFT_REG_VADJ_8822C) +#define BIT_CLEAR_REG_VADJ_8822C(x) ((x) & (~BITS_REG_VADJ_8822C)) +#define BIT_GET_REG_VADJ_8822C(x) \ + (((x) >> BIT_SHIFT_REG_VADJ_8822C) & BIT_MASK_REG_VADJ_8822C) +#define BIT_SET_REG_VADJ_8822C(x, v) \ + (BIT_CLEAR_REG_VADJ_8822C(x) | BIT_REG_VADJ_8822C(v)) + +/* 2 REG_LDO_SWR_CTRL_8822C */ +#define BIT_EXT_SWR_CTRL_EN_8822C BIT(31) +#define BIT_ZCD_HW_AUTO_EN_8822C BIT(27) +#define BIT_ZCD_REGSEL_8822C BIT(26) + +#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C 21 +#define BIT_MASK_AUTO_ZCD_IN_CODE_8822C 0x1f +#define BIT_AUTO_ZCD_IN_CODE_8822C(x) \ + (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822C) \ + << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C) +#define BITS_AUTO_ZCD_IN_CODE_8822C \ + (BIT_MASK_AUTO_ZCD_IN_CODE_8822C << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C) +#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8822C(x) \ + ((x) & (~BITS_AUTO_ZCD_IN_CODE_8822C)) +#define BIT_GET_AUTO_ZCD_IN_CODE_8822C(x) \ + (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C) & \ + BIT_MASK_AUTO_ZCD_IN_CODE_8822C) +#define BIT_SET_AUTO_ZCD_IN_CODE_8822C(x, v) \ + (BIT_CLEAR_AUTO_ZCD_IN_CODE_8822C(x) | BIT_AUTO_ZCD_IN_CODE_8822C(v)) + +#define BIT_SHIFT_ZCD_CODE_IN_L_8822C 16 +#define BIT_MASK_ZCD_CODE_IN_L_8822C 0x1f +#define BIT_ZCD_CODE_IN_L_8822C(x) \ + (((x) & BIT_MASK_ZCD_CODE_IN_L_8822C) << BIT_SHIFT_ZCD_CODE_IN_L_8822C) +#define BITS_ZCD_CODE_IN_L_8822C \ + (BIT_MASK_ZCD_CODE_IN_L_8822C << BIT_SHIFT_ZCD_CODE_IN_L_8822C) +#define BIT_CLEAR_ZCD_CODE_IN_L_8822C(x) ((x) & (~BITS_ZCD_CODE_IN_L_8822C)) +#define BIT_GET_ZCD_CODE_IN_L_8822C(x) \ + (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822C) & BIT_MASK_ZCD_CODE_IN_L_8822C) +#define BIT_SET_ZCD_CODE_IN_L_8822C(x, v) \ + (BIT_CLEAR_ZCD_CODE_IN_L_8822C(x) | BIT_ZCD_CODE_IN_L_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_MCUFW_CTRL_8822C */ + +#define BIT_SHIFT_RPWM_8822C 24 +#define BIT_MASK_RPWM_8822C 0xff +#define BIT_RPWM_8822C(x) (((x) & BIT_MASK_RPWM_8822C) << BIT_SHIFT_RPWM_8822C) +#define BITS_RPWM_8822C (BIT_MASK_RPWM_8822C << BIT_SHIFT_RPWM_8822C) +#define BIT_CLEAR_RPWM_8822C(x) ((x) & (~BITS_RPWM_8822C)) +#define BIT_GET_RPWM_8822C(x) \ + (((x) >> BIT_SHIFT_RPWM_8822C) & BIT_MASK_RPWM_8822C) +#define BIT_SET_RPWM_8822C(x, v) (BIT_CLEAR_RPWM_8822C(x) | BIT_RPWM_8822C(v)) + +#define BIT_ANA_PORT_EN_8822C BIT(22) +#define BIT_MAC_PORT_EN_8822C BIT(21) +#define BIT_BOOT_FSPI_EN_8822C BIT(20) +#define BIT_ROM_DLEN_8822C BIT(19) + +#define BIT_SHIFT_ROM_PGE_8822C 16 +#define BIT_MASK_ROM_PGE_8822C 0x7 +#define BIT_ROM_PGE_8822C(x) \ + (((x) & BIT_MASK_ROM_PGE_8822C) << BIT_SHIFT_ROM_PGE_8822C) +#define BITS_ROM_PGE_8822C (BIT_MASK_ROM_PGE_8822C << BIT_SHIFT_ROM_PGE_8822C) +#define BIT_CLEAR_ROM_PGE_8822C(x) ((x) & (~BITS_ROM_PGE_8822C)) +#define BIT_GET_ROM_PGE_8822C(x) \ + (((x) >> BIT_SHIFT_ROM_PGE_8822C) & BIT_MASK_ROM_PGE_8822C) +#define BIT_SET_ROM_PGE_8822C(x, v) \ + (BIT_CLEAR_ROM_PGE_8822C(x) | BIT_ROM_PGE_8822C(v)) + +#define BIT_FW_INIT_RDY_8822C BIT(15) +#define BIT_FW_DW_RDY_8822C BIT(14) + +#define BIT_SHIFT_CPU_CLK_SEL_8822C 12 +#define BIT_MASK_CPU_CLK_SEL_8822C 0x3 +#define BIT_CPU_CLK_SEL_8822C(x) \ + (((x) & BIT_MASK_CPU_CLK_SEL_8822C) << BIT_SHIFT_CPU_CLK_SEL_8822C) +#define BITS_CPU_CLK_SEL_8822C \ + (BIT_MASK_CPU_CLK_SEL_8822C << BIT_SHIFT_CPU_CLK_SEL_8822C) +#define BIT_CLEAR_CPU_CLK_SEL_8822C(x) ((x) & (~BITS_CPU_CLK_SEL_8822C)) +#define BIT_GET_CPU_CLK_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_CPU_CLK_SEL_8822C) & BIT_MASK_CPU_CLK_SEL_8822C) +#define BIT_SET_CPU_CLK_SEL_8822C(x, v) \ + (BIT_CLEAR_CPU_CLK_SEL_8822C(x) | BIT_CPU_CLK_SEL_8822C(v)) + +#define BIT_CCLK_CHG_MASK_8822C BIT(11) +#define BIT_EMEM__TXBUF_CHKSUM_OK_8822C BIT(10) +#define BIT_EMEM_TXBUF_DW_RDY_8822C BIT(9) +#define BIT_EMEM_CHKSUM_OK_8822C BIT(8) +#define BIT_EMEM_DW_OK_8822C BIT(7) +#define BIT_DMEM_CHKSUM_OK_8822C BIT(6) +#define BIT_DMEM_DW_OK_8822C BIT(5) +#define BIT_IMEM_CHKSUM_OK_8822C BIT(4) +#define BIT_IMEM_DW_OK_8822C BIT(3) +#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8822C BIT(2) +#define BIT_IMEM_BOOT_LOAD_DW_OK_8822C BIT(1) +#define BIT_MCUFWDL_EN_8822C BIT(0) + +/* 2 REG_MCU_TST_CFG_8822C */ + +#define BIT_SHIFT_LBKTST_8822C 0 +#define BIT_MASK_LBKTST_8822C 0xffff +#define BIT_LBKTST_8822C(x) \ + (((x) & BIT_MASK_LBKTST_8822C) << BIT_SHIFT_LBKTST_8822C) +#define BITS_LBKTST_8822C (BIT_MASK_LBKTST_8822C << BIT_SHIFT_LBKTST_8822C) +#define BIT_CLEAR_LBKTST_8822C(x) ((x) & (~BITS_LBKTST_8822C)) +#define BIT_GET_LBKTST_8822C(x) \ + (((x) >> BIT_SHIFT_LBKTST_8822C) & BIT_MASK_LBKTST_8822C) +#define BIT_SET_LBKTST_8822C(x, v) \ + (BIT_CLEAR_LBKTST_8822C(x) | BIT_LBKTST_8822C(v)) + +/* 2 REG_HMEBOX_E0_E1_8822C */ + +#define BIT_SHIFT_HOST_MSG_E1_8822C 16 +#define BIT_MASK_HOST_MSG_E1_8822C 0xffff +#define BIT_HOST_MSG_E1_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_E1_8822C) << BIT_SHIFT_HOST_MSG_E1_8822C) +#define BITS_HOST_MSG_E1_8822C \ + (BIT_MASK_HOST_MSG_E1_8822C << BIT_SHIFT_HOST_MSG_E1_8822C) +#define BIT_CLEAR_HOST_MSG_E1_8822C(x) ((x) & (~BITS_HOST_MSG_E1_8822C)) +#define BIT_GET_HOST_MSG_E1_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E1_8822C) & BIT_MASK_HOST_MSG_E1_8822C) +#define BIT_SET_HOST_MSG_E1_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_E1_8822C(x) | BIT_HOST_MSG_E1_8822C(v)) + +#define BIT_SHIFT_HOST_MSG_E0_8822C 0 +#define BIT_MASK_HOST_MSG_E0_8822C 0xffff +#define BIT_HOST_MSG_E0_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_E0_8822C) << BIT_SHIFT_HOST_MSG_E0_8822C) +#define BITS_HOST_MSG_E0_8822C \ + (BIT_MASK_HOST_MSG_E0_8822C << BIT_SHIFT_HOST_MSG_E0_8822C) +#define BIT_CLEAR_HOST_MSG_E0_8822C(x) ((x) & (~BITS_HOST_MSG_E0_8822C)) +#define BIT_GET_HOST_MSG_E0_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E0_8822C) & BIT_MASK_HOST_MSG_E0_8822C) +#define BIT_SET_HOST_MSG_E0_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_E0_8822C(x) | BIT_HOST_MSG_E0_8822C(v)) + +/* 2 REG_HMEBOX_E2_E3_8822C */ + +#define BIT_SHIFT_HOST_MSG_E3_8822C 16 +#define BIT_MASK_HOST_MSG_E3_8822C 0xffff +#define BIT_HOST_MSG_E3_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_E3_8822C) << BIT_SHIFT_HOST_MSG_E3_8822C) +#define BITS_HOST_MSG_E3_8822C \ + (BIT_MASK_HOST_MSG_E3_8822C << BIT_SHIFT_HOST_MSG_E3_8822C) +#define BIT_CLEAR_HOST_MSG_E3_8822C(x) ((x) & (~BITS_HOST_MSG_E3_8822C)) +#define BIT_GET_HOST_MSG_E3_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E3_8822C) & BIT_MASK_HOST_MSG_E3_8822C) +#define BIT_SET_HOST_MSG_E3_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_E3_8822C(x) | BIT_HOST_MSG_E3_8822C(v)) + +#define BIT_SHIFT_HOST_MSG_E2_8822C 0 +#define BIT_MASK_HOST_MSG_E2_8822C 0xffff +#define BIT_HOST_MSG_E2_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_E2_8822C) << BIT_SHIFT_HOST_MSG_E2_8822C) +#define BITS_HOST_MSG_E2_8822C \ + (BIT_MASK_HOST_MSG_E2_8822C << BIT_SHIFT_HOST_MSG_E2_8822C) +#define BIT_CLEAR_HOST_MSG_E2_8822C(x) ((x) & (~BITS_HOST_MSG_E2_8822C)) +#define BIT_GET_HOST_MSG_E2_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_E2_8822C) & BIT_MASK_HOST_MSG_E2_8822C) +#define BIT_SET_HOST_MSG_E2_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_E2_8822C(x) | BIT_HOST_MSG_E2_8822C(v)) + +/* 2 REG_WLLPS_CTRL_8822C */ +#define BIT_WLLPSOP_EABM_8822C BIT(31) +#define BIT_WLLPSOP_ACKF_8822C BIT(30) +#define BIT_WLLPSOP_DLDM_8822C BIT(29) +#define BIT_WLLPSOP_ESWR_8822C BIT(28) +#define BIT_WLLPSOP_PWMM_8822C BIT(27) +#define BIT_WLLPSOP_EECK_8822C BIT(26) +#define BIT_WLLPSOP_WLMACOFF_8822C BIT(25) +#define BIT_WLLPSOP_EXTAL_8822C BIT(24) +#define BIT_WL_SYNPON_VOLTSPDN_8822C BIT(23) +#define BIT_WLLPSOP_WLBBOFF_8822C BIT(22) +#define BIT_WLLPSOP_WLMEM_DS_8822C BIT(21) +#define BIT_WLLPSOP_LDO_WAIT_TIME_8822C BIT(20) +#define BIT_WLLPSOP_ANA_CLK_DIVISION_2_8822C BIT(19) +#define BIT_AFE_BCN_8822C BIT(18) + +#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C 12 +#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C 0xf +#define BIT_LPLDH12_VADJ_STEP_DN_8822C(x) \ + (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C) \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C) +#define BITS_LPLDH12_VADJ_STEP_DN_8822C \ + (BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C \ + << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C) +#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822C(x) \ + ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8822C)) +#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822C(x) \ + (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C) & \ + BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C) +#define BIT_SET_LPLDH12_VADJ_STEP_DN_8822C(x, v) \ + (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822C(x) | \ + BIT_LPLDH12_VADJ_STEP_DN_8822C(v)) + +#define BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C 8 +#define BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C 0xf +#define BIT_V15ADJ_L1_STEP_DN_V1_8822C(x) \ + (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C) \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C) +#define BITS_V15ADJ_L1_STEP_DN_V1_8822C \ + (BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C \ + << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C) +#define BIT_CLEAR_V15ADJ_L1_STEP_DN_V1_8822C(x) \ + ((x) & (~BITS_V15ADJ_L1_STEP_DN_V1_8822C)) +#define BIT_GET_V15ADJ_L1_STEP_DN_V1_8822C(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C) & \ + BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C) +#define BIT_SET_V15ADJ_L1_STEP_DN_V1_8822C(x, v) \ + (BIT_CLEAR_V15ADJ_L1_STEP_DN_V1_8822C(x) | \ + BIT_V15ADJ_L1_STEP_DN_V1_8822C(v)) + +#define BIT_FORCE_LEAVE_LPS_8822C BIT(3) +#define BIT_SW_AFE_MODE_8822C BIT(2) +#define BIT_REGU_32K_CLK_EN_8822C BIT(1) +#define BIT_WL_LPS_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_GPIO_DEBOUNCE_CTRL_8822C */ +#define BIT_WLGP_DBC1EN_8822C BIT(15) + +#define BIT_SHIFT_WLGP_DBC1_8822C 8 +#define BIT_MASK_WLGP_DBC1_8822C 0xf +#define BIT_WLGP_DBC1_8822C(x) \ + (((x) & BIT_MASK_WLGP_DBC1_8822C) << BIT_SHIFT_WLGP_DBC1_8822C) +#define BITS_WLGP_DBC1_8822C \ + (BIT_MASK_WLGP_DBC1_8822C << BIT_SHIFT_WLGP_DBC1_8822C) +#define BIT_CLEAR_WLGP_DBC1_8822C(x) ((x) & (~BITS_WLGP_DBC1_8822C)) +#define BIT_GET_WLGP_DBC1_8822C(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC1_8822C) & BIT_MASK_WLGP_DBC1_8822C) +#define BIT_SET_WLGP_DBC1_8822C(x, v) \ + (BIT_CLEAR_WLGP_DBC1_8822C(x) | BIT_WLGP_DBC1_8822C(v)) + +#define BIT_WLGP_DBC0EN_8822C BIT(7) + +#define BIT_SHIFT_WLGP_DBC0_8822C 0 +#define BIT_MASK_WLGP_DBC0_8822C 0xf +#define BIT_WLGP_DBC0_8822C(x) \ + (((x) & BIT_MASK_WLGP_DBC0_8822C) << BIT_SHIFT_WLGP_DBC0_8822C) +#define BITS_WLGP_DBC0_8822C \ + (BIT_MASK_WLGP_DBC0_8822C << BIT_SHIFT_WLGP_DBC0_8822C) +#define BIT_CLEAR_WLGP_DBC0_8822C(x) ((x) & (~BITS_WLGP_DBC0_8822C)) +#define BIT_GET_WLGP_DBC0_8822C(x) \ + (((x) >> BIT_SHIFT_WLGP_DBC0_8822C) & BIT_MASK_WLGP_DBC0_8822C) +#define BIT_SET_WLGP_DBC0_8822C(x, v) \ + (BIT_CLEAR_WLGP_DBC0_8822C(x) | BIT_WLGP_DBC0_8822C(v)) + +/* 2 REG_RPWM2_8822C */ + +#define BIT_SHIFT_RPWM2_8822C 16 +#define BIT_MASK_RPWM2_8822C 0xffff +#define BIT_RPWM2_8822C(x) \ + (((x) & BIT_MASK_RPWM2_8822C) << BIT_SHIFT_RPWM2_8822C) +#define BITS_RPWM2_8822C (BIT_MASK_RPWM2_8822C << BIT_SHIFT_RPWM2_8822C) +#define BIT_CLEAR_RPWM2_8822C(x) ((x) & (~BITS_RPWM2_8822C)) +#define BIT_GET_RPWM2_8822C(x) \ + (((x) >> BIT_SHIFT_RPWM2_8822C) & BIT_MASK_RPWM2_8822C) +#define BIT_SET_RPWM2_8822C(x, v) \ + (BIT_CLEAR_RPWM2_8822C(x) | BIT_RPWM2_8822C(v)) + +/* 2 REG_SYSON_FSM_MON_8822C */ + +#define BIT_SHIFT_FSM_MON_SEL_8822C 24 +#define BIT_MASK_FSM_MON_SEL_8822C 0x7 +#define BIT_FSM_MON_SEL_8822C(x) \ + (((x) & BIT_MASK_FSM_MON_SEL_8822C) << BIT_SHIFT_FSM_MON_SEL_8822C) +#define BITS_FSM_MON_SEL_8822C \ + (BIT_MASK_FSM_MON_SEL_8822C << BIT_SHIFT_FSM_MON_SEL_8822C) +#define BIT_CLEAR_FSM_MON_SEL_8822C(x) ((x) & (~BITS_FSM_MON_SEL_8822C)) +#define BIT_GET_FSM_MON_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_FSM_MON_SEL_8822C) & BIT_MASK_FSM_MON_SEL_8822C) +#define BIT_SET_FSM_MON_SEL_8822C(x, v) \ + (BIT_CLEAR_FSM_MON_SEL_8822C(x) | BIT_FSM_MON_SEL_8822C(v)) + +#define BIT_DOP_ELDO_8822C BIT(23) +#define BIT_FSM_MON_UPD_8822C BIT(15) + +#define BIT_SHIFT_FSM_PAR_8822C 0 +#define BIT_MASK_FSM_PAR_8822C 0x7fff +#define BIT_FSM_PAR_8822C(x) \ + (((x) & BIT_MASK_FSM_PAR_8822C) << BIT_SHIFT_FSM_PAR_8822C) +#define BITS_FSM_PAR_8822C (BIT_MASK_FSM_PAR_8822C << BIT_SHIFT_FSM_PAR_8822C) +#define BIT_CLEAR_FSM_PAR_8822C(x) ((x) & (~BITS_FSM_PAR_8822C)) +#define BIT_GET_FSM_PAR_8822C(x) \ + (((x) >> BIT_SHIFT_FSM_PAR_8822C) & BIT_MASK_FSM_PAR_8822C) +#define BIT_SET_FSM_PAR_8822C(x, v) \ + (BIT_CLEAR_FSM_PAR_8822C(x) | BIT_FSM_PAR_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_PMC_DBG_CTRL1_8822C */ +#define BIT_BT_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C 16 +#define BIT_MASK_RD_WR_WIFI_BT_INFO_8822C 0x7fff +#define BIT_RD_WR_WIFI_BT_INFO_8822C(x) \ + (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822C) \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C) +#define BITS_RD_WR_WIFI_BT_INFO_8822C \ + (BIT_MASK_RD_WR_WIFI_BT_INFO_8822C \ + << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C) +#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822C(x) \ + ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8822C)) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C) & \ + BIT_MASK_RD_WR_WIFI_BT_INFO_8822C) +#define BIT_SET_RD_WR_WIFI_BT_INFO_8822C(x, v) \ + (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822C(x) | \ + BIT_RD_WR_WIFI_BT_INFO_8822C(v)) + +#define BIT_PMC_WR_OVF_8822C BIT(8) + +#define BIT_SHIFT_WLPMC_ERRINT_8822C 0 +#define BIT_MASK_WLPMC_ERRINT_8822C 0xff +#define BIT_WLPMC_ERRINT_8822C(x) \ + (((x) & BIT_MASK_WLPMC_ERRINT_8822C) << BIT_SHIFT_WLPMC_ERRINT_8822C) +#define BITS_WLPMC_ERRINT_8822C \ + (BIT_MASK_WLPMC_ERRINT_8822C << BIT_SHIFT_WLPMC_ERRINT_8822C) +#define BIT_CLEAR_WLPMC_ERRINT_8822C(x) ((x) & (~BITS_WLPMC_ERRINT_8822C)) +#define BIT_GET_WLPMC_ERRINT_8822C(x) \ + (((x) >> BIT_SHIFT_WLPMC_ERRINT_8822C) & BIT_MASK_WLPMC_ERRINT_8822C) +#define BIT_SET_WLPMC_ERRINT_8822C(x, v) \ + (BIT_CLEAR_WLPMC_ERRINT_8822C(x) | BIT_WLPMC_ERRINT_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_HIMR0_8822C */ +#define BIT_TIMEOUT_INTERRUPT2_MASK_8822C BIT(31) +#define BIT_TIMEOUT_INTERRUTP1_MASK_8822C BIT(30) +#define BIT_PSTIMEOUT_MSK_8822C BIT(29) +#define BIT_GTINT4_MSK_8822C BIT(28) +#define BIT_GTINT3_MSK_8822C BIT(27) +#define BIT_TXBCN0ERR_MSK_8822C BIT(26) +#define BIT_TXBCN0OK_MSK_8822C BIT(25) +#define BIT_TSF_BIT32_TOGGLE_MSK_8822C BIT(24) +#define BIT_BCNDMAINT0_MSK_8822C BIT(20) +#define BIT_BCNDERR0_MSK_8822C BIT(16) +#define BIT_HSISR_IND_ON_INT_MSK_8822C BIT(15) +#define BIT_BCNDMAINT_E_MSK_8822C BIT(14) +#define BIT_CTWEND_MSK_8822C BIT(12) +#define BIT_HISR1_IND_MSK_8822C BIT(11) +#define BIT_C2HCMD_MSK_8822C BIT(10) +#define BIT_CPWM2_MSK_8822C BIT(9) +#define BIT_CPWM_MSK_8822C BIT(8) +#define BIT_HIGHDOK_MSK_8822C BIT(7) +#define BIT_MGTDOK_MSK_8822C BIT(6) +#define BIT_BKDOK_MSK_8822C BIT(5) +#define BIT_BEDOK_MSK_8822C BIT(4) +#define BIT_VIDOK_MSK_8822C BIT(3) +#define BIT_VODOK_MSK_8822C BIT(2) +#define BIT_RDU_MSK_8822C BIT(1) +#define BIT_RXOK_MSK_8822C BIT(0) + +/* 2 REG_HISR0_8822C */ +#define BIT_PSTIMEOUT2_8822C BIT(31) +#define BIT_PSTIMEOUT1_8822C BIT(30) +#define BIT_PSTIMEOUT_8822C BIT(29) +#define BIT_GTINT4_8822C BIT(28) +#define BIT_GTINT3_8822C BIT(27) +#define BIT_TXBCN0ERR_8822C BIT(26) +#define BIT_TXBCN0OK_8822C BIT(25) +#define BIT_TSF_BIT32_TOGGLE_8822C BIT(24) +#define BIT_BCNDMAINT0_8822C BIT(20) +#define BIT_BCNDERR0_8822C BIT(16) +#define BIT_HSISR_IND_ON_INT_8822C BIT(15) +#define BIT_BCNDMAINT_E_8822C BIT(14) +#define BIT_CTWEND_8822C BIT(12) +#define BIT_HISR1_IND_INT_8822C BIT(11) +#define BIT_C2HCMD_8822C BIT(10) +#define BIT_CPWM2_8822C BIT(9) +#define BIT_CPWM_8822C BIT(8) +#define BIT_HIGHDOK_8822C BIT(7) +#define BIT_MGTDOK_8822C BIT(6) +#define BIT_BKDOK_8822C BIT(5) +#define BIT_BEDOK_8822C BIT(4) +#define BIT_VIDOK_8822C BIT(3) +#define BIT_VODOK_8822C BIT(2) +#define BIT_RDU_8822C BIT(1) +#define BIT_RXOK_8822C BIT(0) + +/* 2 REG_HIMR1_8822C */ +#define BIT_TXFIFO_TH_INT_8822C BIT(30) +#define BIT_BTON_STS_UPDATE_MASK_8822C BIT(29) +#define BIT_MCU_ERR_MASK_8822C BIT(28) +#define BIT_BCNDMAINT7__MSK_8822C BIT(27) +#define BIT_BCNDMAINT6__MSK_8822C BIT(26) +#define BIT_BCNDMAINT5__MSK_8822C BIT(25) +#define BIT_BCNDMAINT4__MSK_8822C BIT(24) +#define BIT_BCNDMAINT3_MSK_8822C BIT(23) +#define BIT_BCNDMAINT2_MSK_8822C BIT(22) +#define BIT_BCNDMAINT1_MSK_8822C BIT(21) +#define BIT_BCNDERR7_MSK_8822C BIT(20) +#define BIT_BCNDERR6_MSK_8822C BIT(19) +#define BIT_BCNDERR5_MSK_8822C BIT(18) +#define BIT_BCNDERR4_MSK_8822C BIT(17) +#define BIT_BCNDERR3_MSK_8822C BIT(16) +#define BIT_BCNDERR2_MSK_8822C BIT(15) +#define BIT_BCNDERR1_MSK_8822C BIT(14) +#define BIT_ATIMEND_E_MSK_8822C BIT(13) +#define BIT_ATIMEND__MSK_8822C BIT(12) +#define BIT_TXERR_MSK_8822C BIT(11) +#define BIT_RXERR_MSK_8822C BIT(10) +#define BIT_TXFOVW_MSK_8822C BIT(9) +#define BIT_FOVW_MSK_8822C BIT(8) +#define BIT_CPU_MGQ_TXDONE_MSK_8822C BIT(5) +#define BIT_PS_TIMER_C_MSK_8822C BIT(4) +#define BIT_PS_TIMER_B_MSK_8822C BIT(3) +#define BIT_PS_TIMER_A_MSK_8822C BIT(2) +#define BIT_CPUMGQ_TX_TIMER_MSK_8822C BIT(1) + +/* 2 REG_HISR1_8822C */ +#define BIT_TXFIFO_TH_INT_8822C BIT(30) +#define BIT_BTON_STS_UPDATE_INT_8822C BIT(29) +#define BIT_MCU_ERR_8822C BIT(28) +#define BIT_BCNDMAINT7_8822C BIT(27) +#define BIT_BCNDMAINT6_8822C BIT(26) +#define BIT_BCNDMAINT5_8822C BIT(25) +#define BIT_BCNDMAINT4_8822C BIT(24) +#define BIT_BCNDMAINT3_8822C BIT(23) +#define BIT_BCNDMAINT2_8822C BIT(22) +#define BIT_BCNDMAINT1_8822C BIT(21) +#define BIT_BCNDERR7_8822C BIT(20) +#define BIT_BCNDERR6_8822C BIT(19) +#define BIT_BCNDERR5_8822C BIT(18) +#define BIT_BCNDERR4_8822C BIT(17) +#define BIT_BCNDERR3_8822C BIT(16) +#define BIT_BCNDERR2_8822C BIT(15) +#define BIT_BCNDERR1_8822C BIT(14) +#define BIT_ATIMEND_E_8822C BIT(13) +#define BIT_ATIMEND_8822C BIT(12) +#define BIT_TXERR_INT_8822C BIT(11) +#define BIT_RXERR_INT_8822C BIT(10) +#define BIT_TXFOVW_8822C BIT(9) +#define BIT_FOVW_8822C BIT(8) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_CPU_MGQ_TXDONE_8822C BIT(5) +#define BIT_PS_TIMER_C_8822C BIT(4) +#define BIT_PS_TIMER_B_8822C BIT(3) +#define BIT_PS_TIMER_A_8822C BIT(2) +#define BIT_CPUMGQ_TX_TIMER_8822C BIT(1) + +/* 2 REG_DBG_PORT_SEL_8822C */ + +#define BIT_SHIFT_DEBUG_ST_8822C 0 +#define BIT_MASK_DEBUG_ST_8822C 0xffffffffL +#define BIT_DEBUG_ST_8822C(x) \ + (((x) & BIT_MASK_DEBUG_ST_8822C) << BIT_SHIFT_DEBUG_ST_8822C) +#define BITS_DEBUG_ST_8822C \ + (BIT_MASK_DEBUG_ST_8822C << BIT_SHIFT_DEBUG_ST_8822C) +#define BIT_CLEAR_DEBUG_ST_8822C(x) ((x) & (~BITS_DEBUG_ST_8822C)) +#define BIT_GET_DEBUG_ST_8822C(x) \ + (((x) >> BIT_SHIFT_DEBUG_ST_8822C) & BIT_MASK_DEBUG_ST_8822C) +#define BIT_SET_DEBUG_ST_8822C(x, v) \ + (BIT_CLEAR_DEBUG_ST_8822C(x) | BIT_DEBUG_ST_8822C(v)) + +/* 2 REG_PAD_CTRL2_8822C */ +#define BIT_USB3_USB2_TRANSITION_8822C BIT(20) + +#define BIT_SHIFT_USB23_SW_MODE_V1_8822C 18 +#define BIT_MASK_USB23_SW_MODE_V1_8822C 0x3 +#define BIT_USB23_SW_MODE_V1_8822C(x) \ + (((x) & BIT_MASK_USB23_SW_MODE_V1_8822C) \ + << BIT_SHIFT_USB23_SW_MODE_V1_8822C) +#define BITS_USB23_SW_MODE_V1_8822C \ + (BIT_MASK_USB23_SW_MODE_V1_8822C << BIT_SHIFT_USB23_SW_MODE_V1_8822C) +#define BIT_CLEAR_USB23_SW_MODE_V1_8822C(x) \ + ((x) & (~BITS_USB23_SW_MODE_V1_8822C)) +#define BIT_GET_USB23_SW_MODE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822C) & \ + BIT_MASK_USB23_SW_MODE_V1_8822C) +#define BIT_SET_USB23_SW_MODE_V1_8822C(x, v) \ + (BIT_CLEAR_USB23_SW_MODE_V1_8822C(x) | BIT_USB23_SW_MODE_V1_8822C(v)) + +#define BIT_NO_PDN_CHIPOFF_V1_8822C BIT(17) +#define BIT_RSM_EN_V1_8822C BIT(16) + +#define BIT_SHIFT_MATCH_CNT_8822C 8 +#define BIT_MASK_MATCH_CNT_8822C 0xff +#define BIT_MATCH_CNT_8822C(x) \ + (((x) & BIT_MASK_MATCH_CNT_8822C) << BIT_SHIFT_MATCH_CNT_8822C) +#define BITS_MATCH_CNT_8822C \ + (BIT_MASK_MATCH_CNT_8822C << BIT_SHIFT_MATCH_CNT_8822C) +#define BIT_CLEAR_MATCH_CNT_8822C(x) ((x) & (~BITS_MATCH_CNT_8822C)) +#define BIT_GET_MATCH_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_MATCH_CNT_8822C) & BIT_MASK_MATCH_CNT_8822C) +#define BIT_SET_MATCH_CNT_8822C(x, v) \ + (BIT_CLEAR_MATCH_CNT_8822C(x) | BIT_MATCH_CNT_8822C(v)) + +#define BIT_LD_B12V_EN_8822C BIT(7) +#define BIT_EECS_IOSEL_V1_8822C BIT(6) +#define BIT_EECS_DATA_O_V1_8822C BIT(5) +#define BIT_EECS_DATA_I_V1_8822C BIT(4) +#define BIT_EESK_IOSEL_V1_8822C BIT(2) +#define BIT_EESK_DATA_O_V1_8822C BIT(1) +#define BIT_EESK_DATA_I_V1_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_PMC_DBG_CTRL2_8822C */ + +#define BIT_SHIFT_EFUSE_BURN_GNT_8822C 24 +#define BIT_MASK_EFUSE_BURN_GNT_8822C 0xff +#define BIT_EFUSE_BURN_GNT_8822C(x) \ + (((x) & BIT_MASK_EFUSE_BURN_GNT_8822C) \ + << BIT_SHIFT_EFUSE_BURN_GNT_8822C) +#define BITS_EFUSE_BURN_GNT_8822C \ + (BIT_MASK_EFUSE_BURN_GNT_8822C << BIT_SHIFT_EFUSE_BURN_GNT_8822C) +#define BIT_CLEAR_EFUSE_BURN_GNT_8822C(x) ((x) & (~BITS_EFUSE_BURN_GNT_8822C)) +#define BIT_GET_EFUSE_BURN_GNT_8822C(x) \ + (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822C) & \ + BIT_MASK_EFUSE_BURN_GNT_8822C) +#define BIT_SET_EFUSE_BURN_GNT_8822C(x, v) \ + (BIT_CLEAR_EFUSE_BURN_GNT_8822C(x) | BIT_EFUSE_BURN_GNT_8822C(v)) + +#define BIT_STOP_WL_PMC_8822C BIT(9) +#define BIT_STOP_SYM_PMC_8822C BIT(8) +#define BIT_BT_ACCESS_WL_PAGE0_8822C BIT(6) +#define BIT_REG_RST_WLPMC_8822C BIT(5) +#define BIT_REG_RST_PD12N_8822C BIT(4) +#define BIT_SYSON_DIS_WLREG_WRMSK_8822C BIT(3) +#define BIT_SYSON_DIS_PMCREG_WRMSK_8822C BIT(2) + +#define BIT_SHIFT_SYSON_REG_ARB_8822C 0 +#define BIT_MASK_SYSON_REG_ARB_8822C 0x3 +#define BIT_SYSON_REG_ARB_8822C(x) \ + (((x) & BIT_MASK_SYSON_REG_ARB_8822C) << BIT_SHIFT_SYSON_REG_ARB_8822C) +#define BITS_SYSON_REG_ARB_8822C \ + (BIT_MASK_SYSON_REG_ARB_8822C << BIT_SHIFT_SYSON_REG_ARB_8822C) +#define BIT_CLEAR_SYSON_REG_ARB_8822C(x) ((x) & (~BITS_SYSON_REG_ARB_8822C)) +#define BIT_GET_SYSON_REG_ARB_8822C(x) \ + (((x) >> BIT_SHIFT_SYSON_REG_ARB_8822C) & BIT_MASK_SYSON_REG_ARB_8822C) +#define BIT_SET_SYSON_REG_ARB_8822C(x, v) \ + (BIT_CLEAR_SYSON_REG_ARB_8822C(x) | BIT_SYSON_REG_ARB_8822C(v)) + +/* 2 REG_BIST_CTRL_8822C */ +#define BIT_BIST_USB_DIS_8822C BIT(27) +#define BIT_BIST_PCI_DIS_8822C BIT(26) +#define BIT_BIST_BT_DIS_8822C BIT(25) +#define BIT_BIST_WL_DIS_8822C BIT(24) + +#define BIT_SHIFT_BIST_RPT_SEL_8822C 16 +#define BIT_MASK_BIST_RPT_SEL_8822C 0xf +#define BIT_BIST_RPT_SEL_8822C(x) \ + (((x) & BIT_MASK_BIST_RPT_SEL_8822C) << BIT_SHIFT_BIST_RPT_SEL_8822C) +#define BITS_BIST_RPT_SEL_8822C \ + (BIT_MASK_BIST_RPT_SEL_8822C << BIT_SHIFT_BIST_RPT_SEL_8822C) +#define BIT_CLEAR_BIST_RPT_SEL_8822C(x) ((x) & (~BITS_BIST_RPT_SEL_8822C)) +#define BIT_GET_BIST_RPT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_BIST_RPT_SEL_8822C) & BIT_MASK_BIST_RPT_SEL_8822C) +#define BIT_SET_BIST_RPT_SEL_8822C(x, v) \ + (BIT_CLEAR_BIST_RPT_SEL_8822C(x) | BIT_BIST_RPT_SEL_8822C(v)) + +#define BIT_BIST_RESUME_PS_8822C BIT(4) +#define BIT_BIST_RESUME_8822C BIT(3) +#define BIT_BIST_NORMAL_8822C BIT(2) +#define BIT_BIST_RSTN_8822C BIT(1) +#define BIT_BIST_CLK_EN_8822C BIT(0) + +/* 2 REG_BIST_RPT_8822C */ + +#define BIT_SHIFT_MBIST_REPORT_8822C 0 +#define BIT_MASK_MBIST_REPORT_8822C 0xffffffffL +#define BIT_MBIST_REPORT_8822C(x) \ + (((x) & BIT_MASK_MBIST_REPORT_8822C) << BIT_SHIFT_MBIST_REPORT_8822C) +#define BITS_MBIST_REPORT_8822C \ + (BIT_MASK_MBIST_REPORT_8822C << BIT_SHIFT_MBIST_REPORT_8822C) +#define BIT_CLEAR_MBIST_REPORT_8822C(x) ((x) & (~BITS_MBIST_REPORT_8822C)) +#define BIT_GET_MBIST_REPORT_8822C(x) \ + (((x) >> BIT_SHIFT_MBIST_REPORT_8822C) & BIT_MASK_MBIST_REPORT_8822C) +#define BIT_SET_MBIST_REPORT_8822C(x, v) \ + (BIT_CLEAR_MBIST_REPORT_8822C(x) | BIT_MBIST_REPORT_8822C(v)) + +/* 2 REG_MEM_CTRL_8822C */ +#define BIT_UMEM_RME_8822C BIT(31) + +#define BIT_SHIFT_BT_SPRAM_8822C 28 +#define BIT_MASK_BT_SPRAM_8822C 0x3 +#define BIT_BT_SPRAM_8822C(x) \ + (((x) & BIT_MASK_BT_SPRAM_8822C) << BIT_SHIFT_BT_SPRAM_8822C) +#define BITS_BT_SPRAM_8822C \ + (BIT_MASK_BT_SPRAM_8822C << BIT_SHIFT_BT_SPRAM_8822C) +#define BIT_CLEAR_BT_SPRAM_8822C(x) ((x) & (~BITS_BT_SPRAM_8822C)) +#define BIT_GET_BT_SPRAM_8822C(x) \ + (((x) >> BIT_SHIFT_BT_SPRAM_8822C) & BIT_MASK_BT_SPRAM_8822C) +#define BIT_SET_BT_SPRAM_8822C(x, v) \ + (BIT_CLEAR_BT_SPRAM_8822C(x) | BIT_BT_SPRAM_8822C(v)) + +#define BIT_SHIFT_BT_ROM_8822C 24 +#define BIT_MASK_BT_ROM_8822C 0xf +#define BIT_BT_ROM_8822C(x) \ + (((x) & BIT_MASK_BT_ROM_8822C) << BIT_SHIFT_BT_ROM_8822C) +#define BITS_BT_ROM_8822C (BIT_MASK_BT_ROM_8822C << BIT_SHIFT_BT_ROM_8822C) +#define BIT_CLEAR_BT_ROM_8822C(x) ((x) & (~BITS_BT_ROM_8822C)) +#define BIT_GET_BT_ROM_8822C(x) \ + (((x) >> BIT_SHIFT_BT_ROM_8822C) & BIT_MASK_BT_ROM_8822C) +#define BIT_SET_BT_ROM_8822C(x, v) \ + (BIT_CLEAR_BT_ROM_8822C(x) | BIT_BT_ROM_8822C(v)) + +#define BIT_SHIFT_PCI_DPRAM_8822C 10 +#define BIT_MASK_PCI_DPRAM_8822C 0x3 +#define BIT_PCI_DPRAM_8822C(x) \ + (((x) & BIT_MASK_PCI_DPRAM_8822C) << BIT_SHIFT_PCI_DPRAM_8822C) +#define BITS_PCI_DPRAM_8822C \ + (BIT_MASK_PCI_DPRAM_8822C << BIT_SHIFT_PCI_DPRAM_8822C) +#define BIT_CLEAR_PCI_DPRAM_8822C(x) ((x) & (~BITS_PCI_DPRAM_8822C)) +#define BIT_GET_PCI_DPRAM_8822C(x) \ + (((x) >> BIT_SHIFT_PCI_DPRAM_8822C) & BIT_MASK_PCI_DPRAM_8822C) +#define BIT_SET_PCI_DPRAM_8822C(x, v) \ + (BIT_CLEAR_PCI_DPRAM_8822C(x) | BIT_PCI_DPRAM_8822C(v)) + +#define BIT_SHIFT_PCI_SPRAM_8822C 8 +#define BIT_MASK_PCI_SPRAM_8822C 0x3 +#define BIT_PCI_SPRAM_8822C(x) \ + (((x) & BIT_MASK_PCI_SPRAM_8822C) << BIT_SHIFT_PCI_SPRAM_8822C) +#define BITS_PCI_SPRAM_8822C \ + (BIT_MASK_PCI_SPRAM_8822C << BIT_SHIFT_PCI_SPRAM_8822C) +#define BIT_CLEAR_PCI_SPRAM_8822C(x) ((x) & (~BITS_PCI_SPRAM_8822C)) +#define BIT_GET_PCI_SPRAM_8822C(x) \ + (((x) >> BIT_SHIFT_PCI_SPRAM_8822C) & BIT_MASK_PCI_SPRAM_8822C) +#define BIT_SET_PCI_SPRAM_8822C(x, v) \ + (BIT_CLEAR_PCI_SPRAM_8822C(x) | BIT_PCI_SPRAM_8822C(v)) + +#define BIT_SHIFT_USB_SPRAM_8822C 6 +#define BIT_MASK_USB_SPRAM_8822C 0x3 +#define BIT_USB_SPRAM_8822C(x) \ + (((x) & BIT_MASK_USB_SPRAM_8822C) << BIT_SHIFT_USB_SPRAM_8822C) +#define BITS_USB_SPRAM_8822C \ + (BIT_MASK_USB_SPRAM_8822C << BIT_SHIFT_USB_SPRAM_8822C) +#define BIT_CLEAR_USB_SPRAM_8822C(x) ((x) & (~BITS_USB_SPRAM_8822C)) +#define BIT_GET_USB_SPRAM_8822C(x) \ + (((x) >> BIT_SHIFT_USB_SPRAM_8822C) & BIT_MASK_USB_SPRAM_8822C) +#define BIT_SET_USB_SPRAM_8822C(x, v) \ + (BIT_CLEAR_USB_SPRAM_8822C(x) | BIT_USB_SPRAM_8822C(v)) + +#define BIT_SHIFT_USB_SPRF_8822C 4 +#define BIT_MASK_USB_SPRF_8822C 0x3 +#define BIT_USB_SPRF_8822C(x) \ + (((x) & BIT_MASK_USB_SPRF_8822C) << BIT_SHIFT_USB_SPRF_8822C) +#define BITS_USB_SPRF_8822C \ + (BIT_MASK_USB_SPRF_8822C << BIT_SHIFT_USB_SPRF_8822C) +#define BIT_CLEAR_USB_SPRF_8822C(x) ((x) & (~BITS_USB_SPRF_8822C)) +#define BIT_GET_USB_SPRF_8822C(x) \ + (((x) >> BIT_SHIFT_USB_SPRF_8822C) & BIT_MASK_USB_SPRF_8822C) +#define BIT_SET_USB_SPRF_8822C(x, v) \ + (BIT_CLEAR_USB_SPRF_8822C(x) | BIT_USB_SPRF_8822C(v)) + +#define BIT_SHIFT_MCU_ROM_8822C 0 +#define BIT_MASK_MCU_ROM_8822C 0xf +#define BIT_MCU_ROM_8822C(x) \ + (((x) & BIT_MASK_MCU_ROM_8822C) << BIT_SHIFT_MCU_ROM_8822C) +#define BITS_MCU_ROM_8822C (BIT_MASK_MCU_ROM_8822C << BIT_SHIFT_MCU_ROM_8822C) +#define BIT_CLEAR_MCU_ROM_8822C(x) ((x) & (~BITS_MCU_ROM_8822C)) +#define BIT_GET_MCU_ROM_8822C(x) \ + (((x) >> BIT_SHIFT_MCU_ROM_8822C) & BIT_MASK_MCU_ROM_8822C) +#define BIT_SET_MCU_ROM_8822C(x, v) \ + (BIT_CLEAR_MCU_ROM_8822C(x) | BIT_MCU_ROM_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_USB_SIE_INTF_8822C */ +#define BIT_RD_SEL_8822C BIT(31) +#define BIT_USB_SIE_INTF_WE_V1_8822C BIT(30) +#define BIT_USB_SIE_INTF_BYIOREG_V1_8822C BIT(29) +#define BIT_USB_SIE_SELECT_8822C BIT(28) + +#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C 16 +#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C 0x1ff +#define BIT_USB_SIE_INTF_ADDR_V1_8822C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C) \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C) +#define BITS_USB_SIE_INTF_ADDR_V1_8822C \ + (BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C \ + << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C) +#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822C(x) \ + ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8822C)) +#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C) & \ + BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C) +#define BIT_SET_USB_SIE_INTF_ADDR_V1_8822C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822C(x) | \ + BIT_USB_SIE_INTF_ADDR_V1_8822C(v)) + +#define BIT_SHIFT_USB_SIE_INTF_RD_8822C 8 +#define BIT_MASK_USB_SIE_INTF_RD_8822C 0xff +#define BIT_USB_SIE_INTF_RD_8822C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_RD_8822C) \ + << BIT_SHIFT_USB_SIE_INTF_RD_8822C) +#define BITS_USB_SIE_INTF_RD_8822C \ + (BIT_MASK_USB_SIE_INTF_RD_8822C << BIT_SHIFT_USB_SIE_INTF_RD_8822C) +#define BIT_CLEAR_USB_SIE_INTF_RD_8822C(x) ((x) & (~BITS_USB_SIE_INTF_RD_8822C)) +#define BIT_GET_USB_SIE_INTF_RD_8822C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822C) & \ + BIT_MASK_USB_SIE_INTF_RD_8822C) +#define BIT_SET_USB_SIE_INTF_RD_8822C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_RD_8822C(x) | BIT_USB_SIE_INTF_RD_8822C(v)) + +#define BIT_SHIFT_USB_SIE_INTF_WD_8822C 0 +#define BIT_MASK_USB_SIE_INTF_WD_8822C 0xff +#define BIT_USB_SIE_INTF_WD_8822C(x) \ + (((x) & BIT_MASK_USB_SIE_INTF_WD_8822C) \ + << BIT_SHIFT_USB_SIE_INTF_WD_8822C) +#define BITS_USB_SIE_INTF_WD_8822C \ + (BIT_MASK_USB_SIE_INTF_WD_8822C << BIT_SHIFT_USB_SIE_INTF_WD_8822C) +#define BIT_CLEAR_USB_SIE_INTF_WD_8822C(x) ((x) & (~BITS_USB_SIE_INTF_WD_8822C)) +#define BIT_GET_USB_SIE_INTF_WD_8822C(x) \ + (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822C) & \ + BIT_MASK_USB_SIE_INTF_WD_8822C) +#define BIT_SET_USB_SIE_INTF_WD_8822C(x, v) \ + (BIT_CLEAR_USB_SIE_INTF_WD_8822C(x) | BIT_USB_SIE_INTF_WD_8822C(v)) + +/* 2 REG_PCIE_MIO_INTF_8822C */ + +#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C 16 +#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C 0x3 +#define BIT_PCIE_MIO_ADDR_PAGE_8822C(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C) \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C) +#define BITS_PCIE_MIO_ADDR_PAGE_8822C \ + (BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C \ + << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C) +#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8822C(x) \ + ((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8822C)) +#define BIT_GET_PCIE_MIO_ADDR_PAGE_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C) & \ + BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C) +#define BIT_SET_PCIE_MIO_ADDR_PAGE_8822C(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8822C(x) | \ + BIT_PCIE_MIO_ADDR_PAGE_8822C(v)) + +#define BIT_PCIE_MIO_BYIOREG_8822C BIT(13) +#define BIT_PCIE_MIO_RE_8822C BIT(12) + +#define BIT_SHIFT_PCIE_MIO_WE_8822C 8 +#define BIT_MASK_PCIE_MIO_WE_8822C 0xf +#define BIT_PCIE_MIO_WE_8822C(x) \ + (((x) & BIT_MASK_PCIE_MIO_WE_8822C) << BIT_SHIFT_PCIE_MIO_WE_8822C) +#define BITS_PCIE_MIO_WE_8822C \ + (BIT_MASK_PCIE_MIO_WE_8822C << BIT_SHIFT_PCIE_MIO_WE_8822C) +#define BIT_CLEAR_PCIE_MIO_WE_8822C(x) ((x) & (~BITS_PCIE_MIO_WE_8822C)) +#define BIT_GET_PCIE_MIO_WE_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_WE_8822C) & BIT_MASK_PCIE_MIO_WE_8822C) +#define BIT_SET_PCIE_MIO_WE_8822C(x, v) \ + (BIT_CLEAR_PCIE_MIO_WE_8822C(x) | BIT_PCIE_MIO_WE_8822C(v)) + +#define BIT_SHIFT_PCIE_MIO_ADDR_8822C 0 +#define BIT_MASK_PCIE_MIO_ADDR_8822C 0xff +#define BIT_PCIE_MIO_ADDR_8822C(x) \ + (((x) & BIT_MASK_PCIE_MIO_ADDR_8822C) << BIT_SHIFT_PCIE_MIO_ADDR_8822C) +#define BITS_PCIE_MIO_ADDR_8822C \ + (BIT_MASK_PCIE_MIO_ADDR_8822C << BIT_SHIFT_PCIE_MIO_ADDR_8822C) +#define BIT_CLEAR_PCIE_MIO_ADDR_8822C(x) ((x) & (~BITS_PCIE_MIO_ADDR_8822C)) +#define BIT_GET_PCIE_MIO_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822C) & BIT_MASK_PCIE_MIO_ADDR_8822C) +#define BIT_SET_PCIE_MIO_ADDR_8822C(x, v) \ + (BIT_CLEAR_PCIE_MIO_ADDR_8822C(x) | BIT_PCIE_MIO_ADDR_8822C(v)) + +/* 2 REG_PCIE_MIO_INTD_8822C */ + +#define BIT_SHIFT_PCIE_MIO_DATA_8822C 0 +#define BIT_MASK_PCIE_MIO_DATA_8822C 0xffffffffL +#define BIT_PCIE_MIO_DATA_8822C(x) \ + (((x) & BIT_MASK_PCIE_MIO_DATA_8822C) << BIT_SHIFT_PCIE_MIO_DATA_8822C) +#define BITS_PCIE_MIO_DATA_8822C \ + (BIT_MASK_PCIE_MIO_DATA_8822C << BIT_SHIFT_PCIE_MIO_DATA_8822C) +#define BIT_CLEAR_PCIE_MIO_DATA_8822C(x) ((x) & (~BITS_PCIE_MIO_DATA_8822C)) +#define BIT_GET_PCIE_MIO_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822C) & BIT_MASK_PCIE_MIO_DATA_8822C) +#define BIT_SET_PCIE_MIO_DATA_8822C(x, v) \ + (BIT_CLEAR_PCIE_MIO_DATA_8822C(x) | BIT_PCIE_MIO_DATA_8822C(v)) + +/* 2 REG_WLRF1_8822C */ + +#define BIT_SHIFT_WLRF1_CTRL_8822C 24 +#define BIT_MASK_WLRF1_CTRL_8822C 0xff +#define BIT_WLRF1_CTRL_8822C(x) \ + (((x) & BIT_MASK_WLRF1_CTRL_8822C) << BIT_SHIFT_WLRF1_CTRL_8822C) +#define BITS_WLRF1_CTRL_8822C \ + (BIT_MASK_WLRF1_CTRL_8822C << BIT_SHIFT_WLRF1_CTRL_8822C) +#define BIT_CLEAR_WLRF1_CTRL_8822C(x) ((x) & (~BITS_WLRF1_CTRL_8822C)) +#define BIT_GET_WLRF1_CTRL_8822C(x) \ + (((x) >> BIT_SHIFT_WLRF1_CTRL_8822C) & BIT_MASK_WLRF1_CTRL_8822C) +#define BIT_SET_WLRF1_CTRL_8822C(x, v) \ + (BIT_CLEAR_WLRF1_CTRL_8822C(x) | BIT_WLRF1_CTRL_8822C(v)) + +/* 2 REG_SYS_CFG1_8822C */ + +#define BIT_SHIFT_TRP_ICFG_8822C 28 +#define BIT_MASK_TRP_ICFG_8822C 0xf +#define BIT_TRP_ICFG_8822C(x) \ + (((x) & BIT_MASK_TRP_ICFG_8822C) << BIT_SHIFT_TRP_ICFG_8822C) +#define BITS_TRP_ICFG_8822C \ + (BIT_MASK_TRP_ICFG_8822C << BIT_SHIFT_TRP_ICFG_8822C) +#define BIT_CLEAR_TRP_ICFG_8822C(x) ((x) & (~BITS_TRP_ICFG_8822C)) +#define BIT_GET_TRP_ICFG_8822C(x) \ + (((x) >> BIT_SHIFT_TRP_ICFG_8822C) & BIT_MASK_TRP_ICFG_8822C) +#define BIT_SET_TRP_ICFG_8822C(x, v) \ + (BIT_CLEAR_TRP_ICFG_8822C(x) | BIT_TRP_ICFG_8822C(v)) + +#define BIT_RF_TYPE_ID_8822C BIT(27) +#define BIT_BD_HCI_SEL_8822C BIT(26) +#define BIT_BD_PKG_SEL_8822C BIT(25) +#define BIT_INTERNAL_EXTERNAL_SWR_8822C BIT(24) +#define BIT_RTL_ID_8822C BIT(23) +#define BIT_PAD_HWPD_IDN_8822C BIT(22) +#define BIT_TESTMODE_8822C BIT(20) + +#define BIT_SHIFT_VENDOR_ID_8822C 16 +#define BIT_MASK_VENDOR_ID_8822C 0xf +#define BIT_VENDOR_ID_8822C(x) \ + (((x) & BIT_MASK_VENDOR_ID_8822C) << BIT_SHIFT_VENDOR_ID_8822C) +#define BITS_VENDOR_ID_8822C \ + (BIT_MASK_VENDOR_ID_8822C << BIT_SHIFT_VENDOR_ID_8822C) +#define BIT_CLEAR_VENDOR_ID_8822C(x) ((x) & (~BITS_VENDOR_ID_8822C)) +#define BIT_GET_VENDOR_ID_8822C(x) \ + (((x) >> BIT_SHIFT_VENDOR_ID_8822C) & BIT_MASK_VENDOR_ID_8822C) +#define BIT_SET_VENDOR_ID_8822C(x, v) \ + (BIT_CLEAR_VENDOR_ID_8822C(x) | BIT_VENDOR_ID_8822C(v)) + +#define BIT_SHIFT_CHIP_VER_8822C 12 +#define BIT_MASK_CHIP_VER_8822C 0xf +#define BIT_CHIP_VER_8822C(x) \ + (((x) & BIT_MASK_CHIP_VER_8822C) << BIT_SHIFT_CHIP_VER_8822C) +#define BITS_CHIP_VER_8822C \ + (BIT_MASK_CHIP_VER_8822C << BIT_SHIFT_CHIP_VER_8822C) +#define BIT_CLEAR_CHIP_VER_8822C(x) ((x) & (~BITS_CHIP_VER_8822C)) +#define BIT_GET_CHIP_VER_8822C(x) \ + (((x) >> BIT_SHIFT_CHIP_VER_8822C) & BIT_MASK_CHIP_VER_8822C) +#define BIT_SET_CHIP_VER_8822C(x, v) \ + (BIT_CLEAR_CHIP_VER_8822C(x) | BIT_CHIP_VER_8822C(v)) + +#define BIT_BD_MAC3_8822C BIT(11) +#define BIT_BD_MAC1_8822C BIT(10) +#define BIT_BD_MAC2_8822C BIT(9) +#define BIT_SIC_IDLE_8822C BIT(8) +#define BIT_SW_OFFLOAD_EN_8822C BIT(7) +#define BIT_OCP_SHUTDN_8822C BIT(6) +#define BIT_V15_VLD_8822C BIT(5) +#define BIT_PCIRSTB_8822C BIT(4) +#define BIT_PCLK_VLD_8822C BIT(3) +#define BIT_UCLK_VLD_8822C BIT(2) +#define BIT_ACLK_VLD_8822C BIT(1) +#define BIT_XCLK_VLD_8822C BIT(0) + +/* 2 REG_SYS_STATUS1_8822C */ + +#define BIT_SHIFT_RF_RL_ID_8822C 28 +#define BIT_MASK_RF_RL_ID_8822C 0xf +#define BIT_RF_RL_ID_8822C(x) \ + (((x) & BIT_MASK_RF_RL_ID_8822C) << BIT_SHIFT_RF_RL_ID_8822C) +#define BITS_RF_RL_ID_8822C \ + (BIT_MASK_RF_RL_ID_8822C << BIT_SHIFT_RF_RL_ID_8822C) +#define BIT_CLEAR_RF_RL_ID_8822C(x) ((x) & (~BITS_RF_RL_ID_8822C)) +#define BIT_GET_RF_RL_ID_8822C(x) \ + (((x) >> BIT_SHIFT_RF_RL_ID_8822C) & BIT_MASK_RF_RL_ID_8822C) +#define BIT_SET_RF_RL_ID_8822C(x, v) \ + (BIT_CLEAR_RF_RL_ID_8822C(x) | BIT_RF_RL_ID_8822C(v)) + +#define BIT_HPHY_ICFG_8822C BIT(19) + +#define BIT_SHIFT_SEL_0XC0_8822C 16 +#define BIT_MASK_SEL_0XC0_8822C 0x3 +#define BIT_SEL_0XC0_8822C(x) \ + (((x) & BIT_MASK_SEL_0XC0_8822C) << BIT_SHIFT_SEL_0XC0_8822C) +#define BITS_SEL_0XC0_8822C \ + (BIT_MASK_SEL_0XC0_8822C << BIT_SHIFT_SEL_0XC0_8822C) +#define BIT_CLEAR_SEL_0XC0_8822C(x) ((x) & (~BITS_SEL_0XC0_8822C)) +#define BIT_GET_SEL_0XC0_8822C(x) \ + (((x) >> BIT_SHIFT_SEL_0XC0_8822C) & BIT_MASK_SEL_0XC0_8822C) +#define BIT_SET_SEL_0XC0_8822C(x, v) \ + (BIT_CLEAR_SEL_0XC0_8822C(x) | BIT_SEL_0XC0_8822C(v)) + +#define BIT_SHIFT_HCI_SEL_V4_8822C 12 +#define BIT_MASK_HCI_SEL_V4_8822C 0x3 +#define BIT_HCI_SEL_V4_8822C(x) \ + (((x) & BIT_MASK_HCI_SEL_V4_8822C) << BIT_SHIFT_HCI_SEL_V4_8822C) +#define BITS_HCI_SEL_V4_8822C \ + (BIT_MASK_HCI_SEL_V4_8822C << BIT_SHIFT_HCI_SEL_V4_8822C) +#define BIT_CLEAR_HCI_SEL_V4_8822C(x) ((x) & (~BITS_HCI_SEL_V4_8822C)) +#define BIT_GET_HCI_SEL_V4_8822C(x) \ + (((x) >> BIT_SHIFT_HCI_SEL_V4_8822C) & BIT_MASK_HCI_SEL_V4_8822C) +#define BIT_SET_HCI_SEL_V4_8822C(x, v) \ + (BIT_CLEAR_HCI_SEL_V4_8822C(x) | BIT_HCI_SEL_V4_8822C(v)) + +#define BIT_USB_OPERATION_MODE_8822C BIT(10) +#define BIT_BT_PDN_8822C BIT(9) +#define BIT_AUTO_WLPON_8822C BIT(8) +#define BIT_WL_MODE_8822C BIT(7) +#define BIT_PKG_SEL_HCI_8822C BIT(6) + +#define BIT_SHIFT_PAD_HCI_SEL_V2_8822C 3 +#define BIT_MASK_PAD_HCI_SEL_V2_8822C 0x3 +#define BIT_PAD_HCI_SEL_V2_8822C(x) \ + (((x) & BIT_MASK_PAD_HCI_SEL_V2_8822C) \ + << BIT_SHIFT_PAD_HCI_SEL_V2_8822C) +#define BITS_PAD_HCI_SEL_V2_8822C \ + (BIT_MASK_PAD_HCI_SEL_V2_8822C << BIT_SHIFT_PAD_HCI_SEL_V2_8822C) +#define BIT_CLEAR_PAD_HCI_SEL_V2_8822C(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8822C)) +#define BIT_GET_PAD_HCI_SEL_V2_8822C(x) \ + (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8822C) & \ + BIT_MASK_PAD_HCI_SEL_V2_8822C) +#define BIT_SET_PAD_HCI_SEL_V2_8822C(x, v) \ + (BIT_CLEAR_PAD_HCI_SEL_V2_8822C(x) | BIT_PAD_HCI_SEL_V2_8822C(v)) + +#define BIT_SHIFT_EFS_HCI_SEL_V1_8822C 0 +#define BIT_MASK_EFS_HCI_SEL_V1_8822C 0x7 +#define BIT_EFS_HCI_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_EFS_HCI_SEL_V1_8822C) \ + << BIT_SHIFT_EFS_HCI_SEL_V1_8822C) +#define BITS_EFS_HCI_SEL_V1_8822C \ + (BIT_MASK_EFS_HCI_SEL_V1_8822C << BIT_SHIFT_EFS_HCI_SEL_V1_8822C) +#define BIT_CLEAR_EFS_HCI_SEL_V1_8822C(x) ((x) & (~BITS_EFS_HCI_SEL_V1_8822C)) +#define BIT_GET_EFS_HCI_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822C) & \ + BIT_MASK_EFS_HCI_SEL_V1_8822C) +#define BIT_SET_EFS_HCI_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_EFS_HCI_SEL_V1_8822C(x) | BIT_EFS_HCI_SEL_V1_8822C(v)) + +/* 2 REG_SYS_STATUS2_8822C */ +#define BIT_HIOE_ON_TIMEOUT_8822C BIT(23) +#define BIT_SIC_ON_TIMEOUT_8822C BIT(22) +#define BIT_CPU_ON_TIMEOUT_8822C BIT(21) +#define BIT_HCI_ON_TIMEOUT_8822C BIT(20) +#define BIT_SIO_ALDN_8822C BIT(19) +#define BIT_USB_ALDN_8822C BIT(18) +#define BIT_PCI_ALDN_8822C BIT(17) +#define BIT_SYS_ALDN_8822C BIT(16) + +#define BIT_SHIFT_EPVID1_8822C 8 +#define BIT_MASK_EPVID1_8822C 0xff +#define BIT_EPVID1_8822C(x) \ + (((x) & BIT_MASK_EPVID1_8822C) << BIT_SHIFT_EPVID1_8822C) +#define BITS_EPVID1_8822C (BIT_MASK_EPVID1_8822C << BIT_SHIFT_EPVID1_8822C) +#define BIT_CLEAR_EPVID1_8822C(x) ((x) & (~BITS_EPVID1_8822C)) +#define BIT_GET_EPVID1_8822C(x) \ + (((x) >> BIT_SHIFT_EPVID1_8822C) & BIT_MASK_EPVID1_8822C) +#define BIT_SET_EPVID1_8822C(x, v) \ + (BIT_CLEAR_EPVID1_8822C(x) | BIT_EPVID1_8822C(v)) + +#define BIT_SHIFT_EPVID0_8822C 0 +#define BIT_MASK_EPVID0_8822C 0xff +#define BIT_EPVID0_8822C(x) \ + (((x) & BIT_MASK_EPVID0_8822C) << BIT_SHIFT_EPVID0_8822C) +#define BITS_EPVID0_8822C (BIT_MASK_EPVID0_8822C << BIT_SHIFT_EPVID0_8822C) +#define BIT_CLEAR_EPVID0_8822C(x) ((x) & (~BITS_EPVID0_8822C)) +#define BIT_GET_EPVID0_8822C(x) \ + (((x) >> BIT_SHIFT_EPVID0_8822C) & BIT_MASK_EPVID0_8822C) +#define BIT_SET_EPVID0_8822C(x, v) \ + (BIT_CLEAR_EPVID0_8822C(x) | BIT_EPVID0_8822C(v)) + +/* 2 REG_SYS_CFG2_8822C */ +#define BIT_HCI_SEL_EMBEDDED_8822C BIT(8) + +#define BIT_SHIFT_HW_ID_8822C 0 +#define BIT_MASK_HW_ID_8822C 0xff +#define BIT_HW_ID_8822C(x) \ + (((x) & BIT_MASK_HW_ID_8822C) << BIT_SHIFT_HW_ID_8822C) +#define BITS_HW_ID_8822C (BIT_MASK_HW_ID_8822C << BIT_SHIFT_HW_ID_8822C) +#define BIT_CLEAR_HW_ID_8822C(x) ((x) & (~BITS_HW_ID_8822C)) +#define BIT_GET_HW_ID_8822C(x) \ + (((x) >> BIT_SHIFT_HW_ID_8822C) & BIT_MASK_HW_ID_8822C) +#define BIT_SET_HW_ID_8822C(x, v) \ + (BIT_CLEAR_HW_ID_8822C(x) | BIT_HW_ID_8822C(v)) + +/* 2 REG_SYS_CFG3_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ANAPARSW_MAC_0_8822C */ +#define BIT_OCP_L_8822C BIT(31) +#define BIT_POWOCP_L_8822C BIT(30) + +#define BIT_SHIFT_CF_L_V2_8822C 28 +#define BIT_MASK_CF_L_V2_8822C 0x3 +#define BIT_CF_L_V2_8822C(x) \ + (((x) & BIT_MASK_CF_L_V2_8822C) << BIT_SHIFT_CF_L_V2_8822C) +#define BITS_CF_L_V2_8822C (BIT_MASK_CF_L_V2_8822C << BIT_SHIFT_CF_L_V2_8822C) +#define BIT_CLEAR_CF_L_V2_8822C(x) ((x) & (~BITS_CF_L_V2_8822C)) +#define BIT_GET_CF_L_V2_8822C(x) \ + (((x) >> BIT_SHIFT_CF_L_V2_8822C) & BIT_MASK_CF_L_V2_8822C) +#define BIT_SET_CF_L_V2_8822C(x, v) \ + (BIT_CLEAR_CF_L_V2_8822C(x) | BIT_CF_L_V2_8822C(v)) + +#define BIT_SHIFT_CFC_L_V2_8822C 26 +#define BIT_MASK_CFC_L_V2_8822C 0x3 +#define BIT_CFC_L_V2_8822C(x) \ + (((x) & BIT_MASK_CFC_L_V2_8822C) << BIT_SHIFT_CFC_L_V2_8822C) +#define BITS_CFC_L_V2_8822C \ + (BIT_MASK_CFC_L_V2_8822C << BIT_SHIFT_CFC_L_V2_8822C) +#define BIT_CLEAR_CFC_L_V2_8822C(x) ((x) & (~BITS_CFC_L_V2_8822C)) +#define BIT_GET_CFC_L_V2_8822C(x) \ + (((x) >> BIT_SHIFT_CFC_L_V2_8822C) & BIT_MASK_CFC_L_V2_8822C) +#define BIT_SET_CFC_L_V2_8822C(x, v) \ + (BIT_CLEAR_CFC_L_V2_8822C(x) | BIT_CFC_L_V2_8822C(v)) + +#define BIT_SHIFT_R3_L_V2_8822C 24 +#define BIT_MASK_R3_L_V2_8822C 0x3 +#define BIT_R3_L_V2_8822C(x) \ + (((x) & BIT_MASK_R3_L_V2_8822C) << BIT_SHIFT_R3_L_V2_8822C) +#define BITS_R3_L_V2_8822C (BIT_MASK_R3_L_V2_8822C << BIT_SHIFT_R3_L_V2_8822C) +#define BIT_CLEAR_R3_L_V2_8822C(x) ((x) & (~BITS_R3_L_V2_8822C)) +#define BIT_GET_R3_L_V2_8822C(x) \ + (((x) >> BIT_SHIFT_R3_L_V2_8822C) & BIT_MASK_R3_L_V2_8822C) +#define BIT_SET_R3_L_V2_8822C(x, v) \ + (BIT_CLEAR_R3_L_V2_8822C(x) | BIT_R3_L_V2_8822C(v)) + +#define BIT_SHIFT_R2_L_8822C 22 +#define BIT_MASK_R2_L_8822C 0x3 +#define BIT_R2_L_8822C(x) (((x) & BIT_MASK_R2_L_8822C) << BIT_SHIFT_R2_L_8822C) +#define BITS_R2_L_8822C (BIT_MASK_R2_L_8822C << BIT_SHIFT_R2_L_8822C) +#define BIT_CLEAR_R2_L_8822C(x) ((x) & (~BITS_R2_L_8822C)) +#define BIT_GET_R2_L_8822C(x) \ + (((x) >> BIT_SHIFT_R2_L_8822C) & BIT_MASK_R2_L_8822C) +#define BIT_SET_R2_L_8822C(x, v) (BIT_CLEAR_R2_L_8822C(x) | BIT_R2_L_8822C(v)) + +#define BIT_SHIFT_R1_L_8822C 20 +#define BIT_MASK_R1_L_8822C 0x3 +#define BIT_R1_L_8822C(x) (((x) & BIT_MASK_R1_L_8822C) << BIT_SHIFT_R1_L_8822C) +#define BITS_R1_L_8822C (BIT_MASK_R1_L_8822C << BIT_SHIFT_R1_L_8822C) +#define BIT_CLEAR_R1_L_8822C(x) ((x) & (~BITS_R1_L_8822C)) +#define BIT_GET_R1_L_8822C(x) \ + (((x) >> BIT_SHIFT_R1_L_8822C) & BIT_MASK_R1_L_8822C) +#define BIT_SET_R1_L_8822C(x, v) (BIT_CLEAR_R1_L_8822C(x) | BIT_R1_L_8822C(v)) + +#define BIT_SHIFT_C3_L_8822C 18 +#define BIT_MASK_C3_L_8822C 0x3 +#define BIT_C3_L_8822C(x) (((x) & BIT_MASK_C3_L_8822C) << BIT_SHIFT_C3_L_8822C) +#define BITS_C3_L_8822C (BIT_MASK_C3_L_8822C << BIT_SHIFT_C3_L_8822C) +#define BIT_CLEAR_C3_L_8822C(x) ((x) & (~BITS_C3_L_8822C)) +#define BIT_GET_C3_L_8822C(x) \ + (((x) >> BIT_SHIFT_C3_L_8822C) & BIT_MASK_C3_L_8822C) +#define BIT_SET_C3_L_8822C(x, v) (BIT_CLEAR_C3_L_8822C(x) | BIT_C3_L_8822C(v)) + +#define BIT_SHIFT_C2_L_8822C 16 +#define BIT_MASK_C2_L_8822C 0x3 +#define BIT_C2_L_8822C(x) (((x) & BIT_MASK_C2_L_8822C) << BIT_SHIFT_C2_L_8822C) +#define BITS_C2_L_8822C (BIT_MASK_C2_L_8822C << BIT_SHIFT_C2_L_8822C) +#define BIT_CLEAR_C2_L_8822C(x) ((x) & (~BITS_C2_L_8822C)) +#define BIT_GET_C2_L_8822C(x) \ + (((x) >> BIT_SHIFT_C2_L_8822C) & BIT_MASK_C2_L_8822C) +#define BIT_SET_C2_L_8822C(x, v) (BIT_CLEAR_C2_L_8822C(x) | BIT_C2_L_8822C(v)) + +#define BIT_SHIFT_C1_L_V2_8822C 14 +#define BIT_MASK_C1_L_V2_8822C 0x3 +#define BIT_C1_L_V2_8822C(x) \ + (((x) & BIT_MASK_C1_L_V2_8822C) << BIT_SHIFT_C1_L_V2_8822C) +#define BITS_C1_L_V2_8822C (BIT_MASK_C1_L_V2_8822C << BIT_SHIFT_C1_L_V2_8822C) +#define BIT_CLEAR_C1_L_V2_8822C(x) ((x) & (~BITS_C1_L_V2_8822C)) +#define BIT_GET_C1_L_V2_8822C(x) \ + (((x) >> BIT_SHIFT_C1_L_V2_8822C) & BIT_MASK_C1_L_V2_8822C) +#define BIT_SET_C1_L_V2_8822C(x, v) \ + (BIT_CLEAR_C1_L_V2_8822C(x) | BIT_C1_L_V2_8822C(v)) + +#define BIT_REG_OCPS_L_V2_8822C BIT(13) +#define BIT_REG_PWM_L_8822C BIT(12) + +#define BIT_SHIFT_V15ADJ_L_8822C 9 +#define BIT_MASK_V15ADJ_L_8822C 0x7 +#define BIT_V15ADJ_L_8822C(x) \ + (((x) & BIT_MASK_V15ADJ_L_8822C) << BIT_SHIFT_V15ADJ_L_8822C) +#define BITS_V15ADJ_L_8822C \ + (BIT_MASK_V15ADJ_L_8822C << BIT_SHIFT_V15ADJ_L_8822C) +#define BIT_CLEAR_V15ADJ_L_8822C(x) ((x) & (~BITS_V15ADJ_L_8822C)) +#define BIT_GET_V15ADJ_L_8822C(x) \ + (((x) >> BIT_SHIFT_V15ADJ_L_8822C) & BIT_MASK_V15ADJ_L_8822C) +#define BIT_SET_V15ADJ_L_8822C(x, v) \ + (BIT_CLEAR_V15ADJ_L_8822C(x) | BIT_V15ADJ_L_8822C(v)) + +#define BIT_SHIFT_IN_L_8822C 6 +#define BIT_MASK_IN_L_8822C 0x7 +#define BIT_IN_L_8822C(x) (((x) & BIT_MASK_IN_L_8822C) << BIT_SHIFT_IN_L_8822C) +#define BITS_IN_L_8822C (BIT_MASK_IN_L_8822C << BIT_SHIFT_IN_L_8822C) +#define BIT_CLEAR_IN_L_8822C(x) ((x) & (~BITS_IN_L_8822C)) +#define BIT_GET_IN_L_8822C(x) \ + (((x) >> BIT_SHIFT_IN_L_8822C) & BIT_MASK_IN_L_8822C) +#define BIT_SET_IN_L_8822C(x, v) (BIT_CLEAR_IN_L_8822C(x) | BIT_IN_L_8822C(v)) + +#define BIT_SHIFT_STD_L_8822C 4 +#define BIT_MASK_STD_L_8822C 0x3 +#define BIT_STD_L_8822C(x) \ + (((x) & BIT_MASK_STD_L_8822C) << BIT_SHIFT_STD_L_8822C) +#define BITS_STD_L_8822C (BIT_MASK_STD_L_8822C << BIT_SHIFT_STD_L_8822C) +#define BIT_CLEAR_STD_L_8822C(x) ((x) & (~BITS_STD_L_8822C)) +#define BIT_GET_STD_L_8822C(x) \ + (((x) >> BIT_SHIFT_STD_L_8822C) & BIT_MASK_STD_L_8822C) +#define BIT_SET_STD_L_8822C(x, v) \ + (BIT_CLEAR_STD_L_8822C(x) | BIT_STD_L_8822C(v)) + +#define BIT_SHIFT_VOL_L_8822C 0 +#define BIT_MASK_VOL_L_8822C 0xf +#define BIT_VOL_L_8822C(x) \ + (((x) & BIT_MASK_VOL_L_8822C) << BIT_SHIFT_VOL_L_8822C) +#define BITS_VOL_L_8822C (BIT_MASK_VOL_L_8822C << BIT_SHIFT_VOL_L_8822C) +#define BIT_CLEAR_VOL_L_8822C(x) ((x) & (~BITS_VOL_L_8822C)) +#define BIT_GET_VOL_L_8822C(x) \ + (((x) >> BIT_SHIFT_VOL_L_8822C) & BIT_MASK_VOL_L_8822C) +#define BIT_SET_VOL_L_8822C(x, v) \ + (BIT_CLEAR_VOL_L_8822C(x) | BIT_VOL_L_8822C(v)) + +/* 2 REG_ANAPARSW_MAC_1_8822C */ + +#define BIT_SHIFT_OCP_L_PFM_8822C 29 +#define BIT_MASK_OCP_L_PFM_8822C 0x7 +#define BIT_OCP_L_PFM_8822C(x) \ + (((x) & BIT_MASK_OCP_L_PFM_8822C) << BIT_SHIFT_OCP_L_PFM_8822C) +#define BITS_OCP_L_PFM_8822C \ + (BIT_MASK_OCP_L_PFM_8822C << BIT_SHIFT_OCP_L_PFM_8822C) +#define BIT_CLEAR_OCP_L_PFM_8822C(x) ((x) & (~BITS_OCP_L_PFM_8822C)) +#define BIT_GET_OCP_L_PFM_8822C(x) \ + (((x) >> BIT_SHIFT_OCP_L_PFM_8822C) & BIT_MASK_OCP_L_PFM_8822C) +#define BIT_SET_OCP_L_PFM_8822C(x, v) \ + (BIT_CLEAR_OCP_L_PFM_8822C(x) | BIT_OCP_L_PFM_8822C(v)) + +#define BIT_SHIFT_CFC_L_PFM_8822C 27 +#define BIT_MASK_CFC_L_PFM_8822C 0x3 +#define BIT_CFC_L_PFM_8822C(x) \ + (((x) & BIT_MASK_CFC_L_PFM_8822C) << BIT_SHIFT_CFC_L_PFM_8822C) +#define BITS_CFC_L_PFM_8822C \ + (BIT_MASK_CFC_L_PFM_8822C << BIT_SHIFT_CFC_L_PFM_8822C) +#define BIT_CLEAR_CFC_L_PFM_8822C(x) ((x) & (~BITS_CFC_L_PFM_8822C)) +#define BIT_GET_CFC_L_PFM_8822C(x) \ + (((x) >> BIT_SHIFT_CFC_L_PFM_8822C) & BIT_MASK_CFC_L_PFM_8822C) +#define BIT_SET_CFC_L_PFM_8822C(x, v) \ + (BIT_CLEAR_CFC_L_PFM_8822C(x) | BIT_CFC_L_PFM_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_REG_FREQ_L_V1_8822C 20 +#define BIT_MASK_REG_FREQ_L_V1_8822C 0x7 +#define BIT_REG_FREQ_L_V1_8822C(x) \ + (((x) & BIT_MASK_REG_FREQ_L_V1_8822C) << BIT_SHIFT_REG_FREQ_L_V1_8822C) +#define BITS_REG_FREQ_L_V1_8822C \ + (BIT_MASK_REG_FREQ_L_V1_8822C << BIT_SHIFT_REG_FREQ_L_V1_8822C) +#define BIT_CLEAR_REG_FREQ_L_V1_8822C(x) ((x) & (~BITS_REG_FREQ_L_V1_8822C)) +#define BIT_GET_REG_FREQ_L_V1_8822C(x) \ + (((x) >> BIT_SHIFT_REG_FREQ_L_V1_8822C) & BIT_MASK_REG_FREQ_L_V1_8822C) +#define BIT_SET_REG_FREQ_L_V1_8822C(x, v) \ + (BIT_CLEAR_REG_FREQ_L_V1_8822C(x) | BIT_REG_FREQ_L_V1_8822C(v)) + +#define BIT_EN_DUTY_8822C BIT(19) + +#define BIT_SHIFT_REG_MODE_V2_8822C 17 +#define BIT_MASK_REG_MODE_V2_8822C 0x3 +#define BIT_REG_MODE_V2_8822C(x) \ + (((x) & BIT_MASK_REG_MODE_V2_8822C) << BIT_SHIFT_REG_MODE_V2_8822C) +#define BITS_REG_MODE_V2_8822C \ + (BIT_MASK_REG_MODE_V2_8822C << BIT_SHIFT_REG_MODE_V2_8822C) +#define BIT_CLEAR_REG_MODE_V2_8822C(x) ((x) & (~BITS_REG_MODE_V2_8822C)) +#define BIT_GET_REG_MODE_V2_8822C(x) \ + (((x) >> BIT_SHIFT_REG_MODE_V2_8822C) & BIT_MASK_REG_MODE_V2_8822C) +#define BIT_SET_REG_MODE_V2_8822C(x, v) \ + (BIT_CLEAR_REG_MODE_V2_8822C(x) | BIT_REG_MODE_V2_8822C(v)) + +#define BIT_EN_SP_8822C BIT(16) +#define BIT_REG_AUTO_L_V2_8822C BIT(15) +#define BIT_REG_LDOF_L_V2_8822C BIT(14) +#define BIT_REG_TYPE_L_V2_8822C BIT(13) +#define BIT_VO15_V1P05_H_8822C BIT(12) +#define BIT_ARENB_L_V2_8822C BIT(11) + +#define BIT_SHIFT_TBOX_L1_V2_8822C 9 +#define BIT_MASK_TBOX_L1_V2_8822C 0x3 +#define BIT_TBOX_L1_V2_8822C(x) \ + (((x) & BIT_MASK_TBOX_L1_V2_8822C) << BIT_SHIFT_TBOX_L1_V2_8822C) +#define BITS_TBOX_L1_V2_8822C \ + (BIT_MASK_TBOX_L1_V2_8822C << BIT_SHIFT_TBOX_L1_V2_8822C) +#define BIT_CLEAR_TBOX_L1_V2_8822C(x) ((x) & (~BITS_TBOX_L1_V2_8822C)) +#define BIT_GET_TBOX_L1_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TBOX_L1_V2_8822C) & BIT_MASK_TBOX_L1_V2_8822C) +#define BIT_SET_TBOX_L1_V2_8822C(x, v) \ + (BIT_CLEAR_TBOX_L1_V2_8822C(x) | BIT_TBOX_L1_V2_8822C(v)) + +#define BIT_SHIFT_REG_DELAY_L_8822C 7 +#define BIT_MASK_REG_DELAY_L_8822C 0x3 +#define BIT_REG_DELAY_L_8822C(x) \ + (((x) & BIT_MASK_REG_DELAY_L_8822C) << BIT_SHIFT_REG_DELAY_L_8822C) +#define BITS_REG_DELAY_L_8822C \ + (BIT_MASK_REG_DELAY_L_8822C << BIT_SHIFT_REG_DELAY_L_8822C) +#define BIT_CLEAR_REG_DELAY_L_8822C(x) ((x) & (~BITS_REG_DELAY_L_8822C)) +#define BIT_GET_REG_DELAY_L_8822C(x) \ + (((x) >> BIT_SHIFT_REG_DELAY_L_8822C) & BIT_MASK_REG_DELAY_L_8822C) +#define BIT_SET_REG_DELAY_L_8822C(x, v) \ + (BIT_CLEAR_REG_DELAY_L_8822C(x) | BIT_REG_DELAY_L_8822C(v)) + +#define BIT_REG_CLAMP_D_L_8822C BIT(6) +#define BIT_REG_BYPASS_L_V2_8822C BIT(5) +#define BIT_REG_AUTOZCD_L_8822C BIT(4) +#define BIT_POW_ZCD_L_V2_8822C BIT(3) +#define BIT_REG_HALF_L_8822C BIT(2) + +#define BIT_SHIFT_OCP_L_V2_8822C 0 +#define BIT_MASK_OCP_L_V2_8822C 0x3 +#define BIT_OCP_L_V2_8822C(x) \ + (((x) & BIT_MASK_OCP_L_V2_8822C) << BIT_SHIFT_OCP_L_V2_8822C) +#define BITS_OCP_L_V2_8822C \ + (BIT_MASK_OCP_L_V2_8822C << BIT_SHIFT_OCP_L_V2_8822C) +#define BIT_CLEAR_OCP_L_V2_8822C(x) ((x) & (~BITS_OCP_L_V2_8822C)) +#define BIT_GET_OCP_L_V2_8822C(x) \ + (((x) >> BIT_SHIFT_OCP_L_V2_8822C) & BIT_MASK_OCP_L_V2_8822C) +#define BIT_SET_OCP_L_V2_8822C(x, v) \ + (BIT_CLEAR_OCP_L_V2_8822C(x) | BIT_OCP_L_V2_8822C(v)) + +/* 2 REG_ANAPAR_MAC_0_8822C */ + +#define BIT_SHIFT_REG_LPF_R3_8822C 29 +#define BIT_MASK_REG_LPF_R3_8822C 0x7 +#define BIT_REG_LPF_R3_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_R3_8822C) << BIT_SHIFT_REG_LPF_R3_8822C) +#define BITS_REG_LPF_R3_8822C \ + (BIT_MASK_REG_LPF_R3_8822C << BIT_SHIFT_REG_LPF_R3_8822C) +#define BIT_CLEAR_REG_LPF_R3_8822C(x) ((x) & (~BITS_REG_LPF_R3_8822C)) +#define BIT_GET_REG_LPF_R3_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3_8822C) & BIT_MASK_REG_LPF_R3_8822C) +#define BIT_SET_REG_LPF_R3_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_R3_8822C(x) | BIT_REG_LPF_R3_8822C(v)) + +#define BIT_SHIFT_REG_LPF_R2_8822C 24 +#define BIT_MASK_REG_LPF_R2_8822C 0x1f +#define BIT_REG_LPF_R2_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_R2_8822C) << BIT_SHIFT_REG_LPF_R2_8822C) +#define BITS_REG_LPF_R2_8822C \ + (BIT_MASK_REG_LPF_R2_8822C << BIT_SHIFT_REG_LPF_R2_8822C) +#define BIT_CLEAR_REG_LPF_R2_8822C(x) ((x) & (~BITS_REG_LPF_R2_8822C)) +#define BIT_GET_REG_LPF_R2_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R2_8822C) & BIT_MASK_REG_LPF_R2_8822C) +#define BIT_SET_REG_LPF_R2_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_R2_8822C(x) | BIT_REG_LPF_R2_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C3_8822C 21 +#define BIT_MASK_REG_LPF_C3_8822C 0x7 +#define BIT_REG_LPF_C3_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C3_8822C) << BIT_SHIFT_REG_LPF_C3_8822C) +#define BITS_REG_LPF_C3_8822C \ + (BIT_MASK_REG_LPF_C3_8822C << BIT_SHIFT_REG_LPF_C3_8822C) +#define BIT_CLEAR_REG_LPF_C3_8822C(x) ((x) & (~BITS_REG_LPF_C3_8822C)) +#define BIT_GET_REG_LPF_C3_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C3_8822C) & BIT_MASK_REG_LPF_C3_8822C) +#define BIT_SET_REG_LPF_C3_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C3_8822C(x) | BIT_REG_LPF_C3_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C2_8822C 18 +#define BIT_MASK_REG_LPF_C2_8822C 0x7 +#define BIT_REG_LPF_C2_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C2_8822C) << BIT_SHIFT_REG_LPF_C2_8822C) +#define BITS_REG_LPF_C2_8822C \ + (BIT_MASK_REG_LPF_C2_8822C << BIT_SHIFT_REG_LPF_C2_8822C) +#define BIT_CLEAR_REG_LPF_C2_8822C(x) ((x) & (~BITS_REG_LPF_C2_8822C)) +#define BIT_GET_REG_LPF_C2_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C2_8822C) & BIT_MASK_REG_LPF_C2_8822C) +#define BIT_SET_REG_LPF_C2_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C2_8822C(x) | BIT_REG_LPF_C2_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C1_8822C 15 +#define BIT_MASK_REG_LPF_C1_8822C 0x7 +#define BIT_REG_LPF_C1_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C1_8822C) << BIT_SHIFT_REG_LPF_C1_8822C) +#define BITS_REG_LPF_C1_8822C \ + (BIT_MASK_REG_LPF_C1_8822C << BIT_SHIFT_REG_LPF_C1_8822C) +#define BIT_CLEAR_REG_LPF_C1_8822C(x) ((x) & (~BITS_REG_LPF_C1_8822C)) +#define BIT_GET_REG_LPF_C1_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C1_8822C) & BIT_MASK_REG_LPF_C1_8822C) +#define BIT_SET_REG_LPF_C1_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C1_8822C(x) | BIT_REG_LPF_C1_8822C(v)) + +#define BIT_SHIFT_REG_LDO_SEL_V1_8822C 13 +#define BIT_MASK_REG_LDO_SEL_V1_8822C 0x3 +#define BIT_REG_LDO_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_REG_LDO_SEL_V1_8822C) \ + << BIT_SHIFT_REG_LDO_SEL_V1_8822C) +#define BITS_REG_LDO_SEL_V1_8822C \ + (BIT_MASK_REG_LDO_SEL_V1_8822C << BIT_SHIFT_REG_LDO_SEL_V1_8822C) +#define BIT_CLEAR_REG_LDO_SEL_V1_8822C(x) ((x) & (~BITS_REG_LDO_SEL_V1_8822C)) +#define BIT_GET_REG_LDO_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LDO_SEL_V1_8822C) & \ + BIT_MASK_REG_LDO_SEL_V1_8822C) +#define BIT_SET_REG_LDO_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_REG_LDO_SEL_V1_8822C(x) | BIT_REG_LDO_SEL_V1_8822C(v)) + +#define BIT_REG_CP_ICPX2_8822C BIT(12) + +#define BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C 9 +#define BIT_MASK_REG_CP_ICP_SEL_FAST_8822C 0x7 +#define BIT_REG_CP_ICP_SEL_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_CP_ICP_SEL_FAST_8822C) \ + << BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C) +#define BITS_REG_CP_ICP_SEL_FAST_8822C \ + (BIT_MASK_REG_CP_ICP_SEL_FAST_8822C \ + << BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C) +#define BIT_CLEAR_REG_CP_ICP_SEL_FAST_8822C(x) \ + ((x) & (~BITS_REG_CP_ICP_SEL_FAST_8822C)) +#define BIT_GET_REG_CP_ICP_SEL_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C) & \ + BIT_MASK_REG_CP_ICP_SEL_FAST_8822C) +#define BIT_SET_REG_CP_ICP_SEL_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_CP_ICP_SEL_FAST_8822C(x) | \ + BIT_REG_CP_ICP_SEL_FAST_8822C(v)) + +#define BIT_SHIFT_REG_CP_ICP_SEL_8822C 6 +#define BIT_MASK_REG_CP_ICP_SEL_8822C 0x7 +#define BIT_REG_CP_ICP_SEL_8822C(x) \ + (((x) & BIT_MASK_REG_CP_ICP_SEL_8822C) \ + << BIT_SHIFT_REG_CP_ICP_SEL_8822C) +#define BITS_REG_CP_ICP_SEL_8822C \ + (BIT_MASK_REG_CP_ICP_SEL_8822C << BIT_SHIFT_REG_CP_ICP_SEL_8822C) +#define BIT_CLEAR_REG_CP_ICP_SEL_8822C(x) ((x) & (~BITS_REG_CP_ICP_SEL_8822C)) +#define BIT_GET_REG_CP_ICP_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_REG_CP_ICP_SEL_8822C) & \ + BIT_MASK_REG_CP_ICP_SEL_8822C) +#define BIT_SET_REG_CP_ICP_SEL_8822C(x, v) \ + (BIT_CLEAR_REG_CP_ICP_SEL_8822C(x) | BIT_REG_CP_ICP_SEL_8822C(v)) + +#define BIT_SHIFT_REG_IB_PI_8822C 4 +#define BIT_MASK_REG_IB_PI_8822C 0x3 +#define BIT_REG_IB_PI_8822C(x) \ + (((x) & BIT_MASK_REG_IB_PI_8822C) << BIT_SHIFT_REG_IB_PI_8822C) +#define BITS_REG_IB_PI_8822C \ + (BIT_MASK_REG_IB_PI_8822C << BIT_SHIFT_REG_IB_PI_8822C) +#define BIT_CLEAR_REG_IB_PI_8822C(x) ((x) & (~BITS_REG_IB_PI_8822C)) +#define BIT_GET_REG_IB_PI_8822C(x) \ + (((x) >> BIT_SHIFT_REG_IB_PI_8822C) & BIT_MASK_REG_IB_PI_8822C) +#define BIT_SET_REG_IB_PI_8822C(x, v) \ + (BIT_CLEAR_REG_IB_PI_8822C(x) | BIT_REG_IB_PI_8822C(v)) + +#define BIT_LDO2PWRCUT_8822C BIT(3) +#define BIT_VPULSE_LDO_8822C BIT(2) + +#define BIT_SHIFT_LDO_VSEL_8822C 0 +#define BIT_MASK_LDO_VSEL_8822C 0x3 +#define BIT_LDO_VSEL_8822C(x) \ + (((x) & BIT_MASK_LDO_VSEL_8822C) << BIT_SHIFT_LDO_VSEL_8822C) +#define BITS_LDO_VSEL_8822C \ + (BIT_MASK_LDO_VSEL_8822C << BIT_SHIFT_LDO_VSEL_8822C) +#define BIT_CLEAR_LDO_VSEL_8822C(x) ((x) & (~BITS_LDO_VSEL_8822C)) +#define BIT_GET_LDO_VSEL_8822C(x) \ + (((x) >> BIT_SHIFT_LDO_VSEL_8822C) & BIT_MASK_LDO_VSEL_8822C) +#define BIT_SET_LDO_VSEL_8822C(x, v) \ + (BIT_CLEAR_LDO_VSEL_8822C(x) | BIT_LDO_VSEL_8822C(v)) + +/* 2 REG_ANAPAR_MAC_1_8822C */ + +#define BIT_SHIFT_REG_CK_MON_SEL_8822C 29 +#define BIT_MASK_REG_CK_MON_SEL_8822C 0x7 +#define BIT_REG_CK_MON_SEL_8822C(x) \ + (((x) & BIT_MASK_REG_CK_MON_SEL_8822C) \ + << BIT_SHIFT_REG_CK_MON_SEL_8822C) +#define BITS_REG_CK_MON_SEL_8822C \ + (BIT_MASK_REG_CK_MON_SEL_8822C << BIT_SHIFT_REG_CK_MON_SEL_8822C) +#define BIT_CLEAR_REG_CK_MON_SEL_8822C(x) ((x) & (~BITS_REG_CK_MON_SEL_8822C)) +#define BIT_GET_REG_CK_MON_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_REG_CK_MON_SEL_8822C) & \ + BIT_MASK_REG_CK_MON_SEL_8822C) +#define BIT_SET_REG_CK_MON_SEL_8822C(x, v) \ + (BIT_CLEAR_REG_CK_MON_SEL_8822C(x) | BIT_REG_CK_MON_SEL_8822C(v)) + +#define BIT_REG_CK_MON_EN_8822C BIT(28) +#define BIT_REG_XTAL_FREQ_SEL_8822C BIT(27) +#define BIT_REG_XTAL_EDGE_SEL_8822C BIT(26) +#define BIT_REG_VCO_KVCO_8822C BIT(25) +#define BIT_REG_SDM_EDGE_SEL_8822C BIT(24) +#define BIT_REG_SDM_CK_SEL_8822C BIT(23) +#define BIT_REG_SDM_CK_GATED_8822C BIT(22) +#define BIT_REG_PFD_RESET_GATED_8822C BIT(21) + +#define BIT_SHIFT_REG_LPF_R3_FAST_8822C 16 +#define BIT_MASK_REG_LPF_R3_FAST_8822C 0x1f +#define BIT_REG_LPF_R3_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_R3_FAST_8822C) \ + << BIT_SHIFT_REG_LPF_R3_FAST_8822C) +#define BITS_REG_LPF_R3_FAST_8822C \ + (BIT_MASK_REG_LPF_R3_FAST_8822C << BIT_SHIFT_REG_LPF_R3_FAST_8822C) +#define BIT_CLEAR_REG_LPF_R3_FAST_8822C(x) ((x) & (~BITS_REG_LPF_R3_FAST_8822C)) +#define BIT_GET_REG_LPF_R3_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3_FAST_8822C) & \ + BIT_MASK_REG_LPF_R3_FAST_8822C) +#define BIT_SET_REG_LPF_R3_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_R3_FAST_8822C(x) | BIT_REG_LPF_R3_FAST_8822C(v)) + +#define BIT_SHIFT_REG_LPF_R2_FAST_8822C 11 +#define BIT_MASK_REG_LPF_R2_FAST_8822C 0x1f +#define BIT_REG_LPF_R2_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_R2_FAST_8822C) \ + << BIT_SHIFT_REG_LPF_R2_FAST_8822C) +#define BITS_REG_LPF_R2_FAST_8822C \ + (BIT_MASK_REG_LPF_R2_FAST_8822C << BIT_SHIFT_REG_LPF_R2_FAST_8822C) +#define BIT_CLEAR_REG_LPF_R2_FAST_8822C(x) ((x) & (~BITS_REG_LPF_R2_FAST_8822C)) +#define BIT_GET_REG_LPF_R2_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R2_FAST_8822C) & \ + BIT_MASK_REG_LPF_R2_FAST_8822C) +#define BIT_SET_REG_LPF_R2_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_R2_FAST_8822C(x) | BIT_REG_LPF_R2_FAST_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C3_FAST_8822C 8 +#define BIT_MASK_REG_LPF_C3_FAST_8822C 0x7 +#define BIT_REG_LPF_C3_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C3_FAST_8822C) \ + << BIT_SHIFT_REG_LPF_C3_FAST_8822C) +#define BITS_REG_LPF_C3_FAST_8822C \ + (BIT_MASK_REG_LPF_C3_FAST_8822C << BIT_SHIFT_REG_LPF_C3_FAST_8822C) +#define BIT_CLEAR_REG_LPF_C3_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C3_FAST_8822C)) +#define BIT_GET_REG_LPF_C3_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C3_FAST_8822C) & \ + BIT_MASK_REG_LPF_C3_FAST_8822C) +#define BIT_SET_REG_LPF_C3_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C3_FAST_8822C(x) | BIT_REG_LPF_C3_FAST_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C2_FAST_8822C 5 +#define BIT_MASK_REG_LPF_C2_FAST_8822C 0x7 +#define BIT_REG_LPF_C2_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C2_FAST_8822C) \ + << BIT_SHIFT_REG_LPF_C2_FAST_8822C) +#define BITS_REG_LPF_C2_FAST_8822C \ + (BIT_MASK_REG_LPF_C2_FAST_8822C << BIT_SHIFT_REG_LPF_C2_FAST_8822C) +#define BIT_CLEAR_REG_LPF_C2_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C2_FAST_8822C)) +#define BIT_GET_REG_LPF_C2_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C2_FAST_8822C) & \ + BIT_MASK_REG_LPF_C2_FAST_8822C) +#define BIT_SET_REG_LPF_C2_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C2_FAST_8822C(x) | BIT_REG_LPF_C2_FAST_8822C(v)) + +#define BIT_SHIFT_REG_LPF_C1_FAST_8822C 2 +#define BIT_MASK_REG_LPF_C1_FAST_8822C 0x7 +#define BIT_REG_LPF_C1_FAST_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_C1_FAST_8822C) \ + << BIT_SHIFT_REG_LPF_C1_FAST_8822C) +#define BITS_REG_LPF_C1_FAST_8822C \ + (BIT_MASK_REG_LPF_C1_FAST_8822C << BIT_SHIFT_REG_LPF_C1_FAST_8822C) +#define BIT_CLEAR_REG_LPF_C1_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C1_FAST_8822C)) +#define BIT_GET_REG_LPF_C1_FAST_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_C1_FAST_8822C) & \ + BIT_MASK_REG_LPF_C1_FAST_8822C) +#define BIT_SET_REG_LPF_C1_FAST_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_C1_FAST_8822C(x) | BIT_REG_LPF_C1_FAST_8822C(v)) + +#define BIT_SHIFT_REG_LPF_R3_V1_8822C 0 +#define BIT_MASK_REG_LPF_R3_V1_8822C 0x3 +#define BIT_REG_LPF_R3_V1_8822C(x) \ + (((x) & BIT_MASK_REG_LPF_R3_V1_8822C) << BIT_SHIFT_REG_LPF_R3_V1_8822C) +#define BITS_REG_LPF_R3_V1_8822C \ + (BIT_MASK_REG_LPF_R3_V1_8822C << BIT_SHIFT_REG_LPF_R3_V1_8822C) +#define BIT_CLEAR_REG_LPF_R3_V1_8822C(x) ((x) & (~BITS_REG_LPF_R3_V1_8822C)) +#define BIT_GET_REG_LPF_R3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_REG_LPF_R3_V1_8822C) & BIT_MASK_REG_LPF_R3_V1_8822C) +#define BIT_SET_REG_LPF_R3_V1_8822C(x, v) \ + (BIT_CLEAR_REG_LPF_R3_V1_8822C(x) | BIT_REG_LPF_R3_V1_8822C(v)) + +/* 2 REG_ANAPAR_MAC_2_8822C */ + +#define BIT_SHIFT_AGPIO_DRV_V1_8822C 30 +#define BIT_MASK_AGPIO_DRV_V1_8822C 0x3 +#define BIT_AGPIO_DRV_V1_8822C(x) \ + (((x) & BIT_MASK_AGPIO_DRV_V1_8822C) << BIT_SHIFT_AGPIO_DRV_V1_8822C) +#define BITS_AGPIO_DRV_V1_8822C \ + (BIT_MASK_AGPIO_DRV_V1_8822C << BIT_SHIFT_AGPIO_DRV_V1_8822C) +#define BIT_CLEAR_AGPIO_DRV_V1_8822C(x) ((x) & (~BITS_AGPIO_DRV_V1_8822C)) +#define BIT_GET_AGPIO_DRV_V1_8822C(x) \ + (((x) >> BIT_SHIFT_AGPIO_DRV_V1_8822C) & BIT_MASK_AGPIO_DRV_V1_8822C) +#define BIT_SET_AGPIO_DRV_V1_8822C(x, v) \ + (BIT_CLEAR_AGPIO_DRV_V1_8822C(x) | BIT_AGPIO_DRV_V1_8822C(v)) + +#define BIT_AGPIO_GPO_V1_8822C BIT(29) +#define BIT_AGPIO_GPE_V1_8822C BIT(28) +#define BIT_SEL_CLK_8822C BIT(27) + +#define BIT_SHIFT_LS_XTAL_SEL_8822C 23 +#define BIT_MASK_LS_XTAL_SEL_8822C 0xf +#define BIT_LS_XTAL_SEL_8822C(x) \ + (((x) & BIT_MASK_LS_XTAL_SEL_8822C) << BIT_SHIFT_LS_XTAL_SEL_8822C) +#define BITS_LS_XTAL_SEL_8822C \ + (BIT_MASK_LS_XTAL_SEL_8822C << BIT_SHIFT_LS_XTAL_SEL_8822C) +#define BIT_CLEAR_LS_XTAL_SEL_8822C(x) ((x) & (~BITS_LS_XTAL_SEL_8822C)) +#define BIT_GET_LS_XTAL_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_LS_XTAL_SEL_8822C) & BIT_MASK_LS_XTAL_SEL_8822C) +#define BIT_SET_LS_XTAL_SEL_8822C(x, v) \ + (BIT_CLEAR_LS_XTAL_SEL_8822C(x) | BIT_LS_XTAL_SEL_8822C(v)) + +#define BIT_LS_SDM_ORDER_V1_8822C BIT(22) +#define BIT_LS_DELAY_PH_8822C BIT(21) +#define BIT_DIVIDER_SEL_8822C BIT(20) + +#define BIT_SHIFT_PCODE_8822C 15 +#define BIT_MASK_PCODE_8822C 0x1f +#define BIT_PCODE_8822C(x) \ + (((x) & BIT_MASK_PCODE_8822C) << BIT_SHIFT_PCODE_8822C) +#define BITS_PCODE_8822C (BIT_MASK_PCODE_8822C << BIT_SHIFT_PCODE_8822C) +#define BIT_CLEAR_PCODE_8822C(x) ((x) & (~BITS_PCODE_8822C)) +#define BIT_GET_PCODE_8822C(x) \ + (((x) >> BIT_SHIFT_PCODE_8822C) & BIT_MASK_PCODE_8822C) +#define BIT_SET_PCODE_8822C(x, v) \ + (BIT_CLEAR_PCODE_8822C(x) | BIT_PCODE_8822C(v)) + +#define BIT_SHIFT_NCODE_8822C 7 +#define BIT_MASK_NCODE_8822C 0xff +#define BIT_NCODE_8822C(x) \ + (((x) & BIT_MASK_NCODE_8822C) << BIT_SHIFT_NCODE_8822C) +#define BITS_NCODE_8822C (BIT_MASK_NCODE_8822C << BIT_SHIFT_NCODE_8822C) +#define BIT_CLEAR_NCODE_8822C(x) ((x) & (~BITS_NCODE_8822C)) +#define BIT_GET_NCODE_8822C(x) \ + (((x) >> BIT_SHIFT_NCODE_8822C) & BIT_MASK_NCODE_8822C) +#define BIT_SET_NCODE_8822C(x, v) \ + (BIT_CLEAR_NCODE_8822C(x) | BIT_NCODE_8822C(v)) + +#define BIT_REG_BEACON_8822C BIT(6) +#define BIT_REG_MBIASE_8822C BIT(5) + +#define BIT_SHIFT_REG_FAST_SEL_8822C 3 +#define BIT_MASK_REG_FAST_SEL_8822C 0x3 +#define BIT_REG_FAST_SEL_8822C(x) \ + (((x) & BIT_MASK_REG_FAST_SEL_8822C) << BIT_SHIFT_REG_FAST_SEL_8822C) +#define BITS_REG_FAST_SEL_8822C \ + (BIT_MASK_REG_FAST_SEL_8822C << BIT_SHIFT_REG_FAST_SEL_8822C) +#define BIT_CLEAR_REG_FAST_SEL_8822C(x) ((x) & (~BITS_REG_FAST_SEL_8822C)) +#define BIT_GET_REG_FAST_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_REG_FAST_SEL_8822C) & BIT_MASK_REG_FAST_SEL_8822C) +#define BIT_SET_REG_FAST_SEL_8822C(x, v) \ + (BIT_CLEAR_REG_FAST_SEL_8822C(x) | BIT_REG_FAST_SEL_8822C(v)) + +#define BIT_REG_CK960M_EN_8822C BIT(2) +#define BIT_REG_CK320M_EN_8822C BIT(1) +#define BIT_REG_CK_5M_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ANAPAR_XTAL_0_8822C */ +#define BIT_XTAL_SC_LPS_8822C BIT(31) + +#define BIT_SHIFT_XTAL_SC_INIT_8822C 24 +#define BIT_MASK_XTAL_SC_INIT_8822C 0x7f +#define BIT_XTAL_SC_INIT_8822C(x) \ + (((x) & BIT_MASK_XTAL_SC_INIT_8822C) << BIT_SHIFT_XTAL_SC_INIT_8822C) +#define BITS_XTAL_SC_INIT_8822C \ + (BIT_MASK_XTAL_SC_INIT_8822C << BIT_SHIFT_XTAL_SC_INIT_8822C) +#define BIT_CLEAR_XTAL_SC_INIT_8822C(x) ((x) & (~BITS_XTAL_SC_INIT_8822C)) +#define BIT_GET_XTAL_SC_INIT_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_INIT_8822C) & BIT_MASK_XTAL_SC_INIT_8822C) +#define BIT_SET_XTAL_SC_INIT_8822C(x, v) \ + (BIT_CLEAR_XTAL_SC_INIT_8822C(x) | BIT_XTAL_SC_INIT_8822C(v)) + +#define BIT_SHIFT_XTAL_SC_XO_8822C 17 +#define BIT_MASK_XTAL_SC_XO_8822C 0x7f +#define BIT_XTAL_SC_XO_8822C(x) \ + (((x) & BIT_MASK_XTAL_SC_XO_8822C) << BIT_SHIFT_XTAL_SC_XO_8822C) +#define BITS_XTAL_SC_XO_8822C \ + (BIT_MASK_XTAL_SC_XO_8822C << BIT_SHIFT_XTAL_SC_XO_8822C) +#define BIT_CLEAR_XTAL_SC_XO_8822C(x) ((x) & (~BITS_XTAL_SC_XO_8822C)) +#define BIT_GET_XTAL_SC_XO_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XO_8822C) & BIT_MASK_XTAL_SC_XO_8822C) +#define BIT_SET_XTAL_SC_XO_8822C(x, v) \ + (BIT_CLEAR_XTAL_SC_XO_8822C(x) | BIT_XTAL_SC_XO_8822C(v)) + +#define BIT_SHIFT_XTAL_SC_XI_8822C 10 +#define BIT_MASK_XTAL_SC_XI_8822C 0x7f +#define BIT_XTAL_SC_XI_8822C(x) \ + (((x) & BIT_MASK_XTAL_SC_XI_8822C) << BIT_SHIFT_XTAL_SC_XI_8822C) +#define BITS_XTAL_SC_XI_8822C \ + (BIT_MASK_XTAL_SC_XI_8822C << BIT_SHIFT_XTAL_SC_XI_8822C) +#define BIT_CLEAR_XTAL_SC_XI_8822C(x) ((x) & (~BITS_XTAL_SC_XI_8822C)) +#define BIT_GET_XTAL_SC_XI_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_XI_8822C) & BIT_MASK_XTAL_SC_XI_8822C) +#define BIT_SET_XTAL_SC_XI_8822C(x, v) \ + (BIT_CLEAR_XTAL_SC_XI_8822C(x) | BIT_XTAL_SC_XI_8822C(v)) + +#define BIT_SHIFT_XTAL_GMN_V3_8822C 5 +#define BIT_MASK_XTAL_GMN_V3_8822C 0x1f +#define BIT_XTAL_GMN_V3_8822C(x) \ + (((x) & BIT_MASK_XTAL_GMN_V3_8822C) << BIT_SHIFT_XTAL_GMN_V3_8822C) +#define BITS_XTAL_GMN_V3_8822C \ + (BIT_MASK_XTAL_GMN_V3_8822C << BIT_SHIFT_XTAL_GMN_V3_8822C) +#define BIT_CLEAR_XTAL_GMN_V3_8822C(x) ((x) & (~BITS_XTAL_GMN_V3_8822C)) +#define BIT_GET_XTAL_GMN_V3_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_GMN_V3_8822C) & BIT_MASK_XTAL_GMN_V3_8822C) +#define BIT_SET_XTAL_GMN_V3_8822C(x, v) \ + (BIT_CLEAR_XTAL_GMN_V3_8822C(x) | BIT_XTAL_GMN_V3_8822C(v)) + +#define BIT_SHIFT_XTAL_GMP_V3_8822C 0 +#define BIT_MASK_XTAL_GMP_V3_8822C 0x1f +#define BIT_XTAL_GMP_V3_8822C(x) \ + (((x) & BIT_MASK_XTAL_GMP_V3_8822C) << BIT_SHIFT_XTAL_GMP_V3_8822C) +#define BITS_XTAL_GMP_V3_8822C \ + (BIT_MASK_XTAL_GMP_V3_8822C << BIT_SHIFT_XTAL_GMP_V3_8822C) +#define BIT_CLEAR_XTAL_GMP_V3_8822C(x) ((x) & (~BITS_XTAL_GMP_V3_8822C)) +#define BIT_GET_XTAL_GMP_V3_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_GMP_V3_8822C) & BIT_MASK_XTAL_GMP_V3_8822C) +#define BIT_SET_XTAL_GMP_V3_8822C(x, v) \ + (BIT_CLEAR_XTAL_GMP_V3_8822C(x) | BIT_XTAL_GMP_V3_8822C(v)) + +/* 2 REG_ANAPAR_XTAL_1_8822C */ +#define BIT_XTAL_SEL_TOK_V1_8822C BIT(31) +#define BIT_XTAL_DELAY_DIGI_V2_8822C BIT(30) +#define BIT_XTAL_DELAY_USB_V2_8822C BIT(29) +#define BIT_XTAL_DELAY_AFE_V2_8822C BIT(28) + +#define BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C 26 +#define BIT_MASK_XTAL_DRV_DIGI_V2_8822C 0x3 +#define BIT_XTAL_DRV_DIGI_V2_8822C(x) \ + (((x) & BIT_MASK_XTAL_DRV_DIGI_V2_8822C) \ + << BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C) +#define BITS_XTAL_DRV_DIGI_V2_8822C \ + (BIT_MASK_XTAL_DRV_DIGI_V2_8822C << BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C) +#define BIT_CLEAR_XTAL_DRV_DIGI_V2_8822C(x) \ + ((x) & (~BITS_XTAL_DRV_DIGI_V2_8822C)) +#define BIT_GET_XTAL_DRV_DIGI_V2_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C) & \ + BIT_MASK_XTAL_DRV_DIGI_V2_8822C) +#define BIT_SET_XTAL_DRV_DIGI_V2_8822C(x, v) \ + (BIT_CLEAR_XTAL_DRV_DIGI_V2_8822C(x) | BIT_XTAL_DRV_DIGI_V2_8822C(v)) + +#define BIT_EN_XTAL_DRV_LPS_8822C BIT(25) +#define BIT_EN_XTAL_DRV_DIGI_V2_8822C BIT(24) + +#define BIT_SHIFT_XTAL_DRV_USB_8822C 22 +#define BIT_MASK_XTAL_DRV_USB_8822C 0x3 +#define BIT_XTAL_DRV_USB_8822C(x) \ + (((x) & BIT_MASK_XTAL_DRV_USB_8822C) << BIT_SHIFT_XTAL_DRV_USB_8822C) +#define BITS_XTAL_DRV_USB_8822C \ + (BIT_MASK_XTAL_DRV_USB_8822C << BIT_SHIFT_XTAL_DRV_USB_8822C) +#define BIT_CLEAR_XTAL_DRV_USB_8822C(x) ((x) & (~BITS_XTAL_DRV_USB_8822C)) +#define BIT_GET_XTAL_DRV_USB_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_USB_8822C) & BIT_MASK_XTAL_DRV_USB_8822C) +#define BIT_SET_XTAL_DRV_USB_8822C(x, v) \ + (BIT_CLEAR_XTAL_DRV_USB_8822C(x) | BIT_XTAL_DRV_USB_8822C(v)) + +#define BIT_EN_XTAL_DRV_USB_8822C BIT(21) + +#define BIT_SHIFT_XTAL_DRV_AFE_V2_8822C 19 +#define BIT_MASK_XTAL_DRV_AFE_V2_8822C 0x3 +#define BIT_XTAL_DRV_AFE_V2_8822C(x) \ + (((x) & BIT_MASK_XTAL_DRV_AFE_V2_8822C) \ + << BIT_SHIFT_XTAL_DRV_AFE_V2_8822C) +#define BITS_XTAL_DRV_AFE_V2_8822C \ + (BIT_MASK_XTAL_DRV_AFE_V2_8822C << BIT_SHIFT_XTAL_DRV_AFE_V2_8822C) +#define BIT_CLEAR_XTAL_DRV_AFE_V2_8822C(x) ((x) & (~BITS_XTAL_DRV_AFE_V2_8822C)) +#define BIT_GET_XTAL_DRV_AFE_V2_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_AFE_V2_8822C) & \ + BIT_MASK_XTAL_DRV_AFE_V2_8822C) +#define BIT_SET_XTAL_DRV_AFE_V2_8822C(x, v) \ + (BIT_CLEAR_XTAL_DRV_AFE_V2_8822C(x) | BIT_XTAL_DRV_AFE_V2_8822C(v)) + +#define BIT_EN_XTAL_DRV_AFE_8822C BIT(18) + +#define BIT_SHIFT_XTAL_DRV_RF2_V2_8822C 16 +#define BIT_MASK_XTAL_DRV_RF2_V2_8822C 0x3 +#define BIT_XTAL_DRV_RF2_V2_8822C(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF2_V2_8822C) \ + << BIT_SHIFT_XTAL_DRV_RF2_V2_8822C) +#define BITS_XTAL_DRV_RF2_V2_8822C \ + (BIT_MASK_XTAL_DRV_RF2_V2_8822C << BIT_SHIFT_XTAL_DRV_RF2_V2_8822C) +#define BIT_CLEAR_XTAL_DRV_RF2_V2_8822C(x) ((x) & (~BITS_XTAL_DRV_RF2_V2_8822C)) +#define BIT_GET_XTAL_DRV_RF2_V2_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF2_V2_8822C) & \ + BIT_MASK_XTAL_DRV_RF2_V2_8822C) +#define BIT_SET_XTAL_DRV_RF2_V2_8822C(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF2_V2_8822C(x) | BIT_XTAL_DRV_RF2_V2_8822C(v)) + +#define BIT_EN_XTAL_DRV_RF2_8822C BIT(15) + +#define BIT_SHIFT_XTAL_DRV_RF1_8822C 13 +#define BIT_MASK_XTAL_DRV_RF1_8822C 0x3 +#define BIT_XTAL_DRV_RF1_8822C(x) \ + (((x) & BIT_MASK_XTAL_DRV_RF1_8822C) << BIT_SHIFT_XTAL_DRV_RF1_8822C) +#define BITS_XTAL_DRV_RF1_8822C \ + (BIT_MASK_XTAL_DRV_RF1_8822C << BIT_SHIFT_XTAL_DRV_RF1_8822C) +#define BIT_CLEAR_XTAL_DRV_RF1_8822C(x) ((x) & (~BITS_XTAL_DRV_RF1_8822C)) +#define BIT_GET_XTAL_DRV_RF1_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822C) & BIT_MASK_XTAL_DRV_RF1_8822C) +#define BIT_SET_XTAL_DRV_RF1_8822C(x, v) \ + (BIT_CLEAR_XTAL_DRV_RF1_8822C(x) | BIT_XTAL_DRV_RF1_8822C(v)) + +#define BIT_EN_XTAL_DRV_RF1_8822C BIT(12) +#define BIT_XTAL_DRV_RF_LATCH_V4_8822C BIT(11) +#define BIT_XTAL_GM_SEP_V3_8822C BIT(10) +#define BIT_XQSEL_RF_AWAKE_V3_8822C BIT(9) +#define BIT_XQSEL_RF_INITIAL_V3_8822C BIT(8) +#define BIT_XQSEL_V2_8822C BIT(7) +#define BIT_GATED_XTAL_OK0_V2_8822C BIT(6) + +#define BIT_SHIFT_XTAL_SC_LPS_V2_8822C 0 +#define BIT_MASK_XTAL_SC_LPS_V2_8822C 0x3f +#define BIT_XTAL_SC_LPS_V2_8822C(x) \ + (((x) & BIT_MASK_XTAL_SC_LPS_V2_8822C) \ + << BIT_SHIFT_XTAL_SC_LPS_V2_8822C) +#define BITS_XTAL_SC_LPS_V2_8822C \ + (BIT_MASK_XTAL_SC_LPS_V2_8822C << BIT_SHIFT_XTAL_SC_LPS_V2_8822C) +#define BIT_CLEAR_XTAL_SC_LPS_V2_8822C(x) ((x) & (~BITS_XTAL_SC_LPS_V2_8822C)) +#define BIT_GET_XTAL_SC_LPS_V2_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_SC_LPS_V2_8822C) & \ + BIT_MASK_XTAL_SC_LPS_V2_8822C) +#define BIT_SET_XTAL_SC_LPS_V2_8822C(x, v) \ + (BIT_CLEAR_XTAL_SC_LPS_V2_8822C(x) | BIT_XTAL_SC_LPS_V2_8822C(v)) + +/* 2 REG_ANAPAR_XTAL_2_8822C */ +#define BIT_XTAL_AAC_CAP_8822C BIT(31) + +#define BIT_SHIFT_XTAL_PDSW_8822C 29 +#define BIT_MASK_XTAL_PDSW_8822C 0x3 +#define BIT_XTAL_PDSW_8822C(x) \ + (((x) & BIT_MASK_XTAL_PDSW_8822C) << BIT_SHIFT_XTAL_PDSW_8822C) +#define BITS_XTAL_PDSW_8822C \ + (BIT_MASK_XTAL_PDSW_8822C << BIT_SHIFT_XTAL_PDSW_8822C) +#define BIT_CLEAR_XTAL_PDSW_8822C(x) ((x) & (~BITS_XTAL_PDSW_8822C)) +#define BIT_GET_XTAL_PDSW_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_PDSW_8822C) & BIT_MASK_XTAL_PDSW_8822C) +#define BIT_SET_XTAL_PDSW_8822C(x, v) \ + (BIT_CLEAR_XTAL_PDSW_8822C(x) | BIT_XTAL_PDSW_8822C(v)) + +#define BIT_SHIFT_XTAL_LPS_BUF_VB_8822C 27 +#define BIT_MASK_XTAL_LPS_BUF_VB_8822C 0x3 +#define BIT_XTAL_LPS_BUF_VB_8822C(x) \ + (((x) & BIT_MASK_XTAL_LPS_BUF_VB_8822C) \ + << BIT_SHIFT_XTAL_LPS_BUF_VB_8822C) +#define BITS_XTAL_LPS_BUF_VB_8822C \ + (BIT_MASK_XTAL_LPS_BUF_VB_8822C << BIT_SHIFT_XTAL_LPS_BUF_VB_8822C) +#define BIT_CLEAR_XTAL_LPS_BUF_VB_8822C(x) ((x) & (~BITS_XTAL_LPS_BUF_VB_8822C)) +#define BIT_GET_XTAL_LPS_BUF_VB_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB_8822C) & \ + BIT_MASK_XTAL_LPS_BUF_VB_8822C) +#define BIT_SET_XTAL_LPS_BUF_VB_8822C(x, v) \ + (BIT_CLEAR_XTAL_LPS_BUF_VB_8822C(x) | BIT_XTAL_LPS_BUF_VB_8822C(v)) + +#define BIT_XTAL_PDCK_MANU_8822C BIT(26) +#define BIT_XTAL_PDCK_OK_MANU_8822C BIT(25) + +#define BIT_SHIFT_XTAL_VREF_SEL_8822C 20 +#define BIT_MASK_XTAL_VREF_SEL_8822C 0x1f +#define BIT_XTAL_VREF_SEL_8822C(x) \ + (((x) & BIT_MASK_XTAL_VREF_SEL_8822C) << BIT_SHIFT_XTAL_VREF_SEL_8822C) +#define BITS_XTAL_VREF_SEL_8822C \ + (BIT_MASK_XTAL_VREF_SEL_8822C << BIT_SHIFT_XTAL_VREF_SEL_8822C) +#define BIT_CLEAR_XTAL_VREF_SEL_8822C(x) ((x) & (~BITS_XTAL_VREF_SEL_8822C)) +#define BIT_GET_XTAL_VREF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_VREF_SEL_8822C) & BIT_MASK_XTAL_VREF_SEL_8822C) +#define BIT_SET_XTAL_VREF_SEL_8822C(x, v) \ + (BIT_CLEAR_XTAL_VREF_SEL_8822C(x) | BIT_XTAL_VREF_SEL_8822C(v)) + +#define BIT_EN_XTAL_PDCK_VREF_8822C BIT(19) +#define BIT_XTAL_SEL_PWR_V1_8822C BIT(18) +#define BIT_XTAL_LPS_DIVISOR_8822C BIT(17) +#define BIT_XTAL_CKDIGI_SEL_8822C BIT(16) +#define BIT_EN_XTAL_LPS_CLK_8822C BIT(15) +#define BIT_EN_XTAL_SCHMITT_8822C BIT(14) +#define BIT_XTAL_PK_SEL_OFFSET_8822C BIT(13) + +#define BIT_SHIFT_XTAL_MANU_PK_SEL_8822C 11 +#define BIT_MASK_XTAL_MANU_PK_SEL_8822C 0x3 +#define BIT_XTAL_MANU_PK_SEL_8822C(x) \ + (((x) & BIT_MASK_XTAL_MANU_PK_SEL_8822C) \ + << BIT_SHIFT_XTAL_MANU_PK_SEL_8822C) +#define BITS_XTAL_MANU_PK_SEL_8822C \ + (BIT_MASK_XTAL_MANU_PK_SEL_8822C << BIT_SHIFT_XTAL_MANU_PK_SEL_8822C) +#define BIT_CLEAR_XTAL_MANU_PK_SEL_8822C(x) \ + ((x) & (~BITS_XTAL_MANU_PK_SEL_8822C)) +#define BIT_GET_XTAL_MANU_PK_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL_8822C) & \ + BIT_MASK_XTAL_MANU_PK_SEL_8822C) +#define BIT_SET_XTAL_MANU_PK_SEL_8822C(x, v) \ + (BIT_CLEAR_XTAL_MANU_PK_SEL_8822C(x) | BIT_XTAL_MANU_PK_SEL_8822C(v)) + +#define BIT_XTAL_AACK_PK_MANU_8822C BIT(10) +#define BIT_EN_XTAL_AAC_PKDET_V1_8822C BIT(9) +#define BIT_EN_XTAL_AAC_GM_V1_8822C BIT(8) +#define BIT_XTAL_LDO_OPVB_SEL_8822C BIT(7) +#define BIT_XTAL_LDO_NC_8822C BIT(6) + +#define BIT_SHIFT_XTAL_LDO_VREF_V2_8822C 3 +#define BIT_MASK_XTAL_LDO_VREF_V2_8822C 0x7 +#define BIT_XTAL_LDO_VREF_V2_8822C(x) \ + (((x) & BIT_MASK_XTAL_LDO_VREF_V2_8822C) \ + << BIT_SHIFT_XTAL_LDO_VREF_V2_8822C) +#define BITS_XTAL_LDO_VREF_V2_8822C \ + (BIT_MASK_XTAL_LDO_VREF_V2_8822C << BIT_SHIFT_XTAL_LDO_VREF_V2_8822C) +#define BIT_CLEAR_XTAL_LDO_VREF_V2_8822C(x) \ + ((x) & (~BITS_XTAL_LDO_VREF_V2_8822C)) +#define BIT_GET_XTAL_LDO_VREF_V2_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_VREF_V2_8822C) & \ + BIT_MASK_XTAL_LDO_VREF_V2_8822C) +#define BIT_SET_XTAL_LDO_VREF_V2_8822C(x, v) \ + (BIT_CLEAR_XTAL_LDO_VREF_V2_8822C(x) | BIT_XTAL_LDO_VREF_V2_8822C(v)) + +#define BIT_XTAL_LPMODE_V1_8822C BIT(2) + +#define BIT_SHIFT_XTAL_SEL_TOK_V3_8822C 0 +#define BIT_MASK_XTAL_SEL_TOK_V3_8822C 0x3 +#define BIT_XTAL_SEL_TOK_V3_8822C(x) \ + (((x) & BIT_MASK_XTAL_SEL_TOK_V3_8822C) \ + << BIT_SHIFT_XTAL_SEL_TOK_V3_8822C) +#define BITS_XTAL_SEL_TOK_V3_8822C \ + (BIT_MASK_XTAL_SEL_TOK_V3_8822C << BIT_SHIFT_XTAL_SEL_TOK_V3_8822C) +#define BIT_CLEAR_XTAL_SEL_TOK_V3_8822C(x) ((x) & (~BITS_XTAL_SEL_TOK_V3_8822C)) +#define BIT_GET_XTAL_SEL_TOK_V3_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V3_8822C) & \ + BIT_MASK_XTAL_SEL_TOK_V3_8822C) +#define BIT_SET_XTAL_SEL_TOK_V3_8822C(x, v) \ + (BIT_CLEAR_XTAL_SEL_TOK_V3_8822C(x) | BIT_XTAL_SEL_TOK_V3_8822C(v)) + +/* 2 REG_ANAPAR_XTAL_3_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_XTAL_DUMMY_V1_8822C 7 +#define BIT_MASK_XTAL_DUMMY_V1_8822C 0x3f +#define BIT_XTAL_DUMMY_V1_8822C(x) \ + (((x) & BIT_MASK_XTAL_DUMMY_V1_8822C) << BIT_SHIFT_XTAL_DUMMY_V1_8822C) +#define BITS_XTAL_DUMMY_V1_8822C \ + (BIT_MASK_XTAL_DUMMY_V1_8822C << BIT_SHIFT_XTAL_DUMMY_V1_8822C) +#define BIT_CLEAR_XTAL_DUMMY_V1_8822C(x) ((x) & (~BITS_XTAL_DUMMY_V1_8822C)) +#define BIT_GET_XTAL_DUMMY_V1_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_DUMMY_V1_8822C) & BIT_MASK_XTAL_DUMMY_V1_8822C) +#define BIT_SET_XTAL_DUMMY_V1_8822C(x, v) \ + (BIT_CLEAR_XTAL_DUMMY_V1_8822C(x) | BIT_XTAL_DUMMY_V1_8822C(v)) + +#define BIT_XTAL_EN_LNBUF_8822C BIT(6) +#define BIT_XTAL__AAC_TIE_MID_8822C BIT(5) + +#define BIT_SHIFT_XTAL_AAC_OPCUR_8822C 3 +#define BIT_MASK_XTAL_AAC_OPCUR_8822C 0x3 +#define BIT_XTAL_AAC_OPCUR_8822C(x) \ + (((x) & BIT_MASK_XTAL_AAC_OPCUR_8822C) \ + << BIT_SHIFT_XTAL_AAC_OPCUR_8822C) +#define BITS_XTAL_AAC_OPCUR_8822C \ + (BIT_MASK_XTAL_AAC_OPCUR_8822C << BIT_SHIFT_XTAL_AAC_OPCUR_8822C) +#define BIT_CLEAR_XTAL_AAC_OPCUR_8822C(x) ((x) & (~BITS_XTAL_AAC_OPCUR_8822C)) +#define BIT_GET_XTAL_AAC_OPCUR_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_OPCUR_8822C) & \ + BIT_MASK_XTAL_AAC_OPCUR_8822C) +#define BIT_SET_XTAL_AAC_OPCUR_8822C(x, v) \ + (BIT_CLEAR_XTAL_AAC_OPCUR_8822C(x) | BIT_XTAL_AAC_OPCUR_8822C(v)) + +#define BIT_SHIFT_XTAL_AAC_IOFFSET_8822C 1 +#define BIT_MASK_XTAL_AAC_IOFFSET_8822C 0x3 +#define BIT_XTAL_AAC_IOFFSET_8822C(x) \ + (((x) & BIT_MASK_XTAL_AAC_IOFFSET_8822C) \ + << BIT_SHIFT_XTAL_AAC_IOFFSET_8822C) +#define BITS_XTAL_AAC_IOFFSET_8822C \ + (BIT_MASK_XTAL_AAC_IOFFSET_8822C << BIT_SHIFT_XTAL_AAC_IOFFSET_8822C) +#define BIT_CLEAR_XTAL_AAC_IOFFSET_8822C(x) \ + ((x) & (~BITS_XTAL_AAC_IOFFSET_8822C)) +#define BIT_GET_XTAL_AAC_IOFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET_8822C) & \ + BIT_MASK_XTAL_AAC_IOFFSET_8822C) +#define BIT_SET_XTAL_AAC_IOFFSET_8822C(x, v) \ + (BIT_CLEAR_XTAL_AAC_IOFFSET_8822C(x) | BIT_XTAL_AAC_IOFFSET_8822C(v)) + +#define BIT_XTAL_AAC_CAP_V1_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ANAPAR_XTAL_AACK_0_8822C */ +#define BIT_XAAC_LPOW_8822C BIT(31) + +#define BIT_SHIFT_AAC_MODE_8822C 29 +#define BIT_MASK_AAC_MODE_8822C 0x3 +#define BIT_AAC_MODE_8822C(x) \ + (((x) & BIT_MASK_AAC_MODE_8822C) << BIT_SHIFT_AAC_MODE_8822C) +#define BITS_AAC_MODE_8822C \ + (BIT_MASK_AAC_MODE_8822C << BIT_SHIFT_AAC_MODE_8822C) +#define BIT_CLEAR_AAC_MODE_8822C(x) ((x) & (~BITS_AAC_MODE_8822C)) +#define BIT_GET_AAC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_AAC_MODE_8822C) & BIT_MASK_AAC_MODE_8822C) +#define BIT_SET_AAC_MODE_8822C(x, v) \ + (BIT_CLEAR_AAC_MODE_8822C(x) | BIT_AAC_MODE_8822C(v)) + +#define BIT_EN_XTAL_AAC_TRIG_8822C BIT(28) +#define BIT_EN_XTAL_AAC_8822C BIT(27) +#define BIT_EN_XTAL_AAC_DIGI_8822C BIT(26) + +#define BIT_SHIFT_GM_MANUAL_8822C 21 +#define BIT_MASK_GM_MANUAL_8822C 0x1f +#define BIT_GM_MANUAL_8822C(x) \ + (((x) & BIT_MASK_GM_MANUAL_8822C) << BIT_SHIFT_GM_MANUAL_8822C) +#define BITS_GM_MANUAL_8822C \ + (BIT_MASK_GM_MANUAL_8822C << BIT_SHIFT_GM_MANUAL_8822C) +#define BIT_CLEAR_GM_MANUAL_8822C(x) ((x) & (~BITS_GM_MANUAL_8822C)) +#define BIT_GET_GM_MANUAL_8822C(x) \ + (((x) >> BIT_SHIFT_GM_MANUAL_8822C) & BIT_MASK_GM_MANUAL_8822C) +#define BIT_SET_GM_MANUAL_8822C(x, v) \ + (BIT_CLEAR_GM_MANUAL_8822C(x) | BIT_GM_MANUAL_8822C(v)) + +#define BIT_SHIFT_GM_STUP_8822C 16 +#define BIT_MASK_GM_STUP_8822C 0x1f +#define BIT_GM_STUP_8822C(x) \ + (((x) & BIT_MASK_GM_STUP_8822C) << BIT_SHIFT_GM_STUP_8822C) +#define BITS_GM_STUP_8822C (BIT_MASK_GM_STUP_8822C << BIT_SHIFT_GM_STUP_8822C) +#define BIT_CLEAR_GM_STUP_8822C(x) ((x) & (~BITS_GM_STUP_8822C)) +#define BIT_GET_GM_STUP_8822C(x) \ + (((x) >> BIT_SHIFT_GM_STUP_8822C) & BIT_MASK_GM_STUP_8822C) +#define BIT_SET_GM_STUP_8822C(x, v) \ + (BIT_CLEAR_GM_STUP_8822C(x) | BIT_GM_STUP_8822C(v)) + +#define BIT_SHIFT_XTAL_CK_SET_8822C 13 +#define BIT_MASK_XTAL_CK_SET_8822C 0x7 +#define BIT_XTAL_CK_SET_8822C(x) \ + (((x) & BIT_MASK_XTAL_CK_SET_8822C) << BIT_SHIFT_XTAL_CK_SET_8822C) +#define BITS_XTAL_CK_SET_8822C \ + (BIT_MASK_XTAL_CK_SET_8822C << BIT_SHIFT_XTAL_CK_SET_8822C) +#define BIT_CLEAR_XTAL_CK_SET_8822C(x) ((x) & (~BITS_XTAL_CK_SET_8822C)) +#define BIT_GET_XTAL_CK_SET_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_CK_SET_8822C) & BIT_MASK_XTAL_CK_SET_8822C) +#define BIT_SET_XTAL_CK_SET_8822C(x, v) \ + (BIT_CLEAR_XTAL_CK_SET_8822C(x) | BIT_XTAL_CK_SET_8822C(v)) + +#define BIT_SHIFT_GM_INIT_8822C 8 +#define BIT_MASK_GM_INIT_8822C 0x1f +#define BIT_GM_INIT_8822C(x) \ + (((x) & BIT_MASK_GM_INIT_8822C) << BIT_SHIFT_GM_INIT_8822C) +#define BITS_GM_INIT_8822C (BIT_MASK_GM_INIT_8822C << BIT_SHIFT_GM_INIT_8822C) +#define BIT_CLEAR_GM_INIT_8822C(x) ((x) & (~BITS_GM_INIT_8822C)) +#define BIT_GET_GM_INIT_8822C(x) \ + (((x) >> BIT_SHIFT_GM_INIT_8822C) & BIT_MASK_GM_INIT_8822C) +#define BIT_SET_GM_INIT_8822C(x, v) \ + (BIT_CLEAR_GM_INIT_8822C(x) | BIT_GM_INIT_8822C(v)) + +#define BIT_GM_STEP_8822C BIT(7) + +#define BIT_SHIFT_XAAC_GM_OFFSET_8822C 2 +#define BIT_MASK_XAAC_GM_OFFSET_8822C 0x1f +#define BIT_XAAC_GM_OFFSET_8822C(x) \ + (((x) & BIT_MASK_XAAC_GM_OFFSET_8822C) \ + << BIT_SHIFT_XAAC_GM_OFFSET_8822C) +#define BITS_XAAC_GM_OFFSET_8822C \ + (BIT_MASK_XAAC_GM_OFFSET_8822C << BIT_SHIFT_XAAC_GM_OFFSET_8822C) +#define BIT_CLEAR_XAAC_GM_OFFSET_8822C(x) ((x) & (~BITS_XAAC_GM_OFFSET_8822C)) +#define BIT_GET_XAAC_GM_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_XAAC_GM_OFFSET_8822C) & \ + BIT_MASK_XAAC_GM_OFFSET_8822C) +#define BIT_SET_XAAC_GM_OFFSET_8822C(x, v) \ + (BIT_CLEAR_XAAC_GM_OFFSET_8822C(x) | BIT_XAAC_GM_OFFSET_8822C(v)) + +#define BIT_OFFSET_PLUS_8822C BIT(1) +#define BIT_RESET_N_8822C BIT(0) + +/* 2 REG_ANAPAR_XTAL_AACK_1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_PK_END_AR_8822C 3 +#define BIT_MASK_PK_END_AR_8822C 0x3 +#define BIT_PK_END_AR_8822C(x) \ + (((x) & BIT_MASK_PK_END_AR_8822C) << BIT_SHIFT_PK_END_AR_8822C) +#define BITS_PK_END_AR_8822C \ + (BIT_MASK_PK_END_AR_8822C << BIT_SHIFT_PK_END_AR_8822C) +#define BIT_CLEAR_PK_END_AR_8822C(x) ((x) & (~BITS_PK_END_AR_8822C)) +#define BIT_GET_PK_END_AR_8822C(x) \ + (((x) >> BIT_SHIFT_PK_END_AR_8822C) & BIT_MASK_PK_END_AR_8822C) +#define BIT_SET_PK_END_AR_8822C(x, v) \ + (BIT_CLEAR_PK_END_AR_8822C(x) | BIT_PK_END_AR_8822C(v)) + +#define BIT_SHIFT_PK_START_AR_8822C 1 +#define BIT_MASK_PK_START_AR_8822C 0x3 +#define BIT_PK_START_AR_8822C(x) \ + (((x) & BIT_MASK_PK_START_AR_8822C) << BIT_SHIFT_PK_START_AR_8822C) +#define BITS_PK_START_AR_8822C \ + (BIT_MASK_PK_START_AR_8822C << BIT_SHIFT_PK_START_AR_8822C) +#define BIT_CLEAR_PK_START_AR_8822C(x) ((x) & (~BITS_PK_START_AR_8822C)) +#define BIT_GET_PK_START_AR_8822C(x) \ + (((x) >> BIT_SHIFT_PK_START_AR_8822C) & BIT_MASK_PK_START_AR_8822C) +#define BIT_SET_PK_START_AR_8822C(x, v) \ + (BIT_CLEAR_PK_START_AR_8822C(x) | BIT_PK_START_AR_8822C(v)) + +#define BIT_XAAC_LUT_MANUAL_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ANAPAR_XTAL_MODE_DECODER_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_XTAL_LDO_LPS_8822C 21 +#define BIT_MASK_XTAL_LDO_LPS_8822C 0x7 +#define BIT_XTAL_LDO_LPS_8822C(x) \ + (((x) & BIT_MASK_XTAL_LDO_LPS_8822C) << BIT_SHIFT_XTAL_LDO_LPS_8822C) +#define BITS_XTAL_LDO_LPS_8822C \ + (BIT_MASK_XTAL_LDO_LPS_8822C << BIT_SHIFT_XTAL_LDO_LPS_8822C) +#define BIT_CLEAR_XTAL_LDO_LPS_8822C(x) ((x) & (~BITS_XTAL_LDO_LPS_8822C)) +#define BIT_GET_XTAL_LDO_LPS_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_LPS_8822C) & BIT_MASK_XTAL_LDO_LPS_8822C) +#define BIT_SET_XTAL_LDO_LPS_8822C(x, v) \ + (BIT_CLEAR_XTAL_LDO_LPS_8822C(x) | BIT_XTAL_LDO_LPS_8822C(v)) + +#define BIT_SHIFT_XTAL_WAIT_CYC_8822C 15 +#define BIT_MASK_XTAL_WAIT_CYC_8822C 0x3f +#define BIT_XTAL_WAIT_CYC_8822C(x) \ + (((x) & BIT_MASK_XTAL_WAIT_CYC_8822C) << BIT_SHIFT_XTAL_WAIT_CYC_8822C) +#define BITS_XTAL_WAIT_CYC_8822C \ + (BIT_MASK_XTAL_WAIT_CYC_8822C << BIT_SHIFT_XTAL_WAIT_CYC_8822C) +#define BIT_CLEAR_XTAL_WAIT_CYC_8822C(x) ((x) & (~BITS_XTAL_WAIT_CYC_8822C)) +#define BIT_GET_XTAL_WAIT_CYC_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_WAIT_CYC_8822C) & BIT_MASK_XTAL_WAIT_CYC_8822C) +#define BIT_SET_XTAL_WAIT_CYC_8822C(x, v) \ + (BIT_CLEAR_XTAL_WAIT_CYC_8822C(x) | BIT_XTAL_WAIT_CYC_8822C(v)) + +#define BIT_SHIFT_XTAL_LDO_OK_8822C 12 +#define BIT_MASK_XTAL_LDO_OK_8822C 0x7 +#define BIT_XTAL_LDO_OK_8822C(x) \ + (((x) & BIT_MASK_XTAL_LDO_OK_8822C) << BIT_SHIFT_XTAL_LDO_OK_8822C) +#define BITS_XTAL_LDO_OK_8822C \ + (BIT_MASK_XTAL_LDO_OK_8822C << BIT_SHIFT_XTAL_LDO_OK_8822C) +#define BIT_CLEAR_XTAL_LDO_OK_8822C(x) ((x) & (~BITS_XTAL_LDO_OK_8822C)) +#define BIT_GET_XTAL_LDO_OK_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_LDO_OK_8822C) & BIT_MASK_XTAL_LDO_OK_8822C) +#define BIT_SET_XTAL_LDO_OK_8822C(x, v) \ + (BIT_CLEAR_XTAL_LDO_OK_8822C(x) | BIT_XTAL_LDO_OK_8822C(v)) + +#define BIT_XTAL_MD_LPOW_8822C BIT(11) + +#define BIT_SHIFT_XTAL_OV_RATIO_8822C 9 +#define BIT_MASK_XTAL_OV_RATIO_8822C 0x3 +#define BIT_XTAL_OV_RATIO_8822C(x) \ + (((x) & BIT_MASK_XTAL_OV_RATIO_8822C) << BIT_SHIFT_XTAL_OV_RATIO_8822C) +#define BITS_XTAL_OV_RATIO_8822C \ + (BIT_MASK_XTAL_OV_RATIO_8822C << BIT_SHIFT_XTAL_OV_RATIO_8822C) +#define BIT_CLEAR_XTAL_OV_RATIO_8822C(x) ((x) & (~BITS_XTAL_OV_RATIO_8822C)) +#define BIT_GET_XTAL_OV_RATIO_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_OV_RATIO_8822C) & BIT_MASK_XTAL_OV_RATIO_8822C) +#define BIT_SET_XTAL_OV_RATIO_8822C(x, v) \ + (BIT_CLEAR_XTAL_OV_RATIO_8822C(x) | BIT_XTAL_OV_RATIO_8822C(v)) + +#define BIT_SHIFT_XTAL_OV_UNIT_8822C 6 +#define BIT_MASK_XTAL_OV_UNIT_8822C 0x7 +#define BIT_XTAL_OV_UNIT_8822C(x) \ + (((x) & BIT_MASK_XTAL_OV_UNIT_8822C) << BIT_SHIFT_XTAL_OV_UNIT_8822C) +#define BITS_XTAL_OV_UNIT_8822C \ + (BIT_MASK_XTAL_OV_UNIT_8822C << BIT_SHIFT_XTAL_OV_UNIT_8822C) +#define BIT_CLEAR_XTAL_OV_UNIT_8822C(x) ((x) & (~BITS_XTAL_OV_UNIT_8822C)) +#define BIT_GET_XTAL_OV_UNIT_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_OV_UNIT_8822C) & BIT_MASK_XTAL_OV_UNIT_8822C) +#define BIT_SET_XTAL_OV_UNIT_8822C(x, v) \ + (BIT_CLEAR_XTAL_OV_UNIT_8822C(x) | BIT_XTAL_OV_UNIT_8822C(v)) + +#define BIT_SHIFT_XTAL_MODE_MANUAL_8822C 4 +#define BIT_MASK_XTAL_MODE_MANUAL_8822C 0x3 +#define BIT_XTAL_MODE_MANUAL_8822C(x) \ + (((x) & BIT_MASK_XTAL_MODE_MANUAL_8822C) \ + << BIT_SHIFT_XTAL_MODE_MANUAL_8822C) +#define BITS_XTAL_MODE_MANUAL_8822C \ + (BIT_MASK_XTAL_MODE_MANUAL_8822C << BIT_SHIFT_XTAL_MODE_MANUAL_8822C) +#define BIT_CLEAR_XTAL_MODE_MANUAL_8822C(x) \ + ((x) & (~BITS_XTAL_MODE_MANUAL_8822C)) +#define BIT_GET_XTAL_MODE_MANUAL_8822C(x) \ + (((x) >> BIT_SHIFT_XTAL_MODE_MANUAL_8822C) & \ + BIT_MASK_XTAL_MODE_MANUAL_8822C) +#define BIT_SET_XTAL_MODE_MANUAL_8822C(x, v) \ + (BIT_CLEAR_XTAL_MODE_MANUAL_8822C(x) | BIT_XTAL_MODE_MANUAL_8822C(v)) + +#define BIT_XTAL_MANU_SEL_8822C BIT(3) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_XTAL_MODE_8822C BIT(1) +#define BIT_RESET_N_DECODER_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SYS_CFG5_8822C */ +#define BIT_LPS_STATUS_8822C BIT(3) +#define BIT_HCI_TXDMA_BUSY_8822C BIT(2) +#define BIT_HCI_TXDMA_ALLOW_8822C BIT(1) +#define BIT_FW_CTRL_HCI_TXDMA_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_CPU_DMEM_CON_8822C */ +#define BIT_WDT_AUTO_MODE_8822C BIT(22) +#define BIT_WDT_PLATFORM_EN_8822C BIT(21) +#define BIT_WDT_CPU_EN_8822C BIT(20) +#define BIT_WDT_OPT_IOWRAPPER_8822C BIT(19) +#define BIT_ANA_PORT_IDLE_8822C BIT(18) +#define BIT_MAC_PORT_IDLE_8822C BIT(17) +#define BIT_WL_PLATFORM_RST_8822C BIT(16) +#define BIT_WL_SECURITY_CLK_8822C BIT(15) +#define BIT_DDMA_EN_8822C BIT(8) + +#define BIT_SHIFT_CPU_DMEM_CON_8822C 0 +#define BIT_MASK_CPU_DMEM_CON_8822C 0xff +#define BIT_CPU_DMEM_CON_8822C(x) \ + (((x) & BIT_MASK_CPU_DMEM_CON_8822C) << BIT_SHIFT_CPU_DMEM_CON_8822C) +#define BITS_CPU_DMEM_CON_8822C \ + (BIT_MASK_CPU_DMEM_CON_8822C << BIT_SHIFT_CPU_DMEM_CON_8822C) +#define BIT_CLEAR_CPU_DMEM_CON_8822C(x) ((x) & (~BITS_CPU_DMEM_CON_8822C)) +#define BIT_GET_CPU_DMEM_CON_8822C(x) \ + (((x) >> BIT_SHIFT_CPU_DMEM_CON_8822C) & BIT_MASK_CPU_DMEM_CON_8822C) +#define BIT_SET_CPU_DMEM_CON_8822C(x, v) \ + (BIT_CLEAR_CPU_DMEM_CON_8822C(x) | BIT_CPU_DMEM_CON_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_BOOT_REASON_8822C */ + +#define BIT_SHIFT_BOOT_REASON_V1_8822C 0 +#define BIT_MASK_BOOT_REASON_V1_8822C 0x7 +#define BIT_BOOT_REASON_V1_8822C(x) \ + (((x) & BIT_MASK_BOOT_REASON_V1_8822C) \ + << BIT_SHIFT_BOOT_REASON_V1_8822C) +#define BITS_BOOT_REASON_V1_8822C \ + (BIT_MASK_BOOT_REASON_V1_8822C << BIT_SHIFT_BOOT_REASON_V1_8822C) +#define BIT_CLEAR_BOOT_REASON_V1_8822C(x) ((x) & (~BITS_BOOT_REASON_V1_8822C)) +#define BIT_GET_BOOT_REASON_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BOOT_REASON_V1_8822C) & \ + BIT_MASK_BOOT_REASON_V1_8822C) +#define BIT_SET_BOOT_REASON_V1_8822C(x, v) \ + (BIT_CLEAR_BOOT_REASON_V1_8822C(x) | BIT_BOOT_REASON_V1_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_HIMR2_8822C */ +#define BIT_BCNDMAINT_P4_MSK_8822C BIT(31) +#define BIT_BCNDMAINT_P3_MSK_8822C BIT(30) +#define BIT_BCNDMAINT_P2_MSK_8822C BIT(29) +#define BIT_BCNDMAINT_P1_MSK_8822C BIT(28) +#define BIT_ATIMEND7_MSK_8822C BIT(22) +#define BIT_ATIMEND6_MSK_8822C BIT(21) +#define BIT_ATIMEND5_MSK_8822C BIT(20) +#define BIT_ATIMEND4_MSK_8822C BIT(19) +#define BIT_ATIMEND3_MSK_8822C BIT(18) +#define BIT_ATIMEND2_MSK_8822C BIT(17) +#define BIT_ATIMEND1_MSK_8822C BIT(16) +#define BIT_TXBCN7OK_MSK_8822C BIT(14) +#define BIT_TXBCN6OK_MSK_8822C BIT(13) +#define BIT_TXBCN5OK_MSK_8822C BIT(12) +#define BIT_TXBCN4OK_MSK_8822C BIT(11) +#define BIT_TXBCN3OK_MSK_8822C BIT(10) +#define BIT_TXBCN2OK_MSK_8822C BIT(9) +#define BIT_TXBCN1OK_MSK_V1_8822C BIT(8) +#define BIT_TXBCN7ERR_MSK_8822C BIT(6) +#define BIT_TXBCN6ERR_MSK_8822C BIT(5) +#define BIT_TXBCN5ERR_MSK_8822C BIT(4) +#define BIT_TXBCN4ERR_MSK_8822C BIT(3) +#define BIT_TXBCN3ERR_MSK_8822C BIT(2) +#define BIT_TXBCN2ERR_MSK_8822C BIT(1) +#define BIT_TXBCN1ERR_MSK_V1_8822C BIT(0) + +/* 2 REG_HISR2_8822C */ +#define BIT_BCNDMAINT_P4_8822C BIT(31) +#define BIT_BCNDMAINT_P3_8822C BIT(30) +#define BIT_BCNDMAINT_P2_8822C BIT(29) +#define BIT_BCNDMAINT_P1_8822C BIT(28) +#define BIT_ATIMEND7_8822C BIT(22) +#define BIT_ATIMEND6_8822C BIT(21) +#define BIT_ATIMEND5_8822C BIT(20) +#define BIT_ATIMEND4_8822C BIT(19) +#define BIT_ATIMEND3_8822C BIT(18) +#define BIT_ATIMEND2_8822C BIT(17) +#define BIT_ATIMEND1_8822C BIT(16) +#define BIT_TXBCN7OK_8822C BIT(14) +#define BIT_TXBCN6OK_8822C BIT(13) +#define BIT_TXBCN5OK_8822C BIT(12) +#define BIT_TXBCN4OK_8822C BIT(11) +#define BIT_TXBCN3OK_8822C BIT(10) +#define BIT_TXBCN2OK_8822C BIT(9) +#define BIT_TXBCN1OK_8822C BIT(8) +#define BIT_TXBCN7ERR_8822C BIT(6) +#define BIT_TXBCN6ERR_8822C BIT(5) +#define BIT_TXBCN5ERR_8822C BIT(4) +#define BIT_TXBCN4ERR_8822C BIT(3) +#define BIT_TXBCN3ERR_8822C BIT(2) +#define BIT_TXBCN2ERR_8822C BIT(1) +#define BIT_TXBCN1ERR_8822C BIT(0) + +/* 2 REG_HIMR3_8822C */ +#define BIT_WDT_PLATFORM_INT_MSK_8822C BIT(18) +#define BIT_WDT_CPU_INT_MSK_8822C BIT(17) +#define BIT_SETH2CDOK_MASK_8822C BIT(16) +#define BIT_H2C_CMD_FULL_MASK_8822C BIT(15) +#define BIT_PWR_INT_127_MASK_8822C BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8822C BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8822C BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8822C BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8822C BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8822C BIT(9) +#define BIT_PWR_INT_127_MASK_V1_8822C BIT(8) +#define BIT_PWR_INT_126TO96_MASK_8822C BIT(7) +#define BIT_PWR_INT_95TO64_MASK_8822C BIT(6) +#define BIT_PWR_INT_63TO32_MASK_8822C BIT(5) +#define BIT_PWR_INT_31TO0_MASK_8822C BIT(4) +#define BIT_RX_DMA_STUCK_MSK_8822C BIT(3) +#define BIT_TX_DMA_STUCK_MSK_8822C BIT(2) +#define BIT_DDMA0_LP_INT_MSK_8822C BIT(1) +#define BIT_DDMA0_HP_INT_MSK_8822C BIT(0) + +/* 2 REG_HISR3_8822C */ +#define BIT_WDT_PLATFORM_INT_8822C BIT(18) +#define BIT_WDT_CPU_INT_8822C BIT(17) +#define BIT_SETH2CDOK_8822C BIT(16) +#define BIT_H2C_CMD_FULL_8822C BIT(15) +#define BIT_PWR_INT_127_8822C BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822C BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_8822C BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_8822C BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_8822C BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_8822C BIT(9) +#define BIT_PWR_INT_127_V1_8822C BIT(8) +#define BIT_PWR_INT_126TO96_8822C BIT(7) +#define BIT_PWR_INT_95TO64_8822C BIT(6) +#define BIT_PWR_INT_63TO32_8822C BIT(5) +#define BIT_PWR_INT_31TO0_8822C BIT(4) +#define BIT_RX_DMA_STUCK_8822C BIT(3) +#define BIT_TX_DMA_STUCK_8822C BIT(2) +#define BIT_DDMA0_LP_INT_8822C BIT(1) +#define BIT_DDMA0_HP_INT_8822C BIT(0) + +/* 2 REG_SW_MDIO_8822C */ +#define BIT_DIS_TIMEOUT_IO_8822C BIT(24) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_H2C_PKT_READADDR_8822C */ + +#define BIT_SHIFT_H2C_PKT_READADDR_8822C 0 +#define BIT_MASK_H2C_PKT_READADDR_8822C 0x3ffff +#define BIT_H2C_PKT_READADDR_8822C(x) \ + (((x) & BIT_MASK_H2C_PKT_READADDR_8822C) \ + << BIT_SHIFT_H2C_PKT_READADDR_8822C) +#define BITS_H2C_PKT_READADDR_8822C \ + (BIT_MASK_H2C_PKT_READADDR_8822C << BIT_SHIFT_H2C_PKT_READADDR_8822C) +#define BIT_CLEAR_H2C_PKT_READADDR_8822C(x) \ + ((x) & (~BITS_H2C_PKT_READADDR_8822C)) +#define BIT_GET_H2C_PKT_READADDR_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822C) & \ + BIT_MASK_H2C_PKT_READADDR_8822C) +#define BIT_SET_H2C_PKT_READADDR_8822C(x, v) \ + (BIT_CLEAR_H2C_PKT_READADDR_8822C(x) | BIT_H2C_PKT_READADDR_8822C(v)) + +/* 2 REG_H2C_PKT_WRITEADDR_8822C */ + +#define BIT_SHIFT_H2C_PKT_WRITEADDR_8822C 0 +#define BIT_MASK_H2C_PKT_WRITEADDR_8822C 0x3ffff +#define BIT_H2C_PKT_WRITEADDR_8822C(x) \ + (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822C) \ + << BIT_SHIFT_H2C_PKT_WRITEADDR_8822C) +#define BITS_H2C_PKT_WRITEADDR_8822C \ + (BIT_MASK_H2C_PKT_WRITEADDR_8822C << BIT_SHIFT_H2C_PKT_WRITEADDR_8822C) +#define BIT_CLEAR_H2C_PKT_WRITEADDR_8822C(x) \ + ((x) & (~BITS_H2C_PKT_WRITEADDR_8822C)) +#define BIT_GET_H2C_PKT_WRITEADDR_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822C) & \ + BIT_MASK_H2C_PKT_WRITEADDR_8822C) +#define BIT_SET_H2C_PKT_WRITEADDR_8822C(x, v) \ + (BIT_CLEAR_H2C_PKT_WRITEADDR_8822C(x) | BIT_H2C_PKT_WRITEADDR_8822C(v)) + +/* 2 REG_MEM_PWR_CRTL_8822C */ +#define BIT_MEM_BB_SD_8822C BIT(17) +#define BIT_MEM_BB_DS_8822C BIT(16) +#define BIT_MEM_BT_DS_8822C BIT(10) +#define BIT_MEM_SDIO_LS_8822C BIT(9) +#define BIT_MEM_SDIO_DS_8822C BIT(8) +#define BIT_MEM_USB_LS_8822C BIT(7) +#define BIT_MEM_USB_DS_8822C BIT(6) +#define BIT_MEM_PCI_LS_8822C BIT(5) +#define BIT_MEM_PCI_DS_8822C BIT(4) +#define BIT_MEM_WLMAC_LS_8822C BIT(3) +#define BIT_MEM_WLMAC_DS_8822C BIT(2) +#define BIT_MEM_WLMCU_LS_8822C BIT(1) +#define BIT_MEM_WLMCU_DS_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_FW_DBG6_8822C */ + +#define BIT_SHIFT_FW_DBG6_8822C 0 +#define BIT_MASK_FW_DBG6_8822C 0xffffffffL +#define BIT_FW_DBG6_8822C(x) \ + (((x) & BIT_MASK_FW_DBG6_8822C) << BIT_SHIFT_FW_DBG6_8822C) +#define BITS_FW_DBG6_8822C (BIT_MASK_FW_DBG6_8822C << BIT_SHIFT_FW_DBG6_8822C) +#define BIT_CLEAR_FW_DBG6_8822C(x) ((x) & (~BITS_FW_DBG6_8822C)) +#define BIT_GET_FW_DBG6_8822C(x) \ + (((x) >> BIT_SHIFT_FW_DBG6_8822C) & BIT_MASK_FW_DBG6_8822C) +#define BIT_SET_FW_DBG6_8822C(x, v) \ + (BIT_CLEAR_FW_DBG6_8822C(x) | BIT_FW_DBG6_8822C(v)) + +/* 2 REG_FW_DBG7_8822C */ + +#define BIT_SHIFT_FW_DBG7_8822C 0 +#define BIT_MASK_FW_DBG7_8822C 0xffffffffL +#define BIT_FW_DBG7_8822C(x) \ + (((x) & BIT_MASK_FW_DBG7_8822C) << BIT_SHIFT_FW_DBG7_8822C) +#define BITS_FW_DBG7_8822C (BIT_MASK_FW_DBG7_8822C << BIT_SHIFT_FW_DBG7_8822C) +#define BIT_CLEAR_FW_DBG7_8822C(x) ((x) & (~BITS_FW_DBG7_8822C)) +#define BIT_GET_FW_DBG7_8822C(x) \ + (((x) >> BIT_SHIFT_FW_DBG7_8822C) & BIT_MASK_FW_DBG7_8822C) +#define BIT_SET_FW_DBG7_8822C(x, v) \ + (BIT_CLEAR_FW_DBG7_8822C(x) | BIT_FW_DBG7_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_CR_8822C */ + +#define BIT_SHIFT_LBMODE_8822C 24 +#define BIT_MASK_LBMODE_8822C 0x1f +#define BIT_LBMODE_8822C(x) \ + (((x) & BIT_MASK_LBMODE_8822C) << BIT_SHIFT_LBMODE_8822C) +#define BITS_LBMODE_8822C (BIT_MASK_LBMODE_8822C << BIT_SHIFT_LBMODE_8822C) +#define BIT_CLEAR_LBMODE_8822C(x) ((x) & (~BITS_LBMODE_8822C)) +#define BIT_GET_LBMODE_8822C(x) \ + (((x) >> BIT_SHIFT_LBMODE_8822C) & BIT_MASK_LBMODE_8822C) +#define BIT_SET_LBMODE_8822C(x, v) \ + (BIT_CLEAR_LBMODE_8822C(x) | BIT_LBMODE_8822C(v)) + +#define BIT_SHIFT_NETYPE1_8822C 18 +#define BIT_MASK_NETYPE1_8822C 0x3 +#define BIT_NETYPE1_8822C(x) \ + (((x) & BIT_MASK_NETYPE1_8822C) << BIT_SHIFT_NETYPE1_8822C) +#define BITS_NETYPE1_8822C (BIT_MASK_NETYPE1_8822C << BIT_SHIFT_NETYPE1_8822C) +#define BIT_CLEAR_NETYPE1_8822C(x) ((x) & (~BITS_NETYPE1_8822C)) +#define BIT_GET_NETYPE1_8822C(x) \ + (((x) >> BIT_SHIFT_NETYPE1_8822C) & BIT_MASK_NETYPE1_8822C) +#define BIT_SET_NETYPE1_8822C(x, v) \ + (BIT_CLEAR_NETYPE1_8822C(x) | BIT_NETYPE1_8822C(v)) + +#define BIT_SHIFT_NETYPE0_8822C 16 +#define BIT_MASK_NETYPE0_8822C 0x3 +#define BIT_NETYPE0_8822C(x) \ + (((x) & BIT_MASK_NETYPE0_8822C) << BIT_SHIFT_NETYPE0_8822C) +#define BITS_NETYPE0_8822C (BIT_MASK_NETYPE0_8822C << BIT_SHIFT_NETYPE0_8822C) +#define BIT_CLEAR_NETYPE0_8822C(x) ((x) & (~BITS_NETYPE0_8822C)) +#define BIT_GET_NETYPE0_8822C(x) \ + (((x) >> BIT_SHIFT_NETYPE0_8822C) & BIT_MASK_NETYPE0_8822C) +#define BIT_SET_NETYPE0_8822C(x, v) \ + (BIT_CLEAR_NETYPE0_8822C(x) | BIT_NETYPE0_8822C(v)) + +#define BIT_COUNTER_STS_EN_8822C BIT(13) +#define BIT_I2C_MAILBOX_EN_8822C BIT(12) +#define BIT_SHCUT_EN_8822C BIT(11) +#define BIT_32K_CAL_TMR_EN_8822C BIT(10) +#define BIT_MAC_SEC_EN_8822C BIT(9) +#define BIT_ENSWBCN_8822C BIT(8) +#define BIT_MACRXEN_8822C BIT(7) +#define BIT_MACTXEN_8822C BIT(6) +#define BIT_SCHEDULE_EN_8822C BIT(5) +#define BIT_PROTOCOL_EN_8822C BIT(4) +#define BIT_RXDMA_EN_8822C BIT(3) +#define BIT_TXDMA_EN_8822C BIT(2) +#define BIT_HCI_RXDMA_EN_8822C BIT(1) +#define BIT_HCI_TXDMA_EN_8822C BIT(0) + +/* 2 REG_PG_SIZE_8822C */ + +#define BIT_SHIFT_DBG_FIFO_SEL_8822C 16 +#define BIT_MASK_DBG_FIFO_SEL_8822C 0xff +#define BIT_DBG_FIFO_SEL_8822C(x) \ + (((x) & BIT_MASK_DBG_FIFO_SEL_8822C) << BIT_SHIFT_DBG_FIFO_SEL_8822C) +#define BITS_DBG_FIFO_SEL_8822C \ + (BIT_MASK_DBG_FIFO_SEL_8822C << BIT_SHIFT_DBG_FIFO_SEL_8822C) +#define BIT_CLEAR_DBG_FIFO_SEL_8822C(x) ((x) & (~BITS_DBG_FIFO_SEL_8822C)) +#define BIT_GET_DBG_FIFO_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_DBG_FIFO_SEL_8822C) & BIT_MASK_DBG_FIFO_SEL_8822C) +#define BIT_SET_DBG_FIFO_SEL_8822C(x, v) \ + (BIT_CLEAR_DBG_FIFO_SEL_8822C(x) | BIT_DBG_FIFO_SEL_8822C(v)) + +/* 2 REG_PKT_BUFF_ACCESS_CTRL_8822C */ + +#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C 0 +#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C 0xff +#define BIT_PKT_BUFF_ACCESS_CTRL_8822C(x) \ + (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C) \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C) +#define BITS_PKT_BUFF_ACCESS_CTRL_8822C \ + (BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C \ + << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C) +#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8822C(x) \ + ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8822C)) +#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8822C(x) \ + (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C) & \ + BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C) +#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8822C(x, v) \ + (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8822C(x) | \ + BIT_PKT_BUFF_ACCESS_CTRL_8822C(v)) + +/* 2 REG_TSF_CLK_STATE_8822C */ +#define BIT_TSF_CLK_STABLE_8822C BIT(15) + +/* 2 REG_TXDMA_PQ_MAP_8822C */ +#define BIT_CSI_BW_EN_8822C BIT(31) + +#define BIT_SHIFT_TXDMA_H2C_MAP_8822C 16 +#define BIT_MASK_TXDMA_H2C_MAP_8822C 0x3 +#define BIT_TXDMA_H2C_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_H2C_MAP_8822C) << BIT_SHIFT_TXDMA_H2C_MAP_8822C) +#define BITS_TXDMA_H2C_MAP_8822C \ + (BIT_MASK_TXDMA_H2C_MAP_8822C << BIT_SHIFT_TXDMA_H2C_MAP_8822C) +#define BIT_CLEAR_TXDMA_H2C_MAP_8822C(x) ((x) & (~BITS_TXDMA_H2C_MAP_8822C)) +#define BIT_GET_TXDMA_H2C_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8822C) & BIT_MASK_TXDMA_H2C_MAP_8822C) +#define BIT_SET_TXDMA_H2C_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_H2C_MAP_8822C(x) | BIT_TXDMA_H2C_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_HIQ_MAP_8822C 14 +#define BIT_MASK_TXDMA_HIQ_MAP_8822C 0x3 +#define BIT_TXDMA_HIQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_HIQ_MAP_8822C) << BIT_SHIFT_TXDMA_HIQ_MAP_8822C) +#define BITS_TXDMA_HIQ_MAP_8822C \ + (BIT_MASK_TXDMA_HIQ_MAP_8822C << BIT_SHIFT_TXDMA_HIQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_HIQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8822C)) +#define BIT_GET_TXDMA_HIQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822C) & BIT_MASK_TXDMA_HIQ_MAP_8822C) +#define BIT_SET_TXDMA_HIQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_HIQ_MAP_8822C(x) | BIT_TXDMA_HIQ_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_MGQ_MAP_8822C 12 +#define BIT_MASK_TXDMA_MGQ_MAP_8822C 0x3 +#define BIT_TXDMA_MGQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_MGQ_MAP_8822C) << BIT_SHIFT_TXDMA_MGQ_MAP_8822C) +#define BITS_TXDMA_MGQ_MAP_8822C \ + (BIT_MASK_TXDMA_MGQ_MAP_8822C << BIT_SHIFT_TXDMA_MGQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_MGQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8822C)) +#define BIT_GET_TXDMA_MGQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822C) & BIT_MASK_TXDMA_MGQ_MAP_8822C) +#define BIT_SET_TXDMA_MGQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_MGQ_MAP_8822C(x) | BIT_TXDMA_MGQ_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_BKQ_MAP_8822C 10 +#define BIT_MASK_TXDMA_BKQ_MAP_8822C 0x3 +#define BIT_TXDMA_BKQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_BKQ_MAP_8822C) << BIT_SHIFT_TXDMA_BKQ_MAP_8822C) +#define BITS_TXDMA_BKQ_MAP_8822C \ + (BIT_MASK_TXDMA_BKQ_MAP_8822C << BIT_SHIFT_TXDMA_BKQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_BKQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8822C)) +#define BIT_GET_TXDMA_BKQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822C) & BIT_MASK_TXDMA_BKQ_MAP_8822C) +#define BIT_SET_TXDMA_BKQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_BKQ_MAP_8822C(x) | BIT_TXDMA_BKQ_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_BEQ_MAP_8822C 8 +#define BIT_MASK_TXDMA_BEQ_MAP_8822C 0x3 +#define BIT_TXDMA_BEQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_BEQ_MAP_8822C) << BIT_SHIFT_TXDMA_BEQ_MAP_8822C) +#define BITS_TXDMA_BEQ_MAP_8822C \ + (BIT_MASK_TXDMA_BEQ_MAP_8822C << BIT_SHIFT_TXDMA_BEQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_BEQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8822C)) +#define BIT_GET_TXDMA_BEQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822C) & BIT_MASK_TXDMA_BEQ_MAP_8822C) +#define BIT_SET_TXDMA_BEQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_BEQ_MAP_8822C(x) | BIT_TXDMA_BEQ_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_VIQ_MAP_8822C 6 +#define BIT_MASK_TXDMA_VIQ_MAP_8822C 0x3 +#define BIT_TXDMA_VIQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_VIQ_MAP_8822C) << BIT_SHIFT_TXDMA_VIQ_MAP_8822C) +#define BITS_TXDMA_VIQ_MAP_8822C \ + (BIT_MASK_TXDMA_VIQ_MAP_8822C << BIT_SHIFT_TXDMA_VIQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_VIQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8822C)) +#define BIT_GET_TXDMA_VIQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822C) & BIT_MASK_TXDMA_VIQ_MAP_8822C) +#define BIT_SET_TXDMA_VIQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_VIQ_MAP_8822C(x) | BIT_TXDMA_VIQ_MAP_8822C(v)) + +#define BIT_SHIFT_TXDMA_VOQ_MAP_8822C 4 +#define BIT_MASK_TXDMA_VOQ_MAP_8822C 0x3 +#define BIT_TXDMA_VOQ_MAP_8822C(x) \ + (((x) & BIT_MASK_TXDMA_VOQ_MAP_8822C) << BIT_SHIFT_TXDMA_VOQ_MAP_8822C) +#define BITS_TXDMA_VOQ_MAP_8822C \ + (BIT_MASK_TXDMA_VOQ_MAP_8822C << BIT_SHIFT_TXDMA_VOQ_MAP_8822C) +#define BIT_CLEAR_TXDMA_VOQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8822C)) +#define BIT_GET_TXDMA_VOQ_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822C) & BIT_MASK_TXDMA_VOQ_MAP_8822C) +#define BIT_SET_TXDMA_VOQ_MAP_8822C(x, v) \ + (BIT_CLEAR_TXDMA_VOQ_MAP_8822C(x) | BIT_TXDMA_VOQ_MAP_8822C(v)) + +#define BIT_TXDMA_BW_EN_8822C BIT(3) +#define BIT_RXDMA_AGG_EN_8822C BIT(2) +#define BIT_RXSHFT_EN_8822C BIT(1) +#define BIT_RXDMA_ARBBW_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_TRXFF_BNDY_8822C */ + +#define BIT_SHIFT_FWFFOVFL_RSV_8822C 16 +#define BIT_MASK_FWFFOVFL_RSV_8822C 0xf +#define BIT_FWFFOVFL_RSV_8822C(x) \ + (((x) & BIT_MASK_FWFFOVFL_RSV_8822C) << BIT_SHIFT_FWFFOVFL_RSV_8822C) +#define BITS_FWFFOVFL_RSV_8822C \ + (BIT_MASK_FWFFOVFL_RSV_8822C << BIT_SHIFT_FWFFOVFL_RSV_8822C) +#define BIT_CLEAR_FWFFOVFL_RSV_8822C(x) ((x) & (~BITS_FWFFOVFL_RSV_8822C)) +#define BIT_GET_FWFFOVFL_RSV_8822C(x) \ + (((x) >> BIT_SHIFT_FWFFOVFL_RSV_8822C) & BIT_MASK_FWFFOVFL_RSV_8822C) +#define BIT_SET_FWFFOVFL_RSV_8822C(x, v) \ + (BIT_CLEAR_FWFFOVFL_RSV_8822C(x) | BIT_FWFFOVFL_RSV_8822C(v)) + +#define BIT_SHIFT_RXFFOVFL_RSV_V2_8822C 8 +#define BIT_MASK_RXFFOVFL_RSV_V2_8822C 0xf +#define BIT_RXFFOVFL_RSV_V2_8822C(x) \ + (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822C) \ + << BIT_SHIFT_RXFFOVFL_RSV_V2_8822C) +#define BITS_RXFFOVFL_RSV_V2_8822C \ + (BIT_MASK_RXFFOVFL_RSV_V2_8822C << BIT_SHIFT_RXFFOVFL_RSV_V2_8822C) +#define BIT_CLEAR_RXFFOVFL_RSV_V2_8822C(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8822C)) +#define BIT_GET_RXFFOVFL_RSV_V2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822C) & \ + BIT_MASK_RXFFOVFL_RSV_V2_8822C) +#define BIT_SET_RXFFOVFL_RSV_V2_8822C(x, v) \ + (BIT_CLEAR_RXFFOVFL_RSV_V2_8822C(x) | BIT_RXFFOVFL_RSV_V2_8822C(v)) + +/* 2 REG_PTA_I2C_MBOX_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_I2C_M_STATUS_8822C 8 +#define BIT_MASK_I2C_M_STATUS_8822C 0xf +#define BIT_I2C_M_STATUS_8822C(x) \ + (((x) & BIT_MASK_I2C_M_STATUS_8822C) << BIT_SHIFT_I2C_M_STATUS_8822C) +#define BITS_I2C_M_STATUS_8822C \ + (BIT_MASK_I2C_M_STATUS_8822C << BIT_SHIFT_I2C_M_STATUS_8822C) +#define BIT_CLEAR_I2C_M_STATUS_8822C(x) ((x) & (~BITS_I2C_M_STATUS_8822C)) +#define BIT_GET_I2C_M_STATUS_8822C(x) \ + (((x) >> BIT_SHIFT_I2C_M_STATUS_8822C) & BIT_MASK_I2C_M_STATUS_8822C) +#define BIT_SET_I2C_M_STATUS_8822C(x, v) \ + (BIT_CLEAR_I2C_M_STATUS_8822C(x) | BIT_I2C_M_STATUS_8822C(v)) + +#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C 4 +#define BIT_MASK_I2C_M_BUS_GNT_FW_8822C 0x7 +#define BIT_I2C_M_BUS_GNT_FW_8822C(x) \ + (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822C) \ + << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C) +#define BITS_I2C_M_BUS_GNT_FW_8822C \ + (BIT_MASK_I2C_M_BUS_GNT_FW_8822C << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C) +#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8822C(x) \ + ((x) & (~BITS_I2C_M_BUS_GNT_FW_8822C)) +#define BIT_GET_I2C_M_BUS_GNT_FW_8822C(x) \ + (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C) & \ + BIT_MASK_I2C_M_BUS_GNT_FW_8822C) +#define BIT_SET_I2C_M_BUS_GNT_FW_8822C(x, v) \ + (BIT_CLEAR_I2C_M_BUS_GNT_FW_8822C(x) | BIT_I2C_M_BUS_GNT_FW_8822C(v)) + +#define BIT_I2C_M_GNT_FW_8822C BIT(3) + +#define BIT_SHIFT_I2C_M_SPEED_8822C 1 +#define BIT_MASK_I2C_M_SPEED_8822C 0x3 +#define BIT_I2C_M_SPEED_8822C(x) \ + (((x) & BIT_MASK_I2C_M_SPEED_8822C) << BIT_SHIFT_I2C_M_SPEED_8822C) +#define BITS_I2C_M_SPEED_8822C \ + (BIT_MASK_I2C_M_SPEED_8822C << BIT_SHIFT_I2C_M_SPEED_8822C) +#define BIT_CLEAR_I2C_M_SPEED_8822C(x) ((x) & (~BITS_I2C_M_SPEED_8822C)) +#define BIT_GET_I2C_M_SPEED_8822C(x) \ + (((x) >> BIT_SHIFT_I2C_M_SPEED_8822C) & BIT_MASK_I2C_M_SPEED_8822C) +#define BIT_SET_I2C_M_SPEED_8822C(x, v) \ + (BIT_CLEAR_I2C_M_SPEED_8822C(x) | BIT_I2C_M_SPEED_8822C(v)) + +#define BIT_I2C_M_UNLOCK_8822C BIT(0) + +/* 2 REG_RXFF_BNDY_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_RXFF0_BNDY_V2_8822C 0 +#define BIT_MASK_RXFF0_BNDY_V2_8822C 0x3ffff +#define BIT_RXFF0_BNDY_V2_8822C(x) \ + (((x) & BIT_MASK_RXFF0_BNDY_V2_8822C) << BIT_SHIFT_RXFF0_BNDY_V2_8822C) +#define BITS_RXFF0_BNDY_V2_8822C \ + (BIT_MASK_RXFF0_BNDY_V2_8822C << BIT_SHIFT_RXFF0_BNDY_V2_8822C) +#define BIT_CLEAR_RXFF0_BNDY_V2_8822C(x) ((x) & (~BITS_RXFF0_BNDY_V2_8822C)) +#define BIT_GET_RXFF0_BNDY_V2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822C) & BIT_MASK_RXFF0_BNDY_V2_8822C) +#define BIT_SET_RXFF0_BNDY_V2_8822C(x, v) \ + (BIT_CLEAR_RXFF0_BNDY_V2_8822C(x) | BIT_RXFF0_BNDY_V2_8822C(v)) + +/* 2 REG_FE1IMR_8822C */ +#define BIT_FS_SW_PLL_LEAVE_32K_INT_EN_8822C BIT(31) +#define BIT_FS_FWFF_FULL_INT_EN_8822C BIT(30) +#define BIT_FS_BB_STOP_RX_INT_EN_8822C BIT(29) +#define BIT_FS_RXDMA2_DONE_INT_EN_8822C BIT(28) +#define BIT_FS_RXDONE2_INT_EN_8822C BIT(26) +#define BIT_FS_RX_BCN_P4_INT_EN_8822C BIT(25) +#define BIT_FS_RX_BCN_P3_INT_EN_8822C BIT(24) +#define BIT_FS_RX_BCN_P2_INT_EN_8822C BIT(23) +#define BIT_FS_RX_BCN_P1_INT_EN_8822C BIT(22) +#define BIT_FS_RX_BCN_P0_INT_EN_8822C BIT(21) +#define BIT_FS_RX_UMD0_INT_EN_8822C BIT(20) +#define BIT_FS_RX_UMD1_INT_EN_8822C BIT(19) +#define BIT_FS_RX_BMD0_INT_EN_8822C BIT(18) +#define BIT_FS_RX_BMD1_INT_EN_8822C BIT(17) +#define BIT_FS_RXDONE_INT_EN_8822C BIT(16) +#define BIT_FS_WWLAN_INT_EN_8822C BIT(15) +#define BIT_FS_SOUND_DONE_INT_EN_8822C BIT(14) +#define BIT_FS_BF1_PRETO_INT_EN_8822C BIT(11) +#define BIT_FS_BF0_PRETO_INT_EN_8822C BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8822C BIT(9) +#define BIT_FS_PRETX_ERRHLD_INT_EN_8822C BIT(8) +#define BIT_FS_LTE_COEX_EN_8822C BIT(6) +#define BIT_FS_WLACTOFF_INT_EN_8822C BIT(5) +#define BIT_FS_WLACTON_INT_EN_8822C BIT(4) +#define BIT_FS_BTCMD_INT_EN_8822C BIT(3) +#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8822C BIT(2) +#define BIT_FS_TRPC_TO_INT_EN_V1_8822C BIT(1) +#define BIT_FS_RPC_O_T_INT_EN_V1_8822C BIT(0) + +/* 2 REG_FE1ISR_8822C */ +#define BIT_FS_SW_PLL_LEAVE_32K_INT_8822C BIT(31) +#define BIT_FS_FS_FWFF_FULL_INT_8822C BIT(30) +#define BIT_FS_BB_STOP_RX_INT_8822C BIT(29) +#define BIT_FS_RXDMA2_DONE_INT_8822C BIT(28) +#define BIT_FS_RXDONE2_INT_8822C BIT(26) +#define BIT_FS_RX_BCN_P4_INT_8822C BIT(25) +#define BIT_FS_RX_BCN_P3_INT_8822C BIT(24) +#define BIT_FS_RX_BCN_P2_INT_8822C BIT(23) +#define BIT_FS_RX_BCN_P1_INT_8822C BIT(22) +#define BIT_FS_RX_BCN_P0_INT_8822C BIT(21) +#define BIT_FS_RX_UMD0_INT_8822C BIT(20) +#define BIT_FS_RX_UMD1_INT_8822C BIT(19) +#define BIT_FS_RX_BMD0_INT_8822C BIT(18) +#define BIT_FS_RX_BMD1_INT_8822C BIT(17) +#define BIT_FS_RXDONE_INT_8822C BIT(16) +#define BIT_FS_WWLAN_INT_8822C BIT(15) +#define BIT_FS_SOUND_DONE_INT_8822C BIT(14) +#define BIT_FS_BF1_PRETO_INT_8822C BIT(11) +#define BIT_FS_BF0_PRETO_INT_8822C BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT_8822C BIT(9) +#define BIT_FS_PRETX_ERRHLD_INT_8822C BIT(8) +#define BIT_FS_LTE_COEX_INT_8822C BIT(6) +#define BIT_FS_WLACTOFF_INT_8822C BIT(5) +#define BIT_FS_WLACTON_INT_8822C BIT(4) +#define BIT_FS_BCN_RX_INT_INT_8822C BIT(3) +#define BIT_FS_MAILBOX_TO_I2C_INT_8822C BIT(2) +#define BIT_FS_TRPC_TO_INT_8822C BIT(1) +#define BIT_FS_RPC_O_T_INT_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_CPWM_8822C */ +#define BIT_CPWM_TOGGLING_8822C BIT(31) + +#define BIT_SHIFT_CPWM_MOD_8822C 24 +#define BIT_MASK_CPWM_MOD_8822C 0x7f +#define BIT_CPWM_MOD_8822C(x) \ + (((x) & BIT_MASK_CPWM_MOD_8822C) << BIT_SHIFT_CPWM_MOD_8822C) +#define BITS_CPWM_MOD_8822C \ + (BIT_MASK_CPWM_MOD_8822C << BIT_SHIFT_CPWM_MOD_8822C) +#define BIT_CLEAR_CPWM_MOD_8822C(x) ((x) & (~BITS_CPWM_MOD_8822C)) +#define BIT_GET_CPWM_MOD_8822C(x) \ + (((x) >> BIT_SHIFT_CPWM_MOD_8822C) & BIT_MASK_CPWM_MOD_8822C) +#define BIT_SET_CPWM_MOD_8822C(x, v) \ + (BIT_CLEAR_CPWM_MOD_8822C(x) | BIT_CPWM_MOD_8822C(v)) + +/* 2 REG_FWIMR_8822C */ +#define BIT_FS_TXBCNOK_MB7_INT_EN_8822C BIT(31) +#define BIT_FS_TXBCNOK_MB6_INT_EN_8822C BIT(30) +#define BIT_FS_TXBCNOK_MB5_INT_EN_8822C BIT(29) +#define BIT_FS_TXBCNOK_MB4_INT_EN_8822C BIT(28) +#define BIT_FS_TXBCNOK_MB3_INT_EN_8822C BIT(27) +#define BIT_FS_TXBCNOK_MB2_INT_EN_8822C BIT(26) +#define BIT_FS_TXBCNOK_MB1_INT_EN_8822C BIT(25) +#define BIT_FS_TXBCNOK_MB0_INT_EN_8822C BIT(24) +#define BIT_FS_TXBCNERR_MB7_INT_EN_8822C BIT(23) +#define BIT_FS_TXBCNERR_MB6_INT_EN_8822C BIT(22) +#define BIT_FS_TXBCNERR_MB5_INT_EN_8822C BIT(21) +#define BIT_FS_TXBCNERR_MB4_INT_EN_8822C BIT(20) +#define BIT_FS_TXBCNERR_MB3_INT_EN_8822C BIT(19) +#define BIT_FS_TXBCNERR_MB2_INT_EN_8822C BIT(18) +#define BIT_FS_TXBCNERR_MB1_INT_EN_8822C BIT(17) +#define BIT_FS_TXBCNERR_MB0_INT_EN_8822C BIT(16) +#define BIT_CPU_MGQ_TXDONE_INT_EN_8822C BIT(15) +#define BIT_SIFS_OVERSPEC_INT_EN_8822C BIT(14) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8822C BIT(13) +#define BIT_FS_MGNTQFF_TO_INT_EN_8822C BIT(12) +#define BIT_FS_CPUMGQ_ERR_INT_EN_8822C BIT(11) +#define BIT_FS_DDMA0_LP_INT_EN_8822C BIT(9) +#define BIT_FS_DDMA0_HP_INT_EN_8822C BIT(8) +#define BIT_FS_TRXRPT_INT_EN_8822C BIT(7) +#define BIT_FS_C2H_W_READY_INT_EN_8822C BIT(6) +#define BIT_FS_HRCV_INT_EN_8822C BIT(5) +#define BIT_FS_H2CCMD_INT_EN_8822C BIT(4) +#define BIT_FS_TXPKTIN_INT_EN_8822C BIT(3) +#define BIT_FS_ERRORHDL_INT_EN_8822C BIT(2) +#define BIT_FS_TXCCX_INT_EN_8822C BIT(1) +#define BIT_FS_TXCLOSE_INT_EN_8822C BIT(0) + +/* 2 REG_FWISR_8822C */ +#define BIT_FS_TXBCNOK_MB7_INT_8822C BIT(31) +#define BIT_FS_TXBCNOK_MB6_INT_8822C BIT(30) +#define BIT_FS_TXBCNOK_MB5_INT_8822C BIT(29) +#define BIT_FS_TXBCNOK_MB4_INT_8822C BIT(28) +#define BIT_FS_TXBCNOK_MB3_INT_8822C BIT(27) +#define BIT_FS_TXBCNOK_MB2_INT_8822C BIT(26) +#define BIT_FS_TXBCNOK_MB1_INT_8822C BIT(25) +#define BIT_FS_TXBCNOK_MB0_INT_8822C BIT(24) +#define BIT_FS_TXBCNERR_MB7_INT_8822C BIT(23) +#define BIT_FS_TXBCNERR_MB6_INT_8822C BIT(22) +#define BIT_FS_TXBCNERR_MB5_INT_8822C BIT(21) +#define BIT_FS_TXBCNERR_MB4_INT_8822C BIT(20) +#define BIT_FS_TXBCNERR_MB3_INT_8822C BIT(19) +#define BIT_FS_TXBCNERR_MB2_INT_8822C BIT(18) +#define BIT_FS_TXBCNERR_MB1_INT_8822C BIT(17) +#define BIT_FS_TXBCNERR_MB0_INT_8822C BIT(16) +#define BIT_CPU_MGQ_TXDONE_INT_8822C BIT(15) +#define BIT_SIFS_OVERSPEC_INT_8822C BIT(14) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8822C BIT(13) +#define BIT_FS_MGNTQFF_TO_INT_8822C BIT(12) +#define BIT_FS_CPUMGQ_ERR_INT_8822C BIT(11) +#define BIT_FS_DDMA0_LP_INT_8822C BIT(9) +#define BIT_FS_DDMA0_HP_INT_8822C BIT(8) +#define BIT_FS_TRXRPT_INT_8822C BIT(7) +#define BIT_FS_C2H_W_READY_INT_8822C BIT(6) +#define BIT_FS_HRCV_INT_8822C BIT(5) +#define BIT_FS_H2CCMD_INT_8822C BIT(4) +#define BIT_FS_TXPKTIN_INT_8822C BIT(3) +#define BIT_FS_ERRORHDL_INT_8822C BIT(2) +#define BIT_FS_TXCCX_INT_8822C BIT(1) +#define BIT_FS_TXCLOSE_INT_8822C BIT(0) + +/* 2 REG_FTIMR_8822C */ +#define BIT_PS_TIMER_C_EARLY_INT_EN_8822C BIT(23) +#define BIT_PS_TIMER_B_EARLY_INT_EN_8822C BIT(22) +#define BIT_PS_TIMER_A_EARLY_INT_EN_8822C BIT(21) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8822C BIT(20) +#define BIT_PS_TIMER_C_INT_EN_8822C BIT(19) +#define BIT_PS_TIMER_B_INT_EN_8822C BIT(18) +#define BIT_PS_TIMER_A_INT_EN_8822C BIT(17) +#define BIT_CPUMGQ_TX_TIMER_INT_EN_8822C BIT(16) +#define BIT_FS_PS_TIMEOUT2_EN_8822C BIT(15) +#define BIT_FS_PS_TIMEOUT1_EN_8822C BIT(14) +#define BIT_FS_PS_TIMEOUT0_EN_8822C BIT(13) +#define BIT_FS_GTINT8_EN_8822C BIT(8) +#define BIT_FS_GTINT7_EN_8822C BIT(7) +#define BIT_FS_GTINT6_EN_8822C BIT(6) +#define BIT_FS_GTINT5_EN_8822C BIT(5) +#define BIT_FS_GTINT4_EN_8822C BIT(4) +#define BIT_FS_GTINT3_EN_8822C BIT(3) +#define BIT_FS_GTINT2_EN_8822C BIT(2) +#define BIT_FS_GTINT1_EN_8822C BIT(1) +#define BIT_FS_GTINT0_EN_8822C BIT(0) + +/* 2 REG_FTISR_8822C */ +#define BIT_PS_TIMER_C_EARLY__INT_8822C BIT(23) +#define BIT_PS_TIMER_B_EARLY__INT_8822C BIT(22) +#define BIT_PS_TIMER_A_EARLY__INT_8822C BIT(21) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8822C BIT(20) +#define BIT_PS_TIMER_C_INT_8822C BIT(19) +#define BIT_PS_TIMER_B_INT_8822C BIT(18) +#define BIT_PS_TIMER_A_INT_8822C BIT(17) +#define BIT_CPUMGQ_TX_TIMER_INT_8822C BIT(16) +#define BIT_FS_PS_TIMEOUT2_INT_8822C BIT(15) +#define BIT_FS_PS_TIMEOUT1_INT_8822C BIT(14) +#define BIT_FS_PS_TIMEOUT0_INT_8822C BIT(13) +#define BIT_FS_GTINT8_INT_8822C BIT(8) +#define BIT_FS_GTINT7_INT_8822C BIT(7) +#define BIT_FS_GTINT6_INT_8822C BIT(6) +#define BIT_FS_GTINT5_INT_8822C BIT(5) +#define BIT_FS_GTINT4_INT_8822C BIT(4) +#define BIT_FS_GTINT3_INT_8822C BIT(3) +#define BIT_FS_GTINT2_INT_8822C BIT(2) +#define BIT_FS_GTINT1_INT_8822C BIT(1) +#define BIT_FS_GTINT0_INT_8822C BIT(0) + +/* 2 REG_PKTBUF_DBG_CTRL_8822C */ + +#define BIT_SHIFT_PKTBUF_WRITE_EN_8822C 24 +#define BIT_MASK_PKTBUF_WRITE_EN_8822C 0xff +#define BIT_PKTBUF_WRITE_EN_8822C(x) \ + (((x) & BIT_MASK_PKTBUF_WRITE_EN_8822C) \ + << BIT_SHIFT_PKTBUF_WRITE_EN_8822C) +#define BITS_PKTBUF_WRITE_EN_8822C \ + (BIT_MASK_PKTBUF_WRITE_EN_8822C << BIT_SHIFT_PKTBUF_WRITE_EN_8822C) +#define BIT_CLEAR_PKTBUF_WRITE_EN_8822C(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8822C)) +#define BIT_GET_PKTBUF_WRITE_EN_8822C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822C) & \ + BIT_MASK_PKTBUF_WRITE_EN_8822C) +#define BIT_SET_PKTBUF_WRITE_EN_8822C(x, v) \ + (BIT_CLEAR_PKTBUF_WRITE_EN_8822C(x) | BIT_PKTBUF_WRITE_EN_8822C(v)) + +#define BIT_TXRPTBUF_DBG_8822C BIT(23) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_TXPKTBUF_DBG_V2_8822C BIT(20) +#define BIT_RXPKTBUF_DBG_8822C BIT(16) + +#define BIT_SHIFT_PKTBUF_DBG_ADDR_8822C 0 +#define BIT_MASK_PKTBUF_DBG_ADDR_8822C 0x1fff +#define BIT_PKTBUF_DBG_ADDR_8822C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822C) \ + << BIT_SHIFT_PKTBUF_DBG_ADDR_8822C) +#define BITS_PKTBUF_DBG_ADDR_8822C \ + (BIT_MASK_PKTBUF_DBG_ADDR_8822C << BIT_SHIFT_PKTBUF_DBG_ADDR_8822C) +#define BIT_CLEAR_PKTBUF_DBG_ADDR_8822C(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8822C)) +#define BIT_GET_PKTBUF_DBG_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822C) & \ + BIT_MASK_PKTBUF_DBG_ADDR_8822C) +#define BIT_SET_PKTBUF_DBG_ADDR_8822C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_ADDR_8822C(x) | BIT_PKTBUF_DBG_ADDR_8822C(v)) + +/* 2 REG_PKTBUF_DBG_DATA_L_8822C */ + +#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C 0 +#define BIT_MASK_PKTBUF_DBG_DATA_L_8822C 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_L_8822C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822C) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C) +#define BITS_PKTBUF_DBG_DATA_L_8822C \ + (BIT_MASK_PKTBUF_DBG_DATA_L_8822C << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C) +#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8822C(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_L_8822C)) +#define BIT_GET_PKTBUF_DBG_DATA_L_8822C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C) & \ + BIT_MASK_PKTBUF_DBG_DATA_L_8822C) +#define BIT_SET_PKTBUF_DBG_DATA_L_8822C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_L_8822C(x) | BIT_PKTBUF_DBG_DATA_L_8822C(v)) + +/* 2 REG_PKTBUF_DBG_DATA_H_8822C */ + +#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C 0 +#define BIT_MASK_PKTBUF_DBG_DATA_H_8822C 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_H_8822C(x) \ + (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822C) \ + << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C) +#define BITS_PKTBUF_DBG_DATA_H_8822C \ + (BIT_MASK_PKTBUF_DBG_DATA_H_8822C << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C) +#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8822C(x) \ + ((x) & (~BITS_PKTBUF_DBG_DATA_H_8822C)) +#define BIT_GET_PKTBUF_DBG_DATA_H_8822C(x) \ + (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C) & \ + BIT_MASK_PKTBUF_DBG_DATA_H_8822C) +#define BIT_SET_PKTBUF_DBG_DATA_H_8822C(x, v) \ + (BIT_CLEAR_PKTBUF_DBG_DATA_H_8822C(x) | BIT_PKTBUF_DBG_DATA_H_8822C(v)) + +/* 2 REG_CPWM2_8822C */ + +#define BIT_SHIFT_L0S_TO_RCVY_NUM_8822C 16 +#define BIT_MASK_L0S_TO_RCVY_NUM_8822C 0xff +#define BIT_L0S_TO_RCVY_NUM_8822C(x) \ + (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822C) \ + << BIT_SHIFT_L0S_TO_RCVY_NUM_8822C) +#define BITS_L0S_TO_RCVY_NUM_8822C \ + (BIT_MASK_L0S_TO_RCVY_NUM_8822C << BIT_SHIFT_L0S_TO_RCVY_NUM_8822C) +#define BIT_CLEAR_L0S_TO_RCVY_NUM_8822C(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8822C)) +#define BIT_GET_L0S_TO_RCVY_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822C) & \ + BIT_MASK_L0S_TO_RCVY_NUM_8822C) +#define BIT_SET_L0S_TO_RCVY_NUM_8822C(x, v) \ + (BIT_CLEAR_L0S_TO_RCVY_NUM_8822C(x) | BIT_L0S_TO_RCVY_NUM_8822C(v)) + +#define BIT_CPWM2_TOGGLING_8822C BIT(15) + +#define BIT_SHIFT_CPWM2_MOD_8822C 0 +#define BIT_MASK_CPWM2_MOD_8822C 0x7fff +#define BIT_CPWM2_MOD_8822C(x) \ + (((x) & BIT_MASK_CPWM2_MOD_8822C) << BIT_SHIFT_CPWM2_MOD_8822C) +#define BITS_CPWM2_MOD_8822C \ + (BIT_MASK_CPWM2_MOD_8822C << BIT_SHIFT_CPWM2_MOD_8822C) +#define BIT_CLEAR_CPWM2_MOD_8822C(x) ((x) & (~BITS_CPWM2_MOD_8822C)) +#define BIT_GET_CPWM2_MOD_8822C(x) \ + (((x) >> BIT_SHIFT_CPWM2_MOD_8822C) & BIT_MASK_CPWM2_MOD_8822C) +#define BIT_SET_CPWM2_MOD_8822C(x, v) \ + (BIT_CLEAR_CPWM2_MOD_8822C(x) | BIT_CPWM2_MOD_8822C(v)) + +/* 2 REG_TC0_CTRL_8822C */ +#define BIT_TC0INT_EN_8822C BIT(26) +#define BIT_TC0MODE_8822C BIT(25) +#define BIT_TC0EN_8822C BIT(24) + +#define BIT_SHIFT_TC0DATA_8822C 0 +#define BIT_MASK_TC0DATA_8822C 0xffffff +#define BIT_TC0DATA_8822C(x) \ + (((x) & BIT_MASK_TC0DATA_8822C) << BIT_SHIFT_TC0DATA_8822C) +#define BITS_TC0DATA_8822C (BIT_MASK_TC0DATA_8822C << BIT_SHIFT_TC0DATA_8822C) +#define BIT_CLEAR_TC0DATA_8822C(x) ((x) & (~BITS_TC0DATA_8822C)) +#define BIT_GET_TC0DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC0DATA_8822C) & BIT_MASK_TC0DATA_8822C) +#define BIT_SET_TC0DATA_8822C(x, v) \ + (BIT_CLEAR_TC0DATA_8822C(x) | BIT_TC0DATA_8822C(v)) + +/* 2 REG_TC1_CTRL_8822C */ +#define BIT_TC1INT_EN_8822C BIT(26) +#define BIT_TC1MODE_8822C BIT(25) +#define BIT_TC1EN_8822C BIT(24) + +#define BIT_SHIFT_TC1DATA_8822C 0 +#define BIT_MASK_TC1DATA_8822C 0xffffff +#define BIT_TC1DATA_8822C(x) \ + (((x) & BIT_MASK_TC1DATA_8822C) << BIT_SHIFT_TC1DATA_8822C) +#define BITS_TC1DATA_8822C (BIT_MASK_TC1DATA_8822C << BIT_SHIFT_TC1DATA_8822C) +#define BIT_CLEAR_TC1DATA_8822C(x) ((x) & (~BITS_TC1DATA_8822C)) +#define BIT_GET_TC1DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC1DATA_8822C) & BIT_MASK_TC1DATA_8822C) +#define BIT_SET_TC1DATA_8822C(x, v) \ + (BIT_CLEAR_TC1DATA_8822C(x) | BIT_TC1DATA_8822C(v)) + +/* 2 REG_TC2_CTRL_8822C */ +#define BIT_TC2INT_EN_8822C BIT(26) +#define BIT_TC2MODE_8822C BIT(25) +#define BIT_TC2EN_8822C BIT(24) + +#define BIT_SHIFT_TC2DATA_8822C 0 +#define BIT_MASK_TC2DATA_8822C 0xffffff +#define BIT_TC2DATA_8822C(x) \ + (((x) & BIT_MASK_TC2DATA_8822C) << BIT_SHIFT_TC2DATA_8822C) +#define BITS_TC2DATA_8822C (BIT_MASK_TC2DATA_8822C << BIT_SHIFT_TC2DATA_8822C) +#define BIT_CLEAR_TC2DATA_8822C(x) ((x) & (~BITS_TC2DATA_8822C)) +#define BIT_GET_TC2DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC2DATA_8822C) & BIT_MASK_TC2DATA_8822C) +#define BIT_SET_TC2DATA_8822C(x, v) \ + (BIT_CLEAR_TC2DATA_8822C(x) | BIT_TC2DATA_8822C(v)) + +/* 2 REG_TC3_CTRL_8822C */ +#define BIT_TC3INT_EN_8822C BIT(26) +#define BIT_TC3MODE_8822C BIT(25) +#define BIT_TC3EN_8822C BIT(24) + +#define BIT_SHIFT_TC3DATA_8822C 0 +#define BIT_MASK_TC3DATA_8822C 0xffffff +#define BIT_TC3DATA_8822C(x) \ + (((x) & BIT_MASK_TC3DATA_8822C) << BIT_SHIFT_TC3DATA_8822C) +#define BITS_TC3DATA_8822C (BIT_MASK_TC3DATA_8822C << BIT_SHIFT_TC3DATA_8822C) +#define BIT_CLEAR_TC3DATA_8822C(x) ((x) & (~BITS_TC3DATA_8822C)) +#define BIT_GET_TC3DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC3DATA_8822C) & BIT_MASK_TC3DATA_8822C) +#define BIT_SET_TC3DATA_8822C(x, v) \ + (BIT_CLEAR_TC3DATA_8822C(x) | BIT_TC3DATA_8822C(v)) + +/* 2 REG_TC4_CTRL_8822C */ +#define BIT_TC4INT_EN_8822C BIT(26) +#define BIT_TC4MODE_8822C BIT(25) +#define BIT_TC4EN_8822C BIT(24) + +#define BIT_SHIFT_TC4DATA_8822C 0 +#define BIT_MASK_TC4DATA_8822C 0xffffff +#define BIT_TC4DATA_8822C(x) \ + (((x) & BIT_MASK_TC4DATA_8822C) << BIT_SHIFT_TC4DATA_8822C) +#define BITS_TC4DATA_8822C (BIT_MASK_TC4DATA_8822C << BIT_SHIFT_TC4DATA_8822C) +#define BIT_CLEAR_TC4DATA_8822C(x) ((x) & (~BITS_TC4DATA_8822C)) +#define BIT_GET_TC4DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC4DATA_8822C) & BIT_MASK_TC4DATA_8822C) +#define BIT_SET_TC4DATA_8822C(x, v) \ + (BIT_CLEAR_TC4DATA_8822C(x) | BIT_TC4DATA_8822C(v)) + +/* 2 REG_TCUNIT_BASE_8822C */ + +#define BIT_SHIFT_TCUNIT_BASE_8822C 0 +#define BIT_MASK_TCUNIT_BASE_8822C 0x3fff +#define BIT_TCUNIT_BASE_8822C(x) \ + (((x) & BIT_MASK_TCUNIT_BASE_8822C) << BIT_SHIFT_TCUNIT_BASE_8822C) +#define BITS_TCUNIT_BASE_8822C \ + (BIT_MASK_TCUNIT_BASE_8822C << BIT_SHIFT_TCUNIT_BASE_8822C) +#define BIT_CLEAR_TCUNIT_BASE_8822C(x) ((x) & (~BITS_TCUNIT_BASE_8822C)) +#define BIT_GET_TCUNIT_BASE_8822C(x) \ + (((x) >> BIT_SHIFT_TCUNIT_BASE_8822C) & BIT_MASK_TCUNIT_BASE_8822C) +#define BIT_SET_TCUNIT_BASE_8822C(x, v) \ + (BIT_CLEAR_TCUNIT_BASE_8822C(x) | BIT_TCUNIT_BASE_8822C(v)) + +/* 2 REG_TC5_CTRL_8822C */ +#define BIT_TC5INT_EN_8822C BIT(26) +#define BIT_TC5MODE_8822C BIT(25) +#define BIT_TC5EN_8822C BIT(24) + +#define BIT_SHIFT_TC5DATA_8822C 0 +#define BIT_MASK_TC5DATA_8822C 0xffffff +#define BIT_TC5DATA_8822C(x) \ + (((x) & BIT_MASK_TC5DATA_8822C) << BIT_SHIFT_TC5DATA_8822C) +#define BITS_TC5DATA_8822C (BIT_MASK_TC5DATA_8822C << BIT_SHIFT_TC5DATA_8822C) +#define BIT_CLEAR_TC5DATA_8822C(x) ((x) & (~BITS_TC5DATA_8822C)) +#define BIT_GET_TC5DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC5DATA_8822C) & BIT_MASK_TC5DATA_8822C) +#define BIT_SET_TC5DATA_8822C(x, v) \ + (BIT_CLEAR_TC5DATA_8822C(x) | BIT_TC5DATA_8822C(v)) + +/* 2 REG_TC6_CTRL_8822C */ +#define BIT_TC6INT_EN_8822C BIT(26) +#define BIT_TC6MODE_8822C BIT(25) +#define BIT_TC6EN_8822C BIT(24) + +#define BIT_SHIFT_TC6DATA_8822C 0 +#define BIT_MASK_TC6DATA_8822C 0xffffff +#define BIT_TC6DATA_8822C(x) \ + (((x) & BIT_MASK_TC6DATA_8822C) << BIT_SHIFT_TC6DATA_8822C) +#define BITS_TC6DATA_8822C (BIT_MASK_TC6DATA_8822C << BIT_SHIFT_TC6DATA_8822C) +#define BIT_CLEAR_TC6DATA_8822C(x) ((x) & (~BITS_TC6DATA_8822C)) +#define BIT_GET_TC6DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC6DATA_8822C) & BIT_MASK_TC6DATA_8822C) +#define BIT_SET_TC6DATA_8822C(x, v) \ + (BIT_CLEAR_TC6DATA_8822C(x) | BIT_TC6DATA_8822C(v)) + +/* 2 REG_MBIST_DRF_FAIL_8822C */ + +#define BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C 26 +#define BIT_MASK_8051_MBIST_DRF_FAIL_8822C 0x3f +#define BIT_8051_MBIST_DRF_FAIL_8822C(x) \ + (((x) & BIT_MASK_8051_MBIST_DRF_FAIL_8822C) \ + << BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C) +#define BITS_8051_MBIST_DRF_FAIL_8822C \ + (BIT_MASK_8051_MBIST_DRF_FAIL_8822C \ + << BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C) +#define BIT_CLEAR_8051_MBIST_DRF_FAIL_8822C(x) \ + ((x) & (~BITS_8051_MBIST_DRF_FAIL_8822C)) +#define BIT_GET_8051_MBIST_DRF_FAIL_8822C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C) & \ + BIT_MASK_8051_MBIST_DRF_FAIL_8822C) +#define BIT_SET_8051_MBIST_DRF_FAIL_8822C(x, v) \ + (BIT_CLEAR_8051_MBIST_DRF_FAIL_8822C(x) | \ + BIT_8051_MBIST_DRF_FAIL_8822C(v)) + +#define BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C 24 +#define BIT_MASK_USB_MBIST_DRF_FAIL_8822C 0x3 +#define BIT_USB_MBIST_DRF_FAIL_8822C(x) \ + (((x) & BIT_MASK_USB_MBIST_DRF_FAIL_8822C) \ + << BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C) +#define BITS_USB_MBIST_DRF_FAIL_8822C \ + (BIT_MASK_USB_MBIST_DRF_FAIL_8822C \ + << BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C) +#define BIT_CLEAR_USB_MBIST_DRF_FAIL_8822C(x) \ + ((x) & (~BITS_USB_MBIST_DRF_FAIL_8822C)) +#define BIT_GET_USB_MBIST_DRF_FAIL_8822C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C) & \ + BIT_MASK_USB_MBIST_DRF_FAIL_8822C) +#define BIT_SET_USB_MBIST_DRF_FAIL_8822C(x, v) \ + (BIT_CLEAR_USB_MBIST_DRF_FAIL_8822C(x) | \ + BIT_USB_MBIST_DRF_FAIL_8822C(v)) + +#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C 18 +#define BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C 0x3f +#define BIT_PCIE_MBIST_DRF_FAIL_8822C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C) \ + << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C) +#define BITS_PCIE_MBIST_DRF_FAIL_8822C \ + (BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C \ + << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C) +#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8822C(x) \ + ((x) & (~BITS_PCIE_MBIST_DRF_FAIL_8822C)) +#define BIT_GET_PCIE_MBIST_DRF_FAIL_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C) & \ + BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C) +#define BIT_SET_PCIE_MBIST_DRF_FAIL_8822C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8822C(x) | \ + BIT_PCIE_MBIST_DRF_FAIL_8822C(v)) + +#define BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C 0 +#define BIT_MASK_MAC_MBIST_DRF_FAIL_8822C 0x3ffff +#define BIT_MAC_MBIST_DRF_FAIL_8822C(x) \ + (((x) & BIT_MASK_MAC_MBIST_DRF_FAIL_8822C) \ + << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C) +#define BITS_MAC_MBIST_DRF_FAIL_8822C \ + (BIT_MASK_MAC_MBIST_DRF_FAIL_8822C \ + << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C) +#define BIT_CLEAR_MAC_MBIST_DRF_FAIL_8822C(x) \ + ((x) & (~BITS_MAC_MBIST_DRF_FAIL_8822C)) +#define BIT_GET_MAC_MBIST_DRF_FAIL_8822C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C) & \ + BIT_MASK_MAC_MBIST_DRF_FAIL_8822C) +#define BIT_SET_MAC_MBIST_DRF_FAIL_8822C(x, v) \ + (BIT_CLEAR_MAC_MBIST_DRF_FAIL_8822C(x) | \ + BIT_MAC_MBIST_DRF_FAIL_8822C(v)) + +/* 2 REG_MBIST_START_PAUSE_8822C */ + +#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C 26 +#define BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C 0x3f +#define BIT_8051_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C) \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C) +#define BITS_8051_MBIST_START_PAUSE_V1_8822C \ + (BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C \ + << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C) +#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8822C(x) \ + ((x) & (~BITS_8051_MBIST_START_PAUSE_V1_8822C)) +#define BIT_GET_8051_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C) & \ + BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C) +#define BIT_SET_8051_MBIST_START_PAUSE_V1_8822C(x, v) \ + (BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8822C(x) | \ + BIT_8051_MBIST_START_PAUSE_V1_8822C(v)) + +#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C 24 +#define BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C 0x3 +#define BIT_USB_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C) \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C) +#define BITS_USB_MBIST_START_PAUSE_V1_8822C \ + (BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C \ + << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C) +#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8822C(x) \ + ((x) & (~BITS_USB_MBIST_START_PAUSE_V1_8822C)) +#define BIT_GET_USB_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C) & \ + BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C) +#define BIT_SET_USB_MBIST_START_PAUSE_V1_8822C(x, v) \ + (BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8822C(x) | \ + BIT_USB_MBIST_START_PAUSE_V1_8822C(v)) + +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C 18 +#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C 0x3f +#define BIT_PCIE_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C) \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C) +#define BITS_PCIE_MBIST_START_PAUSE_V1_8822C \ + (BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C \ + << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C) +#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8822C(x) \ + ((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1_8822C)) +#define BIT_GET_PCIE_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C) & \ + BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C) +#define BIT_SET_PCIE_MBIST_START_PAUSE_V1_8822C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8822C(x) | \ + BIT_PCIE_MBIST_START_PAUSE_V1_8822C(v)) + +#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C 0 +#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C 0x3ffff +#define BIT_MAC_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C) \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C) +#define BITS_MAC_MBIST_START_PAUSE_V1_8822C \ + (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C \ + << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C) +#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8822C(x) \ + ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8822C)) +#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C) & \ + BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C) +#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8822C(x, v) \ + (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8822C(x) | \ + BIT_MAC_MBIST_START_PAUSE_V1_8822C(v)) + +/* 2 REG_MBIST_DONE_8822C */ + +#define BIT_SHIFT_8051_MBIST_DONE_V1_8822C 26 +#define BIT_MASK_8051_MBIST_DONE_V1_8822C 0x3f +#define BIT_8051_MBIST_DONE_V1_8822C(x) \ + (((x) & BIT_MASK_8051_MBIST_DONE_V1_8822C) \ + << BIT_SHIFT_8051_MBIST_DONE_V1_8822C) +#define BITS_8051_MBIST_DONE_V1_8822C \ + (BIT_MASK_8051_MBIST_DONE_V1_8822C \ + << BIT_SHIFT_8051_MBIST_DONE_V1_8822C) +#define BIT_CLEAR_8051_MBIST_DONE_V1_8822C(x) \ + ((x) & (~BITS_8051_MBIST_DONE_V1_8822C)) +#define BIT_GET_8051_MBIST_DONE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_8051_MBIST_DONE_V1_8822C) & \ + BIT_MASK_8051_MBIST_DONE_V1_8822C) +#define BIT_SET_8051_MBIST_DONE_V1_8822C(x, v) \ + (BIT_CLEAR_8051_MBIST_DONE_V1_8822C(x) | \ + BIT_8051_MBIST_DONE_V1_8822C(v)) + +#define BIT_SHIFT_USB_MBIST_DONE_V1_8822C 24 +#define BIT_MASK_USB_MBIST_DONE_V1_8822C 0x3 +#define BIT_USB_MBIST_DONE_V1_8822C(x) \ + (((x) & BIT_MASK_USB_MBIST_DONE_V1_8822C) \ + << BIT_SHIFT_USB_MBIST_DONE_V1_8822C) +#define BITS_USB_MBIST_DONE_V1_8822C \ + (BIT_MASK_USB_MBIST_DONE_V1_8822C << BIT_SHIFT_USB_MBIST_DONE_V1_8822C) +#define BIT_CLEAR_USB_MBIST_DONE_V1_8822C(x) \ + ((x) & (~BITS_USB_MBIST_DONE_V1_8822C)) +#define BIT_GET_USB_MBIST_DONE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_USB_MBIST_DONE_V1_8822C) & \ + BIT_MASK_USB_MBIST_DONE_V1_8822C) +#define BIT_SET_USB_MBIST_DONE_V1_8822C(x, v) \ + (BIT_CLEAR_USB_MBIST_DONE_V1_8822C(x) | BIT_USB_MBIST_DONE_V1_8822C(v)) + +#define BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C 18 +#define BIT_MASK_PCIE_MBIST_DONE_V1_8822C 0x3f +#define BIT_PCIE_MBIST_DONE_V1_8822C(x) \ + (((x) & BIT_MASK_PCIE_MBIST_DONE_V1_8822C) \ + << BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C) +#define BITS_PCIE_MBIST_DONE_V1_8822C \ + (BIT_MASK_PCIE_MBIST_DONE_V1_8822C \ + << BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C) +#define BIT_CLEAR_PCIE_MBIST_DONE_V1_8822C(x) \ + ((x) & (~BITS_PCIE_MBIST_DONE_V1_8822C)) +#define BIT_GET_PCIE_MBIST_DONE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C) & \ + BIT_MASK_PCIE_MBIST_DONE_V1_8822C) +#define BIT_SET_PCIE_MBIST_DONE_V1_8822C(x, v) \ + (BIT_CLEAR_PCIE_MBIST_DONE_V1_8822C(x) | \ + BIT_PCIE_MBIST_DONE_V1_8822C(v)) + +#define BIT_SHIFT_MAC_MBIST_DONE_V1_8822C 0 +#define BIT_MASK_MAC_MBIST_DONE_V1_8822C 0x3ffff +#define BIT_MAC_MBIST_DONE_V1_8822C(x) \ + (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8822C) \ + << BIT_SHIFT_MAC_MBIST_DONE_V1_8822C) +#define BITS_MAC_MBIST_DONE_V1_8822C \ + (BIT_MASK_MAC_MBIST_DONE_V1_8822C << BIT_SHIFT_MAC_MBIST_DONE_V1_8822C) +#define BIT_CLEAR_MAC_MBIST_DONE_V1_8822C(x) \ + ((x) & (~BITS_MAC_MBIST_DONE_V1_8822C)) +#define BIT_GET_MAC_MBIST_DONE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8822C) & \ + BIT_MASK_MAC_MBIST_DONE_V1_8822C) +#define BIT_SET_MAC_MBIST_DONE_V1_8822C(x, v) \ + (BIT_CLEAR_MAC_MBIST_DONE_V1_8822C(x) | BIT_MAC_MBIST_DONE_V1_8822C(v)) + +/* 2 REG_MBIST_READ_BIST_RPT_8822C */ + +#define BIT_SHIFT_MBIST_READ_BIST_RPT_8822C 0 +#define BIT_MASK_MBIST_READ_BIST_RPT_8822C 0xffffffffL +#define BIT_MBIST_READ_BIST_RPT_8822C(x) \ + (((x) & BIT_MASK_MBIST_READ_BIST_RPT_8822C) \ + << BIT_SHIFT_MBIST_READ_BIST_RPT_8822C) +#define BITS_MBIST_READ_BIST_RPT_8822C \ + (BIT_MASK_MBIST_READ_BIST_RPT_8822C \ + << BIT_SHIFT_MBIST_READ_BIST_RPT_8822C) +#define BIT_CLEAR_MBIST_READ_BIST_RPT_8822C(x) \ + ((x) & (~BITS_MBIST_READ_BIST_RPT_8822C)) +#define BIT_GET_MBIST_READ_BIST_RPT_8822C(x) \ + (((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT_8822C) & \ + BIT_MASK_MBIST_READ_BIST_RPT_8822C) +#define BIT_SET_MBIST_READ_BIST_RPT_8822C(x, v) \ + (BIT_CLEAR_MBIST_READ_BIST_RPT_8822C(x) | \ + BIT_MBIST_READ_BIST_RPT_8822C(v)) + +/* 2 REG_AES_DECRPT_DATA_8822C */ + +#define BIT_SHIFT_IPS_CFG_ADDR_8822C 0 +#define BIT_MASK_IPS_CFG_ADDR_8822C 0xff +#define BIT_IPS_CFG_ADDR_8822C(x) \ + (((x) & BIT_MASK_IPS_CFG_ADDR_8822C) << BIT_SHIFT_IPS_CFG_ADDR_8822C) +#define BITS_IPS_CFG_ADDR_8822C \ + (BIT_MASK_IPS_CFG_ADDR_8822C << BIT_SHIFT_IPS_CFG_ADDR_8822C) +#define BIT_CLEAR_IPS_CFG_ADDR_8822C(x) ((x) & (~BITS_IPS_CFG_ADDR_8822C)) +#define BIT_GET_IPS_CFG_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822C) & BIT_MASK_IPS_CFG_ADDR_8822C) +#define BIT_SET_IPS_CFG_ADDR_8822C(x, v) \ + (BIT_CLEAR_IPS_CFG_ADDR_8822C(x) | BIT_IPS_CFG_ADDR_8822C(v)) + +/* 2 REG_AES_DECRPT_CFG_8822C */ + +#define BIT_SHIFT_IPS_CFG_DATA_8822C 0 +#define BIT_MASK_IPS_CFG_DATA_8822C 0xffffffffL +#define BIT_IPS_CFG_DATA_8822C(x) \ + (((x) & BIT_MASK_IPS_CFG_DATA_8822C) << BIT_SHIFT_IPS_CFG_DATA_8822C) +#define BITS_IPS_CFG_DATA_8822C \ + (BIT_MASK_IPS_CFG_DATA_8822C << BIT_SHIFT_IPS_CFG_DATA_8822C) +#define BIT_CLEAR_IPS_CFG_DATA_8822C(x) ((x) & (~BITS_IPS_CFG_DATA_8822C)) +#define BIT_GET_IPS_CFG_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_IPS_CFG_DATA_8822C) & BIT_MASK_IPS_CFG_DATA_8822C) +#define BIT_SET_IPS_CFG_DATA_8822C(x, v) \ + (BIT_CLEAR_IPS_CFG_DATA_8822C(x) | BIT_IPS_CFG_DATA_8822C(v)) + +/* 2 REG_HIOE_CTRL_8822C */ +#define BIT_HIOE_CFG_FILE_LOC_SEL_8822C BIT(31) +#define BIT_HIOE_WRITE_REQ_8822C BIT(30) +#define BIT_HIOE_READ_REQ_8822C BIT(29) +#define BIT_INST_FORMAT_ERR_8822C BIT(25) +#define BIT_OP_TIMEOUT_ERR_8822C BIT(24) + +#define BIT_SHIFT_HIOE_OP_TIMEOUT_8822C 16 +#define BIT_MASK_HIOE_OP_TIMEOUT_8822C 0xff +#define BIT_HIOE_OP_TIMEOUT_8822C(x) \ + (((x) & BIT_MASK_HIOE_OP_TIMEOUT_8822C) \ + << BIT_SHIFT_HIOE_OP_TIMEOUT_8822C) +#define BITS_HIOE_OP_TIMEOUT_8822C \ + (BIT_MASK_HIOE_OP_TIMEOUT_8822C << BIT_SHIFT_HIOE_OP_TIMEOUT_8822C) +#define BIT_CLEAR_HIOE_OP_TIMEOUT_8822C(x) ((x) & (~BITS_HIOE_OP_TIMEOUT_8822C)) +#define BIT_GET_HIOE_OP_TIMEOUT_8822C(x) \ + (((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT_8822C) & \ + BIT_MASK_HIOE_OP_TIMEOUT_8822C) +#define BIT_SET_HIOE_OP_TIMEOUT_8822C(x, v) \ + (BIT_CLEAR_HIOE_OP_TIMEOUT_8822C(x) | BIT_HIOE_OP_TIMEOUT_8822C(v)) + +#define BIT_SHIFT_BITDATA_CHECKSUM_8822C 0 +#define BIT_MASK_BITDATA_CHECKSUM_8822C 0xffff +#define BIT_BITDATA_CHECKSUM_8822C(x) \ + (((x) & BIT_MASK_BITDATA_CHECKSUM_8822C) \ + << BIT_SHIFT_BITDATA_CHECKSUM_8822C) +#define BITS_BITDATA_CHECKSUM_8822C \ + (BIT_MASK_BITDATA_CHECKSUM_8822C << BIT_SHIFT_BITDATA_CHECKSUM_8822C) +#define BIT_CLEAR_BITDATA_CHECKSUM_8822C(x) \ + ((x) & (~BITS_BITDATA_CHECKSUM_8822C)) +#define BIT_GET_BITDATA_CHECKSUM_8822C(x) \ + (((x) >> BIT_SHIFT_BITDATA_CHECKSUM_8822C) & \ + BIT_MASK_BITDATA_CHECKSUM_8822C) +#define BIT_SET_BITDATA_CHECKSUM_8822C(x, v) \ + (BIT_CLEAR_BITDATA_CHECKSUM_8822C(x) | BIT_BITDATA_CHECKSUM_8822C(v)) + +/* 2 REG_HIOE_CFG_FILE_8822C */ + +#define BIT_SHIFT_TXBF_END_ADDR_8822C 16 +#define BIT_MASK_TXBF_END_ADDR_8822C 0xffff +#define BIT_TXBF_END_ADDR_8822C(x) \ + (((x) & BIT_MASK_TXBF_END_ADDR_8822C) << BIT_SHIFT_TXBF_END_ADDR_8822C) +#define BITS_TXBF_END_ADDR_8822C \ + (BIT_MASK_TXBF_END_ADDR_8822C << BIT_SHIFT_TXBF_END_ADDR_8822C) +#define BIT_CLEAR_TXBF_END_ADDR_8822C(x) ((x) & (~BITS_TXBF_END_ADDR_8822C)) +#define BIT_GET_TXBF_END_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_TXBF_END_ADDR_8822C) & BIT_MASK_TXBF_END_ADDR_8822C) +#define BIT_SET_TXBF_END_ADDR_8822C(x, v) \ + (BIT_CLEAR_TXBF_END_ADDR_8822C(x) | BIT_TXBF_END_ADDR_8822C(v)) + +#define BIT_SHIFT_TXBF_STR_ADDR_8822C 0 +#define BIT_MASK_TXBF_STR_ADDR_8822C 0xffff +#define BIT_TXBF_STR_ADDR_8822C(x) \ + (((x) & BIT_MASK_TXBF_STR_ADDR_8822C) << BIT_SHIFT_TXBF_STR_ADDR_8822C) +#define BITS_TXBF_STR_ADDR_8822C \ + (BIT_MASK_TXBF_STR_ADDR_8822C << BIT_SHIFT_TXBF_STR_ADDR_8822C) +#define BIT_CLEAR_TXBF_STR_ADDR_8822C(x) ((x) & (~BITS_TXBF_STR_ADDR_8822C)) +#define BIT_GET_TXBF_STR_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_TXBF_STR_ADDR_8822C) & BIT_MASK_TXBF_STR_ADDR_8822C) +#define BIT_SET_TXBF_STR_ADDR_8822C(x, v) \ + (BIT_CLEAR_TXBF_STR_ADDR_8822C(x) | BIT_TXBF_STR_ADDR_8822C(v)) + +/* 2 REG_TMETER_8822C */ +#define BIT_TEMP_VALID_8822C BIT(31) + +#define BIT_SHIFT_TEMP_VALUE_8822C 24 +#define BIT_MASK_TEMP_VALUE_8822C 0x3f +#define BIT_TEMP_VALUE_8822C(x) \ + (((x) & BIT_MASK_TEMP_VALUE_8822C) << BIT_SHIFT_TEMP_VALUE_8822C) +#define BITS_TEMP_VALUE_8822C \ + (BIT_MASK_TEMP_VALUE_8822C << BIT_SHIFT_TEMP_VALUE_8822C) +#define BIT_CLEAR_TEMP_VALUE_8822C(x) ((x) & (~BITS_TEMP_VALUE_8822C)) +#define BIT_GET_TEMP_VALUE_8822C(x) \ + (((x) >> BIT_SHIFT_TEMP_VALUE_8822C) & BIT_MASK_TEMP_VALUE_8822C) +#define BIT_SET_TEMP_VALUE_8822C(x, v) \ + (BIT_CLEAR_TEMP_VALUE_8822C(x) | BIT_TEMP_VALUE_8822C(v)) + +#define BIT_SHIFT_REG_TMETER_TIMER_8822C 8 +#define BIT_MASK_REG_TMETER_TIMER_8822C 0xfff +#define BIT_REG_TMETER_TIMER_8822C(x) \ + (((x) & BIT_MASK_REG_TMETER_TIMER_8822C) \ + << BIT_SHIFT_REG_TMETER_TIMER_8822C) +#define BITS_REG_TMETER_TIMER_8822C \ + (BIT_MASK_REG_TMETER_TIMER_8822C << BIT_SHIFT_REG_TMETER_TIMER_8822C) +#define BIT_CLEAR_REG_TMETER_TIMER_8822C(x) \ + ((x) & (~BITS_REG_TMETER_TIMER_8822C)) +#define BIT_GET_REG_TMETER_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822C) & \ + BIT_MASK_REG_TMETER_TIMER_8822C) +#define BIT_SET_REG_TMETER_TIMER_8822C(x, v) \ + (BIT_CLEAR_REG_TMETER_TIMER_8822C(x) | BIT_REG_TMETER_TIMER_8822C(v)) + +#define BIT_SHIFT_REG_TEMP_DELTA_8822C 2 +#define BIT_MASK_REG_TEMP_DELTA_8822C 0x3f +#define BIT_REG_TEMP_DELTA_8822C(x) \ + (((x) & BIT_MASK_REG_TEMP_DELTA_8822C) \ + << BIT_SHIFT_REG_TEMP_DELTA_8822C) +#define BITS_REG_TEMP_DELTA_8822C \ + (BIT_MASK_REG_TEMP_DELTA_8822C << BIT_SHIFT_REG_TEMP_DELTA_8822C) +#define BIT_CLEAR_REG_TEMP_DELTA_8822C(x) ((x) & (~BITS_REG_TEMP_DELTA_8822C)) +#define BIT_GET_REG_TEMP_DELTA_8822C(x) \ + (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822C) & \ + BIT_MASK_REG_TEMP_DELTA_8822C) +#define BIT_SET_REG_TEMP_DELTA_8822C(x, v) \ + (BIT_CLEAR_REG_TEMP_DELTA_8822C(x) | BIT_REG_TEMP_DELTA_8822C(v)) + +#define BIT_REG_TMETER_EN_8822C BIT(0) + +/* 2 REG_OSC_32K_CTRL_8822C */ + +#define BIT_SHIFT_OSC_32K_CLKGEN_0_8822C 16 +#define BIT_MASK_OSC_32K_CLKGEN_0_8822C 0xffff +#define BIT_OSC_32K_CLKGEN_0_8822C(x) \ + (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822C) \ + << BIT_SHIFT_OSC_32K_CLKGEN_0_8822C) +#define BITS_OSC_32K_CLKGEN_0_8822C \ + (BIT_MASK_OSC_32K_CLKGEN_0_8822C << BIT_SHIFT_OSC_32K_CLKGEN_0_8822C) +#define BIT_CLEAR_OSC_32K_CLKGEN_0_8822C(x) \ + ((x) & (~BITS_OSC_32K_CLKGEN_0_8822C)) +#define BIT_GET_OSC_32K_CLKGEN_0_8822C(x) \ + (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822C) & \ + BIT_MASK_OSC_32K_CLKGEN_0_8822C) +#define BIT_SET_OSC_32K_CLKGEN_0_8822C(x, v) \ + (BIT_CLEAR_OSC_32K_CLKGEN_0_8822C(x) | BIT_OSC_32K_CLKGEN_0_8822C(v)) + +#define BIT_SHIFT_OSC_32K_RES_COMP_8822C 4 +#define BIT_MASK_OSC_32K_RES_COMP_8822C 0x3 +#define BIT_OSC_32K_RES_COMP_8822C(x) \ + (((x) & BIT_MASK_OSC_32K_RES_COMP_8822C) \ + << BIT_SHIFT_OSC_32K_RES_COMP_8822C) +#define BITS_OSC_32K_RES_COMP_8822C \ + (BIT_MASK_OSC_32K_RES_COMP_8822C << BIT_SHIFT_OSC_32K_RES_COMP_8822C) +#define BIT_CLEAR_OSC_32K_RES_COMP_8822C(x) \ + ((x) & (~BITS_OSC_32K_RES_COMP_8822C)) +#define BIT_GET_OSC_32K_RES_COMP_8822C(x) \ + (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822C) & \ + BIT_MASK_OSC_32K_RES_COMP_8822C) +#define BIT_SET_OSC_32K_RES_COMP_8822C(x, v) \ + (BIT_CLEAR_OSC_32K_RES_COMP_8822C(x) | BIT_OSC_32K_RES_COMP_8822C(v)) + +#define BIT_OSC_32K_OUT_SEL_8822C BIT(3) +#define BIT_ISO_WL_2_OSC_32K_8822C BIT(1) +#define BIT_POW_CKGEN_8822C BIT(0) + +/* 2 REG_32K_CAL_REG1_8822C */ +#define BIT_CAL_32K_REG_WR_8822C BIT(31) +#define BIT_CAL_32K_DBG_SEL_8822C BIT(22) + +#define BIT_SHIFT_CAL_32K_REG_ADDR_8822C 16 +#define BIT_MASK_CAL_32K_REG_ADDR_8822C 0x3f +#define BIT_CAL_32K_REG_ADDR_8822C(x) \ + (((x) & BIT_MASK_CAL_32K_REG_ADDR_8822C) \ + << BIT_SHIFT_CAL_32K_REG_ADDR_8822C) +#define BITS_CAL_32K_REG_ADDR_8822C \ + (BIT_MASK_CAL_32K_REG_ADDR_8822C << BIT_SHIFT_CAL_32K_REG_ADDR_8822C) +#define BIT_CLEAR_CAL_32K_REG_ADDR_8822C(x) \ + ((x) & (~BITS_CAL_32K_REG_ADDR_8822C)) +#define BIT_GET_CAL_32K_REG_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822C) & \ + BIT_MASK_CAL_32K_REG_ADDR_8822C) +#define BIT_SET_CAL_32K_REG_ADDR_8822C(x, v) \ + (BIT_CLEAR_CAL_32K_REG_ADDR_8822C(x) | BIT_CAL_32K_REG_ADDR_8822C(v)) + +#define BIT_SHIFT_CAL_32K_REG_DATA_8822C 0 +#define BIT_MASK_CAL_32K_REG_DATA_8822C 0xffff +#define BIT_CAL_32K_REG_DATA_8822C(x) \ + (((x) & BIT_MASK_CAL_32K_REG_DATA_8822C) \ + << BIT_SHIFT_CAL_32K_REG_DATA_8822C) +#define BITS_CAL_32K_REG_DATA_8822C \ + (BIT_MASK_CAL_32K_REG_DATA_8822C << BIT_SHIFT_CAL_32K_REG_DATA_8822C) +#define BIT_CLEAR_CAL_32K_REG_DATA_8822C(x) \ + ((x) & (~BITS_CAL_32K_REG_DATA_8822C)) +#define BIT_GET_CAL_32K_REG_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822C) & \ + BIT_MASK_CAL_32K_REG_DATA_8822C) +#define BIT_SET_CAL_32K_REG_DATA_8822C(x, v) \ + (BIT_CLEAR_CAL_32K_REG_DATA_8822C(x) | BIT_CAL_32K_REG_DATA_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_C2HEVT_8822C */ + +#define BIT_SHIFT_C2HEVT_MSG_V1_8822C 0 +#define BIT_MASK_C2HEVT_MSG_V1_8822C 0xffffffffL +#define BIT_C2HEVT_MSG_V1_8822C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_V1_8822C) << BIT_SHIFT_C2HEVT_MSG_V1_8822C) +#define BITS_C2HEVT_MSG_V1_8822C \ + (BIT_MASK_C2HEVT_MSG_V1_8822C << BIT_SHIFT_C2HEVT_MSG_V1_8822C) +#define BIT_CLEAR_C2HEVT_MSG_V1_8822C(x) ((x) & (~BITS_C2HEVT_MSG_V1_8822C)) +#define BIT_GET_C2HEVT_MSG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8822C) & BIT_MASK_C2HEVT_MSG_V1_8822C) +#define BIT_SET_C2HEVT_MSG_V1_8822C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_V1_8822C(x) | BIT_C2HEVT_MSG_V1_8822C(v)) + +/* 2 REG_C2HEVT_1_8822C */ + +#define BIT_SHIFT_C2HEVT_MSG_1_8822C 0 +#define BIT_MASK_C2HEVT_MSG_1_8822C 0xffffffffL +#define BIT_C2HEVT_MSG_1_8822C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_1_8822C) << BIT_SHIFT_C2HEVT_MSG_1_8822C) +#define BITS_C2HEVT_MSG_1_8822C \ + (BIT_MASK_C2HEVT_MSG_1_8822C << BIT_SHIFT_C2HEVT_MSG_1_8822C) +#define BIT_CLEAR_C2HEVT_MSG_1_8822C(x) ((x) & (~BITS_C2HEVT_MSG_1_8822C)) +#define BIT_GET_C2HEVT_MSG_1_8822C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8822C) & BIT_MASK_C2HEVT_MSG_1_8822C) +#define BIT_SET_C2HEVT_MSG_1_8822C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_1_8822C(x) | BIT_C2HEVT_MSG_1_8822C(v)) + +/* 2 REG_C2HEVT_2_8822C */ + +#define BIT_SHIFT_C2HEVT_MSG_2_8822C 0 +#define BIT_MASK_C2HEVT_MSG_2_8822C 0xffffffffL +#define BIT_C2HEVT_MSG_2_8822C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_2_8822C) << BIT_SHIFT_C2HEVT_MSG_2_8822C) +#define BITS_C2HEVT_MSG_2_8822C \ + (BIT_MASK_C2HEVT_MSG_2_8822C << BIT_SHIFT_C2HEVT_MSG_2_8822C) +#define BIT_CLEAR_C2HEVT_MSG_2_8822C(x) ((x) & (~BITS_C2HEVT_MSG_2_8822C)) +#define BIT_GET_C2HEVT_MSG_2_8822C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8822C) & BIT_MASK_C2HEVT_MSG_2_8822C) +#define BIT_SET_C2HEVT_MSG_2_8822C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_2_8822C(x) | BIT_C2HEVT_MSG_2_8822C(v)) + +/* 2 REG_C2HEVT_3_8822C */ + +#define BIT_SHIFT_C2HEVT_MSG_3_8822C 0 +#define BIT_MASK_C2HEVT_MSG_3_8822C 0xffffffffL +#define BIT_C2HEVT_MSG_3_8822C(x) \ + (((x) & BIT_MASK_C2HEVT_MSG_3_8822C) << BIT_SHIFT_C2HEVT_MSG_3_8822C) +#define BITS_C2HEVT_MSG_3_8822C \ + (BIT_MASK_C2HEVT_MSG_3_8822C << BIT_SHIFT_C2HEVT_MSG_3_8822C) +#define BIT_CLEAR_C2HEVT_MSG_3_8822C(x) ((x) & (~BITS_C2HEVT_MSG_3_8822C)) +#define BIT_GET_C2HEVT_MSG_3_8822C(x) \ + (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8822C) & BIT_MASK_C2HEVT_MSG_3_8822C) +#define BIT_SET_C2HEVT_MSG_3_8822C(x, v) \ + (BIT_CLEAR_C2HEVT_MSG_3_8822C(x) | BIT_C2HEVT_MSG_3_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SW_DEFINED_PAGE1_8822C */ + +#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C 0 +#define BIT_MASK_SW_DEFINED_PAGE1_V1_8822C 0xffffffffL +#define BIT_SW_DEFINED_PAGE1_V1_8822C(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8822C) \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C) +#define BITS_SW_DEFINED_PAGE1_V1_8822C \ + (BIT_MASK_SW_DEFINED_PAGE1_V1_8822C \ + << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C) +#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8822C(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE1_V1_8822C)) +#define BIT_GET_SW_DEFINED_PAGE1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C) & \ + BIT_MASK_SW_DEFINED_PAGE1_V1_8822C) +#define BIT_SET_SW_DEFINED_PAGE1_V1_8822C(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE1_V1_8822C(x) | \ + BIT_SW_DEFINED_PAGE1_V1_8822C(v)) + +/* 2 REG_SW_DEFINED_PAGE2_8822C */ + +#define BIT_SHIFT_SW_DEFINED_PAGE2_8822C 0 +#define BIT_MASK_SW_DEFINED_PAGE2_8822C 0xffffffffL +#define BIT_SW_DEFINED_PAGE2_8822C(x) \ + (((x) & BIT_MASK_SW_DEFINED_PAGE2_8822C) \ + << BIT_SHIFT_SW_DEFINED_PAGE2_8822C) +#define BITS_SW_DEFINED_PAGE2_8822C \ + (BIT_MASK_SW_DEFINED_PAGE2_8822C << BIT_SHIFT_SW_DEFINED_PAGE2_8822C) +#define BIT_CLEAR_SW_DEFINED_PAGE2_8822C(x) \ + ((x) & (~BITS_SW_DEFINED_PAGE2_8822C)) +#define BIT_GET_SW_DEFINED_PAGE2_8822C(x) \ + (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8822C) & \ + BIT_MASK_SW_DEFINED_PAGE2_8822C) +#define BIT_SET_SW_DEFINED_PAGE2_8822C(x, v) \ + (BIT_CLEAR_SW_DEFINED_PAGE2_8822C(x) | BIT_SW_DEFINED_PAGE2_8822C(v)) + +/* 2 REG_MCUTST_I_8822C */ + +#define BIT_SHIFT_MCUDMSG_I_8822C 0 +#define BIT_MASK_MCUDMSG_I_8822C 0xffffffffL +#define BIT_MCUDMSG_I_8822C(x) \ + (((x) & BIT_MASK_MCUDMSG_I_8822C) << BIT_SHIFT_MCUDMSG_I_8822C) +#define BITS_MCUDMSG_I_8822C \ + (BIT_MASK_MCUDMSG_I_8822C << BIT_SHIFT_MCUDMSG_I_8822C) +#define BIT_CLEAR_MCUDMSG_I_8822C(x) ((x) & (~BITS_MCUDMSG_I_8822C)) +#define BIT_GET_MCUDMSG_I_8822C(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_I_8822C) & BIT_MASK_MCUDMSG_I_8822C) +#define BIT_SET_MCUDMSG_I_8822C(x, v) \ + (BIT_CLEAR_MCUDMSG_I_8822C(x) | BIT_MCUDMSG_I_8822C(v)) + +/* 2 REG_MCUTST_II_8822C */ + +#define BIT_SHIFT_MCUDMSG_II_8822C 0 +#define BIT_MASK_MCUDMSG_II_8822C 0xffffffffL +#define BIT_MCUDMSG_II_8822C(x) \ + (((x) & BIT_MASK_MCUDMSG_II_8822C) << BIT_SHIFT_MCUDMSG_II_8822C) +#define BITS_MCUDMSG_II_8822C \ + (BIT_MASK_MCUDMSG_II_8822C << BIT_SHIFT_MCUDMSG_II_8822C) +#define BIT_CLEAR_MCUDMSG_II_8822C(x) ((x) & (~BITS_MCUDMSG_II_8822C)) +#define BIT_GET_MCUDMSG_II_8822C(x) \ + (((x) >> BIT_SHIFT_MCUDMSG_II_8822C) & BIT_MASK_MCUDMSG_II_8822C) +#define BIT_SET_MCUDMSG_II_8822C(x, v) \ + (BIT_CLEAR_MCUDMSG_II_8822C(x) | BIT_MCUDMSG_II_8822C(v)) + +/* 2 REG_FMETHR_8822C */ +#define BIT_FMSG_INT_8822C BIT(31) + +#define BIT_SHIFT_FW_MSG_8822C 0 +#define BIT_MASK_FW_MSG_8822C 0xffffffffL +#define BIT_FW_MSG_8822C(x) \ + (((x) & BIT_MASK_FW_MSG_8822C) << BIT_SHIFT_FW_MSG_8822C) +#define BITS_FW_MSG_8822C (BIT_MASK_FW_MSG_8822C << BIT_SHIFT_FW_MSG_8822C) +#define BIT_CLEAR_FW_MSG_8822C(x) ((x) & (~BITS_FW_MSG_8822C)) +#define BIT_GET_FW_MSG_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_8822C) & BIT_MASK_FW_MSG_8822C) +#define BIT_SET_FW_MSG_8822C(x, v) \ + (BIT_CLEAR_FW_MSG_8822C(x) | BIT_FW_MSG_8822C(v)) + +/* 2 REG_HMETFR_8822C */ + +#define BIT_SHIFT_HRCV_MSG_8822C 24 +#define BIT_MASK_HRCV_MSG_8822C 0xff +#define BIT_HRCV_MSG_8822C(x) \ + (((x) & BIT_MASK_HRCV_MSG_8822C) << BIT_SHIFT_HRCV_MSG_8822C) +#define BITS_HRCV_MSG_8822C \ + (BIT_MASK_HRCV_MSG_8822C << BIT_SHIFT_HRCV_MSG_8822C) +#define BIT_CLEAR_HRCV_MSG_8822C(x) ((x) & (~BITS_HRCV_MSG_8822C)) +#define BIT_GET_HRCV_MSG_8822C(x) \ + (((x) >> BIT_SHIFT_HRCV_MSG_8822C) & BIT_MASK_HRCV_MSG_8822C) +#define BIT_SET_HRCV_MSG_8822C(x, v) \ + (BIT_CLEAR_HRCV_MSG_8822C(x) | BIT_HRCV_MSG_8822C(v)) + +#define BIT_INT_BOX3_8822C BIT(3) +#define BIT_INT_BOX2_8822C BIT(2) +#define BIT_INT_BOX1_8822C BIT(1) +#define BIT_INT_BOX0_8822C BIT(0) + +/* 2 REG_HMEBOX0_8822C */ + +#define BIT_SHIFT_HOST_MSG_0_8822C 0 +#define BIT_MASK_HOST_MSG_0_8822C 0xffffffffL +#define BIT_HOST_MSG_0_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_0_8822C) << BIT_SHIFT_HOST_MSG_0_8822C) +#define BITS_HOST_MSG_0_8822C \ + (BIT_MASK_HOST_MSG_0_8822C << BIT_SHIFT_HOST_MSG_0_8822C) +#define BIT_CLEAR_HOST_MSG_0_8822C(x) ((x) & (~BITS_HOST_MSG_0_8822C)) +#define BIT_GET_HOST_MSG_0_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_0_8822C) & BIT_MASK_HOST_MSG_0_8822C) +#define BIT_SET_HOST_MSG_0_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_0_8822C(x) | BIT_HOST_MSG_0_8822C(v)) + +/* 2 REG_HMEBOX1_8822C */ + +#define BIT_SHIFT_HOST_MSG_1_8822C 0 +#define BIT_MASK_HOST_MSG_1_8822C 0xffffffffL +#define BIT_HOST_MSG_1_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_1_8822C) << BIT_SHIFT_HOST_MSG_1_8822C) +#define BITS_HOST_MSG_1_8822C \ + (BIT_MASK_HOST_MSG_1_8822C << BIT_SHIFT_HOST_MSG_1_8822C) +#define BIT_CLEAR_HOST_MSG_1_8822C(x) ((x) & (~BITS_HOST_MSG_1_8822C)) +#define BIT_GET_HOST_MSG_1_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_1_8822C) & BIT_MASK_HOST_MSG_1_8822C) +#define BIT_SET_HOST_MSG_1_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_1_8822C(x) | BIT_HOST_MSG_1_8822C(v)) + +/* 2 REG_HMEBOX2_8822C */ + +#define BIT_SHIFT_HOST_MSG_2_8822C 0 +#define BIT_MASK_HOST_MSG_2_8822C 0xffffffffL +#define BIT_HOST_MSG_2_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_2_8822C) << BIT_SHIFT_HOST_MSG_2_8822C) +#define BITS_HOST_MSG_2_8822C \ + (BIT_MASK_HOST_MSG_2_8822C << BIT_SHIFT_HOST_MSG_2_8822C) +#define BIT_CLEAR_HOST_MSG_2_8822C(x) ((x) & (~BITS_HOST_MSG_2_8822C)) +#define BIT_GET_HOST_MSG_2_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_2_8822C) & BIT_MASK_HOST_MSG_2_8822C) +#define BIT_SET_HOST_MSG_2_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_2_8822C(x) | BIT_HOST_MSG_2_8822C(v)) + +/* 2 REG_HMEBOX3_8822C */ + +#define BIT_SHIFT_HOST_MSG_3_8822C 0 +#define BIT_MASK_HOST_MSG_3_8822C 0xffffffffL +#define BIT_HOST_MSG_3_8822C(x) \ + (((x) & BIT_MASK_HOST_MSG_3_8822C) << BIT_SHIFT_HOST_MSG_3_8822C) +#define BITS_HOST_MSG_3_8822C \ + (BIT_MASK_HOST_MSG_3_8822C << BIT_SHIFT_HOST_MSG_3_8822C) +#define BIT_CLEAR_HOST_MSG_3_8822C(x) ((x) & (~BITS_HOST_MSG_3_8822C)) +#define BIT_GET_HOST_MSG_3_8822C(x) \ + (((x) >> BIT_SHIFT_HOST_MSG_3_8822C) & BIT_MASK_HOST_MSG_3_8822C) +#define BIT_SET_HOST_MSG_3_8822C(x, v) \ + (BIT_CLEAR_HOST_MSG_3_8822C(x) | BIT_HOST_MSG_3_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_BB_ACCESS_CTRL_8822C */ + +#define BIT_SHIFT_BB_WRITE_READ_8822C 30 +#define BIT_MASK_BB_WRITE_READ_8822C 0x3 +#define BIT_BB_WRITE_READ_8822C(x) \ + (((x) & BIT_MASK_BB_WRITE_READ_8822C) << BIT_SHIFT_BB_WRITE_READ_8822C) +#define BITS_BB_WRITE_READ_8822C \ + (BIT_MASK_BB_WRITE_READ_8822C << BIT_SHIFT_BB_WRITE_READ_8822C) +#define BIT_CLEAR_BB_WRITE_READ_8822C(x) ((x) & (~BITS_BB_WRITE_READ_8822C)) +#define BIT_GET_BB_WRITE_READ_8822C(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_READ_8822C) & BIT_MASK_BB_WRITE_READ_8822C) +#define BIT_SET_BB_WRITE_READ_8822C(x, v) \ + (BIT_CLEAR_BB_WRITE_READ_8822C(x) | BIT_BB_WRITE_READ_8822C(v)) + +#define BIT_SHIFT_BB_WRITE_EN_8822C 12 +#define BIT_MASK_BB_WRITE_EN_8822C 0xf +#define BIT_BB_WRITE_EN_8822C(x) \ + (((x) & BIT_MASK_BB_WRITE_EN_8822C) << BIT_SHIFT_BB_WRITE_EN_8822C) +#define BITS_BB_WRITE_EN_8822C \ + (BIT_MASK_BB_WRITE_EN_8822C << BIT_SHIFT_BB_WRITE_EN_8822C) +#define BIT_CLEAR_BB_WRITE_EN_8822C(x) ((x) & (~BITS_BB_WRITE_EN_8822C)) +#define BIT_GET_BB_WRITE_EN_8822C(x) \ + (((x) >> BIT_SHIFT_BB_WRITE_EN_8822C) & BIT_MASK_BB_WRITE_EN_8822C) +#define BIT_SET_BB_WRITE_EN_8822C(x, v) \ + (BIT_CLEAR_BB_WRITE_EN_8822C(x) | BIT_BB_WRITE_EN_8822C(v)) + +#define BIT_SHIFT_BB_ADDR_8822C 2 +#define BIT_MASK_BB_ADDR_8822C 0x1ff +#define BIT_BB_ADDR_8822C(x) \ + (((x) & BIT_MASK_BB_ADDR_8822C) << BIT_SHIFT_BB_ADDR_8822C) +#define BITS_BB_ADDR_8822C (BIT_MASK_BB_ADDR_8822C << BIT_SHIFT_BB_ADDR_8822C) +#define BIT_CLEAR_BB_ADDR_8822C(x) ((x) & (~BITS_BB_ADDR_8822C)) +#define BIT_GET_BB_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_BB_ADDR_8822C) & BIT_MASK_BB_ADDR_8822C) +#define BIT_SET_BB_ADDR_8822C(x, v) \ + (BIT_CLEAR_BB_ADDR_8822C(x) | BIT_BB_ADDR_8822C(v)) + +#define BIT_BB_ERRACC_8822C BIT(0) + +/* 2 REG_BB_ACCESS_DATA_8822C */ + +#define BIT_SHIFT_BB_DATA_8822C 0 +#define BIT_MASK_BB_DATA_8822C 0xffffffffL +#define BIT_BB_DATA_8822C(x) \ + (((x) & BIT_MASK_BB_DATA_8822C) << BIT_SHIFT_BB_DATA_8822C) +#define BITS_BB_DATA_8822C (BIT_MASK_BB_DATA_8822C << BIT_SHIFT_BB_DATA_8822C) +#define BIT_CLEAR_BB_DATA_8822C(x) ((x) & (~BITS_BB_DATA_8822C)) +#define BIT_GET_BB_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_BB_DATA_8822C) & BIT_MASK_BB_DATA_8822C) +#define BIT_SET_BB_DATA_8822C(x, v) \ + (BIT_CLEAR_BB_DATA_8822C(x) | BIT_BB_DATA_8822C(v)) + +/* 2 REG_HMEBOX_E0_8822C */ + +#define BIT_SHIFT_HMEBOX_E0_8822C 0 +#define BIT_MASK_HMEBOX_E0_8822C 0xffffffffL +#define BIT_HMEBOX_E0_8822C(x) \ + (((x) & BIT_MASK_HMEBOX_E0_8822C) << BIT_SHIFT_HMEBOX_E0_8822C) +#define BITS_HMEBOX_E0_8822C \ + (BIT_MASK_HMEBOX_E0_8822C << BIT_SHIFT_HMEBOX_E0_8822C) +#define BIT_CLEAR_HMEBOX_E0_8822C(x) ((x) & (~BITS_HMEBOX_E0_8822C)) +#define BIT_GET_HMEBOX_E0_8822C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E0_8822C) & BIT_MASK_HMEBOX_E0_8822C) +#define BIT_SET_HMEBOX_E0_8822C(x, v) \ + (BIT_CLEAR_HMEBOX_E0_8822C(x) | BIT_HMEBOX_E0_8822C(v)) + +/* 2 REG_HMEBOX_E1_8822C */ + +#define BIT_SHIFT_HMEBOX_E1_8822C 0 +#define BIT_MASK_HMEBOX_E1_8822C 0xffffffffL +#define BIT_HMEBOX_E1_8822C(x) \ + (((x) & BIT_MASK_HMEBOX_E1_8822C) << BIT_SHIFT_HMEBOX_E1_8822C) +#define BITS_HMEBOX_E1_8822C \ + (BIT_MASK_HMEBOX_E1_8822C << BIT_SHIFT_HMEBOX_E1_8822C) +#define BIT_CLEAR_HMEBOX_E1_8822C(x) ((x) & (~BITS_HMEBOX_E1_8822C)) +#define BIT_GET_HMEBOX_E1_8822C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E1_8822C) & BIT_MASK_HMEBOX_E1_8822C) +#define BIT_SET_HMEBOX_E1_8822C(x, v) \ + (BIT_CLEAR_HMEBOX_E1_8822C(x) | BIT_HMEBOX_E1_8822C(v)) + +/* 2 REG_HMEBOX_E2_8822C */ + +#define BIT_SHIFT_HMEBOX_E2_8822C 0 +#define BIT_MASK_HMEBOX_E2_8822C 0xffffffffL +#define BIT_HMEBOX_E2_8822C(x) \ + (((x) & BIT_MASK_HMEBOX_E2_8822C) << BIT_SHIFT_HMEBOX_E2_8822C) +#define BITS_HMEBOX_E2_8822C \ + (BIT_MASK_HMEBOX_E2_8822C << BIT_SHIFT_HMEBOX_E2_8822C) +#define BIT_CLEAR_HMEBOX_E2_8822C(x) ((x) & (~BITS_HMEBOX_E2_8822C)) +#define BIT_GET_HMEBOX_E2_8822C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E2_8822C) & BIT_MASK_HMEBOX_E2_8822C) +#define BIT_SET_HMEBOX_E2_8822C(x, v) \ + (BIT_CLEAR_HMEBOX_E2_8822C(x) | BIT_HMEBOX_E2_8822C(v)) + +/* 2 REG_HMEBOX_E3_8822C */ + +#define BIT_SHIFT_HMEBOX_E3_8822C 0 +#define BIT_MASK_HMEBOX_E3_8822C 0xffffffffL +#define BIT_HMEBOX_E3_8822C(x) \ + (((x) & BIT_MASK_HMEBOX_E3_8822C) << BIT_SHIFT_HMEBOX_E3_8822C) +#define BITS_HMEBOX_E3_8822C \ + (BIT_MASK_HMEBOX_E3_8822C << BIT_SHIFT_HMEBOX_E3_8822C) +#define BIT_CLEAR_HMEBOX_E3_8822C(x) ((x) & (~BITS_HMEBOX_E3_8822C)) +#define BIT_GET_HMEBOX_E3_8822C(x) \ + (((x) >> BIT_SHIFT_HMEBOX_E3_8822C) & BIT_MASK_HMEBOX_E3_8822C) +#define BIT_SET_HMEBOX_E3_8822C(x, v) \ + (BIT_CLEAR_HMEBOX_E3_8822C(x) | BIT_HMEBOX_E3_8822C(v)) + +/* 2 REG_CR_EXT_8822C */ + +#define BIT_SHIFT_PHY_REQ_DELAY_8822C 24 +#define BIT_MASK_PHY_REQ_DELAY_8822C 0xf +#define BIT_PHY_REQ_DELAY_8822C(x) \ + (((x) & BIT_MASK_PHY_REQ_DELAY_8822C) << BIT_SHIFT_PHY_REQ_DELAY_8822C) +#define BITS_PHY_REQ_DELAY_8822C \ + (BIT_MASK_PHY_REQ_DELAY_8822C << BIT_SHIFT_PHY_REQ_DELAY_8822C) +#define BIT_CLEAR_PHY_REQ_DELAY_8822C(x) ((x) & (~BITS_PHY_REQ_DELAY_8822C)) +#define BIT_GET_PHY_REQ_DELAY_8822C(x) \ + (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822C) & BIT_MASK_PHY_REQ_DELAY_8822C) +#define BIT_SET_PHY_REQ_DELAY_8822C(x, v) \ + (BIT_CLEAR_PHY_REQ_DELAY_8822C(x) | BIT_PHY_REQ_DELAY_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_SPD_DOWN_8822C BIT(16) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_NETYPE4_8822C 4 +#define BIT_MASK_NETYPE4_8822C 0x3 +#define BIT_NETYPE4_8822C(x) \ + (((x) & BIT_MASK_NETYPE4_8822C) << BIT_SHIFT_NETYPE4_8822C) +#define BITS_NETYPE4_8822C (BIT_MASK_NETYPE4_8822C << BIT_SHIFT_NETYPE4_8822C) +#define BIT_CLEAR_NETYPE4_8822C(x) ((x) & (~BITS_NETYPE4_8822C)) +#define BIT_GET_NETYPE4_8822C(x) \ + (((x) >> BIT_SHIFT_NETYPE4_8822C) & BIT_MASK_NETYPE4_8822C) +#define BIT_SET_NETYPE4_8822C(x, v) \ + (BIT_CLEAR_NETYPE4_8822C(x) | BIT_NETYPE4_8822C(v)) + +#define BIT_SHIFT_NETYPE3_8822C 2 +#define BIT_MASK_NETYPE3_8822C 0x3 +#define BIT_NETYPE3_8822C(x) \ + (((x) & BIT_MASK_NETYPE3_8822C) << BIT_SHIFT_NETYPE3_8822C) +#define BITS_NETYPE3_8822C (BIT_MASK_NETYPE3_8822C << BIT_SHIFT_NETYPE3_8822C) +#define BIT_CLEAR_NETYPE3_8822C(x) ((x) & (~BITS_NETYPE3_8822C)) +#define BIT_GET_NETYPE3_8822C(x) \ + (((x) >> BIT_SHIFT_NETYPE3_8822C) & BIT_MASK_NETYPE3_8822C) +#define BIT_SET_NETYPE3_8822C(x, v) \ + (BIT_CLEAR_NETYPE3_8822C(x) | BIT_NETYPE3_8822C(v)) + +#define BIT_SHIFT_NETYPE2_8822C 0 +#define BIT_MASK_NETYPE2_8822C 0x3 +#define BIT_NETYPE2_8822C(x) \ + (((x) & BIT_MASK_NETYPE2_8822C) << BIT_SHIFT_NETYPE2_8822C) +#define BITS_NETYPE2_8822C (BIT_MASK_NETYPE2_8822C << BIT_SHIFT_NETYPE2_8822C) +#define BIT_CLEAR_NETYPE2_8822C(x) ((x) & (~BITS_NETYPE2_8822C)) +#define BIT_GET_NETYPE2_8822C(x) \ + (((x) >> BIT_SHIFT_NETYPE2_8822C) & BIT_MASK_NETYPE2_8822C) +#define BIT_SET_NETYPE2_8822C(x, v) \ + (BIT_CLEAR_NETYPE2_8822C(x) | BIT_NETYPE2_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_FWFF_8822C */ + +#define BIT_SHIFT_PKTNUM_TH_V1_8822C 24 +#define BIT_MASK_PKTNUM_TH_V1_8822C 0xff +#define BIT_PKTNUM_TH_V1_8822C(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V1_8822C) << BIT_SHIFT_PKTNUM_TH_V1_8822C) +#define BITS_PKTNUM_TH_V1_8822C \ + (BIT_MASK_PKTNUM_TH_V1_8822C << BIT_SHIFT_PKTNUM_TH_V1_8822C) +#define BIT_CLEAR_PKTNUM_TH_V1_8822C(x) ((x) & (~BITS_PKTNUM_TH_V1_8822C)) +#define BIT_GET_PKTNUM_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822C) & BIT_MASK_PKTNUM_TH_V1_8822C) +#define BIT_SET_PKTNUM_TH_V1_8822C(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V1_8822C(x) | BIT_PKTNUM_TH_V1_8822C(v)) + +#define BIT_SHIFT_TIMER_TH_8822C 16 +#define BIT_MASK_TIMER_TH_8822C 0xff +#define BIT_TIMER_TH_8822C(x) \ + (((x) & BIT_MASK_TIMER_TH_8822C) << BIT_SHIFT_TIMER_TH_8822C) +#define BITS_TIMER_TH_8822C \ + (BIT_MASK_TIMER_TH_8822C << BIT_SHIFT_TIMER_TH_8822C) +#define BIT_CLEAR_TIMER_TH_8822C(x) ((x) & (~BITS_TIMER_TH_8822C)) +#define BIT_GET_TIMER_TH_8822C(x) \ + (((x) >> BIT_SHIFT_TIMER_TH_8822C) & BIT_MASK_TIMER_TH_8822C) +#define BIT_SET_TIMER_TH_8822C(x, v) \ + (BIT_CLEAR_TIMER_TH_8822C(x) | BIT_TIMER_TH_8822C(v)) + +#define BIT_SHIFT_RXPKT1ENADDR_8822C 0 +#define BIT_MASK_RXPKT1ENADDR_8822C 0xffff +#define BIT_RXPKT1ENADDR_8822C(x) \ + (((x) & BIT_MASK_RXPKT1ENADDR_8822C) << BIT_SHIFT_RXPKT1ENADDR_8822C) +#define BITS_RXPKT1ENADDR_8822C \ + (BIT_MASK_RXPKT1ENADDR_8822C << BIT_SHIFT_RXPKT1ENADDR_8822C) +#define BIT_CLEAR_RXPKT1ENADDR_8822C(x) ((x) & (~BITS_RXPKT1ENADDR_8822C)) +#define BIT_GET_RXPKT1ENADDR_8822C(x) \ + (((x) >> BIT_SHIFT_RXPKT1ENADDR_8822C) & BIT_MASK_RXPKT1ENADDR_8822C) +#define BIT_SET_RXPKT1ENADDR_8822C(x, v) \ + (BIT_CLEAR_RXPKT1ENADDR_8822C(x) | BIT_RXPKT1ENADDR_8822C(v)) + +/* 2 REG_RXFF_PTR_V1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_RXFF0_RDPTR_V2_8822C 0 +#define BIT_MASK_RXFF0_RDPTR_V2_8822C 0x3ffff +#define BIT_RXFF0_RDPTR_V2_8822C(x) \ + (((x) & BIT_MASK_RXFF0_RDPTR_V2_8822C) \ + << BIT_SHIFT_RXFF0_RDPTR_V2_8822C) +#define BITS_RXFF0_RDPTR_V2_8822C \ + (BIT_MASK_RXFF0_RDPTR_V2_8822C << BIT_SHIFT_RXFF0_RDPTR_V2_8822C) +#define BIT_CLEAR_RXFF0_RDPTR_V2_8822C(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8822C)) +#define BIT_GET_RXFF0_RDPTR_V2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822C) & \ + BIT_MASK_RXFF0_RDPTR_V2_8822C) +#define BIT_SET_RXFF0_RDPTR_V2_8822C(x, v) \ + (BIT_CLEAR_RXFF0_RDPTR_V2_8822C(x) | BIT_RXFF0_RDPTR_V2_8822C(v)) + +/* 2 REG_RXFF_WTR_V1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_RXFF0_WTPTR_V2_8822C 0 +#define BIT_MASK_RXFF0_WTPTR_V2_8822C 0x3ffff +#define BIT_RXFF0_WTPTR_V2_8822C(x) \ + (((x) & BIT_MASK_RXFF0_WTPTR_V2_8822C) \ + << BIT_SHIFT_RXFF0_WTPTR_V2_8822C) +#define BITS_RXFF0_WTPTR_V2_8822C \ + (BIT_MASK_RXFF0_WTPTR_V2_8822C << BIT_SHIFT_RXFF0_WTPTR_V2_8822C) +#define BIT_CLEAR_RXFF0_WTPTR_V2_8822C(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8822C)) +#define BIT_GET_RXFF0_WTPTR_V2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822C) & \ + BIT_MASK_RXFF0_WTPTR_V2_8822C) +#define BIT_SET_RXFF0_WTPTR_V2_8822C(x, v) \ + (BIT_CLEAR_RXFF0_WTPTR_V2_8822C(x) | BIT_RXFF0_WTPTR_V2_8822C(v)) + +/* 2 REG_FE2IMR_8822C */ +#define BIT__FE4ISR__IND_MSK_8822C BIT(29) +#define BIT_FS_TXSC_DESC_DONE_INT_EN_8822C BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_EN_8822C BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_EN_8822C BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_EN_8822C BIT(25) +#define BIT_FS_TXSC_VODONE_INT_EN_8822C BIT(24) +#define BIT_FS_ATIM_MB7_INT_EN_8822C BIT(23) +#define BIT_FS_ATIM_MB6_INT_EN_8822C BIT(22) +#define BIT_FS_ATIM_MB5_INT_EN_8822C BIT(21) +#define BIT_FS_ATIM_MB4_INT_EN_8822C BIT(20) +#define BIT_FS_ATIM_MB3_INT_EN_8822C BIT(19) +#define BIT_FS_ATIM_MB2_INT_EN_8822C BIT(18) +#define BIT_FS_ATIM_MB1_INT_EN_8822C BIT(17) +#define BIT_FS_ATIM_MB0_INT_EN_8822C BIT(16) +#define BIT_FS_TBTT4INT_EN_8822C BIT(11) +#define BIT_FS_TBTT3INT_EN_8822C BIT(10) +#define BIT_FS_TBTT2INT_EN_8822C BIT(9) +#define BIT_FS_TBTT1INT_EN_8822C BIT(8) +#define BIT_FS_TBTT0_MB7INT_EN_8822C BIT(7) +#define BIT_FS_TBTT0_MB6INT_EN_8822C BIT(6) +#define BIT_FS_TBTT0_MB5INT_EN_8822C BIT(5) +#define BIT_FS_TBTT0_MB4INT_EN_8822C BIT(4) +#define BIT_FS_TBTT0_MB3INT_EN_8822C BIT(3) +#define BIT_FS_TBTT0_MB2INT_EN_8822C BIT(2) +#define BIT_FS_TBTT0_MB1INT_EN_8822C BIT(1) +#define BIT_FS_TBTT0_INT_EN_8822C BIT(0) + +/* 2 REG_FE2ISR_8822C */ +#define BIT__FE4ISR__IND_INT_8822C BIT(29) +#define BIT_FS_TXSC_DESC_DONE_INT_8822C BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_8822C BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_8822C BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_8822C BIT(25) +#define BIT_FS_TXSC_VODONE_INT_8822C BIT(24) +#define BIT_FS_ATIM_MB7_INT_8822C BIT(23) +#define BIT_FS_ATIM_MB6_INT_8822C BIT(22) +#define BIT_FS_ATIM_MB5_INT_8822C BIT(21) +#define BIT_FS_ATIM_MB4_INT_8822C BIT(20) +#define BIT_FS_ATIM_MB3_INT_8822C BIT(19) +#define BIT_FS_ATIM_MB2_INT_8822C BIT(18) +#define BIT_FS_ATIM_MB1_INT_8822C BIT(17) +#define BIT_FS_ATIM_MB0_INT_8822C BIT(16) +#define BIT_FS_TBTT4INT_8822C BIT(11) +#define BIT_FS_TBTT3INT_8822C BIT(10) +#define BIT_FS_TBTT2INT_8822C BIT(9) +#define BIT_FS_TBTT1INT_8822C BIT(8) +#define BIT_FS_TBTT0_MB7INT_8822C BIT(7) +#define BIT_FS_TBTT0_MB6INT_8822C BIT(6) +#define BIT_FS_TBTT0_MB5INT_8822C BIT(5) +#define BIT_FS_TBTT0_MB4INT_8822C BIT(4) +#define BIT_FS_TBTT0_MB3INT_8822C BIT(3) +#define BIT_FS_TBTT0_MB2INT_8822C BIT(2) +#define BIT_FS_TBTT0_MB1INT_8822C BIT(1) +#define BIT_FS_TBTT0_INT_8822C BIT(0) + +/* 2 REG_FE3IMR_8822C */ +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8822C BIT(31) +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8822C BIT(30) +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8822C BIT(29) +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8822C BIT(28) +#define BIT_FS_BCNDMA4_INT_EN_8822C BIT(27) +#define BIT_FS_BCNDMA3_INT_EN_8822C BIT(26) +#define BIT_FS_BCNDMA2_INT_EN_8822C BIT(25) +#define BIT_FS_BCNDMA1_INT_EN_8822C BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_EN_8822C BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_EN_8822C BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_EN_8822C BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_EN_8822C BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_EN_8822C BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_EN_8822C BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_EN_8822C BIT(17) +#define BIT_FS_BCNDMA0_INT_EN_8822C BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8822C BIT(15) +#define BIT_FS_BCNERLY4_INT_EN_8822C BIT(11) +#define BIT_FS_BCNERLY3_INT_EN_8822C BIT(10) +#define BIT_FS_BCNERLY2_INT_EN_8822C BIT(9) +#define BIT_FS_BCNERLY1_INT_EN_8822C BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_EN_8822C BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_EN_8822C BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_EN_8822C BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_EN_8822C BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_EN_8822C BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_EN_8822C BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_EN_8822C BIT(1) +#define BIT_FS_BCNERLY0_INT_EN_8822C BIT(0) + +/* 2 REG_FE3ISR_8822C */ +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8822C BIT(31) +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8822C BIT(30) +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8822C BIT(29) +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8822C BIT(28) +#define BIT_FS_BCNDMA4_INT_8822C BIT(27) +#define BIT_FS_BCNDMA3_INT_8822C BIT(26) +#define BIT_FS_BCNDMA2_INT_8822C BIT(25) +#define BIT_FS_BCNDMA1_INT_8822C BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_8822C BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_8822C BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_8822C BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_8822C BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_8822C BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_8822C BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_8822C BIT(17) +#define BIT_FS_BCNDMA0_INT_8822C BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT_8822C BIT(15) +#define BIT_FS_BCNERLY4_INT_8822C BIT(11) +#define BIT_FS_BCNERLY3_INT_8822C BIT(10) +#define BIT_FS_BCNERLY2_INT_8822C BIT(9) +#define BIT_FS_BCNERLY1_INT_8822C BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_8822C BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_8822C BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_8822C BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_8822C BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_8822C BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_8822C BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_8822C BIT(1) +#define BIT_FS_BCNERLY0_INT_8822C BIT(0) + +/* 2 REG_FE4IMR_8822C */ +#define BIT_FS_CLI3_TXPKTIN_INT_EN_8822C BIT(19) +#define BIT_FS_CLI2_TXPKTIN_INT_EN_8822C BIT(18) +#define BIT_FS_CLI1_TXPKTIN_INT_EN_8822C BIT(17) +#define BIT_FS_CLI0_TXPKTIN_INT_EN_8822C BIT(16) +#define BIT_FS_CLI3_RX_UMD0_INT_EN_8822C BIT(15) +#define BIT_FS_CLI3_RX_UMD1_INT_EN_8822C BIT(14) +#define BIT_FS_CLI3_RX_BMD0_INT_EN_8822C BIT(13) +#define BIT_FS_CLI3_RX_BMD1_INT_EN_8822C BIT(12) +#define BIT_FS_CLI2_RX_UMD0_INT_EN_8822C BIT(11) +#define BIT_FS_CLI2_RX_UMD1_INT_EN_8822C BIT(10) +#define BIT_FS_CLI2_RX_BMD0_INT_EN_8822C BIT(9) +#define BIT_FS_CLI2_RX_BMD1_INT_EN_8822C BIT(8) +#define BIT_FS_CLI1_RX_UMD0_INT_EN_8822C BIT(7) +#define BIT_FS_CLI1_RX_UMD1_INT_EN_8822C BIT(6) +#define BIT_FS_CLI1_RX_BMD0_INT_EN_8822C BIT(5) +#define BIT_FS_CLI1_RX_BMD1_INT_EN_8822C BIT(4) +#define BIT_FS_CLI0_RX_UMD0_INT_EN_8822C BIT(3) +#define BIT_FS_CLI0_RX_UMD1_INT_EN_8822C BIT(2) +#define BIT_FS_CLI0_RX_BMD0_INT_EN_8822C BIT(1) +#define BIT_FS_CLI0_RX_BMD1_INT_EN_8822C BIT(0) + +/* 2 REG_FE4ISR_8822C */ +#define BIT_FS_CLI3_TXPKTIN_INT_8822C BIT(19) +#define BIT_FS_CLI2_TXPKTIN_INT_8822C BIT(18) +#define BIT_FS_CLI1_TXPKTIN_INT_8822C BIT(17) +#define BIT_FS_CLI0_TXPKTIN_INT_8822C BIT(16) +#define BIT_FS_CLI3_RX_UMD0_INT_8822C BIT(15) +#define BIT_FS_CLI3_RX_UMD1_INT_8822C BIT(14) +#define BIT_FS_CLI3_RX_BMD0_INT_8822C BIT(13) +#define BIT_FS_CLI3_RX_BMD1_INT_8822C BIT(12) +#define BIT_FS_CLI2_RX_UMD0_INT_8822C BIT(11) +#define BIT_FS_CLI2_RX_UMD1_INT_8822C BIT(10) +#define BIT_FS_CLI2_RX_BMD0_INT_8822C BIT(9) +#define BIT_FS_CLI2_RX_BMD1_INT_8822C BIT(8) +#define BIT_FS_CLI1_RX_UMD0_INT_8822C BIT(7) +#define BIT_FS_CLI1_RX_UMD1_INT_8822C BIT(6) +#define BIT_FS_CLI1_RX_BMD0_INT_8822C BIT(5) +#define BIT_FS_CLI1_RX_BMD1_INT_8822C BIT(4) +#define BIT_FS_CLI0_RX_UMD0_INT_8822C BIT(3) +#define BIT_FS_CLI0_RX_UMD1_INT_8822C BIT(2) +#define BIT_FS_CLI0_RX_BMD0_INT_8822C BIT(1) +#define BIT_FS_CLI0_RX_BMD1_INT_8822C BIT(0) + +/* 2 REG_FT1IMR_8822C */ +#define BIT__FT2ISR__IND_MSK_8822C BIT(30) +#define BIT_FTM_PTT_INT_EN_8822C BIT(29) +#define BIT_RXFTMREQ_INT_EN_8822C BIT(28) +#define BIT_RXFTM_INT_EN_8822C BIT(27) +#define BIT_TXFTM_INT_EN_8822C BIT(26) +#define BIT_FS_H2C_CMD_OK_INT_EN_8822C BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_EN_8822C BIT(24) +#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8822C BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8822C BIT(22) +#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8822C BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8822C BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8822C BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8822C BIT(18) +#define BIT_FS_CTWEND2_INT_EN_8822C BIT(17) +#define BIT_FS_CTWEND1_INT_EN_8822C BIT(16) +#define BIT_FS_CTWEND0_INT_EN_8822C BIT(15) +#define BIT_FS_TX_NULL1_INT_EN_8822C BIT(14) +#define BIT_FS_TX_NULL0_INT_EN_8822C BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_EN_8822C BIT(12) +#define BIT_FS_P2P_RFON2_INT_EN_8822C BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_EN_8822C BIT(10) +#define BIT_FS_P2P_RFON1_INT_EN_8822C BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_EN_8822C BIT(8) +#define BIT_FS_P2P_RFON0_INT_EN_8822C BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_EN_8822C BIT(6) +#define BIT_FS_RX_UAPSDMD1_EN_8822C BIT(5) +#define BIT_FS_RX_UAPSDMD0_EN_8822C BIT(4) +#define BIT_FS_TRIGGER_PKT_EN_8822C BIT(3) +#define BIT_FS_EOSP_INT_EN_8822C BIT(2) +#define BIT_FS_RPWM2_INT_EN_8822C BIT(1) +#define BIT_FS_RPWM_INT_EN_8822C BIT(0) + +/* 2 REG_FT1ISR_8822C */ +#define BIT__FT2ISR__IND_INT_8822C BIT(30) +#define BIT_FTM_PTT_INT_8822C BIT(29) +#define BIT_RXFTMREQ_INT_8822C BIT(28) +#define BIT_RXFTM_INT_8822C BIT(27) +#define BIT_TXFTM_INT_8822C BIT(26) +#define BIT_FS_H2C_CMD_OK_INT_8822C BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_8822C BIT(24) +#define BIT_FS_MACID_PWRCHANGE5_INT_8822C BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_8822C BIT(22) +#define BIT_FS_MACID_PWRCHANGE3_INT_8822C BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_8822C BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_8822C BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_8822C BIT(18) +#define BIT_FS_CTWEND2_INT_8822C BIT(17) +#define BIT_FS_CTWEND1_INT_8822C BIT(16) +#define BIT_FS_CTWEND0_INT_8822C BIT(15) +#define BIT_FS_TX_NULL1_INT_8822C BIT(14) +#define BIT_FS_TX_NULL0_INT_8822C BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_INT_8822C BIT(12) +#define BIT_FS_P2P_RFON2_INT_8822C BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_8822C BIT(10) +#define BIT_FS_P2P_RFON1_INT_8822C BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_8822C BIT(8) +#define BIT_FS_P2P_RFON0_INT_8822C BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_8822C BIT(6) +#define BIT_FS_RX_UAPSDMD1_INT_8822C BIT(5) +#define BIT_FS_RX_UAPSDMD0_INT_8822C BIT(4) +#define BIT_FS_TRIGGER_PKT_INT_8822C BIT(3) +#define BIT_FS_EOSP_INT_8822C BIT(2) +#define BIT_FS_RPWM2_INT_8822C BIT(1) +#define BIT_FS_RPWM_INT_8822C BIT(0) + +/* 2 REG_SPWR0_8822C */ + +#define BIT_SHIFT_MID_31TO0_8822C 0 +#define BIT_MASK_MID_31TO0_8822C 0xffffffffL +#define BIT_MID_31TO0_8822C(x) \ + (((x) & BIT_MASK_MID_31TO0_8822C) << BIT_SHIFT_MID_31TO0_8822C) +#define BITS_MID_31TO0_8822C \ + (BIT_MASK_MID_31TO0_8822C << BIT_SHIFT_MID_31TO0_8822C) +#define BIT_CLEAR_MID_31TO0_8822C(x) ((x) & (~BITS_MID_31TO0_8822C)) +#define BIT_GET_MID_31TO0_8822C(x) \ + (((x) >> BIT_SHIFT_MID_31TO0_8822C) & BIT_MASK_MID_31TO0_8822C) +#define BIT_SET_MID_31TO0_8822C(x, v) \ + (BIT_CLEAR_MID_31TO0_8822C(x) | BIT_MID_31TO0_8822C(v)) + +/* 2 REG_SPWR1_8822C */ + +#define BIT_SHIFT_MID_63TO32_8822C 0 +#define BIT_MASK_MID_63TO32_8822C 0xffffffffL +#define BIT_MID_63TO32_8822C(x) \ + (((x) & BIT_MASK_MID_63TO32_8822C) << BIT_SHIFT_MID_63TO32_8822C) +#define BITS_MID_63TO32_8822C \ + (BIT_MASK_MID_63TO32_8822C << BIT_SHIFT_MID_63TO32_8822C) +#define BIT_CLEAR_MID_63TO32_8822C(x) ((x) & (~BITS_MID_63TO32_8822C)) +#define BIT_GET_MID_63TO32_8822C(x) \ + (((x) >> BIT_SHIFT_MID_63TO32_8822C) & BIT_MASK_MID_63TO32_8822C) +#define BIT_SET_MID_63TO32_8822C(x, v) \ + (BIT_CLEAR_MID_63TO32_8822C(x) | BIT_MID_63TO32_8822C(v)) + +/* 2 REG_SPWR2_8822C */ + +#define BIT_SHIFT_MID_95O64_8822C 0 +#define BIT_MASK_MID_95O64_8822C 0xffffffffL +#define BIT_MID_95O64_8822C(x) \ + (((x) & BIT_MASK_MID_95O64_8822C) << BIT_SHIFT_MID_95O64_8822C) +#define BITS_MID_95O64_8822C \ + (BIT_MASK_MID_95O64_8822C << BIT_SHIFT_MID_95O64_8822C) +#define BIT_CLEAR_MID_95O64_8822C(x) ((x) & (~BITS_MID_95O64_8822C)) +#define BIT_GET_MID_95O64_8822C(x) \ + (((x) >> BIT_SHIFT_MID_95O64_8822C) & BIT_MASK_MID_95O64_8822C) +#define BIT_SET_MID_95O64_8822C(x, v) \ + (BIT_CLEAR_MID_95O64_8822C(x) | BIT_MID_95O64_8822C(v)) + +/* 2 REG_SPWR3_8822C */ + +#define BIT_SHIFT_MID_127TO96_8822C 0 +#define BIT_MASK_MID_127TO96_8822C 0xffffffffL +#define BIT_MID_127TO96_8822C(x) \ + (((x) & BIT_MASK_MID_127TO96_8822C) << BIT_SHIFT_MID_127TO96_8822C) +#define BITS_MID_127TO96_8822C \ + (BIT_MASK_MID_127TO96_8822C << BIT_SHIFT_MID_127TO96_8822C) +#define BIT_CLEAR_MID_127TO96_8822C(x) ((x) & (~BITS_MID_127TO96_8822C)) +#define BIT_GET_MID_127TO96_8822C(x) \ + (((x) >> BIT_SHIFT_MID_127TO96_8822C) & BIT_MASK_MID_127TO96_8822C) +#define BIT_SET_MID_127TO96_8822C(x, v) \ + (BIT_CLEAR_MID_127TO96_8822C(x) | BIT_MID_127TO96_8822C(v)) + +/* 2 REG_POWSEQ_8822C */ + +#define BIT_SHIFT_SEQNUM_MID_8822C 16 +#define BIT_MASK_SEQNUM_MID_8822C 0xffff +#define BIT_SEQNUM_MID_8822C(x) \ + (((x) & BIT_MASK_SEQNUM_MID_8822C) << BIT_SHIFT_SEQNUM_MID_8822C) +#define BITS_SEQNUM_MID_8822C \ + (BIT_MASK_SEQNUM_MID_8822C << BIT_SHIFT_SEQNUM_MID_8822C) +#define BIT_CLEAR_SEQNUM_MID_8822C(x) ((x) & (~BITS_SEQNUM_MID_8822C)) +#define BIT_GET_SEQNUM_MID_8822C(x) \ + (((x) >> BIT_SHIFT_SEQNUM_MID_8822C) & BIT_MASK_SEQNUM_MID_8822C) +#define BIT_SET_SEQNUM_MID_8822C(x, v) \ + (BIT_CLEAR_SEQNUM_MID_8822C(x) | BIT_SEQNUM_MID_8822C(v)) + +#define BIT_SHIFT_REF_MID_8822C 0 +#define BIT_MASK_REF_MID_8822C 0x7f +#define BIT_REF_MID_8822C(x) \ + (((x) & BIT_MASK_REF_MID_8822C) << BIT_SHIFT_REF_MID_8822C) +#define BITS_REF_MID_8822C (BIT_MASK_REF_MID_8822C << BIT_SHIFT_REF_MID_8822C) +#define BIT_CLEAR_REF_MID_8822C(x) ((x) & (~BITS_REF_MID_8822C)) +#define BIT_GET_REF_MID_8822C(x) \ + (((x) >> BIT_SHIFT_REF_MID_8822C) & BIT_MASK_REF_MID_8822C) +#define BIT_SET_REF_MID_8822C(x, v) \ + (BIT_CLEAR_REF_MID_8822C(x) | BIT_REF_MID_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_TC7_CTRL_V1_8822C */ +#define BIT_TC7INT_EN_8822C BIT(26) +#define BIT_TC7MODE_8822C BIT(25) +#define BIT_TC7EN_8822C BIT(24) + +#define BIT_SHIFT_TC7DATA_8822C 0 +#define BIT_MASK_TC7DATA_8822C 0xffffff +#define BIT_TC7DATA_8822C(x) \ + (((x) & BIT_MASK_TC7DATA_8822C) << BIT_SHIFT_TC7DATA_8822C) +#define BITS_TC7DATA_8822C (BIT_MASK_TC7DATA_8822C << BIT_SHIFT_TC7DATA_8822C) +#define BIT_CLEAR_TC7DATA_8822C(x) ((x) & (~BITS_TC7DATA_8822C)) +#define BIT_GET_TC7DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC7DATA_8822C) & BIT_MASK_TC7DATA_8822C) +#define BIT_SET_TC7DATA_8822C(x, v) \ + (BIT_CLEAR_TC7DATA_8822C(x) | BIT_TC7DATA_8822C(v)) + +/* 2 REG_TC8_CTRL_V1_8822C */ +#define BIT_TC8INT_EN_8822C BIT(26) +#define BIT_TC8MODE_8822C BIT(25) +#define BIT_TC8EN_8822C BIT(24) + +#define BIT_SHIFT_TC8DATA_8822C 0 +#define BIT_MASK_TC8DATA_8822C 0xffffff +#define BIT_TC8DATA_8822C(x) \ + (((x) & BIT_MASK_TC8DATA_8822C) << BIT_SHIFT_TC8DATA_8822C) +#define BITS_TC8DATA_8822C (BIT_MASK_TC8DATA_8822C << BIT_SHIFT_TC8DATA_8822C) +#define BIT_CLEAR_TC8DATA_8822C(x) ((x) & (~BITS_TC8DATA_8822C)) +#define BIT_GET_TC8DATA_8822C(x) \ + (((x) >> BIT_SHIFT_TC8DATA_8822C) & BIT_MASK_TC8DATA_8822C) +#define BIT_SET_TC8DATA_8822C(x, v) \ + (BIT_CLEAR_TC8DATA_8822C(x) | BIT_TC8DATA_8822C(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL0_8822C */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C 24 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8822C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8822C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT2_8822C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C 16 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8822C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8822C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT1_8822C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C 8 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8822C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8822C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT0_8822C(v)) + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C 0xff +#define BIT_RX_BCN_TBTT_ITVL_PORT0_8822C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C) +#define BITS_RX_BCN_TBTT_ITVL_PORT0_8822C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8822C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8822C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8822C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C) +#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8822C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8822C(x) | \ + BIT_RX_BCN_TBTT_ITVL_PORT0_8822C(v)) + +/* 2 REG_RX_BCN_TBTT_ITVL1_8822C */ + +#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C 0 +#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C 0xff +#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) \ + (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C) \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C) +#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8822C \ + (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C \ + << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C) +#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) \ + ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8822C)) +#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) \ + (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C) & \ + BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C) +#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x, v) \ + (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) | \ + BIT_RX_BCN_TBTT_ITVL_CLIENT3_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_IO_WRAP_ERR_FLAG_8822C */ +#define BIT_IO_WRAP_ERR_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SPEED_SENSOR_8822C */ +#define BIT_DSS_1_RST_N_8822C BIT(31) +#define BIT_DSS_1_SPEED_EN_8822C BIT(30) +#define BIT_DSS_1_WIRE_SEL_8822C BIT(29) +#define BIT_DSS_ENCLK_8822C BIT(28) + +#define BIT_SHIFT_DSS_1_RO_SEL_8822C 24 +#define BIT_MASK_DSS_1_RO_SEL_8822C 0x7 +#define BIT_DSS_1_RO_SEL_8822C(x) \ + (((x) & BIT_MASK_DSS_1_RO_SEL_8822C) << BIT_SHIFT_DSS_1_RO_SEL_8822C) +#define BITS_DSS_1_RO_SEL_8822C \ + (BIT_MASK_DSS_1_RO_SEL_8822C << BIT_SHIFT_DSS_1_RO_SEL_8822C) +#define BIT_CLEAR_DSS_1_RO_SEL_8822C(x) ((x) & (~BITS_DSS_1_RO_SEL_8822C)) +#define BIT_GET_DSS_1_RO_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_1_RO_SEL_8822C) & BIT_MASK_DSS_1_RO_SEL_8822C) +#define BIT_SET_DSS_1_RO_SEL_8822C(x, v) \ + (BIT_CLEAR_DSS_1_RO_SEL_8822C(x) | BIT_DSS_1_RO_SEL_8822C(v)) + +#define BIT_SHIFT_DSS_1_DATA_IN_8822C 0 +#define BIT_MASK_DSS_1_DATA_IN_8822C 0xfffff +#define BIT_DSS_1_DATA_IN_8822C(x) \ + (((x) & BIT_MASK_DSS_1_DATA_IN_8822C) << BIT_SHIFT_DSS_1_DATA_IN_8822C) +#define BITS_DSS_1_DATA_IN_8822C \ + (BIT_MASK_DSS_1_DATA_IN_8822C << BIT_SHIFT_DSS_1_DATA_IN_8822C) +#define BIT_CLEAR_DSS_1_DATA_IN_8822C(x) ((x) & (~BITS_DSS_1_DATA_IN_8822C)) +#define BIT_GET_DSS_1_DATA_IN_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_1_DATA_IN_8822C) & BIT_MASK_DSS_1_DATA_IN_8822C) +#define BIT_SET_DSS_1_DATA_IN_8822C(x, v) \ + (BIT_CLEAR_DSS_1_DATA_IN_8822C(x) | BIT_DSS_1_DATA_IN_8822C(v)) + +/* 2 REG_SPEED_SENSOR1_8822C */ +#define BIT_DSS_1_READY_8822C BIT(31) +#define BIT_DSS_1_WSORT_GO_8822C BIT(30) + +#define BIT_SHIFT_DSS_1_COUNT_OUT_8822C 0 +#define BIT_MASK_DSS_1_COUNT_OUT_8822C 0xfffff +#define BIT_DSS_1_COUNT_OUT_8822C(x) \ + (((x) & BIT_MASK_DSS_1_COUNT_OUT_8822C) \ + << BIT_SHIFT_DSS_1_COUNT_OUT_8822C) +#define BITS_DSS_1_COUNT_OUT_8822C \ + (BIT_MASK_DSS_1_COUNT_OUT_8822C << BIT_SHIFT_DSS_1_COUNT_OUT_8822C) +#define BIT_CLEAR_DSS_1_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8822C)) +#define BIT_GET_DSS_1_COUNT_OUT_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8822C) & \ + BIT_MASK_DSS_1_COUNT_OUT_8822C) +#define BIT_SET_DSS_1_COUNT_OUT_8822C(x, v) \ + (BIT_CLEAR_DSS_1_COUNT_OUT_8822C(x) | BIT_DSS_1_COUNT_OUT_8822C(v)) + +/* 2 REG_SPEED_SENSOR2_8822C */ +#define BIT_DSS_2_RST_N_8822C BIT(31) +#define BIT_DSS_2_SPEED_EN_8822C BIT(30) +#define BIT_DSS_2_WIRE_SEL_8822C BIT(29) +#define BIT_DSS_ENCLK_8822C BIT(28) + +#define BIT_SHIFT_DSS_2_RO_SEL_8822C 24 +#define BIT_MASK_DSS_2_RO_SEL_8822C 0x7 +#define BIT_DSS_2_RO_SEL_8822C(x) \ + (((x) & BIT_MASK_DSS_2_RO_SEL_8822C) << BIT_SHIFT_DSS_2_RO_SEL_8822C) +#define BITS_DSS_2_RO_SEL_8822C \ + (BIT_MASK_DSS_2_RO_SEL_8822C << BIT_SHIFT_DSS_2_RO_SEL_8822C) +#define BIT_CLEAR_DSS_2_RO_SEL_8822C(x) ((x) & (~BITS_DSS_2_RO_SEL_8822C)) +#define BIT_GET_DSS_2_RO_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_2_RO_SEL_8822C) & BIT_MASK_DSS_2_RO_SEL_8822C) +#define BIT_SET_DSS_2_RO_SEL_8822C(x, v) \ + (BIT_CLEAR_DSS_2_RO_SEL_8822C(x) | BIT_DSS_2_RO_SEL_8822C(v)) + +#define BIT_SHIFT_DSS_2_DATA_IN_8822C 0 +#define BIT_MASK_DSS_2_DATA_IN_8822C 0xfffff +#define BIT_DSS_2_DATA_IN_8822C(x) \ + (((x) & BIT_MASK_DSS_2_DATA_IN_8822C) << BIT_SHIFT_DSS_2_DATA_IN_8822C) +#define BITS_DSS_2_DATA_IN_8822C \ + (BIT_MASK_DSS_2_DATA_IN_8822C << BIT_SHIFT_DSS_2_DATA_IN_8822C) +#define BIT_CLEAR_DSS_2_DATA_IN_8822C(x) ((x) & (~BITS_DSS_2_DATA_IN_8822C)) +#define BIT_GET_DSS_2_DATA_IN_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_2_DATA_IN_8822C) & BIT_MASK_DSS_2_DATA_IN_8822C) +#define BIT_SET_DSS_2_DATA_IN_8822C(x, v) \ + (BIT_CLEAR_DSS_2_DATA_IN_8822C(x) | BIT_DSS_2_DATA_IN_8822C(v)) + +/* 2 REG_SPEED_SENSOR3_8822C */ +#define BIT_DSS_2_READY_8822C BIT(31) +#define BIT_DSS_2_WSORT_GO_8822C BIT(30) + +#define BIT_SHIFT_DSS_2_COUNT_OUT_8822C 0 +#define BIT_MASK_DSS_2_COUNT_OUT_8822C 0xfffff +#define BIT_DSS_2_COUNT_OUT_8822C(x) \ + (((x) & BIT_MASK_DSS_2_COUNT_OUT_8822C) \ + << BIT_SHIFT_DSS_2_COUNT_OUT_8822C) +#define BITS_DSS_2_COUNT_OUT_8822C \ + (BIT_MASK_DSS_2_COUNT_OUT_8822C << BIT_SHIFT_DSS_2_COUNT_OUT_8822C) +#define BIT_CLEAR_DSS_2_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8822C)) +#define BIT_GET_DSS_2_COUNT_OUT_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8822C) & \ + BIT_MASK_DSS_2_COUNT_OUT_8822C) +#define BIT_SET_DSS_2_COUNT_OUT_8822C(x, v) \ + (BIT_CLEAR_DSS_2_COUNT_OUT_8822C(x) | BIT_DSS_2_COUNT_OUT_8822C(v)) + +/* 2 REG_SPEED_SENSOR4_8822C */ +#define BIT_DSS_3_RST_N_8822C BIT(31) +#define BIT_DSS_3_SPEED_EN_8822C BIT(30) +#define BIT_DSS_3_WIRE_SEL_8822C BIT(29) +#define BIT_DSS_ENCLK_8822C BIT(28) + +#define BIT_SHIFT_DSS_3_RO_SEL_8822C 24 +#define BIT_MASK_DSS_3_RO_SEL_8822C 0x7 +#define BIT_DSS_3_RO_SEL_8822C(x) \ + (((x) & BIT_MASK_DSS_3_RO_SEL_8822C) << BIT_SHIFT_DSS_3_RO_SEL_8822C) +#define BITS_DSS_3_RO_SEL_8822C \ + (BIT_MASK_DSS_3_RO_SEL_8822C << BIT_SHIFT_DSS_3_RO_SEL_8822C) +#define BIT_CLEAR_DSS_3_RO_SEL_8822C(x) ((x) & (~BITS_DSS_3_RO_SEL_8822C)) +#define BIT_GET_DSS_3_RO_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_3_RO_SEL_8822C) & BIT_MASK_DSS_3_RO_SEL_8822C) +#define BIT_SET_DSS_3_RO_SEL_8822C(x, v) \ + (BIT_CLEAR_DSS_3_RO_SEL_8822C(x) | BIT_DSS_3_RO_SEL_8822C(v)) + +#define BIT_SHIFT_DSS_3_DATA_IN_8822C 0 +#define BIT_MASK_DSS_3_DATA_IN_8822C 0xfffff +#define BIT_DSS_3_DATA_IN_8822C(x) \ + (((x) & BIT_MASK_DSS_3_DATA_IN_8822C) << BIT_SHIFT_DSS_3_DATA_IN_8822C) +#define BITS_DSS_3_DATA_IN_8822C \ + (BIT_MASK_DSS_3_DATA_IN_8822C << BIT_SHIFT_DSS_3_DATA_IN_8822C) +#define BIT_CLEAR_DSS_3_DATA_IN_8822C(x) ((x) & (~BITS_DSS_3_DATA_IN_8822C)) +#define BIT_GET_DSS_3_DATA_IN_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_3_DATA_IN_8822C) & BIT_MASK_DSS_3_DATA_IN_8822C) +#define BIT_SET_DSS_3_DATA_IN_8822C(x, v) \ + (BIT_CLEAR_DSS_3_DATA_IN_8822C(x) | BIT_DSS_3_DATA_IN_8822C(v)) + +/* 2 REG_SPEED_SENSOR5_8822C */ +#define BIT_DSS_3_READY_8822C BIT(31) +#define BIT_DSS_3_WSORT_GO_8822C BIT(30) + +#define BIT_SHIFT_DSS_3_COUNT_OUT_8822C 0 +#define BIT_MASK_DSS_3_COUNT_OUT_8822C 0xfffff +#define BIT_DSS_3_COUNT_OUT_8822C(x) \ + (((x) & BIT_MASK_DSS_3_COUNT_OUT_8822C) \ + << BIT_SHIFT_DSS_3_COUNT_OUT_8822C) +#define BITS_DSS_3_COUNT_OUT_8822C \ + (BIT_MASK_DSS_3_COUNT_OUT_8822C << BIT_SHIFT_DSS_3_COUNT_OUT_8822C) +#define BIT_CLEAR_DSS_3_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8822C)) +#define BIT_GET_DSS_3_COUNT_OUT_8822C(x) \ + (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8822C) & \ + BIT_MASK_DSS_3_COUNT_OUT_8822C) +#define BIT_SET_DSS_3_COUNT_OUT_8822C(x, v) \ + (BIT_CLEAR_DSS_3_COUNT_OUT_8822C(x) | BIT_DSS_3_COUNT_OUT_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_COUNTER_CTRL_8822C */ + +#define BIT_SHIFT_COUNTER_BASE_8822C 16 +#define BIT_MASK_COUNTER_BASE_8822C 0x1fff +#define BIT_COUNTER_BASE_8822C(x) \ + (((x) & BIT_MASK_COUNTER_BASE_8822C) << BIT_SHIFT_COUNTER_BASE_8822C) +#define BITS_COUNTER_BASE_8822C \ + (BIT_MASK_COUNTER_BASE_8822C << BIT_SHIFT_COUNTER_BASE_8822C) +#define BIT_CLEAR_COUNTER_BASE_8822C(x) ((x) & (~BITS_COUNTER_BASE_8822C)) +#define BIT_GET_COUNTER_BASE_8822C(x) \ + (((x) >> BIT_SHIFT_COUNTER_BASE_8822C) & BIT_MASK_COUNTER_BASE_8822C) +#define BIT_SET_COUNTER_BASE_8822C(x, v) \ + (BIT_CLEAR_COUNTER_BASE_8822C(x) | BIT_COUNTER_BASE_8822C(v)) + +#define BIT_EN_RTS_REQ_8822C BIT(9) +#define BIT_EN_EDCA_REQ_8822C BIT(8) +#define BIT_EN_PTCL_REQ_8822C BIT(7) +#define BIT_EN_SCH_REQ_8822C BIT(6) +#define BIT_USB_COUNT_EN_8822C BIT(5) +#define BIT_PCIE_COUNT_EN_8822C BIT(4) +#define BIT_RQPN_COUNT_EN_8822C BIT(3) +#define BIT_RDE_COUNT_EN_8822C BIT(2) +#define BIT_TDE_COUNT_EN_8822C BIT(1) +#define BIT_DISABLE_COUNTER_8822C BIT(0) + +/* 2 REG_COUNTER_THRESHOLD_8822C */ +#define BIT_SEL_ALL_MACID_8822C BIT(31) + +#define BIT_SHIFT_COUNTER_MACID_8822C 24 +#define BIT_MASK_COUNTER_MACID_8822C 0x7f +#define BIT_COUNTER_MACID_8822C(x) \ + (((x) & BIT_MASK_COUNTER_MACID_8822C) << BIT_SHIFT_COUNTER_MACID_8822C) +#define BITS_COUNTER_MACID_8822C \ + (BIT_MASK_COUNTER_MACID_8822C << BIT_SHIFT_COUNTER_MACID_8822C) +#define BIT_CLEAR_COUNTER_MACID_8822C(x) ((x) & (~BITS_COUNTER_MACID_8822C)) +#define BIT_GET_COUNTER_MACID_8822C(x) \ + (((x) >> BIT_SHIFT_COUNTER_MACID_8822C) & BIT_MASK_COUNTER_MACID_8822C) +#define BIT_SET_COUNTER_MACID_8822C(x, v) \ + (BIT_CLEAR_COUNTER_MACID_8822C(x) | BIT_COUNTER_MACID_8822C(v)) + +#define BIT_SHIFT_AGG_VALUE2_8822C 16 +#define BIT_MASK_AGG_VALUE2_8822C 0x7f +#define BIT_AGG_VALUE2_8822C(x) \ + (((x) & BIT_MASK_AGG_VALUE2_8822C) << BIT_SHIFT_AGG_VALUE2_8822C) +#define BITS_AGG_VALUE2_8822C \ + (BIT_MASK_AGG_VALUE2_8822C << BIT_SHIFT_AGG_VALUE2_8822C) +#define BIT_CLEAR_AGG_VALUE2_8822C(x) ((x) & (~BITS_AGG_VALUE2_8822C)) +#define BIT_GET_AGG_VALUE2_8822C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE2_8822C) & BIT_MASK_AGG_VALUE2_8822C) +#define BIT_SET_AGG_VALUE2_8822C(x, v) \ + (BIT_CLEAR_AGG_VALUE2_8822C(x) | BIT_AGG_VALUE2_8822C(v)) + +#define BIT_SHIFT_AGG_VALUE1_8822C 8 +#define BIT_MASK_AGG_VALUE1_8822C 0x7f +#define BIT_AGG_VALUE1_8822C(x) \ + (((x) & BIT_MASK_AGG_VALUE1_8822C) << BIT_SHIFT_AGG_VALUE1_8822C) +#define BITS_AGG_VALUE1_8822C \ + (BIT_MASK_AGG_VALUE1_8822C << BIT_SHIFT_AGG_VALUE1_8822C) +#define BIT_CLEAR_AGG_VALUE1_8822C(x) ((x) & (~BITS_AGG_VALUE1_8822C)) +#define BIT_GET_AGG_VALUE1_8822C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE1_8822C) & BIT_MASK_AGG_VALUE1_8822C) +#define BIT_SET_AGG_VALUE1_8822C(x, v) \ + (BIT_CLEAR_AGG_VALUE1_8822C(x) | BIT_AGG_VALUE1_8822C(v)) + +#define BIT_SHIFT_AGG_VALUE0_8822C 0 +#define BIT_MASK_AGG_VALUE0_8822C 0x7f +#define BIT_AGG_VALUE0_8822C(x) \ + (((x) & BIT_MASK_AGG_VALUE0_8822C) << BIT_SHIFT_AGG_VALUE0_8822C) +#define BITS_AGG_VALUE0_8822C \ + (BIT_MASK_AGG_VALUE0_8822C << BIT_SHIFT_AGG_VALUE0_8822C) +#define BIT_CLEAR_AGG_VALUE0_8822C(x) ((x) & (~BITS_AGG_VALUE0_8822C)) +#define BIT_GET_AGG_VALUE0_8822C(x) \ + (((x) >> BIT_SHIFT_AGG_VALUE0_8822C) & BIT_MASK_AGG_VALUE0_8822C) +#define BIT_SET_AGG_VALUE0_8822C(x, v) \ + (BIT_CLEAR_AGG_VALUE0_8822C(x) | BIT_AGG_VALUE0_8822C(v)) + +/* 2 REG_COUNTER_SET_8822C */ + +#define BIT_SHIFT_REQUEST_RESET_8822C 16 +#define BIT_MASK_REQUEST_RESET_8822C 0xffff +#define BIT_REQUEST_RESET_8822C(x) \ + (((x) & BIT_MASK_REQUEST_RESET_8822C) << BIT_SHIFT_REQUEST_RESET_8822C) +#define BITS_REQUEST_RESET_8822C \ + (BIT_MASK_REQUEST_RESET_8822C << BIT_SHIFT_REQUEST_RESET_8822C) +#define BIT_CLEAR_REQUEST_RESET_8822C(x) ((x) & (~BITS_REQUEST_RESET_8822C)) +#define BIT_GET_REQUEST_RESET_8822C(x) \ + (((x) >> BIT_SHIFT_REQUEST_RESET_8822C) & BIT_MASK_REQUEST_RESET_8822C) +#define BIT_SET_REQUEST_RESET_8822C(x, v) \ + (BIT_CLEAR_REQUEST_RESET_8822C(x) | BIT_REQUEST_RESET_8822C(v)) + +#define BIT_SHIFT_REQUEST_START_8822C 0 +#define BIT_MASK_REQUEST_START_8822C 0xffff +#define BIT_REQUEST_START_8822C(x) \ + (((x) & BIT_MASK_REQUEST_START_8822C) << BIT_SHIFT_REQUEST_START_8822C) +#define BITS_REQUEST_START_8822C \ + (BIT_MASK_REQUEST_START_8822C << BIT_SHIFT_REQUEST_START_8822C) +#define BIT_CLEAR_REQUEST_START_8822C(x) ((x) & (~BITS_REQUEST_START_8822C)) +#define BIT_GET_REQUEST_START_8822C(x) \ + (((x) >> BIT_SHIFT_REQUEST_START_8822C) & BIT_MASK_REQUEST_START_8822C) +#define BIT_SET_REQUEST_START_8822C(x, v) \ + (BIT_CLEAR_REQUEST_START_8822C(x) | BIT_REQUEST_START_8822C(v)) + +/* 2 REG_COUNTER_OVERFLOW_8822C */ + +#define BIT_SHIFT_CNT_OVF_REG_8822C 0 +#define BIT_MASK_CNT_OVF_REG_8822C 0xffff +#define BIT_CNT_OVF_REG_8822C(x) \ + (((x) & BIT_MASK_CNT_OVF_REG_8822C) << BIT_SHIFT_CNT_OVF_REG_8822C) +#define BITS_CNT_OVF_REG_8822C \ + (BIT_MASK_CNT_OVF_REG_8822C << BIT_SHIFT_CNT_OVF_REG_8822C) +#define BIT_CLEAR_CNT_OVF_REG_8822C(x) ((x) & (~BITS_CNT_OVF_REG_8822C)) +#define BIT_GET_CNT_OVF_REG_8822C(x) \ + (((x) >> BIT_SHIFT_CNT_OVF_REG_8822C) & BIT_MASK_CNT_OVF_REG_8822C) +#define BIT_SET_CNT_OVF_REG_8822C(x, v) \ + (BIT_CLEAR_CNT_OVF_REG_8822C(x) | BIT_CNT_OVF_REG_8822C(v)) + +/* 2 REG_TXDMA_LEN_THRESHOLD_8822C */ + +#define BIT_SHIFT_TDE_LEN_TH1_8822C 16 +#define BIT_MASK_TDE_LEN_TH1_8822C 0xffff +#define BIT_TDE_LEN_TH1_8822C(x) \ + (((x) & BIT_MASK_TDE_LEN_TH1_8822C) << BIT_SHIFT_TDE_LEN_TH1_8822C) +#define BITS_TDE_LEN_TH1_8822C \ + (BIT_MASK_TDE_LEN_TH1_8822C << BIT_SHIFT_TDE_LEN_TH1_8822C) +#define BIT_CLEAR_TDE_LEN_TH1_8822C(x) ((x) & (~BITS_TDE_LEN_TH1_8822C)) +#define BIT_GET_TDE_LEN_TH1_8822C(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH1_8822C) & BIT_MASK_TDE_LEN_TH1_8822C) +#define BIT_SET_TDE_LEN_TH1_8822C(x, v) \ + (BIT_CLEAR_TDE_LEN_TH1_8822C(x) | BIT_TDE_LEN_TH1_8822C(v)) + +#define BIT_SHIFT_TDE_LEN_TH0_8822C 0 +#define BIT_MASK_TDE_LEN_TH0_8822C 0xffff +#define BIT_TDE_LEN_TH0_8822C(x) \ + (((x) & BIT_MASK_TDE_LEN_TH0_8822C) << BIT_SHIFT_TDE_LEN_TH0_8822C) +#define BITS_TDE_LEN_TH0_8822C \ + (BIT_MASK_TDE_LEN_TH0_8822C << BIT_SHIFT_TDE_LEN_TH0_8822C) +#define BIT_CLEAR_TDE_LEN_TH0_8822C(x) ((x) & (~BITS_TDE_LEN_TH0_8822C)) +#define BIT_GET_TDE_LEN_TH0_8822C(x) \ + (((x) >> BIT_SHIFT_TDE_LEN_TH0_8822C) & BIT_MASK_TDE_LEN_TH0_8822C) +#define BIT_SET_TDE_LEN_TH0_8822C(x, v) \ + (BIT_CLEAR_TDE_LEN_TH0_8822C(x) | BIT_TDE_LEN_TH0_8822C(v)) + +/* 2 REG_RXDMA_LEN_THRESHOLD_8822C */ + +#define BIT_SHIFT_RDE_LEN_TH1_8822C 16 +#define BIT_MASK_RDE_LEN_TH1_8822C 0xffff +#define BIT_RDE_LEN_TH1_8822C(x) \ + (((x) & BIT_MASK_RDE_LEN_TH1_8822C) << BIT_SHIFT_RDE_LEN_TH1_8822C) +#define BITS_RDE_LEN_TH1_8822C \ + (BIT_MASK_RDE_LEN_TH1_8822C << BIT_SHIFT_RDE_LEN_TH1_8822C) +#define BIT_CLEAR_RDE_LEN_TH1_8822C(x) ((x) & (~BITS_RDE_LEN_TH1_8822C)) +#define BIT_GET_RDE_LEN_TH1_8822C(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH1_8822C) & BIT_MASK_RDE_LEN_TH1_8822C) +#define BIT_SET_RDE_LEN_TH1_8822C(x, v) \ + (BIT_CLEAR_RDE_LEN_TH1_8822C(x) | BIT_RDE_LEN_TH1_8822C(v)) + +#define BIT_SHIFT_RDE_LEN_TH0_8822C 0 +#define BIT_MASK_RDE_LEN_TH0_8822C 0xffff +#define BIT_RDE_LEN_TH0_8822C(x) \ + (((x) & BIT_MASK_RDE_LEN_TH0_8822C) << BIT_SHIFT_RDE_LEN_TH0_8822C) +#define BITS_RDE_LEN_TH0_8822C \ + (BIT_MASK_RDE_LEN_TH0_8822C << BIT_SHIFT_RDE_LEN_TH0_8822C) +#define BIT_CLEAR_RDE_LEN_TH0_8822C(x) ((x) & (~BITS_RDE_LEN_TH0_8822C)) +#define BIT_GET_RDE_LEN_TH0_8822C(x) \ + (((x) >> BIT_SHIFT_RDE_LEN_TH0_8822C) & BIT_MASK_RDE_LEN_TH0_8822C) +#define BIT_SET_RDE_LEN_TH0_8822C(x, v) \ + (BIT_CLEAR_RDE_LEN_TH0_8822C(x) | BIT_RDE_LEN_TH0_8822C(v)) + +/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8822C */ + +#define BIT_SHIFT_COUNT_INT_SEL_8822C 16 +#define BIT_MASK_COUNT_INT_SEL_8822C 0x3 +#define BIT_COUNT_INT_SEL_8822C(x) \ + (((x) & BIT_MASK_COUNT_INT_SEL_8822C) << BIT_SHIFT_COUNT_INT_SEL_8822C) +#define BITS_COUNT_INT_SEL_8822C \ + (BIT_MASK_COUNT_INT_SEL_8822C << BIT_SHIFT_COUNT_INT_SEL_8822C) +#define BIT_CLEAR_COUNT_INT_SEL_8822C(x) ((x) & (~BITS_COUNT_INT_SEL_8822C)) +#define BIT_GET_COUNT_INT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_COUNT_INT_SEL_8822C) & BIT_MASK_COUNT_INT_SEL_8822C) +#define BIT_SET_COUNT_INT_SEL_8822C(x, v) \ + (BIT_CLEAR_COUNT_INT_SEL_8822C(x) | BIT_COUNT_INT_SEL_8822C(v)) + +#define BIT_SHIFT_EXEC_TIME_TH_8822C 0 +#define BIT_MASK_EXEC_TIME_TH_8822C 0xffff +#define BIT_EXEC_TIME_TH_8822C(x) \ + (((x) & BIT_MASK_EXEC_TIME_TH_8822C) << BIT_SHIFT_EXEC_TIME_TH_8822C) +#define BITS_EXEC_TIME_TH_8822C \ + (BIT_MASK_EXEC_TIME_TH_8822C << BIT_SHIFT_EXEC_TIME_TH_8822C) +#define BIT_CLEAR_EXEC_TIME_TH_8822C(x) ((x) & (~BITS_EXEC_TIME_TH_8822C)) +#define BIT_GET_EXEC_TIME_TH_8822C(x) \ + (((x) >> BIT_SHIFT_EXEC_TIME_TH_8822C) & BIT_MASK_EXEC_TIME_TH_8822C) +#define BIT_SET_EXEC_TIME_TH_8822C(x, v) \ + (BIT_CLEAR_EXEC_TIME_TH_8822C(x) | BIT_EXEC_TIME_TH_8822C(v)) + +/* 2 REG_FT2IMR_8822C */ +#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822C BIT(31) +#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8822C BIT(30) +#define BIT_FS_CLI3_TRIGGER_PKT_EN_8822C BIT(29) +#define BIT_FS_CLI3_EOSP_INT_EN_8822C BIT(28) +#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8822C BIT(27) +#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8822C BIT(26) +#define BIT_FS_CLI2_TRIGGER_PKT_EN_8822C BIT(25) +#define BIT_FS_CLI2_EOSP_INT_EN_8822C BIT(24) +#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8822C BIT(23) +#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8822C BIT(22) +#define BIT_FS_CLI1_TRIGGER_PKT_EN_8822C BIT(21) +#define BIT_FS_CLI1_EOSP_INT_EN_8822C BIT(20) +#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8822C BIT(19) +#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8822C BIT(18) +#define BIT_FS_CLI0_TRIGGER_PKT_EN_8822C BIT(17) +#define BIT_FS_CLI0_EOSP_INT_EN_8822C BIT(16) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8822C BIT(9) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8822C BIT(8) +#define BIT_FS_CLI3_TX_NULL1_INT_EN_8822C BIT(7) +#define BIT_FS_CLI3_TX_NULL0_INT_EN_8822C BIT(6) +#define BIT_FS_CLI2_TX_NULL1_INT_EN_8822C BIT(5) +#define BIT_FS_CLI2_TX_NULL0_INT_EN_8822C BIT(4) +#define BIT_FS_CLI1_TX_NULL1_INT_EN_8822C BIT(3) +#define BIT_FS_CLI1_TX_NULL0_INT_EN_8822C BIT(2) +#define BIT_FS_CLI0_TX_NULL1_INT_EN_8822C BIT(1) +#define BIT_FS_CLI0_TX_NULL0_INT_EN_8822C BIT(0) + +/* 2 REG_FT2ISR_8822C */ +#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8822C BIT(31) +#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8822C BIT(30) +#define BIT_FS_CLI3_TRIGGER_PKT_INT_8822C BIT(29) +#define BIT_FS_CLI3_EOSP_INT_8822C BIT(28) +#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8822C BIT(27) +#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8822C BIT(26) +#define BIT_FS_CLI2_TRIGGER_PKT_INT_8822C BIT(25) +#define BIT_FS_CLI2_EOSP_INT_8822C BIT(24) +#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8822C BIT(23) +#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8822C BIT(22) +#define BIT_FS_CLI1_TRIGGER_PKT_INT_8822C BIT(21) +#define BIT_FS_CLI1_EOSP_INT_8822C BIT(20) +#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8822C BIT(19) +#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8822C BIT(18) +#define BIT_FS_CLI0_TRIGGER_PKT_INT_8822C BIT(17) +#define BIT_FS_CLI0_EOSP_INT_8822C BIT(16) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8822C BIT(9) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8822C BIT(8) +#define BIT_FS_CLI3_TX_NULL1_INT_8822C BIT(7) +#define BIT_FS_CLI3_TX_NULL0_INT_8822C BIT(6) +#define BIT_FS_CLI2_TX_NULL1_INT_8822C BIT(5) +#define BIT_FS_CLI2_TX_NULL0_INT_8822C BIT(4) +#define BIT_FS_CLI1_TX_NULL1_INT_8822C BIT(3) +#define BIT_FS_CLI1_TX_NULL0_INT_8822C BIT(2) +#define BIT_FS_CLI0_TX_NULL1_INT_8822C BIT(1) +#define BIT_FS_CLI0_TX_NULL0_INT_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_MSG2_8822C */ + +#define BIT_SHIFT_FW_MSG2_8822C 0 +#define BIT_MASK_FW_MSG2_8822C 0xffffffffL +#define BIT_FW_MSG2_8822C(x) \ + (((x) & BIT_MASK_FW_MSG2_8822C) << BIT_SHIFT_FW_MSG2_8822C) +#define BITS_FW_MSG2_8822C (BIT_MASK_FW_MSG2_8822C << BIT_SHIFT_FW_MSG2_8822C) +#define BIT_CLEAR_FW_MSG2_8822C(x) ((x) & (~BITS_FW_MSG2_8822C)) +#define BIT_GET_FW_MSG2_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG2_8822C) & BIT_MASK_FW_MSG2_8822C) +#define BIT_SET_FW_MSG2_8822C(x, v) \ + (BIT_CLEAR_FW_MSG2_8822C(x) | BIT_FW_MSG2_8822C(v)) + +/* 2 REG_MSG3_8822C */ + +#define BIT_SHIFT_FW_MSG3_8822C 0 +#define BIT_MASK_FW_MSG3_8822C 0xffffffffL +#define BIT_FW_MSG3_8822C(x) \ + (((x) & BIT_MASK_FW_MSG3_8822C) << BIT_SHIFT_FW_MSG3_8822C) +#define BITS_FW_MSG3_8822C (BIT_MASK_FW_MSG3_8822C << BIT_SHIFT_FW_MSG3_8822C) +#define BIT_CLEAR_FW_MSG3_8822C(x) ((x) & (~BITS_FW_MSG3_8822C)) +#define BIT_GET_FW_MSG3_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG3_8822C) & BIT_MASK_FW_MSG3_8822C) +#define BIT_SET_FW_MSG3_8822C(x, v) \ + (BIT_CLEAR_FW_MSG3_8822C(x) | BIT_FW_MSG3_8822C(v)) + +/* 2 REG_MSG4_8822C */ + +#define BIT_SHIFT_FW_MSG4_8822C 0 +#define BIT_MASK_FW_MSG4_8822C 0xffffffffL +#define BIT_FW_MSG4_8822C(x) \ + (((x) & BIT_MASK_FW_MSG4_8822C) << BIT_SHIFT_FW_MSG4_8822C) +#define BITS_FW_MSG4_8822C (BIT_MASK_FW_MSG4_8822C << BIT_SHIFT_FW_MSG4_8822C) +#define BIT_CLEAR_FW_MSG4_8822C(x) ((x) & (~BITS_FW_MSG4_8822C)) +#define BIT_GET_FW_MSG4_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG4_8822C) & BIT_MASK_FW_MSG4_8822C) +#define BIT_SET_FW_MSG4_8822C(x, v) \ + (BIT_CLEAR_FW_MSG4_8822C(x) | BIT_FW_MSG4_8822C(v)) + +/* 2 REG_MSG5_8822C */ + +#define BIT_SHIFT_FW_MSG5_8822C 0 +#define BIT_MASK_FW_MSG5_8822C 0xffffffffL +#define BIT_FW_MSG5_8822C(x) \ + (((x) & BIT_MASK_FW_MSG5_8822C) << BIT_SHIFT_FW_MSG5_8822C) +#define BITS_FW_MSG5_8822C (BIT_MASK_FW_MSG5_8822C << BIT_SHIFT_FW_MSG5_8822C) +#define BIT_CLEAR_FW_MSG5_8822C(x) ((x) & (~BITS_FW_MSG5_8822C)) +#define BIT_GET_FW_MSG5_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG5_8822C) & BIT_MASK_FW_MSG5_8822C) +#define BIT_SET_FW_MSG5_8822C(x, v) \ + (BIT_CLEAR_FW_MSG5_8822C(x) | BIT_FW_MSG5_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_FIFOPAGE_CTRL_1_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C 16 +#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C 0xff +#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822C(x) \ + (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C) \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C) +#define BITS_TX_OQT_HE_FREE_SPACE_V1_8822C \ + (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C \ + << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C) +#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822C(x) \ + ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8822C)) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C) & \ + BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C) +#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8822C(x, v) \ + (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822C(x) | \ + BIT_TX_OQT_HE_FREE_SPACE_V1_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C 0 +#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C 0xff +#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822C(x) \ + (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C) \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C) +#define BITS_TX_OQT_NL_FREE_SPACE_V1_8822C \ + (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C \ + << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C) +#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822C(x) \ + ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8822C)) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C) & \ + BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C) +#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8822C(x, v) \ + (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822C(x) | \ + BIT_TX_OQT_NL_FREE_SPACE_V1_8822C(v)) + +/* 2 REG_FIFOPAGE_CTRL_2_8822C */ +#define BIT_BCN_VALID_1_V1_8822C BIT(31) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_BCN_HEAD_1_V1_8822C 16 +#define BIT_MASK_BCN_HEAD_1_V1_8822C 0xfff +#define BIT_BCN_HEAD_1_V1_8822C(x) \ + (((x) & BIT_MASK_BCN_HEAD_1_V1_8822C) << BIT_SHIFT_BCN_HEAD_1_V1_8822C) +#define BITS_BCN_HEAD_1_V1_8822C \ + (BIT_MASK_BCN_HEAD_1_V1_8822C << BIT_SHIFT_BCN_HEAD_1_V1_8822C) +#define BIT_CLEAR_BCN_HEAD_1_V1_8822C(x) ((x) & (~BITS_BCN_HEAD_1_V1_8822C)) +#define BIT_GET_BCN_HEAD_1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822C) & BIT_MASK_BCN_HEAD_1_V1_8822C) +#define BIT_SET_BCN_HEAD_1_V1_8822C(x, v) \ + (BIT_CLEAR_BCN_HEAD_1_V1_8822C(x) | BIT_BCN_HEAD_1_V1_8822C(v)) + +#define BIT_BCN_VALID_V1_8822C BIT(15) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_BCN_HEAD_V1_8822C 0 +#define BIT_MASK_BCN_HEAD_V1_8822C 0xfff +#define BIT_BCN_HEAD_V1_8822C(x) \ + (((x) & BIT_MASK_BCN_HEAD_V1_8822C) << BIT_SHIFT_BCN_HEAD_V1_8822C) +#define BITS_BCN_HEAD_V1_8822C \ + (BIT_MASK_BCN_HEAD_V1_8822C << BIT_SHIFT_BCN_HEAD_V1_8822C) +#define BIT_CLEAR_BCN_HEAD_V1_8822C(x) ((x) & (~BITS_BCN_HEAD_V1_8822C)) +#define BIT_GET_BCN_HEAD_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_HEAD_V1_8822C) & BIT_MASK_BCN_HEAD_V1_8822C) +#define BIT_SET_BCN_HEAD_V1_8822C(x, v) \ + (BIT_CLEAR_BCN_HEAD_V1_8822C(x) | BIT_BCN_HEAD_V1_8822C(v)) + +/* 2 REG_AUTO_LLT_V1_8822C */ + +#define BIT_SHIFT_MAX_TX_PKT_V1_8822C 24 +#define BIT_MASK_MAX_TX_PKT_V1_8822C 0xff +#define BIT_MAX_TX_PKT_V1_8822C(x) \ + (((x) & BIT_MASK_MAX_TX_PKT_V1_8822C) << BIT_SHIFT_MAX_TX_PKT_V1_8822C) +#define BITS_MAX_TX_PKT_V1_8822C \ + (BIT_MASK_MAX_TX_PKT_V1_8822C << BIT_SHIFT_MAX_TX_PKT_V1_8822C) +#define BIT_CLEAR_MAX_TX_PKT_V1_8822C(x) ((x) & (~BITS_MAX_TX_PKT_V1_8822C)) +#define BIT_GET_MAX_TX_PKT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_TX_PKT_V1_8822C) & BIT_MASK_MAX_TX_PKT_V1_8822C) +#define BIT_SET_MAX_TX_PKT_V1_8822C(x, v) \ + (BIT_CLEAR_MAX_TX_PKT_V1_8822C(x) | BIT_MAX_TX_PKT_V1_8822C(v)) + +#define BIT_TDE_ERROR_STOP_V1_8822C BIT(23) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_LLT_FREE_PAGE_V2_8822C 8 +#define BIT_MASK_LLT_FREE_PAGE_V2_8822C 0xfff +#define BIT_LLT_FREE_PAGE_V2_8822C(x) \ + (((x) & BIT_MASK_LLT_FREE_PAGE_V2_8822C) \ + << BIT_SHIFT_LLT_FREE_PAGE_V2_8822C) +#define BITS_LLT_FREE_PAGE_V2_8822C \ + (BIT_MASK_LLT_FREE_PAGE_V2_8822C << BIT_SHIFT_LLT_FREE_PAGE_V2_8822C) +#define BIT_CLEAR_LLT_FREE_PAGE_V2_8822C(x) \ + ((x) & (~BITS_LLT_FREE_PAGE_V2_8822C)) +#define BIT_GET_LLT_FREE_PAGE_V2_8822C(x) \ + (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2_8822C) & \ + BIT_MASK_LLT_FREE_PAGE_V2_8822C) +#define BIT_SET_LLT_FREE_PAGE_V2_8822C(x, v) \ + (BIT_CLEAR_LLT_FREE_PAGE_V2_8822C(x) | BIT_LLT_FREE_PAGE_V2_8822C(v)) + +#define BIT_SHIFT_BLK_DESC_NUM_8822C 4 +#define BIT_MASK_BLK_DESC_NUM_8822C 0xf +#define BIT_BLK_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_BLK_DESC_NUM_8822C) << BIT_SHIFT_BLK_DESC_NUM_8822C) +#define BITS_BLK_DESC_NUM_8822C \ + (BIT_MASK_BLK_DESC_NUM_8822C << BIT_SHIFT_BLK_DESC_NUM_8822C) +#define BIT_CLEAR_BLK_DESC_NUM_8822C(x) ((x) & (~BITS_BLK_DESC_NUM_8822C)) +#define BIT_GET_BLK_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_BLK_DESC_NUM_8822C) & BIT_MASK_BLK_DESC_NUM_8822C) +#define BIT_SET_BLK_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_BLK_DESC_NUM_8822C(x) | BIT_BLK_DESC_NUM_8822C(v)) + +#define BIT_R_BCN_HEAD_SEL_8822C BIT(3) +#define BIT_R_EN_BCN_SW_HEAD_SEL_8822C BIT(2) +#define BIT_LLT_DBG_SEL_8822C BIT(1) +#define BIT_AUTO_INIT_LLT_V1_8822C BIT(0) + +/* 2 REG_TXDMA_OFFSET_CHK_8822C */ +#define BIT_EM_CHKSUM_FIN_8822C BIT(31) +#define BIT_EMN_PCIE_DMA_MOD_8822C BIT(30) +#define BIT_EN_TXQUE_CLR_8822C BIT(29) +#define BIT_EN_PCIE_FIFO_MODE_8822C BIT(28) + +#define BIT_SHIFT_PG_UNDER_TH_V1_8822C 16 +#define BIT_MASK_PG_UNDER_TH_V1_8822C 0xfff +#define BIT_PG_UNDER_TH_V1_8822C(x) \ + (((x) & BIT_MASK_PG_UNDER_TH_V1_8822C) \ + << BIT_SHIFT_PG_UNDER_TH_V1_8822C) +#define BITS_PG_UNDER_TH_V1_8822C \ + (BIT_MASK_PG_UNDER_TH_V1_8822C << BIT_SHIFT_PG_UNDER_TH_V1_8822C) +#define BIT_CLEAR_PG_UNDER_TH_V1_8822C(x) ((x) & (~BITS_PG_UNDER_TH_V1_8822C)) +#define BIT_GET_PG_UNDER_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822C) & \ + BIT_MASK_PG_UNDER_TH_V1_8822C) +#define BIT_SET_PG_UNDER_TH_V1_8822C(x, v) \ + (BIT_CLEAR_PG_UNDER_TH_V1_8822C(x) | BIT_PG_UNDER_TH_V1_8822C(v)) + +#define BIT_R_EN_RESET_RESTORE_H2C_8822C BIT(15) +#define BIT_SDIO_TDE_FINISH_8822C BIT(14) +#define BIT_SDIO_TXDESC_CHKSUM_EN_8822C BIT(13) +#define BIT_RST_RDPTR_8822C BIT(12) +#define BIT_RST_WRPTR_8822C BIT(11) +#define BIT_CHK_PG_TH_EN_8822C BIT(10) +#define BIT_DROP_DATA_EN_8822C BIT(9) +#define BIT_CHECK_OFFSET_EN_8822C BIT(8) + +#define BIT_SHIFT_CHECK_OFFSET_8822C 0 +#define BIT_MASK_CHECK_OFFSET_8822C 0xff +#define BIT_CHECK_OFFSET_8822C(x) \ + (((x) & BIT_MASK_CHECK_OFFSET_8822C) << BIT_SHIFT_CHECK_OFFSET_8822C) +#define BITS_CHECK_OFFSET_8822C \ + (BIT_MASK_CHECK_OFFSET_8822C << BIT_SHIFT_CHECK_OFFSET_8822C) +#define BIT_CLEAR_CHECK_OFFSET_8822C(x) ((x) & (~BITS_CHECK_OFFSET_8822C)) +#define BIT_GET_CHECK_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_CHECK_OFFSET_8822C) & BIT_MASK_CHECK_OFFSET_8822C) +#define BIT_SET_CHECK_OFFSET_8822C(x, v) \ + (BIT_CLEAR_CHECK_OFFSET_8822C(x) | BIT_CHECK_OFFSET_8822C(v)) + +/* 2 REG_TXDMA_STATUS_8822C */ +#define BIT_TXPKTBUF_REQ_ERR_8822C BIT(18) +#define BIT_HI_OQT_UDN_8822C BIT(17) +#define BIT_HI_OQT_OVF_8822C BIT(16) +#define BIT_PAYLOAD_CHKSUM_ERR_8822C BIT(15) +#define BIT_PAYLOAD_UDN_8822C BIT(14) +#define BIT_PAYLOAD_OVF_8822C BIT(13) +#define BIT_DSC_CHKSUM_FAIL_8822C BIT(12) +#define BIT_UNKNOWN_QSEL_8822C BIT(11) +#define BIT_EP_QSEL_DIFF_8822C BIT(10) +#define BIT_TX_OFFS_UNMATCH_8822C BIT(9) +#define BIT_TXOQT_UDN_8822C BIT(8) +#define BIT_TXOQT_OVF_8822C BIT(7) +#define BIT_TXDMA_SFF_UDN_8822C BIT(6) +#define BIT_TXDMA_SFF_OVF_8822C BIT(5) +#define BIT_LLT_NULL_PG_8822C BIT(4) +#define BIT_PAGE_UDN_8822C BIT(3) +#define BIT_PAGE_OVF_8822C BIT(2) +#define BIT_TXFF_PG_UDN_8822C BIT(1) +#define BIT_TXFF_PG_OVF_8822C BIT(0) + +/* 2 REG_TX_DMA_DBG_8822C */ + +/* 2 REG_TQPNT1_8822C */ +#define BIT_HPQ_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_HPQ_HIGH_TH_V1_8822C 16 +#define BIT_MASK_HPQ_HIGH_TH_V1_8822C 0xfff +#define BIT_HPQ_HIGH_TH_V1_8822C(x) \ + (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822C) \ + << BIT_SHIFT_HPQ_HIGH_TH_V1_8822C) +#define BITS_HPQ_HIGH_TH_V1_8822C \ + (BIT_MASK_HPQ_HIGH_TH_V1_8822C << BIT_SHIFT_HPQ_HIGH_TH_V1_8822C) +#define BIT_CLEAR_HPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8822C)) +#define BIT_GET_HPQ_HIGH_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822C) & \ + BIT_MASK_HPQ_HIGH_TH_V1_8822C) +#define BIT_SET_HPQ_HIGH_TH_V1_8822C(x, v) \ + (BIT_CLEAR_HPQ_HIGH_TH_V1_8822C(x) | BIT_HPQ_HIGH_TH_V1_8822C(v)) + +#define BIT_SHIFT_HPQ_LOW_TH_V1_8822C 0 +#define BIT_MASK_HPQ_LOW_TH_V1_8822C 0xfff +#define BIT_HPQ_LOW_TH_V1_8822C(x) \ + (((x) & BIT_MASK_HPQ_LOW_TH_V1_8822C) << BIT_SHIFT_HPQ_LOW_TH_V1_8822C) +#define BITS_HPQ_LOW_TH_V1_8822C \ + (BIT_MASK_HPQ_LOW_TH_V1_8822C << BIT_SHIFT_HPQ_LOW_TH_V1_8822C) +#define BIT_CLEAR_HPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8822C)) +#define BIT_GET_HPQ_LOW_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822C) & BIT_MASK_HPQ_LOW_TH_V1_8822C) +#define BIT_SET_HPQ_LOW_TH_V1_8822C(x, v) \ + (BIT_CLEAR_HPQ_LOW_TH_V1_8822C(x) | BIT_HPQ_LOW_TH_V1_8822C(v)) + +/* 2 REG_TQPNT2_8822C */ +#define BIT_NPQ_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_NPQ_HIGH_TH_V1_8822C 16 +#define BIT_MASK_NPQ_HIGH_TH_V1_8822C 0xfff +#define BIT_NPQ_HIGH_TH_V1_8822C(x) \ + (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822C) \ + << BIT_SHIFT_NPQ_HIGH_TH_V1_8822C) +#define BITS_NPQ_HIGH_TH_V1_8822C \ + (BIT_MASK_NPQ_HIGH_TH_V1_8822C << BIT_SHIFT_NPQ_HIGH_TH_V1_8822C) +#define BIT_CLEAR_NPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8822C)) +#define BIT_GET_NPQ_HIGH_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822C) & \ + BIT_MASK_NPQ_HIGH_TH_V1_8822C) +#define BIT_SET_NPQ_HIGH_TH_V1_8822C(x, v) \ + (BIT_CLEAR_NPQ_HIGH_TH_V1_8822C(x) | BIT_NPQ_HIGH_TH_V1_8822C(v)) + +#define BIT_SHIFT_NPQ_LOW_TH_V1_8822C 0 +#define BIT_MASK_NPQ_LOW_TH_V1_8822C 0xfff +#define BIT_NPQ_LOW_TH_V1_8822C(x) \ + (((x) & BIT_MASK_NPQ_LOW_TH_V1_8822C) << BIT_SHIFT_NPQ_LOW_TH_V1_8822C) +#define BITS_NPQ_LOW_TH_V1_8822C \ + (BIT_MASK_NPQ_LOW_TH_V1_8822C << BIT_SHIFT_NPQ_LOW_TH_V1_8822C) +#define BIT_CLEAR_NPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8822C)) +#define BIT_GET_NPQ_LOW_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822C) & BIT_MASK_NPQ_LOW_TH_V1_8822C) +#define BIT_SET_NPQ_LOW_TH_V1_8822C(x, v) \ + (BIT_CLEAR_NPQ_LOW_TH_V1_8822C(x) | BIT_NPQ_LOW_TH_V1_8822C(v)) + +/* 2 REG_TQPNT3_8822C */ +#define BIT_LPQ_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_LPQ_HIGH_TH_V1_8822C 16 +#define BIT_MASK_LPQ_HIGH_TH_V1_8822C 0xfff +#define BIT_LPQ_HIGH_TH_V1_8822C(x) \ + (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822C) \ + << BIT_SHIFT_LPQ_HIGH_TH_V1_8822C) +#define BITS_LPQ_HIGH_TH_V1_8822C \ + (BIT_MASK_LPQ_HIGH_TH_V1_8822C << BIT_SHIFT_LPQ_HIGH_TH_V1_8822C) +#define BIT_CLEAR_LPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8822C)) +#define BIT_GET_LPQ_HIGH_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822C) & \ + BIT_MASK_LPQ_HIGH_TH_V1_8822C) +#define BIT_SET_LPQ_HIGH_TH_V1_8822C(x, v) \ + (BIT_CLEAR_LPQ_HIGH_TH_V1_8822C(x) | BIT_LPQ_HIGH_TH_V1_8822C(v)) + +#define BIT_SHIFT_LPQ_LOW_TH_V1_8822C 0 +#define BIT_MASK_LPQ_LOW_TH_V1_8822C 0xfff +#define BIT_LPQ_LOW_TH_V1_8822C(x) \ + (((x) & BIT_MASK_LPQ_LOW_TH_V1_8822C) << BIT_SHIFT_LPQ_LOW_TH_V1_8822C) +#define BITS_LPQ_LOW_TH_V1_8822C \ + (BIT_MASK_LPQ_LOW_TH_V1_8822C << BIT_SHIFT_LPQ_LOW_TH_V1_8822C) +#define BIT_CLEAR_LPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8822C)) +#define BIT_GET_LPQ_LOW_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822C) & BIT_MASK_LPQ_LOW_TH_V1_8822C) +#define BIT_SET_LPQ_LOW_TH_V1_8822C(x, v) \ + (BIT_CLEAR_LPQ_LOW_TH_V1_8822C(x) | BIT_LPQ_LOW_TH_V1_8822C(v)) + +/* 2 REG_TQPNT4_8822C */ +#define BIT_EXQ_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_EXQ_HIGH_TH_V1_8822C 16 +#define BIT_MASK_EXQ_HIGH_TH_V1_8822C 0xfff +#define BIT_EXQ_HIGH_TH_V1_8822C(x) \ + (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822C) \ + << BIT_SHIFT_EXQ_HIGH_TH_V1_8822C) +#define BITS_EXQ_HIGH_TH_V1_8822C \ + (BIT_MASK_EXQ_HIGH_TH_V1_8822C << BIT_SHIFT_EXQ_HIGH_TH_V1_8822C) +#define BIT_CLEAR_EXQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8822C)) +#define BIT_GET_EXQ_HIGH_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822C) & \ + BIT_MASK_EXQ_HIGH_TH_V1_8822C) +#define BIT_SET_EXQ_HIGH_TH_V1_8822C(x, v) \ + (BIT_CLEAR_EXQ_HIGH_TH_V1_8822C(x) | BIT_EXQ_HIGH_TH_V1_8822C(v)) + +#define BIT_SHIFT_EXQ_LOW_TH_V1_8822C 0 +#define BIT_MASK_EXQ_LOW_TH_V1_8822C 0xfff +#define BIT_EXQ_LOW_TH_V1_8822C(x) \ + (((x) & BIT_MASK_EXQ_LOW_TH_V1_8822C) << BIT_SHIFT_EXQ_LOW_TH_V1_8822C) +#define BITS_EXQ_LOW_TH_V1_8822C \ + (BIT_MASK_EXQ_LOW_TH_V1_8822C << BIT_SHIFT_EXQ_LOW_TH_V1_8822C) +#define BIT_CLEAR_EXQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8822C)) +#define BIT_GET_EXQ_LOW_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822C) & BIT_MASK_EXQ_LOW_TH_V1_8822C) +#define BIT_SET_EXQ_LOW_TH_V1_8822C(x, v) \ + (BIT_CLEAR_EXQ_LOW_TH_V1_8822C(x) | BIT_EXQ_LOW_TH_V1_8822C(v)) + +/* 2 REG_RQPN_CTRL_1_8822C */ + +#define BIT_SHIFT_TXPKTNUM_H_V2_8822C 16 +#define BIT_MASK_TXPKTNUM_H_V2_8822C 0xfff +#define BIT_TXPKTNUM_H_V2_8822C(x) \ + (((x) & BIT_MASK_TXPKTNUM_H_V2_8822C) << BIT_SHIFT_TXPKTNUM_H_V2_8822C) +#define BITS_TXPKTNUM_H_V2_8822C \ + (BIT_MASK_TXPKTNUM_H_V2_8822C << BIT_SHIFT_TXPKTNUM_H_V2_8822C) +#define BIT_CLEAR_TXPKTNUM_H_V2_8822C(x) ((x) & (~BITS_TXPKTNUM_H_V2_8822C)) +#define BIT_GET_TXPKTNUM_H_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_H_V2_8822C) & BIT_MASK_TXPKTNUM_H_V2_8822C) +#define BIT_SET_TXPKTNUM_H_V2_8822C(x, v) \ + (BIT_CLEAR_TXPKTNUM_H_V2_8822C(x) | BIT_TXPKTNUM_H_V2_8822C(v)) + +#define BIT_SHIFT_TXPKTNUM_V3_8822C 0 +#define BIT_MASK_TXPKTNUM_V3_8822C 0xfff +#define BIT_TXPKTNUM_V3_8822C(x) \ + (((x) & BIT_MASK_TXPKTNUM_V3_8822C) << BIT_SHIFT_TXPKTNUM_V3_8822C) +#define BITS_TXPKTNUM_V3_8822C \ + (BIT_MASK_TXPKTNUM_V3_8822C << BIT_SHIFT_TXPKTNUM_V3_8822C) +#define BIT_CLEAR_TXPKTNUM_V3_8822C(x) ((x) & (~BITS_TXPKTNUM_V3_8822C)) +#define BIT_GET_TXPKTNUM_V3_8822C(x) \ + (((x) >> BIT_SHIFT_TXPKTNUM_V3_8822C) & BIT_MASK_TXPKTNUM_V3_8822C) +#define BIT_SET_TXPKTNUM_V3_8822C(x, v) \ + (BIT_CLEAR_TXPKTNUM_V3_8822C(x) | BIT_TXPKTNUM_V3_8822C(v)) + +/* 2 REG_RQPN_CTRL_2_8822C */ +#define BIT_LD_RQPN_8822C BIT(31) +#define BIT_EXQ_PUBLIC_DIS_V1_8822C BIT(19) +#define BIT_NPQ_PUBLIC_DIS_V1_8822C BIT(18) +#define BIT_LPQ_PUBLIC_DIS_V1_8822C BIT(17) +#define BIT_HPQ_PUBLIC_DIS_V1_8822C BIT(16) +#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_8822C BIT(15) + +#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C 0 +#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C 0xfff +#define BIT_SDIO_TXAGG_ALIGN_SIZE_8822C(x) \ + (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C) \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C) +#define BITS_SDIO_TXAGG_ALIGN_SIZE_8822C \ + (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C \ + << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C) +#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8822C(x) \ + ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_8822C)) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C) & \ + BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C) +#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_8822C(x, v) \ + (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8822C(x) | \ + BIT_SDIO_TXAGG_ALIGN_SIZE_8822C(v)) + +/* 2 REG_FIFOPAGE_INFO_1_8822C */ + +#define BIT_SHIFT_HPQ_AVAL_PG_V1_8822C 16 +#define BIT_MASK_HPQ_AVAL_PG_V1_8822C 0xfff +#define BIT_HPQ_AVAL_PG_V1_8822C(x) \ + (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822C) \ + << BIT_SHIFT_HPQ_AVAL_PG_V1_8822C) +#define BITS_HPQ_AVAL_PG_V1_8822C \ + (BIT_MASK_HPQ_AVAL_PG_V1_8822C << BIT_SHIFT_HPQ_AVAL_PG_V1_8822C) +#define BIT_CLEAR_HPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8822C)) +#define BIT_GET_HPQ_AVAL_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822C) & \ + BIT_MASK_HPQ_AVAL_PG_V1_8822C) +#define BIT_SET_HPQ_AVAL_PG_V1_8822C(x, v) \ + (BIT_CLEAR_HPQ_AVAL_PG_V1_8822C(x) | BIT_HPQ_AVAL_PG_V1_8822C(v)) + +#define BIT_SHIFT_HPQ_V1_8822C 0 +#define BIT_MASK_HPQ_V1_8822C 0xfff +#define BIT_HPQ_V1_8822C(x) \ + (((x) & BIT_MASK_HPQ_V1_8822C) << BIT_SHIFT_HPQ_V1_8822C) +#define BITS_HPQ_V1_8822C (BIT_MASK_HPQ_V1_8822C << BIT_SHIFT_HPQ_V1_8822C) +#define BIT_CLEAR_HPQ_V1_8822C(x) ((x) & (~BITS_HPQ_V1_8822C)) +#define BIT_GET_HPQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HPQ_V1_8822C) & BIT_MASK_HPQ_V1_8822C) +#define BIT_SET_HPQ_V1_8822C(x, v) \ + (BIT_CLEAR_HPQ_V1_8822C(x) | BIT_HPQ_V1_8822C(v)) + +/* 2 REG_FIFOPAGE_INFO_2_8822C */ + +#define BIT_SHIFT_LPQ_AVAL_PG_V1_8822C 16 +#define BIT_MASK_LPQ_AVAL_PG_V1_8822C 0xfff +#define BIT_LPQ_AVAL_PG_V1_8822C(x) \ + (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822C) \ + << BIT_SHIFT_LPQ_AVAL_PG_V1_8822C) +#define BITS_LPQ_AVAL_PG_V1_8822C \ + (BIT_MASK_LPQ_AVAL_PG_V1_8822C << BIT_SHIFT_LPQ_AVAL_PG_V1_8822C) +#define BIT_CLEAR_LPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8822C)) +#define BIT_GET_LPQ_AVAL_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822C) & \ + BIT_MASK_LPQ_AVAL_PG_V1_8822C) +#define BIT_SET_LPQ_AVAL_PG_V1_8822C(x, v) \ + (BIT_CLEAR_LPQ_AVAL_PG_V1_8822C(x) | BIT_LPQ_AVAL_PG_V1_8822C(v)) + +#define BIT_SHIFT_LPQ_V1_8822C 0 +#define BIT_MASK_LPQ_V1_8822C 0xfff +#define BIT_LPQ_V1_8822C(x) \ + (((x) & BIT_MASK_LPQ_V1_8822C) << BIT_SHIFT_LPQ_V1_8822C) +#define BITS_LPQ_V1_8822C (BIT_MASK_LPQ_V1_8822C << BIT_SHIFT_LPQ_V1_8822C) +#define BIT_CLEAR_LPQ_V1_8822C(x) ((x) & (~BITS_LPQ_V1_8822C)) +#define BIT_GET_LPQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LPQ_V1_8822C) & BIT_MASK_LPQ_V1_8822C) +#define BIT_SET_LPQ_V1_8822C(x, v) \ + (BIT_CLEAR_LPQ_V1_8822C(x) | BIT_LPQ_V1_8822C(v)) + +/* 2 REG_FIFOPAGE_INFO_3_8822C */ + +#define BIT_SHIFT_NPQ_AVAL_PG_V1_8822C 16 +#define BIT_MASK_NPQ_AVAL_PG_V1_8822C 0xfff +#define BIT_NPQ_AVAL_PG_V1_8822C(x) \ + (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822C) \ + << BIT_SHIFT_NPQ_AVAL_PG_V1_8822C) +#define BITS_NPQ_AVAL_PG_V1_8822C \ + (BIT_MASK_NPQ_AVAL_PG_V1_8822C << BIT_SHIFT_NPQ_AVAL_PG_V1_8822C) +#define BIT_CLEAR_NPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8822C)) +#define BIT_GET_NPQ_AVAL_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822C) & \ + BIT_MASK_NPQ_AVAL_PG_V1_8822C) +#define BIT_SET_NPQ_AVAL_PG_V1_8822C(x, v) \ + (BIT_CLEAR_NPQ_AVAL_PG_V1_8822C(x) | BIT_NPQ_AVAL_PG_V1_8822C(v)) + +#define BIT_SHIFT_NPQ_V1_8822C 0 +#define BIT_MASK_NPQ_V1_8822C 0xfff +#define BIT_NPQ_V1_8822C(x) \ + (((x) & BIT_MASK_NPQ_V1_8822C) << BIT_SHIFT_NPQ_V1_8822C) +#define BITS_NPQ_V1_8822C (BIT_MASK_NPQ_V1_8822C << BIT_SHIFT_NPQ_V1_8822C) +#define BIT_CLEAR_NPQ_V1_8822C(x) ((x) & (~BITS_NPQ_V1_8822C)) +#define BIT_GET_NPQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NPQ_V1_8822C) & BIT_MASK_NPQ_V1_8822C) +#define BIT_SET_NPQ_V1_8822C(x, v) \ + (BIT_CLEAR_NPQ_V1_8822C(x) | BIT_NPQ_V1_8822C(v)) + +/* 2 REG_FIFOPAGE_INFO_4_8822C */ + +#define BIT_SHIFT_EXQ_AVAL_PG_V1_8822C 16 +#define BIT_MASK_EXQ_AVAL_PG_V1_8822C 0xfff +#define BIT_EXQ_AVAL_PG_V1_8822C(x) \ + (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822C) \ + << BIT_SHIFT_EXQ_AVAL_PG_V1_8822C) +#define BITS_EXQ_AVAL_PG_V1_8822C \ + (BIT_MASK_EXQ_AVAL_PG_V1_8822C << BIT_SHIFT_EXQ_AVAL_PG_V1_8822C) +#define BIT_CLEAR_EXQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8822C)) +#define BIT_GET_EXQ_AVAL_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822C) & \ + BIT_MASK_EXQ_AVAL_PG_V1_8822C) +#define BIT_SET_EXQ_AVAL_PG_V1_8822C(x, v) \ + (BIT_CLEAR_EXQ_AVAL_PG_V1_8822C(x) | BIT_EXQ_AVAL_PG_V1_8822C(v)) + +#define BIT_SHIFT_EXQ_V1_8822C 0 +#define BIT_MASK_EXQ_V1_8822C 0xfff +#define BIT_EXQ_V1_8822C(x) \ + (((x) & BIT_MASK_EXQ_V1_8822C) << BIT_SHIFT_EXQ_V1_8822C) +#define BITS_EXQ_V1_8822C (BIT_MASK_EXQ_V1_8822C << BIT_SHIFT_EXQ_V1_8822C) +#define BIT_CLEAR_EXQ_V1_8822C(x) ((x) & (~BITS_EXQ_V1_8822C)) +#define BIT_GET_EXQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EXQ_V1_8822C) & BIT_MASK_EXQ_V1_8822C) +#define BIT_SET_EXQ_V1_8822C(x, v) \ + (BIT_CLEAR_EXQ_V1_8822C(x) | BIT_EXQ_V1_8822C(v)) + +/* 2 REG_FIFOPAGE_INFO_5_8822C */ + +#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C 16 +#define BIT_MASK_PUBQ_AVAL_PG_V1_8822C 0xfff +#define BIT_PUBQ_AVAL_PG_V1_8822C(x) \ + (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822C) \ + << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C) +#define BITS_PUBQ_AVAL_PG_V1_8822C \ + (BIT_MASK_PUBQ_AVAL_PG_V1_8822C << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C) +#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8822C)) +#define BIT_GET_PUBQ_AVAL_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C) & \ + BIT_MASK_PUBQ_AVAL_PG_V1_8822C) +#define BIT_SET_PUBQ_AVAL_PG_V1_8822C(x, v) \ + (BIT_CLEAR_PUBQ_AVAL_PG_V1_8822C(x) | BIT_PUBQ_AVAL_PG_V1_8822C(v)) + +#define BIT_SHIFT_PUBQ_V1_8822C 0 +#define BIT_MASK_PUBQ_V1_8822C 0xfff +#define BIT_PUBQ_V1_8822C(x) \ + (((x) & BIT_MASK_PUBQ_V1_8822C) << BIT_SHIFT_PUBQ_V1_8822C) +#define BITS_PUBQ_V1_8822C (BIT_MASK_PUBQ_V1_8822C << BIT_SHIFT_PUBQ_V1_8822C) +#define BIT_CLEAR_PUBQ_V1_8822C(x) ((x) & (~BITS_PUBQ_V1_8822C)) +#define BIT_GET_PUBQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PUBQ_V1_8822C) & BIT_MASK_PUBQ_V1_8822C) +#define BIT_SET_PUBQ_V1_8822C(x, v) \ + (BIT_CLEAR_PUBQ_V1_8822C(x) | BIT_PUBQ_V1_8822C(v)) + +/* 2 REG_H2C_HEAD_8822C */ + +#define BIT_SHIFT_H2C_HEAD_8822C 0 +#define BIT_MASK_H2C_HEAD_8822C 0x3ffff +#define BIT_H2C_HEAD_8822C(x) \ + (((x) & BIT_MASK_H2C_HEAD_8822C) << BIT_SHIFT_H2C_HEAD_8822C) +#define BITS_H2C_HEAD_8822C \ + (BIT_MASK_H2C_HEAD_8822C << BIT_SHIFT_H2C_HEAD_8822C) +#define BIT_CLEAR_H2C_HEAD_8822C(x) ((x) & (~BITS_H2C_HEAD_8822C)) +#define BIT_GET_H2C_HEAD_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_HEAD_8822C) & BIT_MASK_H2C_HEAD_8822C) +#define BIT_SET_H2C_HEAD_8822C(x, v) \ + (BIT_CLEAR_H2C_HEAD_8822C(x) | BIT_H2C_HEAD_8822C(v)) + +/* 2 REG_H2C_TAIL_8822C */ + +#define BIT_SHIFT_H2C_TAIL_8822C 0 +#define BIT_MASK_H2C_TAIL_8822C 0x3ffff +#define BIT_H2C_TAIL_8822C(x) \ + (((x) & BIT_MASK_H2C_TAIL_8822C) << BIT_SHIFT_H2C_TAIL_8822C) +#define BITS_H2C_TAIL_8822C \ + (BIT_MASK_H2C_TAIL_8822C << BIT_SHIFT_H2C_TAIL_8822C) +#define BIT_CLEAR_H2C_TAIL_8822C(x) ((x) & (~BITS_H2C_TAIL_8822C)) +#define BIT_GET_H2C_TAIL_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_TAIL_8822C) & BIT_MASK_H2C_TAIL_8822C) +#define BIT_SET_H2C_TAIL_8822C(x, v) \ + (BIT_CLEAR_H2C_TAIL_8822C(x) | BIT_H2C_TAIL_8822C(v)) + +/* 2 REG_H2C_READ_ADDR_8822C */ + +#define BIT_SHIFT_H2C_READ_ADDR_8822C 0 +#define BIT_MASK_H2C_READ_ADDR_8822C 0x3ffff +#define BIT_H2C_READ_ADDR_8822C(x) \ + (((x) & BIT_MASK_H2C_READ_ADDR_8822C) << BIT_SHIFT_H2C_READ_ADDR_8822C) +#define BITS_H2C_READ_ADDR_8822C \ + (BIT_MASK_H2C_READ_ADDR_8822C << BIT_SHIFT_H2C_READ_ADDR_8822C) +#define BIT_CLEAR_H2C_READ_ADDR_8822C(x) ((x) & (~BITS_H2C_READ_ADDR_8822C)) +#define BIT_GET_H2C_READ_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_READ_ADDR_8822C) & BIT_MASK_H2C_READ_ADDR_8822C) +#define BIT_SET_H2C_READ_ADDR_8822C(x, v) \ + (BIT_CLEAR_H2C_READ_ADDR_8822C(x) | BIT_H2C_READ_ADDR_8822C(v)) + +/* 2 REG_H2C_WR_ADDR_8822C */ + +#define BIT_SHIFT_H2C_WR_ADDR_8822C 0 +#define BIT_MASK_H2C_WR_ADDR_8822C 0x3ffff +#define BIT_H2C_WR_ADDR_8822C(x) \ + (((x) & BIT_MASK_H2C_WR_ADDR_8822C) << BIT_SHIFT_H2C_WR_ADDR_8822C) +#define BITS_H2C_WR_ADDR_8822C \ + (BIT_MASK_H2C_WR_ADDR_8822C << BIT_SHIFT_H2C_WR_ADDR_8822C) +#define BIT_CLEAR_H2C_WR_ADDR_8822C(x) ((x) & (~BITS_H2C_WR_ADDR_8822C)) +#define BIT_GET_H2C_WR_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_WR_ADDR_8822C) & BIT_MASK_H2C_WR_ADDR_8822C) +#define BIT_SET_H2C_WR_ADDR_8822C(x, v) \ + (BIT_CLEAR_H2C_WR_ADDR_8822C(x) | BIT_H2C_WR_ADDR_8822C(v)) + +/* 2 REG_H2C_INFO_8822C */ +#define BIT_H2C_SPACE_VLD_8822C BIT(3) +#define BIT_H2C_WR_ADDR_RST_8822C BIT(2) + +#define BIT_SHIFT_H2C_LEN_SEL_8822C 0 +#define BIT_MASK_H2C_LEN_SEL_8822C 0x3 +#define BIT_H2C_LEN_SEL_8822C(x) \ + (((x) & BIT_MASK_H2C_LEN_SEL_8822C) << BIT_SHIFT_H2C_LEN_SEL_8822C) +#define BITS_H2C_LEN_SEL_8822C \ + (BIT_MASK_H2C_LEN_SEL_8822C << BIT_SHIFT_H2C_LEN_SEL_8822C) +#define BIT_CLEAR_H2C_LEN_SEL_8822C(x) ((x) & (~BITS_H2C_LEN_SEL_8822C)) +#define BIT_GET_H2C_LEN_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_H2C_LEN_SEL_8822C) & BIT_MASK_H2C_LEN_SEL_8822C) +#define BIT_SET_H2C_LEN_SEL_8822C(x, v) \ + (BIT_CLEAR_H2C_LEN_SEL_8822C(x) | BIT_H2C_LEN_SEL_8822C(v)) + +/* 2 REG_PGSUB_CNT_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_RST_PGSUB_CNT_8822C BIT(1) +#define BIT_PGSUB_CNT_EN_8822C BIT(0) + +/* 2 REG_PGSUB_H_8822C */ + +#define BIT_SHIFT_HPQ_PGSUB_CNT_8822C 0 +#define BIT_MASK_HPQ_PGSUB_CNT_8822C 0xffffffffL +#define BIT_HPQ_PGSUB_CNT_8822C(x) \ + (((x) & BIT_MASK_HPQ_PGSUB_CNT_8822C) << BIT_SHIFT_HPQ_PGSUB_CNT_8822C) +#define BITS_HPQ_PGSUB_CNT_8822C \ + (BIT_MASK_HPQ_PGSUB_CNT_8822C << BIT_SHIFT_HPQ_PGSUB_CNT_8822C) +#define BIT_CLEAR_HPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_HPQ_PGSUB_CNT_8822C)) +#define BIT_GET_HPQ_PGSUB_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_HPQ_PGSUB_CNT_8822C) & BIT_MASK_HPQ_PGSUB_CNT_8822C) +#define BIT_SET_HPQ_PGSUB_CNT_8822C(x, v) \ + (BIT_CLEAR_HPQ_PGSUB_CNT_8822C(x) | BIT_HPQ_PGSUB_CNT_8822C(v)) + +/* 2 REG_PGSUB_N_8822C */ + +#define BIT_SHIFT_NPQ_PGSUB_CNT_8822C 0 +#define BIT_MASK_NPQ_PGSUB_CNT_8822C 0xffffffffL +#define BIT_NPQ_PGSUB_CNT_8822C(x) \ + (((x) & BIT_MASK_NPQ_PGSUB_CNT_8822C) << BIT_SHIFT_NPQ_PGSUB_CNT_8822C) +#define BITS_NPQ_PGSUB_CNT_8822C \ + (BIT_MASK_NPQ_PGSUB_CNT_8822C << BIT_SHIFT_NPQ_PGSUB_CNT_8822C) +#define BIT_CLEAR_NPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_NPQ_PGSUB_CNT_8822C)) +#define BIT_GET_NPQ_PGSUB_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_NPQ_PGSUB_CNT_8822C) & BIT_MASK_NPQ_PGSUB_CNT_8822C) +#define BIT_SET_NPQ_PGSUB_CNT_8822C(x, v) \ + (BIT_CLEAR_NPQ_PGSUB_CNT_8822C(x) | BIT_NPQ_PGSUB_CNT_8822C(v)) + +/* 2 REG_PGSUB_L_8822C */ + +#define BIT_SHIFT_LPQ_PGSUB_CNT_8822C 0 +#define BIT_MASK_LPQ_PGSUB_CNT_8822C 0xffffffffL +#define BIT_LPQ_PGSUB_CNT_8822C(x) \ + (((x) & BIT_MASK_LPQ_PGSUB_CNT_8822C) << BIT_SHIFT_LPQ_PGSUB_CNT_8822C) +#define BITS_LPQ_PGSUB_CNT_8822C \ + (BIT_MASK_LPQ_PGSUB_CNT_8822C << BIT_SHIFT_LPQ_PGSUB_CNT_8822C) +#define BIT_CLEAR_LPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_LPQ_PGSUB_CNT_8822C)) +#define BIT_GET_LPQ_PGSUB_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_LPQ_PGSUB_CNT_8822C) & BIT_MASK_LPQ_PGSUB_CNT_8822C) +#define BIT_SET_LPQ_PGSUB_CNT_8822C(x, v) \ + (BIT_CLEAR_LPQ_PGSUB_CNT_8822C(x) | BIT_LPQ_PGSUB_CNT_8822C(v)) + +/* 2 REG_PGSUB_E_8822C */ + +#define BIT_SHIFT_EPQ_PGSUB_CNT_8822C 0 +#define BIT_MASK_EPQ_PGSUB_CNT_8822C 0xffffffffL +#define BIT_EPQ_PGSUB_CNT_8822C(x) \ + (((x) & BIT_MASK_EPQ_PGSUB_CNT_8822C) << BIT_SHIFT_EPQ_PGSUB_CNT_8822C) +#define BITS_EPQ_PGSUB_CNT_8822C \ + (BIT_MASK_EPQ_PGSUB_CNT_8822C << BIT_SHIFT_EPQ_PGSUB_CNT_8822C) +#define BIT_CLEAR_EPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_EPQ_PGSUB_CNT_8822C)) +#define BIT_GET_EPQ_PGSUB_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_EPQ_PGSUB_CNT_8822C) & BIT_MASK_EPQ_PGSUB_CNT_8822C) +#define BIT_SET_EPQ_PGSUB_CNT_8822C(x, v) \ + (BIT_CLEAR_EPQ_PGSUB_CNT_8822C(x) | BIT_EPQ_PGSUB_CNT_8822C(v)) + +/* 2 REG_RXDMA_AGG_PG_TH_8822C */ +#define BIT_USB_RXDMA_AGG_EN_8822C BIT(31) +#define BIT_EN_FW_ADD_8822C BIT(30) +#define BIT_EN_PRE_CALC_8822C BIT(29) +#define BIT_RXAGG_SW_EN_8822C BIT(28) +#define BIT_RXAGG_SW_TRIG_8822C BIT(27) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DMA_AGG_TO_V1_8822C 8 +#define BIT_MASK_DMA_AGG_TO_V1_8822C 0xff +#define BIT_DMA_AGG_TO_V1_8822C(x) \ + (((x) & BIT_MASK_DMA_AGG_TO_V1_8822C) << BIT_SHIFT_DMA_AGG_TO_V1_8822C) +#define BITS_DMA_AGG_TO_V1_8822C \ + (BIT_MASK_DMA_AGG_TO_V1_8822C << BIT_SHIFT_DMA_AGG_TO_V1_8822C) +#define BIT_CLEAR_DMA_AGG_TO_V1_8822C(x) ((x) & (~BITS_DMA_AGG_TO_V1_8822C)) +#define BIT_GET_DMA_AGG_TO_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8822C) & BIT_MASK_DMA_AGG_TO_V1_8822C) +#define BIT_SET_DMA_AGG_TO_V1_8822C(x, v) \ + (BIT_CLEAR_DMA_AGG_TO_V1_8822C(x) | BIT_DMA_AGG_TO_V1_8822C(v)) + +#define BIT_SHIFT_RXDMA_AGG_PG_TH_8822C 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_8822C 0xff +#define BIT_RXDMA_AGG_PG_TH_8822C(x) \ + (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8822C) \ + << BIT_SHIFT_RXDMA_AGG_PG_TH_8822C) +#define BITS_RXDMA_AGG_PG_TH_8822C \ + (BIT_MASK_RXDMA_AGG_PG_TH_8822C << BIT_SHIFT_RXDMA_AGG_PG_TH_8822C) +#define BIT_CLEAR_RXDMA_AGG_PG_TH_8822C(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8822C)) +#define BIT_GET_RXDMA_AGG_PG_TH_8822C(x) \ + (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8822C) & \ + BIT_MASK_RXDMA_AGG_PG_TH_8822C) +#define BIT_SET_RXDMA_AGG_PG_TH_8822C(x, v) \ + (BIT_CLEAR_RXDMA_AGG_PG_TH_8822C(x) | BIT_RXDMA_AGG_PG_TH_8822C(v)) + +/* 2 REG_RXPKT_NUM_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C 20 +#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C 0xf +#define BIT_FW_UPD_RDPTR19_TO_16_8822C(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C) \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C) +#define BITS_FW_UPD_RDPTR19_TO_16_8822C \ + (BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C \ + << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C) +#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822C(x) \ + ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8822C)) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822C(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C) & \ + BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C) +#define BIT_SET_FW_UPD_RDPTR19_TO_16_8822C(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822C(x) | \ + BIT_FW_UPD_RDPTR19_TO_16_8822C(v)) + +#define BIT_RXDMA_REQ_8822C BIT(19) +#define BIT_RW_RELEASE_EN_8822C BIT(18) +#define BIT_RXDMA_IDLE_8822C BIT(17) +#define BIT_RXPKT_RELEASE_POLL_8822C BIT(16) + +#define BIT_SHIFT_FW_UPD_RDPTR_8822C 0 +#define BIT_MASK_FW_UPD_RDPTR_8822C 0xffff +#define BIT_FW_UPD_RDPTR_8822C(x) \ + (((x) & BIT_MASK_FW_UPD_RDPTR_8822C) << BIT_SHIFT_FW_UPD_RDPTR_8822C) +#define BITS_FW_UPD_RDPTR_8822C \ + (BIT_MASK_FW_UPD_RDPTR_8822C << BIT_SHIFT_FW_UPD_RDPTR_8822C) +#define BIT_CLEAR_FW_UPD_RDPTR_8822C(x) ((x) & (~BITS_FW_UPD_RDPTR_8822C)) +#define BIT_GET_FW_UPD_RDPTR_8822C(x) \ + (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822C) & BIT_MASK_FW_UPD_RDPTR_8822C) +#define BIT_SET_FW_UPD_RDPTR_8822C(x, v) \ + (BIT_CLEAR_FW_UPD_RDPTR_8822C(x) | BIT_FW_UPD_RDPTR_8822C(v)) + +/* 2 REG_RXDMA_STATUS_8822C */ +#define BIT_C2H_PKT_OVF_8822C BIT(7) +#define BIT_AGG_CONFGI_ISSUE_8822C BIT(6) +#define BIT_FW_POLL_ISSUE_8822C BIT(5) +#define BIT_RX_DATA_UDN_8822C BIT(4) +#define BIT_RX_SFF_UDN_8822C BIT(3) +#define BIT_RX_SFF_OVF_8822C BIT(2) +#define BIT_RXPKT_OVF_8822C BIT(0) + +/* 2 REG_RXDMA_DPR_8822C */ + +#define BIT_SHIFT_RDE_DEBUG_8822C 0 +#define BIT_MASK_RDE_DEBUG_8822C 0xffffffffL +#define BIT_RDE_DEBUG_8822C(x) \ + (((x) & BIT_MASK_RDE_DEBUG_8822C) << BIT_SHIFT_RDE_DEBUG_8822C) +#define BITS_RDE_DEBUG_8822C \ + (BIT_MASK_RDE_DEBUG_8822C << BIT_SHIFT_RDE_DEBUG_8822C) +#define BIT_CLEAR_RDE_DEBUG_8822C(x) ((x) & (~BITS_RDE_DEBUG_8822C)) +#define BIT_GET_RDE_DEBUG_8822C(x) \ + (((x) >> BIT_SHIFT_RDE_DEBUG_8822C) & BIT_MASK_RDE_DEBUG_8822C) +#define BIT_SET_RDE_DEBUG_8822C(x, v) \ + (BIT_CLEAR_RDE_DEBUG_8822C(x) | BIT_RDE_DEBUG_8822C(v)) + +/* 2 REG_RXDMA_MODE_8822C */ + +#define BIT_SHIFT_PKTNUM_TH_V2_8822C 24 +#define BIT_MASK_PKTNUM_TH_V2_8822C 0x1f +#define BIT_PKTNUM_TH_V2_8822C(x) \ + (((x) & BIT_MASK_PKTNUM_TH_V2_8822C) << BIT_SHIFT_PKTNUM_TH_V2_8822C) +#define BITS_PKTNUM_TH_V2_8822C \ + (BIT_MASK_PKTNUM_TH_V2_8822C << BIT_SHIFT_PKTNUM_TH_V2_8822C) +#define BIT_CLEAR_PKTNUM_TH_V2_8822C(x) ((x) & (~BITS_PKTNUM_TH_V2_8822C)) +#define BIT_GET_PKTNUM_TH_V2_8822C(x) \ + (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822C) & BIT_MASK_PKTNUM_TH_V2_8822C) +#define BIT_SET_PKTNUM_TH_V2_8822C(x, v) \ + (BIT_CLEAR_PKTNUM_TH_V2_8822C(x) | BIT_PKTNUM_TH_V2_8822C(v)) + +#define BIT_TXBA_BREAK_USBAGG_8822C BIT(23) + +#define BIT_SHIFT_PKTLEN_PARA_8822C 16 +#define BIT_MASK_PKTLEN_PARA_8822C 0x7 +#define BIT_PKTLEN_PARA_8822C(x) \ + (((x) & BIT_MASK_PKTLEN_PARA_8822C) << BIT_SHIFT_PKTLEN_PARA_8822C) +#define BITS_PKTLEN_PARA_8822C \ + (BIT_MASK_PKTLEN_PARA_8822C << BIT_SHIFT_PKTLEN_PARA_8822C) +#define BIT_CLEAR_PKTLEN_PARA_8822C(x) ((x) & (~BITS_PKTLEN_PARA_8822C)) +#define BIT_GET_PKTLEN_PARA_8822C(x) \ + (((x) >> BIT_SHIFT_PKTLEN_PARA_8822C) & BIT_MASK_PKTLEN_PARA_8822C) +#define BIT_SET_PKTLEN_PARA_8822C(x, v) \ + (BIT_CLEAR_PKTLEN_PARA_8822C(x) | BIT_PKTLEN_PARA_8822C(v)) + +#define BIT_RX_DBG_SEL_8822C BIT(7) +#define BIT_EN_SPD_8822C BIT(6) + +#define BIT_SHIFT_BURST_SIZE_8822C 4 +#define BIT_MASK_BURST_SIZE_8822C 0x3 +#define BIT_BURST_SIZE_8822C(x) \ + (((x) & BIT_MASK_BURST_SIZE_8822C) << BIT_SHIFT_BURST_SIZE_8822C) +#define BITS_BURST_SIZE_8822C \ + (BIT_MASK_BURST_SIZE_8822C << BIT_SHIFT_BURST_SIZE_8822C) +#define BIT_CLEAR_BURST_SIZE_8822C(x) ((x) & (~BITS_BURST_SIZE_8822C)) +#define BIT_GET_BURST_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_BURST_SIZE_8822C) & BIT_MASK_BURST_SIZE_8822C) +#define BIT_SET_BURST_SIZE_8822C(x, v) \ + (BIT_CLEAR_BURST_SIZE_8822C(x) | BIT_BURST_SIZE_8822C(v)) + +#define BIT_SHIFT_BURST_CNT_8822C 2 +#define BIT_MASK_BURST_CNT_8822C 0x3 +#define BIT_BURST_CNT_8822C(x) \ + (((x) & BIT_MASK_BURST_CNT_8822C) << BIT_SHIFT_BURST_CNT_8822C) +#define BITS_BURST_CNT_8822C \ + (BIT_MASK_BURST_CNT_8822C << BIT_SHIFT_BURST_CNT_8822C) +#define BIT_CLEAR_BURST_CNT_8822C(x) ((x) & (~BITS_BURST_CNT_8822C)) +#define BIT_GET_BURST_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_BURST_CNT_8822C) & BIT_MASK_BURST_CNT_8822C) +#define BIT_SET_BURST_CNT_8822C(x, v) \ + (BIT_CLEAR_BURST_CNT_8822C(x) | BIT_BURST_CNT_8822C(v)) + +#define BIT_DMA_MODE_8822C BIT(1) + +/* 2 REG_C2H_PKT_8822C */ + +#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C 24 +#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C 0xf +#define BIT_R_C2H_STR_ADDR_16_TO_19_8822C(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C) \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C) +#define BITS_R_C2H_STR_ADDR_16_TO_19_8822C \ + (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C \ + << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C) +#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822C(x) \ + ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8822C)) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822C(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C) & \ + BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C) +#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8822C(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822C(x) | \ + BIT_R_C2H_STR_ADDR_16_TO_19_8822C(v)) + +#define BIT_R_C2H_PKT_REQ_8822C BIT(16) + +#define BIT_SHIFT_R_C2H_STR_ADDR_8822C 0 +#define BIT_MASK_R_C2H_STR_ADDR_8822C 0xffff +#define BIT_R_C2H_STR_ADDR_8822C(x) \ + (((x) & BIT_MASK_R_C2H_STR_ADDR_8822C) \ + << BIT_SHIFT_R_C2H_STR_ADDR_8822C) +#define BITS_R_C2H_STR_ADDR_8822C \ + (BIT_MASK_R_C2H_STR_ADDR_8822C << BIT_SHIFT_R_C2H_STR_ADDR_8822C) +#define BIT_CLEAR_R_C2H_STR_ADDR_8822C(x) ((x) & (~BITS_R_C2H_STR_ADDR_8822C)) +#define BIT_GET_R_C2H_STR_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822C) & \ + BIT_MASK_R_C2H_STR_ADDR_8822C) +#define BIT_SET_R_C2H_STR_ADDR_8822C(x, v) \ + (BIT_CLEAR_R_C2H_STR_ADDR_8822C(x) | BIT_R_C2H_STR_ADDR_8822C(v)) + +/* 2 REG_FWFF_C2H_8822C */ + +#define BIT_SHIFT_C2H_DMA_ADDR_8822C 0 +#define BIT_MASK_C2H_DMA_ADDR_8822C 0x3ffff +#define BIT_C2H_DMA_ADDR_8822C(x) \ + (((x) & BIT_MASK_C2H_DMA_ADDR_8822C) << BIT_SHIFT_C2H_DMA_ADDR_8822C) +#define BITS_C2H_DMA_ADDR_8822C \ + (BIT_MASK_C2H_DMA_ADDR_8822C << BIT_SHIFT_C2H_DMA_ADDR_8822C) +#define BIT_CLEAR_C2H_DMA_ADDR_8822C(x) ((x) & (~BITS_C2H_DMA_ADDR_8822C)) +#define BIT_GET_C2H_DMA_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822C) & BIT_MASK_C2H_DMA_ADDR_8822C) +#define BIT_SET_C2H_DMA_ADDR_8822C(x, v) \ + (BIT_CLEAR_C2H_DMA_ADDR_8822C(x) | BIT_C2H_DMA_ADDR_8822C(v)) + +/* 2 REG_FWFF_CTRL_8822C */ +#define BIT_FWFF_DMAPKT_REQ_8822C BIT(31) + +#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C 16 +#define BIT_MASK_FWFF_DMA_PKT_NUM_8822C 0xff +#define BIT_FWFF_DMA_PKT_NUM_8822C(x) \ + (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822C) \ + << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C) +#define BITS_FWFF_DMA_PKT_NUM_8822C \ + (BIT_MASK_FWFF_DMA_PKT_NUM_8822C << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C) +#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8822C(x) \ + ((x) & (~BITS_FWFF_DMA_PKT_NUM_8822C)) +#define BIT_GET_FWFF_DMA_PKT_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C) & \ + BIT_MASK_FWFF_DMA_PKT_NUM_8822C) +#define BIT_SET_FWFF_DMA_PKT_NUM_8822C(x, v) \ + (BIT_CLEAR_FWFF_DMA_PKT_NUM_8822C(x) | BIT_FWFF_DMA_PKT_NUM_8822C(v)) + +#define BIT_SHIFT_FWFF_STR_ADDR_8822C 0 +#define BIT_MASK_FWFF_STR_ADDR_8822C 0xffff +#define BIT_FWFF_STR_ADDR_8822C(x) \ + (((x) & BIT_MASK_FWFF_STR_ADDR_8822C) << BIT_SHIFT_FWFF_STR_ADDR_8822C) +#define BITS_FWFF_STR_ADDR_8822C \ + (BIT_MASK_FWFF_STR_ADDR_8822C << BIT_SHIFT_FWFF_STR_ADDR_8822C) +#define BIT_CLEAR_FWFF_STR_ADDR_8822C(x) ((x) & (~BITS_FWFF_STR_ADDR_8822C)) +#define BIT_GET_FWFF_STR_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822C) & BIT_MASK_FWFF_STR_ADDR_8822C) +#define BIT_SET_FWFF_STR_ADDR_8822C(x, v) \ + (BIT_CLEAR_FWFF_STR_ADDR_8822C(x) | BIT_FWFF_STR_ADDR_8822C(v)) + +/* 2 REG_FWFF_PKT_INFO_8822C */ + +#define BIT_SHIFT_FWFF_PKT_QUEUED_8822C 16 +#define BIT_MASK_FWFF_PKT_QUEUED_8822C 0xff +#define BIT_FWFF_PKT_QUEUED_8822C(x) \ + (((x) & BIT_MASK_FWFF_PKT_QUEUED_8822C) \ + << BIT_SHIFT_FWFF_PKT_QUEUED_8822C) +#define BITS_FWFF_PKT_QUEUED_8822C \ + (BIT_MASK_FWFF_PKT_QUEUED_8822C << BIT_SHIFT_FWFF_PKT_QUEUED_8822C) +#define BIT_CLEAR_FWFF_PKT_QUEUED_8822C(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8822C)) +#define BIT_GET_FWFF_PKT_QUEUED_8822C(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822C) & \ + BIT_MASK_FWFF_PKT_QUEUED_8822C) +#define BIT_SET_FWFF_PKT_QUEUED_8822C(x, v) \ + (BIT_CLEAR_FWFF_PKT_QUEUED_8822C(x) | BIT_FWFF_PKT_QUEUED_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C 0 +#define BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C 0x3fff +#define BIT_FWFF_PKT_STR_ADDR_V2_8822C(x) \ + (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C) \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C) +#define BITS_FWFF_PKT_STR_ADDR_V2_8822C \ + (BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C \ + << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C) +#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V2_8822C(x) \ + ((x) & (~BITS_FWFF_PKT_STR_ADDR_V2_8822C)) +#define BIT_GET_FWFF_PKT_STR_ADDR_V2_8822C(x) \ + (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C) & \ + BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C) +#define BIT_SET_FWFF_PKT_STR_ADDR_V2_8822C(x, v) \ + (BIT_CLEAR_FWFF_PKT_STR_ADDR_V2_8822C(x) | \ + BIT_FWFF_PKT_STR_ADDR_V2_8822C(v)) + +/* 2 REG_RXPKTNUM_8822C */ + +#define BIT_SHIFT_PKT_NUM_WOL_V1_8822C 16 +#define BIT_MASK_PKT_NUM_WOL_V1_8822C 0xffff +#define BIT_PKT_NUM_WOL_V1_8822C(x) \ + (((x) & BIT_MASK_PKT_NUM_WOL_V1_8822C) \ + << BIT_SHIFT_PKT_NUM_WOL_V1_8822C) +#define BITS_PKT_NUM_WOL_V1_8822C \ + (BIT_MASK_PKT_NUM_WOL_V1_8822C << BIT_SHIFT_PKT_NUM_WOL_V1_8822C) +#define BIT_CLEAR_PKT_NUM_WOL_V1_8822C(x) ((x) & (~BITS_PKT_NUM_WOL_V1_8822C)) +#define BIT_GET_PKT_NUM_WOL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PKT_NUM_WOL_V1_8822C) & \ + BIT_MASK_PKT_NUM_WOL_V1_8822C) +#define BIT_SET_PKT_NUM_WOL_V1_8822C(x, v) \ + (BIT_CLEAR_PKT_NUM_WOL_V1_8822C(x) | BIT_PKT_NUM_WOL_V1_8822C(v)) + +#define BIT_SHIFT_RXPKT_NUM_V1_8822C 0 +#define BIT_MASK_RXPKT_NUM_V1_8822C 0xffff +#define BIT_RXPKT_NUM_V1_8822C(x) \ + (((x) & BIT_MASK_RXPKT_NUM_V1_8822C) << BIT_SHIFT_RXPKT_NUM_V1_8822C) +#define BITS_RXPKT_NUM_V1_8822C \ + (BIT_MASK_RXPKT_NUM_V1_8822C << BIT_SHIFT_RXPKT_NUM_V1_8822C) +#define BIT_CLEAR_RXPKT_NUM_V1_8822C(x) ((x) & (~BITS_RXPKT_NUM_V1_8822C)) +#define BIT_GET_RXPKT_NUM_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_V1_8822C) & BIT_MASK_RXPKT_NUM_V1_8822C) +#define BIT_SET_RXPKT_NUM_V1_8822C(x, v) \ + (BIT_CLEAR_RXPKT_NUM_V1_8822C(x) | BIT_RXPKT_NUM_V1_8822C(v)) + +/* 2 REG_RXPKTNUM_TH_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_RXPKT_NUM_TH_8822C 0 +#define BIT_MASK_RXPKT_NUM_TH_8822C 0xff +#define BIT_RXPKT_NUM_TH_8822C(x) \ + (((x) & BIT_MASK_RXPKT_NUM_TH_8822C) << BIT_SHIFT_RXPKT_NUM_TH_8822C) +#define BITS_RXPKT_NUM_TH_8822C \ + (BIT_MASK_RXPKT_NUM_TH_8822C << BIT_SHIFT_RXPKT_NUM_TH_8822C) +#define BIT_CLEAR_RXPKT_NUM_TH_8822C(x) ((x) & (~BITS_RXPKT_NUM_TH_8822C)) +#define BIT_GET_RXPKT_NUM_TH_8822C(x) \ + (((x) >> BIT_SHIFT_RXPKT_NUM_TH_8822C) & BIT_MASK_RXPKT_NUM_TH_8822C) +#define BIT_SET_RXPKT_NUM_TH_8822C(x, v) \ + (BIT_CLEAR_RXPKT_NUM_TH_8822C(x) | BIT_RXPKT_NUM_TH_8822C(v)) + +/* 2 REG_FW_MSG1_8822C */ + +#define BIT_SHIFT_FW_MSG_REG1_8822C 0 +#define BIT_MASK_FW_MSG_REG1_8822C 0xffffffffL +#define BIT_FW_MSG_REG1_8822C(x) \ + (((x) & BIT_MASK_FW_MSG_REG1_8822C) << BIT_SHIFT_FW_MSG_REG1_8822C) +#define BITS_FW_MSG_REG1_8822C \ + (BIT_MASK_FW_MSG_REG1_8822C << BIT_SHIFT_FW_MSG_REG1_8822C) +#define BIT_CLEAR_FW_MSG_REG1_8822C(x) ((x) & (~BITS_FW_MSG_REG1_8822C)) +#define BIT_GET_FW_MSG_REG1_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG1_8822C) & BIT_MASK_FW_MSG_REG1_8822C) +#define BIT_SET_FW_MSG_REG1_8822C(x, v) \ + (BIT_CLEAR_FW_MSG_REG1_8822C(x) | BIT_FW_MSG_REG1_8822C(v)) + +/* 2 REG_FW_MSG2_8822C */ + +#define BIT_SHIFT_FW_MSG_REG2_8822C 0 +#define BIT_MASK_FW_MSG_REG2_8822C 0xffffffffL +#define BIT_FW_MSG_REG2_8822C(x) \ + (((x) & BIT_MASK_FW_MSG_REG2_8822C) << BIT_SHIFT_FW_MSG_REG2_8822C) +#define BITS_FW_MSG_REG2_8822C \ + (BIT_MASK_FW_MSG_REG2_8822C << BIT_SHIFT_FW_MSG_REG2_8822C) +#define BIT_CLEAR_FW_MSG_REG2_8822C(x) ((x) & (~BITS_FW_MSG_REG2_8822C)) +#define BIT_GET_FW_MSG_REG2_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG2_8822C) & BIT_MASK_FW_MSG_REG2_8822C) +#define BIT_SET_FW_MSG_REG2_8822C(x, v) \ + (BIT_CLEAR_FW_MSG_REG2_8822C(x) | BIT_FW_MSG_REG2_8822C(v)) + +/* 2 REG_FW_MSG3_8822C */ + +#define BIT_SHIFT_FW_MSG_REG3_8822C 0 +#define BIT_MASK_FW_MSG_REG3_8822C 0xffffffffL +#define BIT_FW_MSG_REG3_8822C(x) \ + (((x) & BIT_MASK_FW_MSG_REG3_8822C) << BIT_SHIFT_FW_MSG_REG3_8822C) +#define BITS_FW_MSG_REG3_8822C \ + (BIT_MASK_FW_MSG_REG3_8822C << BIT_SHIFT_FW_MSG_REG3_8822C) +#define BIT_CLEAR_FW_MSG_REG3_8822C(x) ((x) & (~BITS_FW_MSG_REG3_8822C)) +#define BIT_GET_FW_MSG_REG3_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG3_8822C) & BIT_MASK_FW_MSG_REG3_8822C) +#define BIT_SET_FW_MSG_REG3_8822C(x, v) \ + (BIT_CLEAR_FW_MSG_REG3_8822C(x) | BIT_FW_MSG_REG3_8822C(v)) + +/* 2 REG_FW_MSG4_8822C */ + +#define BIT_SHIFT_FW_MSG_REG4_8822C 0 +#define BIT_MASK_FW_MSG_REG4_8822C 0xffffffffL +#define BIT_FW_MSG_REG4_8822C(x) \ + (((x) & BIT_MASK_FW_MSG_REG4_8822C) << BIT_SHIFT_FW_MSG_REG4_8822C) +#define BITS_FW_MSG_REG4_8822C \ + (BIT_MASK_FW_MSG_REG4_8822C << BIT_SHIFT_FW_MSG_REG4_8822C) +#define BIT_CLEAR_FW_MSG_REG4_8822C(x) ((x) & (~BITS_FW_MSG_REG4_8822C)) +#define BIT_GET_FW_MSG_REG4_8822C(x) \ + (((x) >> BIT_SHIFT_FW_MSG_REG4_8822C) & BIT_MASK_FW_MSG_REG4_8822C) +#define BIT_SET_FW_MSG_REG4_8822C(x, v) \ + (BIT_CLEAR_FW_MSG_REG4_8822C(x) | BIT_FW_MSG_REG4_8822C(v)) + +/* 2 REG_DDMA_CH0SA_8822C */ + +#define BIT_SHIFT_DDMACH0_SA_8822C 0 +#define BIT_MASK_DDMACH0_SA_8822C 0xffffffffL +#define BIT_DDMACH0_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH0_SA_8822C) << BIT_SHIFT_DDMACH0_SA_8822C) +#define BITS_DDMACH0_SA_8822C \ + (BIT_MASK_DDMACH0_SA_8822C << BIT_SHIFT_DDMACH0_SA_8822C) +#define BIT_CLEAR_DDMACH0_SA_8822C(x) ((x) & (~BITS_DDMACH0_SA_8822C)) +#define BIT_GET_DDMACH0_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_SA_8822C) & BIT_MASK_DDMACH0_SA_8822C) +#define BIT_SET_DDMACH0_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH0_SA_8822C(x) | BIT_DDMACH0_SA_8822C(v)) + +/* 2 REG_DDMA_CH0DA_8822C */ + +#define BIT_SHIFT_DDMACH0_DA_8822C 0 +#define BIT_MASK_DDMACH0_DA_8822C 0xffffffffL +#define BIT_DDMACH0_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH0_DA_8822C) << BIT_SHIFT_DDMACH0_DA_8822C) +#define BITS_DDMACH0_DA_8822C \ + (BIT_MASK_DDMACH0_DA_8822C << BIT_SHIFT_DDMACH0_DA_8822C) +#define BIT_CLEAR_DDMACH0_DA_8822C(x) ((x) & (~BITS_DDMACH0_DA_8822C)) +#define BIT_GET_DDMACH0_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DA_8822C) & BIT_MASK_DDMACH0_DA_8822C) +#define BIT_SET_DDMACH0_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH0_DA_8822C(x) | BIT_DDMACH0_DA_8822C(v)) + +/* 2 REG_DDMA_CH0CTRL_8822C */ +#define BIT_DDMACH0_OWN_8822C BIT(31) +#define BIT_DDMACH0_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH0_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH0_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH0_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH0_DDMA_MODE_8822C BIT(26) +#define BIT_DDMACH0_RESET_CHKSUM_STS_8822C BIT(25) +#define BIT_DDMACH0_CHKSUM_CONT_8822C BIT(24) + +#define BIT_SHIFT_DDMACH0_DLEN_8822C 0 +#define BIT_MASK_DDMACH0_DLEN_8822C 0x3ffff +#define BIT_DDMACH0_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH0_DLEN_8822C) << BIT_SHIFT_DDMACH0_DLEN_8822C) +#define BITS_DDMACH0_DLEN_8822C \ + (BIT_MASK_DDMACH0_DLEN_8822C << BIT_SHIFT_DDMACH0_DLEN_8822C) +#define BIT_CLEAR_DDMACH0_DLEN_8822C(x) ((x) & (~BITS_DDMACH0_DLEN_8822C)) +#define BIT_GET_DDMACH0_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH0_DLEN_8822C) & BIT_MASK_DDMACH0_DLEN_8822C) +#define BIT_SET_DDMACH0_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH0_DLEN_8822C(x) | BIT_DDMACH0_DLEN_8822C(v)) + +/* 2 REG_DDMA_CH1SA_8822C */ + +#define BIT_SHIFT_DDMACH1_SA_8822C 0 +#define BIT_MASK_DDMACH1_SA_8822C 0xffffffffL +#define BIT_DDMACH1_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH1_SA_8822C) << BIT_SHIFT_DDMACH1_SA_8822C) +#define BITS_DDMACH1_SA_8822C \ + (BIT_MASK_DDMACH1_SA_8822C << BIT_SHIFT_DDMACH1_SA_8822C) +#define BIT_CLEAR_DDMACH1_SA_8822C(x) ((x) & (~BITS_DDMACH1_SA_8822C)) +#define BIT_GET_DDMACH1_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_SA_8822C) & BIT_MASK_DDMACH1_SA_8822C) +#define BIT_SET_DDMACH1_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH1_SA_8822C(x) | BIT_DDMACH1_SA_8822C(v)) + +/* 2 REG_DDMA_CH1DA_8822C */ + +#define BIT_SHIFT_DDMACH1_DA_8822C 0 +#define BIT_MASK_DDMACH1_DA_8822C 0xffffffffL +#define BIT_DDMACH1_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH1_DA_8822C) << BIT_SHIFT_DDMACH1_DA_8822C) +#define BITS_DDMACH1_DA_8822C \ + (BIT_MASK_DDMACH1_DA_8822C << BIT_SHIFT_DDMACH1_DA_8822C) +#define BIT_CLEAR_DDMACH1_DA_8822C(x) ((x) & (~BITS_DDMACH1_DA_8822C)) +#define BIT_GET_DDMACH1_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DA_8822C) & BIT_MASK_DDMACH1_DA_8822C) +#define BIT_SET_DDMACH1_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH1_DA_8822C(x) | BIT_DDMACH1_DA_8822C(v)) + +/* 2 REG_DDMA_CH1CTRL_8822C */ +#define BIT_DDMACH1_OWN_8822C BIT(31) +#define BIT_DDMACH1_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH1_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH1_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH1_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH1_DDMA_MODE_8822C BIT(26) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DDMACH1_DLEN_8822C 0 +#define BIT_MASK_DDMACH1_DLEN_8822C 0x3ffff +#define BIT_DDMACH1_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH1_DLEN_8822C) << BIT_SHIFT_DDMACH1_DLEN_8822C) +#define BITS_DDMACH1_DLEN_8822C \ + (BIT_MASK_DDMACH1_DLEN_8822C << BIT_SHIFT_DDMACH1_DLEN_8822C) +#define BIT_CLEAR_DDMACH1_DLEN_8822C(x) ((x) & (~BITS_DDMACH1_DLEN_8822C)) +#define BIT_GET_DDMACH1_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH1_DLEN_8822C) & BIT_MASK_DDMACH1_DLEN_8822C) +#define BIT_SET_DDMACH1_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH1_DLEN_8822C(x) | BIT_DDMACH1_DLEN_8822C(v)) + +/* 2 REG_DDMA_CH2SA_8822C */ + +#define BIT_SHIFT_DDMACH2_SA_8822C 0 +#define BIT_MASK_DDMACH2_SA_8822C 0xffffffffL +#define BIT_DDMACH2_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH2_SA_8822C) << BIT_SHIFT_DDMACH2_SA_8822C) +#define BITS_DDMACH2_SA_8822C \ + (BIT_MASK_DDMACH2_SA_8822C << BIT_SHIFT_DDMACH2_SA_8822C) +#define BIT_CLEAR_DDMACH2_SA_8822C(x) ((x) & (~BITS_DDMACH2_SA_8822C)) +#define BIT_GET_DDMACH2_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_SA_8822C) & BIT_MASK_DDMACH2_SA_8822C) +#define BIT_SET_DDMACH2_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH2_SA_8822C(x) | BIT_DDMACH2_SA_8822C(v)) + +/* 2 REG_DDMA_CH2DA_8822C */ + +#define BIT_SHIFT_DDMACH2_DA_8822C 0 +#define BIT_MASK_DDMACH2_DA_8822C 0xffffffffL +#define BIT_DDMACH2_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH2_DA_8822C) << BIT_SHIFT_DDMACH2_DA_8822C) +#define BITS_DDMACH2_DA_8822C \ + (BIT_MASK_DDMACH2_DA_8822C << BIT_SHIFT_DDMACH2_DA_8822C) +#define BIT_CLEAR_DDMACH2_DA_8822C(x) ((x) & (~BITS_DDMACH2_DA_8822C)) +#define BIT_GET_DDMACH2_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DA_8822C) & BIT_MASK_DDMACH2_DA_8822C) +#define BIT_SET_DDMACH2_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH2_DA_8822C(x) | BIT_DDMACH2_DA_8822C(v)) + +/* 2 REG_DDMA_CH2CTRL_8822C */ +#define BIT_DDMACH2_OWN_8822C BIT(31) +#define BIT_DDMACH2_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH2_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH2_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH2_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH2_DDMA_MODE_8822C BIT(26) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DDMACH2_DLEN_8822C 0 +#define BIT_MASK_DDMACH2_DLEN_8822C 0x3ffff +#define BIT_DDMACH2_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH2_DLEN_8822C) << BIT_SHIFT_DDMACH2_DLEN_8822C) +#define BITS_DDMACH2_DLEN_8822C \ + (BIT_MASK_DDMACH2_DLEN_8822C << BIT_SHIFT_DDMACH2_DLEN_8822C) +#define BIT_CLEAR_DDMACH2_DLEN_8822C(x) ((x) & (~BITS_DDMACH2_DLEN_8822C)) +#define BIT_GET_DDMACH2_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH2_DLEN_8822C) & BIT_MASK_DDMACH2_DLEN_8822C) +#define BIT_SET_DDMACH2_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH2_DLEN_8822C(x) | BIT_DDMACH2_DLEN_8822C(v)) + +/* 2 REG_DDMA_CH3SA_8822C */ + +#define BIT_SHIFT_DDMACH3_SA_8822C 0 +#define BIT_MASK_DDMACH3_SA_8822C 0xffffffffL +#define BIT_DDMACH3_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH3_SA_8822C) << BIT_SHIFT_DDMACH3_SA_8822C) +#define BITS_DDMACH3_SA_8822C \ + (BIT_MASK_DDMACH3_SA_8822C << BIT_SHIFT_DDMACH3_SA_8822C) +#define BIT_CLEAR_DDMACH3_SA_8822C(x) ((x) & (~BITS_DDMACH3_SA_8822C)) +#define BIT_GET_DDMACH3_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_SA_8822C) & BIT_MASK_DDMACH3_SA_8822C) +#define BIT_SET_DDMACH3_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH3_SA_8822C(x) | BIT_DDMACH3_SA_8822C(v)) + +/* 2 REG_DDMA_CH3DA_8822C */ + +#define BIT_SHIFT_DDMACH3_DA_8822C 0 +#define BIT_MASK_DDMACH3_DA_8822C 0xffffffffL +#define BIT_DDMACH3_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH3_DA_8822C) << BIT_SHIFT_DDMACH3_DA_8822C) +#define BITS_DDMACH3_DA_8822C \ + (BIT_MASK_DDMACH3_DA_8822C << BIT_SHIFT_DDMACH3_DA_8822C) +#define BIT_CLEAR_DDMACH3_DA_8822C(x) ((x) & (~BITS_DDMACH3_DA_8822C)) +#define BIT_GET_DDMACH3_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DA_8822C) & BIT_MASK_DDMACH3_DA_8822C) +#define BIT_SET_DDMACH3_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH3_DA_8822C(x) | BIT_DDMACH3_DA_8822C(v)) + +/* 2 REG_DDMA_CH3CTRL_8822C */ +#define BIT_DDMACH3_OWN_8822C BIT(31) +#define BIT_DDMACH3_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH3_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH3_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH3_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH3_DDMA_MODE_8822C BIT(26) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DDMACH3_DLEN_8822C 0 +#define BIT_MASK_DDMACH3_DLEN_8822C 0x3ffff +#define BIT_DDMACH3_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH3_DLEN_8822C) << BIT_SHIFT_DDMACH3_DLEN_8822C) +#define BITS_DDMACH3_DLEN_8822C \ + (BIT_MASK_DDMACH3_DLEN_8822C << BIT_SHIFT_DDMACH3_DLEN_8822C) +#define BIT_CLEAR_DDMACH3_DLEN_8822C(x) ((x) & (~BITS_DDMACH3_DLEN_8822C)) +#define BIT_GET_DDMACH3_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH3_DLEN_8822C) & BIT_MASK_DDMACH3_DLEN_8822C) +#define BIT_SET_DDMACH3_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH3_DLEN_8822C(x) | BIT_DDMACH3_DLEN_8822C(v)) + +/* 2 REG_DDMA_CH4SA_8822C */ + +#define BIT_SHIFT_DDMACH4_SA_8822C 0 +#define BIT_MASK_DDMACH4_SA_8822C 0xffffffffL +#define BIT_DDMACH4_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH4_SA_8822C) << BIT_SHIFT_DDMACH4_SA_8822C) +#define BITS_DDMACH4_SA_8822C \ + (BIT_MASK_DDMACH4_SA_8822C << BIT_SHIFT_DDMACH4_SA_8822C) +#define BIT_CLEAR_DDMACH4_SA_8822C(x) ((x) & (~BITS_DDMACH4_SA_8822C)) +#define BIT_GET_DDMACH4_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_SA_8822C) & BIT_MASK_DDMACH4_SA_8822C) +#define BIT_SET_DDMACH4_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH4_SA_8822C(x) | BIT_DDMACH4_SA_8822C(v)) + +/* 2 REG_DDMA_CH4DA_8822C */ + +#define BIT_SHIFT_DDMACH4_DA_8822C 0 +#define BIT_MASK_DDMACH4_DA_8822C 0xffffffffL +#define BIT_DDMACH4_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH4_DA_8822C) << BIT_SHIFT_DDMACH4_DA_8822C) +#define BITS_DDMACH4_DA_8822C \ + (BIT_MASK_DDMACH4_DA_8822C << BIT_SHIFT_DDMACH4_DA_8822C) +#define BIT_CLEAR_DDMACH4_DA_8822C(x) ((x) & (~BITS_DDMACH4_DA_8822C)) +#define BIT_GET_DDMACH4_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DA_8822C) & BIT_MASK_DDMACH4_DA_8822C) +#define BIT_SET_DDMACH4_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH4_DA_8822C(x) | BIT_DDMACH4_DA_8822C(v)) + +/* 2 REG_DDMA_CH4CTRL_8822C */ +#define BIT_DDMACH4_OWN_8822C BIT(31) +#define BIT_DDMACH4_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH4_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH4_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH4_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH4_DDMA_MODE_8822C BIT(26) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DDMACH4_DLEN_8822C 0 +#define BIT_MASK_DDMACH4_DLEN_8822C 0x3ffff +#define BIT_DDMACH4_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH4_DLEN_8822C) << BIT_SHIFT_DDMACH4_DLEN_8822C) +#define BITS_DDMACH4_DLEN_8822C \ + (BIT_MASK_DDMACH4_DLEN_8822C << BIT_SHIFT_DDMACH4_DLEN_8822C) +#define BIT_CLEAR_DDMACH4_DLEN_8822C(x) ((x) & (~BITS_DDMACH4_DLEN_8822C)) +#define BIT_GET_DDMACH4_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH4_DLEN_8822C) & BIT_MASK_DDMACH4_DLEN_8822C) +#define BIT_SET_DDMACH4_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH4_DLEN_8822C(x) | BIT_DDMACH4_DLEN_8822C(v)) + +/* 2 REG_DDMA_CH5SA_8822C */ + +#define BIT_SHIFT_DDMACH5_SA_8822C 0 +#define BIT_MASK_DDMACH5_SA_8822C 0xffffffffL +#define BIT_DDMACH5_SA_8822C(x) \ + (((x) & BIT_MASK_DDMACH5_SA_8822C) << BIT_SHIFT_DDMACH5_SA_8822C) +#define BITS_DDMACH5_SA_8822C \ + (BIT_MASK_DDMACH5_SA_8822C << BIT_SHIFT_DDMACH5_SA_8822C) +#define BIT_CLEAR_DDMACH5_SA_8822C(x) ((x) & (~BITS_DDMACH5_SA_8822C)) +#define BIT_GET_DDMACH5_SA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_SA_8822C) & BIT_MASK_DDMACH5_SA_8822C) +#define BIT_SET_DDMACH5_SA_8822C(x, v) \ + (BIT_CLEAR_DDMACH5_SA_8822C(x) | BIT_DDMACH5_SA_8822C(v)) + +/* 2 REG_DDMA_CH5DA_8822C */ + +#define BIT_SHIFT_DDMACH5_DA_8822C 0 +#define BIT_MASK_DDMACH5_DA_8822C 0xffffffffL +#define BIT_DDMACH5_DA_8822C(x) \ + (((x) & BIT_MASK_DDMACH5_DA_8822C) << BIT_SHIFT_DDMACH5_DA_8822C) +#define BITS_DDMACH5_DA_8822C \ + (BIT_MASK_DDMACH5_DA_8822C << BIT_SHIFT_DDMACH5_DA_8822C) +#define BIT_CLEAR_DDMACH5_DA_8822C(x) ((x) & (~BITS_DDMACH5_DA_8822C)) +#define BIT_GET_DDMACH5_DA_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DA_8822C) & BIT_MASK_DDMACH5_DA_8822C) +#define BIT_SET_DDMACH5_DA_8822C(x, v) \ + (BIT_CLEAR_DDMACH5_DA_8822C(x) | BIT_DDMACH5_DA_8822C(v)) + +/* 2 REG_DDMA_CH5CTRL_8822C */ +#define BIT_DDMACH5_OWN_8822C BIT(31) +#define BIT_DDMACH5_IDMEM_ERR_8822C BIT(30) +#define BIT_DDMACH5_CHKSUM_EN_8822C BIT(29) +#define BIT_DDMACH5_DA_W_DISABLE_8822C BIT(28) +#define BIT_DDMACH5_CHKSUM_STS_8822C BIT(27) +#define BIT_DDMACH5_DDMA_MODE_8822C BIT(26) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_DDMACH5_DLEN_8822C 0 +#define BIT_MASK_DDMACH5_DLEN_8822C 0x3ffff +#define BIT_DDMACH5_DLEN_8822C(x) \ + (((x) & BIT_MASK_DDMACH5_DLEN_8822C) << BIT_SHIFT_DDMACH5_DLEN_8822C) +#define BITS_DDMACH5_DLEN_8822C \ + (BIT_MASK_DDMACH5_DLEN_8822C << BIT_SHIFT_DDMACH5_DLEN_8822C) +#define BIT_CLEAR_DDMACH5_DLEN_8822C(x) ((x) & (~BITS_DDMACH5_DLEN_8822C)) +#define BIT_GET_DDMACH5_DLEN_8822C(x) \ + (((x) >> BIT_SHIFT_DDMACH5_DLEN_8822C) & BIT_MASK_DDMACH5_DLEN_8822C) +#define BIT_SET_DDMACH5_DLEN_8822C(x, v) \ + (BIT_CLEAR_DDMACH5_DLEN_8822C(x) | BIT_DDMACH5_DLEN_8822C(v)) + +/* 2 REG_DDMA_INT_MSK_8822C */ +#define BIT_DDMACH5_MSK_8822C BIT(5) +#define BIT_DDMACH4_MSK_8822C BIT(4) +#define BIT_DDMACH3_MSK_8822C BIT(3) +#define BIT_DDMACH2_MSK_8822C BIT(2) +#define BIT_DDMACH1_MSK_8822C BIT(1) +#define BIT_DDMACH0_MSK_8822C BIT(0) + +/* 2 REG_DDMA_CHSTATUS_8822C */ +#define BIT_DDMACH5_BUSY_8822C BIT(5) +#define BIT_DDMACH4_BUSY_8822C BIT(4) +#define BIT_DDMACH3_BUSY_8822C BIT(3) +#define BIT_DDMACH2_BUSY_8822C BIT(2) +#define BIT_DDMACH1_BUSY_8822C BIT(1) +#define BIT_DDMACH0_BUSY_8822C BIT(0) + +/* 2 REG_DDMA_CHKSUM_8822C */ + +#define BIT_SHIFT_IDDMA0_CHKSUM_8822C 0 +#define BIT_MASK_IDDMA0_CHKSUM_8822C 0xffff +#define BIT_IDDMA0_CHKSUM_8822C(x) \ + (((x) & BIT_MASK_IDDMA0_CHKSUM_8822C) << BIT_SHIFT_IDDMA0_CHKSUM_8822C) +#define BITS_IDDMA0_CHKSUM_8822C \ + (BIT_MASK_IDDMA0_CHKSUM_8822C << BIT_SHIFT_IDDMA0_CHKSUM_8822C) +#define BIT_CLEAR_IDDMA0_CHKSUM_8822C(x) ((x) & (~BITS_IDDMA0_CHKSUM_8822C)) +#define BIT_GET_IDDMA0_CHKSUM_8822C(x) \ + (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822C) & BIT_MASK_IDDMA0_CHKSUM_8822C) +#define BIT_SET_IDDMA0_CHKSUM_8822C(x, v) \ + (BIT_CLEAR_IDDMA0_CHKSUM_8822C(x) | BIT_IDDMA0_CHKSUM_8822C(v)) + +/* 2 REG_DDMA_MONITOR_8822C */ +#define BIT_IDDMA0_PERMU_UNDERFLOW_8822C BIT(14) +#define BIT_IDDMA0_FIFO_UNDERFLOW_8822C BIT(13) +#define BIT_IDDMA0_FIFO_OVERFLOW_8822C BIT(12) +#define BIT_CH5_ERR_8822C BIT(5) +#define BIT_CH4_ERR_8822C BIT(4) +#define BIT_CH3_ERR_8822C BIT(3) +#define BIT_CH2_ERR_8822C BIT(2) +#define BIT_CH1_ERR_8822C BIT(1) +#define BIT_CH0_ERR_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_PCIE_CTRL_8822C */ +#define BIT_PCIEIO_PERSTB_SEL_8822C BIT(31) + +#define BIT_SHIFT_PCIE_MAX_RXDMA_8822C 28 +#define BIT_MASK_PCIE_MAX_RXDMA_8822C 0x7 +#define BIT_PCIE_MAX_RXDMA_8822C(x) \ + (((x) & BIT_MASK_PCIE_MAX_RXDMA_8822C) \ + << BIT_SHIFT_PCIE_MAX_RXDMA_8822C) +#define BITS_PCIE_MAX_RXDMA_8822C \ + (BIT_MASK_PCIE_MAX_RXDMA_8822C << BIT_SHIFT_PCIE_MAX_RXDMA_8822C) +#define BIT_CLEAR_PCIE_MAX_RXDMA_8822C(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8822C)) +#define BIT_GET_PCIE_MAX_RXDMA_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822C) & \ + BIT_MASK_PCIE_MAX_RXDMA_8822C) +#define BIT_SET_PCIE_MAX_RXDMA_8822C(x, v) \ + (BIT_CLEAR_PCIE_MAX_RXDMA_8822C(x) | BIT_PCIE_MAX_RXDMA_8822C(v)) + +#define BIT_SHIFT_PCIE_MAX_TXDMA_8822C 24 +#define BIT_MASK_PCIE_MAX_TXDMA_8822C 0x7 +#define BIT_PCIE_MAX_TXDMA_8822C(x) \ + (((x) & BIT_MASK_PCIE_MAX_TXDMA_8822C) \ + << BIT_SHIFT_PCIE_MAX_TXDMA_8822C) +#define BITS_PCIE_MAX_TXDMA_8822C \ + (BIT_MASK_PCIE_MAX_TXDMA_8822C << BIT_SHIFT_PCIE_MAX_TXDMA_8822C) +#define BIT_CLEAR_PCIE_MAX_TXDMA_8822C(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8822C)) +#define BIT_GET_PCIE_MAX_TXDMA_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822C) & \ + BIT_MASK_PCIE_MAX_TXDMA_8822C) +#define BIT_SET_PCIE_MAX_TXDMA_8822C(x, v) \ + (BIT_CLEAR_PCIE_MAX_TXDMA_8822C(x) | BIT_PCIE_MAX_TXDMA_8822C(v)) + +#define BIT_EN_CPL_TIMEOUT_PS_8822C BIT(22) +#define BIT_REG_TXDMA_FAIL_PS_8822C BIT(21) +#define BIT_PCIE_RST_TRXDMA_INTF_8822C BIT(20) +#define BIT_EN_HWENTR_L1_8822C BIT(19) +#define BIT_EN_ADV_CLKGATE_8822C BIT(18) +#define BIT_PCIE_EN_SWENT_L23_8822C BIT(17) +#define BIT_PCIE_EN_HWEXT_L1_8822C BIT(16) +#define BIT_RX_CLOSE_EN_8822C BIT(15) +#define BIT_STOP_BCNQ_8822C BIT(14) +#define BIT_STOP_MGQ_8822C BIT(13) +#define BIT_STOP_VOQ_8822C BIT(12) +#define BIT_STOP_VIQ_8822C BIT(11) +#define BIT_STOP_BEQ_8822C BIT(10) +#define BIT_STOP_BKQ_8822C BIT(9) +#define BIT_STOP_RXQ_8822C BIT(8) +#define BIT_STOP_HI7Q_8822C BIT(7) +#define BIT_STOP_HI6Q_8822C BIT(6) +#define BIT_STOP_HI5Q_8822C BIT(5) +#define BIT_STOP_HI4Q_8822C BIT(4) +#define BIT_STOP_HI3Q_8822C BIT(3) +#define BIT_STOP_HI2Q_8822C BIT(2) +#define BIT_STOP_HI1Q_8822C BIT(1) +#define BIT_STOP_HI0Q_8822C BIT(0) + +/* 2 REG_INT_MIG_8822C */ + +#define BIT_SHIFT_TRXCOUNTER_MATCH_8822C 24 +#define BIT_MASK_TRXCOUNTER_MATCH_8822C 0xff +#define BIT_TRXCOUNTER_MATCH_8822C(x) \ + (((x) & BIT_MASK_TRXCOUNTER_MATCH_8822C) \ + << BIT_SHIFT_TRXCOUNTER_MATCH_8822C) +#define BITS_TRXCOUNTER_MATCH_8822C \ + (BIT_MASK_TRXCOUNTER_MATCH_8822C << BIT_SHIFT_TRXCOUNTER_MATCH_8822C) +#define BIT_CLEAR_TRXCOUNTER_MATCH_8822C(x) \ + ((x) & (~BITS_TRXCOUNTER_MATCH_8822C)) +#define BIT_GET_TRXCOUNTER_MATCH_8822C(x) \ + (((x) >> BIT_SHIFT_TRXCOUNTER_MATCH_8822C) & \ + BIT_MASK_TRXCOUNTER_MATCH_8822C) +#define BIT_SET_TRXCOUNTER_MATCH_8822C(x, v) \ + (BIT_CLEAR_TRXCOUNTER_MATCH_8822C(x) | BIT_TRXCOUNTER_MATCH_8822C(v)) + +#define BIT_SHIFT_TRXTIMER_MATCH_8822C 16 +#define BIT_MASK_TRXTIMER_MATCH_8822C 0xff +#define BIT_TRXTIMER_MATCH_8822C(x) \ + (((x) & BIT_MASK_TRXTIMER_MATCH_8822C) \ + << BIT_SHIFT_TRXTIMER_MATCH_8822C) +#define BITS_TRXTIMER_MATCH_8822C \ + (BIT_MASK_TRXTIMER_MATCH_8822C << BIT_SHIFT_TRXTIMER_MATCH_8822C) +#define BIT_CLEAR_TRXTIMER_MATCH_8822C(x) ((x) & (~BITS_TRXTIMER_MATCH_8822C)) +#define BIT_GET_TRXTIMER_MATCH_8822C(x) \ + (((x) >> BIT_SHIFT_TRXTIMER_MATCH_8822C) & \ + BIT_MASK_TRXTIMER_MATCH_8822C) +#define BIT_SET_TRXTIMER_MATCH_8822C(x, v) \ + (BIT_CLEAR_TRXTIMER_MATCH_8822C(x) | BIT_TRXTIMER_MATCH_8822C(v)) + +#define BIT_SHIFT_TRXTIMER_UNIT_8822C 0 +#define BIT_MASK_TRXTIMER_UNIT_8822C 0x3 +#define BIT_TRXTIMER_UNIT_8822C(x) \ + (((x) & BIT_MASK_TRXTIMER_UNIT_8822C) << BIT_SHIFT_TRXTIMER_UNIT_8822C) +#define BITS_TRXTIMER_UNIT_8822C \ + (BIT_MASK_TRXTIMER_UNIT_8822C << BIT_SHIFT_TRXTIMER_UNIT_8822C) +#define BIT_CLEAR_TRXTIMER_UNIT_8822C(x) ((x) & (~BITS_TRXTIMER_UNIT_8822C)) +#define BIT_GET_TRXTIMER_UNIT_8822C(x) \ + (((x) >> BIT_SHIFT_TRXTIMER_UNIT_8822C) & BIT_MASK_TRXTIMER_UNIT_8822C) +#define BIT_SET_TRXTIMER_UNIT_8822C(x, v) \ + (BIT_CLEAR_TRXTIMER_UNIT_8822C(x) | BIT_TRXTIMER_UNIT_8822C(v)) + +/* 2 REG_BCNQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_BCNQ_TXBD_DESA_8822C 0 +#define BIT_MASK_BCNQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_BCNQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_BCNQ_TXBD_DESA_8822C) \ + << BIT_SHIFT_BCNQ_TXBD_DESA_8822C) +#define BITS_BCNQ_TXBD_DESA_8822C \ + (BIT_MASK_BCNQ_TXBD_DESA_8822C << BIT_SHIFT_BCNQ_TXBD_DESA_8822C) +#define BIT_CLEAR_BCNQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8822C)) +#define BIT_GET_BCNQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822C) & \ + BIT_MASK_BCNQ_TXBD_DESA_8822C) +#define BIT_SET_BCNQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_BCNQ_TXBD_DESA_8822C(x) | BIT_BCNQ_TXBD_DESA_8822C(v)) + +/* 2 REG_MGQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_MGQ_TXBD_DESA_8822C 0 +#define BIT_MASK_MGQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_MGQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_MGQ_TXBD_DESA_8822C) << BIT_SHIFT_MGQ_TXBD_DESA_8822C) +#define BITS_MGQ_TXBD_DESA_8822C \ + (BIT_MASK_MGQ_TXBD_DESA_8822C << BIT_SHIFT_MGQ_TXBD_DESA_8822C) +#define BIT_CLEAR_MGQ_TXBD_DESA_8822C(x) ((x) & (~BITS_MGQ_TXBD_DESA_8822C)) +#define BIT_GET_MGQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822C) & BIT_MASK_MGQ_TXBD_DESA_8822C) +#define BIT_SET_MGQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_MGQ_TXBD_DESA_8822C(x) | BIT_MGQ_TXBD_DESA_8822C(v)) + +/* 2 REG_VOQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_VOQ_TXBD_DESA_8822C 0 +#define BIT_MASK_VOQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_VOQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_VOQ_TXBD_DESA_8822C) << BIT_SHIFT_VOQ_TXBD_DESA_8822C) +#define BITS_VOQ_TXBD_DESA_8822C \ + (BIT_MASK_VOQ_TXBD_DESA_8822C << BIT_SHIFT_VOQ_TXBD_DESA_8822C) +#define BIT_CLEAR_VOQ_TXBD_DESA_8822C(x) ((x) & (~BITS_VOQ_TXBD_DESA_8822C)) +#define BIT_GET_VOQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822C) & BIT_MASK_VOQ_TXBD_DESA_8822C) +#define BIT_SET_VOQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_VOQ_TXBD_DESA_8822C(x) | BIT_VOQ_TXBD_DESA_8822C(v)) + +/* 2 REG_VIQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_VIQ_TXBD_DESA_8822C 0 +#define BIT_MASK_VIQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_VIQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_VIQ_TXBD_DESA_8822C) << BIT_SHIFT_VIQ_TXBD_DESA_8822C) +#define BITS_VIQ_TXBD_DESA_8822C \ + (BIT_MASK_VIQ_TXBD_DESA_8822C << BIT_SHIFT_VIQ_TXBD_DESA_8822C) +#define BIT_CLEAR_VIQ_TXBD_DESA_8822C(x) ((x) & (~BITS_VIQ_TXBD_DESA_8822C)) +#define BIT_GET_VIQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822C) & BIT_MASK_VIQ_TXBD_DESA_8822C) +#define BIT_SET_VIQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_VIQ_TXBD_DESA_8822C(x) | BIT_VIQ_TXBD_DESA_8822C(v)) + +/* 2 REG_BEQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_BEQ_TXBD_DESA_8822C 0 +#define BIT_MASK_BEQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_BEQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_BEQ_TXBD_DESA_8822C) << BIT_SHIFT_BEQ_TXBD_DESA_8822C) +#define BITS_BEQ_TXBD_DESA_8822C \ + (BIT_MASK_BEQ_TXBD_DESA_8822C << BIT_SHIFT_BEQ_TXBD_DESA_8822C) +#define BIT_CLEAR_BEQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BEQ_TXBD_DESA_8822C)) +#define BIT_GET_BEQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822C) & BIT_MASK_BEQ_TXBD_DESA_8822C) +#define BIT_SET_BEQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_BEQ_TXBD_DESA_8822C(x) | BIT_BEQ_TXBD_DESA_8822C(v)) + +/* 2 REG_BKQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_BKQ_TXBD_DESA_8822C 0 +#define BIT_MASK_BKQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_BKQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_BKQ_TXBD_DESA_8822C) << BIT_SHIFT_BKQ_TXBD_DESA_8822C) +#define BITS_BKQ_TXBD_DESA_8822C \ + (BIT_MASK_BKQ_TXBD_DESA_8822C << BIT_SHIFT_BKQ_TXBD_DESA_8822C) +#define BIT_CLEAR_BKQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BKQ_TXBD_DESA_8822C)) +#define BIT_GET_BKQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822C) & BIT_MASK_BKQ_TXBD_DESA_8822C) +#define BIT_SET_BKQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_BKQ_TXBD_DESA_8822C(x) | BIT_BKQ_TXBD_DESA_8822C(v)) + +/* 2 REG_RXQ_RXBD_DESA_8822C */ + +#define BIT_SHIFT_RXQ_RXBD_DESA_8822C 0 +#define BIT_MASK_RXQ_RXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_RXQ_RXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_RXQ_RXBD_DESA_8822C) << BIT_SHIFT_RXQ_RXBD_DESA_8822C) +#define BITS_RXQ_RXBD_DESA_8822C \ + (BIT_MASK_RXQ_RXBD_DESA_8822C << BIT_SHIFT_RXQ_RXBD_DESA_8822C) +#define BIT_CLEAR_RXQ_RXBD_DESA_8822C(x) ((x) & (~BITS_RXQ_RXBD_DESA_8822C)) +#define BIT_GET_RXQ_RXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822C) & BIT_MASK_RXQ_RXBD_DESA_8822C) +#define BIT_SET_RXQ_RXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_RXQ_RXBD_DESA_8822C(x) | BIT_RXQ_RXBD_DESA_8822C(v)) + +/* 2 REG_HI0Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI0Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI0Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI0Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI0Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI0Q_TXBD_DESA_8822C) +#define BITS_HI0Q_TXBD_DESA_8822C \ + (BIT_MASK_HI0Q_TXBD_DESA_8822C << BIT_SHIFT_HI0Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI0Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8822C)) +#define BIT_GET_HI0Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI0Q_TXBD_DESA_8822C) +#define BIT_SET_HI0Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI0Q_TXBD_DESA_8822C(x) | BIT_HI0Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI1Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI1Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI1Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI1Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI1Q_TXBD_DESA_8822C) +#define BITS_HI1Q_TXBD_DESA_8822C \ + (BIT_MASK_HI1Q_TXBD_DESA_8822C << BIT_SHIFT_HI1Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI1Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8822C)) +#define BIT_GET_HI1Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI1Q_TXBD_DESA_8822C) +#define BIT_SET_HI1Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI1Q_TXBD_DESA_8822C(x) | BIT_HI1Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI2Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI2Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI2Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI2Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI2Q_TXBD_DESA_8822C) +#define BITS_HI2Q_TXBD_DESA_8822C \ + (BIT_MASK_HI2Q_TXBD_DESA_8822C << BIT_SHIFT_HI2Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI2Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8822C)) +#define BIT_GET_HI2Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI2Q_TXBD_DESA_8822C) +#define BIT_SET_HI2Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI2Q_TXBD_DESA_8822C(x) | BIT_HI2Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI3Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI3Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI3Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI3Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI3Q_TXBD_DESA_8822C) +#define BITS_HI3Q_TXBD_DESA_8822C \ + (BIT_MASK_HI3Q_TXBD_DESA_8822C << BIT_SHIFT_HI3Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI3Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8822C)) +#define BIT_GET_HI3Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI3Q_TXBD_DESA_8822C) +#define BIT_SET_HI3Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI3Q_TXBD_DESA_8822C(x) | BIT_HI3Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI4Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI4Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI4Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI4Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI4Q_TXBD_DESA_8822C) +#define BITS_HI4Q_TXBD_DESA_8822C \ + (BIT_MASK_HI4Q_TXBD_DESA_8822C << BIT_SHIFT_HI4Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI4Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8822C)) +#define BIT_GET_HI4Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI4Q_TXBD_DESA_8822C) +#define BIT_SET_HI4Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI4Q_TXBD_DESA_8822C(x) | BIT_HI4Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI5Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI5Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI5Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI5Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI5Q_TXBD_DESA_8822C) +#define BITS_HI5Q_TXBD_DESA_8822C \ + (BIT_MASK_HI5Q_TXBD_DESA_8822C << BIT_SHIFT_HI5Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI5Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8822C)) +#define BIT_GET_HI5Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI5Q_TXBD_DESA_8822C) +#define BIT_SET_HI5Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI5Q_TXBD_DESA_8822C(x) | BIT_HI5Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI6Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI6Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI6Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI6Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI6Q_TXBD_DESA_8822C) +#define BITS_HI6Q_TXBD_DESA_8822C \ + (BIT_MASK_HI6Q_TXBD_DESA_8822C << BIT_SHIFT_HI6Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI6Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8822C)) +#define BIT_GET_HI6Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI6Q_TXBD_DESA_8822C) +#define BIT_SET_HI6Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI6Q_TXBD_DESA_8822C(x) | BIT_HI6Q_TXBD_DESA_8822C(v)) + +/* 2 REG_HI7Q_TXBD_DESA_8822C */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_8822C 0 +#define BIT_MASK_HI7Q_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_HI7Q_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_HI7Q_TXBD_DESA_8822C) \ + << BIT_SHIFT_HI7Q_TXBD_DESA_8822C) +#define BITS_HI7Q_TXBD_DESA_8822C \ + (BIT_MASK_HI7Q_TXBD_DESA_8822C << BIT_SHIFT_HI7Q_TXBD_DESA_8822C) +#define BIT_CLEAR_HI7Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8822C)) +#define BIT_GET_HI7Q_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822C) & \ + BIT_MASK_HI7Q_TXBD_DESA_8822C) +#define BIT_SET_HI7Q_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_HI7Q_TXBD_DESA_8822C(x) | BIT_HI7Q_TXBD_DESA_8822C(v)) + +/* 2 REG_MGQ_TXBD_NUM_8822C */ +#define BIT_PCIE_MGQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_MGQ_DESC_MODE_8822C 12 +#define BIT_MASK_MGQ_DESC_MODE_8822C 0x3 +#define BIT_MGQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_MGQ_DESC_MODE_8822C) << BIT_SHIFT_MGQ_DESC_MODE_8822C) +#define BITS_MGQ_DESC_MODE_8822C \ + (BIT_MASK_MGQ_DESC_MODE_8822C << BIT_SHIFT_MGQ_DESC_MODE_8822C) +#define BIT_CLEAR_MGQ_DESC_MODE_8822C(x) ((x) & (~BITS_MGQ_DESC_MODE_8822C)) +#define BIT_GET_MGQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822C) & BIT_MASK_MGQ_DESC_MODE_8822C) +#define BIT_SET_MGQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_MGQ_DESC_MODE_8822C(x) | BIT_MGQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_MGQ_DESC_NUM_8822C 0 +#define BIT_MASK_MGQ_DESC_NUM_8822C 0xfff +#define BIT_MGQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_MGQ_DESC_NUM_8822C) << BIT_SHIFT_MGQ_DESC_NUM_8822C) +#define BITS_MGQ_DESC_NUM_8822C \ + (BIT_MASK_MGQ_DESC_NUM_8822C << BIT_SHIFT_MGQ_DESC_NUM_8822C) +#define BIT_CLEAR_MGQ_DESC_NUM_8822C(x) ((x) & (~BITS_MGQ_DESC_NUM_8822C)) +#define BIT_GET_MGQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822C) & BIT_MASK_MGQ_DESC_NUM_8822C) +#define BIT_SET_MGQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_MGQ_DESC_NUM_8822C(x) | BIT_MGQ_DESC_NUM_8822C(v)) + +/* 2 REG_RX_RXBD_NUM_8822C */ +#define BIT_SYS_32_64_8822C BIT(15) + +#define BIT_SHIFT_BCNQ_DESC_MODE_8822C 13 +#define BIT_MASK_BCNQ_DESC_MODE_8822C 0x3 +#define BIT_BCNQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_BCNQ_DESC_MODE_8822C) \ + << BIT_SHIFT_BCNQ_DESC_MODE_8822C) +#define BITS_BCNQ_DESC_MODE_8822C \ + (BIT_MASK_BCNQ_DESC_MODE_8822C << BIT_SHIFT_BCNQ_DESC_MODE_8822C) +#define BIT_CLEAR_BCNQ_DESC_MODE_8822C(x) ((x) & (~BITS_BCNQ_DESC_MODE_8822C)) +#define BIT_GET_BCNQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822C) & \ + BIT_MASK_BCNQ_DESC_MODE_8822C) +#define BIT_SET_BCNQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_BCNQ_DESC_MODE_8822C(x) | BIT_BCNQ_DESC_MODE_8822C(v)) + +#define BIT_PCIE_BCNQ_FLAG_8822C BIT(12) + +#define BIT_SHIFT_RXQ_DESC_NUM_8822C 0 +#define BIT_MASK_RXQ_DESC_NUM_8822C 0xfff +#define BIT_RXQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_RXQ_DESC_NUM_8822C) << BIT_SHIFT_RXQ_DESC_NUM_8822C) +#define BITS_RXQ_DESC_NUM_8822C \ + (BIT_MASK_RXQ_DESC_NUM_8822C << BIT_SHIFT_RXQ_DESC_NUM_8822C) +#define BIT_CLEAR_RXQ_DESC_NUM_8822C(x) ((x) & (~BITS_RXQ_DESC_NUM_8822C)) +#define BIT_GET_RXQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822C) & BIT_MASK_RXQ_DESC_NUM_8822C) +#define BIT_SET_RXQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_RXQ_DESC_NUM_8822C(x) | BIT_RXQ_DESC_NUM_8822C(v)) + +/* 2 REG_VOQ_TXBD_NUM_8822C */ +#define BIT_PCIE_VOQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_VOQ_DESC_MODE_8822C 12 +#define BIT_MASK_VOQ_DESC_MODE_8822C 0x3 +#define BIT_VOQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_VOQ_DESC_MODE_8822C) << BIT_SHIFT_VOQ_DESC_MODE_8822C) +#define BITS_VOQ_DESC_MODE_8822C \ + (BIT_MASK_VOQ_DESC_MODE_8822C << BIT_SHIFT_VOQ_DESC_MODE_8822C) +#define BIT_CLEAR_VOQ_DESC_MODE_8822C(x) ((x) & (~BITS_VOQ_DESC_MODE_8822C)) +#define BIT_GET_VOQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822C) & BIT_MASK_VOQ_DESC_MODE_8822C) +#define BIT_SET_VOQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_VOQ_DESC_MODE_8822C(x) | BIT_VOQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_VOQ_DESC_NUM_8822C 0 +#define BIT_MASK_VOQ_DESC_NUM_8822C 0xfff +#define BIT_VOQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_VOQ_DESC_NUM_8822C) << BIT_SHIFT_VOQ_DESC_NUM_8822C) +#define BITS_VOQ_DESC_NUM_8822C \ + (BIT_MASK_VOQ_DESC_NUM_8822C << BIT_SHIFT_VOQ_DESC_NUM_8822C) +#define BIT_CLEAR_VOQ_DESC_NUM_8822C(x) ((x) & (~BITS_VOQ_DESC_NUM_8822C)) +#define BIT_GET_VOQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822C) & BIT_MASK_VOQ_DESC_NUM_8822C) +#define BIT_SET_VOQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_VOQ_DESC_NUM_8822C(x) | BIT_VOQ_DESC_NUM_8822C(v)) + +/* 2 REG_VIQ_TXBD_NUM_8822C */ +#define BIT_PCIE_VIQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_VIQ_DESC_MODE_8822C 12 +#define BIT_MASK_VIQ_DESC_MODE_8822C 0x3 +#define BIT_VIQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_VIQ_DESC_MODE_8822C) << BIT_SHIFT_VIQ_DESC_MODE_8822C) +#define BITS_VIQ_DESC_MODE_8822C \ + (BIT_MASK_VIQ_DESC_MODE_8822C << BIT_SHIFT_VIQ_DESC_MODE_8822C) +#define BIT_CLEAR_VIQ_DESC_MODE_8822C(x) ((x) & (~BITS_VIQ_DESC_MODE_8822C)) +#define BIT_GET_VIQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822C) & BIT_MASK_VIQ_DESC_MODE_8822C) +#define BIT_SET_VIQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_VIQ_DESC_MODE_8822C(x) | BIT_VIQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_VIQ_DESC_NUM_8822C 0 +#define BIT_MASK_VIQ_DESC_NUM_8822C 0xfff +#define BIT_VIQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_VIQ_DESC_NUM_8822C) << BIT_SHIFT_VIQ_DESC_NUM_8822C) +#define BITS_VIQ_DESC_NUM_8822C \ + (BIT_MASK_VIQ_DESC_NUM_8822C << BIT_SHIFT_VIQ_DESC_NUM_8822C) +#define BIT_CLEAR_VIQ_DESC_NUM_8822C(x) ((x) & (~BITS_VIQ_DESC_NUM_8822C)) +#define BIT_GET_VIQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822C) & BIT_MASK_VIQ_DESC_NUM_8822C) +#define BIT_SET_VIQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_VIQ_DESC_NUM_8822C(x) | BIT_VIQ_DESC_NUM_8822C(v)) + +/* 2 REG_BEQ_TXBD_NUM_8822C */ +#define BIT_PCIE_BEQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_BEQ_DESC_MODE_8822C 12 +#define BIT_MASK_BEQ_DESC_MODE_8822C 0x3 +#define BIT_BEQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_BEQ_DESC_MODE_8822C) << BIT_SHIFT_BEQ_DESC_MODE_8822C) +#define BITS_BEQ_DESC_MODE_8822C \ + (BIT_MASK_BEQ_DESC_MODE_8822C << BIT_SHIFT_BEQ_DESC_MODE_8822C) +#define BIT_CLEAR_BEQ_DESC_MODE_8822C(x) ((x) & (~BITS_BEQ_DESC_MODE_8822C)) +#define BIT_GET_BEQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822C) & BIT_MASK_BEQ_DESC_MODE_8822C) +#define BIT_SET_BEQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_BEQ_DESC_MODE_8822C(x) | BIT_BEQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_BEQ_DESC_NUM_8822C 0 +#define BIT_MASK_BEQ_DESC_NUM_8822C 0xfff +#define BIT_BEQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_BEQ_DESC_NUM_8822C) << BIT_SHIFT_BEQ_DESC_NUM_8822C) +#define BITS_BEQ_DESC_NUM_8822C \ + (BIT_MASK_BEQ_DESC_NUM_8822C << BIT_SHIFT_BEQ_DESC_NUM_8822C) +#define BIT_CLEAR_BEQ_DESC_NUM_8822C(x) ((x) & (~BITS_BEQ_DESC_NUM_8822C)) +#define BIT_GET_BEQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822C) & BIT_MASK_BEQ_DESC_NUM_8822C) +#define BIT_SET_BEQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_BEQ_DESC_NUM_8822C(x) | BIT_BEQ_DESC_NUM_8822C(v)) + +/* 2 REG_BKQ_TXBD_NUM_8822C */ +#define BIT_PCIE_BKQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_BKQ_DESC_MODE_8822C 12 +#define BIT_MASK_BKQ_DESC_MODE_8822C 0x3 +#define BIT_BKQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_BKQ_DESC_MODE_8822C) << BIT_SHIFT_BKQ_DESC_MODE_8822C) +#define BITS_BKQ_DESC_MODE_8822C \ + (BIT_MASK_BKQ_DESC_MODE_8822C << BIT_SHIFT_BKQ_DESC_MODE_8822C) +#define BIT_CLEAR_BKQ_DESC_MODE_8822C(x) ((x) & (~BITS_BKQ_DESC_MODE_8822C)) +#define BIT_GET_BKQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822C) & BIT_MASK_BKQ_DESC_MODE_8822C) +#define BIT_SET_BKQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_BKQ_DESC_MODE_8822C(x) | BIT_BKQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_BKQ_DESC_NUM_8822C 0 +#define BIT_MASK_BKQ_DESC_NUM_8822C 0xfff +#define BIT_BKQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_BKQ_DESC_NUM_8822C) << BIT_SHIFT_BKQ_DESC_NUM_8822C) +#define BITS_BKQ_DESC_NUM_8822C \ + (BIT_MASK_BKQ_DESC_NUM_8822C << BIT_SHIFT_BKQ_DESC_NUM_8822C) +#define BIT_CLEAR_BKQ_DESC_NUM_8822C(x) ((x) & (~BITS_BKQ_DESC_NUM_8822C)) +#define BIT_GET_BKQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822C) & BIT_MASK_BKQ_DESC_NUM_8822C) +#define BIT_SET_BKQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_BKQ_DESC_NUM_8822C(x) | BIT_BKQ_DESC_NUM_8822C(v)) + +/* 2 REG_HI0Q_TXBD_NUM_8822C */ +#define BIT_HI0Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI0Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI0Q_DESC_MODE_8822C 0x3 +#define BIT_HI0Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI0Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI0Q_DESC_MODE_8822C) +#define BITS_HI0Q_DESC_MODE_8822C \ + (BIT_MASK_HI0Q_DESC_MODE_8822C << BIT_SHIFT_HI0Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI0Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI0Q_DESC_MODE_8822C)) +#define BIT_GET_HI0Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822C) & \ + BIT_MASK_HI0Q_DESC_MODE_8822C) +#define BIT_SET_HI0Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI0Q_DESC_MODE_8822C(x) | BIT_HI0Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI0Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI0Q_DESC_NUM_8822C 0xfff +#define BIT_HI0Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI0Q_DESC_NUM_8822C) << BIT_SHIFT_HI0Q_DESC_NUM_8822C) +#define BITS_HI0Q_DESC_NUM_8822C \ + (BIT_MASK_HI0Q_DESC_NUM_8822C << BIT_SHIFT_HI0Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI0Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI0Q_DESC_NUM_8822C)) +#define BIT_GET_HI0Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822C) & BIT_MASK_HI0Q_DESC_NUM_8822C) +#define BIT_SET_HI0Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI0Q_DESC_NUM_8822C(x) | BIT_HI0Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI1Q_TXBD_NUM_8822C */ +#define BIT_HI1Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI1Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI1Q_DESC_MODE_8822C 0x3 +#define BIT_HI1Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI1Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI1Q_DESC_MODE_8822C) +#define BITS_HI1Q_DESC_MODE_8822C \ + (BIT_MASK_HI1Q_DESC_MODE_8822C << BIT_SHIFT_HI1Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI1Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI1Q_DESC_MODE_8822C)) +#define BIT_GET_HI1Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822C) & \ + BIT_MASK_HI1Q_DESC_MODE_8822C) +#define BIT_SET_HI1Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI1Q_DESC_MODE_8822C(x) | BIT_HI1Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI1Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI1Q_DESC_NUM_8822C 0xfff +#define BIT_HI1Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI1Q_DESC_NUM_8822C) << BIT_SHIFT_HI1Q_DESC_NUM_8822C) +#define BITS_HI1Q_DESC_NUM_8822C \ + (BIT_MASK_HI1Q_DESC_NUM_8822C << BIT_SHIFT_HI1Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI1Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI1Q_DESC_NUM_8822C)) +#define BIT_GET_HI1Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822C) & BIT_MASK_HI1Q_DESC_NUM_8822C) +#define BIT_SET_HI1Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI1Q_DESC_NUM_8822C(x) | BIT_HI1Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI2Q_TXBD_NUM_8822C */ +#define BIT_HI2Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI2Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI2Q_DESC_MODE_8822C 0x3 +#define BIT_HI2Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI2Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI2Q_DESC_MODE_8822C) +#define BITS_HI2Q_DESC_MODE_8822C \ + (BIT_MASK_HI2Q_DESC_MODE_8822C << BIT_SHIFT_HI2Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI2Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI2Q_DESC_MODE_8822C)) +#define BIT_GET_HI2Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822C) & \ + BIT_MASK_HI2Q_DESC_MODE_8822C) +#define BIT_SET_HI2Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI2Q_DESC_MODE_8822C(x) | BIT_HI2Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI2Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI2Q_DESC_NUM_8822C 0xfff +#define BIT_HI2Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI2Q_DESC_NUM_8822C) << BIT_SHIFT_HI2Q_DESC_NUM_8822C) +#define BITS_HI2Q_DESC_NUM_8822C \ + (BIT_MASK_HI2Q_DESC_NUM_8822C << BIT_SHIFT_HI2Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI2Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI2Q_DESC_NUM_8822C)) +#define BIT_GET_HI2Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822C) & BIT_MASK_HI2Q_DESC_NUM_8822C) +#define BIT_SET_HI2Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI2Q_DESC_NUM_8822C(x) | BIT_HI2Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI3Q_TXBD_NUM_8822C */ +#define BIT_HI3Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI3Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI3Q_DESC_MODE_8822C 0x3 +#define BIT_HI3Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI3Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI3Q_DESC_MODE_8822C) +#define BITS_HI3Q_DESC_MODE_8822C \ + (BIT_MASK_HI3Q_DESC_MODE_8822C << BIT_SHIFT_HI3Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI3Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI3Q_DESC_MODE_8822C)) +#define BIT_GET_HI3Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822C) & \ + BIT_MASK_HI3Q_DESC_MODE_8822C) +#define BIT_SET_HI3Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI3Q_DESC_MODE_8822C(x) | BIT_HI3Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI3Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI3Q_DESC_NUM_8822C 0xfff +#define BIT_HI3Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI3Q_DESC_NUM_8822C) << BIT_SHIFT_HI3Q_DESC_NUM_8822C) +#define BITS_HI3Q_DESC_NUM_8822C \ + (BIT_MASK_HI3Q_DESC_NUM_8822C << BIT_SHIFT_HI3Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI3Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI3Q_DESC_NUM_8822C)) +#define BIT_GET_HI3Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822C) & BIT_MASK_HI3Q_DESC_NUM_8822C) +#define BIT_SET_HI3Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI3Q_DESC_NUM_8822C(x) | BIT_HI3Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI4Q_TXBD_NUM_8822C */ +#define BIT_HI4Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI4Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI4Q_DESC_MODE_8822C 0x3 +#define BIT_HI4Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI4Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI4Q_DESC_MODE_8822C) +#define BITS_HI4Q_DESC_MODE_8822C \ + (BIT_MASK_HI4Q_DESC_MODE_8822C << BIT_SHIFT_HI4Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI4Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI4Q_DESC_MODE_8822C)) +#define BIT_GET_HI4Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822C) & \ + BIT_MASK_HI4Q_DESC_MODE_8822C) +#define BIT_SET_HI4Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI4Q_DESC_MODE_8822C(x) | BIT_HI4Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI4Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI4Q_DESC_NUM_8822C 0xfff +#define BIT_HI4Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI4Q_DESC_NUM_8822C) << BIT_SHIFT_HI4Q_DESC_NUM_8822C) +#define BITS_HI4Q_DESC_NUM_8822C \ + (BIT_MASK_HI4Q_DESC_NUM_8822C << BIT_SHIFT_HI4Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI4Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI4Q_DESC_NUM_8822C)) +#define BIT_GET_HI4Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822C) & BIT_MASK_HI4Q_DESC_NUM_8822C) +#define BIT_SET_HI4Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI4Q_DESC_NUM_8822C(x) | BIT_HI4Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI5Q_TXBD_NUM_8822C */ +#define BIT_HI5Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI5Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI5Q_DESC_MODE_8822C 0x3 +#define BIT_HI5Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI5Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI5Q_DESC_MODE_8822C) +#define BITS_HI5Q_DESC_MODE_8822C \ + (BIT_MASK_HI5Q_DESC_MODE_8822C << BIT_SHIFT_HI5Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI5Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI5Q_DESC_MODE_8822C)) +#define BIT_GET_HI5Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822C) & \ + BIT_MASK_HI5Q_DESC_MODE_8822C) +#define BIT_SET_HI5Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI5Q_DESC_MODE_8822C(x) | BIT_HI5Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI5Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI5Q_DESC_NUM_8822C 0xfff +#define BIT_HI5Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI5Q_DESC_NUM_8822C) << BIT_SHIFT_HI5Q_DESC_NUM_8822C) +#define BITS_HI5Q_DESC_NUM_8822C \ + (BIT_MASK_HI5Q_DESC_NUM_8822C << BIT_SHIFT_HI5Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI5Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI5Q_DESC_NUM_8822C)) +#define BIT_GET_HI5Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822C) & BIT_MASK_HI5Q_DESC_NUM_8822C) +#define BIT_SET_HI5Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI5Q_DESC_NUM_8822C(x) | BIT_HI5Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI6Q_TXBD_NUM_8822C */ +#define BIT_HI6Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI6Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI6Q_DESC_MODE_8822C 0x3 +#define BIT_HI6Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI6Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI6Q_DESC_MODE_8822C) +#define BITS_HI6Q_DESC_MODE_8822C \ + (BIT_MASK_HI6Q_DESC_MODE_8822C << BIT_SHIFT_HI6Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI6Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI6Q_DESC_MODE_8822C)) +#define BIT_GET_HI6Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822C) & \ + BIT_MASK_HI6Q_DESC_MODE_8822C) +#define BIT_SET_HI6Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI6Q_DESC_MODE_8822C(x) | BIT_HI6Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI6Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI6Q_DESC_NUM_8822C 0xfff +#define BIT_HI6Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI6Q_DESC_NUM_8822C) << BIT_SHIFT_HI6Q_DESC_NUM_8822C) +#define BITS_HI6Q_DESC_NUM_8822C \ + (BIT_MASK_HI6Q_DESC_NUM_8822C << BIT_SHIFT_HI6Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI6Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI6Q_DESC_NUM_8822C)) +#define BIT_GET_HI6Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822C) & BIT_MASK_HI6Q_DESC_NUM_8822C) +#define BIT_SET_HI6Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI6Q_DESC_NUM_8822C(x) | BIT_HI6Q_DESC_NUM_8822C(v)) + +/* 2 REG_HI7Q_TXBD_NUM_8822C */ +#define BIT_HI7Q_FLAG_8822C BIT(14) + +#define BIT_SHIFT_HI7Q_DESC_MODE_8822C 12 +#define BIT_MASK_HI7Q_DESC_MODE_8822C 0x3 +#define BIT_HI7Q_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_HI7Q_DESC_MODE_8822C) \ + << BIT_SHIFT_HI7Q_DESC_MODE_8822C) +#define BITS_HI7Q_DESC_MODE_8822C \ + (BIT_MASK_HI7Q_DESC_MODE_8822C << BIT_SHIFT_HI7Q_DESC_MODE_8822C) +#define BIT_CLEAR_HI7Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI7Q_DESC_MODE_8822C)) +#define BIT_GET_HI7Q_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822C) & \ + BIT_MASK_HI7Q_DESC_MODE_8822C) +#define BIT_SET_HI7Q_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_HI7Q_DESC_MODE_8822C(x) | BIT_HI7Q_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_HI7Q_DESC_NUM_8822C 0 +#define BIT_MASK_HI7Q_DESC_NUM_8822C 0xfff +#define BIT_HI7Q_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_HI7Q_DESC_NUM_8822C) << BIT_SHIFT_HI7Q_DESC_NUM_8822C) +#define BITS_HI7Q_DESC_NUM_8822C \ + (BIT_MASK_HI7Q_DESC_NUM_8822C << BIT_SHIFT_HI7Q_DESC_NUM_8822C) +#define BIT_CLEAR_HI7Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI7Q_DESC_NUM_8822C)) +#define BIT_GET_HI7Q_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822C) & BIT_MASK_HI7Q_DESC_NUM_8822C) +#define BIT_SET_HI7Q_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_HI7Q_DESC_NUM_8822C(x) | BIT_HI7Q_DESC_NUM_8822C(v)) + +/* 2 REG_TSFTIMER_HCI_8822C */ + +#define BIT_SHIFT_TSFT2_HCI_8822C 16 +#define BIT_MASK_TSFT2_HCI_8822C 0xffff +#define BIT_TSFT2_HCI_8822C(x) \ + (((x) & BIT_MASK_TSFT2_HCI_8822C) << BIT_SHIFT_TSFT2_HCI_8822C) +#define BITS_TSFT2_HCI_8822C \ + (BIT_MASK_TSFT2_HCI_8822C << BIT_SHIFT_TSFT2_HCI_8822C) +#define BIT_CLEAR_TSFT2_HCI_8822C(x) ((x) & (~BITS_TSFT2_HCI_8822C)) +#define BIT_GET_TSFT2_HCI_8822C(x) \ + (((x) >> BIT_SHIFT_TSFT2_HCI_8822C) & BIT_MASK_TSFT2_HCI_8822C) +#define BIT_SET_TSFT2_HCI_8822C(x, v) \ + (BIT_CLEAR_TSFT2_HCI_8822C(x) | BIT_TSFT2_HCI_8822C(v)) + +#define BIT_SHIFT_TSFT1_HCI_8822C 0 +#define BIT_MASK_TSFT1_HCI_8822C 0xffff +#define BIT_TSFT1_HCI_8822C(x) \ + (((x) & BIT_MASK_TSFT1_HCI_8822C) << BIT_SHIFT_TSFT1_HCI_8822C) +#define BITS_TSFT1_HCI_8822C \ + (BIT_MASK_TSFT1_HCI_8822C << BIT_SHIFT_TSFT1_HCI_8822C) +#define BIT_CLEAR_TSFT1_HCI_8822C(x) ((x) & (~BITS_TSFT1_HCI_8822C)) +#define BIT_GET_TSFT1_HCI_8822C(x) \ + (((x) >> BIT_SHIFT_TSFT1_HCI_8822C) & BIT_MASK_TSFT1_HCI_8822C) +#define BIT_SET_TSFT1_HCI_8822C(x, v) \ + (BIT_CLEAR_TSFT1_HCI_8822C(x) | BIT_TSFT1_HCI_8822C(v)) + +/* 2 REG_BD_RWPTR_CLR_8822C */ +#define BIT_CLR_HI7Q_HW_IDX_8822C BIT(29) +#define BIT_CLR_HI6Q_HW_IDX_8822C BIT(28) +#define BIT_CLR_HI5Q_HW_IDX_8822C BIT(27) +#define BIT_CLR_HI4Q_HW_IDX_8822C BIT(26) +#define BIT_CLR_HI3Q_HW_IDX_8822C BIT(25) +#define BIT_CLR_HI2Q_HW_IDX_8822C BIT(24) +#define BIT_CLR_HI1Q_HW_IDX_8822C BIT(23) +#define BIT_CLR_HI0Q_HW_IDX_8822C BIT(22) +#define BIT_CLR_BKQ_HW_IDX_8822C BIT(21) +#define BIT_CLR_BEQ_HW_IDX_8822C BIT(20) +#define BIT_CLR_VIQ_HW_IDX_8822C BIT(19) +#define BIT_CLR_VOQ_HW_IDX_8822C BIT(18) +#define BIT_CLR_MGQ_HW_IDX_8822C BIT(17) +#define BIT_CLR_RXQ_HW_IDX_8822C BIT(16) +#define BIT_CLR_HI7Q_HOST_IDX_8822C BIT(13) +#define BIT_CLR_HI6Q_HOST_IDX_8822C BIT(12) +#define BIT_CLR_HI5Q_HOST_IDX_8822C BIT(11) +#define BIT_CLR_HI4Q_HOST_IDX_8822C BIT(10) +#define BIT_CLR_HI3Q_HOST_IDX_8822C BIT(9) +#define BIT_CLR_HI2Q_HOST_IDX_8822C BIT(8) +#define BIT_CLR_HI1Q_HOST_IDX_8822C BIT(7) +#define BIT_CLR_HI0Q_HOST_IDX_8822C BIT(6) +#define BIT_CLR_BKQ_HOST_IDX_8822C BIT(5) +#define BIT_CLR_BEQ_HOST_IDX_8822C BIT(4) +#define BIT_CLR_VIQ_HOST_IDX_8822C BIT(3) +#define BIT_CLR_VOQ_HOST_IDX_8822C BIT(2) +#define BIT_CLR_MGQ_HOST_IDX_8822C BIT(1) +#define BIT_CLR_RXQ_HOST_IDX_8822C BIT(0) + +/* 2 REG_VOQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_VOQ_HW_IDX_8822C 16 +#define BIT_MASK_VOQ_HW_IDX_8822C 0xfff +#define BIT_VOQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_VOQ_HW_IDX_8822C) << BIT_SHIFT_VOQ_HW_IDX_8822C) +#define BITS_VOQ_HW_IDX_8822C \ + (BIT_MASK_VOQ_HW_IDX_8822C << BIT_SHIFT_VOQ_HW_IDX_8822C) +#define BIT_CLEAR_VOQ_HW_IDX_8822C(x) ((x) & (~BITS_VOQ_HW_IDX_8822C)) +#define BIT_GET_VOQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_VOQ_HW_IDX_8822C) & BIT_MASK_VOQ_HW_IDX_8822C) +#define BIT_SET_VOQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_VOQ_HW_IDX_8822C(x) | BIT_VOQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_VOQ_HOST_IDX_8822C 0 +#define BIT_MASK_VOQ_HOST_IDX_8822C 0xfff +#define BIT_VOQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_VOQ_HOST_IDX_8822C) << BIT_SHIFT_VOQ_HOST_IDX_8822C) +#define BITS_VOQ_HOST_IDX_8822C \ + (BIT_MASK_VOQ_HOST_IDX_8822C << BIT_SHIFT_VOQ_HOST_IDX_8822C) +#define BIT_CLEAR_VOQ_HOST_IDX_8822C(x) ((x) & (~BITS_VOQ_HOST_IDX_8822C)) +#define BIT_GET_VOQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822C) & BIT_MASK_VOQ_HOST_IDX_8822C) +#define BIT_SET_VOQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_VOQ_HOST_IDX_8822C(x) | BIT_VOQ_HOST_IDX_8822C(v)) + +/* 2 REG_VIQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_VIQ_HW_IDX_8822C 16 +#define BIT_MASK_VIQ_HW_IDX_8822C 0xfff +#define BIT_VIQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_VIQ_HW_IDX_8822C) << BIT_SHIFT_VIQ_HW_IDX_8822C) +#define BITS_VIQ_HW_IDX_8822C \ + (BIT_MASK_VIQ_HW_IDX_8822C << BIT_SHIFT_VIQ_HW_IDX_8822C) +#define BIT_CLEAR_VIQ_HW_IDX_8822C(x) ((x) & (~BITS_VIQ_HW_IDX_8822C)) +#define BIT_GET_VIQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_VIQ_HW_IDX_8822C) & BIT_MASK_VIQ_HW_IDX_8822C) +#define BIT_SET_VIQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_VIQ_HW_IDX_8822C(x) | BIT_VIQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_VIQ_HOST_IDX_8822C 0 +#define BIT_MASK_VIQ_HOST_IDX_8822C 0xfff +#define BIT_VIQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_VIQ_HOST_IDX_8822C) << BIT_SHIFT_VIQ_HOST_IDX_8822C) +#define BITS_VIQ_HOST_IDX_8822C \ + (BIT_MASK_VIQ_HOST_IDX_8822C << BIT_SHIFT_VIQ_HOST_IDX_8822C) +#define BIT_CLEAR_VIQ_HOST_IDX_8822C(x) ((x) & (~BITS_VIQ_HOST_IDX_8822C)) +#define BIT_GET_VIQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822C) & BIT_MASK_VIQ_HOST_IDX_8822C) +#define BIT_SET_VIQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_VIQ_HOST_IDX_8822C(x) | BIT_VIQ_HOST_IDX_8822C(v)) + +/* 2 REG_BEQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_BEQ_HW_IDX_8822C 16 +#define BIT_MASK_BEQ_HW_IDX_8822C 0xfff +#define BIT_BEQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_BEQ_HW_IDX_8822C) << BIT_SHIFT_BEQ_HW_IDX_8822C) +#define BITS_BEQ_HW_IDX_8822C \ + (BIT_MASK_BEQ_HW_IDX_8822C << BIT_SHIFT_BEQ_HW_IDX_8822C) +#define BIT_CLEAR_BEQ_HW_IDX_8822C(x) ((x) & (~BITS_BEQ_HW_IDX_8822C)) +#define BIT_GET_BEQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_BEQ_HW_IDX_8822C) & BIT_MASK_BEQ_HW_IDX_8822C) +#define BIT_SET_BEQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_BEQ_HW_IDX_8822C(x) | BIT_BEQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_BEQ_HOST_IDX_8822C 0 +#define BIT_MASK_BEQ_HOST_IDX_8822C 0xfff +#define BIT_BEQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_BEQ_HOST_IDX_8822C) << BIT_SHIFT_BEQ_HOST_IDX_8822C) +#define BITS_BEQ_HOST_IDX_8822C \ + (BIT_MASK_BEQ_HOST_IDX_8822C << BIT_SHIFT_BEQ_HOST_IDX_8822C) +#define BIT_CLEAR_BEQ_HOST_IDX_8822C(x) ((x) & (~BITS_BEQ_HOST_IDX_8822C)) +#define BIT_GET_BEQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822C) & BIT_MASK_BEQ_HOST_IDX_8822C) +#define BIT_SET_BEQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_BEQ_HOST_IDX_8822C(x) | BIT_BEQ_HOST_IDX_8822C(v)) + +/* 2 REG_BKQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_BKQ_HW_IDX_8822C 16 +#define BIT_MASK_BKQ_HW_IDX_8822C 0xfff +#define BIT_BKQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_BKQ_HW_IDX_8822C) << BIT_SHIFT_BKQ_HW_IDX_8822C) +#define BITS_BKQ_HW_IDX_8822C \ + (BIT_MASK_BKQ_HW_IDX_8822C << BIT_SHIFT_BKQ_HW_IDX_8822C) +#define BIT_CLEAR_BKQ_HW_IDX_8822C(x) ((x) & (~BITS_BKQ_HW_IDX_8822C)) +#define BIT_GET_BKQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_BKQ_HW_IDX_8822C) & BIT_MASK_BKQ_HW_IDX_8822C) +#define BIT_SET_BKQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_BKQ_HW_IDX_8822C(x) | BIT_BKQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_BKQ_HOST_IDX_8822C 0 +#define BIT_MASK_BKQ_HOST_IDX_8822C 0xfff +#define BIT_BKQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_BKQ_HOST_IDX_8822C) << BIT_SHIFT_BKQ_HOST_IDX_8822C) +#define BITS_BKQ_HOST_IDX_8822C \ + (BIT_MASK_BKQ_HOST_IDX_8822C << BIT_SHIFT_BKQ_HOST_IDX_8822C) +#define BIT_CLEAR_BKQ_HOST_IDX_8822C(x) ((x) & (~BITS_BKQ_HOST_IDX_8822C)) +#define BIT_GET_BKQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822C) & BIT_MASK_BKQ_HOST_IDX_8822C) +#define BIT_SET_BKQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_BKQ_HOST_IDX_8822C(x) | BIT_BKQ_HOST_IDX_8822C(v)) + +/* 2 REG_MGQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_MGQ_HW_IDX_8822C 16 +#define BIT_MASK_MGQ_HW_IDX_8822C 0xfff +#define BIT_MGQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_MGQ_HW_IDX_8822C) << BIT_SHIFT_MGQ_HW_IDX_8822C) +#define BITS_MGQ_HW_IDX_8822C \ + (BIT_MASK_MGQ_HW_IDX_8822C << BIT_SHIFT_MGQ_HW_IDX_8822C) +#define BIT_CLEAR_MGQ_HW_IDX_8822C(x) ((x) & (~BITS_MGQ_HW_IDX_8822C)) +#define BIT_GET_MGQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_HW_IDX_8822C) & BIT_MASK_MGQ_HW_IDX_8822C) +#define BIT_SET_MGQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_MGQ_HW_IDX_8822C(x) | BIT_MGQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_MGQ_HOST_IDX_8822C 0 +#define BIT_MASK_MGQ_HOST_IDX_8822C 0xfff +#define BIT_MGQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_MGQ_HOST_IDX_8822C) << BIT_SHIFT_MGQ_HOST_IDX_8822C) +#define BITS_MGQ_HOST_IDX_8822C \ + (BIT_MASK_MGQ_HOST_IDX_8822C << BIT_SHIFT_MGQ_HOST_IDX_8822C) +#define BIT_CLEAR_MGQ_HOST_IDX_8822C(x) ((x) & (~BITS_MGQ_HOST_IDX_8822C)) +#define BIT_GET_MGQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822C) & BIT_MASK_MGQ_HOST_IDX_8822C) +#define BIT_SET_MGQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_MGQ_HOST_IDX_8822C(x) | BIT_MGQ_HOST_IDX_8822C(v)) + +/* 2 REG_RXQ_RXBD_IDX_8822C */ + +#define BIT_SHIFT_RXQ_HW_IDX_8822C 16 +#define BIT_MASK_RXQ_HW_IDX_8822C 0xfff +#define BIT_RXQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_RXQ_HW_IDX_8822C) << BIT_SHIFT_RXQ_HW_IDX_8822C) +#define BITS_RXQ_HW_IDX_8822C \ + (BIT_MASK_RXQ_HW_IDX_8822C << BIT_SHIFT_RXQ_HW_IDX_8822C) +#define BIT_CLEAR_RXQ_HW_IDX_8822C(x) ((x) & (~BITS_RXQ_HW_IDX_8822C)) +#define BIT_GET_RXQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RXQ_HW_IDX_8822C) & BIT_MASK_RXQ_HW_IDX_8822C) +#define BIT_SET_RXQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_RXQ_HW_IDX_8822C(x) | BIT_RXQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_RXQ_HOST_IDX_8822C 0 +#define BIT_MASK_RXQ_HOST_IDX_8822C 0xfff +#define BIT_RXQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_RXQ_HOST_IDX_8822C) << BIT_SHIFT_RXQ_HOST_IDX_8822C) +#define BITS_RXQ_HOST_IDX_8822C \ + (BIT_MASK_RXQ_HOST_IDX_8822C << BIT_SHIFT_RXQ_HOST_IDX_8822C) +#define BIT_CLEAR_RXQ_HOST_IDX_8822C(x) ((x) & (~BITS_RXQ_HOST_IDX_8822C)) +#define BIT_GET_RXQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822C) & BIT_MASK_RXQ_HOST_IDX_8822C) +#define BIT_SET_RXQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_RXQ_HOST_IDX_8822C(x) | BIT_RXQ_HOST_IDX_8822C(v)) + +/* 2 REG_HI0Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI0Q_HW_IDX_8822C 16 +#define BIT_MASK_HI0Q_HW_IDX_8822C 0xfff +#define BIT_HI0Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI0Q_HW_IDX_8822C) << BIT_SHIFT_HI0Q_HW_IDX_8822C) +#define BITS_HI0Q_HW_IDX_8822C \ + (BIT_MASK_HI0Q_HW_IDX_8822C << BIT_SHIFT_HI0Q_HW_IDX_8822C) +#define BIT_CLEAR_HI0Q_HW_IDX_8822C(x) ((x) & (~BITS_HI0Q_HW_IDX_8822C)) +#define BIT_GET_HI0Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822C) & BIT_MASK_HI0Q_HW_IDX_8822C) +#define BIT_SET_HI0Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI0Q_HW_IDX_8822C(x) | BIT_HI0Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI0Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI0Q_HOST_IDX_8822C 0xfff +#define BIT_HI0Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI0Q_HOST_IDX_8822C) << BIT_SHIFT_HI0Q_HOST_IDX_8822C) +#define BITS_HI0Q_HOST_IDX_8822C \ + (BIT_MASK_HI0Q_HOST_IDX_8822C << BIT_SHIFT_HI0Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI0Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI0Q_HOST_IDX_8822C)) +#define BIT_GET_HI0Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822C) & BIT_MASK_HI0Q_HOST_IDX_8822C) +#define BIT_SET_HI0Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI0Q_HOST_IDX_8822C(x) | BIT_HI0Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI1Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI1Q_HW_IDX_8822C 16 +#define BIT_MASK_HI1Q_HW_IDX_8822C 0xfff +#define BIT_HI1Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI1Q_HW_IDX_8822C) << BIT_SHIFT_HI1Q_HW_IDX_8822C) +#define BITS_HI1Q_HW_IDX_8822C \ + (BIT_MASK_HI1Q_HW_IDX_8822C << BIT_SHIFT_HI1Q_HW_IDX_8822C) +#define BIT_CLEAR_HI1Q_HW_IDX_8822C(x) ((x) & (~BITS_HI1Q_HW_IDX_8822C)) +#define BIT_GET_HI1Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822C) & BIT_MASK_HI1Q_HW_IDX_8822C) +#define BIT_SET_HI1Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI1Q_HW_IDX_8822C(x) | BIT_HI1Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI1Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI1Q_HOST_IDX_8822C 0xfff +#define BIT_HI1Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI1Q_HOST_IDX_8822C) << BIT_SHIFT_HI1Q_HOST_IDX_8822C) +#define BITS_HI1Q_HOST_IDX_8822C \ + (BIT_MASK_HI1Q_HOST_IDX_8822C << BIT_SHIFT_HI1Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI1Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI1Q_HOST_IDX_8822C)) +#define BIT_GET_HI1Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822C) & BIT_MASK_HI1Q_HOST_IDX_8822C) +#define BIT_SET_HI1Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI1Q_HOST_IDX_8822C(x) | BIT_HI1Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI2Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI2Q_HW_IDX_8822C 16 +#define BIT_MASK_HI2Q_HW_IDX_8822C 0xfff +#define BIT_HI2Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI2Q_HW_IDX_8822C) << BIT_SHIFT_HI2Q_HW_IDX_8822C) +#define BITS_HI2Q_HW_IDX_8822C \ + (BIT_MASK_HI2Q_HW_IDX_8822C << BIT_SHIFT_HI2Q_HW_IDX_8822C) +#define BIT_CLEAR_HI2Q_HW_IDX_8822C(x) ((x) & (~BITS_HI2Q_HW_IDX_8822C)) +#define BIT_GET_HI2Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822C) & BIT_MASK_HI2Q_HW_IDX_8822C) +#define BIT_SET_HI2Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI2Q_HW_IDX_8822C(x) | BIT_HI2Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI2Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI2Q_HOST_IDX_8822C 0xfff +#define BIT_HI2Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI2Q_HOST_IDX_8822C) << BIT_SHIFT_HI2Q_HOST_IDX_8822C) +#define BITS_HI2Q_HOST_IDX_8822C \ + (BIT_MASK_HI2Q_HOST_IDX_8822C << BIT_SHIFT_HI2Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI2Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI2Q_HOST_IDX_8822C)) +#define BIT_GET_HI2Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822C) & BIT_MASK_HI2Q_HOST_IDX_8822C) +#define BIT_SET_HI2Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI2Q_HOST_IDX_8822C(x) | BIT_HI2Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI3Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI3Q_HW_IDX_8822C 16 +#define BIT_MASK_HI3Q_HW_IDX_8822C 0xfff +#define BIT_HI3Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI3Q_HW_IDX_8822C) << BIT_SHIFT_HI3Q_HW_IDX_8822C) +#define BITS_HI3Q_HW_IDX_8822C \ + (BIT_MASK_HI3Q_HW_IDX_8822C << BIT_SHIFT_HI3Q_HW_IDX_8822C) +#define BIT_CLEAR_HI3Q_HW_IDX_8822C(x) ((x) & (~BITS_HI3Q_HW_IDX_8822C)) +#define BIT_GET_HI3Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822C) & BIT_MASK_HI3Q_HW_IDX_8822C) +#define BIT_SET_HI3Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI3Q_HW_IDX_8822C(x) | BIT_HI3Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI3Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI3Q_HOST_IDX_8822C 0xfff +#define BIT_HI3Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI3Q_HOST_IDX_8822C) << BIT_SHIFT_HI3Q_HOST_IDX_8822C) +#define BITS_HI3Q_HOST_IDX_8822C \ + (BIT_MASK_HI3Q_HOST_IDX_8822C << BIT_SHIFT_HI3Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI3Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI3Q_HOST_IDX_8822C)) +#define BIT_GET_HI3Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822C) & BIT_MASK_HI3Q_HOST_IDX_8822C) +#define BIT_SET_HI3Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI3Q_HOST_IDX_8822C(x) | BIT_HI3Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI4Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI4Q_HW_IDX_8822C 16 +#define BIT_MASK_HI4Q_HW_IDX_8822C 0xfff +#define BIT_HI4Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI4Q_HW_IDX_8822C) << BIT_SHIFT_HI4Q_HW_IDX_8822C) +#define BITS_HI4Q_HW_IDX_8822C \ + (BIT_MASK_HI4Q_HW_IDX_8822C << BIT_SHIFT_HI4Q_HW_IDX_8822C) +#define BIT_CLEAR_HI4Q_HW_IDX_8822C(x) ((x) & (~BITS_HI4Q_HW_IDX_8822C)) +#define BIT_GET_HI4Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822C) & BIT_MASK_HI4Q_HW_IDX_8822C) +#define BIT_SET_HI4Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI4Q_HW_IDX_8822C(x) | BIT_HI4Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI4Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI4Q_HOST_IDX_8822C 0xfff +#define BIT_HI4Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI4Q_HOST_IDX_8822C) << BIT_SHIFT_HI4Q_HOST_IDX_8822C) +#define BITS_HI4Q_HOST_IDX_8822C \ + (BIT_MASK_HI4Q_HOST_IDX_8822C << BIT_SHIFT_HI4Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI4Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI4Q_HOST_IDX_8822C)) +#define BIT_GET_HI4Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822C) & BIT_MASK_HI4Q_HOST_IDX_8822C) +#define BIT_SET_HI4Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI4Q_HOST_IDX_8822C(x) | BIT_HI4Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI5Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI5Q_HW_IDX_8822C 16 +#define BIT_MASK_HI5Q_HW_IDX_8822C 0xfff +#define BIT_HI5Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI5Q_HW_IDX_8822C) << BIT_SHIFT_HI5Q_HW_IDX_8822C) +#define BITS_HI5Q_HW_IDX_8822C \ + (BIT_MASK_HI5Q_HW_IDX_8822C << BIT_SHIFT_HI5Q_HW_IDX_8822C) +#define BIT_CLEAR_HI5Q_HW_IDX_8822C(x) ((x) & (~BITS_HI5Q_HW_IDX_8822C)) +#define BIT_GET_HI5Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822C) & BIT_MASK_HI5Q_HW_IDX_8822C) +#define BIT_SET_HI5Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI5Q_HW_IDX_8822C(x) | BIT_HI5Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI5Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI5Q_HOST_IDX_8822C 0xfff +#define BIT_HI5Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI5Q_HOST_IDX_8822C) << BIT_SHIFT_HI5Q_HOST_IDX_8822C) +#define BITS_HI5Q_HOST_IDX_8822C \ + (BIT_MASK_HI5Q_HOST_IDX_8822C << BIT_SHIFT_HI5Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI5Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI5Q_HOST_IDX_8822C)) +#define BIT_GET_HI5Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822C) & BIT_MASK_HI5Q_HOST_IDX_8822C) +#define BIT_SET_HI5Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI5Q_HOST_IDX_8822C(x) | BIT_HI5Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI6Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI6Q_HW_IDX_8822C 16 +#define BIT_MASK_HI6Q_HW_IDX_8822C 0xfff +#define BIT_HI6Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI6Q_HW_IDX_8822C) << BIT_SHIFT_HI6Q_HW_IDX_8822C) +#define BITS_HI6Q_HW_IDX_8822C \ + (BIT_MASK_HI6Q_HW_IDX_8822C << BIT_SHIFT_HI6Q_HW_IDX_8822C) +#define BIT_CLEAR_HI6Q_HW_IDX_8822C(x) ((x) & (~BITS_HI6Q_HW_IDX_8822C)) +#define BIT_GET_HI6Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822C) & BIT_MASK_HI6Q_HW_IDX_8822C) +#define BIT_SET_HI6Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI6Q_HW_IDX_8822C(x) | BIT_HI6Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI6Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI6Q_HOST_IDX_8822C 0xfff +#define BIT_HI6Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI6Q_HOST_IDX_8822C) << BIT_SHIFT_HI6Q_HOST_IDX_8822C) +#define BITS_HI6Q_HOST_IDX_8822C \ + (BIT_MASK_HI6Q_HOST_IDX_8822C << BIT_SHIFT_HI6Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI6Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI6Q_HOST_IDX_8822C)) +#define BIT_GET_HI6Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822C) & BIT_MASK_HI6Q_HOST_IDX_8822C) +#define BIT_SET_HI6Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI6Q_HOST_IDX_8822C(x) | BIT_HI6Q_HOST_IDX_8822C(v)) + +/* 2 REG_HI7Q_TXBD_IDX_8822C */ + +#define BIT_SHIFT_HI7Q_HW_IDX_8822C 16 +#define BIT_MASK_HI7Q_HW_IDX_8822C 0xfff +#define BIT_HI7Q_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_HI7Q_HW_IDX_8822C) << BIT_SHIFT_HI7Q_HW_IDX_8822C) +#define BITS_HI7Q_HW_IDX_8822C \ + (BIT_MASK_HI7Q_HW_IDX_8822C << BIT_SHIFT_HI7Q_HW_IDX_8822C) +#define BIT_CLEAR_HI7Q_HW_IDX_8822C(x) ((x) & (~BITS_HI7Q_HW_IDX_8822C)) +#define BIT_GET_HI7Q_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822C) & BIT_MASK_HI7Q_HW_IDX_8822C) +#define BIT_SET_HI7Q_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_HI7Q_HW_IDX_8822C(x) | BIT_HI7Q_HW_IDX_8822C(v)) + +#define BIT_SHIFT_HI7Q_HOST_IDX_8822C 0 +#define BIT_MASK_HI7Q_HOST_IDX_8822C 0xfff +#define BIT_HI7Q_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_HI7Q_HOST_IDX_8822C) << BIT_SHIFT_HI7Q_HOST_IDX_8822C) +#define BITS_HI7Q_HOST_IDX_8822C \ + (BIT_MASK_HI7Q_HOST_IDX_8822C << BIT_SHIFT_HI7Q_HOST_IDX_8822C) +#define BIT_CLEAR_HI7Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI7Q_HOST_IDX_8822C)) +#define BIT_GET_HI7Q_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822C) & BIT_MASK_HI7Q_HOST_IDX_8822C) +#define BIT_SET_HI7Q_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_HI7Q_HOST_IDX_8822C(x) | BIT_HI7Q_HOST_IDX_8822C(v)) + +/* 2 REG_DBG_SEL_V1_8822C */ + +#define BIT_SHIFT_DBG_SEL_8822C 0 +#define BIT_MASK_DBG_SEL_8822C 0xff +#define BIT_DBG_SEL_8822C(x) \ + (((x) & BIT_MASK_DBG_SEL_8822C) << BIT_SHIFT_DBG_SEL_8822C) +#define BITS_DBG_SEL_8822C (BIT_MASK_DBG_SEL_8822C << BIT_SHIFT_DBG_SEL_8822C) +#define BIT_CLEAR_DBG_SEL_8822C(x) ((x) & (~BITS_DBG_SEL_8822C)) +#define BIT_GET_DBG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_DBG_SEL_8822C) & BIT_MASK_DBG_SEL_8822C) +#define BIT_SET_DBG_SEL_8822C(x, v) \ + (BIT_CLEAR_DBG_SEL_8822C(x) | BIT_DBG_SEL_8822C(v)) + +/* 2 REG_PCIE_HRPWM1_V1_8822C */ + +#define BIT_SHIFT_PCIE_HRPWM_8822C 0 +#define BIT_MASK_PCIE_HRPWM_8822C 0xff +#define BIT_PCIE_HRPWM_8822C(x) \ + (((x) & BIT_MASK_PCIE_HRPWM_8822C) << BIT_SHIFT_PCIE_HRPWM_8822C) +#define BITS_PCIE_HRPWM_8822C \ + (BIT_MASK_PCIE_HRPWM_8822C << BIT_SHIFT_PCIE_HRPWM_8822C) +#define BIT_CLEAR_PCIE_HRPWM_8822C(x) ((x) & (~BITS_PCIE_HRPWM_8822C)) +#define BIT_GET_PCIE_HRPWM_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM_8822C) & BIT_MASK_PCIE_HRPWM_8822C) +#define BIT_SET_PCIE_HRPWM_8822C(x, v) \ + (BIT_CLEAR_PCIE_HRPWM_8822C(x) | BIT_PCIE_HRPWM_8822C(v)) + +/* 2 REG_PCIE_HCPWM1_V1_8822C */ + +#define BIT_SHIFT_PCIE_HCPWM_8822C 0 +#define BIT_MASK_PCIE_HCPWM_8822C 0xff +#define BIT_PCIE_HCPWM_8822C(x) \ + (((x) & BIT_MASK_PCIE_HCPWM_8822C) << BIT_SHIFT_PCIE_HCPWM_8822C) +#define BITS_PCIE_HCPWM_8822C \ + (BIT_MASK_PCIE_HCPWM_8822C << BIT_SHIFT_PCIE_HCPWM_8822C) +#define BIT_CLEAR_PCIE_HCPWM_8822C(x) ((x) & (~BITS_PCIE_HCPWM_8822C)) +#define BIT_GET_PCIE_HCPWM_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM_8822C) & BIT_MASK_PCIE_HCPWM_8822C) +#define BIT_SET_PCIE_HCPWM_8822C(x, v) \ + (BIT_CLEAR_PCIE_HCPWM_8822C(x) | BIT_PCIE_HCPWM_8822C(v)) + +/* 2 REG_PCIE_CTRL2_8822C */ +#define BIT_DIS_TXDMA_PRE_8822C BIT(7) +#define BIT_DIS_RXDMA_PRE_8822C BIT(6) + +#define BIT_SHIFT_HPS_CLKR_PCIE_8822C 4 +#define BIT_MASK_HPS_CLKR_PCIE_8822C 0x3 +#define BIT_HPS_CLKR_PCIE_8822C(x) \ + (((x) & BIT_MASK_HPS_CLKR_PCIE_8822C) << BIT_SHIFT_HPS_CLKR_PCIE_8822C) +#define BITS_HPS_CLKR_PCIE_8822C \ + (BIT_MASK_HPS_CLKR_PCIE_8822C << BIT_SHIFT_HPS_CLKR_PCIE_8822C) +#define BIT_CLEAR_HPS_CLKR_PCIE_8822C(x) ((x) & (~BITS_HPS_CLKR_PCIE_8822C)) +#define BIT_GET_HPS_CLKR_PCIE_8822C(x) \ + (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822C) & BIT_MASK_HPS_CLKR_PCIE_8822C) +#define BIT_SET_HPS_CLKR_PCIE_8822C(x, v) \ + (BIT_CLEAR_HPS_CLKR_PCIE_8822C(x) | BIT_HPS_CLKR_PCIE_8822C(v)) + +#define BIT_PCIE_INT_8822C BIT(3) +#define BIT_TXFLAG_EXIT_L1_EN_8822C BIT(2) +#define BIT_EN_RXDMA_ALIGN_8822C BIT(1) +#define BIT_EN_TXDMA_ALIGN_8822C BIT(0) + +/* 2 REG_PCIE_HRPWM2_V1_8822C */ + +#define BIT_SHIFT_PCIE_HRPWM2_8822C 0 +#define BIT_MASK_PCIE_HRPWM2_8822C 0xffff +#define BIT_PCIE_HRPWM2_8822C(x) \ + (((x) & BIT_MASK_PCIE_HRPWM2_8822C) << BIT_SHIFT_PCIE_HRPWM2_8822C) +#define BITS_PCIE_HRPWM2_8822C \ + (BIT_MASK_PCIE_HRPWM2_8822C << BIT_SHIFT_PCIE_HRPWM2_8822C) +#define BIT_CLEAR_PCIE_HRPWM2_8822C(x) ((x) & (~BITS_PCIE_HRPWM2_8822C)) +#define BIT_GET_PCIE_HRPWM2_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_HRPWM2_8822C) & BIT_MASK_PCIE_HRPWM2_8822C) +#define BIT_SET_PCIE_HRPWM2_8822C(x, v) \ + (BIT_CLEAR_PCIE_HRPWM2_8822C(x) | BIT_PCIE_HRPWM2_8822C(v)) + +/* 2 REG_PCIE_HCPWM2_V1_8822C */ + +#define BIT_SHIFT_PCIE_HCPWM2_8822C 0 +#define BIT_MASK_PCIE_HCPWM2_8822C 0xffff +#define BIT_PCIE_HCPWM2_8822C(x) \ + (((x) & BIT_MASK_PCIE_HCPWM2_8822C) << BIT_SHIFT_PCIE_HCPWM2_8822C) +#define BITS_PCIE_HCPWM2_8822C \ + (BIT_MASK_PCIE_HCPWM2_8822C << BIT_SHIFT_PCIE_HCPWM2_8822C) +#define BIT_CLEAR_PCIE_HCPWM2_8822C(x) ((x) & (~BITS_PCIE_HCPWM2_8822C)) +#define BIT_GET_PCIE_HCPWM2_8822C(x) \ + (((x) >> BIT_SHIFT_PCIE_HCPWM2_8822C) & BIT_MASK_PCIE_HCPWM2_8822C) +#define BIT_SET_PCIE_HCPWM2_8822C(x, v) \ + (BIT_CLEAR_PCIE_HCPWM2_8822C(x) | BIT_PCIE_HCPWM2_8822C(v)) + +/* 2 REG_PCIE_H2C_MSG_V1_8822C */ + +#define BIT_SHIFT_DRV2FW_INFO_8822C 0 +#define BIT_MASK_DRV2FW_INFO_8822C 0xffffffffL +#define BIT_DRV2FW_INFO_8822C(x) \ + (((x) & BIT_MASK_DRV2FW_INFO_8822C) << BIT_SHIFT_DRV2FW_INFO_8822C) +#define BITS_DRV2FW_INFO_8822C \ + (BIT_MASK_DRV2FW_INFO_8822C << BIT_SHIFT_DRV2FW_INFO_8822C) +#define BIT_CLEAR_DRV2FW_INFO_8822C(x) ((x) & (~BITS_DRV2FW_INFO_8822C)) +#define BIT_GET_DRV2FW_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_DRV2FW_INFO_8822C) & BIT_MASK_DRV2FW_INFO_8822C) +#define BIT_SET_DRV2FW_INFO_8822C(x, v) \ + (BIT_CLEAR_DRV2FW_INFO_8822C(x) | BIT_DRV2FW_INFO_8822C(v)) + +/* 2 REG_PCIE_C2H_MSG_V1_8822C */ + +#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C 0 +#define BIT_MASK_HCI_PCIE_C2H_MSG_8822C 0xffffffffL +#define BIT_HCI_PCIE_C2H_MSG_8822C(x) \ + (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822C) \ + << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C) +#define BITS_HCI_PCIE_C2H_MSG_8822C \ + (BIT_MASK_HCI_PCIE_C2H_MSG_8822C << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C) +#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8822C(x) \ + ((x) & (~BITS_HCI_PCIE_C2H_MSG_8822C)) +#define BIT_GET_HCI_PCIE_C2H_MSG_8822C(x) \ + (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C) & \ + BIT_MASK_HCI_PCIE_C2H_MSG_8822C) +#define BIT_SET_HCI_PCIE_C2H_MSG_8822C(x, v) \ + (BIT_CLEAR_HCI_PCIE_C2H_MSG_8822C(x) | BIT_HCI_PCIE_C2H_MSG_8822C(v)) + +/* 2 REG_DBI_WDATA_V1_8822C */ + +#define BIT_SHIFT_DBI_WDATA_8822C 0 +#define BIT_MASK_DBI_WDATA_8822C 0xffffffffL +#define BIT_DBI_WDATA_8822C(x) \ + (((x) & BIT_MASK_DBI_WDATA_8822C) << BIT_SHIFT_DBI_WDATA_8822C) +#define BITS_DBI_WDATA_8822C \ + (BIT_MASK_DBI_WDATA_8822C << BIT_SHIFT_DBI_WDATA_8822C) +#define BIT_CLEAR_DBI_WDATA_8822C(x) ((x) & (~BITS_DBI_WDATA_8822C)) +#define BIT_GET_DBI_WDATA_8822C(x) \ + (((x) >> BIT_SHIFT_DBI_WDATA_8822C) & BIT_MASK_DBI_WDATA_8822C) +#define BIT_SET_DBI_WDATA_8822C(x, v) \ + (BIT_CLEAR_DBI_WDATA_8822C(x) | BIT_DBI_WDATA_8822C(v)) + +/* 2 REG_DBI_RDATA_V1_8822C */ + +#define BIT_SHIFT_DBI_RDATA_8822C 0 +#define BIT_MASK_DBI_RDATA_8822C 0xffffffffL +#define BIT_DBI_RDATA_8822C(x) \ + (((x) & BIT_MASK_DBI_RDATA_8822C) << BIT_SHIFT_DBI_RDATA_8822C) +#define BITS_DBI_RDATA_8822C \ + (BIT_MASK_DBI_RDATA_8822C << BIT_SHIFT_DBI_RDATA_8822C) +#define BIT_CLEAR_DBI_RDATA_8822C(x) ((x) & (~BITS_DBI_RDATA_8822C)) +#define BIT_GET_DBI_RDATA_8822C(x) \ + (((x) >> BIT_SHIFT_DBI_RDATA_8822C) & BIT_MASK_DBI_RDATA_8822C) +#define BIT_SET_DBI_RDATA_8822C(x, v) \ + (BIT_CLEAR_DBI_RDATA_8822C(x) | BIT_DBI_RDATA_8822C(v)) + +/* 2 REG_DBI_FLAG_V1_8822C */ +#define BIT_EN_STUCK_DBG_8822C BIT(26) +#define BIT_RX_STUCK_8822C BIT(25) +#define BIT_TX_STUCK_8822C BIT(24) +#define BIT_DBI_RFLAG_8822C BIT(17) +#define BIT_DBI_WFLAG_8822C BIT(16) + +#define BIT_SHIFT_DBI_WREN_8822C 12 +#define BIT_MASK_DBI_WREN_8822C 0xf +#define BIT_DBI_WREN_8822C(x) \ + (((x) & BIT_MASK_DBI_WREN_8822C) << BIT_SHIFT_DBI_WREN_8822C) +#define BITS_DBI_WREN_8822C \ + (BIT_MASK_DBI_WREN_8822C << BIT_SHIFT_DBI_WREN_8822C) +#define BIT_CLEAR_DBI_WREN_8822C(x) ((x) & (~BITS_DBI_WREN_8822C)) +#define BIT_GET_DBI_WREN_8822C(x) \ + (((x) >> BIT_SHIFT_DBI_WREN_8822C) & BIT_MASK_DBI_WREN_8822C) +#define BIT_SET_DBI_WREN_8822C(x, v) \ + (BIT_CLEAR_DBI_WREN_8822C(x) | BIT_DBI_WREN_8822C(v)) + +#define BIT_SHIFT_DBI_ADDR_8822C 0 +#define BIT_MASK_DBI_ADDR_8822C 0xfff +#define BIT_DBI_ADDR_8822C(x) \ + (((x) & BIT_MASK_DBI_ADDR_8822C) << BIT_SHIFT_DBI_ADDR_8822C) +#define BITS_DBI_ADDR_8822C \ + (BIT_MASK_DBI_ADDR_8822C << BIT_SHIFT_DBI_ADDR_8822C) +#define BIT_CLEAR_DBI_ADDR_8822C(x) ((x) & (~BITS_DBI_ADDR_8822C)) +#define BIT_GET_DBI_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_DBI_ADDR_8822C) & BIT_MASK_DBI_ADDR_8822C) +#define BIT_SET_DBI_ADDR_8822C(x, v) \ + (BIT_CLEAR_DBI_ADDR_8822C(x) | BIT_DBI_ADDR_8822C(v)) + +/* 2 REG_MDIO_V1_8822C */ + +#define BIT_SHIFT_MDIO_RDATA_8822C 16 +#define BIT_MASK_MDIO_RDATA_8822C 0xffff +#define BIT_MDIO_RDATA_8822C(x) \ + (((x) & BIT_MASK_MDIO_RDATA_8822C) << BIT_SHIFT_MDIO_RDATA_8822C) +#define BITS_MDIO_RDATA_8822C \ + (BIT_MASK_MDIO_RDATA_8822C << BIT_SHIFT_MDIO_RDATA_8822C) +#define BIT_CLEAR_MDIO_RDATA_8822C(x) ((x) & (~BITS_MDIO_RDATA_8822C)) +#define BIT_GET_MDIO_RDATA_8822C(x) \ + (((x) >> BIT_SHIFT_MDIO_RDATA_8822C) & BIT_MASK_MDIO_RDATA_8822C) +#define BIT_SET_MDIO_RDATA_8822C(x, v) \ + (BIT_CLEAR_MDIO_RDATA_8822C(x) | BIT_MDIO_RDATA_8822C(v)) + +#define BIT_SHIFT_MDIO_WDATA_8822C 0 +#define BIT_MASK_MDIO_WDATA_8822C 0xffff +#define BIT_MDIO_WDATA_8822C(x) \ + (((x) & BIT_MASK_MDIO_WDATA_8822C) << BIT_SHIFT_MDIO_WDATA_8822C) +#define BITS_MDIO_WDATA_8822C \ + (BIT_MASK_MDIO_WDATA_8822C << BIT_SHIFT_MDIO_WDATA_8822C) +#define BIT_CLEAR_MDIO_WDATA_8822C(x) ((x) & (~BITS_MDIO_WDATA_8822C)) +#define BIT_GET_MDIO_WDATA_8822C(x) \ + (((x) >> BIT_SHIFT_MDIO_WDATA_8822C) & BIT_MASK_MDIO_WDATA_8822C) +#define BIT_SET_MDIO_WDATA_8822C(x, v) \ + (BIT_CLEAR_MDIO_WDATA_8822C(x) | BIT_MDIO_WDATA_8822C(v)) + +/* 2 REG_PCIE_MIX_CFG_8822C */ + +#define BIT_SHIFT_MDIO_PHY_ADDR_8822C 24 +#define BIT_MASK_MDIO_PHY_ADDR_8822C 0x1f +#define BIT_MDIO_PHY_ADDR_8822C(x) \ + (((x) & BIT_MASK_MDIO_PHY_ADDR_8822C) << BIT_SHIFT_MDIO_PHY_ADDR_8822C) +#define BITS_MDIO_PHY_ADDR_8822C \ + (BIT_MASK_MDIO_PHY_ADDR_8822C << BIT_SHIFT_MDIO_PHY_ADDR_8822C) +#define BIT_CLEAR_MDIO_PHY_ADDR_8822C(x) ((x) & (~BITS_MDIO_PHY_ADDR_8822C)) +#define BIT_GET_MDIO_PHY_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822C) & BIT_MASK_MDIO_PHY_ADDR_8822C) +#define BIT_SET_MDIO_PHY_ADDR_8822C(x, v) \ + (BIT_CLEAR_MDIO_PHY_ADDR_8822C(x) | BIT_MDIO_PHY_ADDR_8822C(v)) + +#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C 10 +#define BIT_MASK_WATCH_DOG_RECORD_V1_8822C 0x3fff +#define BIT_WATCH_DOG_RECORD_V1_8822C(x) \ + (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822C) \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C) +#define BITS_WATCH_DOG_RECORD_V1_8822C \ + (BIT_MASK_WATCH_DOG_RECORD_V1_8822C \ + << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C) +#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8822C(x) \ + ((x) & (~BITS_WATCH_DOG_RECORD_V1_8822C)) +#define BIT_GET_WATCH_DOG_RECORD_V1_8822C(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C) & \ + BIT_MASK_WATCH_DOG_RECORD_V1_8822C) +#define BIT_SET_WATCH_DOG_RECORD_V1_8822C(x, v) \ + (BIT_CLEAR_WATCH_DOG_RECORD_V1_8822C(x) | \ + BIT_WATCH_DOG_RECORD_V1_8822C(v)) + +#define BIT_R_IO_TIMEOUT_FLAG_V1_8822C BIT(9) +#define BIT_EN_WATCH_DOG_8822C BIT(8) +#define BIT_ECRC_EN_V1_8822C BIT(7) +#define BIT_MDIO_RFLAG_V1_8822C BIT(6) +#define BIT_MDIO_WFLAG_V1_8822C BIT(5) + +#define BIT_SHIFT_MDIO_REG_ADDR_V1_8822C 0 +#define BIT_MASK_MDIO_REG_ADDR_V1_8822C 0x1f +#define BIT_MDIO_REG_ADDR_V1_8822C(x) \ + (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822C) \ + << BIT_SHIFT_MDIO_REG_ADDR_V1_8822C) +#define BITS_MDIO_REG_ADDR_V1_8822C \ + (BIT_MASK_MDIO_REG_ADDR_V1_8822C << BIT_SHIFT_MDIO_REG_ADDR_V1_8822C) +#define BIT_CLEAR_MDIO_REG_ADDR_V1_8822C(x) \ + ((x) & (~BITS_MDIO_REG_ADDR_V1_8822C)) +#define BIT_GET_MDIO_REG_ADDR_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822C) & \ + BIT_MASK_MDIO_REG_ADDR_V1_8822C) +#define BIT_SET_MDIO_REG_ADDR_V1_8822C(x, v) \ + (BIT_CLEAR_MDIO_REG_ADDR_V1_8822C(x) | BIT_MDIO_REG_ADDR_V1_8822C(v)) + +/* 2 REG_HCI_MIX_CFG_8822C */ + +#define BIT_SHIFT_WATCH_DOG_TIMER_8822C 28 +#define BIT_MASK_WATCH_DOG_TIMER_8822C 0xf +#define BIT_WATCH_DOG_TIMER_8822C(x) \ + (((x) & BIT_MASK_WATCH_DOG_TIMER_8822C) \ + << BIT_SHIFT_WATCH_DOG_TIMER_8822C) +#define BITS_WATCH_DOG_TIMER_8822C \ + (BIT_MASK_WATCH_DOG_TIMER_8822C << BIT_SHIFT_WATCH_DOG_TIMER_8822C) +#define BIT_CLEAR_WATCH_DOG_TIMER_8822C(x) ((x) & (~BITS_WATCH_DOG_TIMER_8822C)) +#define BIT_GET_WATCH_DOG_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_WATCH_DOG_TIMER_8822C) & \ + BIT_MASK_WATCH_DOG_TIMER_8822C) +#define BIT_SET_WATCH_DOG_TIMER_8822C(x, v) \ + (BIT_CLEAR_WATCH_DOG_TIMER_8822C(x) | BIT_WATCH_DOG_TIMER_8822C(v)) + +#define BIT_EN_ALIGN_MTU_8822C BIT(23) + +#define BIT_SHIFT_LATENCY_CONTROL_8822C 21 +#define BIT_MASK_LATENCY_CONTROL_8822C 0x3 +#define BIT_LATENCY_CONTROL_8822C(x) \ + (((x) & BIT_MASK_LATENCY_CONTROL_8822C) \ + << BIT_SHIFT_LATENCY_CONTROL_8822C) +#define BITS_LATENCY_CONTROL_8822C \ + (BIT_MASK_LATENCY_CONTROL_8822C << BIT_SHIFT_LATENCY_CONTROL_8822C) +#define BIT_CLEAR_LATENCY_CONTROL_8822C(x) ((x) & (~BITS_LATENCY_CONTROL_8822C)) +#define BIT_GET_LATENCY_CONTROL_8822C(x) \ + (((x) >> BIT_SHIFT_LATENCY_CONTROL_8822C) & \ + BIT_MASK_LATENCY_CONTROL_8822C) +#define BIT_SET_LATENCY_CONTROL_8822C(x, v) \ + (BIT_CLEAR_LATENCY_CONTROL_8822C(x) | BIT_LATENCY_CONTROL_8822C(v)) + +#define BIT_HOST_GEN2_SUPPORT_8822C BIT(20) + +#define BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C 15 +#define BIT_MASK_TXDMA_ERR_FLAG_V1_8822C 0x1f +#define BIT_TXDMA_ERR_FLAG_V1_8822C(x) \ + (((x) & BIT_MASK_TXDMA_ERR_FLAG_V1_8822C) \ + << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C) +#define BITS_TXDMA_ERR_FLAG_V1_8822C \ + (BIT_MASK_TXDMA_ERR_FLAG_V1_8822C << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C) +#define BIT_CLEAR_TXDMA_ERR_FLAG_V1_8822C(x) \ + ((x) & (~BITS_TXDMA_ERR_FLAG_V1_8822C)) +#define BIT_GET_TXDMA_ERR_FLAG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C) & \ + BIT_MASK_TXDMA_ERR_FLAG_V1_8822C) +#define BIT_SET_TXDMA_ERR_FLAG_V1_8822C(x, v) \ + (BIT_CLEAR_TXDMA_ERR_FLAG_V1_8822C(x) | BIT_TXDMA_ERR_FLAG_V1_8822C(v)) + +#define BIT_EPHY_RX50_EN_8822C BIT(11) + +#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C 8 +#define BIT_MASK_MSI_TIMEOUT_ID_V1_8822C 0x7 +#define BIT_MSI_TIMEOUT_ID_V1_8822C(x) \ + (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822C) \ + << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C) +#define BITS_MSI_TIMEOUT_ID_V1_8822C \ + (BIT_MASK_MSI_TIMEOUT_ID_V1_8822C << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C) +#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822C(x) \ + ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8822C)) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C) & \ + BIT_MASK_MSI_TIMEOUT_ID_V1_8822C) +#define BIT_SET_MSI_TIMEOUT_ID_V1_8822C(x, v) \ + (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822C(x) | BIT_MSI_TIMEOUT_ID_V1_8822C(v)) + +#define BIT_RADDR_RD_8822C BIT(7) +#define BIT_L1OFF_PWR_OFF_EN_8822C BIT(6) +#define BIT_L0S_LINK_OFF_8822C BIT(4) +#define BIT_ACT_LINK_OFF_8822C BIT(3) +#define BIT_EN_SLOW_MAC_TX_8822C BIT(2) +#define BIT_EN_SLOW_MAC_RX_8822C BIT(1) +#define BIT_EN_SLOW_MAC_HW_8822C BIT(0) + +/* 2 REG_STC_INT_CS_8822C(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */ +#define BIT_STC_INT_EN_8822C BIT(31) + +#define BIT_SHIFT_STC_INT_FLAG_8822C 16 +#define BIT_MASK_STC_INT_FLAG_8822C 0xff +#define BIT_STC_INT_FLAG_8822C(x) \ + (((x) & BIT_MASK_STC_INT_FLAG_8822C) << BIT_SHIFT_STC_INT_FLAG_8822C) +#define BITS_STC_INT_FLAG_8822C \ + (BIT_MASK_STC_INT_FLAG_8822C << BIT_SHIFT_STC_INT_FLAG_8822C) +#define BIT_CLEAR_STC_INT_FLAG_8822C(x) ((x) & (~BITS_STC_INT_FLAG_8822C)) +#define BIT_GET_STC_INT_FLAG_8822C(x) \ + (((x) >> BIT_SHIFT_STC_INT_FLAG_8822C) & BIT_MASK_STC_INT_FLAG_8822C) +#define BIT_SET_STC_INT_FLAG_8822C(x, v) \ + (BIT_CLEAR_STC_INT_FLAG_8822C(x) | BIT_STC_INT_FLAG_8822C(v)) + +#define BIT_SHIFT_STC_INT_IDX_8822C 8 +#define BIT_MASK_STC_INT_IDX_8822C 0x7 +#define BIT_STC_INT_IDX_8822C(x) \ + (((x) & BIT_MASK_STC_INT_IDX_8822C) << BIT_SHIFT_STC_INT_IDX_8822C) +#define BITS_STC_INT_IDX_8822C \ + (BIT_MASK_STC_INT_IDX_8822C << BIT_SHIFT_STC_INT_IDX_8822C) +#define BIT_CLEAR_STC_INT_IDX_8822C(x) ((x) & (~BITS_STC_INT_IDX_8822C)) +#define BIT_GET_STC_INT_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_STC_INT_IDX_8822C) & BIT_MASK_STC_INT_IDX_8822C) +#define BIT_SET_STC_INT_IDX_8822C(x, v) \ + (BIT_CLEAR_STC_INT_IDX_8822C(x) | BIT_STC_INT_IDX_8822C(v)) + +#define BIT_SHIFT_STC_INT_REALTIME_CS_8822C 0 +#define BIT_MASK_STC_INT_REALTIME_CS_8822C 0x3f +#define BIT_STC_INT_REALTIME_CS_8822C(x) \ + (((x) & BIT_MASK_STC_INT_REALTIME_CS_8822C) \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8822C) +#define BITS_STC_INT_REALTIME_CS_8822C \ + (BIT_MASK_STC_INT_REALTIME_CS_8822C \ + << BIT_SHIFT_STC_INT_REALTIME_CS_8822C) +#define BIT_CLEAR_STC_INT_REALTIME_CS_8822C(x) \ + ((x) & (~BITS_STC_INT_REALTIME_CS_8822C)) +#define BIT_GET_STC_INT_REALTIME_CS_8822C(x) \ + (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822C) & \ + BIT_MASK_STC_INT_REALTIME_CS_8822C) +#define BIT_SET_STC_INT_REALTIME_CS_8822C(x, v) \ + (BIT_CLEAR_STC_INT_REALTIME_CS_8822C(x) | \ + BIT_STC_INT_REALTIME_CS_8822C(v)) + +#define BIT_STC_INT_GRP_EN_8822C BIT(31) + +#define BIT_SHIFT_STC_INT_EXPECT_LS_8822C 8 +#define BIT_MASK_STC_INT_EXPECT_LS_8822C 0x3f +#define BIT_STC_INT_EXPECT_LS_8822C(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_LS_8822C) \ + << BIT_SHIFT_STC_INT_EXPECT_LS_8822C) +#define BITS_STC_INT_EXPECT_LS_8822C \ + (BIT_MASK_STC_INT_EXPECT_LS_8822C << BIT_SHIFT_STC_INT_EXPECT_LS_8822C) +#define BIT_CLEAR_STC_INT_EXPECT_LS_8822C(x) \ + ((x) & (~BITS_STC_INT_EXPECT_LS_8822C)) +#define BIT_GET_STC_INT_EXPECT_LS_8822C(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822C) & \ + BIT_MASK_STC_INT_EXPECT_LS_8822C) +#define BIT_SET_STC_INT_EXPECT_LS_8822C(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_LS_8822C(x) | BIT_STC_INT_EXPECT_LS_8822C(v)) + +#define BIT_SHIFT_STC_INT_EXPECT_CS_8822C 0 +#define BIT_MASK_STC_INT_EXPECT_CS_8822C 0x3f +#define BIT_STC_INT_EXPECT_CS_8822C(x) \ + (((x) & BIT_MASK_STC_INT_EXPECT_CS_8822C) \ + << BIT_SHIFT_STC_INT_EXPECT_CS_8822C) +#define BITS_STC_INT_EXPECT_CS_8822C \ + (BIT_MASK_STC_INT_EXPECT_CS_8822C << BIT_SHIFT_STC_INT_EXPECT_CS_8822C) +#define BIT_CLEAR_STC_INT_EXPECT_CS_8822C(x) \ + ((x) & (~BITS_STC_INT_EXPECT_CS_8822C)) +#define BIT_GET_STC_INT_EXPECT_CS_8822C(x) \ + (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822C) & \ + BIT_MASK_STC_INT_EXPECT_CS_8822C) +#define BIT_SET_STC_INT_EXPECT_CS_8822C(x, v) \ + (BIT_CLEAR_STC_INT_EXPECT_CS_8822C(x) | BIT_STC_INT_EXPECT_CS_8822C(v)) + +/* 2 REG_H2CQ_TXBD_DESA_8822C */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA_8822C 0 +#define BIT_MASK_H2CQ_TXBD_DESA_8822C 0xffffffffffffffffL +#define BIT_H2CQ_TXBD_DESA_8822C(x) \ + (((x) & BIT_MASK_H2CQ_TXBD_DESA_8822C) \ + << BIT_SHIFT_H2CQ_TXBD_DESA_8822C) +#define BITS_H2CQ_TXBD_DESA_8822C \ + (BIT_MASK_H2CQ_TXBD_DESA_8822C << BIT_SHIFT_H2CQ_TXBD_DESA_8822C) +#define BIT_CLEAR_H2CQ_TXBD_DESA_8822C(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8822C)) +#define BIT_GET_H2CQ_TXBD_DESA_8822C(x) \ + (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822C) & \ + BIT_MASK_H2CQ_TXBD_DESA_8822C) +#define BIT_SET_H2CQ_TXBD_DESA_8822C(x, v) \ + (BIT_CLEAR_H2CQ_TXBD_DESA_8822C(x) | BIT_H2CQ_TXBD_DESA_8822C(v)) + +/* 2 REG_H2CQ_TXBD_NUM_8822C */ +#define BIT_PCIE_H2CQ_FLAG_8822C BIT(14) + +#define BIT_SHIFT_H2CQ_DESC_MODE_8822C 12 +#define BIT_MASK_H2CQ_DESC_MODE_8822C 0x3 +#define BIT_H2CQ_DESC_MODE_8822C(x) \ + (((x) & BIT_MASK_H2CQ_DESC_MODE_8822C) \ + << BIT_SHIFT_H2CQ_DESC_MODE_8822C) +#define BITS_H2CQ_DESC_MODE_8822C \ + (BIT_MASK_H2CQ_DESC_MODE_8822C << BIT_SHIFT_H2CQ_DESC_MODE_8822C) +#define BIT_CLEAR_H2CQ_DESC_MODE_8822C(x) ((x) & (~BITS_H2CQ_DESC_MODE_8822C)) +#define BIT_GET_H2CQ_DESC_MODE_8822C(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822C) & \ + BIT_MASK_H2CQ_DESC_MODE_8822C) +#define BIT_SET_H2CQ_DESC_MODE_8822C(x, v) \ + (BIT_CLEAR_H2CQ_DESC_MODE_8822C(x) | BIT_H2CQ_DESC_MODE_8822C(v)) + +#define BIT_SHIFT_H2CQ_DESC_NUM_8822C 0 +#define BIT_MASK_H2CQ_DESC_NUM_8822C 0xfff +#define BIT_H2CQ_DESC_NUM_8822C(x) \ + (((x) & BIT_MASK_H2CQ_DESC_NUM_8822C) << BIT_SHIFT_H2CQ_DESC_NUM_8822C) +#define BITS_H2CQ_DESC_NUM_8822C \ + (BIT_MASK_H2CQ_DESC_NUM_8822C << BIT_SHIFT_H2CQ_DESC_NUM_8822C) +#define BIT_CLEAR_H2CQ_DESC_NUM_8822C(x) ((x) & (~BITS_H2CQ_DESC_NUM_8822C)) +#define BIT_GET_H2CQ_DESC_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822C) & BIT_MASK_H2CQ_DESC_NUM_8822C) +#define BIT_SET_H2CQ_DESC_NUM_8822C(x, v) \ + (BIT_CLEAR_H2CQ_DESC_NUM_8822C(x) | BIT_H2CQ_DESC_NUM_8822C(v)) + +/* 2 REG_H2CQ_TXBD_IDX_8822C */ + +#define BIT_SHIFT_H2CQ_HW_IDX_8822C 16 +#define BIT_MASK_H2CQ_HW_IDX_8822C 0xfff +#define BIT_H2CQ_HW_IDX_8822C(x) \ + (((x) & BIT_MASK_H2CQ_HW_IDX_8822C) << BIT_SHIFT_H2CQ_HW_IDX_8822C) +#define BITS_H2CQ_HW_IDX_8822C \ + (BIT_MASK_H2CQ_HW_IDX_8822C << BIT_SHIFT_H2CQ_HW_IDX_8822C) +#define BIT_CLEAR_H2CQ_HW_IDX_8822C(x) ((x) & (~BITS_H2CQ_HW_IDX_8822C)) +#define BIT_GET_H2CQ_HW_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822C) & BIT_MASK_H2CQ_HW_IDX_8822C) +#define BIT_SET_H2CQ_HW_IDX_8822C(x, v) \ + (BIT_CLEAR_H2CQ_HW_IDX_8822C(x) | BIT_H2CQ_HW_IDX_8822C(v)) + +#define BIT_SHIFT_H2CQ_HOST_IDX_8822C 0 +#define BIT_MASK_H2CQ_HOST_IDX_8822C 0xfff +#define BIT_H2CQ_HOST_IDX_8822C(x) \ + (((x) & BIT_MASK_H2CQ_HOST_IDX_8822C) << BIT_SHIFT_H2CQ_HOST_IDX_8822C) +#define BITS_H2CQ_HOST_IDX_8822C \ + (BIT_MASK_H2CQ_HOST_IDX_8822C << BIT_SHIFT_H2CQ_HOST_IDX_8822C) +#define BIT_CLEAR_H2CQ_HOST_IDX_8822C(x) ((x) & (~BITS_H2CQ_HOST_IDX_8822C)) +#define BIT_GET_H2CQ_HOST_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822C) & BIT_MASK_H2CQ_HOST_IDX_8822C) +#define BIT_SET_H2CQ_HOST_IDX_8822C(x, v) \ + (BIT_CLEAR_H2CQ_HOST_IDX_8822C(x) | BIT_H2CQ_HOST_IDX_8822C(v)) + +/* 2 REG_H2CQ_CSR_8822C[31:0] (H2CQ CONTROL AND STATUS) */ +#define BIT_H2CQ_FULL_8822C BIT(31) +#define BIT_CLR_H2CQ_HOST_IDX_8822C BIT(16) +#define BIT_CLR_H2CQ_HW_IDX_8822C BIT(8) +#define BIT_STOP_H2CQ_8822C BIT(0) + +/* 2 REG_CHANGE_PCIE_SPEED_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_RXDMA_ERR_CNT_8822C 8 +#define BIT_MASK_RXDMA_ERR_CNT_8822C 0xff +#define BIT_RXDMA_ERR_CNT_8822C(x) \ + (((x) & BIT_MASK_RXDMA_ERR_CNT_8822C) << BIT_SHIFT_RXDMA_ERR_CNT_8822C) +#define BITS_RXDMA_ERR_CNT_8822C \ + (BIT_MASK_RXDMA_ERR_CNT_8822C << BIT_SHIFT_RXDMA_ERR_CNT_8822C) +#define BIT_CLEAR_RXDMA_ERR_CNT_8822C(x) ((x) & (~BITS_RXDMA_ERR_CNT_8822C)) +#define BIT_GET_RXDMA_ERR_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_RXDMA_ERR_CNT_8822C) & BIT_MASK_RXDMA_ERR_CNT_8822C) +#define BIT_SET_RXDMA_ERR_CNT_8822C(x, v) \ + (BIT_CLEAR_RXDMA_ERR_CNT_8822C(x) | BIT_RXDMA_ERR_CNT_8822C(v)) + +#define BIT_TXDMA_ERR_HANDLE_REQ_8822C BIT(7) +#define BIT_TXDMA_ERROR_PS_8822C BIT(6) +#define BIT_EN_TXDMA_STUCK_ERR_HANDLE_8822C BIT(5) +#define BIT_EN_TXDMA_RTN_ERR_HANDLE_8822C BIT(4) +#define BIT_RXDMA_ERR_HANDLE_REQ_8822C BIT(3) +#define BIT_RXDMA_ERROR_PS_8822C BIT(2) +#define BIT_EN_RXDMA_STUCK_ERR_HANDLE_8822C BIT(1) +#define BIT_EN_RXDMA_RTN_ERR_HANDLE_8822C BIT(0) + +/* 2 REG_DEBUG_STATE1_8822C */ + +#define BIT_SHIFT_DEBUG_STATE1_8822C 0 +#define BIT_MASK_DEBUG_STATE1_8822C 0xffffffffL +#define BIT_DEBUG_STATE1_8822C(x) \ + (((x) & BIT_MASK_DEBUG_STATE1_8822C) << BIT_SHIFT_DEBUG_STATE1_8822C) +#define BITS_DEBUG_STATE1_8822C \ + (BIT_MASK_DEBUG_STATE1_8822C << BIT_SHIFT_DEBUG_STATE1_8822C) +#define BIT_CLEAR_DEBUG_STATE1_8822C(x) ((x) & (~BITS_DEBUG_STATE1_8822C)) +#define BIT_GET_DEBUG_STATE1_8822C(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE1_8822C) & BIT_MASK_DEBUG_STATE1_8822C) +#define BIT_SET_DEBUG_STATE1_8822C(x, v) \ + (BIT_CLEAR_DEBUG_STATE1_8822C(x) | BIT_DEBUG_STATE1_8822C(v)) + +/* 2 REG_DEBUG_STATE2_8822C */ + +#define BIT_SHIFT_DEBUG_STATE2_8822C 0 +#define BIT_MASK_DEBUG_STATE2_8822C 0xffffffffL +#define BIT_DEBUG_STATE2_8822C(x) \ + (((x) & BIT_MASK_DEBUG_STATE2_8822C) << BIT_SHIFT_DEBUG_STATE2_8822C) +#define BITS_DEBUG_STATE2_8822C \ + (BIT_MASK_DEBUG_STATE2_8822C << BIT_SHIFT_DEBUG_STATE2_8822C) +#define BIT_CLEAR_DEBUG_STATE2_8822C(x) ((x) & (~BITS_DEBUG_STATE2_8822C)) +#define BIT_GET_DEBUG_STATE2_8822C(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE2_8822C) & BIT_MASK_DEBUG_STATE2_8822C) +#define BIT_SET_DEBUG_STATE2_8822C(x, v) \ + (BIT_CLEAR_DEBUG_STATE2_8822C(x) | BIT_DEBUG_STATE2_8822C(v)) + +/* 2 REG_DEBUG_STATE3_8822C */ + +#define BIT_SHIFT_DEBUG_STATE3_8822C 0 +#define BIT_MASK_DEBUG_STATE3_8822C 0xffffffffL +#define BIT_DEBUG_STATE3_8822C(x) \ + (((x) & BIT_MASK_DEBUG_STATE3_8822C) << BIT_SHIFT_DEBUG_STATE3_8822C) +#define BITS_DEBUG_STATE3_8822C \ + (BIT_MASK_DEBUG_STATE3_8822C << BIT_SHIFT_DEBUG_STATE3_8822C) +#define BIT_CLEAR_DEBUG_STATE3_8822C(x) ((x) & (~BITS_DEBUG_STATE3_8822C)) +#define BIT_GET_DEBUG_STATE3_8822C(x) \ + (((x) >> BIT_SHIFT_DEBUG_STATE3_8822C) & BIT_MASK_DEBUG_STATE3_8822C) +#define BIT_SET_DEBUG_STATE3_8822C(x, v) \ + (BIT_CLEAR_DEBUG_STATE3_8822C(x) | BIT_DEBUG_STATE3_8822C(v)) + +/* 2 REG_CHNL_DMA_CFG_V1_8822C */ +#define BIT_TXHCI_EN_V1_8822C BIT(26) +#define BIT_TXHCI_IDLE_V1_8822C BIT(25) +#define BIT_DMA_PRI_EN_V1_8822C BIT(24) + +/* 2 REG_PCIE_HISR0_V1_8822C */ +#define BIT_PSTIMER_2_8822C BIT(31) +#define BIT_PSTIMER_1_8822C BIT(30) +#define BIT_PSTIMER_0_8822C BIT(29) +#define BIT_GTINT4_8822C BIT(28) +#define BIT_GTINT3_8822C BIT(27) +#define BIT_TXBCN0ERR_8822C BIT(26) +#define BIT_TXBCN0OK_8822C BIT(25) +#define BIT_TSF_BIT32_TOGGLE_8822C BIT(24) +#define BIT_TXDMA_START_INT_8822C BIT(23) +#define BIT_TXDMA_STOP_INT_8822C BIT(22) +#define BIT_HISR7_IND_8822C BIT(21) +#define BIT_BCNDMAINT0_8822C BIT(20) +#define BIT_HISR6_IND_8822C BIT(19) +#define BIT_HISR5_IND_8822C BIT(18) +#define BIT_HISR4_IND_8822C BIT(17) +#define BIT_BCNDERR0_8822C BIT(16) +#define BIT_HSISR_IND_ON_INT_8822C BIT(15) +#define BIT_HISR3_IND_8822C BIT(14) +#define BIT_HISR2_IND_8822C BIT(13) +#define BIT_HISR1_IND_8822C BIT(11) +#define BIT_C2HCMD_8822C BIT(10) +#define BIT_CPWM2_8822C BIT(9) +#define BIT_CPWM_8822C BIT(8) +#define BIT_TXDMAOK_CHANNEL15_8822C BIT(7) +#define BIT_TXDMAOK_CHANNEL14_8822C BIT(6) +#define BIT_TXDMAOK_CHANNEL3_8822C BIT(5) +#define BIT_TXDMAOK_CHANNEL2_8822C BIT(4) +#define BIT_TXDMAOK_CHANNEL1_8822C BIT(3) +#define BIT_TXDMAOK_CHANNEL0_8822C BIT(2) +#define BIT_RDU_8822C BIT(1) +#define BIT_RXOK_8822C BIT(0) + +/* 2 REG_PCIE_HISR1_V1_8822C */ +#define BIT_PRE_TX_ERR_INT_8822C BIT(31) +#define BIT_TXFIFO_TH_INT_8822C BIT(30) +#define BIT_BTON_STS_UPDATE_INT_8822C BIT(29) +#define BIT_BCNDMAINT7_8822C BIT(27) +#define BIT_BCNDMAINT6_8822C BIT(26) +#define BIT_BCNDMAINT5_8822C BIT(25) +#define BIT_BCNDMAINT4_8822C BIT(24) +#define BIT_BCNDMAINT3_8822C BIT(23) +#define BIT_BCNDMAINT2_8822C BIT(22) +#define BIT_BCNDMAINT1_8822C BIT(21) +#define BIT_BCNDERR7_8822C BIT(20) +#define BIT_BCNDERR6_8822C BIT(19) +#define BIT_BCNDERR5_8822C BIT(18) +#define BIT_BCNDERR4_8822C BIT(17) +#define BIT_BCNDERR3_8822C BIT(16) +#define BIT_BCNDERR2_8822C BIT(15) +#define BIT_BCNDERR1_8822C BIT(14) +#define BIT_ATIMEND_8822C BIT(12) +#define BIT_TXERR_INT_8822C BIT(11) +#define BIT_RXERR_INT_8822C BIT(10) +#define BIT_TXFOVW_8822C BIT(9) +#define BIT_FOVW_8822C BIT(8) +#define BIT_CPU_MGQ_EARLY_INT_8822C BIT(6) +#define BIT_CPU_MGQ_TXDONE_8822C BIT(5) +#define BIT_PSTIMER_5_8822C BIT(4) +#define BIT_PSTIMER_4_8822C BIT(3) +#define BIT_PSTIMER_3_8822C BIT(2) +#define BIT_CPUMGQ_TX_TIMER_8822C BIT(1) +#define BIT_BB_STOPRX_INT_8822C BIT(0) + +/* 2 REG_PCIE_HISR2_V1_8822C */ +#define BIT_BCNDMAINT_P4_8822C BIT(31) +#define BIT_BCNDMAINT_P3_8822C BIT(30) +#define BIT_BCNDMAINT_P2_8822C BIT(29) +#define BIT_BCNDMAINT_P1_8822C BIT(28) +#define BIT_SCH_PHY_TXOP_SIFS_INT_8822C BIT(23) +#define BIT_ATIMEND7_8822C BIT(22) +#define BIT_ATIMEND6_8822C BIT(21) +#define BIT_ATIMEND5_8822C BIT(20) +#define BIT_ATIMEND4_8822C BIT(19) +#define BIT_ATIMEND3_8822C BIT(18) +#define BIT_ATIMEND2_8822C BIT(17) +#define BIT_ATIMEND1_8822C BIT(16) +#define BIT_TXBCN7OK_8822C BIT(14) +#define BIT_TXBCN6OK_8822C BIT(13) +#define BIT_TXBCN5OK_8822C BIT(12) +#define BIT_TXBCN4OK_8822C BIT(11) +#define BIT_TXBCN3OK_8822C BIT(10) +#define BIT_TXBCN2OK_8822C BIT(9) +#define BIT_TXBCN1OK_8822C BIT(8) +#define BIT_TXBCN7ERR_8822C BIT(6) +#define BIT_TXBCN6ERR_8822C BIT(5) +#define BIT_TXBCN5ERR_8822C BIT(4) +#define BIT_TXBCN4ERR_8822C BIT(3) +#define BIT_TXBCN3ERR_8822C BIT(2) +#define BIT_TXBCN2ERR_8822C BIT(1) +#define BIT_TXBCN1ERR_8822C BIT(0) + +/* 2 REG_PCIE_HISR3_V1_8822C */ +#define BIT_GTINT12_8822C BIT(24) +#define BIT_GTINT11_8822C BIT(23) +#define BIT_GTINT10_8822C BIT(22) +#define BIT_GTINT9_8822C BIT(21) +#define BIT_RX_DESC_BUF_FULL_8822C BIT(20) +#define BIT_CPHY_LDO_OCP_DET_INT_8822C BIT(19) +#define BIT_WDT_PLATFORM_INT_8822C BIT(18) +#define BIT_WDT_CPU_INT_8822C BIT(17) +#define BIT_SETH2CDOK_8822C BIT(16) +#define BIT_H2C_CMD_FULL_8822C BIT(15) +#define BIT_PKT_TRANS_ERR_8822C BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822C BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_8822C BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_8822C BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_8822C BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_8822C BIT(9) +#define BIT_SEARCH_FAIL_8822C BIT(8) +#define BIT_PWR_INT_127TO96_8822C BIT(7) +#define BIT_PWR_INT_95TO64_8822C BIT(6) +#define BIT_PWR_INT_63TO32_8822C BIT(5) +#define BIT_PWR_INT_31TO0_8822C BIT(4) +#define BIT_RX_DMA_STUCK_8822C BIT(3) +#define BIT_TX_DMA_STUCK_8822C BIT(2) +#define BIT_DDMA0_LP_INT_8822C BIT(1) +#define BIT_DDMA0_HP_INT_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_Q0_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q0_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q0_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q0_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q0_V1_8822C) +#define BITS_QUEUEMACID_Q0_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q0_V1_8822C << BIT_SHIFT_QUEUEMACID_Q0_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q0_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q0_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q0_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q0_V1_8822C) +#define BIT_SET_QUEUEMACID_Q0_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q0_V1_8822C(x) | BIT_QUEUEMACID_Q0_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q0_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q0_V1_8822C 0x3 +#define BIT_QUEUEAC_Q0_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q0_V1_8822C) << BIT_SHIFT_QUEUEAC_Q0_V1_8822C) +#define BITS_QUEUEAC_Q0_V1_8822C \ + (BIT_MASK_QUEUEAC_Q0_V1_8822C << BIT_SHIFT_QUEUEAC_Q0_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q0_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8822C)) +#define BIT_GET_QUEUEAC_Q0_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822C) & BIT_MASK_QUEUEAC_Q0_V1_8822C) +#define BIT_SET_QUEUEAC_Q0_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q0_V1_8822C(x) | BIT_QUEUEAC_Q0_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q0_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q0_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q0_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q0_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q0_V2_8822C) +#define BITS_TAIL_PKT_Q0_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q0_V2_8822C << BIT_SHIFT_TAIL_PKT_Q0_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q0_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q0_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q0_V2_8822C) +#define BIT_SET_TAIL_PKT_Q0_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q0_V2_8822C(x) | BIT_TAIL_PKT_Q0_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q0_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q0_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q0_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q0_V1_8822C) +#define BITS_HEAD_PKT_Q0_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q0_V1_8822C << BIT_SHIFT_HEAD_PKT_Q0_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q0_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q0_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q0_V1_8822C) +#define BIT_SET_HEAD_PKT_Q0_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q0_V1_8822C(x) | BIT_HEAD_PKT_Q0_V1_8822C(v)) + +/* 2 REG_Q1_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q1_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q1_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q1_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q1_V1_8822C) +#define BITS_QUEUEMACID_Q1_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q1_V1_8822C << BIT_SHIFT_QUEUEMACID_Q1_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q1_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q1_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q1_V1_8822C) +#define BIT_SET_QUEUEMACID_Q1_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q1_V1_8822C(x) | BIT_QUEUEMACID_Q1_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q1_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q1_V1_8822C 0x3 +#define BIT_QUEUEAC_Q1_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q1_V1_8822C) << BIT_SHIFT_QUEUEAC_Q1_V1_8822C) +#define BITS_QUEUEAC_Q1_V1_8822C \ + (BIT_MASK_QUEUEAC_Q1_V1_8822C << BIT_SHIFT_QUEUEAC_Q1_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q1_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8822C)) +#define BIT_GET_QUEUEAC_Q1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822C) & BIT_MASK_QUEUEAC_Q1_V1_8822C) +#define BIT_SET_QUEUEAC_Q1_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q1_V1_8822C(x) | BIT_QUEUEAC_Q1_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q1_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q1_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q1_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q1_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q1_V2_8822C) +#define BITS_TAIL_PKT_Q1_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q1_V2_8822C << BIT_SHIFT_TAIL_PKT_Q1_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q1_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q1_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q1_V2_8822C) +#define BIT_SET_TAIL_PKT_Q1_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q1_V2_8822C(x) | BIT_TAIL_PKT_Q1_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q1_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q1_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q1_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q1_V1_8822C) +#define BITS_HEAD_PKT_Q1_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q1_V1_8822C << BIT_SHIFT_HEAD_PKT_Q1_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q1_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q1_V1_8822C) +#define BIT_SET_HEAD_PKT_Q1_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q1_V1_8822C(x) | BIT_HEAD_PKT_Q1_V1_8822C(v)) + +/* 2 REG_Q2_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q2_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q2_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q2_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q2_V1_8822C) +#define BITS_QUEUEMACID_Q2_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q2_V1_8822C << BIT_SHIFT_QUEUEMACID_Q2_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q2_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q2_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q2_V1_8822C) +#define BIT_SET_QUEUEMACID_Q2_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q2_V1_8822C(x) | BIT_QUEUEMACID_Q2_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q2_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q2_V1_8822C 0x3 +#define BIT_QUEUEAC_Q2_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q2_V1_8822C) << BIT_SHIFT_QUEUEAC_Q2_V1_8822C) +#define BITS_QUEUEAC_Q2_V1_8822C \ + (BIT_MASK_QUEUEAC_Q2_V1_8822C << BIT_SHIFT_QUEUEAC_Q2_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q2_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8822C)) +#define BIT_GET_QUEUEAC_Q2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822C) & BIT_MASK_QUEUEAC_Q2_V1_8822C) +#define BIT_SET_QUEUEAC_Q2_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q2_V1_8822C(x) | BIT_QUEUEAC_Q2_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q2_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q2_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q2_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q2_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q2_V2_8822C) +#define BITS_TAIL_PKT_Q2_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q2_V2_8822C << BIT_SHIFT_TAIL_PKT_Q2_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q2_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q2_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q2_V2_8822C) +#define BIT_SET_TAIL_PKT_Q2_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q2_V2_8822C(x) | BIT_TAIL_PKT_Q2_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q2_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q2_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q2_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q2_V1_8822C) +#define BITS_HEAD_PKT_Q2_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q2_V1_8822C << BIT_SHIFT_HEAD_PKT_Q2_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q2_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q2_V1_8822C) +#define BIT_SET_HEAD_PKT_Q2_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q2_V1_8822C(x) | BIT_HEAD_PKT_Q2_V1_8822C(v)) + +/* 2 REG_Q3_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q3_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q3_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q3_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q3_V1_8822C) +#define BITS_QUEUEMACID_Q3_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q3_V1_8822C << BIT_SHIFT_QUEUEMACID_Q3_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q3_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q3_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q3_V1_8822C) +#define BIT_SET_QUEUEMACID_Q3_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q3_V1_8822C(x) | BIT_QUEUEMACID_Q3_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q3_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q3_V1_8822C 0x3 +#define BIT_QUEUEAC_Q3_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q3_V1_8822C) << BIT_SHIFT_QUEUEAC_Q3_V1_8822C) +#define BITS_QUEUEAC_Q3_V1_8822C \ + (BIT_MASK_QUEUEAC_Q3_V1_8822C << BIT_SHIFT_QUEUEAC_Q3_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q3_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8822C)) +#define BIT_GET_QUEUEAC_Q3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822C) & BIT_MASK_QUEUEAC_Q3_V1_8822C) +#define BIT_SET_QUEUEAC_Q3_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q3_V1_8822C(x) | BIT_QUEUEAC_Q3_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q3_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q3_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q3_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q3_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q3_V2_8822C) +#define BITS_TAIL_PKT_Q3_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q3_V2_8822C << BIT_SHIFT_TAIL_PKT_Q3_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q3_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q3_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q3_V2_8822C) +#define BIT_SET_TAIL_PKT_Q3_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q3_V2_8822C(x) | BIT_TAIL_PKT_Q3_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q3_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q3_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q3_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q3_V1_8822C) +#define BITS_HEAD_PKT_Q3_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q3_V1_8822C << BIT_SHIFT_HEAD_PKT_Q3_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q3_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q3_V1_8822C) +#define BIT_SET_HEAD_PKT_Q3_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q3_V1_8822C(x) | BIT_HEAD_PKT_Q3_V1_8822C(v)) + +/* 2 REG_MGQ_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_MGQ_V1_8822C 0x7f +#define BIT_QUEUEMACID_MGQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C) +#define BITS_QUEUEMACID_MGQ_V1_8822C \ + (BIT_MASK_QUEUEMACID_MGQ_V1_8822C << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_MGQ_V1_8822C)) +#define BIT_GET_QUEUEMACID_MGQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C) & \ + BIT_MASK_QUEUEMACID_MGQ_V1_8822C) +#define BIT_SET_QUEUEMACID_MGQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_MGQ_V1_8822C(x) | BIT_QUEUEMACID_MGQ_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_MGQ_V1_8822C 23 +#define BIT_MASK_QUEUEAC_MGQ_V1_8822C 0x3 +#define BIT_QUEUEAC_MGQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822C) \ + << BIT_SHIFT_QUEUEAC_MGQ_V1_8822C) +#define BITS_QUEUEAC_MGQ_V1_8822C \ + (BIT_MASK_QUEUEAC_MGQ_V1_8822C << BIT_SHIFT_QUEUEAC_MGQ_V1_8822C) +#define BIT_CLEAR_QUEUEAC_MGQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8822C)) +#define BIT_GET_QUEUEAC_MGQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822C) & \ + BIT_MASK_QUEUEAC_MGQ_V1_8822C) +#define BIT_SET_QUEUEAC_MGQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_MGQ_V1_8822C(x) | BIT_QUEUEAC_MGQ_V1_8822C(v)) + +#define BIT_TIDEMPTY_MGQ_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_MGQ_V2_8822C 0x7ff +#define BIT_TAIL_PKT_MGQ_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C) +#define BITS_TAIL_PKT_MGQ_V2_8822C \ + (BIT_MASK_TAIL_PKT_MGQ_V2_8822C << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8822C)) +#define BIT_GET_TAIL_PKT_MGQ_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C) & \ + BIT_MASK_TAIL_PKT_MGQ_V2_8822C) +#define BIT_SET_TAIL_PKT_MGQ_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_MGQ_V2_8822C(x) | BIT_TAIL_PKT_MGQ_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_MGQ_V1_8822C 0x7ff +#define BIT_HEAD_PKT_MGQ_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C) +#define BITS_HEAD_PKT_MGQ_V1_8822C \ + (BIT_MASK_HEAD_PKT_MGQ_V1_8822C << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8822C)) +#define BIT_GET_HEAD_PKT_MGQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C) & \ + BIT_MASK_HEAD_PKT_MGQ_V1_8822C) +#define BIT_SET_HEAD_PKT_MGQ_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_MGQ_V1_8822C(x) | BIT_HEAD_PKT_MGQ_V1_8822C(v)) + +/* 2 REG_HIQ_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_HIQ_V1_8822C 0x7f +#define BIT_QUEUEMACID_HIQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C) +#define BITS_QUEUEMACID_HIQ_V1_8822C \ + (BIT_MASK_QUEUEMACID_HIQ_V1_8822C << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_HIQ_V1_8822C)) +#define BIT_GET_QUEUEMACID_HIQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C) & \ + BIT_MASK_QUEUEMACID_HIQ_V1_8822C) +#define BIT_SET_QUEUEMACID_HIQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_HIQ_V1_8822C(x) | BIT_QUEUEMACID_HIQ_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_HIQ_V1_8822C 23 +#define BIT_MASK_QUEUEAC_HIQ_V1_8822C 0x3 +#define BIT_QUEUEAC_HIQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822C) \ + << BIT_SHIFT_QUEUEAC_HIQ_V1_8822C) +#define BITS_QUEUEAC_HIQ_V1_8822C \ + (BIT_MASK_QUEUEAC_HIQ_V1_8822C << BIT_SHIFT_QUEUEAC_HIQ_V1_8822C) +#define BIT_CLEAR_QUEUEAC_HIQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8822C)) +#define BIT_GET_QUEUEAC_HIQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822C) & \ + BIT_MASK_QUEUEAC_HIQ_V1_8822C) +#define BIT_SET_QUEUEAC_HIQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_HIQ_V1_8822C(x) | BIT_QUEUEAC_HIQ_V1_8822C(v)) + +#define BIT_TIDEMPTY_HIQ_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_HIQ_V2_8822C 0x7ff +#define BIT_TAIL_PKT_HIQ_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C) +#define BITS_TAIL_PKT_HIQ_V2_8822C \ + (BIT_MASK_TAIL_PKT_HIQ_V2_8822C << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8822C)) +#define BIT_GET_TAIL_PKT_HIQ_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C) & \ + BIT_MASK_TAIL_PKT_HIQ_V2_8822C) +#define BIT_SET_TAIL_PKT_HIQ_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_HIQ_V2_8822C(x) | BIT_TAIL_PKT_HIQ_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_HIQ_V1_8822C 0x7ff +#define BIT_HEAD_PKT_HIQ_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C) +#define BITS_HEAD_PKT_HIQ_V1_8822C \ + (BIT_MASK_HEAD_PKT_HIQ_V1_8822C << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8822C)) +#define BIT_GET_HEAD_PKT_HIQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C) & \ + BIT_MASK_HEAD_PKT_HIQ_V1_8822C) +#define BIT_SET_HEAD_PKT_HIQ_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_HIQ_V1_8822C(x) | BIT_HEAD_PKT_HIQ_V1_8822C(v)) + +/* 2 REG_BCNQ_INFO_8822C */ + +#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C 0 +#define BIT_MASK_BCNQ_HEAD_PG_V1_8822C 0xfff +#define BIT_BCNQ_HEAD_PG_V1_8822C(x) \ + (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822C) \ + << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C) +#define BITS_BCNQ_HEAD_PG_V1_8822C \ + (BIT_MASK_BCNQ_HEAD_PG_V1_8822C << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C) +#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8822C(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8822C)) +#define BIT_GET_BCNQ_HEAD_PG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C) & \ + BIT_MASK_BCNQ_HEAD_PG_V1_8822C) +#define BIT_SET_BCNQ_HEAD_PG_V1_8822C(x, v) \ + (BIT_CLEAR_BCNQ_HEAD_PG_V1_8822C(x) | BIT_BCNQ_HEAD_PG_V1_8822C(v)) + +/* 2 REG_TXPKT_EMPTY_8822C */ +#define BIT_BCNQ_EMPTY_8822C BIT(11) +#define BIT_HQQ_EMPTY_8822C BIT(10) +#define BIT_MQQ_EMPTY_8822C BIT(9) +#define BIT_MGQ_CPU_EMPTY_8822C BIT(8) +#define BIT_AC7Q_EMPTY_8822C BIT(7) +#define BIT_AC6Q_EMPTY_8822C BIT(6) +#define BIT_AC5Q_EMPTY_8822C BIT(5) +#define BIT_AC4Q_EMPTY_8822C BIT(4) +#define BIT_AC3Q_EMPTY_8822C BIT(3) +#define BIT_AC2Q_EMPTY_8822C BIT(2) +#define BIT_AC1Q_EMPTY_8822C BIT(1) +#define BIT_AC0Q_EMPTY_8822C BIT(0) + +/* 2 REG_CPU_MGQ_INFO_8822C */ +#define BIT_BCN1_POLL_8822C BIT(30) +#define BIT_CPUMGT_POLL_8822C BIT(29) +#define BIT_BCN_POLL_8822C BIT(28) +#define BIT_CPUMGQ_FW_NUM_V1_8822C BIT(12) + +#define BIT_SHIFT_FW_FREE_TAIL_V1_8822C 0 +#define BIT_MASK_FW_FREE_TAIL_V1_8822C 0xfff +#define BIT_FW_FREE_TAIL_V1_8822C(x) \ + (((x) & BIT_MASK_FW_FREE_TAIL_V1_8822C) \ + << BIT_SHIFT_FW_FREE_TAIL_V1_8822C) +#define BITS_FW_FREE_TAIL_V1_8822C \ + (BIT_MASK_FW_FREE_TAIL_V1_8822C << BIT_SHIFT_FW_FREE_TAIL_V1_8822C) +#define BIT_CLEAR_FW_FREE_TAIL_V1_8822C(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8822C)) +#define BIT_GET_FW_FREE_TAIL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822C) & \ + BIT_MASK_FW_FREE_TAIL_V1_8822C) +#define BIT_SET_FW_FREE_TAIL_V1_8822C(x, v) \ + (BIT_CLEAR_FW_FREE_TAIL_V1_8822C(x) | BIT_FW_FREE_TAIL_V1_8822C(v)) + +/* 2 REG_FWHW_TXQ_CTRL_8822C */ +#define BIT_RTS_LIMIT_IN_OFDM_8822C BIT(23) +#define BIT_EN_BCNQ_DL_8822C BIT(22) +#define BIT_EN_RD_RESP_NAV_BK_8822C BIT(21) +#define BIT_EN_WR_FREE_TAIL_8822C BIT(20) +#define BIT_NOTXRPT_USERATE_EN_8822C BIT(19) +#define BIT_DIS_TXFAIL_RPT_8822C BIT(18) +#define BIT_FTM_TIMEOUT_BYPASS_8822C BIT(16) + +#define BIT_SHIFT_EN_QUEUE_RPT_8822C 8 +#define BIT_MASK_EN_QUEUE_RPT_8822C 0xff +#define BIT_EN_QUEUE_RPT_8822C(x) \ + (((x) & BIT_MASK_EN_QUEUE_RPT_8822C) << BIT_SHIFT_EN_QUEUE_RPT_8822C) +#define BITS_EN_QUEUE_RPT_8822C \ + (BIT_MASK_EN_QUEUE_RPT_8822C << BIT_SHIFT_EN_QUEUE_RPT_8822C) +#define BIT_CLEAR_EN_QUEUE_RPT_8822C(x) ((x) & (~BITS_EN_QUEUE_RPT_8822C)) +#define BIT_GET_EN_QUEUE_RPT_8822C(x) \ + (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822C) & BIT_MASK_EN_QUEUE_RPT_8822C) +#define BIT_SET_EN_QUEUE_RPT_8822C(x, v) \ + (BIT_CLEAR_EN_QUEUE_RPT_8822C(x) | BIT_EN_QUEUE_RPT_8822C(v)) + +#define BIT_EN_RTY_BK_8822C BIT(7) +#define BIT_EN_USE_INI_RAT_8822C BIT(6) +#define BIT_EN_RTS_NAV_BK_8822C BIT(5) +#define BIT_DIS_SSN_CHECK_8822C BIT(4) +#define BIT_MACID_MATCH_RTS_8822C BIT(3) +#define BIT_EN_BCN_TRXRPT_V1_8822C BIT(2) +#define BIT_R_EN_FTMRPT_V1_8822C BIT(1) +#define BIT_R_BMC_NAV_PROTECT_8822C BIT(0) + +/* 2 REG_DATAFB_SEL_8822C */ +#define BIT_BROADCAST_RTY_EN_8822C BIT(3) +#define BIT_EN_RTY_BK_COD_8822C BIT(2) + +#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C 0 +#define BIT_MASK__R_DATA_FALLBACK_SEL_8822C 0x3 +#define BIT__R_DATA_FALLBACK_SEL_8822C(x) \ + (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822C) \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C) +#define BITS__R_DATA_FALLBACK_SEL_8822C \ + (BIT_MASK__R_DATA_FALLBACK_SEL_8822C \ + << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C) +#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8822C(x) \ + ((x) & (~BITS__R_DATA_FALLBACK_SEL_8822C)) +#define BIT_GET__R_DATA_FALLBACK_SEL_8822C(x) \ + (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C) & \ + BIT_MASK__R_DATA_FALLBACK_SEL_8822C) +#define BIT_SET__R_DATA_FALLBACK_SEL_8822C(x, v) \ + (BIT_CLEAR__R_DATA_FALLBACK_SEL_8822C(x) | \ + BIT__R_DATA_FALLBACK_SEL_8822C(v)) + +/* 2 REG_BCNQ_BDNY_V1_8822C */ + +#define BIT_SHIFT_BCNQ_PGBNDY_V1_8822C 0 +#define BIT_MASK_BCNQ_PGBNDY_V1_8822C 0xfff +#define BIT_BCNQ_PGBNDY_V1_8822C(x) \ + (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822C) \ + << BIT_SHIFT_BCNQ_PGBNDY_V1_8822C) +#define BITS_BCNQ_PGBNDY_V1_8822C \ + (BIT_MASK_BCNQ_PGBNDY_V1_8822C << BIT_SHIFT_BCNQ_PGBNDY_V1_8822C) +#define BIT_CLEAR_BCNQ_PGBNDY_V1_8822C(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8822C)) +#define BIT_GET_BCNQ_PGBNDY_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822C) & \ + BIT_MASK_BCNQ_PGBNDY_V1_8822C) +#define BIT_SET_BCNQ_PGBNDY_V1_8822C(x, v) \ + (BIT_CLEAR_BCNQ_PGBNDY_V1_8822C(x) | BIT_BCNQ_PGBNDY_V1_8822C(v)) + +/* 2 REG_LIFETIME_EN_8822C */ +#define BIT_BT_INT_CPU_8822C BIT(7) +#define BIT_BT_INT_PTA_8822C BIT(6) +#define BIT_EN_CTRL_RTYBIT_8822C BIT(4) +#define BIT_LIFETIME_BK_EN_8822C BIT(3) +#define BIT_LIFETIME_BE_EN_8822C BIT(2) +#define BIT_LIFETIME_VI_EN_8822C BIT(1) +#define BIT_LIFETIME_VO_EN_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SPEC_SIFS_8822C */ + +#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C 8 +#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C 0xff +#define BIT_SPEC_SIFS_OFDM_PTCL_8822C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C) +#define BITS_SPEC_SIFS_OFDM_PTCL_8822C \ + (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C \ + << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C) +#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822C(x) \ + ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8822C)) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C) & \ + BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C) +#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8822C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822C(x) | \ + BIT_SPEC_SIFS_OFDM_PTCL_8822C(v)) + +#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C 0 +#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C 0xff +#define BIT_SPEC_SIFS_CCK_PTCL_8822C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C) \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C) +#define BITS_SPEC_SIFS_CCK_PTCL_8822C \ + (BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C \ + << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C) +#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822C(x) \ + ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8822C)) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C) & \ + BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C) +#define BIT_SET_SPEC_SIFS_CCK_PTCL_8822C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822C(x) | \ + BIT_SPEC_SIFS_CCK_PTCL_8822C(v)) + +/* 2 REG_RETRY_LIMIT_8822C */ + +#define BIT_SHIFT_SRL_8822C 8 +#define BIT_MASK_SRL_8822C 0x3f +#define BIT_SRL_8822C(x) (((x) & BIT_MASK_SRL_8822C) << BIT_SHIFT_SRL_8822C) +#define BITS_SRL_8822C (BIT_MASK_SRL_8822C << BIT_SHIFT_SRL_8822C) +#define BIT_CLEAR_SRL_8822C(x) ((x) & (~BITS_SRL_8822C)) +#define BIT_GET_SRL_8822C(x) (((x) >> BIT_SHIFT_SRL_8822C) & BIT_MASK_SRL_8822C) +#define BIT_SET_SRL_8822C(x, v) (BIT_CLEAR_SRL_8822C(x) | BIT_SRL_8822C(v)) + +#define BIT_SHIFT_LRL_8822C 0 +#define BIT_MASK_LRL_8822C 0x3f +#define BIT_LRL_8822C(x) (((x) & BIT_MASK_LRL_8822C) << BIT_SHIFT_LRL_8822C) +#define BITS_LRL_8822C (BIT_MASK_LRL_8822C << BIT_SHIFT_LRL_8822C) +#define BIT_CLEAR_LRL_8822C(x) ((x) & (~BITS_LRL_8822C)) +#define BIT_GET_LRL_8822C(x) (((x) >> BIT_SHIFT_LRL_8822C) & BIT_MASK_LRL_8822C) +#define BIT_SET_LRL_8822C(x, v) (BIT_CLEAR_LRL_8822C(x) | BIT_LRL_8822C(v)) + +/* 2 REG_TXBF_CTRL_8822C */ +#define BIT_R_ENABLE_NDPA_8822C BIT(31) +#define BIT_USE_NDPA_PARAMETER_8822C BIT(30) +#define BIT_R_PROP_TXBF_8822C BIT(29) +#define BIT_R_EN_NDPA_INT_8822C BIT(28) +#define BIT_R_TXBF1_80M_8822C BIT(27) +#define BIT_R_TXBF1_40M_8822C BIT(26) +#define BIT_R_TXBF1_20M_8822C BIT(25) + +#define BIT_SHIFT_R_TXBF1_AID_8822C 16 +#define BIT_MASK_R_TXBF1_AID_8822C 0x1ff +#define BIT_R_TXBF1_AID_8822C(x) \ + (((x) & BIT_MASK_R_TXBF1_AID_8822C) << BIT_SHIFT_R_TXBF1_AID_8822C) +#define BITS_R_TXBF1_AID_8822C \ + (BIT_MASK_R_TXBF1_AID_8822C << BIT_SHIFT_R_TXBF1_AID_8822C) +#define BIT_CLEAR_R_TXBF1_AID_8822C(x) ((x) & (~BITS_R_TXBF1_AID_8822C)) +#define BIT_GET_R_TXBF1_AID_8822C(x) \ + (((x) >> BIT_SHIFT_R_TXBF1_AID_8822C) & BIT_MASK_R_TXBF1_AID_8822C) +#define BIT_SET_R_TXBF1_AID_8822C(x, v) \ + (BIT_CLEAR_R_TXBF1_AID_8822C(x) | BIT_R_TXBF1_AID_8822C(v)) + +#define BIT_DIS_NDP_BFEN_8822C BIT(15) +#define BIT_R_TXBCN_NOBLOCK_NDP_8822C BIT(14) +#define BIT_R_TXBF0_80M_8822C BIT(11) +#define BIT_R_TXBF0_40M_8822C BIT(10) +#define BIT_R_TXBF0_20M_8822C BIT(9) + +#define BIT_SHIFT_R_TXBF0_AID_8822C 0 +#define BIT_MASK_R_TXBF0_AID_8822C 0x1ff +#define BIT_R_TXBF0_AID_8822C(x) \ + (((x) & BIT_MASK_R_TXBF0_AID_8822C) << BIT_SHIFT_R_TXBF0_AID_8822C) +#define BITS_R_TXBF0_AID_8822C \ + (BIT_MASK_R_TXBF0_AID_8822C << BIT_SHIFT_R_TXBF0_AID_8822C) +#define BIT_CLEAR_R_TXBF0_AID_8822C(x) ((x) & (~BITS_R_TXBF0_AID_8822C)) +#define BIT_GET_R_TXBF0_AID_8822C(x) \ + (((x) >> BIT_SHIFT_R_TXBF0_AID_8822C) & BIT_MASK_R_TXBF0_AID_8822C) +#define BIT_SET_R_TXBF0_AID_8822C(x, v) \ + (BIT_CLEAR_R_TXBF0_AID_8822C(x) | BIT_R_TXBF0_AID_8822C(v)) + +/* 2 REG_DARFRC_8822C */ + +#define BIT_SHIFT_DARF_RC4_8822C 24 +#define BIT_MASK_DARF_RC4_8822C 0x1f +#define BIT_DARF_RC4_8822C(x) \ + (((x) & BIT_MASK_DARF_RC4_8822C) << BIT_SHIFT_DARF_RC4_8822C) +#define BITS_DARF_RC4_8822C \ + (BIT_MASK_DARF_RC4_8822C << BIT_SHIFT_DARF_RC4_8822C) +#define BIT_CLEAR_DARF_RC4_8822C(x) ((x) & (~BITS_DARF_RC4_8822C)) +#define BIT_GET_DARF_RC4_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC4_8822C) & BIT_MASK_DARF_RC4_8822C) +#define BIT_SET_DARF_RC4_8822C(x, v) \ + (BIT_CLEAR_DARF_RC4_8822C(x) | BIT_DARF_RC4_8822C(v)) + +#define BIT_SHIFT_DARF_RC3_8822C 16 +#define BIT_MASK_DARF_RC3_8822C 0x1f +#define BIT_DARF_RC3_8822C(x) \ + (((x) & BIT_MASK_DARF_RC3_8822C) << BIT_SHIFT_DARF_RC3_8822C) +#define BITS_DARF_RC3_8822C \ + (BIT_MASK_DARF_RC3_8822C << BIT_SHIFT_DARF_RC3_8822C) +#define BIT_CLEAR_DARF_RC3_8822C(x) ((x) & (~BITS_DARF_RC3_8822C)) +#define BIT_GET_DARF_RC3_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC3_8822C) & BIT_MASK_DARF_RC3_8822C) +#define BIT_SET_DARF_RC3_8822C(x, v) \ + (BIT_CLEAR_DARF_RC3_8822C(x) | BIT_DARF_RC3_8822C(v)) + +#define BIT_SHIFT_DARF_RC2_8822C 8 +#define BIT_MASK_DARF_RC2_8822C 0x1f +#define BIT_DARF_RC2_8822C(x) \ + (((x) & BIT_MASK_DARF_RC2_8822C) << BIT_SHIFT_DARF_RC2_8822C) +#define BITS_DARF_RC2_8822C \ + (BIT_MASK_DARF_RC2_8822C << BIT_SHIFT_DARF_RC2_8822C) +#define BIT_CLEAR_DARF_RC2_8822C(x) ((x) & (~BITS_DARF_RC2_8822C)) +#define BIT_GET_DARF_RC2_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC2_8822C) & BIT_MASK_DARF_RC2_8822C) +#define BIT_SET_DARF_RC2_8822C(x, v) \ + (BIT_CLEAR_DARF_RC2_8822C(x) | BIT_DARF_RC2_8822C(v)) + +#define BIT_SHIFT_DARF_RC1_8822C 0 +#define BIT_MASK_DARF_RC1_8822C 0x1f +#define BIT_DARF_RC1_8822C(x) \ + (((x) & BIT_MASK_DARF_RC1_8822C) << BIT_SHIFT_DARF_RC1_8822C) +#define BITS_DARF_RC1_8822C \ + (BIT_MASK_DARF_RC1_8822C << BIT_SHIFT_DARF_RC1_8822C) +#define BIT_CLEAR_DARF_RC1_8822C(x) ((x) & (~BITS_DARF_RC1_8822C)) +#define BIT_GET_DARF_RC1_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC1_8822C) & BIT_MASK_DARF_RC1_8822C) +#define BIT_SET_DARF_RC1_8822C(x, v) \ + (BIT_CLEAR_DARF_RC1_8822C(x) | BIT_DARF_RC1_8822C(v)) + +/* 2 REG_DARFRCH_8822C */ + +#define BIT_SHIFT_DARF_RC8_V1_8822C 24 +#define BIT_MASK_DARF_RC8_V1_8822C 0x1f +#define BIT_DARF_RC8_V1_8822C(x) \ + (((x) & BIT_MASK_DARF_RC8_V1_8822C) << BIT_SHIFT_DARF_RC8_V1_8822C) +#define BITS_DARF_RC8_V1_8822C \ + (BIT_MASK_DARF_RC8_V1_8822C << BIT_SHIFT_DARF_RC8_V1_8822C) +#define BIT_CLEAR_DARF_RC8_V1_8822C(x) ((x) & (~BITS_DARF_RC8_V1_8822C)) +#define BIT_GET_DARF_RC8_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC8_V1_8822C) & BIT_MASK_DARF_RC8_V1_8822C) +#define BIT_SET_DARF_RC8_V1_8822C(x, v) \ + (BIT_CLEAR_DARF_RC8_V1_8822C(x) | BIT_DARF_RC8_V1_8822C(v)) + +#define BIT_SHIFT_DARF_RC7_V1_8822C 16 +#define BIT_MASK_DARF_RC7_V1_8822C 0x1f +#define BIT_DARF_RC7_V1_8822C(x) \ + (((x) & BIT_MASK_DARF_RC7_V1_8822C) << BIT_SHIFT_DARF_RC7_V1_8822C) +#define BITS_DARF_RC7_V1_8822C \ + (BIT_MASK_DARF_RC7_V1_8822C << BIT_SHIFT_DARF_RC7_V1_8822C) +#define BIT_CLEAR_DARF_RC7_V1_8822C(x) ((x) & (~BITS_DARF_RC7_V1_8822C)) +#define BIT_GET_DARF_RC7_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC7_V1_8822C) & BIT_MASK_DARF_RC7_V1_8822C) +#define BIT_SET_DARF_RC7_V1_8822C(x, v) \ + (BIT_CLEAR_DARF_RC7_V1_8822C(x) | BIT_DARF_RC7_V1_8822C(v)) + +#define BIT_SHIFT_DARF_RC6_V1_8822C 8 +#define BIT_MASK_DARF_RC6_V1_8822C 0x1f +#define BIT_DARF_RC6_V1_8822C(x) \ + (((x) & BIT_MASK_DARF_RC6_V1_8822C) << BIT_SHIFT_DARF_RC6_V1_8822C) +#define BITS_DARF_RC6_V1_8822C \ + (BIT_MASK_DARF_RC6_V1_8822C << BIT_SHIFT_DARF_RC6_V1_8822C) +#define BIT_CLEAR_DARF_RC6_V1_8822C(x) ((x) & (~BITS_DARF_RC6_V1_8822C)) +#define BIT_GET_DARF_RC6_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC6_V1_8822C) & BIT_MASK_DARF_RC6_V1_8822C) +#define BIT_SET_DARF_RC6_V1_8822C(x, v) \ + (BIT_CLEAR_DARF_RC6_V1_8822C(x) | BIT_DARF_RC6_V1_8822C(v)) + +#define BIT_SHIFT_DARF_RC5_V1_8822C 0 +#define BIT_MASK_DARF_RC5_V1_8822C 0x1f +#define BIT_DARF_RC5_V1_8822C(x) \ + (((x) & BIT_MASK_DARF_RC5_V1_8822C) << BIT_SHIFT_DARF_RC5_V1_8822C) +#define BITS_DARF_RC5_V1_8822C \ + (BIT_MASK_DARF_RC5_V1_8822C << BIT_SHIFT_DARF_RC5_V1_8822C) +#define BIT_CLEAR_DARF_RC5_V1_8822C(x) ((x) & (~BITS_DARF_RC5_V1_8822C)) +#define BIT_GET_DARF_RC5_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DARF_RC5_V1_8822C) & BIT_MASK_DARF_RC5_V1_8822C) +#define BIT_SET_DARF_RC5_V1_8822C(x, v) \ + (BIT_CLEAR_DARF_RC5_V1_8822C(x) | BIT_DARF_RC5_V1_8822C(v)) + +/* 2 REG_RARFRC_8822C */ + +#define BIT_SHIFT_RARF_RC4_8822C 24 +#define BIT_MASK_RARF_RC4_8822C 0x1f +#define BIT_RARF_RC4_8822C(x) \ + (((x) & BIT_MASK_RARF_RC4_8822C) << BIT_SHIFT_RARF_RC4_8822C) +#define BITS_RARF_RC4_8822C \ + (BIT_MASK_RARF_RC4_8822C << BIT_SHIFT_RARF_RC4_8822C) +#define BIT_CLEAR_RARF_RC4_8822C(x) ((x) & (~BITS_RARF_RC4_8822C)) +#define BIT_GET_RARF_RC4_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC4_8822C) & BIT_MASK_RARF_RC4_8822C) +#define BIT_SET_RARF_RC4_8822C(x, v) \ + (BIT_CLEAR_RARF_RC4_8822C(x) | BIT_RARF_RC4_8822C(v)) + +#define BIT_SHIFT_RARF_RC3_8822C 16 +#define BIT_MASK_RARF_RC3_8822C 0x1f +#define BIT_RARF_RC3_8822C(x) \ + (((x) & BIT_MASK_RARF_RC3_8822C) << BIT_SHIFT_RARF_RC3_8822C) +#define BITS_RARF_RC3_8822C \ + (BIT_MASK_RARF_RC3_8822C << BIT_SHIFT_RARF_RC3_8822C) +#define BIT_CLEAR_RARF_RC3_8822C(x) ((x) & (~BITS_RARF_RC3_8822C)) +#define BIT_GET_RARF_RC3_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC3_8822C) & BIT_MASK_RARF_RC3_8822C) +#define BIT_SET_RARF_RC3_8822C(x, v) \ + (BIT_CLEAR_RARF_RC3_8822C(x) | BIT_RARF_RC3_8822C(v)) + +#define BIT_SHIFT_RARF_RC2_8822C 8 +#define BIT_MASK_RARF_RC2_8822C 0x1f +#define BIT_RARF_RC2_8822C(x) \ + (((x) & BIT_MASK_RARF_RC2_8822C) << BIT_SHIFT_RARF_RC2_8822C) +#define BITS_RARF_RC2_8822C \ + (BIT_MASK_RARF_RC2_8822C << BIT_SHIFT_RARF_RC2_8822C) +#define BIT_CLEAR_RARF_RC2_8822C(x) ((x) & (~BITS_RARF_RC2_8822C)) +#define BIT_GET_RARF_RC2_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC2_8822C) & BIT_MASK_RARF_RC2_8822C) +#define BIT_SET_RARF_RC2_8822C(x, v) \ + (BIT_CLEAR_RARF_RC2_8822C(x) | BIT_RARF_RC2_8822C(v)) + +#define BIT_SHIFT_RARF_RC1_8822C 0 +#define BIT_MASK_RARF_RC1_8822C 0x1f +#define BIT_RARF_RC1_8822C(x) \ + (((x) & BIT_MASK_RARF_RC1_8822C) << BIT_SHIFT_RARF_RC1_8822C) +#define BITS_RARF_RC1_8822C \ + (BIT_MASK_RARF_RC1_8822C << BIT_SHIFT_RARF_RC1_8822C) +#define BIT_CLEAR_RARF_RC1_8822C(x) ((x) & (~BITS_RARF_RC1_8822C)) +#define BIT_GET_RARF_RC1_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC1_8822C) & BIT_MASK_RARF_RC1_8822C) +#define BIT_SET_RARF_RC1_8822C(x, v) \ + (BIT_CLEAR_RARF_RC1_8822C(x) | BIT_RARF_RC1_8822C(v)) + +/* 2 REG_RARFRCH_8822C */ + +#define BIT_SHIFT_RARF_RC8_V1_8822C 24 +#define BIT_MASK_RARF_RC8_V1_8822C 0x1f +#define BIT_RARF_RC8_V1_8822C(x) \ + (((x) & BIT_MASK_RARF_RC8_V1_8822C) << BIT_SHIFT_RARF_RC8_V1_8822C) +#define BITS_RARF_RC8_V1_8822C \ + (BIT_MASK_RARF_RC8_V1_8822C << BIT_SHIFT_RARF_RC8_V1_8822C) +#define BIT_CLEAR_RARF_RC8_V1_8822C(x) ((x) & (~BITS_RARF_RC8_V1_8822C)) +#define BIT_GET_RARF_RC8_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC8_V1_8822C) & BIT_MASK_RARF_RC8_V1_8822C) +#define BIT_SET_RARF_RC8_V1_8822C(x, v) \ + (BIT_CLEAR_RARF_RC8_V1_8822C(x) | BIT_RARF_RC8_V1_8822C(v)) + +#define BIT_SHIFT_RARF_RC7_V1_8822C 16 +#define BIT_MASK_RARF_RC7_V1_8822C 0x1f +#define BIT_RARF_RC7_V1_8822C(x) \ + (((x) & BIT_MASK_RARF_RC7_V1_8822C) << BIT_SHIFT_RARF_RC7_V1_8822C) +#define BITS_RARF_RC7_V1_8822C \ + (BIT_MASK_RARF_RC7_V1_8822C << BIT_SHIFT_RARF_RC7_V1_8822C) +#define BIT_CLEAR_RARF_RC7_V1_8822C(x) ((x) & (~BITS_RARF_RC7_V1_8822C)) +#define BIT_GET_RARF_RC7_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC7_V1_8822C) & BIT_MASK_RARF_RC7_V1_8822C) +#define BIT_SET_RARF_RC7_V1_8822C(x, v) \ + (BIT_CLEAR_RARF_RC7_V1_8822C(x) | BIT_RARF_RC7_V1_8822C(v)) + +#define BIT_SHIFT_RARF_RC6_V1_8822C 8 +#define BIT_MASK_RARF_RC6_V1_8822C 0x1f +#define BIT_RARF_RC6_V1_8822C(x) \ + (((x) & BIT_MASK_RARF_RC6_V1_8822C) << BIT_SHIFT_RARF_RC6_V1_8822C) +#define BITS_RARF_RC6_V1_8822C \ + (BIT_MASK_RARF_RC6_V1_8822C << BIT_SHIFT_RARF_RC6_V1_8822C) +#define BIT_CLEAR_RARF_RC6_V1_8822C(x) ((x) & (~BITS_RARF_RC6_V1_8822C)) +#define BIT_GET_RARF_RC6_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC6_V1_8822C) & BIT_MASK_RARF_RC6_V1_8822C) +#define BIT_SET_RARF_RC6_V1_8822C(x, v) \ + (BIT_CLEAR_RARF_RC6_V1_8822C(x) | BIT_RARF_RC6_V1_8822C(v)) + +#define BIT_SHIFT_RARF_RC5_V1_8822C 0 +#define BIT_MASK_RARF_RC5_V1_8822C 0x1f +#define BIT_RARF_RC5_V1_8822C(x) \ + (((x) & BIT_MASK_RARF_RC5_V1_8822C) << BIT_SHIFT_RARF_RC5_V1_8822C) +#define BITS_RARF_RC5_V1_8822C \ + (BIT_MASK_RARF_RC5_V1_8822C << BIT_SHIFT_RARF_RC5_V1_8822C) +#define BIT_CLEAR_RARF_RC5_V1_8822C(x) ((x) & (~BITS_RARF_RC5_V1_8822C)) +#define BIT_GET_RARF_RC5_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RARF_RC5_V1_8822C) & BIT_MASK_RARF_RC5_V1_8822C) +#define BIT_SET_RARF_RC5_V1_8822C(x, v) \ + (BIT_CLEAR_RARF_RC5_V1_8822C(x) | BIT_RARF_RC5_V1_8822C(v)) + +/* 2 REG_RRSR_8822C */ + +#define BIT_SHIFT_RRSR_RSC_8822C 21 +#define BIT_MASK_RRSR_RSC_8822C 0x3 +#define BIT_RRSR_RSC_8822C(x) \ + (((x) & BIT_MASK_RRSR_RSC_8822C) << BIT_SHIFT_RRSR_RSC_8822C) +#define BITS_RRSR_RSC_8822C \ + (BIT_MASK_RRSR_RSC_8822C << BIT_SHIFT_RRSR_RSC_8822C) +#define BIT_CLEAR_RRSR_RSC_8822C(x) ((x) & (~BITS_RRSR_RSC_8822C)) +#define BIT_GET_RRSR_RSC_8822C(x) \ + (((x) >> BIT_SHIFT_RRSR_RSC_8822C) & BIT_MASK_RRSR_RSC_8822C) +#define BIT_SET_RRSR_RSC_8822C(x, v) \ + (BIT_CLEAR_RRSR_RSC_8822C(x) | BIT_RRSR_RSC_8822C(v)) + +#define BIT_SHIFT_RRSC_BITMAP_8822C 0 +#define BIT_MASK_RRSC_BITMAP_8822C 0xfffff +#define BIT_RRSC_BITMAP_8822C(x) \ + (((x) & BIT_MASK_RRSC_BITMAP_8822C) << BIT_SHIFT_RRSC_BITMAP_8822C) +#define BITS_RRSC_BITMAP_8822C \ + (BIT_MASK_RRSC_BITMAP_8822C << BIT_SHIFT_RRSC_BITMAP_8822C) +#define BIT_CLEAR_RRSC_BITMAP_8822C(x) ((x) & (~BITS_RRSC_BITMAP_8822C)) +#define BIT_GET_RRSC_BITMAP_8822C(x) \ + (((x) >> BIT_SHIFT_RRSC_BITMAP_8822C) & BIT_MASK_RRSC_BITMAP_8822C) +#define BIT_SET_RRSC_BITMAP_8822C(x, v) \ + (BIT_CLEAR_RRSC_BITMAP_8822C(x) | BIT_RRSC_BITMAP_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ARFR0_8822C */ + +#define BIT_SHIFT_ARFRL0_8822C 0 +#define BIT_MASK_ARFRL0_8822C 0xffffffffL +#define BIT_ARFRL0_8822C(x) \ + (((x) & BIT_MASK_ARFRL0_8822C) << BIT_SHIFT_ARFRL0_8822C) +#define BITS_ARFRL0_8822C (BIT_MASK_ARFRL0_8822C << BIT_SHIFT_ARFRL0_8822C) +#define BIT_CLEAR_ARFRL0_8822C(x) ((x) & (~BITS_ARFRL0_8822C)) +#define BIT_GET_ARFRL0_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL0_8822C) & BIT_MASK_ARFRL0_8822C) +#define BIT_SET_ARFRL0_8822C(x, v) \ + (BIT_CLEAR_ARFRL0_8822C(x) | BIT_ARFRL0_8822C(v)) + +/* 2 REG_ARFRH0_8822C */ + +#define BIT_SHIFT_ARFRH0_8822C 0 +#define BIT_MASK_ARFRH0_8822C 0xffffffffL +#define BIT_ARFRH0_8822C(x) \ + (((x) & BIT_MASK_ARFRH0_8822C) << BIT_SHIFT_ARFRH0_8822C) +#define BITS_ARFRH0_8822C (BIT_MASK_ARFRH0_8822C << BIT_SHIFT_ARFRH0_8822C) +#define BIT_CLEAR_ARFRH0_8822C(x) ((x) & (~BITS_ARFRH0_8822C)) +#define BIT_GET_ARFRH0_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH0_8822C) & BIT_MASK_ARFRH0_8822C) +#define BIT_SET_ARFRH0_8822C(x, v) \ + (BIT_CLEAR_ARFRH0_8822C(x) | BIT_ARFRH0_8822C(v)) + +/* 2 REG_ARFR1_V1_8822C */ + +#define BIT_SHIFT_ARFRL1_8822C 0 +#define BIT_MASK_ARFRL1_8822C 0xffffffffL +#define BIT_ARFRL1_8822C(x) \ + (((x) & BIT_MASK_ARFRL1_8822C) << BIT_SHIFT_ARFRL1_8822C) +#define BITS_ARFRL1_8822C (BIT_MASK_ARFRL1_8822C << BIT_SHIFT_ARFRL1_8822C) +#define BIT_CLEAR_ARFRL1_8822C(x) ((x) & (~BITS_ARFRL1_8822C)) +#define BIT_GET_ARFRL1_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL1_8822C) & BIT_MASK_ARFRL1_8822C) +#define BIT_SET_ARFRL1_8822C(x, v) \ + (BIT_CLEAR_ARFRL1_8822C(x) | BIT_ARFRL1_8822C(v)) + +/* 2 REG_ARFRH1_V1_8822C */ + +#define BIT_SHIFT_ARFRH1_8822C 0 +#define BIT_MASK_ARFRH1_8822C 0xffffffffL +#define BIT_ARFRH1_8822C(x) \ + (((x) & BIT_MASK_ARFRH1_8822C) << BIT_SHIFT_ARFRH1_8822C) +#define BITS_ARFRH1_8822C (BIT_MASK_ARFRH1_8822C << BIT_SHIFT_ARFRH1_8822C) +#define BIT_CLEAR_ARFRH1_8822C(x) ((x) & (~BITS_ARFRH1_8822C)) +#define BIT_GET_ARFRH1_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH1_8822C) & BIT_MASK_ARFRH1_8822C) +#define BIT_SET_ARFRH1_8822C(x, v) \ + (BIT_CLEAR_ARFRH1_8822C(x) | BIT_ARFRH1_8822C(v)) + +/* 2 REG_CCK_CHECK_8822C */ +#define BIT_CHECK_CCK_EN_8822C BIT(7) +#define BIT_EN_BCN_PKT_REL_8822C BIT(6) +#define BIT_BCN_PORT_SEL_8822C BIT(5) +#define BIT_MOREDATA_BYPASS_8822C BIT(4) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_8822C BIT(3) +#define BIT_R_EN_SET_MOREDATA_8822C BIT(2) +#define BIT__R_DIS_CLEAR_MACID_RELEASE_8822C BIT(1) +#define BIT__R_MACID_RELEASE_EN_8822C BIT(0) + +/* 2 REG_AMPDU_MAX_TIME_V1_8822C */ + +#define BIT_SHIFT_AMPDU_MAX_TIME_8822C 0 +#define BIT_MASK_AMPDU_MAX_TIME_8822C 0xff +#define BIT_AMPDU_MAX_TIME_8822C(x) \ + (((x) & BIT_MASK_AMPDU_MAX_TIME_8822C) \ + << BIT_SHIFT_AMPDU_MAX_TIME_8822C) +#define BITS_AMPDU_MAX_TIME_8822C \ + (BIT_MASK_AMPDU_MAX_TIME_8822C << BIT_SHIFT_AMPDU_MAX_TIME_8822C) +#define BIT_CLEAR_AMPDU_MAX_TIME_8822C(x) ((x) & (~BITS_AMPDU_MAX_TIME_8822C)) +#define BIT_GET_AMPDU_MAX_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822C) & \ + BIT_MASK_AMPDU_MAX_TIME_8822C) +#define BIT_SET_AMPDU_MAX_TIME_8822C(x, v) \ + (BIT_CLEAR_AMPDU_MAX_TIME_8822C(x) | BIT_AMPDU_MAX_TIME_8822C(v)) + +/* 2 REG_BCNQ1_BDNY_V1_8822C */ + +#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C 0 +#define BIT_MASK_BCNQ1_PGBNDY_V1_8822C 0xfff +#define BIT_BCNQ1_PGBNDY_V1_8822C(x) \ + (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822C) \ + << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C) +#define BITS_BCNQ1_PGBNDY_V1_8822C \ + (BIT_MASK_BCNQ1_PGBNDY_V1_8822C << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C) +#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8822C(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8822C)) +#define BIT_GET_BCNQ1_PGBNDY_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C) & \ + BIT_MASK_BCNQ1_PGBNDY_V1_8822C) +#define BIT_SET_BCNQ1_PGBNDY_V1_8822C(x, v) \ + (BIT_CLEAR_BCNQ1_PGBNDY_V1_8822C(x) | BIT_BCNQ1_PGBNDY_V1_8822C(v)) + +/* 2 REG_AMPDU_MAX_LENGTH_HT_8822C */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C 0xffff +#define BIT_AMPDU_MAX_LENGTH_HT_8822C(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C) +#define BITS_AMPDU_MAX_LENGTH_HT_8822C \ + (BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8822C(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_HT_8822C)) +#define BIT_GET_AMPDU_MAX_LENGTH_HT_8822C(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C) & \ + BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C) +#define BIT_SET_AMPDU_MAX_LENGTH_HT_8822C(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8822C(x) | \ + BIT_AMPDU_MAX_LENGTH_HT_8822C(v)) + +/* 2 REG_ACQ_STOP_8822C */ +#define BIT_AC7Q_STOP_8822C BIT(7) +#define BIT_AC6Q_STOP_8822C BIT(6) +#define BIT_AC5Q_STOP_8822C BIT(5) +#define BIT_AC4Q_STOP_8822C BIT(4) +#define BIT_AC3Q_STOP_8822C BIT(3) +#define BIT_AC2Q_STOP_8822C BIT(2) +#define BIT_AC1Q_STOP_8822C BIT(1) +#define BIT_AC0Q_STOP_8822C BIT(0) + +/* 2 REG_NDPA_RATE_8822C */ + +#define BIT_SHIFT_R_NDPA_RATE_V1_8822C 0 +#define BIT_MASK_R_NDPA_RATE_V1_8822C 0xff +#define BIT_R_NDPA_RATE_V1_8822C(x) \ + (((x) & BIT_MASK_R_NDPA_RATE_V1_8822C) \ + << BIT_SHIFT_R_NDPA_RATE_V1_8822C) +#define BITS_R_NDPA_RATE_V1_8822C \ + (BIT_MASK_R_NDPA_RATE_V1_8822C << BIT_SHIFT_R_NDPA_RATE_V1_8822C) +#define BIT_CLEAR_R_NDPA_RATE_V1_8822C(x) ((x) & (~BITS_R_NDPA_RATE_V1_8822C)) +#define BIT_GET_R_NDPA_RATE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822C) & \ + BIT_MASK_R_NDPA_RATE_V1_8822C) +#define BIT_SET_R_NDPA_RATE_V1_8822C(x, v) \ + (BIT_CLEAR_R_NDPA_RATE_V1_8822C(x) | BIT_R_NDPA_RATE_V1_8822C(v)) + +/* 2 REG_TX_HANG_CTRL_8822C */ +#define BIT_R_EN_GNT_BT_AWAKE_8822C BIT(3) +#define BIT_EN_EOF_V1_8822C BIT(2) +#define BIT_DIS_OQT_BLOCK_8822C BIT(1) +#define BIT_SEARCH_QUEUE_EN_8822C BIT(0) + +/* 2 REG_NDPA_OPT_CTRL_8822C */ +#define BIT_R_DIS_MACID_RELEASE_RTY_8822C BIT(5) + +#define BIT_SHIFT_BW_SIGTA_8822C 3 +#define BIT_MASK_BW_SIGTA_8822C 0x3 +#define BIT_BW_SIGTA_8822C(x) \ + (((x) & BIT_MASK_BW_SIGTA_8822C) << BIT_SHIFT_BW_SIGTA_8822C) +#define BITS_BW_SIGTA_8822C \ + (BIT_MASK_BW_SIGTA_8822C << BIT_SHIFT_BW_SIGTA_8822C) +#define BIT_CLEAR_BW_SIGTA_8822C(x) ((x) & (~BITS_BW_SIGTA_8822C)) +#define BIT_GET_BW_SIGTA_8822C(x) \ + (((x) >> BIT_SHIFT_BW_SIGTA_8822C) & BIT_MASK_BW_SIGTA_8822C) +#define BIT_SET_BW_SIGTA_8822C(x, v) \ + (BIT_CLEAR_BW_SIGTA_8822C(x) | BIT_BW_SIGTA_8822C(v)) + +#define BIT_EN_BAR_SIGTA_8822C BIT(2) + +#define BIT_SHIFT_R_NDPA_BW_8822C 0 +#define BIT_MASK_R_NDPA_BW_8822C 0x3 +#define BIT_R_NDPA_BW_8822C(x) \ + (((x) & BIT_MASK_R_NDPA_BW_8822C) << BIT_SHIFT_R_NDPA_BW_8822C) +#define BITS_R_NDPA_BW_8822C \ + (BIT_MASK_R_NDPA_BW_8822C << BIT_SHIFT_R_NDPA_BW_8822C) +#define BIT_CLEAR_R_NDPA_BW_8822C(x) ((x) & (~BITS_R_NDPA_BW_8822C)) +#define BIT_GET_R_NDPA_BW_8822C(x) \ + (((x) >> BIT_SHIFT_R_NDPA_BW_8822C) & BIT_MASK_R_NDPA_BW_8822C) +#define BIT_SET_R_NDPA_BW_8822C(x, v) \ + (BIT_CLEAR_R_NDPA_BW_8822C(x) | BIT_R_NDPA_BW_8822C(v)) + +/* 2 REG_AMPDU_MAX_LENGTH_VHT_8822C */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C 0xfffff +#define BIT_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) \ + (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C) \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C) +#define BITS_AMPDU_MAX_LENGTH_VHT_V1_8822C \ + (BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C \ + << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C) +#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) \ + ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_V1_8822C)) +#define BIT_GET_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C) & \ + BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C) +#define BIT_SET_AMPDU_MAX_LENGTH_VHT_V1_8822C(x, v) \ + (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) | \ + BIT_AMPDU_MAX_LENGTH_VHT_V1_8822C(v)) + +/* 2 REG_RD_RESP_PKT_TH_8822C */ + +#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C 0 +#define BIT_MASK_RD_RESP_PKT_TH_V1_8822C 0x3f +#define BIT_RD_RESP_PKT_TH_V1_8822C(x) \ + (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822C) \ + << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C) +#define BITS_RD_RESP_PKT_TH_V1_8822C \ + (BIT_MASK_RD_RESP_PKT_TH_V1_8822C << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C) +#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8822C(x) \ + ((x) & (~BITS_RD_RESP_PKT_TH_V1_8822C)) +#define BIT_GET_RD_RESP_PKT_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C) & \ + BIT_MASK_RD_RESP_PKT_TH_V1_8822C) +#define BIT_SET_RD_RESP_PKT_TH_V1_8822C(x, v) \ + (BIT_CLEAR_RD_RESP_PKT_TH_V1_8822C(x) | BIT_RD_RESP_PKT_TH_V1_8822C(v)) + +/* 2 REG_CMDQ_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_CMDQ_V1_8822C 0x7f +#define BIT_QUEUEMACID_CMDQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C) +#define BITS_QUEUEMACID_CMDQ_V1_8822C \ + (BIT_MASK_QUEUEMACID_CMDQ_V1_8822C \ + << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_CMDQ_V1_8822C)) +#define BIT_GET_QUEUEMACID_CMDQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C) & \ + BIT_MASK_QUEUEMACID_CMDQ_V1_8822C) +#define BIT_SET_QUEUEMACID_CMDQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822C(x) | \ + BIT_QUEUEMACID_CMDQ_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C 23 +#define BIT_MASK_QUEUEAC_CMDQ_V1_8822C 0x3 +#define BIT_QUEUEAC_CMDQ_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822C) \ + << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C) +#define BITS_QUEUEAC_CMDQ_V1_8822C \ + (BIT_MASK_QUEUEAC_CMDQ_V1_8822C << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C) +#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8822C)) +#define BIT_GET_QUEUEAC_CMDQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C) & \ + BIT_MASK_QUEUEAC_CMDQ_V1_8822C) +#define BIT_SET_QUEUEAC_CMDQ_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_CMDQ_V1_8822C(x) | BIT_QUEUEAC_CMDQ_V1_8822C(v)) + +#define BIT_TIDEMPTY_CMDQ_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q4_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q4_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) +#define BITS_TAIL_PKT_Q4_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q4_V2_8822C << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q4_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8822C) +#define BIT_SET_TAIL_PKT_Q4_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) | BIT_TAIL_PKT_Q4_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_CMDQ_V1_8822C 0x7ff +#define BIT_HEAD_PKT_CMDQ_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C) +#define BITS_HEAD_PKT_CMDQ_V1_8822C \ + (BIT_MASK_HEAD_PKT_CMDQ_V1_8822C << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822C(x) \ + ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8822C)) +#define BIT_GET_HEAD_PKT_CMDQ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C) & \ + BIT_MASK_HEAD_PKT_CMDQ_V1_8822C) +#define BIT_SET_HEAD_PKT_CMDQ_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822C(x) | BIT_HEAD_PKT_CMDQ_V1_8822C(v)) + +/* 2 REG_Q4_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q4_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q4_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q4_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q4_V1_8822C) +#define BITS_QUEUEMACID_Q4_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q4_V1_8822C << BIT_SHIFT_QUEUEMACID_Q4_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q4_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q4_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q4_V1_8822C) +#define BIT_SET_QUEUEMACID_Q4_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q4_V1_8822C(x) | BIT_QUEUEMACID_Q4_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q4_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q4_V1_8822C 0x3 +#define BIT_QUEUEAC_Q4_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q4_V1_8822C) << BIT_SHIFT_QUEUEAC_Q4_V1_8822C) +#define BITS_QUEUEAC_Q4_V1_8822C \ + (BIT_MASK_QUEUEAC_Q4_V1_8822C << BIT_SHIFT_QUEUEAC_Q4_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q4_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8822C)) +#define BIT_GET_QUEUEAC_Q4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822C) & BIT_MASK_QUEUEAC_Q4_V1_8822C) +#define BIT_SET_QUEUEAC_Q4_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q4_V1_8822C(x) | BIT_QUEUEAC_Q4_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q4_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q4_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q4_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) +#define BITS_TAIL_PKT_Q4_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q4_V2_8822C << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q4_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q4_V2_8822C) +#define BIT_SET_TAIL_PKT_Q4_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) | BIT_TAIL_PKT_Q4_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q4_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q4_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q4_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q4_V1_8822C) +#define BITS_HEAD_PKT_Q4_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q4_V1_8822C << BIT_SHIFT_HEAD_PKT_Q4_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q4_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q4_V1_8822C) +#define BIT_SET_HEAD_PKT_Q4_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q4_V1_8822C(x) | BIT_HEAD_PKT_Q4_V1_8822C(v)) + +/* 2 REG_Q5_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q5_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q5_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q5_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q5_V1_8822C) +#define BITS_QUEUEMACID_Q5_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q5_V1_8822C << BIT_SHIFT_QUEUEMACID_Q5_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q5_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q5_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q5_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q5_V1_8822C) +#define BIT_SET_QUEUEMACID_Q5_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q5_V1_8822C(x) | BIT_QUEUEMACID_Q5_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q5_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q5_V1_8822C 0x3 +#define BIT_QUEUEAC_Q5_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q5_V1_8822C) << BIT_SHIFT_QUEUEAC_Q5_V1_8822C) +#define BITS_QUEUEAC_Q5_V1_8822C \ + (BIT_MASK_QUEUEAC_Q5_V1_8822C << BIT_SHIFT_QUEUEAC_Q5_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q5_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8822C)) +#define BIT_GET_QUEUEAC_Q5_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822C) & BIT_MASK_QUEUEAC_Q5_V1_8822C) +#define BIT_SET_QUEUEAC_Q5_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q5_V1_8822C(x) | BIT_QUEUEAC_Q5_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q5_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q5_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q5_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q5_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q5_V2_8822C) +#define BITS_TAIL_PKT_Q5_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q5_V2_8822C << BIT_SHIFT_TAIL_PKT_Q5_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q5_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q5_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q5_V2_8822C) +#define BIT_SET_TAIL_PKT_Q5_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q5_V2_8822C(x) | BIT_TAIL_PKT_Q5_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q5_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q5_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q5_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q5_V1_8822C) +#define BITS_HEAD_PKT_Q5_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q5_V1_8822C << BIT_SHIFT_HEAD_PKT_Q5_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q5_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q5_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q5_V1_8822C) +#define BIT_SET_HEAD_PKT_Q5_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q5_V1_8822C(x) | BIT_HEAD_PKT_Q5_V1_8822C(v)) + +/* 2 REG_Q6_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q6_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q6_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q6_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q6_V1_8822C) +#define BITS_QUEUEMACID_Q6_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q6_V1_8822C << BIT_SHIFT_QUEUEMACID_Q6_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q6_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q6_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q6_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q6_V1_8822C) +#define BIT_SET_QUEUEMACID_Q6_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q6_V1_8822C(x) | BIT_QUEUEMACID_Q6_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q6_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q6_V1_8822C 0x3 +#define BIT_QUEUEAC_Q6_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q6_V1_8822C) << BIT_SHIFT_QUEUEAC_Q6_V1_8822C) +#define BITS_QUEUEAC_Q6_V1_8822C \ + (BIT_MASK_QUEUEAC_Q6_V1_8822C << BIT_SHIFT_QUEUEAC_Q6_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q6_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8822C)) +#define BIT_GET_QUEUEAC_Q6_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822C) & BIT_MASK_QUEUEAC_Q6_V1_8822C) +#define BIT_SET_QUEUEAC_Q6_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q6_V1_8822C(x) | BIT_QUEUEAC_Q6_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q6_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q6_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q6_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q6_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q6_V2_8822C) +#define BITS_TAIL_PKT_Q6_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q6_V2_8822C << BIT_SHIFT_TAIL_PKT_Q6_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q6_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q6_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q6_V2_8822C) +#define BIT_SET_TAIL_PKT_Q6_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q6_V2_8822C(x) | BIT_TAIL_PKT_Q6_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q6_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q6_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q6_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q6_V1_8822C) +#define BITS_HEAD_PKT_Q6_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q6_V1_8822C << BIT_SHIFT_HEAD_PKT_Q6_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q6_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q6_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q6_V1_8822C) +#define BIT_SET_HEAD_PKT_Q6_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q6_V1_8822C(x) | BIT_HEAD_PKT_Q6_V1_8822C(v)) + +/* 2 REG_Q7_INFO_8822C */ + +#define BIT_SHIFT_QUEUEMACID_Q7_V1_8822C 25 +#define BIT_MASK_QUEUEMACID_Q7_V1_8822C 0x7f +#define BIT_QUEUEMACID_Q7_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822C) \ + << BIT_SHIFT_QUEUEMACID_Q7_V1_8822C) +#define BITS_QUEUEMACID_Q7_V1_8822C \ + (BIT_MASK_QUEUEMACID_Q7_V1_8822C << BIT_SHIFT_QUEUEMACID_Q7_V1_8822C) +#define BIT_CLEAR_QUEUEMACID_Q7_V1_8822C(x) \ + ((x) & (~BITS_QUEUEMACID_Q7_V1_8822C)) +#define BIT_GET_QUEUEMACID_Q7_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822C) & \ + BIT_MASK_QUEUEMACID_Q7_V1_8822C) +#define BIT_SET_QUEUEMACID_Q7_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEMACID_Q7_V1_8822C(x) | BIT_QUEUEMACID_Q7_V1_8822C(v)) + +#define BIT_SHIFT_QUEUEAC_Q7_V1_8822C 23 +#define BIT_MASK_QUEUEAC_Q7_V1_8822C 0x3 +#define BIT_QUEUEAC_Q7_V1_8822C(x) \ + (((x) & BIT_MASK_QUEUEAC_Q7_V1_8822C) << BIT_SHIFT_QUEUEAC_Q7_V1_8822C) +#define BITS_QUEUEAC_Q7_V1_8822C \ + (BIT_MASK_QUEUEAC_Q7_V1_8822C << BIT_SHIFT_QUEUEAC_Q7_V1_8822C) +#define BIT_CLEAR_QUEUEAC_Q7_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8822C)) +#define BIT_GET_QUEUEAC_Q7_V1_8822C(x) \ + (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822C) & BIT_MASK_QUEUEAC_Q7_V1_8822C) +#define BIT_SET_QUEUEAC_Q7_V1_8822C(x, v) \ + (BIT_CLEAR_QUEUEAC_Q7_V1_8822C(x) | BIT_QUEUEAC_Q7_V1_8822C(v)) + +#define BIT_TIDEMPTY_Q7_V1_8822C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q7_V2_8822C 11 +#define BIT_MASK_TAIL_PKT_Q7_V2_8822C 0x7ff +#define BIT_TAIL_PKT_Q7_V2_8822C(x) \ + (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822C) \ + << BIT_SHIFT_TAIL_PKT_Q7_V2_8822C) +#define BITS_TAIL_PKT_Q7_V2_8822C \ + (BIT_MASK_TAIL_PKT_Q7_V2_8822C << BIT_SHIFT_TAIL_PKT_Q7_V2_8822C) +#define BIT_CLEAR_TAIL_PKT_Q7_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8822C)) +#define BIT_GET_TAIL_PKT_Q7_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822C) & \ + BIT_MASK_TAIL_PKT_Q7_V2_8822C) +#define BIT_SET_TAIL_PKT_Q7_V2_8822C(x, v) \ + (BIT_CLEAR_TAIL_PKT_Q7_V2_8822C(x) | BIT_TAIL_PKT_Q7_V2_8822C(v)) + +#define BIT_SHIFT_HEAD_PKT_Q7_V1_8822C 0 +#define BIT_MASK_HEAD_PKT_Q7_V1_8822C 0x7ff +#define BIT_HEAD_PKT_Q7_V1_8822C(x) \ + (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822C) \ + << BIT_SHIFT_HEAD_PKT_Q7_V1_8822C) +#define BITS_HEAD_PKT_Q7_V1_8822C \ + (BIT_MASK_HEAD_PKT_Q7_V1_8822C << BIT_SHIFT_HEAD_PKT_Q7_V1_8822C) +#define BIT_CLEAR_HEAD_PKT_Q7_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8822C)) +#define BIT_GET_HEAD_PKT_Q7_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822C) & \ + BIT_MASK_HEAD_PKT_Q7_V1_8822C) +#define BIT_SET_HEAD_PKT_Q7_V1_8822C(x, v) \ + (BIT_CLEAR_HEAD_PKT_Q7_V1_8822C(x) | BIT_HEAD_PKT_Q7_V1_8822C(v)) + +/* 2 REG_WMAC_LBK_BUF_HD_V1_8822C */ + +#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C 0 +#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C 0xfff +#define BIT_WMAC_LBK_BUF_HEAD_V1_8822C(x) \ + (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C) \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C) +#define BITS_WMAC_LBK_BUF_HEAD_V1_8822C \ + (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C \ + << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C) +#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822C(x) \ + ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8822C)) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C) & \ + BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C) +#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8822C(x, v) \ + (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822C(x) | \ + BIT_WMAC_LBK_BUF_HEAD_V1_8822C(v)) + +/* 2 REG_MGQ_BDNY_V1_8822C */ + +#define BIT_SHIFT_MGQ_PGBNDY_V1_8822C 0 +#define BIT_MASK_MGQ_PGBNDY_V1_8822C 0xfff +#define BIT_MGQ_PGBNDY_V1_8822C(x) \ + (((x) & BIT_MASK_MGQ_PGBNDY_V1_8822C) << BIT_SHIFT_MGQ_PGBNDY_V1_8822C) +#define BITS_MGQ_PGBNDY_V1_8822C \ + (BIT_MASK_MGQ_PGBNDY_V1_8822C << BIT_SHIFT_MGQ_PGBNDY_V1_8822C) +#define BIT_CLEAR_MGQ_PGBNDY_V1_8822C(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8822C)) +#define BIT_GET_MGQ_PGBNDY_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822C) & BIT_MASK_MGQ_PGBNDY_V1_8822C) +#define BIT_SET_MGQ_PGBNDY_V1_8822C(x, v) \ + (BIT_CLEAR_MGQ_PGBNDY_V1_8822C(x) | BIT_MGQ_PGBNDY_V1_8822C(v)) + +/* 2 REG_TXRPT_CTRL_8822C */ + +#define BIT_SHIFT_TRXRPT_TIMER_TH_8822C 24 +#define BIT_MASK_TRXRPT_TIMER_TH_8822C 0xff +#define BIT_TRXRPT_TIMER_TH_8822C(x) \ + (((x) & BIT_MASK_TRXRPT_TIMER_TH_8822C) \ + << BIT_SHIFT_TRXRPT_TIMER_TH_8822C) +#define BITS_TRXRPT_TIMER_TH_8822C \ + (BIT_MASK_TRXRPT_TIMER_TH_8822C << BIT_SHIFT_TRXRPT_TIMER_TH_8822C) +#define BIT_CLEAR_TRXRPT_TIMER_TH_8822C(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8822C)) +#define BIT_GET_TRXRPT_TIMER_TH_8822C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822C) & \ + BIT_MASK_TRXRPT_TIMER_TH_8822C) +#define BIT_SET_TRXRPT_TIMER_TH_8822C(x, v) \ + (BIT_CLEAR_TRXRPT_TIMER_TH_8822C(x) | BIT_TRXRPT_TIMER_TH_8822C(v)) + +#define BIT_SHIFT_TRXRPT_LEN_TH_8822C 16 +#define BIT_MASK_TRXRPT_LEN_TH_8822C 0xff +#define BIT_TRXRPT_LEN_TH_8822C(x) \ + (((x) & BIT_MASK_TRXRPT_LEN_TH_8822C) << BIT_SHIFT_TRXRPT_LEN_TH_8822C) +#define BITS_TRXRPT_LEN_TH_8822C \ + (BIT_MASK_TRXRPT_LEN_TH_8822C << BIT_SHIFT_TRXRPT_LEN_TH_8822C) +#define BIT_CLEAR_TRXRPT_LEN_TH_8822C(x) ((x) & (~BITS_TRXRPT_LEN_TH_8822C)) +#define BIT_GET_TRXRPT_LEN_TH_8822C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822C) & BIT_MASK_TRXRPT_LEN_TH_8822C) +#define BIT_SET_TRXRPT_LEN_TH_8822C(x, v) \ + (BIT_CLEAR_TRXRPT_LEN_TH_8822C(x) | BIT_TRXRPT_LEN_TH_8822C(v)) + +#define BIT_SHIFT_TRXRPT_READ_PTR_8822C 8 +#define BIT_MASK_TRXRPT_READ_PTR_8822C 0xff +#define BIT_TRXRPT_READ_PTR_8822C(x) \ + (((x) & BIT_MASK_TRXRPT_READ_PTR_8822C) \ + << BIT_SHIFT_TRXRPT_READ_PTR_8822C) +#define BITS_TRXRPT_READ_PTR_8822C \ + (BIT_MASK_TRXRPT_READ_PTR_8822C << BIT_SHIFT_TRXRPT_READ_PTR_8822C) +#define BIT_CLEAR_TRXRPT_READ_PTR_8822C(x) ((x) & (~BITS_TRXRPT_READ_PTR_8822C)) +#define BIT_GET_TRXRPT_READ_PTR_8822C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822C) & \ + BIT_MASK_TRXRPT_READ_PTR_8822C) +#define BIT_SET_TRXRPT_READ_PTR_8822C(x, v) \ + (BIT_CLEAR_TRXRPT_READ_PTR_8822C(x) | BIT_TRXRPT_READ_PTR_8822C(v)) + +#define BIT_SHIFT_TRXRPT_WRITE_PTR_8822C 0 +#define BIT_MASK_TRXRPT_WRITE_PTR_8822C 0xff +#define BIT_TRXRPT_WRITE_PTR_8822C(x) \ + (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822C) \ + << BIT_SHIFT_TRXRPT_WRITE_PTR_8822C) +#define BITS_TRXRPT_WRITE_PTR_8822C \ + (BIT_MASK_TRXRPT_WRITE_PTR_8822C << BIT_SHIFT_TRXRPT_WRITE_PTR_8822C) +#define BIT_CLEAR_TRXRPT_WRITE_PTR_8822C(x) \ + ((x) & (~BITS_TRXRPT_WRITE_PTR_8822C)) +#define BIT_GET_TRXRPT_WRITE_PTR_8822C(x) \ + (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822C) & \ + BIT_MASK_TRXRPT_WRITE_PTR_8822C) +#define BIT_SET_TRXRPT_WRITE_PTR_8822C(x, v) \ + (BIT_CLEAR_TRXRPT_WRITE_PTR_8822C(x) | BIT_TRXRPT_WRITE_PTR_8822C(v)) + +/* 2 REG_INIRTS_RATE_SEL_8822C */ +#define BIT_LEAG_RTS_BW_DUP_8822C BIT(5) + +/* 2 REG_BASIC_CFEND_RATE_8822C */ + +#define BIT_SHIFT_BASIC_CFEND_RATE_8822C 0 +#define BIT_MASK_BASIC_CFEND_RATE_8822C 0x1f +#define BIT_BASIC_CFEND_RATE_8822C(x) \ + (((x) & BIT_MASK_BASIC_CFEND_RATE_8822C) \ + << BIT_SHIFT_BASIC_CFEND_RATE_8822C) +#define BITS_BASIC_CFEND_RATE_8822C \ + (BIT_MASK_BASIC_CFEND_RATE_8822C << BIT_SHIFT_BASIC_CFEND_RATE_8822C) +#define BIT_CLEAR_BASIC_CFEND_RATE_8822C(x) \ + ((x) & (~BITS_BASIC_CFEND_RATE_8822C)) +#define BIT_GET_BASIC_CFEND_RATE_8822C(x) \ + (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822C) & \ + BIT_MASK_BASIC_CFEND_RATE_8822C) +#define BIT_SET_BASIC_CFEND_RATE_8822C(x, v) \ + (BIT_CLEAR_BASIC_CFEND_RATE_8822C(x) | BIT_BASIC_CFEND_RATE_8822C(v)) + +/* 2 REG_STBC_CFEND_RATE_8822C */ + +#define BIT_SHIFT_STBC_CFEND_RATE_8822C 0 +#define BIT_MASK_STBC_CFEND_RATE_8822C 0x1f +#define BIT_STBC_CFEND_RATE_8822C(x) \ + (((x) & BIT_MASK_STBC_CFEND_RATE_8822C) \ + << BIT_SHIFT_STBC_CFEND_RATE_8822C) +#define BITS_STBC_CFEND_RATE_8822C \ + (BIT_MASK_STBC_CFEND_RATE_8822C << BIT_SHIFT_STBC_CFEND_RATE_8822C) +#define BIT_CLEAR_STBC_CFEND_RATE_8822C(x) ((x) & (~BITS_STBC_CFEND_RATE_8822C)) +#define BIT_GET_STBC_CFEND_RATE_8822C(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822C) & \ + BIT_MASK_STBC_CFEND_RATE_8822C) +#define BIT_SET_STBC_CFEND_RATE_8822C(x, v) \ + (BIT_CLEAR_STBC_CFEND_RATE_8822C(x) | BIT_STBC_CFEND_RATE_8822C(v)) + +/* 2 REG_DATA_SC_8822C */ + +#define BIT_SHIFT_TXSC_40M_8822C 4 +#define BIT_MASK_TXSC_40M_8822C 0xf +#define BIT_TXSC_40M_8822C(x) \ + (((x) & BIT_MASK_TXSC_40M_8822C) << BIT_SHIFT_TXSC_40M_8822C) +#define BITS_TXSC_40M_8822C \ + (BIT_MASK_TXSC_40M_8822C << BIT_SHIFT_TXSC_40M_8822C) +#define BIT_CLEAR_TXSC_40M_8822C(x) ((x) & (~BITS_TXSC_40M_8822C)) +#define BIT_GET_TXSC_40M_8822C(x) \ + (((x) >> BIT_SHIFT_TXSC_40M_8822C) & BIT_MASK_TXSC_40M_8822C) +#define BIT_SET_TXSC_40M_8822C(x, v) \ + (BIT_CLEAR_TXSC_40M_8822C(x) | BIT_TXSC_40M_8822C(v)) + +#define BIT_SHIFT_TXSC_20M_8822C 0 +#define BIT_MASK_TXSC_20M_8822C 0xf +#define BIT_TXSC_20M_8822C(x) \ + (((x) & BIT_MASK_TXSC_20M_8822C) << BIT_SHIFT_TXSC_20M_8822C) +#define BITS_TXSC_20M_8822C \ + (BIT_MASK_TXSC_20M_8822C << BIT_SHIFT_TXSC_20M_8822C) +#define BIT_CLEAR_TXSC_20M_8822C(x) ((x) & (~BITS_TXSC_20M_8822C)) +#define BIT_GET_TXSC_20M_8822C(x) \ + (((x) >> BIT_SHIFT_TXSC_20M_8822C) & BIT_MASK_TXSC_20M_8822C) +#define BIT_SET_TXSC_20M_8822C(x, v) \ + (BIT_CLEAR_TXSC_20M_8822C(x) | BIT_TXSC_20M_8822C(v)) + +/* 2 REG_MACID_SLEEP3_8822C */ + +#define BIT_SHIFT_MACID127_96_PKTSLEEP_8822C 0 +#define BIT_MASK_MACID127_96_PKTSLEEP_8822C 0xffffffffL +#define BIT_MACID127_96_PKTSLEEP_8822C(x) \ + (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822C) \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8822C) +#define BITS_MACID127_96_PKTSLEEP_8822C \ + (BIT_MASK_MACID127_96_PKTSLEEP_8822C \ + << BIT_SHIFT_MACID127_96_PKTSLEEP_8822C) +#define BIT_CLEAR_MACID127_96_PKTSLEEP_8822C(x) \ + ((x) & (~BITS_MACID127_96_PKTSLEEP_8822C)) +#define BIT_GET_MACID127_96_PKTSLEEP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822C) & \ + BIT_MASK_MACID127_96_PKTSLEEP_8822C) +#define BIT_SET_MACID127_96_PKTSLEEP_8822C(x, v) \ + (BIT_CLEAR_MACID127_96_PKTSLEEP_8822C(x) | \ + BIT_MACID127_96_PKTSLEEP_8822C(v)) + +/* 2 REG_MACID_SLEEP1_8822C */ + +#define BIT_SHIFT_MACID63_32_PKTSLEEP_8822C 0 +#define BIT_MASK_MACID63_32_PKTSLEEP_8822C 0xffffffffL +#define BIT_MACID63_32_PKTSLEEP_8822C(x) \ + (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822C) \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8822C) +#define BITS_MACID63_32_PKTSLEEP_8822C \ + (BIT_MASK_MACID63_32_PKTSLEEP_8822C \ + << BIT_SHIFT_MACID63_32_PKTSLEEP_8822C) +#define BIT_CLEAR_MACID63_32_PKTSLEEP_8822C(x) \ + ((x) & (~BITS_MACID63_32_PKTSLEEP_8822C)) +#define BIT_GET_MACID63_32_PKTSLEEP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822C) & \ + BIT_MASK_MACID63_32_PKTSLEEP_8822C) +#define BIT_SET_MACID63_32_PKTSLEEP_8822C(x, v) \ + (BIT_CLEAR_MACID63_32_PKTSLEEP_8822C(x) | \ + BIT_MACID63_32_PKTSLEEP_8822C(v)) + +/* 2 REG_ARFR2_V1_8822C */ + +#define BIT_SHIFT_ARFRL2_8822C 0 +#define BIT_MASK_ARFRL2_8822C 0xffffffffL +#define BIT_ARFRL2_8822C(x) \ + (((x) & BIT_MASK_ARFRL2_8822C) << BIT_SHIFT_ARFRL2_8822C) +#define BITS_ARFRL2_8822C (BIT_MASK_ARFRL2_8822C << BIT_SHIFT_ARFRL2_8822C) +#define BIT_CLEAR_ARFRL2_8822C(x) ((x) & (~BITS_ARFRL2_8822C)) +#define BIT_GET_ARFRL2_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL2_8822C) & BIT_MASK_ARFRL2_8822C) +#define BIT_SET_ARFRL2_8822C(x, v) \ + (BIT_CLEAR_ARFRL2_8822C(x) | BIT_ARFRL2_8822C(v)) + +/* 2 REG_ARFRH2_V1_8822C */ + +#define BIT_SHIFT_ARFRH2_8822C 0 +#define BIT_MASK_ARFRH2_8822C 0xffffffffL +#define BIT_ARFRH2_8822C(x) \ + (((x) & BIT_MASK_ARFRH2_8822C) << BIT_SHIFT_ARFRH2_8822C) +#define BITS_ARFRH2_8822C (BIT_MASK_ARFRH2_8822C << BIT_SHIFT_ARFRH2_8822C) +#define BIT_CLEAR_ARFRH2_8822C(x) ((x) & (~BITS_ARFRH2_8822C)) +#define BIT_GET_ARFRH2_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH2_8822C) & BIT_MASK_ARFRH2_8822C) +#define BIT_SET_ARFRH2_8822C(x, v) \ + (BIT_CLEAR_ARFRH2_8822C(x) | BIT_ARFRH2_8822C(v)) + +/* 2 REG_ARFR3_V1_8822C */ + +#define BIT_SHIFT_ARFRL3_8822C 0 +#define BIT_MASK_ARFRL3_8822C 0xffffffffL +#define BIT_ARFRL3_8822C(x) \ + (((x) & BIT_MASK_ARFRL3_8822C) << BIT_SHIFT_ARFRL3_8822C) +#define BITS_ARFRL3_8822C (BIT_MASK_ARFRL3_8822C << BIT_SHIFT_ARFRL3_8822C) +#define BIT_CLEAR_ARFRL3_8822C(x) ((x) & (~BITS_ARFRL3_8822C)) +#define BIT_GET_ARFRL3_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL3_8822C) & BIT_MASK_ARFRL3_8822C) +#define BIT_SET_ARFRL3_8822C(x, v) \ + (BIT_CLEAR_ARFRL3_8822C(x) | BIT_ARFRL3_8822C(v)) + +/* 2 REG_ARFRH3_V1_8822C */ + +#define BIT_SHIFT_ARFRH3_8822C 0 +#define BIT_MASK_ARFRH3_8822C 0xffffffffL +#define BIT_ARFRH3_8822C(x) \ + (((x) & BIT_MASK_ARFRH3_8822C) << BIT_SHIFT_ARFRH3_8822C) +#define BITS_ARFRH3_8822C (BIT_MASK_ARFRH3_8822C << BIT_SHIFT_ARFRH3_8822C) +#define BIT_CLEAR_ARFRH3_8822C(x) ((x) & (~BITS_ARFRH3_8822C)) +#define BIT_GET_ARFRH3_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH3_8822C) & BIT_MASK_ARFRH3_8822C) +#define BIT_SET_ARFRH3_8822C(x, v) \ + (BIT_CLEAR_ARFRH3_8822C(x) | BIT_ARFRH3_8822C(v)) + +/* 2 REG_ARFR4_8822C */ + +#define BIT_SHIFT_ARFRL4_8822C 0 +#define BIT_MASK_ARFRL4_8822C 0xffffffffL +#define BIT_ARFRL4_8822C(x) \ + (((x) & BIT_MASK_ARFRL4_8822C) << BIT_SHIFT_ARFRL4_8822C) +#define BITS_ARFRL4_8822C (BIT_MASK_ARFRL4_8822C << BIT_SHIFT_ARFRL4_8822C) +#define BIT_CLEAR_ARFRL4_8822C(x) ((x) & (~BITS_ARFRL4_8822C)) +#define BIT_GET_ARFRL4_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL4_8822C) & BIT_MASK_ARFRL4_8822C) +#define BIT_SET_ARFRL4_8822C(x, v) \ + (BIT_CLEAR_ARFRL4_8822C(x) | BIT_ARFRL4_8822C(v)) + +/* 2 REG_ARFRH4_8822C */ + +#define BIT_SHIFT_ARFRH4_8822C 0 +#define BIT_MASK_ARFRH4_8822C 0xffffffffL +#define BIT_ARFRH4_8822C(x) \ + (((x) & BIT_MASK_ARFRH4_8822C) << BIT_SHIFT_ARFRH4_8822C) +#define BITS_ARFRH4_8822C (BIT_MASK_ARFRH4_8822C << BIT_SHIFT_ARFRH4_8822C) +#define BIT_CLEAR_ARFRH4_8822C(x) ((x) & (~BITS_ARFRH4_8822C)) +#define BIT_GET_ARFRH4_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH4_8822C) & BIT_MASK_ARFRH4_8822C) +#define BIT_SET_ARFRH4_8822C(x, v) \ + (BIT_CLEAR_ARFRH4_8822C(x) | BIT_ARFRH4_8822C(v)) + +/* 2 REG_ARFR5_8822C */ + +#define BIT_SHIFT_ARFRL5_8822C 0 +#define BIT_MASK_ARFRL5_8822C 0xffffffffL +#define BIT_ARFRL5_8822C(x) \ + (((x) & BIT_MASK_ARFRL5_8822C) << BIT_SHIFT_ARFRL5_8822C) +#define BITS_ARFRL5_8822C (BIT_MASK_ARFRL5_8822C << BIT_SHIFT_ARFRL5_8822C) +#define BIT_CLEAR_ARFRL5_8822C(x) ((x) & (~BITS_ARFRL5_8822C)) +#define BIT_GET_ARFRL5_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRL5_8822C) & BIT_MASK_ARFRL5_8822C) +#define BIT_SET_ARFRL5_8822C(x, v) \ + (BIT_CLEAR_ARFRL5_8822C(x) | BIT_ARFRL5_8822C(v)) + +/* 2 REG_ARFRH5_8822C */ + +#define BIT_SHIFT_ARFRH5_8822C 0 +#define BIT_MASK_ARFRH5_8822C 0xffffffffL +#define BIT_ARFRH5_8822C(x) \ + (((x) & BIT_MASK_ARFRH5_8822C) << BIT_SHIFT_ARFRH5_8822C) +#define BITS_ARFRH5_8822C (BIT_MASK_ARFRH5_8822C << BIT_SHIFT_ARFRH5_8822C) +#define BIT_CLEAR_ARFRH5_8822C(x) ((x) & (~BITS_ARFRH5_8822C)) +#define BIT_GET_ARFRH5_8822C(x) \ + (((x) >> BIT_SHIFT_ARFRH5_8822C) & BIT_MASK_ARFRH5_8822C) +#define BIT_SET_ARFRH5_8822C(x, v) \ + (BIT_CLEAR_ARFRH5_8822C(x) | BIT_ARFRH5_8822C(v)) + +/* 2 REG_TXRPT_START_OFFSET_8822C */ + +#define BIT_SHIFT_MACID_MURATE_OFFSET_8822C 24 +#define BIT_MASK_MACID_MURATE_OFFSET_8822C 0xff +#define BIT_MACID_MURATE_OFFSET_8822C(x) \ + (((x) & BIT_MASK_MACID_MURATE_OFFSET_8822C) \ + << BIT_SHIFT_MACID_MURATE_OFFSET_8822C) +#define BITS_MACID_MURATE_OFFSET_8822C \ + (BIT_MASK_MACID_MURATE_OFFSET_8822C \ + << BIT_SHIFT_MACID_MURATE_OFFSET_8822C) +#define BIT_CLEAR_MACID_MURATE_OFFSET_8822C(x) \ + ((x) & (~BITS_MACID_MURATE_OFFSET_8822C)) +#define BIT_GET_MACID_MURATE_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822C) & \ + BIT_MASK_MACID_MURATE_OFFSET_8822C) +#define BIT_SET_MACID_MURATE_OFFSET_8822C(x, v) \ + (BIT_CLEAR_MACID_MURATE_OFFSET_8822C(x) | \ + BIT_MACID_MURATE_OFFSET_8822C(v)) + +#define BIT_SHIFT_TXRPT_MISS_COUNT_8822C 17 +#define BIT_MASK_TXRPT_MISS_COUNT_8822C 0x7 +#define BIT_TXRPT_MISS_COUNT_8822C(x) \ + (((x) & BIT_MASK_TXRPT_MISS_COUNT_8822C) \ + << BIT_SHIFT_TXRPT_MISS_COUNT_8822C) +#define BITS_TXRPT_MISS_COUNT_8822C \ + (BIT_MASK_TXRPT_MISS_COUNT_8822C << BIT_SHIFT_TXRPT_MISS_COUNT_8822C) +#define BIT_CLEAR_TXRPT_MISS_COUNT_8822C(x) \ + ((x) & (~BITS_TXRPT_MISS_COUNT_8822C)) +#define BIT_GET_TXRPT_MISS_COUNT_8822C(x) \ + (((x) >> BIT_SHIFT_TXRPT_MISS_COUNT_8822C) & \ + BIT_MASK_TXRPT_MISS_COUNT_8822C) +#define BIT_SET_TXRPT_MISS_COUNT_8822C(x, v) \ + (BIT_CLEAR_TXRPT_MISS_COUNT_8822C(x) | BIT_TXRPT_MISS_COUNT_8822C(v)) + +#define BIT_RPTFIFO_SIZE_OPT_8822C BIT(16) + +#define BIT_SHIFT_MACID_CTRL_OFFSET_8822C 8 +#define BIT_MASK_MACID_CTRL_OFFSET_8822C 0xff +#define BIT_MACID_CTRL_OFFSET_8822C(x) \ + (((x) & BIT_MASK_MACID_CTRL_OFFSET_8822C) \ + << BIT_SHIFT_MACID_CTRL_OFFSET_8822C) +#define BITS_MACID_CTRL_OFFSET_8822C \ + (BIT_MASK_MACID_CTRL_OFFSET_8822C << BIT_SHIFT_MACID_CTRL_OFFSET_8822C) +#define BIT_CLEAR_MACID_CTRL_OFFSET_8822C(x) \ + ((x) & (~BITS_MACID_CTRL_OFFSET_8822C)) +#define BIT_GET_MACID_CTRL_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822C) & \ + BIT_MASK_MACID_CTRL_OFFSET_8822C) +#define BIT_SET_MACID_CTRL_OFFSET_8822C(x, v) \ + (BIT_CLEAR_MACID_CTRL_OFFSET_8822C(x) | BIT_MACID_CTRL_OFFSET_8822C(v)) + +#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C 0 +#define BIT_MASK_AMPDU_TXRPT_OFFSET_8822C 0xff +#define BIT_AMPDU_TXRPT_OFFSET_8822C(x) \ + (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822C) \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C) +#define BITS_AMPDU_TXRPT_OFFSET_8822C \ + (BIT_MASK_AMPDU_TXRPT_OFFSET_8822C \ + << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C) +#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822C(x) \ + ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8822C)) +#define BIT_GET_AMPDU_TXRPT_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C) & \ + BIT_MASK_AMPDU_TXRPT_OFFSET_8822C) +#define BIT_SET_AMPDU_TXRPT_OFFSET_8822C(x, v) \ + (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822C(x) | \ + BIT_AMPDU_TXRPT_OFFSET_8822C(v)) + +/* 2 REG_POWER_STAGE1_8822C */ +#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822C BIT(31) +#define BIT_PTA_WL_PRI_MASK_BCNQ_8822C BIT(30) +#define BIT_PTA_WL_PRI_MASK_HIQ_8822C BIT(29) +#define BIT_PTA_WL_PRI_MASK_MGQ_8822C BIT(28) +#define BIT_PTA_WL_PRI_MASK_BK_8822C BIT(27) +#define BIT_PTA_WL_PRI_MASK_BE_8822C BIT(26) +#define BIT_PTA_WL_PRI_MASK_VI_8822C BIT(25) +#define BIT_PTA_WL_PRI_MASK_VO_8822C BIT(24) + +#define BIT_SHIFT_POWER_STAGE1_8822C 0 +#define BIT_MASK_POWER_STAGE1_8822C 0xffffff +#define BIT_POWER_STAGE1_8822C(x) \ + (((x) & BIT_MASK_POWER_STAGE1_8822C) << BIT_SHIFT_POWER_STAGE1_8822C) +#define BITS_POWER_STAGE1_8822C \ + (BIT_MASK_POWER_STAGE1_8822C << BIT_SHIFT_POWER_STAGE1_8822C) +#define BIT_CLEAR_POWER_STAGE1_8822C(x) ((x) & (~BITS_POWER_STAGE1_8822C)) +#define BIT_GET_POWER_STAGE1_8822C(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE1_8822C) & BIT_MASK_POWER_STAGE1_8822C) +#define BIT_SET_POWER_STAGE1_8822C(x, v) \ + (BIT_CLEAR_POWER_STAGE1_8822C(x) | BIT_POWER_STAGE1_8822C(v)) + +/* 2 REG_POWER_STAGE2_8822C */ +#define BIT__R_CTRL_PKT_POW_ADJ_8822C BIT(24) + +#define BIT_SHIFT_POWER_STAGE2_8822C 0 +#define BIT_MASK_POWER_STAGE2_8822C 0xffffff +#define BIT_POWER_STAGE2_8822C(x) \ + (((x) & BIT_MASK_POWER_STAGE2_8822C) << BIT_SHIFT_POWER_STAGE2_8822C) +#define BITS_POWER_STAGE2_8822C \ + (BIT_MASK_POWER_STAGE2_8822C << BIT_SHIFT_POWER_STAGE2_8822C) +#define BIT_CLEAR_POWER_STAGE2_8822C(x) ((x) & (~BITS_POWER_STAGE2_8822C)) +#define BIT_GET_POWER_STAGE2_8822C(x) \ + (((x) >> BIT_SHIFT_POWER_STAGE2_8822C) & BIT_MASK_POWER_STAGE2_8822C) +#define BIT_SET_POWER_STAGE2_8822C(x, v) \ + (BIT_CLEAR_POWER_STAGE2_8822C(x) | BIT_POWER_STAGE2_8822C(v)) + +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822C */ + +#define BIT_SHIFT_PAD_NUM_THRES_8822C 24 +#define BIT_MASK_PAD_NUM_THRES_8822C 0x3f +#define BIT_PAD_NUM_THRES_8822C(x) \ + (((x) & BIT_MASK_PAD_NUM_THRES_8822C) << BIT_SHIFT_PAD_NUM_THRES_8822C) +#define BITS_PAD_NUM_THRES_8822C \ + (BIT_MASK_PAD_NUM_THRES_8822C << BIT_SHIFT_PAD_NUM_THRES_8822C) +#define BIT_CLEAR_PAD_NUM_THRES_8822C(x) ((x) & (~BITS_PAD_NUM_THRES_8822C)) +#define BIT_GET_PAD_NUM_THRES_8822C(x) \ + (((x) >> BIT_SHIFT_PAD_NUM_THRES_8822C) & BIT_MASK_PAD_NUM_THRES_8822C) +#define BIT_SET_PAD_NUM_THRES_8822C(x, v) \ + (BIT_CLEAR_PAD_NUM_THRES_8822C(x) | BIT_PAD_NUM_THRES_8822C(v)) + +#define BIT_R_DMA_THIS_QUEUE_BK_8822C BIT(23) +#define BIT_R_DMA_THIS_QUEUE_BE_8822C BIT(22) +#define BIT_R_DMA_THIS_QUEUE_VI_8822C BIT(21) +#define BIT_R_DMA_THIS_QUEUE_VO_8822C BIT(20) + +#define BIT_SHIFT_R_TOTAL_LEN_TH_8822C 8 +#define BIT_MASK_R_TOTAL_LEN_TH_8822C 0xfff +#define BIT_R_TOTAL_LEN_TH_8822C(x) \ + (((x) & BIT_MASK_R_TOTAL_LEN_TH_8822C) \ + << BIT_SHIFT_R_TOTAL_LEN_TH_8822C) +#define BITS_R_TOTAL_LEN_TH_8822C \ + (BIT_MASK_R_TOTAL_LEN_TH_8822C << BIT_SHIFT_R_TOTAL_LEN_TH_8822C) +#define BIT_CLEAR_R_TOTAL_LEN_TH_8822C(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8822C)) +#define BIT_GET_R_TOTAL_LEN_TH_8822C(x) \ + (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822C) & \ + BIT_MASK_R_TOTAL_LEN_TH_8822C) +#define BIT_SET_R_TOTAL_LEN_TH_8822C(x, v) \ + (BIT_CLEAR_R_TOTAL_LEN_TH_8822C(x) | BIT_R_TOTAL_LEN_TH_8822C(v)) + +#define BIT_EN_NEW_EARLY_8822C BIT(7) +#define BIT_PRE_TX_CMD_8822C BIT(6) + +#define BIT_SHIFT_NUM_SCL_EN_8822C 4 +#define BIT_MASK_NUM_SCL_EN_8822C 0x3 +#define BIT_NUM_SCL_EN_8822C(x) \ + (((x) & BIT_MASK_NUM_SCL_EN_8822C) << BIT_SHIFT_NUM_SCL_EN_8822C) +#define BITS_NUM_SCL_EN_8822C \ + (BIT_MASK_NUM_SCL_EN_8822C << BIT_SHIFT_NUM_SCL_EN_8822C) +#define BIT_CLEAR_NUM_SCL_EN_8822C(x) ((x) & (~BITS_NUM_SCL_EN_8822C)) +#define BIT_GET_NUM_SCL_EN_8822C(x) \ + (((x) >> BIT_SHIFT_NUM_SCL_EN_8822C) & BIT_MASK_NUM_SCL_EN_8822C) +#define BIT_SET_NUM_SCL_EN_8822C(x, v) \ + (BIT_CLEAR_NUM_SCL_EN_8822C(x) | BIT_NUM_SCL_EN_8822C(v)) + +#define BIT_BK_EN_8822C BIT(3) +#define BIT_BE_EN_8822C BIT(2) +#define BIT_VI_EN_8822C BIT(1) +#define BIT_VO_EN_8822C BIT(0) + +/* 2 REG_PKT_LIFE_TIME_8822C */ + +#define BIT_SHIFT_PKT_LIFTIME_BEBK_8822C 16 +#define BIT_MASK_PKT_LIFTIME_BEBK_8822C 0xffff +#define BIT_PKT_LIFTIME_BEBK_8822C(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822C) \ + << BIT_SHIFT_PKT_LIFTIME_BEBK_8822C) +#define BITS_PKT_LIFTIME_BEBK_8822C \ + (BIT_MASK_PKT_LIFTIME_BEBK_8822C << BIT_SHIFT_PKT_LIFTIME_BEBK_8822C) +#define BIT_CLEAR_PKT_LIFTIME_BEBK_8822C(x) \ + ((x) & (~BITS_PKT_LIFTIME_BEBK_8822C)) +#define BIT_GET_PKT_LIFTIME_BEBK_8822C(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822C) & \ + BIT_MASK_PKT_LIFTIME_BEBK_8822C) +#define BIT_SET_PKT_LIFTIME_BEBK_8822C(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_BEBK_8822C(x) | BIT_PKT_LIFTIME_BEBK_8822C(v)) + +#define BIT_SHIFT_PKT_LIFTIME_VOVI_8822C 0 +#define BIT_MASK_PKT_LIFTIME_VOVI_8822C 0xffff +#define BIT_PKT_LIFTIME_VOVI_8822C(x) \ + (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822C) \ + << BIT_SHIFT_PKT_LIFTIME_VOVI_8822C) +#define BITS_PKT_LIFTIME_VOVI_8822C \ + (BIT_MASK_PKT_LIFTIME_VOVI_8822C << BIT_SHIFT_PKT_LIFTIME_VOVI_8822C) +#define BIT_CLEAR_PKT_LIFTIME_VOVI_8822C(x) \ + ((x) & (~BITS_PKT_LIFTIME_VOVI_8822C)) +#define BIT_GET_PKT_LIFTIME_VOVI_8822C(x) \ + (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822C) & \ + BIT_MASK_PKT_LIFTIME_VOVI_8822C) +#define BIT_SET_PKT_LIFTIME_VOVI_8822C(x, v) \ + (BIT_CLEAR_PKT_LIFTIME_VOVI_8822C(x) | BIT_PKT_LIFTIME_VOVI_8822C(v)) + +/* 2 REG_STBC_SETTING_8822C */ + +#define BIT_SHIFT_CDEND_TXTIME_L_8822C 4 +#define BIT_MASK_CDEND_TXTIME_L_8822C 0xf +#define BIT_CDEND_TXTIME_L_8822C(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_L_8822C) \ + << BIT_SHIFT_CDEND_TXTIME_L_8822C) +#define BITS_CDEND_TXTIME_L_8822C \ + (BIT_MASK_CDEND_TXTIME_L_8822C << BIT_SHIFT_CDEND_TXTIME_L_8822C) +#define BIT_CLEAR_CDEND_TXTIME_L_8822C(x) ((x) & (~BITS_CDEND_TXTIME_L_8822C)) +#define BIT_GET_CDEND_TXTIME_L_8822C(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822C) & \ + BIT_MASK_CDEND_TXTIME_L_8822C) +#define BIT_SET_CDEND_TXTIME_L_8822C(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_L_8822C(x) | BIT_CDEND_TXTIME_L_8822C(v)) + +#define BIT_SHIFT_NESS_8822C 2 +#define BIT_MASK_NESS_8822C 0x3 +#define BIT_NESS_8822C(x) (((x) & BIT_MASK_NESS_8822C) << BIT_SHIFT_NESS_8822C) +#define BITS_NESS_8822C (BIT_MASK_NESS_8822C << BIT_SHIFT_NESS_8822C) +#define BIT_CLEAR_NESS_8822C(x) ((x) & (~BITS_NESS_8822C)) +#define BIT_GET_NESS_8822C(x) \ + (((x) >> BIT_SHIFT_NESS_8822C) & BIT_MASK_NESS_8822C) +#define BIT_SET_NESS_8822C(x, v) (BIT_CLEAR_NESS_8822C(x) | BIT_NESS_8822C(v)) + +#define BIT_SHIFT_STBC_CFEND_8822C 0 +#define BIT_MASK_STBC_CFEND_8822C 0x3 +#define BIT_STBC_CFEND_8822C(x) \ + (((x) & BIT_MASK_STBC_CFEND_8822C) << BIT_SHIFT_STBC_CFEND_8822C) +#define BITS_STBC_CFEND_8822C \ + (BIT_MASK_STBC_CFEND_8822C << BIT_SHIFT_STBC_CFEND_8822C) +#define BIT_CLEAR_STBC_CFEND_8822C(x) ((x) & (~BITS_STBC_CFEND_8822C)) +#define BIT_GET_STBC_CFEND_8822C(x) \ + (((x) >> BIT_SHIFT_STBC_CFEND_8822C) & BIT_MASK_STBC_CFEND_8822C) +#define BIT_SET_STBC_CFEND_8822C(x, v) \ + (BIT_CLEAR_STBC_CFEND_8822C(x) | BIT_STBC_CFEND_8822C(v)) + +/* 2 REG_STBC_SETTING2_8822C */ + +#define BIT_SHIFT_CDEND_TXTIME_H_8822C 0 +#define BIT_MASK_CDEND_TXTIME_H_8822C 0x1f +#define BIT_CDEND_TXTIME_H_8822C(x) \ + (((x) & BIT_MASK_CDEND_TXTIME_H_8822C) \ + << BIT_SHIFT_CDEND_TXTIME_H_8822C) +#define BITS_CDEND_TXTIME_H_8822C \ + (BIT_MASK_CDEND_TXTIME_H_8822C << BIT_SHIFT_CDEND_TXTIME_H_8822C) +#define BIT_CLEAR_CDEND_TXTIME_H_8822C(x) ((x) & (~BITS_CDEND_TXTIME_H_8822C)) +#define BIT_GET_CDEND_TXTIME_H_8822C(x) \ + (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822C) & \ + BIT_MASK_CDEND_TXTIME_H_8822C) +#define BIT_SET_CDEND_TXTIME_H_8822C(x, v) \ + (BIT_CLEAR_CDEND_TXTIME_H_8822C(x) | BIT_CDEND_TXTIME_H_8822C(v)) + +/* 2 REG_QUEUE_CTRL_8822C */ +#define BIT_FORCE_RND_PRI_8822C BIT(6) +#define BIT_PTA_EDCCA_EN_8822C BIT(5) +#define BIT_PTA_WL_TX_EN_8822C BIT(4) +#define BIT_R_USE_DATA_BW_8822C BIT(3) +#define BIT_TRI_PKT_INT_MODE1_8822C BIT(2) +#define BIT_TRI_PKT_INT_MODE0_8822C BIT(1) +#define BIT_ACQ_MODE_SEL_8822C BIT(0) + +/* 2 REG_SINGLE_AMPDU_CTRL_8822C */ +#define BIT_EN_SINGLE_APMDU_8822C BIT(7) + +#define BIT_SHIFT_SNDTX_MAXTIME_8822C 0 +#define BIT_MASK_SNDTX_MAXTIME_8822C 0x7f +#define BIT_SNDTX_MAXTIME_8822C(x) \ + (((x) & BIT_MASK_SNDTX_MAXTIME_8822C) << BIT_SHIFT_SNDTX_MAXTIME_8822C) +#define BITS_SNDTX_MAXTIME_8822C \ + (BIT_MASK_SNDTX_MAXTIME_8822C << BIT_SHIFT_SNDTX_MAXTIME_8822C) +#define BIT_CLEAR_SNDTX_MAXTIME_8822C(x) ((x) & (~BITS_SNDTX_MAXTIME_8822C)) +#define BIT_GET_SNDTX_MAXTIME_8822C(x) \ + (((x) >> BIT_SHIFT_SNDTX_MAXTIME_8822C) & BIT_MASK_SNDTX_MAXTIME_8822C) +#define BIT_SET_SNDTX_MAXTIME_8822C(x, v) \ + (BIT_CLEAR_SNDTX_MAXTIME_8822C(x) | BIT_SNDTX_MAXTIME_8822C(v)) + +/* 2 REG_PROT_MODE_CTRL_8822C */ +#define BIT_SND_SIFS_TXDATA_8822C BIT(31) +#define BIT_TX_SND_MATCH_MACID_8822C BIT(30) + +#define BIT_SHIFT_RTS_MAX_AGG_NUM_8822C 24 +#define BIT_MASK_RTS_MAX_AGG_NUM_8822C 0x3f +#define BIT_RTS_MAX_AGG_NUM_8822C(x) \ + (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822C) \ + << BIT_SHIFT_RTS_MAX_AGG_NUM_8822C) +#define BITS_RTS_MAX_AGG_NUM_8822C \ + (BIT_MASK_RTS_MAX_AGG_NUM_8822C << BIT_SHIFT_RTS_MAX_AGG_NUM_8822C) +#define BIT_CLEAR_RTS_MAX_AGG_NUM_8822C(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8822C)) +#define BIT_GET_RTS_MAX_AGG_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822C) & \ + BIT_MASK_RTS_MAX_AGG_NUM_8822C) +#define BIT_SET_RTS_MAX_AGG_NUM_8822C(x, v) \ + (BIT_CLEAR_RTS_MAX_AGG_NUM_8822C(x) | BIT_RTS_MAX_AGG_NUM_8822C(v)) + +#define BIT_SHIFT_MAX_AGG_NUM_8822C 16 +#define BIT_MASK_MAX_AGG_NUM_8822C 0x3f +#define BIT_MAX_AGG_NUM_8822C(x) \ + (((x) & BIT_MASK_MAX_AGG_NUM_8822C) << BIT_SHIFT_MAX_AGG_NUM_8822C) +#define BITS_MAX_AGG_NUM_8822C \ + (BIT_MASK_MAX_AGG_NUM_8822C << BIT_SHIFT_MAX_AGG_NUM_8822C) +#define BIT_CLEAR_MAX_AGG_NUM_8822C(x) ((x) & (~BITS_MAX_AGG_NUM_8822C)) +#define BIT_GET_MAX_AGG_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_AGG_NUM_8822C) & BIT_MASK_MAX_AGG_NUM_8822C) +#define BIT_SET_MAX_AGG_NUM_8822C(x, v) \ + (BIT_CLEAR_MAX_AGG_NUM_8822C(x) | BIT_MAX_AGG_NUM_8822C(v)) + +#define BIT_SHIFT_RTS_TXTIME_TH_8822C 8 +#define BIT_MASK_RTS_TXTIME_TH_8822C 0xff +#define BIT_RTS_TXTIME_TH_8822C(x) \ + (((x) & BIT_MASK_RTS_TXTIME_TH_8822C) << BIT_SHIFT_RTS_TXTIME_TH_8822C) +#define BITS_RTS_TXTIME_TH_8822C \ + (BIT_MASK_RTS_TXTIME_TH_8822C << BIT_SHIFT_RTS_TXTIME_TH_8822C) +#define BIT_CLEAR_RTS_TXTIME_TH_8822C(x) ((x) & (~BITS_RTS_TXTIME_TH_8822C)) +#define BIT_GET_RTS_TXTIME_TH_8822C(x) \ + (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822C) & BIT_MASK_RTS_TXTIME_TH_8822C) +#define BIT_SET_RTS_TXTIME_TH_8822C(x, v) \ + (BIT_CLEAR_RTS_TXTIME_TH_8822C(x) | BIT_RTS_TXTIME_TH_8822C(v)) + +#define BIT_SHIFT_RTS_LEN_TH_8822C 0 +#define BIT_MASK_RTS_LEN_TH_8822C 0xff +#define BIT_RTS_LEN_TH_8822C(x) \ + (((x) & BIT_MASK_RTS_LEN_TH_8822C) << BIT_SHIFT_RTS_LEN_TH_8822C) +#define BITS_RTS_LEN_TH_8822C \ + (BIT_MASK_RTS_LEN_TH_8822C << BIT_SHIFT_RTS_LEN_TH_8822C) +#define BIT_CLEAR_RTS_LEN_TH_8822C(x) ((x) & (~BITS_RTS_LEN_TH_8822C)) +#define BIT_GET_RTS_LEN_TH_8822C(x) \ + (((x) >> BIT_SHIFT_RTS_LEN_TH_8822C) & BIT_MASK_RTS_LEN_TH_8822C) +#define BIT_SET_RTS_LEN_TH_8822C(x, v) \ + (BIT_CLEAR_RTS_LEN_TH_8822C(x) | BIT_RTS_LEN_TH_8822C(v)) + +/* 2 REG_BAR_MODE_CTRL_8822C */ + +#define BIT_SHIFT_BAR_RTY_LMT_8822C 16 +#define BIT_MASK_BAR_RTY_LMT_8822C 0x3 +#define BIT_BAR_RTY_LMT_8822C(x) \ + (((x) & BIT_MASK_BAR_RTY_LMT_8822C) << BIT_SHIFT_BAR_RTY_LMT_8822C) +#define BITS_BAR_RTY_LMT_8822C \ + (BIT_MASK_BAR_RTY_LMT_8822C << BIT_SHIFT_BAR_RTY_LMT_8822C) +#define BIT_CLEAR_BAR_RTY_LMT_8822C(x) ((x) & (~BITS_BAR_RTY_LMT_8822C)) +#define BIT_GET_BAR_RTY_LMT_8822C(x) \ + (((x) >> BIT_SHIFT_BAR_RTY_LMT_8822C) & BIT_MASK_BAR_RTY_LMT_8822C) +#define BIT_SET_BAR_RTY_LMT_8822C(x, v) \ + (BIT_CLEAR_BAR_RTY_LMT_8822C(x) | BIT_BAR_RTY_LMT_8822C(v)) + +#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C 8 +#define BIT_MASK_BAR_PKT_TXTIME_TH_8822C 0xff +#define BIT_BAR_PKT_TXTIME_TH_8822C(x) \ + (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822C) \ + << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C) +#define BITS_BAR_PKT_TXTIME_TH_8822C \ + (BIT_MASK_BAR_PKT_TXTIME_TH_8822C << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C) +#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8822C(x) \ + ((x) & (~BITS_BAR_PKT_TXTIME_TH_8822C)) +#define BIT_GET_BAR_PKT_TXTIME_TH_8822C(x) \ + (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C) & \ + BIT_MASK_BAR_PKT_TXTIME_TH_8822C) +#define BIT_SET_BAR_PKT_TXTIME_TH_8822C(x, v) \ + (BIT_CLEAR_BAR_PKT_TXTIME_TH_8822C(x) | BIT_BAR_PKT_TXTIME_TH_8822C(v)) + +#define BIT_BAR_EN_V1_8822C BIT(6) + +#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C 0 +#define BIT_MASK_BAR_PKTNUM_TH_V1_8822C 0x3f +#define BIT_BAR_PKTNUM_TH_V1_8822C(x) \ + (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822C) \ + << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C) +#define BITS_BAR_PKTNUM_TH_V1_8822C \ + (BIT_MASK_BAR_PKTNUM_TH_V1_8822C << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C) +#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8822C(x) \ + ((x) & (~BITS_BAR_PKTNUM_TH_V1_8822C)) +#define BIT_GET_BAR_PKTNUM_TH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C) & \ + BIT_MASK_BAR_PKTNUM_TH_V1_8822C) +#define BIT_SET_BAR_PKTNUM_TH_V1_8822C(x, v) \ + (BIT_CLEAR_BAR_PKTNUM_TH_V1_8822C(x) | BIT_BAR_PKTNUM_TH_V1_8822C(v)) + +/* 2 REG_RA_TRY_RATE_AGG_LMT_8822C */ + +#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C 0 +#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C 0x3f +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822C(x) \ + (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C) \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C) +#define BITS_RA_TRY_RATE_AGG_LMT_V1_8822C \ + (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C \ + << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C) +#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822C(x) \ + ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8822C)) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C) & \ + BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C) +#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8822C(x, v) \ + (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822C(x) | \ + BIT_RA_TRY_RATE_AGG_LMT_V1_8822C(v)) + +/* 2 REG_MACID_SLEEP2_8822C */ + +#define BIT_SHIFT_MACID95_64PKTSLEEP_8822C 0 +#define BIT_MASK_MACID95_64PKTSLEEP_8822C 0xffffffffL +#define BIT_MACID95_64PKTSLEEP_8822C(x) \ + (((x) & BIT_MASK_MACID95_64PKTSLEEP_8822C) \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8822C) +#define BITS_MACID95_64PKTSLEEP_8822C \ + (BIT_MASK_MACID95_64PKTSLEEP_8822C \ + << BIT_SHIFT_MACID95_64PKTSLEEP_8822C) +#define BIT_CLEAR_MACID95_64PKTSLEEP_8822C(x) \ + ((x) & (~BITS_MACID95_64PKTSLEEP_8822C)) +#define BIT_GET_MACID95_64PKTSLEEP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822C) & \ + BIT_MASK_MACID95_64PKTSLEEP_8822C) +#define BIT_SET_MACID95_64PKTSLEEP_8822C(x, v) \ + (BIT_CLEAR_MACID95_64PKTSLEEP_8822C(x) | \ + BIT_MACID95_64PKTSLEEP_8822C(v)) + +/* 2 REG_MACID_SLEEP_8822C */ + +#define BIT_SHIFT_MACID31_0_PKTSLEEP_8822C 0 +#define BIT_MASK_MACID31_0_PKTSLEEP_8822C 0xffffffffL +#define BIT_MACID31_0_PKTSLEEP_8822C(x) \ + (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822C) \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8822C) +#define BITS_MACID31_0_PKTSLEEP_8822C \ + (BIT_MASK_MACID31_0_PKTSLEEP_8822C \ + << BIT_SHIFT_MACID31_0_PKTSLEEP_8822C) +#define BIT_CLEAR_MACID31_0_PKTSLEEP_8822C(x) \ + ((x) & (~BITS_MACID31_0_PKTSLEEP_8822C)) +#define BIT_GET_MACID31_0_PKTSLEEP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822C) & \ + BIT_MASK_MACID31_0_PKTSLEEP_8822C) +#define BIT_SET_MACID31_0_PKTSLEEP_8822C(x, v) \ + (BIT_CLEAR_MACID31_0_PKTSLEEP_8822C(x) | \ + BIT_MACID31_0_PKTSLEEP_8822C(v)) + +/* 2 REG_HW_SEQ0_8822C */ + +#define BIT_SHIFT_HW_SSN_SEQ0_8822C 0 +#define BIT_MASK_HW_SSN_SEQ0_8822C 0xfff +#define BIT_HW_SSN_SEQ0_8822C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ0_8822C) << BIT_SHIFT_HW_SSN_SEQ0_8822C) +#define BITS_HW_SSN_SEQ0_8822C \ + (BIT_MASK_HW_SSN_SEQ0_8822C << BIT_SHIFT_HW_SSN_SEQ0_8822C) +#define BIT_CLEAR_HW_SSN_SEQ0_8822C(x) ((x) & (~BITS_HW_SSN_SEQ0_8822C)) +#define BIT_GET_HW_SSN_SEQ0_8822C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822C) & BIT_MASK_HW_SSN_SEQ0_8822C) +#define BIT_SET_HW_SSN_SEQ0_8822C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ0_8822C(x) | BIT_HW_SSN_SEQ0_8822C(v)) + +/* 2 REG_HW_SEQ1_8822C */ + +#define BIT_SHIFT_HW_SSN_SEQ1_8822C 0 +#define BIT_MASK_HW_SSN_SEQ1_8822C 0xfff +#define BIT_HW_SSN_SEQ1_8822C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ1_8822C) << BIT_SHIFT_HW_SSN_SEQ1_8822C) +#define BITS_HW_SSN_SEQ1_8822C \ + (BIT_MASK_HW_SSN_SEQ1_8822C << BIT_SHIFT_HW_SSN_SEQ1_8822C) +#define BIT_CLEAR_HW_SSN_SEQ1_8822C(x) ((x) & (~BITS_HW_SSN_SEQ1_8822C)) +#define BIT_GET_HW_SSN_SEQ1_8822C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822C) & BIT_MASK_HW_SSN_SEQ1_8822C) +#define BIT_SET_HW_SSN_SEQ1_8822C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ1_8822C(x) | BIT_HW_SSN_SEQ1_8822C(v)) + +/* 2 REG_HW_SEQ2_8822C */ + +#define BIT_SHIFT_HW_SSN_SEQ2_8822C 0 +#define BIT_MASK_HW_SSN_SEQ2_8822C 0xfff +#define BIT_HW_SSN_SEQ2_8822C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ2_8822C) << BIT_SHIFT_HW_SSN_SEQ2_8822C) +#define BITS_HW_SSN_SEQ2_8822C \ + (BIT_MASK_HW_SSN_SEQ2_8822C << BIT_SHIFT_HW_SSN_SEQ2_8822C) +#define BIT_CLEAR_HW_SSN_SEQ2_8822C(x) ((x) & (~BITS_HW_SSN_SEQ2_8822C)) +#define BIT_GET_HW_SSN_SEQ2_8822C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822C) & BIT_MASK_HW_SSN_SEQ2_8822C) +#define BIT_SET_HW_SSN_SEQ2_8822C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ2_8822C(x) | BIT_HW_SSN_SEQ2_8822C(v)) + +/* 2 REG_HW_SEQ3_8822C */ + +#define BIT_SHIFT_CSI_HWSEQ_SEL_8822C 12 +#define BIT_MASK_CSI_HWSEQ_SEL_8822C 0x3 +#define BIT_CSI_HWSEQ_SEL_8822C(x) \ + (((x) & BIT_MASK_CSI_HWSEQ_SEL_8822C) << BIT_SHIFT_CSI_HWSEQ_SEL_8822C) +#define BITS_CSI_HWSEQ_SEL_8822C \ + (BIT_MASK_CSI_HWSEQ_SEL_8822C << BIT_SHIFT_CSI_HWSEQ_SEL_8822C) +#define BIT_CLEAR_CSI_HWSEQ_SEL_8822C(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8822C)) +#define BIT_GET_CSI_HWSEQ_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8822C) & BIT_MASK_CSI_HWSEQ_SEL_8822C) +#define BIT_SET_CSI_HWSEQ_SEL_8822C(x, v) \ + (BIT_CLEAR_CSI_HWSEQ_SEL_8822C(x) | BIT_CSI_HWSEQ_SEL_8822C(v)) + +#define BIT_SHIFT_HW_SSN_SEQ3_8822C 0 +#define BIT_MASK_HW_SSN_SEQ3_8822C 0xfff +#define BIT_HW_SSN_SEQ3_8822C(x) \ + (((x) & BIT_MASK_HW_SSN_SEQ3_8822C) << BIT_SHIFT_HW_SSN_SEQ3_8822C) +#define BITS_HW_SSN_SEQ3_8822C \ + (BIT_MASK_HW_SSN_SEQ3_8822C << BIT_SHIFT_HW_SSN_SEQ3_8822C) +#define BIT_CLEAR_HW_SSN_SEQ3_8822C(x) ((x) & (~BITS_HW_SSN_SEQ3_8822C)) +#define BIT_GET_HW_SSN_SEQ3_8822C(x) \ + (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822C) & BIT_MASK_HW_SSN_SEQ3_8822C) +#define BIT_SET_HW_SSN_SEQ3_8822C(x, v) \ + (BIT_CLEAR_HW_SSN_SEQ3_8822C(x) | BIT_HW_SSN_SEQ3_8822C(v)) + +/* 2 REG_NULL_PKT_STATUS_V1_8822C */ + +#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C 2 +#define BIT_MASK_PTCL_TOTAL_PG_V2_8822C 0x3fff +#define BIT_PTCL_TOTAL_PG_V2_8822C(x) \ + (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822C) \ + << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C) +#define BITS_PTCL_TOTAL_PG_V2_8822C \ + (BIT_MASK_PTCL_TOTAL_PG_V2_8822C << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C) +#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8822C(x) \ + ((x) & (~BITS_PTCL_TOTAL_PG_V2_8822C)) +#define BIT_GET_PTCL_TOTAL_PG_V2_8822C(x) \ + (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C) & \ + BIT_MASK_PTCL_TOTAL_PG_V2_8822C) +#define BIT_SET_PTCL_TOTAL_PG_V2_8822C(x, v) \ + (BIT_CLEAR_PTCL_TOTAL_PG_V2_8822C(x) | BIT_PTCL_TOTAL_PG_V2_8822C(v)) + +#define BIT_TX_NULL_1_8822C BIT(1) +#define BIT_TX_NULL_0_8822C BIT(0) + +/* 2 REG_PTCL_ERR_STATUS_8822C */ +#define BIT_PTCL_RATE_TABLE_INVALID_8822C BIT(7) +#define BIT_FTM_T2R_ERROR_8822C BIT(6) +#define BIT_PTCL_ERR0_8822C BIT(5) +#define BIT_PTCL_ERR1_8822C BIT(4) +#define BIT_PTCL_ERR2_8822C BIT(3) +#define BIT_PTCL_ERR3_8822C BIT(2) +#define BIT_PTCL_ERR4_8822C BIT(1) +#define BIT_PTCL_ERR5_8822C BIT(0) + +/* 2 REG_NULL_PKT_STATUS_EXTEND_8822C */ +#define BIT_CLI3_TX_NULL_1_8822C BIT(7) +#define BIT_CLI3_TX_NULL_0_8822C BIT(6) +#define BIT_CLI2_TX_NULL_1_8822C BIT(5) +#define BIT_CLI2_TX_NULL_0_8822C BIT(4) +#define BIT_CLI1_TX_NULL_1_8822C BIT(3) +#define BIT_CLI1_TX_NULL_0_8822C BIT(2) +#define BIT_CLI0_TX_NULL_1_8822C BIT(1) +#define BIT_CLI0_TX_NULL_0_8822C BIT(0) + +/* 2 REG_HQMGQ_DROP_8822C */ +#define BIT_HIQ_DROP_8822C BIT(7) +#define BIT_MGQ_DROP_8822C BIT(6) +#define BIT_CLR_HGQ_REQ_BLOCK_8822C BIT(5) + +/* 2 REG_PRECNT_CTRL_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_EN_PRECNT_8822C BIT(11) + +#define BIT_SHIFT_PRECNT_TH_8822C 0 +#define BIT_MASK_PRECNT_TH_8822C 0x7ff +#define BIT_PRECNT_TH_8822C(x) \ + (((x) & BIT_MASK_PRECNT_TH_8822C) << BIT_SHIFT_PRECNT_TH_8822C) +#define BITS_PRECNT_TH_8822C \ + (BIT_MASK_PRECNT_TH_8822C << BIT_SHIFT_PRECNT_TH_8822C) +#define BIT_CLEAR_PRECNT_TH_8822C(x) ((x) & (~BITS_PRECNT_TH_8822C)) +#define BIT_GET_PRECNT_TH_8822C(x) \ + (((x) >> BIT_SHIFT_PRECNT_TH_8822C) & BIT_MASK_PRECNT_TH_8822C) +#define BIT_SET_PRECNT_TH_8822C(x, v) \ + (BIT_CLEAR_PRECNT_TH_8822C(x) | BIT_PRECNT_TH_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_BT_POLLUTE_PKT_CNT_8822C */ + +#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C 0 +#define BIT_MASK_BT_POLLUTE_PKT_CNT_8822C 0xffff +#define BIT_BT_POLLUTE_PKT_CNT_8822C(x) \ + (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822C) \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C) +#define BITS_BT_POLLUTE_PKT_CNT_8822C \ + (BIT_MASK_BT_POLLUTE_PKT_CNT_8822C \ + << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C) +#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822C(x) \ + ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8822C)) +#define BIT_GET_BT_POLLUTE_PKT_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C) & \ + BIT_MASK_BT_POLLUTE_PKT_CNT_8822C) +#define BIT_SET_BT_POLLUTE_PKT_CNT_8822C(x, v) \ + (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822C(x) | \ + BIT_BT_POLLUTE_PKT_CNT_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_PTCL_DBG_8822C */ + +#define BIT_SHIFT_PTCL_DBG_8822C 0 +#define BIT_MASK_PTCL_DBG_8822C 0xffffffffL +#define BIT_PTCL_DBG_8822C(x) \ + (((x) & BIT_MASK_PTCL_DBG_8822C) << BIT_SHIFT_PTCL_DBG_8822C) +#define BITS_PTCL_DBG_8822C \ + (BIT_MASK_PTCL_DBG_8822C << BIT_SHIFT_PTCL_DBG_8822C) +#define BIT_CLEAR_PTCL_DBG_8822C(x) ((x) & (~BITS_PTCL_DBG_8822C)) +#define BIT_GET_PTCL_DBG_8822C(x) \ + (((x) >> BIT_SHIFT_PTCL_DBG_8822C) & BIT_MASK_PTCL_DBG_8822C) +#define BIT_SET_PTCL_DBG_8822C(x, v) \ + (BIT_CLEAR_PTCL_DBG_8822C(x) | BIT_PTCL_DBG_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_CPUMGQ_TIMER_CTRL2_8822C */ + +#define BIT_SHIFT_TRI_HEAD_ADDR_8822C 16 +#define BIT_MASK_TRI_HEAD_ADDR_8822C 0xfff +#define BIT_TRI_HEAD_ADDR_8822C(x) \ + (((x) & BIT_MASK_TRI_HEAD_ADDR_8822C) << BIT_SHIFT_TRI_HEAD_ADDR_8822C) +#define BITS_TRI_HEAD_ADDR_8822C \ + (BIT_MASK_TRI_HEAD_ADDR_8822C << BIT_SHIFT_TRI_HEAD_ADDR_8822C) +#define BIT_CLEAR_TRI_HEAD_ADDR_8822C(x) ((x) & (~BITS_TRI_HEAD_ADDR_8822C)) +#define BIT_GET_TRI_HEAD_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822C) & BIT_MASK_TRI_HEAD_ADDR_8822C) +#define BIT_SET_TRI_HEAD_ADDR_8822C(x, v) \ + (BIT_CLEAR_TRI_HEAD_ADDR_8822C(x) | BIT_TRI_HEAD_ADDR_8822C(v)) + +#define BIT_DROP_TH_EN_8822C BIT(8) + +#define BIT_SHIFT_DROP_TH_8822C 0 +#define BIT_MASK_DROP_TH_8822C 0xff +#define BIT_DROP_TH_8822C(x) \ + (((x) & BIT_MASK_DROP_TH_8822C) << BIT_SHIFT_DROP_TH_8822C) +#define BITS_DROP_TH_8822C (BIT_MASK_DROP_TH_8822C << BIT_SHIFT_DROP_TH_8822C) +#define BIT_CLEAR_DROP_TH_8822C(x) ((x) & (~BITS_DROP_TH_8822C)) +#define BIT_GET_DROP_TH_8822C(x) \ + (((x) >> BIT_SHIFT_DROP_TH_8822C) & BIT_MASK_DROP_TH_8822C) +#define BIT_SET_DROP_TH_8822C(x, v) \ + (BIT_CLEAR_DROP_TH_8822C(x) | BIT_DROP_TH_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_DUMMY_PAGE4_V1_8822C */ + +/* 2 REG_MOREDATA_8822C */ +#define BIT_MOREDATA_CTRL2_EN_V1_8822C BIT(3) +#define BIT_MOREDATA_CTRL1_EN_V1_8822C BIT(2) +#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8822C BIT(0) + +/* 2 REG_Q0_Q1_INFO_8822C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8822C 28 +#define BIT_MASK_GTAB_ID_8822C 0x7 +#define BIT_GTAB_ID_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C) +#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C) +#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C)) +#define BIT_GET_GTAB_ID_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C) +#define BIT_SET_GTAB_ID_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v)) + +#define BIT_SHIFT_AC1_PKT_INFO_8822C 16 +#define BIT_MASK_AC1_PKT_INFO_8822C 0xfff +#define BIT_AC1_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC1_PKT_INFO_8822C) << BIT_SHIFT_AC1_PKT_INFO_8822C) +#define BITS_AC1_PKT_INFO_8822C \ + (BIT_MASK_AC1_PKT_INFO_8822C << BIT_SHIFT_AC1_PKT_INFO_8822C) +#define BIT_CLEAR_AC1_PKT_INFO_8822C(x) ((x) & (~BITS_AC1_PKT_INFO_8822C)) +#define BIT_GET_AC1_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC1_PKT_INFO_8822C) & BIT_MASK_AC1_PKT_INFO_8822C) +#define BIT_SET_AC1_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC1_PKT_INFO_8822C(x) | BIT_AC1_PKT_INFO_8822C(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8822C 12 +#define BIT_MASK_GTAB_ID_V1_8822C 0x7 +#define BIT_GTAB_ID_V1_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BITS_GTAB_ID_V1_8822C \ + (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C)) +#define BIT_GET_GTAB_ID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C) +#define BIT_SET_GTAB_ID_V1_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v)) + +#define BIT_SHIFT_AC0_PKT_INFO_8822C 0 +#define BIT_MASK_AC0_PKT_INFO_8822C 0xfff +#define BIT_AC0_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC0_PKT_INFO_8822C) << BIT_SHIFT_AC0_PKT_INFO_8822C) +#define BITS_AC0_PKT_INFO_8822C \ + (BIT_MASK_AC0_PKT_INFO_8822C << BIT_SHIFT_AC0_PKT_INFO_8822C) +#define BIT_CLEAR_AC0_PKT_INFO_8822C(x) ((x) & (~BITS_AC0_PKT_INFO_8822C)) +#define BIT_GET_AC0_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC0_PKT_INFO_8822C) & BIT_MASK_AC0_PKT_INFO_8822C) +#define BIT_SET_AC0_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC0_PKT_INFO_8822C(x) | BIT_AC0_PKT_INFO_8822C(v)) + +/* 2 REG_Q2_Q3_INFO_8822C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8822C 28 +#define BIT_MASK_GTAB_ID_8822C 0x7 +#define BIT_GTAB_ID_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C) +#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C) +#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C)) +#define BIT_GET_GTAB_ID_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C) +#define BIT_SET_GTAB_ID_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v)) + +#define BIT_SHIFT_AC3_PKT_INFO_8822C 16 +#define BIT_MASK_AC3_PKT_INFO_8822C 0xfff +#define BIT_AC3_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC3_PKT_INFO_8822C) << BIT_SHIFT_AC3_PKT_INFO_8822C) +#define BITS_AC3_PKT_INFO_8822C \ + (BIT_MASK_AC3_PKT_INFO_8822C << BIT_SHIFT_AC3_PKT_INFO_8822C) +#define BIT_CLEAR_AC3_PKT_INFO_8822C(x) ((x) & (~BITS_AC3_PKT_INFO_8822C)) +#define BIT_GET_AC3_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC3_PKT_INFO_8822C) & BIT_MASK_AC3_PKT_INFO_8822C) +#define BIT_SET_AC3_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC3_PKT_INFO_8822C(x) | BIT_AC3_PKT_INFO_8822C(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8822C 12 +#define BIT_MASK_GTAB_ID_V1_8822C 0x7 +#define BIT_GTAB_ID_V1_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BITS_GTAB_ID_V1_8822C \ + (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C)) +#define BIT_GET_GTAB_ID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C) +#define BIT_SET_GTAB_ID_V1_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v)) + +#define BIT_SHIFT_AC2_PKT_INFO_8822C 0 +#define BIT_MASK_AC2_PKT_INFO_8822C 0xfff +#define BIT_AC2_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC2_PKT_INFO_8822C) << BIT_SHIFT_AC2_PKT_INFO_8822C) +#define BITS_AC2_PKT_INFO_8822C \ + (BIT_MASK_AC2_PKT_INFO_8822C << BIT_SHIFT_AC2_PKT_INFO_8822C) +#define BIT_CLEAR_AC2_PKT_INFO_8822C(x) ((x) & (~BITS_AC2_PKT_INFO_8822C)) +#define BIT_GET_AC2_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC2_PKT_INFO_8822C) & BIT_MASK_AC2_PKT_INFO_8822C) +#define BIT_SET_AC2_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC2_PKT_INFO_8822C(x) | BIT_AC2_PKT_INFO_8822C(v)) + +/* 2 REG_Q4_Q5_INFO_8822C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8822C 28 +#define BIT_MASK_GTAB_ID_8822C 0x7 +#define BIT_GTAB_ID_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C) +#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C) +#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C)) +#define BIT_GET_GTAB_ID_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C) +#define BIT_SET_GTAB_ID_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v)) + +#define BIT_SHIFT_AC5_PKT_INFO_8822C 16 +#define BIT_MASK_AC5_PKT_INFO_8822C 0xfff +#define BIT_AC5_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC5_PKT_INFO_8822C) << BIT_SHIFT_AC5_PKT_INFO_8822C) +#define BITS_AC5_PKT_INFO_8822C \ + (BIT_MASK_AC5_PKT_INFO_8822C << BIT_SHIFT_AC5_PKT_INFO_8822C) +#define BIT_CLEAR_AC5_PKT_INFO_8822C(x) ((x) & (~BITS_AC5_PKT_INFO_8822C)) +#define BIT_GET_AC5_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC5_PKT_INFO_8822C) & BIT_MASK_AC5_PKT_INFO_8822C) +#define BIT_SET_AC5_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC5_PKT_INFO_8822C(x) | BIT_AC5_PKT_INFO_8822C(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8822C 12 +#define BIT_MASK_GTAB_ID_V1_8822C 0x7 +#define BIT_GTAB_ID_V1_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BITS_GTAB_ID_V1_8822C \ + (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C)) +#define BIT_GET_GTAB_ID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C) +#define BIT_SET_GTAB_ID_V1_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v)) + +#define BIT_SHIFT_AC4_PKT_INFO_8822C 0 +#define BIT_MASK_AC4_PKT_INFO_8822C 0xfff +#define BIT_AC4_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC4_PKT_INFO_8822C) << BIT_SHIFT_AC4_PKT_INFO_8822C) +#define BITS_AC4_PKT_INFO_8822C \ + (BIT_MASK_AC4_PKT_INFO_8822C << BIT_SHIFT_AC4_PKT_INFO_8822C) +#define BIT_CLEAR_AC4_PKT_INFO_8822C(x) ((x) & (~BITS_AC4_PKT_INFO_8822C)) +#define BIT_GET_AC4_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC4_PKT_INFO_8822C) & BIT_MASK_AC4_PKT_INFO_8822C) +#define BIT_SET_AC4_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC4_PKT_INFO_8822C(x) | BIT_AC4_PKT_INFO_8822C(v)) + +/* 2 REG_Q6_Q7_INFO_8822C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8822C 28 +#define BIT_MASK_GTAB_ID_8822C 0x7 +#define BIT_GTAB_ID_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C) +#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C) +#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C)) +#define BIT_GET_GTAB_ID_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C) +#define BIT_SET_GTAB_ID_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v)) + +#define BIT_SHIFT_AC7_PKT_INFO_8822C 16 +#define BIT_MASK_AC7_PKT_INFO_8822C 0xfff +#define BIT_AC7_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC7_PKT_INFO_8822C) << BIT_SHIFT_AC7_PKT_INFO_8822C) +#define BITS_AC7_PKT_INFO_8822C \ + (BIT_MASK_AC7_PKT_INFO_8822C << BIT_SHIFT_AC7_PKT_INFO_8822C) +#define BIT_CLEAR_AC7_PKT_INFO_8822C(x) ((x) & (~BITS_AC7_PKT_INFO_8822C)) +#define BIT_GET_AC7_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC7_PKT_INFO_8822C) & BIT_MASK_AC7_PKT_INFO_8822C) +#define BIT_SET_AC7_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC7_PKT_INFO_8822C(x) | BIT_AC7_PKT_INFO_8822C(v)) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8822C 12 +#define BIT_MASK_GTAB_ID_V1_8822C 0x7 +#define BIT_GTAB_ID_V1_8822C(x) \ + (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BITS_GTAB_ID_V1_8822C \ + (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C) +#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C)) +#define BIT_GET_GTAB_ID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C) +#define BIT_SET_GTAB_ID_V1_8822C(x, v) \ + (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v)) + +#define BIT_SHIFT_AC6_PKT_INFO_8822C 0 +#define BIT_MASK_AC6_PKT_INFO_8822C 0xfff +#define BIT_AC6_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_AC6_PKT_INFO_8822C) << BIT_SHIFT_AC6_PKT_INFO_8822C) +#define BITS_AC6_PKT_INFO_8822C \ + (BIT_MASK_AC6_PKT_INFO_8822C << BIT_SHIFT_AC6_PKT_INFO_8822C) +#define BIT_CLEAR_AC6_PKT_INFO_8822C(x) ((x) & (~BITS_AC6_PKT_INFO_8822C)) +#define BIT_GET_AC6_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_AC6_PKT_INFO_8822C) & BIT_MASK_AC6_PKT_INFO_8822C) +#define BIT_SET_AC6_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_AC6_PKT_INFO_8822C(x) | BIT_AC6_PKT_INFO_8822C(v)) + +/* 2 REG_MGQ_HIQ_INFO_8822C */ + +#define BIT_SHIFT_HIQ_PKT_INFO_8822C 16 +#define BIT_MASK_HIQ_PKT_INFO_8822C 0xfff +#define BIT_HIQ_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_HIQ_PKT_INFO_8822C) << BIT_SHIFT_HIQ_PKT_INFO_8822C) +#define BITS_HIQ_PKT_INFO_8822C \ + (BIT_MASK_HIQ_PKT_INFO_8822C << BIT_SHIFT_HIQ_PKT_INFO_8822C) +#define BIT_CLEAR_HIQ_PKT_INFO_8822C(x) ((x) & (~BITS_HIQ_PKT_INFO_8822C)) +#define BIT_GET_HIQ_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822C) & BIT_MASK_HIQ_PKT_INFO_8822C) +#define BIT_SET_HIQ_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_HIQ_PKT_INFO_8822C(x) | BIT_HIQ_PKT_INFO_8822C(v)) + +#define BIT_SHIFT_MGQ_PKT_INFO_8822C 0 +#define BIT_MASK_MGQ_PKT_INFO_8822C 0xfff +#define BIT_MGQ_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_MGQ_PKT_INFO_8822C) << BIT_SHIFT_MGQ_PKT_INFO_8822C) +#define BITS_MGQ_PKT_INFO_8822C \ + (BIT_MASK_MGQ_PKT_INFO_8822C << BIT_SHIFT_MGQ_PKT_INFO_8822C) +#define BIT_CLEAR_MGQ_PKT_INFO_8822C(x) ((x) & (~BITS_MGQ_PKT_INFO_8822C)) +#define BIT_GET_MGQ_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822C) & BIT_MASK_MGQ_PKT_INFO_8822C) +#define BIT_SET_MGQ_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_MGQ_PKT_INFO_8822C(x) | BIT_MGQ_PKT_INFO_8822C(v)) + +/* 2 REG_CMDQ_BCNQ_INFO_8822C */ + +#define BIT_SHIFT_CMDQ_PKT_INFO_8822C 16 +#define BIT_MASK_CMDQ_PKT_INFO_8822C 0xfff +#define BIT_CMDQ_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_CMDQ_PKT_INFO_8822C) << BIT_SHIFT_CMDQ_PKT_INFO_8822C) +#define BITS_CMDQ_PKT_INFO_8822C \ + (BIT_MASK_CMDQ_PKT_INFO_8822C << BIT_SHIFT_CMDQ_PKT_INFO_8822C) +#define BIT_CLEAR_CMDQ_PKT_INFO_8822C(x) ((x) & (~BITS_CMDQ_PKT_INFO_8822C)) +#define BIT_GET_CMDQ_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822C) & BIT_MASK_CMDQ_PKT_INFO_8822C) +#define BIT_SET_CMDQ_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_CMDQ_PKT_INFO_8822C(x) | BIT_CMDQ_PKT_INFO_8822C(v)) + +#define BIT_SHIFT_BCNQ_PKT_INFO_8822C 0 +#define BIT_MASK_BCNQ_PKT_INFO_8822C 0xfff +#define BIT_BCNQ_PKT_INFO_8822C(x) \ + (((x) & BIT_MASK_BCNQ_PKT_INFO_8822C) << BIT_SHIFT_BCNQ_PKT_INFO_8822C) +#define BITS_BCNQ_PKT_INFO_8822C \ + (BIT_MASK_BCNQ_PKT_INFO_8822C << BIT_SHIFT_BCNQ_PKT_INFO_8822C) +#define BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) ((x) & (~BITS_BCNQ_PKT_INFO_8822C)) +#define BIT_GET_BCNQ_PKT_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822C) & BIT_MASK_BCNQ_PKT_INFO_8822C) +#define BIT_SET_BCNQ_PKT_INFO_8822C(x, v) \ + (BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) | BIT_BCNQ_PKT_INFO_8822C(v)) + +/* 2 REG_LOOPBACK_OPTION_8822C */ +#define BIT_LOOPACK_FAST_EDCA_EN_8822C BIT(24) + +/* 2 REG_AESIV_SETTING_8822C */ + +#define BIT_SHIFT_AESIV_OFFSET_8822C 0 +#define BIT_MASK_AESIV_OFFSET_8822C 0xfff +#define BIT_AESIV_OFFSET_8822C(x) \ + (((x) & BIT_MASK_AESIV_OFFSET_8822C) << BIT_SHIFT_AESIV_OFFSET_8822C) +#define BITS_AESIV_OFFSET_8822C \ + (BIT_MASK_AESIV_OFFSET_8822C << BIT_SHIFT_AESIV_OFFSET_8822C) +#define BIT_CLEAR_AESIV_OFFSET_8822C(x) ((x) & (~BITS_AESIV_OFFSET_8822C)) +#define BIT_GET_AESIV_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_AESIV_OFFSET_8822C) & BIT_MASK_AESIV_OFFSET_8822C) +#define BIT_SET_AESIV_OFFSET_8822C(x, v) \ + (BIT_CLEAR_AESIV_OFFSET_8822C(x) | BIT_AESIV_OFFSET_8822C(v)) + +/* 2 REG_BF0_TIME_SETTING_8822C */ +#define BIT_BF0_TIMER_SET_8822C BIT(31) +#define BIT_BF0_TIMER_CLR_8822C BIT(30) +#define BIT_BF0_UPDATE_EN_8822C BIT(29) +#define BIT_BF0_TIMER_EN_8822C BIT(28) + +#define BIT_SHIFT_BF0_PRETIME_OVER_8822C 16 +#define BIT_MASK_BF0_PRETIME_OVER_8822C 0xfff +#define BIT_BF0_PRETIME_OVER_8822C(x) \ + (((x) & BIT_MASK_BF0_PRETIME_OVER_8822C) \ + << BIT_SHIFT_BF0_PRETIME_OVER_8822C) +#define BITS_BF0_PRETIME_OVER_8822C \ + (BIT_MASK_BF0_PRETIME_OVER_8822C << BIT_SHIFT_BF0_PRETIME_OVER_8822C) +#define BIT_CLEAR_BF0_PRETIME_OVER_8822C(x) \ + ((x) & (~BITS_BF0_PRETIME_OVER_8822C)) +#define BIT_GET_BF0_PRETIME_OVER_8822C(x) \ + (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822C) & \ + BIT_MASK_BF0_PRETIME_OVER_8822C) +#define BIT_SET_BF0_PRETIME_OVER_8822C(x, v) \ + (BIT_CLEAR_BF0_PRETIME_OVER_8822C(x) | BIT_BF0_PRETIME_OVER_8822C(v)) + +#define BIT_SHIFT_BF0_LIFETIME_8822C 0 +#define BIT_MASK_BF0_LIFETIME_8822C 0xffff +#define BIT_BF0_LIFETIME_8822C(x) \ + (((x) & BIT_MASK_BF0_LIFETIME_8822C) << BIT_SHIFT_BF0_LIFETIME_8822C) +#define BITS_BF0_LIFETIME_8822C \ + (BIT_MASK_BF0_LIFETIME_8822C << BIT_SHIFT_BF0_LIFETIME_8822C) +#define BIT_CLEAR_BF0_LIFETIME_8822C(x) ((x) & (~BITS_BF0_LIFETIME_8822C)) +#define BIT_GET_BF0_LIFETIME_8822C(x) \ + (((x) >> BIT_SHIFT_BF0_LIFETIME_8822C) & BIT_MASK_BF0_LIFETIME_8822C) +#define BIT_SET_BF0_LIFETIME_8822C(x, v) \ + (BIT_CLEAR_BF0_LIFETIME_8822C(x) | BIT_BF0_LIFETIME_8822C(v)) + +/* 2 REG_BF1_TIME_SETTING_8822C */ +#define BIT_BF1_TIMER_SET_8822C BIT(31) +#define BIT_BF1_TIMER_CLR_8822C BIT(30) +#define BIT_BF1_UPDATE_EN_8822C BIT(29) +#define BIT_BF1_TIMER_EN_8822C BIT(28) + +#define BIT_SHIFT_BF1_PRETIME_OVER_8822C 16 +#define BIT_MASK_BF1_PRETIME_OVER_8822C 0xfff +#define BIT_BF1_PRETIME_OVER_8822C(x) \ + (((x) & BIT_MASK_BF1_PRETIME_OVER_8822C) \ + << BIT_SHIFT_BF1_PRETIME_OVER_8822C) +#define BITS_BF1_PRETIME_OVER_8822C \ + (BIT_MASK_BF1_PRETIME_OVER_8822C << BIT_SHIFT_BF1_PRETIME_OVER_8822C) +#define BIT_CLEAR_BF1_PRETIME_OVER_8822C(x) \ + ((x) & (~BITS_BF1_PRETIME_OVER_8822C)) +#define BIT_GET_BF1_PRETIME_OVER_8822C(x) \ + (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822C) & \ + BIT_MASK_BF1_PRETIME_OVER_8822C) +#define BIT_SET_BF1_PRETIME_OVER_8822C(x, v) \ + (BIT_CLEAR_BF1_PRETIME_OVER_8822C(x) | BIT_BF1_PRETIME_OVER_8822C(v)) + +#define BIT_SHIFT_BF1_LIFETIME_8822C 0 +#define BIT_MASK_BF1_LIFETIME_8822C 0xffff +#define BIT_BF1_LIFETIME_8822C(x) \ + (((x) & BIT_MASK_BF1_LIFETIME_8822C) << BIT_SHIFT_BF1_LIFETIME_8822C) +#define BITS_BF1_LIFETIME_8822C \ + (BIT_MASK_BF1_LIFETIME_8822C << BIT_SHIFT_BF1_LIFETIME_8822C) +#define BIT_CLEAR_BF1_LIFETIME_8822C(x) ((x) & (~BITS_BF1_LIFETIME_8822C)) +#define BIT_GET_BF1_LIFETIME_8822C(x) \ + (((x) >> BIT_SHIFT_BF1_LIFETIME_8822C) & BIT_MASK_BF1_LIFETIME_8822C) +#define BIT_SET_BF1_LIFETIME_8822C(x, v) \ + (BIT_CLEAR_BF1_LIFETIME_8822C(x) | BIT_BF1_LIFETIME_8822C(v)) + +/* 2 REG_BF_TIMEOUT_EN_8822C */ +#define BIT_EN_VHT_LDPC_8822C BIT(9) +#define BIT_EN_HT_LDPC_8822C BIT(8) +#define BIT_BF1_TIMEOUT_EN_8822C BIT(1) +#define BIT_BF0_TIMEOUT_EN_8822C BIT(0) + +/* 2 REG_MACID_RELEASE0_8822C */ + +#define BIT_SHIFT_MACID31_0_RELEASE_8822C 0 +#define BIT_MASK_MACID31_0_RELEASE_8822C 0xffffffffL +#define BIT_MACID31_0_RELEASE_8822C(x) \ + (((x) & BIT_MASK_MACID31_0_RELEASE_8822C) \ + << BIT_SHIFT_MACID31_0_RELEASE_8822C) +#define BITS_MACID31_0_RELEASE_8822C \ + (BIT_MASK_MACID31_0_RELEASE_8822C << BIT_SHIFT_MACID31_0_RELEASE_8822C) +#define BIT_CLEAR_MACID31_0_RELEASE_8822C(x) \ + ((x) & (~BITS_MACID31_0_RELEASE_8822C)) +#define BIT_GET_MACID31_0_RELEASE_8822C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822C) & \ + BIT_MASK_MACID31_0_RELEASE_8822C) +#define BIT_SET_MACID31_0_RELEASE_8822C(x, v) \ + (BIT_CLEAR_MACID31_0_RELEASE_8822C(x) | BIT_MACID31_0_RELEASE_8822C(v)) + +/* 2 REG_MACID_RELEASE1_8822C */ + +#define BIT_SHIFT_MACID63_32_RELEASE_8822C 0 +#define BIT_MASK_MACID63_32_RELEASE_8822C 0xffffffffL +#define BIT_MACID63_32_RELEASE_8822C(x) \ + (((x) & BIT_MASK_MACID63_32_RELEASE_8822C) \ + << BIT_SHIFT_MACID63_32_RELEASE_8822C) +#define BITS_MACID63_32_RELEASE_8822C \ + (BIT_MASK_MACID63_32_RELEASE_8822C \ + << BIT_SHIFT_MACID63_32_RELEASE_8822C) +#define BIT_CLEAR_MACID63_32_RELEASE_8822C(x) \ + ((x) & (~BITS_MACID63_32_RELEASE_8822C)) +#define BIT_GET_MACID63_32_RELEASE_8822C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822C) & \ + BIT_MASK_MACID63_32_RELEASE_8822C) +#define BIT_SET_MACID63_32_RELEASE_8822C(x, v) \ + (BIT_CLEAR_MACID63_32_RELEASE_8822C(x) | \ + BIT_MACID63_32_RELEASE_8822C(v)) + +/* 2 REG_MACID_RELEASE2_8822C */ + +#define BIT_SHIFT_MACID95_64_RELEASE_8822C 0 +#define BIT_MASK_MACID95_64_RELEASE_8822C 0xffffffffL +#define BIT_MACID95_64_RELEASE_8822C(x) \ + (((x) & BIT_MASK_MACID95_64_RELEASE_8822C) \ + << BIT_SHIFT_MACID95_64_RELEASE_8822C) +#define BITS_MACID95_64_RELEASE_8822C \ + (BIT_MASK_MACID95_64_RELEASE_8822C \ + << BIT_SHIFT_MACID95_64_RELEASE_8822C) +#define BIT_CLEAR_MACID95_64_RELEASE_8822C(x) \ + ((x) & (~BITS_MACID95_64_RELEASE_8822C)) +#define BIT_GET_MACID95_64_RELEASE_8822C(x) \ + (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822C) & \ + BIT_MASK_MACID95_64_RELEASE_8822C) +#define BIT_SET_MACID95_64_RELEASE_8822C(x, v) \ + (BIT_CLEAR_MACID95_64_RELEASE_8822C(x) | \ + BIT_MACID95_64_RELEASE_8822C(v)) + +/* 2 REG_MACID_RELEASE3_8822C */ + +#define BIT_SHIFT_MACID127_96_RELEASE_8822C 0 +#define BIT_MASK_MACID127_96_RELEASE_8822C 0xffffffffL +#define BIT_MACID127_96_RELEASE_8822C(x) \ + (((x) & BIT_MASK_MACID127_96_RELEASE_8822C) \ + << BIT_SHIFT_MACID127_96_RELEASE_8822C) +#define BITS_MACID127_96_RELEASE_8822C \ + (BIT_MASK_MACID127_96_RELEASE_8822C \ + << BIT_SHIFT_MACID127_96_RELEASE_8822C) +#define BIT_CLEAR_MACID127_96_RELEASE_8822C(x) \ + ((x) & (~BITS_MACID127_96_RELEASE_8822C)) +#define BIT_GET_MACID127_96_RELEASE_8822C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822C) & \ + BIT_MASK_MACID127_96_RELEASE_8822C) +#define BIT_SET_MACID127_96_RELEASE_8822C(x, v) \ + (BIT_CLEAR_MACID127_96_RELEASE_8822C(x) | \ + BIT_MACID127_96_RELEASE_8822C(v)) + +/* 2 REG_MACID_RELEASE_SETTING_8822C */ +#define BIT_MACID_VALUE_8822C BIT(7) + +#define BIT_SHIFT_MACID_OFFSET_8822C 0 +#define BIT_MASK_MACID_OFFSET_8822C 0x7f +#define BIT_MACID_OFFSET_8822C(x) \ + (((x) & BIT_MASK_MACID_OFFSET_8822C) << BIT_SHIFT_MACID_OFFSET_8822C) +#define BITS_MACID_OFFSET_8822C \ + (BIT_MASK_MACID_OFFSET_8822C << BIT_SHIFT_MACID_OFFSET_8822C) +#define BIT_CLEAR_MACID_OFFSET_8822C(x) ((x) & (~BITS_MACID_OFFSET_8822C)) +#define BIT_GET_MACID_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_MACID_OFFSET_8822C) & BIT_MASK_MACID_OFFSET_8822C) +#define BIT_SET_MACID_OFFSET_8822C(x, v) \ + (BIT_CLEAR_MACID_OFFSET_8822C(x) | BIT_MACID_OFFSET_8822C(v)) + +/* 2 REG_FAST_EDCA_VOVI_SETTING_8822C */ + +#define BIT_SHIFT_VI_FAST_EDCA_TO_8822C 24 +#define BIT_MASK_VI_FAST_EDCA_TO_8822C 0xff +#define BIT_VI_FAST_EDCA_TO_8822C(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_TO_8822C) \ + << BIT_SHIFT_VI_FAST_EDCA_TO_8822C) +#define BITS_VI_FAST_EDCA_TO_8822C \ + (BIT_MASK_VI_FAST_EDCA_TO_8822C << BIT_SHIFT_VI_FAST_EDCA_TO_8822C) +#define BIT_CLEAR_VI_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8822C)) +#define BIT_GET_VI_FAST_EDCA_TO_8822C(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822C) & \ + BIT_MASK_VI_FAST_EDCA_TO_8822C) +#define BIT_SET_VI_FAST_EDCA_TO_8822C(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_TO_8822C(x) | BIT_VI_FAST_EDCA_TO_8822C(v)) + +#define BIT_VI_THRESHOLD_SEL_8822C BIT(23) + +#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C 16 +#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C 0x7f +#define BIT_VI_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C) \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C) +#define BITS_VI_FAST_EDCA_PKT_TH_8822C \ + (BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C \ + << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C) +#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822C(x) \ + ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8822C)) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C) & \ + BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C) +#define BIT_SET_VI_FAST_EDCA_PKT_TH_8822C(x, v) \ + (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822C(x) | \ + BIT_VI_FAST_EDCA_PKT_TH_8822C(v)) + +#define BIT_SHIFT_VO_FAST_EDCA_TO_8822C 8 +#define BIT_MASK_VO_FAST_EDCA_TO_8822C 0xff +#define BIT_VO_FAST_EDCA_TO_8822C(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_TO_8822C) \ + << BIT_SHIFT_VO_FAST_EDCA_TO_8822C) +#define BITS_VO_FAST_EDCA_TO_8822C \ + (BIT_MASK_VO_FAST_EDCA_TO_8822C << BIT_SHIFT_VO_FAST_EDCA_TO_8822C) +#define BIT_CLEAR_VO_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8822C)) +#define BIT_GET_VO_FAST_EDCA_TO_8822C(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822C) & \ + BIT_MASK_VO_FAST_EDCA_TO_8822C) +#define BIT_SET_VO_FAST_EDCA_TO_8822C(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_TO_8822C(x) | BIT_VO_FAST_EDCA_TO_8822C(v)) + +#define BIT_VO_THRESHOLD_SEL_8822C BIT(7) + +#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C 0 +#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C 0x7f +#define BIT_VO_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C) \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C) +#define BITS_VO_FAST_EDCA_PKT_TH_8822C \ + (BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C \ + << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C) +#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822C(x) \ + ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8822C)) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C) & \ + BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C) +#define BIT_SET_VO_FAST_EDCA_PKT_TH_8822C(x, v) \ + (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822C(x) | \ + BIT_VO_FAST_EDCA_PKT_TH_8822C(v)) + +/* 2 REG_FAST_EDCA_BEBK_SETTING_8822C */ + +#define BIT_SHIFT_BK_FAST_EDCA_TO_8822C 24 +#define BIT_MASK_BK_FAST_EDCA_TO_8822C 0xff +#define BIT_BK_FAST_EDCA_TO_8822C(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_TO_8822C) \ + << BIT_SHIFT_BK_FAST_EDCA_TO_8822C) +#define BITS_BK_FAST_EDCA_TO_8822C \ + (BIT_MASK_BK_FAST_EDCA_TO_8822C << BIT_SHIFT_BK_FAST_EDCA_TO_8822C) +#define BIT_CLEAR_BK_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8822C)) +#define BIT_GET_BK_FAST_EDCA_TO_8822C(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822C) & \ + BIT_MASK_BK_FAST_EDCA_TO_8822C) +#define BIT_SET_BK_FAST_EDCA_TO_8822C(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_TO_8822C(x) | BIT_BK_FAST_EDCA_TO_8822C(v)) + +#define BIT_BK_THRESHOLD_SEL_8822C BIT(23) + +#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C 16 +#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C 0x7f +#define BIT_BK_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C) \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C) +#define BITS_BK_FAST_EDCA_PKT_TH_8822C \ + (BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C \ + << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C) +#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822C(x) \ + ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8822C)) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C) & \ + BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C) +#define BIT_SET_BK_FAST_EDCA_PKT_TH_8822C(x, v) \ + (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822C(x) | \ + BIT_BK_FAST_EDCA_PKT_TH_8822C(v)) + +#define BIT_SHIFT_BE_FAST_EDCA_TO_8822C 8 +#define BIT_MASK_BE_FAST_EDCA_TO_8822C 0xff +#define BIT_BE_FAST_EDCA_TO_8822C(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_TO_8822C) \ + << BIT_SHIFT_BE_FAST_EDCA_TO_8822C) +#define BITS_BE_FAST_EDCA_TO_8822C \ + (BIT_MASK_BE_FAST_EDCA_TO_8822C << BIT_SHIFT_BE_FAST_EDCA_TO_8822C) +#define BIT_CLEAR_BE_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8822C)) +#define BIT_GET_BE_FAST_EDCA_TO_8822C(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822C) & \ + BIT_MASK_BE_FAST_EDCA_TO_8822C) +#define BIT_SET_BE_FAST_EDCA_TO_8822C(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_TO_8822C(x) | BIT_BE_FAST_EDCA_TO_8822C(v)) + +#define BIT_BE_THRESHOLD_SEL_8822C BIT(7) + +#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C 0 +#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C 0x7f +#define BIT_BE_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C) \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C) +#define BITS_BE_FAST_EDCA_PKT_TH_8822C \ + (BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C \ + << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C) +#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822C(x) \ + ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8822C)) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822C(x) \ + (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C) & \ + BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C) +#define BIT_SET_BE_FAST_EDCA_PKT_TH_8822C(x, v) \ + (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822C(x) | \ + BIT_BE_FAST_EDCA_PKT_TH_8822C(v)) + +/* 2 REG_MACID_DROP0_8822C */ + +#define BIT_SHIFT_MACID31_0_DROP_8822C 0 +#define BIT_MASK_MACID31_0_DROP_8822C 0xffffffffL +#define BIT_MACID31_0_DROP_8822C(x) \ + (((x) & BIT_MASK_MACID31_0_DROP_8822C) \ + << BIT_SHIFT_MACID31_0_DROP_8822C) +#define BITS_MACID31_0_DROP_8822C \ + (BIT_MASK_MACID31_0_DROP_8822C << BIT_SHIFT_MACID31_0_DROP_8822C) +#define BIT_CLEAR_MACID31_0_DROP_8822C(x) ((x) & (~BITS_MACID31_0_DROP_8822C)) +#define BIT_GET_MACID31_0_DROP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID31_0_DROP_8822C) & \ + BIT_MASK_MACID31_0_DROP_8822C) +#define BIT_SET_MACID31_0_DROP_8822C(x, v) \ + (BIT_CLEAR_MACID31_0_DROP_8822C(x) | BIT_MACID31_0_DROP_8822C(v)) + +/* 2 REG_MACID_DROP1_8822C */ + +#define BIT_SHIFT_MACID63_32_DROP_8822C 0 +#define BIT_MASK_MACID63_32_DROP_8822C 0xffffffffL +#define BIT_MACID63_32_DROP_8822C(x) \ + (((x) & BIT_MASK_MACID63_32_DROP_8822C) \ + << BIT_SHIFT_MACID63_32_DROP_8822C) +#define BITS_MACID63_32_DROP_8822C \ + (BIT_MASK_MACID63_32_DROP_8822C << BIT_SHIFT_MACID63_32_DROP_8822C) +#define BIT_CLEAR_MACID63_32_DROP_8822C(x) ((x) & (~BITS_MACID63_32_DROP_8822C)) +#define BIT_GET_MACID63_32_DROP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID63_32_DROP_8822C) & \ + BIT_MASK_MACID63_32_DROP_8822C) +#define BIT_SET_MACID63_32_DROP_8822C(x, v) \ + (BIT_CLEAR_MACID63_32_DROP_8822C(x) | BIT_MACID63_32_DROP_8822C(v)) + +/* 2 REG_MACID_DROP2_8822C */ + +#define BIT_SHIFT_MACID95_64_DROP_8822C 0 +#define BIT_MASK_MACID95_64_DROP_8822C 0xffffffffL +#define BIT_MACID95_64_DROP_8822C(x) \ + (((x) & BIT_MASK_MACID95_64_DROP_8822C) \ + << BIT_SHIFT_MACID95_64_DROP_8822C) +#define BITS_MACID95_64_DROP_8822C \ + (BIT_MASK_MACID95_64_DROP_8822C << BIT_SHIFT_MACID95_64_DROP_8822C) +#define BIT_CLEAR_MACID95_64_DROP_8822C(x) ((x) & (~BITS_MACID95_64_DROP_8822C)) +#define BIT_GET_MACID95_64_DROP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID95_64_DROP_8822C) & \ + BIT_MASK_MACID95_64_DROP_8822C) +#define BIT_SET_MACID95_64_DROP_8822C(x, v) \ + (BIT_CLEAR_MACID95_64_DROP_8822C(x) | BIT_MACID95_64_DROP_8822C(v)) + +/* 2 REG_MACID_DROP3_8822C */ + +#define BIT_SHIFT_MACID127_96_DROP_8822C 0 +#define BIT_MASK_MACID127_96_DROP_8822C 0xffffffffL +#define BIT_MACID127_96_DROP_8822C(x) \ + (((x) & BIT_MASK_MACID127_96_DROP_8822C) \ + << BIT_SHIFT_MACID127_96_DROP_8822C) +#define BITS_MACID127_96_DROP_8822C \ + (BIT_MASK_MACID127_96_DROP_8822C << BIT_SHIFT_MACID127_96_DROP_8822C) +#define BIT_CLEAR_MACID127_96_DROP_8822C(x) \ + ((x) & (~BITS_MACID127_96_DROP_8822C)) +#define BIT_GET_MACID127_96_DROP_8822C(x) \ + (((x) >> BIT_SHIFT_MACID127_96_DROP_8822C) & \ + BIT_MASK_MACID127_96_DROP_8822C) +#define BIT_SET_MACID127_96_DROP_8822C(x, v) \ + (BIT_CLEAR_MACID127_96_DROP_8822C(x) | BIT_MACID127_96_DROP_8822C(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_0_8822C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C) +#define BITS_R_MACID_RELEASE_SUCCESS_0_8822C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8822C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8822C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_0_8822C(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_1_8822C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C) +#define BITS_R_MACID_RELEASE_SUCCESS_1_8822C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8822C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8822C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_1_8822C(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_2_8822C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C) +#define BITS_R_MACID_RELEASE_SUCCESS_2_8822C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8822C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8822C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_2_8822C(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_3_8822C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C) +#define BITS_R_MACID_RELEASE_SUCCESS_3_8822C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8822C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8822C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_3_8822C(v)) + +/* 2 REG_MGQ_FIFO_WRITE_POINTER_8822C */ +#define BIT_MGQ_FIFO_OV_8822C BIT(7) +#define BIT_MGQ_FIFO_WPTR_ERROR_8822C BIT(6) +#define BIT_EN_MGQ_FIFO_LIFETIME_8822C BIT(5) + +#define BIT_SHIFT_MGQ_FIFO_WPTR_8822C 0 +#define BIT_MASK_MGQ_FIFO_WPTR_8822C 0x1f +#define BIT_MGQ_FIFO_WPTR_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_WPTR_8822C) << BIT_SHIFT_MGQ_FIFO_WPTR_8822C) +#define BITS_MGQ_FIFO_WPTR_8822C \ + (BIT_MASK_MGQ_FIFO_WPTR_8822C << BIT_SHIFT_MGQ_FIFO_WPTR_8822C) +#define BIT_CLEAR_MGQ_FIFO_WPTR_8822C(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8822C)) +#define BIT_GET_MGQ_FIFO_WPTR_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8822C) & BIT_MASK_MGQ_FIFO_WPTR_8822C) +#define BIT_SET_MGQ_FIFO_WPTR_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_WPTR_8822C(x) | BIT_MGQ_FIFO_WPTR_8822C(v)) + +/* 2 REG_MGQ_FIFO_READ_POINTER_8822C */ + +#define BIT_SHIFT_MGQ_FIFO_SIZE_8822C 14 +#define BIT_MASK_MGQ_FIFO_SIZE_8822C 0x3 +#define BIT_MGQ_FIFO_SIZE_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_SIZE_8822C) << BIT_SHIFT_MGQ_FIFO_SIZE_8822C) +#define BITS_MGQ_FIFO_SIZE_8822C \ + (BIT_MASK_MGQ_FIFO_SIZE_8822C << BIT_SHIFT_MGQ_FIFO_SIZE_8822C) +#define BIT_CLEAR_MGQ_FIFO_SIZE_8822C(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8822C)) +#define BIT_GET_MGQ_FIFO_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8822C) & BIT_MASK_MGQ_FIFO_SIZE_8822C) +#define BIT_SET_MGQ_FIFO_SIZE_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_SIZE_8822C(x) | BIT_MGQ_FIFO_SIZE_8822C(v)) + +#define BIT_MGQ_FIFO_PAUSE_8822C BIT(13) + +#define BIT_SHIFT_MGQ_FIFO_RPTR_8822C 8 +#define BIT_MASK_MGQ_FIFO_RPTR_8822C 0x1f +#define BIT_MGQ_FIFO_RPTR_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_RPTR_8822C) << BIT_SHIFT_MGQ_FIFO_RPTR_8822C) +#define BITS_MGQ_FIFO_RPTR_8822C \ + (BIT_MASK_MGQ_FIFO_RPTR_8822C << BIT_SHIFT_MGQ_FIFO_RPTR_8822C) +#define BIT_CLEAR_MGQ_FIFO_RPTR_8822C(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8822C)) +#define BIT_GET_MGQ_FIFO_RPTR_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8822C) & BIT_MASK_MGQ_FIFO_RPTR_8822C) +#define BIT_SET_MGQ_FIFO_RPTR_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_RPTR_8822C(x) | BIT_MGQ_FIFO_RPTR_8822C(v)) + +/* 2 REG_MGQ_FIFO_ENABLE_8822C */ +#define BIT_MGQ_FIFO_EN_8822C BIT(15) + +#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C 12 +#define BIT_MASK_MGQ_FIFO_PG_SIZE_8822C 0x7 +#define BIT_MGQ_FIFO_PG_SIZE_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8822C) \ + << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C) +#define BITS_MGQ_FIFO_PG_SIZE_8822C \ + (BIT_MASK_MGQ_FIFO_PG_SIZE_8822C << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C) +#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_PG_SIZE_8822C)) +#define BIT_GET_MGQ_FIFO_PG_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C) & \ + BIT_MASK_MGQ_FIFO_PG_SIZE_8822C) +#define BIT_SET_MGQ_FIFO_PG_SIZE_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PG_SIZE_8822C(x) | BIT_MGQ_FIFO_PG_SIZE_8822C(v)) + +#define BIT_SHIFT_MGQ_FIFO_START_PG_8822C 0 +#define BIT_MASK_MGQ_FIFO_START_PG_8822C 0xfff +#define BIT_MGQ_FIFO_START_PG_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_START_PG_8822C) \ + << BIT_SHIFT_MGQ_FIFO_START_PG_8822C) +#define BITS_MGQ_FIFO_START_PG_8822C \ + (BIT_MASK_MGQ_FIFO_START_PG_8822C << BIT_SHIFT_MGQ_FIFO_START_PG_8822C) +#define BIT_CLEAR_MGQ_FIFO_START_PG_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_START_PG_8822C)) +#define BIT_GET_MGQ_FIFO_START_PG_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8822C) & \ + BIT_MASK_MGQ_FIFO_START_PG_8822C) +#define BIT_SET_MGQ_FIFO_START_PG_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_START_PG_8822C(x) | BIT_MGQ_FIFO_START_PG_8822C(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8822C */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C 0xffff +#define BIT_MGQ_FIFO_REL_INT_MASK_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C) +#define BITS_MGQ_FIFO_REL_INT_MASK_8822C \ + (BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8822C)) +#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C) & \ + BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C) +#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8822C(x) | \ + BIT_MGQ_FIFO_REL_INT_MASK_8822C(v)) + +/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8822C */ + +#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C 0 +#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C 0xffff +#define BIT_MGQ_FIFO_REL_INT_FLAG_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C) \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C) +#define BITS_MGQ_FIFO_REL_INT_FLAG_8822C \ + (BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C \ + << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C) +#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8822C)) +#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C) & \ + BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C) +#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8822C(x) | \ + BIT_MGQ_FIFO_REL_INT_FLAG_8822C(v)) + +/* 2 REG_MGQ_FIFO_VALID_MAP_8822C */ + +#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C 0 +#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C 0xffff +#define BIT_MGQ_FIFO_PKT_VALID_MAP_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C) \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C) +#define BITS_MGQ_FIFO_PKT_VALID_MAP_8822C \ + (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C \ + << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C) +#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8822C)) +#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C) & \ + BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C) +#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8822C(x) | \ + BIT_MGQ_FIFO_PKT_VALID_MAP_8822C(v)) + +/* 2 REG_MGQ_FIFO_LIFETIME_8822C */ + +#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C 0 +#define BIT_MASK_MGQ_FIFO_LIFETIME_8822C 0xffff +#define BIT_MGQ_FIFO_LIFETIME_8822C(x) \ + (((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8822C) \ + << BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C) +#define BITS_MGQ_FIFO_LIFETIME_8822C \ + (BIT_MASK_MGQ_FIFO_LIFETIME_8822C << BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C) +#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8822C(x) \ + ((x) & (~BITS_MGQ_FIFO_LIFETIME_8822C)) +#define BIT_GET_MGQ_FIFO_LIFETIME_8822C(x) \ + (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C) & \ + BIT_MASK_MGQ_FIFO_LIFETIME_8822C) +#define BIT_SET_MGQ_FIFO_LIFETIME_8822C(x, v) \ + (BIT_CLEAR_MGQ_FIFO_LIFETIME_8822C(x) | BIT_MGQ_FIFO_LIFETIME_8822C(v)) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0x7f +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) \ + (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) +#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C \ + (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C \ + << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) +#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) \ + ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) & \ + BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) +#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x, v) \ + (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) | \ + BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(v)) + +/* 2 REG_SHCUT_SETTING_8822C */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE0_8822C */ + +/* 2 REG_SHCUT_LLC_ETH_TYPE1_8822C */ + +/* 2 REG_SHCUT_LLC_OUI0_8822C */ + +/* 2 REG_SHCUT_LLC_OUI1_8822C */ + +/* 2 REG_SHCUT_LLC_OUI2_8822C */ + +/* 2 REG_MU_TX_CTL_8822C */ +#define BIT_R_MU_P1_WAIT_STATE_EN_8822C BIT(16) + +#define BIT_SHIFT_R_MU_RL_8822C 12 +#define BIT_MASK_R_MU_RL_8822C 0xf +#define BIT_R_MU_RL_8822C(x) \ + (((x) & BIT_MASK_R_MU_RL_8822C) << BIT_SHIFT_R_MU_RL_8822C) +#define BITS_R_MU_RL_8822C (BIT_MASK_R_MU_RL_8822C << BIT_SHIFT_R_MU_RL_8822C) +#define BIT_CLEAR_R_MU_RL_8822C(x) ((x) & (~BITS_R_MU_RL_8822C)) +#define BIT_GET_R_MU_RL_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_RL_8822C) & BIT_MASK_R_MU_RL_8822C) +#define BIT_SET_R_MU_RL_8822C(x, v) \ + (BIT_CLEAR_R_MU_RL_8822C(x) | BIT_R_MU_RL_8822C(v)) + +#define BIT_R_FORCE_P1_RATEDOWN_8822C BIT(11) + +#define BIT_SHIFT_R_MU_TAB_SEL_8822C 8 +#define BIT_MASK_R_MU_TAB_SEL_8822C 0x7 +#define BIT_R_MU_TAB_SEL_8822C(x) \ + (((x) & BIT_MASK_R_MU_TAB_SEL_8822C) << BIT_SHIFT_R_MU_TAB_SEL_8822C) +#define BITS_R_MU_TAB_SEL_8822C \ + (BIT_MASK_R_MU_TAB_SEL_8822C << BIT_SHIFT_R_MU_TAB_SEL_8822C) +#define BIT_CLEAR_R_MU_TAB_SEL_8822C(x) ((x) & (~BITS_R_MU_TAB_SEL_8822C)) +#define BIT_GET_R_MU_TAB_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8822C) & BIT_MASK_R_MU_TAB_SEL_8822C) +#define BIT_SET_R_MU_TAB_SEL_8822C(x, v) \ + (BIT_CLEAR_R_MU_TAB_SEL_8822C(x) | BIT_R_MU_TAB_SEL_8822C(v)) + +#define BIT_R_EN_MU_MIMO_8822C BIT(7) +#define BIT_R_EN_REVERS_GTAB_8822C BIT(6) + +#define BIT_SHIFT_R_MU_TABLE_VALID_8822C 0 +#define BIT_MASK_R_MU_TABLE_VALID_8822C 0x3f +#define BIT_R_MU_TABLE_VALID_8822C(x) \ + (((x) & BIT_MASK_R_MU_TABLE_VALID_8822C) \ + << BIT_SHIFT_R_MU_TABLE_VALID_8822C) +#define BITS_R_MU_TABLE_VALID_8822C \ + (BIT_MASK_R_MU_TABLE_VALID_8822C << BIT_SHIFT_R_MU_TABLE_VALID_8822C) +#define BIT_CLEAR_R_MU_TABLE_VALID_8822C(x) \ + ((x) & (~BITS_R_MU_TABLE_VALID_8822C)) +#define BIT_GET_R_MU_TABLE_VALID_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822C) & \ + BIT_MASK_R_MU_TABLE_VALID_8822C) +#define BIT_SET_R_MU_TABLE_VALID_8822C(x, v) \ + (BIT_CLEAR_R_MU_TABLE_VALID_8822C(x) | BIT_R_MU_TABLE_VALID_8822C(v)) + +/* 2 REG_MU_STA_GID_VLD_8822C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID_8822C 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID_8822C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822C) \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C) +#define BITS_R_MU_STA_GTAB_VALID_8822C \ + (BIT_MASK_R_MU_STA_GTAB_VALID_8822C \ + << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C) +#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822C)) +#define BIT_GET_R_MU_STA_GTAB_VALID_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C) & \ + BIT_MASK_R_MU_STA_GTAB_VALID_8822C) +#define BIT_SET_R_MU_STA_GTAB_VALID_8822C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822C(x) | \ + BIT_R_MU_STA_GTAB_VALID_8822C(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_8822C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_L_8822C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C) +#define BITS_R_MU_STA_GTAB_POSITION_L_8822C \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8822C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_L_8822C)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_L_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C) +#define BIT_SET_R_MU_STA_GTAB_POSITION_L_8822C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8822C(x) | \ + BIT_R_MU_STA_GTAB_POSITION_L_8822C(v)) + +/* 2 REG_MU_STA_USER_POS_INFO_H_8822C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C 0xffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_H_8822C(x) \ + (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C) \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C) +#define BITS_R_MU_STA_GTAB_POSITION_H_8822C \ + (BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C \ + << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C) +#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8822C(x) \ + ((x) & (~BITS_R_MU_STA_GTAB_POSITION_H_8822C)) +#define BIT_GET_R_MU_STA_GTAB_POSITION_H_8822C(x) \ + (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C) & \ + BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C) +#define BIT_SET_R_MU_STA_GTAB_POSITION_H_8822C(x, v) \ + (BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8822C(x) | \ + BIT_R_MU_STA_GTAB_POSITION_H_8822C(v)) + +/* 2 REG_CHNL_INFO_CTRL_8822C */ +#define BIT_CHNL_REF_RXNAV_8822C BIT(7) +#define BIT_CHNL_REF_VBON_8822C BIT(6) +#define BIT_CHNL_REF_EDCA_8822C BIT(5) +#define BIT_CHNL_REF_CCA_8822C BIT(4) +#define BIT_RST_CHNL_BUSY_8822C BIT(3) +#define BIT_RST_CHNL_IDLE_8822C BIT(2) +#define BIT_CHNL_INFO_RST_8822C BIT(1) +#define BIT_ATM_AIRTIME_EN_8822C BIT(0) + +/* 2 REG_CHNL_IDLE_TIME_8822C */ + +#define BIT_SHIFT_CHNL_IDLE_TIME_8822C 0 +#define BIT_MASK_CHNL_IDLE_TIME_8822C 0xffffffffL +#define BIT_CHNL_IDLE_TIME_8822C(x) \ + (((x) & BIT_MASK_CHNL_IDLE_TIME_8822C) \ + << BIT_SHIFT_CHNL_IDLE_TIME_8822C) +#define BITS_CHNL_IDLE_TIME_8822C \ + (BIT_MASK_CHNL_IDLE_TIME_8822C << BIT_SHIFT_CHNL_IDLE_TIME_8822C) +#define BIT_CLEAR_CHNL_IDLE_TIME_8822C(x) ((x) & (~BITS_CHNL_IDLE_TIME_8822C)) +#define BIT_GET_CHNL_IDLE_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8822C) & \ + BIT_MASK_CHNL_IDLE_TIME_8822C) +#define BIT_SET_CHNL_IDLE_TIME_8822C(x, v) \ + (BIT_CLEAR_CHNL_IDLE_TIME_8822C(x) | BIT_CHNL_IDLE_TIME_8822C(v)) + +/* 2 REG_CHNL_BUSY_TIME_8822C */ + +#define BIT_SHIFT_CHNL_BUSY_TIME_8822C 0 +#define BIT_MASK_CHNL_BUSY_TIME_8822C 0xffffffffL +#define BIT_CHNL_BUSY_TIME_8822C(x) \ + (((x) & BIT_MASK_CHNL_BUSY_TIME_8822C) \ + << BIT_SHIFT_CHNL_BUSY_TIME_8822C) +#define BITS_CHNL_BUSY_TIME_8822C \ + (BIT_MASK_CHNL_BUSY_TIME_8822C << BIT_SHIFT_CHNL_BUSY_TIME_8822C) +#define BIT_CLEAR_CHNL_BUSY_TIME_8822C(x) ((x) & (~BITS_CHNL_BUSY_TIME_8822C)) +#define BIT_GET_CHNL_BUSY_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8822C) & \ + BIT_MASK_CHNL_BUSY_TIME_8822C) +#define BIT_SET_CHNL_BUSY_TIME_8822C(x, v) \ + (BIT_CLEAR_CHNL_BUSY_TIME_8822C(x) | BIT_CHNL_BUSY_TIME_8822C(v)) + +/* 2 REG_MU_TRX_DBG_CNT_V1_8822C */ +#define BIT_MU_DNGCNT_RST_8822C BIT(20) + +#define BIT_SHIFT_MU_DNGCNT_SEL_8822C 16 +#define BIT_MASK_MU_DNGCNT_SEL_8822C 0xf +#define BIT_MU_DNGCNT_SEL_8822C(x) \ + (((x) & BIT_MASK_MU_DNGCNT_SEL_8822C) << BIT_SHIFT_MU_DNGCNT_SEL_8822C) +#define BITS_MU_DNGCNT_SEL_8822C \ + (BIT_MASK_MU_DNGCNT_SEL_8822C << BIT_SHIFT_MU_DNGCNT_SEL_8822C) +#define BIT_CLEAR_MU_DNGCNT_SEL_8822C(x) ((x) & (~BITS_MU_DNGCNT_SEL_8822C)) +#define BIT_GET_MU_DNGCNT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_SEL_8822C) & BIT_MASK_MU_DNGCNT_SEL_8822C) +#define BIT_SET_MU_DNGCNT_SEL_8822C(x, v) \ + (BIT_CLEAR_MU_DNGCNT_SEL_8822C(x) | BIT_MU_DNGCNT_SEL_8822C(v)) + +#define BIT_SHIFT_MU_DNGCNT_8822C 0 +#define BIT_MASK_MU_DNGCNT_8822C 0xffff +#define BIT_MU_DNGCNT_8822C(x) \ + (((x) & BIT_MASK_MU_DNGCNT_8822C) << BIT_SHIFT_MU_DNGCNT_8822C) +#define BITS_MU_DNGCNT_8822C \ + (BIT_MASK_MU_DNGCNT_8822C << BIT_SHIFT_MU_DNGCNT_8822C) +#define BIT_CLEAR_MU_DNGCNT_8822C(x) ((x) & (~BITS_MU_DNGCNT_8822C)) +#define BIT_GET_MU_DNGCNT_8822C(x) \ + (((x) >> BIT_SHIFT_MU_DNGCNT_8822C) & BIT_MASK_MU_DNGCNT_8822C) +#define BIT_SET_MU_DNGCNT_8822C(x, v) \ + (BIT_CLEAR_MU_DNGCNT_8822C(x) | BIT_MU_DNGCNT_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_EDCA_VO_PARAM_8822C */ + +#define BIT_SHIFT_TXOPLIMIT_8822C 16 +#define BIT_MASK_TXOPLIMIT_8822C 0x7ff +#define BIT_TXOPLIMIT_8822C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C) +#define BITS_TXOPLIMIT_8822C \ + (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C) +#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C)) +#define BIT_GET_TXOPLIMIT_8822C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C) +#define BIT_SET_TXOPLIMIT_8822C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v)) + +#define BIT_SHIFT_CW_8822C 8 +#define BIT_MASK_CW_8822C 0xff +#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C) +#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C) +#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C)) +#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C) +#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v)) + +#define BIT_SHIFT_AIFS_8822C 0 +#define BIT_MASK_AIFS_8822C 0xff +#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C) +#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C) +#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C)) +#define BIT_GET_AIFS_8822C(x) \ + (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C) +#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v)) + +/* 2 REG_EDCA_VI_PARAM_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_TXOPLIMIT_8822C 16 +#define BIT_MASK_TXOPLIMIT_8822C 0x7ff +#define BIT_TXOPLIMIT_8822C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C) +#define BITS_TXOPLIMIT_8822C \ + (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C) +#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C)) +#define BIT_GET_TXOPLIMIT_8822C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C) +#define BIT_SET_TXOPLIMIT_8822C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v)) + +#define BIT_SHIFT_CW_8822C 8 +#define BIT_MASK_CW_8822C 0xff +#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C) +#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C) +#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C)) +#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C) +#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v)) + +#define BIT_SHIFT_AIFS_8822C 0 +#define BIT_MASK_AIFS_8822C 0xff +#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C) +#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C) +#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C)) +#define BIT_GET_AIFS_8822C(x) \ + (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C) +#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v)) + +/* 2 REG_EDCA_BE_PARAM_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_TXOPLIMIT_8822C 16 +#define BIT_MASK_TXOPLIMIT_8822C 0x7ff +#define BIT_TXOPLIMIT_8822C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C) +#define BITS_TXOPLIMIT_8822C \ + (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C) +#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C)) +#define BIT_GET_TXOPLIMIT_8822C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C) +#define BIT_SET_TXOPLIMIT_8822C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v)) + +#define BIT_SHIFT_CW_8822C 8 +#define BIT_MASK_CW_8822C 0xff +#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C) +#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C) +#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C)) +#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C) +#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v)) + +#define BIT_SHIFT_AIFS_8822C 0 +#define BIT_MASK_AIFS_8822C 0xff +#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C) +#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C) +#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C)) +#define BIT_GET_AIFS_8822C(x) \ + (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C) +#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v)) + +/* 2 REG_EDCA_BK_PARAM_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_TXOPLIMIT_8822C 16 +#define BIT_MASK_TXOPLIMIT_8822C 0x7ff +#define BIT_TXOPLIMIT_8822C(x) \ + (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C) +#define BITS_TXOPLIMIT_8822C \ + (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C) +#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C)) +#define BIT_GET_TXOPLIMIT_8822C(x) \ + (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C) +#define BIT_SET_TXOPLIMIT_8822C(x, v) \ + (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v)) + +#define BIT_SHIFT_CW_8822C 8 +#define BIT_MASK_CW_8822C 0xff +#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C) +#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C) +#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C)) +#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C) +#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v)) + +#define BIT_SHIFT_AIFS_8822C 0 +#define BIT_MASK_AIFS_8822C 0xff +#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C) +#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C) +#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C)) +#define BIT_GET_AIFS_8822C(x) \ + (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C) +#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v)) + +/* 2 REG_BCNTCFG_8822C */ + +#define BIT_SHIFT_BCNCW_MAX_8822C 12 +#define BIT_MASK_BCNCW_MAX_8822C 0xf +#define BIT_BCNCW_MAX_8822C(x) \ + (((x) & BIT_MASK_BCNCW_MAX_8822C) << BIT_SHIFT_BCNCW_MAX_8822C) +#define BITS_BCNCW_MAX_8822C \ + (BIT_MASK_BCNCW_MAX_8822C << BIT_SHIFT_BCNCW_MAX_8822C) +#define BIT_CLEAR_BCNCW_MAX_8822C(x) ((x) & (~BITS_BCNCW_MAX_8822C)) +#define BIT_GET_BCNCW_MAX_8822C(x) \ + (((x) >> BIT_SHIFT_BCNCW_MAX_8822C) & BIT_MASK_BCNCW_MAX_8822C) +#define BIT_SET_BCNCW_MAX_8822C(x, v) \ + (BIT_CLEAR_BCNCW_MAX_8822C(x) | BIT_BCNCW_MAX_8822C(v)) + +#define BIT_SHIFT_BCNCW_MIN_8822C 8 +#define BIT_MASK_BCNCW_MIN_8822C 0xf +#define BIT_BCNCW_MIN_8822C(x) \ + (((x) & BIT_MASK_BCNCW_MIN_8822C) << BIT_SHIFT_BCNCW_MIN_8822C) +#define BITS_BCNCW_MIN_8822C \ + (BIT_MASK_BCNCW_MIN_8822C << BIT_SHIFT_BCNCW_MIN_8822C) +#define BIT_CLEAR_BCNCW_MIN_8822C(x) ((x) & (~BITS_BCNCW_MIN_8822C)) +#define BIT_GET_BCNCW_MIN_8822C(x) \ + (((x) >> BIT_SHIFT_BCNCW_MIN_8822C) & BIT_MASK_BCNCW_MIN_8822C) +#define BIT_SET_BCNCW_MIN_8822C(x, v) \ + (BIT_CLEAR_BCNCW_MIN_8822C(x) | BIT_BCNCW_MIN_8822C(v)) + +#define BIT_SHIFT_BCNIFS_8822C 0 +#define BIT_MASK_BCNIFS_8822C 0xff +#define BIT_BCNIFS_8822C(x) \ + (((x) & BIT_MASK_BCNIFS_8822C) << BIT_SHIFT_BCNIFS_8822C) +#define BITS_BCNIFS_8822C (BIT_MASK_BCNIFS_8822C << BIT_SHIFT_BCNIFS_8822C) +#define BIT_CLEAR_BCNIFS_8822C(x) ((x) & (~BITS_BCNIFS_8822C)) +#define BIT_GET_BCNIFS_8822C(x) \ + (((x) >> BIT_SHIFT_BCNIFS_8822C) & BIT_MASK_BCNIFS_8822C) +#define BIT_SET_BCNIFS_8822C(x, v) \ + (BIT_CLEAR_BCNIFS_8822C(x) | BIT_BCNIFS_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_PIFS_8822C */ + +#define BIT_SHIFT_PIFS_8822C 0 +#define BIT_MASK_PIFS_8822C 0xff +#define BIT_PIFS_8822C(x) (((x) & BIT_MASK_PIFS_8822C) << BIT_SHIFT_PIFS_8822C) +#define BITS_PIFS_8822C (BIT_MASK_PIFS_8822C << BIT_SHIFT_PIFS_8822C) +#define BIT_CLEAR_PIFS_8822C(x) ((x) & (~BITS_PIFS_8822C)) +#define BIT_GET_PIFS_8822C(x) \ + (((x) >> BIT_SHIFT_PIFS_8822C) & BIT_MASK_PIFS_8822C) +#define BIT_SET_PIFS_8822C(x, v) (BIT_CLEAR_PIFS_8822C(x) | BIT_PIFS_8822C(v)) + +/* 2 REG_RDG_PIFS_8822C */ + +#define BIT_SHIFT_RDG_PIFS_8822C 0 +#define BIT_MASK_RDG_PIFS_8822C 0xff +#define BIT_RDG_PIFS_8822C(x) \ + (((x) & BIT_MASK_RDG_PIFS_8822C) << BIT_SHIFT_RDG_PIFS_8822C) +#define BITS_RDG_PIFS_8822C \ + (BIT_MASK_RDG_PIFS_8822C << BIT_SHIFT_RDG_PIFS_8822C) +#define BIT_CLEAR_RDG_PIFS_8822C(x) ((x) & (~BITS_RDG_PIFS_8822C)) +#define BIT_GET_RDG_PIFS_8822C(x) \ + (((x) >> BIT_SHIFT_RDG_PIFS_8822C) & BIT_MASK_RDG_PIFS_8822C) +#define BIT_SET_RDG_PIFS_8822C(x, v) \ + (BIT_CLEAR_RDG_PIFS_8822C(x) | BIT_RDG_PIFS_8822C(v)) + +/* 2 REG_SIFS_8822C */ + +#define BIT_SHIFT_SIFS_OFDM_TRX_8822C 24 +#define BIT_MASK_SIFS_OFDM_TRX_8822C 0xff +#define BIT_SIFS_OFDM_TRX_8822C(x) \ + (((x) & BIT_MASK_SIFS_OFDM_TRX_8822C) << BIT_SHIFT_SIFS_OFDM_TRX_8822C) +#define BITS_SIFS_OFDM_TRX_8822C \ + (BIT_MASK_SIFS_OFDM_TRX_8822C << BIT_SHIFT_SIFS_OFDM_TRX_8822C) +#define BIT_CLEAR_SIFS_OFDM_TRX_8822C(x) ((x) & (~BITS_SIFS_OFDM_TRX_8822C)) +#define BIT_GET_SIFS_OFDM_TRX_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822C) & BIT_MASK_SIFS_OFDM_TRX_8822C) +#define BIT_SET_SIFS_OFDM_TRX_8822C(x, v) \ + (BIT_CLEAR_SIFS_OFDM_TRX_8822C(x) | BIT_SIFS_OFDM_TRX_8822C(v)) + +#define BIT_SHIFT_SIFS_CCK_TRX_8822C 16 +#define BIT_MASK_SIFS_CCK_TRX_8822C 0xff +#define BIT_SIFS_CCK_TRX_8822C(x) \ + (((x) & BIT_MASK_SIFS_CCK_TRX_8822C) << BIT_SHIFT_SIFS_CCK_TRX_8822C) +#define BITS_SIFS_CCK_TRX_8822C \ + (BIT_MASK_SIFS_CCK_TRX_8822C << BIT_SHIFT_SIFS_CCK_TRX_8822C) +#define BIT_CLEAR_SIFS_CCK_TRX_8822C(x) ((x) & (~BITS_SIFS_CCK_TRX_8822C)) +#define BIT_GET_SIFS_CCK_TRX_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822C) & BIT_MASK_SIFS_CCK_TRX_8822C) +#define BIT_SET_SIFS_CCK_TRX_8822C(x, v) \ + (BIT_CLEAR_SIFS_CCK_TRX_8822C(x) | BIT_SIFS_CCK_TRX_8822C(v)) + +#define BIT_SHIFT_SIFS_OFDM_CTX_8822C 8 +#define BIT_MASK_SIFS_OFDM_CTX_8822C 0xff +#define BIT_SIFS_OFDM_CTX_8822C(x) \ + (((x) & BIT_MASK_SIFS_OFDM_CTX_8822C) << BIT_SHIFT_SIFS_OFDM_CTX_8822C) +#define BITS_SIFS_OFDM_CTX_8822C \ + (BIT_MASK_SIFS_OFDM_CTX_8822C << BIT_SHIFT_SIFS_OFDM_CTX_8822C) +#define BIT_CLEAR_SIFS_OFDM_CTX_8822C(x) ((x) & (~BITS_SIFS_OFDM_CTX_8822C)) +#define BIT_GET_SIFS_OFDM_CTX_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822C) & BIT_MASK_SIFS_OFDM_CTX_8822C) +#define BIT_SET_SIFS_OFDM_CTX_8822C(x, v) \ + (BIT_CLEAR_SIFS_OFDM_CTX_8822C(x) | BIT_SIFS_OFDM_CTX_8822C(v)) + +#define BIT_SHIFT_SIFS_CCK_CTX_8822C 0 +#define BIT_MASK_SIFS_CCK_CTX_8822C 0xff +#define BIT_SIFS_CCK_CTX_8822C(x) \ + (((x) & BIT_MASK_SIFS_CCK_CTX_8822C) << BIT_SHIFT_SIFS_CCK_CTX_8822C) +#define BITS_SIFS_CCK_CTX_8822C \ + (BIT_MASK_SIFS_CCK_CTX_8822C << BIT_SHIFT_SIFS_CCK_CTX_8822C) +#define BIT_CLEAR_SIFS_CCK_CTX_8822C(x) ((x) & (~BITS_SIFS_CCK_CTX_8822C)) +#define BIT_GET_SIFS_CCK_CTX_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822C) & BIT_MASK_SIFS_CCK_CTX_8822C) +#define BIT_SET_SIFS_CCK_CTX_8822C(x, v) \ + (BIT_CLEAR_SIFS_CCK_CTX_8822C(x) | BIT_SIFS_CCK_CTX_8822C(v)) + +/* 2 REG_TSFTR_SYN_OFFSET_8822C */ + +#define BIT_SHIFT_TSFTR_SNC_OFFSET_8822C 0 +#define BIT_MASK_TSFTR_SNC_OFFSET_8822C 0xffff +#define BIT_TSFTR_SNC_OFFSET_8822C(x) \ + (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822C) \ + << BIT_SHIFT_TSFTR_SNC_OFFSET_8822C) +#define BITS_TSFTR_SNC_OFFSET_8822C \ + (BIT_MASK_TSFTR_SNC_OFFSET_8822C << BIT_SHIFT_TSFTR_SNC_OFFSET_8822C) +#define BIT_CLEAR_TSFTR_SNC_OFFSET_8822C(x) \ + ((x) & (~BITS_TSFTR_SNC_OFFSET_8822C)) +#define BIT_GET_TSFTR_SNC_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822C) & \ + BIT_MASK_TSFTR_SNC_OFFSET_8822C) +#define BIT_SET_TSFTR_SNC_OFFSET_8822C(x, v) \ + (BIT_CLEAR_TSFTR_SNC_OFFSET_8822C(x) | BIT_TSFTR_SNC_OFFSET_8822C(v)) + +/* 2 REG_AGGR_BREAK_TIME_8822C */ + +#define BIT_SHIFT_AGGR_BK_TIME_8822C 0 +#define BIT_MASK_AGGR_BK_TIME_8822C 0xff +#define BIT_AGGR_BK_TIME_8822C(x) \ + (((x) & BIT_MASK_AGGR_BK_TIME_8822C) << BIT_SHIFT_AGGR_BK_TIME_8822C) +#define BITS_AGGR_BK_TIME_8822C \ + (BIT_MASK_AGGR_BK_TIME_8822C << BIT_SHIFT_AGGR_BK_TIME_8822C) +#define BIT_CLEAR_AGGR_BK_TIME_8822C(x) ((x) & (~BITS_AGGR_BK_TIME_8822C)) +#define BIT_GET_AGGR_BK_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_AGGR_BK_TIME_8822C) & BIT_MASK_AGGR_BK_TIME_8822C) +#define BIT_SET_AGGR_BK_TIME_8822C(x, v) \ + (BIT_CLEAR_AGGR_BK_TIME_8822C(x) | BIT_AGGR_BK_TIME_8822C(v)) + +/* 2 REG_SLOT_8822C */ + +#define BIT_SHIFT_SLOT_8822C 0 +#define BIT_MASK_SLOT_8822C 0xff +#define BIT_SLOT_8822C(x) (((x) & BIT_MASK_SLOT_8822C) << BIT_SHIFT_SLOT_8822C) +#define BITS_SLOT_8822C (BIT_MASK_SLOT_8822C << BIT_SHIFT_SLOT_8822C) +#define BIT_CLEAR_SLOT_8822C(x) ((x) & (~BITS_SLOT_8822C)) +#define BIT_GET_SLOT_8822C(x) \ + (((x) >> BIT_SHIFT_SLOT_8822C) & BIT_MASK_SLOT_8822C) +#define BIT_SET_SLOT_8822C(x, v) (BIT_CLEAR_SLOT_8822C(x) | BIT_SLOT_8822C(v)) + +/* 2 REG_NOA_ON_ERLY_TIME_8822C */ + +#define BIT_SHIFT__NOA_ON_ERLY_TIME_8822C 0 +#define BIT_MASK__NOA_ON_ERLY_TIME_8822C 0xff +#define BIT__NOA_ON_ERLY_TIME_8822C(x) \ + (((x) & BIT_MASK__NOA_ON_ERLY_TIME_8822C) \ + << BIT_SHIFT__NOA_ON_ERLY_TIME_8822C) +#define BITS__NOA_ON_ERLY_TIME_8822C \ + (BIT_MASK__NOA_ON_ERLY_TIME_8822C << BIT_SHIFT__NOA_ON_ERLY_TIME_8822C) +#define BIT_CLEAR__NOA_ON_ERLY_TIME_8822C(x) \ + ((x) & (~BITS__NOA_ON_ERLY_TIME_8822C)) +#define BIT_GET__NOA_ON_ERLY_TIME_8822C(x) \ + (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8822C) & \ + BIT_MASK__NOA_ON_ERLY_TIME_8822C) +#define BIT_SET__NOA_ON_ERLY_TIME_8822C(x, v) \ + (BIT_CLEAR__NOA_ON_ERLY_TIME_8822C(x) | BIT__NOA_ON_ERLY_TIME_8822C(v)) + +/* 2 REG_NOA_OFF_ERLY_TIME_8822C */ + +#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C 0 +#define BIT_MASK__NOA_OFF_ERLY_TIME_8822C 0xff +#define BIT__NOA_OFF_ERLY_TIME_8822C(x) \ + (((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8822C) \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C) +#define BITS__NOA_OFF_ERLY_TIME_8822C \ + (BIT_MASK__NOA_OFF_ERLY_TIME_8822C \ + << BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C) +#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8822C(x) \ + ((x) & (~BITS__NOA_OFF_ERLY_TIME_8822C)) +#define BIT_GET__NOA_OFF_ERLY_TIME_8822C(x) \ + (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C) & \ + BIT_MASK__NOA_OFF_ERLY_TIME_8822C) +#define BIT_SET__NOA_OFF_ERLY_TIME_8822C(x, v) \ + (BIT_CLEAR__NOA_OFF_ERLY_TIME_8822C(x) | \ + BIT__NOA_OFF_ERLY_TIME_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_TX_PTCL_CTRL_8822C */ +#define BIT_DIS_EDCCA_8822C BIT(15) +#define BIT_DIS_CCA_8822C BIT(14) +#define BIT_LSIG_TXOP_TXCMD_NAV_8822C BIT(13) +#define BIT_SIFS_BK_EN_8822C BIT(12) + +#define BIT_SHIFT_TXQ_NAV_MSK_8822C 8 +#define BIT_MASK_TXQ_NAV_MSK_8822C 0xf +#define BIT_TXQ_NAV_MSK_8822C(x) \ + (((x) & BIT_MASK_TXQ_NAV_MSK_8822C) << BIT_SHIFT_TXQ_NAV_MSK_8822C) +#define BITS_TXQ_NAV_MSK_8822C \ + (BIT_MASK_TXQ_NAV_MSK_8822C << BIT_SHIFT_TXQ_NAV_MSK_8822C) +#define BIT_CLEAR_TXQ_NAV_MSK_8822C(x) ((x) & (~BITS_TXQ_NAV_MSK_8822C)) +#define BIT_GET_TXQ_NAV_MSK_8822C(x) \ + (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822C) & BIT_MASK_TXQ_NAV_MSK_8822C) +#define BIT_SET_TXQ_NAV_MSK_8822C(x, v) \ + (BIT_CLEAR_TXQ_NAV_MSK_8822C(x) | BIT_TXQ_NAV_MSK_8822C(v)) + +#define BIT_DIS_CW_8822C BIT(7) +#define BIT_NAV_END_TXOP_8822C BIT(6) +#define BIT_RDG_END_TXOP_8822C BIT(5) +#define BIT_AC_INBCN_HOLD_8822C BIT(4) +#define BIT_MGTQ_TXOP_EN_8822C BIT(3) +#define BIT_MGTQ_RTSMF_EN_8822C BIT(2) +#define BIT_HIQ_RTSMF_EN_8822C BIT(1) +#define BIT_BCN_RTSMF_EN_8822C BIT(0) + +/* 2 REG_TXPAUSE_8822C */ +#define BIT_STOP_BCN_HI_MGT_8822C BIT(7) +#define BIT_MAC_STOPBCNQ_8822C BIT(6) +#define BIT_MAC_STOPHIQ_8822C BIT(5) +#define BIT_MAC_STOPMGQ_8822C BIT(4) +#define BIT_MAC_STOPBK_8822C BIT(3) +#define BIT_MAC_STOPBE_8822C BIT(2) +#define BIT_MAC_STOPVI_8822C BIT(1) +#define BIT_MAC_STOPVO_8822C BIT(0) + +/* 2 REG_DIS_TXREQ_CLR_8822C */ +#define BIT_DIS_BT_CCA_8822C BIT(7) +#define BIT_DIS_TXREQ_CLR_HI_8822C BIT(5) +#define BIT_DIS_TXREQ_CLR_MGQ_8822C BIT(4) +#define BIT_DIS_TXREQ_CLR_VO_8822C BIT(3) +#define BIT_DIS_TXREQ_CLR_VI_8822C BIT(2) +#define BIT_DIS_TXREQ_CLR_BE_8822C BIT(1) +#define BIT_DIS_TXREQ_CLR_BK_8822C BIT(0) + +/* 2 REG_RD_CTRL_8822C */ +#define BIT_EN_CLR_TXREQ_INCCA_8822C BIT(15) +#define BIT_DIS_TX_OVER_BCNQ_8822C BIT(14) +#define BIT_EN_BCNERR_INCCCA_8822C BIT(13) +#define BIT_EDCCA_MSK_CNTDOWN_EN_8822C BIT(11) +#define BIT_DIS_TXOP_CFE_8822C BIT(10) +#define BIT_DIS_LSIG_CFE_8822C BIT(9) +#define BIT_DIS_STBC_CFE_8822C BIT(8) +#define BIT_BKQ_RD_INIT_EN_8822C BIT(7) +#define BIT_BEQ_RD_INIT_EN_8822C BIT(6) +#define BIT_VIQ_RD_INIT_EN_8822C BIT(5) +#define BIT_VOQ_RD_INIT_EN_8822C BIT(4) +#define BIT_BKQ_RD_RESP_EN_8822C BIT(3) +#define BIT_BEQ_RD_RESP_EN_8822C BIT(2) +#define BIT_VIQ_RD_RESP_EN_8822C BIT(1) +#define BIT_VOQ_RD_RESP_EN_8822C BIT(0) + +/* 2 REG_MBSSID_CTRL_8822C */ +#define BIT_MBID_BCNQ7_EN_8822C BIT(7) +#define BIT_MBID_BCNQ6_EN_8822C BIT(6) +#define BIT_MBID_BCNQ5_EN_8822C BIT(5) +#define BIT_MBID_BCNQ4_EN_8822C BIT(4) +#define BIT_MBID_BCNQ3_EN_8822C BIT(3) +#define BIT_MBID_BCNQ2_EN_8822C BIT(2) +#define BIT_MBID_BCNQ1_EN_8822C BIT(1) +#define BIT_MBID_BCNQ0_EN_8822C BIT(0) + +/* 2 REG_P2PPS_CTRL_8822C */ +#define BIT_P2P_CTW_ALLSTASLEEP_8822C BIT(7) +#define BIT_P2P_OFF_DISTX_EN_8822C BIT(6) +#define BIT_PWR_MGT_EN_8822C BIT(5) +#define BIT_P2P_NOA1_EN_8822C BIT(2) +#define BIT_P2P_NOA0_EN_8822C BIT(1) + +/* 2 REG_PKT_LIFETIME_CTRL_8822C */ +#define BIT_EN_P2P_CTWND1_8822C BIT(23) +#define BIT_EN_BKF_CLR_TXREQ_8822C BIT(22) +#define BIT_EN_TSFBIT32_RST_P2P_8822C BIT(21) +#define BIT_EN_BCN_TX_BTCCA_8822C BIT(20) +#define BIT_DIS_PKT_TX_ATIM_8822C BIT(19) +#define BIT_DIS_BCN_DIS_CTN_8822C BIT(18) +#define BIT_EN_NAVEND_RST_TXOP_8822C BIT(17) +#define BIT_EN_FILTER_CCA_8822C BIT(16) + +#define BIT_SHIFT_CCA_FILTER_THRS_8822C 8 +#define BIT_MASK_CCA_FILTER_THRS_8822C 0xff +#define BIT_CCA_FILTER_THRS_8822C(x) \ + (((x) & BIT_MASK_CCA_FILTER_THRS_8822C) \ + << BIT_SHIFT_CCA_FILTER_THRS_8822C) +#define BITS_CCA_FILTER_THRS_8822C \ + (BIT_MASK_CCA_FILTER_THRS_8822C << BIT_SHIFT_CCA_FILTER_THRS_8822C) +#define BIT_CLEAR_CCA_FILTER_THRS_8822C(x) ((x) & (~BITS_CCA_FILTER_THRS_8822C)) +#define BIT_GET_CCA_FILTER_THRS_8822C(x) \ + (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822C) & \ + BIT_MASK_CCA_FILTER_THRS_8822C) +#define BIT_SET_CCA_FILTER_THRS_8822C(x, v) \ + (BIT_CLEAR_CCA_FILTER_THRS_8822C(x) | BIT_CCA_FILTER_THRS_8822C(v)) + +#define BIT_SHIFT_EDCCA_THRS_8822C 0 +#define BIT_MASK_EDCCA_THRS_8822C 0xff +#define BIT_EDCCA_THRS_8822C(x) \ + (((x) & BIT_MASK_EDCCA_THRS_8822C) << BIT_SHIFT_EDCCA_THRS_8822C) +#define BITS_EDCCA_THRS_8822C \ + (BIT_MASK_EDCCA_THRS_8822C << BIT_SHIFT_EDCCA_THRS_8822C) +#define BIT_CLEAR_EDCCA_THRS_8822C(x) ((x) & (~BITS_EDCCA_THRS_8822C)) +#define BIT_GET_EDCCA_THRS_8822C(x) \ + (((x) >> BIT_SHIFT_EDCCA_THRS_8822C) & BIT_MASK_EDCCA_THRS_8822C) +#define BIT_SET_EDCCA_THRS_8822C(x, v) \ + (BIT_CLEAR_EDCCA_THRS_8822C(x) | BIT_EDCCA_THRS_8822C(v)) + +/* 2 REG_P2PPS_SPEC_STATE_8822C */ +#define BIT_SPEC_POWER_STATE_8822C BIT(7) +#define BIT_SPEC_CTWINDOW_ON_8822C BIT(6) +#define BIT_SPEC_BEACON_AREA_ON_8822C BIT(5) +#define BIT_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_SPEC_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_SPEC_FORCE_DOZE1_8822C BIT(2) +#define BIT_SPEC_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_SPEC_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_TXOP_LIMIT_CTRL_8822C */ + +#define BIT_SHIFT_TXOP_TBTT_CNT_8822C 24 +#define BIT_MASK_TXOP_TBTT_CNT_8822C 0xff +#define BIT_TXOP_TBTT_CNT_8822C(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_8822C) << BIT_SHIFT_TXOP_TBTT_CNT_8822C) +#define BITS_TXOP_TBTT_CNT_8822C \ + (BIT_MASK_TXOP_TBTT_CNT_8822C << BIT_SHIFT_TXOP_TBTT_CNT_8822C) +#define BIT_CLEAR_TXOP_TBTT_CNT_8822C(x) ((x) & (~BITS_TXOP_TBTT_CNT_8822C)) +#define BIT_GET_TXOP_TBTT_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8822C) & BIT_MASK_TXOP_TBTT_CNT_8822C) +#define BIT_SET_TXOP_TBTT_CNT_8822C(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_8822C(x) | BIT_TXOP_TBTT_CNT_8822C(v)) + +#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C 20 +#define BIT_MASK_TXOP_TBTT_CNT_SEL_8822C 0xf +#define BIT_TXOP_TBTT_CNT_SEL_8822C(x) \ + (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8822C) \ + << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C) +#define BITS_TXOP_TBTT_CNT_SEL_8822C \ + (BIT_MASK_TXOP_TBTT_CNT_SEL_8822C << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C) +#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822C(x) \ + ((x) & (~BITS_TXOP_TBTT_CNT_SEL_8822C)) +#define BIT_GET_TXOP_TBTT_CNT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C) & \ + BIT_MASK_TXOP_TBTT_CNT_SEL_8822C) +#define BIT_SET_TXOP_TBTT_CNT_SEL_8822C(x, v) \ + (BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822C(x) | BIT_TXOP_TBTT_CNT_SEL_8822C(v)) + +#define BIT_SHIFT_TXOP_LMT_EN_8822C 16 +#define BIT_MASK_TXOP_LMT_EN_8822C 0xf +#define BIT_TXOP_LMT_EN_8822C(x) \ + (((x) & BIT_MASK_TXOP_LMT_EN_8822C) << BIT_SHIFT_TXOP_LMT_EN_8822C) +#define BITS_TXOP_LMT_EN_8822C \ + (BIT_MASK_TXOP_LMT_EN_8822C << BIT_SHIFT_TXOP_LMT_EN_8822C) +#define BIT_CLEAR_TXOP_LMT_EN_8822C(x) ((x) & (~BITS_TXOP_LMT_EN_8822C)) +#define BIT_GET_TXOP_LMT_EN_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_EN_8822C) & BIT_MASK_TXOP_LMT_EN_8822C) +#define BIT_SET_TXOP_LMT_EN_8822C(x, v) \ + (BIT_CLEAR_TXOP_LMT_EN_8822C(x) | BIT_TXOP_LMT_EN_8822C(v)) + +#define BIT_SHIFT_TXOP_LMT_TX_TIME_8822C 8 +#define BIT_MASK_TXOP_LMT_TX_TIME_8822C 0xff +#define BIT_TXOP_LMT_TX_TIME_8822C(x) \ + (((x) & BIT_MASK_TXOP_LMT_TX_TIME_8822C) \ + << BIT_SHIFT_TXOP_LMT_TX_TIME_8822C) +#define BITS_TXOP_LMT_TX_TIME_8822C \ + (BIT_MASK_TXOP_LMT_TX_TIME_8822C << BIT_SHIFT_TXOP_LMT_TX_TIME_8822C) +#define BIT_CLEAR_TXOP_LMT_TX_TIME_8822C(x) \ + ((x) & (~BITS_TXOP_LMT_TX_TIME_8822C)) +#define BIT_GET_TXOP_LMT_TX_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8822C) & \ + BIT_MASK_TXOP_LMT_TX_TIME_8822C) +#define BIT_SET_TXOP_LMT_TX_TIME_8822C(x, v) \ + (BIT_CLEAR_TXOP_LMT_TX_TIME_8822C(x) | BIT_TXOP_LMT_TX_TIME_8822C(v)) + +#define BIT_TXOP_CNT_TRIGGER_RESET_8822C BIT(7) + +#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C 0 +#define BIT_MASK_TXOP_LMT_PKT_NUM_8822C 0x3f +#define BIT_TXOP_LMT_PKT_NUM_8822C(x) \ + (((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8822C) \ + << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C) +#define BITS_TXOP_LMT_PKT_NUM_8822C \ + (BIT_MASK_TXOP_LMT_PKT_NUM_8822C << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C) +#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8822C(x) \ + ((x) & (~BITS_TXOP_LMT_PKT_NUM_8822C)) +#define BIT_GET_TXOP_LMT_PKT_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C) & \ + BIT_MASK_TXOP_LMT_PKT_NUM_8822C) +#define BIT_SET_TXOP_LMT_PKT_NUM_8822C(x, v) \ + (BIT_CLEAR_TXOP_LMT_PKT_NUM_8822C(x) | BIT_TXOP_LMT_PKT_NUM_8822C(v)) + +/* 2 REG_BAR_TX_CTRL_8822C */ + +/* 2 REG_P2PON_DIS_TXTIME_8822C */ + +#define BIT_SHIFT_P2PON_DIS_TXTIME_8822C 0 +#define BIT_MASK_P2PON_DIS_TXTIME_8822C 0xff +#define BIT_P2PON_DIS_TXTIME_8822C(x) \ + (((x) & BIT_MASK_P2PON_DIS_TXTIME_8822C) \ + << BIT_SHIFT_P2PON_DIS_TXTIME_8822C) +#define BITS_P2PON_DIS_TXTIME_8822C \ + (BIT_MASK_P2PON_DIS_TXTIME_8822C << BIT_SHIFT_P2PON_DIS_TXTIME_8822C) +#define BIT_CLEAR_P2PON_DIS_TXTIME_8822C(x) \ + ((x) & (~BITS_P2PON_DIS_TXTIME_8822C)) +#define BIT_GET_P2PON_DIS_TXTIME_8822C(x) \ + (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822C) & \ + BIT_MASK_P2PON_DIS_TXTIME_8822C) +#define BIT_SET_P2PON_DIS_TXTIME_8822C(x, v) \ + (BIT_CLEAR_P2PON_DIS_TXTIME_8822C(x) | BIT_P2PON_DIS_TXTIME_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_CCA_TXEN_CNT_8822C */ +#define BIT_ENABLE_STOP_UPDATE_NAV_8822C BIT(21) +#define BIT_ENABLE_GEN_RANDON_SLOT_TX_8822C BIT(20) +#define BIT_ENABLE_RANDOM_SHIFT_TX_8822C BIT(19) +#define BIT_ENABLE_EDCA_REF_FUNCTION_8822C BIT(18) +#define BIT_CCA_TXEN_CNT_SWITCH_8822C BIT(17) +#define BIT_CCA_TXEN_CNT_EN_8822C BIT(16) + +#define BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C 8 +#define BIT_MASK_CCA_TXEN_BIG_CNT_8822C 0xff +#define BIT_CCA_TXEN_BIG_CNT_8822C(x) \ + (((x) & BIT_MASK_CCA_TXEN_BIG_CNT_8822C) \ + << BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C) +#define BITS_CCA_TXEN_BIG_CNT_8822C \ + (BIT_MASK_CCA_TXEN_BIG_CNT_8822C << BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C) +#define BIT_CLEAR_CCA_TXEN_BIG_CNT_8822C(x) \ + ((x) & (~BITS_CCA_TXEN_BIG_CNT_8822C)) +#define BIT_GET_CCA_TXEN_BIG_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C) & \ + BIT_MASK_CCA_TXEN_BIG_CNT_8822C) +#define BIT_SET_CCA_TXEN_BIG_CNT_8822C(x, v) \ + (BIT_CLEAR_CCA_TXEN_BIG_CNT_8822C(x) | BIT_CCA_TXEN_BIG_CNT_8822C(v)) + +#define BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C 0 +#define BIT_MASK_CCA_TXEN_SMALL_CNT_8822C 0xff +#define BIT_CCA_TXEN_SMALL_CNT_8822C(x) \ + (((x) & BIT_MASK_CCA_TXEN_SMALL_CNT_8822C) \ + << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C) +#define BITS_CCA_TXEN_SMALL_CNT_8822C \ + (BIT_MASK_CCA_TXEN_SMALL_CNT_8822C \ + << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C) +#define BIT_CLEAR_CCA_TXEN_SMALL_CNT_8822C(x) \ + ((x) & (~BITS_CCA_TXEN_SMALL_CNT_8822C)) +#define BIT_GET_CCA_TXEN_SMALL_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C) & \ + BIT_MASK_CCA_TXEN_SMALL_CNT_8822C) +#define BIT_SET_CCA_TXEN_SMALL_CNT_8822C(x, v) \ + (BIT_CLEAR_CCA_TXEN_SMALL_CNT_8822C(x) | \ + BIT_CCA_TXEN_SMALL_CNT_8822C(v)) + +/* 2 REG_MAX_INTER_COLLISION_8822C */ + +#define BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C 24 +#define BIT_MASK_MAX_INTER_COLLISION_BK_8822C 0xff +#define BIT_MAX_INTER_COLLISION_BK_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BK_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C) +#define BITS_MAX_INTER_COLLISION_BK_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_BK_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_BK_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BK_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_BK_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_BK_8822C) +#define BIT_SET_MAX_INTER_COLLISION_BK_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BK_8822C(x) | \ + BIT_MAX_INTER_COLLISION_BK_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C 16 +#define BIT_MASK_MAX_INTER_COLLISION_BE_8822C 0xff +#define BIT_MAX_INTER_COLLISION_BE_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_BE_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C) +#define BITS_MAX_INTER_COLLISION_BE_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_BE_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_BE_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_BE_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_BE_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_BE_8822C) +#define BIT_SET_MAX_INTER_COLLISION_BE_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_BE_8822C(x) | \ + BIT_MAX_INTER_COLLISION_BE_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C 8 +#define BIT_MASK_MAX_INTER_COLLISION_VI_8822C 0xff +#define BIT_MAX_INTER_COLLISION_VI_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VI_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C) +#define BITS_MAX_INTER_COLLISION_VI_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_VI_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_VI_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VI_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_VI_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_VI_8822C) +#define BIT_SET_MAX_INTER_COLLISION_VI_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VI_8822C(x) | \ + BIT_MAX_INTER_COLLISION_VI_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C 0 +#define BIT_MASK_MAX_INTER_COLLISION_VO_8822C 0xff +#define BIT_MAX_INTER_COLLISION_VO_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_VO_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C) +#define BITS_MAX_INTER_COLLISION_VO_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_VO_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_VO_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_VO_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_VO_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_VO_8822C) +#define BIT_SET_MAX_INTER_COLLISION_VO_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_VO_8822C(x) | \ + BIT_MAX_INTER_COLLISION_VO_8822C(v)) + +/* 2 REG_MAX_INTER_COLLISION_CNT_8822C */ +#define BIT_MAX_INTER_COLLISION_EN_8822C BIT(16) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C 12 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BK_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C) +#define BITS_MAX_INTER_COLLISION_CNT_BK_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BK_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BK_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8822C(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BK_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C 8 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C 0xf +#define BIT_MAX_INTER_COLLISION_CNT_BE_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C) +#define BITS_MAX_INTER_COLLISION_CNT_BE_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_BE_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C) +#define BIT_SET_MAX_INTER_COLLISION_CNT_BE_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8822C(x) | \ + BIT_MAX_INTER_COLLISION_CNT_BE_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C 4 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VI_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C) +#define BITS_MAX_INTER_COLLISION_CNT_VI_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VI_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VI_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8822C(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VI_8822C(v)) + +#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C 0 +#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C 0xf +#define BIT_MAX_INTER_COLLISION_CNT_VO_8822C(x) \ + (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C) \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C) +#define BITS_MAX_INTER_COLLISION_CNT_VO_8822C \ + (BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C \ + << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C) +#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8822C(x) \ + ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO_8822C)) +#define BIT_GET_MAX_INTER_COLLISION_CNT_VO_8822C(x) \ + (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C) & \ + BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C) +#define BIT_SET_MAX_INTER_COLLISION_CNT_VO_8822C(x, v) \ + (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8822C(x) | \ + BIT_MAX_INTER_COLLISION_CNT_VO_8822C(v)) + +/* 2 REG_TBTT_PROHIBIT_8822C */ + +#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C 8 +#define BIT_MASK_TBTT_HOLD_TIME_AP_8822C 0xfff +#define BIT_TBTT_HOLD_TIME_AP_8822C(x) \ + (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822C) \ + << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C) +#define BITS_TBTT_HOLD_TIME_AP_8822C \ + (BIT_MASK_TBTT_HOLD_TIME_AP_8822C << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C) +#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8822C(x) \ + ((x) & (~BITS_TBTT_HOLD_TIME_AP_8822C)) +#define BIT_GET_TBTT_HOLD_TIME_AP_8822C(x) \ + (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C) & \ + BIT_MASK_TBTT_HOLD_TIME_AP_8822C) +#define BIT_SET_TBTT_HOLD_TIME_AP_8822C(x, v) \ + (BIT_CLEAR_TBTT_HOLD_TIME_AP_8822C(x) | BIT_TBTT_HOLD_TIME_AP_8822C(v)) + +#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C 0 +#define BIT_MASK_TBTT_PROHIBIT_SETUP_8822C 0xf +#define BIT_TBTT_PROHIBIT_SETUP_8822C(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822C) \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C) +#define BITS_TBTT_PROHIBIT_SETUP_8822C \ + (BIT_MASK_TBTT_PROHIBIT_SETUP_8822C \ + << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C) +#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822C(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8822C)) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8822C(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C) & \ + BIT_MASK_TBTT_PROHIBIT_SETUP_8822C) +#define BIT_SET_TBTT_PROHIBIT_SETUP_8822C(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822C(x) | \ + BIT_TBTT_PROHIBIT_SETUP_8822C(v)) + +/* 2 REG_P2PPS_STATE_8822C */ +#define BIT_POWER_STATE_8822C BIT(7) +#define BIT_CTWINDOW_ON_8822C BIT(6) +#define BIT_BEACON_AREA_ON_8822C BIT(5) +#define BIT_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_FORCE_DOZE1_8822C BIT(2) +#define BIT_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_RD_NAV_NXT_8822C */ + +#define BIT_SHIFT_RD_NAV_PROT_NXT_8822C 0 +#define BIT_MASK_RD_NAV_PROT_NXT_8822C 0xffff +#define BIT_RD_NAV_PROT_NXT_8822C(x) \ + (((x) & BIT_MASK_RD_NAV_PROT_NXT_8822C) \ + << BIT_SHIFT_RD_NAV_PROT_NXT_8822C) +#define BITS_RD_NAV_PROT_NXT_8822C \ + (BIT_MASK_RD_NAV_PROT_NXT_8822C << BIT_SHIFT_RD_NAV_PROT_NXT_8822C) +#define BIT_CLEAR_RD_NAV_PROT_NXT_8822C(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8822C)) +#define BIT_GET_RD_NAV_PROT_NXT_8822C(x) \ + (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822C) & \ + BIT_MASK_RD_NAV_PROT_NXT_8822C) +#define BIT_SET_RD_NAV_PROT_NXT_8822C(x, v) \ + (BIT_CLEAR_RD_NAV_PROT_NXT_8822C(x) | BIT_RD_NAV_PROT_NXT_8822C(v)) + +/* 2 REG_NAV_PROT_LEN_8822C */ + +#define BIT_SHIFT_NAV_PROT_LEN_8822C 0 +#define BIT_MASK_NAV_PROT_LEN_8822C 0xffff +#define BIT_NAV_PROT_LEN_8822C(x) \ + (((x) & BIT_MASK_NAV_PROT_LEN_8822C) << BIT_SHIFT_NAV_PROT_LEN_8822C) +#define BITS_NAV_PROT_LEN_8822C \ + (BIT_MASK_NAV_PROT_LEN_8822C << BIT_SHIFT_NAV_PROT_LEN_8822C) +#define BIT_CLEAR_NAV_PROT_LEN_8822C(x) ((x) & (~BITS_NAV_PROT_LEN_8822C)) +#define BIT_GET_NAV_PROT_LEN_8822C(x) \ + (((x) >> BIT_SHIFT_NAV_PROT_LEN_8822C) & BIT_MASK_NAV_PROT_LEN_8822C) +#define BIT_SET_NAV_PROT_LEN_8822C(x, v) \ + (BIT_CLEAR_NAV_PROT_LEN_8822C(x) | BIT_NAV_PROT_LEN_8822C(v)) + +/* 2 REG_FTM_PTT_8822C */ + +#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C 22 +#define BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C 0x7 +#define BIT_FTM_PTT_TSF_R2T_SEL_8822C(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C) \ + << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C) +#define BITS_FTM_PTT_TSF_R2T_SEL_8822C \ + (BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C \ + << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C) +#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8822C(x) \ + ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL_8822C)) +#define BIT_GET_FTM_PTT_TSF_R2T_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C) & \ + BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C) +#define BIT_SET_FTM_PTT_TSF_R2T_SEL_8822C(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8822C(x) | \ + BIT_FTM_PTT_TSF_R2T_SEL_8822C(v)) + +#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C 19 +#define BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C 0x7 +#define BIT_FTM_PTT_TSF_T2R_SEL_8822C(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C) \ + << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C) +#define BITS_FTM_PTT_TSF_T2R_SEL_8822C \ + (BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C \ + << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C) +#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8822C(x) \ + ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL_8822C)) +#define BIT_GET_FTM_PTT_TSF_T2R_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C) & \ + BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C) +#define BIT_SET_FTM_PTT_TSF_T2R_SEL_8822C(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8822C(x) | \ + BIT_FTM_PTT_TSF_T2R_SEL_8822C(v)) + +#define BIT_SHIFT_FTM_PTT_TSF_SEL_8822C 16 +#define BIT_MASK_FTM_PTT_TSF_SEL_8822C 0x7 +#define BIT_FTM_PTT_TSF_SEL_8822C(x) \ + (((x) & BIT_MASK_FTM_PTT_TSF_SEL_8822C) \ + << BIT_SHIFT_FTM_PTT_TSF_SEL_8822C) +#define BITS_FTM_PTT_TSF_SEL_8822C \ + (BIT_MASK_FTM_PTT_TSF_SEL_8822C << BIT_SHIFT_FTM_PTT_TSF_SEL_8822C) +#define BIT_CLEAR_FTM_PTT_TSF_SEL_8822C(x) ((x) & (~BITS_FTM_PTT_TSF_SEL_8822C)) +#define BIT_GET_FTM_PTT_TSF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL_8822C) & \ + BIT_MASK_FTM_PTT_TSF_SEL_8822C) +#define BIT_SET_FTM_PTT_TSF_SEL_8822C(x, v) \ + (BIT_CLEAR_FTM_PTT_TSF_SEL_8822C(x) | BIT_FTM_PTT_TSF_SEL_8822C(v)) + +#define BIT_SHIFT_FTM_PTT_VALUE_8822C 0 +#define BIT_MASK_FTM_PTT_VALUE_8822C 0xffff +#define BIT_FTM_PTT_VALUE_8822C(x) \ + (((x) & BIT_MASK_FTM_PTT_VALUE_8822C) << BIT_SHIFT_FTM_PTT_VALUE_8822C) +#define BITS_FTM_PTT_VALUE_8822C \ + (BIT_MASK_FTM_PTT_VALUE_8822C << BIT_SHIFT_FTM_PTT_VALUE_8822C) +#define BIT_CLEAR_FTM_PTT_VALUE_8822C(x) ((x) & (~BITS_FTM_PTT_VALUE_8822C)) +#define BIT_GET_FTM_PTT_VALUE_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_PTT_VALUE_8822C) & BIT_MASK_FTM_PTT_VALUE_8822C) +#define BIT_SET_FTM_PTT_VALUE_8822C(x, v) \ + (BIT_CLEAR_FTM_PTT_VALUE_8822C(x) | BIT_FTM_PTT_VALUE_8822C(v)) + +/* 2 REG_FTM_TSF_8822C */ + +#define BIT_SHIFT_FTM_T2_TSF_8822C 16 +#define BIT_MASK_FTM_T2_TSF_8822C 0xffff +#define BIT_FTM_T2_TSF_8822C(x) \ + (((x) & BIT_MASK_FTM_T2_TSF_8822C) << BIT_SHIFT_FTM_T2_TSF_8822C) +#define BITS_FTM_T2_TSF_8822C \ + (BIT_MASK_FTM_T2_TSF_8822C << BIT_SHIFT_FTM_T2_TSF_8822C) +#define BIT_CLEAR_FTM_T2_TSF_8822C(x) ((x) & (~BITS_FTM_T2_TSF_8822C)) +#define BIT_GET_FTM_T2_TSF_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_T2_TSF_8822C) & BIT_MASK_FTM_T2_TSF_8822C) +#define BIT_SET_FTM_T2_TSF_8822C(x, v) \ + (BIT_CLEAR_FTM_T2_TSF_8822C(x) | BIT_FTM_T2_TSF_8822C(v)) + +#define BIT_SHIFT_FTM_T1_TSF_8822C 0 +#define BIT_MASK_FTM_T1_TSF_8822C 0xffff +#define BIT_FTM_T1_TSF_8822C(x) \ + (((x) & BIT_MASK_FTM_T1_TSF_8822C) << BIT_SHIFT_FTM_T1_TSF_8822C) +#define BITS_FTM_T1_TSF_8822C \ + (BIT_MASK_FTM_T1_TSF_8822C << BIT_SHIFT_FTM_T1_TSF_8822C) +#define BIT_CLEAR_FTM_T1_TSF_8822C(x) ((x) & (~BITS_FTM_T1_TSF_8822C)) +#define BIT_GET_FTM_T1_TSF_8822C(x) \ + (((x) >> BIT_SHIFT_FTM_T1_TSF_8822C) & BIT_MASK_FTM_T1_TSF_8822C) +#define BIT_SET_FTM_T1_TSF_8822C(x, v) \ + (BIT_CLEAR_FTM_T1_TSF_8822C(x) | BIT_FTM_T1_TSF_8822C(v)) + +/* 2 REG_BCN_CTRL_8822C */ +#define BIT_DIS_RX_BSSID_FIT_8822C BIT(6) +#define BIT_P0_EN_TXBCN_RPT_8822C BIT(5) +#define BIT_DIS_TSF_UDT_8822C BIT(4) +#define BIT_EN_BCN_FUNCTION_8822C BIT(3) +#define BIT_P0_EN_RXBCN_RPT_8822C BIT(2) +#define BIT_EN_P2P_CTWINDOW_8822C BIT(1) +#define BIT_EN_P2P_BCNQ_AREA_8822C BIT(0) + +/* 2 REG_BCN_CTRL_CLINT0_8822C */ +#define BIT_CLI0_DIS_RX_BSSID_FIT_8822C BIT(6) +#define BIT_CLI0_DIS_TSF_UDT_8822C BIT(4) +#define BIT_CLI0_EN_BCN_FUNCTION_8822C BIT(3) +#define BIT_CLI0_EN_RXBCN_RPT_8822C BIT(2) +#define BIT_CLI0_ENP2P_CTWINDOW_8822C BIT(1) +#define BIT_CLI0_ENP2P_BCNQ_AREA_8822C BIT(0) + +/* 2 REG_MBID_NUM_8822C */ +#define BIT_EN_PRE_DL_BEACON_8822C BIT(3) + +#define BIT_SHIFT_MBID_BCN_NUM_8822C 0 +#define BIT_MASK_MBID_BCN_NUM_8822C 0x7 +#define BIT_MBID_BCN_NUM_8822C(x) \ + (((x) & BIT_MASK_MBID_BCN_NUM_8822C) << BIT_SHIFT_MBID_BCN_NUM_8822C) +#define BITS_MBID_BCN_NUM_8822C \ + (BIT_MASK_MBID_BCN_NUM_8822C << BIT_SHIFT_MBID_BCN_NUM_8822C) +#define BIT_CLEAR_MBID_BCN_NUM_8822C(x) ((x) & (~BITS_MBID_BCN_NUM_8822C)) +#define BIT_GET_MBID_BCN_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_MBID_BCN_NUM_8822C) & BIT_MASK_MBID_BCN_NUM_8822C) +#define BIT_SET_MBID_BCN_NUM_8822C(x, v) \ + (BIT_CLEAR_MBID_BCN_NUM_8822C(x) | BIT_MBID_BCN_NUM_8822C(v)) + +/* 2 REG_DUAL_TSF_RST_8822C */ +#define BIT_FREECNT_RST_8822C BIT(5) +#define BIT_TSFTR_CLI3_RST_8822C BIT(4) +#define BIT_TSFTR_CLI2_RST_8822C BIT(3) +#define BIT_TSFTR_CLI1_RST_8822C BIT(2) +#define BIT_TSFTR_CLI0_RST_8822C BIT(1) +#define BIT_TSFTR_RST_8822C BIT(0) + +/* 2 REG_MBSSID_BCN_SPACE_8822C */ + +#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C 28 +#define BIT_MASK_BCN_TIMER_SEL_FWRD_8822C 0x7 +#define BIT_BCN_TIMER_SEL_FWRD_8822C(x) \ + (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822C) \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C) +#define BITS_BCN_TIMER_SEL_FWRD_8822C \ + (BIT_MASK_BCN_TIMER_SEL_FWRD_8822C \ + << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C) +#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822C(x) \ + ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8822C)) +#define BIT_GET_BCN_TIMER_SEL_FWRD_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C) & \ + BIT_MASK_BCN_TIMER_SEL_FWRD_8822C) +#define BIT_SET_BCN_TIMER_SEL_FWRD_8822C(x, v) \ + (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822C(x) | \ + BIT_BCN_TIMER_SEL_FWRD_8822C(v)) + +#define BIT_SHIFT_BCN_SPACE_CLINT0_8822C 16 +#define BIT_MASK_BCN_SPACE_CLINT0_8822C 0xfff +#define BIT_BCN_SPACE_CLINT0_8822C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT0_8822C) \ + << BIT_SHIFT_BCN_SPACE_CLINT0_8822C) +#define BITS_BCN_SPACE_CLINT0_8822C \ + (BIT_MASK_BCN_SPACE_CLINT0_8822C << BIT_SHIFT_BCN_SPACE_CLINT0_8822C) +#define BIT_CLEAR_BCN_SPACE_CLINT0_8822C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT0_8822C)) +#define BIT_GET_BCN_SPACE_CLINT0_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822C) & \ + BIT_MASK_BCN_SPACE_CLINT0_8822C) +#define BIT_SET_BCN_SPACE_CLINT0_8822C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT0_8822C(x) | BIT_BCN_SPACE_CLINT0_8822C(v)) + +#define BIT_SHIFT_BCN_SPACE0_8822C 0 +#define BIT_MASK_BCN_SPACE0_8822C 0xffff +#define BIT_BCN_SPACE0_8822C(x) \ + (((x) & BIT_MASK_BCN_SPACE0_8822C) << BIT_SHIFT_BCN_SPACE0_8822C) +#define BITS_BCN_SPACE0_8822C \ + (BIT_MASK_BCN_SPACE0_8822C << BIT_SHIFT_BCN_SPACE0_8822C) +#define BIT_CLEAR_BCN_SPACE0_8822C(x) ((x) & (~BITS_BCN_SPACE0_8822C)) +#define BIT_GET_BCN_SPACE0_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE0_8822C) & BIT_MASK_BCN_SPACE0_8822C) +#define BIT_SET_BCN_SPACE0_8822C(x, v) \ + (BIT_CLEAR_BCN_SPACE0_8822C(x) | BIT_BCN_SPACE0_8822C(v)) + +/* 2 REG_DRVERLYINT_8822C */ + +#define BIT_SHIFT_DRVERLYITV_8822C 0 +#define BIT_MASK_DRVERLYITV_8822C 0xff +#define BIT_DRVERLYITV_8822C(x) \ + (((x) & BIT_MASK_DRVERLYITV_8822C) << BIT_SHIFT_DRVERLYITV_8822C) +#define BITS_DRVERLYITV_8822C \ + (BIT_MASK_DRVERLYITV_8822C << BIT_SHIFT_DRVERLYITV_8822C) +#define BIT_CLEAR_DRVERLYITV_8822C(x) ((x) & (~BITS_DRVERLYITV_8822C)) +#define BIT_GET_DRVERLYITV_8822C(x) \ + (((x) >> BIT_SHIFT_DRVERLYITV_8822C) & BIT_MASK_DRVERLYITV_8822C) +#define BIT_SET_DRVERLYITV_8822C(x, v) \ + (BIT_CLEAR_DRVERLYITV_8822C(x) | BIT_DRVERLYITV_8822C(v)) + +/* 2 REG_BCNDMATIM_8822C */ + +#define BIT_SHIFT_BCNDMATIM_8822C 0 +#define BIT_MASK_BCNDMATIM_8822C 0xff +#define BIT_BCNDMATIM_8822C(x) \ + (((x) & BIT_MASK_BCNDMATIM_8822C) << BIT_SHIFT_BCNDMATIM_8822C) +#define BITS_BCNDMATIM_8822C \ + (BIT_MASK_BCNDMATIM_8822C << BIT_SHIFT_BCNDMATIM_8822C) +#define BIT_CLEAR_BCNDMATIM_8822C(x) ((x) & (~BITS_BCNDMATIM_8822C)) +#define BIT_GET_BCNDMATIM_8822C(x) \ + (((x) >> BIT_SHIFT_BCNDMATIM_8822C) & BIT_MASK_BCNDMATIM_8822C) +#define BIT_SET_BCNDMATIM_8822C(x, v) \ + (BIT_CLEAR_BCNDMATIM_8822C(x) | BIT_BCNDMATIM_8822C(v)) + +/* 2 REG_ATIMWND_8822C */ + +#define BIT_SHIFT_ATIMWND0_8822C 0 +#define BIT_MASK_ATIMWND0_8822C 0xffff +#define BIT_ATIMWND0_8822C(x) \ + (((x) & BIT_MASK_ATIMWND0_8822C) << BIT_SHIFT_ATIMWND0_8822C) +#define BITS_ATIMWND0_8822C \ + (BIT_MASK_ATIMWND0_8822C << BIT_SHIFT_ATIMWND0_8822C) +#define BIT_CLEAR_ATIMWND0_8822C(x) ((x) & (~BITS_ATIMWND0_8822C)) +#define BIT_GET_ATIMWND0_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND0_8822C) & BIT_MASK_ATIMWND0_8822C) +#define BIT_SET_ATIMWND0_8822C(x, v) \ + (BIT_CLEAR_ATIMWND0_8822C(x) | BIT_ATIMWND0_8822C(v)) + +/* 2 REG_USTIME_TSF_8822C */ + +#define BIT_SHIFT_USTIME_TSF_V1_8822C 0 +#define BIT_MASK_USTIME_TSF_V1_8822C 0xff +#define BIT_USTIME_TSF_V1_8822C(x) \ + (((x) & BIT_MASK_USTIME_TSF_V1_8822C) << BIT_SHIFT_USTIME_TSF_V1_8822C) +#define BITS_USTIME_TSF_V1_8822C \ + (BIT_MASK_USTIME_TSF_V1_8822C << BIT_SHIFT_USTIME_TSF_V1_8822C) +#define BIT_CLEAR_USTIME_TSF_V1_8822C(x) ((x) & (~BITS_USTIME_TSF_V1_8822C)) +#define BIT_GET_USTIME_TSF_V1_8822C(x) \ + (((x) >> BIT_SHIFT_USTIME_TSF_V1_8822C) & BIT_MASK_USTIME_TSF_V1_8822C) +#define BIT_SET_USTIME_TSF_V1_8822C(x, v) \ + (BIT_CLEAR_USTIME_TSF_V1_8822C(x) | BIT_USTIME_TSF_V1_8822C(v)) + +/* 2 REG_BCN_MAX_ERR_8822C */ + +#define BIT_SHIFT_BCN_MAX_ERR_8822C 0 +#define BIT_MASK_BCN_MAX_ERR_8822C 0xff +#define BIT_BCN_MAX_ERR_8822C(x) \ + (((x) & BIT_MASK_BCN_MAX_ERR_8822C) << BIT_SHIFT_BCN_MAX_ERR_8822C) +#define BITS_BCN_MAX_ERR_8822C \ + (BIT_MASK_BCN_MAX_ERR_8822C << BIT_SHIFT_BCN_MAX_ERR_8822C) +#define BIT_CLEAR_BCN_MAX_ERR_8822C(x) ((x) & (~BITS_BCN_MAX_ERR_8822C)) +#define BIT_GET_BCN_MAX_ERR_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_MAX_ERR_8822C) & BIT_MASK_BCN_MAX_ERR_8822C) +#define BIT_SET_BCN_MAX_ERR_8822C(x, v) \ + (BIT_CLEAR_BCN_MAX_ERR_8822C(x) | BIT_BCN_MAX_ERR_8822C(v)) + +/* 2 REG_RXTSF_OFFSET_CCK_8822C */ + +#define BIT_SHIFT_CCK_RXTSF_OFFSET_8822C 0 +#define BIT_MASK_CCK_RXTSF_OFFSET_8822C 0xff +#define BIT_CCK_RXTSF_OFFSET_8822C(x) \ + (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822C) \ + << BIT_SHIFT_CCK_RXTSF_OFFSET_8822C) +#define BITS_CCK_RXTSF_OFFSET_8822C \ + (BIT_MASK_CCK_RXTSF_OFFSET_8822C << BIT_SHIFT_CCK_RXTSF_OFFSET_8822C) +#define BIT_CLEAR_CCK_RXTSF_OFFSET_8822C(x) \ + ((x) & (~BITS_CCK_RXTSF_OFFSET_8822C)) +#define BIT_GET_CCK_RXTSF_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822C) & \ + BIT_MASK_CCK_RXTSF_OFFSET_8822C) +#define BIT_SET_CCK_RXTSF_OFFSET_8822C(x, v) \ + (BIT_CLEAR_CCK_RXTSF_OFFSET_8822C(x) | BIT_CCK_RXTSF_OFFSET_8822C(v)) + +/* 2 REG_RXTSF_OFFSET_OFDM_8822C */ + +#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C 0 +#define BIT_MASK_OFDM_RXTSF_OFFSET_8822C 0xff +#define BIT_OFDM_RXTSF_OFFSET_8822C(x) \ + (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822C) \ + << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C) +#define BITS_OFDM_RXTSF_OFFSET_8822C \ + (BIT_MASK_OFDM_RXTSF_OFFSET_8822C << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C) +#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8822C(x) \ + ((x) & (~BITS_OFDM_RXTSF_OFFSET_8822C)) +#define BIT_GET_OFDM_RXTSF_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C) & \ + BIT_MASK_OFDM_RXTSF_OFFSET_8822C) +#define BIT_SET_OFDM_RXTSF_OFFSET_8822C(x, v) \ + (BIT_CLEAR_OFDM_RXTSF_OFFSET_8822C(x) | BIT_OFDM_RXTSF_OFFSET_8822C(v)) + +/* 2 REG_TSFTR_8822C */ + +#define BIT_SHIFT_TSF_TIMER_V1_8822C 0 +#define BIT_MASK_TSF_TIMER_V1_8822C 0xffffffffL +#define BIT_TSF_TIMER_V1_8822C(x) \ + (((x) & BIT_MASK_TSF_TIMER_V1_8822C) << BIT_SHIFT_TSF_TIMER_V1_8822C) +#define BITS_TSF_TIMER_V1_8822C \ + (BIT_MASK_TSF_TIMER_V1_8822C << BIT_SHIFT_TSF_TIMER_V1_8822C) +#define BIT_CLEAR_TSF_TIMER_V1_8822C(x) ((x) & (~BITS_TSF_TIMER_V1_8822C)) +#define BIT_GET_TSF_TIMER_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V1_8822C) & BIT_MASK_TSF_TIMER_V1_8822C) +#define BIT_SET_TSF_TIMER_V1_8822C(x, v) \ + (BIT_CLEAR_TSF_TIMER_V1_8822C(x) | BIT_TSF_TIMER_V1_8822C(v)) + +/* 2 REG_TSFTR_1_8822C */ + +#define BIT_SHIFT_TSF_TIMER_V2_8822C 0 +#define BIT_MASK_TSF_TIMER_V2_8822C 0xffffffffL +#define BIT_TSF_TIMER_V2_8822C(x) \ + (((x) & BIT_MASK_TSF_TIMER_V2_8822C) << BIT_SHIFT_TSF_TIMER_V2_8822C) +#define BITS_TSF_TIMER_V2_8822C \ + (BIT_MASK_TSF_TIMER_V2_8822C << BIT_SHIFT_TSF_TIMER_V2_8822C) +#define BIT_CLEAR_TSF_TIMER_V2_8822C(x) ((x) & (~BITS_TSF_TIMER_V2_8822C)) +#define BIT_GET_TSF_TIMER_V2_8822C(x) \ + (((x) >> BIT_SHIFT_TSF_TIMER_V2_8822C) & BIT_MASK_TSF_TIMER_V2_8822C) +#define BIT_SET_TSF_TIMER_V2_8822C(x, v) \ + (BIT_CLEAR_TSF_TIMER_V2_8822C(x) | BIT_TSF_TIMER_V2_8822C(v)) + +/* 2 REG_FREERUN_CNT_8822C */ + +#define BIT_SHIFT_FREERUN_CNT_V1_8822C 0 +#define BIT_MASK_FREERUN_CNT_V1_8822C 0xffffffffL +#define BIT_FREERUN_CNT_V1_8822C(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V1_8822C) \ + << BIT_SHIFT_FREERUN_CNT_V1_8822C) +#define BITS_FREERUN_CNT_V1_8822C \ + (BIT_MASK_FREERUN_CNT_V1_8822C << BIT_SHIFT_FREERUN_CNT_V1_8822C) +#define BIT_CLEAR_FREERUN_CNT_V1_8822C(x) ((x) & (~BITS_FREERUN_CNT_V1_8822C)) +#define BIT_GET_FREERUN_CNT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8822C) & \ + BIT_MASK_FREERUN_CNT_V1_8822C) +#define BIT_SET_FREERUN_CNT_V1_8822C(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V1_8822C(x) | BIT_FREERUN_CNT_V1_8822C(v)) + +/* 2 REG_FREERUN_CNT_1_8822C */ + +#define BIT_SHIFT_FREERUN_CNT_V2_8822C 0 +#define BIT_MASK_FREERUN_CNT_V2_8822C 0xffffffffL +#define BIT_FREERUN_CNT_V2_8822C(x) \ + (((x) & BIT_MASK_FREERUN_CNT_V2_8822C) \ + << BIT_SHIFT_FREERUN_CNT_V2_8822C) +#define BITS_FREERUN_CNT_V2_8822C \ + (BIT_MASK_FREERUN_CNT_V2_8822C << BIT_SHIFT_FREERUN_CNT_V2_8822C) +#define BIT_CLEAR_FREERUN_CNT_V2_8822C(x) ((x) & (~BITS_FREERUN_CNT_V2_8822C)) +#define BIT_GET_FREERUN_CNT_V2_8822C(x) \ + (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8822C) & \ + BIT_MASK_FREERUN_CNT_V2_8822C) +#define BIT_SET_FREERUN_CNT_V2_8822C(x, v) \ + (BIT_CLEAR_FREERUN_CNT_V2_8822C(x) | BIT_FREERUN_CNT_V2_8822C(v)) + +/* 2 REG_ATIMWND1_V1_8822C */ + +#define BIT_SHIFT_ATIMWND1_V1_8822C 0 +#define BIT_MASK_ATIMWND1_V1_8822C 0xff +#define BIT_ATIMWND1_V1_8822C(x) \ + (((x) & BIT_MASK_ATIMWND1_V1_8822C) << BIT_SHIFT_ATIMWND1_V1_8822C) +#define BITS_ATIMWND1_V1_8822C \ + (BIT_MASK_ATIMWND1_V1_8822C << BIT_SHIFT_ATIMWND1_V1_8822C) +#define BIT_CLEAR_ATIMWND1_V1_8822C(x) ((x) & (~BITS_ATIMWND1_V1_8822C)) +#define BIT_GET_ATIMWND1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND1_V1_8822C) & BIT_MASK_ATIMWND1_V1_8822C) +#define BIT_SET_ATIMWND1_V1_8822C(x, v) \ + (BIT_CLEAR_ATIMWND1_V1_8822C(x) | BIT_ATIMWND1_V1_8822C(v)) + +/* 2 REG_TBTT_PROHIBIT_INFRA_8822C */ + +#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C 0 +#define BIT_MASK_TBTT_PROHIBIT_INFRA_8822C 0xff +#define BIT_TBTT_PROHIBIT_INFRA_8822C(x) \ + (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822C) \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C) +#define BITS_TBTT_PROHIBIT_INFRA_8822C \ + (BIT_MASK_TBTT_PROHIBIT_INFRA_8822C \ + << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C) +#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822C(x) \ + ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8822C)) +#define BIT_GET_TBTT_PROHIBIT_INFRA_8822C(x) \ + (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C) & \ + BIT_MASK_TBTT_PROHIBIT_INFRA_8822C) +#define BIT_SET_TBTT_PROHIBIT_INFRA_8822C(x, v) \ + (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822C(x) | \ + BIT_TBTT_PROHIBIT_INFRA_8822C(v)) + +/* 2 REG_CTWND_8822C */ + +#define BIT_SHIFT_CTWND_8822C 0 +#define BIT_MASK_CTWND_8822C 0xff +#define BIT_CTWND_8822C(x) \ + (((x) & BIT_MASK_CTWND_8822C) << BIT_SHIFT_CTWND_8822C) +#define BITS_CTWND_8822C (BIT_MASK_CTWND_8822C << BIT_SHIFT_CTWND_8822C) +#define BIT_CLEAR_CTWND_8822C(x) ((x) & (~BITS_CTWND_8822C)) +#define BIT_GET_CTWND_8822C(x) \ + (((x) >> BIT_SHIFT_CTWND_8822C) & BIT_MASK_CTWND_8822C) +#define BIT_SET_CTWND_8822C(x, v) \ + (BIT_CLEAR_CTWND_8822C(x) | BIT_CTWND_8822C(v)) + +/* 2 REG_BCNIVLCUNT_8822C */ + +#define BIT_SHIFT_BCNIVLCUNT_8822C 0 +#define BIT_MASK_BCNIVLCUNT_8822C 0x7f +#define BIT_BCNIVLCUNT_8822C(x) \ + (((x) & BIT_MASK_BCNIVLCUNT_8822C) << BIT_SHIFT_BCNIVLCUNT_8822C) +#define BITS_BCNIVLCUNT_8822C \ + (BIT_MASK_BCNIVLCUNT_8822C << BIT_SHIFT_BCNIVLCUNT_8822C) +#define BIT_CLEAR_BCNIVLCUNT_8822C(x) ((x) & (~BITS_BCNIVLCUNT_8822C)) +#define BIT_GET_BCNIVLCUNT_8822C(x) \ + (((x) >> BIT_SHIFT_BCNIVLCUNT_8822C) & BIT_MASK_BCNIVLCUNT_8822C) +#define BIT_SET_BCNIVLCUNT_8822C(x, v) \ + (BIT_CLEAR_BCNIVLCUNT_8822C(x) | BIT_BCNIVLCUNT_8822C(v)) + +/* 2 REG_BCNDROPCTRL_8822C */ +#define BIT_BEACON_DROP_EN_8822C BIT(7) + +#define BIT_SHIFT_BEACON_DROP_IVL_8822C 0 +#define BIT_MASK_BEACON_DROP_IVL_8822C 0x7f +#define BIT_BEACON_DROP_IVL_8822C(x) \ + (((x) & BIT_MASK_BEACON_DROP_IVL_8822C) \ + << BIT_SHIFT_BEACON_DROP_IVL_8822C) +#define BITS_BEACON_DROP_IVL_8822C \ + (BIT_MASK_BEACON_DROP_IVL_8822C << BIT_SHIFT_BEACON_DROP_IVL_8822C) +#define BIT_CLEAR_BEACON_DROP_IVL_8822C(x) ((x) & (~BITS_BEACON_DROP_IVL_8822C)) +#define BIT_GET_BEACON_DROP_IVL_8822C(x) \ + (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822C) & \ + BIT_MASK_BEACON_DROP_IVL_8822C) +#define BIT_SET_BEACON_DROP_IVL_8822C(x, v) \ + (BIT_CLEAR_BEACON_DROP_IVL_8822C(x) | BIT_BEACON_DROP_IVL_8822C(v)) + +/* 2 REG_HGQ_TIMEOUT_PERIOD_8822C */ + +#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C 0 +#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C 0xff +#define BIT_HGQ_TIMEOUT_PERIOD_8822C(x) \ + (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C) \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C) +#define BITS_HGQ_TIMEOUT_PERIOD_8822C \ + (BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C \ + << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C) +#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822C(x) \ + ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8822C)) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822C(x) \ + (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C) & \ + BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C) +#define BIT_SET_HGQ_TIMEOUT_PERIOD_8822C(x, v) \ + (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822C(x) | \ + BIT_HGQ_TIMEOUT_PERIOD_8822C(v)) + +/* 2 REG_TXCMD_TIMEOUT_PERIOD_8822C */ + +#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C 0 +#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C 0xff +#define BIT_TXCMD_TIMEOUT_PERIOD_8822C(x) \ + (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C) \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C) +#define BITS_TXCMD_TIMEOUT_PERIOD_8822C \ + (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C \ + << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C) +#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822C(x) \ + ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8822C)) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822C(x) \ + (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C) & \ + BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C) +#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8822C(x, v) \ + (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822C(x) | \ + BIT_TXCMD_TIMEOUT_PERIOD_8822C(v)) + +/* 2 REG_MISC_CTRL_8822C */ +#define BIT_DIS_MARK_TSF_US_V2_8822C BIT(7) +#define BIT_AUTO_SYNC_BY_TBTT_8822C BIT(6) +#define BIT_DIS_TRX_CAL_BCN_8822C BIT(5) +#define BIT_DIS_TX_CAL_TBTT_8822C BIT(4) +#define BIT_EN_FREECNT_8822C BIT(3) +#define BIT_BCN_AGGRESSION_8822C BIT(2) + +#define BIT_SHIFT_DIS_SECONDARY_CCA_8822C 0 +#define BIT_MASK_DIS_SECONDARY_CCA_8822C 0x3 +#define BIT_DIS_SECONDARY_CCA_8822C(x) \ + (((x) & BIT_MASK_DIS_SECONDARY_CCA_8822C) \ + << BIT_SHIFT_DIS_SECONDARY_CCA_8822C) +#define BITS_DIS_SECONDARY_CCA_8822C \ + (BIT_MASK_DIS_SECONDARY_CCA_8822C << BIT_SHIFT_DIS_SECONDARY_CCA_8822C) +#define BIT_CLEAR_DIS_SECONDARY_CCA_8822C(x) \ + ((x) & (~BITS_DIS_SECONDARY_CCA_8822C)) +#define BIT_GET_DIS_SECONDARY_CCA_8822C(x) \ + (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822C) & \ + BIT_MASK_DIS_SECONDARY_CCA_8822C) +#define BIT_SET_DIS_SECONDARY_CCA_8822C(x, v) \ + (BIT_CLEAR_DIS_SECONDARY_CCA_8822C(x) | BIT_DIS_SECONDARY_CCA_8822C(v)) + +/* 2 REG_BCN_CTRL_CLINT1_8822C */ +#define BIT_CLI1_DIS_RX_BSSID_FIT_8822C BIT(6) +#define BIT_CLI1_DIS_TSF_UDT_8822C BIT(4) +#define BIT_CLI1_EN_BCN_FUNCTION_8822C BIT(3) +#define BIT_CLI1_EN_RXBCN_RPT_8822C BIT(2) +#define BIT_CLI1_ENP2P_CTWINDOW_8822C BIT(1) +#define BIT_CLI1_ENP2P_BCNQ_AREA_8822C BIT(0) + +/* 2 REG_BCN_CTRL_CLINT2_8822C */ +#define BIT_CLI2_DIS_RX_BSSID_FIT_8822C BIT(6) +#define BIT_CLI2_DIS_TSF_UDT_8822C BIT(4) +#define BIT_CLI2_EN_BCN_FUNCTION_8822C BIT(3) +#define BIT_CLI2_EN_RXBCN_RPT_8822C BIT(2) +#define BIT_CLI2_ENP2P_CTWINDOW_8822C BIT(1) +#define BIT_CLI2_ENP2P_BCNQ_AREA_8822C BIT(0) + +/* 2 REG_BCN_CTRL_CLINT3_8822C */ +#define BIT_CLI3_DIS_RX_BSSID_FIT_8822C BIT(6) +#define BIT_CLI3_DIS_TSF_UDT_8822C BIT(4) +#define BIT_CLI3_EN_BCN_FUNCTION_8822C BIT(3) +#define BIT_CLI3_EN_RXBCN_RPT_8822C BIT(2) +#define BIT_CLI3_ENP2P_CTWINDOW_8822C BIT(1) +#define BIT_CLI3_ENP2P_BCNQ_AREA_8822C BIT(0) + +/* 2 REG_EXTEND_CTRL_8822C */ +#define BIT_EN_TSFBIT32_RST_P2P2_8822C BIT(5) +#define BIT_EN_TSFBIT32_RST_P2P1_8822C BIT(4) + +#define BIT_SHIFT_PORT_SEL_8822C 0 +#define BIT_MASK_PORT_SEL_8822C 0x7 +#define BIT_PORT_SEL_8822C(x) \ + (((x) & BIT_MASK_PORT_SEL_8822C) << BIT_SHIFT_PORT_SEL_8822C) +#define BITS_PORT_SEL_8822C \ + (BIT_MASK_PORT_SEL_8822C << BIT_SHIFT_PORT_SEL_8822C) +#define BIT_CLEAR_PORT_SEL_8822C(x) ((x) & (~BITS_PORT_SEL_8822C)) +#define BIT_GET_PORT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_PORT_SEL_8822C) & BIT_MASK_PORT_SEL_8822C) +#define BIT_SET_PORT_SEL_8822C(x, v) \ + (BIT_CLEAR_PORT_SEL_8822C(x) | BIT_PORT_SEL_8822C(v)) + +/* 2 REG_P2PPS1_SPEC_STATE_8822C */ +#define BIT_P2P1_SPEC_POWER_STATE_8822C BIT(7) +#define BIT_P2P1_SPEC_CTWINDOW_ON_8822C BIT(6) +#define BIT_P2P1_SPEC_BCN_AREA_ON_8822C BIT(5) +#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_P2P1_SPEC_FORCE_DOZE1_8822C BIT(2) +#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_P2P1_SPEC_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_P2PPS1_STATE_8822C */ +#define BIT_P2P1_POWER_STATE_8822C BIT(7) +#define BIT_P2P1_CTWINDOW_ON_8822C BIT(6) +#define BIT_P2P1_BEACON_AREA_ON_8822C BIT(5) +#define BIT_P2P1_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_P2P1_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_P2P1_FORCE_DOZE1_8822C BIT(2) +#define BIT_P2P1_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_P2P1_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_P2PPS2_SPEC_STATE_8822C */ +#define BIT_P2P2_SPEC_POWER_STATE_8822C BIT(7) +#define BIT_P2P2_SPEC_CTWINDOW_ON_8822C BIT(6) +#define BIT_P2P2_SPEC_BCN_AREA_ON_8822C BIT(5) +#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_P2P2_SPEC_FORCE_DOZE1_8822C BIT(2) +#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_P2P2_SPEC_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_P2PPS2_STATE_8822C */ +#define BIT_P2P2_POWER_STATE_8822C BIT(7) +#define BIT_P2P2_CTWINDOW_ON_8822C BIT(6) +#define BIT_P2P2_BEACON_AREA_ON_8822C BIT(5) +#define BIT_P2P2_CTWIN_EARLY_DISTX_8822C BIT(4) +#define BIT_P2P2_NOA1_OFF_PERIOD_8822C BIT(3) +#define BIT_P2P2_FORCE_DOZE1_8822C BIT(2) +#define BIT_P2P2_NOA0_OFF_PERIOD_8822C BIT(1) +#define BIT_P2P2_FORCE_DOZE0_8822C BIT(0) + +/* 2 REG_PS_TIMER0_8822C */ + +#define BIT_SHIFT_PSTIMER0_INT_8822C 5 +#define BIT_MASK_PSTIMER0_INT_8822C 0x7ffffff +#define BIT_PSTIMER0_INT_8822C(x) \ + (((x) & BIT_MASK_PSTIMER0_INT_8822C) << BIT_SHIFT_PSTIMER0_INT_8822C) +#define BITS_PSTIMER0_INT_8822C \ + (BIT_MASK_PSTIMER0_INT_8822C << BIT_SHIFT_PSTIMER0_INT_8822C) +#define BIT_CLEAR_PSTIMER0_INT_8822C(x) ((x) & (~BITS_PSTIMER0_INT_8822C)) +#define BIT_GET_PSTIMER0_INT_8822C(x) \ + (((x) >> BIT_SHIFT_PSTIMER0_INT_8822C) & BIT_MASK_PSTIMER0_INT_8822C) +#define BIT_SET_PSTIMER0_INT_8822C(x, v) \ + (BIT_CLEAR_PSTIMER0_INT_8822C(x) | BIT_PSTIMER0_INT_8822C(v)) + +/* 2 REG_PS_TIMER1_8822C */ + +#define BIT_SHIFT_PSTIMER1_INT_8822C 5 +#define BIT_MASK_PSTIMER1_INT_8822C 0x7ffffff +#define BIT_PSTIMER1_INT_8822C(x) \ + (((x) & BIT_MASK_PSTIMER1_INT_8822C) << BIT_SHIFT_PSTIMER1_INT_8822C) +#define BITS_PSTIMER1_INT_8822C \ + (BIT_MASK_PSTIMER1_INT_8822C << BIT_SHIFT_PSTIMER1_INT_8822C) +#define BIT_CLEAR_PSTIMER1_INT_8822C(x) ((x) & (~BITS_PSTIMER1_INT_8822C)) +#define BIT_GET_PSTIMER1_INT_8822C(x) \ + (((x) >> BIT_SHIFT_PSTIMER1_INT_8822C) & BIT_MASK_PSTIMER1_INT_8822C) +#define BIT_SET_PSTIMER1_INT_8822C(x, v) \ + (BIT_CLEAR_PSTIMER1_INT_8822C(x) | BIT_PSTIMER1_INT_8822C(v)) + +/* 2 REG_PS_TIMER2_8822C */ + +#define BIT_SHIFT_PSTIMER2_INT_8822C 5 +#define BIT_MASK_PSTIMER2_INT_8822C 0x7ffffff +#define BIT_PSTIMER2_INT_8822C(x) \ + (((x) & BIT_MASK_PSTIMER2_INT_8822C) << BIT_SHIFT_PSTIMER2_INT_8822C) +#define BITS_PSTIMER2_INT_8822C \ + (BIT_MASK_PSTIMER2_INT_8822C << BIT_SHIFT_PSTIMER2_INT_8822C) +#define BIT_CLEAR_PSTIMER2_INT_8822C(x) ((x) & (~BITS_PSTIMER2_INT_8822C)) +#define BIT_GET_PSTIMER2_INT_8822C(x) \ + (((x) >> BIT_SHIFT_PSTIMER2_INT_8822C) & BIT_MASK_PSTIMER2_INT_8822C) +#define BIT_SET_PSTIMER2_INT_8822C(x, v) \ + (BIT_CLEAR_PSTIMER2_INT_8822C(x) | BIT_PSTIMER2_INT_8822C(v)) + +/* 2 REG_TBTT_CTN_AREA_8822C */ + +#define BIT_SHIFT_TBTT_CTN_AREA_8822C 0 +#define BIT_MASK_TBTT_CTN_AREA_8822C 0xff +#define BIT_TBTT_CTN_AREA_8822C(x) \ + (((x) & BIT_MASK_TBTT_CTN_AREA_8822C) << BIT_SHIFT_TBTT_CTN_AREA_8822C) +#define BITS_TBTT_CTN_AREA_8822C \ + (BIT_MASK_TBTT_CTN_AREA_8822C << BIT_SHIFT_TBTT_CTN_AREA_8822C) +#define BIT_CLEAR_TBTT_CTN_AREA_8822C(x) ((x) & (~BITS_TBTT_CTN_AREA_8822C)) +#define BIT_GET_TBTT_CTN_AREA_8822C(x) \ + (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822C) & BIT_MASK_TBTT_CTN_AREA_8822C) +#define BIT_SET_TBTT_CTN_AREA_8822C(x, v) \ + (BIT_CLEAR_TBTT_CTN_AREA_8822C(x) | BIT_TBTT_CTN_AREA_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_FORCE_BCN_IFS_8822C */ + +#define BIT_SHIFT_FORCE_BCN_IFS_8822C 0 +#define BIT_MASK_FORCE_BCN_IFS_8822C 0xff +#define BIT_FORCE_BCN_IFS_8822C(x) \ + (((x) & BIT_MASK_FORCE_BCN_IFS_8822C) << BIT_SHIFT_FORCE_BCN_IFS_8822C) +#define BITS_FORCE_BCN_IFS_8822C \ + (BIT_MASK_FORCE_BCN_IFS_8822C << BIT_SHIFT_FORCE_BCN_IFS_8822C) +#define BIT_CLEAR_FORCE_BCN_IFS_8822C(x) ((x) & (~BITS_FORCE_BCN_IFS_8822C)) +#define BIT_GET_FORCE_BCN_IFS_8822C(x) \ + (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822C) & BIT_MASK_FORCE_BCN_IFS_8822C) +#define BIT_SET_FORCE_BCN_IFS_8822C(x, v) \ + (BIT_CLEAR_FORCE_BCN_IFS_8822C(x) | BIT_FORCE_BCN_IFS_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_TXOP_MIN_8822C */ +#define BIT_HIQ_NAV_BREAK_EN_8822C BIT(15) +#define BIT_MGQ_NAV_BREAK_EN_8822C BIT(14) + +#define BIT_SHIFT_TXOP_MIN_8822C 0 +#define BIT_MASK_TXOP_MIN_8822C 0x3fff +#define BIT_TXOP_MIN_8822C(x) \ + (((x) & BIT_MASK_TXOP_MIN_8822C) << BIT_SHIFT_TXOP_MIN_8822C) +#define BITS_TXOP_MIN_8822C \ + (BIT_MASK_TXOP_MIN_8822C << BIT_SHIFT_TXOP_MIN_8822C) +#define BIT_CLEAR_TXOP_MIN_8822C(x) ((x) & (~BITS_TXOP_MIN_8822C)) +#define BIT_GET_TXOP_MIN_8822C(x) \ + (((x) >> BIT_SHIFT_TXOP_MIN_8822C) & BIT_MASK_TXOP_MIN_8822C) +#define BIT_SET_TXOP_MIN_8822C(x, v) \ + (BIT_CLEAR_TXOP_MIN_8822C(x) | BIT_TXOP_MIN_8822C(v)) + +/* 2 REG_PRE_BKF_TIME_8822C */ + +#define BIT_SHIFT_PRE_BKF_TIME_8822C 0 +#define BIT_MASK_PRE_BKF_TIME_8822C 0xff +#define BIT_PRE_BKF_TIME_8822C(x) \ + (((x) & BIT_MASK_PRE_BKF_TIME_8822C) << BIT_SHIFT_PRE_BKF_TIME_8822C) +#define BITS_PRE_BKF_TIME_8822C \ + (BIT_MASK_PRE_BKF_TIME_8822C << BIT_SHIFT_PRE_BKF_TIME_8822C) +#define BIT_CLEAR_PRE_BKF_TIME_8822C(x) ((x) & (~BITS_PRE_BKF_TIME_8822C)) +#define BIT_GET_PRE_BKF_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_PRE_BKF_TIME_8822C) & BIT_MASK_PRE_BKF_TIME_8822C) +#define BIT_SET_PRE_BKF_TIME_8822C(x, v) \ + (BIT_CLEAR_PRE_BKF_TIME_8822C(x) | BIT_PRE_BKF_TIME_8822C(v)) + +/* 2 REG_CROSS_TXOP_CTRL_8822C */ +#define BIT_TXFAIL_BREACK_TXOP_EN_8822C BIT(3) +#define BIT_DTIM_BYPASS_8822C BIT(2) +#define BIT_RTS_NAV_TXOP_8822C BIT(1) +#define BIT_NOT_CROSS_TXOP_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_RX_TBTT_SHIFT_V1_8822C */ +#define BIT_RX_TBTT_SHIFT_RW_FLAG_V1_8822C BIT(31) + +#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C 16 +#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C 0xfff +#define BIT_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C) \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C) +#define BITS_RX_TBTT_SHIFT_OFFSET_V1_8822C \ + (BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C \ + << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C) +#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) \ + ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_V1_8822C)) +#define BIT_GET_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C) & \ + BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C) +#define BIT_SET_RX_TBTT_SHIFT_OFFSET_V1_8822C(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) | \ + BIT_RX_TBTT_SHIFT_OFFSET_V1_8822C(v)) + +#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C 8 +#define BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C 0x7 +#define BIT_RX_TBTT_SHIFT_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C) \ + << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C) +#define BITS_RX_TBTT_SHIFT_SEL_V1_8822C \ + (BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C \ + << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C) +#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1_8822C(x) \ + ((x) & (~BITS_RX_TBTT_SHIFT_SEL_V1_8822C)) +#define BIT_GET_RX_TBTT_SHIFT_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C) & \ + BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C) +#define BIT_SET_RX_TBTT_SHIFT_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1_8822C(x) | \ + BIT_RX_TBTT_SHIFT_SEL_V1_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_ATIMWND2_8822C */ + +#define BIT_SHIFT_ATIMWND2_8822C 0 +#define BIT_MASK_ATIMWND2_8822C 0xff +#define BIT_ATIMWND2_8822C(x) \ + (((x) & BIT_MASK_ATIMWND2_8822C) << BIT_SHIFT_ATIMWND2_8822C) +#define BITS_ATIMWND2_8822C \ + (BIT_MASK_ATIMWND2_8822C << BIT_SHIFT_ATIMWND2_8822C) +#define BIT_CLEAR_ATIMWND2_8822C(x) ((x) & (~BITS_ATIMWND2_8822C)) +#define BIT_GET_ATIMWND2_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND2_8822C) & BIT_MASK_ATIMWND2_8822C) +#define BIT_SET_ATIMWND2_8822C(x, v) \ + (BIT_CLEAR_ATIMWND2_8822C(x) | BIT_ATIMWND2_8822C(v)) + +/* 2 REG_ATIMWND3_8822C */ + +#define BIT_SHIFT_ATIMWND3_8822C 0 +#define BIT_MASK_ATIMWND3_8822C 0xff +#define BIT_ATIMWND3_8822C(x) \ + (((x) & BIT_MASK_ATIMWND3_8822C) << BIT_SHIFT_ATIMWND3_8822C) +#define BITS_ATIMWND3_8822C \ + (BIT_MASK_ATIMWND3_8822C << BIT_SHIFT_ATIMWND3_8822C) +#define BIT_CLEAR_ATIMWND3_8822C(x) ((x) & (~BITS_ATIMWND3_8822C)) +#define BIT_GET_ATIMWND3_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND3_8822C) & BIT_MASK_ATIMWND3_8822C) +#define BIT_SET_ATIMWND3_8822C(x, v) \ + (BIT_CLEAR_ATIMWND3_8822C(x) | BIT_ATIMWND3_8822C(v)) + +/* 2 REG_ATIMWND4_8822C */ + +#define BIT_SHIFT_ATIMWND4_8822C 0 +#define BIT_MASK_ATIMWND4_8822C 0xff +#define BIT_ATIMWND4_8822C(x) \ + (((x) & BIT_MASK_ATIMWND4_8822C) << BIT_SHIFT_ATIMWND4_8822C) +#define BITS_ATIMWND4_8822C \ + (BIT_MASK_ATIMWND4_8822C << BIT_SHIFT_ATIMWND4_8822C) +#define BIT_CLEAR_ATIMWND4_8822C(x) ((x) & (~BITS_ATIMWND4_8822C)) +#define BIT_GET_ATIMWND4_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND4_8822C) & BIT_MASK_ATIMWND4_8822C) +#define BIT_SET_ATIMWND4_8822C(x, v) \ + (BIT_CLEAR_ATIMWND4_8822C(x) | BIT_ATIMWND4_8822C(v)) + +/* 2 REG_ATIMWND5_8822C */ + +#define BIT_SHIFT_ATIMWND5_8822C 0 +#define BIT_MASK_ATIMWND5_8822C 0xff +#define BIT_ATIMWND5_8822C(x) \ + (((x) & BIT_MASK_ATIMWND5_8822C) << BIT_SHIFT_ATIMWND5_8822C) +#define BITS_ATIMWND5_8822C \ + (BIT_MASK_ATIMWND5_8822C << BIT_SHIFT_ATIMWND5_8822C) +#define BIT_CLEAR_ATIMWND5_8822C(x) ((x) & (~BITS_ATIMWND5_8822C)) +#define BIT_GET_ATIMWND5_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND5_8822C) & BIT_MASK_ATIMWND5_8822C) +#define BIT_SET_ATIMWND5_8822C(x, v) \ + (BIT_CLEAR_ATIMWND5_8822C(x) | BIT_ATIMWND5_8822C(v)) + +/* 2 REG_ATIMWND6_8822C */ + +#define BIT_SHIFT_ATIMWND6_8822C 0 +#define BIT_MASK_ATIMWND6_8822C 0xff +#define BIT_ATIMWND6_8822C(x) \ + (((x) & BIT_MASK_ATIMWND6_8822C) << BIT_SHIFT_ATIMWND6_8822C) +#define BITS_ATIMWND6_8822C \ + (BIT_MASK_ATIMWND6_8822C << BIT_SHIFT_ATIMWND6_8822C) +#define BIT_CLEAR_ATIMWND6_8822C(x) ((x) & (~BITS_ATIMWND6_8822C)) +#define BIT_GET_ATIMWND6_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND6_8822C) & BIT_MASK_ATIMWND6_8822C) +#define BIT_SET_ATIMWND6_8822C(x, v) \ + (BIT_CLEAR_ATIMWND6_8822C(x) | BIT_ATIMWND6_8822C(v)) + +/* 2 REG_ATIMWND7_8822C */ + +#define BIT_SHIFT_ATIMWND7_8822C 0 +#define BIT_MASK_ATIMWND7_8822C 0xff +#define BIT_ATIMWND7_8822C(x) \ + (((x) & BIT_MASK_ATIMWND7_8822C) << BIT_SHIFT_ATIMWND7_8822C) +#define BITS_ATIMWND7_8822C \ + (BIT_MASK_ATIMWND7_8822C << BIT_SHIFT_ATIMWND7_8822C) +#define BIT_CLEAR_ATIMWND7_8822C(x) ((x) & (~BITS_ATIMWND7_8822C)) +#define BIT_GET_ATIMWND7_8822C(x) \ + (((x) >> BIT_SHIFT_ATIMWND7_8822C) & BIT_MASK_ATIMWND7_8822C) +#define BIT_SET_ATIMWND7_8822C(x, v) \ + (BIT_CLEAR_ATIMWND7_8822C(x) | BIT_ATIMWND7_8822C(v)) + +/* 2 REG_ATIMUGT_8822C */ + +#define BIT_SHIFT_ATIM_URGENT_8822C 0 +#define BIT_MASK_ATIM_URGENT_8822C 0xff +#define BIT_ATIM_URGENT_8822C(x) \ + (((x) & BIT_MASK_ATIM_URGENT_8822C) << BIT_SHIFT_ATIM_URGENT_8822C) +#define BITS_ATIM_URGENT_8822C \ + (BIT_MASK_ATIM_URGENT_8822C << BIT_SHIFT_ATIM_URGENT_8822C) +#define BIT_CLEAR_ATIM_URGENT_8822C(x) ((x) & (~BITS_ATIM_URGENT_8822C)) +#define BIT_GET_ATIM_URGENT_8822C(x) \ + (((x) >> BIT_SHIFT_ATIM_URGENT_8822C) & BIT_MASK_ATIM_URGENT_8822C) +#define BIT_SET_ATIM_URGENT_8822C(x, v) \ + (BIT_CLEAR_ATIM_URGENT_8822C(x) | BIT_ATIM_URGENT_8822C(v)) + +/* 2 REG_HIQ_NO_LMT_EN_8822C */ +#define BIT_HIQ_NO_LMT_EN_VAP7_8822C BIT(7) +#define BIT_HIQ_NO_LMT_EN_VAP6_8822C BIT(6) +#define BIT_HIQ_NO_LMT_EN_VAP5_8822C BIT(5) +#define BIT_HIQ_NO_LMT_EN_VAP4_8822C BIT(4) +#define BIT_HIQ_NO_LMT_EN_VAP3_8822C BIT(3) +#define BIT_HIQ_NO_LMT_EN_VAP2_8822C BIT(2) +#define BIT_HIQ_NO_LMT_EN_VAP1_8822C BIT(1) +#define BIT_HIQ_NO_LMT_EN_ROOT_8822C BIT(0) + +/* 2 REG_DTIM_COUNTER_ROOT_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_ROOT_8822C 0 +#define BIT_MASK_DTIM_COUNT_ROOT_8822C 0xff +#define BIT_DTIM_COUNT_ROOT_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_ROOT_8822C) \ + << BIT_SHIFT_DTIM_COUNT_ROOT_8822C) +#define BITS_DTIM_COUNT_ROOT_8822C \ + (BIT_MASK_DTIM_COUNT_ROOT_8822C << BIT_SHIFT_DTIM_COUNT_ROOT_8822C) +#define BIT_CLEAR_DTIM_COUNT_ROOT_8822C(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8822C)) +#define BIT_GET_DTIM_COUNT_ROOT_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822C) & \ + BIT_MASK_DTIM_COUNT_ROOT_8822C) +#define BIT_SET_DTIM_COUNT_ROOT_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_ROOT_8822C(x) | BIT_DTIM_COUNT_ROOT_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP1_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP1_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP1_8822C 0xff +#define BIT_DTIM_COUNT_VAP1_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP1_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP1_8822C) +#define BITS_DTIM_COUNT_VAP1_8822C \ + (BIT_MASK_DTIM_COUNT_VAP1_8822C << BIT_SHIFT_DTIM_COUNT_VAP1_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP1_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8822C)) +#define BIT_GET_DTIM_COUNT_VAP1_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP1_8822C) +#define BIT_SET_DTIM_COUNT_VAP1_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP1_8822C(x) | BIT_DTIM_COUNT_VAP1_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP2_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP2_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP2_8822C 0xff +#define BIT_DTIM_COUNT_VAP2_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP2_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP2_8822C) +#define BITS_DTIM_COUNT_VAP2_8822C \ + (BIT_MASK_DTIM_COUNT_VAP2_8822C << BIT_SHIFT_DTIM_COUNT_VAP2_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP2_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8822C)) +#define BIT_GET_DTIM_COUNT_VAP2_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP2_8822C) +#define BIT_SET_DTIM_COUNT_VAP2_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP2_8822C(x) | BIT_DTIM_COUNT_VAP2_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP3_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP3_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP3_8822C 0xff +#define BIT_DTIM_COUNT_VAP3_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP3_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP3_8822C) +#define BITS_DTIM_COUNT_VAP3_8822C \ + (BIT_MASK_DTIM_COUNT_VAP3_8822C << BIT_SHIFT_DTIM_COUNT_VAP3_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP3_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8822C)) +#define BIT_GET_DTIM_COUNT_VAP3_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP3_8822C) +#define BIT_SET_DTIM_COUNT_VAP3_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP3_8822C(x) | BIT_DTIM_COUNT_VAP3_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP4_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP4_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP4_8822C 0xff +#define BIT_DTIM_COUNT_VAP4_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP4_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP4_8822C) +#define BITS_DTIM_COUNT_VAP4_8822C \ + (BIT_MASK_DTIM_COUNT_VAP4_8822C << BIT_SHIFT_DTIM_COUNT_VAP4_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP4_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8822C)) +#define BIT_GET_DTIM_COUNT_VAP4_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP4_8822C) +#define BIT_SET_DTIM_COUNT_VAP4_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP4_8822C(x) | BIT_DTIM_COUNT_VAP4_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP5_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP5_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP5_8822C 0xff +#define BIT_DTIM_COUNT_VAP5_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP5_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP5_8822C) +#define BITS_DTIM_COUNT_VAP5_8822C \ + (BIT_MASK_DTIM_COUNT_VAP5_8822C << BIT_SHIFT_DTIM_COUNT_VAP5_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP5_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8822C)) +#define BIT_GET_DTIM_COUNT_VAP5_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP5_8822C) +#define BIT_SET_DTIM_COUNT_VAP5_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP5_8822C(x) | BIT_DTIM_COUNT_VAP5_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP6_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP6_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP6_8822C 0xff +#define BIT_DTIM_COUNT_VAP6_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP6_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP6_8822C) +#define BITS_DTIM_COUNT_VAP6_8822C \ + (BIT_MASK_DTIM_COUNT_VAP6_8822C << BIT_SHIFT_DTIM_COUNT_VAP6_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP6_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8822C)) +#define BIT_GET_DTIM_COUNT_VAP6_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP6_8822C) +#define BIT_SET_DTIM_COUNT_VAP6_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP6_8822C(x) | BIT_DTIM_COUNT_VAP6_8822C(v)) + +/* 2 REG_DTIM_COUNTER_VAP7_8822C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP7_8822C 0 +#define BIT_MASK_DTIM_COUNT_VAP7_8822C 0xff +#define BIT_DTIM_COUNT_VAP7_8822C(x) \ + (((x) & BIT_MASK_DTIM_COUNT_VAP7_8822C) \ + << BIT_SHIFT_DTIM_COUNT_VAP7_8822C) +#define BITS_DTIM_COUNT_VAP7_8822C \ + (BIT_MASK_DTIM_COUNT_VAP7_8822C << BIT_SHIFT_DTIM_COUNT_VAP7_8822C) +#define BIT_CLEAR_DTIM_COUNT_VAP7_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8822C)) +#define BIT_GET_DTIM_COUNT_VAP7_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822C) & \ + BIT_MASK_DTIM_COUNT_VAP7_8822C) +#define BIT_SET_DTIM_COUNT_VAP7_8822C(x, v) \ + (BIT_CLEAR_DTIM_COUNT_VAP7_8822C(x) | BIT_DTIM_COUNT_VAP7_8822C(v)) + +/* 2 REG_DIS_ATIM_8822C */ +#define BIT_DIS_ATIM_VAP7_8822C BIT(7) +#define BIT_DIS_ATIM_VAP6_8822C BIT(6) +#define BIT_DIS_ATIM_VAP5_8822C BIT(5) +#define BIT_DIS_ATIM_VAP4_8822C BIT(4) +#define BIT_DIS_ATIM_VAP3_8822C BIT(3) +#define BIT_DIS_ATIM_VAP2_8822C BIT(2) +#define BIT_DIS_ATIM_VAP1_8822C BIT(1) +#define BIT_DIS_ATIM_ROOT_8822C BIT(0) + +/* 2 REG_EARLY_128US_8822C */ + +#define BIT_SHIFT_TSFT_SEL_TIMER1_8822C 3 +#define BIT_MASK_TSFT_SEL_TIMER1_8822C 0x7 +#define BIT_TSFT_SEL_TIMER1_8822C(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER1_8822C) \ + << BIT_SHIFT_TSFT_SEL_TIMER1_8822C) +#define BITS_TSFT_SEL_TIMER1_8822C \ + (BIT_MASK_TSFT_SEL_TIMER1_8822C << BIT_SHIFT_TSFT_SEL_TIMER1_8822C) +#define BIT_CLEAR_TSFT_SEL_TIMER1_8822C(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8822C)) +#define BIT_GET_TSFT_SEL_TIMER1_8822C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822C) & \ + BIT_MASK_TSFT_SEL_TIMER1_8822C) +#define BIT_SET_TSFT_SEL_TIMER1_8822C(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER1_8822C(x) | BIT_TSFT_SEL_TIMER1_8822C(v)) + +#define BIT_SHIFT_EARLY_128US_8822C 0 +#define BIT_MASK_EARLY_128US_8822C 0x7 +#define BIT_EARLY_128US_8822C(x) \ + (((x) & BIT_MASK_EARLY_128US_8822C) << BIT_SHIFT_EARLY_128US_8822C) +#define BITS_EARLY_128US_8822C \ + (BIT_MASK_EARLY_128US_8822C << BIT_SHIFT_EARLY_128US_8822C) +#define BIT_CLEAR_EARLY_128US_8822C(x) ((x) & (~BITS_EARLY_128US_8822C)) +#define BIT_GET_EARLY_128US_8822C(x) \ + (((x) >> BIT_SHIFT_EARLY_128US_8822C) & BIT_MASK_EARLY_128US_8822C) +#define BIT_SET_EARLY_128US_8822C(x, v) \ + (BIT_CLEAR_EARLY_128US_8822C(x) | BIT_EARLY_128US_8822C(v)) + +/* 2 REG_P2PPS1_CTRL_8822C */ +#define BIT_P2P1_CTW_ALLSTASLEEP_8822C BIT(7) +#define BIT_P2P1_OFF_DISTX_EN_8822C BIT(6) +#define BIT_P2P1_PWR_MGT_EN_8822C BIT(5) +#define BIT_P2P1_NOA1_EN_8822C BIT(2) +#define BIT_P2P1_NOA0_EN_8822C BIT(1) + +/* 2 REG_P2PPS2_CTRL_8822C */ +#define BIT_P2P2_CTW_ALLSTASLEEP_8822C BIT(7) +#define BIT_P2P2_OFF_DISTX_EN_8822C BIT(6) +#define BIT_P2P2_PWR_MGT_EN_8822C BIT(5) +#define BIT_P2P2_NOA1_EN_8822C BIT(2) +#define BIT_P2P2_NOA0_EN_8822C BIT(1) + +/* 2 REG_TIMER0_SRC_SEL_8822C */ + +#define BIT_SHIFT_SYNC_CLI_SEL_8822C 4 +#define BIT_MASK_SYNC_CLI_SEL_8822C 0x7 +#define BIT_SYNC_CLI_SEL_8822C(x) \ + (((x) & BIT_MASK_SYNC_CLI_SEL_8822C) << BIT_SHIFT_SYNC_CLI_SEL_8822C) +#define BITS_SYNC_CLI_SEL_8822C \ + (BIT_MASK_SYNC_CLI_SEL_8822C << BIT_SHIFT_SYNC_CLI_SEL_8822C) +#define BIT_CLEAR_SYNC_CLI_SEL_8822C(x) ((x) & (~BITS_SYNC_CLI_SEL_8822C)) +#define BIT_GET_SYNC_CLI_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822C) & BIT_MASK_SYNC_CLI_SEL_8822C) +#define BIT_SET_SYNC_CLI_SEL_8822C(x, v) \ + (BIT_CLEAR_SYNC_CLI_SEL_8822C(x) | BIT_SYNC_CLI_SEL_8822C(v)) + +#define BIT_SHIFT_TSFT_SEL_TIMER0_8822C 0 +#define BIT_MASK_TSFT_SEL_TIMER0_8822C 0x7 +#define BIT_TSFT_SEL_TIMER0_8822C(x) \ + (((x) & BIT_MASK_TSFT_SEL_TIMER0_8822C) \ + << BIT_SHIFT_TSFT_SEL_TIMER0_8822C) +#define BITS_TSFT_SEL_TIMER0_8822C \ + (BIT_MASK_TSFT_SEL_TIMER0_8822C << BIT_SHIFT_TSFT_SEL_TIMER0_8822C) +#define BIT_CLEAR_TSFT_SEL_TIMER0_8822C(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8822C)) +#define BIT_GET_TSFT_SEL_TIMER0_8822C(x) \ + (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822C) & \ + BIT_MASK_TSFT_SEL_TIMER0_8822C) +#define BIT_SET_TSFT_SEL_TIMER0_8822C(x, v) \ + (BIT_CLEAR_TSFT_SEL_TIMER0_8822C(x) | BIT_TSFT_SEL_TIMER0_8822C(v)) + +/* 2 REG_NOA_UNIT_SEL_8822C */ + +#define BIT_SHIFT_NOA_UNIT2_SEL_8822C 8 +#define BIT_MASK_NOA_UNIT2_SEL_8822C 0x7 +#define BIT_NOA_UNIT2_SEL_8822C(x) \ + (((x) & BIT_MASK_NOA_UNIT2_SEL_8822C) << BIT_SHIFT_NOA_UNIT2_SEL_8822C) +#define BITS_NOA_UNIT2_SEL_8822C \ + (BIT_MASK_NOA_UNIT2_SEL_8822C << BIT_SHIFT_NOA_UNIT2_SEL_8822C) +#define BIT_CLEAR_NOA_UNIT2_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT2_SEL_8822C)) +#define BIT_GET_NOA_UNIT2_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822C) & BIT_MASK_NOA_UNIT2_SEL_8822C) +#define BIT_SET_NOA_UNIT2_SEL_8822C(x, v) \ + (BIT_CLEAR_NOA_UNIT2_SEL_8822C(x) | BIT_NOA_UNIT2_SEL_8822C(v)) + +#define BIT_SHIFT_NOA_UNIT1_SEL_8822C 4 +#define BIT_MASK_NOA_UNIT1_SEL_8822C 0x7 +#define BIT_NOA_UNIT1_SEL_8822C(x) \ + (((x) & BIT_MASK_NOA_UNIT1_SEL_8822C) << BIT_SHIFT_NOA_UNIT1_SEL_8822C) +#define BITS_NOA_UNIT1_SEL_8822C \ + (BIT_MASK_NOA_UNIT1_SEL_8822C << BIT_SHIFT_NOA_UNIT1_SEL_8822C) +#define BIT_CLEAR_NOA_UNIT1_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT1_SEL_8822C)) +#define BIT_GET_NOA_UNIT1_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822C) & BIT_MASK_NOA_UNIT1_SEL_8822C) +#define BIT_SET_NOA_UNIT1_SEL_8822C(x, v) \ + (BIT_CLEAR_NOA_UNIT1_SEL_8822C(x) | BIT_NOA_UNIT1_SEL_8822C(v)) + +#define BIT_SHIFT_NOA_UNIT0_SEL_8822C 0 +#define BIT_MASK_NOA_UNIT0_SEL_8822C 0x7 +#define BIT_NOA_UNIT0_SEL_8822C(x) \ + (((x) & BIT_MASK_NOA_UNIT0_SEL_8822C) << BIT_SHIFT_NOA_UNIT0_SEL_8822C) +#define BITS_NOA_UNIT0_SEL_8822C \ + (BIT_MASK_NOA_UNIT0_SEL_8822C << BIT_SHIFT_NOA_UNIT0_SEL_8822C) +#define BIT_CLEAR_NOA_UNIT0_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT0_SEL_8822C)) +#define BIT_GET_NOA_UNIT0_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822C) & BIT_MASK_NOA_UNIT0_SEL_8822C) +#define BIT_SET_NOA_UNIT0_SEL_8822C(x, v) \ + (BIT_CLEAR_NOA_UNIT0_SEL_8822C(x) | BIT_NOA_UNIT0_SEL_8822C(v)) + +/* 2 REG_P2POFF_DIS_TXTIME_8822C */ + +#define BIT_SHIFT_P2POFF_DIS_TXTIME_8822C 0 +#define BIT_MASK_P2POFF_DIS_TXTIME_8822C 0xff +#define BIT_P2POFF_DIS_TXTIME_8822C(x) \ + (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822C) \ + << BIT_SHIFT_P2POFF_DIS_TXTIME_8822C) +#define BITS_P2POFF_DIS_TXTIME_8822C \ + (BIT_MASK_P2POFF_DIS_TXTIME_8822C << BIT_SHIFT_P2POFF_DIS_TXTIME_8822C) +#define BIT_CLEAR_P2POFF_DIS_TXTIME_8822C(x) \ + ((x) & (~BITS_P2POFF_DIS_TXTIME_8822C)) +#define BIT_GET_P2POFF_DIS_TXTIME_8822C(x) \ + (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822C) & \ + BIT_MASK_P2POFF_DIS_TXTIME_8822C) +#define BIT_SET_P2POFF_DIS_TXTIME_8822C(x, v) \ + (BIT_CLEAR_P2POFF_DIS_TXTIME_8822C(x) | BIT_P2POFF_DIS_TXTIME_8822C(v)) + +/* 2 REG_MBSSID_BCN_SPACE2_8822C */ + +#define BIT_SHIFT_BCN_SPACE_CLINT2_8822C 16 +#define BIT_MASK_BCN_SPACE_CLINT2_8822C 0xfff +#define BIT_BCN_SPACE_CLINT2_8822C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT2_8822C) \ + << BIT_SHIFT_BCN_SPACE_CLINT2_8822C) +#define BITS_BCN_SPACE_CLINT2_8822C \ + (BIT_MASK_BCN_SPACE_CLINT2_8822C << BIT_SHIFT_BCN_SPACE_CLINT2_8822C) +#define BIT_CLEAR_BCN_SPACE_CLINT2_8822C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT2_8822C)) +#define BIT_GET_BCN_SPACE_CLINT2_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822C) & \ + BIT_MASK_BCN_SPACE_CLINT2_8822C) +#define BIT_SET_BCN_SPACE_CLINT2_8822C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT2_8822C(x) | BIT_BCN_SPACE_CLINT2_8822C(v)) + +#define BIT_SHIFT_BCN_SPACE_CLINT1_8822C 0 +#define BIT_MASK_BCN_SPACE_CLINT1_8822C 0xfff +#define BIT_BCN_SPACE_CLINT1_8822C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT1_8822C) \ + << BIT_SHIFT_BCN_SPACE_CLINT1_8822C) +#define BITS_BCN_SPACE_CLINT1_8822C \ + (BIT_MASK_BCN_SPACE_CLINT1_8822C << BIT_SHIFT_BCN_SPACE_CLINT1_8822C) +#define BIT_CLEAR_BCN_SPACE_CLINT1_8822C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT1_8822C)) +#define BIT_GET_BCN_SPACE_CLINT1_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822C) & \ + BIT_MASK_BCN_SPACE_CLINT1_8822C) +#define BIT_SET_BCN_SPACE_CLINT1_8822C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT1_8822C(x) | BIT_BCN_SPACE_CLINT1_8822C(v)) + +/* 2 REG_MBSSID_BCN_SPACE3_8822C */ + +#define BIT_SHIFT_SUB_BCN_SPACE_8822C 16 +#define BIT_MASK_SUB_BCN_SPACE_8822C 0xff +#define BIT_SUB_BCN_SPACE_8822C(x) \ + (((x) & BIT_MASK_SUB_BCN_SPACE_8822C) << BIT_SHIFT_SUB_BCN_SPACE_8822C) +#define BITS_SUB_BCN_SPACE_8822C \ + (BIT_MASK_SUB_BCN_SPACE_8822C << BIT_SHIFT_SUB_BCN_SPACE_8822C) +#define BIT_CLEAR_SUB_BCN_SPACE_8822C(x) ((x) & (~BITS_SUB_BCN_SPACE_8822C)) +#define BIT_GET_SUB_BCN_SPACE_8822C(x) \ + (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822C) & BIT_MASK_SUB_BCN_SPACE_8822C) +#define BIT_SET_SUB_BCN_SPACE_8822C(x, v) \ + (BIT_CLEAR_SUB_BCN_SPACE_8822C(x) | BIT_SUB_BCN_SPACE_8822C(v)) + +#define BIT_SHIFT_BCN_SPACE_CLINT3_8822C 0 +#define BIT_MASK_BCN_SPACE_CLINT3_8822C 0xfff +#define BIT_BCN_SPACE_CLINT3_8822C(x) \ + (((x) & BIT_MASK_BCN_SPACE_CLINT3_8822C) \ + << BIT_SHIFT_BCN_SPACE_CLINT3_8822C) +#define BITS_BCN_SPACE_CLINT3_8822C \ + (BIT_MASK_BCN_SPACE_CLINT3_8822C << BIT_SHIFT_BCN_SPACE_CLINT3_8822C) +#define BIT_CLEAR_BCN_SPACE_CLINT3_8822C(x) \ + ((x) & (~BITS_BCN_SPACE_CLINT3_8822C)) +#define BIT_GET_BCN_SPACE_CLINT3_8822C(x) \ + (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822C) & \ + BIT_MASK_BCN_SPACE_CLINT3_8822C) +#define BIT_SET_BCN_SPACE_CLINT3_8822C(x, v) \ + (BIT_CLEAR_BCN_SPACE_CLINT3_8822C(x) | BIT_BCN_SPACE_CLINT3_8822C(v)) + +/* 2 REG_ACMHWCTRL_8822C */ +#define BIT_BEQ_ACM_STATUS_8822C BIT(7) +#define BIT_VIQ_ACM_STATUS_8822C BIT(6) +#define BIT_VOQ_ACM_STATUS_8822C BIT(5) +#define BIT_BEQ_ACM_EN_8822C BIT(3) +#define BIT_VIQ_ACM_EN_8822C BIT(2) +#define BIT_VOQ_ACM_EN_8822C BIT(1) +#define BIT_ACMHWEN_8822C BIT(0) + +/* 2 REG_ACMRSTCTRL_8822C */ +#define BIT_BE_ACM_RESET_USED_TIME_8822C BIT(2) +#define BIT_VI_ACM_RESET_USED_TIME_8822C BIT(1) +#define BIT_VO_ACM_RESET_USED_TIME_8822C BIT(0) + +/* 2 REG_ACMAVG_8822C */ + +#define BIT_SHIFT_AVGPERIOD_8822C 0 +#define BIT_MASK_AVGPERIOD_8822C 0xffff +#define BIT_AVGPERIOD_8822C(x) \ + (((x) & BIT_MASK_AVGPERIOD_8822C) << BIT_SHIFT_AVGPERIOD_8822C) +#define BITS_AVGPERIOD_8822C \ + (BIT_MASK_AVGPERIOD_8822C << BIT_SHIFT_AVGPERIOD_8822C) +#define BIT_CLEAR_AVGPERIOD_8822C(x) ((x) & (~BITS_AVGPERIOD_8822C)) +#define BIT_GET_AVGPERIOD_8822C(x) \ + (((x) >> BIT_SHIFT_AVGPERIOD_8822C) & BIT_MASK_AVGPERIOD_8822C) +#define BIT_SET_AVGPERIOD_8822C(x, v) \ + (BIT_CLEAR_AVGPERIOD_8822C(x) | BIT_AVGPERIOD_8822C(v)) + +/* 2 REG_VO_ADMTIME_8822C */ + +#define BIT_SHIFT_VO_ADMITTED_TIME_8822C 0 +#define BIT_MASK_VO_ADMITTED_TIME_8822C 0xffff +#define BIT_VO_ADMITTED_TIME_8822C(x) \ + (((x) & BIT_MASK_VO_ADMITTED_TIME_8822C) \ + << BIT_SHIFT_VO_ADMITTED_TIME_8822C) +#define BITS_VO_ADMITTED_TIME_8822C \ + (BIT_MASK_VO_ADMITTED_TIME_8822C << BIT_SHIFT_VO_ADMITTED_TIME_8822C) +#define BIT_CLEAR_VO_ADMITTED_TIME_8822C(x) \ + ((x) & (~BITS_VO_ADMITTED_TIME_8822C)) +#define BIT_GET_VO_ADMITTED_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822C) & \ + BIT_MASK_VO_ADMITTED_TIME_8822C) +#define BIT_SET_VO_ADMITTED_TIME_8822C(x, v) \ + (BIT_CLEAR_VO_ADMITTED_TIME_8822C(x) | BIT_VO_ADMITTED_TIME_8822C(v)) + +/* 2 REG_VI_ADMTIME_8822C */ + +#define BIT_SHIFT_VI_ADMITTED_TIME_8822C 0 +#define BIT_MASK_VI_ADMITTED_TIME_8822C 0xffff +#define BIT_VI_ADMITTED_TIME_8822C(x) \ + (((x) & BIT_MASK_VI_ADMITTED_TIME_8822C) \ + << BIT_SHIFT_VI_ADMITTED_TIME_8822C) +#define BITS_VI_ADMITTED_TIME_8822C \ + (BIT_MASK_VI_ADMITTED_TIME_8822C << BIT_SHIFT_VI_ADMITTED_TIME_8822C) +#define BIT_CLEAR_VI_ADMITTED_TIME_8822C(x) \ + ((x) & (~BITS_VI_ADMITTED_TIME_8822C)) +#define BIT_GET_VI_ADMITTED_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822C) & \ + BIT_MASK_VI_ADMITTED_TIME_8822C) +#define BIT_SET_VI_ADMITTED_TIME_8822C(x, v) \ + (BIT_CLEAR_VI_ADMITTED_TIME_8822C(x) | BIT_VI_ADMITTED_TIME_8822C(v)) + +/* 2 REG_BE_ADMTIME_8822C */ + +#define BIT_SHIFT_BE_ADMITTED_TIME_8822C 0 +#define BIT_MASK_BE_ADMITTED_TIME_8822C 0xffff +#define BIT_BE_ADMITTED_TIME_8822C(x) \ + (((x) & BIT_MASK_BE_ADMITTED_TIME_8822C) \ + << BIT_SHIFT_BE_ADMITTED_TIME_8822C) +#define BITS_BE_ADMITTED_TIME_8822C \ + (BIT_MASK_BE_ADMITTED_TIME_8822C << BIT_SHIFT_BE_ADMITTED_TIME_8822C) +#define BIT_CLEAR_BE_ADMITTED_TIME_8822C(x) \ + ((x) & (~BITS_BE_ADMITTED_TIME_8822C)) +#define BIT_GET_BE_ADMITTED_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822C) & \ + BIT_MASK_BE_ADMITTED_TIME_8822C) +#define BIT_SET_BE_ADMITTED_TIME_8822C(x, v) \ + (BIT_CLEAR_BE_ADMITTED_TIME_8822C(x) | BIT_BE_ADMITTED_TIME_8822C(v)) + +/* 2 REG_MAC_HEADER_NAV_OFFSET_8822C */ + +#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C 0 +#define BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C 0xff +#define BIT_MAC_HEADER_NAV_OFFSET_8822C(x) \ + (((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C) \ + << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C) +#define BITS_MAC_HEADER_NAV_OFFSET_8822C \ + (BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C \ + << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C) +#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8822C(x) \ + ((x) & (~BITS_MAC_HEADER_NAV_OFFSET_8822C)) +#define BIT_GET_MAC_HEADER_NAV_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C) & \ + BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C) +#define BIT_SET_MAC_HEADER_NAV_OFFSET_8822C(x, v) \ + (BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8822C(x) | \ + BIT_MAC_HEADER_NAV_OFFSET_8822C(v)) + +/* 2 REG_DIS_NDPA_NAV_CHECK_8822C */ +#define BIT_CHG_POWER_BCN_AREA_V1_8822C BIT(1) +#define BIT_DIS_NDPA_NAV_CHECK_8822C BIT(0) + +/* 2 REG_EDCA_RANDOM_GEN_8822C */ + +#define BIT_SHIFT_RANDOM_GEN_8822C 0 +#define BIT_MASK_RANDOM_GEN_8822C 0xffffff +#define BIT_RANDOM_GEN_8822C(x) \ + (((x) & BIT_MASK_RANDOM_GEN_8822C) << BIT_SHIFT_RANDOM_GEN_8822C) +#define BITS_RANDOM_GEN_8822C \ + (BIT_MASK_RANDOM_GEN_8822C << BIT_SHIFT_RANDOM_GEN_8822C) +#define BIT_CLEAR_RANDOM_GEN_8822C(x) ((x) & (~BITS_RANDOM_GEN_8822C)) +#define BIT_GET_RANDOM_GEN_8822C(x) \ + (((x) >> BIT_SHIFT_RANDOM_GEN_8822C) & BIT_MASK_RANDOM_GEN_8822C) +#define BIT_SET_RANDOM_GEN_8822C(x, v) \ + (BIT_CLEAR_RANDOM_GEN_8822C(x) | BIT_RANDOM_GEN_8822C(v)) + +/* 2 REG_TXCMD_NOA_SEL_8822C */ + +#define BIT_SHIFT_NOA_SEL_V2_8822C 4 +#define BIT_MASK_NOA_SEL_V2_8822C 0x7 +#define BIT_NOA_SEL_V2_8822C(x) \ + (((x) & BIT_MASK_NOA_SEL_V2_8822C) << BIT_SHIFT_NOA_SEL_V2_8822C) +#define BITS_NOA_SEL_V2_8822C \ + (BIT_MASK_NOA_SEL_V2_8822C << BIT_SHIFT_NOA_SEL_V2_8822C) +#define BIT_CLEAR_NOA_SEL_V2_8822C(x) ((x) & (~BITS_NOA_SEL_V2_8822C)) +#define BIT_GET_NOA_SEL_V2_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_SEL_V2_8822C) & BIT_MASK_NOA_SEL_V2_8822C) +#define BIT_SET_NOA_SEL_V2_8822C(x, v) \ + (BIT_CLEAR_NOA_SEL_V2_8822C(x) | BIT_NOA_SEL_V2_8822C(v)) + +#define BIT_SHIFT_TXCMD_SEG_SEL_8822C 0 +#define BIT_MASK_TXCMD_SEG_SEL_8822C 0xf +#define BIT_TXCMD_SEG_SEL_8822C(x) \ + (((x) & BIT_MASK_TXCMD_SEG_SEL_8822C) << BIT_SHIFT_TXCMD_SEG_SEL_8822C) +#define BITS_TXCMD_SEG_SEL_8822C \ + (BIT_MASK_TXCMD_SEG_SEL_8822C << BIT_SHIFT_TXCMD_SEG_SEL_8822C) +#define BIT_CLEAR_TXCMD_SEG_SEL_8822C(x) ((x) & (~BITS_TXCMD_SEG_SEL_8822C)) +#define BIT_GET_TXCMD_SEG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822C) & BIT_MASK_TXCMD_SEG_SEL_8822C) +#define BIT_SET_TXCMD_SEG_SEL_8822C(x, v) \ + (BIT_CLEAR_TXCMD_SEG_SEL_8822C(x) | BIT_TXCMD_SEG_SEL_8822C(v)) + +/* 2 REG_32K_CLK_SEL_8822C */ +#define BIT_R_BCNERR_CNT_EN_8822C BIT(20) + +#define BIT_SHIFT_R_BCNERR_PORT_SEL_8822C 16 +#define BIT_MASK_R_BCNERR_PORT_SEL_8822C 0x7 +#define BIT_R_BCNERR_PORT_SEL_8822C(x) \ + (((x) & BIT_MASK_R_BCNERR_PORT_SEL_8822C) \ + << BIT_SHIFT_R_BCNERR_PORT_SEL_8822C) +#define BITS_R_BCNERR_PORT_SEL_8822C \ + (BIT_MASK_R_BCNERR_PORT_SEL_8822C << BIT_SHIFT_R_BCNERR_PORT_SEL_8822C) +#define BIT_CLEAR_R_BCNERR_PORT_SEL_8822C(x) \ + ((x) & (~BITS_R_BCNERR_PORT_SEL_8822C)) +#define BIT_GET_R_BCNERR_PORT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_BCNERR_PORT_SEL_8822C) & \ + BIT_MASK_R_BCNERR_PORT_SEL_8822C) +#define BIT_SET_R_BCNERR_PORT_SEL_8822C(x, v) \ + (BIT_CLEAR_R_BCNERR_PORT_SEL_8822C(x) | BIT_R_BCNERR_PORT_SEL_8822C(v)) + +#define BIT_SHIFT_R_TXPAUSE1_8822C 8 +#define BIT_MASK_R_TXPAUSE1_8822C 0xff +#define BIT_R_TXPAUSE1_8822C(x) \ + (((x) & BIT_MASK_R_TXPAUSE1_8822C) << BIT_SHIFT_R_TXPAUSE1_8822C) +#define BITS_R_TXPAUSE1_8822C \ + (BIT_MASK_R_TXPAUSE1_8822C << BIT_SHIFT_R_TXPAUSE1_8822C) +#define BIT_CLEAR_R_TXPAUSE1_8822C(x) ((x) & (~BITS_R_TXPAUSE1_8822C)) +#define BIT_GET_R_TXPAUSE1_8822C(x) \ + (((x) >> BIT_SHIFT_R_TXPAUSE1_8822C) & BIT_MASK_R_TXPAUSE1_8822C) +#define BIT_SET_R_TXPAUSE1_8822C(x, v) \ + (BIT_CLEAR_R_TXPAUSE1_8822C(x) | BIT_R_TXPAUSE1_8822C(v)) + +#define BIT_SLEEP_32K_EN_V1_8822C BIT(2) + +#define BIT_SHIFT_BW_CFG_8822C 0 +#define BIT_MASK_BW_CFG_8822C 0x3 +#define BIT_BW_CFG_8822C(x) \ + (((x) & BIT_MASK_BW_CFG_8822C) << BIT_SHIFT_BW_CFG_8822C) +#define BITS_BW_CFG_8822C (BIT_MASK_BW_CFG_8822C << BIT_SHIFT_BW_CFG_8822C) +#define BIT_CLEAR_BW_CFG_8822C(x) ((x) & (~BITS_BW_CFG_8822C)) +#define BIT_GET_BW_CFG_8822C(x) \ + (((x) >> BIT_SHIFT_BW_CFG_8822C) & BIT_MASK_BW_CFG_8822C) +#define BIT_SET_BW_CFG_8822C(x, v) \ + (BIT_CLEAR_BW_CFG_8822C(x) | BIT_BW_CFG_8822C(v)) + +/* 2 REG_EARLYINT_ADJUST_8822C */ + +#define BIT_SHIFT_RXBCN_TIMER_8822C 16 +#define BIT_MASK_RXBCN_TIMER_8822C 0xffff +#define BIT_RXBCN_TIMER_8822C(x) \ + (((x) & BIT_MASK_RXBCN_TIMER_8822C) << BIT_SHIFT_RXBCN_TIMER_8822C) +#define BITS_RXBCN_TIMER_8822C \ + (BIT_MASK_RXBCN_TIMER_8822C << BIT_SHIFT_RXBCN_TIMER_8822C) +#define BIT_CLEAR_RXBCN_TIMER_8822C(x) ((x) & (~BITS_RXBCN_TIMER_8822C)) +#define BIT_GET_RXBCN_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_RXBCN_TIMER_8822C) & BIT_MASK_RXBCN_TIMER_8822C) +#define BIT_SET_RXBCN_TIMER_8822C(x, v) \ + (BIT_CLEAR_RXBCN_TIMER_8822C(x) | BIT_RXBCN_TIMER_8822C(v)) + +#define BIT_SHIFT_R_ERLYINTADJ_8822C 0 +#define BIT_MASK_R_ERLYINTADJ_8822C 0xffff +#define BIT_R_ERLYINTADJ_8822C(x) \ + (((x) & BIT_MASK_R_ERLYINTADJ_8822C) << BIT_SHIFT_R_ERLYINTADJ_8822C) +#define BITS_R_ERLYINTADJ_8822C \ + (BIT_MASK_R_ERLYINTADJ_8822C << BIT_SHIFT_R_ERLYINTADJ_8822C) +#define BIT_CLEAR_R_ERLYINTADJ_8822C(x) ((x) & (~BITS_R_ERLYINTADJ_8822C)) +#define BIT_GET_R_ERLYINTADJ_8822C(x) \ + (((x) >> BIT_SHIFT_R_ERLYINTADJ_8822C) & BIT_MASK_R_ERLYINTADJ_8822C) +#define BIT_SET_R_ERLYINTADJ_8822C(x, v) \ + (BIT_CLEAR_R_ERLYINTADJ_8822C(x) | BIT_R_ERLYINTADJ_8822C(v)) + +/* 2 REG_BCNERR_CNT_8822C */ + +#define BIT_SHIFT_BCNERR_CNT_OTHERS_8822C 24 +#define BIT_MASK_BCNERR_CNT_OTHERS_8822C 0xff +#define BIT_BCNERR_CNT_OTHERS_8822C(x) \ + (((x) & BIT_MASK_BCNERR_CNT_OTHERS_8822C) \ + << BIT_SHIFT_BCNERR_CNT_OTHERS_8822C) +#define BITS_BCNERR_CNT_OTHERS_8822C \ + (BIT_MASK_BCNERR_CNT_OTHERS_8822C << BIT_SHIFT_BCNERR_CNT_OTHERS_8822C) +#define BIT_CLEAR_BCNERR_CNT_OTHERS_8822C(x) \ + ((x) & (~BITS_BCNERR_CNT_OTHERS_8822C)) +#define BIT_GET_BCNERR_CNT_OTHERS_8822C(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8822C) & \ + BIT_MASK_BCNERR_CNT_OTHERS_8822C) +#define BIT_SET_BCNERR_CNT_OTHERS_8822C(x, v) \ + (BIT_CLEAR_BCNERR_CNT_OTHERS_8822C(x) | BIT_BCNERR_CNT_OTHERS_8822C(v)) + +#define BIT_SHIFT_BCNERR_CNT_INVALID_8822C 16 +#define BIT_MASK_BCNERR_CNT_INVALID_8822C 0xff +#define BIT_BCNERR_CNT_INVALID_8822C(x) \ + (((x) & BIT_MASK_BCNERR_CNT_INVALID_8822C) \ + << BIT_SHIFT_BCNERR_CNT_INVALID_8822C) +#define BITS_BCNERR_CNT_INVALID_8822C \ + (BIT_MASK_BCNERR_CNT_INVALID_8822C \ + << BIT_SHIFT_BCNERR_CNT_INVALID_8822C) +#define BIT_CLEAR_BCNERR_CNT_INVALID_8822C(x) \ + ((x) & (~BITS_BCNERR_CNT_INVALID_8822C)) +#define BIT_GET_BCNERR_CNT_INVALID_8822C(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8822C) & \ + BIT_MASK_BCNERR_CNT_INVALID_8822C) +#define BIT_SET_BCNERR_CNT_INVALID_8822C(x, v) \ + (BIT_CLEAR_BCNERR_CNT_INVALID_8822C(x) | \ + BIT_BCNERR_CNT_INVALID_8822C(v)) + +#define BIT_SHIFT_BCNERR_CNT_MAC_8822C 8 +#define BIT_MASK_BCNERR_CNT_MAC_8822C 0xff +#define BIT_BCNERR_CNT_MAC_8822C(x) \ + (((x) & BIT_MASK_BCNERR_CNT_MAC_8822C) \ + << BIT_SHIFT_BCNERR_CNT_MAC_8822C) +#define BITS_BCNERR_CNT_MAC_8822C \ + (BIT_MASK_BCNERR_CNT_MAC_8822C << BIT_SHIFT_BCNERR_CNT_MAC_8822C) +#define BIT_CLEAR_BCNERR_CNT_MAC_8822C(x) ((x) & (~BITS_BCNERR_CNT_MAC_8822C)) +#define BIT_GET_BCNERR_CNT_MAC_8822C(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8822C) & \ + BIT_MASK_BCNERR_CNT_MAC_8822C) +#define BIT_SET_BCNERR_CNT_MAC_8822C(x, v) \ + (BIT_CLEAR_BCNERR_CNT_MAC_8822C(x) | BIT_BCNERR_CNT_MAC_8822C(v)) + +#define BIT_SHIFT_BCNERR_CNT_CCA_8822C 0 +#define BIT_MASK_BCNERR_CNT_CCA_8822C 0xff +#define BIT_BCNERR_CNT_CCA_8822C(x) \ + (((x) & BIT_MASK_BCNERR_CNT_CCA_8822C) \ + << BIT_SHIFT_BCNERR_CNT_CCA_8822C) +#define BITS_BCNERR_CNT_CCA_8822C \ + (BIT_MASK_BCNERR_CNT_CCA_8822C << BIT_SHIFT_BCNERR_CNT_CCA_8822C) +#define BIT_CLEAR_BCNERR_CNT_CCA_8822C(x) ((x) & (~BITS_BCNERR_CNT_CCA_8822C)) +#define BIT_GET_BCNERR_CNT_CCA_8822C(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8822C) & \ + BIT_MASK_BCNERR_CNT_CCA_8822C) +#define BIT_SET_BCNERR_CNT_CCA_8822C(x, v) \ + (BIT_CLEAR_BCNERR_CNT_CCA_8822C(x) | BIT_BCNERR_CNT_CCA_8822C(v)) + +/* 2 REG_BCNERR_CNT_2_8822C */ + +#define BIT_SHIFT_BCNERR_CNT_EDCCA_8822C 0 +#define BIT_MASK_BCNERR_CNT_EDCCA_8822C 0xff +#define BIT_BCNERR_CNT_EDCCA_8822C(x) \ + (((x) & BIT_MASK_BCNERR_CNT_EDCCA_8822C) \ + << BIT_SHIFT_BCNERR_CNT_EDCCA_8822C) +#define BITS_BCNERR_CNT_EDCCA_8822C \ + (BIT_MASK_BCNERR_CNT_EDCCA_8822C << BIT_SHIFT_BCNERR_CNT_EDCCA_8822C) +#define BIT_CLEAR_BCNERR_CNT_EDCCA_8822C(x) \ + ((x) & (~BITS_BCNERR_CNT_EDCCA_8822C)) +#define BIT_GET_BCNERR_CNT_EDCCA_8822C(x) \ + (((x) >> BIT_SHIFT_BCNERR_CNT_EDCCA_8822C) & \ + BIT_MASK_BCNERR_CNT_EDCCA_8822C) +#define BIT_SET_BCNERR_CNT_EDCCA_8822C(x, v) \ + (BIT_CLEAR_BCNERR_CNT_EDCCA_8822C(x) | BIT_BCNERR_CNT_EDCCA_8822C(v)) + +/* 2 REG_NOA_PARAM_8822C */ + +#define BIT_SHIFT_NOA_DURATION_V1_8822C 0 +#define BIT_MASK_NOA_DURATION_V1_8822C 0xffffffffL +#define BIT_NOA_DURATION_V1_8822C(x) \ + (((x) & BIT_MASK_NOA_DURATION_V1_8822C) \ + << BIT_SHIFT_NOA_DURATION_V1_8822C) +#define BITS_NOA_DURATION_V1_8822C \ + (BIT_MASK_NOA_DURATION_V1_8822C << BIT_SHIFT_NOA_DURATION_V1_8822C) +#define BIT_CLEAR_NOA_DURATION_V1_8822C(x) ((x) & (~BITS_NOA_DURATION_V1_8822C)) +#define BIT_GET_NOA_DURATION_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_DURATION_V1_8822C) & \ + BIT_MASK_NOA_DURATION_V1_8822C) +#define BIT_SET_NOA_DURATION_V1_8822C(x, v) \ + (BIT_CLEAR_NOA_DURATION_V1_8822C(x) | BIT_NOA_DURATION_V1_8822C(v)) + +/* 2 REG_NOA_PARAM_1_8822C */ + +#define BIT_SHIFT_NOA_INTERVAL_V1_8822C 0 +#define BIT_MASK_NOA_INTERVAL_V1_8822C 0xffffffffL +#define BIT_NOA_INTERVAL_V1_8822C(x) \ + (((x) & BIT_MASK_NOA_INTERVAL_V1_8822C) \ + << BIT_SHIFT_NOA_INTERVAL_V1_8822C) +#define BITS_NOA_INTERVAL_V1_8822C \ + (BIT_MASK_NOA_INTERVAL_V1_8822C << BIT_SHIFT_NOA_INTERVAL_V1_8822C) +#define BIT_CLEAR_NOA_INTERVAL_V1_8822C(x) ((x) & (~BITS_NOA_INTERVAL_V1_8822C)) +#define BIT_GET_NOA_INTERVAL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8822C) & \ + BIT_MASK_NOA_INTERVAL_V1_8822C) +#define BIT_SET_NOA_INTERVAL_V1_8822C(x, v) \ + (BIT_CLEAR_NOA_INTERVAL_V1_8822C(x) | BIT_NOA_INTERVAL_V1_8822C(v)) + +/* 2 REG_NOA_PARAM_2_8822C */ + +#define BIT_SHIFT_NOA_START_TIME_V1_8822C 0 +#define BIT_MASK_NOA_START_TIME_V1_8822C 0xffffffffL +#define BIT_NOA_START_TIME_V1_8822C(x) \ + (((x) & BIT_MASK_NOA_START_TIME_V1_8822C) \ + << BIT_SHIFT_NOA_START_TIME_V1_8822C) +#define BITS_NOA_START_TIME_V1_8822C \ + (BIT_MASK_NOA_START_TIME_V1_8822C << BIT_SHIFT_NOA_START_TIME_V1_8822C) +#define BIT_CLEAR_NOA_START_TIME_V1_8822C(x) \ + ((x) & (~BITS_NOA_START_TIME_V1_8822C)) +#define BIT_GET_NOA_START_TIME_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8822C) & \ + BIT_MASK_NOA_START_TIME_V1_8822C) +#define BIT_SET_NOA_START_TIME_V1_8822C(x, v) \ + (BIT_CLEAR_NOA_START_TIME_V1_8822C(x) | BIT_NOA_START_TIME_V1_8822C(v)) + +/* 2 REG_NOA_PARAM_3_8822C */ + +#define BIT_SHIFT_NOA_COUNT_V1_8822C 0 +#define BIT_MASK_NOA_COUNT_V1_8822C 0xffffffffL +#define BIT_NOA_COUNT_V1_8822C(x) \ + (((x) & BIT_MASK_NOA_COUNT_V1_8822C) << BIT_SHIFT_NOA_COUNT_V1_8822C) +#define BITS_NOA_COUNT_V1_8822C \ + (BIT_MASK_NOA_COUNT_V1_8822C << BIT_SHIFT_NOA_COUNT_V1_8822C) +#define BIT_CLEAR_NOA_COUNT_V1_8822C(x) ((x) & (~BITS_NOA_COUNT_V1_8822C)) +#define BIT_GET_NOA_COUNT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NOA_COUNT_V1_8822C) & BIT_MASK_NOA_COUNT_V1_8822C) +#define BIT_SET_NOA_COUNT_V1_8822C(x, v) \ + (BIT_CLEAR_NOA_COUNT_V1_8822C(x) | BIT_NOA_COUNT_V1_8822C(v)) + +/* 2 REG_P2P_RST_8822C */ +#define BIT_P2P2_PWR_RST1_8822C BIT(5) +#define BIT_P2P2_PWR_RST0_8822C BIT(4) +#define BIT_P2P1_PWR_RST1_8822C BIT(3) +#define BIT_P2P1_PWR_RST0_8822C BIT(2) +#define BIT_P2P_PWR_RST1_V1_8822C BIT(1) +#define BIT_P2P_PWR_RST0_V1_8822C BIT(0) + +/* 2 REG_SCHEDULER_RST_8822C */ +#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8822C BIT(2) +#define BIT_SYNC_CLI_ONCE_BY_TBTT_8822C BIT(1) +#define BIT_SCHEDULER_RST_V1_8822C BIT(0) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SCH_DBG_VALUE_8822C */ + +#define BIT_SHIFT_SCH_DBG_VALUE_8822C 0 +#define BIT_MASK_SCH_DBG_VALUE_8822C 0xffffffffL +#define BIT_SCH_DBG_VALUE_8822C(x) \ + (((x) & BIT_MASK_SCH_DBG_VALUE_8822C) << BIT_SHIFT_SCH_DBG_VALUE_8822C) +#define BITS_SCH_DBG_VALUE_8822C \ + (BIT_MASK_SCH_DBG_VALUE_8822C << BIT_SHIFT_SCH_DBG_VALUE_8822C) +#define BIT_CLEAR_SCH_DBG_VALUE_8822C(x) ((x) & (~BITS_SCH_DBG_VALUE_8822C)) +#define BIT_GET_SCH_DBG_VALUE_8822C(x) \ + (((x) >> BIT_SHIFT_SCH_DBG_VALUE_8822C) & BIT_MASK_SCH_DBG_VALUE_8822C) +#define BIT_SET_SCH_DBG_VALUE_8822C(x, v) \ + (BIT_CLEAR_SCH_DBG_VALUE_8822C(x) | BIT_SCH_DBG_VALUE_8822C(v)) + +/* 2 REG_SCH_TXCMD_8822C */ + +#define BIT_SHIFT_SCH_TXCMD_8822C 0 +#define BIT_MASK_SCH_TXCMD_8822C 0xffffffffL +#define BIT_SCH_TXCMD_8822C(x) \ + (((x) & BIT_MASK_SCH_TXCMD_8822C) << BIT_SHIFT_SCH_TXCMD_8822C) +#define BITS_SCH_TXCMD_8822C \ + (BIT_MASK_SCH_TXCMD_8822C << BIT_SHIFT_SCH_TXCMD_8822C) +#define BIT_CLEAR_SCH_TXCMD_8822C(x) ((x) & (~BITS_SCH_TXCMD_8822C)) +#define BIT_GET_SCH_TXCMD_8822C(x) \ + (((x) >> BIT_SHIFT_SCH_TXCMD_8822C) & BIT_MASK_SCH_TXCMD_8822C) +#define BIT_SET_SCH_TXCMD_8822C(x, v) \ + (BIT_CLEAR_SCH_TXCMD_8822C(x) | BIT_SCH_TXCMD_8822C(v)) + +/* 2 REG_PAGE5_DUMMY_8822C */ + +/* 2 REG_CPUMGQ_TX_TIMER_8822C */ + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C 0xffffffffL +#define BIT_CPUMGQ_TX_TIMER_V1_8822C(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C) +#define BITS_CPUMGQ_TX_TIMER_V1_8822C \ + (BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822C(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8822C)) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C) & \ + BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C) +#define BIT_SET_CPUMGQ_TX_TIMER_V1_8822C(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822C(x) | \ + BIT_CPUMGQ_TX_TIMER_V1_8822C(v)) + +/* 2 REG_PS_TIMER_A_8822C */ + +#define BIT_SHIFT_PS_TIMER_A_V1_8822C 0 +#define BIT_MASK_PS_TIMER_A_V1_8822C 0xffffffffL +#define BIT_PS_TIMER_A_V1_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_V1_8822C) << BIT_SHIFT_PS_TIMER_A_V1_8822C) +#define BITS_PS_TIMER_A_V1_8822C \ + (BIT_MASK_PS_TIMER_A_V1_8822C << BIT_SHIFT_PS_TIMER_A_V1_8822C) +#define BIT_CLEAR_PS_TIMER_A_V1_8822C(x) ((x) & (~BITS_PS_TIMER_A_V1_8822C)) +#define BIT_GET_PS_TIMER_A_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822C) & BIT_MASK_PS_TIMER_A_V1_8822C) +#define BIT_SET_PS_TIMER_A_V1_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_V1_8822C(x) | BIT_PS_TIMER_A_V1_8822C(v)) + +/* 2 REG_PS_TIMER_B_8822C */ + +#define BIT_SHIFT_PS_TIMER_B_V1_8822C 0 +#define BIT_MASK_PS_TIMER_B_V1_8822C 0xffffffffL +#define BIT_PS_TIMER_B_V1_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_V1_8822C) << BIT_SHIFT_PS_TIMER_B_V1_8822C) +#define BITS_PS_TIMER_B_V1_8822C \ + (BIT_MASK_PS_TIMER_B_V1_8822C << BIT_SHIFT_PS_TIMER_B_V1_8822C) +#define BIT_CLEAR_PS_TIMER_B_V1_8822C(x) ((x) & (~BITS_PS_TIMER_B_V1_8822C)) +#define BIT_GET_PS_TIMER_B_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822C) & BIT_MASK_PS_TIMER_B_V1_8822C) +#define BIT_SET_PS_TIMER_B_V1_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_V1_8822C(x) | BIT_PS_TIMER_B_V1_8822C(v)) + +/* 2 REG_PS_TIMER_C_8822C */ + +#define BIT_SHIFT_PS_TIMER_C_V1_8822C 0 +#define BIT_MASK_PS_TIMER_C_V1_8822C 0xffffffffL +#define BIT_PS_TIMER_C_V1_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_V1_8822C) << BIT_SHIFT_PS_TIMER_C_V1_8822C) +#define BITS_PS_TIMER_C_V1_8822C \ + (BIT_MASK_PS_TIMER_C_V1_8822C << BIT_SHIFT_PS_TIMER_C_V1_8822C) +#define BIT_CLEAR_PS_TIMER_C_V1_8822C(x) ((x) & (~BITS_PS_TIMER_C_V1_8822C)) +#define BIT_GET_PS_TIMER_C_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822C) & BIT_MASK_PS_TIMER_C_V1_8822C) +#define BIT_SET_PS_TIMER_C_V1_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_V1_8822C(x) | BIT_PS_TIMER_C_V1_8822C(v)) + +/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822C */ +#define BIT_CPUMGQ_TIMER_EN_8822C BIT(31) +#define BIT_CPUMGQ_TX_EN_8822C BIT(28) + +#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C 24 +#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C 0x7 +#define BIT_CPUMGQ_TIMER_TSF_SEL_8822C(x) \ + (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C) \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C) +#define BITS_CPUMGQ_TIMER_TSF_SEL_8822C \ + (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C \ + << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C) +#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822C(x) \ + ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8822C)) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C) & \ + BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C) +#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8822C(x, v) \ + (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822C(x) | \ + BIT_CPUMGQ_TIMER_TSF_SEL_8822C(v)) + +#define BIT_PS_TIMER_C_EN_8822C BIT(23) + +#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C 16 +#define BIT_MASK_PS_TIMER_C_TSF_SEL_8822C 0x7 +#define BIT_PS_TIMER_C_TSF_SEL_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822C) \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C) +#define BITS_PS_TIMER_C_TSF_SEL_8822C \ + (BIT_MASK_PS_TIMER_C_TSF_SEL_8822C \ + << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C) +#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822C(x) \ + ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8822C)) +#define BIT_GET_PS_TIMER_C_TSF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C) & \ + BIT_MASK_PS_TIMER_C_TSF_SEL_8822C) +#define BIT_SET_PS_TIMER_C_TSF_SEL_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822C(x) | \ + BIT_PS_TIMER_C_TSF_SEL_8822C(v)) + +#define BIT_PS_TIMER_B_EN_8822C BIT(15) + +#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C 8 +#define BIT_MASK_PS_TIMER_B_TSF_SEL_8822C 0x7 +#define BIT_PS_TIMER_B_TSF_SEL_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822C) \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C) +#define BITS_PS_TIMER_B_TSF_SEL_8822C \ + (BIT_MASK_PS_TIMER_B_TSF_SEL_8822C \ + << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C) +#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822C(x) \ + ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8822C)) +#define BIT_GET_PS_TIMER_B_TSF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C) & \ + BIT_MASK_PS_TIMER_B_TSF_SEL_8822C) +#define BIT_SET_PS_TIMER_B_TSF_SEL_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822C(x) | \ + BIT_PS_TIMER_B_TSF_SEL_8822C(v)) + +#define BIT_PS_TIMER_A_EN_8822C BIT(7) + +#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C 0 +#define BIT_MASK_PS_TIMER_A_TSF_SEL_8822C 0x7 +#define BIT_PS_TIMER_A_TSF_SEL_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822C) \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C) +#define BITS_PS_TIMER_A_TSF_SEL_8822C \ + (BIT_MASK_PS_TIMER_A_TSF_SEL_8822C \ + << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C) +#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822C(x) \ + ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8822C)) +#define BIT_GET_PS_TIMER_A_TSF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C) & \ + BIT_MASK_PS_TIMER_A_TSF_SEL_8822C) +#define BIT_SET_PS_TIMER_A_TSF_SEL_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822C(x) | \ + BIT_PS_TIMER_A_TSF_SEL_8822C(v)) + +/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822C */ + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C 0xff +#define BIT_CPUMGQ_TX_TIMER_EARLY_8822C(x) \ + (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C) \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C) +#define BITS_CPUMGQ_TX_TIMER_EARLY_8822C \ + (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C \ + << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C) +#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822C(x) \ + ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8822C)) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822C(x) \ + (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C) & \ + BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C) +#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8822C(x, v) \ + (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822C(x) | \ + BIT_CPUMGQ_TX_TIMER_EARLY_8822C(v)) + +/* 2 REG_PS_TIMER_A_EARLY_8822C */ + +#define BIT_SHIFT_PS_TIMER_A_EARLY_8822C 0 +#define BIT_MASK_PS_TIMER_A_EARLY_8822C 0xff +#define BIT_PS_TIMER_A_EARLY_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_A_EARLY_8822C) \ + << BIT_SHIFT_PS_TIMER_A_EARLY_8822C) +#define BITS_PS_TIMER_A_EARLY_8822C \ + (BIT_MASK_PS_TIMER_A_EARLY_8822C << BIT_SHIFT_PS_TIMER_A_EARLY_8822C) +#define BIT_CLEAR_PS_TIMER_A_EARLY_8822C(x) \ + ((x) & (~BITS_PS_TIMER_A_EARLY_8822C)) +#define BIT_GET_PS_TIMER_A_EARLY_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822C) & \ + BIT_MASK_PS_TIMER_A_EARLY_8822C) +#define BIT_SET_PS_TIMER_A_EARLY_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_A_EARLY_8822C(x) | BIT_PS_TIMER_A_EARLY_8822C(v)) + +/* 2 REG_PS_TIMER_B_EARLY_8822C */ + +#define BIT_SHIFT_PS_TIMER_B_EARLY_8822C 0 +#define BIT_MASK_PS_TIMER_B_EARLY_8822C 0xff +#define BIT_PS_TIMER_B_EARLY_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_B_EARLY_8822C) \ + << BIT_SHIFT_PS_TIMER_B_EARLY_8822C) +#define BITS_PS_TIMER_B_EARLY_8822C \ + (BIT_MASK_PS_TIMER_B_EARLY_8822C << BIT_SHIFT_PS_TIMER_B_EARLY_8822C) +#define BIT_CLEAR_PS_TIMER_B_EARLY_8822C(x) \ + ((x) & (~BITS_PS_TIMER_B_EARLY_8822C)) +#define BIT_GET_PS_TIMER_B_EARLY_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822C) & \ + BIT_MASK_PS_TIMER_B_EARLY_8822C) +#define BIT_SET_PS_TIMER_B_EARLY_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_B_EARLY_8822C(x) | BIT_PS_TIMER_B_EARLY_8822C(v)) + +/* 2 REG_PS_TIMER_C_EARLY_8822C */ + +#define BIT_SHIFT_PS_TIMER_C_EARLY_8822C 0 +#define BIT_MASK_PS_TIMER_C_EARLY_8822C 0xff +#define BIT_PS_TIMER_C_EARLY_8822C(x) \ + (((x) & BIT_MASK_PS_TIMER_C_EARLY_8822C) \ + << BIT_SHIFT_PS_TIMER_C_EARLY_8822C) +#define BITS_PS_TIMER_C_EARLY_8822C \ + (BIT_MASK_PS_TIMER_C_EARLY_8822C << BIT_SHIFT_PS_TIMER_C_EARLY_8822C) +#define BIT_CLEAR_PS_TIMER_C_EARLY_8822C(x) \ + ((x) & (~BITS_PS_TIMER_C_EARLY_8822C)) +#define BIT_GET_PS_TIMER_C_EARLY_8822C(x) \ + (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822C) & \ + BIT_MASK_PS_TIMER_C_EARLY_8822C) +#define BIT_SET_PS_TIMER_C_EARLY_8822C(x, v) \ + (BIT_CLEAR_PS_TIMER_C_EARLY_8822C(x) | BIT_PS_TIMER_C_EARLY_8822C(v)) + +/* 2 REG_CPUMGQ_PARAMETER_8822C */ + +/* 2 REG_NOT_VALID_8822C */ +#define BIT_MAC_STOP_CPUMGQ_8822C BIT(16) + +#define BIT_SHIFT_CW_8822C 8 +#define BIT_MASK_CW_8822C 0xff +#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C) +#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C) +#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C)) +#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C) +#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v)) + +#define BIT_SHIFT_AIFS_8822C 0 +#define BIT_MASK_AIFS_8822C 0xff +#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C) +#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C) +#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C)) +#define BIT_GET_AIFS_8822C(x) \ + (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C) +#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_TSF_SYNC_ADJ_8822C */ + +#define BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C 16 +#define BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C 0xffff +#define BIT_R_P0_TSFT_ADJ_VAL_8822C(x) \ + (((x) & BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C) \ + << BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C) +#define BITS_R_P0_TSFT_ADJ_VAL_8822C \ + (BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C << BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C) +#define BIT_CLEAR_R_P0_TSFT_ADJ_VAL_8822C(x) \ + ((x) & (~BITS_R_P0_TSFT_ADJ_VAL_8822C)) +#define BIT_GET_R_P0_TSFT_ADJ_VAL_8822C(x) \ + (((x) >> BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C) & \ + BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C) +#define BIT_SET_R_P0_TSFT_ADJ_VAL_8822C(x, v) \ + (BIT_CLEAR_R_P0_TSFT_ADJ_VAL_8822C(x) | BIT_R_P0_TSFT_ADJ_VAL_8822C(v)) + +#define BIT_R_X_COMP_Y_OVER_8822C BIT(8) + +#define BIT_SHIFT_R_X_SYNC_SEL_8822C 3 +#define BIT_MASK_R_X_SYNC_SEL_8822C 0x7 +#define BIT_R_X_SYNC_SEL_8822C(x) \ + (((x) & BIT_MASK_R_X_SYNC_SEL_8822C) << BIT_SHIFT_R_X_SYNC_SEL_8822C) +#define BITS_R_X_SYNC_SEL_8822C \ + (BIT_MASK_R_X_SYNC_SEL_8822C << BIT_SHIFT_R_X_SYNC_SEL_8822C) +#define BIT_CLEAR_R_X_SYNC_SEL_8822C(x) ((x) & (~BITS_R_X_SYNC_SEL_8822C)) +#define BIT_GET_R_X_SYNC_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_X_SYNC_SEL_8822C) & BIT_MASK_R_X_SYNC_SEL_8822C) +#define BIT_SET_R_X_SYNC_SEL_8822C(x, v) \ + (BIT_CLEAR_R_X_SYNC_SEL_8822C(x) | BIT_R_X_SYNC_SEL_8822C(v)) + +#define BIT_SHIFT_R_SYNC_Y_SEL_8822C 0 +#define BIT_MASK_R_SYNC_Y_SEL_8822C 0x7 +#define BIT_R_SYNC_Y_SEL_8822C(x) \ + (((x) & BIT_MASK_R_SYNC_Y_SEL_8822C) << BIT_SHIFT_R_SYNC_Y_SEL_8822C) +#define BITS_R_SYNC_Y_SEL_8822C \ + (BIT_MASK_R_SYNC_Y_SEL_8822C << BIT_SHIFT_R_SYNC_Y_SEL_8822C) +#define BIT_CLEAR_R_SYNC_Y_SEL_8822C(x) ((x) & (~BITS_R_SYNC_Y_SEL_8822C)) +#define BIT_GET_R_SYNC_Y_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_SYNC_Y_SEL_8822C) & BIT_MASK_R_SYNC_Y_SEL_8822C) +#define BIT_SET_R_SYNC_Y_SEL_8822C(x, v) \ + (BIT_CLEAR_R_SYNC_Y_SEL_8822C(x) | BIT_R_SYNC_Y_SEL_8822C(v)) + +/* 2 REG_TSF_ADJ_VLAUE_8822C */ + +#define BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C 16 +#define BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C 0xffff +#define BIT_R_CLI1_TSFT_ADJ_VAL_8822C(x) \ + (((x) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C) \ + << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C) +#define BITS_R_CLI1_TSFT_ADJ_VAL_8822C \ + (BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C \ + << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C) +#define BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL_8822C(x) \ + ((x) & (~BITS_R_CLI1_TSFT_ADJ_VAL_8822C)) +#define BIT_GET_R_CLI1_TSFT_ADJ_VAL_8822C(x) \ + (((x) >> BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C) & \ + BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C) +#define BIT_SET_R_CLI1_TSFT_ADJ_VAL_8822C(x, v) \ + (BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL_8822C(x) | \ + BIT_R_CLI1_TSFT_ADJ_VAL_8822C(v)) + +#define BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C 0 +#define BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C 0xffff +#define BIT_R_CLI0_TSFT_ADJ_VAL_8822C(x) \ + (((x) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C) \ + << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C) +#define BITS_R_CLI0_TSFT_ADJ_VAL_8822C \ + (BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C \ + << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C) +#define BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL_8822C(x) \ + ((x) & (~BITS_R_CLI0_TSFT_ADJ_VAL_8822C)) +#define BIT_GET_R_CLI0_TSFT_ADJ_VAL_8822C(x) \ + (((x) >> BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C) & \ + BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C) +#define BIT_SET_R_CLI0_TSFT_ADJ_VAL_8822C(x, v) \ + (BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL_8822C(x) | \ + BIT_R_CLI0_TSFT_ADJ_VAL_8822C(v)) + +/* 2 REG_TSF_ADJ_VLAUE_2_8822C */ + +#define BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C 16 +#define BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C 0xffff +#define BIT_R_CLI3_TSFT_ADJ_VAL_8822C(x) \ + (((x) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C) \ + << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C) +#define BITS_R_CLI3_TSFT_ADJ_VAL_8822C \ + (BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C \ + << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C) +#define BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL_8822C(x) \ + ((x) & (~BITS_R_CLI3_TSFT_ADJ_VAL_8822C)) +#define BIT_GET_R_CLI3_TSFT_ADJ_VAL_8822C(x) \ + (((x) >> BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C) & \ + BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C) +#define BIT_SET_R_CLI3_TSFT_ADJ_VAL_8822C(x, v) \ + (BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL_8822C(x) | \ + BIT_R_CLI3_TSFT_ADJ_VAL_8822C(v)) + +#define BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C 0 +#define BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C 0xffff +#define BIT_R_CLI2_TSFT_ADJ_VAL_8822C(x) \ + (((x) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C) \ + << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C) +#define BITS_R_CLI2_TSFT_ADJ_VAL_8822C \ + (BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C \ + << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C) +#define BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL_8822C(x) \ + ((x) & (~BITS_R_CLI2_TSFT_ADJ_VAL_8822C)) +#define BIT_GET_R_CLI2_TSFT_ADJ_VAL_8822C(x) \ + (((x) >> BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C) & \ + BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C) +#define BIT_SET_R_CLI2_TSFT_ADJ_VAL_8822C(x, v) \ + (BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL_8822C(x) | \ + BIT_R_CLI2_TSFT_ADJ_VAL_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C */ +#define BIT_P2PPS_NOA_STOP_TX_HANG_8822C BIT(31) +#define BIT_P2PPS_MACID_PAUSE_EN_8822C BIT(11) +#define BIT_P2PPS__MGQ_PAUSE_8822C BIT(10) +#define BIT_P2PPS__HIQ_PAUSE_8822C BIT(9) +#define BIT_P2PPS__BCNQ_PAUSE_8822C BIT(8) + +#define BIT_SHIFT_P2PPS_MACID_PAUSE_8822C 0 +#define BIT_MASK_P2PPS_MACID_PAUSE_8822C 0xff +#define BIT_P2PPS_MACID_PAUSE_8822C(x) \ + (((x) & BIT_MASK_P2PPS_MACID_PAUSE_8822C) \ + << BIT_SHIFT_P2PPS_MACID_PAUSE_8822C) +#define BITS_P2PPS_MACID_PAUSE_8822C \ + (BIT_MASK_P2PPS_MACID_PAUSE_8822C << BIT_SHIFT_P2PPS_MACID_PAUSE_8822C) +#define BIT_CLEAR_P2PPS_MACID_PAUSE_8822C(x) \ + ((x) & (~BITS_P2PPS_MACID_PAUSE_8822C)) +#define BIT_GET_P2PPS_MACID_PAUSE_8822C(x) \ + (((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE_8822C) & \ + BIT_MASK_P2PPS_MACID_PAUSE_8822C) +#define BIT_SET_P2PPS_MACID_PAUSE_8822C(x, v) \ + (BIT_CLEAR_P2PPS_MACID_PAUSE_8822C(x) | BIT_P2PPS_MACID_PAUSE_8822C(v)) + +/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C */ +#define BIT_P2PPS1_NOA_STOP_TX_HANG_8822C BIT(31) +#define BIT_P2PPS1_MACID_PAUSE_EN_8822C BIT(11) +#define BIT_P2PPS1__MGQ_PAUSE_8822C BIT(10) +#define BIT_P2PPS1__HIQ_PAUSE_8822C BIT(9) +#define BIT_P2PPS1__BCNQ_PAUSE_8822C BIT(8) + +#define BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C 0 +#define BIT_MASK_P2PPS1_MACID_PAUSE_8822C 0xff +#define BIT_P2PPS1_MACID_PAUSE_8822C(x) \ + (((x) & BIT_MASK_P2PPS1_MACID_PAUSE_8822C) \ + << BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C) +#define BITS_P2PPS1_MACID_PAUSE_8822C \ + (BIT_MASK_P2PPS1_MACID_PAUSE_8822C \ + << BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C) +#define BIT_CLEAR_P2PPS1_MACID_PAUSE_8822C(x) \ + ((x) & (~BITS_P2PPS1_MACID_PAUSE_8822C)) +#define BIT_GET_P2PPS1_MACID_PAUSE_8822C(x) \ + (((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C) & \ + BIT_MASK_P2PPS1_MACID_PAUSE_8822C) +#define BIT_SET_P2PPS1_MACID_PAUSE_8822C(x, v) \ + (BIT_CLEAR_P2PPS1_MACID_PAUSE_8822C(x) | \ + BIT_P2PPS1_MACID_PAUSE_8822C(v)) + +/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C */ +#define BIT_P2PPS2_NOA_STOP_TX_HANG_8822C BIT(31) +#define BIT_P2PPS2_MACID_PAUSE_EN_8822C BIT(11) +#define BIT_P2PPS2__MGQ_PAUSE_8822C BIT(10) +#define BIT_P2PPS2__HIQ_PAUSE_8822C BIT(9) +#define BIT_P2PPS2__BCNQ_PAUSE_8822C BIT(8) + +#define BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C 0 +#define BIT_MASK_P2PPS2_MACID_PAUSE_8822C 0xff +#define BIT_P2PPS2_MACID_PAUSE_8822C(x) \ + (((x) & BIT_MASK_P2PPS2_MACID_PAUSE_8822C) \ + << BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C) +#define BITS_P2PPS2_MACID_PAUSE_8822C \ + (BIT_MASK_P2PPS2_MACID_PAUSE_8822C \ + << BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C) +#define BIT_CLEAR_P2PPS2_MACID_PAUSE_8822C(x) \ + ((x) & (~BITS_P2PPS2_MACID_PAUSE_8822C)) +#define BIT_GET_P2PPS2_MACID_PAUSE_8822C(x) \ + (((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C) & \ + BIT_MASK_P2PPS2_MACID_PAUSE_8822C) +#define BIT_SET_P2PPS2_MACID_PAUSE_8822C(x, v) \ + (BIT_CLEAR_P2PPS2_MACID_PAUSE_8822C(x) | \ + BIT_P2PPS2_MACID_PAUSE_8822C(v)) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_SCHEDULER_COUNTER_8822C */ + +#define BIT_SHIFT__SCHEDULER_COUNTER_8822C 16 +#define BIT_MASK__SCHEDULER_COUNTER_8822C 0xffff +#define BIT__SCHEDULER_COUNTER_8822C(x) \ + (((x) & BIT_MASK__SCHEDULER_COUNTER_8822C) \ + << BIT_SHIFT__SCHEDULER_COUNTER_8822C) +#define BITS__SCHEDULER_COUNTER_8822C \ + (BIT_MASK__SCHEDULER_COUNTER_8822C \ + << BIT_SHIFT__SCHEDULER_COUNTER_8822C) +#define BIT_CLEAR__SCHEDULER_COUNTER_8822C(x) \ + ((x) & (~BITS__SCHEDULER_COUNTER_8822C)) +#define BIT_GET__SCHEDULER_COUNTER_8822C(x) \ + (((x) >> BIT_SHIFT__SCHEDULER_COUNTER_8822C) & \ + BIT_MASK__SCHEDULER_COUNTER_8822C) +#define BIT_SET__SCHEDULER_COUNTER_8822C(x, v) \ + (BIT_CLEAR__SCHEDULER_COUNTER_8822C(x) | \ + BIT__SCHEDULER_COUNTER_8822C(v)) + +#define BIT__SCHEDULER_COUNTER_RST_8822C BIT(8) + +#define BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C 0 +#define BIT_MASK_SCHEDULER_COUNTER_SEL_8822C 0xff +#define BIT_SCHEDULER_COUNTER_SEL_8822C(x) \ + (((x) & BIT_MASK_SCHEDULER_COUNTER_SEL_8822C) \ + << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C) +#define BITS_SCHEDULER_COUNTER_SEL_8822C \ + (BIT_MASK_SCHEDULER_COUNTER_SEL_8822C \ + << BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C) +#define BIT_CLEAR_SCHEDULER_COUNTER_SEL_8822C(x) \ + ((x) & (~BITS_SCHEDULER_COUNTER_SEL_8822C)) +#define BIT_GET_SCHEDULER_COUNTER_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL_8822C) & \ + BIT_MASK_SCHEDULER_COUNTER_SEL_8822C) +#define BIT_SET_SCHEDULER_COUNTER_SEL_8822C(x, v) \ + (BIT_CLEAR_SCHEDULER_COUNTER_SEL_8822C(x) | \ + BIT_SCHEDULER_COUNTER_SEL_8822C(v)) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_WMAC_CR_8822C (WMAC CR AND APSD CONTROL REGISTER) */ +#define BIT_IC_MACPHY_M_8822C BIT(0) + +/* 2 REG_WMAC_FWPKT_CR_8822C */ +#define BIT_FWEN_8822C BIT(7) +#define BIT_PHYSTS_PKT_CTRL_8822C BIT(6) +#define BIT_APPHDR_MIDSRCH_FAIL_8822C BIT(4) +#define BIT_FWPARSING_EN_8822C BIT(3) + +#define BIT_SHIFT_APPEND_MHDR_LEN_8822C 0 +#define BIT_MASK_APPEND_MHDR_LEN_8822C 0x7 +#define BIT_APPEND_MHDR_LEN_8822C(x) \ + (((x) & BIT_MASK_APPEND_MHDR_LEN_8822C) \ + << BIT_SHIFT_APPEND_MHDR_LEN_8822C) +#define BITS_APPEND_MHDR_LEN_8822C \ + (BIT_MASK_APPEND_MHDR_LEN_8822C << BIT_SHIFT_APPEND_MHDR_LEN_8822C) +#define BIT_CLEAR_APPEND_MHDR_LEN_8822C(x) ((x) & (~BITS_APPEND_MHDR_LEN_8822C)) +#define BIT_GET_APPEND_MHDR_LEN_8822C(x) \ + (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822C) & \ + BIT_MASK_APPEND_MHDR_LEN_8822C) +#define BIT_SET_APPEND_MHDR_LEN_8822C(x, v) \ + (BIT_CLEAR_APPEND_MHDR_LEN_8822C(x) | BIT_APPEND_MHDR_LEN_8822C(v)) + +/* 2 REG_FW_STS_FILTER_8822C */ +#define BIT_DATA_FW_STS_FILTER_8822C BIT(2) +#define BIT_CTRL_FW_STS_FILTER_8822C BIT(1) +#define BIT_MGNT_FW_STS_FILTER_8822C BIT(0) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_TCR_8822C (TRANSMISSION CONFIGURATION REGISTER) */ +#define BIT_WMAC_EN_RTS_ADDR_8822C BIT(31) +#define BIT_WMAC_DISABLE_CCK_8822C BIT(30) +#define BIT_WMAC_RAW_LEN_8822C BIT(29) +#define BIT_WMAC_NOTX_IN_RXNDP_8822C BIT(28) +#define BIT_WMAC_EN_EOF_8822C BIT(27) +#define BIT_WMAC_BF_SEL_8822C BIT(26) +#define BIT_WMAC_ANTMODE_SEL_8822C BIT(25) +#define BIT_WMAC_TCRPWRMGT_HWCTL_8822C BIT(24) +#define BIT_WMAC_SMOOTH_VAL_8822C BIT(23) +#define BIT_WMAC_EN_SCRAM_INC_8822C BIT(22) +#define BIT_UNDERFLOWEN_CMPLEN_SEL_8822C BIT(21) +#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8822C BIT(20) +#define BIT_WMAC_TCR_EN_20MST_8822C BIT(19) +#define BIT_WMAC_DIS_SIGTA_8822C BIT(18) +#define BIT_WMAC_DIS_A2B0_8822C BIT(17) +#define BIT_WMAC_MSK_SIGBCRC_8822C BIT(16) +#define BIT_WMAC_TCR_ERRSTEN_3_8822C BIT(15) +#define BIT_WMAC_TCR_ERRSTEN_2_8822C BIT(14) +#define BIT_WMAC_TCR_ERRSTEN_1_8822C BIT(13) +#define BIT_WMAC_TCR_ERRSTEN_0_8822C BIT(12) +#define BIT_WMAC_TCR_TXSK_PERPKT_8822C BIT(11) +#define BIT_ICV_8822C BIT(10) +#define BIT_CFEND_FORMAT_8822C BIT(9) +#define BIT_CRC_8822C BIT(8) +#define BIT_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(7) +#define BIT_PWR_ST_8822C BIT(6) +#define BIT_WMAC_TCR_UPD_TIMIE_8822C BIT(5) +#define BIT_WMAC_TCR_UPD_HGQMD_8822C BIT(4) +#define BIT_VHTSIGA1_TXPS_8822C BIT(3) +#define BIT_PAD_SEL_8822C BIT(2) +#define BIT_DIS_GCLK_8822C BIT(1) +#define BIT_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(0) + +/* 2 REG_RCR_8822C (RECEIVE CONFIGURATION REGISTER) */ +#define BIT_APP_FCS_8822C BIT(31) +#define BIT_APP_MIC_8822C BIT(30) +#define BIT_APP_ICV_8822C BIT(29) +#define BIT_APP_PHYSTS_8822C BIT(28) +#define BIT_APP_BASSN_8822C BIT(27) +#define BIT_VHT_DACK_8822C BIT(26) +#define BIT_TCPOFLD_EN_8822C BIT(25) +#define BIT_ENMBID_8822C BIT(24) +#define BIT_LSIGEN_8822C BIT(23) +#define BIT_MFBEN_8822C BIT(22) +#define BIT_DISCHKPPDLLEN_8822C BIT(21) +#define BIT_PKTCTL_DLEN_8822C BIT(20) +#define BIT_DISGCLK_8822C BIT(19) +#define BIT_TIM_PARSER_EN_8822C BIT(18) +#define BIT_BC_MD_EN_8822C BIT(17) +#define BIT_UC_MD_EN_8822C BIT(16) +#define BIT_RXSK_PERPKT_8822C BIT(15) +#define BIT_HTC_LOC_CTRL_8822C BIT(14) +#define BIT_ACK_WITH_CBSSID_DATA_OPTION_8822C BIT(13) +#define BIT_RPFM_CAM_ENABLE_8822C BIT(12) +#define BIT_TA_BCN_8822C BIT(11) +#define BIT_DISDECMYPKT_8822C BIT(10) +#define BIT_AICV_8822C BIT(9) +#define BIT_ACRC32_8822C BIT(8) +#define BIT_CBSSID_BCN_8822C BIT(7) +#define BIT_CBSSID_DATA_8822C BIT(6) +#define BIT_APWRMGT_8822C BIT(5) +#define BIT_ADD3_8822C BIT(4) +#define BIT_AB_8822C BIT(3) +#define BIT_AM_8822C BIT(2) +#define BIT_APM_8822C BIT(1) +#define BIT_AAP_8822C BIT(0) + +/* 2 REG_RX_PKT_LIMIT_8822C (RX PACKET LENGTH LIMIT REGISTER) */ + +#define BIT_SHIFT_RXPKTLMT_8822C 0 +#define BIT_MASK_RXPKTLMT_8822C 0x3f +#define BIT_RXPKTLMT_8822C(x) \ + (((x) & BIT_MASK_RXPKTLMT_8822C) << BIT_SHIFT_RXPKTLMT_8822C) +#define BITS_RXPKTLMT_8822C \ + (BIT_MASK_RXPKTLMT_8822C << BIT_SHIFT_RXPKTLMT_8822C) +#define BIT_CLEAR_RXPKTLMT_8822C(x) ((x) & (~BITS_RXPKTLMT_8822C)) +#define BIT_GET_RXPKTLMT_8822C(x) \ + (((x) >> BIT_SHIFT_RXPKTLMT_8822C) & BIT_MASK_RXPKTLMT_8822C) +#define BIT_SET_RXPKTLMT_8822C(x, v) \ + (BIT_CLEAR_RXPKTLMT_8822C(x) | BIT_RXPKTLMT_8822C(v)) + +/* 2 REG_RX_DLK_TIME_8822C (RX DEADLOCK TIME REGISTER) */ + +#define BIT_SHIFT_RX_DLK_TIME_8822C 0 +#define BIT_MASK_RX_DLK_TIME_8822C 0xff +#define BIT_RX_DLK_TIME_8822C(x) \ + (((x) & BIT_MASK_RX_DLK_TIME_8822C) << BIT_SHIFT_RX_DLK_TIME_8822C) +#define BITS_RX_DLK_TIME_8822C \ + (BIT_MASK_RX_DLK_TIME_8822C << BIT_SHIFT_RX_DLK_TIME_8822C) +#define BIT_CLEAR_RX_DLK_TIME_8822C(x) ((x) & (~BITS_RX_DLK_TIME_8822C)) +#define BIT_GET_RX_DLK_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_RX_DLK_TIME_8822C) & BIT_MASK_RX_DLK_TIME_8822C) +#define BIT_SET_RX_DLK_TIME_8822C(x, v) \ + (BIT_CLEAR_RX_DLK_TIME_8822C(x) | BIT_RX_DLK_TIME_8822C(v)) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RX_DRVINFO_SZ_8822C (RX DRIVER INFO SIZE REGISTER) */ +#define BIT_PHYSTS_PER_PKT_MODE_8822C BIT(7) + +#define BIT_SHIFT_DRVINFO_SZ_V1_8822C 0 +#define BIT_MASK_DRVINFO_SZ_V1_8822C 0xf +#define BIT_DRVINFO_SZ_V1_8822C(x) \ + (((x) & BIT_MASK_DRVINFO_SZ_V1_8822C) << BIT_SHIFT_DRVINFO_SZ_V1_8822C) +#define BITS_DRVINFO_SZ_V1_8822C \ + (BIT_MASK_DRVINFO_SZ_V1_8822C << BIT_SHIFT_DRVINFO_SZ_V1_8822C) +#define BIT_CLEAR_DRVINFO_SZ_V1_8822C(x) ((x) & (~BITS_DRVINFO_SZ_V1_8822C)) +#define BIT_GET_DRVINFO_SZ_V1_8822C(x) \ + (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822C) & BIT_MASK_DRVINFO_SZ_V1_8822C) +#define BIT_SET_DRVINFO_SZ_V1_8822C(x, v) \ + (BIT_CLEAR_DRVINFO_SZ_V1_8822C(x) | BIT_DRVINFO_SZ_V1_8822C(v)) + +/* 2 REG_MACID_8822C (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_V1_8822C 0 +#define BIT_MASK_MACID_V1_8822C 0xffffffffL +#define BIT_MACID_V1_8822C(x) \ + (((x) & BIT_MASK_MACID_V1_8822C) << BIT_SHIFT_MACID_V1_8822C) +#define BITS_MACID_V1_8822C \ + (BIT_MASK_MACID_V1_8822C << BIT_SHIFT_MACID_V1_8822C) +#define BIT_CLEAR_MACID_V1_8822C(x) ((x) & (~BITS_MACID_V1_8822C)) +#define BIT_GET_MACID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID_V1_8822C) & BIT_MASK_MACID_V1_8822C) +#define BIT_SET_MACID_V1_8822C(x, v) \ + (BIT_CLEAR_MACID_V1_8822C(x) | BIT_MACID_V1_8822C(v)) + +/* 2 REG_MACID_H_8822C (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_H_V1_8822C 0 +#define BIT_MASK_MACID_H_V1_8822C 0xffff +#define BIT_MACID_H_V1_8822C(x) \ + (((x) & BIT_MASK_MACID_H_V1_8822C) << BIT_SHIFT_MACID_H_V1_8822C) +#define BITS_MACID_H_V1_8822C \ + (BIT_MASK_MACID_H_V1_8822C << BIT_SHIFT_MACID_H_V1_8822C) +#define BIT_CLEAR_MACID_H_V1_8822C(x) ((x) & (~BITS_MACID_H_V1_8822C)) +#define BIT_GET_MACID_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID_H_V1_8822C) & BIT_MASK_MACID_H_V1_8822C) +#define BIT_SET_MACID_H_V1_8822C(x, v) \ + (BIT_CLEAR_MACID_H_V1_8822C(x) | BIT_MACID_H_V1_8822C(v)) + +/* 2 REG_BSSID_8822C (BSSID REGISTER) */ + +#define BIT_SHIFT_BSSID_V1_8822C 0 +#define BIT_MASK_BSSID_V1_8822C 0xffffffffL +#define BIT_BSSID_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID_V1_8822C) << BIT_SHIFT_BSSID_V1_8822C) +#define BITS_BSSID_V1_8822C \ + (BIT_MASK_BSSID_V1_8822C << BIT_SHIFT_BSSID_V1_8822C) +#define BIT_CLEAR_BSSID_V1_8822C(x) ((x) & (~BITS_BSSID_V1_8822C)) +#define BIT_GET_BSSID_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID_V1_8822C) & BIT_MASK_BSSID_V1_8822C) +#define BIT_SET_BSSID_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID_V1_8822C(x) | BIT_BSSID_V1_8822C(v)) + +/* 2 REG_BSSID_H_8822C (BSSID REGISTER) */ + +/* 2 REG_NOT_VALID_8822C */ + +#define BIT_SHIFT_BSSID_H_V1_8822C 0 +#define BIT_MASK_BSSID_H_V1_8822C 0xffff +#define BIT_BSSID_H_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID_H_V1_8822C) << BIT_SHIFT_BSSID_H_V1_8822C) +#define BITS_BSSID_H_V1_8822C \ + (BIT_MASK_BSSID_H_V1_8822C << BIT_SHIFT_BSSID_H_V1_8822C) +#define BIT_CLEAR_BSSID_H_V1_8822C(x) ((x) & (~BITS_BSSID_H_V1_8822C)) +#define BIT_GET_BSSID_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID_H_V1_8822C) & BIT_MASK_BSSID_H_V1_8822C) +#define BIT_SET_BSSID_H_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID_H_V1_8822C(x) | BIT_BSSID_H_V1_8822C(v)) + +/* 2 REG_MAR_8822C (MULTICAST ADDRESS REGISTER) */ + +#define BIT_SHIFT_MAR_V1_8822C 0 +#define BIT_MASK_MAR_V1_8822C 0xffffffffL +#define BIT_MAR_V1_8822C(x) \ + (((x) & BIT_MASK_MAR_V1_8822C) << BIT_SHIFT_MAR_V1_8822C) +#define BITS_MAR_V1_8822C (BIT_MASK_MAR_V1_8822C << BIT_SHIFT_MAR_V1_8822C) +#define BIT_CLEAR_MAR_V1_8822C(x) ((x) & (~BITS_MAR_V1_8822C)) +#define BIT_GET_MAR_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MAR_V1_8822C) & BIT_MASK_MAR_V1_8822C) +#define BIT_SET_MAR_V1_8822C(x, v) \ + (BIT_CLEAR_MAR_V1_8822C(x) | BIT_MAR_V1_8822C(v)) + +/* 2 REG_MAR_H_8822C (MULTICAST ADDRESS REGISTER) */ + +#define BIT_SHIFT_MAR_H_V1_8822C 0 +#define BIT_MASK_MAR_H_V1_8822C 0xffffffffL +#define BIT_MAR_H_V1_8822C(x) \ + (((x) & BIT_MASK_MAR_H_V1_8822C) << BIT_SHIFT_MAR_H_V1_8822C) +#define BITS_MAR_H_V1_8822C \ + (BIT_MASK_MAR_H_V1_8822C << BIT_SHIFT_MAR_H_V1_8822C) +#define BIT_CLEAR_MAR_H_V1_8822C(x) ((x) & (~BITS_MAR_H_V1_8822C)) +#define BIT_GET_MAR_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MAR_H_V1_8822C) & BIT_MASK_MAR_H_V1_8822C) +#define BIT_SET_MAR_H_V1_8822C(x, v) \ + (BIT_CLEAR_MAR_H_V1_8822C(x) | BIT_MAR_H_V1_8822C(v)) + +/* 2 REG_MBIDCAMCFG_1_8822C (MBSSID CAM CONFIGURATION REGISTER) */ + +#define BIT_SHIFT_MBIDCAM_RWDATA_L_8822C 0 +#define BIT_MASK_MBIDCAM_RWDATA_L_8822C 0xffffffffL +#define BIT_MBIDCAM_RWDATA_L_8822C(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822C) \ + << BIT_SHIFT_MBIDCAM_RWDATA_L_8822C) +#define BITS_MBIDCAM_RWDATA_L_8822C \ + (BIT_MASK_MBIDCAM_RWDATA_L_8822C << BIT_SHIFT_MBIDCAM_RWDATA_L_8822C) +#define BIT_CLEAR_MBIDCAM_RWDATA_L_8822C(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_L_8822C)) +#define BIT_GET_MBIDCAM_RWDATA_L_8822C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822C) & \ + BIT_MASK_MBIDCAM_RWDATA_L_8822C) +#define BIT_SET_MBIDCAM_RWDATA_L_8822C(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_L_8822C(x) | BIT_MBIDCAM_RWDATA_L_8822C(v)) + +/* 2 REG_MBIDCAMCFG_2_8822C (MBSSID CAM CONFIGURATION REGISTER) */ +#define BIT_MBIDCAM_POLL_8822C BIT(31) +#define BIT_MBIDCAM_WT_EN_8822C BIT(30) + +#define BIT_SHIFT_MBIDCAM_ADDR_V1_8822C 24 +#define BIT_MASK_MBIDCAM_ADDR_V1_8822C 0x3f +#define BIT_MBIDCAM_ADDR_V1_8822C(x) \ + (((x) & BIT_MASK_MBIDCAM_ADDR_V1_8822C) \ + << BIT_SHIFT_MBIDCAM_ADDR_V1_8822C) +#define BITS_MBIDCAM_ADDR_V1_8822C \ + (BIT_MASK_MBIDCAM_ADDR_V1_8822C << BIT_SHIFT_MBIDCAM_ADDR_V1_8822C) +#define BIT_CLEAR_MBIDCAM_ADDR_V1_8822C(x) ((x) & (~BITS_MBIDCAM_ADDR_V1_8822C)) +#define BIT_GET_MBIDCAM_ADDR_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1_8822C) & \ + BIT_MASK_MBIDCAM_ADDR_V1_8822C) +#define BIT_SET_MBIDCAM_ADDR_V1_8822C(x, v) \ + (BIT_CLEAR_MBIDCAM_ADDR_V1_8822C(x) | BIT_MBIDCAM_ADDR_V1_8822C(v)) + +#define BIT_MBIDCAM_VALID_8822C BIT(23) +#define BIT_LSIC_TXOP_EN_8822C BIT(17) +#define BIT_CTS_EN_8822C BIT(16) + +#define BIT_SHIFT_MBIDCAM_RWDATA_H_8822C 0 +#define BIT_MASK_MBIDCAM_RWDATA_H_8822C 0xffff +#define BIT_MBIDCAM_RWDATA_H_8822C(x) \ + (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822C) \ + << BIT_SHIFT_MBIDCAM_RWDATA_H_8822C) +#define BITS_MBIDCAM_RWDATA_H_8822C \ + (BIT_MASK_MBIDCAM_RWDATA_H_8822C << BIT_SHIFT_MBIDCAM_RWDATA_H_8822C) +#define BIT_CLEAR_MBIDCAM_RWDATA_H_8822C(x) \ + ((x) & (~BITS_MBIDCAM_RWDATA_H_8822C)) +#define BIT_GET_MBIDCAM_RWDATA_H_8822C(x) \ + (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822C) & \ + BIT_MASK_MBIDCAM_RWDATA_H_8822C) +#define BIT_SET_MBIDCAM_RWDATA_H_8822C(x, v) \ + (BIT_CLEAR_MBIDCAM_RWDATA_H_8822C(x) | BIT_MBIDCAM_RWDATA_H_8822C(v)) + +/* 2 REG_WMAC_TCR_TSFT_OFS_8822C */ + +#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C 0 +#define BIT_MASK_WMAC_TCR_TSFT_OFS_8822C 0xffff +#define BIT_WMAC_TCR_TSFT_OFS_8822C(x) \ + (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822C) \ + << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C) +#define BITS_WMAC_TCR_TSFT_OFS_8822C \ + (BIT_MASK_WMAC_TCR_TSFT_OFS_8822C << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C) +#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822C(x) \ + ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8822C)) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C) & \ + BIT_MASK_WMAC_TCR_TSFT_OFS_8822C) +#define BIT_SET_WMAC_TCR_TSFT_OFS_8822C(x, v) \ + (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822C(x) | BIT_WMAC_TCR_TSFT_OFS_8822C(v)) + +/* 2 REG_UDF_THSD_8822C */ +#define BIT_UDF_THSD_V1_8822C BIT(7) + +#define BIT_SHIFT_UDF_THSD_VALUE_8822C 0 +#define BIT_MASK_UDF_THSD_VALUE_8822C 0x7f +#define BIT_UDF_THSD_VALUE_8822C(x) \ + (((x) & BIT_MASK_UDF_THSD_VALUE_8822C) \ + << BIT_SHIFT_UDF_THSD_VALUE_8822C) +#define BITS_UDF_THSD_VALUE_8822C \ + (BIT_MASK_UDF_THSD_VALUE_8822C << BIT_SHIFT_UDF_THSD_VALUE_8822C) +#define BIT_CLEAR_UDF_THSD_VALUE_8822C(x) ((x) & (~BITS_UDF_THSD_VALUE_8822C)) +#define BIT_GET_UDF_THSD_VALUE_8822C(x) \ + (((x) >> BIT_SHIFT_UDF_THSD_VALUE_8822C) & \ + BIT_MASK_UDF_THSD_VALUE_8822C) +#define BIT_SET_UDF_THSD_VALUE_8822C(x, v) \ + (BIT_CLEAR_UDF_THSD_VALUE_8822C(x) | BIT_UDF_THSD_VALUE_8822C(v)) + +/* 2 REG_ZLD_NUM_8822C */ + +#define BIT_SHIFT_ZLD_NUM_8822C 0 +#define BIT_MASK_ZLD_NUM_8822C 0xff +#define BIT_ZLD_NUM_8822C(x) \ + (((x) & BIT_MASK_ZLD_NUM_8822C) << BIT_SHIFT_ZLD_NUM_8822C) +#define BITS_ZLD_NUM_8822C (BIT_MASK_ZLD_NUM_8822C << BIT_SHIFT_ZLD_NUM_8822C) +#define BIT_CLEAR_ZLD_NUM_8822C(x) ((x) & (~BITS_ZLD_NUM_8822C)) +#define BIT_GET_ZLD_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_ZLD_NUM_8822C) & BIT_MASK_ZLD_NUM_8822C) +#define BIT_SET_ZLD_NUM_8822C(x, v) \ + (BIT_CLEAR_ZLD_NUM_8822C(x) | BIT_ZLD_NUM_8822C(v)) + +/* 2 REG_STMP_THSD_8822C */ + +#define BIT_SHIFT_STMP_THSD_8822C 0 +#define BIT_MASK_STMP_THSD_8822C 0xff +#define BIT_STMP_THSD_8822C(x) \ + (((x) & BIT_MASK_STMP_THSD_8822C) << BIT_SHIFT_STMP_THSD_8822C) +#define BITS_STMP_THSD_8822C \ + (BIT_MASK_STMP_THSD_8822C << BIT_SHIFT_STMP_THSD_8822C) +#define BIT_CLEAR_STMP_THSD_8822C(x) ((x) & (~BITS_STMP_THSD_8822C)) +#define BIT_GET_STMP_THSD_8822C(x) \ + (((x) >> BIT_SHIFT_STMP_THSD_8822C) & BIT_MASK_STMP_THSD_8822C) +#define BIT_SET_STMP_THSD_8822C(x, v) \ + (BIT_CLEAR_STMP_THSD_8822C(x) | BIT_STMP_THSD_8822C(v)) + +/* 2 REG_WMAC_TXTIMEOUT_8822C */ + +#define BIT_SHIFT_WMAC_TXTIMEOUT_8822C 0 +#define BIT_MASK_WMAC_TXTIMEOUT_8822C 0xff +#define BIT_WMAC_TXTIMEOUT_8822C(x) \ + (((x) & BIT_MASK_WMAC_TXTIMEOUT_8822C) \ + << BIT_SHIFT_WMAC_TXTIMEOUT_8822C) +#define BITS_WMAC_TXTIMEOUT_8822C \ + (BIT_MASK_WMAC_TXTIMEOUT_8822C << BIT_SHIFT_WMAC_TXTIMEOUT_8822C) +#define BIT_CLEAR_WMAC_TXTIMEOUT_8822C(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8822C)) +#define BIT_GET_WMAC_TXTIMEOUT_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822C) & \ + BIT_MASK_WMAC_TXTIMEOUT_8822C) +#define BIT_SET_WMAC_TXTIMEOUT_8822C(x, v) \ + (BIT_CLEAR_WMAC_TXTIMEOUT_8822C(x) | BIT_WMAC_TXTIMEOUT_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_USTIME_EDCA_8822C (US TIME TUNING FOR EDCA REGISTER) */ + +#define BIT_SHIFT_USTIME_EDCA_8822C 0 +#define BIT_MASK_USTIME_EDCA_8822C 0xff +#define BIT_USTIME_EDCA_8822C(x) \ + (((x) & BIT_MASK_USTIME_EDCA_8822C) << BIT_SHIFT_USTIME_EDCA_8822C) +#define BITS_USTIME_EDCA_8822C \ + (BIT_MASK_USTIME_EDCA_8822C << BIT_SHIFT_USTIME_EDCA_8822C) +#define BIT_CLEAR_USTIME_EDCA_8822C(x) ((x) & (~BITS_USTIME_EDCA_8822C)) +#define BIT_GET_USTIME_EDCA_8822C(x) \ + (((x) >> BIT_SHIFT_USTIME_EDCA_8822C) & BIT_MASK_USTIME_EDCA_8822C) +#define BIT_SET_USTIME_EDCA_8822C(x, v) \ + (BIT_CLEAR_USTIME_EDCA_8822C(x) | BIT_USTIME_EDCA_8822C(v)) + +/* 2 REG_ACKTO_CCK_8822C (ACK TIMEOUT REGISTER FOR CCK RATE) */ + +#define BIT_SHIFT_ACKTO_CCK_8822C 0 +#define BIT_MASK_ACKTO_CCK_8822C 0xff +#define BIT_ACKTO_CCK_8822C(x) \ + (((x) & BIT_MASK_ACKTO_CCK_8822C) << BIT_SHIFT_ACKTO_CCK_8822C) +#define BITS_ACKTO_CCK_8822C \ + (BIT_MASK_ACKTO_CCK_8822C << BIT_SHIFT_ACKTO_CCK_8822C) +#define BIT_CLEAR_ACKTO_CCK_8822C(x) ((x) & (~BITS_ACKTO_CCK_8822C)) +#define BIT_GET_ACKTO_CCK_8822C(x) \ + (((x) >> BIT_SHIFT_ACKTO_CCK_8822C) & BIT_MASK_ACKTO_CCK_8822C) +#define BIT_SET_ACKTO_CCK_8822C(x, v) \ + (BIT_CLEAR_ACKTO_CCK_8822C(x) | BIT_ACKTO_CCK_8822C(v)) + +/* 2 REG_MAC_SPEC_SIFS_8822C (SPECIFICATION SIFS REGISTER) */ + +#define BIT_SHIFT_SPEC_SIFS_OFDM_8822C 8 +#define BIT_MASK_SPEC_SIFS_OFDM_8822C 0xff +#define BIT_SPEC_SIFS_OFDM_8822C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_OFDM_8822C) \ + << BIT_SHIFT_SPEC_SIFS_OFDM_8822C) +#define BITS_SPEC_SIFS_OFDM_8822C \ + (BIT_MASK_SPEC_SIFS_OFDM_8822C << BIT_SHIFT_SPEC_SIFS_OFDM_8822C) +#define BIT_CLEAR_SPEC_SIFS_OFDM_8822C(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8822C)) +#define BIT_GET_SPEC_SIFS_OFDM_8822C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822C) & \ + BIT_MASK_SPEC_SIFS_OFDM_8822C) +#define BIT_SET_SPEC_SIFS_OFDM_8822C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_OFDM_8822C(x) | BIT_SPEC_SIFS_OFDM_8822C(v)) + +#define BIT_SHIFT_SPEC_SIFS_CCK_8822C 0 +#define BIT_MASK_SPEC_SIFS_CCK_8822C 0xff +#define BIT_SPEC_SIFS_CCK_8822C(x) \ + (((x) & BIT_MASK_SPEC_SIFS_CCK_8822C) << BIT_SHIFT_SPEC_SIFS_CCK_8822C) +#define BITS_SPEC_SIFS_CCK_8822C \ + (BIT_MASK_SPEC_SIFS_CCK_8822C << BIT_SHIFT_SPEC_SIFS_CCK_8822C) +#define BIT_CLEAR_SPEC_SIFS_CCK_8822C(x) ((x) & (~BITS_SPEC_SIFS_CCK_8822C)) +#define BIT_GET_SPEC_SIFS_CCK_8822C(x) \ + (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822C) & BIT_MASK_SPEC_SIFS_CCK_8822C) +#define BIT_SET_SPEC_SIFS_CCK_8822C(x, v) \ + (BIT_CLEAR_SPEC_SIFS_CCK_8822C(x) | BIT_SPEC_SIFS_CCK_8822C(v)) + +/* 2 REG_RESP_SIFS_CCK_8822C (RESPONSE SIFS FOR CCK REGISTER) */ + +#define BIT_SHIFT_SIFS_R2T_CCK_8822C 8 +#define BIT_MASK_SIFS_R2T_CCK_8822C 0xff +#define BIT_SIFS_R2T_CCK_8822C(x) \ + (((x) & BIT_MASK_SIFS_R2T_CCK_8822C) << BIT_SHIFT_SIFS_R2T_CCK_8822C) +#define BITS_SIFS_R2T_CCK_8822C \ + (BIT_MASK_SIFS_R2T_CCK_8822C << BIT_SHIFT_SIFS_R2T_CCK_8822C) +#define BIT_CLEAR_SIFS_R2T_CCK_8822C(x) ((x) & (~BITS_SIFS_R2T_CCK_8822C)) +#define BIT_GET_SIFS_R2T_CCK_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822C) & BIT_MASK_SIFS_R2T_CCK_8822C) +#define BIT_SET_SIFS_R2T_CCK_8822C(x, v) \ + (BIT_CLEAR_SIFS_R2T_CCK_8822C(x) | BIT_SIFS_R2T_CCK_8822C(v)) + +#define BIT_SHIFT_SIFS_T2T_CCK_8822C 0 +#define BIT_MASK_SIFS_T2T_CCK_8822C 0xff +#define BIT_SIFS_T2T_CCK_8822C(x) \ + (((x) & BIT_MASK_SIFS_T2T_CCK_8822C) << BIT_SHIFT_SIFS_T2T_CCK_8822C) +#define BITS_SIFS_T2T_CCK_8822C \ + (BIT_MASK_SIFS_T2T_CCK_8822C << BIT_SHIFT_SIFS_T2T_CCK_8822C) +#define BIT_CLEAR_SIFS_T2T_CCK_8822C(x) ((x) & (~BITS_SIFS_T2T_CCK_8822C)) +#define BIT_GET_SIFS_T2T_CCK_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822C) & BIT_MASK_SIFS_T2T_CCK_8822C) +#define BIT_SET_SIFS_T2T_CCK_8822C(x, v) \ + (BIT_CLEAR_SIFS_T2T_CCK_8822C(x) | BIT_SIFS_T2T_CCK_8822C(v)) + +/* 2 REG_RESP_SIFS_OFDM_8822C (RESPONSE SIFS FOR OFDM REGISTER) */ + +#define BIT_SHIFT_SIFS_R2T_OFDM_8822C 8 +#define BIT_MASK_SIFS_R2T_OFDM_8822C 0xff +#define BIT_SIFS_R2T_OFDM_8822C(x) \ + (((x) & BIT_MASK_SIFS_R2T_OFDM_8822C) << BIT_SHIFT_SIFS_R2T_OFDM_8822C) +#define BITS_SIFS_R2T_OFDM_8822C \ + (BIT_MASK_SIFS_R2T_OFDM_8822C << BIT_SHIFT_SIFS_R2T_OFDM_8822C) +#define BIT_CLEAR_SIFS_R2T_OFDM_8822C(x) ((x) & (~BITS_SIFS_R2T_OFDM_8822C)) +#define BIT_GET_SIFS_R2T_OFDM_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822C) & BIT_MASK_SIFS_R2T_OFDM_8822C) +#define BIT_SET_SIFS_R2T_OFDM_8822C(x, v) \ + (BIT_CLEAR_SIFS_R2T_OFDM_8822C(x) | BIT_SIFS_R2T_OFDM_8822C(v)) + +#define BIT_SHIFT_SIFS_T2T_OFDM_8822C 0 +#define BIT_MASK_SIFS_T2T_OFDM_8822C 0xff +#define BIT_SIFS_T2T_OFDM_8822C(x) \ + (((x) & BIT_MASK_SIFS_T2T_OFDM_8822C) << BIT_SHIFT_SIFS_T2T_OFDM_8822C) +#define BITS_SIFS_T2T_OFDM_8822C \ + (BIT_MASK_SIFS_T2T_OFDM_8822C << BIT_SHIFT_SIFS_T2T_OFDM_8822C) +#define BIT_CLEAR_SIFS_T2T_OFDM_8822C(x) ((x) & (~BITS_SIFS_T2T_OFDM_8822C)) +#define BIT_GET_SIFS_T2T_OFDM_8822C(x) \ + (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822C) & BIT_MASK_SIFS_T2T_OFDM_8822C) +#define BIT_SET_SIFS_T2T_OFDM_8822C(x, v) \ + (BIT_CLEAR_SIFS_T2T_OFDM_8822C(x) | BIT_SIFS_T2T_OFDM_8822C(v)) + +/* 2 REG_ACKTO_8822C (ACK TIMEOUT REGISTER) */ + +#define BIT_SHIFT_ACKTO_8822C 0 +#define BIT_MASK_ACKTO_8822C 0xff +#define BIT_ACKTO_8822C(x) \ + (((x) & BIT_MASK_ACKTO_8822C) << BIT_SHIFT_ACKTO_8822C) +#define BITS_ACKTO_8822C (BIT_MASK_ACKTO_8822C << BIT_SHIFT_ACKTO_8822C) +#define BIT_CLEAR_ACKTO_8822C(x) ((x) & (~BITS_ACKTO_8822C)) +#define BIT_GET_ACKTO_8822C(x) \ + (((x) >> BIT_SHIFT_ACKTO_8822C) & BIT_MASK_ACKTO_8822C) +#define BIT_SET_ACKTO_8822C(x, v) \ + (BIT_CLEAR_ACKTO_8822C(x) | BIT_ACKTO_8822C(v)) + +/* 2 REG_CTS2TO_8822C (CTS2 TIMEOUT REGISTER) */ + +#define BIT_SHIFT_CTS2TO_8822C 0 +#define BIT_MASK_CTS2TO_8822C 0xff +#define BIT_CTS2TO_8822C(x) \ + (((x) & BIT_MASK_CTS2TO_8822C) << BIT_SHIFT_CTS2TO_8822C) +#define BITS_CTS2TO_8822C (BIT_MASK_CTS2TO_8822C << BIT_SHIFT_CTS2TO_8822C) +#define BIT_CLEAR_CTS2TO_8822C(x) ((x) & (~BITS_CTS2TO_8822C)) +#define BIT_GET_CTS2TO_8822C(x) \ + (((x) >> BIT_SHIFT_CTS2TO_8822C) & BIT_MASK_CTS2TO_8822C) +#define BIT_SET_CTS2TO_8822C(x, v) \ + (BIT_CLEAR_CTS2TO_8822C(x) | BIT_CTS2TO_8822C(v)) + +/* 2 REG_EIFS_8822C (EIFS REGISTER) */ + +#define BIT_SHIFT_EIFS_8822C 0 +#define BIT_MASK_EIFS_8822C 0xffff +#define BIT_EIFS_8822C(x) (((x) & BIT_MASK_EIFS_8822C) << BIT_SHIFT_EIFS_8822C) +#define BITS_EIFS_8822C (BIT_MASK_EIFS_8822C << BIT_SHIFT_EIFS_8822C) +#define BIT_CLEAR_EIFS_8822C(x) ((x) & (~BITS_EIFS_8822C)) +#define BIT_GET_EIFS_8822C(x) \ + (((x) >> BIT_SHIFT_EIFS_8822C) & BIT_MASK_EIFS_8822C) +#define BIT_SET_EIFS_8822C(x, v) (BIT_CLEAR_EIFS_8822C(x) | BIT_EIFS_8822C(v)) + +/* 2 REG_RPFM_MAP0_8822C */ +#define BIT_MGT_RPFM15EN_8822C BIT(15) +#define BIT_MGT_RPFM14EN_8822C BIT(14) +#define BIT_MGT_RPFM13EN_8822C BIT(13) +#define BIT_MGT_RPFM12EN_8822C BIT(12) +#define BIT_MGT_RPFM11EN_8822C BIT(11) +#define BIT_MGT_RPFM10EN_8822C BIT(10) +#define BIT_MGT_RPFM9EN_8822C BIT(9) +#define BIT_MGT_RPFM8EN_8822C BIT(8) +#define BIT_MGT_RPFM7EN_8822C BIT(7) +#define BIT_MGT_RPFM6EN_8822C BIT(6) +#define BIT_MGT_RPFM5EN_8822C BIT(5) +#define BIT_MGT_RPFM4EN_8822C BIT(4) +#define BIT_MGT_RPFM3EN_8822C BIT(3) +#define BIT_MGT_RPFM2EN_8822C BIT(2) +#define BIT_MGT_RPFM1EN_8822C BIT(1) +#define BIT_MGT_RPFM0EN_8822C BIT(0) + +/* 2 REG_RPFM_MAP1_V1_8822C */ +#define BIT_DATA_RPFM15EN_8822C BIT(15) +#define BIT_DATA_RPFM14EN_8822C BIT(14) +#define BIT_DATA_RPFM13EN_8822C BIT(13) +#define BIT_DATA_RPFM12EN_8822C BIT(12) +#define BIT_DATA_RPFM11EN_8822C BIT(11) +#define BIT_DATA_RPFM10EN_8822C BIT(10) +#define BIT_DATA_RPFM9EN_8822C BIT(9) +#define BIT_DATA_RPFM8EN_8822C BIT(8) +#define BIT_DATA_RPFM7EN_8822C BIT(7) +#define BIT_DATA_RPFM6EN_8822C BIT(6) +#define BIT_DATA_RPFM5EN_8822C BIT(5) +#define BIT_DATA_RPFM4EN_8822C BIT(4) +#define BIT_DATA_RPFM3EN_8822C BIT(3) +#define BIT_DATA_RPFM2EN_8822C BIT(2) +#define BIT_DATA_RPFM1EN_8822C BIT(1) +#define BIT_DATA_RPFM0EN_8822C BIT(0) + +/* 2 REG_RPFM_CAM_CMD_8822C (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */ +#define BIT_RPFM_CAM_POLLING_8822C BIT(31) +#define BIT_RPFM_CAM_CLR_8822C BIT(30) +#define BIT_RPFM_CAM_WE_8822C BIT(16) + +#define BIT_SHIFT_RPFM_CAM_ADDR_8822C 0 +#define BIT_MASK_RPFM_CAM_ADDR_8822C 0x7f +#define BIT_RPFM_CAM_ADDR_8822C(x) \ + (((x) & BIT_MASK_RPFM_CAM_ADDR_8822C) << BIT_SHIFT_RPFM_CAM_ADDR_8822C) +#define BITS_RPFM_CAM_ADDR_8822C \ + (BIT_MASK_RPFM_CAM_ADDR_8822C << BIT_SHIFT_RPFM_CAM_ADDR_8822C) +#define BIT_CLEAR_RPFM_CAM_ADDR_8822C(x) ((x) & (~BITS_RPFM_CAM_ADDR_8822C)) +#define BIT_GET_RPFM_CAM_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8822C) & BIT_MASK_RPFM_CAM_ADDR_8822C) +#define BIT_SET_RPFM_CAM_ADDR_8822C(x, v) \ + (BIT_CLEAR_RPFM_CAM_ADDR_8822C(x) | BIT_RPFM_CAM_ADDR_8822C(v)) + +/* 2 REG_RPFM_CAM_RWD_8822C (ACK TIMEOUT REGISTER) */ + +#define BIT_SHIFT_RPFM_CAM_RWD_8822C 0 +#define BIT_MASK_RPFM_CAM_RWD_8822C 0xffffffffL +#define BIT_RPFM_CAM_RWD_8822C(x) \ + (((x) & BIT_MASK_RPFM_CAM_RWD_8822C) << BIT_SHIFT_RPFM_CAM_RWD_8822C) +#define BITS_RPFM_CAM_RWD_8822C \ + (BIT_MASK_RPFM_CAM_RWD_8822C << BIT_SHIFT_RPFM_CAM_RWD_8822C) +#define BIT_CLEAR_RPFM_CAM_RWD_8822C(x) ((x) & (~BITS_RPFM_CAM_RWD_8822C)) +#define BIT_GET_RPFM_CAM_RWD_8822C(x) \ + (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8822C) & BIT_MASK_RPFM_CAM_RWD_8822C) +#define BIT_SET_RPFM_CAM_RWD_8822C(x, v) \ + (BIT_CLEAR_RPFM_CAM_RWD_8822C(x) | BIT_RPFM_CAM_RWD_8822C(v)) + +/* 2 REG_NAV_CTRL_8822C (NAV CONTROL REGISTER) */ + +#define BIT_SHIFT_NAV_UPPER_8822C 16 +#define BIT_MASK_NAV_UPPER_8822C 0xff +#define BIT_NAV_UPPER_8822C(x) \ + (((x) & BIT_MASK_NAV_UPPER_8822C) << BIT_SHIFT_NAV_UPPER_8822C) +#define BITS_NAV_UPPER_8822C \ + (BIT_MASK_NAV_UPPER_8822C << BIT_SHIFT_NAV_UPPER_8822C) +#define BIT_CLEAR_NAV_UPPER_8822C(x) ((x) & (~BITS_NAV_UPPER_8822C)) +#define BIT_GET_NAV_UPPER_8822C(x) \ + (((x) >> BIT_SHIFT_NAV_UPPER_8822C) & BIT_MASK_NAV_UPPER_8822C) +#define BIT_SET_NAV_UPPER_8822C(x, v) \ + (BIT_CLEAR_NAV_UPPER_8822C(x) | BIT_NAV_UPPER_8822C(v)) + +#define BIT_SHIFT_RXMYRTS_NAV_8822C 8 +#define BIT_MASK_RXMYRTS_NAV_8822C 0xf +#define BIT_RXMYRTS_NAV_8822C(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_8822C) << BIT_SHIFT_RXMYRTS_NAV_8822C) +#define BITS_RXMYRTS_NAV_8822C \ + (BIT_MASK_RXMYRTS_NAV_8822C << BIT_SHIFT_RXMYRTS_NAV_8822C) +#define BIT_CLEAR_RXMYRTS_NAV_8822C(x) ((x) & (~BITS_RXMYRTS_NAV_8822C)) +#define BIT_GET_RXMYRTS_NAV_8822C(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_8822C) & BIT_MASK_RXMYRTS_NAV_8822C) +#define BIT_SET_RXMYRTS_NAV_8822C(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_8822C(x) | BIT_RXMYRTS_NAV_8822C(v)) + +#define BIT_SHIFT_RTSRST_8822C 0 +#define BIT_MASK_RTSRST_8822C 0xff +#define BIT_RTSRST_8822C(x) \ + (((x) & BIT_MASK_RTSRST_8822C) << BIT_SHIFT_RTSRST_8822C) +#define BITS_RTSRST_8822C (BIT_MASK_RTSRST_8822C << BIT_SHIFT_RTSRST_8822C) +#define BIT_CLEAR_RTSRST_8822C(x) ((x) & (~BITS_RTSRST_8822C)) +#define BIT_GET_RTSRST_8822C(x) \ + (((x) >> BIT_SHIFT_RTSRST_8822C) & BIT_MASK_RTSRST_8822C) +#define BIT_SET_RTSRST_8822C(x, v) \ + (BIT_CLEAR_RTSRST_8822C(x) | BIT_RTSRST_8822C(v)) + +/* 2 REG_BACAMCMD_8822C (BLOCK ACK CAM COMMAND REGISTER) */ +#define BIT_BACAM_POLL_8822C BIT(31) +#define BIT_BACAM_RST_8822C BIT(17) +#define BIT_BACAM_RW_8822C BIT(16) + +#define BIT_SHIFT_TXSBM_8822C 14 +#define BIT_MASK_TXSBM_8822C 0x3 +#define BIT_TXSBM_8822C(x) \ + (((x) & BIT_MASK_TXSBM_8822C) << BIT_SHIFT_TXSBM_8822C) +#define BITS_TXSBM_8822C (BIT_MASK_TXSBM_8822C << BIT_SHIFT_TXSBM_8822C) +#define BIT_CLEAR_TXSBM_8822C(x) ((x) & (~BITS_TXSBM_8822C)) +#define BIT_GET_TXSBM_8822C(x) \ + (((x) >> BIT_SHIFT_TXSBM_8822C) & BIT_MASK_TXSBM_8822C) +#define BIT_SET_TXSBM_8822C(x, v) \ + (BIT_CLEAR_TXSBM_8822C(x) | BIT_TXSBM_8822C(v)) + +#define BIT_SHIFT_BACAM_ADDR_8822C 0 +#define BIT_MASK_BACAM_ADDR_8822C 0x3f +#define BIT_BACAM_ADDR_8822C(x) \ + (((x) & BIT_MASK_BACAM_ADDR_8822C) << BIT_SHIFT_BACAM_ADDR_8822C) +#define BITS_BACAM_ADDR_8822C \ + (BIT_MASK_BACAM_ADDR_8822C << BIT_SHIFT_BACAM_ADDR_8822C) +#define BIT_CLEAR_BACAM_ADDR_8822C(x) ((x) & (~BITS_BACAM_ADDR_8822C)) +#define BIT_GET_BACAM_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_BACAM_ADDR_8822C) & BIT_MASK_BACAM_ADDR_8822C) +#define BIT_SET_BACAM_ADDR_8822C(x, v) \ + (BIT_CLEAR_BACAM_ADDR_8822C(x) | BIT_BACAM_ADDR_8822C(v)) + +/* 2 REG_BACAMCONTENT_8822C (BLOCK ACK CAM CONTENT REGISTER) */ + +#define BIT_SHIFT_BA_CONTENT_L_8822C 0 +#define BIT_MASK_BA_CONTENT_L_8822C 0xffffffffL +#define BIT_BA_CONTENT_L_8822C(x) \ + (((x) & BIT_MASK_BA_CONTENT_L_8822C) << BIT_SHIFT_BA_CONTENT_L_8822C) +#define BITS_BA_CONTENT_L_8822C \ + (BIT_MASK_BA_CONTENT_L_8822C << BIT_SHIFT_BA_CONTENT_L_8822C) +#define BIT_CLEAR_BA_CONTENT_L_8822C(x) ((x) & (~BITS_BA_CONTENT_L_8822C)) +#define BIT_GET_BA_CONTENT_L_8822C(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_L_8822C) & BIT_MASK_BA_CONTENT_L_8822C) +#define BIT_SET_BA_CONTENT_L_8822C(x, v) \ + (BIT_CLEAR_BA_CONTENT_L_8822C(x) | BIT_BA_CONTENT_L_8822C(v)) + +/* 2 REG_BACAMCONTENT_H_8822C (BLOCK ACK CAM CONTENT REGISTER) */ + +#define BIT_SHIFT_BA_CONTENT_H_8822C 0 +#define BIT_MASK_BA_CONTENT_H_8822C 0xffffffffL +#define BIT_BA_CONTENT_H_8822C(x) \ + (((x) & BIT_MASK_BA_CONTENT_H_8822C) << BIT_SHIFT_BA_CONTENT_H_8822C) +#define BITS_BA_CONTENT_H_8822C \ + (BIT_MASK_BA_CONTENT_H_8822C << BIT_SHIFT_BA_CONTENT_H_8822C) +#define BIT_CLEAR_BA_CONTENT_H_8822C(x) ((x) & (~BITS_BA_CONTENT_H_8822C)) +#define BIT_GET_BA_CONTENT_H_8822C(x) \ + (((x) >> BIT_SHIFT_BA_CONTENT_H_8822C) & BIT_MASK_BA_CONTENT_H_8822C) +#define BIT_SET_BA_CONTENT_H_8822C(x, v) \ + (BIT_CLEAR_BA_CONTENT_H_8822C(x) | BIT_BA_CONTENT_H_8822C(v)) + +/* 2 REG_LBDLY_8822C (LOOPBACK DELAY REGISTER) */ + +#define BIT_SHIFT_LBDLY_8822C 0 +#define BIT_MASK_LBDLY_8822C 0x1f +#define BIT_LBDLY_8822C(x) \ + (((x) & BIT_MASK_LBDLY_8822C) << BIT_SHIFT_LBDLY_8822C) +#define BITS_LBDLY_8822C (BIT_MASK_LBDLY_8822C << BIT_SHIFT_LBDLY_8822C) +#define BIT_CLEAR_LBDLY_8822C(x) ((x) & (~BITS_LBDLY_8822C)) +#define BIT_GET_LBDLY_8822C(x) \ + (((x) >> BIT_SHIFT_LBDLY_8822C) & BIT_MASK_LBDLY_8822C) +#define BIT_SET_LBDLY_8822C(x, v) \ + (BIT_CLEAR_LBDLY_8822C(x) | BIT_LBDLY_8822C(v)) + +/* 2 REG_WMAC_BACAM_RPMEN_8822C */ + +#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C 2 +#define BIT_MASK_BITMAP_SSNBK_COUNTER_8822C 0x3f +#define BIT_BITMAP_SSNBK_COUNTER_8822C(x) \ + (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822C) \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C) +#define BITS_BITMAP_SSNBK_COUNTER_8822C \ + (BIT_MASK_BITMAP_SSNBK_COUNTER_8822C \ + << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C) +#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822C(x) \ + ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8822C)) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8822C(x) \ + (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C) & \ + BIT_MASK_BITMAP_SSNBK_COUNTER_8822C) +#define BIT_SET_BITMAP_SSNBK_COUNTER_8822C(x, v) \ + (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822C(x) | \ + BIT_BITMAP_SSNBK_COUNTER_8822C(v)) + +#define BIT_BITMAP_EN_8822C BIT(1) +#define BIT_WMAC_BACAM_RPMEN_8822C BIT(0) + +/* 2 REG_TX_RX_8822C STATUS */ + +#define BIT_SHIFT_RXPKT_TYPE_8822C 2 +#define BIT_MASK_RXPKT_TYPE_8822C 0x3f +#define BIT_RXPKT_TYPE_8822C(x) \ + (((x) & BIT_MASK_RXPKT_TYPE_8822C) << BIT_SHIFT_RXPKT_TYPE_8822C) +#define BITS_RXPKT_TYPE_8822C \ + (BIT_MASK_RXPKT_TYPE_8822C << BIT_SHIFT_RXPKT_TYPE_8822C) +#define BIT_CLEAR_RXPKT_TYPE_8822C(x) ((x) & (~BITS_RXPKT_TYPE_8822C)) +#define BIT_GET_RXPKT_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_RXPKT_TYPE_8822C) & BIT_MASK_RXPKT_TYPE_8822C) +#define BIT_SET_RXPKT_TYPE_8822C(x, v) \ + (BIT_CLEAR_RXPKT_TYPE_8822C(x) | BIT_RXPKT_TYPE_8822C(v)) + +#define BIT_TXACT_IND_8822C BIT(1) +#define BIT_RXACT_IND_8822C BIT(0) + +/* 2 REG_WMAC_BITMAP_CTL_8822C */ +#define BIT_BITMAP_VO_8822C BIT(7) +#define BIT_BITMAP_VI_8822C BIT(6) +#define BIT_BITMAP_BE_8822C BIT(5) +#define BIT_BITMAP_BK_8822C BIT(4) + +#define BIT_SHIFT_BITMAP_CONDITION_8822C 2 +#define BIT_MASK_BITMAP_CONDITION_8822C 0x3 +#define BIT_BITMAP_CONDITION_8822C(x) \ + (((x) & BIT_MASK_BITMAP_CONDITION_8822C) \ + << BIT_SHIFT_BITMAP_CONDITION_8822C) +#define BITS_BITMAP_CONDITION_8822C \ + (BIT_MASK_BITMAP_CONDITION_8822C << BIT_SHIFT_BITMAP_CONDITION_8822C) +#define BIT_CLEAR_BITMAP_CONDITION_8822C(x) \ + ((x) & (~BITS_BITMAP_CONDITION_8822C)) +#define BIT_GET_BITMAP_CONDITION_8822C(x) \ + (((x) >> BIT_SHIFT_BITMAP_CONDITION_8822C) & \ + BIT_MASK_BITMAP_CONDITION_8822C) +#define BIT_SET_BITMAP_CONDITION_8822C(x, v) \ + (BIT_CLEAR_BITMAP_CONDITION_8822C(x) | BIT_BITMAP_CONDITION_8822C(v)) + +#define BIT_BITMAP_SSNBK_COUNTER_CLR_8822C BIT(1) +#define BIT_BITMAP_FORCE_8822C BIT(0) + +/* 2 REG_RXERR_RPT_8822C (RX ERROR REPORT REGISTER) */ + +#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C 28 +#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C 0xf +#define BIT_RXERR_RPT_SEL_V1_3_0_8822C(x) \ + (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C) \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C) +#define BITS_RXERR_RPT_SEL_V1_3_0_8822C \ + (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C \ + << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C) +#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822C(x) \ + ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8822C)) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822C(x) \ + (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C) & \ + BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C) +#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8822C(x, v) \ + (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822C(x) | \ + BIT_RXERR_RPT_SEL_V1_3_0_8822C(v)) + +#define BIT_RXERR_RPT_RST_8822C BIT(27) +#define BIT_RXERR_RPT_SEL_V1_4_8822C BIT(26) + +#define BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C 24 +#define BIT_MASK_UD_SELECT_BSSID_2_1_8822C 0x3 +#define BIT_UD_SELECT_BSSID_2_1_8822C(x) \ + (((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8822C) \ + << BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C) +#define BITS_UD_SELECT_BSSID_2_1_8822C \ + (BIT_MASK_UD_SELECT_BSSID_2_1_8822C \ + << BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C) +#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8822C(x) \ + ((x) & (~BITS_UD_SELECT_BSSID_2_1_8822C)) +#define BIT_GET_UD_SELECT_BSSID_2_1_8822C(x) \ + (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C) & \ + BIT_MASK_UD_SELECT_BSSID_2_1_8822C) +#define BIT_SET_UD_SELECT_BSSID_2_1_8822C(x, v) \ + (BIT_CLEAR_UD_SELECT_BSSID_2_1_8822C(x) | \ + BIT_UD_SELECT_BSSID_2_1_8822C(v)) + +#define BIT_W1S_8822C BIT(23) +#define BIT_UD_SELECT_BSSID_0_8822C BIT(22) + +#define BIT_SHIFT_UD_SUB_TYPE_8822C 18 +#define BIT_MASK_UD_SUB_TYPE_8822C 0xf +#define BIT_UD_SUB_TYPE_8822C(x) \ + (((x) & BIT_MASK_UD_SUB_TYPE_8822C) << BIT_SHIFT_UD_SUB_TYPE_8822C) +#define BITS_UD_SUB_TYPE_8822C \ + (BIT_MASK_UD_SUB_TYPE_8822C << BIT_SHIFT_UD_SUB_TYPE_8822C) +#define BIT_CLEAR_UD_SUB_TYPE_8822C(x) ((x) & (~BITS_UD_SUB_TYPE_8822C)) +#define BIT_GET_UD_SUB_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_UD_SUB_TYPE_8822C) & BIT_MASK_UD_SUB_TYPE_8822C) +#define BIT_SET_UD_SUB_TYPE_8822C(x, v) \ + (BIT_CLEAR_UD_SUB_TYPE_8822C(x) | BIT_UD_SUB_TYPE_8822C(v)) + +#define BIT_SHIFT_UD_TYPE_8822C 16 +#define BIT_MASK_UD_TYPE_8822C 0x3 +#define BIT_UD_TYPE_8822C(x) \ + (((x) & BIT_MASK_UD_TYPE_8822C) << BIT_SHIFT_UD_TYPE_8822C) +#define BITS_UD_TYPE_8822C (BIT_MASK_UD_TYPE_8822C << BIT_SHIFT_UD_TYPE_8822C) +#define BIT_CLEAR_UD_TYPE_8822C(x) ((x) & (~BITS_UD_TYPE_8822C)) +#define BIT_GET_UD_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_UD_TYPE_8822C) & BIT_MASK_UD_TYPE_8822C) +#define BIT_SET_UD_TYPE_8822C(x, v) \ + (BIT_CLEAR_UD_TYPE_8822C(x) | BIT_UD_TYPE_8822C(v)) + +#define BIT_SHIFT_RPT_COUNTER_8822C 0 +#define BIT_MASK_RPT_COUNTER_8822C 0xffff +#define BIT_RPT_COUNTER_8822C(x) \ + (((x) & BIT_MASK_RPT_COUNTER_8822C) << BIT_SHIFT_RPT_COUNTER_8822C) +#define BITS_RPT_COUNTER_8822C \ + (BIT_MASK_RPT_COUNTER_8822C << BIT_SHIFT_RPT_COUNTER_8822C) +#define BIT_CLEAR_RPT_COUNTER_8822C(x) ((x) & (~BITS_RPT_COUNTER_8822C)) +#define BIT_GET_RPT_COUNTER_8822C(x) \ + (((x) >> BIT_SHIFT_RPT_COUNTER_8822C) & BIT_MASK_RPT_COUNTER_8822C) +#define BIT_SET_RPT_COUNTER_8822C(x, v) \ + (BIT_CLEAR_RPT_COUNTER_8822C(x) | BIT_RPT_COUNTER_8822C(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_8822C (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ +#define BIT_ACKTO_BLOCK_SCH_EN_8822C BIT(27) +#define BIT_EIFS_BLOCK_SCH_EN_8822C BIT(26) +#define BIT_PLCPCHK_RST_EIFS_8822C BIT(25) +#define BIT_CCA_RST_EIFS_8822C BIT(24) +#define BIT_DIS_UPD_MYRXPKTNAV_8822C BIT(23) +#define BIT_EARLY_TXBA_8822C BIT(22) + +#define BIT_SHIFT_RESP_CHNBUSY_8822C 20 +#define BIT_MASK_RESP_CHNBUSY_8822C 0x3 +#define BIT_RESP_CHNBUSY_8822C(x) \ + (((x) & BIT_MASK_RESP_CHNBUSY_8822C) << BIT_SHIFT_RESP_CHNBUSY_8822C) +#define BITS_RESP_CHNBUSY_8822C \ + (BIT_MASK_RESP_CHNBUSY_8822C << BIT_SHIFT_RESP_CHNBUSY_8822C) +#define BIT_CLEAR_RESP_CHNBUSY_8822C(x) ((x) & (~BITS_RESP_CHNBUSY_8822C)) +#define BIT_GET_RESP_CHNBUSY_8822C(x) \ + (((x) >> BIT_SHIFT_RESP_CHNBUSY_8822C) & BIT_MASK_RESP_CHNBUSY_8822C) +#define BIT_SET_RESP_CHNBUSY_8822C(x, v) \ + (BIT_CLEAR_RESP_CHNBUSY_8822C(x) | BIT_RESP_CHNBUSY_8822C(v)) + +#define BIT_RESP_DCTS_EN_8822C BIT(19) +#define BIT_RESP_DCFE_EN_8822C BIT(18) +#define BIT_RESP_SPLCPEN_8822C BIT(17) +#define BIT_RESP_SGIEN_8822C BIT(16) +#define BIT_RESP_LDPC_EN_8822C BIT(15) +#define BIT_DIS_RESP_ACKINCCA_8822C BIT(14) +#define BIT_DIS_RESP_CTSINCCA_8822C BIT(13) + +#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C 10 +#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C 0x7 +#define BIT_R_WMAC_SECOND_CCA_TIMER_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C) \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C) +#define BITS_R_WMAC_SECOND_CCA_TIMER_8822C \ + (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C \ + << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C) +#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822C(x) \ + ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8822C)) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C) & \ + BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C) +#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822C(x) | \ + BIT_R_WMAC_SECOND_CCA_TIMER_8822C(v)) + +#define BIT_SHIFT_RFMOD_8822C 7 +#define BIT_MASK_RFMOD_8822C 0x3 +#define BIT_RFMOD_8822C(x) \ + (((x) & BIT_MASK_RFMOD_8822C) << BIT_SHIFT_RFMOD_8822C) +#define BITS_RFMOD_8822C (BIT_MASK_RFMOD_8822C << BIT_SHIFT_RFMOD_8822C) +#define BIT_CLEAR_RFMOD_8822C(x) ((x) & (~BITS_RFMOD_8822C)) +#define BIT_GET_RFMOD_8822C(x) \ + (((x) >> BIT_SHIFT_RFMOD_8822C) & BIT_MASK_RFMOD_8822C) +#define BIT_SET_RFMOD_8822C(x, v) \ + (BIT_CLEAR_RFMOD_8822C(x) | BIT_RFMOD_8822C(v)) + +#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C 5 +#define BIT_MASK_RESP_CTS_DYNBW_SEL_8822C 0x3 +#define BIT_RESP_CTS_DYNBW_SEL_8822C(x) \ + (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822C) \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C) +#define BITS_RESP_CTS_DYNBW_SEL_8822C \ + (BIT_MASK_RESP_CTS_DYNBW_SEL_8822C \ + << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C) +#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822C(x) \ + ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8822C)) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C) & \ + BIT_MASK_RESP_CTS_DYNBW_SEL_8822C) +#define BIT_SET_RESP_CTS_DYNBW_SEL_8822C(x, v) \ + (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822C(x) | \ + BIT_RESP_CTS_DYNBW_SEL_8822C(v)) + +#define BIT_DLY_TX_WAIT_RXANTSEL_8822C BIT(4) +#define BIT_TXRESP_BY_RXANTSEL_8822C BIT(3) + +#define BIT_SHIFT_ORIG_DCTS_CHK_8822C 0 +#define BIT_MASK_ORIG_DCTS_CHK_8822C 0x3 +#define BIT_ORIG_DCTS_CHK_8822C(x) \ + (((x) & BIT_MASK_ORIG_DCTS_CHK_8822C) << BIT_SHIFT_ORIG_DCTS_CHK_8822C) +#define BITS_ORIG_DCTS_CHK_8822C \ + (BIT_MASK_ORIG_DCTS_CHK_8822C << BIT_SHIFT_ORIG_DCTS_CHK_8822C) +#define BIT_CLEAR_ORIG_DCTS_CHK_8822C(x) ((x) & (~BITS_ORIG_DCTS_CHK_8822C)) +#define BIT_GET_ORIG_DCTS_CHK_8822C(x) \ + (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822C) & BIT_MASK_ORIG_DCTS_CHK_8822C) +#define BIT_SET_ORIG_DCTS_CHK_8822C(x, v) \ + (BIT_CLEAR_ORIG_DCTS_CHK_8822C(x) | BIT_ORIG_DCTS_CHK_8822C(v)) + +/* 2 REG_WMAC_TRXPTCL_CTL_H_8822C */ + +#define BIT_SHIFT_ACKBA_TYPSEL_8822C 28 +#define BIT_MASK_ACKBA_TYPSEL_8822C 0xf +#define BIT_ACKBA_TYPSEL_8822C(x) \ + (((x) & BIT_MASK_ACKBA_TYPSEL_8822C) << BIT_SHIFT_ACKBA_TYPSEL_8822C) +#define BITS_ACKBA_TYPSEL_8822C \ + (BIT_MASK_ACKBA_TYPSEL_8822C << BIT_SHIFT_ACKBA_TYPSEL_8822C) +#define BIT_CLEAR_ACKBA_TYPSEL_8822C(x) ((x) & (~BITS_ACKBA_TYPSEL_8822C)) +#define BIT_GET_ACKBA_TYPSEL_8822C(x) \ + (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822C) & BIT_MASK_ACKBA_TYPSEL_8822C) +#define BIT_SET_ACKBA_TYPSEL_8822C(x, v) \ + (BIT_CLEAR_ACKBA_TYPSEL_8822C(x) | BIT_ACKBA_TYPSEL_8822C(v)) + +#define BIT_SHIFT_ACKBA_ACKPCHK_8822C 24 +#define BIT_MASK_ACKBA_ACKPCHK_8822C 0xf +#define BIT_ACKBA_ACKPCHK_8822C(x) \ + (((x) & BIT_MASK_ACKBA_ACKPCHK_8822C) << BIT_SHIFT_ACKBA_ACKPCHK_8822C) +#define BITS_ACKBA_ACKPCHK_8822C \ + (BIT_MASK_ACKBA_ACKPCHK_8822C << BIT_SHIFT_ACKBA_ACKPCHK_8822C) +#define BIT_CLEAR_ACKBA_ACKPCHK_8822C(x) ((x) & (~BITS_ACKBA_ACKPCHK_8822C)) +#define BIT_GET_ACKBA_ACKPCHK_8822C(x) \ + (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822C) & BIT_MASK_ACKBA_ACKPCHK_8822C) +#define BIT_SET_ACKBA_ACKPCHK_8822C(x, v) \ + (BIT_CLEAR_ACKBA_ACKPCHK_8822C(x) | BIT_ACKBA_ACKPCHK_8822C(v)) + +#define BIT_SHIFT_ACKBAR_TYPESEL_8822C 16 +#define BIT_MASK_ACKBAR_TYPESEL_8822C 0xff +#define BIT_ACKBAR_TYPESEL_8822C(x) \ + (((x) & BIT_MASK_ACKBAR_TYPESEL_8822C) \ + << BIT_SHIFT_ACKBAR_TYPESEL_8822C) +#define BITS_ACKBAR_TYPESEL_8822C \ + (BIT_MASK_ACKBAR_TYPESEL_8822C << BIT_SHIFT_ACKBAR_TYPESEL_8822C) +#define BIT_CLEAR_ACKBAR_TYPESEL_8822C(x) ((x) & (~BITS_ACKBAR_TYPESEL_8822C)) +#define BIT_GET_ACKBAR_TYPESEL_8822C(x) \ + (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822C) & \ + BIT_MASK_ACKBAR_TYPESEL_8822C) +#define BIT_SET_ACKBAR_TYPESEL_8822C(x, v) \ + (BIT_CLEAR_ACKBAR_TYPESEL_8822C(x) | BIT_ACKBAR_TYPESEL_8822C(v)) + +#define BIT_SHIFT_ACKBAR_ACKPCHK_8822C 12 +#define BIT_MASK_ACKBAR_ACKPCHK_8822C 0xf +#define BIT_ACKBAR_ACKPCHK_8822C(x) \ + (((x) & BIT_MASK_ACKBAR_ACKPCHK_8822C) \ + << BIT_SHIFT_ACKBAR_ACKPCHK_8822C) +#define BITS_ACKBAR_ACKPCHK_8822C \ + (BIT_MASK_ACKBAR_ACKPCHK_8822C << BIT_SHIFT_ACKBAR_ACKPCHK_8822C) +#define BIT_CLEAR_ACKBAR_ACKPCHK_8822C(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8822C)) +#define BIT_GET_ACKBAR_ACKPCHK_8822C(x) \ + (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822C) & \ + BIT_MASK_ACKBAR_ACKPCHK_8822C) +#define BIT_SET_ACKBAR_ACKPCHK_8822C(x, v) \ + (BIT_CLEAR_ACKBAR_ACKPCHK_8822C(x) | BIT_ACKBAR_ACKPCHK_8822C(v)) + +#define BIT_RXBA_IGNOREA2_V1_8822C BIT(10) +#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8822C BIT(9) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8822C BIT(8) +#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8822C BIT(7) +#define BIT_DIS_TXBA_RXBARINFULL_V1_8822C BIT(6) +#define BIT_DIS_TXCFE_INFULL_V1_8822C BIT(5) +#define BIT_DIS_TXCTS_INFULL_V1_8822C BIT(4) +#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8822C BIT(3) +#define BIT_EN_TXACKBA_IN_TXOP_V1_8822C BIT(2) +#define BIT_EN_TXCTS_IN_RXNAV_V1_8822C BIT(1) +#define BIT_EN_TXCTS_INTXOP_V1_8822C BIT(0) + +/* 2 REG_CAMCMD_8822C (CAM COMMAND REGISTER) */ +#define BIT_SECCAM_POLLING_8822C BIT(31) +#define BIT_SECCAM_CLR_8822C BIT(30) +#define BIT_SECCAM_WE_8822C BIT(16) + +#define BIT_SHIFT_SECCAM_ADDR_V2_8822C 0 +#define BIT_MASK_SECCAM_ADDR_V2_8822C 0x3ff +#define BIT_SECCAM_ADDR_V2_8822C(x) \ + (((x) & BIT_MASK_SECCAM_ADDR_V2_8822C) \ + << BIT_SHIFT_SECCAM_ADDR_V2_8822C) +#define BITS_SECCAM_ADDR_V2_8822C \ + (BIT_MASK_SECCAM_ADDR_V2_8822C << BIT_SHIFT_SECCAM_ADDR_V2_8822C) +#define BIT_CLEAR_SECCAM_ADDR_V2_8822C(x) ((x) & (~BITS_SECCAM_ADDR_V2_8822C)) +#define BIT_GET_SECCAM_ADDR_V2_8822C(x) \ + (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822C) & \ + BIT_MASK_SECCAM_ADDR_V2_8822C) +#define BIT_SET_SECCAM_ADDR_V2_8822C(x, v) \ + (BIT_CLEAR_SECCAM_ADDR_V2_8822C(x) | BIT_SECCAM_ADDR_V2_8822C(v)) + +/* 2 REG_CAMWRITE_8822C (CAM WRITE REGISTER) */ + +#define BIT_SHIFT_CAMW_DATA_8822C 0 +#define BIT_MASK_CAMW_DATA_8822C 0xffffffffL +#define BIT_CAMW_DATA_8822C(x) \ + (((x) & BIT_MASK_CAMW_DATA_8822C) << BIT_SHIFT_CAMW_DATA_8822C) +#define BITS_CAMW_DATA_8822C \ + (BIT_MASK_CAMW_DATA_8822C << BIT_SHIFT_CAMW_DATA_8822C) +#define BIT_CLEAR_CAMW_DATA_8822C(x) ((x) & (~BITS_CAMW_DATA_8822C)) +#define BIT_GET_CAMW_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_CAMW_DATA_8822C) & BIT_MASK_CAMW_DATA_8822C) +#define BIT_SET_CAMW_DATA_8822C(x, v) \ + (BIT_CLEAR_CAMW_DATA_8822C(x) | BIT_CAMW_DATA_8822C(v)) + +/* 2 REG_CAMREAD_8822C (CAM READ REGISTER) */ + +#define BIT_SHIFT_CAMR_DATA_8822C 0 +#define BIT_MASK_CAMR_DATA_8822C 0xffffffffL +#define BIT_CAMR_DATA_8822C(x) \ + (((x) & BIT_MASK_CAMR_DATA_8822C) << BIT_SHIFT_CAMR_DATA_8822C) +#define BITS_CAMR_DATA_8822C \ + (BIT_MASK_CAMR_DATA_8822C << BIT_SHIFT_CAMR_DATA_8822C) +#define BIT_CLEAR_CAMR_DATA_8822C(x) ((x) & (~BITS_CAMR_DATA_8822C)) +#define BIT_GET_CAMR_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_CAMR_DATA_8822C) & BIT_MASK_CAMR_DATA_8822C) +#define BIT_SET_CAMR_DATA_8822C(x, v) \ + (BIT_CLEAR_CAMR_DATA_8822C(x) | BIT_CAMR_DATA_8822C(v)) + +/* 2 REG_CAMDBG_8822C (CAM DEBUG REGISTER) */ +#define BIT_SECCAM_INFO_8822C BIT(31) +#define BIT_SEC_KEYFOUND_8822C BIT(15) + +#define BIT_SHIFT_CAMDBG_SEC_TYPE_8822C 12 +#define BIT_MASK_CAMDBG_SEC_TYPE_8822C 0x7 +#define BIT_CAMDBG_SEC_TYPE_8822C(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822C) \ + << BIT_SHIFT_CAMDBG_SEC_TYPE_8822C) +#define BITS_CAMDBG_SEC_TYPE_8822C \ + (BIT_MASK_CAMDBG_SEC_TYPE_8822C << BIT_SHIFT_CAMDBG_SEC_TYPE_8822C) +#define BIT_CLEAR_CAMDBG_SEC_TYPE_8822C(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8822C)) +#define BIT_GET_CAMDBG_SEC_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822C) & \ + BIT_MASK_CAMDBG_SEC_TYPE_8822C) +#define BIT_SET_CAMDBG_SEC_TYPE_8822C(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_TYPE_8822C(x) | BIT_CAMDBG_SEC_TYPE_8822C(v)) + +#define BIT_CAMDBG_EXT_SECTYPE_8822C BIT(11) + +#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C 5 +#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C 0x1f +#define BIT_CAMDBG_MIC_KEY_IDX_8822C(x) \ + (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C) \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C) +#define BITS_CAMDBG_MIC_KEY_IDX_8822C \ + (BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C \ + << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C) +#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822C(x) \ + ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8822C)) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C) & \ + BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C) +#define BIT_SET_CAMDBG_MIC_KEY_IDX_8822C(x, v) \ + (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822C(x) | \ + BIT_CAMDBG_MIC_KEY_IDX_8822C(v)) + +#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C 0 +#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C 0x1f +#define BIT_CAMDBG_SEC_KEY_IDX_8822C(x) \ + (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C) \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C) +#define BITS_CAMDBG_SEC_KEY_IDX_8822C \ + (BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C \ + << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C) +#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822C(x) \ + ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8822C)) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C) & \ + BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C) +#define BIT_SET_CAMDBG_SEC_KEY_IDX_8822C(x, v) \ + (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822C(x) | \ + BIT_CAMDBG_SEC_KEY_IDX_8822C(v)) + +/* 2 REG_SECCFG_8822C (SECURITY CONFIGURATION REGISTER) */ +#define BIT_DIS_GCLK_WAPI_8822C BIT(15) +#define BIT_DIS_GCLK_AES_8822C BIT(14) +#define BIT_DIS_GCLK_TKIP_8822C BIT(13) +#define BIT_AES_SEL_QC_1_8822C BIT(12) +#define BIT_AES_SEL_QC_0_8822C BIT(11) +#define BIT_CHK_BMC_8822C BIT(9) +#define BIT_CHK_KEYID_8822C BIT(8) +#define BIT_RXBCUSEDK_8822C BIT(7) +#define BIT_TXBCUSEDK_8822C BIT(6) +#define BIT_NOSKMC_8822C BIT(5) +#define BIT_SKBYA2_8822C BIT(4) +#define BIT_RXDEC_8822C BIT(3) +#define BIT_TXENC_8822C BIT(2) +#define BIT_RXUHUSEDK_8822C BIT(1) +#define BIT_TXUHUSEDK_8822C BIT(0) + +/* 2 REG_RXFILTER_CATEGORY_1_8822C */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_1_8822C 0 +#define BIT_MASK_RXFILTER_CATEGORY_1_8822C 0xff +#define BIT_RXFILTER_CATEGORY_1_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8822C) +#define BITS_RXFILTER_CATEGORY_1_8822C \ + (BIT_MASK_RXFILTER_CATEGORY_1_8822C \ + << BIT_SHIFT_RXFILTER_CATEGORY_1_8822C) +#define BIT_CLEAR_RXFILTER_CATEGORY_1_8822C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_1_8822C)) +#define BIT_GET_RXFILTER_CATEGORY_1_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822C) & \ + BIT_MASK_RXFILTER_CATEGORY_1_8822C) +#define BIT_SET_RXFILTER_CATEGORY_1_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_1_8822C(x) | \ + BIT_RXFILTER_CATEGORY_1_8822C(v)) + +/* 2 REG_RXFILTER_ACTION_1_8822C */ + +#define BIT_SHIFT_RXFILTER_ACTION_1_8822C 0 +#define BIT_MASK_RXFILTER_ACTION_1_8822C 0xff +#define BIT_RXFILTER_ACTION_1_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_1_8822C) \ + << BIT_SHIFT_RXFILTER_ACTION_1_8822C) +#define BITS_RXFILTER_ACTION_1_8822C \ + (BIT_MASK_RXFILTER_ACTION_1_8822C << BIT_SHIFT_RXFILTER_ACTION_1_8822C) +#define BIT_CLEAR_RXFILTER_ACTION_1_8822C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_1_8822C)) +#define BIT_GET_RXFILTER_ACTION_1_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822C) & \ + BIT_MASK_RXFILTER_ACTION_1_8822C) +#define BIT_SET_RXFILTER_ACTION_1_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_1_8822C(x) | BIT_RXFILTER_ACTION_1_8822C(v)) + +/* 2 REG_RXFILTER_CATEGORY_2_8822C */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_2_8822C 0 +#define BIT_MASK_RXFILTER_CATEGORY_2_8822C 0xff +#define BIT_RXFILTER_CATEGORY_2_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8822C) +#define BITS_RXFILTER_CATEGORY_2_8822C \ + (BIT_MASK_RXFILTER_CATEGORY_2_8822C \ + << BIT_SHIFT_RXFILTER_CATEGORY_2_8822C) +#define BIT_CLEAR_RXFILTER_CATEGORY_2_8822C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_2_8822C)) +#define BIT_GET_RXFILTER_CATEGORY_2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822C) & \ + BIT_MASK_RXFILTER_CATEGORY_2_8822C) +#define BIT_SET_RXFILTER_CATEGORY_2_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_2_8822C(x) | \ + BIT_RXFILTER_CATEGORY_2_8822C(v)) + +/* 2 REG_RXFILTER_ACTION_2_8822C */ + +#define BIT_SHIFT_RXFILTER_ACTION_2_8822C 0 +#define BIT_MASK_RXFILTER_ACTION_2_8822C 0xff +#define BIT_RXFILTER_ACTION_2_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_2_8822C) \ + << BIT_SHIFT_RXFILTER_ACTION_2_8822C) +#define BITS_RXFILTER_ACTION_2_8822C \ + (BIT_MASK_RXFILTER_ACTION_2_8822C << BIT_SHIFT_RXFILTER_ACTION_2_8822C) +#define BIT_CLEAR_RXFILTER_ACTION_2_8822C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_2_8822C)) +#define BIT_GET_RXFILTER_ACTION_2_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822C) & \ + BIT_MASK_RXFILTER_ACTION_2_8822C) +#define BIT_SET_RXFILTER_ACTION_2_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_2_8822C(x) | BIT_RXFILTER_ACTION_2_8822C(v)) + +/* 2 REG_RXFILTER_CATEGORY_3_8822C */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_3_8822C 0 +#define BIT_MASK_RXFILTER_CATEGORY_3_8822C 0xff +#define BIT_RXFILTER_CATEGORY_3_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822C) \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8822C) +#define BITS_RXFILTER_CATEGORY_3_8822C \ + (BIT_MASK_RXFILTER_CATEGORY_3_8822C \ + << BIT_SHIFT_RXFILTER_CATEGORY_3_8822C) +#define BIT_CLEAR_RXFILTER_CATEGORY_3_8822C(x) \ + ((x) & (~BITS_RXFILTER_CATEGORY_3_8822C)) +#define BIT_GET_RXFILTER_CATEGORY_3_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822C) & \ + BIT_MASK_RXFILTER_CATEGORY_3_8822C) +#define BIT_SET_RXFILTER_CATEGORY_3_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_CATEGORY_3_8822C(x) | \ + BIT_RXFILTER_CATEGORY_3_8822C(v)) + +/* 2 REG_RXFILTER_ACTION_3_8822C */ + +#define BIT_SHIFT_RXFILTER_ACTION_3_8822C 0 +#define BIT_MASK_RXFILTER_ACTION_3_8822C 0xff +#define BIT_RXFILTER_ACTION_3_8822C(x) \ + (((x) & BIT_MASK_RXFILTER_ACTION_3_8822C) \ + << BIT_SHIFT_RXFILTER_ACTION_3_8822C) +#define BITS_RXFILTER_ACTION_3_8822C \ + (BIT_MASK_RXFILTER_ACTION_3_8822C << BIT_SHIFT_RXFILTER_ACTION_3_8822C) +#define BIT_CLEAR_RXFILTER_ACTION_3_8822C(x) \ + ((x) & (~BITS_RXFILTER_ACTION_3_8822C)) +#define BIT_GET_RXFILTER_ACTION_3_8822C(x) \ + (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822C) & \ + BIT_MASK_RXFILTER_ACTION_3_8822C) +#define BIT_SET_RXFILTER_ACTION_3_8822C(x, v) \ + (BIT_CLEAR_RXFILTER_ACTION_3_8822C(x) | BIT_RXFILTER_ACTION_3_8822C(v)) + +/* 2 REG_RXFLTMAP3_8822C (RX FILTER MAP GROUP 3) */ +#define BIT_MGTFLT15EN_FW_8822C BIT(15) +#define BIT_MGTFLT14EN_FW_8822C BIT(14) +#define BIT_MGTFLT13EN_FW_8822C BIT(13) +#define BIT_MGTFLT12EN_FW_8822C BIT(12) +#define BIT_MGTFLT11EN_FW_8822C BIT(11) +#define BIT_MGTFLT10EN_FW_8822C BIT(10) +#define BIT_MGTFLT9EN_FW_8822C BIT(9) +#define BIT_MGTFLT8EN_FW_8822C BIT(8) +#define BIT_MGTFLT7EN_FW_8822C BIT(7) +#define BIT_MGTFLT6EN_FW_8822C BIT(6) +#define BIT_MGTFLT5EN_FW_8822C BIT(5) +#define BIT_MGTFLT4EN_FW_8822C BIT(4) +#define BIT_MGTFLT3EN_FW_8822C BIT(3) +#define BIT_MGTFLT2EN_FW_8822C BIT(2) +#define BIT_MGTFLT1EN_FW_8822C BIT(1) +#define BIT_MGTFLT0EN_FW_8822C BIT(0) + +/* 2 REG_RXFLTMAP4_8822C (RX FILTER MAP GROUP 4) */ +#define BIT_CTRLFLT15EN_FW_8822C BIT(15) +#define BIT_CTRLFLT14EN_FW_8822C BIT(14) +#define BIT_CTRLFLT13EN_FW_8822C BIT(13) +#define BIT_CTRLFLT12EN_FW_8822C BIT(12) +#define BIT_CTRLFLT11EN_FW_8822C BIT(11) +#define BIT_CTRLFLT10EN_FW_8822C BIT(10) +#define BIT_CTRLFLT9EN_FW_8822C BIT(9) +#define BIT_CTRLFLT8EN_FW_8822C BIT(8) +#define BIT_CTRLFLT7EN_FW_8822C BIT(7) +#define BIT_CTRLFLT6EN_FW_8822C BIT(6) +#define BIT_CTRLFLT5EN_FW_8822C BIT(5) +#define BIT_CTRLFLT4EN_FW_8822C BIT(4) +#define BIT_CTRLFLT3EN_FW_8822C BIT(3) +#define BIT_CTRLFLT2EN_FW_8822C BIT(2) +#define BIT_CTRLFLT1EN_FW_8822C BIT(1) +#define BIT_CTRLFLT0EN_FW_8822C BIT(0) + +/* 2 REG_RXFLTMAP5_8822C (RX FILTER MAP GROUP 5) */ +#define BIT_DATAFLT15EN_FW_8822C BIT(15) +#define BIT_DATAFLT14EN_FW_8822C BIT(14) +#define BIT_DATAFLT13EN_FW_8822C BIT(13) +#define BIT_DATAFLT12EN_FW_8822C BIT(12) +#define BIT_DATAFLT11EN_FW_8822C BIT(11) +#define BIT_DATAFLT10EN_FW_8822C BIT(10) +#define BIT_DATAFLT9EN_FW_8822C BIT(9) +#define BIT_DATAFLT8EN_FW_8822C BIT(8) +#define BIT_DATAFLT7EN_FW_8822C BIT(7) +#define BIT_DATAFLT6EN_FW_8822C BIT(6) +#define BIT_DATAFLT5EN_FW_8822C BIT(5) +#define BIT_DATAFLT4EN_FW_8822C BIT(4) +#define BIT_DATAFLT3EN_FW_8822C BIT(3) +#define BIT_DATAFLT2EN_FW_8822C BIT(2) +#define BIT_DATAFLT1EN_FW_8822C BIT(1) +#define BIT_DATAFLT0EN_FW_8822C BIT(0) + +/* 2 REG_RXFLTMAP6_8822C (RX FILTER MAP GROUP 6) */ +#define BIT_ACTIONFLT15EN_FW_8822C BIT(15) +#define BIT_ACTIONFLT14EN_FW_8822C BIT(14) +#define BIT_ACTIONFLT13EN_FW_8822C BIT(13) +#define BIT_ACTIONFLT12EN_FW_8822C BIT(12) +#define BIT_ACTIONFLT11EN_FW_8822C BIT(11) +#define BIT_ACTIONFLT10EN_FW_8822C BIT(10) +#define BIT_ACTIONFLT9EN_FW_8822C BIT(9) +#define BIT_ACTIONFLT8EN_FW_8822C BIT(8) +#define BIT_ACTIONFLT7EN_FW_8822C BIT(7) +#define BIT_ACTIONFLT6EN_FW_8822C BIT(6) +#define BIT_ACTIONFLT5EN_FW_8822C BIT(5) +#define BIT_ACTIONFLT4EN_FW_8822C BIT(4) +#define BIT_ACTIONFLT3EN_FW_8822C BIT(3) +#define BIT_ACTIONFLT2EN_FW_8822C BIT(2) +#define BIT_ACTIONFLT1EN_FW_8822C BIT(1) +#define BIT_ACTIONFLT0EN_FW_8822C BIT(0) + +/* 2 REG_WOW_CTRL_8822C (WAKE ON WLAN CONTROL REGISTER) */ + +#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C 6 +#define BIT_MASK_PSF_BSSIDSEL_B2B1_8822C 0x3 +#define BIT_PSF_BSSIDSEL_B2B1_8822C(x) \ + (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822C) \ + << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C) +#define BITS_PSF_BSSIDSEL_B2B1_8822C \ + (BIT_MASK_PSF_BSSIDSEL_B2B1_8822C << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C) +#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822C(x) \ + ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8822C)) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8822C(x) \ + (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C) & \ + BIT_MASK_PSF_BSSIDSEL_B2B1_8822C) +#define BIT_SET_PSF_BSSIDSEL_B2B1_8822C(x, v) \ + (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822C(x) | BIT_PSF_BSSIDSEL_B2B1_8822C(v)) + +#define BIT_WOWHCI_8822C BIT(5) +#define BIT_PSF_BSSIDSEL_B0_8822C BIT(4) +#define BIT_UWF_8822C BIT(3) +#define BIT_MAGIC_8822C BIT(2) +#define BIT_WOWEN_8822C BIT(1) +#define BIT_FORCE_WAKEUP_8822C BIT(0) + +/* 2 REG_NAN_RX_TSF_FILTER_8822C(NAN_RX_TSF_ADDRESS_FILTER) */ +#define BIT_CHK_TSF_TA_8822C BIT(2) +#define BIT_CHK_TSF_CBSSID_8822C BIT(1) +#define BIT_CHK_TSF_EN_8822C BIT(0) + +/* 2 REG_PS_RX_INFO_8822C (POWER SAVE RX INFORMATION REGISTER) */ + +#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C 5 +#define BIT_MASK_PORTSEL__PS_RX_INFO_8822C 0x7 +#define BIT_PORTSEL__PS_RX_INFO_8822C(x) \ + (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822C) \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C) +#define BITS_PORTSEL__PS_RX_INFO_8822C \ + (BIT_MASK_PORTSEL__PS_RX_INFO_8822C \ + << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C) +#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8822C(x) \ + ((x) & (~BITS_PORTSEL__PS_RX_INFO_8822C)) +#define BIT_GET_PORTSEL__PS_RX_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C) & \ + BIT_MASK_PORTSEL__PS_RX_INFO_8822C) +#define BIT_SET_PORTSEL__PS_RX_INFO_8822C(x, v) \ + (BIT_CLEAR_PORTSEL__PS_RX_INFO_8822C(x) | \ + BIT_PORTSEL__PS_RX_INFO_8822C(v)) + +#define BIT_RXCTRLIN0_8822C BIT(4) +#define BIT_RXMGTIN0_8822C BIT(3) +#define BIT_RXDATAIN2_8822C BIT(2) +#define BIT_RXDATAIN1_8822C BIT(1) +#define BIT_RXDATAIN0_8822C BIT(0) + +/* 2 REG_WMMPS_UAPSD_TID_8822C (WMM POWER SAVE UAPSD TID REGISTER) */ +#define BIT_WMMPS_UAPSD_TID7_8822C BIT(7) +#define BIT_WMMPS_UAPSD_TID6_8822C BIT(6) +#define BIT_WMMPS_UAPSD_TID5_8822C BIT(5) +#define BIT_WMMPS_UAPSD_TID4_8822C BIT(4) +#define BIT_WMMPS_UAPSD_TID3_8822C BIT(3) +#define BIT_WMMPS_UAPSD_TID2_8822C BIT(2) +#define BIT_WMMPS_UAPSD_TID1_8822C BIT(1) +#define BIT_WMMPS_UAPSD_TID0_8822C BIT(0) + +/* 2 REG_LPNAV_CTRL_8822C (LOW POWER NAV CONTROL REGISTER) */ + +/* 2 REG_WKFMCAM_CMD_8822C (WAKEUP FRAME CAM COMMAND REGISTER) */ +#define BIT_WKFCAM_POLLING_V1_8822C BIT(31) +#define BIT_WKFCAM_CLR_V1_8822C BIT(30) +#define BIT_WKFCAM_WE_8822C BIT(16) + +#define BIT_SHIFT_WKFCAM_ADDR_V2_8822C 8 +#define BIT_MASK_WKFCAM_ADDR_V2_8822C 0xff +#define BIT_WKFCAM_ADDR_V2_8822C(x) \ + (((x) & BIT_MASK_WKFCAM_ADDR_V2_8822C) \ + << BIT_SHIFT_WKFCAM_ADDR_V2_8822C) +#define BITS_WKFCAM_ADDR_V2_8822C \ + (BIT_MASK_WKFCAM_ADDR_V2_8822C << BIT_SHIFT_WKFCAM_ADDR_V2_8822C) +#define BIT_CLEAR_WKFCAM_ADDR_V2_8822C(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8822C)) +#define BIT_GET_WKFCAM_ADDR_V2_8822C(x) \ + (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822C) & \ + BIT_MASK_WKFCAM_ADDR_V2_8822C) +#define BIT_SET_WKFCAM_ADDR_V2_8822C(x, v) \ + (BIT_CLEAR_WKFCAM_ADDR_V2_8822C(x) | BIT_WKFCAM_ADDR_V2_8822C(v)) + +#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C 0 +#define BIT_MASK_WKFCAM_CAM_NUM_V1_8822C 0xff +#define BIT_WKFCAM_CAM_NUM_V1_8822C(x) \ + (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822C) \ + << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C) +#define BITS_WKFCAM_CAM_NUM_V1_8822C \ + (BIT_MASK_WKFCAM_CAM_NUM_V1_8822C << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C) +#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822C(x) \ + ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8822C)) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8822C(x) \ + (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C) & \ + BIT_MASK_WKFCAM_CAM_NUM_V1_8822C) +#define BIT_SET_WKFCAM_CAM_NUM_V1_8822C(x, v) \ + (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822C(x) | BIT_WKFCAM_CAM_NUM_V1_8822C(v)) + +/* 2 REG_WKFMCAM_RWD_8822C (WAKEUP FRAME READ/WRITE DATA) */ + +#define BIT_SHIFT_WKFMCAM_RWD_8822C 0 +#define BIT_MASK_WKFMCAM_RWD_8822C 0xffffffffL +#define BIT_WKFMCAM_RWD_8822C(x) \ + (((x) & BIT_MASK_WKFMCAM_RWD_8822C) << BIT_SHIFT_WKFMCAM_RWD_8822C) +#define BITS_WKFMCAM_RWD_8822C \ + (BIT_MASK_WKFMCAM_RWD_8822C << BIT_SHIFT_WKFMCAM_RWD_8822C) +#define BIT_CLEAR_WKFMCAM_RWD_8822C(x) ((x) & (~BITS_WKFMCAM_RWD_8822C)) +#define BIT_GET_WKFMCAM_RWD_8822C(x) \ + (((x) >> BIT_SHIFT_WKFMCAM_RWD_8822C) & BIT_MASK_WKFMCAM_RWD_8822C) +#define BIT_SET_WKFMCAM_RWD_8822C(x, v) \ + (BIT_CLEAR_WKFMCAM_RWD_8822C(x) | BIT_WKFMCAM_RWD_8822C(v)) + +/* 2 REG_RXFLTMAP0_8822C (RX FILTER MAP GROUP 0) */ +#define BIT_MGTFLT15EN_8822C BIT(15) +#define BIT_MGTFLT14EN_8822C BIT(14) +#define BIT_MGTFLT13EN_8822C BIT(13) +#define BIT_MGTFLT12EN_8822C BIT(12) +#define BIT_MGTFLT11EN_8822C BIT(11) +#define BIT_MGTFLT10EN_8822C BIT(10) +#define BIT_MGTFLT9EN_8822C BIT(9) +#define BIT_MGTFLT8EN_8822C BIT(8) +#define BIT_MGTFLT7EN_8822C BIT(7) +#define BIT_MGTFLT6EN_8822C BIT(6) +#define BIT_MGTFLT5EN_8822C BIT(5) +#define BIT_MGTFLT4EN_8822C BIT(4) +#define BIT_MGTFLT3EN_8822C BIT(3) +#define BIT_MGTFLT2EN_8822C BIT(2) +#define BIT_MGTFLT1EN_8822C BIT(1) +#define BIT_MGTFLT0EN_8822C BIT(0) + +/* 2 REG_RXFLTMAP1_8822C (RX FILTER MAP GROUP 1) */ +#define BIT_CTRLFLT15EN_8822C BIT(15) +#define BIT_CTRLFLT14EN_8822C BIT(14) +#define BIT_CTRLFLT13EN_8822C BIT(13) +#define BIT_CTRLFLT12EN_8822C BIT(12) +#define BIT_CTRLFLT11EN_8822C BIT(11) +#define BIT_CTRLFLT10EN_8822C BIT(10) +#define BIT_CTRLFLT9EN_8822C BIT(9) +#define BIT_CTRLFLT8EN_8822C BIT(8) +#define BIT_CTRLFLT7EN_8822C BIT(7) +#define BIT_CTRLFLT6EN_8822C BIT(6) +#define BIT_CTRLFLT5EN_8822C BIT(5) +#define BIT_CTRLFLT4EN_8822C BIT(4) +#define BIT_CTRLFLT3EN_8822C BIT(3) +#define BIT_CTRLFLT2EN_8822C BIT(2) +#define BIT_CTRLFLT1EN_8822C BIT(1) +#define BIT_CTRLFLT0EN_8822C BIT(0) + +/* 2 REG_RXFLTMAP2_8822C (RX FILTER MAP GROUP 2) */ +#define BIT_DATAFLT15EN_8822C BIT(15) +#define BIT_DATAFLT14EN_8822C BIT(14) +#define BIT_DATAFLT13EN_8822C BIT(13) +#define BIT_DATAFLT12EN_8822C BIT(12) +#define BIT_DATAFLT11EN_8822C BIT(11) +#define BIT_DATAFLT10EN_8822C BIT(10) +#define BIT_DATAFLT9EN_8822C BIT(9) +#define BIT_DATAFLT8EN_8822C BIT(8) +#define BIT_DATAFLT7EN_8822C BIT(7) +#define BIT_DATAFLT6EN_8822C BIT(6) +#define BIT_DATAFLT5EN_8822C BIT(5) +#define BIT_DATAFLT4EN_8822C BIT(4) +#define BIT_DATAFLT3EN_8822C BIT(3) +#define BIT_DATAFLT2EN_8822C BIT(2) +#define BIT_DATAFLT1EN_8822C BIT(1) +#define BIT_DATAFLT0EN_8822C BIT(0) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_BCN_PSR_RPT_8822C (BEACON PARSER REPORT REGISTER) */ + +#define BIT_SHIFT_DTIM_CNT_8822C 24 +#define BIT_MASK_DTIM_CNT_8822C 0xff +#define BIT_DTIM_CNT_8822C(x) \ + (((x) & BIT_MASK_DTIM_CNT_8822C) << BIT_SHIFT_DTIM_CNT_8822C) +#define BITS_DTIM_CNT_8822C \ + (BIT_MASK_DTIM_CNT_8822C << BIT_SHIFT_DTIM_CNT_8822C) +#define BIT_CLEAR_DTIM_CNT_8822C(x) ((x) & (~BITS_DTIM_CNT_8822C)) +#define BIT_GET_DTIM_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT_8822C) & BIT_MASK_DTIM_CNT_8822C) +#define BIT_SET_DTIM_CNT_8822C(x, v) \ + (BIT_CLEAR_DTIM_CNT_8822C(x) | BIT_DTIM_CNT_8822C(v)) + +#define BIT_SHIFT_DTIM_PERIOD_8822C 16 +#define BIT_MASK_DTIM_PERIOD_8822C 0xff +#define BIT_DTIM_PERIOD_8822C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD_8822C) << BIT_SHIFT_DTIM_PERIOD_8822C) +#define BITS_DTIM_PERIOD_8822C \ + (BIT_MASK_DTIM_PERIOD_8822C << BIT_SHIFT_DTIM_PERIOD_8822C) +#define BIT_CLEAR_DTIM_PERIOD_8822C(x) ((x) & (~BITS_DTIM_PERIOD_8822C)) +#define BIT_GET_DTIM_PERIOD_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD_8822C) & BIT_MASK_DTIM_PERIOD_8822C) +#define BIT_SET_DTIM_PERIOD_8822C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD_8822C(x) | BIT_DTIM_PERIOD_8822C(v)) + +#define BIT_DTIM_8822C BIT(15) +#define BIT_TIM_8822C BIT(14) +#define BIT_RPT_VALID_8822C BIT(13) + +#define BIT_SHIFT_PS_AID_0_8822C 0 +#define BIT_MASK_PS_AID_0_8822C 0x7ff +#define BIT_PS_AID_0_8822C(x) \ + (((x) & BIT_MASK_PS_AID_0_8822C) << BIT_SHIFT_PS_AID_0_8822C) +#define BITS_PS_AID_0_8822C \ + (BIT_MASK_PS_AID_0_8822C << BIT_SHIFT_PS_AID_0_8822C) +#define BIT_CLEAR_PS_AID_0_8822C(x) ((x) & (~BITS_PS_AID_0_8822C)) +#define BIT_GET_PS_AID_0_8822C(x) \ + (((x) >> BIT_SHIFT_PS_AID_0_8822C) & BIT_MASK_PS_AID_0_8822C) +#define BIT_SET_PS_AID_0_8822C(x, v) \ + (BIT_CLEAR_PS_AID_0_8822C(x) | BIT_PS_AID_0_8822C(v)) + +/* 2 REG_FLC_RPC_8822C (FW LPS CONDITION -- RX PKT COUNTER) */ + +#define BIT_SHIFT_FLC_RPC_8822C 0 +#define BIT_MASK_FLC_RPC_8822C 0xff +#define BIT_FLC_RPC_8822C(x) \ + (((x) & BIT_MASK_FLC_RPC_8822C) << BIT_SHIFT_FLC_RPC_8822C) +#define BITS_FLC_RPC_8822C (BIT_MASK_FLC_RPC_8822C << BIT_SHIFT_FLC_RPC_8822C) +#define BIT_CLEAR_FLC_RPC_8822C(x) ((x) & (~BITS_FLC_RPC_8822C)) +#define BIT_GET_FLC_RPC_8822C(x) \ + (((x) >> BIT_SHIFT_FLC_RPC_8822C) & BIT_MASK_FLC_RPC_8822C) +#define BIT_SET_FLC_RPC_8822C(x, v) \ + (BIT_CLEAR_FLC_RPC_8822C(x) | BIT_FLC_RPC_8822C(v)) + +/* 2 REG_FLC_RPCT_8822C (FLC_RPC THRESHOLD) */ + +#define BIT_SHIFT_FLC_RPCT_8822C 0 +#define BIT_MASK_FLC_RPCT_8822C 0xff +#define BIT_FLC_RPCT_8822C(x) \ + (((x) & BIT_MASK_FLC_RPCT_8822C) << BIT_SHIFT_FLC_RPCT_8822C) +#define BITS_FLC_RPCT_8822C \ + (BIT_MASK_FLC_RPCT_8822C << BIT_SHIFT_FLC_RPCT_8822C) +#define BIT_CLEAR_FLC_RPCT_8822C(x) ((x) & (~BITS_FLC_RPCT_8822C)) +#define BIT_GET_FLC_RPCT_8822C(x) \ + (((x) >> BIT_SHIFT_FLC_RPCT_8822C) & BIT_MASK_FLC_RPCT_8822C) +#define BIT_SET_FLC_RPCT_8822C(x, v) \ + (BIT_CLEAR_FLC_RPCT_8822C(x) | BIT_FLC_RPCT_8822C(v)) + +/* 2 REG_FLC_PTS_8822C (PKT TYPE SELECTION OF FLC_RPC T) */ +#define BIT_CMF_8822C BIT(2) +#define BIT_CCF_8822C BIT(1) +#define BIT_CDF_8822C BIT(0) + +/* 2 REG_FLC_TRPC_8822C (TIMER OF FLC_RPC) */ +#define BIT_FLC_RPCT_V1_8822C BIT(7) +#define BIT_MODE_8822C BIT(6) + +#define BIT_SHIFT_TRPCD_8822C 0 +#define BIT_MASK_TRPCD_8822C 0x3f +#define BIT_TRPCD_8822C(x) \ + (((x) & BIT_MASK_TRPCD_8822C) << BIT_SHIFT_TRPCD_8822C) +#define BITS_TRPCD_8822C (BIT_MASK_TRPCD_8822C << BIT_SHIFT_TRPCD_8822C) +#define BIT_CLEAR_TRPCD_8822C(x) ((x) & (~BITS_TRPCD_8822C)) +#define BIT_GET_TRPCD_8822C(x) \ + (((x) >> BIT_SHIFT_TRPCD_8822C) & BIT_MASK_TRPCD_8822C) +#define BIT_SET_TRPCD_8822C(x, v) \ + (BIT_CLEAR_TRPCD_8822C(x) | BIT_TRPCD_8822C(v)) + +/* 2 REG_RXPKTMON_CTRL_8822C */ + +#define BIT_SHIFT_RXBKQPKT_SEQ_8822C 20 +#define BIT_MASK_RXBKQPKT_SEQ_8822C 0xf +#define BIT_RXBKQPKT_SEQ_8822C(x) \ + (((x) & BIT_MASK_RXBKQPKT_SEQ_8822C) << BIT_SHIFT_RXBKQPKT_SEQ_8822C) +#define BITS_RXBKQPKT_SEQ_8822C \ + (BIT_MASK_RXBKQPKT_SEQ_8822C << BIT_SHIFT_RXBKQPKT_SEQ_8822C) +#define BIT_CLEAR_RXBKQPKT_SEQ_8822C(x) ((x) & (~BITS_RXBKQPKT_SEQ_8822C)) +#define BIT_GET_RXBKQPKT_SEQ_8822C(x) \ + (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822C) & BIT_MASK_RXBKQPKT_SEQ_8822C) +#define BIT_SET_RXBKQPKT_SEQ_8822C(x, v) \ + (BIT_CLEAR_RXBKQPKT_SEQ_8822C(x) | BIT_RXBKQPKT_SEQ_8822C(v)) + +#define BIT_SHIFT_RXBEQPKT_SEQ_8822C 16 +#define BIT_MASK_RXBEQPKT_SEQ_8822C 0xf +#define BIT_RXBEQPKT_SEQ_8822C(x) \ + (((x) & BIT_MASK_RXBEQPKT_SEQ_8822C) << BIT_SHIFT_RXBEQPKT_SEQ_8822C) +#define BITS_RXBEQPKT_SEQ_8822C \ + (BIT_MASK_RXBEQPKT_SEQ_8822C << BIT_SHIFT_RXBEQPKT_SEQ_8822C) +#define BIT_CLEAR_RXBEQPKT_SEQ_8822C(x) ((x) & (~BITS_RXBEQPKT_SEQ_8822C)) +#define BIT_GET_RXBEQPKT_SEQ_8822C(x) \ + (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822C) & BIT_MASK_RXBEQPKT_SEQ_8822C) +#define BIT_SET_RXBEQPKT_SEQ_8822C(x, v) \ + (BIT_CLEAR_RXBEQPKT_SEQ_8822C(x) | BIT_RXBEQPKT_SEQ_8822C(v)) + +#define BIT_SHIFT_RXVIQPKT_SEQ_8822C 12 +#define BIT_MASK_RXVIQPKT_SEQ_8822C 0xf +#define BIT_RXVIQPKT_SEQ_8822C(x) \ + (((x) & BIT_MASK_RXVIQPKT_SEQ_8822C) << BIT_SHIFT_RXVIQPKT_SEQ_8822C) +#define BITS_RXVIQPKT_SEQ_8822C \ + (BIT_MASK_RXVIQPKT_SEQ_8822C << BIT_SHIFT_RXVIQPKT_SEQ_8822C) +#define BIT_CLEAR_RXVIQPKT_SEQ_8822C(x) ((x) & (~BITS_RXVIQPKT_SEQ_8822C)) +#define BIT_GET_RXVIQPKT_SEQ_8822C(x) \ + (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822C) & BIT_MASK_RXVIQPKT_SEQ_8822C) +#define BIT_SET_RXVIQPKT_SEQ_8822C(x, v) \ + (BIT_CLEAR_RXVIQPKT_SEQ_8822C(x) | BIT_RXVIQPKT_SEQ_8822C(v)) + +#define BIT_SHIFT_RXVOQPKT_SEQ_8822C 8 +#define BIT_MASK_RXVOQPKT_SEQ_8822C 0xf +#define BIT_RXVOQPKT_SEQ_8822C(x) \ + (((x) & BIT_MASK_RXVOQPKT_SEQ_8822C) << BIT_SHIFT_RXVOQPKT_SEQ_8822C) +#define BITS_RXVOQPKT_SEQ_8822C \ + (BIT_MASK_RXVOQPKT_SEQ_8822C << BIT_SHIFT_RXVOQPKT_SEQ_8822C) +#define BIT_CLEAR_RXVOQPKT_SEQ_8822C(x) ((x) & (~BITS_RXVOQPKT_SEQ_8822C)) +#define BIT_GET_RXVOQPKT_SEQ_8822C(x) \ + (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822C) & BIT_MASK_RXVOQPKT_SEQ_8822C) +#define BIT_SET_RXVOQPKT_SEQ_8822C(x, v) \ + (BIT_CLEAR_RXVOQPKT_SEQ_8822C(x) | BIT_RXVOQPKT_SEQ_8822C(v)) + +#define BIT_RXBKQPKT_ERR_8822C BIT(7) +#define BIT_RXBEQPKT_ERR_8822C BIT(6) +#define BIT_RXVIQPKT_ERR_8822C BIT(5) +#define BIT_RXVOQPKT_ERR_8822C BIT(4) +#define BIT_RXDMA_MON_EN_8822C BIT(2) +#define BIT_RXPKT_MON_RST_8822C BIT(1) +#define BIT_RXPKT_MON_EN_8822C BIT(0) + +/* 2 REG_STATE_MON_8822C */ + +#define BIT_SHIFT_STATE_SEL_8822C 24 +#define BIT_MASK_STATE_SEL_8822C 0x1f +#define BIT_STATE_SEL_8822C(x) \ + (((x) & BIT_MASK_STATE_SEL_8822C) << BIT_SHIFT_STATE_SEL_8822C) +#define BITS_STATE_SEL_8822C \ + (BIT_MASK_STATE_SEL_8822C << BIT_SHIFT_STATE_SEL_8822C) +#define BIT_CLEAR_STATE_SEL_8822C(x) ((x) & (~BITS_STATE_SEL_8822C)) +#define BIT_GET_STATE_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_STATE_SEL_8822C) & BIT_MASK_STATE_SEL_8822C) +#define BIT_SET_STATE_SEL_8822C(x, v) \ + (BIT_CLEAR_STATE_SEL_8822C(x) | BIT_STATE_SEL_8822C(v)) + +#define BIT_SHIFT_STATE_INFO_8822C 8 +#define BIT_MASK_STATE_INFO_8822C 0xff +#define BIT_STATE_INFO_8822C(x) \ + (((x) & BIT_MASK_STATE_INFO_8822C) << BIT_SHIFT_STATE_INFO_8822C) +#define BITS_STATE_INFO_8822C \ + (BIT_MASK_STATE_INFO_8822C << BIT_SHIFT_STATE_INFO_8822C) +#define BIT_CLEAR_STATE_INFO_8822C(x) ((x) & (~BITS_STATE_INFO_8822C)) +#define BIT_GET_STATE_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_STATE_INFO_8822C) & BIT_MASK_STATE_INFO_8822C) +#define BIT_SET_STATE_INFO_8822C(x, v) \ + (BIT_CLEAR_STATE_INFO_8822C(x) | BIT_STATE_INFO_8822C(v)) + +#define BIT_UPD_NXT_STATE_8822C BIT(7) + +#define BIT_SHIFT_CUR_STATE_8822C 0 +#define BIT_MASK_CUR_STATE_8822C 0x7f +#define BIT_CUR_STATE_8822C(x) \ + (((x) & BIT_MASK_CUR_STATE_8822C) << BIT_SHIFT_CUR_STATE_8822C) +#define BITS_CUR_STATE_8822C \ + (BIT_MASK_CUR_STATE_8822C << BIT_SHIFT_CUR_STATE_8822C) +#define BIT_CLEAR_CUR_STATE_8822C(x) ((x) & (~BITS_CUR_STATE_8822C)) +#define BIT_GET_CUR_STATE_8822C(x) \ + (((x) >> BIT_SHIFT_CUR_STATE_8822C) & BIT_MASK_CUR_STATE_8822C) +#define BIT_SET_CUR_STATE_8822C(x, v) \ + (BIT_CLEAR_CUR_STATE_8822C(x) | BIT_CUR_STATE_8822C(v)) + +/* 2 REG_ERROR_MON_8822C */ +#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC_8822C BIT(23) +#define BIT_CSI_CHKSUM_ERROR_8822C BIT(22) +#define BIT_MACRX_ERR_4_8822C BIT(20) +#define BIT_MACRX_ERR_3_8822C BIT(19) +#define BIT_MACRX_ERR_2_8822C BIT(18) +#define BIT_MACRX_ERR_1_8822C BIT(17) +#define BIT_MACRX_ERR_0_8822C BIT(16) +#define BIT_WMAC_PRETX_ERRHDL_EN_8822C BIT(15) +#define BIT_MACTX_ERR_5_8822C BIT(5) +#define BIT_MACTX_ERR_4_8822C BIT(4) +#define BIT_MACTX_ERR_3_8822C BIT(3) +#define BIT_MACTX_ERR_2_8822C BIT(2) +#define BIT_MACTX_ERR_1_8822C BIT(1) +#define BIT_MACTX_ERR_0_8822C BIT(0) + +/* 2 REG_SEARCH_MACID_8822C */ +#define BIT_EN_TXRPTBUF_CLK_8822C BIT(31) + +#define BIT_SHIFT_INFO_INDEX_OFFSET_8822C 16 +#define BIT_MASK_INFO_INDEX_OFFSET_8822C 0x1fff +#define BIT_INFO_INDEX_OFFSET_8822C(x) \ + (((x) & BIT_MASK_INFO_INDEX_OFFSET_8822C) \ + << BIT_SHIFT_INFO_INDEX_OFFSET_8822C) +#define BITS_INFO_INDEX_OFFSET_8822C \ + (BIT_MASK_INFO_INDEX_OFFSET_8822C << BIT_SHIFT_INFO_INDEX_OFFSET_8822C) +#define BIT_CLEAR_INFO_INDEX_OFFSET_8822C(x) \ + ((x) & (~BITS_INFO_INDEX_OFFSET_8822C)) +#define BIT_GET_INFO_INDEX_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822C) & \ + BIT_MASK_INFO_INDEX_OFFSET_8822C) +#define BIT_SET_INFO_INDEX_OFFSET_8822C(x, v) \ + (BIT_CLEAR_INFO_INDEX_OFFSET_8822C(x) | BIT_INFO_INDEX_OFFSET_8822C(v)) + +#define BIT_WMAC_SRCH_FIFOFULL_8822C BIT(15) +#define BIT_DIS_INFOSRCH_8822C BIT(14) + +#define BIT_SHIFT_INFO_ADDR_OFFSET_8822C 0 +#define BIT_MASK_INFO_ADDR_OFFSET_8822C 0x1fff +#define BIT_INFO_ADDR_OFFSET_8822C(x) \ + (((x) & BIT_MASK_INFO_ADDR_OFFSET_8822C) \ + << BIT_SHIFT_INFO_ADDR_OFFSET_8822C) +#define BITS_INFO_ADDR_OFFSET_8822C \ + (BIT_MASK_INFO_ADDR_OFFSET_8822C << BIT_SHIFT_INFO_ADDR_OFFSET_8822C) +#define BIT_CLEAR_INFO_ADDR_OFFSET_8822C(x) \ + ((x) & (~BITS_INFO_ADDR_OFFSET_8822C)) +#define BIT_GET_INFO_ADDR_OFFSET_8822C(x) \ + (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822C) & \ + BIT_MASK_INFO_ADDR_OFFSET_8822C) +#define BIT_SET_INFO_ADDR_OFFSET_8822C(x, v) \ + (BIT_CLEAR_INFO_ADDR_OFFSET_8822C(x) | BIT_INFO_ADDR_OFFSET_8822C(v)) + +/* 2 REG_BT_COEX_TABLE_8822C (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_COEX_TABLE_1_8822C 0 +#define BIT_MASK_COEX_TABLE_1_8822C 0xffffffffL +#define BIT_COEX_TABLE_1_8822C(x) \ + (((x) & BIT_MASK_COEX_TABLE_1_8822C) << BIT_SHIFT_COEX_TABLE_1_8822C) +#define BITS_COEX_TABLE_1_8822C \ + (BIT_MASK_COEX_TABLE_1_8822C << BIT_SHIFT_COEX_TABLE_1_8822C) +#define BIT_CLEAR_COEX_TABLE_1_8822C(x) ((x) & (~BITS_COEX_TABLE_1_8822C)) +#define BIT_GET_COEX_TABLE_1_8822C(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_1_8822C) & BIT_MASK_COEX_TABLE_1_8822C) +#define BIT_SET_COEX_TABLE_1_8822C(x, v) \ + (BIT_CLEAR_COEX_TABLE_1_8822C(x) | BIT_COEX_TABLE_1_8822C(v)) + +/* 2 REG_BT_COEX_TABLE2_8822C (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_COEX_TABLE_2_8822C 0 +#define BIT_MASK_COEX_TABLE_2_8822C 0xffffffffL +#define BIT_COEX_TABLE_2_8822C(x) \ + (((x) & BIT_MASK_COEX_TABLE_2_8822C) << BIT_SHIFT_COEX_TABLE_2_8822C) +#define BITS_COEX_TABLE_2_8822C \ + (BIT_MASK_COEX_TABLE_2_8822C << BIT_SHIFT_COEX_TABLE_2_8822C) +#define BIT_CLEAR_COEX_TABLE_2_8822C(x) ((x) & (~BITS_COEX_TABLE_2_8822C)) +#define BIT_GET_COEX_TABLE_2_8822C(x) \ + (((x) >> BIT_SHIFT_COEX_TABLE_2_8822C) & BIT_MASK_COEX_TABLE_2_8822C) +#define BIT_SET_COEX_TABLE_2_8822C(x, v) \ + (BIT_CLEAR_COEX_TABLE_2_8822C(x) | BIT_COEX_TABLE_2_8822C(v)) + +/* 2 REG_BT_COEX_BREAK_TABLE_8822C (BT-COEXISTENCE CONTROL REGISTER) */ + +#define BIT_SHIFT_BREAK_TABLE_2_8822C 16 +#define BIT_MASK_BREAK_TABLE_2_8822C 0xffff +#define BIT_BREAK_TABLE_2_8822C(x) \ + (((x) & BIT_MASK_BREAK_TABLE_2_8822C) << BIT_SHIFT_BREAK_TABLE_2_8822C) +#define BITS_BREAK_TABLE_2_8822C \ + (BIT_MASK_BREAK_TABLE_2_8822C << BIT_SHIFT_BREAK_TABLE_2_8822C) +#define BIT_CLEAR_BREAK_TABLE_2_8822C(x) ((x) & (~BITS_BREAK_TABLE_2_8822C)) +#define BIT_GET_BREAK_TABLE_2_8822C(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_2_8822C) & BIT_MASK_BREAK_TABLE_2_8822C) +#define BIT_SET_BREAK_TABLE_2_8822C(x, v) \ + (BIT_CLEAR_BREAK_TABLE_2_8822C(x) | BIT_BREAK_TABLE_2_8822C(v)) + +#define BIT_SHIFT_BREAK_TABLE_1_8822C 0 +#define BIT_MASK_BREAK_TABLE_1_8822C 0xffff +#define BIT_BREAK_TABLE_1_8822C(x) \ + (((x) & BIT_MASK_BREAK_TABLE_1_8822C) << BIT_SHIFT_BREAK_TABLE_1_8822C) +#define BITS_BREAK_TABLE_1_8822C \ + (BIT_MASK_BREAK_TABLE_1_8822C << BIT_SHIFT_BREAK_TABLE_1_8822C) +#define BIT_CLEAR_BREAK_TABLE_1_8822C(x) ((x) & (~BITS_BREAK_TABLE_1_8822C)) +#define BIT_GET_BREAK_TABLE_1_8822C(x) \ + (((x) >> BIT_SHIFT_BREAK_TABLE_1_8822C) & BIT_MASK_BREAK_TABLE_1_8822C) +#define BIT_SET_BREAK_TABLE_1_8822C(x, v) \ + (BIT_CLEAR_BREAK_TABLE_1_8822C(x) | BIT_BREAK_TABLE_1_8822C(v)) + +/* 2 REG_BT_COEX_TABLE_H_8822C (BT-COEXISTENCE CONTROL REGISTER) */ +#define BIT_PRI_MASK_RX_RESP_V1_8822C BIT(30) +#define BIT_PRI_MASK_RXOFDM_V1_8822C BIT(29) +#define BIT_PRI_MASK_RXCCK_V1_8822C BIT(28) + +#define BIT_SHIFT_PRI_MASK_TXAC_8822C 21 +#define BIT_MASK_PRI_MASK_TXAC_8822C 0x7f +#define BIT_PRI_MASK_TXAC_8822C(x) \ + (((x) & BIT_MASK_PRI_MASK_TXAC_8822C) << BIT_SHIFT_PRI_MASK_TXAC_8822C) +#define BITS_PRI_MASK_TXAC_8822C \ + (BIT_MASK_PRI_MASK_TXAC_8822C << BIT_SHIFT_PRI_MASK_TXAC_8822C) +#define BIT_CLEAR_PRI_MASK_TXAC_8822C(x) ((x) & (~BITS_PRI_MASK_TXAC_8822C)) +#define BIT_GET_PRI_MASK_TXAC_8822C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822C) & BIT_MASK_PRI_MASK_TXAC_8822C) +#define BIT_SET_PRI_MASK_TXAC_8822C(x, v) \ + (BIT_CLEAR_PRI_MASK_TXAC_8822C(x) | BIT_PRI_MASK_TXAC_8822C(v)) + +#define BIT_SHIFT_PRI_MASK_NAV_8822C 13 +#define BIT_MASK_PRI_MASK_NAV_8822C 0xff +#define BIT_PRI_MASK_NAV_8822C(x) \ + (((x) & BIT_MASK_PRI_MASK_NAV_8822C) << BIT_SHIFT_PRI_MASK_NAV_8822C) +#define BITS_PRI_MASK_NAV_8822C \ + (BIT_MASK_PRI_MASK_NAV_8822C << BIT_SHIFT_PRI_MASK_NAV_8822C) +#define BIT_CLEAR_PRI_MASK_NAV_8822C(x) ((x) & (~BITS_PRI_MASK_NAV_8822C)) +#define BIT_GET_PRI_MASK_NAV_8822C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NAV_8822C) & BIT_MASK_PRI_MASK_NAV_8822C) +#define BIT_SET_PRI_MASK_NAV_8822C(x, v) \ + (BIT_CLEAR_PRI_MASK_NAV_8822C(x) | BIT_PRI_MASK_NAV_8822C(v)) + +#define BIT_PRI_MASK_CCK_V1_8822C BIT(12) +#define BIT_PRI_MASK_OFDM_V1_8822C BIT(11) +#define BIT_PRI_MASK_RTY_V1_8822C BIT(10) + +#define BIT_SHIFT_PRI_MASK_NUM_8822C 6 +#define BIT_MASK_PRI_MASK_NUM_8822C 0xf +#define BIT_PRI_MASK_NUM_8822C(x) \ + (((x) & BIT_MASK_PRI_MASK_NUM_8822C) << BIT_SHIFT_PRI_MASK_NUM_8822C) +#define BITS_PRI_MASK_NUM_8822C \ + (BIT_MASK_PRI_MASK_NUM_8822C << BIT_SHIFT_PRI_MASK_NUM_8822C) +#define BIT_CLEAR_PRI_MASK_NUM_8822C(x) ((x) & (~BITS_PRI_MASK_NUM_8822C)) +#define BIT_GET_PRI_MASK_NUM_8822C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_NUM_8822C) & BIT_MASK_PRI_MASK_NUM_8822C) +#define BIT_SET_PRI_MASK_NUM_8822C(x, v) \ + (BIT_CLEAR_PRI_MASK_NUM_8822C(x) | BIT_PRI_MASK_NUM_8822C(v)) + +#define BIT_SHIFT_PRI_MASK_TYPE_8822C 2 +#define BIT_MASK_PRI_MASK_TYPE_8822C 0xf +#define BIT_PRI_MASK_TYPE_8822C(x) \ + (((x) & BIT_MASK_PRI_MASK_TYPE_8822C) << BIT_SHIFT_PRI_MASK_TYPE_8822C) +#define BITS_PRI_MASK_TYPE_8822C \ + (BIT_MASK_PRI_MASK_TYPE_8822C << BIT_SHIFT_PRI_MASK_TYPE_8822C) +#define BIT_CLEAR_PRI_MASK_TYPE_8822C(x) ((x) & (~BITS_PRI_MASK_TYPE_8822C)) +#define BIT_GET_PRI_MASK_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822C) & BIT_MASK_PRI_MASK_TYPE_8822C) +#define BIT_SET_PRI_MASK_TYPE_8822C(x, v) \ + (BIT_CLEAR_PRI_MASK_TYPE_8822C(x) | BIT_PRI_MASK_TYPE_8822C(v)) + +#define BIT_OOB_V1_8822C BIT(1) +#define BIT_ANT_SEL_V1_8822C BIT(0) + +/* 2 REG_RXCMD_0_8822C */ +#define BIT_RXCMD_EN_8822C BIT(31) + +#define BIT_SHIFT_RXCMD_INFO_8822C 0 +#define BIT_MASK_RXCMD_INFO_8822C 0x7fffffffL +#define BIT_RXCMD_INFO_8822C(x) \ + (((x) & BIT_MASK_RXCMD_INFO_8822C) << BIT_SHIFT_RXCMD_INFO_8822C) +#define BITS_RXCMD_INFO_8822C \ + (BIT_MASK_RXCMD_INFO_8822C << BIT_SHIFT_RXCMD_INFO_8822C) +#define BIT_CLEAR_RXCMD_INFO_8822C(x) ((x) & (~BITS_RXCMD_INFO_8822C)) +#define BIT_GET_RXCMD_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_RXCMD_INFO_8822C) & BIT_MASK_RXCMD_INFO_8822C) +#define BIT_SET_RXCMD_INFO_8822C(x, v) \ + (BIT_CLEAR_RXCMD_INFO_8822C(x) | BIT_RXCMD_INFO_8822C(v)) + +/* 2 REG_RXCMD_1_8822C */ + +#define BIT_SHIFT_RXCMD_PRD_8822C 0 +#define BIT_MASK_RXCMD_PRD_8822C 0xffff +#define BIT_RXCMD_PRD_8822C(x) \ + (((x) & BIT_MASK_RXCMD_PRD_8822C) << BIT_SHIFT_RXCMD_PRD_8822C) +#define BITS_RXCMD_PRD_8822C \ + (BIT_MASK_RXCMD_PRD_8822C << BIT_SHIFT_RXCMD_PRD_8822C) +#define BIT_CLEAR_RXCMD_PRD_8822C(x) ((x) & (~BITS_RXCMD_PRD_8822C)) +#define BIT_GET_RXCMD_PRD_8822C(x) \ + (((x) >> BIT_SHIFT_RXCMD_PRD_8822C) & BIT_MASK_RXCMD_PRD_8822C) +#define BIT_SET_RXCMD_PRD_8822C(x, v) \ + (BIT_CLEAR_RXCMD_PRD_8822C(x) | BIT_RXCMD_PRD_8822C(v)) + +/* 2 REG_WMAC_RESP_TXINFO_8822C (RESPONSE TXINFO REGISTER) */ + +#define BIT_SHIFT_WMAC_RESP_MFB_8822C 25 +#define BIT_MASK_WMAC_RESP_MFB_8822C 0x7f +#define BIT_WMAC_RESP_MFB_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_MFB_8822C) << BIT_SHIFT_WMAC_RESP_MFB_8822C) +#define BITS_WMAC_RESP_MFB_8822C \ + (BIT_MASK_WMAC_RESP_MFB_8822C << BIT_SHIFT_WMAC_RESP_MFB_8822C) +#define BIT_CLEAR_WMAC_RESP_MFB_8822C(x) ((x) & (~BITS_WMAC_RESP_MFB_8822C)) +#define BIT_GET_WMAC_RESP_MFB_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822C) & BIT_MASK_WMAC_RESP_MFB_8822C) +#define BIT_SET_WMAC_RESP_MFB_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_MFB_8822C(x) | BIT_WMAC_RESP_MFB_8822C(v)) + +#define BIT_SHIFT_WMAC_ANTINF_SEL_8822C 23 +#define BIT_MASK_WMAC_ANTINF_SEL_8822C 0x3 +#define BIT_WMAC_ANTINF_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_ANTINF_SEL_8822C) \ + << BIT_SHIFT_WMAC_ANTINF_SEL_8822C) +#define BITS_WMAC_ANTINF_SEL_8822C \ + (BIT_MASK_WMAC_ANTINF_SEL_8822C << BIT_SHIFT_WMAC_ANTINF_SEL_8822C) +#define BIT_CLEAR_WMAC_ANTINF_SEL_8822C(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8822C)) +#define BIT_GET_WMAC_ANTINF_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822C) & \ + BIT_MASK_WMAC_ANTINF_SEL_8822C) +#define BIT_SET_WMAC_ANTINF_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_ANTINF_SEL_8822C(x) | BIT_WMAC_ANTINF_SEL_8822C(v)) + +#define BIT_SHIFT_WMAC_ANTSEL_SEL_8822C 21 +#define BIT_MASK_WMAC_ANTSEL_SEL_8822C 0x3 +#define BIT_WMAC_ANTSEL_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822C) \ + << BIT_SHIFT_WMAC_ANTSEL_SEL_8822C) +#define BITS_WMAC_ANTSEL_SEL_8822C \ + (BIT_MASK_WMAC_ANTSEL_SEL_8822C << BIT_SHIFT_WMAC_ANTSEL_SEL_8822C) +#define BIT_CLEAR_WMAC_ANTSEL_SEL_8822C(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8822C)) +#define BIT_GET_WMAC_ANTSEL_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822C) & \ + BIT_MASK_WMAC_ANTSEL_SEL_8822C) +#define BIT_SET_WMAC_ANTSEL_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_ANTSEL_SEL_8822C(x) | BIT_WMAC_ANTSEL_SEL_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C 18 +#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C 0x3 +#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) +#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C \ + (BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C \ + << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) +#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) \ + ((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)) +#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) & \ + BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) +#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) | \ + BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C 6 +#define BIT_MASK_WMAC_RESP_TXANT_V1_8822C 0xfff +#define BIT_WMAC_RESP_TXANT_V1_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXANT_V1_8822C) \ + << BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C) +#define BITS_WMAC_RESP_TXANT_V1_8822C \ + (BIT_MASK_WMAC_RESP_TXANT_V1_8822C \ + << BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C) +#define BIT_CLEAR_WMAC_RESP_TXANT_V1_8822C(x) \ + ((x) & (~BITS_WMAC_RESP_TXANT_V1_8822C)) +#define BIT_GET_WMAC_RESP_TXANT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C) & \ + BIT_MASK_WMAC_RESP_TXANT_V1_8822C) +#define BIT_SET_WMAC_RESP_TXANT_V1_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXANT_V1_8822C(x) | \ + BIT_WMAC_RESP_TXANT_V1_8822C(v)) + +/* 2 REG_BBPSF_CTRL_8822C */ +#define BIT_CTL_IDLE_CLR_CSI_RPT_8822C BIT(31) +#define BIT_WMAC_USE_NDPARATE_8822C BIT(30) + +#define BIT_SHIFT_WMAC_CSI_RATE_8822C 24 +#define BIT_MASK_WMAC_CSI_RATE_8822C 0x3f +#define BIT_WMAC_CSI_RATE_8822C(x) \ + (((x) & BIT_MASK_WMAC_CSI_RATE_8822C) << BIT_SHIFT_WMAC_CSI_RATE_8822C) +#define BITS_WMAC_CSI_RATE_8822C \ + (BIT_MASK_WMAC_CSI_RATE_8822C << BIT_SHIFT_WMAC_CSI_RATE_8822C) +#define BIT_CLEAR_WMAC_CSI_RATE_8822C(x) ((x) & (~BITS_WMAC_CSI_RATE_8822C)) +#define BIT_GET_WMAC_CSI_RATE_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822C) & BIT_MASK_WMAC_CSI_RATE_8822C) +#define BIT_SET_WMAC_CSI_RATE_8822C(x, v) \ + (BIT_CLEAR_WMAC_CSI_RATE_8822C(x) | BIT_WMAC_CSI_RATE_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_TXRATE_8822C 16 +#define BIT_MASK_WMAC_RESP_TXRATE_8822C 0xff +#define BIT_WMAC_RESP_TXRATE_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_TXRATE_8822C) \ + << BIT_SHIFT_WMAC_RESP_TXRATE_8822C) +#define BITS_WMAC_RESP_TXRATE_8822C \ + (BIT_MASK_WMAC_RESP_TXRATE_8822C << BIT_SHIFT_WMAC_RESP_TXRATE_8822C) +#define BIT_CLEAR_WMAC_RESP_TXRATE_8822C(x) \ + ((x) & (~BITS_WMAC_RESP_TXRATE_8822C)) +#define BIT_GET_WMAC_RESP_TXRATE_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822C) & \ + BIT_MASK_WMAC_RESP_TXRATE_8822C) +#define BIT_SET_WMAC_RESP_TXRATE_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_TXRATE_8822C(x) | BIT_WMAC_RESP_TXRATE_8822C(v)) + +#define BIT_SHIFT_CSI_RSC_8822C 13 +#define BIT_MASK_CSI_RSC_8822C 0x3 +#define BIT_CSI_RSC_8822C(x) \ + (((x) & BIT_MASK_CSI_RSC_8822C) << BIT_SHIFT_CSI_RSC_8822C) +#define BITS_CSI_RSC_8822C (BIT_MASK_CSI_RSC_8822C << BIT_SHIFT_CSI_RSC_8822C) +#define BIT_CLEAR_CSI_RSC_8822C(x) ((x) & (~BITS_CSI_RSC_8822C)) +#define BIT_GET_CSI_RSC_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_RSC_8822C) & BIT_MASK_CSI_RSC_8822C) +#define BIT_SET_CSI_RSC_8822C(x, v) \ + (BIT_CLEAR_CSI_RSC_8822C(x) | BIT_CSI_RSC_8822C(v)) + +#define BIT_CSI_GID_SEL_8822C BIT(12) +#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8822C BIT(9) +#define BIT_RDCSI_EMPTY_APPZERO_8822C BIT(8) +#define BIT_CSI_RATE_FB_EN_8822C BIT(7) +#define BIT_RXFIFO_WRPTR_WO_CHKSUM_8822C BIT(6) + +/* 2 REG_P2P_RX_BCN_NOA_8822C (P2P RX BEACON NOA REGISTER) */ +#define BIT_NOA_PARSER_EN_8822C BIT(15) + +#define BIT_SHIFT_BSSID_SEL_V1_8822C 12 +#define BIT_MASK_BSSID_SEL_V1_8822C 0x7 +#define BIT_BSSID_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID_SEL_V1_8822C) << BIT_SHIFT_BSSID_SEL_V1_8822C) +#define BITS_BSSID_SEL_V1_8822C \ + (BIT_MASK_BSSID_SEL_V1_8822C << BIT_SHIFT_BSSID_SEL_V1_8822C) +#define BIT_CLEAR_BSSID_SEL_V1_8822C(x) ((x) & (~BITS_BSSID_SEL_V1_8822C)) +#define BIT_GET_BSSID_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID_SEL_V1_8822C) & BIT_MASK_BSSID_SEL_V1_8822C) +#define BIT_SET_BSSID_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID_SEL_V1_8822C(x) | BIT_BSSID_SEL_V1_8822C(v)) + +#define BIT_SHIFT_P2P_OUI_TYPE_8822C 0 +#define BIT_MASK_P2P_OUI_TYPE_8822C 0xff +#define BIT_P2P_OUI_TYPE_8822C(x) \ + (((x) & BIT_MASK_P2P_OUI_TYPE_8822C) << BIT_SHIFT_P2P_OUI_TYPE_8822C) +#define BITS_P2P_OUI_TYPE_8822C \ + (BIT_MASK_P2P_OUI_TYPE_8822C << BIT_SHIFT_P2P_OUI_TYPE_8822C) +#define BIT_CLEAR_P2P_OUI_TYPE_8822C(x) ((x) & (~BITS_P2P_OUI_TYPE_8822C)) +#define BIT_GET_P2P_OUI_TYPE_8822C(x) \ + (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822C) & BIT_MASK_P2P_OUI_TYPE_8822C) +#define BIT_SET_P2P_OUI_TYPE_8822C(x, v) \ + (BIT_CLEAR_P2P_OUI_TYPE_8822C(x) | BIT_P2P_OUI_TYPE_8822C(v)) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_ASSOCIATED_BFMER0_INFO_8822C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8822C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(v)) + +/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8822C */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C 16 +#define BIT_MASK_R_WMAC_TXCSI_AID0_8822C 0x1ff +#define BIT_R_WMAC_TXCSI_AID0_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822C) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C) +#define BITS_R_WMAC_TXCSI_AID0_8822C \ + (BIT_MASK_R_WMAC_TXCSI_AID0_8822C << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C) +#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8822C(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID0_8822C)) +#define BIT_GET_R_WMAC_TXCSI_AID0_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C) & \ + BIT_MASK_R_WMAC_TXCSI_AID0_8822C) +#define BIT_SET_R_WMAC_TXCSI_AID0_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID0_8822C(x) | BIT_R_WMAC_TXCSI_AID0_8822C(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) +#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(v)) + +/* 2 REG_ASSOCIATED_BFMER1_INFO_8822C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C 0xffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8822C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(v)) + +/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8822C */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C 16 +#define BIT_MASK_R_WMAC_TXCSI_AID1_8822C 0x1ff +#define BIT_R_WMAC_TXCSI_AID1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822C) \ + << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C) +#define BITS_R_WMAC_TXCSI_AID1_8822C \ + (BIT_MASK_R_WMAC_TXCSI_AID1_8822C << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C) +#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8822C(x) \ + ((x) & (~BITS_R_WMAC_TXCSI_AID1_8822C)) +#define BIT_GET_R_WMAC_TXCSI_AID1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C) & \ + BIT_MASK_R_WMAC_TXCSI_AID1_8822C) +#define BIT_SET_R_WMAC_TXCSI_AID1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_TXCSI_AID1_8822C(x) | BIT_R_WMAC_TXCSI_AID1_8822C(v)) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C 0xffff +#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) +#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C \ + (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C \ + << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) +#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) \ + ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) & \ + BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) +#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) | \ + BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(v)) + +/* 2 REG_TX_CSI_RPT_PARAM_BW20_8822C (TX CSI REPORT PARAMETER REGISTER) */ + +#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C 16 +#define BIT_MASK_R_WMAC_BFINFO_20M_1_8822C 0xfff +#define BIT_R_WMAC_BFINFO_20M_1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822C) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C) +#define BITS_R_WMAC_BFINFO_20M_1_8822C \ + (BIT_MASK_R_WMAC_BFINFO_20M_1_8822C \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822C(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8822C)) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C) & \ + BIT_MASK_R_WMAC_BFINFO_20M_1_8822C) +#define BIT_SET_R_WMAC_BFINFO_20M_1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822C(x) | \ + BIT_R_WMAC_BFINFO_20M_1_8822C(v)) + +#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C 0 +#define BIT_MASK_R_WMAC_BFINFO_20M_0_8822C 0xfff +#define BIT_R_WMAC_BFINFO_20M_0_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822C) \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C) +#define BITS_R_WMAC_BFINFO_20M_0_8822C \ + (BIT_MASK_R_WMAC_BFINFO_20M_0_8822C \ + << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C) +#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822C(x) \ + ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8822C)) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C) & \ + BIT_MASK_R_WMAC_BFINFO_20M_0_8822C) +#define BIT_SET_R_WMAC_BFINFO_20M_0_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822C(x) | \ + BIT_R_WMAC_BFINFO_20M_0_8822C(v)) + +/* 2 REG_TX_CSI_RPT_PARAM_BW40_8822C (TX CSI REPORT PARAMETER_BW40 REGISTER) */ + +#define BIT_SHIFT_WMAC_RESP_ANTD_8822C 12 +#define BIT_MASK_WMAC_RESP_ANTD_8822C 0xf +#define BIT_WMAC_RESP_ANTD_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTD_8822C) \ + << BIT_SHIFT_WMAC_RESP_ANTD_8822C) +#define BITS_WMAC_RESP_ANTD_8822C \ + (BIT_MASK_WMAC_RESP_ANTD_8822C << BIT_SHIFT_WMAC_RESP_ANTD_8822C) +#define BIT_CLEAR_WMAC_RESP_ANTD_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTD_8822C)) +#define BIT_GET_WMAC_RESP_ANTD_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTD_8822C) & \ + BIT_MASK_WMAC_RESP_ANTD_8822C) +#define BIT_SET_WMAC_RESP_ANTD_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTD_8822C(x) | BIT_WMAC_RESP_ANTD_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTC_8822C 8 +#define BIT_MASK_WMAC_RESP_ANTC_8822C 0xf +#define BIT_WMAC_RESP_ANTC_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTC_8822C) \ + << BIT_SHIFT_WMAC_RESP_ANTC_8822C) +#define BITS_WMAC_RESP_ANTC_8822C \ + (BIT_MASK_WMAC_RESP_ANTC_8822C << BIT_SHIFT_WMAC_RESP_ANTC_8822C) +#define BIT_CLEAR_WMAC_RESP_ANTC_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTC_8822C)) +#define BIT_GET_WMAC_RESP_ANTC_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTC_8822C) & \ + BIT_MASK_WMAC_RESP_ANTC_8822C) +#define BIT_SET_WMAC_RESP_ANTC_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTC_8822C(x) | BIT_WMAC_RESP_ANTC_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTB_8822C 4 +#define BIT_MASK_WMAC_RESP_ANTB_8822C 0xf +#define BIT_WMAC_RESP_ANTB_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTB_8822C) \ + << BIT_SHIFT_WMAC_RESP_ANTB_8822C) +#define BITS_WMAC_RESP_ANTB_8822C \ + (BIT_MASK_WMAC_RESP_ANTB_8822C << BIT_SHIFT_WMAC_RESP_ANTB_8822C) +#define BIT_CLEAR_WMAC_RESP_ANTB_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTB_8822C)) +#define BIT_GET_WMAC_RESP_ANTB_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTB_8822C) & \ + BIT_MASK_WMAC_RESP_ANTB_8822C) +#define BIT_SET_WMAC_RESP_ANTB_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTB_8822C(x) | BIT_WMAC_RESP_ANTB_8822C(v)) + +#define BIT_SHIFT_WMAC_RESP_ANTA_8822C 0 +#define BIT_MASK_WMAC_RESP_ANTA_8822C 0xf +#define BIT_WMAC_RESP_ANTA_8822C(x) \ + (((x) & BIT_MASK_WMAC_RESP_ANTA_8822C) \ + << BIT_SHIFT_WMAC_RESP_ANTA_8822C) +#define BITS_WMAC_RESP_ANTA_8822C \ + (BIT_MASK_WMAC_RESP_ANTA_8822C << BIT_SHIFT_WMAC_RESP_ANTA_8822C) +#define BIT_CLEAR_WMAC_RESP_ANTA_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTA_8822C)) +#define BIT_GET_WMAC_RESP_ANTA_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RESP_ANTA_8822C) & \ + BIT_MASK_WMAC_RESP_ANTA_8822C) +#define BIT_SET_WMAC_RESP_ANTA_8822C(x, v) \ + (BIT_CLEAR_WMAC_RESP_ANTA_8822C(x) | BIT_WMAC_RESP_ANTA_8822C(v)) + +/* 2 REG_CSI_PTR_8822C */ + +#define BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C 16 +#define BIT_MASK_CSI_RADDR_LATCH_V2_8822C 0xffff +#define BIT_CSI_RADDR_LATCH_V2_8822C(x) \ + (((x) & BIT_MASK_CSI_RADDR_LATCH_V2_8822C) \ + << BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C) +#define BITS_CSI_RADDR_LATCH_V2_8822C \ + (BIT_MASK_CSI_RADDR_LATCH_V2_8822C \ + << BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C) +#define BIT_CLEAR_CSI_RADDR_LATCH_V2_8822C(x) \ + ((x) & (~BITS_CSI_RADDR_LATCH_V2_8822C)) +#define BIT_GET_CSI_RADDR_LATCH_V2_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C) & \ + BIT_MASK_CSI_RADDR_LATCH_V2_8822C) +#define BIT_SET_CSI_RADDR_LATCH_V2_8822C(x, v) \ + (BIT_CLEAR_CSI_RADDR_LATCH_V2_8822C(x) | \ + BIT_CSI_RADDR_LATCH_V2_8822C(v)) + +#define BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C 0 +#define BIT_MASK_CSI_WADDR_LATCH_V2_8822C 0xffff +#define BIT_CSI_WADDR_LATCH_V2_8822C(x) \ + (((x) & BIT_MASK_CSI_WADDR_LATCH_V2_8822C) \ + << BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C) +#define BITS_CSI_WADDR_LATCH_V2_8822C \ + (BIT_MASK_CSI_WADDR_LATCH_V2_8822C \ + << BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C) +#define BIT_CLEAR_CSI_WADDR_LATCH_V2_8822C(x) \ + ((x) & (~BITS_CSI_WADDR_LATCH_V2_8822C)) +#define BIT_GET_CSI_WADDR_LATCH_V2_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C) & \ + BIT_MASK_CSI_WADDR_LATCH_V2_8822C) +#define BIT_SET_CSI_WADDR_LATCH_V2_8822C(x, v) \ + (BIT_CLEAR_CSI_WADDR_LATCH_V2_8822C(x) | \ + BIT_CSI_WADDR_LATCH_V2_8822C(v)) + +/* 2 REG_BCN_PSR_RPT2_8822C (BEACON PARSER REPORT REGISTER2) */ + +#define BIT_SHIFT_DTIM_CNT2_8822C 24 +#define BIT_MASK_DTIM_CNT2_8822C 0xff +#define BIT_DTIM_CNT2_8822C(x) \ + (((x) & BIT_MASK_DTIM_CNT2_8822C) << BIT_SHIFT_DTIM_CNT2_8822C) +#define BITS_DTIM_CNT2_8822C \ + (BIT_MASK_DTIM_CNT2_8822C << BIT_SHIFT_DTIM_CNT2_8822C) +#define BIT_CLEAR_DTIM_CNT2_8822C(x) ((x) & (~BITS_DTIM_CNT2_8822C)) +#define BIT_GET_DTIM_CNT2_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT2_8822C) & BIT_MASK_DTIM_CNT2_8822C) +#define BIT_SET_DTIM_CNT2_8822C(x, v) \ + (BIT_CLEAR_DTIM_CNT2_8822C(x) | BIT_DTIM_CNT2_8822C(v)) + +#define BIT_SHIFT_DTIM_PERIOD2_8822C 16 +#define BIT_MASK_DTIM_PERIOD2_8822C 0xff +#define BIT_DTIM_PERIOD2_8822C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD2_8822C) << BIT_SHIFT_DTIM_PERIOD2_8822C) +#define BITS_DTIM_PERIOD2_8822C \ + (BIT_MASK_DTIM_PERIOD2_8822C << BIT_SHIFT_DTIM_PERIOD2_8822C) +#define BIT_CLEAR_DTIM_PERIOD2_8822C(x) ((x) & (~BITS_DTIM_PERIOD2_8822C)) +#define BIT_GET_DTIM_PERIOD2_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD2_8822C) & BIT_MASK_DTIM_PERIOD2_8822C) +#define BIT_SET_DTIM_PERIOD2_8822C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD2_8822C(x) | BIT_DTIM_PERIOD2_8822C(v)) + +#define BIT_DTIM2_8822C BIT(15) +#define BIT_TIM2_8822C BIT(14) +#define BIT_RPT_VALID_8822C BIT(13) + +#define BIT_SHIFT_PS_AID_2_8822C 0 +#define BIT_MASK_PS_AID_2_8822C 0x7ff +#define BIT_PS_AID_2_8822C(x) \ + (((x) & BIT_MASK_PS_AID_2_8822C) << BIT_SHIFT_PS_AID_2_8822C) +#define BITS_PS_AID_2_8822C \ + (BIT_MASK_PS_AID_2_8822C << BIT_SHIFT_PS_AID_2_8822C) +#define BIT_CLEAR_PS_AID_2_8822C(x) ((x) & (~BITS_PS_AID_2_8822C)) +#define BIT_GET_PS_AID_2_8822C(x) \ + (((x) >> BIT_SHIFT_PS_AID_2_8822C) & BIT_MASK_PS_AID_2_8822C) +#define BIT_SET_PS_AID_2_8822C(x, v) \ + (BIT_CLEAR_PS_AID_2_8822C(x) | BIT_PS_AID_2_8822C(v)) + +/* 2 REG_BCN_PSR_RPT3_8822C (BEACON PARSER REPORT REGISTER3) */ + +#define BIT_SHIFT_DTIM_CNT3_8822C 24 +#define BIT_MASK_DTIM_CNT3_8822C 0xff +#define BIT_DTIM_CNT3_8822C(x) \ + (((x) & BIT_MASK_DTIM_CNT3_8822C) << BIT_SHIFT_DTIM_CNT3_8822C) +#define BITS_DTIM_CNT3_8822C \ + (BIT_MASK_DTIM_CNT3_8822C << BIT_SHIFT_DTIM_CNT3_8822C) +#define BIT_CLEAR_DTIM_CNT3_8822C(x) ((x) & (~BITS_DTIM_CNT3_8822C)) +#define BIT_GET_DTIM_CNT3_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT3_8822C) & BIT_MASK_DTIM_CNT3_8822C) +#define BIT_SET_DTIM_CNT3_8822C(x, v) \ + (BIT_CLEAR_DTIM_CNT3_8822C(x) | BIT_DTIM_CNT3_8822C(v)) + +#define BIT_SHIFT_DTIM_PERIOD3_8822C 16 +#define BIT_MASK_DTIM_PERIOD3_8822C 0xff +#define BIT_DTIM_PERIOD3_8822C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD3_8822C) << BIT_SHIFT_DTIM_PERIOD3_8822C) +#define BITS_DTIM_PERIOD3_8822C \ + (BIT_MASK_DTIM_PERIOD3_8822C << BIT_SHIFT_DTIM_PERIOD3_8822C) +#define BIT_CLEAR_DTIM_PERIOD3_8822C(x) ((x) & (~BITS_DTIM_PERIOD3_8822C)) +#define BIT_GET_DTIM_PERIOD3_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD3_8822C) & BIT_MASK_DTIM_PERIOD3_8822C) +#define BIT_SET_DTIM_PERIOD3_8822C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD3_8822C(x) | BIT_DTIM_PERIOD3_8822C(v)) + +#define BIT_DTIM3_8822C BIT(15) +#define BIT_TIM3_8822C BIT(14) +#define BIT_RPT_VALID_8822C BIT(13) + +#define BIT_SHIFT_PS_AID_3_8822C 0 +#define BIT_MASK_PS_AID_3_8822C 0x7ff +#define BIT_PS_AID_3_8822C(x) \ + (((x) & BIT_MASK_PS_AID_3_8822C) << BIT_SHIFT_PS_AID_3_8822C) +#define BITS_PS_AID_3_8822C \ + (BIT_MASK_PS_AID_3_8822C << BIT_SHIFT_PS_AID_3_8822C) +#define BIT_CLEAR_PS_AID_3_8822C(x) ((x) & (~BITS_PS_AID_3_8822C)) +#define BIT_GET_PS_AID_3_8822C(x) \ + (((x) >> BIT_SHIFT_PS_AID_3_8822C) & BIT_MASK_PS_AID_3_8822C) +#define BIT_SET_PS_AID_3_8822C(x, v) \ + (BIT_CLEAR_PS_AID_3_8822C(x) | BIT_PS_AID_3_8822C(v)) + +/* 2 REG_BCN_PSR_RPT4_8822C (BEACON PARSER REPORT REGISTER4) */ + +#define BIT_SHIFT_DTIM_CNT4_8822C 24 +#define BIT_MASK_DTIM_CNT4_8822C 0xff +#define BIT_DTIM_CNT4_8822C(x) \ + (((x) & BIT_MASK_DTIM_CNT4_8822C) << BIT_SHIFT_DTIM_CNT4_8822C) +#define BITS_DTIM_CNT4_8822C \ + (BIT_MASK_DTIM_CNT4_8822C << BIT_SHIFT_DTIM_CNT4_8822C) +#define BIT_CLEAR_DTIM_CNT4_8822C(x) ((x) & (~BITS_DTIM_CNT4_8822C)) +#define BIT_GET_DTIM_CNT4_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT4_8822C) & BIT_MASK_DTIM_CNT4_8822C) +#define BIT_SET_DTIM_CNT4_8822C(x, v) \ + (BIT_CLEAR_DTIM_CNT4_8822C(x) | BIT_DTIM_CNT4_8822C(v)) + +#define BIT_SHIFT_DTIM_PERIOD4_8822C 16 +#define BIT_MASK_DTIM_PERIOD4_8822C 0xff +#define BIT_DTIM_PERIOD4_8822C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD4_8822C) << BIT_SHIFT_DTIM_PERIOD4_8822C) +#define BITS_DTIM_PERIOD4_8822C \ + (BIT_MASK_DTIM_PERIOD4_8822C << BIT_SHIFT_DTIM_PERIOD4_8822C) +#define BIT_CLEAR_DTIM_PERIOD4_8822C(x) ((x) & (~BITS_DTIM_PERIOD4_8822C)) +#define BIT_GET_DTIM_PERIOD4_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD4_8822C) & BIT_MASK_DTIM_PERIOD4_8822C) +#define BIT_SET_DTIM_PERIOD4_8822C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD4_8822C(x) | BIT_DTIM_PERIOD4_8822C(v)) + +#define BIT_DTIM4_8822C BIT(15) +#define BIT_TIM4_8822C BIT(14) +#define BIT_RPT_VALID_8822C BIT(13) + +#define BIT_SHIFT_PS_AID_4_8822C 0 +#define BIT_MASK_PS_AID_4_8822C 0x7ff +#define BIT_PS_AID_4_8822C(x) \ + (((x) & BIT_MASK_PS_AID_4_8822C) << BIT_SHIFT_PS_AID_4_8822C) +#define BITS_PS_AID_4_8822C \ + (BIT_MASK_PS_AID_4_8822C << BIT_SHIFT_PS_AID_4_8822C) +#define BIT_CLEAR_PS_AID_4_8822C(x) ((x) & (~BITS_PS_AID_4_8822C)) +#define BIT_GET_PS_AID_4_8822C(x) \ + (((x) >> BIT_SHIFT_PS_AID_4_8822C) & BIT_MASK_PS_AID_4_8822C) +#define BIT_SET_PS_AID_4_8822C(x, v) \ + (BIT_CLEAR_PS_AID_4_8822C(x) | BIT_PS_AID_4_8822C(v)) + +/* 2 REG_A1_ADDR_MASK_8822C (A1 ADDR MASK REGISTER) */ + +#define BIT_SHIFT_A1_ADDR_MASK_8822C 0 +#define BIT_MASK_A1_ADDR_MASK_8822C 0xffffffffL +#define BIT_A1_ADDR_MASK_8822C(x) \ + (((x) & BIT_MASK_A1_ADDR_MASK_8822C) << BIT_SHIFT_A1_ADDR_MASK_8822C) +#define BITS_A1_ADDR_MASK_8822C \ + (BIT_MASK_A1_ADDR_MASK_8822C << BIT_SHIFT_A1_ADDR_MASK_8822C) +#define BIT_CLEAR_A1_ADDR_MASK_8822C(x) ((x) & (~BITS_A1_ADDR_MASK_8822C)) +#define BIT_GET_A1_ADDR_MASK_8822C(x) \ + (((x) >> BIT_SHIFT_A1_ADDR_MASK_8822C) & BIT_MASK_A1_ADDR_MASK_8822C) +#define BIT_SET_A1_ADDR_MASK_8822C(x, v) \ + (BIT_CLEAR_A1_ADDR_MASK_8822C(x) | BIT_A1_ADDR_MASK_8822C(v)) + +/* 2 REG_RXPSF_CTRL_8822C */ +#define BIT_RXGCK_FIFOTHR_EN_8822C BIT(28) + +#define BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C 26 +#define BIT_MASK_RXGCK_VHT_FIFOTHR_8822C 0x3 +#define BIT_RXGCK_VHT_FIFOTHR_8822C(x) \ + (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR_8822C) \ + << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C) +#define BITS_RXGCK_VHT_FIFOTHR_8822C \ + (BIT_MASK_RXGCK_VHT_FIFOTHR_8822C << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C) +#define BIT_CLEAR_RXGCK_VHT_FIFOTHR_8822C(x) \ + ((x) & (~BITS_RXGCK_VHT_FIFOTHR_8822C)) +#define BIT_GET_RXGCK_VHT_FIFOTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C) & \ + BIT_MASK_RXGCK_VHT_FIFOTHR_8822C) +#define BIT_SET_RXGCK_VHT_FIFOTHR_8822C(x, v) \ + (BIT_CLEAR_RXGCK_VHT_FIFOTHR_8822C(x) | BIT_RXGCK_VHT_FIFOTHR_8822C(v)) + +#define BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C 24 +#define BIT_MASK_RXGCK_HT_FIFOTHR_8822C 0x3 +#define BIT_RXGCK_HT_FIFOTHR_8822C(x) \ + (((x) & BIT_MASK_RXGCK_HT_FIFOTHR_8822C) \ + << BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C) +#define BITS_RXGCK_HT_FIFOTHR_8822C \ + (BIT_MASK_RXGCK_HT_FIFOTHR_8822C << BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C) +#define BIT_CLEAR_RXGCK_HT_FIFOTHR_8822C(x) \ + ((x) & (~BITS_RXGCK_HT_FIFOTHR_8822C)) +#define BIT_GET_RXGCK_HT_FIFOTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C) & \ + BIT_MASK_RXGCK_HT_FIFOTHR_8822C) +#define BIT_SET_RXGCK_HT_FIFOTHR_8822C(x, v) \ + (BIT_CLEAR_RXGCK_HT_FIFOTHR_8822C(x) | BIT_RXGCK_HT_FIFOTHR_8822C(v)) + +#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C 22 +#define BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C 0x3 +#define BIT_RXGCK_OFDM_FIFOTHR_8822C(x) \ + (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C) \ + << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C) +#define BITS_RXGCK_OFDM_FIFOTHR_8822C \ + (BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C \ + << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C) +#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8822C(x) \ + ((x) & (~BITS_RXGCK_OFDM_FIFOTHR_8822C)) +#define BIT_GET_RXGCK_OFDM_FIFOTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C) & \ + BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C) +#define BIT_SET_RXGCK_OFDM_FIFOTHR_8822C(x, v) \ + (BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8822C(x) | \ + BIT_RXGCK_OFDM_FIFOTHR_8822C(v)) + +#define BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C 20 +#define BIT_MASK_RXGCK_CCK_FIFOTHR_8822C 0x3 +#define BIT_RXGCK_CCK_FIFOTHR_8822C(x) \ + (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR_8822C) \ + << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C) +#define BITS_RXGCK_CCK_FIFOTHR_8822C \ + (BIT_MASK_RXGCK_CCK_FIFOTHR_8822C << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C) +#define BIT_CLEAR_RXGCK_CCK_FIFOTHR_8822C(x) \ + ((x) & (~BITS_RXGCK_CCK_FIFOTHR_8822C)) +#define BIT_GET_RXGCK_CCK_FIFOTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C) & \ + BIT_MASK_RXGCK_CCK_FIFOTHR_8822C) +#define BIT_SET_RXGCK_CCK_FIFOTHR_8822C(x, v) \ + (BIT_CLEAR_RXGCK_CCK_FIFOTHR_8822C(x) | BIT_RXGCK_CCK_FIFOTHR_8822C(v)) + +#define BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C 17 +#define BIT_MASK_RXGCK_ENTRY_DELAY_8822C 0x7 +#define BIT_RXGCK_ENTRY_DELAY_8822C(x) \ + (((x) & BIT_MASK_RXGCK_ENTRY_DELAY_8822C) \ + << BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C) +#define BITS_RXGCK_ENTRY_DELAY_8822C \ + (BIT_MASK_RXGCK_ENTRY_DELAY_8822C << BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C) +#define BIT_CLEAR_RXGCK_ENTRY_DELAY_8822C(x) \ + ((x) & (~BITS_RXGCK_ENTRY_DELAY_8822C)) +#define BIT_GET_RXGCK_ENTRY_DELAY_8822C(x) \ + (((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C) & \ + BIT_MASK_RXGCK_ENTRY_DELAY_8822C) +#define BIT_SET_RXGCK_ENTRY_DELAY_8822C(x, v) \ + (BIT_CLEAR_RXGCK_ENTRY_DELAY_8822C(x) | BIT_RXGCK_ENTRY_DELAY_8822C(v)) + +#define BIT_RXGCK_OFDMCCA_EN_8822C BIT(16) + +#define BIT_SHIFT_RXPSF_PKTLENTHR_8822C 13 +#define BIT_MASK_RXPSF_PKTLENTHR_8822C 0x7 +#define BIT_RXPSF_PKTLENTHR_8822C(x) \ + (((x) & BIT_MASK_RXPSF_PKTLENTHR_8822C) \ + << BIT_SHIFT_RXPSF_PKTLENTHR_8822C) +#define BITS_RXPSF_PKTLENTHR_8822C \ + (BIT_MASK_RXPSF_PKTLENTHR_8822C << BIT_SHIFT_RXPSF_PKTLENTHR_8822C) +#define BIT_CLEAR_RXPSF_PKTLENTHR_8822C(x) ((x) & (~BITS_RXPSF_PKTLENTHR_8822C)) +#define BIT_GET_RXPSF_PKTLENTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXPSF_PKTLENTHR_8822C) & \ + BIT_MASK_RXPSF_PKTLENTHR_8822C) +#define BIT_SET_RXPSF_PKTLENTHR_8822C(x, v) \ + (BIT_CLEAR_RXPSF_PKTLENTHR_8822C(x) | BIT_RXPSF_PKTLENTHR_8822C(v)) + +#define BIT_RXPSF_CTRLEN_8822C BIT(12) +#define BIT_RXPSF_VHTCHKEN_8822C BIT(11) +#define BIT_RXPSF_HTCHKEN_8822C BIT(10) +#define BIT_RXPSF_OFDMCHKEN_8822C BIT(9) +#define BIT_RXPSF_CCKCHKEN_8822C BIT(8) +#define BIT_RXPSF_OFDMRST_8822C BIT(7) +#define BIT_RXPSF_CCKRST_8822C BIT(6) +#define BIT_RXPSF_MHCHKEN_8822C BIT(5) +#define BIT_RXPSF_CONT_ERRCHKEN_8822C BIT(4) +#define BIT_RXPSF_ALL_ERRCHKEN_8822C BIT(3) + +#define BIT_SHIFT_RXPSF_ERRTHR_8822C 0 +#define BIT_MASK_RXPSF_ERRTHR_8822C 0x7 +#define BIT_RXPSF_ERRTHR_8822C(x) \ + (((x) & BIT_MASK_RXPSF_ERRTHR_8822C) << BIT_SHIFT_RXPSF_ERRTHR_8822C) +#define BITS_RXPSF_ERRTHR_8822C \ + (BIT_MASK_RXPSF_ERRTHR_8822C << BIT_SHIFT_RXPSF_ERRTHR_8822C) +#define BIT_CLEAR_RXPSF_ERRTHR_8822C(x) ((x) & (~BITS_RXPSF_ERRTHR_8822C)) +#define BIT_GET_RXPSF_ERRTHR_8822C(x) \ + (((x) >> BIT_SHIFT_RXPSF_ERRTHR_8822C) & BIT_MASK_RXPSF_ERRTHR_8822C) +#define BIT_SET_RXPSF_ERRTHR_8822C(x, v) \ + (BIT_CLEAR_RXPSF_ERRTHR_8822C(x) | BIT_RXPSF_ERRTHR_8822C(v)) + +/* 2 REG_RXPSF_TYPE_CTRL_8822C */ +#define BIT_RXPSF_DATA15EN_8822C BIT(31) +#define BIT_RXPSF_DATA14EN_8822C BIT(30) +#define BIT_RXPSF_DATA13EN_8822C BIT(29) +#define BIT_RXPSF_DATA12EN_8822C BIT(28) +#define BIT_RXPSF_DATA11EN_8822C BIT(27) +#define BIT_RXPSF_DATA10EN_8822C BIT(26) +#define BIT_RXPSF_DATA9EN_8822C BIT(25) +#define BIT_RXPSF_DATA8EN_8822C BIT(24) +#define BIT_RXPSF_DATA7EN_8822C BIT(23) +#define BIT_RXPSF_DATA6EN_8822C BIT(22) +#define BIT_RXPSF_DATA5EN_8822C BIT(21) +#define BIT_RXPSF_DATA4EN_8822C BIT(20) +#define BIT_RXPSF_DATA3EN_8822C BIT(19) +#define BIT_RXPSF_DATA2EN_8822C BIT(18) +#define BIT_RXPSF_DATA1EN_8822C BIT(17) +#define BIT_RXPSF_DATA0EN_8822C BIT(16) +#define BIT_RXPSF_MGT15EN_8822C BIT(15) +#define BIT_RXPSF_MGT14EN_8822C BIT(14) +#define BIT_RXPSF_MGT13EN_8822C BIT(13) +#define BIT_RXPSF_MGT12EN_8822C BIT(12) +#define BIT_RXPSF_MGT11EN_8822C BIT(11) +#define BIT_RXPSF_MGT10EN_8822C BIT(10) +#define BIT_RXPSF_MGT9EN_8822C BIT(9) +#define BIT_RXPSF_MGT8EN_8822C BIT(8) +#define BIT_RXPSF_MGT7EN_8822C BIT(7) +#define BIT_RXPSF_MGT6EN_8822C BIT(6) +#define BIT_RXPSF_MGT5EN_8822C BIT(5) +#define BIT_RXPSF_MGT4EN_8822C BIT(4) +#define BIT_RXPSF_MGT3EN_8822C BIT(3) +#define BIT_RXPSF_MGT2EN_8822C BIT(2) +#define BIT_RXPSF_MGT1EN_8822C BIT(1) +#define BIT_RXPSF_MGT0EN_8822C BIT(0) + +/* 2 REG_CAM_ACCESS_CTRL_8822C */ +#define BIT_INDIRECT_ERR_8822C BIT(6) +#define BIT_DIRECT_ERR_8822C BIT(5) +#define BIT_DIR_ACCESS_EN_RX_BA_8822C BIT(4) +#define BIT_DIR_ACCESS_EN_MBSSIDCAM_8822C BIT(3) +#define BIT_DIR_ACCESS_EN_KEY_8822C BIT(2) +#define BIT_DIR_ACCESS_EN_WOWLAN_8822C BIT(1) +#define BIT_DIR_ACCESS_EN_FW_FILTER_8822C BIT(0) + +/* 2 REG_HT_SND_REF_RATE_8822C */ + +#define BIT_SHIFT_WMAC_HT_CSI_RATE_8822C 0 +#define BIT_MASK_WMAC_HT_CSI_RATE_8822C 0x3f +#define BIT_WMAC_HT_CSI_RATE_8822C(x) \ + (((x) & BIT_MASK_WMAC_HT_CSI_RATE_8822C) \ + << BIT_SHIFT_WMAC_HT_CSI_RATE_8822C) +#define BITS_WMAC_HT_CSI_RATE_8822C \ + (BIT_MASK_WMAC_HT_CSI_RATE_8822C << BIT_SHIFT_WMAC_HT_CSI_RATE_8822C) +#define BIT_CLEAR_WMAC_HT_CSI_RATE_8822C(x) \ + ((x) & (~BITS_WMAC_HT_CSI_RATE_8822C)) +#define BIT_GET_WMAC_HT_CSI_RATE_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_HT_CSI_RATE_8822C) & \ + BIT_MASK_WMAC_HT_CSI_RATE_8822C) +#define BIT_SET_WMAC_HT_CSI_RATE_8822C(x, v) \ + (BIT_CLEAR_WMAC_HT_CSI_RATE_8822C(x) | BIT_WMAC_HT_CSI_RATE_8822C(v)) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_MACID2_8822C (MAC ID2 REGISTER) */ + +#define BIT_SHIFT_MACID2_V1_8822C 0 +#define BIT_MASK_MACID2_V1_8822C 0xffffffffL +#define BIT_MACID2_V1_8822C(x) \ + (((x) & BIT_MASK_MACID2_V1_8822C) << BIT_SHIFT_MACID2_V1_8822C) +#define BITS_MACID2_V1_8822C \ + (BIT_MASK_MACID2_V1_8822C << BIT_SHIFT_MACID2_V1_8822C) +#define BIT_CLEAR_MACID2_V1_8822C(x) ((x) & (~BITS_MACID2_V1_8822C)) +#define BIT_GET_MACID2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID2_V1_8822C) & BIT_MASK_MACID2_V1_8822C) +#define BIT_SET_MACID2_V1_8822C(x, v) \ + (BIT_CLEAR_MACID2_V1_8822C(x) | BIT_MACID2_V1_8822C(v)) + +/* 2 REG_MACID2_H_8822C (MAC ID2 REGISTER) */ + +#define BIT_SHIFT_MACID2_H_V1_8822C 0 +#define BIT_MASK_MACID2_H_V1_8822C 0xffff +#define BIT_MACID2_H_V1_8822C(x) \ + (((x) & BIT_MASK_MACID2_H_V1_8822C) << BIT_SHIFT_MACID2_H_V1_8822C) +#define BITS_MACID2_H_V1_8822C \ + (BIT_MASK_MACID2_H_V1_8822C << BIT_SHIFT_MACID2_H_V1_8822C) +#define BIT_CLEAR_MACID2_H_V1_8822C(x) ((x) & (~BITS_MACID2_H_V1_8822C)) +#define BIT_GET_MACID2_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID2_H_V1_8822C) & BIT_MASK_MACID2_H_V1_8822C) +#define BIT_SET_MACID2_H_V1_8822C(x, v) \ + (BIT_CLEAR_MACID2_H_V1_8822C(x) | BIT_MACID2_H_V1_8822C(v)) + +/* 2 REG_BSSID2_8822C (BSSID2 REGISTER) */ + +#define BIT_SHIFT_BSSID2_V1_8822C 0 +#define BIT_MASK_BSSID2_V1_8822C 0xffffffffL +#define BIT_BSSID2_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID2_V1_8822C) << BIT_SHIFT_BSSID2_V1_8822C) +#define BITS_BSSID2_V1_8822C \ + (BIT_MASK_BSSID2_V1_8822C << BIT_SHIFT_BSSID2_V1_8822C) +#define BIT_CLEAR_BSSID2_V1_8822C(x) ((x) & (~BITS_BSSID2_V1_8822C)) +#define BIT_GET_BSSID2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID2_V1_8822C) & BIT_MASK_BSSID2_V1_8822C) +#define BIT_SET_BSSID2_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID2_V1_8822C(x) | BIT_BSSID2_V1_8822C(v)) + +/* 2 REG_BSSID2_H_8822C (BSSID2 REGISTER) */ + +#define BIT_SHIFT_BSSID2_H_V1_8822C 0 +#define BIT_MASK_BSSID2_H_V1_8822C 0xffff +#define BIT_BSSID2_H_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID2_H_V1_8822C) << BIT_SHIFT_BSSID2_H_V1_8822C) +#define BITS_BSSID2_H_V1_8822C \ + (BIT_MASK_BSSID2_H_V1_8822C << BIT_SHIFT_BSSID2_H_V1_8822C) +#define BIT_CLEAR_BSSID2_H_V1_8822C(x) ((x) & (~BITS_BSSID2_H_V1_8822C)) +#define BIT_GET_BSSID2_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID2_H_V1_8822C) & BIT_MASK_BSSID2_H_V1_8822C) +#define BIT_SET_BSSID2_H_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID2_H_V1_8822C(x) | BIT_BSSID2_H_V1_8822C(v)) + +/* 2 REG_MACID3_8822C (MAC ID3 REGISTER) */ + +#define BIT_SHIFT_MACID3_V1_8822C 0 +#define BIT_MASK_MACID3_V1_8822C 0xffffffffL +#define BIT_MACID3_V1_8822C(x) \ + (((x) & BIT_MASK_MACID3_V1_8822C) << BIT_SHIFT_MACID3_V1_8822C) +#define BITS_MACID3_V1_8822C \ + (BIT_MASK_MACID3_V1_8822C << BIT_SHIFT_MACID3_V1_8822C) +#define BIT_CLEAR_MACID3_V1_8822C(x) ((x) & (~BITS_MACID3_V1_8822C)) +#define BIT_GET_MACID3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID3_V1_8822C) & BIT_MASK_MACID3_V1_8822C) +#define BIT_SET_MACID3_V1_8822C(x, v) \ + (BIT_CLEAR_MACID3_V1_8822C(x) | BIT_MACID3_V1_8822C(v)) + +/* 2 REG_MACID3_H_8822C (MAC ID3 REGISTER) */ + +#define BIT_SHIFT_MACID3_H_V1_8822C 0 +#define BIT_MASK_MACID3_H_V1_8822C 0xffff +#define BIT_MACID3_H_V1_8822C(x) \ + (((x) & BIT_MASK_MACID3_H_V1_8822C) << BIT_SHIFT_MACID3_H_V1_8822C) +#define BITS_MACID3_H_V1_8822C \ + (BIT_MASK_MACID3_H_V1_8822C << BIT_SHIFT_MACID3_H_V1_8822C) +#define BIT_CLEAR_MACID3_H_V1_8822C(x) ((x) & (~BITS_MACID3_H_V1_8822C)) +#define BIT_GET_MACID3_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID3_H_V1_8822C) & BIT_MASK_MACID3_H_V1_8822C) +#define BIT_SET_MACID3_H_V1_8822C(x, v) \ + (BIT_CLEAR_MACID3_H_V1_8822C(x) | BIT_MACID3_H_V1_8822C(v)) + +/* 2 REG_BSSID3_8822C (BSSID3 REGISTER) */ + +#define BIT_SHIFT_BSSID3_V1_8822C 0 +#define BIT_MASK_BSSID3_V1_8822C 0xffffffffL +#define BIT_BSSID3_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID3_V1_8822C) << BIT_SHIFT_BSSID3_V1_8822C) +#define BITS_BSSID3_V1_8822C \ + (BIT_MASK_BSSID3_V1_8822C << BIT_SHIFT_BSSID3_V1_8822C) +#define BIT_CLEAR_BSSID3_V1_8822C(x) ((x) & (~BITS_BSSID3_V1_8822C)) +#define BIT_GET_BSSID3_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID3_V1_8822C) & BIT_MASK_BSSID3_V1_8822C) +#define BIT_SET_BSSID3_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID3_V1_8822C(x) | BIT_BSSID3_V1_8822C(v)) + +/* 2 REG_BSSID3_H_8822C (BSSID3 REGISTER) */ + +#define BIT_SHIFT_BSSID3_H_V1_8822C 0 +#define BIT_MASK_BSSID3_H_V1_8822C 0xffff +#define BIT_BSSID3_H_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID3_H_V1_8822C) << BIT_SHIFT_BSSID3_H_V1_8822C) +#define BITS_BSSID3_H_V1_8822C \ + (BIT_MASK_BSSID3_H_V1_8822C << BIT_SHIFT_BSSID3_H_V1_8822C) +#define BIT_CLEAR_BSSID3_H_V1_8822C(x) ((x) & (~BITS_BSSID3_H_V1_8822C)) +#define BIT_GET_BSSID3_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID3_H_V1_8822C) & BIT_MASK_BSSID3_H_V1_8822C) +#define BIT_SET_BSSID3_H_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID3_H_V1_8822C(x) | BIT_BSSID3_H_V1_8822C(v)) + +/* 2 REG_MACID4_8822C (MAC ID4 REGISTER) */ + +#define BIT_SHIFT_MACID4_V1_8822C 0 +#define BIT_MASK_MACID4_V1_8822C 0xffffffffL +#define BIT_MACID4_V1_8822C(x) \ + (((x) & BIT_MASK_MACID4_V1_8822C) << BIT_SHIFT_MACID4_V1_8822C) +#define BITS_MACID4_V1_8822C \ + (BIT_MASK_MACID4_V1_8822C << BIT_SHIFT_MACID4_V1_8822C) +#define BIT_CLEAR_MACID4_V1_8822C(x) ((x) & (~BITS_MACID4_V1_8822C)) +#define BIT_GET_MACID4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID4_V1_8822C) & BIT_MASK_MACID4_V1_8822C) +#define BIT_SET_MACID4_V1_8822C(x, v) \ + (BIT_CLEAR_MACID4_V1_8822C(x) | BIT_MACID4_V1_8822C(v)) + +/* 2 REG_MACID4_H_8822C (MAC ID4 REGISTER) */ + +#define BIT_SHIFT_MACID4_H_V1_8822C 0 +#define BIT_MASK_MACID4_H_V1_8822C 0xffff +#define BIT_MACID4_H_V1_8822C(x) \ + (((x) & BIT_MASK_MACID4_H_V1_8822C) << BIT_SHIFT_MACID4_H_V1_8822C) +#define BITS_MACID4_H_V1_8822C \ + (BIT_MASK_MACID4_H_V1_8822C << BIT_SHIFT_MACID4_H_V1_8822C) +#define BIT_CLEAR_MACID4_H_V1_8822C(x) ((x) & (~BITS_MACID4_H_V1_8822C)) +#define BIT_GET_MACID4_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID4_H_V1_8822C) & BIT_MASK_MACID4_H_V1_8822C) +#define BIT_SET_MACID4_H_V1_8822C(x, v) \ + (BIT_CLEAR_MACID4_H_V1_8822C(x) | BIT_MACID4_H_V1_8822C(v)) + +/* 2 REG_BSSID4_8822C (BSSID4 REGISTER) */ + +#define BIT_SHIFT_BSSID4_V1_8822C 0 +#define BIT_MASK_BSSID4_V1_8822C 0xffffffffL +#define BIT_BSSID4_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID4_V1_8822C) << BIT_SHIFT_BSSID4_V1_8822C) +#define BITS_BSSID4_V1_8822C \ + (BIT_MASK_BSSID4_V1_8822C << BIT_SHIFT_BSSID4_V1_8822C) +#define BIT_CLEAR_BSSID4_V1_8822C(x) ((x) & (~BITS_BSSID4_V1_8822C)) +#define BIT_GET_BSSID4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID4_V1_8822C) & BIT_MASK_BSSID4_V1_8822C) +#define BIT_SET_BSSID4_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID4_V1_8822C(x) | BIT_BSSID4_V1_8822C(v)) + +/* 2 REG_BSSID4_H_8822C (BSSID4 REGISTER) */ + +#define BIT_SHIFT_BSSID4_H_V1_8822C 0 +#define BIT_MASK_BSSID4_H_V1_8822C 0xffff +#define BIT_BSSID4_H_V1_8822C(x) \ + (((x) & BIT_MASK_BSSID4_H_V1_8822C) << BIT_SHIFT_BSSID4_H_V1_8822C) +#define BITS_BSSID4_H_V1_8822C \ + (BIT_MASK_BSSID4_H_V1_8822C << BIT_SHIFT_BSSID4_H_V1_8822C) +#define BIT_CLEAR_BSSID4_H_V1_8822C(x) ((x) & (~BITS_BSSID4_H_V1_8822C)) +#define BIT_GET_BSSID4_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID4_H_V1_8822C) & BIT_MASK_BSSID4_H_V1_8822C) +#define BIT_SET_BSSID4_H_V1_8822C(x, v) \ + (BIT_CLEAR_BSSID4_H_V1_8822C(x) | BIT_BSSID4_H_V1_8822C(v)) + +/* 2 REG_NOA_REPORT_8822C */ + +/* 2 REG_NOA_REPORT_1_8822C */ + +/* 2 REG_NOA_REPORT_2_8822C */ + +/* 2 REG_NOA_REPORT_3_8822C */ + +/* 2 REG_PWRBIT_SETTING_8822C */ +#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(15) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(14) +#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(13) +#define BIT_CLI3_PWR_ST_V1_8822C BIT(12) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(11) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(10) +#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(9) +#define BIT_CLI2_PWR_ST_V1_8822C BIT(8) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(7) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(6) +#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(5) +#define BIT_CLI1_PWR_ST_V1_8822C BIT(4) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(3) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(2) +#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(1) +#define BIT_CLI0_PWR_ST_V1_8822C BIT(0) + +/* 2 REG_GENERAL_OPTION_8822C */ +#define BIT_WMAC_RXRST_NDP_TIMEOUT_8822C BIT(11) +#define BIT_WMAC_NDP_STANDBY_WAIT_RXEND_8822C BIT(10) +#define BIT_DUMMY_FCS_READY_MASK_EN_8822C BIT(9) +#define BIT_RXFIFO_GNT_CUT_8822C BIT(8) +#define BIT_DUMMY_RXD_FCS_ERROR_MASK_EN_V1_8822C BIT(7) +#define BIT_WMAC_EXT_DBG_SEL_V1_8822C BIT(6) +#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8822C BIT(5) +#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA_8822C BIT(4) +#define BIT_RX_DMA_BYPASS_CHECK_MGTBIT_RX_DMA_BYPASS_CHECK_MGT_8822C BIT(3) +#define BIT_TXSERV_FIELD_SEL_8822C BIT(2) +#define BIT_RXVHT_LEN_SEL_8822C BIT(1) +#define BIT_RXMIC_PROTECT_EN_8822C BIT(0) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_CSI_RRSR_8822C */ +#define BIT_CSI_LDPC_EN_8822C BIT(29) +#define BIT_CSI_STBC_EN_8822C BIT(28) + +#define BIT_SHIFT_CSI_RRSC_BITMAP_8822C 4 +#define BIT_MASK_CSI_RRSC_BITMAP_8822C 0xffffff +#define BIT_CSI_RRSC_BITMAP_8822C(x) \ + (((x) & BIT_MASK_CSI_RRSC_BITMAP_8822C) \ + << BIT_SHIFT_CSI_RRSC_BITMAP_8822C) +#define BITS_CSI_RRSC_BITMAP_8822C \ + (BIT_MASK_CSI_RRSC_BITMAP_8822C << BIT_SHIFT_CSI_RRSC_BITMAP_8822C) +#define BIT_CLEAR_CSI_RRSC_BITMAP_8822C(x) ((x) & (~BITS_CSI_RRSC_BITMAP_8822C)) +#define BIT_GET_CSI_RRSC_BITMAP_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_RRSC_BITMAP_8822C) & \ + BIT_MASK_CSI_RRSC_BITMAP_8822C) +#define BIT_SET_CSI_RRSC_BITMAP_8822C(x, v) \ + (BIT_CLEAR_CSI_RRSC_BITMAP_8822C(x) | BIT_CSI_RRSC_BITMAP_8822C(v)) + +#define BIT_SHIFT_OFDM_LEN_TH_8822C 0 +#define BIT_MASK_OFDM_LEN_TH_8822C 0xf +#define BIT_OFDM_LEN_TH_8822C(x) \ + (((x) & BIT_MASK_OFDM_LEN_TH_8822C) << BIT_SHIFT_OFDM_LEN_TH_8822C) +#define BITS_OFDM_LEN_TH_8822C \ + (BIT_MASK_OFDM_LEN_TH_8822C << BIT_SHIFT_OFDM_LEN_TH_8822C) +#define BIT_CLEAR_OFDM_LEN_TH_8822C(x) ((x) & (~BITS_OFDM_LEN_TH_8822C)) +#define BIT_GET_OFDM_LEN_TH_8822C(x) \ + (((x) >> BIT_SHIFT_OFDM_LEN_TH_8822C) & BIT_MASK_OFDM_LEN_TH_8822C) +#define BIT_SET_OFDM_LEN_TH_8822C(x, v) \ + (BIT_CLEAR_OFDM_LEN_TH_8822C(x) | BIT_OFDM_LEN_TH_8822C(v)) + +/* 2 REG_MU_BF_OPTION_8822C */ +#define BIT_WMAC_RESP_NONSTA1_DIS_8822C BIT(7) +#define BIT_WMAC_TXMU_ACKPOLICY_EN_8822C BIT(6) + +#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C 4 +#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C 0x3 +#define BIT_WMAC_TXMU_ACKPOLICY_8822C(x) \ + (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C) \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C) +#define BITS_WMAC_TXMU_ACKPOLICY_8822C \ + (BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C \ + << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C) +#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822C(x) \ + ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8822C)) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C) & \ + BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C) +#define BIT_SET_WMAC_TXMU_ACKPOLICY_8822C(x, v) \ + (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822C(x) | \ + BIT_WMAC_TXMU_ACKPOLICY_8822C(v)) + +#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C 1 +#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C 0x7 +#define BIT_WMAC_MU_BFEE_PORT_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C) +#define BITS_WMAC_MU_BFEE_PORT_SEL_8822C \ + (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C \ + << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8822C)) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C) & \ + BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C) +#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822C(x) | \ + BIT_WMAC_MU_BFEE_PORT_SEL_8822C(v)) + +#define BIT_WMAC_MU_BFEE_DIS_8822C BIT(0) + +/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8822C */ + +#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C 0 +#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C 0xff +#define BIT_WMAC_PAUSE_BB_CLR_TH_8822C(x) \ + (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C) \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C) +#define BITS_WMAC_PAUSE_BB_CLR_TH_8822C \ + (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C \ + << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C) +#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822C(x) \ + ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8822C)) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C) & \ + BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C) +#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8822C(x, v) \ + (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822C(x) | \ + BIT_WMAC_PAUSE_BB_CLR_TH_8822C(v)) + +/* 2 REG__WMAC_MULBK_BUF_8822C */ + +#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C 0 +#define BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C 0xff +#define BIT_WMAC_MULBK_PAGE_SIZE_8822C(x) \ + (((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C) \ + << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C) +#define BITS_WMAC_MULBK_PAGE_SIZE_8822C \ + (BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C \ + << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C) +#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8822C(x) \ + ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE_8822C)) +#define BIT_GET_WMAC_MULBK_PAGE_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C) & \ + BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C) +#define BIT_SET_WMAC_MULBK_PAGE_SIZE_8822C(x, v) \ + (BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8822C(x) | \ + BIT_WMAC_MULBK_PAGE_SIZE_8822C(v)) + +/* 2 REG_WMAC_MU_OPTION_8822C */ + +/* 2 REG_WMAC_MU_BF_CTL_8822C */ +#define BIT_WMAC_INVLD_BFPRT_CHK_8822C BIT(15) +#define BIT_WMAC_RETXBFRPTSEQ_UPD_8822C BIT(14) + +#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C 12 +#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C 0x3 +#define BIT_WMAC_MU_BFRPTSEG_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C) \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C) +#define BITS_WMAC_MU_BFRPTSEG_SEL_8822C \ + (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C \ + << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822C)) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C) & \ + BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x) | \ + BIT_WMAC_MU_BFRPTSEG_SEL_8822C(v)) + +#define BIT_SHIFT_WMAC_MU_BF_MYAID_8822C 0 +#define BIT_MASK_WMAC_MU_BF_MYAID_8822C 0xfff +#define BIT_WMAC_MU_BF_MYAID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822C) \ + << BIT_SHIFT_WMAC_MU_BF_MYAID_8822C) +#define BITS_WMAC_MU_BF_MYAID_8822C \ + (BIT_MASK_WMAC_MU_BF_MYAID_8822C << BIT_SHIFT_WMAC_MU_BF_MYAID_8822C) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BF_MYAID_8822C)) +#define BIT_GET_WMAC_MU_BF_MYAID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822C) & \ + BIT_MASK_WMAC_MU_BF_MYAID_8822C) +#define BIT_SET_WMAC_MU_BF_MYAID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x) | BIT_WMAC_MU_BF_MYAID_8822C(v)) + +/* 2 REG_WMAC_MU_BFRPT_PARA_8822C */ + +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C 13 +#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C 0x7 +#define BIT_BFRPT_PARA_USERID_SEL_V1_8822C(x) \ + (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C) \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C) +#define BITS_BFRPT_PARA_USERID_SEL_V1_8822C \ + (BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C \ + << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C) +#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8822C(x) \ + ((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1_8822C)) +#define BIT_GET_BFRPT_PARA_USERID_SEL_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C) & \ + BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C) +#define BIT_SET_BFRPT_PARA_USERID_SEL_V1_8822C(x, v) \ + (BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8822C(x) | \ + BIT_BFRPT_PARA_USERID_SEL_V1_8822C(v)) + +#define BIT_SHIFT_BFRPT_PARA_V1_8822C 0 +#define BIT_MASK_BFRPT_PARA_V1_8822C 0x1fff +#define BIT_BFRPT_PARA_V1_8822C(x) \ + (((x) & BIT_MASK_BFRPT_PARA_V1_8822C) << BIT_SHIFT_BFRPT_PARA_V1_8822C) +#define BITS_BFRPT_PARA_V1_8822C \ + (BIT_MASK_BFRPT_PARA_V1_8822C << BIT_SHIFT_BFRPT_PARA_V1_8822C) +#define BIT_CLEAR_BFRPT_PARA_V1_8822C(x) ((x) & (~BITS_BFRPT_PARA_V1_8822C)) +#define BIT_GET_BFRPT_PARA_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BFRPT_PARA_V1_8822C) & BIT_MASK_BFRPT_PARA_V1_8822C) +#define BIT_SET_BFRPT_PARA_V1_8822C(x, v) \ + (BIT_CLEAR_BFRPT_PARA_V1_8822C(x) | BIT_BFRPT_PARA_V1_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C */ +#define BIT_STATUS_BFEE2_8822C BIT(10) +#define BIT_WMAC_MU_BFEE2_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE2_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE2_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C) +#define BITS_WMAC_MU_BFEE2_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE2_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE2_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE2_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE2_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE2_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE2_AID_8822C(x) | BIT_WMAC_MU_BFEE2_AID_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C */ +#define BIT_STATUS_BFEE3_8822C BIT(10) +#define BIT_WMAC_MU_BFEE3_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE3_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE3_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C) +#define BITS_WMAC_MU_BFEE3_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE3_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE3_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE3_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE3_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE3_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE3_AID_8822C(x) | BIT_WMAC_MU_BFEE3_AID_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C */ +#define BIT_STATUS_BFEE4_8822C BIT(10) +#define BIT_WMAC_MU_BFEE4_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE4_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE4_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C) +#define BITS_WMAC_MU_BFEE4_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE4_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE4_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE4_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE4_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE4_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE4_AID_8822C(x) | BIT_WMAC_MU_BFEE4_AID_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C */ +#define BIT_BIT_STATUS_BFEE5_8822C BIT(10) +#define BIT_WMAC_MU_BFEE5_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE5_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE5_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C) +#define BITS_WMAC_MU_BFEE5_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE5_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE5_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE5_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE5_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE5_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE5_AID_8822C(x) | BIT_WMAC_MU_BFEE5_AID_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C */ +#define BIT_STATUS_BFEE6_8822C BIT(10) +#define BIT_WMAC_MU_BFEE6_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE6_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE6_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C) +#define BITS_WMAC_MU_BFEE6_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE6_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE6_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE6_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE6_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE6_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE6_AID_8822C(x) | BIT_WMAC_MU_BFEE6_AID_8822C(v)) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C */ +#define BIT_STATUS_BFEE7_8822C BIT(10) +#define BIT_WMAC_MU_BFEE7_EN_8822C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C 0 +#define BIT_MASK_WMAC_MU_BFEE7_AID_8822C 0x1ff +#define BIT_WMAC_MU_BFEE7_AID_8822C(x) \ + (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822C) \ + << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C) +#define BITS_WMAC_MU_BFEE7_AID_8822C \ + (BIT_MASK_WMAC_MU_BFEE7_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C) +#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8822C(x) \ + ((x) & (~BITS_WMAC_MU_BFEE7_AID_8822C)) +#define BIT_GET_WMAC_MU_BFEE7_AID_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C) & \ + BIT_MASK_WMAC_MU_BFEE7_AID_8822C) +#define BIT_SET_WMAC_MU_BFEE7_AID_8822C(x, v) \ + (BIT_CLEAR_WMAC_MU_BFEE7_AID_8822C(x) | BIT_WMAC_MU_BFEE7_AID_8822C(v)) + +/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8822C */ +#define BIT_RST_ALL_COUNTER_8822C BIT(31) + +#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C 16 +#define BIT_MASK_ABORT_RX_VBON_COUNTER_8822C 0xff +#define BIT_ABORT_RX_VBON_COUNTER_8822C(x) \ + (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822C) \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C) +#define BITS_ABORT_RX_VBON_COUNTER_8822C \ + (BIT_MASK_ABORT_RX_VBON_COUNTER_8822C \ + << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C) +#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822C(x) \ + ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8822C)) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8822C(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C) & \ + BIT_MASK_ABORT_RX_VBON_COUNTER_8822C) +#define BIT_SET_ABORT_RX_VBON_COUNTER_8822C(x, v) \ + (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822C(x) | \ + BIT_ABORT_RX_VBON_COUNTER_8822C(v)) + +#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C 8 +#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C 0xff +#define BIT_ABORT_RX_RDRDY_COUNTER_8822C(x) \ + (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C) \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C) +#define BITS_ABORT_RX_RDRDY_COUNTER_8822C \ + (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C \ + << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C) +#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822C(x) \ + ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8822C)) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822C(x) \ + (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C) & \ + BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C) +#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8822C(x, v) \ + (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822C(x) | \ + BIT_ABORT_RX_RDRDY_COUNTER_8822C(v)) + +#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C 0 +#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C 0xff +#define BIT_VBON_EARLY_FALLING_COUNTER_8822C(x) \ + (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C) \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C) +#define BITS_VBON_EARLY_FALLING_COUNTER_8822C \ + (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C \ + << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C) +#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822C(x) \ + ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8822C)) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822C(x) \ + (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C) & \ + BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C) +#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8822C(x, v) \ + (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822C(x) | \ + BIT_VBON_EARLY_FALLING_COUNTER_8822C(v)) + +/* 2 REG_WMAC_PLCP_MONITOR_8822C */ +#define BIT_WMAC_PLCP_TRX_SEL_8822C BIT(31) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C 28 +#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C 0x7 +#define BIT_WMAC_PLCP_RDSIG_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C) +#define BITS_WMAC_PLCP_RDSIG_SEL_8822C \ + (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822C(x) \ + ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8822C)) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C) +#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822C(x) | \ + BIT_WMAC_PLCP_RDSIG_SEL_8822C(v)) + +#define BIT_SHIFT_WMAC_RATE_IDX_8822C 24 +#define BIT_MASK_WMAC_RATE_IDX_8822C 0xf +#define BIT_WMAC_RATE_IDX_8822C(x) \ + (((x) & BIT_MASK_WMAC_RATE_IDX_8822C) << BIT_SHIFT_WMAC_RATE_IDX_8822C) +#define BITS_WMAC_RATE_IDX_8822C \ + (BIT_MASK_WMAC_RATE_IDX_8822C << BIT_SHIFT_WMAC_RATE_IDX_8822C) +#define BIT_CLEAR_WMAC_RATE_IDX_8822C(x) ((x) & (~BITS_WMAC_RATE_IDX_8822C)) +#define BIT_GET_WMAC_RATE_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822C) & BIT_MASK_WMAC_RATE_IDX_8822C) +#define BIT_SET_WMAC_RATE_IDX_8822C(x, v) \ + (BIT_CLEAR_WMAC_RATE_IDX_8822C(x) | BIT_WMAC_RATE_IDX_8822C(v)) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822C 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8822C 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8822C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) +#define BITS_WMAC_PLCP_RDSIG_8822C \ + (BIT_MASK_WMAC_PLCP_RDSIG_8822C << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822C)) +#define BIT_GET_WMAC_PLCP_RDSIG_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8822C) +#define BIT_SET_WMAC_PLCP_RDSIG_8822C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) | BIT_WMAC_PLCP_RDSIG_8822C(v)) + +/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8822C */ +#define BIT_WMAC_MUTX_IDX_8822C BIT(24) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822C 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8822C 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8822C(x) \ + (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822C) \ + << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) +#define BITS_WMAC_PLCP_RDSIG_8822C \ + (BIT_MASK_WMAC_PLCP_RDSIG_8822C << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) +#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822C)) +#define BIT_GET_WMAC_PLCP_RDSIG_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) & \ + BIT_MASK_WMAC_PLCP_RDSIG_8822C) +#define BIT_SET_WMAC_PLCP_RDSIG_8822C(x, v) \ + (BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) | BIT_WMAC_PLCP_RDSIG_8822C(v)) + +/* 2 REG_WMAC_CSIDMA_CFG_8822C */ + +#define BIT_SHIFT_CSI_SEG_SIZE_8822C 16 +#define BIT_MASK_CSI_SEG_SIZE_8822C 0xfff +#define BIT_CSI_SEG_SIZE_8822C(x) \ + (((x) & BIT_MASK_CSI_SEG_SIZE_8822C) << BIT_SHIFT_CSI_SEG_SIZE_8822C) +#define BITS_CSI_SEG_SIZE_8822C \ + (BIT_MASK_CSI_SEG_SIZE_8822C << BIT_SHIFT_CSI_SEG_SIZE_8822C) +#define BIT_CLEAR_CSI_SEG_SIZE_8822C(x) ((x) & (~BITS_CSI_SEG_SIZE_8822C)) +#define BIT_GET_CSI_SEG_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_SEG_SIZE_8822C) & BIT_MASK_CSI_SEG_SIZE_8822C) +#define BIT_SET_CSI_SEG_SIZE_8822C(x, v) \ + (BIT_CLEAR_CSI_SEG_SIZE_8822C(x) | BIT_CSI_SEG_SIZE_8822C(v)) + +#define BIT_SHIFT_CSI_START_PAGE_8822C 0 +#define BIT_MASK_CSI_START_PAGE_8822C 0xfff +#define BIT_CSI_START_PAGE_8822C(x) \ + (((x) & BIT_MASK_CSI_START_PAGE_8822C) \ + << BIT_SHIFT_CSI_START_PAGE_8822C) +#define BITS_CSI_START_PAGE_8822C \ + (BIT_MASK_CSI_START_PAGE_8822C << BIT_SHIFT_CSI_START_PAGE_8822C) +#define BIT_CLEAR_CSI_START_PAGE_8822C(x) ((x) & (~BITS_CSI_START_PAGE_8822C)) +#define BIT_GET_CSI_START_PAGE_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_START_PAGE_8822C) & \ + BIT_MASK_CSI_START_PAGE_8822C) +#define BIT_SET_CSI_START_PAGE_8822C(x, v) \ + (BIT_CLEAR_CSI_START_PAGE_8822C(x) | BIT_CSI_START_PAGE_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_0_8822C (TA0 REGISTER) */ + +#define BIT_SHIFT_TA0_V1_8822C 0 +#define BIT_MASK_TA0_V1_8822C 0xffffffffL +#define BIT_TA0_V1_8822C(x) \ + (((x) & BIT_MASK_TA0_V1_8822C) << BIT_SHIFT_TA0_V1_8822C) +#define BITS_TA0_V1_8822C (BIT_MASK_TA0_V1_8822C << BIT_SHIFT_TA0_V1_8822C) +#define BIT_CLEAR_TA0_V1_8822C(x) ((x) & (~BITS_TA0_V1_8822C)) +#define BIT_GET_TA0_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA0_V1_8822C) & BIT_MASK_TA0_V1_8822C) +#define BIT_SET_TA0_V1_8822C(x, v) \ + (BIT_CLEAR_TA0_V1_8822C(x) | BIT_TA0_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_0_H_8822C (TA0 REGISTER) */ + +#define BIT_SHIFT_TA0_H_V1_8822C 0 +#define BIT_MASK_TA0_H_V1_8822C 0xffff +#define BIT_TA0_H_V1_8822C(x) \ + (((x) & BIT_MASK_TA0_H_V1_8822C) << BIT_SHIFT_TA0_H_V1_8822C) +#define BITS_TA0_H_V1_8822C \ + (BIT_MASK_TA0_H_V1_8822C << BIT_SHIFT_TA0_H_V1_8822C) +#define BIT_CLEAR_TA0_H_V1_8822C(x) ((x) & (~BITS_TA0_H_V1_8822C)) +#define BIT_GET_TA0_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA0_H_V1_8822C) & BIT_MASK_TA0_H_V1_8822C) +#define BIT_SET_TA0_H_V1_8822C(x, v) \ + (BIT_CLEAR_TA0_H_V1_8822C(x) | BIT_TA0_H_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_1_8822C (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_V1_8822C 0 +#define BIT_MASK_TA1_V1_8822C 0xffffffffL +#define BIT_TA1_V1_8822C(x) \ + (((x) & BIT_MASK_TA1_V1_8822C) << BIT_SHIFT_TA1_V1_8822C) +#define BITS_TA1_V1_8822C (BIT_MASK_TA1_V1_8822C << BIT_SHIFT_TA1_V1_8822C) +#define BIT_CLEAR_TA1_V1_8822C(x) ((x) & (~BITS_TA1_V1_8822C)) +#define BIT_GET_TA1_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA1_V1_8822C) & BIT_MASK_TA1_V1_8822C) +#define BIT_SET_TA1_V1_8822C(x, v) \ + (BIT_CLEAR_TA1_V1_8822C(x) | BIT_TA1_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_1_H_8822C (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_H_V1_8822C 0 +#define BIT_MASK_TA1_H_V1_8822C 0xffff +#define BIT_TA1_H_V1_8822C(x) \ + (((x) & BIT_MASK_TA1_H_V1_8822C) << BIT_SHIFT_TA1_H_V1_8822C) +#define BITS_TA1_H_V1_8822C \ + (BIT_MASK_TA1_H_V1_8822C << BIT_SHIFT_TA1_H_V1_8822C) +#define BIT_CLEAR_TA1_H_V1_8822C(x) ((x) & (~BITS_TA1_H_V1_8822C)) +#define BIT_GET_TA1_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA1_H_V1_8822C) & BIT_MASK_TA1_H_V1_8822C) +#define BIT_SET_TA1_H_V1_8822C(x, v) \ + (BIT_CLEAR_TA1_H_V1_8822C(x) | BIT_TA1_H_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_2_8822C (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_V1_8822C 0 +#define BIT_MASK_TA2_V1_8822C 0xffffffffL +#define BIT_TA2_V1_8822C(x) \ + (((x) & BIT_MASK_TA2_V1_8822C) << BIT_SHIFT_TA2_V1_8822C) +#define BITS_TA2_V1_8822C (BIT_MASK_TA2_V1_8822C << BIT_SHIFT_TA2_V1_8822C) +#define BIT_CLEAR_TA2_V1_8822C(x) ((x) & (~BITS_TA2_V1_8822C)) +#define BIT_GET_TA2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8822C) & BIT_MASK_TA2_V1_8822C) +#define BIT_SET_TA2_V1_8822C(x, v) \ + (BIT_CLEAR_TA2_V1_8822C(x) | BIT_TA2_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_2_H_8822C (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_H_V1_8822C 0 +#define BIT_MASK_TA2_H_V1_8822C 0xffff +#define BIT_TA2_H_V1_8822C(x) \ + (((x) & BIT_MASK_TA2_H_V1_8822C) << BIT_SHIFT_TA2_H_V1_8822C) +#define BITS_TA2_H_V1_8822C \ + (BIT_MASK_TA2_H_V1_8822C << BIT_SHIFT_TA2_H_V1_8822C) +#define BIT_CLEAR_TA2_H_V1_8822C(x) ((x) & (~BITS_TA2_H_V1_8822C)) +#define BIT_GET_TA2_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA2_H_V1_8822C) & BIT_MASK_TA2_H_V1_8822C) +#define BIT_SET_TA2_H_V1_8822C(x, v) \ + (BIT_CLEAR_TA2_H_V1_8822C(x) | BIT_TA2_H_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_3_8822C (TA3 REGISTER) */ + +#define BIT_SHIFT_TA2_V1_8822C 0 +#define BIT_MASK_TA2_V1_8822C 0xffffffffL +#define BIT_TA2_V1_8822C(x) \ + (((x) & BIT_MASK_TA2_V1_8822C) << BIT_SHIFT_TA2_V1_8822C) +#define BITS_TA2_V1_8822C (BIT_MASK_TA2_V1_8822C << BIT_SHIFT_TA2_V1_8822C) +#define BIT_CLEAR_TA2_V1_8822C(x) ((x) & (~BITS_TA2_V1_8822C)) +#define BIT_GET_TA2_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA2_V1_8822C) & BIT_MASK_TA2_V1_8822C) +#define BIT_SET_TA2_V1_8822C(x, v) \ + (BIT_CLEAR_TA2_V1_8822C(x) | BIT_TA2_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_3_H_8822C (TA3 REGISTER) */ + +#define BIT_SHIFT_TA3_H_V1_8822C 0 +#define BIT_MASK_TA3_H_V1_8822C 0xffff +#define BIT_TA3_H_V1_8822C(x) \ + (((x) & BIT_MASK_TA3_H_V1_8822C) << BIT_SHIFT_TA3_H_V1_8822C) +#define BITS_TA3_H_V1_8822C \ + (BIT_MASK_TA3_H_V1_8822C << BIT_SHIFT_TA3_H_V1_8822C) +#define BIT_CLEAR_TA3_H_V1_8822C(x) ((x) & (~BITS_TA3_H_V1_8822C)) +#define BIT_GET_TA3_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA3_H_V1_8822C) & BIT_MASK_TA3_H_V1_8822C) +#define BIT_SET_TA3_H_V1_8822C(x, v) \ + (BIT_CLEAR_TA3_H_V1_8822C(x) | BIT_TA3_H_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_4_8822C (TA4 REGISTER) */ + +#define BIT_SHIFT_TA4_V1_8822C 0 +#define BIT_MASK_TA4_V1_8822C 0xffffffffL +#define BIT_TA4_V1_8822C(x) \ + (((x) & BIT_MASK_TA4_V1_8822C) << BIT_SHIFT_TA4_V1_8822C) +#define BITS_TA4_V1_8822C (BIT_MASK_TA4_V1_8822C << BIT_SHIFT_TA4_V1_8822C) +#define BIT_CLEAR_TA4_V1_8822C(x) ((x) & (~BITS_TA4_V1_8822C)) +#define BIT_GET_TA4_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA4_V1_8822C) & BIT_MASK_TA4_V1_8822C) +#define BIT_SET_TA4_V1_8822C(x, v) \ + (BIT_CLEAR_TA4_V1_8822C(x) | BIT_TA4_V1_8822C(v)) + +/* 2 REG_TRANSMIT_ADDRSS_4_H_8822C (TA4 REGISTER) */ + +#define BIT_SHIFT_TA4_H_V1_8822C 0 +#define BIT_MASK_TA4_H_V1_8822C 0xffff +#define BIT_TA4_H_V1_8822C(x) \ + (((x) & BIT_MASK_TA4_H_V1_8822C) << BIT_SHIFT_TA4_H_V1_8822C) +#define BITS_TA4_H_V1_8822C \ + (BIT_MASK_TA4_H_V1_8822C << BIT_SHIFT_TA4_H_V1_8822C) +#define BIT_CLEAR_TA4_H_V1_8822C(x) ((x) & (~BITS_TA4_H_V1_8822C)) +#define BIT_GET_TA4_H_V1_8822C(x) \ + (((x) >> BIT_SHIFT_TA4_H_V1_8822C) & BIT_MASK_TA4_H_V1_8822C) +#define BIT_SET_TA4_H_V1_8822C(x, v) \ + (BIT_CLEAR_TA4_H_V1_8822C(x) | BIT_TA4_H_V1_8822C(v)) + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_RSVD_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_MACID1_8822C */ + +#define BIT_SHIFT_MACID1_0_8822C 0 +#define BIT_MASK_MACID1_0_8822C 0xffffffffL +#define BIT_MACID1_0_8822C(x) \ + (((x) & BIT_MASK_MACID1_0_8822C) << BIT_SHIFT_MACID1_0_8822C) +#define BITS_MACID1_0_8822C \ + (BIT_MASK_MACID1_0_8822C << BIT_SHIFT_MACID1_0_8822C) +#define BIT_CLEAR_MACID1_0_8822C(x) ((x) & (~BITS_MACID1_0_8822C)) +#define BIT_GET_MACID1_0_8822C(x) \ + (((x) >> BIT_SHIFT_MACID1_0_8822C) & BIT_MASK_MACID1_0_8822C) +#define BIT_SET_MACID1_0_8822C(x, v) \ + (BIT_CLEAR_MACID1_0_8822C(x) | BIT_MACID1_0_8822C(v)) + +/* 2 REG_MACID1_1_8822C */ + +#define BIT_SHIFT_MACID1_1_8822C 0 +#define BIT_MASK_MACID1_1_8822C 0xffff +#define BIT_MACID1_1_8822C(x) \ + (((x) & BIT_MASK_MACID1_1_8822C) << BIT_SHIFT_MACID1_1_8822C) +#define BITS_MACID1_1_8822C \ + (BIT_MASK_MACID1_1_8822C << BIT_SHIFT_MACID1_1_8822C) +#define BIT_CLEAR_MACID1_1_8822C(x) ((x) & (~BITS_MACID1_1_8822C)) +#define BIT_GET_MACID1_1_8822C(x) \ + (((x) >> BIT_SHIFT_MACID1_1_8822C) & BIT_MASK_MACID1_1_8822C) +#define BIT_SET_MACID1_1_8822C(x, v) \ + (BIT_CLEAR_MACID1_1_8822C(x) | BIT_MACID1_1_8822C(v)) + +/* 2 REG_BSSID1_8822C */ + +#define BIT_SHIFT_BSSID1_0_8822C 0 +#define BIT_MASK_BSSID1_0_8822C 0xffffffffL +#define BIT_BSSID1_0_8822C(x) \ + (((x) & BIT_MASK_BSSID1_0_8822C) << BIT_SHIFT_BSSID1_0_8822C) +#define BITS_BSSID1_0_8822C \ + (BIT_MASK_BSSID1_0_8822C << BIT_SHIFT_BSSID1_0_8822C) +#define BIT_CLEAR_BSSID1_0_8822C(x) ((x) & (~BITS_BSSID1_0_8822C)) +#define BIT_GET_BSSID1_0_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID1_0_8822C) & BIT_MASK_BSSID1_0_8822C) +#define BIT_SET_BSSID1_0_8822C(x, v) \ + (BIT_CLEAR_BSSID1_0_8822C(x) | BIT_BSSID1_0_8822C(v)) + +/* 2 REG_BSSID1_1_8822C */ + +#define BIT_SHIFT_BSSID1_1_8822C 0 +#define BIT_MASK_BSSID1_1_8822C 0xffff +#define BIT_BSSID1_1_8822C(x) \ + (((x) & BIT_MASK_BSSID1_1_8822C) << BIT_SHIFT_BSSID1_1_8822C) +#define BITS_BSSID1_1_8822C \ + (BIT_MASK_BSSID1_1_8822C << BIT_SHIFT_BSSID1_1_8822C) +#define BIT_CLEAR_BSSID1_1_8822C(x) ((x) & (~BITS_BSSID1_1_8822C)) +#define BIT_GET_BSSID1_1_8822C(x) \ + (((x) >> BIT_SHIFT_BSSID1_1_8822C) & BIT_MASK_BSSID1_1_8822C) +#define BIT_SET_BSSID1_1_8822C(x, v) \ + (BIT_CLEAR_BSSID1_1_8822C(x) | BIT_BSSID1_1_8822C(v)) + +/* 2 REG_BCN_PSR_RPT1_8822C */ + +#define BIT_SHIFT_DTIM_CNT1_8822C 24 +#define BIT_MASK_DTIM_CNT1_8822C 0xff +#define BIT_DTIM_CNT1_8822C(x) \ + (((x) & BIT_MASK_DTIM_CNT1_8822C) << BIT_SHIFT_DTIM_CNT1_8822C) +#define BITS_DTIM_CNT1_8822C \ + (BIT_MASK_DTIM_CNT1_8822C << BIT_SHIFT_DTIM_CNT1_8822C) +#define BIT_CLEAR_DTIM_CNT1_8822C(x) ((x) & (~BITS_DTIM_CNT1_8822C)) +#define BIT_GET_DTIM_CNT1_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_CNT1_8822C) & BIT_MASK_DTIM_CNT1_8822C) +#define BIT_SET_DTIM_CNT1_8822C(x, v) \ + (BIT_CLEAR_DTIM_CNT1_8822C(x) | BIT_DTIM_CNT1_8822C(v)) + +#define BIT_SHIFT_DTIM_PERIOD1_8822C 16 +#define BIT_MASK_DTIM_PERIOD1_8822C 0xff +#define BIT_DTIM_PERIOD1_8822C(x) \ + (((x) & BIT_MASK_DTIM_PERIOD1_8822C) << BIT_SHIFT_DTIM_PERIOD1_8822C) +#define BITS_DTIM_PERIOD1_8822C \ + (BIT_MASK_DTIM_PERIOD1_8822C << BIT_SHIFT_DTIM_PERIOD1_8822C) +#define BIT_CLEAR_DTIM_PERIOD1_8822C(x) ((x) & (~BITS_DTIM_PERIOD1_8822C)) +#define BIT_GET_DTIM_PERIOD1_8822C(x) \ + (((x) >> BIT_SHIFT_DTIM_PERIOD1_8822C) & BIT_MASK_DTIM_PERIOD1_8822C) +#define BIT_SET_DTIM_PERIOD1_8822C(x, v) \ + (BIT_CLEAR_DTIM_PERIOD1_8822C(x) | BIT_DTIM_PERIOD1_8822C(v)) + +#define BIT_DTIM1_8822C BIT(15) +#define BIT_TIM1_8822C BIT(14) +#define BIT_BCN_VALID_V2_8822C BIT(13) + +#define BIT_SHIFT_PS_AID_1_8822C 0 +#define BIT_MASK_PS_AID_1_8822C 0x7ff +#define BIT_PS_AID_1_8822C(x) \ + (((x) & BIT_MASK_PS_AID_1_8822C) << BIT_SHIFT_PS_AID_1_8822C) +#define BITS_PS_AID_1_8822C \ + (BIT_MASK_PS_AID_1_8822C << BIT_SHIFT_PS_AID_1_8822C) +#define BIT_CLEAR_PS_AID_1_8822C(x) ((x) & (~BITS_PS_AID_1_8822C)) +#define BIT_GET_PS_AID_1_8822C(x) \ + (((x) >> BIT_SHIFT_PS_AID_1_8822C) & BIT_MASK_PS_AID_1_8822C) +#define BIT_SET_PS_AID_1_8822C(x, v) \ + (BIT_CLEAR_PS_AID_1_8822C(x) | BIT_PS_AID_1_8822C(v)) + +/* 2 REG_ASSOCIATED_BFMEE_SEL_8822C */ +#define BIT_TXUSER_ID1_8822C BIT(25) + +#define BIT_SHIFT_AID1_8822C 16 +#define BIT_MASK_AID1_8822C 0x1ff +#define BIT_AID1_8822C(x) (((x) & BIT_MASK_AID1_8822C) << BIT_SHIFT_AID1_8822C) +#define BITS_AID1_8822C (BIT_MASK_AID1_8822C << BIT_SHIFT_AID1_8822C) +#define BIT_CLEAR_AID1_8822C(x) ((x) & (~BITS_AID1_8822C)) +#define BIT_GET_AID1_8822C(x) \ + (((x) >> BIT_SHIFT_AID1_8822C) & BIT_MASK_AID1_8822C) +#define BIT_SET_AID1_8822C(x, v) (BIT_CLEAR_AID1_8822C(x) | BIT_AID1_8822C(v)) + +#define BIT_TXUSER_ID0_8822C BIT(9) + +#define BIT_SHIFT_AID0_8822C 0 +#define BIT_MASK_AID0_8822C 0x1ff +#define BIT_AID0_8822C(x) (((x) & BIT_MASK_AID0_8822C) << BIT_SHIFT_AID0_8822C) +#define BITS_AID0_8822C (BIT_MASK_AID0_8822C << BIT_SHIFT_AID0_8822C) +#define BIT_CLEAR_AID0_8822C(x) ((x) & (~BITS_AID0_8822C)) +#define BIT_GET_AID0_8822C(x) \ + (((x) >> BIT_SHIFT_AID0_8822C) & BIT_MASK_AID0_8822C) +#define BIT_SET_AID0_8822C(x, v) (BIT_CLEAR_AID0_8822C(x) | BIT_AID0_8822C(v)) + +/* 2 REG_SND_PTCL_CTRL_8822C */ + +#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C 24 +#define BIT_MASK_NDP_RX_STANDBY_TIMER_8822C 0xff +#define BIT_NDP_RX_STANDBY_TIMER_8822C(x) \ + (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822C) \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C) +#define BITS_NDP_RX_STANDBY_TIMER_8822C \ + (BIT_MASK_NDP_RX_STANDBY_TIMER_8822C \ + << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C) +#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822C(x) \ + ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8822C)) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C) & \ + BIT_MASK_NDP_RX_STANDBY_TIMER_8822C) +#define BIT_SET_NDP_RX_STANDBY_TIMER_8822C(x, v) \ + (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822C(x) | \ + BIT_NDP_RX_STANDBY_TIMER_8822C(v)) + +#define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS_8822C BIT(23) +#define BIT_R_WMAC_CHK_UCNDPA_A2_DIS_8822C BIT(22) + +#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C 16 +#define BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C 0x3f +#define BIT_CSI_RPT_OFFSET_HT_V1_8822C(x) \ + (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C) \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C) +#define BITS_CSI_RPT_OFFSET_HT_V1_8822C \ + (BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C \ + << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C) +#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822C(x) \ + ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1_8822C)) +#define BIT_GET_CSI_RPT_OFFSET_HT_V1_8822C(x) \ + (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C) & \ + BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C) +#define BIT_SET_CSI_RPT_OFFSET_HT_V1_8822C(x, v) \ + (BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822C(x) | \ + BIT_CSI_RPT_OFFSET_HT_V1_8822C(v)) + +#define BIT_R_WMAC_OFFSET_RPTPOLL_EN_8822C BIT(15) +#define BIT_R_WMAC_CSI_CHKSUM_DIS_8822C BIT(14) + +#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C 8 +#define BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C 0x3f +#define BIT_R_WMAC_VHT_CATEGORY_V1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C) \ + << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C) +#define BITS_R_WMAC_VHT_CATEGORY_V1_8822C \ + (BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C \ + << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C) +#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1_8822C(x) \ + ((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1_8822C)) +#define BIT_GET_R_WMAC_VHT_CATEGORY_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C) & \ + BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C) +#define BIT_SET_R_WMAC_VHT_CATEGORY_V1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1_8822C(x) | \ + BIT_R_WMAC_VHT_CATEGORY_V1_8822C(v)) + +#define BIT_R_WMAC_USE_NSTS_8822C BIT(7) +#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822C BIT(6) +#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8822C BIT(5) +#define BIT_R_WMAC_BFPARAM_SEL_8822C BIT(4) +#define BIT_R_WMAC_CSISEQ_SEL_8822C BIT(3) +#define BIT_R_WMAC_CSI_WITHHTC_EN_8822C BIT(2) +#define BIT_R_WMAC_HT_NDPA_EN_8822C BIT(1) +#define BIT_R_WMAC_VHT_NDPA_EN_8822C BIT(0) + +/* 2 REG_RX_CSI_RPT_INFO_8822C */ +#define BIT_WRITE_ENABLE_8822C BIT(31) +#define BIT_WMAC_CHECK_SOUNDING_SEQ_8822C BIT(30) + +#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C 1 +#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C 0xffffff +#define BIT_VHTHT_MIMO_CTRL_FIELD_8822C(x) \ + (((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C) \ + << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C) +#define BITS_VHTHT_MIMO_CTRL_FIELD_8822C \ + (BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C \ + << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C) +#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8822C(x) \ + ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD_8822C)) +#define BIT_GET_VHTHT_MIMO_CTRL_FIELD_8822C(x) \ + (((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C) & \ + BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C) +#define BIT_SET_VHTHT_MIMO_CTRL_FIELD_8822C(x, v) \ + (BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8822C(x) | \ + BIT_VHTHT_MIMO_CTRL_FIELD_8822C(v)) + +#define BIT_CSI_INTERRUPT_STATUS_8822C BIT(0) + +/* 2 REG_NS_ARP_CTRL_8822C */ +#define BIT_R_WMAC_NSARP_RSPEN_8822C BIT(15) +#define BIT_R_WMAC_NSARP_RARP_8822C BIT(9) +#define BIT_R_WMAC_NSARP_RIPV6_8822C BIT(8) + +#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C 6 +#define BIT_MASK_R_WMAC_NSARP_MODEN_8822C 0x3 +#define BIT_R_WMAC_NSARP_MODEN_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822C) \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C) +#define BITS_R_WMAC_NSARP_MODEN_8822C \ + (BIT_MASK_R_WMAC_NSARP_MODEN_8822C \ + << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C) +#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8822C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_MODEN_8822C)) +#define BIT_GET_R_WMAC_NSARP_MODEN_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C) & \ + BIT_MASK_R_WMAC_NSARP_MODEN_8822C) +#define BIT_SET_R_WMAC_NSARP_MODEN_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_MODEN_8822C(x) | \ + BIT_R_WMAC_NSARP_MODEN_8822C(v)) + +#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C 4 +#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C 0x3 +#define BIT_R_WMAC_NSARP_RSPFTP_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C) +#define BITS_R_WMAC_NSARP_RSPFTP_8822C \ + (BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C \ + << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C) +#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8822C)) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C) & \ + BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C) +#define BIT_SET_R_WMAC_NSARP_RSPFTP_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822C(x) | \ + BIT_R_WMAC_NSARP_RSPFTP_8822C(v)) + +#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C 0 +#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C 0xf +#define BIT_R_WMAC_NSARP_RSPSEC_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C) \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C) +#define BITS_R_WMAC_NSARP_RSPSEC_8822C \ + (BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C \ + << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C) +#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822C(x) \ + ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8822C)) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C) & \ + BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C) +#define BIT_SET_R_WMAC_NSARP_RSPSEC_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822C(x) | \ + BIT_R_WMAC_NSARP_RSPSEC_8822C(v)) + +/* 2 REG_NS_ARP_INFO_8822C */ +#define BIT_REQ_IS_MCNS_8822C BIT(23) +#define BIT_REQ_IS_UCNS_8822C BIT(22) +#define BIT_REQ_IS_USNS_8822C BIT(21) +#define BIT_REQ_IS_ARP_8822C BIT(20) +#define BIT_EXPRSP_MH_WITHQC_8822C BIT(19) + +#define BIT_SHIFT_EXPRSP_SECTYPE_8822C 16 +#define BIT_MASK_EXPRSP_SECTYPE_8822C 0x7 +#define BIT_EXPRSP_SECTYPE_8822C(x) \ + (((x) & BIT_MASK_EXPRSP_SECTYPE_8822C) \ + << BIT_SHIFT_EXPRSP_SECTYPE_8822C) +#define BITS_EXPRSP_SECTYPE_8822C \ + (BIT_MASK_EXPRSP_SECTYPE_8822C << BIT_SHIFT_EXPRSP_SECTYPE_8822C) +#define BIT_CLEAR_EXPRSP_SECTYPE_8822C(x) ((x) & (~BITS_EXPRSP_SECTYPE_8822C)) +#define BIT_GET_EXPRSP_SECTYPE_8822C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822C) & \ + BIT_MASK_EXPRSP_SECTYPE_8822C) +#define BIT_SET_EXPRSP_SECTYPE_8822C(x, v) \ + (BIT_CLEAR_EXPRSP_SECTYPE_8822C(x) | BIT_EXPRSP_SECTYPE_8822C(v)) + +#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C 8 +#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C 0xff +#define BIT_EXPRSP_CHKSM_7_TO_0_8822C(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C) \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C) +#define BITS_EXPRSP_CHKSM_7_TO_0_8822C \ + (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C \ + << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C) +#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822C(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8822C)) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C) & \ + BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C) +#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8822C(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822C(x) | \ + BIT_EXPRSP_CHKSM_7_TO_0_8822C(v)) + +#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C 0 +#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C 0xff +#define BIT_EXPRSP_CHKSM_15_TO_8_8822C(x) \ + (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C) \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C) +#define BITS_EXPRSP_CHKSM_15_TO_8_8822C \ + (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C \ + << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C) +#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822C(x) \ + ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8822C)) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822C(x) \ + (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C) & \ + BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C) +#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8822C(x, v) \ + (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822C(x) | \ + BIT_EXPRSP_CHKSM_15_TO_8_8822C(v)) + +/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822C */ + +#define BIT_SHIFT_WMAC_ARPIP_8822C 0 +#define BIT_MASK_WMAC_ARPIP_8822C 0xffffffffL +#define BIT_WMAC_ARPIP_8822C(x) \ + (((x) & BIT_MASK_WMAC_ARPIP_8822C) << BIT_SHIFT_WMAC_ARPIP_8822C) +#define BITS_WMAC_ARPIP_8822C \ + (BIT_MASK_WMAC_ARPIP_8822C << BIT_SHIFT_WMAC_ARPIP_8822C) +#define BIT_CLEAR_WMAC_ARPIP_8822C(x) ((x) & (~BITS_WMAC_ARPIP_8822C)) +#define BIT_GET_WMAC_ARPIP_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_ARPIP_8822C) & BIT_MASK_WMAC_ARPIP_8822C) +#define BIT_SET_WMAC_ARPIP_8822C(x, v) \ + (BIT_CLEAR_WMAC_ARPIP_8822C(x) | BIT_WMAC_ARPIP_8822C(v)) + +/* 2 REG_BEAMFORMING_INFO_NSARP_8822C */ + +#define BIT_SHIFT_UPD_BFMEE_USERID_8822C 13 +#define BIT_MASK_UPD_BFMEE_USERID_8822C 0x7 +#define BIT_UPD_BFMEE_USERID_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_USERID_8822C) \ + << BIT_SHIFT_UPD_BFMEE_USERID_8822C) +#define BITS_UPD_BFMEE_USERID_8822C \ + (BIT_MASK_UPD_BFMEE_USERID_8822C << BIT_SHIFT_UPD_BFMEE_USERID_8822C) +#define BIT_CLEAR_UPD_BFMEE_USERID_8822C(x) \ + ((x) & (~BITS_UPD_BFMEE_USERID_8822C)) +#define BIT_GET_UPD_BFMEE_USERID_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_USERID_8822C) & \ + BIT_MASK_UPD_BFMEE_USERID_8822C) +#define BIT_SET_UPD_BFMEE_USERID_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_USERID_8822C(x) | BIT_UPD_BFMEE_USERID_8822C(v)) + +#define BIT_UPD_BFMEE_FBTP_8822C BIT(12) + +#define BIT_SHIFT_UPD_BFMEE_BW_8822C 0 +#define BIT_MASK_UPD_BFMEE_BW_8822C 0xfff +#define BIT_UPD_BFMEE_BW_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_BW_8822C) << BIT_SHIFT_UPD_BFMEE_BW_8822C) +#define BITS_UPD_BFMEE_BW_8822C \ + (BIT_MASK_UPD_BFMEE_BW_8822C << BIT_SHIFT_UPD_BFMEE_BW_8822C) +#define BIT_CLEAR_UPD_BFMEE_BW_8822C(x) ((x) & (~BITS_UPD_BFMEE_BW_8822C)) +#define BIT_GET_UPD_BFMEE_BW_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_BW_8822C) & BIT_MASK_UPD_BFMEE_BW_8822C) +#define BIT_SET_UPD_BFMEE_BW_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_BW_8822C(x) | BIT_UPD_BFMEE_BW_8822C(v)) + +#define BIT_SHIFT_UPD_BFMEE_CB_8822C 8 +#define BIT_MASK_UPD_BFMEE_CB_8822C 0x3 +#define BIT_UPD_BFMEE_CB_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_CB_8822C) << BIT_SHIFT_UPD_BFMEE_CB_8822C) +#define BITS_UPD_BFMEE_CB_8822C \ + (BIT_MASK_UPD_BFMEE_CB_8822C << BIT_SHIFT_UPD_BFMEE_CB_8822C) +#define BIT_CLEAR_UPD_BFMEE_CB_8822C(x) ((x) & (~BITS_UPD_BFMEE_CB_8822C)) +#define BIT_GET_UPD_BFMEE_CB_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_CB_8822C) & BIT_MASK_UPD_BFMEE_CB_8822C) +#define BIT_SET_UPD_BFMEE_CB_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_CB_8822C(x) | BIT_UPD_BFMEE_CB_8822C(v)) + +#define BIT_SHIFT_UPD_BFMEE_NG_8822C 6 +#define BIT_MASK_UPD_BFMEE_NG_8822C 0x3 +#define BIT_UPD_BFMEE_NG_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NG_8822C) << BIT_SHIFT_UPD_BFMEE_NG_8822C) +#define BITS_UPD_BFMEE_NG_8822C \ + (BIT_MASK_UPD_BFMEE_NG_8822C << BIT_SHIFT_UPD_BFMEE_NG_8822C) +#define BIT_CLEAR_UPD_BFMEE_NG_8822C(x) ((x) & (~BITS_UPD_BFMEE_NG_8822C)) +#define BIT_GET_UPD_BFMEE_NG_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NG_8822C) & BIT_MASK_UPD_BFMEE_NG_8822C) +#define BIT_SET_UPD_BFMEE_NG_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NG_8822C(x) | BIT_UPD_BFMEE_NG_8822C(v)) + +#define BIT_SHIFT_UPD_BFMEE_NR_8822C 3 +#define BIT_MASK_UPD_BFMEE_NR_8822C 0x7 +#define BIT_UPD_BFMEE_NR_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NR_8822C) << BIT_SHIFT_UPD_BFMEE_NR_8822C) +#define BITS_UPD_BFMEE_NR_8822C \ + (BIT_MASK_UPD_BFMEE_NR_8822C << BIT_SHIFT_UPD_BFMEE_NR_8822C) +#define BIT_CLEAR_UPD_BFMEE_NR_8822C(x) ((x) & (~BITS_UPD_BFMEE_NR_8822C)) +#define BIT_GET_UPD_BFMEE_NR_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NR_8822C) & BIT_MASK_UPD_BFMEE_NR_8822C) +#define BIT_SET_UPD_BFMEE_NR_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NR_8822C(x) | BIT_UPD_BFMEE_NR_8822C(v)) + +#define BIT_SHIFT_UPD_BFMEE_NC_8822C 0 +#define BIT_MASK_UPD_BFMEE_NC_8822C 0x7 +#define BIT_UPD_BFMEE_NC_8822C(x) \ + (((x) & BIT_MASK_UPD_BFMEE_NC_8822C) << BIT_SHIFT_UPD_BFMEE_NC_8822C) +#define BITS_UPD_BFMEE_NC_8822C \ + (BIT_MASK_UPD_BFMEE_NC_8822C << BIT_SHIFT_UPD_BFMEE_NC_8822C) +#define BIT_CLEAR_UPD_BFMEE_NC_8822C(x) ((x) & (~BITS_UPD_BFMEE_NC_8822C)) +#define BIT_GET_UPD_BFMEE_NC_8822C(x) \ + (((x) >> BIT_SHIFT_UPD_BFMEE_NC_8822C) & BIT_MASK_UPD_BFMEE_NC_8822C) +#define BIT_SET_UPD_BFMEE_NC_8822C(x, v) \ + (BIT_CLEAR_UPD_BFMEE_NC_8822C(x) | BIT_UPD_BFMEE_NC_8822C(v)) + +/* 2 REG_IPV6_8822C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_0_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C) +#define BITS_R_WMAC_IPV6_MYIPAD_0_8822C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8822C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8822C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8822C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_0_8822C(v)) + +/* 2 REG_IPV6_1_8822C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C) +#define BITS_R_WMAC_IPV6_MYIPAD_1_8822C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8822C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8822C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8822C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_1_8822C(v)) + +/* 2 REG_IPV6_2_8822C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_2_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C) +#define BITS_R_WMAC_IPV6_MYIPAD_2_8822C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8822C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8822C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8822C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_2_8822C(v)) + +/* 2 REG_IPV6_3_8822C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_3_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C) \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C) +#define BITS_R_WMAC_IPV6_MYIPAD_3_8822C \ + (BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C \ + << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C) +#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8822C(x) \ + ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8822C)) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C) & \ + BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C) +#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8822C(x) | \ + BIT_R_WMAC_IPV6_MYIPAD_3_8822C(v)) + +/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822C */ + +#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C 4 +#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C 0xf +#define BIT_R_WMAC_CTX_SUBTYPE_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C) \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C) +#define BITS_R_WMAC_CTX_SUBTYPE_8822C \ + (BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C \ + << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C) +#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822C(x) \ + ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8822C)) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C) & \ + BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C) +#define BIT_SET_R_WMAC_CTX_SUBTYPE_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822C(x) | \ + BIT_R_WMAC_CTX_SUBTYPE_8822C(v)) + +#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C 0 +#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C 0xf +#define BIT_R_WMAC_RTX_SUBTYPE_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C) \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C) +#define BITS_R_WMAC_RTX_SUBTYPE_8822C \ + (BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C \ + << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C) +#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822C(x) \ + ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8822C)) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C) & \ + BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C) +#define BIT_SET_R_WMAC_RTX_SUBTYPE_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822C(x) | \ + BIT_R_WMAC_RTX_SUBTYPE_8822C(v)) + +/* 2 REG_WMAC_SWAES_DIO_B63_B32_8822C */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C 0 +#define BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B63_B32_8822C(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C) +#define BITS_WMAC_SWAES_DIO_B63_B32_8822C \ + (BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C \ + << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C) +#define BIT_CLEAR_WMAC_SWAES_DIO_B63_B32_8822C(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B63_B32_8822C)) +#define BIT_GET_WMAC_SWAES_DIO_B63_B32_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C) & \ + BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C) +#define BIT_SET_WMAC_SWAES_DIO_B63_B32_8822C(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B63_B32_8822C(x) | \ + BIT_WMAC_SWAES_DIO_B63_B32_8822C(v)) + +/* 2 REG_WMAC_SWAES_DIO_B95_B64_8822C */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C 0 +#define BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B95_B64_8822C(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C) +#define BITS_WMAC_SWAES_DIO_B95_B64_8822C \ + (BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C \ + << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C) +#define BIT_CLEAR_WMAC_SWAES_DIO_B95_B64_8822C(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B95_B64_8822C)) +#define BIT_GET_WMAC_SWAES_DIO_B95_B64_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C) & \ + BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C) +#define BIT_SET_WMAC_SWAES_DIO_B95_B64_8822C(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B95_B64_8822C(x) | \ + BIT_WMAC_SWAES_DIO_B95_B64_8822C(v)) + +/* 2 REG_WMAC_SWAES_DIO_B127_B96_8822C */ + +#define BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C 0 +#define BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C 0xffffffffL +#define BIT_WMAC_SWAES_DIO_B127_B96_8822C(x) \ + (((x) & BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C) \ + << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C) +#define BITS_WMAC_SWAES_DIO_B127_B96_8822C \ + (BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C \ + << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C) +#define BIT_CLEAR_WMAC_SWAES_DIO_B127_B96_8822C(x) \ + ((x) & (~BITS_WMAC_SWAES_DIO_B127_B96_8822C)) +#define BIT_GET_WMAC_SWAES_DIO_B127_B96_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C) & \ + BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C) +#define BIT_SET_WMAC_SWAES_DIO_B127_B96_8822C(x, v) \ + (BIT_CLEAR_WMAC_SWAES_DIO_B127_B96_8822C(x) | \ + BIT_WMAC_SWAES_DIO_B127_B96_8822C(v)) + +/* 2 REG_WMAC_SWAES_CFG_8822C */ + +/* 2 REG_BT_COEX_V2_8822C */ +#define BIT_GNT_BT_POLARITY_8822C BIT(12) +#define BIT_GNT_BT_BYPASS_PRIORITY_8822C BIT(8) + +#define BIT_SHIFT_TIMER_8822C 0 +#define BIT_MASK_TIMER_8822C 0xff +#define BIT_TIMER_8822C(x) \ + (((x) & BIT_MASK_TIMER_8822C) << BIT_SHIFT_TIMER_8822C) +#define BITS_TIMER_8822C (BIT_MASK_TIMER_8822C << BIT_SHIFT_TIMER_8822C) +#define BIT_CLEAR_TIMER_8822C(x) ((x) & (~BITS_TIMER_8822C)) +#define BIT_GET_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_TIMER_8822C) & BIT_MASK_TIMER_8822C) +#define BIT_SET_TIMER_8822C(x, v) \ + (BIT_CLEAR_TIMER_8822C(x) | BIT_TIMER_8822C(v)) + +/* 2 REG_BT_COEX_8822C */ +#define BIT_R_GNT_BT_RFC_SW_8822C BIT(12) +#define BIT_R_GNT_BT_RFC_SW_EN_8822C BIT(11) +#define BIT_R_GNT_BT_BB_SW_8822C BIT(10) +#define BIT_R_GNT_BT_BB_SW_EN_8822C BIT(9) +#define BIT_R_BT_CNT_THREN_8822C BIT(8) + +#define BIT_SHIFT_R_BT_CNT_THR_8822C 0 +#define BIT_MASK_R_BT_CNT_THR_8822C 0xff +#define BIT_R_BT_CNT_THR_8822C(x) \ + (((x) & BIT_MASK_R_BT_CNT_THR_8822C) << BIT_SHIFT_R_BT_CNT_THR_8822C) +#define BITS_R_BT_CNT_THR_8822C \ + (BIT_MASK_R_BT_CNT_THR_8822C << BIT_SHIFT_R_BT_CNT_THR_8822C) +#define BIT_CLEAR_R_BT_CNT_THR_8822C(x) ((x) & (~BITS_R_BT_CNT_THR_8822C)) +#define BIT_GET_R_BT_CNT_THR_8822C(x) \ + (((x) >> BIT_SHIFT_R_BT_CNT_THR_8822C) & BIT_MASK_R_BT_CNT_THR_8822C) +#define BIT_SET_R_BT_CNT_THR_8822C(x, v) \ + (BIT_CLEAR_R_BT_CNT_THR_8822C(x) | BIT_R_BT_CNT_THR_8822C(v)) + +/* 2 REG_WLAN_ACT_MASK_CTRL_8822C */ + +#define BIT_SHIFT_RXMYRTS_NAV_V1_8822C 8 +#define BIT_MASK_RXMYRTS_NAV_V1_8822C 0xff +#define BIT_RXMYRTS_NAV_V1_8822C(x) \ + (((x) & BIT_MASK_RXMYRTS_NAV_V1_8822C) \ + << BIT_SHIFT_RXMYRTS_NAV_V1_8822C) +#define BITS_RXMYRTS_NAV_V1_8822C \ + (BIT_MASK_RXMYRTS_NAV_V1_8822C << BIT_SHIFT_RXMYRTS_NAV_V1_8822C) +#define BIT_CLEAR_RXMYRTS_NAV_V1_8822C(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8822C)) +#define BIT_GET_RXMYRTS_NAV_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822C) & \ + BIT_MASK_RXMYRTS_NAV_V1_8822C) +#define BIT_SET_RXMYRTS_NAV_V1_8822C(x, v) \ + (BIT_CLEAR_RXMYRTS_NAV_V1_8822C(x) | BIT_RXMYRTS_NAV_V1_8822C(v)) + +#define BIT_SHIFT_RTSRST_V1_8822C 0 +#define BIT_MASK_RTSRST_V1_8822C 0xff +#define BIT_RTSRST_V1_8822C(x) \ + (((x) & BIT_MASK_RTSRST_V1_8822C) << BIT_SHIFT_RTSRST_V1_8822C) +#define BITS_RTSRST_V1_8822C \ + (BIT_MASK_RTSRST_V1_8822C << BIT_SHIFT_RTSRST_V1_8822C) +#define BIT_CLEAR_RTSRST_V1_8822C(x) ((x) & (~BITS_RTSRST_V1_8822C)) +#define BIT_GET_RTSRST_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RTSRST_V1_8822C) & BIT_MASK_RTSRST_V1_8822C) +#define BIT_SET_RTSRST_V1_8822C(x, v) \ + (BIT_CLEAR_RTSRST_V1_8822C(x) | BIT_RTSRST_V1_8822C(v)) + +/* 2 REG_WLAN_ACT_MASK_CTRL_1_8822C */ +#define BIT_WLRX_TER_BY_CTL_1_8822C BIT(11) +#define BIT_WLRX_TER_BY_AD_1_8822C BIT(10) +#define BIT_ANT_DIVERSITY_SEL_1_8822C BIT(9) +#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8822C BIT(8) +#define BIT_WLACT_LOW_GNTWL_EN_1_8822C BIT(2) +#define BIT_WLACT_HIGH_GNTBT_EN_1_8822C BIT(1) +#define BIT_NAV_UPPER_1_V1_8822C BIT(0) + +/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822C */ + +#define BIT_SHIFT_BT_STAT_DELAY_8822C 12 +#define BIT_MASK_BT_STAT_DELAY_8822C 0xf +#define BIT_BT_STAT_DELAY_8822C(x) \ + (((x) & BIT_MASK_BT_STAT_DELAY_8822C) << BIT_SHIFT_BT_STAT_DELAY_8822C) +#define BITS_BT_STAT_DELAY_8822C \ + (BIT_MASK_BT_STAT_DELAY_8822C << BIT_SHIFT_BT_STAT_DELAY_8822C) +#define BIT_CLEAR_BT_STAT_DELAY_8822C(x) ((x) & (~BITS_BT_STAT_DELAY_8822C)) +#define BIT_GET_BT_STAT_DELAY_8822C(x) \ + (((x) >> BIT_SHIFT_BT_STAT_DELAY_8822C) & BIT_MASK_BT_STAT_DELAY_8822C) +#define BIT_SET_BT_STAT_DELAY_8822C(x, v) \ + (BIT_CLEAR_BT_STAT_DELAY_8822C(x) | BIT_BT_STAT_DELAY_8822C(v)) + +#define BIT_SHIFT_BT_TRX_INIT_DETECT_8822C 8 +#define BIT_MASK_BT_TRX_INIT_DETECT_8822C 0xf +#define BIT_BT_TRX_INIT_DETECT_8822C(x) \ + (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822C) \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8822C) +#define BITS_BT_TRX_INIT_DETECT_8822C \ + (BIT_MASK_BT_TRX_INIT_DETECT_8822C \ + << BIT_SHIFT_BT_TRX_INIT_DETECT_8822C) +#define BIT_CLEAR_BT_TRX_INIT_DETECT_8822C(x) \ + ((x) & (~BITS_BT_TRX_INIT_DETECT_8822C)) +#define BIT_GET_BT_TRX_INIT_DETECT_8822C(x) \ + (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822C) & \ + BIT_MASK_BT_TRX_INIT_DETECT_8822C) +#define BIT_SET_BT_TRX_INIT_DETECT_8822C(x, v) \ + (BIT_CLEAR_BT_TRX_INIT_DETECT_8822C(x) | \ + BIT_BT_TRX_INIT_DETECT_8822C(v)) + +#define BIT_SHIFT_BT_PRI_DETECT_TO_8822C 4 +#define BIT_MASK_BT_PRI_DETECT_TO_8822C 0xf +#define BIT_BT_PRI_DETECT_TO_8822C(x) \ + (((x) & BIT_MASK_BT_PRI_DETECT_TO_8822C) \ + << BIT_SHIFT_BT_PRI_DETECT_TO_8822C) +#define BITS_BT_PRI_DETECT_TO_8822C \ + (BIT_MASK_BT_PRI_DETECT_TO_8822C << BIT_SHIFT_BT_PRI_DETECT_TO_8822C) +#define BIT_CLEAR_BT_PRI_DETECT_TO_8822C(x) \ + ((x) & (~BITS_BT_PRI_DETECT_TO_8822C)) +#define BIT_GET_BT_PRI_DETECT_TO_8822C(x) \ + (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822C) & \ + BIT_MASK_BT_PRI_DETECT_TO_8822C) +#define BIT_SET_BT_PRI_DETECT_TO_8822C(x, v) \ + (BIT_CLEAR_BT_PRI_DETECT_TO_8822C(x) | BIT_BT_PRI_DETECT_TO_8822C(v)) + +#define BIT_R_GRANTALL_WLMASK_8822C BIT(3) +#define BIT_STATIS_BT_EN_8822C BIT(2) +#define BIT_WL_ACT_MASK_ENABLE_8822C BIT(1) +#define BIT_ENHANCED_BT_8822C BIT(0) + +/* 2 REG_BT_ACT_STATISTICS_8822C */ + +#define BIT_SHIFT_STATIS_BT_HI_RX_8822C 16 +#define BIT_MASK_STATIS_BT_HI_RX_8822C 0xffff +#define BIT_STATIS_BT_HI_RX_8822C(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_RX_8822C) \ + << BIT_SHIFT_STATIS_BT_HI_RX_8822C) +#define BITS_STATIS_BT_HI_RX_8822C \ + (BIT_MASK_STATIS_BT_HI_RX_8822C << BIT_SHIFT_STATIS_BT_HI_RX_8822C) +#define BIT_CLEAR_STATIS_BT_HI_RX_8822C(x) ((x) & (~BITS_STATIS_BT_HI_RX_8822C)) +#define BIT_GET_STATIS_BT_HI_RX_8822C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822C) & \ + BIT_MASK_STATIS_BT_HI_RX_8822C) +#define BIT_SET_STATIS_BT_HI_RX_8822C(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_RX_8822C(x) | BIT_STATIS_BT_HI_RX_8822C(v)) + +#define BIT_SHIFT_STATIS_BT_HI_TX_8822C 0 +#define BIT_MASK_STATIS_BT_HI_TX_8822C 0xffff +#define BIT_STATIS_BT_HI_TX_8822C(x) \ + (((x) & BIT_MASK_STATIS_BT_HI_TX_8822C) \ + << BIT_SHIFT_STATIS_BT_HI_TX_8822C) +#define BITS_STATIS_BT_HI_TX_8822C \ + (BIT_MASK_STATIS_BT_HI_TX_8822C << BIT_SHIFT_STATIS_BT_HI_TX_8822C) +#define BIT_CLEAR_STATIS_BT_HI_TX_8822C(x) ((x) & (~BITS_STATIS_BT_HI_TX_8822C)) +#define BIT_GET_STATIS_BT_HI_TX_8822C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822C) & \ + BIT_MASK_STATIS_BT_HI_TX_8822C) +#define BIT_SET_STATIS_BT_HI_TX_8822C(x, v) \ + (BIT_CLEAR_STATIS_BT_HI_TX_8822C(x) | BIT_STATIS_BT_HI_TX_8822C(v)) + +/* 2 REG_BT_ACT_STATISTICS_1_8822C */ + +#define BIT_SHIFT_STATIS_BT_LO_RX_1_8822C 16 +#define BIT_MASK_STATIS_BT_LO_RX_1_8822C 0xffff +#define BIT_STATIS_BT_LO_RX_1_8822C(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8822C) \ + << BIT_SHIFT_STATIS_BT_LO_RX_1_8822C) +#define BITS_STATIS_BT_LO_RX_1_8822C \ + (BIT_MASK_STATIS_BT_LO_RX_1_8822C << BIT_SHIFT_STATIS_BT_LO_RX_1_8822C) +#define BIT_CLEAR_STATIS_BT_LO_RX_1_8822C(x) \ + ((x) & (~BITS_STATIS_BT_LO_RX_1_8822C)) +#define BIT_GET_STATIS_BT_LO_RX_1_8822C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8822C) & \ + BIT_MASK_STATIS_BT_LO_RX_1_8822C) +#define BIT_SET_STATIS_BT_LO_RX_1_8822C(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_RX_1_8822C(x) | BIT_STATIS_BT_LO_RX_1_8822C(v)) + +#define BIT_SHIFT_STATIS_BT_LO_TX_1_8822C 0 +#define BIT_MASK_STATIS_BT_LO_TX_1_8822C 0xffff +#define BIT_STATIS_BT_LO_TX_1_8822C(x) \ + (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8822C) \ + << BIT_SHIFT_STATIS_BT_LO_TX_1_8822C) +#define BITS_STATIS_BT_LO_TX_1_8822C \ + (BIT_MASK_STATIS_BT_LO_TX_1_8822C << BIT_SHIFT_STATIS_BT_LO_TX_1_8822C) +#define BIT_CLEAR_STATIS_BT_LO_TX_1_8822C(x) \ + ((x) & (~BITS_STATIS_BT_LO_TX_1_8822C)) +#define BIT_GET_STATIS_BT_LO_TX_1_8822C(x) \ + (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8822C) & \ + BIT_MASK_STATIS_BT_LO_TX_1_8822C) +#define BIT_SET_STATIS_BT_LO_TX_1_8822C(x, v) \ + (BIT_CLEAR_STATIS_BT_LO_TX_1_8822C(x) | BIT_STATIS_BT_LO_TX_1_8822C(v)) + +/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822C */ + +#define BIT_SHIFT_R_BT_CMD_RPT_8822C 16 +#define BIT_MASK_R_BT_CMD_RPT_8822C 0xffff +#define BIT_R_BT_CMD_RPT_8822C(x) \ + (((x) & BIT_MASK_R_BT_CMD_RPT_8822C) << BIT_SHIFT_R_BT_CMD_RPT_8822C) +#define BITS_R_BT_CMD_RPT_8822C \ + (BIT_MASK_R_BT_CMD_RPT_8822C << BIT_SHIFT_R_BT_CMD_RPT_8822C) +#define BIT_CLEAR_R_BT_CMD_RPT_8822C(x) ((x) & (~BITS_R_BT_CMD_RPT_8822C)) +#define BIT_GET_R_BT_CMD_RPT_8822C(x) \ + (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822C) & BIT_MASK_R_BT_CMD_RPT_8822C) +#define BIT_SET_R_BT_CMD_RPT_8822C(x, v) \ + (BIT_CLEAR_R_BT_CMD_RPT_8822C(x) | BIT_R_BT_CMD_RPT_8822C(v)) + +#define BIT_SHIFT_R_RPT_FROM_BT_8822C 8 +#define BIT_MASK_R_RPT_FROM_BT_8822C 0xff +#define BIT_R_RPT_FROM_BT_8822C(x) \ + (((x) & BIT_MASK_R_RPT_FROM_BT_8822C) << BIT_SHIFT_R_RPT_FROM_BT_8822C) +#define BITS_R_RPT_FROM_BT_8822C \ + (BIT_MASK_R_RPT_FROM_BT_8822C << BIT_SHIFT_R_RPT_FROM_BT_8822C) +#define BIT_CLEAR_R_RPT_FROM_BT_8822C(x) ((x) & (~BITS_R_RPT_FROM_BT_8822C)) +#define BIT_GET_R_RPT_FROM_BT_8822C(x) \ + (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822C) & BIT_MASK_R_RPT_FROM_BT_8822C) +#define BIT_SET_R_RPT_FROM_BT_8822C(x, v) \ + (BIT_CLEAR_R_RPT_FROM_BT_8822C(x) | BIT_R_RPT_FROM_BT_8822C(v)) + +#define BIT_SHIFT_BT_HID_ISR_SET_8822C 6 +#define BIT_MASK_BT_HID_ISR_SET_8822C 0x3 +#define BIT_BT_HID_ISR_SET_8822C(x) \ + (((x) & BIT_MASK_BT_HID_ISR_SET_8822C) \ + << BIT_SHIFT_BT_HID_ISR_SET_8822C) +#define BITS_BT_HID_ISR_SET_8822C \ + (BIT_MASK_BT_HID_ISR_SET_8822C << BIT_SHIFT_BT_HID_ISR_SET_8822C) +#define BIT_CLEAR_BT_HID_ISR_SET_8822C(x) ((x) & (~BITS_BT_HID_ISR_SET_8822C)) +#define BIT_GET_BT_HID_ISR_SET_8822C(x) \ + (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822C) & \ + BIT_MASK_BT_HID_ISR_SET_8822C) +#define BIT_SET_BT_HID_ISR_SET_8822C(x, v) \ + (BIT_CLEAR_BT_HID_ISR_SET_8822C(x) | BIT_BT_HID_ISR_SET_8822C(v)) + +#define BIT_TDMA_BT_START_NOTIFY_8822C BIT(5) +#define BIT_ENABLE_TDMA_FW_MODE_8822C BIT(4) +#define BIT_ENABLE_PTA_TDMA_MODE_8822C BIT(3) +#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8822C BIT(2) +#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8822C BIT(1) +#define BIT_RTK_BT_ENABLE_8822C BIT(0) + +/* 2 REG_BT_STATUS_REPORT_REGISTER_8822C */ + +#define BIT_SHIFT_BT_PROFILE_8822C 24 +#define BIT_MASK_BT_PROFILE_8822C 0xff +#define BIT_BT_PROFILE_8822C(x) \ + (((x) & BIT_MASK_BT_PROFILE_8822C) << BIT_SHIFT_BT_PROFILE_8822C) +#define BITS_BT_PROFILE_8822C \ + (BIT_MASK_BT_PROFILE_8822C << BIT_SHIFT_BT_PROFILE_8822C) +#define BIT_CLEAR_BT_PROFILE_8822C(x) ((x) & (~BITS_BT_PROFILE_8822C)) +#define BIT_GET_BT_PROFILE_8822C(x) \ + (((x) >> BIT_SHIFT_BT_PROFILE_8822C) & BIT_MASK_BT_PROFILE_8822C) +#define BIT_SET_BT_PROFILE_8822C(x, v) \ + (BIT_CLEAR_BT_PROFILE_8822C(x) | BIT_BT_PROFILE_8822C(v)) + +#define BIT_SHIFT_BT_POWER_8822C 16 +#define BIT_MASK_BT_POWER_8822C 0xff +#define BIT_BT_POWER_8822C(x) \ + (((x) & BIT_MASK_BT_POWER_8822C) << BIT_SHIFT_BT_POWER_8822C) +#define BITS_BT_POWER_8822C \ + (BIT_MASK_BT_POWER_8822C << BIT_SHIFT_BT_POWER_8822C) +#define BIT_CLEAR_BT_POWER_8822C(x) ((x) & (~BITS_BT_POWER_8822C)) +#define BIT_GET_BT_POWER_8822C(x) \ + (((x) >> BIT_SHIFT_BT_POWER_8822C) & BIT_MASK_BT_POWER_8822C) +#define BIT_SET_BT_POWER_8822C(x, v) \ + (BIT_CLEAR_BT_POWER_8822C(x) | BIT_BT_POWER_8822C(v)) + +#define BIT_SHIFT_BT_PREDECT_STATUS_8822C 8 +#define BIT_MASK_BT_PREDECT_STATUS_8822C 0xff +#define BIT_BT_PREDECT_STATUS_8822C(x) \ + (((x) & BIT_MASK_BT_PREDECT_STATUS_8822C) \ + << BIT_SHIFT_BT_PREDECT_STATUS_8822C) +#define BITS_BT_PREDECT_STATUS_8822C \ + (BIT_MASK_BT_PREDECT_STATUS_8822C << BIT_SHIFT_BT_PREDECT_STATUS_8822C) +#define BIT_CLEAR_BT_PREDECT_STATUS_8822C(x) \ + ((x) & (~BITS_BT_PREDECT_STATUS_8822C)) +#define BIT_GET_BT_PREDECT_STATUS_8822C(x) \ + (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822C) & \ + BIT_MASK_BT_PREDECT_STATUS_8822C) +#define BIT_SET_BT_PREDECT_STATUS_8822C(x, v) \ + (BIT_CLEAR_BT_PREDECT_STATUS_8822C(x) | BIT_BT_PREDECT_STATUS_8822C(v)) + +#define BIT_SHIFT_BT_CMD_INFO_8822C 0 +#define BIT_MASK_BT_CMD_INFO_8822C 0xff +#define BIT_BT_CMD_INFO_8822C(x) \ + (((x) & BIT_MASK_BT_CMD_INFO_8822C) << BIT_SHIFT_BT_CMD_INFO_8822C) +#define BITS_BT_CMD_INFO_8822C \ + (BIT_MASK_BT_CMD_INFO_8822C << BIT_SHIFT_BT_CMD_INFO_8822C) +#define BIT_CLEAR_BT_CMD_INFO_8822C(x) ((x) & (~BITS_BT_CMD_INFO_8822C)) +#define BIT_GET_BT_CMD_INFO_8822C(x) \ + (((x) >> BIT_SHIFT_BT_CMD_INFO_8822C) & BIT_MASK_BT_CMD_INFO_8822C) +#define BIT_SET_BT_CMD_INFO_8822C(x, v) \ + (BIT_CLEAR_BT_CMD_INFO_8822C(x) | BIT_BT_CMD_INFO_8822C(v)) + +/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822C */ +#define BIT_EN_MAC_NULL_PKT_NOTIFY_8822C BIT(31) +#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8822C BIT(30) +#define BIT_EN_BT_STSTUS_RPT_8822C BIT(29) +#define BIT_EN_BT_POWER_8822C BIT(28) +#define BIT_EN_BT_CHANNEL_8822C BIT(27) +#define BIT_EN_BT_SLOT_CHANGE_8822C BIT(26) +#define BIT_EN_BT_PROFILE_OR_HID_8822C BIT(25) +#define BIT_WLAN_RPT_NOTIFY_8822C BIT(24) + +#define BIT_SHIFT_WLAN_RPT_DATA_8822C 16 +#define BIT_MASK_WLAN_RPT_DATA_8822C 0xff +#define BIT_WLAN_RPT_DATA_8822C(x) \ + (((x) & BIT_MASK_WLAN_RPT_DATA_8822C) << BIT_SHIFT_WLAN_RPT_DATA_8822C) +#define BITS_WLAN_RPT_DATA_8822C \ + (BIT_MASK_WLAN_RPT_DATA_8822C << BIT_SHIFT_WLAN_RPT_DATA_8822C) +#define BIT_CLEAR_WLAN_RPT_DATA_8822C(x) ((x) & (~BITS_WLAN_RPT_DATA_8822C)) +#define BIT_GET_WLAN_RPT_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822C) & BIT_MASK_WLAN_RPT_DATA_8822C) +#define BIT_SET_WLAN_RPT_DATA_8822C(x, v) \ + (BIT_CLEAR_WLAN_RPT_DATA_8822C(x) | BIT_WLAN_RPT_DATA_8822C(v)) + +#define BIT_SHIFT_CMD_ID_8822C 8 +#define BIT_MASK_CMD_ID_8822C 0xff +#define BIT_CMD_ID_8822C(x) \ + (((x) & BIT_MASK_CMD_ID_8822C) << BIT_SHIFT_CMD_ID_8822C) +#define BITS_CMD_ID_8822C (BIT_MASK_CMD_ID_8822C << BIT_SHIFT_CMD_ID_8822C) +#define BIT_CLEAR_CMD_ID_8822C(x) ((x) & (~BITS_CMD_ID_8822C)) +#define BIT_GET_CMD_ID_8822C(x) \ + (((x) >> BIT_SHIFT_CMD_ID_8822C) & BIT_MASK_CMD_ID_8822C) +#define BIT_SET_CMD_ID_8822C(x, v) \ + (BIT_CLEAR_CMD_ID_8822C(x) | BIT_CMD_ID_8822C(v)) + +#define BIT_SHIFT_BT_DATA_8822C 0 +#define BIT_MASK_BT_DATA_8822C 0xff +#define BIT_BT_DATA_8822C(x) \ + (((x) & BIT_MASK_BT_DATA_8822C) << BIT_SHIFT_BT_DATA_8822C) +#define BITS_BT_DATA_8822C (BIT_MASK_BT_DATA_8822C << BIT_SHIFT_BT_DATA_8822C) +#define BIT_CLEAR_BT_DATA_8822C(x) ((x) & (~BITS_BT_DATA_8822C)) +#define BIT_GET_BT_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_BT_DATA_8822C) & BIT_MASK_BT_DATA_8822C) +#define BIT_SET_BT_DATA_8822C(x, v) \ + (BIT_CLEAR_BT_DATA_8822C(x) | BIT_BT_DATA_8822C(v)) + +/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822C */ + +#define BIT_SHIFT_WLAN_RPT_TO_8822C 0 +#define BIT_MASK_WLAN_RPT_TO_8822C 0xff +#define BIT_WLAN_RPT_TO_8822C(x) \ + (((x) & BIT_MASK_WLAN_RPT_TO_8822C) << BIT_SHIFT_WLAN_RPT_TO_8822C) +#define BITS_WLAN_RPT_TO_8822C \ + (BIT_MASK_WLAN_RPT_TO_8822C << BIT_SHIFT_WLAN_RPT_TO_8822C) +#define BIT_CLEAR_WLAN_RPT_TO_8822C(x) ((x) & (~BITS_WLAN_RPT_TO_8822C)) +#define BIT_GET_WLAN_RPT_TO_8822C(x) \ + (((x) >> BIT_SHIFT_WLAN_RPT_TO_8822C) & BIT_MASK_WLAN_RPT_TO_8822C) +#define BIT_SET_WLAN_RPT_TO_8822C(x, v) \ + (BIT_CLEAR_WLAN_RPT_TO_8822C(x) | BIT_WLAN_RPT_TO_8822C(v)) + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822C */ + +#define BIT_SHIFT_ISOLATION_CHK_0_8822C 1 +#define BIT_MASK_ISOLATION_CHK_0_8822C 0x7fffff +#define BIT_ISOLATION_CHK_0_8822C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_0_8822C) \ + << BIT_SHIFT_ISOLATION_CHK_0_8822C) +#define BITS_ISOLATION_CHK_0_8822C \ + (BIT_MASK_ISOLATION_CHK_0_8822C << BIT_SHIFT_ISOLATION_CHK_0_8822C) +#define BIT_CLEAR_ISOLATION_CHK_0_8822C(x) ((x) & (~BITS_ISOLATION_CHK_0_8822C)) +#define BIT_GET_ISOLATION_CHK_0_8822C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8822C) & \ + BIT_MASK_ISOLATION_CHK_0_8822C) +#define BIT_SET_ISOLATION_CHK_0_8822C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_0_8822C(x) | BIT_ISOLATION_CHK_0_8822C(v)) + +#define BIT_ISOLATION_EN_8822C BIT(0) + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8822C */ + +#define BIT_SHIFT_ISOLATION_CHK_1_8822C 0 +#define BIT_MASK_ISOLATION_CHK_1_8822C 0xffffffffL +#define BIT_ISOLATION_CHK_1_8822C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_1_8822C) \ + << BIT_SHIFT_ISOLATION_CHK_1_8822C) +#define BITS_ISOLATION_CHK_1_8822C \ + (BIT_MASK_ISOLATION_CHK_1_8822C << BIT_SHIFT_ISOLATION_CHK_1_8822C) +#define BIT_CLEAR_ISOLATION_CHK_1_8822C(x) ((x) & (~BITS_ISOLATION_CHK_1_8822C)) +#define BIT_GET_ISOLATION_CHK_1_8822C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8822C) & \ + BIT_MASK_ISOLATION_CHK_1_8822C) +#define BIT_SET_ISOLATION_CHK_1_8822C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_1_8822C(x) | BIT_ISOLATION_CHK_1_8822C(v)) + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8822C */ + +#define BIT_SHIFT_ISOLATION_CHK_2_8822C 0 +#define BIT_MASK_ISOLATION_CHK_2_8822C 0xffffff +#define BIT_ISOLATION_CHK_2_8822C(x) \ + (((x) & BIT_MASK_ISOLATION_CHK_2_8822C) \ + << BIT_SHIFT_ISOLATION_CHK_2_8822C) +#define BITS_ISOLATION_CHK_2_8822C \ + (BIT_MASK_ISOLATION_CHK_2_8822C << BIT_SHIFT_ISOLATION_CHK_2_8822C) +#define BIT_CLEAR_ISOLATION_CHK_2_8822C(x) ((x) & (~BITS_ISOLATION_CHK_2_8822C)) +#define BIT_GET_ISOLATION_CHK_2_8822C(x) \ + (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8822C) & \ + BIT_MASK_ISOLATION_CHK_2_8822C) +#define BIT_SET_ISOLATION_CHK_2_8822C(x, v) \ + (BIT_CLEAR_ISOLATION_CHK_2_8822C(x) | BIT_ISOLATION_CHK_2_8822C(v)) + +/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8822C */ +#define BIT_BT_HID_ISR_8822C BIT(7) +#define BIT_BT_QUERY_ISR_8822C BIT(6) +#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8822C BIT(5) +#define BIT_WLAN_RPT_ISR_8822C BIT(4) +#define BIT_BT_POWER_ISR_8822C BIT(3) +#define BIT_BT_CHANNEL_ISR_8822C BIT(2) +#define BIT_BT_SLOT_CHANGE_ISR_8822C BIT(1) +#define BIT_BT_PROFILE_ISR_8822C BIT(0) + +/* 2 REG_BT_TDMA_TIME_REGISTER_8822C */ + +#define BIT_SHIFT_BT_TIME_8822C 6 +#define BIT_MASK_BT_TIME_8822C 0x3ffffff +#define BIT_BT_TIME_8822C(x) \ + (((x) & BIT_MASK_BT_TIME_8822C) << BIT_SHIFT_BT_TIME_8822C) +#define BITS_BT_TIME_8822C (BIT_MASK_BT_TIME_8822C << BIT_SHIFT_BT_TIME_8822C) +#define BIT_CLEAR_BT_TIME_8822C(x) ((x) & (~BITS_BT_TIME_8822C)) +#define BIT_GET_BT_TIME_8822C(x) \ + (((x) >> BIT_SHIFT_BT_TIME_8822C) & BIT_MASK_BT_TIME_8822C) +#define BIT_SET_BT_TIME_8822C(x, v) \ + (BIT_CLEAR_BT_TIME_8822C(x) | BIT_BT_TIME_8822C(v)) + +#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C 0 +#define BIT_MASK_BT_RPT_SAMPLE_RATE_8822C 0x3f +#define BIT_BT_RPT_SAMPLE_RATE_8822C(x) \ + (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822C) \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C) +#define BITS_BT_RPT_SAMPLE_RATE_8822C \ + (BIT_MASK_BT_RPT_SAMPLE_RATE_8822C \ + << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C) +#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822C(x) \ + ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8822C)) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8822C(x) \ + (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C) & \ + BIT_MASK_BT_RPT_SAMPLE_RATE_8822C) +#define BIT_SET_BT_RPT_SAMPLE_RATE_8822C(x, v) \ + (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822C(x) | \ + BIT_BT_RPT_SAMPLE_RATE_8822C(v)) + +/* 2 REG_BT_ACT_REGISTER_8822C */ + +#define BIT_SHIFT_BT_EISR_EN_8822C 16 +#define BIT_MASK_BT_EISR_EN_8822C 0xff +#define BIT_BT_EISR_EN_8822C(x) \ + (((x) & BIT_MASK_BT_EISR_EN_8822C) << BIT_SHIFT_BT_EISR_EN_8822C) +#define BITS_BT_EISR_EN_8822C \ + (BIT_MASK_BT_EISR_EN_8822C << BIT_SHIFT_BT_EISR_EN_8822C) +#define BIT_CLEAR_BT_EISR_EN_8822C(x) ((x) & (~BITS_BT_EISR_EN_8822C)) +#define BIT_GET_BT_EISR_EN_8822C(x) \ + (((x) >> BIT_SHIFT_BT_EISR_EN_8822C) & BIT_MASK_BT_EISR_EN_8822C) +#define BIT_SET_BT_EISR_EN_8822C(x, v) \ + (BIT_CLEAR_BT_EISR_EN_8822C(x) | BIT_BT_EISR_EN_8822C(v)) + +#define BIT_BT_ACT_FALLING_ISR_8822C BIT(10) +#define BIT_BT_ACT_RISING_ISR_8822C BIT(9) +#define BIT_TDMA_TO_ISR_8822C BIT(8) + +#define BIT_SHIFT_BT_CH_V1_8822C 0 +#define BIT_MASK_BT_CH_V1_8822C 0x7f +#define BIT_BT_CH_V1_8822C(x) \ + (((x) & BIT_MASK_BT_CH_V1_8822C) << BIT_SHIFT_BT_CH_V1_8822C) +#define BITS_BT_CH_V1_8822C \ + (BIT_MASK_BT_CH_V1_8822C << BIT_SHIFT_BT_CH_V1_8822C) +#define BIT_CLEAR_BT_CH_V1_8822C(x) ((x) & (~BITS_BT_CH_V1_8822C)) +#define BIT_GET_BT_CH_V1_8822C(x) \ + (((x) >> BIT_SHIFT_BT_CH_V1_8822C) & BIT_MASK_BT_CH_V1_8822C) +#define BIT_SET_BT_CH_V1_8822C(x, v) \ + (BIT_CLEAR_BT_CH_V1_8822C(x) | BIT_BT_CH_V1_8822C(v)) + +/* 2 REG_OBFF_CTRL_BASIC_8822C */ +#define BIT_OBFF_EN_V1_8822C BIT(31) + +#define BIT_SHIFT_OBFF_STATE_V1_8822C 28 +#define BIT_MASK_OBFF_STATE_V1_8822C 0x3 +#define BIT_OBFF_STATE_V1_8822C(x) \ + (((x) & BIT_MASK_OBFF_STATE_V1_8822C) << BIT_SHIFT_OBFF_STATE_V1_8822C) +#define BITS_OBFF_STATE_V1_8822C \ + (BIT_MASK_OBFF_STATE_V1_8822C << BIT_SHIFT_OBFF_STATE_V1_8822C) +#define BIT_CLEAR_OBFF_STATE_V1_8822C(x) ((x) & (~BITS_OBFF_STATE_V1_8822C)) +#define BIT_GET_OBFF_STATE_V1_8822C(x) \ + (((x) >> BIT_SHIFT_OBFF_STATE_V1_8822C) & BIT_MASK_OBFF_STATE_V1_8822C) +#define BIT_SET_OBFF_STATE_V1_8822C(x, v) \ + (BIT_CLEAR_OBFF_STATE_V1_8822C(x) | BIT_OBFF_STATE_V1_8822C(v)) + +#define BIT_OBFF_ACT_RXDMA_EN_8822C BIT(27) +#define BIT_OBFF_BLOCK_INT_EN_8822C BIT(26) +#define BIT_OBFF_AUTOACT_EN_8822C BIT(25) +#define BIT_OBFF_AUTOIDLE_EN_8822C BIT(24) + +#define BIT_SHIFT_WAKE_MAX_PLS_8822C 20 +#define BIT_MASK_WAKE_MAX_PLS_8822C 0x7 +#define BIT_WAKE_MAX_PLS_8822C(x) \ + (((x) & BIT_MASK_WAKE_MAX_PLS_8822C) << BIT_SHIFT_WAKE_MAX_PLS_8822C) +#define BITS_WAKE_MAX_PLS_8822C \ + (BIT_MASK_WAKE_MAX_PLS_8822C << BIT_SHIFT_WAKE_MAX_PLS_8822C) +#define BIT_CLEAR_WAKE_MAX_PLS_8822C(x) ((x) & (~BITS_WAKE_MAX_PLS_8822C)) +#define BIT_GET_WAKE_MAX_PLS_8822C(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822C) & BIT_MASK_WAKE_MAX_PLS_8822C) +#define BIT_SET_WAKE_MAX_PLS_8822C(x, v) \ + (BIT_CLEAR_WAKE_MAX_PLS_8822C(x) | BIT_WAKE_MAX_PLS_8822C(v)) + +#define BIT_SHIFT_WAKE_MIN_PLS_8822C 16 +#define BIT_MASK_WAKE_MIN_PLS_8822C 0x7 +#define BIT_WAKE_MIN_PLS_8822C(x) \ + (((x) & BIT_MASK_WAKE_MIN_PLS_8822C) << BIT_SHIFT_WAKE_MIN_PLS_8822C) +#define BITS_WAKE_MIN_PLS_8822C \ + (BIT_MASK_WAKE_MIN_PLS_8822C << BIT_SHIFT_WAKE_MIN_PLS_8822C) +#define BIT_CLEAR_WAKE_MIN_PLS_8822C(x) ((x) & (~BITS_WAKE_MIN_PLS_8822C)) +#define BIT_GET_WAKE_MIN_PLS_8822C(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822C) & BIT_MASK_WAKE_MIN_PLS_8822C) +#define BIT_SET_WAKE_MIN_PLS_8822C(x, v) \ + (BIT_CLEAR_WAKE_MIN_PLS_8822C(x) | BIT_WAKE_MIN_PLS_8822C(v)) + +#define BIT_SHIFT_WAKE_MAX_F2F_8822C 12 +#define BIT_MASK_WAKE_MAX_F2F_8822C 0x7 +#define BIT_WAKE_MAX_F2F_8822C(x) \ + (((x) & BIT_MASK_WAKE_MAX_F2F_8822C) << BIT_SHIFT_WAKE_MAX_F2F_8822C) +#define BITS_WAKE_MAX_F2F_8822C \ + (BIT_MASK_WAKE_MAX_F2F_8822C << BIT_SHIFT_WAKE_MAX_F2F_8822C) +#define BIT_CLEAR_WAKE_MAX_F2F_8822C(x) ((x) & (~BITS_WAKE_MAX_F2F_8822C)) +#define BIT_GET_WAKE_MAX_F2F_8822C(x) \ + (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822C) & BIT_MASK_WAKE_MAX_F2F_8822C) +#define BIT_SET_WAKE_MAX_F2F_8822C(x, v) \ + (BIT_CLEAR_WAKE_MAX_F2F_8822C(x) | BIT_WAKE_MAX_F2F_8822C(v)) + +#define BIT_SHIFT_WAKE_MIN_F2F_8822C 8 +#define BIT_MASK_WAKE_MIN_F2F_8822C 0x7 +#define BIT_WAKE_MIN_F2F_8822C(x) \ + (((x) & BIT_MASK_WAKE_MIN_F2F_8822C) << BIT_SHIFT_WAKE_MIN_F2F_8822C) +#define BITS_WAKE_MIN_F2F_8822C \ + (BIT_MASK_WAKE_MIN_F2F_8822C << BIT_SHIFT_WAKE_MIN_F2F_8822C) +#define BIT_CLEAR_WAKE_MIN_F2F_8822C(x) ((x) & (~BITS_WAKE_MIN_F2F_8822C)) +#define BIT_GET_WAKE_MIN_F2F_8822C(x) \ + (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822C) & BIT_MASK_WAKE_MIN_F2F_8822C) +#define BIT_SET_WAKE_MIN_F2F_8822C(x, v) \ + (BIT_CLEAR_WAKE_MIN_F2F_8822C(x) | BIT_WAKE_MIN_F2F_8822C(v)) + +#define BIT_APP_CPU_ACT_V1_8822C BIT(3) +#define BIT_APP_OBFF_V1_8822C BIT(2) +#define BIT_APP_IDLE_V1_8822C BIT(1) +#define BIT_APP_INIT_V1_8822C BIT(0) + +/* 2 REG_OBFF_CTRL2_TIMER_8822C */ + +#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C 24 +#define BIT_MASK_RX_HIGH_TIMER_IDX_8822C 0x7 +#define BIT_RX_HIGH_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822C) \ + << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C) +#define BITS_RX_HIGH_TIMER_IDX_8822C \ + (BIT_MASK_RX_HIGH_TIMER_IDX_8822C << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C) +#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_RX_HIGH_TIMER_IDX_8822C)) +#define BIT_GET_RX_HIGH_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C) & \ + BIT_MASK_RX_HIGH_TIMER_IDX_8822C) +#define BIT_SET_RX_HIGH_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_HIGH_TIMER_IDX_8822C(x) | BIT_RX_HIGH_TIMER_IDX_8822C(v)) + +#define BIT_SHIFT_RX_MED_TIMER_IDX_8822C 16 +#define BIT_MASK_RX_MED_TIMER_IDX_8822C 0x7 +#define BIT_RX_MED_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_MED_TIMER_IDX_8822C) \ + << BIT_SHIFT_RX_MED_TIMER_IDX_8822C) +#define BITS_RX_MED_TIMER_IDX_8822C \ + (BIT_MASK_RX_MED_TIMER_IDX_8822C << BIT_SHIFT_RX_MED_TIMER_IDX_8822C) +#define BIT_CLEAR_RX_MED_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_RX_MED_TIMER_IDX_8822C)) +#define BIT_GET_RX_MED_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822C) & \ + BIT_MASK_RX_MED_TIMER_IDX_8822C) +#define BIT_SET_RX_MED_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_MED_TIMER_IDX_8822C(x) | BIT_RX_MED_TIMER_IDX_8822C(v)) + +#define BIT_SHIFT_RX_LOW_TIMER_IDX_8822C 8 +#define BIT_MASK_RX_LOW_TIMER_IDX_8822C 0x7 +#define BIT_RX_LOW_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822C) \ + << BIT_SHIFT_RX_LOW_TIMER_IDX_8822C) +#define BITS_RX_LOW_TIMER_IDX_8822C \ + (BIT_MASK_RX_LOW_TIMER_IDX_8822C << BIT_SHIFT_RX_LOW_TIMER_IDX_8822C) +#define BIT_CLEAR_RX_LOW_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_RX_LOW_TIMER_IDX_8822C)) +#define BIT_GET_RX_LOW_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822C) & \ + BIT_MASK_RX_LOW_TIMER_IDX_8822C) +#define BIT_SET_RX_LOW_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_LOW_TIMER_IDX_8822C(x) | BIT_RX_LOW_TIMER_IDX_8822C(v)) + +#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C 0 +#define BIT_MASK_OBFF_INT_TIMER_IDX_8822C 0x7 +#define BIT_OBFF_INT_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822C) \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C) +#define BITS_OBFF_INT_TIMER_IDX_8822C \ + (BIT_MASK_OBFF_INT_TIMER_IDX_8822C \ + << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C) +#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_OBFF_INT_TIMER_IDX_8822C)) +#define BIT_GET_OBFF_INT_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C) & \ + BIT_MASK_OBFF_INT_TIMER_IDX_8822C) +#define BIT_SET_OBFF_INT_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_OBFF_INT_TIMER_IDX_8822C(x) | \ + BIT_OBFF_INT_TIMER_IDX_8822C(v)) + +/* 2 REG_LTR_CTRL_BASIC_8822C */ +#define BIT_LTR_EN_V1_8822C BIT(31) +#define BIT_LTR_HW_EN_V1_8822C BIT(30) +#define BIT_LRT_ACT_CTS_EN_8822C BIT(29) +#define BIT_LTR_ACT_RXPKT_EN_8822C BIT(28) +#define BIT_LTR_ACT_RXDMA_EN_8822C BIT(27) +#define BIT_LTR_IDLE_NO_SNOOP_8822C BIT(26) +#define BIT_SPDUP_MGTPKT_8822C BIT(25) +#define BIT_RX_AGG_EN_8822C BIT(24) +#define BIT_APP_LTR_ACT_8822C BIT(23) +#define BIT_APP_LTR_IDLE_8822C BIT(22) + +#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C 20 +#define BIT_MASK_HIGH_RATE_TRIG_SEL_8822C 0x3 +#define BIT_HIGH_RATE_TRIG_SEL_8822C(x) \ + (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822C) \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C) +#define BITS_HIGH_RATE_TRIG_SEL_8822C \ + (BIT_MASK_HIGH_RATE_TRIG_SEL_8822C \ + << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C) +#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822C(x) \ + ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8822C)) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C) & \ + BIT_MASK_HIGH_RATE_TRIG_SEL_8822C) +#define BIT_SET_HIGH_RATE_TRIG_SEL_8822C(x, v) \ + (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822C(x) | \ + BIT_HIGH_RATE_TRIG_SEL_8822C(v)) + +#define BIT_SHIFT_MED_RATE_TRIG_SEL_8822C 18 +#define BIT_MASK_MED_RATE_TRIG_SEL_8822C 0x3 +#define BIT_MED_RATE_TRIG_SEL_8822C(x) \ + (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822C) \ + << BIT_SHIFT_MED_RATE_TRIG_SEL_8822C) +#define BITS_MED_RATE_TRIG_SEL_8822C \ + (BIT_MASK_MED_RATE_TRIG_SEL_8822C << BIT_SHIFT_MED_RATE_TRIG_SEL_8822C) +#define BIT_CLEAR_MED_RATE_TRIG_SEL_8822C(x) \ + ((x) & (~BITS_MED_RATE_TRIG_SEL_8822C)) +#define BIT_GET_MED_RATE_TRIG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822C) & \ + BIT_MASK_MED_RATE_TRIG_SEL_8822C) +#define BIT_SET_MED_RATE_TRIG_SEL_8822C(x, v) \ + (BIT_CLEAR_MED_RATE_TRIG_SEL_8822C(x) | BIT_MED_RATE_TRIG_SEL_8822C(v)) + +#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C 16 +#define BIT_MASK_LOW_RATE_TRIG_SEL_8822C 0x3 +#define BIT_LOW_RATE_TRIG_SEL_8822C(x) \ + (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822C) \ + << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C) +#define BITS_LOW_RATE_TRIG_SEL_8822C \ + (BIT_MASK_LOW_RATE_TRIG_SEL_8822C << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C) +#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8822C(x) \ + ((x) & (~BITS_LOW_RATE_TRIG_SEL_8822C)) +#define BIT_GET_LOW_RATE_TRIG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C) & \ + BIT_MASK_LOW_RATE_TRIG_SEL_8822C) +#define BIT_SET_LOW_RATE_TRIG_SEL_8822C(x, v) \ + (BIT_CLEAR_LOW_RATE_TRIG_SEL_8822C(x) | BIT_LOW_RATE_TRIG_SEL_8822C(v)) + +#define BIT_SHIFT_HIGH_RATE_BD_IDX_8822C 8 +#define BIT_MASK_HIGH_RATE_BD_IDX_8822C 0x7f +#define BIT_HIGH_RATE_BD_IDX_8822C(x) \ + (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822C) \ + << BIT_SHIFT_HIGH_RATE_BD_IDX_8822C) +#define BITS_HIGH_RATE_BD_IDX_8822C \ + (BIT_MASK_HIGH_RATE_BD_IDX_8822C << BIT_SHIFT_HIGH_RATE_BD_IDX_8822C) +#define BIT_CLEAR_HIGH_RATE_BD_IDX_8822C(x) \ + ((x) & (~BITS_HIGH_RATE_BD_IDX_8822C)) +#define BIT_GET_HIGH_RATE_BD_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822C) & \ + BIT_MASK_HIGH_RATE_BD_IDX_8822C) +#define BIT_SET_HIGH_RATE_BD_IDX_8822C(x, v) \ + (BIT_CLEAR_HIGH_RATE_BD_IDX_8822C(x) | BIT_HIGH_RATE_BD_IDX_8822C(v)) + +#define BIT_SHIFT_LOW_RATE_BD_IDX_8822C 0 +#define BIT_MASK_LOW_RATE_BD_IDX_8822C 0x7f +#define BIT_LOW_RATE_BD_IDX_8822C(x) \ + (((x) & BIT_MASK_LOW_RATE_BD_IDX_8822C) \ + << BIT_SHIFT_LOW_RATE_BD_IDX_8822C) +#define BITS_LOW_RATE_BD_IDX_8822C \ + (BIT_MASK_LOW_RATE_BD_IDX_8822C << BIT_SHIFT_LOW_RATE_BD_IDX_8822C) +#define BIT_CLEAR_LOW_RATE_BD_IDX_8822C(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8822C)) +#define BIT_GET_LOW_RATE_BD_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822C) & \ + BIT_MASK_LOW_RATE_BD_IDX_8822C) +#define BIT_SET_LOW_RATE_BD_IDX_8822C(x, v) \ + (BIT_CLEAR_LOW_RATE_BD_IDX_8822C(x) | BIT_LOW_RATE_BD_IDX_8822C(v)) + +/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822C */ + +#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C 24 +#define BIT_MASK_RX_EMPTY_TIMER_IDX_8822C 0x7 +#define BIT_RX_EMPTY_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822C) \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C) +#define BITS_RX_EMPTY_TIMER_IDX_8822C \ + (BIT_MASK_RX_EMPTY_TIMER_IDX_8822C \ + << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C) +#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8822C)) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C) & \ + BIT_MASK_RX_EMPTY_TIMER_IDX_8822C) +#define BIT_SET_RX_EMPTY_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822C(x) | \ + BIT_RX_EMPTY_TIMER_IDX_8822C(v)) + +#define BIT_SHIFT_RX_AFULL_TH_IDX_8822C 20 +#define BIT_MASK_RX_AFULL_TH_IDX_8822C 0x7 +#define BIT_RX_AFULL_TH_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_AFULL_TH_IDX_8822C) \ + << BIT_SHIFT_RX_AFULL_TH_IDX_8822C) +#define BITS_RX_AFULL_TH_IDX_8822C \ + (BIT_MASK_RX_AFULL_TH_IDX_8822C << BIT_SHIFT_RX_AFULL_TH_IDX_8822C) +#define BIT_CLEAR_RX_AFULL_TH_IDX_8822C(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8822C)) +#define BIT_GET_RX_AFULL_TH_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822C) & \ + BIT_MASK_RX_AFULL_TH_IDX_8822C) +#define BIT_SET_RX_AFULL_TH_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_AFULL_TH_IDX_8822C(x) | BIT_RX_AFULL_TH_IDX_8822C(v)) + +#define BIT_SHIFT_RX_HIGH_TH_IDX_8822C 16 +#define BIT_MASK_RX_HIGH_TH_IDX_8822C 0x7 +#define BIT_RX_HIGH_TH_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_HIGH_TH_IDX_8822C) \ + << BIT_SHIFT_RX_HIGH_TH_IDX_8822C) +#define BITS_RX_HIGH_TH_IDX_8822C \ + (BIT_MASK_RX_HIGH_TH_IDX_8822C << BIT_SHIFT_RX_HIGH_TH_IDX_8822C) +#define BIT_CLEAR_RX_HIGH_TH_IDX_8822C(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8822C)) +#define BIT_GET_RX_HIGH_TH_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822C) & \ + BIT_MASK_RX_HIGH_TH_IDX_8822C) +#define BIT_SET_RX_HIGH_TH_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_HIGH_TH_IDX_8822C(x) | BIT_RX_HIGH_TH_IDX_8822C(v)) + +#define BIT_SHIFT_RX_MED_TH_IDX_8822C 12 +#define BIT_MASK_RX_MED_TH_IDX_8822C 0x7 +#define BIT_RX_MED_TH_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_MED_TH_IDX_8822C) << BIT_SHIFT_RX_MED_TH_IDX_8822C) +#define BITS_RX_MED_TH_IDX_8822C \ + (BIT_MASK_RX_MED_TH_IDX_8822C << BIT_SHIFT_RX_MED_TH_IDX_8822C) +#define BIT_CLEAR_RX_MED_TH_IDX_8822C(x) ((x) & (~BITS_RX_MED_TH_IDX_8822C)) +#define BIT_GET_RX_MED_TH_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822C) & BIT_MASK_RX_MED_TH_IDX_8822C) +#define BIT_SET_RX_MED_TH_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_MED_TH_IDX_8822C(x) | BIT_RX_MED_TH_IDX_8822C(v)) + +#define BIT_SHIFT_RX_LOW_TH_IDX_8822C 8 +#define BIT_MASK_RX_LOW_TH_IDX_8822C 0x7 +#define BIT_RX_LOW_TH_IDX_8822C(x) \ + (((x) & BIT_MASK_RX_LOW_TH_IDX_8822C) << BIT_SHIFT_RX_LOW_TH_IDX_8822C) +#define BITS_RX_LOW_TH_IDX_8822C \ + (BIT_MASK_RX_LOW_TH_IDX_8822C << BIT_SHIFT_RX_LOW_TH_IDX_8822C) +#define BIT_CLEAR_RX_LOW_TH_IDX_8822C(x) ((x) & (~BITS_RX_LOW_TH_IDX_8822C)) +#define BIT_GET_RX_LOW_TH_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822C) & BIT_MASK_RX_LOW_TH_IDX_8822C) +#define BIT_SET_RX_LOW_TH_IDX_8822C(x, v) \ + (BIT_CLEAR_RX_LOW_TH_IDX_8822C(x) | BIT_RX_LOW_TH_IDX_8822C(v)) + +#define BIT_SHIFT_LTR_SPACE_IDX_8822C 4 +#define BIT_MASK_LTR_SPACE_IDX_8822C 0x3 +#define BIT_LTR_SPACE_IDX_8822C(x) \ + (((x) & BIT_MASK_LTR_SPACE_IDX_8822C) << BIT_SHIFT_LTR_SPACE_IDX_8822C) +#define BITS_LTR_SPACE_IDX_8822C \ + (BIT_MASK_LTR_SPACE_IDX_8822C << BIT_SHIFT_LTR_SPACE_IDX_8822C) +#define BIT_CLEAR_LTR_SPACE_IDX_8822C(x) ((x) & (~BITS_LTR_SPACE_IDX_8822C)) +#define BIT_GET_LTR_SPACE_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822C) & BIT_MASK_LTR_SPACE_IDX_8822C) +#define BIT_SET_LTR_SPACE_IDX_8822C(x, v) \ + (BIT_CLEAR_LTR_SPACE_IDX_8822C(x) | BIT_LTR_SPACE_IDX_8822C(v)) + +#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C 0 +#define BIT_MASK_LTR_IDLE_TIMER_IDX_8822C 0x7 +#define BIT_LTR_IDLE_TIMER_IDX_8822C(x) \ + (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822C) \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C) +#define BITS_LTR_IDLE_TIMER_IDX_8822C \ + (BIT_MASK_LTR_IDLE_TIMER_IDX_8822C \ + << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C) +#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822C(x) \ + ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8822C)) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8822C(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C) & \ + BIT_MASK_LTR_IDLE_TIMER_IDX_8822C) +#define BIT_SET_LTR_IDLE_TIMER_IDX_8822C(x, v) \ + (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822C(x) | \ + BIT_LTR_IDLE_TIMER_IDX_8822C(v)) + +/* 2 REG_LTR_IDLE_LATENCY_V1_8822C */ + +#define BIT_SHIFT_LTR_IDLE_L_8822C 0 +#define BIT_MASK_LTR_IDLE_L_8822C 0xffffffffL +#define BIT_LTR_IDLE_L_8822C(x) \ + (((x) & BIT_MASK_LTR_IDLE_L_8822C) << BIT_SHIFT_LTR_IDLE_L_8822C) +#define BITS_LTR_IDLE_L_8822C \ + (BIT_MASK_LTR_IDLE_L_8822C << BIT_SHIFT_LTR_IDLE_L_8822C) +#define BIT_CLEAR_LTR_IDLE_L_8822C(x) ((x) & (~BITS_LTR_IDLE_L_8822C)) +#define BIT_GET_LTR_IDLE_L_8822C(x) \ + (((x) >> BIT_SHIFT_LTR_IDLE_L_8822C) & BIT_MASK_LTR_IDLE_L_8822C) +#define BIT_SET_LTR_IDLE_L_8822C(x, v) \ + (BIT_CLEAR_LTR_IDLE_L_8822C(x) | BIT_LTR_IDLE_L_8822C(v)) + +/* 2 REG_LTR_ACTIVE_LATENCY_V1_8822C */ + +#define BIT_SHIFT_LTR_ACT_L_8822C 0 +#define BIT_MASK_LTR_ACT_L_8822C 0xffffffffL +#define BIT_LTR_ACT_L_8822C(x) \ + (((x) & BIT_MASK_LTR_ACT_L_8822C) << BIT_SHIFT_LTR_ACT_L_8822C) +#define BITS_LTR_ACT_L_8822C \ + (BIT_MASK_LTR_ACT_L_8822C << BIT_SHIFT_LTR_ACT_L_8822C) +#define BIT_CLEAR_LTR_ACT_L_8822C(x) ((x) & (~BITS_LTR_ACT_L_8822C)) +#define BIT_GET_LTR_ACT_L_8822C(x) \ + (((x) >> BIT_SHIFT_LTR_ACT_L_8822C) & BIT_MASK_LTR_ACT_L_8822C) +#define BIT_SET_LTR_ACT_L_8822C(x, v) \ + (BIT_CLEAR_LTR_ACT_L_8822C(x) | BIT_LTR_ACT_L_8822C(v)) + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822C */ + +#define BIT_SHIFT_TRAIN_STA_ADDR_0_8822C 0 +#define BIT_MASK_TRAIN_STA_ADDR_0_8822C 0xffffffffL +#define BIT_TRAIN_STA_ADDR_0_8822C(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8822C) \ + << BIT_SHIFT_TRAIN_STA_ADDR_0_8822C) +#define BITS_TRAIN_STA_ADDR_0_8822C \ + (BIT_MASK_TRAIN_STA_ADDR_0_8822C << BIT_SHIFT_TRAIN_STA_ADDR_0_8822C) +#define BIT_CLEAR_TRAIN_STA_ADDR_0_8822C(x) \ + ((x) & (~BITS_TRAIN_STA_ADDR_0_8822C)) +#define BIT_GET_TRAIN_STA_ADDR_0_8822C(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8822C) & \ + BIT_MASK_TRAIN_STA_ADDR_0_8822C) +#define BIT_SET_TRAIN_STA_ADDR_0_8822C(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_0_8822C(x) | BIT_TRAIN_STA_ADDR_0_8822C(v)) + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8822C */ +#define BIT_ANTTRN_SWITCH_8822C BIT(19) +#define BIT_APPEND_MACID_IN_RESP_EN_1_8822C BIT(18) +#define BIT_ADDR2_MATCH_EN_1_8822C BIT(17) +#define BIT_ANTTRN_EN_1_8822C BIT(16) + +#define BIT_SHIFT_TRAIN_STA_ADDR_1_8822C 0 +#define BIT_MASK_TRAIN_STA_ADDR_1_8822C 0xffff +#define BIT_TRAIN_STA_ADDR_1_8822C(x) \ + (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8822C) \ + << BIT_SHIFT_TRAIN_STA_ADDR_1_8822C) +#define BITS_TRAIN_STA_ADDR_1_8822C \ + (BIT_MASK_TRAIN_STA_ADDR_1_8822C << BIT_SHIFT_TRAIN_STA_ADDR_1_8822C) +#define BIT_CLEAR_TRAIN_STA_ADDR_1_8822C(x) \ + ((x) & (~BITS_TRAIN_STA_ADDR_1_8822C)) +#define BIT_GET_TRAIN_STA_ADDR_1_8822C(x) \ + (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8822C) & \ + BIT_MASK_TRAIN_STA_ADDR_1_8822C) +#define BIT_SET_TRAIN_STA_ADDR_1_8822C(x, v) \ + (BIT_CLEAR_TRAIN_STA_ADDR_1_8822C(x) | BIT_TRAIN_STA_ADDR_1_8822C(v)) + +/* 2 REG_WMAC_PKTCNT_RWD_8822C */ + +#define BIT_SHIFT_PKTCNT_BSSIDMAP_8822C 4 +#define BIT_MASK_PKTCNT_BSSIDMAP_8822C 0xf +#define BIT_PKTCNT_BSSIDMAP_8822C(x) \ + (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822C) \ + << BIT_SHIFT_PKTCNT_BSSIDMAP_8822C) +#define BITS_PKTCNT_BSSIDMAP_8822C \ + (BIT_MASK_PKTCNT_BSSIDMAP_8822C << BIT_SHIFT_PKTCNT_BSSIDMAP_8822C) +#define BIT_CLEAR_PKTCNT_BSSIDMAP_8822C(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8822C)) +#define BIT_GET_PKTCNT_BSSIDMAP_8822C(x) \ + (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822C) & \ + BIT_MASK_PKTCNT_BSSIDMAP_8822C) +#define BIT_SET_PKTCNT_BSSIDMAP_8822C(x, v) \ + (BIT_CLEAR_PKTCNT_BSSIDMAP_8822C(x) | BIT_PKTCNT_BSSIDMAP_8822C(v)) + +#define BIT_PKTCNT_CNTRST_8822C BIT(1) +#define BIT_PKTCNT_CNTEN_8822C BIT(0) + +/* 2 REG_WMAC_PKTCNT_CTRL_8822C */ +#define BIT_WMAC_PKTCNT_TRST_8822C BIT(9) +#define BIT_WMAC_PKTCNT_FEN_8822C BIT(8) + +#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C 0 +#define BIT_MASK_WMAC_PKTCNT_CFGAD_8822C 0xff +#define BIT_WMAC_PKTCNT_CFGAD_8822C(x) \ + (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822C) \ + << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C) +#define BITS_WMAC_PKTCNT_CFGAD_8822C \ + (BIT_MASK_WMAC_PKTCNT_CFGAD_8822C << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C) +#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822C(x) \ + ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8822C)) +#define BIT_GET_WMAC_PKTCNT_CFGAD_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C) & \ + BIT_MASK_WMAC_PKTCNT_CFGAD_8822C) +#define BIT_SET_WMAC_PKTCNT_CFGAD_8822C(x, v) \ + (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822C(x) | BIT_WMAC_PKTCNT_CFGAD_8822C(v)) + +/* 2 REG_IQ_DUMP_8822C */ + +#define BIT_SHIFT_DUMP_OK_ADDR_8822C 16 +#define BIT_MASK_DUMP_OK_ADDR_8822C 0xffff +#define BIT_DUMP_OK_ADDR_8822C(x) \ + (((x) & BIT_MASK_DUMP_OK_ADDR_8822C) << BIT_SHIFT_DUMP_OK_ADDR_8822C) +#define BITS_DUMP_OK_ADDR_8822C \ + (BIT_MASK_DUMP_OK_ADDR_8822C << BIT_SHIFT_DUMP_OK_ADDR_8822C) +#define BIT_CLEAR_DUMP_OK_ADDR_8822C(x) ((x) & (~BITS_DUMP_OK_ADDR_8822C)) +#define BIT_GET_DUMP_OK_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822C) & BIT_MASK_DUMP_OK_ADDR_8822C) +#define BIT_SET_DUMP_OK_ADDR_8822C(x, v) \ + (BIT_CLEAR_DUMP_OK_ADDR_8822C(x) | BIT_DUMP_OK_ADDR_8822C(v)) + +#define BIT_MACDBG_TRIG_IQDUMP_8822C BIT(15) + +#define BIT_SHIFT_R_TRIG_TIME_SEL_8822C 8 +#define BIT_MASK_R_TRIG_TIME_SEL_8822C 0x7f +#define BIT_R_TRIG_TIME_SEL_8822C(x) \ + (((x) & BIT_MASK_R_TRIG_TIME_SEL_8822C) \ + << BIT_SHIFT_R_TRIG_TIME_SEL_8822C) +#define BITS_R_TRIG_TIME_SEL_8822C \ + (BIT_MASK_R_TRIG_TIME_SEL_8822C << BIT_SHIFT_R_TRIG_TIME_SEL_8822C) +#define BIT_CLEAR_R_TRIG_TIME_SEL_8822C(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8822C)) +#define BIT_GET_R_TRIG_TIME_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822C) & \ + BIT_MASK_R_TRIG_TIME_SEL_8822C) +#define BIT_SET_R_TRIG_TIME_SEL_8822C(x, v) \ + (BIT_CLEAR_R_TRIG_TIME_SEL_8822C(x) | BIT_R_TRIG_TIME_SEL_8822C(v)) + +#define BIT_SHIFT_R_MAC_TRIG_SEL_8822C 6 +#define BIT_MASK_R_MAC_TRIG_SEL_8822C 0x3 +#define BIT_R_MAC_TRIG_SEL_8822C(x) \ + (((x) & BIT_MASK_R_MAC_TRIG_SEL_8822C) \ + << BIT_SHIFT_R_MAC_TRIG_SEL_8822C) +#define BITS_R_MAC_TRIG_SEL_8822C \ + (BIT_MASK_R_MAC_TRIG_SEL_8822C << BIT_SHIFT_R_MAC_TRIG_SEL_8822C) +#define BIT_CLEAR_R_MAC_TRIG_SEL_8822C(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8822C)) +#define BIT_GET_R_MAC_TRIG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822C) & \ + BIT_MASK_R_MAC_TRIG_SEL_8822C) +#define BIT_SET_R_MAC_TRIG_SEL_8822C(x, v) \ + (BIT_CLEAR_R_MAC_TRIG_SEL_8822C(x) | BIT_R_MAC_TRIG_SEL_8822C(v)) + +#define BIT_MAC_TRIG_REG_8822C BIT(5) + +#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C 3 +#define BIT_MASK_R_LEVEL_PULSE_SEL_8822C 0x3 +#define BIT_R_LEVEL_PULSE_SEL_8822C(x) \ + (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822C) \ + << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C) +#define BITS_R_LEVEL_PULSE_SEL_8822C \ + (BIT_MASK_R_LEVEL_PULSE_SEL_8822C << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C) +#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8822C(x) \ + ((x) & (~BITS_R_LEVEL_PULSE_SEL_8822C)) +#define BIT_GET_R_LEVEL_PULSE_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C) & \ + BIT_MASK_R_LEVEL_PULSE_SEL_8822C) +#define BIT_SET_R_LEVEL_PULSE_SEL_8822C(x, v) \ + (BIT_CLEAR_R_LEVEL_PULSE_SEL_8822C(x) | BIT_R_LEVEL_PULSE_SEL_8822C(v)) + +#define BIT_EN_LA_MAC_8822C BIT(2) +#define BIT_R_EN_IQDUMP_8822C BIT(1) +#define BIT_R_IQDATA_DUMP_8822C BIT(0) + +/* 2 REG_IQ_DUMP_1_8822C */ + +#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C 0 +#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C 0xffffffffL +#define BIT_R_WMAC_MASK_LA_MAC_1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C) \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C) +#define BITS_R_WMAC_MASK_LA_MAC_1_8822C \ + (BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C \ + << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C) +#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8822C(x) \ + ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8822C)) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C) & \ + BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C) +#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8822C(x) | \ + BIT_R_WMAC_MASK_LA_MAC_1_8822C(v)) + +/* 2 REG_IQ_DUMP_2_8822C */ + +#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C 0 +#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C 0xffffffffL +#define BIT_R_WMAC_MATCH_REF_MAC_2_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C) \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C) +#define BITS_R_WMAC_MATCH_REF_MAC_2_8822C \ + (BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C \ + << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C) +#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8822C(x) \ + ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8822C)) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C) & \ + BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C) +#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8822C(x) | \ + BIT_R_WMAC_MATCH_REF_MAC_2_8822C(v)) + +/* 2 REG_WMAC_FTM_CTL_8822C */ +#define BIT_RXFTM_TXACK_SC_8822C BIT(6) +#define BIT_RXFTM_TXACK_BW_8822C BIT(5) +#define BIT_RXFTM_EN_8822C BIT(3) +#define BIT_RXFTMREQ_BYDRV_8822C BIT(2) +#define BIT_RXFTMREQ_EN_8822C BIT(1) +#define BIT_FTM_EN_8822C BIT(0) + +/* 2 REG_WMAC_IQ_MDPK_FUNC_8822C */ + +/* 2 REG_WMAC_OPTION_FUNCTION_8822C */ + +#define BIT_SHIFT_R_OFDM_LEN_V1_8822C 16 +#define BIT_MASK_R_OFDM_LEN_V1_8822C 0xffff +#define BIT_R_OFDM_LEN_V1_8822C(x) \ + (((x) & BIT_MASK_R_OFDM_LEN_V1_8822C) << BIT_SHIFT_R_OFDM_LEN_V1_8822C) +#define BITS_R_OFDM_LEN_V1_8822C \ + (BIT_MASK_R_OFDM_LEN_V1_8822C << BIT_SHIFT_R_OFDM_LEN_V1_8822C) +#define BIT_CLEAR_R_OFDM_LEN_V1_8822C(x) ((x) & (~BITS_R_OFDM_LEN_V1_8822C)) +#define BIT_GET_R_OFDM_LEN_V1_8822C(x) \ + (((x) >> BIT_SHIFT_R_OFDM_LEN_V1_8822C) & BIT_MASK_R_OFDM_LEN_V1_8822C) +#define BIT_SET_R_OFDM_LEN_V1_8822C(x, v) \ + (BIT_CLEAR_R_OFDM_LEN_V1_8822C(x) | BIT_R_OFDM_LEN_V1_8822C(v)) + +#define BIT_SHIFT_R_CCK_LEN_8822C 0 +#define BIT_MASK_R_CCK_LEN_8822C 0xffff +#define BIT_R_CCK_LEN_8822C(x) \ + (((x) & BIT_MASK_R_CCK_LEN_8822C) << BIT_SHIFT_R_CCK_LEN_8822C) +#define BITS_R_CCK_LEN_8822C \ + (BIT_MASK_R_CCK_LEN_8822C << BIT_SHIFT_R_CCK_LEN_8822C) +#define BIT_CLEAR_R_CCK_LEN_8822C(x) ((x) & (~BITS_R_CCK_LEN_8822C)) +#define BIT_GET_R_CCK_LEN_8822C(x) \ + (((x) >> BIT_SHIFT_R_CCK_LEN_8822C) & BIT_MASK_R_CCK_LEN_8822C) +#define BIT_SET_R_CCK_LEN_8822C(x, v) \ + (BIT_CLEAR_R_CCK_LEN_8822C(x) | BIT_R_CCK_LEN_8822C(v)) + +/* 2 REG_WMAC_OPTION_FUNCTION_1_8822C */ + +#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C 24 +#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C 0xff +#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C) \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C) +#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8822C \ + (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C \ + << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C) +#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) \ + ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8822C)) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C) & \ + BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C) +#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) | \ + BIT_R_WMAC_RXFIFO_FULL_TH_1_8822C(v)) + +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8822C BIT(23) +#define BIT_R_WMAC_RXRST_DLY_1_8822C BIT(22) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8822C BIT(21) +#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8822C BIT(20) +#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8822C BIT(19) +#define BIT_R_WMAC_NDP_RST_1_8822C BIT(18) +#define BIT_R_WMAC_POWINT_EN_1_8822C BIT(17) +#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8822C BIT(16) +#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8822C BIT(15) +#define BIT_R_WMAC_PFIN_TOEN_1_8822C BIT(14) +#define BIT_R_WMAC_FIL_SECERR_1_8822C BIT(13) +#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8822C BIT(12) +#define BIT_R_WMAC_FIL_FCTYPE_1_8822C BIT(11) +#define BIT_R_WMAC_FIL_FCPROVER_1_8822C BIT(10) +#define BIT_R_WMAC_PHYSTS_SNIF_1_8822C BIT(9) +#define BIT_R_WMAC_PHYSTS_PLCP_1_8822C BIT(8) +#define BIT_R_MAC_TCR_VBONF_RD_1_8822C BIT(7) +#define BIT_R_WMAC_TCR_MPAR_NDP_1_8822C BIT(6) +#define BIT_R_WMAC_NDP_FILTER_1_8822C BIT(5) +#define BIT_R_WMAC_RXLEN_SEL_1_8822C BIT(4) +#define BIT_R_WMAC_RXLEN_SEL1_1_8822C BIT(3) +#define BIT_R_OFDM_FILTER_1_8822C BIT(2) +#define BIT_R_WMAC_CHK_OFDM_LEN_1_8822C BIT(1) +#define BIT_R_WMAC_CHK_CCK_LEN_1_8822C BIT(0) + +/* 2 REG_WMAC_OPTION_FUNCTION_2_8822C */ + +#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C 0 +#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C 0xffff +#define BIT_R_WMAC_RX_FIL_LEN_2_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C) \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C) +#define BITS_R_WMAC_RX_FIL_LEN_2_8822C \ + (BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C \ + << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C) +#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8822C(x) \ + ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8822C)) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C) & \ + BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C) +#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8822C(x) | \ + BIT_R_WMAC_RX_FIL_LEN_2_8822C(v)) + +/* 2 REG_RX_FILTER_FUNCTION_8822C */ +#define BIT_RXHANG_EN_8822C BIT(15) +#define BIT_R_WMAC_MHRDDY_LATCH_8822C BIT(14) +#define BIT_R_WMAC_MHRDDY_CLR_8822C BIT(13) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8822C BIT(12) +#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8822C BIT(11) +#define BIT_R_CHK_DELIMIT_LEN_8822C BIT(10) +#define BIT_R_REAPTER_ADDR_MATCH_8822C BIT(9) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8822C BIT(8) +#define BIT_R_LATCH_MACHRDY_8822C BIT(7) +#define BIT_R_WMAC_RXFIL_REND_8822C BIT(6) +#define BIT_R_WMAC_MPDURDY_CLR_8822C BIT(5) +#define BIT_R_WMAC_CLRRXSEC_8822C BIT(4) +#define BIT_R_WMAC_RXFIL_RDEL_8822C BIT(3) +#define BIT_R_WMAC_RXFIL_FCSE_8822C BIT(2) +#define BIT_R_WMAC_RXFIL_MESH_DEL_8822C BIT(1) +#define BIT_R_WMAC_RXFIL_MASKM_8822C BIT(0) + +/* 2 REG_NDP_SIG_8822C */ + +#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C 0 +#define BIT_MASK_R_WMAC_TXNDP_SIGB_8822C 0x1fffff +#define BIT_R_WMAC_TXNDP_SIGB_8822C(x) \ + (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822C) \ + << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C) +#define BITS_R_WMAC_TXNDP_SIGB_8822C \ + (BIT_MASK_R_WMAC_TXNDP_SIGB_8822C << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C) +#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822C(x) \ + ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8822C)) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8822C(x) \ + (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C) & \ + BIT_MASK_R_WMAC_TXNDP_SIGB_8822C) +#define BIT_SET_R_WMAC_TXNDP_SIGB_8822C(x, v) \ + (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822C(x) | BIT_R_WMAC_TXNDP_SIGB_8822C(v)) + +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822C */ + +#define BIT_SHIFT_R_MAC_DBG_SHIFT_8822C 8 +#define BIT_MASK_R_MAC_DBG_SHIFT_8822C 0x7 +#define BIT_R_MAC_DBG_SHIFT_8822C(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822C) \ + << BIT_SHIFT_R_MAC_DBG_SHIFT_8822C) +#define BITS_R_MAC_DBG_SHIFT_8822C \ + (BIT_MASK_R_MAC_DBG_SHIFT_8822C << BIT_SHIFT_R_MAC_DBG_SHIFT_8822C) +#define BIT_CLEAR_R_MAC_DBG_SHIFT_8822C(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8822C)) +#define BIT_GET_R_MAC_DBG_SHIFT_8822C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822C) & \ + BIT_MASK_R_MAC_DBG_SHIFT_8822C) +#define BIT_SET_R_MAC_DBG_SHIFT_8822C(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SHIFT_8822C(x) | BIT_R_MAC_DBG_SHIFT_8822C(v)) + +#define BIT_SHIFT_R_MAC_DBG_SEL_8822C 0 +#define BIT_MASK_R_MAC_DBG_SEL_8822C 0x3 +#define BIT_R_MAC_DBG_SEL_8822C(x) \ + (((x) & BIT_MASK_R_MAC_DBG_SEL_8822C) << BIT_SHIFT_R_MAC_DBG_SEL_8822C) +#define BITS_R_MAC_DBG_SEL_8822C \ + (BIT_MASK_R_MAC_DBG_SEL_8822C << BIT_SHIFT_R_MAC_DBG_SEL_8822C) +#define BIT_CLEAR_R_MAC_DBG_SEL_8822C(x) ((x) & (~BITS_R_MAC_DBG_SEL_8822C)) +#define BIT_GET_R_MAC_DBG_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822C) & BIT_MASK_R_MAC_DBG_SEL_8822C) +#define BIT_SET_R_MAC_DBG_SEL_8822C(x, v) \ + (BIT_CLEAR_R_MAC_DBG_SEL_8822C(x) | BIT_R_MAC_DBG_SEL_8822C(v)) + +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8822C */ + +#define BIT_SHIFT_R_MAC_DEBUG_1_8822C 0 +#define BIT_MASK_R_MAC_DEBUG_1_8822C 0xffffffffL +#define BIT_R_MAC_DEBUG_1_8822C(x) \ + (((x) & BIT_MASK_R_MAC_DEBUG_1_8822C) << BIT_SHIFT_R_MAC_DEBUG_1_8822C) +#define BITS_R_MAC_DEBUG_1_8822C \ + (BIT_MASK_R_MAC_DEBUG_1_8822C << BIT_SHIFT_R_MAC_DEBUG_1_8822C) +#define BIT_CLEAR_R_MAC_DEBUG_1_8822C(x) ((x) & (~BITS_R_MAC_DEBUG_1_8822C)) +#define BIT_GET_R_MAC_DEBUG_1_8822C(x) \ + (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8822C) & BIT_MASK_R_MAC_DEBUG_1_8822C) +#define BIT_SET_R_MAC_DEBUG_1_8822C(x, v) \ + (BIT_CLEAR_R_MAC_DEBUG_1_8822C(x) | BIT_R_MAC_DEBUG_1_8822C(v)) + +/* 2 REG_WSEC_OPTION_8822C */ +#define BIT_RXDEC_BM_MGNT_8822C BIT(22) +#define BIT_TXENC_BM_MGNT_8822C BIT(21) +#define BIT_RXDEC_UNI_MGNT_8822C BIT(20) +#define BIT_TXENC_UNI_MGNT_8822C BIT(19) +#define BIT_WMAC_SEC_MASKIV_8822C BIT(18) + +#define BIT_SHIFT_WMAC_SEC_PN_SEL_8822C 16 +#define BIT_MASK_WMAC_SEC_PN_SEL_8822C 0x3 +#define BIT_WMAC_SEC_PN_SEL_8822C(x) \ + (((x) & BIT_MASK_WMAC_SEC_PN_SEL_8822C) \ + << BIT_SHIFT_WMAC_SEC_PN_SEL_8822C) +#define BITS_WMAC_SEC_PN_SEL_8822C \ + (BIT_MASK_WMAC_SEC_PN_SEL_8822C << BIT_SHIFT_WMAC_SEC_PN_SEL_8822C) +#define BIT_CLEAR_WMAC_SEC_PN_SEL_8822C(x) ((x) & (~BITS_WMAC_SEC_PN_SEL_8822C)) +#define BIT_GET_WMAC_SEC_PN_SEL_8822C(x) \ + (((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL_8822C) & \ + BIT_MASK_WMAC_SEC_PN_SEL_8822C) +#define BIT_SET_WMAC_SEC_PN_SEL_8822C(x, v) \ + (BIT_CLEAR_WMAC_SEC_PN_SEL_8822C(x) | BIT_WMAC_SEC_PN_SEL_8822C(v)) + +#define BIT_SHIFT_BT_TIME_CNT_8822C 0 +#define BIT_MASK_BT_TIME_CNT_8822C 0xff +#define BIT_BT_TIME_CNT_8822C(x) \ + (((x) & BIT_MASK_BT_TIME_CNT_8822C) << BIT_SHIFT_BT_TIME_CNT_8822C) +#define BITS_BT_TIME_CNT_8822C \ + (BIT_MASK_BT_TIME_CNT_8822C << BIT_SHIFT_BT_TIME_CNT_8822C) +#define BIT_CLEAR_BT_TIME_CNT_8822C(x) ((x) & (~BITS_BT_TIME_CNT_8822C)) +#define BIT_GET_BT_TIME_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_BT_TIME_CNT_8822C) & BIT_MASK_BT_TIME_CNT_8822C) +#define BIT_SET_BT_TIME_CNT_8822C(x, v) \ + (BIT_CLEAR_BT_TIME_CNT_8822C(x) | BIT_BT_TIME_CNT_8822C(v)) + +/* 2 REG_RTS_ADDRESS_0_8822C */ + +/* 2 REG_RTS_ADDRESS_0_1_8822C */ + +/* 2 REG_RTS_ADDRESS_1_8822C */ + +/* 2 REG_RTS_ADDRESS_1_1_8822C */ + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822C */ +#define BIT_LTECOEX_ACCESS_START_V1_8822C BIT(31) +#define BIT_LTECOEX_WRITE_MODE_V1_8822C BIT(30) +#define BIT_LTECOEX_READY_BIT_V1_8822C BIT(29) + +#define BIT_SHIFT_WRITE_BYTE_EN_V1_8822C 16 +#define BIT_MASK_WRITE_BYTE_EN_V1_8822C 0xf +#define BIT_WRITE_BYTE_EN_V1_8822C(x) \ + (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822C) \ + << BIT_SHIFT_WRITE_BYTE_EN_V1_8822C) +#define BITS_WRITE_BYTE_EN_V1_8822C \ + (BIT_MASK_WRITE_BYTE_EN_V1_8822C << BIT_SHIFT_WRITE_BYTE_EN_V1_8822C) +#define BIT_CLEAR_WRITE_BYTE_EN_V1_8822C(x) \ + ((x) & (~BITS_WRITE_BYTE_EN_V1_8822C)) +#define BIT_GET_WRITE_BYTE_EN_V1_8822C(x) \ + (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822C) & \ + BIT_MASK_WRITE_BYTE_EN_V1_8822C) +#define BIT_SET_WRITE_BYTE_EN_V1_8822C(x, v) \ + (BIT_CLEAR_WRITE_BYTE_EN_V1_8822C(x) | BIT_WRITE_BYTE_EN_V1_8822C(v)) + +#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C 0 +#define BIT_MASK_LTECOEX_REG_ADDR_V1_8822C 0xffff +#define BIT_LTECOEX_REG_ADDR_V1_8822C(x) \ + (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822C) \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C) +#define BITS_LTECOEX_REG_ADDR_V1_8822C \ + (BIT_MASK_LTECOEX_REG_ADDR_V1_8822C \ + << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C) +#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822C(x) \ + ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8822C)) +#define BIT_GET_LTECOEX_REG_ADDR_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C) & \ + BIT_MASK_LTECOEX_REG_ADDR_V1_8822C) +#define BIT_SET_LTECOEX_REG_ADDR_V1_8822C(x, v) \ + (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822C(x) | \ + BIT_LTECOEX_REG_ADDR_V1_8822C(v)) + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822C */ + +#define BIT_SHIFT_LTECOEX_W_DATA_V1_8822C 0 +#define BIT_MASK_LTECOEX_W_DATA_V1_8822C 0xffffffffL +#define BIT_LTECOEX_W_DATA_V1_8822C(x) \ + (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822C) \ + << BIT_SHIFT_LTECOEX_W_DATA_V1_8822C) +#define BITS_LTECOEX_W_DATA_V1_8822C \ + (BIT_MASK_LTECOEX_W_DATA_V1_8822C << BIT_SHIFT_LTECOEX_W_DATA_V1_8822C) +#define BIT_CLEAR_LTECOEX_W_DATA_V1_8822C(x) \ + ((x) & (~BITS_LTECOEX_W_DATA_V1_8822C)) +#define BIT_GET_LTECOEX_W_DATA_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822C) & \ + BIT_MASK_LTECOEX_W_DATA_V1_8822C) +#define BIT_SET_LTECOEX_W_DATA_V1_8822C(x, v) \ + (BIT_CLEAR_LTECOEX_W_DATA_V1_8822C(x) | BIT_LTECOEX_W_DATA_V1_8822C(v)) + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C */ + +#define BIT_SHIFT_LTECOEX_R_DATA_V1_8822C 0 +#define BIT_MASK_LTECOEX_R_DATA_V1_8822C 0xffffffffL +#define BIT_LTECOEX_R_DATA_V1_8822C(x) \ + (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822C) \ + << BIT_SHIFT_LTECOEX_R_DATA_V1_8822C) +#define BITS_LTECOEX_R_DATA_V1_8822C \ + (BIT_MASK_LTECOEX_R_DATA_V1_8822C << BIT_SHIFT_LTECOEX_R_DATA_V1_8822C) +#define BIT_CLEAR_LTECOEX_R_DATA_V1_8822C(x) \ + ((x) & (~BITS_LTECOEX_R_DATA_V1_8822C)) +#define BIT_GET_LTECOEX_R_DATA_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822C) & \ + BIT_MASK_LTECOEX_R_DATA_V1_8822C) +#define BIT_SET_LTECOEX_R_DATA_V1_8822C(x, v) \ + (BIT_CLEAR_LTECOEX_R_DATA_V1_8822C(x) | BIT_LTECOEX_R_DATA_V1_8822C(v)) + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_NOT_VALID_8822C */ + +/* 2 REG_SDIO_TX_CTRL_8822C */ + +#define BIT_SHIFT_SDIO_INT_TIMEOUT_8822C 16 +#define BIT_MASK_SDIO_INT_TIMEOUT_8822C 0xffff +#define BIT_SDIO_INT_TIMEOUT_8822C(x) \ + (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822C) \ + << BIT_SHIFT_SDIO_INT_TIMEOUT_8822C) +#define BITS_SDIO_INT_TIMEOUT_8822C \ + (BIT_MASK_SDIO_INT_TIMEOUT_8822C << BIT_SHIFT_SDIO_INT_TIMEOUT_8822C) +#define BIT_CLEAR_SDIO_INT_TIMEOUT_8822C(x) \ + ((x) & (~BITS_SDIO_INT_TIMEOUT_8822C)) +#define BIT_GET_SDIO_INT_TIMEOUT_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822C) & \ + BIT_MASK_SDIO_INT_TIMEOUT_8822C) +#define BIT_SET_SDIO_INT_TIMEOUT_8822C(x, v) \ + (BIT_CLEAR_SDIO_INT_TIMEOUT_8822C(x) | BIT_SDIO_INT_TIMEOUT_8822C(v)) + +#define BIT_IO_ERR_STATUS_8822C BIT(15) +#define BIT_CMD53_W_MIX_8822C BIT(14) +#define BIT_CMD53_TX_FORMAT_8822C BIT(13) +#define BIT_CMD53_R_TIMEOUT_MASK_8822C BIT(12) + +#define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C 10 +#define BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C 0x3 +#define BIT_CMD53_R_TIMEOUT_UNIT_8822C(x) \ + (((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C) \ + << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C) +#define BITS_CMD53_R_TIMEOUT_UNIT_8822C \ + (BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C \ + << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C) +#define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT_8822C(x) \ + ((x) & (~BITS_CMD53_R_TIMEOUT_UNIT_8822C)) +#define BIT_GET_CMD53_R_TIMEOUT_UNIT_8822C(x) \ + (((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C) & \ + BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C) +#define BIT_SET_CMD53_R_TIMEOUT_UNIT_8822C(x, v) \ + (BIT_CLEAR_CMD53_R_TIMEOUT_UNIT_8822C(x) | \ + BIT_CMD53_R_TIMEOUT_UNIT_8822C(v)) + +#define BIT_REPLY_ERRCRC_IN_DATA_8822C BIT(9) +#define BIT_EN_CMD53_OVERLAP_8822C BIT(8) +#define BIT_REPLY_ERR_IN_R5_8822C BIT(7) +#define BIT_R18A_EN_8822C BIT(6) +#define BIT_SDIO_CMD_FORCE_VLD_8822C BIT(5) +#define BIT_INIT_CMD_EN_8822C BIT(4) +#define BIT_RXINT_READ_MASK_DIS_8822C BIT(3) +#define BIT_EN_RXDMA_MASK_INT_8822C BIT(2) +#define BIT_EN_MASK_TIMER_8822C BIT(1) +#define BIT_CMD_ERR_STOP_INT_EN_8822C BIT(0) + +/* 2 REG_SDIO_CMD11_VOL_SWITCH_8822C */ + +#define BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C 4 +#define BIT_MASK_CMD11_SEQ_END_DELAY_8822C 0xf +#define BIT_CMD11_SEQ_END_DELAY_8822C(x) \ + (((x) & BIT_MASK_CMD11_SEQ_END_DELAY_8822C) \ + << BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C) +#define BITS_CMD11_SEQ_END_DELAY_8822C \ + (BIT_MASK_CMD11_SEQ_END_DELAY_8822C \ + << BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C) +#define BIT_CLEAR_CMD11_SEQ_END_DELAY_8822C(x) \ + ((x) & (~BITS_CMD11_SEQ_END_DELAY_8822C)) +#define BIT_GET_CMD11_SEQ_END_DELAY_8822C(x) \ + (((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C) & \ + BIT_MASK_CMD11_SEQ_END_DELAY_8822C) +#define BIT_SET_CMD11_SEQ_END_DELAY_8822C(x, v) \ + (BIT_CLEAR_CMD11_SEQ_END_DELAY_8822C(x) | \ + BIT_CMD11_SEQ_END_DELAY_8822C(v)) + +#define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C 1 +#define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C 0x7 +#define BIT_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) \ + (((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C) \ + << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C) +#define BITS_CMD11_SEQ_SAMPLE_INTERVAL_8822C \ + (BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C \ + << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C) +#define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) \ + ((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL_8822C)) +#define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) \ + (((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C) & \ + BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C) +#define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x, v) \ + (BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) | \ + BIT_CMD11_SEQ_SAMPLE_INTERVAL_8822C(v)) + +#define BIT_CMD11_SEQ_EN_8822C BIT(0) + +/* 2 REG_SDIO_CTRL_8822C */ +#define BIT_SIG_OUT_PH_8822C BIT(0) + +/* 2 REG_SDIO_DRIVING_8822C */ + +#define BIT_SHIFT_SDIO_DRV_TYPE_D_8822C 12 +#define BIT_MASK_SDIO_DRV_TYPE_D_8822C 0xf +#define BIT_SDIO_DRV_TYPE_D_8822C(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_D_8822C) \ + << BIT_SHIFT_SDIO_DRV_TYPE_D_8822C) +#define BITS_SDIO_DRV_TYPE_D_8822C \ + (BIT_MASK_SDIO_DRV_TYPE_D_8822C << BIT_SHIFT_SDIO_DRV_TYPE_D_8822C) +#define BIT_CLEAR_SDIO_DRV_TYPE_D_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_D_8822C)) +#define BIT_GET_SDIO_DRV_TYPE_D_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D_8822C) & \ + BIT_MASK_SDIO_DRV_TYPE_D_8822C) +#define BIT_SET_SDIO_DRV_TYPE_D_8822C(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_D_8822C(x) | BIT_SDIO_DRV_TYPE_D_8822C(v)) + +#define BIT_SHIFT_SDIO_DRV_TYPE_C_8822C 8 +#define BIT_MASK_SDIO_DRV_TYPE_C_8822C 0xf +#define BIT_SDIO_DRV_TYPE_C_8822C(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_C_8822C) \ + << BIT_SHIFT_SDIO_DRV_TYPE_C_8822C) +#define BITS_SDIO_DRV_TYPE_C_8822C \ + (BIT_MASK_SDIO_DRV_TYPE_C_8822C << BIT_SHIFT_SDIO_DRV_TYPE_C_8822C) +#define BIT_CLEAR_SDIO_DRV_TYPE_C_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_C_8822C)) +#define BIT_GET_SDIO_DRV_TYPE_C_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C_8822C) & \ + BIT_MASK_SDIO_DRV_TYPE_C_8822C) +#define BIT_SET_SDIO_DRV_TYPE_C_8822C(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_C_8822C(x) | BIT_SDIO_DRV_TYPE_C_8822C(v)) + +#define BIT_SHIFT_SDIO_DRV_TYPE_B_8822C 4 +#define BIT_MASK_SDIO_DRV_TYPE_B_8822C 0xf +#define BIT_SDIO_DRV_TYPE_B_8822C(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_B_8822C) \ + << BIT_SHIFT_SDIO_DRV_TYPE_B_8822C) +#define BITS_SDIO_DRV_TYPE_B_8822C \ + (BIT_MASK_SDIO_DRV_TYPE_B_8822C << BIT_SHIFT_SDIO_DRV_TYPE_B_8822C) +#define BIT_CLEAR_SDIO_DRV_TYPE_B_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_B_8822C)) +#define BIT_GET_SDIO_DRV_TYPE_B_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B_8822C) & \ + BIT_MASK_SDIO_DRV_TYPE_B_8822C) +#define BIT_SET_SDIO_DRV_TYPE_B_8822C(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_B_8822C(x) | BIT_SDIO_DRV_TYPE_B_8822C(v)) + +#define BIT_SHIFT_SDIO_DRV_TYPE_A_8822C 0 +#define BIT_MASK_SDIO_DRV_TYPE_A_8822C 0xf +#define BIT_SDIO_DRV_TYPE_A_8822C(x) \ + (((x) & BIT_MASK_SDIO_DRV_TYPE_A_8822C) \ + << BIT_SHIFT_SDIO_DRV_TYPE_A_8822C) +#define BITS_SDIO_DRV_TYPE_A_8822C \ + (BIT_MASK_SDIO_DRV_TYPE_A_8822C << BIT_SHIFT_SDIO_DRV_TYPE_A_8822C) +#define BIT_CLEAR_SDIO_DRV_TYPE_A_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_A_8822C)) +#define BIT_GET_SDIO_DRV_TYPE_A_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A_8822C) & \ + BIT_MASK_SDIO_DRV_TYPE_A_8822C) +#define BIT_SET_SDIO_DRV_TYPE_A_8822C(x, v) \ + (BIT_CLEAR_SDIO_DRV_TYPE_A_8822C(x) | BIT_SDIO_DRV_TYPE_A_8822C(v)) + +/* 2 REG_SDIO_MONITOR_8822C */ + +#define BIT_SHIFT_SDIO_INT_START_8822C 0 +#define BIT_MASK_SDIO_INT_START_8822C 0xffffffffL +#define BIT_SDIO_INT_START_8822C(x) \ + (((x) & BIT_MASK_SDIO_INT_START_8822C) \ + << BIT_SHIFT_SDIO_INT_START_8822C) +#define BITS_SDIO_INT_START_8822C \ + (BIT_MASK_SDIO_INT_START_8822C << BIT_SHIFT_SDIO_INT_START_8822C) +#define BIT_CLEAR_SDIO_INT_START_8822C(x) ((x) & (~BITS_SDIO_INT_START_8822C)) +#define BIT_GET_SDIO_INT_START_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_INT_START_8822C) & \ + BIT_MASK_SDIO_INT_START_8822C) +#define BIT_SET_SDIO_INT_START_8822C(x, v) \ + (BIT_CLEAR_SDIO_INT_START_8822C(x) | BIT_SDIO_INT_START_8822C(v)) + +/* 2 REG_SDIO_MONITOR_2_8822C */ +#define BIT_CMD53_WT_EN_8822C BIT(23) + +#define BIT_SHIFT_SDIO_CLK_MONITOR_8822C 21 +#define BIT_MASK_SDIO_CLK_MONITOR_8822C 0x3 +#define BIT_SDIO_CLK_MONITOR_8822C(x) \ + (((x) & BIT_MASK_SDIO_CLK_MONITOR_8822C) \ + << BIT_SHIFT_SDIO_CLK_MONITOR_8822C) +#define BITS_SDIO_CLK_MONITOR_8822C \ + (BIT_MASK_SDIO_CLK_MONITOR_8822C << BIT_SHIFT_SDIO_CLK_MONITOR_8822C) +#define BIT_CLEAR_SDIO_CLK_MONITOR_8822C(x) \ + ((x) & (~BITS_SDIO_CLK_MONITOR_8822C)) +#define BIT_GET_SDIO_CLK_MONITOR_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_CLK_MONITOR_8822C) & \ + BIT_MASK_SDIO_CLK_MONITOR_8822C) +#define BIT_SET_SDIO_CLK_MONITOR_8822C(x, v) \ + (BIT_CLEAR_SDIO_CLK_MONITOR_8822C(x) | BIT_SDIO_CLK_MONITOR_8822C(v)) + +#define BIT_SHIFT_SDIO_CLK_CNT_8822C 0 +#define BIT_MASK_SDIO_CLK_CNT_8822C 0x1fffff +#define BIT_SDIO_CLK_CNT_8822C(x) \ + (((x) & BIT_MASK_SDIO_CLK_CNT_8822C) << BIT_SHIFT_SDIO_CLK_CNT_8822C) +#define BITS_SDIO_CLK_CNT_8822C \ + (BIT_MASK_SDIO_CLK_CNT_8822C << BIT_SHIFT_SDIO_CLK_CNT_8822C) +#define BIT_CLEAR_SDIO_CLK_CNT_8822C(x) ((x) & (~BITS_SDIO_CLK_CNT_8822C)) +#define BIT_GET_SDIO_CLK_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_CLK_CNT_8822C) & BIT_MASK_SDIO_CLK_CNT_8822C) +#define BIT_SET_SDIO_CLK_CNT_8822C(x, v) \ + (BIT_CLEAR_SDIO_CLK_CNT_8822C(x) | BIT_SDIO_CLK_CNT_8822C(v)) + +/* 2 REG_SDIO_HIMR_8822C */ +#define BIT_SDIO_CRCERR_MSK_8822C BIT(31) +#define BIT_SDIO_HSISR3_IND_MSK_8822C BIT(30) +#define BIT_SDIO_HSISR2_IND_MSK_8822C BIT(29) +#define BIT_SDIO_HEISR_IND_MSK_8822C BIT(28) +#define BIT_SDIO_CTWEND_MSK_8822C BIT(27) +#define BIT_SDIO_ATIMEND_E_MSK_8822C BIT(26) +#define BIT_SDIIO_ATIMEND_MSK_8822C BIT(25) +#define BIT_SDIO_OCPINT_MSK_8822C BIT(24) +#define BIT_SDIO_PSTIMEOUT_MSK_8822C BIT(23) +#define BIT_SDIO_GTINT4_MSK_8822C BIT(22) +#define BIT_SDIO_GTINT3_MSK_8822C BIT(21) +#define BIT_SDIO_HSISR_IND_MSK_8822C BIT(20) +#define BIT_SDIO_CPWM2_MSK_8822C BIT(19) +#define BIT_SDIO_CPWM1_MSK_8822C BIT(18) +#define BIT_SDIO_C2HCMD_INT_MSK_8822C BIT(17) +#define BIT_SDIO_BCNERLY_INT_MSK_8822C BIT(16) +#define BIT_SDIO_TXBCNERR_MSK_8822C BIT(7) +#define BIT_SDIO_TXBCNOK_MSK_8822C BIT(6) +#define BIT_SDIO_RXFOVW_MSK_8822C BIT(5) +#define BIT_SDIO_TXFOVW_MSK_8822C BIT(4) +#define BIT_SDIO_RXERR_MSK_8822C BIT(3) +#define BIT_SDIO_TXERR_MSK_8822C BIT(2) +#define BIT_SDIO_AVAL_MSK_8822C BIT(1) +#define BIT_RX_REQUEST_MSK_8822C BIT(0) + +/* 2 REG_SDIO_HISR_8822C */ +#define BIT_SDIO_CRCERR_8822C BIT(31) +#define BIT_SDIO_HSISR3_IND_8822C BIT(30) +#define BIT_SDIO_HSISR2_IND_8822C BIT(29) +#define BIT_SDIO_HEISR_IND_8822C BIT(28) +#define BIT_SDIO_CTWEND_8822C BIT(27) +#define BIT_SDIO_ATIMEND_E_8822C BIT(26) +#define BIT_SDIO_ATIMEND_8822C BIT(25) +#define BIT_SDIO_OCPINT_8822C BIT(24) +#define BIT_SDIO_PSTIMEOUT_8822C BIT(23) +#define BIT_SDIO_GTINT4_8822C BIT(22) +#define BIT_SDIO_GTINT3_8822C BIT(21) +#define BIT_SDIO_HSISR_IND_8822C BIT(20) +#define BIT_SDIO_CPWM2_8822C BIT(19) +#define BIT_SDIO_CPWM1_8822C BIT(18) +#define BIT_SDIO_C2HCMD_INT_8822C BIT(17) +#define BIT_SDIO_BCNERLY_INT_8822C BIT(16) +#define BIT_SDIO_TXBCNERR_8822C BIT(7) +#define BIT_SDIO_TXBCNOK_8822C BIT(6) +#define BIT_SDIO_RXFOVW_8822C BIT(5) +#define BIT_SDIO_TXFOVW_8822C BIT(4) +#define BIT_SDIO_RXERR_8822C BIT(3) +#define BIT_SDIO_TXERR_8822C BIT(2) +#define BIT_SDIO_AVAL_8822C BIT(1) +#define BIT_RX_REQUEST_8822C BIT(0) + +/* 2 REG_SDIO_RX_REQ_LEN_8822C */ + +#define BIT_SHIFT_RX_REQ_LEN_V1_8822C 0 +#define BIT_MASK_RX_REQ_LEN_V1_8822C 0x3ffff +#define BIT_RX_REQ_LEN_V1_8822C(x) \ + (((x) & BIT_MASK_RX_REQ_LEN_V1_8822C) << BIT_SHIFT_RX_REQ_LEN_V1_8822C) +#define BITS_RX_REQ_LEN_V1_8822C \ + (BIT_MASK_RX_REQ_LEN_V1_8822C << BIT_SHIFT_RX_REQ_LEN_V1_8822C) +#define BIT_CLEAR_RX_REQ_LEN_V1_8822C(x) ((x) & (~BITS_RX_REQ_LEN_V1_8822C)) +#define BIT_GET_RX_REQ_LEN_V1_8822C(x) \ + (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822C) & BIT_MASK_RX_REQ_LEN_V1_8822C) +#define BIT_SET_RX_REQ_LEN_V1_8822C(x, v) \ + (BIT_CLEAR_RX_REQ_LEN_V1_8822C(x) | BIT_RX_REQ_LEN_V1_8822C(v)) + +/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822C */ + +#define BIT_SHIFT_FREE_TXPG_SEQ_8822C 0 +#define BIT_MASK_FREE_TXPG_SEQ_8822C 0xff +#define BIT_FREE_TXPG_SEQ_8822C(x) \ + (((x) & BIT_MASK_FREE_TXPG_SEQ_8822C) << BIT_SHIFT_FREE_TXPG_SEQ_8822C) +#define BITS_FREE_TXPG_SEQ_8822C \ + (BIT_MASK_FREE_TXPG_SEQ_8822C << BIT_SHIFT_FREE_TXPG_SEQ_8822C) +#define BIT_CLEAR_FREE_TXPG_SEQ_8822C(x) ((x) & (~BITS_FREE_TXPG_SEQ_8822C)) +#define BIT_GET_FREE_TXPG_SEQ_8822C(x) \ + (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822C) & BIT_MASK_FREE_TXPG_SEQ_8822C) +#define BIT_SET_FREE_TXPG_SEQ_8822C(x, v) \ + (BIT_CLEAR_FREE_TXPG_SEQ_8822C(x) | BIT_FREE_TXPG_SEQ_8822C(v)) + +/* 2 REG_SDIO_FREE_TXPG_8822C */ + +#define BIT_SHIFT_MID_FREEPG_V1_8822C 16 +#define BIT_MASK_MID_FREEPG_V1_8822C 0xfff +#define BIT_MID_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_MID_FREEPG_V1_8822C) << BIT_SHIFT_MID_FREEPG_V1_8822C) +#define BITS_MID_FREEPG_V1_8822C \ + (BIT_MASK_MID_FREEPG_V1_8822C << BIT_SHIFT_MID_FREEPG_V1_8822C) +#define BIT_CLEAR_MID_FREEPG_V1_8822C(x) ((x) & (~BITS_MID_FREEPG_V1_8822C)) +#define BIT_GET_MID_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_MID_FREEPG_V1_8822C) & BIT_MASK_MID_FREEPG_V1_8822C) +#define BIT_SET_MID_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_MID_FREEPG_V1_8822C(x) | BIT_MID_FREEPG_V1_8822C(v)) + +#define BIT_SHIFT_HIQ_FREEPG_V1_8822C 0 +#define BIT_MASK_HIQ_FREEPG_V1_8822C 0xfff +#define BIT_HIQ_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_HIQ_FREEPG_V1_8822C) << BIT_SHIFT_HIQ_FREEPG_V1_8822C) +#define BITS_HIQ_FREEPG_V1_8822C \ + (BIT_MASK_HIQ_FREEPG_V1_8822C << BIT_SHIFT_HIQ_FREEPG_V1_8822C) +#define BIT_CLEAR_HIQ_FREEPG_V1_8822C(x) ((x) & (~BITS_HIQ_FREEPG_V1_8822C)) +#define BIT_GET_HIQ_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822C) & BIT_MASK_HIQ_FREEPG_V1_8822C) +#define BIT_SET_HIQ_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_HIQ_FREEPG_V1_8822C(x) | BIT_HIQ_FREEPG_V1_8822C(v)) + +/* 2 REG_SDIO_FREE_TXPG2_8822C */ + +#define BIT_SHIFT_PUB_FREEPG_V1_8822C 16 +#define BIT_MASK_PUB_FREEPG_V1_8822C 0xfff +#define BIT_PUB_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_PUB_FREEPG_V1_8822C) << BIT_SHIFT_PUB_FREEPG_V1_8822C) +#define BITS_PUB_FREEPG_V1_8822C \ + (BIT_MASK_PUB_FREEPG_V1_8822C << BIT_SHIFT_PUB_FREEPG_V1_8822C) +#define BIT_CLEAR_PUB_FREEPG_V1_8822C(x) ((x) & (~BITS_PUB_FREEPG_V1_8822C)) +#define BIT_GET_PUB_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822C) & BIT_MASK_PUB_FREEPG_V1_8822C) +#define BIT_SET_PUB_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_PUB_FREEPG_V1_8822C(x) | BIT_PUB_FREEPG_V1_8822C(v)) + +#define BIT_SHIFT_LOW_FREEPG_V1_8822C 0 +#define BIT_MASK_LOW_FREEPG_V1_8822C 0xfff +#define BIT_LOW_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_LOW_FREEPG_V1_8822C) << BIT_SHIFT_LOW_FREEPG_V1_8822C) +#define BITS_LOW_FREEPG_V1_8822C \ + (BIT_MASK_LOW_FREEPG_V1_8822C << BIT_SHIFT_LOW_FREEPG_V1_8822C) +#define BIT_CLEAR_LOW_FREEPG_V1_8822C(x) ((x) & (~BITS_LOW_FREEPG_V1_8822C)) +#define BIT_GET_LOW_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822C) & BIT_MASK_LOW_FREEPG_V1_8822C) +#define BIT_SET_LOW_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_LOW_FREEPG_V1_8822C(x) | BIT_LOW_FREEPG_V1_8822C(v)) + +/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822C */ + +#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C 24 +#define BIT_MASK_NOAC_OQT_FREEPG_V1_8822C 0xff +#define BIT_NOAC_OQT_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822C) \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C) +#define BITS_NOAC_OQT_FREEPG_V1_8822C \ + (BIT_MASK_NOAC_OQT_FREEPG_V1_8822C \ + << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C) +#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822C(x) \ + ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8822C)) +#define BIT_GET_NOAC_OQT_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C) & \ + BIT_MASK_NOAC_OQT_FREEPG_V1_8822C) +#define BIT_SET_NOAC_OQT_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822C(x) | \ + BIT_NOAC_OQT_FREEPG_V1_8822C(v)) + +#define BIT_SHIFT_AC_OQT_FREEPG_V1_8822C 16 +#define BIT_MASK_AC_OQT_FREEPG_V1_8822C 0xff +#define BIT_AC_OQT_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822C) \ + << BIT_SHIFT_AC_OQT_FREEPG_V1_8822C) +#define BITS_AC_OQT_FREEPG_V1_8822C \ + (BIT_MASK_AC_OQT_FREEPG_V1_8822C << BIT_SHIFT_AC_OQT_FREEPG_V1_8822C) +#define BIT_CLEAR_AC_OQT_FREEPG_V1_8822C(x) \ + ((x) & (~BITS_AC_OQT_FREEPG_V1_8822C)) +#define BIT_GET_AC_OQT_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822C) & \ + BIT_MASK_AC_OQT_FREEPG_V1_8822C) +#define BIT_SET_AC_OQT_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_AC_OQT_FREEPG_V1_8822C(x) | BIT_AC_OQT_FREEPG_V1_8822C(v)) + +#define BIT_SHIFT_EXQ_FREEPG_V1_8822C 0 +#define BIT_MASK_EXQ_FREEPG_V1_8822C 0xfff +#define BIT_EXQ_FREEPG_V1_8822C(x) \ + (((x) & BIT_MASK_EXQ_FREEPG_V1_8822C) << BIT_SHIFT_EXQ_FREEPG_V1_8822C) +#define BITS_EXQ_FREEPG_V1_8822C \ + (BIT_MASK_EXQ_FREEPG_V1_8822C << BIT_SHIFT_EXQ_FREEPG_V1_8822C) +#define BIT_CLEAR_EXQ_FREEPG_V1_8822C(x) ((x) & (~BITS_EXQ_FREEPG_V1_8822C)) +#define BIT_GET_EXQ_FREEPG_V1_8822C(x) \ + (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822C) & BIT_MASK_EXQ_FREEPG_V1_8822C) +#define BIT_SET_EXQ_FREEPG_V1_8822C(x, v) \ + (BIT_CLEAR_EXQ_FREEPG_V1_8822C(x) | BIT_EXQ_FREEPG_V1_8822C(v)) + +/* 2 REG_SDIO_TXPKT_EMPTY_8822C */ +#define BIT_SDIO_BCNQ_EMPTY_8822C BIT(11) +#define BIT_SDIO_HQQ_EMPTY_8822C BIT(10) +#define BIT_SDIO_MQQ_EMPTY_8822C BIT(9) +#define BIT_SDIO_MGQ_CPU_EMPTY_8822C BIT(8) +#define BIT_SDIO_AC7Q_EMPTY_8822C BIT(7) +#define BIT_SDIO_AC6Q_EMPTY_8822C BIT(6) +#define BIT_SDIO_AC5Q_EMPTY_8822C BIT(5) +#define BIT_SDIO_AC4Q_EMPTY_8822C BIT(4) +#define BIT_SDIO_AC3Q_EMPTY_8822C BIT(3) +#define BIT_SDIO_AC2Q_EMPTY_8822C BIT(2) +#define BIT_SDIO_AC1Q_EMPTY_8822C BIT(1) +#define BIT_SDIO_AC0Q_EMPTY_8822C BIT(0) + +/* 2 REG_SDIO_HTSFR_INFO_8822C */ + +#define BIT_SHIFT_HTSFR1_8822C 16 +#define BIT_MASK_HTSFR1_8822C 0xffff +#define BIT_HTSFR1_8822C(x) \ + (((x) & BIT_MASK_HTSFR1_8822C) << BIT_SHIFT_HTSFR1_8822C) +#define BITS_HTSFR1_8822C (BIT_MASK_HTSFR1_8822C << BIT_SHIFT_HTSFR1_8822C) +#define BIT_CLEAR_HTSFR1_8822C(x) ((x) & (~BITS_HTSFR1_8822C)) +#define BIT_GET_HTSFR1_8822C(x) \ + (((x) >> BIT_SHIFT_HTSFR1_8822C) & BIT_MASK_HTSFR1_8822C) +#define BIT_SET_HTSFR1_8822C(x, v) \ + (BIT_CLEAR_HTSFR1_8822C(x) | BIT_HTSFR1_8822C(v)) + +#define BIT_SHIFT_HTSFR0_8822C 0 +#define BIT_MASK_HTSFR0_8822C 0xffff +#define BIT_HTSFR0_8822C(x) \ + (((x) & BIT_MASK_HTSFR0_8822C) << BIT_SHIFT_HTSFR0_8822C) +#define BITS_HTSFR0_8822C (BIT_MASK_HTSFR0_8822C << BIT_SHIFT_HTSFR0_8822C) +#define BIT_CLEAR_HTSFR0_8822C(x) ((x) & (~BITS_HTSFR0_8822C)) +#define BIT_GET_HTSFR0_8822C(x) \ + (((x) >> BIT_SHIFT_HTSFR0_8822C) & BIT_MASK_HTSFR0_8822C) +#define BIT_SET_HTSFR0_8822C(x, v) \ + (BIT_CLEAR_HTSFR0_8822C(x) | BIT_HTSFR0_8822C(v)) + +/* 2 REG_SDIO_HCPWM1_V2_8822C */ +#define BIT_TOGGLE_8822C BIT(7) +#define BIT_CUR_PS_8822C BIT(0) + +/* 2 REG_SDIO_HCPWM2_V2_8822C */ + +/* 2 REG_SDIO_INDIRECT_REG_CFG_8822C */ +#define BIT_INDIRECT_REG_RDY_8822C BIT(20) +#define BIT_INDIRECT_REG_R_8822C BIT(19) +#define BIT_INDIRECT_REG_W_8822C BIT(18) + +#define BIT_SHIFT_INDIRECT_REG_SIZE_8822C 16 +#define BIT_MASK_INDIRECT_REG_SIZE_8822C 0x3 +#define BIT_INDIRECT_REG_SIZE_8822C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_SIZE_8822C) \ + << BIT_SHIFT_INDIRECT_REG_SIZE_8822C) +#define BITS_INDIRECT_REG_SIZE_8822C \ + (BIT_MASK_INDIRECT_REG_SIZE_8822C << BIT_SHIFT_INDIRECT_REG_SIZE_8822C) +#define BIT_CLEAR_INDIRECT_REG_SIZE_8822C(x) \ + ((x) & (~BITS_INDIRECT_REG_SIZE_8822C)) +#define BIT_GET_INDIRECT_REG_SIZE_8822C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822C) & \ + BIT_MASK_INDIRECT_REG_SIZE_8822C) +#define BIT_SET_INDIRECT_REG_SIZE_8822C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_SIZE_8822C(x) | BIT_INDIRECT_REG_SIZE_8822C(v)) + +#define BIT_SHIFT_INDIRECT_REG_ADDR_8822C 0 +#define BIT_MASK_INDIRECT_REG_ADDR_8822C 0xffff +#define BIT_INDIRECT_REG_ADDR_8822C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_ADDR_8822C) \ + << BIT_SHIFT_INDIRECT_REG_ADDR_8822C) +#define BITS_INDIRECT_REG_ADDR_8822C \ + (BIT_MASK_INDIRECT_REG_ADDR_8822C << BIT_SHIFT_INDIRECT_REG_ADDR_8822C) +#define BIT_CLEAR_INDIRECT_REG_ADDR_8822C(x) \ + ((x) & (~BITS_INDIRECT_REG_ADDR_8822C)) +#define BIT_GET_INDIRECT_REG_ADDR_8822C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822C) & \ + BIT_MASK_INDIRECT_REG_ADDR_8822C) +#define BIT_SET_INDIRECT_REG_ADDR_8822C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_ADDR_8822C(x) | BIT_INDIRECT_REG_ADDR_8822C(v)) + +/* 2 REG_SDIO_INDIRECT_REG_DATA_8822C */ + +#define BIT_SHIFT_INDIRECT_REG_DATA_8822C 0 +#define BIT_MASK_INDIRECT_REG_DATA_8822C 0xffffffffL +#define BIT_INDIRECT_REG_DATA_8822C(x) \ + (((x) & BIT_MASK_INDIRECT_REG_DATA_8822C) \ + << BIT_SHIFT_INDIRECT_REG_DATA_8822C) +#define BITS_INDIRECT_REG_DATA_8822C \ + (BIT_MASK_INDIRECT_REG_DATA_8822C << BIT_SHIFT_INDIRECT_REG_DATA_8822C) +#define BIT_CLEAR_INDIRECT_REG_DATA_8822C(x) \ + ((x) & (~BITS_INDIRECT_REG_DATA_8822C)) +#define BIT_GET_INDIRECT_REG_DATA_8822C(x) \ + (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822C) & \ + BIT_MASK_INDIRECT_REG_DATA_8822C) +#define BIT_SET_INDIRECT_REG_DATA_8822C(x, v) \ + (BIT_CLEAR_INDIRECT_REG_DATA_8822C(x) | BIT_INDIRECT_REG_DATA_8822C(v)) + +/* 2 REG_SDIO_H2C_8822C */ + +#define BIT_SHIFT_SDIO_H2C_MSG_8822C 0 +#define BIT_MASK_SDIO_H2C_MSG_8822C 0xffffffffL +#define BIT_SDIO_H2C_MSG_8822C(x) \ + (((x) & BIT_MASK_SDIO_H2C_MSG_8822C) << BIT_SHIFT_SDIO_H2C_MSG_8822C) +#define BITS_SDIO_H2C_MSG_8822C \ + (BIT_MASK_SDIO_H2C_MSG_8822C << BIT_SHIFT_SDIO_H2C_MSG_8822C) +#define BIT_CLEAR_SDIO_H2C_MSG_8822C(x) ((x) & (~BITS_SDIO_H2C_MSG_8822C)) +#define BIT_GET_SDIO_H2C_MSG_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822C) & BIT_MASK_SDIO_H2C_MSG_8822C) +#define BIT_SET_SDIO_H2C_MSG_8822C(x, v) \ + (BIT_CLEAR_SDIO_H2C_MSG_8822C(x) | BIT_SDIO_H2C_MSG_8822C(v)) + +/* 2 REG_SDIO_C2H_8822C */ + +#define BIT_SHIFT_SDIO_C2H_MSG_8822C 0 +#define BIT_MASK_SDIO_C2H_MSG_8822C 0xffffffffL +#define BIT_SDIO_C2H_MSG_8822C(x) \ + (((x) & BIT_MASK_SDIO_C2H_MSG_8822C) << BIT_SHIFT_SDIO_C2H_MSG_8822C) +#define BITS_SDIO_C2H_MSG_8822C \ + (BIT_MASK_SDIO_C2H_MSG_8822C << BIT_SHIFT_SDIO_C2H_MSG_8822C) +#define BIT_CLEAR_SDIO_C2H_MSG_8822C(x) ((x) & (~BITS_SDIO_C2H_MSG_8822C)) +#define BIT_GET_SDIO_C2H_MSG_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822C) & BIT_MASK_SDIO_C2H_MSG_8822C) +#define BIT_SET_SDIO_C2H_MSG_8822C(x, v) \ + (BIT_CLEAR_SDIO_C2H_MSG_8822C(x) | BIT_SDIO_C2H_MSG_8822C(v)) + +/* 2 REG_SDIO_HRPWM1_8822C */ +#define BIT_TOGGLE_8822C BIT(7) +#define BIT_ACK_8822C BIT(6) +#define BIT_REQ_PS_8822C BIT(0) + +/* 2 REG_SDIO_HRPWM2_8822C */ + +/* 2 REG_SDIO_HPS_CLKR_8822C */ + +/* 2 REG_SDIO_BUS_CTRL_8822C */ +#define BIT_INT_MASK_DIS_8822C BIT(4) +#define BIT_PAD_CLK_XHGE_EN_8822C BIT(3) +#define BIT_INTER_CLK_EN_8822C BIT(2) +#define BIT_EN_RPT_TXCRC_8822C BIT(1) +#define BIT_DIS_RXDMA_STS_8822C BIT(0) + +/* 2 REG_SDIO_HSUS_CTRL_8822C */ +#define BIT_INTR_CTRL_8822C BIT(4) +#define BIT_SDIO_VOLTAGE_8822C BIT(3) +#define BIT_BYPASS_INIT_8822C BIT(2) +#define BIT_HCI_RESUME_RDY_8822C BIT(1) +#define BIT_HCI_SUS_REQ_8822C BIT(0) + +/* 2 REG_SDIO_RESPONSE_TIMER_8822C */ + +#define BIT_SHIFT_CMDIN_2RESP_TIMER_8822C 0 +#define BIT_MASK_CMDIN_2RESP_TIMER_8822C 0xffff +#define BIT_CMDIN_2RESP_TIMER_8822C(x) \ + (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822C) \ + << BIT_SHIFT_CMDIN_2RESP_TIMER_8822C) +#define BITS_CMDIN_2RESP_TIMER_8822C \ + (BIT_MASK_CMDIN_2RESP_TIMER_8822C << BIT_SHIFT_CMDIN_2RESP_TIMER_8822C) +#define BIT_CLEAR_CMDIN_2RESP_TIMER_8822C(x) \ + ((x) & (~BITS_CMDIN_2RESP_TIMER_8822C)) +#define BIT_GET_CMDIN_2RESP_TIMER_8822C(x) \ + (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822C) & \ + BIT_MASK_CMDIN_2RESP_TIMER_8822C) +#define BIT_SET_CMDIN_2RESP_TIMER_8822C(x, v) \ + (BIT_CLEAR_CMDIN_2RESP_TIMER_8822C(x) | BIT_CMDIN_2RESP_TIMER_8822C(v)) + +/* 2 REG_SDIO_CMD_CRC_8822C */ + +#define BIT_SHIFT_SDIO_CMD_CRC_V1_8822C 0 +#define BIT_MASK_SDIO_CMD_CRC_V1_8822C 0xff +#define BIT_SDIO_CMD_CRC_V1_8822C(x) \ + (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822C) \ + << BIT_SHIFT_SDIO_CMD_CRC_V1_8822C) +#define BITS_SDIO_CMD_CRC_V1_8822C \ + (BIT_MASK_SDIO_CMD_CRC_V1_8822C << BIT_SHIFT_SDIO_CMD_CRC_V1_8822C) +#define BIT_CLEAR_SDIO_CMD_CRC_V1_8822C(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8822C)) +#define BIT_GET_SDIO_CMD_CRC_V1_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822C) & \ + BIT_MASK_SDIO_CMD_CRC_V1_8822C) +#define BIT_SET_SDIO_CMD_CRC_V1_8822C(x, v) \ + (BIT_CLEAR_SDIO_CMD_CRC_V1_8822C(x) | BIT_SDIO_CMD_CRC_V1_8822C(v)) + +/* 2 REG_SDIO_HSISR_8822C */ +#define BIT_DRV_WLAN_INT_CLR_8822C BIT(1) +#define BIT_DRV_WLAN_INT_8822C BIT(0) + +/* 2 REG_SDIO_HSIMR_8822C */ +#define BIT_HISR_MASK_8822C BIT(0) + +/* 2 REG_SDIO_DIOERR_RPT_8822C */ +#define BIT_SDIO_PAGE_ERR_8822C BIT(0) + +/* 2 REG_SDIO_CMD_ERRCNT_8822C */ + +#define BIT_SHIFT_CMD_CRC_ERR_CNT_8822C 0 +#define BIT_MASK_CMD_CRC_ERR_CNT_8822C 0xff +#define BIT_CMD_CRC_ERR_CNT_8822C(x) \ + (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822C) \ + << BIT_SHIFT_CMD_CRC_ERR_CNT_8822C) +#define BITS_CMD_CRC_ERR_CNT_8822C \ + (BIT_MASK_CMD_CRC_ERR_CNT_8822C << BIT_SHIFT_CMD_CRC_ERR_CNT_8822C) +#define BIT_CLEAR_CMD_CRC_ERR_CNT_8822C(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8822C)) +#define BIT_GET_CMD_CRC_ERR_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822C) & \ + BIT_MASK_CMD_CRC_ERR_CNT_8822C) +#define BIT_SET_CMD_CRC_ERR_CNT_8822C(x, v) \ + (BIT_CLEAR_CMD_CRC_ERR_CNT_8822C(x) | BIT_CMD_CRC_ERR_CNT_8822C(v)) + +/* 2 REG_SDIO_DATA_ERRCNT_8822C */ + +#define BIT_SHIFT_DATA_CRC_ERR_CNT_8822C 0 +#define BIT_MASK_DATA_CRC_ERR_CNT_8822C 0xff +#define BIT_DATA_CRC_ERR_CNT_8822C(x) \ + (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822C) \ + << BIT_SHIFT_DATA_CRC_ERR_CNT_8822C) +#define BITS_DATA_CRC_ERR_CNT_8822C \ + (BIT_MASK_DATA_CRC_ERR_CNT_8822C << BIT_SHIFT_DATA_CRC_ERR_CNT_8822C) +#define BIT_CLEAR_DATA_CRC_ERR_CNT_8822C(x) \ + ((x) & (~BITS_DATA_CRC_ERR_CNT_8822C)) +#define BIT_GET_DATA_CRC_ERR_CNT_8822C(x) \ + (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822C) & \ + BIT_MASK_DATA_CRC_ERR_CNT_8822C) +#define BIT_SET_DATA_CRC_ERR_CNT_8822C(x, v) \ + (BIT_CLEAR_DATA_CRC_ERR_CNT_8822C(x) | BIT_DATA_CRC_ERR_CNT_8822C(v)) + +/* 2 REG_SDIO_CMD_ERR_CONTENT_8822C */ + +#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C 0 +#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C 0xffffffffffL +#define BIT_SDIO_CMD_ERR_CONTENT_8822C(x) \ + (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C) \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C) +#define BITS_SDIO_CMD_ERR_CONTENT_8822C \ + (BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C \ + << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C) +#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822C(x) \ + ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8822C)) +#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C) & \ + BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C) +#define BIT_SET_SDIO_CMD_ERR_CONTENT_8822C(x, v) \ + (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822C(x) | \ + BIT_SDIO_CMD_ERR_CONTENT_8822C(v)) + +/* 2 REG_SDIO_CRC_ERR_IDX_8822C */ +#define BIT_D3_CRC_ERR_8822C BIT(4) +#define BIT_D2_CRC_ERR_8822C BIT(3) +#define BIT_D1_CRC_ERR_8822C BIT(2) +#define BIT_D0_CRC_ERR_8822C BIT(1) +#define BIT_CMD_CRC_ERR_8822C BIT(0) + +/* 2 REG_SDIO_DATA_CRC_8822C */ + +#define BIT_SHIFT_SDIO_DATA_CRC_8822C 0 +#define BIT_MASK_SDIO_DATA_CRC_8822C 0xffff +#define BIT_SDIO_DATA_CRC_8822C(x) \ + (((x) & BIT_MASK_SDIO_DATA_CRC_8822C) << BIT_SHIFT_SDIO_DATA_CRC_8822C) +#define BITS_SDIO_DATA_CRC_8822C \ + (BIT_MASK_SDIO_DATA_CRC_8822C << BIT_SHIFT_SDIO_DATA_CRC_8822C) +#define BIT_CLEAR_SDIO_DATA_CRC_8822C(x) ((x) & (~BITS_SDIO_DATA_CRC_8822C)) +#define BIT_GET_SDIO_DATA_CRC_8822C(x) \ + (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822C) & BIT_MASK_SDIO_DATA_CRC_8822C) +#define BIT_SET_SDIO_DATA_CRC_8822C(x, v) \ + (BIT_CLEAR_SDIO_DATA_CRC_8822C(x) | BIT_SDIO_DATA_CRC_8822C(v)) + +/* 2 REG_SDIO_TRANS_FIFO_STATUS_8822C */ +#define BIT_TRANS_FIFO_UNDERFLOW_8822C BIT(1) +#define BIT_TRANS_FIFO_OVERFLOW_8822C BIT(0) + +#endif diff --git a/hal/halmac/halmac_fw_info.h b/hal/halmac/halmac_fw_info.h index 0ad43ba..1da64fb 100644 --- a/hal/halmac/halmac_fw_info.h +++ b/hal/halmac/halmac_fw_info.h @@ -1,22 +1,56 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_FW_INFO_H_ #define _HALMAC_FW_INFO_H_ -#define H2C_FORMAT_VERSION 6 - -#define H2C_ACK_HDR_CONTENT_LENGTH 8 -#define CFG_PARAMETER_ACK_CONTENT_LENGTH 16 -#define SCAN_STATUS_RPT_CONTENT_LENGTH 4 -#define C2H_DBG_HEADER_LENGTH 4 -#define C2H_DBG_CONTENT_MAX_LENGTH 228 - -#define C2H_DBG_CONTENT_SEQ_OFFSET 1 +#define H2C_FORMAT_VERSION 11 + +/* FW bin information */ +#define WLAN_FW_HDR_SIZE 64 +#define WLAN_FW_HDR_CHKSUM_SIZE 8 + +#define WLAN_FW_HDR_VERSION 4 +#define WLAN_FW_HDR_SUBVERSION 6 +#define WLAN_FW_HDR_SUBINDEX 7 +#define WLAN_FW_HDR_MONTH 16 +#define WLAN_FW_HDR_DATE 17 +#define WLAN_FW_HDR_HOUR 18 +#define WLAN_FW_HDR_MIN 19 +#define WLAN_FW_HDR_YEAR 20 +#define WLAN_FW_HDR_MEM_USAGE 24 +#define WLAN_FW_HDR_H2C_FMT_VER 28 +#define WLAN_FW_HDR_DMEM_ADDR 32 +#define WLAN_FW_HDR_DMEM_SIZE 36 +#define WLAN_FW_HDR_IMEM_SIZE 48 +#define WLAN_FW_HDR_EMEM_SIZE 52 +#define WLAN_FW_HDR_EMEM_ADDR 56 +#define WLAN_FW_HDR_IMEM_ADDR 60 + +#define H2C_ACK_HDR_CONTENT_LENGTH 8 +#define CFG_PARAMETER_ACK_CONTENT_LENGTH 16 +#define SCAN_STATUS_RPT_CONTENT_LENGTH 4 +#define C2H_DBG_HDR_LEN 4 +#define C2H_DBG_CONTENT_MAX_LENGTH 228 +#define C2H_DBG_CONTENT_SEQ_OFFSET 1 /* Rename from FW SysHalCom_Debug_RAM.h */ -#define FW_REG_H2CPKT_DONE_SEQ 0x1C8 -#define FW_REG_WoW_REASON 0x1C7 +#define FW_REG_H2CPKT_DONE_SEQ 0x1C8 +#define FW_REG_WOW_REASON 0x1C7 - -typedef enum _HALMAC_DATA_TYPE { +enum halmac_data_type { HALMAC_DATA_TYPE_MAC_REG = 0x00, HALMAC_DATA_TYPE_BB_REG = 0x01, HALMAC_DATA_TYPE_RADIO_A = 0x02, @@ -29,73 +63,57 @@ typedef enum _HALMAC_DATA_TYPE { HALMAC_DATA_TYPE_DRV_DEFINE_2 = 0x82, HALMAC_DATA_TYPE_DRV_DEFINE_3 = 0x83, HALMAC_DATA_TYPE_UNDEFINE = 0x7FFFFFFF, -} HALMAC_DATA_TYPE; +}; -typedef enum _HALMAC_PACKET_ID { +enum halmac_packet_id { HALMAC_PACKET_PROBE_REQ = 0x00, HALMAC_PACKET_SYNC_BCN = 0x01, HALMAC_PACKET_DISCOVERY_BCN = 0x02, - HALMAC_PACKET_UNDEFINE = 0x7FFFFFFF, -} HALMAC_PACKET_ID; +}; -/* Channel Switch Action ID */ -typedef enum _HALMAC_CS_ACTION_ID { +enum halmac_cs_action_id { HALMAC_CS_ACTION_NONE = 0x00, HALMAC_CS_ACTIVE_SCAN = 0x01, HALMAC_CS_NAN_NONMASTER_DW = 0x02, HALMAC_CS_NAN_NONMASTER_NONDW = 0x03, HALMAC_CS_NAN_MASTER_NONDW = 0x04, HALMAC_CS_NAN_MASTER_DW = 0x05, - HALMAC_CS_ACTION_UNDEFINE = 0x7FFFFFFF, -} HALMAC_CS_ACTION_ID; +}; -/* Channel Switch Extra Action ID */ -typedef enum _HALMAC_CS_EXTRA_ACTION_ID { +enum halmac_cs_extra_action_id { HALMAC_CS_EXTRA_ACTION_NONE = 0x00, HALMAC_CS_EXTRA_UPDATE_PROBE = 0x01, HALMAC_CS_EXTRA_UPDATE_BEACON = 0x02, - - HALMAC_CS_EXTRA_ACTION_UNDEFINE = 0x7FFFFFFF, -} HALMAC_CS_EXTRA_ACTION_ID; +}; -typedef enum _HALMAC_H2C_RETURN_CODE { +enum halmac_h2c_return_code { HALMAC_H2C_RETURN_SUCCESS = 0x00, HALMAC_H2C_RETURN_CFG_ERR_LEN = 0x01, HALMAC_H2C_RETURN_CFG_ERR_CMD = 0x02, - HALMAC_H2C_RETURN_EFUSE_ERR_DUMP = 0x03, - - HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04, /* DMEM buffer full */ - HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05, /* Invalid pack id */ - - HALMAC_H2C_RETURN_RUN_ERR_EMPTY = 0x06, /* No data in dedicated buffer */ + HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04, + HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05, + HALMAC_H2C_RETURN_RUN_ERR_EMPTY = 0x06, HALMAC_H2C_RETURN_RUN_ERR_LEN = 0x07, HALMAC_H2C_RETURN_RUN_ERR_CMD = 0x08, - HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09, /* Invalid pack id */ - - HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A, /* DMEM buffer full */ - HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B, /* Invalid packet id */ - - HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C, /* DMEM buffer full */ - HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D, /* PHYDM API return fail */ - - HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E, /* Invalid original H2C cmd id */ - + HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09, + HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A, + HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B, + HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C, + HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D, + HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E, HALMAC_H2C_RETURN_UNDEFINE = 0x7FFFFFFF, -} HALMAC_H2C_RETURN_CODE; - -typedef enum _HALMAC_SCAN_REPORT_CODE { - HALMAC_SCAN_REPORT_DONE = 0x00, - HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01, /* PHYDM API return fail */ - HALMAC_SCAN_REPORT_ERR_ID = 0x02, /* Invalid ActionID */ - HALMAC_SCAN_REPORT_ERR_TX = 0x03, /* Tx RsvdPage fail */ +}; +enum halmac_scan_report_code { + HALMAC_SCAN_REPORT_DONE = 0x00, + HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01, + HALMAC_SCAN_REPORT_ERR_ID = 0x02, + HALMAC_SCAN_REPORT_ERR_TX = 0x03, HALMAC_SCAN_REPORT_UNDEFINE = 0x7FFFFFFF, -} HALMAC_SCAN_REPORT_CODE; - - +}; #endif diff --git a/hal/halmac/halmac_fw_offload_c2h_ap.h b/hal/halmac/halmac_fw_offload_c2h_ap.h index 77ebd60..ec6974b 100644 --- a/hal/halmac/halmac_fw_offload_c2h_ap.h +++ b/hal/halmac/halmac_fw_offload_c2h_ap.h @@ -1,157 +1,515 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_ #define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_ -#define C2H_SUB_CMD_ID_C2H_DBG 0X00 -#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02 -#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03 -#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01 -#define C2H_SUB_CMD_ID_CFG_PARAMETER_ACK 0X01 -#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01 -#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01 -#define C2H_SUB_CMD_ID_UPDATE_PACKET_ACK 0X01 -#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01 -#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01 -#define C2H_SUB_CMD_ID_CHANNEL_SWITCH_ACK 0X01 -#define C2H_SUB_CMD_ID_IQK_ACK 0X01 -#define C2H_SUB_CMD_ID_POWER_TRACKING_ACK 0X01 -#define C2H_SUB_CMD_ID_PSD_ACK 0X01 -#define C2H_SUB_CMD_ID_PSD_DATA 0X04 -#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 -#define C2H_SUB_CMD_ID_IQK_DATA 0X06 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A -#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B -#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C -#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E -#define C2H_SUB_CMD_ID_CCX_RPT 0X0F -#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 -#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 -#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C -#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D -#define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER +#define C2H_SUB_CMD_ID_C2H_DBG 0X00 +#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02 +#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03 +#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01 +#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01 +#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01 +#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01 +#define C2H_SUB_CMD_ID_IQK_ACK 0X01 +#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_ACK 0X01 +#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_DATA 0X04 +#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 +#define C2H_SUB_CMD_ID_IQK_DATA 0X06 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A +#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B +#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C +#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E +#define C2H_SUB_CMD_ID_CCX_RPT 0X0F +#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 +#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 +#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C +#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D +#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF +#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01 +#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F +#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20 +#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21 +#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23 +#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM #define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX #define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE -#define H2C_SUB_CMD_ID_UPDATE_PACKET_ACK SUB_CMD_ID_UPDATE_PACKET +#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT #define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK #define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK -#define H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK SUB_CMD_ID_CHANNEL_SWITCH +#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH #define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK -#define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING +#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK #define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD +#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP #define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT -#define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF -#define H2C_CMD_ID_BT_COEX_ACK 0XFF -#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF -#define H2C_CMD_ID_UPDATE_PACKET_ACK 0XFF -#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF -#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF -#define H2C_CMD_ID_CHANNEL_SWITCH_ACK 0XFF -#define H2C_CMD_ID_IQK_ACK 0XFF -#define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF -#define H2C_CMD_ID_PSD_ACK 0XFF -#define H2C_CMD_ID_CCX_RPT 0XFF -#define C2H_HDR_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_HDR_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_HDR_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_HDR_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_HDR_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_HDR_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_HDR_GET_C2H_SUB_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define C2H_HDR_SET_C2H_SUB_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_HDR_SET_C2H_SUB_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_HDR_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_HDR_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_HDR_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_DBG_GET_DBG_MSG(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define C2H_DBG_SET_DBG_MSG(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_DBG_SET_DBG_MSG_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define BT_COEX_INFO_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define BT_COEX_INFO_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define BT_COEX_INFO_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define SCAN_STATUS_RPT_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) -#define SCAN_STATUS_RPT_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) -#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) -#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define H2C_ACK_HDR_SET_H2C_RETURN_CODE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define H2C_ACK_HDR_GET_H2C_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define H2C_ACK_HDR_SET_H2C_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define H2C_ACK_HDR_SET_H2C_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) -#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) -#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) -#define H2C_ACK_HDR_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 16) -#define H2C_ACK_HDR_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 16, __Value) -#define H2C_ACK_HDR_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 16, __Value) -#define CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(__pC2H) GET_C2H_FIELD(__pC2H + 0XC, 0, 32) -#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0XC, 0, 32, __Value) -#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0XC, 0, 32, __Value) -#define CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(__pC2H) GET_C2H_FIELD(__pC2H + 0X10, 0, 32) -#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X10, 0, 32, __Value) -#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X10, 0, 32, __Value) -#define BT_COEX_ACK_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0XC, 0, 8) -#define BT_COEX_ACK_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0XC, 0, 8, __Value) -#define BT_COEX_ACK_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0XC, 0, 8, __Value) -#define PSD_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7) -#define PSD_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value) -#define PSD_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value) -#define PSD_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1) -#define PSD_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value) -#define PSD_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value) -#define PSD_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define PSD_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define PSD_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define PSD_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) -#define PSD_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) -#define PSD_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) -#define PSD_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16) -#define PSD_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value) -#define PSD_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value) -#define PSD_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8) -#define PSD_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value) -#define PSD_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value) -#define EFUSE_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7) -#define EFUSE_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value) -#define EFUSE_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value) -#define EFUSE_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1) -#define EFUSE_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value) -#define EFUSE_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value) -#define EFUSE_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define EFUSE_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define EFUSE_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define EFUSE_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) -#define EFUSE_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) -#define EFUSE_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) -#define EFUSE_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16) -#define EFUSE_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value) -#define EFUSE_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value) -#define EFUSE_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8) -#define EFUSE_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value) -#define EFUSE_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value) -#define IQK_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7) -#define IQK_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value) -#define IQK_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value) -#define IQK_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1) -#define IQK_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value) -#define IQK_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value) -#define IQK_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define IQK_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define IQK_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define IQK_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) -#define IQK_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) -#define IQK_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) -#define IQK_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16) -#define IQK_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value) -#define IQK_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value) -#define IQK_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8) -#define IQK_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value) -#define IQK_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value) -#define CCX_RPT_GET_CCX RPT(__pC2H) GET_C2H_FIELD(__pC2H + 0X4, 0, 129) -#define CCX_RPT_SET_CCX RPT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X4, 0, 129, __Value) -#define CCX_RPT_SET_CCX RPT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X4, 0, 129, __Value) +#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG +#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING +#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT +#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK +#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK +#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF +#define H2C_CMD_ID_BT_COEX_ACK 0XFF +#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF +#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF +#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF +#define H2C_CMD_ID_IQK_ACK 0XFF +#define H2C_CMD_ID_PWR_TRK_ACK 0XFF +#define H2C_CMD_ID_PSD_ACK 0XFF +#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF +#define H2C_CMD_ID_CCX_RPT 0XFF +#define H2C_CMD_ID_FW_DBG_MSG 0XFF +#define H2C_CMD_ID_FW_SNDING_ACK 0XFF +#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF +#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF +#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF +#define C2H_HDR_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_HDR_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_HDR_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_HDR_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_HDR_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_HDR_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_HDR_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_HDR_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_HDR_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_HDR_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_DBG_GET_DBG_MSG(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_DBG_SET_DBG_MSG_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define BT_COEX_INFO_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define BT_COEX_INFO_SET_DATA_START_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define H2C_ACK_HDR_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define H2C_ACK_HDR_SET_H2C_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 16) +#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 16, value) +#define H2C_ACK_HDR_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 16, value) +#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0XC, 0, 32) +#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 32, value) +#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 32, value) +#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X10, 0, 32) +#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 32, value) +#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 32, value) +#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 8) +#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 8, value) +#define BT_COEX_ACK_SET_DATA_START_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 8, value) +#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7) +#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value) +#define PSD_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value) +#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1) +#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value) +#define PSD_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value) +#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define PSD_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define PSD_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16) +#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value) +#define PSD_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value) +#define PSD_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define PSD_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define PSD_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7) +#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value) +#define EFUSE_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value) +#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1) +#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value) +#define EFUSE_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value) +#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define EFUSE_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define EFUSE_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16) +#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value) +#define EFUSE_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value) +#define EFUSE_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define EFUSE_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7) +#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value) +#define IQK_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value) +#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1) +#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value) +#define IQK_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value) +#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define IQK_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define IQK_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16) +#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value) +#define IQK_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value) +#define IQK_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define IQK_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define IQK_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define CCX_RPT_GET_POLLUTED(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 0, 1) +#define CCX_RPT_SET_POLLUTED(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 0, 1, value) +#define CCX_RPT_SET_POLLUTED_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 0, 1, value) +#define CCX_RPT_GET_RPT_SEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 5, 3) +#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 5, 3, value) +#define CCX_RPT_SET_RPT_SEL_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 5, 3, value) +#define CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 8, 5) +#define CCX_RPT_SET_QSEL(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 8, 5, value) +#define CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 8, 5, value) +#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 13, 3) +#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 13, 3, value) +#define CCX_RPT_SET_MISSED_RPT_NUM_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 13, 3, value) +#define CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 16, 7) +#define CCX_RPT_SET_MACID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 16, 7, value) +#define CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 16, 7, value) +#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X4, 24, 7) +#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 24, 7, value) +#define CCX_RPT_SET_INITIAL_DATA_RATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 24, 7, value) +#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 31, 1) +#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 31, 1, value) +#define CCX_RPT_SET_INITIAL_SGI_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 31, 1, value) +#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16) +#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value) +#define CCX_RPT_SET_QUEUE_TIME_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value) +#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define CCX_RPT_SET_SW_DEFINE_BYTE0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 24, 4) +#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 4, value) +#define CCX_RPT_SET_RTS_RETRY_COUNT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 4, value) +#define CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 29, 1) +#define CCX_RPT_SET_BMC(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 29, 1, value) +#define CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 29, 1, value) +#define CCX_RPT_GET_TX_STATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 30, 2) +#define CCX_RPT_SET_TX_STATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 30, 2, value) +#define CCX_RPT_SET_TX_STATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 30, 2, value) +#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 6) +#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 6, value) +#define CCX_RPT_SET_DATA_RETRY_COUNT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 6, value) +#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 8, 7) +#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 8, 7, value) +#define CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 8, 7, value) +#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 15, 1) +#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 15, 1, value) +#define CCX_RPT_SET_FINAL_SGI_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 15, 1, value) +#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 16, 10) +#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 16, 10, value) +#define CCX_RPT_SET_RF_CH_NUM_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 16, 10, value) +#define CCX_RPT_GET_SC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 26, 4) +#define CCX_RPT_SET_SC(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 26, 4, value) +#define CCX_RPT_SET_SC_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 26, 4, value) +#define CCX_RPT_GET_BW(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 30, 2) +#define CCX_RPT_SET_BW(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 30, 2, value) +#define CCX_RPT_SET_BW_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 30, 2, value) +#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define FW_DBG_MSG_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define FW_DBG_MSG_GET_FULL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1) +#define FW_DBG_MSG_SET_FULL(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value) +#define FW_DBG_MSG_SET_FULL_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value) +#define FW_DBG_MSG_GET_OWN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 31, 1) +#define FW_DBG_MSG_SET_OWN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 31, 1, value) +#define FW_DBG_MSG_SET_OWN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 31, 1, value) +#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define FW_FWCTRL_RPT_SET_EVT_TYPE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define FW_FWCTRL_RPT_SET_LENGTH_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define FW_FWCTRL_RPT_SET_SEQ_NUM_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1) +#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value) +#define FW_FWCTRL_RPT_SET_IS_ACK_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value) +#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 25, 1) +#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 25, 1, value) +#define FW_FWCTRL_RPT_SET_MORE_CONTENT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 25, 1, value) +#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 26, 6) +#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 26, 6, value) +#define FW_FWCTRL_RPT_SET_CONTENT_IDX_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 26, 6, value) +#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define FW_FWCTRL_RPT_SET_CLASS_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16) +#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value) +#define FW_FWCTRL_RPT_SET_CONTENT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 0, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 8, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 24, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 0, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 8, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X8, 24, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value) +#define FW_TBTT_RPT_GET_PORT_NUMBER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define FW_TBTT_RPT_SET_PORT_NUMBER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define FW_TBTT_RPT_SET_PORT_NUMBER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) #endif diff --git a/hal/halmac/halmac_fw_offload_c2h_nic.h b/hal/halmac/halmac_fw_offload_c2h_nic.h index d74f4dd..bf3483a 100644 --- a/hal/halmac/halmac_fw_offload_c2h_nic.h +++ b/hal/halmac/halmac_fw_offload_c2h_nic.h @@ -1,123 +1,379 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_ #define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_ -#define C2H_SUB_CMD_ID_C2H_DBG 0X00 -#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02 -#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03 -#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01 -#define C2H_SUB_CMD_ID_CFG_PARAMETER_ACK 0X01 -#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01 -#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01 -#define C2H_SUB_CMD_ID_UPDATE_PACKET_ACK 0X01 -#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01 -#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01 -#define C2H_SUB_CMD_ID_CHANNEL_SWITCH_ACK 0X01 -#define C2H_SUB_CMD_ID_IQK_ACK 0X01 -#define C2H_SUB_CMD_ID_POWER_TRACKING_ACK 0X01 -#define C2H_SUB_CMD_ID_PSD_ACK 0X01 -#define C2H_SUB_CMD_ID_PSD_DATA 0X04 -#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 -#define C2H_SUB_CMD_ID_IQK_DATA 0X06 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A -#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B -#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C -#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D -#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E -#define C2H_SUB_CMD_ID_CCX_RPT 0X0F -#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 -#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 -#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C -#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D -#define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER +#define C2H_SUB_CMD_ID_C2H_DBG 0X00 +#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02 +#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03 +#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01 +#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01 +#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01 +#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01 +#define C2H_SUB_CMD_ID_IQK_ACK 0X01 +#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_ACK 0X01 +#define C2H_SUB_CMD_ID_FW_MEM_DUMP_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_DATA 0X04 +#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 +#define C2H_SUB_CMD_ID_IQK_DATA 0X06 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A +#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B +#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C +#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E +#define C2H_SUB_CMD_ID_CCX_RPT 0X0F +#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 +#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 +#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C +#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D +#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF +#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01 +#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F +#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20 +#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21 +#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23 +#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM #define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX #define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE -#define H2C_SUB_CMD_ID_UPDATE_PACKET_ACK SUB_CMD_ID_UPDATE_PACKET +#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT #define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK #define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK -#define H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK SUB_CMD_ID_CHANNEL_SWITCH +#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH #define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK -#define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING +#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK #define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD +#define H2C_SUB_CMD_ID_FW_MEM_DUMP_ACK SUB_CMD_ID_FW_MEM_DUMP #define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT -#define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF -#define H2C_CMD_ID_BT_COEX_ACK 0XFF -#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF -#define H2C_CMD_ID_UPDATE_PACKET_ACK 0XFF -#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF -#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF -#define H2C_CMD_ID_CHANNEL_SWITCH_ACK 0XFF -#define H2C_CMD_ID_IQK_ACK 0XFF -#define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF -#define H2C_CMD_ID_PSD_ACK 0XFF -#define H2C_CMD_ID_CCX_RPT 0XFF -#define C2H_HDR_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_HDR_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_HDR_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_HDR_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_HDR_GET_C2H_SUB_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define C2H_HDR_SET_C2H_SUB_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define C2H_HDR_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_HDR_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_DBG_GET_DBG_MSG(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define C2H_DBG_SET_DBG_MSG(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define BT_COEX_INFO_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define BT_COEX_INFO_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define SCAN_STATUS_RPT_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) -#define SCAN_STATUS_RPT_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) -#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define H2C_ACK_HDR_GET_H2C_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define H2C_ACK_HDR_SET_H2C_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) -#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) -#define H2C_ACK_HDR_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 16) -#define H2C_ACK_HDR_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 16, __Value) -#define CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0XC, 0, 32) -#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0XC, 0, 32, __Value) -#define CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X10, 0, 32) -#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X10, 0, 32, __Value) -#define BT_COEX_ACK_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0XC, 0, 8) -#define BT_COEX_ACK_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0XC, 0, 8, __Value) -#define PSD_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7) -#define PSD_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value) -#define PSD_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1) -#define PSD_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value) -#define PSD_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define PSD_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define PSD_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) -#define PSD_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) -#define PSD_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16) -#define PSD_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value) -#define PSD_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8) -#define PSD_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value) -#define EFUSE_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7) -#define EFUSE_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value) -#define EFUSE_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1) -#define EFUSE_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value) -#define EFUSE_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define EFUSE_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define EFUSE_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) -#define EFUSE_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) -#define EFUSE_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16) -#define EFUSE_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value) -#define EFUSE_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8) -#define EFUSE_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value) -#define IQK_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7) -#define IQK_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value) -#define IQK_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1) -#define IQK_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value) -#define IQK_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define IQK_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define IQK_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) -#define IQK_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) -#define IQK_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16) -#define IQK_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value) -#define IQK_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8) -#define IQK_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value) -#define CCX_RPT_GET_CCX RPT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X4, 0, 129) -#define CCX_RPT_SET_CCX RPT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X4, 0, 129, __Value) +#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG +#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING +#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT +#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK +#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK +#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF +#define H2C_CMD_ID_BT_COEX_ACK 0XFF +#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF +#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF +#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF +#define H2C_CMD_ID_IQK_ACK 0XFF +#define H2C_CMD_ID_PWR_TRK_ACK 0XFF +#define H2C_CMD_ID_PSD_ACK 0XFF +#define H2C_CMD_ID_FW_MEM_DUMP_ACK 0XFF +#define H2C_CMD_ID_CCX_RPT 0XFF +#define H2C_CMD_ID_FW_DBG_MSG 0XFF +#define H2C_CMD_ID_FW_SNDING_ACK 0XFF +#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF +#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF +#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF +#define C2H_HDR_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_HDR_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_HDR_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_HDR_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define C2H_HDR_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_HDR_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_DBG_GET_DBG_MSG(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define BT_COEX_INFO_GET_DATA_START(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 16) +#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 16, value) +#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 32) +#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 32, value) +#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 32) +#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 32, value) +#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 8) +#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 8, value) +#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7) +#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value) +#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1) +#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value) +#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16) +#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value) +#define PSD_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define PSD_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7) +#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value) +#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1) +#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value) +#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16) +#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value) +#define EFUSE_DATA_GET_DATA_START(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7) +#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value) +#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1) +#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value) +#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16) +#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value) +#define IQK_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define IQK_DATA_SET_DATA_START(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define CCX_RPT_GET_POLLUTED(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 0, 1) +#define CCX_RPT_SET_POLLUTED(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 0, 1, value) +#define CCX_RPT_GET_RPT_SEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 5, 3) +#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 5, 3, value) +#define CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 8, 5) +#define CCX_RPT_SET_QSEL(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 8, 5, value) +#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 13, 3) +#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 13, 3, value) +#define CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 16, 7) +#define CCX_RPT_SET_MACID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 16, 7, value) +#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 24, 7) +#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 24, 7, value) +#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 31, 1) +#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 31, 1, value) +#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16) +#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value) +#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 4) +#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 4, value) +#define CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 29, 1) +#define CCX_RPT_SET_BMC(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 29, 1, value) +#define CCX_RPT_GET_TX_STATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 30, 2) +#define CCX_RPT_SET_TX_STATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 30, 2, value) +#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 6) +#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 6, value) +#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 8, 7) +#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 8, 7, value) +#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 15, 1) +#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 15, 1, value) +#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 16, 10) +#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 16, 10, value) +#define CCX_RPT_GET_SC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 26, 4) +#define CCX_RPT_SET_SC(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 26, 4, value) +#define CCX_RPT_GET_BW(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 30, 2) +#define CCX_RPT_SET_BW(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 30, 2, value) +#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define FW_DBG_MSG_GET_FULL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1) +#define FW_DBG_MSG_SET_FULL(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value) +#define FW_DBG_MSG_GET_OWN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 31, 1) +#define FW_DBG_MSG_SET_OWN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 31, 1, value) +#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1) +#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value) +#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 25, 1) +#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 25, 1, value) +#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 26, 6) +#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 26, 6, value) +#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16) +#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8) +#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value) +#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8) +#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value) +#define FW_TBTT_RPT_GET_PORT_NUMBER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define FW_TBTT_RPT_SET_PORT_NUMBER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) #endif diff --git a/hal/halmac/halmac_fw_offload_h2c_ap.h b/hal/halmac/halmac_fw_offload_h2c_ap.h index dec1d66..2546b23 100644 --- a/hal/halmac/halmac_fw_offload_h2c_ap.h +++ b/hal/halmac/halmac_fw_offload_h2c_ap.h @@ -1,420 +1,989 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_ #define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_ -#define CMD_ID_FW_OFFLOAD_H2C 0XFF -#define CMD_ID_CHANNEL_SWITCH 0XFF -#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF -#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF -#define CMD_ID_CFG_PARAMETER 0XFF -#define CMD_ID_UPDATE_DATAPACK 0XFF -#define CMD_ID_RUN_DATAPACK 0XFF -#define CMD_ID_DOWNLOAD_FLASH 0XFF -#define CMD_ID_UPDATE_PACKET 0XFF -#define CMD_ID_GENERAL_INFO 0XFF -#define CMD_ID_IQK 0XFF -#define CMD_ID_POWER_TRACKING 0XFF -#define CMD_ID_PSD 0XFF -#define CMD_ID_P2PPS 0XFF -#define CMD_ID_BT_COEX 0XFF -#define CMD_ID_NAN_CTRL 0XFF -#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF -#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF -#define CATEGORY_H2C_CMD_HEADER 0X00 -#define CATEGORY_FW_OFFLOAD_H2C 0X01 -#define CATEGORY_CHANNEL_SWITCH 0X01 -#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01 -#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01 -#define CATEGORY_CFG_PARAMETER 0X01 -#define CATEGORY_UPDATE_DATAPACK 0X01 -#define CATEGORY_RUN_DATAPACK 0X01 -#define CATEGORY_DOWNLOAD_FLASH 0X01 -#define CATEGORY_UPDATE_PACKET 0X01 -#define CATEGORY_GENERAL_INFO 0X01 -#define CATEGORY_IQK 0X01 -#define CATEGORY_POWER_TRACKING 0X01 -#define CATEGORY_PSD 0X01 -#define CATEGORY_P2PPS 0X01 -#define CATEGORY_BT_COEX 0X01 -#define CATEGORY_NAN_CTRL 0X01 -#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 -#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 -#define SUB_CMD_ID_CHANNEL_SWITCH 0X02 -#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 -#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 -#define SUB_CMD_ID_CFG_PARAMETER 0X08 -#define SUB_CMD_ID_UPDATE_DATAPACK 0X09 -#define SUB_CMD_ID_RUN_DATAPACK 0X0A -#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B -#define SUB_CMD_ID_UPDATE_PACKET 0X0C -#define SUB_CMD_ID_GENERAL_INFO 0X0D -#define SUB_CMD_ID_IQK 0X0E -#define SUB_CMD_ID_POWER_TRACKING 0X0F -#define SUB_CMD_ID_PSD 0X10 -#define SUB_CMD_ID_P2PPS 0X24 -#define SUB_CMD_ID_BT_COEX 0X60 -#define SUB_CMD_ID_NAN_CTRL 0XB2 -#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 -#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 -#define H2C_CMD_HEADER_GET_CATEGORY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 7) -#define H2C_CMD_HEADER_SET_CATEGORY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 7, __Value) -#define H2C_CMD_HEADER_SET_CATEGORY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 7, __Value) -#define H2C_CMD_HEADER_GET_ACK(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 7, 1) -#define H2C_CMD_HEADER_SET_ACK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 7, 1, __Value) -#define H2C_CMD_HEADER_SET_ACK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 7, 1, __Value) -#define H2C_CMD_HEADER_GET_TOTAL_LEN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 16) -#define H2C_CMD_HEADER_SET_TOTAL_LEN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 16, __Value) -#define H2C_CMD_HEADER_SET_TOTAL_LEN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 16, __Value) -#define H2C_CMD_HEADER_GET_SEQ_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 16) -#define H2C_CMD_HEADER_SET_SEQ_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 16, __Value) -#define H2C_CMD_HEADER_SET_SEQ_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 16, __Value) -#define FW_OFFLOAD_H2C_GET_CATEGORY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 7) -#define FW_OFFLOAD_H2C_SET_CATEGORY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 7, __Value) -#define FW_OFFLOAD_H2C_SET_CATEGORY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 7, __Value) -#define FW_OFFLOAD_H2C_GET_ACK(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 7, 1) -#define FW_OFFLOAD_H2C_SET_ACK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 7, 1, __Value) -#define FW_OFFLOAD_H2C_SET_ACK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 7, 1, __Value) -#define FW_OFFLOAD_H2C_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define FW_OFFLOAD_H2C_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define FW_OFFLOAD_H2C_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 16) -#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 16, __Value) -#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 16, __Value) -#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 16) -#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 16, __Value) -#define FW_OFFLOAD_H2C_SET_TOTAL_LEN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 16, __Value) -#define FW_OFFLOAD_H2C_GET_SEQ_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 16) -#define FW_OFFLOAD_H2C_SET_SEQ_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 16, __Value) -#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 16, __Value) -#define CHANNEL_SWITCH_GET_SWITCH_START(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) -#define CHANNEL_SWITCH_SET_SWITCH_START(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) -#define CHANNEL_SWITCH_SET_SWITCH_START_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) -#define CHANNEL_SWITCH_GET_DEST_CH_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) -#define CHANNEL_SWITCH_SET_DEST_CH_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) -#define CHANNEL_SWITCH_SET_DEST_CH_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) -#define CHANNEL_SWITCH_GET_ABSOLUTE_TIME(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1) -#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value) -#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value) -#define CHANNEL_SWITCH_GET_PERIODIC_OPTION(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 2) -#define CHANNEL_SWITCH_SET_PERIODIC_OPTION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 2, __Value) -#define CHANNEL_SWITCH_SET_PERIODIC_OPTION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 2, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_INFO_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define CHANNEL_SWITCH_SET_CHANNEL_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define CHANNEL_SWITCH_SET_CHANNEL_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define CHANNEL_SWITCH_GET_PRI_CH_IDX(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 4) -#define CHANNEL_SWITCH_SET_PRI_CH_IDX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 4, __Value) -#define CHANNEL_SWITCH_SET_PRI_CH_IDX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 4, __Value) -#define CHANNEL_SWITCH_GET_DEST_BW(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 28, 4) -#define CHANNEL_SWITCH_SET_DEST_BW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 28, 4, __Value) -#define CHANNEL_SWITCH_SET_DEST_BW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 28, 4, __Value) -#define CHANNEL_SWITCH_GET_DEST_CH(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) -#define CHANNEL_SWITCH_SET_DEST_CH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define CHANNEL_SWITCH_SET_DEST_CH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define CHANNEL_SWITCH_GET_NORMAL_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 8) -#define CHANNEL_SWITCH_SET_NORMAL_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 8, __Value) -#define CHANNEL_SWITCH_SET_NORMAL_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 8, __Value) -#define CHANNEL_SWITCH_GET_SLOW_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 8) -#define CHANNEL_SWITCH_SET_SLOW_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 8, __Value) -#define CHANNEL_SWITCH_SET_SLOW_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 8, __Value) -#define CHANNEL_SWITCH_GET_NORMAL_CYCLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 24, 8) -#define CHANNEL_SWITCH_SET_NORMAL_CYCLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 24, 8, __Value) -#define CHANNEL_SWITCH_SET_NORMAL_CYCLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 24, 8, __Value) -#define CHANNEL_SWITCH_GET_TSF_HIGH(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) -#define CHANNEL_SWITCH_SET_TSF_HIGH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) -#define CHANNEL_SWITCH_SET_TSF_HIGH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) -#define CHANNEL_SWITCH_GET_TSF_LOW(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32) -#define CHANNEL_SWITCH_SET_TSF_LOW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value) -#define CHANNEL_SWITCH_SET_TSF_LOW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_INFO_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 16) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 16, __Value) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 16, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) -#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 4) -#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 12, 4) -#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 12, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 12, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 32, __Value) -#define CFG_PARAMETER_GET_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) -#define CFG_PARAMETER_SET_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) -#define CFG_PARAMETER_SET_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) -#define CFG_PARAMETER_GET_INIT_CASE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 1) -#define CFG_PARAMETER_SET_INIT_CASE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 1, __Value) -#define CFG_PARAMETER_SET_INIT_CASE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 1, __Value) -#define CFG_PARAMETER_GET_PHY_PARAMETER_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) -#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) -#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_DATAPACK_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) -#define UPDATE_DATAPACK_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_DATAPACK_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_DATAPACK_SET_DATAPACK_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_DATAPACK_SET_DATAPACK_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define UPDATE_DATAPACK_GET_END_SEGMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 1) -#define UPDATE_DATAPACK_SET_END_SEGMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 1, __Value) -#define UPDATE_DATAPACK_SET_END_SEGMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 1, __Value) -#define RUN_DATAPACK_GET_DATAPACK_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define RUN_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define RUN_DATAPACK_SET_DATAPACK_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define DOWNLOAD_FLASH_GET_SPI_CMD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define DOWNLOAD_FLASH_SET_SPI_CMD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define DOWNLOAD_FLASH_SET_SPI_CMD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define DOWNLOAD_FLASH_GET_LOCATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 16) -#define DOWNLOAD_FLASH_SET_LOCATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 16, __Value) -#define DOWNLOAD_FLASH_SET_LOCATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 16, __Value) -#define DOWNLOAD_FLASH_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 32) -#define DOWNLOAD_FLASH_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 32, __Value) -#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 32, __Value) -#define DOWNLOAD_FLASH_GET_START_ADDR(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) -#define DOWNLOAD_FLASH_SET_START_ADDR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) -#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) -#define UPDATE_PACKET_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) -#define UPDATE_PACKET_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_PACKET_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_PACKET_GET_PACKET_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define UPDATE_PACKET_SET_PACKET_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_PACKET_SET_PACKET_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_PACKET_GET_PACKET_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) -#define UPDATE_PACKET_SET_PACKET_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_PACKET_SET_PACKET_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) -#define GENERAL_INFO_GET_REF_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define GENERAL_INFO_SET_REF_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define GENERAL_INFO_SET_REF_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define GENERAL_INFO_GET_RF_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 9) -#define GENERAL_INFO_SET_RF_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 9, __Value) -#define GENERAL_INFO_SET_RF_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 9, __Value) -#define GENERAL_INFO_GET_FW_TX_BOUNDARY(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define GENERAL_INFO_SET_FW_TX_BOUNDARY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define GENERAL_INFO_SET_FW_TX_BOUNDARY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define IQK_GET_CLEAR(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) -#define IQK_SET_CLEAR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) -#define IQK_SET_CLEAR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) -#define IQK_GET_SEGMENT_IQK(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) -#define IQK_SET_SEGMENT_IQK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) -#define IQK_SET_SEGMENT_IQK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) -#define POWER_TRACKING_SET_ENABLE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) -#define POWER_TRACKING_SET_ENABLE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) -#define POWER_TRACKING_SET_ENABLE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) -#define POWER_TRACKING_SET_ENABLE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1) -#define POWER_TRACKING_SET_ENABLE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value) -#define POWER_TRACKING_SET_ENABLE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 1) -#define POWER_TRACKING_SET_ENABLE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 1, __Value) -#define POWER_TRACKING_SET_ENABLE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 1, __Value) -#define POWER_TRACKING_GET_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 4, 3) -#define POWER_TRACKING_SET_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 4, 3, __Value) -#define POWER_TRACKING_SET_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 4, 3, __Value) -#define POWER_TRACKING_GET_BBSWING_INDEX(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) -#define POWER_TRACKING_SET_BBSWING_INDEX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) -#define POWER_TRACKING_SET_BBSWING_INDEX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define POWER_TRACKING_SET_TX_PWR_INDEX_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 8, __Value) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 8, __Value) -#define POWER_TRACKING_SET_TSSI_VALUE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value) -#define POWER_TRACKING_SET_TX_PWR_INDEX_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 16, 8, __Value) -#define POWER_TRACKING_SET_TSSI_VALUE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 8, __Value) -#define POWER_TRACKING_SET_TX_PWR_INDEX_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 8, 8, __Value) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 8, __Value) -#define POWER_TRACKING_SET_TSSI_VALUE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value) -#define POWER_TRACKING_SET_TX_PWR_INDEX_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 16, 8, __Value) -#define POWER_TRACKING_SET_TSSI_VALUE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 16, 8, __Value) -#define PSD_GET_START_PSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) -#define PSD_SET_START_PSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) -#define PSD_SET_START_PSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) -#define PSD_GET_END_PSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 16) -#define PSD_SET_END_PSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 16, __Value) -#define PSD_SET_END_PSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 16, __Value) -#define P2PPS_GET_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) -#define P2PPS_SET_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) -#define P2PPS_SET_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) -#define P2PPS_GET_ROLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) -#define P2PPS_SET_ROLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) -#define P2PPS_SET_ROLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) -#define P2PPS_GET_CTWINDOW_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1) -#define P2PPS_SET_CTWINDOW_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value) -#define P2PPS_SET_CTWINDOW_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value) -#define P2PPS_GET_NOA_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 1) -#define P2PPS_SET_NOA_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 1, __Value) -#define P2PPS_SET_NOA_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 1, __Value) -#define P2PPS_GET_NOA_SEL(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 4, 1) -#define P2PPS_SET_NOA_SEL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 4, 1, __Value) -#define P2PPS_SET_NOA_SEL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 4, 1, __Value) -#define P2PPS_GET_ALLSTASLEEP(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 5, 1) -#define P2PPS_SET_ALLSTASLEEP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 5, 1, __Value) -#define P2PPS_SET_ALLSTASLEEP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 5, 1, __Value) -#define P2PPS_GET_DISCOVERY(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 6, 1) -#define P2PPS_SET_DISCOVERY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 6, 1, __Value) -#define P2PPS_SET_DISCOVERY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 6, 1, __Value) -#define P2PPS_GET_P2P_PORT_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) -#define P2PPS_SET_P2P_PORT_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) -#define P2PPS_SET_P2P_PORT_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) -#define P2PPS_GET_P2P_GROUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define P2PPS_SET_P2P_GROUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define P2PPS_SET_P2P_GROUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define P2PPS_GET_P2P_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) -#define P2PPS_SET_P2P_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) -#define P2PPS_SET_P2P_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) -#define P2PPS_GET_CTWINDOW_LENGTH(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) -#define P2PPS_SET_CTWINDOW_LENGTH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define P2PPS_SET_CTWINDOW_LENGTH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define P2PPS_GET_NOA_DURATION_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) -#define P2PPS_SET_NOA_DURATION_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) -#define P2PPS_SET_NOA_DURATION_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) -#define P2PPS_GET_NOA_INTERVAL_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32) -#define P2PPS_SET_NOA_INTERVAL_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value) -#define P2PPS_SET_NOA_INTERVAL_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value) -#define P2PPS_GET_NOA_START_TIME_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 32) -#define P2PPS_SET_NOA_START_TIME_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 32, __Value) -#define P2PPS_SET_NOA_START_TIME_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 32, __Value) -#define P2PPS_GET_NOA_COUNT_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 32) -#define P2PPS_SET_NOA_COUNT_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 32, __Value) -#define P2PPS_SET_NOA_COUNT_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 32, __Value) -#define BT_COEX_GET_DATA_START(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define BT_COEX_SET_DATA_START(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define BT_COEX_SET_DATA_START_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CTRL_GET_NAN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 2) -#define NAN_CTRL_SET_NAN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 2, __Value) -#define NAN_CTRL_SET_NAN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 2, __Value) -#define NAN_CTRL_GET_SUPPORT_BAND (__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 2) -#define NAN_CTRL_SET_SUPPORT_BAND (__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 2, __Value) -#define NAN_CTRL_SET_SUPPORT_BAND _NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 2, __Value) -#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 10, 1) -#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 10, 1, __Value) -#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 10, 1, __Value) -#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 11, 1) -#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 11, 1, __Value) -#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 11, 1, __Value) -#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) -#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) -#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) -#define NAN_CTRL_GET_CHANNEL_2G(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) -#define NAN_CTRL_SET_CHANNEL_2G(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) -#define NAN_CTRL_SET_CHANNEL_2G_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) -#define NAN_CTRL_GET_CHANNEL_5G(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) -#define NAN_CTRL_SET_CHANNEL_5G(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define NAN_CTRL_SET_CHANNEL_5G_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 16, 16, __Value) +#define CMD_ID_FW_OFFLOAD_H2C 0XFF +#define CMD_ID_FW_ACCESS_TEST 0XFF +#define CMD_ID_CH_SWITCH 0XFF +#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF +#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF +#define CMD_ID_CFG_PARAM 0XFF +#define CMD_ID_UPDATE_DATAPACK 0XFF +#define CMD_ID_RUN_DATAPACK 0XFF +#define CMD_ID_DOWNLOAD_FLASH 0XFF +#define CMD_ID_UPDATE_PKT 0XFF +#define CMD_ID_GENERAL_INFO 0XFF +#define CMD_ID_IQK 0XFF +#define CMD_ID_PWR_TRK 0XFF +#define CMD_ID_PSD 0XFF +#define CMD_ID_PHYDM_INFO 0XFF +#define CMD_ID_FW_SNDING 0XFF +#define CMD_ID_FW_FWCTRL 0XFF +#define CMD_ID_H2C_LOOPBACK 0XFF +#define CMD_ID_FWCMD_LOOPBACK 0XFF +#define CMD_ID_P2PPS 0XFF +#define CMD_ID_BT_COEX 0XFF +#define CMD_ID_NAN_CTRL 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF +#define CATEGORY_H2C_CMD_HEADER 0X00 +#define CATEGORY_FW_OFFLOAD_H2C 0X01 +#define CATEGORY_FW_ACCESS_TEST 0X01 +#define CATEGORY_CH_SWITCH 0X01 +#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01 +#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01 +#define CATEGORY_CFG_PARAM 0X01 +#define CATEGORY_UPDATE_DATAPACK 0X01 +#define CATEGORY_RUN_DATAPACK 0X01 +#define CATEGORY_DOWNLOAD_FLASH 0X01 +#define CATEGORY_UPDATE_PKT 0X01 +#define CATEGORY_GENERAL_INFO 0X01 +#define CATEGORY_IQK 0X01 +#define CATEGORY_PWR_TRK 0X01 +#define CATEGORY_PSD 0X01 +#define CATEGORY_PHYDM_INFO 0X01 +#define CATEGORY_FW_SNDING 0X01 +#define CATEGORY_FW_FWCTRL 0X01 +#define CATEGORY_H2C_LOOPBACK 0X01 +#define CATEGORY_FWCMD_LOOPBACK 0X01 +#define CATEGORY_P2PPS 0X01 +#define CATEGORY_BT_COEX 0X01 +#define CATEGORY_NAN_CTRL 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 +#define SUB_CMD_ID_FW_ACCESS_TEST 0X00 +#define SUB_CMD_ID_CH_SWITCH 0X02 +#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 +#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 +#define SUB_CMD_ID_CFG_PARAM 0X08 +#define SUB_CMD_ID_UPDATE_DATAPACK 0X09 +#define SUB_CMD_ID_RUN_DATAPACK 0X0A +#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B +#define SUB_CMD_ID_UPDATE_PKT 0X0C +#define SUB_CMD_ID_GENERAL_INFO 0X0D +#define SUB_CMD_ID_IQK 0X0E +#define SUB_CMD_ID_PWR_TRK 0X0F +#define SUB_CMD_ID_PSD 0X10 +#define SUB_CMD_ID_PHYDM_INFO 0X11 +#define SUB_CMD_ID_FW_SNDING 0X12 +#define SUB_CMD_ID_FW_FWCTRL 0X13 +#define SUB_CMD_ID_H2C_LOOPBACK 0X14 +#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15 +#define SUB_CMD_ID_P2PPS 0X24 +#define SUB_CMD_ID_BT_COEX 0X60 +#define SUB_CMD_ID_NAN_CTRL 0XB2 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 +#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7) +#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value) +#define H2C_CMD_HEADER_SET_CATEGORY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value) +#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1) +#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value) +#define H2C_CMD_HEADER_SET_ACK_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value) +#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 16) +#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value) +#define H2C_CMD_HEADER_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value) +#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 16) +#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value) +#define H2C_CMD_HEADER_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value) +#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7) +#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value) +#define FW_OFFLOAD_H2C_SET_CATEGORY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value) +#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1) +#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value) +#define FW_OFFLOAD_H2C_SET_ACK_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value) +#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define FW_OFFLOAD_H2C_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 16) +#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 16, value) +#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 16, value) +#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 16) +#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value) +#define FW_OFFLOAD_H2C_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value) +#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 16) +#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value) +#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value) +#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_TXFF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_RXFF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_FWFF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PHYFF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1) +#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_CAM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1) +#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1) +#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 9, 1) +#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 17, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 17, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 17, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 18, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 18, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 18, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 19, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 19, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 19, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 20, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 20, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 20, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 21, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 21, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE5_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 21, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 22, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 22, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE6_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 22, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 23, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 23, 1, value) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE7_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 23, 1, value) +#define CH_SWITCH_GET_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define CH_SWITCH_SET_START(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define CH_SWITCH_SET_START_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define CH_SWITCH_SET_DEST_CH_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define CH_SWITCH_SET_ABSOLUTE_TIME_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 2) +#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 2, value) +#define CH_SWITCH_SET_PERIODIC_OPT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 2, value) +#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define CH_SWITCH_SET_INFO_LOC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define CH_SWITCH_GET_CH_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define CH_SWITCH_SET_CH_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4) +#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value) +#define CH_SWITCH_SET_PRI_CH_IDX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value) +#define CH_SWITCH_GET_DEST_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4) +#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value) +#define CH_SWITCH_SET_DEST_BW_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value) +#define CH_SWITCH_GET_DEST_CH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8) +#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define CH_SWITCH_SET_DEST_CH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 6) +#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 6, value) +#define CH_SWITCH_SET_NORMAL_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 6, value) +#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 14, 2) +#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 14, 2, value) +#define CH_SWITCH_SET_NORMAL_PERIOD_SEL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 14, 2, value) +#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 6) +#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 6, value) +#define CH_SWITCH_SET_SLOW_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 6, value) +#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 22, 2) +#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 22, 2, value) +#define CH_SWITCH_SET_SLOW_PERIOD_SEL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 22, 2, value) +#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 24, 8) +#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 24, 8, value) +#define CH_SWITCH_SET_NORMAL_CYCLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 24, 8, value) +#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32) +#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value) +#define CH_SWITCH_SET_TSF_HIGH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value) +#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32) +#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value) +#define CH_SWITCH_SET_TSF_LOW_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value) +#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 16) +#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 16, value) +#define CH_SWITCH_SET_INFO_SIZE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 16, value) +#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 8, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 4, value) +#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 4, value) +#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 12, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 12, 4, value) +#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 12, 4, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value) +#define CFG_PARAM_GET_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16) +#define CFG_PARAM_SET_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value) +#define CFG_PARAM_SET_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value) +#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1) +#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value) +#define CFG_PARAM_SET_INIT_CASE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value) +#define CFG_PARAM_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define CFG_PARAM_SET_LOC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define CFG_PARAM_SET_LOC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16) +#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_DATAPACK_SET_SIZE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_DATAPACK_SET_DATAPACK_LOC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 1) +#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 1, value) +#define UPDATE_DATAPACK_SET_END_SEGMENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 1, value) +#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define RUN_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define DOWNLOAD_FLASH_SET_SPI_CMD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 8, 16) +#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 16, value) +#define DOWNLOAD_FLASH_SET_LOCATION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 16, value) +#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32) +#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value) +#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value) +#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32) +#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value) +#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value) +#define UPDATE_PKT_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16) +#define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_PKT_SET_SIZE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_PKT_GET_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define UPDATE_PKT_SET_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_PKT_SET_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_PKT_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define UPDATE_PKT_SET_LOC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_PKT_SET_LOC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define GENERAL_INFO_SET_FW_TX_BOUNDARY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define IQK_GET_CLEAR(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define IQK_SET_CLEAR(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define IQK_SET_CLEAR_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define IQK_GET_SEGMENT_IQK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define IQK_SET_SEGMENT_IQK_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define PWR_TRK_GET_ENABLE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define PWR_TRK_SET_ENABLE_A_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define PWR_TRK_GET_ENABLE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define PWR_TRK_SET_ENABLE_B_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define PWR_TRK_GET_ENABLE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define PWR_TRK_SET_ENABLE_C_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define PWR_TRK_GET_ENABLE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1) +#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value) +#define PWR_TRK_SET_ENABLE_D_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value) +#define PWR_TRK_GET_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 3) +#define PWR_TRK_SET_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 3, value) +#define PWR_TRK_SET_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 3, value) +#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define PWR_TRK_SET_BBSWING_INDEX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define PWR_TRK_SET_TX_PWR_INDEX_A_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value) +#define PWR_TRK_SET_OFFSET_VALUE_A_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value) +#define PWR_TRK_SET_TSSI_VALUE_A_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value) +#define PWR_TRK_SET_TX_PWR_INDEX_B_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value) +#define PWR_TRK_SET_OFFSET_VALUE_B_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 16, 8, value) +#define PWR_TRK_SET_TSSI_VALUE_B_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 8, value) +#define PWR_TRK_SET_TX_PWR_INDEX_C_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 8, 8, value) +#define PWR_TRK_SET_OFFSET_VALUE_C_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 8, value) +#define PWR_TRK_SET_TSSI_VALUE_C_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value) +#define PWR_TRK_SET_TX_PWR_INDEX_D_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value) +#define PWR_TRK_SET_OFFSET_VALUE_D_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 16, 8, value) +#define PWR_TRK_SET_TSSI_VALUE_D_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 16, 8, value) +#define PSD_GET_START_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16) +#define PSD_SET_START_PSD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value) +#define PSD_SET_START_PSD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value) +#define PSD_GET_END_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 16) +#define PSD_SET_END_PSD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 16, value) +#define PSD_SET_END_PSD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 16, value) +#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define PHYDM_INFO_SET_REF_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define PHYDM_INFO_SET_RF_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define PHYDM_INFO_SET_CUT_VER_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4) +#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value) +#define PHYDM_INFO_SET_RX_ANT_STATUS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value) +#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4) +#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value) +#define PHYDM_INFO_SET_TX_ANT_STATUS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value) +#define FW_SNDING_GET_SU0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define FW_SNDING_SET_SU0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define FW_SNDING_SET_SU0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define FW_SNDING_GET_SU1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define FW_SNDING_SET_SU1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define FW_SNDING_SET_SU1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define FW_SNDING_GET_MU(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define FW_SNDING_SET_MU(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define FW_SNDING_SET_MU_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define FW_SNDING_GET_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define FW_SNDING_SET_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define FW_SNDING_SET_NDPA0_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define FW_SNDING_SET_NDPA1_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0XC, 0, 8) +#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 8, value) +#define FW_SNDING_SET_MU_NDPA_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 8, value) +#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 8, 8) +#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 8, 8, value) +#define FW_SNDING_SET_RPT0_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 8, 8, value) +#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 16, 8) +#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 16, 8, value) +#define FW_SNDING_SET_RPT1_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 16, 8, value) +#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 24, 8) +#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 24, 8, value) +#define FW_SNDING_SET_RPT2_HEAD_PG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 24, 8, value) +#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define FW_FWCTRL_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1) +#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value) +#define FW_FWCTRL_SET_MORE_CONTENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value) +#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 9, 7) +#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 7, value) +#define FW_FWCTRL_SET_CONTENT_IDX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 7, value) +#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define FW_FWCTRL_SET_CLASS_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define FW_FWCTRL_GET_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define FW_FWCTRL_SET_LENGTH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define FW_FWCTRL_GET_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32) +#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value) +#define FW_FWCTRL_SET_CONTENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value) +#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1) +#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value) +#define P2PPS_SET_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value) +#define P2PPS_GET_ROLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1) +#define P2PPS_SET_ROLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value) +#define P2PPS_SET_ROLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value) +#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define P2PPS_SET_CTWINDOW_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define P2PPS_GET_NOA_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1) +#define P2PPS_SET_NOA_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value) +#define P2PPS_SET_NOA_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value) +#define P2PPS_GET_NOA_SEL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1) +#define P2PPS_SET_NOA_SEL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value) +#define P2PPS_SET_NOA_SEL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value) +#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1) +#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value) +#define P2PPS_SET_ALLSTASLEEP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value) +#define P2PPS_GET_DISCOVERY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1) +#define P2PPS_SET_DISCOVERY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value) +#define P2PPS_SET_DISCOVERY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value) +#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1) +#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value) +#define P2PPS_SET_DISABLE_CLOSERF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value) +#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define P2PPS_SET_P2P_PORT_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define P2PPS_GET_P2P_GROUP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define P2PPS_SET_P2P_GROUP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define P2PPS_SET_P2P_GROUP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define P2PPS_GET_P2P_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define P2PPS_SET_P2P_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define P2PPS_SET_P2P_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8) +#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define P2PPS_SET_CTWINDOW_LENGTH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32) +#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value) +#define P2PPS_SET_NOA_DURATION_PARA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value) +#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32) +#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value) +#define P2PPS_SET_NOA_INTERVAL_PARA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value) +#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 0, 32) +#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value) +#define P2PPS_SET_NOA_START_TIME_PARA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value) +#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32) +#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value) +#define P2PPS_SET_NOA_COUNT_PARA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value) +#define BT_COEX_GET_DATA_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define BT_COEX_SET_DATA_START(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define BT_COEX_SET_DATA_START_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CTRL_GET_NAN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 2) +#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 2, value) +#define NAN_CTRL_SET_NAN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 2, value) +#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1) +#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value) +#define NAN_CTRL_SET_WARMUP_TIMER_FLAG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value) +#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 2) +#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 2, value) +#define NAN_CTRL_SET_SUPPORT_BAND_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 2, value) +#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 10, 1) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 10, 1, value) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 10, 1, value) +#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 11, 1) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 11, 1, value) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 11, 1, value) +#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value) +#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8) +#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value) +#define NAN_CTRL_SET_CHANNEL_2G_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value) +#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8) +#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define NAN_CTRL_SET_CHANNEL_5G_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value) +#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8) +#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value) +#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value) +#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8) +#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value) +#define NAN_CTRL_SET_RANDOMFACTOR_VALUE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value) #endif diff --git a/hal/halmac/halmac_fw_offload_h2c_nic.h b/hal/halmac/halmac_fw_offload_h2c_nic.h index 0b00b4f..6703f67 100644 --- a/hal/halmac/halmac_fw_offload_h2c_nic.h +++ b/hal/halmac/halmac_fw_offload_h2c_nic.h @@ -1,299 +1,694 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_ #define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_ -#define CMD_ID_FW_OFFLOAD_H2C 0XFF -#define CMD_ID_CHANNEL_SWITCH 0XFF -#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF -#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF -#define CMD_ID_CFG_PARAMETER 0XFF -#define CMD_ID_UPDATE_DATAPACK 0XFF -#define CMD_ID_RUN_DATAPACK 0XFF -#define CMD_ID_DOWNLOAD_FLASH 0XFF -#define CMD_ID_UPDATE_PACKET 0XFF -#define CMD_ID_GENERAL_INFO 0XFF -#define CMD_ID_IQK 0XFF -#define CMD_ID_POWER_TRACKING 0XFF -#define CMD_ID_PSD 0XFF -#define CMD_ID_P2PPS 0XFF -#define CMD_ID_BT_COEX 0XFF -#define CMD_ID_NAN_CTRL 0XFF -#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF -#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF -#define CATEGORY_H2C_CMD_HEADER 0X00 -#define CATEGORY_FW_OFFLOAD_H2C 0X01 -#define CATEGORY_CHANNEL_SWITCH 0X01 -#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01 -#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01 -#define CATEGORY_CFG_PARAMETER 0X01 -#define CATEGORY_UPDATE_DATAPACK 0X01 -#define CATEGORY_RUN_DATAPACK 0X01 -#define CATEGORY_DOWNLOAD_FLASH 0X01 -#define CATEGORY_UPDATE_PACKET 0X01 -#define CATEGORY_GENERAL_INFO 0X01 -#define CATEGORY_IQK 0X01 -#define CATEGORY_POWER_TRACKING 0X01 -#define CATEGORY_PSD 0X01 -#define CATEGORY_P2PPS 0X01 -#define CATEGORY_BT_COEX 0X01 -#define CATEGORY_NAN_CTRL 0X01 -#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 -#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 -#define SUB_CMD_ID_CHANNEL_SWITCH 0X02 -#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 -#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 -#define SUB_CMD_ID_CFG_PARAMETER 0X08 -#define SUB_CMD_ID_UPDATE_DATAPACK 0X09 -#define SUB_CMD_ID_RUN_DATAPACK 0X0A -#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B -#define SUB_CMD_ID_UPDATE_PACKET 0X0C -#define SUB_CMD_ID_GENERAL_INFO 0X0D -#define SUB_CMD_ID_IQK 0X0E -#define SUB_CMD_ID_POWER_TRACKING 0X0F -#define SUB_CMD_ID_PSD 0X10 -#define SUB_CMD_ID_P2PPS 0X24 -#define SUB_CMD_ID_BT_COEX 0X60 -#define SUB_CMD_ID_NAN_CTRL 0XB2 -#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 -#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 -#define H2C_CMD_HEADER_GET_CATEGORY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 7) -#define H2C_CMD_HEADER_SET_CATEGORY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 7, __Value) -#define H2C_CMD_HEADER_GET_ACK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 7, 1) -#define H2C_CMD_HEADER_SET_ACK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 7, 1, __Value) -#define H2C_CMD_HEADER_GET_TOTAL_LEN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 16) -#define H2C_CMD_HEADER_SET_TOTAL_LEN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 16, __Value) -#define H2C_CMD_HEADER_GET_SEQ_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 16) -#define H2C_CMD_HEADER_SET_SEQ_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 16, __Value) -#define FW_OFFLOAD_H2C_GET_CATEGORY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 7) -#define FW_OFFLOAD_H2C_SET_CATEGORY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 7, __Value) -#define FW_OFFLOAD_H2C_GET_ACK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 7, 1) -#define FW_OFFLOAD_H2C_SET_ACK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 7, 1, __Value) -#define FW_OFFLOAD_H2C_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define FW_OFFLOAD_H2C_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 16) -#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 16, __Value) -#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 16) -#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 16, __Value) -#define FW_OFFLOAD_H2C_GET_SEQ_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 16) -#define FW_OFFLOAD_H2C_SET_SEQ_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 16, __Value) -#define CHANNEL_SWITCH_GET_SWITCH_START(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) -#define CHANNEL_SWITCH_SET_SWITCH_START(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) -#define CHANNEL_SWITCH_GET_DEST_CH_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) -#define CHANNEL_SWITCH_SET_DEST_CH_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) -#define CHANNEL_SWITCH_GET_ABSOLUTE_TIME(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1) -#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value) -#define CHANNEL_SWITCH_GET_PERIODIC_OPTION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 2) -#define CHANNEL_SWITCH_SET_PERIODIC_OPTION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 2, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_INFO_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define CHANNEL_SWITCH_SET_CHANNEL_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define CHANNEL_SWITCH_GET_PRI_CH_IDX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 4) -#define CHANNEL_SWITCH_SET_PRI_CH_IDX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 4, __Value) -#define CHANNEL_SWITCH_GET_DEST_BW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 28, 4) -#define CHANNEL_SWITCH_SET_DEST_BW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 28, 4, __Value) -#define CHANNEL_SWITCH_GET_DEST_CH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) -#define CHANNEL_SWITCH_SET_DEST_CH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) -#define CHANNEL_SWITCH_GET_NORMAL_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 8) -#define CHANNEL_SWITCH_SET_NORMAL_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 8, __Value) -#define CHANNEL_SWITCH_GET_SLOW_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 8) -#define CHANNEL_SWITCH_SET_SLOW_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 8, __Value) -#define CHANNEL_SWITCH_GET_NORMAL_CYCLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 24, 8) -#define CHANNEL_SWITCH_SET_NORMAL_CYCLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 24, 8, __Value) -#define CHANNEL_SWITCH_GET_TSF_HIGH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) -#define CHANNEL_SWITCH_SET_TSF_HIGH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) -#define CHANNEL_SWITCH_GET_TSF_LOW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32) -#define CHANNEL_SWITCH_SET_TSF_LOW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value) -#define CHANNEL_SWITCH_GET_CHANNEL_INFO_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 16) -#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 16, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) -#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 4) -#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 12, 4) -#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 12, 4, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 32, __Value) -#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 32) -#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 32, __Value) -#define CFG_PARAMETER_GET_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) -#define CFG_PARAMETER_SET_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) -#define CFG_PARAMETER_GET_INIT_CASE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 1) -#define CFG_PARAMETER_SET_INIT_CASE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 1, __Value) -#define CFG_PARAMETER_GET_PHY_PARAMETER_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) -#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_DATAPACK_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) -#define UPDATE_DATAPACK_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) -#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) -#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) -#define UPDATE_DATAPACK_GET_END_SEGMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 1) -#define UPDATE_DATAPACK_SET_END_SEGMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 1, __Value) -#define RUN_DATAPACK_GET_DATAPACK_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define RUN_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define DOWNLOAD_FLASH_GET_SPI_CMD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define DOWNLOAD_FLASH_SET_SPI_CMD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define DOWNLOAD_FLASH_GET_LOCATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 16) -#define DOWNLOAD_FLASH_SET_LOCATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 16, __Value) -#define DOWNLOAD_FLASH_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 32) -#define DOWNLOAD_FLASH_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 32, __Value) -#define DOWNLOAD_FLASH_GET_START_ADDR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) -#define DOWNLOAD_FLASH_SET_START_ADDR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) -#define UPDATE_PACKET_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) -#define UPDATE_PACKET_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) -#define UPDATE_PACKET_GET_PACKET_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define UPDATE_PACKET_SET_PACKET_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define UPDATE_PACKET_GET_PACKET_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) -#define UPDATE_PACKET_SET_PACKET_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) -#define GENERAL_INFO_GET_REF_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define GENERAL_INFO_SET_REF_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define GENERAL_INFO_GET_RF_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 9) -#define GENERAL_INFO_SET_RF_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 9, __Value) -#define GENERAL_INFO_GET_FW_TX_BOUNDARY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define GENERAL_INFO_SET_FW_TX_BOUNDARY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define IQK_GET_CLEAR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) -#define IQK_SET_CLEAR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) -#define IQK_GET_SEGMENT_IQK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) -#define IQK_SET_SEGMENT_IQK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) -#define POWER_TRACKING_SET_ENABLE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) -#define POWER_TRACKING_SET_ENABLE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1) -#define POWER_TRACKING_SET_ENABLE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value) -#define POWER_TRACKING_GET_ENABLE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 1) -#define POWER_TRACKING_SET_ENABLE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 1, __Value) -#define POWER_TRACKING_GET_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 4, 3) -#define POWER_TRACKING_SET_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 4, 3, __Value) -#define POWER_TRACKING_GET_BBSWING_INDEX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) -#define POWER_TRACKING_SET_BBSWING_INDEX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 8, __Value) -#define POWER_TRACKING_GET_TX_PWR_INDEX_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8) -#define POWER_TRACKING_SET_TX_PWR_INDEX_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value) -#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8) -#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value) -#define POWER_TRACKING_GET_TSSI_VALUE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 16, 8) -#define POWER_TRACKING_SET_TSSI_VALUE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 16, 8, __Value) -#define PSD_GET_START_PSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) -#define PSD_SET_START_PSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) -#define PSD_GET_END_PSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 16) -#define PSD_SET_END_PSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 16, __Value) -#define P2PPS_GET_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) -#define P2PPS_SET_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) -#define P2PPS_GET_ROLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) -#define P2PPS_SET_ROLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) -#define P2PPS_GET_CTWINDOW_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1) -#define P2PPS_SET_CTWINDOW_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value) -#define P2PPS_GET_NOA_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 1) -#define P2PPS_SET_NOA_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 1, __Value) -#define P2PPS_GET_NOA_SEL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 4, 1) -#define P2PPS_SET_NOA_SEL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 4, 1, __Value) -#define P2PPS_GET_ALLSTASLEEP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 5, 1) -#define P2PPS_SET_ALLSTASLEEP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 5, 1, __Value) -#define P2PPS_GET_DISCOVERY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 6, 1) -#define P2PPS_SET_DISCOVERY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 6, 1, __Value) -#define P2PPS_GET_P2P_PORT_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) -#define P2PPS_SET_P2P_PORT_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) -#define P2PPS_GET_P2P_GROUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define P2PPS_SET_P2P_GROUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define P2PPS_GET_P2P_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) -#define P2PPS_SET_P2P_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) -#define P2PPS_GET_CTWINDOW_LENGTH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) -#define P2PPS_SET_CTWINDOW_LENGTH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) -#define P2PPS_GET_NOA_DURATION_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) -#define P2PPS_SET_NOA_DURATION_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) -#define P2PPS_GET_NOA_INTERVAL_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32) -#define P2PPS_SET_NOA_INTERVAL_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value) -#define P2PPS_GET_NOA_START_TIME_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 32) -#define P2PPS_SET_NOA_START_TIME_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 32, __Value) -#define P2PPS_GET_NOA_COUNT_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 32) -#define P2PPS_SET_NOA_COUNT_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 32, __Value) -#define BT_COEX_GET_DATA_START(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define BT_COEX_SET_DATA_START(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CTRL_GET_NAN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 2) -#define NAN_CTRL_SET_NAN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 2, __Value) -#define NAN_CTRL_GET_SUPPORT_BAND (__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 2) -#define NAN_CTRL_SET_SUPPORT_BAND (__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 2, __Value) -#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 10, 1) -#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 10, 1, __Value) -#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 11, 1) -#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 11, 1, __Value) -#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) -#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) -#define NAN_CTRL_GET_CHANNEL_2G(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) -#define NAN_CTRL_SET_CHANNEL_2G(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) -#define NAN_CTRL_GET_CHANNEL_5G(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) -#define NAN_CTRL_SET_CHANNEL_5G(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8) -#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8) -#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 16) -#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 16, 16) -#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8) -#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8) -#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value) -#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 16) -#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 16, __Value) -#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 16, 16) -#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 16, 16, __Value) +#define CMD_ID_FW_OFFLOAD_H2C 0XFF +#define CMD_ID_FW_ACCESS_TEST 0XFF +#define CMD_ID_CH_SWITCH 0XFF +#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF +#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF +#define CMD_ID_CFG_PARAM 0XFF +#define CMD_ID_UPDATE_DATAPACK 0XFF +#define CMD_ID_RUN_DATAPACK 0XFF +#define CMD_ID_DOWNLOAD_FLASH 0XFF +#define CMD_ID_UPDATE_PKT 0XFF +#define CMD_ID_GENERAL_INFO 0XFF +#define CMD_ID_IQK 0XFF +#define CMD_ID_PWR_TRK 0XFF +#define CMD_ID_PSD 0XFF +#define CMD_ID_PHYDM_INFO 0XFF +#define CMD_ID_FW_SNDING 0XFF +#define CMD_ID_FW_FWCTRL 0XFF +#define CMD_ID_H2C_LOOPBACK 0XFF +#define CMD_ID_FWCMD_LOOPBACK 0XFF +#define CMD_ID_P2PPS 0XFF +#define CMD_ID_BT_COEX 0XFF +#define CMD_ID_NAN_CTRL 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF +#define CATEGORY_H2C_CMD_HEADER 0X00 +#define CATEGORY_FW_OFFLOAD_H2C 0X01 +#define CATEGORY_FW_ACCESS_TEST 0X01 +#define CATEGORY_CH_SWITCH 0X01 +#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01 +#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01 +#define CATEGORY_CFG_PARAM 0X01 +#define CATEGORY_UPDATE_DATAPACK 0X01 +#define CATEGORY_RUN_DATAPACK 0X01 +#define CATEGORY_DOWNLOAD_FLASH 0X01 +#define CATEGORY_UPDATE_PKT 0X01 +#define CATEGORY_GENERAL_INFO 0X01 +#define CATEGORY_IQK 0X01 +#define CATEGORY_PWR_TRK 0X01 +#define CATEGORY_PSD 0X01 +#define CATEGORY_PHYDM_INFO 0X01 +#define CATEGORY_FW_SNDING 0X01 +#define CATEGORY_FW_FWCTRL 0X01 +#define CATEGORY_H2C_LOOPBACK 0X01 +#define CATEGORY_FWCMD_LOOPBACK 0X01 +#define CATEGORY_P2PPS 0X01 +#define CATEGORY_BT_COEX 0X01 +#define CATEGORY_NAN_CTRL 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 +#define SUB_CMD_ID_FW_ACCESS_TEST 0X00 +#define SUB_CMD_ID_CH_SWITCH 0X02 +#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 +#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 +#define SUB_CMD_ID_CFG_PARAM 0X08 +#define SUB_CMD_ID_UPDATE_DATAPACK 0X09 +#define SUB_CMD_ID_RUN_DATAPACK 0X0A +#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B +#define SUB_CMD_ID_UPDATE_PKT 0X0C +#define SUB_CMD_ID_GENERAL_INFO 0X0D +#define SUB_CMD_ID_IQK 0X0E +#define SUB_CMD_ID_PWR_TRK 0X0F +#define SUB_CMD_ID_PSD 0X10 +#define SUB_CMD_ID_PHYDM_INFO 0X11 +#define SUB_CMD_ID_FW_SNDING 0X12 +#define SUB_CMD_ID_FW_FWCTRL 0X13 +#define SUB_CMD_ID_H2C_LOOPBACK 0X14 +#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15 +#define SUB_CMD_ID_P2PPS 0X24 +#define SUB_CMD_ID_BT_COEX 0X60 +#define SUB_CMD_ID_NAN_CTRL 0XB2 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 +#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7) +#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value) +#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1) +#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value) +#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16) +#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value) +#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16) +#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value) +#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7) +#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value) +#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1) +#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value) +#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 16) +#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 16, value) +#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16) +#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value) +#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16) +#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value) +#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1) +#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1) +#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1) +#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1) +#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 1) +#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 17, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 17, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 18, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 18, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 19, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 19, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 20, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 20, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 21, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 21, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 22, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 22, 1, value) +#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 23, 1) +#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 23, 1, value) +#define CH_SWITCH_GET_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define CH_SWITCH_SET_START(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 2) +#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 2, value) +#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define CH_SWITCH_GET_CH_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4) +#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value) +#define CH_SWITCH_GET_DEST_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4) +#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value) +#define CH_SWITCH_GET_DEST_CH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8) +#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value) +#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 6) +#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 6, value) +#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 14, 2) +#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 14, 2, value) +#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 6) +#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 6, value) +#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 22, 2) +#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 22, 2, value) +#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 24, 8) +#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 24, 8, value) +#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32) +#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value) +#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32) +#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value) +#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 16) +#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 16, value) +#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 4, value) +#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 12, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 12, 4, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value) +#define CFG_PARAM_GET_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16) +#define CFG_PARAM_SET_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value) +#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1) +#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value) +#define CFG_PARAM_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define CFG_PARAM_SET_LOC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16) +#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value) +#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 1) +#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 1, value) +#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 16) +#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 16, value) +#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32) +#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value) +#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32) +#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value) +#define UPDATE_PKT_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16) +#define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value) +#define UPDATE_PKT_GET_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define UPDATE_PKT_SET_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define UPDATE_PKT_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define UPDATE_PKT_SET_LOC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define IQK_GET_CLEAR(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define IQK_SET_CLEAR(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define IQK_GET_SEGMENT_IQK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define PWR_TRK_GET_ENABLE_A(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define PWR_TRK_GET_ENABLE_B(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define PWR_TRK_GET_ENABLE_C(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define PWR_TRK_GET_ENABLE_D(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1) +#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value) +#define PWR_TRK_GET_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 3) +#define PWR_TRK_SET_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 3, value) +#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 8, value) +#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8) +#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value) +#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8) +#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value) +#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 16, 8) +#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 16, 8, value) +#define PSD_GET_START_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16) +#define PSD_SET_START_PSD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value) +#define PSD_GET_END_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 16) +#define PSD_SET_END_PSD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 16, value) +#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4) +#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value) +#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4) +#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value) +#define FW_SNDING_GET_SU0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define FW_SNDING_SET_SU0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define FW_SNDING_GET_SU1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define FW_SNDING_SET_SU1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define FW_SNDING_GET_MU(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define FW_SNDING_SET_MU(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define FW_SNDING_GET_PERIOD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 8) +#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 8, value) +#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 8, 8) +#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 8, 8, value) +#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 16, 8) +#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 16, 8, value) +#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 24, 8) +#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 24, 8, value) +#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1) +#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value) +#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 7) +#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 7, value) +#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define FW_FWCTRL_GET_LENGTH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define FW_FWCTRL_GET_CONTENT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32) +#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value) +#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1) +#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value) +#define P2PPS_GET_ROLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1) +#define P2PPS_SET_ROLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value) +#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define P2PPS_GET_NOA_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1) +#define P2PPS_SET_NOA_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value) +#define P2PPS_GET_NOA_SEL(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1) +#define P2PPS_SET_NOA_SEL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value) +#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1) +#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value) +#define P2PPS_GET_DISCOVERY(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1) +#define P2PPS_SET_DISCOVERY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value) +#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1) +#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value) +#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define P2PPS_GET_P2P_GROUP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define P2PPS_SET_P2P_GROUP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define P2PPS_GET_P2P_MACID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define P2PPS_SET_P2P_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8) +#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value) +#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32) +#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value) +#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32) +#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value) +#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32) +#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value) +#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32) +#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value) +#define BT_COEX_GET_DATA_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define BT_COEX_SET_DATA_START(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CTRL_GET_NAN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 2) +#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 2, value) +#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1) +#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value) +#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 2) +#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 2, value) +#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 10, 1) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 10, 1, value) +#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 11, 1) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 11, 1, value) +#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value) +#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8) +#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value) +#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8) +#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value) +#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8) +#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value) +#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8) +#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value) #endif diff --git a/hal/halmac/halmac_gpio_cmd.h b/hal/halmac/halmac_gpio_cmd.h new file mode 100644 index 0000000..818f413 --- /dev/null +++ b/hal/halmac/halmac_gpio_cmd.h @@ -0,0 +1,101 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef HALMAC_GPIO_CMD +#define HALMAC_GPIO_CMD + +#include "halmac_2_platform.h" + +/* GPIO ID */ +#define HALMAC_GPIO0 0 +#define HALMAC_GPIO1 1 +#define HALMAC_GPIO2 2 +#define HALMAC_GPIO3 3 +#define HALMAC_GPIO4 4 +#define HALMAC_GPIO5 5 +#define HALMAC_GPIO6 6 +#define HALMAC_GPIO7 7 +#define HALMAC_GPIO8 8 +#define HALMAC_GPIO9 9 +#define HALMAC_GPIO10 10 +#define HALMAC_GPIO11 11 +#define HALMAC_GPIO12 12 +#define HALMAC_GPIO13 13 +#define HALMAC_GPIO14 14 +#define HALMAC_GPIO15 15 +#define HALMAC_GPIO_NUM 16 + +/* GPIO type */ +#define HALMAC_GPIO_IN 0 +#define HALMAC_GPIO_OUT 1 +#define HALMAC_GPIO_IN_OUT 2 + +/* Function name */ +#define HALMAC_WL_HWPDN 0 +#define HALMAC_BT_HWPDN 1 +#define HALMAC_BT_GPIO 2 +#define HALMAC_WL_HW_EXTWOL 3 +#define HALMAC_BT_HW_EXTWOL 4 +#define HALMAC_BT_SFLASH 5 +#define HALMAC_WL_SFLASH 6 +#define HALMAC_WL_LED 7 +#define HALMAC_SDIO_INT 8 +#define HALMAC_UART0 9 +#define HALMAC_EEPROM 10 +#define HALMAC_JTAG 11 +#define HALMAC_LTE_COEX_UART 12 +#define HALMAC_3W_LTE_WL_GPIO 13 +#define HALMAC_GPIO2_3_WL_CTRL_EN 14 +#define HALMAC_GPIO13_14_WL_CTRL_EN 15 +#define HALMAC_DBG_GNT_WL_BT 16 +#define HALMAC_BT_3DDLS_A 17 +#define HALMAC_BT_3DDLS_B 18 +#define HALMAC_BT_PTA 19 +#define HALMAC_WL_PTA 20 +#define HALMAC_WL_UART 21 +#define HALMAC_WLMAC_DBG 22 +#define HALMAC_WLPHY_DBG 23 +#define HALMAC_BT_DBG 24 +#define HALMAC_WLPHY_RFE_CTRL2GPIO 25 +#define HALMAC_EXT_XTAL 26 +#define HALMAC_SW_IO 27 +#define HALMAC_BT_SDIO_INT 28 +#define HALMAC_BT_JTAG 29 +#define HALMAC_WL_JTAG 30 +#define HALMAC_BT_RF 31 +#define HALMAC_WLPHY_RFE_CTRL2GPIO_2 32 +#define HALMAC_MAILBOX_3W 33 +#define HALMAC_MAILBOX_1W 34 +#define HALMAC_SW_DPDT_SEL 35 +#define HALMAC_BT_DPDT_SEL 36 +#define HALMAC_WL_DPDT_SEL 37 +#define HALMAC_BT_PAPE_SEL 38 +#define HALMAC_SW_PAPE_SEL 39 +#define HALMAC_WLBT_PAPE_SEL 40 +#define HALMAC_SW_LNAON_SET 41 +#define HALMAC_BT_LNAON_SEL 42 +#define HALMAC_WLBT_LNAON_SEL 43 +#define HALMAC_SWR_CTRL_EN 44 + +struct halmac_gpio_pimux_list { + u16 func; + u8 id; + u8 type; + u16 offset; + u8 msk; + u8 value; +}; + +#endif diff --git a/hal/halmac/halmac_h2c_extra_info_ap.h b/hal/halmac/halmac_h2c_extra_info_ap.h index f19324a..8362987 100644 --- a/hal/halmac/halmac_h2c_extra_info_ap.h +++ b/hal/halmac/halmac_h2c_extra_info_ap.h @@ -1,69 +1,220 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_ #define _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_ -#define PHY_PARAMETER_INFO_GET_LENGTH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 8) -#define PHY_PARAMETER_INFO_SET_LENGTH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 8, __Value) -#define PHY_PARAMETER_INFO_SET_LENGTH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 8, __Value) -#define PHY_PARAMETER_INFO_GET_IO_CMD(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 7) -#define PHY_PARAMETER_INFO_SET_IO_CMD(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 7, __Value) -#define PHY_PARAMETER_INFO_SET_IO_CMD_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 7, __Value) -#define PHY_PARAMETER_INFO_GET_MSK_EN(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 15, 1) -#define PHY_PARAMETER_INFO_SET_MSK_EN(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 15, 1, __Value) -#define PHY_PARAMETER_INFO_SET_MSK_EN_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 15, 1, __Value) -#define PHY_PARAMETER_INFO_GET_LLT_PG_BNDY(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_EFUSE_RSVDPAGE_LOC(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_EFUSE_PATCH_EN(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_RF_ADDR(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_RF_ADDR(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_SET_RF_ADDR_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_IO_ADDR(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 16) -#define PHY_PARAMETER_INFO_SET_IO_ADDR(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_SET_IO_ADDR_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_GET_DELAY_VALUE(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 16) -#define PHY_PARAMETER_INFO_SET_DELAY_VALUE(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_SET_DELAY_VALUE_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_GET_RF_PATH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 24, 8) -#define PHY_PARAMETER_INFO_SET_RF_PATH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 24, 8, __Value) -#define PHY_PARAMETER_INFO_SET_RF_PATH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 24, 8, __Value) -#define PHY_PARAMETER_INFO_GET_DATA(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X04, 0, 32) -#define PHY_PARAMETER_INFO_SET_DATA(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X04, 0, 32, __Value) -#define PHY_PARAMETER_INFO_SET_DATA_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X04, 0, 32, __Value) -#define PHY_PARAMETER_INFO_GET_MASK(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X08, 0, 32) -#define PHY_PARAMETER_INFO_SET_MASK(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X08, 0, 32, __Value) -#define PHY_PARAMETER_INFO_SET_MASK_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X08, 0, 32, __Value) -#define CHANNEL_INFO_GET_CHANNEL(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 8) -#define CHANNEL_INFO_SET_CHANNEL(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 8, __Value) -#define CHANNEL_INFO_SET_CHANNEL_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 8, __Value) -#define CHANNEL_INFO_GET_PRI_CH_IDX(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 4) -#define CHANNEL_INFO_SET_PRI_CH_IDX(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 4, __Value) -#define CHANNEL_INFO_SET_PRI_CH_IDX_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 4, __Value) -#define CHANNEL_INFO_GET_BANDWIDTH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 12, 4) -#define CHANNEL_INFO_SET_BANDWIDTH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 12, 4, __Value) -#define CHANNEL_INFO_SET_BANDWIDTH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 12, 4, __Value) -#define CHANNEL_INFO_GET_TIMEOUT(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) -#define CHANNEL_INFO_SET_TIMEOUT(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define CHANNEL_INFO_SET_TIMEOUT_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) -#define CHANNEL_INFO_GET_ACTION_ID(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 24, 7) -#define CHANNEL_INFO_SET_ACTION_ID(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 24, 7, __Value) -#define CHANNEL_INFO_SET_ACTION_ID_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 24, 7, __Value) -#define CHANNEL_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 31, 1) -#define CHANNEL_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 31, 1, __Value) -#define CHANNEL_INFO_SET_CH_EXTRA_INFO_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 31, 1, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_ID(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 7) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 7, __Value) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 7, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 7, 1) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 7, 1, __Value) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 7, 1, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_SIZE(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 8) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 8, __Value) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 8, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_DATA(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 1) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 1, __Value) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 1, __Value) +#define PARAM_INFO_GET_LEN(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8) +#define PARAM_INFO_SET_LEN(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value) +#define PARAM_INFO_SET_LEN_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value) +#define PARAM_INFO_GET_IO_CMD(extra_info) GET_C2H_FIELD(extra_info + 0X00, 8, 7) +#define PARAM_INFO_SET_IO_CMD(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 7, value) +#define PARAM_INFO_SET_IO_CMD_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 7, value) +#define PARAM_INFO_GET_MSK_EN(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 15, 1) +#define PARAM_INFO_SET_MSK_EN(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 15, 1, value) +#define PARAM_INFO_SET_MSK_EN_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 15, 1, value) +#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_SET_LLT_PG_BNDY_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_SET_EFUSE_PATCH_EN_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_RF_ADDR(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_RF_ADDR(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_SET_RF_ADDR_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_IO_ADDR(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 16) +#define PARAM_INFO_SET_IO_ADDR(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_SET_IO_ADDR_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_GET_DELAY_VAL(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 16) +#define PARAM_INFO_SET_DELAY_VAL(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_SET_DELAY_VAL_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_GET_RF_PATH(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 24, 8) +#define PARAM_INFO_SET_RF_PATH(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 24, 8, value) +#define PARAM_INFO_SET_RF_PATH_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 8, value) +#define PARAM_INFO_GET_DATA(extra_info) GET_C2H_FIELD(extra_info + 0X04, 0, 32) +#define PARAM_INFO_SET_DATA(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 32, value) +#define PARAM_INFO_SET_DATA_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 32, value) +#define PARAM_INFO_GET_MASK(extra_info) GET_C2H_FIELD(extra_info + 0X08, 0, 32) +#define PARAM_INFO_SET_MASK(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X08, 0, 32, value) +#define PARAM_INFO_SET_MASK_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X08, 0, 32, value) +#define CH_INFO_GET_CH(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8) +#define CH_INFO_SET_CH(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value) +#define CH_INFO_SET_CH_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value) +#define CH_INFO_GET_PRI_CH_IDX(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 8, 4) +#define CH_INFO_SET_PRI_CH_IDX(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 4, value) +#define CH_INFO_SET_PRI_CH_IDX_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 4, value) +#define CH_INFO_GET_BW(extra_info) GET_C2H_FIELD(extra_info + 0X00, 12, 4) +#define CH_INFO_SET_BW(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 12, 4, value) +#define CH_INFO_SET_BW_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 12, 4, value) +#define CH_INFO_GET_TIMEOUT(extra_info) GET_C2H_FIELD(extra_info + 0X00, 16, 8) +#define CH_INFO_SET_TIMEOUT(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value) +#define CH_INFO_SET_TIMEOUT_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value) +#define CH_INFO_GET_ACTION_ID(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 24, 7) +#define CH_INFO_SET_ACTION_ID(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 24, 7, value) +#define CH_INFO_SET_ACTION_ID_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 7, value) +#define CH_INFO_GET_EXTRA_INFO(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 31, 1) +#define CH_INFO_SET_EXTRA_INFO(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 31, 1, value) +#define CH_INFO_SET_EXTRA_INFO_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 31, 1, value) +#define CH_EXTRA_INFO_GET_ID(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 7) +#define CH_EXTRA_INFO_SET_ID(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 7, value) +#define CH_EXTRA_INFO_SET_ID_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 7, value) +#define CH_EXTRA_INFO_GET_INFO(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 7, 1) +#define CH_EXTRA_INFO_SET_INFO(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 7, 1, value) +#define CH_EXTRA_INFO_SET_INFO_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 7, 1, value) +#define CH_EXTRA_INFO_GET_SIZE(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 8, 8) +#define CH_EXTRA_INFO_SET_SIZE(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 8, value) +#define CH_EXTRA_INFO_SET_SIZE_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 8, value) +#define CH_EXTRA_INFO_GET_DATA(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 1) +#define CH_EXTRA_INFO_SET_DATA(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 1, value) +#define CH_EXTRA_INFO_SET_DATA_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 0, 16) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 0, 16) +#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_SET_BITDATA_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 16) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info) \ + GET_C2H_FIELD(extra_info + 0X00, 16, 16) +#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_SET_BITMASK_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 0, 22) +#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 0, 22) +#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 22, 1) +#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 22, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 22, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 23, 1) +#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 23, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 23, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 24, 4) +#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 24, 4, value) +#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 24, 4, value) +#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 28, 1) +#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 28, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_RD_EN_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 28, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 29, 1) +#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 29, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_WR_EN_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 29, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 30, 1) +#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 30, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_RAW_R_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 30, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info) \ + GET_C2H_FIELD(extra_info + 0X04, 31, 1) +#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value) \ + SET_C2H_FIELD_CLR(extra_info + 0X04, 31, 1, value) +#define HIOE_INSTRUCTION_INFO_SET_RAW_NO_CLR(extra_info, value) \ + SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 31, 1, value) #endif diff --git a/hal/halmac/halmac_h2c_extra_info_nic.h b/hal/halmac/halmac_h2c_extra_info_nic.h index 20bfb5a..d48a683 100644 --- a/hal/halmac/halmac_h2c_extra_info_nic.h +++ b/hal/halmac/halmac_h2c_extra_info_nic.h @@ -1,47 +1,171 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_ #define _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_ -#define PHY_PARAMETER_INFO_GET_LENGTH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 8) -#define PHY_PARAMETER_INFO_SET_LENGTH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 8, __Value) -#define PHY_PARAMETER_INFO_GET_IO_CMD(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 7) -#define PHY_PARAMETER_INFO_SET_IO_CMD(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 7, __Value) -#define PHY_PARAMETER_INFO_GET_MSK_EN(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 15, 1) -#define PHY_PARAMETER_INFO_SET_MSK_EN(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 15, 1, __Value) -#define PHY_PARAMETER_INFO_GET_LLT_PG_BNDY(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_EFUSE_RSVDPAGE_LOC(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_EFUSE_PATCH_EN(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_RF_ADDR(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) -#define PHY_PARAMETER_INFO_SET_RF_ADDR(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) -#define PHY_PARAMETER_INFO_GET_IO_ADDR(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 16) -#define PHY_PARAMETER_INFO_SET_IO_ADDR(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_GET_DELAY_VALUE(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 16) -#define PHY_PARAMETER_INFO_SET_DELAY_VALUE(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 16, __Value) -#define PHY_PARAMETER_INFO_GET_RF_PATH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 24, 8) -#define PHY_PARAMETER_INFO_SET_RF_PATH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 24, 8, __Value) -#define PHY_PARAMETER_INFO_GET_DATA(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X04, 0, 32) -#define PHY_PARAMETER_INFO_SET_DATA(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X04, 0, 32, __Value) -#define PHY_PARAMETER_INFO_GET_MASK(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X08, 0, 32) -#define PHY_PARAMETER_INFO_SET_MASK(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X08, 0, 32, __Value) -#define CHANNEL_INFO_GET_CHANNEL(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 8) -#define CHANNEL_INFO_SET_CHANNEL(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 8, __Value) -#define CHANNEL_INFO_GET_PRI_CH_IDX(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 4) -#define CHANNEL_INFO_SET_PRI_CH_IDX(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 4, __Value) -#define CHANNEL_INFO_GET_BANDWIDTH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 12, 4) -#define CHANNEL_INFO_SET_BANDWIDTH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 12, 4, __Value) -#define CHANNEL_INFO_GET_TIMEOUT(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) -#define CHANNEL_INFO_SET_TIMEOUT(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) -#define CHANNEL_INFO_GET_ACTION_ID(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 24, 7) -#define CHANNEL_INFO_SET_ACTION_ID(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 24, 7, __Value) -#define CHANNEL_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 31, 1) -#define CHANNEL_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 31, 1, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_ID(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 7) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 7, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 7, 1) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 7, 1, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_SIZE(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 8) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 8, __Value) -#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_DATA(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 1) -#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 1, __Value) + +/* H2C extra info (rsvd page) usage, unit : page (128byte)*/ +/* dlfw : not include txdesc size*/ +/* update pkt : not include txdesc size*/ +/* cfg param : not include txdesc size*/ +/* scan info : not include txdesc size*/ +/* dl flash : not include txdesc size*/ +#define DLFW_RSVDPG_SIZE 2048 +#define UPDATE_PKT_RSVDPG_SIZE 2048 +#define CFG_PARAM_RSVDPG_SIZE 2048 +#define SCAN_INFO_RSVDPG_SIZE 256 +#define DL_FLASH_RSVDPG_SIZE 2048 +/* su0 snding pkt : include txdesc size */ +#define SU0_SNDING_PKT_OFFSET 0 +#define SU0_SNDING_PKT_RSVDPG_SIZE 128 + +#define PARAM_INFO_GET_LEN(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8) +#define PARAM_INFO_SET_LEN(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value) +#define PARAM_INFO_GET_IO_CMD(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 7) +#define PARAM_INFO_SET_IO_CMD(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 7, value) +#define PARAM_INFO_GET_MSK_EN(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 15, 1) +#define PARAM_INFO_SET_MSK_EN(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 15, 1, value) +#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_RF_ADDR(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8) +#define PARAM_INFO_SET_RF_ADDR(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value) +#define PARAM_INFO_GET_IO_ADDR(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16) +#define PARAM_INFO_SET_IO_ADDR(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_GET_DELAY_VAL(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16) +#define PARAM_INFO_SET_DELAY_VAL(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value) +#define PARAM_INFO_GET_RF_PATH(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 24, 8) +#define PARAM_INFO_SET_RF_PATH(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 8, value) +#define PARAM_INFO_GET_DATA(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 32) +#define PARAM_INFO_SET_DATA(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 32, value) +#define PARAM_INFO_GET_MASK(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X08, 0, 32) +#define PARAM_INFO_SET_MASK(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X08, 0, 32, value) +#define CH_INFO_GET_CH(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8) +#define CH_INFO_SET_CH(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value) +#define CH_INFO_GET_PRI_CH_IDX(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 4) +#define CH_INFO_SET_PRI_CH_IDX(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 4, value) +#define CH_INFO_GET_BW(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 12, 4) +#define CH_INFO_SET_BW(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 12, 4, value) +#define CH_INFO_GET_TIMEOUT(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8) +#define CH_INFO_SET_TIMEOUT(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value) +#define CH_INFO_GET_ACTION_ID(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 24, 7) +#define CH_INFO_SET_ACTION_ID(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 7, value) +#define CH_INFO_GET_EXTRA_INFO(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 31, 1) +#define CH_INFO_SET_EXTRA_INFO(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 31, 1, value) +#define CH_EXTRA_INFO_GET_ID(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 7) +#define CH_EXTRA_INFO_SET_ID(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 7, value) +#define CH_EXTRA_INFO_GET_INFO(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 7, 1) +#define CH_EXTRA_INFO_SET_INFO(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 7, 1, value) +#define CH_EXTRA_INFO_GET_SIZE(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 8) +#define CH_EXTRA_INFO_SET_SIZE(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 8, value) +#define CH_EXTRA_INFO_GET_DATA(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 1) +#define CH_EXTRA_INFO_SET_DATA(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16) +#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16) +#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16) +#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value) +#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22) +#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22) +#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value) +#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 22, 1) +#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 22, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 23, 1) +#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 23, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 24, 4) +#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 24, 4, value) +#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 28, 1) +#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 28, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 29, 1) +#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 29, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 30, 1) +#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 30, 1, value) +#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info) \ + LE_BITS_TO_4BYTE(extra_info + 0X04, 31, 1) +#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value) \ + SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 31, 1, value) #endif diff --git a/hal/halmac/halmac_hw_cfg.h b/hal/halmac/halmac_hw_cfg.h index abde040..560f0f2 100644 --- a/hal/halmac/halmac_hw_cfg.h +++ b/hal/halmac/halmac_hw_cfg.h @@ -1,11 +1,22 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __HALMAC__HW_CFG_H__ #define __HALMAC__HW_CFG_H__ -#include /* CONFIG_[IC] */ - -#ifndef BIT - #define BIT(x) (1 << (x)) -#endif +#include /* CONFIG_[IC], CONFIG_[INTF]_HCI */ #ifdef CONFIG_RTL8723A #define HALMAC_8723A_SUPPORT 1 @@ -61,12 +72,6 @@ #define HALMAC_8814A_SUPPORT 0 #endif -#ifdef CONFIG_RTL8814B -#define HALMAC_8814B_SUPPORT 1 -#else -#define HALMAC_8814B_SUPPORT 0 -#endif - #ifdef CONFIG_RTL8881A #define HALMAC_8881A_SUPPORT 1 #else @@ -109,6 +114,12 @@ #define HALMAC_8195A_SUPPORT 0 #endif +#ifdef CONFIG_RTL8821B +#define HALMAC_8821B_SUPPORT 1 +#else +#define HALMAC_8821B_SUPPORT 0 +#endif + #ifdef CONFIG_RTL8196F #define HALMAC_8196F_SUPPORT 1 #else @@ -121,6 +132,33 @@ #define HALMAC_8197F_SUPPORT 0 #endif +#ifdef CONFIG_RTL8198F +#define HALMAC_8198F_SUPPORT 1 +#else +#define HALMAC_8198F_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8192F +#define HALMAC_8192F_SUPPORT 1 +#else +#define HALMAC_8192F_SUPPORT 0 +#endif + +#ifdef CONFIG_RTL8812F +#define HALMAC_8812F_SUPPORT 1 +#else +#define HALMAC_8812F_SUPPORT 0 +#endif + + +/* Halmac support IC version */ + +#ifdef CONFIG_RTL8814B +#define HALMAC_8814B_SUPPORT 1 +#else +#define HALMAC_8814B_SUPPORT 0 +#endif + #ifdef CONFIG_RTL8821C #define HALMAC_8821C_SUPPORT 1 #else @@ -133,6 +171,30 @@ #define HALMAC_8822B_SUPPORT 0 #endif +#ifdef CONFIG_RTL8822C +#define HALMAC_8822C_SUPPORT 1 +#else +#define HALMAC_8822C_SUPPORT 0 +#endif + + +/* Interface support */ +#ifdef CONFIG_SDIO_HCI +#define HALMAC_SDIO_SUPPORT 1 +#else +#define HALMAC_SDIO_SUPPORT 0 +#endif +#ifdef CONFIG_USB_HCI +#define HALMAC_USB_SUPPORT 1 +#else +#define HALMAC_USB_SUPPORT 0 +#endif +#ifdef CONFIG_PCI_HCI +#define HALMAC_PCIE_SUPPORT 1 +#else +#define HALMAC_PCIE_SUPPORT 0 +#endif + #endif /* __HALMAC__HW_CFG_H__ */ diff --git a/hal/halmac/halmac_intf_phy_cmd.h b/hal/halmac/halmac_intf_phy_cmd.h index ec9b198..f44bfa1 100644 --- a/hal/halmac/halmac_intf_phy_cmd.h +++ b/hal/halmac/halmac_intf_phy_cmd.h @@ -1,8 +1,23 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef HALMAC_INTF_PHY_CMD #define HALMAC_INTF_PHY_CMD /* Cut mask */ -typedef enum _HALMAC_INTF_PHY_CUT { +enum halmac_intf_phy_cut { HALMAC_INTF_PHY_CUT_TESTCHIP = BIT(0), HALMAC_INTF_PHY_CUT_A = BIT(1), HALMAC_INTF_PHY_CUT_B = BIT(2), @@ -12,19 +27,19 @@ typedef enum _HALMAC_INTF_PHY_CUT { HALMAC_INTF_PHY_CUT_F = BIT(6), HALMAC_INTF_PHY_CUT_G = BIT(7), HALMAC_INTF_PHY_CUT_ALL = 0x7FFF, -} HALMAC_INTF_PHY_CUT; +}; /* IP selection */ -typedef enum _HALMAC_IP_SEL { - HALMAC_IP_SEL_INTF_PHY = 0, +enum halmac_ip_sel { + HALMAC_IP_INTF_PHY = 0, HALMAC_IP_SEL_MAC = 1, - HALMAC_IP_SEL_PCIE_DBI = 2, + HALMAC_IP_PCIE_DBI = 2, HALMAC_IP_SEL_UNDEFINE = 0x7FFF, -} HALMAC_IP_SEL; +}; /* Platform mask */ -typedef enum _HALMAC_INTF_PHY_PLATFORM { +enum halmac_intf_phy_platform { HALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF, -} HALMAC_INTF_PHY_PLATFORM; +}; #endif diff --git a/hal/halmac/halmac_original_c2h_ap.h b/hal/halmac/halmac_original_c2h_ap.h index 433da10..4f44d4f 100644 --- a/hal/halmac/halmac_original_c2h_ap.h +++ b/hal/halmac/halmac_original_c2h_ap.h @@ -1,336 +1,650 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_ #define _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_ -#define CMD_ID_C2H 0X00 -#define CMD_ID_DBG 0X00 -#define CMD_ID_C2H_LB 0X01 -#define CMD_ID_C2H_SND_TXBF 0X02 -#define CMD_ID_C2H_CCX_RPT 0X03 -#define CMD_ID_C2H_AP_REQ_TXRPT 0X04 -#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05 -#define CMD_ID_C2H_RA_RPT 0X0C -#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D -#define CMD_ID_C2H_RA_PARA_RPT 0X0E -#define CMD_ID_C2H_CUR_CHANNEL 0X10 -#define CMD_ID_C2H_GPIO_WAKEUP 0X14 -#define C2H_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define DBG_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define DBG_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define DBG_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define DBG_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define DBG_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define DBG_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define DBG_GET_DBG_STR1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define DBG_SET_DBG_STR1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define DBG_SET_DBG_STR1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define DBG_GET_DBG_STR2(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define DBG_SET_DBG_STR2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define DBG_SET_DBG_STR2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define DBG_GET_DBG_STR3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define DBG_SET_DBG_STR3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define DBG_SET_DBG_STR3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define DBG_GET_DBG_STR4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define DBG_SET_DBG_STR4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define DBG_SET_DBG_STR4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define DBG_GET_DBG_STR5(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) -#define DBG_SET_DBG_STR5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) -#define DBG_SET_DBG_STR5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) -#define DBG_GET_DBG_STR6(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) -#define DBG_SET_DBG_STR6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) -#define DBG_SET_DBG_STR6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) -#define DBG_GET_DBG_STR7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) -#define DBG_SET_DBG_STR7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) -#define DBG_SET_DBG_STR7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) -#define DBG_GET_DBG_STR8(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) -#define DBG_SET_DBG_STR8(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) -#define DBG_SET_DBG_STR8_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) -#define DBG_GET_DBG_STR9(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8) -#define DBG_SET_DBG_STR9(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value) -#define DBG_SET_DBG_STR9_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value) -#define DBG_GET_DBG_STR10(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 24, 8) -#define DBG_SET_DBG_STR10(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 24, 8, __Value) -#define DBG_SET_DBG_STR10_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 24, 8, __Value) -#define DBG_GET_DBG_STR11(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 0, 8) -#define DBG_SET_DBG_STR11(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 0, 8, __Value) -#define DBG_SET_DBG_STR11_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 0, 8, __Value) -#define DBG_GET_DBG_STR12(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 8, 8) -#define DBG_SET_DBG_STR12(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 8, 8, __Value) -#define DBG_SET_DBG_STR12_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 8, 8, __Value) -#define DBG_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define DBG_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define DBG_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define DBG_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define DBG_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define DBG_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_LB_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_LB_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_LB_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_LB_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_LB_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_LB_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_LB_GET_PAYLOAD1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 16) -#define C2H_LB_SET_PAYLOAD1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 16, __Value) -#define C2H_LB_SET_PAYLOAD1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 16, __Value) -#define C2H_LB_GET_PAYLOAD2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 32) -#define C2H_LB_SET_PAYLOAD2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 32, __Value) -#define C2H_LB_SET_PAYLOAD2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 32, __Value) -#define C2H_LB_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_LB_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_LB_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_LB_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_LB_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_LB_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SND_TXBF_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_SND_TXBF_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SND_TXBF_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SND_TXBF_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_SND_TXBF_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SND_TXBF_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SND_TXBF_GET_SND_RESULT(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 1) -#define C2H_SND_TXBF_SET_SND_RESULT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 1, __Value) -#define C2H_SND_TXBF_SET_SND_RESULT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 1, __Value) -#define C2H_SND_TXBF_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_SND_TXBF_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SND_TXBF_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SND_TXBF_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_SND_TXBF_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SND_TXBF_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CCX_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_CCX_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CCX_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CCX_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_CCX_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CCX_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CCX_RPT_GET_QSEL(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 5) -#define C2H_CCX_RPT_SET_QSEL(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 5, __Value) -#define C2H_CCX_RPT_SET_QSEL_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 5, __Value) -#define C2H_CCX_RPT_GET_BMC(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 21, 1) -#define C2H_CCX_RPT_SET_BMC(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 21, 1, __Value) -#define C2H_CCX_RPT_SET_BMC_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 21, 1, __Value) -#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 22, 1) -#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 22, 1, __Value) -#define C2H_CCX_RPT_SET_LIFE_TIME_OVER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 22, 1, __Value) -#define C2H_CCX_RPT_GET_RETRY_OVER(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 23, 1) -#define C2H_CCX_RPT_SET_RETRY_OVER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 23, 1, __Value) -#define C2H_CCX_RPT_SET_RETRY_OVER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 23, 1, __Value) -#define C2H_CCX_RPT_GET_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_CCX_RPT_SET_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_CCX_RPT_SET_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 6) -#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 6, __Value) -#define C2H_CCX_RPT_SET_DATA_RETRY_CNT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 6, __Value) -#define C2H_CCX_RPT_GET_QUEUE7_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define C2H_CCX_RPT_SET_QUEUE7_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_CCX_RPT_SET_QUEUE7_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_CCX_RPT_GET_QUEUE15_8(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) -#define C2H_CCX_RPT_SET_QUEUE15_8(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_CCX_RPT_SET_QUEUE15_8_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) -#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_CCX_RPT_GET_SW_DEFINE_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) -#define C2H_CCX_RPT_SET_SW_DEFINE_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_CCX_RPT_SET_SW_DEFINE_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_CCX_RPT_GET_SW_DEFINE_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 4) -#define C2H_CCX_RPT_SET_SW_DEFINE_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 4, __Value) -#define C2H_CCX_RPT_SET_SW_DEFINE_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 4, __Value) -#define C2H_CCX_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_CCX_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CCX_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CCX_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_CCX_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CCX_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 7) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 7, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 7, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_RA_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_RA_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_RPT_GET_RATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define C2H_RA_RPT_SET_RATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_RA_RPT_SET_RATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_RA_RPT_GET_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_RA_RPT_SET_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_RA_RPT_SET_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_RA_RPT_GET_USE_LDPC(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 1) -#define C2H_RA_RPT_SET_USE_LDPC(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 1, __Value) -#define C2H_RA_RPT_SET_USE_LDPC_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 1, __Value) -#define C2H_RA_RPT_GET_USE_TXBF(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 1, 1) -#define C2H_RA_RPT_SET_USE_TXBF(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 1, 1, __Value) -#define C2H_RA_RPT_SET_USE_TXBF_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 1, 1, __Value) -#define C2H_RA_RPT_GET_COLLISION_STATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define C2H_RA_RPT_SET_COLLISION_STATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_RA_RPT_SET_COLLISION_STATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_RA_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_RA_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_RA_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA0(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA5(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA6(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_DATA7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_PARA_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_RA_PARA_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_PARA_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_PARA_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_RA_PARA_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_PARA_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_PARA_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_RA_PARA_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_PARA_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_PARA_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_RA_PARA_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_PARA_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CUR_CHANNEL_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_CUR_CHANNEL_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CUR_CHANNEL_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CUR_CHANNEL_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_CUR_CHANNEL_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CUR_CHANNEL_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) -#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) -#define C2H_CUR_CHANNEL_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_CUR_CHANNEL_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CUR_CHANNEL_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CUR_CHANNEL_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_CUR_CHANNEL_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CUR_CHANNEL_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) -#define C2H_GPIO_WAKEUP_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_GPIO_WAKEUP_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) -#define C2H_GPIO_WAKEUP_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_GPIO_WAKEUP_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) -#define C2H_GPIO_WAKEUP_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_GPIO_WAKEUP_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) -#define C2H_GPIO_WAKEUP_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define CMD_ID_C2H 0X00 +#define CMD_ID_DBG 0X00 +#define CMD_ID_C2H_LB 0X01 +#define CMD_ID_C2H_SND_TXBF 0X02 +#define CMD_ID_C2H_CCX_RPT 0X03 +#define CMD_ID_C2H_AP_REQ_TXRPT 0X04 +#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05 +#define CMD_ID_C2H_RA_RPT 0X0C +#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D +#define CMD_ID_C2H_RA_PARA_RPT 0X0E +#define CMD_ID_C2H_CUR_CHANNEL 0X10 +#define CMD_ID_C2H_GPIO_WAKEUP 0X14 +#define CMD_ID_C2H_DROPID_RPT 0X2D +#define C2H_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define DBG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define DBG_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define DBG_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define DBG_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define DBG_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define DBG_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define DBG_GET_DBG_STR1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define DBG_SET_DBG_STR1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define DBG_SET_DBG_STR1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define DBG_GET_DBG_STR2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define DBG_SET_DBG_STR2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define DBG_SET_DBG_STR2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define DBG_GET_DBG_STR3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define DBG_SET_DBG_STR3(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define DBG_SET_DBG_STR3_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define DBG_GET_DBG_STR4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define DBG_SET_DBG_STR4(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define DBG_SET_DBG_STR4_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define DBG_GET_DBG_STR5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define DBG_SET_DBG_STR5(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define DBG_SET_DBG_STR5_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define DBG_GET_DBG_STR6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define DBG_SET_DBG_STR6(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define DBG_SET_DBG_STR6_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define DBG_GET_DBG_STR7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8) +#define DBG_SET_DBG_STR7(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value) +#define DBG_SET_DBG_STR7_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value) +#define DBG_GET_DBG_STR8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8) +#define DBG_SET_DBG_STR8(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value) +#define DBG_SET_DBG_STR8_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value) +#define DBG_GET_DBG_STR9(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8) +#define DBG_SET_DBG_STR9(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value) +#define DBG_SET_DBG_STR9_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value) +#define DBG_GET_DBG_STR10(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8) +#define DBG_SET_DBG_STR10(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value) +#define DBG_SET_DBG_STR10_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value) +#define DBG_GET_DBG_STR11(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8) +#define DBG_SET_DBG_STR11(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value) +#define DBG_SET_DBG_STR11_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value) +#define DBG_GET_DBG_STR12(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8) +#define DBG_SET_DBG_STR12(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value) +#define DBG_SET_DBG_STR12_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value) +#define DBG_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define DBG_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define DBG_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define DBG_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define DBG_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define DBG_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_LB_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_LB_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_LB_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_LB_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_LB_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_LB_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_LB_GET_PAYLOAD1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 16) +#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 16, value) +#define C2H_LB_SET_PAYLOAD1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 16, value) +#define C2H_LB_GET_PAYLOAD2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 32) +#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 32, value) +#define C2H_LB_SET_PAYLOAD2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 32, value) +#define C2H_LB_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_LB_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_LB_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_LB_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_LB_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_LB_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SND_TXBF_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SND_TXBF_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 1) +#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 1, value) +#define C2H_SND_TXBF_SET_SND_RESULT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 1, value) +#define C2H_SND_TXBF_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SND_TXBF_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SND_TXBF_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CCX_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CCX_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 5) +#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 5, value) +#define C2H_CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 5, value) +#define C2H_CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 21, 1) +#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 21, 1, value) +#define C2H_CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 21, 1, value) +#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 22, 1) +#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 22, 1, value) +#define C2H_CCX_RPT_SET_LIFE_TIME_OVER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 22, 1, value) +#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 23, 1) +#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 23, 1, value) +#define C2H_CCX_RPT_SET_RETRY_OVER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 23, 1, value) +#define C2H_CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 6) +#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 6, value) +#define C2H_CCX_RPT_SET_DATA_RETRY_CNT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 6, value) +#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_CCX_RPT_SET_QUEUE7_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_CCX_RPT_SET_QUEUE15_8_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8) +#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_CCX_RPT_SET_SW_DEFINE_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 4) +#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 4, value) +#define C2H_CCX_RPT_SET_SW_DEFINE_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 4, value) +#define C2H_CCX_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CCX_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CCX_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_AP_REQ_TXRPT_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_AP_REQ_TXRPT_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_AP_REQ_TXRPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 7) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 7, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 7, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_RPT_GET_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define C2H_RA_RPT_SET_RATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_RA_RPT_SET_RATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_RA_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_RA_RPT_SET_MACID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_RA_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 1) +#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 1, value) +#define C2H_RA_RPT_SET_USE_LDPC_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 1, value) +#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 1, 1) +#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 1, 1, value) +#define C2H_RA_RPT_SET_USE_TXBF_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 1, 1, value) +#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_RA_RPT_SET_COLLISION_STATE_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_RA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_RA_RPT_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA0_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA1_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA2_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA3_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA4_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA5_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA6_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_DATA7_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_PARA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_PARA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_PARA_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_PARA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CUR_CHANNEL_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CUR_CHANNEL_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8) +#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value) +#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CUR_CHANNEL_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CUR_CHANNEL_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_GPIO_WAKEUP_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_GPIO_WAKEUP_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_GPIO_WAKEUP_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_DROPID_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8) +#define C2H_DROPID_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_DROPID_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value) +#define C2H_DROPID_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8) +#define C2H_DROPID_RPT_SET_SEQ(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_DROPID_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value) +#define C2H_DROPID_RPT_GET_DROPIDBIT(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 16, 4) +#define C2H_DROPID_RPT_SET_DROPIDBIT(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 4, value) +#define C2H_DROPID_RPT_SET_DROPIDBIT_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 4, value) +#define C2H_DROPID_RPT_GET_CURDROPID(c2h_pkt) \ + GET_C2H_FIELD(c2h_pkt + 0X00, 20, 2) +#define C2H_DROPID_RPT_SET_CURDROPID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 20, 2, value) +#define C2H_DROPID_RPT_SET_CURDROPID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 20, 2, value) +#define C2H_DROPID_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8) +#define C2H_DROPID_RPT_SET_MACID(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_DROPID_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value) +#define C2H_DROPID_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8) +#define C2H_DROPID_RPT_SET_LEN(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_DROPID_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_DROPID_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8) +#define C2H_DROPID_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_DROPID_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \ + SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value) #endif diff --git a/hal/halmac/halmac_original_c2h_nic.h b/hal/halmac/halmac_original_c2h_nic.h index b72c1ce..616487e 100644 --- a/hal/halmac/halmac_original_c2h_nic.h +++ b/hal/halmac/halmac_original_c2h_nic.h @@ -1,229 +1,434 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_ #define _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_ -#define CMD_ID_C2H 0X00 -#define CMD_ID_DBG 0X00 -#define CMD_ID_C2H_LB 0X01 -#define CMD_ID_C2H_SND_TXBF 0X02 -#define CMD_ID_C2H_CCX_RPT 0X03 -#define CMD_ID_C2H_AP_REQ_TXRPT 0X04 -#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05 -#define CMD_ID_C2H_RA_RPT 0X0C -#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D -#define CMD_ID_C2H_RA_PARA_RPT 0X0E -#define CMD_ID_C2H_CUR_CHANNEL 0X10 -#define CMD_ID_C2H_GPIO_WAKEUP 0X14 -#define C2H_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define DBG_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define DBG_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define DBG_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define DBG_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define DBG_GET_DBG_STR1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define DBG_SET_DBG_STR1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define DBG_GET_DBG_STR2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define DBG_SET_DBG_STR2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define DBG_GET_DBG_STR3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define DBG_SET_DBG_STR3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define DBG_GET_DBG_STR4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define DBG_SET_DBG_STR4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define DBG_GET_DBG_STR5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) -#define DBG_SET_DBG_STR5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) -#define DBG_GET_DBG_STR6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) -#define DBG_SET_DBG_STR6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) -#define DBG_GET_DBG_STR7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) -#define DBG_SET_DBG_STR7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) -#define DBG_GET_DBG_STR8(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) -#define DBG_SET_DBG_STR8(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) -#define DBG_GET_DBG_STR9(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8) -#define DBG_SET_DBG_STR9(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value) -#define DBG_GET_DBG_STR10(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 24, 8) -#define DBG_SET_DBG_STR10(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 24, 8, __Value) -#define DBG_GET_DBG_STR11(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 0, 8) -#define DBG_SET_DBG_STR11(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 0, 8, __Value) -#define DBG_GET_DBG_STR12(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 8, 8) -#define DBG_SET_DBG_STR12(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 8, 8, __Value) -#define DBG_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define DBG_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define DBG_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define DBG_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_LB_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_LB_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_LB_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_LB_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_LB_GET_PAYLOAD1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 16) -#define C2H_LB_SET_PAYLOAD1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 16, __Value) -#define C2H_LB_GET_PAYLOAD2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 32) -#define C2H_LB_SET_PAYLOAD2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 32, __Value) -#define C2H_LB_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_LB_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_LB_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_LB_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SND_TXBF_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_SND_TXBF_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SND_TXBF_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_SND_TXBF_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SND_TXBF_GET_SND_RESULT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 1) -#define C2H_SND_TXBF_SET_SND_RESULT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 1, __Value) -#define C2H_SND_TXBF_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_SND_TXBF_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SND_TXBF_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_SND_TXBF_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CCX_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_CCX_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CCX_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_CCX_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CCX_RPT_GET_QSEL(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 5) -#define C2H_CCX_RPT_SET_QSEL(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 5, __Value) -#define C2H_CCX_RPT_GET_BMC(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 21, 1) -#define C2H_CCX_RPT_SET_BMC(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 21, 1, __Value) -#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 22, 1) -#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 22, 1, __Value) -#define C2H_CCX_RPT_GET_RETRY_OVER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 23, 1) -#define C2H_CCX_RPT_SET_RETRY_OVER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 23, 1, __Value) -#define C2H_CCX_RPT_GET_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_CCX_RPT_SET_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 6) -#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 6, __Value) -#define C2H_CCX_RPT_GET_QUEUE7_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define C2H_CCX_RPT_SET_QUEUE7_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define C2H_CCX_RPT_GET_QUEUE15_8(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) -#define C2H_CCX_RPT_SET_QUEUE15_8(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) -#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) -#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) -#define C2H_CCX_RPT_GET_SW_DEFINE_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) -#define C2H_CCX_RPT_SET_SW_DEFINE_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) -#define C2H_CCX_RPT_GET_SW_DEFINE_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 4) -#define C2H_CCX_RPT_SET_SW_DEFINE_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 4, __Value) -#define C2H_CCX_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_CCX_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CCX_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_CCX_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 24, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 0, 8) -#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 0, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 8, 8) -#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 8, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_AP_REQ_TXRPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_AP_REQ_TXRPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_AP_REQ_TXRPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 7) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 7, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_RA_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_RA_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_RPT_GET_RATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define C2H_RA_RPT_SET_RATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define C2H_RA_RPT_GET_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_RA_RPT_SET_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_RA_RPT_GET_USE_LDPC(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 1) -#define C2H_RA_RPT_SET_USE_LDPC(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 1, __Value) -#define C2H_RA_RPT_GET_USE_TXBF(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 1, 1) -#define C2H_RA_RPT_SET_USE_TXBF(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 1, 1, __Value) -#define C2H_RA_RPT_GET_COLLISION_STATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define C2H_RA_RPT_SET_COLLISION_STATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define C2H_RA_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_RA_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_RA_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_DATA7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_DATA7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_SPECIAL_STATISTICS_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_RA_PARA_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_RA_PARA_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_RA_PARA_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_RA_PARA_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_RA_PARA_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_RA_PARA_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_RA_PARA_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_RA_PARA_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_CUR_CHANNEL_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_CUR_CHANNEL_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_CUR_CHANNEL_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_CUR_CHANNEL_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) -#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) -#define C2H_CUR_CHANNEL_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_CUR_CHANNEL_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_CUR_CHANNEL_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_CUR_CHANNEL_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) -#define C2H_GPIO_WAKEUP_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) -#define C2H_GPIO_WAKEUP_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) -#define C2H_GPIO_WAKEUP_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) -#define C2H_GPIO_WAKEUP_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) -#define C2H_GPIO_WAKEUP_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define CMD_ID_C2H 0X00 +#define CMD_ID_DBG 0X00 +#define CMD_ID_C2H_LB 0X01 +#define CMD_ID_C2H_SND_TXBF 0X02 +#define CMD_ID_C2H_CCX_RPT 0X03 +#define CMD_ID_C2H_AP_REQ_TXRPT 0X04 +#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05 +#define CMD_ID_C2H_RA_RPT 0X0C +#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D +#define CMD_ID_C2H_RA_PARA_RPT 0X0E +#define CMD_ID_C2H_CUR_CHANNEL 0X10 +#define CMD_ID_C2H_GPIO_WAKEUP 0X14 +#define CMD_ID_C2H_DROPID_RPT 0X2D +#define C2H_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define DBG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define DBG_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define DBG_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define DBG_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define DBG_GET_DBG_STR1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define DBG_SET_DBG_STR1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define DBG_GET_DBG_STR2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define DBG_SET_DBG_STR2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define DBG_GET_DBG_STR3(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define DBG_SET_DBG_STR3(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define DBG_GET_DBG_STR4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define DBG_SET_DBG_STR4(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define DBG_GET_DBG_STR5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define DBG_SET_DBG_STR5(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define DBG_GET_DBG_STR6(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define DBG_SET_DBG_STR6(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define DBG_GET_DBG_STR7(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8) +#define DBG_SET_DBG_STR7(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value) +#define DBG_GET_DBG_STR8(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8) +#define DBG_SET_DBG_STR8(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value) +#define DBG_GET_DBG_STR9(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8) +#define DBG_SET_DBG_STR9(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value) +#define DBG_GET_DBG_STR10(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8) +#define DBG_SET_DBG_STR10(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value) +#define DBG_GET_DBG_STR11(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8) +#define DBG_SET_DBG_STR11(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value) +#define DBG_GET_DBG_STR12(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8) +#define DBG_SET_DBG_STR12(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value) +#define DBG_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define DBG_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define DBG_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define DBG_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_LB_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_LB_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_LB_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_LB_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_LB_GET_PAYLOAD1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 16) +#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 16, value) +#define C2H_LB_GET_PAYLOAD2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 32) +#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 32, value) +#define C2H_LB_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_LB_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_LB_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_LB_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 1) +#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 1, value) +#define C2H_SND_TXBF_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 5) +#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 5, value) +#define C2H_CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 21, 1) +#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 21, 1, value) +#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 22, 1) +#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 22, 1, value) +#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 23, 1) +#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 23, 1, value) +#define C2H_CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 6) +#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 6, value) +#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8) +#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value) +#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 4) +#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 4, value) +#define C2H_CCX_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value) +#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 7) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 7, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_RPT_GET_RATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define C2H_RA_RPT_SET_RATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define C2H_RA_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_RA_RPT_SET_MACID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 1) +#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 1, value) +#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 1, 1) +#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 1, 1, value) +#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define C2H_RA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_RA_RPT_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8) +#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value) +#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) +#define C2H_DROPID_RPT_GET_CMD_ID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8) +#define C2H_DROPID_RPT_SET_CMD_ID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value) +#define C2H_DROPID_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8) +#define C2H_DROPID_RPT_SET_SEQ(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value) +#define C2H_DROPID_RPT_GET_DROPIDBIT(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 4) +#define C2H_DROPID_RPT_SET_DROPIDBIT(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 4, value) +#define C2H_DROPID_RPT_GET_CURDROPID(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 20, 2) +#define C2H_DROPID_RPT_SET_CURDROPID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 20, 2, value) +#define C2H_DROPID_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) +#define C2H_DROPID_RPT_SET_MACID(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value) +#define C2H_DROPID_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8) +#define C2H_DROPID_RPT_SET_LEN(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value) +#define C2H_DROPID_RPT_GET_TRIGGER(c2h_pkt) \ + LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8) +#define C2H_DROPID_RPT_SET_TRIGGER(c2h_pkt, value) \ + SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value) #endif diff --git a/hal/halmac/halmac_original_h2c_ap.h b/hal/halmac/halmac_original_h2c_ap.h index 1b8f14e..b28c995 100644 --- a/hal/halmac/halmac_original_h2c_ap.h +++ b/hal/halmac/halmac_original_h2c_ap.h @@ -1,39 +1,57 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_ #define _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_ -#define CMD_ID_ORIGINAL_H2C 0X00 -#define CMD_ID_H2C2H_LB 0X0 -#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06 -#define CMD_ID_RSVD_PAGE 0X0 -#define CMD_ID_MEDIA_STATUS_RPT 0X01 -#define CMD_ID_KEEP_ALIVE 0X03 -#define CMD_ID_DISCONNECT_DECISION 0X04 -#define CMD_ID_AP_OFFLOAD 0X08 -#define CMD_ID_BCN_RSVDPAGE 0X09 -#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A -#define CMD_ID_SET_PWR_MODE 0X00 -#define CMD_ID_PS_TUNING_PARA 0X01 -#define CMD_ID_PS_TUNING_PARA_II 0X02 -#define CMD_ID_PS_LPS_PARA 0X03 -#define CMD_ID_P2P_PS_OFFLOAD 0X04 -#define CMD_ID_PS_SCAN_EN 0X05 -#define CMD_ID_SAP_PS 0X06 -#define CMD_ID_INACTIVE_PS 0X07 -#define CMD_ID_MACID_CFG 0X00 -#define CMD_ID_TXBF 0X01 -#define CMD_ID_RSSI_SETTING 0X02 -#define CMD_ID_AP_REQ_TXRPT 0X03 -#define CMD_ID_INIT_RATE_COLLECTION 0X04 -#define CMD_ID_IQK_OFFLOAD 0X05 -#define CMD_ID_MACID_CFG_3SS 0X06 -#define CMD_ID_RA_PARA_ADJUST 0X07 -#define CMD_ID_WWLAN 0X00 -#define CMD_ID_REMOTE_WAKE_CTRL 0X01 -#define CMD_ID_AOAC_GLOBAL_INFO 0X02 -#define CMD_ID_AOAC_RSVD_PAGE 0X03 -#define CMD_ID_AOAC_RSVD_PAGE2 0X04 -#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 -#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07 -#define CMD_ID_AOAC_RSVD_PAGE3 0X08 +#define CMD_ID_ORIGINAL_H2C 0X00 +#define CMD_ID_H2C2H_LB 0X0 +#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06 +#define CMD_ID_RSVD_PAGE 0X0 +#define CMD_ID_MEDIA_STATUS_RPT 0X01 +#define CMD_ID_KEEP_ALIVE 0X03 +#define CMD_ID_DISCONNECT_DECISION 0X04 +#define CMD_ID_AP_OFFLOAD 0X08 +#define CMD_ID_BCN_RSVDPAGE 0X09 +#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A +#define CMD_ID_SINGLE_CHANNELSWITCH 0X1C +#define CMD_ID_SINGLE_CHANNELSWITCH_V2 0X1D +#define CMD_ID_SET_PWR_MODE 0X00 +#define CMD_ID_PS_TUNING_PARA 0X01 +#define CMD_ID_PS_TUNING_PARA_II 0X02 +#define CMD_ID_PS_LPS_PARA 0X03 +#define CMD_ID_P2P_PS_OFFLOAD 0X04 +#define CMD_ID_PS_SCAN_EN 0X05 +#define CMD_ID_SAP_PS 0X06 +#define CMD_ID_INACTIVE_PS 0X07 +#define CMD_ID_MACID_CFG 0X00 +#define CMD_ID_TXBF 0X01 +#define CMD_ID_RSSI_SETTING 0X02 +#define CMD_ID_AP_REQ_TXRPT 0X03 +#define CMD_ID_INIT_RATE_COLLECTION 0X04 +#define CMD_ID_IQK_OFFLOAD 0X05 +#define CMD_ID_MACID_CFG_3SS 0X06 +#define CMD_ID_RA_PARA_ADJUST 0X07 +#define CMD_ID_WWLAN 0X00 +#define CMD_ID_REMOTE_WAKE_CTRL 0X01 +#define CMD_ID_AOAC_GLOBAL_INFO 0X02 +#define CMD_ID_AOAC_RSVD_PAGE 0X03 +#define CMD_ID_AOAC_RSVD_PAGE2 0X04 +#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 +#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07 +#define CMD_ID_AOAC_RSVD_PAGE3 0X08 +#define CMD_ID_DBG_MSG_CTRL 0X1E #define CLASS_ORIGINAL_H2C 0X00 #define CLASS_H2C2H_LB 0X07 #define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04 @@ -44,6 +62,8 @@ #define CLASS_AP_OFFLOAD 0X0 #define CLASS_BCN_RSVDPAGE 0X0 #define CLASS_PROBE_RSP_RSVDPAGE 0X0 +#define CLASS_SINGLE_CHANNELSWITCH 0X0 +#define CLASS_SINGLE_CHANNELSWITCH_V2 0X0 #define CLASS_SET_PWR_MODE 0X01 #define CLASS_PS_TUNING_PARA 0X01 #define CLASS_PS_TUNING_PARA_II 0X01 @@ -68,811 +88,1574 @@ #define CLASS_D0_SCAN_OFFLOAD_INFO 0X04 #define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04 #define CLASS_AOAC_RSVD_PAGE3 0X04 -#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define ORIGINAL_H2C_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define ORIGINAL_H2C_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define ORIGINAL_H2C_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define ORIGINAL_H2C_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define H2C2H_LB_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define H2C2H_LB_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define H2C2H_LB_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_GET_SEQ(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define H2C2H_LB_SET_SEQ(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define H2C2H_LB_SET_SEQ_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define H2C2H_LB_GET_PAYLOAD1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 16) -#define H2C2H_LB_SET_PAYLOAD1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 16, __Value) -#define H2C2H_LB_SET_PAYLOAD1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 16, __Value) -#define H2C2H_LB_GET_PAYLOAD2(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 32) -#define H2C2H_LB_SET_PAYLOAD2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 32, __Value) -#define H2C2H_LB_SET_PAYLOAD2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 32, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 17) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 17, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 17, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RSVD_PAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RSVD_PAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RSVD_PAGE_GET_LOC_PROBE_RSP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define RSVD_PAGE_SET_LOC_PROBE_RSP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RSVD_PAGE_SET_LOC_PROBE_RSP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RSVD_PAGE_GET_LOC_PS_POLL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define RSVD_PAGE_SET_LOC_PS_POLL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define RSVD_PAGE_SET_LOC_PS_POLL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define RSVD_PAGE_GET_LOC_NULL_DATA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define RSVD_PAGE_SET_LOC_NULL_DATA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RSVD_PAGE_SET_LOC_NULL_DATA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RSVD_PAGE_GET_LOC_QOS_NULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define RSVD_PAGE_SET_LOC_QOS_NULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_SET_LOC_QOS_NULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define RSVD_PAGE_SET_LOC_BT_QOS_NULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define RSVD_PAGE_GET_LOC_CTS2SELF(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define RSVD_PAGE_SET_LOC_CTS2SELF(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define RSVD_PAGE_SET_LOC_CTS2SELF_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MEDIA_STATUS_RPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MEDIA_STATUS_RPT_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define MEDIA_STATUS_RPT_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MEDIA_STATUS_RPT_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MEDIA_STATUS_RPT_GET_OP_MODE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define MEDIA_STATUS_RPT_SET_OP_MODE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define MEDIA_STATUS_RPT_SET_OP_MODE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define MEDIA_STATUS_RPT_GET_MACID_IN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define MEDIA_STATUS_RPT_SET_MACID_IN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define MEDIA_STATUS_RPT_SET_MACID_IN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define MEDIA_STATUS_RPT_GET_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define MEDIA_STATUS_RPT_SET_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define MEDIA_STATUS_RPT_SET_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define MEDIA_STATUS_RPT_GET_MACID_END(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define MEDIA_STATUS_RPT_SET_MACID_END(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define MEDIA_STATUS_RPT_SET_MACID_END_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define KEEP_ALIVE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define KEEP_ALIVE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define KEEP_ALIVE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define KEEP_ALIVE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define KEEP_ALIVE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define KEEP_ALIVE_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define KEEP_ALIVE_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define KEEP_ALIVE_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define KEEP_ALIVE_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define KEEP_ALIVE_GET_PKT_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define KEEP_ALIVE_SET_PKT_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define KEEP_ALIVE_SET_PKT_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define DISCONNECT_DECISION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define DISCONNECT_DECISION_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define DISCONNECT_DECISION_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define DISCONNECT_DECISION_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define DISCONNECT_DECISION_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define DISCONNECT_DECISION_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define DISCONNECT_DECISION_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define DISCONNECT_DECISION_GET_DISCONNECT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define DISCONNECT_DECISION_SET_DISCONNECT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define DISCONNECT_DECISION_SET_DISCONNECT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define DISCONNECT_DECISION_SET_TRY_PKT_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AP_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AP_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AP_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AP_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AP_OFFLOAD_GET_ON(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define AP_OFFLOAD_SET_ON(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define AP_OFFLOAD_SET_ON_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define AP_OFFLOAD_GET_LINKED(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define AP_OFFLOAD_SET_LINKED(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define AP_OFFLOAD_SET_LINKED_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define AP_OFFLOAD_GET_EN_AUTO_WAKE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define AP_OFFLOAD_SET_EN_AUTO_WAKE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define AP_OFFLOAD_SET_EN_AUTO_WAKE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define AP_OFFLOAD_GET_WAKE_FLAG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) -#define AP_OFFLOAD_SET_WAKE_FLAG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) -#define AP_OFFLOAD_SET_WAKE_FLAG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 1) -#define AP_OFFLOAD_SET_HIDDEN_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 1, __Value) -#define AP_OFFLOAD_SET_HIDDEN_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 17, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 17, 1, __Value) -#define AP_OFFLOAD_SET_HIDDEN_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 17, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 18, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 18, 1, __Value) -#define AP_OFFLOAD_SET_HIDDEN_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 18, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 19, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 19, 1, __Value) -#define AP_OFFLOAD_SET_HIDDEN_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 19, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 20, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 20, 1, __Value) -#define AP_OFFLOAD_SET_HIDDEN_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 20, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1) -#define AP_OFFLOAD_SET_DENYANY_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value) -#define AP_OFFLOAD_SET_DENYANY_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 25, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 25, 1, __Value) -#define AP_OFFLOAD_SET_DENYANY_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 25, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 26, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 26, 1, __Value) -#define AP_OFFLOAD_SET_DENYANY_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 26, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 27, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 27, 1, __Value) -#define AP_OFFLOAD_SET_DENYANY_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 27, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 1, __Value) -#define AP_OFFLOAD_SET_DENYANY_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 1, __Value) -#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_SET_WAIT_TBTT_CNT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_GET_WAKE_TIMEOUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define AP_OFFLOAD_SET_WAKE_TIMEOUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AP_OFFLOAD_SET_WAKE_TIMEOUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AP_OFFLOAD_GET_LEN_IV_PAIR(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define AP_OFFLOAD_SET_LEN_IV_PAIR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AP_OFFLOAD_SET_LEN_IV_PAIR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AP_OFFLOAD_GET_LEN_IV_GRP(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define AP_OFFLOAD_SET_LEN_IV_GRP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define AP_OFFLOAD_SET_LEN_IV_GRP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define BCN_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define BCN_RSVDPAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define BCN_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define BCN_RSVDPAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define BCN_RSVDPAGE_GET_LOC_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define BCN_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define BCN_RSVDPAGE_SET_LOC_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define BCN_RSVDPAGE_SET_LOC_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define BCN_RSVDPAGE_SET_LOC_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define BCN_RSVDPAGE_SET_LOC_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define BCN_RSVDPAGE_SET_LOC_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PROBE_RSP_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PROBE_RSP_RSVDPAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define PROBE_RSP_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PROBE_RSP_RSVDPAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define SET_PWR_MODE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define SET_PWR_MODE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define SET_PWR_MODE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define SET_PWR_MODE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define SET_PWR_MODE_GET_MODE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7) -#define SET_PWR_MODE_SET_MODE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value) -#define SET_PWR_MODE_SET_MODE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value) -#define SET_PWR_MODE_GET_CLK_REQUEST(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) -#define SET_PWR_MODE_SET_CLK_REQUEST(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) -#define SET_PWR_MODE_SET_CLK_REQUEST_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) -#define SET_PWR_MODE_GET_RLBM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 4) -#define SET_PWR_MODE_SET_RLBM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 4, __Value) -#define SET_PWR_MODE_SET_RLBM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 4, __Value) -#define SET_PWR_MODE_GET_SMART_PS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 20, 4) -#define SET_PWR_MODE_SET_SMART_PS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 20, 4, __Value) -#define SET_PWR_MODE_SET_SMART_PS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 20, 4, __Value) -#define SET_PWR_MODE_GET_AWAKE_INTERVAL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define SET_PWR_MODE_SET_AWAKE_INTERVAL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define SET_PWR_MODE_SET_AWAKE_INTERVAL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 1) -#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 1, __Value) -#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 1, __Value) -#define SET_PWR_MODE_GET_BCN_EARLY_RPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 2, 1) -#define SET_PWR_MODE_SET_BCN_EARLY_RPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 2, 1, __Value) -#define SET_PWR_MODE_SET_BCN_EARLY_RPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 2, 1, __Value) -#define SET_PWR_MODE_GET_PORT_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 5, 3) -#define SET_PWR_MODE_SET_PORT_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 5, 3, __Value) -#define SET_PWR_MODE_SET_PORT_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 5, 3, __Value) -#define SET_PWR_MODE_GET_PWR_STATE(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define SET_PWR_MODE_SET_PWR_STATE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 1) -#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 1, __Value) -#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 1, __Value) -#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 17, 1) -#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 17, 1, __Value) -#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 17, 1, __Value) -#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 18, 1) -#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 18, 1, __Value) -#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 18, 1, __Value) -#define SET_PWR_MODE_GET_PROTECT_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 19, 1) -#define SET_PWR_MODE_SET_PROTECT_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 19, 1, __Value) -#define SET_PWR_MODE_SET_PROTECT_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 19, 1, __Value) -#define SET_PWR_MODE_GET_SILENCE_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 20, 1) -#define SET_PWR_MODE_SET_SILENCE_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 20, 1, __Value) -#define SET_PWR_MODE_SET_SILENCE_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 20, 1, __Value) -#define SET_PWR_MODE_GET_FAST_BT_CONNECT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 21, 1) -#define SET_PWR_MODE_SET_FAST_BT_CONNECT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 21, 1, __Value) -#define SET_PWR_MODE_SET_FAST_BT_CONNECT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 21, 1, __Value) -#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 22, 1) -#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 22, 1, __Value) -#define SET_PWR_MODE_SET_TWO_ANTENNA_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 22, 1, __Value) -#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 1) -#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 1, __Value) -#define SET_PWR_MODE_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 1, __Value) -#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 25, 3) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 25, 3, __Value) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 25, 3, __Value) -#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 28, 4) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 28, 4, __Value) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 28, 4, __Value) -#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define PS_TUNING_PARA_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7) -#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_SET_BCN_TO_LIMIT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) -#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_SET_DTIM_TIME_OUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_GET_PS_TIME_OUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 4) -#define PS_TUNING_PARA_SET_PS_TIME_OUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 4, __Value) -#define PS_TUNING_PARA_SET_PS_TIME_OUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 4, __Value) -#define PS_TUNING_PARA_GET_ADOPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define PS_TUNING_PARA_SET_ADOPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define PS_TUNING_PARA_SET_ADOPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_II_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_II_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define PS_TUNING_PARA_II_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_II_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7) -#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_II_GET_ADOPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) -#define PS_TUNING_PARA_II_SET_ADOPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_II_SET_ADOPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define PS_LPS_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_LPS_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_LPS_PARA_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define PS_LPS_PARA_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_LPS_PARA_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_LPS_PARA_GET_LPS_CONTROL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define PS_LPS_PARA_SET_LPS_CONTROL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define PS_LPS_PARA_SET_LPS_CONTROL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define P2P_PS_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define P2P_PS_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define P2P_PS_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define P2P_PS_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define P2P_PS_OFFLOAD_GET_ROLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define P2P_PS_OFFLOAD_SET_ROLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define P2P_PS_OFFLOAD_SET_ROLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define P2P_PS_OFFLOAD_GET_NOA0_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define P2P_PS_OFFLOAD_SET_NOA0_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define P2P_PS_OFFLOAD_SET_NOA0_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define P2P_PS_OFFLOAD_GET_NOA1_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) -#define P2P_PS_OFFLOAD_SET_NOA1_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) -#define P2P_PS_OFFLOAD_SET_NOA1_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) -#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1) -#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value) -#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value) -#define P2P_PS_OFFLOAD_GET_DISCOVERY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1) -#define P2P_PS_OFFLOAD_SET_DISCOVERY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value) -#define P2P_PS_OFFLOAD_SET_DISCOVERY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value) -#define PS_SCAN_EN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_SCAN_EN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define PS_SCAN_EN_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define PS_SCAN_EN_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_SCAN_EN_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define PS_SCAN_EN_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define PS_SCAN_EN_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define PS_SCAN_EN_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define SAP_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define SAP_PS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define SAP_PS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define SAP_PS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define SAP_PS_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define SAP_PS_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_GET_EN_PS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define SAP_PS_SET_EN_PS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define SAP_PS_SET_EN_PS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define SAP_PS_GET_EN_LP_RX(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define SAP_PS_SET_EN_LP_RX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define SAP_PS_SET_EN_LP_RX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define SAP_PS_GET_MANUAL_32K(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define SAP_PS_SET_MANUAL_32K(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define SAP_PS_SET_MANUAL_32K_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define SAP_PS_GET_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define SAP_PS_SET_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define SAP_PS_SET_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define INACTIVE_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define INACTIVE_PS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define INACTIVE_PS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define INACTIVE_PS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define INACTIVE_PS_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define INACTIVE_PS_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define INACTIVE_PS_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define INACTIVE_PS_SET_IGNORE_PS_CONDITION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define INACTIVE_PS_GET_FREQUENCY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define INACTIVE_PS_SET_FREQUENCY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_SET_FREQUENCY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_GET_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define INACTIVE_PS_SET_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define INACTIVE_PS_SET_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define MACID_CFG_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define MACID_CFG_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define MACID_CFG_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_GET_RATE_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 5) -#define MACID_CFG_SET_RATE_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 5, __Value) -#define MACID_CFG_SET_RATE_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 5, __Value) -#define MACID_CFG_GET_INIT_RATE_LV(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 21, 2) -#define MACID_CFG_SET_INIT_RATE_LV(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 21, 2, __Value) -#define MACID_CFG_SET_INIT_RATE_LV_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 21, 2, __Value) -#define MACID_CFG_GET_SGI(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 23, 1) -#define MACID_CFG_SET_SGI(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 23, 1, __Value) -#define MACID_CFG_SET_SGI_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 23, 1, __Value) -#define MACID_CFG_GET_BW(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 2) -#define MACID_CFG_SET_BW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 2, __Value) -#define MACID_CFG_SET_BW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 2, __Value) -#define MACID_CFG_GET_LDPC_CAP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 26, 1) -#define MACID_CFG_SET_LDPC_CAP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 26, 1, __Value) -#define MACID_CFG_SET_LDPC_CAP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 26, 1, __Value) -#define MACID_CFG_GET_NO_UPDATE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 27, 1) -#define MACID_CFG_SET_NO_UPDATE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 27, 1, __Value) -#define MACID_CFG_SET_NO_UPDATE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 27, 1, __Value) -#define MACID_CFG_GET_WHT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 2) -#define MACID_CFG_SET_WHT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 2, __Value) -#define MACID_CFG_SET_WHT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 2, __Value) -#define MACID_CFG_GET_DISPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 30, 1) -#define MACID_CFG_SET_DISPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 30, 1, __Value) -#define MACID_CFG_SET_DISPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 30, 1, __Value) -#define MACID_CFG_GET_DISRA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 31, 1) -#define MACID_CFG_SET_DISRA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 31, 1, __Value) -#define MACID_CFG_SET_DISRA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 31, 1, __Value) -#define MACID_CFG_GET_RATE_MASK7_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define MACID_CFG_SET_RATE_MASK7_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_SET_RATE_MASK7_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_GET_RATE_MASK15_8(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define MACID_CFG_SET_RATE_MASK15_8(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define MACID_CFG_SET_RATE_MASK15_8_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define MACID_CFG_GET_RATE_MASK23_16(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define MACID_CFG_SET_RATE_MASK23_16(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define MACID_CFG_SET_RATE_MASK23_16_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define MACID_CFG_GET_RATE_MASK31_24(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define MACID_CFG_SET_RATE_MASK31_24(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define MACID_CFG_SET_RATE_MASK31_24_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define TXBF_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define TXBF_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define TXBF_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define TXBF_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define TXBF_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define TXBF_GET_NDPA0_HEAD_PAGE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define TXBF_SET_NDPA0_HEAD_PAGE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define TXBF_SET_NDPA0_HEAD_PAGE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define TXBF_GET_NDPA1_HEAD_PAGE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define TXBF_SET_NDPA1_HEAD_PAGE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define TXBF_SET_NDPA1_HEAD_PAGE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define TXBF_GET_PERIOD_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define TXBF_SET_PERIOD_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define TXBF_SET_PERIOD_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RSSI_SETTING_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RSSI_SETTING_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RSSI_SETTING_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define RSSI_SETTING_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RSSI_SETTING_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RSSI_SETTING_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define RSSI_SETTING_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RSSI_SETTING_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RSSI_SETTING_GET_RSSI(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 7) -#define RSSI_SETTING_SET_RSSI(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 7, __Value) -#define RSSI_SETTING_SET_RSSI_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 7, __Value) -#define RSSI_SETTING_GET_RA_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define RSSI_SETTING_SET_RA_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RSSI_SETTING_SET_RA_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AP_REQ_TXRPT_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AP_REQ_TXRPT_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AP_REQ_TXRPT_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AP_REQ_TXRPT_GET_STA1_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define AP_REQ_TXRPT_SET_STA1_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AP_REQ_TXRPT_GET_STA2_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define AP_REQ_TXRPT_SET_STA2_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1) -#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value) -#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value) -#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 25, 1) -#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 25, 1, __Value) -#define AP_REQ_TXRPT_SET_RTY_CNT_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 25, 1, __Value) -#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define INIT_RATE_COLLECTION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define INIT_RATE_COLLECTION_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define INIT_RATE_COLLECTION_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define INIT_RATE_COLLECTION_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define INIT_RATE_COLLECTION_GET_STA1_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define INIT_RATE_COLLECTION_SET_STA1_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA1_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA2_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define INIT_RATE_COLLECTION_SET_STA2_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA2_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA3_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define INIT_RATE_COLLECTION_SET_STA3_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA3_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA4_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define INIT_RATE_COLLECTION_SET_STA4_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA4_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA5_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define INIT_RATE_COLLECTION_SET_STA5_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA5_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA6_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define INIT_RATE_COLLECTION_SET_STA6_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA6_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA7_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define INIT_RATE_COLLECTION_SET_STA7_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define INIT_RATE_COLLECTION_SET_STA7_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define IQK_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define IQK_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define IQK_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define IQK_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define IQK_OFFLOAD_GET_CHANNEL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define IQK_OFFLOAD_SET_CHANNEL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define IQK_OFFLOAD_SET_CHANNEL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define IQK_OFFLOAD_GET_BWBAND(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define IQK_OFFLOAD_SET_BWBAND(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define IQK_OFFLOAD_SET_BWBAND_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define IQK_OFFLOAD_GET_EXTPALNA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define IQK_OFFLOAD_SET_EXTPALNA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define IQK_OFFLOAD_SET_EXTPALNA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define MACID_CFG_3SS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define MACID_CFG_3SS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_3SS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_3SS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define MACID_CFG_3SS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_3SS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_3SS_GET_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define MACID_CFG_3SS_SET_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_3SS_SET_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_3SS_GET_RATE_MASK_39_32(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define MACID_CFG_3SS_SET_RATE_MASK_39_32(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_3SS_SET_RATE_MASK_39_32_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_3SS_GET_RATE_MASK_47_40(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define MACID_CFG_3SS_SET_RATE_MASK_47_40(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define MACID_CFG_3SS_SET_RATE_MASK_47_40_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RA_PARA_ADJUST_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define RA_PARA_ADJUST_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define RA_PARA_ADJUST_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RA_PARA_ADJUST_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define RA_PARA_ADJUST_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define RA_PARA_ADJUST_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RA_PARA_ADJUST_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define RA_PARA_ADJUST_SET_PARAMETER_INDEX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define RA_PARA_ADJUST_GET_RATE_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define RA_PARA_ADJUST_SET_RATE_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RA_PARA_ADJUST_SET_RATE_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define RA_PARA_ADJUST_GET_VALUE_BYTE0(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define RA_PARA_ADJUST_SET_VALUE_BYTE0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RA_PARA_ADJUST_SET_VALUE_BYTE0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define RA_PARA_ADJUST_GET_VALUE_BYTE1(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define RA_PARA_ADJUST_SET_VALUE_BYTE1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define RA_PARA_ADJUST_SET_VALUE_BYTE1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define WWLAN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define WWLAN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define WWLAN_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define WWLAN_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define WWLAN_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define WWLAN_GET_FUNC_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define WWLAN_SET_FUNC_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define WWLAN_SET_FUNC_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define WWLAN_GET_PATTERM_MAT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define WWLAN_SET_PATTERM_MAT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define WWLAN_SET_PATTERM_MAT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define WWLAN_GET_MAGIC_PKT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define WWLAN_SET_MAGIC_PKT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define WWLAN_SET_MAGIC_PKT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define WWLAN_GET_UNICAST_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define WWLAN_SET_UNICAST_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define WWLAN_SET_UNICAST_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define WWLAN_GET_ALL_PKT_DROP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) -#define WWLAN_SET_ALL_PKT_DROP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) -#define WWLAN_SET_ALL_PKT_DROP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) -#define WWLAN_GET_GPIO_ACTIVE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1) -#define WWLAN_SET_GPIO_ACTIVE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value) -#define WWLAN_SET_GPIO_ACTIVE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value) -#define WWLAN_GET_REKEY_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1) -#define WWLAN_SET_REKEY_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value) -#define WWLAN_SET_REKEY_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value) -#define WWLAN_GET_DEAUTH_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) -#define WWLAN_SET_DEAUTH_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) -#define WWLAN_SET_DEAUTH_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) -#define WWLAN_GET_GPIO_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 7) -#define WWLAN_SET_GPIO_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 7, __Value) -#define WWLAN_SET_GPIO_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 7, __Value) -#define WWLAN_GET_DATAPIN_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 23, 1) -#define WWLAN_SET_DATAPIN_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 23, 1, __Value) -#define WWLAN_SET_DATAPIN_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 23, 1, __Value) -#define WWLAN_GET_GPIO_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define WWLAN_SET_GPIO_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define WWLAN_SET_GPIO_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define WWLAN_GET_GPIO_PLUS_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 1) -#define WWLAN_SET_GPIO_PLUS_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 1, __Value) -#define WWLAN_SET_GPIO_PLUS_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 1, __Value) -#define WWLAN_GET_GPIO_PULSE_COUNT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 1, 7) -#define WWLAN_SET_GPIO_PULSE_COUNT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 1, 7, __Value) -#define WWLAN_SET_GPIO_PULSE_COUNT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 1, 7, __Value) -#define WWLAN_GET_DISABLE_UPHY(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 1) -#define WWLAN_SET_DISABLE_UPHY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 1, __Value) -#define WWLAN_SET_DISABLE_UPHY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 1, __Value) -#define WWLAN_GET_HST2DEV_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 9, 1) -#define WWLAN_SET_HST2DEV_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 9, 1, __Value) -#define WWLAN_SET_HST2DEV_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 9, 1, __Value) -#define WWLAN_GET_GPIO_DURATION_MS(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 10, 1) -#define WWLAN_SET_GPIO_DURATION_MS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 10, 1, __Value) -#define WWLAN_SET_GPIO_DURATION_MS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define REMOTE_WAKE_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define REMOTE_WAKE_CTRL_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define REMOTE_WAKE_CTRL_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define REMOTE_WAKE_CTRL_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) -#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_ARP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) -#define REMOTE_WAKE_CTRL_SET_ARP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_ARP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NDP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) -#define REMOTE_WAKE_CTRL_SET_NDP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_NDP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_GTK_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) -#define REMOTE_WAKE_CTRL_SET_GTK_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_GTK_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) -#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) -#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_FW_UNICAST_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 1) -#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 17, 1) -#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 17, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 17, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 18, 1) -#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 18, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 18, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1) -#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_ARP_ACTION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 1) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 29, 1) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 29, 1, __Value) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 29, 1, __Value) -#define AOAC_GLOBAL_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AOAC_GLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_GLOBAL_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_GLOBAL_INFO_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AOAC_GLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_GLOBAL_INFO_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE2_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE2_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE2_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE2_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_INFO_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE3_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE3_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE3_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE3_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define CLASS_DBG_MSG_CTRL 0X07 +#define ORIGINAL_H2C_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define ORIGINAL_H2C_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define ORIGINAL_H2C_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define ORIGINAL_H2C_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define ORIGINAL_H2C_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define ORIGINAL_H2C_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define H2C2H_LB_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define H2C2H_LB_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define H2C2H_LB_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define H2C2H_LB_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define H2C2H_LB_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define H2C2H_LB_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define H2C2H_LB_GET_SEQ(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define H2C2H_LB_SET_SEQ(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define H2C2H_LB_SET_SEQ_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define H2C2H_LB_GET_PAYLOAD1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 16) +#define H2C2H_LB_SET_PAYLOAD1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 16, value) +#define H2C2H_LB_SET_PAYLOAD1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 16, value) +#define H2C2H_LB_GET_PAYLOAD2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 32) +#define H2C2H_LB_SET_PAYLOAD2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 32, value) +#define H2C2H_LB_SET_PAYLOAD2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 32, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 17) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 17, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 17, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RSVD_PAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RSVD_PAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RSVD_PAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define RSVD_PAGE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RSVD_PAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RSVD_PAGE_GET_LOC_PROBE_RSP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define RSVD_PAGE_SET_LOC_PROBE_RSP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RSVD_PAGE_SET_LOC_PROBE_RSP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RSVD_PAGE_GET_LOC_PS_POLL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define RSVD_PAGE_SET_LOC_PS_POLL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define RSVD_PAGE_SET_LOC_PS_POLL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define RSVD_PAGE_GET_LOC_NULL_DATA(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define RSVD_PAGE_SET_LOC_NULL_DATA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define RSVD_PAGE_SET_LOC_NULL_DATA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define RSVD_PAGE_GET_LOC_QOS_NULL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define RSVD_PAGE_SET_LOC_QOS_NULL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RSVD_PAGE_SET_LOC_QOS_NULL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define RSVD_PAGE_SET_LOC_BT_QOS_NULL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define RSVD_PAGE_GET_LOC_CTS2SELF(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define RSVD_PAGE_SET_LOC_CTS2SELF(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define RSVD_PAGE_SET_LOC_CTS2SELF_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define MEDIA_STATUS_RPT_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define MEDIA_STATUS_RPT_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MEDIA_STATUS_RPT_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MEDIA_STATUS_RPT_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define MEDIA_STATUS_RPT_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MEDIA_STATUS_RPT_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MEDIA_STATUS_RPT_GET_OP_MODE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define MEDIA_STATUS_RPT_SET_OP_MODE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define MEDIA_STATUS_RPT_GET_MACID_IN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define MEDIA_STATUS_RPT_SET_MACID_IN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define MEDIA_STATUS_RPT_SET_MACID_IN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define MEDIA_STATUS_RPT_GET_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define MEDIA_STATUS_RPT_SET_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define MEDIA_STATUS_RPT_GET_MACID_END(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define MEDIA_STATUS_RPT_SET_MACID_END(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define MEDIA_STATUS_RPT_SET_MACID_END_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define KEEP_ALIVE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define KEEP_ALIVE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define KEEP_ALIVE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define KEEP_ALIVE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define KEEP_ALIVE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define KEEP_ALIVE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define KEEP_ALIVE_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define KEEP_ALIVE_SET_ENABLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define KEEP_ALIVE_SET_ENABLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define KEEP_ALIVE_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define KEEP_ALIVE_GET_PKT_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define KEEP_ALIVE_SET_PKT_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define KEEP_ALIVE_SET_PKT_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define DISCONNECT_DECISION_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define DISCONNECT_DECISION_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define DISCONNECT_DECISION_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define DISCONNECT_DECISION_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define DISCONNECT_DECISION_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define DISCONNECT_DECISION_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define DISCONNECT_DECISION_GET_ENABLE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define DISCONNECT_DECISION_SET_ENABLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define DISCONNECT_DECISION_SET_ENABLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN_NO_CLR(h2c_pkt, \ + value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define DISCONNECT_DECISION_GET_DISCONNECT_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define DISCONNECT_DECISION_SET_DISCONNECT_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define DISCONNECT_DECISION_SET_DISCONNECT_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD_NO_CLR(h2c_pkt, \ + value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define DISCONNECT_DECISION_SET_TRY_PKT_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT_NO_CLR(h2c_pkt, \ + value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AP_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AP_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AP_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AP_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AP_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AP_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AP_OFFLOAD_GET_ON(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define AP_OFFLOAD_SET_ON(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define AP_OFFLOAD_SET_ON_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define AP_OFFLOAD_GET_LINKED(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define AP_OFFLOAD_SET_LINKED(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define AP_OFFLOAD_SET_LINKED_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define AP_OFFLOAD_GET_EN_AUTO_WAKE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define AP_OFFLOAD_SET_EN_AUTO_WAKE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define AP_OFFLOAD_SET_EN_AUTO_WAKE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define AP_OFFLOAD_GET_WAKE_FLAG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1) +#define AP_OFFLOAD_SET_WAKE_FLAG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value) +#define AP_OFFLOAD_SET_WAKE_FLAG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_ROOT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 1) +#define AP_OFFLOAD_SET_HIDDEN_ROOT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 1, value) +#define AP_OFFLOAD_SET_HIDDEN_ROOT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 17, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 17, 1, value) +#define AP_OFFLOAD_SET_HIDDEN_VAP1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 17, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 18, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 1, value) +#define AP_OFFLOAD_SET_HIDDEN_VAP2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP3(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 19, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 19, 1, value) +#define AP_OFFLOAD_SET_HIDDEN_VAP3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 19, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP4(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 20, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 1, value) +#define AP_OFFLOAD_SET_HIDDEN_VAP4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 1, value) +#define AP_OFFLOAD_GET_DENYANY_ROOT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1) +#define AP_OFFLOAD_SET_DENYANY_ROOT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value) +#define AP_OFFLOAD_SET_DENYANY_ROOT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 25, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 25, 1, value) +#define AP_OFFLOAD_SET_DENYANY_VAP1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 25, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 26, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 26, 1, value) +#define AP_OFFLOAD_SET_DENYANY_VAP2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 26, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 27, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 27, 1, value) +#define AP_OFFLOAD_SET_DENYANY_VAP3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 27, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 28, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 1, value) +#define AP_OFFLOAD_SET_DENYANY_VAP4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 1, value) +#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AP_OFFLOAD_SET_WAIT_TBTT_CNT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AP_OFFLOAD_GET_WAKE_TIMEOUT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define AP_OFFLOAD_SET_WAKE_TIMEOUT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AP_OFFLOAD_SET_WAKE_TIMEOUT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AP_OFFLOAD_GET_LEN_IV_PAIR(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define AP_OFFLOAD_SET_LEN_IV_PAIR(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AP_OFFLOAD_SET_LEN_IV_PAIR_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AP_OFFLOAD_GET_LEN_IV_GRP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define AP_OFFLOAD_SET_LEN_IV_GRP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define AP_OFFLOAD_SET_LEN_IV_GRP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define BCN_RSVDPAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define BCN_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define BCN_RSVDPAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define BCN_RSVDPAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define BCN_RSVDPAGE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define BCN_RSVDPAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define BCN_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define BCN_RSVDPAGE_SET_LOC_ROOT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define BCN_RSVDPAGE_SET_LOC_VAP1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define BCN_RSVDPAGE_SET_LOC_VAP2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define BCN_RSVDPAGE_SET_LOC_VAP3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define BCN_RSVDPAGE_SET_LOC_VAP4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PROBE_RSP_RSVDPAGE_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define PROBE_RSP_RSVDPAGE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PROBE_RSP_RSVDPAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define SINGLE_CHANNELSWITCH_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define SINGLE_CHANNELSWITCH_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define SINGLE_CHANNELSWITCH_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_GET_CHANNEL_NUM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_GET_BW(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 2) +#define SINGLE_CHANNELSWITCH_SET_BW(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 2, value) +#define SINGLE_CHANNELSWITCH_SET_BW_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 2, value) +#define SINGLE_CHANNELSWITCH_GET_BW40SC(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 18, 3) +#define SINGLE_CHANNELSWITCH_SET_BW40SC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 3, value) +#define SINGLE_CHANNELSWITCH_SET_BW40SC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 3, value) +#define SINGLE_CHANNELSWITCH_GET_BW80SC(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 21, 3) +#define SINGLE_CHANNELSWITCH_SET_BW80SC(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 21, 3, value) +#define SINGLE_CHANNELSWITCH_SET_BW80SC_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 21, 3, value) +#define SINGLE_CHANNELSWITCH_GET_RFE_TYPE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 4) +#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 4, value) +#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 4, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define SINGLE_CHANNELSWITCH_V2_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_V2_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CENTRAL_CH(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_V2_GET_PRIMARY_CH_IDX(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4) +#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value) +#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value) +#define SINGLE_CHANNELSWITCH_V2_GET_BW(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 20, 4) +#define SINGLE_CHANNELSWITCH_V2_SET_BW(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 4, value) +#define SINGLE_CHANNELSWITCH_V2_SET_BW_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 4, value) +#define SET_PWR_MODE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define SET_PWR_MODE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SET_PWR_MODE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SET_PWR_MODE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define SET_PWR_MODE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SET_PWR_MODE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SET_PWR_MODE_GET_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7) +#define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value) +#define SET_PWR_MODE_SET_MODE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value) +#define SET_PWR_MODE_GET_CLK_REQUEST(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1) +#define SET_PWR_MODE_SET_CLK_REQUEST(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value) +#define SET_PWR_MODE_SET_CLK_REQUEST_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value) +#define SET_PWR_MODE_GET_RLBM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4) +#define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value) +#define SET_PWR_MODE_SET_RLBM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value) +#define SET_PWR_MODE_GET_SMART_PS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 20, 4) +#define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 4, value) +#define SET_PWR_MODE_SET_SMART_PS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 4, value) +#define SET_PWR_MODE_GET_AWAKE_INTERVAL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define SET_PWR_MODE_SET_AWAKE_INTERVAL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 1) +#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 1, value) +#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 1, value) +#define SET_PWR_MODE_GET_BCN_EARLY_RPT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 2, 1) +#define SET_PWR_MODE_SET_BCN_EARLY_RPT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 2, 1, value) +#define SET_PWR_MODE_SET_BCN_EARLY_RPT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 2, 1, value) +#define SET_PWR_MODE_GET_PORT_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 5, 3) +#define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 5, 3, value) +#define SET_PWR_MODE_SET_PORT_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 5, 3, value) +#define SET_PWR_MODE_GET_PWR_STATE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 1) +#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 1, value) +#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 1, value) +#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 17, 1) +#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 17, 1, value) +#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 17, 1, value) +#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 18, 1) +#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 18, 1, value) +#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 18, 1, value) +#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 19, 1) +#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 19, 1, value) +#define SET_PWR_MODE_SET_PROTECT_BCN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 19, 1, value) +#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 20, 1) +#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 20, 1, value) +#define SET_PWR_MODE_SET_SILENCE_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 20, 1, value) +#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 21, 1) +#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 21, 1, value) +#define SET_PWR_MODE_SET_FAST_BT_CONNECT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 21, 1, value) +#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 22, 1) +#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 22, 1, value) +#define SET_PWR_MODE_SET_TWO_ANTENNA_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 22, 1, value) +#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 1) +#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 1, value) +#define SET_PWR_MODE_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 1, value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 25, 3) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 25, 3, value) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 25, 3, value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 28, 4) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 28, 4, value) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 28, 4, value) +#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define PS_TUNING_PARA_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7) +#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_SET_BCN_TO_LIMIT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1) +#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_SET_DTIM_TIME_OUT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_GET_PS_TIME_OUT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4) +#define PS_TUNING_PARA_SET_PS_TIME_OUT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value) +#define PS_TUNING_PARA_SET_PS_TIME_OUT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value) +#define PS_TUNING_PARA_GET_ADOPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define PS_TUNING_PARA_SET_ADOPT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define PS_TUNING_PARA_SET_ADOPT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define PS_TUNING_PARA_II_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define PS_TUNING_PARA_II_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_II_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_II_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define PS_TUNING_PARA_II_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_II_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7) +#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_II_GET_ADOPT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1) +#define PS_TUNING_PARA_II_SET_ADOPT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_II_SET_ADOPT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define PS_LPS_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define PS_LPS_PARA_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_LPS_PARA_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_LPS_PARA_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define PS_LPS_PARA_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_LPS_PARA_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_LPS_PARA_GET_LPS_CONTROL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define PS_LPS_PARA_SET_LPS_CONTROL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define PS_LPS_PARA_SET_LPS_CONTROL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define P2P_PS_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define P2P_PS_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define P2P_PS_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define P2P_PS_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define P2P_PS_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define P2P_PS_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define P2P_PS_OFFLOAD_GET_ROLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define P2P_PS_OFFLOAD_SET_ROLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define P2P_PS_OFFLOAD_SET_ROLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define P2P_PS_OFFLOAD_GET_NOA0_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define P2P_PS_OFFLOAD_SET_NOA0_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define P2P_PS_OFFLOAD_SET_NOA0_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define P2P_PS_OFFLOAD_GET_NOA1_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1) +#define P2P_PS_OFFLOAD_SET_NOA1_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value) +#define P2P_PS_OFFLOAD_SET_NOA1_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value) +#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1) +#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value) +#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value) +#define P2P_PS_OFFLOAD_GET_DISCOVERY(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1) +#define P2P_PS_OFFLOAD_SET_DISCOVERY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value) +#define P2P_PS_OFFLOAD_SET_DISCOVERY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value) +#define PS_SCAN_EN_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define PS_SCAN_EN_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_SCAN_EN_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define PS_SCAN_EN_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define PS_SCAN_EN_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_SCAN_EN_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define PS_SCAN_EN_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define PS_SCAN_EN_SET_ENABLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define PS_SCAN_EN_SET_ENABLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define SAP_PS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define SAP_PS_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SAP_PS_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define SAP_PS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define SAP_PS_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SAP_PS_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define SAP_PS_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define SAP_PS_SET_ENABLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define SAP_PS_SET_ENABLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define SAP_PS_GET_EN_PS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define SAP_PS_SET_EN_PS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define SAP_PS_SET_EN_PS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define SAP_PS_GET_EN_LP_RX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define SAP_PS_SET_EN_LP_RX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define SAP_PS_SET_EN_LP_RX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define SAP_PS_GET_MANUAL_32K(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define SAP_PS_SET_MANUAL_32K(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define SAP_PS_SET_MANUAL_32K_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define SAP_PS_GET_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define SAP_PS_SET_DURATION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define SAP_PS_SET_DURATION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define INACTIVE_PS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define INACTIVE_PS_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define INACTIVE_PS_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define INACTIVE_PS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define INACTIVE_PS_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define INACTIVE_PS_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define INACTIVE_PS_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define INACTIVE_PS_SET_ENABLE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define INACTIVE_PS_SET_ENABLE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define INACTIVE_PS_SET_IGNORE_PS_CONDITION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define INACTIVE_PS_GET_FREQUENCY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define INACTIVE_PS_SET_FREQUENCY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define INACTIVE_PS_SET_FREQUENCY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define INACTIVE_PS_GET_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define INACTIVE_PS_SET_DURATION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define INACTIVE_PS_SET_DURATION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define MACID_CFG_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define MACID_CFG_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define MACID_CFG_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define MACID_CFG_SET_MAC_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_SET_MAC_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_GET_RATE_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 5) +#define MACID_CFG_SET_RATE_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 5, value) +#define MACID_CFG_SET_RATE_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 5, value) +#define MACID_CFG_GET_INIT_RATE_LV(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 21, 2) +#define MACID_CFG_SET_INIT_RATE_LV(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 21, 2, value) +#define MACID_CFG_SET_INIT_RATE_LV_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 21, 2, value) +#define MACID_CFG_GET_SGI(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 23, 1) +#define MACID_CFG_SET_SGI(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 23, 1, value) +#define MACID_CFG_SET_SGI_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 23, 1, value) +#define MACID_CFG_GET_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 2) +#define MACID_CFG_SET_BW(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 2, value) +#define MACID_CFG_SET_BW_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 2, value) +#define MACID_CFG_GET_LDPC_CAP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 26, 1) +#define MACID_CFG_SET_LDPC_CAP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 26, 1, value) +#define MACID_CFG_SET_LDPC_CAP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 26, 1, value) +#define MACID_CFG_GET_NO_UPDATE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 27, 1) +#define MACID_CFG_SET_NO_UPDATE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 27, 1, value) +#define MACID_CFG_SET_NO_UPDATE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 27, 1, value) +#define MACID_CFG_GET_WHT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 28, 2) +#define MACID_CFG_SET_WHT_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 2, value) +#define MACID_CFG_SET_WHT_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 2, value) +#define MACID_CFG_GET_DISPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 30, 1) +#define MACID_CFG_SET_DISPT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 30, 1, value) +#define MACID_CFG_SET_DISPT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 30, 1, value) +#define MACID_CFG_GET_DISRA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 31, 1) +#define MACID_CFG_SET_DISRA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 31, 1, value) +#define MACID_CFG_SET_DISRA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 31, 1, value) +#define MACID_CFG_GET_RATE_MASK7_0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define MACID_CFG_SET_RATE_MASK7_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_SET_RATE_MASK7_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_GET_RATE_MASK15_8(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define MACID_CFG_SET_RATE_MASK15_8(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define MACID_CFG_SET_RATE_MASK15_8_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define MACID_CFG_GET_RATE_MASK23_16(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define MACID_CFG_SET_RATE_MASK23_16(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define MACID_CFG_SET_RATE_MASK23_16_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define MACID_CFG_GET_RATE_MASK31_24(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define MACID_CFG_SET_RATE_MASK31_24(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define MACID_CFG_SET_RATE_MASK31_24_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define TXBF_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define TXBF_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define TXBF_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define TXBF_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define TXBF_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define TXBF_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define TXBF_GET_NDPA0_HEAD_PAGE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define TXBF_SET_NDPA0_HEAD_PAGE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define TXBF_SET_NDPA0_HEAD_PAGE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define TXBF_GET_NDPA1_HEAD_PAGE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define TXBF_SET_NDPA1_HEAD_PAGE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define TXBF_SET_NDPA1_HEAD_PAGE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define TXBF_GET_PERIOD_0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define TXBF_SET_PERIOD_0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define TXBF_SET_PERIOD_0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define RSSI_SETTING_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define RSSI_SETTING_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RSSI_SETTING_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RSSI_SETTING_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define RSSI_SETTING_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RSSI_SETTING_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RSSI_SETTING_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define RSSI_SETTING_SET_MAC_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RSSI_SETTING_SET_MAC_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RSSI_SETTING_GET_RSSI(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 7) +#define RSSI_SETTING_SET_RSSI(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 7, value) +#define RSSI_SETTING_SET_RSSI_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 7, value) +#define RSSI_SETTING_GET_RA_INFO(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define RSSI_SETTING_SET_RA_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RSSI_SETTING_SET_RA_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AP_REQ_TXRPT_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AP_REQ_TXRPT_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AP_REQ_TXRPT_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AP_REQ_TXRPT_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AP_REQ_TXRPT_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AP_REQ_TXRPT_GET_STA1_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define AP_REQ_TXRPT_SET_STA1_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AP_REQ_TXRPT_GET_STA2_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define AP_REQ_TXRPT_SET_STA2_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1) +#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value) +#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value) +#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 25, 1) +#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 25, 1, value) +#define AP_REQ_TXRPT_SET_RTY_CNT_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 25, 1, value) +#define INIT_RATE_COLLECTION_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define INIT_RATE_COLLECTION_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define INIT_RATE_COLLECTION_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define INIT_RATE_COLLECTION_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define INIT_RATE_COLLECTION_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define INIT_RATE_COLLECTION_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define INIT_RATE_COLLECTION_GET_STA1_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA1_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define INIT_RATE_COLLECTION_SET_STA1_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define INIT_RATE_COLLECTION_GET_STA2_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA2_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define INIT_RATE_COLLECTION_SET_STA2_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define INIT_RATE_COLLECTION_GET_STA3_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA3_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define INIT_RATE_COLLECTION_SET_STA3_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define INIT_RATE_COLLECTION_GET_STA4_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define INIT_RATE_COLLECTION_SET_STA4_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define INIT_RATE_COLLECTION_SET_STA4_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define INIT_RATE_COLLECTION_GET_STA5_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA5_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define INIT_RATE_COLLECTION_SET_STA5_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define INIT_RATE_COLLECTION_GET_STA6_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA6_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define INIT_RATE_COLLECTION_SET_STA6_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define INIT_RATE_COLLECTION_GET_STA7_MACID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA7_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define INIT_RATE_COLLECTION_SET_STA7_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define IQK_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define IQK_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define IQK_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define IQK_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define IQK_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define IQK_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define IQK_OFFLOAD_GET_CHANNEL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define IQK_OFFLOAD_SET_CHANNEL(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define IQK_OFFLOAD_SET_CHANNEL_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define IQK_OFFLOAD_GET_BWBAND(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define IQK_OFFLOAD_SET_BWBAND(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define IQK_OFFLOAD_SET_BWBAND_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define IQK_OFFLOAD_GET_EXTPALNA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define IQK_OFFLOAD_SET_EXTPALNA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define IQK_OFFLOAD_SET_EXTPALNA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define MACID_CFG_3SS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define MACID_CFG_3SS_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_3SS_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_3SS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define MACID_CFG_3SS_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_3SS_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_3SS_GET_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define MACID_CFG_3SS_SET_MACID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_3SS_SET_MACID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_3SS_GET_RATE_MASK_39_32(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_3SS_GET_RATE_MASK_47_40(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define RA_PARA_ADJUST_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define RA_PARA_ADJUST_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RA_PARA_ADJUST_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define RA_PARA_ADJUST_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define RA_PARA_ADJUST_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RA_PARA_ADJUST_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define RA_PARA_ADJUST_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define RA_PARA_ADJUST_SET_MAC_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RA_PARA_ADJUST_SET_MAC_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define RA_PARA_ADJUST_SET_PARAMETER_INDEX_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define RA_PARA_ADJUST_GET_RATE_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define RA_PARA_ADJUST_SET_RATE_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define RA_PARA_ADJUST_SET_RATE_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE0(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE0(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RA_PARA_ADJUST_SET_VALUE_BYTE0_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE1(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE1(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define RA_PARA_ADJUST_SET_VALUE_BYTE1_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define WWLAN_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define WWLAN_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define WWLAN_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define WWLAN_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define WWLAN_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define WWLAN_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define WWLAN_GET_FUNC_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define WWLAN_SET_FUNC_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define WWLAN_SET_FUNC_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define WWLAN_GET_PATTERM_MAT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define WWLAN_SET_PATTERM_MAT_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define WWLAN_SET_PATTERM_MAT_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define WWLAN_GET_MAGIC_PKT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define WWLAN_SET_MAGIC_PKT_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define WWLAN_SET_MAGIC_PKT_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define WWLAN_GET_UNICAST_WAKEUP_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define WWLAN_SET_UNICAST_WAKEUP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define WWLAN_SET_UNICAST_WAKEUP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define WWLAN_GET_ALL_PKT_DROP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1) +#define WWLAN_SET_ALL_PKT_DROP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value) +#define WWLAN_SET_ALL_PKT_DROP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value) +#define WWLAN_GET_GPIO_ACTIVE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1) +#define WWLAN_SET_GPIO_ACTIVE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value) +#define WWLAN_SET_GPIO_ACTIVE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value) +#define WWLAN_GET_REKEY_WAKEUP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1) +#define WWLAN_SET_REKEY_WAKEUP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value) +#define WWLAN_SET_REKEY_WAKEUP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value) +#define WWLAN_GET_DEAUTH_WAKEUP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1) +#define WWLAN_SET_DEAUTH_WAKEUP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value) +#define WWLAN_SET_DEAUTH_WAKEUP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value) +#define WWLAN_GET_GPIO_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 7) +#define WWLAN_SET_GPIO_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 7, value) +#define WWLAN_SET_GPIO_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 7, value) +#define WWLAN_GET_DATAPIN_WAKEUP_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 23, 1) +#define WWLAN_SET_DATAPIN_WAKEUP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 23, 1, value) +#define WWLAN_SET_DATAPIN_WAKEUP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 23, 1, value) +#define WWLAN_GET_GPIO_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define WWLAN_SET_GPIO_DURATION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define WWLAN_SET_GPIO_DURATION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define WWLAN_GET_GPIO_PLUS_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 1) +#define WWLAN_SET_GPIO_PLUS_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 1, value) +#define WWLAN_SET_GPIO_PLUS_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 1, value) +#define WWLAN_GET_GPIO_PULSE_COUNT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 1, 7) +#define WWLAN_SET_GPIO_PULSE_COUNT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 1, 7, value) +#define WWLAN_SET_GPIO_PULSE_COUNT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 1, 7, value) +#define WWLAN_GET_DISABLE_UPHY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 1) +#define WWLAN_SET_DISABLE_UPHY(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 1, value) +#define WWLAN_SET_DISABLE_UPHY_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 1, value) +#define WWLAN_GET_HST2DEV_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 9, 1) +#define WWLAN_SET_HST2DEV_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 9, 1, value) +#define WWLAN_SET_HST2DEV_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 9, 1, value) +#define WWLAN_GET_GPIO_DURATION_MS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 10, 1) +#define WWLAN_SET_GPIO_DURATION_MS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 10, 1, value) +#define WWLAN_SET_GPIO_DURATION_MS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 10, 1, value) +#define REMOTE_WAKE_CTRL_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define REMOTE_WAKE_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define REMOTE_WAKE_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define REMOTE_WAKE_CTRL_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define REMOTE_WAKE_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define REMOTE_WAKE_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define REMOTE_WAKE_CTRL_GET_ARP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value) +#define REMOTE_WAKE_CTRL_SET_ARP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value) +#define REMOTE_WAKE_CTRL_GET_NDP_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1) +#define REMOTE_WAKE_CTRL_SET_NDP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value) +#define REMOTE_WAKE_CTRL_SET_NDP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value) +#define REMOTE_WAKE_CTRL_GET_GTK_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1) +#define REMOTE_WAKE_CTRL_SET_GTK_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value) +#define REMOTE_WAKE_CTRL_SET_GTK_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value) +#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1) +#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value) +#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1) +#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value) +#define REMOTE_WAKE_CTRL_SET_FW_UNICAST_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value) +#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 1) +#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 1, value) +#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 1, value) +#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 17, 1) +#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 17, 1, value) +#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 17, 1, value) +#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 18, 1) +#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 1, value) +#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 1, value) +#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value) +#define REMOTE_WAKE_CTRL_SET_ARP_ACTION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 28, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 1, value) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 29, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 29, 1, value) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 29, 1, value) +#define AOAC_GLOBAL_INFO_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AOAC_GLOBAL_INFO_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_GLOBAL_INFO_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_GLOBAL_INFO_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AOAC_GLOBAL_INFO_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_GLOBAL_INFO_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define AOAC_RSVD_PAGE2_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE2_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE2_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE2_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE2_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE2_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value) +#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value) +#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_INFO_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE3_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE3_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE3_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE3_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE3_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE3_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(h2c_pkt) \ + GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value) +#define DBG_MSG_CTRL_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5) +#define DBG_MSG_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value) +#define DBG_MSG_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value) +#define DBG_MSG_CTRL_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3) +#define DBG_MSG_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value) +#define DBG_MSG_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value) +#define DBG_MSG_CTRL_GET_FUN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1) +#define DBG_MSG_CTRL_SET_FUN_EN(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value) +#define DBG_MSG_CTRL_SET_FUN_EN_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value) +#define DBG_MSG_CTRL_GET_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 4) +#define DBG_MSG_CTRL_SET_MODE(h2c_pkt, value) \ + SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 4, value) +#define DBG_MSG_CTRL_SET_MODE_NO_CLR(h2c_pkt, value) \ + SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 4, value) #endif diff --git a/hal/halmac/halmac_original_h2c_nic.h b/hal/halmac/halmac_original_h2c_nic.h index ede47dd..3870ff4 100644 --- a/hal/halmac/halmac_original_h2c_nic.h +++ b/hal/halmac/halmac_original_h2c_nic.h @@ -1,39 +1,57 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_ #define _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_ -#define CMD_ID_ORIGINAL_H2C 0X00 -#define CMD_ID_H2C2H_LB 0X0 -#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06 -#define CMD_ID_RSVD_PAGE 0X0 -#define CMD_ID_MEDIA_STATUS_RPT 0X01 -#define CMD_ID_KEEP_ALIVE 0X03 -#define CMD_ID_DISCONNECT_DECISION 0X04 -#define CMD_ID_AP_OFFLOAD 0X08 -#define CMD_ID_BCN_RSVDPAGE 0X09 -#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A -#define CMD_ID_SET_PWR_MODE 0X00 -#define CMD_ID_PS_TUNING_PARA 0X01 -#define CMD_ID_PS_TUNING_PARA_II 0X02 -#define CMD_ID_PS_LPS_PARA 0X03 -#define CMD_ID_P2P_PS_OFFLOAD 0X04 -#define CMD_ID_PS_SCAN_EN 0X05 -#define CMD_ID_SAP_PS 0X06 -#define CMD_ID_INACTIVE_PS 0X07 -#define CMD_ID_MACID_CFG 0X00 -#define CMD_ID_TXBF 0X01 -#define CMD_ID_RSSI_SETTING 0X02 -#define CMD_ID_AP_REQ_TXRPT 0X03 -#define CMD_ID_INIT_RATE_COLLECTION 0X04 -#define CMD_ID_IQK_OFFLOAD 0X05 -#define CMD_ID_MACID_CFG_3SS 0X06 -#define CMD_ID_RA_PARA_ADJUST 0X07 -#define CMD_ID_WWLAN 0X00 -#define CMD_ID_REMOTE_WAKE_CTRL 0X01 -#define CMD_ID_AOAC_GLOBAL_INFO 0X02 -#define CMD_ID_AOAC_RSVD_PAGE 0X03 -#define CMD_ID_AOAC_RSVD_PAGE2 0X04 -#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 -#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07 -#define CMD_ID_AOAC_RSVD_PAGE3 0X08 +#define CMD_ID_ORIGINAL_H2C 0X00 +#define CMD_ID_H2C2H_LB 0X0 +#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06 +#define CMD_ID_RSVD_PAGE 0X0 +#define CMD_ID_MEDIA_STATUS_RPT 0X01 +#define CMD_ID_KEEP_ALIVE 0X03 +#define CMD_ID_DISCONNECT_DECISION 0X04 +#define CMD_ID_AP_OFFLOAD 0X08 +#define CMD_ID_BCN_RSVDPAGE 0X09 +#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A +#define CMD_ID_SINGLE_CHANNELSWITCH 0X1C +#define CMD_ID_SINGLE_CHANNELSWITCH_V2 0X1D +#define CMD_ID_SET_PWR_MODE 0X00 +#define CMD_ID_PS_TUNING_PARA 0X01 +#define CMD_ID_PS_TUNING_PARA_II 0X02 +#define CMD_ID_PS_LPS_PARA 0X03 +#define CMD_ID_P2P_PS_OFFLOAD 0X04 +#define CMD_ID_PS_SCAN_EN 0X05 +#define CMD_ID_SAP_PS 0X06 +#define CMD_ID_INACTIVE_PS 0X07 +#define CMD_ID_MACID_CFG 0X00 +#define CMD_ID_TXBF 0X01 +#define CMD_ID_RSSI_SETTING 0X02 +#define CMD_ID_AP_REQ_TXRPT 0X03 +#define CMD_ID_INIT_RATE_COLLECTION 0X04 +#define CMD_ID_IQK_OFFLOAD 0X05 +#define CMD_ID_MACID_CFG_3SS 0X06 +#define CMD_ID_RA_PARA_ADJUST 0X07 +#define CMD_ID_WWLAN 0X00 +#define CMD_ID_REMOTE_WAKE_CTRL 0X01 +#define CMD_ID_AOAC_GLOBAL_INFO 0X02 +#define CMD_ID_AOAC_RSVD_PAGE 0X03 +#define CMD_ID_AOAC_RSVD_PAGE2 0X04 +#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 +#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07 +#define CMD_ID_AOAC_RSVD_PAGE3 0X08 +#define CMD_ID_DBG_MSG_CTRL 0X1E #define CLASS_ORIGINAL_H2C 0X00 #define CLASS_H2C2H_LB 0X07 #define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04 @@ -44,6 +62,8 @@ #define CLASS_AP_OFFLOAD 0X0 #define CLASS_BCN_RSVDPAGE 0X0 #define CLASS_PROBE_RSP_RSVDPAGE 0X0 +#define CLASS_SINGLE_CHANNELSWITCH 0X0 +#define CLASS_SINGLE_CHANNELSWITCH_V2 0X0 #define CLASS_SET_PWR_MODE 0X01 #define CLASS_PS_TUNING_PARA 0X01 #define CLASS_PS_TUNING_PARA_II 0X01 @@ -68,542 +88,1056 @@ #define CLASS_D0_SCAN_OFFLOAD_INFO 0X04 #define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04 #define CLASS_AOAC_RSVD_PAGE3 0X04 -#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define ORIGINAL_H2C_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define ORIGINAL_H2C_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define H2C2H_LB_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define H2C2H_LB_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define H2C2H_LB_GET_SEQ(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define H2C2H_LB_SET_SEQ(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define H2C2H_LB_GET_PAYLOAD1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 16) -#define H2C2H_LB_SET_PAYLOAD1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 16, __Value) -#define H2C2H_LB_GET_PAYLOAD2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 32) -#define H2C2H_LB_SET_PAYLOAD2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 32, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) -#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 17) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 17, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define RSVD_PAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define RSVD_PAGE_GET_LOC_PROBE_RSP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define RSVD_PAGE_SET_LOC_PROBE_RSP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define RSVD_PAGE_GET_LOC_PS_POLL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define RSVD_PAGE_SET_LOC_PS_POLL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define RSVD_PAGE_GET_LOC_NULL_DATA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define RSVD_PAGE_SET_LOC_NULL_DATA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define RSVD_PAGE_GET_LOC_QOS_NULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define RSVD_PAGE_SET_LOC_QOS_NULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define RSVD_PAGE_GET_LOC_CTS2SELF(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define RSVD_PAGE_SET_LOC_CTS2SELF(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define MEDIA_STATUS_RPT_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define MEDIA_STATUS_RPT_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define MEDIA_STATUS_RPT_GET_OP_MODE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define MEDIA_STATUS_RPT_SET_OP_MODE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define MEDIA_STATUS_RPT_GET_MACID_IN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define MEDIA_STATUS_RPT_SET_MACID_IN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define MEDIA_STATUS_RPT_GET_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define MEDIA_STATUS_RPT_SET_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define MEDIA_STATUS_RPT_GET_MACID_END(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define MEDIA_STATUS_RPT_SET_MACID_END(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define KEEP_ALIVE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define KEEP_ALIVE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define KEEP_ALIVE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define KEEP_ALIVE_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define KEEP_ALIVE_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define KEEP_ALIVE_GET_PKT_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define KEEP_ALIVE_SET_PKT_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define DISCONNECT_DECISION_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define DISCONNECT_DECISION_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define DISCONNECT_DECISION_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define DISCONNECT_DECISION_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define DISCONNECT_DECISION_GET_DISCONNECT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define DISCONNECT_DECISION_SET_DISCONNECT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AP_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AP_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AP_OFFLOAD_GET_ON(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define AP_OFFLOAD_SET_ON(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define AP_OFFLOAD_GET_LINKED(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define AP_OFFLOAD_SET_LINKED(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define AP_OFFLOAD_GET_EN_AUTO_WAKE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define AP_OFFLOAD_SET_EN_AUTO_WAKE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define AP_OFFLOAD_GET_WAKE_FLAG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) -#define AP_OFFLOAD_SET_WAKE_FLAG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 1) -#define AP_OFFLOAD_SET_HIDDEN_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 17, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 17, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 18, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 18, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 19, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 19, 1, __Value) -#define AP_OFFLOAD_GET_HIDDEN_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 20, 1) -#define AP_OFFLOAD_SET_HIDDEN_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 20, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1) -#define AP_OFFLOAD_SET_DENYANY_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 25, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 25, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 26, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 26, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 27, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 27, 1, __Value) -#define AP_OFFLOAD_GET_DENYANY_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 1) -#define AP_OFFLOAD_SET_DENYANY_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 1, __Value) -#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AP_OFFLOAD_GET_WAKE_TIMEOUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define AP_OFFLOAD_SET_WAKE_TIMEOUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define AP_OFFLOAD_GET_LEN_IV_PAIR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define AP_OFFLOAD_SET_LEN_IV_PAIR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define AP_OFFLOAD_GET_LEN_IV_GRP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define AP_OFFLOAD_SET_LEN_IV_GRP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define BCN_RSVDPAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define BCN_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define BCN_RSVDPAGE_GET_LOC_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define BCN_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define BCN_RSVDPAGE_GET_LOC_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define BCN_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define PROBE_RSP_RSVDPAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define PROBE_RSP_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define SET_PWR_MODE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define SET_PWR_MODE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define SET_PWR_MODE_GET_MODE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) -#define SET_PWR_MODE_SET_MODE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value) -#define SET_PWR_MODE_GET_CLK_REQUEST(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) -#define SET_PWR_MODE_SET_CLK_REQUEST(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) -#define SET_PWR_MODE_GET_RLBM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 4) -#define SET_PWR_MODE_SET_RLBM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 4, __Value) -#define SET_PWR_MODE_GET_SMART_PS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 20, 4) -#define SET_PWR_MODE_SET_SMART_PS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 20, 4, __Value) -#define SET_PWR_MODE_GET_AWAKE_INTERVAL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define SET_PWR_MODE_SET_AWAKE_INTERVAL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 1) -#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 1, __Value) -#define SET_PWR_MODE_GET_BCN_EARLY_RPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 2, 1) -#define SET_PWR_MODE_SET_BCN_EARLY_RPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 2, 1, __Value) -#define SET_PWR_MODE_GET_PORT_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 5, 3) -#define SET_PWR_MODE_SET_PORT_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 5, 3, __Value) -#define SET_PWR_MODE_GET_PWR_STATE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define SET_PWR_MODE_SET_PWR_STATE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 1) -#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 1, __Value) -#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 17, 1) -#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 17, 1, __Value) -#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 18, 1) -#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 18, 1, __Value) -#define SET_PWR_MODE_GET_PROTECT_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 19, 1) -#define SET_PWR_MODE_SET_PROTECT_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 19, 1, __Value) -#define SET_PWR_MODE_GET_SILENCE_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 20, 1) -#define SET_PWR_MODE_SET_SILENCE_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 20, 1, __Value) -#define SET_PWR_MODE_GET_FAST_BT_CONNECT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 21, 1) -#define SET_PWR_MODE_SET_FAST_BT_CONNECT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 21, 1, __Value) -#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 22, 1) -#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 22, 1, __Value) -#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 1) -#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 1, __Value) -#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 25, 3) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 25, 3, __Value) -#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 28, 4) -#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 28, 4, __Value) -#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define PS_TUNING_PARA_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) -#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) -#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_GET_PS_TIME_OUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 4) -#define PS_TUNING_PARA_SET_PS_TIME_OUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 4, __Value) -#define PS_TUNING_PARA_GET_ADOPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define PS_TUNING_PARA_SET_ADOPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define PS_TUNING_PARA_II_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define PS_TUNING_PARA_II_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) -#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value) -#define PS_TUNING_PARA_II_GET_ADOPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) -#define PS_TUNING_PARA_II_SET_ADOPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) -#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define PS_LPS_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define PS_LPS_PARA_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define PS_LPS_PARA_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define PS_LPS_PARA_GET_LPS_CONTROL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define PS_LPS_PARA_SET_LPS_CONTROL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define P2P_PS_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define P2P_PS_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define P2P_PS_OFFLOAD_GET_ROLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define P2P_PS_OFFLOAD_SET_ROLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define P2P_PS_OFFLOAD_GET_NOA0_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define P2P_PS_OFFLOAD_SET_NOA0_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define P2P_PS_OFFLOAD_GET_NOA1_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) -#define P2P_PS_OFFLOAD_SET_NOA1_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) -#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1) -#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value) -#define P2P_PS_OFFLOAD_GET_DISCOVERY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1) -#define P2P_PS_OFFLOAD_SET_DISCOVERY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value) -#define PS_SCAN_EN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define PS_SCAN_EN_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define PS_SCAN_EN_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define PS_SCAN_EN_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define PS_SCAN_EN_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define SAP_PS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define SAP_PS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define SAP_PS_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define SAP_PS_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define SAP_PS_GET_EN_PS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define SAP_PS_SET_EN_PS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define SAP_PS_GET_EN_LP_RX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define SAP_PS_SET_EN_LP_RX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define SAP_PS_GET_MANUAL_32K(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define SAP_PS_SET_MANUAL_32K(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define SAP_PS_GET_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define SAP_PS_SET_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define INACTIVE_PS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define INACTIVE_PS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define INACTIVE_PS_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define INACTIVE_PS_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define INACTIVE_PS_GET_FREQUENCY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define INACTIVE_PS_SET_FREQUENCY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define INACTIVE_PS_GET_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define INACTIVE_PS_SET_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define MACID_CFG_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define MACID_CFG_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define MACID_CFG_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_GET_RATE_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 5) -#define MACID_CFG_SET_RATE_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 5, __Value) -#define MACID_CFG_GET_INIT_RATE_LV(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 21, 2) -#define MACID_CFG_SET_INIT_RATE_LV(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 21, 2, __Value) -#define MACID_CFG_GET_SGI(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 23, 1) -#define MACID_CFG_SET_SGI(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 23, 1, __Value) -#define MACID_CFG_GET_BW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 2) -#define MACID_CFG_SET_BW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 2, __Value) -#define MACID_CFG_GET_LDPC_CAP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 26, 1) -#define MACID_CFG_SET_LDPC_CAP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 26, 1, __Value) -#define MACID_CFG_GET_NO_UPDATE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 27, 1) -#define MACID_CFG_SET_NO_UPDATE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 27, 1, __Value) -#define MACID_CFG_GET_WHT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 2) -#define MACID_CFG_SET_WHT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 2, __Value) -#define MACID_CFG_GET_DISPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 30, 1) -#define MACID_CFG_SET_DISPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 30, 1, __Value) -#define MACID_CFG_GET_DISRA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 31, 1) -#define MACID_CFG_SET_DISRA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 31, 1, __Value) -#define MACID_CFG_GET_RATE_MASK7_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define MACID_CFG_SET_RATE_MASK7_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_GET_RATE_MASK15_8(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define MACID_CFG_SET_RATE_MASK15_8(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define MACID_CFG_GET_RATE_MASK23_16(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define MACID_CFG_SET_RATE_MASK23_16(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define MACID_CFG_GET_RATE_MASK31_24(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define MACID_CFG_SET_RATE_MASK31_24(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define TXBF_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define TXBF_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define TXBF_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define TXBF_GET_NDPA0_HEAD_PAGE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define TXBF_SET_NDPA0_HEAD_PAGE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define TXBF_GET_NDPA1_HEAD_PAGE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define TXBF_SET_NDPA1_HEAD_PAGE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define TXBF_GET_PERIOD_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define TXBF_SET_PERIOD_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define RSSI_SETTING_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define RSSI_SETTING_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define RSSI_SETTING_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define RSSI_SETTING_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define RSSI_SETTING_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define RSSI_SETTING_GET_RSSI(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 7) -#define RSSI_SETTING_SET_RSSI(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 7, __Value) -#define RSSI_SETTING_GET_RA_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define RSSI_SETTING_SET_RA_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AP_REQ_TXRPT_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AP_REQ_TXRPT_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AP_REQ_TXRPT_GET_STA1_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define AP_REQ_TXRPT_SET_STA1_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define AP_REQ_TXRPT_GET_STA2_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define AP_REQ_TXRPT_SET_STA2_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1) -#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value) -#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 25, 1) -#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 25, 1, __Value) -#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define INIT_RATE_COLLECTION_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define INIT_RATE_COLLECTION_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define INIT_RATE_COLLECTION_GET_STA1_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define INIT_RATE_COLLECTION_SET_STA1_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA2_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define INIT_RATE_COLLECTION_SET_STA2_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA3_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define INIT_RATE_COLLECTION_SET_STA3_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA4_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define INIT_RATE_COLLECTION_SET_STA4_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA5_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define INIT_RATE_COLLECTION_SET_STA5_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA6_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define INIT_RATE_COLLECTION_SET_STA6_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define INIT_RATE_COLLECTION_GET_STA7_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define INIT_RATE_COLLECTION_SET_STA7_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define IQK_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define IQK_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define IQK_OFFLOAD_GET_CHANNEL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define IQK_OFFLOAD_SET_CHANNEL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define IQK_OFFLOAD_GET_BWBAND(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define IQK_OFFLOAD_SET_BWBAND(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define IQK_OFFLOAD_GET_EXTPALNA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define IQK_OFFLOAD_SET_EXTPALNA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define MACID_CFG_3SS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define MACID_CFG_3SS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define MACID_CFG_3SS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define MACID_CFG_3SS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define MACID_CFG_3SS_GET_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define MACID_CFG_3SS_SET_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define MACID_CFG_3SS_GET_RATE_MASK_39_32(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define MACID_CFG_3SS_SET_RATE_MASK_39_32(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define MACID_CFG_3SS_GET_RATE_MASK_47_40(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define MACID_CFG_3SS_SET_RATE_MASK_47_40(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define RA_PARA_ADJUST_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define RA_PARA_ADJUST_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define RA_PARA_ADJUST_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define RA_PARA_ADJUST_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define RA_PARA_ADJUST_GET_RATE_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define RA_PARA_ADJUST_SET_RATE_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define RA_PARA_ADJUST_GET_VALUE_BYTE0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define RA_PARA_ADJUST_SET_VALUE_BYTE0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define RA_PARA_ADJUST_GET_VALUE_BYTE1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define RA_PARA_ADJUST_SET_VALUE_BYTE1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define WWLAN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define WWLAN_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define WWLAN_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define WWLAN_GET_FUNC_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define WWLAN_SET_FUNC_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define WWLAN_GET_PATTERM_MAT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define WWLAN_SET_PATTERM_MAT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define WWLAN_GET_MAGIC_PKT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define WWLAN_SET_MAGIC_PKT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define WWLAN_GET_UNICAST_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define WWLAN_SET_UNICAST_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define WWLAN_GET_ALL_PKT_DROP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) -#define WWLAN_SET_ALL_PKT_DROP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) -#define WWLAN_GET_GPIO_ACTIVE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1) -#define WWLAN_SET_GPIO_ACTIVE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value) -#define WWLAN_GET_REKEY_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1) -#define WWLAN_SET_REKEY_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value) -#define WWLAN_GET_DEAUTH_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) -#define WWLAN_SET_DEAUTH_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) -#define WWLAN_GET_GPIO_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 7) -#define WWLAN_SET_GPIO_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 7, __Value) -#define WWLAN_GET_DATAPIN_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 23, 1) -#define WWLAN_SET_DATAPIN_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 23, 1, __Value) -#define WWLAN_GET_GPIO_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define WWLAN_SET_GPIO_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define WWLAN_GET_GPIO_PLUS_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 1) -#define WWLAN_SET_GPIO_PLUS_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 1, __Value) -#define WWLAN_GET_GPIO_PULSE_COUNT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 1, 7) -#define WWLAN_SET_GPIO_PULSE_COUNT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 1, 7, __Value) -#define WWLAN_GET_DISABLE_UPHY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 1) -#define WWLAN_SET_DISABLE_UPHY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 1, __Value) -#define WWLAN_GET_HST2DEV_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 9, 1) -#define WWLAN_SET_HST2DEV_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 9, 1, __Value) -#define WWLAN_GET_GPIO_DURATION_MS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 10, 1) -#define WWLAN_SET_GPIO_DURATION_MS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define REMOTE_WAKE_CTRL_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define REMOTE_WAKE_CTRL_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) -#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_ARP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) -#define REMOTE_WAKE_CTRL_SET_ARP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NDP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) -#define REMOTE_WAKE_CTRL_SET_NDP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_GTK_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) -#define REMOTE_WAKE_CTRL_SET_GTK_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) -#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1) -#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) -#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 1) -#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 17, 1) -#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 17, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 18, 1) -#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 18, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1) -#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 1) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 1, __Value) -#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 29, 1) -#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 29, 1, __Value) -#define AOAC_GLOBAL_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AOAC_GLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_GLOBAL_INFO_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AOAC_GLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE2_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE2_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) -#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) -#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) -#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) -#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) -#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) -#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) -#define AOAC_RSVD_PAGE3_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) -#define AOAC_RSVD_PAGE3_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) -#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) -#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) -#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) -#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define CLASS_DBG_MSG_CTRL 0X07 +#define ORIGINAL_H2C_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define ORIGINAL_H2C_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define ORIGINAL_H2C_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define ORIGINAL_H2C_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define H2C2H_LB_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define H2C2H_LB_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define H2C2H_LB_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define H2C2H_LB_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define H2C2H_LB_GET_SEQ(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define H2C2H_LB_SET_SEQ(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define H2C2H_LB_GET_PAYLOAD1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 16) +#define H2C2H_LB_SET_PAYLOAD1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 16, value) +#define H2C2H_LB_GET_PAYLOAD2(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 32) +#define H2C2H_LB_SET_PAYLOAD2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 32, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 17) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 17, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define RSVD_PAGE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define RSVD_PAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define RSVD_PAGE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define RSVD_PAGE_GET_LOC_PROBE_RSP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define RSVD_PAGE_SET_LOC_PROBE_RSP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define RSVD_PAGE_GET_LOC_PS_POLL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define RSVD_PAGE_SET_LOC_PS_POLL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define RSVD_PAGE_GET_LOC_NULL_DATA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define RSVD_PAGE_SET_LOC_NULL_DATA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define RSVD_PAGE_GET_LOC_QOS_NULL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define RSVD_PAGE_SET_LOC_QOS_NULL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define RSVD_PAGE_GET_LOC_CTS2SELF(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define RSVD_PAGE_SET_LOC_CTS2SELF(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define MEDIA_STATUS_RPT_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define MEDIA_STATUS_RPT_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define MEDIA_STATUS_RPT_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define MEDIA_STATUS_RPT_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define MEDIA_STATUS_RPT_GET_OP_MODE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define MEDIA_STATUS_RPT_GET_MACID_IN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define MEDIA_STATUS_RPT_SET_MACID_IN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define MEDIA_STATUS_RPT_GET_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define MEDIA_STATUS_RPT_GET_MACID_END(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define MEDIA_STATUS_RPT_SET_MACID_END(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define KEEP_ALIVE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define KEEP_ALIVE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define KEEP_ALIVE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define KEEP_ALIVE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define KEEP_ALIVE_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define KEEP_ALIVE_SET_ENABLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define KEEP_ALIVE_GET_PKT_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define KEEP_ALIVE_SET_PKT_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define DISCONNECT_DECISION_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define DISCONNECT_DECISION_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define DISCONNECT_DECISION_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define DISCONNECT_DECISION_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define DISCONNECT_DECISION_GET_ENABLE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define DISCONNECT_DECISION_SET_ENABLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define DISCONNECT_DECISION_GET_DISCONNECT_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define DISCONNECT_DECISION_SET_DISCONNECT_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define AP_OFFLOAD_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AP_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AP_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AP_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AP_OFFLOAD_GET_ON(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define AP_OFFLOAD_SET_ON(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define AP_OFFLOAD_GET_LINKED(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define AP_OFFLOAD_SET_LINKED(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define AP_OFFLOAD_GET_EN_AUTO_WAKE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define AP_OFFLOAD_SET_EN_AUTO_WAKE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define AP_OFFLOAD_GET_WAKE_FLAG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1) +#define AP_OFFLOAD_SET_WAKE_FLAG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_ROOT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 1) +#define AP_OFFLOAD_SET_HIDDEN_ROOT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 17, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 17, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 19, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 19, 1, value) +#define AP_OFFLOAD_GET_HIDDEN_VAP4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 1, value) +#define AP_OFFLOAD_GET_DENYANY_ROOT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1) +#define AP_OFFLOAD_SET_DENYANY_ROOT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 25, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 25, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 26, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 26, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 27, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 27, 1, value) +#define AP_OFFLOAD_GET_DENYANY_VAP4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 1, value) +#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define AP_OFFLOAD_GET_WAKE_TIMEOUT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define AP_OFFLOAD_SET_WAKE_TIMEOUT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define AP_OFFLOAD_GET_LEN_IV_PAIR(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define AP_OFFLOAD_SET_LEN_IV_PAIR(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define AP_OFFLOAD_GET_LEN_IV_GRP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define AP_OFFLOAD_SET_LEN_IV_GRP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define BCN_RSVDPAGE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define BCN_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define BCN_RSVDPAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define BCN_RSVDPAGE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define BCN_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define BCN_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define PROBE_RSP_RSVDPAGE_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define PROBE_RSP_RSVDPAGE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define SINGLE_CHANNELSWITCH_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define SINGLE_CHANNELSWITCH_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define SINGLE_CHANNELSWITCH_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_GET_CHANNEL_NUM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_GET_BW(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 2) +#define SINGLE_CHANNELSWITCH_SET_BW(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 2, value) +#define SINGLE_CHANNELSWITCH_GET_BW40SC(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 3) +#define SINGLE_CHANNELSWITCH_SET_BW40SC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 3, value) +#define SINGLE_CHANNELSWITCH_GET_BW80SC(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 21, 3) +#define SINGLE_CHANNELSWITCH_SET_BW80SC(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 21, 3, value) +#define SINGLE_CHANNELSWITCH_GET_RFE_TYPE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 4) +#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 4, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define SINGLE_CHANNELSWITCH_V2_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define SINGLE_CHANNELSWITCH_V2_GET_CENTRAL_CH(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define SINGLE_CHANNELSWITCH_V2_GET_PRIMARY_CH_IDX(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4) +#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value) +#define SINGLE_CHANNELSWITCH_V2_GET_BW(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 4) +#define SINGLE_CHANNELSWITCH_V2_SET_BW(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 4, value) +#define SET_PWR_MODE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define SET_PWR_MODE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define SET_PWR_MODE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define SET_PWR_MODE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define SET_PWR_MODE_GET_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7) +#define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value) +#define SET_PWR_MODE_GET_CLK_REQUEST(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1) +#define SET_PWR_MODE_SET_CLK_REQUEST(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value) +#define SET_PWR_MODE_GET_RLBM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4) +#define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value) +#define SET_PWR_MODE_GET_SMART_PS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 4) +#define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 4, value) +#define SET_PWR_MODE_GET_AWAKE_INTERVAL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 1) +#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 1, value) +#define SET_PWR_MODE_GET_BCN_EARLY_RPT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 2, 1) +#define SET_PWR_MODE_SET_BCN_EARLY_RPT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 2, 1, value) +#define SET_PWR_MODE_GET_PORT_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 5, 3) +#define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 5, 3, value) +#define SET_PWR_MODE_GET_PWR_STATE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 1) +#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 1, value) +#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 17, 1) +#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 17, 1, value) +#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 18, 1) +#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 18, 1, value) +#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 19, 1) +#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 19, 1, value) +#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 20, 1) +#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 20, 1, value) +#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 21, 1) +#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 21, 1, value) +#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 22, 1) +#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 22, 1, value) +#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 1) +#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 1, value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 25, 3) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 25, 3, value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 28, 4) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 28, 4, value) +#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define PS_TUNING_PARA_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7) +#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1) +#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_GET_PS_TIME_OUT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4) +#define PS_TUNING_PARA_SET_PS_TIME_OUT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value) +#define PS_TUNING_PARA_GET_ADOPT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define PS_TUNING_PARA_SET_ADOPT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define PS_TUNING_PARA_II_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define PS_TUNING_PARA_II_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define PS_TUNING_PARA_II_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define PS_TUNING_PARA_II_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7) +#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value) +#define PS_TUNING_PARA_II_GET_ADOPT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1) +#define PS_TUNING_PARA_II_SET_ADOPT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value) +#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define PS_LPS_PARA_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define PS_LPS_PARA_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define PS_LPS_PARA_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define PS_LPS_PARA_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define PS_LPS_PARA_GET_LPS_CONTROL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define PS_LPS_PARA_SET_LPS_CONTROL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define P2P_PS_OFFLOAD_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define P2P_PS_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define P2P_PS_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define P2P_PS_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define P2P_PS_OFFLOAD_GET_ROLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define P2P_PS_OFFLOAD_SET_ROLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define P2P_PS_OFFLOAD_GET_NOA0_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define P2P_PS_OFFLOAD_SET_NOA0_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define P2P_PS_OFFLOAD_GET_NOA1_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1) +#define P2P_PS_OFFLOAD_SET_NOA1_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value) +#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1) +#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value) +#define P2P_PS_OFFLOAD_GET_DISCOVERY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1) +#define P2P_PS_OFFLOAD_SET_DISCOVERY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value) +#define PS_SCAN_EN_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define PS_SCAN_EN_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define PS_SCAN_EN_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define PS_SCAN_EN_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define PS_SCAN_EN_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define PS_SCAN_EN_SET_ENABLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define SAP_PS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define SAP_PS_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define SAP_PS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define SAP_PS_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define SAP_PS_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define SAP_PS_SET_ENABLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define SAP_PS_GET_EN_PS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define SAP_PS_SET_EN_PS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define SAP_PS_GET_EN_LP_RX(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define SAP_PS_SET_EN_LP_RX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define SAP_PS_GET_MANUAL_32K(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define SAP_PS_SET_MANUAL_32K(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define SAP_PS_GET_DURATION(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define SAP_PS_SET_DURATION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define INACTIVE_PS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define INACTIVE_PS_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define INACTIVE_PS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define INACTIVE_PS_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define INACTIVE_PS_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define INACTIVE_PS_SET_ENABLE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define INACTIVE_PS_GET_FREQUENCY(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define INACTIVE_PS_SET_FREQUENCY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define INACTIVE_PS_GET_DURATION(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define INACTIVE_PS_SET_DURATION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define MACID_CFG_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define MACID_CFG_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define MACID_CFG_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_GET_MAC_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define MACID_CFG_SET_MAC_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_GET_RATE_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 5) +#define MACID_CFG_SET_RATE_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 5, value) +#define MACID_CFG_GET_INIT_RATE_LV(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 21, 2) +#define MACID_CFG_SET_INIT_RATE_LV(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 21, 2, value) +#define MACID_CFG_GET_SGI(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 23, 1) +#define MACID_CFG_SET_SGI(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 23, 1, value) +#define MACID_CFG_GET_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 2) +#define MACID_CFG_SET_BW(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 2, value) +#define MACID_CFG_GET_LDPC_CAP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 26, 1) +#define MACID_CFG_SET_LDPC_CAP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 26, 1, value) +#define MACID_CFG_GET_NO_UPDATE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 27, 1) +#define MACID_CFG_SET_NO_UPDATE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 27, 1, value) +#define MACID_CFG_GET_WHT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 2) +#define MACID_CFG_SET_WHT_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 2, value) +#define MACID_CFG_GET_DISPT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 30, 1) +#define MACID_CFG_SET_DISPT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 30, 1, value) +#define MACID_CFG_GET_DISRA(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 31, 1) +#define MACID_CFG_SET_DISRA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 31, 1, value) +#define MACID_CFG_GET_RATE_MASK7_0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define MACID_CFG_SET_RATE_MASK7_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_GET_RATE_MASK15_8(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define MACID_CFG_SET_RATE_MASK15_8(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define MACID_CFG_GET_RATE_MASK23_16(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define MACID_CFG_SET_RATE_MASK23_16(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define MACID_CFG_GET_RATE_MASK31_24(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define MACID_CFG_SET_RATE_MASK31_24(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define TXBF_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define TXBF_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define TXBF_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define TXBF_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define TXBF_GET_NDPA0_HEAD_PAGE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define TXBF_SET_NDPA0_HEAD_PAGE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define TXBF_GET_NDPA1_HEAD_PAGE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define TXBF_SET_NDPA1_HEAD_PAGE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define TXBF_GET_PERIOD_0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define TXBF_SET_PERIOD_0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define RSSI_SETTING_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define RSSI_SETTING_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define RSSI_SETTING_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define RSSI_SETTING_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define RSSI_SETTING_GET_MAC_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define RSSI_SETTING_SET_MAC_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define RSSI_SETTING_GET_RSSI(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 7) +#define RSSI_SETTING_SET_RSSI(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 7, value) +#define RSSI_SETTING_GET_RA_INFO(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define RSSI_SETTING_SET_RA_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define AP_REQ_TXRPT_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AP_REQ_TXRPT_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AP_REQ_TXRPT_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AP_REQ_TXRPT_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AP_REQ_TXRPT_GET_STA1_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define AP_REQ_TXRPT_SET_STA1_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define AP_REQ_TXRPT_GET_STA2_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define AP_REQ_TXRPT_SET_STA2_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1) +#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value) +#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 25, 1) +#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 25, 1, value) +#define INIT_RATE_COLLECTION_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define INIT_RATE_COLLECTION_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define INIT_RATE_COLLECTION_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define INIT_RATE_COLLECTION_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define INIT_RATE_COLLECTION_GET_STA1_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA1_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define INIT_RATE_COLLECTION_GET_STA2_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA2_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define INIT_RATE_COLLECTION_GET_STA3_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA3_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define INIT_RATE_COLLECTION_GET_STA4_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define INIT_RATE_COLLECTION_SET_STA4_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define INIT_RATE_COLLECTION_GET_STA5_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA5_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define INIT_RATE_COLLECTION_GET_STA6_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA6_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define INIT_RATE_COLLECTION_GET_STA7_MACID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA7_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define IQK_OFFLOAD_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define IQK_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define IQK_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define IQK_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define IQK_OFFLOAD_GET_CHANNEL(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define IQK_OFFLOAD_SET_CHANNEL(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define IQK_OFFLOAD_GET_BWBAND(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define IQK_OFFLOAD_SET_BWBAND(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define IQK_OFFLOAD_GET_EXTPALNA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define IQK_OFFLOAD_SET_EXTPALNA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define MACID_CFG_3SS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define MACID_CFG_3SS_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define MACID_CFG_3SS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define MACID_CFG_3SS_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define MACID_CFG_3SS_GET_MACID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define MACID_CFG_3SS_SET_MACID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define MACID_CFG_3SS_GET_RATE_MASK_39_32(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define MACID_CFG_3SS_GET_RATE_MASK_47_40(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define RA_PARA_ADJUST_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define RA_PARA_ADJUST_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define RA_PARA_ADJUST_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define RA_PARA_ADJUST_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define RA_PARA_ADJUST_GET_MAC_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define RA_PARA_ADJUST_SET_MAC_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define RA_PARA_ADJUST_GET_RATE_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define RA_PARA_ADJUST_SET_RATE_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE0(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE0(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE1(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE1(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define WWLAN_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define WWLAN_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define WWLAN_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define WWLAN_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define WWLAN_GET_FUNC_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define WWLAN_SET_FUNC_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define WWLAN_GET_PATTERM_MAT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define WWLAN_SET_PATTERM_MAT_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define WWLAN_GET_MAGIC_PKT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define WWLAN_SET_MAGIC_PKT_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define WWLAN_GET_UNICAST_WAKEUP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define WWLAN_SET_UNICAST_WAKEUP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define WWLAN_GET_ALL_PKT_DROP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1) +#define WWLAN_SET_ALL_PKT_DROP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value) +#define WWLAN_GET_GPIO_ACTIVE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1) +#define WWLAN_SET_GPIO_ACTIVE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value) +#define WWLAN_GET_REKEY_WAKEUP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1) +#define WWLAN_SET_REKEY_WAKEUP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value) +#define WWLAN_GET_DEAUTH_WAKEUP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1) +#define WWLAN_SET_DEAUTH_WAKEUP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value) +#define WWLAN_GET_GPIO_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 7) +#define WWLAN_SET_GPIO_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 7, value) +#define WWLAN_GET_DATAPIN_WAKEUP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 23, 1) +#define WWLAN_SET_DATAPIN_WAKEUP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 23, 1, value) +#define WWLAN_GET_GPIO_DURATION(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define WWLAN_SET_GPIO_DURATION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define WWLAN_GET_GPIO_PLUS_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 1) +#define WWLAN_SET_GPIO_PLUS_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 1, value) +#define WWLAN_GET_GPIO_PULSE_COUNT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 1, 7) +#define WWLAN_SET_GPIO_PULSE_COUNT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 1, 7, value) +#define WWLAN_GET_DISABLE_UPHY(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 1) +#define WWLAN_SET_DISABLE_UPHY(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 1, value) +#define WWLAN_GET_HST2DEV_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 9, 1) +#define WWLAN_SET_HST2DEV_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 9, 1, value) +#define WWLAN_GET_GPIO_DURATION_MS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 10, 1) +#define WWLAN_SET_GPIO_DURATION_MS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 10, 1, value) +#define REMOTE_WAKE_CTRL_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define REMOTE_WAKE_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define REMOTE_WAKE_CTRL_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define REMOTE_WAKE_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define REMOTE_WAKE_CTRL_GET_ARP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value) +#define REMOTE_WAKE_CTRL_GET_NDP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1) +#define REMOTE_WAKE_CTRL_SET_NDP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value) +#define REMOTE_WAKE_CTRL_GET_GTK_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1) +#define REMOTE_WAKE_CTRL_SET_GTK_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value) +#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1) +#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1) +#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value) +#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 1) +#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 1, value) +#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 17, 1) +#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 17, 1, value) +#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 1) +#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 1, value) +#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 1, value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 29, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 29, 1, value) +#define AOAC_GLOBAL_INFO_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AOAC_GLOBAL_INFO_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_GLOBAL_INFO_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AOAC_GLOBAL_INFO_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define AOAC_RSVD_PAGE2_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE2_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE2_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE2_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value) +#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value) +#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value) +#define AOAC_RSVD_PAGE3_GET_CMD_ID(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define AOAC_RSVD_PAGE3_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define AOAC_RSVD_PAGE3_GET_CLASS(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define AOAC_RSVD_PAGE3_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value) +#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(h2c_pkt) \ + LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value) +#define DBG_MSG_CTRL_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5) +#define DBG_MSG_CTRL_SET_CMD_ID(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value) +#define DBG_MSG_CTRL_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3) +#define DBG_MSG_CTRL_SET_CLASS(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value) +#define DBG_MSG_CTRL_GET_FUN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1) +#define DBG_MSG_CTRL_SET_FUN_EN(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value) +#define DBG_MSG_CTRL_GET_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 4) +#define DBG_MSG_CTRL_SET_MODE(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 4, value) #endif diff --git a/hal/halmac/halmac_pcie_reg.h b/hal/halmac/halmac_pcie_reg.h index 8808e7b..a2406be 100644 --- a/hal/halmac/halmac_pcie_reg.h +++ b/hal/halmac/halmac_pcie_reg.h @@ -1,8 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __HALMAC_PCIE_REG_H__ #define __HALMAC_PCIE_REG_H__ +/* PCIE PHY register */ +#define RAC_CTRL_PPR 0x00 +#define RAC_SET_PPR 0x20 +#define RAC_TRG_PPR 0x21 +/* PCIE CFG register */ +#define PCIE_L1_BACKDOOR 0x719 +#define PCIE_ASPM_CTRL 0x70F +/* PCIE MAC register */ +#define LINK_CTRL2_REG_OFFSET 0xA0 +#define GEN2_CTRL_OFFSET 0x80C +#define LINK_STATUS_REG_OFFSET 0x82 +#define PCIE_GEN1_SPEED 0x01 +#define PCIE_GEN2_SPEED 0x02 #endif/* __HALMAC_PCIE_REG_H__ */ diff --git a/hal/halmac/halmac_pwr_seq_cmd.h b/hal/halmac/halmac_pwr_seq_cmd.h index 9b60e59..c51fb52 100644 --- a/hal/halmac/halmac_pwr_seq_cmd.h +++ b/hal/halmac/halmac_pwr_seq_cmd.h @@ -1,81 +1,75 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef HALMAC_POWER_SEQUENCE_CMD #define HALMAC_POWER_SEQUENCE_CMD #include "halmac_2_platform.h" -#include "halmac_type.h" -#define HALMAC_POLLING_READY_TIMEOUT_COUNT 20000 +#define HALMAC_PWR_POLLING_CNT 20000 -/* -* The value of cmd : 4 bits -*/ +/* The value of cmd : 4 bits */ -/* -* offset : the read register offset -* msk : the mask of the read value -* value : N/A, left by 0 -* Note : dirver shall implement this function by read & msk -*/ +/* offset : the read register offset + * msk : the mask of the read value + * value : N/A, left by 0 + * Note : dirver shall implement this function by read & msk + */ #define HALMAC_PWR_CMD_READ 0x00 -/* -* offset: the read register offset -* msk: the mask of the write bits -* value: write value -* Note: driver shall implement this cmd by read & msk after write -*/ +/* offset: the read register offset + * msk: the mask of the write bits + * value: write value + * Note: driver shall implement this cmd by read & msk after write + */ #define HALMAC_PWR_CMD_WRITE 0x01 -/* -* offset: the read register offset -* msk: the mask of the polled value -* value: the value to be polled, masked by the msd field. -* Note: driver shall implement this cmd by -* do{ -* if( (Read(offset) & msk) == (value & msk) ) -* break; -* } while(not timeout); -*/ +/* offset: the read register offset + * msk: the mask of the polled value + * value: the value to be polled, masked by the msd field. + * Note: driver shall implement this cmd by + * do{ + * if( (Read(offset) & msk) == (value & msk) ) + * break; + * } while(not timeout); + */ #define HALMAC_PWR_CMD_POLLING 0x02 -/* -* offset: the value to delay -* msk: N/A -* value: the unit of delay, 0: us, 1: ms -*/ +/* offset: the value to delay + * msk: N/A + * value: the unit of delay, 0: us, 1: ms + */ #define HALMAC_PWR_CMD_DELAY 0x03 -/* -* offset: N/A -* msk: N/A -* value: N/A -*/ -#define HALMAC_PWR_CMD_END 0x04 +/* offset: N/A + * msk: N/A + * value: N/A + */ +#define HALMAC_PWR_CMD_END 0x04 -/* -* The value of base : 4 bits -*/ +/* The value of base : 4 bits */ /* define the base address of each block */ -#define HALMAC_PWR_BASEADDR_MAC 0x00 -#define HALMAC_PWR_BASEADDR_USB 0x01 -#define HALMAC_PWR_BASEADDR_PCIE 0x02 -#define HALMAC_PWR_BASEADDR_SDIO 0x03 +#define HALMAC_PWR_ADDR_MAC 0x00 +#define HALMAC_PWR_ADDR_USB 0x01 +#define HALMAC_PWR_ADDR_PCIE 0x02 +#define HALMAC_PWR_ADDR_SDIO 0x03 -/* -* The value of interface_msk : 4 bits -*/ +/* The value of interface_msk : 4 bits */ #define HALMAC_PWR_INTF_SDIO_MSK BIT(0) #define HALMAC_PWR_INTF_USB_MSK BIT(1) #define HALMAC_PWR_INTF_PCI_MSK BIT(2) -#define HALMAC_PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) - -/* -* The value of fab_msk : 4 bits -*/ -#define HALMAC_PWR_FAB_TSMC_MSK BIT(0) -#define HALMAC_PWR_FAB_UMC_MSK BIT(1) -#define HALMAC_PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) +#define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) -/* -* The value of cut_msk : 8 bits -*/ +/* The value of cut_msk : 8 bits */ #define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0) #define HALMAC_PWR_CUT_A_MSK BIT(1) #define HALMAC_PWR_CUT_B_MSK BIT(2) @@ -86,21 +80,19 @@ #define HALMAC_PWR_CUT_G_MSK BIT(7) #define HALMAC_PWR_CUT_ALL_MSK 0xFF -typedef enum _HALMAC_PWRSEQ_CMD_DELAY_UNIT_ { - HALMAC_PWRSEQ_DELAY_US, - HALMAC_PWRSEQ_DELAY_MS, -} HALMAC_PWRSEQ_DELAY_UNIT; +enum halmac_pwrseq_cmd_delay_unit { + HALMAC_PWR_DELAY_US, + HALMAC_PWR_DELAY_MS, +}; -/* Don't care endian issue, because element of pwer seq vector is fixed address */ -typedef struct _HALMAC_WL_PWR_CFG_ { +struct halmac_wlan_pwr_cfg { u16 offset; - u8 cut_msk; - u8 fab_msk:4; - u8 interface_msk:4; - u8 base:4; - u8 cmd:4; - u8 msk; - u8 value; -} HALMAC_WLAN_PWR_CFG, *PHALMAC_WLAN_PWR_CFG; + u8 cut_msk; + u8 interface_msk; + u8 base:4; + u8 cmd:4; + u8 msk; + u8 value; +}; #endif diff --git a/hal/halmac/halmac_reg2.h b/hal/halmac/halmac_reg2.h index 5627a04..673e33e 100644 --- a/hal/halmac/halmac_reg2.h +++ b/hal/halmac/halmac_reg2.h @@ -1,3159 +1,8111 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __HALMAC_COM_REG_H__ #define __HALMAC_COM_REG_H__ -/*-------------------------Modification Log----------------------------------- - For Page0, it is based on Combo_And_WL_Only_Page0_Reg.xls SVN524 - The supported IC are 8723A, 8881A, 8723B, 8192E, 8881A - 8812A and 8188E is not included in page0 register - - For other pages, it is based on MAC_Register.doc SVN502 - Most IC is the same with 8812A --------------------------Modification Log-----------------------------------*/ -/*--------------------------Include File--------------------------------------*/ #include "halmac_hw_cfg.h" -/*--------------------------Include File--------------------------------------*/ +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) +#define REG_SYS_ISO_CTRL 0x0000 +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define REG_SYS_ISO_CTRL 0x0000 +#define REG_SDIO_TX_CTRL 0x10250000 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_TX_CTRL 0x10250000 +#define REG_SYS_FUNC_EN 0x0002 +#define REG_SYS_PW_CTRL 0x0004 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SYS_FUNC_EN 0x0002 -#define REG_SYS_PW_CTRL 0x0004 -#define REG_SYS_CLK_CTRL 0x0008 -#define REG_SYS_EEPROM_CTRL 0x000A -#define REG_EE_VPD 0x000C -#define REG_SYS_SWR_CTRL1 0x0010 -#define REG_SYS_SWR_CTRL2 0x0014 +#define REG_SDIO_CMD11_VOL_SWITCH 0x10250004 +#define REG_SDIO_CTRL 0x10250005 +#define REG_SDIO_DRIVING 0x10250006 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HIMR 0x10250014 +#define REG_SYS_CLK_CTRL 0x0008 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SYS_SWR_CTRL3 0x0018 +#define REG_SDIO_MONITOR 0x10250008 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HISR 0x10250018 +#define REG_SYS_EEPROM_CTRL 0x000A +#define REG_EE_VPD 0x000C #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RSV_CTRL 0x001C +#define REG_SDIO_MONITOR_2 0x1025000C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_RX_REQ_LEN 0x1025001C +#define REG_SYS_SWR_CTRL1 0x0010 +#define REG_SYS_SWR_CTRL2 0x0014 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RF_CTRL 0x001F +#define REG_SDIO_HIMR 0x10250014 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_RF0_CTRL 0x001F +#define REG_SYS_SWR_CTRL3 0x0018 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F +#define REG_SDIO_HISR 0x10250018 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AFE_LDO_CTRL 0x0020 +#define REG_RSV_CTRL 0x001C #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_FREE_TXPG 0x10250020 +#define REG_SDIO_RX_REQ_LEN 0x1025001C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AFE_CTRL1 0x0024 +#define REG_RF_CTRL 0x001F #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_FREE_TXPG2 0x10250024 +#define REG_RF0_CTRL 0x001F #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AFE_CTRL2 0x0028 +#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028 +#define REG_AFE_LDO_CTRL 0x0020 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AFE_CTRL3 0x002C -#define REG_EFUSE_CTRL 0x0030 +#define REG_SDIO_FREE_TXPG 0x10250020 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HTSFR_INFO 0x10250030 +#define REG_AFE_CTRL1 0x0024 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LDO_EFUSE_CTRL 0x0034 -#define REG_PWR_OPTION_CTRL 0x0038 +#define REG_SDIO_FREE_TXPG2 0x10250024 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HCPWM1_V2 0x10250038 -#define REG_SDIO_HCPWM2_V2 0x1025003A +#define REG_AFE_CTRL2 0x0028 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028 -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define REG_CAL_TIMER 0x003C -#define REG_ACLK_MON 0x003E -#define REG_GPIO_MUXCFG 0x0040 +#define REG_ANAPARSW_POW_MAC 0x0028 +#define REG_ANAPARLDO_POW_MAC 0x0029 +#define REG_ANAPAR_POW_MAC 0x002A +#define REG_ANAPAR_POW_XTAL 0x002B #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_AFE_CTRL3 0x002C + +#endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#define REG_SDIO_INDIRECT_REG_CFG 0x10250040 +#define REG_ANAPARLDO_MAC 0x002C #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SDIO_TXPKT_EMPTY 0x1025002C + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_GPIO_PIN_CTRL 0x0044 +#define REG_EFUSE_CTRL 0x0030 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define REG_SDIO_HTSFR_INFO 0x10250030 -#define REG_SDIO_INDIRECT_REG_DATA 0x10250044 +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_LDO_EFUSE_CTRL 0x0034 +#define REG_PWR_OPTION_CTRL 0x0038 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_SDIO_HCPWM1_V2 0x10250038 +#define REG_SDIO_HCPWM2_V2 0x1025003A -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_GPIO_INTM 0x0048 -#define REG_LED_CFG 0x004C -#define REG_FSIMR 0x0050 -#define REG_FSISR 0x0054 -#define REG_HSIMR 0x0058 -#define REG_HSISR 0x005C -#define REG_GPIO_EXT_CTRL 0x0060 +#define REG_CAL_TIMER 0x003C +#define REG_ACLK_MON 0x003E #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_GPIO_MUXCFG_2 0x003F + +#endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_SDIO_H2C 0x10250060 +#define REG_GPIO_MUXCFG 0x0040 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_SDIO_INDIRECT_REG_CFG 0x10250040 + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_PAD_CTRL1 0x0064 +#define REG_GPIO_PIN_CTRL 0x0044 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#define REG_SDIO_INDIRECT_REG_DATA 0x10250044 -#define REG_SDIO_C2H 0x10250064 +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_GPIO_INTM 0x0048 +#define REG_LED_CFG 0x004C +#define REG_FSIMR 0x0050 +#define REG_FSISR 0x0054 +#define REG_HSIMR 0x0058 +#define REG_HSISR 0x005C +#define REG_GPIO_EXT_CTRL 0x0060 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_SDIO_H2C 0x10250060 -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_WL_BT_PWR_CTRL 0x0068 +#define REG_PAD_CTRL1 0x0064 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_SDIO_C2H 0x10250064 + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_SDM_DEBUG 0x006C +#define REG_WL_BT_PWR_CTRL 0x0068 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_SDM_DEBUG 0x006C + +#endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define REG_GSSR 0x006C +#define REG_GSSR 0x006C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SYS_SDIO_CTRL 0x0070 +#define REG_SYS_SDIO_CTRL 0x0070 #endif - #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define REG_SYS_CLKR 0x0070 +#define REG_SYS_CLKR 0x0070 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HCI_OPT_CTRL 0x0074 +#define REG_HCI_OPT_CTRL 0x0074 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AFE_CTRL4 0x0078 +#define REG_AFE_CTRL4 0x0078 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_HCI_BG_CTRL 0x0078 + +#endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define REG_AFE_XTAL_CTRL_EXT 0x0078 +#define REG_AFE_XTAL_CTRL_EXT 0x0078 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LDO_SWR_CTRL 0x007C +#define REG_HCI_LDO_CTRL 0x007A #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_LDO_SWR_CTRL 0x007C + +#endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_8051FW_CTRL 0x0080 +#define REG_8051FW_CTRL 0x0080 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MCUFW_CTRL 0x0080 +#define REG_MCUFW_CTRL 0x0080 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HRPWM1 0x10250080 -#define REG_SDIO_HRPWM2 0x10250082 +#define REG_SDIO_HRPWM1 0x10250080 +#define REG_SDIO_HRPWM2 0x10250082 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MCU_TST_CFG 0x0084 +#define REG_MCU_TST_CFG 0x0084 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HPS_CLKR 0x10250084 -#define REG_SDIO_BUS_CTRL 0x10250085 +#define REG_SDIO_HPS_CLKR 0x10250084 +#define REG_SDIO_BUS_CTRL 0x10250085 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HSUS_CTRL 0x10250086 +#define REG_SDIO_HSUS_CTRL 0x10250086 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HMEBOX_E0_E1 0x0088 +#define REG_HMEBOX_E0_E1 0x0088 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_RESPONSE_TIMER 0x10250088 +#define REG_SDIO_RESPONSE_TIMER 0x10250088 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_CMD_CRC 0x1025008A +#define REG_SDIO_CMD_CRC 0x1025008A #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HMEBOX_E2_E3 0x008C -#define REG_WLLPS_CTRL 0x0090 +#define REG_HMEBOX_E2_E3 0x008C +#define REG_WLLPS_CTRL 0x0090 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_HSISR 0x10250090 -#define REG_SDIO_HSIMR 0x10250091 +#define REG_SDIO_HSISR 0x10250090 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_AFE_CTRL5 0x0094 +#define REG_SDIO_HSIMR 0x10250091 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_GPIO_DEBOUNCE_CTRL 0x0098 -#define REG_RPWM2 0x009C -#define REG_SYSON_FSM_MON 0x00A0 +#define REG_AFE_CTRL5 0x0094 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_AFE_CTRL6 0x00A4 +#define REG_GPIO_DEBOUNCE_CTRL 0x0098 +#define REG_RPWM2 0x009C +#define REG_SYSON_FSM_MON 0x00A0 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PMC_DBG_CTRL1 0x00A8 +#define REG_AFE_CTRL6 0x00A4 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_AFE_CTRL7 0x00AC +#define REG_PMC_DBG_CTRL1 0x00A8 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HIMR0 0x00B0 -#define REG_HISR0 0x00B4 -#define REG_HIMR1 0x00B8 -#define REG_HISR1 0x00BC -#define REG_DBG_PORT_SEL 0x00C0 +#define REG_AFE_CTRL7 0x00AC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_ERR_RPT 0x102500C0 -#define REG_SDIO_CMD_ERRCNT 0x102500C1 -#define REG_SDIO_DATA_ERRCNT 0x102500C2 +#define REG_HIMR0 0x00B0 +#define REG_HISR0 0x00B4 +#define REG_HIMR1 0x00B8 +#define REG_HISR1 0x00BC +#define REG_DBG_PORT_SEL 0x00C0 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SDIO_DIOERR_RPT 0x102500C0 -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#define REG_PAD_CTRL2 0x00C4 +#define REG_SDIO_ERR_RPT 0x102500C0 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_SDIO_CMD_ERRCNT 0x102500C2 +#define REG_SDIO_DATA_ERRCNT 0x102500C3 + +#endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4 +#define REG_PAD_CTRL2 0x00C4 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4 + +#endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define REG_MEM_RMC 0x00C8 +#define REG_MEM_RMC 0x00C8 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SDIO_CRC_ERR_IDX 0x102500C9 -#define REG_SDIO_DATA_CRC 0x102500CA -#define REG_SDIO_DATA_REPLY_TIME 0x102500CB +#define REG_SDIO_CRC_ERR_IDX 0x102500C9 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PMC_DBG_CTRL2 0x00CC -#define REG_BIST_CTRL 0x00D0 -#define REG_BIST_RPT 0x00D4 -#define REG_MEM_CTRL 0x00D8 +#define REG_SDIO_DATA_CRC 0x102500CA #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_AFE_CTRL8 0x00DC +#define REG_SDIO_DATA_REPLY_TIME 0x102500CB #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_WLAN_DBG 0x00DC +#define REG_PMC_DBG_CTRL2 0x00CC #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_USB_SIE_INTF 0x00E0 -#define REG_PCIE_MIO_INTF 0x00E4 -#define REG_PCIE_MIO_INTD 0x00E8 +#define REG_SDIO_TRANS_FIFO_STATUS 0x102500CC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BIST_CTRL 0x00D0 +#define REG_BIST_RPT 0x00D4 -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_WLRF1 0x00EC +#define REG_MEM_CTRL 0x00D8 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_AFE_CTRL8 0x00DC + +#endif #if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#define REG_HPON_FSM 0x00EC +#define REG_WLAN_DBG 0x00DC #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SYS_CFG1 0x00F0 -#define REG_SYS_STATUS1 0x00F4 -#define REG_SYS_STATUS2 0x00F8 -#define REG_SYS_CFG2 0x00FC -#define REG_CR 0x0100 +#define REG_SYN_RFC_CTRL 0x00DC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 +#define REG_USB_SIE_INTF 0x00E0 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TSF_CLK_STATE 0x0108 -#define REG_TXDMA_PQ_MAP 0x010C -#define REG_TRXFF_BNDY 0x0114 +#define REG_SYS_PINMUX 0x00E0 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PTA_I2C_MBOX 0x0118 +#define REG_PCIE_MIO_INTF 0x00E4 +#define REG_PCIE_MIO_INTD 0x00E8 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT) - -#define REG_FF_STATUS 0x0118 +#define REG_WLRF1 0x00EC #endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RXFF_PTR 0x011C +#define REG_HPON_FSM 0x00EC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RXFF_BNDY 0x011C +#define REG_SYS_CFG1 0x00F0 +#define REG_SYS_STATUS1 0x00F4 +#define REG_SYS_STATUS2 0x00F8 +#define REG_SYS_CFG2 0x00FC +#define REG_CR 0x0100 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_FEIMR 0x0120 +#define REG_PG_SIZE 0x0104 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FE1IMR 0x0120 +#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_FEISR 0x0124 +#define REG_TSF_CLK_STATE 0x0108 +#define REG_TXDMA_PQ_MAP 0x010C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FE1ISR 0x0124 +#define REG_TRXFF_BNDY 0x0114 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_CPWM 0x012C -#define REG_FWIMR 0x0130 -#define REG_FWISR 0x0134 -#define REG_FTIMR 0x0138 -#define REG_FTISR 0x013C -#define REG_PKTBUF_DBG_CTRL 0x0140 -#define REG_PKTBUF_DBG_DATA_L 0x0144 -#define REG_PKTBUF_DBG_DATA_H 0x0148 -#define REG_CPWM2 0x014C -#define REG_TC0_CTRL 0x0150 -#define REG_TC1_CTRL 0x0154 -#define REG_TC2_CTRL 0x0158 -#define REG_TC3_CTRL 0x015C -#define REG_TC4_CTRL 0x0160 -#define REG_TCUNIT_BASE 0x0164 -#define REG_TC5_CTRL 0x0168 -#define REG_TC6_CTRL 0x016C -#define REG_MBIST_FAIL 0x0170 -#define REG_MBIST_START_PAUSE 0x0174 -#define REG_MBIST_DONE 0x0178 +#define REG_RXFF_BNDY_V1 0x0114 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MBIST_ROM_CRC_DATA 0x017C +#define REG_PTA_I2C_MBOX 0x0118 #endif +#if (HALMAC_8814A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MBIST_FAIL_NRML 0x017C +#define REG_FF_STATUS 0x0118 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AES_DECRPT_DATA 0x0180 -#define REG_AES_DECRPT_CFG 0x0184 +#define REG_RXFF_PTR 0x011C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_MACCLKFRQ 0x018C +#define REG_RXFF_BNDY 0x011C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TMETER 0x0190 -#define REG_OSC_32K_CTRL 0x0194 -#define REG_32K_CAL_REG1 0x0198 -#define REG_C2HEVT 0x01A0 +#define REG_FEIMR 0x0120 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_C2HEVT_1 0x01A4 -#define REG_C2HEVT_2 0x01A8 -#define REG_C2HEVT_3 0x01AC +#define REG_FE1IMR 0x0120 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814A_SUPPORT) - -#define REG_TC7_CTRL 0x01B0 -#define REG_TC8_CTRL 0x01B4 +#define REG_FEISR 0x0124 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SW_DEFINED_PAGE1 0x01B8 +#define REG_FE1ISR 0x0124 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_SW_DEFINED_PAGE2 0x01BC +#define REG_CPWM 0x012C +#define REG_FWIMR 0x0130 +#define REG_FWISR 0x0134 +#define REG_FTIMR 0x0138 +#define REG_FTISR 0x013C +#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_PKTBUF_DBG_DATA_L 0x0144 +#define REG_PKTBUF_DBG_DATA_H 0x0148 +#define REG_CPWM2 0x014C +#define REG_TC0_CTRL 0x0150 +#define REG_TC1_CTRL 0x0154 +#define REG_TC2_CTRL 0x0158 +#define REG_TC3_CTRL 0x015C +#define REG_TC4_CTRL 0x0160 +#define REG_TCUNIT_BASE 0x0164 +#define REG_TC5_CTRL 0x0168 +#define REG_TC6_CTRL 0x016C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_MBIST_FAIL 0x0170 + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#define REG_MCUTST_I 0x01C0 -#define REG_MCUTST_II 0x01C4 -#define REG_FMETHR 0x01C8 -#define REG_HMETFR 0x01CC -#define REG_HMEBOX0 0x01D0 -#define REG_HMEBOX1 0x01D4 -#define REG_HMEBOX2 0x01D8 -#define REG_HMEBOX3 0x01DC -#define REG_LLT_INIT 0x01E0 +#define REG_MBIST_DRF_FAIL 0x0170 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MBIST_START_PAUSE 0x0174 +#define REG_MBIST_DONE 0x0178 + +#endif #if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) -#define REG_GENTST 0x01E4 +#define REG_MBIST_ROM_CRC_DATA 0x017C #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_LLT_INIT_ADDR 0x01E4 +#define REG_MBIST_NRML_FAIL 0x017C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BB_ACCESS_CTRL 0x01E8 -#define REG_BB_ACCESS_DATA 0x01EC -#define REG_HMEBOX_E0 0x01F0 -#define REG_HMEBOX_E1 0x01F4 -#define REG_HMEBOX_E2 0x01F8 -#define REG_HMEBOX_E3 0x01FC +#define REG_MBIST_FAIL_NRML 0x017C #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RQPN_CTRL_HLPQ 0x0200 +#define REG_MBIST_READ_BIST_RPT 0x017C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FIFOPAGE_CTRL_1 0x0200 +#define REG_AES_DECRPT_DATA 0x0180 +#define REG_AES_DECRPT_CFG 0x0184 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_FIFOPAGE_INFO 0x0204 +#define REG_MBIST_READ_BIST_RPT_V1 0x0188 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FIFOPAGE_CTRL_2 0x0204 +#define REG_HIOE_CTRL 0x0188 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_DWBCN0_CTRL 0x0208 +#define REG_MACCLKFRQ 0x018C #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_AUTO_LLT_V1 0x0208 +#define REG_HIOE_CFG_FILE 0x018C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TXDMA_OFFSET_CHK 0x020C -#define REG_TXDMA_STATUS 0x0210 +#define REG_TMETER 0x0190 +#define REG_OSC_32K_CTRL 0x0194 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RQPN_NPQ 0x0214 +#define REG_32K_CAL_REG1 0x0198 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TX_DMA_DBG 0x0214 +#define REG_32K_CAL_REG0 0x0198 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TQPNT1 0x0218 -#define REG_TQPNT2 0x021C +#define REG_C2HEVT 0x01A0 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TDE_DEBUG 0x0220 +#define REG_C2HEVT_1 0x01A4 +#define REG_C2HEVT_2 0x01A8 +#define REG_C2HEVT_3 0x01AC #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TQPNT3 0x0220 +#define REG_MISC_CTRL_V1 0x01B0 #endif +#if (HALMAC_8814A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AUTO_LLT 0x0224 +#define REG_TC7_CTRL 0x01B0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TQPNT4 0x0224 +#define REG_RXDESC_BUFF_RPTR 0x01B0 #endif +#if (HALMAC_8814A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_DWBCN1_CTRL 0x0228 +#define REG_TC8_CTRL 0x01B4 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RQPN_CTRL_1 0x0228 -#define REG_RQPN_CTRL_2 0x022C -#define REG_FIFOPAGE_INFO_1 0x0230 -#define REG_FIFOPAGE_INFO_2 0x0234 -#define REG_FIFOPAGE_INFO_3 0x0238 -#define REG_FIFOPAGE_INFO_4 0x023C -#define REG_FIFOPAGE_INFO_5 0x0240 +#define REG_RXDESC_BUFF_WPTR 0x01B4 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_H2C_HEAD 0x0244 -#define REG_H2C_TAIL 0x0248 -#define REG_H2C_READ_ADDR 0x024C -#define REG_H2C_WR_ADDR 0x0250 -#define REG_H2C_INFO 0x0254 +#define REG_SW_DEFINED_PAGE1 0x01B8 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RXDMA_AGG_PG_TH 0x0280 -#define REG_RXPKT_NUM 0x0284 -#define REG_RXDMA_STATUS 0x0288 -#define REG_RXDMA_DPR 0x028C -#define REG_RXDMA_MODE 0x0290 -#define REG_C2H_PKT 0x0294 +#define REG_SW_DEFINED_PAGE2 0x01BC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FWFF_C2H 0x0298 -#define REG_FWFF_CTRL 0x029C -#define REG_FWFF_PKT_INFO 0x02A0 +#define REG_MCUTST_I 0x01C0 +#define REG_MCUTST_II 0x01C4 +#define REG_FMETHR 0x01C8 +#define REG_HMETFR 0x01CC +#define REG_HMEBOX0 0x01D0 +#define REG_HMEBOX1 0x01D4 +#define REG_HMEBOX2 0x01D8 +#define REG_HMEBOX3 0x01DC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_FC2H_INFO 0x02A6 +#define REG_LLT_INIT 0x01E0 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PCIE_CTRL 0x0300 +#define REG_LLT_IND_ACCESS 0x01E0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_CTRL 0x0300 +#define REG_RXDESC_BUFF_BNDY 0x01E0 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_LX_CTRL1 0x0300 +#define REG_GENTST 0x01E4 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_INT_MIG 0x0304 -#define REG_BCNQ_TXBD_DESA 0x0308 -#define REG_MGQ_TXBD_DESA 0x0310 -#define REG_VOQ_TXBD_DESA 0x0318 -#define REG_VIQ_TXBD_DESA 0x0320 -#define REG_BEQ_TXBD_DESA 0x0328 -#define REG_BKQ_TXBD_DESA 0x0330 -#define REG_RXQ_RXBD_DESA 0x0338 -#define REG_HI0Q_TXBD_DESA 0x0340 -#define REG_HI1Q_TXBD_DESA 0x0348 -#define REG_HI2Q_TXBD_DESA 0x0350 -#define REG_HI3Q_TXBD_DESA 0x0358 -#define REG_HI4Q_TXBD_DESA 0x0360 -#define REG_HI5Q_TXBD_DESA 0x0368 -#define REG_HI6Q_TXBD_DESA 0x0370 -#define REG_HI7Q_TXBD_DESA 0x0378 -#define REG_MGQ_TXBD_NUM 0x0380 -#define REG_RX_RXBD_NUM 0x0382 -#define REG_VOQ_TXBD_NUM 0x0384 -#define REG_VIQ_TXBD_NUM 0x0386 -#define REG_BEQ_TXBD_NUM 0x0388 -#define REG_BKQ_TXBD_NUM 0x038A -#define REG_HI0Q_TXBD_NUM 0x038C -#define REG_HI1Q_TXBD_NUM 0x038E -#define REG_HI2Q_TXBD_NUM 0x0390 -#define REG_HI3Q_TXBD_NUM 0x0392 -#define REG_HI4Q_TXBD_NUM 0x0394 -#define REG_HI5Q_TXBD_NUM 0x0396 -#define REG_HI6Q_TXBD_NUM 0x0398 -#define REG_HI7Q_TXBD_NUM 0x039A -#define REG_TSFTIMER_HCI 0x039C -#define REG_BD_RWPTR_CLR 0x039C -#define REG_VOQ_TXBD_IDX 0x03A0 -#define REG_VIQ_TXBD_IDX 0x03A4 -#define REG_BEQ_TXBD_IDX 0x03A8 -#define REG_BKQ_TXBD_IDX 0x03AC -#define REG_MGQ_TXBD_IDX 0x03B0 -#define REG_RXQ_RXBD_IDX 0x03B4 -#define REG_HI0Q_TXBD_IDX 0x03B8 -#define REG_HI1Q_TXBD_IDX 0x03BC -#define REG_HI2Q_TXBD_IDX 0x03C0 -#define REG_HI3Q_TXBD_IDX 0x03C4 -#define REG_HI4Q_TXBD_IDX 0x03C8 -#define REG_HI5Q_TXBD_IDX 0x03CC -#define REG_HI6Q_TXBD_IDX 0x03D0 -#define REG_HI7Q_TXBD_IDX 0x03D4 +#define REG_LLT_INIT_ADDR 0x01E4 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DBG_SEL_V1 0x03D8 +#define REG_BB_ACCESS_CTRL 0x01E8 +#define REG_BB_ACCESS_DATA 0x01EC +#define REG_HMEBOX_E0 0x01F0 +#define REG_HMEBOX_E1 0x01F4 +#define REG_HMEBOX_E2 0x01F8 +#define REG_HMEBOX_E3 0x01FC #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_HRPWM1_V1 0x03D9 +#define REG_RQPN_CTRL_HLPQ 0x0200 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_HRPWM1_V1 0x03D9 +#define REG_FIFOPAGE_CTRL_1 0x0200 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_HCPWM1_V1 0x03DA +#define REG_BCN_CTRL_0 0x0200 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_HCPWM1_V1 0x03DA +#define REG_FIFOPAGE_INFO 0x0204 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PCIE_CTRL2 0x03DB +#define REG_FIFOPAGE_CTRL_2 0x0204 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_CTRL2 0x03DB +#define REG_BCN_CTRL_1 0x0204 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_LX_CTRL2 0x03DB +#define REG_DWBCN0_CTRL 0x0208 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_HRPWM2_V1 0x03DC +#define REG_AUTO_LLT_V1 0x0208 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_HRPWM2_V1 0x03DC +#define REG_TXDMA_OFFSET_CHK 0x020C +#define REG_TXDMA_STATUS 0x0210 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_HCPWM2_V1 0x03DE +#define REG_RQPN_NPQ 0x0214 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_HCPWM2_V1 0x03DE +#define REG_TX_DMA_DBG 0x0214 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_H2C_MSG_V1 0x03E0 +#define REG_TQPNT1 0x0218 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_H2C_MSG_V1 0x03E0 +#define REG_DMA_RQPN_INFO_PUB 0x0218 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PCIE_C2H_MSG_V1 0x03E4 +#define REG_TQPNT2 0x021C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_HCI_C2H_MSG_V1 0x03E4 +#define REG_RQPN_CTRL_2_V1 0x021C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DBI_WDATA_V1 0x03E8 +#define REG_TDE_DEBUG 0x0220 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_LX_DMA_ISR 0x03E8 +#define REG_TQPNT3 0x0220 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DBI_RDATA_V1 0x03EC +#define REG_BCN_CTRL_2 0x0220 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_LX_DMA_IMR 0x03EC +#define REG_AUTO_LLT 0x0224 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DBI_FLAG_V1 0x03F0 +#define REG_TQPNT4 0x0224 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_STUCK_FLAG_V1 0x03F0 +#define REG_DWBCN1_CTRL 0x0228 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_LX_DMA_DBG 0x03F0 +#define REG_RQPN_CTRL_1 0x0228 +#define REG_RQPN_CTRL_2 0x022C #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MDIO_V1 0x03F4 +#define REG_RQPN_EXQ1_EXQ2 0x0230 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT) - -#define REG_MDIO2_V1 0x03F8 +#define REG_FIFOPAGE_INFO_1 0x0230 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_WDT_CFG 0x03F8 +#define REG_TXPKTNUM_0 0x0230 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PCIE_MIX_CFG 0x03F8 +#define REG_TQPNT3_V1 0x0234 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_BUS_MIX_CFG 0x03F8 +#define REG_FIFOPAGE_INFO_2 0x0234 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_HCI_MIX_CFG 0x03FC +#define REG_TXPKTNUM_1 0x0234 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8881A_SUPPORT) - -#define REG_BUS_MIX_CFG1 0x03FC +#define REG_FIFOPAGE_INFO_3 0x0238 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_Q0_INFO 0x0400 -#define REG_Q1_INFO 0x0404 -#define REG_Q2_INFO 0x0408 -#define REG_Q3_INFO 0x040C -#define REG_MGQ_INFO 0x0410 -#define REG_HIQ_INFO 0x0414 -#define REG_BCNQ_INFO 0x0418 -#define REG_TXPKT_EMPTY 0x041A -#define REG_CPU_MGQ_INFO 0x041C -#define REG_FWHW_TXQ_CTRL 0x0420 +#define REG_TXPKTNUM_2 0x0238 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HWSEQ_CTRL 0x0423 +#define REG_FIFOPAGE_INFO_4 0x023C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DATAFB_SEL 0x0423 +#define REG_TXPKTNUM_3 0x023C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BCNQ_BDNY 0x0424 +#define REG_FIFOPAGE_INFO_5 0x0240 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BCNQ_BDNY_V1 0x0424 +#define REG_TX_AGG_ALIGN 0x0240 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MGQ_BDNY 0x0425 +#define REG_H2C_HEAD 0x0244 +#define REG_H2C_TAIL 0x0248 +#define REG_H2C_READ_ADDR 0x024C +#define REG_H2C_WR_ADDR 0x0250 +#define REG_H2C_INFO 0x0254 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LIFETIME_EN 0x0426 +#define REG_TQPNT5 0x0260 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_FW_FREE_TAIL 0x0427 +#define REG_DMA_OQT_0 0x0260 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SPEC_SIFS 0x0428 -#define REG_RETRY_LIMIT 0x042A -#define REG_TXBF_CTRL 0x042C -#define REG_DARFRC 0x0430 -#define REG_RARFRC 0x0438 -#define REG_RRSR 0x0440 -#define REG_ARFR0 0x0444 -#define REG_ARFR1_V1 0x044C -#define REG_CCK_CHECK 0x0454 +#define REG_TQPNT6 0x0264 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AMPDU_BURST_CTRL 0x0455 +#define REG_DMA_OQT_1 0x0264 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_AMPDU_MAX_TIME_V1 0x0455 +#define REG_FIFOPAGE_INFO_6 0x0268 +#define REG_FIFOPAGE_INFO_7 0x026C #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AMPDU_MAX_TIME 0x0456 +#define REG_PGSUB_CNT 0x026C +#define REG_PGSUB_H 0x0270 +#define REG_PGSUB_N 0x0274 +#define REG_PGSUB_L 0x0278 +#define REG_PGSUB_E 0x027C #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BCNQ1_BDNY_V1 0x0456 +#define REG_RXDMA_AGG_PG_TH 0x0280 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BCNQ1_BDNY 0x0457 +#define REG_RXPKT_NUM 0x0284 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_AMPDU_MAX_LENGTH 0x0458 -#define REG_ACQ_STOP 0x045C +#define REG_RXDMA_CTRL 0x0284 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WMAC_LBK_BUF_HD 0x045D +#define REG_RXDMA_STATUS 0x0288 +#define REG_RXDMA_DPR 0x028C +#define REG_RXDMA_MODE 0x0290 +#define REG_C2H_PKT 0x0294 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_NDPA_RATE 0x045D +#define REG_FWFF_C2H 0x0298 +#define REG_FWFF_CTRL 0x029C +#define REG_FWFF_PKT_INFO 0x02A0 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TX_HANG_CTRL 0x045E -#define REG_NDPA_OPT_CTRL 0x045F +#define REG_FC2H_INFO 0x02A4 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_FAST_EDCA_CTRL 0x0460 +#define REG_FWFF_PKT_INFO2 0x02A4 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RXPKTNUM 0x02B0 +#define REG_RXPKTNUM_TH 0x02B4 + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define REG_RD_RESP_PKT_TH 0x0463 -#define REG_CMDQ_INFO 0x0464 -#define REG_Q4_INFO 0x0468 -#define REG_Q5_INFO 0x046C -#define REG_Q6_INFO 0x0470 -#define REG_Q7_INFO 0x0474 +#define REG_FW_UPD_RXDES_RDPTR 0x02B8 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FW_MSG1 0x02E0 +#define REG_FW_MSG2 0x02E4 +#define REG_FW_MSG3 0x02E8 +#define REG_FW_MSG4 0x02EC + +#endif -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define REG_WMAC_LBK_BUF_HD_V1 0x0478 -#define REG_MGQ_BDNY_V1 0x047A +#define REG_PCIE_CTRL 0x0300 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) +#define REG_HCI_CTRL 0x0300 + +#endif + +#if (HALMAC_8881A_SUPPORT) -#define REG_TXRPT_CTRL 0x047C -#define REG_INIRTS_RATE_SEL 0x0480 -#define REG_BASIC_CFEND_RATE 0x0481 -#define REG_STBC_CFEND_RATE 0x0482 -#define REG_DATA_SC 0x0483 -#define REG_MACID_SLEEP3 0x0484 -#define REG_MACID_SLEEP1 0x0488 -#define REG_ARFR2_V1 0x048C -#define REG_ARFR3_V1 0x0494 -#define REG_ARFR4 0x049C -#define REG_ARFR5 0x04A4 -#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_LX_CTRL1 0x0300 #endif +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_INT_MIG 0x0304 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH_CTRL 0x0304 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCNQ_TXBD_DESA 0x0308 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_HIQ_CTRL 0x0308 +#define REG_INT_MIG_V1 0x030C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MGQ_TXBD_DESA 0x0310 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0MGQ_TXBD_DESA_L 0x0310 +#define REG_P0MGQ_TXBD_DESA_H 0x0314 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_VOQ_TXBD_DESA 0x0318 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH0_TXBD_DESA_L 0x0318 +#define REG_ACH0_TXBD_DESA_H 0x031C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_VIQ_TXBD_DESA 0x0320 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH1_TXBD_DESA_L 0x0320 +#define REG_ACH1_TXBD_DESA_H 0x0324 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BEQ_TXBD_DESA 0x0328 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH2_TXBD_DESA_L 0x0328 +#define REG_ACH2_TXBD_DESA_H 0x032C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BKQ_TXBD_DESA 0x0330 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH3_TXBD_DESA_L 0x0330 +#define REG_ACH3_TXBD_DESA_H 0x0334 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RXQ_RXBD_DESA 0x0338 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0RXQ_RXBD_DESA_L 0x0338 +#define REG_P0RXQ_RXBD_DESA_H 0x033C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI0Q_TXBD_DESA 0x0340 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0BCNQ_TXBD_DESA_L 0x0340 +#define REG_P0BCNQ_TXBD_DESA_H 0x0344 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI1Q_TXBD_DESA 0x0348 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_FWCMDQ_TXBD_DESA_L 0x0348 +#define REG_FWCMDQ_TXBD_DESA_H 0x034C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI2Q_TXBD_DESA 0x0350 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_HRPWM1_HCPWM1_DCPU 0x0354 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI3Q_TXBD_DESA 0x0358 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0_MPRT_BCNQ_TXBD_DESA_L 0x0358 +#define REG_P0_MPRT_BCNQ_TXBD_DESA_H 0x035C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI4Q_TXBD_DESA 0x0360 +#define REG_HI5Q_TXBD_DESA 0x0368 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0_MPRT_BCNQ_TXRXBD_NUM 0x036C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI6Q_TXBD_DESA 0x0370 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_BD_RWPTR_CLR2 0x0370 +#define REG_BD_RWPTR_CLR3 0x0374 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI7Q_TXBD_DESA 0x0378 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0MGQ_RXQ_TXRXBD_NUM 0x0378 +#define REG_CHNL_DMA_CFG 0x037C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MGQ_TXBD_NUM 0x0380 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_FWCMDQ_TXBD_NUM 0x0380 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RX_RXBD_NUM 0x0382 +#define REG_VOQ_TXBD_NUM 0x0384 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH0_ACH1_TXBD_NUM 0x0384 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_VIQ_TXBD_NUM 0x0386 +#define REG_BEQ_TXBD_NUM 0x0388 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH2_ACH3_TXBD_NUM 0x0388 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BKQ_TXBD_NUM 0x038A +#define REG_HI0Q_TXBD_NUM 0x038C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI0Q_HI1Q_TXBD_NUM 0x038C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI1Q_TXBD_NUM 0x038E +#define REG_HI2Q_TXBD_NUM 0x0390 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI2Q_HI3Q_TXBD_NUM 0x0390 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI3Q_TXBD_NUM 0x0392 +#define REG_HI4Q_TXBD_NUM 0x0394 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI4Q_HI5Q_TXBD_NUM 0x0394 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI5Q_TXBD_NUM 0x0396 +#define REG_HI6Q_TXBD_NUM 0x0398 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI6Q_HI7Q_TXBD_NUM 0x0398 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI7Q_TXBD_NUM 0x039A + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TSFTIMER_HCI 0x039C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BD_RWPTR_CLR 0x039C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_BD_RWPTR_CLR1 0x039C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_VOQ_TXBD_IDX 0x03A0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH0_TXBD_IDX 0x03A0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_VIQ_TXBD_IDX 0x03A4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH1_TXBD_IDX 0x03A4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BEQ_TXBD_IDX 0x03A8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH2_TXBD_IDX 0x03A8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BKQ_TXBD_IDX 0x03AC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACH3_TXBD_IDX 0x03AC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MGQ_TXBD_IDX 0x03B0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0MGQ_TXBD_IDX 0x03B0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RXQ_RXBD_IDX 0x03B4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0RXQ_RXBD_IDX 0x03B4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI0Q_TXBD_IDX 0x03B8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI0Q_TXBD_IDX 0x03B8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI1Q_TXBD_IDX 0x03BC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI1Q_TXBD_IDX 0x03BC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI2Q_TXBD_IDX 0x03C0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI2Q_TXBD_IDX 0x03C0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI3Q_TXBD_IDX 0x03C4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI3Q_TXBD_IDX 0x03C4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI4Q_TXBD_IDX 0x03C8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI4Q_TXBD_IDX 0x03C8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI5Q_TXBD_IDX 0x03CC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI5Q_TXBD_IDX 0x03CC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI6Q_TXBD_IDX 0x03D0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI6Q_TXBD_IDX 0x03D0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HI7Q_TXBD_IDX 0x03D4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_P0HI7Q_TXBD_IDX 0x03D4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_DBG_SEL_V1 0x03D8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1 0x03D8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PCIE_HRPWM1_V1 0x03D9 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_HRPWM1_V1 0x03D9 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PCIE_HCPWM1_V1 0x03DA + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_HCPWM1_V1 0x03DA + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_PCIE_CTRL2 0x03DB + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_CTRL2 0x03DB + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_LX_CTRL2 0x03DB + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PCIE_HRPWM2_V1 0x03DC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_HRPWM2_V1 0x03DC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_HRPWM2_HCPWM2_V1 0x03DC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PCIE_HCPWM2_V1 0x03DE + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_HCPWM2_V1 0x03DE + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_PCIE_H2C_MSG_V1 0x03E0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_H2C_MSG_V1 0x03E0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_PCIE_C2H_MSG_V1 0x03E4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_HCI_C2H_MSG_V1 0x03E4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DBI_WDATA_V1 0x03E8 + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_LX_DMA_ISR 0x03E8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DBI_RDATA_V1 0x03EC + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_LX_DMA_IMR 0x03EC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DBI_FLAG_V1 0x03F0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_STUCK_FLAG_V1 0x03F0 + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_LX_DMA_DBG 0x03F0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MDIO_V1 0x03F4 + +#endif + +#if (HALMAC_8192E_SUPPORT) + +#define REG_MDIO2_V1 0x03F8 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_PCIE_MIX_CFG 0x03F8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_WDT_CFG 0x03F8 + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_BUS_MIX_CFG 0x03F8 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_HCI_MIX_CFG 0x03FC + +#endif + +#if (HALMAC_8881A_SUPPORT) + +#define REG_BUS_MIX_CFG1 0x03FC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q0_INFO 0x0400 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_INFO0 0x0400 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_QUEUE_INFO1 0x0400 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q1_INFO 0x0404 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_INFO1 0x0404 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_QUEUE_INFO2 0x0404 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q2_INFO 0x0408 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_QUEUE_INFO3 0x0408 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_INFO2 0x0408 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q3_INFO 0x040C + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_QINFO_INDEX 0x040C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_INFO3 0x040C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MGQ_INFO 0x0410 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_QUEUE_EMPTY 0x0410 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_INFO_EMPTY 0x0410 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HIQ_INFO 0x0414 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_QUEUELIST_INFO2_V1 0x0414 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ACQ_STOP_V1 0x0414 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_QUEUELIST_ACQ_EN 0x0414 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCNQ_INFO 0x0418 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_TXPKT_EMPTY_V1 0x0418 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_BCNQ_BDNY_V2 0x0418 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TXPKT_EMPTY 0x041A + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_CPU_MGQ_INFO 0x041C +#define REG_FWHW_TXQ_CTRL 0x0420 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HWSEQ_CTRL 0x0423 + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DATAFB_SEL 0x0423 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCNQ_BDNY 0x0424 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BCNQ_BDNY_V1 0x0424 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TXBDNY 0x0424 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MGQ_BDNY 0x0425 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_LIFETIME_EN 0x0426 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_FW_FREE_TAIL 0x0427 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_SPEC_SIFS 0x0428 +#define REG_RETRY_LIMIT 0x042A +#define REG_TXBF_CTRL 0x042C +#define REG_DARFRC 0x0430 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DARFRCH 0x0434 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RARFRC 0x0438 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RARFRCH 0x043C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RRSR 0x0440 +#define REG_ARFR0 0x0444 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ARFRH0 0x0448 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ARFR1_V1 0x044C + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_ARFR1 0x044C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_REG_ARFR_WT0 0x044C + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_ARFRH1 0x0450 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ARFRH1_V1 0x0450 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_REG_ARFR_WT1 0x0450 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_CCK_CHECK 0x0454 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_AMPDU_BURST_CTRL 0x0455 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_BCNQ2_HEAD 0x0455 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_AMPDU_MAX_TIME_V1 0x0455 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_AMPDU_MAX_TIME 0x0456 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BCNQ1_BDNY_V1 0x0456 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TAB_SEL 0x0456 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCNQ1_BDNY 0x0457 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_BCN_INVALID_CTRL 0x0457 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_AMPDU_MAX_LENGTH 0x0458 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_AMPDU_MAX_LENGTH_HT 0x0458 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ACQ_STOP 0x045C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WMAC_LBK_BUF_HD 0x045D + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NDPA_RATE 0x045D + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TX_HANG_CTRL 0x045E +#define REG_NDPA_OPT_CTRL 0x045F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_FAST_EDCA_CTRL 0x0460 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_AMPDU_MAX_LENGTH_VHT 0x0460 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RD_RESP_PKT_TH 0x0463 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_CMDQ_INFO 0x0464 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_NEW_EDCA_CTRL_V1 0x0464 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q4_INFO 0x0468 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ACQ_STOP_V2 0x0468 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_Q5_INFO 0x046C +#define REG_Q6_INFO 0x0470 +#define REG_Q7_INFO 0x0474 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_LBK_BUF_HD_V1 0x0478 +#define REG_MGQ_BDNY_V1 0x047A + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TXRPT_CTRL 0x047C +#define REG_INIRTS_RATE_SEL 0x0480 +#define REG_BASIC_CFEND_RATE 0x0481 +#define REG_STBC_CFEND_RATE 0x0482 +#define REG_DATA_SC 0x0483 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MACID_SLEEP3 0x0484 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MOREDATA_V1 0x0484 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_MACID_SLEEP4 0x0485 +#define REG_MACID_SLEEP5 0x0487 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_DATA_SC1 0x0487 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MACID_SLEEP1 0x0488 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ARFR2_V1 0x048C + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_ARFR2 0x048C +#define REG_ARFRH2 0x0490 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ARFRH2_V1 0x0490 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ARFR3_V1 0x0494 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_ARFR3 0x0494 +#define REG_ARFRH3 0x0498 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ARFRH3_V1 0x0498 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ARFR4 0x049C + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_ARFRH4 0x04A0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ARFR5 0x04A4 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_ARFRH5 0x04A8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TXRPT_START_OFFSET 0x04AC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TRYING_CNT_TH 0x04B0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_TRY_CNT_IDX 0x04B0 + +#endif + +#if (HALMAC_8812F_SUPPORT) + +#define REG_RRSR_CTS 0x04B0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_POWER_STAGE1 0x04B4 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_POWER_STAGE2 0x04B8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC +#define REG_PKT_LIFE_TIME 0x04C0 +#define REG_STBC_SETTING 0x04C4 +#define REG_STBC_SETTING2 0x04C5 +#define REG_QUEUE_CTRL 0x04C6 +#define REG_SINGLE_AMPDU_CTRL 0x04C7 +#define REG_PROT_MODE_CTRL 0x04C8 +#define REG_BAR_MODE_CTRL 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT 0x04CF + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MACID_SLEEP2 0x04D0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MACID_SLEEP_CTRL 0x04D0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MACID_SLEEP 0x04D4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MACID_SLEEP_INFO 0x04D4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_HW_SEQ0 0x04D8 +#define REG_HW_SEQ1 0x04DA +#define REG_HW_SEQ2 0x04DC +#define REG_HW_SEQ3 0x04DE + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +#define REG_CSI_SEQ 0x04DE + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NULL_PKT_STATUS 0x04E0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NULL_PKT_STATUS_V1 0x04E0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_PTCL_ERR_STATUS 0x04E2 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) + +#define REG_PTCL_ERR_STATUS_V1 0x04E2 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PTCL_PKT_NUM 0x04E3 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NULL_PKT_STATUS_EXTEND 0x04E3 + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +#define REG_TRXRPT_MISS_CNT 0x04E3 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_HQMGQ_DROP 0x04E4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_NULL_PKT_STATUS_V2 0x04E4 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_PRECNT_CTRL 0x04E5 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_NULL_PKT_STATUS_EXTEND_V1 0x04E7 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_BT_POLLUTE_PKTCNT_V1 0x04E8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_POLLUTE_PKT_CNT 0x04E8 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_DROP_PKT_NUM 0x04EC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_PTCL_DBG 0x04EC + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_DROP_NUM 0x04EC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PTCL_DBG_V1 0x04EC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PTCL_TX_RPT 0x04F0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_TX_RPT_INFO_L32 0x04F0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_TXOP_EXTRA_CTRL 0x04F0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_BT_POLLUTE_PKTCNT 0x04F0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_TX_RPT_INFO_H32 0x04F4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_CPUMGQ_TIMER_CTRL2 0x04F4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PTCL_DBG_OUT 0x04F8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_DUMMY_PAGE4 0x04FC + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_DUMMY_PAGE4_V1 0x04FC + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8814B_SUPPORT) + +#define REG_DUMMY_PAGE4_1 0x04FE + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MOREDATA 0x04FE + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050C +#define REG_BCNTCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS 0x0514 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TSFTR_SYN_OFFSET 0x0518 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_FORCE_BCN_IFS_V1 0x0518 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_AGGR_BREAK_TIME 0x051A +#define REG_SLOT 0x051B + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_NOA_ON_ERLY_TIME 0x051C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_EDCA_CPUMGQ_PARAM 0x051C + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_NOA_OFF_ERLY_TIME 0x051D + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_CPUMGQ_PAUSE 0x051E + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_PS_TIMER_CTRL 0x051F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MBSSID_CTRL 0x0526 +#define REG_P2PPS_CTRL 0x0527 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PKT_LIFETIME_CTRL 0x0528 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_P2PPS_SPEC_STATE 0x052B + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_P2PPS0_SPEC_STATE 0x052B + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_PS_TIMER_A_V2 0x052C + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_TXOP_LIMIT_CTRL 0x052C + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BAR_TX_CTRL 0x0530 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_P2PON_DIS_TXTIME 0x0531 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_PS_TIMER_B_V2 0x0534 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_CCA_TXEN_CNT 0x0534 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_QUEUE_INCOL_THR 0x0538 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MAX_INTER_COLLISION 0x0538 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_QUEUE_INCOL_EN 0x053C + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MAX_INTER_COLLISION_CNT 0x053C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_P2PPS_STATE 0x0543 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_FTM_SETTING 0x0548 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_FTM_CTRL 0x0548 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FTM_PTT 0x0548 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_FTM_TSF_CNT 0x054C + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FTM_TSF 0x054C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCN_CTRL 0x0550 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCN_CTRL1 0x0551 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BCN_CTRL_CLINT0 0x0551 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define REG_MBSSID_BCN_SPACE 0x0554 +#define REG_DRVERLYINT 0x0558 +#define REG_BCNDMATIM 0x0559 +#define REG_ATIMWND 0x055A +#define REG_USTIME_TSF 0x055C +#define REG_BCN_MAX_ERR 0x055D +#define REG_RXTSF_OFFSET_CCK 0x055E +#define REG_RXTSF_OFFSET_OFDM 0x055F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_TSFTR 0x0560 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_TSFTR0_L 0x0560 +#define REG_TSFTR0_H 0x0564 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_TSFTR_1 0x0564 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TSFTR1 0x0568 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_TSFTR1_L 0x0568 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FREERUN_CNT 0x0568 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_TSFTR1_H 0x056C + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FREERUN_CNT_1 0x056C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND1 0x0570 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_ATIMWND1_V1 0x0570 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_TBTT_PROHIBIT_INFRA 0x0571 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_CTWND 0x0572 +#define REG_BCNIVLCUNT 0x0573 +#define REG_BCNDROPCTRL 0x0574 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_HGQ_TIMEOUT_PERIOD 0x0575 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_TXCMD_TIMEOUT_PERIOD 0x0576 +#define REG_MISC_CTRL 0x0577 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_TSFTR2_L 0x0578 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BCN_CTRL_CLINT1 0x0578 +#define REG_BCN_CTRL_CLINT2 0x0579 +#define REG_BCN_CTRL_CLINT3 0x057A + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_EXTEND_CTRL 0x057B + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_TSFTR2_H 0x057C + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_P2PPS1_SPEC_STATE 0x057C +#define REG_P2PPS1_STATE 0x057D +#define REG_P2PPS2_SPEC_STATE 0x057E +#define REG_P2PPS2_STATE 0x057F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PS_TIMER 0x0580 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_PS_TIMER0 0x0580 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TIMER0 0x0584 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_PS_TIMER1 0x0584 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TIMER1 0x0588 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_PS_TIMER2 0x0588 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TBTT_CTN_AREA 0x058C +#define REG_FORCE_BCN_IFS 0x058E + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_DRVERLYINT_V1 0x058F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TXOP_MIN 0x0590 +#define REG_PRE_BKF_TIME 0x0592 +#define REG_CROSS_TXOP_CTRL 0x0593 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_FREERUN_CNT_L 0x0594 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_TBTT_INT_SHIFT_CLI0 0x0594 +#define REG_TBTT_INT_SHIFT_CLI1 0x0595 +#define REG_TBTT_INT_SHIFT_CLI2 0x0596 +#define REG_TBTT_INT_SHIFT_CLI3 0x0597 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_FREERUN_CNT_H 0x0598 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_TBTT_INT_SHIFT_ENABLE 0x0598 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RX_TBTT_SHIFT_V1 0x0598 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND2 0x05A0 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ATIMWND_GROUP1 0x05A0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND3 0x05A1 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ATIMWND_GROUP2 0x05A1 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND4 0x05A2 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ATIMWND_GROUP3 0x05A2 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND5 0x05A3 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ATIMWND_GROUP4 0x05A3 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND6 0x05A4 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_DTIM_COUNT_GROUP1 0x05A4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ATIMWND7 0x05A5 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_DTIM_COUNT_GROUP2 0x05A5 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_ATIMUGT 0x05A6 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_DTIM_COUNT_GROUP3 0x05A6 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_HIQ_NO_LMT_EN 0x05A7 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_DTIM_COUNT_GROUP4 0x05A7 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_DTIM_COUNTER_ROOT 0x05A8 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_HIQ_NO_LMT_EN_V2 0x05A8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_DTIM_COUNTER_VAP1 0x05A9 +#define REG_DTIM_COUNTER_VAP2 0x05AA +#define REG_DTIM_COUNTER_VAP3 0x05AB +#define REG_DTIM_COUNTER_VAP4 0x05AC + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_MBID_BCNQ_EN 0x05AC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_DTIM_COUNTER_VAP5 0x05AD +#define REG_DTIM_COUNTER_VAP6 0x05AE +#define REG_DTIM_COUNTER_VAP7 0x05AF +#define REG_DIS_ATIM 0x05B0 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_EARLY_128US 0x05B1 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_TBTT_HOLD_PREDICT_P1 0x05B2 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_P2PPS1_CTRL 0x05B2 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_MULTI_BCN_CS 0x05B3 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_P2PPS2_CTRL 0x05B3 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_TSFT_SHIFT 0x05B4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_TIMER0_SRC_SEL 0x05B4 +#define REG_NOA_UNIT_SEL 0x05B5 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_P2POFF_DIS_TXTIME 0x05B7 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MBSSID_BCN_SPACE2 0x05B8 +#define REG_MBSSID_BCN_SPACE3 0x05BC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ACMHWCTRL 0x05C0 +#define REG_ACMRSTCTRL 0x05C1 +#define REG_ACMAVG 0x05C2 +#define REG_VO_ADMTIME 0x05C4 +#define REG_VI_ADMTIME 0x05C6 +#define REG_BE_ADMTIME 0x05C8 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MAC_HEADER_NAV_OFFSET 0x05CA +#define REG_DIS_NDPA_NAV_CHECK 0x05CB + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_EDCA_RANDOM_GEN 0x05CC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TXCMD_NOA_SEL 0x05CF + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TXCMD_SEL 0x05CF + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_DRVERLYINT2 0x05D0 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_32K_CLK_SEL 0x05D0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_NAN_SETTING 0x05D4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_EARLYINT_ADJUST 0x05D4 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_NAN_BCNSPACE 0x05D8 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BCNERR_CNT 0x05D8 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_NAN_SETTING1 0x05DC + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BCNERR_CNT_2 0x05DC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NOA_PARAM 0x05E0 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_NOA_PARAM_1 0x05E4 +#define REG_NOA_PARAM_2 0x05E8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MU_DBG_INFO 0x05E8 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_NOA_PARAM_3 0x05EC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MU_DBG_INFO_1 0x05EC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NOA_SUBIE 0x05ED + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_P2P_RST 0x05F0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_SCH_DBG_SEL 0x05F0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SCHEDULER_RST 0x05F1 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_MU_DBG_ERR_FLAG 0x05F2 +#define REG_TX_ERR_RECOVERY_RST 0x05F3 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_SCH_DBG 0x05F4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SCH_DBG_VALUE 0x05F4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_SCH_TXCMD 0x05F8 +#define REG_PAGE5_DUMMY 0x05FC +#define REG_WMAC_CR 0x0600 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_FWPKT_CR 0x0601 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_FW_STS_FILTER 0x0602 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_WMAC_BWOPMODE 0x0603 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_BWOPMODE 0x0603 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TCR 0x0604 +#define REG_RCR 0x0608 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RX_PKT_LIMIT 0x060C + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_RXPKT_LIMIT 0x060C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RX_DLK_TIME 0x060D + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_SDIO_RXINT_LEN_TH 0x1025060E + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RX_DRVINFO_SZ 0x060F +#define REG_MACID 0x0610 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MACID_H 0x0614 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BSSID 0x0618 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BSSID_H 0x061C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MAR 0x0620 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MAR_H 0x0624 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MBIDCAMCFG_1 0x0628 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_MBIDCAMCFG_2 0x062C + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_MBIDCAM_CFG 0x062C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_WMAC_DEBUG_SEL 0x062C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MCU_TEST_1 0x0630 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_TCR_TSFT_OFS 0x0630 +#define REG_UDF_THSD 0x0632 +#define REG_ZLD_NUM 0x0633 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MCU_TEST_2 0x0634 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_STMP_THSD 0x0634 +#define REG_WMAC_TXTIMEOUT 0x0635 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) + +#define REG_MCU_TEST_2_V1 0x0636 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_USTIME_EDCA 0x0638 + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ACKTO_CCK 0x0639 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MAC_SPEC_SIFS 0x063A +#define REG_RESP_SIFS_CCK 0x063C +#define REG_RESP_SIFS_OFDM 0x063E +#define REG_ACKTO 0x0640 +#define REG_CTS2TO 0x0641 +#define REG_EIFS 0x0642 + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RPFM_MAP0 0x0644 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_RPFM_MAP1 0x0646 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RPFM_MAP1_V1 0x0646 + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RPFM_CAM_CMD 0x0648 +#define REG_RPFM_CAM_RWD 0x064C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NAV_CTRL 0x0650 +#define REG_BACAMCMD 0x0654 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BACAMCONTENT 0x0658 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_BACAM_WD 0x0658 +#define REG_BACAM_WD_H 0x065C + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BACAMCONTENT_H 0x065C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_LBDLY 0x0660 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_LBK_DLY 0x0660 +#define REG_BITMAP_CMD 0x0661 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_BACAM_RPMEN 0x0661 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_TX_RX 0x0662 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_BITMAP_CTL 0x0663 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RXERR_RPT 0x0664 +#define REG_WMAC_TRXPTCL_CTL 0x0668 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_TRXPTCL_CTL_H 0x066C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_CAMCMD 0x0670 +#define REG_CAMWRITE 0x0674 +#define REG_CAMREAD 0x0678 +#define REG_CAMDBG 0x067C +#define REG_SECCFG 0x0680 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RXFILTER_CATEGORY_1 0x0682 +#define REG_RXFILTER_ACTION_1 0x0683 +#define REG_RXFILTER_CATEGORY_2 0x0684 +#define REG_RXFILTER_ACTION_2 0x0685 +#define REG_RXFILTER_CATEGORY_3 0x0686 +#define REG_RXFILTER_ACTION_3 0x0687 +#define REG_RXFLTMAP3 0x0688 +#define REG_RXFLTMAP4 0x068A +#define REG_RXFLTMAP5 0x068C +#define REG_RXFLTMAP6 0x068E + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WOW_CTRL 0x0690 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NAN_RX_TSF_FILTER 0x0691 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_PS_RX_INFO 0x0692 +#define REG_WMMPS_UAPSD_TID 0x0693 +#define REG_LPNAV_CTRL 0x0694 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WKFMCAM_NUM 0x0698 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_WKFMCAM_CMD 0x0698 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WKFMCAM_RWD 0x069C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RXFLTMAP0 0x06A0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_RXFLTER0 0x06A0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RXFLTMAP1 0x06A2 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_RXFLTER1 0x06A2 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RXFLTMAP 0x06A4 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_RXFLTER2 0x06A4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RXFLTMAP2 0x06A4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCN_PSR_RPT 0x06A8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_FLC_RPC 0x06AC +#define REG_FLC_RPCT 0x06AD +#define REG_FLC_PTS 0x06AE +#define REG_FLC_TRPC 0x06AF + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RXPKTMON_CTRL 0x06B0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_STATE_MON 0x06B4 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_ERROR_EVT_CTL 0x06B8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ERROR_MON 0x06B8 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_RESPINFO 0x06BC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SEARCH_MACID 0x06BC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_COEX_TABLE 0x06C0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_BT_COEX_TABLE_V1 0x06C0 +#define REG_BT_COEX_TABLE2_V1 0x06C4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BT_COEX_TABLE2 0x06C4 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_COEX_BREAK_TABLE 0x06C8 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_BT_COEX_TABLE_H_V1 0x06CC + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BT_COEX_TABLE_H 0x06CC + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RXCMD_0 0x06D0 +#define REG_RXCMD_1 0x06D4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WMAC_RESP_TXINFO 0x06D8 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_RESP_TXINFO_CFG 0x06D8 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BBPSF_CTRL 0x06DC + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_RESP_TXINFO_RATE 0x06DE + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_P2P_RX_BCN_NOA 0x06E0 +#define REG_ASSOCIATED_BFMER0_INFO 0x06E4 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_SOUNDING_CFG1 0x06E8 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_ASSOCIATED_BFMER0_INFO_H 0x06E8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ASSOCIATED_BFMER1_INFO 0x06EC + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_SOUNDING_CFG2 0x06EC +#define REG_SOUNDING_CFG3 0x06F0 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_ASSOCIATED_BFMER1_INFO_H 0x06F0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_SOUNDING_CFG0 0x06F4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_ANTCD_INFO 0x06F8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8881A_SUPPORT) + +#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_CSI_RRSR_V1 0x06FC + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_CSI_PTR 0x06FC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_MACID1 0x0700 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MACID1_1 0x0704 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BSSID1 0x0708 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_FORCE_LINK_L 0x0709 +#define REG_PCIE_CFG_FORCE_LINK_H 0x070A + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BSSID1_1 0x070C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0x070C +#define REG_PCIE_CFG_CX_NFTS 0x070D +#define REG_PCIE_CFG_DEFAULT_ENTR_LATENCY 0x070F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BCN_PSR_RPT1 0x0710 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_L1_MISC_SEL 0x0711 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ASSOCIATED_BFMEE_SEL 0x0714 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_ASSOCIATED_BFMEE_SEL_1 0x0714 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_SND_PTCL_CTRL 0x0718 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x0718 +#define REG_PCIE_CFG_FORCE_CLKREQ_N_PAD 0x0719 +#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY 0x071A +#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG 0x071B + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_RX_CSI_RPT_INFO 0x071C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_L 0x071C +#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_H 0x071D + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_RX_CSI_RPT_INFO_H 0x071F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NS_ARP_CTRL 0x0720 +#define REG_NS_ARP_INFO 0x0724 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_CFG_L1_UNIT_SEL 0x0724 +#define REG_PCIE_CFG_MIN_CLKREQ_SEL 0x0725 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NS_ARP_IPADDR 0x0728 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_PWR_INT_CTRL 0x0728 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WRITE_RX_CSI_RPT_INFO 0x072C + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_RX_CSI_RPT_INFO_V1 0x072C + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BEAMFORMING_INFO_NSARP 0x072C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_NS_ARP_IPV6_MYADDR 0x0730 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_POWER_MGT_0_V1 0x0730 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_IPV6 0x0730 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_POWER_MGT_1_V1 0x0734 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_IPV6_1 0x0734 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_POWER_MGT_2_V1 0x0738 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_IPV6_2 0x0738 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_POWER_MGT_3_V1 0x073C + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_IPV6_3 0x073C + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_PLCP_HEADER 0x0740 +#define REG_TXDRXDMONITOR 0x0744 +#define REG_TXDRXDMONITOR_CTL 0x0748 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_WMAC_SWAES_RD0_V1 0x0754 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_SWAES_DIO_B63_B32 0x0754 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_WMAC_SWAES_RD1_V1 0x0758 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_SWAES_DIO_B95_B64 0x0758 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_WMAC_SWAES_RD3_V1 0x075C + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_SWAES_DIO_B127_B96 0x075C + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_SWAES_CFG 0x0760 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BT_COEX_V2 0x0762 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_COEX 0x0764 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WLAN_ACT_MSK_CTRL 0x0768 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_WLAN_ACT_MASK_CTRL 0x0768 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WLAN_ACT_MASK_CTRL_1 0x076C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_STATISTICS_CTRL 0x076E +#define REG_BT_COEX_ENH_INTF_CTRL 0x076E + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_ACT_STATISTICS 0x0770 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_ACT_STATISTICS_1 0x0774 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_STATISTICS_OTH_CTRL 0x0778 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_CMD_ID 0x077C + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BT_STATUS_REPORT_REGISTER 0x077C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT__STATUS_RPT 0x077D +#define REG_BT_DATA 0x0780 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WLAN_RPT_ 0x0781 +#define REG_BT_ISR_CTRL 0x0783 +#define REG_WLAN_RPT_TO_CTR 0x0784 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_ISOLATION_TABLE 0x0785 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 0x0788 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 0x078C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_ISR_STA 0x078F + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_TDMA_TIME_AND_RPT_SAM_SET 0x0790 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BT_TDMA_TIME_REGISTER 0x0790 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_CH_INFO 0x0794 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_BT_ACT_REGISTER 0x0794 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_BT_STATIC_INFO_EXT 0x0795 +#define REG_LTR_IDLE_LATENCY 0x0798 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_LTR_IDLE_LATENCY_V2 0x0798 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_OBFF_CTRL_BASIC 0x0798 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_LTR_ACTIVE_LATENCY 0x079C + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_LTR_ACTIVE_LATENCY_V2 0x079C + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_OBFF_CTRL2_TIMER 0x079C + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_OBFF_CTRL 0x07A0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_LTR_CTRL_BASIC 0x07A0 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_LTR_CTRL 0x07A4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_LTR_CTRL2 0x07A8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_LTR_IDLE_LATENCY_V1 0x07A8 +#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_ANTTRN_CTRL 0x07B0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_ANTTRN_CTR_V1 0x07B0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_SMART_ANT_CONDITION 0x07B0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_ANTTRN_CTR 0x07B4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 0x07B4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_SMART_ANT_CTRL 0x07B4 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WMAC_PKTCNT_RWD 0x07B8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_CONTROL_FRAME_REPORT 0x07B8 + +#endif + +#if (HALMAC_8192E_SUPPORT || HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT) + +#define REG_WMAC_PKTCNT_CTRL 0x07BC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_CONTROL_FRAME_CNT_CTRL 0x07BC + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL 0x07C0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_IQ_DUMP 0x07C0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA 0x07C4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_IQ_DUMP_1 0x07C4 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA 0x07C8 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_IQ_DUMP_2 0x07C8 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_FTM_CTL 0x07CC + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_IQ_MDPK_FUNC 0x07CE + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_IQ_DUMP_EXT 0x07CF + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) + +#define REG_OFDM_CCK_LEN_MASK 0x07D0 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_WMAC_OPTION_FUNCTION 0x07D0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_FA_FILTER1 0x07D4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_WMAC_OPTION_FUNCTION_1 0x07D4 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_FA_FILTER2 0x07D8 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_WMAC_OPTION_FUNCTION_2 0x07D8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RX_FILTER_FUNCTION 0x07DA + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_NAN_FUN 0x07DC +#define REG_NAN_CTL 0x07E0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_NDP_SIG 0x07E0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_RX_NAN_ADDR_FILTER 0x07E4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_NAN_ADDR 0x07E8 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_TXCMD_INFO_FOR_RSP_PKT_1 0x07E8 + +#endif + +#if (HALMAC_8814AMP_SUPPORT) + +#define REG_SEC_OPT 0x07E8 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_RXA1_MASK 0x07EC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_SEC_OPT_V2 0x07EC + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_WSEC_OPTION 0x07EC + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_DUMP_FUNC 0x07F0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RTS_ADDRESS_0 0x07F0 + +#endif + +#if (HALMAC_8814AMP_SUPPORT) + +#define REG_RTS_ADDR0 0x07F0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_MASK_LA_MAC 0x07F4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RTS_ADDRESS_0_1 0x07F4 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_MATCH_REF_MAC 0x07F8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RTS_ADDRESS_1 0x07F8 + +#endif + +#if (HALMAC_8814AMP_SUPPORT) + +#define REG_RTS_ADDR1 0x07F8 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_LA_DUMP_FUNC_EXT 0x07FC + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RTS_ADDRESS_1_1 0x07FC + +#endif + +#if (HALMAC_8822B_SUPPORT) + +#define REG__RPFM_MAP1 0x07FE + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SYS_CFG3 0x1000 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ANAPARSW_MAC_0 0x1010 +#define REG_ANAPARSW_MAC_1 0x1014 +#define REG_ANAPAR_MAC_0 0x1018 +#define REG_ANAPAR_MAC_1 0x101C +#define REG_ANAPAR_MAC_2 0x1020 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ANAPAR_MAC_3 0x1024 +#define REG_ANAPAR_MAC_4 0x1028 +#define REG_ANAPAR_MAC_5 0x102C +#define REG_ANAPAR_MAC_6 0x1030 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_SYS_CFG4 0x1034 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ANAPAR_MAC_7 0x1034 +#define REG_ANAPAR_MAC_8 0x1038 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ANAPAR_XTAL_0 0x1040 +#define REG_ANAPAR_XTAL_1 0x1044 +#define REG_ANAPAR_XTAL_2 0x1048 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ANAPAR_XTAL_3 0x104C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_ANAPAR_XTAL_AAC 0x104C +#define REG_ANAPAR_XTAL_R_ONLY 0x1050 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ANAPAR_XTAL_AACK_0 0x1054 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_CPHY_LDO 0x1054 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ANAPAR_XTAL_AACK_1 0x1058 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_CPHY_BG 0x1058 +#define REG_HIMR_4 0x1060 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_ANAPAR_XTAL_MODE_DECODER 0x1064 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_HISR_4 0x1064 +#define REG_HIMR_5 0x1068 +#define REG_HISR_5 0x106C + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_SYS_CFG5 0x1070 + +#endif + +#if (HALMAC_8812F_SUPPORT) + +#define REG_REGU_32K_1 0x1078 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_HIMR_6 0x1078 + +#endif + +#if (HALMAC_8812F_SUPPORT) + +#define REG_REGU_32K_2 0x107C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_HISR_6 0x107C + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_CPU_DMEM_CON 0x1080 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_BOOT_REASON 0x1088 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_HIMR4 0x1090 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_DATA_CPU_CTL0 0x1090 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_HISR4 0x1094 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_DATA_CPU_CTL1 0x1094 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_HIMR5 0x1098 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TXDMA_STOP_HIMR 0x1098 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_HISR5 0x109C + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TXDMA_STOP_HISR 0x109C +#define REG_TXDMA_START_HIMR 0x10A0 +#define REG_TXDMA_START_HISR 0x10A4 + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_NFCPAD_CTRL 0x10A8 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_HIMR2 0x10B0 +#define REG_HISR2 0x10B4 +#define REG_HIMR3 0x10B8 +#define REG_HISR3 0x10BC +#define REG_SW_MDIO 0x10C0 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_SW_FLUSH 0x10C4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_DBG_GPIO_BMUX 0x10C8 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_HIMR_7 0x10C8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_FPGA_TAG 0x10CC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_HISR_7 0x10CC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_WL_DSS_CTRL0 0x10D0 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_H2C_PKT_READADDR 0x10D0 + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define REG_WL_DSS_STATUS0 0x10D4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_H2C_PKT_WRITEADDR 0x10D4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_WL_DSS_CTRL1 0x10D8 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_MEM_PWR_CRTL 0x10D8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_WL_DSS_STATUS1 0x10DC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_FW_DRV_HANDSHAKE 0x10DC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) + +#define REG_FW_DBG0 0x10E0 +#define REG_FW_DBG1 0x10E4 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8822B_SUPPORT) + +#define REG_FW_DBG2 0x10E8 +#define REG_FW_DBG3 0x10EC +#define REG_FW_DBG4 0x10F0 +#define REG_FW_DBG5 0x10F4 + +#endif + +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_FW_DBG6 0x10F8 +#define REG_FW_DBG7 0x10FC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_CR_EXT 0x1100 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TC9_CTRL 0x1104 +#define REG_TC10_CTRL 0x1108 +#define REG_TC11_CTRL 0x110C +#define REG_TC12_CTRL 0x1110 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FWFF 0x1114 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_RXFF_PTR_V1 0x1118 +#define REG_RXFF_WTR_V1 0x111C + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_FE2IMR 0x1120 +#define REG_FE2ISR 0x1124 +#define REG_FE3IMR 0x1128 +#define REG_FE3ISR 0x112C +#define REG_FE4IMR 0x1130 +#define REG_FE4ISR 0x1134 +#define REG_FT1IMR 0x1138 +#define REG_FT1ISR 0x113C +#define REG_SPWR0 0x1140 +#define REG_SPWR1 0x1144 +#define REG_SPWR2 0x1148 +#define REG_SPWR3 0x114C +#define REG_POWSEQ 0x1150 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_TC7_CTRL_V1 0x1158 +#define REG_TC8_CTRL_V1 0x115C + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3 0x1160 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RX_BCN_TBTT_ITVL0 0x1160 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define REG_RXBCN_TBTT_INTERVAL_PORT4 0x1164 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RX_BCN_TBTT_ITVL1 0x1164 + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) + +#define REG_FWIMR1 0x1168 +#define REG_FWISR1 0x116C +#define REG_FWIMR2 0x1170 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_IO_WRAP_ERR_FLAG 0x1170 + +#endif + +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) + +#define REG_FWISR2 0x1174 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_FWIMR3 0x1178 +#define REG_FWISR3 0x117C + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_SPEED_SENSOR 0x1180 +#define REG_SPEED_SENSOR1 0x1184 +#define REG_SPEED_SENSOR2 0x1188 +#define REG_SPEED_SENSOR3 0x118C +#define REG_SPEED_SENSOR4 0x1190 +#define REG_SPEED_SENSOR5 0x1194 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_RXPKTBUF_1_MAX_ADDR 0x1198 +#define REG_RXFWBUF_1_MAX_ADDR 0x119C +#define REG_IO_WRAP_ERR_FLAG_V1 0x11A0 +#define REG_RXPKTBUF_1_READ 0x11A4 +#define REG_RXPKTBUF_1_WRITE 0x11A8 +#define REG_BUFF_DBGUG 0x11AC +#define REG_RFE_CTRL_PAD_E2 0x11B0 +#define REG_RFE_CTRL_PAD_SR 0x11B4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +#define REG_EXT_QUEUE_REG 0x11C0 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_H2C_PRIORITY_SEL 0x11C0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +#define REG_COUNTER_CONTROL 0x11C4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_COUNTER_CTRL 0x11C4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +#define REG_COUNTER_TH 0x11C8 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_COUNTER_THRESHOLD 0x11C8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_COUNTER_SET 0x11CC +#define REG_COUNTER_OVERFLOW 0x11D0 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +#define REG_TDE_LEN_TH 0x11D4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_TXDMA_LEN_THRESHOLD 0x11D4 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +#define REG_RDE_LEN_TH 0x11D8 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_RXDMA_LEN_THRESHOLD 0x11D8 + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT) + +#define REG_PCIE_EXEC_TIME 0x11DC + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_PCIE_EXEC_TIME_THRESHOLD 0x11DC + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) + +#define REG_FT2IMR 0x11E0 +#define REG_FT2ISR 0x11E4 + +#endif -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#define REG_TRYING_CNT_TH 0x04B0 +#define REG_MSG2 0x11F0 +#define REG_MSG3 0x11F4 +#define REG_MSG4 0x11F8 +#define REG_MSG5 0x11FC +#define REG_DDMA_CH0SA 0x1200 +#define REG_DDMA_CH0DA 0x1204 +#define REG_DDMA_CH0CTRL 0x1208 +#define REG_DDMA_CH1SA 0x1210 +#define REG_DDMA_CH1DA 0x1214 +#define REG_DDMA_CH1CTRL 0x1218 +#define REG_DDMA_CH2SA 0x1220 +#define REG_DDMA_CH2DA 0x1224 +#define REG_DDMA_CH2CTRL 0x1228 +#define REG_DDMA_CH3SA 0x1230 +#define REG_DDMA_CH3DA 0x1234 +#define REG_DDMA_CH3CTRL 0x1238 +#define REG_DDMA_CH4SA 0x1240 +#define REG_DDMA_CH4DA 0x1244 +#define REG_DDMA_CH4CTRL 0x1248 +#define REG_DDMA_CH5SA 0x1250 +#define REG_DDMA_CH5DA 0x1254 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_POWER_STAGE1 0x04B4 +#define REG_REG_DDMA_CH5CTRL 0x1258 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_POWER_STAGE2 0x04B8 +#define REG_DDMA_CH5CTRL 0x1258 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC -#define REG_PKT_LIFE_TIME 0x04C0 -#define REG_STBC_SETTING 0x04C4 -#define REG_STBC_SETTING2 0x04C5 -#define REG_QUEUE_CTRL 0x04C6 -#define REG_SINGLE_AMPDU_CTRL 0x04C7 -#define REG_PROT_MODE_CTRL 0x04C8 -#define REG_BAR_MODE_CTRL 0x04CC -#define REG_RA_TRY_RATE_AGG_LMT 0x04CF -#define REG_MACID_SLEEP2 0x04D0 -#define REG_MACID_SLEEP 0x04D4 +#define REG_DDMA_INT_MSK 0x12E0 +#define REG_DDMA_CHSTATUS 0x12E8 +#define REG_DDMA_CHKSUM 0x12F0 +#define REG_DDMA_MONITOR 0x12FC #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_HW_SEQ0 0x04D8 -#define REG_HW_SEQ1 0x04DA -#define REG_HW_SEQ2 0x04DC -#define REG_HW_SEQ3 0x04DE +#define REG_STC_INT_CS 0x1300 +#define REG_ST_INT_CFG 0x1304 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_CSI_SEQ 0x04DE +#define REG_ACH4_ACH5_TXBD_NUM 0x130C #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_NULL_PKT_STATUS 0x04E0 +#define REG_CMU_DLY_CTRL 0x1310 +#define REG_CMU_DLY_CFG 0x1314 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_NULL_PKT_STATUS_V1 0x04E0 +#define REG_FWCMDQ_TXBD_IDX 0x1318 +#define REG_P0HI8Q_TXBD_IDX 0x131C #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PTCL_ERR_STATUS 0x04E2 +#define REG_H2CQ_TXBD_DESA 0x1320 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PTCL_PKT_NUM 0x04E3 +#define REG_H2CQ_TXBD_DESA_L 0x1320 +#define REG_H2CQ_TXBD_DESA_H 0x1324 #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_NULL_PKT_STATUS_EXTEND 0x04E3 +#define REG_H2CQ_TXBD_NUM 0x1328 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_TRXRPT_MISS_CNT 0x04E3 +#define REG_H2CQ_TXBD_IDX 0x132C #endif +#if (HALMAC_8192F_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8812F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4 +#define REG_H2CQ_CSR 0x1330 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_POLLUTE_PKT_CNT 0x04E8 -#define REG_PTCL_DBG 0x04EC +#define REG_P0HI9Q_TXBD_IDX 0x1334 +#define REG_P0HI10Q_TXBD_IDX 0x1338 +#define REG_P0HI11Q_TXBD_IDX 0x133C +#define REG_P0HI12Q_TXBD_IDX 0x1340 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PTCL_TX_RPT 0x04F0 +#define REG_CPL_BUFFER_MONITOR 0x1344 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_TXOP_EXTRA_CTRL 0x04F0 +#define REG_P0HI13Q_TXBD_IDX 0x1344 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_CPUMGQ_TIMER_CTRL2 0x04F4 +#define REG_PTM_LOCAL_CLOCK 0x1348 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_DUMMY_PAGE4 0x04FC +#define REG_P0HI14Q_TXBD_IDX 0x1348 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DUMMY_PAGE4_V1 0x04FC -#define REG_MOREDATA 0x04FE +#define REG_PTM_LOCAL_CLOCK_H 0x134C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_EDCA_VO_PARAM 0x0500 -#define REG_EDCA_VI_PARAM 0x0504 -#define REG_EDCA_BE_PARAM 0x0508 -#define REG_EDCA_BK_PARAM 0x050C -#define REG_BCNTCFG 0x0510 -#define REG_PIFS 0x0512 -#define REG_RDG_PIFS 0x0513 -#define REG_SIFS 0x0514 -#define REG_TSFTR_SYN_OFFSET 0x0518 -#define REG_AGGR_BREAK_TIME 0x051A -#define REG_SLOT 0x051B -#define REG_TX_PTCL_CTRL 0x0520 -#define REG_TXPAUSE 0x0522 -#define REG_DIS_TXREQ_CLR 0x0523 -#define REG_RD_CTRL 0x0524 -#define REG_MBSSID_CTRL 0x0526 -#define REG_P2PPS_CTRL 0x0527 -#define REG_PKT_LIFETIME_CTRL 0x0528 -#define REG_P2PPS_SPEC_STATE 0x052B +#define REG_P0HI15Q_TXBD_IDX 0x134C #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BAR_TX_CTRL 0x0530 +#define REG_TSFT_PTM_DIFF 0x1350 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_QUEUE_INCOL_THR 0x0538 -#define REG_QUEUE_INCOL_EN 0x053C +#define REG_AXI_EXCEPT_CS 0x1350 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TBTT_PROHIBIT 0x0540 -#define REG_P2PPS_STATE 0x0543 -#define REG_RD_NAV_NXT 0x0544 -#define REG_NAV_PROT_LEN 0x0546 +#define REG_CHANGE_PCIE_SPEED 0x1350 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_FTM_CTRL 0x0548 -#define REG_FTM_TSF_CNT 0x054C +#define REG_PTM_CTRL_STATUS 0x1354 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BCN_CTRL 0x0550 +#define REG_AXI_EXCEPT_TIME 0x1354 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BCN_CTRL1 0x0551 +#define REG_DEBUG_STATE1 0x1354 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BCN_CTRL_CLINT0 0x0551 +#define REG_QUEUE_HEADER_CUR_REMAIN 0x1358 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MBID_NUM 0x0552 -#define REG_DUAL_TSF_RST 0x0553 -#define REG_MBSSID_BCN_SPACE 0x0554 -#define REG_DRVERLYINT 0x0558 -#define REG_BCNDMATIM 0x0559 -#define REG_ATIMWND 0x055A -#define REG_USTIME_TSF 0x055C -#define REG_BCN_MAX_ERR 0x055D -#define REG_RXTSF_OFFSET_CCK 0x055E -#define REG_RXTSF_OFFSET_OFDM 0x055F -#define REG_TSFTR 0x0560 +#define REG_HI8Q_TXBD_IDX 0x1358 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_TSFTR_1 0x0564 +#define REG_DEBUG_STATE2 0x1358 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TSFTR1 0x0568 +#define REG_QUEUE_HEADER_MIN_REMAIN 0x135C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FREERUN_CNT 0x0568 +#define REG_HI9Q_TXBD_IDX 0x135C #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_FREERUN_CNT_1 0x056C +#define REG_DEBUG_STATE3 0x135C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_ATIMWND1 0x0570 +#define REG_HI10Q_TXBD_IDX 0x1360 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_ATIMWND1_V1 0x0570 +#define REG_ACH5_TXBD_DESA_L 0x1360 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TBTT_PROHIBIT_INFRA 0x0571 +#define REG_HI11Q_TXBD_IDX 0x1364 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_CTWND 0x0572 -#define REG_BCNIVLCUNT 0x0573 -#define REG_BCNDROPCTRL 0x0574 -#define REG_HGQ_TIMEOUT_PERIOD 0x0575 +#define REG_ACH5_TXBD_DESA_H 0x1364 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TXCMD_TIMEOUT_PERIOD 0x0576 -#define REG_MISC_CTRL 0x0577 -#define REG_BCN_CTRL_CLINT1 0x0578 -#define REG_BCN_CTRL_CLINT2 0x0579 -#define REG_BCN_CTRL_CLINT3 0x057A +#define REG_HI12Q_TXBD_IDX 0x1368 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_EXTEND_CTRL 0x057B +#define REG_ACH6_TXBD_DESA_L 0x1368 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_P2PPS1_SPEC_STATE 0x057C -#define REG_P2PPS1_STATE 0x057D -#define REG_P2PPS2_SPEC_STATE 0x057E -#define REG_P2PPS2_STATE 0x057F +#define REG_HI13Q_TXBD_IDX 0x136C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PS_TIMER 0x0580 +#define REG_ACH6_TXBD_DESA_H 0x136C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PS_TIMER0 0x0580 +#define REG_HI14Q_TXBD_IDX 0x1370 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TIMER0 0x0584 +#define REG_ACH7_TXBD_DESA_L 0x1370 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PS_TIMER1 0x0584 +#define REG_HI15Q_TXBD_IDX 0x1374 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TIMER1 0x0588 +#define REG_ACH7_TXBD_DESA_H 0x1374 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_PS_TIMER2 0x0588 +#define REG_HI8Q_TXBD_DESA 0x1378 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TBTT_CTN_AREA 0x058C -#define REG_FORCE_BCN_IFS 0x058E -#define REG_TXOP_MIN 0x0590 -#define REG_PRE_BKF_TIME 0x0592 -#define REG_CROSS_TXOP_CTRL 0x0593 +#define REG_ACH8_TXBD_DESA_L 0x1378 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_TBTT_INT_SHIFT_CLI0 0x0594 -#define REG_TBTT_INT_SHIFT_CLI1 0x0595 -#define REG_TBTT_INT_SHIFT_CLI2 0x0596 -#define REG_TBTT_INT_SHIFT_CLI3 0x0597 -#define REG_TBTT_INT_SHIFT_ENABLE 0x0598 +#define REG_CHNL_DMA_CFG_V1 0x137C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_ATIMWND2 0x05A0 -#define REG_ATIMWND3 0x05A1 -#define REG_ATIMWND4 0x05A2 -#define REG_ATIMWND5 0x05A3 -#define REG_ATIMWND6 0x05A4 -#define REG_ATIMWND7 0x05A5 -#define REG_ATIMUGT 0x05A6 -#define REG_HIQ_NO_LMT_EN 0x05A7 -#define REG_DTIM_COUNTER_ROOT 0x05A8 -#define REG_DTIM_COUNTER_VAP1 0x05A9 -#define REG_DTIM_COUNTER_VAP2 0x05AA -#define REG_DTIM_COUNTER_VAP3 0x05AB -#define REG_DTIM_COUNTER_VAP4 0x05AC -#define REG_DTIM_COUNTER_VAP5 0x05AD -#define REG_DTIM_COUNTER_VAP6 0x05AE -#define REG_DTIM_COUNTER_VAP7 0x05AF -#define REG_DIS_ATIM 0x05B0 +#define REG_ACH8_TXBD_DESA_H 0x137C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_EARLY_128US 0x05B1 -#define REG_P2PPS1_CTRL 0x05B2 -#define REG_P2PPS2_CTRL 0x05B3 -#define REG_TIMER0_SRC_SEL 0x05B4 -#define REG_NOA_UNIT_SEL 0x05B5 -#define REG_P2POFF_DIS_TXTIME 0x05B7 -#define REG_MBSSID_BCN_SPACE2 0x05B8 -#define REG_MBSSID_BCN_SPACE3 0x05BC +#define REG_HI9Q_TXBD_DESA 0x1380 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_ACMHWCTRL 0x05C0 -#define REG_ACMRSTCTRL 0x05C1 -#define REG_ACMAVG 0x05C2 -#define REG_VO_ADMTIME 0x05C4 -#define REG_VI_ADMTIME 0x05C6 -#define REG_BE_ADMTIME 0x05C8 -#define REG_EDCA_RANDOM_GEN 0x05CC -#define REG_TXCMD_NOA_SEL 0x05CF -#define REG_NOA_PARAM 0x05E0 +#define REG_ACH9_TXBD_DESA_L 0x1380 +#define REG_ACH9_TXBD_DESA_H 0x1384 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_NOA_PARAM_1 0x05E4 -#define REG_NOA_PARAM_2 0x05E8 -#define REG_NOA_PARAM_3 0x05EC +#define REG_HI10Q_TXBD_DESA 0x1388 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_NOA_SUBIE 0x05ED +#define REG_ACH10_TXBD_DESA_L 0x1388 +#define REG_ACH10_TXBD_DESA_H 0x138C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_P2P_RST 0x05F0 -#define REG_SCHEDULER_RST 0x05F1 +#define REG_HI11Q_TXBD_DESA 0x1390 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_SCH_TXCMD 0x05F8 -#define REG_PAGE5_DUMMY 0x05FC -#define REG_WMAC_CR 0x0600 +#define REG_ACH11_TXBD_DESA_L 0x1390 +#define REG_ACH11_TXBD_DESA_H 0x1394 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_FWPKT_CR 0x0601 +#define REG_HI12Q_TXBD_DESA 0x1398 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_FW_STS_FILTER 0x0602 +#define REG_ACH12_TXBD_DESA_L 0x1398 +#define REG_ACH12_TXBD_DESA_H 0x139C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BWOPMODE 0x0603 +#define REG_HI13Q_TXBD_DESA 0x13A0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TCR 0x0604 -#define REG_RCR 0x0608 -#define REG_RX_PKT_LIMIT 0x060C -#define REG_RX_DLK_TIME 0x060D -#define REG_RX_DRVINFO_SZ 0x060F -#define REG_MACID 0x0610 -#define REG_BSSID 0x0618 -#define REG_MAR 0x0620 -#define REG_MBIDCAMCFG_1 0x0628 -#define REG_MBIDCAMCFG_2 0x062C +#define REG_ACH13_TXBD_DESA_L 0x13A0 +#define REG_ACH13_TXBD_DESA_H 0x13A4 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MCU_TEST_1 0x0630 +#define REG_HI14Q_TXBD_DESA 0x13A8 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_TCR_TSFT_OFS 0x0630 -#define REG_UDF_THSD 0x0632 -#define REG_ZLD_NUM 0x0633 +#define REG_HI0Q_TXBD_DESA_L 0x13A8 +#define REG_HI0Q_TXBD_DESA_H 0x13AC #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MCU_TEST_2 0x0634 +#define REG_HI15Q_TXBD_DESA 0x13B0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_STMP_THSD 0x0634 -#define REG_WMAC_TXTIMEOUT 0x0635 -#define REG_MCU_TEST_2_V1 0x0636 +#define REG_HI1Q_TXBD_DESA_L 0x13B0 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_USTIME_EDCA 0x0638 +#define REG_PCIE_HISR0_V1 0x13B4 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_ACKTO_CCK 0x0639 +#define REG_HI1Q_TXBD_DESA_H 0x13B4 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_MAC_SPEC_SIFS 0x063A -#define REG_RESP_SIFS_CCK 0x063C -#define REG_RESP_SIFS_OFDM 0x063E -#define REG_ACKTO 0x0640 -#define REG_CTS2TO 0x0641 -#define REG_EIFS 0x0642 +#define REG_HI8Q_TXBD_NUM 0x13B8 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_RPFM_MAP0 0x0644 -#define REG_RPFM_MAP1 0x0646 -#define REG_RPFM_CAM_CMD 0x0648 -#define REG_RPFM_CAM_RWD 0x064C +#define REG_HI2Q_TXBD_DESA_L 0x13B8 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_NAV_CTRL 0x0650 -#define REG_BACAMCMD 0x0654 -#define REG_BACAMCONTENT 0x0658 -#define REG_LBDLY 0x0660 +#define REG_HI9Q_TXBD_NUM 0x13BA +#define REG_HI10Q_TXBD_NUM 0x13BC #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_BACAM_RPMEN 0x0661 +#define REG_PCIE_HISR1_V1 0x13BC #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TX_RX 0x0662 +#define REG_HI2Q_TXBD_DESA_H 0x13BC #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_BITMAP_CTL 0x0663 +#define REG_HI11Q_TXBD_NUM 0x13BE +#define REG_HI12Q_TXBD_NUM 0x13C0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RXERR_RPT 0x0664 -#define REG_WMAC_TRXPTCL_CTL 0x0668 -#define REG_CAMCMD 0x0670 -#define REG_CAMWRITE 0x0674 -#define REG_CAMREAD 0x0678 -#define REG_CAMDBG 0x067C -#define REG_SECCFG 0x0680 +#define REG_HI3Q_TXBD_DESA_L 0x13C0 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RXFILTER_CATEGORY_1 0x0682 -#define REG_RXFILTER_ACTION_1 0x0683 -#define REG_RXFILTER_CATEGORY_2 0x0684 -#define REG_RXFILTER_ACTION_2 0x0685 -#define REG_RXFILTER_CATEGORY_3 0x0686 -#define REG_RXFILTER_ACTION_3 0x0687 -#define REG_RXFLTMAP3 0x0688 -#define REG_RXFLTMAP4 0x068A -#define REG_RXFLTMAP5 0x068C -#define REG_RXFLTMAP6 0x068E +#define REG_HI13Q_TXBD_NUM 0x13C2 +#define REG_HI14Q_TXBD_NUM 0x13C4 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WOW_CTRL 0x0690 +#define REG_HI3Q_TXBD_DESA_H 0x13C4 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_NAN_RX_TSF_FILTER 0x0691 +#define REG_HI15Q_TXBD_NUM 0x13C6 +#define REG_HIQ_DMA_STOP 0x13C8 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_PS_RX_INFO 0x0692 -#define REG_WMMPS_UAPSD_TID 0x0693 -#define REG_LPNAV_CTRL 0x0694 +#define REG_HI4Q_TXBD_DESA_L 0x13C8 +#define REG_HI4Q_TXBD_DESA_H 0x13CC +#define REG_HI5Q_TXBD_DESA_L 0x13D0 +#define REG_HI5Q_TXBD_DESA_H 0x13D4 +#define REG_HI6Q_TXBD_DESA_L 0x13D8 +#define REG_HI6Q_TXBD_DESA_H 0x13DC +#define REG_HI7Q_TXBD_DESA_L 0x13E0 +#define REG_HI7Q_TXBD_DESA_H 0x13E4 +#define REG_ACH8_ACH9_TXBD_NUM 0x13E8 +#define REG_ACH10_ACH11_TXBD_NUM 0x13EC +#define REG_ACH12_ACH13_TXBD_NUM 0x13F0 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WKFMCAM_NUM 0x0698 +#define REG_OLD_DEHANG 0x13F4 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WKFMCAM_CMD 0x0698 -#define REG_WKFMCAM_RWD 0x069C +#define REG_ACH4_TXBD_DESA_L 0x13F8 +#define REG_ACH4_TXBD_DESA_H 0x13FC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_RXFLTMAP0 0x06A0 -#define REG_RXFLTMAP1 0x06A2 -#define REG_RXFLTMAP 0x06A4 -#define REG_BCN_PSR_RPT 0x06A8 +#define REG_Q0_Q1_INFO 0x1400 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_FLC_RPC 0x06AC -#define REG_FLC_RPCT 0x06AD -#define REG_FLC_PTS 0x06AE -#define REG_FLC_TRPC 0x06AF +#define REG_ARFR6 0x1400 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RXPKTMON_CTRL 0x06B0 +#define REG_MU_OFFSET 0x1400 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_STATE_MON 0x06B4 +#define REG_Q2_Q3_INFO 0x1404 +#define REG_Q4_Q5_INFO 0x1408 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_ERROR_MON 0x06B8 -#define REG_SEARCH_MACID 0x06BC +#define REG_ARFR7 0x1408 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_COEX_TABLE 0x06C0 +#define REG_Q6_Q7_INFO 0x140C +#define REG_MGQ_HIQ_INFO 0x1410 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RXCMD_0 0x06D0 -#define REG_RXCMD_1 0x06D4 +#define REG_ARFR8 0x1410 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WMAC_RESP_TXINFO 0x06D8 +#define REG_CMDQ_BCNQ_INFO 0x1414 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BBPSF_CTRL 0x06DC +#define REG_USEREG_SETTING 0x1420 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_P2P_RX_BCN_NOA 0x06E0 -#define REG_ASSOCIATED_BFMER0_INFO 0x06E4 -#define REG_ASSOCIATED_BFMER1_INFO 0x06EC -#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4 -#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8 -#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC -#define REG_MACID1 0x0700 +#define REG_LOOPBACK_OPTION 0x1420 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_MACID1_1 0x0704 +#define REG_AESIV_SETTING 0x1424 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BSSID1 0x0708 +#define REG_BF0_TIME_SETTING 0x1428 +#define REG_BF1_TIME_SETTING 0x142C +#define REG_BF_TIMEOUT_EN 0x1430 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_BSSID1_1 0x070C +#define REG_MACID_RELEASE0 0x1434 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BCN_PSR_RPT1 0x0710 -#define REG_ASSOCIATED_BFMEE_SEL 0x0714 -#define REG_SND_PTCL_CTRL 0x0718 -#define REG_RX_CSI_RPT_INFO 0x071C -#define REG_NS_ARP_CTRL 0x0720 -#define REG_NS_ARP_INFO 0x0724 +#define REG_MACID_RELEASE_INFO 0x1434 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_NS_ARP_IPADDR 0x0728 +#define REG_MACID_RELEASE1 0x1438 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728 +#define REG_MACID_RELEASE_SUCCESS_INFO 0x1438 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WRITE_RX_CSI_RPT_INFO 0x072C +#define REG_MACID_RELEASE2 0x143C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BEAMFORMING_INFO_NSARP 0x072C +#define REG_MACID_RELEASE_CTRL 0x143C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_NS_ARP_IPV6_MYADDR 0x0730 +#define REG_MACID_RELEASE3 0x1440 +#define REG_MACID_RELEASE_SETTING 0x1444 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_IPV6 0x0730 -#define REG_IPV6_1 0x0734 -#define REG_IPV6_2 0x0738 -#define REG_IPV6_3 0x073C +#define REG_FAST_EDCA_VOVI_SETTING 0x1448 +#define REG_FAST_EDCA_BEBK_SETTING 0x144C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750 +#define REG_MACID_DROP0 0x1450 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_SWAES_CFG 0x0760 +#define REG_MACID_DROP_INFO 0x1450 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_COEX_V2 0x0762 +#define REG_MACID_DROP1 0x1454 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_COEX 0x0764 +#define REG_MACID_DROP_CTRL 0x1454 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WLAN_ACT_MSK_CTRL 0x0768 +#define REG_MACID_DROP2 0x1458 +#define REG_MACID_DROP3 0x145C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WLAN_ACT_MASK_CTRL 0x0768 +#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460 +#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464 +#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468 +#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WLAN_ACT_MASK_CTRL_1 0x076C +#define REG_MGG_FIFO_CRTL 0x1470 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_STATISTICS_CTRL 0x076E -#define REG_BT_COEX_ENH_INTF_CTRL 0x076E +#define REG_MGQ_FIFO_WRITE_POINTER 0x1470 +#define REG_MGQ_FIFO_READ_POINTER 0x1472 +#define REG_MGQ_FIFO_ENABLE 0x1472 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E +#define REG_MGG_FIFO_INT 0x1474 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_ACT_STATISTICS 0x0770 +#define REG_MGQ_FIFO_RELEASE_INT_MASK 0x1474 +#define REG_MGQ_FIFO_RELEASE_INT_FLAG 0x1476 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_BT_ACT_STATISTICS_1 0x0774 +#define REG_MGG_FIFO_LIFETIME 0x1478 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_STATISTICS_OTH_CTRL 0x0778 +#define REG_MGQ_FIFO_VALID_MAP 0x1478 +#define REG_MGQ_FIFO_LIFETIME 0x147A #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778 +#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_CMD_ID 0x077C +#define REG_SHCUT_SETTING 0x1480 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_STATUS_REPORT_REGISTER 0x077C +#define REG_PKT_TRANS 0x1480 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT__STATUS_RPT 0x077D -#define REG_BT_DATA 0x0780 +#define REG_SHCUT_LLC_ETH_TYPE0 0x1484 +#define REG_SHCUT_LLC_ETH_TYPE1 0x1488 +#define REG_SHCUT_LLC_OUI0 0x148C +#define REG_SHCUT_LLC_OUI1 0x1490 +#define REG_SHCUT_LLC_OUI2 0x1494 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780 +#define REG_SHCUT_LLC_OUI3 0x1498 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WLAN_RPT_ 0x0781 -#define REG_BT_ISR_CTRL 0x0783 -#define REG_WLAN_RPT_TO_CTR 0x0784 +#define REG_FWCMDQ_CTRL 0x14A0 +#define REG_FWCMDQ_PAGE 0x14A4 +#define REG_FWCMDQ_INFO 0x14A8 +#define REG_FWCMDQ_HOLD_PKTNUM 0x14AC #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784 +#define REG_MU_TX_CTL 0x14C0 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_ISOLATION_TABLE 0x0785 +#define REG_MU_TX_CTRL 0x14C0 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785 +#define REG_MU_STA_GID_VLD 0x14C4 +#define REG_MU_STA_USER_POS_INFO 0x14C8 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 0x0788 -#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 0x078C +#define REG_MU_STA_USER_POS_INFO_H 0x14CC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_ISR_STA 0x078F +#define REG_CHNL_INFO_CTRL 0x14D0 #endif +#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F +#define REG_MU_TRX_DBG_CNT 0x14D0 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_TDMA_TIME_AND_RPT_SAM_SET 0x0790 +#define REG_CHNL_IDLE_TIME 0x14D4 +#define REG_CHNL_BUSY_TIME 0x14D8 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_TDMA_TIME_REGISTER 0x0790 +#define REG_MU_TRX_DBG_CNT_V1 0x14DC #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_CH_INFO 0x0794 +#define REG_NEW_EDCA_CTRL 0x14F0 #endif +#if (HALMAC_8812F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BT_ACT_REGISTER 0x0794 +#define REG_SU_DURATION 0x14F0 +#define REG_MU_DURATION 0x14F2 #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_BT_STATIC_INFO_EXT 0x0795 -#define REG_LTR_IDLE_LATENCY 0x0798 +#define REG_SWPS_CTRL 0x14F4 #endif +#if (HALMAC_8812F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_OBFF_CTRL_BASIC 0x0798 +#define REG_HW_NDPA_RTY_LIMIT 0x14F4 #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LTR_ACTIVE_LATENCY 0x079C +#define REG_SWPS_PKT_TH 0x14F6 +#define REG_SWPS_TIME_TH 0x14F8 +#define REG_MACID_SWPS_EN 0x14FC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_OBFF_CTRL2_TIMER 0x079C +#define REG_CPUMGQ_TX_TIMER 0x1500 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_OBFF_CTRL 0x07A0 +#define REG_PORT_CTRL_SEL 0x1500 +#define REG_PORT_CTRL_CFG 0x1501 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_LTR_CTRL_BASIC 0x07A0 +#define REG_PS_TIMER_A 0x1504 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LTR_CTRL 0x07A4 +#define REG_TBTT_PROHIBIT_CFG 0x1504 +#define REG_DRVERLYINT_CFG 0x1507 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4 +#define REG_PS_TIMER_B 0x1508 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_LTR_CTRL2 0x07A8 +#define REG_BCNDMATIM_CFG 0x1508 +#define REG_CTWND_CFG 0x1509 +#define REG_BCNIVLCUNT_CFG 0x150A +#define REG_EARLY_128US_CFG 0x150B #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_LTR_IDLE_LATENCY_V1 0x07A8 -#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC +#define REG_PS_TIMER_C 0x150C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_ANTTRN_CTRL 0x07B0 +#define REG_TSFTR_SYNC_OFFSET_CFG 0x150C +#define REG_TSFTR_SYNC_CTRL_CFG 0x150F #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0 +#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 0x07B4 +#define REG_BCN_SPACE_CFG 0x1510 +#define REG_EARLY_INT_ADJUST_CFG 0x1512 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT) - -#define REG_WMAC_PKTCNT_RWD 0x07B8 -#define REG_WMAC_PKTCNT_CTRL 0x07BC +#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514 +#define REG_PS_TIMER_A_EARLY 0x1515 +#define REG_PS_TIMER_B_EARLY 0x1516 +#define REG_PS_TIMER_C_EARLY 0x1517 #endif +#if (HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_IQ_DUMP 0x07C0 +#define REG_CPUMGQ_PARAMETER 0x1518 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_IQ_DUMP_1 0x07C4 -#define REG_IQ_DUMP_2 0x07C8 +#define REG_SW_TBTT_TSF_INFO 0x151C #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_FTM_CTL 0x07CC +#define REG_TSF_SYN_CTRL0 0x1520 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_IQ_MDPK_FUNC 0x07CE +#define REG_TSF_SYNC_ADJ 0x1520 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_IQ_DUMP_EXT 0x07CF +#define REG_TSFTR_LOW 0x1520 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_OFDM_CCK_LEN_MASK 0x07D0 +#define REG_TSF_SYN_CTRL1 0x1521 +#define REG_TSF_SYN_OFFSET0 0x1522 +#define REG_TSF_SYN_OFFSET1 0x1524 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_OPTION_FUNCTION 0x07D0 +#define REG_TSF_ADJ_VLAUE 0x1524 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WMAC_OPTION_FUNCTION_1 0x07D4 -#define REG_WMAC_OPTION_FUNCTION_2 0x07D8 +#define REG_TSFTR_HIGH 0x1524 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RX_FILTER_FUNCTION 0x07DA +#define REG_TSF_SYN_OFFSET2 0x1528 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_NDP_SIG 0x07E0 -#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4 +#define REG_TSF_ADJ_VLAUE_2 0x1528 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) - -#define REG_SEC_OPT 0x07E8 +#define REG_BCN_ERR_CNT_MAC 0x1528 +#define REG_BCN_ERR_CNT_EDCCA 0x1529 +#define REG_BCN_ERR_CNT_CCA 0x152A +#define REG_BCN_ERR_CNT_INVALID 0x152B +#define REG_BCN_ERR_CNT_OTHERS 0x152C +#define REG_RX_BCN_TIMER 0x152D #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_TXCMD_INFO_FOR_RSP_PKT_1 0x07E8 +#define REG_TSF_SYN_COMPARE_VALUE 0x1530 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_SEC_OPT_V2 0x07EC +#define REG_TBTT_CTN_AREA_V1 0x1530 +#define REG_BCN_MAX_ERR_V1 0x1531 +#define REG_RXTSF_OFFSET_CCK_V1 0x1532 +#define REG_RXTSF_OFFSET_OFDM_V1 0x1533 +#define REG_SUB_BCN_SPACE 0x1534 +#define REG_MBID_NUM_V1 0x1535 +#define REG_MBSSID_CTRL_V1 0x1536 +#define REG_USTIME_TSF_V1 0x1538 +#define REG_BW_CFG 0x1539 +#define REG_ATIMWND_CFG 0x153A +#define REG_DTIM_COUNTER_CFG 0x153B +#define REG_ATIM_DTIM_CTRL_SEL 0x153C +#define REG_ATIMUGT_V1 0x153D +#define REG_BCNDROPCTRL_V1 0x153E +#define REG_DIS_ATIM_V1 0x1540 +#define REG_HIQ_NO_LMT_EN_V1 0x1544 +#define REG_P2PPS_CTRL_V1 0x1548 +#define REG_P2PPS_SPEC_STATE_V1 0x154A +#define REG_P2PPS_STATE_V1 0x154B +#define REG_P2PPS1_CTRL_V1 0x154C +#define REG_P2PPS1_SPEC_STATE_V1 0x154E +#define REG_P2PPS1_STATE_V1 0x154F +#define REG_P2PPS2_CTRL_V1 0x1550 +#define REG_P2PPS2_SPEC_STATE_V1 0x1552 +#define REG_P2PPS2_STATE_V1 0x1553 +#define REG_P2PON_DIS_TXTIME_V1 0x1554 +#define REG_P2POFF_DIS_TXTIME_V1 0x1555 +#define REG_CHG_POWER_BCN_AREA 0x1556 +#define REG_NOA_SEL 0x1557 +#define REG_NOA_PARAM_V1 0x1558 +#define REG_NOA_PARAM_1_V1 0x155C +#define REG_NOA_PARAM_2_V1 0x1560 +#define REG_NOA_PARAM_3_V1 0x1564 +#define REG_NOA_ON_ERLY_TIME_V1 0x1568 +#define REG_NOA_OFF_ERLY_TIME_V1 0x1569 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WSEC_OPTION 0x07EC +#define REG_P2PPS_HW_AUTO_PAUSE_CTRL 0x156C +#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL 0x1570 +#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL 0x1574 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RTS_ADDRESS_0 0x07F0 +#define REG_RX_TBTT_SHIFT 0x1578 +#define REG_FREERUN_CNT_LOW 0x1580 +#define REG_FREERUN_CNT_HIGH 0x1584 +#define REG_CPUMGQ_TX_TIMER_V1 0x1588 +#define REG_PS_TIMER_0 0x158C +#define REG_PS_TIMER_1 0x1590 +#define REG_PS_TIMER_2 0x1594 +#define REG_PS_TIMER_3 0x1598 +#define REG_PS_TIMER_4 0x159C +#define REG_PS_TIMER_5 0x15A0 +#define REG_PS_TIMER_01_CTRL 0x15A4 +#define REG_PS_TIMER_23_CTRL 0x15A8 +#define REG_PS_TIMER_45_CTRL 0x15AC +#define REG_CPUMGQ_FREERUN_TIMER_CTRL 0x15B0 +#define REG_CPUMGQ_PROHIBIT 0x15B4 +#define REG_TIMER_COMPARE 0x15C0 +#define REG_TIMER_COMPARE_VALUE_LOW 0x15C4 +#define REG_TIMER_COMPARE_VALUE_HIGH 0x15C8 #endif +#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) - -#define REG_RTS_ADDR0 0x07F0 +#define REG_SCHEDULER_COUNTER 0x15D0 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_RTS_ADDRESS_0_1 0x07F4 +#define REG_BCN_PSR_RPT2 0x1600 +#define REG_BCN_PSR_RPT3 0x1604 +#define REG_BCN_PSR_RPT4 0x1608 +#define REG_A1_ADDR_MASK 0x160C #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RTS_ADDRESS_1 0x07F8 +#define REG_RXPSF_CTRL 0x1610 +#define REG_RXPSF_TYPE_CTRL 0x1614 +#define REG_CAM_ACCESS_CTRL 0x1618 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814AMP_SUPPORT) - -#define REG_RTS_ADDR1 0x07F8 +#define REG_HT_SND_REF_RATE 0x161C #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_RTS_ADDRESS_1_1 0x07FC +#define REG_CUT_AMSDU_CTRL 0x161C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) - -#define REG__RPFM_MAP1 0x07FE +#define REG_MACID2 0x1620 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SYS_CFG3 0x1000 -#define REG_SYS_CFG4 0x1034 +#define REG_MACID2_H 0x1624 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_SYS_CFG5 0x1070 +#define REG_BSSID2 0x1628 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_CPU_DMEM_CON 0x1080 +#define REG_BSSID2_H 0x162C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BOOT_REASON 0x1088 -#define REG_NFCPAD_CTRL 0x10A8 +#define REG_MACID3 0x1630 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_HIMR2 0x10B0 -#define REG_HISR2 0x10B4 -#define REG_HIMR3 0x10B8 -#define REG_HISR3 0x10BC -#define REG_SW_MDIO 0x10C0 -#define REG_SW_FLUSH 0x10C4 +#define REG_MACID3_H 0x1634 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_DBG_GPIO_BMUX 0x10C8 -#define REG_FPGA_TAG 0x10CC -#define REG_WL_DSS_CTRL0 0x10D0 +#define REG_BSSID3 0x1638 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_H2C_PKT_READADDR 0x10D0 -#define REG_H2C_PKT_WRITEADDR 0x10D4 +#define REG_BSSID3_H 0x163C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_WL_DSS_CTRL1 0x10D8 +#define REG_MACID4 0x1640 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MEM_PWR_CRTL 0x10D8 +#define REG_MACID4_H 0x1644 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_WL_DSS_STATUS1 0x10DC +#define REG_BSSID4 0x1648 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FW_DBG0 0x10E0 -#define REG_FW_DBG1 0x10E4 -#define REG_FW_DBG2 0x10E8 -#define REG_FW_DBG3 0x10EC -#define REG_FW_DBG4 0x10F0 -#define REG_FW_DBG5 0x10F4 -#define REG_FW_DBG6 0x10F8 -#define REG_FW_DBG7 0x10FC -#define REG_CR_EXT 0x1100 -#define REG_FWFF 0x1114 +#define REG_BSSID4_H 0x164C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_RXFF_PTR_V1 0x1118 -#define REG_RXFF_WTR_V1 0x111C +#define REG_NOA_REPORT 0x1650 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FE2IMR 0x1120 -#define REG_FE2ISR 0x1124 -#define REG_FE3IMR 0x1128 -#define REG_FE3ISR 0x112C -#define REG_FE4IMR 0x1130 -#define REG_FE4ISR 0x1134 -#define REG_FT1IMR 0x1138 -#define REG_FT1ISR 0x113C -#define REG_SPWR0 0x1140 -#define REG_SPWR1 0x1144 -#define REG_SPWR2 0x1148 -#define REG_SPWR3 0x114C -#define REG_POWSEQ 0x1150 +#define REG_NOA_REPORT_1 0x1654 +#define REG_NOA_REPORT_2 0x1658 +#define REG_NOA_REPORT_3 0x165C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TC7_CTRL_V1 0x1158 -#define REG_TC8_CTRL_V1 0x115C +#define REG_PWRBIT_SETTING 0x1660 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3 0x1160 -#define REG_RXBCN_TBTT_INTERVAL_PORT4 0x1164 +#define REG_GENERAL_OPTION 0x1664 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_EXT_QUEUE_REG 0x11C0 -#define REG_COUNTER_CONTROL 0x11C4 -#define REG_COUNTER_TH 0x11C8 -#define REG_COUNTER_SET 0x11CC -#define REG_COUNTER_OVERFLOW 0x11D0 -#define REG_TDE_LEN_TH 0x11D4 -#define REG_RDE_LEN_TH 0x11D8 -#define REG_PCIE_EXEC_TIME 0x11DC +#define REG_FWPHYFF_RCR 0x1668 +#define REG_ADDRCAM_WRITE_CONTENT 0x166C +#define REG_ADDRCAM_READ_CONTENT 0x1670 +#define REG_ADDRCAM_CFG 0x1674 #endif +#if (HALMAC_8198F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_FT2IMR 0x11E0 -#define REG_FT2ISR 0x11E4 +#define REG_WMAC_CSI_FRAME_RRSR_SETTING 0x1678 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MSG2 0x11F0 -#define REG_MSG3 0x11F4 -#define REG_MSG4 0x11F8 -#define REG_MSG5 0x11FC -#define REG_DDMA_CH0SA 0x1200 -#define REG_DDMA_CH0DA 0x1204 -#define REG_DDMA_CH0CTRL 0x1208 -#define REG_DDMA_CH1SA 0x1210 -#define REG_DDMA_CH1DA 0x1214 -#define REG_DDMA_CH1CTRL 0x1218 -#define REG_DDMA_CH2SA 0x1220 -#define REG_DDMA_CH2DA 0x1224 -#define REG_DDMA_CH2CTRL 0x1228 -#define REG_DDMA_CH3SA 0x1230 -#define REG_DDMA_CH3DA 0x1234 -#define REG_DDMA_CH3CTRL 0x1238 -#define REG_DDMA_CH4SA 0x1240 -#define REG_DDMA_CH4DA 0x1244 -#define REG_DDMA_CH4CTRL 0x1248 -#define REG_DDMA_CH5SA 0x1250 -#define REG_DDMA_CH5DA 0x1254 +#define REG_CSI_RRSR 0x1678 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_REG_DDMA_CH5CTRL 0x1258 +#define REG_WMAC_MU_BF_OPTION 0x167C #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_DDMA_CH5CTRL 0x1258 +#define REG_MU_BF_OPTION 0x167C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_DDMA_INT_MSK 0x12E0 -#define REG_DDMA_CHSTATUS 0x12E8 -#define REG_DDMA_CHKSUM 0x12F0 -#define REG_DDMA_MONITOR 0x12FC +#define REG_WMAC_PAUSE_BB_CLR_TH 0x167D #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_STC_INT_CS 0x1300 -#define REG_ST_INT_CFG 0x1304 -#define REG_CMU_DLY_CTRL 0x1310 -#define REG_CMU_DLY_CFG 0x1314 -#define REG_H2CQ_TXBD_DESA 0x1320 -#define REG_H2CQ_TXBD_NUM 0x1328 -#define REG_H2CQ_TXBD_IDX 0x132C -#define REG_H2CQ_CSR 0x1330 +#define REG_WMAC_MU_ARB 0x167E #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_AXI_EXCEPT_CS 0x1350 +#define REG__WMAC_MULBK_BUF 0x167E #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8822B_SUPPORT) - -#define REG_CHANGE_PCIE_SPEED 0x1350 +#define REG_WMAC_MULBK_BUF 0x167E #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT) - -#define REG_AXI_EXCEPT_TIME 0x1354 +#define REG_WMAC_MU_OPTION 0x167F +#define REG_WMAC_MU_BF_CTL 0x1680 +#define REG_WMAC_MU_BFRPT_PARA 0x1682 +#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684 +#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686 +#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688 +#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A +#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C +#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) - -#define REG_OLD_DEHANG 0x13F4 +#define REG_WMAC_BB_STOP_RX_COUNTER 0x1690 +#define REG_WMAC_PLCP_MONITOR 0x1694 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_Q0_Q1_INFO 0x1400 -#define REG_Q2_Q3_INFO 0x1404 -#define REG_Q4_Q5_INFO 0x1408 -#define REG_Q6_Q7_INFO 0x140C -#define REG_MGQ_HIQ_INFO 0x1410 -#define REG_CMDQ_BCNQ_INFO 0x1414 -#define REG_USEREG_SETTING 0x1420 -#define REG_AESIV_SETTING 0x1424 -#define REG_BF0_TIME_SETTING 0x1428 -#define REG_BF1_TIME_SETTING 0x142C -#define REG_BF_TIMEOUT_EN 0x1430 -#define REG_MACID_RELEASE0 0x1434 -#define REG_MACID_RELEASE1 0x1438 -#define REG_MACID_RELEASE2 0x143C -#define REG_MACID_RELEASE3 0x1440 -#define REG_MACID_RELEASE_SETTING 0x1444 -#define REG_FAST_EDCA_VOVI_SETTING 0x1448 -#define REG_FAST_EDCA_BEBK_SETTING 0x144C -#define REG_MACID_DROP0 0x1450 -#define REG_MACID_DROP1 0x1454 -#define REG_MACID_DROP2 0x1458 -#define REG_MACID_DROP3 0x145C +#define REG_WMAC_PLCP_MONITOR_MUTX 0x1698 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460 -#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464 -#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468 -#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C -#define REG_MGG_FIFO_CRTL 0x1470 -#define REG_MGG_FIFO_INT 0x1474 -#define REG_MGG_FIFO_LIFETIME 0x1478 -#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C +#define REG_WMAC_DEBUG_PORT 0x1698 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_SHCUT_SETTING 0x1480 +#define REG_WMAC_CSIDMA_CFG 0x169C #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8822B_SUPPORT) - -#define REG_MACID_SHCUT_OFFSET 0x1480 +#define REG_TRANSMIT_ADDRSS_0 0x16A0 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT) - -#define REG_SHCUT_LLC_ETH_TYPE0 0x1484 -#define REG_SHCUT_LLC_ETH_TYPE1 0x1488 -#define REG_SHCUT_LLC_OUI0 0x148C -#define REG_SHCUT_LLC_OUI1 0x1490 -#define REG_SHCUT_LLC_OUI2 0x1494 -#define REG_SHCUT_LLC_OUI3 0x1498 +#define REG_TRANSMIT_ADDRSS_0_H 0x16A4 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_MU_TX_CTL 0x14C0 -#define REG_MU_STA_GID_VLD 0x14C4 -#define REG_MU_STA_USER_POS_INFO 0x14C8 -#define REG_MU_TRX_DBG_CNT 0x14D0 +#define REG_TRANSMIT_ADDRSS_1 0x16A8 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_CPUMGQ_TX_TIMER 0x1500 -#define REG_PS_TIMER_A 0x1504 -#define REG_PS_TIMER_B 0x1508 -#define REG_PS_TIMER_C 0x150C -#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510 -#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514 -#define REG_PS_TIMER_A_EARLY 0x1515 -#define REG_PS_TIMER_B_EARLY 0x1516 -#define REG_PS_TIMER_C_EARLY 0x1517 +#define REG_TRANSMIT_ADDRSS_1_H 0x16AC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_BCN_PSR_RPT2 0x1600 -#define REG_BCN_PSR_RPT3 0x1604 -#define REG_BCN_PSR_RPT4 0x1608 -#define REG_A1_ADDR_MASK 0x160C -#define REG_MACID2 0x1620 -#define REG_BSSID2 0x1628 -#define REG_MACID3 0x1630 -#define REG_BSSID3 0x1638 -#define REG_MACID4 0x1640 -#define REG_BSSID4 0x1648 +#define REG_TRANSMIT_ADDRSS_2 0x16B0 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_NOA_REPORT 0x1650 -#define REG_PWRBIT_SETTING 0x1660 -#define REG_WMAC_MU_BF_OPTION 0x167C +#define REG_TRANSMIT_ADDRSS_2_H 0x16B4 #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WMAC_PAUSE_BB_CLR_TH 0x167D +#define REG_TRANSMIT_ADDRSS_3 0x16B8 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_MU_ARB 0x167E -#define REG_WMAC_MU_OPTION 0x167F -#define REG_WMAC_MU_BF_CTL 0x1680 +#define REG_TRANSMIT_ADDRSS_3_H 0x16BC #endif +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8812F_SUPPORT || \ + HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_MU_BFRPT_PARA 0x1682 +#define REG_TRANSMIT_ADDRSS_4 0x16C0 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WMAC_MU_BIT_BFRPT_PARA 0x1682 +#define REG_TRANSMIT_ADDRSS_4_H 0x16C4 #endif +#if (HALMAC_8812F_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684 -#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686 -#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688 -#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A -#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C -#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E +#define REG_SND_AID12 0x16D0 +#define REG_SND_PKT_INFO 0x16D2 #endif +#if (HALMAC_8812F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT) - -#define REG_WMAC_BB_STOP_RX_COUNTER 0x1690 -#define REG_WMAC_PLCP_MONITOR 0x1694 -#define REG_WMAC_PLCP_MONITOR_MUTX 0x1698 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 #endif +#if (HALMAC_8814B_SUPPORT) -#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_TRANSMIT_ADDRSS_0 0x16A0 -#define REG_TRANSMIT_ADDRSS_1 0x16A8 -#define REG_TRANSMIT_ADDRSS_2 0x16B0 -#define REG_TRANSMIT_ADDRSS_3 0x16B8 -#define REG_TRANSMIT_ADDRSS_4 0x16C0 +#define REG_BIST_RSTN0 0x2100 +#define REG_BIST_RSTN2 0x2108 +#define REG_BIST_MODE_NRML0 0x2110 +#define REG_BIST_MODE_NRML1 0x2114 +#define REG_BIST_MODE_NRML2 0x2118 +#define REG_BIST_MODE_NRML3 0x211C +#define REG_BIST_DONE_NRML_MAC 0x2150 +#define REG_BIST_DONE_NRML1 0x2158 +#define REG_BIST_DONE_DRF_MAC 0x2160 +#define REG_BIST_DONE_DRF 0x2164 +#define REG_BIST_DONE_DRF1 0x2168 +#define REG_BIST_FAIL_NRML_MAC 0x2170 +#define REG_BIST_FAIL_NRML 0x2174 +#define REG_BIST_FAIL_NRML1 0x2178 +#define REG_BIST_FAIL_NRML_MAC_V1 0x2180 +#define REG_BIST_FAIL_NRML_V1 0x2184 +#define REG_BIST_FAIL_NRML1_V1 0x2188 +#define REG_BIST_MISR_DATAOUT 0x2190 +#define REG_BIST_MISR_DATAOUT1 0x2194 +#define REG_BIST_MISR_DATAOUT_CPU 0x2198 +#define REG_BIST_MISR_DATAOUT_CPU1 0x219C +#define REG_BIST_MISR_DATAOUT_CPU2 0x21A0 +#define REG_BIST_MISR_DATOUT_CPU3 0x21A4 +#define REG_DMA_RQPN_INFO_0 0x2200 +#define REG_DMA_RQPN_INFO_1 0x2204 +#define REG_DMA_RQPN_INFO_2 0x2208 +#define REG_DMA_RQPN_INFO_3 0x220C +#define REG_DMA_RQPN_INFO_4 0x2210 +#define REG_DMA_RQPN_INFO_5 0x2214 +#define REG_DMA_RQPN_INFO_6 0x2218 +#define REG_DMA_RQPN_INFO_7 0x221C +#define REG_DMA_RQPN_INFO_8 0x2220 +#define REG_DMA_RQPN_INFO_9 0x2224 +#define REG_DMA_RQPN_INFO_10 0x2228 +#define REG_DMA_RQPN_INFO_11 0x222C +#define REG_DMA_RQPN_INFO_12 0x2230 +#define REG_DMA_RQPN_INFO_13 0x2234 +#define REG_DMA_RQPN_INFO_14 0x2238 +#define REG_DMA_RQPN_INFO_15 0x223C +#define REG_DMA_RQPN_INFO_16 0x2240 +#define REG_HWAMSDU_CTL1 0x2250 +#define REG_HWAMSDU_CTL2 0x2254 +#define REG_HI8Q_TXBD_DESA_L 0x2300 +#define REG_HI8Q_TXBD_DESA_H 0x2304 +#define REG_HI9Q_TXBD_DESA_L 0x2308 +#define REG_HI9Q_TXBD_DESA_H 0x230C +#define REG_HI10Q_TXBD_DESA_L 0x2310 +#define REG_HI10Q_TXBD_DESA_H 0x2314 +#define REG_HI11Q_TXBD_DESA_L 0x2318 +#define REG_HI11Q_TXBD_DESA_H 0x231C +#define REG_HI12Q_TXBD_DESA_L 0x2320 +#define REG_HI12Q_TXBD_DESA_H 0x2324 +#define REG_HI13Q_TXBD_DESA_L 0x2328 #endif +#if (HALMAC_8192F_SUPPORT) -#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT) - -#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 -#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 -#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 +#define REG_H2CQ_TXBD_IDX_V1 0x232C #endif +#if (HALMAC_8814B_SUPPORT) +#define REG_HI13Q_TXBD_DESA_H 0x232C +#define REG_HI14Q_TXBD_DESA_L 0x2330 +#define REG_HI14Q_TXBD_DESA_H 0x2334 +#define REG_HI15Q_TXBD_DESA_L 0x2338 +#define REG_HI15Q_TXBD_DESA_H 0x233C +#define REG_HI16Q_TXBD_DESA_L 0x2340 +#define REG_HI16Q_TXBD_DESA_H 0x2344 +#define REG_HI17Q_TXBD_DESA_L 0x2348 +#define REG_HI17Q_TXBD_DESA_H 0x234C +#define REG_HI18Q_TXBD_DESA_L 0x2350 +#define REG_HI18Q_TXBD_DESA_H 0x2354 +#define REG_HI19Q_TXBD_DESA_L 0x2358 +#define REG_HI19Q_TXBD_DESA_H 0x235C +#define REG_BD_RWPTR_CLR6 0x2364 +#define REG_P0HI16Q_TXBD_IDX 0x2370 +#define REG_P0HI17Q_TXBD_IDX 0x2374 +#define REG_P0HI18Q_TXBD_IDX 0x2378 +#define REG_P0HI19Q_TXBD_IDX 0x237C +#define REG_P0HI16Q_HI17Q_TXBD_NUM 0x2380 +#define REG_P0HI18Q_HI19Q_TXBD_NUM 0x2384 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_PCIE_HISR2_V1 0x23B4 + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_HISR0 0x23B4 + +#endif + +#if (HALMAC_8812F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define REG_PCIE_HISR3_V1 0x23BC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_PCIE_HISR1 0x23BC +#define REG_P0HI8Q_HI9Q_TXBD_NUM 0x23C0 +#define REG_P0HI10Q_HI11Q_TXBD_NUM 0x23C4 +#define REG_P0HI12Q_HI13Q_TXBD_NUM 0x23C8 +#define REG_P0HI14Q_HI15Q_TXBD_NUM 0x23CC +#define REG_ACH6_ACH7_TXBD_NUM 0x23F0 + +#endif + +#if (HALMAC_8192F_SUPPORT) + +#define REG_BF0_TIME_SETTING_V1 0x2428 +#define REG_BF1_TIME_SETTING_V1 0x242C +#define REG_BF_TIMEOUT_EN_V1 0x2430 +#define REG_MACID_RELEASE0_V1 0x2434 +#define REG_MACID_RELEASE1_V1 0x2438 +#define REG_MACID_RELEASE2_V1 0x243C +#define REG_MACID_RELEASE3_V1 0x2440 +#define REG_MACID_RELEASE_SETTING_V1 0x2444 +#define REG_FAST_EDCA_VOVI_SETTING_V1 0x2448 +#define REG_FAST_EDCA_BEBK_SETTING_V1 0x244C +#define REG_R_MACID_RELEASE_SUCCESS_0_V1 0x2460 +#define REG_R_MACID_RELEASE_SUCCESS_1_V1 0x2464 +#define REG_R_MACID_RELEASE_SUCCESS_2_V1 0x2468 +#define REG_R_MACID_RELEASE_SUCCESS_3_V1 0x246C +#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_V1 0x247C +#define REG_NAN_INFO0 0x2480 +#define REG_NAN_INFO1 0x2484 +#define REG_NAN_INFO2 0x2488 +#define REG_NAN_INFO3 0x248C +#define REG_NAN_INFO4 0x2490 +#define REG_NAN_INFO5 0x2494 +#define REG_NAN_INFO6 0x2498 +#define REG_NAN_INFO7 0x249C +#define REG_NAN_INFO8 0x24A0 +#define REG_NAN_INFO9 0x24A4 +#define REG_CHNL_INFO_CTRL_V1 0x24D0 +#define REG_CHNL_IDLE_TIME_V1 0x24D4 +#define REG_CHNL_BUSY_TIME_V1 0x24D8 +#define REG_SWPS_CTRL_V1 0x24F4 +#define REG_SWPS_PKT_TH_V1 0x24F6 +#define REG_SWPS_TIME_TH_V1 0x24F8 +#define REG_MACID_SWPS_EN_V1 0x24FC + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define REG_TXPAGE_INT_CTRL_0 0x3200 +#define REG_TXPAGE_INT_CTRL_1 0x3204 +#define REG_TXPAGE_INT_CTRL_2 0x3208 +#define REG_TXPAGE_INT_CTRL_3 0x320C +#define REG_TXPAGE_INT_CTRL_4 0x3210 +#define REG_TXPAGE_INT_CTRL_5 0x3214 +#define REG_TXPAGE_INT_CTRL_6 0x3218 +#define REG_TXPAGE_INT_CTRL_7 0x321C +#define REG_TXPAGE_INT_CTRL_8 0x3220 +#define REG_TXPAGE_INT_CTRL_9 0x3224 +#define REG_TXPAGE_INT_CTRL_10 0x3228 +#define REG_TXPAGE_INT_CTRL_11 0x322C +#define REG_TXPAGE_INT_CTRL_12 0x3230 +#define REG_TXPAGE_INT_CTRL_13 0x3234 +#define REG_TXPAGE_INT_CTRL_14 0x3238 +#define REG_TXPAGE_INT_CTRL_15 0x323C +#define REG_TXPAGE_INT_CTRL_16 0x3240 +#define REG_ACH4_TXBD_IDX 0x3340 +#define REG_ACH5_TXBD_IDX 0x3344 +#define REG_ACH6_TXBD_IDX 0x3348 +#define REG_ACH7_TXBD_IDX 0x334C +#define REG_ACH8_TXBD_IDX 0x3350 +#define REG_ACH9_TXBD_IDX 0x3354 +#define REG_ACH10_TXBD_IDX 0x3358 +#define REG_ACH11_TXBD_IDX 0x335C +#define REG_ACH12_TXBD_IDX 0x3360 +#define REG_ACH13_TXBD_IDX 0x3364 +#define REG_AC_CHANNEL0_WEIGHT 0x3368 +#define REG_AC_CHANNEL1_WEIGHT 0x3369 +#define REG_AC_CHANNEL2_WEIGHT 0x336A +#define REG_AC_CHANNEL3_WEIGHT 0x336B +#define REG_AC_CHANNEL4_WEIGHT 0x336C +#define REG_AC_CHANNEL5_WEIGHT 0x336D +#define REG_AC_CHANNEL6_WEIGHT 0x336E +#define REG_AC_CHANNEL7_WEIGHT 0x336F +#define REG_AC_CHANNEL8_WEIGHT 0x3370 +#define REG_AC_CHANNEL9_WEIGHT 0x3371 +#define REG_AC_CHANNEL10_WEIGHT 0x3372 +#define REG_AC_CHANNEL11_WEIGHT 0x3373 +#define REG_AC_CHANNEL12_WEIGHT 0x3374 +#define REG_AC_CHANNEL13_WEIGHT 0x3375 +#define REG_PCIE_HISR2 0x33B4 +#define REG_PCIE_HISR3 0x33BC + +#endif /* ----------------------------------------------------- */ /* */ /* 0xFB00h ~ 0xFCFFh TX/RX packet buffer affress */ /* */ /* ----------------------------------------------------- */ -#define REG_RXPKTBUF_STARTADDR 0xFB00 -#define REG_TXPKTBUF_STARTADDR 0xFC00 +#define REG_RXPKTBUF_STARTADDR 0xFB00 +#define REG_TXPKTBUF_STARTADDR 0xFC00 /* ----------------------------------------------------- */ /* */ /* 0xFD00h ~ 0xFDFFh 8051 CPU Local REG */ /* */ /* ----------------------------------------------------- */ -#define REG_SYS_CTRL 0xFD00 -#define REG_PONSTS_RPT1 0xFD01 -#define REG_PONSTS_RPT2 0xFD02 -#define REG_PONSTS_RPT3 0xFD03 -#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */ -#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */ -#define REG_8051ERRFLAG 0xFD08 -#define REG_8051ERRFLAG_MASK 0xFD09 -#define REG_TXADDRH 0xFD10 /* Tx Packet High Address */ -#define REG_RXADDRH 0xFD11 /* Rx Packet High Address */ -#define REG_TXADDRH_EXT 0xFD12 /* 0xFD12[0] : for 8051 access txpktbuf high64k as external register */ - -#define REG_U3_STATE 0xFD48 /* (Read only) [7:4] : usb3 changed last state. [3:0] usb3 state */ +#define REG_SYS_CTRL 0xFD00 +#define REG_PONSTS_RPT1 0xFD01 +#define REG_PONSTS_RPT2 0xFD02 +#define REG_PONSTS_RPT3 0xFD03 +#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */ +#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */ +#define REG_8051ERRFLAG 0xFD08 +#define REG_8051ERRFLAG_MASK 0xFD09 +#define REG_TXADDRH 0xFD10 /* Tx Packet High Address */ +#define REG_RXADDRH 0xFD11 /* Rx Packet High Address */ +#define REG_TXADDRH_EXT 0xFD12 + +#define REG_U3_STATE 0xFD48 /* for MAILBOX */ -#define REG_OUTDATA0 0xFD50 -#define REG_OUTDATA1 0xFD54 -#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady, bit[1] : OutEmptyIntEn */ +#define REG_OUTDATA0 0xFD50 +#define REG_OUTDATA1 0xFD54 +#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady, bit[1] : OutEmptyIntEn */ -#define REG_INDATA0 0xFD60 -#define REG_INDATA1 0xFD64 -#define REG_INRDY 0xFD68 /* bit[0] : InReady, bit[1] : InRdyIntEn */ +#define REG_INDATA0 0xFD60 +#define REG_INDATA1 0xFD64 +#define REG_INRDY 0xFD68 /* bit[0] : InReady, bit[1] : InRdyIntEn */ /* MCU ERROR debug REG */ -#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */ -#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */ -#define REG_MCUERR_ACC 0xFD92 -#define REG_MCUERR_B 0xFD93 -#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */ -#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */ -#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */ -#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */ -#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */ -#define REG_VERA_SIM 0xFD9F +#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */ +#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */ +#define REG_MCUERR_ACC 0xFD92 +#define REG_MCUERR_B 0xFD93 +#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */ +#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */ +#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */ +#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */ +#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */ +#define REG_VERA_SIM 0xFD9F /* 0xFD99~0xFD9F are reserved.. */ /* ----------------------------------------------------- */ @@ -3163,70 +8115,70 @@ /* ----------------------------------------------------- */ /* RTS5101 USB Register Definition */ -#define REG_USB_SETUP_DEC_INT 0xFE00 -#define REG_USB_DMACTL 0xFE01 -#define REG_USB_IRQSTAT0 0xFE02 -#define REG_USB_IRQSTAT1 0xFE03 -#define REG_USB_IRQEN0 0xFE04 -#define REG_USB_IRQEN1 0xFE05 -#define REG_USB_AUTOPTRL 0xFE06 -#define REG_USB_AUTOPTRH 0xFE07 -#define REG_USB_AUTODAT 0xFE08 - -#define REG_USB_SCRATCH0 0xFE09 -#define REG_USB_SCRATCH1 0xFE0A -#define REG_USB_SEEPROM 0xFE0B -#define REG_USB_GPIO0 0xFE0C -#define REG_USB_GPIO0DIR 0xFE0D -#define REG_USB_CLKSEL 0xFE0E -#define REG_USB_BOOTCTL 0xFE0F - -#define REG_USB_USBCTL 0xFE10 -#define REG_USB_USBSTAT 0xFE11 -#define REG_USB_DEVADDR 0xFE12 -#define REG_USB_USBTEST 0xFE13 -#define REG_USB_FNUM0 0xFE14 -#define REG_USB_FNUM1 0xFE15 - -#define REG_USB_EP_IDX 0xFE20 -#define REG_USB_EP_CFG 0xFE21 -#define REG_USB_EP_CTL 0xFE22 -#define REG_USB_EP_STAT 0xFE23 -#define REG_USB_EP_IRQ 0xFE24 -#define REG_USB_EP_IRQEN 0xFE25 -#define REG_USB_EP_MAXPKT0 0xFE26 -#define REG_USB_EP_MAXPKT1 0xFE27 -#define REG_USB_EP_DAT 0xFE28 -#define REG_USB_EP_BC0 0xFE29 -#define REG_USB_EP_BC1 0xFE2A -#define REG_USB_EP_TC0 0xFE2B -#define REG_USB_EP_TC1 0xFE2C -#define REG_USB_EP_TC2 0xFE2D -#define REG_USB_EP_CTL2 0xFE2E - -#define REG_USB_INFO 0xFE17 -#define REG_USB_SPECIAL_OPTION 0xFE55 -#define REG_USB_DMA_AGG_TO 0xFE5B -#define REG_USB_AGG_TO 0xFE5C -#define REG_USB_AGG_TH 0xFE5D - -#define REG_USB_VID 0xFE60 -#define REG_USB_PID 0xFE62 -#define REG_USB_OPT 0xFE64 -#define REG_USB_CONFIG 0xFE65 /* RX EP setting. 0xFE65 Bit[3:0] : RXQ, Bit[7:4] : INTQ */ - /* TX EP setting. 0xFE66 Bit[3:0] : TXQ0, Bit[7:4] : TXQ1, 0xFE67 Bit[3:0] : TXQ2 */ -#define REG_USB_PHY_PARA1 0xFE68 /* Bit[7:4]: XCVR_SEN (USB PHY 0xE2[7:4]), Bit[3:0]: XCVR_SH (USB PHY 0xE2[3:0]) */ -#define REG_USB_PHY_PARA2 0xFE69 /* Bit[7:5]: XCVR_BG (USB PHY 0xE3[5:3]), Bit[4:2]: XCVR_DR (USB PHY 0xE3[2:0]), Bit[1]: SE0_LVL (USB PHY 0xE5[7]), Bit[0]: FORCE_XTL_ON (USB PHY 0xE5[1]) */ -#define REG_USB_PHY_PARA3 0xFE6A /* Bit[7:5]: XCVR_SRC (USB PHY 0xE5[4:2]), Bit[4]: LATE_DLLEN (USB PHY 0xF0[4]), Bit[3]: HS_LP_MODE (USB PHY 0xF0[3]), Bit[2]: UTMI_POS_OUT (USB PHY 0xF1 [7]), Bit[1:0]: TX_DELAY (USB PHY 0xF1 [2:1]) */ -#define REG_USB_PHY_PARA4 0xFE6B /* (USB PHY 0xE7[7:0]) */ -#define REG_USB_OPT2 0xFE6C -#define REG_USB_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ -#define REG_USB_MANUFACTURE_SETTING 0xFE80 /* 0xFE80~0xFE90 Max : 32 bytes */ -#define REG_USB_PRODUCT_STRING 0xFEA0 /* 0xFEA0~0xFECF Max : 48 bytes */ -#define REG_USB_SERIAL_NUMBER_STRING 0xFED0 /* 0xFED0~0xFEDF Max : 12 bytes */ - -#define REG_USB_ALTERNATE_SETTING 0xFE4F -#define REG_USB_INT_BINTERVAL 0xFE6E -#define REG_USB_GPS_EP_CONFIG 0xFE6D - -#endif /* __HALMAC_COM_REG_H__ */ +#define REG_USB_SETUP_DEC_INT 0xFE00 +#define REG_USB_DMACTL 0xFE01 +#define REG_USB_IRQSTAT0 0xFE02 +#define REG_USB_IRQSTAT1 0xFE03 +#define REG_USB_IRQEN0 0xFE04 +#define REG_USB_IRQEN1 0xFE05 +#define REG_USB_AUTOPTRL 0xFE06 +#define REG_USB_AUTOPTRH 0xFE07 +#define REG_USB_AUTODAT 0xFE08 + +#define REG_USB_SCRATCH0 0xFE09 +#define REG_USB_SCRATCH1 0xFE0A +#define REG_USB_SEEPROM 0xFE0B +#define REG_USB_GPIO0 0xFE0C +#define REG_USB_GPIO0DIR 0xFE0D +#define REG_USB_CLKSEL 0xFE0E +#define REG_USB_BOOTCTL 0xFE0F + +#define REG_USB_USBCTL 0xFE10 +#define REG_USB_USBSTAT 0xFE11 +#define REG_USB_DEVADDR 0xFE12 +#define REG_USB_USBTEST 0xFE13 +#define REG_USB_FNUM0 0xFE14 +#define REG_USB_FNUM1 0xFE15 + +#define REG_USB_EP_IDX 0xFE20 +#define REG_USB_EP_CFG 0xFE21 +#define REG_USB_EP_CTL 0xFE22 +#define REG_USB_EP_STAT 0xFE23 +#define REG_USB_EP_IRQ 0xFE24 +#define REG_USB_EP_IRQEN 0xFE25 +#define REG_USB_EP_MAXPKT0 0xFE26 +#define REG_USB_EP_MAXPKT1 0xFE27 +#define REG_USB_EP_DAT 0xFE28 +#define REG_USB_EP_BC0 0xFE29 +#define REG_USB_EP_BC1 0xFE2A +#define REG_USB_EP_TC0 0xFE2B +#define REG_USB_EP_TC1 0xFE2C +#define REG_USB_EP_TC2 0xFE2D +#define REG_USB_EP_CTL2 0xFE2E + +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_VID 0xFE60 +#define REG_USB_PID 0xFE62 +#define REG_USB_OPT 0xFE64 +#define REG_USB_CONFIG 0xFE65 + +#define REG_USB_PHY_PARA1 0xFE68 +#define REG_USB_PHY_PARA2 0xFE69 +#define REG_USB_PHY_PARA3 0xFE6A +#define REG_USB_PHY_PARA4 0xFE6B +#define REG_USB_OPT2 0xFE6C +#define REG_USB_MAC_ADDR 0xFE70 +#define REG_USB_MANUFACTURE_SETTING 0xFE80 +#define REG_USB_PRODUCT_STRING 0xFEA0 +#define REG_USB_SERIAL_NUMBER_STRING 0xFED0 + +#define REG_USB_ALTERNATE_SETTING 0xFE4F +#define REG_USB_INT_BINTERVAL 0xFE6E +#define REG_USB_GPS_EP_CONFIG 0xFE6D + +#endif /* __HALMAC_COM_REG_H__ */ diff --git a/hal/halmac/halmac_reg_8197f.h b/hal/halmac/halmac_reg_8197f.h index f7cdb87..6be0b3f 100644 --- a/hal/halmac/halmac_reg_8197f.h +++ b/hal/halmac/halmac_reg_8197f.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_REG_8197F_H #define __INC_HALMAC_REG_8197F_H @@ -209,7 +224,7 @@ #define REG_FWFF_C2H_8197F 0x0298 #define REG_FWFF_CTRL_8197F 0x029C #define REG_FWFF_PKT_INFO_8197F 0x02A0 -#define REG_FC2H_INFO_8197F 0x02A6 +#define REG_FC2H_INFO_8197F 0x02A4 #define REG_DDMA_CH0SA_8197F 0x1200 #define REG_DDMA_CH0DA_8197F 0x1204 #define REG_DDMA_CH0CTRL_8197F 0x1208 @@ -414,6 +429,9 @@ #define REG_SHCUT_LLC_OUI1_8197F 0x1490 #define REG_SHCUT_LLC_OUI2_8197F 0x1494 #define REG_SHCUT_LLC_OUI3_8197F 0x1498 +#define REG_CHNL_INFO_CTRL_8197F 0x14D0 +#define REG_CHNL_IDLE_TIME_8197F 0x14D4 +#define REG_CHNL_BUSY_TIME_8197F 0x14D8 #define REG_EDCA_VO_PARAM_8197F 0x0500 #define REG_EDCA_VI_PARAM_8197F 0x0504 #define REG_EDCA_BE_PARAM_8197F 0x0508 diff --git a/hal/halmac/halmac_reg_8814b.h b/hal/halmac/halmac_reg_8814b.h index d8bb510..c82a651 100644 --- a/hal/halmac/halmac_reg_8814b.h +++ b/hal/halmac/halmac_reg_8814b.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_REG_8814B_H #define __INC_HALMAC_REG_8814B_H @@ -14,8 +29,11 @@ #define REG_RF_CTRL_8814B 0x001F #define REG_AFE_LDO_CTRL_8814B 0x0020 #define REG_AFE_CTRL1_8814B 0x0024 -#define REG_AFE_CTRL2_8814B 0x0028 -#define REG_AFE_CTRL3_8814B 0x002C +#define REG_ANAPARSW_POW_MAC_8814B 0x0028 +#define REG_ANAPARLDO_POW_MAC_8814B 0x0029 +#define REG_ANAPAR_POW_MAC_8814B 0x002A +#define REG_ANAPAR_POW_XTAL_8814B 0x002B +#define REG_ANAPARLDO_MAC_8814B 0x002C #define REG_EFUSE_CTRL_8814B 0x0030 #define REG_LDO_EFUSE_CTRL_8814B 0x0034 #define REG_PWR_OPTION_CTRL_8814B 0x0038 @@ -56,10 +74,8 @@ #define REG_DBG_PORT_SEL_8814B 0x00C0 #define REG_PAD_CTRL2_8814B 0x00C4 #define REG_PMC_DBG_CTRL2_8814B 0x00CC -#define REG_BIST_CTRL_8814B 0x00D0 -#define REG_BIST_RPT_8814B 0x00D4 #define REG_MEM_CTRL_8814B 0x00D8 -#define REG_AFE_CTRL8_8814B 0x00DC +#define REG_SYN_RFC_CTRL_8814B 0x00DC #define REG_USB_SIE_INTF_8814B 0x00E0 #define REG_PCIE_MIO_INTF_8814B 0x00E4 #define REG_PCIE_MIO_INTD_8814B 0x00E8 @@ -68,21 +84,51 @@ #define REG_SYS_STATUS1_8814B 0x00F4 #define REG_SYS_STATUS2_8814B 0x00F8 #define REG_SYS_CFG2_8814B 0x00FC -#define REG_SYS_CFG3_8814B 0x1000 -#define REG_SYS_CFG4_8814B 0x1034 +#define REG_ANAPARSW_MAC_0_8814B 0x1010 +#define REG_ANAPARSW_MAC_1_8814B 0x1014 +#define REG_ANAPAR_MAC_0_8814B 0x1018 +#define REG_ANAPAR_MAC_1_8814B 0x101C +#define REG_ANAPAR_MAC_2_8814B 0x1020 +#define REG_ANAPAR_MAC_3_8814B 0x1024 +#define REG_ANAPAR_MAC_4_8814B 0x1028 +#define REG_ANAPAR_MAC_5_8814B 0x102C +#define REG_ANAPAR_MAC_6_8814B 0x1030 +#define REG_ANAPAR_MAC_7_8814B 0x1034 +#define REG_ANAPAR_MAC_8_8814B 0x1038 +#define REG_ANAPAR_XTAL_0_8814B 0x1040 +#define REG_ANAPAR_XTAL_1_8814B 0x1044 +#define REG_ANAPAR_XTAL_2_8814B 0x1048 +#define REG_ANAPAR_XTAL_AAC_8814B 0x104C +#define REG_ANAPAR_XTAL_R_ONLY_8814B 0x1050 +#define REG_CPHY_LDO_8814B 0x1054 +#define REG_CPHY_BG_8814B 0x1058 +#define REG_HIMR_4_8814B 0x1060 +#define REG_HISR_4_8814B 0x1064 +#define REG_HIMR_5_8814B 0x1068 +#define REG_HISR_5_8814B 0x106C #define REG_SYS_CFG5_8814B 0x1070 +#define REG_HIMR_6_8814B 0x1078 +#define REG_HISR_6_8814B 0x107C #define REG_CPU_DMEM_CON_8814B 0x1080 #define REG_BOOT_REASON_8814B 0x1088 +#define REG_DATA_CPU_CTL0_8814B 0x1090 +#define REG_DATA_CPU_CTL1_8814B 0x1094 +#define REG_TXDMA_STOP_HIMR_8814B 0x1098 +#define REG_TXDMA_STOP_HISR_8814B 0x109C +#define REG_TXDMA_START_HIMR_8814B 0x10A0 +#define REG_TXDMA_START_HISR_8814B 0x10A4 #define REG_NFCPAD_CTRL_8814B 0x10A8 #define REG_HIMR2_8814B 0x10B0 #define REG_HISR2_8814B 0x10B4 #define REG_HIMR3_8814B 0x10B8 #define REG_HISR3_8814B 0x10BC #define REG_SW_MDIO_8814B 0x10C0 -#define REG_SW_FLUSH_8814B 0x10C4 +#define REG_HIMR_7_8814B 0x10C8 +#define REG_HISR_7_8814B 0x10CC #define REG_H2C_PKT_READADDR_8814B 0x10D0 #define REG_H2C_PKT_WRITEADDR_8814B 0x10D4 #define REG_MEM_PWR_CRTL_8814B 0x10D8 +#define REG_FW_DRV_HANDSHAKE_8814B 0x10DC #define REG_FW_DBG0_8814B 0x10E0 #define REG_FW_DBG1_8814B 0x10E4 #define REG_FW_DBG2_8814B 0x10E8 @@ -92,6 +138,7 @@ #define REG_FW_DBG6_8814B 0x10F8 #define REG_FW_DBG7_8814B 0x10FC #define REG_CR_8814B 0x0100 +#define REG_PG_SIZE_8814B 0x0104 #define REG_PKT_BUFF_ACCESS_CTRL_8814B 0x0106 #define REG_TSF_CLK_STATE_8814B 0x0108 #define REG_TXDMA_PQ_MAP_8814B 0x010C @@ -117,12 +164,10 @@ #define REG_TCUNIT_BASE_8814B 0x0164 #define REG_TC5_CTRL_8814B 0x0168 #define REG_TC6_CTRL_8814B 0x016C -#define REG_MBIST_FAIL_8814B 0x0170 -#define REG_MBIST_START_PAUSE_8814B 0x0174 -#define REG_MBIST_DONE_8814B 0x0178 -#define REG_MBIST_FAIL_NRML_8814B 0x017C #define REG_AES_DECRPT_DATA_8814B 0x0180 #define REG_AES_DECRPT_CFG_8814B 0x0184 +#define REG_HIOE_CTRL_8814B 0x0188 +#define REG_HIOE_CFG_FILE_8814B 0x018C #define REG_TMETER_8814B 0x0190 #define REG_OSC_32K_CTRL_8814B 0x0194 #define REG_32K_CAL_REG1_8814B 0x0198 @@ -130,6 +175,8 @@ #define REG_C2HEVT_1_8814B 0x01A4 #define REG_C2HEVT_2_8814B 0x01A8 #define REG_C2HEVT_3_8814B 0x01AC +#define REG_RXDESC_BUFF_RPTR_8814B 0x01B0 +#define REG_RXDESC_BUFF_WPTR_8814B 0x01B4 #define REG_SW_DEFINED_PAGE1_8814B 0x01B8 #define REG_SW_DEFINED_PAGE2_8814B 0x01BC #define REG_MCUTST_I_8814B 0x01C0 @@ -140,8 +187,7 @@ #define REG_HMEBOX1_8814B 0x01D4 #define REG_HMEBOX2_8814B 0x01D8 #define REG_HMEBOX3_8814B 0x01DC -#define REG_LLT_INIT_8814B 0x01E0 -#define REG_LLT_INIT_ADDR_8814B 0x01E4 +#define REG_RXDESC_BUFF_BNDY_8814B 0x01E0 #define REG_BB_ACCESS_CTRL_8814B 0x01E8 #define REG_BB_ACCESS_DATA_8814B 0x01EC #define REG_HMEBOX_E0_8814B 0x01F0 @@ -149,6 +195,10 @@ #define REG_HMEBOX_E2_8814B 0x01F8 #define REG_HMEBOX_E3_8814B 0x01FC #define REG_CR_EXT_8814B 0x1100 +#define REG_TC9_CTRL_8814B 0x1104 +#define REG_TC10_CTRL_8814B 0x1108 +#define REG_TC11_CTRL_8814B 0x110C +#define REG_TC12_CTRL_8814B 0x1110 #define REG_FWFF_8814B 0x1114 #define REG_RXFF_PTR_V1_8814B 0x1118 #define REG_RXFF_WTR_V1_8814B 0x111C @@ -167,36 +217,88 @@ #define REG_POWSEQ_8814B 0x1150 #define REG_TC7_CTRL_V1_8814B 0x1158 #define REG_TC8_CTRL_V1_8814B 0x115C +#define REG_RX_BCN_TBTT_ITVL0_8814B 0x1160 +#define REG_RX_BCN_TBTT_ITVL1_8814B 0x1164 +#define REG_FWIMR1_8814B 0x1168 +#define REG_FWISR1_8814B 0x116C +#define REG_FWIMR2_8814B 0x1170 +#define REG_FWISR2_8814B 0x1174 +#define REG_FWIMR3_8814B 0x1178 +#define REG_FWISR3_8814B 0x117C +#define REG_SPEED_SENSOR_8814B 0x1180 +#define REG_SPEED_SENSOR1_8814B 0x1184 +#define REG_SPEED_SENSOR2_8814B 0x1188 +#define REG_SPEED_SENSOR3_8814B 0x118C +#define REG_SPEED_SENSOR4_8814B 0x1190 +#define REG_SPEED_SENSOR5_8814B 0x1194 +#define REG_RXPKTBUF_1_MAX_ADDR_8814B 0x1198 +#define REG_RXFWBUF_1_MAX_ADDR_8814B 0x119C +#define REG_IO_WRAP_ERR_FLAG_V1_8814B 0x11A0 +#define REG_RXPKTBUF_1_READ_8814B 0x11A4 +#define REG_RXPKTBUF_1_WRITE_8814B 0x11A8 +#define REG_BUFF_DBGUG_8814B 0x11AC +#define REG_RFE_CTRL_PAD_E2_8814B 0x11B0 +#define REG_RFE_CTRL_PAD_SR_8814B 0x11B4 +#define REG_H2C_PRIORITY_SEL_8814B 0x11C0 +#define REG_COUNTER_CTRL_8814B 0x11C4 +#define REG_COUNTER_THRESHOLD_8814B 0x11C8 +#define REG_COUNTER_SET_8814B 0x11CC +#define REG_COUNTER_OVERFLOW_8814B 0x11D0 +#define REG_TXDMA_LEN_THRESHOLD_8814B 0x11D4 +#define REG_RXDMA_LEN_THRESHOLD_8814B 0x11D8 +#define REG_PCIE_EXEC_TIME_THRESHOLD_8814B 0x11DC #define REG_FT2IMR_8814B 0x11E0 #define REG_FT2ISR_8814B 0x11E4 #define REG_MSG2_8814B 0x11F0 #define REG_MSG3_8814B 0x11F4 #define REG_MSG4_8814B 0x11F8 #define REG_MSG5_8814B 0x11FC -#define REG_FIFOPAGE_CTRL_1_8814B 0x0200 -#define REG_FIFOPAGE_CTRL_2_8814B 0x0204 +#define REG_BIST_RSTN0_8814B 0x2100 +#define REG_BIST_RSTN2_8814B 0x2108 +#define REG_BIST_MODE_NRML0_8814B 0x2110 +#define REG_BIST_MODE_NRML1_8814B 0x2114 +#define REG_BIST_MODE_NRML2_8814B 0x2118 +#define REG_BIST_MODE_NRML3_8814B 0x211C +#define REG_BIST_DONE_NRML_MAC_8814B 0x2150 +#define REG_BIST_DONE_NRML1_8814B 0x2158 +#define REG_BIST_DONE_DRF_MAC_8814B 0x2160 +#define REG_BIST_DONE_DRF_8814B 0x2164 +#define REG_BIST_DONE_DRF1_8814B 0x2168 +#define REG_BIST_FAIL_NRML_MAC_8814B 0x2170 +#define REG_BIST_FAIL_NRML_8814B 0x2174 +#define REG_BIST_FAIL_NRML1_8814B 0x2178 +#define REG_BIST_FAIL_NRML_MAC_V1_8814B 0x2180 +#define REG_BIST_FAIL_NRML_V1_8814B 0x2184 +#define REG_BIST_FAIL_NRML1_V1_8814B 0x2188 +#define REG_BIST_MISR_DATAOUT_8814B 0x2190 +#define REG_BIST_MISR_DATAOUT1_8814B 0x2194 +#define REG_BIST_MISR_DATAOUT_CPU_8814B 0x2198 +#define REG_BIST_MISR_DATAOUT_CPU1_8814B 0x219C +#define REG_BIST_MISR_DATAOUT_CPU2_8814B 0x21A0 +#define REG_BIST_MISR_DATOUT_CPU3_8814B 0x21A4 +#define REG_BCN_CTRL_0_8814B 0x0200 +#define REG_BCN_CTRL_1_8814B 0x0204 #define REG_AUTO_LLT_V1_8814B 0x0208 #define REG_TXDMA_OFFSET_CHK_8814B 0x020C #define REG_TXDMA_STATUS_8814B 0x0210 #define REG_TX_DMA_DBG_8814B 0x0214 -#define REG_TQPNT1_8814B 0x0218 -#define REG_TQPNT2_8814B 0x021C -#define REG_TQPNT3_8814B 0x0220 -#define REG_TQPNT4_8814B 0x0224 -#define REG_RQPN_CTRL_1_8814B 0x0228 -#define REG_RQPN_CTRL_2_8814B 0x022C -#define REG_FIFOPAGE_INFO_1_8814B 0x0230 -#define REG_FIFOPAGE_INFO_2_8814B 0x0234 -#define REG_FIFOPAGE_INFO_3_8814B 0x0238 -#define REG_FIFOPAGE_INFO_4_8814B 0x023C -#define REG_FIFOPAGE_INFO_5_8814B 0x0240 +#define REG_DMA_RQPN_INFO_PUB_8814B 0x0218 +#define REG_RQPN_CTRL_2_V1_8814B 0x021C +#define REG_BCN_CTRL_2_8814B 0x0220 +#define REG_TXPKTNUM_0_8814B 0x0230 +#define REG_TXPKTNUM_1_8814B 0x0234 +#define REG_TXPKTNUM_2_8814B 0x0238 +#define REG_TXPKTNUM_3_8814B 0x023C +#define REG_TX_AGG_ALIGN_8814B 0x0240 #define REG_H2C_HEAD_8814B 0x0244 #define REG_H2C_TAIL_8814B 0x0248 #define REG_H2C_READ_ADDR_8814B 0x024C #define REG_H2C_WR_ADDR_8814B 0x0250 #define REG_H2C_INFO_8814B 0x0254 +#define REG_DMA_OQT_0_8814B 0x0260 +#define REG_DMA_OQT_1_8814B 0x0264 #define REG_RXDMA_AGG_PG_TH_8814B 0x0280 -#define REG_RXPKT_NUM_8814B 0x0284 +#define REG_RXDMA_CTRL_8814B 0x0284 #define REG_RXDMA_STATUS_8814B 0x0288 #define REG_RXDMA_DPR_8814B 0x028C #define REG_RXDMA_MODE_8814B 0x0290 @@ -204,6 +306,10 @@ #define REG_FWFF_C2H_8814B 0x0298 #define REG_FWFF_CTRL_8814B 0x029C #define REG_FWFF_PKT_INFO_8814B 0x02A0 +#define REG_FWFF_PKT_INFO2_8814B 0x02A4 +#define REG_RXPKTNUM_8814B 0x02B0 +#define REG_RXPKTNUM_TH_8814B 0x02B4 +#define REG_FW_UPD_RXDES_RDPTR_8814B 0x02B8 #define REG_DDMA_CH0SA_8814B 0x1200 #define REG_DDMA_CH0DA_8814B 0x1204 #define REG_DDMA_CH0CTRL_8814B 0x1208 @@ -226,59 +332,95 @@ #define REG_DDMA_CHSTATUS_8814B 0x12E8 #define REG_DDMA_CHKSUM_8814B 0x12F0 #define REG_DDMA_MONITOR_8814B 0x12FC +#define REG_DMA_RQPN_INFO_0_8814B 0x2200 +#define REG_DMA_RQPN_INFO_1_8814B 0x2204 +#define REG_DMA_RQPN_INFO_2_8814B 0x2208 +#define REG_DMA_RQPN_INFO_3_8814B 0x220C +#define REG_DMA_RQPN_INFO_4_8814B 0x2210 +#define REG_DMA_RQPN_INFO_5_8814B 0x2214 +#define REG_DMA_RQPN_INFO_6_8814B 0x2218 +#define REG_DMA_RQPN_INFO_7_8814B 0x221C +#define REG_DMA_RQPN_INFO_8_8814B 0x2220 +#define REG_DMA_RQPN_INFO_9_8814B 0x2224 +#define REG_DMA_RQPN_INFO_10_8814B 0x2228 +#define REG_DMA_RQPN_INFO_11_8814B 0x222C +#define REG_DMA_RQPN_INFO_12_8814B 0x2230 +#define REG_DMA_RQPN_INFO_13_8814B 0x2234 +#define REG_DMA_RQPN_INFO_14_8814B 0x2238 +#define REG_DMA_RQPN_INFO_15_8814B 0x223C +#define REG_DMA_RQPN_INFO_16_8814B 0x2240 +#define REG_HWAMSDU_CTL1_8814B 0x2250 +#define REG_HWAMSDU_CTL2_8814B 0x2254 +#define REG_TXPAGE_INT_CTRL_0_8814B 0x3200 +#define REG_TXPAGE_INT_CTRL_1_8814B 0x3204 +#define REG_TXPAGE_INT_CTRL_2_8814B 0x3208 +#define REG_TXPAGE_INT_CTRL_3_8814B 0x320C +#define REG_TXPAGE_INT_CTRL_4_8814B 0x3210 +#define REG_TXPAGE_INT_CTRL_5_8814B 0x3214 +#define REG_TXPAGE_INT_CTRL_6_8814B 0x3218 +#define REG_TXPAGE_INT_CTRL_7_8814B 0x321C +#define REG_TXPAGE_INT_CTRL_8_8814B 0x3220 +#define REG_TXPAGE_INT_CTRL_9_8814B 0x3224 +#define REG_TXPAGE_INT_CTRL_10_8814B 0x3228 +#define REG_TXPAGE_INT_CTRL_11_8814B 0x322C +#define REG_TXPAGE_INT_CTRL_12_8814B 0x3230 +#define REG_TXPAGE_INT_CTRL_13_8814B 0x3234 +#define REG_TXPAGE_INT_CTRL_14_8814B 0x3238 +#define REG_TXPAGE_INT_CTRL_15_8814B 0x323C +#define REG_TXPAGE_INT_CTRL_16_8814B 0x3240 #define REG_PCIE_CTRL_8814B 0x0300 -#define REG_INT_MIG_8814B 0x0304 -#define REG_BCNQ_TXBD_DESA_8814B 0x0308 -#define REG_MGQ_TXBD_DESA_8814B 0x0310 -#define REG_VOQ_TXBD_DESA_8814B 0x0318 -#define REG_VIQ_TXBD_DESA_8814B 0x0320 -#define REG_BEQ_TXBD_DESA_8814B 0x0328 -#define REG_BKQ_TXBD_DESA_8814B 0x0330 -#define REG_RXQ_RXBD_DESA_8814B 0x0338 -#define REG_HI0Q_TXBD_DESA_8814B 0x0340 -#define REG_HI1Q_TXBD_DESA_8814B 0x0348 -#define REG_HI2Q_TXBD_DESA_8814B 0x0350 -#define REG_HI3Q_TXBD_DESA_8814B 0x0358 -#define REG_HI4Q_TXBD_DESA_8814B 0x0360 -#define REG_HI5Q_TXBD_DESA_8814B 0x0368 -#define REG_HI6Q_TXBD_DESA_8814B 0x0370 -#define REG_HI7Q_TXBD_DESA_8814B 0x0378 -#define REG_MGQ_TXBD_NUM_8814B 0x0380 -#define REG_RX_RXBD_NUM_8814B 0x0382 -#define REG_VOQ_TXBD_NUM_8814B 0x0384 -#define REG_VIQ_TXBD_NUM_8814B 0x0386 -#define REG_BEQ_TXBD_NUM_8814B 0x0388 -#define REG_BKQ_TXBD_NUM_8814B 0x038A -#define REG_HI0Q_TXBD_NUM_8814B 0x038C -#define REG_HI1Q_TXBD_NUM_8814B 0x038E -#define REG_HI2Q_TXBD_NUM_8814B 0x0390 -#define REG_HI3Q_TXBD_NUM_8814B 0x0392 -#define REG_HI4Q_TXBD_NUM_8814B 0x0394 -#define REG_HI5Q_TXBD_NUM_8814B 0x0396 -#define REG_HI6Q_TXBD_NUM_8814B 0x0398 -#define REG_HI7Q_TXBD_NUM_8814B 0x039A +#define REG_ACH_CTRL_8814B 0x0304 +#define REG_HIQ_CTRL_8814B 0x0308 +#define REG_INT_MIG_V1_8814B 0x030C +#define REG_P0MGQ_TXBD_DESA_L_8814B 0x0310 +#define REG_P0MGQ_TXBD_DESA_H_8814B 0x0314 +#define REG_ACH0_TXBD_DESA_L_8814B 0x0318 +#define REG_ACH0_TXBD_DESA_H_8814B 0x031C +#define REG_ACH1_TXBD_DESA_L_8814B 0x0320 +#define REG_ACH1_TXBD_DESA_H_8814B 0x0324 +#define REG_ACH2_TXBD_DESA_L_8814B 0x0328 +#define REG_ACH2_TXBD_DESA_H_8814B 0x032C +#define REG_ACH3_TXBD_DESA_L_8814B 0x0330 +#define REG_ACH3_TXBD_DESA_H_8814B 0x0334 +#define REG_P0RXQ_RXBD_DESA_L_8814B 0x0338 +#define REG_P0RXQ_RXBD_DESA_H_8814B 0x033C +#define REG_P0BCNQ_TXBD_DESA_L_8814B 0x0340 +#define REG_P0BCNQ_TXBD_DESA_H_8814B 0x0344 +#define REG_FWCMDQ_TXBD_DESA_L_8814B 0x0348 +#define REG_FWCMDQ_TXBD_DESA_H_8814B 0x034C +#define REG_PCIE_HRPWM1_HCPWM1_DCPU_8814B 0x0354 +#define REG_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0x0358 +#define REG_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0x035C +#define REG_P0_MPRT_BCNQ_TXRXBD_NUM_8814B 0x036C +#define REG_BD_RWPTR_CLR2_8814B 0x0370 +#define REG_BD_RWPTR_CLR3_8814B 0x0374 +#define REG_P0MGQ_RXQ_TXRXBD_NUM_8814B 0x0378 +#define REG_CHNL_DMA_CFG_8814B 0x037C +#define REG_FWCMDQ_TXBD_NUM_8814B 0x0380 +#define REG_ACH0_ACH1_TXBD_NUM_8814B 0x0384 +#define REG_ACH2_ACH3_TXBD_NUM_8814B 0x0388 +#define REG_P0HI0Q_HI1Q_TXBD_NUM_8814B 0x038C +#define REG_P0HI2Q_HI3Q_TXBD_NUM_8814B 0x0390 +#define REG_P0HI4Q_HI5Q_TXBD_NUM_8814B 0x0394 +#define REG_P0HI6Q_HI7Q_TXBD_NUM_8814B 0x0398 +#define REG_BD_RWPTR_CLR1_8814B 0x039C #define REG_TSFTIMER_HCI_8814B 0x039C -#define REG_BD_RWPTR_CLR_8814B 0x039C -#define REG_VOQ_TXBD_IDX_8814B 0x03A0 -#define REG_VIQ_TXBD_IDX_8814B 0x03A4 -#define REG_BEQ_TXBD_IDX_8814B 0x03A8 -#define REG_BKQ_TXBD_IDX_8814B 0x03AC -#define REG_MGQ_TXBD_IDX_8814B 0x03B0 -#define REG_RXQ_RXBD_IDX_8814B 0x03B4 -#define REG_HI0Q_TXBD_IDX_8814B 0x03B8 -#define REG_HI1Q_TXBD_IDX_8814B 0x03BC -#define REG_HI2Q_TXBD_IDX_8814B 0x03C0 -#define REG_HI3Q_TXBD_IDX_8814B 0x03C4 -#define REG_HI4Q_TXBD_IDX_8814B 0x03C8 -#define REG_HI5Q_TXBD_IDX_8814B 0x03CC -#define REG_HI6Q_TXBD_IDX_8814B 0x03D0 -#define REG_HI7Q_TXBD_IDX_8814B 0x03D4 -#define REG_DBG_SEL_V1_8814B 0x03D8 -#define REG_PCIE_HRPWM1_V1_8814B 0x03D9 -#define REG_PCIE_HCPWM1_V1_8814B 0x03DA -#define REG_PCIE_CTRL2_8814B 0x03DB -#define REG_PCIE_HRPWM2_V1_8814B 0x03DC -#define REG_PCIE_HCPWM2_V1_8814B 0x03DE +#define REG_ACH0_TXBD_IDX_8814B 0x03A0 +#define REG_ACH1_TXBD_IDX_8814B 0x03A4 +#define REG_ACH2_TXBD_IDX_8814B 0x03A8 +#define REG_ACH3_TXBD_IDX_8814B 0x03AC +#define REG_P0MGQ_TXBD_IDX_8814B 0x03B0 +#define REG_P0RXQ_RXBD_IDX_8814B 0x03B4 +#define REG_P0HI0Q_TXBD_IDX_8814B 0x03B8 +#define REG_P0HI1Q_TXBD_IDX_8814B 0x03BC +#define REG_P0HI2Q_TXBD_IDX_8814B 0x03C0 +#define REG_P0HI3Q_TXBD_IDX_8814B 0x03C4 +#define REG_P0HI4Q_TXBD_IDX_8814B 0x03C8 +#define REG_P0HI5Q_TXBD_IDX_8814B 0x03CC +#define REG_P0HI6Q_TXBD_IDX_8814B 0x03D0 +#define REG_P0HI7Q_TXBD_IDX_8814B 0x03D4 +#define REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1_8814B 0x03D8 +#define REG_PCIE_HRPWM2_HCPWM2_V1_8814B 0x03DC #define REG_PCIE_H2C_MSG_V1_8814B 0x03E0 #define REG_PCIE_C2H_MSG_V1_8814B 0x03E4 #define REG_DBI_WDATA_V1_8814B 0x03E8 @@ -289,47 +431,165 @@ #define REG_HCI_MIX_CFG_8814B 0x03FC #define REG_STC_INT_CS_8814B 0x1300 #define REG_ST_INT_CFG_8814B 0x1304 -#define REG_CMU_DLY_CTRL_8814B 0x1310 -#define REG_CMU_DLY_CFG_8814B 0x1314 -#define REG_H2CQ_TXBD_DESA_8814B 0x1320 +#define REG_ACH4_ACH5_TXBD_NUM_8814B 0x130C +#define REG_FWCMDQ_TXBD_IDX_8814B 0x1318 +#define REG_P0HI8Q_TXBD_IDX_8814B 0x131C +#define REG_H2CQ_TXBD_DESA_L_8814B 0x1320 +#define REG_H2CQ_TXBD_DESA_H_8814B 0x1324 #define REG_H2CQ_TXBD_NUM_8814B 0x1328 #define REG_H2CQ_TXBD_IDX_8814B 0x132C #define REG_H2CQ_CSR_8814B 0x1330 -#define REG_Q0_INFO_8814B 0x0400 -#define REG_Q1_INFO_8814B 0x0404 -#define REG_Q2_INFO_8814B 0x0408 -#define REG_Q3_INFO_8814B 0x040C -#define REG_MGQ_INFO_8814B 0x0410 -#define REG_HIQ_INFO_8814B 0x0414 -#define REG_BCNQ_INFO_8814B 0x0418 -#define REG_TXPKT_EMPTY_8814B 0x041A +#define REG_P0HI9Q_TXBD_IDX_8814B 0x1334 +#define REG_P0HI10Q_TXBD_IDX_8814B 0x1338 +#define REG_P0HI11Q_TXBD_IDX_8814B 0x133C +#define REG_P0HI12Q_TXBD_IDX_8814B 0x1340 +#define REG_P0HI13Q_TXBD_IDX_8814B 0x1344 +#define REG_P0HI14Q_TXBD_IDX_8814B 0x1348 +#define REG_P0HI15Q_TXBD_IDX_8814B 0x134C +#define REG_CHANGE_PCIE_SPEED_8814B 0x1350 +#define REG_DEBUG_STATE1_8814B 0x1354 +#define REG_DEBUG_STATE2_8814B 0x1358 +#define REG_DEBUG_STATE3_8814B 0x135C +#define REG_ACH5_TXBD_DESA_L_8814B 0x1360 +#define REG_ACH5_TXBD_DESA_H_8814B 0x1364 +#define REG_ACH6_TXBD_DESA_L_8814B 0x1368 +#define REG_ACH6_TXBD_DESA_H_8814B 0x136C +#define REG_ACH7_TXBD_DESA_L_8814B 0x1370 +#define REG_ACH7_TXBD_DESA_H_8814B 0x1374 +#define REG_ACH8_TXBD_DESA_L_8814B 0x1378 +#define REG_ACH8_TXBD_DESA_H_8814B 0x137C +#define REG_ACH9_TXBD_DESA_L_8814B 0x1380 +#define REG_ACH9_TXBD_DESA_H_8814B 0x1384 +#define REG_ACH10_TXBD_DESA_L_8814B 0x1388 +#define REG_ACH10_TXBD_DESA_H_8814B 0x138C +#define REG_ACH11_TXBD_DESA_L_8814B 0x1390 +#define REG_ACH11_TXBD_DESA_H_8814B 0x1394 +#define REG_ACH12_TXBD_DESA_L_8814B 0x1398 +#define REG_ACH12_TXBD_DESA_H_8814B 0x139C +#define REG_ACH13_TXBD_DESA_L_8814B 0x13A0 +#define REG_ACH13_TXBD_DESA_H_8814B 0x13A4 +#define REG_HI0Q_TXBD_DESA_L_8814B 0x13A8 +#define REG_HI0Q_TXBD_DESA_H_8814B 0x13AC +#define REG_HI1Q_TXBD_DESA_L_8814B 0x13B0 +#define REG_HI1Q_TXBD_DESA_H_8814B 0x13B4 +#define REG_HI2Q_TXBD_DESA_L_8814B 0x13B8 +#define REG_HI2Q_TXBD_DESA_H_8814B 0x13BC +#define REG_HI3Q_TXBD_DESA_L_8814B 0x13C0 +#define REG_HI3Q_TXBD_DESA_H_8814B 0x13C4 +#define REG_HI4Q_TXBD_DESA_L_8814B 0x13C8 +#define REG_HI4Q_TXBD_DESA_H_8814B 0x13CC +#define REG_HI5Q_TXBD_DESA_L_8814B 0x13D0 +#define REG_HI5Q_TXBD_DESA_H_8814B 0x13D4 +#define REG_HI6Q_TXBD_DESA_L_8814B 0x13D8 +#define REG_HI6Q_TXBD_DESA_H_8814B 0x13DC +#define REG_HI7Q_TXBD_DESA_L_8814B 0x13E0 +#define REG_HI7Q_TXBD_DESA_H_8814B 0x13E4 +#define REG_ACH8_ACH9_TXBD_NUM_8814B 0x13E8 +#define REG_ACH10_ACH11_TXBD_NUM_8814B 0x13EC +#define REG_ACH12_ACH13_TXBD_NUM_8814B 0x13F0 +#define REG_OLD_DEHANG_8814B 0x13F4 +#define REG_ACH4_TXBD_DESA_L_8814B 0x13F8 +#define REG_ACH4_TXBD_DESA_H_8814B 0x13FC +#define REG_HI8Q_TXBD_DESA_L_8814B 0x2300 +#define REG_HI8Q_TXBD_DESA_H_8814B 0x2304 +#define REG_HI9Q_TXBD_DESA_L_8814B 0x2308 +#define REG_HI9Q_TXBD_DESA_H_8814B 0x230C +#define REG_HI10Q_TXBD_DESA_L_8814B 0x2310 +#define REG_HI10Q_TXBD_DESA_H_8814B 0x2314 +#define REG_HI11Q_TXBD_DESA_L_8814B 0x2318 +#define REG_HI11Q_TXBD_DESA_H_8814B 0x231C +#define REG_HI12Q_TXBD_DESA_L_8814B 0x2320 +#define REG_HI12Q_TXBD_DESA_H_8814B 0x2324 +#define REG_HI13Q_TXBD_DESA_L_8814B 0x2328 +#define REG_HI13Q_TXBD_DESA_H_8814B 0x232C +#define REG_HI14Q_TXBD_DESA_L_8814B 0x2330 +#define REG_HI14Q_TXBD_DESA_H_8814B 0x2334 +#define REG_HI15Q_TXBD_DESA_L_8814B 0x2338 +#define REG_HI15Q_TXBD_DESA_H_8814B 0x233C +#define REG_HI16Q_TXBD_DESA_L_8814B 0x2340 +#define REG_HI16Q_TXBD_DESA_H_8814B 0x2344 +#define REG_HI17Q_TXBD_DESA_L_8814B 0x2348 +#define REG_HI17Q_TXBD_DESA_H_8814B 0x234C +#define REG_HI18Q_TXBD_DESA_L_8814B 0x2350 +#define REG_HI18Q_TXBD_DESA_H_8814B 0x2354 +#define REG_HI19Q_TXBD_DESA_L_8814B 0x2358 +#define REG_HI19Q_TXBD_DESA_H_8814B 0x235C +#define REG_BD_RWPTR_CLR6_8814B 0x2364 +#define REG_P0HI16Q_TXBD_IDX_8814B 0x2370 +#define REG_P0HI17Q_TXBD_IDX_8814B 0x2374 +#define REG_P0HI18Q_TXBD_IDX_8814B 0x2378 +#define REG_P0HI19Q_TXBD_IDX_8814B 0x237C +#define REG_P0HI16Q_HI17Q_TXBD_NUM_8814B 0x2380 +#define REG_P0HI18Q_HI19Q_TXBD_NUM_8814B 0x2384 +#define REG_PCIE_HISR0_8814B 0x23B4 +#define REG_PCIE_HISR1_8814B 0x23BC +#define REG_P0HI8Q_HI9Q_TXBD_NUM_8814B 0x23C0 +#define REG_P0HI10Q_HI11Q_TXBD_NUM_8814B 0x23C4 +#define REG_P0HI12Q_HI13Q_TXBD_NUM_8814B 0x23C8 +#define REG_P0HI14Q_HI15Q_TXBD_NUM_8814B 0x23CC +#define REG_ACH6_ACH7_TXBD_NUM_8814B 0x23F0 +#define REG_ACH4_TXBD_IDX_8814B 0x3340 +#define REG_ACH5_TXBD_IDX_8814B 0x3344 +#define REG_ACH6_TXBD_IDX_8814B 0x3348 +#define REG_ACH7_TXBD_IDX_8814B 0x334C +#define REG_ACH8_TXBD_IDX_8814B 0x3350 +#define REG_ACH9_TXBD_IDX_8814B 0x3354 +#define REG_ACH10_TXBD_IDX_8814B 0x3358 +#define REG_ACH11_TXBD_IDX_8814B 0x335C +#define REG_ACH12_TXBD_IDX_8814B 0x3360 +#define REG_ACH13_TXBD_IDX_8814B 0x3364 +#define REG_AC_CHANNEL0_WEIGHT_8814B 0x3368 +#define REG_AC_CHANNEL1_WEIGHT_8814B 0x3369 +#define REG_AC_CHANNEL2_WEIGHT_8814B 0x336A +#define REG_AC_CHANNEL3_WEIGHT_8814B 0x336B +#define REG_AC_CHANNEL4_WEIGHT_8814B 0x336C +#define REG_AC_CHANNEL5_WEIGHT_8814B 0x336D +#define REG_AC_CHANNEL6_WEIGHT_8814B 0x336E +#define REG_AC_CHANNEL7_WEIGHT_8814B 0x336F +#define REG_AC_CHANNEL8_WEIGHT_8814B 0x3370 +#define REG_AC_CHANNEL9_WEIGHT_8814B 0x3371 +#define REG_AC_CHANNEL10_WEIGHT_8814B 0x3372 +#define REG_AC_CHANNEL11_WEIGHT_8814B 0x3373 +#define REG_AC_CHANNEL12_WEIGHT_8814B 0x3374 +#define REG_AC_CHANNEL13_WEIGHT_8814B 0x3375 +#define REG_PCIE_HISR2_8814B 0x33B4 +#define REG_PCIE_HISR3_8814B 0x33BC +#define REG_QUEUELIST_INFO0_8814B 0x0400 +#define REG_QUEUELIST_INFO1_8814B 0x0404 +#define REG_QUEUELIST_INFO2_8814B 0x0408 +#define REG_QUEUELIST_INFO3_8814B 0x040C +#define REG_QUEUELIST_INFO_EMPTY_8814B 0x0410 +#define REG_QUEUELIST_ACQ_EN_8814B 0x0414 +#define REG_BCNQ_BDNY_V2_8814B 0x0418 #define REG_CPU_MGQ_INFO_8814B 0x041C #define REG_FWHW_TXQ_CTRL_8814B 0x0420 #define REG_DATAFB_SEL_8814B 0x0423 -#define REG_BCNQ_BDNY_V1_8814B 0x0424 +#define REG_TXBDNY_8814B 0x0424 #define REG_LIFETIME_EN_8814B 0x0426 #define REG_SPEC_SIFS_8814B 0x0428 #define REG_RETRY_LIMIT_8814B 0x042A #define REG_TXBF_CTRL_8814B 0x042C #define REG_DARFRC_8814B 0x0430 +#define REG_DARFRCH_8814B 0x0434 #define REG_RARFRC_8814B 0x0438 +#define REG_RARFRCH_8814B 0x043C #define REG_RRSR_8814B 0x0440 #define REG_ARFR0_8814B 0x0444 -#define REG_ARFR1_V1_8814B 0x044C +#define REG_ARFRH0_8814B 0x0448 +#define REG_REG_ARFR_WT0_8814B 0x044C +#define REG_REG_ARFR_WT1_8814B 0x0450 #define REG_CCK_CHECK_8814B 0x0454 #define REG_AMPDU_MAX_TIME_V1_8814B 0x0455 -#define REG_BCNQ1_BDNY_V1_8814B 0x0456 -#define REG_AMPDU_MAX_LENGTH_8814B 0x0458 -#define REG_ACQ_STOP_8814B 0x045C +#define REG_TAB_SEL_8814B 0x0456 +#define REG_BCN_INVALID_CTRL_8814B 0x0457 +#define REG_AMPDU_MAX_LENGTH_HT_8814B 0x0458 #define REG_NDPA_RATE_8814B 0x045D #define REG_TX_HANG_CTRL_8814B 0x045E #define REG_NDPA_OPT_CTRL_8814B 0x045F +#define REG_AMPDU_MAX_LENGTH_VHT_8814B 0x0460 #define REG_RD_RESP_PKT_TH_8814B 0x0463 -#define REG_CMDQ_INFO_8814B 0x0464 -#define REG_Q4_INFO_8814B 0x0468 -#define REG_Q5_INFO_8814B 0x046C -#define REG_Q6_INFO_8814B 0x0470 -#define REG_Q7_INFO_8814B 0x0474 +#define REG_NEW_EDCA_CTRL_V1_8814B 0x0464 +#define REG_ACQ_STOP_V2_8814B 0x0468 #define REG_WMAC_LBK_BUF_HD_V1_8814B 0x0478 #define REG_MGQ_BDNY_V1_8814B 0x047A #define REG_TXRPT_CTRL_8814B 0x047C @@ -337,12 +597,8 @@ #define REG_BASIC_CFEND_RATE_8814B 0x0481 #define REG_STBC_CFEND_RATE_8814B 0x0482 #define REG_DATA_SC_8814B 0x0483 -#define REG_MACID_SLEEP3_8814B 0x0484 -#define REG_MACID_SLEEP1_8814B 0x0488 -#define REG_ARFR2_V1_8814B 0x048C -#define REG_ARFR3_V1_8814B 0x0494 -#define REG_ARFR4_8814B 0x049C -#define REG_ARFR5_8814B 0x04A4 +#define REG_MOREDATA_V1_8814B 0x0484 +#define REG_DATA_SC1_8814B 0x0487 #define REG_TXRPT_START_OFFSET_8814B 0x04AC #define REG_POWER_STAGE1_8814B 0x04B4 #define REG_POWER_STAGE2_8814B 0x04B8 @@ -355,55 +611,62 @@ #define REG_PROT_MODE_CTRL_8814B 0x04C8 #define REG_BAR_MODE_CTRL_8814B 0x04CC #define REG_RA_TRY_RATE_AGG_LMT_8814B 0x04CF -#define REG_MACID_SLEEP2_8814B 0x04D0 -#define REG_MACID_SLEEP_8814B 0x04D4 +#define REG_MACID_SLEEP_CTRL_8814B 0x04D0 +#define REG_MACID_SLEEP_INFO_8814B 0x04D4 #define REG_HW_SEQ0_8814B 0x04D8 #define REG_HW_SEQ1_8814B 0x04DA #define REG_HW_SEQ2_8814B 0x04DC #define REG_HW_SEQ3_8814B 0x04DE -#define REG_NULL_PKT_STATUS_V1_8814B 0x04E0 -#define REG_PTCL_ERR_STATUS_8814B 0x04E2 -#define REG_NULL_PKT_STATUS_EXTEND_8814B 0x04E3 -#define REG_VIDEO_ENHANCEMENT_FUN_8814B 0x04E4 -#define REG_BT_POLLUTE_PKT_CNT_8814B 0x04E8 -#define REG_PTCL_DBG_8814B 0x04EC +#define REG_PTCL_ERR_STATUS_V1_8814B 0x04E2 +#define REG_NULL_PKT_STATUS_V2_8814B 0x04E4 +#define REG_PRECNT_CTRL_8814B 0x04E5 +#define REG_NULL_PKT_STATUS_EXTEND_V1_8814B 0x04E7 +#define REG_PTCL_DBG_V1_8814B 0x04EC +#define REG_BT_POLLUTE_PKTCNT_8814B 0x04F0 #define REG_CPUMGQ_TIMER_CTRL2_8814B 0x04F4 +#define REG_PTCL_DBG_OUT_8814B 0x04F8 #define REG_DUMMY_PAGE4_V1_8814B 0x04FC -#define REG_MOREDATA_8814B 0x04FE -#define REG_Q0_Q1_INFO_8814B 0x1400 -#define REG_Q2_Q3_INFO_8814B 0x1404 -#define REG_Q4_Q5_INFO_8814B 0x1408 -#define REG_Q6_Q7_INFO_8814B 0x140C -#define REG_MGQ_HIQ_INFO_8814B 0x1410 -#define REG_CMDQ_BCNQ_INFO_8814B 0x1414 -#define REG_USEREG_SETTING_8814B 0x1420 -#define REG_AESIV_SETTING_8814B 0x1424 +#define REG_DUMMY_PAGE4_1_8814B 0x04FE +#define REG_MU_OFFSET_8814B 0x1400 #define REG_BF0_TIME_SETTING_8814B 0x1428 #define REG_BF1_TIME_SETTING_8814B 0x142C #define REG_BF_TIMEOUT_EN_8814B 0x1430 -#define REG_MACID_RELEASE0_8814B 0x1434 -#define REG_MACID_RELEASE1_8814B 0x1438 -#define REG_MACID_RELEASE2_8814B 0x143C -#define REG_MACID_RELEASE3_8814B 0x1440 -#define REG_MACID_RELEASE_SETTING_8814B 0x1444 +#define REG_MACID_RELEASE_INFO_8814B 0x1434 +#define REG_MACID_RELEASE_SUCCESS_INFO_8814B 0x1438 +#define REG_MACID_RELEASE_CTRL_8814B 0x143C #define REG_FAST_EDCA_VOVI_SETTING_8814B 0x1448 #define REG_FAST_EDCA_BEBK_SETTING_8814B 0x144C -#define REG_MACID_DROP0_8814B 0x1450 -#define REG_MACID_DROP1_8814B 0x1454 -#define REG_MACID_DROP2_8814B 0x1458 -#define REG_MACID_DROP3_8814B 0x145C -#define REG_R_MACID_RELEASE_SUCCESS_0_8814B 0x1460 -#define REG_R_MACID_RELEASE_SUCCESS_1_8814B 0x1464 -#define REG_R_MACID_RELEASE_SUCCESS_2_8814B 0x1468 -#define REG_R_MACID_RELEASE_SUCCESS_3_8814B 0x146C -#define REG_MGG_FIFO_CRTL_8814B 0x1470 -#define REG_MGG_FIFO_INT_8814B 0x1474 -#define REG_MGG_FIFO_LIFETIME_8814B 0x1478 -#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8814B 0x147C -#define REG_MU_TX_CTL_8814B 0x14C0 +#define REG_MACID_DROP_INFO_8814B 0x1450 +#define REG_MACID_DROP_CTRL_8814B 0x1454 +#define REG_MGQ_FIFO_WRITE_POINTER_8814B 0x1470 +#define REG_MGQ_FIFO_READ_POINTER_8814B 0x1472 +#define REG_MGQ_FIFO_ENABLE_8814B 0x1472 +#define REG_MGQ_FIFO_RELEASE_INT_MASK_8814B 0x1474 +#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8814B 0x1476 +#define REG_MGQ_FIFO_VALID_MAP_8814B 0x1478 +#define REG_MGQ_FIFO_LIFETIME_8814B 0x147A +#define REG_PKT_TRANS_8814B 0x1480 +#define REG_SHCUT_LLC_ETH_TYPE0_8814B 0x1484 +#define REG_SHCUT_LLC_ETH_TYPE1_8814B 0x1488 +#define REG_SHCUT_LLC_OUI0_8814B 0x148C +#define REG_SHCUT_LLC_OUI1_8814B 0x1490 +#define REG_SHCUT_LLC_OUI2_8814B 0x1494 +#define REG_FWCMDQ_CTRL_8814B 0x14A0 +#define REG_FWCMDQ_PAGE_8814B 0x14A4 +#define REG_FWCMDQ_INFO_8814B 0x14A8 +#define REG_FWCMDQ_HOLD_PKTNUM_8814B 0x14AC +#define REG_MU_TX_CTRL_8814B 0x14C0 #define REG_MU_STA_GID_VLD_8814B 0x14C4 #define REG_MU_STA_USER_POS_INFO_8814B 0x14C8 -#define REG_MU_TRX_DBG_CNT_8814B 0x14D0 +#define REG_MU_STA_USER_POS_INFO_H_8814B 0x14CC +#define REG_CHNL_INFO_CTRL_8814B 0x14D0 +#define REG_CHNL_IDLE_TIME_8814B 0x14D4 +#define REG_CHNL_BUSY_TIME_8814B 0x14D8 +#define REG_MU_TRX_DBG_CNT_V1_8814B 0x14DC +#define REG_SWPS_CTRL_8814B 0x14F4 +#define REG_SWPS_PKT_TH_8814B 0x14F6 +#define REG_SWPS_TIME_TH_8814B 0x14F8 +#define REG_MACID_SWPS_EN_8814B 0x14FC #define REG_EDCA_VO_PARAM_8814B 0x0500 #define REG_EDCA_VI_PARAM_8814B 0x0504 #define REG_EDCA_BE_PARAM_8814B 0x0508 @@ -412,126 +675,142 @@ #define REG_PIFS_8814B 0x0512 #define REG_RDG_PIFS_8814B 0x0513 #define REG_SIFS_8814B 0x0514 -#define REG_TSFTR_SYN_OFFSET_8814B 0x0518 +#define REG_FORCE_BCN_IFS_V1_8814B 0x0518 #define REG_AGGR_BREAK_TIME_8814B 0x051A #define REG_SLOT_8814B 0x051B +#define REG_EDCA_CPUMGQ_PARAM_8814B 0x051C +#define REG_CPUMGQ_PAUSE_8814B 0x051E #define REG_TX_PTCL_CTRL_8814B 0x0520 #define REG_TXPAUSE_8814B 0x0522 #define REG_DIS_TXREQ_CLR_8814B 0x0523 #define REG_RD_CTRL_8814B 0x0524 -#define REG_MBSSID_CTRL_8814B 0x0526 -#define REG_P2PPS_CTRL_8814B 0x0527 #define REG_PKT_LIFETIME_CTRL_8814B 0x0528 -#define REG_P2PPS_SPEC_STATE_8814B 0x052B -#define REG_BAR_TX_CTRL_8814B 0x0530 -#define REG_TBTT_PROHIBIT_8814B 0x0540 -#define REG_P2PPS_STATE_8814B 0x0543 +#define REG_TXOP_LIMIT_CTRL_8814B 0x052C +#define REG_CCA_TXEN_CNT_8814B 0x0534 +#define REG_MAX_INTER_COLLISION_8814B 0x0538 +#define REG_MAX_INTER_COLLISION_CNT_8814B 0x053C #define REG_RD_NAV_NXT_8814B 0x0544 #define REG_NAV_PROT_LEN_8814B 0x0546 -#define REG_BCN_CTRL_8814B 0x0550 -#define REG_BCN_CTRL_CLINT0_8814B 0x0551 -#define REG_MBID_NUM_8814B 0x0552 -#define REG_DUAL_TSF_RST_8814B 0x0553 -#define REG_MBSSID_BCN_SPACE_8814B 0x0554 -#define REG_DRVERLYINT_8814B 0x0558 -#define REG_BCNDMATIM_8814B 0x0559 -#define REG_ATIMWND_8814B 0x055A -#define REG_USTIME_TSF_8814B 0x055C -#define REG_BCN_MAX_ERR_8814B 0x055D -#define REG_RXTSF_OFFSET_CCK_8814B 0x055E -#define REG_RXTSF_OFFSET_OFDM_8814B 0x055F -#define REG_TSFTR_8814B 0x0560 -#define REG_TSFTR_1_8814B 0x0564 -#define REG_FREERUN_CNT_8814B 0x0568 -#define REG_FREERUN_CNT_1_8814B 0x056C -#define REG_ATIMWND1_V1_8814B 0x0570 -#define REG_TBTT_PROHIBIT_INFRA_8814B 0x0571 -#define REG_CTWND_8814B 0x0572 -#define REG_BCNIVLCUNT_8814B 0x0573 -#define REG_BCNDROPCTRL_8814B 0x0574 +#define REG_FTM_PTT_8814B 0x0548 +#define REG_FTM_TSF_8814B 0x054C #define REG_HGQ_TIMEOUT_PERIOD_8814B 0x0575 #define REG_TXCMD_TIMEOUT_PERIOD_8814B 0x0576 #define REG_MISC_CTRL_8814B 0x0577 -#define REG_BCN_CTRL_CLINT1_8814B 0x0578 -#define REG_BCN_CTRL_CLINT2_8814B 0x0579 -#define REG_BCN_CTRL_CLINT3_8814B 0x057A -#define REG_EXTEND_CTRL_8814B 0x057B -#define REG_P2PPS1_SPEC_STATE_8814B 0x057C -#define REG_P2PPS1_STATE_8814B 0x057D -#define REG_P2PPS2_SPEC_STATE_8814B 0x057E -#define REG_P2PPS2_STATE_8814B 0x057F -#define REG_PS_TIMER0_8814B 0x0580 -#define REG_PS_TIMER1_8814B 0x0584 -#define REG_PS_TIMER2_8814B 0x0588 -#define REG_TBTT_CTN_AREA_8814B 0x058C -#define REG_FORCE_BCN_IFS_8814B 0x058E #define REG_TXOP_MIN_8814B 0x0590 #define REG_PRE_BKF_TIME_8814B 0x0592 #define REG_CROSS_TXOP_CTRL_8814B 0x0593 -#define REG_ATIMWND2_8814B 0x05A0 -#define REG_ATIMWND3_8814B 0x05A1 -#define REG_ATIMWND4_8814B 0x05A2 -#define REG_ATIMWND5_8814B 0x05A3 -#define REG_ATIMWND6_8814B 0x05A4 -#define REG_ATIMWND7_8814B 0x05A5 -#define REG_ATIMUGT_8814B 0x05A6 -#define REG_HIQ_NO_LMT_EN_8814B 0x05A7 -#define REG_DTIM_COUNTER_ROOT_8814B 0x05A8 -#define REG_DTIM_COUNTER_VAP1_8814B 0x05A9 -#define REG_DTIM_COUNTER_VAP2_8814B 0x05AA -#define REG_DTIM_COUNTER_VAP3_8814B 0x05AB -#define REG_DTIM_COUNTER_VAP4_8814B 0x05AC -#define REG_DTIM_COUNTER_VAP5_8814B 0x05AD -#define REG_DTIM_COUNTER_VAP6_8814B 0x05AE -#define REG_DTIM_COUNTER_VAP7_8814B 0x05AF -#define REG_DIS_ATIM_8814B 0x05B0 -#define REG_EARLY_128US_8814B 0x05B1 -#define REG_P2PPS1_CTRL_8814B 0x05B2 -#define REG_P2PPS2_CTRL_8814B 0x05B3 -#define REG_TIMER0_SRC_SEL_8814B 0x05B4 -#define REG_NOA_UNIT_SEL_8814B 0x05B5 -#define REG_P2POFF_DIS_TXTIME_8814B 0x05B7 -#define REG_MBSSID_BCN_SPACE2_8814B 0x05B8 -#define REG_MBSSID_BCN_SPACE3_8814B 0x05BC #define REG_ACMHWCTRL_8814B 0x05C0 #define REG_ACMRSTCTRL_8814B 0x05C1 #define REG_ACMAVG_8814B 0x05C2 #define REG_VO_ADMTIME_8814B 0x05C4 #define REG_VI_ADMTIME_8814B 0x05C6 #define REG_BE_ADMTIME_8814B 0x05C8 +#define REG_MAC_HEADER_NAV_OFFSET_8814B 0x05CA +#define REG_DIS_NDPA_NAV_CHECK_8814B 0x05CB #define REG_EDCA_RANDOM_GEN_8814B 0x05CC -#define REG_TXCMD_NOA_SEL_8814B 0x05CF -#define REG_NOA_PARAM_8814B 0x05E0 -#define REG_NOA_PARAM_1_8814B 0x05E4 -#define REG_NOA_PARAM_2_8814B 0x05E8 -#define REG_NOA_PARAM_3_8814B 0x05EC -#define REG_P2P_RST_8814B 0x05F0 +#define REG_TXCMD_SEL_8814B 0x05CF +#define REG_MU_DBG_INFO_8814B 0x05E8 +#define REG_MU_DBG_INFO_1_8814B 0x05EC +#define REG_SCH_DBG_SEL_8814B 0x05F0 #define REG_SCHEDULER_RST_8814B 0x05F1 +#define REG_MU_DBG_ERR_FLAG_8814B 0x05F2 +#define REG_TX_ERR_RECOVERY_RST_8814B 0x05F3 +#define REG_SCH_DBG_VALUE_8814B 0x05F4 #define REG_SCH_TXCMD_8814B 0x05F8 #define REG_PAGE5_DUMMY_8814B 0x05FC -#define REG_CPUMGQ_TX_TIMER_8814B 0x1500 -#define REG_PS_TIMER_A_8814B 0x1504 -#define REG_PS_TIMER_B_8814B 0x1508 -#define REG_PS_TIMER_C_8814B 0x150C -#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8814B 0x1510 -#define REG_CPUMGQ_TX_TIMER_EARLY_8814B 0x1514 -#define REG_PS_TIMER_A_EARLY_8814B 0x1515 -#define REG_PS_TIMER_B_EARLY_8814B 0x1516 -#define REG_PS_TIMER_C_EARLY_8814B 0x1517 +#define REG_PORT_CTRL_SEL_8814B 0x1500 +#define REG_PORT_CTRL_CFG_8814B 0x1501 +#define REG_TBTT_PROHIBIT_CFG_8814B 0x1504 +#define REG_DRVERLYINT_CFG_8814B 0x1507 +#define REG_BCNDMATIM_CFG_8814B 0x1508 +#define REG_CTWND_CFG_8814B 0x1509 +#define REG_BCNIVLCUNT_CFG_8814B 0x150A +#define REG_EARLY_128US_CFG_8814B 0x150B +#define REG_TSFTR_SYNC_OFFSET_CFG_8814B 0x150C +#define REG_TSFTR_SYNC_CTRL_CFG_8814B 0x150F +#define REG_BCN_SPACE_CFG_8814B 0x1510 +#define REG_EARLY_INT_ADJUST_CFG_8814B 0x1512 +#define REG_SW_TBTT_TSF_INFO_8814B 0x151C +#define REG_TSFTR_LOW_8814B 0x1520 +#define REG_TSFTR_HIGH_8814B 0x1524 +#define REG_BCN_ERR_CNT_MAC_8814B 0x1528 +#define REG_BCN_ERR_CNT_EDCCA_8814B 0x1529 +#define REG_BCN_ERR_CNT_CCA_8814B 0x152A +#define REG_BCN_ERR_CNT_INVALID_8814B 0x152B +#define REG_BCN_ERR_CNT_OTHERS_8814B 0x152C +#define REG_RX_BCN_TIMER_8814B 0x152D +#define REG_TBTT_CTN_AREA_V1_8814B 0x1530 +#define REG_BCN_MAX_ERR_V1_8814B 0x1531 +#define REG_RXTSF_OFFSET_CCK_V1_8814B 0x1532 +#define REG_RXTSF_OFFSET_OFDM_V1_8814B 0x1533 +#define REG_SUB_BCN_SPACE_8814B 0x1534 +#define REG_MBID_NUM_V1_8814B 0x1535 +#define REG_MBSSID_CTRL_V1_8814B 0x1536 +#define REG_USTIME_TSF_V1_8814B 0x1538 +#define REG_BW_CFG_8814B 0x1539 +#define REG_ATIMWND_CFG_8814B 0x153A +#define REG_DTIM_COUNTER_CFG_8814B 0x153B +#define REG_ATIM_DTIM_CTRL_SEL_8814B 0x153C +#define REG_ATIMUGT_V1_8814B 0x153D +#define REG_BCNDROPCTRL_V1_8814B 0x153E +#define REG_DIS_ATIM_V1_8814B 0x1540 +#define REG_HIQ_NO_LMT_EN_V1_8814B 0x1544 +#define REG_P2PPS_CTRL_V1_8814B 0x1548 +#define REG_P2PPS_SPEC_STATE_V1_8814B 0x154A +#define REG_P2PPS_STATE_V1_8814B 0x154B +#define REG_P2PPS1_CTRL_V1_8814B 0x154C +#define REG_P2PPS1_SPEC_STATE_V1_8814B 0x154E +#define REG_P2PPS1_STATE_V1_8814B 0x154F +#define REG_P2PPS2_CTRL_V1_8814B 0x1550 +#define REG_P2PPS2_SPEC_STATE_V1_8814B 0x1552 +#define REG_P2PPS2_STATE_V1_8814B 0x1553 +#define REG_P2PON_DIS_TXTIME_V1_8814B 0x1554 +#define REG_P2POFF_DIS_TXTIME_V1_8814B 0x1555 +#define REG_CHG_POWER_BCN_AREA_8814B 0x1556 +#define REG_NOA_SEL_8814B 0x1557 +#define REG_NOA_PARAM_V1_8814B 0x1558 +#define REG_NOA_PARAM_1_V1_8814B 0x155C +#define REG_NOA_PARAM_2_V1_8814B 0x1560 +#define REG_NOA_PARAM_3_V1_8814B 0x1564 +#define REG_NOA_ON_ERLY_TIME_V1_8814B 0x1568 +#define REG_NOA_OFF_ERLY_TIME_V1_8814B 0x1569 +#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8814B 0x156C +#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8814B 0x1570 +#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8814B 0x1574 +#define REG_RX_TBTT_SHIFT_8814B 0x1578 +#define REG_FREERUN_CNT_LOW_8814B 0x1580 +#define REG_FREERUN_CNT_HIGH_8814B 0x1584 +#define REG_CPUMGQ_TX_TIMER_V1_8814B 0x1588 +#define REG_PS_TIMER_0_8814B 0x158C +#define REG_PS_TIMER_1_8814B 0x1590 +#define REG_PS_TIMER_2_8814B 0x1594 +#define REG_PS_TIMER_3_8814B 0x1598 +#define REG_PS_TIMER_4_8814B 0x159C +#define REG_PS_TIMER_5_8814B 0x15A0 +#define REG_PS_TIMER_01_CTRL_8814B 0x15A4 +#define REG_PS_TIMER_23_CTRL_8814B 0x15A8 +#define REG_PS_TIMER_45_CTRL_8814B 0x15AC +#define REG_CPUMGQ_FREERUN_TIMER_CTRL_8814B 0x15B0 +#define REG_CPUMGQ_PROHIBIT_8814B 0x15B4 +#define REG_TIMER_COMPARE_8814B 0x15C0 +#define REG_TIMER_COMPARE_VALUE_LOW_8814B 0x15C4 +#define REG_TIMER_COMPARE_VALUE_HIGH_8814B 0x15C8 +#define REG_SCHEDULER_COUNTER_8814B 0x15D0 #define REG_WMAC_CR_8814B 0x0600 #define REG_WMAC_FWPKT_CR_8814B 0x0601 #define REG_FW_STS_FILTER_8814B 0x0602 -#define REG_BWOPMODE_8814B 0x0603 #define REG_TCR_8814B 0x0604 #define REG_RCR_8814B 0x0608 #define REG_RX_PKT_LIMIT_8814B 0x060C #define REG_RX_DLK_TIME_8814B 0x060D #define REG_RX_DRVINFO_SZ_8814B 0x060F #define REG_MACID_8814B 0x0610 +#define REG_MACID_H_8814B 0x0614 #define REG_BSSID_8814B 0x0618 +#define REG_BSSID_H_8814B 0x061C #define REG_MAR_8814B 0x0620 -#define REG_MBIDCAMCFG_1_8814B 0x0628 -#define REG_MBIDCAMCFG_2_8814B 0x062C +#define REG_MAR_H_8814B 0x0624 +#define REG_WMAC_DEBUG_SEL_8814B 0x062C #define REG_WMAC_TCR_TSFT_OFS_8814B 0x0630 #define REG_UDF_THSD_8814B 0x0632 #define REG_ZLD_NUM_8814B 0x0633 @@ -547,18 +826,20 @@ #define REG_CTS2TO_8814B 0x0641 #define REG_EIFS_8814B 0x0642 #define REG_RPFM_MAP0_8814B 0x0644 -#define REG_RPFM_MAP1_8814B 0x0646 +#define REG_RPFM_MAP1_V1_8814B 0x0646 #define REG_RPFM_CAM_CMD_8814B 0x0648 #define REG_RPFM_CAM_RWD_8814B 0x064C #define REG_NAV_CTRL_8814B 0x0650 #define REG_BACAMCMD_8814B 0x0654 #define REG_BACAMCONTENT_8814B 0x0658 +#define REG_BACAMCONTENT_H_8814B 0x065C #define REG_LBDLY_8814B 0x0660 #define REG_WMAC_BACAM_RPMEN_8814B 0x0661 #define REG_TX_RX_8814B 0x0662 #define REG_WMAC_BITMAP_CTL_8814B 0x0663 #define REG_RXERR_RPT_8814B 0x0664 #define REG_WMAC_TRXPTCL_CTL_8814B 0x0668 +#define REG_WMAC_TRXPTCL_CTL_H_8814B 0x066C #define REG_CAMCMD_8814B 0x0670 #define REG_CAMWRITE_8814B 0x0674 #define REG_CAMREAD_8814B 0x0678 @@ -583,7 +864,7 @@ #define REG_WKFMCAM_RWD_8814B 0x069C #define REG_RXFLTMAP0_8814B 0x06A0 #define REG_RXFLTMAP1_8814B 0x06A2 -#define REG_RXFLTMAP_8814B 0x06A4 +#define REG_RXFLTMAP2_8814B 0x06A4 #define REG_BCN_PSR_RPT_8814B 0x06A8 #define REG_FLC_RPC_8814B 0x06AC #define REG_FLC_RPCT_8814B 0x06AD @@ -594,34 +875,57 @@ #define REG_ERROR_MON_8814B 0x06B8 #define REG_SEARCH_MACID_8814B 0x06BC #define REG_BT_COEX_TABLE_8814B 0x06C0 +#define REG_BT_COEX_TABLE2_8814B 0x06C4 +#define REG_BT_COEX_BREAK_TABLE_8814B 0x06C8 +#define REG_BT_COEX_TABLE_H_8814B 0x06CC #define REG_RXCMD_0_8814B 0x06D0 #define REG_RXCMD_1_8814B 0x06D4 #define REG_WMAC_RESP_TXINFO_8814B 0x06D8 #define REG_BBPSF_CTRL_8814B 0x06DC #define REG_P2P_RX_BCN_NOA_8814B 0x06E0 #define REG_ASSOCIATED_BFMER0_INFO_8814B 0x06E4 +#define REG_ASSOCIATED_BFMER0_INFO_H_8814B 0x06E8 #define REG_ASSOCIATED_BFMER1_INFO_8814B 0x06EC +#define REG_ASSOCIATED_BFMER1_INFO_H_8814B 0x06F0 #define REG_TX_CSI_RPT_PARAM_BW20_8814B 0x06F4 #define REG_TX_CSI_RPT_PARAM_BW40_8814B 0x06F8 -#define REG_TX_CSI_RPT_PARAM_BW80_8814B 0x06FC #define REG_BCN_PSR_RPT2_8814B 0x1600 #define REG_BCN_PSR_RPT3_8814B 0x1604 #define REG_BCN_PSR_RPT4_8814B 0x1608 #define REG_A1_ADDR_MASK_8814B 0x160C +#define REG_RXPSF_CTRL_8814B 0x1610 +#define REG_RXPSF_TYPE_CTRL_8814B 0x1614 +#define REG_CAM_ACCESS_CTRL_8814B 0x1618 +#define REG_CUT_AMSDU_CTRL_8814B 0x161C #define REG_MACID2_8814B 0x1620 +#define REG_MACID2_H_8814B 0x1624 #define REG_BSSID2_8814B 0x1628 +#define REG_BSSID2_H_8814B 0x162C #define REG_MACID3_8814B 0x1630 +#define REG_MACID3_H_8814B 0x1634 #define REG_BSSID3_8814B 0x1638 +#define REG_BSSID3_H_8814B 0x163C #define REG_MACID4_8814B 0x1640 +#define REG_MACID4_H_8814B 0x1644 #define REG_BSSID4_8814B 0x1648 +#define REG_BSSID4_H_8814B 0x164C #define REG_NOA_REPORT_8814B 0x1650 +#define REG_NOA_REPORT_1_8814B 0x1654 +#define REG_NOA_REPORT_2_8814B 0x1658 +#define REG_NOA_REPORT_3_8814B 0x165C #define REG_PWRBIT_SETTING_8814B 0x1660 -#define REG_WMAC_MU_BF_OPTION_8814B 0x167C +#define REG_GENERAL_OPTION_8814B 0x1664 +#define REG_FWPHYFF_RCR_8814B 0x1668 +#define REG_ADDRCAM_WRITE_CONTENT_8814B 0x166C +#define REG_ADDRCAM_READ_CONTENT_8814B 0x1670 +#define REG_ADDRCAM_CFG_8814B 0x1674 +#define REG_CSI_RRSR_8814B 0x1678 +#define REG_MU_BF_OPTION_8814B 0x167C #define REG_WMAC_PAUSE_BB_CLR_TH_8814B 0x167D -#define REG_WMAC_MU_ARB_8814B 0x167E +#define REG_WMAC_MULBK_BUF_8814B 0x167E #define REG_WMAC_MU_OPTION_8814B 0x167F #define REG_WMAC_MU_BF_CTL_8814B 0x1680 -#define REG_WMAC_MU_BIT_BFRPT_PARA_8814B 0x1682 +#define REG_WMAC_MU_BFRPT_PARA_8814B 0x1682 #define REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B 0x1684 #define REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B 0x1686 #define REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B 0x1688 @@ -630,12 +934,17 @@ #define REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B 0x168E #define REG_WMAC_BB_STOP_RX_COUNTER_8814B 0x1690 #define REG_WMAC_PLCP_MONITOR_8814B 0x1694 -#define REG_WMAC_PLCP_MONITOR_MUTX_8814B 0x1698 +#define REG_WMAC_DEBUG_PORT_8814B 0x1698 #define REG_TRANSMIT_ADDRSS_0_8814B 0x16A0 +#define REG_TRANSMIT_ADDRSS_0_H_8814B 0x16A4 #define REG_TRANSMIT_ADDRSS_1_8814B 0x16A8 +#define REG_TRANSMIT_ADDRSS_1_H_8814B 0x16AC #define REG_TRANSMIT_ADDRSS_2_8814B 0x16B0 +#define REG_TRANSMIT_ADDRSS_2_H_8814B 0x16B4 #define REG_TRANSMIT_ADDRSS_3_8814B 0x16B8 +#define REG_TRANSMIT_ADDRSS_3_H_8814B 0x16BC #define REG_TRANSMIT_ADDRSS_4_8814B 0x16C0 +#define REG_TRANSMIT_ADDRSS_4_H_8814B 0x16C4 #define REG_MACID1_8814B 0x0700 #define REG_MACID1_1_8814B 0x0704 #define REG_BSSID1_8814B 0x0708 @@ -677,10 +986,10 @@ #define REG_LTR_CTRL2_TIMER_THRESHOLD_8814B 0x07A4 #define REG_LTR_IDLE_LATENCY_V1_8814B 0x07A8 #define REG_LTR_ACTIVE_LATENCY_V1_8814B 0x07AC -#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8814B 0x07B0 -#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8814B 0x07B4 -#define REG_WMAC_PKTCNT_RWD_8814B 0x07B8 -#define REG_WMAC_PKTCNT_CTRL_8814B 0x07BC +#define REG_SMART_ANT_CONDITION_8814B 0x07B0 +#define REG_SMART_ANT_CTRL_8814B 0x07B4 +#define REG_CONTROL_FRAME_REPORT_8814B 0x07B8 +#define REG_CONTROL_FRAME_CNT_CTRL_8814B 0x07BC #define REG_IQ_DUMP_8814B 0x07C0 #define REG_IQ_DUMP_1_8814B 0x07C4 #define REG_IQ_DUMP_2_8814B 0x07C8 @@ -701,6 +1010,20 @@ #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8814B 0x1700 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B 0x1704 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B 0x1708 +#define REG_PCIE_CFG_FORCE_LINK_L_8814B 0x0709 +#define REG_PCIE_CFG_FORCE_LINK_H_8814B 0x070A +#define REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0x070C +#define REG_PCIE_CFG_CX_NFTS_8814B 0x070D +#define REG_PCIE_CFG_DEFAULT_ENTR_LATENCY_8814B 0x070F +#define REG_PCIE_CFG_L1_MISC_SEL_8814B 0x0711 +#define REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF_8814B 0x0718 +#define REG_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B 0x0719 +#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY_8814B 0x071A +#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG_8814B 0x071B +#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0x071C +#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0x071D +#define REG_PCIE_CFG_L1_UNIT_SEL_8814B 0x0724 +#define REG_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0x0725 #define REG_SDIO_TX_CTRL_8814B 0x10250000 #define REG_SDIO_HIMR_8814B 0x10250014 #define REG_SDIO_HISR_8814B 0x10250018 @@ -724,10 +1047,9 @@ #define REG_SDIO_RESPONSE_TIMER_8814B 0x10250088 #define REG_SDIO_CMD_CRC_8814B 0x1025008A #define REG_SDIO_HSISR_8814B 0x10250090 -#define REG_SDIO_HSIMR_8814B 0x10250091 #define REG_SDIO_ERR_RPT_8814B 0x102500C0 -#define REG_SDIO_CMD_ERRCNT_8814B 0x102500C1 -#define REG_SDIO_DATA_ERRCNT_8814B 0x102500C2 +#define REG_SDIO_CMD_ERRCNT_8814B 0x102500C2 +#define REG_SDIO_DATA_ERRCNT_8814B 0x102500C3 #define REG_SDIO_CMD_ERR_CONTENT_8814B 0x102500C4 #define REG_SDIO_CRC_ERR_IDX_8814B 0x102500C9 #define REG_SDIO_DATA_CRC_8814B 0x102500CA diff --git a/hal/halmac/halmac_reg_8821c.h b/hal/halmac/halmac_reg_8821c.h index 4f22ee2..dd93baf 100644 --- a/hal/halmac/halmac_reg_8821c.h +++ b/hal/halmac/halmac_reg_8821c.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_REG_8821C_H #define __INC_HALMAC_REG_8821C_H @@ -69,7 +84,6 @@ #define REG_SYS_STATUS2_8821C 0x00F8 #define REG_SYS_CFG2_8821C 0x00FC #define REG_SYS_CFG3_8821C 0x1000 -#define REG_SYS_CFG4_8821C 0x1034 #define REG_SYS_CFG5_8821C 0x1070 #define REG_CPU_DMEM_CON_8821C 0x1080 #define REG_BOOT_REASON_8821C 0x1088 @@ -79,19 +93,13 @@ #define REG_HIMR3_8821C 0x10B8 #define REG_HISR3_8821C 0x10BC #define REG_SW_MDIO_8821C 0x10C0 -#define REG_SW_FLUSH_8821C 0x10C4 #define REG_H2C_PKT_READADDR_8821C 0x10D0 #define REG_H2C_PKT_WRITEADDR_8821C 0x10D4 #define REG_MEM_PWR_CRTL_8821C 0x10D8 -#define REG_FW_DBG0_8821C 0x10E0 -#define REG_FW_DBG1_8821C 0x10E4 -#define REG_FW_DBG2_8821C 0x10E8 -#define REG_FW_DBG3_8821C 0x10EC -#define REG_FW_DBG4_8821C 0x10F0 -#define REG_FW_DBG5_8821C 0x10F4 #define REG_FW_DBG6_8821C 0x10F8 #define REG_FW_DBG7_8821C 0x10FC #define REG_CR_8821C 0x0100 +#define REG_PG_SIZE_8821C 0x0104 #define REG_PKT_BUFF_ACCESS_CTRL_8821C 0x0106 #define REG_TSF_CLK_STATE_8821C 0x0108 #define REG_TXDMA_PQ_MAP_8821C 0x010C @@ -117,10 +125,10 @@ #define REG_TCUNIT_BASE_8821C 0x0164 #define REG_TC5_CTRL_8821C 0x0168 #define REG_TC6_CTRL_8821C 0x016C -#define REG_MBIST_FAIL_8821C 0x0170 +#define REG_MBIST_DRF_FAIL_8821C 0x0170 #define REG_MBIST_START_PAUSE_8821C 0x0174 #define REG_MBIST_DONE_8821C 0x0178 -#define REG_MBIST_FAIL_NRML_8821C 0x017C +#define REG_MBIST_READ_BIST_RPT_8821C 0x017C #define REG_AES_DECRPT_DATA_8821C 0x0180 #define REG_AES_DECRPT_CFG_8821C 0x0184 #define REG_TMETER_8821C 0x0190 @@ -140,8 +148,6 @@ #define REG_HMEBOX1_8821C 0x01D4 #define REG_HMEBOX2_8821C 0x01D8 #define REG_HMEBOX3_8821C 0x01DC -#define REG_LLT_INIT_8821C 0x01E0 -#define REG_LLT_INIT_ADDR_8821C 0x01E4 #define REG_BB_ACCESS_CTRL_8821C 0x01E8 #define REG_BB_ACCESS_DATA_8821C 0x01EC #define REG_HMEBOX_E0_8821C 0x01F0 @@ -167,6 +173,22 @@ #define REG_POWSEQ_8821C 0x1150 #define REG_TC7_CTRL_V1_8821C 0x1158 #define REG_TC8_CTRL_V1_8821C 0x115C +#define REG_RX_BCN_TBTT_ITVL0_8821C 0x1160 +#define REG_RX_BCN_TBTT_ITVL1_8821C 0x1164 +#define REG_IO_WRAP_ERR_FLAG_8821C 0x1170 +#define REG_SPEED_SENSOR_8821C 0x1180 +#define REG_SPEED_SENSOR1_8821C 0x1184 +#define REG_SPEED_SENSOR2_8821C 0x1188 +#define REG_SPEED_SENSOR3_8821C 0x118C +#define REG_SPEED_SENSOR4_8821C 0x1190 +#define REG_SPEED_SENSOR5_8821C 0x1194 +#define REG_COUNTER_CTRL_8821C 0x11C4 +#define REG_COUNTER_THRESHOLD_8821C 0x11C8 +#define REG_COUNTER_SET_8821C 0x11CC +#define REG_COUNTER_OVERFLOW_8821C 0x11D0 +#define REG_TXDMA_LEN_THRESHOLD_8821C 0x11D4 +#define REG_RXDMA_LEN_THRESHOLD_8821C 0x11D8 +#define REG_PCIE_EXEC_TIME_THRESHOLD_8821C 0x11DC #define REG_FT2IMR_8821C 0x11E0 #define REG_FT2ISR_8821C 0x11E4 #define REG_MSG2_8821C 0x11F0 @@ -312,10 +334,14 @@ #define REG_RETRY_LIMIT_8821C 0x042A #define REG_TXBF_CTRL_8821C 0x042C #define REG_DARFRC_8821C 0x0430 +#define REG_DARFRCH_8821C 0x0434 #define REG_RARFRC_8821C 0x0438 +#define REG_RARFRCH_8821C 0x043C #define REG_RRSR_8821C 0x0440 #define REG_ARFR0_8821C 0x0444 +#define REG_ARFRH0_8821C 0x0448 #define REG_ARFR1_V1_8821C 0x044C +#define REG_ARFRH1_V1_8821C 0x0450 #define REG_CCK_CHECK_8821C 0x0454 #define REG_AMPDU_MAX_TIME_V1_8821C 0x0455 #define REG_BCNQ1_BDNY_V1_8821C 0x0456 @@ -340,9 +366,13 @@ #define REG_MACID_SLEEP3_8821C 0x0484 #define REG_MACID_SLEEP1_8821C 0x0488 #define REG_ARFR2_V1_8821C 0x048C +#define REG_ARFRH2_V1_8821C 0x0490 #define REG_ARFR3_V1_8821C 0x0494 +#define REG_ARFRH3_V1_8821C 0x0498 #define REG_ARFR4_8821C 0x049C +#define REG_ARFRH4_8821C 0x04A0 #define REG_ARFR5_8821C 0x04A4 +#define REG_ARFRH5_8821C 0x04A8 #define REG_TXRPT_START_OFFSET_8821C 0x04AC #define REG_POWER_STAGE1_8821C 0x04B4 #define REG_POWER_STAGE2_8821C 0x04B8 @@ -365,6 +395,7 @@ #define REG_PTCL_ERR_STATUS_8821C 0x04E2 #define REG_NULL_PKT_STATUS_EXTEND_8821C 0x04E3 #define REG_VIDEO_ENHANCEMENT_FUN_8821C 0x04E4 +#define REG_PRECNT_CTRL_8821C 0x04E5 #define REG_BT_POLLUTE_PKT_CNT_8821C 0x04E8 #define REG_PTCL_DBG_8821C 0x04EC #define REG_CPUMGQ_TIMER_CTRL2_8821C 0x04F4 @@ -396,13 +427,24 @@ #define REG_R_MACID_RELEASE_SUCCESS_1_8821C 0x1464 #define REG_R_MACID_RELEASE_SUCCESS_2_8821C 0x1468 #define REG_R_MACID_RELEASE_SUCCESS_3_8821C 0x146C -#define REG_MGG_FIFO_CRTL_8821C 0x1470 -#define REG_MGG_FIFO_INT_8821C 0x1474 -#define REG_MGG_FIFO_LIFETIME_8821C 0x1478 +#define REG_MGQ_FIFO_WRITE_POINTER_8821C 0x1470 +#define REG_MGQ_FIFO_READ_POINTER_8821C 0x1472 +#define REG_MGQ_FIFO_ENABLE_8821C 0x1472 +#define REG_MGQ_FIFO_RELEASE_INT_MASK_8821C 0x1474 +#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C 0x1476 +#define REG_MGQ_FIFO_VALID_MAP_8821C 0x1478 +#define REG_MGQ_FIFO_LIFETIME_8821C 0x147A #define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x147C +#define REG_SHCUT_SETTING_8821C 0x1480 +#define REG_SHCUT_LLC_ETH_TYPE0_8821C 0x1484 +#define REG_SHCUT_LLC_ETH_TYPE1_8821C 0x1488 +#define REG_SHCUT_LLC_OUI0_8821C 0x148C +#define REG_SHCUT_LLC_OUI1_8821C 0x1490 +#define REG_SHCUT_LLC_OUI2_8821C 0x1494 #define REG_MU_TX_CTL_8821C 0x14C0 #define REG_MU_STA_GID_VLD_8821C 0x14C4 #define REG_MU_STA_USER_POS_INFO_8821C 0x14C8 +#define REG_MU_STA_USER_POS_INFO_H_8821C 0x14CC #define REG_MU_TRX_DBG_CNT_8821C 0x14D0 #define REG_EDCA_VO_PARAM_8821C 0x0500 #define REG_EDCA_VI_PARAM_8821C 0x0504 @@ -415,6 +457,8 @@ #define REG_TSFTR_SYN_OFFSET_8821C 0x0518 #define REG_AGGR_BREAK_TIME_8821C 0x051A #define REG_SLOT_8821C 0x051B +#define REG_NOA_ON_ERLY_TIME_8821C 0x051C +#define REG_NOA_OFF_ERLY_TIME_8821C 0x051D #define REG_TX_PTCL_CTRL_8821C 0x0520 #define REG_TXPAUSE_8821C 0x0522 #define REG_DIS_TXREQ_CLR_8821C 0x0523 @@ -424,6 +468,7 @@ #define REG_PKT_LIFETIME_CTRL_8821C 0x0528 #define REG_P2PPS_SPEC_STATE_8821C 0x052B #define REG_BAR_TX_CTRL_8821C 0x0530 +#define REG_P2PON_DIS_TXTIME_8821C 0x0531 #define REG_TBTT_PROHIBIT_8821C 0x0540 #define REG_P2PPS_STATE_8821C 0x0543 #define REG_RD_NAV_NXT_8821C 0x0544 @@ -518,18 +563,21 @@ #define REG_PS_TIMER_A_EARLY_8821C 0x1515 #define REG_PS_TIMER_B_EARLY_8821C 0x1516 #define REG_PS_TIMER_C_EARLY_8821C 0x1517 +#define REG_CPUMGQ_PARAMETER_8821C 0x1518 #define REG_WMAC_CR_8821C 0x0600 #define REG_WMAC_FWPKT_CR_8821C 0x0601 #define REG_FW_STS_FILTER_8821C 0x0602 -#define REG_BWOPMODE_8821C 0x0603 #define REG_TCR_8821C 0x0604 #define REG_RCR_8821C 0x0608 #define REG_RX_PKT_LIMIT_8821C 0x060C #define REG_RX_DLK_TIME_8821C 0x060D #define REG_RX_DRVINFO_SZ_8821C 0x060F #define REG_MACID_8821C 0x0610 +#define REG_MACID_H_8821C 0x0614 #define REG_BSSID_8821C 0x0618 +#define REG_BSSID_H_8821C 0x061C #define REG_MAR_8821C 0x0620 +#define REG_MAR_H_8821C 0x0624 #define REG_MBIDCAMCFG_1_8821C 0x0628 #define REG_MBIDCAMCFG_2_8821C 0x062C #define REG_WMAC_TCR_TSFT_OFS_8821C 0x0630 @@ -547,18 +595,20 @@ #define REG_CTS2TO_8821C 0x0641 #define REG_EIFS_8821C 0x0642 #define REG_RPFM_MAP0_8821C 0x0644 -#define REG_RPFM_MAP1_8821C 0x0646 +#define REG_RPFM_MAP1_V1_8821C 0x0646 #define REG_RPFM_CAM_CMD_8821C 0x0648 #define REG_RPFM_CAM_RWD_8821C 0x064C #define REG_NAV_CTRL_8821C 0x0650 #define REG_BACAMCMD_8821C 0x0654 #define REG_BACAMCONTENT_8821C 0x0658 +#define REG_BACAMCONTENT_H_8821C 0x065C #define REG_LBDLY_8821C 0x0660 #define REG_WMAC_BACAM_RPMEN_8821C 0x0661 #define REG_TX_RX_8821C 0x0662 #define REG_WMAC_BITMAP_CTL_8821C 0x0663 #define REG_RXERR_RPT_8821C 0x0664 #define REG_WMAC_TRXPTCL_CTL_8821C 0x0668 +#define REG_WMAC_TRXPTCL_CTL_H_8821C 0x066C #define REG_CAMCMD_8821C 0x0670 #define REG_CAMWRITE_8821C 0x0674 #define REG_CAMREAD_8821C 0x0678 @@ -583,7 +633,7 @@ #define REG_WKFMCAM_RWD_8821C 0x069C #define REG_RXFLTMAP0_8821C 0x06A0 #define REG_RXFLTMAP1_8821C 0x06A2 -#define REG_RXFLTMAP_8821C 0x06A4 +#define REG_RXFLTMAP2_8821C 0x06A4 #define REG_BCN_PSR_RPT_8821C 0x06A8 #define REG_FLC_RPC_8821C 0x06AC #define REG_FLC_RPCT_8821C 0x06AD @@ -594,34 +644,47 @@ #define REG_ERROR_MON_8821C 0x06B8 #define REG_SEARCH_MACID_8821C 0x06BC #define REG_BT_COEX_TABLE_8821C 0x06C0 +#define REG_BT_COEX_TABLE2_8821C 0x06C4 +#define REG_BT_COEX_BREAK_TABLE_8821C 0x06C8 +#define REG_BT_COEX_TABLE_H_8821C 0x06CC #define REG_RXCMD_0_8821C 0x06D0 #define REG_RXCMD_1_8821C 0x06D4 #define REG_WMAC_RESP_TXINFO_8821C 0x06D8 #define REG_BBPSF_CTRL_8821C 0x06DC #define REG_P2P_RX_BCN_NOA_8821C 0x06E0 #define REG_ASSOCIATED_BFMER0_INFO_8821C 0x06E4 +#define REG_ASSOCIATED_BFMER0_INFO_H_8821C 0x06E8 #define REG_ASSOCIATED_BFMER1_INFO_8821C 0x06EC +#define REG_ASSOCIATED_BFMER1_INFO_H_8821C 0x06F0 #define REG_TX_CSI_RPT_PARAM_BW20_8821C 0x06F4 #define REG_TX_CSI_RPT_PARAM_BW40_8821C 0x06F8 -#define REG_TX_CSI_RPT_PARAM_BW80_8821C 0x06FC #define REG_BCN_PSR_RPT2_8821C 0x1600 #define REG_BCN_PSR_RPT3_8821C 0x1604 #define REG_BCN_PSR_RPT4_8821C 0x1608 #define REG_A1_ADDR_MASK_8821C 0x160C #define REG_MACID2_8821C 0x1620 +#define REG_MACID2_H_8821C 0x1624 #define REG_BSSID2_8821C 0x1628 +#define REG_BSSID2_H_8821C 0x162C #define REG_MACID3_8821C 0x1630 +#define REG_MACID3_H_8821C 0x1634 #define REG_BSSID3_8821C 0x1638 +#define REG_BSSID3_H_8821C 0x163C #define REG_MACID4_8821C 0x1640 +#define REG_MACID4_H_8821C 0x1644 #define REG_BSSID4_8821C 0x1648 +#define REG_BSSID4_H_8821C 0x164C #define REG_NOA_REPORT_8821C 0x1650 +#define REG_NOA_REPORT_1_8821C 0x1654 +#define REG_NOA_REPORT_2_8821C 0x1658 +#define REG_NOA_REPORT_3_8821C 0x165C #define REG_PWRBIT_SETTING_8821C 0x1660 -#define REG_WMAC_MU_BF_OPTION_8821C 0x167C +#define REG_MU_BF_OPTION_8821C 0x167C #define REG_WMAC_PAUSE_BB_CLR_TH_8821C 0x167D #define REG_WMAC_MU_ARB_8821C 0x167E #define REG_WMAC_MU_OPTION_8821C 0x167F #define REG_WMAC_MU_BF_CTL_8821C 0x1680 -#define REG_WMAC_MU_BIT_BFRPT_PARA_8821C 0x1682 +#define REG_WMAC_MU_BFRPT_PARA_8821C 0x1682 #define REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C 0x1684 #define REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C 0x1686 #define REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C 0x1688 @@ -632,10 +695,15 @@ #define REG_WMAC_PLCP_MONITOR_8821C 0x1694 #define REG_WMAC_PLCP_MONITOR_MUTX_8821C 0x1698 #define REG_TRANSMIT_ADDRSS_0_8821C 0x16A0 +#define REG_TRANSMIT_ADDRSS_0_H_8821C 0x16A4 #define REG_TRANSMIT_ADDRSS_1_8821C 0x16A8 +#define REG_TRANSMIT_ADDRSS_1_H_8821C 0x16AC #define REG_TRANSMIT_ADDRSS_2_8821C 0x16B0 +#define REG_TRANSMIT_ADDRSS_2_H_8821C 0x16B4 #define REG_TRANSMIT_ADDRSS_3_8821C 0x16B8 +#define REG_TRANSMIT_ADDRSS_3_H_8821C 0x16BC #define REG_TRANSMIT_ADDRSS_4_8821C 0x16C0 +#define REG_TRANSMIT_ADDRSS_4_H_8821C 0x16C4 #define REG_MACID1_8821C 0x0700 #define REG_MACID1_1_8821C 0x0704 #define REG_BSSID1_8821C 0x0708 @@ -724,10 +792,9 @@ #define REG_SDIO_RESPONSE_TIMER_8821C 0x10250088 #define REG_SDIO_CMD_CRC_8821C 0x1025008A #define REG_SDIO_HSISR_8821C 0x10250090 -#define REG_SDIO_HSIMR_8821C 0x10250091 #define REG_SDIO_ERR_RPT_8821C 0x102500C0 -#define REG_SDIO_CMD_ERRCNT_8821C 0x102500C1 -#define REG_SDIO_DATA_ERRCNT_8821C 0x102500C2 +#define REG_SDIO_CMD_ERRCNT_8821C 0x102500C2 +#define REG_SDIO_DATA_ERRCNT_8821C 0x102500C3 #define REG_SDIO_CMD_ERR_CONTENT_8821C 0x102500C4 #define REG_SDIO_CRC_ERR_IDX_8821C 0x102500C9 #define REG_SDIO_DATA_CRC_8821C 0x102500CA diff --git a/hal/halmac/halmac_reg_8822b.h b/hal/halmac/halmac_reg_8822b.h index e956627..e06f67e 100644 --- a/hal/halmac/halmac_reg_8822b.h +++ b/hal/halmac/halmac_reg_8822b.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __INC_HALMAC_REG_8822B_H #define __INC_HALMAC_REG_8822B_H @@ -92,7 +107,6 @@ #define REG_FW_DBG6_8822B 0x10F8 #define REG_FW_DBG7_8822B 0x10FC #define REG_CR_8822B 0x0100 -#define REG_PKT_BUFF_ACCESS_CTRL_8822B 0x0106 #define REG_TSF_CLK_STATE_8822B 0x0108 #define REG_TXDMA_PQ_MAP_8822B 0x010C #define REG_TRXFF_BNDY_8822B 0x0114 @@ -127,6 +141,9 @@ #define REG_OSC_32K_CTRL_8822B 0x0194 #define REG_32K_CAL_REG1_8822B 0x0198 #define REG_C2HEVT_8822B 0x01A0 +#define REG_C2HEVT_1_8822B 0x01A4 +#define REG_C2HEVT_2_8822B 0x01A8 +#define REG_C2HEVT_3_8822B 0x01AC #define REG_SW_DEFINED_PAGE1_8822B 0x01B8 #define REG_MCUTST_I_8822B 0x01C0 #define REG_MCUTST_II_8822B 0x01C4 @@ -398,10 +415,20 @@ #define REG_MGG_FIFO_INT_8822B 0x1474 #define REG_MGG_FIFO_LIFETIME_8822B 0x1478 #define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x147C -#define REG_MACID_SHCUT_OFFSET_8822B 0x1480 +#define REG_SHCUT_SETTING_8822B 0x1480 +#define REG_SHCUT_LLC_ETH_TYPE0_8822B 0x1484 +#define REG_SHCUT_LLC_ETH_TYPE1_8822B 0x1488 +#define REG_SHCUT_LLC_OUI0_8822B 0x148C +#define REG_SHCUT_LLC_OUI1_8822B 0x1490 +#define REG_SHCUT_LLC_OUI2_8822B 0x1494 +#define REG_SHCUT_LLC_OUI3_8822B 0x1498 +#define REG_MU_TX_CTL_8822B 0x14C0 #define REG_MU_TX_CTL_8822B 0x14C0 #define REG_MU_STA_GID_VLD_8822B 0x14C4 +#define REG_MU_STA_GID_VLD_8822B 0x14C4 #define REG_MU_STA_USER_POS_INFO_8822B 0x14C8 +#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8 +#define REG_MU_TRX_DBG_CNT_8822B 0x14D0 #define REG_MU_TRX_DBG_CNT_8822B 0x14D0 #define REG_EDCA_VO_PARAM_8822B 0x0500 #define REG_EDCA_VI_PARAM_8822B 0x0504 @@ -422,7 +449,9 @@ #define REG_P2PPS_CTRL_8822B 0x0527 #define REG_PKT_LIFETIME_CTRL_8822B 0x0528 #define REG_P2PPS_SPEC_STATE_8822B 0x052B +#define REG_TXOP_LIMIT_CTRL_8822B 0x052C #define REG_BAR_TX_CTRL_8822B 0x0530 +#define REG_P2PON_DIS_TXTIME_8822B 0x0531 #define REG_QUEUE_INCOL_THR_8822B 0x0538 #define REG_QUEUE_INCOL_EN_8822B 0x053C #define REG_TBTT_PROHIBIT_8822B 0x0540 @@ -514,6 +543,7 @@ #define REG_PS_TIMER_A_EARLY_8822B 0x1515 #define REG_PS_TIMER_B_EARLY_8822B 0x1516 #define REG_PS_TIMER_C_EARLY_8822B 0x1517 +#define REG_CPUMGQ_PARAMETER_8822B 0x1518 #define REG_WMAC_CR_8822B 0x0600 #define REG_WMAC_FWPKT_CR_8822B 0x0601 #define REG_BWOPMODE_8822B 0x0603 @@ -573,7 +603,7 @@ #define REG_WKFMCAM_RWD_8822B 0x069C #define REG_RXFLTMAP0_8822B 0x06A0 #define REG_RXFLTMAP1_8822B 0x06A2 -#define REG_RXFLTMAP_8822B 0x06A4 +#define REG_RXFLTMAP2_8822B 0x06A4 #define REG_BCN_PSR_RPT_8822B 0x06A8 #define REG_FLC_RPC_8822B 0x06AC #define REG_FLC_RPCT_8822B 0x06AD @@ -692,10 +722,9 @@ #define REG_SDIO_RESPONSE_TIMER_8822B 0x10250088 #define REG_SDIO_CMD_CRC_8822B 0x1025008A #define REG_SDIO_HSISR_8822B 0x10250090 -#define REG_SDIO_HSIMR_8822B 0x10250091 #define REG_SDIO_ERR_RPT_8822B 0x102500C0 -#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C1 -#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C2 +#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C2 +#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C3 #define REG_SDIO_CMD_ERR_CONTENT_8822B 0x102500C4 #define REG_SDIO_CRC_ERR_IDX_8822B 0x102500C9 #define REG_SDIO_DATA_CRC_8822B 0x102500CA diff --git a/hal/halmac/halmac_reg_8822c.h b/hal/halmac/halmac_reg_8822c.h new file mode 100644 index 0000000..bfe112b --- /dev/null +++ b/hal/halmac/halmac_reg_8822c.h @@ -0,0 +1,877 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef __INC_HALMAC_REG_8822C_H +#define __INC_HALMAC_REG_8822C_H + +#define REG_SYS_ISO_CTRL_8822C 0x0000 +#define REG_SYS_FUNC_EN_8822C 0x0002 +#define REG_SYS_PW_CTRL_8822C 0x0004 +#define REG_SYS_CLK_CTRL_8822C 0x0008 +#define REG_SYS_EEPROM_CTRL_8822C 0x000A +#define REG_EE_VPD_8822C 0x000C +#define REG_SYS_SWR_CTRL1_8822C 0x0010 +#define REG_SYS_SWR_CTRL2_8822C 0x0014 +#define REG_SYS_SWR_CTRL3_8822C 0x0018 +#define REG_RSV_CTRL_8822C 0x001C +#define REG_RF_CTRL_8822C 0x001F +#define REG_AFE_LDO_CTRL_8822C 0x0020 +#define REG_AFE_CTRL1_8822C 0x0024 +#define REG_ANAPARSW_POW_MAC_8822C 0x0028 +#define REG_ANAPARLDO_POW_MAC_8822C 0x0029 +#define REG_ANAPAR_POW_MAC_8822C 0x002A +#define REG_ANAPAR_POW_XTAL_8822C 0x002B +#define REG_ANAPARLDO_MAC_8822C 0x002C +#define REG_EFUSE_CTRL_8822C 0x0030 +#define REG_LDO_EFUSE_CTRL_8822C 0x0034 +#define REG_PWR_OPTION_CTRL_8822C 0x0038 +#define REG_CAL_TIMER_8822C 0x003C +#define REG_ACLK_MON_8822C 0x003E +#define REG_GPIO_MUXCFG_2_8822C 0x003F +#define REG_GPIO_MUXCFG_8822C 0x0040 +#define REG_GPIO_PIN_CTRL_8822C 0x0044 +#define REG_GPIO_INTM_8822C 0x0048 +#define REG_LED_CFG_8822C 0x004C +#define REG_FSIMR_8822C 0x0050 +#define REG_FSISR_8822C 0x0054 +#define REG_HSIMR_8822C 0x0058 +#define REG_HSISR_8822C 0x005C +#define REG_GPIO_EXT_CTRL_8822C 0x0060 +#define REG_PAD_CTRL1_8822C 0x0064 +#define REG_WL_BT_PWR_CTRL_8822C 0x0068 +#define REG_SDM_DEBUG_8822C 0x006C +#define REG_SYS_SDIO_CTRL_8822C 0x0070 +#define REG_HCI_OPT_CTRL_8822C 0x0074 +#define REG_HCI_BG_CTRL_8822C 0x0078 +#define REG_HCI_LDO_CTRL_8822C 0x007A +#define REG_LDO_SWR_CTRL_8822C 0x007C +#define REG_MCUFW_CTRL_8822C 0x0080 +#define REG_MCU_TST_CFG_8822C 0x0084 +#define REG_HMEBOX_E0_E1_8822C 0x0088 +#define REG_HMEBOX_E2_E3_8822C 0x008C +#define REG_WLLPS_CTRL_8822C 0x0090 +#define REG_GPIO_DEBOUNCE_CTRL_8822C 0x0098 +#define REG_RPWM2_8822C 0x009C +#define REG_SYSON_FSM_MON_8822C 0x00A0 +#define REG_PMC_DBG_CTRL1_8822C 0x00A8 +#define REG_HIMR0_8822C 0x00B0 +#define REG_HISR0_8822C 0x00B4 +#define REG_HIMR1_8822C 0x00B8 +#define REG_HISR1_8822C 0x00BC +#define REG_DBG_PORT_SEL_8822C 0x00C0 +#define REG_PAD_CTRL2_8822C 0x00C4 +#define REG_PMC_DBG_CTRL2_8822C 0x00CC +#define REG_BIST_CTRL_8822C 0x00D0 +#define REG_BIST_RPT_8822C 0x00D4 +#define REG_MEM_CTRL_8822C 0x00D8 +#define REG_USB_SIE_INTF_8822C 0x00E0 +#define REG_PCIE_MIO_INTF_8822C 0x00E4 +#define REG_PCIE_MIO_INTD_8822C 0x00E8 +#define REG_WLRF1_8822C 0x00EC +#define REG_SYS_CFG1_8822C 0x00F0 +#define REG_SYS_STATUS1_8822C 0x00F4 +#define REG_SYS_STATUS2_8822C 0x00F8 +#define REG_SYS_CFG2_8822C 0x00FC +#define REG_SYS_CFG3_8822C 0x1000 +#define REG_ANAPARSW_MAC_0_8822C 0x1010 +#define REG_ANAPARSW_MAC_1_8822C 0x1014 +#define REG_ANAPAR_MAC_0_8822C 0x1018 +#define REG_ANAPAR_MAC_1_8822C 0x101C +#define REG_ANAPAR_MAC_2_8822C 0x1020 +#define REG_ANAPAR_XTAL_0_8822C 0x1040 +#define REG_ANAPAR_XTAL_1_8822C 0x1044 +#define REG_ANAPAR_XTAL_2_8822C 0x1048 +#define REG_ANAPAR_XTAL_3_8822C 0x104C +#define REG_ANAPAR_XTAL_AACK_0_8822C 0x1054 +#define REG_ANAPAR_XTAL_AACK_1_8822C 0x1058 +#define REG_ANAPAR_XTAL_MODE_DECODER_8822C 0x1064 +#define REG_SYS_CFG5_8822C 0x1070 +#define REG_CPU_DMEM_CON_8822C 0x1080 +#define REG_BOOT_REASON_8822C 0x1088 +#define REG_HIMR2_8822C 0x10B0 +#define REG_HISR2_8822C 0x10B4 +#define REG_HIMR3_8822C 0x10B8 +#define REG_HISR3_8822C 0x10BC +#define REG_SW_MDIO_8822C 0x10C0 +#define REG_H2C_PKT_READADDR_8822C 0x10D0 +#define REG_H2C_PKT_WRITEADDR_8822C 0x10D4 +#define REG_MEM_PWR_CRTL_8822C 0x10D8 +#define REG_FW_DBG6_8822C 0x10F8 +#define REG_FW_DBG7_8822C 0x10FC +#define REG_CR_8822C 0x0100 +#define REG_PG_SIZE_8822C 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL_8822C 0x0106 +#define REG_TSF_CLK_STATE_8822C 0x0108 +#define REG_TXDMA_PQ_MAP_8822C 0x010C +#define REG_TRXFF_BNDY_8822C 0x0114 +#define REG_PTA_I2C_MBOX_8822C 0x0118 +#define REG_RXFF_BNDY_8822C 0x011C +#define REG_FE1IMR_8822C 0x0120 +#define REG_FE1ISR_8822C 0x0124 +#define REG_CPWM_8822C 0x012C +#define REG_FWIMR_8822C 0x0130 +#define REG_FWISR_8822C 0x0134 +#define REG_FTIMR_8822C 0x0138 +#define REG_FTISR_8822C 0x013C +#define REG_PKTBUF_DBG_CTRL_8822C 0x0140 +#define REG_PKTBUF_DBG_DATA_L_8822C 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8822C 0x0148 +#define REG_CPWM2_8822C 0x014C +#define REG_TC0_CTRL_8822C 0x0150 +#define REG_TC1_CTRL_8822C 0x0154 +#define REG_TC2_CTRL_8822C 0x0158 +#define REG_TC3_CTRL_8822C 0x015C +#define REG_TC4_CTRL_8822C 0x0160 +#define REG_TCUNIT_BASE_8822C 0x0164 +#define REG_TC5_CTRL_8822C 0x0168 +#define REG_TC6_CTRL_8822C 0x016C +#define REG_MBIST_DRF_FAIL_8822C 0x0170 +#define REG_MBIST_START_PAUSE_8822C 0x0174 +#define REG_MBIST_DONE_8822C 0x0178 +#define REG_MBIST_READ_BIST_RPT_8822C 0x017C +#define REG_AES_DECRPT_DATA_8822C 0x0180 +#define REG_AES_DECRPT_CFG_8822C 0x0184 +#define REG_HIOE_CTRL_8822C 0x0188 +#define REG_HIOE_CFG_FILE_8822C 0x018C +#define REG_TMETER_8822C 0x0190 +#define REG_OSC_32K_CTRL_8822C 0x0194 +#define REG_32K_CAL_REG1_8822C 0x0198 +#define REG_C2HEVT_8822C 0x01A0 +#define REG_C2HEVT_1_8822C 0x01A4 +#define REG_C2HEVT_2_8822C 0x01A8 +#define REG_C2HEVT_3_8822C 0x01AC +#define REG_SW_DEFINED_PAGE1_8822C 0x01B8 +#define REG_SW_DEFINED_PAGE2_8822C 0x01BC +#define REG_MCUTST_I_8822C 0x01C0 +#define REG_MCUTST_II_8822C 0x01C4 +#define REG_FMETHR_8822C 0x01C8 +#define REG_HMETFR_8822C 0x01CC +#define REG_HMEBOX0_8822C 0x01D0 +#define REG_HMEBOX1_8822C 0x01D4 +#define REG_HMEBOX2_8822C 0x01D8 +#define REG_HMEBOX3_8822C 0x01DC +#define REG_BB_ACCESS_CTRL_8822C 0x01E8 +#define REG_BB_ACCESS_DATA_8822C 0x01EC +#define REG_HMEBOX_E0_8822C 0x01F0 +#define REG_HMEBOX_E1_8822C 0x01F4 +#define REG_HMEBOX_E2_8822C 0x01F8 +#define REG_HMEBOX_E3_8822C 0x01FC +#define REG_CR_EXT_8822C 0x1100 +#define REG_FWFF_8822C 0x1114 +#define REG_RXFF_PTR_V1_8822C 0x1118 +#define REG_RXFF_WTR_V1_8822C 0x111C +#define REG_FE2IMR_8822C 0x1120 +#define REG_FE2ISR_8822C 0x1124 +#define REG_FE3IMR_8822C 0x1128 +#define REG_FE3ISR_8822C 0x112C +#define REG_FE4IMR_8822C 0x1130 +#define REG_FE4ISR_8822C 0x1134 +#define REG_FT1IMR_8822C 0x1138 +#define REG_FT1ISR_8822C 0x113C +#define REG_SPWR0_8822C 0x1140 +#define REG_SPWR1_8822C 0x1144 +#define REG_SPWR2_8822C 0x1148 +#define REG_SPWR3_8822C 0x114C +#define REG_POWSEQ_8822C 0x1150 +#define REG_TC7_CTRL_V1_8822C 0x1158 +#define REG_TC8_CTRL_V1_8822C 0x115C +#define REG_RX_BCN_TBTT_ITVL0_8822C 0x1160 +#define REG_RX_BCN_TBTT_ITVL1_8822C 0x1164 +#define REG_IO_WRAP_ERR_FLAG_8822C 0x1170 +#define REG_SPEED_SENSOR_8822C 0x1180 +#define REG_SPEED_SENSOR1_8822C 0x1184 +#define REG_SPEED_SENSOR2_8822C 0x1188 +#define REG_SPEED_SENSOR3_8822C 0x118C +#define REG_SPEED_SENSOR4_8822C 0x1190 +#define REG_SPEED_SENSOR5_8822C 0x1194 +#define REG_COUNTER_CTRL_8822C 0x11C4 +#define REG_COUNTER_THRESHOLD_8822C 0x11C8 +#define REG_COUNTER_SET_8822C 0x11CC +#define REG_COUNTER_OVERFLOW_8822C 0x11D0 +#define REG_TXDMA_LEN_THRESHOLD_8822C 0x11D4 +#define REG_RXDMA_LEN_THRESHOLD_8822C 0x11D8 +#define REG_PCIE_EXEC_TIME_THRESHOLD_8822C 0x11DC +#define REG_FT2IMR_8822C 0x11E0 +#define REG_FT2ISR_8822C 0x11E4 +#define REG_MSG2_8822C 0x11F0 +#define REG_MSG3_8822C 0x11F4 +#define REG_MSG4_8822C 0x11F8 +#define REG_MSG5_8822C 0x11FC +#define REG_FIFOPAGE_CTRL_1_8822C 0x0200 +#define REG_FIFOPAGE_CTRL_2_8822C 0x0204 +#define REG_AUTO_LLT_V1_8822C 0x0208 +#define REG_TXDMA_OFFSET_CHK_8822C 0x020C +#define REG_TXDMA_STATUS_8822C 0x0210 +#define REG_TX_DMA_DBG_8822C 0x0214 +#define REG_TQPNT1_8822C 0x0218 +#define REG_TQPNT2_8822C 0x021C +#define REG_TQPNT3_8822C 0x0220 +#define REG_TQPNT4_8822C 0x0224 +#define REG_RQPN_CTRL_1_8822C 0x0228 +#define REG_RQPN_CTRL_2_8822C 0x022C +#define REG_FIFOPAGE_INFO_1_8822C 0x0230 +#define REG_FIFOPAGE_INFO_2_8822C 0x0234 +#define REG_FIFOPAGE_INFO_3_8822C 0x0238 +#define REG_FIFOPAGE_INFO_4_8822C 0x023C +#define REG_FIFOPAGE_INFO_5_8822C 0x0240 +#define REG_H2C_HEAD_8822C 0x0244 +#define REG_H2C_TAIL_8822C 0x0248 +#define REG_H2C_READ_ADDR_8822C 0x024C +#define REG_H2C_WR_ADDR_8822C 0x0250 +#define REG_H2C_INFO_8822C 0x0254 +#define REG_PGSUB_CNT_8822C 0x026C +#define REG_PGSUB_H_8822C 0x0270 +#define REG_PGSUB_N_8822C 0x0274 +#define REG_PGSUB_L_8822C 0x0278 +#define REG_PGSUB_E_8822C 0x027C +#define REG_RXDMA_AGG_PG_TH_8822C 0x0280 +#define REG_RXPKT_NUM_8822C 0x0284 +#define REG_RXDMA_STATUS_8822C 0x0288 +#define REG_RXDMA_DPR_8822C 0x028C +#define REG_RXDMA_MODE_8822C 0x0290 +#define REG_C2H_PKT_8822C 0x0294 +#define REG_FWFF_C2H_8822C 0x0298 +#define REG_FWFF_CTRL_8822C 0x029C +#define REG_FWFF_PKT_INFO_8822C 0x02A0 +#define REG_RXPKTNUM_8822C 0x02B0 +#define REG_RXPKTNUM_TH_8822C 0x02B4 +#define REG_FW_MSG1_8822C 0x02E0 +#define REG_FW_MSG2_8822C 0x02E4 +#define REG_FW_MSG3_8822C 0x02E8 +#define REG_FW_MSG4_8822C 0x02EC +#define REG_DDMA_CH0SA_8822C 0x1200 +#define REG_DDMA_CH0DA_8822C 0x1204 +#define REG_DDMA_CH0CTRL_8822C 0x1208 +#define REG_DDMA_CH1SA_8822C 0x1210 +#define REG_DDMA_CH1DA_8822C 0x1214 +#define REG_DDMA_CH1CTRL_8822C 0x1218 +#define REG_DDMA_CH2SA_8822C 0x1220 +#define REG_DDMA_CH2DA_8822C 0x1224 +#define REG_DDMA_CH2CTRL_8822C 0x1228 +#define REG_DDMA_CH3SA_8822C 0x1230 +#define REG_DDMA_CH3DA_8822C 0x1234 +#define REG_DDMA_CH3CTRL_8822C 0x1238 +#define REG_DDMA_CH4SA_8822C 0x1240 +#define REG_DDMA_CH4DA_8822C 0x1244 +#define REG_DDMA_CH4CTRL_8822C 0x1248 +#define REG_DDMA_CH5SA_8822C 0x1250 +#define REG_DDMA_CH5DA_8822C 0x1254 +#define REG_DDMA_CH5CTRL_8822C 0x1258 +#define REG_DDMA_INT_MSK_8822C 0x12E0 +#define REG_DDMA_CHSTATUS_8822C 0x12E8 +#define REG_DDMA_CHKSUM_8822C 0x12F0 +#define REG_DDMA_MONITOR_8822C 0x12FC +#define REG_PCIE_CTRL_8822C 0x0300 +#define REG_INT_MIG_8822C 0x0304 +#define REG_BCNQ_TXBD_DESA_8822C 0x0308 +#define REG_MGQ_TXBD_DESA_8822C 0x0310 +#define REG_VOQ_TXBD_DESA_8822C 0x0318 +#define REG_VIQ_TXBD_DESA_8822C 0x0320 +#define REG_BEQ_TXBD_DESA_8822C 0x0328 +#define REG_BKQ_TXBD_DESA_8822C 0x0330 +#define REG_RXQ_RXBD_DESA_8822C 0x0338 +#define REG_HI0Q_TXBD_DESA_8822C 0x0340 +#define REG_HI1Q_TXBD_DESA_8822C 0x0348 +#define REG_HI2Q_TXBD_DESA_8822C 0x0350 +#define REG_HI3Q_TXBD_DESA_8822C 0x0358 +#define REG_HI4Q_TXBD_DESA_8822C 0x0360 +#define REG_HI5Q_TXBD_DESA_8822C 0x0368 +#define REG_HI6Q_TXBD_DESA_8822C 0x0370 +#define REG_HI7Q_TXBD_DESA_8822C 0x0378 +#define REG_MGQ_TXBD_NUM_8822C 0x0380 +#define REG_RX_RXBD_NUM_8822C 0x0382 +#define REG_VOQ_TXBD_NUM_8822C 0x0384 +#define REG_VIQ_TXBD_NUM_8822C 0x0386 +#define REG_BEQ_TXBD_NUM_8822C 0x0388 +#define REG_BKQ_TXBD_NUM_8822C 0x038A +#define REG_HI0Q_TXBD_NUM_8822C 0x038C +#define REG_HI1Q_TXBD_NUM_8822C 0x038E +#define REG_HI2Q_TXBD_NUM_8822C 0x0390 +#define REG_HI3Q_TXBD_NUM_8822C 0x0392 +#define REG_HI4Q_TXBD_NUM_8822C 0x0394 +#define REG_HI5Q_TXBD_NUM_8822C 0x0396 +#define REG_HI6Q_TXBD_NUM_8822C 0x0398 +#define REG_HI7Q_TXBD_NUM_8822C 0x039A +#define REG_TSFTIMER_HCI_8822C 0x039C +#define REG_BD_RWPTR_CLR_8822C 0x039C +#define REG_VOQ_TXBD_IDX_8822C 0x03A0 +#define REG_VIQ_TXBD_IDX_8822C 0x03A4 +#define REG_BEQ_TXBD_IDX_8822C 0x03A8 +#define REG_BKQ_TXBD_IDX_8822C 0x03AC +#define REG_MGQ_TXBD_IDX_8822C 0x03B0 +#define REG_RXQ_RXBD_IDX_8822C 0x03B4 +#define REG_HI0Q_TXBD_IDX_8822C 0x03B8 +#define REG_HI1Q_TXBD_IDX_8822C 0x03BC +#define REG_HI2Q_TXBD_IDX_8822C 0x03C0 +#define REG_HI3Q_TXBD_IDX_8822C 0x03C4 +#define REG_HI4Q_TXBD_IDX_8822C 0x03C8 +#define REG_HI5Q_TXBD_IDX_8822C 0x03CC +#define REG_HI6Q_TXBD_IDX_8822C 0x03D0 +#define REG_HI7Q_TXBD_IDX_8822C 0x03D4 +#define REG_DBG_SEL_V1_8822C 0x03D8 +#define REG_PCIE_HRPWM1_V1_8822C 0x03D9 +#define REG_PCIE_HCPWM1_V1_8822C 0x03DA +#define REG_PCIE_CTRL2_8822C 0x03DB +#define REG_PCIE_HRPWM2_V1_8822C 0x03DC +#define REG_PCIE_HCPWM2_V1_8822C 0x03DE +#define REG_PCIE_H2C_MSG_V1_8822C 0x03E0 +#define REG_PCIE_C2H_MSG_V1_8822C 0x03E4 +#define REG_DBI_WDATA_V1_8822C 0x03E8 +#define REG_DBI_RDATA_V1_8822C 0x03EC +#define REG_DBI_FLAG_V1_8822C 0x03F0 +#define REG_MDIO_V1_8822C 0x03F4 +#define REG_PCIE_MIX_CFG_8822C 0x03F8 +#define REG_HCI_MIX_CFG_8822C 0x03FC +#define REG_STC_INT_CS_8822C 0x1300 +#define REG_ST_INT_CFG_8822C 0x1304 +#define REG_H2CQ_TXBD_DESA_8822C 0x1320 +#define REG_H2CQ_TXBD_NUM_8822C 0x1328 +#define REG_H2CQ_TXBD_IDX_8822C 0x132C +#define REG_H2CQ_CSR_8822C 0x1330 +#define REG_CHANGE_PCIE_SPEED_8822C 0x1350 +#define REG_DEBUG_STATE1_8822C 0x1354 +#define REG_DEBUG_STATE2_8822C 0x1358 +#define REG_DEBUG_STATE3_8822C 0x135C +#define REG_CHNL_DMA_CFG_V1_8822C 0x137C +#define REG_PCIE_HISR0_V1_8822C 0x13B4 +#define REG_PCIE_HISR1_V1_8822C 0x13BC +#define REG_PCIE_HISR2_V1_8822C 0x23B4 +#define REG_PCIE_HISR3_V1_8822C 0x23BC +#define REG_Q0_INFO_8822C 0x0400 +#define REG_Q1_INFO_8822C 0x0404 +#define REG_Q2_INFO_8822C 0x0408 +#define REG_Q3_INFO_8822C 0x040C +#define REG_MGQ_INFO_8822C 0x0410 +#define REG_HIQ_INFO_8822C 0x0414 +#define REG_BCNQ_INFO_8822C 0x0418 +#define REG_TXPKT_EMPTY_8822C 0x041A +#define REG_CPU_MGQ_INFO_8822C 0x041C +#define REG_FWHW_TXQ_CTRL_8822C 0x0420 +#define REG_DATAFB_SEL_8822C 0x0423 +#define REG_BCNQ_BDNY_V1_8822C 0x0424 +#define REG_LIFETIME_EN_8822C 0x0426 +#define REG_SPEC_SIFS_8822C 0x0428 +#define REG_RETRY_LIMIT_8822C 0x042A +#define REG_TXBF_CTRL_8822C 0x042C +#define REG_DARFRC_8822C 0x0430 +#define REG_DARFRCH_8822C 0x0434 +#define REG_RARFRC_8822C 0x0438 +#define REG_RARFRCH_8822C 0x043C +#define REG_RRSR_8822C 0x0440 +#define REG_ARFR0_8822C 0x0444 +#define REG_ARFRH0_8822C 0x0448 +#define REG_ARFR1_V1_8822C 0x044C +#define REG_ARFRH1_V1_8822C 0x0450 +#define REG_CCK_CHECK_8822C 0x0454 +#define REG_AMPDU_MAX_TIME_V1_8822C 0x0455 +#define REG_BCNQ1_BDNY_V1_8822C 0x0456 +#define REG_AMPDU_MAX_LENGTH_HT_8822C 0x0458 +#define REG_ACQ_STOP_8822C 0x045C +#define REG_NDPA_RATE_8822C 0x045D +#define REG_TX_HANG_CTRL_8822C 0x045E +#define REG_NDPA_OPT_CTRL_8822C 0x045F +#define REG_AMPDU_MAX_LENGTH_VHT_8822C 0x0460 +#define REG_RD_RESP_PKT_TH_8822C 0x0463 +#define REG_CMDQ_INFO_8822C 0x0464 +#define REG_Q4_INFO_8822C 0x0468 +#define REG_Q5_INFO_8822C 0x046C +#define REG_Q6_INFO_8822C 0x0470 +#define REG_Q7_INFO_8822C 0x0474 +#define REG_WMAC_LBK_BUF_HD_V1_8822C 0x0478 +#define REG_MGQ_BDNY_V1_8822C 0x047A +#define REG_TXRPT_CTRL_8822C 0x047C +#define REG_INIRTS_RATE_SEL_8822C 0x0480 +#define REG_BASIC_CFEND_RATE_8822C 0x0481 +#define REG_STBC_CFEND_RATE_8822C 0x0482 +#define REG_DATA_SC_8822C 0x0483 +#define REG_MACID_SLEEP3_8822C 0x0484 +#define REG_MACID_SLEEP1_8822C 0x0488 +#define REG_ARFR2_V1_8822C 0x048C +#define REG_ARFRH2_V1_8822C 0x0490 +#define REG_ARFR3_V1_8822C 0x0494 +#define REG_ARFRH3_V1_8822C 0x0498 +#define REG_ARFR4_8822C 0x049C +#define REG_ARFRH4_8822C 0x04A0 +#define REG_ARFR5_8822C 0x04A4 +#define REG_ARFRH5_8822C 0x04A8 +#define REG_TXRPT_START_OFFSET_8822C 0x04AC +#define REG_POWER_STAGE1_8822C 0x04B4 +#define REG_POWER_STAGE2_8822C 0x04B8 +#define REG_SW_AMPDU_BURST_MODE_CTRL_8822C 0x04BC +#define REG_PKT_LIFE_TIME_8822C 0x04C0 +#define REG_STBC_SETTING_8822C 0x04C4 +#define REG_STBC_SETTING2_8822C 0x04C5 +#define REG_QUEUE_CTRL_8822C 0x04C6 +#define REG_SINGLE_AMPDU_CTRL_8822C 0x04C7 +#define REG_PROT_MODE_CTRL_8822C 0x04C8 +#define REG_BAR_MODE_CTRL_8822C 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8822C 0x04CF +#define REG_MACID_SLEEP2_8822C 0x04D0 +#define REG_MACID_SLEEP_8822C 0x04D4 +#define REG_HW_SEQ0_8822C 0x04D8 +#define REG_HW_SEQ1_8822C 0x04DA +#define REG_HW_SEQ2_8822C 0x04DC +#define REG_HW_SEQ3_8822C 0x04DE +#define REG_NULL_PKT_STATUS_V1_8822C 0x04E0 +#define REG_PTCL_ERR_STATUS_8822C 0x04E2 +#define REG_NULL_PKT_STATUS_EXTEND_8822C 0x04E3 +#define REG_HQMGQ_DROP_8822C 0x04E4 +#define REG_PRECNT_CTRL_8822C 0x04E5 +#define REG_BT_POLLUTE_PKT_CNT_8822C 0x04E8 +#define REG_PTCL_DBG_8822C 0x04EC +#define REG_CPUMGQ_TIMER_CTRL2_8822C 0x04F4 +#define REG_DUMMY_PAGE4_V1_8822C 0x04FC +#define REG_MOREDATA_8822C 0x04FE +#define REG_Q0_Q1_INFO_8822C 0x1400 +#define REG_Q2_Q3_INFO_8822C 0x1404 +#define REG_Q4_Q5_INFO_8822C 0x1408 +#define REG_Q6_Q7_INFO_8822C 0x140C +#define REG_MGQ_HIQ_INFO_8822C 0x1410 +#define REG_CMDQ_BCNQ_INFO_8822C 0x1414 +#define REG_LOOPBACK_OPTION_8822C 0x1420 +#define REG_AESIV_SETTING_8822C 0x1424 +#define REG_BF0_TIME_SETTING_8822C 0x1428 +#define REG_BF1_TIME_SETTING_8822C 0x142C +#define REG_BF_TIMEOUT_EN_8822C 0x1430 +#define REG_MACID_RELEASE0_8822C 0x1434 +#define REG_MACID_RELEASE1_8822C 0x1438 +#define REG_MACID_RELEASE2_8822C 0x143C +#define REG_MACID_RELEASE3_8822C 0x1440 +#define REG_MACID_RELEASE_SETTING_8822C 0x1444 +#define REG_FAST_EDCA_VOVI_SETTING_8822C 0x1448 +#define REG_FAST_EDCA_BEBK_SETTING_8822C 0x144C +#define REG_MACID_DROP0_8822C 0x1450 +#define REG_MACID_DROP1_8822C 0x1454 +#define REG_MACID_DROP2_8822C 0x1458 +#define REG_MACID_DROP3_8822C 0x145C +#define REG_R_MACID_RELEASE_SUCCESS_0_8822C 0x1460 +#define REG_R_MACID_RELEASE_SUCCESS_1_8822C 0x1464 +#define REG_R_MACID_RELEASE_SUCCESS_2_8822C 0x1468 +#define REG_R_MACID_RELEASE_SUCCESS_3_8822C 0x146C +#define REG_MGQ_FIFO_WRITE_POINTER_8822C 0x1470 +#define REG_MGQ_FIFO_READ_POINTER_8822C 0x1472 +#define REG_MGQ_FIFO_ENABLE_8822C 0x1472 +#define REG_MGQ_FIFO_RELEASE_INT_MASK_8822C 0x1474 +#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8822C 0x1476 +#define REG_MGQ_FIFO_VALID_MAP_8822C 0x1478 +#define REG_MGQ_FIFO_LIFETIME_8822C 0x147A +#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0x147C +#define REG_SHCUT_SETTING_8822C 0x1480 +#define REG_SHCUT_LLC_ETH_TYPE0_8822C 0x1484 +#define REG_SHCUT_LLC_ETH_TYPE1_8822C 0x1488 +#define REG_SHCUT_LLC_OUI0_8822C 0x148C +#define REG_SHCUT_LLC_OUI1_8822C 0x1490 +#define REG_SHCUT_LLC_OUI2_8822C 0x1494 +#define REG_MU_TX_CTL_8822C 0x14C0 +#define REG_MU_STA_GID_VLD_8822C 0x14C4 +#define REG_MU_STA_USER_POS_INFO_8822C 0x14C8 +#define REG_MU_STA_USER_POS_INFO_H_8822C 0x14CC +#define REG_CHNL_INFO_CTRL_8822C 0x14D0 +#define REG_CHNL_IDLE_TIME_8822C 0x14D4 +#define REG_CHNL_BUSY_TIME_8822C 0x14D8 +#define REG_MU_TRX_DBG_CNT_V1_8822C 0x14DC +#define REG_EDCA_VO_PARAM_8822C 0x0500 +#define REG_EDCA_VI_PARAM_8822C 0x0504 +#define REG_EDCA_BE_PARAM_8822C 0x0508 +#define REG_EDCA_BK_PARAM_8822C 0x050C +#define REG_BCNTCFG_8822C 0x0510 +#define REG_PIFS_8822C 0x0512 +#define REG_RDG_PIFS_8822C 0x0513 +#define REG_SIFS_8822C 0x0514 +#define REG_TSFTR_SYN_OFFSET_8822C 0x0518 +#define REG_AGGR_BREAK_TIME_8822C 0x051A +#define REG_SLOT_8822C 0x051B +#define REG_NOA_ON_ERLY_TIME_8822C 0x051C +#define REG_NOA_OFF_ERLY_TIME_8822C 0x051D +#define REG_TX_PTCL_CTRL_8822C 0x0520 +#define REG_TXPAUSE_8822C 0x0522 +#define REG_DIS_TXREQ_CLR_8822C 0x0523 +#define REG_RD_CTRL_8822C 0x0524 +#define REG_MBSSID_CTRL_8822C 0x0526 +#define REG_P2PPS_CTRL_8822C 0x0527 +#define REG_PKT_LIFETIME_CTRL_8822C 0x0528 +#define REG_P2PPS_SPEC_STATE_8822C 0x052B +#define REG_TXOP_LIMIT_CTRL_8822C 0x052C +#define REG_BAR_TX_CTRL_8822C 0x0530 +#define REG_P2PON_DIS_TXTIME_8822C 0x0531 +#define REG_CCA_TXEN_CNT_8822C 0x0534 +#define REG_MAX_INTER_COLLISION_8822C 0x0538 +#define REG_MAX_INTER_COLLISION_CNT_8822C 0x053C +#define REG_TBTT_PROHIBIT_8822C 0x0540 +#define REG_P2PPS_STATE_8822C 0x0543 +#define REG_RD_NAV_NXT_8822C 0x0544 +#define REG_NAV_PROT_LEN_8822C 0x0546 +#define REG_FTM_PTT_8822C 0x0548 +#define REG_FTM_TSF_8822C 0x054C +#define REG_BCN_CTRL_8822C 0x0550 +#define REG_BCN_CTRL_CLINT0_8822C 0x0551 +#define REG_MBID_NUM_8822C 0x0552 +#define REG_DUAL_TSF_RST_8822C 0x0553 +#define REG_MBSSID_BCN_SPACE_8822C 0x0554 +#define REG_DRVERLYINT_8822C 0x0558 +#define REG_BCNDMATIM_8822C 0x0559 +#define REG_ATIMWND_8822C 0x055A +#define REG_USTIME_TSF_8822C 0x055C +#define REG_BCN_MAX_ERR_8822C 0x055D +#define REG_RXTSF_OFFSET_CCK_8822C 0x055E +#define REG_RXTSF_OFFSET_OFDM_8822C 0x055F +#define REG_TSFTR_8822C 0x0560 +#define REG_TSFTR_1_8822C 0x0564 +#define REG_FREERUN_CNT_8822C 0x0568 +#define REG_FREERUN_CNT_1_8822C 0x056C +#define REG_ATIMWND1_V1_8822C 0x0570 +#define REG_TBTT_PROHIBIT_INFRA_8822C 0x0571 +#define REG_CTWND_8822C 0x0572 +#define REG_BCNIVLCUNT_8822C 0x0573 +#define REG_BCNDROPCTRL_8822C 0x0574 +#define REG_HGQ_TIMEOUT_PERIOD_8822C 0x0575 +#define REG_TXCMD_TIMEOUT_PERIOD_8822C 0x0576 +#define REG_MISC_CTRL_8822C 0x0577 +#define REG_BCN_CTRL_CLINT1_8822C 0x0578 +#define REG_BCN_CTRL_CLINT2_8822C 0x0579 +#define REG_BCN_CTRL_CLINT3_8822C 0x057A +#define REG_EXTEND_CTRL_8822C 0x057B +#define REG_P2PPS1_SPEC_STATE_8822C 0x057C +#define REG_P2PPS1_STATE_8822C 0x057D +#define REG_P2PPS2_SPEC_STATE_8822C 0x057E +#define REG_P2PPS2_STATE_8822C 0x057F +#define REG_PS_TIMER0_8822C 0x0580 +#define REG_PS_TIMER1_8822C 0x0584 +#define REG_PS_TIMER2_8822C 0x0588 +#define REG_TBTT_CTN_AREA_8822C 0x058C +#define REG_FORCE_BCN_IFS_8822C 0x058E +#define REG_TXOP_MIN_8822C 0x0590 +#define REG_PRE_BKF_TIME_8822C 0x0592 +#define REG_CROSS_TXOP_CTRL_8822C 0x0593 +#define REG_RX_TBTT_SHIFT_V1_8822C 0x0598 +#define REG_ATIMWND2_8822C 0x05A0 +#define REG_ATIMWND3_8822C 0x05A1 +#define REG_ATIMWND4_8822C 0x05A2 +#define REG_ATIMWND5_8822C 0x05A3 +#define REG_ATIMWND6_8822C 0x05A4 +#define REG_ATIMWND7_8822C 0x05A5 +#define REG_ATIMUGT_8822C 0x05A6 +#define REG_HIQ_NO_LMT_EN_8822C 0x05A7 +#define REG_DTIM_COUNTER_ROOT_8822C 0x05A8 +#define REG_DTIM_COUNTER_VAP1_8822C 0x05A9 +#define REG_DTIM_COUNTER_VAP2_8822C 0x05AA +#define REG_DTIM_COUNTER_VAP3_8822C 0x05AB +#define REG_DTIM_COUNTER_VAP4_8822C 0x05AC +#define REG_DTIM_COUNTER_VAP5_8822C 0x05AD +#define REG_DTIM_COUNTER_VAP6_8822C 0x05AE +#define REG_DTIM_COUNTER_VAP7_8822C 0x05AF +#define REG_DIS_ATIM_8822C 0x05B0 +#define REG_EARLY_128US_8822C 0x05B1 +#define REG_P2PPS1_CTRL_8822C 0x05B2 +#define REG_P2PPS2_CTRL_8822C 0x05B3 +#define REG_TIMER0_SRC_SEL_8822C 0x05B4 +#define REG_NOA_UNIT_SEL_8822C 0x05B5 +#define REG_P2POFF_DIS_TXTIME_8822C 0x05B7 +#define REG_MBSSID_BCN_SPACE2_8822C 0x05B8 +#define REG_MBSSID_BCN_SPACE3_8822C 0x05BC +#define REG_ACMHWCTRL_8822C 0x05C0 +#define REG_ACMRSTCTRL_8822C 0x05C1 +#define REG_ACMAVG_8822C 0x05C2 +#define REG_VO_ADMTIME_8822C 0x05C4 +#define REG_VI_ADMTIME_8822C 0x05C6 +#define REG_BE_ADMTIME_8822C 0x05C8 +#define REG_MAC_HEADER_NAV_OFFSET_8822C 0x05CA +#define REG_DIS_NDPA_NAV_CHECK_8822C 0x05CB +#define REG_EDCA_RANDOM_GEN_8822C 0x05CC +#define REG_TXCMD_NOA_SEL_8822C 0x05CF +#define REG_32K_CLK_SEL_8822C 0x05D0 +#define REG_EARLYINT_ADJUST_8822C 0x05D4 +#define REG_BCNERR_CNT_8822C 0x05D8 +#define REG_BCNERR_CNT_2_8822C 0x05DC +#define REG_NOA_PARAM_8822C 0x05E0 +#define REG_NOA_PARAM_1_8822C 0x05E4 +#define REG_NOA_PARAM_2_8822C 0x05E8 +#define REG_NOA_PARAM_3_8822C 0x05EC +#define REG_P2P_RST_8822C 0x05F0 +#define REG_SCHEDULER_RST_8822C 0x05F1 +#define REG_SCH_DBG_VALUE_8822C 0x05F4 +#define REG_SCH_TXCMD_8822C 0x05F8 +#define REG_PAGE5_DUMMY_8822C 0x05FC +#define REG_CPUMGQ_TX_TIMER_8822C 0x1500 +#define REG_PS_TIMER_A_8822C 0x1504 +#define REG_PS_TIMER_B_8822C 0x1508 +#define REG_PS_TIMER_C_8822C 0x150C +#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822C 0x1510 +#define REG_CPUMGQ_TX_TIMER_EARLY_8822C 0x1514 +#define REG_PS_TIMER_A_EARLY_8822C 0x1515 +#define REG_PS_TIMER_B_EARLY_8822C 0x1516 +#define REG_PS_TIMER_C_EARLY_8822C 0x1517 +#define REG_CPUMGQ_PARAMETER_8822C 0x1518 +#define REG_TSF_SYNC_ADJ_8822C 0x1520 +#define REG_TSF_ADJ_VLAUE_8822C 0x1524 +#define REG_TSF_ADJ_VLAUE_2_8822C 0x1528 +#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C 0x156C +#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C 0x1570 +#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C 0x1574 +#define REG_SCHEDULER_COUNTER_8822C 0x15D0 +#define REG_WMAC_CR_8822C 0x0600 +#define REG_WMAC_FWPKT_CR_8822C 0x0601 +#define REG_FW_STS_FILTER_8822C 0x0602 +#define REG_TCR_8822C 0x0604 +#define REG_RCR_8822C 0x0608 +#define REG_RX_PKT_LIMIT_8822C 0x060C +#define REG_RX_DLK_TIME_8822C 0x060D +#define REG_RX_DRVINFO_SZ_8822C 0x060F +#define REG_MACID_8822C 0x0610 +#define REG_MACID_H_8822C 0x0614 +#define REG_BSSID_8822C 0x0618 +#define REG_BSSID_H_8822C 0x061C +#define REG_MAR_8822C 0x0620 +#define REG_MAR_H_8822C 0x0624 +#define REG_MBIDCAMCFG_1_8822C 0x0628 +#define REG_MBIDCAMCFG_2_8822C 0x062C +#define REG_WMAC_TCR_TSFT_OFS_8822C 0x0630 +#define REG_UDF_THSD_8822C 0x0632 +#define REG_ZLD_NUM_8822C 0x0633 +#define REG_STMP_THSD_8822C 0x0634 +#define REG_WMAC_TXTIMEOUT_8822C 0x0635 +#define REG_USTIME_EDCA_8822C 0x0638 +#define REG_ACKTO_CCK_8822C 0x0639 +#define REG_MAC_SPEC_SIFS_8822C 0x063A +#define REG_RESP_SIFS_CCK_8822C 0x063C +#define REG_RESP_SIFS_OFDM_8822C 0x063E +#define REG_ACKTO_8822C 0x0640 +#define REG_CTS2TO_8822C 0x0641 +#define REG_EIFS_8822C 0x0642 +#define REG_RPFM_MAP0_8822C 0x0644 +#define REG_RPFM_MAP1_V1_8822C 0x0646 +#define REG_RPFM_CAM_CMD_8822C 0x0648 +#define REG_RPFM_CAM_RWD_8822C 0x064C +#define REG_NAV_CTRL_8822C 0x0650 +#define REG_BACAMCMD_8822C 0x0654 +#define REG_BACAMCONTENT_8822C 0x0658 +#define REG_BACAMCONTENT_H_8822C 0x065C +#define REG_LBDLY_8822C 0x0660 +#define REG_WMAC_BACAM_RPMEN_8822C 0x0661 +#define REG_TX_RX_8822C 0x0662 +#define REG_WMAC_BITMAP_CTL_8822C 0x0663 +#define REG_RXERR_RPT_8822C 0x0664 +#define REG_WMAC_TRXPTCL_CTL_8822C 0x0668 +#define REG_WMAC_TRXPTCL_CTL_H_8822C 0x066C +#define REG_CAMCMD_8822C 0x0670 +#define REG_CAMWRITE_8822C 0x0674 +#define REG_CAMREAD_8822C 0x0678 +#define REG_CAMDBG_8822C 0x067C +#define REG_SECCFG_8822C 0x0680 +#define REG_RXFILTER_CATEGORY_1_8822C 0x0682 +#define REG_RXFILTER_ACTION_1_8822C 0x0683 +#define REG_RXFILTER_CATEGORY_2_8822C 0x0684 +#define REG_RXFILTER_ACTION_2_8822C 0x0685 +#define REG_RXFILTER_CATEGORY_3_8822C 0x0686 +#define REG_RXFILTER_ACTION_3_8822C 0x0687 +#define REG_RXFLTMAP3_8822C 0x0688 +#define REG_RXFLTMAP4_8822C 0x068A +#define REG_RXFLTMAP5_8822C 0x068C +#define REG_RXFLTMAP6_8822C 0x068E +#define REG_WOW_CTRL_8822C 0x0690 +#define REG_NAN_RX_TSF_FILTER_8822C 0x0691 +#define REG_PS_RX_INFO_8822C 0x0692 +#define REG_WMMPS_UAPSD_TID_8822C 0x0693 +#define REG_LPNAV_CTRL_8822C 0x0694 +#define REG_WKFMCAM_CMD_8822C 0x0698 +#define REG_WKFMCAM_RWD_8822C 0x069C +#define REG_RXFLTMAP0_8822C 0x06A0 +#define REG_RXFLTMAP1_8822C 0x06A2 +#define REG_RXFLTMAP2_8822C 0x06A4 +#define REG_BCN_PSR_RPT_8822C 0x06A8 +#define REG_FLC_RPC_8822C 0x06AC +#define REG_FLC_RPCT_8822C 0x06AD +#define REG_FLC_PTS_8822C 0x06AE +#define REG_FLC_TRPC_8822C 0x06AF +#define REG_RXPKTMON_CTRL_8822C 0x06B0 +#define REG_STATE_MON_8822C 0x06B4 +#define REG_ERROR_MON_8822C 0x06B8 +#define REG_SEARCH_MACID_8822C 0x06BC +#define REG_BT_COEX_TABLE_8822C 0x06C0 +#define REG_BT_COEX_TABLE2_8822C 0x06C4 +#define REG_BT_COEX_BREAK_TABLE_8822C 0x06C8 +#define REG_BT_COEX_TABLE_H_8822C 0x06CC +#define REG_RXCMD_0_8822C 0x06D0 +#define REG_RXCMD_1_8822C 0x06D4 +#define REG_WMAC_RESP_TXINFO_8822C 0x06D8 +#define REG_BBPSF_CTRL_8822C 0x06DC +#define REG_P2P_RX_BCN_NOA_8822C 0x06E0 +#define REG_ASSOCIATED_BFMER0_INFO_8822C 0x06E4 +#define REG_ASSOCIATED_BFMER0_INFO_H_8822C 0x06E8 +#define REG_ASSOCIATED_BFMER1_INFO_8822C 0x06EC +#define REG_ASSOCIATED_BFMER1_INFO_H_8822C 0x06F0 +#define REG_TX_CSI_RPT_PARAM_BW20_8822C 0x06F4 +#define REG_TX_CSI_RPT_PARAM_BW40_8822C 0x06F8 +#define REG_CSI_PTR_8822C 0x06FC +#define REG_BCN_PSR_RPT2_8822C 0x1600 +#define REG_BCN_PSR_RPT3_8822C 0x1604 +#define REG_BCN_PSR_RPT4_8822C 0x1608 +#define REG_A1_ADDR_MASK_8822C 0x160C +#define REG_RXPSF_CTRL_8822C 0x1610 +#define REG_RXPSF_TYPE_CTRL_8822C 0x1614 +#define REG_CAM_ACCESS_CTRL_8822C 0x1618 +#define REG_HT_SND_REF_RATE_8822C 0x161C +#define REG_MACID2_8822C 0x1620 +#define REG_MACID2_H_8822C 0x1624 +#define REG_BSSID2_8822C 0x1628 +#define REG_BSSID2_H_8822C 0x162C +#define REG_MACID3_8822C 0x1630 +#define REG_MACID3_H_8822C 0x1634 +#define REG_BSSID3_8822C 0x1638 +#define REG_BSSID3_H_8822C 0x163C +#define REG_MACID4_8822C 0x1640 +#define REG_MACID4_H_8822C 0x1644 +#define REG_BSSID4_8822C 0x1648 +#define REG_BSSID4_H_8822C 0x164C +#define REG_NOA_REPORT_8822C 0x1650 +#define REG_NOA_REPORT_1_8822C 0x1654 +#define REG_NOA_REPORT_2_8822C 0x1658 +#define REG_NOA_REPORT_3_8822C 0x165C +#define REG_PWRBIT_SETTING_8822C 0x1660 +#define REG_GENERAL_OPTION_8822C 0x1664 +#define REG_CSI_RRSR_8822C 0x1678 +#define REG_MU_BF_OPTION_8822C 0x167C +#define REG_WMAC_PAUSE_BB_CLR_TH_8822C 0x167D +#define REG__WMAC_MULBK_BUF_8822C 0x167E +#define REG_WMAC_MU_OPTION_8822C 0x167F +#define REG_WMAC_MU_BF_CTL_8822C 0x1680 +#define REG_WMAC_MU_BFRPT_PARA_8822C 0x1682 +#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C 0x1684 +#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C 0x1686 +#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C 0x1688 +#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C 0x168A +#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C 0x168C +#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C 0x168E +#define REG_WMAC_BB_STOP_RX_COUNTER_8822C 0x1690 +#define REG_WMAC_PLCP_MONITOR_8822C 0x1694 +#define REG_WMAC_PLCP_MONITOR_MUTX_8822C 0x1698 +#define REG_WMAC_CSIDMA_CFG_8822C 0x169C +#define REG_TRANSMIT_ADDRSS_0_8822C 0x16A0 +#define REG_TRANSMIT_ADDRSS_0_H_8822C 0x16A4 +#define REG_TRANSMIT_ADDRSS_1_8822C 0x16A8 +#define REG_TRANSMIT_ADDRSS_1_H_8822C 0x16AC +#define REG_TRANSMIT_ADDRSS_2_8822C 0x16B0 +#define REG_TRANSMIT_ADDRSS_2_H_8822C 0x16B4 +#define REG_TRANSMIT_ADDRSS_3_8822C 0x16B8 +#define REG_TRANSMIT_ADDRSS_3_H_8822C 0x16BC +#define REG_TRANSMIT_ADDRSS_4_8822C 0x16C0 +#define REG_TRANSMIT_ADDRSS_4_H_8822C 0x16C4 +#define REG_MACID1_8822C 0x0700 +#define REG_MACID1_1_8822C 0x0704 +#define REG_BSSID1_8822C 0x0708 +#define REG_BSSID1_1_8822C 0x070C +#define REG_BCN_PSR_RPT1_8822C 0x0710 +#define REG_ASSOCIATED_BFMEE_SEL_8822C 0x0714 +#define REG_SND_PTCL_CTRL_8822C 0x0718 +#define REG_RX_CSI_RPT_INFO_8822C 0x071C +#define REG_NS_ARP_CTRL_8822C 0x0720 +#define REG_NS_ARP_INFO_8822C 0x0724 +#define REG_BEAMFORMING_INFO_NSARP_V1_8822C 0x0728 +#define REG_BEAMFORMING_INFO_NSARP_8822C 0x072C +#define REG_IPV6_8822C 0x0730 +#define REG_IPV6_1_8822C 0x0734 +#define REG_IPV6_2_8822C 0x0738 +#define REG_IPV6_3_8822C 0x073C +#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822C 0x0750 +#define REG_WMAC_SWAES_DIO_B63_B32_8822C 0x0754 +#define REG_WMAC_SWAES_DIO_B95_B64_8822C 0x0758 +#define REG_WMAC_SWAES_DIO_B127_B96_8822C 0x075C +#define REG_WMAC_SWAES_CFG_8822C 0x0760 +#define REG_BT_COEX_V2_8822C 0x0762 +#define REG_BT_COEX_8822C 0x0764 +#define REG_WLAN_ACT_MASK_CTRL_8822C 0x0768 +#define REG_WLAN_ACT_MASK_CTRL_1_8822C 0x076C +#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822C 0x076E +#define REG_BT_ACT_STATISTICS_8822C 0x0770 +#define REG_BT_ACT_STATISTICS_1_8822C 0x0774 +#define REG_BT_STATISTICS_CONTROL_REGISTER_8822C 0x0778 +#define REG_BT_STATUS_REPORT_REGISTER_8822C 0x077C +#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822C 0x0780 +#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822C 0x0784 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822C 0x0785 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8822C 0x0788 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8822C 0x078C +#define REG_BT_INTERRUPT_STATUS_REGISTER_8822C 0x078F +#define REG_BT_TDMA_TIME_REGISTER_8822C 0x0790 +#define REG_BT_ACT_REGISTER_8822C 0x0794 +#define REG_OBFF_CTRL_BASIC_8822C 0x0798 +#define REG_OBFF_CTRL2_TIMER_8822C 0x079C +#define REG_LTR_CTRL_BASIC_8822C 0x07A0 +#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822C 0x07A4 +#define REG_LTR_IDLE_LATENCY_V1_8822C 0x07A8 +#define REG_LTR_ACTIVE_LATENCY_V1_8822C 0x07AC +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822C 0x07B0 +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8822C 0x07B4 +#define REG_WMAC_PKTCNT_RWD_8822C 0x07B8 +#define REG_WMAC_PKTCNT_CTRL_8822C 0x07BC +#define REG_IQ_DUMP_8822C 0x07C0 +#define REG_IQ_DUMP_1_8822C 0x07C4 +#define REG_IQ_DUMP_2_8822C 0x07C8 +#define REG_WMAC_FTM_CTL_8822C 0x07CC +#define REG_WMAC_IQ_MDPK_FUNC_8822C 0x07CE +#define REG_WMAC_OPTION_FUNCTION_8822C 0x07D0 +#define REG_WMAC_OPTION_FUNCTION_1_8822C 0x07D4 +#define REG_WMAC_OPTION_FUNCTION_2_8822C 0x07D8 +#define REG_RX_FILTER_FUNCTION_8822C 0x07DA +#define REG_NDP_SIG_8822C 0x07E0 +#define REG_TXCMD_INFO_FOR_RSP_PKT_8822C 0x07E4 +#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8822C 0x07E8 +#define REG_WSEC_OPTION_8822C 0x07EC +#define REG_RTS_ADDRESS_0_8822C 0x07F0 +#define REG_RTS_ADDRESS_0_1_8822C 0x07F4 +#define REG_RTS_ADDRESS_1_8822C 0x07F8 +#define REG_RTS_ADDRESS_1_1_8822C 0x07FC +#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822C 0x1700 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822C 0x1704 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C 0x1708 +#define REG_SDIO_TX_CTRL_8822C 0x10250000 +#define REG_SDIO_CMD11_VOL_SWITCH_8822C 0x10250004 +#define REG_SDIO_CTRL_8822C 0x10250005 +#define REG_SDIO_DRIVING_8822C 0x10250006 +#define REG_SDIO_MONITOR_8822C 0x10250008 +#define REG_SDIO_MONITOR_2_8822C 0x1025000C +#define REG_SDIO_HIMR_8822C 0x10250014 +#define REG_SDIO_HISR_8822C 0x10250018 +#define REG_SDIO_RX_REQ_LEN_8822C 0x1025001C +#define REG_SDIO_FREE_TXPG_SEQ_V1_8822C 0x1025001F +#define REG_SDIO_FREE_TXPG_8822C 0x10250020 +#define REG_SDIO_FREE_TXPG2_8822C 0x10250024 +#define REG_SDIO_OQT_FREE_TXPG_V1_8822C 0x10250028 +#define REG_SDIO_TXPKT_EMPTY_8822C 0x1025002C +#define REG_SDIO_HTSFR_INFO_8822C 0x10250030 +#define REG_SDIO_HCPWM1_V2_8822C 0x10250038 +#define REG_SDIO_HCPWM2_V2_8822C 0x1025003A +#define REG_SDIO_INDIRECT_REG_CFG_8822C 0x10250040 +#define REG_SDIO_INDIRECT_REG_DATA_8822C 0x10250044 +#define REG_SDIO_H2C_8822C 0x10250060 +#define REG_SDIO_C2H_8822C 0x10250064 +#define REG_SDIO_HRPWM1_8822C 0x10250080 +#define REG_SDIO_HRPWM2_8822C 0x10250082 +#define REG_SDIO_HPS_CLKR_8822C 0x10250084 +#define REG_SDIO_BUS_CTRL_8822C 0x10250085 +#define REG_SDIO_HSUS_CTRL_8822C 0x10250086 +#define REG_SDIO_RESPONSE_TIMER_8822C 0x10250088 +#define REG_SDIO_CMD_CRC_8822C 0x1025008A +#define REG_SDIO_HSISR_8822C 0x10250090 +#define REG_SDIO_HSIMR_8822C 0x10250091 +#define REG_SDIO_DIOERR_RPT_8822C 0x102500C0 +#define REG_SDIO_CMD_ERRCNT_8822C 0x102500C2 +#define REG_SDIO_DATA_ERRCNT_8822C 0x102500C3 +#define REG_SDIO_CMD_ERR_CONTENT_8822C 0x102500C4 +#define REG_SDIO_CRC_ERR_IDX_8822C 0x102500C9 +#define REG_SDIO_DATA_CRC_8822C 0x102500CA +#define REG_SDIO_TRANS_FIFO_STATUS_8822C 0x102500CC + +#endif diff --git a/hal/halmac/halmac_rx_bd_nic.h b/hal/halmac/halmac_rx_bd_nic.h index dc7d5cd..442405e 100644 --- a/hal/halmac/halmac_rx_bd_nic.h +++ b/hal/halmac/halmac_rx_bd_nic.h @@ -1,25 +1,41 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_RX_BD_NIC_H_ #define _HALMAC_RX_BD_NIC_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||\ + HALMAC_8812F_SUPPORT) /*TXBD_DW0*/ -#define GET_RX_BD_RXFAIL(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 31, 1) -#define GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 16, 13) -#define GET_RX_BD_RXTAG(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 16, 13) -#define GET_RX_BD_FS(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 15, 1) -#define GET_RX_BD_LS(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 14, 1) -#define GET_RX_BD_RXBUFFSIZE(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 0, 14) +#define GET_RX_BD_RXFAIL(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 31, 1) +#define GET_RX_BD_TOTALRXPKTSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13) +#define GET_RX_BD_RXTAG(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13) +#define GET_RX_BD_FS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 15, 1) +#define GET_RX_BD_LS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 14, 1) +#define GET_RX_BD_RXBUFFSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 0, 14) /*TXBD_DW1*/ -#define GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x04, 0, 32) +#define GET_RX_BD_PHYSICAL_ADDR_LOW(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x04, 0, 32) /*TXBD_DW2*/ -#define GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x08, 0, 32) +#define GET_RX_BD_PHYSICAL_ADDR_HIGH(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x08, 0, 32) #endif - #endif diff --git a/hal/halmac/halmac_rx_desc_ap.h b/hal/halmac/halmac_rx_desc_ap.h index c71eba1..6f6991b 100644 --- a/hal/halmac/halmac_rx_desc_ap.h +++ b/hal/halmac/halmac_rx_desc_ap.h @@ -1,132 +1,630 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_RX_DESC_AP_H_ #define _HALMAC_RX_DESC_AP_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 30) -#define GET_RX_DESC_PHYPKTIDC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 28) -#define GET_RX_DESC_SWDEC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 27) -#define GET_RX_DESC_PHYST(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 26) -#define GET_RX_DESC_SHIFT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x3, 24) -#define GET_RX_DESC_QOS(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 23) -#define GET_RX_DESC_SECURITY(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x7, 20) -#define GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0xf, 16) -#define GET_RX_DESC_ICV_ERR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 15) -#define GET_RX_DESC_CRC32(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 14) -#define GET_RX_DESC_PKT_LEN(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x3fff, 0) +#define GET_RX_DESC_EOR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 30) +#define GET_RX_DESC_PHYPKTIDC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 28) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_EVT_PKT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 28) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_SWDEC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 27) +#define GET_RX_DESC_PHYST(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 26) +#define GET_RX_DESC_SHIFT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x3, \ + 24) +#define GET_RX_DESC_QOS(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 23) +#define GET_RX_DESC_SECURITY(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x7, \ + 20) +#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0xf, \ + 16) +#define GET_RX_DESC_ICV_ERR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 15) +#define GET_RX_DESC_CRC32(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \ + 14) +#define GET_RX_DESC_PKT_LEN(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, \ + 0x3fff, 0) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 31) -#define GET_RX_DESC_MC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 30) -#define GET_RX_DESC_TY_PE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x3, 28) -#define GET_RX_DESC_MF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 27) -#define GET_RX_DESC_MD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 26) -#define GET_RX_DESC_PWR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 25) -#define GET_RX_DESC_PAM(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 24) -#define GET_RX_DESC_CHK_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 23) -#define GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 22) -#define GET_RX_DESC_RX_IPV(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 21) -#define GET_RX_DESC_CHKERR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 20) -#define GET_RX_DESC_PAGGR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 15) -#define GET_RX_DESC_RXID_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 14) -#define GET_RX_DESC_AMSDU(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 13) -#define GET_RX_DESC_MACID_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 12) -#define GET_RX_DESC_TID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0xf, 8) +#define GET_RX_DESC_BC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 31) +#define GET_RX_DESC_MC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 30) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_TY_PE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3, \ + 28) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_TYPE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3, \ + 28) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_MF(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 27) +#define GET_RX_DESC_MD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 26) +#define GET_RX_DESC_PWR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 25) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_PAM(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_A1_MATCH(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 24) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_CHK_VLD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 23) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 23) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 22) +#define GET_RX_DESC_RX_IPV(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 21) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_CHKERR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 20) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 20) +#define GET_RX_DESC_PHY_PKT_IDC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 17) +#define GET_RX_DESC_FW_FIFO_FULL(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 16) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_PAGGR(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 15) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_AMPDU(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 15) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_RXID_MATCH(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 14) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_RXCMD_IDC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 14) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_AMSDU(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 13) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define GET_RX_DESC_EXT_SECTYPE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 7) +#define GET_RX_DESC_MACID_VLD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \ + 12) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_TID(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0xf, 8) + +#endif -#define GET_RX_DESC_MACID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x7f, 0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_MACID(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x7f, \ + 0) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 31) +#define GET_RX_DESC_FCS_OK(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 31) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_AMSDU_CUT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 31) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_PPDU_CNT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3, \ + 29) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_C2H(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 28) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_HWRSVD_V1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x7, \ + 25) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_HWRSVD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf, \ + 24) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_RXMAGPKT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 24) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3f, \ + 18) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_LAST_MSDU(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 17) + +#endif + +#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_RX_STATISTICS(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 17) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_RX_IS_QOS(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 16) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_PPDU_CNT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x3, 29) +#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \ + 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define GET_RX_DESC_C2H(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 28) -#define GET_RX_DESC_HWRSVD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xf, 24) -#define GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x3f, 18) -#define GET_RX_DESC_RX_IS_QOS(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 16) -#define GET_RX_DESC_FRAG(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xf, 12) -#define GET_RX_DESC_SEQ(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xfff, 0) +#define GET_RX_DESC_FRAG(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf, \ + 12) +#define GET_RX_DESC_SEQ(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, \ + 0xfff, 0) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 31) -#define GET_RX_DESC_UNICAST_WAKE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 30) -#define GET_RX_DESC_PATTERN_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 29) +#define GET_RX_DESC_MAGIC_WAKE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 31) +#define GET_RX_DESC_UNICAST_WAKE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 30) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 28) -#define GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0xf, 24) +#define GET_RX_DESC_PATTERN_MATCH(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 29) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0xff, 16) -#define GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x3, 12) -#define GET_RX_DESC_EOSP(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 11) -#define GET_RX_DESC_HTC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 10) +#define GET_RX_DESC_PATTERN_WAKE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 29) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x7, 7) +#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 28) +#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xf, \ + 24) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xff, \ + 16) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x3, \ + 12) +#define GET_RX_DESC_EOSP(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 11) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1f, \ + 11) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_HTC(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \ + 10) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_AMPDU_END_PKT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 9) +#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 8) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7, 7) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_EOSP_V1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 7) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_RX_RATE(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7f, \ + 0) -#define GET_RX_DESC_RX_RATE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x7f, 0) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1f, 24) +#define GET_RX_DESC_A1_FIT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \ + 24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_ADDRESS_CAM(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \ + 24) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_A1_FIT_A1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \ + 24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_MACID_VLD_V1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \ + 23) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \ + 17) +#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \ + 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x7f, 17) -#define GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1, 16) -#define GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x7f, 9) -#define GET_RX_DESC_RX_EOF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1, 8) +#define GET_RX_DESC_MACID_V1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \ + 15) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define GET_RX_DESC_PATTERN_IDX(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0xff, 0) +#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \ + 9) +#define GET_RX_DESC_RX_EOF(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_FC_POWER(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 7) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 6) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_SWPS_RPT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 5) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \ + 0) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \ + 0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \ + 0) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword5, 0xffffffff, 0) +#define GET_RX_DESC_TSFL(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5, \ + 0xffffffff, 0) #endif +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_FREERUN_CNT(rxdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5, \ + 0xffffffff, 0) #endif +#endif diff --git a/hal/halmac/halmac_rx_desc_chip.h b/hal/halmac/halmac_rx_desc_chip.h index 860eb88..7c8db73 100644 --- a/hal/halmac/halmac_rx_desc_chip.h +++ b/hal/halmac/halmac_rx_desc_chip.h @@ -1,76 +1,98 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_RX_DESC_CHIP_H_ #define _HALMAC_RX_DESC_CHIP_H_ #if (HALMAC_8814A_SUPPORT) /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR_8814A(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc) -#define GET_RX_DESC_PHYPKTIDC_8814A(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc) -#define GET_RX_DESC_SWDEC_8814A(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc) -#define GET_RX_DESC_PHYST_8814A(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc) -#define GET_RX_DESC_SHIFT_8814A(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc) -#define GET_RX_DESC_QOS_8814A(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc) -#define GET_RX_DESC_SECURITY_8814A(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc) -#define GET_RX_DESC_DRV_INFO_SIZE_8814A(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) -#define GET_RX_DESC_ICV_ERR_8814A(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc) -#define GET_RX_DESC_CRC32_8814A(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc) -#define GET_RX_DESC_PKT_LEN_8814A(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc) +#define GET_RX_DESC_EOR_8814A(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8814A(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8814A(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8814A(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8814A(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8814A(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8814A(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8814A(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8814A(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8814A(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8814A(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC_8814A(__pRxDesc) GET_RX_DESC_BC(__pRxDesc) -#define GET_RX_DESC_MC_8814A(__pRxDesc) GET_RX_DESC_MC(__pRxDesc) -#define GET_RX_DESC_TY_PE_8814A(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc) -#define GET_RX_DESC_MF_8814A(__pRxDesc) GET_RX_DESC_MF(__pRxDesc) -#define GET_RX_DESC_MD_8814A(__pRxDesc) GET_RX_DESC_MD(__pRxDesc) -#define GET_RX_DESC_PWR_8814A(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc) -#define GET_RX_DESC_PAM_8814A(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc) -#define GET_RX_DESC_CHK_VLD_8814A(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc) -#define GET_RX_DESC_RX_IS_TCP_UDP_8814A(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) -#define GET_RX_DESC_RX_IPV_8814A(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc) -#define GET_RX_DESC_CHKERR_8814A(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc) -#define GET_RX_DESC_PAGGR_8814A(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc) -#define GET_RX_DESC_RXID_MATCH_8814A(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc) -#define GET_RX_DESC_AMSDU_8814A(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc) -#define GET_RX_DESC_MACID_VLD_8814A(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc) -#define GET_RX_DESC_TID_8814A(__pRxDesc) GET_RX_DESC_TID(__pRxDesc) -#define GET_RX_DESC_EXT_SECTYPE_8814A(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc) -#define GET_RX_DESC_MACID_8814A(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc) +#define GET_RX_DESC_BC_8814A(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8814A(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8814A(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8814A(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8814A(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8814A(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8814A(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8814A(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8814A(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8814A(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8814A(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8814A(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8814A(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8814A(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8814A(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8814A(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8814A(rxdesc) GET_RX_DESC_MACID(rxdesc) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK_8814A(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) -#define GET_RX_DESC_C2H_8814A(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) -#define GET_RX_DESC_HWRSVD_8814A(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) -#define GET_RX_DESC_WLANHD_IV_LEN_8814A(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) -#define GET_RX_DESC_RX_IS_QOS_8814A(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc) -#define GET_RX_DESC_FRAG_8814A(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc) -#define GET_RX_DESC_SEQ_8814A(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc) +#define GET_RX_DESC_FCS_OK_8814A(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_C2H_8814A(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8814A(rxdesc) GET_RX_DESC_HWRSVD(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8814A(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8814A(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8814A(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8814A(rxdesc) GET_RX_DESC_SEQ(rxdesc) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE_8814A(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) -#define GET_RX_DESC_UNICAST_WAKE_8814A(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) -#define GET_RX_DESC_PATTERN_MATCH_8814A(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) -#define GET_RX_DESC_DMA_AGG_NUM_8814A(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_1_0_8814A(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) -#define GET_RX_DESC_EOSP_8814A(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) -#define GET_RX_DESC_HTC_8814A(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_4_2_8814A(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) -#define GET_RX_DESC_RX_RATE_8814A(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc) +#define GET_RX_DESC_MAGIC_WAKE_8814A(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8814A(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8814A(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8814A(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8814A(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8814A(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8814A(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8814A(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8814A(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT_8814A(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc) -#define GET_RX_DESC_MACID_RPT_BUFF_8814A(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) -#define GET_RX_DESC_RX_PRE_NDP_VLD_8814A(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) -#define GET_RX_DESC_RX_SCRAMBLER_8814A(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) -#define GET_RX_DESC_RX_EOF_8814A(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc) -#define GET_RX_DESC_PATTERN_IDX_8814A(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc) +#define GET_RX_DESC_A1_FIT_8814A(rxdesc) GET_RX_DESC_A1_FIT(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8814A(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8814A(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8814A(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8814A(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8814A(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL_8814A(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc) +#define GET_RX_DESC_TSFL_8814A(rxdesc) GET_RX_DESC_TSFL(rxdesc) #endif @@ -78,76 +100,84 @@ /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR_8822B(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc) -#define GET_RX_DESC_PHYPKTIDC_8822B(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc) -#define GET_RX_DESC_SWDEC_8822B(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc) -#define GET_RX_DESC_PHYST_8822B(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc) -#define GET_RX_DESC_SHIFT_8822B(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc) -#define GET_RX_DESC_QOS_8822B(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc) -#define GET_RX_DESC_SECURITY_8822B(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc) -#define GET_RX_DESC_DRV_INFO_SIZE_8822B(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) -#define GET_RX_DESC_ICV_ERR_8822B(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc) -#define GET_RX_DESC_CRC32_8822B(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc) -#define GET_RX_DESC_PKT_LEN_8822B(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc) +#define GET_RX_DESC_EOR_8822B(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8822B(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8822B(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8822B(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8822B(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8822B(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8822B(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8822B(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8822B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8822B(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8822B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC_8822B(__pRxDesc) GET_RX_DESC_BC(__pRxDesc) -#define GET_RX_DESC_MC_8822B(__pRxDesc) GET_RX_DESC_MC(__pRxDesc) -#define GET_RX_DESC_TY_PE_8822B(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc) -#define GET_RX_DESC_MF_8822B(__pRxDesc) GET_RX_DESC_MF(__pRxDesc) -#define GET_RX_DESC_MD_8822B(__pRxDesc) GET_RX_DESC_MD(__pRxDesc) -#define GET_RX_DESC_PWR_8822B(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc) -#define GET_RX_DESC_PAM_8822B(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc) -#define GET_RX_DESC_CHK_VLD_8822B(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc) -#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) -#define GET_RX_DESC_RX_IPV_8822B(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc) -#define GET_RX_DESC_CHKERR_8822B(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc) -#define GET_RX_DESC_PAGGR_8822B(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc) -#define GET_RX_DESC_RXID_MATCH_8822B(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc) -#define GET_RX_DESC_AMSDU_8822B(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc) -#define GET_RX_DESC_MACID_VLD_8822B(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc) -#define GET_RX_DESC_TID_8822B(__pRxDesc) GET_RX_DESC_TID(__pRxDesc) -#define GET_RX_DESC_EXT_SECTYPE_8822B(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc) -#define GET_RX_DESC_MACID_8822B(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc) +#define GET_RX_DESC_BC_8822B(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8822B(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8822B(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8822B(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8822B(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8822B(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8822B(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8822B(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8822B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8822B(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8822B(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8822B(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8822B(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8822B(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8822B(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8822B(rxdesc) GET_RX_DESC_MACID(rxdesc) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK_8822B(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) -#define GET_RX_DESC_PPDU_CNT_8822B(__pRxDesc) GET_RX_DESC_PPDU_CNT(__pRxDesc) -#define GET_RX_DESC_C2H_8822B(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) -#define GET_RX_DESC_HWRSVD_8822B(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) -#define GET_RX_DESC_WLANHD_IV_LEN_8822B(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) -#define GET_RX_DESC_RX_IS_QOS_8822B(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc) -#define GET_RX_DESC_FRAG_8822B(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc) -#define GET_RX_DESC_SEQ_8822B(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc) +#define GET_RX_DESC_FCS_OK_8822B(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_PPDU_CNT_8822B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc) +#define GET_RX_DESC_C2H_8822B(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8822B(rxdesc) GET_RX_DESC_HWRSVD(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8822B(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8822B(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8822B(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8822B(rxdesc) GET_RX_DESC_SEQ(rxdesc) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE_8822B(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) -#define GET_RX_DESC_UNICAST_WAKE_8822B(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) -#define GET_RX_DESC_PATTERN_MATCH_8822B(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) -#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(__pRxDesc) GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) -#define GET_RX_DESC_RXPAYLOAD_ID_8822B(__pRxDesc) GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) -#define GET_RX_DESC_DMA_AGG_NUM_8822B(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_1_0_8822B(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) -#define GET_RX_DESC_EOSP_8822B(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) -#define GET_RX_DESC_HTC_8822B(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_4_2_8822B(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) -#define GET_RX_DESC_RX_RATE_8822B(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc) +#define GET_RX_DESC_MAGIC_WAKE_8822B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8822B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8822B(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(rxdesc) \ + GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8822B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8822B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8822B(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8822B(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8822B(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8822B(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8822B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT_8822B(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc) -#define GET_RX_DESC_MACID_RPT_BUFF_8822B(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) -#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) -#define GET_RX_DESC_RX_SCRAMBLER_8822B(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) -#define GET_RX_DESC_RX_EOF_8822B(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc) -#define GET_RX_DESC_PATTERN_IDX_8822B(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc) +#define GET_RX_DESC_A1_FIT_8822B(rxdesc) GET_RX_DESC_A1_FIT(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8822B(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8822B(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8822B(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8822B(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL_8822B(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc) +#define GET_RX_DESC_TSFL_8822B(rxdesc) GET_RX_DESC_TSFL(rxdesc) #endif @@ -155,73 +185,81 @@ /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR_8197F(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc) -#define GET_RX_DESC_PHYPKTIDC_8197F(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc) -#define GET_RX_DESC_SWDEC_8197F(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc) -#define GET_RX_DESC_PHYST_8197F(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc) -#define GET_RX_DESC_SHIFT_8197F(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc) -#define GET_RX_DESC_QOS_8197F(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc) -#define GET_RX_DESC_SECURITY_8197F(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc) -#define GET_RX_DESC_DRV_INFO_SIZE_8197F(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) -#define GET_RX_DESC_ICV_ERR_8197F(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc) -#define GET_RX_DESC_CRC32_8197F(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc) -#define GET_RX_DESC_PKT_LEN_8197F(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc) +#define GET_RX_DESC_EOR_8197F(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8197F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8197F(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8197F(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8197F(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8197F(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8197F(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8197F(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8197F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8197F(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8197F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC_8197F(__pRxDesc) GET_RX_DESC_BC(__pRxDesc) -#define GET_RX_DESC_MC_8197F(__pRxDesc) GET_RX_DESC_MC(__pRxDesc) -#define GET_RX_DESC_TY_PE_8197F(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc) -#define GET_RX_DESC_MF_8197F(__pRxDesc) GET_RX_DESC_MF(__pRxDesc) -#define GET_RX_DESC_MD_8197F(__pRxDesc) GET_RX_DESC_MD(__pRxDesc) -#define GET_RX_DESC_PWR_8197F(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc) -#define GET_RX_DESC_PAM_8197F(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc) -#define GET_RX_DESC_CHK_VLD_8197F(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc) -#define GET_RX_DESC_RX_IS_TCP_UDP_8197F(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) -#define GET_RX_DESC_RX_IPV_8197F(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc) -#define GET_RX_DESC_CHKERR_8197F(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc) -#define GET_RX_DESC_PAGGR_8197F(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc) -#define GET_RX_DESC_RXID_MATCH_8197F(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc) -#define GET_RX_DESC_AMSDU_8197F(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc) -#define GET_RX_DESC_MACID_VLD_8197F(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc) -#define GET_RX_DESC_TID_8197F(__pRxDesc) GET_RX_DESC_TID(__pRxDesc) -#define GET_RX_DESC_EXT_SECTYPE_8197F(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc) -#define GET_RX_DESC_MACID_8197F(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc) +#define GET_RX_DESC_BC_8197F(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8197F(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8197F(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8197F(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8197F(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8197F(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8197F(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8197F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8197F(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8197F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8197F(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8197F(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8197F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8197F(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8197F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8197F(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8197F(rxdesc) GET_RX_DESC_MACID(rxdesc) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK_8197F(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) -#define GET_RX_DESC_C2H_8197F(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) -#define GET_RX_DESC_HWRSVD_8197F(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) -#define GET_RX_DESC_WLANHD_IV_LEN_8197F(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) -#define GET_RX_DESC_RX_IS_QOS_8197F(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc) -#define GET_RX_DESC_FRAG_8197F(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc) -#define GET_RX_DESC_SEQ_8197F(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc) +#define GET_RX_DESC_FCS_OK_8197F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_C2H_8197F(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8197F(rxdesc) GET_RX_DESC_HWRSVD(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8197F(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8197F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8197F(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8197F(rxdesc) GET_RX_DESC_SEQ(rxdesc) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE_8197F(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) -#define GET_RX_DESC_UNICAST_WAKE_8197F(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) -#define GET_RX_DESC_PATTERN_MATCH_8197F(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) -#define GET_RX_DESC_DMA_AGG_NUM_8197F(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_1_0_8197F(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) -#define GET_RX_DESC_EOSP_8197F(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) -#define GET_RX_DESC_HTC_8197F(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_4_2_8197F(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) -#define GET_RX_DESC_RX_RATE_8197F(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc) +#define GET_RX_DESC_MAGIC_WAKE_8197F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8197F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8197F(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8197F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8197F(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8197F(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8197F(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8197F(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8197F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT_8197F(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc) -#define GET_RX_DESC_MACID_RPT_BUFF_8197F(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) -#define GET_RX_DESC_RX_PRE_NDP_VLD_8197F(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) -#define GET_RX_DESC_RX_SCRAMBLER_8197F(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) -#define GET_RX_DESC_RX_EOF_8197F(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc) -#define GET_RX_DESC_PATTERN_IDX_8197F(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc) +#define GET_RX_DESC_A1_FIT_8197F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8197F(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8197F(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8197F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8197F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_FC_POWER_8197F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8197F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL_8197F(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc) +#define GET_RX_DESC_TSFL_8197F(rxdesc) GET_RX_DESC_TSFL(rxdesc) #endif @@ -229,147 +267,432 @@ /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR_8821C(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc) -#define GET_RX_DESC_PHYPKTIDC_8821C(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc) -#define GET_RX_DESC_SWDEC_8821C(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc) -#define GET_RX_DESC_PHYST_8821C(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc) -#define GET_RX_DESC_SHIFT_8821C(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc) -#define GET_RX_DESC_QOS_8821C(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc) -#define GET_RX_DESC_SECURITY_8821C(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc) -#define GET_RX_DESC_DRV_INFO_SIZE_8821C(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) -#define GET_RX_DESC_ICV_ERR_8821C(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc) -#define GET_RX_DESC_CRC32_8821C(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc) -#define GET_RX_DESC_PKT_LEN_8821C(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc) +#define GET_RX_DESC_EOR_8821C(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8821C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8821C(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8821C(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8821C(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8821C(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8821C(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8821C(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8821C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8821C(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8821C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) + +/*RXDESC_WORD1*/ + +#define GET_RX_DESC_BC_8821C(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8821C(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8821C(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8821C(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8821C(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8821C(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8821C(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8821C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8821C(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8821C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8821C(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8821C(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8821C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8821C(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8821C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8821C(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8821C(rxdesc) GET_RX_DESC_MACID(rxdesc) + +/*RXDESC_WORD2*/ + +#define GET_RX_DESC_FCS_OK_8821C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_PPDU_CNT_8821C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc) +#define GET_RX_DESC_C2H_8821C(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8821C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8821C(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8821C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8821C(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8821C(rxdesc) GET_RX_DESC_SEQ(rxdesc) + +/*RXDESC_WORD3*/ + +#define GET_RX_DESC_MAGIC_WAKE_8821C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8821C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8821C(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8821C(rxdesc) \ + GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8821C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8821C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8821C(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8821C(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8821C(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8821C(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8821C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) + +/*RXDESC_WORD4*/ + +#define GET_RX_DESC_A1_FIT_8821C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8821C(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8821C(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8821C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8821C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8821C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc) + +/*RXDESC_WORD5*/ + +#define GET_RX_DESC_TSFL_8821C(rxdesc) GET_RX_DESC_TSFL(rxdesc) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +/*RXDESC_WORD0*/ + +#define GET_RX_DESC_EVT_PKT_8814B(rxdesc) GET_RX_DESC_EVT_PKT(rxdesc) +#define GET_RX_DESC_SWDEC_8814B(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8814B(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8814B(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8814B(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8814B(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8814B(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8814B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8814B(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8814B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) + +/*RXDESC_WORD1*/ + +#define GET_RX_DESC_BC_8814B(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8814B(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TYPE_8814B(rxdesc) GET_RX_DESC_TYPE(rxdesc) +#define GET_RX_DESC_MF_8814B(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8814B(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8814B(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_A1_MATCH_8814B(rxdesc) GET_RX_DESC_A1_MATCH(rxdesc) +#define GET_RX_DESC_TCP_CHKSUM_VLD_8814B(rxdesc) \ + GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8814B(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8814B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_TCP_CHKSUM_ERR_8814B(rxdesc) \ + GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc) +#define GET_RX_DESC_PHY_PKT_IDC_8814B(rxdesc) GET_RX_DESC_PHY_PKT_IDC(rxdesc) +#define GET_RX_DESC_FW_FIFO_FULL_8814B(rxdesc) GET_RX_DESC_FW_FIFO_FULL(rxdesc) +#define GET_RX_DESC_AMPDU_8814B(rxdesc) GET_RX_DESC_AMPDU(rxdesc) +#define GET_RX_DESC_RXCMD_IDC_8814B(rxdesc) GET_RX_DESC_RXCMD_IDC(rxdesc) +#define GET_RX_DESC_AMSDU_8814B(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_TID_8814B(rxdesc) GET_RX_DESC_TID(rxdesc) + +/*RXDESC_WORD2*/ + +#define GET_RX_DESC_AMSDU_CUT_8814B(rxdesc) GET_RX_DESC_AMSDU_CUT(rxdesc) +#define GET_RX_DESC_PPDU_CNT_8814B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc) +#define GET_RX_DESC_C2H_8814B(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8814B(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_LAST_MSDU_8814B(rxdesc) GET_RX_DESC_LAST_MSDU(rxdesc) +#define GET_RX_DESC_EXT_SEC_TYPE_8814B(rxdesc) GET_RX_DESC_EXT_SEC_TYPE(rxdesc) +#define GET_RX_DESC_FRAG_8814B(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8814B(rxdesc) GET_RX_DESC_SEQ(rxdesc) + +/*RXDESC_WORD3*/ + +#define GET_RX_DESC_MAGIC_WAKE_8814B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8814B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_WAKE_8814B(rxdesc) GET_RX_DESC_PATTERN_WAKE(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8814B(rxdesc) \ + GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8814B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8814B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_8814B(rxdesc) GET_RX_DESC_BSSID_FIT(rxdesc) +#define GET_RX_DESC_HTC_8814B(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_AMPDU_END_PKT_8814B(rxdesc) \ + GET_RX_DESC_AMPDU_END_PKT(rxdesc) +#define GET_RX_DESC_ADDRESS_CAM_VLD_8814B(rxdesc) \ + GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc) +#define GET_RX_DESC_EOSP_8814B(rxdesc) GET_RX_DESC_EOSP_V1(rxdesc) +#define GET_RX_DESC_RX_RATE_8814B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) + +/*RXDESC_WORD4*/ + +#define GET_RX_DESC_ADDRESS_CAM_8814B(rxdesc) GET_RX_DESC_ADDRESS_CAM(rxdesc) +#define GET_RX_DESC_MACID_VLD_8814B(rxdesc) GET_RX_DESC_MACID_VLD_V1(rxdesc) +#define GET_RX_DESC_MACID_8814B(rxdesc) GET_RX_DESC_MACID_V1(rxdesc) +#define GET_RX_DESC_SWPS_RPT_8814B(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8814B(rxdesc) GET_RX_DESC_PATTERN_IDX_V2(rxdesc) + +/*RXDESC_WORD5*/ + +#define GET_RX_DESC_FREERUN_CNT_8814B(rxdesc) GET_RX_DESC_FREERUN_CNT(rxdesc) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/*RXDESC_WORD0*/ + +#define GET_RX_DESC_EOR_8198F(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8198F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8198F(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8198F(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8198F(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8198F(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8198F(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8198F(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8198F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8198F(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8198F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC_8821C(__pRxDesc) GET_RX_DESC_BC(__pRxDesc) -#define GET_RX_DESC_MC_8821C(__pRxDesc) GET_RX_DESC_MC(__pRxDesc) -#define GET_RX_DESC_TY_PE_8821C(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc) -#define GET_RX_DESC_MF_8821C(__pRxDesc) GET_RX_DESC_MF(__pRxDesc) -#define GET_RX_DESC_MD_8821C(__pRxDesc) GET_RX_DESC_MD(__pRxDesc) -#define GET_RX_DESC_PWR_8821C(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc) -#define GET_RX_DESC_PAM_8821C(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc) -#define GET_RX_DESC_CHK_VLD_8821C(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc) -#define GET_RX_DESC_RX_IS_TCP_UDP_8821C(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) -#define GET_RX_DESC_RX_IPV_8821C(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc) -#define GET_RX_DESC_CHKERR_8821C(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc) -#define GET_RX_DESC_PAGGR_8821C(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc) -#define GET_RX_DESC_RXID_MATCH_8821C(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc) -#define GET_RX_DESC_AMSDU_8821C(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc) -#define GET_RX_DESC_MACID_VLD_8821C(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc) -#define GET_RX_DESC_TID_8821C(__pRxDesc) GET_RX_DESC_TID(__pRxDesc) -#define GET_RX_DESC_EXT_SECTYPE_8821C(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc) -#define GET_RX_DESC_MACID_8821C(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc) +#define GET_RX_DESC_BC_8198F(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8198F(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8198F(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8198F(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8198F(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8198F(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8198F(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8198F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8198F(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8198F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8198F(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8198F(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8198F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8198F(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8198F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8198F(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8198F(rxdesc) GET_RX_DESC_MACID(rxdesc) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK_8821C(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) -#define GET_RX_DESC_PPDU_CNT_8821C(__pRxDesc) GET_RX_DESC_PPDU_CNT(__pRxDesc) -#define GET_RX_DESC_C2H_8821C(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) -#define GET_RX_DESC_HWRSVD_8821C(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) -#define GET_RX_DESC_WLANHD_IV_LEN_8821C(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) -#define GET_RX_DESC_RX_IS_QOS_8821C(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc) -#define GET_RX_DESC_FRAG_8821C(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc) -#define GET_RX_DESC_SEQ_8821C(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc) +#define GET_RX_DESC_FCS_OK_8198F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_PPDU_CNT_8198F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc) +#define GET_RX_DESC_C2H_8198F(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8198F(rxdesc) GET_RX_DESC_HWRSVD_V1(rxdesc) +#define GET_RX_DESC_RXMAGPKT_8198F(rxdesc) GET_RX_DESC_RXMAGPKT(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8198F(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8198F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8198F(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8198F(rxdesc) GET_RX_DESC_SEQ(rxdesc) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE_8821C(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) -#define GET_RX_DESC_UNICAST_WAKE_8821C(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) -#define GET_RX_DESC_PATTERN_MATCH_8821C(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) -#define GET_RX_DESC_RXPAYLOAD_MATCH_8821C(__pRxDesc) GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) -#define GET_RX_DESC_RXPAYLOAD_ID_8821C(__pRxDesc) GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) -#define GET_RX_DESC_DMA_AGG_NUM_8821C(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_1_0_8821C(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) -#define GET_RX_DESC_EOSP_8821C(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) -#define GET_RX_DESC_HTC_8821C(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_4_2_8821C(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) -#define GET_RX_DESC_RX_RATE_8821C(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc) +#define GET_RX_DESC_MAGIC_WAKE_8198F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8198F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8198F(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8198F(rxdesc) \ + GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8198F(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8198F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8198F(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8198F(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8198F(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8198F(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8198F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT_8821C(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc) -#define GET_RX_DESC_MACID_RPT_BUFF_8821C(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) -#define GET_RX_DESC_RX_PRE_NDP_VLD_8821C(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) -#define GET_RX_DESC_RX_SCRAMBLER_8821C(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) -#define GET_RX_DESC_RX_EOF_8821C(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc) -#define GET_RX_DESC_PATTERN_IDX_8821C(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc) +#define GET_RX_DESC_A1_FIT_A1_8198F(rxdesc) GET_RX_DESC_A1_FIT_A1(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8198F(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8198F(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8198F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8198F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_FC_POWER_8198F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc) +#define GET_RX_DESC_TXRPTMID_CTL_MASK_8198F(rxdesc) \ + GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc) +#define GET_RX_DESC_SWPS_RPT_8198F(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8198F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL_8821C(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc) +#define GET_RX_DESC_TSFL_8198F(rxdesc) GET_RX_DESC_TSFL(rxdesc) #endif -#if (HALMAC_8188F_SUPPORT) +#if (HALMAC_8822C_SUPPORT) /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR_8188F(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc) -#define GET_RX_DESC_PHYPKTIDC_8188F(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc) -#define GET_RX_DESC_SWDEC_8188F(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc) -#define GET_RX_DESC_PHYST_8188F(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc) -#define GET_RX_DESC_SHIFT_8188F(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc) -#define GET_RX_DESC_QOS_8188F(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc) -#define GET_RX_DESC_SECURITY_8188F(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc) -#define GET_RX_DESC_DRV_INFO_SIZE_8188F(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) -#define GET_RX_DESC_ICV_ERR_8188F(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc) -#define GET_RX_DESC_CRC32_8188F(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc) -#define GET_RX_DESC_PKT_LEN_8188F(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc) +#define GET_RX_DESC_EOR_8822C(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8822C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8822C(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8822C(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8822C(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8822C(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8822C(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8822C(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8822C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8822C(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8822C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC_8188F(__pRxDesc) GET_RX_DESC_BC(__pRxDesc) -#define GET_RX_DESC_MC_8188F(__pRxDesc) GET_RX_DESC_MC(__pRxDesc) -#define GET_RX_DESC_TY_PE_8188F(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc) -#define GET_RX_DESC_MF_8188F(__pRxDesc) GET_RX_DESC_MF(__pRxDesc) -#define GET_RX_DESC_MD_8188F(__pRxDesc) GET_RX_DESC_MD(__pRxDesc) -#define GET_RX_DESC_PWR_8188F(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc) -#define GET_RX_DESC_PAM_8188F(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc) -#define GET_RX_DESC_CHK_VLD_8188F(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc) -#define GET_RX_DESC_RX_IS_TCP_UDP_8188F(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) -#define GET_RX_DESC_RX_IPV_8188F(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc) -#define GET_RX_DESC_CHKERR_8188F(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc) -#define GET_RX_DESC_PAGGR_8188F(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc) -#define GET_RX_DESC_RXID_MATCH_8188F(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc) -#define GET_RX_DESC_AMSDU_8188F(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc) -#define GET_RX_DESC_MACID_VLD_8188F(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc) -#define GET_RX_DESC_TID_8188F(__pRxDesc) GET_RX_DESC_TID(__pRxDesc) -#define GET_RX_DESC_MACID_8188F(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc) +#define GET_RX_DESC_BC_8822C(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8822C(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8822C(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8822C(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8822C(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8822C(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8822C(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8822C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8822C(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8822C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8822C(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8822C(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8822C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8822C(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8822C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8822C(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8822C(rxdesc) GET_RX_DESC_MACID(rxdesc) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK_8188F(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) -#define GET_RX_DESC_C2H_8188F(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) -#define GET_RX_DESC_HWRSVD_8188F(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) -#define GET_RX_DESC_WLANHD_IV_LEN_8188F(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) -#define GET_RX_DESC_RX_IS_QOS_8188F(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc) -#define GET_RX_DESC_FRAG_8188F(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc) -#define GET_RX_DESC_SEQ_8188F(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc) +#define GET_RX_DESC_FCS_OK_8822C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_PPDU_CNT_8822C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc) +#define GET_RX_DESC_C2H_8822C(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8822C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8822C(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_STATISTICS_8822C(rxdesc) \ + GET_RX_DESC_RX_STATISTICS(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8822C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8822C(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8822C(rxdesc) GET_RX_DESC_SEQ(rxdesc) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE_8188F(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) -#define GET_RX_DESC_UNICAST_WAKE_8188F(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) -#define GET_RX_DESC_PATTERN_MATCH_8188F(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) -#define GET_RX_DESC_DMA_AGG_NUM_8188F(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) -#define GET_RX_DESC_BSSID_FIT_1_0_8188F(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) -#define GET_RX_DESC_EOSP_8188F(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) -#define GET_RX_DESC_HTC_8188F(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc) -#define GET_RX_DESC_RX_RATE_8188F(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc) +#define GET_RX_DESC_MAGIC_WAKE_8822C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8822C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8822C(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8822C(rxdesc) \ + GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8822C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8822C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8822C(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8822C(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8822C(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8822C(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8822C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT_8188F(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc) -#define GET_RX_DESC_PATTERN_IDX_8188F(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc) +#define GET_RX_DESC_A1_FIT_8822C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8822C(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8822C(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8822C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8822C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8822C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL_8188F(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc) +#define GET_RX_DESC_TSFL_8822C(rxdesc) GET_RX_DESC_TSFL(rxdesc) #endif +#if (HALMAC_8812F_SUPPORT) + +/*RXDESC_WORD0*/ + +#define GET_RX_DESC_EOR_8812F(rxdesc) GET_RX_DESC_EOR(rxdesc) +#define GET_RX_DESC_PHYPKTIDC_8812F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc) +#define GET_RX_DESC_SWDEC_8812F(rxdesc) GET_RX_DESC_SWDEC(rxdesc) +#define GET_RX_DESC_PHYST_8812F(rxdesc) GET_RX_DESC_PHYST(rxdesc) +#define GET_RX_DESC_SHIFT_8812F(rxdesc) GET_RX_DESC_SHIFT(rxdesc) +#define GET_RX_DESC_QOS_8812F(rxdesc) GET_RX_DESC_QOS(rxdesc) +#define GET_RX_DESC_SECURITY_8812F(rxdesc) GET_RX_DESC_SECURITY(rxdesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8812F(rxdesc) \ + GET_RX_DESC_DRV_INFO_SIZE(rxdesc) +#define GET_RX_DESC_ICV_ERR_8812F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc) +#define GET_RX_DESC_CRC32_8812F(rxdesc) GET_RX_DESC_CRC32(rxdesc) +#define GET_RX_DESC_PKT_LEN_8812F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc) + +/*RXDESC_WORD1*/ + +#define GET_RX_DESC_BC_8812F(rxdesc) GET_RX_DESC_BC(rxdesc) +#define GET_RX_DESC_MC_8812F(rxdesc) GET_RX_DESC_MC(rxdesc) +#define GET_RX_DESC_TY_PE_8812F(rxdesc) GET_RX_DESC_TY_PE(rxdesc) +#define GET_RX_DESC_MF_8812F(rxdesc) GET_RX_DESC_MF(rxdesc) +#define GET_RX_DESC_MD_8812F(rxdesc) GET_RX_DESC_MD(rxdesc) +#define GET_RX_DESC_PWR_8812F(rxdesc) GET_RX_DESC_PWR(rxdesc) +#define GET_RX_DESC_PAM_8812F(rxdesc) GET_RX_DESC_PAM(rxdesc) +#define GET_RX_DESC_CHK_VLD_8812F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8812F(rxdesc) \ + GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) +#define GET_RX_DESC_RX_IPV_8812F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc) +#define GET_RX_DESC_CHKERR_8812F(rxdesc) GET_RX_DESC_CHKERR(rxdesc) +#define GET_RX_DESC_PAGGR_8812F(rxdesc) GET_RX_DESC_PAGGR(rxdesc) +#define GET_RX_DESC_RXID_MATCH_8812F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc) +#define GET_RX_DESC_AMSDU_8812F(rxdesc) GET_RX_DESC_AMSDU(rxdesc) +#define GET_RX_DESC_MACID_VLD_8812F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc) +#define GET_RX_DESC_TID_8812F(rxdesc) GET_RX_DESC_TID(rxdesc) +#define GET_RX_DESC_MACID_8812F(rxdesc) GET_RX_DESC_MACID(rxdesc) + +/*RXDESC_WORD2*/ + +#define GET_RX_DESC_FCS_OK_8812F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc) +#define GET_RX_DESC_PPDU_CNT_8812F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc) +#define GET_RX_DESC_C2H_8812F(rxdesc) GET_RX_DESC_C2H(rxdesc) +#define GET_RX_DESC_HWRSVD_8812F(rxdesc) GET_RX_DESC_HWRSVD(rxdesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8812F(rxdesc) \ + GET_RX_DESC_WLANHD_IV_LEN(rxdesc) +#define GET_RX_DESC_RX_STATISTICS_8812F(rxdesc) \ + GET_RX_DESC_RX_STATISTICS(rxdesc) +#define GET_RX_DESC_RX_IS_QOS_8812F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc) +#define GET_RX_DESC_FRAG_8812F(rxdesc) GET_RX_DESC_FRAG(rxdesc) +#define GET_RX_DESC_SEQ_8812F(rxdesc) GET_RX_DESC_SEQ(rxdesc) + +/*RXDESC_WORD3*/ + +#define GET_RX_DESC_MAGIC_WAKE_8812F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc) +#define GET_RX_DESC_UNICAST_WAKE_8812F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc) +#define GET_RX_DESC_PATTERN_MATCH_8812F(rxdesc) \ + GET_RX_DESC_PATTERN_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8812F(rxdesc) \ + GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8812F(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc) +#define GET_RX_DESC_DMA_AGG_NUM_8812F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8812F(rxdesc) \ + GET_RX_DESC_BSSID_FIT_1_0(rxdesc) +#define GET_RX_DESC_EOSP_8812F(rxdesc) GET_RX_DESC_EOSP(rxdesc) +#define GET_RX_DESC_HTC_8812F(rxdesc) GET_RX_DESC_HTC(rxdesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8812F(rxdesc) \ + GET_RX_DESC_BSSID_FIT_4_2(rxdesc) +#define GET_RX_DESC_RX_RATE_8812F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc) + +/*RXDESC_WORD4*/ + +#define GET_RX_DESC_A1_FIT_8812F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8812F(rxdesc) \ + GET_RX_DESC_MACID_RPT_BUFF(rxdesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8812F(rxdesc) \ + GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) +#define GET_RX_DESC_RX_SCRAMBLER_8812F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc) +#define GET_RX_DESC_RX_EOF_8812F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc) +#define GET_RX_DESC_PATTERN_IDX_8812F(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc) + +/*RXDESC_WORD5*/ + +#define GET_RX_DESC_TSFL_8812F(rxdesc) GET_RX_DESC_TSFL(rxdesc) #endif +#endif diff --git a/hal/halmac/halmac_rx_desc_nic.h b/hal/halmac/halmac_rx_desc_nic.h index 50231fd..2d4f82a 100644 --- a/hal/halmac/halmac_rx_desc_nic.h +++ b/hal/halmac/halmac_rx_desc_nic.h @@ -1,132 +1,478 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_RX_DESC_NIC_H_ #define _HALMAC_RX_DESC_NIC_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) /*RXDESC_WORD0*/ -#define GET_RX_DESC_EOR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 30, 1) -#define GET_RX_DESC_PHYPKTIDC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 28, 1) -#define GET_RX_DESC_SWDEC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 27, 1) -#define GET_RX_DESC_PHYST(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 26, 1) -#define GET_RX_DESC_SHIFT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 24, 2) -#define GET_RX_DESC_QOS(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 23, 1) -#define GET_RX_DESC_SECURITY(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 20, 3) -#define GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 16, 4) -#define GET_RX_DESC_ICV_ERR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 15, 1) -#define GET_RX_DESC_CRC32(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 14, 1) -#define GET_RX_DESC_PKT_LEN(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 0, 14) +#define GET_RX_DESC_EOR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 30, 1) +#define GET_RX_DESC_PHYPKTIDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_EVT_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_SWDEC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 27, 1) +#define GET_RX_DESC_PHYST(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 26, 1) +#define GET_RX_DESC_SHIFT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 24, 2) +#define GET_RX_DESC_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 23, 1) +#define GET_RX_DESC_SECURITY(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 20, 3) +#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 16, 4) +#define GET_RX_DESC_ICV_ERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 15, 1) +#define GET_RX_DESC_CRC32(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 14, 1) +#define GET_RX_DESC_PKT_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 0, 14) /*RXDESC_WORD1*/ -#define GET_RX_DESC_BC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 31, 1) -#define GET_RX_DESC_MC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 30, 1) -#define GET_RX_DESC_TY_PE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 28, 2) -#define GET_RX_DESC_MF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 27, 1) -#define GET_RX_DESC_MD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 26, 1) -#define GET_RX_DESC_PWR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 25, 1) -#define GET_RX_DESC_PAM(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 24, 1) -#define GET_RX_DESC_CHK_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 23, 1) -#define GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 22, 1) -#define GET_RX_DESC_RX_IPV(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 21, 1) -#define GET_RX_DESC_CHKERR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 20, 1) -#define GET_RX_DESC_PAGGR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 15, 1) -#define GET_RX_DESC_RXID_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 14, 1) -#define GET_RX_DESC_AMSDU(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 13, 1) -#define GET_RX_DESC_MACID_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 12, 1) -#define GET_RX_DESC_TID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 8, 4) +#define GET_RX_DESC_BC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 31, 1) +#define GET_RX_DESC_MC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 30, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_TY_PE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_MF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 27, 1) +#define GET_RX_DESC_MD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 26, 1) +#define GET_RX_DESC_PWR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 25, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_PAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_A1_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_CHK_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 22, 1) +#define GET_RX_DESC_RX_IPV(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 21, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_CHKERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_EXT_SECTYPE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 7, 1) +#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1) +#define GET_RX_DESC_PHY_PKT_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 17, 1) +#define GET_RX_DESC_FW_FIFO_FULL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 16, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_PAGGR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1) + +#endif -#define GET_RX_DESC_MACID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 0, 7) +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_AMPDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_RXID_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_RXCMD_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_AMSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 13, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_MACID_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 12, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_TID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 8, 4) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_MACID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 0, 7) /*RXDESC_WORD2*/ -#define GET_RX_DESC_FCS_OK(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 31, 1) +#define GET_RX_DESC_FCS_OK(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_AMSDU_CUT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_PPDU_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 29, 2) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define GET_RX_DESC_PPDU_CNT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 29, 2) +#define GET_RX_DESC_C2H(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 28, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_HWRSVD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 25, 3) + +#endif -#define GET_RX_DESC_C2H(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 28, 1) -#define GET_RX_DESC_HWRSVD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 24, 4) -#define GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 18, 6) -#define GET_RX_DESC_RX_IS_QOS(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 16, 1) -#define GET_RX_DESC_FRAG(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 12, 4) -#define GET_RX_DESC_SEQ(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 0, 12) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_HWRSVD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 4) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_RXMAGPKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 18, 6) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_LAST_MSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1) + +#endif + +#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_RX_STATISTICS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_RX_IS_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_FRAG(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 12, 4) +#define GET_RX_DESC_SEQ(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 0, 12) /*RXDESC_WORD3*/ -#define GET_RX_DESC_MAGIC_WAKE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 31, 1) -#define GET_RX_DESC_UNICAST_WAKE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 30, 1) -#define GET_RX_DESC_PATTERN_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 29, 1) +#define GET_RX_DESC_MAGIC_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 31, 1) +#define GET_RX_DESC_UNICAST_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 30, 1) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 28, 1) -#define GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 24, 4) +#define GET_RX_DESC_PATTERN_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 16, 8) -#define GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 12, 2) -#define GET_RX_DESC_EOSP(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 11, 1) -#define GET_RX_DESC_HTC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 10, 1) +#define GET_RX_DESC_PATTERN_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 7, 3) +#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x0C, 28, 1) +#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 24, 4) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 16, 8) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 12, 2) +#define GET_RX_DESC_EOSP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 5) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_HTC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 10, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_AMPDU_END_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 9, 1) +#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x0C, 8, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 3) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_EOSP_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_RX_RATE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 0, 7) -#define GET_RX_DESC_RX_RATE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 0, 7) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) /*RXDESC_WORD4*/ -#define GET_RX_DESC_A1_FIT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 24, 5) +#define GET_RX_DESC_A1_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 5) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_ADDRESS_CAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 8) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_A1_FIT_A1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 7) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_MACID_VLD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 23, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x10, 17, 7) +#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x10, 16, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 17, 7) -#define GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 16, 1) -#define GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 9, 7) -#define GET_RX_DESC_RX_EOF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 8, 1) +#define GET_RX_DESC_MACID_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 15, 8) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define GET_RX_DESC_PATTERN_IDX(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 0, 8) +#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 9, 7) +#define GET_RX_DESC_RX_EOF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 8, 1) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_FC_POWER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 7, 1) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc) \ + LE_BITS_TO_4BYTE(rxdesc + 0x10, 6, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_SWPS_RPT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 5, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 8) + +#endif + +#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) /*RXDESC_WORD5*/ -#define GET_RX_DESC_TSFL(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x14, 0, 32) +#define GET_RX_DESC_TSFL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32) #endif +#if (HALMAC_8814B_SUPPORT) + +#define GET_RX_DESC_FREERUN_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32) #endif +#endif diff --git a/hal/halmac/halmac_sdio_reg.h b/hal/halmac/halmac_sdio_reg.h index 09c131f..71f3de6 100644 --- a/hal/halmac/halmac_sdio_reg.h +++ b/hal/halmac/halmac_sdio_reg.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __HALMAC_SDIO_REG_H__ #define __HALMAC_SDIO_REG_H__ @@ -5,11 +20,11 @@ #define HALMAC_SDIO_4BYTE_LEN_MASK 0x1FFF #define HALMAC_SDIO_LOCAL_MSK 0x0FFF -#define HALMAC_WLAN_MAC_REG_MSK 0xFFFF -#define HALMAC_WLAN_IOREG_MSK 0xFFFF +#define HALMAC_WLAN_MAC_REG_MSK 0xFFFF +#define HALMAC_WLAN_IOREG_MSK 0xFFFF /* Sdio Address for SDIO Local Reg, TRX FIFO, MAC Reg */ -typedef enum { +enum halmac_sdio_cmd_addr { HALMAC_SDIO_CMD_ADDR_SDIO_REG = 0, HALMAC_SDIO_CMD_ADDR_MAC_REG = 8, HALMAC_SDIO_CMD_ADDR_TXFF_HIGH = 4, @@ -17,7 +32,7 @@ typedef enum { HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL = 5, HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA = 7, HALMAC_SDIO_CMD_ADDR_RXFF = 7, -} HALMAC_SDIO_CMD_ADDR; +}; /* IO Bus domain address mapping */ #define SDIO_LOCAL_OFFSET 0x10250000 @@ -31,8 +46,10 @@ typedef enum { /* Get TX WLAN FIFO information in CMD53 addr */ #if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT) -#define GET_WLAN_TXFF_DEVICE_ID(__pCmd53_addr) LE_BITS_TO_4BYTE((u32 *)__pCmd53_addr, 13, 4) -#define GET_WLAN_TXFF_PKT_SIZE(__pCmd53_addr) LE_BITS_TO_4BYTE((u32 *)__pCmd53_addr, 0, 13) << 2 +#define GET_WLAN_TXFF_DEVICE_ID(cmd53_addr) \ + LE_BITS_TO_4BYTE((u32 *)cmd53_addr, 13, 4) +#define GET_WLAN_TXFF_PKT_SIZE(cmd53_addr) \ + (LE_BITS_TO_4BYTE((u32 *)cmd53_addr, 0, 13) << 2) #endif #endif/* __HALMAC_SDIO_REG_H__ */ diff --git a/hal/halmac/halmac_state_machine.h b/hal/halmac/halmac_state_machine.h new file mode 100644 index 0000000..d6cce79 --- /dev/null +++ b/hal/halmac/halmac_state_machine.h @@ -0,0 +1,157 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_STATE_MACHINE_H_ +#define _HALMAC_STATE_MACHINE_H_ + +enum halmac_dlfw_state { + HALMAC_DLFW_NONE = 0, + HALMAC_DLFW_DONE = 1, + HALMAC_GEN_INFO_SENT = 2, + + /* Data CPU firmware download framework */ + HALMAC_DLFW_INIT = 0x11, + HALMAC_DLFW_START = 0x12, + HALMAC_DLFW_CONF_READY = 0x13, + HALMAC_DLFW_CPU_READY = 0x14, + HALMAC_DLFW_MEM_READY = 0x15, + HALMAC_DLFW_SW_READY = 0x16, + HALMAC_DLFW_OFLD_READY = 0x17, + + HALMAC_DLFW_UNDEFINED = 0x7F, +}; + +enum halmac_gpio_cfg_state { + HALMAC_GPIO_CFG_STATE_IDLE = 0, + HALMAC_GPIO_CFG_STATE_BUSY = 1, + HALMAC_GPIO_CFG_STATE_UNDEFINED = 0x7F, +}; + +enum halmac_rsvd_pg_state { + HALMAC_RSVD_PG_STATE_IDLE = 0, + HALMAC_RSVD_PG_STATE_BUSY = 1, + HALMAC_RSVD_PG_STATE_UNDEFINED = 0x7F, +}; + +enum halmac_api_state { + HALMAC_API_STATE_INIT = 0, + HALMAC_API_STATE_HALT = 1, + HALMAC_API_STATE_UNDEFINED = 0x7F, +}; + +enum halmac_cmd_construct_state { + HALMAC_CMD_CNSTR_IDLE = 0, + HALMAC_CMD_CNSTR_BUSY = 1, + HALMAC_CMD_CNSTR_H2C_SENT = 2, + HALMAC_CMD_CNSTR_CNSTR = 3, + HALMAC_CMD_CNSTR_BUF_CLR = 4, + HALMAC_CMD_CNSTR_UNDEFINED = 0x7F, +}; + +enum halmac_cmd_process_status { + HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */ + HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */ + HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */ + HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */ + HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */ + HALMAC_CMD_PROCESS_UNDEFINE = 0x7F, +}; + +enum halmac_mac_power { + HALMAC_MAC_POWER_OFF = 0x0, + HALMAC_MAC_POWER_ON = 0x1, + HALMAC_MAC_POWER_UNDEFINE = 0x7F, +}; + +enum halmac_wlcpu_mode { + HALMAC_WLCPU_ACTIVE = 0x0, + HALMAC_WLCPU_ENTER_SLEEP = 0x1, + HALMAC_WLCPU_SLEEP = 0x2, + HALMAC_WLCPU_UNDEFINE = 0x7F, +}; + +struct halmac_efuse_state { + enum halmac_cmd_construct_state cmd_cnstr_state; + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_cfg_param_state { + enum halmac_cmd_construct_state cmd_cnstr_state; + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_scan_state { + enum halmac_cmd_construct_state cmd_cnstr_state; + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_update_pkt_state { + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_iqk_state { + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_pwr_tracking_state { + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_psd_state { + enum halmac_cmd_process_status proc_status; + u16 data_size; + u16 seg_size; + u8 *data; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_fw_snding_state { + enum halmac_cmd_construct_state cmd_cnstr_state; + enum halmac_cmd_process_status proc_status; + u8 fw_rc; + u16 seq_num; +}; + +struct halmac_state { + struct halmac_efuse_state efuse_state; + struct halmac_cfg_param_state cfg_param_state; + struct halmac_scan_state scan_state; + struct halmac_update_pkt_state update_pkt_state; + struct halmac_iqk_state iqk_state; + struct halmac_pwr_tracking_state pwr_trk_state; + struct halmac_psd_state psd_state; + struct halmac_fw_snding_state fw_snding_state; + enum halmac_api_state api_state; + enum halmac_mac_power mac_pwr; + enum halmac_dlfw_state dlfw_state; + enum halmac_wlcpu_mode wlcpu_mode; + enum halmac_gpio_cfg_state gpio_cfg_state; + enum halmac_rsvd_pg_state rsvd_pg_state; +}; + +#endif diff --git a/hal/halmac/halmac_tx_bd_nic.h b/hal/halmac/halmac_tx_bd_nic.h index 1d53acc..b54f274 100644 --- a/hal/halmac/halmac_tx_bd_nic.h +++ b/hal/halmac/halmac_tx_bd_nic.h @@ -1,78 +1,111 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TX_BD_NIC_H_ #define _HALMAC_TX_BD_NIC_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT ||\ + HALMAC_8812F_SUPPORT) /*TXBD_DW0*/ -#define SET_TX_BD_OWN(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 31, 1, __Value) -#define GET_TX_BD_OWN(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 31, 1) -#define SET_TX_BD_PSB(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 16, 8, __Value) -#define GET_TX_BD_PSB(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 16, 8) -#define SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 0, 16, __Value) -#define GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 0, 16) +#define SET_TX_BD_OWN(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x00, 31, 1, value) +#define GET_TX_BD_OWN(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 31, 1) +#define SET_TX_BD_PSB(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x00, 16, 8, value) +#define GET_TX_BD_PSB(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 16, 8) +#define SET_TX_BD_TX_BUFF_SIZE0(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x00, 0, 16, value) +#define GET_TX_BD_TX_BUFF_SIZE0(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 0, 16) /*TXBD_DW1*/ -#define SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x04, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x04, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x04, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x04, 0, 32) /*TXBD_DW2*/ -#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x08, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x08, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x08, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x08, 0, 32) /*TXBD_DW4*/ -#define SET_TX_BD_A1(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x10, 31, 1, __Value) -#define GET_TX_BD_A1(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x10, 31, 1) -#define SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x10, 0, 16, __Value) -#define GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x10, 0, 16) +#define SET_TX_BD_A1(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x10, 31, 1, value) +#define GET_TX_BD_A1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 31, 1) +#define SET_TX_BD_TX_BUFF_SIZE1(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x10, 0, 16, value) +#define GET_TX_BD_TX_BUFF_SIZE1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 0, 16) /*TXBD_DW5*/ -#define SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x14, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x14, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR1_LOW(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x14, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR1_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x14, 0, 32) /*TXBD_DW6*/ -#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x18, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x18, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x18, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x18, 0, 32) /*TXBD_DW8*/ -#define SET_TX_BD_A2(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x20, 31, 1, __Value) -#define GET_TX_BD_A2(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x20, 31, 1) -#define SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x20, 0, 16, __Value) -#define GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x20, 0, 16) +#define SET_TX_BD_A2(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x20, 31, 1, value) +#define GET_TX_BD_A2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 31, 1) +#define SET_TX_BD_TX_BUFF_SIZE2(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x20, 0, 16, value) +#define GET_TX_BD_TX_BUFF_SIZE2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 0, 16) /*TXBD_DW9*/ -#define SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x24, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x24, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR2_LOW(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x24, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR2_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x24, 0, 32) /*TXBD_DW10*/ -#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x28, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x28, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x28, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x28, 0, 32) /*TXBD_DW12*/ -#define SET_TX_BD_A3(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x30, 31, 1, __Value) -#define GET_TX_BD_A3(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x30, 31, 1) -#define SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x30, 0, 16, __Value) -#define GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x30, 0, 16) +#define SET_TX_BD_A3(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x30, 31, 1, value) +#define GET_TX_BD_A3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 31, 1) +#define SET_TX_BD_TX_BUFF_SIZE3(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x30, 0, 16, value) +#define GET_TX_BD_TX_BUFF_SIZE3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 0, 16) /*TXBD_DW13*/ -#define SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x34, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x34, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR3_LOW(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x34, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR3_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x34, 0, 32) /*TXBD_DW14*/ -#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x38, 0, 32, __Value) -#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x38, 0, 32) +#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd, value) \ + SET_BITS_TO_LE_4BYTE(txbd + 0x38, 0, 32, value) +#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x38, 0, 32) #endif - #endif diff --git a/hal/halmac/halmac_tx_desc_ap.h b/hal/halmac/halmac_tx_desc_ap.h index e9c1e59..c09f080 100644 --- a/hal/halmac/halmac_tx_desc_ap.h +++ b/hal/halmac/halmac_tx_desc_ap.h @@ -1,566 +1,1942 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TX_DESC_AP_H_ #define _HALMAC_TX_DESC_AP_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 31) -#define SET_TX_DESC_DISQSELSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 31) -#define GET_TX_DESC_DISQSELSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 31) +#define SET_TX_DESC_DISQSELSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 31) +#define SET_TX_DESC_DISQSELSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31) +#define GET_TX_DESC_DISQSELSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 31) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_IE_END_BODY(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 31) +#define SET_TX_DESC_IE_END_BODY_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31) +#define GET_TX_DESC_IE_END_BODY(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 31) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_GF(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 30) +#define SET_TX_DESC_GF_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30) +#define GET_TX_DESC_GF(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 30) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_GF(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 30) -#define SET_TX_DESC_GF_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 30) -#define GET_TX_DESC_GF(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 30) -#define SET_TX_DESC_NO_ACM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 29) -#define SET_TX_DESC_NO_ACM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 29) -#define GET_TX_DESC_NO_ACM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 29) +#define SET_TX_DESC_AGG_EN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 30) +#define SET_TX_DESC_AGG_EN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30) +#define GET_TX_DESC_AGG_EN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 30) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 28) -#define SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 28) -#define GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 28) +#define SET_TX_DESC_NO_ACM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 29) +#define SET_TX_DESC_NO_ACM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29) +#define GET_TX_DESC_NO_ACM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 29) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 27) -#define SET_TX_DESC_AMSDU_PAD_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 27) -#define GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 27) +#define SET_TX_DESC_BK_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 29) +#define SET_TX_DESC_BK_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29) +#define GET_TX_DESC_BK_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 29) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_LS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 26) -#define SET_TX_DESC_LS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 26) -#define GET_TX_DESC_LS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 26) -#define SET_TX_DESC_HTC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 25) -#define SET_TX_DESC_HTC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 25) -#define GET_TX_DESC_HTC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 25) -#define SET_TX_DESC_BMC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 24) -#define SET_TX_DESC_BMC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 24) -#define GET_TX_DESC_BMC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 24) -#define SET_TX_DESC_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xff, 16) -#define SET_TX_DESC_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xff, 16) -#define GET_TX_DESC_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0xff, 16) -#define SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xffff, 0) -#define SET_TX_DESC_TXPKTSIZE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xffff, 0) -#define GET_TX_DESC_TXPKTSIZE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0xffff, 0) +#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 28) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 28) +#define GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 28) -/*TXDESC_WORD1*/ +#endif -#define SET_TX_DESC_MOREDATA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 29) -#define SET_TX_DESC_MOREDATA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 29) -#define GET_TX_DESC_MOREDATA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 29) -#define SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 24) -#define SET_TX_DESC_PKT_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 24) -#define GET_TX_DESC_PKT_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 24) -#define SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x3, 22) -#define SET_TX_DESC_SEC_TYPE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x3, 22) -#define GET_TX_DESC_SEC_TYPE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x3, 22) -#define SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 21) -#define SET_TX_DESC_EN_DESC_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 21) -#define GET_TX_DESC_EN_DESC_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 21) -#define SET_TX_DESC_RATE_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 16) -#define SET_TX_DESC_RATE_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 16) -#define GET_TX_DESC_RATE_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 16) -#define SET_TX_DESC_PIFS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 15) -#define SET_TX_DESC_PIFS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 15) -#define GET_TX_DESC_PIFS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 15) -#define SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 14) -#define SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 14) -#define GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 14) -#define SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 13) -#define SET_TX_DESC_RD_NAV_EXT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 13) -#define GET_TX_DESC_RD_NAV_EXT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 13) -#define SET_TX_DESC_QSEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 8) -#define SET_TX_DESC_QSEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 8) -#define GET_TX_DESC_QSEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 8) -#define SET_TX_DESC_MACID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x7f, 0) -#define SET_TX_DESC_MACID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x7f, 0) -#define GET_TX_DESC_MACID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x7f, 0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 27) +#define SET_TX_DESC_AMSDU_PAD_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 27) +#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 27) +#define SET_TX_DESC_LS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 26) +#define SET_TX_DESC_LS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 26) +#define GET_TX_DESC_LS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 26) +#define SET_TX_DESC_HTC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 25) +#define SET_TX_DESC_HTC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 25) +#define GET_TX_DESC_HTC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 25) +#define SET_TX_DESC_BMC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 24) +#define SET_TX_DESC_BMC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 24) +#define GET_TX_DESC_BMC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 24) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_PKT_OFFSET_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1f, 24) +#define SET_TX_DESC_PKT_OFFSET_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1f, 24) +#define GET_TX_DESC_PKT_OFFSET_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1f, \ + 24) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0xff, 16) +#define SET_TX_DESC_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xff, 16) +#define GET_TX_DESC_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0xff, \ + 16) +#define SET_TX_DESC_TXPKTSIZE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0xffff, 0) +#define SET_TX_DESC_TXPKTSIZE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xffff, 0) +#define GET_TX_DESC_TXPKTSIZE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, \ + 0xffff, 0) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/*WORD1*/ + +#define SET_TX_DESC_HW_AES_IV_V2(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 31) +#define SET_TX_DESC_HW_AES_IV_V2_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 31) +#define GET_TX_DESC_HW_AES_IV_V2(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 31) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_AMSDU(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 30) +#define SET_TX_DESC_AMSDU_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30) +#define GET_TX_DESC_AMSDU(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 30) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_FTM_EN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 30) +#define SET_TX_DESC_FTM_EN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30) +#define GET_TX_DESC_FTM_EN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 30) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_MOREDATA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 29) +#define SET_TX_DESC_MOREDATA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29) +#define GET_TX_DESC_MOREDATA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 29) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_HW_AES_IV_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 29) +#define SET_TX_DESC_HW_AES_IV_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29) +#define GET_TX_DESC_HW_AES_IV_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 29) +#define SET_TX_DESC_MHR_CP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 25) +#define SET_TX_DESC_MHR_CP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 25) +#define GET_TX_DESC_MHR_CP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 25) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1f, 24) +#define SET_TX_DESC_PKT_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 24) +#define GET_TX_DESC_PKT_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \ + 24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_SMH_EN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 24) +#define SET_TX_DESC_SMH_EN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 24) +#define GET_TX_DESC_SMH_EN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 24) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_SEC_TYPE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x3, 22) +#define SET_TX_DESC_SEC_TYPE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x3, 22) +#define GET_TX_DESC_SEC_TYPE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x3, \ + 22) +#define SET_TX_DESC_EN_DESC_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 21) +#define SET_TX_DESC_EN_DESC_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 21) +#define GET_TX_DESC_EN_DESC_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 21) +#define SET_TX_DESC_RATE_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1f, 16) +#define SET_TX_DESC_RATE_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 16) +#define GET_TX_DESC_RATE_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \ + 16) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_SMH_CAM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0xff, 16) +#define SET_TX_DESC_SMH_CAM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0xff, 16) +#define GET_TX_DESC_SMH_CAM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0xff, \ + 16) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_PIFS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 15) +#define SET_TX_DESC_PIFS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 15) +#define GET_TX_DESC_PIFS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 15) +#define SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 14) +#define SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 14) +#define GET_TX_DESC_LSIG_TXOP_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 14) +#define SET_TX_DESC_RD_NAV_EXT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 13) +#define SET_TX_DESC_RD_NAV_EXT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13) +#define GET_TX_DESC_RD_NAV_EXT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 13) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_EXT_EDCA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 13) +#define SET_TX_DESC_EXT_EDCA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13) +#define GET_TX_DESC_EXT_EDCA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 13) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_QSEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1f, 8) +#define SET_TX_DESC_QSEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 8) +#define GET_TX_DESC_QSEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \ + 8) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_SPECIAL_CW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 7) +#define SET_TX_DESC_SPECIAL_CW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 7) +#define GET_TX_DESC_SPECIAL_CW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, 7) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_MACID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x7f, 0) +#define SET_TX_DESC_MACID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x7f, 0) +#define GET_TX_DESC_MACID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x7f, \ + 0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_MACID_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x7f, 0) +#define SET_TX_DESC_MACID_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x7f, 0) +#define GET_TX_DESC_MACID_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x7f, \ + 0) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 31) -#define SET_TX_DESC_HW_AES_IV_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 31) -#define GET_TX_DESC_HW_AES_IV(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 31) +#define SET_TX_DESC_HW_AES_IV(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 31) +#define SET_TX_DESC_HW_AES_IV_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31) +#define GET_TX_DESC_HW_AES_IV(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 31) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_CHK_EN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 31) +#define SET_TX_DESC_CHK_EN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31) +#define GET_TX_DESC_CHK_EN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 31) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_FTM_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 30) -#define SET_TX_DESC_FTM_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 30) -#define GET_TX_DESC_FTM_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 30) +#define SET_TX_DESC_FTM_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 30) +#define SET_TX_DESC_FTM_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 30) +#define GET_TX_DESC_FTM_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 30) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_G_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3f, 24) -#define SET_TX_DESC_G_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3f, 24) -#define GET_TX_DESC_G_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x3f, 24) -#define SET_TX_DESC_BT_NULL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 23) -#define SET_TX_DESC_BT_NULL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 23) -#define GET_TX_DESC_BT_NULL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 23) -#define SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x7, 20) -#define SET_TX_DESC_AMPDU_DENSITY_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x7, 20) -#define GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x7, 20) -#define SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 19) -#define SET_TX_DESC_SPE_RPT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 19) -#define GET_TX_DESC_SPE_RPT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 19) -#define SET_TX_DESC_RAW(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 18) -#define SET_TX_DESC_RAW_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 18) -#define GET_TX_DESC_RAW(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 18) -#define SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 17) -#define SET_TX_DESC_MOREFRAG_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 17) -#define GET_TX_DESC_MOREFRAG(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 17) -#define SET_TX_DESC_BK(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 16) -#define SET_TX_DESC_BK_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 16) -#define GET_TX_DESC_BK(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 16) -#define SET_TX_DESC_NULL_1(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 15) -#define SET_TX_DESC_NULL_1_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 15) -#define GET_TX_DESC_NULL_1(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 15) -#define SET_TX_DESC_NULL_0(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 14) -#define SET_TX_DESC_NULL_0_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 14) -#define GET_TX_DESC_NULL_0(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 14) -#define SET_TX_DESC_RDG_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 13) -#define SET_TX_DESC_RDG_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 13) -#define GET_TX_DESC_RDG_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 13) -#define SET_TX_DESC_AGG_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 12) -#define SET_TX_DESC_AGG_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 12) -#define GET_TX_DESC_AGG_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 12) -#define SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3, 10) -#define SET_TX_DESC_CCA_RTS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3, 10) -#define GET_TX_DESC_CCA_RTS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x3, 10) +#define SET_TX_DESC_ANTCEL_D_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xf, 28) +#define SET_TX_DESC_ANTCEL_D_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xf, 28) +#define GET_TX_DESC_ANTCEL_D_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xf, \ + 28) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 9) -#define SET_TX_DESC_TRI_FRAME_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 9) -#define GET_TX_DESC_TRI_FRAME(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 9) +#define SET_TX_DESC_DMA_PRI(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 27) +#define SET_TX_DESC_DMA_PRI_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 27) +#define GET_TX_DESC_DMA_PRI(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 27) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_G_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x3f, 24) +#define SET_TX_DESC_G_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3f, 24) +#define GET_TX_DESC_G_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3f, \ + 24) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x7, 24) +#define SET_TX_DESC_MAX_AMSDU_MODE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 24) +#define GET_TX_DESC_MAX_AMSDU_MODE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7, \ + 24) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_C_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xf, 24) +#define SET_TX_DESC_ANTSEL_C_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xf, 24) +#define GET_TX_DESC_ANTSEL_C_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xf, \ + 24) + +#endif -#define SET_TX_DESC_P_AID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1ff, 0) -#define SET_TX_DESC_P_AID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1ff, 0) -#define GET_TX_DESC_P_AID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1ff, 0) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_BT_NULL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 23) +#define SET_TX_DESC_BT_NULL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 23) +#define GET_TX_DESC_BT_NULL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 23) +#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x7, 20) +#define SET_TX_DESC_AMPDU_DENSITY_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 20) +#define GET_TX_DESC_AMPDU_DENSITY(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7, \ + 20) +#define SET_TX_DESC_SPE_RPT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 19) +#define SET_TX_DESC_SPE_RPT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 19) +#define GET_TX_DESC_SPE_RPT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 19) +#define SET_TX_DESC_RAW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 18) +#define SET_TX_DESC_RAW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 18) +#define GET_TX_DESC_RAW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 18) +#define SET_TX_DESC_MOREFRAG(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 17) +#define SET_TX_DESC_MOREFRAG_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 17) +#define GET_TX_DESC_MOREFRAG(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 17) +#define SET_TX_DESC_BK(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 16) +#define SET_TX_DESC_BK_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 16) +#define GET_TX_DESC_BK(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 16) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xff, 16) +#define SET_TX_DESC_DMA_TXAGG_NUM_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xff, 16) +#define GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xff, \ + 16) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_NULL_1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 15) +#define SET_TX_DESC_NULL_1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 15) +#define GET_TX_DESC_NULL_1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 15) +#define SET_TX_DESC_NULL_0(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 14) +#define SET_TX_DESC_NULL_0_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 14) +#define GET_TX_DESC_NULL_0(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 14) +#define SET_TX_DESC_RDG_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 13) +#define SET_TX_DESC_RDG_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 13) +#define GET_TX_DESC_RDG_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 13) +#define SET_TX_DESC_AGG_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 12) +#define SET_TX_DESC_AGG_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 12) +#define GET_TX_DESC_AGG_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 12) +#define SET_TX_DESC_CCA_RTS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x3, 10) +#define SET_TX_DESC_CCA_RTS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3, 10) +#define GET_TX_DESC_CCA_RTS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3, \ + 10) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_TRI_FRAME(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 9) +#define SET_TX_DESC_TRI_FRAME_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 9) +#define GET_TX_DESC_TRI_FRAME(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, 9) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_P_AID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1ff, 0) +#define SET_TX_DESC_P_AID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1ff, 0) +#define GET_TX_DESC_P_AID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, \ + 0x1ff, 0) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xffff, 0) +#define SET_TX_DESC_TXDESC_CHECKSUM_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xffff, 0) +#define GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, \ + 0xffff, 0) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0xff, 24) -#define SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0xff, 24) -#define GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0xff, 24) -#define SET_TX_DESC_NDPA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 22) -#define SET_TX_DESC_NDPA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 22) -#define GET_TX_DESC_NDPA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x3, 22) -#define SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 17) -#define SET_TX_DESC_MAX_AGG_NUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 17) -#define GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1f, 17) -#define SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 16) -#define SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 16) -#define GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 16) -#define SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 15) -#define SET_TX_DESC_NAVUSEHDR_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 15) -#define GET_TX_DESC_NAVUSEHDR(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 15) +#define SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0xff, 24) +#define SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0xff, 24) +#define GET_TX_DESC_AMPDU_MAX_TIME(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0xff, \ + 24) +#define SET_TX_DESC_NDPA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x3, 22) +#define SET_TX_DESC_NDPA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x3, 22) +#define GET_TX_DESC_NDPA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x3, \ + 22) +#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 17) +#define SET_TX_DESC_MAX_AGG_NUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 17) +#define GET_TX_DESC_MAX_AGG_NUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 17) +#define SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 16) +#define SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 16) +#define GET_TX_DESC_USE_MAX_TIME_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_CHK_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 14) -#define SET_TX_DESC_CHK_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 14) -#define GET_TX_DESC_CHK_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 14) +#define SET_TX_DESC_OFFLOAD_SIZE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x7fff, 16) +#define SET_TX_DESC_OFFLOAD_SIZE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7fff, 16) +#define GET_TX_DESC_OFFLOAD_SIZE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, \ + 0x7fff, 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 15) +#define SET_TX_DESC_NAVUSEHDR_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 15) +#define GET_TX_DESC_NAVUSEHDR(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 15) +#define SET_TX_DESC_CHK_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 14) +#define SET_TX_DESC_CHK_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 14) +#define GET_TX_DESC_CHK_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 14) +#define SET_TX_DESC_HW_RTS_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 13) +#define SET_TX_DESC_HW_RTS_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 13) +#define GET_TX_DESC_HW_RTS_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 13) +#define SET_TX_DESC_RTSEN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 12) +#define SET_TX_DESC_RTSEN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 12) +#define GET_TX_DESC_RTSEN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 12) +#define SET_TX_DESC_CTS2SELF(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 11) +#define SET_TX_DESC_CTS2SELF_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 11) +#define GET_TX_DESC_CTS2SELF(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 11) -#define SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 13) -#define SET_TX_DESC_HW_RTS_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 13) -#define GET_TX_DESC_HW_RTS_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 13) -#define SET_TX_DESC_RTSEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 12) -#define SET_TX_DESC_RTSEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 12) -#define GET_TX_DESC_RTSEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 12) -#define SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 11) -#define SET_TX_DESC_CTS2SELF_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 11) -#define GET_TX_DESC_CTS2SELF(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 11) -#define SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 10) -#define SET_TX_DESC_DISDATAFB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 10) -#define GET_TX_DESC_DISDATAFB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 10) -#define SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 9) -#define SET_TX_DESC_DISRTSFB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 9) -#define GET_TX_DESC_DISRTSFB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 9) -#define SET_TX_DESC_USE_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 8) -#define SET_TX_DESC_USE_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 8) -#define GET_TX_DESC_USE_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 8) -#define SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 6) -#define SET_TX_DESC_HW_SSN_SEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 6) -#define GET_TX_DESC_HW_SSN_SEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x3, 6) +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_CHANNEL_DMA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 11) +#define SET_TX_DESC_CHANNEL_DMA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 11) +#define GET_TX_DESC_CHANNEL_DMA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 11) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_DISDATAFB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 10) +#define SET_TX_DESC_DISDATAFB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 10) +#define GET_TX_DESC_DISDATAFB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \ + 10) +#define SET_TX_DESC_DISRTSFB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 9) +#define SET_TX_DESC_DISRTSFB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 9) +#define GET_TX_DESC_DISRTSFB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 9) +#define SET_TX_DESC_USE_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 8) +#define SET_TX_DESC_USE_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 8) +#define GET_TX_DESC_USE_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 8) +#define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x3, 6) +#define SET_TX_DESC_HW_SSN_SEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x3, 6) +#define GET_TX_DESC_HW_SSN_SEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x3, 6) -#define SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 0) -#define SET_TX_DESC_WHEADER_LEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 0) -#define GET_TX_DESC_WHEADER_LEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1f, 0) +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_IE_CNT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x7, 6) +#define SET_TX_DESC_IE_CNT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7, 6) +#define GET_TX_DESC_IE_CNT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x7, 6) +#define SET_TX_DESC_IE_CNT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 5) +#define SET_TX_DESC_IE_CNT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 5) +#define GET_TX_DESC_IE_CNT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 5) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) +#define SET_TX_DESC_WHEADER_LEN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 0) +#define SET_TX_DESC_WHEADER_LEN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0) +#define GET_TX_DESC_WHEADER_LEN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 0) -/*TXDESC_WORD4*/ +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_WHEADER_LEN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 0) +#define SET_TX_DESC_WHEADER_LEN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0) +#define GET_TX_DESC_WHEADER_LEN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 0) + +#endif -#define SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3, 30) -#define SET_TX_DESC_PCTS_MASK_IDX_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3, 30) -#define GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x3, 30) -#define SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 29) -#define SET_TX_DESC_PCTS_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 29) -#define GET_TX_DESC_PCTS_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 29) -#define SET_TX_DESC_RTSRATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 24) -#define SET_TX_DESC_RTSRATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 24) -#define GET_TX_DESC_RTSRATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1f, 24) -#define SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3f, 18) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3f, 18) -#define GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x3f, 18) -#define SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 17) -#define SET_TX_DESC_RTY_LMT_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 17) -#define GET_TX_DESC_RTY_LMT_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 17) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0xf, 13) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0xf, 13) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0xf, 13) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 8) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 8) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1f, 8) -#define SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 7) -#define SET_TX_DESC_TRY_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 7) -#define GET_TX_DESC_TRY_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 7) -#define SET_TX_DESC_DATARATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x7f, 0) -#define SET_TX_DESC_DATARATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x7f, 0) -#define GET_TX_DESC_DATARATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x7f, 0) - -#endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x3, 30) +#define SET_TX_DESC_PCTS_MASK_IDX_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3, 30) +#define GET_TX_DESC_PCTS_MASK_IDX(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3, \ + 30) +#define SET_TX_DESC_PCTS_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 29) +#define SET_TX_DESC_PCTS_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 29) +#define GET_TX_DESC_PCTS_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \ + 29) +#define SET_TX_DESC_RTSRATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1f, 24) +#define SET_TX_DESC_RTSRATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1f, 24) +#define GET_TX_DESC_RTSRATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1f, \ + 24) +#define SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x3f, 18) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3f, 18) +#define GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3f, \ + 18) +#define SET_TX_DESC_RTY_LMT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 17) +#define SET_TX_DESC_RTY_LMT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 17) +#define GET_TX_DESC_RTY_LMT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \ + 17) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0xf, 13) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0xf, 13) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0xf, \ + 13) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1f, 8) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1f, 8) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1f, \ + 8) +#define SET_TX_DESC_TRY_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 7) +#define SET_TX_DESC_TRY_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 7) +#define GET_TX_DESC_TRY_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, 7) +#define SET_TX_DESC_DATARATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x7f, 0) +#define SET_TX_DESC_DATARATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7f, 0) +#define GET_TX_DESC_DATARATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x7f, \ + 0) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 31) -#define SET_TX_DESC_POLLUTED_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 31) -#define GET_TX_DESC_POLLUTED(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 31) +#define SET_TX_DESC_POLLUTED(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 31) +#define SET_TX_DESC_POLLUTED_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 31) +#define GET_TX_DESC_POLLUTED(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 31) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 28) -#define SET_TX_DESC_TXPWR_OFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 28) -#define GET_TX_DESC_TXPWR_OFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 28) -#define SET_TX_DESC_TX_ANT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 24) -#define SET_TX_DESC_TX_ANT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 24) -#define GET_TX_DESC_TX_ANT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 24) -#define SET_TX_DESC_PORT_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 21) -#define SET_TX_DESC_PORT_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 21) -#define GET_TX_DESC_PORT_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 21) +#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 30) +#define SET_TX_DESC_ANTSEL_EN_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 30) +#define GET_TX_DESC_ANTSEL_EN_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 30) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 18) -#define SET_TX_DESC_MULTIPLE_PORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 18) -#define GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 18) +#define SET_TX_DESC_TXPWR_OFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x7, 28) +#define SET_TX_DESC_TXPWR_OFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 28) +#define GET_TX_DESC_TXPWR_OFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7, \ + 28) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 17) -#define SET_TX_DESC_SIGNALING_TAPKT_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 17) -#define GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 17) +#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 28) +#define SET_TX_DESC_TXPWR_OFSET_TYPE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 28) +#define GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, \ + 28) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_RTS_SC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 13) -#define SET_TX_DESC_RTS_SC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 13) -#define GET_TX_DESC_RTS_SC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 13) -#define SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 12) -#define SET_TX_DESC_RTS_SHORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 12) -#define GET_TX_DESC_RTS_SHORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 12) +#define SET_TX_DESC_TX_ANT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xf, 24) +#define SET_TX_DESC_TX_ANT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 24) +#define GET_TX_DESC_TX_ANT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \ + 24) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10) -#define SET_TX_DESC_VCS_STBC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10) -#define GET_TX_DESC_VCS_STBC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 10) +#define SET_TX_DESC_DROP_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 24) +#define SET_TX_DESC_DROP_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 24) +#define GET_TX_DESC_DROP_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, \ + 24) #endif -#if (HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_RTS_STBC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10) -#define SET_TX_DESC_RTS_STBC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10) -#define GET_TX_DESC_RTS_STBC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 10) +#define SET_TX_DESC_PORT_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x7, 21) +#define SET_TX_DESC_PORT_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 21) +#define GET_TX_DESC_PORT_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7, \ + 21) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 8) -#define SET_TX_DESC_DATA_STBC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 8) -#define GET_TX_DESC_DATA_STBC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 8) +#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x7, 18) +#define SET_TX_DESC_MULTIPLE_PORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 18) +#define GET_TX_DESC_MULTIPLE_PORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7, \ + 18) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 7) -#define SET_TX_DESC_DATA_LDPC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 7) -#define GET_TX_DESC_DATA_LDPC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 7) +#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 17) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 17) +#define GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 17) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_DATA_BW(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 5) -#define SET_TX_DESC_DATA_BW_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 5) -#define GET_TX_DESC_DATA_BW(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 5) -#define SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 4) -#define SET_TX_DESC_DATA_SHORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 4) -#define GET_TX_DESC_DATA_SHORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 4) -#define SET_TX_DESC_DATA_SC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 0) -#define SET_TX_DESC_DATA_SC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 0) -#define GET_TX_DESC_DATA_SC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 0) +#define SET_TX_DESC_RTS_SC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xf, 13) +#define SET_TX_DESC_RTS_SC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 13) +#define GET_TX_DESC_RTS_SC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \ + 13) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xf, 13) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 13) +#define GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \ + 13) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_RTS_SHORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 12) +#define SET_TX_DESC_RTS_SHORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 12) +#define GET_TX_DESC_RTS_SHORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 12) +#define SET_TX_DESC_VCS_STBC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 10) +#define SET_TX_DESC_VCS_STBC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 10) +#define GET_TX_DESC_VCS_STBC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, \ + 10) +#define SET_TX_DESC_DATA_STBC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 8) +#define SET_TX_DESC_DATA_STBC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 8) +#define GET_TX_DESC_DATA_STBC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 8) +#define SET_TX_DESC_DATA_LDPC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 7) +#define SET_TX_DESC_DATA_LDPC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 7) +#define GET_TX_DESC_DATA_LDPC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 7) +#define SET_TX_DESC_DATA_BW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 5) +#define SET_TX_DESC_DATA_BW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 5) +#define GET_TX_DESC_DATA_BW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 5) +#define SET_TX_DESC_DATA_SHORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 4) +#define SET_TX_DESC_DATA_SHORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 4) +#define GET_TX_DESC_DATA_SHORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 4) +#define SET_TX_DESC_DATA_SC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xf, 0) +#define SET_TX_DESC_DATA_SC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 0) +#define GET_TX_DESC_DATA_SC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, 0) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 30) -#define SET_TX_DESC_ANTSEL_D_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 30) -#define GET_TX_DESC_ANTSEL_D(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 30) -#define SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 28) -#define SET_TX_DESC_ANT_MAPD_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 28) -#define GET_TX_DESC_ANT_MAPD(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 28) -#define SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 26) -#define SET_TX_DESC_ANT_MAPC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 26) -#define GET_TX_DESC_ANT_MAPC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 26) -#define SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 24) -#define SET_TX_DESC_ANT_MAPB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 24) -#define GET_TX_DESC_ANT_MAPB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 24) -#define SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 22) -#define SET_TX_DESC_ANT_MAPA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 22) -#define GET_TX_DESC_ANT_MAPA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 22) -#define SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 20) -#define SET_TX_DESC_ANTSEL_C_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 20) -#define GET_TX_DESC_ANTSEL_C(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 20) -#define SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 18) -#define SET_TX_DESC_ANTSEL_B_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 18) -#define GET_TX_DESC_ANTSEL_B(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 18) - -#endif - -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) - -#define SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 16) -#define SET_TX_DESC_ANTSEL_A_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 16) -#define GET_TX_DESC_ANTSEL_A(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 16) -#define SET_TX_DESC_MBSSID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xf, 12) -#define SET_TX_DESC_MBSSID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xf, 12) -#define GET_TX_DESC_MBSSID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0xf, 12) -#define SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xfff, 0) -#define SET_TX_DESC_SW_DEFINE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xfff, 0) -#define GET_TX_DESC_SW_DEFINE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0xfff, 0) +#define SET_TX_DESC_ANTSEL_D(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 30) +#define SET_TX_DESC_ANTSEL_D_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30) +#define GET_TX_DESC_ANTSEL_D(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 30) -/*TXDESC_WORD7*/ +#endif + +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) -#define SET_TX_DESC_DMA_TXAGG_NUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) -#define GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xff, 24) +#define SET_TX_DESC_ANT_MAPD_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 30) +#define SET_TX_DESC_ANT_MAPD_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30) +#define GET_TX_DESC_ANT_MAPD_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 30) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) -#define SET_TX_DESC_FINAL_DATA_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) -#define GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xff, 24) -#define SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xf, 20) -#define SET_TX_DESC_NTX_MAP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xf, 20) -#define GET_TX_DESC_NTX_MAP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xf, 20) +#define SET_TX_DESC_ANT_MAPD(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 28) +#define SET_TX_DESC_ANT_MAPD_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28) +#define GET_TX_DESC_ANT_MAPD(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 28) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define SET_TX_DESC_TX_BUFF_SIZE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0) -#define SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define SET_TX_DESC_TXDESC_CHECKSUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0) -#define SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define SET_TX_DESC_TIMESTAMP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) -#define GET_TX_DESC_TIMESTAMP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0) +#define SET_TX_DESC_ANT_MAPC_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 28) +#define SET_TX_DESC_ANT_MAPC_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28) +#define GET_TX_DESC_ANT_MAPC_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 28) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) +#define SET_TX_DESC_ANT_MAPC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 26) +#define SET_TX_DESC_ANT_MAPC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26) +#define GET_TX_DESC_ANT_MAPC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 26) -/*TXDESC_WORD8*/ +#endif + +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 31) -#define SET_TX_DESC_TXWIFI_CP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 31) -#define GET_TX_DESC_TXWIFI_CP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 31) -#define SET_TX_DESC_MAC_CP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 30) -#define SET_TX_DESC_MAC_CP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 30) -#define GET_TX_DESC_MAC_CP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 30) -#define SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 29) -#define SET_TX_DESC_STW_PKTRE_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 29) -#define GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 29) -#define SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 28) -#define SET_TX_DESC_STW_RB_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 28) -#define GET_TX_DESC_STW_RB_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 28) -#define SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 27) -#define SET_TX_DESC_STW_RATE_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 27) -#define GET_TX_DESC_STW_RATE_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 27) -#define SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 26) -#define SET_TX_DESC_STW_ANT_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 26) -#define GET_TX_DESC_STW_ANT_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 26) -#define SET_TX_DESC_STW_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 25) -#define SET_TX_DESC_STW_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 25) -#define GET_TX_DESC_STW_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 25) -#define SET_TX_DESC_SMH_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 24) -#define SET_TX_DESC_SMH_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 24) -#define GET_TX_DESC_SMH_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 24) +#define SET_TX_DESC_ANT_MAPB_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 26) +#define SET_TX_DESC_ANT_MAPB_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26) +#define GET_TX_DESC_ANT_MAPB_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 26) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 24) -#define SET_TX_DESC_TAILPAGE_L_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 24) -#define GET_TX_DESC_TAILPAGE_L(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 24) +#define SET_TX_DESC_ANT_MAPB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 24) +#define SET_TX_DESC_ANT_MAPB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24) +#define GET_TX_DESC_ANT_MAPB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 24) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANT_MAPA_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 24) +#define SET_TX_DESC_ANT_MAPA_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24) +#define GET_TX_DESC_ANT_MAPA_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 24) + +#endif -#define SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) -#define SET_TX_DESC_SDIO_DMASEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) -#define GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 16) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_ANT_MAPA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 22) +#define SET_TX_DESC_ANT_MAPA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 22) +#define GET_TX_DESC_ANT_MAPA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 22) +#define SET_TX_DESC_ANTSEL_C(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 20) +#define SET_TX_DESC_ANTSEL_C_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 20) +#define GET_TX_DESC_ANTSEL_C(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 20) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) -#define SET_TX_DESC_NEXTHEADPAGE_L_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) -#define GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 16) -#define SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 15) -#define SET_TX_DESC_EN_HWSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 15) -#define GET_TX_DESC_EN_HWSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 15) +#define SET_TX_DESC_ANTSEL_B_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0xf, 20) +#define SET_TX_DESC_ANTSEL_B_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 20) +#define GET_TX_DESC_ANTSEL_B_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf, \ + 20) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_B(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 18) +#define SET_TX_DESC_ANTSEL_B_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 18) +#define GET_TX_DESC_ANTSEL_B(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 18) +#define SET_TX_DESC_ANTSEL_A(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 16) +#define SET_TX_DESC_ANTSEL_A_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 16) +#define GET_TX_DESC_ANTSEL_A(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 16) -#define SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 14) -#define SET_TX_DESC_EN_HWEXSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 14) -#define GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 14) +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_A_V1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0xf, 16) +#define SET_TX_DESC_ANTSEL_A_V1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 16) +#define GET_TX_DESC_ANTSEL_A_V1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf, \ + 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_DATA_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 8) -#define SET_TX_DESC_DATA_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 8) -#define GET_TX_DESC_DATA_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3f, 8) -#define SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3, 6) -#define SET_TX_DESC_BAR_RTY_TH_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3, 6) -#define GET_TX_DESC_BAR_RTY_TH(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3, 6) -#define SET_TX_DESC_RTS_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 0) -#define SET_TX_DESC_RTS_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 0) -#define GET_TX_DESC_RTS_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3f, 0) +#define SET_TX_DESC_MBSSID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0xf, 12) +#define SET_TX_DESC_MBSSID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 12) +#define GET_TX_DESC_MBSSID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf, \ + 12) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) +#define SET_TX_DESC_SW_DEFINE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0xfff, 0) +#define SET_TX_DESC_SW_DEFINE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xfff, 0) +#define GET_TX_DESC_SW_DEFINE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, \ + 0xfff, 0) -/*TXDESC_WORD9*/ +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_SWPS_SEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0xfff, 0) +#define SET_TX_DESC_SWPS_SEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xfff, 0) +#define GET_TX_DESC_SWPS_SEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, \ + 0xfff, 0) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xff, 24) +#define SET_TX_DESC_DMA_TXAGG_NUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xff, 24) +#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \ + 24) +#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xff, 24) +#define SET_TX_DESC_FINAL_DATA_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xff, 24) +#define GET_TX_DESC_FINAL_DATA_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \ + 24) +#define SET_TX_DESC_NTX_MAP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xf, 20) +#define SET_TX_DESC_NTX_MAP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xf, 20) +#define GET_TX_DESC_NTX_MAP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xf, \ + 20) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0x1, 19) +#define SET_TX_DESC_ANTSEL_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 19) +#define GET_TX_DESC_ANTSEL_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, \ + 19) +#define SET_TX_DESC_MBSSID_EX(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0x7, 16) +#define SET_TX_DESC_MBSSID_EX_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x7, 16) +#define GET_TX_DESC_MBSSID_EX(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x7, \ + 16) -#define SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 28) -#define SET_TX_DESC_TAILPAGE_H_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 28) -#define GET_TX_DESC_TAILPAGE_H(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xf, 28) -#define SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 24) -#define SET_TX_DESC_NEXTHEADPAGE_H_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 24) -#define GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xf, 24) +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xffff, 0) +#define SET_TX_DESC_TX_BUFF_SIZE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0) +#define GET_TX_DESC_TX_BUFF_SIZE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \ + 0xffff, 0) +#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xffff, 0) +#define SET_TX_DESC_TXDESC_CHECKSUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0) +#define GET_TX_DESC_TXDESC_CHECKSUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \ + 0xffff, 0) +#define SET_TX_DESC_TIMESTAMP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xffff, 0) +#define SET_TX_DESC_TIMESTAMP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0) +#define GET_TX_DESC_TIMESTAMP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \ + 0xffff, 0) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_TXWIFI_CP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 31) +#define SET_TX_DESC_TXWIFI_CP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 31) +#define GET_TX_DESC_TXWIFI_CP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 31) +#define SET_TX_DESC_MAC_CP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 30) +#define SET_TX_DESC_MAC_CP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 30) +#define GET_TX_DESC_MAC_CP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 30) +#define SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 29) +#define SET_TX_DESC_STW_PKTRE_DIS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 29) +#define GET_TX_DESC_STW_PKTRE_DIS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 29) +#define SET_TX_DESC_STW_RB_DIS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 28) +#define SET_TX_DESC_STW_RB_DIS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 28) +#define GET_TX_DESC_STW_RB_DIS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 28) +#define SET_TX_DESC_STW_RATE_DIS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 27) +#define SET_TX_DESC_STW_RATE_DIS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 27) +#define GET_TX_DESC_STW_RATE_DIS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 27) +#define SET_TX_DESC_STW_ANT_DIS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 26) +#define SET_TX_DESC_STW_ANT_DIS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 26) +#define GET_TX_DESC_STW_ANT_DIS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 26) +#define SET_TX_DESC_STW_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 25) +#define SET_TX_DESC_STW_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 25) +#define GET_TX_DESC_STW_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 25) +#define SET_TX_DESC_SMH_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 24) +#define SET_TX_DESC_SMH_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 24) +#define GET_TX_DESC_SMH_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 24) +#define SET_TX_DESC_TAILPAGE_L(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xff, 24) +#define SET_TX_DESC_TAILPAGE_L_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 24) +#define GET_TX_DESC_TAILPAGE_L(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \ + 24) +#define SET_TX_DESC_SDIO_DMASEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xff, 16) +#define SET_TX_DESC_SDIO_DMASEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 16) +#define GET_TX_DESC_SDIO_DMASEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \ + 16) +#define SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xff, 16) +#define SET_TX_DESC_NEXTHEADPAGE_L_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 16) +#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \ + 16) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 15) +#define SET_TX_DESC_EN_HWSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 15) +#define GET_TX_DESC_EN_HWSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 15) +#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 14) +#define SET_TX_DESC_EN_HWEXSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 14) +#define GET_TX_DESC_EN_HWEXSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \ + 14) -#define SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xfff, 12) -#define SET_TX_DESC_SW_SEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xfff, 12) -#define GET_TX_DESC_SW_SEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xfff, 12) -#define SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x1, 11) -#define SET_TX_DESC_TXBF_PATH_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x1, 11) -#define GET_TX_DESC_TXBF_PATH(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0x1, 11) -#define SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x7ff, 0) -#define SET_TX_DESC_PADDING_LEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x7ff, 0) -#define GET_TX_DESC_PADDING_LEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0x7ff, 0) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xff, 0) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xff, 0) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xff, 0) +#endif + +#if (HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3, 14) +#define SET_TX_DESC_EN_HWSEQ_MODE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 14) +#define GET_TX_DESC_EN_HWSEQ_MODE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \ + 14) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_DATA_RC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3f, 8) +#define SET_TX_DESC_DATA_RC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3f, 8) +#define GET_TX_DESC_DATA_RC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \ + 8) +#define SET_TX_DESC_BAR_RTY_TH(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3, 6) +#define SET_TX_DESC_BAR_RTY_TH_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 6) +#define GET_TX_DESC_BAR_RTY_TH(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, 6) +#define SET_TX_DESC_RTS_RC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3f, 0) +#define SET_TX_DESC_RTS_RC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3f, 0) +#define GET_TX_DESC_RTS_RC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \ + 0) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_TAILPAGE_H(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xf, 28) +#define SET_TX_DESC_TAILPAGE_H_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 28) +#define GET_TX_DESC_TAILPAGE_H(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf, \ + 28) +#define SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xf, 24) +#define SET_TX_DESC_NEXTHEADPAGE_H_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 24) +#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf, \ + 24) +#define SET_TX_DESC_SW_SEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xfff, 12) +#define SET_TX_DESC_SW_SEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xfff, 12) +#define GET_TX_DESC_SW_SEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, \ + 0xfff, 12) +#define SET_TX_DESC_TXBF_PATH(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 11) +#define SET_TX_DESC_TXBF_PATH_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 11) +#define GET_TX_DESC_TXBF_PATH(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \ + 11) +#define SET_TX_DESC_PADDING_LEN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x7ff, 0) +#define SET_TX_DESC_PADDING_LEN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x7ff, 0) +#define GET_TX_DESC_PADDING_LEN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, \ + 0x7ff, 0) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xff, 0) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 0) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \ + 0) +#endif + +#if (HALMAC_8812F_SUPPORT) /*WORD10*/ -#define SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xff, 8) -#define SET_TX_DESC_MU_DATARATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xff, 8) -#define GET_TX_DESC_MU_DATARATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0xff, 8) -#define SET_TX_DESC_MU_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xf, 4) -#define SET_TX_DESC_MU_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xf, 4) -#define GET_TX_DESC_MU_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0xf, 4) -#define SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0x3, 0) -#define SET_TX_DESC_SND_PKT_SEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0x3, 0) -#define GET_TX_DESC_SND_PKT_SEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0x3, 0) +#define SET_TX_DESC_HT_DATA_SND(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 31) +#define SET_TX_DESC_HT_DATA_SND_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 31) +#define GET_TX_DESC_HT_DATA_SND(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 31) +#define SET_TX_DESC_SHCUT_CAM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x3f, 16) +#define SET_TX_DESC_SHCUT_CAM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3f, 16) +#define GET_TX_DESC_SHCUT_CAM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \ + 0x3f, 16) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_MU_DATARATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0xff, 8) +#define SET_TX_DESC_MU_DATARATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 8) +#define GET_TX_DESC_MU_DATARATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \ + 0xff, 8) +#define SET_TX_DESC_MU_RC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0xf, 4) +#define SET_TX_DESC_MU_RC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xf, 4) +#define GET_TX_DESC_MU_RC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0xf, \ + 4) #endif +#if (HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_NDPA_RATE_SEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 3) +#define SET_TX_DESC_NDPA_RATE_SEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 3) +#define GET_TX_DESC_NDPA_RATE_SEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 3) +#define SET_TX_DESC_HW_NDPA_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 2) +#define SET_TX_DESC_HW_NDPA_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 2) +#define GET_TX_DESC_HW_NDPA_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 2) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_SND_PKT_SEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x3, 0) +#define SET_TX_DESC_SND_PKT_SEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3, 0) +#define GET_TX_DESC_SND_PKT_SEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x3, \ + 0) + +#endif #endif diff --git a/hal/halmac/halmac_tx_desc_buffer_ap.h b/hal/halmac/halmac_tx_desc_buffer_ap.h new file mode 100644 index 0000000..353571a --- /dev/null +++ b/hal/halmac/halmac_tx_desc_buffer_ap.h @@ -0,0 +1,1078 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_BUFFER_AP_H_ +#define _HALMAC_TX_DESC_BUFFER_AP_H_ +#if (HALMAC_8814B_SUPPORT) + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_BUFFER_RDG_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 31) +#define SET_TX_DESC_BUFFER_RDG_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31) +#define GET_TX_DESC_BUFFER_RDG_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 31) +#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 30) +#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30) +#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 30) +#define SET_TX_DESC_BUFFER_AGG_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1, 29) +#define SET_TX_DESC_BUFFER_AGG_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29) +#define GET_TX_DESC_BUFFER_AGG_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \ + 29) +#define SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0x1f, 24) +#define SET_TX_DESC_BUFFER_PKT_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1f, 24) +#define GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1f, \ + 24) +#define SET_TX_DESC_BUFFER_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0xff, 16) +#define SET_TX_DESC_BUFFER_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xff, 16) +#define GET_TX_DESC_BUFFER_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0xff, \ + 16) +#define SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \ + value, 0xffff, 0) +#define SET_TX_DESC_BUFFER_TXPKTSIZE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xffff, 0) +#define GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, \ + 0xffff, 0) + +/*TXDESC_WORD1*/ + +#define SET_TX_DESC_BUFFER_USERATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 31) +#define SET_TX_DESC_BUFFER_USERATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 31) +#define GET_TX_DESC_BUFFER_USERATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 31) +#define SET_TX_DESC_BUFFER_AMSDU(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 30) +#define SET_TX_DESC_BUFFER_AMSDU_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30) +#define GET_TX_DESC_BUFFER_AMSDU(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 30) +#define SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 29) +#define SET_TX_DESC_BUFFER_EN_HWSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29) +#define GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 29) +#define SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 28) +#define SET_TX_DESC_BUFFER_EN_HWEXSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 28) +#define GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 28) +#define SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0xfff, 16) +#define SET_TX_DESC_BUFFER_SW_SEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0xfff, 16) +#define GET_TX_DESC_BUFFER_SW_SEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, \ + 0xfff, 16) +#define SET_TX_DESC_BUFFER_DROP_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x3, 14) +#define SET_TX_DESC_BUFFER_DROP_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x3, 14) +#define GET_TX_DESC_BUFFER_DROP_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x3, \ + 14) +#define SET_TX_DESC_BUFFER_MOREDATA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1, 13) +#define SET_TX_DESC_BUFFER_MOREDATA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13) +#define GET_TX_DESC_BUFFER_MOREDATA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \ + 13) +#define SET_TX_DESC_BUFFER_QSEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0x1f, 8) +#define SET_TX_DESC_BUFFER_QSEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 8) +#define GET_TX_DESC_BUFFER_QSEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \ + 8) +#define SET_TX_DESC_BUFFER_MACID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \ + value, 0xff, 0) +#define SET_TX_DESC_BUFFER_MACID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword1, value, 0xff, 0) +#define GET_TX_DESC_BUFFER_MACID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0xff, \ + 0) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_BUFFER_CHK_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 31) +#define SET_TX_DESC_BUFFER_CHK_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31) +#define GET_TX_DESC_BUFFER_CHK_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 31) +#define SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 30) +#define SET_TX_DESC_BUFFER_DISQSELSEQ_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 30) +#define GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 30) +#define SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x3, 28) +#define SET_TX_DESC_BUFFER_SND_PKT_SEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3, 28) +#define GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3, \ + 28) +#define SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x1, 27) +#define SET_TX_DESC_BUFFER_DMA_PRI_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 27) +#define GET_TX_DESC_BUFFER_DMA_PRI(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \ + 27) +#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0x7, 24) +#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 24) +#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7, \ + 24) +#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xff, 16) +#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xff, 16) +#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xff, \ + 16) +#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \ + value, 0xffff, 0) +#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xffff, 0) +#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, \ + 0xffff, 0) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x7fff, 16) +#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7fff, 16) +#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, \ + 0x7fff, 16) +#define SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 11) +#define SET_TX_DESC_BUFFER_CHANNEL_DMA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 11) +#define GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 11) +#define SET_TX_DESC_BUFFER_MBSSID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0xf, 7) +#define SET_TX_DESC_BUFFER_MBSSID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0xf, 7) +#define GET_TX_DESC_BUFFER_MBSSID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0xf, 7) +#define SET_TX_DESC_BUFFER_BK(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1, 6) +#define SET_TX_DESC_BUFFER_BK_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 6) +#define GET_TX_DESC_BUFFER_BK(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 6) +#define SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \ + value, 0x1f, 0) +#define SET_TX_DESC_BUFFER_WHEADER_LEN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0) +#define GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \ + 0) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 26) +#define SET_TX_DESC_BUFFER_TRY_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 26) +#define GET_TX_DESC_BUFFER_TRY_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \ + 26) +#define SET_TX_DESC_BUFFER_DATA_BW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x3, 24) +#define SET_TX_DESC_BUFFER_DATA_BW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3, 24) +#define GET_TX_DESC_BUFFER_DATA_BW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3, \ + 24) +#define SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 23) +#define SET_TX_DESC_BUFFER_DATA_SHORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 23) +#define GET_TX_DESC_BUFFER_DATA_SHORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \ + 23) +#define SET_TX_DESC_BUFFER_DATARATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x7f, 16) +#define SET_TX_DESC_BUFFER_DATARATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7f, 16) +#define GET_TX_DESC_BUFFER_DATARATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x7f, \ + 16) +#define SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x1, 11) +#define SET_TX_DESC_BUFFER_TXBF_PATH_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 11) +#define GET_TX_DESC_BUFFER_TXBF_PATH(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \ + 11) +#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \ + value, 0x7ff, 0) +#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7ff, 0) +#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, \ + 0x7ff, 0) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 31) +#define SET_TX_DESC_BUFFER_RTY_LMT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 31) +#define GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 31) +#define SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 30) +#define SET_TX_DESC_BUFFER_HW_RTS_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 30) +#define GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 30) +#define SET_TX_DESC_BUFFER_RTS_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 29) +#define SET_TX_DESC_BUFFER_RTS_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 29) +#define GET_TX_DESC_BUFFER_RTS_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 29) +#define SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 28) +#define SET_TX_DESC_BUFFER_CTS2SELF_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 28) +#define GET_TX_DESC_BUFFER_CTS2SELF(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 28) +#define SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xf, 24) +#define SET_TX_DESC_BUFFER_TAILPAGE_H_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 24) +#define GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \ + 24) +#define SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0xff, 16) +#define SET_TX_DESC_BUFFER_TAILPAGE_L_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xff, 16) +#define GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xff, \ + 16) +#define SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 15) +#define SET_TX_DESC_BUFFER_NAVUSEHDR_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 15) +#define GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 15) +#define SET_TX_DESC_BUFFER_BMC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 14) +#define SET_TX_DESC_BUFFER_BMC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 14) +#define GET_TX_DESC_BUFFER_BMC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \ + 14) +#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3f, 8) +#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3f, 8) +#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3f, \ + 8) +#define SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 7) +#define SET_TX_DESC_BUFFER_HW_AES_IV_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 7) +#define GET_TX_DESC_BUFFER_HW_AES_IV(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 7) +#define SET_TX_DESC_BUFFER_BT_NULL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 3) +#define SET_TX_DESC_BUFFER_BT_NULL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 3) +#define GET_TX_DESC_BUFFER_BT_NULL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 3) +#define SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x1, 2) +#define SET_TX_DESC_BUFFER_EN_DESC_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 2) +#define GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 2) +#define SET_TX_DESC_BUFFER_SECTYPE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \ + value, 0x3, 0) +#define SET_TX_DESC_BUFFER_SECTYPE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 0) +#define GET_TX_DESC_BUFFER_SECTYPE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 0) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x7, 29) +#define SET_TX_DESC_BUFFER_MULTIPLE_PORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7, 29) +#define GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7, \ + 29) +#define SET_TX_DESC_BUFFER_POLLUTED(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 28) +#define SET_TX_DESC_BUFFER_POLLUTED_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 28) +#define GET_TX_DESC_BUFFER_POLLUTED(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 28) +#define SET_TX_DESC_BUFFER_NULL_1(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 27) +#define SET_TX_DESC_BUFFER_NULL_1_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 27) +#define GET_TX_DESC_BUFFER_NULL_1(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 27) +#define SET_TX_DESC_BUFFER_NULL_0(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 26) +#define SET_TX_DESC_BUFFER_NULL_0_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 26) +#define GET_TX_DESC_BUFFER_NULL_0(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 26) +#define SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 25) +#define SET_TX_DESC_BUFFER_TRI_FRAME_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 25) +#define GET_TX_DESC_BUFFER_TRI_FRAME(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 25) +#define SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 24) +#define SET_TX_DESC_BUFFER_SPE_RPT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 24) +#define GET_TX_DESC_BUFFER_SPE_RPT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 24) +#define SET_TX_DESC_BUFFER_FTM_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1, 23) +#define SET_TX_DESC_BUFFER_FTM_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 23) +#define GET_TX_DESC_BUFFER_FTM_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \ + 23) +#define SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x7f, 16) +#define SET_TX_DESC_BUFFER_MU_DATARATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7f, 16) +#define GET_TX_DESC_BUFFER_MU_DATARATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7f, \ + 16) +#define SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 14) +#define SET_TX_DESC_BUFFER_CCA_RTS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 14) +#define GET_TX_DESC_BUFFER_CCA_RTS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 14) +#define SET_TX_DESC_BUFFER_NDPA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 12) +#define SET_TX_DESC_BUFFER_NDPA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 12) +#define GET_TX_DESC_BUFFER_NDPA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \ + 12) +#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x3, 9) +#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 9) +#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, 9) +#define SET_TX_DESC_BUFFER_P_AID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \ + value, 0x1ff, 0) +#define SET_TX_DESC_BUFFER_P_AID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1ff, 0) +#define GET_TX_DESC_BUFFER_P_AID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, \ + 0x1ff, 0) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xfff, 16) +#define SET_TX_DESC_BUFFER_SW_DEFINE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xfff, 16) +#define GET_TX_DESC_BUFFER_SW_DEFINE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \ + 0xfff, 16) +#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0x1, 9) +#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 9) +#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, 9) +#define SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0xf, 5) +#define SET_TX_DESC_BUFFER_CTRL_CNT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xf, 5) +#define GET_TX_DESC_BUFFER_CTRL_CNT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xf, 5) +#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \ + value, 0x1f, 0) +#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1f, 0) +#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1f, \ + 0) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3, 30) +#define SET_TX_DESC_BUFFER_PATH_MAPA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 30) +#define GET_TX_DESC_BUFFER_PATH_MAPA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \ + 30) +#define SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3, 28) +#define SET_TX_DESC_BUFFER_PATH_MAPB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 28) +#define GET_TX_DESC_BUFFER_PATH_MAPB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \ + 28) +#define SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3, 26) +#define SET_TX_DESC_BUFFER_PATH_MAPC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 26) +#define GET_TX_DESC_BUFFER_PATH_MAPC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \ + 26) +#define SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x3, 24) +#define SET_TX_DESC_BUFFER_PATH_MAPD_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 24) +#define GET_TX_DESC_BUFFER_PATH_MAPD(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \ + 24) +#define SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xf, 20) +#define SET_TX_DESC_BUFFER_ANTSEL_A_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 20) +#define GET_TX_DESC_BUFFER_ANTSEL_A(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, \ + 20) +#define SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xf, 16) +#define SET_TX_DESC_BUFFER_ANTSEL_B_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 16) +#define GET_TX_DESC_BUFFER_ANTSEL_B(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, \ + 16) +#define SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xf, 12) +#define SET_TX_DESC_BUFFER_ANTSEL_C_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 12) +#define GET_TX_DESC_BUFFER_ANTSEL_C(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, \ + 12) +#define SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xf, 8) +#define SET_TX_DESC_BUFFER_ANTSEL_D_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 8) +#define GET_TX_DESC_BUFFER_ANTSEL_D(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, 8) +#define SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0xf, 4) +#define SET_TX_DESC_BUFFER_NTX_PATH_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 4) +#define GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, 4) +#define SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x1, 3) +#define SET_TX_DESC_BUFFER_ANTLSEL_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 3) +#define GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, 3) +#define SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \ + value, 0x7, 0) +#define SET_TX_DESC_BUFFER_AMPDU_DENSITY_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x7, 0) +#define GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x7, 0) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x3, 30) +#define SET_TX_DESC_BUFFER_VCS_STBC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x3, 30) +#define GET_TX_DESC_BUFFER_VCS_STBC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x3, \ + 30) +#define SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x3, 28) +#define SET_TX_DESC_BUFFER_DATA_STBC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x3, 28) +#define GET_TX_DESC_BUFFER_DATA_STBC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x3, \ + 28) +#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xf, 24) +#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 24) +#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf, \ + 24) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 23) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 23) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \ + 23) +#define SET_TX_DESC_BUFFER_MHR_CP(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 22) +#define SET_TX_DESC_BUFFER_MHR_CP_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 22) +#define GET_TX_DESC_BUFFER_MHR_CP(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \ + 22) +#define SET_TX_DESC_BUFFER_SMH_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 21) +#define SET_TX_DESC_BUFFER_SMH_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 21) +#define GET_TX_DESC_BUFFER_SMH_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \ + 21) +#define SET_TX_DESC_BUFFER_RTSRATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1f, 16) +#define SET_TX_DESC_BUFFER_RTSRATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1f, 16) +#define GET_TX_DESC_BUFFER_RTSRATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1f, \ + 16) +#define SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0xff, 8) +#define SET_TX_DESC_BUFFER_SMH_CAM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 8) +#define GET_TX_DESC_BUFFER_SMH_CAM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \ + 8) +#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 7) +#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 7) +#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 7) +#define SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 6) +#define SET_TX_DESC_BUFFER_ARFR_HT_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 6) +#define GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 6) +#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 5) +#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 5) +#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 5) +#define SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 4) +#define SET_TX_DESC_BUFFER_ARFR_CCK_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 4) +#define GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 4) +#define SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 3) +#define SET_TX_DESC_BUFFER_RTS_SHORT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 3) +#define GET_TX_DESC_BUFFER_RTS_SHORT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 3) +#define SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 2) +#define SET_TX_DESC_BUFFER_DISDATAFB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 2) +#define GET_TX_DESC_BUFFER_DISDATAFB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 2) +#define SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 1) +#define SET_TX_DESC_BUFFER_DISRTSFB_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 1) +#define GET_TX_DESC_BUFFER_DISRTSFB(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 1) +#define SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \ + value, 0x1, 0) +#define SET_TX_DESC_BUFFER_EXT_EDCA_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 0) +#define GET_TX_DESC_BUFFER_EXT_EDCA(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 0) + +/*TXDESC_WORD10*/ + +#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0xff, 24) +#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 24) +#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \ + 0xff, 24) +#define SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 23) +#define SET_TX_DESC_BUFFER_SPECIAL_CW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 23) +#define GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 23) +#define SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 22) +#define SET_TX_DESC_BUFFER_RDG_NAV_EXT_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 22) +#define GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 22) +#define SET_TX_DESC_BUFFER_RAW(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 21) +#define SET_TX_DESC_BUFFER_RAW_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 21) +#define GET_TX_DESC_BUFFER_RAW(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 21) +#define SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1f, 16) +#define SET_TX_DESC_BUFFER_MAX_AGG_NUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1f, 16) +#define GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \ + 0x1f, 16) +#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0xff, 8) +#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 8) +#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \ + 0xff, 8) +#define SET_TX_DESC_BUFFER_GF(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 7) +#define SET_TX_DESC_BUFFER_GF_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 7) +#define GET_TX_DESC_BUFFER_GF(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 7) +#define SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 6) +#define SET_TX_DESC_BUFFER_MOREFRAG_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 6) +#define GET_TX_DESC_BUFFER_MOREFRAG(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 6) +#define SET_TX_DESC_BUFFER_NOACM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 5) +#define SET_TX_DESC_BUFFER_NOACM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 5) +#define GET_TX_DESC_BUFFER_NOACM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 5) +#define SET_TX_DESC_BUFFER_HTC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 4) +#define SET_TX_DESC_BUFFER_HTC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 4) +#define GET_TX_DESC_BUFFER_HTC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 4) +#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 3) +#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 3) +#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 3) +#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x1, 2) +#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 2) +#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \ + 2) +#define SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \ + value, 0x3, 0) +#define SET_TX_DESC_BUFFER_HW_SSN_SEL_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3, 0) +#define GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x3, \ + 0) + +/*TXDESC_WORD11*/ + +#define SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0xff, 24) +#define SET_TX_DESC_BUFFER_ADDR_CAM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xff, 24) +#define GET_TX_DESC_BUFFER_ADDR_CAM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, \ + 0xff, 24) +#define SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0xff, 16) +#define SET_TX_DESC_BUFFER_SND_TARGET_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xff, 16) +#define GET_TX_DESC_BUFFER_SND_TARGET(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, \ + 0xff, 16) +#define SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0x1, 15) +#define SET_TX_DESC_BUFFER_DATA_LDPC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0x1, 15) +#define GET_TX_DESC_BUFFER_DATA_LDPC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0x1, \ + 15) +#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0x1, 14) +#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0x1, 14) +#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0x1, \ + 14) +#define SET_TX_DESC_BUFFER_G_ID(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0x3f, 8) +#define SET_TX_DESC_BUFFER_G_ID_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0x3f, 8) +#define GET_TX_DESC_BUFFER_G_ID(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, \ + 0x3f, 8) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0xf, 4) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xf, 4) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0xf, \ + 4) +#define SET_TX_DESC_BUFFER_DATA_SC(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \ + value, 0xf, 0) +#define SET_TX_DESC_BUFFER_DATA_SC_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xf, 0) +#define GET_TX_DESC_BUFFER_DATA_SC(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0xf, \ + 0) + +/*TXDESC_WORD12*/ + +#define SET_TX_DESC_BUFFER_LEN1_L(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12, \ + value, 0x7f, 17) +#define SET_TX_DESC_BUFFER_LEN1_L_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword12, value, 0x7f, 17) +#define GET_TX_DESC_BUFFER_LEN1_L(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12, \ + 0x7f, 17) +#define SET_TX_DESC_BUFFER_LEN0(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12, \ + value, 0x1fff, 4) +#define SET_TX_DESC_BUFFER_LEN0_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword12, value, 0x1fff, 4) +#define GET_TX_DESC_BUFFER_LEN0(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12, \ + 0x1fff, 4) +#define SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12, \ + value, 0xf, 0) +#define SET_TX_DESC_BUFFER_PKT_NUM_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword12, value, 0xf, 0) +#define GET_TX_DESC_BUFFER_PKT_NUM(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12, 0xf, \ + 0) + +/*TXDESC_WORD13*/ + +#define SET_TX_DESC_BUFFER_LEN3(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13, \ + value, 0x1fff, 19) +#define SET_TX_DESC_BUFFER_LEN3_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword13, value, 0x1fff, 19) +#define GET_TX_DESC_BUFFER_LEN3(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13, \ + 0x1fff, 19) +#define SET_TX_DESC_BUFFER_LEN2(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13, \ + value, 0x1fff, 6) +#define SET_TX_DESC_BUFFER_LEN2_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword13, value, 0x1fff, 6) +#define GET_TX_DESC_BUFFER_LEN2(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13, \ + 0x1fff, 6) +#define SET_TX_DESC_BUFFER_LEN1_H(txdesc, value) \ + HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13, \ + value, 0x3f, 0) +#define SET_TX_DESC_BUFFER_LEN1_H_NO_CLR(txdesc, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc)->dword13, value, 0x3f, 0) +#define GET_TX_DESC_BUFFER_LEN1_H(txdesc) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13, \ + 0x3f, 0) + +#endif + +#endif diff --git a/hal/halmac/halmac_tx_desc_buffer_chip.h b/hal/halmac/halmac_tx_desc_buffer_chip.h new file mode 100644 index 0000000..a3e80ca --- /dev/null +++ b/hal/halmac/halmac_tx_desc_buffer_chip.h @@ -0,0 +1,509 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_BUFFER_CHIP_H_ +#define _HALMAC_TX_DESC_BUFFER_CHIP_H_ +#if (HALMAC_8814B_SUPPORT) + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RDG_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RDG_EN(txdesc) +#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc) \ + GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_AGG_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_AGG_EN(txdesc) +#define SET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc) +#define SET_TX_DESC_BUFFER_OFFSET_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_OFFSET(txdesc, value) +#define GET_TX_DESC_BUFFER_OFFSET_8814B(txdesc) \ + GET_TX_DESC_BUFFER_OFFSET(txdesc) +#define SET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc) + +/*TXDESC_WORD1*/ + +#define SET_TX_DESC_BUFFER_USERATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_USERATE(txdesc, value) +#define GET_TX_DESC_BUFFER_USERATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_USERATE(txdesc) +#define SET_TX_DESC_BUFFER_AMSDU_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_AMSDU(txdesc, value) +#define GET_TX_DESC_BUFFER_AMSDU_8814B(txdesc) GET_TX_DESC_BUFFER_AMSDU(txdesc) +#define SET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc) \ + GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc) +#define SET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc) \ + GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value) +#define GET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SW_SEQ(txdesc) +#define SET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DROP_ID(txdesc, value) +#define GET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DROP_ID(txdesc) +#define SET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MOREDATA(txdesc, value) +#define GET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MOREDATA(txdesc) +#define SET_TX_DESC_BUFFER_QSEL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_QSEL(txdesc, value) +#define GET_TX_DESC_BUFFER_QSEL_8814B(txdesc) GET_TX_DESC_BUFFER_QSEL(txdesc) +#define SET_TX_DESC_BUFFER_MACID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MACID(txdesc, value) +#define GET_TX_DESC_BUFFER_MACID_8814B(txdesc) GET_TX_DESC_BUFFER_MACID(txdesc) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CHK_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CHK_EN(txdesc) +#define SET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc) +#define SET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value) +#define GET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc) +#define SET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value) +#define GET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DMA_PRI(txdesc) +#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value) +#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc) +#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value) +#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc) +#define SET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value) +#define GET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc) +#define SET_TX_DESC_BUFFER_MBSSID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MBSSID(txdesc, value) +#define GET_TX_DESC_BUFFER_MBSSID_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MBSSID(txdesc) +#define SET_TX_DESC_BUFFER_BK_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_BK(txdesc, value) +#define GET_TX_DESC_BUFFER_BK_8814B(txdesc) GET_TX_DESC_BUFFER_BK(txdesc) +#define SET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value) +#define GET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TRY_RATE(txdesc) +#define SET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_BW(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_BW(txdesc) +#define SET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_SHORT(txdesc) +#define SET_TX_DESC_BUFFER_DATARATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATARATE(txdesc, value) +#define GET_TX_DESC_BUFFER_DATARATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATARATE(txdesc) +#define SET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TXBF_PATH(txdesc) +#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc) \ + GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc) +#define SET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTS_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTS_EN(txdesc) +#define SET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value) +#define GET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CTS2SELF(txdesc) +#define SET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc) +#define SET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc) +#define SET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc) \ + GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc) +#define SET_TX_DESC_BUFFER_BMC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_BMC(txdesc, value) +#define GET_TX_DESC_BUFFER_BMC_8814B(txdesc) GET_TX_DESC_BUFFER_BMC(txdesc) +#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc) \ + GET_TX_DESC_BUFFER_HW_AES_IV(txdesc) +#define SET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_BT_NULL(txdesc, value) +#define GET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc) \ + GET_TX_DESC_BUFFER_BT_NULL(txdesc) +#define SET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc) \ + GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc) +#define SET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SECTYPE(txdesc, value) +#define GET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SECTYPE(txdesc) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_POLLUTED(txdesc, value) +#define GET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc) \ + GET_TX_DESC_BUFFER_POLLUTED(txdesc) +#define SET_TX_DESC_BUFFER_NULL_1_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NULL_1(txdesc, value) +#define GET_TX_DESC_BUFFER_NULL_1_8814B(txdesc) \ + GET_TX_DESC_BUFFER_NULL_1(txdesc) +#define SET_TX_DESC_BUFFER_NULL_0_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NULL_0(txdesc, value) +#define GET_TX_DESC_BUFFER_NULL_0_8814B(txdesc) \ + GET_TX_DESC_BUFFER_NULL_0(txdesc) +#define SET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TRI_FRAME(txdesc) +#define SET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value) +#define GET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SPE_RPT(txdesc) +#define SET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_FTM_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_FTM_EN(txdesc) +#define SET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value) +#define GET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MU_DATARATE(txdesc) +#define SET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value) +#define GET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CCA_RTS(txdesc) +#define SET_TX_DESC_BUFFER_NDPA_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NDPA(txdesc, value) +#define GET_TX_DESC_BUFFER_NDPA_8814B(txdesc) GET_TX_DESC_BUFFER_NDPA(txdesc) +#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value) +#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc) +#define SET_TX_DESC_BUFFER_P_AID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_P_AID(txdesc, value) +#define GET_TX_DESC_BUFFER_P_AID_8814B(txdesc) GET_TX_DESC_BUFFER_P_AID(txdesc) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SW_DEFINE(txdesc) +#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value) +#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc) +#define SET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value) +#define GET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_CTRL_CNT(txdesc) +#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value) +#define GET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PATH_MAPA(txdesc) +#define SET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value) +#define GET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PATH_MAPB(txdesc) +#define SET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value) +#define GET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PATH_MAPC(txdesc) +#define SET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value) +#define GET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PATH_MAPD(txdesc) +#define SET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ANTSEL_A(txdesc) +#define SET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ANTSEL_B(txdesc) +#define SET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ANTSEL_C(txdesc) +#define SET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ANTSEL_D(txdesc) +#define SET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc) +#define SET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc) +#define SET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc) \ + GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value) +#define GET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_VCS_STBC(txdesc) +#define SET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_STBC(txdesc) +#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc) +#define SET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MHR_CP(txdesc, value) +#define GET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MHR_CP(txdesc) +#define SET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SMH_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SMH_EN(txdesc) +#define SET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTSRATE(txdesc, value) +#define GET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTSRATE(txdesc) +#define SET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value) +#define GET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SMH_CAM(txdesc) +#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value) +#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc) +#define SET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc) +#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc) +#define SET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc) +#define SET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RTS_SHORT(txdesc) +#define SET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value) +#define GET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DISDATAFB(txdesc) +#define SET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value) +#define GET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DISRTSFB(txdesc) +#define SET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value) +#define GET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc) \ + GET_TX_DESC_BUFFER_EXT_EDCA(txdesc) + +/*TXDESC_WORD10*/ + +#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc) \ + GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value) +#define GET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc) +#define SET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value) +#define GET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc) \ + GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc) +#define SET_TX_DESC_BUFFER_RAW_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_RAW(txdesc, value) +#define GET_TX_DESC_BUFFER_RAW_8814B(txdesc) GET_TX_DESC_BUFFER_RAW(txdesc) +#define SET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc) \ + GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_BUFFER_GF_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_GF(txdesc, value) +#define GET_TX_DESC_BUFFER_GF_8814B(txdesc) GET_TX_DESC_BUFFER_GF(txdesc) +#define SET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value) +#define GET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc) \ + GET_TX_DESC_BUFFER_MOREFRAG(txdesc) +#define SET_TX_DESC_BUFFER_NOACM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_NOACM(txdesc, value) +#define GET_TX_DESC_BUFFER_NOACM_8814B(txdesc) GET_TX_DESC_BUFFER_NOACM(txdesc) +#define SET_TX_DESC_BUFFER_HTC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_HTC(txdesc, value) +#define GET_TX_DESC_BUFFER_HTC_8814B(txdesc) GET_TX_DESC_BUFFER_HTC(txdesc) +#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value) +#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc) \ + GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc) +#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc) \ + GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc) + +/*TXDESC_WORD11*/ + +#define SET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value) +#define GET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_ADDR_CAM(txdesc) +#define SET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value) +#define GET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SND_TARGET(txdesc) +#define SET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_LDPC(txdesc) +#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc) \ + GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_BUFFER_G_ID_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_G_ID(txdesc, value) +#define GET_TX_DESC_BUFFER_G_ID_8814B(txdesc) GET_TX_DESC_BUFFER_G_ID(txdesc) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc) +#define SET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_DATA_SC(txdesc, value) +#define GET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc) \ + GET_TX_DESC_BUFFER_DATA_SC(txdesc) + +/*TXDESC_WORD12*/ + +#define SET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LEN1_L(txdesc, value) +#define GET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc) \ + GET_TX_DESC_BUFFER_LEN1_L(txdesc) +#define SET_TX_DESC_BUFFER_LEN0_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LEN0(txdesc, value) +#define GET_TX_DESC_BUFFER_LEN0_8814B(txdesc) GET_TX_DESC_BUFFER_LEN0(txdesc) +#define SET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value) +#define GET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc) \ + GET_TX_DESC_BUFFER_PKT_NUM(txdesc) + +/*TXDESC_WORD13*/ + +#define SET_TX_DESC_BUFFER_LEN3_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LEN3(txdesc, value) +#define GET_TX_DESC_BUFFER_LEN3_8814B(txdesc) GET_TX_DESC_BUFFER_LEN3(txdesc) +#define SET_TX_DESC_BUFFER_LEN2_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LEN2(txdesc, value) +#define GET_TX_DESC_BUFFER_LEN2_8814B(txdesc) GET_TX_DESC_BUFFER_LEN2(txdesc) +#define SET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc, value) \ + SET_TX_DESC_BUFFER_LEN1_H(txdesc, value) +#define GET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc) \ + GET_TX_DESC_BUFFER_LEN1_H(txdesc) + +#endif + +#endif diff --git a/hal/halmac/halmac_tx_desc_buffer_nic.h b/hal/halmac/halmac_tx_desc_buffer_nic.h new file mode 100644 index 0000000..6274102 --- /dev/null +++ b/hal/halmac/halmac_tx_desc_buffer_nic.h @@ -0,0 +1,491 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_BUFFER_NIC_H_ +#define _HALMAC_TX_DESC_BUFFER_NIC_H_ +#if (HALMAC_8814B_SUPPORT) + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_BUFFER_RDG_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value) +#define GET_TX_DESC_BUFFER_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1) +#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value) +#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1) +#define SET_TX_DESC_BUFFER_AGG_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value) +#define GET_TX_DESC_BUFFER_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1) +#define SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value) +#define GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5) +#define SET_TX_DESC_BUFFER_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value) +#define GET_TX_DESC_BUFFER_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8) +#define SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value) +#define GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16) + +/*TXDESC_WORD1*/ + +#define SET_TX_DESC_BUFFER_USERATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value) +#define GET_TX_DESC_BUFFER_USERATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1) +#define SET_TX_DESC_BUFFER_AMSDU(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value) +#define GET_TX_DESC_BUFFER_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1) +#define SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value) +#define GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1) +#define SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 28, 1, value) +#define GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 28, 1) +#define SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 12, value) +#define GET_TX_DESC_BUFFER_SW_SEQ(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 12) +#define SET_TX_DESC_BUFFER_DROP_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 2, value) +#define GET_TX_DESC_BUFFER_DROP_ID(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 14, 2) +#define SET_TX_DESC_BUFFER_MOREDATA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value) +#define GET_TX_DESC_BUFFER_MOREDATA(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1) +#define SET_TX_DESC_BUFFER_QSEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value) +#define GET_TX_DESC_BUFFER_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5) +#define SET_TX_DESC_BUFFER_MACID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 8, value) +#define GET_TX_DESC_BUFFER_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 8) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_BUFFER_CHK_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value) +#define GET_TX_DESC_BUFFER_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1) +#define SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value) +#define GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1) +#define SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 2, value) +#define GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 28, 2) +#define SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value) +#define GET_TX_DESC_BUFFER_DMA_PRI(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1) +#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value) +#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3) +#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value) +#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8) +#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value) +#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value) +#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15) +#define SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value) +#define GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5) +#define SET_TX_DESC_BUFFER_MBSSID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 7, 4, value) +#define GET_TX_DESC_BUFFER_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 7, 4) +#define SET_TX_DESC_BUFFER_BK(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 1, value) +#define GET_TX_DESC_BUFFER_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 1) +#define SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value) +#define GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 26, 1, value) +#define GET_TX_DESC_BUFFER_TRY_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 26, 1) +#define SET_TX_DESC_BUFFER_DATA_BW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 2, value) +#define GET_TX_DESC_BUFFER_DATA_BW(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 24, 2) +#define SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 23, 1, value) +#define GET_TX_DESC_BUFFER_DATA_SHORT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 23, 1) +#define SET_TX_DESC_BUFFER_DATARATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 16, 7, value) +#define GET_TX_DESC_BUFFER_DATARATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 16, 7) +#define SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 11, 1, value) +#define GET_TX_DESC_BUFFER_TXBF_PATH(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 11, 1) +#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 11, value) +#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 0, 11) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value) +#define GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1) +#define SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value) +#define GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1) +#define SET_TX_DESC_BUFFER_RTS_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 29, 1, value) +#define GET_TX_DESC_BUFFER_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 29, 1) +#define SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 1, value) +#define GET_TX_DESC_BUFFER_CTS2SELF(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 1) +#define SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value) +#define GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4) +#define SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 16, 8, value) +#define GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 16, 8) +#define SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 15, 1, value) +#define GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 15, 1) +#define SET_TX_DESC_BUFFER_BMC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 14, 1, value) +#define GET_TX_DESC_BUFFER_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 14, 1) +#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 6, value) +#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 8, 6) +#define SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value) +#define GET_TX_DESC_BUFFER_HW_AES_IV(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1) +#define SET_TX_DESC_BUFFER_BT_NULL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 3, 1, value) +#define GET_TX_DESC_BUFFER_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 3, 1) +#define SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 2, 1, value) +#define GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 2, 1) +#define SET_TX_DESC_BUFFER_SECTYPE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 2, value) +#define GET_TX_DESC_BUFFER_SECTYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 2) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 29, 3, value) +#define GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 29, 3) +#define SET_TX_DESC_BUFFER_POLLUTED(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 1, value) +#define GET_TX_DESC_BUFFER_POLLUTED(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 1) +#define SET_TX_DESC_BUFFER_NULL_1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 27, 1, value) +#define GET_TX_DESC_BUFFER_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 27, 1) +#define SET_TX_DESC_BUFFER_NULL_0(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 1, value) +#define GET_TX_DESC_BUFFER_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 1) +#define SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 25, 1, value) +#define GET_TX_DESC_BUFFER_TRI_FRAME(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 25, 1) +#define SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 1, value) +#define GET_TX_DESC_BUFFER_SPE_RPT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 1) +#define SET_TX_DESC_BUFFER_FTM_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 23, 1, value) +#define GET_TX_DESC_BUFFER_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 23, 1) +#define SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 7, value) +#define GET_TX_DESC_BUFFER_MU_DATARATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 7) +#define SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 14, 2, value) +#define GET_TX_DESC_BUFFER_CCA_RTS(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 14, 2) +#define SET_TX_DESC_BUFFER_NDPA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 2, value) +#define GET_TX_DESC_BUFFER_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 2) +#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 9, 2, value) +#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x18, 9, 2) +#define SET_TX_DESC_BUFFER_P_AID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 9, value) +#define GET_TX_DESC_BUFFER_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 9) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 12, value) +#define GET_TX_DESC_BUFFER_SW_DEFINE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 12) +#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 9, 1, value) +#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 9, 1) +#define SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 5, 4, value) +#define GET_TX_DESC_BUFFER_CTRL_CNT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 5, 4) +#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 5, value) +#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 5) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 2, value) +#define GET_TX_DESC_BUFFER_PATH_MAPA(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 30, 2) +#define SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 2, value) +#define GET_TX_DESC_BUFFER_PATH_MAPB(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 28, 2) +#define SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 2, value) +#define GET_TX_DESC_BUFFER_PATH_MAPC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 26, 2) +#define SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 2, value) +#define GET_TX_DESC_BUFFER_PATH_MAPD(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 2) +#define SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 20, 4, value) +#define GET_TX_DESC_BUFFER_ANTSEL_A(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 20, 4) +#define SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 4, value) +#define GET_TX_DESC_BUFFER_ANTSEL_B(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 4) +#define SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 12, 4, value) +#define GET_TX_DESC_BUFFER_ANTSEL_C(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 12, 4) +#define SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 4, value) +#define GET_TX_DESC_BUFFER_ANTSEL_D(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 4) +#define SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 4, 4, value) +#define GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 4, 4) +#define SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 3, 1, value) +#define GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 3, 1) +#define SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 3, value) +#define GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 3) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 30, 2, value) +#define GET_TX_DESC_BUFFER_VCS_STBC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 30, 2) +#define SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 2, value) +#define GET_TX_DESC_BUFFER_DATA_STBC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 28, 2) +#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value) +#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 23, 1, value) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 23, 1) +#define SET_TX_DESC_BUFFER_MHR_CP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 22, 1, value) +#define GET_TX_DESC_BUFFER_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 22, 1) +#define SET_TX_DESC_BUFFER_SMH_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 21, 1, value) +#define GET_TX_DESC_BUFFER_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 21, 1) +#define SET_TX_DESC_BUFFER_RTSRATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 16, 5, value) +#define GET_TX_DESC_BUFFER_RTSRATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 16, 5) +#define SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 8, 8, value) +#define GET_TX_DESC_BUFFER_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 8, 8) +#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 7, 1, value) +#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 7, 1) +#define SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 6, 1, value) +#define GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 6, 1) +#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 5, 1, value) +#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 5, 1) +#define SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 4, 1, value) +#define GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 4, 1) +#define SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 3, 1, value) +#define GET_TX_DESC_BUFFER_RTS_SHORT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 3, 1) +#define SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 2, 1, value) +#define GET_TX_DESC_BUFFER_DISDATAFB(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 2, 1) +#define SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 1, 1, value) +#define GET_TX_DESC_BUFFER_DISRTSFB(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 1, 1) +#define SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 1, value) +#define GET_TX_DESC_BUFFER_EXT_EDCA(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 1) + +/*TXDESC_WORD10*/ + +#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 24, 8, value) +#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 24, 8) +#define SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 23, 1, value) +#define GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 23, 1) +#define SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 22, 1, value) +#define GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 22, 1) +#define SET_TX_DESC_BUFFER_RAW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 21, 1, value) +#define GET_TX_DESC_BUFFER_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 21, 1) +#define SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 16, 5, value) +#define GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 16, 5) +#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value) +#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8) +#define SET_TX_DESC_BUFFER_GF(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 7, 1, value) +#define GET_TX_DESC_BUFFER_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 7, 1) +#define SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 6, 1, value) +#define GET_TX_DESC_BUFFER_MOREFRAG(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 6, 1) +#define SET_TX_DESC_BUFFER_NOACM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 5, 1, value) +#define GET_TX_DESC_BUFFER_NOACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 5, 1) +#define SET_TX_DESC_BUFFER_HTC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 1, value) +#define GET_TX_DESC_BUFFER_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 1) +#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 3, 1, value) +#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 3, 1) +#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 2, 1, value) +#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 2, 1) +#define SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value) +#define GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2) + +/*TXDESC_WORD11*/ + +#define SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 24, 8, value) +#define GET_TX_DESC_BUFFER_ADDR_CAM(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x2C, 24, 8) +#define SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 16, 8, value) +#define GET_TX_DESC_BUFFER_SND_TARGET(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x2C, 16, 8) +#define SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 15, 1, value) +#define GET_TX_DESC_BUFFER_DATA_LDPC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x2C, 15, 1) +#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 14, 1, value) +#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x2C, 14, 1) +#define SET_TX_DESC_BUFFER_G_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 8, 6, value) +#define GET_TX_DESC_BUFFER_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 8, 6) +#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 4, 4, value) +#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x2C, 4, 4) +#define SET_TX_DESC_BUFFER_DATA_SC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 0, 4, value) +#define GET_TX_DESC_BUFFER_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 0, 4) + +/*TXDESC_WORD12*/ + +#define SET_TX_DESC_BUFFER_LEN1_L(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 17, 7, value) +#define GET_TX_DESC_BUFFER_LEN1_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 17, 7) +#define SET_TX_DESC_BUFFER_LEN0(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 4, 13, value) +#define GET_TX_DESC_BUFFER_LEN0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 4, 13) +#define SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 0, 4, value) +#define GET_TX_DESC_BUFFER_PKT_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 0, 4) + +/*TXDESC_WORD13*/ + +#define SET_TX_DESC_BUFFER_LEN3(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 19, 13, value) +#define GET_TX_DESC_BUFFER_LEN3(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 19, 13) +#define SET_TX_DESC_BUFFER_LEN2(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 6, 13, value) +#define GET_TX_DESC_BUFFER_LEN2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 6, 13) +#define SET_TX_DESC_BUFFER_LEN1_H(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 0, 6, value) +#define GET_TX_DESC_BUFFER_LEN1_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 0, 6) + +#endif + +#endif diff --git a/hal/halmac/halmac_tx_desc_chip.h b/hal/halmac/halmac_tx_desc_chip.h index d15b6cf..8f01ab7 100644 --- a/hal/halmac/halmac_tx_desc_chip.h +++ b/hal/halmac/halmac_tx_desc_chip.h @@ -1,518 +1,759 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TX_DESC_CHIP_H_ #define _HALMAC_TX_DESC_CHIP_H_ #if (HALMAC_8814A_SUPPORT) /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc) -#define SET_TX_DESC_GF_8814A(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value) -#define GET_TX_DESC_GF_8814A(__pTxDesc) GET_TX_DESC_GF(__pTxDesc) -#define SET_TX_DESC_NO_ACM_8814A(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value) -#define GET_TX_DESC_NO_ACM_8814A(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc) -#define SET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) -#define SET_TX_DESC_LS_8814A(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value) -#define GET_TX_DESC_LS_8814A(__pTxDesc) GET_TX_DESC_LS(__pTxDesc) -#define SET_TX_DESC_HTC_8814A(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value) -#define GET_TX_DESC_HTC_8814A(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc) -#define SET_TX_DESC_BMC_8814A(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value) -#define GET_TX_DESC_BMC_8814A(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc) -#define SET_TX_DESC_OFFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_OFFSET_8814A(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc) -#define SET_TX_DESC_TXPKTSIZE_8814A(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TXPKTSIZE_8814A(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc) - -/*TXDESC_WORD1*/ - -#define SET_TX_DESC_MOREDATA_8814A(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value) -#define GET_TX_DESC_MOREDATA_8814A(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc) -#define SET_TX_DESC_PKT_OFFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_PKT_OFFSET_8814A(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc) -#define SET_TX_DESC_SEC_TYPE_8814A(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) -#define GET_TX_DESC_SEC_TYPE_8814A(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc) -#define SET_TX_DESC_EN_DESC_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) -#define GET_TX_DESC_EN_DESC_ID_8814A(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc) -#define SET_TX_DESC_RATE_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value) -#define GET_TX_DESC_RATE_ID_8814A(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc) -#define SET_TX_DESC_PIFS_8814A(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value) -#define GET_TX_DESC_PIFS_8814A(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc) -#define SET_TX_DESC_LSIG_TXOP_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN_8814A(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) -#define SET_TX_DESC_RD_NAV_EXT_8814A(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) -#define GET_TX_DESC_RD_NAV_EXT_8814A(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc) -#define SET_TX_DESC_QSEL_8814A(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value) -#define GET_TX_DESC_QSEL_8814A(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc) -#define SET_TX_DESC_MACID_8814A(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value) -#define GET_TX_DESC_MACID_8814A(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc) +#define SET_TX_DESC_DISQSELSEQ_8814A(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8814A(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8814A(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8814A(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8814A(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8814A(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8814A(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8814A(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8814A(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8814A(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8814A(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8814A(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8814A(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8814A(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8814A(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8814A(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8814A(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8814A(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_MOREDATA_8814A(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8814A(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8814A(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8814A(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8814A(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8814A(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8814A(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8814A(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8814A(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8814A(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8814A(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8814A(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8814A(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8814A(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8814A(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8814A(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8814A(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8814A(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8814A(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8814A(txdesc) GET_TX_DESC_MACID(txdesc) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV_8814A(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) -#define GET_TX_DESC_HW_AES_IV_8814A(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc) -#define SET_TX_DESC_G_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value) -#define GET_TX_DESC_G_ID_8814A(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc) -#define SET_TX_DESC_BT_NULL_8814A(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value) -#define GET_TX_DESC_BT_NULL_8814A(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc) -#define SET_TX_DESC_AMPDU_DENSITY_8814A(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_DENSITY_8814A(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) -#define SET_TX_DESC_SPE_RPT_8814A(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) -#define GET_TX_DESC_SPE_RPT_8814A(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc) -#define SET_TX_DESC_RAW_8814A(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value) -#define GET_TX_DESC_RAW_8814A(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc) -#define SET_TX_DESC_MOREFRAG_8814A(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) -#define GET_TX_DESC_MOREFRAG_8814A(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc) -#define SET_TX_DESC_BK_8814A(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value) -#define GET_TX_DESC_BK_8814A(__pTxDesc) GET_TX_DESC_BK(__pTxDesc) -#define SET_TX_DESC_NULL_1_8814A(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_1_8814A(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc) -#define SET_TX_DESC_NULL_0_8814A(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_0_8814A(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc) -#define SET_TX_DESC_RDG_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RDG_EN_8814A(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc) -#define SET_TX_DESC_AGG_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AGG_EN_8814A(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc) -#define SET_TX_DESC_CCA_RTS_8814A(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) -#define GET_TX_DESC_CCA_RTS_8814A(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc) -#define SET_TX_DESC_P_AID_8814A(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value) -#define GET_TX_DESC_P_AID_8814A(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc) +#define SET_TX_DESC_HW_AES_IV_8814A(txdesc, value) \ + SET_TX_DESC_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8814A(txdesc) GET_TX_DESC_HW_AES_IV(txdesc) +#define SET_TX_DESC_G_ID_8814A(txdesc, value) SET_TX_DESC_G_ID(txdesc, value) +#define GET_TX_DESC_G_ID_8814A(txdesc) GET_TX_DESC_G_ID(txdesc) +#define SET_TX_DESC_BT_NULL_8814A(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8814A(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8814A(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8814A(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8814A(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8814A(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8814A(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8814A(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8814A(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8814A(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8814A(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8814A(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8814A(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8814A(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8814A(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8814A(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8814A(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8814A(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8814A(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8814A(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8814A(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8814A(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_P_AID_8814A(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8814A(txdesc) GET_TX_DESC_P_AID(txdesc) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME_8814A(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) -#define SET_TX_DESC_NDPA_8814A(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value) -#define GET_TX_DESC_NDPA_8814A(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc) -#define SET_TX_DESC_MAX_AGG_NUM_8814A(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_MAX_AGG_NUM_8814A(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) -#define SET_TX_DESC_USE_MAX_TIME_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN_8814A(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) -#define SET_TX_DESC_NAVUSEHDR_8814A(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) -#define GET_TX_DESC_NAVUSEHDR_8814A(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc) -#define SET_TX_DESC_CHK_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value) -#define GET_TX_DESC_CHK_EN_8814A(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc) -#define SET_TX_DESC_HW_RTS_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_HW_RTS_EN_8814A(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSEN_8814A(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value) -#define GET_TX_DESC_RTSEN_8814A(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc) -#define SET_TX_DESC_CTS2SELF_8814A(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) -#define GET_TX_DESC_CTS2SELF_8814A(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc) -#define SET_TX_DESC_DISDATAFB_8814A(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISDATAFB_8814A(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc) -#define SET_TX_DESC_DISRTSFB_8814A(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISRTSFB_8814A(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc) -#define SET_TX_DESC_USE_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_USE_RATE_8814A(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc) -#define SET_TX_DESC_HW_SSN_SEL_8814A(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_HW_SSN_SEL_8814A(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc) -#define SET_TX_DESC_WHEADER_LEN_8814A(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_WHEADER_LEN_8814A(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc) +#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8814A(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8814A(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8814A(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8814A(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8814A(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8814A(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8814A(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8814A(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8814A(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8814A(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8814A(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8814A(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8814A(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8814A(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8814A(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8814A(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8814A(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8814A(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8814A(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8814A(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8814A(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8814A(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8814A(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8814A(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8814A(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8814A(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8814A(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) /*TXDESC_WORD4*/ -#define SET_TX_DESC_PCTS_MASK_IDX_8814A(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX_8814A(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) -#define SET_TX_DESC_PCTS_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_EN_8814A(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSRATE_8814A(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTSRATE_8814A(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT_8814A(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) -#define SET_TX_DESC_RTY_LMT_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RTY_LMT_EN_8814A(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_TRY_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_TRY_RATE_8814A(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc) -#define SET_TX_DESC_DATARATE_8814A(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATARATE_8814A(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc) +#define SET_TX_DESC_PCTS_MASK_IDX_8814A(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8814A(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8814A(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8814A(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8814A(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8814A(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8814A(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8814A(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8814A(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8814A(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8814A(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8814A(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8814A(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8814A(txdesc) GET_TX_DESC_DATARATE(txdesc) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED_8814A(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value) -#define GET_TX_DESC_POLLUTED_8814A(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc) -#define SET_TX_DESC_TXPWR_OFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) -#define GET_TX_DESC_TXPWR_OFSET_8814A(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc) -#define SET_TX_DESC_TX_ANT_8814A(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value) -#define GET_TX_DESC_TX_ANT_8814A(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc) -#define SET_TX_DESC_PORT_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value) -#define GET_TX_DESC_PORT_ID_8814A(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc) -#define SET_TX_DESC_SIGNALING_TAPKT_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SIGNALING_TAPKT_EN_8814A(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_SC_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SC_8814A(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc) -#define SET_TX_DESC_RTS_SHORT_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SHORT_8814A(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc) -#define SET_TX_DESC_VCS_STBC_8814A(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_VCS_STBC_8814A(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_STBC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_STBC_8814A(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_LDPC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_LDPC_8814A(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc) -#define SET_TX_DESC_DATA_BW_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_BW_8814A(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc) -#define SET_TX_DESC_DATA_SHORT_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SHORT_8814A(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc) -#define SET_TX_DESC_DATA_SC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SC_8814A(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc) +#define SET_TX_DESC_POLLUTED_8814A(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8814A(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_8814A(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_8814A(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc) +#define SET_TX_DESC_TX_ANT_8814A(txdesc, value) \ + SET_TX_DESC_TX_ANT(txdesc, value) +#define GET_TX_DESC_TX_ANT_8814A(txdesc) GET_TX_DESC_TX_ANT(txdesc) +#define SET_TX_DESC_PORT_ID_8814A(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8814A(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8814A(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8814A(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_RTS_SC_8814A(txdesc, value) \ + SET_TX_DESC_RTS_SC(txdesc, value) +#define GET_TX_DESC_RTS_SC_8814A(txdesc) GET_TX_DESC_RTS_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8814A(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8814A(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8814A(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8814A(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8814A(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8814A(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8814A(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8814A(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8814A(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8814A(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8814A(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8814A(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8814A(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8814A(txdesc) GET_TX_DESC_DATA_SC(txdesc) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_D_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc) -#define SET_TX_DESC_ANT_MAPD_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPD_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc) -#define SET_TX_DESC_ANT_MAPC_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPC_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc) -#define SET_TX_DESC_ANT_MAPB_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPB_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc) -#define SET_TX_DESC_ANT_MAPA_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPA_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc) -#define SET_TX_DESC_ANTSEL_C_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_C_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc) -#define SET_TX_DESC_ANTSEL_B_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_B_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc) -#define SET_TX_DESC_ANTSEL_A_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_A_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc) -#define SET_TX_DESC_MBSSID_8814A(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value) -#define GET_TX_DESC_MBSSID_8814A(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc) -#define SET_TX_DESC_SW_DEFINE_8814A(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) -#define GET_TX_DESC_SW_DEFINE_8814A(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc) +#define SET_TX_DESC_ANTSEL_D_8814A(txdesc, value) \ + SET_TX_DESC_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_ANTSEL_D_8814A(txdesc) GET_TX_DESC_ANTSEL_D(txdesc) +#define SET_TX_DESC_ANT_MAPD_8814A(txdesc, value) \ + SET_TX_DESC_ANT_MAPD(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8814A(txdesc) GET_TX_DESC_ANT_MAPD(txdesc) +#define SET_TX_DESC_ANT_MAPC_8814A(txdesc, value) \ + SET_TX_DESC_ANT_MAPC(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8814A(txdesc) GET_TX_DESC_ANT_MAPC(txdesc) +#define SET_TX_DESC_ANT_MAPB_8814A(txdesc, value) \ + SET_TX_DESC_ANT_MAPB(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8814A(txdesc) GET_TX_DESC_ANT_MAPB(txdesc) +#define SET_TX_DESC_ANT_MAPA_8814A(txdesc, value) \ + SET_TX_DESC_ANT_MAPA(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8814A(txdesc) GET_TX_DESC_ANT_MAPA(txdesc) +#define SET_TX_DESC_ANTSEL_C_8814A(txdesc, value) \ + SET_TX_DESC_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8814A(txdesc) GET_TX_DESC_ANTSEL_C(txdesc) +#define SET_TX_DESC_ANTSEL_B_8814A(txdesc, value) \ + SET_TX_DESC_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8814A(txdesc) GET_TX_DESC_ANTSEL_B(txdesc) +#define SET_TX_DESC_ANTSEL_A_8814A(txdesc, value) \ + SET_TX_DESC_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8814A(txdesc) GET_TX_DESC_ANTSEL_A(txdesc) +#define SET_TX_DESC_MBSSID_8814A(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8814A(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SW_DEFINE_8814A(txdesc, value) \ + SET_TX_DESC_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_SW_DEFINE_8814A(txdesc) GET_TX_DESC_SW_DEFINE(txdesc) /*TXDESC_WORD7*/ -#define SET_TX_DESC_DMA_TXAGG_NUM_8814A(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM_8814A(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) -#define SET_TX_DESC_FINAL_DATA_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_FINAL_DATA_RATE_8814A(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) -#define SET_TX_DESC_NTX_MAP_8814A(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) -#define GET_TX_DESC_NTX_MAP_8814A(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc) -#define SET_TX_DESC_TX_BUFF_SIZE_8814A(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE_8814A(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) -#define SET_TX_DESC_TXDESC_CHECKSUM_8814A(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM_8814A(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) -#define SET_TX_DESC_TIMESTAMP_8814A(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) -#define GET_TX_DESC_TIMESTAMP_8814A(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8814A(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8814A(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8814A(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8814A(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8814A(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8814A(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8814A(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8814A(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8814A(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8814A(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8814A(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8814A(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) /*TXDESC_WORD8*/ -#define SET_TX_DESC_TXWIFI_CP_8814A(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) -#define GET_TX_DESC_TXWIFI_CP_8814A(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc) -#define SET_TX_DESC_MAC_CP_8814A(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value) -#define GET_TX_DESC_MAC_CP_8814A(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc) -#define SET_TX_DESC_STW_PKTRE_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_PKTRE_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RB_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RB_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RATE_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RATE_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_ANT_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_ANT_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc) -#define SET_TX_DESC_STW_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value) -#define GET_TX_DESC_STW_EN_8814A(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc) -#define SET_TX_DESC_SMH_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SMH_EN_8814A(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc) -#define SET_TX_DESC_TAILPAGE_L_8814A(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_L_8814A(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc) -#define SET_TX_DESC_SDIO_DMASEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SDIO_DMASEQ_8814A(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_L_8814A(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L_8814A(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) -#define SET_TX_DESC_EN_HWSEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWSEQ_8814A(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc) -#define SET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) -#define SET_TX_DESC_DATA_RC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RC_8814A(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc) -#define SET_TX_DESC_BAR_RTY_TH_8814A(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) -#define GET_TX_DESC_BAR_RTY_TH_8814A(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc) -#define SET_TX_DESC_RTS_RC_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RC_8814A(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc) +#define SET_TX_DESC_TXWIFI_CP_8814A(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8814A(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8814A(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8814A(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8814A(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8814A(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8814A(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8814A(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8814A(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8814A(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8814A(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8814A(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8814A(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8814A(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8814A(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8814A(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8814A(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8814A(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8814A(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8814A(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8814A(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8814A(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8814A(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8814A(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8814A(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8814A(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8814A(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8814A(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8814A(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8814A(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8814A(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8814A(txdesc) GET_TX_DESC_RTS_RC(txdesc) /*TXDESC_WORD9*/ -#define SET_TX_DESC_TAILPAGE_H_8814A(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_H_8814A(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_H_8814A(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_H_8814A(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) -#define SET_TX_DESC_SW_SEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SW_SEQ_8814A(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc) -#define SET_TX_DESC_TXBF_PATH_8814A(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) -#define GET_TX_DESC_TXBF_PATH_8814A(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc) -#define SET_TX_DESC_PADDING_LEN_8814A(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_PADDING_LEN_8814A(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) +#define SET_TX_DESC_TAILPAGE_H_8814A(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8814A(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8814A(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8814A(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8814A(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8814A(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8814A(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8814A(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8814A(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8814A(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) /*WORD10*/ - #endif #if (HALMAC_8822B_SUPPORT) /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_DISQSELSEQ_8822B(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc) -#define SET_TX_DESC_GF_8822B(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value) -#define GET_TX_DESC_GF_8822B(__pTxDesc) GET_TX_DESC_GF(__pTxDesc) -#define SET_TX_DESC_NO_ACM_8822B(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value) -#define GET_TX_DESC_NO_ACM_8822B(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc) -#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__pTxDesc, __Value) SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) -#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__pTxDesc) GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) -#define SET_TX_DESC_AMSDU_PAD_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AMSDU_PAD_EN_8822B(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) -#define SET_TX_DESC_LS_8822B(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value) -#define GET_TX_DESC_LS_8822B(__pTxDesc) GET_TX_DESC_LS(__pTxDesc) -#define SET_TX_DESC_HTC_8822B(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value) -#define GET_TX_DESC_HTC_8822B(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc) -#define SET_TX_DESC_BMC_8822B(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value) -#define GET_TX_DESC_BMC_8822B(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc) -#define SET_TX_DESC_OFFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_OFFSET_8822B(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc) -#define SET_TX_DESC_TXPKTSIZE_8822B(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TXPKTSIZE_8822B(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc) - -/*TXDESC_WORD1*/ - -#define SET_TX_DESC_MOREDATA_8822B(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value) -#define GET_TX_DESC_MOREDATA_8822B(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc) -#define SET_TX_DESC_PKT_OFFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_PKT_OFFSET_8822B(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc) -#define SET_TX_DESC_SEC_TYPE_8822B(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) -#define GET_TX_DESC_SEC_TYPE_8822B(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc) -#define SET_TX_DESC_EN_DESC_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) -#define GET_TX_DESC_EN_DESC_ID_8822B(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc) -#define SET_TX_DESC_RATE_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value) -#define GET_TX_DESC_RATE_ID_8822B(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc) -#define SET_TX_DESC_PIFS_8822B(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value) -#define GET_TX_DESC_PIFS_8822B(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc) -#define SET_TX_DESC_LSIG_TXOP_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN_8822B(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) -#define SET_TX_DESC_RD_NAV_EXT_8822B(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) -#define GET_TX_DESC_RD_NAV_EXT_8822B(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc) -#define SET_TX_DESC_QSEL_8822B(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value) -#define GET_TX_DESC_QSEL_8822B(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc) -#define SET_TX_DESC_MACID_8822B(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value) -#define GET_TX_DESC_MACID_8822B(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc) +#define SET_TX_DESC_DISQSELSEQ_8822B(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8822B(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8822B(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8822B(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8822B(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8822B(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822B(txdesc, value) \ + SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822B(txdesc) \ + GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8822B(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8822B(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8822B(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8822B(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8822B(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8822B(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8822B(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8822B(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8822B(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8822B(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8822B(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8822B(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_MOREDATA_8822B(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8822B(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8822B(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8822B(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8822B(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8822B(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8822B(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8822B(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8822B(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8822B(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8822B(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8822B(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8822B(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8822B(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8822B(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8822B(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8822B(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8822B(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8822B(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8822B(txdesc) GET_TX_DESC_MACID(txdesc) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV_8822B(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) -#define GET_TX_DESC_HW_AES_IV_8822B(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc) -#define SET_TX_DESC_FTM_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value) -#define GET_TX_DESC_FTM_EN_8822B(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc) -#define SET_TX_DESC_G_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value) -#define GET_TX_DESC_G_ID_8822B(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc) -#define SET_TX_DESC_BT_NULL_8822B(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value) -#define GET_TX_DESC_BT_NULL_8822B(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc) -#define SET_TX_DESC_AMPDU_DENSITY_8822B(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_DENSITY_8822B(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) -#define SET_TX_DESC_SPE_RPT_8822B(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) -#define GET_TX_DESC_SPE_RPT_8822B(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc) -#define SET_TX_DESC_RAW_8822B(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value) -#define GET_TX_DESC_RAW_8822B(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc) -#define SET_TX_DESC_MOREFRAG_8822B(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) -#define GET_TX_DESC_MOREFRAG_8822B(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc) -#define SET_TX_DESC_BK_8822B(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value) -#define GET_TX_DESC_BK_8822B(__pTxDesc) GET_TX_DESC_BK(__pTxDesc) -#define SET_TX_DESC_NULL_1_8822B(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_1_8822B(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc) -#define SET_TX_DESC_NULL_0_8822B(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_0_8822B(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc) -#define SET_TX_DESC_RDG_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RDG_EN_8822B(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc) -#define SET_TX_DESC_AGG_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AGG_EN_8822B(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc) -#define SET_TX_DESC_CCA_RTS_8822B(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) -#define GET_TX_DESC_CCA_RTS_8822B(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc) -#define SET_TX_DESC_TRI_FRAME_8822B(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) -#define GET_TX_DESC_TRI_FRAME_8822B(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc) -#define SET_TX_DESC_P_AID_8822B(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value) -#define GET_TX_DESC_P_AID_8822B(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc) +#define SET_TX_DESC_HW_AES_IV_8822B(txdesc, value) \ + SET_TX_DESC_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8822B(txdesc) GET_TX_DESC_HW_AES_IV(txdesc) +#define SET_TX_DESC_FTM_EN_8822B(txdesc, value) \ + SET_TX_DESC_FTM_EN(txdesc, value) +#define GET_TX_DESC_FTM_EN_8822B(txdesc) GET_TX_DESC_FTM_EN(txdesc) +#define SET_TX_DESC_G_ID_8822B(txdesc, value) SET_TX_DESC_G_ID(txdesc, value) +#define GET_TX_DESC_G_ID_8822B(txdesc) GET_TX_DESC_G_ID(txdesc) +#define SET_TX_DESC_BT_NULL_8822B(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8822B(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8822B(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8822B(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8822B(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8822B(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8822B(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8822B(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8822B(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8822B(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8822B(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8822B(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8822B(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8822B(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8822B(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8822B(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8822B(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8822B(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8822B(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8822B(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8822B(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8822B(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_TRI_FRAME_8822B(txdesc, value) \ + SET_TX_DESC_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_TRI_FRAME_8822B(txdesc) GET_TX_DESC_TRI_FRAME(txdesc) +#define SET_TX_DESC_P_AID_8822B(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8822B(txdesc) GET_TX_DESC_P_AID(txdesc) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME_8822B(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME_8822B(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) -#define SET_TX_DESC_NDPA_8822B(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value) -#define GET_TX_DESC_NDPA_8822B(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc) -#define SET_TX_DESC_MAX_AGG_NUM_8822B(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_MAX_AGG_NUM_8822B(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) -#define SET_TX_DESC_USE_MAX_TIME_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN_8822B(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) -#define SET_TX_DESC_NAVUSEHDR_8822B(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) -#define GET_TX_DESC_NAVUSEHDR_8822B(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc) -#define SET_TX_DESC_CHK_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value) -#define GET_TX_DESC_CHK_EN_8822B(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc) -#define SET_TX_DESC_HW_RTS_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_HW_RTS_EN_8822B(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSEN_8822B(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value) -#define GET_TX_DESC_RTSEN_8822B(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc) -#define SET_TX_DESC_CTS2SELF_8822B(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) -#define GET_TX_DESC_CTS2SELF_8822B(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc) -#define SET_TX_DESC_DISDATAFB_8822B(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISDATAFB_8822B(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc) -#define SET_TX_DESC_DISRTSFB_8822B(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISRTSFB_8822B(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc) -#define SET_TX_DESC_USE_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_USE_RATE_8822B(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc) -#define SET_TX_DESC_HW_SSN_SEL_8822B(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_HW_SSN_SEL_8822B(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc) -#define SET_TX_DESC_WHEADER_LEN_8822B(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_WHEADER_LEN_8822B(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc) +#define SET_TX_DESC_AMPDU_MAX_TIME_8822B(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8822B(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8822B(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8822B(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8822B(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8822B(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8822B(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8822B(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8822B(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8822B(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8822B(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8822B(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8822B(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8822B(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8822B(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8822B(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8822B(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8822B(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8822B(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8822B(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8822B(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8822B(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8822B(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8822B(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8822B(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8822B(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8822B(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8822B(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) /*TXDESC_WORD4*/ -#define SET_TX_DESC_PCTS_MASK_IDX_8822B(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX_8822B(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) -#define SET_TX_DESC_PCTS_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_EN_8822B(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSRATE_8822B(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTSRATE_8822B(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) -#define SET_TX_DESC_RTY_LMT_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RTY_LMT_EN_8822B(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_TRY_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_TRY_RATE_8822B(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc) -#define SET_TX_DESC_DATARATE_8822B(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATARATE_8822B(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc) +#define SET_TX_DESC_PCTS_MASK_IDX_8822B(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8822B(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8822B(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8822B(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8822B(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8822B(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822B(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8822B(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8822B(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8822B(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8822B(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8822B(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8822B(txdesc) GET_TX_DESC_DATARATE(txdesc) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED_8822B(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value) -#define GET_TX_DESC_POLLUTED_8822B(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc) -#define SET_TX_DESC_TXPWR_OFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) -#define GET_TX_DESC_TXPWR_OFSET_8822B(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc) -#define SET_TX_DESC_TX_ANT_8822B(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value) -#define GET_TX_DESC_TX_ANT_8822B(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc) -#define SET_TX_DESC_PORT_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value) -#define GET_TX_DESC_PORT_ID_8822B(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc) -#define SET_TX_DESC_MULTIPLE_PORT_8822B(__pTxDesc, __Value) SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) -#define GET_TX_DESC_MULTIPLE_PORT_8822B(__pTxDesc) GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) -#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_SC_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SC_8822B(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc) -#define SET_TX_DESC_RTS_SHORT_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SHORT_8822B(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc) -#define SET_TX_DESC_VCS_STBC_8822B(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_VCS_STBC_8822B(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_STBC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_STBC_8822B(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_LDPC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_LDPC_8822B(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc) -#define SET_TX_DESC_DATA_BW_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_BW_8822B(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc) -#define SET_TX_DESC_DATA_SHORT_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SHORT_8822B(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc) -#define SET_TX_DESC_DATA_SC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SC_8822B(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc) +#define SET_TX_DESC_POLLUTED_8822B(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8822B(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_8822B(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_8822B(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc) +#define SET_TX_DESC_TX_ANT_8822B(txdesc, value) \ + SET_TX_DESC_TX_ANT(txdesc, value) +#define GET_TX_DESC_TX_ANT_8822B(txdesc) GET_TX_DESC_TX_ANT(txdesc) +#define SET_TX_DESC_PORT_ID_8822B(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8822B(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_MULTIPLE_PORT_8822B(txdesc, value) \ + SET_TX_DESC_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_MULTIPLE_PORT_8822B(txdesc) \ + GET_TX_DESC_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822B(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822B(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8822B(txdesc, value) \ + SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) +#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8822B(txdesc) \ + GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8822B(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8822B(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8822B(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8822B(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8822B(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8822B(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8822B(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8822B(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8822B(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8822B(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8822B(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8822B(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8822B(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8822B(txdesc) GET_TX_DESC_DATA_SC(txdesc) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_D_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc) -#define SET_TX_DESC_ANT_MAPD_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPD_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc) -#define SET_TX_DESC_ANT_MAPC_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPC_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc) -#define SET_TX_DESC_ANT_MAPB_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPB_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc) -#define SET_TX_DESC_ANT_MAPA_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPA_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc) -#define SET_TX_DESC_ANTSEL_C_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_C_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc) -#define SET_TX_DESC_ANTSEL_B_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_B_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc) -#define SET_TX_DESC_ANTSEL_A_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_A_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc) -#define SET_TX_DESC_MBSSID_8822B(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value) -#define GET_TX_DESC_MBSSID_8822B(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc) -#define SET_TX_DESC_SW_DEFINE_8822B(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) -#define GET_TX_DESC_SW_DEFINE_8822B(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc) +#define SET_TX_DESC_ANTSEL_D_8822B(txdesc, value) \ + SET_TX_DESC_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_ANTSEL_D_8822B(txdesc) GET_TX_DESC_ANTSEL_D(txdesc) +#define SET_TX_DESC_ANT_MAPD_8822B(txdesc, value) \ + SET_TX_DESC_ANT_MAPD(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8822B(txdesc) GET_TX_DESC_ANT_MAPD(txdesc) +#define SET_TX_DESC_ANT_MAPC_8822B(txdesc, value) \ + SET_TX_DESC_ANT_MAPC(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8822B(txdesc) GET_TX_DESC_ANT_MAPC(txdesc) +#define SET_TX_DESC_ANT_MAPB_8822B(txdesc, value) \ + SET_TX_DESC_ANT_MAPB(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8822B(txdesc) GET_TX_DESC_ANT_MAPB(txdesc) +#define SET_TX_DESC_ANT_MAPA_8822B(txdesc, value) \ + SET_TX_DESC_ANT_MAPA(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8822B(txdesc) GET_TX_DESC_ANT_MAPA(txdesc) +#define SET_TX_DESC_ANTSEL_C_8822B(txdesc, value) \ + SET_TX_DESC_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8822B(txdesc) GET_TX_DESC_ANTSEL_C(txdesc) +#define SET_TX_DESC_ANTSEL_B_8822B(txdesc, value) \ + SET_TX_DESC_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8822B(txdesc) GET_TX_DESC_ANTSEL_B(txdesc) +#define SET_TX_DESC_ANTSEL_A_8822B(txdesc, value) \ + SET_TX_DESC_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8822B(txdesc) GET_TX_DESC_ANTSEL_A(txdesc) +#define SET_TX_DESC_MBSSID_8822B(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8822B(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SW_DEFINE_8822B(txdesc, value) \ + SET_TX_DESC_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_SW_DEFINE_8822B(txdesc) GET_TX_DESC_SW_DEFINE(txdesc) /*TXDESC_WORD7*/ -#define SET_TX_DESC_DMA_TXAGG_NUM_8822B(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM_8822B(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) -#define SET_TX_DESC_FINAL_DATA_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_FINAL_DATA_RATE_8822B(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) -#define SET_TX_DESC_NTX_MAP_8822B(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) -#define GET_TX_DESC_NTX_MAP_8822B(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc) -#define SET_TX_DESC_TX_BUFF_SIZE_8822B(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE_8822B(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) -#define SET_TX_DESC_TXDESC_CHECKSUM_8822B(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM_8822B(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) -#define SET_TX_DESC_TIMESTAMP_8822B(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) -#define GET_TX_DESC_TIMESTAMP_8822B(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8822B(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8822B(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8822B(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8822B(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8822B(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8822B(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8822B(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8822B(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8822B(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8822B(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8822B(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8822B(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) /*TXDESC_WORD8*/ -#define SET_TX_DESC_TXWIFI_CP_8822B(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) -#define GET_TX_DESC_TXWIFI_CP_8822B(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc) -#define SET_TX_DESC_MAC_CP_8822B(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value) -#define GET_TX_DESC_MAC_CP_8822B(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc) -#define SET_TX_DESC_STW_PKTRE_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_PKTRE_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RB_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RB_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RATE_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RATE_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_ANT_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_ANT_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc) -#define SET_TX_DESC_STW_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value) -#define GET_TX_DESC_STW_EN_8822B(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc) -#define SET_TX_DESC_SMH_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SMH_EN_8822B(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc) -#define SET_TX_DESC_TAILPAGE_L_8822B(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_L_8822B(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc) -#define SET_TX_DESC_SDIO_DMASEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SDIO_DMASEQ_8822B(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_L_8822B(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L_8822B(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) -#define SET_TX_DESC_EN_HWSEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWSEQ_8822B(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc) -#define SET_TX_DESC_EN_HWEXSEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWEXSEQ_8822B(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) -#define SET_TX_DESC_DATA_RC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RC_8822B(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc) -#define SET_TX_DESC_BAR_RTY_TH_8822B(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) -#define GET_TX_DESC_BAR_RTY_TH_8822B(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc) -#define SET_TX_DESC_RTS_RC_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RC_8822B(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc) +#define SET_TX_DESC_TXWIFI_CP_8822B(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8822B(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8822B(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8822B(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8822B(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8822B(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8822B(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8822B(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8822B(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8822B(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8822B(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8822B(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8822B(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8822B(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8822B(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8822B(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8822B(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8822B(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8822B(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8822B(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8822B(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8822B(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8822B(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8822B(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8822B(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8822B(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8822B(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8822B(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8822B(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8822B(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8822B(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8822B(txdesc) GET_TX_DESC_RTS_RC(txdesc) /*TXDESC_WORD9*/ -#define SET_TX_DESC_TAILPAGE_H_8822B(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_H_8822B(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_H_8822B(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_H_8822B(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) -#define SET_TX_DESC_SW_SEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SW_SEQ_8822B(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc) -#define SET_TX_DESC_TXBF_PATH_8822B(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) -#define GET_TX_DESC_TXBF_PATH_8822B(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc) -#define SET_TX_DESC_PADDING_LEN_8822B(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_PADDING_LEN_8822B(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) +#define SET_TX_DESC_TAILPAGE_H_8822B(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8822B(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8822B(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8822B(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8822B(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8822B(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8822B(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8822B(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8822B(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8822B(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) /*WORD10*/ -#define SET_TX_DESC_MU_DATARATE_8822B(__pTxDesc, __Value) SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_MU_DATARATE_8822B(__pTxDesc) GET_TX_DESC_MU_DATARATE(__pTxDesc) -#define SET_TX_DESC_MU_RC_8822B(__pTxDesc, __Value) SET_TX_DESC_MU_RC(__pTxDesc, __Value) -#define GET_TX_DESC_MU_RC_8822B(__pTxDesc) GET_TX_DESC_MU_RC(__pTxDesc) -#define SET_TX_DESC_SND_PKT_SEL_8822B(__pTxDesc, __Value) SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_SND_PKT_SEL_8822B(__pTxDesc) GET_TX_DESC_SND_PKT_SEL(__pTxDesc) +#define SET_TX_DESC_MU_DATARATE_8822B(txdesc, value) \ + SET_TX_DESC_MU_DATARATE(txdesc, value) +#define GET_TX_DESC_MU_DATARATE_8822B(txdesc) GET_TX_DESC_MU_DATARATE(txdesc) +#define SET_TX_DESC_MU_RC_8822B(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value) +#define GET_TX_DESC_MU_RC_8822B(txdesc) GET_TX_DESC_MU_RC(txdesc) +#define SET_TX_DESC_SND_PKT_SEL_8822B(txdesc, value) \ + SET_TX_DESC_SND_PKT_SEL(txdesc, value) +#define GET_TX_DESC_SND_PKT_SEL_8822B(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc) #endif @@ -520,728 +761,2023 @@ /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_DISQSELSEQ_8197F(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc) -#define SET_TX_DESC_GF_8197F(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value) -#define GET_TX_DESC_GF_8197F(__pTxDesc) GET_TX_DESC_GF(__pTxDesc) -#define SET_TX_DESC_NO_ACM_8197F(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value) -#define GET_TX_DESC_NO_ACM_8197F(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc) -#define SET_TX_DESC_BCNPKT_TSF_CTRL_8197F(__pTxDesc, __Value) SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) -#define GET_TX_DESC_BCNPKT_TSF_CTRL_8197F(__pTxDesc) GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) -#define SET_TX_DESC_AMSDU_PAD_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AMSDU_PAD_EN_8197F(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) -#define SET_TX_DESC_LS_8197F(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value) -#define GET_TX_DESC_LS_8197F(__pTxDesc) GET_TX_DESC_LS(__pTxDesc) -#define SET_TX_DESC_HTC_8197F(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value) -#define GET_TX_DESC_HTC_8197F(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc) -#define SET_TX_DESC_BMC_8197F(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value) -#define GET_TX_DESC_BMC_8197F(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc) -#define SET_TX_DESC_OFFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_OFFSET_8197F(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc) -#define SET_TX_DESC_TXPKTSIZE_8197F(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TXPKTSIZE_8197F(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc) - -/*TXDESC_WORD1*/ - -#define SET_TX_DESC_MOREDATA_8197F(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value) -#define GET_TX_DESC_MOREDATA_8197F(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc) -#define SET_TX_DESC_PKT_OFFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_PKT_OFFSET_8197F(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc) -#define SET_TX_DESC_SEC_TYPE_8197F(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) -#define GET_TX_DESC_SEC_TYPE_8197F(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc) -#define SET_TX_DESC_EN_DESC_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) -#define GET_TX_DESC_EN_DESC_ID_8197F(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc) -#define SET_TX_DESC_RATE_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value) -#define GET_TX_DESC_RATE_ID_8197F(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc) -#define SET_TX_DESC_PIFS_8197F(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value) -#define GET_TX_DESC_PIFS_8197F(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc) -#define SET_TX_DESC_LSIG_TXOP_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN_8197F(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) -#define SET_TX_DESC_RD_NAV_EXT_8197F(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) -#define GET_TX_DESC_RD_NAV_EXT_8197F(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc) -#define SET_TX_DESC_QSEL_8197F(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value) -#define GET_TX_DESC_QSEL_8197F(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc) -#define SET_TX_DESC_MACID_8197F(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value) -#define GET_TX_DESC_MACID_8197F(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc) +#define SET_TX_DESC_DISQSELSEQ_8197F(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8197F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8197F(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8197F(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8197F(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8197F(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8197F(txdesc, value) \ + SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8197F(txdesc) \ + GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8197F(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8197F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8197F(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8197F(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8197F(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8197F(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8197F(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8197F(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8197F(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8197F(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8197F(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8197F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_MOREDATA_8197F(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8197F(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8197F(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8197F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8197F(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8197F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8197F(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8197F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8197F(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8197F(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8197F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8197F(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8197F(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8197F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8197F(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8197F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8197F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8197F(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8197F(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8197F(txdesc) GET_TX_DESC_MACID(txdesc) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV_8197F(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) -#define GET_TX_DESC_HW_AES_IV_8197F(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc) -#define SET_TX_DESC_FTM_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value) -#define GET_TX_DESC_FTM_EN_8197F(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc) -#define SET_TX_DESC_G_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value) -#define GET_TX_DESC_G_ID_8197F(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc) -#define SET_TX_DESC_BT_NULL_8197F(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value) -#define GET_TX_DESC_BT_NULL_8197F(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc) -#define SET_TX_DESC_AMPDU_DENSITY_8197F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_DENSITY_8197F(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) -#define SET_TX_DESC_SPE_RPT_8197F(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) -#define GET_TX_DESC_SPE_RPT_8197F(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc) -#define SET_TX_DESC_RAW_8197F(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value) -#define GET_TX_DESC_RAW_8197F(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc) -#define SET_TX_DESC_MOREFRAG_8197F(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) -#define GET_TX_DESC_MOREFRAG_8197F(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc) -#define SET_TX_DESC_BK_8197F(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value) -#define GET_TX_DESC_BK_8197F(__pTxDesc) GET_TX_DESC_BK(__pTxDesc) -#define SET_TX_DESC_NULL_1_8197F(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_1_8197F(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc) -#define SET_TX_DESC_NULL_0_8197F(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_0_8197F(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc) -#define SET_TX_DESC_RDG_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RDG_EN_8197F(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc) -#define SET_TX_DESC_AGG_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AGG_EN_8197F(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc) -#define SET_TX_DESC_CCA_RTS_8197F(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) -#define GET_TX_DESC_CCA_RTS_8197F(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc) -#define SET_TX_DESC_TRI_FRAME_8197F(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) -#define GET_TX_DESC_TRI_FRAME_8197F(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc) -#define SET_TX_DESC_P_AID_8197F(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value) -#define GET_TX_DESC_P_AID_8197F(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc) +#define SET_TX_DESC_HW_AES_IV_8197F(txdesc, value) \ + SET_TX_DESC_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8197F(txdesc) GET_TX_DESC_HW_AES_IV(txdesc) +#define SET_TX_DESC_FTM_EN_8197F(txdesc, value) \ + SET_TX_DESC_FTM_EN(txdesc, value) +#define GET_TX_DESC_FTM_EN_8197F(txdesc) GET_TX_DESC_FTM_EN(txdesc) +#define SET_TX_DESC_G_ID_8197F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value) +#define GET_TX_DESC_G_ID_8197F(txdesc) GET_TX_DESC_G_ID(txdesc) +#define SET_TX_DESC_BT_NULL_8197F(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8197F(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8197F(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8197F(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8197F(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8197F(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8197F(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8197F(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8197F(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8197F(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8197F(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8197F(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8197F(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8197F(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8197F(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8197F(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8197F(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8197F(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8197F(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8197F(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8197F(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8197F(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_TRI_FRAME_8197F(txdesc, value) \ + SET_TX_DESC_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_TRI_FRAME_8197F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc) +#define SET_TX_DESC_P_AID_8197F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8197F(txdesc) GET_TX_DESC_P_AID(txdesc) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME_8197F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME_8197F(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) -#define SET_TX_DESC_NDPA_8197F(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value) -#define GET_TX_DESC_NDPA_8197F(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc) -#define SET_TX_DESC_MAX_AGG_NUM_8197F(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_MAX_AGG_NUM_8197F(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) -#define SET_TX_DESC_USE_MAX_TIME_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN_8197F(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) -#define SET_TX_DESC_NAVUSEHDR_8197F(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) -#define GET_TX_DESC_NAVUSEHDR_8197F(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc) -#define SET_TX_DESC_CHK_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value) -#define GET_TX_DESC_CHK_EN_8197F(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc) -#define SET_TX_DESC_HW_RTS_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_HW_RTS_EN_8197F(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSEN_8197F(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value) -#define GET_TX_DESC_RTSEN_8197F(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc) -#define SET_TX_DESC_CTS2SELF_8197F(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) -#define GET_TX_DESC_CTS2SELF_8197F(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc) -#define SET_TX_DESC_DISDATAFB_8197F(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISDATAFB_8197F(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc) -#define SET_TX_DESC_DISRTSFB_8197F(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISRTSFB_8197F(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc) -#define SET_TX_DESC_USE_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_USE_RATE_8197F(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc) -#define SET_TX_DESC_HW_SSN_SEL_8197F(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_HW_SSN_SEL_8197F(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc) -#define SET_TX_DESC_WHEADER_LEN_8197F(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_WHEADER_LEN_8197F(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc) +#define SET_TX_DESC_AMPDU_MAX_TIME_8197F(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8197F(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8197F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8197F(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8197F(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8197F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8197F(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8197F(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8197F(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8197F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8197F(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8197F(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8197F(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8197F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8197F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8197F(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8197F(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8197F(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8197F(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8197F(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8197F(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8197F(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8197F(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8197F(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8197F(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8197F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8197F(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8197F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) /*TXDESC_WORD4*/ -#define SET_TX_DESC_PCTS_MASK_IDX_8197F(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX_8197F(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) -#define SET_TX_DESC_PCTS_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_EN_8197F(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSRATE_8197F(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTSRATE_8197F(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT_8197F(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) -#define SET_TX_DESC_RTY_LMT_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RTY_LMT_EN_8197F(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_TRY_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_TRY_RATE_8197F(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc) -#define SET_TX_DESC_DATARATE_8197F(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATARATE_8197F(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc) +#define SET_TX_DESC_PCTS_MASK_IDX_8197F(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8197F(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8197F(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8197F(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8197F(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8197F(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8197F(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8197F(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8197F(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8197F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8197F(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8197F(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8197F(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8197F(txdesc) GET_TX_DESC_DATARATE(txdesc) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED_8197F(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value) -#define GET_TX_DESC_POLLUTED_8197F(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc) -#define SET_TX_DESC_TXPWR_OFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) -#define GET_TX_DESC_TXPWR_OFSET_8197F(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc) -#define SET_TX_DESC_TX_ANT_8197F(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value) -#define GET_TX_DESC_TX_ANT_8197F(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc) -#define SET_TX_DESC_PORT_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value) -#define GET_TX_DESC_PORT_ID_8197F(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc) -#define SET_TX_DESC_MULTIPLE_PORT_8197F(__pTxDesc, __Value) SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) -#define GET_TX_DESC_MULTIPLE_PORT_8197F(__pTxDesc) GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) -#define SET_TX_DESC_SIGNALING_TAPKT_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SIGNALING_TAPKT_EN_8197F(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_SC_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SC_8197F(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc) -#define SET_TX_DESC_RTS_SHORT_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SHORT_8197F(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc) -#define SET_TX_DESC_VCS_STBC_8197F(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_VCS_STBC_8197F(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_STBC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_STBC_8197F(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_LDPC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_LDPC_8197F(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc) -#define SET_TX_DESC_DATA_BW_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_BW_8197F(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc) -#define SET_TX_DESC_DATA_SHORT_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SHORT_8197F(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc) -#define SET_TX_DESC_DATA_SC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SC_8197F(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc) +#define SET_TX_DESC_POLLUTED_8197F(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8197F(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_8197F(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_8197F(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc) +#define SET_TX_DESC_TX_ANT_8197F(txdesc, value) \ + SET_TX_DESC_TX_ANT(txdesc, value) +#define GET_TX_DESC_TX_ANT_8197F(txdesc) GET_TX_DESC_TX_ANT(txdesc) +#define SET_TX_DESC_PORT_ID_8197F(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8197F(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_MULTIPLE_PORT_8197F(txdesc, value) \ + SET_TX_DESC_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_MULTIPLE_PORT_8197F(txdesc) \ + GET_TX_DESC_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8197F(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8197F(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_RTS_SC_8197F(txdesc, value) \ + SET_TX_DESC_RTS_SC(txdesc, value) +#define GET_TX_DESC_RTS_SC_8197F(txdesc) GET_TX_DESC_RTS_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8197F(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8197F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8197F(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8197F(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8197F(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8197F(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8197F(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8197F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8197F(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8197F(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8197F(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8197F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8197F(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8197F(txdesc) GET_TX_DESC_DATA_SC(txdesc) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_D_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc) -#define SET_TX_DESC_ANT_MAPD_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPD_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc) -#define SET_TX_DESC_ANT_MAPC_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPC_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc) -#define SET_TX_DESC_ANT_MAPB_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPB_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc) -#define SET_TX_DESC_ANT_MAPA_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPA_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc) -#define SET_TX_DESC_ANTSEL_C_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_C_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc) -#define SET_TX_DESC_ANTSEL_B_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_B_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc) -#define SET_TX_DESC_ANTSEL_A_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_A_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc) -#define SET_TX_DESC_MBSSID_8197F(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value) -#define GET_TX_DESC_MBSSID_8197F(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc) -#define SET_TX_DESC_SW_DEFINE_8197F(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) -#define GET_TX_DESC_SW_DEFINE_8197F(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc) +#define SET_TX_DESC_ANTSEL_D_8197F(txdesc, value) \ + SET_TX_DESC_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_ANTSEL_D_8197F(txdesc) GET_TX_DESC_ANTSEL_D(txdesc) +#define SET_TX_DESC_ANT_MAPD_8197F(txdesc, value) \ + SET_TX_DESC_ANT_MAPD(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8197F(txdesc) GET_TX_DESC_ANT_MAPD(txdesc) +#define SET_TX_DESC_ANT_MAPC_8197F(txdesc, value) \ + SET_TX_DESC_ANT_MAPC(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8197F(txdesc) GET_TX_DESC_ANT_MAPC(txdesc) +#define SET_TX_DESC_ANT_MAPB_8197F(txdesc, value) \ + SET_TX_DESC_ANT_MAPB(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8197F(txdesc) GET_TX_DESC_ANT_MAPB(txdesc) +#define SET_TX_DESC_ANT_MAPA_8197F(txdesc, value) \ + SET_TX_DESC_ANT_MAPA(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8197F(txdesc) GET_TX_DESC_ANT_MAPA(txdesc) +#define SET_TX_DESC_ANTSEL_C_8197F(txdesc, value) \ + SET_TX_DESC_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8197F(txdesc) GET_TX_DESC_ANTSEL_C(txdesc) +#define SET_TX_DESC_ANTSEL_B_8197F(txdesc, value) \ + SET_TX_DESC_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8197F(txdesc) GET_TX_DESC_ANTSEL_B(txdesc) +#define SET_TX_DESC_ANTSEL_A_8197F(txdesc, value) \ + SET_TX_DESC_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8197F(txdesc) GET_TX_DESC_ANTSEL_A(txdesc) +#define SET_TX_DESC_MBSSID_8197F(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8197F(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SW_DEFINE_8197F(txdesc, value) \ + SET_TX_DESC_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_SW_DEFINE_8197F(txdesc) GET_TX_DESC_SW_DEFINE(txdesc) /*TXDESC_WORD7*/ -#define SET_TX_DESC_DMA_TXAGG_NUM_8197F(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM_8197F(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) -#define SET_TX_DESC_FINAL_DATA_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_FINAL_DATA_RATE_8197F(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) -#define SET_TX_DESC_NTX_MAP_8197F(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) -#define GET_TX_DESC_NTX_MAP_8197F(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc) -#define SET_TX_DESC_TX_BUFF_SIZE_8197F(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE_8197F(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) -#define SET_TX_DESC_TXDESC_CHECKSUM_8197F(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM_8197F(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) -#define SET_TX_DESC_TIMESTAMP_8197F(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) -#define GET_TX_DESC_TIMESTAMP_8197F(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8197F(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8197F(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8197F(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8197F(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8197F(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8197F(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8197F(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8197F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8197F(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8197F(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8197F(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8197F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) /*TXDESC_WORD8*/ -#define SET_TX_DESC_TXWIFI_CP_8197F(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) -#define GET_TX_DESC_TXWIFI_CP_8197F(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc) -#define SET_TX_DESC_MAC_CP_8197F(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value) -#define GET_TX_DESC_MAC_CP_8197F(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc) -#define SET_TX_DESC_STW_PKTRE_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_PKTRE_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RB_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RB_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RATE_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RATE_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_ANT_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_ANT_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc) -#define SET_TX_DESC_STW_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value) -#define GET_TX_DESC_STW_EN_8197F(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc) -#define SET_TX_DESC_SMH_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SMH_EN_8197F(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc) -#define SET_TX_DESC_TAILPAGE_L_8197F(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_L_8197F(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc) -#define SET_TX_DESC_SDIO_DMASEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SDIO_DMASEQ_8197F(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_L_8197F(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L_8197F(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) -#define SET_TX_DESC_EN_HWSEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWSEQ_8197F(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc) -#define SET_TX_DESC_EN_HWEXSEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWEXSEQ_8197F(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) -#define SET_TX_DESC_DATA_RC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RC_8197F(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc) -#define SET_TX_DESC_BAR_RTY_TH_8197F(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) -#define GET_TX_DESC_BAR_RTY_TH_8197F(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc) -#define SET_TX_DESC_RTS_RC_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RC_8197F(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc) +#define SET_TX_DESC_TXWIFI_CP_8197F(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8197F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8197F(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8197F(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8197F(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8197F(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8197F(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8197F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8197F(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8197F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8197F(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8197F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8197F(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8197F(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8197F(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8197F(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8197F(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8197F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8197F(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8197F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8197F(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8197F(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8197F(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8197F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8197F(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8197F(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8197F(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8197F(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8197F(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8197F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8197F(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8197F(txdesc) GET_TX_DESC_RTS_RC(txdesc) /*TXDESC_WORD9*/ -#define SET_TX_DESC_TAILPAGE_H_8197F(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_H_8197F(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_H_8197F(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_H_8197F(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) -#define SET_TX_DESC_SW_SEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SW_SEQ_8197F(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc) -#define SET_TX_DESC_TXBF_PATH_8197F(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) -#define GET_TX_DESC_TXBF_PATH_8197F(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc) -#define SET_TX_DESC_PADDING_LEN_8197F(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_PADDING_LEN_8197F(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) +#define SET_TX_DESC_TAILPAGE_H_8197F(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8197F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8197F(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8197F(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8197F(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8197F(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8197F(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8197F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8197F(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8197F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) /*WORD10*/ -#define SET_TX_DESC_MU_DATARATE_8197F(__pTxDesc, __Value) SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_MU_DATARATE_8197F(__pTxDesc) GET_TX_DESC_MU_DATARATE(__pTxDesc) -#define SET_TX_DESC_MU_RC_8197F(__pTxDesc, __Value) SET_TX_DESC_MU_RC(__pTxDesc, __Value) -#define GET_TX_DESC_MU_RC_8197F(__pTxDesc) GET_TX_DESC_MU_RC(__pTxDesc) -#define SET_TX_DESC_SND_PKT_SEL_8197F(__pTxDesc, __Value) SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_SND_PKT_SEL_8197F(__pTxDesc) GET_TX_DESC_SND_PKT_SEL(__pTxDesc) - #endif #if (HALMAC_8821C_SUPPORT) /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_DISQSELSEQ_8821C(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc) -#define SET_TX_DESC_GF_8821C(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value) -#define GET_TX_DESC_GF_8821C(__pTxDesc) GET_TX_DESC_GF(__pTxDesc) -#define SET_TX_DESC_NO_ACM_8821C(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value) -#define GET_TX_DESC_NO_ACM_8821C(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc) -#define SET_TX_DESC_BCNPKT_TSF_CTRL_8821C(__pTxDesc, __Value) SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) -#define GET_TX_DESC_BCNPKT_TSF_CTRL_8821C(__pTxDesc) GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) -#define SET_TX_DESC_AMSDU_PAD_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AMSDU_PAD_EN_8821C(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) -#define SET_TX_DESC_LS_8821C(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value) -#define GET_TX_DESC_LS_8821C(__pTxDesc) GET_TX_DESC_LS(__pTxDesc) -#define SET_TX_DESC_HTC_8821C(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value) -#define GET_TX_DESC_HTC_8821C(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc) -#define SET_TX_DESC_BMC_8821C(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value) -#define GET_TX_DESC_BMC_8821C(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc) -#define SET_TX_DESC_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_OFFSET_8821C(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc) -#define SET_TX_DESC_TXPKTSIZE_8821C(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TXPKTSIZE_8821C(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc) - -/*TXDESC_WORD1*/ - -#define SET_TX_DESC_MOREDATA_8821C(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value) -#define GET_TX_DESC_MOREDATA_8821C(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc) -#define SET_TX_DESC_PKT_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_PKT_OFFSET_8821C(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc) -#define SET_TX_DESC_SEC_TYPE_8821C(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) -#define GET_TX_DESC_SEC_TYPE_8821C(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc) -#define SET_TX_DESC_EN_DESC_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) -#define GET_TX_DESC_EN_DESC_ID_8821C(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc) -#define SET_TX_DESC_RATE_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value) -#define GET_TX_DESC_RATE_ID_8821C(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc) -#define SET_TX_DESC_PIFS_8821C(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value) -#define GET_TX_DESC_PIFS_8821C(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc) -#define SET_TX_DESC_LSIG_TXOP_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN_8821C(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) -#define SET_TX_DESC_RD_NAV_EXT_8821C(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) -#define GET_TX_DESC_RD_NAV_EXT_8821C(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc) -#define SET_TX_DESC_QSEL_8821C(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value) -#define GET_TX_DESC_QSEL_8821C(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc) -#define SET_TX_DESC_MACID_8821C(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value) -#define GET_TX_DESC_MACID_8821C(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc) +#define SET_TX_DESC_DISQSELSEQ_8821C(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8821C(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8821C(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8821C(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8821C(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8821C(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8821C(txdesc, value) \ + SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8821C(txdesc) \ + GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8821C(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8821C(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8821C(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8821C(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8821C(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8821C(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8821C(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8821C(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8821C(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8821C(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8821C(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8821C(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_MOREDATA_8821C(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8821C(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8821C(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8821C(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8821C(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8821C(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8821C(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8821C(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8821C(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8821C(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8821C(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8821C(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8821C(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8821C(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8821C(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8821C(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8821C(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8821C(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8821C(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8821C(txdesc) GET_TX_DESC_MACID(txdesc) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) -#define GET_TX_DESC_HW_AES_IV_8821C(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc) -#define SET_TX_DESC_FTM_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value) -#define GET_TX_DESC_FTM_EN_8821C(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc) -#define SET_TX_DESC_G_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value) -#define GET_TX_DESC_G_ID_8821C(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc) -#define SET_TX_DESC_BT_NULL_8821C(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value) -#define GET_TX_DESC_BT_NULL_8821C(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc) -#define SET_TX_DESC_AMPDU_DENSITY_8821C(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_DENSITY_8821C(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) -#define SET_TX_DESC_SPE_RPT_8821C(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) -#define GET_TX_DESC_SPE_RPT_8821C(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc) -#define SET_TX_DESC_RAW_8821C(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value) -#define GET_TX_DESC_RAW_8821C(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc) -#define SET_TX_DESC_MOREFRAG_8821C(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) -#define GET_TX_DESC_MOREFRAG_8821C(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc) -#define SET_TX_DESC_BK_8821C(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value) -#define GET_TX_DESC_BK_8821C(__pTxDesc) GET_TX_DESC_BK(__pTxDesc) -#define SET_TX_DESC_NULL_1_8821C(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_1_8821C(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc) -#define SET_TX_DESC_NULL_0_8821C(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_0_8821C(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc) -#define SET_TX_DESC_RDG_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RDG_EN_8821C(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc) -#define SET_TX_DESC_AGG_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AGG_EN_8821C(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc) -#define SET_TX_DESC_CCA_RTS_8821C(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) -#define GET_TX_DESC_CCA_RTS_8821C(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc) -#define SET_TX_DESC_TRI_FRAME_8821C(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) -#define GET_TX_DESC_TRI_FRAME_8821C(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc) -#define SET_TX_DESC_P_AID_8821C(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value) -#define GET_TX_DESC_P_AID_8821C(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc) +#define SET_TX_DESC_HW_AES_IV_8821C(txdesc, value) \ + SET_TX_DESC_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8821C(txdesc) GET_TX_DESC_HW_AES_IV(txdesc) +#define SET_TX_DESC_FTM_EN_8821C(txdesc, value) \ + SET_TX_DESC_FTM_EN(txdesc, value) +#define GET_TX_DESC_FTM_EN_8821C(txdesc) GET_TX_DESC_FTM_EN(txdesc) +#define SET_TX_DESC_G_ID_8821C(txdesc, value) SET_TX_DESC_G_ID(txdesc, value) +#define GET_TX_DESC_G_ID_8821C(txdesc) GET_TX_DESC_G_ID(txdesc) +#define SET_TX_DESC_BT_NULL_8821C(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8821C(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8821C(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8821C(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8821C(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8821C(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8821C(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8821C(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8821C(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8821C(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8821C(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8821C(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8821C(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8821C(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8821C(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8821C(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8821C(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8821C(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8821C(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8821C(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8821C(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8821C(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_TRI_FRAME_8821C(txdesc, value) \ + SET_TX_DESC_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_TRI_FRAME_8821C(txdesc) GET_TX_DESC_TRI_FRAME(txdesc) +#define SET_TX_DESC_P_AID_8821C(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8821C(txdesc) GET_TX_DESC_P_AID(txdesc) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME_8821C(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME_8821C(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) -#define SET_TX_DESC_NDPA_8821C(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value) -#define GET_TX_DESC_NDPA_8821C(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc) -#define SET_TX_DESC_MAX_AGG_NUM_8821C(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_MAX_AGG_NUM_8821C(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) -#define SET_TX_DESC_USE_MAX_TIME_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN_8821C(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) -#define SET_TX_DESC_NAVUSEHDR_8821C(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) -#define GET_TX_DESC_NAVUSEHDR_8821C(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc) -#define SET_TX_DESC_CHK_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value) -#define GET_TX_DESC_CHK_EN_8821C(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc) -#define SET_TX_DESC_HW_RTS_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_HW_RTS_EN_8821C(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSEN_8821C(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value) -#define GET_TX_DESC_RTSEN_8821C(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc) -#define SET_TX_DESC_CTS2SELF_8821C(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) -#define GET_TX_DESC_CTS2SELF_8821C(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc) -#define SET_TX_DESC_DISDATAFB_8821C(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISDATAFB_8821C(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc) -#define SET_TX_DESC_DISRTSFB_8821C(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISRTSFB_8821C(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc) -#define SET_TX_DESC_USE_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_USE_RATE_8821C(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc) -#define SET_TX_DESC_HW_SSN_SEL_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_HW_SSN_SEL_8821C(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc) -#define SET_TX_DESC_WHEADER_LEN_8821C(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_WHEADER_LEN_8821C(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc) +#define SET_TX_DESC_AMPDU_MAX_TIME_8821C(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8821C(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8821C(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8821C(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8821C(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8821C(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8821C(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8821C(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8821C(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8821C(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8821C(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8821C(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8821C(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8821C(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8821C(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8821C(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8821C(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8821C(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8821C(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8821C(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8821C(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8821C(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8821C(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8821C(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8821C(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8821C(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8821C(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8821C(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) /*TXDESC_WORD4*/ -#define SET_TX_DESC_PCTS_MASK_IDX_8821C(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX_8821C(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) -#define SET_TX_DESC_PCTS_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_EN_8821C(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSRATE_8821C(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTSRATE_8821C(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT_8821C(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) -#define SET_TX_DESC_RTY_LMT_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RTY_LMT_EN_8821C(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_TRY_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_TRY_RATE_8821C(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc) -#define SET_TX_DESC_DATARATE_8821C(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATARATE_8821C(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc) +#define SET_TX_DESC_PCTS_MASK_IDX_8821C(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8821C(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8821C(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8821C(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8821C(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8821C(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8821C(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8821C(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8821C(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8821C(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8821C(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8821C(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8821C(txdesc) GET_TX_DESC_DATARATE(txdesc) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED_8821C(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value) -#define GET_TX_DESC_POLLUTED_8821C(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc) -#define SET_TX_DESC_TXPWR_OFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) -#define GET_TX_DESC_TXPWR_OFSET_8821C(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc) -#define SET_TX_DESC_TX_ANT_8821C(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value) -#define GET_TX_DESC_TX_ANT_8821C(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc) -#define SET_TX_DESC_PORT_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value) -#define GET_TX_DESC_PORT_ID_8821C(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc) -#define SET_TX_DESC_MULTIPLE_PORT_8821C(__pTxDesc, __Value) SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) -#define GET_TX_DESC_MULTIPLE_PORT_8821C(__pTxDesc) GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) -#define SET_TX_DESC_SIGNALING_TAPKT_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SIGNALING_TAPKT_EN_8821C(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_SC_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SC_8821C(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc) -#define SET_TX_DESC_RTS_SHORT_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SHORT_8821C(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc) -#define SET_TX_DESC_VCS_STBC_8821C(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_VCS_STBC_8821C(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_STBC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_STBC_8821C(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_LDPC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_LDPC_8821C(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc) -#define SET_TX_DESC_DATA_BW_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_BW_8821C(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc) -#define SET_TX_DESC_DATA_SHORT_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SHORT_8821C(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc) -#define SET_TX_DESC_DATA_SC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SC_8821C(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc) +#define SET_TX_DESC_POLLUTED_8821C(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8821C(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_8821C(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_8821C(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc) +#define SET_TX_DESC_TX_ANT_8821C(txdesc, value) \ + SET_TX_DESC_TX_ANT(txdesc, value) +#define GET_TX_DESC_TX_ANT_8821C(txdesc) GET_TX_DESC_TX_ANT(txdesc) +#define SET_TX_DESC_PORT_ID_8821C(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8821C(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_MULTIPLE_PORT_8821C(txdesc, value) \ + SET_TX_DESC_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_MULTIPLE_PORT_8821C(txdesc) \ + GET_TX_DESC_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8821C(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8821C(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(txdesc, value) \ + SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) +#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(txdesc) \ + GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8821C(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8821C(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8821C(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8821C(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8821C(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8821C(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8821C(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8821C(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8821C(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8821C(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8821C(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8821C(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8821C(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8821C(txdesc) GET_TX_DESC_DATA_SC(txdesc) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_D_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc) -#define SET_TX_DESC_ANT_MAPD_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPD_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc) -#define SET_TX_DESC_ANT_MAPC_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPC_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc) -#define SET_TX_DESC_ANT_MAPB_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPB_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc) -#define SET_TX_DESC_ANT_MAPA_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) -#define GET_TX_DESC_ANT_MAPA_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc) -#define SET_TX_DESC_ANTSEL_C_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_C_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc) -#define SET_TX_DESC_ANTSEL_B_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_B_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc) -#define SET_TX_DESC_ANTSEL_A_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_A_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc) -#define SET_TX_DESC_MBSSID_8821C(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value) -#define GET_TX_DESC_MBSSID_8821C(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc) -#define SET_TX_DESC_SW_DEFINE_8821C(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) -#define GET_TX_DESC_SW_DEFINE_8821C(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc) +#define SET_TX_DESC_ANTSEL_D_8821C(txdesc, value) \ + SET_TX_DESC_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_ANTSEL_D_8821C(txdesc) GET_TX_DESC_ANTSEL_D(txdesc) +#define SET_TX_DESC_ANT_MAPD_8821C(txdesc, value) \ + SET_TX_DESC_ANT_MAPD(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8821C(txdesc) GET_TX_DESC_ANT_MAPD(txdesc) +#define SET_TX_DESC_ANT_MAPC_8821C(txdesc, value) \ + SET_TX_DESC_ANT_MAPC(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8821C(txdesc) GET_TX_DESC_ANT_MAPC(txdesc) +#define SET_TX_DESC_ANT_MAPB_8821C(txdesc, value) \ + SET_TX_DESC_ANT_MAPB(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8821C(txdesc) GET_TX_DESC_ANT_MAPB(txdesc) +#define SET_TX_DESC_ANT_MAPA_8821C(txdesc, value) \ + SET_TX_DESC_ANT_MAPA(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8821C(txdesc) GET_TX_DESC_ANT_MAPA(txdesc) +#define SET_TX_DESC_ANTSEL_C_8821C(txdesc, value) \ + SET_TX_DESC_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8821C(txdesc) GET_TX_DESC_ANTSEL_C(txdesc) +#define SET_TX_DESC_ANTSEL_B_8821C(txdesc, value) \ + SET_TX_DESC_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8821C(txdesc) GET_TX_DESC_ANTSEL_B(txdesc) +#define SET_TX_DESC_ANTSEL_A_8821C(txdesc, value) \ + SET_TX_DESC_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8821C(txdesc) GET_TX_DESC_ANTSEL_A(txdesc) +#define SET_TX_DESC_MBSSID_8821C(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8821C(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SW_DEFINE_8821C(txdesc, value) \ + SET_TX_DESC_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_SW_DEFINE_8821C(txdesc) GET_TX_DESC_SW_DEFINE(txdesc) /*TXDESC_WORD7*/ -#define SET_TX_DESC_DMA_TXAGG_NUM_8821C(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM_8821C(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) -#define SET_TX_DESC_FINAL_DATA_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_FINAL_DATA_RATE_8821C(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) -#define SET_TX_DESC_NTX_MAP_8821C(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) -#define GET_TX_DESC_NTX_MAP_8821C(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc) -#define SET_TX_DESC_TX_BUFF_SIZE_8821C(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE_8821C(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) -#define SET_TX_DESC_TXDESC_CHECKSUM_8821C(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM_8821C(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) -#define SET_TX_DESC_TIMESTAMP_8821C(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) -#define GET_TX_DESC_TIMESTAMP_8821C(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8821C(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8821C(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8821C(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8821C(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8821C(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8821C(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8821C(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8821C(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8821C(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8821C(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8821C(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8821C(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) /*TXDESC_WORD8*/ -#define SET_TX_DESC_TXWIFI_CP_8821C(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) -#define GET_TX_DESC_TXWIFI_CP_8821C(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc) -#define SET_TX_DESC_MAC_CP_8821C(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value) -#define GET_TX_DESC_MAC_CP_8821C(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc) -#define SET_TX_DESC_STW_PKTRE_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_PKTRE_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RB_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RB_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc) -#define SET_TX_DESC_STW_RATE_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_RATE_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc) -#define SET_TX_DESC_STW_ANT_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) -#define GET_TX_DESC_STW_ANT_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc) -#define SET_TX_DESC_STW_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value) -#define GET_TX_DESC_STW_EN_8821C(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc) -#define SET_TX_DESC_SMH_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value) -#define GET_TX_DESC_SMH_EN_8821C(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc) -#define SET_TX_DESC_TAILPAGE_L_8821C(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_L_8821C(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc) -#define SET_TX_DESC_SDIO_DMASEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SDIO_DMASEQ_8821C(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_L_8821C(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L_8821C(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) -#define SET_TX_DESC_EN_HWSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWSEQ_8821C(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc) -#define SET_TX_DESC_EN_HWEXSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWEXSEQ_8821C(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) -#define SET_TX_DESC_DATA_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RC_8821C(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc) -#define SET_TX_DESC_BAR_RTY_TH_8821C(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) -#define GET_TX_DESC_BAR_RTY_TH_8821C(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc) -#define SET_TX_DESC_RTS_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RC_8821C(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc) +#define SET_TX_DESC_TXWIFI_CP_8821C(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8821C(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8821C(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8821C(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8821C(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8821C(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8821C(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8821C(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8821C(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8821C(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8821C(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8821C(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8821C(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8821C(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8821C(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8821C(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8821C(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8821C(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8821C(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8821C(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8821C(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8821C(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8821C(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8821C(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8821C(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8821C(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8821C(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8821C(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8821C(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8821C(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8821C(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8821C(txdesc) GET_TX_DESC_RTS_RC(txdesc) /*TXDESC_WORD9*/ -#define SET_TX_DESC_TAILPAGE_H_8821C(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_H_8821C(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_H_8821C(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_H_8821C(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) -#define SET_TX_DESC_SW_SEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SW_SEQ_8821C(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc) -#define SET_TX_DESC_TXBF_PATH_8821C(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) -#define GET_TX_DESC_TXBF_PATH_8821C(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc) -#define SET_TX_DESC_PADDING_LEN_8821C(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_PADDING_LEN_8821C(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) +#define SET_TX_DESC_TAILPAGE_H_8821C(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8821C(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8821C(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8821C(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8821C(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8821C(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8821C(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8821C(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8821C(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8821C(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) /*WORD10*/ -#define SET_TX_DESC_MU_DATARATE_8821C(__pTxDesc, __Value) SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_MU_DATARATE_8821C(__pTxDesc) GET_TX_DESC_MU_DATARATE(__pTxDesc) -#define SET_TX_DESC_MU_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_MU_RC(__pTxDesc, __Value) -#define GET_TX_DESC_MU_RC_8821C(__pTxDesc) GET_TX_DESC_MU_RC(__pTxDesc) -#define SET_TX_DESC_SND_PKT_SEL_8821C(__pTxDesc, __Value) SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_SND_PKT_SEL_8821C(__pTxDesc) GET_TX_DESC_SND_PKT_SEL(__pTxDesc) +#define SET_TX_DESC_MU_DATARATE_8821C(txdesc, value) \ + SET_TX_DESC_MU_DATARATE(txdesc, value) +#define GET_TX_DESC_MU_DATARATE_8821C(txdesc) GET_TX_DESC_MU_DATARATE(txdesc) +#define SET_TX_DESC_MU_RC_8821C(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value) +#define GET_TX_DESC_MU_RC_8821C(txdesc) GET_TX_DESC_MU_RC(txdesc) +#define SET_TX_DESC_SND_PKT_SEL_8821C(txdesc, value) \ + SET_TX_DESC_SND_PKT_SEL(txdesc, value) +#define GET_TX_DESC_SND_PKT_SEL_8821C(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc) #endif -#if (HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) /*TXDESC_WORD0*/ -#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value) -#define GET_TX_DESC_GF_8188F(__pTxDesc) GET_TX_DESC_GF(__pTxDesc) -#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value) -#define GET_TX_DESC_NO_ACM_8188F(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc) -#define SET_TX_DESC_LS_8188F(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value) -#define GET_TX_DESC_LS_8188F(__pTxDesc) GET_TX_DESC_LS(__pTxDesc) -#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value) -#define GET_TX_DESC_HTC_8188F(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc) -#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value) -#define GET_TX_DESC_BMC_8188F(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc) -#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_OFFSET_8188F(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc) -#define SET_TX_DESC_TXPKTSIZE_8188F(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TXPKTSIZE_8188F(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc) - -/*TXDESC_WORD1*/ - -#define SET_TX_DESC_MOREDATA_8188F(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value) -#define GET_TX_DESC_MOREDATA_8188F(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc) -#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc) -#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) -#define GET_TX_DESC_SEC_TYPE_8188F(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc) -#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) -#define GET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc) -#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value) -#define GET_TX_DESC_RATE_ID_8188F(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc) -#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value) -#define GET_TX_DESC_PIFS_8188F(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc) -#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) -#define SET_TX_DESC_RD_NAV_EXT_8188F(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) -#define GET_TX_DESC_RD_NAV_EXT_8188F(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc) -#define SET_TX_DESC_QSEL_8188F(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value) -#define GET_TX_DESC_QSEL_8188F(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc) -#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value) -#define GET_TX_DESC_MACID_8188F(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc) +#define SET_TX_DESC_IE_END_BODY_8814B(txdesc, value) \ + SET_TX_DESC_IE_END_BODY(txdesc, value) +#define GET_TX_DESC_IE_END_BODY_8814B(txdesc) GET_TX_DESC_IE_END_BODY(txdesc) +#define SET_TX_DESC_AGG_EN_8814B(txdesc, value) \ + SET_TX_DESC_AGG_EN_V1(txdesc, value) +#define GET_TX_DESC_AGG_EN_8814B(txdesc) GET_TX_DESC_AGG_EN_V1(txdesc) +#define SET_TX_DESC_BK_8814B(txdesc, value) SET_TX_DESC_BK_V1(txdesc, value) +#define GET_TX_DESC_BK_8814B(txdesc) GET_TX_DESC_BK_V1(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8814B(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET_V1(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8814B(txdesc) GET_TX_DESC_PKT_OFFSET_V1(txdesc) +#define SET_TX_DESC_OFFSET_8814B(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8814B(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8814B(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8814B(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_AMSDU_8814B(txdesc, value) SET_TX_DESC_AMSDU(txdesc, value) +#define GET_TX_DESC_AMSDU_8814B(txdesc) GET_TX_DESC_AMSDU(txdesc) +#define SET_TX_DESC_HW_AES_IV_8814B(txdesc, value) \ + SET_TX_DESC_HW_AES_IV_V1(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8814B(txdesc) GET_TX_DESC_HW_AES_IV_V1(txdesc) +#define SET_TX_DESC_MHR_CP_8814B(txdesc, value) \ + SET_TX_DESC_MHR_CP(txdesc, value) +#define GET_TX_DESC_MHR_CP_8814B(txdesc) GET_TX_DESC_MHR_CP(txdesc) +#define SET_TX_DESC_SMH_EN_8814B(txdesc, value) \ + SET_TX_DESC_SMH_EN_V1(txdesc, value) +#define GET_TX_DESC_SMH_EN_8814B(txdesc) GET_TX_DESC_SMH_EN_V1(txdesc) +#define SET_TX_DESC_SMH_CAM_8814B(txdesc, value) \ + SET_TX_DESC_SMH_CAM(txdesc, value) +#define GET_TX_DESC_SMH_CAM_8814B(txdesc) GET_TX_DESC_SMH_CAM(txdesc) +#define SET_TX_DESC_EXT_EDCA_8814B(txdesc, value) \ + SET_TX_DESC_EXT_EDCA(txdesc, value) +#define GET_TX_DESC_EXT_EDCA_8814B(txdesc) GET_TX_DESC_EXT_EDCA(txdesc) +#define SET_TX_DESC_QSEL_8814B(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8814B(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8814B(txdesc, value) \ + SET_TX_DESC_MACID_V1(txdesc, value) +#define GET_TX_DESC_MACID_8814B(txdesc) GET_TX_DESC_MACID_V1(txdesc) /*TXDESC_WORD2*/ -#define SET_TX_DESC_FTM_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value) -#define GET_TX_DESC_FTM_EN_8188F(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc) -#define SET_TX_DESC_G_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value) -#define GET_TX_DESC_G_ID_8188F(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc) -#define SET_TX_DESC_BT_NULL_8188F(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value) -#define GET_TX_DESC_BT_NULL_8188F(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc) -#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) -#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) -#define GET_TX_DESC_SPE_RPT_8188F(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc) -#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value) -#define GET_TX_DESC_RAW_8188F(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc) -#define SET_TX_DESC_MOREFRAG_8188F(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) -#define GET_TX_DESC_MOREFRAG_8188F(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc) -#define SET_TX_DESC_BK_8188F(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value) -#define GET_TX_DESC_BK_8188F(__pTxDesc) GET_TX_DESC_BK(__pTxDesc) -#define SET_TX_DESC_NULL_1_8188F(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_1_8188F(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc) -#define SET_TX_DESC_NULL_0_8188F(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value) -#define GET_TX_DESC_NULL_0_8188F(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc) -#define SET_TX_DESC_RDG_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RDG_EN_8188F(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc) -#define SET_TX_DESC_AGG_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value) -#define GET_TX_DESC_AGG_EN_8188F(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc) -#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) -#define GET_TX_DESC_CCA_RTS_8188F(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc) -#define SET_TX_DESC_TRI_FRAME_8188F(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) -#define GET_TX_DESC_TRI_FRAME_8188F(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc) -#define SET_TX_DESC_P_AID_8188F(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value) -#define GET_TX_DESC_P_AID_8188F(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc) +#define SET_TX_DESC_CHK_EN_8814B(txdesc, value) \ + SET_TX_DESC_CHK_EN_V1(txdesc, value) +#define GET_TX_DESC_CHK_EN_8814B(txdesc) GET_TX_DESC_CHK_EN_V1(txdesc) +#define SET_TX_DESC_DMA_PRI_8814B(txdesc, value) \ + SET_TX_DESC_DMA_PRI(txdesc, value) +#define GET_TX_DESC_DMA_PRI_8814B(txdesc) GET_TX_DESC_DMA_PRI(txdesc) +#define SET_TX_DESC_MAX_AMSDU_MODE_8814B(txdesc, value) \ + SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value) +#define GET_TX_DESC_MAX_AMSDU_MODE_8814B(txdesc) \ + GET_TX_DESC_MAX_AMSDU_MODE(txdesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8814B(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8814B(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8814B(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8814B(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) -#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value) -#define GET_TX_DESC_NDPA_8188F(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc) -#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) -#define SET_TX_DESC_USE_MAX_TIME_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN_8188F(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) -#define SET_TX_DESC_NAVUSEHDR_8188F(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) -#define GET_TX_DESC_NAVUSEHDR_8188F(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc) -#define SET_TX_DESC_HW_RTS_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_HW_RTS_EN_8188F(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSEN_8188F(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value) -#define GET_TX_DESC_RTSEN_8188F(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc) -#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) -#define GET_TX_DESC_CTS2SELF_8188F(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc) -#define SET_TX_DESC_DISDATAFB_8188F(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISDATAFB_8188F(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc) -#define SET_TX_DESC_DISRTSFB_8188F(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) -#define GET_TX_DESC_DISRTSFB_8188F(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc) -#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_USE_RATE_8188F(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc) -#define SET_TX_DESC_HW_SSN_SEL_8188F(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) -#define GET_TX_DESC_HW_SSN_SEL_8188F(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc) +#define SET_TX_DESC_OFFLOAD_SIZE_8814B(txdesc, value) \ + SET_TX_DESC_OFFLOAD_SIZE(txdesc, value) +#define GET_TX_DESC_OFFLOAD_SIZE_8814B(txdesc) GET_TX_DESC_OFFLOAD_SIZE(txdesc) +#define SET_TX_DESC_CHANNEL_DMA_8814B(txdesc, value) \ + SET_TX_DESC_CHANNEL_DMA(txdesc, value) +#define GET_TX_DESC_CHANNEL_DMA_8814B(txdesc) GET_TX_DESC_CHANNEL_DMA(txdesc) +#define SET_TX_DESC_IE_CNT_8814B(txdesc, value) \ + SET_TX_DESC_IE_CNT(txdesc, value) +#define GET_TX_DESC_IE_CNT_8814B(txdesc) GET_TX_DESC_IE_CNT(txdesc) +#define SET_TX_DESC_IE_CNT_EN_8814B(txdesc, value) \ + SET_TX_DESC_IE_CNT_EN(txdesc, value) +#define GET_TX_DESC_IE_CNT_EN_8814B(txdesc) GET_TX_DESC_IE_CNT_EN(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8814B(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN_V1(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8814B(txdesc) GET_TX_DESC_WHEADER_LEN_V1(txdesc) /*TXDESC_WORD4*/ -#define SET_TX_DESC_PCTS_MASK_IDX_8188F(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX_8188F(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) -#define SET_TX_DESC_PCTS_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) -#define GET_TX_DESC_PCTS_EN_8188F(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc) -#define SET_TX_DESC_RTSRATE_8188F(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTSRATE_8188F(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc) -#define SET_TX_DESC_RTS_DATA_RTY_LMT_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT_8188F(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) -#define SET_TX_DESC_RTY_LMT_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) -#define GET_TX_DESC_RTY_LMT_EN_8188F(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8188F(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8188F(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) -#define SET_TX_DESC_TRY_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) -#define GET_TX_DESC_TRY_RATE_8188F(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc) -#define SET_TX_DESC_DATARATE_8188F(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value) -#define GET_TX_DESC_DATARATE_8188F(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc) +/*TXDESC_WORD5*/ + +/*TXDESC_WORD6*/ + +/*TXDESC_WORD7*/ + +/*TXDESC_WORD8*/ + +/*TXDESC_WORD9*/ + +/*WORD10*/ + +#endif + +#if (HALMAC_8198F_SUPPORT) + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_DISQSELSEQ_8198F(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8198F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8198F(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8198F(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8198F(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8198F(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8198F(txdesc, value) \ + SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8198F(txdesc) \ + GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8198F(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8198F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8198F(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8198F(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8198F(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8198F(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8198F(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8198F(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8198F(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8198F(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8198F(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8198F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_HW_AES_IV_8198F(txdesc, value) \ + SET_TX_DESC_HW_AES_IV_V2(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8198F(txdesc) GET_TX_DESC_HW_AES_IV_V2(txdesc) +#define SET_TX_DESC_FTM_EN_8198F(txdesc, value) \ + SET_TX_DESC_FTM_EN_V1(txdesc, value) +#define GET_TX_DESC_FTM_EN_8198F(txdesc) GET_TX_DESC_FTM_EN_V1(txdesc) +#define SET_TX_DESC_MOREDATA_8198F(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8198F(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8198F(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8198F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8198F(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8198F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8198F(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8198F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8198F(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8198F(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8198F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8198F(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8198F(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8198F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8198F(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8198F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8198F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8198F(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_SPECIAL_CW_8198F(txdesc, value) \ + SET_TX_DESC_SPECIAL_CW(txdesc, value) +#define GET_TX_DESC_SPECIAL_CW_8198F(txdesc) GET_TX_DESC_SPECIAL_CW(txdesc) +#define SET_TX_DESC_MACID_8198F(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8198F(txdesc) GET_TX_DESC_MACID(txdesc) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_ANTCEL_D_8198F(txdesc, value) \ + SET_TX_DESC_ANTCEL_D_V1(txdesc, value) +#define GET_TX_DESC_ANTCEL_D_8198F(txdesc) GET_TX_DESC_ANTCEL_D_V1(txdesc) +#define SET_TX_DESC_ANTSEL_C_8198F(txdesc, value) \ + SET_TX_DESC_ANTSEL_C_V1(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8198F(txdesc) GET_TX_DESC_ANTSEL_C_V1(txdesc) +#define SET_TX_DESC_BT_NULL_8198F(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8198F(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8198F(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8198F(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8198F(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8198F(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8198F(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8198F(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8198F(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8198F(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8198F(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8198F(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8198F(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8198F(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8198F(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8198F(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8198F(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8198F(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8198F(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8198F(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8198F(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8198F(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_TRI_FRAME_8198F(txdesc, value) \ + SET_TX_DESC_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_TRI_FRAME_8198F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc) +#define SET_TX_DESC_P_AID_8198F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8198F(txdesc) GET_TX_DESC_P_AID(txdesc) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_AMPDU_MAX_TIME_8198F(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8198F(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8198F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8198F(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8198F(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8198F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8198F(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8198F(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8198F(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8198F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8198F(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8198F(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8198F(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8198F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8198F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8198F(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8198F(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8198F(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8198F(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8198F(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8198F(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8198F(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8198F(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8198F(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8198F(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8198F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8198F(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8198F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_PCTS_MASK_IDX_8198F(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8198F(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8198F(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8198F(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8198F(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8198F(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8198F(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8198F(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8198F(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8198F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8198F(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8198F(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8198F(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8198F(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8198F(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8198F(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8198F(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8198F(txdesc) GET_TX_DESC_DATARATE(txdesc) /*TXDESC_WORD5*/ -#define SET_TX_DESC_TXPWR_OFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) -#define GET_TX_DESC_TXPWR_OFSET_8188F(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc) -#define SET_TX_DESC_TX_ANT_8188F(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value) -#define GET_TX_DESC_TX_ANT_8188F(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc) -#define SET_TX_DESC_PORT_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value) -#define GET_TX_DESC_PORT_ID_8188F(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc) -#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SC_8188F(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc) -#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_SHORT_8188F(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc) -#define SET_TX_DESC_RTS_STBC_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_STBC_8188F(__pTxDesc) GET_TX_DESC_RTS_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_STBC_8188F(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc) -#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_BW_8188F(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc) -#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SHORT_8188F(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc) -#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_SC_8188F(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc) +#define SET_TX_DESC_POLLUTED_8198F(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8198F(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_8198F(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_8198F(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc) +#define SET_TX_DESC_DROP_ID_8198F(txdesc, value) \ + SET_TX_DESC_DROP_ID(txdesc, value) +#define GET_TX_DESC_DROP_ID_8198F(txdesc) GET_TX_DESC_DROP_ID(txdesc) +#define SET_TX_DESC_PORT_ID_8198F(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8198F(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_MULTIPLE_PORT_8198F(txdesc, value) \ + SET_TX_DESC_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_MULTIPLE_PORT_8198F(txdesc) \ + GET_TX_DESC_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8198F(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8198F(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_RTS_SC_8198F(txdesc, value) \ + SET_TX_DESC_RTS_SC(txdesc, value) +#define GET_TX_DESC_RTS_SC_8198F(txdesc) GET_TX_DESC_RTS_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8198F(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8198F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8198F(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8198F(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8198F(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8198F(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8198F(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8198F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8198F(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8198F(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8198F(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8198F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8198F(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8198F(txdesc) GET_TX_DESC_DATA_SC(txdesc) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) -#define GET_TX_DESC_ANTSEL_A_8188F(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc) -#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value) -#define GET_TX_DESC_MBSSID_8188F(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc) -#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) -#define GET_TX_DESC_SW_DEFINE_8188F(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc) +#define SET_TX_DESC_ANT_MAPD_8198F(txdesc, value) \ + SET_TX_DESC_ANT_MAPD_V1(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8198F(txdesc) GET_TX_DESC_ANT_MAPD_V1(txdesc) +#define SET_TX_DESC_ANT_MAPC_8198F(txdesc, value) \ + SET_TX_DESC_ANT_MAPC_V1(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8198F(txdesc) GET_TX_DESC_ANT_MAPC_V1(txdesc) +#define SET_TX_DESC_ANT_MAPB_8198F(txdesc, value) \ + SET_TX_DESC_ANT_MAPB_V1(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8198F(txdesc) GET_TX_DESC_ANT_MAPB_V1(txdesc) +#define SET_TX_DESC_ANT_MAPA_8198F(txdesc, value) \ + SET_TX_DESC_ANT_MAPA_V1(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8198F(txdesc) GET_TX_DESC_ANT_MAPA_V1(txdesc) +#define SET_TX_DESC_ANTSEL_B_8198F(txdesc, value) \ + SET_TX_DESC_ANTSEL_B_V1(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8198F(txdesc) GET_TX_DESC_ANTSEL_B_V1(txdesc) +#define SET_TX_DESC_ANTSEL_A_8198F(txdesc, value) \ + SET_TX_DESC_ANTSEL_A_V1(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8198F(txdesc) GET_TX_DESC_ANTSEL_A_V1(txdesc) +#define SET_TX_DESC_MBSSID_8198F(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8198F(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SWPS_SEQ_8198F(txdesc, value) \ + SET_TX_DESC_SWPS_SEQ(txdesc, value) +#define GET_TX_DESC_SWPS_SEQ_8198F(txdesc) GET_TX_DESC_SWPS_SEQ(txdesc) /*TXDESC_WORD7*/ -#define SET_TX_DESC_DMA_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM_8188F(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) -#define SET_TX_DESC_TX_BUFF_SIZE_8188F(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE_8188F(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) -#define SET_TX_DESC_TXDESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM_8188F(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) -#define SET_TX_DESC_TIMESTAMP_8188F(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) -#define GET_TX_DESC_TIMESTAMP_8188F(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc) +#define SET_TX_DESC_DMA_TXAGG_NUM_8198F(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8198F(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8198F(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8198F(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8198F(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8198F(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_ANTSEL_EN_8198F(txdesc, value) \ + SET_TX_DESC_ANTSEL_EN(txdesc, value) +#define GET_TX_DESC_ANTSEL_EN_8198F(txdesc) GET_TX_DESC_ANTSEL_EN(txdesc) +#define SET_TX_DESC_MBSSID_EX_8198F(txdesc, value) \ + SET_TX_DESC_MBSSID_EX(txdesc, value) +#define GET_TX_DESC_MBSSID_EX_8198F(txdesc) GET_TX_DESC_MBSSID_EX(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8198F(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8198F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8198F(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8198F(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8198F(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8198F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) /*TXDESC_WORD8*/ -#define SET_TX_DESC_TAILPAGE_L_8188F(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_TAILPAGE_L_8188F(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc) -#define SET_TX_DESC_NEXTHEADPAGE_L_8188F(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L_8188F(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) -#define SET_TX_DESC_EN_HWSEQ_8188F(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) -#define GET_TX_DESC_EN_HWSEQ_8188F(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc) -#define SET_TX_DESC_DATA_RC_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value) -#define GET_TX_DESC_DATA_RC_8188F(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc) -#define SET_TX_DESC_BAR_RTY_TH_8188F(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) -#define GET_TX_DESC_BAR_RTY_TH_8188F(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc) -#define SET_TX_DESC_RTS_RC_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value) -#define GET_TX_DESC_RTS_RC_8188F(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc) +#define SET_TX_DESC_TXWIFI_CP_8198F(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8198F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8198F(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8198F(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8198F(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8198F(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8198F(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8198F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8198F(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8198F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8198F(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8198F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8198F(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8198F(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8198F(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8198F(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8198F(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8198F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8198F(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8198F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8198F(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8198F(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8198F(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8198F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8198F(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8198F(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8198F(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8198F(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8198F(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8198F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8198F(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8198F(txdesc) GET_TX_DESC_RTS_RC(txdesc) /*TXDESC_WORD9*/ -#define SET_TX_DESC_SW_SEQ_8188F(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) -#define GET_TX_DESC_SW_SEQ_8188F(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc) -#define SET_TX_DESC_TXBF_PATH_8188F(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) -#define GET_TX_DESC_TXBF_PATH_8188F(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc) -#define SET_TX_DESC_PADDING_LEN_8188F(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) -#define GET_TX_DESC_PADDING_LEN_8188F(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8188F(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) +#define SET_TX_DESC_TAILPAGE_H_8198F(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8198F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8198F(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8198F(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8198F(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8198F(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8198F(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8198F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8198F(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8198F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8198F(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8198F(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) /*WORD10*/ +#endif + +#if (HALMAC_8822C_SUPPORT) + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_DISQSELSEQ_8822C(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8822C(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8822C(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8822C(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8822C(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8822C(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822C(txdesc, value) \ + SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822C(txdesc) \ + GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8822C(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8822C(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8822C(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8822C(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8822C(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8822C(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8822C(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8822C(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8822C(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8822C(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8822C(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8822C(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_MOREDATA_8822C(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8822C(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8822C(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8822C(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8822C(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8822C(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8822C(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8822C(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8822C(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8822C(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8822C(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8822C(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8822C(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8822C(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8822C(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8822C(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8822C(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8822C(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8822C(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8822C(txdesc) GET_TX_DESC_MACID(txdesc) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_HW_AES_IV_8822C(txdesc, value) \ + SET_TX_DESC_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8822C(txdesc) GET_TX_DESC_HW_AES_IV(txdesc) +#define SET_TX_DESC_FTM_EN_8822C(txdesc, value) \ + SET_TX_DESC_FTM_EN(txdesc, value) +#define GET_TX_DESC_FTM_EN_8822C(txdesc) GET_TX_DESC_FTM_EN(txdesc) +#define SET_TX_DESC_G_ID_8822C(txdesc, value) SET_TX_DESC_G_ID(txdesc, value) +#define GET_TX_DESC_G_ID_8822C(txdesc) GET_TX_DESC_G_ID(txdesc) +#define SET_TX_DESC_BT_NULL_8822C(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8822C(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8822C(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8822C(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8822C(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8822C(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8822C(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8822C(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8822C(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8822C(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8822C(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8822C(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8822C(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8822C(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8822C(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8822C(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8822C(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8822C(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8822C(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8822C(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8822C(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8822C(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_TRI_FRAME_8822C(txdesc, value) \ + SET_TX_DESC_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_TRI_FRAME_8822C(txdesc) GET_TX_DESC_TRI_FRAME(txdesc) +#define SET_TX_DESC_P_AID_8822C(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8822C(txdesc) GET_TX_DESC_P_AID(txdesc) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_AMPDU_MAX_TIME_8822C(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8822C(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8822C(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8822C(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8822C(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8822C(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8822C(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8822C(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8822C(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8822C(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8822C(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8822C(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8822C(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8822C(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8822C(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8822C(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8822C(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8822C(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8822C(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8822C(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8822C(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8822C(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8822C(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8822C(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8822C(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8822C(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8822C(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8822C(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_PCTS_MASK_IDX_8822C(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8822C(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8822C(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8822C(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8822C(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8822C(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822C(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822C(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8822C(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8822C(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8822C(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8822C(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8822C(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8822C(txdesc) GET_TX_DESC_DATARATE(txdesc) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_POLLUTED_8822C(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8822C(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_ANTSEL_EN_8822C(txdesc, value) \ + SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) +#define GET_TX_DESC_ANTSEL_EN_8822C(txdesc) GET_TX_DESC_ANTSEL_EN_V1(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_TYPE_8822C(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_TYPE_8822C(txdesc) \ + GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc) +#define SET_TX_DESC_TX_ANT_8822C(txdesc, value) \ + SET_TX_DESC_TX_ANT(txdesc, value) +#define GET_TX_DESC_TX_ANT_8822C(txdesc) GET_TX_DESC_TX_ANT(txdesc) +#define SET_TX_DESC_PORT_ID_8822C(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8822C(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_MULTIPLE_PORT_8822C(txdesc, value) \ + SET_TX_DESC_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_MULTIPLE_PORT_8822C(txdesc) \ + GET_TX_DESC_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822C(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822C(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(txdesc, value) \ + SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) +#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(txdesc) \ + GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8822C(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8822C(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8822C(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8822C(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8822C(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8822C(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8822C(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8822C(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8822C(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8822C(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8822C(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8822C(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8822C(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8822C(txdesc) GET_TX_DESC_DATA_SC(txdesc) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_ANTSEL_D_8822C(txdesc, value) \ + SET_TX_DESC_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_ANTSEL_D_8822C(txdesc) GET_TX_DESC_ANTSEL_D(txdesc) +#define SET_TX_DESC_ANT_MAPD_8822C(txdesc, value) \ + SET_TX_DESC_ANT_MAPD(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8822C(txdesc) GET_TX_DESC_ANT_MAPD(txdesc) +#define SET_TX_DESC_ANT_MAPC_8822C(txdesc, value) \ + SET_TX_DESC_ANT_MAPC(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8822C(txdesc) GET_TX_DESC_ANT_MAPC(txdesc) +#define SET_TX_DESC_ANT_MAPB_8822C(txdesc, value) \ + SET_TX_DESC_ANT_MAPB(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8822C(txdesc) GET_TX_DESC_ANT_MAPB(txdesc) +#define SET_TX_DESC_ANT_MAPA_8822C(txdesc, value) \ + SET_TX_DESC_ANT_MAPA(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8822C(txdesc) GET_TX_DESC_ANT_MAPA(txdesc) +#define SET_TX_DESC_ANTSEL_C_8822C(txdesc, value) \ + SET_TX_DESC_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8822C(txdesc) GET_TX_DESC_ANTSEL_C(txdesc) +#define SET_TX_DESC_ANTSEL_B_8822C(txdesc, value) \ + SET_TX_DESC_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8822C(txdesc) GET_TX_DESC_ANTSEL_B(txdesc) +#define SET_TX_DESC_ANTSEL_A_8822C(txdesc, value) \ + SET_TX_DESC_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8822C(txdesc) GET_TX_DESC_ANTSEL_A(txdesc) +#define SET_TX_DESC_MBSSID_8822C(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8822C(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SW_DEFINE_8822C(txdesc, value) \ + SET_TX_DESC_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_SW_DEFINE_8822C(txdesc) GET_TX_DESC_SW_DEFINE(txdesc) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_DMA_TXAGG_NUM_8822C(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8822C(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8822C(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8822C(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8822C(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8822C(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8822C(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8822C(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8822C(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8822C(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8822C(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8822C(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_TXWIFI_CP_8822C(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8822C(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8822C(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8822C(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8822C(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8822C(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8822C(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8822C(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8822C(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8822C(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8822C(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8822C(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8822C(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8822C(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8822C(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8822C(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8822C(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8822C(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8822C(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8822C(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8822C(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8822C(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_8822C(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_8822C(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc) +#define SET_TX_DESC_EN_HWEXSEQ_8822C(txdesc, value) \ + SET_TX_DESC_EN_HWEXSEQ(txdesc, value) +#define GET_TX_DESC_EN_HWEXSEQ_8822C(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc) +#define SET_TX_DESC_DATA_RC_8822C(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8822C(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8822C(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8822C(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8822C(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8822C(txdesc) GET_TX_DESC_RTS_RC(txdesc) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_TAILPAGE_H_8822C(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8822C(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8822C(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8822C(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8822C(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8822C(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8822C(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8822C(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8822C(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8822C(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822C(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822C(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) + +/*WORD10*/ + +#define SET_TX_DESC_MU_DATARATE_8822C(txdesc, value) \ + SET_TX_DESC_MU_DATARATE(txdesc, value) +#define GET_TX_DESC_MU_DATARATE_8822C(txdesc) GET_TX_DESC_MU_DATARATE(txdesc) +#define SET_TX_DESC_MU_RC_8822C(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value) +#define GET_TX_DESC_MU_RC_8822C(txdesc) GET_TX_DESC_MU_RC(txdesc) +#define SET_TX_DESC_SND_PKT_SEL_8822C(txdesc, value) \ + SET_TX_DESC_SND_PKT_SEL(txdesc, value) +#define GET_TX_DESC_SND_PKT_SEL_8822C(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc) #endif +#if (HALMAC_8812F_SUPPORT) + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_DISQSELSEQ_8812F(txdesc, value) \ + SET_TX_DESC_DISQSELSEQ(txdesc, value) +#define GET_TX_DESC_DISQSELSEQ_8812F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc) +#define SET_TX_DESC_GF_8812F(txdesc, value) SET_TX_DESC_GF(txdesc, value) +#define GET_TX_DESC_GF_8812F(txdesc) GET_TX_DESC_GF(txdesc) +#define SET_TX_DESC_NO_ACM_8812F(txdesc, value) \ + SET_TX_DESC_NO_ACM(txdesc, value) +#define GET_TX_DESC_NO_ACM_8812F(txdesc) GET_TX_DESC_NO_ACM(txdesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8812F(txdesc, value) \ + SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8812F(txdesc) \ + GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8812F(txdesc, value) \ + SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) +#define GET_TX_DESC_AMSDU_PAD_EN_8812F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc) +#define SET_TX_DESC_LS_8812F(txdesc, value) SET_TX_DESC_LS(txdesc, value) +#define GET_TX_DESC_LS_8812F(txdesc) GET_TX_DESC_LS(txdesc) +#define SET_TX_DESC_HTC_8812F(txdesc, value) SET_TX_DESC_HTC(txdesc, value) +#define GET_TX_DESC_HTC_8812F(txdesc) GET_TX_DESC_HTC(txdesc) +#define SET_TX_DESC_BMC_8812F(txdesc, value) SET_TX_DESC_BMC(txdesc, value) +#define GET_TX_DESC_BMC_8812F(txdesc) GET_TX_DESC_BMC(txdesc) +#define SET_TX_DESC_OFFSET_8812F(txdesc, value) \ + SET_TX_DESC_OFFSET(txdesc, value) +#define GET_TX_DESC_OFFSET_8812F(txdesc) GET_TX_DESC_OFFSET(txdesc) +#define SET_TX_DESC_TXPKTSIZE_8812F(txdesc, value) \ + SET_TX_DESC_TXPKTSIZE(txdesc, value) +#define GET_TX_DESC_TXPKTSIZE_8812F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc) + +/*WORD1*/ + +#define SET_TX_DESC_MOREDATA_8812F(txdesc, value) \ + SET_TX_DESC_MOREDATA(txdesc, value) +#define GET_TX_DESC_MOREDATA_8812F(txdesc) GET_TX_DESC_MOREDATA(txdesc) +#define SET_TX_DESC_PKT_OFFSET_8812F(txdesc, value) \ + SET_TX_DESC_PKT_OFFSET(txdesc, value) +#define GET_TX_DESC_PKT_OFFSET_8812F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc) +#define SET_TX_DESC_SEC_TYPE_8812F(txdesc, value) \ + SET_TX_DESC_SEC_TYPE(txdesc, value) +#define GET_TX_DESC_SEC_TYPE_8812F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc) +#define SET_TX_DESC_EN_DESC_ID_8812F(txdesc, value) \ + SET_TX_DESC_EN_DESC_ID(txdesc, value) +#define GET_TX_DESC_EN_DESC_ID_8812F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc) +#define SET_TX_DESC_RATE_ID_8812F(txdesc, value) \ + SET_TX_DESC_RATE_ID(txdesc, value) +#define GET_TX_DESC_RATE_ID_8812F(txdesc) GET_TX_DESC_RATE_ID(txdesc) +#define SET_TX_DESC_PIFS_8812F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value) +#define GET_TX_DESC_PIFS_8812F(txdesc) GET_TX_DESC_PIFS(txdesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8812F(txdesc, value) \ + SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) +#define GET_TX_DESC_LSIG_TXOP_EN_8812F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc) +#define SET_TX_DESC_RD_NAV_EXT_8812F(txdesc, value) \ + SET_TX_DESC_RD_NAV_EXT(txdesc, value) +#define GET_TX_DESC_RD_NAV_EXT_8812F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc) +#define SET_TX_DESC_QSEL_8812F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value) +#define GET_TX_DESC_QSEL_8812F(txdesc) GET_TX_DESC_QSEL(txdesc) +#define SET_TX_DESC_MACID_8812F(txdesc, value) SET_TX_DESC_MACID(txdesc, value) +#define GET_TX_DESC_MACID_8812F(txdesc) GET_TX_DESC_MACID(txdesc) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_HW_AES_IV_8812F(txdesc, value) \ + SET_TX_DESC_HW_AES_IV(txdesc, value) +#define GET_TX_DESC_HW_AES_IV_8812F(txdesc) GET_TX_DESC_HW_AES_IV(txdesc) +#define SET_TX_DESC_FTM_EN_8812F(txdesc, value) \ + SET_TX_DESC_FTM_EN(txdesc, value) +#define GET_TX_DESC_FTM_EN_8812F(txdesc) GET_TX_DESC_FTM_EN(txdesc) +#define SET_TX_DESC_G_ID_8812F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value) +#define GET_TX_DESC_G_ID_8812F(txdesc) GET_TX_DESC_G_ID(txdesc) +#define SET_TX_DESC_BT_NULL_8812F(txdesc, value) \ + SET_TX_DESC_BT_NULL(txdesc, value) +#define GET_TX_DESC_BT_NULL_8812F(txdesc) GET_TX_DESC_BT_NULL(txdesc) +#define SET_TX_DESC_AMPDU_DENSITY_8812F(txdesc, value) \ + SET_TX_DESC_AMPDU_DENSITY(txdesc, value) +#define GET_TX_DESC_AMPDU_DENSITY_8812F(txdesc) \ + GET_TX_DESC_AMPDU_DENSITY(txdesc) +#define SET_TX_DESC_SPE_RPT_8812F(txdesc, value) \ + SET_TX_DESC_SPE_RPT(txdesc, value) +#define GET_TX_DESC_SPE_RPT_8812F(txdesc) GET_TX_DESC_SPE_RPT(txdesc) +#define SET_TX_DESC_RAW_8812F(txdesc, value) SET_TX_DESC_RAW(txdesc, value) +#define GET_TX_DESC_RAW_8812F(txdesc) GET_TX_DESC_RAW(txdesc) +#define SET_TX_DESC_MOREFRAG_8812F(txdesc, value) \ + SET_TX_DESC_MOREFRAG(txdesc, value) +#define GET_TX_DESC_MOREFRAG_8812F(txdesc) GET_TX_DESC_MOREFRAG(txdesc) +#define SET_TX_DESC_BK_8812F(txdesc, value) SET_TX_DESC_BK(txdesc, value) +#define GET_TX_DESC_BK_8812F(txdesc) GET_TX_DESC_BK(txdesc) +#define SET_TX_DESC_NULL_1_8812F(txdesc, value) \ + SET_TX_DESC_NULL_1(txdesc, value) +#define GET_TX_DESC_NULL_1_8812F(txdesc) GET_TX_DESC_NULL_1(txdesc) +#define SET_TX_DESC_NULL_0_8812F(txdesc, value) \ + SET_TX_DESC_NULL_0(txdesc, value) +#define GET_TX_DESC_NULL_0_8812F(txdesc) GET_TX_DESC_NULL_0(txdesc) +#define SET_TX_DESC_RDG_EN_8812F(txdesc, value) \ + SET_TX_DESC_RDG_EN(txdesc, value) +#define GET_TX_DESC_RDG_EN_8812F(txdesc) GET_TX_DESC_RDG_EN(txdesc) +#define SET_TX_DESC_AGG_EN_8812F(txdesc, value) \ + SET_TX_DESC_AGG_EN(txdesc, value) +#define GET_TX_DESC_AGG_EN_8812F(txdesc) GET_TX_DESC_AGG_EN(txdesc) +#define SET_TX_DESC_CCA_RTS_8812F(txdesc, value) \ + SET_TX_DESC_CCA_RTS(txdesc, value) +#define GET_TX_DESC_CCA_RTS_8812F(txdesc) GET_TX_DESC_CCA_RTS(txdesc) +#define SET_TX_DESC_TRI_FRAME_8812F(txdesc, value) \ + SET_TX_DESC_TRI_FRAME(txdesc, value) +#define GET_TX_DESC_TRI_FRAME_8812F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc) +#define SET_TX_DESC_P_AID_8812F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value) +#define GET_TX_DESC_P_AID_8812F(txdesc) GET_TX_DESC_P_AID(txdesc) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_AMPDU_MAX_TIME_8812F(txdesc, value) \ + SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8812F(txdesc) \ + GET_TX_DESC_AMPDU_MAX_TIME(txdesc) +#define SET_TX_DESC_NDPA_8812F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value) +#define GET_TX_DESC_NDPA_8812F(txdesc) GET_TX_DESC_NDPA(txdesc) +#define SET_TX_DESC_MAX_AGG_NUM_8812F(txdesc, value) \ + SET_TX_DESC_MAX_AGG_NUM(txdesc, value) +#define GET_TX_DESC_MAX_AGG_NUM_8812F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8812F(txdesc, value) \ + SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8812F(txdesc) \ + GET_TX_DESC_USE_MAX_TIME_EN(txdesc) +#define SET_TX_DESC_NAVUSEHDR_8812F(txdesc, value) \ + SET_TX_DESC_NAVUSEHDR(txdesc, value) +#define GET_TX_DESC_NAVUSEHDR_8812F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc) +#define SET_TX_DESC_CHK_EN_8812F(txdesc, value) \ + SET_TX_DESC_CHK_EN(txdesc, value) +#define GET_TX_DESC_CHK_EN_8812F(txdesc) GET_TX_DESC_CHK_EN(txdesc) +#define SET_TX_DESC_HW_RTS_EN_8812F(txdesc, value) \ + SET_TX_DESC_HW_RTS_EN(txdesc, value) +#define GET_TX_DESC_HW_RTS_EN_8812F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc) +#define SET_TX_DESC_RTSEN_8812F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value) +#define GET_TX_DESC_RTSEN_8812F(txdesc) GET_TX_DESC_RTSEN(txdesc) +#define SET_TX_DESC_CTS2SELF_8812F(txdesc, value) \ + SET_TX_DESC_CTS2SELF(txdesc, value) +#define GET_TX_DESC_CTS2SELF_8812F(txdesc) GET_TX_DESC_CTS2SELF(txdesc) +#define SET_TX_DESC_DISDATAFB_8812F(txdesc, value) \ + SET_TX_DESC_DISDATAFB(txdesc, value) +#define GET_TX_DESC_DISDATAFB_8812F(txdesc) GET_TX_DESC_DISDATAFB(txdesc) +#define SET_TX_DESC_DISRTSFB_8812F(txdesc, value) \ + SET_TX_DESC_DISRTSFB(txdesc, value) +#define GET_TX_DESC_DISRTSFB_8812F(txdesc) GET_TX_DESC_DISRTSFB(txdesc) +#define SET_TX_DESC_USE_RATE_8812F(txdesc, value) \ + SET_TX_DESC_USE_RATE(txdesc, value) +#define GET_TX_DESC_USE_RATE_8812F(txdesc) GET_TX_DESC_USE_RATE(txdesc) +#define SET_TX_DESC_HW_SSN_SEL_8812F(txdesc, value) \ + SET_TX_DESC_HW_SSN_SEL(txdesc, value) +#define GET_TX_DESC_HW_SSN_SEL_8812F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc) +#define SET_TX_DESC_WHEADER_LEN_8812F(txdesc, value) \ + SET_TX_DESC_WHEADER_LEN(txdesc, value) +#define GET_TX_DESC_WHEADER_LEN_8812F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_PCTS_MASK_IDX_8812F(txdesc, value) \ + SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) +#define GET_TX_DESC_PCTS_MASK_IDX_8812F(txdesc) \ + GET_TX_DESC_PCTS_MASK_IDX(txdesc) +#define SET_TX_DESC_PCTS_EN_8812F(txdesc, value) \ + SET_TX_DESC_PCTS_EN(txdesc, value) +#define GET_TX_DESC_PCTS_EN_8812F(txdesc) GET_TX_DESC_PCTS_EN(txdesc) +#define SET_TX_DESC_RTSRATE_8812F(txdesc, value) \ + SET_TX_DESC_RTSRATE(txdesc, value) +#define GET_TX_DESC_RTSRATE_8812F(txdesc) GET_TX_DESC_RTSRATE(txdesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8812F(txdesc, value) \ + SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8812F(txdesc) \ + GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) +#define SET_TX_DESC_RTY_LMT_EN_8812F(txdesc, value) \ + SET_TX_DESC_RTY_LMT_EN(txdesc, value) +#define GET_TX_DESC_RTY_LMT_EN_8812F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8812F(txdesc, value) \ + SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8812F(txdesc) \ + GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8812F(txdesc, value) \ + SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8812F(txdesc) \ + GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) +#define SET_TX_DESC_TRY_RATE_8812F(txdesc, value) \ + SET_TX_DESC_TRY_RATE(txdesc, value) +#define GET_TX_DESC_TRY_RATE_8812F(txdesc) GET_TX_DESC_TRY_RATE(txdesc) +#define SET_TX_DESC_DATARATE_8812F(txdesc, value) \ + SET_TX_DESC_DATARATE(txdesc, value) +#define GET_TX_DESC_DATARATE_8812F(txdesc) GET_TX_DESC_DATARATE(txdesc) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_POLLUTED_8812F(txdesc, value) \ + SET_TX_DESC_POLLUTED(txdesc, value) +#define GET_TX_DESC_POLLUTED_8812F(txdesc) GET_TX_DESC_POLLUTED(txdesc) +#define SET_TX_DESC_ANTSEL_EN_8812F(txdesc, value) \ + SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) +#define GET_TX_DESC_ANTSEL_EN_8812F(txdesc) GET_TX_DESC_ANTSEL_EN_V1(txdesc) +#define SET_TX_DESC_TXPWR_OFSET_TYPE_8812F(txdesc, value) \ + SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) +#define GET_TX_DESC_TXPWR_OFSET_TYPE_8812F(txdesc) \ + GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc) +#define SET_TX_DESC_TX_ANT_8812F(txdesc, value) \ + SET_TX_DESC_TX_ANT(txdesc, value) +#define GET_TX_DESC_TX_ANT_8812F(txdesc) GET_TX_DESC_TX_ANT(txdesc) +#define SET_TX_DESC_PORT_ID_8812F(txdesc, value) \ + SET_TX_DESC_PORT_ID(txdesc, value) +#define GET_TX_DESC_PORT_ID_8812F(txdesc) GET_TX_DESC_PORT_ID(txdesc) +#define SET_TX_DESC_MULTIPLE_PORT_8812F(txdesc, value) \ + SET_TX_DESC_MULTIPLE_PORT(txdesc, value) +#define GET_TX_DESC_MULTIPLE_PORT_8812F(txdesc) \ + GET_TX_DESC_MULTIPLE_PORT(txdesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8812F(txdesc, value) \ + SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8812F(txdesc) \ + GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8812F(txdesc, value) \ + SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) +#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8812F(txdesc) \ + GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) +#define SET_TX_DESC_RTS_SHORT_8812F(txdesc, value) \ + SET_TX_DESC_RTS_SHORT(txdesc, value) +#define GET_TX_DESC_RTS_SHORT_8812F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc) +#define SET_TX_DESC_VCS_STBC_8812F(txdesc, value) \ + SET_TX_DESC_VCS_STBC(txdesc, value) +#define GET_TX_DESC_VCS_STBC_8812F(txdesc) GET_TX_DESC_VCS_STBC(txdesc) +#define SET_TX_DESC_DATA_STBC_8812F(txdesc, value) \ + SET_TX_DESC_DATA_STBC(txdesc, value) +#define GET_TX_DESC_DATA_STBC_8812F(txdesc) GET_TX_DESC_DATA_STBC(txdesc) +#define SET_TX_DESC_DATA_LDPC_8812F(txdesc, value) \ + SET_TX_DESC_DATA_LDPC(txdesc, value) +#define GET_TX_DESC_DATA_LDPC_8812F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc) +#define SET_TX_DESC_DATA_BW_8812F(txdesc, value) \ + SET_TX_DESC_DATA_BW(txdesc, value) +#define GET_TX_DESC_DATA_BW_8812F(txdesc) GET_TX_DESC_DATA_BW(txdesc) +#define SET_TX_DESC_DATA_SHORT_8812F(txdesc, value) \ + SET_TX_DESC_DATA_SHORT(txdesc, value) +#define GET_TX_DESC_DATA_SHORT_8812F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc) +#define SET_TX_DESC_DATA_SC_8812F(txdesc, value) \ + SET_TX_DESC_DATA_SC(txdesc, value) +#define GET_TX_DESC_DATA_SC_8812F(txdesc) GET_TX_DESC_DATA_SC(txdesc) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_ANTSEL_D_8812F(txdesc, value) \ + SET_TX_DESC_ANTSEL_D(txdesc, value) +#define GET_TX_DESC_ANTSEL_D_8812F(txdesc) GET_TX_DESC_ANTSEL_D(txdesc) +#define SET_TX_DESC_ANT_MAPD_8812F(txdesc, value) \ + SET_TX_DESC_ANT_MAPD(txdesc, value) +#define GET_TX_DESC_ANT_MAPD_8812F(txdesc) GET_TX_DESC_ANT_MAPD(txdesc) +#define SET_TX_DESC_ANT_MAPC_8812F(txdesc, value) \ + SET_TX_DESC_ANT_MAPC(txdesc, value) +#define GET_TX_DESC_ANT_MAPC_8812F(txdesc) GET_TX_DESC_ANT_MAPC(txdesc) +#define SET_TX_DESC_ANT_MAPB_8812F(txdesc, value) \ + SET_TX_DESC_ANT_MAPB(txdesc, value) +#define GET_TX_DESC_ANT_MAPB_8812F(txdesc) GET_TX_DESC_ANT_MAPB(txdesc) +#define SET_TX_DESC_ANT_MAPA_8812F(txdesc, value) \ + SET_TX_DESC_ANT_MAPA(txdesc, value) +#define GET_TX_DESC_ANT_MAPA_8812F(txdesc) GET_TX_DESC_ANT_MAPA(txdesc) +#define SET_TX_DESC_ANTSEL_C_8812F(txdesc, value) \ + SET_TX_DESC_ANTSEL_C(txdesc, value) +#define GET_TX_DESC_ANTSEL_C_8812F(txdesc) GET_TX_DESC_ANTSEL_C(txdesc) +#define SET_TX_DESC_ANTSEL_B_8812F(txdesc, value) \ + SET_TX_DESC_ANTSEL_B(txdesc, value) +#define GET_TX_DESC_ANTSEL_B_8812F(txdesc) GET_TX_DESC_ANTSEL_B(txdesc) +#define SET_TX_DESC_ANTSEL_A_8812F(txdesc, value) \ + SET_TX_DESC_ANTSEL_A(txdesc, value) +#define GET_TX_DESC_ANTSEL_A_8812F(txdesc) GET_TX_DESC_ANTSEL_A(txdesc) +#define SET_TX_DESC_MBSSID_8812F(txdesc, value) \ + SET_TX_DESC_MBSSID(txdesc, value) +#define GET_TX_DESC_MBSSID_8812F(txdesc) GET_TX_DESC_MBSSID(txdesc) +#define SET_TX_DESC_SW_DEFINE_8812F(txdesc, value) \ + SET_TX_DESC_SW_DEFINE(txdesc, value) +#define GET_TX_DESC_SW_DEFINE_8812F(txdesc) GET_TX_DESC_SW_DEFINE(txdesc) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_DMA_TXAGG_NUM_8812F(txdesc, value) \ + SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8812F(txdesc) \ + GET_TX_DESC_DMA_TXAGG_NUM(txdesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8812F(txdesc, value) \ + SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) +#define GET_TX_DESC_FINAL_DATA_RATE_8812F(txdesc) \ + GET_TX_DESC_FINAL_DATA_RATE(txdesc) +#define SET_TX_DESC_NTX_MAP_8812F(txdesc, value) \ + SET_TX_DESC_NTX_MAP(txdesc, value) +#define GET_TX_DESC_NTX_MAP_8812F(txdesc) GET_TX_DESC_NTX_MAP(txdesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8812F(txdesc, value) \ + SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) +#define GET_TX_DESC_TX_BUFF_SIZE_8812F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8812F(txdesc, value) \ + SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8812F(txdesc) \ + GET_TX_DESC_TXDESC_CHECKSUM(txdesc) +#define SET_TX_DESC_TIMESTAMP_8812F(txdesc, value) \ + SET_TX_DESC_TIMESTAMP(txdesc, value) +#define GET_TX_DESC_TIMESTAMP_8812F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_TXWIFI_CP_8812F(txdesc, value) \ + SET_TX_DESC_TXWIFI_CP(txdesc, value) +#define GET_TX_DESC_TXWIFI_CP_8812F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc) +#define SET_TX_DESC_MAC_CP_8812F(txdesc, value) \ + SET_TX_DESC_MAC_CP(txdesc, value) +#define GET_TX_DESC_MAC_CP_8812F(txdesc) GET_TX_DESC_MAC_CP(txdesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8812F(txdesc, value) \ + SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) +#define GET_TX_DESC_STW_PKTRE_DIS_8812F(txdesc) \ + GET_TX_DESC_STW_PKTRE_DIS(txdesc) +#define SET_TX_DESC_STW_RB_DIS_8812F(txdesc, value) \ + SET_TX_DESC_STW_RB_DIS(txdesc, value) +#define GET_TX_DESC_STW_RB_DIS_8812F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc) +#define SET_TX_DESC_STW_RATE_DIS_8812F(txdesc, value) \ + SET_TX_DESC_STW_RATE_DIS(txdesc, value) +#define GET_TX_DESC_STW_RATE_DIS_8812F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc) +#define SET_TX_DESC_STW_ANT_DIS_8812F(txdesc, value) \ + SET_TX_DESC_STW_ANT_DIS(txdesc, value) +#define GET_TX_DESC_STW_ANT_DIS_8812F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc) +#define SET_TX_DESC_STW_EN_8812F(txdesc, value) \ + SET_TX_DESC_STW_EN(txdesc, value) +#define GET_TX_DESC_STW_EN_8812F(txdesc) GET_TX_DESC_STW_EN(txdesc) +#define SET_TX_DESC_SMH_EN_8812F(txdesc, value) \ + SET_TX_DESC_SMH_EN(txdesc, value) +#define GET_TX_DESC_SMH_EN_8812F(txdesc) GET_TX_DESC_SMH_EN(txdesc) +#define SET_TX_DESC_TAILPAGE_L_8812F(txdesc, value) \ + SET_TX_DESC_TAILPAGE_L(txdesc, value) +#define GET_TX_DESC_TAILPAGE_L_8812F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc) +#define SET_TX_DESC_SDIO_DMASEQ_8812F(txdesc, value) \ + SET_TX_DESC_SDIO_DMASEQ(txdesc, value) +#define GET_TX_DESC_SDIO_DMASEQ_8812F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8812F(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8812F(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_L(txdesc) +#define SET_TX_DESC_EN_HWSEQ_MODE_8812F(txdesc, value) \ + SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value) +#define GET_TX_DESC_EN_HWSEQ_MODE_8812F(txdesc) \ + GET_TX_DESC_EN_HWSEQ_MODE(txdesc) +#define SET_TX_DESC_DATA_RC_8812F(txdesc, value) \ + SET_TX_DESC_DATA_RC(txdesc, value) +#define GET_TX_DESC_DATA_RC_8812F(txdesc) GET_TX_DESC_DATA_RC(txdesc) +#define SET_TX_DESC_BAR_RTY_TH_8812F(txdesc, value) \ + SET_TX_DESC_BAR_RTY_TH(txdesc, value) +#define GET_TX_DESC_BAR_RTY_TH_8812F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc) +#define SET_TX_DESC_RTS_RC_8812F(txdesc, value) \ + SET_TX_DESC_RTS_RC(txdesc, value) +#define GET_TX_DESC_RTS_RC_8812F(txdesc) GET_TX_DESC_RTS_RC(txdesc) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_TAILPAGE_H_8812F(txdesc, value) \ + SET_TX_DESC_TAILPAGE_H(txdesc, value) +#define GET_TX_DESC_TAILPAGE_H_8812F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8812F(txdesc, value) \ + SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8812F(txdesc) \ + GET_TX_DESC_NEXTHEADPAGE_H(txdesc) +#define SET_TX_DESC_SW_SEQ_8812F(txdesc, value) \ + SET_TX_DESC_SW_SEQ(txdesc, value) +#define GET_TX_DESC_SW_SEQ_8812F(txdesc) GET_TX_DESC_SW_SEQ(txdesc) +#define SET_TX_DESC_TXBF_PATH_8812F(txdesc, value) \ + SET_TX_DESC_TXBF_PATH(txdesc, value) +#define GET_TX_DESC_TXBF_PATH_8812F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc) +#define SET_TX_DESC_PADDING_LEN_8812F(txdesc, value) \ + SET_TX_DESC_PADDING_LEN(txdesc, value) +#define GET_TX_DESC_PADDING_LEN_8812F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8812F(txdesc, value) \ + SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8812F(txdesc) \ + GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) + +/*WORD10*/ + +#define SET_TX_DESC_HT_DATA_SND_8812F(txdesc, value) \ + SET_TX_DESC_HT_DATA_SND(txdesc, value) +#define GET_TX_DESC_HT_DATA_SND_8812F(txdesc) GET_TX_DESC_HT_DATA_SND(txdesc) +#define SET_TX_DESC_SHCUT_CAM_8812F(txdesc, value) \ + SET_TX_DESC_SHCUT_CAM(txdesc, value) +#define GET_TX_DESC_SHCUT_CAM_8812F(txdesc) GET_TX_DESC_SHCUT_CAM(txdesc) +#define SET_TX_DESC_MU_DATARATE_8812F(txdesc, value) \ + SET_TX_DESC_MU_DATARATE(txdesc, value) +#define GET_TX_DESC_MU_DATARATE_8812F(txdesc) GET_TX_DESC_MU_DATARATE(txdesc) +#define SET_TX_DESC_MU_RC_8812F(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value) +#define GET_TX_DESC_MU_RC_8812F(txdesc) GET_TX_DESC_MU_RC(txdesc) +#define SET_TX_DESC_NDPA_RATE_SEL_8812F(txdesc, value) \ + SET_TX_DESC_NDPA_RATE_SEL(txdesc, value) +#define GET_TX_DESC_NDPA_RATE_SEL_8812F(txdesc) \ + GET_TX_DESC_NDPA_RATE_SEL(txdesc) +#define SET_TX_DESC_HW_NDPA_EN_8812F(txdesc, value) \ + SET_TX_DESC_HW_NDPA_EN(txdesc, value) +#define GET_TX_DESC_HW_NDPA_EN_8812F(txdesc) GET_TX_DESC_HW_NDPA_EN(txdesc) +#define SET_TX_DESC_SND_PKT_SEL_8812F(txdesc, value) \ + SET_TX_DESC_SND_PKT_SEL(txdesc, value) +#define GET_TX_DESC_SND_PKT_SEL_8812F(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc) + +#endif #endif diff --git a/hal/halmac/halmac_tx_desc_ie_ap.h b/hal/halmac/halmac_tx_desc_ie_ap.h new file mode 100644 index 0000000..a6d215f --- /dev/null +++ b/hal/halmac/halmac_tx_desc_ie_ap.h @@ -0,0 +1,1005 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_IE_AP_H_ +#define _HALMAC_TX_DESC_IE_AP_H_ +#if (HALMAC_8814B_SUPPORT) + +#define IE0_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE0_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE0_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE0_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE0_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE0_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE0_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE0_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 19) +#define IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 19) +#define IE0_SET_TX_DESC_ARFR_TABLE_SEL_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 19) +#define IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 18) +#define IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 18) +#define IE0_SET_TX_DESC_ARFR_HT_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 18) +#define IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 17) +#define IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 17) +#define IE0_SET_TX_DESC_ARFR_OFDM_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 17) +#define IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 16) +#define IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 16) +#define IE0_SET_TX_DESC_ARFR_CCK_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 16) +#define IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 9) +#define IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9) +#define IE0_SET_TX_DESC_HW_RTS_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9) +#define IE0_GET_TX_DESC_RTS_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 8) +#define IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8) +#define IE0_SET_TX_DESC_RTS_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8) +#define IE0_GET_TX_DESC_CTS2SELF(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 7) +#define IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE0_SET_TX_DESC_CTS2SELF_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 6) +#define IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE0_SET_TX_DESC_RTY_LMT_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 5) +#define IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5) +#define IE0_SET_TX_DESC_RTS_SHORT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5) +#define IE0_GET_TX_DESC_DISDATAFB(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 4) +#define IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4) +#define IE0_SET_TX_DESC_DISDATAFB_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4) +#define IE0_GET_TX_DESC_DISRTSFB(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 3) +#define IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE0_SET_TX_DESC_DISRTSFB_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 2) +#define IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE0_SET_TX_DESC_DATA_SHORT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE0_GET_TX_DESC_TRY_RATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 1) +#define IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE0_SET_TX_DESC_TRY_RATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE0_GET_TX_DESC_USERATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 0) +#define IE0_SET_TX_DESC_USERATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE0_SET_TX_DESC_USERATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 27) +#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27) +#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27) +#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1f, 22) +#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1f, 22) +#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1f, 22) +#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3f, 16) +#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 16) +#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 16) +#define IE0_GET_TX_DESC_DATA_BW(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 12) +#define IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12) +#define IE0_SET_TX_DESC_DATA_BW_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12) +#define IE0_GET_TX_DESC_RTSRATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 7) +#define IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 7) +#define IE0_SET_TX_DESC_RTSRATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 7) +#define IE0_GET_TX_DESC_DATARATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x7f, 0) +#define IE0_SET_TX_DESC_DATARATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0) +#define IE0_SET_TX_DESC_DATARATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0) +#define IE1_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE1_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE1_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE1_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE1_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE1_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE1_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE1_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x7, 21) +#define IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 21) +#define IE1_SET_TX_DESC_AMPDU_DENSITY_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 21) +#define IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1f, 16) +#define IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1f, 16) +#define IE1_SET_TX_DESC_MAX_AGG_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1f, 16) +#define IE1_GET_TX_DESC_SECTYPE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x3, 14) +#define IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 14) +#define IE1_SET_TX_DESC_SECTYPE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 14) +#define IE1_GET_TX_DESC_MOREFRAG(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 13) +#define IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 13) +#define IE1_SET_TX_DESC_MOREFRAG_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 13) +#define IE1_GET_TX_DESC_NOACM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 12) +#define IE1_SET_TX_DESC_NOACM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 12) +#define IE1_SET_TX_DESC_NOACM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 12) +#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 11) +#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11) +#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11) +#define IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 10) +#define IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10) +#define IE1_SET_TX_DESC_NAVUSEHDR_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10) +#define IE1_GET_TX_DESC_HTC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 9) +#define IE1_SET_TX_DESC_HTC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9) +#define IE1_SET_TX_DESC_HTC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9) +#define IE1_GET_TX_DESC_BMC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 8) +#define IE1_SET_TX_DESC_BMC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8) +#define IE1_SET_TX_DESC_BMC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8) +#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 7) +#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 6) +#define IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE1_SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x3, 4) +#define IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 4) +#define IE1_SET_TX_DESC_HW_SSN_SEL_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 4) +#define IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 3) +#define IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE1_SET_TX_DESC_DISQSELSEQ_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 2) +#define IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE1_SET_TX_DESC_EN_HWSEQ_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 1) +#define IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE1_SET_TX_DESC_EN_HWEXSEQ_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 0) +#define IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE1_SET_TX_DESC_EN_DESC_ID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xff, 24) +#define IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 24) +#define IE1_SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 24) +#define IE1_GET_TX_DESC_P_AID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1ff, 15) +#define IE1_SET_TX_DESC_P_AID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1ff, \ + 15) +#define IE1_SET_TX_DESC_P_AID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1ff, \ + 15) +#define IE1_GET_TX_DESC_MOREDATA(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1, 14) +#define IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 14) +#define IE1_SET_TX_DESC_MOREDATA_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 14) +#define IE1_GET_TX_DESC_SW_SEQ(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xfff, 0) +#define IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0) +#define IE1_SET_TX_DESC_SW_SEQ_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0) +#define IE2_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE2_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE2_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE2_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE2_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE2_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE2_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE2_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xff, 16) +#define IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xff, 16) +#define IE2_SET_TX_DESC_ADDR_CAM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xff, 16) +#define IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x7, 12) +#define IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 12) +#define IE2_SET_TX_DESC_MULTIPLE_PORT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 12) +#define IE2_GET_TX_DESC_RAW(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 11) +#define IE2_SET_TX_DESC_RAW(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11) +#define IE2_SET_TX_DESC_RAW_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11) +#define IE2_GET_TX_DESC_RDG_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 10) +#define IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10) +#define IE2_SET_TX_DESC_RDG_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10) +#define IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 7) +#define IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE2_SET_TX_DESC_SPECIAL_CW_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7) +#define IE2_GET_TX_DESC_POLLUTED(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 6) +#define IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE2_SET_TX_DESC_POLLUTED_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6) +#define IE2_GET_TX_DESC_BT_NULL(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 5) +#define IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5) +#define IE2_SET_TX_DESC_BT_NULL_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5) +#define IE2_GET_TX_DESC_NULL_1(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 4) +#define IE2_SET_TX_DESC_NULL_1(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4) +#define IE2_SET_TX_DESC_NULL_1_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4) +#define IE2_GET_TX_DESC_NULL_0(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 3) +#define IE2_SET_TX_DESC_NULL_0(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE2_SET_TX_DESC_NULL_0_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3) +#define IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 2) +#define IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE2_SET_TX_DESC_TRI_FRAME_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE2_GET_TX_DESC_SPE_RPT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 1) +#define IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE2_SET_TX_DESC_SPE_RPT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE2_GET_TX_DESC_FTM_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 0) +#define IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE2_SET_TX_DESC_FTM_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE2_GET_TX_DESC_MBSSID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 27) +#define IE2_SET_TX_DESC_MBSSID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27) +#define IE2_SET_TX_DESC_MBSSID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27) +#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x7ff, 16) +#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7ff, \ + 16) +#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7ff, \ + 16) +#define IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1, 15) +#define IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 15) +#define IE2_SET_TX_DESC_RDG_NAV_EXT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 15) +#define IE2_GET_TX_DESC_DROP_ID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 12) +#define IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12) +#define IE2_SET_TX_DESC_DROP_ID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12) +#define IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xfff, 0) +#define IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0) +#define IE2_SET_TX_DESC_SW_DEFINE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0) +#define IE3_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE3_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE3_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE3_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE3_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE3_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE3_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE3_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE3_GET_TX_DESC_DATA_SC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 20) +#define IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 20) +#define IE3_SET_TX_DESC_DATA_SC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 20) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 16) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 16) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 16) +#define IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 8) +#define IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 8) +#define IE3_SET_TX_DESC_CTRL_CNT_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 8) +#define IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 1) +#define IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE3_SET_TX_DESC_CTRL_CNT_VALID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 0) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE3_GET_TX_DESC_G_ID(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3f, 24) +#define IE3_SET_TX_DESC_G_ID(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 24) +#define IE3_SET_TX_DESC_G_ID_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 24) +#define IE3_GET_TX_DESC_SND_TARGET(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xff, 16) +#define IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 16) +#define IE3_SET_TX_DESC_SND_TARGET_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 16) +#define IE3_GET_TX_DESC_CCA_RTS(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 11) +#define IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 11) +#define IE3_SET_TX_DESC_CCA_RTS_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 11) +#define IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 9) +#define IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 9) +#define IE3_SET_TX_DESC_SND_PKT_SEL_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 9) +#define IE3_GET_TX_DESC_NDPA(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 7) +#define IE3_SET_TX_DESC_NDPA(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 7) +#define IE3_SET_TX_DESC_NDPA_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 7) +#define IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x7f, 0) +#define IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0) +#define IE3_SET_TX_DESC_MU_DATARATE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0) +#define IE4_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE4_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE4_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE4_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE4_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE4_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE4_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE4_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE4_GET_TX_DESC_VCS_STBC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x3, 10) +#define IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 10) +#define IE4_SET_TX_DESC_VCS_STBC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 10) +#define IE4_GET_TX_DESC_DATA_STBC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x3, 8) +#define IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 8) +#define IE4_SET_TX_DESC_DATA_STBC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 8) +#define IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 2) +#define IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE4_SET_TX_DESC_DATA_LDPC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2) +#define IE4_GET_TX_DESC_GF(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 1) +#define IE4_SET_TX_DESC_GF(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE4_SET_TX_DESC_GF_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1) +#define IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 0) +#define IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE4_SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0) +#define IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 30) +#define IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 30) +#define IE4_SET_TX_DESC_PATH_MAPA_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 30) +#define IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 28) +#define IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 28) +#define IE4_SET_TX_DESC_PATH_MAPB_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 28) +#define IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 26) +#define IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 26) +#define IE4_SET_TX_DESC_PATH_MAPC_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 26) +#define IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 24) +#define IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 24) +#define IE4_SET_TX_DESC_PATH_MAPD_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 24) +#define IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 20) +#define IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 20) +#define IE4_SET_TX_DESC_ANTSEL_A_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 20) +#define IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 16) +#define IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 16) +#define IE4_SET_TX_DESC_ANTSEL_B_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 16) +#define IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 12) +#define IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 12) +#define IE4_SET_TX_DESC_ANTSEL_C_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 12) +#define IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 8) +#define IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 8) +#define IE4_SET_TX_DESC_ANTSEL_D_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 8) +#define IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0xf, 4) +#define IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 4) +#define IE4_SET_TX_DESC_NTX_PATH_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 4) +#define IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1, 3) +#define IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 3) +#define IE4_SET_TX_DESC_ANTLSEL_EN_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 3) +#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3, 0) +#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 0) +#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 0) +#define IE5_GET_TX_DESC_IE_END(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 31) +#define IE5_SET_TX_DESC_IE_END(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE5_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31) +#define IE5_GET_TX_DESC_IE_UP(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1, 30) +#define IE5_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE5_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30) +#define IE5_GET_TX_DESC_IE_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 24) +#define IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE5_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24) +#define IE5_GET_TX_DESC_LEN1_L(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x7f, 17) +#define IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7f, 17) +#define IE5_SET_TX_DESC_LEN1_L_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7f, 17) +#define IE5_GET_TX_DESC_LEN0(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0x1fff, 4) +#define IE5_SET_TX_DESC_LEN0(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1fff, \ + 4) +#define IE5_SET_TX_DESC_LEN0_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1fff, \ + 4) +#define IE5_GET_TX_DESC_PKT_NUM(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \ + 0xf, 0) +#define IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 0) +#define IE5_SET_TX_DESC_PKT_NUM_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 0) +#define IE5_GET_TX_DESC_LEN3(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1fff, 19) +#define IE5_SET_TX_DESC_LEN3(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \ + 19) +#define IE5_SET_TX_DESC_LEN3_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \ + 19) +#define IE5_GET_TX_DESC_LEN2(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x1fff, 6) +#define IE5_SET_TX_DESC_LEN2(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \ + 6) +#define IE5_SET_TX_DESC_LEN2_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \ + 6) +#define IE5_GET_TX_DESC_LEN1_H(txdesc_ie) \ + HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \ + 0x3f, 0) +#define IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 0) +#define IE5_SET_TX_DESC_LEN1_H_NO_CLR(txdesc_ie, value) \ + HALMAC_SET_DESC_FIELD_NO_CLR( \ + ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 0) + +#endif + +#endif diff --git a/hal/halmac/halmac_tx_desc_ie_chip.h b/hal/halmac/halmac_tx_desc_ie_chip.h new file mode 100644 index 0000000..8126a0c --- /dev/null +++ b/hal/halmac/halmac_tx_desc_ie_chip.h @@ -0,0 +1,438 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_IE_CHIP_H_ +#define _HALMAC_TX_DESC_IE_CHIP_H_ +#if (HALMAC_8814B_SUPPORT) + +#define IE0_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_IE_END(txdesc_ie) +#define IE0_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE0_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE0_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE0_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE0_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE0_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE0_GET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie) +#define IE0_SET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value) +#define IE0_GET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie) +#define IE0_SET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie) +#define IE0_SET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie) +#define IE0_SET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie) +#define IE0_SET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTS_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTS_EN(txdesc_ie) +#define IE0_SET_TX_DESC_RTS_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_CTS2SELF_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_CTS2SELF(txdesc_ie) +#define IE0_SET_TX_DESC_CTS2SELF_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie) +#define IE0_SET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTS_SHORT_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie) +#define IE0_SET_TX_DESC_RTS_SHORT_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value) +#define IE0_GET_TX_DESC_DISDATAFB_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DISDATAFB(txdesc_ie) +#define IE0_SET_TX_DESC_DISDATAFB_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value) +#define IE0_GET_TX_DESC_DISRTSFB_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DISRTSFB(txdesc_ie) +#define IE0_SET_TX_DESC_DISRTSFB_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value) +#define IE0_GET_TX_DESC_DATA_SHORT_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie) +#define IE0_SET_TX_DESC_DATA_SHORT_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value) +#define IE0_GET_TX_DESC_TRY_RATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_TRY_RATE(txdesc_ie) +#define IE0_SET_TX_DESC_TRY_RATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value) +#define IE0_GET_TX_DESC_USERATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_USERATE(txdesc_ie) +#define IE0_SET_TX_DESC_USERATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_USERATE(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie) +#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value) +#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie) +#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie) +#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value) +#define IE0_GET_TX_DESC_DATA_BW_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DATA_BW(txdesc_ie) +#define IE0_SET_TX_DESC_DATA_BW_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value) +#define IE0_GET_TX_DESC_RTSRATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_RTSRATE(txdesc_ie) +#define IE0_SET_TX_DESC_RTSRATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value) +#define IE0_GET_TX_DESC_DATARATE_8814B(txdesc_ie) \ + IE0_GET_TX_DESC_DATARATE(txdesc_ie) +#define IE0_SET_TX_DESC_DATARATE_8814B(txdesc_ie, value) \ + IE0_SET_TX_DESC_DATARATE(txdesc_ie, value) +#define IE1_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_IE_END(txdesc_ie) +#define IE1_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE1_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE1_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE1_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE1_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE1_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE1_GET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie) +#define IE1_SET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value) +#define IE1_GET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie) +#define IE1_SET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value) +#define IE1_GET_TX_DESC_SECTYPE_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_SECTYPE(txdesc_ie) +#define IE1_SET_TX_DESC_SECTYPE_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value) +#define IE1_GET_TX_DESC_MOREFRAG_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_MOREFRAG(txdesc_ie) +#define IE1_SET_TX_DESC_MOREFRAG_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value) +#define IE1_GET_TX_DESC_NOACM_8814B(txdesc_ie) IE1_GET_TX_DESC_NOACM(txdesc_ie) +#define IE1_SET_TX_DESC_NOACM_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_NOACM(txdesc_ie, value) +#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie) +#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value) +#define IE1_GET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie) +#define IE1_SET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value) +#define IE1_GET_TX_DESC_HTC_8814B(txdesc_ie) IE1_GET_TX_DESC_HTC(txdesc_ie) +#define IE1_SET_TX_DESC_HTC_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_HTC(txdesc_ie, value) +#define IE1_GET_TX_DESC_BMC_8814B(txdesc_ie) IE1_GET_TX_DESC_BMC(txdesc_ie) +#define IE1_SET_TX_DESC_BMC_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_BMC(txdesc_ie, value) +#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie) +#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value) +#define IE1_GET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie) +#define IE1_SET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value) +#define IE1_GET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie) +#define IE1_SET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value) +#define IE1_GET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie) +#define IE1_SET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value) +#define IE1_GET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie) +#define IE1_SET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value) +#define IE1_GET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie) +#define IE1_SET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value) +#define IE1_GET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie) +#define IE1_SET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value) +#define IE1_GET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie) +#define IE1_SET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value) +#define IE1_GET_TX_DESC_P_AID_8814B(txdesc_ie) IE1_GET_TX_DESC_P_AID(txdesc_ie) +#define IE1_SET_TX_DESC_P_AID_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_P_AID(txdesc_ie, value) +#define IE1_GET_TX_DESC_MOREDATA_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_MOREDATA(txdesc_ie) +#define IE1_SET_TX_DESC_MOREDATA_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value) +#define IE1_GET_TX_DESC_SW_SEQ_8814B(txdesc_ie) \ + IE1_GET_TX_DESC_SW_SEQ(txdesc_ie) +#define IE1_SET_TX_DESC_SW_SEQ_8814B(txdesc_ie, value) \ + IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value) +#define IE2_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_IE_END(txdesc_ie) +#define IE2_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE2_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE2_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE2_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE2_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE2_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE2_GET_TX_DESC_ADDR_CAM_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie) +#define IE2_SET_TX_DESC_ADDR_CAM_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value) +#define IE2_GET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie) +#define IE2_SET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value) +#define IE2_GET_TX_DESC_RAW_8814B(txdesc_ie) IE2_GET_TX_DESC_RAW(txdesc_ie) +#define IE2_SET_TX_DESC_RAW_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_RAW(txdesc_ie, value) +#define IE2_GET_TX_DESC_RDG_EN_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_RDG_EN(txdesc_ie) +#define IE2_SET_TX_DESC_RDG_EN_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value) +#define IE2_GET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie) +#define IE2_SET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value) +#define IE2_GET_TX_DESC_POLLUTED_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_POLLUTED(txdesc_ie) +#define IE2_SET_TX_DESC_POLLUTED_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value) +#define IE2_GET_TX_DESC_BT_NULL_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_BT_NULL(txdesc_ie) +#define IE2_SET_TX_DESC_BT_NULL_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value) +#define IE2_GET_TX_DESC_NULL_1_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_NULL_1(txdesc_ie) +#define IE2_SET_TX_DESC_NULL_1_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_NULL_1(txdesc_ie, value) +#define IE2_GET_TX_DESC_NULL_0_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_NULL_0(txdesc_ie) +#define IE2_SET_TX_DESC_NULL_0_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_NULL_0(txdesc_ie, value) +#define IE2_GET_TX_DESC_TRI_FRAME_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie) +#define IE2_SET_TX_DESC_TRI_FRAME_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value) +#define IE2_GET_TX_DESC_SPE_RPT_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_SPE_RPT(txdesc_ie) +#define IE2_SET_TX_DESC_SPE_RPT_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value) +#define IE2_GET_TX_DESC_FTM_EN_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_FTM_EN(txdesc_ie) +#define IE2_SET_TX_DESC_FTM_EN_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value) +#define IE2_GET_TX_DESC_MBSSID_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_MBSSID(txdesc_ie) +#define IE2_SET_TX_DESC_MBSSID_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_MBSSID(txdesc_ie, value) +#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie) +#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value) +#define IE2_GET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie) +#define IE2_SET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value) +#define IE2_GET_TX_DESC_DROP_ID_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_DROP_ID(txdesc_ie) +#define IE2_SET_TX_DESC_DROP_ID_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value) +#define IE2_GET_TX_DESC_SW_DEFINE_8814B(txdesc_ie) \ + IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie) +#define IE2_SET_TX_DESC_SW_DEFINE_8814B(txdesc_ie, value) \ + IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value) +#define IE3_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_IE_END(txdesc_ie) +#define IE3_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE3_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE3_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE3_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE3_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE3_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE3_GET_TX_DESC_DATA_SC_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_DATA_SC(txdesc_ie) +#define IE3_SET_TX_DESC_DATA_SC_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value) +#define IE3_GET_TX_DESC_CTRL_CNT_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie) +#define IE3_SET_TX_DESC_CTRL_CNT_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value) +#define IE3_GET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie) +#define IE3_SET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value) +#define IE3_GET_TX_DESC_G_ID_8814B(txdesc_ie) IE3_GET_TX_DESC_G_ID(txdesc_ie) +#define IE3_SET_TX_DESC_G_ID_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_G_ID(txdesc_ie, value) +#define IE3_GET_TX_DESC_SND_TARGET_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_SND_TARGET(txdesc_ie) +#define IE3_SET_TX_DESC_SND_TARGET_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value) +#define IE3_GET_TX_DESC_CCA_RTS_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_CCA_RTS(txdesc_ie) +#define IE3_SET_TX_DESC_CCA_RTS_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value) +#define IE3_GET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie) +#define IE3_SET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value) +#define IE3_GET_TX_DESC_NDPA_8814B(txdesc_ie) IE3_GET_TX_DESC_NDPA(txdesc_ie) +#define IE3_SET_TX_DESC_NDPA_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_NDPA(txdesc_ie, value) +#define IE3_GET_TX_DESC_MU_DATARATE_8814B(txdesc_ie) \ + IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie) +#define IE3_SET_TX_DESC_MU_DATARATE_8814B(txdesc_ie, value) \ + IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value) +#define IE4_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_IE_END(txdesc_ie) +#define IE4_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE4_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE4_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE4_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE4_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE4_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE4_GET_TX_DESC_VCS_STBC_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_VCS_STBC(txdesc_ie) +#define IE4_SET_TX_DESC_VCS_STBC_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value) +#define IE4_GET_TX_DESC_DATA_STBC_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_DATA_STBC(txdesc_ie) +#define IE4_SET_TX_DESC_DATA_STBC_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value) +#define IE4_GET_TX_DESC_DATA_LDPC_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie) +#define IE4_SET_TX_DESC_DATA_LDPC_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value) +#define IE4_GET_TX_DESC_GF_8814B(txdesc_ie) IE4_GET_TX_DESC_GF(txdesc_ie) +#define IE4_SET_TX_DESC_GF_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_GF(txdesc_ie, value) +#define IE4_GET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie) +#define IE4_SET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value) +#define IE4_GET_TX_DESC_PATH_MAPA_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie) +#define IE4_SET_TX_DESC_PATH_MAPA_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value) +#define IE4_GET_TX_DESC_PATH_MAPB_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie) +#define IE4_SET_TX_DESC_PATH_MAPB_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value) +#define IE4_GET_TX_DESC_PATH_MAPC_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie) +#define IE4_SET_TX_DESC_PATH_MAPC_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value) +#define IE4_GET_TX_DESC_PATH_MAPD_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie) +#define IE4_SET_TX_DESC_PATH_MAPD_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value) +#define IE4_GET_TX_DESC_ANTSEL_A_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie) +#define IE4_SET_TX_DESC_ANTSEL_A_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value) +#define IE4_GET_TX_DESC_ANTSEL_B_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie) +#define IE4_SET_TX_DESC_ANTSEL_B_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value) +#define IE4_GET_TX_DESC_ANTSEL_C_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie) +#define IE4_SET_TX_DESC_ANTSEL_C_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value) +#define IE4_GET_TX_DESC_ANTSEL_D_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie) +#define IE4_SET_TX_DESC_ANTSEL_D_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value) +#define IE4_GET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie) +#define IE4_SET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value) +#define IE4_GET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie) +#define IE4_SET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value) +#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie) \ + IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie) +#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie, value) \ + IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value) +#define IE5_GET_TX_DESC_IE_END_8814B(txdesc_ie) \ + IE5_GET_TX_DESC_IE_END(txdesc_ie) +#define IE5_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_IE_END(txdesc_ie, value) +#define IE5_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE5_GET_TX_DESC_IE_UP(txdesc_ie) +#define IE5_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_IE_UP(txdesc_ie, value) +#define IE5_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \ + IE5_GET_TX_DESC_IE_NUM(txdesc_ie) +#define IE5_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value) +#define IE5_GET_TX_DESC_LEN1_L_8814B(txdesc_ie) \ + IE5_GET_TX_DESC_LEN1_L(txdesc_ie) +#define IE5_SET_TX_DESC_LEN1_L_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value) +#define IE5_GET_TX_DESC_LEN0_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN0(txdesc_ie) +#define IE5_SET_TX_DESC_LEN0_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_LEN0(txdesc_ie, value) +#define IE5_GET_TX_DESC_PKT_NUM_8814B(txdesc_ie) \ + IE5_GET_TX_DESC_PKT_NUM(txdesc_ie) +#define IE5_SET_TX_DESC_PKT_NUM_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value) +#define IE5_GET_TX_DESC_LEN3_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN3(txdesc_ie) +#define IE5_SET_TX_DESC_LEN3_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_LEN3(txdesc_ie, value) +#define IE5_GET_TX_DESC_LEN2_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN2(txdesc_ie) +#define IE5_SET_TX_DESC_LEN2_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_LEN2(txdesc_ie, value) +#define IE5_GET_TX_DESC_LEN1_H_8814B(txdesc_ie) \ + IE5_GET_TX_DESC_LEN1_H(txdesc_ie) +#define IE5_SET_TX_DESC_LEN1_H_8814B(txdesc_ie, value) \ + IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value) + +#endif + +#endif diff --git a/hal/halmac/halmac_tx_desc_ie_nic.h b/hal/halmac/halmac_tx_desc_ie_nic.h new file mode 100644 index 0000000..c88f8fa --- /dev/null +++ b/hal/halmac/halmac_tx_desc_ie_nic.h @@ -0,0 +1,450 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + +#ifndef _HALMAC_TX_DESC_IE_NIC_H_ +#define _HALMAC_TX_DESC_IE_NIC_H_ +#if (HALMAC_8814B_SUPPORT) + +#define IE0_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE0_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE0_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE0_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE0_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 19, 1) +#define IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 19, 1, value) +#define IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 18, 1) +#define IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 18, 1, value) +#define IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 1) +#define IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 1, value) +#define IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 1) +#define IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 1, value) +#define IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1) +#define IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value) +#define IE0_GET_TX_DESC_RTS_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1) +#define IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value) +#define IE0_GET_TX_DESC_CTS2SELF(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1) +#define IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value) +#define IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1) +#define IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value) +#define IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1) +#define IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value) +#define IE0_GET_TX_DESC_DISDATAFB(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1) +#define IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value) +#define IE0_GET_TX_DESC_DISRTSFB(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1) +#define IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value) +#define IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1) +#define IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value) +#define IE0_GET_TX_DESC_TRY_RATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1) +#define IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value) +#define IE0_GET_TX_DESC_USERATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1) +#define IE0_SET_TX_DESC_USERATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value) +#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4) +#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value) +#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 22, 5) +#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 22, 5, value) +#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 6) +#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 6, value) +#define IE0_GET_TX_DESC_DATA_BW(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2) +#define IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value) +#define IE0_GET_TX_DESC_RTSRATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 4) +#define IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 4, value) +#define IE0_GET_TX_DESC_DATARATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7) +#define IE0_SET_TX_DESC_DATARATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value) +#define IE1_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE1_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE1_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE1_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE1_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 21, 3) +#define IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 21, 3, value) +#define IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 5) +#define IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 5, value) +#define IE1_GET_TX_DESC_SECTYPE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 14, 2) +#define IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 14, 2, value) +#define IE1_GET_TX_DESC_MOREFRAG(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 13, 1) +#define IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 13, 1, value) +#define IE1_GET_TX_DESC_NOACM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 1) +#define IE1_SET_TX_DESC_NOACM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 1, value) +#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1) +#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value) +#define IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1) +#define IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value) +#define IE1_GET_TX_DESC_HTC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1) +#define IE1_SET_TX_DESC_HTC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value) +#define IE1_GET_TX_DESC_BMC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1) +#define IE1_SET_TX_DESC_BMC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value) +#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1) +#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value) +#define IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1) +#define IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value) +#define IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 2) +#define IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 2, value) +#define IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1) +#define IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value) +#define IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1) +#define IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value) +#define IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1) +#define IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value) +#define IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1) +#define IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value) +#define IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 8) +#define IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 8, value) +#define IE1_GET_TX_DESC_P_AID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 9) +#define IE1_SET_TX_DESC_P_AID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 9, value) +#define IE1_GET_TX_DESC_MOREDATA(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 14, 1) +#define IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 14, 1, value) +#define IE1_GET_TX_DESC_SW_SEQ(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12) +#define IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value) +#define IE2_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE2_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE2_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE2_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE2_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 8) +#define IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 8, value) +#define IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 3) +#define IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 3, value) +#define IE2_GET_TX_DESC_RAW(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1) +#define IE2_SET_TX_DESC_RAW(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value) +#define IE2_GET_TX_DESC_RDG_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1) +#define IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value) +#define IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1) +#define IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value) +#define IE2_GET_TX_DESC_POLLUTED(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1) +#define IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value) +#define IE2_GET_TX_DESC_BT_NULL(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1) +#define IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value) +#define IE2_GET_TX_DESC_NULL_1(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1) +#define IE2_SET_TX_DESC_NULL_1(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value) +#define IE2_GET_TX_DESC_NULL_0(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1) +#define IE2_SET_TX_DESC_NULL_0(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value) +#define IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1) +#define IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value) +#define IE2_GET_TX_DESC_SPE_RPT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1) +#define IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value) +#define IE2_GET_TX_DESC_FTM_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1) +#define IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value) +#define IE2_GET_TX_DESC_MBSSID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4) +#define IE2_SET_TX_DESC_MBSSID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value) +#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 11) +#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 11, value) +#define IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 1) +#define IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 1, value) +#define IE2_GET_TX_DESC_DROP_ID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2) +#define IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value) +#define IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12) +#define IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value) +#define IE3_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE3_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE3_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE3_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE3_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE3_GET_TX_DESC_DATA_SC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 20, 4) +#define IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 20, 4, value) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 4) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 4, value) +#define IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 4) +#define IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 4, value) +#define IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1) +#define IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value) +#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1) +#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value) +#define IE3_GET_TX_DESC_G_ID(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 6) +#define IE3_SET_TX_DESC_G_ID(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 6, value) +#define IE3_GET_TX_DESC_SND_TARGET(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 8) +#define IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 8, value) +#define IE3_GET_TX_DESC_CCA_RTS(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 11, 2) +#define IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 11, 2, value) +#define IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 9, 2) +#define IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 9, 2, value) +#define IE3_GET_TX_DESC_NDPA(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 2) +#define IE3_SET_TX_DESC_NDPA(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 2, value) +#define IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7) +#define IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value) +#define IE4_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE4_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE4_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE4_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE4_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE4_GET_TX_DESC_VCS_STBC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 2) +#define IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 2, value) +#define IE4_GET_TX_DESC_DATA_STBC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 2) +#define IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 2, value) +#define IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1) +#define IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value) +#define IE4_GET_TX_DESC_GF(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1) +#define IE4_SET_TX_DESC_GF(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value) +#define IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1) +#define IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value) +#define IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 30, 2) +#define IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 30, 2, value) +#define IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 28, 2) +#define IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 28, 2, value) +#define IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 26, 2) +#define IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 26, 2, value) +#define IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 2) +#define IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 2, value) +#define IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 20, 4) +#define IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 20, 4, value) +#define IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 4) +#define IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 4, value) +#define IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 4) +#define IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 4, value) +#define IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 8, 4) +#define IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 8, 4, value) +#define IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 4, 4) +#define IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 4, 4, value) +#define IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 3, 1) +#define IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 3, 1, value) +#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 2) +#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 2, value) +#define IE5_GET_TX_DESC_IE_END(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1) +#define IE5_SET_TX_DESC_IE_END(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value) +#define IE5_GET_TX_DESC_IE_UP(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1) +#define IE5_SET_TX_DESC_IE_UP(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value) +#define IE5_GET_TX_DESC_IE_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4) +#define IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value) +#define IE5_GET_TX_DESC_LEN1_L(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 7) +#define IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 7, value) +#define IE5_GET_TX_DESC_LEN0(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 13) +#define IE5_SET_TX_DESC_LEN0(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 13, value) +#define IE5_GET_TX_DESC_PKT_NUM(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 4) +#define IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 4, value) +#define IE5_GET_TX_DESC_LEN3(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 19, 13) +#define IE5_SET_TX_DESC_LEN3(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 19, 13, value) +#define IE5_GET_TX_DESC_LEN2(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 6, 13) +#define IE5_SET_TX_DESC_LEN2(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 6, 13, value) +#define IE5_GET_TX_DESC_LEN1_H(txdesc_ie) \ + LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 6) +#define IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value) \ + SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 6, value) + +#endif + +#endif diff --git a/hal/halmac/halmac_tx_desc_nic.h b/hal/halmac/halmac_tx_desc_nic.h index 94eefbe..3f67b7b 100644 --- a/hal/halmac/halmac_tx_desc_nic.h +++ b/hal/halmac/halmac_tx_desc_nic.h @@ -1,451 +1,1025 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TX_DESC_NIC_H_ #define _HALMAC_TX_DESC_NIC_H_ -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) /*TXDESC_WORD0*/ -#define SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 31, 1, __Value) -#define GET_TX_DESC_DISQSELSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 31, 1) +#define SET_TX_DESC_DISQSELSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value) +#define GET_TX_DESC_DISQSELSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_IE_END_BODY(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value) +#define GET_TX_DESC_IE_END_BODY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_GF(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value) +#define GET_TX_DESC_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_AGG_EN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value) +#define GET_TX_DESC_AGG_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_NO_ACM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value) +#define GET_TX_DESC_NO_ACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_BK_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value) +#define GET_TX_DESC_BK_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 28, 1, value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x00, 28, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 27, 1, value) +#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 27, 1) +#define SET_TX_DESC_LS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 26, 1, value) +#define GET_TX_DESC_LS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 26, 1) +#define SET_TX_DESC_HTC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 25, 1, value) +#define GET_TX_DESC_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 25, 1) +#define SET_TX_DESC_BMC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 1, value) +#define GET_TX_DESC_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_PKT_OFFSET_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value) +#define GET_TX_DESC_PKT_OFFSET_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_GF(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 30, 1, __Value) -#define GET_TX_DESC_GF(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 30, 1) -#define SET_TX_DESC_NO_ACM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 29, 1, __Value) -#define GET_TX_DESC_NO_ACM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 29, 1) +#define SET_TX_DESC_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value) +#define GET_TX_DESC_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8) +#define SET_TX_DESC_TXPKTSIZE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value) +#define GET_TX_DESC_TXPKTSIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 28, 1, __Value) -#define GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 28, 1) +/*WORD1*/ + +#define SET_TX_DESC_HW_AES_IV_V2(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value) +#define GET_TX_DESC_HW_AES_IV_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 27, 1, __Value) -#define GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 27, 1) +#define SET_TX_DESC_AMSDU(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value) +#define GET_TX_DESC_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_FTM_EN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value) +#define GET_TX_DESC_FTM_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1) -#define SET_TX_DESC_LS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 26, 1, __Value) -#define GET_TX_DESC_LS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 26, 1) -#define SET_TX_DESC_HTC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 25, 1, __Value) -#define GET_TX_DESC_HTC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 25, 1) -#define SET_TX_DESC_BMC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 24, 1, __Value) -#define GET_TX_DESC_BMC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 24, 1) -#define SET_TX_DESC_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 16, 8, __Value) -#define GET_TX_DESC_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 16, 8) -#define SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 0, 16, __Value) -#define GET_TX_DESC_TXPKTSIZE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 0, 16) +#endif -/*TXDESC_WORD1*/ +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_MOREDATA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 29, 1, __Value) -#define GET_TX_DESC_MOREDATA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 29, 1) -#define SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 24, 5, __Value) -#define GET_TX_DESC_PKT_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 24, 5) -#define SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 22, 2, __Value) -#define GET_TX_DESC_SEC_TYPE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 22, 2) -#define SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 21, 1, __Value) -#define GET_TX_DESC_EN_DESC_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 21, 1) -#define SET_TX_DESC_RATE_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 16, 5, __Value) -#define GET_TX_DESC_RATE_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 16, 5) -#define SET_TX_DESC_PIFS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 15, 1, __Value) -#define GET_TX_DESC_PIFS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 15, 1) -#define SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 14, 1, __Value) -#define GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 14, 1) -#define SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 13, 1, __Value) -#define GET_TX_DESC_RD_NAV_EXT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 13, 1) -#define SET_TX_DESC_QSEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 8, 5, __Value) -#define GET_TX_DESC_QSEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 8, 5) -#define SET_TX_DESC_MACID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 0, 7, __Value) -#define GET_TX_DESC_MACID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 0, 7) +#define SET_TX_DESC_MOREDATA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value) +#define GET_TX_DESC_MOREDATA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_HW_AES_IV_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value) +#define GET_TX_DESC_HW_AES_IV_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1) +#define SET_TX_DESC_MHR_CP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 25, 1, value) +#define GET_TX_DESC_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 25, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 5, value) +#define GET_TX_DESC_PKT_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 5) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_SMH_EN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 1, value) +#define GET_TX_DESC_SMH_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 1) + +#endif +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_SEC_TYPE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 22, 2, value) +#define GET_TX_DESC_SEC_TYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 22, 2) +#define SET_TX_DESC_EN_DESC_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 21, 1, value) +#define GET_TX_DESC_EN_DESC_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 21, 1) +#define SET_TX_DESC_RATE_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 5, value) +#define GET_TX_DESC_RATE_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 5) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_SMH_CAM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 8, value) +#define GET_TX_DESC_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 8) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_PIFS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 15, 1, value) +#define GET_TX_DESC_PIFS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 15, 1) +#define SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 1, value) +#define GET_TX_DESC_LSIG_TXOP_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 14, 1) +#define SET_TX_DESC_RD_NAV_EXT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value) +#define GET_TX_DESC_RD_NAV_EXT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_EXT_EDCA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value) +#define GET_TX_DESC_EXT_EDCA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_QSEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value) +#define GET_TX_DESC_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_SPECIAL_CW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 7, 1, value) +#define GET_TX_DESC_SPECIAL_CW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 7, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_MACID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value) +#define GET_TX_DESC_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_MACID_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value) +#define GET_TX_DESC_MACID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) /*TXDESC_WORD2*/ -#define SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 31, 1, __Value) -#define GET_TX_DESC_HW_AES_IV(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 31, 1) +#define SET_TX_DESC_HW_AES_IV(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value) +#define GET_TX_DESC_HW_AES_IV(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_CHK_EN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value) +#define GET_TX_DESC_CHK_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_FTM_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value) +#define GET_TX_DESC_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1) + +#endif + +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTCEL_D_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 4, value) +#define GET_TX_DESC_ANTCEL_D_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 28, 4) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_DMA_PRI(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value) +#define GET_TX_DESC_DMA_PRI(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_G_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 6, value) +#define GET_TX_DESC_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 6) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_FTM_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 30, 1, __Value) -#define GET_TX_DESC_FTM_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 30, 1) +#define SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value) +#define GET_TX_DESC_MAX_AMSDU_MODE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_C_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 4, value) +#define GET_TX_DESC_ANTSEL_C_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 4) + +#endif -#define SET_TX_DESC_G_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 24, 6, __Value) -#define GET_TX_DESC_G_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 24, 6) -#define SET_TX_DESC_BT_NULL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 23, 1, __Value) -#define GET_TX_DESC_BT_NULL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 23, 1) -#define SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 20, 3, __Value) -#define GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 20, 3) -#define SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 19, 1, __Value) -#define GET_TX_DESC_SPE_RPT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 19, 1) -#define SET_TX_DESC_RAW(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 18, 1, __Value) -#define GET_TX_DESC_RAW(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 18, 1) -#define SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 17, 1, __Value) -#define GET_TX_DESC_MOREFRAG(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 17, 1) -#define SET_TX_DESC_BK(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 16, 1, __Value) -#define GET_TX_DESC_BK(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 16, 1) -#define SET_TX_DESC_NULL_1(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 15, 1, __Value) -#define GET_TX_DESC_NULL_1(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 15, 1) -#define SET_TX_DESC_NULL_0(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 14, 1, __Value) -#define GET_TX_DESC_NULL_0(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 14, 1) -#define SET_TX_DESC_RDG_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 13, 1, __Value) -#define GET_TX_DESC_RDG_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 13, 1) -#define SET_TX_DESC_AGG_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 12, 1, __Value) -#define GET_TX_DESC_AGG_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 12, 1) -#define SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 10, 2, __Value) -#define GET_TX_DESC_CCA_RTS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 10, 2) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_BT_NULL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 23, 1, value) +#define GET_TX_DESC_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 23, 1) +#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 20, 3, value) +#define GET_TX_DESC_AMPDU_DENSITY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 20, 3) +#define SET_TX_DESC_SPE_RPT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 19, 1, value) +#define GET_TX_DESC_SPE_RPT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 19, 1) +#define SET_TX_DESC_RAW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 18, 1, value) +#define GET_TX_DESC_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 18, 1) +#define SET_TX_DESC_MOREFRAG(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 17, 1, value) +#define GET_TX_DESC_MOREFRAG(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 17, 1) +#define SET_TX_DESC_BK(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 1, value) +#define GET_TX_DESC_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 1) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 9, 1, __Value) -#define GET_TX_DESC_TRI_FRAME(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 9, 1) +#define SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value) +#define GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_NULL_1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 15, 1, value) +#define GET_TX_DESC_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 15, 1) +#define SET_TX_DESC_NULL_0(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 14, 1, value) +#define GET_TX_DESC_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 14, 1) +#define SET_TX_DESC_RDG_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 13, 1, value) +#define GET_TX_DESC_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 13, 1) +#define SET_TX_DESC_AGG_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 12, 1, value) +#define GET_TX_DESC_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 12, 1) +#define SET_TX_DESC_CCA_RTS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 10, 2, value) +#define GET_TX_DESC_CCA_RTS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 10, 2) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_TRI_FRAME(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 9, 1, value) +#define GET_TX_DESC_TRI_FRAME(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 9, 1) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_P_AID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 9, value) +#define GET_TX_DESC_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 9) + +#endif + +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value) +#define GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16) + +#endif -#define SET_TX_DESC_P_AID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 0, 9, __Value) -#define GET_TX_DESC_P_AID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 0, 9) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) /*TXDESC_WORD3*/ -#define SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 24, 8, __Value) -#define GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 24, 8) -#define SET_TX_DESC_NDPA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 22, 2, __Value) -#define GET_TX_DESC_NDPA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 22, 2) -#define SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 17, 5, __Value) -#define GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 17, 5) -#define SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 16, 1, __Value) -#define GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 16, 1) -#define SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 15, 1, __Value) -#define GET_TX_DESC_NAVUSEHDR(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 15, 1) +#define SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 24, 8, value) +#define GET_TX_DESC_AMPDU_MAX_TIME(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x0C, 24, 8) +#define SET_TX_DESC_NDPA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 22, 2, value) +#define GET_TX_DESC_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 22, 2) +#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 17, 5, value) +#define GET_TX_DESC_MAX_AGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 17, 5) +#define SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 1, value) +#define GET_TX_DESC_USE_MAX_TIME_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_OFFLOAD_SIZE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value) +#define GET_TX_DESC_OFFLOAD_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15) + +#endif -#define SET_TX_DESC_CHK_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 14, 1, __Value) -#define GET_TX_DESC_CHK_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 14, 1) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 15, 1, value) +#define GET_TX_DESC_NAVUSEHDR(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 15, 1) +#define SET_TX_DESC_CHK_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 14, 1, value) +#define GET_TX_DESC_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 14, 1) +#define SET_TX_DESC_HW_RTS_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 13, 1, value) +#define GET_TX_DESC_HW_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 13, 1) +#define SET_TX_DESC_RTSEN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 12, 1, value) +#define GET_TX_DESC_RTSEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 12, 1) +#define SET_TX_DESC_CTS2SELF(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 1, value) +#define GET_TX_DESC_CTS2SELF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_CHANNEL_DMA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value) +#define GET_TX_DESC_CHANNEL_DMA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5) + +#endif -#define SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 13, 1, __Value) -#define GET_TX_DESC_HW_RTS_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 13, 1) -#define SET_TX_DESC_RTSEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 12, 1, __Value) -#define GET_TX_DESC_RTSEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 12, 1) -#define SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 11, 1, __Value) -#define GET_TX_DESC_CTS2SELF(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 11, 1) -#define SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 10, 1, __Value) -#define GET_TX_DESC_DISDATAFB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 10, 1) -#define SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 9, 1, __Value) -#define GET_TX_DESC_DISRTSFB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 9, 1) -#define SET_TX_DESC_USE_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 8, 1, __Value) -#define GET_TX_DESC_USE_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 8, 1) -#define SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 6, 2, __Value) -#define GET_TX_DESC_HW_SSN_SEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 6, 2) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_DISDATAFB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 10, 1, value) +#define GET_TX_DESC_DISDATAFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 10, 1) +#define SET_TX_DESC_DISRTSFB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 9, 1, value) +#define GET_TX_DESC_DISRTSFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 9, 1) +#define SET_TX_DESC_USE_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 8, 1, value) +#define GET_TX_DESC_USE_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 8, 1) +#define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 2, value) +#define GET_TX_DESC_HW_SSN_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814B_SUPPORT) -#define SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 0, 5, __Value) -#define GET_TX_DESC_WHEADER_LEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 0, 5) +#define SET_TX_DESC_IE_CNT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 3, value) +#define GET_TX_DESC_IE_CNT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 3) +#define SET_TX_DESC_IE_CNT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 5, 1, value) +#define GET_TX_DESC_IE_CNT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 5, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) +#define SET_TX_DESC_WHEADER_LEN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value) +#define GET_TX_DESC_WHEADER_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5) -/*TXDESC_WORD4*/ +#endif -#define SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 30, 2, __Value) -#define GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 30, 2) -#define SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 29, 1, __Value) -#define GET_TX_DESC_PCTS_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 29, 1) -#define SET_TX_DESC_RTSRATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 24, 5, __Value) -#define GET_TX_DESC_RTSRATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 24, 5) -#define SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 18, 6, __Value) -#define GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 18, 6) -#define SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 17, 1, __Value) -#define GET_TX_DESC_RTY_LMT_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 17, 1) -#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 13, 4, __Value) -#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 13, 4) -#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 8, 5, __Value) -#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 8, 5) -#define SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 7, 1, __Value) -#define GET_TX_DESC_TRY_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 7, 1) -#define SET_TX_DESC_DATARATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 0, 7, __Value) -#define GET_TX_DESC_DATARATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 0, 7) +#if (HALMAC_8814B_SUPPORT) + +#define SET_TX_DESC_WHEADER_LEN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value) +#define GET_TX_DESC_WHEADER_LEN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +/*TXDESC_WORD4*/ +#define SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 30, 2, value) +#define GET_TX_DESC_PCTS_MASK_IDX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 30, 2) +#define SET_TX_DESC_PCTS_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 29, 1, value) +#define GET_TX_DESC_PCTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 29, 1) +#define SET_TX_DESC_RTSRATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 5, value) +#define GET_TX_DESC_RTSRATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 24, 5) +#define SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 18, 6, value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 18, 6) +#define SET_TX_DESC_RTY_LMT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 17, 1, value) +#define GET_TX_DESC_RTY_LMT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 17, 1) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 13, 4, value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 13, 4) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 8, 5, value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x10, 8, 5) +#define SET_TX_DESC_TRY_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 7, 1, value) +#define GET_TX_DESC_TRY_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 7, 1) +#define SET_TX_DESC_DATARATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 7, value) +#define GET_TX_DESC_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 0, 7) /*TXDESC_WORD5*/ -#define SET_TX_DESC_POLLUTED(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 31, 1, __Value) -#define GET_TX_DESC_POLLUTED(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 31, 1) +#define SET_TX_DESC_POLLUTED(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value) +#define GET_TX_DESC_POLLUTED(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 28, 3, __Value) -#define GET_TX_DESC_TXPWR_OFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 28, 3) -#define SET_TX_DESC_TX_ANT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 24, 4, __Value) -#define GET_TX_DESC_TX_ANT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 24, 4) -#define SET_TX_DESC_PORT_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 21, 3, __Value) -#define GET_TX_DESC_PORT_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 21, 3) +#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value) +#define GET_TX_DESC_ANTSEL_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 18, 3, __Value) -#define GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 18, 3) +#define SET_TX_DESC_TXPWR_OFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 3, value) +#define GET_TX_DESC_TXPWR_OFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 3) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 17, 1, __Value) -#define GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 17, 1) +#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 2, value) +#define GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_RTS_SC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 13, 4, __Value) -#define GET_TX_DESC_RTS_SC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 13, 4) -#define SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 12, 1, __Value) -#define GET_TX_DESC_RTS_SHORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 12, 1) +#define SET_TX_DESC_TX_ANT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value) +#define GET_TX_DESC_TX_ANT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 10, 2, __Value) -#define GET_TX_DESC_VCS_STBC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 10, 2) +#define SET_TX_DESC_DROP_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 2, value) +#define GET_TX_DESC_DROP_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 2) #endif -#if (HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_RTS_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 10, 2, __Value) -#define GET_TX_DESC_RTS_STBC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 10, 2) +#define SET_TX_DESC_PORT_ID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 21, 3, value) +#define GET_TX_DESC_PORT_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 21, 3) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \ + HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 8, 2, __Value) -#define GET_TX_DESC_DATA_STBC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 8, 2) +#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 18, 3, value) +#define GET_TX_DESC_MULTIPLE_PORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 18, 3) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 7, 1, __Value) -#define GET_TX_DESC_DATA_LDPC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 7, 1) +#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 17, 1, value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 17, 1) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_DATA_BW(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 5, 2, __Value) -#define GET_TX_DESC_DATA_BW(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 5, 2) -#define SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 4, 1, __Value) -#define GET_TX_DESC_DATA_SHORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 4, 1) -#define SET_TX_DESC_DATA_SC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 0, 4, __Value) -#define GET_TX_DESC_DATA_SC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 0, 4) +#define SET_TX_DESC_RTS_SC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value) +#define GET_TX_DESC_RTS_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) +#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value) +#define GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_RTS_SHORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 12, 1, value) +#define GET_TX_DESC_RTS_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 12, 1) +#define SET_TX_DESC_VCS_STBC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 10, 2, value) +#define GET_TX_DESC_VCS_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 10, 2) +#define SET_TX_DESC_DATA_STBC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 2, value) +#define GET_TX_DESC_DATA_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 8, 2) +#define SET_TX_DESC_DATA_LDPC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value) +#define GET_TX_DESC_DATA_LDPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1) +#define SET_TX_DESC_DATA_BW(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 5, 2, value) +#define GET_TX_DESC_DATA_BW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 5, 2) +#define SET_TX_DESC_DATA_SHORT(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 4, 1, value) +#define GET_TX_DESC_DATA_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 4, 1) +#define SET_TX_DESC_DATA_SC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 4, value) +#define GET_TX_DESC_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 4) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) /*TXDESC_WORD6*/ -#define SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 30, 2, __Value) -#define GET_TX_DESC_ANTSEL_D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 30, 2) -#define SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 28, 2, __Value) -#define GET_TX_DESC_ANT_MAPD(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 28, 2) -#define SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 26, 2, __Value) -#define GET_TX_DESC_ANT_MAPC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 26, 2) -#define SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 24, 2, __Value) -#define GET_TX_DESC_ANT_MAPB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 24, 2) -#define SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 22, 2, __Value) -#define GET_TX_DESC_ANT_MAPA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 22, 2) -#define SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 20, 2, __Value) -#define GET_TX_DESC_ANTSEL_C(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 20, 2) -#define SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 18, 2, __Value) -#define GET_TX_DESC_ANTSEL_B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 18, 2) +#define SET_TX_DESC_ANTSEL_D(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value) +#define GET_TX_DESC_ANTSEL_D(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 16, 2, __Value) -#define GET_TX_DESC_ANTSEL_A(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 16, 2) -#define SET_TX_DESC_MBSSID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 12, 4, __Value) -#define GET_TX_DESC_MBSSID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 12, 4) -#define SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 0, 12, __Value) -#define GET_TX_DESC_SW_DEFINE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 0, 12) +#define SET_TX_DESC_ANT_MAPD_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value) +#define GET_TX_DESC_ANT_MAPD_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2) -/*TXDESC_WORD7*/ +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 24, 8, __Value) -#define GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 24, 8) +#define SET_TX_DESC_ANT_MAPD(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value) +#define GET_TX_DESC_ANT_MAPD(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 24, 8, __Value) -#define GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 24, 8) -#define SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 20, 4, __Value) -#define GET_TX_DESC_NTX_MAP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 20, 4) +#define SET_TX_DESC_ANT_MAPC_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value) +#define GET_TX_DESC_ANT_MAPC_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value) -#define GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16) -#define SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value) -#define GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16) -#define SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value) -#define GET_TX_DESC_TIMESTAMP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16) +#define SET_TX_DESC_ANT_MAPC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value) +#define GET_TX_DESC_ANT_MAPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) +#define SET_TX_DESC_ANT_MAPB_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value) +#define GET_TX_DESC_ANT_MAPB_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2) -/*TXDESC_WORD8*/ +#endif -#define SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 31, 1, __Value) -#define GET_TX_DESC_TXWIFI_CP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 31, 1) -#define SET_TX_DESC_MAC_CP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 30, 1, __Value) -#define GET_TX_DESC_MAC_CP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 30, 1) -#define SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 29, 1, __Value) -#define GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 29, 1) -#define SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 28, 1, __Value) -#define GET_TX_DESC_STW_RB_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 28, 1) -#define SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 27, 1, __Value) -#define GET_TX_DESC_STW_RATE_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 27, 1) -#define SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 26, 1, __Value) -#define GET_TX_DESC_STW_ANT_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 26, 1) -#define SET_TX_DESC_STW_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 25, 1, __Value) -#define GET_TX_DESC_STW_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 25, 1) -#define SET_TX_DESC_SMH_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 24, 1, __Value) -#define GET_TX_DESC_SMH_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 24, 1) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_ANT_MAPB(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value) +#define GET_TX_DESC_ANT_MAPB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 24, 8, __Value) -#define GET_TX_DESC_TAILPAGE_L(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 24, 8) +#define SET_TX_DESC_ANT_MAPA_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value) +#define GET_TX_DESC_ANT_MAPA_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 16, 8, __Value) -#define GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 16, 8) +#define SET_TX_DESC_ANT_MAPA(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 22, 2, value) +#define GET_TX_DESC_ANT_MAPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 22, 2) +#define SET_TX_DESC_ANTSEL_C(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 2, value) +#define GET_TX_DESC_ANTSEL_C(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 16, 8, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 16, 8) -#define SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 15, 1, __Value) -#define GET_TX_DESC_EN_HWSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 15, 1) +#define SET_TX_DESC_ANTSEL_B_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 4, value) +#define GET_TX_DESC_ANTSEL_B_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 4) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) -#define SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 14, 1, __Value) -#define GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 14, 1) +#define SET_TX_DESC_ANTSEL_B(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 18, 2, value) +#define GET_TX_DESC_ANTSEL_B(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 18, 2) +#define SET_TX_DESC_ANTSEL_A(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 2, value) +#define GET_TX_DESC_ANTSEL_A(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 2) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_DATA_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 8, 6, __Value) -#define GET_TX_DESC_DATA_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 8, 6) -#define SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 6, 2, __Value) -#define GET_TX_DESC_BAR_RTY_TH(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 6, 2) -#define SET_TX_DESC_RTS_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 0, 6, __Value) -#define GET_TX_DESC_RTS_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 0, 6) +#define SET_TX_DESC_ANTSEL_A_V1(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 4, value) +#define GET_TX_DESC_ANTSEL_A_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 4) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) +#define SET_TX_DESC_MBSSID(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 4, value) +#define GET_TX_DESC_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 4) -/*TXDESC_WORD9*/ +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_SW_DEFINE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value) +#define GET_TX_DESC_SW_DEFINE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12) + +#endif + +#if (HALMAC_8198F_SUPPORT) -#define SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 28, 4, __Value) -#define GET_TX_DESC_TAILPAGE_H(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 28, 4) -#define SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 24, 4, __Value) -#define GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 24, 4) +#define SET_TX_DESC_SWPS_SEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value) +#define GET_TX_DESC_SWPS_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12) #endif -#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT) +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +/*TXDESC_WORD7*/ -#define SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 12, 12, __Value) -#define GET_TX_DESC_SW_SEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 12, 12) -#define SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 11, 1, __Value) -#define GET_TX_DESC_TXBF_PATH(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 11, 1) -#define SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 0, 11, __Value) -#define GET_TX_DESC_PADDING_LEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 0, 11) -#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 0, 8, __Value) -#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 0, 8) +#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value) +#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8) +#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value) +#define GET_TX_DESC_FINAL_DATA_RATE(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8) +#define SET_TX_DESC_NTX_MAP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 20, 4, value) +#define GET_TX_DESC_NTX_MAP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 20, 4) #endif -#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT) +#if (HALMAC_8198F_SUPPORT) + +#define SET_TX_DESC_ANTSEL_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 19, 1, value) +#define GET_TX_DESC_ANTSEL_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 19, 1) +#define SET_TX_DESC_MBSSID_EX(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 3, value) +#define GET_TX_DESC_MBSSID_EX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 3) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value) +#define GET_TX_DESC_TX_BUFF_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16) +#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value) +#define GET_TX_DESC_TXDESC_CHECKSUM(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16) +#define SET_TX_DESC_TIMESTAMP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value) +#define GET_TX_DESC_TIMESTAMP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_TXWIFI_CP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 31, 1, value) +#define GET_TX_DESC_TXWIFI_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 31, 1) +#define SET_TX_DESC_MAC_CP(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 1, value) +#define GET_TX_DESC_MAC_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 30, 1) +#define SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 29, 1, value) +#define GET_TX_DESC_STW_PKTRE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 29, 1) +#define SET_TX_DESC_STW_RB_DIS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 1, value) +#define GET_TX_DESC_STW_RB_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 28, 1) +#define SET_TX_DESC_STW_RATE_DIS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 27, 1, value) +#define GET_TX_DESC_STW_RATE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 27, 1) +#define SET_TX_DESC_STW_ANT_DIS(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 1, value) +#define GET_TX_DESC_STW_ANT_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 26, 1) +#define SET_TX_DESC_STW_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 25, 1, value) +#define GET_TX_DESC_STW_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 25, 1) +#define SET_TX_DESC_SMH_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 1, value) +#define GET_TX_DESC_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 1) +#define SET_TX_DESC_TAILPAGE_L(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 8, value) +#define GET_TX_DESC_TAILPAGE_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 8) +#define SET_TX_DESC_SDIO_DMASEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value) +#define GET_TX_DESC_SDIO_DMASEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8) +#define SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value) +#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT) + +#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 15, 1, value) +#define GET_TX_DESC_EN_HWSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 15, 1) +#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 1, value) +#define GET_TX_DESC_EN_HWEXSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 1) + +#endif +#if (HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_EN_HWSEQ_MODE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 2, value) +#define GET_TX_DESC_EN_HWSEQ_MODE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 2) + +#endif + +#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \ + HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_DATA_RC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 6, value) +#define GET_TX_DESC_DATA_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 6) +#define SET_TX_DESC_BAR_RTY_TH(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 6, 2, value) +#define GET_TX_DESC_BAR_RTY_TH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 6, 2) +#define SET_TX_DESC_RTS_RC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 6, value) +#define GET_TX_DESC_RTS_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 6) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_TAILPAGE_H(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 4, value) +#define GET_TX_DESC_TAILPAGE_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 28, 4) +#define SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value) +#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4) +#define SET_TX_DESC_SW_SEQ(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 12, 12, value) +#define GET_TX_DESC_SW_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 12, 12) +#define SET_TX_DESC_TXBF_PATH(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 11, 1, value) +#define GET_TX_DESC_TXBF_PATH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 11, 1) +#define SET_TX_DESC_PADDING_LEN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 11, value) +#define GET_TX_DESC_PADDING_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 11) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 8, value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) \ + LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 8) + +#endif + +#if (HALMAC_8812F_SUPPORT) /*WORD10*/ -#define SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 8, 8, __Value) -#define GET_TX_DESC_MU_DATARATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 8, 8) -#define SET_TX_DESC_MU_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 4, 4, __Value) -#define GET_TX_DESC_MU_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 4, 4) -#define SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 0, 2, __Value) -#define GET_TX_DESC_SND_PKT_SEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 0, 2) +#define SET_TX_DESC_HT_DATA_SND(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 31, 1, value) +#define GET_TX_DESC_HT_DATA_SND(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 31, 1) +#define SET_TX_DESC_SHCUT_CAM(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 16, 6, value) +#define GET_TX_DESC_SHCUT_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 16, 6) #endif +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_MU_DATARATE(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value) +#define GET_TX_DESC_MU_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8) +#define SET_TX_DESC_MU_RC(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 4, value) +#define GET_TX_DESC_MU_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 4) + +#endif + +#if (HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_NDPA_RATE_SEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 3, 1, value) +#define GET_TX_DESC_NDPA_RATE_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 3, 1) +#define SET_TX_DESC_HW_NDPA_EN(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 2, 1, value) +#define GET_TX_DESC_HW_NDPA_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 2, 1) + +#endif + +#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \ + HALMAC_8812F_SUPPORT) + +#define SET_TX_DESC_SND_PKT_SEL(txdesc, value) \ + SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value) +#define GET_TX_DESC_SND_PKT_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2) + +#endif #endif diff --git a/hal/halmac/halmac_type.h b/hal/halmac/halmac_type.h index 6b333f9..5d0c520 100644 --- a/hal/halmac/halmac_type.h +++ b/hal/halmac/halmac_type.h @@ -1,3 +1,18 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef _HALMAC_TYPE_H_ #define _HALMAC_TYPE_H_ @@ -5,92 +20,215 @@ #include "halmac_hw_cfg.h" #include "halmac_fw_info.h" #include "halmac_intf_phy_cmd.h" +#include "halmac_state_machine.h" #define IN #define OUT #define INOUT -#define VOID void - -#define HALMAC_SCAN_CH_NUM_MAX 28 -#define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */ -#define HALMAC_PHY_PARAMETER_SIZE 12 -#define HALMAC_PHY_PARAMETER_MAX_NUM 128 -#define HALMAC_MAX_SSID_LEN 32 -#define HALMAC_SUPPORT_NLO_NUM 16 -#define HALMAC_SUPPORT_PROBE_REQ_NUM 8 -#define HALMC_DDMA_POLLING_COUNT 1000 -#define API_ARRAY_SIZE 32 + +#define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */ #ifndef HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE -#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 48 +#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 80 +#endif + +#ifndef HALMAC_MSG_LEVEL_TRACE +#define HALMAC_MSG_LEVEL_TRACE 3 +#endif + +#ifndef HALMAC_MSG_LEVEL_WARNING +#define HALMAC_MSG_LEVEL_WARNING 2 +#endif + +#ifndef HALMAC_MSG_LEVEL_ERR +#define HALMAC_MSG_LEVEL_ERR 1 +#endif + +#ifndef HALMAC_MSG_LEVEL_NO_LOG +#define HALMAC_MSG_LEVEL_NO_LOG 0 +#endif + +#ifndef HALMAC_SDIO_SUPPORT +#define HALMAC_SDIO_SUPPORT 1 +#endif + +#ifndef HALMAC_USB_SUPPORT +#define HALMAC_USB_SUPPORT 1 +#endif + +#ifndef HALMAC_PCIE_SUPPORT +#define HALMAC_PCIE_SUPPORT 1 +#endif + +#ifndef HALMAC_MSG_LEVEL +#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE #endif /* platform api */ -#define PLATFORM_SDIO_CMD52_READ pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_READ -#define PLATFORM_SDIO_CMD53_READ_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_8 -#define PLATFORM_SDIO_CMD53_READ_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_16 -#define PLATFORM_SDIO_CMD53_READ_32 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_32 -#define PLATFORM_SDIO_CMD53_READ_N pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_N -#define PLATFORM_SDIO_CMD52_WRITE pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_WRITE -#define PLATFORM_SDIO_CMD53_WRITE_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_8 -#define PLATFORM_SDIO_CMD53_WRITE_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_16 -#define PLATFORM_SDIO_CMD53_WRITE_32 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_32 - -#define PLATFORM_REG_READ_8 pHalmac_adapter->pHalmac_platform_api->REG_READ_8 -#define PLATFORM_REG_READ_16 pHalmac_adapter->pHalmac_platform_api->REG_READ_16 -#define PLATFORM_REG_READ_32 pHalmac_adapter->pHalmac_platform_api->REG_READ_32 -#define PLATFORM_REG_WRITE_8 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_8 -#define PLATFORM_REG_WRITE_16 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_16 -#define PLATFORM_REG_WRITE_32 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_32 - -#define PLATFORM_SEND_RSVD_PAGE pHalmac_adapter->pHalmac_platform_api->SEND_RSVD_PAGE -#define PLATFORM_SEND_H2C_PKT pHalmac_adapter->pHalmac_platform_api->SEND_H2C_PKT - -#define PLATFORM_RTL_FREE pHalmac_adapter->pHalmac_platform_api->RTL_FREE -#define PLATFORM_RTL_MALLOC pHalmac_adapter->pHalmac_platform_api->RTL_MALLOC -#define PLATFORM_RTL_MEMCPY pHalmac_adapter->pHalmac_platform_api->RTL_MEMCPY -#define PLATFORM_RTL_MEMSET pHalmac_adapter->pHalmac_platform_api->RTL_MEMSET -#define PLATFORM_RTL_DELAY_US pHalmac_adapter->pHalmac_platform_api->RTL_DELAY_US - -#define PLATFORM_MUTEX_INIT pHalmac_adapter->pHalmac_platform_api->MUTEX_INIT -#define PLATFORM_MUTEX_DEINIT pHalmac_adapter->pHalmac_platform_api->MUTEX_DEINIT -#define PLATFORM_MUTEX_LOCK pHalmac_adapter->pHalmac_platform_api->MUTEX_LOCK -#define PLATFORM_MUTEX_UNLOCK pHalmac_adapter->pHalmac_platform_api->MUTEX_UNLOCK - -#define PLATFORM_EVENT_INDICATION pHalmac_adapter->pHalmac_platform_api->EVENT_INDICATION +#define PLTFM_SDIO_CMD52_R(offset) \ + adapter->pltfm_api->SDIO_CMD52_READ(adapter->drv_adapter, offset) +#define PLTFM_SDIO_CMD53_R8(offset) \ + adapter->pltfm_api->SDIO_CMD53_READ_8(adapter->drv_adapter, offset) +#define PLTFM_SDIO_CMD53_R16(offset) \ + adapter->pltfm_api->SDIO_CMD53_READ_16(adapter->drv_adapter, offset) +#define PLTFM_SDIO_CMD53_R32(offset) \ + adapter->pltfm_api->SDIO_CMD53_READ_32(adapter->drv_adapter, offset) +#define PLTFM_SDIO_CMD53_RN(offset, size, data) \ + adapter->pltfm_api->SDIO_CMD53_READ_N(adapter->drv_adapter, offset, \ + size, data) +#define PLTFM_SDIO_CMD52_W(offset, val) \ + adapter->pltfm_api->SDIO_CMD52_WRITE(adapter->drv_adapter, offset, val) +#define PLTFM_SDIO_CMD53_W8(offset, val) \ + adapter->pltfm_api->SDIO_CMD53_WRITE_8(adapter->drv_adapter, offset, \ + val) +#define PLTFM_SDIO_CMD53_W16(offset, val) \ + adapter->pltfm_api->SDIO_CMD53_WRITE_16(adapter->drv_adapter, offset, \ + val) +#define PLTFM_SDIO_CMD53_W32(offset, val) \ + adapter->pltfm_api->SDIO_CMD53_WRITE_32(adapter->drv_adapter, offset, \ + val) +#define PLTFM_SDIO_CMD52_CIA_R(offset) \ + adapter->pltfm_api->SDIO_CMD52_CIA_READ(adapter->drv_adapter, offset) + +#define PLTFM_REG_R8(offset) \ + adapter->pltfm_api->REG_READ_8(adapter->drv_adapter, offset) +#define PLTFM_REG_R16(offset) \ + adapter->pltfm_api->REG_READ_16(adapter->drv_adapter, offset) +#define PLTFM_REG_R32(offset) \ + adapter->pltfm_api->REG_READ_32(adapter->drv_adapter, offset) +#define PLTFM_REG_W8(offset, val) \ + adapter->pltfm_api->REG_WRITE_8(adapter->drv_adapter, offset, val) +#define PLTFM_REG_W16(offset, val) \ + adapter->pltfm_api->REG_WRITE_16(adapter->drv_adapter, offset, val) +#define PLTFM_REG_W32(offset, val) \ + adapter->pltfm_api->REG_WRITE_32(adapter->drv_adapter, offset, val) + +#define PLTFM_SEND_RSVD_PAGE(buf, size) \ + adapter->pltfm_api->SEND_RSVD_PAGE(adapter->drv_adapter, buf, size) +#define PLTFM_SEND_H2C_PKT(buf, size) \ + adapter->pltfm_api->SEND_H2C_PKT(adapter->drv_adapter, buf, size) + +#define PLTFM_FREE(buf, size) \ + adapter->pltfm_api->RTL_FREE(adapter->drv_adapter, buf, size) +#define PLTFM_MALLOC(size) \ + adapter->pltfm_api->RTL_MALLOC(adapter->drv_adapter, size) +#define PLTFM_MEMCPY(dest, src, size) \ + adapter->pltfm_api->RTL_MEMCPY(adapter->drv_adapter, dest, src, size) +#define PLTFM_MEMSET(addr, value, size) \ + adapter->pltfm_api->RTL_MEMSET(adapter->drv_adapter, addr, value, size) +#define PLTFM_DELAY_US(us) \ + adapter->pltfm_api->RTL_DELAY_US(adapter->drv_adapter, us) + +#define PLTFM_MUTEX_INIT(mutex) \ + adapter->pltfm_api->MUTEX_INIT(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_DEINIT(mutex) \ + adapter->pltfm_api->MUTEX_DEINIT(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_LOCK(mutex) \ + adapter->pltfm_api->MUTEX_LOCK(adapter->drv_adapter, mutex) +#define PLTFM_MUTEX_UNLOCK(mutex) \ + adapter->pltfm_api->MUTEX_UNLOCK(adapter->drv_adapter, mutex) + +#define PLTFM_EVENT_SIG(feature_id, proc_status, buf, size) \ + adapter->pltfm_api->EVENT_INDICATION(adapter->drv_adapter, feature_id, \ + proc_status, buf, size) + +#if HALMAC_PLATFORM_WINDOWS +#define PLTFM_MSG_PRINT adapter->pltfm_api->MSG_PRINT +#endif +#define PLTFM_MSG_ALWAYS(...) \ + adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \ + HALMAC_DBG_ALWAYS, __VA_ARGS__) #if HALMAC_DBG_MSG_ENABLE -#define PLATFORM_MSG_PRINT pHalmac_adapter->pHalmac_platform_api->MSG_PRINT + +/* Enable debug msg depends on HALMAC_MSG_LEVEL */ +#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_ERR) +#define PLTFM_MSG_ERR(...) \ + adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \ + HALMAC_DBG_ERR, __VA_ARGS__) #else -#define PLATFORM_MSG_PRINT(pDriver_adapter, msg_type, msg_level, fmt, ...) +#define PLTFM_MSG_ERR(...) do {} while (0) #endif -#if HALMAC_PLATFORM_TESTPROGRAM -#define PLATFORM_WRITE_DATA_SDIO_ADDR pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_SDIO_ADDR -#define PLATFORM_WRITE_DATA_USB_BULKOUT_ID pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_USB_BULKOUT_ID -#define PLATFORM_WRITE_DATA_PCIE_QUEUE pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_PCIE_QUEUE -#define PLATFORM_READ_DATA pHalmac_adapter->pHalmac_platform_api->READ_DATA +#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_WARNING) +#define PLTFM_MSG_WARN(...) \ + adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \ + HALMAC_DBG_WARN, __VA_ARGS__) +#else +#define PLTFM_MSG_WARN(...) do {} while (0) #endif -#define HALMAC_REG_READ_8 pHalmac_api->halmac_reg_read_8 -#define HALMAC_REG_READ_16 pHalmac_api->halmac_reg_read_16 -#define HALMAC_REG_READ_32 pHalmac_api->halmac_reg_read_32 -#define HALMAC_REG_WRITE_8 pHalmac_api->halmac_reg_write_8 -#define HALMAC_REG_WRITE_16 pHalmac_api->halmac_reg_write_16 -#define HALMAC_REG_WRITE_32 pHalmac_api->halmac_reg_write_32 -#define HALMAC_REG_SDIO_CMD53_READ_N pHalmac_api->halmac_reg_sdio_cmd53_read_n +#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_TRACE) +#define PLTFM_MSG_TRACE(...) \ + adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \ + HALMAC_DBG_TRACE, __VA_ARGS__) +#else +#define PLTFM_MSG_TRACE(...) do {} while (0) +#endif + +#else + +/* Disable debug msg */ +#define PLTFM_MSG_ERR(...) do {} while (0) +#define PLTFM_MSG_WARN(...) do {} while (0) +#define PLTFM_MSG_TRACE(...) do {} while (0) + +#endif + +#define HALMAC_REG_R8(offset) api->halmac_reg_read_8(adapter, offset) +#define HALMAC_REG_R16(offset) api->halmac_reg_read_16(adapter, offset) +#define HALMAC_REG_R32(offset) api->halmac_reg_read_32(adapter, offset) +#define HALMAC_REG_W8(offset, val) api->halmac_reg_write_8(adapter, offset, val) +#define HALMAC_REG_W16(offset, val) \ + api->halmac_reg_write_16(adapter, offset, val) +#define HALMAC_REG_W32(offset, val) \ + api->halmac_reg_write_32(adapter, offset, val) +#define HALMAC_REG_SDIO_RN(offset, size, data) \ + api->halmac_reg_sdio_cmd53_read_n(adapter, offset, size, data) + +#define HALMAC_REG_W8_CLR(offset, mask) \ + do { \ + u32 __offset = (u32)offset; \ + HALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) & ~(mask)); \ + } while (0) +#define HALMAC_REG_W16_CLR(offset, mask) \ + do { \ + u32 __offset = (u32)offset; \ + HALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) & ~(mask)); \ + } while (0) +#define HALMAC_REG_W32_CLR(offset, mask) \ + do { \ + u32 __offset = (u32)offset; \ + HALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) & ~(mask)); \ + } while (0) + +#define HALMAC_REG_W8_SET(offset, mask) \ + do { \ + u32 __offset = (u32)offset; \ + HALMAC_REG_W8(__offset, HALMAC_REG_R8(__offset) | mask); \ + } while (0) +#define HALMAC_REG_W16_SET(offset, mask) \ + do { \ + u32 __offset = (u32)offset; \ + HALMAC_REG_W16(__offset, HALMAC_REG_R16(__offset) | mask); \ + } while (0) +#define HALMAC_REG_W32_SET(offset, mask) \ + do { \ + u32 __offset = (u32)offset; \ + HALMAC_REG_W32(__offset, HALMAC_REG_R32(__offset) | mask); \ + } while (0) /* Swap Little-endian <-> Big-endia*/ -#define SWAP32(x) ((u32)( \ - (((u32)(x) & (u32)0x000000ff) << 24) | \ - (((u32)(x) & (u32)0x0000ff00) << 8) | \ - (((u32)(x) & (u32)0x00ff0000) >> 8) | \ - (((u32)(x) & (u32)0xff000000) >> 24))) +#define SWAP32(x) \ + ((u32)((((u32)(x) & (u32)0x000000ff) << 24) | \ + (((u32)(x) & (u32)0x0000ff00) << 8) | \ + (((u32)(x) & (u32)0x00ff0000) >> 8) | \ + (((u32)(x) & (u32)0xff000000) >> 24))) -#define SWAP16(x) ((u16)( \ - (((u16)(x) & (u16)0x00ff) << 8) | \ - (((u16)(x) & (u16)0xff00) >> 8))) +#define SWAP16(x) \ + ((u16)((((u16)(x) & (u16)0x00ff) << 8) | \ + (((u16)(x) & (u16)0xff00) >> 8))) /*1->Little endian 0->Big endian*/ #if HALMAC_SYSTEM_ENDIAN @@ -124,16 +262,16 @@ #if !((HALMAC_PLATFORM_WINDOWS == 1) && (HALMAC_PLATFORM_TESTPROGRAM == 0)) /* Byte Swapping routine */ -#ifndef EF1Byte -#define EF1Byte (u8) +#ifndef EF1BYTE +#define EF1BYTE (u8) #endif -#ifndef EF2Byte -#define EF2Byte rtk_le16_to_cpu +#ifndef EF2BYTE +#define EF2BYTE rtk_le16_to_cpu #endif -#ifndef EF4Byte -#define EF4Byte rtk_le32_to_cpu +#ifndef EF4BYTE +#define EF4BYTE rtk_le32_to_cpu #endif /* Example: @@ -143,8 +281,7 @@ * BIT_LEN_MASK_32(32) => 0xFFFFFFFF */ #ifndef BIT_LEN_MASK_32 -#define BIT_LEN_MASK_32(__BitLen) \ - (0xFFFFFFFF >> (32 - (__BitLen))) +#define BIT_LEN_MASK_32(__bitlen) (0xFFFFFFFF >> (32 - (__bitlen))) #endif /* Example: @@ -152,29 +289,24 @@ * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 */ #ifndef BIT_OFFSET_LEN_MASK_32 -#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \ - (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) +#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ + (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) #endif /* Return 4-byte value in host byte ordering from * 4-byte pointer in litten-endian system */ #ifndef LE_P4BYTE_TO_HOST_4BYTE -#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ - (EF4Byte(*((u32 *)(__pStart)))) +#define LE_P4BYTE_TO_HOST_4BYTE(__start) (EF4BYTE(*((u32 *)(__start)))) #endif - /* Translate subfield (continuous bits in little-endian) of * 4-byte value in litten byte to 4-byte value in host byte ordering */ #ifndef LE_BITS_TO_4BYTE -#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - (LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) \ - & \ - BIT_LEN_MASK_32(__BitLen) \ - ) +#define LE_BITS_TO_4BYTE(__start, __bitoffset, __bitlen) \ + ((LE_P4BYTE_TO_HOST_4BYTE(__start) >> (__bitoffset)) & \ + BIT_LEN_MASK_32(__bitlen)) #endif /* Mask subfield (continuous bits in little-endian) of 4-byte @@ -182,50 +314,47 @@ * value in host byte ordering */ #ifndef LE_BITS_CLEARED_TO_4BYTE -#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - ( \ - LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ - & \ - (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)) \ - ) +#define LE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen) \ + (LE_P4BYTE_TO_HOST_4BYTE(__start) & \ + (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen))) #endif /* Set subfield of little-endian 4-byte value to specified value */ #ifndef SET_BITS_TO_LE_4BYTE -#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ - do { \ - *((u32 *)(__pStart)) = \ - EF4Byte( \ - LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ - | \ - ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \ - ); \ +#define SET_BITS_TO_LE_4BYTE(__start, __bitoffset, __bitlen, __value) \ + do { \ + *((u32 *)(__start)) = \ + EF4BYTE( \ + LE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen) | \ + ((((u32)__value) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset))\ + ); \ } while (0) #endif #ifndef HALMAC_BIT_OFFSET_VAL_MASK_32 -#define HALMAC_BIT_OFFSET_VAL_MASK_32(__BitVal, __BitOffset) \ - (__BitVal << (__BitOffset)) +#define HALMAC_BIT_OFFSET_VAL_MASK_32(__bitval, __bitoffset) \ + (__bitval << (__bitoffset)) #endif #ifndef SET_MEM_OP -#define SET_MEM_OP(Dw, Value32, Mask, Shift) \ - (((Dw) & ~((Mask) << (Shift))) | (((Value32) & (Mask)) << (Shift))) +#define SET_MEM_OP(dw, value32, mask, shift) \ + (((dw) & ~((mask) << (shift))) | (((value32) & (mask)) << (shift))) #endif #ifndef HALMAC_SET_DESC_FIELD_CLR -#define HALMAC_SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \ - (Dw = (rtk_cpu_to_le32(SET_MEM_OP(rtk_cpu_to_le32(Dw), Value32, Mask, Shift)))) +#define HALMAC_SET_DESC_FIELD_CLR(dw, value32, mask, shift) \ + (dw = (rtk_cpu_to_le32( \ + SET_MEM_OP(rtk_cpu_to_le32(dw), value32, mask, shift)))) #endif #ifndef HALMAC_SET_DESC_FIELD_NO_CLR -#define HALMAC_SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \ - (Dw |= (rtk_cpu_to_le32(((Value32) & (Mask)) << (Shift)))) +#define HALMAC_SET_DESC_FIELD_NO_CLR(dw, value32, mask, shift) \ + (dw |= (rtk_cpu_to_le32(((value32) & (mask)) << (shift)))) #endif #ifndef HALMAC_GET_DESC_FIELD -#define HALMAC_GET_DESC_FIELD(Dw, Mask, Shift) \ - ((rtk_le32_to_cpu(Dw) >> (Shift)) & (Mask)) +#define HALMAC_GET_DESC_FIELD(dw, mask, shift) \ + ((rtk_le32_to_cpu(dw) >> (shift)) & (mask)) #endif #define HALMAC_SET_BD_FIELD_CLR HALMAC_SET_DESC_FIELD_CLR @@ -262,10 +391,15 @@ #define BIT(x) (1 << (x)) #endif +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#endif + /* HALMAC API return status*/ -typedef enum _HALMAC_RET_STATUS { +enum halmac_ret_status { HALMAC_RET_SUCCESS = 0x00, - HALMAC_RET_SUCCESS_ENQUEUE = 0x01, + HALMAC_RET_NOT_SUPPORT = 0x01, + HALMAC_RET_SUCCESS_ENQUEUE = 0x01, /*Don't use this return code!!*/ HALMAC_RET_PLATFORM_API_NULL = 0x02, HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03, HALMAC_RET_MALLOC_FAIL = 0x04, @@ -273,7 +407,7 @@ typedef enum _HALMAC_RET_STATUS { HALMAC_RET_ITF_INCORRECT = 0x06, HALMAC_RET_DLFW_FAIL = 0x07, HALMAC_RET_PORT_NOT_SUPPORT = 0x08, - HALMAC_RET_TRXMODE_NOT_SUPPORT = 0x09, + HALMAC_RET_TXAGG_OVERFLOW = 0x09, HALMAC_RET_INIT_LLT_FAIL = 0x0A, HALMAC_RET_POWER_STATE_INVALID = 0x0B, HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C, @@ -339,7 +473,6 @@ typedef enum _HALMAC_RET_STATUS { HALMAC_RET_EEPROM_PARSING_FAIL = 0x48, HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49, HALMAC_RET_WRONG_ARGUMENT = 0x4A, - HALMAC_RET_NOT_SUPPORT = 0x4B, HALMAC_RET_C2H_NOT_HANDLED = 0x4C, HALMAC_RET_PARA_SENDING = 0x4D, HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E, @@ -357,60 +490,38 @@ typedef enum _HALMAC_RET_STATUS { HALMAC_RET_OQT_NOT_ENOUGH = 0x5A, HALMAC_RET_PWR_UNCHANGE = 0x5B, HALMAC_RET_WRONG_INTF = 0x5C, + HALMAC_RET_POLLING_HIOE_REQ_FAIL = 0x5E, + HALMAC_RET_HIOE_CHKSUM_FAIL = 0x5F, + HALMAC_RET_HIOE_ERR = 0x60, HALMAC_RET_FW_NO_SUPPORT = 0x60, HALMAC_RET_TXFIFO_NO_EMPTY = 0x61, HALMAC_RET_SDIO_CLOCK_ERR = 0x62, -} HALMAC_RET_STATUS; - -typedef enum _HALMAC_MAC_CLOCK_HW_DEF { - HALMAC_MAC_CLOCK_HW_DEF_80M = 0, - HALMAC_MAC_CLOCK_HW_DEF_40M = 1, - HALMAC_MAC_CLOCK_HW_DEF_20M = 2, -} HALMAC_MAC_CLOCK_HW_DEF; - -/* Rx aggregation parameters */ -typedef enum _HALMAC_NORMAL_RXAGG_TH_TO { - HALMAC_NORMAL_RXAGG_THRESHOLD = 0xFF, - HALMAC_NORMAL_RXAGG_TIMEOUT = 0x01, -} HALMAC_NORMAL_RXAGG_TH_TO; - -typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO { - HALMAC_LOOPBACK_RXAGG_THRESHOLD = 0xFF, - HALMAC_LOOPBACK_RXAGG_TIMEOUT = 0x01, -} HALMAC_LOOPBACK_RXAGG_TH_TO; - -/* Chip ID*/ -typedef enum _HALMAC_CHIP_ID { + HALMAC_RET_GET_PINMUX_ERR = 0x63, + HALMAC_RET_PINMUX_USED = 0x64, + HALMAC_RET_WRONG_GPIO = 0x65, + HALMAC_RET_LTECOEX_READY_FAIL = 0x66, + HALMAC_RET_IDMEM_CHKSUM_FAIL = 0x67, + HALMAC_RET_ILLEGAL_KEY_FAIL = 0x68, + HALMAC_RET_FW_READY_CHK_FAIL = 0x69, + HALMAC_RET_RSVD_PG_OVERFLOW_FAIL = 0x70, + HALMAC_RET_THRESHOLD_FAIL = 0x71, + HALMAC_RET_SDIO_MIX_MODE = 0x72, + HALMAC_RET_TXDESC_SET_FAIL = 0x73, + HALMAC_RET_WLHDR_FAIL = 0x74, + HALMAC_RET_WLAN_MODE_FAIL = 0x75, +}; + +enum halmac_chip_id { HALMAC_CHIP_ID_8822B = 0, HALMAC_CHIP_ID_8821C = 1, HALMAC_CHIP_ID_8814B = 2, HALMAC_CHIP_ID_8197F = 3, + HALMAC_CHIP_ID_8822C = 4, + HALMAC_CHIP_ID_8812F = 5, HALMAC_CHIP_ID_UNDEFINE = 0x7F, -} HALMAC_CHIP_ID; - -typedef enum _HALMAC_CHIP_ID_HW_DEF { - HALMAC_CHIP_ID_HW_DEF_8723A = 0x01, - HALMAC_CHIP_ID_HW_DEF_8188E = 0x02, - HALMAC_CHIP_ID_HW_DEF_8881A = 0x03, - HALMAC_CHIP_ID_HW_DEF_8812A = 0x04, - HALMAC_CHIP_ID_HW_DEF_8821A = 0x05, - HALMAC_CHIP_ID_HW_DEF_8723B = 0x06, - HALMAC_CHIP_ID_HW_DEF_8192E = 0x07, - HALMAC_CHIP_ID_HW_DEF_8814A = 0x08, - HALMAC_CHIP_ID_HW_DEF_8821C = 0x09, - HALMAC_CHIP_ID_HW_DEF_8822B = 0x0A, - HALMAC_CHIP_ID_HW_DEF_8703B = 0x0B, - HALMAC_CHIP_ID_HW_DEF_8188F = 0x0C, - HALMAC_CHIP_ID_HW_DEF_8192F = 0x0D, - HALMAC_CHIP_ID_HW_DEF_8197F = 0x0E, - HALMAC_CHIP_ID_HW_DEF_8723D = 0x0F, - HALMAC_CHIP_ID_HW_DEF_8814B = 0x10, - HALMAC_CHIP_ID_HW_DEF_UNDEFINE = 0x7F, - HALMAC_CHIP_ID_HW_DEF_PS = 0xEA, -} HALMAC_CHIP_ID_HW_DEF; - -/* Chip Version*/ -typedef enum _HALMAC_CHIP_VER { +}; + +enum halmac_chip_ver { HALMAC_CHIP_VER_A_CUT = 0x00, HALMAC_CHIP_VER_B_CUT = 0x01, HALMAC_CHIP_VER_C_CUT = 0x02, @@ -419,33 +530,37 @@ typedef enum _HALMAC_CHIP_VER { HALMAC_CHIP_VER_F_CUT = 0x05, HALMAC_CHIP_VER_TEST = 0xFF, HALMAC_CHIP_VER_UNDEFINE = 0x7FFF, -} HALMAC_CHIP_VER; +}; -/* Network type select */ -typedef enum _HALMAC_NETWORK_TYPE_SELECT { +enum halmac_network_type_select { HALMAC_NETWORK_NO_LINK = 0, HALMAC_NETWORK_ADHOC = 1, HALMAC_NETWORK_INFRASTRUCTURE = 2, HALMAC_NETWORK_AP = 3, HALMAC_NETWORK_UNDEFINE = 0x7F, -} HALMAC_NETWORK_TYPE_SELECT; +}; -/* Transfer mode select */ -typedef enum _HALMAC_TRNSFER_MODE_SELECT { +enum halmac_transfer_mode_select { HALMAC_TRNSFER_NORMAL = 0x0, HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB, HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3, HALMAC_TRNSFER_UNDEFINE = 0x7F, -} HALMAC_TRNSFER_MODE_SELECT; +}; -/* Queue select */ -typedef enum _HALMAC_DMA_MAPPING { +enum halmac_dma_mapping { HALMAC_DMA_MAPPING_EXTRA = 0, HALMAC_DMA_MAPPING_LOW = 1, HALMAC_DMA_MAPPING_NORMAL = 2, HALMAC_DMA_MAPPING_HIGH = 3, HALMAC_DMA_MAPPING_UNDEFINE = 0x7F, -} HALMAC_DMA_MAPPING; +}; + +enum halmac_io_size { + HALMAC_IO_BYTE = 0x0, + HALMAC_IO_WORD = 0x1, + HALMAC_IO_DWORD = 0x2, + HALMAC_IO_UNDEFINE = 0x7F, +}; #define HALMAC_MAP2_HQ HALMAC_DMA_MAPPING_HIGH #define HALMAC_MAP2_NQ HALMAC_DMA_MAPPING_NORMAL @@ -453,8 +568,7 @@ typedef enum _HALMAC_DMA_MAPPING { #define HALMAC_MAP2_EXQ HALMAC_DMA_MAPPING_EXTRA #define HALMAC_MAP2_UNDEF HALMAC_DMA_MAPPING_UNDEFINE -/* TXDESC queue select TID */ -typedef enum _HALMAC_TXDESC_QUEUE_TID { +enum halmac_txdesc_queue_tid { HALMAC_TXDESC_QSEL_TID0 = 0, HALMAC_TXDESC_QSEL_TID1 = 1, HALMAC_TXDESC_QSEL_TID2 = 2, @@ -476,88 +590,143 @@ typedef enum _HALMAC_TXDESC_QUEUE_TID { HALMAC_TXDESC_QSEL_HIGH = 0x11, HALMAC_TXDESC_QSEL_MGT = 0x12, HALMAC_TXDESC_QSEL_H2C_CMD = 0x13, + HALMAC_TXDESC_QSEL_FWCMD = 0x14, HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F, -} HALMAC_TXDESC_QUEUE_TID; - -typedef enum _HALMAC_PTCL_QUEUE { - HALMAC_PTCL_QUEUE_VO = 0x0, - HALMAC_PTCL_QUEUE_VI = 0x1, - HALMAC_PTCL_QUEUE_BE = 0x2, - HALMAC_PTCL_QUEUE_BK = 0x3, - HALMAC_PTCL_QUEUE_MG = 0x4, - HALMAC_PTCL_QUEUE_HI = 0x5, - HALMAC_PTCL_QUEUE_NUM = 0x6, - HALMAC_PTCL_QUEUE_UNDEFINE = 0x7F, -} HALMAC_PTCL_QUEUE; - -typedef enum { - HALMAC_QUEUE_SELECT_VO = HALMAC_TXDESC_QSEL_TID6, - HALMAC_QUEUE_SELECT_VI = HALMAC_TXDESC_QSEL_TID4, - HALMAC_QUEUE_SELECT_BE = HALMAC_TXDESC_QSEL_TID0, - HALMAC_QUEUE_SELECT_BK = HALMAC_TXDESC_QSEL_TID1, - HALMAC_QUEUE_SELECT_VO_V2 = HALMAC_TXDESC_QSEL_TID7, - HALMAC_QUEUE_SELECT_VI_V2 = HALMAC_TXDESC_QSEL_TID5, - HALMAC_QUEUE_SELECT_BE_V2 = HALMAC_TXDESC_QSEL_TID3, - HALMAC_QUEUE_SELECT_BK_V2 = HALMAC_TXDESC_QSEL_TID2, - HALMAC_QUEUE_SELECT_BCN = HALMAC_TXDESC_QSEL_BEACON, - HALMAC_QUEUE_SELECT_HIGH = HALMAC_TXDESC_QSEL_HIGH, - HALMAC_QUEUE_SELECT_MGNT = HALMAC_TXDESC_QSEL_MGT, - HALMAC_QUEUE_SELECT_CMD = HALMAC_TXDESC_QSEL_H2C_CMD, - HALMAC_QUEUE_SELECT_UNDEFINE = 0x7F, -} HALMAC_QUEUE_SELECT; - - -/* USB burst size */ -typedef enum _HALMAC_USB_BURST_SIZE { - HALMAC_USB_BURST_SIZE_3_0 = 0x0, - HALMAC_USB_BURST_SIZE_2_0_HSPEED = 0x1, - HALMAC_USB_BURST_SIZE_2_0_FSPEED = 0x2, - HALMAC_USB_BURST_SIZE_2_0_OTHERS = 0x3, - HALMAC_USB_BURST_SIZE_UNDEFINE = 0x7F, -} HALMAC_USB_BURST_SIZE; - -/* HAL API function parameters*/ -typedef enum _HALMAC_INTERFACE { +}; + +enum halmac_pq_map_id { + HALMAC_PQ_MAP_VO = 0x0, + HALMAC_PQ_MAP_VI = 0x1, + HALMAC_PQ_MAP_BE = 0x2, + HALMAC_PQ_MAP_BK = 0x3, + HALMAC_PQ_MAP_MG = 0x4, + HALMAC_PQ_MAP_HI = 0x5, + HALMAC_PQ_MAP_NUM = 0x6, + HALMAC_PQ_MAP_UNDEF = 0x7F, +}; + +enum halmac_qsel { + HALMAC_QSEL_VO = HALMAC_TXDESC_QSEL_TID6, + HALMAC_QSEL_VI = HALMAC_TXDESC_QSEL_TID4, + HALMAC_QSEL_BE = HALMAC_TXDESC_QSEL_TID0, + HALMAC_QSEL_BK = HALMAC_TXDESC_QSEL_TID1, + HALMAC_QSEL_VO_V2 = HALMAC_TXDESC_QSEL_TID7, + HALMAC_QSEL_VI_V2 = HALMAC_TXDESC_QSEL_TID5, + HALMAC_QSEL_BE_V2 = HALMAC_TXDESC_QSEL_TID3, + HALMAC_QSEL_BK_V2 = HALMAC_TXDESC_QSEL_TID2, + HALMAC_QSEL_TID8 = HALMAC_TXDESC_QSEL_TID8, + HALMAC_QSEL_TID9 = HALMAC_TXDESC_QSEL_TID9, + HALMAC_QSEL_TIDA = HALMAC_TXDESC_QSEL_TIDA, + HALMAC_QSEL_TIDB = HALMAC_TXDESC_QSEL_TIDB, + HALMAC_QSEL_TIDC = HALMAC_TXDESC_QSEL_TIDC, + HALMAC_QSEL_TIDD = HALMAC_TXDESC_QSEL_TIDD, + HALMAC_QSEL_TIDE = HALMAC_TXDESC_QSEL_TIDE, + HALMAC_QSEL_TIDF = HALMAC_TXDESC_QSEL_TIDF, + HALMAC_QSEL_BCN = HALMAC_TXDESC_QSEL_BEACON, + HALMAC_QSEL_HIGH = HALMAC_TXDESC_QSEL_HIGH, + HALMAC_QSEL_MGNT = HALMAC_TXDESC_QSEL_MGT, + HALMAC_QSEL_CMD = HALMAC_TXDESC_QSEL_H2C_CMD, + HALMAC_QSEL_FWCMD = HALMAC_TXDESC_QSEL_FWCMD, + HALMAC_QSEL_UNDEFINE = 0x7F, +}; + +enum halmac_acq_id { + HALMAC_ACQ_ID_VO = 0, + HALMAC_ACQ_ID_VI = 1, + HALMAC_ACQ_ID_BE = 2, + HALMAC_ACQ_ID_BK = 3, + HALMAC_ACQ_ID_MAX = 0x7F, +}; + +enum halmac_txdesc_dma_ch { + HALMAC_TXDESC_DMA_CH0 = 0, + HALMAC_TXDESC_DMA_CH1 = 1, + HALMAC_TXDESC_DMA_CH2 = 2, + HALMAC_TXDESC_DMA_CH3 = 3, + HALMAC_TXDESC_DMA_CH4 = 4, + HALMAC_TXDESC_DMA_CH5 = 5, + HALMAC_TXDESC_DMA_CH6 = 6, + HALMAC_TXDESC_DMA_CH7 = 7, + HALMAC_TXDESC_DMA_CH8 = 8, + HALMAC_TXDESC_DMA_CH9 = 9, + HALMAC_TXDESC_DMA_CH10 = 10, + HALMAC_TXDESC_DMA_CH11 = 11, + HALMAC_TXDESC_DMA_CH12 = 12, + HALMAC_TXDESC_DMA_CH13 = 13, + HALMAC_TXDESC_DMA_CH14 = 14, + HALMAC_TXDESC_DMA_CH15 = 15, + HALMAC_TXDESC_DMA_CH16 = 16, + HALMAC_TXDESC_DMA_CH17 = 17, + HALMAC_TXDESC_DMA_CH18 = 18, + HALMAC_TXDESC_DMA_CH19 = 19, + HALMAC_TXDESC_DMA_CH20 = 20, + HALMAC_TXDESC_DMA_CHMAX, + HALMAC_TXDESC_DMA_CHUNDEFINE = 0x7F, +}; + +enum halmac_dma_ch { + HALMAC_DMA_CH_0 = HALMAC_TXDESC_DMA_CH0, + HALMAC_DMA_CH_1 = HALMAC_TXDESC_DMA_CH1, + HALMAC_DMA_CH_2 = HALMAC_TXDESC_DMA_CH2, + HALMAC_DMA_CH_3 = HALMAC_TXDESC_DMA_CH3, + HALMAC_DMA_CH_4 = HALMAC_TXDESC_DMA_CH4, + HALMAC_DMA_CH_5 = HALMAC_TXDESC_DMA_CH5, + HALMAC_DMA_CH_6 = HALMAC_TXDESC_DMA_CH6, + HALMAC_DMA_CH_7 = HALMAC_TXDESC_DMA_CH7, + HALMAC_DMA_CH_8 = HALMAC_TXDESC_DMA_CH8, + HALMAC_DMA_CH_9 = HALMAC_TXDESC_DMA_CH9, + HALMAC_DMA_CH_10 = HALMAC_TXDESC_DMA_CH10, + HALMAC_DMA_CH_11 = HALMAC_TXDESC_DMA_CH11, + HALMAC_DMA_CH_S0 = HALMAC_TXDESC_DMA_CH12, + HALMAC_DMA_CH_S1 = HALMAC_TXDESC_DMA_CH13, + HALMAC_DMA_CH_MGQ = HALMAC_TXDESC_DMA_CH14, + HALMAC_DMA_CH_HIGH = HALMAC_TXDESC_DMA_CH15, + HALMAC_DMA_CH_FWCMD = HALMAC_TXDESC_DMA_CH16, + HALMAC_DMA_CH_MGQ_BAND1 = HALMAC_TXDESC_DMA_CH17, + HALMAC_DMA_CH_HIGH_BAND1 = HALMAC_TXDESC_DMA_CH18, + HALMAC_DMA_CH_BCN = HALMAC_TXDESC_DMA_CH19, + HALMAC_DMA_CH_H2C = HALMAC_TXDESC_DMA_CH20, + HALMAC_DMA_CH_MAX = HALMAC_TXDESC_DMA_CHMAX, + HALMAC_DMA_CH_UNDEFINE = 0x7F, +}; + +enum halmac_interface { HALMAC_INTERFACE_PCIE = 0x0, HALMAC_INTERFACE_USB = 0x1, HALMAC_INTERFACE_SDIO = 0x2, HALMAC_INTERFACE_AXI = 0x3, HALMAC_INTERFACE_UNDEFINE = 0x7F, -} HALMAC_INTERFACE; +}; -typedef enum _HALMAC_RX_AGG_MODE { +enum halmac_rx_agg_mode { HALMAC_RX_AGG_MODE_NONE = 0x0, HALMAC_RX_AGG_MODE_DMA = 0x1, HALMAC_RX_AGG_MODE_USB = 0x2, HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F, -} HALMAC_RX_AGG_MODE; -typedef struct _HALMAC_RXAGG_TH { +}; + +struct halmac_rxagg_th { u8 drv_define; u8 timeout; u8 size; -} HALMAC_RXAGG_TH, *PHALMAC_RXAGG_TH; - -typedef struct _HALMAC_RXAGG_CFG { - HALMAC_RX_AGG_MODE mode; - HALMAC_RXAGG_TH threshold; -} HALMAC_RXAGG_CFG, *PHALMAC_RXAGG_CFG; - - -typedef enum _HALMAC_MAC_POWER { - HALMAC_MAC_POWER_OFF = 0x0, - HALMAC_MAC_POWER_ON = 0x1, - HALMAC_MAC_POWER_UNDEFINE = 0x7F, -} HALMAC_MAC_POWER; - -typedef enum _HALMAC_PS_STATE { - HALMAC_PS_STATE_ACT = 0x0, - HALMAC_PS_STATE_LPS = 0x1, - HALMAC_PS_STATE_IPS = 0x2, - HALMAC_PS_STATE_UNDEFINE = 0x7F, -} HALMAC_PS_STATE; - -typedef enum _HALMAC_TRX_MODE { + u8 size_limit_en; +}; + +struct halmac_rxagg_cfg { + enum halmac_rx_agg_mode mode; + struct halmac_rxagg_th threshold; +}; + +struct halmac_api_registry { + u8 rx_exp_en:1; + u8 la_mode_en:1; + u8 cfg_drv_rsvd_pg_en:1; + u8 sdio_cmd53_4byte_en:1; + u8 rsvd:4; +}; + +enum halmac_trx_mode { HALMAC_TRX_MODE_NORMAL = 0x0, HALMAC_TRX_MODE_TRXSHARE = 0x1, HALMAC_TRX_MODE_WMM = 0x2, @@ -567,17 +736,17 @@ typedef enum _HALMAC_TRX_MODE { HALMAC_TRX_MODE_MAX = 0x6, HALMAC_TRX_MODE_WMM_LINUX = 0x7E, HALMAC_TRX_MODE_UNDEFINE = 0x7F, -} HALMAC_TRX_MODE; +}; -typedef enum _HALMAC_WIRELESS_MODE { +enum halmac_wireless_mode { HALMAC_WIRELESS_MODE_B = 0x0, HALMAC_WIRELESS_MODE_G = 0x1, HALMAC_WIRELESS_MODE_N = 0x2, HALMAC_WIRELESS_MODE_AC = 0x3, HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F, -} HALMAC_WIRELESS_MODE; +}; -typedef enum _HALMAC_BW { +enum halmac_bw { HALMAC_BW_20 = 0x00, HALMAC_BW_40 = 0x01, HALMAC_BW_80 = 0x02, @@ -586,91 +755,56 @@ typedef enum _HALMAC_BW { HALMAC_BW_10 = 0x05, HALMAC_BW_MAX = 0x06, HALMAC_BW_UNDEFINE = 0x7F, -} HALMAC_BW; - +}; -typedef enum _HALMAC_EFUSE_READ_CFG { +enum halmac_efuse_read_cfg { HALMAC_EFUSE_R_AUTO = 0x00, HALMAC_EFUSE_R_DRV = 0x01, HALMAC_EFUSE_R_FW = 0x02, HALMAC_EFUSE_R_UNDEFINE = 0x7F, -} HALMAC_EFUSE_READ_CFG; +}; -typedef enum _HALMAC_DLFW_MEM { +enum halmac_dlfw_mem { HALMAC_DLFW_MEM_EMEM = 0x00, + HALMAC_DLFW_MEM_EMEM_RSVD_PG = 0x01, HALMAC_DLFW_MEM_UNDEFINE = 0x7F, -} HALMAC_DLFW_MEM; - -typedef struct _HALMAC_TX_DESC { - u32 Dword0; - u32 Dword1; - u32 Dword2; - u32 Dword3; - u32 Dword4; - u32 Dword5; - u32 Dword6; - u32 Dword7; - u32 Dword8; - u32 Dword9; - u32 Dword10; - u32 Dword11; -} HALMAC_TX_DESC, *PHALMAC_TX_DESC; - -typedef struct _HALMAC_RX_DESC { - u32 Dword0; - u32 Dword1; - u32 Dword2; - u32 Dword3; - u32 Dword4; - u32 Dword5; -} HALMAC_RX_DESC, *PHALMAC_RX_DESC; - -typedef struct _HALMAC_FWLPS_OPTION { - u8 mode; - u8 clk_request; - u8 rlbm; - u8 smart_ps; - u8 awake_interval; - u8 all_queue_uapsd; - u8 pwr_state; - u8 low_pwr_rx_beacon; - u8 ant_auto_switch; - u8 ps_allow_bt_high_Priority; - u8 protect_bcn; - u8 silence_period; - u8 fast_bt_connect; - u8 two_antenna_en; - u8 adopt_user_Setting; - u8 drv_bcn_early_shift; - u8 enter_32K; -} HALMAC_FWLPS_OPTION, *PHALMAC_FWLPS_OPTION; - -typedef struct _HALMAC_FWIPS_OPTION { - u8 adopt_user_Setting; -} HALMAC_FWIPS_OPTION, *PHALMAC_FWIPS_OPTION; - -typedef struct _HALMAC_WOWLAN_OPTION { - u8 adopt_user_Setting; -} HALMAC_WOWLAN_OPTION, *PHALMAC_WOWLAN_OPTION; - -typedef struct _HALMAC_BCN_IE_INFO { - u8 func_en; - u8 size_th; - u8 timeout; - u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE]; -} HALMAC_BCN_IE_INFO, *PHALMAC_BCN_IE_INFO; - -typedef enum _HALMAC_REG_TYPE { - HALMAC_REG_TYPE_MAC = 0x0, - HALMAC_REG_TYPE_BB = 0x1, - HALMAC_REG_TYPE_RF = 0x2, - HALMAC_REG_TYPE_UNDEFINE = 0x7F, -} HALMAC_REG_TYPE; - -typedef enum _HALMAC_PARAMETER_CMD { - /* HALMAC_PARAMETER_CMD_LLT = 0x1, */ - /* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */ - /* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */ +}; + +struct halmac_tx_desc { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; + u32 dword6; + u32 dword7; + u32 dword8; + u32 dword9; + u32 dword10; + u32 dword11; +}; + +struct halmac_rx_desc { + u32 dword0; + u32 dword1; + u32 dword2; + u32 dword3; + u32 dword4; + u32 dword5; +}; + +struct halmac_bcn_ie_info { + u8 func_en; + u8 size_th; + u8 timeout; + u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE]; +}; + +enum halmac_parameter_cmd { + /* HALMAC_PARAMETER_CMD_LLT = 0x1, */ + /* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */ + /* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */ HALMAC_PARAMETER_CMD_MAC_W8 = 0x4, HALMAC_PARAMETER_CMD_MAC_W16 = 0x5, HALMAC_PARAMETER_CMD_MAC_W32 = 0x6, @@ -681,164 +815,159 @@ typedef enum _HALMAC_PARAMETER_CMD { HALMAC_PARAMETER_CMD_DELAY_US = 0X10, HALMAC_PARAMETER_CMD_DELAY_MS = 0X11, HALMAC_PARAMETER_CMD_END = 0XFF, -} HALMAC_PARAMETER_CMD; +}; -typedef union _HALMAC_PARAMETER_CONTENT { +union halmac_parameter_content { struct _MAC_REG_W { - u32 value; - u32 msk; - u16 offset; - u8 msk_en; + u32 value; + u32 msk; + u16 offset; + u8 msk_en; } MAC_REG_W; struct _BB_REG_W { - u32 value; - u32 msk; - u16 offset; - u8 msk_en; + u32 value; + u32 msk; + u16 offset; + u8 msk_en; } BB_REG_W; struct _RF_REG_W { - u32 value; - u32 msk; - u8 offset; - u8 msk_en; - u8 rf_path; + u32 value; + u32 msk; + u8 offset; + u8 msk_en; + u8 rf_path; } RF_REG_W; struct _DELAY_TIME { - u32 rsvd1; - u32 rsvd2; - u16 delay_time; - u8 rsvd3; + u32 rsvd1; + u32 rsvd2; + u16 delay_time; + u8 rsvd3; } DELAY_TIME; -} HALMAC_PARAMETER_CONTENT, *PHALMAC_PARAMETER_CONTENT; - -typedef struct _HALMAC_PHY_PARAMETER_INFO { - HALMAC_PARAMETER_CMD cmd_id; - HALMAC_PARAMETER_CONTENT content; -} HALMAC_PHY_PARAMETER_INFO, *PHALMAC_PHY_PARAMETER_INFO; - -typedef struct _HALMAC_H2C_INFO { - u16 h2c_seq_num; /* H2C sequence number */ - u8 in_use; /* 0 : empty 1 : used */ - HALMAC_H2C_RETURN_CODE status; -} HALMAC_H2C_INFO, *PHALMAC_H2C_INFO; - -typedef struct _HALMAC_PG_EFUSE_INFO { - u8 *pEfuse_map; - u32 efuse_map_size; - u8 *pEfuse_mask; +}; + +struct halmac_phy_parameter_info { + enum halmac_parameter_cmd cmd_id; + union halmac_parameter_content content; +}; + +struct halmac_pg_efuse_info { + u8 *efuse_map; + u32 efuse_map_size; + u8 *efuse_mask; u32 efuse_mask_size; -} HALMAC_PG_EFUSE_INFO, *PHALMAC_PG_EFUSE_INFO; - -typedef struct _HALMAC_TXAGG_BUFF_INFO { - u8 *pTx_agg_buf; - u8 *pCurr_pkt_buf; - u32 avai_buf_size; - u32 total_pkt_size; - u8 agg_num; -} HALMAC_TXAGG_BUFF_INFO, *PHALMAC_TXAGG_BUFF_INFO; - -typedef struct _HALMAC_CONFIG_PARA_INFO { - u32 para_buf_size; /* Parameter buffer size */ - u8 *pCfg_para_buf; /* Buffer for config parameter */ - u8 *pPara_buf_w; /* Write pointer of the parameter buffer */ - u32 para_num; /* Parameter numbers in parameter buffer */ - u32 avai_para_buf_size; /* Free size of parameter buffer */ - u32 offset_accumulation; - u32 value_accumulation; - HALMAC_DATA_TYPE data_type; /*DataType which is passed to FW*/ - u8 datapack_segment; /*DataPack Segment, from segment0...*/ - u8 full_fifo_mode; /* Used full tx fifo to save cfg parameter */ -} HALMAC_CONFIG_PARA_INFO, *PHALMAC_CONFIG_PARA_INFO; - -typedef struct _HALMAC_HW_CONFIG_INFO { - u32 efuse_size; /* Record efuse size */ - u32 eeprom_size; /* Record eeprom size */ - u32 bt_efuse_size; /* Record BT efuse size */ - u32 tx_fifo_size; /* Record tx fifo size */ - u32 rx_fifo_size; /* Record rx fifo size */ - u8 txdesc_size; /* Record tx desc size */ - u8 rxdesc_size; /* Record rx desc size */ - u32 page_size; /* Record page size */ +}; + +struct halmac_cfg_param_info { + u32 buf_size; + u8 *buf; + u8 *buf_wptr; + u32 num; + u32 avl_buf_size; + u32 offset_accum; + u32 value_accum; + enum halmac_data_type data_type; + u8 full_fifo_mode; +}; + +struct halmac_hw_cfg_info { + u32 efuse_size; + u32 eeprom_size; + u32 bt_efuse_size; + u32 tx_fifo_size; + u32 rx_fifo_size; + u32 rx_desc_fifo_size; + u32 page_size; u16 tx_align_size; - u8 page_size_2_power; - u8 cam_entry_num; /* Record CAM entry number */ -} HALMAC_HW_CONFIG_INFO, *PHALMAC_HW_CONFIG_INFO; - -typedef struct _HALMAC_SDIO_FREE_SPACE { - u16 high_queue_number; /* Free space of HIQ */ - u16 normal_queue_number; /* Free space of MIDQ */ - u16 low_queue_number; /* Free space of LOWQ */ - u16 public_queue_number; /* Free space of PUBQ */ - u16 extra_queue_number; /* Free space of EXBQ */ - u8 ac_oqt_number; - u8 non_ac_oqt_number; + u8 txdesc_size; + u8 rxdesc_size; + u8 cam_entry_num; + u8 chk_security_keyid; + u8 txdesc_ie_max_num; + u8 txdesc_body_size; + u8 ac_oqt_size; + u8 non_ac_oqt_size; + u8 acq_num; + u8 trx_mode; + u8 usb_txagg_num; +}; + +struct halmac_sdio_free_space { + u16 hiq_pg_num; + u16 miq_pg_num; + u16 lowq_pg_num; + u16 pubq_pg_num; + u16 exq_pg_num; + u8 ac_oqt_num; + u8 non_ac_oqt_num; u8 ac_empty; -} HALMAC_SDIO_FREE_SPACE, *PHALMAC_SDIO_FREE_SPACE; + u8 *macid_map; + u32 macid_map_size; +}; -typedef enum _HAL_FIFO_SEL { +enum hal_fifo_sel { HAL_FIFO_SEL_TX, HAL_FIFO_SEL_RX, HAL_FIFO_SEL_RSVD_PAGE, HAL_FIFO_SEL_REPORT, HAL_FIFO_SEL_LLT, -} HAL_FIFO_SEL; - -typedef enum _HALMAC_DRV_INFO { - HALMAC_DRV_INFO_NONE, /* No information is appended in rx_pkt */ - HALMAC_DRV_INFO_PHY_STATUS, /* PHY status is appended after rx_desc */ - HALMAC_DRV_INFO_PHY_SNIFFER, /* PHY status and sniffer info are appended after rx_desc */ - HALMAC_DRV_INFO_PHY_PLCP, /* PHY status and plcp header are appended after rx_desc */ + HAL_FIFO_SEL_RXBUF_FW, + HAL_FIFO_SEL_RXBUF_PHY, + HAL_FIFO_SEL_RXDESC, + HAL_BUF_SECURITY_CAM, + HAL_BUF_WOW_CAM, + HAL_BUF_RX_FILTER_CAM, + HAL_BUF_BA_CAM, + HAL_BUF_MBSSID_CAM +}; + +enum halmac_drv_info { + /* No information is appended in rx_pkt */ + HALMAC_DRV_INFO_NONE, + /* PHY status is appended after rx_desc */ + HALMAC_DRV_INFO_PHY_STATUS, + /* PHY status and sniffer info are appended after rx_desc */ + HALMAC_DRV_INFO_PHY_SNIFFER, + /* PHY status and plcp header are appended after rx_desc */ + HALMAC_DRV_INFO_PHY_PLCP, HALMAC_DRV_INFO_UNDEFINE, -} HALMAC_DRV_INFO; - -typedef struct _HALMAC_BT_COEX_CMD { - u8 element_id; - u8 op_code; - u8 op_code_ver; - u8 req_num; - u8 data0; - u8 data1; - u8 data2; - u8 data3; - u8 data4; -} HALMAC_BT_COEX_CMD, *PHALMAC_BT_COEX_CMD; - -typedef enum _HALMAC_PRI_CH_IDX { +}; + +enum halmac_pri_ch_idx { HALMAC_CH_IDX_UNDEFINE = 0, HALMAC_CH_IDX_1 = 1, HALMAC_CH_IDX_2 = 2, HALMAC_CH_IDX_3 = 3, HALMAC_CH_IDX_4 = 4, HALMAC_CH_IDX_MAX = 5, -} HALMAC_PRI_CH_IDX; +}; -typedef struct _HALMAC_CH_INFO { - HALMAC_CS_ACTION_ID action_id; - HALMAC_BW bw; - HALMAC_PRI_CH_IDX pri_ch_idx; +struct halmac_ch_info { + enum halmac_cs_action_id action_id; + enum halmac_bw bw; + enum halmac_pri_ch_idx pri_ch_idx; u8 channel; u8 timeout; u8 extra_info; -} HALMAC_CH_INFO, *PHALMAC_CH_INFO; +}; -typedef struct _HALMAC_CH_EXTRA_INFO { +struct halmac_ch_extra_info { u8 extra_info; - HALMAC_CS_EXTRA_ACTION_ID extra_action_id; + enum halmac_cs_extra_action_id extra_action_id; u8 extra_info_size; u8 *extra_info_data; -} HALMAC_CH_EXTRA_INFO, *PHALMAC_CH_EXTRA_INFO; +}; -typedef enum _HALMAC_CS_PERIODIC_OPTION { +enum halmac_cs_periodic_option { HALMAC_CS_PERIODIC_NONE, HALMAC_CS_PERIODIC_NORMAL, HALMAC_CS_PERIODIC_2_PHASE, HALMAC_CS_PERIODIC_SEAMLESS, -} HALMAC_CS_PERIODIC_OPTION; +}; -typedef struct _HALMAC_CH_SWITCH_OPTION { - HALMAC_BW dest_bw; - HALMAC_CS_PERIODIC_OPTION periodic_option; - HALMAC_PRI_CH_IDX dest_pri_ch_idx; +struct halmac_ch_switch_option { + enum halmac_bw dest_bw; + enum halmac_cs_periodic_option periodic_option; + enum halmac_pri_ch_idx dest_pri_ch_idx; /* u32 tsf_high; */ u32 tsf_low; u8 switch_en; @@ -846,27 +975,51 @@ typedef struct _HALMAC_CH_SWITCH_OPTION { u8 absolute_time_en; u8 dest_ch; u8 normal_period; + u8 normal_period_sel; u8 normal_cycle; u8 phase_2_period; -} HALMAC_CH_SWITCH_OPTION, *PHALMAC_CH_SWITCH_OPTION; + u8 phase_2_period_sel; +}; + +struct halmac_p2pps { + u8 offload_en:1; + u8 role:1; + u8 ctwindow_en:1; + u8 noa_en:1; + u8 noa_sel:1; + u8 all_sta_sleep:1; + u8 discovery:1; + u8 disable_close_rf:1; + u8 p2p_port_id; + u8 p2p_group; + u8 p2p_macid; + u8 ctwindow_length; + u8 rsvd3; + u8 rsvd4; + u8 rsvd5; + u32 noa_duration_para; + u32 noa_interval_para; + u32 noa_start_time_para; + u32 noa_count_para; +}; -typedef struct _HALMAC_FW_BUILD_TIME { +struct halmac_fw_build_time { u16 year; u8 month; u8 date; u8 hour; u8 min; -} HALMAC_FW_BUILD_TIME, *PHALMAC_FW_BUILD_TIME; +}; -typedef struct _HALMAC_FW_VERSION { +struct halmac_fw_version { u16 version; u8 sub_version; u8 sub_index; u16 h2c_version; - HALMAC_FW_BUILD_TIME build_time; -} HALMAC_FW_VERSION, *PHALMAC_FW_VERSION; + struct halmac_fw_build_time build_time; +}; -typedef enum _HALMAC_RF_TYPE { +enum halmac_rf_type { HALMAC_RF_1T2R = 0, HALMAC_RF_2T4R = 1, HALMAC_RF_2T2R = 2, @@ -877,43 +1030,35 @@ typedef enum _HALMAC_RF_TYPE { HALMAC_RF_3T4R = 7, HALMAC_RF_4T4R = 8, HALMAC_RF_MAX_TYPE = 0xF, -} HALMAC_RF_TYPE; +}; -typedef struct _HALMAC_GENERAL_INFO { +struct halmac_general_info { u8 rfe_type; - HALMAC_RF_TYPE rf_type; -} HALMAC_GENERAL_INFO, *PHALMAC_GENERAL_INFO; + enum halmac_rf_type rf_type; + u8 tx_ant_status; + u8 rx_ant_status; +}; -typedef struct _HALMAC_PWR_TRACKING_PARA { +struct halmac_pwr_tracking_para { u8 enable; u8 tx_pwr_index; u8 pwr_tracking_offset_value; u8 tssi_value; -} HALMAC_PWR_TRACKING_PARA, *PHALMAC_PWR_TRACKING_PARA; +}; -typedef struct _HALMAC_PWR_TRACKING_OPTION { +struct halmac_pwr_tracking_option { u8 type; u8 bbswing_index; - HALMAC_PWR_TRACKING_PARA pwr_tracking_para[4]; /* pathA, pathB, pathC, pathD */ -} HALMAC_PWR_TRACKING_OPTION, *PHALMAC_PWR_TRACKING_OPTION; - -typedef struct _HALMAC_NLO_CFG { - u8 num_of_ssid; - u8 num_of_hidden_ap; - u8 rsvd[2]; - u32 pattern_check; - u32 rsvd1; - u32 rsvd2; - u8 ssid_len[HALMAC_SUPPORT_NLO_NUM]; - u8 ChiperType[HALMAC_SUPPORT_NLO_NUM]; - u8 rsvd3[HALMAC_SUPPORT_NLO_NUM]; - u8 loc_probeReq[HALMAC_SUPPORT_PROBE_REQ_NUM]; - u8 rsvd4[56]; - u8 ssid[HALMAC_SUPPORT_NLO_NUM][HALMAC_MAX_SSID_LEN]; -} HALMAC_NLO_CFG, *PHALMAC_NLO_CFG; - - -typedef enum _HALMAC_DATA_RATE { + /* pathA, pathB, pathC, pathD */ + struct halmac_pwr_tracking_para pwr_tracking_para[4]; +}; + +struct halmac_fast_edca_cfg { + enum halmac_acq_id acq_id; + u8 queue_to; /* unit : 32us*/ +}; + +enum halmac_data_rate { HALMAC_CCK1, HALMAC_CCK2, HALMAC_CCK5_5, @@ -997,24 +1142,22 @@ typedef enum _HALMAC_DATA_RATE { HALMAC_VHT_NSS4_MCS6, HALMAC_VHT_NSS4_MCS7, HALMAC_VHT_NSS4_MCS8, - HALMAC_VHT_NSS4_MCS9 -} HALMAC_DATA_RATE; - -typedef enum _HALMAC_RF_PATH { + HALMAC_VHT_NSS4_MCS9, + /*FPGA only*/ + HALMAC_VHT_NSS5_MCS0, + HALMAC_VHT_NSS6_MCS0, + HALMAC_VHT_NSS7_MCS0, + HALMAC_VHT_NSS8_MCS0 +}; + +enum halmac_rf_path { HALMAC_RF_PATH_A, HALMAC_RF_PATH_B, HALMAC_RF_PATH_C, HALMAC_RF_PATH_D -} HALMAC_RF_PATH; +}; -typedef enum _HALMAC_SND_PKT_SEL { - HALMAC_UNI_NDPA, - HALMAC_BMC_NDPA, - HALMAC_NON_FINAL_BFRPRPOLL, - HALMAC_FINAL_BFRPTPOLL, -} HALMAC_SND_PKT_SEL; - -typedef enum _HAL_SECURITY_TYPE { +enum hal_security_type { HAL_SECURITY_TYPE_NONE = 0, HAL_SECURITY_TYPE_WEP40 = 1, HAL_SECURITY_TYPE_WEP104 = 2, @@ -1027,174 +1170,32 @@ typedef enum _HAL_SECURITY_TYPE { HAL_SECURITY_TYPE_GCMSMS4 = 9, HAL_SECURITY_TYPE_BIP = 10, HAL_SECURITY_TYPE_UNDEFINE = 0x7F, -} HAL_SECURITY_TYPE; +}; -typedef enum _HAL_INTF_PHY { +enum hal_intf_phy { HAL_INTF_PHY_USB2 = 0, HAL_INTF_PHY_USB3 = 1, HAL_INTF_PHY_PCIE_GEN1 = 2, HAL_INTF_PHY_PCIE_GEN2 = 3, HAL_INTF_PHY_UNDEFINE = 0x7F, -} HAL_INTF_PHY; +}; -#if HALMAC_PLATFORM_TESTPROGRAM +struct halmac_cut_amsdu_cfg { + u8 cut_amsdu_en; + u8 chk_len_en; + u8 chk_len_def_val; + u8 chk_len_l_th; + u16 chk_len_h_th; +}; -typedef enum _HALMAC_PWR_SEQ_ID { - HALMAC_PWR_SEQ_ENABLE, - HALMAC_PWR_SEQ_DISABLE, - HALMAC_PWR_SEQ_ENTER_LPS, - HALMAC_PWR_SEQ_ENTER_DEEP_LPS, - HALMAC_PWR_SEQ_LEAVE_LPS, - HALMAC_PWR_SEQ_MAX -} HALMAC_PWR_SEQ_ID; - -typedef enum _HAL_TX_ID { - HAL_TX_ID_VO, - HAL_TX_ID_VI, - HAL_TX_ID_BE, - HAL_TX_ID_BK, - HAL_TX_ID_BCN, - HAL_TX_ID_H2C, - HAL_TX_ID_MAX -} HAL_TX_ID; - -typedef enum _HAL_QSEL { - HAL_QSEL_TID0, - HAL_QSEL_TID1, - HAL_QSEL_TID2, - HAL_QSEL_TID3, - HAL_QSEL_TID4, - HAL_QSEL_TID5, - HAL_QSEL_TID6, - HAL_QSEL_TID7, - - HAL_QSEL_BEACON = 0x10, - HAL_QSEL_HIGH = 0x11, - HAL_QSEL_MGT = 0x12, - HAL_QSEL_CMD = 0x13 -} HAL_QSEL; - -typedef enum _HAL_RTS_MODE { - HAL_RTS_MODE_NONE, - HAL_RTS_MODE_CTS2SELF, - HAL_RTS_MODE_RTS, -} HAL_RTS_MODE; - -typedef enum _HAL_DATA_BW { - HAL_DATA_BW_20M, - HAL_DATA_BW_40M, - HAL_DATA_BW_80M, - HAL_DATA_BW_160M, -} HAL_DATA_BW; - -typedef enum _HAL_RTS_SHORT { - HAL_RTS_SHORT_SHORT, - HAL_RTS_SHORT_LONG, -} HAL_RTS_SHORT; - -typedef enum _HAL_SECURITY_METHOD { - HAL_SECURITY_METHOD_HW = 0, - HAL_SECURITY_METHOD_SW = 1, - HAL_SECURITY_METHOD_UNDEFINE = 0x7F, -} HAL_SECURITY_METHOD; - -typedef struct _HAL_TXDESC_INFO { - u32 txdesc_length; - u32 packet_size; /* payload + wlheader */ - HAL_TX_ID tx_id; - HALMAC_DATA_RATE data_rate; - HAL_RTS_MODE rts_mode; - HAL_DATA_BW data_bw; - HAL_RTS_SHORT rts_short; - HAL_SECURITY_TYPE security_type; - HAL_SECURITY_METHOD encryption_method; - u16 seq_num; - u8 retry_limit_en; - u8 retry_limit_number; - u8 rts_threshold; - u8 qos; - u8 ht; - u8 ampdu; - u8 early_mode; - u8 bm_cast; - u8 data_short; - u8 mac_id; -} HAL_TXDESC_INFO, *PHAL_TXDESC_INFO; - -typedef struct _HAL_RXDESC_INFO { - u8 c2h; - u8 *pWifi_pkt; - u32 packet_size; - u8 crc_err; - u8 icv_err; -} HAL_RXDESC_INFO, *PHAL_RXDESC_INFO; - -typedef struct _HAL_TXDESC_PARSER { - u8 txdesc_len; - u16 txpkt_size; -} HAL_TXDESC_PARSER, *PHAL_TXDESC_PARSER; - -typedef struct _HAL_RXDESC_PARSER { - u32 driver_info_size; - u16 rxpkt_size; - u8 rxdesc_len; - u8 c2h; - u8 crc_err; - u8 icv_err; -} HAL_RXDESC_PARSER, *PHAL_RXDESC_PARSER; - -typedef struct _HAL_RF_REG_INFO { - HALMAC_RF_PATH rf_path; - u32 offset; - u32 bit_mask; - u32 data; -} HAL_RF_REG_INFO, *PHAL_RF_REG_INFO; - -typedef struct _HALMAC_SDIO_HIMR_INFO { - u8 rx_request; - u8 aval_msk; -} HALMAC_SDIO_HIMR_INFO, *PHALMAC_SDIO_HIMR_INFO; - -typedef struct _HALMAC_BEACON_INFO { -} HALMAC_BEACON_INFO, *PHALMAC_BEACON_INFO; - -typedef struct _HALMAC_MGNT_INFO { - u8 mu_enable; - u8 bip; - u8 unicast; - u32 packet_size; -} HALMAC_MGNT_INFO, *PHALMAC_MGNT_INFO; - -typedef struct _HALMAC_CTRL_INFO { - u8 snd_enable; - HALMAC_SND_PKT_SEL snd_pkt_sel; /* 0:unicast ndpa 1:broadcast ndpa 3:non-final BF Rpt Poll 4:final BF Rpt Poll */ - u8 *pPacket_desc; - u32 desc_size; - u16 seq_num; - u8 bw; - u16 paid; -} HALMAC_CTRL_INFO, *PHALMAC_CTRL_INFO; - -typedef struct _HALMAC_HIGH_QUEUE_INFO { - u8 *pPacket_desc; - u32 desc_size; -} HALMAC_HIGH_QUEUE_INFO, *PHALMAC_HIGH_QUEUE_INFO; - -typedef struct _HALMAC_CHIP_TYPE { - HALMAC_CHIP_ID chip_id; - HALMAC_CHIP_VER chip_version; -} HALMAC_CHIP_TYPE, *PHALMAC_CHIP_TYPE; - -#endif /* End of test program */ - -typedef enum _HALMAC_DBG_MSG_INFO { +enum halmac_dbg_msg_info { HALMAC_DBG_ALWAYS, HALMAC_DBG_ERR, HALMAC_DBG_WARN, HALMAC_DBG_TRACE, -} HALMAC_DBG_MSG_INFO; +}; -typedef enum _HALMAC_DBG_MSG_TYPE { +enum halmac_dbg_msg_type { HALMAC_MSG_INIT, HALMAC_MSG_EFUSE, HALMAC_MSG_FW, @@ -1204,19 +1205,10 @@ typedef enum _HALMAC_DBG_MSG_TYPE { HALMAC_MSG_COMMON, HALMAC_MSG_DBI, HALMAC_MSG_MDIO, - HALMAC_MSG_USB -} HALMAC_DBG_MSG_TYPE; - -typedef enum _HALMAC_CMD_PROCESS_STATUS { - HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */ - HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */ - HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */ - HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */ - HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */ - HALMAC_CMD_PROCESS_UNDEFINE = 0x7F, -} HALMAC_CMD_PROCESS_STATUS; - -typedef enum _HALMAC_FEATURE_ID { + HALMAC_MSG_USB, +}; + +enum halmac_feature_id { HALMAC_FEATURE_CFG_PARA, /* Support */ HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, /* Support */ HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, /* Support */ @@ -1227,332 +1219,186 @@ typedef enum _HALMAC_FEATURE_ID { HALMAC_FEATURE_IQK, /* Support */ HALMAC_FEATURE_POWER_TRACKING, /* Support */ HALMAC_FEATURE_PSD, /* Support */ + HALMAC_FEATURE_FW_SNDING, /* Support */ HALMAC_FEATURE_ALL, /* Support, only for reset */ -} HALMAC_FEATURE_ID; +}; -typedef enum _HALMAC_DRV_RSVD_PG_NUM { +enum halmac_drv_rsvd_pg_num { + HALMAC_RSVD_PG_NUM8, /* 1K */ HALMAC_RSVD_PG_NUM16, /* 2K */ HALMAC_RSVD_PG_NUM24, /* 3K */ HALMAC_RSVD_PG_NUM32, /* 4K */ -} HALMAC_DRV_RSVD_PG_NUM; + HALMAC_RSVD_PG_NUM64, /* 8K */ + HALMAC_RSVD_PG_NUM128, /* 16K */ +}; -typedef enum _HALMAC_PCIE_CFG { +enum halmac_pcie_cfg { HALMAC_PCIE_GEN1, HALMAC_PCIE_GEN2, HALMAC_PCIE_CFG_UNDEFINE, -} HALMAC_PCIE_CFG; +}; -typedef enum _HALMAC_PORTID { +enum halmac_portid { HALMAC_PORTID0 = 0, HALMAC_PORTID1 = 1, HALMAC_PORTID2 = 2, HALMAC_PORTID3 = 3, HALMAC_PORTID4 = 4, - HALMAC_PORTIDMAX -} HALMAC_PORTID; - -typedef struct _HALMAC_P2PPS { - /*DW0*/ - u8 offload_en:1; - u8 role:1; - u8 ctwindow_en:1; - u8 noa_en:1; - u8 noa_sel:1; - u8 all_sta_sleep:1; - u8 discovery:1; - u8 rsvd2:1; - u8 p2p_port_id; - u8 p2p_group; - u8 p2p_macid; - - /*DW1*/ - u8 ctwindow_length; - u8 rsvd3; - u8 rsvd4; - u8 rsvd5; - - /*DW2*/ - u32 noa_duration_para; - - /*DW3*/ - u32 noa_interval_para; - - /*DW4*/ - u32 noa_start_time_para; - - /*DW5*/ - u32 noa_count_para; -} HALMAC_P2PPS, *PHALMAC_P2PPS; - - -/* Platform API setting */ -typedef struct _HALMAC_PLATFORM_API { - /* R/W register */ - u8 (*SDIO_CMD52_READ)(VOID *pDriver_adapter, u32 offset); - u8 (*SDIO_CMD53_READ_8)(VOID *pDriver_adapter, u32 offset); - u16 (*SDIO_CMD53_READ_16)(VOID *pDriver_adapter, u32 offset); - u32 (*SDIO_CMD53_READ_32)(VOID *pDriver_adapter, u32 offset); - u8 (*SDIO_CMD53_READ_N)(VOID *pDriver_adapter, u32 offset, u32 size, u8 *data); - VOID (*SDIO_CMD52_WRITE)(VOID *pDriver_adapter, u32 offset, u8 value); - VOID (*SDIO_CMD53_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value); - VOID (*SDIO_CMD53_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value); - VOID (*SDIO_CMD53_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value); - u8 (*REG_READ_8)(VOID *pDriver_adapter, u32 offset); - u16 (*REG_READ_16)(VOID *pDriver_adapter, u32 offset); - u32 (*REG_READ_32)(VOID *pDriver_adapter, u32 offset); - VOID (*REG_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value); - VOID (*REG_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value); - VOID (*REG_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value); - - /* send pBuf to reserved page, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = bcn */ - u8 (*SEND_RSVD_PAGE)(VOID *pDriver_adapter, u8 *pBuf, u32 size); - /* send pBuf to h2c queue, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = h2c */ - u8 (*SEND_H2C_PKT)(VOID *pDriver_adapter, u8 *pBuf, u32 size); - - u8 (*RTL_FREE)(VOID *pDriver_adapter, VOID *pBuf, u32 size); - VOID* (*RTL_MALLOC)(VOID *pDriver_adapter, u32 size); - u8 (*RTL_MEMCPY)(VOID *pDriver_adapter, VOID *dest, VOID *src, u32 size); - u8 (*RTL_MEMSET)(VOID *pDriver_adapter, VOID *pAddress, u8 value, u32 size); - VOID (*RTL_DELAY_US)(VOID *pDriver_adapter, u32 us); - - u8 (*MUTEX_INIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); - u8 (*MUTEX_DEINIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); - u8 (*MUTEX_LOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); - u8 (*MUTEX_UNLOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); - - u8 (*MSG_PRINT)(VOID *pDriver_adapter, u32 msg_type, u8 msg_level, s8 *fmt, ...); - u8 (*BUFF_PRINT)(VOID *pDriver_adapter, u32 msg_type, u8 msg_level, s8 *buf, u32 size); - - u8 (*EVENT_INDICATION)(VOID *pDriver_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size); - -#if HALMAC_PLATFORM_TESTPROGRAM - VOID* (*PCI_ALLOC_COMM_BUFF)(VOID *pDriver_adapter, u32 size, u32 *physical_addr, u8 cache_en); - VOID (*PCI_FREE_COMM_BUFF)(VOID *pDriver_adapter, u32 size, u32 physical_addr, VOID *virtual_addr, u8 cache_en); - u8 (*WRITE_DATA_SDIO_ADDR)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u32 addr); - u8 (*WRITE_DATA_USB_BULKOUT_ID)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u8 bulkout_id); - u8 (*WRITE_DATA_PCIE_QUEUE)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u8 queue); - u8 (*READ_DATA)(VOID *pDriver_adapter, u8 *pBuf, u32 *read_length); -#endif -} HALMAC_PLATFORM_API, *PHALMAC_PLATFORM_API; - -/*1->Little endian 0->Big endian*/ -#if HALMAC_SYSTEM_ENDIAN - -#else - -#endif - -/* User can not use members in Address_L_H, use Address[6] is mandatory */ -typedef union _HALMAC_WLAN_ADDR { - u8 Address[6]; /* WLAN address (MACID, BSSID, Brodcast ID). Address[0] is lowest, Address[5] is highest*/ + HALMAC_PORTID_NUM = 5, +}; + +struct halmac_bcn_ctrl { + u8 dis_rx_bssid_fit; + u8 en_txbcn_rpt; + u8 dis_tsf_udt; + u8 en_bcn; + u8 en_rxbcn_rpt; + u8 en_p2p_ctwin; + u8 en_p2p_bcn_area; +}; + +/* User only can use Address[6]*/ +/* Address[0] is lowest, Address[5] is highest */ +union halmac_wlan_addr { + u8 addr[6]; struct { union { - u32 Address_Low; - u8 Address_Low_B[4]; + __le32 low; + u8 low_byte[4]; }; union { - u16 Address_High; - u8 Address_High_B[2]; + __le16 high; + u8 high_byte[2]; }; - } Address_L_H; -} HALMAC_WLAN_ADDR, *PHALMAC_WLAN_ADDR; + } addr_l_h; +}; -typedef enum _HALMAC_SND_ROLE { +struct halmac_platform_api { + /* R/W register */ + u8 (*SDIO_CMD52_READ)(void *drv_adapter, u32 offset); + u8 (*SDIO_CMD53_READ_8)(void *drv_adapter, u32 offset); + u16 (*SDIO_CMD53_READ_16)(void *drv_adapter, u32 offset); + u32 (*SDIO_CMD53_READ_32)(void *drv_adapter, u32 offset); + u8 (*SDIO_CMD53_READ_N)(void *drv_adapter, u32 offset, u32 size, + u8 *data); + void (*SDIO_CMD52_WRITE)(void *drv_adapter, u32 offset, u8 value); + void (*SDIO_CMD53_WRITE_8)(void *drv_adapter, u32 offset, u8 value); + void (*SDIO_CMD53_WRITE_16)(void *drv_adapter, u32 offset, u16 value); + void (*SDIO_CMD53_WRITE_32)(void *drv_adapter, u32 offset, u32 value); + u8 (*REG_READ_8)(void *drv_adapter, u32 offset); + u16 (*REG_READ_16)(void *drv_adapter, u32 offset); + u32 (*REG_READ_32)(void *drv_adapter, u32 offset); + void (*REG_WRITE_8)(void *drv_adapter, u32 offset, u8 value); + void (*REG_WRITE_16)(void *drv_adapter, u32 offset, u16 value); + void (*REG_WRITE_32)(void *drv_adapter, u32 offset, u32 value); + u8 (*SDIO_CMD52_CIA_READ)(void *drv_adapter, u32 offset); + + /* send pBuf to reserved page, the tx_desc is not included in pBuf */ + /* driver need to fill tx_desc with qsel = bcn */ + u8 (*SEND_RSVD_PAGE)(void *drv_adapter, u8 *buf, u32 size); + /* send pBuf to h2c queue, the tx_desc is not included in pBuf */ + /* driver need to fill tx_desc with qsel = h2c */ + u8 (*SEND_H2C_PKT)(void *drv_adapter, u8 *buf, u32 size); + + u8 (*RTL_FREE)(void *drv_adapter, void *buf, u32 size); + void* (*RTL_MALLOC)(void *drv_adapter, u32 size); + u8 (*RTL_MEMCPY)(void *drv_adapter, void *dest, void *src, u32 size); + u8 (*RTL_MEMSET)(void *drv_adapter, void *addr, u8 value, u32 size); + void (*RTL_DELAY_US)(void *drv_adapter, u32 us); + + u8 (*MUTEX_INIT)(void *drv_adapter, HALMAC_MUTEX *mutex); + u8 (*MUTEX_DEINIT)(void *drv_adapter, HALMAC_MUTEX *mutex); + u8 (*MUTEX_LOCK)(void *drv_adapter, HALMAC_MUTEX *mutex); + u8 (*MUTEX_UNLOCK)(void *drv_adapter, HALMAC_MUTEX *mutex); + + u8 (*MSG_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level, + s8 *fmt, ...); + u8 (*BUFF_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level, s8 *buf, + u32 size); + + u8 (*EVENT_INDICATION)(void *drv_adapter, + enum halmac_feature_id feature_id, + enum halmac_cmd_process_status process_status, + u8 *buf, u32 size); + +#if HALMAC_PLATFORM_TESTPROGRAM + struct halmisc_platform_api *halmisc_pltfm_api; +#endif +}; + +enum halmac_snd_role { HAL_BFER = 0, HAL_BFEE = 1, -} HALMAC_SND_ROLE; +}; -typedef enum _HALMAC_CSI_SEG_LEN { +enum halmac_csi_seg_len { HAL_CSI_SEG_4K = 0, HAL_CSI_SEG_8K = 1, HAL_CSI_SEG_11K = 2, -} HALMAC_CSI_SEG_LEN; +}; -typedef struct _HALMAC_CFG_MUMIMO_PARA { - HALMAC_SND_ROLE role; +struct halmac_cfg_mumimo_para { + enum halmac_snd_role role; u8 sounding_sts[6]; u16 grouping_bitmap; u8 mu_tx_en; u32 given_gid_tab[2]; u32 given_user_pos[4]; -} HALMAC_CFG_MUMIMO_PARA, *PHALMAC_CFG_MUMIMO_PARA; +}; -typedef struct _HALMAC_SU_BFER_INIT_PARA { +struct halmac_su_bfer_init_para { u8 userid; u16 paid; u16 csi_para; - HALMAC_WLAN_ADDR bfer_address; -} HALMAC_SU_BFER_INIT_PARA, *PHALMAC_SU_BFER_INIT_PARA; + union halmac_wlan_addr bfer_address; +}; -typedef struct _HALMAC_MU_BFEE_INIT_PARA { +struct halmac_mu_bfee_init_para { u8 userid; u16 paid; - u32 user_position_l; - u32 user_position_h; -} HALMAC_MU_BFEE_INIT_PARA, *PHALMAC_MU_BFEE_INIT_PARA; + u32 user_position_l; /*for gid 0~15*/ + u32 user_position_h; /*for gid 16~31*/ + u32 user_position_l_1; /*for gid 32~47*/ + u32 user_position_h_1; /*for gid 48~63*/ +}; -typedef struct _HALMAC_MU_BFER_INIT_PARA { +struct halmac_mu_bfer_init_para { u16 paid; u16 csi_para; u16 my_aid; - HALMAC_CSI_SEG_LEN csi_length_sel; - HALMAC_WLAN_ADDR bfer_address; -} HALMAC_MU_BFER_INIT_PARA, *PHALMAC_MU_BFER_INIT_PARA; + enum halmac_csi_seg_len csi_length_sel; + union halmac_wlan_addr bfer_address; +}; -typedef struct _HALMAC_SND_INFO { - u16 paid; - u8 userid; - HALMAC_DATA_RATE ndpa_rate; - u16 csi_para; - u16 my_aid; - HALMAC_DATA_RATE csi_rate; - HALMAC_CSI_SEG_LEN csi_length_sel; - HALMAC_SND_ROLE role; - HALMAC_WLAN_ADDR bfer_address; - HALMAC_BW bw; - u8 txbf_en; - PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init; - PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init; - PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init; -} HALMAC_SND_INFO, *PHALMAC_SND_INFO; - -typedef struct _HALMAC_CS_INFO { - u8 *ch_info_buf; - u8 *ch_info_buf_w; +struct halmac_ch_sw_info { + u8 *buf; + u8 *buf_wptr; u8 extra_info_en; - u32 buf_size; /* buffer size */ - u32 avai_buf_size; /* buffer size */ - u32 total_size; - u32 accu_timeout; - u32 ch_num; -} HALMAC_CS_INFO, *PHALMAC_CS_INFO; - -typedef struct _HALMAC_RESTORE_INFO { - u32 mac_register; - u32 value; - u8 length; -} HALMAC_RESTORE_INFO, *PHALMAC_RESTORE_INFO; - -typedef struct _HALMAC_EVENT_TRIGGER { - u32 physical_efuse_map : 1; - u32 logical_efuse_map : 1; - u32 rsvd1 : 28; -} HALMAC_EVENT_TRIGGER, *PHALMAC_EVENT_TRIGGER; - -typedef struct _HALMAC_H2C_HEADER_INFO { - u16 sub_cmd_id; - u16 content_size; + u32 buf_size; + u32 avl_buf_size; + u32 total_size; + u32 ch_num; +}; + +struct halmac_event_trigger { + u32 phy_efuse_map : 1; + u32 log_efuse_map : 1; + u32 rsvd1 : 28; +}; + +struct halmac_h2c_header_info { + u16 sub_cmd_id; + u16 content_size; u8 ack; -} HALMAC_H2C_HEADER_INFO, *PHALMAC_H2C_HEADER_INFO; - -typedef enum _HALMAC_DLFW_STATE { - HALMAC_DLFW_NONE = 0, - HALMAC_DLFW_DONE = 1, - HALMAC_GEN_INFO_SENT = 2, - HALMAC_DLFW_UNDEFINED = 0x7F, -} HALMAC_DLFW_STATE; - -typedef enum _HALMAC_EFUSE_CMD_CONSTRUCT_STATE { - HALMAC_EFUSE_CMD_CONSTRUCT_IDLE = 0, - HALMAC_EFUSE_CMD_CONSTRUCT_BUSY = 1, - HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT = 2, - HALMAC_EFUSE_CMD_CONSTRUCT_STATE_NUM = 3, - HALMAC_EFUSE_CMD_CONSTRUCT_UNDEFINED = 0x7F, -} HALMAC_EFUSE_CMD_CONSTRUCT_STATE; - -typedef enum _HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE { - HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE = 0, - HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING = 1, - HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT = 2, - HALMAC_CFG_PARA_CMD_CONSTRUCT_NUM = 3, - HALMAC_CFG_PARA_CMD_CONSTRUCT_UNDEFINED = 0x7F, -} HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE; - -typedef enum _HALMAC_SCAN_CMD_CONSTRUCT_STATE { - HALMAC_SCAN_CMD_CONSTRUCT_IDLE = 0, - HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED = 1, - HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING = 2, - HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT = 3, - HALMAC_SCAN_CMD_CONSTRUCT_STATE_NUM = 4, - HALMAC_SCAN_CMD_CONSTRUCT_UNDEFINED = 0x7F, -} HALMAC_SCAN_CMD_CONSTRUCT_STATE; - -typedef enum _HALMAC_API_STATE { - HALMAC_API_STATE_INIT = 0, - HALMAC_API_STATE_HALT = 1, - HALMAC_API_STATE_UNDEFINED = 0x7F, -} HALMAC_API_STATE; - -typedef struct _HALMAC_EFUSE_STATE_SET { - HALMAC_EFUSE_CMD_CONSTRUCT_STATE efuse_cmd_construct_state; - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_EFUSE_STATE_SET, *PHALMAC_EFUSE_STATE_SET; - -typedef struct _HALMAC_CFG_PARA_STATE_SET { - HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE cfg_para_cmd_construct_state; - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_CFG_PARA_STATE_SET, *PHALMAC_CFG_PARA_STATE_SET; - -typedef struct _HALMAC_SCAN_STATE_SET { - HALMAC_SCAN_CMD_CONSTRUCT_STATE scan_cmd_construct_state; - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_SCAN_STATE_SET, *PHALMAC_SCAN_STATE_SET; - -typedef struct _HALMAC_UPDATE_PACKET_STATE_SET { - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_UPDATE_PACKET_STATE_SET, *PHALMAC_UPDATE_PACKET_STATE_SET; - -typedef struct _HALMAC_IQK_STATE_SET { - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_IQK_STATE_SET, *PHALMAC_IQK_STATE_SET; - -typedef struct _HALMAC_POWER_TRACKING_STATE_SET { - HALMAC_CMD_PROCESS_STATUS process_status; - u8 fw_return_code; - u16 seq_num; -} HALMAC_POWER_TRACKING_STATE_SET, *PHALMAC_POWER_TRACKING_STATE_SET; - -typedef struct _HALMAC_PSD_STATE_SET { - HALMAC_CMD_PROCESS_STATUS process_status; - u16 data_size; - u16 segment_size; - u8 *pData; - u8 fw_return_code; - u16 seq_num; -} HALMAC_PSD_STATE_SET, *PHALMAC_PSD_STATE_SET; - -typedef struct _HALMAC_STATE { - HALMAC_EFUSE_STATE_SET efuse_state_set; /* State machine + cmd process status */ - HALMAC_CFG_PARA_STATE_SET cfg_para_state_set; /* State machine + cmd process status */ - HALMAC_SCAN_STATE_SET scan_state_set; /* State machine + cmd process status */ - HALMAC_UPDATE_PACKET_STATE_SET update_packet_set; /* cmd process status */ - HALMAC_IQK_STATE_SET iqk_set; /* cmd process status */ - HALMAC_POWER_TRACKING_STATE_SET power_tracking_set; /* cmd process status */ - HALMAC_PSD_STATE_SET psd_set; /* cmd process status */ - HALMAC_API_STATE api_state; /* Halmac api state */ - HALMAC_MAC_POWER mac_power; /* 0 : power off, 1 : power on*/ - HALMAC_PS_STATE ps_state; /* power saving state */ - HALMAC_DLFW_STATE dlfw_state; /* download FW state */ -} HALMAC_STATE, *PHALMAC_STATE; - -typedef struct _HALMAC_VER { +}; + +struct halmac_ver { u8 major_ver; u8 prototype_ver; u8 minor_ver; -} HALMAC_VER, *PHALMAC_VER; +}; - -typedef enum _HALMAC_API_ID { +enum halmac_api_id { /*stuff, need to be the 1st*/ HALMAC_API_STUFF = 0x0, /*stuff, need to be the 1st*/ @@ -1582,8 +1428,6 @@ typedef enum _HALMAC_API_ID { HALMAC_API_DEINIT_INTERFACE_CFG = 0x18, HALMAC_API_GET_EFUSE_SIZE = 0x19, HALMAC_API_DUMP_EFUSE_MAP = 0x1A, - HALMAC_API_WRITE_EFUSE = 0x1B, - HALMAC_API_READ_EFUSE = 0x1C, HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D, HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E, HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F, @@ -1653,7 +1497,6 @@ typedef enum _HALMAC_API_ID { HALMAC_API_GET_HW_VALUE = 0x5F, HALMAC_API_SET_HW_VALUE = 0x60, HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61, - HALMAC_API_SWITCH_EFUSE_BANK = 0x62, HALMAC_API_WRITE_EFUSE_BT = 0x63, HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64, HALMAC_API_DL_DRV_RSVD_PG = 0x65, @@ -1677,44 +1520,77 @@ typedef enum _HALMAC_API_ID { HALMAC_API_CFG_TRANS_ADDR = 0x77, HALMAC_API_INTF_INTEGRA_TUNING = 0x78, HALMAC_API_TXFIFO_IS_EMPTY = 0x79, + HALMAC_API_DOWNLOAD_FLASH = 0x7A, + HALMAC_API_READ_FLASH = 0x7B, + HALMAC_API_ERASE_FLASH = 0x7C, + HALMAC_API_CHECK_FLASH = 0x7D, HALMAC_API_SDIO_HW_INFO = 0x80, + HALMAC_API_READ_EFUSE_BT = 0x81, + HALMAC_API_CFG_EFUSE_AUTO_CHECK = 0x82, + HALMAC_API_CFG_PINMUX_GET_FUNC = 0x83, + HALMAC_API_CFG_PINMUX_SET_FUNC = 0x84, + HALMAC_API_CFG_PINMUX_FREE_FUNC = 0x85, + HALMAC_API_CFG_PINMUX_WL_LED_MODE = 0x86, + HALMAC_API_CFG_PINMUX_WL_LED_SW_CTRL = 0x87, + HALMAC_API_CFG_PINMUX_SDIO_INT_POLARITY = 0x88, + HALMAC_API_CFG_PINMUX_GPIO_MODE = 0x89, + HALMAC_API_CFG_PINMUX_GPIO_OUTPUT = 0x90, + HALMAC_API_REG_READ_INDIRECT_32 = 0x91, + HALMAC_API_REG_SDIO_CMD53_READ_N = 0x92, + HALMAC_API_PINMUX_PIN_STATUS = 0x94, + HALMAC_API_OFLD_FUNC_CFG = 0x95, + HALMAC_API_MASK_LOGICAL_EFUSE = 0x96, + HALMAC_API_RX_CUT_AMSDU_CFG = 0x97, + HALMAC_API_FW_SNDING = 0x98, + HALMAC_API_ENTER_CPU_SLEEP_MODE = 0x99, + HALMAC_API_GET_CPU_MODE = 0x9A, + HALMAC_API_DRV_FWCTRL = 0x9B, + HALMAC_API_EN_REF_AUTOK = 0x9C, HALMAC_API_MAX -} HALMAC_API_ID; - -typedef struct _HALMAC_API_RECORD { - HALMAC_API_ID api_array[API_ARRAY_SIZE]; - u8 array_wptr; -} HALMAC_API_RECORD, *PHALMAC_API_RECORD; +}; -typedef enum _HALMAC_LA_MODE { +enum halmac_la_mode { HALMAC_LA_MODE_DISABLE = 0, HALMAC_LA_MODE_PARTIAL = 1, HALMAC_LA_MODE_FULL = 2, HALMAC_LA_MODE_UNDEFINE = 0x7F, -} HALMAC_LA_MODE; +}; -typedef enum _HALMAC_RX_FIFO_EXPANDING_MODE { +enum halmac_rx_fifo_expanding_mode { HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0, HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1, HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2, HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3, + HALMAC_RX_FIFO_EXPANDING_MODE_4_BLOCK = 4, HALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F, -} HALMAC_RX_FIFO_EXPANDING_MODE; +}; -typedef enum _HALMAC_SDIO_CMD53_4BYTE_MODE { +enum halmac_sdio_cmd53_4byte_mode { HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0, HALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1, HALMAC_SDIO_CMD53_4BYTE_MODE_R = 2, HALMAC_SDIO_CMD53_4BYTE_MODE_W = 3, HALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F, -} HALMAC_SDIO_CMD53_4BYTE_MODE; +}; -typedef enum _HALMAC_USB_MODE { +enum halmac_usb_mode { HALMAC_USB_MODE_U2 = 1, HALMAC_USB_MODE_U3 = 2, -} HALMAC_USB_MODE; +}; + +enum halmac_sdio_tx_format { + HALMAC_SDIO_AGG_MODE = 1, + HALMAC_SDIO_DUMMY_BLOCK_MODE = 2, + HALMAC_SDIO_DUMMY_AUTO_MODE = 3, +}; + +enum halmac_sdio_clk_monitor { + HALMAC_MONITOR_5US = 1, + HALMAC_MONITOR_50US = 2, + HALMAC_MONITOR_9MS = 3, +}; -typedef enum _HALMAC_HW_ID { +enum halmac_hw_id { /* Get HW value */ HALMAC_HW_RQPN_MAPPING = 0x00, HALMAC_HW_EFUSE_SIZE = 0x01, @@ -1723,19 +1599,32 @@ typedef enum _HALMAC_HW_ID { HALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04, HALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05, HALMAC_HW_TXFIFO_SIZE = 0x06, - HALMAC_HW_RSVD_PG_BNDY = 0x07, - HALMAC_HW_CAM_ENTRY_NUM = 0x08, - HALMAC_HW_IC_VERSION = 0x09, - HALMAC_HW_PAGE_SIZE = 0x0A, - HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0B, - HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0C, - HALMAC_HW_DRV_INFO_SIZE = 0x0D, - HALMAC_HW_TXFF_ALLOCATION = 0x0E, - HALMAC_HW_RSVD_EFUSE_SIZE = 0x0F, - HALMAC_HW_FW_HDR_SIZE = 0x10, - HALMAC_HW_TX_DESC_SIZE = 0x11, - HALMAC_HW_RX_DESC_SIZE = 0x12, - HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x13, + HALMAC_HW_RXFIFO_SIZE = 0x07, + HALMAC_HW_RSVD_PG_BNDY = 0x08, + HALMAC_HW_CAM_ENTRY_NUM = 0x09, + HALMAC_HW_IC_VERSION = 0x0A, + HALMAC_HW_PAGE_SIZE = 0x0B, + HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0C, + HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0D, + HALMAC_HW_DRV_INFO_SIZE = 0x0E, + HALMAC_HW_TXFF_ALLOCATION = 0x0F, + HALMAC_HW_RSVD_EFUSE_SIZE = 0x10, + HALMAC_HW_FW_HDR_SIZE = 0x11, + HALMAC_HW_TX_DESC_SIZE = 0x12, + HALMAC_HW_RX_DESC_SIZE = 0x13, + HALMAC_HW_FW_MAX_SIZE = 0x14, + HALMAC_HW_ORI_H2C_SIZE = 0x15, + HALMAC_HW_RSVD_DRV_PGNUM = 0x16, + HALMAC_HW_TX_PAGE_SIZE = 0x17, + HALMAC_HW_USB_TXAGG_DESC_NUM = 0x18, + HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x19, + HALMAC_HW_AC_OQT_SIZE = 0x1C, + HALMAC_HW_NON_AC_OQT_SIZE = 0x1D, + HALMAC_HW_AC_QUEUE_NUM = 0x1E, + HALMAC_HW_RQPN_CH_MAPPING = 0x1F, + HALMAC_HW_PWR_STATE = 0x20, + HALMAC_HW_SDIO_INT_LAT = 0x21, + HALMAC_HW_SDIO_CLK_CNT = 0x22, /* Set HW value */ HALMAC_HW_USB_MODE = 0x60, HALMAC_HW_SEQ_EN = 0x61, @@ -1745,387 +1634,776 @@ typedef enum _HALMAC_HW_ID { HALMAC_HW_EN_BB_RF = 0x65, HALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66, HALMAC_HW_AMPDU_CONFIG = 0x67, - + HALMAC_HW_RX_SHIFT = 0x68, + HALMAC_HW_TXDESC_CHECKSUM = 0x69, + HALMAC_HW_RX_CLK_GATE = 0x6A, + HALMAC_HW_RXGCK_FIFO = 0x6B, + HALMAC_HW_RX_IGNORE = 0x6C, + HALMAC_HW_SDIO_TX_FORMAT = 0x6D, + HALMAC_HW_FAST_EDCA = 0x6E, + HALMAC_HW_LDO25_EN = 0x6F, + HALMAC_HW_PCIE_REF_AUTOK = 0x70, + HALMAC_HW_RTS_FULL_BW = 0x71, + HALMAC_HW_FREE_CNT_EN = 0x72, + HALMAC_HW_SDIO_WT_EN = 0x73, + HALMAC_HW_SDIO_CLK_MONITOR = 0x74, HALMAC_HW_ID_UNDEFINE = 0x7F, -} HALMAC_HW_ID; -typedef enum _HALMAC_EFUSE_BANK { +}; + +enum halmac_efuse_bank { HALMAC_EFUSE_BANK_WIFI = 0, HALMAC_EFUSE_BANK_BT = 1, HALMAC_EFUSE_BANK_BT_1 = 2, HALMAC_EFUSE_BANK_BT_2 = 3, HALMAC_EFUSE_BANK_MAX, HALMAC_EFUSE_BANK_UNDEFINE = 0X7F, -} HALMAC_EFUSE_BANK; +}; -typedef enum _HALMAC_SDIO_SPEC_VER { +enum halmac_sdio_spec_ver { HALMAC_SDIO_SPEC_VER_2_00 = 0, HALMAC_SDIO_SPEC_VER_3_00 = 1, HALMAC_SDIO_SPEC_VER_UNDEFINE = 0X7F, -} HALMAC_SDIO_SPEC_VER; - -typedef struct _HALMAC_TXFF_ALLOCATION { +}; + +enum halmac_gpio_func { + HALMAC_GPIO_FUNC_WL_LED = 0, + HALMAC_GPIO_FUNC_SDIO_INT = 1, + HALMAC_GPIO_FUNC_SW_IO_0 = 2, + HALMAC_GPIO_FUNC_SW_IO_1 = 3, + HALMAC_GPIO_FUNC_SW_IO_2 = 4, + HALMAC_GPIO_FUNC_SW_IO_3 = 5, + HALMAC_GPIO_FUNC_SW_IO_4 = 6, + HALMAC_GPIO_FUNC_SW_IO_5 = 7, + HALMAC_GPIO_FUNC_SW_IO_6 = 8, + HALMAC_GPIO_FUNC_SW_IO_7 = 9, + HALMAC_GPIO_FUNC_SW_IO_8 = 10, + HALMAC_GPIO_FUNC_SW_IO_9 = 11, + HALMAC_GPIO_FUNC_SW_IO_10 = 12, + HALMAC_GPIO_FUNC_SW_IO_11 = 13, + HALMAC_GPIO_FUNC_SW_IO_12 = 14, + HALMAC_GPIO_FUNC_SW_IO_13 = 15, + HALMAC_GPIO_FUNC_SW_IO_14 = 16, + HALMAC_GPIO_FUNC_SW_IO_15 = 17, + HALMAC_GPIO_FUNC_BT_HOST_WAKE1 = 18, + HALMAC_GPIO_FUNC_BT_DEV_WAKE1 = 19, + HALMAC_GPIO_FUNC_UNDEFINE = 0X7F, +}; + +enum halmac_wlled_mode { + HALMAC_WLLED_MODE_TRX = 0, + HALMAC_WLLED_MODE_TX = 1, + HALMAC_WLLED_MODE_RX = 2, + HALMAC_WLLED_MODE_SW_CTRL = 3, + HALMAC_WLLED_MODE_UNDEFINE = 0X7F, +}; + +enum halmac_psf_fcs_chk_thr { + HALMAC_PSF_FCS_CHK_THR_1 = 0, + HALMAC_PSF_FCS_CHK_THR_4 = 1, + HALMAC_PSF_FCS_CHK_THR_8 = 2, + HALMAC_PSF_FCS_CHK_THR_12 = 3, + HALMAC_PSF_FCS_CHK_THR_16 = 4, + HALMAC_PSF_FCS_CHK_THR_20 = 5, + HALMAC_PSF_FCS_CHK_THR_24 = 6, + HALMAC_PSF_FCS_CHK_THR_28 = 7, +}; + +struct halmac_txff_allocation { u16 tx_fifo_pg_num; u16 rsvd_pg_num; u16 rsvd_drv_pg_num; - u16 ac_q_pg_num; + u16 acq_pg_num; u16 high_queue_pg_num; u16 low_queue_pg_num; u16 normal_queue_pg_num; u16 extra_queue_pg_num; u16 pub_queue_pg_num; - u16 rsvd_pg_bndy; - u16 rsvd_drv_pg_bndy; - u16 rsvd_h2c_extra_info_pg_bndy; - u16 rsvd_h2c_queue_pg_bndy; - u16 rsvd_cpu_instr_pg_bndy; - u16 rsvd_fw_txbuff_pg_bndy; - HALMAC_LA_MODE la_mode; - HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode; -} HALMAC_TXFF_ALLOCATION, *PHALMAC_TXFF_ALLOCATION; - -typedef struct _HALMAC_RQPN_MAP { - HALMAC_DMA_MAPPING dma_map_vo; - HALMAC_DMA_MAPPING dma_map_vi; - HALMAC_DMA_MAPPING dma_map_be; - HALMAC_DMA_MAPPING dma_map_bk; - HALMAC_DMA_MAPPING dma_map_mg; - HALMAC_DMA_MAPPING dma_map_hi; -} HALMAC_RQPN_MAP, *PHALMAC_RQPN_MAP; - -typedef struct _HALMAC_SECURITY_SETTING { + u16 rsvd_boundary; + u16 rsvd_drv_addr; + u16 rsvd_h2c_info_addr; + u16 rsvd_h2c_sta_info_addr; + u16 rsvd_h2cq_addr; + u16 rsvd_cpu_instr_addr; + u16 rsvd_fw_txbuf_addr; + u16 rsvd_csibuf_addr; + enum halmac_la_mode la_mode; + enum halmac_rx_fifo_expanding_mode rx_fifo_exp_mode; +}; + +struct halmac_rqpn_map { + enum halmac_dma_mapping dma_map_vo; + enum halmac_dma_mapping dma_map_vi; + enum halmac_dma_mapping dma_map_be; + enum halmac_dma_mapping dma_map_bk; + enum halmac_dma_mapping dma_map_mg; + enum halmac_dma_mapping dma_map_hi; +}; + +struct halmac_rqpn_ch_map { + enum halmac_dma_ch dma_map_vo; + enum halmac_dma_ch dma_map_vi; + enum halmac_dma_ch dma_map_be; + enum halmac_dma_ch dma_map_bk; + enum halmac_dma_ch dma_map_mg; + enum halmac_dma_ch dma_map_hi; +}; + +struct halmac_security_setting { u8 tx_encryption; u8 rx_decryption; u8 bip_enable; -} HALMAC_SECURITY_SETTING, *PHALMAC_SECURITY_SETTING; + u8 compare_keyid; +}; -typedef struct _HALMAC_CAM_ENTRY_INFO { - HAL_SECURITY_TYPE security_type; +struct halmac_cam_entry_info { + enum hal_security_type security_type; u32 key[4]; u32 key_ext[4]; u8 mac_address[6]; u8 unicast; u8 key_id; u8 valid; -} HALMAC_CAM_ENTRY_INFO, *PHALMAC_CAM_ENTRY_INFO; - -typedef struct _HALMAC_CAM_ENTRY_FORMAT { - u16 key_id : 2; - u16 type : 3; - u16 mic : 1; - u16 grp : 1; - u16 spp_mode : 1; - u16 rpt_md : 1; - u16 ext_sectype : 1; +}; + +struct halmac_cam_entry_format { + u16 key_id : 2; + u16 type : 3; + u16 mic : 1; + u16 grp : 1; + u16 spp_mode : 1; + u16 rpt_md : 1; + u16 ext_sectype : 1; u16 mgnt : 1; - u16 rsvd1 : 4; + u16 rsvd1 : 4; u16 valid : 1; u8 mac_address[6]; - u32 key[4]; - u32 rsvd[2]; -} HALMAC_CAM_ENTRY_FORMAT, *PHALMAC_CAM_ENTRY_FORMAT; + u32 key[4]; + u32 rsvd[2]; +}; -typedef struct _HALMAC_TX_PAGE_THRESHOLD_INFO { +struct halmac_tx_page_threshold_info { u32 threshold; - HALMAC_DMA_MAPPING dma_queue_sel; -} HALMAC_TX_PAGE_THRESHOLD_INFO, *PHALMAC_TX_PAGE_THRESHOLD_INFO; + enum halmac_dma_mapping dma_queue_sel; + u8 enable; +}; -typedef struct _HALMAC_AMPDU_CONFIG { +struct halmac_ampdu_config { u8 max_agg_num; -} HALMAC_AMPDU_CONFIG, *PHALMAC_AMPDU_CONFIG; - -typedef struct _HALMAC_PORT_CFG { - u8 port0_sync_tsf; - u8 port1_sync_tsf; -} HALMAC_PORT_CFG, *PHALMAC_PORT_CFG; - -typedef struct _HALMAC_RQPN_ { - HALMAC_TRX_MODE mode; - HALMAC_DMA_MAPPING dma_map_vo; - HALMAC_DMA_MAPPING dma_map_vi; - HALMAC_DMA_MAPPING dma_map_be; - HALMAC_DMA_MAPPING dma_map_bk; - HALMAC_DMA_MAPPING dma_map_mg; - HALMAC_DMA_MAPPING dma_map_hi; -} HALMAC_RQPN, *PHALMAC_RQPN; - -typedef struct _HALMAC_PG_NUM_ { - HALMAC_TRX_MODE mode; - u16 hq_num; + u8 max_len_en; + u32 ht_max_len; + u32 vht_max_len; +}; + +struct halmac_rqpn { + enum halmac_trx_mode mode; + enum halmac_dma_mapping dma_map_vo; + enum halmac_dma_mapping dma_map_vi; + enum halmac_dma_mapping dma_map_be; + enum halmac_dma_mapping dma_map_bk; + enum halmac_dma_mapping dma_map_mg; + enum halmac_dma_mapping dma_map_hi; +}; + +struct halmac_ch_mapping { + enum halmac_trx_mode mode; + enum halmac_dma_ch dma_map_vo; + enum halmac_dma_ch dma_map_vi; + enum halmac_dma_ch dma_map_be; + enum halmac_dma_ch dma_map_bk; + enum halmac_dma_ch dma_map_mg; + enum halmac_dma_ch dma_map_hi; +}; + +struct halmac_pg_num { + enum halmac_trx_mode mode; + u16 hq_num; u16 nq_num; u16 lq_num; u16 exq_num; u16 gap_num;/*used for loopback mode*/ -} HALMAC_PG_NUM, *PHALMAC_PG_NUM; +}; + +struct halmac_ch_pg_num { + enum halmac_trx_mode mode; + u16 ch_num[HALMAC_TXDESC_DMA_CH16 + 1]; + u16 gap_num; +}; -typedef struct _HALMAC_INTF_PHY_PARA_ { +struct halmac_intf_phy_para { u16 offset; u16 value; u16 ip_sel; u16 cut; u16 plaform; -} HALMAC_INTF_PHY_PARA, *PHALMAC_INTF_PHY_PARA; +}; -typedef struct _HALMAC_IQK_PARA_ { +struct halmac_iqk_para { u8 clear; u8 segment_iqk; -} HALMAC_IQK_PARA, *PHALMAC_IQK_PARA; +}; -typedef struct _HALMAC_SDIO_HW_INFO { - HALMAC_SDIO_SPEC_VER spec_ver; +struct halmac_txdesc_ie_param { + u8 *start_offset; + u8 *end_offset; + u8 *ie_offset; + u8 *ie_exist; +}; + +struct halmac_sdio_hw_info { + enum halmac_sdio_spec_ver spec_ver; u32 clock_speed; u8 io_hi_speed_flag; /* Halmac internal use */ -} HALMAC_SDIO_HW_INFO, *PHALMAC_SDIO_HW_INFO; - -/* Hal mac adapter */ -typedef struct _HALMAC_ADAPTER { - HALMAC_DMA_MAPPING halmac_ptcl_queue[HALMAC_PTCL_QUEUE_NUM]; /* Dma mapping of protocol queues */ - HALMAC_FWLPS_OPTION fwlps_option; /* low power state option */ - HALMAC_WLAN_ADDR pHal_mac_addr[HALMAC_PORTIDMAX]; /* mac address information, suppot 2 ports */ - HALMAC_WLAN_ADDR pHal_bss_addr[HALMAC_PORTIDMAX]; /* bss address information, suppot 2 ports */ - HALMAC_MUTEX h2c_seq_mutex; /* Protect h2c_packet_seq packet*/ - HALMAC_MUTEX EfuseMutex; /* Protect Efuse map memory of halmac_adapter */ - HALMAC_CONFIG_PARA_INFO config_para_info; - HALMAC_CS_INFO ch_sw_info; - HALMAC_EVENT_TRIGGER event_trigger; - HALMAC_HW_CONFIG_INFO hw_config_info; /* HW related information */ - HALMAC_SDIO_FREE_SPACE sdio_free_space; - HALMAC_SND_INFO snd_info; - VOID *pHalAdapter_backup; /* Backup HalAdapter address */ - VOID *pDriver_adapter; /* Driver or FW adapter address. Do not write this memory*/ - u8 *pHalEfuse_map; - VOID *pHalmac_api; /* Record function pointer of halmac api */ - PHALMAC_PLATFORM_API pHalmac_platform_api; /* Record function pointer of platform api */ - u32 efuse_end; /* Record efuse used memory */ - u32 h2c_buf_free_space; - u32 h2c_buff_size; - u32 max_download_size; - HALMAC_CHIP_ID chip_id; /* Chip ID, 8822B, 8821C... */ - HALMAC_CHIP_VER chip_version; /* A cut, B cut... */ - HALMAC_FW_VERSION fw_version; - HALMAC_STATE halmac_state; - HALMAC_INTERFACE halmac_interface; /* Interface information, get from driver */ - HALMAC_TRX_MODE trx_mode; /* Noraml, WMM, P2P, LoopBack... */ - HALMAC_TXFF_ALLOCATION txff_allocation; - u8 h2c_packet_seq; /* current h2c packet sequence number */ - u16 ack_h2c_packet_seq; /*the acked h2c packet sequence number */ - u8 hal_efuse_map_valid; - u8 efuse_segment_size; - u8 rpwm_record; /* record rpwm value */ - u8 low_clk; /*LPS 32K or IPS 32K*/ - u8 halmac_bulkout_num; /* USB bulkout num */ - HALMAC_API_RECORD api_record; /* API record */ - u8 gen_info_valid; - HALMAC_GENERAL_INFO general_info; + enum halmac_sdio_tx_format tx_addr_format; + u16 block_size; + u8 tx_seq; + u8 io_indir_flag; /* Halmac internal use */ +}; + +struct halmac_edca_para { + u8 aifs; + u8 cw; + u16 txop_limit; +}; + +struct halmac_mac_rx_ignore_cfg { + u8 hdr_chk_en; + u8 fcs_chk_en; + u8 cck_rst_en; + enum halmac_psf_fcs_chk_thr fcs_chk_thr; +}; + +struct halmac_rx_ignore_info { + u8 hdr_chk_mask; + u8 fcs_chk_mask; + u8 hdr_chk_en; + u8 fcs_chk_en; + u8 cck_rst_en; + enum halmac_psf_fcs_chk_thr fcs_chk_thr; +}; + +struct halmac_pinmux_info { + /* byte0 */ + u8 wl_led:1; + u8 sdio_int:1; + u8 bt_host_wake:1; + u8 bt_dev_wake:1; + u8 rsvd1:4; + /* byte1 */ + u8 sw_io_0:1; + u8 sw_io_1:1; + u8 sw_io_2:1; + u8 sw_io_3:1; + u8 sw_io_4:1; + u8 sw_io_5:1; + u8 sw_io_6:1; + u8 sw_io_7:1; + /* byte2 */ + u8 sw_io_8:1; + u8 sw_io_9:1; + u8 sw_io_10:1; + u8 sw_io_11:1; + u8 sw_io_12:1; + u8 sw_io_13:1; + u8 sw_io_14:1; + u8 sw_io_15:1; +}; + +struct halmac_ofld_func_info { + u32 halmac_malloc_max_sz; + u32 rsvd_pg_drv_buf_max_sz; +}; + +struct halmac_pltfm_cfg_info { + u32 malloc_size; + u32 rsvd_pg_size; +}; + +struct halmac_su_snding_info { + u8 su0_en; + u8 *su0_ndpa_pkt; + u32 su0_pkt_sz; +}; + +struct halmac_mu_snding_info { + u8 tmp; +}; + +struct halmac_h2c_info { + u32 buf_fs; + u32 buf_size; + u8 seq_num; +}; + +struct halmac_adapter { + enum halmac_dma_mapping pq_map[HALMAC_PQ_MAP_NUM]; + enum halmac_dma_ch ch_map[HALMAC_PQ_MAP_NUM]; + HALMAC_MUTEX h2c_seq_mutex; /* protect h2c seq num */ + HALMAC_MUTEX efuse_mutex; /*protect adapter efuse map */ + HALMAC_MUTEX sdio_indir_mutex; /*protect sdio indirect access */ + struct halmac_cfg_param_info cfg_param_info; + struct halmac_ch_sw_info ch_sw_info; + struct halmac_event_trigger evnt; + struct halmac_hw_cfg_info hw_cfg_info; + struct halmac_sdio_free_space sdio_fs; + struct halmac_api_registry api_registry; + struct halmac_pinmux_info pinmux_info; + struct halmac_pltfm_cfg_info pltfm_info; + struct halmac_h2c_info h2c_info; + void *drv_adapter; + u8 *efuse_map; + void *halmac_api; + struct halmac_platform_api *pltfm_api; + u32 efuse_end; + u32 dlfw_pkt_size; + enum halmac_chip_id chip_id; + enum halmac_chip_ver chip_ver; + struct halmac_fw_version fw_ver; + struct halmac_state halmac_state; + enum halmac_interface intf; + enum halmac_trx_mode trx_mode; + struct halmac_txff_allocation txff_alloc; + u8 efuse_map_valid; + u8 efuse_seg_size; + u8 rpwm; + u8 bulkout_num; u8 drv_info_size; - HALMAC_SDIO_CMD53_4BYTE_MODE sdio_cmd53_4byte; - HALMAC_SDIO_HW_INFO sdio_hw_info; + enum halmac_sdio_cmd53_4byte_mode sdio_cmd53_4byte; + struct halmac_sdio_hw_info sdio_hw_info; + u8 tx_desc_transfer; + u8 tx_desc_checksum; + u8 efuse_auto_check_en; + u8 pcie_refautok_en; + u8 pwr_off_flow_flag; + struct halmac_rx_ignore_info rx_ignore_info; #if HALMAC_PLATFORM_TESTPROGRAM - HALMAC_TXAGG_BUFF_INFO halmac_tx_buf_info[4]; - HALMAC_MUTEX agg_buff_mutex; /*used for tx_agg_buffer */ - u8 max_agg_num; - u8 send_bcn_reg_cr_backup; + struct halmisc_adapter *halmisc_adapter; +#endif +}; + +struct halmac_api { + enum halmac_ret_status + (*halmac_register_api)(struct halmac_adapter *adapter, + struct halmac_api_registry *registry); + enum halmac_ret_status + (*halmac_mac_power_switch)(struct halmac_adapter *adapter, + enum halmac_mac_power pwr); + enum halmac_ret_status + (*halmac_download_firmware)(struct halmac_adapter *adapter, u8 *fw_bin, + u32 size); + enum halmac_ret_status + (*halmac_free_download_firmware)(struct halmac_adapter *adapter, + enum halmac_dlfw_mem mem_sel, + u8 *fw_bin, u32 size); + enum halmac_ret_status + (*halmac_get_fw_version)(struct halmac_adapter *adapter, + struct halmac_fw_version *ver); + enum halmac_ret_status + (*halmac_cfg_mac_addr)(struct halmac_adapter *adapter, + u8 port, union halmac_wlan_addr *addr); + enum halmac_ret_status + (*halmac_cfg_bssid)(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + enum halmac_ret_status + (*halmac_cfg_multicast_addr)(struct halmac_adapter *adapter, + union halmac_wlan_addr *addr); + enum halmac_ret_status + (*halmac_pre_init_system_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_system_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_trx_cfg)(struct halmac_adapter *adapter, + enum halmac_trx_mode mode); + enum halmac_ret_status + (*halmac_init_h2c)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_cfg_rx_aggregation)(struct halmac_adapter *adapter, + struct halmac_rxagg_cfg *cfg); + enum halmac_ret_status + (*halmac_init_protocol_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_edca_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_cfg_operation_mode)(struct halmac_adapter *adapter, + enum halmac_wireless_mode mode); + enum halmac_ret_status + (*halmac_cfg_ch_bw)(struct halmac_adapter *adapter, u8 ch, + enum halmac_pri_ch_idx idx, enum halmac_bw bw); + enum halmac_ret_status + (*halmac_cfg_bw)(struct halmac_adapter *adapter, enum halmac_bw bw); + enum halmac_ret_status + (*halmac_init_wmac_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_mac_cfg)(struct halmac_adapter *adapter, + enum halmac_trx_mode mode); + enum halmac_ret_status + (*halmac_init_interface_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_deinit_interface_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_sdio_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_usb_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_init_pcie_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_deinit_sdio_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_deinit_usb_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_deinit_pcie_cfg)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_get_efuse_size)(struct halmac_adapter *adapter, u32 *size); + enum halmac_ret_status + (*halmac_get_efuse_available_size)(struct halmac_adapter *adapter, + u32 *size); + enum halmac_ret_status + (*halmac_dump_efuse_map)(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg); + enum halmac_ret_status + (*halmac_dump_efuse_map_bt)(struct halmac_adapter *adapter, + enum halmac_efuse_bank bank, u32 size, + u8 *map); + enum halmac_ret_status + (*halmac_write_efuse_bt)(struct halmac_adapter *adapter, u32 offset, + u8 value, enum halmac_efuse_bank bank); + enum halmac_ret_status + (*halmac_read_efuse_bt)(struct halmac_adapter *adapter, u32 offset, + u8 *value, enum halmac_efuse_bank bank); + enum halmac_ret_status + (*halmac_cfg_efuse_auto_check)(struct halmac_adapter *adapter, + u8 enable); + enum halmac_ret_status + (*halmac_get_logical_efuse_size)(struct halmac_adapter *adapter, + u32 *size); + enum halmac_ret_status + (*halmac_dump_logical_efuse_map)(struct halmac_adapter *adapter, + enum halmac_efuse_read_cfg cfg); + enum halmac_ret_status + (*halmac_write_logical_efuse)(struct halmac_adapter *adapter, + u32 offset, u8 value); + enum halmac_ret_status + (*halmac_read_logical_efuse)(struct halmac_adapter *adapter, u32 offset, + u8 *value); + enum halmac_ret_status + (*halmac_pg_efuse_by_map)(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info, + enum halmac_efuse_read_cfg cfg); + enum halmac_ret_status + (*halmac_mask_logical_efuse)(struct halmac_adapter *adapter, + struct halmac_pg_efuse_info *info); + enum halmac_ret_status + (*halmac_get_c2h_info)(struct halmac_adapter *adapter, u8 *buf, + u32 size); + enum halmac_ret_status + (*halmac_h2c_lb)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_debug)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_cfg_parameter)(struct halmac_adapter *adapter, + struct halmac_phy_parameter_info *info, + u8 full_fifo); + enum halmac_ret_status + (*halmac_update_packet)(struct halmac_adapter *adapter, + enum halmac_packet_id pkt_id, u8 *pkt, + u32 size); + enum halmac_ret_status + (*halmac_bcn_ie_filter)(struct halmac_adapter *adapter, + struct halmac_bcn_ie_info *info); + u8 + (*halmac_reg_read_8)(struct halmac_adapter *adapter, u32 offset); + enum halmac_ret_status + (*halmac_reg_write_8)(struct halmac_adapter *adapter, u32 offset, + u8 value); + u16 + (*halmac_reg_read_16)(struct halmac_adapter *adapter, u32 offset); + enum halmac_ret_status + (*halmac_reg_write_16)(struct halmac_adapter *adapter, u32 offset, + u16 value); + u32 + (*halmac_reg_read_32)(struct halmac_adapter *adapter, u32 offset); + enum halmac_ret_status + (*halmac_reg_write_32)(struct halmac_adapter *adapter, u32 offset, + u32 value); + u32 + (*halmac_reg_read_indirect_32)(struct halmac_adapter *adapter, + u32 offset); + enum halmac_ret_status + (*halmac_reg_sdio_cmd53_read_n)(struct halmac_adapter *adapter, + u32 offset, u32 size, u8 *value); + enum halmac_ret_status + (*halmac_tx_allowed_sdio)(struct halmac_adapter *adapter, u8 *buf, + u32 size); + enum halmac_ret_status + (*halmac_set_bulkout_num)(struct halmac_adapter *adapter, u8 num); + enum halmac_ret_status + (*halmac_get_sdio_tx_addr)(struct halmac_adapter *adapter, u8 *buf, + u32 size, u32 *cmd53_addr); + enum halmac_ret_status + (*halmac_get_usb_bulkout_id)(struct halmac_adapter *adapter, u8 *buf, + u32 size, u8 *id); + enum halmac_ret_status + (*halmac_fill_txdesc_checksum)(struct halmac_adapter *adapter, + u8 *txdesc); + enum halmac_ret_status + (*halmac_update_datapack)(struct halmac_adapter *adapter, + enum halmac_data_type data_type, + struct halmac_phy_parameter_info *info); + enum halmac_ret_status + (*halmac_run_datapack)(struct halmac_adapter *adapter, + enum halmac_data_type data_type); + enum halmac_ret_status + (*halmac_cfg_drv_info)(struct halmac_adapter *adapter, + enum halmac_drv_info drv_info); + enum halmac_ret_status + (*halmac_send_bt_coex)(struct halmac_adapter *adapter, u8 *buf, + u32 size, u8 ack); + enum halmac_ret_status + (*halmac_verify_platform_api)(struct halmac_adapter *adapter); + u32 + (*halmac_get_fifo_size)(struct halmac_adapter *adapter, + enum hal_fifo_sel sel); + enum halmac_ret_status + (*halmac_dump_fifo)(struct halmac_adapter *adapter, + enum hal_fifo_sel sel, u32 start_addr, u32 size, + u8 *data); + enum halmac_ret_status + (*halmac_cfg_txbf)(struct halmac_adapter *adapter, u8 userid, + enum halmac_bw bw, u8 txbf_en); + enum halmac_ret_status + (*halmac_cfg_mumimo)(struct halmac_adapter *adapter, + struct halmac_cfg_mumimo_para *param); + enum halmac_ret_status + (*halmac_cfg_sounding)(struct halmac_adapter *adapter, + enum halmac_snd_role role, + enum halmac_data_rate rate); + enum halmac_ret_status + (*halmac_del_sounding)(struct halmac_adapter *adapter, + enum halmac_snd_role role); + enum halmac_ret_status + (*halmac_su_bfer_entry_init)(struct halmac_adapter *adapter, + struct halmac_su_bfer_init_para *param); + enum halmac_ret_status + (*halmac_su_bfee_entry_init)(struct halmac_adapter *adapter, u8 userid, + u16 paid); + enum halmac_ret_status + (*halmac_mu_bfer_entry_init)(struct halmac_adapter *adapter, + struct halmac_mu_bfer_init_para *param); + enum halmac_ret_status + (*halmac_mu_bfee_entry_init)(struct halmac_adapter *adapter, + struct halmac_mu_bfee_init_para *param); + enum halmac_ret_status + (*halmac_su_bfer_entry_del)(struct halmac_adapter *adapter, u8 userid); + enum halmac_ret_status + (*halmac_su_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid); + enum halmac_ret_status + (*halmac_mu_bfer_entry_del)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_mu_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid); + enum halmac_ret_status + (*halmac_add_ch_info)(struct halmac_adapter *adapter, + struct halmac_ch_info *info); + enum halmac_ret_status + (*halmac_add_extra_ch_info)(struct halmac_adapter *adapter, + struct halmac_ch_extra_info *info); + enum halmac_ret_status + (*halmac_ctrl_ch_switch)(struct halmac_adapter *adapter, + struct halmac_ch_switch_option *opt); + enum halmac_ret_status + (*halmac_p2pps)(struct halmac_adapter *adapter, + struct halmac_p2pps *info); + enum halmac_ret_status + (*halmac_clear_ch_info)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_send_general_info)(struct halmac_adapter *adapter, + struct halmac_general_info *info); + enum halmac_ret_status + (*halmac_start_iqk)(struct halmac_adapter *adapter, + struct halmac_iqk_para *param); + enum halmac_ret_status + (*halmac_ctrl_pwr_tracking)(struct halmac_adapter *adapter, + struct halmac_pwr_tracking_option *opt); + enum halmac_ret_status + (*halmac_psd)(struct halmac_adapter *adapter, u16 start_psd, + u16 end_psd); + enum halmac_ret_status + (*halmac_cfg_tx_agg_align)(struct halmac_adapter *adapter, u8 enable, + u16 align_size); + enum halmac_ret_status + (*halmac_query_status)(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id, + enum halmac_cmd_process_status *proc_status, + u8 *data, u32 *size); + enum halmac_ret_status + (*halmac_reset_feature)(struct halmac_adapter *adapter, + enum halmac_feature_id feature_id); + enum halmac_ret_status + (*halmac_check_fw_status)(struct halmac_adapter *adapter, + u8 *fw_status); + enum halmac_ret_status + (*halmac_dump_fw_dmem)(struct halmac_adapter *adapter, u8 *dmem, + u32 *size); + enum halmac_ret_status + (*halmac_cfg_max_dl_size)(struct halmac_adapter *adapter, u32 size); + enum halmac_ret_status + (*halmac_cfg_la_mode)(struct halmac_adapter *adapter, + enum halmac_la_mode mode); + enum halmac_ret_status + (*halmac_cfg_rxff_expand_mode)(struct halmac_adapter *adapter, + enum halmac_rx_fifo_expanding_mode mode); + enum halmac_ret_status + (*halmac_config_security)(struct halmac_adapter *adapter, + struct halmac_security_setting *setting); + u8 + (*halmac_get_used_cam_entry_num)(struct halmac_adapter *adapter, + enum hal_security_type sec_type); + enum halmac_ret_status + (*halmac_write_cam)(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_info *info); + enum halmac_ret_status + (*halmac_read_cam_entry)(struct halmac_adapter *adapter, u32 idx, + struct halmac_cam_entry_format *content); + enum halmac_ret_status + (*halmac_clear_cam_entry)(struct halmac_adapter *adapter, u32 idx); + enum halmac_ret_status + (*halmac_get_hw_value)(struct halmac_adapter *adapter, + enum halmac_hw_id hw_id, void *value); + enum halmac_ret_status + (*halmac_set_hw_value)(struct halmac_adapter *adapter, + enum halmac_hw_id hw_id, void *value); + enum halmac_ret_status + (*halmac_cfg_drv_rsvd_pg_num)(struct halmac_adapter *adapter, + enum halmac_drv_rsvd_pg_num pg_num); + enum halmac_ret_status + (*halmac_get_chip_version)(struct halmac_adapter *adapter, + struct halmac_ver *ver); + enum halmac_ret_status + (*halmac_chk_txdesc)(struct halmac_adapter *adapter, u8 *buf, u32 size); + enum halmac_ret_status + (*halmac_dl_drv_rsvd_page)(struct halmac_adapter *adapter, u8 pg_offset, + u8 *buf, u32 size); + enum halmac_ret_status + (*halmac_pcie_switch)(struct halmac_adapter *adapter, + enum halmac_pcie_cfg cfg); + enum halmac_ret_status + (*halmac_phy_cfg)(struct halmac_adapter *adapter, + enum halmac_intf_phy_platform pltfm); + enum halmac_ret_status + (*halmac_cfg_csi_rate)(struct halmac_adapter *adapter, u8 rssi, + u8 cur_rate, u8 fixrate_en, u8 *new_rate); +#if HALMAC_SDIO_SUPPORT + enum halmac_ret_status + (*halmac_sdio_cmd53_4byte)(struct halmac_adapter *adapter, + enum halmac_sdio_cmd53_4byte_mode mode); + enum halmac_ret_status + (*halmac_sdio_hw_info)(struct halmac_adapter *adapter, + struct halmac_sdio_hw_info *info); +#endif + enum halmac_ret_status + (*halmac_cfg_transmitter_addr)(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + enum halmac_ret_status + (*halmac_cfg_net_type)(struct halmac_adapter *adapter, u8 port, + enum halmac_network_type_select net_type); + enum halmac_ret_status + (*halmac_cfg_tsf_rst)(struct halmac_adapter *adapter, u8 port); + enum halmac_ret_status + (*halmac_cfg_bcn_space)(struct halmac_adapter *adapter, u8 port, + u32 bcn_space); + enum halmac_ret_status + (*halmac_rw_bcn_ctrl)(struct halmac_adapter *adapter, u8 port, + u8 write_en, struct halmac_bcn_ctrl *ctrl); + enum halmac_ret_status + (*halmac_interface_integration_tuning)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_txfifo_is_empty)(struct halmac_adapter *adapter, u32 chk_num); + enum halmac_ret_status + (*halmac_download_flash)(struct halmac_adapter *adapter, u8 *fw_bin, + u32 size, u32 rom_addr); + enum halmac_ret_status + (*halmac_read_flash)(struct halmac_adapter *adapter, u32 addr, + u32 length); + enum halmac_ret_status + (*halmac_erase_flash)(struct halmac_adapter *adapter, u8 erase_cmd, + u32 addr); + enum halmac_ret_status + (*halmac_check_flash)(struct halmac_adapter *adapter, u8 *fw_bin, + u32 size, u32 addr); + enum halmac_ret_status + (*halmac_cfg_edca_para)(struct halmac_adapter *adapter, + enum halmac_acq_id acq_id, + struct halmac_edca_para *param); + enum halmac_ret_status + (*halmac_pinmux_get_func)(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func, u8 *enable); + enum halmac_ret_status + (*halmac_pinmux_set_func)(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func); + enum halmac_ret_status + (*halmac_pinmux_free_func)(struct halmac_adapter *adapter, + enum halmac_gpio_func gpio_func); + enum halmac_ret_status + (*halmac_pinmux_wl_led_mode)(struct halmac_adapter *adapter, + enum halmac_wlled_mode mode); + void + (*halmac_pinmux_wl_led_sw_ctrl)(struct halmac_adapter *adapter, u8 on); + void + (*halmac_pinmux_sdio_int_polarity)(struct halmac_adapter *adapter, + u8 low_active); + enum halmac_ret_status + (*halmac_pinmux_gpio_mode)(struct halmac_adapter *adapter, u8 gpio_id, + u8 output); + enum halmac_ret_status + (*halmac_pinmux_gpio_output)(struct halmac_adapter *adapter, u8 gpio_id, + u8 high); + enum halmac_ret_status + (*halmac_pinmux_pin_status)(struct halmac_adapter *adapter, u8 pin_id, + u8 *high); + enum halmac_ret_status + (*halmac_ofld_func_cfg)(struct halmac_adapter *adapter, + struct halmac_ofld_func_info *info); + enum halmac_ret_status + (*halmac_rx_cut_amsdu_cfg)(struct halmac_adapter *adapter, + struct halmac_cut_amsdu_cfg *cfg); + enum halmac_ret_status + (*halmac_fw_snding)(struct halmac_adapter *adapter, + struct halmac_su_snding_info *su_info, + struct halmac_mu_snding_info *mu_info, u8 period); + enum halmac_ret_status + (*halmac_get_mac_addr)(struct halmac_adapter *adapter, u8 port, + union halmac_wlan_addr *addr); + enum halmac_ret_status + (*halmac_init_low_pwr)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_enter_cpu_sleep_mode)(struct halmac_adapter *adapter); + enum halmac_ret_status + (*halmac_get_cpu_mode)(struct halmac_adapter *adapter, + enum halmac_wlcpu_mode *mode); + enum halmac_ret_status + (*halmac_drv_fwctrl)(struct halmac_adapter *adapter, u8 *payload, + u32 size, u8 ack); + enum halmac_ret_status + (*halmac_read_efuse)(struct halmac_adapter *adapter, u32 offset, + u8 *value); + enum halmac_ret_status + (*halmac_write_efuse)(struct halmac_adapter *adapter, u32 offset, + u8 value); +#if HALMAC_PCIE_SUPPORT + void + (*halmac_en_ref_autok_pcie)(struct halmac_adapter *adapter, u8 en); #endif -} HALMAC_ADAPTER, *PHALMAC_ADAPTER; - - -/* Function pointer of Hal mac API */ -typedef struct _HALMAC_API { - HALMAC_RET_STATUS(*halmac_mac_power_switch)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_MAC_POWER halmac_power); - HALMAC_RET_STATUS(*halmac_download_firmware)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size); - HALMAC_RET_STATUS (*halmac_free_download_firmware)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DLFW_MEM dlfw_mem, u8 *pHamacl_fw, u32 halmac_fw_size); - HALMAC_RET_STATUS(*halmac_get_fw_version)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FW_VERSION pFw_version); - HALMAC_RET_STATUS(*halmac_cfg_mac_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address); - HALMAC_RET_STATUS(*halmac_cfg_bssid)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address); - HALMAC_RET_STATUS(*halmac_cfg_multicast_addr)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WLAN_ADDR pHal_address); - HALMAC_RET_STATUS(*halmac_pre_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_init_trx_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode); - HALMAC_RET_STATUS(*halmac_init_h2c)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_cfg_rx_aggregation)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_RXAGG_CFG phalmac_rxagg_cfg); - HALMAC_RET_STATUS(*halmac_init_protocol_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_init_edca_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_cfg_operation_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_WIRELESS_MODE wireless_mode); - HALMAC_RET_STATUS(*halmac_cfg_ch_bw)(PHALMAC_ADAPTER pHalmac_adapter, u8 channel, HALMAC_PRI_CH_IDX pri_ch_idx, HALMAC_BW bw); - HALMAC_RET_STATUS(*halmac_cfg_bw)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_BW bw); - HALMAC_RET_STATUS(*halmac_init_wmac_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_init_mac_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode); - HALMAC_RET_STATUS(*halmac_init_sdio_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_init_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_init_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_init_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_deinit_sdio_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_deinit_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_deinit_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_deinit_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_get_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); - HALMAC_RET_STATUS(*halmac_get_efuse_available_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); - HALMAC_RET_STATUS(*halmac_dump_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg); - HALMAC_RET_STATUS(*halmac_dump_efuse_map_bt)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank, u32 bt_efuse_map_size, u8 *pBT_efuse_map); - HALMAC_RET_STATUS(*halmac_write_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value); - HALMAC_RET_STATUS(*halmac_read_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue); - HALMAC_RET_STATUS(*halmac_switch_efuse_bank)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank); - HALMAC_RET_STATUS(*halmac_write_efuse_bt)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value, HALMAC_EFUSE_BANK halmac_efues_bank); - HALMAC_RET_STATUS(*halmac_get_logical_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); - HALMAC_RET_STATUS(*halmac_dump_logical_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg); - HALMAC_RET_STATUS(*halmac_write_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value); - HALMAC_RET_STATUS(*halmac_read_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue); - HALMAC_RET_STATUS(*halmac_pg_efuse_by_map)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PG_EFUSE_INFO pPg_efuse_info, HALMAC_EFUSE_READ_CFG cfg); - HALMAC_RET_STATUS(*halmac_get_c2h_info)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size); - HALMAC_RET_STATUS(*halmac_cfg_fwlps_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWLPS_OPTION pLps_option); - HALMAC_RET_STATUS(*halmac_cfg_fwips_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWIPS_OPTION pIps_option); - HALMAC_RET_STATUS(*halmac_enter_wowlan)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WOWLAN_OPTION pWowlan_option); - HALMAC_RET_STATUS(*halmac_leave_wowlan)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_enter_ps)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PS_STATE ps_state); - HALMAC_RET_STATUS(*halmac_leave_ps)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_h2c_lb)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_debug)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_cfg_parameter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PHY_PARAMETER_INFO para_info, u8 full_fifo); - HALMAC_RET_STATUS(*halmac_update_packet)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PACKET_ID pkt_id, u8 *pkt, u32 pkt_size); - HALMAC_RET_STATUS(*halmac_bcn_ie_filter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_BCN_IE_INFO pBcn_ie_info); - u8 (*halmac_reg_read_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); - HALMAC_RET_STATUS(*halmac_reg_write_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_data); - u16 (*halmac_reg_read_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); - HALMAC_RET_STATUS(*halmac_reg_write_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u16 halmac_data); - u32 (*halmac_reg_read_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); - u32 (*halmac_reg_read_indirect_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); - u8 (*halmac_reg_sdio_cmd53_read_n)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_size, u8 *halmac_data); - HALMAC_RET_STATUS(*halmac_reg_write_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data); - HALMAC_RET_STATUS(*halmac_tx_allowed_sdio)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size); - HALMAC_RET_STATUS(*halmac_set_bulkout_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 bulkout_num); - HALMAC_RET_STATUS(*halmac_get_sdio_tx_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr); - HALMAC_RET_STATUS(*halmac_get_usb_bulkout_id)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id); - HALMAC_RET_STATUS(*halmac_timer_2s)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_fill_txdesc_checksum)(PHALMAC_ADAPTER pHalmac_adapter, u8 *cur_desc); - HALMAC_RET_STATUS(*halmac_update_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type, PHALMAC_PHY_PARAMETER_INFO para_info); - HALMAC_RET_STATUS(*halmac_run_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type); - HALMAC_RET_STATUS(*halmac_cfg_drv_info)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_INFO halmac_drv_info); - HALMAC_RET_STATUS(*halmac_send_bt_coex)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBt_buf, u32 bt_size, u8 ack); - HALMAC_RET_STATUS(*halmac_verify_platform_api)(PHALMAC_ADAPTER pHalmac_adapte); - u32 (*halmac_get_fifo_size)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel); - HALMAC_RET_STATUS(*halmac_dump_fifo)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel, u32 halmac_start_addr, u32 halmac_fifo_dump_size, u8 *pFifo_map); - HALMAC_RET_STATUS(*halmac_cfg_txbf)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, HALMAC_BW bw, u8 txbf_en); - HALMAC_RET_STATUS(*halmac_cfg_mumimo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CFG_MUMIMO_PARA pCfgmu); - HALMAC_RET_STATUS(*halmac_cfg_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role, HALMAC_DATA_RATE datarate); - HALMAC_RET_STATUS(*halmac_del_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role); - HALMAC_RET_STATUS(*halmac_su_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init); - HALMAC_RET_STATUS(*halmac_su_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, u16 paid); - HALMAC_RET_STATUS(*halmac_mu_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init); - HALMAC_RET_STATUS(*halmac_mu_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init); - HALMAC_RET_STATUS(*halmac_su_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid); - HALMAC_RET_STATUS(*halmac_su_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid); - HALMAC_RET_STATUS(*halmac_mu_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_mu_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid); - HALMAC_RET_STATUS(*halmac_add_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_INFO pCh_info); - HALMAC_RET_STATUS(*halmac_add_extra_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_EXTRA_INFO pCh_extra_info); - HALMAC_RET_STATUS(*halmac_ctrl_ch_switch)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_SWITCH_OPTION pCs_option); - HALMAC_RET_STATUS (*halmac_p2pps)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_P2PPS pP2PPS); - HALMAC_RET_STATUS(*halmac_clear_ch_info)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_send_general_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_GENERAL_INFO pgGeneral_info); - HALMAC_RET_STATUS (*halmac_start_iqk)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_IQK_PARA pIqk_para); - HALMAC_RET_STATUS(*halmac_ctrl_pwr_tracking)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt); - HALMAC_RET_STATUS(*halmac_psd)(PHALMAC_ADAPTER pHalmac_adapter, u16 start_psd, u16 end_psd); - HALMAC_RET_STATUS(*halmac_cfg_tx_agg_align)(PHALMAC_ADAPTER pHalmac_adapter, u8 enable, u16 align_size); - HALMAC_RET_STATUS(*halmac_query_status)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS *pProcess_status, u8 *data, u32 *size); - HALMAC_RET_STATUS(*halmac_reset_feature)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id); - HALMAC_RET_STATUS(*halmac_check_fw_status)(PHALMAC_ADAPTER pHalmac_adapter, u8 *fw_status); - HALMAC_RET_STATUS(*halmac_dump_fw_dmem)(PHALMAC_ADAPTER pHalmac_adapter, u8 *dmem, u32 *size); - HALMAC_RET_STATUS(*halmac_cfg_max_dl_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 size); - HALMAC_RET_STATUS(*halmac_cfg_la_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_LA_MODE la_mode); - HALMAC_RET_STATUS(*halmac_cfg_rx_fifo_expanding_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode); - HALMAC_RET_STATUS(*halmac_config_security)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SECURITY_SETTING pSec_setting); - u8 (*halmac_get_used_cam_entry_num)(PHALMAC_ADAPTER pHalmac_adapter, HAL_SECURITY_TYPE sec_type); - HALMAC_RET_STATUS(*halmac_write_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_INFO pCam_entry_info); - HALMAC_RET_STATUS(*halmac_read_cam_entry)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_FORMAT pContent); - HALMAC_RET_STATUS(*halmac_clear_cam_entry)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index); - HALMAC_RET_STATUS(*halmac_get_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue); - HALMAC_RET_STATUS(*halmac_set_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue); - HALMAC_RET_STATUS(*halmac_cfg_drv_rsvd_pg_num)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_RSVD_PG_NUM pg_num); - HALMAC_RET_STATUS(*halmac_get_chip_version)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_VER *version); - HALMAC_RET_STATUS(*halmac_chk_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size); - HALMAC_RET_STATUS(*halmac_dl_drv_rsvd_page)(PHALMAC_ADAPTER pHalmac_adapter, u8 pg_offset, u8 *pHal_buf, u32 size); - HALMAC_RET_STATUS(*halmac_pcie_switch)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PCIE_CFG pcie_cfg); - HALMAC_RET_STATUS(*halmac_phy_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_INTF_PHY_PLATFORM platform); - HALMAC_RET_STATUS(*halmac_cfg_csi_rate)(PHALMAC_ADAPTER pHalmac_adapter, u8 rssi, u8 current_rate, u8 fixrate_en, u8 *new_rate); - HALMAC_RET_STATUS (*halmac_sdio_cmd53_4byte)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SDIO_CMD53_4BYTE_MODE cmd53_4byte_mode); - HALMAC_RET_STATUS (*halmac_sdio_hw_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SDIO_HW_INFO pSdio_hw_info); - HALMAC_RET_STATUS (*halmac_interface_integration_tuning)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS (*halmac_txfifo_is_empty)(PHALMAC_ADAPTER pHalmac_adapter, u32 chk_num); #if HALMAC_PLATFORM_TESTPROGRAM - HALMAC_RET_STATUS(*halmac_gen_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pPcket_buffer, PHAL_TXDESC_INFO pTxdesc_info); - HALMAC_RET_STATUS(*halmac_txdesc_parser)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pTxdesc, PHAL_TXDESC_PARSER pTxdesc_parser); - HALMAC_RET_STATUS(*halmac_rxdesc_parser)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pRxdesc, PHAL_RXDESC_PARSER pRxdesc_parser); - HALMAC_RET_STATUS(*halmac_get_txdesc_size)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_TXDESC_INFO pTxdesc_info, u32 *size); - HALMAC_RET_STATUS(*halmac_send_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHAL_TXDESC_INFO pTxdesc_Info); - HALMAC_RET_STATUS(*halmac_get_pcie_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 *size); - HALMAC_RET_STATUS(*halmac_gen_txagg_desc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pPcket_buffer, u32 agg_num); - HALMAC_RET_STATUS(*halmac_parse_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, PHAL_RXDESC_INFO pRxdesc_info, u8 **next_pkt); - u32 (*halmac_bb_reg_read)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 len); - HALMAC_RET_STATUS(*halmac_bb_reg_write)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data, u8 len); - u32 (*halmac_rf_reg_read)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_RF_REG_INFO pRf_reg_info); - HALMAC_RET_STATUS(*halmac_rf_reg_write)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_RF_REG_INFO pRf_reg_info); - HALMAC_RET_STATUS(*halmac_init_antenna_selection)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_bb_preconfig)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_init_crystal_capacity)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_trx_antenna_setting)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_himr_setting_sdio)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SDIO_HIMR_INFO sdio_himr_sdio); - HALMAC_RET_STATUS(*halmac_dump_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table); - HALMAC_RET_STATUS(*halmac_load_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u8 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table); - HALMAC_RET_STATUS(*halmac_send_beacon)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_BEACON_INFO pbeacon_info); - HALMAC_RET_STATUS(*halmac_get_management_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 *pSize, PHALMAC_MGNT_INFO pmgnt_info); - HALMAC_RET_STATUS(*halmac_send_control)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_CTRL_INFO pctrl_info); - HALMAC_RET_STATUS(*halmac_send_hiqueue)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_HIGH_QUEUE_INFO pHigh_info); - HALMAC_RET_STATUS(*halmac_run_pwrseq)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PWR_SEQ_ID seq); - HALMAC_RET_STATUS(*halmac_media_status_rpt)(PHALMAC_ADAPTER pHalmac_adapter, u8 op_mode, u8 mac_id_ind, u8 mac_id, u8 mac_id_end); - HALMAC_RET_STATUS(*halmac_stop_beacon)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_check_trx_status)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_set_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 agg_num); - HALMAC_RET_STATUS(*halmac_timer_10ms)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_download_firmware_fpag)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 iram_address); - HALMAC_RET_STATUS(*halmac_download_rom_fpga)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address); - HALMAC_RET_STATUS(*halmac_download_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address); - HALMAC_RET_STATUS(*halmac_erase_flash)(PHALMAC_ADAPTER pHalmac_adapter); - HALMAC_RET_STATUS(*halmac_check_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size); - HALMAC_RET_STATUS(*halmac_send_nlo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_NLO_CFG pNlo_cfg); - HALMAC_RET_STATUS(*halmac_get_chip_type)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CHIP_TYPE pChip_type); - u32 (*halmac_get_rx_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u32 pkt_size, u8 *pPkt_buff); - u8 (*halmac_check_rx_scsi_resp)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pRxdesc, PHAL_RXDESC_PARSER pRxdesc_parser); - VOID (*halmac_get_hcpwm)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHcpwm); - VOID (*halmac_get_hcpwm2)(PHALMAC_ADAPTER pHalmac_adapter, u16 *pHcpwm2); - VOID (*halmac_set_hrpwm)(PHALMAC_ADAPTER pHalmac_adapter, u8 hrpwm); - VOID (*halmac_set_hrpwm2)(PHALMAC_ADAPTER pHalmac_adapter, u16 hrpwm2); + struct halmisc_api *halmisc_api; #endif -} HALMAC_API, *PHALMAC_API; - -#define HALMAC_GET_API(phalmac_adapter) ((PHALMAC_API)phalmac_adapter->pHalmac_api) - -static HALMAC_INLINE HALMAC_RET_STATUS -halmac_adapter_validate( - PHALMAC_ADAPTER pHalmac_adapter -) -{ - if ((NULL == pHalmac_adapter) || (pHalmac_adapter->pHalAdapter_backup != pHalmac_adapter)) - return HALMAC_RET_ADAPTER_INVALID; - - return HALMAC_RET_SUCCESS; -} +}; -static HALMAC_INLINE HALMAC_RET_STATUS -halmac_api_validate( - PHALMAC_ADAPTER pHalmac_adapter -) -{ - if (HALMAC_API_STATE_INIT != pHalmac_adapter->halmac_state.api_state) - return HALMAC_RET_API_INVALID; - - return HALMAC_RET_SUCCESS; -} +#define HALMAC_GET_API(halmac_adapter) \ + ((struct halmac_api *)halmac_adapter->halmac_api) -static HALMAC_INLINE HALMAC_RET_STATUS -halmac_fw_validate( - PHALMAC_ADAPTER pHalmac_adapter -) +static HALMAC_INLINE enum halmac_ret_status +halmac_fw_validate(struct halmac_adapter *adapter) { - if (HALMAC_DLFW_DONE != pHalmac_adapter->halmac_state.dlfw_state && HALMAC_GEN_INFO_SENT != pHalmac_adapter->halmac_state.dlfw_state) + if (adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE && + adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) return HALMAC_RET_NO_DLFW; return HALMAC_RET_SUCCESS; diff --git a/hal/halmac/halmac_usb_reg.h b/hal/halmac/halmac_usb_reg.h index 1ff9bde..b856c55 100644 --- a/hal/halmac/halmac_usb_reg.h +++ b/hal/halmac/halmac_usb_reg.h @@ -1,8 +1,19 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + ******************************************************************************/ + #ifndef __HALMAC_USB_REG_H__ #define __HALMAC_USB_REG_H__ - - - - #endif/* __HALMAC_USB_REG_H__ */ diff --git a/hal/led/hal_led.c b/hal/led/hal_led.c new file mode 100644 index 0000000..95d3daa --- /dev/null +++ b/hal/led/hal_led.c @@ -0,0 +1,254 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include +#include + +#ifdef CONFIG_RTW_LED +void dump_led_config(void *sel, _adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct led_priv *ledpriv = adapter_to_led(adapter); + int i; + + RTW_PRINT_SEL(sel, "strategy:%u\n", ledpriv->LedStrategy); +#ifdef CONFIG_RTW_SW_LED + RTW_PRINT_SEL(sel, "bRegUseLed:%u\n", ledpriv->bRegUseLed); + RTW_PRINT_SEL(sel, "iface_en_mask:0x%02X\n", ledpriv->iface_en_mask); + for (i = 0; i < dvobj->iface_nums; i++) + RTW_PRINT_SEL(sel, "ctl_en_mask[%d]:0x%08X\n", i, ledpriv->ctl_en_mask[i]); +#endif +} + +void rtw_led_set_strategy(_adapter *adapter, u8 strategy) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + _adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter); + +#ifndef CONFIG_RTW_SW_LED + if (IS_SW_LED_STRATEGY(strategy)) { + RTW_WARN("CONFIG_RTW_SW_LED is not defined\n"); + return; + } +#endif + +#ifdef CONFIG_RTW_SW_LED + if (!ledpriv->bRegUseLed) + return; +#endif + + if (ledpriv->LedStrategy == strategy) + return; + + if (IS_HW_LED_STRATEGY(strategy) || IS_HW_LED_STRATEGY(ledpriv->LedStrategy)) { + RTW_WARN("switching on/off HW_LED strategy is not supported\n"); + return; + } + + ledpriv->LedStrategy = strategy; + +#ifdef CONFIG_RTW_SW_LED + rtw_hal_sw_led_deinit(pri_adapter); +#endif + + rtw_led_control(pri_adapter, RTW_LED_OFF); +} + +#ifdef CONFIG_RTW_SW_LED +#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY +void rtw_sw_led_blink_uc_trx_only(LED_DATA *led) +{ + _adapter *adapter = led->padapter; + BOOLEAN bStopBlinking = _FALSE; + + if (led->BlinkingLedState == RTW_LED_ON) + SwLedOn(adapter, led); + else + SwLedOff(adapter, led); + + switch (led->CurrLedState) { + case RTW_LED_ON: + SwLedOn(adapter, led); + break; + + case RTW_LED_OFF: + SwLedOff(adapter, led); + break; + + case LED_BLINK_TXRX: + led->BlinkTimes--; + if (led->BlinkTimes == 0) + bStopBlinking = _TRUE; + + if (adapter_to_pwrctl(adapter)->rf_pwrstate != rf_on + && adapter_to_pwrctl(adapter)->rfoff_reason > RF_CHANGE_BY_PS + ) { + SwLedOff(adapter, led); + led->bLedBlinkInProgress = _FALSE; + } else { + if (led->bLedOn) + led->BlinkingLedState = RTW_LED_OFF; + else + led->BlinkingLedState = RTW_LED_ON; + + if (bStopBlinking) { + led->CurrLedState = RTW_LED_OFF; + led->bLedBlinkInProgress = _FALSE; + } + _set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + break; + + default: + break; + } +} + +void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + LED_DATA *led = &(ledpriv->SwLed0); + LED_DATA *led1 = &(ledpriv->SwLed1); + LED_DATA *led2 = &(ledpriv->SwLed2); + + switch (ctl) { + case LED_CTL_UC_TX: + case LED_CTL_UC_RX: + if (led->bLedBlinkInProgress == _FALSE) { + led->bLedBlinkInProgress = _TRUE; + led->CurrLedState = LED_BLINK_TXRX; + led->BlinkTimes = 2; + if (led->bLedOn) + led->BlinkingLedState = RTW_LED_OFF; + else + led->BlinkingLedState = RTW_LED_ON; + _set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + break; + + case LED_CTL_POWER_OFF: + led->CurrLedState = RTW_LED_OFF; + led->BlinkingLedState = RTW_LED_OFF; + + if (led->bLedBlinkInProgress) { + _cancel_timer_ex(&(led->BlinkTimer)); + led->bLedBlinkInProgress = _FALSE; + } + + SwLedOff(adapter, led); + SwLedOff(adapter, led1); + SwLedOff(adapter, led2); + break; + + default: + break; + } +} +#endif /* CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY */ + +void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + + if (ledpriv->LedControlHandler) { + #if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + if (ledpriv->LedStrategy != SW_LED_MODE_UC_TRX_ONLY) { + if (ctl == LED_CTL_UC_TX || ctl == LED_CTL_BMC_TX) { + if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_TX)) + ctl = LED_CTL_TX; /* transform specific TX ctl to general TX ctl */ + } else if (ctl == LED_CTL_UC_RX || ctl == LED_CTL_BMC_RX) { + if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_RX)) + ctl = LED_CTL_RX; /* transform specific RX ctl to general RX ctl */ + } + } + #endif + + if ((ledpriv->iface_en_mask & BIT(adapter->iface_id)) + && (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(ctl))) + ledpriv->LedControlHandler(adapter, ctl); + } +} + +void rtw_led_tx_control(_adapter *adapter, const u8 *da) +{ +#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + if (IS_MCAST(da)) + rtw_led_control(adapter, LED_CTL_BMC_TX); + else + rtw_led_control(adapter, LED_CTL_UC_TX); +#else + rtw_led_control(adapter, LED_CTL_TX); +#endif +} + +void rtw_led_rx_control(_adapter *adapter, const u8 *da) +{ +#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + if (IS_MCAST(da)) + rtw_led_control(adapter, LED_CTL_BMC_RX); + else + rtw_led_control(adapter, LED_CTL_UC_RX); +#else + rtw_led_control(adapter, LED_CTL_RX); +#endif +} + +void rtw_led_set_iface_en(_adapter *adapter, u8 en) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + + if (en) + ledpriv->iface_en_mask |= BIT(adapter->iface_id); + else + ledpriv->iface_en_mask &= ~BIT(adapter->iface_id); +} + +void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + + ledpriv->iface_en_mask = mask; +} + +void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask) +{ + struct led_priv *ledpriv = adapter_to_led(adapter); + +#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + if (ctl_mask & BIT(LED_CTL_TX)) + ctl_mask |= BIT(LED_CTL_UC_TX) | BIT(LED_CTL_BMC_TX); + if (ctl_mask & BIT(LED_CTL_RX)) + ctl_mask |= BIT(LED_CTL_UC_RX) | BIT(LED_CTL_BMC_RX); +#endif + + ledpriv->ctl_en_mask[adapter->iface_id] = ctl_mask; +} + +void rtw_led_set_ctl_en_mask_primary(_adapter *adapter) +{ + rtw_led_set_ctl_en_mask(adapter, 0xFFFFFFFF); +} + +void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter) +{ + rtw_led_set_ctl_en_mask(adapter + , BIT(LED_CTL_POWER_ON) | BIT(LED_CTL_POWER_OFF) + | BIT(LED_CTL_TX) | BIT(LED_CTL_RX) + ); +} +#endif /* CONFIG_RTW_SW_LED */ + +#endif /* CONFIG_RTW_LED */ + diff --git a/hal/led/hal_pci_led.c b/hal/led/hal_pci_led.c index 3fccb14..72d996e 100644 --- a/hal/led/hal_pci_led.c +++ b/hal/led/hal_pci_led.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,15 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #include +#ifdef CONFIG_RTW_SW_LED /* * Description: @@ -724,7 +720,7 @@ SwLedBlink12( void BlinkHandler(PLED_PCIE pLed) { _adapter *padapter = pLed->padapter; - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); if (RTW_CANNOT_RUN(padapter)) return; @@ -736,6 +732,12 @@ void BlinkHandler(PLED_PCIE pLed) return; switch (ledpriv->LedStrategy) { + #if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + case SW_LED_MODE_UC_TRX_ONLY: + rtw_sw_led_blink_uc_trx_only(pLed); + break; + #endif + case SW_LED_MODE1: /* SwLedBlink(pLed); */ break; @@ -785,9 +787,9 @@ void BlinkHandler(PLED_PCIE pLed) * Callback function of LED BlinkTimer, * it just schedules to corresponding BlinkWorkItem/led_blink_hdl * */ -void BlinkTimerCallback(struct timer_list *t) +void BlinkTimerCallback(void *data) { - PLED_PCIE pLed = from_timer(pLed, t, BlinkTimer); + PLED_PCIE pLed = (PLED_PCIE)data; _adapter *padapter = pLed->padapter; /* RTW_INFO("%s\n", __FUNCTION__); */ @@ -801,7 +803,7 @@ void BlinkTimerCallback(struct timer_list *t) return; } -#ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD +#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD rtw_led_blink_cmd(padapter, pLed); #else BlinkHandler(pLed); @@ -817,7 +819,7 @@ SwLedControlMode0( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_PCIE pLed0 = &(ledpriv->SwLed0); PLED_PCIE pLed1 = &(ledpriv->SwLed1); @@ -875,7 +877,7 @@ SwLedControlMode1( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); PLED_PCIE pLed = &(ledpriv->SwLed1); @@ -973,7 +975,7 @@ SwLedControlMode2( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); PLED_PCIE pLed0 = &(ledpriv->SwLed0); PLED_PCIE pLed1 = &(ledpriv->SwLed1); @@ -1065,7 +1067,7 @@ SwLedControlMode3( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_PCIE pLed0 = &(ledpriv->SwLed0); PLED_PCIE pLed1 = &(ledpriv->SwLed1); @@ -1123,7 +1125,7 @@ SwLedControlMode4( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_PCIE pLed0 = &(ledpriv->SwLed0); PLED_PCIE pLed1 = &(ledpriv->SwLed1); @@ -1181,7 +1183,7 @@ SwLedControlMode5( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_PCIE pLed0 = &(ledpriv->SwLed0); PLED_PCIE pLed1 = &(ledpriv->SwLed1); /* Decide led state */ @@ -1270,7 +1272,7 @@ SwLedControlMode6( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_PCIE pLed0 = &(ledpriv->SwLed0); PLED_PCIE pLed1 = &(ledpriv->SwLed1); @@ -1343,7 +1345,7 @@ SwLedControlMode7( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_PCIE pLed0 = &(ledpriv->SwLed0); switch (LedAction) { @@ -1369,7 +1371,7 @@ SwLedControlMode8( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_PCIE pLed = &(ledpriv->SwLed0); struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); @@ -1424,7 +1426,7 @@ SwLedControlMode9( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_PCIE pLed = &(ledpriv->SwLed0); struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); @@ -1537,7 +1539,7 @@ SwLedControlMode10( ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_PCIE pLed0 = &(ledpriv->SwLed0); PLED_PCIE pLed1 = &(ledpriv->SwLed1); struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); @@ -1706,7 +1708,7 @@ SwLedControlMode11( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_PCIE pLed = &(ledpriv->SwLed0); /* Decide led state */ @@ -1798,7 +1800,7 @@ SwLedControlMode12( IN LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(Adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(Adapter); PLED_PCIE pLed = &(ledpriv->SwLed0); struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); LED_STATE LedState = LED_UNKNOWN; @@ -1939,7 +1941,7 @@ LedControlPCIE( LED_CTL_MODE LedAction ) { - struct led_priv *ledpriv = &(padapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(padapter); #if (MP_DRIVER == 1) if (padapter->registrypriv.mp_mode == 1) @@ -1952,12 +1954,6 @@ LedControlPCIE( /* if(priv->bInHctTest) */ /* return; */ -#ifdef CONFIG_CONCURRENT_MODE - /* Only do led action for PRIMARY_ADAPTER */ - if (padapter->adapter_type != PRIMARY_ADAPTER) - return; -#endif - if ((adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) && (LedAction == LED_CTL_TX || LedAction == LED_CTL_RX || @@ -1970,6 +1966,12 @@ LedControlPCIE( } switch (ledpriv->LedStrategy) { + #if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY + case SW_LED_MODE_UC_TRX_ONLY: + rtw_sw_led_ctl_mode_uc_trx_only(padapter, LedAction); + break; + #endif + case SW_LED_MODE0: /* SwLedControlMode0(padapter, LedAction); */ break; @@ -2051,8 +2053,8 @@ gen_RefreshLedState( { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter); - struct led_priv *pledpriv = &(Adapter->ledpriv); - PLED_PCIE pLed0 = &(Adapter->ledpriv.SwLed0); + struct led_priv *pledpriv = adapter_to_led(Adapter); + PLED_PCIE pLed0 = &(pledpriv->SwLed0); RTW_INFO("gen_RefreshLedState:() pwrctrlpriv->rfoff_reason=%x\n", pwrctrlpriv->rfoff_reason); @@ -2148,7 +2150,7 @@ InitLed( ResetLedStatus(pLed); - rtw_init_timer(&(pLed->BlinkTimer), padapter, BlinkTimerCallback); + rtw_init_timer(&(pLed->BlinkTimer), padapter, BlinkTimerCallback, pLed); } @@ -2164,3 +2166,4 @@ DeInitLed( _cancel_timer_ex(&(pLed->BlinkTimer)); ResetLedStatus(pLed); } +#endif diff --git a/hal/phydm/ap_makefile.mk b/hal/phydm/ap_makefile.mk new file mode 100644 index 0000000..6206183 --- /dev/null +++ b/hal/phydm/ap_makefile.mk @@ -0,0 +1,174 @@ + +_PHYDM_FILES :=\ + phydm/phydm.o \ + phydm/phydm_dig.o\ + phydm/phydm_antdiv.o\ + phydm/phydm_soml.o\ + phydm/phydm_smt_ant.o\ + phydm/phydm_pathdiv.o\ + phydm/phydm_rainfo.o\ + phydm/phydm_dynamictxpower.o\ + phydm/phydm_adaptivity.o\ + phydm/phydm_debug.o\ + phydm/phydm_interface.o\ + phydm/phydm_phystatus.o\ + phydm/phydm_hwconfig.o\ + phydm/phydm_dfs.o\ + phydm/phydm_cfotracking.o\ + phydm/phydm_adc_sampling.o\ + phydm/phydm_ccx.o\ + phydm/phydm_primary_cca.o\ + phydm/phydm_cck_pd.o\ + phydm/phydm_rssi_monitor.o\ + phydm/phydm_auto_dbg.o\ + phydm/phydm_math_lib.o\ + phydm/phydm_noisemonitor.o\ + phydm/phydm_api.o\ + phydm/phydm_pow_train.o\ + phydm/phydm_lna_sat.o\ + phydm/phydm_pmac_tx_setting.o\ + phydm/phydm_mp.o\ + phydm/txbf/phydm_hal_txbf_api.o\ + EdcaTurboCheck.o\ + phydm/halrf/halrf.o\ + phydm/halrf/halrf_debug.o\ + phydm/halrf/halphyrf_ap.o\ + phydm/halrf/halrf_powertracking_ap.o\ + phydm/halrf/halrf_powertracking.o\ + phydm/halrf/halrf_kfree.o + +ifeq ($(CONFIG_RTL_88E_SUPPORT),y) + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8188e/halhwimg8188e_bb.o\ + phydm/rtl8188e/halhwimg8188e_mac.o\ + phydm/rtl8188e/halhwimg8188e_rf.o\ + phydm/rtl8188e/phydm_regconfig8188e.o\ + phydm/rtl8188e/hal8188erateadaptive.o\ + phydm/rtl8188e/phydm_rtl8188e.o\ + phydm/halrf/rtl8188e/halrf_8188e_ap.o + endif +endif + +ifeq ($(CONFIG_RTL_8812_SUPPORT),y) + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o + endif + _PHYDM_FILES += phydm/rtl8812a/phydm_rtl8812a.o +endif + +ifeq ($(CONFIG_WLAN_HAL_8881A),y) + _PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o +endif + +ifeq ($(CONFIG_WLAN_HAL_8192EE),y) + _PHYDM_FILES += \ + phydm/halrf/rtl8192e/halrf_8192e_ap.o\ + phydm/rtl8192e/phydm_rtl8192e.o +endif + +ifeq ($(CONFIG_WLAN_HAL_8814AE),y) + rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o + rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + rtl8192cd-objs += \ + phydm/rtl8814a/halhwimg8814a_bb.o\ + phydm/rtl8814a/halhwimg8814a_mac.o\ + phydm/rtl8814a/halhwimg8814a_rf.o\ + phydm/rtl8814a/phydm_regconfig8814a.o\ + phydm/rtl8814a/phydm_rtl8814a.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8822BE),y) + _PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o + _PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8822b/halhwimg8822b_bb.o\ + phydm/rtl8822b/halhwimg8822b_mac.o\ + phydm/rtl8822b/halhwimg8822b_rf.o\ + phydm/rtl8822b/phydm_regconfig8822b.o\ + phydm/rtl8822b/phydm_hal_api8822b.o\ + phydm/rtl8822b/phydm_rtl8822b.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8821CE),y) + _PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o + _PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8821c/halhwimg8821c_bb.o\ + phydm/rtl8821c/halhwimg8821c_mac.o\ + phydm/rtl8821c/halhwimg8821c_rf.o\ + phydm/rtl8821c/phydm_regconfig8821c.o\ + phydm/rtl8821c/phydm_hal_api8821c.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8197F),y) + _PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o + _PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o + _PHYDM_FILES += phydm/halrf/rtl8197f/halrf_dpk_8197f.o + _PHYDM_FILES += efuse_97f/efuse.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8197f/halhwimg8197f_bb.o\ + phydm/rtl8197f/halhwimg8197f_mac.o\ + phydm/rtl8197f/halhwimg8197f_rf.o\ + phydm/rtl8197f/phydm_hal_api8197f.o\ + phydm/rtl8197f/phydm_regconfig8197f.o\ + phydm/rtl8197f/phydm_rtl8197f.o + endif +endif + + +ifeq ($(CONFIG_WLAN_HAL_8192FE),y) + _PHYDM_FILES += phydm/halrf/rtl8192f/halrf_8192f.o + _PHYDM_FILES += phydm/halrf/rtl8192f/halrf_dpk_8192f.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8192f/halhwimg8192f_bb.o\ + phydm/rtl8192f/halhwimg8192f_mac.o\ + phydm/rtl8192f/halhwimg8192f_rf.o\ + phydm/rtl8192f/phydm_hal_api8192f.o\ + phydm/rtl8192f/phydm_regconfig8192f.o\ + phydm/rtl8192f/phydm_rtl8192f.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8198F),y) + _PHYDM_FILES += phydm/halrf/rtl8198f/halrf_8198f.o + _PHYDM_FILES += phydm/halrf/rtl8198f/halrf_iqk_8198f.o + _PHYDM_FILES += phydm/halrf/rtl8198f/halrf_dpk_8198f.o + _PHYDM_FILES += phydm/halrf/rtl8198f/halrf_rfk_init_8198f.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8198f/phydm_hal_api8198f.o\ + phydm/rtl8198f/halhwimg8198f_bb.o\ + phydm/rtl8198f/halhwimg8198f_mac.o\ + phydm/rtl8198f/halhwimg8198f_rf.o\ + phydm/rtl8198f/phydm_regconfig8198f.o \ + phydm/halrf/rtl8198f/halrf_8198f.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8814B),y) + _PHYDM_FILES += phydm/halrf/rtl8814b/halrf_8814b.o + _PHYDM_FILES += phydm/halrf/rtl8814b/halrf_iqk_8814b.o + _PHYDM_FILES += phydm/halrf/rtl8814b/halrf_dpk_8814b.o + _PHYDM_FILES += phydm/halrf/rtl8814b/halrf_rfk_init_8814b.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8814b/phydm_hal_api8814b.o\ + phydm/rtl8814b/halhwimg8814b_bb.o\ + phydm/rtl8814b/halhwimg8814b_mac.o\ + phydm/rtl8814b/halhwimg8814b_rf.o\ + phydm/rtl8814b/phydm_regconfig8814b.o \ + phydm/halrf/rtl8814b/halrf_8814b.o + endif +endif + + + diff --git a/hal/phydm/halhwimg.h b/hal/phydm/halhwimg.h index 14a9f63..6d658b3 100644 --- a/hal/phydm/halhwimg.h +++ b/hal/phydm/halhwimg.h @@ -1,77 +1,91 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #pragma once #ifndef __INC_HW_IMG_H #define __INC_HW_IMG_H -/* +/*@ * 2011/03/15 MH Add for different IC HW image file selection. code size consideration. * */ #if RT_PLATFORM == PLATFORM_LINUX #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - /* For 92C */ + /* @For 92C */ #define RTL8192CE_HWIMG_SUPPORT 1 #define RTL8192CE_TEST_HWIMG_SUPPORT 0 #define RTL8192CU_HWIMG_SUPPORT 0 #define RTL8192CU_TEST_HWIMG_SUPPORT 0 - /* For 92D */ + /* @For 92D */ #define RTL8192DE_HWIMG_SUPPORT 1 #define RTL8192DE_TEST_HWIMG_SUPPORT 0 #define RTL8192DU_HWIMG_SUPPORT 0 #define RTL8192DU_TEST_HWIMG_SUPPORT 0 - /* For 8723 */ + /* @For 8723 */ #define RTL8723E_HWIMG_SUPPORT 1 #define RTL8723U_HWIMG_SUPPORT 0 #define RTL8723S_HWIMG_SUPPORT 0 - /* For 88E */ + /* @For 88E */ #define RTL8188EE_HWIMG_SUPPORT 0 #define RTL8188EU_HWIMG_SUPPORT 0 #define RTL8188ES_HWIMG_SUPPORT 0 #elif (DEV_BUS_TYPE == RT_USB_INTERFACE) - /* For 92C */ + /* @For 92C */ #define RTL8192CE_HWIMG_SUPPORT 0 #define RTL8192CE_TEST_HWIMG_SUPPORT 0 #define RTL8192CU_HWIMG_SUPPORT 1 #define RTL8192CU_TEST_HWIMG_SUPPORT 0 - /* For 92D */ + /* @For 92D */ #define RTL8192DE_HWIMG_SUPPORT 0 #define RTL8192DE_TEST_HWIMG_SUPPORT 0 #define RTL8192DU_HWIMG_SUPPORT 1 #define RTL8192DU_TEST_HWIMG_SUPPORT 0 - /* For 8723 */ + /* @For 8723 */ #define RTL8723E_HWIMG_SUPPORT 0 #define RTL8723U_HWIMG_SUPPORT 1 #define RTL8723S_HWIMG_SUPPORT 0 - /* For 88E */ + /* @For 88E */ #define RTL8188EE_HWIMG_SUPPORT 0 #define RTL8188EU_HWIMG_SUPPORT 0 #define RTL8188ES_HWIMG_SUPPORT 0 #elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE) - /* For 92C */ + /* @For 92C */ #define RTL8192CE_HWIMG_SUPPORT 0 #define RTL8192CE_TEST_HWIMG_SUPPORT 0 #define RTL8192CU_HWIMG_SUPPORT 1 #define RTL8192CU_TEST_HWIMG_SUPPORT 0 - /* For 92D */ + /* @For 92D */ #define RTL8192DE_HWIMG_SUPPORT 0 #define RTL8192DE_TEST_HWIMG_SUPPORT 0 #define RTL8192DU_HWIMG_SUPPORT 1 #define RTL8192DU_TEST_HWIMG_SUPPORT 0 - /* For 8723 */ + /* @For 8723 */ #define RTL8723E_HWIMG_SUPPORT 0 #define RTL8723U_HWIMG_SUPPORT 0 #define RTL8723S_HWIMG_SUPPORT 1 - /* For 88E */ + /* @For 88E */ #define RTL8188EE_HWIMG_SUPPORT 0 #define RTL8188EU_HWIMG_SUPPORT 0 #define RTL8188ES_HWIMG_SUPPORT 0 @@ -79,40 +93,40 @@ #else /* PLATFORM_WINDOWS & MacOSX */ - /* For 92C */ + /* @For 92C */ #define RTL8192CE_HWIMG_SUPPORT 1 #define RTL8192CE_TEST_HWIMG_SUPPORT 1 #define RTL8192CU_HWIMG_SUPPORT 1 #define RTL8192CU_TEST_HWIMG_SUPPORT 1 - /* For 92D */ + /* @For 92D */ #define RTL8192DE_HWIMG_SUPPORT 1 #define RTL8192DE_TEST_HWIMG_SUPPORT 1 #define RTL8192DU_HWIMG_SUPPORT 1 #define RTL8192DU_TEST_HWIMG_SUPPORT 1 #if defined(UNDER_CE) - /* For 8723 */ + /* @For 8723 */ #define RTL8723E_HWIMG_SUPPORT 0 #define RTL8723U_HWIMG_SUPPORT 0 #define RTL8723S_HWIMG_SUPPORT 1 - /* For 88E */ + /* @For 88E */ #define RTL8188EE_HWIMG_SUPPORT 0 #define RTL8188EU_HWIMG_SUPPORT 0 #define RTL8188ES_HWIMG_SUPPORT 0 #else - /* For 8723 */ + /* @For 8723 */ #define RTL8723E_HWIMG_SUPPORT 1 - /* #define RTL_8723E_TEST_HWIMG_SUPPORT 1 */ + /* @#define RTL_8723E_TEST_HWIMG_SUPPORT 1 */ #define RTL8723U_HWIMG_SUPPORT 1 - /* #define RTL_8723U_TEST_HWIMG_SUPPORT 1 */ + /* @#define RTL_8723U_TEST_HWIMG_SUPPORT 1 */ #define RTL8723S_HWIMG_SUPPORT 1 - /* #define RTL_8723S_TEST_HWIMG_SUPPORT 1 */ + /* @#define RTL_8723S_TEST_HWIMG_SUPPORT 1 */ - /* For 88E */ + /* @For 88E */ #define RTL8188EE_HWIMG_SUPPORT 1 #define RTL8188EU_HWIMG_SUPPORT 1 #define RTL8188ES_HWIMG_SUPPORT 1 @@ -120,4 +134,4 @@ #endif -#endif /* __INC_HW_IMG_H */ +#endif /* @__INC_HW_IMG_H */ diff --git a/hal/phydm/halrf/halphyrf_ap.c b/hal/phydm/halrf/halphyrf_ap.c new file mode 100644 index 0000000..1d19b91 --- /dev/null +++ b/hal/phydm/halrf/halphyrf_ap.c @@ -0,0 +1,1340 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifndef index_mapping_NUM_88E + #define index_mapping_NUM_88E 15 +#endif + +/* #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) */ + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \ + do {\ + for (_offset = 0; _offset < _size; _offset++) { \ + \ + if (_delta_thermal < thermal_threshold[_direction][_offset]) { \ + \ + if (_offset != 0)\ + _offset--;\ + break;\ + } \ + } \ + if (_offset >= _size)\ + _offset = _size-1;\ + } while (0) + + +void configure_txpower_track( + void *dm_void, + struct txpwrtrack_cfg *config +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if RTL8812A_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* if (IS_HARDWARE_TYPE_8812(dm->adapter)) */ + if (dm->support_ic_type == ODM_RTL8812) + configure_txpower_track_8812a(config); + /* else */ +#endif +#endif + +#if RTL8814A_SUPPORT + if (dm->support_ic_type == ODM_RTL8814A) + configure_txpower_track_8814a(config); +#endif + + +#if RTL8188E_SUPPORT + if (dm->support_ic_type == ODM_RTL8188E) + configure_txpower_track_8188e(config); +#endif + +#if RTL8197F_SUPPORT + if (dm->support_ic_type == ODM_RTL8197F) + configure_txpower_track_8197f(config); +#endif + +#if RTL8822B_SUPPORT + if (dm->support_ic_type == ODM_RTL8822B) + configure_txpower_track_8822b(config); +#endif + +#if RTL8192F_SUPPORT + if (dm->support_ic_type == ODM_RTL8192F) + configure_txpower_track_8192f(config); +#endif + +#if RTL8198F_SUPPORT + if (dm->support_ic_type == ODM_RTL8198F) + configure_txpower_track_8198f(config); +#endif + +} + +#if (RTL8192E_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_92e( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 thermal_value = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode; + u8 thermal_value_avg_count = 0; + u8 OFDM_min_index = 10; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur */ + s8 OFDM_index[2], index ; + u32 thermal_value_avg = 0, reg0x18; + u32 i = 0, j = 0, rf; + s32 value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y; + struct rtl8192cd_priv *priv = dm->priv; + + rf_mimo_mode = dm->rf_type; + /* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode); */ + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == false) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + thermal_value = (unsigned char)odm_get_rf_reg(dm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther); + + + switch (rf_mimo_mode) { + case RF_1T1R: + rf = 1; + break; + case RF_2T2R: + rf = 2; + break; + default: + rf = 2; + break; + } + + /* Query OFDM path A default setting Bit[31:21] */ + ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D); + for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { + if (ele_D == (ofdm_swing_table_92e[i] >> 22)) { + OFDM_index[0] = (unsigned char)i; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]); + break; + } + } + + /* Query OFDM path B default setting */ + if (rf_mimo_mode == RF_2T2R) { + ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKOFDM_D); + for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { + if (ele_D == (ofdm_swing_table_92e[i] >> 22)) { + OFDM_index[1] = (unsigned char)i; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]); + break; + } + } + } + + /* calculate average thermal meter */ + { + priv->pshare->thermal_value_avg_88xx[priv->pshare->thermal_value_avg_index_88xx] = thermal_value; + priv->pshare->thermal_value_avg_index_88xx++; + if (priv->pshare->thermal_value_avg_index_88xx == AVG_THERMAL_NUM_88XX) + priv->pshare->thermal_value_avg_index_88xx = 0; + + for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) { + if (priv->pshare->thermal_value_avg_88xx[i]) { + thermal_value_avg += priv->pshare->thermal_value_avg_88xx[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { + thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value); + } + } + + /* Initialize */ + if (!priv->pshare->thermal_value) { + priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther; + priv->pshare->thermal_value_iqk = thermal_value; + priv->pshare->thermal_value_lck = thermal_value; + } + + if (thermal_value != priv->pshare->thermal_value) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n"); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther); + + delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); + delta_IQK = RTL_ABS(thermal_value, priv->pshare->thermal_value_iqk); + delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck); + is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0); + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)); + + if (is_decrease) { + for (i = 0; i < rf; i++) { + OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); + OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)); + CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); + CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1)); + } + } else { + for (i = 0; i < rf; i++) { + OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); + OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)); + CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); + CCK_index = ((CCK_index < 0) ? 0 : CCK_index); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1)); + } + } + } +#endif /* CFG_TRACKING_TABLE_FILE */ + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]); + + /* Adujst OFDM Ant_A according to IQK result */ + ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22; + X = priv->pshare->rege94; + Y = priv->pshare->rege9c; + + if (X != 0) { + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D) >> 8) & 0x000003FF; + + /* new element C = element D x Y */ + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D) >> 8) & 0x000003FF; + + /* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */ + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32); + + value32 = ((X * ele_D) >> 7) & 0x01; + phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), value32); + } else { + phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]); + phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00); + phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), 0x00); + } + + set_CCK_swing_index(priv, CCK_index); + + if (rf == 2) { + ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22; + X = priv->pshare->regeb4; + Y = priv->pshare->regebc; + + if (X != 0) { + if ((X & 0x00000200) != 0) /* consider minus */ + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D) >> 8) & 0x000003FF; + + /* new element C = element D x Y */ + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D) >> 8) & 0x00003FF; + + /* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */ + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32); + + value32 = ((X * ele_D) >> 7) & 0x01; + phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), value32); + } else { + phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]); + phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00); + phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), 0x00); + } + + } + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD)); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD)); + + if ((delta_IQK > 3) && (!iqk_info->rfk_forbidden)) { + priv->pshare->thermal_value_iqk = thermal_value; +#ifdef MP_TEST +#endif if (!(*(dm->mp_mode) && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET)))) + + halrf_iqk_trigger(dm, false); + } + + if ((delta_LCK > 8) && (!iqk_info->rfk_forbidden)) { + RTL_W8(0x522, 0xff); + reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1); + phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1); + phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1); + delay_ms(1); + phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0); + phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18); + RTL_W8(0x522, 0x0); + priv->pshare->thermal_value_lck = thermal_value; + } + } + + /* update thermal meter value */ + priv->pshare->thermal_value = thermal_value; + for (i = 0 ; i < rf ; i++) + priv->pshare->OFDM_index[i] = OFDM_index[i]; + priv->pshare->CCK_index = CCK_index; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__); +} +#endif + + + +#if (RTL8197F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\ + RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_jaguar_series3( + void *dm_void +) +{ +#if 1 + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase; + u8 thermal_value_avg_count = 0, p = 0, i = 0; + u32 thermal_value_avg = 0; + struct rtl8192cd_priv *priv = dm->priv; + struct txpwrtrack_cfg c; + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + struct dm_iqk_info *iqk_info = &dm->IQK_info; + struct _hal_rf_ *rf = &dm->rf_table; + /*The following tables decide the final index of OFDM/CCK swing table.*/ + u8 *pwrtrk_tab_up_a = NULL, *pwrtrk_tab_down_a = NULL; + u8 *pwrtrk_tab_up_b = NULL, *pwrtrk_tab_down_b = NULL; + u8 *pwrtrk_tab_up_cck_a = NULL, *pwrtrk_tab_down_cck_a = NULL; + u8 *pwrtrk_tab_up_cck_b = NULL, *pwrtrk_tab_down_cck_b = NULL; + /*for 8814 add by Yu Chen*/ + u8 *pwrtrk_tab_up_c = NULL, *pwrtrk_tab_down_c = NULL; + u8 *pwrtrk_tab_up_d = NULL, *pwrtrk_tab_down_d = NULL; + u8 *pwrtrk_tab_up_cck_c = NULL, *pwrtrk_tab_down_cck_c = NULL; + u8 *pwrtrk_tab_up_cck_d = NULL, *pwrtrk_tab_down_cck_d = NULL; + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == false) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + configure_txpower_track(dm, &c); + + (*c.get_delta_all_swing_table)(dm, + (u8 **)&pwrtrk_tab_up_a, (u8 **)&pwrtrk_tab_down_a, + (u8 **)&pwrtrk_tab_up_b, (u8 **)&pwrtrk_tab_down_b, + (u8 **)&pwrtrk_tab_up_cck_a, (u8 **)&pwrtrk_tab_down_cck_a, + (u8 **)&pwrtrk_tab_up_cck_b, (u8 **)&pwrtrk_tab_down_cck_b); + + if (GET_CHIP_VER(priv) == VERSION_8198F) { + (*c.get_delta_all_swing_table_ex)(dm, + (u8 **)&pwrtrk_tab_up_c, (u8 **)&pwrtrk_tab_down_c, + (u8 **)&pwrtrk_tab_up_d, (u8 **)&pwrtrk_tab_down_d, + (u8 **)&pwrtrk_tab_up_cck_c, (u8 **)&pwrtrk_tab_down_cck_c, + (u8 **)&pwrtrk_tab_up_cck_d, (u8 **)&pwrtrk_tab_down_cck_d); + } + /*0x42: RF Reg[15:10] 88E*/ + thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); +#ifdef THER_TRIM + if (GET_CHIP_VER(priv) == VERSION_8197F) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val); + + thermal_value += priv->pshare->rf_ft_var.ther_trim_val; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"after thermal trim, thermal_value=%d\n", thermal_value); + } +#endif + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n\n\nCurrent Thermal = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n" + , thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther); + + /* Initialize */ + if (!dm->rf_calibrate_info.thermal_value) + dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther; + + if (!dm->rf_calibrate_info.thermal_value_lck) + dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther; + + if (!dm->rf_calibrate_info.thermal_value_iqk) + dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther; + + /* calculate average thermal meter */ + dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; + dm->rf_calibrate_info.thermal_value_avg_index++; + + if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ + dm->rf_calibrate_info.thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (dm->rf_calibrate_info.thermal_value_avg[i]) { + thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) {/*Calculate Average thermal_value after average enough times*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"thermal_value_avg=0x%x(%d) thermal_value_avg_count = %d\n" + , thermal_value_avg, thermal_value_avg, thermal_value_avg_count); + + thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther); + } + + /*4 Calculate delta, delta_LCK, delta_IQK.*/ + delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); + delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck); + delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk); + is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1); + + if (delta > 29) { /* power track table index(thermal diff.) upper bound*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta(%d) > 29, set delta to 29\n", delta); + delta = 29; + } + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK); + + /*4 if necessary, do LCK.*/ + if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk); + dm->rf_calibrate_info.thermal_value_lck = thermal_value; +#if (RTL8822B_SUPPORT != 1) + if (!(dm->support_ic_type & ODM_RTL8822B)) { + if (c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(dm); + } +#endif + } + + if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ + return; + + /*4 Do Power Tracking*/ + + if (thermal_value != dm->rf_calibrate_info.thermal_value) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******** START POWER TRACKING ********\n"); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", + thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther); + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + if (is_increase) { /*thermal is higher than base*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + switch (p) { + case RF_PATH_B: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_b[%d] = %d pwrtrk_tab_up_cck_b[%d] = %d\n", delta, pwrtrk_tab_up_b[delta], delta, pwrtrk_tab_up_cck_b[delta]); + cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_b[delta]; + cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_b[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); + break; + + case RF_PATH_C: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_c[%d] = %d pwrtrk_tab_up_cck_c[%d] = %d\n", delta, pwrtrk_tab_up_c[delta], delta, pwrtrk_tab_up_cck_c[delta]); + cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_c[delta]; + cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_c[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); + break; + + case RF_PATH_D: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_d[%d] = %d pwrtrk_tab_up_cck_d[%d] = %d\n", delta, pwrtrk_tab_up_d[delta], delta, pwrtrk_tab_up_cck_d[delta]); + cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_d[delta]; + cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_d[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); + break; + default: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_up_a[%d] = %d pwrtrk_tab_up_cck_a[%d] = %d\n", delta, pwrtrk_tab_up_a[delta], delta, pwrtrk_tab_up_cck_a[delta]); + cali_info->absolute_ofdm_swing_idx[p] = pwrtrk_tab_up_a[delta]; + cali_info->absolute_cck_swing_idx[p] = pwrtrk_tab_up_cck_a[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); + break; + } + } + } else { /* thermal is lower than base*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + switch (p) { + case RF_PATH_B: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_b[%d] = %d pwrtrk_tab_down_cck_b[%d] = %d\n", delta, pwrtrk_tab_down_b[delta], delta, pwrtrk_tab_down_cck_b[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_b[delta]; + cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_b[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); + break; + + case RF_PATH_C: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_c[%d] = %d pwrtrk_tab_down_cck_c[%d] = %d\n", delta, pwrtrk_tab_down_c[delta], delta, pwrtrk_tab_down_cck_c[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_c[delta]; + cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_c[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); + break; + + case RF_PATH_D: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_d[%d] = %d pwrtrk_tab_down_cck_d[%d] = %d\n", delta, pwrtrk_tab_down_d[delta], delta, pwrtrk_tab_down_cck_d[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_d[delta]; + cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_d[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); + break; + + default: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"pwrtrk_tab_down_a[%d] = %d pwrtrk_tab_down_cck_a[%d] = %d\n", delta, pwrtrk_tab_down_a[delta], delta, pwrtrk_tab_down_cck_a[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * pwrtrk_tab_down_a[delta]; + cali_info->absolute_cck_swing_idx[p] = -1 * pwrtrk_tab_down_cck_a[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]); + break; + } + } + } + + if (is_increase) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n"); + if (GET_CHIP_VER(priv) == VERSION_8197F) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0); + //} else if (GET_CHIP_VER(priv) == VERSION_8192F) { + // for (p = RF_PATH_A; p < c.rf_path_count; p++) + // (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8822B) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8821C) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8198F) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n"); + if (GET_CHIP_VER(priv) == VERSION_8197F) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0); + //} else if (GET_CHIP_VER(priv) == VERSION_8192F) { + // for (p = RF_PATH_A; p < c.rf_path_count; p++) + // (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8822B) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8821C) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else if (GET_CHIP_VER(priv) == VERSION_8198F) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } + } + } +#endif + + if (GET_CHIP_VER(priv) != VERSION_8198F) { + if ((delta_IQK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk); + dm->rf_calibrate_info.thermal_value_iqk = thermal_value; + if (c.do_iqk) + (*c.do_iqk)(dm, false, thermal_value, 0); + } + } + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n\n", __func__); + /*update thermal meter value*/ + dm->rf_calibrate_info.thermal_value = thermal_value; + + } + +#endif +} +#endif + +/*#if (RTL8814A_SUPPORT == 1)*/ +#if (RTL8814A_SUPPORT == 1) + +void +odm_txpowertracking_callback_thermal_meter_jaguar_series2( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase; + u8 thermal_value_avg_count = 0, p = 0, i = 0; + u32 thermal_value_avg = 0, reg0x18; + u32 bb_swing_reg[4] = {REG_A_TX_SCALE_JAGUAR, REG_B_TX_SCALE_JAGUAR, REG_C_TX_SCALE_JAGUAR2, REG_D_TX_SCALE_JAGUAR2}; + s32 ele_D; + u32 bb_swing_idx; + struct rtl8192cd_priv *priv = dm->priv; + struct txpwrtrack_cfg c; + boolean is_tssi_enable = false; + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ + u8 *delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL; + u8 *delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL; + /* for 8814 add by Yu Chen */ + u8 *delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL; + u8 *delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL; + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == false) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + configure_txpower_track(dm, &c); + cali_info->default_ofdm_index = priv->pshare->OFDM_index0[RF_PATH_A]; + + (*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b); + + if (dm->support_ic_type & ODM_RTL8814A) /* for 8814 path C & D */ + (*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, + (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d); + + thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther); + + /* Initialize */ + if (!dm->rf_calibrate_info.thermal_value) + dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther; + + if (!dm->rf_calibrate_info.thermal_value_lck) + dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther; + + if (!dm->rf_calibrate_info.thermal_value_iqk) + dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther; + + is_tssi_enable = (boolean)odm_get_rf_reg(dm, RF_PATH_A, REG_RF_TX_GAIN_OFFSET, BIT(7)); /* check TSSI enable */ + + /* 4 Query OFDM BB swing default setting Bit[31:21] */ + for (p = RF_PATH_A ; p < c.rf_path_count ; p++) { + ele_D = odm_get_bb_reg(dm, bb_swing_reg[p], 0xffe00000); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(dm, bb_swing_reg[p], MASKDWORD), ele_D); + + for (bb_swing_idx = 0; bb_swing_idx < TXSCALE_TABLE_SIZE; bb_swing_idx++) {/* 4 */ + if (ele_D == tx_scaling_table_jaguar[bb_swing_idx]) { + dm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"OFDM_index[%d]=%d\n", p, dm->rf_calibrate_info.OFDM_index[p]); + break; + } + } + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "kfree_offset[%d]=%d\n", p, cali_info->kfree_offset[p]); + + } + + /* calculate average thermal meter */ + dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; + dm->rf_calibrate_info.thermal_value_avg_index++; + if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) /* Average times = c.average_thermal_num */ + dm->rf_calibrate_info.thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (dm->rf_calibrate_info.thermal_value_avg[i]) { + thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */ + thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther); + } + + /* 4 Calculate delta, delta_LCK, delta_IQK. */ + delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); + delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck); + delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk); + is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1); + + /* 4 if necessary, do LCK. */ + if (!(dm->support_ic_type & ODM_RTL8821)) { + if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk); + dm->rf_calibrate_info.thermal_value_lck = thermal_value; + + /*Use RTLCK, so close power tracking driver LCK*/ +#if (RTL8814A_SUPPORT != 1) + if (!(dm->support_ic_type & ODM_RTL8814A)) { + if (c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(dm); + } +#endif + } + } + + if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) { + panic_printk("%s(%d)\n", __FUNCTION__, __LINE__); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk); + dm->rf_calibrate_info.thermal_value_iqk = thermal_value; + if (c.do_iqk) + (*c.do_iqk)(dm, true, 0, 0); + } + + if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ + return; + + /* 4 Do Power Tracking */ + + if (is_tssi_enable == true) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter PURE TSSI MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0); + } else if (thermal_value != dm->rf_calibrate_info.thermal_value) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\n******** START POWER TRACKING ********\n"); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther); + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + if (is_increase) { /* thermal is higher than base */ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + switch (p) { + case RF_PATH_B: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /* Record delta swing for mix mode power tracking */ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_C: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /* Record delta swing for mix mode power tracking */ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_D: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /* Record delta swing for mix mode power tracking */ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + default: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]); + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /* Record delta swing for mix mode power tracking */ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + } + } + } else { /* thermal is lower than base */ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + switch (p) { + case RF_PATH_B: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /* Record delta swing for mix mode power tracking */ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_C: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /* Record delta swing for mix mode power tracking */ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_D: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /* Record delta swing for mix mode power tracking */ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + default: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]); + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /* Record delta swing for mix mode power tracking */ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + } + } + } + + if (is_increase) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power --->\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power --->\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } + } +#endif + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__); + /* update thermal meter value */ + dm->rf_calibrate_info.thermal_value = thermal_value; + + } +} +#endif + +#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_jaguar_series( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + unsigned char thermal_value = 0, delta, delta_LCK, channel, is_decrease; + unsigned char thermal_value_avg_count = 0; + unsigned int thermal_value_avg = 0, reg0x18; + unsigned int bb_swing_reg[4] = {0xc1c, 0xe1c, 0x181c, 0x1a1c}; + int ele_D, value32; + char OFDM_index[2], index; + unsigned int i = 0, j = 0, rf_path, max_rf_path = 2, rf; + struct rtl8192cd_priv *priv = dm->priv; + unsigned char OFDM_min_index = 7; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic */ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == false) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + +#if RTL8881A_SUPPORT + if (dm->support_ic_type == ODM_RTL8881A) { + max_rf_path = 1; + if ((get_bonding_type_8881A() == BOND_8881AM || get_bonding_type_8881A() == BOND_8881AN) + && priv->pshare->rf_ft_var.use_intpa8881A && (*dm->band_type == ODM_BAND_2_4G)) + OFDM_min_index = 6; /* intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phy_band_select == PHY_BAND_2G)) */ + else + OFDM_min_index = 10; /* OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic */ + } +#endif + + + thermal_value = (unsigned char)phy_query_rf_reg(priv, RF_PATH_A, 0x42, 0xfc00, 1); /* 0x42: RF Reg[15:10] 88E */ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther); + + + /* 4 Query OFDM BB swing default setting Bit[31:21] */ + for (rf_path = 0 ; rf_path < max_rf_path ; rf_path++) { + ele_D = phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */ + if (ele_D == ofdm_swing_table_8812[i]) { + OFDM_index[rf_path] = (unsigned char)i; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path]); + break; + } + } + } +#if 0 + /* Query OFDM path A default setting Bit[31:21] */ + ele_D = phy_query_bb_reg(priv, 0xc1c, 0xffe00000); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */ + if (ele_D == ofdm_swing_table_8812[i]) { + OFDM_index[0] = (unsigned char)i; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[0]=%d\n", OFDM_index[0]); + break; + } + } + /* Query OFDM path B default setting */ + if (rf == 2) { + ele_D = phy_query_bb_reg(priv, 0xe1c, 0xffe00000); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) { + if (ele_D == ofdm_swing_table_8812[i]) { + OFDM_index[1] = (unsigned char)i; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "OFDM_index[1]=%d\n", OFDM_index[1]); + break; + } + } + } +#endif + /* Initialize */ + if (!priv->pshare->thermal_value) { + priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther; + priv->pshare->thermal_value_lck = thermal_value; + } + + /* calculate average thermal meter */ + { + priv->pshare->thermal_value_avg_8812[priv->pshare->thermal_value_avg_index_8812] = thermal_value; + priv->pshare->thermal_value_avg_index_8812++; + if (priv->pshare->thermal_value_avg_index_8812 == AVG_THERMAL_NUM_8812) + priv->pshare->thermal_value_avg_index_8812 = 0; + + for (i = 0; i < AVG_THERMAL_NUM_8812; i++) { + if (priv->pshare->thermal_value_avg_8812[i]) { + thermal_value_avg += priv->pshare->thermal_value_avg_8812[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { + thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count); + /* printk("AVG Thermal Meter = 0x%x\n", thermal_value); */ + } + } + + + /* 4 If necessary, do power tracking */ + + if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ + return; + + if (thermal_value != priv->pshare->thermal_value) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n"); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther); + delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther); + delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck); + is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0); + /* if (*dm->band_type == ODM_BAND_5G) */ + { +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + for (rf_path = 0; rf_path < max_rf_path; rf_path++) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)); + if (is_decrease) { + OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); + OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)); +#if 0/* RTL8881A_SUPPORT */ + if (dm->support_ic_type == ODM_RTL8881A) { + if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) { + if (priv->pshare->add_tx_agc) { /* tx_agc has been added */ + add_tx_power88xx_ac(priv, 0); + priv->pshare->add_tx_agc = 0; + priv->pshare->add_tx_agc_index = 0; + } + } + } +#endif + } else { + + OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); +#if 0/* RTL8881A_SUPPORT */ + if (dm->support_ic_type == ODM_RTL8881A) { + if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) { + if (OFDM_index[i] < OFDM_min_index) { + priv->pshare->add_tx_agc_index = (OFDM_min_index - OFDM_index[i]) / 2; /* Calculate Remnant tx_agc value, 2 index for 1 tx_agc */ + add_tx_power88xx_ac(priv, priv->pshare->add_tx_agc_index); + priv->pshare->add_tx_agc = 1; /* add_tx_agc Flag = 1 */ + OFDM_index[i] = OFDM_min_index; + } else { + if (priv->pshare->add_tx_agc) { /* tx_agc been added */ + priv->pshare->add_tx_agc = 0; + priv->pshare->add_tx_agc_index = 0; + add_tx_power88xx_ac(priv, 0); /* minus the added TPI */ + } + } + } + } +#else + OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ? OFDM_min_index : OFDM_index[rf_path]); +#endif + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, ">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)); + } + } + } +#endif + /* 4 Set new BB swing index */ + for (rf_path = 0; rf_path < max_rf_path; rf_path++) { + phy_set_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000, ofdm_swing_table_8812[(unsigned int)OFDM_index[rf_path]]); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]); + } + + } + if ((delta_LCK > 8) && (!iqk_info->rfk_forbidden)) { + RTL_W8(0x522, 0xff); + reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1); + phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1); + phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1); + delay_ms(200); /* frequency deviation */ + phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0); + phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18); +#ifdef CONFIG_RTL_8812_SUPPORT + if (GET_CHIP_VER(priv) == VERSION_8812E) + update_bbrf_val8812(priv, priv->pmib->dot11RFEntry.dot11channel); +#endif + RTL_W8(0x522, 0x0); + priv->pshare->thermal_value_lck = thermal_value; + } + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__); + + /* update thermal meter value */ + priv->pshare->thermal_value = thermal_value; + for (rf_path = 0; rf_path < max_rf_path; rf_path++) + priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path]; + } +} + +#endif + + +void +odm_txpowertracking_callback_thermal_meter( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + struct dm_iqk_info *iqk_info = &dm->IQK_info; + +#if (RTL8197F_SUPPORT == 1 ||RTL8192F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8822B + || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8198F) { + odm_txpowertracking_callback_thermal_meter_jaguar_series3(dm); + return; + } +#endif +#if (RTL8814A_SUPPORT == 1) /*use this function to do power tracking after 8814 by YuChen*/ + if (dm->support_ic_type & ODM_RTL8814A) { + odm_txpowertracking_callback_thermal_meter_jaguar_series2(dm); + return; + } +#endif +#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8812 || dm->support_ic_type & ODM_RTL8881A) { + odm_txpowertracking_callback_thermal_meter_jaguar_series(dm); + return; + } +#endif + +#if (RTL8192E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192E) { + odm_txpowertracking_callback_thermal_meter_92e(dm); + return; + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + /* PMGNT_INFO mgnt_info = &adapter->mgnt_info; */ +#endif + + + u8 thermal_value = 0, delta, delta_LCK, delta_IQK, offset; + u8 thermal_value_avg_count = 0; + u32 thermal_value_avg = 0; + /* s32 ele_A=0, ele_D, TempCCk, X, value32; + * s32 Y, ele_C=0; + * s8 OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index; + * s8 deltaPowerIndex = 0; */ + u32 i = 0;/* , j = 0; */ + boolean is2T = false; + /* bool bInteralPA = false; */ + + u8 OFDM_max_index = 34, rf = (is2T) ? 2 : 1; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ + u8 indexforchannel = 0;/*get_right_chnl_place_for_iqk(hal_data->current_channel)*/ + enum _POWER_DEC_INC { POWER_DEC, POWER_INC }; + + struct txpwrtrack_cfg c; + + + /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ + s8 delta_swing_table_idx[2][index_mapping_NUM_88E] = { + /* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */ + {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11}, {0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 7, 8, 9, 9, 10} + }; + u8 thermal_threshold[2][index_mapping_NUM_88E] = { + /* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */ + {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25} + }; + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + struct rtl8192cd_priv *priv = dm->priv; +#endif + + /* 4 2. Initilization ( 7 steps in total ) */ + + configure_txpower_track(dm, &c); + + dm->rf_calibrate_info.txpowertracking_callback_cnt++; /* cosa add for debug */ + dm->rf_calibrate_info.is_txpowertracking_init = true; + +#if (MP_DRIVER == 1) + dm->rf_calibrate_info.txpowertrack_control = hal_data->txpowertrack_control; /* We should keep updating the control variable according to HalData. + * rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */ + dm->rf_calibrate_info.rega24 = 0x090e1317; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST) + if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) { + if (dm->priv->pshare->mp_txpwr_tracking == false) + return; + } +#endif + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "===>odm_txpowertracking_callback_thermal_meter_8188e, dm->bb_swing_idx_cck_base: %d, dm->bb_swing_idx_ofdm_base: %d\n", cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base); + /* + if (!dm->rf_calibrate_info.tm_trigger) { + odm_set_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3); + dm->rf_calibrate_info.tm_trigger = 1; + return; + } + */ + thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (!thermal_value || !dm->rf_calibrate_info.txpowertrack_control) +#else + if (!dm->rf_calibrate_info.txpowertrack_control) +#endif + return; + + /* 4 3. Initialize ThermalValues of rf_calibrate_info */ + + if (!dm->rf_calibrate_info.thermal_value) { + dm->rf_calibrate_info.thermal_value_lck = thermal_value; + dm->rf_calibrate_info.thermal_value_iqk = thermal_value; + } + + if (dm->rf_calibrate_info.is_reloadtxpowerindex) + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n"); + + /* 4 4. Calculate average thermal meter */ + + dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; + dm->rf_calibrate_info.thermal_value_avg_index++; + if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) + dm->rf_calibrate_info.thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (dm->rf_calibrate_info.thermal_value_avg[i]) { + thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { + /* Give the new thermo value a weighting */ + thermal_value_avg += (thermal_value * 4); + + thermal_value = (u8)(thermal_value_avg / (thermal_value_avg_count + 4)); + cali_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value); + } + + /* 4 5. Calculate delta, delta_LCK, delta_IQK. */ + + delta = (thermal_value > dm->rf_calibrate_info.thermal_value) ? (thermal_value - dm->rf_calibrate_info.thermal_value) : (dm->rf_calibrate_info.thermal_value - thermal_value); + delta_LCK = (thermal_value > dm->rf_calibrate_info.thermal_value_lck) ? (thermal_value - dm->rf_calibrate_info.thermal_value_lck) : (dm->rf_calibrate_info.thermal_value_lck - thermal_value); + delta_IQK = (thermal_value > dm->rf_calibrate_info.thermal_value_iqk) ? (thermal_value - dm->rf_calibrate_info.thermal_value_iqk) : (dm->rf_calibrate_info.thermal_value_iqk - thermal_value); + + /* 4 6. If necessary, do LCK. */ + if (!(dm->support_ic_type & ODM_RTL8821)) { + /*if((delta_LCK > hal_data->delta_lck) && (hal_data->delta_lck != 0))*/ + if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) { + /*Delta temperature is equal to or larger than 20 centigrade.*/ + dm->rf_calibrate_info.thermal_value_lck = thermal_value; + (*c.phy_lc_calibrate)(dm); + } + } + + /* 3 7. If necessary, move the index of swing table to adjust Tx power. */ + + if (delta > 0 && dm->rf_calibrate_info.txpowertrack_control) { + + delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value); + + /* 4 7.1 The Final Power index = BaseIndex + power_index_offset */ + + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) { + CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta); + dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index; + dm->rf_calibrate_info.delta_power_index = delta_swing_table_idx[POWER_INC][offset]; + + } else { + + CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta); + dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index; + dm->rf_calibrate_info.delta_power_index = (-1) * delta_swing_table_idx[POWER_DEC][offset]; + } + + if (dm->rf_calibrate_info.delta_power_index == dm->rf_calibrate_info.delta_power_index_last) + dm->rf_calibrate_info.power_index_offset = 0; + else + dm->rf_calibrate_info.power_index_offset = dm->rf_calibrate_info.delta_power_index - dm->rf_calibrate_info.delta_power_index_last; + + for (i = 0; i < rf; i++) + dm->rf_calibrate_info.OFDM_index[i] = cali_info->bb_swing_idx_ofdm_base + dm->rf_calibrate_info.power_index_offset; + dm->rf_calibrate_info.CCK_index = cali_info->bb_swing_idx_cck_base + dm->rf_calibrate_info.power_index_offset; + + cali_info->bb_swing_idx_cck = dm->rf_calibrate_info.CCK_index; + cali_info->bb_swing_idx_ofdm[RF_PATH_A] = dm->rf_calibrate_info.OFDM_index[RF_PATH_A]; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, dm->rf_calibrate_info.power_index_offset); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base, dm->rf_calibrate_info.power_index_offset); + + /* 4 7.1 Handle boundary conditions of index. */ + + + for (i = 0; i < rf; i++) { + if (dm->rf_calibrate_info.OFDM_index[i] > OFDM_max_index) + dm->rf_calibrate_info.OFDM_index[i] = OFDM_max_index; + else if (dm->rf_calibrate_info.OFDM_index[i] < 0) + dm->rf_calibrate_info.OFDM_index[i] = 0; + } + + if (dm->rf_calibrate_info.CCK_index > c.swing_table_size_cck - 1) + dm->rf_calibrate_info.CCK_index = c.swing_table_size_cck - 1; + else if (dm->rf_calibrate_info.CCK_index < 0) + dm->rf_calibrate_info.CCK_index = 0; + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, dm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, dm->rf_calibrate_info.thermal_value); + dm->rf_calibrate_info.power_index_offset = 0; + } + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.CCK_index, cali_info->bb_swing_idx_cck_base); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK,"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.OFDM_index[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base); + + if (dm->rf_calibrate_info.power_index_offset != 0 && dm->rf_calibrate_info.txpowertrack_control) { + /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ + + dm->rf_calibrate_info.is_tx_power_changed = true; /* Always true after Tx Power is adjusted by power tracking. */ + /* */ + /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */ + /* to increase TX power. Otherwise, EVM will be bad. */ + /* */ + /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ + if (thermal_value > dm->rf_calibrate_info.thermal_value) { + /* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */ + /* "Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */ + /* dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */ + } else if (thermal_value < dm->rf_calibrate_info.thermal_value) { /* Low temperature */ + /* RF_DBG(dm,DBG_RF_TX_PWR_TRACK, */ + /* "Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */ + /* dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */ + } + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) + { + /* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */ + (*c.odm_tx_pwr_track_set_pwr)(dm, TXAGC, 0, 0); + } else { + /* RF_DBG(dm,DBG_RF_TX_PWR_TRACK,"Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */ + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_A, indexforchannel); + if (is2T) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_B, indexforchannel); + } + + cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; + cali_info->bb_swing_idx_ofdm_base = cali_info->bb_swing_idx_ofdm[RF_PATH_A]; + dm->rf_calibrate_info.thermal_value = thermal_value; + + } + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n"); + + dm->rf_calibrate_info.tx_powercount = 0; +} + +/* 3============================================================ + * 3 IQ Calibration + * 3============================================================ */ + +void +odm_reset_iqk_result( + void *dm_void +) +{ + return; +} +#if 1/* !(DM_ODM_SUPPORT_TYPE & ODM_AP) */ +u8 odm_get_right_chnl_place_for_iqk(u8 chnl) +{ + u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165 + }; + u8 place = chnl; + + + if (chnl > 14) { + for (place = 14; place < sizeof(channel_all); place++) { + if (channel_all[place] == chnl) + return place - 13; + } + } + return 0; + +} +#endif + +void +odm_iq_calibrate( + struct dm_struct *dm +) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) { + if ((*dm->channel != dm->pre_channel) && (!*dm->is_scan_in_process)) { + dm->pre_channel = *dm->channel; + dm->linked_interval = 0; + } + + if (dm->linked_interval < 3) + dm->linked_interval++; + + if (dm->linked_interval == 2) + halrf_iqk_trigger(dm, false); + } else + dm->linked_interval = 0; + +} + +void phydm_rf_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + odm_txpowertracking_init(dm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8814A) + phy_iq_calibrate_8814a_init(dm); +#endif +#endif + +} + +void phydm_rf_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + odm_txpowertracking_check(dm); + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + odm_iq_calibrate(dm); +#endif +} diff --git a/hal/phydm/halrf/halphyrf_ap.h b/hal/phydm/halrf/halphyrf_ap.h new file mode 100644 index 0000000..1975b5a --- /dev/null +++ b/hal/phydm/halrf/halphyrf_ap.h @@ -0,0 +1,134 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __HALPHYRF_H__ +#define __HALPHYRF_H__ + +#include "halrf/halrf_powertracking_ap.h" +#include "halrf/halrf_kfree.h" + +#if (RTL8814A_SUPPORT == 1) + #include "halrf/rtl8814a/halrf_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) + #include "halrf/rtl8822b/halrf_iqk_8822b.h" +#endif + +#if (RTL8821C_SUPPORT == 1) + #include "halrf/rtl8821c/halrf_iqk_8821c.h" +#endif + +#if (RTL8195B_SUPPORT == 1) +// #include "halrf/rtl8195b/halrf.h" + #include "halrf/rtl8195b/halrf_iqk_8195b.h" + #include "halrf/rtl8195b/halrf_txgapk_8195b.h" + #include "halrf/rtl8195b/halrf_dpk_8195b.h" +#endif +#if (RTL8198F_SUPPORT == 1) + #include "halrf/rtl8198f/halrf_iqk_8198f.h" + #include "halrf/rtl8198f/halrf_dpk_8198f.h" +#endif + +enum pwrtrack_method { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE +}; + +typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8); +typedef void(*func_iqk)(void *, u8, u8, u8); +typedef void (*func_lck)(void *); +/* refine by YuChen for 8814A */ +typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_all_swing_ex)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **); + +struct txpwrtrack_cfg { + u8 swing_table_size_cck; + u8 swing_table_size_ofdm; + u8 threshold_iqk; + u8 threshold_dpk; + u8 average_thermal_num; + u8 rf_path_count; + u32 thermal_reg_addr; + func_set_pwr odm_tx_pwr_track_set_pwr; + func_iqk do_iqk; + func_lck phy_lc_calibrate; + func_swing get_delta_swing_table; + func_swing8814only get_delta_swing_table8814only; + func_all_swing get_delta_all_swing_table; + func_all_swing_ex get_delta_all_swing_table_ex; +}; + +void +configure_txpower_track( + void *dm_void, + struct txpwrtrack_cfg *config +); + + +void +odm_txpowertracking_callback_thermal_meter( + void *dm_void +); + +#if (RTL8192E_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_92e( + void *dm_void +); +#endif + +#if (RTL8814A_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_jaguar_series2( + void *dm_void +); + +#elif ODM_IC_11AC_SERIES_SUPPORT +void +odm_txpowertracking_callback_thermal_meter_jaguar_series( + void *dm_void +); + +#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1) +void +odm_txpowertracking_callback_thermal_meter_jaguar_series3( + void *dm_void +); + +#endif + +#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M) + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +void +odm_reset_iqk_result( + void *dm_void +); +u8 +odm_get_right_chnl_place_for_iqk( + u8 chnl +); + +void phydm_rf_init(void *dm_void); +void phydm_rf_watchdog(void *dm_void); + +#endif /*#ifndef __HALPHYRF_H__*/ diff --git a/hal/phydm/halrf/halphyrf_ce.c b/hal/phydm/halrf/halphyrf_ce.c new file mode 100644 index 0000000..05bd92c --- /dev/null +++ b/hal/phydm/halrf/halphyrf_ce.c @@ -0,0 +1,918 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal)\ + do { \ + u32 __offset = (u32)_offset; \ + u32 __size = (u32)_size; \ + for (__offset = 0; __offset < __size; __offset++) { \ + if (_delta_thermal < \ + thermal_threshold[_direction][__offset]) { \ + if (__offset != 0) \ + __offset--; \ + break; \ + } \ + } \ + if (__offset >= __size) \ + __offset = __size - 1; \ + } while (0) + +void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if RTL8192E_SUPPORT + if (dm->support_ic_type == ODM_RTL8192E) + configure_txpower_track_8192e(config); +#endif +#if RTL8821A_SUPPORT + if (dm->support_ic_type == ODM_RTL8821) + configure_txpower_track_8821a(config); +#endif +#if RTL8812A_SUPPORT + if (dm->support_ic_type == ODM_RTL8812) + configure_txpower_track_8812a(config); +#endif +#if RTL8188E_SUPPORT + if (dm->support_ic_type == ODM_RTL8188E) + configure_txpower_track_8188e(config); +#endif + +#if RTL8723B_SUPPORT + if (dm->support_ic_type == ODM_RTL8723B) + configure_txpower_track_8723b(config); +#endif + +#if RTL8814A_SUPPORT + if (dm->support_ic_type == ODM_RTL8814A) + configure_txpower_track_8814a(config); +#endif + +#if RTL8703B_SUPPORT + if (dm->support_ic_type == ODM_RTL8703B) + configure_txpower_track_8703b(config); +#endif + +#if RTL8188F_SUPPORT + if (dm->support_ic_type == ODM_RTL8188F) + configure_txpower_track_8188f(config); +#endif +#if RTL8723D_SUPPORT + if (dm->support_ic_type == ODM_RTL8723D) + configure_txpower_track_8723d(config); +#endif +/* JJ ADD 20161014 */ +#if RTL8710B_SUPPORT + if (dm->support_ic_type == ODM_RTL8710B) + configure_txpower_track_8710b(config); +#endif +#if RTL8822B_SUPPORT + if (dm->support_ic_type == ODM_RTL8822B) + configure_txpower_track_8822b(config); +#endif +#if RTL8821C_SUPPORT + if (dm->support_ic_type == ODM_RTL8821C) + configure_txpower_track_8821c(config); +#endif + +#if RTL8192F_SUPPORT + if (dm->support_ic_type == ODM_RTL8192F) + configure_txpower_track_8192f(config); +#endif +} + +/* ********************************************************************** + * <20121113, Kordan> This function should be called when tx_agc changed. + * Otherwise the previous compensation is gone, because we record the + * delta of temperature between two TxPowerTracking watch dogs. + * + * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still + * need to call this function. + * ********************************************************************** + */ +void odm_clear_txpowertracking_state(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + u8 p = 0; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + cali_info->bb_swing_idx_cck = cali_info->default_cck_index; + dm->rf_calibrate_info.CCK_index = 0; + + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { + cali_info->bb_swing_idx_ofdm_base[p] + = cali_info->default_ofdm_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index; + cali_info->OFDM_index[p] = cali_info->default_ofdm_index; + + cali_info->power_index_offset[p] = 0; + cali_info->delta_power_index[p] = 0; + cali_info->delta_power_index_last[p] = 0; + + /* Initial Mix mode power tracking*/ + cali_info->absolute_ofdm_swing_idx[p] = 0; + cali_info->remnant_ofdm_swing_idx[p] = 0; + cali_info->kfree_offset[p] = 0; + } + /* Initial Mix mode power tracking*/ + cali_info->modify_tx_agc_flag_path_a = false; + cali_info->modify_tx_agc_flag_path_b = false; + cali_info->modify_tx_agc_flag_path_c = false; + cali_info->modify_tx_agc_flag_path_d = false; + cali_info->remnant_cck_swing_idx = 0; + cali_info->thermal_value = rf->eeprom_thermal; + cali_info->modify_tx_agc_value_cck = 0; + cali_info->modify_tx_agc_value_ofdm = 0; +} + +void odm_get_tracking_table(void *dm_void, u8 thermal_value, u8 delta) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + struct _hal_rf_ *rf = &dm->rf_table; + struct txpwrtrack_cfg c = {0}; + + u8 p; + /* 4 1. TWO tables decide the final index of OFDM/CCK swing table. */ + u8 *pwrtrk_tab_up_a = NULL; + u8 *pwrtrk_tab_down_a = NULL; + u8 *pwrtrk_tab_up_b = NULL; + u8 *pwrtrk_tab_down_b = NULL; + /*for 8814 add by Yu Chen*/ + u8 *pwrtrk_tab_up_c = NULL; + u8 *pwrtrk_tab_down_c = NULL; + u8 *pwrtrk_tab_up_d = NULL; + u8 *pwrtrk_tab_down_d = NULL; + /*for Xtal Offset by James.Tung*/ + s8 *xtal_tab_up = NULL; + s8 *xtal_tab_down = NULL; + + configure_txpower_track(dm, &c); + + (*c.get_delta_swing_table)(dm, + (u8 **)&pwrtrk_tab_up_a, + (u8 **)&pwrtrk_tab_down_a, + (u8 **)&pwrtrk_tab_up_b, + (u8 **)&pwrtrk_tab_down_b); + + if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/ + (*c.get_delta_swing_table8814only)(dm, + (u8 **)&pwrtrk_tab_up_c, + (u8 **)&pwrtrk_tab_down_c, + (u8 **)&pwrtrk_tab_up_d, + (u8 **)&pwrtrk_tab_down_d); + /*for Xtal Offset*/ + if (dm->support_ic_type & + (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) + (*c.get_delta_swing_xtal_table)(dm, + (s8 **)&xtal_tab_up, + (s8 **)&xtal_tab_down); + + if (thermal_value > rf->eeprom_thermal) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + /*recording power index offset*/ + cali_info->delta_power_index_last[p] = + cali_info->delta_power_index[p]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is higher******\n"); + switch (p) { + case RF_PATH_B: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "pwrtrk_tab_up_b[%d] = %d\n", delta, + pwrtrk_tab_up_b[delta]); + + cali_info->delta_power_index[p] = + pwrtrk_tab_up_b[delta]; + cali_info->absolute_ofdm_swing_idx[p] = + pwrtrk_tab_up_b[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "absolute_ofdm_swing_idx[PATH_B] = %d\n", + cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_C: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "pwrtrk_tab_up_c[%d] = %d\n", delta, + pwrtrk_tab_up_c[delta]); + + cali_info->delta_power_index[p] = + pwrtrk_tab_up_c[delta]; + cali_info->absolute_ofdm_swing_idx[p] = + pwrtrk_tab_up_c[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "absolute_ofdm_swing_idx[PATH_C] = %d\n", + cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_D: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "pwrtrk_tab_up_d[%d] = %d\n", delta, + pwrtrk_tab_up_d[delta]); + + cali_info->delta_power_index[p] = + pwrtrk_tab_up_d[delta]; + cali_info->absolute_ofdm_swing_idx[p] = + pwrtrk_tab_up_d[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "absolute_ofdm_swing_idx[PATH_D] = %d\n", + cali_info->absolute_ofdm_swing_idx[p]); + break; + + default: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "pwrtrk_tab_up_a[%d] = %d\n", delta, + pwrtrk_tab_up_a[delta]); + + cali_info->delta_power_index[p] = + pwrtrk_tab_up_a[delta]; + cali_info->absolute_ofdm_swing_idx[p] = + pwrtrk_tab_up_a[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "absolute_ofdm_swing_idx[PATH_A] = %d\n", + cali_info->absolute_ofdm_swing_idx[p]); + break; + } + } + /* JJ ADD 20161014 */ + /*Save xtal_offset from Xtal table*/ + if (dm->support_ic_type & + (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | + ODM_RTL8192F)) { + /*recording last Xtal offset*/ + cali_info->xtal_offset_last = cali_info->xtal_offset; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "[Xtal] xtal_tab_up[%d] = %d\n", + delta, xtal_tab_up[delta]); + cali_info->xtal_offset = xtal_tab_up[delta]; + if (cali_info->xtal_offset_last != xtal_tab_up[delta]) + cali_info->xtal_offset_eanble = 1; + } + } else { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + /*recording power index offset*/ + cali_info->delta_power_index_last[p] = + cali_info->delta_power_index[p]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is lower******\n"); + switch (p) { + case RF_PATH_B: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "pwrtrk_tab_down_b[%d] = %d\n", delta, + pwrtrk_tab_down_b[delta]); + cali_info->delta_power_index[p] = + -1 * pwrtrk_tab_down_b[delta]; + cali_info->absolute_ofdm_swing_idx[p] = + -1 * pwrtrk_tab_down_b[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "absolute_ofdm_swing_idx[PATH_B] = %d\n", + cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_C: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "pwrtrk_tab_down_c[%d] = %d\n", delta, + pwrtrk_tab_down_c[delta]); + cali_info->delta_power_index[p] = + -1 * pwrtrk_tab_down_c[delta]; + cali_info->absolute_ofdm_swing_idx[p] = + -1 * pwrtrk_tab_down_c[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "absolute_ofdm_swing_idx[PATH_C] = %d\n", + cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_D: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "pwrtrk_tab_down_d[%d] = %d\n", delta, + pwrtrk_tab_down_d[delta]); + cali_info->delta_power_index[p] = + -1 * pwrtrk_tab_down_d[delta]; + cali_info->absolute_ofdm_swing_idx[p] = + -1 * pwrtrk_tab_down_d[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "absolute_ofdm_swing_idx[PATH_D] = %d\n", + cali_info->absolute_ofdm_swing_idx[p]); + break; + + default: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "pwrtrk_tab_down_a[%d] = %d\n", delta, + pwrtrk_tab_down_a[delta]); + cali_info->delta_power_index[p] = + -1 * pwrtrk_tab_down_a[delta]; + cali_info->absolute_ofdm_swing_idx[p] = + -1 * pwrtrk_tab_down_a[delta]; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "absolute_ofdm_swing_idx[PATH_A] = %d\n", + cali_info->absolute_ofdm_swing_idx[p]); + break; + } + } + /* JJ ADD 20161014 */ + if (dm->support_ic_type & + (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | + ODM_RTL8192F)) { + /*recording last Xtal offset*/ + cali_info->xtal_offset_last = cali_info->xtal_offset; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "[Xtal] xtal_tab_down[%d] = %d\n", delta, + xtal_tab_down[delta]); + /*Save xtal_offset from Xtal table*/ + cali_info->xtal_offset = xtal_tab_down[delta]; + if (cali_info->xtal_offset_last != xtal_tab_down[delta]) + cali_info->xtal_offset_eanble = 1; + } + } +} + +void odm_pwrtrk_method(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 p, idxforchnl = 0; + + struct txpwrtrack_cfg c = {0}; + + configure_txpower_track(dm, &c); + + if (dm->support_ic_type & + (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8812 | + ODM_RTL8723B | ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8188F | + ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B | + ODM_RTL8192F)) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "***Enter PwrTrk MIX_MODE***\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "***Enter PwrTrk BBSWING_MODE***\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr) + (dm, BBSWING, p, idxforchnl); + } +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +void odm_txpowertracking_callback_thermal_meter(struct dm_struct *dm) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void odm_txpowertracking_callback_thermal_meter(void *dm_void) +#else +void odm_txpowertracking_callback_thermal_meter(void *adapter) +#endif +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct dm_struct *dm = (struct dm_struct *)dm_void; +#endif + + struct _hal_rf_ *rf = &dm->rf_table; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + u8 thermal_value = 0, delta, delta_lck, delta_iqk, p = 0, i = 0; + u8 thermal_value_avg_count = 0; + u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4; + + /* OFDM BB Swing should be less than +3.0dB, required by Arthur */ +#if 0 + u8 OFDM_min_index = 0; +#endif + /* get_right_chnl_place_for_iqk(hal_data->current_channel) */ + u8 power_tracking_type = rf->pwt_type; + s8 thermal_value_temp = 0; + + struct txpwrtrack_cfg c = {0}; + + /* 4 2. Initialization ( 7 steps in total ) */ + + configure_txpower_track(dm, &c); + + cali_info->txpowertracking_callback_cnt++; + cali_info->is_txpowertracking_init = true; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "\n\n\n===>%s bbsw_idx_cck_base=%d\n", + __func__, cali_info->bb_swing_idx_cck_base); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "bbsw_idx_ofdm_base[A]=%d default_ofdm_idx=%d\n", + cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], + cali_info->default_ofdm_index); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "cali_info->txpowertrack_control=%d, rf->eeprom_thermal %d\n", + cali_info->txpowertrack_control, rf->eeprom_thermal); + + /* 0x42: RF Reg[15:10] 88E */ + thermal_value = + (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); + + thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "thermal_value_temp(%d) = ther_value(%d) + pwr_trim_ther(%d)\n", + thermal_value_temp, thermal_value, + phydm_get_thermal_offset(dm)); + + if (thermal_value_temp > 63) + thermal_value = 63; + else if (thermal_value_temp < 0) + thermal_value = 0; + else + thermal_value = thermal_value_temp; + + /*add log by zhao he, check c80/c94/c14/ca0 value*/ + if (dm->support_ic_type & + (ODM_RTL8723D | ODM_RTL8710B)) { + regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF); + RF_DBG(dm, DBG_RF_IQK, + "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", + regc80, regcd0, regcd4, regab4); + } + + if (!cali_info->txpowertrack_control) + return; + + if (rf->eeprom_thermal == 0xff) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", + rf->eeprom_thermal); + return; + } + + /*4 3. Initialize ThermalValues of rf_calibrate_info*/ + + if (cali_info->is_reloadtxpowerindex) + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "reload ofdm index for band switch\n"); + + /*4 4. Calculate average thermal meter*/ + + cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] + = thermal_value; + + cali_info->thermal_value_avg_index++; + /*Average times = c.average_thermal_num*/ + if (cali_info->thermal_value_avg_index == c.average_thermal_num) + cali_info->thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (cali_info->thermal_value_avg[i]) { + thermal_value_avg += cali_info->thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + /* Calculate Average thermal_value after average enough times */ + if (thermal_value_avg_count) { + thermal_value = + (u8)(thermal_value_avg / thermal_value_avg_count); + cali_info->thermal_value_delta + = thermal_value - rf->eeprom_thermal; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", + thermal_value, rf->eeprom_thermal); + } + + /* 4 5. Calculate delta, delta_lck, delta_iqk. */ + /* "delta" here is used to determine thermal value changes or not. */ + if (thermal_value > cali_info->thermal_value) + delta = thermal_value - cali_info->thermal_value; + else + delta = cali_info->thermal_value - thermal_value; + + if (thermal_value > cali_info->thermal_value_lck) + delta_lck = thermal_value - cali_info->thermal_value_lck; + else + delta_lck = cali_info->thermal_value_lck - thermal_value; + + if (thermal_value > cali_info->thermal_value_iqk) + delta_iqk = thermal_value - cali_info->thermal_value_iqk; + else + delta_iqk = cali_info->thermal_value_iqk - thermal_value; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "(delta, delta_lck, delta_iqk) = (%d, %d, %d)\n", delta, + delta_lck, delta_iqk); + + /*4 6. If necessary, do LCK.*/ + /* Wait sacn to do LCK by RF Jenyu*/ + if (!(*dm->is_scan_in_process) && !iqk_info->rfk_forbidden) { + /* Delta temperature is equal to or larger than 20 centigrade.*/ + if (delta_lck >= c.threshold_iqk) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_lck(%d) >= threshold_iqk(%d)\n", + delta_lck, c.threshold_iqk); + cali_info->thermal_value_lck = thermal_value; + + /*Use RTLCK, close power tracking driver LCK*/ + /*8821 don't do LCK*/ + if (!(dm->support_ic_type & + (ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B)) && + c.phy_lc_calibrate) { + (*c.phy_lc_calibrate)(dm); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "do pwrtrk lck\n"); + } + } + } + + /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ + /* "delta" here is used to record the absolute value of difference. */ + if (delta > 0 && cali_info->txpowertrack_control) { + if (thermal_value > rf->eeprom_thermal) + delta = thermal_value - rf->eeprom_thermal; + else + delta = rf->eeprom_thermal - thermal_value; + + if (delta >= TXPWR_TRACK_TABLE_SIZE) + delta = TXPWR_TRACK_TABLE_SIZE - 1; + + odm_get_tracking_table(dm, thermal_value, delta); + + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "\n[path-%d] Calculate pwr_idx_offset\n", p); + + /*If Thermal value changes but table value is the same*/ + if (cali_info->delta_power_index[p] == + cali_info->delta_power_index_last[p]) + cali_info->power_index_offset[p] = 0; + else + cali_info->power_index_offset[p] = + cali_info->delta_power_index[p] - + cali_info->delta_power_index_last[p]; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "path-%d pwridx_diff%d=pwr_idx%d - last_idx%d\n", + p, cali_info->power_index_offset[p], + cali_info->delta_power_index[p], + cali_info->delta_power_index_last[p]); +#if 0 + + cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p]; + cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p]; + + cali_info->bb_swing_idx_cck = cali_info->CCK_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p]; + + /*************Print BB Swing base and index Offset*************/ + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", + cali_info->bb_swing_idx_cck, + cali_info->bb_swing_idx_cck_base, + cali_info->power_index_offset[p]); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", + cali_info->bb_swing_idx_ofdm[p], p, + cali_info->bb_swing_idx_ofdm_base[p], + cali_info->power_index_offset[p]); + + /*4 7.1 Handle boundary conditions of index.*/ + + if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1) + cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1; + else if (cali_info->OFDM_index[p] <= OFDM_min_index) + cali_info->OFDM_index[p] = OFDM_min_index; +#endif + } +#if 0 + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "\n\n========================================================================================================\n"); + + if (cali_info->CCK_index > c.swing_table_size_cck - 1) + cali_info->CCK_index = c.swing_table_size_cck - 1; + else if (cali_info->CCK_index <= 0) + cali_info->CCK_index = 0; +#endif + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Thermal is unchanged thermal=%d last_thermal=%d\n", + thermal_value, + cali_info->thermal_value); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + cali_info->power_index_offset[p] = 0; + } + +#if 0 + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", + cali_info->CCK_index, + cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/ + + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n", + cali_info->OFDM_index[p], p, + cali_info->bb_swing_idx_ofdm_base[p]); + } +#endif + + if ((dm->support_ic_type & ODM_RTL8814A)) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "power_tracking_type=%d\n", + power_tracking_type); + + if (power_tracking_type == 0) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "***Enter PwrTrk MIX_MODE***\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr) + (dm, MIX_MODE, p, 0); + } else if (power_tracking_type == 1) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "***Enter PwrTrk MIX(2G) TSSI(5G) MODE***\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr) + (dm, MIX_2G_TSSI_5G_MODE, p, 0); + } else if (power_tracking_type == 2) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "***Enter PwrTrk MIX(5G) TSSI(2G)MODE***\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr) + (dm, MIX_5G_TSSI_2G_MODE, p, 0); + } else if (power_tracking_type == 3) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "***Enter PwrTrk TSSI MODE***\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr) + (dm, TSSI_MODE, p, 0); + } + } else if ((cali_info->power_index_offset[RF_PATH_A] != 0 || + cali_info->power_index_offset[RF_PATH_B] != 0 || + cali_info->power_index_offset[RF_PATH_C] != 0 || + cali_info->power_index_offset[RF_PATH_D] != 0)) { +#if 0 + /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ + /*Always true after Tx Power is adjusted by power tracking.*/ + + cali_info->is_tx_power_changed = true; + /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital + * to increase TX power. Otherwise, EVM will be bad. + * + * 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. + */ + if (thermal_value > cali_info->thermal_value) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, cali_info->power_index_offset[p], + delta, thermal_value, rf->eeprom_thermal, + cali_info->thermal_value); + } + } else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, cali_info->power_index_offset[p], + delta, thermal_value, rf->eeprom_thermal, + cali_info->thermal_value); + } + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (thermal_value > rf->eeprom_thermal) { +#else + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) { +#endif + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) higher than PG value(%d)\n", + thermal_value, rf->eeprom_thermal); + + odm_pwrtrk_method(dm); + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) lower than PG value(%d)\n", + thermal_value, rf->eeprom_thermal); + + odm_pwrtrk_method(dm); + } + +#if 0 + /*Record last time Power Tracking result as base.*/ + cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; + for (p = RF_PATH_A; p < c.rf_path_count; p++) + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p]; +#endif + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "cali_info->thermal_value = %d thermal_value= %d\n", + cali_info->thermal_value, thermal_value); + } + /*Record last Power Tracking Thermal value*/ + cali_info->thermal_value = thermal_value; + + if (dm->support_ic_type & + (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8192F | ODM_RTL8710B)) { + if (cali_info->xtal_offset_eanble != 0 && + cali_info->txpowertrack_control && + rf->eeprom_thermal != 0xff) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "**********Enter Xtal Tracking**********\n"); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (thermal_value > rf->eeprom_thermal) { +#else + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) { +#endif + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) higher than PG (%d)\n", + thermal_value, rf->eeprom_thermal); + (*c.odm_txxtaltrack_set_xtal)(dm); + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) lower than PG (%d)\n", + thermal_value, rf->eeprom_thermal); + (*c.odm_txxtaltrack_set_xtal)(dm); + } + } + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "**********End Xtal Tracking**********\n"); + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + /* Wait sacn to do IQK by RF Jenyu*/ + if (!(*dm->is_scan_in_process) && !iqk_info->rfk_forbidden && + !cali_info->is_iqk_in_progress) { + if (!(dm->support_ic_type & ODM_RTL8723B)) { + /*Delta temperature is equal or larger than 20 Celsius*/ + /*When threshold is 8*/ + if (delta_iqk >= c.threshold_iqk) { + cali_info->thermal_value_iqk = thermal_value; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_iqk(%d) >= threshold_iqk(%d)\n", + delta_iqk, c.threshold_iqk); + (*c.do_iqk)(dm, delta_iqk, thermal_value, 8); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "do pwrtrk iqk\n"); + } + } + } + +#if 0 + if (cali_info->dpk_thermal[RF_PATH_A] != 0) { + if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) { + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk)); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk); + + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } else { + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } + } + if (cali_info->dpk_thermal[RF_PATH_B] != 0) { + if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) { + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk)); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk); + + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } else { + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } + } +#endif + +#endif + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===%s\n", __func__); + + cali_info->tx_powercount = 0; +} + +/* 3============================================================ + * 3 IQ Calibration + * 3============================================================ + */ + +void odm_reset_iqk_result(void *dm_void) +{ +} + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +u8 odm_get_right_chnl_place_for_iqk(u8 chnl) +{ + u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, + 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, + 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, + 124, 126, 128, 130, 132, 134, 136, 138, 140, + 149, 151, 153, 155, 157, 159, 161, 163, 165}; + u8 place = chnl; + + if (chnl > 14) { + for (place = 14; place < sizeof(channel_all); place++) { + if (channel_all[place] == chnl) + return place - 13; + } + } + return 0; +} +#endif + +void odm_iq_calibrate(struct dm_struct *dm) +{ + void *adapter = dm->adapter; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (*dm->is_fcs_mode_enable) + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + if (IS_HARDWARE_TYPE_8812AU(adapter)) + return; +#endif + + if (dm->is_linked && !iqk_info->rfk_forbidden) { + if ((*dm->channel != dm->pre_channel) && + (!*dm->is_scan_in_process)) { + dm->pre_channel = *dm->channel; + dm->linked_interval = 0; + } + + if (dm->linked_interval < 3) + dm->linked_interval++; + + if (dm->linked_interval == 2) + halrf_iqk_trigger(dm, false); + } else { + dm->linked_interval = 0; + } +} + +void phydm_rf_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_txpowertracking_init(dm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + odm_clear_txpowertracking_state(dm); +#endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8814A) + phy_iq_calibrate_8814a_init(dm); +#endif +#endif +} + +void phydm_rf_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + odm_txpowertracking_check(dm); +#if 0 +/*if (dm->support_ic_type & ODM_IC_11AC_SERIES)*/ +/*odm_iq_calibrate(dm);*/ +#endif +#endif +} diff --git a/hal/phydm/halrf/halphyrf_ce.h b/hal/phydm/halrf/halphyrf_ce.h new file mode 100644 index 0000000..d635657 --- /dev/null +++ b/hal/phydm/halrf/halphyrf_ce.h @@ -0,0 +1,110 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALPHYRF_H__ +#define __HALPHYRF_H__ + +#include "halrf/halrf_kfree.h" +#if (RTL8814A_SUPPORT == 1) +#include "halrf/rtl8814a/halrf_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) +#include "halrf/rtl8822b/halrf_iqk_8822b.h" +#endif + +#if (RTL8821C_SUPPORT == 1) +#include "halrf/rtl8821c/halrf_iqk_8821c.h" +#endif + +#if (RTL8195B_SUPPORT == 1) +/* #include "halrf/rtl8195b/halrf.h" */ +#include "halrf/rtl8195b/halrf_iqk_8195b.h" +#include "halrf/rtl8195b/halrf_txgapk_8195b.h" +#include "halrf/rtl8195b/halrf_dpk_8195b.h" +#endif + +#include "halrf/halrf_powertracking_ce.h" + +enum spur_cal_method { + PLL_RESET, + AFE_PHASE_SEL +}; + +enum pwrtrack_method { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE, + MIX_2G_TSSI_5G_MODE, + MIX_5G_TSSI_2G_MODE +}; + +typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8); +typedef void (*func_iqk)(void *, u8, u8, u8); +typedef void (*func_lck)(void *); +typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_swing_xtal)(void *, s8 **, s8 **); +typedef void (*func_set_xtal)(void *); + +struct txpwrtrack_cfg { + u8 swing_table_size_cck; + u8 swing_table_size_ofdm; + u8 threshold_iqk; + u8 threshold_dpk; + u8 average_thermal_num; + u8 rf_path_count; + u32 thermal_reg_addr; + func_set_pwr odm_tx_pwr_track_set_pwr; + func_iqk do_iqk; + func_lck phy_lc_calibrate; + func_swing get_delta_swing_table; + func_swing8814only get_delta_swing_table8814only; + func_swing_xtal get_delta_swing_xtal_table; + func_set_xtal odm_txxtaltrack_set_xtal; +}; + +void configure_txpower_track(void *dm_void, struct txpwrtrack_cfg *config); + +void odm_clear_txpowertracking_state(void *dm_void); + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +void odm_txpowertracking_callback_thermal_meter(void *dm_void); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +void odm_txpowertracking_callback_thermal_meter(void *dm); +#else +void odm_txpowertracking_callback_thermal_meter(void *adapter); +#endif + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + +void odm_reset_iqk_result(void *dm_void); +u8 odm_get_right_chnl_place_for_iqk(u8 chnl); + +void phydm_rf_init(void *dm_void); +void phydm_rf_watchdog(void *dm_void); + +#endif /*#ifndef __HALPHYRF_H__*/ diff --git a/hal/phydm/halrf/halphyrf_iot.c b/hal/phydm/halrf/halphyrf_iot.c new file mode 100644 index 0000000..b72b831 --- /dev/null +++ b/hal/phydm/halrf/halphyrf_iot.c @@ -0,0 +1,478 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \ + do {\ + for (_offset = 0; _offset < _size; _offset++) { \ + if (_delta_thermal < thermal_threshold[_direction][_offset]) { \ + if (_offset != 0)\ + _offset--;\ + break;\ + } \ + } \ + if (_offset >= _size)\ + _offset = _size-1;\ + } while (0) + +void configure_txpower_track( + void *dm_void, + struct txpwrtrack_cfg *config +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if RTL8195B_SUPPORT + if (dm->support_ic_type == ODM_RTL8195B) + configure_txpower_track_8195b(config); +#endif + +} + +/* ********************************************************************** + * <20121113, Kordan> This function should be called when tx_agc changed. + * Otherwise the previous compensation is gone, because we record the + * delta of temperature between two TxPowerTracking watch dogs. + * + * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still + * need to call this function. + * ********************************************************************** */ +void +odm_clear_txpowertracking_state( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + u8 p = 0; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + cali_info->bb_swing_idx_cck = cali_info->default_cck_index; + dm->rf_calibrate_info.CCK_index = 0; + + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index; + cali_info->OFDM_index[p] = cali_info->default_ofdm_index; + + cali_info->power_index_offset[p] = 0; + cali_info->delta_power_index[p] = 0; + cali_info->delta_power_index_last[p] = 0; + + cali_info->absolute_ofdm_swing_idx[p] = 0; + cali_info->remnant_ofdm_swing_idx[p] = 0; + cali_info->kfree_offset[p] = 0; + } + + cali_info->modify_tx_agc_flag_path_a = false; + cali_info->modify_tx_agc_flag_path_b = false; + cali_info->modify_tx_agc_flag_path_c = false; + cali_info->modify_tx_agc_flag_path_d = false; + cali_info->remnant_cck_swing_idx = 0; + cali_info->thermal_value = rf->eeprom_thermal; + cali_info->modify_tx_agc_value_cck = 0; + cali_info->modify_tx_agc_value_ofdm = 0; +} + +void +odm_txpowertracking_callback_thermal_meter( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; + u8 thermal_value_avg_count = 0; + u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4; + + u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ + u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */ + u8 power_tracking_type = rf->pwt_type; + u8 xtal_offset_eanble = 0; + s8 thermal_value_temp = 0; + + struct txpwrtrack_cfg c = {0}; + + /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ + u8 *delta_swing_table_idx_tup_a = NULL; + u8 *delta_swing_table_idx_tdown_a = NULL; + u8 *delta_swing_table_idx_tup_b = NULL; + u8 *delta_swing_table_idx_tdown_b = NULL; + /*for Xtal Offset by James.Tung*/ + s8 *delta_swing_table_xtal_up = NULL; + s8 *delta_swing_table_xtal_down = NULL; + + /* 4 2. Initialization ( 7 steps in total ) */ + + configure_txpower_track(dm, &c); + + (*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b); + + if (dm->support_ic_type & ODM_RTL8195B) /*for Xtal Offset*/ + (*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down); + + cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/ + cali_info->is_txpowertracking_init = true; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n", + cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "cali_info->txpowertrack_control = %d, hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control, rf->eeprom_thermal); + + thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + + thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm)); + + if (thermal_value_temp > 63) + thermal_value = 63; + else if (thermal_value_temp < 0) + thermal_value = 0; + else + thermal_value = thermal_value_temp; + + if (!cali_info->txpowertrack_control) + return; + + if (rf->eeprom_thermal == 0xff) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", rf->eeprom_thermal); + return; + } + + /*4 3. Initialize ThermalValues of rf_calibrate_info*/ + //if (cali_info->is_reloadtxpowerindex) + // RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n"); + + /*4 4. Calculate average thermal meter*/ + + cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value; + cali_info->thermal_value_avg_index++; + if (cali_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ + cali_info->thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (cali_info->thermal_value_avg[i]) { + thermal_value_avg += cali_info->thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */ + thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); + cali_info->thermal_value_delta = thermal_value - rf->eeprom_thermal; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, rf->eeprom_thermal); + } + + /* 4 5. Calculate delta, delta_LCK, delta_IQK. */ + /* "delta" here is used to determine whether thermal value changes or not. */ + delta = (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value); + delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value); + delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value); + + /*4 6. If necessary, do LCK.*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK); + + /* Wait sacn to do LCK by RF Jenyu*/ + if ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden)) { + /* Delta temperature is equal to or larger than 20 centigrade.*/ + if (delta_LCK >= c.threshold_iqk) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk); + cali_info->thermal_value_lck = thermal_value; + + /*Use RTLCK, so close power tracking driver LCK*/ + (*c.phy_lc_calibrate)(dm); + } + } + + /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ + if (delta > 0 && cali_info->txpowertrack_control) { + /* "delta" here is used to record the absolute value of difference. */ + delta = thermal_value > rf->eeprom_thermal ? (thermal_value - rf->eeprom_thermal) : (rf->eeprom_thermal - thermal_value); + + if (delta >= TXPWR_TRACK_TABLE_SIZE) + delta = TXPWR_TRACK_TABLE_SIZE - 1; + + /*4 7.1 The Final Power index = BaseIndex + power_index_offset*/ + if (thermal_value > rf->eeprom_thermal) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/ + switch (p) { + case RF_PATH_B: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]); + + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + default: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]); + + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + } + } + /* JJ ADD 20161014 */ + if (dm->support_ic_type & ODM_RTL8195B) { + /*Save xtal_offset from Xtal table*/ + cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]); + cali_info->xtal_offset = delta_swing_table_xtal_up[delta]; + xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset); + } + + } else { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/ + + switch (p) { + case RF_PATH_B: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + default: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + } + } + /* JJ ADD 20161014 */ + + if (dm->support_ic_type & ODM_RTL8195B) { + /*Save xtal_offset from Xtal table*/ + cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]); + cali_info->xtal_offset = delta_swing_table_xtal_down[delta]; + xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset); + } + } +#if 0 + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p); + + if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/ + cali_info->power_index_offset[p] = 0; + else + cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/ + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]); + + cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p]; + cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p]; + + cali_info->bb_swing_idx_cck = cali_info->CCK_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p]; + + /*************Print BB Swing base and index Offset*************/ + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]); + + /*4 7.1 Handle boundary conditions of index.*/ + + if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1) + cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1; + else if (cali_info->OFDM_index[p] <= OFDM_min_index) + cali_info->OFDM_index[p] = OFDM_min_index; + } + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "\n\n========================================================================================================\n"); + + if (cali_info->CCK_index > c.swing_table_size_cck - 1) + cali_info->CCK_index = c.swing_table_size_cck - 1; + else if (cali_info->CCK_index <= 0) + cali_info->CCK_index = 0; +#endif + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n", + cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value); + + for (p = RF_PATH_A; p < c.rf_path_count; p++) + cali_info->power_index_offset[p] = 0; + } +#if 0 + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", + cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/ + + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n", + cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]); + } +#endif + if (thermal_value > rf->eeprom_thermal) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal); + + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 || + dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A || + dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B || + dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B || + dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8195B){ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel); + } + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal); + + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 || + dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A || + dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B || + dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B || + dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8195B) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel); + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel); + } + + cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p]; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value); + + cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + } + + if (dm->support_ic_type == ODM_RTL8195B) {/* JJ ADD 20161014 */ + if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rf->eeprom_thermal != 0xff)) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n"); + + if (thermal_value > rf->eeprom_thermal) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) higher than PG value(%d)\n", thermal_value, rf->eeprom_thermal); + (*c.odm_txxtaltrack_set_xtal)(dm); + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) lower than PG value(%d)\n", thermal_value, rf->eeprom_thermal); + (*c.odm_txxtaltrack_set_xtal)(dm); + } + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n"); + } + } + + /* Wait sacn to do IQK by RF Jenyu*/ + if ((!*dm->is_scan_in_process) && (!iqk_info->rfk_forbidden)) { + /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ + if (delta_IQK >= c.threshold_iqk) { + cali_info->thermal_value_iqk = thermal_value; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk); + if (!cali_info->is_iqk_in_progress) + (*c.do_iqk)(dm, delta_IQK, thermal_value, 8); + } + } + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n"); + + cali_info->tx_powercount = 0; +} + +/* 3============================================================ + * 3 IQ Calibration + * 3============================================================ + */ + +void +odm_reset_iqk_result( + void *dm_void +) +{ + return; +} + +u8 odm_get_right_chnl_place_for_iqk(u8 chnl) +{ + +} + +void +odm_iq_calibrate( + struct dm_struct *dm +) +{ + +} + +void phydm_rf_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_txpowertracking_init(dm); + + odm_clear_txpowertracking_state(dm); +} + +void phydm_rf_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_txpowertracking_check(dm); +} diff --git a/hal/phydm/halrf/halphyrf_iot.h b/hal/phydm/halrf/halphyrf_iot.h new file mode 100644 index 0000000..7eba821 --- /dev/null +++ b/hal/phydm/halrf/halphyrf_iot.h @@ -0,0 +1,124 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALPHYRF_H__ +#define __HALPHYRF_H__ + +#include "halrf/halrf_kfree.h" + +#if (RTL8821C_SUPPORT == 1) + #include "halrf/rtl8821c/halrf_iqk_8821c.h" +#endif + +#if (RTL8195B_SUPPORT == 1) +// #include "halrf/rtl8195b/halrf.h" + #include "halrf/rtl8195b/halrf_iqk_8195b.h" + #include "halrf/rtl8195b/halrf_txgapk_8195b.h" + #include "halrf/rtl8195b/halrf_dpk_8195b.h" +#endif + +#include "halrf/halrf_powertracking_iot.h" + + +enum spur_cal_method { + PLL_RESET, + AFE_PHASE_SEL +}; + +enum pwrtrack_method { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE, + MIX_2G_TSSI_5G_MODE, + MIX_5G_TSSI_2G_MODE +}; + +typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8); +typedef void(*func_iqk)(void *, u8, u8, u8); +typedef void (*func_lck)(void *); +typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void(*func_swing_xtal)(void *, s8 **, s8 **); +typedef void(*func_set_xtal)(void *); + +struct txpwrtrack_cfg { + u8 swing_table_size_cck; + u8 swing_table_size_ofdm; + u8 threshold_iqk; + u8 threshold_dpk; + u8 average_thermal_num; + u8 rf_path_count; + u32 thermal_reg_addr; + func_set_pwr odm_tx_pwr_track_set_pwr; + func_iqk do_iqk; + func_lck phy_lc_calibrate; + func_swing get_delta_swing_table; + func_swing8814only get_delta_swing_table8814only; + func_swing_xtal get_delta_swing_xtal_table; + func_set_xtal odm_txxtaltrack_set_xtal; +}; + +void +configure_txpower_track( + void *dm_void, + struct txpwrtrack_cfg *config +); + + +void +odm_clear_txpowertracking_state( + void *dm_void +); + +void +odm_txpowertracking_callback_thermal_meter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + void *dm_void +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *dm +#else + void *adapter +#endif +); + + + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +void +odm_reset_iqk_result( + void *dm_void +); +u8 +odm_get_right_chnl_place_for_iqk( + u8 chnl +); + +void phydm_rf_init(void *dm_void); +void phydm_rf_watchdog(void *dm_void); + +#endif /*#ifndef __HALPHYRF_H__*/ diff --git a/hal/phydm/halrf/halphyrf_win.c b/hal/phydm/halrf/halphyrf_win.c new file mode 100644 index 0000000..0a906d7 --- /dev/null +++ b/hal/phydm/halrf/halphyrf_win.c @@ -0,0 +1,836 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \ + do {\ + for (_offset = 0; _offset < _size; _offset++) { \ + \ + if (_delta_thermal < thermal_threshold[_direction][_offset]) { \ + \ + if (_offset != 0)\ + _offset--;\ + break;\ + } \ + } \ + if (_offset >= _size)\ + _offset = _size-1;\ + } while (0) + +void configure_txpower_track( + struct dm_struct *dm, + struct txpwrtrack_cfg *config +) +{ +#if RTL8192E_SUPPORT + if (dm->support_ic_type == ODM_RTL8192E) + configure_txpower_track_8192e(config); +#endif +#if RTL8821A_SUPPORT + if (dm->support_ic_type == ODM_RTL8821) + configure_txpower_track_8821a(config); +#endif +#if RTL8812A_SUPPORT + if (dm->support_ic_type == ODM_RTL8812) + configure_txpower_track_8812a(config); +#endif +#if RTL8188E_SUPPORT + if (dm->support_ic_type == ODM_RTL8188E) + configure_txpower_track_8188e(config); +#endif + +#if RTL8188F_SUPPORT + if (dm->support_ic_type == ODM_RTL8188F) + configure_txpower_track_8188f(config); +#endif + +#if RTL8723B_SUPPORT + if (dm->support_ic_type == ODM_RTL8723B) + configure_txpower_track_8723b(config); +#endif + +#if RTL8814A_SUPPORT + if (dm->support_ic_type == ODM_RTL8814A) + configure_txpower_track_8814a(config); +#endif + +#if RTL8703B_SUPPORT + if (dm->support_ic_type == ODM_RTL8703B) + configure_txpower_track_8703b(config); +#endif + +#if RTL8822B_SUPPORT + if (dm->support_ic_type == ODM_RTL8822B) + configure_txpower_track_8822b(config); +#endif + +#if RTL8723D_SUPPORT + if (dm->support_ic_type == ODM_RTL8723D) + configure_txpower_track_8723d(config); +#endif + +/* JJ ADD 20161014 */ +#if RTL8710B_SUPPORT + if (dm->support_ic_type == ODM_RTL8710B) + configure_txpower_track_8710b(config); +#endif + +#if RTL8821C_SUPPORT + if (dm->support_ic_type == ODM_RTL8821C) + configure_txpower_track_8821c(config); +#endif + +#if RTL8192F_SUPPORT + if (dm->support_ic_type == ODM_RTL8192F) + configure_txpower_track_8192f(config); +#endif + +} + +/* ********************************************************************** + * <20121113, Kordan> This function should be called when tx_agc changed. + * Otherwise the previous compensation is gone, because we record the + * delta of temperature between two TxPowerTracking watch dogs. + * + * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still + * need to call this function. + * ********************************************************************** */ +void +odm_clear_txpowertracking_state( + struct dm_struct *dm +) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA((PADAPTER)(dm->adapter)); + u8 p = 0; + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + cali_info->bb_swing_idx_cck = cali_info->default_cck_index; + cali_info->CCK_index = 0; + + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index; + cali_info->OFDM_index[p] = cali_info->default_ofdm_index; + + cali_info->power_index_offset[p] = 0; + cali_info->delta_power_index[p] = 0; + cali_info->delta_power_index_last[p] = 0; + + cali_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/ + cali_info->remnant_ofdm_swing_idx[p] = 0; + cali_info->kfree_offset[p] = 0; + } + + cali_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/ + cali_info->remnant_cck_swing_idx = 0; + cali_info->thermal_value = hal_data->eeprom_thermal_meter; + + cali_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */ + cali_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */ + +} + +void +odm_txpowertracking_callback_thermal_meter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + struct dm_struct *dm +#else + void *adapter +#endif +) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct dm_struct *dm = &hal_data->DM_OutSrc; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct dm_struct *dm = &hal_data->odmpriv; +#endif +#endif + + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; + s8 diff_DPK[4] = {0}; + u8 thermal_value_avg_count = 0; + u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4, regc88, rege14, reg848,reg838, reg86c; + + u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ + u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */ + u8 power_tracking_type = hal_data->RfPowerTrackingType; + u8 xtal_offset_eanble = 0; + s8 thermal_value_temp = 0; + + struct txpwrtrack_cfg c; + + /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ + u8 *delta_swing_table_idx_tup_a = NULL; + u8 *delta_swing_table_idx_tdown_a = NULL; + u8 *delta_swing_table_idx_tup_b = NULL; + u8 *delta_swing_table_idx_tdown_b = NULL; + /*for 8814 add by Yu Chen*/ + u8 *delta_swing_table_idx_tup_c = NULL; + u8 *delta_swing_table_idx_tdown_c = NULL; + u8 *delta_swing_table_idx_tup_d = NULL; + u8 *delta_swing_table_idx_tdown_d = NULL; + /*for Xtal Offset by James.Tung*/ + s8 *delta_swing_table_xtal_up = NULL; + s8 *delta_swing_table_xtal_down = NULL; + + /* 4 2. Initilization ( 7 steps in total ) */ + + configure_txpower_track(dm, &c); + + (*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b); + + if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/ + (*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, + (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d); + /* JJ ADD 20161014 */ + if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) /*for Xtal Offset*/ + (*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down); + + + cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/ + cali_info->is_txpowertracking_init = true; + + /*cali_info->txpowertrack_control = hal_data->txpowertrack_control; + We should keep updating the control variable according to HalData. + rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + cali_info->rega24 = 0x090e1317; +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (*(dm->mp_mode) == true) + cali_info->rega24 = 0x090e1317; +#endif + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n", + cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "cali_info->txpowertrack_control=%d, hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control, hal_data->eeprom_thermal_meter); + thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + + thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm)); + + if (thermal_value_temp > 63) + thermal_value = 63; + else if (thermal_value_temp < 0) + thermal_value = 0; + else + thermal_value = thermal_value_temp; + + /*add log by zhao he, check c80/c94/c14/ca0 value*/ + if (dm->support_ic_type == ODM_RTL8723D) { + regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF); + RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4); + } + + /* JJ ADD 20161014 */ + if (dm->support_ic_type == ODM_RTL8710B) { + regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(dm, R_0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(dm, R_0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(dm, R_0xab4, 0x000007FF); + RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4); + } + /* Winnita add 20171205 */ + if (dm->support_ic_type == ODM_RTL8192F) { + regc80 = odm_get_bb_reg(dm, R_0xc80, MASKDWORD); + regc88 = odm_get_bb_reg(dm, R_0xc88, MASKDWORD); + regab4 = odm_get_bb_reg(dm, R_0xab4, MASKDWORD); + rege14 = odm_get_bb_reg(dm, R_0xe14, MASKDWORD); + reg848 = odm_get_bb_reg(dm, R_0x848, MASKDWORD); + reg838 = odm_get_bb_reg(dm, R_0x838, MASKDWORD); + reg86c = odm_get_bb_reg(dm, R_0x86c, MASKDWORD); + RF_DBG(dm, DBG_RF_IQK, "0xc80 = 0x%x 0xc88 = 0x%x 0xab4 = 0x%x 0xe14 = 0x%x\n", regc80, regc88, regab4, rege14); + RF_DBG(dm, DBG_RF_IQK, "0x848 = 0x%x 0x838 = 0x%x 0x86c = 0x%x\n", reg848, reg838, reg86c); + } + + if (!cali_info->txpowertrack_control) + return; + + if (hal_data->eeprom_thermal_meter == 0xff) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter); + return; + } + + /*4 3. Initialize ThermalValues of rf_calibrate_info*/ + + if (cali_info->is_reloadtxpowerindex) + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "reload ofdm index for band switch\n"); + + /*4 4. Calculate average thermal meter*/ + + cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value; + cali_info->thermal_value_avg_index++; + if (cali_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ + cali_info->thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (cali_info->thermal_value_avg[i]) { + thermal_value_avg += cali_info->thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */ + thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); + cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter); + } + + /* 4 5. Calculate delta, delta_LCK, delta_IQK. */ + + /* "delta" here is used to determine whether thermal value changes or not. */ + delta = (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value); + delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value); + delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value); + + if (cali_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/ + cali_info->thermal_value_iqk = thermal_value; + delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n"); + } + + for (p = RF_PATH_A; p < c.rf_path_count; p++) + diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p]; + + /*4 6. If necessary, do LCK.*/ + + if (!(dm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/ + if (cali_info->thermal_value_lck == 0xff) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "no PG, do LCK\n"); + cali_info->thermal_value_lck = thermal_value; + + /*Use RTLCK, so close power tracking driver LCK*/ + if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) { + if (c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(dm); + } + + delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value); + } + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK); + + /* Wait sacn to do LCK by RF Jenyu*/ + if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) { + /* Delta temperature is equal to or larger than 20 centigrade.*/ + if (delta_LCK >= c.threshold_iqk) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk); + cali_info->thermal_value_lck = thermal_value; + + /*Use RTLCK, so close power tracking driver LCK*/ + if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) { + if (c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(dm); + } + } + } + } + + /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ + + if (delta > 0 && cali_info->txpowertrack_control) { + /* "delta" here is used to record the absolute value of differrence. */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + delta = thermal_value > hal_data->eeprom_thermal_meter ? (thermal_value - hal_data->eeprom_thermal_meter) : (hal_data->eeprom_thermal_meter - thermal_value); +#else + delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value); +#endif + if (delta >= TXPWR_TRACK_TABLE_SIZE) + delta = TXPWR_TRACK_TABLE_SIZE - 1; + + /*4 7.1 The Final Power index = BaseIndex + power_index_offset*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (thermal_value > hal_data->eeprom_thermal_meter) { +#else + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) { +#endif + + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/ + switch (p) { + case RF_PATH_B: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]); + + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_C: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]); + + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_D: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]); + + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + default: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]); + + cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta]; + cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + } + } + /* JJ ADD 20161014 */ + if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) { + /*Save xtal_offset from Xtal table*/ + cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]); + cali_info->xtal_offset = delta_swing_table_xtal_up[delta]; + + if (cali_info->xtal_offset_last == cali_info->xtal_offset) + xtal_offset_eanble = 0; + else + xtal_offset_eanble = 1; + } + + } else { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/ + + switch (p) { + case RF_PATH_B: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_C: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + case RF_PATH_D: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + + default: + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]); + cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta]; + cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]); + break; + } + } + /* JJ ADD 20161014 */ + if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B | ODM_RTL8192F)) { + /*Save xtal_offset from Xtal table*/ + cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/ + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]); + cali_info->xtal_offset = delta_swing_table_xtal_down[delta]; + + if (cali_info->xtal_offset_last == cali_info->xtal_offset) + xtal_offset_eanble = 0; + else + xtal_offset_eanble = 1; + } + + } + + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p); + + if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/ + cali_info->power_index_offset[p] = 0; + else + cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/ + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]); + + cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p]; + cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p]; + + cali_info->bb_swing_idx_cck = cali_info->CCK_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p]; + + /*************Print BB Swing base and index Offset*************/ + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]); + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]); + + /*4 7.1 Handle boundary conditions of index.*/ + + if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1) + cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1; + else if (cali_info->OFDM_index[p] <= OFDM_min_index) + cali_info->OFDM_index[p] = OFDM_min_index; + } + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "\n\n========================================================================================================\n"); + + if (cali_info->CCK_index > c.swing_table_size_cck - 1) + cali_info->CCK_index = c.swing_table_size_cck - 1; + else if (cali_info->CCK_index <= 0) + cali_info->CCK_index = 0; + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n", + cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value); + + for (p = RF_PATH_A; p < c.rf_path_count; p++) + cali_info->power_index_offset[p] = 0; + } + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", + cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/ + + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n", + cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]); + } + + if ((dm->support_ic_type & ODM_RTL8814A)) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type); + + if (power_tracking_type == 0) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else if (power_tracking_type == 1) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0); + } else if (power_tracking_type == 2) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0); + } else if (power_tracking_type == 3) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0); + } + cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + + } else if ((cali_info->power_index_offset[RF_PATH_A] != 0 || + cali_info->power_index_offset[RF_PATH_B] != 0 || + cali_info->power_index_offset[RF_PATH_C] != 0 || + cali_info->power_index_offset[RF_PATH_D] != 0) && + cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) { + /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ + + cali_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/ + /* */ + /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */ + /* to increase TX power. Otherwise, EVM will be bad. */ + /* */ + /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ + if (thermal_value > cali_info->thermal_value) { + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value); + } + } else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value); + } + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (thermal_value > hal_data->eeprom_thermal_meter) +#else + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) +#endif + { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); + + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 || + dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A || + dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B || + dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B || + dm->support_ic_type == ODM_RTL8192F) { + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0); + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel); + } + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); + + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 || + dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A || + dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B || + dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B || + dm->support_ic_type == ODM_RTL8192F) { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel); + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n"); + for (p = RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel); + } + + } + + cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/ + for (p = RF_PATH_A; p < c.rf_path_count; p++) + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p]; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value); + + cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + + } + + + if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || + dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + + if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) { + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n"); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (thermal_value > hal_data->eeprom_thermal_meter) { +#else + if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) { +#endif + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); + (*c.odm_txxtaltrack_set_xtal)(dm); + } else { + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter); + (*c.odm_txxtaltrack_set_xtal)(dm); + } + } + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "**********End Xtal Tracking**********\n"); + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + /* Wait sacn to do IQK by RF Jenyu*/ + if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) { + if (!IS_HARDWARE_TYPE_8723B(adapter)) { + /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ + if (delta_IQK >= c.threshold_iqk) { + cali_info->thermal_value_iqk = thermal_value; + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk); + if (!cali_info->is_iqk_in_progress) + (*c.do_iqk)(dm, delta_IQK, thermal_value, 8); + } + } + } + if (cali_info->dpk_thermal[RF_PATH_A] != 0) { + if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) { + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk)); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk); + + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } else { + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } + } + if (cali_info->dpk_thermal[RF_PATH_B] != 0) { + if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) { + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk)); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk); + + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } else { + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, R_0x82c, BIT(31), 0x0); + } + } + +#endif + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n"); + + cali_info->tx_powercount = 0; +} + + + +/* 3============================================================ + * 3 IQ Calibration + * 3============================================================ */ + +void +odm_reset_iqk_result( + struct dm_struct *dm +) +{ + return; +} +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +u8 odm_get_right_chnl_place_for_iqk(u8 chnl) +{ + u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165 + }; + u8 place = chnl; + + + if (chnl > 14) { + for (place = 14; place < sizeof(channel_all); place++) { + if (channel_all[place] == chnl) + return place - 13; + } + } + return 0; + +} +#endif + +void +odm_iq_calibrate( + struct dm_struct *dm +) +{ + void *adapter = dm->adapter; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + RF_DBG(dm, DBG_RF_IQK, "=>%s\n",__FUNCTION__); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (*dm->is_fcs_mode_enable) + return; +#endif + + if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) { + RF_DBG(dm, DBG_RF_IQK, "interval=%d ch=%d prech=%d scan=%s\n", dm->linked_interval, + *dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE"); + + if (*dm->channel != dm->pre_channel) { + dm->pre_channel = *dm->channel; + dm->linked_interval = 0; + } + + if ((dm->linked_interval < 3) && (!*dm->is_scan_in_process)) + dm->linked_interval++; + + if (dm->linked_interval == 2) + PHY_IQCalibrate(adapter, false); + } else + dm->linked_interval = 0; + + RF_DBG(dm, DBG_RF_IQK, "<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, dm->linked_interval, + *dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE?"TRUE":"FALSE"); +} + +void phydm_rf_init(struct dm_struct *dm) +{ + + odm_txpowertracking_init(dm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + odm_clear_txpowertracking_state(dm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8814A) + phy_iq_calibrate_8814a_init(dm); +#endif +#endif + +} + +void phydm_rf_watchdog(struct dm_struct *dm) +{ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + odm_txpowertracking_check(dm); + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + odm_iq_calibrate(dm); +#endif +} diff --git a/hal/phydm/halrf/halphyrf_win.h b/hal/phydm/halrf/halphyrf_win.h new file mode 100644 index 0000000..e502913 --- /dev/null +++ b/hal/phydm/halrf/halphyrf_win.h @@ -0,0 +1,122 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __HALPHYRF_H__ +#define __HALPHYRF_H__ + +#if (RTL8814A_SUPPORT == 1) + #include "halrf/rtl8814a/halrf_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) + #include "halrf/rtl8822b/halrf_iqk_8822b.h" + #include "../mac/Halmac_type.h" +#endif +#include "halrf/halrf_powertracking_win.h" +#include "halrf/halrf_kfree.h" +#include "halrf/halrf_txgapcal.h" +#if (RTL8821C_SUPPORT == 1) + #include "halrf/rtl8821c/halrf_iqk_8821c.h" +#endif + +#if (RTL8195B_SUPPORT == 1) +// #include "halrf/rtl8195b/halrf.h" + #include "halrf/rtl8195b/halrf_iqk_8195b.h" + #include "halrf/rtl8195b/halrf_txgapk_8195b.h" + #include "halrf/rtl8195b/halrf_dpk_8195b.h" +#endif + + +enum spur_cal_method { + PLL_RESET, + AFE_PHASE_SEL +}; + +enum pwrtrack_method { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE, + MIX_2G_TSSI_5G_MODE, + MIX_5G_TSSI_2G_MODE +}; + +typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8); +typedef void(*func_iqk)(void *, u8, u8, u8); +typedef void(*func_lck)(void *); +typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_swing_xtal)(void *, s8 **, s8 **); +typedef void (*func_set_xtal)(void *); +typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **); + +struct txpwrtrack_cfg { + u8 swing_table_size_cck; + u8 swing_table_size_ofdm; + u8 threshold_iqk; + u8 threshold_dpk; + u8 average_thermal_num; + u8 rf_path_count; + u32 thermal_reg_addr; + func_set_pwr odm_tx_pwr_track_set_pwr; + func_iqk do_iqk; + func_lck phy_lc_calibrate; + func_swing get_delta_swing_table; + func_swing8814only get_delta_swing_table8814only; + func_swing_xtal get_delta_swing_xtal_table; + func_set_xtal odm_txxtaltrack_set_xtal; + func_all_swing get_delta_all_swing_table; +}; + +void +configure_txpower_track( + struct dm_struct *dm, + struct txpwrtrack_cfg *config +); + + +void +odm_clear_txpowertracking_state( + struct dm_struct *dm +); + +void +odm_txpowertracking_callback_thermal_meter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + struct dm_struct *dm +#else + void *adapter +#endif +); + + + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +void +odm_reset_iqk_result( + struct dm_struct *dm +); +u8 +odm_get_right_chnl_place_for_iqk( + u8 chnl +); + +void odm_iq_calibrate(struct dm_struct *dm); +void phydm_rf_init(struct dm_struct *dm); +void phydm_rf_watchdog(struct dm_struct *dm); + +#endif /*#ifndef __HALPHYRF_H__*/ diff --git a/hal/phydm/halrf/halrf.c b/hal/phydm/halrf/halrf.c new file mode 100644 index 0000000..a5f29ef --- /dev/null +++ b/hal/phydm/halrf/halrf.c @@ -0,0 +1,1806 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ + */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\ + RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1) +void _iqk_page_switch(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type == ODM_RTL8821C) + odm_write_4byte(dm, 0x1b00, 0xf8000008); + else + odm_write_4byte(dm, 0x1b00, 0xf800000a); +} + +u32 halrf_psd_log2base(u32 val) +{ + u8 j; + u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0; + u32 result, val_fractiond_b = 0; + u32 table_fraction[21] = { + 0, 432, 332, 274, 232, 200, 174, 151, 132, 115, + 100, 86, 74, 62, 51, 42, 32, 23, 15, 7, 0}; + + if (val == 0) + return 0; + + tmp = val; + + while (1) { + if (tmp == 1) + break; + + tmp = (tmp >> 1); + shiftcount++; + } + + val_integerd_b = shiftcount + 1; + + tmp2 = 1; + for (j = 1; j <= val_integerd_b; j++) + tmp2 = tmp2 * 2; + + tmp = (val * 100) / tmp2; + tindex = tmp / 5; + + if (tindex > 20) + tindex = 20; + + val_fractiond_b = table_fraction[tindex]; + + result = val_integerd_b * 100 - val_fractiond_b; + + return result; +} + +void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + u8 i, ch; + u32 tmp; + u32 bit_mask_20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16); + + if (debug) + ch = 2; + else + ch = 0; + + odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0xf8000008 | path << 1); + if (idx == 0) + odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x3); + else + odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x1); + odm_set_bb_reg(dm, R_0x1bd4, bit_mask_20_16, 0x10); + for (i = 0; i < 8; i++) { + odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0xe0000001 + (i * 4)); + tmp = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD); + iqk_info->iqk_cfir_real[ch][path][idx][i] = + (tmp & 0x0fff0000) >> 16; + iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0xfff; + } + odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x0); +} + +void halrf_iqk_xym_enable(struct dm_struct *dm, u8 xym_enable) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (xym_enable == 0) + iqk_info->xym_read = false; + else + iqk_info->xym_read = true; + + RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s %s\n", "xym_read = ", + (iqk_info->xym_read ? "true" : "false")); +} + +/*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/ +void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 i, start, num; + u32 tmp1, tmp2; + + if (!iqk_info->xym_read) + return; + + if (*dm->band_width == 0) { + start = 3; + num = 4; + } else if (*dm->band_width == 1) { + start = 2; + num = 6; + } else { + start = 0; + num = 10; + } + + odm_write_4byte(dm, 0x1b00, 0xf8000008); + tmp1 = odm_read_4byte(dm, 0x1b1c); + odm_write_4byte(dm, 0x1b1c, 0xa2193c32); + + odm_write_4byte(dm, 0x1b00, 0xf800000a); + tmp2 = odm_read_4byte(dm, 0x1b1c); + odm_write_4byte(dm, 0x1b1c, 0xa2193c32); + + for (path = 0; path < 2; path++) { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + switch (xym_type) { + case 0: + for (i = 0; i < num; i++) { + odm_write_4byte(dm, 0x1b14, 0xe6 + start + i); + odm_write_4byte(dm, 0x1b14, 0x0); + iqk_info->rx_xym[path][i] = + odm_read_4byte(dm, 0x1b38); + } + break; + case 1: + for (i = 0; i < num; i++) { + odm_write_4byte(dm, 0x1b14, 0xe6 + start + i); + odm_write_4byte(dm, 0x1b14, 0x0); + iqk_info->tx_xym[path][i] = + odm_read_4byte(dm, 0x1b38); + } + break; + case 2: + for (i = 0; i < 6; i++) { + odm_write_4byte(dm, 0x1b14, 0xe0 + i); + odm_write_4byte(dm, 0x1b14, 0x0); + iqk_info->gs1_xym[path][i] = + odm_read_4byte(dm, 0x1b38); + } + break; + case 3: + for (i = 0; i < 6; i++) { + odm_write_4byte(dm, 0x1b14, 0xe0 + i); + odm_write_4byte(dm, 0x1b14, 0x0); + iqk_info->gs2_xym[path][i] = + odm_read_4byte(dm, 0x1b38); + } + break; + case 4: + for (i = 0; i < 6; i++) { + odm_write_4byte(dm, 0x1b14, 0xe0 + i); + odm_write_4byte(dm, 0x1b14, 0x0); + iqk_info->rxk1_xym[path][i] = + odm_read_4byte(dm, 0x1b38); + } + break; + } + odm_write_4byte(dm, 0x1b38, 0x20000000); + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1b1c, tmp1); + odm_write_4byte(dm, 0x1b00, 0xf800000a); + odm_write_4byte(dm, 0x1b1c, tmp2); + _iqk_page_switch(dm); + } +} + +/*xym_type => 0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/ +void halrf_iqk_xym_show(struct dm_struct *dm, u8 xym_type) +{ + u8 num, path, path_num, i; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (dm->rf_type == RF_1T1R) + path_num = 0x1; + else if (dm->rf_type == RF_2T2R) + path_num = 0x2; + else + path_num = 0x4; + + if (*dm->band_width == CHANNEL_WIDTH_20) + num = 4; + else if (*dm->band_width == CHANNEL_WIDTH_40) + num = 6; + else + num = 10; + + for (path = 0; path < path_num; path++) { + switch (xym_type) { + case 0: + for (i = 0; i < num; i++) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]%-20s %-2d: 0x%x\n", + (path == 0) ? "PATH A RX-XYM " : + "PATH B RX-XYM", i, + iqk_info->rx_xym[path][i]); + break; + case 1: + for (i = 0; i < num; i++) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]%-20s %-2d: 0x%x\n", + (path == 0) ? "PATH A TX-XYM " : + "PATH B TX-XYM", i, + iqk_info->tx_xym[path][i]); + break; + case 2: + for (i = 0; i < 6; i++) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]%-20s %-2d: 0x%x\n", + (path == 0) ? "PATH A GS1-XYM " : + "PATH B GS1-XYM", i, + iqk_info->gs1_xym[path][i]); + break; + case 3: + for (i = 0; i < 6; i++) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]%-20s %-2d: 0x%x\n", + (path == 0) ? "PATH A GS2-XYM " : + "PATH B GS2-XYM", i, + iqk_info->gs2_xym[path][i]); + break; + case 4: + for (i = 0; i < 6; i++) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]%-20s %-2d: 0x%x\n", + (path == 0) ? "PATH A RXK1-XYM " : + "PATH B RXK1-XYM", i, + iqk_info->rxk1_xym[path][i]); + break; + } + } +} + +void halrf_iqk_xym_dump(void *dm_void) +{ + u32 tmp1, tmp2; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_write_4byte(dm, 0x1b00, 0xf8000008); + tmp1 = odm_read_4byte(dm, 0x1b1c); + odm_write_4byte(dm, 0x1b00, 0xf800000a); + tmp2 = odm_read_4byte(dm, 0x1b1c); +#if 0 + /*halrf_iqk_xym_read(dm, xym_type);*/ +#endif + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1b1c, tmp1); + odm_write_4byte(dm, 0x1b00, 0xf800000a); + odm_write_4byte(dm, 0x1b1c, tmp2); + _iqk_page_switch(dm); +} + +void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u8 rf_path, j, reload_iqk = 0; + u32 tmp; + /*two channel, PATH, TX/RX, 0:pass 1 :fail*/ + boolean iqk_result[2][NUM][2]; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (!(dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))) + return; + + /* IQK INFO */ + PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n", + "% IQK Info %"); + PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s\n", + (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" : + "Driver-IQK"); + + reload_iqk = (u8)odm_get_bb_reg(dm, R_0x1bf0, BIT(16)); + PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n", + "reload", (reload_iqk) ? "True" : "False"); + + PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n", + "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False"); +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \ + RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1) + PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n", + "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False"); +#endif + + PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s:%d %d\n", + "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt); + + PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %d\n", + "channel", *dm->channel); + + if (*dm->band_width == CHANNEL_WIDTH_20) + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", "bandwidth", "BW_20"); + else if (*dm->band_width == CHANNEL_WIDTH_40) + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", "bandwidth", "BW_40"); + else if (*dm->band_width == CHANNEL_WIDTH_80) + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", "bandwidth", "BW_80"); + else if (*dm->band_width == CHANNEL_WIDTH_160) + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", "bandwidth", "BW_160"); + else + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %s\n", "bandwidth", "BW_UNKNOWN"); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: %llu %s\n", "progressing_time", + dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)"); + + tmp = odm_read_4byte(dm, 0x1bf0); + for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) + for (j = 0; j < 2; j++) + iqk_result[0][rf_path][j] = (boolean) + (tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4)))); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-20s: 0x%08x\n", "Reg0x1bf0", tmp); + PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n", + "PATH_A-Tx result", + (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass"); + PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n", + "PATH_A-Rx result", + (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass"); +#if (RTL8822B_SUPPORT == 1) + PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n", + "PATH_B-Tx result", + (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass"); + PDM_SNPF(out_len, used, output + used, out_len - used, "%-20s: %s\n", + "PATH_B-Rx result", + (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass"); +#endif + *_used = used; + *_out_len = out_len; +} + +void halrf_get_fw_version(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + rf->fw_ver = (dm->fw_version << 16) | dm->fw_sub_version; +} + +void halrf_iqk_dbg(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rf_path, j; + u32 tmp; + /*two channel, PATH, TX/RX, 0:pass 1 :fail*/ + boolean iqk_result[2][NUM][2]; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + struct _hal_rf_ *rf = &dm->rf_table; + + /* IQK INFO */ + RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== IQK Info ======"); + + RF_DBG(dm, DBG_RF_IQK, "%-20s\n", + (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" : + "Driver-IQK"); + + if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) { + halrf_get_fw_version(dm); + RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x\n", "FW_VER", rf->fw_ver); + } else { + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "IQK_VER", HALRF_IQK_VER); + } + + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "reload", + (iqk_info->is_reload) ? "True" : "False"); + + RF_DBG(dm, DBG_RF_IQK, "%-20s: %d %d\n", "iqk count / fail count", + dm->n_iqk_cnt, dm->n_iqk_fail_cnt); + + RF_DBG(dm, DBG_RF_IQK, "%-20s: %d\n", "channel", *dm->channel); + + if (*dm->band_width == CHANNEL_WIDTH_20) + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_20"); + else if (*dm->band_width == CHANNEL_WIDTH_40) + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_40"); + else if (*dm->band_width == CHANNEL_WIDTH_80) + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_80"); + else if (*dm->band_width == CHANNEL_WIDTH_160) + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", "BW_160"); + else + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "bandwidth", + "BW_UNKNOWN"); +#if 0 +/* + * RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", + * "progressing_time", + * dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)"); + */ +#endif + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "rfk_forbidden", + (iqk_info->rfk_forbidden) ? "True" : "False"); +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \ + RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1) + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "segment_iqk", + (iqk_info->segment_iqk) ? "True" : "False"); +#endif + + RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time", + dm->rf_calibrate_info.iqk_progressing_time, "(ms)"); + + tmp = odm_read_4byte(dm, 0x1bf0); + for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) + for (j = 0; j < 2; j++) + iqk_result[0][rf_path][j] = (boolean) + (tmp & (BIT(rf_path + (j * 4)) >> (rf_path + (j * 4)))); + + RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1bf0", tmp); + RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%08x\n", "Reg0x1be8", + odm_read_4byte(dm, 0x1be8)); + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Tx result", + (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass"); + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_A-Rx result", + (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass"); +#if (RTL8822B_SUPPORT == 1) + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Tx result", + (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass"); + RF_DBG(dm, DBG_RF_IQK, "%-20s: %s\n", "PATH_B-Rx result", + (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass"); +#endif +} + +void halrf_lck_dbg(struct dm_struct *dm) +{ + RF_DBG(dm, DBG_RF_IQK, "%-20s\n", "====== LCK Info ======"); +#if 0 + /*RF_DBG(dm, DBG_RF_IQK, "%-20s\n", + * (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "LCK" : "RTK")); + */ +#endif + RF_DBG(dm, DBG_RF_IQK, "%-20s: %llu %s\n", "progressing_time", + dm->rf_calibrate_info.lck_progressing_time, "(ms)"); +} + +void halrf_iqk_dbg_cfir_backup(struct dm_struct *dm) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 path, idx, i; + + RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR"); + + for (path = 0; path < 2; path++) + for (idx = 0; idx < 2; idx++) + phydm_get_iqk_cfir(dm, idx, path, true); + + for (path = 0; path < 2; path++) { + for (idx = 0; idx < 2; idx++) { + for (i = 0; i < 8; i++) { + RF_DBG(dm, DBG_RF_IQK, + "[IQK]%-7s %-3s CFIR_real: %-2d: 0x%x\n", + (path == 0) ? "PATH A" : "PATH B", + (idx == 0) ? "TX" : "RX", i, + iqk_info->iqk_cfir_real[2][path][idx][i]) + ; + } + for (i = 0; i < 8; i++) { + RF_DBG(dm, DBG_RF_IQK, + "[IQK]%-7s %-3s CFIR_img:%-2d: 0x%x\n", + (path == 0) ? "PATH A" : "PATH B", + (idx == 0) ? "TX" : "RX", i, + iqk_info->iqk_cfir_imag[2][path][idx][i]) + ; + } + } + } +} + +void halrf_iqk_dbg_cfir_backup_update(struct dm_struct *dm) +{ + struct dm_iqk_info *iqk = &dm->IQK_info; + u8 i, path, idx; + u32 bmask13_12 = BIT(13) | BIT(12); + u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16); + u32 data; + + if (iqk->iqk_cfir_real[2][0][0][0] == 0) { + RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid"); + return; + } + for (path = 0; path < 2; path++) { + for (idx = 0; idx < 2; idx++) { + odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, + 0xf8000008 | path << 1); + odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7); + odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000); + if (idx == 0) + odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x3); + else + odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x1); + odm_set_bb_reg(dm, R_0x1bd4, bmask20_16, 0x10); + for (i = 0; i < 8; i++) { + data = ((0xc0000000 >> idx) + 0x3) + (i * 4) + + (iqk->iqk_cfir_real[2][path][idx][i] + << 9); + odm_write_4byte(dm, 0x1bd8, data); + data = ((0xc0000000 >> idx) + 0x1) + (i * 4) + + (iqk->iqk_cfir_imag[2][path][idx][i] + << 9); + odm_write_4byte(dm, 0x1bd8, data); +#if 0 + /*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_real[2][path][idx][i]);*/ + /*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_imag[2][path][idx][i]);*/ +#endif + } + } + odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x0); + } + RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "update new CFIR"); +} + +void halrf_iqk_dbg_cfir_reload(struct dm_struct *dm) +{ + struct dm_iqk_info *iqk = &dm->IQK_info; + u8 i, path, idx; + u32 bmask13_12 = BIT(13) | BIT(12); + u32 bmask20_16 = BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16); + u32 data; + + if (iqk->iqk_cfir_real[0][0][0][0] == 0) { + RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "CFIR is invalid"); + return; + } + for (path = 0; path < 2; path++) { + for (idx = 0; idx < 2; idx++) { + odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, + 0xf8000008 | path << 1); + odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7); + odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000); + if (idx == 0) + odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x3); + else + odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x1); + odm_set_bb_reg(dm, R_0x1bd4, bmask20_16, 0x10); + for (i = 0; i < 8; i++) { +#if 0 + /*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_real[0][path][idx][i]);*/ + /*odm_write_4byte(dm, 0x1bd8, iqk->iqk_cfir_imag[0][path][idx][i]);*/ +#endif + data = ((0xc0000000 >> idx) + 0x3) + (i * 4) + + (iqk->iqk_cfir_real[0][path][idx][i] + << 9); + odm_write_4byte(dm, 0x1bd8, data); + data = ((0xc0000000 >> idx) + 0x1) + (i * 4) + + (iqk->iqk_cfir_imag[0][path][idx][i] + << 9); + odm_write_4byte(dm, 0x1bd8, data); + } + } + odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(dm, R_0x1b0c, bmask13_12, 0x0); + } + RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "write CFIR with default value"); +} + +void halrf_iqk_dbg_cfir_write(struct dm_struct *dm, u8 type, u32 path, u32 idx, + u32 i, u32 data) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (type == 0) + iqk_info->iqk_cfir_real[2][path][idx][i] = data; + else + iqk_info->iqk_cfir_imag[2][path][idx][i] = data; +} + +void halrf_iqk_dbg_cfir_backup_show(struct dm_struct *dm) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 path, idx, i; + + RF_DBG(dm, DBG_RF_IQK, "[IQK]%-20s\n", "backup TX/RX CFIR"); + + for (path = 0; path < 2; path++) { + for (idx = 0; idx < 2; idx++) { + for (i = 0; i < 8; i++) { + RF_DBG(dm, DBG_RF_IQK, + "[IQK]%-10s %-3s CFIR_real:%-2d: 0x%x\n", + (path == 0) ? "PATH A" : "PATH B", + (idx == 0) ? "TX" : "RX", i, + iqk_info->iqk_cfir_real[2][path][idx][i]) + ; + } + for (i = 0; i < 8; i++) { + RF_DBG(dm, DBG_RF_IQK, + "[IQK]%-10s %-3s CFIR_img:%-2d: 0x%x\n", + (path == 0) ? "PATH A" : "PATH B", + (idx == 0) ? "TX" : "RX", i, + iqk_info->iqk_cfir_imag[2][path][idx][i]) + ; + } + } + } +} + +void halrf_do_imr_test(void *dm_void, u8 flag_imr_test) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (flag_imr_test != 0x0) + switch (dm->support_ic_type) { +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + do_imr_test_8822b(dm); + break; +#endif +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + do_imr_test_8821c(dm); + break; +#endif + default: + break; + } +} + +void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if 0 + /*dm_value[0]=0x0: backup from SRAM & show*/ + /*dm_value[0]=0x1: write backup CFIR to SRAM*/ + /*dm_value[0]=0x2: reload default CFIR to SRAM*/ + /*dm_value[0]=0x3: show backup*/ + /*dm_value[0]=0x10: write backup CFIR real part*/ + /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/ + /*dm_value[0]=0x11: write backup CFIR imag*/ + /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/ + /*dm_value[0]=0x20 :xym_read enable*/ + /*--> dm_value[1]:0:disable, 1:enable*/ + /*if dm_value[0]=0x20 = enable, */ + /*0x1:show rx_sym; 0x2: tx_xym; 0x3:gs1_xym; 0x4:gs2_sym; 0x5:rxk1_xym*/ +#endif + if (dm_value[0] == 0x0) + halrf_iqk_dbg_cfir_backup(dm); + else if (dm_value[0] == 0x1) + halrf_iqk_dbg_cfir_backup_update(dm); + else if (dm_value[0] == 0x2) + halrf_iqk_dbg_cfir_reload(dm); + else if (dm_value[0] == 0x3) + halrf_iqk_dbg_cfir_backup_show(dm); + else if (dm_value[0] == 0x10) + halrf_iqk_dbg_cfir_write(dm, 0, dm_value[1], dm_value[2], + dm_value[3], dm_value[4]); + else if (dm_value[0] == 0x11) + halrf_iqk_dbg_cfir_write(dm, 1, dm_value[1], dm_value[2], + dm_value[3], dm_value[4]); + else if (dm_value[0] == 0x20) + halrf_iqk_xym_enable(dm, (u8)dm_value[1]); + else if (dm_value[0] == 0x21) + halrf_iqk_xym_show(dm, (u8)dm_value[1]); + else if (dm_value[0] == 0x30) + halrf_do_imr_test(dm, (u8)dm_value[1]); +} + +void halrf_iqk_hwtx_check(void *dm_void, boolean is_check) +{ +#if 0 + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u32 tmp_b04; + + if (is_check) { + iqk_info->is_hwtx = (boolean)odm_get_bb_reg(dm, R_0xb00, BIT(8)); + } else { + if (iqk_info->is_hwtx) { + tmp_b04 = odm_read_4byte(dm, 0xb04); + odm_set_bb_reg(dm, R_0xb04, BIT(3) | BIT(2), 0x0); + odm_write_4byte(dm, 0xb04, tmp_b04); + } + } +#endif +} + +void halrf_segment_iqk_trigger(void *dm_void, boolean clear, + boolean segment_iqk) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + struct _hal_rf_ *rf = &dm->rf_table; + u64 start_time; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (odm_check_power_status(dm) == false) + return; +#endif + + if (dm->mp_mode && + rf->is_con_tx && + rf->is_single_tone && + rf->is_carrier_suppresion) + if (*dm->mp_mode && + ((*rf->is_con_tx || + *rf->is_single_tone || + *rf->is_carrier_suppresion))) + return; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(rf->rf_supportability & HAL_RF_IQK)) + return; +#endif + +#if DISABLE_BB_RF + return; +#endif + if (iqk_info->rfk_forbidden) + return; + + if (!dm->rf_calibrate_info.is_iqk_in_progress) { + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = true; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + start_time = odm_get_current_time(dm); + dm->IQK_info.segment_iqk = segment_iqk; + + switch (dm->support_ic_type) { +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + phy_iq_calibrate_8822b(dm, clear, segment_iqk); + break; +#endif +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + phy_iq_calibrate_8821c(dm, clear, segment_iqk); + break; +#endif +#if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + break; +#endif +#if (RTL8195B_SUPPORT == 1) + case ODM_RTL8195B: + phy_iq_calibrate_8195b(dm, clear, segment_iqk); + break; +#endif +#if (RTL8198F_SUPPORT == 1) + case ODM_RTL8198F: + phy_iq_calibrate_8198f(dm, clear, segment_iqk); + break; +#endif + + default: + break; + } + dm->rf_calibrate_info.iqk_progressing_time = + odm_get_progressing_time(dm, start_time); + RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK progressing_time = %lld ms\n", + dm->rf_calibrate_info.iqk_progressing_time); + + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + } else { + RF_DBG(dm, DBG_RF_IQK, + "== Return the IQK CMD, because RFKs in Progress ==\n"); + } +} + +#endif + +u8 halrf_match_iqk_version(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + u32 iqk_version = 0; + char temp[10] = {0}; + + odm_move_memory(dm, temp, HALRF_IQK_VER, sizeof(temp)); + PHYDM_SSCANF(temp + 2, DCMD_HEX, &iqk_version); + + if (dm->support_ic_type == ODM_RTL8822B) { + if (iqk_version >= 0x24 && (odm_get_hw_img_version(dm) >= 72)) + return 1; + else if ((iqk_version <= 0x23) && + (odm_get_hw_img_version(dm) <= 71)) + return 1; + else + return 0; + } + + if (dm->support_ic_type == ODM_RTL8821C) { + if (iqk_version >= 0x18 && (odm_get_hw_img_version(dm) >= 37)) + return 1; + else + return 0; + } + + return 1; +} + +void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + switch (dm->support_ic_type) { +#if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + halrf_rf_lna_setting_8188e(dm, type); + break; +#endif +#if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: + halrf_rf_lna_setting_8192e(dm, type); + break; +#endif +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + halrf_rf_lna_setting_8192f(dm, type); + break; +#endif + +#if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + halrf_rf_lna_setting_8723b(dm, type); + break; +#endif +#if (RTL8812A_SUPPORT == 1) + case ODM_RTL8812: + halrf_rf_lna_setting_8812a(dm, type); + break; +#endif +#if ((RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1)) + case ODM_RTL8881A: + case ODM_RTL8821: + halrf_rf_lna_setting_8821a(dm, type); + break; +#endif +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + halrf_rf_lna_setting_8822b(dm_void, type); + break; +#endif +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + halrf_rf_lna_setting_8821c(dm_void, type); + break; +#endif + default: + break; + } +} + +void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + u32 dm_value[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + for (i = 0; i < 5; i++) + if (input[i + 1]) + PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &dm_value[i]); + + if (dm_value[0] == 100) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n[RF Supportability]\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))Power Tracking\n", + ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ? + ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))IQK\n", + ((rf->rf_supportability & HAL_RF_IQK) ? ("V") : + ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "02. (( %s ))LCK\n", + ((rf->rf_supportability & HAL_RF_LCK) ? ("V") : + ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "03. (( %s ))DPK\n", + ((rf->rf_supportability & HAL_RF_DPK) ? ("V") : + ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "04. (( %s ))HAL_RF_TXGAPK\n", + ((rf->rf_supportability & HAL_RF_TXGAPK) ? ("V") : + ("."))); + } else { + if (dm_value[1] == 1) /* enable */ + rf->rf_supportability |= BIT(dm_value[0]); + else if (dm_value[1] == 2) /* disable */ + rf->rf_supportability &= ~(BIT(dm_value[0])); + else + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Warning!!!] 1:enable, 2:disable\n"); + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "\nCurr-RF_supportability = 0x%x\n\n", rf->rf_supportability); + + *_used = used; + *_out_len = out_len; +} + +void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info, + u32 value) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + switch (cmn_info) { + case HALRF_CMNINFO_EEPROM_THERMAL_VALUE: + rf->eeprom_thermal = (u8)value; + break; + case HALRF_CMNINFO_PWT_TYPE: + rf->pwt_type = (u8)value; + break; + default: + break; + } +} + +void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info, + void *value) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + switch (cmn_info) { + case HALRF_CMNINFO_CON_TX: + rf->is_con_tx = (boolean *)value; + break; + case HALRF_CMNINFO_SINGLE_TONE: + rf->is_single_tone = (boolean *)value; + break; + case HALRF_CMNINFO_CARRIER_SUPPRESSION: + rf->is_carrier_suppresion = (boolean *)value; + break; + case HALRF_CMNINFO_MP_RATE_INDEX: + rf->mp_rate_index = (u8 *)value; + break; + default: + /*do nothing*/ + break; + } +} + +void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value) +{ + /* This init variable may be changed in run time. */ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + switch (cmn_info) { + case HALRF_CMNINFO_ABILITY: + rf->rf_supportability = (u32)value; + break; + + case HALRF_CMNINFO_DPK_EN: + rf->dpk_en = (u8)value; + break; + case HALRF_CMNINFO_RFK_FORBIDDEN: + dm->IQK_info.rfk_forbidden = (boolean)value; + break; +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \ + RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1) + case HALRF_CMNINFO_IQK_SEGMENT: + dm->IQK_info.segment_iqk = (boolean)value; + break; +#endif + case HALRF_CMNINFO_RATE_INDEX: + rf->p_rate_index = (u32)value; + break; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + case HALRF_CMNINFO_MP_PSD_POINT: + rf->halrf_psd_data.point = (u32)value; + break; + case HALRF_CMNINFO_MP_PSD_START_POINT: + rf->halrf_psd_data.start_point = (u32)value; + break; + case HALRF_CMNINFO_MP_PSD_STOP_POINT: + rf->halrf_psd_data.stop_point = (u32)value; + break; + case HALRF_CMNINFO_MP_PSD_AVERAGE: + rf->halrf_psd_data.average = (u32)value; + break; +#endif + default: + /* do nothing */ + break; + } +} + +u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info) +{ + /* This init variable may be changed in run time. */ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + u64 return_value = 0; + + switch (cmn_info) { + case HALRF_CMNINFO_ABILITY: + return_value = (u32)rf->rf_supportability; + break; + case HALRF_CMNINFO_RFK_FORBIDDEN: + return_value = dm->IQK_info.rfk_forbidden; + break; +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || \ + RTL8821C_SUPPORT == 1 || RTL8195B_SUPPORT == 1) + case HALRF_CMNINFO_IQK_SEGMENT: + return_value = dm->IQK_info.segment_iqk; + break; +#endif + default: + /* do nothing */ + break; + } + + return return_value; +} + +void halrf_supportability_init_mp(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + switch (dm->support_ic_type) { + case ODM_RTL8814B: +#if (RTL8814B_SUPPORT == 1) + rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; +#endif + break; +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; + break; +#endif + +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + /*HAL_RF_TXGAPK |*/ + 0; + break; +#endif +#if (RTL8195B_SUPPORT == 1) + case ODM_RTL8195B: + rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + HAL_RF_DPK | + HAL_RF_TXGAPK | + 0; + break; +#endif + + default: + rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + /*HAL_RF_TXGAPK |*/ + 0; + break; + } + + RF_DBG(dm, DBG_RF_INIT, + "IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n", + dm->support_ic_type, rf->rf_supportability); +} + +void halrf_supportability_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + switch (dm->support_ic_type) { + case ODM_RTL8814B: +#if (RTL8814B_SUPPORT == 1) + rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; +#endif + break; +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; + break; +#endif + +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + /*HAL_RF_TXGAPK |*/ + 0; + break; +#endif +#if (RTL8195B_SUPPORT == 1) + case ODM_RTL8195B: + rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + HAL_RF_DPK | + HAL_RF_TXGAPK | + 0; + break; +#endif + + default: + rf->rf_supportability = + HAL_RF_TX_PWR_TRACK | + HAL_RF_IQK | + HAL_RF_LCK | + /*HAL_RF_DPK |*/ + 0; + break; + } + + RF_DBG(dm, DBG_RF_INIT, + "IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n", + dm->support_ic_type, rf->rf_supportability); +} + +void halrf_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if 0 + /*RF_DBG(dm, DBG_RF_TMP, "%s\n", __func__);*/ +#endif + + phydm_rf_watchdog(dm); +} + +#if 0 +void +halrf_iqk_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + switch (dm->support_ic_type) { +#if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + break; +#endif +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + _iq_calibrate_8822b_init(dm); + break; +#endif +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + break; +#endif + + default: + break; + } +} +#endif + +void halrf_iqk_trigger(void *dm_void, boolean is_recovery) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + struct dm_dpk_info *dpk_info = &dm->dpk_info; + struct _hal_rf_ *rf = &dm->rf_table; + u64 start_time; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (odm_check_power_status(dm) == false) + return; +#endif + + if (dm->mp_mode && + rf->is_con_tx && + rf->is_single_tone && + rf->is_carrier_suppresion) + if (*dm->mp_mode && + ((*rf->is_con_tx || + *rf->is_single_tone || + *rf->is_carrier_suppresion))) + return; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(rf->rf_supportability & HAL_RF_IQK)) + return; +#endif + +#if DISABLE_BB_RF + return; +#endif + + if (iqk_info->rfk_forbidden) + return; + + if (!dm->rf_calibrate_info.is_iqk_in_progress) { + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = true; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + start_time = odm_get_current_time(dm); + switch (dm->support_ic_type) { +#if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + phy_iq_calibrate_8188e(dm, is_recovery); + break; +#endif +#if (RTL8188F_SUPPORT == 1) + case ODM_RTL8188F: + phy_iq_calibrate_8188f(dm, is_recovery); + break; +#endif +#if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: + phy_iq_calibrate_8192e(dm, is_recovery); + break; +#endif +#if (RTL8197F_SUPPORT == 1) + case ODM_RTL8197F: + phy_iq_calibrate_8197f(dm, is_recovery); + break; +#endif +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + phy_iq_calibrate_8192f(dm, is_recovery); + break; +#endif +#if (RTL8703B_SUPPORT == 1) + case ODM_RTL8703B: + phy_iq_calibrate_8703b(dm, is_recovery); + break; +#endif +#if (RTL8710B_SUPPORT == 1) + case ODM_RTL8710B: + phy_iq_calibrate_8710b(dm, is_recovery); + break; +#endif +#if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + phy_iq_calibrate_8723b(dm, is_recovery); + break; +#endif +#if (RTL8723D_SUPPORT == 1) + case ODM_RTL8723D: + phy_iq_calibrate_8723d(dm, is_recovery); + break; +#endif +#if (RTL8812A_SUPPORT == 1) + case ODM_RTL8812: + phy_iq_calibrate_8812a(dm, is_recovery); + break; +#endif +#if (RTL8821A_SUPPORT == 1) + case ODM_RTL8821: + phy_iq_calibrate_8821a(dm, is_recovery); + break; +#endif +#if (RTL8814A_SUPPORT == 1) + case ODM_RTL8814A: + phy_iq_calibrate_8814a(dm, is_recovery); + break; +#endif +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + phy_iq_calibrate_8822b(dm, false, false); + break; +#endif +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + phy_iq_calibrate_8821c(dm, false, false); + break; +#endif +#if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + break; +#endif +#if (RTL8195B_SUPPORT == 1) + case ODM_RTL8195B: + phy_iq_calibrate_8195b(dm, false, false); + break; +#endif +#if (RTL8198F_SUPPORT == 1) + case ODM_RTL8198F: + phy_iq_calibrate_8198f(dm, false, false); + break; +#endif + + default: + break; + } + dm->rf_calibrate_info.iqk_progressing_time = + odm_get_progressing_time(dm, start_time); + RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK progressing_time = %lld ms\n", + dm->rf_calibrate_info.iqk_progressing_time); + + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + } else { + RF_DBG(dm, DBG_RF_IQK, + "== Return the IQK CMD, because RFKs in Progress ==\n"); + } +} + +void halrf_lck_trigger(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + struct _hal_rf_ *rf = &dm->rf_table; + u64 start_time; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (odm_check_power_status(dm) == false) + return; +#endif + + if (dm->mp_mode && + rf->is_con_tx && + rf->is_single_tone && + rf->is_carrier_suppresion) + if (*dm->mp_mode && + ((*rf->is_con_tx || + *rf->is_single_tone || + *rf->is_carrier_suppresion))) + return; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(rf->rf_supportability & HAL_RF_LCK)) + return; +#endif + +#if DISABLE_BB_RF + return; +#endif + if (iqk_info->rfk_forbidden) + return; + while (*dm->is_scan_in_process) { + RF_DBG(dm, DBG_RF_IQK, "[LCK]scan is in process, bypass LCK\n"); + return; + } + + if (!dm->rf_calibrate_info.is_lck_in_progress) { + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_lck_in_progress = true; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + start_time = odm_get_current_time(dm); + switch (dm->support_ic_type) { +#if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + phy_lc_calibrate_8188e(dm); + break; +#endif +#if (RTL8188F_SUPPORT == 1) + case ODM_RTL8188F: + phy_lc_calibrate_8188f(dm); + break; +#endif +#if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: + phy_lc_calibrate_8192e(dm); + break; +#endif +#if (RTL8197F_SUPPORT == 1) + case ODM_RTL8197F: + phy_lc_calibrate_8197f(dm); + break; +#endif +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + phy_lc_calibrate_8192f(dm); + break; +#endif +#if (RTL8703B_SUPPORT == 1) + case ODM_RTL8703B: + phy_lc_calibrate_8703b(dm); + break; +#endif +#if (RTL8710B_SUPPORT == 1) + case ODM_RTL8710B: + phy_lc_calibrate_8710b(dm); + break; +#endif +#if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + phy_lc_calibrate_8723b(dm); + break; +#endif +#if (RTL8723D_SUPPORT == 1) + case ODM_RTL8723D: + phy_lc_calibrate_8723d(dm); + break; +#endif +#if (RTL8812A_SUPPORT == 1) + case ODM_RTL8812: + phy_lc_calibrate_8812a(dm); + break; +#endif +#if (RTL8821A_SUPPORT == 1) + case ODM_RTL8821: + phy_lc_calibrate_8821a(dm); + break; +#endif +#if (RTL8814A_SUPPORT == 1) + case ODM_RTL8814A: + phy_lc_calibrate_8814a(dm); + break; +#endif +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + phy_lc_calibrate_8822b(dm); + break; +#endif +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + phy_lc_calibrate_8821c(dm); + break; +#endif +#if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + break; +#endif + default: + break; + } + dm->rf_calibrate_info.lck_progressing_time = + odm_get_progressing_time(dm, start_time); + RF_DBG(dm, DBG_RF_IQK, "[IQK]LCK progressing_time = %lld ms\n", + dm->rf_calibrate_info.lck_progressing_time); +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + halrf_lck_dbg(dm); +#endif + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_lck_in_progress = false; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + } else { + RF_DBG(dm, DBG_RF_IQK, + "= Return the LCK CMD, because RFK is in Progress =\n"); + } +} + +void halrf_aac_check(struct dm_struct *dm) +{ + switch (dm->support_ic_type) { +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: +#if 0 + aac_check_8821c(dm); +#endif + break; +#endif +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: +#if 1 + aac_check_8822b(dm); +#endif + break; +#endif + default: + break; + } +} + +void halrf_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + RF_DBG(dm, DBG_RF_INIT, "HALRF_Init\n"); + rf->aac_checked = false; + halrf_init_debug_setting(dm); + + if (*dm->mp_mode) + halrf_supportability_init_mp(dm); + else + halrf_supportability_init(dm); + + /*Init all RF funciton*/ + halrf_aac_check(dm); +} + +void halrf_dpk_trigger(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + u64 start_time; + + start_time = odm_get_current_time(dm); + + switch (dm->support_ic_type) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8197F_SUPPORT == 1) + case ODM_RTL8197F: + do_dpk_8197f(dm); + break; +#endif +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + do_dpk_8192f(dm); + break; +#endif + +#if (RTL8198F_SUPPORT == 1) + case ODM_RTL8198F: + do_dpk_8198f(dm); + break; +#endif + +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT)) +#if (RTL8195B_SUPPORT == 1) + case ODM_RTL8195B: + do_dpk_8195b(dm, false); + break; +#endif +#endif + + default: + break; + } + rf->dpk_progressing_time = odm_get_progressing_time(dm, start_time); + RF_DBG(dm, DBG_RF_DPK, "[DPK]DPK progressing_time = %lld ms\n", + rf->dpk_progressing_time); +} + +u8 halrf_dpk_result_check(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_dpk_info *dpk_info = &dm->dpk_info; + + u8 result = 0; + + switch (dm->support_ic_type) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#if (RTL8197F_SUPPORT == 1) + case ODM_RTL8197F: + if (dpk_info->dpk_path_ok == 0x3) + result = 1; + else + result = 0; + break; +#endif + +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + if (dpk_info->dpk_path_ok == 0x3) + result = 1; + else + result = 0; + break; +#endif + +#if (RTL8198F_SUPPORT == 1) + case ODM_RTL8198F: + if (dpk_info->dpk_path_ok == 0xf) + result = 1; + else + result = 0; + break; +#endif + +#endif + default: + break; + } + return result; +} + +void halrf_dpk_sram_read(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + u8 path, group; + + switch (dm->support_ic_type) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#if (RTL8197F_SUPPORT == 1) + case ODM_RTL8197F: + dpk_sram_read_8197f(dm); + break; +#endif + +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + dpk_sram_read_8192f(dm); + break; +#endif + +#if (RTL8198F_SUPPORT == 1) + case ODM_RTL8198F: + dpk_sram_read_8198f(dm); + break; +#endif + +#endif + default: + break; + } +} + +void halrf_dpk_enable_disable(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + switch (dm->support_ic_type) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#if (RTL8197F_SUPPORT == 1) + case ODM_RTL8197F: + phy_dpk_enable_disable_8197f(dm); + break; +#endif +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + phy_dpk_enable_disable_8192f(dm); + break; +#endif + +#if (RTL8198F_SUPPORT == 1) + case ODM_RTL8198F: + dpk_enable_disable_8198f(dm); + break; +#endif + +#endif + default: + break; + } +} + +void halrf_dpk_track(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_dpk_info *dpk_info = &dm->dpk_info; + + switch (dm->support_ic_type) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#if (RTL8197F_SUPPORT == 1) + case ODM_RTL8197F: + phy_dpk_track_8197f(dm); + break; +#endif + +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + phy_dpk_track_8192f(dm); + break; +#endif + +#if (RTL8198F_SUPPORT == 1) + case ODM_RTL8198F: + dpk_track_8198f(dm); + break; +#endif + +#endif + default: + break; + } +} + +void halrf_dpk_reload(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_dpk_info *dpk_info = &dm->dpk_info; + + switch (dm->support_ic_type) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#if (RTL8197F_SUPPORT == 1) + case ODM_RTL8197F: + if (dpk_info->dpk_path_ok > 0) + dpk_reload_8197f(dm); + break; +#endif + +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + if (dpk_info->dpk_path_ok > 0) + dpk_reload_8192f(dm); + + break; +#endif + +#if (RTL8198F_SUPPORT == 1) + case ODM_RTL8198F: + if (dpk_info->dpk_path_ok > 0) + dpk_reload_8198f(dm); + break; +#endif + +#endif + default: + break; + } +} + +enum hal_status +halrf_config_rfk_with_header_file(void *dm_void, u32 config_type) +{ +#if (RTL8198F_SUPPORT == 1) + struct dm_struct *dm = (struct dm_struct *)dm_void; +#endif + enum hal_status result = HAL_STATUS_SUCCESS; +#if 0 +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + if (config_type == CONFIG_BB_RF_CAL_INIT) + odm_read_and_config_mp_8822b_cal_init(dm); + } +#endif +#endif + +#if 1 +#if (RTL8198F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8198F) { + if (config_type == CONFIG_BB_RF_CAL_INIT) + odm_read_and_config_mp_8198f_cal_init(dm); + } +#endif +#endif + return result; +} diff --git a/hal/phydm/halrf/halrf.h b/hal/phydm/halrf/halrf.h new file mode 100644 index 0000000..52404e6 --- /dev/null +++ b/hal/phydm/halrf/halrf.h @@ -0,0 +1,471 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_H__ +#define __HALRF_H__ + +/*============================================================*/ +/*include files*/ +/*============================================================*/ +#include "halrf/halrf_psd.h" +#if (RTL8822B_SUPPORT == 1) +#include "halrf/rtl8822b/halrf_rfk_init_8822b.h" +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#if (RTL8198F_SUPPORT == 1) +#include "halrf/rtl8198f/halrf_rfk_init_8198f.h" +#endif +#endif + +/*============================================================*/ +/*Definition */ +/*============================================================*/ +/*IQK version*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +#define IQK_VER_8188E "0x14" +#define IQK_VER_8192E "0x01" +#define IQK_VER_8192F "0x01" +#define IQK_VER_8723B "0x1e" +#define IQK_VER_8812A "0x01" +#define IQK_VER_8821A "0x01" +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +#define IQK_VER_8188E "0x01" +#define IQK_VER_8192E "0x01" +#define IQK_VER_8192F "0x01" +#define IQK_VER_8723B "0x1e" +#define IQK_VER_8812A "0x01" +#define IQK_VER_8821A "0x01" +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#define IQK_VER_8188E "0x01" +#define IQK_VER_8192E "0x01" +#define IQK_VER_8192F "0x01" +#define IQK_VER_8723B "0x1e" +#define IQK_VER_8812A "0x01" +#define IQK_VER_8821A "0x01" +#elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT)) +#define IQK_VER_8188E "0x01" +#define IQK_VER_8192E "0x01" +#define IQK_VER_8192F "0x01" +#define IQK_VER_8723B "0x1e" +#define IQK_VER_8812A "0x01" +#define IQK_VER_8821A "0x01" +#endif +#define IQK_VER_8814A "0x0f" +#define IQK_VER_8188F "0x01" +#define IQK_VER_8197F "0x1c" +#define IQK_VER_8703B "0x05" +#define IQK_VER_8710B "0x01" +#define IQK_VER_8723D "0x02" +#define IQK_VER_8822B "0x2f" +#define IQK_VER_8821C "0x23" +#define IQK_VER_8198F "0x06" + +/*LCK version*/ +#define LCK_VER_8188E "0x01" +#define LCK_VER_8192E "0x01" +#define LCK_VER_8192F "0x01" +#define LCK_VER_8723B "0x01" +#define LCK_VER_8812A "0x01" +#define LCK_VER_8821A "0x01" +#define LCK_VER_8814A "0x01" +#define LCK_VER_8188F "0x01" +#define LCK_VER_8197F "0x01" +#define LCK_VER_8703B "0x01" +#define LCK_VER_8710B "0x01" +#define LCK_VER_8723D "0x01" +#define LCK_VER_8822B "0x01" +#define LCK_VER_8821C "0x02" + +/*power tracking version*/ +#define PWRTRK_VER_8188E "0x01" +#define PWRTRK_VER_8192E "0x01" +#define PWRTRK_VER_8192F "0x01" +#define PWRTRK_VER_8723B "0x01" +#define PWRTRK_VER_8812A "0x01" +#define PWRTRK_VER_8821A "0x01" +#define PWRTRK_VER_8814A "0x01" +#define PWRTRK_VER_8188F "0x01" +#define PWRTRK_VER_8197F "0x01" +#define PWRTRK_VER_8703B "0x01" +#define PWRTRK_VER_8710B "0x01" +#define PWRTRK_VER_8723D "0x01" +#define PWRTRK_VER_8822B "0x01" +#define PWRTRK_VER_8821C "0x01" + +/*DPK tracking version*/ +#define DPK_VER_8188E "NONE" +#define DPK_VER_8192E "NONE" +#define DPK_VER_8723B "NONE" +#define DPK_VER_8812A "NONE" +#define DPK_VER_8821A "NONE" +#define DPK_VER_8814A "NONE" +#define DPK_VER_8188F "NONE" +#define DPK_VER_8197F "0x07" +#define DPK_VER_8703B "NONE" +#define DPK_VER_8710B "NONE" +#define DPK_VER_8723D "NONE" +#define DPK_VER_8822B "NONE" +#define DPK_VER_8821C "NONE" +#define DPK_VER_8192F "0x0a" +#define DPK_VER_8198F "0x06" + +/*RFK_INIT version*/ +#define RFK_INIT_VER_8822B "0x8" +#define RFK_INIT_VER_8195B "0x1" +#define RFK_INIT_VER_8198F "0x5" + +/*Kfree tracking version*/ +#define KFREE_VER_8188E \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8192E \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8192F \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8723B \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8812A \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8821A \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8814A \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8188F \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8197F \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8703B \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8710B \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8723D \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8822B \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" +#define KFREE_VER_8821C \ + (dm->power_trim_data.flag & KFREE_FLAG_ON) ? "0x01" : "NONE" + +/*PA Bias Calibration version*/ +#define PABIASK_VER_8188E \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8192E \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8192F \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8723B \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8812A \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8821A \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8814A \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8188F \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8197F \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8703B \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8710B \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8723D \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8822B \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" +#define PABIASK_VER_8821C \ + (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON) ? "0x01" : "NONE" + +#define HALRF_IQK_VER \ + (dm->support_ic_type == ODM_RTL8188E) ? IQK_VER_8188E : \ + (dm->support_ic_type == ODM_RTL8192E) ? IQK_VER_8192E : \ + (dm->support_ic_type == ODM_RTL8192F) ? IQK_VER_8192F : \ + (dm->support_ic_type == ODM_RTL8723B) ? IQK_VER_8723B : \ + (dm->support_ic_type == ODM_RTL8812) ? IQK_VER_8812A : \ + (dm->support_ic_type == ODM_RTL8821) ? IQK_VER_8821A : \ + (dm->support_ic_type == ODM_RTL8814A) ? IQK_VER_8814A : \ + (dm->support_ic_type == ODM_RTL8188F) ? IQK_VER_8188F : \ + (dm->support_ic_type == ODM_RTL8197F) ? IQK_VER_8197F : \ + (dm->support_ic_type == ODM_RTL8703B) ? IQK_VER_8703B : \ + (dm->support_ic_type == ODM_RTL8710B) ? IQK_VER_8710B : \ + (dm->support_ic_type == ODM_RTL8723D) ? IQK_VER_8723D : \ + (dm->support_ic_type == ODM_RTL8822B) ? IQK_VER_8822B : \ + (dm->support_ic_type == ODM_RTL8821C) ? IQK_VER_8821C : "unknown" + +#define HALRF_LCK_VER \ + (dm->support_ic_type == ODM_RTL8188E) ? LCK_VER_8188E : \ + (dm->support_ic_type == ODM_RTL8192E) ? LCK_VER_8192E : \ + (dm->support_ic_type == ODM_RTL8192F) ? LCK_VER_8192F : \ + (dm->support_ic_type == ODM_RTL8723B) ? LCK_VER_8723B : \ + (dm->support_ic_type == ODM_RTL8812) ? LCK_VER_8812A : \ + (dm->support_ic_type == ODM_RTL8821) ? LCK_VER_8821A : \ + (dm->support_ic_type == ODM_RTL8814A) ? LCK_VER_8814A : \ + (dm->support_ic_type == ODM_RTL8188F) ? LCK_VER_8188F : \ + (dm->support_ic_type == ODM_RTL8197F) ? LCK_VER_8197F : \ + (dm->support_ic_type == ODM_RTL8703B) ? LCK_VER_8703B : \ + (dm->support_ic_type == ODM_RTL8710B) ? LCK_VER_8710B : \ + (dm->support_ic_type == ODM_RTL8723D) ? LCK_VER_8723D : \ + (dm->support_ic_type == ODM_RTL8822B) ? LCK_VER_8822B : \ + (dm->support_ic_type == ODM_RTL8821C) ? LCK_VER_8821C : "unknown" + +#define HALRF_POWRTRACKING_VER \ + (dm->support_ic_type == ODM_RTL8188E) ? PWRTRK_VER_8188E : \ + (dm->support_ic_type == ODM_RTL8192E) ? PWRTRK_VER_8192E : \ + (dm->support_ic_type == ODM_RTL8192F) ? PWRTRK_VER_8192F : \ + (dm->support_ic_type == ODM_RTL8723B) ? PWRTRK_VER_8723B : \ + (dm->support_ic_type == ODM_RTL8812) ? PWRTRK_VER_8812A : \ + (dm->support_ic_type == ODM_RTL8821) ? PWRTRK_VER_8821A : \ + (dm->support_ic_type == ODM_RTL8814A) ? PWRTRK_VER_8814A : \ + (dm->support_ic_type == ODM_RTL8188F) ? PWRTRK_VER_8188F : \ + (dm->support_ic_type == ODM_RTL8197F) ? PWRTRK_VER_8197F : \ + (dm->support_ic_type == ODM_RTL8703B) ? PWRTRK_VER_8703B : \ + (dm->support_ic_type == ODM_RTL8710B) ? PWRTRK_VER_8710B : \ + (dm->support_ic_type == ODM_RTL8723D) ? PWRTRK_VER_8723D : \ + (dm->support_ic_type == ODM_RTL8822B) ? PWRTRK_VER_8822B : \ + (dm->support_ic_type == ODM_RTL8821C) ? PWRTRK_VER_8821C : "unknown" + +#define HALRF_DPK_VER \ + (dm->support_ic_type == ODM_RTL8188E) ? DPK_VER_8188E : \ + (dm->support_ic_type == ODM_RTL8192E) ? DPK_VER_8192E : \ + (dm->support_ic_type == ODM_RTL8192F) ? DPK_VER_8192F : \ + (dm->support_ic_type == ODM_RTL8723B) ? DPK_VER_8723B : \ + (dm->support_ic_type == ODM_RTL8812) ? DPK_VER_8812A : \ + (dm->support_ic_type == ODM_RTL8821) ? DPK_VER_8821A : \ + (dm->support_ic_type == ODM_RTL8814A) ? DPK_VER_8814A : \ + (dm->support_ic_type == ODM_RTL8188F) ? DPK_VER_8188F : \ + (dm->support_ic_type == ODM_RTL8197F) ? DPK_VER_8197F : \ + (dm->support_ic_type == ODM_RTL8198F) ? DPK_VER_8198F : \ + (dm->support_ic_type == ODM_RTL8703B) ? DPK_VER_8703B : \ + (dm->support_ic_type == ODM_RTL8710B) ? DPK_VER_8710B : \ + (dm->support_ic_type == ODM_RTL8723D) ? DPK_VER_8723D : \ + (dm->support_ic_type == ODM_RTL8822B) ? DPK_VER_8822B : \ + (dm->support_ic_type == ODM_RTL8821C) ? DPK_VER_8821C : "unknown" + +#define HALRF_KFREE_VER \ + (dm->support_ic_type == ODM_RTL8188E) ? KFREE_VER_8188E : \ + (dm->support_ic_type == ODM_RTL8192E) ? KFREE_VER_8192E : \ + (dm->support_ic_type == ODM_RTL8192F) ? KFREE_VER_8192F : \ + (dm->support_ic_type == ODM_RTL8723B) ? KFREE_VER_8723B : \ + (dm->support_ic_type == ODM_RTL8812) ? KFREE_VER_8812A : \ + (dm->support_ic_type == ODM_RTL8821) ? KFREE_VER_8821A : \ + (dm->support_ic_type == ODM_RTL8814A) ? KFREE_VER_8814A : \ + (dm->support_ic_type == ODM_RTL8188F) ? KFREE_VER_8188F : \ + (dm->support_ic_type == ODM_RTL8197F) ? KFREE_VER_8197F : \ + (dm->support_ic_type == ODM_RTL8703B) ? KFREE_VER_8703B : \ + (dm->support_ic_type == ODM_RTL8710B) ? KFREE_VER_8710B : \ + (dm->support_ic_type == ODM_RTL8723D) ? KFREE_VER_8723D : \ + (dm->support_ic_type == ODM_RTL8822B) ? KFREE_VER_8822B : \ + (dm->support_ic_type == ODM_RTL8821C) ? KFREE_VER_8821C : "unknown" + +#define HALRF_PABIASK_VER \ + (dm->support_ic_type == ODM_RTL8188E) ? PABIASK_VER_8188E : \ + (dm->support_ic_type == ODM_RTL8192E) ? PABIASK_VER_8192E : \ + (dm->support_ic_type == ODM_RTL8192F) ? PABIASK_VER_8192F : \ + (dm->support_ic_type == ODM_RTL8723B) ? PABIASK_VER_8723B : \ + (dm->support_ic_type == ODM_RTL8812) ? PABIASK_VER_8812A : \ + (dm->support_ic_type == ODM_RTL8821) ? PABIASK_VER_8821A : \ + (dm->support_ic_type == ODM_RTL8814A) ? PABIASK_VER_8814A : \ + (dm->support_ic_type == ODM_RTL8188F) ? PABIASK_VER_8188F : \ + (dm->support_ic_type == ODM_RTL8197F) ? PABIASK_VER_8197F : \ + (dm->support_ic_type == ODM_RTL8703B) ? PABIASK_VER_8703B : \ + (dm->support_ic_type == ODM_RTL8710B) ? PABIASK_VER_8710B : \ + (dm->support_ic_type == ODM_RTL8723D) ? PABIASK_VER_8723D : \ + (dm->support_ic_type == ODM_RTL8822B) ? PABIASK_VER_8822B : \ + (dm->support_ic_type == ODM_RTL8821C) ? PABIASK_VER_8821C : "unknown" + +#define HALRF_RFK_INIT_VER \ + (dm->support_ic_type == ODM_RTL8822B) ? RFK_INIT_VER_8822B : "unknown" + +#define IQK_THRESHOLD 8 +#define DPK_THRESHOLD 4 + +/*===========================================================*/ +/*AGC RX High Power mode*/ +/*===========================================================*/ +#define lna_low_gain_1 0x64 +#define lna_low_gain_2 0x5A +#define lna_low_gain_3 0x58 + +/*============================================================*/ +/* enumeration */ +/*============================================================*/ + +enum halrf_func_idx { /*F_XXX = PHYDM XXX function*/ + RF00_PWR_TRK = 0, + RF01_IQK = 1, + RF02_LCK = 2, + RF03_DPK = 3, + RF04_TXGAPK = 4, +}; + +enum halrf_ability { + HAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK), + HAL_RF_IQK = BIT(RF01_IQK), + HAL_RF_LCK = BIT(RF02_LCK), + HAL_RF_DPK = BIT(RF03_DPK), + HAL_RF_TXGAPK = BIT(RF04_TXGAPK) +}; + +enum halrf_dbg_comp { + DBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK), + DBG_RF_IQK = BIT(RF01_IQK), + DBG_RF_LCK = BIT(RF02_LCK), + DBG_RF_DPK = BIT(RF03_DPK), + DBG_RF_TXGAPK = BIT(RF04_TXGAPK), + DBG_RF_MP = BIT(29), + DBG_RF_TMP = BIT(30), + DBG_RF_INIT = BIT(31) +}; + +enum halrf_cmninfo_init { + HALRF_CMNINFO_ABILITY = 0, + HALRF_CMNINFO_DPK_EN = 1, + HALRF_CMNINFO_EEPROM_THERMAL_VALUE, + HALRF_CMNINFO_RFK_FORBIDDEN, + HALRF_CMNINFO_IQK_SEGMENT, + HALRF_CMNINFO_RATE_INDEX, + HALRF_CMNINFO_PWT_TYPE, + HALRF_CMNINFO_MP_PSD_POINT, + HALRF_CMNINFO_MP_PSD_START_POINT, + HALRF_CMNINFO_MP_PSD_STOP_POINT, + HALRF_CMNINFO_MP_PSD_AVERAGE +}; + +enum halrf_cmninfo_hook { + HALRF_CMNINFO_CON_TX, + HALRF_CMNINFO_SINGLE_TONE, + HALRF_CMNINFO_CARRIER_SUPPRESSION, + HALRF_CMNINFO_MP_RATE_INDEX +}; + +enum halrf_lna_set { + HALRF_LNA_DISABLE = 0, + HALRF_LNA_ENABLE = 1, +}; + +/*============================================================*/ +/* structure */ +/*============================================================*/ + +struct _hal_rf_ { + /*hook*/ + u8 *test1; + + /*update*/ + u32 rf_supportability; + + u8 eeprom_thermal; + u8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/ + boolean dpk_done; + u64 dpk_progressing_time; + u32 fw_ver; + + boolean *is_con_tx; + boolean *is_single_tone; + boolean *is_carrier_suppresion; + boolean aac_checked; + + u8 *mp_rate_index; + u32 p_rate_index; + u8 pwt_type; + u32 rf_dbg_comp; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _halrf_psd_data halrf_psd_data; +#endif +}; + +/*============================================================*/ +/* function prototype */ +/*============================================================*/ + +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\ + RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1) +void halrf_iqk_info_dump(void *dm_void, u32 *_used, char *output, + u32 *_out_len); + +void halrf_iqk_hwtx_check(void *dm_void, boolean is_check); +#endif + +u8 halrf_match_iqk_version(void *dm_void); + +void halrf_support_ability_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void halrf_cmn_info_init(void *dm_void, enum halrf_cmninfo_init cmn_info, + u32 value); + +void halrf_cmn_info_hook(void *dm_void, enum halrf_cmninfo_hook cmn_info, + void *value); + +void halrf_cmn_info_set(void *dm_void, u32 cmn_info, u64 value); + +u64 halrf_cmn_info_get(void *dm_void, u32 cmn_info); + +void halrf_watchdog(void *dm_void); + +void halrf_supportability_init(void *dm_void); + +void halrf_init(void *dm_void); + +void halrf_iqk_trigger(void *dm_void, boolean is_recovery); + +void halrf_segment_iqk_trigger(void *dm_void, boolean clear, + boolean segment_iqk); + +void halrf_lck_trigger(void *dm_void); + +void halrf_iqk_debug(void *dm_void, u32 *const dm_value, u32 *_used, + char *output, u32 *_out_len); + +void phydm_get_iqk_cfir(void *dm_void, u8 idx, u8 path, boolean debug); + +void halrf_iqk_xym_read(void *dm_void, u8 path, u8 xym_type); + +void halrf_rf_lna_setting(void *dm_void, enum halrf_lna_set type); + +void halrf_do_imr_test(void *dm_void, u8 data); + +u32 halrf_psd_log2base(u32 val); + +void halrf_dpk_trigger(void *dm_void); + +u8 halrf_dpk_result_check(void *dm_void); + +void halrf_dpk_sram_read(void *dm_void); + +void halrf_dpk_enable_disable(void *dm_void); + +void halrf_dpk_track(void *dm_void); + +void halrf_dpk_reload(void *dm_void); + +enum hal_status +halrf_config_rfk_with_header_file(void *dm_void, u32 config_type); + +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\ + RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1) +void halrf_iqk_dbg(void *dm_void); +#endif + +#endif /*#ifndef __HALRF_H__*/ diff --git a/hal/phydm/halrf/halrf_debug.c b/hal/phydm/halrf/halrf_debug.c new file mode 100644 index 0000000..8bd6809 --- /dev/null +++ b/hal/phydm/halrf/halrf_debug.c @@ -0,0 +1,259 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ + */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void halrf_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + /* HAL RF version List */ + PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n", + "% HAL RF version %"); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Power Tracking", HALRF_POWRTRACKING_VER); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s %s\n", "IQK", + (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW" : + HALRF_IQK_VER, + (halrf_match_iqk_version(dm_void)) ? "(match)" : "(mismatch)"); + + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "LCK", HALRF_LCK_VER); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "DPK", HALRF_DPK_VER); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "KFREE", HALRF_KFREE_VER); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "TX 2G Current Calibration", HALRF_PABIASK_VER); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "RFK Init. Parameter", HALRF_RFK_INIT_VER); + + *_used = used; + *_out_len = out_len; +#endif +} + +void halrf_debug_trace(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + u32 one = 1; + u32 used = *_used; + u32 out_len = *_out_len; + u32 rf_var[10] = {0}; + u8 i; + + for (i = 0; i < 5; i++) + if (input[i + 1]) + PHYDM_SSCANF(input[i + 2], DCMD_DECIMAL, &rf_var[i]); + + if (rf_var[0] == 100) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n[DBG MSG] RF Selection\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))TX_PWR_TRACK\n", + ((rf->rf_dbg_comp & DBG_RF_TX_PWR_TRACK) ? ("V") : + ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))IQK\n", + ((rf->rf_dbg_comp & DBG_RF_IQK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "02. (( %s ))LCK\n", + ((rf->rf_dbg_comp & DBG_RF_LCK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "03. (( %s ))DPK\n", + ((rf->rf_dbg_comp & DBG_RF_DPK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "04. (( %s ))TXGAPK\n", + ((rf->rf_dbg_comp & DBG_RF_TXGAPK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "29. (( %s ))MP\n", + ((rf->rf_dbg_comp & DBG_RF_MP) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "30. (( %s ))TMP\n", + ((rf->rf_dbg_comp & DBG_RF_TMP) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "31. (( %s ))INIT\n", + ((rf->rf_dbg_comp & DBG_RF_INIT) ? ("V") : ("."))); + + } else if (rf_var[0] == 101) { + rf->rf_dbg_comp = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable all DBG COMP\n"); + } else { + if (rf_var[1] == 1) /*enable*/ + rf->rf_dbg_comp |= (one << rf_var[0]); + else if (rf_var[1] == 2) /*disable*/ + rf->rf_dbg_comp &= ~(one << rf_var[0]); + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "\nCurr-RF_Dbg_Comp = 0x%x\n", rf->rf_dbg_comp); + + *_used = used; + *_out_len = out_len; +} + +struct halrf_command { + char name[16]; + u8 id; +}; + +enum halrf_CMD_ID { + HALRF_HELP, + HALRF_SUPPORTABILITY, + HALRF_DBG_COMP, + HALRF_PROFILE, + HALRF_IQK_INFO, + HALRF_IQK, + HALRF_IQK_DEBUG, +}; + +struct halrf_command halrf_cmd_ary[] = { + {"-h", HALRF_HELP}, + {"ability", HALRF_SUPPORTABILITY}, + {"dbg", HALRF_DBG_COMP}, + {"profile", HALRF_PROFILE}, + {"iqk_info", HALRF_IQK_INFO}, + {"iqk", HALRF_IQK}, + {"iqk_dbg", HALRF_IQK_DEBUG}, +}; + +void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len, u32 input_num) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + u8 id = 0; + u32 rf_var[10] = {0}; + u32 i, input_idx = 0; + u32 halrf_ary_size = + sizeof(halrf_cmd_ary) / sizeof(struct halrf_command); + u32 used = *_used; + u32 out_len = *_out_len; + + /* Parsing Cmd ID */ + for (i = 0; i < halrf_ary_size; i++) { + if (strcmp(halrf_cmd_ary[i].name, input[1]) == 0) { + id = halrf_cmd_ary[i].id; + break; + } + } + + if (i == halrf_ary_size) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "RF Cmd not found\n"); + return; + } + + switch (id) { + case HALRF_HELP: + PDM_SNPF(out_len, used, output + used, out_len - used, + "RF cmd ==>\n"); + + for (i = 0; i < halrf_ary_size - 1; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-5d: %s\n", i, halrf_cmd_ary[i + 1].name); + } + break; + case HALRF_SUPPORTABILITY: + halrf_support_ability_debug(dm, &input[0], &used, output, + &out_len); + break; + case HALRF_DBG_COMP: + halrf_debug_trace(dm, &input[0], &used, output, &out_len); + break; + case HALRF_PROFILE: + halrf_basic_profile(dm, &used, output, &out_len); + break; + case HALRF_IQK_INFO: +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + halrf_iqk_info_dump(dm, &used, output, &out_len); +#endif + break; + case HALRF_IQK: + PDM_SNPF(out_len, used, output + used, out_len - used, + "TRX IQK Trigger\n"); + halrf_iqk_trigger(dm, false); +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + halrf_iqk_info_dump(dm, &used, output, &out_len); +#endif + break; + case HALRF_IQK_DEBUG: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 2], DCMD_HEX, + &rf_var[i]); + input_idx++; + } + } + + if (input_idx >= 1) { +#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) + halrf_iqk_debug(dm, (u32 *)rf_var, &used, + output, &out_len); +#endif + } + break; + default: + break; + } + + *_used = used; + *_out_len = out_len; +#endif +} + +void halrf_init_debug_setting(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + rf->rf_dbg_comp = +#if DBG +#if 0 + /*DBG_RF_TX_PWR_TRACK |*/ + /*DBG_RF_IQK | */ + /*DBG_RF_LCK | */ + /*DBG_RF_DPK | */ + /*DBG_RF_TXGAPK | */ + /*DBG_RF_TMP | */ + /*DBG_RF_INIT | */ +#endif +#endif + 0; +} diff --git a/hal/phydm/halrf/halrf_debug.h b/hal/phydm/halrf/halrf_debug.h new file mode 100644 index 0000000..bd204bf --- /dev/null +++ b/hal/phydm/halrf/halrf_debug.h @@ -0,0 +1,123 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_DEBUG_H__ +#define __HALRF_DEBUG_H__ + +/*============================================================*/ +/*include files*/ +/*============================================================*/ + +/*============================================================*/ +/*Definition */ +/*============================================================*/ + +#if DBG + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#define RF_DBG(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->rf_table.rf_dbg_comp) { \ + pr_debug("[RF] "); \ + RT_PRINTK(fmt, ##args); \ + } \ + } while (0) + +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +static __inline void RF_DBG(PDM_ODM_T dm, int comp, char *fmt, ...) +{ + RT_STATUS rt_status; + va_list args; + char buf[PRINT_MAX_SIZE] = {0}; + + if ((comp & dm->rf_table.rf_dbg_comp) == 0) + return; + + if (fmt == NULL) + return; + + va_start(args, fmt); + rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args); + va_end(args); + + if (rt_status != RT_STATUS_SUCCESS) { + DbgPrint("Failed (%d) to print message to buffer\n", rt_status); + return; + } + + DbgPrint("[RF] %s", buf); +} + +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + +#define RF_DBG(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->rf_table.rf_dbg_comp) { \ + RT_DEBUG(COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args); \ + } \ + } while (0) + +#else +#define RF_DBG(dm, comp, fmt, args...) \ + do { \ + struct dm_struct *__dm = dm; \ + if ((comp) & __dm->rf_table.rf_dbg_comp) { \ + RT_TRACE(((struct rtl_priv *)__dm->adapter), \ + COMP_PHYDM, DBG_DMESG, "[RF] " fmt, ##args); \ + } \ + } while (0) +#endif + +#else /*#if DBG*/ + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +static __inline void RF_DBG(struct dm_struct *dm, int comp, char *fmt, ...) +{ +} +#else +#define RF_DBG(dm, comp, fmt, args...) +#endif + +#endif /*#if DBG*/ + +/*============================================================*/ +/* enumeration */ +/*============================================================*/ + +/*============================================================*/ +/* structure */ +/*============================================================*/ + +/*============================================================*/ +/* function prototype */ +/*============================================================*/ + +void halrf_cmd_parser(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len, u32 input_num); + +void halrf_init_debug_setting(void *dm_void); + +#endif /*#ifndef __HALRF_H__*/ diff --git a/hal/phydm/halrf/halrf_dpk.h b/hal/phydm/halrf/halrf_dpk.h new file mode 100644 index 0000000..ccfcf39 --- /dev/null +++ b/hal/phydm/halrf/halrf_dpk.h @@ -0,0 +1,74 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_DPK_H__ +#define __HALRF_DPK_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define GAIN_LOSS 1 +#define DO_DPK 2 +#define DPK_ON 3 +#define AVG_THERMAL_NUM 8 +#define AVG_THERMAL_NUM_DPK 8 +#define THERMAL_DPK_AVG_NUM 4 + +/*---------------------------End Define Parameters---------------------------*/ + +struct dm_dpk_info { + + boolean is_dpk_enable; + /*boolean is_dpk_path_ok[4];*/ /*path*/ + u16 dpk_path_ok; + /*BIT(15)~BIT(12) : 5G reserved, BIT(11)~BIT(8) 5G_S3~5G_S0*/ + /*BIT(7)~BIT(4) : 2G reserved, BIT(3)~BIT(0) 2G_S3~2G_S0*/ + +#if (RTL8198F_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8197F_SUPPORT == 1) + /*2G DPK data*/ + u8 dpk_result[4][3]; /*path/group*/ + u8 pwsf_2g[4][3]; /*path/group*/ + u32 lut_2g_even[4][3][64]; /*path/group/LUT data*/ + u32 lut_2g_odd[4][3][64]; /*path/group/LUT data*/ +#if 0 + /*5G DPK data*/ + u8 dpk_5g_result[4][9]; /*path/group*/ + u8 pwsf_5g[4][9]; /*path/group*/ + u32 lut_5g_even[4][9][64]; /*path/group/LUT data*/ + u32 lut_5g_odd[4][9][64]; /*path/group/LUT data*/ +#endif + u8 thermal_dpk; + u8 thermal_dpk_avg[AVG_THERMAL_NUM_DPK]; + u8 thermal_dpk_avg_index; + +#endif + +#if (RTL8195B_SUPPORT == 1) + u32 sram_even[7][64]; + u32 sram_odd[7][64]; + boolean dpk_result[7]; + u32 dpk_pwsf[7]; +#endif +}; + +#endif /*#ifndef __HALRF_DPK_H__*/ diff --git a/hal/phydm/halrf/halrf_features.h b/hal/phydm/halrf/halrf_features.h new file mode 100644 index 0000000..da97614 --- /dev/null +++ b/hal/phydm/halrf/halrf_features.h @@ -0,0 +1,43 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_FEATURES_H__ +#define __HALRF_FEATURES_H__ + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#define CONFIG_HALRF_POWERTRACKING 1 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + +#define CONFIG_HALRF_POWERTRACKING 1 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +#define CONFIG_HALRF_POWERTRACKING 1 + +#endif + +#endif /*#ifndef __HALRF_FEATURES_H__*/ diff --git a/hal/phydm/halrf/halrf_iqk.h b/hal/phydm/halrf/halrf_iqk.h new file mode 100644 index 0000000..ff0e548 --- /dev/null +++ b/hal/phydm/halrf/halrf_iqk.h @@ -0,0 +1,92 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_IQK_H__ +#define __HALRF_IQK_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define LOK_delay 1 +#define WBIQK_delay 10 +#define TX_IQK 0 +#define RX_IQK 1 +#define TXIQK 0 +#define RXIQK1 1 +#define RXIQK2 2 +#define kcount_limit_80m 2 +#define kcount_limit_others 4 +#define rxiqk_gs_limit 10 + +#define NUM 4 +/*-----------------------End Define Parameters-----------------------*/ + +struct dm_iqk_info { + boolean lok_fail[NUM]; + boolean iqk_fail[2][NUM]; + u32 iqc_matrix[2][NUM]; + u8 iqk_times; + u32 rf_reg18; + u32 rf_reg08; + u32 lna_idx; + u8 iqk_step; + u8 rxiqk_step; + u8 tmp1bcc; + u8 kcount; + u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/ + boolean rfk_forbidden; +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\ + RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1) + u32 iqk_channel[2]; + boolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */ + /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ + /*channel index = 2 is just for debug*/ + u32 iqk_cfir_real[3][4][2][8]; + /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ + /*channel index = 2 is just for debug*/ + u32 iqk_cfir_imag[3][4][2][8]; + u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */ + u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */ + /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */ + u8 rxiqk_fail_code[2][4]; + u32 lok_idac[2][4]; /*channel / path*/ + u16 rxiqk_agc[2][4]; /*channel / path*/ + u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/ + u32 txgap_result[8]; /*txagpK result */ + u32 tmp_gntwl; + boolean is_btg; + boolean isbnd; + boolean is_reload; + boolean segment_iqk; + boolean is_hwtx; + boolean xym_read; + boolean trximr_enable; + u32 rx_xym[2][10]; + u32 tx_xym[2][10]; + u32 gs1_xym[2][6]; + u32 gs2_xym[2][6]; + u32 rxk1_xym[2][6]; +#endif +}; + +#endif /*#ifndef __HALRF_IQK_H__*/ diff --git a/hal/phydm/halrf/halrf_kfree.c b/hal/phydm/halrf/halrf_kfree.c new file mode 100644 index 0000000..2d0d7d1 --- /dev/null +++ b/hal/phydm/halrf/halrf_kfree.c @@ -0,0 +1,1013 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*============================================================*/ +/*include files*/ +/*============================================================*/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/* Add for KFree Feature Requested by RF David.*/ +/*This is a phydm API*/ + +void phydm_set_kfree_to_rf_8814a(void *dm_void, u8 e_rf_path, u8 data) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + boolean is_odd; + u32 tx_gain_bitmask = (BIT(17) | BIT(16) | BIT(15)); + + if ((data % 2) != 0) { /*odd->positive*/ + data = data - 1; + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 1); + is_odd = true; + } else { /*even->negative*/ + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), 0); + is_odd = false; + } + RF_DBG(dm, DBG_RF_MP, "phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", + is_odd); + switch (data) { + case 0: + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0); + cali_info->kfree_offset[e_rf_path] = 0; + break; + case 2: + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 0); + cali_info->kfree_offset[e_rf_path] = 0; + break; + case 4: + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1); + cali_info->kfree_offset[e_rf_path] = 1; + break; + case 6: + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 1); + cali_info->kfree_offset[e_rf_path] = 1; + break; + case 8: + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2); + cali_info->kfree_offset[e_rf_path] = 2; + break; + case 10: + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 2); + cali_info->kfree_offset[e_rf_path] = 2; + break; + case 12: + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3); + cali_info->kfree_offset[e_rf_path] = 3; + break; + case 14: + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 3); + cali_info->kfree_offset[e_rf_path] = 3; + break; + case 16: + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4); + cali_info->kfree_offset[e_rf_path] = 4; + break; + case 18: + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 4); + cali_info->kfree_offset[e_rf_path] = 4; + break; + case 20: + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(14), 0); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, tx_gain_bitmask, 5); + cali_info->kfree_offset[e_rf_path] = 5; + break; + + default: + break; + } + + if (!is_odd) { + /*that means Kfree offset is negative, we need to record it.*/ + cali_info->kfree_offset[e_rf_path] = + (-1) * cali_info->kfree_offset[e_rf_path]; + RF_DBG(dm, DBG_RF_MP, + "phy_ConfigKFree8814A(): kfree_offset = %d\n", + cali_info->kfree_offset[e_rf_path]); + } else { + RF_DBG(dm, DBG_RF_MP, + "phy_ConfigKFree8814A(): kfree_offset = %d\n", + cali_info->kfree_offset[e_rf_path]); + } +} + +void phydm_get_thermal_trim_offset_8821c(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; + + u8 pg_therm = 0xff; + + odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_21C, &pg_therm, false); + + if (pg_therm != 0xff) { + pg_therm = pg_therm & 0x1f; + if ((pg_therm & BIT(0)) == 0) + power_trim_info->thermal = (-1 * (pg_therm >> 1)); + else + power_trim_info->thermal = (pg_therm >> 1); + + power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; + } + + RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c thermal trim flag:0x%02x\n", + power_trim_info->flag); + + if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c thermal:%d\n", + power_trim_info->thermal); +} + +void phydm_get_power_trim_offset_8821c(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; + + u8 pg_power = 0xff, i; + + odm_efuse_one_byte_read(dm, PPG_2G_TXAB_21C, &pg_power, false); + + if (pg_power != 0xff) { + power_trim_info->bb_gain[0][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_21C, &pg_power, false); + power_trim_info->bb_gain[1][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_21C, &pg_power, false); + power_trim_info->bb_gain[2][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_21C, &pg_power, false); + power_trim_info->bb_gain[3][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_21C, &pg_power, false); + power_trim_info->bb_gain[4][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_21C, &pg_power, false); + power_trim_info->bb_gain[5][0] = pg_power; + power_trim_info->flag = + power_trim_info->flag | KFREE_FLAG_ON | + KFREE_FLAG_ON_2G | KFREE_FLAG_ON_5G; + } + + RF_DBG(dm, DBG_RF_MP, "[kfree] 8821c power trim flag:0x%02x\n", + power_trim_info->flag); + + if (power_trim_info->flag & KFREE_FLAG_ON) { + for (i = 0; i < KFREE_BAND_NUM; i++) + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8821c pwr_trim->bb_gain[%d][0]=0x%X\n", + i, power_trim_info->bb_gain[i][0]); + } +} + +void phydm_set_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, boolean wlg_btg, + u8 data) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 wlg, btg; + u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)); + u32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) | + BIT(16) | BIT(15) | BIT(14)); + + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1); + + if (wlg_btg) { + wlg = data & 0xf; + btg = (data & 0xf0) >> 4; + + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (wlg & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (wlg >> 1)); + + odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (btg & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (btg >> 1)); + } else { + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), data & BIT(0)); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, + ((data & 0x1f) >> 1)); + } + + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n", + odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask), + odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask)); +} + +void phydm_clear_kfree_to_rf_8821c(void *dm_void, u8 e_rf_path, u8 data) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)); + u32 s_gain_bmask = (BIT(19) | BIT(18) | BIT(17) | + BIT(16) | BIT(15) | BIT(14)); + + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 1); + + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, (data >> 1)); + + odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, RF_0x65, gain_bmask, (data >> 1)); + + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0); + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(5), 0); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(6), 0); + odm_set_rf_reg(dm, e_rf_path, RF_0x65, BIT(6), 0); + + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n", + odm_get_rf_reg(dm, e_rf_path, RF_0x55, s_gain_bmask), + odm_get_rf_reg(dm, e_rf_path, RF_0x65, s_gain_bmask)); +} + +void phydm_get_thermal_trim_offset_8822b(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; + + u8 pg_therm = 0xff; + + odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_22B, &pg_therm, false); + + if (pg_therm != 0xff) { + pg_therm = pg_therm & 0x1f; + if ((pg_therm & BIT(0)) == 0) + power_trim_info->thermal = (-1 * (pg_therm >> 1)); + else + power_trim_info->thermal = (pg_therm >> 1); + + power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; + } + + RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b thermal trim flag:0x%02x\n", + power_trim_info->flag); + + if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b thermal:%d\n", + power_trim_info->thermal); +} + +void phydm_get_power_trim_offset_8822b(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; + + u8 pg_power = 0xff, i, j; + + odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false); + + if (pg_power != 0xff) { + /*Path A*/ + odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false); + power_trim_info->bb_gain[0][0] = (pg_power & 0xf); + + /*Path B*/ + odm_efuse_one_byte_read(dm, PPG_2G_TXAB_22B, &pg_power, false); + power_trim_info->bb_gain[0][1] = ((pg_power & 0xf0) >> 4); + + power_trim_info->flag |= KFREE_FLAG_ON_2G; + power_trim_info->flag |= KFREE_FLAG_ON; + } + + odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false); + + if (pg_power != 0xff) { + /*Path A*/ + odm_efuse_one_byte_read(dm, PPG_5GL1_TXA_22B, &pg_power, false); + power_trim_info->bb_gain[1][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GL2_TXA_22B, &pg_power, false); + power_trim_info->bb_gain[2][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GM1_TXA_22B, &pg_power, false); + power_trim_info->bb_gain[3][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GM2_TXA_22B, &pg_power, false); + power_trim_info->bb_gain[4][0] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GH1_TXA_22B, &pg_power, false); + power_trim_info->bb_gain[5][0] = pg_power; + + /*Path B*/ + odm_efuse_one_byte_read(dm, PPG_5GL1_TXB_22B, &pg_power, false); + power_trim_info->bb_gain[1][1] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GL2_TXB_22B, &pg_power, false); + power_trim_info->bb_gain[2][1] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GM1_TXB_22B, &pg_power, false); + power_trim_info->bb_gain[3][1] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GM2_TXB_22B, &pg_power, false); + power_trim_info->bb_gain[4][1] = pg_power; + odm_efuse_one_byte_read(dm, PPG_5GH1_TXB_22B, &pg_power, false); + power_trim_info->bb_gain[5][1] = pg_power; + + power_trim_info->flag |= KFREE_FLAG_ON_5G; + power_trim_info->flag |= KFREE_FLAG_ON; + } + + RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b power trim flag:0x%02x\n", + power_trim_info->flag); + + if (!(power_trim_info->flag & KFREE_FLAG_ON)) + return; + + for (i = 0; i < KFREE_BAND_NUM; i++) { + for (j = 0; j < 2; j++) + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8822b PwrTrim->bb_gain[%d][%d]=0x%X\n", + i, j, power_trim_info->bb_gain[i][j]); + } +} + +void phydm_set_pa_bias_to_rf_8822b(void *dm_void, u8 e_rf_path, s8 tx_pa_bias) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 rf_reg_51 = 0, rf_reg_52 = 0, rf_reg_3f = 0; + u32 tx_pa_bias_bmask = (BIT(12) | BIT(11) | BIT(10) | BIT(9)); + + rf_reg_51 = odm_get_rf_reg(dm, e_rf_path, RF_0x51, RFREGOFFSETMASK); + rf_reg_52 = odm_get_rf_reg(dm, e_rf_path, RF_0x52, RFREGOFFSETMASK); + + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8822b 2g rf(0x51)=0x%X rf(0x52)=0x%X path=%d\n", + rf_reg_51, rf_reg_52, e_rf_path); + +#if 0 + /*rf3f => rf52[19:17] = rf3f[2:0] rf52[16:15] = rf3f[4:3] rf52[3:0] = rf3f[8:5]*/ + /*rf3f => rf51[6:3] = rf3f[12:9] rf52[13] = rf3f[13]*/ +#endif + rf_reg_3f = ((rf_reg_52 & 0xe0000) >> 17) | + (((rf_reg_52 & 0x18000) >> 15) << 3) | + ((rf_reg_52 & 0xf) << 5) | + (((rf_reg_51 & 0x78) >> 3) << 9) | + (((rf_reg_52 & 0x2000) >> 13) << 13); + + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8822b 2g original pa_bias=%d rf_reg_3f=0x%X path=%d\n", + tx_pa_bias, rf_reg_3f, e_rf_path); + + tx_pa_bias = (s8)((rf_reg_3f & tx_pa_bias_bmask) >> 9) + tx_pa_bias; + + if (tx_pa_bias < 0) + tx_pa_bias = 0; + else if (tx_pa_bias > 7) + tx_pa_bias = 7; + + rf_reg_3f = ((rf_reg_3f & 0xfe1ff) | (tx_pa_bias << 9)); + + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8822b 2g 0x%X 0x%X pa_bias=%d rfreg_3f=0x%X path=%d\n", + PPG_PABIAS_2GA_22B, PPG_PABIAS_2GB_22B, + tx_pa_bias, rf_reg_3f, e_rf_path); + + odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x1); + odm_set_rf_reg(dm, e_rf_path, RF_0x33, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f); + odm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(0), 0x1); + odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f); + odm_set_rf_reg(dm, e_rf_path, RF_0x33, BIT(1), 0x1); + odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f); + odm_set_rf_reg(dm, e_rf_path, RF_0x33, (BIT(1) | BIT(0)), 0x3); + odm_set_rf_reg(dm, e_rf_path, RF_0x3f, RFREGOFFSETMASK, rf_reg_3f); + odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(10), 0x0); + + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8822b 2g tx pa bias rf_0x3f(0x%X) path=%d\n", + odm_get_rf_reg(dm, e_rf_path, RF_0x3f, + (BIT(12) | BIT(11) | BIT(10) | BIT(9))), + e_rf_path); +} + +void phydm_get_pa_bias_offset_8822b(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; + + u8 pg_pa_bias = 0xff, e_rf_path = 0; + s8 tx_pa_bias[2] = {0}; + + odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B, &pg_pa_bias, false); + + if (pg_pa_bias != 0xff) { + /*paht a*/ + odm_efuse_one_byte_read(dm, PPG_PABIAS_2GA_22B, + &pg_pa_bias, false); + pg_pa_bias = pg_pa_bias & 0xf; + + if ((pg_pa_bias & BIT(0)) == 0) + tx_pa_bias[0] = (-1 * (pg_pa_bias >> 1)); + else + tx_pa_bias[0] = (pg_pa_bias >> 1); + + /*paht b*/ + odm_efuse_one_byte_read(dm, PPG_PABIAS_2GB_22B, + &pg_pa_bias, false); + pg_pa_bias = pg_pa_bias & 0xf; + + if ((pg_pa_bias & BIT(0)) == 0) + tx_pa_bias[1] = (-1 * (pg_pa_bias >> 1)); + else + tx_pa_bias[1] = (pg_pa_bias >> 1); + + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8822b 2g PathA_pa_bias:%d PathB_pa_bias:%d\n", + tx_pa_bias[0], tx_pa_bias[1]); + + for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++) + phydm_set_pa_bias_to_rf_8822b(dm, e_rf_path, + tx_pa_bias[e_rf_path]); + + power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON; + } else { + RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b 2g tx pa bias no pg\n"); + } +} + +void phydm_set_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)); + + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1); + + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, + ((data & 0x1f) >> 1)); + + RF_DBG(dm, DBG_RF_MP, "[kfree] 8822b 0x55[19:14]=0x%X path=%d\n", + odm_get_rf_reg(dm, e_rf_path, RF_0x55, + (BIT(19) | BIT(18) | BIT(17) | BIT(16) | + BIT(15) | BIT(14))), e_rf_path); +} + +void phydm_clear_kfree_to_rf_8822b(void *dm_void, u8 e_rf_path, u8 data) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)); + + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1); + + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, + ((data & 0x1f) >> 1)); + + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(0), 0); + odm_set_rf_reg(dm, e_rf_path, RF_0xde, BIT(4), 1); + odm_set_rf_reg(dm, e_rf_path, RF_0x65, MASKLWORD, 0x9000); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 0); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(7), 0); + + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8822b clear power trim 0x55[19:14]=0x%X path=%d\n", + odm_get_rf_reg(dm, e_rf_path, RF_0x55, + (BIT(19) | BIT(18) | BIT(17) | BIT(16) | + BIT(15) | BIT(14))), e_rf_path); +} + +void phydm_get_thermal_trim_offset_8710b(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; + + u8 pg_therm = 0xff; + + odm_efuse_one_byte_read(dm, 0x0EF, &pg_therm, false); + + if (pg_therm != 0xff) { + pg_therm = pg_therm & 0x1f; + if ((pg_therm & BIT(0)) == 0) + power_trim_info->thermal = (-1 * (pg_therm >> 1)); + else + power_trim_info->thermal = (pg_therm >> 1); + + power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; + } + + RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b thermal trim flag:0x%02x\n", + power_trim_info->flag); + + if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b thermal:%d\n", + power_trim_info->thermal); +} + +void phydm_get_power_trim_offset_8710b(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; + + u8 pg_power = 0xff; + + odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false); + + if (pg_power != 0xff) { + /*Path A*/ + odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false); + power_trim_info->bb_gain[0][0] = (pg_power & 0xf); + + power_trim_info->flag |= KFREE_FLAG_ON_2G; + power_trim_info->flag |= KFREE_FLAG_ON; + } + + RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b power trim flag:0x%02x\n", + power_trim_info->flag); + + if (power_trim_info->flag & KFREE_FLAG_ON) + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8710b power_trim_data->bb_gain[0][0]=0x%X\n", + power_trim_info->bb_gain[0][0]); +} + +void phydm_set_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15)); + + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, ((data & 0xf) >> 1)); + + RF_DBG(dm, DBG_RF_MP, "[kfree] 8710b 0x55[19:14]=0x%X path=%d\n", + odm_get_rf_reg(dm, e_rf_path, RF_0x55, + (BIT(19) | BIT(18) | BIT(17) | BIT(16) | + BIT(15) | BIT(14))), e_rf_path); +} + +void phydm_clear_kfree_to_rf_8710b(void *dm_void, u8 e_rf_path, u8 data) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 gain_bmask = (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)); + + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, gain_bmask, + ((data & 0x1f) >> 1)); + + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8710b clear power trim 0x55[19:14]=0x%X path=%d\n", + odm_get_rf_reg(dm, e_rf_path, RF_0x55, + (BIT(19) | BIT(18) | BIT(17) | BIT(16) | + BIT(15) | BIT(14))), e_rf_path); +} + +void phydm_get_thermal_trim_offset_8192f(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; + + u8 pg_therm = 0xff; + + odm_efuse_one_byte_read(dm, 0x1EF, &pg_therm, false); + + if (pg_therm != 0xff) { + pg_therm = pg_therm & 0x1f; + if ((pg_therm & BIT(0)) == 0) + power_trim_info->thermal = (-1 * (pg_therm >> 1)); + else + power_trim_info->thermal = (pg_therm >> 1); + + power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; + } + + RF_DBG(dm, DBG_RF_MP, "[kfree] 8192f thermal trim flag:0x%02x\n", + power_trim_info->flag); + + if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + RF_DBG(dm, DBG_RF_MP, "[kfree] 8192f thermal:%d\n", + power_trim_info->thermal); +} + +void phydm_get_power_trim_offset_8192f(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; + + u8 pg_power1 = 0xff, pg_power2 = 0xff, pg_power3 = 0xff, i, j; + + odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false); /*CH4-9*/ + + if (pg_power1 != 0xff) { + /*Path A*/ + odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false); + power_trim_info->bb_gain[1][0] = (pg_power1 & 0xf); + /*Path B*/ + odm_efuse_one_byte_read(dm, 0x1EE, &pg_power1, false); + power_trim_info->bb_gain[1][1] = ((pg_power1 & 0xf0) >> 4); + + power_trim_info->flag |= KFREE_FLAG_ON_2G; + power_trim_info->flag |= KFREE_FLAG_ON; + } + + odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false); /*CH1-3*/ + + if (pg_power2 != 0xff) { + /*Path A*/ + odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false); + power_trim_info->bb_gain[0][0] = (pg_power2 & 0xf); + /*Path B*/ + odm_efuse_one_byte_read(dm, 0x1EC, &pg_power2, false); + power_trim_info->bb_gain[0][1] = ((pg_power2 & 0xf0) >> 4); + + power_trim_info->flag |= KFREE_FLAG_ON_2G; + power_trim_info->flag |= KFREE_FLAG_ON; + } else { + power_trim_info->bb_gain[0][0] = (pg_power1 & 0xf); + power_trim_info->bb_gain[0][1] = ((pg_power1 & 0xf0) >> 4); + } + + odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false); /*CH10-14*/ + + if (pg_power3 != 0xff) { + /*Path A*/ + odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false); + power_trim_info->bb_gain[2][0] = (pg_power3 & 0xf); + /*Path B*/ + odm_efuse_one_byte_read(dm, 0x1EA, &pg_power3, false); + power_trim_info->bb_gain[2][1] = ((pg_power3 & 0xf0) >> 4); + + power_trim_info->flag |= KFREE_FLAG_ON_2G; + power_trim_info->flag |= KFREE_FLAG_ON; + } else { + power_trim_info->bb_gain[2][0] = (pg_power1 & 0xf); + power_trim_info->bb_gain[2][1] = ((pg_power1 & 0xf0) >> 4); + } + + RF_DBG(dm, DBG_RF_MP, "[kfree] 8192F power trim flag:0x%02x\n", + power_trim_info->flag); + + if (!(power_trim_info->flag & KFREE_FLAG_ON)) + return; + + for (i = 0; i < KFREE_CH_NUM; i++) { + for (j = 0; j < 2; j++) + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8192F PwrTrim->bb_gain[%d][%d]=0x%X\n", + i, j, power_trim_info->bb_gain[i][j]); + } +} + +void phydm_set_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 channel_idx, + u8 data) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*power_trim based on 55[19:14]*/ + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(5), 1); + /*enable 55[14] for 0.5db step*/ + odm_set_rf_reg(dm, e_rf_path, RF_0xf5, BIT(18), 1); + /*enter power_trim debug mode*/ + odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 1); + /*write enable*/ + odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 1); + + if (e_rf_path == 0) { + if (channel_idx == 0) { + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + + } else if (channel_idx == 1) { + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + } else if (channel_idx == 2) { + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + } + } else if (e_rf_path == 1) { + if (channel_idx == 0) { + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 0); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 1); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + } else if (channel_idx == 1) { + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 2); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 3); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + } else if (channel_idx == 2) { + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 4); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + + odm_set_rf_reg(dm, e_rf_path, RF_0x33, 0x70000, 5); + odm_set_rf_reg(dm, e_rf_path, 0x33, 0x3F, data); + } + } + + /*leave power_trim debug mode*/ + odm_set_rf_reg(dm, e_rf_path, RF_0xdf, BIT(7), 0); + /*write disable*/ + odm_set_rf_reg(dm, e_rf_path, RF_0xef, BIT(7), 0); + + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8192F 0x55[19:14]=0x%X path=%d channel=%d\n", + odm_get_rf_reg(dm, e_rf_path, RF_0x55, + (BIT(19) | BIT(18) | BIT(17) | BIT(16) | + BIT(15) | BIT(14))), e_rf_path, channel_idx); +} + +#if 0 +/* +void phydm_clear_kfree_to_rf_8192f(void *dm_void, u8 e_rf_path, u8 data) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + odm_set_rf_reg(dm, e_rf_path, RF_0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(dm, e_rf_path, RF_0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); + + RF_DBG(dm, DBG_RF_MP, + "[kfree] 8192F clear power trim 0x55[19:14]=0x%X path=%d\n", + odm_get_rf_reg(dm, e_rf_path, RF_0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), + e_rf_path + ); +} +*/ +#endif + +void phydm_set_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_RTL8814A) + phydm_set_kfree_to_rf_8814a(dm, e_rf_path, data); + + if ((dm->support_ic_type & ODM_RTL8821C) && + (*dm->band_type == ODM_BAND_2_4G)) + phydm_set_kfree_to_rf_8821c(dm, e_rf_path, true, data); + else if (dm->support_ic_type & ODM_RTL8821C) + phydm_set_kfree_to_rf_8821c(dm, e_rf_path, false, data); + + if (dm->support_ic_type & ODM_RTL8822B) + phydm_set_kfree_to_rf_8822b(dm, e_rf_path, data); + + if (dm->support_ic_type & ODM_RTL8710B) + phydm_set_kfree_to_rf_8710b(dm, e_rf_path, data); +} + +void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_RTL8822B) + phydm_clear_kfree_to_rf_8822b(dm, e_rf_path, 1); + + if (dm->support_ic_type & ODM_RTL8821C) + phydm_clear_kfree_to_rf_8821c(dm, e_rf_path, 1); +} + +void phydm_get_thermal_trim_offset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal; + u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2]; + + if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS) + RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n"); +#endif + + if (dm->support_ic_type & ODM_RTL8821C) + phydm_get_thermal_trim_offset_8821c(dm_void); + else if (dm->support_ic_type & ODM_RTL8822B) + phydm_get_thermal_trim_offset_8822b(dm_void); + else if (dm->support_ic_type & ODM_RTL8710B) + phydm_get_thermal_trim_offset_8710b(dm_void); + else if (dm->support_ic_type & ODM_RTL8192F) + phydm_get_thermal_trim_offset_8192f(dm_void); +} + +void phydm_get_power_trim_offset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if 0 //(DM_ODM_SUPPORT_TYPE & ODM_WIN) // 2017 MH DM Should use the same code.s + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal; + u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2]; + + if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS) + RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n"); +#endif + + if (dm->support_ic_type & ODM_RTL8821C) + phydm_get_power_trim_offset_8821c(dm_void); + else if (dm->support_ic_type & ODM_RTL8822B) + phydm_get_power_trim_offset_8822b(dm_void); + else if (dm->support_ic_type & ODM_RTL8710B) + phydm_get_power_trim_offset_8710b(dm_void); + else if (dm->support_ic_type & ODM_RTL8192F) + phydm_get_power_trim_offset_8192f(dm_void); +} + +void phydm_get_pa_bias_offset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal; + u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2]; + + if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS) + RF_DBG(dm, DBG_RF_MP, "[kfree] dump efuse fail !!!\n"); +#endif + + if (dm->support_ic_type & ODM_RTL8822B) + phydm_get_pa_bias_offset_8822b(dm_void); +} + +s8 phydm_get_thermal_offset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *power_trim_info = &dm->power_trim_data; + + if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + return power_trim_info->thermal; + else + return 0; +} + +void phydm_do_kfree(void *dm_void, u8 channel_to_sw) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_power_trim_data *pwrtrim = &dm->power_trim_data; + u8 channel_idx = 0, rfpath = 0, max_path = 0, kfree_band_num = 0; + u8 i, j; + s8 bb_gain; + + if (dm->support_ic_type & ODM_RTL8814A) + max_path = 4; /*0~3*/ + else if (dm->support_ic_type & + (ODM_RTL8812 | ODM_RTL8822B | ODM_RTL8192F)) { + max_path = 2; /*0~1*/ + kfree_band_num = KFREE_BAND_NUM; + } else if (dm->support_ic_type & ODM_RTL8821C) { + max_path = 1; + kfree_band_num = KFREE_BAND_NUM; + } else if (dm->support_ic_type & ODM_RTL8710B) { + max_path = 1; + kfree_band_num = 1; + } + + if (dm->support_ic_type & + (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8821C | + ODM_RTL8814A | ODM_RTL8710B)) { + for (i = 0; i < kfree_band_num; i++) { + for (j = 0; j < max_path; j++) + RF_DBG(dm, DBG_RF_MP, + "[kfree] PwrTrim->gain[%d][%d]=0x%X\n", + i, j, pwrtrim->bb_gain[i][j]); + } + } + if (*dm->band_type == ODM_BAND_2_4G && + pwrtrim->flag & KFREE_FLAG_ON_2G) { + if (!(dm->support_ic_type & ODM_RTL8192F)) { + if (channel_to_sw >= 1 && channel_to_sw <= 14) + channel_idx = PHYDM_2G; + for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) { + RF_DBG(dm, DBG_RF_MP, + "[kfree] %s:chnl=%d PATH=%d gain:0x%X\n", + __func__, channel_to_sw, rfpath, + pwrtrim->bb_gain[channel_idx][rfpath]); + bb_gain = pwrtrim->bb_gain[channel_idx][rfpath]; + phydm_set_kfree_to_rf(dm, rfpath, bb_gain); + } + } else if (dm->support_ic_type & ODM_RTL8192F) { + if (channel_to_sw >= 1 && channel_to_sw <= 3) + channel_idx = 0; + if (channel_to_sw >= 4 && channel_to_sw <= 9) + channel_idx = 1; + if (channel_to_sw >= 10 && channel_to_sw <= 14) + channel_idx = 2; + for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) { + RF_DBG(dm, DBG_RF_MP, + "[kfree] %s:chnl=%d PATH=%d gain:0x%X\n", + __func__, channel_to_sw, rfpath, + pwrtrim->bb_gain[channel_idx][rfpath]); + bb_gain = pwrtrim->bb_gain[channel_idx][rfpath]; + phydm_set_kfree_to_rf_8192f(dm, rfpath, + channel_idx, + bb_gain); + } + } + } else if (*dm->band_type == ODM_BAND_5G && + pwrtrim->flag & KFREE_FLAG_ON_5G) { + if (channel_to_sw >= 36 && channel_to_sw <= 48) + channel_idx = PHYDM_5GLB1; + if (channel_to_sw >= 52 && channel_to_sw <= 64) + channel_idx = PHYDM_5GLB2; + if (channel_to_sw >= 100 && channel_to_sw <= 120) + channel_idx = PHYDM_5GMB1; + if (channel_to_sw >= 122 && channel_to_sw <= 144) + channel_idx = PHYDM_5GMB2; + if (channel_to_sw >= 149 && channel_to_sw <= 177) + channel_idx = PHYDM_5GHB; + + for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) { + RF_DBG(dm, DBG_RF_MP, + "[kfree] %s: channel=%d PATH=%d bb_gain:0x%X\n", + __func__, channel_to_sw, rfpath, + pwrtrim->bb_gain[channel_idx][rfpath]); + bb_gain = pwrtrim->bb_gain[channel_idx][rfpath]; + phydm_set_kfree_to_rf(dm, rfpath, bb_gain); + } + } else { + RF_DBG(dm, DBG_RF_MP, "[kfree] Set default Register\n"); + if (!(dm->support_ic_type & ODM_RTL8192F)) { + for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) { + bb_gain = pwrtrim->bb_gain[channel_idx][rfpath]; + phydm_clear_kfree_to_rf(dm, rfpath, bb_gain); + } + } +#if 0 + /*else if(dm->support_ic_type & ODM_RTL8192F){ + if (channel_to_sw >= 1 && channel_to_sw <= 3) + channel_idx = 0; + if (channel_to_sw >= 4 && channel_to_sw <= 9) + channel_idx = 1; + if (channel_to_sw >= 9 && channel_to_sw <= 14) + channel_idx = 2; + for (rfpath = RF_PATH_A; rfpath < max_path; rfpath++) + phydm_clear_kfree_to_rf_8192f(dm, rfpath, pwrtrim->bb_gain[channel_idx][rfpath]); + }*/ +#endif + } +} + +void phydm_config_kfree(void *dm_void, u8 channel_to_sw) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + struct odm_power_trim_data *pwrtrim = &dm->power_trim_data; + + RF_DBG(dm, DBG_RF_MP, "===>[kfree] phy_ConfigKFree()\n"); + + if (cali_info->reg_rf_kfree_enable == 2) { + RF_DBG(dm, DBG_RF_MP, + "[kfree] %s: reg_rf_kfree_enable == 2, Disable\n", + __func__); + return; + } else if (cali_info->reg_rf_kfree_enable == 1 || + cali_info->reg_rf_kfree_enable == 0) { + RF_DBG(dm, DBG_RF_MP, + "[kfree] %s: reg_rf_kfree_enable == true\n", __func__); + /*Make sure the targetval is defined*/ + if (!(pwrtrim->flag & KFREE_FLAG_ON)) { + RF_DBG(dm, DBG_RF_MP, + "[kfree] %s: efuse is 0xff, KFree not work\n", + __func__); + return; + } +#if 0 + /*if kfree_table[0] == 0xff, means no Kfree*/ +#endif + phydm_do_kfree(dm, channel_to_sw); + } + RF_DBG(dm, DBG_RF_MP, "<===[kfree] phy_ConfigKFree()\n"); +} diff --git a/hal/phydm/halrf/halrf_kfree.h b/hal/phydm/halrf/halrf_kfree.h new file mode 100644 index 0000000..8580bdb --- /dev/null +++ b/hal/phydm/halrf/halrf_kfree.h @@ -0,0 +1,111 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_KFREE_H__ +#define __HALRF_KFREE_H__ + +#define KFREE_VERSION "1.0" + +#define KFREE_BAND_NUM 6 +#define KFREE_CH_NUM 3 + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP)) + +#define BB_GAIN_NUM 6 + +#endif + +#define KFREE_FLAG_ON BIT(0) +#define KFREE_FLAG_THERMAL_K_ON BIT(1) + +#define KFREE_FLAG_ON_2G BIT(2) +#define KFREE_FLAG_ON_5G BIT(3) + +#define PA_BIAS_FLAG_ON BIT(4) + +#define PPG_THERMAL_OFFSET_21C 0x1EF +#define PPG_2G_TXAB_21C 0x1EE +#define PPG_5GL1_TXA_21C 0x1EC +#define PPG_5GL2_TXA_21C 0x1E8 +#define PPG_5GM1_TXA_21C 0x1E4 +#define PPG_5GM2_TXA_21C 0x1E0 +#define PPG_5GH1_TXA_21C 0x1DC + +#define PPG_THERMAL_OFFSET_22B 0x3EF +#define PPG_2G_TXAB_22B 0x3EE +#define PPG_2G_TXCD_22B 0x3ED +#define PPG_5GL1_TXA_22B 0x3EC +#define PPG_5GL1_TXB_22B 0x3EB +#define PPG_5GL1_TXC_22B 0x3EA +#define PPG_5GL1_TXD_22B 0x3E9 +#define PPG_5GL2_TXA_22B 0x3E8 +#define PPG_5GL2_TXB_22B 0x3E7 +#define PPG_5GL2_TXC_22B 0x3E6 +#define PPG_5GL2_TXD_22B 0x3E5 +#define PPG_5GM1_TXA_22B 0x3E4 +#define PPG_5GM1_TXB_22B 0x3E3 +#define PPG_5GM1_TXC_22B 0x3E2 +#define PPG_5GM1_TXD_22B 0x3E1 +#define PPG_5GM2_TXA_22B 0x3E0 +#define PPG_5GM2_TXB_22B 0x3DF +#define PPG_5GM2_TXC_22B 0x3DE +#define PPG_5GM2_TXD_22B 0x3DD +#define PPG_5GH1_TXA_22B 0x3DC +#define PPG_5GH1_TXB_22B 0x3DB +#define PPG_5GH1_TXC_22B 0x3DA +#define PPG_5GH1_TXD_22B 0x3D9 + +#define PPG_PABIAS_2GA_22B 0x3D5 +#define PPG_PABIAS_2GB_22B 0x3D6 + +struct odm_power_trim_data { + u8 flag; + u8 pa_bias_flag; + s8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH]; + s8 thermal; +}; + +enum phydm_kfree_channeltosw { + PHYDM_2G = 0, + PHYDM_5GLB1 = 1, + PHYDM_5GLB2 = 2, + PHYDM_5GMB1 = 3, + PHYDM_5GMB2 = 4, + PHYDM_5GHB = 5, +}; + +void phydm_get_thermal_trim_offset(void *dm_void); + +void phydm_get_power_trim_offset(void *dm_void); + +void phydm_get_pa_bias_offset(void *dm_void); + +s8 phydm_get_thermal_offset(void *dm_void); + +void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data); + +void phydm_config_kfree(void *dm_void, u8 channel_to_sw); + +#endif /*#ifndef __HALRF_KFREE_H__*/ diff --git a/hal/phydm/halrf/halrf_powertracking.c b/hal/phydm/halrf/halrf_powertracking.c new file mode 100644 index 0000000..9f86929 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking.c @@ -0,0 +1,152 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ + */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +boolean +odm_check_power_status(void *dm_void) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct dm_struct *dm = (struct dm_struct *)dm_void; + PADAPTER *adapter = dm->adapter; + + RT_RF_POWER_STATE rt_state; + MGNT_INFO *mgnt_info = &((PADAPTER)adapter)->MgntInfo; + + /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */ + if (mgnt_info->init_adpt_in_progress == true) { + RF_DBG(dm, DBG_RF_INIT, + "check_pow_status Return true, due to initadapter\n"); + return true; + } + + /* + * 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + */ + ((PADAPTER)adapter)->HalFunc.GetHwRegHandler((PADAPTER)adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state)); + if (((PADAPTER)adapter)->bDriverStopped || ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) { + RF_DBG(dm, DBG_RF_INIT, + "check_pow_status Return false, due to %d/%d/%d\n", + ((PADAPTER)adapter)->bDriverStopped, + ((PADAPTER)adapter)->bDriverIsGoingToPnpSetPowerSleep, + rt_state); + return false; + } +#endif + return true; +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +void halrf_update_pwr_track(void *dm_void, u8 rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u8 path_idx = 0; +#endif + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate); + + dm->tx_rate = rate; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +#if USE_WORKITEM + odm_schedule_work_item(&dm->ra_rpt_workitem); +#else + if (dm->support_ic_type == ODM_RTL8821) { +#if (RTL8821A_SUPPORT == 1) + odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0); +#endif + } else if (dm->support_ic_type == ODM_RTL8812) { + for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) { +#if (RTL8812A_SUPPORT == 1) + odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, path_idx, 0); +#endif + } + } else if (dm->support_ic_type == ODM_RTL8723B) { +#if (RTL8723B_SUPPORT == 1) + odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0); +#endif + } else if (dm->support_ic_type == ODM_RTL8192E) { + for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) { +#if (RTL8192E_SUPPORT == 1) + odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, path_idx, 0); +#endif + } + } else if (dm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0); +#endif + } +#endif +#else + odm_schedule_work_item(&dm->ra_rpt_workitem); +#endif +#endif +} + +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void halrf_update_init_rate_work_item_callback( + void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + u8 p = 0; + + if (dm->support_ic_type == ODM_RTL8821) { +#if (RTL8821A_SUPPORT == 1) + odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0); +#endif + } else if (dm->support_ic_type == ODM_RTL8812) { +#if (RTL8812A_SUPPORT == 1) + /*Don't know how to include &c*/ + for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) + odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0); +#endif + } else if (dm->support_ic_type == ODM_RTL8723B) { +#if (RTL8723B_SUPPORT == 1) + odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0); +#endif + } else if (dm->support_ic_type == ODM_RTL8192E) { +#if (RTL8192E_SUPPORT == 1) + /*Don't know how to include &c*/ + for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) + odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0); +#endif + } else if (dm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0); +#endif + } +} +#endif diff --git a/hal/phydm/halrf/halrf_powertracking.h b/hal/phydm/halrf/halrf_powertracking.h new file mode 100644 index 0000000..c456288 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_POWER_TRACKING_H__ +#define __HALRF_POWER_TRACKING_H__ + +boolean +odm_check_power_status(void *dm_void); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +void halrf_update_pwr_track(void *dm_void, u8 rate); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void halrf_update_init_rate_work_item_callback( + void *context); +#endif + +#endif /*#ifndef __HALRF_POWERTRACKING_H__*/ diff --git a/hal/phydm/halrf/halrf_powertracking_ap.c b/hal/phydm/halrf/halrf_powertracking_ap.c new file mode 100644 index 0000000..e9a2e64 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_ap.c @@ -0,0 +1,1219 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if !defined(_OUTSRC_COEXIST) +/* ************************************************************ + * Global var + * ************************************************************ */ + + +u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D] = { + 0x0b40002d, /* 0, -15.0dB */ + 0x0c000030, /* 1, -14.5dB */ + 0x0cc00033, /* 2, -14.0dB */ + 0x0d800036, /* 3, -13.5dB */ + 0x0e400039, /* 4, -13.0dB */ + 0x0f00003c, /* 5, -12.5dB */ + 0x10000040, /* 6, -12.0dB */ + 0x11000044, /* 7, -11.5dB */ + 0x12000048, /* 8, -11.0dB */ + 0x1300004c, /* 9, -10.5dB */ + 0x14400051, /* 10, -10.0dB */ + 0x15800056, /* 11, -9.5dB */ + 0x16c0005b, /* 12, -9.0dB */ + 0x18000060, /* 13, -8.5dB */ + 0x19800066, /* 14, -8.0dB */ + 0x1b00006c, /* 15, -7.5dB */ + 0x1c800072, /* 16, -7.0dB */ + 0x1e400079, /* 17, -6.5dB */ + 0x20000080, /* 18, -6.0dB */ + 0x22000088, /* 19, -5.5dB */ + 0x24000090, /* 20, -5.0dB */ + 0x26000098, /* 21, -4.5dB */ + 0x288000a2, /* 22, -4.0dB */ + 0x2ac000ab, /* 23, -3.5dB */ + 0x2d4000b5, /* 24, -3.0dB */ + 0x300000c0, /* 25, -2.5dB */ + 0x32c000cb, /* 26, -2.0dB */ + 0x35c000d7, /* 27, -1.5dB */ + 0x390000e4, /* 28, -1.0dB */ + 0x3c8000f2, /* 29, -0.5dB */ + 0x40000100, /* 30, +0dB */ + 0x43c0010f, /* 31, +0.5dB */ + 0x47c0011f, /* 32, +1.0dB */ + 0x4c000130, /* 33, +1.5dB */ + 0x50800142, /* 34, +2.0dB */ + 0x55400155, /* 35, +2.5dB */ + 0x5a400169, /* 36, +3.0dB */ + 0x5fc0017f, /* 37, +3.5dB */ + 0x65400195, /* 38, +4.0dB */ + 0x6b8001ae, /* 39, +4.5dB */ + 0x71c001c7, /* 40, +5.0dB */ + 0x788001e2, /* 41, +5.5dB */ + 0x7f8001fe /* 42, +6.0dB */ +}; + +u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */ + {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */ +}; + + +u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ + {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ +}; + +u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D] = { + 0x0b40002d, /* 0, -15.0dB */ + 0x0c000030, /* 1, -14.5dB */ + 0x0cc00033, /* 2, -14.0dB */ + 0x0d800036, /* 3, -13.5dB */ + 0x0e400039, /* 4, -13.0dB */ + 0x0f00003c, /* 5, -12.5dB */ + 0x10000040, /* 6, -12.0dB */ + 0x11000044, /* 7, -11.5dB */ + 0x12000048, /* 8, -11.0dB */ + 0x1300004c, /* 9, -10.5dB */ + 0x14400051, /* 10, -10.0dB */ + 0x15800056, /* 11, -9.5dB */ + 0x16c0005b, /* 12, -9.0dB */ + 0x18000060, /* 13, -8.5dB */ + 0x19800066, /* 14, -8.0dB */ + 0x1b00006c, /* 15, -7.5dB */ + 0x1c800072, /* 16, -7.0dB */ + 0x1e400079, /* 17, -6.5dB */ + 0x20000080, /* 18, -6.0dB */ + 0x22000088, /* 19, -5.5dB */ + 0x24000090, /* 20, -5.0dB */ + 0x26000098, /* 21, -4.5dB */ + 0x288000a2, /* 22, -4.0dB */ + 0x2ac000ab, /* 23, -3.5dB */ + 0x2d4000b5, /* 24, -3.0dB */ + 0x300000c0, /* 25, -2.5dB */ + 0x32c000cb, /* 26, -2.0dB */ + 0x35c000d7, /* 27, -1.5dB */ + 0x390000e4, /* 28, -1.0dB */ + 0x3c8000f2, /* 29, -0.5dB */ + 0x40000100, /* 30, +0dB */ + 0x43c0010f, /* 31, +0.5dB */ + 0x47c0011f, /* 32, +1.0dB */ + 0x4c000130, /* 33, +1.5dB */ + 0x50800142, /* 34, +2.0dB */ + 0x55400155, /* 35, +2.5dB */ + 0x5a400169, /* 36, +3.0dB */ + 0x5fc0017f, /* 37, +3.5dB */ + 0x65400195, /* 38, +4.0dB */ + 0x6b8001ae, /* 39, +4.5dB */ + 0x71c001c7, /* 40, +5.0dB */ + 0x788001e2, /* 41, +5.5dB */ + 0x7f8001fe /* 42, +6.0dB */ +}; + + +u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */ + {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */ +}; + + +u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ + {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ +}; + +u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */ + {0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */ + {0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */ + {0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */ + {0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */ + {0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */ + {0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */ + {0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */ + {0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */ + {0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */ + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */ +}; + + +u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = { + {0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */ + {0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */ + {0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */ + {0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */ + {0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */ + {0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */ + {0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */ + {0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */ + {0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */ + {0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */ + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */ +}; + + +u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + +/* Winnita ADD 20171113 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/ +u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, /*19*/ + 0x287, /*20*/ + 0x2AE, /*21*/ + 0x2D6, /*22*/ + 0x301, /*23*/ + 0x32F, /*24*/ + 0x35F, /*25*/ + 0x392, /*26*/ + 0x3C9, /*27*/ + 0x402, /*28*/ + 0x43F, /*29*/ + 0x47F, /*30*/ + 0x4C3, /*31*/ + 0x50C, /*32*/ + 0x558, /*33*/ + 0x5A9, /*34*/ + 0x5FF, /*35*/ + 0x65A, /*36*/ + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + + +#if 0 +u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = { + /* Index0 6 dB */ 0x7fc001ff, + /* Index1 5.7dB */ 0x7b4001ed, + /* Index2 5.4dB */ 0x774001dd, + /* Index3 5.1dB */ 0x734001cd, + /* Index4 4.8dB */ 0x6f4001bd, + /* Index5 4.5dB */ 0x6b8001ae, + /* Index6 4.2dB */ 0x67c0019f, + /* Index7 3.9dB */ 0x64400191, + /* Index8 3.6dB */ 0x60c00183, + /* Index9 3.3dB */ 0x5d800176, + /* Index10 3 dB */ 0x5a80016a, + /* Index11 2.7dB */ 0x5740015d, + /* Index12 2.4dB */ 0x54400151, + /* Index13 2.1dB */ 0x51800146, + /* Index14 1.8dB */ 0x4ec0013b, + /* Index15 1.5dB */ 0x4c000130, + /* Index16 1.2dB */ 0x49800126, + /* Index17 0.9dB */ 0x4700011c, + /* Index18 0.6dB */ 0x44800112, + /* Index19 0.3dB */ 0x42000108, + /* Index20 0 dB */ 0x40000100, /* 20 This is OFDM base index */ + /* Index21 -0.3dB */ 0x3dc000f7, + /* Index22 -0.6dB */ 0x3bc000ef, + /* Index23 -0.9dB */ 0x39c000e7, + /* Index24 -1.2dB */ 0x37c000df, + /* Index25 -1.5dB */ 0x35c000d7, + /* Index26 -1.8dB */ 0x340000d0, + /* Index27 -2.1dB */ 0x324000c9, + /* Index28 -2.4dB */ 0x308000c2, + /* Index29 -2.7dB */ 0x2f0000bc, + /* Index30 -3 dB */ 0x2d4000b5, + /* Index31 -3.3dB */ 0x2bc000af, + /* Index32 -3.6dB */ 0x2a4000a9, + /* Index33 -3.9dB */ 0x28c000a3, + /* Index34 -4.2dB */ 0x2780009e, + /* Index35 -4.5dB */ 0x26000098, + /* Index36 -4.8dB */ 0x24c00093, + /* Index37 -5.1dB */ 0x2380008e, + /* Index38 -5.4dB */ 0x22400089, + /* Index39 -5.7dB */ 0x21400085, + /* Index40 -6 dB */ 0x20000080, + /* Index41 -6.3dB */ 0x1f00007c, + /* Index42 -6.6dB */ 0x1e000078, + /* Index43 -6.9dB */ 0x1d000074, + /* Index44 -7.2dB */ 0x1c000070, + /* Index45 -7.5dB */ 0x1b00006c, + /* Index46 -7.8dB */ 0x1a000068, + /* Index47 -8.1dB */ 0x19400065, + /* Index48 -8.4dB */ 0x18400061, + /* Index49 -8.7dB */ 0x1780005e, + /* Index50 -9 dB */ 0x16c0005b, + /* Index51 -9.3dB */ 0x16000058, + /* Index52 -9.6dB */ 0x15400055, + /* Index53 -9.9dB */ 0x14800052 +}; +u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04}, + /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04}, + /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04}, + /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04}, + /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03}, + /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03}, + /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03}, + /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03}, + /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03}, + /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03}, + /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03}, + /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03}, + /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03}, + /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03}, + /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02}, + /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02}, + /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02}, + /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02}, + /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02}, + /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02}, + /* Index20 -6.0dB */ {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */ + /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02}, + /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02}, + /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02}, + /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02}, + /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02}, + /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02}, + /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02}, + /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02}, + /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01}, + /* Index30 -9.0dB */ {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */ + /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01}, + /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01}, + /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01}, + /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01}, + /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01}, + /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01}, + /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01}, + /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01}, + /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01}, + /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01}, + /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01}, + /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, + /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01}, + /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01}, + /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, + /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, + /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} +}; +u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00}, + /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00}, + /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00}, + /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00}, + /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00}, + /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00}, + /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00}, + /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00}, + /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00}, + /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00}, + /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00}, + /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00}, + /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00}, + /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00}, + /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00}, + /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00}, + /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00}, + /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00}, + /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00}, + /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00}, + /* Index20 -6 dB */ {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00}, + /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00}, + /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00}, + /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00}, + /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00}, + /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00}, + /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00}, + /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00}, + /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00}, + /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00}, + /* Index30 -9 dB */ {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00}, + /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00}, + /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00}, + /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00}, + /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00}, + /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00}, + /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00} +}; +#endif +#endif + + +u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3 + , 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9 + }; +u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4 + , 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 + }; + + +#ifdef CONFIG_WLAN_HAL_8192EE +u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = { + /* Index0 6 dB */ 0x7fc001ff, + /* Index1 5.7dB */ 0x7b4001ed, + /* Index2 5.4dB */ 0x774001dd, + /* Index3 5.1dB */ 0x734001cd, + /* Index4 4.8dB */ 0x6f4001bd, + /* Index5 4.5dB */ 0x6b8001ae, + /* Index6 4.2dB */ 0x67c0019f, + /* Index7 3.9dB */ 0x64400191, + /* Index8 3.6dB */ 0x60c00183, + /* Index9 3.3dB */ 0x5d800176, + /* Index10 3 dB */ 0x5a80016a, + /* Index11 2.7dB */ 0x5740015d, + /* Index12 2.4dB */ 0x54400151, + /* Index13 2.1dB */ 0x51800146, + /* Index14 1.8dB */ 0x4ec0013b, + /* Index15 1.5dB */ 0x4c000130, + /* Index16 1.2dB */ 0x49800126, + /* Index17 0.9dB */ 0x4700011c, + /* Index18 0.6dB */ 0x44800112, + /* Index19 0.3dB */ 0x42000108, + /* Index20 0 dB */ 0x40000100, /* 20 This is OFDM base index */ + /* Index21 -0.3dB */ 0x3dc000f7, + /* Index22 -0.6dB */ 0x3bc000ef, + /* Index23 -0.9dB */ 0x39c000e7, + /* Index24 -1.2dB */ 0x37c000df, + /* Index25 -1.5dB */ 0x35c000d7, + /* Index26 -1.8dB */ 0x340000d0, + /* Index27 -2.1dB */ 0x324000c9, + /* Index28 -2.4dB */ 0x308000c2, + /* Index29 -2.7dB */ 0x2f0000bc, + /* Index30 -3 dB */ 0x2d4000b5, + /* Index31 -3.3dB */ 0x2bc000af, + /* Index32 -3.6dB */ 0x2a4000a9, + /* Index33 -3.9dB */ 0x28c000a3, + /* Index34 -4.2dB */ 0x2780009e, + /* Index35 -4.5dB */ 0x26000098, + /* Index36 -4.8dB */ 0x24c00093, + /* Index37 -5.1dB */ 0x2380008e, + /* Index38 -5.4dB */ 0x22400089, + /* Index39 -5.7dB */ 0x21400085, + /* Index40 -6 dB */ 0x20000080, + /* Index41 -6.3dB */ 0x1f00007c, + /* Index42 -6.6dB */ 0x1e000078, + /* Index43 -6.9dB */ 0x1d000074, + /* Index44 -7.2dB */ 0x1c000070, + /* Index45 -7.5dB */ 0x1b00006c, + /* Index46 -7.8dB */ 0x1a000068, + /* Index47 -8.1dB */ 0x19400065, + /* Index48 -8.4dB */ 0x18400061, + /* Index49 -8.7dB */ 0x1780005e, + /* Index50 -9 dB */ 0x16c0005b, + /* Index51 -9.3dB */ 0x16000058, + /* Index52 -9.6dB */ 0x15400055, + /* Index53 -9.9dB */ 0x14800052 +}; +u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04}, + /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04}, + /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04}, + /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04}, + /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03}, + /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03}, + /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03}, + /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03}, + /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03}, + /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03}, + /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03}, + /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03}, + /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03}, + /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03}, + /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02}, + /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02}, + /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02}, + /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02}, + /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02}, + /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02}, + /* Index20 -6.0dB */ {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */ + /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02}, + /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02}, + /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02}, + /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02}, + /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02}, + /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02}, + /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02}, + /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02}, + /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01}, + /* Index30 -9.0dB */ {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */ + /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01}, + /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01}, + /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01}, + /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01}, + /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01}, + /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01}, + /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01}, + /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01}, + /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01}, + /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01}, + /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01}, + /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, + /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01}, + /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, + /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01}, + /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01}, + /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, + /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, + /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} +}; +u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00}, + /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00}, + /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00}, + /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00}, + /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00}, + /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00}, + /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00}, + /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00}, + /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00}, + /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00}, + /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00}, + /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00}, + /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00}, + /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00}, + /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00}, + /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00}, + /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00}, + /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00}, + /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00}, + /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00}, + /* Index20 -6 dB */ {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00}, + /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00}, + /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00}, + /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00}, + /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00}, + /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00}, + /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00}, + /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00}, + /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00}, + /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00}, + /* Index30 -9 dB */ {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00}, + /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00}, + /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00}, + /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00}, + /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00}, + /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00}, + /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00}, + /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00}, + /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00}, + /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00}, + /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00}, + /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00} +}; +#endif + +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\ + RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1) +u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = { + 0x081, /* 0, -12.0dB */ + 0x088, /* 1, -11.5dB */ + 0x090, /* 2, -11.0dB */ + 0x099, /* 3, -10.5dB */ + 0x0A2, /* 4, -10.0dB */ + 0x0AC, /* 5, -9.5dB */ + 0x0B6, /* 6, -9.0dB */ + 0x0C0, /* 7, -8.5dB */ + 0x0CC, /* 8, -8.0dB */ + 0x0D8, /* 9, -7.5dB */ + 0x0E5, /* 10, -7.0dB */ + 0x0F2, /* 11, -6.5dB */ + 0x101, /* 12, -6.0dB */ + 0x110, /* 13, -5.5dB */ + 0x120, /* 14, -5.0dB */ + 0x131, /* 15, -4.5dB */ + 0x143, /* 16, -4.0dB */ + 0x156, /* 17, -3.5dB */ + 0x16A, /* 18, -3.0dB */ + 0x180, /* 19, -2.5dB */ + 0x197, /* 20, -2.0dB */ + 0x1AF, /* 21, -1.5dB */ + 0x1C8, /* 22, -1.0dB */ + 0x1E3, /* 23, -0.5dB */ + 0x200, /* 24, +0 dB */ + 0x21E, /* 25, +0.5dB */ + 0x23E, /* 26, +1.0dB */ + 0x261, /* 27, +1.5dB */ + 0x285, /* 28, +2.0dB */ + 0x2AB, /* 29, +2.5dB */ + 0x2D3, /* 30, +3.0dB */ + 0x2FE, /* 31, +3.5dB */ + 0x32B, /* 32, +4.0dB */ + 0x35C, /* 33, +4.5dB */ + 0x38E, /* 34, +5.0dB */ + 0x3C4, /* 35, +5.5dB */ + 0x3FE /* 36, +6.0dB */ +}; +#elif(ODM_IC_11AC_SERIES_SUPPORT) +u32 ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812] = { + 0x3FE, /* 0, (6dB) */ + 0x3C4, /* 1, (5.5dB) */ + 0x38E, /* 2, (5dB) */ + 0x35C, /* 3, (4.5dB) */ + 0x32B, /* 4, (4dB) */ + 0x2FE, /* 5, (3.5dB) */ + 0x2D3, /* 6, (3dB) */ + 0x2AB, /* 7, (2.5dB) */ + 0x285, /* 8, (2dB) */ + 0x261, /* 9, (1.5dB */ + 0x23E, /* 10, (1dB) */ + 0x21E, /* 11, (0.5dB) */ + 0x200, /* 12, (0dB) 8814 int PA 2G default */ + 0x1E3, /* 13, (-0.5dB) */ + 0x1C8, /* 14, (-1dB) */ + 0x1AF, /* 15, (-1.5dB) */ + 0x197, /* 16, (-2dB) */ + 0x180, /* 17, (-2.5dB) */ + 0x16A, /* 18, (-3dB) 8812 / 8814 int PA 5G / 8814 ext PA 2G5G default */ + 0x156, /* 19, (-3.5dB) */ + 0x143, /* 20, (-4dB) 8812 HP default */ + 0x131, /* 21, (-4.5dB) */ + 0x120, /* 22, (-5dB) */ + 0x110, /* 23, (-5.5dB) */ + 0x101, /* 24, (-6dB) */ + 0x0F2, /* 25, (-6.5dB) */ + 0x0E5, /* 26, (-7dB) */ + 0x0D8, /* 27, (-7.5dB) */ + 0x0CC, /* 28, (-8dB) */ + 0x0C0, /* 29, (-8.5dB) */ + 0x0B6, /* 30, (-9dB) */ + 0x0AC, /* 31, (-9.5dB) */ + 0x0A2, /* 32, (-10dB) */ + 0x099, /* 33, (-10.5dB) */ + 0x090, /* 34, (-11dB) */ + 0x088, /* 35, (-11.5dB) */ + 0x081, /* 36, (-12dB) */ + 0x079, /* 37, (-12.5dB) */ + 0x072, /* 38, (-13dB) */ + 0x06c, /* 39, (-13.5dB) */ + 0x066, /* 40, (-14dB) */ + 0x060, /* 41, (-14.5dB) */ + 0x05B /* 42, (-15dB) */ +}; +#endif + +u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = { + 0x0CD, + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; +/* JJ ADD 20161014 */ +u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = { + 0x0CD, + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + + +/* #endif */ +/* 3============================================================ + * 3 Tx Power Tracking + * 3============================================================ */ + +void +odm_txpowertracking_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES))) + return; +#endif + + odm_txpowertracking_thermal_meter_init(dm); +} + + +u8 +get_swing_index( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0, bb_swing_mask = 0; + u32 bb_swing = 0; + u32 swing_table_size = 0; + u32 *swing_table = 0; + struct rtl8192cd_priv *priv = dm->priv; + +#if (RTL8197F_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8197F) { + bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D); + swing_table = ofdm_swing_table_new; + swing_table_size = OFDM_TABLE_SIZE_92D; + bb_swing_mask = 22; + } +#endif + +#if (RTL8192F_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8192F) { + bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D); + swing_table = ofdm_swing_table_new; + swing_table_size = OFDM_TABLE_SIZE_92D; + bb_swing_mask = 22; + } +#endif + +#if (RTL8822B_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8822B) { + bb_swing = phy_query_bb_reg(priv, REG_A_TX_SCALE_JAGUAR, 0xFFE00000); + swing_table = tx_scaling_table_jaguar; + swing_table_size = TXSCALE_TABLE_SIZE; + bb_swing_mask = 0; + } +#endif + + for (i = 0; i < swing_table_size - 1; i++) { + u32 table_value = swing_table[i] >> bb_swing_mask; + + if (bb_swing == table_value) + break; + } + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "bb_swing=0x%x bbswing_index=%d\n", bb_swing, i); + + + return i; +} + + +void +odm_txpowertracking_thermal_meter_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + struct rtl8192cd_priv *priv = dm->priv; + u8 p; + u8 default_swing_index; +#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1) + if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B) ||(GET_CHIP_VER(priv) == VERSION_8192F)) + default_swing_index = get_swing_index(dm); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &adapter->MgntInfo; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + mgnt_info->is_txpowertracking = true; + hal_data->tx_powercount = 0; + hal_data->is_txpowertracking_init = false; + + if (*(dm->mp_mode) == false) + hal_data->txpowertrack_control = true; + RF_DBG(dm, COMP_POWER_TRACKING, "mgnt_info->is_txpowertracking = %d\n", mgnt_info->is_txpowertracking); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#ifdef CONFIG_RTL8188E + { + dm->rf_calibrate_info.is_txpowertracking = true; + dm->rf_calibrate_info.tx_powercount = 0; + dm->rf_calibrate_info.is_txpowertracking_init = false; + + if (*(dm->mp_mode) == false) + dm->rf_calibrate_info.txpowertrack_control = true; + + MSG_8192C("dm txpowertrack_control = %d\n", dm->rf_calibrate_info.txpowertrack_control); + } +#else + { + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_priv *pdmpriv = &hal_data->dmpriv; + + pdmpriv->is_txpowertracking = true; + pdmpriv->tx_powercount = 0; + pdmpriv->is_txpowertracking_init = false; + + if (*(dm->mp_mode) == false) /* for mp driver, turn off txpwrtracking as default */ + pdmpriv->txpowertrack_control = true; + + MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control); + + } +#endif/* endif (CONFIG_RTL8188E==1) */ +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#ifdef RTL8188E_SUPPORT + { + dm->rf_calibrate_info.is_txpowertracking = true; + dm->rf_calibrate_info.tx_powercount = 0; + dm->rf_calibrate_info.is_txpowertracking_init = false; + dm->rf_calibrate_info.txpowertrack_control = true; + dm->rf_calibrate_info.tm_trigger = 0; + } +#endif +#endif + + dm->rf_calibrate_info.txpowertrack_control = true; + dm->rf_calibrate_info.delta_power_index = 0; + dm->rf_calibrate_info.delta_power_index_last = 0; + dm->rf_calibrate_info.power_index_offset = 0; + dm->rf_calibrate_info.thermal_value = 0; + cali_info->default_ofdm_index = 28; + +#if (RTL8197F_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8197F) { + cali_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index; + cali_info->default_cck_index = 28; + } +#endif + +#if (RTL8192F_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8192F) { + cali_info->default_ofdm_index = 30; + cali_info->default_cck_index = 28; + } +#endif + +#if (RTL8822B_SUPPORT == 1) + if (GET_CHIP_VER(priv) == VERSION_8822B) { + cali_info->default_ofdm_index = (default_swing_index >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : default_swing_index; + cali_info->default_cck_index = 20; + } +#endif + + +#if RTL8188E_SUPPORT + cali_info->default_cck_index = 20; /* -6 dB */ +#elif RTL8192E_SUPPORT + cali_info->default_cck_index = 8; /* -12 dB */ +#endif + cali_info->bb_swing_idx_ofdm_base = cali_info->default_ofdm_index; + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + dm->rf_calibrate_info.CCK_index = cali_info->default_cck_index; + + for (p = 0; p < MAX_RF_PATH; p++) { + dm->rf_calibrate_info.OFDM_index[p] = cali_info->default_ofdm_index; + cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index; + cali_info->kfree_offset[p] = 0; /* for 8814 kfree*/ + } + cali_info->bb_swing_idx_cck = cali_info->default_cck_index; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "cali_info->default_ofdm_index=%d cali_info->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index); + + cali_info->tm_trigger = 0; +} + + +void +odm_txpowertracking_check( + void *dm_void +) +{ + /* */ + /* For AP/ADSL use struct rtl8192cd_priv* */ + /* For CE/NIC use struct void* */ + /* */ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &(dm->rf_table); + + + if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + return; + + /* */ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ + /* */ + switch (dm->support_platform) { + case ODM_WIN: + odm_txpowertracking_check_mp(dm); + break; + + case ODM_CE: + odm_txpowertracking_check_ce(dm); + break; + + case ODM_AP: + odm_txpowertracking_check_ap(dm); + break; + } + +} + +void +odm_txpowertracking_check_ce( + void *dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + struct _hal_rf_ *rf = &(dm->rf_table); + +#if (RTL8188E_SUPPORT == 1) + + /* if(!mgnt_info->is_txpowertracking || (!pdmpriv->txpowertrack_control && pdmpriv->is_ap_kdone)) */ + + if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + return; + + if (!dm->rf_calibrate_info.tm_trigger) { /* at least delay 1 sec */ + /* hal_data->TxPowerCheckCnt++; */ /* cosa add for debug */ + odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); + /* DBG_8192C("Trigger 92C Thermal Meter!!\n"); */ + + dm->rf_calibrate_info.tm_trigger = 1; + return; + + } else { + /* DBG_8192C("Schedule TxPowerTracking direct call!!\n"); */ + odm_txpowertracking_callback_thermal_meter_8188e(adapter); + dm->rf_calibrate_info.tm_trigger = 0; + } +#endif + +#endif +} + +void +odm_txpowertracking_check_mp( + void *dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + + if (odm_check_power_status(adapter) == false) + return; + + if (!adapter->is_slave_of_dmsp || adapter->dual_mac_smart_concurrent == false) + odm_txpowertracking_thermal_meter_check(adapter); +#endif + +} + + +void +odm_txpowertracking_check_ap( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct rtl8192cd_priv *priv = dm->priv; + +#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || (RTL8198F_SUPPORT == 1)) + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8198F)) + odm_txpowertracking_callback_thermal_meter(dm); + else +#endif + { + } +#endif + +} diff --git a/hal/phydm/halrf/halrf_powertracking_ap.h b/hal/phydm/halrf/halrf_powertracking_ap.h new file mode 100644 index 0000000..8e1e6d4 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_ap.h @@ -0,0 +1,397 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __HALRF_POWERTRACKING_H__ +#define __HALRF_POWERTRACKING_H__ + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #ifdef RTK_AC_SUPPORT + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #else + #define ODM_IC_11AC_SERIES_SUPPORT 0 + #endif +#else + #define ODM_IC_11AC_SERIES_SUPPORT 1 +#endif + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 3 +#define MAX_RF_PATH 4 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 +/* JJ ADD 20161014 */ +#define CCK_TABLE_SIZE_8710B 41 + +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 + +#define IQK_BB_REG_NUM 9 + +#define AVG_THERMAL_NUM 8 +#define AVG_THERMAL_NUM_DPK 8 +#define THERMAL_DPK_AVG_NUM 4 + +#define iqk_matrix_reg_num 8 +/* #define IQK_MATRIX_SETTINGS_NUM 1+24+21 */ +#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ + +#if !defined(_OUTSRC_COEXIST) + #define OFDM_TABLE_SIZE_92D 43 + #define OFDM_TABLE_SIZE 37 + #define CCK_TABLE_SIZE 33 + #define CCK_TABLE_SIZE_88F 21 + #define CCK_TABLE_SIZE_8192F 41 + + + + /* #define OFDM_TABLE_SIZE_92E 54 */ + /* #define CCK_TABLE_SIZE_92E 54 */ + extern u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D]; + extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8]; + extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8]; + + + extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D]; + extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8]; + extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8]; + extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16]; + extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16]; + extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16]; + extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F]; + +#endif + +#define ODM_OFDM_TABLE_SIZE 37 +#define ODM_CCK_TABLE_SIZE 33 +/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */ +extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE]; +extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE]; + +static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +/* extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E]; + * extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8]; + * extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */ + +#ifdef CONFIG_WLAN_HAL_8192EE + #define OFDM_TABLE_SIZE_92E 54 + #define CCK_TABLE_SIZE_92E 54 + extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E]; + extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8]; + extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; +#endif + +#define OFDM_TABLE_SIZE_8812 43 +#define AVG_THERMAL_NUM_8812 4 + +#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 ||\ + RTL8821C_SUPPORT == 1 || RTL8198F_SUPPORT == 1) + extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE]; + #elif(ODM_IC_11AC_SERIES_SUPPORT) + extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812]; +#endif + +extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D]; +/* JJ ADD 20161014 */ +extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B]; + +#define dm_check_txpowertracking odm_txpowertracking_check + +struct iqk_matrix_regs_setting { + boolean is_iqk_done; + s32 value[1][iqk_matrix_reg_num]; +}; + +struct dm_rf_calibration_struct { + /* for tx power tracking */ + + u32 rega24; /* for TempCCK */ + s32 rege94; + s32 rege9c; + s32 regeb4; + s32 regebc; + + /* u8 is_txpowertracking; */ + u8 tx_powercount; + boolean is_txpowertracking_init; + boolean is_txpowertracking; + u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */ + u8 tm_trigger; + u8 internal_pa_5g[2]; /* pathA / pathB */ + + u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ + u8 thermal_value; + u8 thermal_value_lck; + u8 thermal_value_iqk; + s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ + + u8 thermal_value_avg[AVG_THERMAL_NUM]; + u8 thermal_value_avg_index; + u8 thermal_value_rx_gain; + u8 thermal_value_crystal; + u8 thermal_value_dpk_store; + u8 thermal_value_dpk_track; + boolean txpowertracking_in_progress; + + + boolean is_reloadtxpowerindex; + u8 is_rf_pi_enable; + u32 txpowertracking_callback_cnt; /* cosa add for debug */ + + u8 is_cck_in_ch14; + u8 CCK_index; + u8 OFDM_index[MAX_RF_PATH]; + s8 power_index_offset; + s8 delta_power_index; + s8 delta_power_index_last; + boolean is_tx_power_changed; + + struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + u8 delta_lck; + u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; + + u8 bb_swing_idx_ofdm[MAX_RF_PATH]; + u8 bb_swing_idx_ofdm_current; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + u8 bb_swing_idx_ofdm_base[MAX_RF_PATH]; +#else + u8 bb_swing_idx_ofdm_base; +#endif + boolean bb_swing_flag_ofdm; + u8 bb_swing_idx_cck; + u8 bb_swing_idx_cck_current; + u8 bb_swing_idx_cck_base; + u8 default_ofdm_index; + u8 default_cck_index; + boolean bb_swing_flag_cck; + + s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; + s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; + s8 absolute_cck_swing_idx[MAX_RF_PATH]; + s8 remnant_cck_swing_idx; + s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ + boolean modify_tx_agc_flag_path_a; + boolean modify_tx_agc_flag_path_b; + boolean modify_tx_agc_flag_path_c; + boolean modify_tx_agc_flag_path_d; + boolean modify_tx_agc_flag_path_a_cck; + boolean modify_tx_agc_flag_path_b_cck; + + s8 kfree_offset[MAX_RF_PATH]; + + /* -------------------------------------------------------------------- */ + + /* for IQK */ + u32 regc04; + u32 reg874; + u32 regc08; + u32 regb68; + u32 regb6c; + u32 reg870; + u32 reg860; + u32 reg864; + + boolean is_iqk_initialized; + boolean is_lck_in_progress; + boolean is_antenna_detected; + boolean is_need_iqk; + boolean is_iqk_in_progress; + boolean is_iqk_pa_off; + u8 delta_iqk; + u32 ADDA_backup[IQK_ADDA_REG_NUM]; + u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; + u32 IQK_BB_backup_recover[9]; + u32 IQK_BB_backup[IQK_BB_REG_NUM]; + u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + u64 iqk_start_time; + u64 iqk_total_progressing_time; + u64 iqk_progressing_time; + u64 lck_progressing_time; + u32 lok_result; + u8 iqk_step; + u8 kcount; + u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + boolean is_mp_mode; + + /* for APK */ + u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */ + u8 is_ap_kdone; + u8 is_apk_thermal_meter_ignore; + u8 is_dp_done; +#if 0 /*move below members to halrf_dpk.h*/ + u8 is_dp_path_aok; + u8 is_dp_path_bok; + u8 is_dp_path_cok; + u8 is_dp_path_dok; + u8 dp_path_a_result[3]; + u8 dp_path_b_result[3]; + u8 dp_path_c_result[3]; + u8 dp_path_d_result[3]; + boolean is_dpk_enable; + u32 txrate[11]; + u8 pwsf_2g_a[3]; + u8 pwsf_2g_b[3]; + u8 pwsf_2g_c[3]; + u8 pwsf_2g_d[3]; + u32 lut_2g_even_a[3][64]; + u32 lut_2g_odd_a[3][64]; + u32 lut_2g_even_b[3][64]; + u32 lut_2g_odd_b[3][64]; + u32 lut_2g_even_c[3][64]; + u32 lut_2g_odd_c[3][64]; + u32 lut_2g_even_d[3][64]; + u32 lut_2g_odd_d[3][64]; + u1Byte is_5g_pdk_a_ok; + u1Byte is_5g_pdk_b_ok; + u1Byte is_5g_pdk_c_ok; + u1Byte is_5g_pdk_d_ok; + u1Byte pwsf_5g_a[9]; + u1Byte pwsf_5g_b[9]; + u1Byte pwsf_5g_c[9]; + u1Byte pwsf_5g_d[9]; + u4Byte lut_5g_even_a[9][16]; + u4Byte lut_5g_odd_a[9][16]; + u4Byte lut_5g_even_b[9][16]; + u4Byte lut_5g_odd_b[9][16]; + u4Byte lut_5g_even_c[9][16]; + u4Byte lut_5g_odd_c[9][16]; + u4Byte lut_5g_even_d[9][16]; + u4Byte lut_5g_odd_d[9][16]; + u8 thermal_value_dpk; + u8 thermal_value_dpk_avg[AVG_THERMAL_NUM_DPK]; + u8 thermal_value_dpk_avg_index; +#endif + s8 modify_tx_agc_value_ofdm; + s8 modify_tx_agc_value_cck; + + /*Add by Yuchen for Kfree Phydm*/ + u8 reg_rf_kfree_enable; /*for registry*/ + u8 rf_kfree_enable; /*for efuse enable check*/ + u32 tx_lok[2]; +}; + +void +odm_txpowertracking_check_ap( + void *dm_void +); + +void +odm_txpowertracking_check( + void *dm_void +); + + +void +odm_txpowertracking_thermal_meter_init( + void *dm_void +); + +void +odm_txpowertracking_init( + void *dm_void +); + +void +odm_txpowertracking_check_mp( + void *dm_void +); + + +void +odm_txpowertracking_check_ce( + void *dm_void +); + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +void +odm_txpowertracking_callback_thermal_meter92c( + void *adapter +); + +void +odm_txpowertracking_callback_rx_gain_thermal_meter92d( + void *adapter +); + +void +odm_txpowertracking_callback_thermal_meter92d( + void *adapter +); + +void +odm_txpowertracking_direct_call92c( + void *adapter +); + +void +odm_txpowertracking_thermal_meter_check( + void *adapter +); + +#endif + + + +#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/ diff --git a/hal/phydm/halrf/halrf_powertracking_ce.c b/hal/phydm/halrf/halrf_powertracking_ce.c new file mode 100644 index 0000000..6a13d26 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_ce.c @@ -0,0 +1,840 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*============================================================ + * include files + *============================================================ + */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/* ************************************************************ + * Global var + * ************************************************************ + */ + +u32 ofdm_swing_table[OFDM_TABLE_SIZE] = { + 0x7f8001fe, /* 0, +6.0dB */ + 0x788001e2, /* 1, +5.5dB */ + 0x71c001c7, /* 2, +5.0dB*/ + 0x6b8001ae, /* 3, +4.5dB*/ + 0x65400195, /* 4, +4.0dB*/ + 0x5fc0017f, /* 5, +3.5dB*/ + 0x5a400169, /* 6, +3.0dB*/ + 0x55400155, /* 7, +2.5dB*/ + 0x50800142, /* 8, +2.0dB*/ + 0x4c000130, /* 9, +1.5dB*/ + 0x47c0011f, /* 10, +1.0dB*/ + 0x43c0010f, /* 11, +0.5dB*/ + 0x40000100, /* 12, +0dB*/ + 0x3c8000f2, /* 13, -0.5dB*/ + 0x390000e4, /* 14, -1.0dB*/ + 0x35c000d7, /* 15, -1.5dB*/ + 0x32c000cb, /* 16, -2.0dB*/ + 0x300000c0, /* 17, -2.5dB*/ + 0x2d4000b5, /* 18, -3.0dB*/ + 0x2ac000ab, /* 19, -3.5dB*/ + 0x288000a2, /* 20, -4.0dB*/ + 0x26000098, /* 21, -4.5dB*/ + 0x24000090, /* 22, -5.0dB*/ + 0x22000088, /* 23, -5.5dB*/ + 0x20000080, /* 24, -6.0dB*/ + 0x1e400079, /* 25, -6.5dB*/ + 0x1c800072, /* 26, -7.0dB*/ + 0x1b00006c, /* 27. -7.5dB*/ + 0x19800066, /* 28, -8.0dB*/ + 0x18000060, /* 29, -8.5dB*/ + 0x16c0005b, /* 30, -9.0dB*/ + 0x15800056, /* 31, -9.5dB*/ + 0x14400051, /* 32, -10.0dB*/ + 0x1300004c, /* 33, -10.5dB*/ + 0x12000048, /* 34, -11.0dB*/ + 0x11000044, /* 35, -11.5dB*/ + 0x10000040, /* 36, -12.0dB*/ +}; + +u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0 default*/ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ +}; + +u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0 default*/ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ +}; + +u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = { + 0x0b40002d, /* 0, -15.0dB */ + 0x0c000030, /* 1, -14.5dB */ + 0x0cc00033, /* 2, -14.0dB */ + 0x0d800036, /* 3, -13.5dB */ + 0x0e400039, /* 4, -13.0dB */ + 0x0f00003c, /* 5, -12.5dB */ + 0x10000040, /* 6, -12.0dB */ + 0x11000044, /* 7, -11.5dB */ + 0x12000048, /* 8, -11.0dB */ + 0x1300004c, /* 9, -10.5dB */ + 0x14400051, /* 10, -10.0dB */ + 0x15800056, /* 11, -9.5dB */ + 0x16c0005b, /* 12, -9.0dB */ + 0x18000060, /* 13, -8.5dB */ + 0x19800066, /* 14, -8.0dB */ + 0x1b00006c, /* 15, -7.5dB */ + 0x1c800072, /* 16, -7.0dB */ + 0x1e400079, /* 17, -6.5dB */ + 0x20000080, /* 18, -6.0dB */ + 0x22000088, /* 19, -5.5dB */ + 0x24000090, /* 20, -5.0dB */ + 0x26000098, /* 21, -4.5dB */ + 0x288000a2, /* 22, -4.0dB */ + 0x2ac000ab, /* 23, -3.5dB */ + 0x2d4000b5, /* 24, -3.0dB */ + 0x300000c0, /* 25, -2.5dB */ + 0x32c000cb, /* 26, -2.0dB */ + 0x35c000d7, /* 27, -1.5dB */ + 0x390000e4, /* 28, -1.0dB */ + 0x3c8000f2, /* 29, -0.5dB */ + 0x40000100, /* 30, +0dB */ + 0x43c0010f, /* 31, +0.5dB */ + 0x47c0011f, /* 32, +1.0dB */ + 0x4c000130, /* 33, +1.5dB */ + 0x50800142, /* 34, +2.0dB */ + 0x55400155, /* 35, +2.5dB */ + 0x5a400169, /* 36, +3.0dB */ + 0x5fc0017f, /* 37, +3.5dB */ + 0x65400195, /* 38, +4.0dB */ + 0x6b8001ae, /* 39, +4.5dB */ + 0x71c001c7, /* 40, +5.0dB */ + 0x788001e2, /* 41, +5.5dB */ + 0x7f8001fe /* 42, +6.0dB */ +}; + +u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + +u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + +u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + +u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/ + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/ +}; + +u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ +}; + +u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + +/* JJ ADD 20161014 */ +u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + +/* Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/ +u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, /*19*/ + 0x287, /*20*/ + 0x2AE, /*21*/ + 0x2D6, /*22*/ + 0x301, /*23*/ + 0x32F, /*24*/ + 0x35F, /*25*/ + 0x392, /*26*/ + 0x3C9, /*27*/ + 0x402, /*28*/ + 0x43F, /*29*/ + 0x47F, /*30*/ + 0x4C3, /*31*/ + 0x50C, /*32*/ + 0x558, /*33*/ + 0x5A9, /*34*/ + 0x5FF, /*35*/ + 0x65A, /*36*/ + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + +u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = { + 0x081, /* 0, -12.0dB*/ + 0x088, /* 1, -11.5dB*/ + 0x090, /* 2, -11.0dB*/ + 0x099, /* 3, -10.5dB*/ + 0x0A2, /* 4, -10.0dB*/ + 0x0AC, /* 5, -9.5dB*/ + 0x0B6, /* 6, -9.0dB*/ + 0x0C0, /*7, -8.5dB*/ + 0x0CC, /* 8, -8.0dB*/ + 0x0D8, /* 9, -7.5dB*/ + 0x0E5, /* 10, -7.0dB*/ + 0x0F2, /* 11, -6.5dB*/ + 0x101, /* 12, -6.0dB*/ + 0x110, /* 13, -5.5dB*/ + 0x120, /* 14, -5.0dB*/ + 0x131, /* 15, -4.5dB*/ + 0x143, /* 16, -4.0dB*/ + 0x156, /* 17, -3.5dB*/ + 0x16A, /* 18, -3.0dB*/ + 0x180, /* 19, -2.5dB*/ + 0x197, /* 20, -2.0dB*/ + 0x1AF, /* 21, -1.5dB*/ + 0x1C8, /* 22, -1.0dB*/ + 0x1E3, /* 23, -0.5dB*/ + 0x200, /* 24, +0 dB*/ + 0x21E, /* 25, +0.5dB*/ + 0x23E, /* 26, +1.0dB*/ + 0x261, /* 27, +1.5dB*/ + 0x285, /* 28, +2.0dB*/ + 0x2AB, /* 29, +2.5dB*/ + 0x2D3, /*30, +3.0dB*/ + 0x2FE, /* 31, +3.5dB*/ + 0x32B, /* 32, +4.0dB*/ + 0x35C, /* 33, +4.5dB*/ + 0x38E, /* 34, +5.0dB*/ + 0x3C4, /* 35, +5.5dB*/ + 0x3FE /* 36, +6.0dB */ +}; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#else +u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, + 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, + 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, + 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, + 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; +#endif + +void odm_txpowertracking_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_txpowertracking_thermal_meter_init(dm); +} + +u8 get_swing_index(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); +#endif + u8 i = 0; + u32 bb_swing, table_value; + + if (dm->support_ic_type & + (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E | + ODM_RTL8188F | ODM_RTL8703B | ODM_RTL8723D | + ODM_RTL8710B | ODM_RTL8821)) { +#if (RTL8821A_SUPPORT == 1) + bb_swing = + phy_get_tx_bb_swing_8812a(adapter, + hal_data->current_band_type, + RF_PATH_A); +#else + bb_swing = odm_get_bb_reg(dm, R_0xc80, 0xFFC00000); +#endif + for (i = 0; i < OFDM_TABLE_SIZE; i++) { + table_value = ofdm_swing_table_new[i]; + + if (table_value >= 0x100000) + table_value >>= 22; + if (bb_swing == table_value) + break; + } + } else { +#if (RTL8812A_SUPPORT == 1) + bb_swing = + phy_get_tx_bb_swing_8812a(adapter, + hal_data->current_band_type, + RF_PATH_A); +#else + bb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000); +#endif + for (i = 0; i < TXSCALE_TABLE_SIZE; i++) { + table_value = tx_scaling_table_jaguar[i]; + + if (bb_swing == table_value) + break; + } + } + + return i; +} + +u8 get_cck_swing_index(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + u8 i = 0; + u32 bb_cck_swing; + + if (dm->support_ic_type & + (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E)) { + bb_cck_swing = odm_read_1byte(dm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0]) + break; + } + } else if (dm->support_ic_type & ODM_RTL8703B) { + bb_cck_swing = odm_read_1byte(dm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0]) + break; + } + } + + return i; +} + +void odm_txpowertracking_thermal_meter_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 swing_idx = get_swing_index(dm); + u8 cckswing_idx = get_cck_swing_index(dm); + u8 p = 0; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + struct _hal_rf_ *rf = &dm->rf_table; + + cali_info->is_txpowertracking = true; + cali_info->tx_powercount = 0; + cali_info->is_txpowertracking_init = false; + + if (!(*dm->mp_mode)) + cali_info->txpowertrack_control = true; + else + cali_info->txpowertrack_control = false; + + if (!(*dm->mp_mode)) + cali_info->txpowertrack_control = true; + + RF_DBG(dm, DBG_RF_IQK, "dm txpowertrack_control = %d\n", + cali_info->txpowertrack_control); +#if 0 + /* dm->rf_calibrate_info.txpowertrack_control = true; */ +#endif + cali_info->thermal_value = rf->eeprom_thermal; + cali_info->thermal_value_iqk = rf->eeprom_thermal; + cali_info->thermal_value_lck = rf->eeprom_thermal; + + if (!cali_info->default_bb_swing_index_flag) { + if (dm->support_ic_type & + (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E | + ODM_RTL8703B | ODM_RTL8821)) { + if (swing_idx >= OFDM_TABLE_SIZE) + cali_info->default_ofdm_index = 30; + else + cali_info->default_ofdm_index = swing_idx; + + if (cckswing_idx >= CCK_TABLE_SIZE) + cali_info->default_cck_index = 20; + else + cali_info->default_cck_index = cckswing_idx; + /*add by Mingzhi.Guo 2015-03-23*/ + } else if (dm->support_ic_type == ODM_RTL8188F) { + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 20; /*CCK:-6dB*/ + /*add by zhaohe 2015-10-27*/ + } else if (dm->support_ic_type == ODM_RTL8723D) { + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 28; /*CCK: -6dB*/ + /* JJ ADD 20161014 */ + } else if (dm->support_ic_type == ODM_RTL8710B) { + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 28; /*CCK: -6dB*/ + } else if (dm->support_ic_type == ODM_RTL8192F) { + cali_info->default_ofdm_index = 30;/*OFDM: 0dB*/ + cali_info->default_cck_index = 28; /*CCK: -6dB*/ + } else { + if (swing_idx >= TXSCALE_TABLE_SIZE) + cali_info->default_ofdm_index = 24; + else + cali_info->default_ofdm_index = swing_idx; + + cali_info->default_cck_index = 24; + } + cali_info->default_bb_swing_index_flag = true; + } + + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + cali_info->CCK_index = cali_info->default_cck_index; + + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { + cali_info->bb_swing_idx_ofdm_base[p] = + cali_info->default_ofdm_index; + cali_info->OFDM_index[p] = cali_info->default_ofdm_index; + cali_info->delta_power_index[p] = 0; + cali_info->delta_power_index_last[p] = 0; + cali_info->power_index_offset[p] = 0; + } + cali_info->modify_tx_agc_value_ofdm = 0; + cali_info->modify_tx_agc_value_cck = 0; + cali_info->tm_trigger = 0; +} + +void odm_txpowertracking_check(void *dm_void) +{ + /* 2011/09/29 MH In HW integration first stage + * we provide 4 different handle to operate at the same time. + * In the stage2/3, we need to prive universal interface and merge all + * HW dynamic mechanism. + */ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + switch (dm->support_platform) { + case ODM_WIN: + odm_txpowertracking_check_mp(dm); + break; + + case ODM_CE: + odm_txpowertracking_check_ce(dm); + break; + + case ODM_AP: + odm_txpowertracking_check_ap(dm); + break; + + default: + break; + } +} + +void odm_txpowertracking_check_ce(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + return; + + if (!dm->rf_calibrate_info.tm_trigger) { + if (dm->support_ic_type & + (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8192E | + ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821 | + ODM_RTL8814A | ODM_RTL8703B | ODM_RTL8723D | + ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8710B | + ODM_RTL8192F)) + odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, + (BIT(17) | BIT(16)), 0x03); + else + odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD, + RFREGOFFSETMASK, 0x60); + + dm->rf_calibrate_info.tm_trigger = 1; + return; + } + + odm_txpowertracking_callback_thermal_meter(dm); + dm->rf_calibrate_info.tm_trigger = 0; +#endif +} + +void odm_txpowertracking_check_mp(void *dm_void) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + + if (odm_check_power_status(adapter) == false) { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, + ("check_pow_status, return false\n")); + return; + } + + odm_txpowertracking_thermal_meter_check(adapter); +#endif +} + +void odm_txpowertracking_check_ap(void *dm_void) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rtl8192cd_priv *priv = dm->priv; + + return; + +#endif +} diff --git a/hal/phydm/halrf/halrf_powertracking_ce.h b/hal/phydm/halrf/halrf_powertracking_ce.h new file mode 100644 index 0000000..ef2b0ba --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_ce.h @@ -0,0 +1,325 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_POWERTRACKING_H__ +#define __HALRF_POWERTRACKING_H__ + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_88F 21 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 +/* JJ ADD 20161014 */ +#define CCK_TABLE_SIZE_8710B 41 +#define CCK_TABLE_SIZE_8192F 41 + +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 4 + +#define AVG_THERMAL_NUM 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 + +#define IQK_BB_REG_NUM 9 + +#define iqk_matrix_reg_num 8 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#else +/* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ +#define IQK_MATRIX_SETTINGS_NUM (14 + 24 + 21) +#endif + +extern u32 ofdm_swing_table[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8]; + +extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D]; +/* JJ ADD 20161014 */ +extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B]; +extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F]; + +extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE]; + +/* <20121018, Kordan> In case fail to read TxPowerTrack.txt */ +/* we use the table of 88E as the default table. */ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#else +extern u8 delta_swing_table_idx_2ga_p_8188e[]; +extern u8 delta_swing_table_idx_2ga_n_8188e[]; +#endif + +#define dm_check_txpowertracking odm_txpowertracking_check + +struct iqk_matrix_regs_setting { + boolean is_iqk_done; + s32 value[3][iqk_matrix_reg_num]; + boolean is_bw_iqk_result_saved[3]; +}; + +struct dm_rf_calibration_struct { + /* for tx power tracking */ + + u32 rega24; /* for TempCCK */ + s32 rege94; + s32 rege9c; + s32 regeb4; + s32 regebc; + + u8 tx_powercount; + boolean is_txpowertracking_init; + boolean is_txpowertracking; + /* for mp mode, turn off txpwrtracking as default */ + u8 txpowertrack_control; + u8 tm_trigger; + u8 internal_pa_5g[2]; /* pathA / pathB */ + + /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ + u8 thermal_meter[2]; + u8 thermal_value; + u8 thermal_value_lck; + u8 thermal_value_iqk; + s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ + u8 thermal_value_dpk; + u8 thermal_value_avg[AVG_THERMAL_NUM]; + u8 thermal_value_avg_index; + u8 thermal_value_rx_gain; + u8 thermal_value_crystal; + u8 thermal_value_dpk_store; + u8 thermal_value_dpk_track; + boolean txpowertracking_in_progress; + + boolean is_reloadtxpowerindex; + u8 is_rf_pi_enable; + u32 txpowertracking_callback_cnt; /* cosa add for debug */ + + /* ---------------------- Tx power Tracking ---------------------- */ + u8 is_cck_in_ch14; + u8 CCK_index; + u8 OFDM_index[MAX_RF_PATH]; + s8 power_index_offset[MAX_RF_PATH]; + s8 delta_power_index[MAX_RF_PATH]; + s8 delta_power_index_last[MAX_RF_PATH]; + boolean is_tx_power_changed; + s8 xtal_offset; + s8 xtal_offset_last; + u8 xtal_offset_eanble; + + struct iqk_matrix_regs_setting + iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + u8 delta_lck; + s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */ + u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; + + u8 bb_swing_idx_ofdm[MAX_RF_PATH]; + u8 bb_swing_idx_ofdm_current; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + u8 bb_swing_idx_ofdm_base[MAX_RF_PATH]; +#else + u8 bb_swing_idx_ofdm_base; +#endif + boolean default_bb_swing_index_flag; + boolean bb_swing_flag_ofdm; + u8 bb_swing_idx_cck; + u8 bb_swing_idx_cck_current; + u8 bb_swing_idx_cck_base; + u8 default_ofdm_index; + u8 default_cck_index; + boolean bb_swing_flag_cck; + + s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; + s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; + s8 absolute_cck_swing_idx[MAX_RF_PATH]; + s8 remnant_cck_swing_idx; + s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ + boolean modify_tx_agc_flag_path_a; + boolean modify_tx_agc_flag_path_b; + boolean modify_tx_agc_flag_path_c; + boolean modify_tx_agc_flag_path_d; + boolean modify_tx_agc_flag_path_a_cck; + boolean modify_tx_agc_flag_path_b_cck; + + s8 kfree_offset[MAX_RF_PATH]; + + /* ----------------------------------------------------------------- */ + + /* for IQK */ + u32 regc04; + u32 reg874; + u32 regc08; + u32 regb68; + u32 regb6c; + u32 reg870; + u32 reg860; + u32 reg864; + + boolean is_iqk_initialized; + boolean is_lck_in_progress; + boolean is_antenna_detected; + boolean is_need_iqk; + boolean is_iqk_in_progress; + boolean is_iqk_pa_off; + u8 delta_iqk; + u32 ADDA_backup[IQK_ADDA_REG_NUM]; + u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; + u32 IQK_BB_backup_recover[9]; + u32 IQK_BB_backup[IQK_BB_REG_NUM]; + /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 tx_iqc_8723b[2][3][2]; + /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 rx_iqc_8723b[2][2][2]; + /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 tx_iqc_8703b[3][2]; + /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 rx_iqc_8703b[2][2]; + /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 tx_iqc_8723d[2][3][2]; + /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 rx_iqc_8723d[2][2][2]; + /* JJ ADD 20161014 */ + /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 tx_iqc_8710b[2][3][2]; + /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 rx_iqc_8710b[2][2][2]; + + u8 iqk_step; + u8 kcount; + u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + boolean is_mp_mode; + + /* IQK time measurement */ + u64 iqk_start_time; + u64 iqk_progressing_time; + u64 iqk_total_progressing_time; + u64 lck_progressing_time; + + u32 lok_result; + + /* for APK */ + u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */ + u8 is_ap_kdone; + u8 is_apk_thermal_meter_ignore; + + /* DPK */ + boolean is_dpk_fail; + u8 is_dp_done; + u8 is_dp_path_aok; + u8 is_dp_path_bok; + + u32 tx_lok[2]; + u32 dpk_tx_agc; + s32 dpk_gain; + u32 dpk_thermal[4]; + s8 modify_tx_agc_value_ofdm; + s8 modify_tx_agc_value_cck; + + /*Add by Yuchen for Kfree Phydm*/ + u8 reg_rf_kfree_enable; /*for registry*/ + u8 rf_kfree_enable; /*for efuse enable check*/ +}; + +void odm_txpowertracking_check(void *dm_void); + +void odm_txpowertracking_init(void *dm_void); + +void odm_txpowertracking_check_ap(void *dm_void); + +void odm_txpowertracking_thermal_meter_init(void *dm_void); + +void odm_txpowertracking_init(void *dm_void); + +void odm_txpowertracking_check_mp(void *dm_void); + +void odm_txpowertracking_check_ce(void *dm_void); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +void odm_txpowertracking_callback_thermal_meter92c( + void *adapter); + +void odm_txpowertracking_callback_rx_gain_thermal_meter92d( + void *adapter); + +void odm_txpowertracking_callback_thermal_meter92d( + void *adapter); + +void odm_txpowertracking_direct_call92c( + void *adapter); + +void odm_txpowertracking_thermal_meter_check( + void *adapter); + +#endif + +#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/ diff --git a/hal/phydm/halrf/halrf_powertracking_iot.c b/hal/phydm/halrf/halrf_powertracking_iot.c new file mode 100644 index 0000000..7a38741 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_iot.c @@ -0,0 +1,690 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*============================================================ */ +/* include files */ +/*============================================================ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/* ************************************************************ + * Global var + * ************************************************************ + */ + +u32 ofdm_swing_table[OFDM_TABLE_SIZE] = { + 0x7f8001fe, /* 0, +6.0dB */ + 0x788001e2, /* 1, +5.5dB */ + 0x71c001c7, /* 2, +5.0dB*/ + 0x6b8001ae, /* 3, +4.5dB*/ + 0x65400195, /* 4, +4.0dB*/ + 0x5fc0017f, /* 5, +3.5dB*/ + 0x5a400169, /* 6, +3.0dB*/ + 0x55400155, /* 7, +2.5dB*/ + 0x50800142, /* 8, +2.0dB*/ + 0x4c000130, /* 9, +1.5dB*/ + 0x47c0011f, /* 10, +1.0dB*/ + 0x43c0010f, /* 11, +0.5dB*/ + 0x40000100, /* 12, +0dB*/ + 0x3c8000f2, /* 13, -0.5dB*/ + 0x390000e4, /* 14, -1.0dB*/ + 0x35c000d7, /* 15, -1.5dB*/ + 0x32c000cb, /* 16, -2.0dB*/ + 0x300000c0, /* 17, -2.5dB*/ + 0x2d4000b5, /* 18, -3.0dB*/ + 0x2ac000ab, /* 19, -3.5dB*/ + 0x288000a2, /* 20, -4.0dB*/ + 0x26000098, /* 21, -4.5dB*/ + 0x24000090, /* 22, -5.0dB*/ + 0x22000088, /* 23, -5.5dB*/ + 0x20000080, /* 24, -6.0dB*/ + 0x1e400079, /* 25, -6.5dB*/ + 0x1c800072, /* 26, -7.0dB*/ + 0x1b00006c, /* 27. -7.5dB*/ + 0x19800066, /* 28, -8.0dB*/ + 0x18000060, /* 29, -8.5dB*/ + 0x16c0005b, /* 30, -9.0dB*/ + 0x15800056, /* 31, -9.5dB*/ + 0x14400051, /* 32, -10.0dB*/ + 0x1300004c, /* 33, -10.5dB*/ + 0x12000048, /* 34, -11.0dB*/ + 0x11000044, /* 35, -11.5dB*/ + 0x10000040, /* 36, -12.0dB*/ +}; + +u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/ + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/ +}; + +u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default*/ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/ + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/ +}; + +u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = { + 0x0b40002d, /* 0, -15.0dB */ + 0x0c000030, /* 1, -14.5dB*/ + 0x0cc00033, /* 2, -14.0dB*/ + 0x0d800036, /* 3, -13.5dB*/ + 0x0e400039, /* 4, -13.0dB */ + 0x0f00003c, /* 5, -12.5dB*/ + 0x10000040, /* 6, -12.0dB*/ + 0x11000044, /* 7, -11.5dB*/ + 0x12000048, /* 8, -11.0dB*/ + 0x1300004c, /* 9, -10.5dB*/ + 0x14400051, /* 10, -10.0dB*/ + 0x15800056, /* 11, -9.5dB*/ + 0x16c0005b, /* 12, -9.0dB*/ + 0x18000060, /* 13, -8.5dB*/ + 0x19800066, /* 14, -8.0dB*/ + 0x1b00006c, /* 15, -7.5dB*/ + 0x1c800072, /* 16, -7.0dB*/ + 0x1e400079, /* 17, -6.5dB*/ + 0x20000080, /* 18, -6.0dB*/ + 0x22000088, /* 19, -5.5dB*/ + 0x24000090, /* 20, -5.0dB*/ + 0x26000098, /* 21, -4.5dB*/ + 0x288000a2, /* 22, -4.0dB*/ + 0x2ac000ab, /* 23, -3.5dB*/ + 0x2d4000b5, /* 24, -3.0dB*/ + 0x300000c0, /* 25, -2.5dB*/ + 0x32c000cb, /* 26, -2.0dB*/ + 0x35c000d7, /* 27, -1.5dB*/ + 0x390000e4, /* 28, -1.0dB*/ + 0x3c8000f2, /* 29, -0.5dB*/ + 0x40000100, /* 30, +0dB*/ + 0x43c0010f, /* 31, +0.5dB*/ + 0x47c0011f, /* 32, +1.0dB*/ + 0x4c000130, /* 33, +1.5dB*/ + 0x50800142, /* 34, +2.0dB*/ + 0x55400155, /* 35, +2.5dB*/ + 0x5a400169, /* 36, +3.0dB*/ + 0x5fc0017f, /* 37, +3.5dB*/ + 0x65400195, /* 38, +4.0dB*/ + 0x6b8001ae, /* 39, +4.5dB*/ + 0x71c001c7, /* 40, +5.0dB*/ + 0x788001e2, /* 41, +5.5dB*/ + 0x7f8001fe /* 42, +6.0dB*/ +}; + +u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + +u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + +u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + +u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/ + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/ +}; + +u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ +}; + +u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + +/* JJ ADD 20161014 */ +u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + +/* Winnita ADD 20171116 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/ +u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, /*19*/ + 0x287, /*20*/ + 0x2AE, /*21*/ + 0x2D6, /*22*/ + 0x301, /*23*/ + 0x32F, /*24*/ + 0x35F, /*25*/ + 0x392, /*26*/ + 0x3C9, /*27*/ + 0x402, /*28*/ + 0x43F, /*29*/ + 0x47F, /*30*/ + 0x4C3, /*31*/ + 0x50C, /*32*/ + 0x558, /*33*/ + 0x5A9, /*34*/ + 0x5FF, /*35*/ + 0x65A, /*36*/ + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + +u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = { + 0x081, /* 0, -12.0dB*/ + 0x088, /* 1, -11.5dB*/ + 0x090, /* 2, -11.0dB*/ + 0x099, /* 3, -10.5dB*/ + 0x0A2, /* 4, -10.0dB*/ + 0x0AC, /* 5, -9.5dB*/ + 0x0B6, /* 6, -9.0dB*/ + 0x0C0, /*7, -8.5dB*/ + 0x0CC, /* 8, -8.0dB*/ + 0x0D8, /* 9, -7.5dB*/ + 0x0E5, /* 10, -7.0dB*/ + 0x0F2, /* 11, -6.5dB*/ + 0x101, /* 12, -6.0dB*/ + 0x110, /* 13, -5.5dB*/ + 0x120, /* 14, -5.0dB*/ + 0x131, /* 15, -4.5dB*/ + 0x143, /* 16, -4.0dB*/ + 0x156, /* 17, -3.5dB*/ + 0x16A, /* 18, -3.0dB*/ + 0x180, /* 19, -2.5dB*/ + 0x197, /* 20, -2.0dB*/ + 0x1AF, /* 21, -1.5dB*/ + 0x1C8, /* 22, -1.0dB*/ + 0x1E3, /* 23, -0.5dB*/ + 0x200, /* 24, +0 dB*/ + 0x21E, /* 25, +0.5dB*/ + 0x23E, /* 26, +1.0dB*/ + 0x261, /* 27, +1.5dB*/ + 0x285,/* 28, +2.0dB*/ + 0x2AB, /* 29, +2.5dB*/ + 0x2D3, /*30, +3.0dB*/ + 0x2FE, /* 31, +3.5dB*/ + 0x32B, /* 32, +4.0dB*/ + 0x35C, /* 33, +4.5dB*/ + 0x38E, /* 34, +5.0dB*/ + 0x3C4, /* 35, +5.5dB*/ + 0x3FE /* 36, +6.0dB */ +}; + +void +odm_txpowertracking_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_txpowertracking_thermal_meter_init(dm); +} + +u8 +get_swing_index( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + u8 i = 0; + u32 bb_swing; + u32 swing_table_size; + u32 *swing_table; + + if (dm->support_ic_type == ODM_RTL8195B) { + bb_swing = odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000); + swing_table = tx_scaling_table_jaguar; + swing_table_size = TXSCALE_TABLE_SIZE; + } + + for (i = 0; i < swing_table_size; i++) { + u32 table_value = swing_table[i]; + + table_value = table_value; + if (bb_swing == table_value) + break; + } + + return i; +} + +u8 +get_cck_swing_index( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + u8 i = 0; + u32 bb_cck_swing; + + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B || + dm->support_ic_type == ODM_RTL8192E) { + bb_cck_swing = odm_read_1byte(dm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0]) + break; + } + } else if (dm->support_ic_type == ODM_RTL8703B) { + bb_cck_swing = odm_read_1byte(dm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0]) + break; + } + } + + return i; +} + +void +odm_txpowertracking_thermal_meter_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 default_swing_index = get_swing_index(dm); + u8 p = 0; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + struct _hal_rf_ *rf = &dm->rf_table; + + if (!(*dm->mp_mode)) + cali_info->txpowertrack_control = true; + else + cali_info->txpowertrack_control = false; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "dm txpowertrack_control = %d\n", cali_info->txpowertrack_control); + + /* dm->rf_calibrate_info.txpowertrack_control = true; */ + cali_info->thermal_value = rf->eeprom_thermal; + cali_info->thermal_value_iqk = rf->eeprom_thermal; + cali_info->thermal_value_lck = rf->eeprom_thermal; + + if (!cali_info->default_bb_swing_index_flag) { + if (dm->support_ic_type == ODM_RTL8195B) { + cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index; + cali_info->default_cck_index = 24; + } + cali_info->default_bb_swing_index_flag = true; + } + + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + cali_info->CCK_index = cali_info->default_cck_index; + + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index; + cali_info->OFDM_index[p] = cali_info->default_ofdm_index; + cali_info->delta_power_index[p] = 0; + cali_info->delta_power_index_last[p] = 0; + cali_info->power_index_offset[p] = 0; + } + cali_info->modify_tx_agc_value_ofdm = 0; + cali_info->modify_tx_agc_value_cck = 0; + cali_info->tm_trigger = 0; +} + +void +odm_txpowertracking_check( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_txpowertracking_check_iot(dm); +} + +void +odm_txpowertracking_check_iot( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + return; + + if (!dm->rf_calibrate_info.tm_trigger) { + if (dm->support_ic_type == ODM_RTL8195B) + odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03); + + dm->rf_calibrate_info.tm_trigger = 1; + return; + } + odm_txpowertracking_callback_thermal_meter(dm); + dm->rf_calibrate_info.tm_trigger = 0; +} + +void +odm_txpowertracking_check_mp( + void *dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + + if (odm_check_power_status(adapter) == false) { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status, return false\n")); + return; + } + + odm_txpowertracking_thermal_meter_check(adapter); +#endif +} + +void +odm_txpowertracking_check_ap( + void *dm_void +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rtl8192cd_priv *priv = dm->priv; + + return; + +#endif +} diff --git a/hal/phydm/halrf/halrf_powertracking_iot.h b/hal/phydm/halrf/halrf_powertracking_iot.h new file mode 100644 index 0000000..91813aa --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_iot.h @@ -0,0 +1,347 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_POWERTRACKING_H__ +#define __HALRF_POWERTRACKING_H__ + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_88F 21 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 +/* JJ ADD 20161014 */ +#define CCK_TABLE_SIZE_8710B 41 +#define CCK_TABLE_SIZE_8192F 41 + + +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 4 + +#define AVG_THERMAL_NUM 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 + +#define IQK_BB_REG_NUM 9 + + + +#define iqk_matrix_reg_num 8 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#else +#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ +#endif + +extern u32 ofdm_swing_table[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8]; + +extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D]; +/* JJ ADD 20161014 */ +extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B]; +extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F]; + +extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE]; + +/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#else +static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; +#endif + +void +odm_txpowertracking_init( + void *dm_void +); + +#define dm_check_txpowertracking odm_txpowertracking_check + +struct iqk_matrix_regs_setting { + boolean is_iqk_done; + s32 value[3][iqk_matrix_reg_num]; + boolean is_bw_iqk_result_saved[3]; +}; + +struct dm_rf_calibration_struct { + /* for tx power tracking */ + + u32 rega24; /* for TempCCK */ + s32 rege94; + s32 rege9c; + s32 regeb4; + s32 regebc; + + u8 tx_powercount; + boolean is_txpowertracking_init; + boolean is_txpowertracking; + u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */ + u8 tm_trigger; + u8 internal_pa_5g[2]; /* pathA / pathB */ + + u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ + u8 thermal_value; + u8 thermal_value_lck; + u8 thermal_value_iqk; + s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ + u8 thermal_value_dpk; + u8 thermal_value_avg[AVG_THERMAL_NUM]; + u8 thermal_value_avg_index; + u8 thermal_value_rx_gain; + u8 thermal_value_crystal; + u8 thermal_value_dpk_store; + u8 thermal_value_dpk_track; + boolean txpowertracking_in_progress; + + boolean is_reloadtxpowerindex; + u8 is_rf_pi_enable; + u32 txpowertracking_callback_cnt; /* cosa add for debug */ + + + /* ------------------------- Tx power Tracking ------------------------- */ + u8 is_cck_in_ch14; + u8 CCK_index; + u8 OFDM_index[MAX_RF_PATH]; + s8 power_index_offset[MAX_RF_PATH]; + s8 delta_power_index[MAX_RF_PATH]; + s8 delta_power_index_last[MAX_RF_PATH]; + boolean is_tx_power_changed; + s8 xtal_offset; + s8 xtal_offset_last; + + struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + u8 delta_lck; + s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */ + u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; + + u8 bb_swing_idx_ofdm[MAX_RF_PATH]; + u8 bb_swing_idx_ofdm_current; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT)) + u8 bb_swing_idx_ofdm_base[MAX_RF_PATH]; +#else + u8 bb_swing_idx_ofdm_base; +#endif + boolean default_bb_swing_index_flag; + boolean bb_swing_flag_ofdm; + u8 bb_swing_idx_cck; + u8 bb_swing_idx_cck_current; + u8 bb_swing_idx_cck_base; + u8 default_ofdm_index; + u8 default_cck_index; + boolean bb_swing_flag_cck; + + s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; + s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; + s8 absolute_cck_swing_idx[MAX_RF_PATH]; + s8 remnant_cck_swing_idx; + s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ + boolean modify_tx_agc_flag_path_a; + boolean modify_tx_agc_flag_path_b; + boolean modify_tx_agc_flag_path_c; + boolean modify_tx_agc_flag_path_d; + boolean modify_tx_agc_flag_path_a_cck; + boolean modify_tx_agc_flag_path_b_cck; + + s8 kfree_offset[MAX_RF_PATH]; + + /* -------------------------------------------------------------------- */ + + /* for IQK */ + u32 regc04; + u32 reg874; + u32 regc08; + u32 regb68; + u32 regb6c; + u32 reg870; + u32 reg860; + u32 reg864; + + boolean is_iqk_initialized; + boolean is_lck_in_progress; + boolean is_antenna_detected; + boolean is_need_iqk; + boolean is_iqk_in_progress; + boolean is_iqk_pa_off; + u8 delta_iqk; + u32 ADDA_backup[IQK_ADDA_REG_NUM]; + u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; + u32 IQK_BB_backup_recover[9]; + u32 IQK_BB_backup[IQK_BB_REG_NUM]; + u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + /* JJ ADD 20161014 */ + u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + u8 iqk_step; + u8 kcount; + u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + boolean is_mp_mode; + + + + /* IQK time measurement */ + u64 iqk_start_time; + u64 iqk_progressing_time; + u64 iqk_total_progressing_time; + u64 lck_progressing_time; + + u32 lok_result; + + /* for APK */ + u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */ + u8 is_ap_kdone; + u8 is_apk_thermal_meter_ignore; + + /* DPK */ + boolean is_dpk_fail; + u8 is_dp_done; + u8 is_dp_path_aok; + u8 is_dp_path_bok; + + u32 tx_lok[2]; + u32 dpk_tx_agc; + s32 dpk_gain; + u32 dpk_thermal[4]; + s8 modify_tx_agc_value_ofdm; + s8 modify_tx_agc_value_cck; + + /*Add by Yuchen for Kfree Phydm*/ + u8 reg_rf_kfree_enable; /*for registry*/ + u8 rf_kfree_enable; /*for efuse enable check*/ + +}; + + +void +odm_txpowertracking_check( + void *dm_void +); + +void +odm_txpowertracking_check_ap( + void *dm_void +); + +void +odm_txpowertracking_thermal_meter_init( + void *dm_void +); + + +void +odm_txpowertracking_check_mp( + void *dm_void +); + + +void +odm_txpowertracking_check_iot( + void *dm_void +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +void +odm_txpowertracking_callback_thermal_meter92c( + void *adapter +); + +void +odm_txpowertracking_callback_rx_gain_thermal_meter92d( + void *adapter +); + +void +odm_txpowertracking_callback_thermal_meter92d( + void *adapter +); + +void +odm_txpowertracking_direct_call92c( + void *adapter +); + +void +odm_txpowertracking_thermal_meter_check( + void *adapter +); + +#endif + +#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/ diff --git a/hal/phydm/halrf/halrf_powertracking_win.c b/hal/phydm/halrf/halrf_powertracking_win.c new file mode 100644 index 0000000..5df97b3 --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_win.c @@ -0,0 +1,859 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/*============================================================ */ +/* include files */ +/*============================================================ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/* ************************************************************ + * Global var + * ************************************************************ */ + +u32 ofdm_swing_table[OFDM_TABLE_SIZE] = { + 0x7f8001fe, /* 0, +6.0dB */ + 0x788001e2, /* 1, +5.5dB */ + 0x71c001c7, /* 2, +5.0dB */ + 0x6b8001ae, /* 3, +4.5dB */ + 0x65400195, /* 4, +4.0dB */ + 0x5fc0017f, /* 5, +3.5dB */ + 0x5a400169, /* 6, +3.0dB */ + 0x55400155, /* 7, +2.5dB */ + 0x50800142, /* 8, +2.0dB */ + 0x4c000130, /* 9, +1.5dB */ + 0x47c0011f, /* 10, +1.0dB */ + 0x43c0010f, /* 11, +0.5dB */ + 0x40000100, /* 12, +0dB */ + 0x3c8000f2, /* 13, -0.5dB */ + 0x390000e4, /* 14, -1.0dB */ + 0x35c000d7, /* 15, -1.5dB */ + 0x32c000cb, /* 16, -2.0dB */ + 0x300000c0, /* 17, -2.5dB */ + 0x2d4000b5, /* 18, -3.0dB */ + 0x2ac000ab, /* 19, -3.5dB */ + 0x288000a2, /* 20, -4.0dB */ + 0x26000098, /* 21, -4.5dB */ + 0x24000090, /* 22, -5.0dB */ + 0x22000088, /* 23, -5.5dB */ + 0x20000080, /* 24, -6.0dB */ + 0x1e400079, /* 25, -6.5dB */ + 0x1c800072, /* 26, -7.0dB */ + 0x1b00006c, /* 27. -7.5dB */ + 0x19800066, /* 28, -8.0dB */ + 0x18000060, /* 29, -8.5dB */ + 0x16c0005b, /* 30, -9.0dB */ + 0x15800056, /* 31, -9.5dB */ + 0x14400051, /* 32, -10.0dB */ + 0x1300004c, /* 33, -10.5dB */ + 0x12000048, /* 34, -11.0dB */ + 0x11000044, /* 35, -11.5dB */ + 0x10000040, /* 36, -12.0dB */ +}; + +u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ +}; + + +u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ +}; + + +u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = { + 0x0b40002d, /* 0, -15.0dB */ + 0x0c000030, /* 1, -14.5dB */ + 0x0cc00033, /* 2, -14.0dB */ + 0x0d800036, /* 3, -13.5dB */ + 0x0e400039, /* 4, -13.0dB */ + 0x0f00003c, /* 5, -12.5dB */ + 0x10000040, /* 6, -12.0dB */ + 0x11000044, /* 7, -11.5dB */ + 0x12000048, /* 8, -11.0dB */ + 0x1300004c, /* 9, -10.5dB */ + 0x14400051, /* 10, -10.0dB */ + 0x15800056, /* 11, -9.5dB */ + 0x16c0005b, /* 12, -9.0dB */ + 0x18000060, /* 13, -8.5dB */ + 0x19800066, /* 14, -8.0dB */ + 0x1b00006c, /* 15, -7.5dB */ + 0x1c800072, /* 16, -7.0dB */ + 0x1e400079, /* 17, -6.5dB */ + 0x20000080, /* 18, -6.0dB */ + 0x22000088, /* 19, -5.5dB */ + 0x24000090, /* 20, -5.0dB */ + 0x26000098, /* 21, -4.5dB */ + 0x288000a2, /* 22, -4.0dB */ + 0x2ac000ab, /* 23, -3.5dB */ + 0x2d4000b5, /* 24, -3.0dB */ + 0x300000c0, /* 25, -2.5dB */ + 0x32c000cb, /* 26, -2.0dB */ + 0x35c000d7, /* 27, -1.5dB */ + 0x390000e4, /* 28, -1.0dB */ + 0x3c8000f2, /* 29, -0.5dB */ + 0x40000100, /* 30, +0dB */ + 0x43c0010f, /* 31, +0.5dB */ + 0x47c0011f, /* 32, +1.0dB */ + 0x4c000130, /* 33, +1.5dB */ + 0x50800142, /* 34, +2.0dB */ + 0x55400155, /* 35, +2.5dB */ + 0x5a400169, /* 36, +3.0dB */ + 0x5fc0017f, /* 37, +3.5dB */ + 0x65400195, /* 38, +4.0dB */ + 0x6b8001ae, /* 39, +4.5dB */ + 0x71c001c7, /* 40, +5.0dB */ + 0x788001e2, /* 41, +5.5dB */ + 0x7f8001fe /* 42, +6.0dB */ +}; + + +u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */ +}; + + +u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ +}; +u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = { + 0x0CD, + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; +/* JJ ADD 20161014 */ +u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, /*19*/ + 0x287, /*20*/ + 0x2AE, /*21*/ + 0x2D6, /*22*/ + 0x301, /*23*/ + 0x32F, /*24*/ + 0x35F, /*25*/ + 0x392, /*26*/ + 0x3C9, /*27*/ + 0x402, /*28*/ + 0x43F, /*29*/ + 0x47F, /*30*/ + 0x4C3, /*31*/ + 0x50C, /*32*/ + 0x558, /*33*/ + 0x5A9, /*34*/ + 0x5FF, /*35*/ + 0x65A, /*36*/ + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + +/* Winnita ADD 20170828 PathA 0xAB4[10:0],PathB 0xAB4[21:11]*/ +u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, /*19*/ + 0x287, /*20*/ + 0x2AE, /*21*/ + 0x2D6, /*22*/ + 0x301, /*23*/ + 0x32F, /*24*/ + 0x35F, /*25*/ + 0x392, /*26*/ + 0x3C9, /*27*/ + 0x402, /*28*/ + 0x43F, /*29*/ + 0x47F, /*30*/ + 0x4C3, /*31*/ + 0x50C, /*32*/ + 0x558, /*33*/ + 0x5A9, /*34*/ + 0x5FF, /*35*/ + 0x65A, /*36*/ + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + +u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = { + 0x081, /* 0, -12.0dB */ + 0x088, /* 1, -11.5dB */ + 0x090, /* 2, -11.0dB */ + 0x099, /* 3, -10.5dB */ + 0x0A2, /* 4, -10.0dB */ + 0x0AC, /* 5, -9.5dB */ + 0x0B6, /* 6, -9.0dB */ + 0x0C0, /* 7, -8.5dB */ + 0x0CC, /* 8, -8.0dB */ + 0x0D8, /* 9, -7.5dB */ + 0x0E5, /* 10, -7.0dB */ + 0x0F2, /* 11, -6.5dB */ + 0x101, /* 12, -6.0dB */ + 0x110, /* 13, -5.5dB */ + 0x120, /* 14, -5.0dB */ + 0x131, /* 15, -4.5dB */ + 0x143, /* 16, -4.0dB */ + 0x156, /* 17, -3.5dB */ + 0x16A, /* 18, -3.0dB */ + 0x180, /* 19, -2.5dB */ + 0x197, /* 20, -2.0dB */ + 0x1AF, /* 21, -1.5dB */ + 0x1C8, /* 22, -1.0dB */ + 0x1E3, /* 23, -0.5dB */ + 0x200, /* 24, +0 dB */ + 0x21E, /* 25, +0.5dB */ + 0x23E, /* 26, +1.0dB */ + 0x261, /* 27, +1.5dB */ + 0x285, /* 28, +2.0dB */ + 0x2AB, /* 29, +2.5dB */ + 0x2D3, /* 30, +3.0dB */ + 0x2FE, /* 31, +3.5dB */ + 0x32B, /* 32, +4.0dB */ + 0x35C, /* 33, +4.5dB */ + 0x38E, /* 34, +5.0dB */ + 0x3C4, /* 35, +5.5dB */ + 0x3FE /* 36, +6.0dB */ +}; + +void +odm_txpowertracking_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B))) + return; +#endif + + odm_txpowertracking_thermal_meter_init(dm); +} + +u8 +get_swing_index( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + u8 i = 0; + u32 bb_swing, table_value; + + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B || + dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || + dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || + dm->support_ic_type == ODM_RTL8192F || dm->support_ic_type == ODM_RTL8710B || + dm->support_ic_type == ODM_RTL8821) { + bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000); + + for (i = 0; i < OFDM_TABLE_SIZE; i++) { + table_value = ofdm_swing_table_new[i]; + + if (table_value >= 0x100000) + table_value >>= 22; + if (bb_swing == table_value) + break; + } + } else { + bb_swing = PHY_GetTxBBSwing_8812A(adapter, hal_data->CurrentBandType, RF_PATH_A); + + for (i = 0; i < TXSCALE_TABLE_SIZE; i++) { + table_value = tx_scaling_table_jaguar[i]; + + if (bb_swing == table_value) + break; + } + } + + return i; +} + +u8 +get_cck_swing_index( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + u8 i = 0; + u32 bb_cck_swing; + + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B || + dm->support_ic_type == ODM_RTL8192E) { + bb_cck_swing = odm_read_1byte(dm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0]) + break; + } + } else if (dm->support_ic_type == ODM_RTL8703B) { + bb_cck_swing = odm_read_1byte(dm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0]) + break; + } + } + + return i; +} + + +void +odm_txpowertracking_thermal_meter_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 default_swing_index = get_swing_index(dm); + u8 default_cck_swing_index = get_cck_swing_index(dm); + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + u8 p = 0; + + if (*(dm->mp_mode) == false) + cali_info->txpowertrack_control = true; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#ifdef CONFIG_RTL8188E + { + cali_info->is_txpowertracking = true; + cali_info->tx_powercount = 0; + cali_info->is_txpowertracking_init = false; + + if (*(dm->mp_mode) == false) + cali_info->txpowertrack_control = true; + + MSG_8192C("dm txpowertrack_control = %d\n", cali_info->txpowertrack_control); + } +#else + { + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_priv *pdmpriv = &hal_data->dmpriv; + + pdmpriv->is_txpowertracking = true; + pdmpriv->tx_powercount = 0; + pdmpriv->is_txpowertracking_init = false; + + if (*(dm->mp_mode) == false) + pdmpriv->txpowertrack_control = true; + + MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control); + + } +#endif +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#ifdef RTL8188E_SUPPORT + { + cali_info->is_txpowertracking = true; + cali_info->tx_powercount = 0; + cali_info->is_txpowertracking_init = false; + cali_info->txpowertrack_control = true; + } +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if (MP_DRIVER == 1) + cali_info->txpowertrack_control = false; +#else + cali_info->txpowertrack_control = true; +#endif +#else + cali_info->txpowertrack_control = true; +#endif + + cali_info->thermal_value = hal_data->eeprom_thermal_meter; + cali_info->thermal_value_iqk = hal_data->eeprom_thermal_meter; + cali_info->thermal_value_lck = hal_data->eeprom_thermal_meter; + + if (cali_info->default_bb_swing_index_flag != true) { + /*The index of "0 dB" in SwingTable.*/ + if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B || + dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B || + dm->support_ic_type == ODM_RTL8821) { + cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index; + cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index; + } else if (dm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 20; /*CCK:-6dB*/ + } else if (dm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 28; /*CCK: -6dB*/ + /* JJ ADD 20161014 */ + } else if (dm->support_ic_type == ODM_RTL8710B) { + cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + cali_info->default_cck_index = 28; /*CCK: -6dB*/ + /*Winnita add 20170828*/ + } else if (dm->support_ic_type == ODM_RTL8192F) { + cali_info->default_ofdm_index = 30; /*OFDM: 0dB*/ + cali_info->default_cck_index = 28; /*CCK: -6dB*/ + } else { + cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index; + cali_info->default_cck_index = 24; + } + cali_info->default_bb_swing_index_flag = true; + } + + cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index; + cali_info->CCK_index = cali_info->default_cck_index; + + for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) { + cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index; + cali_info->OFDM_index[p] = cali_info->default_ofdm_index; + cali_info->delta_power_index[p] = 0; + cali_info->delta_power_index_last[p] = 0; + cali_info->power_index_offset[p] = 0; + cali_info->kfree_offset[p] = 0; + } + cali_info->modify_tx_agc_value_ofdm = 0; + cali_info->modify_tx_agc_value_cck = 0; + cali_info->tm_trigger = 0; +} + + +void +odm_txpowertracking_check( + void *dm_void +) +{ + +#if 0 + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ +#endif + + struct dm_struct *dm = (struct dm_struct *)dm_void; + switch (dm->support_platform) { + case ODM_WIN: + odm_txpowertracking_check_mp(dm); + break; + + case ODM_CE: + odm_txpowertracking_check_ce(dm); + break; + + case ODM_AP: + odm_txpowertracking_check_ap(dm); + break; + + default: + break; + } + +} + +void +odm_txpowertracking_check_ce( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &(dm->rf_table); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + void *adapter = dm->adapter; +#if ((RTL8188F_SUPPORT == 1)) + rtl8192c_odm_check_txpowertracking(adapter); +#endif + +#if (RTL8188E_SUPPORT == 1) + + if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) + return; + + if (!cali_info->tm_trigger) { + odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); + /*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/ + + cali_info->tm_trigger = 1; + return; + + } else { + /*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/ + odm_txpowertracking_callback_thermal_meter_8188e(adapter); + cali_info->tm_trigger = 0; + } +#endif +#endif +} + +void +odm_txpowertracking_check_mp( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + + if (*dm->is_fcs_mode_enable) + return; + + if (odm_check_power_status(dm) == false) { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status return false\n")); + return; + } + + if (IS_HARDWARE_TYPE_8821B(adapter)) /* TODO: Don't Do PowerTracking*/ + return; + + odm_txpowertracking_thermal_meter_check(adapter); + + +#endif + +} + + +void +odm_txpowertracking_check_ap( + void *dm_void +) +{ + return; + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void +odm_txpowertracking_direct_call( + void *adapter +) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + odm_txpowertracking_callback_thermal_meter(adapter); +} + +void +odm_txpowertracking_thermal_meter_check( + void *adapter +) +{ + static u8 tm_trigger = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &(pHalData->DM_OutSrc); + struct _hal_rf_ *rf = &(dm->rf_table); + + if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, + ("===>odm_txpowertracking_thermal_meter_check(),mgnt_info->is_txpowertracking is false, return!!\n")); + return; + } + + if (!tm_trigger) { + if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) || IS_HARDWARE_TYPE_8192F(adapter) + ||IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter) + || IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter))/* JJ ADD 20161014 */ + PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03); + else + PHY_SetRFReg(adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60); + + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n")); + + tm_trigger = 1; + return; + } else { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n")); + odm_txpowertracking_direct_call(adapter); + tm_trigger = 0; + } +} + +#endif diff --git a/hal/phydm/halrf/halrf_powertracking_win.h b/hal/phydm/halrf/halrf_powertracking_win.h new file mode 100644 index 0000000..3ecdc1d --- /dev/null +++ b/hal/phydm/halrf/halrf_powertracking_win.h @@ -0,0 +1,302 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __HALRF_POWERTRACKING_H__ +#define __HALRF_POWERTRACKING_H__ + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define TXSCALE_TABLE_SIZE 37 +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_8723D 41 +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 3 +#define MAX_RF_PATH 4 +#define CCK_TABLE_SIZE_88F 21 +/* JJ ADD 20161014 */ +#define CCK_TABLE_SIZE_8710B 41 +#define CCK_TABLE_SIZE_8192F 41 + + +#define dm_check_txpowertracking odm_txpowertracking_check + +#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ +#define AVG_THERMAL_NUM 8 +#define iqk_matrix_reg_num 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 + +#define IQK_BB_REG_NUM 9 + + +extern u32 ofdm_swing_table[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8]; + +extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D]; +/* JJ ADD 20161014 */ +extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B]; +extern u32 cck_swing_table_ch1_ch14_8192f[CCK_TABLE_SIZE_8192F]; + +extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE]; + +/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */ +static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +void +odm_txpowertracking_check( + void *dm_void +); + +void +odm_txpowertracking_check_ap( + void *dm_void +); + +void +odm_txpowertracking_thermal_meter_init( + void *dm_void +); + +void +odm_txpowertracking_init( + void *dm_void +); + +void +odm_txpowertracking_check_mp( + void *dm_void +); + + +void +odm_txpowertracking_check_ce( + void *dm_void +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + +void +odm_txpowertracking_thermal_meter_check( + void *adapter +); + +#endif + +struct iqk_matrix_regs_setting { + boolean is_iqk_done; + s32 value[3][iqk_matrix_reg_num]; + boolean is_bw_iqk_result_saved[3]; +}; + +struct dm_rf_calibration_struct { + /* for tx power tracking */ + + u32 rega24; /* for TempCCK */ + s32 rege94; + s32 rege9c; + s32 regeb4; + s32 regebc; + /* u8 is_txpowertracking; */ + u8 tx_powercount; + boolean is_txpowertracking_init; + boolean is_txpowertracking; + u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */ + u8 tm_trigger; + u8 internal_pa_5g[2]; /* pathA / pathB */ + + u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ + u8 thermal_value; + u8 thermal_value_lck; + u8 thermal_value_iqk; + u8 thermal_value_dpk; + s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ + u8 thermal_value_avg[AVG_THERMAL_NUM]; + u8 thermal_value_avg_index; + u8 thermal_value_rx_gain; + + + boolean is_reloadtxpowerindex; + u8 is_rf_pi_enable; + u32 txpowertracking_callback_cnt; /* cosa add for debug */ + + + /* ------------------------- Tx power Tracking ------------------------- */ + u8 is_cck_in_ch14; + u8 CCK_index; + u8 OFDM_index[MAX_RF_PATH]; + s8 power_index_offset[MAX_RF_PATH]; + s8 delta_power_index[MAX_RF_PATH]; + s8 delta_power_index_last[MAX_RF_PATH]; + boolean is_tx_power_changed; + s8 xtal_offset; + s8 xtal_offset_last; + + struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + u8 delta_lck; + s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */ + u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; + + u8 bb_swing_idx_ofdm[MAX_RF_PATH]; + u8 bb_swing_idx_ofdm_current; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + u8 bb_swing_idx_ofdm_base[MAX_RF_PATH]; +#else + u8 bb_swing_idx_ofdm_base; +#endif + boolean default_bb_swing_index_flag; + boolean bb_swing_flag_ofdm; + u8 bb_swing_idx_cck; + u8 bb_swing_idx_cck_current; + u8 bb_swing_idx_cck_base; + u8 default_ofdm_index; + u8 default_cck_index; + boolean bb_swing_flag_cck; + + s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; + s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; + s8 absolute_cck_swing_idx[MAX_RF_PATH]; + s8 remnant_cck_swing_idx; + s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ + boolean modify_tx_agc_flag_path_a; + boolean modify_tx_agc_flag_path_b; + boolean modify_tx_agc_flag_path_c; + boolean modify_tx_agc_flag_path_d; + boolean modify_tx_agc_flag_path_a_cck; + boolean modify_tx_agc_flag_path_b_cck; + + s8 kfree_offset[MAX_RF_PATH]; + + /* -------------------------------------------------------------------- */ + + /* for IQK */ + u32 regc04; + u32 reg874; + u32 regc08; + u32 regb68; + u32 regb6c; + u32 reg870; + u32 reg860; + u32 reg864; + + boolean is_iqk_initialized; + boolean is_lck_in_progress; + boolean is_antenna_detected; + boolean is_need_iqk; + boolean is_iqk_in_progress; + boolean is_iqk_pa_off; + u8 delta_iqk; + u32 ADDA_backup[IQK_ADDA_REG_NUM]; + u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; + u32 IQK_BB_backup_recover[9]; + u32 IQK_BB_backup[IQK_BB_REG_NUM]; + u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + /* JJ ADD 20161014 */ + u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + u64 iqk_start_time; + u64 iqk_total_progressing_time; + u64 iqk_progressing_time; + u64 lck_progressing_time; + u32 lok_result; + u8 iqk_step; + u8 kcount; + u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + boolean is_mp_mode; + + /* for APK */ + u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */ + u8 is_ap_kdone; + u8 is_apk_thermal_meter_ignore; + + /* DPK */ + boolean is_dpk_fail; + u8 is_dp_done; + u8 is_dp_path_aok; + u8 is_dp_path_bok; + + u32 tx_lok[2]; + u32 dpk_tx_agc; + s32 dpk_gain; + u32 dpk_thermal[4]; + + s8 modify_tx_agc_value_ofdm; + s8 modify_tx_agc_value_cck; + + /*Add by Yuchen for Kfree Phydm*/ + u8 reg_rf_kfree_enable; /*for registry*/ + u8 rf_kfree_enable; /*for efuse enable check*/ +}; + + + + +#endif /*#ifndef __HALRF_POWER_TRACKING_H__*/ diff --git a/hal/phydm/halrf/halrf_psd.c b/hal/phydm/halrf/halrf_psd.c new file mode 100644 index 0000000..ef78918 --- /dev/null +++ b/hal/phydm/halrf/halrf_psd.c @@ -0,0 +1,301 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/*============================================================ + * include files + *============================================================ + */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#if 0 +u32 _sqrt(u64 n) +{ + u64 ans = 0, q = 0; + s64 i; + + /*for (i = sizeof(n) * 8 - 2; i > -1; i = i - 2) {*/ + for (i = 8 * 8 - 2; i > -1; i = i - 2) { + q = (q << 2) | ((n & (3 << i)) >> i); + if (q >= ((ans << 2) | 1)) + { + q = q - ((ans << 2) | 1); + ans = (ans << 1) | 1; + } + else + ans = ans << 1; + } + DbgPrint("ans=0x%x\n", ans); + + return (u32)ans; +} +#endif + +u64 _sqrt(u64 x) +{ + u64 i = 0; + u64 j = x / 2 + 1; + + while (i <= j) { + u64 mid = (i + j) / 2; + + u64 sq = mid * mid; + + if (sq == x) + return mid; + else if (sq < x) + i = mid + 1; + else + j = mid - 1; + } + + return j; +} + +u32 halrf_get_psd_data( + struct dm_struct *dm, + u32 point) +{ + struct _hal_rf_ *rf = &(dm->rf_table); + struct _halrf_psd_data *psd = &(rf->halrf_psd_data); + u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time; + +#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE) + if (psd->average == 0) + delay_time = 100; + else + delay_time = 0; +#else + if (psd->average == 0) + delay_time = 1000; + else + delay_time = 100; +#endif + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) { + psd_reg = R_0x910; + psd_report = R_0xf44; + } else { + psd_reg = R_0x808; + psd_report = R_0x8b4; + } + + if (dm->support_ic_type & ODM_RTL8710B) { + psd_point = 0xeffffc00; + psd_start = 0x10000000; + } else { + psd_point = 0xffbffc00; + psd_start = 0x00400000; + } + + psd_val = odm_get_bb_reg(dm, psd_reg, MASKDWORD); + + psd_val &= psd_point; + psd_val |= point; + + odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val); + + psd_val |= psd_start; + + odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val); + + for (i = 0; i < delay_time; i++) + ODM_delay_us(1); + + psd_val = odm_get_bb_reg(dm, psd_report, MASKDWORD); + + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8710B)) { + psd_val &= MASKL3BYTES; + psd_val = psd_val / 32; + } else { + psd_val &= MASKLWORD; + } + + return psd_val; +} + +void halrf_psd( + struct dm_struct *dm, + u32 point, + u32 start_point, + u32 stop_point, + u32 average) +{ + struct _hal_rf_ *rf = &(dm->rf_table); + struct _halrf_psd_data *psd = &(rf->halrf_psd_data); + + u32 i = 0, j = 0, k = 0; + u32 psd_reg, avg_org, point_temp, average_tmp; + u64 data_tatal = 0, data_temp[64] = {0}; + + psd->buf_size = 256; + + if (average == 0) + average_tmp = 1; + else + average_tmp = average; + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) + psd_reg = R_0x910; + else + psd_reg = R_0x808; + +#if 0 + dbg_print("[PSD]point=%d, start_point=%d, stop_point=%d, average=%d, average_tmp=%d, buf_size=%d\n", + point, start_point, stop_point, average, average_tmp, psd->buf_size); +#endif + + for (i = 0; i < psd->buf_size; i++) + psd->psd_data[i] = 0; + + if (dm->support_ic_type & ODM_RTL8710B) + avg_org = odm_get_bb_reg(dm, psd_reg, 0x30000); + else + avg_org = odm_get_bb_reg(dm, psd_reg, 0x3000); + + if (average != 0) { + if (dm->support_ic_type & ODM_RTL8710B) + odm_set_bb_reg(dm, psd_reg, 0x30000, 0x1); + else + odm_set_bb_reg(dm, psd_reg, 0x3000, 0x1); + } + +#if 0 + if (avg_temp == 0) + avg = 1; + else if (avg_temp == 1) + avg = 8; + else if (avg_temp == 2) + avg = 16; + else if (avg_temp == 3) + avg = 32; +#endif + + i = start_point; + while (i < stop_point) { + data_tatal = 0; + + if (i >= point) + point_temp = i - point; + else + point_temp = i; + + for (k = 0; k < average_tmp; k++) { + data_temp[k] = halrf_get_psd_data(dm, point_temp); + data_tatal = data_tatal + (data_temp[k] * data_temp[k]); + +#if 0 + if ((k % 20) == 0) + dbg_print("\n "); + + dbg_print("0x%x ", data_temp[k]); +#endif + } + /*dbg_print("\n");*/ + + data_tatal = ((data_tatal * 100) / average_tmp); + psd->psd_data[j] = (u32)_sqrt(data_tatal); + + i++; + j++; + } + +#if 0 + for (i = 0; i < psd->buf_size; i++) { + if ((i % 20) == 0) + dbg_print("\n "); + + dbg_print("0x%x ", psd->psd_data[i]); + } + dbg_print("\n\n"); +#endif + + if (dm->support_ic_type & ODM_RTL8710B) + odm_set_bb_reg(dm, psd_reg, 0x30000, avg_org); + else + odm_set_bb_reg(dm, psd_reg, 0x3000, avg_org); +} + +enum rt_status +halrf_psd_init( + struct dm_struct *dm) +{ + enum rt_status ret_status = RT_STATUS_SUCCESS; + struct _hal_rf_ *rf = &(dm->rf_table); + struct _halrf_psd_data *psd = &(rf->halrf_psd_data); + + if (psd->psd_progress) { + ret_status = RT_STATUS_PENDING; + } else { + psd->psd_progress = 1; + halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average); + psd->psd_progress = 0; + } + + return ret_status; +} + +enum rt_status +halrf_psd_query( + struct dm_struct *dm, + u32 *outbuf, + u32 buf_size) +{ + enum rt_status ret_status = RT_STATUS_SUCCESS; + struct _hal_rf_ *rf = &(dm->rf_table); + struct _halrf_psd_data *psd = &(rf->halrf_psd_data); + + if (psd->psd_progress) + ret_status = RT_STATUS_PENDING; + else + PlatformMoveMemory(outbuf, psd->psd_data, 0x400); + + return ret_status; +} + +enum rt_status +halrf_psd_init_query( + struct dm_struct *dm, + u32 *outbuf, + u32 point, + u32 start_point, + u32 stop_point, + u32 average, + u32 buf_size) +{ + enum rt_status ret_status = RT_STATUS_SUCCESS; + struct _hal_rf_ *rf = &(dm->rf_table); + struct _halrf_psd_data *psd = &(rf->halrf_psd_data); + + psd->point = point; + psd->start_point = start_point; + psd->stop_point = stop_point; + psd->average = average; + + if (psd->psd_progress) { + ret_status = RT_STATUS_PENDING; + } else { + psd->psd_progress = 1; + halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average); + PlatformMoveMemory(outbuf, psd->psd_data, 0x400); + psd->psd_progress = 0; + } + + return ret_status; +} + +#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/ diff --git a/hal/phydm/halrf/halrf_psd.h b/hal/phydm/halrf/halrf_psd.h new file mode 100644 index 0000000..6288afd --- /dev/null +++ b/hal/phydm/halrf/halrf_psd.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __HALRF_PSD_H__ +#define __HALRF_PSD_H__ + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + +struct _halrf_psd_data { + u32 point; + u32 start_point; + u32 stop_point; + u32 average; + u32 buf_size; + u32 psd_data[256]; + u32 psd_progress; +}; + +enum rt_status +halrf_psd_init( + struct dm_struct *dm); + +enum rt_status +halrf_psd_query( + struct dm_struct *dm, + u32 *outbuf, + u32 buf_size); + +enum rt_status +halrf_psd_init_query( + struct dm_struct *dm, + u32 *outbuf, + u32 point, + u32 start_point, + u32 stop_point, + u32 average, + u32 buf_size); + +#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/ +#endif /*#ifndef __HALRF_PSD_H__*/ diff --git a/hal/phydm/halrf/halrf_txgapcal.c b/hal/phydm/halrf/halrf_txgapcal.c new file mode 100644 index 0000000..310be54 --- /dev/null +++ b/hal/phydm/halrf/halrf_txgapcal.c @@ -0,0 +1,298 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void odm_bub_sort(u32 *data, u32 n) +{ + int i, j, temp, sp; + + for (i = n - 1; i >= 0; i--) { + sp = 1; + for (j = 0; j < i; j++) { + if (data[j] < data[j + 1]) { + temp = data[j]; + data[j] = data[j + 1]; + data[j + 1] = temp; + sp = 0; + } + } + if (sp == 1) + break; + } +} + +#if (RTL8197F_SUPPORT == 1) + +u4Byte +odm_tx_gain_gap_psd_8197f( + void *dm_void, + u1Byte rf_path, + u4Byte rf56) +{ + PDM_ODM_T dm = (PDM_ODM_T)dm_void; + + u1Byte i, j; + u4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp; + + u4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c}, + {0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}}; + + u4Byte psd_finish_bit[2] = {0x04000000, 0x20000000}; + u4Byte psd_fail_bit[2] = {0x08000000, 0x40000000}; + + u4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c}, + {0x38008c2c, 0x10008c2c}}; + + u4Byte psd_report_addr[2] = {0xea0, 0xec0}; + + odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00e02); + + ODM_delay_us(100); + + odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x0); + + odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56); + while (rf56 != (odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff))) + odm_set_rf_reg(dm, rf_path, RF_0x56, 0xfff, rf56); + + odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44FFBB44); + odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x00400040); + odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005403); + odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000804e4); + odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04203400); + odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x80800000); + + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]); + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]); + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]); + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]); + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F); + odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F); + + odm_set_bb_reg(dm, R_0xe40, 0xffffffff, 0x81007C00); + odm_set_bb_reg(dm, R_0xe44, 0xffffffff, 0x81004800); + odm_set_bb_reg(dm, R_0xe4c, 0xffffffff, 0x0046a8d0); + + for (i = 0; i < psd_avg_time; i++) { + for (j = 0; j < 1000; j++) { + odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xfa005800); + odm_set_bb_reg(dm, R_0xe48, 0xffffffff, 0xf8005800); + + while (!odm_get_bb_reg(dm, R_0xeac, psd_finish_bit[rf_path])) + ; /*wait finish bit*/ + + if (!odm_get_bb_reg(dm, R_0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/ + + psd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff); + + if (psd_vaule[i] > 0xffff) + break; + } + } + + RF_DBG(dm, DBG_RF_IQK, + "[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\n", + odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56, + odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), j, + psd_vaule[i]); + } + + odm_bub_sort(psd_vaule, psd_avg_time); + + psd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)]; + + odm_set_bb_reg(dm, R_0xd94, 0xffffffff, 0x44BBBB44); + odm_set_bb_reg(dm, R_0xe70, 0xffffffff, 0x80408040); + odm_set_bb_reg(dm, R_0xc04, 0xffffffff, 0x6f005433); + odm_set_bb_reg(dm, R_0xc08, 0xffffffff, 0x000004e4); + odm_set_bb_reg(dm, R_0x874, 0xffffffff, 0x04003400); + odm_set_bb_reg(dm, R_0xe28, 0xffffffff, 0x00000000); + + RF_DBG(dm, DBG_RF_IQK, + "[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\n", + odm_get_rf_reg(dm, rf_path, RF_0x0, 0xff), rf56, + odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff), psd_vaule_temp); + + odm_set_rf_reg(dm, rf_path, RF_0xdf, bRFRegOffsetMask, 0x00602); + + return psd_vaule_temp; +} + +void odm_tx_gain_gap_calibration_8197f( + void *dm_void) +{ + PDM_ODM_T dm = (PDM_ODM_T)dm_void; + + u1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3; + + s1Byte delta_gain_gap_pre, delta_gain_gap[2][11]; + u4Byte rf56_current, rf56_next, psd_value_current, psd_value_next; + u4Byte psd_gap, rf56_current_temp[2][11]; + s4Byte rf33[2][11]; + + memset(rf33, 0x0, sizeof(rf33)); + + for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) { + if (rf_path == RF_PATH_A) + odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/ + else if (rf_path == RF_PATH_B) + odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/ + + ODM_delay_us(100); + + for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) { + rf0_idx_current = 3 * (rf0_idx - 1) + 1; + odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_current); + ODM_delay_us(100); + rf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff); + rf56_current = rf56_current_temp[rf_path][rf0_idx]; + + rf0_idx_next = 3 * rf0_idx + 1; + odm_set_rf_reg(dm, rf_path, RF_0x0, 0xff, rf0_idx_next); + ODM_delay_us(100); + rf56_next = odm_get_rf_reg(dm, rf_path, RF_0x56, 0xfff); + + RF_DBG(dm, DBG_RF_IQK, + "[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\n", + rf_path, rf0_idx, rf56_current, rf_path, rf0_idx, + rf56_next); + + if ((rf56_current >> 5) == (rf56_next >> 5)) { + delta_gain_gap[rf_path][rf0_idx] = 0; + + RF_DBG(dm, DBG_RF_IQK, + "[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\n", + rf_path, rf0_idx, (rf56_next >> 5), + rf_path, rf0_idx, + delta_gain_gap[rf_path][rf0_idx]); + + continue; + } + + RF_DBG(dm, DBG_RF_IQK, + "[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\n", + rf_path, rf0_idx, (rf56_current >> 5), rf_path, + rf0_idx, (rf56_next >> 5)); + + for (i = 0; i < delta_gain_retry; i++) { + psd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current); + + psd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2); + + psd_gap = psd_value_next / (psd_value_current / 1000); + +#if 0 + if (psd_gap > 1413) + delta_gain_gap[rf_path][rf0_idx] = 1; + else if (psd_gap > 1122) + delta_gain_gap[rf_path][rf0_idx] = 0; + else + delta_gain_gap[rf_path][rf0_idx] = -1; +#endif + + if (psd_gap > 1445) + delta_gain_gap[rf_path][rf0_idx] = 1; + else if (psd_gap > 1096) + delta_gain_gap[rf_path][rf0_idx] = 0; + else + delta_gain_gap[rf_path][rf0_idx] = -1; + + if (i == 0) + delta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx]; + + RF_DBG(dm, DBG_RF_IQK, + "[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\n", + psd_value_current, psd_value_next, + psd_gap, rf_path, rf0_idx, + delta_gain_gap[rf_path][rf0_idx]); + + if (i == 0 && delta_gain_gap[rf_path][rf0_idx] == 0) + break; + + if (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) { + delta_gain_gap[rf_path][rf0_idx] = 0; + + RF_DBG(dm, DBG_RF_IQK, "[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\n", + delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i); + + break; + } + + RF_DBG(dm, DBG_RF_IQK, + "[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\n", + delta_gain_gap_pre, rf_path, rf0_idx, + delta_gain_gap[rf_path][rf0_idx], i); + } + } + + if (rf_path == RF_PATH_A) + odm_set_bb_reg(dm, R_0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/ + else if (rf_path == RF_PATH_B) + odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/ + + ODM_delay_us(100); + } + + /*odm_set_bb_reg(dm, R_0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/ + + for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) { + odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00100); + + for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) { + rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f); + + for (i = rf0_idx; i <= 10; i++) + rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i]; + + if (rf33[rf_path][rf0_idx] >= 0x1d) + rf33[rf_path][rf0_idx] = 0x1d; + else if (rf33[rf_path][rf0_idx] <= 0x2) + rf33[rf_path][rf0_idx] = 0x2; + + rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0); + + RF_DBG(dm, DBG_RF_IQK, + "[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\n", + rf_path, rf0_idx, + rf56_current_temp[rf_path][rf0_idx], rf_path, + rf0_idx, rf33[rf_path][rf0_idx]); + + odm_set_rf_reg(dm, rf_path, RF_0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]); + } + + odm_set_rf_reg(dm, rf_path, RF_0xef, bRFRegOffsetMask, 0x00000); + } +} +#endif + +void odm_tx_gain_gap_calibration(void *dm_void) +{ + PDM_ODM_T dm = (PDM_ODM_T)dm_void; +#if (RTL8197F_SUPPORT == 1) + if (dm->SupportICType & ODM_RTL8197F) + odm_tx_gain_gap_calibration_8197f(dm_void); +#endif +} diff --git a/hal/phydm/halrf/halrf_txgapcal.h b/hal/phydm/halrf/halrf_txgapcal.h new file mode 100644 index 0000000..c2c5c35 --- /dev/null +++ b/hal/phydm/halrf/halrf_txgapcal.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALRF_TXGAPCAL_H__ +#define __HALRF_TXGAPCAL_H__ + +void odm_tx_gain_gap_calibration(void *dm_void); + +#endif /*#ifndef __HALRF_TXGAPCAL_H__*/ diff --git a/hal/phydm/halrf/rtl8821c/halrf_8821c.c b/hal/phydm/halrf/rtl8821c/halrf_8821c.c new file mode 100644 index 0000000..f72edf3 --- /dev/null +++ b/hal/phydm/halrf/rtl8821c/halrf_8821c.c @@ -0,0 +1,469 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include "mp_precomp.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if RT_PLATFORM == PLATFORM_MACOSX +#include "phydm_precomp.h" +#else +#include "../phydm_precomp.h" +#endif +#else +#include "../../phydm_precomp.h" +#endif + +#if (RTL8821C_SUPPORT == 1) +void halrf_rf_lna_setting_8821c(struct dm_struct *dm_void, + enum halrf_lna_set type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 path = 0x0; + + if (type == HALRF_LNA_DISABLE) { + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x0afce); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x0280d); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x0); + } else if (type == HALRF_LNA_ENABLE) { + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x1afce); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00003); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00064); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x0281d); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, BIT(12), 0x0); + } +} + +boolean +get_mix_mode_tx_agc_bbs_wing_offset_8821c(void *dm_void, + enum pwrtrack_method method, + u8 rf_path, + u8 tx_power_index_offest_upper_bound, + s8 tx_power_index_offest_lower_bound) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10; + u8 bb_swing_lower_bound = 0; + + s8 tx_agc_index = 0; + u8 tx_bb_swing_index = cali_info->default_ofdm_index; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "Path_%d pRF->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest_upper_bound=%d, tx_power_index_offest_lower_bound=%d\n", + rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], + tx_power_index_offest_upper_bound, + tx_power_index_offest_lower_bound); + + if (tx_power_index_offest_upper_bound > 0XF) + tx_power_index_offest_upper_bound = 0XF; + + if (tx_power_index_offest_lower_bound < -15) + tx_power_index_offest_lower_bound = -15; + + if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && cali_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest_upper_bound) { + tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path]; + tx_bb_swing_index = cali_info->default_ofdm_index; + } else if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && (cali_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest_upper_bound)) { + tx_agc_index = tx_power_index_offest_upper_bound; + cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest_upper_bound; + tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path]; + + if (tx_bb_swing_index > bb_swing_upper_bound) + tx_bb_swing_index = bb_swing_upper_bound; + } else if (cali_info->absolute_ofdm_swing_idx[rf_path] < 0 && (cali_info->absolute_ofdm_swing_idx[rf_path] >= tx_power_index_offest_lower_bound)) { + tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path]; + tx_bb_swing_index = cali_info->default_ofdm_index; + } else if (cali_info->absolute_ofdm_swing_idx[rf_path] < 0 && (cali_info->absolute_ofdm_swing_idx[rf_path] < tx_power_index_offest_lower_bound)) { + tx_agc_index = tx_power_index_offest_lower_bound; + cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest_lower_bound; + + if (cali_info->default_ofdm_index > (cali_info->remnant_ofdm_swing_idx[rf_path] * (-1))) + tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path]; + else + tx_bb_swing_index = bb_swing_lower_bound; + } + + cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index; + cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "MixMode Offset Path_%d pRF->absolute_ofdm_swing_idx[rf_path]=%d pRF->bb_swing_idx_ofdm[rf_path]=%d TxPwrIdxOffestUpper=%d TxPwrIdxOffestLower=%d\n", + rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], + cali_info->bb_swing_idx_ofdm[rf_path], + tx_power_index_offest_upper_bound, + tx_power_index_offest_lower_bound); + + return true; +} + +void odm_tx_pwr_track_set_pwr8821c(void *dm_void, enum pwrtrack_method method, + u8 rf_path, u8 channel_mapped_index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct _ADAPTER *adapter = dm->adapter; + u8 channel = *dm->channel; + u8 band_width = *dm->band_width; +#endif + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + struct _hal_rf_ *rf = &dm->rf_table; + u8 tx_power_index_offest_upper_bound = 0; + s8 tx_power_index_offest_lower_bound = 0; + u8 tx_power_index = 0; + u8 tx_rate = 0xFF; + + if (*dm->mp_mode) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx; + + tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#ifdef CONFIG_MP_INCLUDED + PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx); + + tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index); +#endif +#endif +#endif + } else { + u16 rate = *dm->forced_data_rate; + + if (!rate) { /*auto rate*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + tx_rate = dm->tx_rate; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (dm->number_linked_client != 0) + tx_rate = hw_rate_to_m_rate(dm->tx_rate); + else + tx_rate = rf->p_rate_index; +#endif + } else { /*force rate*/ + tx_rate = (u8)rate; + } + } + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, + tx_rate); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n", + cali_info->default_ofdm_index, cali_info->default_cck_index); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n", + cali_info->absolute_ofdm_swing_idx[rf_path], + cali_info->remnant_ofdm_swing_idx[rf_path], + cali_info->absolute_cck_swing_idx[rf_path], + cali_info->remnant_cck_swing_idx, rf_path); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + tx_power_index = odm_get_tx_power_index(dm, (enum rf_path)rf_path, tx_rate, band_width, channel); +#else + tx_power_index = config_phydm_read_txagc_8821c(dm, rf_path, 0x04); /*0x04(TX_AGC_OFDM_6M)*/ +#endif + + if (tx_power_index >= 63) + tx_power_index = 63; + + tx_power_index_offest_upper_bound = 63 - tx_power_index; + + tx_power_index_offest_lower_bound = 0 - tx_power_index; + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "tx_power_index=%d tx_power_index_offest_upper_bound=%d tx_power_index_offest_lower_bound=%d rf_path=%d\n", + tx_power_index, tx_power_index_offest_upper_bound, + tx_power_index_offest_lower_bound, rf_path); + + if (method == BBSWING) { /*use for mp driver clean power tracking status*/ + switch (rf_path) { + case RF_PATH_A: + odm_set_bb_reg(dm, R_0xc94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)), ((cali_info->absolute_ofdm_swing_idx[rf_path]) & 0x3f)); + odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); + break; + + default: + break; + } + + } else if (method == MIX_MODE) { + switch (rf_path) { + case RF_PATH_A: + get_mix_mode_tx_agc_bbs_wing_offset_8821c(dm, method, rf_path, tx_power_index_offest_upper_bound, tx_power_index_offest_lower_bound); + odm_set_bb_reg(dm, R_0xc94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)), ((cali_info->absolute_ofdm_swing_idx[rf_path]) & 0x3f)); + odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]); + + RF_DBG(dm, DBG_RF_TX_PWR_TRACK, + "TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n", + odm_get_bb_reg(dm, R_0xc94, + (BIT(6) | BIT(5) | BIT(4) | + BIT(3) | BIT(2) | BIT(1))), + odm_get_bb_reg(dm, R_0xc1c, 0xFFE00000), + cali_info->bb_swing_idx_ofdm[rf_path], rf_path); + break; + + default: + break; + } + } +} + +void get_delta_swing_table_8821c(void *dm_void, +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + u8 **temperature_up_a, u8 **temperature_down_a, + u8 **temperature_up_b, u8 **temperature_down_b, + u8 **temperature_up_cck_a, + u8 **temperature_down_cck_a, + u8 **temperature_up_cck_b, + u8 **temperature_down_cck_b +#else + u8 **temperature_up_a, u8 **temperature_down_a, + u8 **temperature_up_b, + u8 **temperature_down_b +#endif + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + u8 channel = *(dm->channel); +#else + u8 channel = *dm->channel; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + *temperature_up_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_p; + *temperature_down_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_n; + *temperature_up_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_p; + *temperature_down_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_n; +#endif + + *temperature_up_a = cali_info->delta_swing_table_idx_2ga_p; + *temperature_down_a = cali_info->delta_swing_table_idx_2ga_n; + *temperature_up_b = cali_info->delta_swing_table_idx_2gb_p; + *temperature_down_b = cali_info->delta_swing_table_idx_2gb_n; + + if (channel >= 36 && channel <= 64) { + *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0]; + *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0]; + *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0]; + *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0]; + } else if (channel >= 100 && channel <= 144) { + *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1]; + *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1]; + *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1]; + *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1]; + } else if (channel >= 149 && channel <= 177) { + *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2]; + *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2]; + *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2]; + *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2]; + } +} + +void aac_check_8821c(struct dm_struct *dm) +{ + struct _hal_rf_ *rf = &dm->rf_table; + u32 temp; + + if (!rf->aac_checked) { + RF_DBG(dm, DBG_RF_LCK, "[LCK]AAC check for 8821c\n"); + temp = odm_get_rf_reg(dm, RF_PATH_A, 0xc9, 0xf8); + if (temp < 4 || temp > 7) { + odm_set_rf_reg(dm, RF_PATH_A, 0xca, BIT(19), 0x0); + odm_set_rf_reg(dm, RF_PATH_A, 0xb2, 0x7c000, 0x6); + } + rf->aac_checked = true; + } +} + +void _phy_aac_calibrate_8821c(struct dm_struct *dm) +{ + u32 cnt = 0; + + RF_DBG(dm, DBG_RF_IQK, "[AACK]AACK start!!!!!!!\n"); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xb8, RFREGOFFSETMASK, 0x80a00); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xb0, RFREGOFFSETMASK, 0xff0fa); + ODM_delay_ms(10); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xca, RFREGOFFSETMASK, 0x80000); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xc9, RFREGOFFSETMASK, 0x1c141); + for (cnt = 0; cnt < 100; cnt++) { + ODM_delay_ms(1); + if (odm_get_rf_reg(dm, RF_PATH_A, RF_0xca, 0x1000) != 0x1) + break; + } + + odm_set_rf_reg(dm, RF_PATH_A, RF_0xb0, RFREGOFFSETMASK, 0xff0f8); + + RF_DBG(dm, DBG_RF_IQK, "[AACK]AACK end!!!!!!!\n"); +} + +void _phy_lc_calibrate_8821c(struct dm_struct *dm) +{ +#if 1 + aac_check_8821c(dm); + RF_DBG(dm, DBG_RF_IQK, "[LCK]real-time LCK!!!!!!!\n"); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xcc, RFREGOFFSETMASK, 0x2018); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xc4, RFREGOFFSETMASK, 0x8f602); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xcc, RFREGOFFSETMASK, 0x201c); +#endif +#if 0 + u32 lc_cal = 0, cnt = 0, tmp0xc00; + /*RF to standby mode*/ + tmp0xc00 = odm_read_4byte(dm, 0xc00); + odm_write_4byte(dm, 0xc00, 0x4); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x10000); + + _phy_aac_calibrate_8821c(dm); + + /*backup RF0x18*/ + lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK); + /*Start LCK*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000); + ODM_delay_ms(50); + + for (cnt = 0; cnt < 100; cnt++) { + if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + break; + ODM_delay_ms(10); + } + + /*Recover channel number*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal); + /**restore*/ + odm_write_4byte(dm, 0xc00, tmp0xc00); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x3ffff); + RF_DBG(dm, DBG_RF_IQK, "[LCK]LCK end!!!!!!!\n"); +#endif +} + +/*LCK:0x2*/ +/*1. add AACK check*/ +void phy_lc_calibrate_8821c(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + _phy_lc_calibrate_8821c(dm); +} + +void configure_txpower_track_8821c(struct txpwrtrack_cfg *config) +{ + config->swing_table_size_cck = TXSCALE_TABLE_SIZE; + config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE; + config->threshold_iqk = IQK_THRESHOLD; + config->threshold_dpk = DPK_THRESHOLD; + config->average_thermal_num = AVG_THERMAL_NUM_8821C; + config->rf_path_count = MAX_PATH_NUM_8821C; + config->thermal_reg_addr = RF_T_METER_8821C; + + config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8821c; + config->do_iqk = do_iqk_8821c; + config->phy_lc_calibrate = phy_lc_calibrate_8821c; + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + config->get_delta_all_swing_table = get_delta_swing_table_8821c; +#else + config->get_delta_swing_table = get_delta_swing_table_8821c; +#endif +} + +#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE)) +void phy_set_rf_path_switch_8821c(struct dm_struct *dm, +#else +void phy_set_rf_path_switch_8821c(void *adapter, +#endif + boolean is_main) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; +#endif +#endif + u8 ant_num = 0; /*0: ANT_1, 1: ANT_2*/ + + if (is_main) + ant_num = SWITCH_TO_ANT1; /*Main = ANT_1*/ + else + ant_num = SWITCH_TO_ANT2; /*Aux = ANT_2*/ + + config_phydm_set_ant_path(dm, dm->current_rf_set_8821c, ant_num); +} + + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +boolean _phy_query_rf_path_switch_8821c(struct dm_struct *dm +#else +boolean _phy_query_rf_path_switch_8821c(void *adapter +#endif + ) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct dm_struct *dm = &hal_data->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct dm_struct *dm = &hal_data->DM_OutSrc; +#endif +#endif + u8 ant_num = 0; /*0: ANT_1, 1: ANT_2*/ + + ODM_delay_ms(300); + + ant_num = query_phydm_current_ant_num_8821c(dm); + + if (ant_num == SWITCH_TO_ANT1) + return true; /*Main = ANT_1*/ + else + return false; /*Aux = ANT_2*/ +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +boolean phy_query_rf_path_switch_8821c(struct dm_struct *dm +#else +boolean phy_query_rf_path_switch_8821c(void *adapter +#endif + ) +{ +#if DISABLE_BB_RF + return true; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + return _phy_query_rf_path_switch_8821c(dm); +#else + return _phy_query_rf_path_switch_8821c(adapter); +#endif +} + +#endif /* (RTL8821C_SUPPORT == 0)*/ diff --git a/hal/phydm/halrf/rtl8821c/halrf_8821c.h b/hal/phydm/halrf/rtl8821c/halrf_8821c.h new file mode 100644 index 0000000..9217959 --- /dev/null +++ b/hal/phydm/halrf/rtl8821c/halrf_8821c.h @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __HALRF_8821C_H__ +#define __HALRF_8821C_H__ + +#define AVG_THERMAL_NUM_8821C 4 +#define RF_T_METER_8821C 0x42 + +void configure_txpower_track_8821c(struct txpwrtrack_cfg *config); + +void odm_tx_pwr_track_set_pwr8821c(void *dm_void, enum pwrtrack_method method, + u8 rf_path, u8 channel_mapped_index); + +void get_delta_swing_table_8821c(void *dm_void, +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + u8 **temperature_up_a, u8 **temperature_down_a, + u8 **temperature_up_b, u8 **temperature_down_b, + u8 **temperature_up_cck_a, + u8 **temperature_down_cck_a, + u8 **temperature_up_cck_b, + u8 **temperature_down_cck_b +#else + u8 **temperature_up_a, u8 **temperature_down_a, + u8 **temperature_up_b, + u8 **temperature_down_b +#endif + ); + +void phy_lc_calibrate_8821c(void *dm_void); + +void halrf_rf_lna_setting_8821c(struct dm_struct *dm, enum halrf_lna_set type); + +#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE)) +void phy_set_rf_path_switch_8821c(struct dm_struct *dm, +#else +void phy_set_rf_path_switch_8821c(void *adapter, +#endif + boolean is_main); + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +boolean phy_query_rf_path_switch_8821c(struct dm_struct *dm +#else +boolean phy_query_rf_path_switch_8821c(void *adapter +#endif + ); + +#endif /*#ifndef __HALRF_8821C_H__*/ diff --git a/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.c b/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.c new file mode 100644 index 0000000..e018dbb --- /dev/null +++ b/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.c @@ -0,0 +1,3777 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include "mp_precomp.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if RT_PLATFORM == PLATFORM_MACOSX +#include "phydm_precomp.h" +#else +#include "../phydm_precomp.h" +#endif +#else +#include "../../phydm_precomp.h" +#endif + +#if (RTL8821C_SUPPORT == 1) +/*---------------------------Define Local Constant---------------------------*/ + +static u32 dpk_result[DPK_BACKUP_REG_NUM_8821C]; +static boolean txgap_done[3] = {false, false, false}; +static boolean overflowflag; +#define dpk_forcein_sram4 1 +#define txgap_ref_index 0x0 +#define txgap_k_number 0x7 + +/*---------------------------Define Local Constant---------------------------*/ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void do_iqk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value, + u8 threshold) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + dm->rf_calibrate_info.thermal_value_iqk = thermal_value; + halrf_segment_iqk_trigger(dm, true, iqk_info->segment_iqk); +} +#else +/*Originally config->do_iqk is hooked phy_iq_calibrate_8821c, but do_iqk_8821c and phy_iq_calibrate_8821c have different arguments*/ +void do_iqk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value, + u8 threshold) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + /*boolean is_recovery = (boolean) delta_thermal_index;*/ + halrf_segment_iqk_trigger(dm, true, iqk_info->segment_iqk); +} +#endif +void do_dpk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value, + u8 threshold) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + /*boolean is_recovery = (boolean) delta_thermal_index;*/ + phy_dp_calibrate_8821c(dm, true); +} + +boolean +_iqk_check_nctl_done_8821c(struct dm_struct *dm, u8 path, u32 IQK_CMD) +{ + /*this function is only used after the version of nctl8.0*/ + boolean notready = true; + boolean fail = true; + u32 delay_count = 0x0; + + while (notready) { + if ((IQK_CMD & 0x00000f00) >> 8 == 0xc) { + if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) == 0x1a3b5) + notready = false; + else + notready = true; + } else { + if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) == 0x12345) + notready = false; + else + notready = true; + } + if (notready) { + /*ODM_sleep_ms(1);*/ + ODM_delay_ms(1); + delay_count++; + } else { + fail = (boolean)odm_get_bb_reg(dm, R_0x1b08, BIT(26)); + if (fail) { + RF_DBG(dm, DBG_RF_IQK, + "[IQK](1)IQK_CMD =0x%x, Fail, 0x1b08=0x%x, RF08=0x%x, 1b00=0x%x,fail=0x%x, notready=0x%x!!!\n", + IQK_CMD, odm_read_4byte(dm, 0x1b08), + odm_get_rf_reg(dm, path, RF_0x08, + RFREGOFFSETMASK), + odm_read_4byte(dm, 0x1b00), fail, + notready); + } + break; + } + if (delay_count >= 50) { + RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d IQK timeout!!!\n", + path); + break; + } + } + odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0); + + if (!fail) { + RF_DBG(dm, DBG_RF_IQK, + "[IQK]IQK_CMD =0x%x, delay_count =0x%x RF0x08=0x%x, 0x1b08=0x%x,RF0xef=0x%x,RF0xdf=0x%x, !!!\n", + IQK_CMD, delay_count, + odm_get_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK), + odm_read_4byte(dm, 0x1b08), + odm_get_rf_reg(dm, path, RF_0xef, RFREGOFFSETMASK), + odm_get_rf_reg(dm, path, RF_0xdf, RFREGOFFSETMASK)); + } else { + RF_DBG(dm, DBG_RF_IQK, + "[IQK](2)IQK_CMD =0x%x, Fail, 0x1b08=0x%x, RF08=0x%x!!!\n", + IQK_CMD, odm_read_4byte(dm, 0x1b08), + odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK)); + } + return fail; +} + +void phydm_get_read_counter_8821c(struct dm_struct *dm) +{ + u32 counter = 0x0; + + while (1) { + if ((odm_get_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK) == 0xabcde) || counter > 300) + break; + counter++; + /*ODM_sleep_ms(1);*/ + ODM_delay_ms(1); + }; + odm_set_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK, 0x0); + RF_DBG(dm, DBG_RF_IQK, "[IQK]counter = %d\n", counter); +} + +void _iqk_check_coex_status(struct dm_struct *dm, boolean beforeK) +{ + u8 u1b_tmp; + u16 count = 0; + u8 h2c_parameter; + + h2c_parameter = 1; + + if (beforeK) { + u1b_tmp = odm_read_1byte(dm, 0x49c); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]check 0x49c[0] = 0x%x before h2c 0x6d\n", u1b_tmp); + + /*check if BT IQK */ + u1b_tmp = odm_read_1byte(dm, 0x49c); + while ((u1b_tmp & BIT(1)) && (count < 100)) { + /*ODM_sleep_ms(10);*/ + ODM_delay_ms(10); + u1b_tmp = odm_read_1byte(dm, 0x49c); + count++; + RF_DBG(dm, DBG_RF_IQK, + "[IQK]check 0x49c[1]=0x%x, count = %d\n", + u1b_tmp, count); + } +#if 1 + odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); + + u1b_tmp = odm_read_1byte(dm, 0x49c); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]check 0x49c[0] = 0x%x after h2c 0x6d\n", u1b_tmp); + + u1b_tmp = odm_read_1byte(dm, 0x49c); + /*check if WL IQK available form WL FW */ + while ((!(u1b_tmp & BIT(0))) && (count < 100)) { +#if 0 + /*ODM_sleep_ms(10);*/ +#endif + ODM_delay_ms(10); + u1b_tmp = odm_read_1byte(dm, 0x49c); + count++; + RF_DBG(dm, DBG_RF_IQK, + "[IQK]check 0x49c[1]=0x%x, count = %d\n", + u1b_tmp, count); + } + + if (count >= 100) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]Polling 0x49c to 1 for WiFi calibration H2C cmd FAIL! count(%d)\n", + count); +#endif + + } else { + odm_set_bb_reg(dm, R_0x49c, BIT(0), 0x0); + } +} + +u32 _iqk_indirect_read_reg(struct dm_struct *dm, u16 reg_addr) +{ + u32 j = 0; + + /*wait for ready bit before access 0x1700*/ + odm_write_4byte(dm, 0x1700, 0x800f0000 | reg_addr); + + do { + j++; + } while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000)); + + return odm_read_4byte(dm, 0x1708); /*get read data*/ +} + +void _iqk_indirect_write_reg(struct dm_struct *dm, u16 reg_addr, u32 bit_mask, + u32 reg_value) +{ + u32 val, i = 0, j = 0, bitpos = 0; + + if (bit_mask == 0x0) + return; + if (bit_mask == 0xffffffff) { + odm_write_4byte(dm, 0x1704, reg_value); /*put write data*/ + + /*wait for ready bit before access 0x1700*/ + do { + j++; + } while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000)); + + odm_write_4byte(dm, 0x1700, 0xc00f0000 | reg_addr); + } else { + for (i = 0; i <= 31; i++) { + if (((bit_mask >> i) & 0x1) == 0x1) { + bitpos = i; + break; + } + } + + /*read back register value before write*/ + val = _iqk_indirect_read_reg(dm, reg_addr); + val = (val & (~bit_mask)) | (reg_value << bitpos); + + odm_write_4byte(dm, 0x1704, val); /*put write data*/ + + /*wait for ready bit before access 0x1700*/ + do { + j++; + } while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000)); + + odm_write_4byte(dm, 0x1700, 0xc00f0000 | reg_addr); + } +} + +void _iqk_set_gnt_wl_high(struct dm_struct *dm) +{ + u32 val = 0; + u8 state = 0x1, sw_control = 0x1; + + /*GNT_WL = 1*/ + val = (sw_control) ? ((state << 1) | 0x1) : 0; + _iqk_indirect_write_reg(dm, 0x38, 0x3000, val); /*0x38[13:12]*/ + _iqk_indirect_write_reg(dm, 0x38, 0x0300, val); /*0x38[9:8]*/ +} + +void _iqk_set_gnt_bt_low(struct dm_struct *dm) +{ + u32 val = 0; + u8 state = 0x0, sw_control = 0x1; + + /*GNT_BT = 0*/ + val = (sw_control) ? ((state << 1) | 0x1) : 0; + _iqk_indirect_write_reg(dm, 0x38, 0xc000, val); /*0x38[15:14]*/ + _iqk_indirect_write_reg(dm, 0x38, 0x0c00, val); /*0x38[11:10]*/ +} + +void _iqk_set_gnt_wl_gnt_bt(struct dm_struct *dm, boolean beforeK) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (beforeK) { + _iqk_set_gnt_wl_high(dm); + _iqk_set_gnt_bt_low(dm); + } else { + _iqk_indirect_write_reg(dm, 0x38, MASKDWORD, iqk_info->tmp_gntwl); + } +} + +void _iqk_fail_count_8821c(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 i; + + dm->n_iqk_cnt++; + if (odm_get_rf_reg(dm, RF_PATH_A, RF_0x1bf0, BIT(16)) == 1) + iqk_info->is_reload = true; + else + iqk_info->is_reload = false; + + if (!iqk_info->is_reload) { + for (i = 0; i < 8; i++) { + if (odm_get_bb_reg(dm, R_0x1bf0, BIT(i)) == 1) + dm->n_iqk_fail_cnt++; + } + } + RF_DBG(dm, DBG_RF_IQK, "[IQK]All/Fail = %d %d\n", dm->n_iqk_cnt, + dm->n_iqk_fail_cnt); +} + +void _iqk_fill_iqk_report_8821c(void *dm_void, u8 channel) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u32 tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0; + u8 i; + + for (i = 0; i < SS_8821C; i++) { + tmp1 = tmp1 + ((iqk_info->iqk_fail_report[channel][i][TX_IQK] & 0x1) << i); + tmp2 = tmp2 + ((iqk_info->iqk_fail_report[channel][i][RX_IQK] & 0x1) << (i + 4)); + tmp3 = tmp3 + ((iqk_info->rxiqk_fail_code[channel][i] & 0x3) << (i * 2 + 8)); + } + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_set_bb_reg(dm, R_0x1bf0, 0x00ffffff, tmp1 | tmp2 | tmp3); + + for (i = 0; i < SS_8821C; i++) + odm_write_4byte(dm, 0x1be8 + (i * 4), (iqk_info->rxiqk_agc[channel][(i * 2) + 1] << 16) | iqk_info->rxiqk_agc[channel][i * 2]); + RF_DBG(dm, DBG_RF_IQK, "[IQK] 0x1be8 = %x\n", + odm_read_4byte(dm, 0x1be8)); +} + +void _iqk_iqk_fail_report_8821c(struct dm_struct *dm) +{ + u32 tmp1bf0 = 0x0; + u8 i; + + tmp1bf0 = odm_read_4byte(dm, 0x1bf0); + + for (i = 0; i < 4; i++) { + if (tmp1bf0 & (0x1 << i)) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_DBG(dm, DBG_RF_IQK, "[IQK] please check S%d TXIQK\n", + i); +#else + panic_printk("[IQK] please check S%d TXIQK\n", i); +#endif + if (tmp1bf0 & (0x1 << (i + 12))) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_DBG(dm, DBG_RF_IQK, "[IQK] please check S%d RXIQK\n", + i); +#else + panic_printk("[IQK] please check S%d RXIQK\n", i); +#endif + } +} + +void _iqk_backup_mac_bb_8821c(struct dm_struct *dm, u32 *MAC_backup, + u32 *BB_backup, u32 *backup_mac_reg, + u32 *backup_bb_reg, u8 num_backup_bb_reg) +{ + u32 i; + + for (i = 0; i < MAC_REG_NUM_8821C; i++) + MAC_backup[i] = odm_read_4byte(dm, backup_mac_reg[i]); + + for (i = 0; i < num_backup_bb_reg; i++) + BB_backup[i] = odm_read_4byte(dm, backup_bb_reg[i]); +#if 0 + /* RF_DBG(dm, DBG_RF_IQK, "[IQK]BackupMacBB Success!!!!\n"); */ +#endif +} + +void _iqk_backup_rf_8821c(struct dm_struct *dm, u32 RF_backup[][SS_8821C], + u32 *backup_rf_reg) +{ + u32 i, j; + + for (i = 0; i < RF_REG_NUM_8821C; i++) + for (j = 0; j < SS_8821C; j++) + RF_backup[i][j] = odm_get_rf_reg(dm, (u8)j, backup_rf_reg[i], RFREGOFFSETMASK); +#if 0 + /* RF_DBG(dm, DBG_RF_IQK, "[IQK]BackupRF Success!!!!\n"); */ +#endif +} + +void _iqk_agc_bnd_int_8821c(struct dm_struct *dm) +{ + /*initialize RX AGC bnd, it must do after bbreset*/ + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1b00, 0xf80a7008); + odm_write_4byte(dm, 0x1b00, 0xf8015008); + odm_write_4byte(dm, 0x1b00, 0xf8000008); +#if 0 + /*RF_DBG(dm, DBG_RF_IQK, "[IQK]init. rx agc bnd\n");*/ +#endif +} + +void _iqk_bb_reset_8821c(struct dm_struct *dm) +{ + boolean cca_ing = false; + u32 count = 0; + + odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x10000); + odm_set_bb_reg(dm, R_0x8f8, + BIT(27) | BIT26 | BIT25 | BIT24 | BIT23 | BIT22 | BIT21 | BIT20, 0x0); + + while (1) { + odm_write_4byte(dm, 0x8fc, 0x0); + odm_set_bb_reg(dm, R_0x198c, 0x7, 0x7); + cca_ing = (boolean)odm_get_bb_reg(dm, R_0xfa0, BIT(3)); + + if (count > 30) + cca_ing = false; + + if (cca_ing) { + ODM_sleep_ms(1); + count++; + } else { + odm_write_1byte(dm, 0x808, 0x0); /*RX ant off*/ + odm_set_bb_reg(dm, R_0xa04, BIT(27) | BIT26 | BIT25 | BIT24, 0x0); /*CCK RX path off*/ + + /*BBreset*/ + odm_set_bb_reg(dm, R_0x0, BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x0, BIT(16), 0x1); + + if (odm_get_bb_reg(dm, R_0x660, BIT(16))) + odm_write_4byte(dm, 0x6b4, 0x89000006); + RF_DBG(dm, DBG_RF_IQK, "[IQK]BBreset!!!!\n"); + break; + } + } +} + +void _iqk_afe_setting_8821c(struct dm_struct *dm, boolean do_iqk) +{ + if (do_iqk) { + /*IQK AFE setting RX_WAIT_CCA mode */ + odm_write_4byte(dm, 0xc60, 0x50000000); + odm_write_4byte(dm, 0xc60, 0x700F0040); + + /*AFE setting*/ + odm_write_4byte(dm, 0xc58, 0xd8000402); + odm_write_4byte(dm, 0xc5c, 0xd1000120); + odm_write_4byte(dm, 0xc6c, 0x00000a15); + _iqk_bb_reset_8821c(dm); +#if 0 + /* RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE setting for IQK mode!!!!\n"); */ +#endif + } else { + /*IQK AFE setting RX_WAIT_CCA mode */ + odm_write_4byte(dm, 0xc60, 0x50000000); + odm_write_4byte(dm, 0xc60, 0x700B8040); + + /*AFE setting*/ + odm_write_4byte(dm, 0xc58, 0xd8020402); + odm_write_4byte(dm, 0xc5c, 0xde000120); + odm_write_4byte(dm, 0xc6c, 0x0000122a); +#if 0 + /* RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE setting for Normal mode!!!!\n"); */ +#endif + } + /*0x9a4[31]=0: Select da clock*/ + odm_set_bb_reg(dm, R_0x9a4, BIT(31), 0x0); +} + +void _iqk_restore_mac_bb_8821c(struct dm_struct *dm, u32 *MAC_backup, + u32 *BB_backup, u32 *backup_mac_reg, + u32 *backup_bb_reg, u8 num_backup_bb_reg) +{ + u32 i; + + for (i = 0; i < MAC_REG_NUM_8821C; i++) + odm_write_4byte(dm, backup_mac_reg[i], MAC_backup[i]); + for (i = 0; i < num_backup_bb_reg; i++) + odm_write_4byte(dm, backup_bb_reg[i], BB_backup[i]); +#if 0 + /* RF_DBG(dm, DBG_RF_IQK, "[IQK]RestoreMacBB Success!!!!\n"); */ +#endif +} + +void _iqk_restore_rf_8821c(struct dm_struct *dm, u32 *backup_rf_reg, + u32 RF_backup[][SS_8821C]) +{ + u32 i; + + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, RF_backup[0][RF_PATH_A] & (~BIT(4))); +#if 0 + /*odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK, RF_backup[1][RF_PATH_A]|BIT(4));*/ +#endif + odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK, RF_backup[1][RF_PATH_A] & (~BIT(4))); + + for (i = 2; i < (RF_REG_NUM_8821C - 1); i++) + odm_set_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][RF_PATH_A]); + + odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, (RF_backup[4][RF_PATH_A] & (~BIT(0)))); +#if 0 + /*RF_DBG(dm, DBG_RF_IQK, "[IQK]RestoreRF Success!!!!\n"); */ +#endif +} + +void _iqk_backup_iqk_8821c(struct dm_struct *dm, u8 step, u8 path) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 i, j, k; +#if 0 + /*u16 iqk_apply[2] = {0xc94, 0xe94};*/ +#endif + + switch (step) { + case 0: + iqk_info->iqk_channel[1] = iqk_info->iqk_channel[0]; + for (i = 0; i < SS_8821C; i++) { + iqk_info->lok_idac[1][i] = iqk_info->lok_idac[0][i]; + iqk_info->rxiqk_agc[1][i] = iqk_info->rxiqk_agc[0][i]; + iqk_info->bypass_iqk[1][i] = iqk_info->bypass_iqk[0][i]; + iqk_info->rxiqk_fail_code[1][i] = iqk_info->rxiqk_fail_code[0][i]; + for (j = 0; j < 2; j++) { + iqk_info->iqk_fail_report[1][i][j] = iqk_info->iqk_fail_report[0][i][j]; + for (k = 0; k < 8; k++) { + iqk_info->iqk_cfir_real[1][i][j][k] = iqk_info->iqk_cfir_real[0][i][j][k]; + iqk_info->iqk_cfir_imag[1][i][j][k] = iqk_info->iqk_cfir_imag[0][i][j][k]; + } + } + } + for (i = 0; i < 4; i++) { + iqk_info->rxiqk_fail_code[0][i] = 0x0; + iqk_info->rxiqk_agc[0][i] = 0x0; + for (j = 0; j < 2; j++) { + iqk_info->iqk_fail_report[0][i][j] = true; + iqk_info->gs_retry_count[0][i][j] = 0x0; + } + for (j = 0; j < 3; j++) + iqk_info->retry_count[0][i][j] = 0x0; + } + /*backup channel*/ + iqk_info->iqk_channel[0] = iqk_info->rf_reg18; + break; + case 1: /*LOK backup*/ + iqk_info->lok_idac[0][path] = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK); + break; + case 2: /*TXIQK backup*/ + case 3: /*RXIQK backup*/ + phydm_get_iqk_cfir(dm, (step - 2), path, false); + break; + } +} + +void _iqk_reload_iqk_setting_8821c(struct dm_struct *dm, u8 channel, + u8 reload_idx + /*1: reload TX, 2: reload TX, RX*/) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 i, path, idx; + u16 iqk_apply[2] = {0xc94, 0xe94}; + + for (path = 0; path < SS_8821C; path++) { +#if 0 + if (reload_idx == 2) { + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK, iqk_info->lok_idac[channel][path]); + } +#endif + for (idx = 0; idx < reload_idx; idx++) { + odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0xf8000008 | path << 1); + odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7); + odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000); + odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000); + if (idx == 0) + odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x3); + else + odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x1); + odm_set_bb_reg(dm, R_0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10); + for (i = 0; i < 8; i++) { + odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (iqk_info->iqk_cfir_real[channel][path][idx][i] << 9)); + odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (iqk_info->iqk_cfir_imag[channel][path][idx][i] << 9)); + } + if (idx == 0) + odm_set_bb_reg(dm, iqk_apply[path], BIT(0), ~(iqk_info->iqk_fail_report[channel][path][idx])); + else + odm_set_bb_reg(dm, iqk_apply[path], BIT(10), ~(iqk_info->iqk_fail_report[channel][path][idx])); + } + odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x0); + } +} + +boolean +_iqk_reload_iqk_8821c(struct dm_struct *dm, boolean reset) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 i; + iqk_info->is_reload = false; + odm_set_bb_reg(dm, R_0x1bf0, BIT(16), 0x0); /*clear the reload flag*/ + + if (reset) { + for (i = 0; i < SS_8821C; i++) + iqk_info->iqk_channel[i] = 0x0; + } else { + iqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK); + + for (i = 0; i < SS_8821C; i++) { + if (iqk_info->rf_reg18 == iqk_info->iqk_channel[i]) { + _iqk_reload_iqk_setting_8821c(dm, i, 2); + _iqk_fill_iqk_report_8821c(dm, i); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]reload IQK result before!!!!\n"); + odm_set_bb_reg(dm, R_0x1bf0, BIT(16), 0x1); + iqk_info->is_reload = true; + } + } + } + + return iqk_info->is_reload; +} + +void _iqk_rfe_setting_8821c(struct dm_struct *dm, boolean ext_pa_on) +{ + if (ext_pa_on) { + /*RFE setting*/ + odm_write_4byte(dm, 0xcb0, 0x77777777); + odm_write_4byte(dm, 0xcb4, 0x00007777); + odm_write_4byte(dm, 0xcbc, 0x0000083B); +#if 0 + /*odm_write_4byte(dm, 0x1990, 0x00000c30);*/ +#endif + RF_DBG(dm, DBG_RF_IQK, "[IQK]external PA on!!!!\n"); + } else { + /*RFE setting*/ + odm_write_4byte(dm, 0xcb0, 0x77171117); + odm_write_4byte(dm, 0xcb4, 0x00001177); + odm_write_4byte(dm, 0xcbc, 0x00000404); +#if 0 + /*odm_write_4byte(dm, 0x1990, 0x00000c30);*/ +#endif + RF_DBG(dm, DBG_RF_IQK, "[IQK]external PA off!!!!\n"); + } +} + +void _iqk_rfsetting_8821c(struct dm_struct *dm) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + u8 path; + u32 tmp; + + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1bb8, 0x00000000); + + for (path = 0; path < SS_8821C; path++) { + /*0xdf:B11 = 1,B4 = 0, B1 = 1*/ + tmp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0xdf, RFREGOFFSETMASK); + tmp = (tmp & (~BIT(4))) | BIT(1) | BIT(11); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, RFREGOFFSETMASK, tmp); + + if (iqk_info->is_btg) { + tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK); + tmp = (tmp & (~BIT(4))) | BIT(15); +#if 0 + /*tmp = tmp|BIT(4)|BIT(15); //manual LOK value for A-cut*/ +#endif + odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK, tmp); + } + + if (!iqk_info->is_btg) { + /*WLAN_AG*/ + /*TX IQK mode init*/ + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, RFREGOFFSETMASK, 0x80000); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00024); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x0003f); +#if 0 + /*odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x60fde);*/ +#endif + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0xe0fde); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, RFREGOFFSETMASK, 0x00000); + if (*dm->band_type == ODM_BAND_5G) { + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00026); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00037); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0xdefce); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0); + } else { + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00026); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00037); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x5efce); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0); + } + } else { + /*WLAN_BTG*/ + /*TX IQK mode init*/ + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, RFREGOFFSETMASK, 0x01000); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00004); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x01ec1); + odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, RFREGOFFSETMASK, 0x00000); + } + } +} + +void _iqk_configure_macbb_8821c(struct dm_struct *dm) +{ + /*MACBB register setting*/ + odm_write_1byte(dm, 0x522, 0x7f); + odm_set_bb_reg(dm, R_0x1518, BIT(16), 0x1); + odm_set_bb_reg(dm, R_0x550, BIT(11) | BIT(3), 0x0); + odm_set_bb_reg(dm, R_0x90c, BIT(15), 0x1); /*0x90c[15]=1: dac_buf reset selection*/ + + /*0xc94[0]=1, 0xe94[0]=1: Let tx from IQK*/ + odm_set_bb_reg(dm, R_0xc94, BIT(0), 0x1); + odm_set_bb_reg(dm, R_0xc94, (BIT(11) | BIT(10)), 0x1); + /* 3-wire off*/ + odm_write_4byte(dm, 0xc00, 0x00000004); + /*disable PMAC*/ + odm_set_bb_reg(dm, R_0xb00, BIT(8), 0x0); +#if 0 + /* RF_DBG(dm, DBG_RF_IQK, "[IQK]Set MACBB setting for IQK!!!!\n");*/ +#endif + /*disable CCK block*/ + odm_set_bb_reg(dm, R_0x808, BIT(28), 0x0); + /*disable OFDM CCA*/ + odm_set_bb_reg(dm, R_0x838, BIT(3) | BIT(2) | BIT(1), 0x7); + +} + +void _iqk_lok_setting_8821c(struct dm_struct *dm, u8 path, u8 pad_index) +{ + u32 LOK0x56_2G = 0x50ef3; + u32 LOK0x56_5G = 0x50ee8; + u32 LOK0x33 = 0; + u32 LOK0x78 = 0xbcbba; + u32 tmp = 0; + + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + LOK0x33 = pad_index; + /*add delay of MAC send packet*/ + + if (*dm->mp_mode) + odm_set_bb_reg(dm, R_0x810, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x8); + + if (iqk_info->is_btg) { + tmp = (LOK0x78 & 0x1c000) >> 14; + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1bcc, 0x1b); + odm_write_1byte(dm, 0x1b23, 0x00); + odm_write_1byte(dm, 0x1b2b, 0x80); + /*0x78[11:0] = IDAC value*/ + LOK0x78 = LOK0x78 & (0xe3fff | ((u32)pad_index << 14)); + odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, LOK0x78); + odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x05320); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xac018); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(4), 0x1); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, BIT(3), 0x0); + RF_DBG(dm, DBG_RF_IQK, "[IQK] In the BTG\n"); + } else { + /*tmp = (LOK0x56 & 0xe0) >> 5;*/ + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1bcc, 0x9); + odm_write_1byte(dm, 0x1b23, 0x00); + + switch (*dm->band_type) { + case ODM_BAND_2_4G: + odm_write_1byte(dm, 0x1b2b, 0x00); + LOK0x56_2G = LOK0x56_2G & (0xfff1f | ((u32)pad_index << 5)); + odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, LOK0x56_2G); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xadc18); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(4), 0x1); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, BIT(3), 0x0); + break; + case ODM_BAND_5G: + odm_write_1byte(dm, 0x1b2b, 0x00); + LOK0x56_5G = LOK0x56_5G & (0xfff1f | ((u32)pad_index << 5)); + odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, LOK0x56_5G); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xadc18); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(4), 0x1); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, BIT(3), 0x1); + break; + } + } + /*for IDAC LUT by PAD idx*/ + odm_set_rf_reg(dm, path, RF_0x33, BIT(2) | BIT(1) | BIT(0), LOK0x33); +#if 0 + /* RF_DBG(dm, DBG_RF_IQK, "[IQK]Set LOK setting!!!!\n");*/ +#endif +} + +void _iqk_txk_setting_8821c(struct dm_struct *dm, u8 path) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (iqk_info->is_btg) { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1bcc, 0x1b); + odm_write_4byte(dm, 0x1b20, 0x00840008); + + /*0x78[11:0] = IDAC value*/ + odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0xbcbba); + odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x04320); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xac018); + odm_write_1byte(dm, 0x1b2b, 0x80); + } else { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1bcc, 0x9); + odm_write_4byte(dm, 0x1b20, 0x01440008); + + switch (*dm->band_type) { + case ODM_BAND_2_4G: + odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x50EF3); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xadc18); + odm_write_1byte(dm, 0x1b2b, 0x00); + break; + case ODM_BAND_5G: +#if 0 + /*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x50EF0);*/ + /*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x50Ec8);*/ +#endif + odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x5004e); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c18); + odm_write_1byte(dm, 0x1b2b, 0x00); + break; + } + } +#if 0 + /* RF_DBG(dm, DBG_RF_IQK, "[IQK]Set TXK setting!!!!\n");*/ +#endif +} + +void _iqk_rxk1setting_8821c(struct dm_struct *dm, u8 path) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (iqk_info->is_btg) { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_1byte(dm, 0x1b2b, 0x80); + odm_write_4byte(dm, 0x1bcc, 0x09); + odm_write_4byte(dm, 0x1b20, 0x01450008); + odm_write_4byte(dm, 0x1b24, 0x01460c88); + + /*0x78[11:0] = IDAC value*/ + odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0x8cbba); + odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x00320); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa8018); + } else { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + switch (*dm->band_type) { + case ODM_BAND_2_4G: + odm_write_1byte(dm, 0x1bcc, 0x12); + odm_write_1byte(dm, 0x1b2b, 0x00); + odm_write_4byte(dm, 0x1b20, 0x01450008); + odm_write_4byte(dm, 0x1b24, 0x01461068); + + odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + case ODM_BAND_5G: + odm_write_1byte(dm, 0x1bcc, 0x9); + odm_write_1byte(dm, 0x1b2b, 0x00); + odm_write_4byte(dm, 0x1b20, 0x00450008); + odm_write_4byte(dm, 0x1b24, 0x00461468); + + odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + } + } +#if 0 + /*RF_DBG(dm, DBG_RF_IQK, "[IQK]Set RXK setting!!!!\n");*/ +#endif +} + +static u8 btg_lna[5] = {0x0, 0x4, 0x8, 0xc, 0xf}; +static u8 wlg_lna[5] = {0x0, 0x1, 0x2, 0x3, 0x5}; +static u8 wla_lna[5] = {0x0, 0x1, 0x3, 0x4, 0x5}; + +void _iqk_rxk2setting_8821c(struct dm_struct *dm, u8 path, boolean is_gs) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (iqk_info->is_btg) { + if (is_gs) { + iqk_info->tmp1bcc = 0x1b; + iqk_info->lna_idx = 2; + } + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_1byte(dm, 0x1b2b, 0x80); + odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc); + odm_write_4byte(dm, 0x1b20, 0x01450008); + odm_write_4byte(dm, 0x1b24, (0x01460048 | (btg_lna[iqk_info->lna_idx] << 10))); + /*0x78[11:0] = IDAC value*/ + odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0x8cbba); + odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x00320); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa8018); + } else { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + switch (*dm->band_type) { + case ODM_BAND_2_4G: + if (is_gs) { + iqk_info->tmp1bcc = 0x12; + iqk_info->lna_idx = 2; + } + odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc); + odm_write_1byte(dm, 0x1b2b, 0x00); + odm_write_4byte(dm, 0x1b20, 0x01450008); + odm_write_4byte(dm, 0x1b24, (0x01460048 | (wlg_lna[iqk_info->lna_idx] << 10))); + odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + case ODM_BAND_5G: + if (is_gs) { + /*iqk_info->tmp1bcc = 0x12;*/ + iqk_info->tmp1bcc = 0x09; + iqk_info->lna_idx = 2; + } + odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc); + odm_write_1byte(dm, 0x1b2b, 0x00); + odm_write_4byte(dm, 0x1b20, 0x00450008); + odm_write_4byte(dm, 0x1b24, (0x01460048 | (wla_lna[iqk_info->lna_idx] << 10))); +#if 0 + /*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51000);*/ +#endif + odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51060); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + } + } +#if 0 + /* RF_DBG(dm, DBG_RF_IQK, "[IQK]Set RXK setting!!!!\n");*/ +#endif +} + +boolean +_iqk_check_cal_8821c(struct dm_struct *dm, u32 IQK_CMD) +{ + boolean notready = true, fail = true; + u32 delay_count = 0x0; + + while (notready) { + if (odm_read_4byte(dm, 0x1b00) == (IQK_CMD & 0xffffff0f)) { + fail = (boolean)odm_get_bb_reg(dm, R_0x1b08, BIT(26)); + notready = false; + } else { +#if 0 + /*ODM_sleep_ms(1);*/ +#endif + ODM_delay_ms(1); + delay_count++; + } + + if (delay_count >= 50) { + fail = true; + RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK timeout!!!\n"); + break; + } + } +#if 0 + /* + RF_DBG(dm, DBG_RF_IQK, + "[IQK]delay count = 0x%x!!!\n", delay_count); +*/ +#endif + return fail; +} + +boolean +_iqk_rx_iqk_gain_search_fail_8821c(struct dm_struct *dm, u8 path, u8 step) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + boolean fail = true; + u32 IQK_CMD = 0x0, rf_reg0, tmp, rxbb; + u8 IQMUX[4] = {0x9, 0x12, 0x1b, 0x24}, *plna; + u8 idx; + /*u8 lna_setting[5];*/ + + if (iqk_info->is_btg) + plna = btg_lna; + else if (*dm->band_type == ODM_BAND_2_4G) + plna = wlg_lna; + else + plna = wla_lna; + + for (idx = 0; idx < 4; idx++) + if (iqk_info->tmp1bcc == IQMUX[idx]) + break; + + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc); + + if (step == RXIQK1) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]============ S%d RXIQK GainSearch ============\n", + iqk_info->is_btg); + + if (step == RXIQK1) + IQK_CMD = 0xf8000208 | (1 << (path + 4)); + else + IQK_CMD = 0xf8000308 | (1 << (path + 4)); + + RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d GS%d_Trigger = 0x%x\n", path, step, + IQK_CMD); + + _iqk_set_gnt_wl_gnt_bt(dm, true); + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1); +#if 0 + /*ODM_sleep_ms(GS_delay_8821C);*/ +#endif + ODM_delay_ms(GS_delay_8821C); + fail = _iqk_check_cal_8821c(dm, IQK_CMD); + RF_DBG(dm, DBG_RF_IQK, "[IQK]check 0x49c = %x\n", + odm_read_1byte(dm, 0x49c)); + _iqk_set_gnt_wl_gnt_bt(dm, false); + + if (step == RXIQK2) { + rf_reg0 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x0, RFREGOFFSETMASK); + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]S%d ==> RF0x0 = 0x%x, tmp1bcc = 0x%x, idx = %d, 0x1b3c = 0x%x\n", + path, rf_reg0, iqk_info->tmp1bcc, idx, + odm_read_4byte(dm, 0x1b3c)); + tmp = (rf_reg0 & 0x1fe0) >> 5; + rxbb = tmp & 0x1f; +#if 1 + + if (rxbb == 0x1) { + if (idx != 3) + idx++; + else if (iqk_info->lna_idx != 0x0) + iqk_info->lna_idx--; + else + iqk_info->isbnd = true; + fail = true; + } else if (rxbb == 0xa) { + if (idx != 0) + idx--; + else if (iqk_info->lna_idx != 0x4) + iqk_info->lna_idx++; + else + iqk_info->isbnd = true; + fail = true; + } else { + fail = false; + } + + if (iqk_info->isbnd) + fail = false; +#endif + +#if 0 + if (rxbb == 0x1) { + if (iqk_info->lna_idx != 0x0) + iqk_info->lna_idx--; + else if (idx != 3) + idx++; + else + iqk_info->isbnd = true; + fail = true; + } else if (rxbb == 0xa) { + if (idx != 0) + idx--; + else if (iqk_info->lna_idx != 0x7) + iqk_info->lna_idx++; + else + iqk_info->isbnd = true; + fail = true; + } else + fail = false; + + if (iqk_info->isbnd == true) + fail = false; +#endif + iqk_info->tmp1bcc = IQMUX[idx]; + + if (fail) { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0xffffc3ff) | (*(plna + iqk_info->lna_idx) << 10)); + } + } + return fail; +} +void _iqk_rxk2setting_by_toneindex_8821c(struct dm_struct *dm, u8 path, + boolean is_gs, u8 toneindex) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (iqk_info->is_btg) { + iqk_info->tmp1bcc = 0x1b; + iqk_info->lna_idx = 2; + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_1byte(dm, 0x1b2b, 0x80); + odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc); + odm_write_4byte(dm, 0x1b20, 0x01450008); + odm_write_4byte(dm, 0x1b24, (0x01460048 | (btg_lna[iqk_info->lna_idx] << 10))); + /*0x78[11:0] = IDAC value*/ + odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0x8cbba); + odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x00320); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa8018); + } else { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + switch (*dm->band_type) { + case ODM_BAND_2_4G: + iqk_info->tmp1bcc = 0x12; + iqk_info->lna_idx = 2; + odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc); + odm_write_1byte(dm, 0x1b2b, 0x00); + odm_write_4byte(dm, 0x1b20, 0x01450008); + odm_write_4byte(dm, 0x1b24, (0x01460048 | (wlg_lna[iqk_info->lna_idx] << 10))); + odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + case ODM_BAND_5G: + iqk_info->tmp1bcc = 0x09; + iqk_info->lna_idx = 2; + odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc); + odm_write_1byte(dm, 0x1b2b, 0x00); + odm_write_4byte(dm, 0x1b20, 0x00450008); + odm_write_4byte(dm, 0x1b24, (0x01460048 | (wla_lna[iqk_info->lna_idx] << 10))); +#if 0 + /*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51000);*/ +#endif + odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51060); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + } + } + odm_write_4byte(dm, 0x1b20, (odm_read_4byte(dm, 0x1b20) & 0x000fffff) | toneindex << 20); + odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0x000fffff) | toneindex << 20); +} + +boolean +_iqk_rx_iqk_gain_search_fail_by_toneindex_8821c(struct dm_struct *dm, u8 path, + u8 step, u8 tone_index) +{ + boolean fail = true; + u32 IQK_CMD; +#if 0 + /*u8 lna_setting[5];*/ +#endif + + _iqk_rxk2setting_by_toneindex_8821c(dm, path, RXIQK1, tone_index); + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + + IQK_CMD = 0xf8000208 | (1 << (path + 4)); + + _iqk_set_gnt_wl_gnt_bt(dm, true); + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1); +#if 0 + /*ODM_sleep_ms(GS_delay_8821C);*/ +#endif + ODM_delay_ms(GS_delay_8821C); + fail = _iqk_check_cal_8821c(dm, IQK_CMD); + _iqk_set_gnt_wl_gnt_bt(dm, false); + + return fail; +} + +boolean +_lok_one_shot_8821c(void *dm_void, u8 path, u8 pad_index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 delay_count = 0; + boolean LOK_notready = false; + u32 LOK_temp2 = 0, LOK_temp3 = 0; + u32 IQK_CMD = 0x0; +#if 0 + /*u8 LOKreg[] = {0x58, 0x78};*/ +#endif + RF_DBG(dm, DBG_RF_IQK, "[IQK]==========S%d LOK ==========\n", + iqk_info->is_btg); + + IQK_CMD = 0xf8000008 | (1 << (4 + path)); + + RF_DBG(dm, DBG_RF_IQK, "[IQK]LOK_Trigger = 0x%x\n", IQK_CMD); + + _iqk_set_gnt_wl_gnt_bt(dm, true); + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 1); + /*LOK: CMD ID = 0 {0xf8000018, 0xf8000028}*/ + /*LOK: CMD ID = 0 {0xf8000019, 0xf8000029}*/ +#if 0 + /*ODM_sleep_ms(LOK_delay_8821C);*/ +#endif + ODM_delay_ms(LOK_delay_8821C); + + delay_count = 0; + LOK_notready = true; + + while (LOK_notready) { + if (odm_get_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK) == 0x12345) + LOK_notready = false; + else + LOK_notready = true; + + if (LOK_notready) { +#if 0 + /*ODM_sleep_ms(1);*/ +#endif + ODM_delay_ms(1); + delay_count++; + } + + if (delay_count >= 50) { + RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d LOK timeout!!!\n", + path); + break; + } + } + odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0); + + _iqk_set_gnt_wl_gnt_bt(dm, false); + RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d ==> delay_count = 0x%x\n", path, + delay_count); + + if (!LOK_notready) { + LOK_temp2 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x8, RFREGOFFSETMASK); + LOK_temp3 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK); + + RF_DBG(dm, DBG_RF_IQK, "[IQK]0x8 = 0x%x, 0x58 = 0x%x\n", + LOK_temp2, LOK_temp3); + } else { + RF_DBG(dm, DBG_RF_IQK, "[IQK]==>S%d LOK Fail!!!\n", path); + } + + iqk_info->lok_fail[path] = LOK_notready; + + /*fill IDAC LUT table*/ +#if 0 + /* + for (i = 0; i < 8; i++) { + odm_set_rf_reg(dm, path, RF_0x33, BIT(2)|BIT(1)|BIT(0), i); + odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, LOK_temp2); + } + */ +#endif + return LOK_notready; +} + +boolean +_iqk_one_shot_8821c(void *dm_void, u8 path, u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 delay_count = 0; + boolean fail = true; + u32 IQK_CMD = 0x0; + u16 iqk_apply[2] = {0xc94, 0xe94}; + + if (idx == TX_IQK) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]============ S%d WBTXIQK ============\n", + iqk_info->is_btg); + else if (idx == RXIQK1) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]============ S%d WBRXIQK STEP1============\n", + iqk_info->is_btg); + else + RF_DBG(dm, DBG_RF_IQK, + "[IQK]============ S%d WBRXIQK STEP2============\n", + iqk_info->is_btg); + + if (idx == TXIQK) { + IQK_CMD = 0xf8000008 | ((*dm->band_width + 4) << 8) | (1 << (path + 4)); + RF_DBG(dm, DBG_RF_IQK, "[IQK]TXK_Trigger = 0x%x\n", IQK_CMD); +#if 0 + /*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 4)*/ + /*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 5)*/ + /*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 6)*/ +#endif + } else if (idx == RXIQK1) { + if (*dm->band_width == 2) + IQK_CMD = 0xf8000808 | (1 << (path + 4)); + else + IQK_CMD = 0xf8000708 | (1 << (path + 4)); + RF_DBG(dm, DBG_RF_IQK, "[IQK]RXK1_Trigger = 0x%x\n", IQK_CMD); +#if 0 + /*{0xf8000718, 0xf800072a} ==> 20 WBTXK (CMD = 7)*/ + /*{0xf8000718, 0xf800072a} ==> 40 WBTXK (CMD = 7)*/ + /*{0xf8000818, 0xf800082a} ==> 80 WBTXK (CMD = 8)*/ +#endif + } else if (idx == RXIQK2) { + IQK_CMD = 0xf8000008 | ((*dm->band_width + 9) << 8) | (1 << (path + 4)); + RF_DBG(dm, DBG_RF_IQK, "[IQK]RXK2_Trigger = 0x%x\n", IQK_CMD); +#if 0 + /*{0xf8000918, 0xf800092a} ==> 20 WBRXK (CMD = 9)*/ + /*{0xf8000a18, 0xf8000a2a} ==> 40 WBRXK (CMD = 10)*/ + /*{0xf8000b18, 0xf8000b2a} ==> 80 WBRXK (CMD = 11)*/ +#endif + } + + _iqk_set_gnt_wl_gnt_bt(dm, true); + + odm_write_4byte(dm, 0x1bc8, 0x80000000); + odm_write_4byte(dm, 0x8f8, 0x41400080); + + if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0) + odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0); + + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1); + +#if 0 + /*ODM_sleep_ms(WBIQK_delay_8821C);*/ +#endif + ODM_delay_ms(WBIQK_delay_8821C); + + fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD); + + RF_DBG(dm, DBG_RF_IQK, "[IQK]check 0x49c = %x\n", + odm_read_1byte(dm, 0x49c)); + + _iqk_set_gnt_wl_gnt_bt(dm, false); + + if (dm->debug_components & DBG_RF_IQK) { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n", path, + odm_read_4byte(dm, 0x1b00), odm_read_4byte(dm, 0x1b08)); + RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d ==> delay_count = 0x%x\n", + path, delay_count); + if (idx != TXIQK) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]S%d ==> RF0x0 = 0x%x, RF0x%x = 0x%x\n", + path, + odm_get_rf_reg(dm, path, RF_0x0, + RFREGOFFSETMASK), + (iqk_info->is_btg) ? 0x78 : 0x56, + (iqk_info->is_btg) ? + odm_get_rf_reg(dm, path, RF_0x78, + RFREGOFFSETMASK) : + odm_get_rf_reg(dm, path, RF_0x56, + RFREGOFFSETMASK)); + } + + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + if (idx == TXIQK) { + if (fail) + odm_set_bb_reg(dm, iqk_apply[path], BIT(0), 0x0); + else + _iqk_backup_iqk_8821c(dm, 0x2, path); + } + if (idx == RXIQK2) { + iqk_info->rxiqk_agc[0][path] = + (u16)(((odm_get_rf_reg(dm, (enum rf_path)path, RF_0x0, RFREGOFFSETMASK) >> 5) & 0xff) | + (iqk_info->tmp1bcc << 8)); + + odm_write_4byte(dm, 0x1b38, 0x20000000); + + if (fail) + odm_set_bb_reg(dm, iqk_apply[path], (BIT(11) | BIT(10)), 0x0); + else + _iqk_backup_iqk_8821c(dm, 0x3, path); + } + + if (idx == TXIQK) + iqk_info->iqk_fail_report[0][path][TXIQK] = fail; + else + iqk_info->iqk_fail_report[0][path][RXIQK] = fail; + + return fail; +} + +boolean +_iqk_rxiqkbystep_8821c(void *dm_void, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + boolean KFAIL = true, gonext; + +#if 1 + switch (iqk_info->rxiqk_step) { + case 1: /*gain search_RXK1*/ + _iqk_rxk1setting_8821c(dm, path); + gonext = false; + while (1) { + KFAIL = _iqk_rx_iqk_gain_search_fail_8821c(dm, path, RXIQK1); + if (KFAIL && iqk_info->gs_retry_count[0][path][0] < 2) { + iqk_info->gs_retry_count[0][path][0]++; + } else if (KFAIL) { + iqk_info->rxiqk_fail_code[0][path] = 0; + iqk_info->rxiqk_step = 5; + gonext = true; + } else { + iqk_info->rxiqk_step++; + gonext = true; + } + if (gonext) + break; + } + halrf_iqk_xym_read(dm, 0x0, 0x2); + break; + case 2: /*gain search_RXK2*/ + _iqk_rxk2setting_8821c(dm, path, true); + iqk_info->isbnd = false; + while (1) { + KFAIL = _iqk_rx_iqk_gain_search_fail_8821c(dm, path, RXIQK2); + if (KFAIL && iqk_info->gs_retry_count[0][path][1] < rxiqk_gs_limit) { + iqk_info->gs_retry_count[0][path][1]++; + } else { + iqk_info->rxiqk_step++; + break; + } + } + halrf_iqk_xym_read(dm, 0x0, 0x3); + break; + case 3: /*RXK1*/ + _iqk_rxk1setting_8821c(dm, path); + gonext = false; + while (1) { + KFAIL = _iqk_one_shot_8821c(dm, path, RXIQK1); + if (KFAIL && iqk_info->retry_count[0][path][RXIQK1] < 2) { + iqk_info->retry_count[0][path][RXIQK1]++; + } else if (KFAIL) { + iqk_info->rxiqk_fail_code[0][path] = 1; + iqk_info->rxiqk_step = 5; + gonext = true; + } else { + iqk_info->rxiqk_step++; + gonext = true; + } + if (gonext) + break; + } + halrf_iqk_xym_read(dm, 0x0, 0x4); + break; + case 4: /*RXK2*/ + _iqk_rxk2setting_8821c(dm, path, false); + gonext = false; + while (1) { + KFAIL = _iqk_one_shot_8821c(dm, path, RXIQK2); + if (KFAIL && iqk_info->retry_count[0][path][RXIQK2] < 2) { + iqk_info->retry_count[0][path][RXIQK2]++; + } else if (KFAIL) { + iqk_info->rxiqk_fail_code[0][path] = 2; + iqk_info->rxiqk_step = 5; + gonext = true; + } else { + iqk_info->rxiqk_step++; + gonext = true; + } + if (gonext) + break; + } + halrf_iqk_xym_read(dm, 0x0, 0x0); + break; + } + return KFAIL; +#endif +} +void _iqk_iqk_by_path_8821c(void *dm_void, boolean segment_iqk) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + boolean KFAIL = true; + u8 i, kcount_limit; + +#if 0 + /* RF_DBG(dm, DBG_RF_IQK, "[IQK]iqk_step = 0x%x\n", dm->rf_calibrate_info.iqk_step); */ +#endif + if (*dm->band_width == 2) + kcount_limit = kcount_limit_80m; + else + kcount_limit = kcount_limit_others; + + while (1) { + switch (dm->rf_calibrate_info.iqk_step) { + case 1: /*S0 LOK*/ + for (i = 0; i < 8; i++) { /* the LOK Cal in the each PAD stage*/ + _iqk_lok_setting_8821c(dm, RF_PATH_A, i); + _lok_one_shot_8821c(dm, RF_PATH_A, i); + } + dm->rf_calibrate_info.iqk_step++; + break; + case 2: /*S0 TXIQK*/ + _iqk_txk_setting_8821c(dm, RF_PATH_A); + KFAIL = _iqk_one_shot_8821c(dm, RF_PATH_A, TXIQK); + iqk_info->kcount++; + RF_DBG(dm, DBG_RF_IQK, "[IQK]KFail = 0x%x\n", KFAIL); + if (KFAIL && iqk_info->retry_count[0][RF_PATH_A][TXIQK] < 3) + iqk_info->retry_count[0][RF_PATH_A][TXIQK]++; + else + dm->rf_calibrate_info.iqk_step++; + halrf_iqk_xym_read(dm, 0x0, 0x1); + break; + case 3: /*S0 RXIQK*/ + while (1) { + KFAIL = _iqk_rxiqkbystep_8821c(dm, RF_PATH_A); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]S0RXK KFail = 0x%x\n", KFAIL); + if (iqk_info->rxiqk_step == 5) { + dm->rf_calibrate_info.iqk_step++; + iqk_info->rxiqk_step = 1; + if (KFAIL) + RF_DBG(dm, DBG_RF_IQK, "[IQK]S0RXK fail code: %d!!!\n", iqk_info->rxiqk_fail_code[0][RF_PATH_A]); + break; + } + } + iqk_info->kcount++; + break; + } + + if (dm->rf_calibrate_info.iqk_step == 4) { + RF_DBG(dm, DBG_RF_IQK, + "[IQK]==========LOK summary ==========\n"); + RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_LOK_notready = %d\n", + iqk_info->lok_fail[RF_PATH_A]); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]==========IQK summary ==========\n"); + RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_TXIQK_fail = %d\n", + iqk_info->iqk_fail_report[0][RF_PATH_A][TXIQK]); + RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_RXIQK_fail = %d\n", + iqk_info->iqk_fail_report[0][RF_PATH_A][RXIQK]); + RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_TXIQK_retry = %d\n", + iqk_info->retry_count[0][RF_PATH_A][TXIQK]); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]PathA_RXK1_retry = %d, PathA_RXK2_retry = %d\n", + iqk_info->retry_count[0][RF_PATH_A][RXIQK1], + iqk_info->retry_count[0][RF_PATH_A][RXIQK2]); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]PathA_GS1_retry = %d, PathA_GS2_retry = %d\n", + iqk_info->gs_retry_count[0][RF_PATH_A][0], + iqk_info->gs_retry_count[0][RF_PATH_A][1]); + + for (i = 0; i < SS_8821C; i++) { + odm_write_4byte(dm, 0x1b00, 0xf8000008 | i << 1); + odm_write_4byte(dm, 0x1b2c, 0x7); + odm_write_4byte(dm, 0x1bcc, 0x0); + odm_write_4byte(dm, 0x1b38, 0x20000000); + } + break; + } + RF_DBG(dm, DBG_RF_IQK, "[IQK]segmentIQK = %d, Kcount = %d\n", + segment_iqk, iqk_info->kcount); + if (segment_iqk && iqk_info->kcount == kcount_limit) + break; + } +} + +void _iqk_start_iqk_8821c(struct dm_struct *dm, boolean segment_iqk) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u32 tmp; + + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1bb8, 0x00000000); + /*GNT_WL = 1*/ + if (iqk_info->is_btg) { + tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK); + tmp = (tmp & (~BIT(3))) | BIT(0) | BIT(2) | BIT(5); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, tmp); + } else { + tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK); + tmp = ((tmp & (~BIT(3))) & (~BIT(5))) | BIT(0) | BIT(2); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, tmp); + RF_DBG(dm, DBG_RF_IQK, "[IQK]==> RF0x1 = 0x%x\n", + odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK)); + } + _iqk_iqk_by_path_8821c(dm, segment_iqk); +} + +void _iq_calibrate_8821c_init(struct dm_struct *dm) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + u8 i, j, k, m; + static boolean firstrun = true; + + if (firstrun) { + firstrun = false; + RF_DBG(dm, DBG_RF_IQK, + "[IQK]=====>PHY_IQCalibrate_8821C_Init\n"); + + for (i = 0; i < SS_8821C; i++) { + for (j = 0; j < 2; j++) { + iqk_info->lok_fail[i] = true; + iqk_info->iqk_fail[j][i] = true; + iqk_info->iqc_matrix[j][i] = 0x20000000; + } + } + + for (i = 0; i < 2; i++) { + iqk_info->iqk_channel[i] = 0x0; + + for (j = 0; j < SS_8821C; j++) { + iqk_info->lok_idac[i][j] = 0x0; + iqk_info->rxiqk_agc[i][j] = 0x0; + iqk_info->bypass_iqk[i][j] = 0x0; + + for (k = 0; k < 2; k++) { + iqk_info->iqk_fail_report[i][j][k] = true; + for (m = 0; m < 8; m++) { + iqk_info->iqk_cfir_real[i][j][k][m] = 0x0; + iqk_info->iqk_cfir_imag[i][j][k][m] = 0x0; + } + } + + for (k = 0; k < 3; k++) + iqk_info->retry_count[i][j][k] = 0x0; + } + } + } +} + +u8 _txgapk_txpower_compare_8821c(struct dm_struct *dm, u8 path, u32 pw1, + u32 pw2, u32 *pwr_table) +{ + u8 pwr_delta; + u32 temp = 0x0; + temp = (u32)(pw1 / (pw2 / 1000)); + + if (temp < pwr_table[0]) /*<-3.5 dB*/ + pwr_delta = 0x0; + else if (temp < pwr_table[1]) + pwr_delta = 0x1; + else if (temp < pwr_table[2]) + pwr_delta = 0x2; + else if (temp < pwr_table[3]) + pwr_delta = 0x3; + else if (temp < pwr_table[4]) + pwr_delta = 0x4; + else if (temp < pwr_table[5]) + pwr_delta = 0x5; + else if (temp < pwr_table[6]) + pwr_delta = 0x6; + else if (temp < pwr_table[7]) + pwr_delta = 0x7; + else if (temp < pwr_table[8]) + pwr_delta = 0x8; + else if (temp < pwr_table[9]) + pwr_delta = 0x9; + else if (temp < pwr_table[0xa]) + pwr_delta = 0xa; + else if (temp < pwr_table[0xb]) + pwr_delta = 0xb; + else if (temp < pwr_table[0xc]) + pwr_delta = 0xc; + else if (temp < pwr_table[0xd]) + pwr_delta = 0xd; + else if (temp < pwr_table[0xe]) + pwr_delta = 0xe; + else if (temp < pwr_table[0xf]) + pwr_delta = 0xf; + else if (temp < pwr_table[0x10]) + pwr_delta = 0x10; + else if (temp < pwr_table[0x11]) + pwr_delta = 0x11; + else if (temp < pwr_table[0x12]) + pwr_delta = 0x12; + else if (temp < pwr_table[0x13]) + pwr_delta = 0x13; + else if (temp < pwr_table[0x14]) + pwr_delta = 0x14; + else if (temp < pwr_table[0x15]) + pwr_delta = 0x15; + else if (temp < pwr_table[0x16]) + pwr_delta = 0x16; + else if (temp < pwr_table[0x17]) + pwr_delta = 0x17; + else if (temp < pwr_table[0x18]) + pwr_delta = 0x18; + else if (temp < pwr_table[0x19]) + pwr_delta = 0x19; + else + pwr_delta = 0x1a; + + RF_DBG(dm, DBG_RF_IQK, "[TXGAPK] temp =%d, pwr_delta =%x\n", temp, + pwr_delta); + + return pwr_delta; +} + +u32 _txgapk_txgap_compenstion_8821c(struct dm_struct *dm, u8 path, + u32 txgain_0x56, u8 pwr_delta) +{ + u32 new_txgain_0x56; + + /* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 */ + /* -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 (dB)*/ +#if 0 + /* pwr_table[0xf]={89,100,112,125,141,158,177,199,223,251,281,316,354,398,446}*/ +#endif + + switch (pwr_delta) { + case 0x1a: + case 0x19: + case 0x18: + case 0x17: + case 0x16: + case 0x15: + case 0x14: +#if 0 + /* + if ((txgain_0x56 & 0x1f)<=0x1d) + new_txgain_0x56 = txgain_0x56 + 0x2; //< -1.5 ~ -2.5dB + else if ((txgain_0x56 & 0x1f)<= 0x1e) + new_txgain_0x56 = txgain_0x56 + 0x1; + else + new_txgain_0x56 = txgain_0x56; + break; +*/ +#endif + case 0x13: + case 0x12: + if ((txgain_0x56 & 0x1f) <= 0x1e) + new_txgain_0x56 = txgain_0x56 + 0x1;/*< -0.5 ~ -1.5dB*/ + else + new_txgain_0x56 = txgain_0x56; + break; + case 0x11: + case 0x10: + case 0xf: + case 0xe: + case 0xd: + case 0xc: + new_txgain_0x56 = txgain_0x56; /*< -0.5~0.5dB*/ + break; + case 0xb: + case 0xa: + case 0x9: + case 0x8: + case 0x7: + if ((txgain_0x56 & 0x1f) >= 0x01) + new_txgain_0x56 = txgain_0x56 - 0x1; /* >0.5~1.5dB */ + else + new_txgain_0x56 = txgain_0x56; + break; + case 0x6: + case 0x5: + case 0x4: + case 0x3: +#if 0 + /* + if ((txgain_0x56 & 0x1f)>= 0x02) + new_txgain_0x56 = txgain_0x56 - 0x2; //>1.5~2.5dB + else if ((txgain_0x56 & 0x1f)>= 0x01) + new_txgain_0x56 = txgain_0x56 - 0x1; + else + new_txgain_0x56 = txgain_0x56; + break; +*/ +#endif + case 0x2: + case 0x1: + case 0x0: +#if 0 + /* + if ((txgain_0x56 & 0x1f)>= 0x03) + new_txgain_0x56 = txgain_0x56 - 0x3; //>2.5~3.5dB + else if ((txgain_0x56 & 0x1f)>= 0x02) + new_txgain_0x56 = txgain_0x56 - 0x2; + else if ((txgain_0x56 & 0x1f)>= 0x01) + new_txgain_0x56 = txgain_0x56 - 0x1; + else + new_txgain_0x56 = txgain_0x56; + break; +*/ +#endif + default: + new_txgain_0x56 = txgain_0x56; + break; + } + if ((new_txgain_0x56 & 0x1f) < 0x02) + new_txgain_0x56 = (new_txgain_0x56 & 0xffffc) + 0x2; + if ((new_txgain_0x56 & 0x1f) > 0x1d) + new_txgain_0x56 = (new_txgain_0x56 | 0x3) - 0x2; + + return new_txgain_0x56; +} + +void _txgapk_backup_8821c(struct dm_struct *dm, u32 *backup_txgap, + u32 *backup_txgap_reg, u8 txgapk_reg_num) +{ + u32 i; + + for (i = 0; i < txgapk_reg_num; i++) + backup_txgap[i] = odm_read_4byte(dm, backup_txgap_reg[i]); +} +u32 _txgapk_get_rf_tx_index_8821c(struct dm_struct *dm, u8 path, + u32 txgain_index) +{ + u32 rf_backup_reg00, rf_backup_regdf, rf_reg56; + + rf_backup_reg00 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK); + rf_backup_regdf = odm_get_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK); + + odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x08009); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, 0x20000 + txgain_index); + /*ODM_sleep_us(10);*/ + + ODM_delay_us(10); + rf_reg56 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x56, RFREGOFFSETMASK); + + RF_DBG(dm, DBG_RF_IQK, + "[TXGAPK](2) txgain_index =0x%x, rf_reg56=0x%x\n", txgain_index, + rf_reg56); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_backup_reg00); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, rf_backup_regdf); + return rf_reg56; +} + +void _txgapk_restore_8821c(struct dm_struct *dm, u32 *backup_txgap, + u32 *backup_txgap_reg, u8 txgapk_reg_num) +{ + u32 i; + + for (i = 0; i < txgapk_reg_num; i++) + odm_write_4byte(dm, backup_txgap_reg[i], backup_txgap[i]); +} + +void _txgapk_setting_8821c(struct dm_struct *dm, u8 path) +{ + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + /*RF*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x80000); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00024); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0003F); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xCBFCE); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000); + if (iqk_info->is_btg) { + } else { + switch (*dm->band_type) { + case ODM_BAND_2_4G: + break; + case ODM_BAND_5G: + odm_set_rf_reg(dm, RF_PATH_A, RF_0x8f, RFREGOFFSETMASK, 0xA9C00); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x00809); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, 0x4001c); + + odm_write_4byte(dm, 0x1bcc, 0x00000009); /*try the iqk swing*/ + odm_write_4byte(dm, 0x1b20, 0x01040008); + odm_write_4byte(dm, 0x1b24, 0x01040848); + + odm_write_4byte(dm, 0x1b14, 0x00001000); + odm_write_4byte(dm, 0x1b1c, 0x82193d31); + + odm_write_1byte(dm, 0x1b22, 0x04); /*sync with RF0x33[3:0]*/ + odm_write_1byte(dm, 0x1b26, 0x04); /*sync with RF0x33[3:0]*/ + odm_write_1byte(dm, 0x1b2c, 0x03); + odm_write_4byte(dm, 0x1b38, 0x20000000); + odm_write_4byte(dm, 0x1b3c, 0x20000000); + odm_write_4byte(dm, 0xc00, 0x4); + + RF_DBG(dm, DBG_RF_IQK, + "[IQK](1) txgap calibration setting!!!\n"); + + break; + } + } +} + +u32 _txgapk_one_shot_8821c(struct dm_struct *dm_void, u8 path, u32 reg0x56) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean txgap_k_notready = true; + u8 delay_count = 0x0; + u32 txgap_k_tmp1 = 0x1, txgap_k_tmp2 = 0x2; + u8 offset; + u32 reg_1bb8; + u32 rx_dsp_power; + + reg_1bb8 = odm_read_4byte(dm, 0x1bb8); + /*clear the flag*/ + odm_write_1byte(dm, 0x1bd6, 0x0b); + odm_set_bb_reg(dm, R_0x1bfc, BIT(1), 0x0); + txgap_k_notready = true; + delay_count = 0x0; + /* get tx gain*/ + odm_write_1byte(dm, 0x1b2b, 0x00); + odm_write_1byte(dm, 0x1bb8, 0x00); + odm_set_rf_reg(dm, path, RF_0xdf, RFREGOFFSETMASK, 0x00802); + odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00); + odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, reg0x56); + odm_write_4byte(dm, 0x1bb8, 0x00100000); +#if 0 + /*ODM_sleep_us(10);*/ +#endif + + ODM_delay_us(10); + /* one-shot-1*/ + odm_write_4byte(dm, 0x1b34, 0x1); + odm_write_4byte(dm, 0x1b34, 0x0); + +#if 1 + while (txgap_k_notready) { + odm_write_1byte(dm, 0x1bd6, 0x0b); + if ((boolean)odm_get_bb_reg(dm, R_0x1bfc, BIT(1))) + txgap_k_notready = false; + else + txgap_k_notready = true; + + if (txgap_k_notready) { +#if 0 + /*ODM_sleep_us(100);*/ +#endif + ODM_delay_us(100); + delay_count++; + } + + if (delay_count >= 20) { + RF_DBG(dm, DBG_RF_IQK, + "[TXGAPK] (3)txgapktimeout,delay_count=0x%x !!!\n", + delay_count); + txgap_k_notready = false; + break; + } + } +#else + ODM_sleep_ms(1); + if ((boolean)odm_get_bb_reg(dm, R_0x1bfc, BIT(1))) + txgap_k_notready = false; + else + txgap_k_notready = true; + +#endif + + if (!txgap_k_notready) { + odm_write_1byte(dm, 0x1bd6, 0x5); + txgap_k_tmp1 = odm_read_4byte(dm, 0x1bfc) >> 27; + odm_write_1byte(dm, 0x1bd6, 0xe); + txgap_k_tmp2 = odm_read_4byte(dm, 0x1bfc); + + RF_DBG(dm, DBG_RF_IQK, + "[TXGAPK] reg0x56 =0x%x, txgapK_tmp1 =0x%x, txgapK_tmp2 =0x%x!!!\n", + reg0x56, txgap_k_tmp1, txgap_k_tmp2); + + if (txgap_k_tmp1 == 0) + offset = 0x0; + else if (txgap_k_tmp1 < 2) + offset = 0x1; + else if (txgap_k_tmp1 < 4) + offset = 0x2; + else + offset = 0x3; + + if (txgap_k_tmp1 == 0x0) { + rx_dsp_power = txgap_k_tmp2; + } else { + txgap_k_tmp1 = txgap_k_tmp1 << (32 - offset); + txgap_k_tmp2 = txgap_k_tmp2 >> offset; + rx_dsp_power = txgap_k_tmp1 + txgap_k_tmp2; + overflowflag = true; + RF_DBG(dm, DBG_RF_IQK, + "[TXGAPK](3) (1)overflowflag = true, txgapK_tmp1 =0x%x, txgapK_tmp2 =0x%x!!!\n", + txgap_k_tmp1, txgap_k_tmp2); + } + } else { + RF_DBG(dm, DBG_RF_IQK, "[TXGAPK](3) txgapK Fail!!!\n"); + } + + odm_write_4byte(dm, 0x1bb8, reg_1bb8); + + return rx_dsp_power; +} + +void _phy_txgapk_calibrate_8821c(void *dm_void, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 txgain[txgap_k_number] = {0, 0, 0, 0, 0, 0, 0}; + u32 txgain_rf56[txgap_k_number] = {0, 0, 0, 0, 0, 0, 0}; + u8 add_base, txgapk_num = 0x0, psd_delta = 0x0; + u8 i, bandselect = 0x0; + u32 backup_txgap_reg[11] = {0x1b14, 0x1b1c, 0x1b20, 0x1b24, 0x1b28, 0x1b2c, 0x1b38, 0x1b3c, 0x1bd6, 0x1bb8, 0x1bcc}; + u32 backup_txgap[11]; + u8 gain_gap_index[txgap_k_number] = {0x13, 0x10, 0xd, 0xa, 0x7, 0x4, 0x1}; + u32 txgainindex[txgap_k_number] = {0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20}; + u32 tmp1, tmp2, tmp3, tmp4, tmp5; + u8 skip_low_power_index = 0x3; + + s8 psd_single_tone_offset_1db[3][3] = {{-1, 0, 0}, {-2, -1, -1}, {-1, -1, -1} }; /*5G, L,M,H, index 32,26,20*/ + static u32 pwr_table_1db[27] = {590, 630, 668, 707, 749, 794, 841, 891, 944, 1000, 1040, 1096, 1148, 1202, 1258, 1318, + 1380, 1412, 1513, 1584, 1678, 1778, 1888, 1995, 2113, 2387, 2391}; + static u32 pwr_table_3db[27] = {944, 1000, 1059, 1122, 1185, 1258, 1333, 1412, 1496, 1584, 1659, 1737, 1819, 1905, 1995, 2089, + 2187, 2290, 2398, 2511, 2660, 2818, 2985, 3162, 3349, 3548, 3758}; + boolean txgapkdone = false; + u8 txgap_changed = 0x0; + u8 ref_val = 0x0; + + overflowflag = 0; + RF_DBG(dm, DBG_RF_IQK, + "[TXGAPK] (1) *dm->band_width = %x, *dm->channel =%d, *dm->band_type=%x\n", + *dm->band_width, *dm->channel, *dm->band_type); + + if (!(*dm->mp_mode)) + return; + + if (!(*dm->band_type == ODM_BAND_5G)) + return; + + if (*dm->band_width == 0) { +#if 0 + /* return;*/ +#endif + if (*dm->channel < 64) { + bandselect = 0x0; + add_base = 0x0; + } else if (*dm->channel < 153) { + bandselect = 0x1; + add_base = 0x40; +#if 0 + /*else if (*dm->channel ==153){*/ +#endif + } else { + bandselect = 0x2; + add_base = 0x80; + } + } else if (*dm->band_width == 1) { + if (*dm->channel < 102) { + bandselect = 0x0; + add_base = 0x0; + } else if (*dm->channel < 151) { + bandselect = 0x1; + add_base = 0x40; +#if 0 + /*else if (*dm->channel ==151){*/ +#endif + } else { + bandselect = 0x2; + add_base = 0x80; + } + } else if (*dm->band_width == 2) { + /* return;*/ + if (*dm->channel < 106) { + bandselect = 0x0; + add_base = 0x0; + } else if (*dm->channel < 155) { + bandselect = 0x1; + add_base = 0x40; +#if 0 + /*else if (*dm->channel ==155){*/ +#endif + } else { + bandselect = 0x2; + add_base = 0x80; + } + } else { + return; + } + + if (txgap_done[bandselect]) + return; + + /*Step 1*/ + _txgapk_backup_8821c(dm, backup_txgap, backup_txgap_reg, 0xb); + /*step 2*/ + phydm_clear_kfree_to_rf(dm, RF_PATH_A, 1); + + for (i = 0; i < txgap_k_number; i++) { + txgain_rf56[i] = _txgapk_get_rf_tx_index_8821c(dm, RF_PATH_A, gain_gap_index[i]); + txgain[i] = txgain_rf56[i]; + } + + for (i = 0; i < txgap_k_number; i++) { + RF_DBG(dm, DBG_RF_IQK, "[TXGAPK] start txgain1[%x]=0x%x\n", i, + txgain_rf56[i]); + } + + _txgapk_setting_8821c(dm, RF_PATH_A); + + /*step 3*/ + + /*1st*/ + while (!txgapkdone) { + txgapk_num++; + if (txgapk_num > 2) + break; + + for (i = 0; i < txgap_k_number - 1 - skip_low_power_index; i++) { + tmp1 = (txgain[i] & 0x000000e0) >> 5; + tmp2 = (txgain[i + 1] & 0x000000e0) >> 5; + tmp5 = txgain[i + 1]; +#if 0 + //if (tmp1 != tmp2){ +#endif + if (true) { + tmp3 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i] - 2); + tmp4 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i + 1]); + if (overflowflag) + overflowflag = false; +#if 0 + //tmp4 = tmp4>>1; +#endif + + psd_delta = + _txgapk_txpower_compare_8821c(dm, RF_PATH_A, tmp3, tmp4, pwr_table_1db); + + psd_delta = psd_delta + psd_single_tone_offset_1db[bandselect][i]; + RF_DBG(dm, DBG_RF_IQK, + "[TXGAPK] new psd_detla = %x\n", + psd_delta); + + if (psd_delta <= 0xb) + txgap_changed++; + else if (psd_delta <= 0x11) + ; + else + txgap_changed++; + + txgain[i + 1] = + _txgapk_txgap_compenstion_8821c(dm, RF_PATH_A, txgain[i + 1], psd_delta); + } else { + RF_DBG(dm, DBG_RF_IQK, + "[TXGAPK]skip i=%d, txgain[%x]=0x%x\n", + i, i + 1, txgain[i + 1]); + } + } + + /*2nd*/ + + if (txgap_changed > 0x0) { + RF_DBG(dm, DBG_RF_IQK, "[TXGAPK] do 3dB check\n"); + + for (i = 0; i < txgap_k_number - 1 - skip_low_power_index; i++) { + tmp1 = (txgain[i] & 0x000000e0) >> 5; + tmp2 = (txgain[i + 1] & 0x000000e0) >> 5; + + if (tmp1 != tmp2) { + if (i == 0) + tmp3 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i] - 2); + else + tmp3 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i]); + + tmp4 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i + 1]); + + if (overflowflag) { + overflowflag = false; + RF_DBG(dm, DBG_RF_IQK, "[IQK] tmp3= %x, tmp4= %x\n", tmp3, tmp4); + } + if (i == 0) + psd_delta = + _txgapk_txpower_compare_8821c(dm, RF_PATH_A, tmp3, tmp4, pwr_table_1db); + + else + psd_delta = + _txgapk_txpower_compare_8821c(dm, RF_PATH_A, tmp3, tmp4, pwr_table_3db); + + if (psd_delta <= 0xa) + ref_val++; + else if (psd_delta <= 0x12) + ; + else + ref_val++; + } else { + RF_DBG(dm, DBG_RF_IQK, "[TXGAPK]skip i=%d, txgain[%x]=0x%x\n", i, i + 1, txgain[i + 1]); + } + } + + if (ref_val == 0x0) { + txgapkdone = true; + txgap_changed = 0x0; + } else { + /* restore default rf 0x56 */ + for (i = 0; i < txgap_k_number; i++) + txgain[i] = txgain_rf56[i]; + } + + } else { + txgapkdone = true; + } + } + + /*step 7*/ + _txgapk_restore_8821c(dm, backup_txgap, backup_txgap_reg, 0xb); + + /*step 8*/ + RF_DBG(dm, DBG_RF_IQK, + "[TXGAPK]txgapkdone =%x, txgap_changed=0x%x, ref_val =0x%x\n", + txgapkdone, txgap_changed, ref_val); + + if (txgapkdone) { + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00800); + + for (i = 0; i < txgap_k_number; i++) { + odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, txgainindex[i] + add_base); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, txgain[i]); + } + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000); + txgap_done[bandselect] = true; + txgapkdone = false; + } +} + +#if 0 +/* +void +_DPK_BackupReg_8821C( + struct dm_struct* dm, + static u32* DPK_backup, + u32* backup_dpk_reg + ) +{ + + u32 i; + + for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++) + DPK_backup[i] = odm_read_4byte(dm, backup_dpk_reg[i]); + +} +void +_DPK_Restore_8821C( + struct dm_struct* dm, + static u32* DPK_backup, + u32* backup_dpk_reg + ) +{ + u32 i; + for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++) + odm_write_4byte(dm, backup_dpk_reg[i], DPK_backup[i]); +} + +*/ +#endif +void _dpk_toggle_rxagc(struct dm_struct *dm, boolean reset) +{ + /*toggle RXAGC workaround method*/ + u32 tmp1; + tmp1 = odm_read_4byte(dm, 0xc50); + odm_set_bb_reg(dm, R_0xc50, BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x0); +#if 0 + /* ODM_sleep_ms(2);*/ +#endif + ODM_delay_ms(2); + odm_set_bb_reg(dm, R_0xc50, BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x2); +#if 0 + /* ODM_sleep_ms(2);*/ +#endif + ODM_delay_ms(2); + odm_set_bb_reg(dm, R_0xc50, BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x0); + odm_write_4byte(dm, 0xc50, tmp1); +} + +void _dpk_set_gain_scaling(struct dm_struct *dm, u8 path) +{ + u32 tmp1, tmp2, tmp3, tmp4, reg_1bfc; + u32 lut_i = 0x0, lut_q = 0x0, lut_pw = 0x0, lut_pw_avg = 0x0; + u16 gain_scaling = 0x0; + + tmp1 = odm_read_4byte(dm, 0x1b00); + tmp2 = odm_read_4byte(dm, 0x1b08); + tmp3 = odm_read_4byte(dm, 0x1bd4); + tmp4 = odm_read_4byte(dm, 0x1bdc); + + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1b08, 0x00000080); + odm_write_4byte(dm, 0x1bd4, 0x00040001); + odm_write_4byte(dm, 0x1bdc, 0xc0000081); + + reg_1bfc = odm_read_4byte(dm, 0x1bfc); + lut_i = (reg_1bfc & 0x003ff800) >> 11; + lut_q = (reg_1bfc & 0x00007ff); + + if ((lut_i & 0x400) == 0x400) + lut_i = 0x800 - lut_i; + if ((lut_q & 0x400) == 0x400) + lut_q = 0x800 - lut_q; + + lut_pw = lut_i * lut_i + lut_q * lut_q; + lut_pw_avg = (u32)(lut_i + lut_q) >> 1; + gain_scaling = (u16)(0x800000 / lut_pw_avg); + + odm_set_bb_reg(dm, R_0x1b98, 0x0000ffff, gain_scaling); + odm_set_bb_reg(dm, R_0x1b98, 0xffff0000, gain_scaling); + + odm_write_4byte(dm, 0x1b00, tmp1); + odm_write_4byte(dm, 0x1b08, tmp2); + odm_write_4byte(dm, 0x1bd4, tmp3); + odm_write_4byte(dm, 0x1bdc, tmp4); + + RF_DBG(dm, DBG_RF_IQK, + "[IQK] reg_1bfc =0x%x, lut_pw =0x%x, lut_i = 0x%x, lut_q = 0x%x, lut_pw_avg = 0x%x, gain_scaling = 0x%x, 0x1b98 =0x%x!!!\n", + reg_1bfc, lut_pw, lut_i, lut_q, lut_pw_avg, gain_scaling, + odm_read_4byte(dm, 0x1b98)); +} + +void _dpk_set_dpk_pa_scan(struct dm_struct *dm, u8 path) +{ + u32 tmp1, tmp2, reg_1bfc; + u32 pa_scan_i = 0x0, pa_scan_q = 0x0, pa_scan_pw = 0x0; + u32 gainloss_back = 0x0; +#if 0 + /* boolean pa_scan_search_fail = false;*/ +#endif + tmp1 = odm_read_4byte(dm, 0x1bcf); + tmp2 = odm_read_4byte(dm, 0x1bd4); + + odm_write_4byte(dm, 0x1bcf, 0x11); + odm_write_4byte(dm, 0x1bd4, 0x00060000); + + reg_1bfc = odm_read_4byte(dm, 0x1bfc); + odm_write_4byte(dm, 0x1bcf, 0x15); + pa_scan_i = (reg_1bfc & 0xffff0000) >> 16; + pa_scan_q = (reg_1bfc & 0x0000ffff); + + if ((pa_scan_i & 0x8000) == 0x8000) + pa_scan_i = 0x10000 - pa_scan_i; + if ((pa_scan_q & 0x8000) == 0x8000) + pa_scan_q = 0x10000 - pa_scan_q; + + pa_scan_pw = pa_scan_i * pa_scan_i + pa_scan_q * pa_scan_q; + + /*estimated pa_scan_pw*/ +#if 0 + /*0dB => (512^2) * 10^(0/10) = 262144*/ + /*1dB => (512^2) * 10^(1/10) = 330019*/ + /*2dB => (512^2) * 10^(2/10) = 415470*/ + /*3dB => (512^2) * 10^(3/10) = 523046*/ + /*4dB => (512^2) * 10^(4/10) = 658475*/ + /*5dB => (512^2) * 10^(5/10) = 828972*/ + /*6dB => (512^2) * 10^(6/10) = 1043614*/ + /*7dB => (512^2) * 10^(7/10) = 1313832*/ + /*8dB => (512^2) * 10^(0/10) = 1654016*/ + /*9dB => (512^2) * 10^(1/10) = 2082283*/ + /*10dB => (512^2) * 10^(2/10) = 2621440*/ + /*11dB => (512^2) * 10^(3/10) = 3300197*/ + /*12dB => (512^2) * 10^(4/10) = 4154702*/ + /*13dB => (512^2) * 10^(5/10) = 5230460*/ + /*14dB => (512^2) * 10^(6/10) = 6584759*/ + /*15dB => (512^2) * 10^(7/10) = 8289721*/ +#endif + if (pa_scan_pw >= 0x7e7db9) + pa_scan_pw = 0x0f; + else if (pa_scan_pw >= 0x6479b7) + pa_scan_pw = 0x0e; + else if (pa_scan_pw >= 0x4fcf7c) + pa_scan_pw = 0x0d; + else if (pa_scan_pw >= 0x3f654e) + pa_scan_pw = 0x0c; + else if (pa_scan_pw >= 0x325b65) + pa_scan_pw = 0x0b; + else if (pa_scan_pw >= 0x280000) + pa_scan_pw = 0x0a; + else if (pa_scan_pw >= 0x1fc5eb) + pa_scan_pw = 0x09; + else if (pa_scan_pw >= 0x193d00) + pa_scan_pw = 0x8; + else if (pa_scan_pw >= 0x140c28) + pa_scan_pw = 0x7; + else if (pa_scan_pw >= 0xefc9e) + pa_scan_pw = 0x6; + else if (pa_scan_pw >= 0xca62c) + pa_scan_pw = 0x5; + else if (pa_scan_pw > 0xa0c2b) + pa_scan_pw = 0x4; + else if (pa_scan_pw > 0x7fb26) + pa_scan_pw = 0x3; + else if (pa_scan_pw > 0x656ee) + pa_scan_pw = 0x2; + else if (pa_scan_pw > 0x50923) + pa_scan_pw = 0x1; + else /*262144 >= pa_scan_pw*/ + pa_scan_pw = 0x0; + + odm_write_4byte(dm, 0x1bd4, 0x00060001); + gainloss_back = (odm_read_4byte(dm, 0x1bfc) & 0x0000000f); + + if (gainloss_back <= 0xa) + gainloss_back = 0xa - gainloss_back; + + if (gainloss_back > pa_scan_pw + 0x8) + odm_set_rf_reg(dm, path, RF_0x8f, BIT(14) | BIT(13), 0x11); + else if ((pa_scan_pw + 0x8 - gainloss_back) >= 0x6) + odm_set_rf_reg(dm, path, RF_0x8f, BIT(14) | BIT(13), 0x00); + else +#if 0 + /*if (0x6 >= (pa_scan_pw + 0x8 - gainloss_back)> 0x0 )*/ +#endif + odm_set_rf_reg(dm, path, RF_0x8f, BIT(14) | BIT(13), 0x01); + + RF_DBG(dm, DBG_RF_IQK, + "[IQK] reg_1bfc =0x%x, pa_scan_pw =0x%x, gainloss_back = 0x%x, pa_scan_i = 0x%x, pa_scan_q = 0x%x, RF0x8f = 0x%x, !!!\n", + reg_1bfc, pa_scan_pw, gainloss_back, pa_scan_i, pa_scan_q, + odm_get_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK)); + + odm_write_4byte(dm, 0x1bcf, tmp1); + odm_write_4byte(dm, 0x1bd4, tmp2); +} + +void _dpk_disable_bb_dynamic_pwr_threshold(struct dm_struct *dm, boolean flag) +{ + if (flag) /*disable BB dynamic pwr threshold hold*/ + odm_set_bb_reg(dm, R_0x1c74, BIT(31) | BIT(30) | BIT(29) | BIT(28), 0x0); + else + odm_set_bb_reg(dm, R_0x1c74, BIT(31) | BIT(30) | BIT(29) | BIT(28), 0x2); + RF_DBG(dm, DBG_RF_IQK, "[DPK]\nset 0x1c74 = 0x%x\n", + odm_read_4byte(dm, 0x1c74)); +} + +void _dpk_set_dpk_sram_to_10_8821c(struct dm_struct *dm, u8 path) +{ + u32 tmp1, tmp2; + u8 i; + tmp1 = odm_read_4byte(dm, 0x1b00); + tmp2 = odm_read_4byte(dm, 0x1b08); + + for (i = 0; i < 64; i++) + odm_write_4byte(dm, 0x1bdc, 0xd0000001 + (i * 2) + 1); + + for (i = 0; i < 64; i++) + odm_write_4byte(dm, 0x1bdc, 0x90000080 + (i * 2) + 1); + +#if 0 + /* + RF_DBG(dm, DBG_RF_IQK, + "[DPK]return txagc = 0x%x , 1bfc = 0x%x,rf00=0x%x\n", + tmp4, odm_read_4byte(dm, 0x1bfc), + odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK)); +*/ +#endif + odm_write_4byte(dm, 0x1bdc, 0x0); + odm_write_4byte(dm, 0x1b00, tmp1); + odm_write_4byte(dm, 0x1b08, tmp2); +} + +void _dpk_set_bbtxagc_8821c(struct dm_struct *dm, u8 path) +{ + u8 hw_rate, tmp; + + for (hw_rate = 0; hw_rate < 0x53; hw_rate++) { + phydm_write_txagc_1byte_8821c(dm, 0x30, (enum rf_path)0x0, hw_rate); + + tmp = config_phydm_read_txagc_8821c(dm, (enum rf_path)0x0, hw_rate); +#if 0 + /* + RF_DBG(dm, DBG_RF_IQK, + "hw_rate =0x%x, tmp =0x%x \n", hw_rate, tmp); +*/ +#endif + } +} + +u8 _dpk_get_txagcindpk_8821c(struct dm_struct *dm, u8 path) +{ + u32 tmp1, tmp2, tmp3; + u8 tmp4; + tmp1 = odm_read_4byte(dm, 0x1bcc); + odm_set_bb_reg(dm, R_0x1bcc, BIT(26), 0x01); + tmp2 = odm_read_4byte(dm, 0x1bd4); + odm_set_bb_reg(dm, R_0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x0a); + tmp3 = odm_read_4byte(dm, 0x1bfc); + tmp4 = ((u8)odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD)) >> 2; +#if 0 + /* + RF_DBG(dm, DBG_RF_IQK, + "[DPK]return txagc = 0x%x , 1bfc = 0x%x,rf00=0x%x\n", + tmp4, odm_read_4byte(dm, 0x1bfc), + odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK)); +*/ +#endif + odm_write_4byte(dm, 0x1bcc, tmp1); + odm_write_4byte(dm, 0x1bd4, tmp2); + + return tmp4; +} + +void _dpk_ampmcurce_8821c(struct dm_struct *dm, u8 path) +{ + u8 i; + RF_DBG(dm, DBG_RF_IQK, "[DPK] 0x1bcc = 0x%x, 0x1bb8 =0x%x\n", + odm_read_4byte(dm, 0x1bcc), odm_read_4byte(dm, 0x1bb8)); + + odm_write_4byte(dm, 0x1bcc, 0x118f8800); + for (i = 0; i < 8; i++) { + odm_write_4byte(dm, 0x1b90, 0x0101e018 + i); + odm_write_4byte(dm, 0x1bd4, 0x00060000); + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + odm_write_4byte(dm, 0x1bd4, 0x00070000); + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + odm_write_4byte(dm, 0x1bd4, 0x00080000); + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + odm_write_4byte(dm, 0x1bd4, 0x00090000); + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + } + + odm_write_4byte(dm, 0x1b90, 0x0001e018); +} +void _dpk_readsram_8821c(struct dm_struct *dm, u8 path) +{ + /* dbg message*/ + u8 i; + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1b08, 0x00000080); + odm_write_4byte(dm, 0x1bd4, 0x00040001); + + RF_DBG(dm, DBG_RF_IQK, "[DPK] SRAM value!!!\n"); + + for (i = 0; i < 64; i++) { +#if 0 + /*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/ +#endif + odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2); + + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + } + odm_write_4byte(dm, 0x1bd4, 0x00050001); + for (i = 0; i < 64; i++) { +#if 0 + /*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/ +#endif + odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2); + + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + } +#if 0 + /*ODM_sleep_ms(200);*/ +#endif + ODM_delay_ms(200); +#if 0 + /*odm_write_4byte(dm, 0x1b08, 0x00000080);*/ +#endif + odm_write_4byte(dm, 0x1bd4, 0xA0001); + odm_write_4byte(dm, 0x1bdc, 0x00000000); +} + +void _dpk_restore_8821c(struct dm_struct *dm, u8 path) +{ + odm_write_4byte(dm, 0xc60, 0x700B8040); + odm_write_4byte(dm, 0xc60, 0x700B8040); + odm_write_4byte(dm, 0xc60, 0x70146040); + odm_write_4byte(dm, 0xc60, 0x70246040); + odm_write_4byte(dm, 0xc60, 0x70346040); + odm_write_4byte(dm, 0xc60, 0x70446040); + odm_write_4byte(dm, 0xc60, 0x705B2040); + odm_write_4byte(dm, 0xc60, 0x70646040); + odm_write_4byte(dm, 0xc60, 0x707B8040); + odm_write_4byte(dm, 0xc60, 0x708B8040); + odm_write_4byte(dm, 0xc60, 0x709B8040); + odm_write_4byte(dm, 0xc60, 0x70aB8040); + odm_write_4byte(dm, 0xc60, 0x70bB6040); + odm_write_4byte(dm, 0xc60, 0x70c06040); + odm_write_4byte(dm, 0xc60, 0x70d06040); + odm_write_4byte(dm, 0xc60, 0x70eF6040); + odm_write_4byte(dm, 0xc60, 0x70f06040); + + odm_write_4byte(dm, 0xc58, 0xd8020402); + odm_write_4byte(dm, 0xc5c, 0xde000120); + odm_write_4byte(dm, 0xc6c, 0x0000122a); + + odm_write_4byte(dm, 0x808, 0x24028211); +#if 0 + /*odm_write_4byte(dm, 0x810, 0x211042A5);*/ +#endif + odm_write_4byte(dm, 0x90c, 0x13000000); + odm_write_4byte(dm, 0x9a4, 0x80000088); + odm_write_4byte(dm, 0xc94, 0x01000101); + odm_write_4byte(dm, 0x1904, 0x00238000); + odm_write_4byte(dm, 0x1904, 0x00228000); + odm_write_4byte(dm, 0xC00, 0x00000007); +} + +void _dpk_clear_sram_8821c(struct dm_struct *dm, u8 path) +{ + u8 i; + + /* write pwsf*/ + /*S3*/ + odm_write_4byte(dm, 0x1bdc, 0x40caffe1); + odm_write_4byte(dm, 0x1bdc, 0x4080a1e3); + odm_write_4byte(dm, 0x1bdc, 0x405165e5); + odm_write_4byte(dm, 0x1bdc, 0x403340e7); + odm_write_4byte(dm, 0x1bdc, 0x402028e9); + odm_write_4byte(dm, 0x1bdc, 0x401419eb); + odm_write_4byte(dm, 0x1bdc, 0x400d10ed); + odm_write_4byte(dm, 0x1bdc, 0x40080aef); + + odm_write_4byte(dm, 0x1bdc, 0x400506f1); + odm_write_4byte(dm, 0x1bdc, 0x400304f3); + odm_write_4byte(dm, 0x1bdc, 0x400203f5); + odm_write_4byte(dm, 0x1bdc, 0x400102f7); + odm_write_4byte(dm, 0x1bdc, 0x400101f9); + odm_write_4byte(dm, 0x1bdc, 0x400101fb); + odm_write_4byte(dm, 0x1bdc, 0x400101fd); + odm_write_4byte(dm, 0x1bdc, 0x400101ff); + /*S0*/ + odm_write_4byte(dm, 0x1bdc, 0x40caff81); + odm_write_4byte(dm, 0x1bdc, 0x4080a183); + odm_write_4byte(dm, 0x1bdc, 0x40516585); + odm_write_4byte(dm, 0x1bdc, 0x40334087); + odm_write_4byte(dm, 0x1bdc, 0x40202889); + odm_write_4byte(dm, 0x1bdc, 0x4014198b); + odm_write_4byte(dm, 0x1bdc, 0x400d108d); + odm_write_4byte(dm, 0x1bdc, 0x40080a8f); + odm_write_4byte(dm, 0x1bdc, 0x40050691); + odm_write_4byte(dm, 0x1bdc, 0x40030493); + odm_write_4byte(dm, 0x1bdc, 0x40020395); + odm_write_4byte(dm, 0x1bdc, 0x40010297); + odm_write_4byte(dm, 0x1bdc, 0x40010199); + odm_write_4byte(dm, 0x1bdc, 0x4001019b); + odm_write_4byte(dm, 0x1bdc, 0x4001019d); + odm_write_4byte(dm, 0x1bdc, 0x4001019f); + + odm_write_4byte(dm, 0x1bdc, 0x00000000); + + /*clear sram even*/ + for (i = 0; i < 0x40; i++) + odm_write_4byte(dm, 0x1bdc, 0xd0000000 + ((i * 2) + 1)); + /*clear sram odd*/ + for (i = 0; i < 0x40; i++) + odm_write_4byte(dm, 0x1bdc, 0x90000080 + ((i * 2) + 1)); + + odm_write_4byte(dm, 0x1bdc, 0x0); + RF_DBG(dm, DBG_RF_IQK, "[DPK]==========write pwsf and clear sram/n"); +} + +void _dpk_setting_8821c(struct dm_struct *dm, u8 path) +{ + RF_DBG(dm, DBG_RF_IQK, + "[DPK]==========Start the DPD setting Initilaize/n"); + /*AFE setting*/ + odm_write_4byte(dm, 0xc60, 0x50000000); + odm_write_4byte(dm, 0xc60, 0x700F0040); + odm_write_4byte(dm, 0xc5c, 0xd1000120); + odm_write_4byte(dm, 0xc58, 0xd8000402); + odm_write_4byte(dm, 0xc6c, 0x00000a15); + odm_write_4byte(dm, 0xc00, 0x00000004); +#if 0 + /*_iqk_bb_reset_8821c(dm);*/ +#endif + odm_write_4byte(dm, 0xe5c, 0xD1000120); + odm_write_4byte(dm, 0xc6c, 0x00000A15); + odm_write_4byte(dm, 0xe6c, 0x00000A15); + odm_write_4byte(dm, 0x808, 0x2D028200); +#if 0 + /*odm_write_4byte(dm, 0x810, 0x211042A5);*/ +#endif + odm_write_4byte(dm, 0x8f4, 0x00d80fb1); + odm_write_4byte(dm, 0x90c, 0x0B00C000); + odm_write_4byte(dm, 0x9a4, 0x00000080); + odm_write_4byte(dm, 0xc94, 0x01000101); + odm_write_4byte(dm, 0xe94, 0x01000101); + odm_write_4byte(dm, 0xe5c, 0xD1000120); + odm_write_4byte(dm, 0xc6c, 0x00000A15); + odm_write_4byte(dm, 0xe6c, 0x00000A15); + odm_write_4byte(dm, 0x1904, 0x00020000); + /*path A*/ + /*RF*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x80000); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00024); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0003F); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xCBFCE); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000); + /*AGC boundary selection*/ + odm_write_4byte(dm, 0x1bbc, 0x0001abf6); + odm_write_4byte(dm, 0x1b90, 0x0001e018); + odm_write_4byte(dm, 0x1bb8, 0x000fffff); + odm_write_4byte(dm, 0x1bc8, 0x000c55aa); +#if 0 + /*odm_write_4byte(dm, 0x1bcc, 0x11978200);*/ +#endif + odm_write_4byte(dm, 0x1bcc, 0x11978800); +#if 0 + /*odm_write_4byte(dm, 0xcb0, 0x77775747);*/ + /*odm_write_4byte(dm, 0xcb4, 0x100000f7);*/ + /*odm_write_4byte(dm, 0xcb4, 0x10000007);*/ + /*odm_write_4byte(dm, 0xcbc, 0x0);*/ +#endif +} + +void _dpk_dynamic_bias_8821c(struct dm_struct *dm, u8 path, u8 dynamicbias) +{ + u32 tmp; + tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK); + tmp = tmp | BIT(8); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, tmp); + if ((*dm->band_type == ODM_BAND_5G) && (*dm->band_width == 1)) + odm_set_rf_reg(dm, path, RF_0x61, BIT(7) | BIT(6) | BIT(5) | BIT(4), dynamicbias); + if ((*dm->band_type == ODM_BAND_5G) && (*dm->band_width == 2)) + odm_set_rf_reg(dm, path, RF_0x61, BIT(7) | BIT(6) | BIT(5) | BIT(4), dynamicbias); + tmp = tmp & (~BIT(8)); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, tmp); + RF_DBG(dm, DBG_RF_IQK, "[DPK]Set DynamicBias 0xdf=0x%x, 0x61=0x%x\n", + odm_get_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK), + odm_get_rf_reg(dm, RF_PATH_A, RF_0x61, RFREGOFFSETMASK)); +} + +void _dpk_boundary_selection_8821c(struct dm_struct *dm, u8 path) +{ + u8 tmp_pad, compared_pad, compared_txbb; + u32 rf_backup_reg00; + u8 i = 0; + u8 j = 1; + u32 boundaryselect = 0; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + RF_DBG(dm, DBG_RF_IQK, "[DPK]Start the DPD boundary selection\n"); + rf_backup_reg00 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x00, RFREGOFFSETMASK); + tmp_pad = 0; + compared_pad = 0; + boundaryselect = 0; +#if dpk_forcein_sram4 + for (i = 0x1f; i > 0x0; i--) { /*i=tx index*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, 0x20000 + i); + + if (iqk_info->is_btg) { + compared_pad = (u8)((0x1c000 & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x78, RFREGOFFSETMASK)) >> 14); + compared_txbb = (u8)((0x07C00 & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x5c, RFREGOFFSETMASK)) >> 10); + } else { + compared_pad = (u8)((0xe0 & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x56, RFREGOFFSETMASK)) >> 5); + compared_txbb = (u8)((0x1f & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x56, RFREGOFFSETMASK))); + } + if (i == 0x1f) { + /*boundaryselect = compared_txbb;*/ + boundaryselect = 0x1f; + tmp_pad = compared_pad; + } + if (compared_pad < tmp_pad) { + boundaryselect = boundaryselect + (i << (j * 5)); + tmp_pad = compared_pad; + j++; + } + + if (j >= 4) + break; + } + +#else + boundaryselect = 0x0; +#endif + odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_backup_reg00); + odm_write_4byte(dm, 0x1bbc, boundaryselect); +} + +u8 _dpk_get_dpk_tx_agc_8821c(struct dm_struct *dm, u8 path) +{ + u8 tx_agc_init_value = 0x1f; /* DPK TXAGC value*/ + u32 rf_reg00 = 0x0; + u8 gainloss = 0x1; + u8 best_tx_agc, txagcindpk = 0x0; + u8 tmp; + boolean fail = true; + u32 IQK_CMD = 0xf8000d18; + + /* rf_reg00 = 0x40000 + tx_agc_init_value; set TXAGC value */ + if (*dm->band_type == ODM_BAND_5G) { + tx_agc_init_value = 0x1c; + rf_reg00 = 0x40000 + tx_agc_init_value; /* set TXAGC value*/ +#if 0 + /*rf_reg00 = 0x54000 + tx_agc_init_value;*/ /* set TXAGC value*/ +#endif + odm_write_4byte(dm, 0x1bc8, 0x000c55aa); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x8f, RFREGOFFSETMASK, 0xa9c00); + } else { + tx_agc_init_value = 0x17; + rf_reg00 = 0x44000 + tx_agc_init_value; /* set TXAGC value*/ +#if 0 + /*rf_reg00 = 0x54000 + tx_agc_init_value; */ /* set TXAGC value*/ +#endif + odm_write_4byte(dm, 0x1bc8, 0x000c44aa); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x8f, RFREGOFFSETMASK, 0xaec00); + } + odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_reg00); + odm_set_bb_reg(dm, R_0x1b8c, BIT(15) | BIT(14) | BIT(13), gainloss); + odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5); + + _dpk_set_bbtxagc_8821c(dm, RF_PATH_A); + txagcindpk = _dpk_get_txagcindpk_8821c(dm, RF_PATH_A); + + if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0) + odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0); + ; +#if 0 + /*ODM_sleep_ms(1);*/ +#endif + ODM_delay_ms(1); + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 1); + + fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD); + + odm_write_4byte(dm, 0x1b90, 0x0001e018); +#if 0 + /* + RF_DBG(dm, DBG_RF_IQK, + "[DPK]rf_reg00 =0x%x, 0x8F =0x%x, txagcindpk =0x%x\n", + odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK), + odm_get_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK),txagcindpk); +*/ +#endif + + odm_write_4byte(dm, 0x1bd4, 0x60001); + tmp = (u8)odm_read_4byte(dm, 0x1bfc); + best_tx_agc = tx_agc_init_value - (0xa - tmp); +#if 0 +/* + RF_DBG(dm, DBG_RF_IQK, + "[DPK](2), 0x1b8c =0x%x, rf_reg00 = 0x%x, 0x1b00 = 0x%x, 0x1bfc = 0x%x, 0x1bd4 = 0x%x,best_tx_agc =0x%x, 0x1bfc[7:0] =0x%x\n", + odm_read_4byte(dm, 0x1b8c), + odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK), + odm_read_4byte(dm, 0x1b00), + odm_read_4byte(dm, 0x1bfc), odm_read_4byte(dm, 0x1bd4), + best_tx_agc, tmp); +*/ +#endif +/* dbg message*/ +#if 0 + + RF_DBG(dm, DBG_RF_IQK, "[DPK] 0x1bcc = 0x%x, 0x1bb8 =0x%x\n", + odm_read_4byte(dm, 0x1bcc), odm_read_4byte(dm, 0x1bb8)); + + odm_write_4byte(dm, 0x1bcc, 0x118f8800); + for (i = 0 ; i < 8; i++) { + odm_write_4byte(dm, 0x1b90, 0x0101e018 + i); + odm_write_4byte(dm, 0x1bd4, 0x00060000); + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + odm_write_4byte(dm, 0x1bd4, 0x00070000); + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + odm_write_4byte(dm, 0x1bd4, 0x00080000); + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + odm_write_4byte(dm, 0x1bd4, 0x00090000); + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + } + + odm_write_4byte(dm, 0x1b90, 0x0001e018); + +#endif + return best_tx_agc; +} + +boolean +_dpk_enable_dpk_8821c(struct dm_struct *dm, u8 path, u8 best_tx_agc) +{ + u32 rf_reg00 = 0x0; + boolean fail = true; + u32 IQK_CMD = 0xf8000e18; + + if (*dm->band_type == ODM_BAND_5G) + rf_reg00 = 0x40000 + best_tx_agc; /* set TXAGC value*/ + else + rf_reg00 = 0x44000 + best_tx_agc; /* set TXAGC value*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_reg00); + _dpk_set_dpk_pa_scan(dm, RF_PATH_A); + + /*ODM_sleep_ms(1);*/ + ODM_delay_ms(1); + odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1); + odm_write_4byte(dm, 0x8f8, 0x41400080); + + if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0) + odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0); + + /*ODM_sleep_ms(1);*/ + ODM_delay_ms(1); + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 1); + + odm_write_4byte(dm, 0x1b90, 0x0001e018); + odm_write_4byte(dm, 0x1bd4, 0xA0001); + fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD); +#if 0 +/* + RF_DBG(dm, DBG_RF_IQK, + "[DPK] (3) 0x1b0b = 0x%x, 0x1bc8 = 0x%x, rf_reg00 = 0x%x, ,0x1bfc = 0x%x, 0x1b90=0x%x, 0x1b94=0x%x\n", + odm_read_1byte(dm, 0x1b0b), odm_read_4byte(dm, 0x1bc8), odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK), + odm_read_4byte(dm, 0x1bfc), odm_read_4byte(dm, 0x1b90), odm_read_4byte(dm, 0x1b94)); +*/ +#endif +#if 0 /* dbg message*/ + u8 delay_count = 0x0; + u8 i; + u32 tmp; + odm_write_4byte(dm, 0x1b00, 0xf8000008); + odm_write_4byte(dm, 0x1b08, 0x00000080); + odm_write_4byte(dm, 0x1bd4, 0x00040001); + + RF_DBG(dm, DBG_RF_IQK, "[DPK] SRAM value!!!\n"); + + for (i = 0 ; i < 64; i++) { + /*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/ + odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2); + + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + } + odm_write_4byte(dm, 0x1bd4, 0x00050001); + for (i = 0 ; i < 64; i++) { + /*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/ + odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2); + + RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc)); + } + + /*odm_write_4byte(dm, 0x1b08, 0x00000080);*/ + odm_write_4byte(dm, 0x1bd4, 0xA0001); + odm_write_4byte(dm, 0x1bdc, 0x00000000); +#endif + return fail; +} + +boolean +_dpk_enable_dpd_8821c(struct dm_struct *dm, u8 path, u8 best_tx_agc) +{ + boolean fail = true; + u8 offset = 0x0; + u32 IQK_CMD = 0xf8000f18; + u8 external_pswf_gain; + boolean gain_scaling_enable = false; + + odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1); + odm_write_4byte(dm, 0x8f8, 0x41400080); + if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0) + odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0); + /*ODM_sleep_ms(1);*/ + ODM_delay_ms(1); + odm_write_4byte(dm, 0x1b00, IQK_CMD); + odm_write_4byte(dm, 0x1b00, IQK_CMD + 1); + fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD); + + odm_write_4byte(dm, 0x1b90, 0x0001e018); + odm_write_4byte(dm, 0x1bd4, 0xA0001); + + if (!fail) { + odm_write_4byte(dm, 0x1bcf, 0x19); + odm_write_4byte(dm, 0x1bdc, 0x0); + /*add 2db extrnal for compensate performnace, the reason is unknown*/ + external_pswf_gain = 0x2; + best_tx_agc = best_tx_agc + external_pswf_gain; + + if (best_tx_agc >= 0x19) + offset = best_tx_agc - 0x19; + else + offset = 0x20 - (0x19 - best_tx_agc); + odm_set_bb_reg(dm, R_0x1bd0, BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), offset); + if (gain_scaling_enable) + _dpk_set_gain_scaling(dm, RF_PATH_A); + else + odm_write_4byte(dm, 0x1b98, 0x4c004c00); + + } else { + RF_DBG(dm, DBG_RF_IQK, + "[DPK](4)0x1b08 =%x, 0x1bc8 = 0x%x,0x1bfc = 0x%x, ,0x1bd0 = 0x%x, offset =%x, 1bcc =%x\n", + odm_read_4byte(dm, 0x1b08), odm_read_4byte(dm, 0x1bc8), + odm_read_1byte(dm, 0x1bfc), odm_read_4byte(dm, 0x1bd0), + offset, odm_read_4byte(dm, 0x1bcc)); + } + + return fail; +} + +void _phy_dpd_calibrate_8821c(struct dm_struct *dm, boolean reset) +{ + u32 backup_dpdbb[3]; + u8 best_tx_agc = 0x1c; + u32 MAC_backup[MAC_REG_NUM_8821C], RF_backup[RF_REG_NUM_8821C][1]; + u32 backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518}; + u32 BB_backup[DPK_BB_REG_NUM_8821C]; + u32 backup_bb_reg[DPK_BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0x1990, 0x9a4, 0xa04, 0xc58, 0xc5c, 0xe58, 0xe5c, 0xc6c, 0xe6c, 0x90c, 0xc94, 0xe94, 0x1904, 0xcb0, 0xcb4, 0xcbc, 0xc00}; + u32 backup_rf_reg[RF_REG_NUM_8821C] = {0xdf, 0xde, 0x8f, 0x0, 0x1}; + u8 i; + u32 backup_dpk_reg[3] = {0x1bd0, 0x1b98, 0x1bbc}; + + struct dm_iqk_info *iqk_info = &dm->IQK_info; + iqk_info->is_btg = (boolean)odm_get_bb_reg(dm, R_0xcb8, BIT(16)); + if (!(*dm->mp_mode)) + if (_iqk_reload_iqk_8821c(dm, reset)) + return; + if (!(*dm->band_type == ODM_BAND_5G)) + return; + + RF_DBG(dm, DBG_RF_IQK, "[DPK]==========DPK strat!!!!!==========\n"); + RF_DBG(dm, DBG_RF_IQK, + "[DPK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n", + (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width, + dm->ext_pa, dm->ext_pa_5g); + _iqk_backup_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, DPK_BB_REG_NUM_8821C); + _iqk_afe_setting_8821c(dm, true); + _iqk_backup_rf_8821c(dm, RF_backup, backup_rf_reg); + + if (iqk_info->is_btg) { + } else { + if (*dm->band_type == ODM_BAND_2_4G) + odm_set_bb_reg(dm, R_0xcb8, BIT(8), 0x1); + else + odm_set_bb_reg(dm, R_0xcb8, BIT(8), 0x0); + } + + /*backup 0x1b2c, 1b38,0x1b3c*/ + backup_dpdbb[0] = odm_read_4byte(dm, 0x1b2c); + backup_dpdbb[1] = odm_read_4byte(dm, 0x1b38); + backup_dpdbb[2] = odm_read_4byte(dm, 0x1b3c); + RF_DBG(dm, DBG_RF_IQK, "[DPK]In DPD Process(1), Backup\n"); + + /*PDK Init Register setting*/ + _dpk_clear_sram_8821c(dm, RF_PATH_A); + _dpk_setting_8821c(dm, RF_PATH_A); + _dpk_boundary_selection_8821c(dm, RF_PATH_A); + odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5); + /* Get the best TXAGC*/ + + best_tx_agc = _dpk_get_dpk_tx_agc_8821c(dm, RF_PATH_A); +#if 0 + /*ODM_sleep_ms(2);*/ +#endif + + ODM_delay_ms(2); + RF_DBG(dm, DBG_RF_IQK, "[DPK]In DPD Process(2), Best TXAGC = 0x%x\n", + best_tx_agc); + + if (_dpk_enable_dpk_8821c(dm, RF_PATH_A, best_tx_agc)) { + RF_DBG(dm, DBG_RF_IQK, + "[DPK]In DPD Process(3), DPK process is Fail\n"); + } +#if 0 + /*ODM_sleep_ms(2);*/ +#endif + ODM_delay_ms(2); + if (_dpk_enable_dpd_8821c(dm, RF_PATH_A, best_tx_agc)) { + RF_DBG(dm, DBG_RF_IQK, + "[DPK]In DPD Process(4), DPD process is Fail\n"); + } + /* restore IQK */ + iqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK); + _iqk_reload_iqk_setting_8821c(dm, 0, 2); + _iqk_fill_iqk_report_8821c(dm, 0); +#if 0 + /* + RF_DBG(dm, DBG_RF_IQK, + "[DPK]reload IQK result before, iqk_info->rf_reg18=0x%x, iqk_info->iqk_channel[0]=0x%x, iqk_info->iqk_channel[1]=0x%x!!!!\n", + iqk_info->rf_reg18, iqk_info->iqk_channel[0], iqk_info->iqk_channel[1]); + */ +#endif + + /* Restore setup */ +#if 0 + /*_dpk_readsram_8821c(dm, RF_PATH_A);*/ +#endif + _dpk_restore_8821c(dm, RF_PATH_A); + odm_set_bb_reg(dm, R_0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5); + odm_set_bb_reg(dm, R_0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x1b00, BIT(2) | BIT(1), 0x0); + odm_set_bb_reg(dm, R_0x1b08, BIT(6) | BIT(5), 0x2); + + odm_write_4byte(dm, 0x1b2c, backup_dpdbb[0]); + odm_write_4byte(dm, 0x1b38, backup_dpdbb[1]); + odm_write_4byte(dm, 0x1b3c, backup_dpdbb[2]); + /*enable DPK*/ + odm_set_bb_reg(dm, R_0x1b2c, BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x5); +/*enable boundary condition*/ +#if dpk_forcein_sram4 /* disable : froce in sram4*/ + odm_set_bb_reg(dm, R_0x1bcc, BIT(27), 0x1); +#endif + odm_write_4byte(dm, 0x1bcc, 0x11868800); + RF_DBG(dm, DBG_RF_IQK, "[DPK]In DPD Process(5), Restore\n"); + _iqk_restore_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, DPK_BB_REG_NUM_8821C); + _iqk_afe_setting_8821c(dm, false); + _iqk_restore_rf_8821c(dm, backup_rf_reg, RF_backup); + /*toggle dynamic_pwr_threshold*/ + + /* backup the DPK current result*/ + for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++) + dpk_result[i] = odm_read_4byte(dm, backup_dpk_reg[i]); + + RF_DBG(dm, DBG_RF_IQK, + "[DPK]the DPD calibration Process Finish (6), 0x1bd0 = 0x%x, 0x1b98 = 0x%x, 0x1bbc0= 0x%x\n", + dpk_result[0], dpk_result[1], dpk_result[2]); +} + +u32 _iqk_tximr_selfcheck_8821c(void *dm_void, u8 tone_index, u8 path) +{ + u32 tx_ini_power_H[2], tx_ini_power_L[2]; + u32 tmp1, tmp2, tmp3, tmp4, tmp5; + u32 IQK_CMD; + u32 tximr = 0x0; + u8 i; + + struct dm_struct *dm = (struct dm_struct *)dm_void; + /*backup*/ + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(dm, 0x1bc8, 0x80000000); + odm_write_4byte(dm, 0x8f8, 0x41400080); + tmp1 = odm_read_4byte(dm, 0x1b0c); + tmp2 = odm_read_4byte(dm, 0x1b14); + tmp3 = odm_read_4byte(dm, 0x1b1c); + tmp4 = odm_read_4byte(dm, 0x1b20); + tmp5 = odm_read_4byte(dm, 0x1b24); + /*setup*/ + odm_write_4byte(dm, 0x1b0c, 0x00003000); + odm_write_4byte(dm, 0x1b1c, 0xA2193C32); + odm_write_1byte(dm, 0x1b15, 0x00); + odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008)); + odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060008)); + odm_write_4byte(dm, 0x1b2c, 0x07); + odm_write_4byte(dm, 0x1b38, 0x20000000); + odm_write_4byte(dm, 0x1b3c, 0x20000000); + /* ======derive pwr1========*/ + for (i = 0; i < 2; i++) { + if (i == 0) + odm_write_4byte(dm, 0x1bcc, 0x0f); + else + odm_write_4byte(dm, 0x1bcc, 0x09); + /* One Shot*/ + IQK_CMD = 0x00000800; + odm_write_4byte(dm, 0x1b34, IQK_CMD + 1); + odm_write_4byte(dm, 0x1b34, IQK_CMD); + ODM_delay_ms(1); + odm_write_4byte(dm, 0x1bd4, 0x00040001); + tx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc); + odm_write_4byte(dm, 0x1bd4, 0x000C0001); + tx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc); + } + /*restore*/ + odm_write_4byte(dm, 0x1b0c, tmp1); + odm_write_4byte(dm, 0x1b14, tmp2); + odm_write_4byte(dm, 0x1b1c, tmp3); + odm_write_4byte(dm, 0x1b20, tmp4); + odm_write_4byte(dm, 0x1b24, tmp5); + + if (tx_ini_power_H[1] == tx_ini_power_H[0]) + tximr = (3 * (halrf_psd_log2base(tx_ini_power_L[0] << 2) - halrf_psd_log2base(tx_ini_power_L[1]))) / 100; + else + tximr = 0; + return tximr; +} + +u32 _iqk_rximr_selfcheck_8821c(void *dm_void, u8 tone_index, u8 path, + u32 tmp1b38) +{ + u32 rx_ini_power_H[2], rx_ini_power_L[2]; /*[0]: psd tone; [1]: image tone*/ + u32 tmp1, tmp2, tmp3, tmp4, tmp5; + u32 IQK_CMD, tmp1bcc; + u8 i; + u32 rximr = 0x0; + + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*backup*/ + odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1); + tmp1 = odm_read_4byte(dm, 0x1b0c); + tmp2 = odm_read_4byte(dm, 0x1b14); + tmp3 = odm_read_4byte(dm, 0x1b1c); + tmp4 = odm_read_4byte(dm, 0x1b20); + tmp5 = odm_read_4byte(dm, 0x1b24); + + tmp1bcc = (odm_read_4byte(dm, 0x1be8) & 0x0000ff00) >> 8; + odm_write_4byte(dm, 0x1b0c, 0x00001000); + odm_write_1byte(dm, 0x1b15, 0x00); + odm_write_4byte(dm, 0x1b1c, 0x82193d31); + odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008)); + odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060048)); + odm_write_4byte(dm, 0x1b2c, 0x07); +#if 0 + //odm_write_4byte(dm, 0x1b38, iqk_info->rxk1_tmp1b38[path][(tone_index&0xff0)>>4]); +#endif + odm_write_4byte(dm, 0x1b38, tmp1b38); + + odm_write_4byte(dm, 0x1b3c, 0x20000000); + odm_write_4byte(dm, 0x1bcc, tmp1bcc); + for (i = 0; i < 2; i++) { + if (i == 0) + odm_write_4byte(dm, 0x1b1c, 0x82193d31); + else + odm_write_4byte(dm, 0x1b1c, 0xA2193d31); + IQK_CMD = 0x00000800; + odm_write_4byte(dm, 0x1b34, IQK_CMD + 1); + odm_write_4byte(dm, 0x1b34, IQK_CMD); + ODM_delay_us(2000); + odm_write_1byte(dm, 0x1bd6, 0xb); +#if 0 + /*if ((boolean)odm_get_bb_reg(dm, R_0x1bfc, BIT(1))){*/ +#endif + if (1) { + odm_write_1byte(dm, 0x1bd6, 0x5); + rx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc); + odm_write_1byte(dm, 0x1bd6, 0xe); + rx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc); + } else { + rx_ini_power_H[i] = 0x0; + rx_ini_power_L[i] = 0x0; + } + } + /*restore*/ + odm_write_4byte(dm, 0x1b0c, tmp1); + odm_write_4byte(dm, 0x1b14, tmp2); + odm_write_4byte(dm, 0x1b1c, tmp3); + odm_write_4byte(dm, 0x1b20, tmp4); + odm_write_4byte(dm, 0x1b24, tmp5); + + for (i = 0; i < 2; i++) + rx_ini_power_H[i] = (rx_ini_power_H[i] & 0xf8000000) >> 27; + + if (rx_ini_power_H[0] != rx_ini_power_H[1]) + switch (rx_ini_power_H[0]) { + case 1: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 1) | 0x80000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 1; + break; + case 2: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 2) | 0x80000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 2; + break; + case 3: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 2) | 0xc0000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 2; + break; + case 4: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0x80000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3; + break; + case 5: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xa0000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3; + break; + case 6: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xc0000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3; + break; + case 7: + rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xe0000000); + rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3; + break; + default: + break; + } + rximr = (u32)(3 * ((halrf_psd_log2base(rx_ini_power_L[0] / 100) - halrf_psd_log2base(rx_ini_power_L[1] / 100))) / 100); +#if 0 + /* + RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x, 0x%x, 0x%x, 0x%x,0x%x, tone_index=%x, rximr= %d\n", + (path == 0) ? "PATH A RXIMR ": "PATH B RXIMR", + rx_ini_power_H[0], rx_ini_power_L[0], rx_ini_power_H[1], rx_ini_power_L[1], tmp1bcc, tone_index, rximr); +*/ +#endif + return rximr; +} + +void _iqk_start_imr_test_8821c(void *dm_void, u8 path) +{ + u8 imr_limit, i, tone_index; + u32 tmp; + boolean KFAIL; + u32 rxk1_tmp1b38[2][15]; + u32 imr_result[2]; + + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*TX IMR*/ + if (*dm->band_width == 2) + imr_limit = 0xe; + else if (*dm->band_width == 1) + imr_limit = 0x7; + else + imr_limit = 0x3; + + _iqk_txk_setting_8821c(dm, RF_PATH_A); + KFAIL = _iqk_one_shot_8821c(dm, RF_PATH_A, TXIQK); + for (i = 0x0; i <= imr_limit; i++) { + tone_index = (u8)(0x08 | i << 4); + imr_result[RF_PATH_A] = _iqk_tximr_selfcheck_8821c(dm, tone_index, RF_PATH_A); + RF_DBG(dm, DBG_RF_IQK, "[IQK]toneindex = %x, TXIMR = %d\n", + tone_index, imr_result[RF_PATH_A]); + } + RF_DBG(dm, DBG_RF_IQK, "\n"); + /*RX IMR*/ + /*get the rxk1 tone index 0x1b38 setting*/ + _iqk_rxk1setting_8821c(dm, path); + tmp = odm_read_4byte(dm, 0x1b1c); + for (path = 0; path < SS_8821C; path++) { + for (i = 0; i <= imr_limit; i++) { + tone_index = (u8)(0x08 | i << 4); + KFAIL = _iqk_rx_iqk_gain_search_fail_by_toneindex_8821c(dm, path, RXIQK1, tone_index); + if (!KFAIL) { + odm_write_4byte(dm, 0x1b1c, 0xa2193c32); + odm_write_4byte(dm, 0x1b14, 0xe5); + odm_write_4byte(dm, 0x1b14, 0x0); + rxk1_tmp1b38[path][i] = odm_read_4byte(dm, 0x1b38); + } else { + rxk1_tmp1b38[path][i] = 0x0; + } + } + } + _iqk_rxk2setting_8821c(dm, path, true); + for (path = 0; path < SS_8821C; path++) { + for (i = 0x0; i <= imr_limit; i++) { + tone_index = (u8)(0x08 | i << 4); + imr_result[RF_PATH_A] = _iqk_rximr_selfcheck_8821c(dm, tone_index, RF_PATH_A, rxk1_tmp1b38[path][i]); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]toneindex = %x, RXIMR = %d\n", tone_index, + imr_result[RF_PATH_A]); + } + } + odm_write_4byte(dm, 0x1b1c, tmp); + odm_write_4byte(dm, 0x1b38, 0x20000000); +} + +void _phy_iq_calibrate_8821c(struct dm_struct *dm, boolean reset, + boolean segment_iqk, boolean do_imr_test) +{ + u32 MAC_backup[MAC_REG_NUM_8821C], BB_backup[BB_REG_NUM_8821C]; + u32 RF_backup[RF_REG_NUM_8821C][1]; + u32 backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518}; + u32 backup_bb_reg[BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0, + 0xcb4, 0xcbc, 0x1990, + 0x9a4, 0xa04, 0x838}; + u32 backup_rf_reg[RF_REG_NUM_8821C] = {0xdf, 0xde, 0x8f, 0x0, 0x1}; + boolean is_mp = false; + + struct dm_iqk_info *iqk_info = &dm->IQK_info; + + if (*dm->mp_mode) + is_mp = true; + else if (dm->is_linked) + segment_iqk = false; + iqk_info->is_btg = (boolean)odm_get_bb_reg(dm, R_0xcb8, BIT(16)); + + if (!is_mp) + if (_iqk_reload_iqk_8821c(dm, reset)) + return; + if (!do_imr_test) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]==========IQK strat!!!!!==========\n"); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n", + (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width, + dm->ext_pa, dm->ext_pa_5g); + RF_DBG(dm, DBG_RF_IQK, "[IQK]Interface = %d, cut_version = %x\n", + dm->support_interface, dm->cut_version); + + iqk_info->tmp_gntwl = _iqk_indirect_read_reg(dm, 0x38); + iqk_info->iqk_times++; + iqk_info->kcount = 0; + dm->rf_calibrate_info.iqk_total_progressing_time = 0; + dm->rf_calibrate_info.iqk_step = 1; + iqk_info->rxiqk_step = 1; + iqk_info->is_reload = false; + + _iqk_backup_iqk_8821c(dm, 0x0, 0x0); + _iqk_backup_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C); + _iqk_backup_rf_8821c(dm, RF_backup, backup_rf_reg); + + while (1) { + if (!is_mp) + dm->rf_calibrate_info.iqk_start_time = odm_get_current_time(dm); + + _iqk_configure_macbb_8821c(dm); + _iqk_afe_setting_8821c(dm, true); + _iqk_rfe_setting_8821c(dm, false); + _iqk_agc_bnd_int_8821c(dm); + _iqk_rfsetting_8821c(dm); + if (do_imr_test) { + _iqk_start_imr_test_8821c(dm, 0x0); + dm->rf_calibrate_info.iqk_step = 4; + } else { + _iqk_start_iqk_8821c(dm, segment_iqk); + } + _iqk_afe_setting_8821c(dm, false); + _iqk_restore_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C); + _iqk_restore_rf_8821c(dm, backup_rf_reg, RF_backup); + + if (!is_mp) { + dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time); + dm->rf_calibrate_info.iqk_total_progressing_time += odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time); + RF_DBG(dm, DBG_RF_IQK, + "[IQK]IQK progressing_time = %lld ms\n", + dm->rf_calibrate_info.iqk_progressing_time); + } + + if (dm->rf_calibrate_info.iqk_step == 4) + break; + + iqk_info->kcount = 0; + RF_DBG(dm, DBG_RF_IQK, "[IQK]delay 50ms!!!\n"); +#if 0 + /*ODM_sleep_ms(50);*/ +#endif + ODM_delay_ms(50); + } + + if (!do_imr_test) { + if (segment_iqk) + _iqk_reload_iqk_setting_8821c(dm, 0x0, 0x1); + _iqk_fill_iqk_report_8821c(dm, 0); + if (!is_mp) + RF_DBG(dm, DBG_RF_IQK, + "[IQK]Total IQK progressing_time = %lld ms\n", + dm->rf_calibrate_info.iqk_total_progressing_time) + ; + RF_DBG(dm, DBG_RF_IQK, + "[IQK]==========IQK end!!!!!==========\n"); + RF_DBG(dm, DBG_RF_IQK, "[IQK]check 0x49c = %x\n", + odm_read_1byte(dm, 0x49c)); + } +} + +void _phy_iq_calibrate_by_fw_8821c(void *dm_void, u8 clear, u8 segment_iqk) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum hal_status status = HAL_STATUS_FAILURE; + + if (*dm->mp_mode) + clear = 0x1; + else if (dm->is_linked) + segment_iqk = 0x1; + + status = odm_iq_calibrate_by_fw(dm, clear, segment_iqk); + + if (status == HAL_STATUS_SUCCESS) + RF_DBG(dm, DBG_RF_IQK, "[IQK]FWIQK OK!!!\n"); + else + RF_DBG(dm, DBG_RF_IQK, "[IQK]FWIQK fail!!!\n"); +} + +/*********debug message start**************/ + +void _phy_iqk_XYM_Read_Using_0x1b38_8821c(struct dm_struct *dm, u8 path) +{ + u32 tmp = 0x0; + u32 tmp2; + u8 i; + + tmp = odm_read_4byte(dm, 0x1b1c); + odm_write_4byte(dm, 0x1b1c, 0xA2193C32); + RF_DBG(dm, DBG_RF_IQK, "\n"); + for (i = 0; i < 0xa; i++) { + odm_write_4byte(dm, 0x1b14, 0xe6 + i); + odm_write_4byte(dm, 0x1b14, 0x0); + tmp2 = odm_read_4byte(dm, 0x1b38); + RF_DBG(dm, DBG_RF_IQK, "%x\n", tmp2); + } + odm_write_4byte(dm, 0x1b1c, tmp); + RF_DBG(dm, DBG_RF_IQK, "\n"); + odm_write_4byte(dm, 0x1b38, 0x20000000); +} + +void _phy_iqk_debug_inner_lpbk_psd_8821c(struct dm_struct *dm, u8 path) +{ + s16 tx_x; + s16 tx_y; + u32 temp = 0x0; + u32 psd_pwr = 0x0; + u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9, tmp10; + + tmp1 = odm_read_4byte(dm, 0x1b20); + tmp2 = odm_read_4byte(dm, 0x1b24); + tmp3 = odm_read_4byte(dm, 0x1b15); + tmp4 = odm_read_4byte(dm, 0x1b18); + tmp5 = odm_read_4byte(dm, 0x1b1c); + tmp6 = odm_read_4byte(dm, 0x1b28); + tmp7 = odm_read_4byte(dm, 0x1b90); + tmp8 = odm_read_4byte(dm, 0x1bcc); + tmp9 = odm_read_4byte(dm, 0x1b2c); + tmp10 = odm_read_4byte(dm, 0x1b30); + odm_write_4byte(dm, 0x1b20, 0x03840008); + odm_write_4byte(dm, 0x1b24, 0x03860008); + odm_write_1byte(dm, 0x1b15, 0x00); + odm_write_4byte(dm, 0x1b18, 0x00010101); + odm_write_4byte(dm, 0x1b1c, 0x02effcb2); + odm_write_4byte(dm, 0x1b28, 0x00060c00); + odm_write_4byte(dm, 0x1b90, 0x00080003); + odm_write_4byte(dm, 0x1bcc, 0x00000009); + odm_write_4byte(dm, 0x1b2c, 0x20000003); + odm_write_4byte(dm, 0x1b30, 0x20000000); + RF_DBG(dm, DBG_RF_IQK, "\n"); + for (tx_x = 507; tx_x <= 532; tx_x++) { + for (tx_y = 0; tx_y <= 10 + 20; tx_y++) { + if (tx_y < 0) + temp = (tx_x << 20) | (tx_y + 2048) << 8; + else + temp = (tx_x << 20) | (tx_y << 8); + odm_write_4byte(dm, 0x1b38, temp); + odm_write_4byte(dm, 0x1b3c, 0x20000000); + odm_write_4byte(dm, 0x1b34, 0x00000801); + odm_write_4byte(dm, 0x1b34, 0x00000800); + ODM_delay_ms(2); + /*PSD_bef_K*/ + odm_write_4byte(dm, 0x1bd4, 0x000c0001); + psd_pwr = odm_read_4byte(dm, 0x1bfc); + RF_DBG(dm, DBG_RF_IQK, "%d ", psd_pwr); + } + } + RF_DBG(dm, DBG_RF_IQK, "\n"); + odm_write_4byte(dm, 0x1b20, tmp1); + odm_write_4byte(dm, 0x1b24, tmp2); + odm_write_4byte(dm, 0x1b15, tmp3); + odm_write_4byte(dm, 0x1b18, tmp4); + odm_write_4byte(dm, 0x1b1c, tmp5); + odm_write_4byte(dm, 0x1b28, tmp6); + odm_write_4byte(dm, 0x1b90, tmp7); + odm_write_4byte(dm, 0x1bcc, tmp8); + odm_write_4byte(dm, 0x1b2c, tmp9); + odm_write_4byte(dm, 0x1b30, tmp10); + odm_write_4byte(dm, 0x1b38, 0x20000000); +} + +void _iqk_readsram_8821c(struct dm_struct *dm, u8 path) +{ + u32 tmp1bd4, tmp1bd8, tmp; + u8 i; + + tmp1bd4 = odm_read_4byte(dm, 0x1bd4); + tmp1bd8 = odm_read_4byte(dm, 0x1bd8); + odm_write_4byte(dm, 0x1bd4, 0x00010001); + for (i = 0; i < 0x80; i++) { + odm_write_4byte(dm, 0x1bd8, 0xa0000101 + (u32)(i << 1)); + tmp = (u32)odm_read_4byte(dm, 0x1bfc) & 0x3ff; + if (i < 0x40) + RF_DBG(dm, DBG_RF_IQK, "adc_i[%d] = %x\n", i, tmp); + else + RF_DBG(dm, DBG_RF_IQK, "adc_q[%d] = %x\n", i, tmp); + } +} + +void do_imr_test_8821c(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + RF_DBG(dm, DBG_RF_IQK, + "[IQK] ************IMR Test *****************\n"); + _phy_iq_calibrate_8821c(dm, false, false, true); + RF_DBG(dm, DBG_RF_IQK, + "[IQK] **********End IMR Test *******************\n"); +} + +/*********debug message end***************/ + +/*IQK version:0x23, NCTL:0x8*/ +/*1. modify the iqk counters for coex.*/ + +void phy_iq_calibrate_8821c(void *dm_void, boolean clear, boolean segment_iqk) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + + if (!(*dm->mp_mode)) + _iqk_check_coex_status(dm, true); + + RF_DBG(dm, DBG_RF_IQK, "[IQK]fw_ver= 0x%x\n", rf->fw_ver); + if (*dm->mp_mode) + halrf_iqk_hwtx_check(dm, true); + /*FW IQK*/ + if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) { + _phy_iq_calibrate_by_fw_8821c(dm, clear, segment_iqk); + phydm_get_read_counter_8821c(dm); + RF_DBG(dm, DBG_RF_IQK, "[IQK]0x38= 0x%x\n", + _iqk_indirect_read_reg(dm, 0x38)); + } else { + _iq_calibrate_8821c_init(dm); + _phy_iq_calibrate_8821c(dm, clear, segment_iqk, false); + } + _iqk_fail_count_8821c(dm); + + if (*dm->mp_mode) + halrf_iqk_hwtx_check(dm, false); +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + _iqk_iqk_fail_report_8821c(dm); +#endif + halrf_iqk_dbg(dm); + + if (!(*dm->mp_mode)) + _iqk_check_coex_status(dm, false); + RF_DBG(dm, DBG_RF_IQK, "[IQK]final 0x49c = %x\n", + odm_read_1byte(dm, 0x49c)); +} + +void phy_dp_calibrate_8821c(void *dm_void, boolean clear) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (odm_check_power_status(dm) == false) + return; +#endif + +#if (MP_DRIVER) + if ((dm->mp_mode != NULL) && (rf->is_con_tx != NULL) && (rf->is_single_tone != NULL) && (rf->is_carrier_suppresion != NULL)) + if (*(dm->mp_mode) && ((*(rf->is_con_tx) || *(rf->is_single_tone) || *(rf->is_carrier_suppresion)))) + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(rf->rf_supportability & HAL_RF_DPK)) + return; +#endif + +#if DISABLE_BB_RF + return; +#endif + + RF_DBG(dm, DBG_RF_IQK, "[DPK] In PHY, dm->dpk_en == %x\n", rf->dpk_en); + + /*if dpk is not enable*/ + if (rf->dpk_en == 0x0) + return; + + /*start*/ + if (!dm->rf_calibrate_info.is_iqk_in_progress) { + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = true; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + if (*dm->mp_mode) + dm->rf_calibrate_info.iqk_start_time = odm_get_current_time(dm); + + if (*dm->mp_mode) { + /*do DPK*/ + _phy_dpd_calibrate_8821c(dm, clear); + _dpk_toggle_rxagc(dm, clear); + } + + if (*dm->mp_mode) { + dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time); + RF_DBG(dm, DBG_RF_IQK, + "[DPK]DPK progressing_time = %lld ms\n", + dm->rf_calibrate_info.iqk_progressing_time); + } + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + } else { + RF_DBG(dm, DBG_RF_IQK, + "[DPK]== Return the DPK CMD, because the DPK in Progress ==\n"); + } +} +void phy_txtap_calibrate_8821c(void *dm_void, boolean clear) +{ + u32 MAC_backup[MAC_REG_NUM_8821C], BB_backup[BB_REG_NUM_8821C], RF_backup[RF_REG_NUM_8821C][1]; + u32 backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518}; + u32 backup_bb_reg[BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0x1990, 0x9a4, 0xa04}; + u32 backup_rf_reg[RF_REG_NUM_8821C] = {0xdf, 0xde, 0x8f, 0x0, 0x1}; + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dm_iqk_info *iqk_info = &dm->IQK_info; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + struct _ADAPTER *adapter = dm->adapter; + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx); +#else +#ifdef CONFIG_MP_INCLUDED + PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx); +#endif +#endif +#endif + + struct _hal_rf_ *rf = &dm->rf_table; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(rf->rf_supportability & HAL_RF_IQK)) + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if (odm_check_power_status(adapter) == false) + return; +#endif + +#if MP_DRIVER == 1 +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (p_mpt_ctx->bSingleTone || p_mpt_ctx->bCarrierSuppression) + return; +#else +#ifdef CONFIG_MP_INCLUDED + if (p_mpt_ctx->is_single_tone || p_mpt_ctx->is_carrier_suppression) + return; +#endif +#endif +#endif +#endif + + if (!(*dm->mp_mode)) + _iqk_check_coex_status(dm, true); + + if ((dm->rf_table.rf_supportability & HAL_RF_TXGAPK)) + if (iqk_info->lok_fail[RF_PATH_A] == 0 && + iqk_info->iqk_fail_report[0][RF_PATH_A][TXIQK] == 0 && + iqk_info->iqk_fail_report[0][RF_PATH_A][RXIQK] == 0) { + _iqk_backup_iqk_8821c(dm, 0x0, 0x0); + _iqk_backup_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C); + _iqk_backup_rf_8821c(dm, RF_backup, backup_rf_reg); + + _iqk_configure_macbb_8821c(dm); + _iqk_afe_setting_8821c(dm, true); + _iqk_rfe_setting_8821c(dm, false); + _iqk_agc_bnd_int_8821c(dm); + _iqk_rfsetting_8821c(dm); + + _phy_txgapk_calibrate_8821c(dm, RF_PATH_A); + + _iqk_afe_setting_8821c(dm, false); + _iqk_restore_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C); + _iqk_restore_rf_8821c(dm, backup_rf_reg, RF_backup); + } +} +void dpk_temperature_compensate_8821c(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _hal_rf_ *rf = &dm->rf_table; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + u8 pgthermal = hal_data->eeprom_thermal_meter; +#else + struct rtl8192cd_priv *priv = dm->priv; + u8 pgthermal = (u8)priv->pmib->dot11RFEntry.ther; + +#endif + static u8 dpk_tm_trigger; + u8 thermal_value = 0, delta_dpk, i = 0; + u8 thermal_value_avg_count = 0; + u8 thermal_value_avg_times = 2; + u32 thermal_value_avg = 0; + u8 tmp, abs_temperature; + + /*if dpk is not enable*/ + if (rf->dpk_en == 0x0) + return; + /*if ap mode, disable dpk*/ + if (DM_ODM_SUPPORT_TYPE & ODM_AP) + return; + if (!dpk_tm_trigger) { + odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17) | BIT(16), 0x03); +#if 0 + /*RF_DBG(dm, DBG_RF_IQK, "[DPK] (1) Trigger Thermal Meter!!\n");*/ +#endif + dpk_tm_trigger = 1; + return; + } + + /* Initialize */ + dpk_tm_trigger = 0; +#if 0 + /*RF_DBG(dm, DBG_RF_IQK, "[DPK] (2) calculate the thermal !!\n"); + */ +#endif + + /* calculate average thermal meter */ + thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x42, 0xfc00); /*0x42: RF Reg[15:10] 88E*/ + RF_DBG(dm, DBG_RF_IQK, "[DPK] (3) current Thermal Meter = %d\n", + thermal_value); + + dm->rf_calibrate_info.thermal_value_dpk = thermal_value; + dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value; + dm->rf_calibrate_info.thermal_value_avg_index++; + if (dm->rf_calibrate_info.thermal_value_avg_index == thermal_value_avg_times) + dm->rf_calibrate_info.thermal_value_avg_index = 0; + for (i = 0; i < thermal_value_avg_times; i++) { + if (dm->rf_calibrate_info.thermal_value_avg[i]) { + thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + if (thermal_value_avg_count) /*Calculate Average thermal_value after average enough times*/ + thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); + /* compensate the DPK */ + delta_dpk = (thermal_value > pgthermal) ? (thermal_value - pgthermal) : (pgthermal - thermal_value); + tmp = (u8)((dpk_result[0] & 0x00001f00) >> 8); + RF_DBG(dm, DBG_RF_IQK, + "[DPK] (5)delta_dpk = %d, eeprom_thermal_meter = %d, tmp=%d\n", + delta_dpk, pgthermal, tmp); + + if (thermal_value > pgthermal) { + abs_temperature = thermal_value - pgthermal; + if (abs_temperature >= 20) + tmp = tmp + 4; + else if (abs_temperature >= 15) + tmp = tmp + 3; + else if (abs_temperature >= 10) + tmp = tmp + 2; + else if (abs_temperature >= 5) + tmp = tmp + 1; + } else { /*low temperature*/ + abs_temperature = pgthermal - thermal_value; + if (abs_temperature >= 20) + tmp = tmp - 4; + else if (abs_temperature >= 15) + tmp = tmp - 3; + else if (abs_temperature >= 10) + tmp = tmp - 2; + else if (abs_temperature >= 5) + tmp = tmp - 1; + } + + odm_set_bb_reg(dm, R_0x1bd0, BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), tmp); + RF_DBG(dm, DBG_RF_IQK, + "[DPK] (6)delta_dpk = %d, eeprom_thermal_meter = %d, new tmp=%d, 0x1bd0=0x%x\n", + delta_dpk, pgthermal, tmp, odm_read_4byte(dm, 0x1bd0)); +} + +#endif diff --git a/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.h b/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.h new file mode 100644 index 0000000..12194f7 --- /dev/null +++ b/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.h @@ -0,0 +1,62 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __HALRF_IQK_8821C_H__ +#define __HALRF_IQK_8821C_H__ + +#if (RTL8821C_SUPPORT == 1) +/*============================================================*/ +/*Definition */ +/*============================================================*/ + +/*--------------------------Define Parameters-------------------------------*/ +#define MAC_REG_NUM_8821C 3 +#define BB_REG_NUM_8821C 10 +#define RF_REG_NUM_8821C 5 +#define DPK_BB_REG_NUM_8821C 23 +#define DPK_BACKUP_REG_NUM_8821C 3 + +#define LOK_delay_8821C 2 +#define GS_delay_8821C 2 +#define WBIQK_delay_8821C 2 + +#define TXIQK 0 +#define RXIQK 1 +#define SS_8821C 1 + +/*---------------------------End Define Parameters-------------------------------*/ + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +void do_iqk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value, + u8 threshold); +#else +void do_iqk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value, + u8 threshold); +#endif + +void phy_iq_calibrate_8821c(void *dm_void, boolean clear, boolean segment_iqk); + +void phy_dp_calibrate_8821c(void *dm_void, boolean clear); + +void do_imr_test_8821c(void *dm_void); + +#else /* (RTL8821C_SUPPORT == 0)*/ + +#define phy_iq_calibrate_8821c(_pdm_void, clear, segment_iqk) +#define phy_dp_calibrate_8821c(_pDM_VOID, clear) + +#endif /* RTL8821C_SUPPORT */ + +#endif /*#ifndef __HALRF_IQK_8821C_H__*/ diff --git a/hal/phydm/mp_precomp.h b/hal/phydm/mp_precomp.h index fa483c6..897adc1 100644 --- a/hal/phydm/mp_precomp.h +++ b/hal/phydm/mp_precomp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,12 +8,17 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ diff --git a/hal/phydm/phydm.c b/hal/phydm/phydm.c index fe7fbc4..3355422 100644 --- a/hal/phydm/phydm.c +++ b/hal/phydm/phydm.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,2086 +8,2546 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -/* ************************************************************ +/*@************************************************************ * include files - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" -const u16 db_invert_table[12][8] = { - { 1, 1, 1, 2, 2, 2, 2, 3}, - { 3, 3, 4, 4, 4, 5, 6, 6}, - { 7, 8, 9, 10, 11, 13, 14, 16}, - { 18, 20, 22, 25, 28, 32, 35, 40}, - { 45, 50, 56, 63, 71, 79, 89, 100}, - { 112, 126, 141, 158, 178, 200, 224, 251}, - { 282, 316, 355, 398, 447, 501, 562, 631}, - { 708, 794, 891, 1000, 1122, 1259, 1413, 1585}, - { 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, - { 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000}, - { 11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119}, - { 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} +const u16 phy_rate_table[] = { + /*@20M*/ + 1, 2, 5, 11, + 6, 9, 12, 18, 24, 36, 48, 54, + 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/ + 13, 26, 39, 52, 78, 104, 117, 130 /*@MCS8~15*/ }; - -/* ************************************************************ - * Local Function predefine. - * ************************************************************ */ - -/* START------------COMMON INFO RELATED--------------- */ - -void -odm_global_adapter_check( - void -); - -/* move to odm_PowerTacking.h by YuChen */ - - - -void -odm_update_power_training_state( - struct PHY_DM_STRUCT *p_dm_odm -); - -/* ************************************************************ - * 3 Export Interface - * ************************************************************ */ - -/*Y = 10*log(X)*/ -s32 -odm_pwdb_conversion( - s32 X, - u32 total_bit, - u32 decimal_bit -) -{ - s32 Y, integer = 0, decimal = 0; - u32 i; - - if (X == 0) - X = 1; /* log2(x), x can't be 0 */ - - for (i = (total_bit - 1); i > 0; i--) { - if (X & BIT(i)) { - integer = i; - if (i > 0) - decimal = (X & BIT(i - 1)) ? 2 : 0; /* decimal is 0.5dB*3=1.5dB~=2dB */ - break; - } - } - - Y = 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */ - - return Y; -} - -s32 -odm_sign_conversion( - s32 value, - u32 total_bit -) +void phydm_traffic_load_decision(void *dm_void) { - if (value & BIT(total_bit - 1)) - value -= BIT(total_bit); - return value; -} + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 shift = 0; -void -phydm_seq_sorting( - void *p_dm_void, - u32 *p_value, - u32 *rank_idx, - u32 *p_idx_out, - u8 seq_length -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i = 0, j = 0; - u32 tmp_a, tmp_b; - u32 tmp_idx_a, tmp_idx_b; - - for (i = 0; i < seq_length; i++) { - rank_idx[i] = i; - /**/ - } + /*@---TP & Trafic-load calculation---*/ - for (i = 0; i < (seq_length - 1); i++) { + if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast) + dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast; - for (j = 0; j < (seq_length - 1 - i); j++) { + if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast) + dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast; - tmp_a = p_value[j]; - tmp_b = p_value[j + 1]; + dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt; + dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt; + dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast; + dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast; - tmp_idx_a = rank_idx[j]; - tmp_idx_b = rank_idx[j + 1]; + /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/ + shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1); + /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/ - if (tmp_a < tmp_b) { - p_value[j] = tmp_b; - p_value[j + 1] = tmp_a; + dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1); + dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1); - rank_idx[j] = tmp_idx_b; - rank_idx[j + 1] = tmp_idx_a; - } - } - } + dm->total_tp = dm->tx_tp + dm->rx_tp; - for (i = 0; i < seq_length; i++) { - p_idx_out[rank_idx[i]] = i + 1; - /**/ + /*@[Calculate TX/RX state]*/ + if (dm->tx_tp > (dm->rx_tp << 1)) + dm->txrx_state_all = TX_STATE; + else if (dm->rx_tp > (dm->tx_tp << 1)) + dm->txrx_state_all = RX_STATE; + else + dm->txrx_state_all = BI_DIRECTION_STATE; + + /*@[Traffic load decision]*/ + dm->pre_traffic_load = dm->traffic_load; + + if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) { + /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/ + dm->traffic_load = TRAFFIC_HIGH; + } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) { + /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/ + dm->traffic_load = TRAFFIC_MID; + } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) { + /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/ + dm->traffic_load = TRAFFIC_LOW; + } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) { + /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/ + dm->traffic_load = TRAFFIC_ULTRA_LOW; + } else { + dm->traffic_load = TRAFFIC_NO_TP; } + /*@[Calculate consecutive idlel time]*/ + if (dm->traffic_load == 0) + dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD; + else + dm->consecutive_idlel_time = 0; + #if 0 + PHYDM_DBG(dm, DBG_COMMON_FLOW, + "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n", + dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt, + dm->last_rx_ok_cnt); + PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp, + dm->rx_tp); + #endif } -void -odm_init_mp_driver_status( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - /* Decide when compile time */ -#if (MP_DRIVER == 1) - p_dm_odm->mp_mode = true; -#else - p_dm_odm->mp_mode = false; -#endif - -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - - struct _ADAPTER *adapter = p_dm_odm->adapter; - - /* Update information every period */ - p_dm_odm->mp_mode = (boolean)adapter->registrypriv.mp_mode; - -#else - - struct rtl8192cd_priv *priv = p_dm_odm->priv; - - p_dm_odm->mp_mode = (boolean)priv->pshare->rf_ft_var.mp_specific; - -#endif -} - -void -odm_update_mp_driver_status( - struct PHY_DM_STRUCT *p_dm_odm -) +void phydm_cck_new_agc_chk(struct dm_struct *dm) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - /* Do nothing. */ - -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; - - /* Update information erery period */ - p_dm_odm->mp_mode = (boolean)adapter->registrypriv.mp_mode; - -#else - - /* Do nothing. */ - + dm->cck_new_agc = 0; + +#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || \ + (RTL8821C_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || \ + (RTL8710B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1) || \ + (RTL8195B_SUPPORT == 1) || (RTL8198F_SUPPORT == 1) || \ + (RTL8822C_SUPPORT == 1)) + if (dm->support_ic_type & + (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8197F | + ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B)) { + /*@1: new agc 0: old agc*/ + dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0xa9c, BIT(17)); + } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) { + /*@1: new agc 0: old agc*/ + dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, R_0x1a9c, + BIT(17)); + } #endif } -void -phydm_init_trx_antenna_setting( - struct PHY_DM_STRUCT *p_dm_odm -) +/*select 3 or 4 bit LNA */ +void phydm_cck_lna_bit_num_chk(struct dm_struct *dm) { - /*#if (RTL8814A_SUPPORT == 1)*/ - - if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) { - u8 rx_ant = 0, tx_ant = 0; + boolean report_type = 0; + #if (RTL8192E_SUPPORT == 1) + u32 value_824, value_82c; + #endif - rx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm)); - tx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_TX_PATH, p_dm_odm), ODM_BIT(BB_TX_PATH, p_dm_odm)); - p_dm_odm->tx_ant_status = (tx_ant & 0xf); - p_dm_odm->rx_ant_status = (rx_ant & 0xf); - } else if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B)) {/* JJ ADD 20161014 */ - p_dm_odm->tx_ant_status = 0x1; - p_dm_odm->rx_ant_status = 0x1; + #if (RTL8192E_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8192E)) { + /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting + * should be equal or CCK RSSI report may be incorrect + */ + value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9)); + value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9)); + if (value_824 != value_82c) + odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824); + odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824); + report_type = (boolean)value_824; } - /*#endif*/ -} - -void -phydm_traffic_load_decision( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - - /*---TP & Trafic-load calculation---*/ - - if (p_dm_odm->last_tx_ok_cnt > (*(p_dm_odm->p_num_tx_bytes_unicast))) - p_dm_odm->last_tx_ok_cnt = (*(p_dm_odm->p_num_tx_bytes_unicast)); - - if (p_dm_odm->last_rx_ok_cnt > (*(p_dm_odm->p_num_rx_bytes_unicast))) - p_dm_odm->last_rx_ok_cnt = (*(p_dm_odm->p_num_rx_bytes_unicast)); - - p_dm_odm->cur_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast) - p_dm_odm->last_tx_ok_cnt; - p_dm_odm->cur_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast) - p_dm_odm->last_rx_ok_cnt; - p_dm_odm->last_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast); - p_dm_odm->last_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast); - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - p_dm_odm->tx_tp = ((p_dm_odm->tx_tp) >> 1) + (u32)(((p_dm_odm->cur_tx_ok_cnt) >> 17) >> 1); /* <<3(8bit), >>20(10^6,M)*/ - p_dm_odm->rx_tp = ((p_dm_odm->rx_tp) >> 1) + (u32)(((p_dm_odm->cur_rx_ok_cnt) >> 17) >> 1); /* <<3(8bit), >>20(10^6,M)*/ -#else - p_dm_odm->tx_tp = ((p_dm_odm->tx_tp) >> 1) + (u32)(((p_dm_odm->cur_tx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ - p_dm_odm->rx_tp = ((p_dm_odm->rx_tp) >> 1) + (u32)(((p_dm_odm->cur_rx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ -#endif - p_dm_odm->total_tp = p_dm_odm->tx_tp + p_dm_odm->rx_tp; - - if (p_dm_odm->total_tp == 0) - p_dm_odm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD; - else - p_dm_odm->consecutive_idlel_time = 0; - /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n", - p_dm_odm->cur_tx_ok_cnt, p_dm_odm->cur_rx_ok_cnt, p_dm_odm->last_tx_ok_cnt, p_dm_odm->last_rx_ok_cnt)); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("tx_tp = %d, rx_tp = %d\n", - p_dm_odm->tx_tp, p_dm_odm->rx_tp)); - */ - - p_dm_odm->pre_traffic_load = p_dm_odm->traffic_load; - - if (p_dm_odm->cur_tx_ok_cnt > 1875000 || p_dm_odm->cur_rx_ok_cnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/ - - p_dm_odm->traffic_load = TRAFFIC_HIGH; - /**/ - } else if (p_dm_odm->cur_tx_ok_cnt > 500000 || p_dm_odm->cur_rx_ok_cnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/ - - p_dm_odm->traffic_load = TRAFFIC_MID; - /**/ - } else if (p_dm_odm->cur_tx_ok_cnt > 100000 || p_dm_odm->cur_rx_ok_cnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/ + #endif - p_dm_odm->traffic_load = TRAFFIC_LOW; - /**/ - } else { + #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT) + if (dm->support_ic_type & + (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11)); - p_dm_odm->traffic_load = TRAFFIC_ULTRA_LOW; - /**/ + if (report_type != 1) + pr_debug("[Warning] CCK should be 4bit LNA\n"); } -} - -void -phydm_config_ofdm_tx_path( - struct PHY_DM_STRUCT *p_dm_odm, - u32 path -) -{ - u8 ofdm_tx_path = 0x33; - -#if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { - - if (path == PHYDM_A) { - odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x81121111); - /**/ - } else if (path == PHYDM_B) { - odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x82221222); - /**/ - } else if (path == PHYDM_AB) { - odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x83321333); - /**/ - } - + #endif + #if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) { + if (dm->default_rf_set_8821c == SWITCH_TO_BTG) + report_type = 1; } -#endif + #endif -#if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8812)) { - - if (path == PHYDM_A) { - ofdm_tx_path = 0x11; - /**/ - } else if (path == PHYDM_B) { - ofdm_tx_path = 0x22; - /**/ - } else if (path == PHYDM_AB) { - ofdm_tx_path = 0x33; - /**/ - } + dm->cck_agc_report_type = report_type; - odm_set_bb_reg(p_dm_odm, 0x80c, 0xff00, ofdm_tx_path); - } -#endif + PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n", + dm->cck_agc_report_type); } -void -phydm_config_ofdm_rx_path( - struct PHY_DM_STRUCT *p_dm_odm, - u32 path -) +void phydm_init_cck_setting(struct dm_struct *dm) { - u8 ofdm_rx_path = 0; + u32 reg_tmp = 0; + u32 mask_tmp = 0; + reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm); + mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm); + dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp); - if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { -#if (RTL8192E_SUPPORT == 1) - if (path == PHYDM_A) { - ofdm_rx_path = 1; - /**/ - } else if (path == PHYDM_B) { - ofdm_rx_path = 2; - /**/ - } else if (path == PHYDM_AB) { - ofdm_rx_path = 3; - /**/ - } + PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain); - odm_set_bb_reg(p_dm_odm, 0xC04, 0xff, (((ofdm_rx_path) << 4) | ofdm_rx_path)); - odm_set_bb_reg(p_dm_odm, 0xD04, 0xf, ofdm_rx_path); -#endif - } -#if (RTL8812A_SUPPORT || RTL8822B_SUPPORT) - else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) { - - if (path == PHYDM_A) { - ofdm_rx_path = 1; - /**/ - } else if (path == PHYDM_B) { - ofdm_rx_path = 2; - /**/ - } else if (path == PHYDM_AB) { - ofdm_rx_path = 3; - /**/ - } + phydm_config_cck_rx_antenna_init(dm); - odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, ((ofdm_rx_path << 4) | ofdm_rx_path)); - } -#endif -} + if (dm->support_ic_type & (ODM_RTL8192F)) + phydm_config_cck_rx_path(dm, BB_PATH_AB); + else + phydm_config_cck_rx_path(dm, BB_PATH_A); -void -phydm_config_cck_rx_antenna_init( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) { - - /*CCK 2R CCA parameters*/ - odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(18), 1); /*enable 2R Rx path*/ - odm_set_bb_reg(p_dm_odm, 0xa2c, BIT(22), 1); /*enable 2R MRC*/ - odm_set_bb_reg(p_dm_odm, 0xa84, BIT(28), 1); /*1. pdx1[5:0] > 2*PD_lim 2. RXIQ_3 = 0 ( signed )*/ - odm_set_bb_reg(p_dm_odm, 0xa70, BIT(7), 0); /*Concurrent CCA at LSB & USB*/ - odm_set_bb_reg(p_dm_odm, 0xa74, BIT(8), 0); /*RX path diversity enable*/ - odm_set_bb_reg(p_dm_odm, 0xa08, BIT(28), 1); /* r_cck_2nd_sel_eco*/ - odm_set_bb_reg(p_dm_odm, 0xa14, BIT(7), 0); /* r_en_mrc_antsel*/ - } -#endif + phydm_cck_new_agc_chk(dm); + phydm_cck_lna_bit_num_chk(dm); + phydm_get_cck_rssi_table_from_reg(dm); } -void -phydm_config_cck_rx_path( - struct PHY_DM_STRUCT *p_dm_odm, - u8 path, - u8 path_div_en -) +void phydm_init_hw_info_by_rfe(struct dm_struct *dm) { - u8 path_div_select = 0; - u8 cck_1_path = 0, cck_2_path = 0; - -#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) { - - if (path == PHYDM_A) { - path_div_select = 0; - cck_1_path = 0; - cck_2_path = 0; - } else if (path == PHYDM_B) { - path_div_select = 0; - cck_1_path = 1; - cck_2_path = 1; - } else if (path == PHYDM_AB) { - - if (path_div_en == CCA_PATHDIV_ENABLE) - path_div_select = 1; - - cck_1_path = 0; - cck_2_path = 1; - - } - - odm_set_bb_reg(p_dm_odm, 0xa04, (BIT(27) | BIT(26)), cck_1_path); - odm_set_bb_reg(p_dm_odm, 0xa04, (BIT(25) | BIT(24)), cck_2_path); - odm_set_bb_reg(p_dm_odm, 0xa74, BIT(8), path_div_select); - - } +#if (RTL8822B_SUPPORT == 1) + /*@if (dm->support_ic_type & ODM_RTL8822B)*/ + /*@phydm_init_hw_info_by_rfe_type_8822b(dm);*/ +#endif +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) + phydm_init_hw_info_by_rfe_type_8821c(dm); +#endif +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) + phydm_init_hw_info_by_rfe_type_8197f(dm); #endif } -void -phydm_config_trx_path( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) +void phydm_common_info_self_init(struct dm_struct *dm) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 pre_support_ability; - u32 used = *_used; - u32 out_len = *_out_len; - - /* CCK */ - if (dm_value[0] == 0) { - - if (dm_value[1] == 1) { /*TX*/ - if (dm_value[2] == 1) - odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x8); - else if (dm_value[2] == 2) - odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x4); - else if (dm_value[2] == 3) - odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0xc); - } else if (dm_value[1] == 2) { /*RX*/ - - phydm_config_cck_rx_antenna_init(p_dm_odm); - - if (dm_value[2] == 1) - phydm_config_cck_rx_path(p_dm_odm, PHYDM_A, CCA_PATHDIV_DISABLE); - else if (dm_value[2] == 2) - phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE); - else if (dm_value[2] == 3) { - if (dm_value[3] == 1) /*enable path diversity*/ - phydm_config_cck_rx_path(p_dm_odm, PHYDM_AB, CCA_PATHDIV_ENABLE); - else - phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE); - } - } - } - /* OFDM */ - else if (dm_value[0] == 1) { - - if (dm_value[1] == 1) { /*TX*/ - phydm_config_ofdm_tx_path(p_dm_odm, dm_value[2]); - /**/ - } else if (dm_value[1] == 2) { /*RX*/ - phydm_config_ofdm_rx_path(p_dm_odm, dm_value[2]); - /**/ - } - } - - PHYDM_SNPRINTF((output + used, out_len - used, "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n", - (dm_value[0] == 1) ? "OFDM" : "CCK", - (dm_value[1] == 1) ? "TX" : "RX", - (dm_value[2] & 0x1) ? "A" : "", - (dm_value[2] & 0x2) ? "B" : "", - (dm_value[2] & 0x4) ? "C" : "", - (dm_value[2] & 0x8) ? "D" : "" - )); + u32 reg_tmp = 0; + u32 mask_tmp = 0; -} + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + dm->ic_ip_series = PHYDM_IC_JGR3; + else if (dm->support_ic_type & ODM_IC_11AC_SERIES) + dm->ic_ip_series = PHYDM_IC_AC; + else if (dm->support_ic_type & ODM_IC_11N_SERIES) + dm->ic_ip_series = PHYDM_IC_N; -void -phydm_init_cck_setting( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - u32 value_824, value_82c; + phydm_init_cck_setting(dm); - p_dm_odm->is_cck_high_power = (boolean) odm_get_bb_reg(p_dm_odm, ODM_REG(CCK_RPT_FORMAT, p_dm_odm), ODM_BIT(CCK_RPT_FORMAT, p_dm_odm)); + reg_tmp = ODM_REG(BB_RX_PATH, dm); + mask_tmp = ODM_BIT(BB_RX_PATH, dm); + dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp); +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) + dm->is_net_closed = &dm->BOOLEAN_temp; -#if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - phydm_config_cck_rx_antenna_init(p_dm_odm); - phydm_config_cck_rx_path(p_dm_odm, PHYDM_A, CCA_PATHDIV_DISABLE); + phydm_init_debug_setting(dm); #endif - /* 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting should be equal or CCK RSSI report may be incorrect */ - value_824 = odm_get_bb_reg(p_dm_odm, 0x824, BIT(9)); - value_82c = odm_get_bb_reg(p_dm_odm, 0x82c, BIT(9)); + phydm_init_soft_ml_setting(dm); - if (value_824 != value_82c) - odm_set_bb_reg(p_dm_odm, 0x82c, BIT(9), value_824); - odm_set_bb_reg(p_dm_odm, 0xa80, BIT(7), value_824); - p_dm_odm->cck_agc_report_type = (boolean)value_824; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("cck_agc_report_type = (( %d )), ext_lna_gain = (( %d ))\n", p_dm_odm->cck_agc_report_type, p_dm_odm->ext_lna_gain)); - } -#endif -/* JJ ADD 20161014 */ -#if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + dm->phydm_sys_up_time = 0; - p_dm_odm->cck_agc_report_type = odm_get_bb_reg(p_dm_odm, 0x950, BIT(11)) ? 1 : 0; /*1: 4bit LNA, 0: 3bit LNA */ - - if (p_dm_odm->cck_agc_report_type != 1) { - dbg_print("[Warning] 8703B/8723D/8710B CCK should be 4bit LNA, ie. 0x950[11] = 1\n"); - /**/ - } - } -#endif -/* JJ ADD 20161014 */ -#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8710B)) - p_dm_odm->cck_new_agc = odm_get_bb_reg(p_dm_odm, 0xa9c, BIT(17)) ? true : false; /*1: new agc 0: old agc*/ + if (dm->support_ic_type & ODM_IC_1SS) + dm->num_rf_path = 1; + else if (dm->support_ic_type & ODM_IC_2SS) + dm->num_rf_path = 2; + else if (dm->support_ic_type & ODM_IC_3SS) + dm->num_rf_path = 3; + else if (dm->support_ic_type & ODM_IC_4SS) + dm->num_rf_path = 4; else -#endif - p_dm_odm->cck_new_agc = false; - -} - - -void -phydm_dynamicsoftmletting( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - - u32 ret_val; - -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->mp_mode == FALSE) { - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + dm->num_rf_path = 1; - if ((!p_dm_odm->is_linked)|(p_dm_odm->bLinkedcmw500)) - return; - - if (TRUE == p_dm_odm->bsomlenabled) { - ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_TRACE,("PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\n")); - return; - } + phydm_trx_antenna_setting_init(dm, dm->num_rf_path); - ret_val = odm_get_bb_reg(p_dm_odm, 0xf8c, bMaskByte0); - ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_TRACE,("PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\n",ret_val)); + dm->tx_rate = 0xFF; + dm->rssi_min_by_path = 0xFF; - if (ret_val < 0x16) { - ODM_RT_TRACE(p_dm_odm,ODM_COMP_API,ODM_DBG_LOUD,("PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\n",ret_val)); - odm_set_bb_reg(p_dm_odm, 0x19a8, bMaskDWord, 0xc10a0000); - p_dm_odm->bsomlenabled = TRUE; - } - } - } -#endif + dm->number_linked_client = 0; + dm->pre_number_linked_client = 0; + dm->number_active_client = 0; + dm->pre_number_active_client = 0; -} + dm->last_tx_ok_cnt = 0; + dm->last_rx_ok_cnt = 0; + dm->tx_tp = 0; + dm->rx_tp = 0; + dm->total_tp = 0; + dm->traffic_load = TRAFFIC_LOW; + dm->nbi_set_result = 0; + dm->is_init_hw_info_by_rfe = false; + dm->pre_dbg_priority = DBGPORT_RELEASE; + dm->tp_active_th = 5; + dm->disable_phydm_watchdog = 0; -void -phydm_init_soft_ml_setting( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->mp_mode == false) { - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - odm_set_bb_reg(p_dm_odm, 0x19a8, MASKDWORD, 0xc10a0000); - } -#endif -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->mp_mode == false) { - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - odm_set_bb_reg(p_dm_odm, 0x19a8, BIT(31)|BIT(30)|BIT(29)|BIT(28), 0xd); - } -#endif -} + dm->u8_dummy = 0xf; + dm->u16_dummy = 0xffff; + dm->u32_dummy = 0xffffffff; -void -phydm_init_hw_info_by_rfe( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - phydm_init_hw_info_by_rfe_type_8822b(p_dm_odm); -#endif -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - phydm_init_hw_info_by_rfe_type_8821c(p_dm_odm); -#endif -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - phydm_init_hw_info_by_rfe_type_8197f(p_dm_odm); -#endif + dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE; + dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE; } -void -odm_common_info_self_init( - struct PHY_DM_STRUCT *p_dm_odm -) +void phydm_cmn_sta_info_update(void *dm_void, u8 macid) { - phydm_init_cck_setting(p_dm_odm); - p_dm_odm->rf_path_rx_enable = (u8) odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm)); -#if (DM_ODM_SUPPORT_TYPE != ODM_CE) - p_dm_odm->p_is_net_closed = &p_dm_odm->BOOLEAN_temp; - - phydm_init_debug_setting(p_dm_odm); -#endif - odm_init_mp_driver_status(p_dm_odm); - phydm_init_trx_antenna_setting(p_dm_odm); - phydm_init_soft_ml_setting(p_dm_odm); - - p_dm_odm->phydm_period = PHYDM_WATCH_DOG_PERIOD; - p_dm_odm->phydm_sys_up_time = 0; - - if (p_dm_odm->support_ic_type & ODM_IC_1SS) - p_dm_odm->num_rf_path = 1; - else if (p_dm_odm->support_ic_type & ODM_IC_2SS) - p_dm_odm->num_rf_path = 2; - else if (p_dm_odm->support_ic_type & ODM_IC_3SS) - p_dm_odm->num_rf_path = 3; - else if (p_dm_odm->support_ic_type & ODM_IC_4SS) - p_dm_odm->num_rf_path = 4; - - p_dm_odm->tx_rate = 0xFF; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct ra_sta_info *ra = NULL; - p_dm_odm->number_linked_client = 0; - p_dm_odm->pre_number_linked_client = 0; - p_dm_odm->number_active_client = 0; - p_dm_odm->pre_number_active_client = 0; + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n", + __func__); + return; + } - p_dm_odm->last_tx_ok_cnt = 0; - p_dm_odm->last_rx_ok_cnt = 0; - p_dm_odm->tx_tp = 0; - p_dm_odm->rx_tp = 0; - p_dm_odm->total_tp = 0; - p_dm_odm->traffic_load = TRAFFIC_LOW; + PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id); - p_dm_odm->nbi_set_result = 0; - p_dm_odm->is_init_hw_info_by_rfe = false; - p_dm_odm->pre_dbg_priority = BB_DBGPORT_RELEASE; + /*@[Calculate TX/RX state]*/ + if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1)) + ra->txrx_state = TX_STATE; + else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1)) + ra->txrx_state = RX_STATE; + else + ra->txrx_state = BI_DIRECTION_STATE; + ra->is_noisy = dm->noisy_decision; } -void -odm_common_info_self_update( - struct PHY_DM_STRUCT *p_dm_odm -) +void phydm_common_info_self_update(struct dm_struct *dm) { - u8 entry_cnt = 0, num_active_client = 0; - u32 i, one_entry_macid = 0, ma_rx_tp = 0; - struct sta_info *p_entry; + u8 sta_cnt = 0, num_active_client = 0; + u32 i, one_entry_macid = 0; + u32 ma_rx_tp = 0; + u32 tp_diff = 0; + struct cmn_sta_info *sta; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; + PADAPTER adapter = (PADAPTER)dm->adapter; - p_entry = p_dm_odm->p_odm_sta_info[0]; - if (p_mgnt_info->mAssoc) { - p_entry->bUsed = true; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; + + sta = dm->phydm_sta_info[0]; + if (mgnt_info->mAssoc) { + sta->dm_ctrl |= STA_DM_CTRL_ACTIVE; for (i = 0; i < 6; i++) - p_entry->MacAddr[i] = p_mgnt_info->Bssid[i]; + sta->mac_addr[i] = mgnt_info->Bssid[i]; } else if (GetFirstClientPort(adapter)) { - struct _ADAPTER *p_client_adapter = GetFirstClientPort(adapter); + //void *client_adapter = GetFirstClientPort(adapter); + struct _ADAPTER *client_adapter = GetFirstClientPort(adapter); - p_entry->bUsed = true; + sta->dm_ctrl |= STA_DM_CTRL_ACTIVE; for (i = 0; i < 6; i++) - p_entry->MacAddr[i] = p_client_adapter->MgntInfo.Bssid[i]; + sta->mac_addr[i] = client_adapter->MgntInfo.Bssid[i]; } else { - p_entry->bUsed = false; + sta->dm_ctrl = sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE); for (i = 0; i < 6; i++) - p_entry->MacAddr[i] = 0; + sta->mac_addr[i] = 0; } /* STA mode is linked to AP */ - if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[0]) && !ACTING_AS_AP(adapter)) - p_dm_odm->bsta_state = true; + if (is_sta_active(sta) && !ACTING_AS_AP(adapter)) + dm->bsta_state = true; else - p_dm_odm->bsta_state = false; -#endif - - /* THis variable cannot be used because it is wrong*/ -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (*(p_dm_odm->p_band_width) == ODM_BW40M) { - if (*(p_dm_odm->p_sec_ch_offset) == 1) - p_dm_odm->control_channel = *(p_dm_odm->p_channel) + 2; - else if (*(p_dm_odm->p_sec_ch_offset) == 2) - p_dm_odm->control_channel = *(p_dm_odm->p_channel) - 2; - } else if (*(p_dm_odm->p_band_width) == ODM_BW80M) { - if (*(p_dm_odm->p_sec_ch_offset) == 1) - p_dm_odm->control_channel = *(p_dm_odm->p_channel) + 6; - else if (*(p_dm_odm->p_sec_ch_offset) == 2) - p_dm_odm->control_channel = *(p_dm_odm->p_channel) - 6; - } else - p_dm_odm->control_channel = *(p_dm_odm->p_channel); -#else - if (*(p_dm_odm->p_band_width) == ODM_BW40M) { - if (*(p_dm_odm->p_sec_ch_offset) == 1) - p_dm_odm->control_channel = *(p_dm_odm->p_channel) - 2; - else if (*(p_dm_odm->p_sec_ch_offset) == 2) - p_dm_odm->control_channel = *(p_dm_odm->p_channel) + 2; - } else - p_dm_odm->control_channel = *(p_dm_odm->p_channel); + dm->bsta_state = false; #endif for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { - entry_cnt++; - if (entry_cnt == 1) + sta = dm->phydm_sta_info[i]; + if (is_sta_active(sta)) { + sta_cnt++; + + if (sta_cnt == 1) one_entry_macid = i; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ma_rx_tp = (p_entry->rx_byte_cnt_low_maw) << 3; /* low moving average RX TP ( bit /sec)*/ + phydm_cmn_sta_info_update(dm, (u8)i); + #if (BEAMFORMING_SUPPORT == 1) +#if 0 + /*phydm_get_txbf_device_num(dm, (u8)i);*/ +#endif + #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("ClientTP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp)); + ma_rx_tp = sta->rx_moving_average_tp + + sta->tx_moving_average_tp; + + PHYDM_DBG(dm, DBG_COMMON_FLOW, + "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp); if (ma_rx_tp > ACTIVE_TP_THRESHOLD) num_active_client++; -#endif } } - if (entry_cnt == 1) { - p_dm_odm->is_one_entry_only = true; - p_dm_odm->one_entry_macid = one_entry_macid; - } else - p_dm_odm->is_one_entry_only = false; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + dm->is_linked = (sta_cnt != 0) ? true : false; +#endif + + if (sta_cnt == 1) { + dm->is_one_entry_only = true; + dm->one_entry_macid = one_entry_macid; + dm->one_entry_tp = ma_rx_tp; + + dm->tp_active_occur = 0; + + PHYDM_DBG(dm, DBG_COMMON_FLOW, + "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n", + dm->one_entry_tp, dm->pre_one_entry_tp); + + if (dm->one_entry_tp > dm->pre_one_entry_tp && + dm->pre_one_entry_tp <= 2) { + tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp; - p_dm_odm->pre_number_linked_client = p_dm_odm->number_linked_client; - p_dm_odm->pre_number_active_client = p_dm_odm->number_active_client; + if (tp_diff > dm->tp_active_th) + dm->tp_active_occur = 1; + } + dm->pre_one_entry_tp = dm->one_entry_tp; + } else { + dm->is_one_entry_only = false; + } - p_dm_odm->number_linked_client = entry_cnt; - p_dm_odm->number_active_client = num_active_client; + dm->pre_number_linked_client = dm->number_linked_client; + dm->pre_number_active_client = dm->number_active_client; - /* Update MP driver status*/ - odm_update_mp_driver_status(p_dm_odm); + dm->number_linked_client = sta_cnt; + dm->number_active_client = num_active_client; /*Traffic load information update*/ - phydm_traffic_load_decision(p_dm_odm); + phydm_traffic_load_decision(dm); + + dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD; - p_dm_odm->phydm_sys_up_time += p_dm_odm->phydm_period; + dm->is_dfs_band = phydm_is_dfs_band(dm); + dm->phy_dbg_info.show_phy_sts_cnt = 0; } -void -odm_common_info_self_reset( - struct PHY_DM_STRUCT *p_dm_odm -) +void phydm_common_info_self_reset(struct dm_struct *dm) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_dm_odm->phy_dbg_info.num_qry_beacon_pkt = 0; -#endif + struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info; + + dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt; + dbg_t->num_qry_beacon_pkt = 0; + + dm->rxsc_l = 0xff; + dm->rxsc_20 = 0xff; + dm->rxsc_40 = 0xff; + dm->rxsc_80 = 0xff; } void * -phydm_get_structure( - struct PHY_DM_STRUCT *p_dm_odm, - u8 structure_type -) +phydm_get_structure(struct dm_struct *dm, u8 structure_type) { - void *p_struct = NULL; -#if RTL8195A_SUPPORT - switch (structure_type) { - case PHYDM_FALSEALMCNT: - p_struct = &false_alm_cnt; - break; + void *structure = NULL; - case PHYDM_CFOTRACK: - p_struct = &dm_cfo_track; + switch (structure_type) { + case PHYDM_FALSEALMCNT: + structure = &dm->false_alm_cnt; break; - case PHYDM_ADAPTIVITY: - p_struct = &(p_dm_odm->adaptivity); - break; - - default: + case PHYDM_CFOTRACK: + structure = &dm->dm_cfo_track; break; - } -#else - switch (structure_type) { - case PHYDM_FALSEALMCNT: - p_struct = &(p_dm_odm->false_alm_cnt); + case PHYDM_ADAPTIVITY: + structure = &dm->adaptivity; break; - case PHYDM_CFOTRACK: - p_struct = &(p_dm_odm->dm_cfo_track); + case PHYDM_DFS: + structure = &dm->dfs; break; - case PHYDM_ADAPTIVITY: - p_struct = &(p_dm_odm->adaptivity); - break; - - case PHYDM_DFS: - p_struct = &(p_dm_odm->dfs); - break; - default: break; } + return structure; +} + +void phydm_phy_info_update(struct dm_struct *dm) +{ +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) + dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm); #endif - return p_struct; } -void -odm_hw_setting( - struct PHY_DM_STRUCT *p_dm_odm -) +void phydm_hw_setting(struct dm_struct *dm) { #if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8821) - odm_hw_setting_8821a(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8821) + odm_hw_setting_8821a(dm); #endif #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - phydm_hwsetting_8814a(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8814A) + phydm_hwsetting_8814a(dm); #endif #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - phydm_hwsetting_8822b(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8822B) + phydm_hwsetting_8822b(dm); #endif -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - phydm_hwsetting_8197f(p_dm_odm); +#if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8812) + phydm_hwsetting_8812a(dm); #endif -} -#if SUPPORTABLITY_PHYDMLIZE -void -phydm_supportability_init( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 support_ability = 0; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; + +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) + phydm_hwsetting_8197f(dm); #endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) - if (p_dm_odm->support_ic_type != ODM_RTL8821C) - return; +#if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8192F) + phydm_hwsetting_8192f(dm); #endif +} - switch (p_dm_odm->support_ic_type) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +u64 phydm_supportability_init_win( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; - /*---------------N Series--------------------*/ - case ODM_RTL8188E: + switch (dm->support_ic_type) { +/*@---------------N Series--------------------*/ +#if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: support_ability |= - ODM_BB_DIG | - ODM_BB_RA_MASK | - ODM_BB_DYNAMIC_TXPWR | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_CCK_PD | - ODM_RF_TX_PWR_TRACK | - ODM_RF_RX_GAIN_TRACK | - ODM_RF_CALIBRATION | - ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT | + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | ODM_BB_PRIMARY_CCA; break; +#endif - case ODM_RTL8192E: +#if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: support_ability |= - ODM_BB_DIG | - ODM_RF_TX_PWR_TRACK | - ODM_BB_RA_MASK | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_CFO_TRACKING | - /* ODM_BB_PWR_TRAIN |*/ - ODM_BB_NHM_CNT | + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | ODM_BB_PRIMARY_CCA; break; +#endif - case ODM_RTL8723B: - support_ability |= - ODM_BB_DIG | - ODM_BB_RA_MASK | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_CCK_PD | - ODM_RF_TX_PWR_TRACK | - ODM_RF_RX_GAIN_TRACK | - ODM_RF_CALIBRATION | - ODM_BB_CFO_TRACKING | - /* ODM_BB_PWR_TRAIN |*/ - ODM_BB_NHM_CNT; - break; - - case ODM_RTL8703B: - support_ability |= - ODM_BB_DIG | - ODM_BB_RA_MASK | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_CCK_PD | - ODM_BB_CFO_TRACKING | - /* ODM_BB_PWR_TRAIN | */ - ODM_BB_NHM_CNT | - ODM_RF_TX_PWR_TRACK | - /* ODM_RF_RX_GAIN_TRACK | */ - ODM_RF_CALIBRATION; - break; - - case ODM_RTL8723D: - support_ability |= - ODM_BB_DIG | - ODM_BB_RA_MASK | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_CCK_PD | - ODM_BB_CFO_TRACKING | - /* ODM_BB_PWR_TRAIN | */ - ODM_BB_NHM_CNT | - ODM_RF_TX_PWR_TRACK; - /* ODM_RF_RX_GAIN_TRACK | */ - /* ODM_RF_CALIBRATION | */ - break; -/* JJ ADD 20161014 */ - case ODM_RTL8710B: - support_ability |= - ODM_BB_DIG | - ODM_BB_RA_MASK | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_CCK_PD | - ODM_BB_CFO_TRACKING | - /* ODM_BB_PWR_TRAIN | */ - ODM_BB_NHM_CNT | - ODM_RF_TX_PWR_TRACK; - /* ODM_RF_RX_GAIN_TRACK | */ - /* ODM_RF_CALIBRATION | */ - break; - - case ODM_RTL8188F: +#if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: support_ability |= - ODM_BB_DIG | - ODM_BB_RA_MASK | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_CCK_PD | - ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT | - ODM_RF_TX_PWR_TRACK | - ODM_RF_CALIBRATION; - break; - - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - case ODM_RTL8198F: - case ODM_RTL8197F: - support_ability |= - ODM_BB_DIG | - ODM_BB_RA_MASK | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_CCK_PD | - ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT | - ODM_RF_TX_PWR_TRACK | - ODM_RF_CALIBRATION; - break; - #endif - - #if (DM_ODM_SUPPORT_TYPE & (ODM_IOT)) - case ODM_RTL8195A: - support_ability |= - ODM_BB_DIG | - ODM_BB_RA_MASK | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_CCK_PD | - ODM_BB_CFO_TRACKING | - ODM_BB_NHM_CNT | - ODM_RF_TX_PWR_TRACK | - ODM_RF_CALIBRATION; + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; break; - #endif - - /*---------------AC Series-------------------*/ +#endif - case ODM_RTL8812: - case ODM_RTL8821: - case ODM_RTL8881A: +#if (RTL8703B_SUPPORT == 1) + case ODM_RTL8703B: support_ability |= - ODM_BB_DIG | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_RA_MASK | - ODM_RF_TX_PWR_TRACK | - ODM_BB_CFO_TRACKING | - /* ODM_BB_PWR_TRAIN |*/ - ODM_BB_DYNAMIC_TXPWR | - ODM_BB_NHM_CNT; + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; break; +#endif - case ODM_RTL8814B: - case ODM_RTL8814A: +#if (RTL8723D_SUPPORT == 1) + case ODM_RTL8723D: support_ability |= - ODM_BB_DIG | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_RA_MASK | - ODM_RF_TX_PWR_TRACK | - ODM_BB_CCK_PD | - ODM_BB_CFO_TRACKING | - ODM_BB_DYNAMIC_TXPWR | - ODM_BB_NHM_CNT; + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_PWR_TRAIN | + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; break; +#endif - case ODM_RTL8822B: +#if (RTL8710B_SUPPORT == 1) + case ODM_RTL8710B: support_ability |= - ODM_BB_DIG | - ODM_BB_FA_CNT | - ODM_BB_CCK_PD | - ODM_BB_CFO_TRACKING | - ODM_BB_RATE_ADAPTIVE | - ODM_BB_RSSI_MONITOR | - ODM_BB_RA_MASK | - ODM_RF_TX_PWR_TRACK; + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_PWR_TRAIN | + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; break; +#endif - case ODM_RTL8821C: +#if (RTL8188F_SUPPORT == 1) + case ODM_RTL8188F: support_ability |= - ODM_BB_DIG | - ODM_BB_RA_MASK | - ODM_BB_CCK_PD | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_RATE_ADAPTIVE | - ODM_RF_TX_PWR_TRACK | - ODM_BB_CFO_TRACKING; /* | - * ODM_BB_DYNAMIC_TXPWR | - * ODM_BB_NHM_CNT;*/ + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; break; +#endif - default: +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: support_ability |= - ODM_BB_DIG | - ODM_BB_FA_CNT | - ODM_BB_CCK_PD | - ODM_BB_CFO_TRACKING | - ODM_BB_RATE_ADAPTIVE | - ODM_BB_RSSI_MONITOR | - ODM_BB_RA_MASK | - ODM_RF_TX_PWR_TRACK; + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_PWR_TRAIN | + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ADAPTIVE_SOML | + ODM_BB_ENV_MONITOR; + /*ODM_BB_LNA_SAT_CHK |*/ + /*ODM_BB_PRIMARY_CCA*/ - dbg_print("[Warning] Supportability Init Warning !!!\n"); break; +#endif - } - - if (*(p_dm_odm->p_enable_antdiv)) - support_ability |= ODM_BB_ANT_DIV; - - if (*(p_dm_odm->p_enable_adaptivity)) { +/*@---------------AC Series-------------------*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM adaptivity is set to Enabled!!!\n")); +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + case ODM_RTL8812: + case ODM_RTL8821: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif - support_ability |= ODM_BB_ADAPTIVITY; +#if (RTL8814A_SUPPORT == 1) + case ODM_RTL8814A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif - #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, p_mgnt_info->RegEnableCarrierSense); - phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_DCBACKOFF, p_mgnt_info->RegDCbackoff); - phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, p_mgnt_info->RegDmLinkAdaptivity); - phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_AP_NUM_TH, p_mgnt_info->RegAPNumTH); - phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_TH_L2H_INI, p_mgnt_info->RegL2HForAdaptivity); - phydm_adaptivity_info_init(p_dm_odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, p_mgnt_info->RegHLDiffForAdaptivity); - #endif - - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM adaptivity is set to disnabled!!!\n")); - /**/ +#if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + /*ODM_BB_ADAPTIVE_SOML |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + + pr_debug("[Warning] Supportability Init Warning !!!\n"); + break; } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHYDM support_ability = ((0x%x))\n", support_ability)); - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ABILITY, support_ability); + + return support_ability; } #endif -/* - * 2011/09/21 MH Add to describe different team necessary resource allocate?? - * */ -void -odm_dm_init( - struct PHY_DM_STRUCT *p_dm_odm -) +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +u64 phydm_supportability_init_ce(void *dm_void) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; + + switch (dm->support_ic_type) { +/*@---------------N Series--------------------*/ +#if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; +#endif + +#if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; #endif -#if SUPPORTABLITY_PHYDMLIZE - phydm_supportability_init(p_dm_odm); +#if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; #endif - odm_common_info_self_init(p_dm_odm); - odm_dig_init(p_dm_odm); - phydm_nhm_counter_statistics_init(p_dm_odm); - phydm_adaptivity_init(p_dm_odm); - phydm_ra_info_init(p_dm_odm); - odm_rate_adaptive_mask_init(p_dm_odm); - odm_cfo_tracking_init(p_dm_odm); -#if PHYDM_SUPPORT_EDCA - odm_edca_turbo_init(p_dm_odm); + +#if (RTL8703B_SUPPORT == 1) + case ODM_RTL8703B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8723D_SUPPORT == 1) + case ODM_RTL8723D: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_PWR_TRAIN | + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8710B_SUPPORT == 1) + case ODM_RTL8710B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8188F_SUPPORT == 1) + case ODM_RTL8188F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_PWR_TRAIN | + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + /*@ODM_BB_ADAPTIVE_SOML |*/ + ODM_BB_ENV_MONITOR; + /*@ODM_BB_LNA_SAT_CHK |*/ + /*@ODM_BB_PRIMARY_CCA*/ + break; +#endif +/*@---------------AC Series-------------------*/ + +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + case ODM_RTL8812: + case ODM_RTL8821: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8814A_SUPPORT == 1) + case ODM_RTL8814A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; #endif - odm_rssi_monitor_init(p_dm_odm); - phydm_rf_init(p_dm_odm); - odm_txpowertracking_init(p_dm_odm); #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - phydm_txcurrentcalibration(p_dm_odm); -#endif - - odm_antenna_diversity_init(p_dm_odm); -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path_init(p_dm_odm); -#endif - odm_auto_channel_select_init(p_dm_odm); - odm_path_diversity_init(p_dm_odm); - odm_dynamic_tx_power_init(p_dm_odm); - phydm_init_ra_info(p_dm_odm); -#if (PHYDM_LA_MODE_SUPPORT == 1) - adc_smp_init(p_dm_odm); + case ODM_RTL8822B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; #endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - #ifdef BEAMFORMING_VERSION_1 - if (p_hal_data->beamforming_version == BEAMFORMING_VERSION_1) - #endif - { - phydm_beamforming_init(p_dm_odm); +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + + pr_debug("[Warning] Supportability Init Warning !!!\n"); + break; } + + return support_ability; +} #endif - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - #if (defined(CONFIG_BB_POWER_SAVING)) - odm_dynamic_bb_power_saving_init(p_dm_odm); - #endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +u64 phydm_supportability_init_ap( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; - #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - odm_primary_cca_init(p_dm_odm); - odm_ra_info_init_all(p_dm_odm); - } - #endif + switch (dm->support_ic_type) { +/*@---------------N Series--------------------*/ +#if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; +#endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; +#endif - #if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) - odm_sw_ant_detect_init(p_dm_odm); - #endif +#if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif - #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) - odm_primary_cca_check_init(p_dm_odm); - #endif +#if ((RTL8198F_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) + case ODM_RTL8198F: + support_ability |= + /*ODM_BB_DIG |*/ + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR; + /*ODM_BB_CCK_PD |*/ + /*ODM_BB_PWR_TRAIN |*/ + /*ODM_BB_RATE_ADAPTIVE |*/ + /*ODM_BB_CFO_TRACKING |*/ + /*ODM_BB_ADAPTIVE_SOML |*/ + /*ODM_BB_ENV_MONITOR |*/ + /*ODM_BB_LNA_SAT_CHK |*/ + /*ODM_BB_PRIMARY_CCA;*/ + break; + case ODM_RTL8197F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ADAPTIVE_SOML | + ODM_BB_ENV_MONITOR | + ODM_BB_LNA_SAT_CHK | + ODM_BB_PRIMARY_CCA; + break; +#endif +#if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + /*ODM_BB_CFO_TRACKING |*/ + ODM_BB_ADAPTIVE_SOML | + /*ODM_BB_ENV_MONITOR |*/ + /*ODM_BB_LNA_SAT_CHK |*/ + /*ODM_BB_PRIMARY_CCA |*/ + 0; + break; +#endif + +/*@---------------AC Series-------------------*/ + +#if (RTL8881A_SUPPORT == 1) + case ODM_RTL8881A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; #endif +#if (RTL8814A_SUPPORT == 1) + case ODM_RTL8814A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8814B_SUPPORT == 1) + case ODM_RTL8814B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8822B_SUPPORT == 1) + case ODM_RTL8822B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + /*ODM_BB_ADAPTIVE_SOML |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + + break; +#endif + + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + + pr_debug("[Warning] Supportability Init Warning !!!\n"); + break; } - #if (CONFIG_PSD_TOOL == 1) - phydm_psd_init(p_dm_odm); - #endif +#if 0 + /*@[Config Antenna Diveristy]*/ + if (*dm->enable_antdiv) + support_ability |= ODM_BB_ANT_DIV; + + /*@[Config Adaptivity]*/ + if (*dm->enable_adaptivity) + support_ability |= ODM_BB_ADAPTIVITY; +#endif + + return support_ability; +} +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT)) +u64 phydm_supportability_init_iot( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; + + switch (dm->support_ic_type) { +#if (RTL8710B_SUPPORT == 1) + case ODM_RTL8710B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8195A_SUPPORT == 1) + case ODM_RTL8195A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + + pr_debug("[Warning] Supportability Init Warning !!!\n"); + break; + } + + return support_ability; +} +#endif + +void phydm_fwoffload_ability_init(struct dm_struct *dm, + enum phydm_offload_ability offload_ability) +{ + switch (offload_ability) { + case PHYDM_PHY_PARAM_OFFLOAD: + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) + dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD; + break; + + case PHYDM_RF_IQK_OFFLOAD: + dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD; + break; + + default: + PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n"); + break; + } + + PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n", + dm->fw_offload_ability); +} + +void phydm_fwoffload_ability_clear(struct dm_struct *dm, + enum phydm_offload_ability offload_ability) +{ + switch (offload_ability) { + case PHYDM_PHY_PARAM_OFFLOAD: + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) + dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD); + break; + + case PHYDM_RF_IQK_OFFLOAD: + dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD); + break; + + default: + PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n"); + break; + } + + PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n", + dm->fw_offload_ability); +} + +void phydm_supportability_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability; + + if (*dm->mp_mode) { + support_ability = 0; + } else { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + support_ability = phydm_supportability_init_win(dm); + #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + support_ability = phydm_supportability_init_ap(dm); + #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) + support_ability = phydm_supportability_init_ce(dm); + #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) + support_ability = phydm_supportability_init_iot(dm); + #endif + + /*@[Config Antenna Diveristy]*/ + if (IS_FUNC_EN(dm->enable_antdiv)) + support_ability |= ODM_BB_ANT_DIV; + /*@[Config Adaptive SOML]*/ + if (IS_FUNC_EN(dm->en_adap_soml)) + support_ability |= ODM_BB_ADAPTIVE_SOML; + + /*@[Config Adaptivity]*/ + if (IS_FUNC_EN(dm->enable_adaptivity)) + support_ability |= ODM_BB_ADAPTIVITY; + } + odm_cmn_info_init(dm, ODM_CMNINFO_ABILITY, support_ability); + PHYDM_DBG(dm, ODM_COMP_INIT, + "IC = ((0x%x)), Supportability Init = ((0x%llx))\n", + dm->support_ic_type, dm->support_ability); } -void -odm_dm_reset( - struct PHY_DM_STRUCT *p_dm_odm -) +void phydm_rfe_init(void *dm_void) { - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; - odm_ant_div_reset(p_dm_odm); - phydm_set_edcca_threshold_api(p_dm_odm, p_dm_dig_table->cur_ig_value); + PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n"); +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) + phydm_rfe_8822b_init(dm); +#endif } +void phydm_dm_early_init(struct dm_struct *dm) +{ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + halrf_init(dm); + #endif +} -void -phydm_support_ability_debug( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) +void odm_dm_init(struct dm_struct *dm) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 pre_support_ability; + halrf_init(dm); + phydm_supportability_init(dm); + phydm_rfe_init(dm); + phydm_common_info_self_init(dm); + phydm_rx_phy_status_init(dm); +#ifdef PHYDM_AUTO_DEGBUG + phydm_auto_dbg_engine_init(dm); +#endif + phydm_dig_init(dm); +#ifdef PHYDM_SUPPORT_CCKPD + phydm_cck_pd_init(dm); +#endif + phydm_env_monitor_init(dm); + phydm_adaptivity_init(dm); + phydm_ra_info_init(dm); + phydm_rssi_monitor_init(dm); + phydm_cfo_tracking_init(dm); + phydm_rf_init(dm); + phydm_dc_cancellation(dm); +#ifdef PHYDM_TXA_CALIBRATION + phydm_txcurrentcalibration(dm); + phydm_get_pa_bias_offset(dm); +#endif +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + odm_antenna_diversity_init(dm); +#endif +#ifdef CONFIG_ADAPTIVE_SOML + phydm_adaptive_soml_init(dm); +#endif +#ifdef CONFIG_PATH_DIVERSITY + phydm_path_diversity_init(dm); +#endif +#ifdef CONFIG_DYNAMIC_TX_TWR + phydm_dynamic_tx_power_init(dm); +#endif +#if (PHYDM_LA_MODE_SUPPORT == 1) + adc_smp_init(dm); +#endif + +#ifdef PHYDM_BEAMFORMING_VERSION1 + phydm_beamforming_init(dm); +#endif + +#if (RTL8188E_SUPPORT == 1) + odm_ra_info_init_all(dm); +#endif +#ifdef PHYDM_PRIMARY_CCA + phydm_primary_cca_init(dm); +#endif +#ifdef CONFIG_PSD_TOOL + phydm_psd_init(dm); +#endif + +#ifdef CONFIG_SMART_ANTENNA + phydm_smt_ant_init(dm); +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + phydm_lna_sat_check_init(dm); +#endif +#ifdef CONFIG_MCC_DM + #if (RTL8822B_SUPPORT == 1) + phydm_mcc_init(dm); + #endif +#endif +} + +void odm_dm_reset(struct dm_struct *dm) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + odm_ant_div_reset(dm); + #endif + phydm_set_edcca_threshold_api(dm, dig_t->cur_ig_value); +} + +void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 dm_value[10] = {0}; + u64 pre_support_ability, one = 1; + u64 comp = 0; u32 used = *_used; u32 out_len = *_out_len; + u8 i; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]); + } + + pre_support_ability = dm->support_ability; + comp = dm->support_ability; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n================================\n"); - pre_support_ability = p_dm_odm->support_ability ; - PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output + used, out_len - used, "[Supportability] PhyDM Selection\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((p_dm_odm->support_ability & ODM_BB_DIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((p_dm_odm->support_ability & ODM_BB_RA_MASK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((p_dm_odm->support_ability & ODM_BB_FA_CNT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))CCK_PD\n", ((p_dm_odm->support_ability & ODM_BB_CCK_PD) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))PWR_TRAIN\n", ((p_dm_odm->support_ability & ODM_BB_PWR_TRAIN) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((p_dm_odm->support_ability & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((p_dm_odm->support_ability & ODM_BB_PATH_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "13. (( %s ))ADAPTIVITY\n", ((p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))struct _CFO_TRACKING_\n", ((p_dm_odm->support_ability & ODM_BB_CFO_TRACKING) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))NHM_CNT\n", ((p_dm_odm->support_ability & ODM_BB_NHM_CNT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))PRIMARY_CCA\n", ((p_dm_odm->support_ability & ODM_BB_PRIMARY_CCA) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))TXBF\n", ((p_dm_odm->support_ability & ODM_BB_TXBF) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))DYNAMIC_ARFR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))EDCA_TURBO\n", ((p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "21. (( %s ))DYNAMIC_RX_PATH\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "24. (( %s ))TX_PWR_TRACK\n", ((p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "25. (( %s ))RX_GAIN_TRACK\n", ((p_dm_odm->support_ability & ODM_RF_RX_GAIN_TRACK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "26. (( %s ))RF_CALIBRATION\n", ((p_dm_odm->support_ability & ODM_RF_CALIBRATION) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Supportability] PhyDM Selection\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))DIG\n", + ((comp & ODM_BB_DIG) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))RA_MASK\n", + ((comp & ODM_BB_RA_MASK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "02. (( %s ))DYN_TXPWR\n", + ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "03. (( %s ))FA_CNT\n", + ((comp & ODM_BB_FA_CNT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "04. (( %s ))RSSI_MNTR\n", + ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "05. (( %s ))CCK_PD\n", + ((comp & ODM_BB_CCK_PD) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "06. (( %s ))ANT_DIV\n", + ((comp & ODM_BB_ANT_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "07. (( %s ))SMT_ANT\n", + ((comp & ODM_BB_SMT_ANT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "08. (( %s ))PWR_TRAIN\n", + ((comp & ODM_BB_PWR_TRAIN) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "09. (( %s ))RA\n", + ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "10. (( %s ))PATH_DIV\n", + ((comp & ODM_BB_PATH_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "11. (( %s ))DFS\n", + ((comp & ODM_BB_DFS) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "12. (( %s ))DYN_ARFR\n", + ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "13. (( %s ))ADAPTIVITY\n", + ((comp & ODM_BB_ADAPTIVITY) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "14. (( %s ))CFO_TRACK\n", + ((comp & ODM_BB_CFO_TRACKING) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "15. (( %s ))ENV_MONITOR\n", + ((comp & ODM_BB_ENV_MONITOR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "16. (( %s ))PRI_CCA\n", + ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "17. (( %s ))ADPTV_SOML\n", + ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "18. (( %s ))LNA_SAT_CHK\n", + ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : ("."))); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Supportability] PhyDM offload ability\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))PHY PARAM OFFLOAD\n", + ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ? + ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))RF IQK OFFLOAD\n", + ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? + ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + + } else if (dm_value[0] == 101) { + dm->support_ability = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable all support_ability components\n"); + } else { + if (dm_value[1] == 1) { /* @enable */ + dm->support_ability |= (one << dm_value[0]); + } else if (dm_value[1] == 2) {/* @disable */ + dm->support_ability &= ~(one << dm_value[0]); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Warning!!!] 1:enable, 2:disable\n"); + } } - /* - else if(dm_value[0] == 101) - { - p_dm_odm->support_ability = 0 ; - dbg_print("Disable all support_ability components\n"); - PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all support_ability components")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "pre-supportability = 0x%llx\n", pre_support_ability); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Cur-supportability = 0x%llx\n", dm->support_ability); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + + *_used = used; + *_out_len = out_len; +} + +void phydm_watchdog_lps_32k(struct dm_struct *dm) +{ + PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__); + + phydm_common_info_self_update(dm); + phydm_rssi_monitor_check(dm); + phydm_dig_lps_32k(dm); + phydm_common_info_self_reset(dm); +} + +void phydm_watchdog_lps(struct dm_struct *dm) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__); + + phydm_common_info_self_update(dm); + phydm_rssi_monitor_check(dm); + phydm_basic_dbg_message(dm); + phydm_receiver_blocking(dm); + phydm_false_alarm_counter_statistics(dm); + phydm_dig_by_rssi_lps(dm); + #ifdef PHYDM_SUPPORT_CCKPD + phydm_cck_pd_th(dm); + #endif + phydm_adaptivity(dm); + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + /*@enable AntDiv in PS mode, request from SD4 Jeff*/ + odm_antenna_diversity(dm); + #endif + #endif + phydm_common_info_self_reset(dm); +#endif +} + +void phydm_watchdog_mp(struct dm_struct *dm) +{ +} + +void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (pause_type == PHYDM_PAUSE) { + dm->disable_phydm_watchdog = 1; + PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n"); + } else { + dm->disable_phydm_watchdog = 0; + PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n"); } - */ - else { +} + +u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_lv, u8 val_lehgth, + u32 *val_buf) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_func_poiner *func_t = &dm->phydm_func_handler; + s8 *pause_lv_pre = &dm->s8_dummy; + u32 *bkp_val = &dm->u32_dummy; + u32 ori_val[5] = {0}; + u64 pause_func_bitmap = (u64)BIT(pause_func); + u8 i; + u8 en_2rcca; + u8 en_bw40m; + u8 pause_result = PAUSE_FAIL; + + PHYDM_DBG(dm, ODM_COMP_API, "\n"); + PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__, + ((pause_type == PHYDM_PAUSE) ? "Pause" : + ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")), + pause_lv, val_lehgth); + + if (pause_lv >= PHYDM_PAUSE_MAX_NUM) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv); + return PAUSE_FAIL; + } + + if (pause_func == F00_DIG) { + PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n"); + + if (val_lehgth != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n"); + return PAUSE_FAIL; + } + + ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value); /*@0xc50*/ + pause_lv_pre = &dm->pause_lv_table.lv_dig; + bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val); + /*@function pointer hook*/ + func_t->pause_phydm_handler = phydm_set_dig_val; + +#ifdef PHYDM_SUPPORT_CCKPD + } else if (pause_func == F05_CCK_PD) { + PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n"); + + if (val_lehgth != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n"); + return PAUSE_FAIL; + } - if (dm_value[1] == 1) { /* enable */ - p_dm_odm->support_ability |= BIT(dm_value[0]) ; - if (BIT(dm_value[0]) & ODM_BB_PATH_DIV) - odm_path_diversity_init(p_dm_odm); - } else if (dm_value[1] == 2) /* disable */ - p_dm_odm->support_ability &= ~(BIT(dm_value[0])) ; - else { - /* dbg_print("\n[Warning!!!] 1:enable, 2:disable \n\n"); */ - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); + ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv; + pause_lv_pre = &dm->pause_lv_table.lv_cckpd; + bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val); + /*@function pointer hook*/ + func_t->pause_phydm_handler = phydm_set_cckpd_val; +#endif + +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + } else if (pause_func == F06_ANT_DIV) { + PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n"); + + if (val_lehgth != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n"); + return PAUSE_FAIL; } + /*@default antenna*/ + ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant); + pause_lv_pre = &dm->pause_lv_table.lv_antdiv; + bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val); + /*@function pointer hook*/ + func_t->pause_phydm_handler = phydm_set_antdiv_val; + +#endif +#ifdef PHYDM_SUPPORT_ADAPTIVITY + } else if (pause_func == F13_ADPTVTY) { + PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n"); + + if (val_lehgth != 2) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n"); + return PAUSE_FAIL; + } + + ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/ + ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/ + pause_lv_pre = &dm->pause_lv_table.lv_adapt; + bkp_val = (u32 *)(&dm->adaptivity.rvrt_val); + /*@function pointer hook*/ + func_t->pause_phydm_handler = phydm_set_edcca_val; + +#endif +#ifdef CONFIG_ADAPTIVE_SOML + } else if (pause_func == F17_ADPTV_SOML) { + PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n"); + + if (val_lehgth != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n"); + return PAUSE_FAIL; + } + /*SOML_ON/OFF*/ + ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off); + + pause_lv_pre = &dm->pause_lv_table.lv_adsl; + bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val); + /*@function pointer hook*/ + func_t->pause_phydm_handler = phydm_set_adsl_val; + +#endif + } else { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n"); + return PAUSE_FAIL; + } + + PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n", + pause_lv, *pause_lv_pre); + + if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) { + if (pause_lv <= *pause_lv_pre) { + PHYDM_DBG(dm, ODM_COMP_API, + "[PAUSE FAIL] Pre_LV >= Curr_LV\n"); + return PAUSE_FAIL; + } + + if (!(dm->pause_ability & pause_func_bitmap)) { + for (i = 0; i < val_lehgth; i++) + bkp_val[i] = ori_val[i]; + } + + dm->pause_ability |= pause_func_bitmap; + PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n", + dm->pause_ability); + + if (pause_type == PHYDM_PAUSE) { + for (i = 0; i < val_lehgth; i++) + PHYDM_DBG(dm, ODM_COMP_API, + "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n", + i, val_buf[i], bkp_val[i]); + func_t->pause_phydm_handler(dm, val_buf, val_lehgth); + } else { + for (i = 0; i < val_lehgth; i++) + PHYDM_DBG(dm, ODM_COMP_API, + "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n", + i, bkp_val[i]); + } + + *pause_lv_pre = pause_lv; + pause_result = PAUSE_SUCCESS; + + } else if (pause_type == PHYDM_RESUME) { + if ((dm->pause_ability & pause_func_bitmap) == 0) { + PHYDM_DBG(dm, ODM_COMP_API, + "[RESUME] No Need to Revert\n"); + return PAUSE_SUCCESS; + } + + dm->pause_ability &= ~pause_func_bitmap; + PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n", + dm->pause_ability); + + *pause_lv_pre = PHYDM_PAUSE_RELEASE; + + for (i = 0; i < val_lehgth; i++) { + PHYDM_DBG(dm, ODM_COMP_API, + "[RESUME] val_idx[%d]={0x%x}\n", i, + bkp_val[i]); + } + + func_t->pause_phydm_handler(dm, bkp_val, val_lehgth); + + pause_result = PAUSE_SUCCESS; + } else { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n"); + pause_result = PAUSE_FAIL; + } + return pause_result; +} + +void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i; + u8 length = 0; + u32 buf[5] = {0}; + u8 set_result = 0; + enum phydm_func_idx func = 0; + enum phydm_pause_type type = 0; + enum phydm_pause_level lv = 0; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n"); + + goto out; + } + + for (i = 0; i < 10; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + } + + func = (enum phydm_func_idx)var1[0]; + type = (enum phydm_pause_type)var1[1]; + lv = (enum phydm_pause_level)var1[2]; + + for (i = 0; i < 5; i++) + buf[i] = var1[3 + i]; + + if (func == F00_DIG) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[DIG]\n"); + length = 1; + + } else if (func == F05_CCK_PD) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[CCK_PD]\n"); + length = 1; + } else if (func == F06_ANT_DIV) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Ant_Div]\n"); + length = 1; + } else if (func == F13_ADPTVTY) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Adaptivity]\n"); + length = 2; + } else if (func == F17_ADPTV_SOML) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ADSL]\n"); + length = 1; + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Set Function Error]\n"); + length = 0; + } + + if (length != 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{%s, lv=%d} val = %d, %d}\n", + ((type == PHYDM_PAUSE) ? "Pause" : + ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")), + lv, var1[3], var1[4]); + + set_result = phydm_pause_func(dm, func, type, lv, length, buf); } - PHYDM_SNPRINTF((output + used, out_len - used, "pre-support_ability = 0x%x\n", pre_support_ability)); - PHYDM_SNPRINTF((output + used, out_len - used, "Curr-support_ability = 0x%x\n", p_dm_odm->support_ability)); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); -} -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -/* - * tmp modify for LC Only - * */ -void -odm_dm_watchdog_lps( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - odm_common_info_self_update(p_dm_odm); - odm_false_alarm_counter_statistics(p_dm_odm); - odm_rssi_monitor_check(p_dm_odm); - odm_dig_by_rssi_lps(p_dm_odm); - odm_cck_packet_detection_thresh(p_dm_odm); - odm_common_info_self_reset(p_dm_odm); - - if (*(p_dm_odm->p_is_power_saving) == true) - return; -} -#endif + PDM_SNPF(out_len, used, output + used, out_len - used, + "set_result = %d\n", set_result); -void -phydm_watchdog_mp( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path_caller(p_dm_odm); -#endif +out: + *_used = used; + *_out_len = out_len; } -/* - * 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. - * You can not add any dummy function here, be care, you can only use DM structure - * to perform any new ODM_DM. - * */ -void -odm_dm_watchdog( - struct PHY_DM_STRUCT *p_dm_odm -) + +u8 phydm_stop_dm_watchdog_check(void *dm_void) { - odm_common_info_self_update(p_dm_odm); - phydm_basic_dbg_message(p_dm_odm); - phydm_receiver_blocking(p_dm_odm); - odm_hw_setting(p_dm_odm); + struct dm_struct *dm = (struct dm_struct *)dm_void; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - { - struct rtl8192cd_priv *priv = p_dm_odm->priv; - if ((priv->auto_channel != 0) && (priv->auto_channel != 2)) /* if struct _ACS_ running, do not do FA/CCA counter read */ - return; + if (dm->disable_phydm_watchdog == 1) { + PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n"); + return true; + } else { + return false; } -#endif - odm_false_alarm_counter_statistics(p_dm_odm); - phydm_noisy_detection(p_dm_odm); +} - odm_rssi_monitor_check(p_dm_odm); +void phydm_watchdog(struct dm_struct *dm) +{ + PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__); - if (*(p_dm_odm->p_is_power_saving) == true) { - odm_dig_by_rssi_lps(p_dm_odm); - phydm_adaptivity(p_dm_odm); -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - odm_antenna_diversity(p_dm_odm); /*enable AntDiv in PS mode, request from SD4 Jeff*/ + phydm_common_info_self_update(dm); + phydm_phy_info_update(dm); + phydm_rssi_monitor_check(dm); + phydm_basic_dbg_message(dm); + phydm_dm_summary(dm, FIRST_MACID); +#ifdef PHYDM_AUTO_DEGBUG + phydm_auto_dbg_engine(dm); #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("DMWatchdog in power saving mode\n")); + phydm_receiver_blocking(dm); + + if (phydm_stop_dm_watchdog_check(dm) == true) return; - } - phydm_check_adaptivity(p_dm_odm); - odm_update_power_training_state(p_dm_odm); - odm_DIG(p_dm_odm); - phydm_adaptivity(p_dm_odm); - odm_cck_packet_detection_thresh(p_dm_odm); + phydm_hw_setting(dm); + + #ifdef PHYDM_TDMA_DIG_SUPPORT + if (dm->original_dig_restore == 0) + phydm_tdma_dig_timer_check(dm); + else + #endif + { + phydm_false_alarm_counter_statistics(dm); + phydm_noisy_detection(dm); + phydm_dig(dm); + #ifdef PHYDM_SUPPORT_CCKPD + phydm_cck_pd_th(dm); + #endif + } - phydm_ra_info_watchdog(p_dm_odm); -#if PHYDM_SUPPORT_EDCA - odm_edca_turbo_check(p_dm_odm); +#ifdef PHYDM_POWER_TRAINING_SUPPORT + phydm_update_power_training_state(dm); #endif - odm_path_diversity(p_dm_odm); - odm_cfo_tracking(p_dm_odm); - odm_dynamic_tx_power(p_dm_odm); - odm_antenna_diversity(p_dm_odm); -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path(p_dm_odm); + phydm_adaptivity(dm); + phydm_ra_info_watchdog(dm); +#ifdef CONFIG_PATH_DIVERSITY + odm_path_diversity(dm); #endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - phydm_beamforming_watchdog(p_dm_odm); + phydm_cfo_tracking(dm); +#ifdef CONFIG_DYNAMIC_TX_TWR + phydm_dynamic_tx_power(dm); #endif - - phydm_rf_watchdog(p_dm_odm); - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - -#if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - odm_dynamic_primary_cca(p_dm_odm); +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + odm_antenna_diversity(dm); #endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - -#if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) - odm_dynamic_primary_cca_check(p_dm_odm); +#ifdef CONFIG_ADAPTIVE_SOML + phydm_adaptive_soml(dm); #endif + +#ifdef PHYDM_BEAMFORMING_VERSION1 + phydm_beamforming_watchdog(dm); #endif - } + halrf_watchdog(dm); +#ifdef PHYDM_PRIMARY_CCA + phydm_primary_cca(dm); +#endif #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - odm_dtc(p_dm_odm); + odm_dtc(dm); #endif - odm_common_info_self_reset(p_dm_odm); + phydm_env_mntr_watchdog(dm); +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + phydm_lna_sat_chk_watchdog(dm); +#endif +#ifdef CONFIG_MCC_DM + #if (RTL8822B_SUPPORT == 1) + phydm_mcc_switch(dm); + #endif +#endif + phydm_common_info_self_reset(dm); } - -/* +/*@ * Init /.. Fixed HW value. Only init time. - * */ -void -odm_cmn_info_init( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, - u32 value -) + */ +void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, + u64 value) { - /* */ /* This section is used for init value */ - /* */ - switch (cmn_info) { - /* */ - /* Fixed ODM value. */ - /* */ - case ODM_CMNINFO_ABILITY: - p_dm_odm->support_ability = (u32)value; + switch (cmn_info) { + /* @Fixed ODM value. */ + case ODM_CMNINFO_ABILITY: + dm->support_ability = (u64)value; break; - case ODM_CMNINFO_RF_TYPE: - p_dm_odm->rf_type = (u8)value; + case ODM_CMNINFO_RF_TYPE: + dm->rf_type = (u8)value; break; - case ODM_CMNINFO_PLATFORM: - p_dm_odm->support_platform = (u8)value; + case ODM_CMNINFO_PLATFORM: + dm->support_platform = (u8)value; break; - case ODM_CMNINFO_INTERFACE: - p_dm_odm->support_interface = (u8)value; + case ODM_CMNINFO_INTERFACE: + dm->support_interface = (u8)value; break; - case ODM_CMNINFO_MP_TEST_CHIP: - p_dm_odm->is_mp_chip = (u8)value; + case ODM_CMNINFO_MP_TEST_CHIP: + dm->is_mp_chip = (u8)value; break; - case ODM_CMNINFO_IC_TYPE: - p_dm_odm->support_ic_type = value; + case ODM_CMNINFO_IC_TYPE: + dm->support_ic_type = (u32)value; break; - case ODM_CMNINFO_CUT_VER: - p_dm_odm->cut_version = (u8)value; + case ODM_CMNINFO_CUT_VER: + dm->cut_version = (u8)value; break; - case ODM_CMNINFO_FAB_VER: - p_dm_odm->fab_version = (u8)value; + case ODM_CMNINFO_FAB_VER: + dm->fab_version = (u8)value; break; - - case ODM_CMNINFO_RFE_TYPE: - p_dm_odm->rfe_type = (u8)value; - phydm_init_hw_info_by_rfe(p_dm_odm); + case ODM_CMNINFO_FW_VER: + dm->fw_version = (u8)value; break; - - case ODM_CMNINFO_DPK_EN: - p_dm_odm->dpk_en = (u1Byte)value; + case ODM_CMNINFO_FW_SUB_VER: + dm->fw_sub_version = (u8)value; break; - case ODM_CMNINFO_RF_ANTENNA_TYPE: - p_dm_odm->ant_div_type = (u8)value; + case ODM_CMNINFO_RFE_TYPE: +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) + dm->rfe_type_expand = (u8)value; + else +#endif + dm->rfe_type = (u8)value; + phydm_init_hw_info_by_rfe(dm); break; - case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH: - p_dm_odm->with_extenal_ant_switch = (u8)value; + case ODM_CMNINFO_RF_ANTENNA_TYPE: + dm->ant_div_type = (u8)value; break; - case ODM_CMNINFO_BE_FIX_TX_ANT: - p_dm_odm->dm_fat_table.b_fix_tx_ant = (u8)value; + case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH: + dm->with_extenal_ant_switch = (u8)value; break; - case ODM_CMNINFO_BOARD_TYPE: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->board_type = (u8)value; +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + case ODM_CMNINFO_BE_FIX_TX_ANT: + dm->dm_fat_table.b_fix_tx_ant = (u8)value; break; +#endif - case ODM_CMNINFO_PACKAGE_TYPE: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->package_type = (u8)value; + case ODM_CMNINFO_BOARD_TYPE: + if (!dm->is_init_hw_info_by_rfe) + dm->board_type = (u8)value; break; - case ODM_CMNINFO_EXT_LNA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->ext_lna = (u8)value; + case ODM_CMNINFO_PACKAGE_TYPE: + if (!dm->is_init_hw_info_by_rfe) + dm->package_type = (u8)value; break; - case ODM_CMNINFO_5G_EXT_LNA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->ext_lna_5g = (u8)value; + case ODM_CMNINFO_EXT_LNA: + if (!dm->is_init_hw_info_by_rfe) + dm->ext_lna = (u8)value; break; - case ODM_CMNINFO_EXT_PA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->ext_pa = (u8)value; + case ODM_CMNINFO_5G_EXT_LNA: + if (!dm->is_init_hw_info_by_rfe) + dm->ext_lna_5g = (u8)value; break; - case ODM_CMNINFO_5G_EXT_PA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->ext_pa_5g = (u8)value; + case ODM_CMNINFO_EXT_PA: + if (!dm->is_init_hw_info_by_rfe) + dm->ext_pa = (u8)value; break; - case ODM_CMNINFO_GPA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->type_gpa = (u16)value; + case ODM_CMNINFO_5G_EXT_PA: + if (!dm->is_init_hw_info_by_rfe) + dm->ext_pa_5g = (u8)value; break; - case ODM_CMNINFO_APA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->type_apa = (u16)value; + case ODM_CMNINFO_GPA: + if (!dm->is_init_hw_info_by_rfe) + dm->type_gpa = (u16)value; break; - case ODM_CMNINFO_GLNA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->type_glna = (u16)value; + case ODM_CMNINFO_APA: + if (!dm->is_init_hw_info_by_rfe) + dm->type_apa = (u16)value; break; - case ODM_CMNINFO_ALNA: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->type_alna = (u16)value; + case ODM_CMNINFO_GLNA: + if (!dm->is_init_hw_info_by_rfe) + dm->type_glna = (u16)value; break; - case ODM_CMNINFO_EXT_TRSW: - if (!p_dm_odm->is_init_hw_info_by_rfe) - p_dm_odm->ext_trsw = (u8)value; + case ODM_CMNINFO_ALNA: + if (!dm->is_init_hw_info_by_rfe) + dm->type_alna = (u16)value; break; - case ODM_CMNINFO_EXT_LNA_GAIN: - p_dm_odm->ext_lna_gain = (u8)value; - break; - case ODM_CMNINFO_PATCH_ID: - p_dm_odm->patch_id = (u8)value; + + case ODM_CMNINFO_EXT_TRSW: + if (!dm->is_init_hw_info_by_rfe) + dm->ext_trsw = (u8)value; break; - case ODM_CMNINFO_BINHCT_TEST: - p_dm_odm->is_in_hct_test = (boolean)value; + case ODM_CMNINFO_EXT_LNA_GAIN: + dm->ext_lna_gain = (u8)value; break; - case ODM_CMNINFO_BWIFI_TEST: - p_dm_odm->wifi_test = (u8)value; + case ODM_CMNINFO_PATCH_ID: + dm->iot_table.win_patch_id = (u8)value; break; - case ODM_CMNINFO_SMART_CONCURRENT: - p_dm_odm->is_dual_mac_smart_concurrent = (boolean)value; + case ODM_CMNINFO_BINHCT_TEST: + dm->is_in_hct_test = (boolean)value; break; - case ODM_CMNINFO_DOMAIN_CODE_2G: - p_dm_odm->odm_regulation_2_4g = (u8)value; + case ODM_CMNINFO_BWIFI_TEST: + dm->wifi_test = (u8)value; break; - case ODM_CMNINFO_DOMAIN_CODE_5G: - p_dm_odm->odm_regulation_5g = (u8)value; + case ODM_CMNINFO_SMART_CONCURRENT: + dm->is_dual_mac_smart_concurrent = (boolean)value; break; - case ODM_CMNINFO_CONFIG_BB_RF: - p_dm_odm->config_bbrf = (boolean)value; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + case ODM_CMNINFO_CONFIG_BB_RF: + dm->config_bbrf = (boolean)value; break; - case ODM_CMNINFO_IQKFWOFFLOAD: - p_dm_odm->iqk_fw_offload = (u8)value; +#endif + case ODM_CMNINFO_IQKPAOFF: + dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value; break; - case ODM_CMNINFO_IQKPAOFF: - p_dm_odm->rf_calibrate_info.is_iqk_pa_off = (boolean)value; + case ODM_CMNINFO_REGRFKFREEENABLE: + dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value; break; - case ODM_CMNINFO_REGRFKFREEENABLE: - p_dm_odm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value; + case ODM_CMNINFO_RFKFREEENABLE: + dm->rf_calibrate_info.rf_kfree_enable = (u8)value; break; - case ODM_CMNINFO_RFKFREEENABLE: - p_dm_odm->rf_calibrate_info.rf_kfree_enable = (u8)value; + case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE: + dm->normal_rx_path = (u8)value; break; - case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE: - p_dm_odm->normal_rx_path = (u8)value; + case ODM_CMNINFO_EFUSE0X3D8: + dm->efuse0x3d8 = (u8)value; break; - case ODM_CMNINFO_EFUSE0X3D8: - p_dm_odm->efuse0x3d8 = (u8)value; + case ODM_CMNINFO_EFUSE0X3D7: + dm->efuse0x3d7 = (u8)value; break; - case ODM_CMNINFO_EFUSE0X3D7: - p_dm_odm->efuse0x3d7 = (u8)value; + case ODM_CMNINFO_ADVANCE_OTA: + dm->p_advance_ota = (u8)value; break; + #ifdef CONFIG_PHYDM_DFS_MASTER - case ODM_CMNINFO_DFS_REGION_DOMAIN: - p_dm_odm->dfs_region_domain = (u8)value; + case ODM_CMNINFO_DFS_REGION_DOMAIN: + dm->dfs_region_domain = (u8)value; break; #endif - case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING: - p_dm_odm->soft_ap_special_setting = (u32)value; - break; - case ODM_CMNINFO_HALMAC_ABILITY: - p_dm_odm->halmac_ability = (u32)value; - break; - /* To remove the compiler warning, must add an empty default statement to handle the other values. */ - default: - /* do nothing */ - break; - - } - -} - - -void -odm_cmn_info_hook( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, - void *p_value -) -{ - /* */ - /* Hook call by reference pointer. */ - /* */ - switch (cmn_info) { - /* */ - /* Dynamic call by reference pointer. */ - /* */ - case ODM_CMNINFO_MAC_PHY_MODE: - p_dm_odm->p_mac_phy_mode = (u8 *)p_value; - break; - - case ODM_CMNINFO_TX_UNI: - p_dm_odm->p_num_tx_bytes_unicast = (u64 *)p_value; + case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING: + dm->soft_ap_special_setting = (u32)value; break; - case ODM_CMNINFO_RX_UNI: - p_dm_odm->p_num_rx_bytes_unicast = (u64 *)p_value; + case ODM_CMNINFO_X_CAP_SETTING: + dm->dm_cfo_track.crystal_cap_default = (u8)value; break; - case ODM_CMNINFO_WM_MODE: - p_dm_odm->p_wireless_mode = (u8 *)p_value; + case ODM_CMNINFO_DPK_EN: + /*@dm->dpk_en = (u1Byte)value;*/ + halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value); break; - case ODM_CMNINFO_BAND: - p_dm_odm->p_band_type = (u8 *)p_value; + case ODM_CMNINFO_HP_HWID: + dm->hp_hw_id = (boolean)value; break; - - case ODM_CMNINFO_SEC_CHNL_OFFSET: - p_dm_odm->p_sec_ch_offset = (u8 *)p_value; + default: break; + } +} - case ODM_CMNINFO_SEC_MODE: - p_dm_odm->p_security = (u8 *)p_value; +void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, + void *value) +{ + /* @Hook call by reference pointer. */ + switch (cmn_info) { + /* @Dynamic call by reference pointer. */ + case ODM_CMNINFO_TX_UNI: + dm->num_tx_bytes_unicast = (u64 *)value; break; - case ODM_CMNINFO_BW: - p_dm_odm->p_band_width = (u8 *)p_value; + case ODM_CMNINFO_RX_UNI: + dm->num_rx_bytes_unicast = (u64 *)value; break; - case ODM_CMNINFO_CHNL: - p_dm_odm->p_channel = (u8 *)p_value; + case ODM_CMNINFO_BAND: + dm->band_type = (u8 *)value; break; - case ODM_CMNINFO_DMSP_GET_VALUE: - p_dm_odm->p_is_get_value_from_other_mac = (boolean *)p_value; + case ODM_CMNINFO_SEC_CHNL_OFFSET: + dm->sec_ch_offset = (u8 *)value; break; - case ODM_CMNINFO_BUDDY_ADAPTOR: - p_dm_odm->p_buddy_adapter = (struct _ADAPTER **)p_value; + case ODM_CMNINFO_SEC_MODE: + dm->security = (u8 *)value; break; - case ODM_CMNINFO_DMSP_IS_MASTER: - p_dm_odm->p_is_master_of_dmsp = (boolean *)p_value; + case ODM_CMNINFO_BW: + dm->band_width = (u8 *)value; break; - case ODM_CMNINFO_SCAN: - p_dm_odm->p_is_scan_in_process = (boolean *)p_value; + case ODM_CMNINFO_CHNL: + dm->channel = (u8 *)value; break; - case ODM_CMNINFO_POWER_SAVING: - p_dm_odm->p_is_power_saving = (boolean *)p_value; + case ODM_CMNINFO_SCAN: + dm->is_scan_in_process = (boolean *)value; break; - case ODM_CMNINFO_ONE_PATH_CCA: - p_dm_odm->p_one_path_cca = (u8 *)p_value; + case ODM_CMNINFO_POWER_SAVING: + dm->is_power_saving = (boolean *)value; break; - case ODM_CMNINFO_DRV_STOP: - p_dm_odm->p_is_driver_stopped = (boolean *)p_value; + case ODM_CMNINFO_ONE_PATH_CCA: + dm->one_path_cca = (u8 *)value; break; - case ODM_CMNINFO_PNP_IN: - p_dm_odm->p_is_driver_is_going_to_pnp_set_power_sleep = (boolean *)p_value; + case ODM_CMNINFO_DRV_STOP: + dm->is_driver_stopped = (boolean *)value; break; - - case ODM_CMNINFO_INIT_ON: - p_dm_odm->pinit_adpt_in_progress = (boolean *)p_value; + case ODM_CMNINFO_INIT_ON: + dm->pinit_adpt_in_progress = (boolean *)value; break; - case ODM_CMNINFO_ANT_TEST: - p_dm_odm->p_antenna_test = (u8 *)p_value; + case ODM_CMNINFO_ANT_TEST: + dm->antenna_test = (u8 *)value; break; - case ODM_CMNINFO_NET_CLOSED: - p_dm_odm->p_is_net_closed = (boolean *)p_value; + case ODM_CMNINFO_NET_CLOSED: + dm->is_net_closed = (boolean *)value; break; - case ODM_CMNINFO_FORCED_RATE: - p_dm_odm->p_forced_data_rate = (u16 *)p_value; + case ODM_CMNINFO_FORCED_RATE: + dm->forced_data_rate = (u16 *)value; break; - case ODM_CMNINFO_ANT_DIV: - p_dm_odm->p_enable_antdiv = (u8 *)p_value; + case ODM_CMNINFO_ANT_DIV: + dm->enable_antdiv = (u8 *)value; break; - case ODM_CMNINFO_ADAPTIVITY: - p_dm_odm->p_enable_adaptivity = (u8 *)p_value; + case ODM_CMNINFO_ADAPTIVE_SOML: + dm->en_adap_soml = (u8 *)value; break; - case ODM_CMNINFO_FORCED_IGI_LB: - p_dm_odm->pu1_forced_igi_lb = (u8 *)p_value; + case ODM_CMNINFO_ADAPTIVITY: + dm->enable_adaptivity = (u8 *)value; break; - case ODM_CMNINFO_P2P_LINK: - p_dm_odm->dm_dig_table.is_p2p_in_process = (u8 *)p_value; + case ODM_CMNINFO_P2P_LINK: + dm->dm_dig_table.is_p2p_in_process = (u8 *)value; break; - case ODM_CMNINFO_IS1ANTENNA: - p_dm_odm->p_is_1_antenna = (boolean *)p_value; + case ODM_CMNINFO_IS1ANTENNA: + dm->is_1_antenna = (boolean *)value; break; - case ODM_CMNINFO_RFDEFAULTPATH: - p_dm_odm->p_rf_default_path = (u8 *)p_value; + case ODM_CMNINFO_RFDEFAULTPATH: + dm->rf_default_path = (u8 *)value; break; - case ODM_CMNINFO_FCS_MODE: - p_dm_odm->p_is_fcs_mode_enable = (boolean *)p_value; + case ODM_CMNINFO_FCS_MODE: + dm->is_fcs_mode_enable = (boolean *)value; break; - /*add by YuChen for beamforming PhyDM*/ - case ODM_CMNINFO_HUBUSBMODE: - p_dm_odm->hub_usb_mode = (u8 *)p_value; + + case ODM_CMNINFO_HUBUSBMODE: + dm->hub_usb_mode = (u8 *)value; break; - case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS: - p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = (boolean *)p_value; + case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS: + dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value; break; - case ODM_CMNINFO_TX_TP: - p_dm_odm->p_current_tx_tp = (u32 *)p_value; + case ODM_CMNINFO_TX_TP: + dm->current_tx_tp = (u32 *)value; break; - case ODM_CMNINFO_RX_TP: - p_dm_odm->p_current_rx_tp = (u32 *)p_value; + case ODM_CMNINFO_RX_TP: + dm->current_rx_tp = (u32 *)value; break; - case ODM_CMNINFO_SOUNDING_SEQ: - p_dm_odm->p_sounding_seq = (u8 *)p_value; + case ODM_CMNINFO_SOUNDING_SEQ: + dm->sounding_seq = (u8 *)value; break; #ifdef CONFIG_PHYDM_DFS_MASTER - case ODM_CMNINFO_DFS_MASTER_ENABLE: - p_dm_odm->dfs_master_enabled = (u8 *)p_value; + case ODM_CMNINFO_DFS_MASTER_ENABLE: + dm->dfs_master_enabled = (u8 *)value; break; #endif - case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC: - p_dm_odm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)p_value; - break; - case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA: - p_dm_odm->dm_fat_table.p_default_s0_s1 = (u8 *)p_value; + +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC: + dm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)value; break; - case ODM_CMNINFO_SOFT_AP_MODE: - p_dm_odm->p_soft_ap_mode = (u32 *)p_value; + case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA: + dm->dm_fat_table.p_default_s0_s1 = (u8 *)value; break; - default: - /*do nothing*/ + case ODM_CMNINFO_BF_ANTDIV_DECISION: + dm->dm_fat_table.is_no_csi_feedback = (boolean *)value; break; - - } - -} - - -void -odm_cmn_info_ptr_array_hook( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, - u16 index, - void *p_value -) -{ - /*Hook call by reference pointer.*/ - switch (cmn_info) { - /*Dynamic call by reference pointer. */ - case ODM_CMNINFO_STA_STATUS: - p_dm_odm->p_odm_sta_info[index] = (struct sta_info *)p_value; - - if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[index])) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->AssociatedMacId] = index; /*associated_mac_id are unique bttween different adapter*/ -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->aid] = index; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->mac_id] = index; #endif + case ODM_CMNINFO_SOFT_AP_MODE: + dm->soft_ap_mode = (u32 *)value; + break; + case ODM_CMNINFO_MP_MODE: + dm->mp_mode = (u8 *)value; + break; + case ODM_CMNINFO_INTERRUPT_MASK: + dm->interrupt_mask = (u32 *)value; + break; + case ODM_CMNINFO_BB_OPERATION_MODE: + dm->bb_op_mode = (u8 *)value; break; - /* To remove the compiler warning, must add an empty default statement to handle the other values. */ default: - /* do nothing */ + /*do nothing*/ break; } - } - -/* +/*@ * Update band/CHannel/.. The values are dynamic but non-per-packet. - * */ -void -odm_cmn_info_update( - struct PHY_DM_STRUCT *p_dm_odm, - u32 cmn_info, - u64 value -) + */ +void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value) { - /* */ /* This init variable may be changed in run time. */ - /* */ - switch (cmn_info) { + switch (cmn_info) { case ODM_CMNINFO_LINK_IN_PROGRESS: - p_dm_odm->is_link_in_process = (boolean)value; - break; - - case ODM_CMNINFO_ABILITY: - p_dm_odm->support_ability = (u32)value; + dm->is_link_in_process = (boolean)value; break; - case ODM_CMNINFO_RF_TYPE: - p_dm_odm->rf_type = (u8)value; + case ODM_CMNINFO_ABILITY: + dm->support_ability = (u64)value; break; - case ODM_CMNINFO_WIFI_DIRECT: - p_dm_odm->is_wifi_direct = (boolean)value; + case ODM_CMNINFO_RF_TYPE: + dm->rf_type = (u8)value; break; - case ODM_CMNINFO_WIFI_DISPLAY: - p_dm_odm->is_wifi_display = (boolean)value; + case ODM_CMNINFO_WIFI_DIRECT: + dm->is_wifi_direct = (boolean)value; break; - case ODM_CMNINFO_LINK: - p_dm_odm->is_linked = (boolean)value; + case ODM_CMNINFO_WIFI_DISPLAY: + dm->is_wifi_display = (boolean)value; break; - case ODM_CMNINFO_CMW500LINK: - p_dm_odm->bLinkedcmw500 = (boolean)value; + case ODM_CMNINFO_LINK: + dm->is_linked = (boolean)value; break; - case ODM_CMNINFO_LPSPG: - p_dm_odm->is_in_lps_pg = (boolean)value; + case ODM_CMNINFO_CMW500LINK: + dm->iot_table.is_linked_cmw500 = (boolean)value; break; - case ODM_CMNINFO_STATION_STATE: - p_dm_odm->bsta_state = (boolean)value; + case ODM_CMNINFO_STATION_STATE: + dm->bsta_state = (boolean)value; break; - case ODM_CMNINFO_RSSI_MIN: - p_dm_odm->rssi_min = (u8)value; + case ODM_CMNINFO_RSSI_MIN: + dm->rssi_min = (u8)value; break; - case ODM_CMNINFO_DBG_COMP: - p_dm_odm->debug_components = (u32)value; + case ODM_CMNINFO_RSSI_MIN_BY_PATH: + dm->rssi_min_by_path = (u8)value; break; - case ODM_CMNINFO_DBG_LEVEL: - p_dm_odm->debug_level = (u32)value; - break; - case ODM_CMNINFO_RA_THRESHOLD_HIGH: - p_dm_odm->rate_adaptive.high_rssi_thresh = (u8)value; + case ODM_CMNINFO_DBG_COMP: + dm->debug_components = (u64)value; break; - case ODM_CMNINFO_RA_THRESHOLD_LOW: - p_dm_odm->rate_adaptive.low_rssi_thresh = (u8)value; - break; -#if defined(BT_SUPPORT) && (BT_SUPPORT == 1) +#ifdef ODM_CONFIG_BT_COEXIST /* The following is for BT HS mode and BT coexist mechanism. */ case ODM_CMNINFO_BT_ENABLED: - p_dm_odm->is_bt_enabled = (boolean)value; + dm->bt_info_table.is_bt_enabled = (boolean)value; break; case ODM_CMNINFO_BT_HS_CONNECT_PROCESS: - p_dm_odm->is_bt_connect_process = (boolean)value; + dm->bt_info_table.is_bt_connect_process = (boolean)value; break; case ODM_CMNINFO_BT_HS_RSSI: - p_dm_odm->bt_hs_rssi = (u8)value; - break; - - case ODM_CMNINFO_BT_OPERATION: - p_dm_odm->is_bt_hs_operation = (boolean)value; - break; - - case ODM_CMNINFO_BT_LIMITED_DIG: - p_dm_odm->is_bt_limited_dig = (boolean)value; - break; - - case ODM_CMNINFO_BT_DIG: - p_dm_odm->bt_hs_dig_val = (u8)value; - break; - - case ODM_CMNINFO_BT_BUSY: - p_dm_odm->is_bt_busy = (boolean)value; + dm->bt_info_table.bt_hs_rssi = (u8)value; break; - case ODM_CMNINFO_BT_DISABLE_EDCA: - p_dm_odm->is_bt_disable_edca_turbo = (boolean)value; + case ODM_CMNINFO_BT_OPERATION: + dm->bt_info_table.is_bt_hs_operation = (boolean)value; break; -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) /* for repeater mode add by YuChen 2014.06.23 */ -#ifdef UNIVERSAL_REPEATER - case ODM_CMNINFO_VXD_LINK: - p_dm_odm->vxd_linked = (boolean)value; + case ODM_CMNINFO_BT_LIMITED_DIG: + dm->bt_info_table.is_bt_limited_dig = (boolean)value; break; #endif -#endif - - case ODM_CMNINFO_AP_TOTAL_NUM: - p_dm_odm->ap_total_num = (u8)value; - break; - case ODM_CMNINFO_POWER_TRAINING: - p_dm_odm->is_disable_power_training = (boolean)value; + case ODM_CMNINFO_AP_TOTAL_NUM: + dm->ap_total_num = (u8)value; break; #ifdef CONFIG_PHYDM_DFS_MASTER - case ODM_CMNINFO_DFS_REGION_DOMAIN: - p_dm_odm->dfs_region_domain = (u8)value; + case ODM_CMNINFO_DFS_REGION_DOMAIN: + dm->dfs_region_domain = (u8)value; break; #endif -#if 0 - case ODM_CMNINFO_OP_MODE: - p_dm_odm->op_mode = (u8)value; - break; - - case ODM_CMNINFO_WM_MODE: - p_dm_odm->wireless_mode = (u8)value; - break; - - case ODM_CMNINFO_BAND: - p_dm_odm->band_type = (u8)value; - break; - - case ODM_CMNINFO_SEC_CHNL_OFFSET: - p_dm_odm->sec_ch_offset = (u8)value; + case ODM_CMNINFO_BT_CONTINUOUS_TURN: + dm->is_bt_continuous_turn = (boolean)value; break; - - case ODM_CMNINFO_SEC_MODE: - p_dm_odm->security = (u8)value; - break; - - case ODM_CMNINFO_BW: - p_dm_odm->band_width = (u8)value; - break; - - case ODM_CMNINFO_CHNL: - p_dm_odm->channel = (u8)value; - break; -#endif default: - /* do nothing */ break; } - - } -u32 -phydm_cmn_info_query( - struct PHY_DM_STRUCT *p_dm_odm, - enum phydm_info_query_e info_type -) +u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type) { - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct ccx_info *ccx_info = &dm->dm_ccx_info; switch (info_type) { + /*@=== [FA Relative] ===========================================*/ case PHYDM_INFO_FA_OFDM: - return false_alm_cnt->cnt_ofdm_fail; + return fa_t->cnt_ofdm_fail; case PHYDM_INFO_FA_CCK: - return false_alm_cnt->cnt_cck_fail; + return fa_t->cnt_cck_fail; case PHYDM_INFO_FA_TOTAL: - return false_alm_cnt->cnt_all; + return fa_t->cnt_all; case PHYDM_INFO_CCA_OFDM: - return false_alm_cnt->cnt_ofdm_cca; + return fa_t->cnt_ofdm_cca; case PHYDM_INFO_CCA_CCK: - return false_alm_cnt->cnt_cck_cca; + return fa_t->cnt_cck_cca; case PHYDM_INFO_CCA_ALL: - return false_alm_cnt->cnt_cca_all; + return fa_t->cnt_cca_all; case PHYDM_INFO_CRC32_OK_VHT: - return false_alm_cnt->cnt_vht_crc32_ok; + return fa_t->cnt_vht_crc32_ok; case PHYDM_INFO_CRC32_OK_HT: - return false_alm_cnt->cnt_ht_crc32_ok; + return fa_t->cnt_ht_crc32_ok; case PHYDM_INFO_CRC32_OK_LEGACY: - return false_alm_cnt->cnt_ofdm_crc32_ok; + return fa_t->cnt_ofdm_crc32_ok; case PHYDM_INFO_CRC32_OK_CCK: - return false_alm_cnt->cnt_cck_crc32_ok; + return fa_t->cnt_cck_crc32_ok; case PHYDM_INFO_CRC32_ERROR_VHT: - return false_alm_cnt->cnt_vht_crc32_error; + return fa_t->cnt_vht_crc32_error; case PHYDM_INFO_CRC32_ERROR_HT: - return false_alm_cnt->cnt_ht_crc32_error; + return fa_t->cnt_ht_crc32_error; case PHYDM_INFO_CRC32_ERROR_LEGACY: - return false_alm_cnt->cnt_ofdm_crc32_error; + return fa_t->cnt_ofdm_crc32_error; case PHYDM_INFO_CRC32_ERROR_CCK: - return false_alm_cnt->cnt_cck_crc32_error; + return fa_t->cnt_cck_crc32_error; case PHYDM_INFO_EDCCA_FLAG: - return false_alm_cnt->edcca_flag; + return fa_t->edcca_flag; case PHYDM_INFO_OFDM_ENABLE: - return false_alm_cnt->ofdm_block_enable; + return fa_t->ofdm_block_enable; case PHYDM_INFO_CCK_ENABLE: - return false_alm_cnt->cck_block_enable; + return fa_t->cck_block_enable; case PHYDM_INFO_DBG_PORT_0: - return false_alm_cnt->dbg_port0; + return fa_t->dbg_port0; + + case PHYDM_INFO_CRC32_OK_HT_AGG: + return fa_t->cnt_ht_crc32_ok_agg; + + case PHYDM_INFO_CRC32_ERROR_HT_AGG: + return fa_t->cnt_ht_crc32_error_agg; + + /*@=== [DIG] ================================================*/ + case PHYDM_INFO_CURR_IGI: + return dig_t->cur_ig_value; + + /*@=== [RSSI] ===============================================*/ + case PHYDM_INFO_RSSI_MIN: + return (u32)dm->rssi_min; + + case PHYDM_INFO_RSSI_MAX: + return (u32)dm->rssi_max; + + case PHYDM_INFO_CLM_RATIO: + return (u32)ccx_info->clm_ratio; + case PHYDM_INFO_NHM_RATIO: + return (u32)ccx_info->nhm_ratio; default: return 0xffffffff; - } } - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm) +void odm_init_all_work_items(struct dm_struct *dm) { - - struct _ADAPTER *p_adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; #if USE_WORKITEM -#if CONFIG_DYNAMIC_RX_PATH - odm_initialize_work_item(p_dm_odm, - &p_dm_odm->dm_drp_table.phydm_dynamic_rx_path_workitem, - (RT_WORKITEM_CALL_BACK)phydm_dynamic_rx_path_workitem_callback, - (void *)p_adapter, - "DynamicRxPathWorkitem"); +#ifdef CONFIG_ADAPTIVE_SOML + odm_initialize_work_item(dm, + &dm->dm_soml_table.phydm_adaptive_soml_workitem, + (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback, + (void *)adapter, + "AdaptiveSOMLWorkitem"); +#endif +#ifdef ODM_EVM_ENHANCE_ANTDIV + odm_initialize_work_item(dm, + &dm->phydm_evm_antdiv_workitem, + (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback, + (void *)adapter, + "EvmAntdivWorkitem"); #endif + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_initialize_work_item(p_dm_odm, - &p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_workitem, - (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback, - (void *)p_adapter, + odm_initialize_work_item(dm, + &dm->dm_swat_table.phydm_sw_antenna_switch_workitem, + (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback, + (void *)adapter, "AntennaSwitchWorkitem"); #endif -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) - odm_initialize_work_item(p_dm_odm, - &p_dm_odm->dm_sat_table.hl_smart_antenna_workitem, - (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback, - (void *)p_adapter, +#if (defined(CONFIG_HL_SMART_ANTENNA)) + odm_initialize_work_item(dm, + &dm->dm_sat_table.hl_smart_antenna_workitem, + (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback, + (void *)adapter, "hl_smart_ant_workitem"); - odm_initialize_work_item(p_dm_odm, - &p_dm_odm->dm_sat_table.hl_smart_antenna_decision_workitem, - (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback, - (void *)p_adapter, + odm_initialize_work_item(dm, + &dm->dm_sat_table.hl_smart_antenna_decision_workitem, + (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback, + (void *)adapter, "hl_smart_ant_decision_workitem"); #endif odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->path_div_switch_workitem), - (RT_WORKITEM_CALL_BACK)odm_path_div_chk_ant_switch_workitem_callback, - (void *)p_adapter, - "SWAS_WorkItem"); - - odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->cck_path_diversity_workitem), - (RT_WORKITEM_CALL_BACK)odm_cck_tx_path_diversity_work_item_callback, - (void *)p_adapter, - "CCKTXPathDiversityWorkItem"); - - odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->mpt_dig_workitem), - (RT_WORKITEM_CALL_BACK)odm_mpt_dig_work_item_callback, - (void *)p_adapter, - "mpt_dig_workitem"); - - odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->ra_rpt_workitem), - (RT_WORKITEM_CALL_BACK)odm_update_init_rate_work_item_callback, - (void *)p_adapter, + dm, + &dm->ra_rpt_workitem, + (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback, + (void *)adapter, "ra_rpt_workitem"); #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->fast_ant_training_workitem), + dm, + &dm->fast_ant_training_workitem, (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback, - (void *)p_adapter, + (void *)adapter, "fast_ant_training_workitem"); #endif @@ -2095,520 +2555,272 @@ odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm) #if (BEAMFORMING_SUPPORT == 1) odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_enter_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_enter_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_enter_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_leave_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_leave_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_leave_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_fw_ndpa_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_clk_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_clk_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_clk_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_rate_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_rate_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_rate_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_status_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_status_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_status_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_reset_tx_path_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item), + dm, + &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item, (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback, - (void *)p_adapter, + (void *)adapter, "txbf_get_tx_rate_work_item"); #endif odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->adaptivity.phydm_pause_edcca_work_item), + dm, + &dm->adaptivity.phydm_pause_edcca_work_item, (RT_WORKITEM_CALL_BACK)phydm_pause_edcca_work_item_callback, - (void *)p_adapter, + (void *)adapter, "phydm_pause_edcca_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->adaptivity.phydm_resume_edcca_work_item), + dm, + &dm->adaptivity.phydm_resume_edcca_work_item, (RT_WORKITEM_CALL_BACK)phydm_resume_edcca_work_item_callback, - (void *)p_adapter, + (void *)adapter, "phydm_resume_edcca_work_item"); #if (PHYDM_LA_MODE_SUPPORT == 1) odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->adcsmp.adc_smp_work_item), + dm, + &dm->adcsmp.adc_smp_work_item, (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback, - (void *)p_adapter, + (void *)adapter, "adc_smp_work_item"); odm_initialize_work_item( - p_dm_odm, - &(p_dm_odm->adcsmp.adc_smp_work_item_1), + dm, + &dm->adcsmp.adc_smp_work_item_1, (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback, - (void *)p_adapter, + (void *)adapter, "adc_smp_work_item_1"); #endif - } -void -odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm_odm) +void odm_free_all_work_items(struct dm_struct *dm) { #if USE_WORKITEM #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_free_work_item(&(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_workitem)); + odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem); #endif -#if CONFIG_DYNAMIC_RX_PATH - odm_free_work_item(&(p_dm_odm->dm_drp_table.phydm_dynamic_rx_path_workitem)); +#ifdef CONFIG_ADAPTIVE_SOML + odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem); #endif +#ifdef ODM_EVM_ENHANCE_ANTDIV + odm_free_work_item(&dm->phydm_evm_antdiv_workitem); +#endif - -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) - odm_free_work_item(&(p_dm_odm->dm_sat_table.hl_smart_antenna_workitem)); - odm_free_work_item(&(p_dm_odm->dm_sat_table.hl_smart_antenna_decision_workitem)); +#if (defined(CONFIG_HL_SMART_ANTENNA)) + odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem); + odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem); #endif - odm_free_work_item(&(p_dm_odm->path_div_switch_workitem)); - odm_free_work_item(&(p_dm_odm->cck_path_diversity_workitem)); #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - odm_free_work_item(&(p_dm_odm->fast_ant_training_workitem)); + odm_free_work_item(&dm->fast_ant_training_workitem); #endif - odm_free_work_item(&(p_dm_odm->mpt_dig_workitem)); - odm_free_work_item(&(p_dm_odm->ra_rpt_workitem)); - /*odm_free_work_item((&p_dm_odm->sbdcnt_workitem));*/ + odm_free_work_item(&dm->ra_rpt_workitem); +/*odm_free_work_item((&dm->sbdcnt_workitem));*/ #endif #if (BEAMFORMING_SUPPORT == 1) - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_enter_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_leave_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_clk_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_rate_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_status_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item)); - odm_free_work_item((&p_dm_odm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item)); #endif - odm_free_work_item((&p_dm_odm->adaptivity.phydm_pause_edcca_work_item)); - odm_free_work_item((&p_dm_odm->adaptivity.phydm_resume_edcca_work_item)); + odm_free_work_item((&dm->adaptivity.phydm_pause_edcca_work_item)); + odm_free_work_item((&dm->adaptivity.phydm_resume_edcca_work_item)); #if (PHYDM_LA_MODE_SUPPORT == 1) - odm_free_work_item((&p_dm_odm->adcsmp.adc_smp_work_item)); - odm_free_work_item((&p_dm_odm->adcsmp.adc_smp_work_item_1)); + odm_free_work_item((&dm->adcsmp.adc_smp_work_item)); + odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1)); #endif - } #endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ -#if 0 -void -odm_FindMinimumRSSI( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - u32 i; - u8 rssi_min = 0xFF; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - /* if(p_dm_odm->p_odm_sta_info[i] != NULL) */ - if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[i])) { - if (p_dm_odm->p_odm_sta_info[i]->rssi_ave < rssi_min) - rssi_min = p_dm_odm->p_odm_sta_info[i]->rssi_ave; - } - } - - p_dm_odm->rssi_min = rssi_min; - -} - -void -odm_IsLinked( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - u32 i; - boolean Linked = false; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[i])) { - Linked = true; - break; - } - - } - - p_dm_odm->is_linked = Linked; -} -#endif - -void -odm_init_all_timers( - struct PHY_DM_STRUCT *p_dm_odm -) +void odm_init_all_timers(struct dm_struct *dm) { #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - odm_ant_div_timers(p_dm_odm, INIT_ANTDIV_TIMMER); + odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER); #endif - -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path_timers(p_dm_odm, INIT_DRP_TIMMER); +#if (defined(PHYDM_TDMA_DIG_SUPPORT)) +#ifdef IS_USE_NEW_TDMA + phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER); #endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#ifdef MP_TEST - if (p_dm_odm->priv->pshare->rf_ft_var.mp_specific) - odm_initialize_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer, - (void *)odm_mpt_dig_callback, NULL, "mpt_dig_timer"); #endif -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_initialize_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer, - (void *)odm_mpt_dig_callback, NULL, "mpt_dig_timer"); +#ifdef CONFIG_ADAPTIVE_SOML + phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER); +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 + phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER); +#endif #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_initialize_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer, - (void *)odm_path_div_chk_ant_switch_callback, NULL, "PathDivTimer"); - odm_initialize_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer, - (void *)odm_cck_tx_path_diversity_callback, NULL, "cck_path_diversity_timer"); - odm_initialize_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer, + odm_initialize_timer(dm, &dm->sbdcnt_timer, (void *)phydm_sbd_callback, NULL, "SbdTimer"); #if (BEAMFORMING_SUPPORT == 1) - odm_initialize_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer, - (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL, "txbf_fw_ndpa_timer"); + odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer, + (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL, + "txbf_fw_ndpa_timer"); #endif #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - odm_initialize_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer, - (void *)beamforming_sw_timer_callback, NULL, "beamforming_timer"); + odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer, + (void *)beamforming_sw_timer_callback, NULL, + "beamforming_timer"); #endif #endif } -void -odm_cancel_all_timers( - struct PHY_DM_STRUCT *p_dm_odm -) +void odm_cancel_all_timers(struct dm_struct *dm) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* */ - /* 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in */ - /* win7 platform. */ - /* */ - HAL_ADAPTER_STS_CHK(p_dm_odm); -#endif - -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - odm_ant_div_timers(p_dm_odm, CANCEL_ANTDIV_TIMMER); -#endif - -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path_timers(p_dm_odm, CANCEL_DRP_TIMMER); -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#ifdef MP_TEST - if (p_dm_odm->priv->pshare->rf_ft_var.mp_specific) - odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); -#endif -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_cancel_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer); - odm_cancel_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer); - odm_cancel_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); - odm_cancel_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer); -#if (BEAMFORMING_SUPPORT == 1) - odm_cancel_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); -#endif -#endif - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (BEAMFORMING_SUPPORT == 1) - odm_cancel_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer); -#endif + /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/ + if (dm->adapter == NULL) + return; #endif -} - - -void -odm_release_all_timers( - struct PHY_DM_STRUCT *p_dm_odm -) -{ #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - odm_ant_div_timers(p_dm_odm, RELEASE_ANTDIV_TIMMER); + odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER); #endif - -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_dynamic_rx_path_timers(p_dm_odm, RELEASE_DRP_TIMMER); +#ifdef CONFIG_ADAPTIVE_SOML + phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER); #endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#ifdef MP_TEST - if (p_dm_odm->priv->pshare->rf_ft_var.mp_specific) - odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 + phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER); #endif -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - odm_release_timer(p_dm_odm, &p_dm_odm->path_div_switch_timer); - odm_release_timer(p_dm_odm, &p_dm_odm->cck_path_diversity_timer); - odm_release_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer); - odm_release_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer); + odm_cancel_timer(dm, &dm->sbdcnt_timer); #if (BEAMFORMING_SUPPORT == 1) - odm_release_timer(p_dm_odm, &p_dm_odm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); + odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); #endif #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - odm_release_timer(p_dm_odm, &p_dm_odm->beamforming_info.beamforming_timer); -#endif -#endif -} - - -/* 3============================================================ - * 3 Tx Power Tracking - * 3============================================================ */ - - - - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -void -odm_init_all_threads( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#ifdef TPT_THREAD - k_tpt_task_init(p_dm_odm->priv); -#endif -} - -void -odm_stop_all_threads( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#ifdef TPT_THREAD - k_tpt_task_stop(p_dm_odm->priv); -#endif -} -#endif - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -/* - * 2011/07/26 MH Add an API for testing IQK fail case. - * */ -boolean -odm_check_power_status( - struct _ADAPTER *adapter) -{ - - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - RT_RF_POWER_STATE rt_state; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); - - /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */ - if (p_mgnt_info->init_adpt_in_progress == true) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("odm_check_power_status Return true, due to initadapter\n")); - return true; - } - - /* */ - /* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */ - /* */ - adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state)); - if (adapter->bDriverStopped || adapter->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n", - adapter->bDriverStopped, adapter->bDriverIsGoingToPnpSetPowerSleep, rt_state)); - return false; - } - return true; -} -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) -boolean -odm_check_power_status( - struct _ADAPTER *adapter) -{ -#if 0 - /* HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); */ - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - RT_RF_POWER_STATE rt_state; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); - - /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */ - if (p_mgnt_info->init_adpt_in_progress == true) { - ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return true, due to initadapter")); - return true; - } - - /* */ - /* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */ - /* */ - phydm_get_hw_reg_interface(p_dm_odm, HW_VAR_RF_STATE, (u8 *)(&rt_state)); - if (adapter->is_driver_stopped || adapter->is_driver_is_going_to_pnp_set_power_sleep || rt_state == eRfOff) { - ODM_RT_TRACE(p_dm_odm, COMP_INIT, DBG_LOUD, ("odm_check_power_status Return false, due to %d/%d/%d\n", - adapter->is_driver_stopped, adapter->is_driver_is_going_to_pnp_set_power_sleep, rt_state)); - return false; - } + odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer); #endif - return true; -} #endif - -/* need to ODM CE Platform - * move to here for ANT detection mechanism using */ - -u32 -odm_convert_to_db( - u32 value) -{ - u8 i; - u8 j; - u32 dB; - - value = value & 0xFFFF; - - for (i = 0; i < 12; i++) { - if (value <= db_invert_table[i][7]) - break; - } - - if (i >= 12) { - return 96; /* maximum 96 dB */ - } - - for (j = 0; j < 8; j++) { - if (value <= db_invert_table[i][j]) - break; - } - - dB = (i << 3) + j + 1; - - return dB; -} - -u32 -odm_convert_to_linear( - u32 value) -{ - u8 i; - u8 j; - u32 linear; - - /* 1dB~96dB */ - - value = value & 0xFF; - - i = (u8)((value - 1) >> 3); - j = (u8)(value - 1) - (i << 3); - - linear = db_invert_table[i][j]; - - return linear; } -/* - * ODM multi-port consideration, added by Roger, 2013.10.01. - * */ -void -odm_asoc_entry_init( - struct PHY_DM_STRUCT *p_dm_odm -) +void odm_release_all_timers(struct dm_struct *dm) { +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER); +#endif +#ifdef CONFIG_ADAPTIVE_SOML + phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER); +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 + phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER); +#endif +#endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(p_dm_odm->adapter); - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_loop_adapter); - struct PHY_DM_STRUCT *p_dm_out_src = &p_hal_data->DM_OutSrc; - u8 total_assoc_entry_num = 0; - u8 index = 0; - u8 adaptercount = 0; - - odm_cmn_info_ptr_array_hook(p_dm_out_src, ODM_CMNINFO_STA_STATUS, 0, &p_loop_adapter->MgntInfo.DefaultPort[0]); - p_loop_adapter->MgntInfo.DefaultPort[0].MultiPortStationIdx = total_assoc_entry_num; - - adaptercount += 1; - RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount)); - p_loop_adapter = GetNextExtAdapter(p_loop_adapter); - total_assoc_entry_num += 1; - - while (p_loop_adapter) { - for (index = 0; index < ASSOCIATE_ENTRY_NUM; index++) { - odm_cmn_info_ptr_array_hook(p_dm_out_src, ODM_CMNINFO_STA_STATUS, total_assoc_entry_num + index, &p_loop_adapter->MgntInfo.AsocEntry[index]); - p_loop_adapter->MgntInfo.AsocEntry[index].MultiPortStationIdx = total_assoc_entry_num + index; - } + odm_release_timer(dm, &dm->sbdcnt_timer); +#if (BEAMFORMING_SUPPORT == 1) + odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); +#endif +#endif - total_assoc_entry_num += index; - if (IS_HARDWARE_TYPE_8188E((p_dm_odm->adapter))) - p_loop_adapter->RASupport = true; - adaptercount += 1; - RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount)); - p_loop_adapter = GetNextExtAdapter(p_loop_adapter); - } +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (BEAMFORMING_SUPPORT == 1) + odm_release_timer(dm, &dm->beamforming_info.beamforming_timer); +#endif +#endif +} - RT_TRACE(COMP_INIT, DBG_LOUD, ("total_assoc_entry_num = %d\n", total_assoc_entry_num)); - if (total_assoc_entry_num < (ODM_ASSOCIATE_ENTRY_NUM - 1)) { +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +void odm_init_all_threads( + struct dm_struct *dm) +{ +#ifdef TPT_THREAD + k_tpt_task_init(dm->priv); +#endif +} - RT_TRACE(COMP_INIT, DBG_LOUD, ("In hook null\n")); - for (index = total_assoc_entry_num; index < ODM_ASSOCIATE_ENTRY_NUM; index++) - odm_cmn_info_ptr_array_hook(p_dm_out_src, ODM_CMNINFO_STA_STATUS, index, NULL); - } +void odm_stop_all_threads( + struct dm_struct *dm) +{ +#ifdef TPT_THREAD + k_tpt_task_stop(dm->priv); #endif } +#endif #if (DM_ODM_SUPPORT_TYPE == ODM_CE) -/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */ -void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm) +/* @Justin: According to the current RRSI to adjust Response Frame TX power, + * 2012/11/05 + */ +void odm_dtc(struct dm_struct *dm) { #ifdef CONFIG_DM_RESP_TXAGC -#define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */ -#define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */ +/* RSSI higher than this value, start to decade TX power */ +#define DTC_BASE 35 + +/* RSSI lower than this value, start to increase TX power */ +#define DTC_DWN_BASE (DTC_BASE - 5) /* RSSI vs TX power step mapping: decade TX power */ static const u8 dtc_table_down[] = { @@ -2617,8 +2829,7 @@ void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm) (DTC_BASE + 10), (DTC_BASE + 15), (DTC_BASE + 20), - (DTC_BASE + 25) - }; + (DTC_BASE + 25)}; /* RSSI vs TX power step mapping: increase TX power */ static const u8 dtc_table_up[] = { @@ -2632,8 +2843,7 @@ void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm) (DTC_DWN_BASE - 25), (DTC_DWN_BASE - 25), (DTC_DWN_BASE - 30), - (DTC_DWN_BASE - 35) - }; + (DTC_DWN_BASE - 35)}; u8 i; u8 dtc_steps = 0; @@ -2641,28 +2851,28 @@ void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm) u8 resp_txagc = 0; #if 0 - /* As DIG is disabled, DTC is also disable */ - if (!(p_dm_odm->support_ability & ODM_XXXXXX)) + /* @As DIG is disabled, DTC is also disable */ + if (!(dm->support_ability & ODM_XXXXXX)) return; #endif - if (DTC_BASE < p_dm_odm->rssi_min) { + if (dm->rssi_min > DTC_BASE) { /* need to decade the CTS TX power */ sign = 1; for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) { - if ((dtc_table_down[i] >= p_dm_odm->rssi_min) || (dtc_steps >= 6)) + if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6) break; else dtc_steps++; } } #if 0 - else if (DTC_DWN_BASE > p_dm_odm->rssi_min) { + else if (dm->rssi_min > DTC_DWN_BASE) { /* needs to increase the CTS TX power */ sign = 0; dtc_steps = 1; for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) { - if ((dtc_table_up[i] <= p_dm_odm->rssi_min) || (dtc_steps >= 10)) + if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10) break; else dtc_steps++; @@ -2676,839 +2886,283 @@ void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm) resp_txagc = dtc_steps | (sign << 4); resp_txagc = resp_txagc | (resp_txagc << 5); - odm_write_1byte(p_dm_odm, 0x06d9, resp_txagc); + odm_write_1byte(dm, 0x06d9, resp_txagc); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PWR_TRAIN, ODM_DBG_LOUD, ("%s rssi_min:%u, set RESP_TXAGC to %s %u\n", - __func__, p_dm_odm->rssi_min, sign ? "minus" : "plus", dtc_steps)); -#endif /* CONFIG_RESP_TXAGC_ADJUST */ + PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN, + "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__, + dm->rssi_min, sign ? "minus" : "plus", dtc_steps); +#endif /* @CONFIG_RESP_TXAGC_ADJUST */ } -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ +#endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ -void -odm_update_power_training_state( - struct PHY_DM_STRUCT *p_dm_odm -) +/*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/ +void phydm_dc_cancellation(struct dm_struct *dm) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u32 score = 0; - - if (!(p_dm_odm->support_ability & ODM_BB_PWR_TRAIN)) - return; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state()============>\n")); - p_dm_odm->is_change_state = false; - - /* Debug command */ - if (p_dm_odm->force_power_training_state) { - if (p_dm_odm->force_power_training_state == 1 && !p_dm_odm->is_disable_power_training) { - p_dm_odm->is_change_state = true; - p_dm_odm->is_disable_power_training = true; - } else if (p_dm_odm->force_power_training_state == 2 && p_dm_odm->is_disable_power_training) { - p_dm_odm->is_change_state = true; - p_dm_odm->is_disable_power_training = false; - } - - p_dm_odm->PT_score = 0; - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): force_power_training_state = %d\n", - p_dm_odm->force_power_training_state)); +#ifdef PHYDM_DC_CANCELLATION + u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0}; + u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0}; + u32 reg_value32[PHYDM_MAX_RF_PATH] = {0}; + u8 path = RF_PATH_A; + u8 set_result; + + if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT)) return; - } - - if (!p_dm_odm->is_linked) + if ((dm->support_ic_type & ODM_RTL8188F) && + dm->cut_version < ODM_CUT_D) return; - - /* First connect */ - if ((p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == false)) { - p_dm_odm->PT_score = 0; - p_dm_odm->is_change_state = true; - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): First Connect\n")); + if ((dm->support_ic_type & ODM_RTL8192F) && + dm->cut_version == ODM_CUT_A) return; - } - - /* Compute score */ - if (p_dm_odm->nhm_cnt_0 >= 215) - score = 2; - else if (p_dm_odm->nhm_cnt_0 >= 190) - score = 1; /* unknow state */ - else { - u32 rx_pkt_cnt; - - rx_pkt_cnt = (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm) + (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck); - - if ((false_alm_cnt->cnt_cca_all > 31 && rx_pkt_cnt > 31) && (false_alm_cnt->cnt_cca_all >= rx_pkt_cnt)) { - if ((rx_pkt_cnt + (rx_pkt_cnt >> 1)) <= false_alm_cnt->cnt_cca_all) - score = 0; - else if ((rx_pkt_cnt + (rx_pkt_cnt >> 2)) <= false_alm_cnt->cnt_cca_all) - score = 1; - else - score = 2; - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): rx_pkt_cnt = %d, cnt_cca_all = %d\n", - rx_pkt_cnt, false_alm_cnt->cnt_cca_all)); - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n", - (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm), (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck))); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): nhm_cnt_0 = %d, score = %d\n", - p_dm_odm->nhm_cnt_0, score)); - - /* smoothing */ - p_dm_odm->PT_score = (score << 4) + (p_dm_odm->PT_score >> 1) + (p_dm_odm->PT_score >> 2); - score = (p_dm_odm->PT_score + 32) >> 6; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): PT_score = %d, score after smoothing = %d\n", - p_dm_odm->PT_score, score)); - - /* mode decision */ - if (score == 2) { - if (p_dm_odm->is_disable_power_training) { - p_dm_odm->is_change_state = true; - p_dm_odm->is_disable_power_training = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n")); - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Enable Power Training\n")); - } else if (score == 0) { - if (!p_dm_odm->is_disable_power_training) { - p_dm_odm->is_change_state = true; - p_dm_odm->is_disable_power_training = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n")); - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Disable Power Training\n")); - } - - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; -#endif -} - - - -/*===========================================================*/ -/* The following is for compile only*/ -/*===========================================================*/ -/*#define TARGET_CHNL_NUM_2G_5G 59*/ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -u8 get_right_chnl_place_for_iqk(u8 chnl) -{ - u8 channel_all[TARGET_CHNL_NUM_2G_5G] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, - 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165 - }; - u8 place = chnl; - - if (chnl > 14) { - for (place = 14; place < sizeof(channel_all); place++) { - if (channel_all[place] == chnl) - return place - 13; - } - } - - return 0; -} - -#endif -/*===========================================================*/ - -void -phydm_noisy_detection( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - u32 total_fa_cnt, total_cca_cnt; - u32 score = 0, i, score_smooth; + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__); - total_cca_cnt = p_dm_odm->false_alm_cnt.cnt_cca_all; - total_fa_cnt = p_dm_odm->false_alm_cnt.cnt_all; + /*@DC_Estimation (only for 2x2 ic now) */ -#if 0 - if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* 87.5 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* 75 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* 56.25 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* 50 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* 43.75 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* 37.5 */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* 31.25% */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* 25% */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* 18.75% */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* 12.5% */ - ; - else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* 6.25% */ - ; -#endif - for (i = 0; i <= 16; i++) { - if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) { - score = 16 - i; + for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) { + if (path > RF_PATH_A && + dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F | + ODM_RTL8710B)) break; + else if (path > RF_PATH_B && + dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F)) + break; + if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) { + PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n"); + return; } - } - - /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */ - p_dm_odm->noisy_decision_smooth = (p_dm_odm->noisy_decision_smooth >> 1) + (score << 2); - - /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */ - score_smooth = (total_cca_cnt >= 300) ? ((p_dm_odm->noisy_decision_smooth + 3) >> 3) : 0; - - p_dm_odm->noisy_decision = (score_smooth >= 3) ? 1 : 0; -#if 0 - switch (score_smooth) { - case 0: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=0%%\n")); - break; - case 1: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=6.25%%\n")); - break; - case 2: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=12.5%%\n")); - break; - case 3: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=18.75%%\n")); - break; - case 4: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=25%%\n")); - break; - case 5: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=31.25%%\n")); - break; - case 6: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=37.5%%\n")); - break; - case 7: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=43.75%%\n")); - break; - case 8: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=50%%\n")); - break; - case 9: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=56.25%%\n")); - break; - case 10: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=62.5%%\n")); - break; - case 11: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=68.75%%\n")); - break; - case 12: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=75%%\n")); - break; - case 13: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=81.25%%\n")); - break; - case 14: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=87.5%%\n")); - break; - case 15: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=93.75%%\n")); - break; - case 16: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] total_fa_cnt/total_cca_cnt=100%%\n")); - break; - default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, - ("[NoisyDetection] Unknown value!! Need Check!!\n")); - } -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, - ("[NoisyDetection] total_cca_cnt=%d, total_fa_cnt=%d, noisy_decision_smooth=%d, score=%d, score_smooth=%d, p_dm_odm->noisy_decision=%d\n", - total_cca_cnt, total_fa_cnt, p_dm_odm->noisy_decision_smooth, score, score_smooth, p_dm_odm->noisy_decision)); - -} - -void -phydm_set_ext_switch( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 used = *_used; - u32 out_len = *_out_len; - u32 ext_ant_switch = dm_value[0]; - - if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { - - /*Output Pin Settings*/ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /*select DPDT_P and DPDT_N as output pin*/ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /*by WLAN control*/ - - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/ - - if (ext_ant_switch == MAIN_ANT) { - odm_set_bb_reg(p_dm_odm, 0xCB4, (BIT(29) | BIT(28)), 1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("***8821A set ant switch = 2b'01 (Main)\n")); - } else if (ext_ant_switch == AUX_ANT) { - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29) | BIT(28), 2); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("***8821A set ant switch = 2b'10 (Aux)\n")); - } - } -} - -void -phydm_csi_mask_enable( - void *p_dm_void, - u32 enable -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 reg_value = 0; - - reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0xD2C, BIT(28), reg_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", reg_value)); - - } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0x874, BIT(0), reg_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", reg_value)); - } - -} - -void -phydm_clean_all_csi_mask( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0xD40, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0xD44, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0xD48, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0xD4c, MASKDWORD, 0); - - } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0x880, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x884, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x888, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x88c, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x890, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x894, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x898, MASKDWORD, 0); - odm_set_bb_reg(p_dm_odm, 0x89c, MASKDWORD, 0); - } -} - -void -phydm_set_csi_mask_reg( - void *p_dm_void, - u32 tone_idx_tmp, - u8 tone_direction -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 byte_offset, bit_offset; - u32 target_reg; - u8 reg_tmp_value; - u32 tone_num = 64; - u32 tone_num_shift = 0; - u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0; - - /* calculate real tone idx*/ - if ((tone_idx_tmp % 10) >= 5) - tone_idx_tmp += 10; - - tone_idx_tmp = (tone_idx_tmp / 10); - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - - tone_num = 64; - csi_mask_reg_p = 0xD40; - csi_mask_reg_n = 0xD48; - - } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - tone_num = 128; - csi_mask_reg_p = 0x880; - csi_mask_reg_n = 0x890; - } - - if (tone_direction == FREQ_POSITIVE) { - - if (tone_idx_tmp >= (tone_num - 1)) - tone_idx_tmp = (tone_num - 1); - - byte_offset = (u8)(tone_idx_tmp >> 3); - bit_offset = (u8)(tone_idx_tmp & 0x7); - target_reg = csi_mask_reg_p + byte_offset; - - } else { - tone_num_shift = tone_num; - - if (tone_idx_tmp >= tone_num) - tone_idx_tmp = tone_num; - - tone_idx_tmp = tone_num - tone_idx_tmp; - - byte_offset = (u8)(tone_idx_tmp >> 3); - bit_offset = (u8)(tone_idx_tmp & 0x7); - target_reg = csi_mask_reg_n + byte_offset; - } - - reg_tmp_value = odm_read_1byte(p_dm_odm, target_reg); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); - reg_tmp_value |= BIT(bit_offset); - odm_write_1byte(p_dm_odm, target_reg, reg_tmp_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); -} - -void -phydm_set_nbi_reg( - void *p_dm_void, - u32 tone_idx_tmp, - u32 bw -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245, /*1~10*/ /*tone_idx X 10*/ - 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/ - 485, 505, 525, 555, 585, 615, 635 - }; /*21~27*/ - - u32 nbi_table_256[NBI_TABLE_SIZE_256] = { 25, 55, 85, 115, 135, 155, 175, 195, 225, 245, /*1~10*/ - 265, 285, 305, 325, 345, 365, 385, 405, 425, 445, /*11~20*/ - 465, 485, 505, 525, 545, 565, 585, 605, 625, 645, /*21~30*/ - 665, 695, 715, 735, 755, 775, 795, 815, 835, 855, /*31~40*/ - 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055, /*41~50*/ - 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275 - }; /*51~59*/ - - u32 reg_idx = 0; - u32 i; - u8 nbi_table_idx = FFT_128_TYPE; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - - nbi_table_idx = FFT_128_TYPE; - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_1_SERIES) - - nbi_table_idx = FFT_256_TYPE; - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_2_SERIES) { - - if (bw == 80) - nbi_table_idx = FFT_256_TYPE; - else /*20M, 40M*/ - nbi_table_idx = FFT_128_TYPE; - } - - if (nbi_table_idx == FFT_128_TYPE) { - - for (i = 0; i < NBI_TABLE_SIZE_128; i++) { - if (tone_idx_tmp < nbi_table_128[i]) { - reg_idx = i + 1; - break; + odm_write_dig(dm, 0x7e); + /*@Disable LNA*/ + if (dm->support_ic_type & ODM_RTL8821C) + halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE); + /*Turn off 3-wire*/ + phydm_stop_3_wire(dm, PHYDM_SET); + if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) { + /*set debug port to 0x235*/ + if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x235)) { + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; } - } - - } else if (nbi_table_idx == FFT_256_TYPE) { - - for (i = 0; i < NBI_TABLE_SIZE_256; i++) { - if (tone_idx_tmp < nbi_table_256[i]) { - reg_idx = i + 1; - break; + } else if (dm->support_ic_type & ODM_RTL8821C) { + if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) { + /*set debug port to 0x200*/ + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; } - } - } - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - odm_set_bb_reg(p_dm_odm, 0xc40, 0x1f000000, reg_idx); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", reg_idx)); - /**/ - } else { - odm_set_bb_reg(p_dm_odm, 0x87c, 0xfc000, reg_idx); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx)); - /**/ - } -} - - -void -phydm_nbi_enable( - void *p_dm_void, - u32 enable -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 reg_value = 0; - - reg_value = (enable == NBI_ENABLE) ? 1 : 0; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0xc40, BIT(9), reg_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value)); - - } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0x87c, BIT(13), reg_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value)); - } -} - -u8 -phydm_calculate_fc( - void *p_dm_void, - u32 channel, - u32 bw, - u32 second_ch, - u32 *fc_in -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 fc = *fc_in; - u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173}; - u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165}; - u32 *p_start_ch = &(start_ch_per_40m[0]); - u32 num_start_channel = NUM_START_CH_40M; - u32 channel_offset = 0; - u32 i; - - /*2.4G*/ - if (channel <= 14 && channel > 0) { - - if (bw == 80) - return SET_ERROR; - - fc = 2412 + (channel - 1) * 5; - - if (bw == 40 && (second_ch == PHYDM_ABOVE)) { - - if (channel >= 10) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch)); - return SET_ERROR; + phydm_bb_dbg_port_header_sel(dm, 0x0); + } else if (dm->support_ic_type & ODM_RTL8822B) { + if (path == RF_PATH_A && + !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) { + /*set debug port to 0x200*/ + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; } - fc += 10; - } else if (bw == 40 && (second_ch == PHYDM_BELOW)) { - - if (channel <= 2) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch)); - return SET_ERROR; + if (path == RF_PATH_B && + !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x202)) { + /*set debug port to 0x200*/ + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; } - fc -= 10; - } - } - /*5G*/ - else if (channel >= 36 && channel <= 177) { - - if (bw != 20) { - - if (bw == 40) { - num_start_channel = NUM_START_CH_40M; - p_start_ch = &(start_ch_per_40m[0]); - channel_offset = CH_OFFSET_40M; - } else if (bw == 80) { - num_start_channel = NUM_START_CH_80M; - p_start_ch = &(start_ch_per_80m[0]); - channel_offset = CH_OFFSET_80M; + phydm_bb_dbg_port_header_sel(dm, 0x0); + } else if (dm->support_ic_type & ODM_RTL8192F) { + if (path == RF_PATH_A && + !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x235)) { + /*set debug port to 0x235*/ + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; } - - for (i = 0; i < num_start_channel; i++) { - - if (channel < p_start_ch[i + 1]) { - channel = p_start_ch[i] + channel_offset; - break; - } + if (path == RF_PATH_B && + !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x23d)) { + /*set debug port to 0x23d*/ + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Mod_CH = ((%d))\n", channel)); } - fc = 5180 + (channel - 36) * 5; - - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)) Error setting\n", channel)); - return SET_ERROR; - } - - *fc_in = fc; - - return SET_SUCCESS; -} - - -u8 -phydm_calculate_intf_distance( - void *p_dm_void, - u32 bw, - u32 fc, - u32 f_interference, - u32 *p_tone_idx_tmp_in -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 bw_up, bw_low; - u32 int_distance; - u32 tone_idx_tmp; - u8 set_result = SET_NO_NEED; - - bw_up = fc + bw / 2; - bw_low = fc - bw / 2; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference)); - - if ((f_interference >= bw_low) && (f_interference <= bw_up)) { - - int_distance = (fc >= f_interference) ? (fc - f_interference) : (f_interference - fc); - tone_idx_tmp = (int_distance << 5); /* =10*(int_distance /0.3125) */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp / 10), (tone_idx_tmp % 10))); - *p_tone_idx_tmp_in = tone_idx_tmp; - set_result = SET_SUCCESS; - } - - return set_result; - -} - - -u8 -phydm_csi_mask_setting( - void *p_dm_void, - u32 enable, - u32 channel, - u32 bw, - u32 f_interference, - u32 second_ch -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 fc; - u32 int_distance; - u8 tone_direction; - u32 tone_idx_tmp; - u8 set_result = SET_SUCCESS; - - if (enable == CSI_MASK_DISABLE) { - set_result = SET_SUCCESS; - phydm_clean_all_csi_mask(p_dm_odm); - - } else { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L"))); - - /*calculate fc*/ - if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR) - set_result = SET_ERROR; - - else { - /*calculate interference distance*/ - if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { - - tone_direction = (f_interference >= fc) ? FREQ_POSITIVE : FREQ_NEGATIVE; - phydm_set_csi_mask_reg(p_dm_odm, tone_idx_tmp, tone_direction); - set_result = SET_SUCCESS; - } else - set_result = SET_NO_NEED; + /*@disable CCK DCNF*/ + odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0); + + PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n"); + + phydm_stop_ck320(dm, true); /*stop ck320*/ + + /* the same debug port both for path-a and path-b*/ + reg_value32[path] = phydm_get_bb_dbg_port_val(dm); + + phydm_stop_ck320(dm, false); /*start ck320*/ + + phydm_release_bb_dbg_port(dm); + /*Turn on 3-wire*/ + phydm_stop_3_wire(dm, PHYDM_REVERT); + /*@Enable LNA*/ + if (dm->support_ic_type & ODM_RTL8821C) + halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE); + + odm_write_dig(dm, 0x20); + + set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT); + + PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n"); + } + + /*@DC_Cancellation*/ + /*@DC compensation to CCK data path*/ + odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1); + if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) { + offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18; + offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8; + + /*@Before filling into registers, + *offset should be multiplexed (-1) + */ + offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ? + (0x400 - offset_i_hex[0]) : + (0x1ff - offset_i_hex[0]); + offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ? + (0x400 - offset_q_hex[0]) : + (0x1ff - offset_q_hex[0]); + + odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]); + odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]); + } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) { + /* Path-a */ + offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10; + offset_q_hex[0] = reg_value32[0] & 0x3ff; + + /*@Before filling into registers, + *offset should be multiplexed (-1) + */ + offset_i_hex[0] = 0x400 - offset_i_hex[0]; + offset_q_hex[0] = 0x400 - offset_q_hex[0]; + + odm_set_bb_reg(dm, R_0xc10, 0x3c000000, + (0x3c0 & offset_i_hex[0]) >> 6); + odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]); + odm_set_bb_reg(dm, R_0xc14, 0x3c000000, + (0x3c0 & offset_q_hex[0]) >> 6); + odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]); + + /* Path-b */ + if (dm->rf_type > RF_1T1R) { + offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10; + offset_q_hex[1] = reg_value32[1] & 0x3ff; + + /*@Before filling into registers, + *offset should be multiplexed (-1) + */ + offset_i_hex[1] = 0x400 - offset_i_hex[1]; + offset_q_hex[1] = 0x400 - offset_q_hex[1]; + + odm_set_bb_reg(dm, R_0xe10, 0x3c000000, + (0x3c0 & offset_i_hex[1]) >> 6); + odm_set_bb_reg(dm, R_0xe10, 0xfc00, + 0x3f & offset_i_hex[1]); + odm_set_bb_reg(dm, R_0xe14, 0x3c000000, + (0x3c0 & offset_q_hex[1]) >> 6); + odm_set_bb_reg(dm, R_0xe14, 0xfc00, + 0x3f & offset_q_hex[1]); } - } - - if (set_result == SET_SUCCESS) - phydm_csi_mask_enable(p_dm_odm, enable); - else - phydm_csi_mask_enable(p_dm_odm, CSI_MASK_DISABLE); - - return set_result; -} - -u8 -phydm_nbi_setting( - void *p_dm_void, - u32 enable, - u32 channel, - u32 bw, - u32 f_interference, - u32 second_ch -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 fc; - u32 int_distance; - u32 tone_idx_tmp; - u8 set_result = SET_SUCCESS; - u32 bw_max = 40; - - if (enable == NBI_DISABLE) - set_result = SET_SUCCESS; - - else { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L"))); - - /*calculate fc*/ - if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR) - set_result = SET_ERROR; - - else { - /*calculate interference distance*/ - if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { - - phydm_set_nbi_reg(p_dm_odm, tone_idx_tmp, bw); - set_result = SET_SUCCESS; - } else - set_result = SET_NO_NEED; + } else if (dm->support_ic_type & (ODM_RTL8192F)) { + /* Path-a I:df4[27:18],Q:df4[17:8]*/ + offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18; + offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8; + + /*@Before filling into registers, + *offset should be multiplexed (-1) + */ + offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ? + (0x400 - offset_i_hex[0]) : + (0xff - offset_i_hex[0]); + offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ? + (0x400 - offset_q_hex[0]) : + (0xff - offset_q_hex[0]); + /*Path-a I:c10[7:0],Q:c10[15:8]*/ + odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]); + odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]); + + /* Path-b */ + if (dm->rf_type > RF_1T1R) { + /* @I:df4[27:18],Q:df4[17:8]*/ + offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18; + offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8; + + /*@Before filling into registers, + *offset should be multiplexed (-1) + */ + offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ? + (0x400 - offset_i_hex[1]) : + (0xff - offset_i_hex[1]); + offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ? + (0x400 - offset_q_hex[1]) : + (0xff - offset_q_hex[1]); + /*Path-b I:c18[7:0],Q:c18[15:8]*/ + odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]); + odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]); } } - - if (set_result == SET_SUCCESS) - phydm_nbi_enable(p_dm_odm, enable); - else - phydm_nbi_enable(p_dm_odm, NBI_DISABLE); - - return set_result; -} - -void -phydm_api_debug( - void *p_dm_void, - u32 function_map, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 used = *_used; - u32 out_len = *_out_len; - u32 channel = dm_value[1]; - u32 bw = dm_value[2]; - u32 f_interference = dm_value[3]; - u32 second_ch = dm_value[4]; - u8 set_result = 0; - - /*PHYDM_API_NBI*/ - /*-------------------------------------------------------------------------------------------------------------------------------*/ - if (function_map == PHYDM_API_NBI) { - - if (dm_value[0] == 100) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); - return; - - } else if (dm_value[0] == NBI_ENABLE) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, ((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((second_ch == PHYDM_ABOVE) ? "H" : "L"))); - set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, bw, f_interference, second_ch); - - } else if (dm_value[0] == NBI_DISABLE) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[Disable NBI]\n")); - set_result = phydm_nbi_setting(p_dm_odm, NBI_DISABLE, channel, bw, f_interference, second_ch); - - } else - - set_result = SET_ERROR; - PHYDM_SNPRINTF((output + used, out_len - used, "[NBI set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); - - } - - /*PHYDM_CSI_MASK*/ - /*-------------------------------------------------------------------------------------------------------------------------------*/ - else if (function_map == PHYDM_API_CSI_MASK) { - - if (dm_value[0] == 100) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); - return; - - } else if (dm_value[0] == CSI_MASK_ENABLE) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", - channel, bw, f_interference, (channel > 14) ? "Don't care" : (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L"))); - set_result = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, channel, bw, f_interference, second_ch); - - } else if (dm_value[0] == CSI_MASK_DISABLE) { - - PHYDM_SNPRINTF((output + used, out_len - used, "[Disable CSI MASK]\n")); - set_result = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_DISABLE, channel, bw, f_interference, second_ch); - - } else - - set_result = SET_ERROR; - PHYDM_SNPRINTF((output + used, out_len - used, "[CSI MASK set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); - } +#endif } -void -phydm_receiver_blocking( - void *p_dm_void -) +void phydm_receiver_blocking(void *dm_void) { #ifdef CONFIG_RECEIVER_BLOCKING - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 channel = *p_dm_odm->p_channel; - u8 bw = *p_dm_odm->p_band_width; - u8 set_result = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 chnl = *dm->channel; + u8 bw = *dm->band_width; + u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000); - if (!(p_dm_odm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT)) + if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) || + !(dm->support_ability & ODM_BB_ADAPTIVITY)) return; - - if (p_dm_odm->consecutive_idlel_time > 10 && p_dm_odm->mp_mode == false && p_dm_odm->adaptivity_enable == true) { - if ((bw == ODM_BW20M) && (channel == 1)) { - set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2410, PHYDM_DONT_CARE); - p_dm_odm->is_receiver_blocking_en = true; - } else if ((bw == ODM_BW20M) && (channel == 13)) { - set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE); - p_dm_odm->is_receiver_blocking_en = true; - } else if ((bw == ODM_BW20M) && (channel == 100)) { - set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 5495, PHYDM_DONT_CARE); - p_dm_odm->is_receiver_blocking_en = true; - } else if (*(p_dm_odm->p_is_scan_in_process) == false) { - if (p_dm_odm->is_receiver_blocking_en && channel != 1 && channel != 13 && channel != 100) { - phydm_nbi_enable(p_dm_odm, NBI_DISABLE); - odm_set_bb_reg(p_dm_odm, 0xc40, 0x1f000000, 0x1f); - p_dm_odm->is_receiver_blocking_en = false; - } + + if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) || + dm->support_ic_type & ODM_RTL8192E) { + /*@8188E_T version*/ + if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode) + goto end; + + if (bw == CHANNEL_WIDTH_20 && chnl == 1) { + phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410, + PHYDM_DONT_CARE); + dm->is_rx_blocking_en = true; + } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) { + phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473, + PHYDM_DONT_CARE); + dm->is_rx_blocking_en = true; + } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) { + phydm_nbi_enable(dm, FUNC_DISABLE); + odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f); + dm->is_rx_blocking_en = false; } - } else { - if (p_dm_odm->is_receiver_blocking_en) { - phydm_nbi_enable(p_dm_odm, NBI_DISABLE); - odm_set_bb_reg(p_dm_odm, 0xc40, 0x1f000000, 0x1f); - p_dm_odm->is_receiver_blocking_en = false; + return; + } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) { + /*@8188E_S version*/ + if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode) + goto end; + + if (bw == CHANNEL_WIDTH_20 && chnl == 13) { + phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473, + PHYDM_DONT_CARE); + dm->is_rx_blocking_en = true; + } else if (dm->is_rx_blocking_en && chnl != 13) { + phydm_nbi_enable(dm, FUNC_DISABLE); + odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f); + dm->is_rx_blocking_en = false; } + return; + } + +end: + if (dm->is_rx_blocking_en) { + phydm_nbi_enable(dm, FUNC_DISABLE); + odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f); + dm->is_rx_blocking_en = false; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, - ("[NBI set result: %s]\n", (set_result == SET_SUCCESS ? "Success" : (set_result == SET_NO_NEED ? "No need" : "Error")))); #endif } diff --git a/hal/phydm/phydm.h b/hal/phydm/phydm.h index 134da26..ecd30dd 100644 --- a/hal/phydm/phydm.h +++ b/hal/phydm/phydm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,301 +8,347 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ - + * Larry Finger + * + *****************************************************************************/ -#ifndef __HALDMOUTSRC_H__ +#ifndef __HALDMOUTSRC_H__ #define __HALDMOUTSRC_H__ -/*============================================================*/ -/*include files*/ -/*============================================================*/ +/*@============================================================*/ +/*@include files*/ +/*@============================================================*/ +/*PHYDM header*/ #include "phydm_pre_define.h" +#include "phydm_features.h" #include "phydm_dig.h" -#if PHYDM_SUPPORT_EDCA -#include "phydm_edcaturbocheck.h" -#endif #include "phydm_pathdiv.h" +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY #include "phydm_antdiv.h" +#endif + +#include "phydm_soml.h" + +#ifdef CONFIG_SMART_ANTENNA +#include "phydm_smt_ant.h" +#endif +#ifdef CONFIG_ANT_DETECTION #include "phydm_antdect.h" -#include "phydm_dynamicbbpowersaving.h" +#endif #include "phydm_rainfo.h" +#ifdef CONFIG_DYNAMIC_TX_TWR #include "phydm_dynamictxpower.h" +#endif #include "phydm_cfotracking.h" -#include "phydm_acs.h" #include "phydm_adaptivity.h" -#include "phydm_iqk.h" #include "phydm_dfs.h" #include "phydm_ccx.h" #include "txbf/phydm_hal_txbf_api.h" - +#if (PHYDM_LA_MODE_SUPPORT == 1) #include "phydm_adc_sampling.h" -#include "phydm_dynamic_rx_path.h" +#endif +#ifdef CONFIG_PSD_TOOL #include "phydm_psd.h" - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) +#endif +#ifdef PHYDM_PRIMARY_CCA +#include "phydm_primary_cca.h" +#endif +#include "phydm_cck_pd.h" +#include "phydm_rssi_monitor.h" +#ifdef PHYDM_AUTO_DEGBUG +#include "phydm_auto_dbg.h" +#endif +#include "phydm_math_lib.h" +#include "phydm_noisemonitor.h" +#include "phydm_api.h" +#ifdef PHYDM_POWER_TRAINING_SUPPORT +#include "phydm_pow_train.h" +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +#include "phydm_lna_sat.h" +#endif +#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT +#include "phydm_pmac_tx_setting.h" +#endif +#ifdef PHYDM_MP_SUPPORT +#include "phydm_mp.h" +#endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #include "phydm_beamforming.h" #endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #include "halphyrf_ap.h" -#endif +#include "phydm_regtable.h" -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - #include "phydm_noisemonitor.h" - #include "halphyrf_ce.h" +/*@HALRF header*/ +#include "halrf/halrf_iqk.h" +#include "halrf/halrf_dpk.h" +#include "halrf/halrf.h" +#include "halrf/halrf_powertracking.h" +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #include "halrf/halphyrf_ap.h" +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) + #include "halrf/halphyrf_ce.h" +#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + #include "halrf/halphyrf_win.h" +#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) + #include "halrf/halphyrf_iot.h" #endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - #include "halphyrf_win.h" - #include "phydm_noisemonitor.h" -#endif +extern const u16 phy_rate_table[28]; -/*============================================================*/ -/*Definition */ -/*============================================================*/ +/*@============================================================*/ +/*@Definition */ +/*@============================================================*/ /* Traffic load decision */ -#define TRAFFIC_ULTRA_LOW 1 +#define TRAFFIC_NO_TP 0 +#define TRAFFIC_ULTRA_LOW 1 #define TRAFFIC_LOW 2 #define TRAFFIC_MID 3 #define TRAFFIC_HIGH 4 -#define NONE 0 - -/*NBI API------------------------------------*/ -#define NBI_ENABLE 1 -#define NBI_DISABLE 2 - -#define NBI_TABLE_SIZE_128 27 -#define NBI_TABLE_SIZE_256 59 - -#define NUM_START_CH_80M 7 -#define NUM_START_CH_40M 14 - -#define CH_OFFSET_40M 2 -#define CH_OFFSET_80M 6 - -/*CSI MASK API------------------------------------*/ -#define CSI_MASK_ENABLE 1 -#define CSI_MASK_DISABLE 2 - -/*------------------------------------------------*/ - -#define FFT_128_TYPE 1 -#define FFT_256_TYPE 2 - -#define SET_SUCCESS 1 -#define SET_ERROR 2 -#define SET_NO_NEED 3 - -#define FREQ_POSITIVE 1 -#define FREQ_NEGATIVE 2 - -#define MAX_2(_x_, _y_) (((_x_)>(_y_))? (_x_) : (_y_)) -#define MIN_2(_x_, _y_) (((_x_)<(_y_))? (_x_) : (_y_)) - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #define PHYDM_WATCH_DOG_PERIOD 1 +#define NONE 0 + +#if defined(DM_ODM_CE_MAC80211) +#define MAX_2(x, y) \ + __max2(typeof(x), typeof(y), \ + x, y) +#define __max2(t1, t2, x, y) ({ \ + t1 m80211_max1 = (x); \ + t2 m80211_max2 = (y); \ + m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; }) + +#define MIN_2(x, y) \ + __min2(typeof(x), typeof(y), \ + x, y) +#define __min2(t1, t2, x, y) ({ \ + t1 m80211_min1 = (x); \ + t2 m80211_min2 = (y); \ + m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; }) + +#define DIFF_2(x, y) \ + __diff2(typeof(x), typeof(y), \ + x, y) +#define __diff2(t1, t2, x, y) ({ \ + t1 __d1 = (x); \ + t2 __d2 = (y); \ + (__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); }) #else - #define PHYDM_WATCH_DOG_PERIOD 2 +#define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_)) +#define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_)) +#define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_)) #endif -/*============================================================*/ -/*structure and define*/ -/*============================================================*/ - -/*2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.*/ -/*We need to remove to other position???*/ +#define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false) +#define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false) -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) -struct rtl8192cd_priv { - u8 temp; - - }; +#if defined(DM_ODM_CE_MAC80211) +#define BYTE_DUPLICATE_2_DWORD(B0) ({ \ + u32 __b_dup = (B0);\ + (((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\ + }) +#else +#define BYTE_DUPLICATE_2_DWORD(B0) \ + (((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0)) #endif +#define BYTE_2_DWORD(B3, B2, B1, B0) \ + (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0)) +#define BIT_2_BYTE(B3, B2, B1, B0) \ + (((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0)) + +/*@For cmn sta info*/ +#if defined(DM_ODM_CE_MAC80211) +#define is_sta_active(sta) ({ \ + struct cmn_sta_info *__sta = (sta); \ + ((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE)); \ + }) + +#define IS_FUNC_EN(name) ({ \ + u8 *__is_func_name = (name); \ + (__is_func_name) && (*__is_func_name); \ + }) +#else +#define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE)) - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -struct _ADAPTER { - u8 temp; -#ifdef AP_BUILD_WORKAROUND - HAL_DATA_TYPE *temp2; - struct rtl8192cd_priv *priv; -#endif -}; +#define IS_FUNC_EN(name) ((name) && (*name)) #endif #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - -struct _WLAN_STA { - u8 temp; -}; - -#endif - -struct _dynamic_primary_cca { - u8 pri_cca_flag; - u8 intf_flag; - u8 intf_type; - u8 dup_rts_flag; - u8 monitor_flag; - u8 CH_offset; - u8 MF_state; -}; - - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - #ifdef ADSL_AP_BUILD_WORKAROUND - #define MAX_TOLERANCE 5 - #define IQK_DELAY_TIME 1 /*ms*/ - #endif -#endif /*#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))*/ - -#define dm_type_by_fw 0 -#define dm_type_by_driver 1 - -/*Declare for common info*/ - -#define IQK_THRESHOLD 8 -#define DPK_THRESHOLD 4 - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -__PACK struct _odm_phy_status_info_ { - u8 rx_pwdb_all; - u8 signal_quality; /* in 0-100 index. */ - u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ - u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */ - s8 rx_mimo_signal_quality[4]; /* EVM */ - s8 rx_snr[4]; /* per-path's SNR */ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u8 rx_count:2; /* RX path counter---*/ - u8 band_width:2; - u8 rxsc:4; /* sub-channel---*/ + #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/ #else - u8 band_width; -#endif -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u8 channel; /* channel number---*/ - boolean is_mu_packet; /* is MU packet or not---*/ - boolean is_beamformed; /* BF packet---*/ + #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/ #endif -}; - -struct _odm_phy_status_info_append_ { - u8 MAC_CRC32; -}; +#define PHY_HIST_SIZE 12 -#else +/*@============================================================*/ +/*structure and define*/ +/*@============================================================*/ + +#define dm_type_by_fw 0 +#define dm_type_by_driver 1 + +#ifdef BB_RAM_SUPPORT + +struct phydm_bb_ram_per_sta { + /* @Reg0x1E84 for RAM I/O*/ + boolean hw_igi_en; + boolean tx_pwr_offset0_en; + boolean tx_pwr_offset1_en; + /* @ macid from 0 to 63, above 63 => mapping to 63*/ + u8 macid_addr; + /* @hw_igi value for paths after packet Tx in a period of time*/ + u8 hw_igi; + /* @tx_pwr_offset0 offset for Tx power index*/ + s8 tx_pwr_offset0; + s8 tx_pwr_offset1; -struct _odm_phy_status_info_ { - /* */ - /* Be care, if you want to add any element please insert between */ - /* rx_pwdb_all & signal_strength. */ - /* */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - u32 rx_pwdb_all; /*in new Phy-status IC, represent the max PWDB among all path*/ -#else - u8 rx_pwdb_all; -#endif - u8 signal_quality; /* in 0-100 index. */ - s8 rx_mimo_signal_quality[4]; /* per-path's EVM translate to 0~100% */ - u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */ - u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ - s16 cfo_short[4]; /* per-path's cfo_short */ - s16 cfo_tail[4]; /* per-path's cfo_tail */ - s8 rx_power; /* in dBm Translate from PWdB */ - s8 recv_signal_power; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ - u8 bt_rx_rssi_percentage; - u8 signal_strength; /* in 0-100 index. */ - s8 rx_pwr[4]; /* per-path's pwdb */ - s8 rx_snr[4]; /* per-path's SNR */ - /* s8 BB_Backup[13]; backup reg. */ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u8 rx_count:2; /* RX path counter---*/ - u8 band_width:2; - u8 rxsc:4; /* sub-channel---*/ -#else - u8 band_width; -#endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - u8 bt_coex_pwr_adjust; -#endif -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u8 channel; /* channel number---*/ - boolean is_mu_packet; /* is MU packet or not---*/ - boolean is_beamformed; /* BF packet---*/ -#endif }; -#endif -struct _odm_per_pkt_info_ { - u8 data_rate; - u8 station_id; - boolean is_packet_match_bssid; - boolean is_packet_to_self; - boolean is_packet_beacon; - boolean is_to_self; - u8 ppdu_cnt; +struct phydm_bb_ram_ctrl { + /*@ For 98F/14B/22C/12F, each TxAGC step will be 0.25dB*/ + struct phydm_bb_ram_per_sta pram_sta_ctrl[ODM_ASSOCIATE_ENTRY_NUM]; + /*------------ For table2 do not set power offset by macid --------*/ + /* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */ + boolean tx_pwr_offset_reg0_en; + u8 tx_pwr_offset_reg0; + /* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */ + boolean tx_pwr_offset_reg1_en; + u8 tx_pwr_offset_reg1; }; - -struct _odm_phy_dbg_info_ { - /*ODM Write,debug info*/ - s8 rx_snr_db[4]; - u32 num_qry_phy_status; - u32 num_qry_phy_status_cck; - u32 num_qry_phy_status_ofdm; -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - u32 num_qry_mu_pkt; - u32 num_qry_bf_pkt; - u32 num_qry_mu_vht_pkt[40]; - u32 num_qry_vht_pkt[40]; - boolean is_ldpc_pkt; - boolean is_stbc_pkt; - u8 num_of_ppdu[4]; - u8 gid_num[4]; #endif - u8 num_qry_beacon_pkt; - /* Others */ - s32 rx_evm[4]; +struct phydm_phystatus_statistic { + /*@[CCK]*/ + u32 rssi_cck_sum; + u32 rssi_cck_cnt; + /*@[OFDM]*/ + u32 rssi_ofdm_sum; + u32 rssi_ofdm_cnt; + u32 evm_ofdm_sum; + u32 snr_ofdm_sum; + u16 evm_ofdm_hist[PHY_HIST_SIZE]; + u16 snr_ofdm_hist[PHY_HIST_SIZE]; + /*@[1SS]*/ + u32 rssi_1ss_cnt; + u32 rssi_1ss_sum; + u32 evm_1ss_sum; + u32 snr_1ss_sum; + u16 evm_1ss_hist[PHY_HIST_SIZE]; + u16 snr_1ss_hist[PHY_HIST_SIZE]; + /*@[2SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + u32 rssi_2ss_cnt; + u32 rssi_2ss_sum[2]; + u32 evm_2ss_sum[2]; + u32 snr_2ss_sum[2]; + u16 evm_2ss_hist[2][PHY_HIST_SIZE]; + u16 snr_2ss_hist[2][PHY_HIST_SIZE]; + #endif + /*@[3SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + u32 rssi_3ss_cnt; + u32 rssi_3ss_sum[3]; + u32 evm_3ss_sum[3]; + u32 snr_3ss_sum[3]; + u16 evm_3ss_hist[3][PHY_HIST_SIZE]; + u16 snr_3ss_hist[3][PHY_HIST_SIZE]; + #endif + /*@[4SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + u32 rssi_4ss_cnt; + u32 rssi_4ss_sum[4]; + u32 evm_4ss_sum[4]; + u32 snr_4ss_sum[4]; + u16 evm_4ss_hist[4][PHY_HIST_SIZE]; + u16 snr_4ss_hist[4][PHY_HIST_SIZE]; + #endif }; - -/*2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info*/ -/*Please declare below ODM relative info in your STA info structure.*/ - -#if 1 -struct _ODM_STA_INFO { - /*Driver Write*/ - boolean is_used; /*record the sta status link or not?*/ - u8 iot_peer; /*Enum value. HT_IOT_PEER_E*/ - - /*ODM Write*/ - /*PHY_STATUS_INFO*/ - u8 rssi_path[4]; - u8 rssi_ave; - u8 RXEVM[4]; - u8 RXSNR[4]; - +struct phydm_phystatus_avg { + /*@[CCK]*/ + u8 rssi_cck_avg; + /*@[OFDM]*/ + u8 rssi_ofdm_avg; + u8 evm_ofdm_avg; + u8 snr_ofdm_avg; + /*@[1SS]*/ + u8 rssi_1ss_avg; + u8 evm_1ss_avg; + u8 snr_1ss_avg; + /*@[2SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + u8 rssi_2ss_avg[2]; + u8 evm_2ss_avg[2]; + u8 snr_2ss_avg[2]; + #endif + /*@[3SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + u8 rssi_3ss_avg[3]; + u8 evm_3ss_avg[3]; + u8 snr_3ss_avg[3]; + #endif + /*@[4SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + u8 rssi_4ss_avg[4]; + u8 evm_4ss_avg[4]; + u8 snr_4ss_avg[4]; + #endif }; + +struct odm_phy_dbg_info { + /*@ODM Write,debug info*/ + u32 num_qry_phy_status_cck; + u32 num_qry_phy_status_ofdm; +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) + u32 num_qry_mu_pkt; + u32 num_qry_bf_pkt; + u16 num_mu_vht_pkt[VHT_RATE_NUM]; + boolean is_ldpc_pkt; + boolean is_stbc_pkt; + u8 num_of_ppdu[4]; + u8 gid_num[4]; #endif + u32 condi_num; /*@condition number U(18,4)*/ + u8 condi_num_cdf[CN_CNT_MAX]; + u8 num_qry_beacon_pkt; + u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/ + u8 beacon_phy_rate; + u8 show_phy_sts_all_pkt; /*@Show phy status witch not match BSSID*/ + u16 show_phy_sts_max_cnt; /*@show number of phy-status row data per PHYDM watchdog*/ + u16 show_phy_sts_cnt; + u16 num_qry_legacy_pkt[LEGACY_RATE_NUM]; + u16 num_qry_ht_pkt[HT_RATE_NUM]; + u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/ + boolean ht_pkt_not_zero; + boolean low_bw_20_occur; + #if ODM_IC_11AC_SERIES_SUPPORT + u16 num_qry_vht_pkt[VHT_RATE_NUM]; + u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/ + boolean vht_pkt_not_zero; + boolean low_bw_40_occur; + #endif + u16 snr_hist_th[PHY_HIST_SIZE - 1]; + u16 evm_hist_th[PHY_HIST_SIZE - 1]; + struct phydm_phystatus_statistic physts_statistic_info; + struct phydm_phystatus_avg phystatus_statistic_avg; +}; -enum odm_cmninfo_e { - /*Fixed value*/ - /*-----------HOOK BEFORE REG INIT-----------*/ +enum odm_cmninfo { + /*@Fixed value*/ + /*@-----------HOOK BEFORE REG INIT-----------*/ ODM_CMNINFO_PLATFORM = 0, ODM_CMNINFO_ABILITY, ODM_CMNINFO_INTERFACE, @@ -310,6 +356,8 @@ enum odm_cmninfo_e { ODM_CMNINFO_IC_TYPE, ODM_CMNINFO_CUT_VER, ODM_CMNINFO_FAB_VER, + ODM_CMNINFO_FW_VER, + ODM_CMNINFO_FW_SUB_VER, ODM_CMNINFO_RF_TYPE, ODM_CMNINFO_RFE_TYPE, ODM_CMNINFO_DPK_EN, @@ -330,9 +378,6 @@ enum odm_cmninfo_e { ODM_CMNINFO_BWIFI_TEST, ODM_CMNINFO_SMART_CONCURRENT, ODM_CMNINFO_CONFIG_BB_RF, - ODM_CMNINFO_DOMAIN_CODE_2G, - ODM_CMNINFO_DOMAIN_CODE_5G, - ODM_CMNINFO_IQKFWOFFLOAD, ODM_CMNINFO_IQKPAOFF, ODM_CMNINFO_HUBUSBMODE, ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, @@ -345,16 +390,16 @@ enum odm_cmninfo_e { ODM_CMNINFO_EFUSE0X3D8, ODM_CMNINFO_EFUSE0X3D7, ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, - ODM_CMNINFO_HALMAC_ABILITY, - /*-----------HOOK BEFORE REG INIT-----------*/ + ODM_CMNINFO_X_CAP_SETTING, + ODM_CMNINFO_ADVANCE_OTA, + ODM_CMNINFO_HP_HWID, + /*@-----------HOOK BEFORE REG INIT-----------*/ - /*Dynamic value:*/ + /*@Dynamic value:*/ - /*--------- POINTER REFERENCE-----------*/ - ODM_CMNINFO_MAC_PHY_MODE, + /*@--------- POINTER REFERENCE-----------*/ ODM_CMNINFO_TX_UNI, ODM_CMNINFO_RX_UNI, - ODM_CMNINFO_WM_MODE, ODM_CMNINFO_BAND, ODM_CMNINFO_SEC_CHNL_OFFSET, ODM_CMNINFO_SEC_MODE, @@ -362,10 +407,8 @@ enum odm_cmninfo_e { ODM_CMNINFO_CHNL, ODM_CMNINFO_FORCED_RATE, ODM_CMNINFO_ANT_DIV, + ODM_CMNINFO_ADAPTIVE_SOML, ODM_CMNINFO_ADAPTIVITY, - ODM_CMNINFO_DMSP_GET_VALUE, - ODM_CMNINFO_BUDDY_ADAPTOR, - ODM_CMNINFO_DMSP_IS_MASTER, ODM_CMNINFO_SCAN, ODM_CMNINFO_POWER_SAVING, ODM_CMNINFO_ONE_PATH_CCA, @@ -374,7 +417,6 @@ enum odm_cmninfo_e { ODM_CMNINFO_INIT_ON, ODM_CMNINFO_ANT_TEST, ODM_CMNINFO_NET_CLOSED, - ODM_CMNINFO_FORCED_IGI_LB, ODM_CMNINFO_P2P_LINK, ODM_CMNINFO_FCS_MODE, ODM_CMNINFO_IS1ANTENNA, @@ -383,21 +425,24 @@ enum odm_cmninfo_e { ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, ODM_CMNINFO_SOFT_AP_MODE, - /*--------- POINTER REFERENCE-----------*/ + ODM_CMNINFO_MP_MODE, + ODM_CMNINFO_INTERRUPT_MASK, + ODM_CMNINFO_BB_OPERATION_MODE, + ODM_CMNINFO_BF_ANTDIV_DECISION, + /*@--------- POINTER REFERENCE-----------*/ - /*------------CALL BY VALUE-------------*/ + /*@------------CALL BY VALUE-------------*/ ODM_CMNINFO_WIFI_DIRECT, ODM_CMNINFO_WIFI_DISPLAY, ODM_CMNINFO_LINK_IN_PROGRESS, ODM_CMNINFO_LINK, ODM_CMNINFO_CMW500LINK, - ODM_CMNINFO_LPSPG, ODM_CMNINFO_STATION_STATE, ODM_CMNINFO_RSSI_MIN, + ODM_CMNINFO_RSSI_MIN_BY_PATH, ODM_CMNINFO_DBG_COMP, - ODM_CMNINFO_DBG_LEVEL, - ODM_CMNINFO_RA_THRESHOLD_HIGH, - ODM_CMNINFO_RA_THRESHOLD_LOW, + ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/ + ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/ ODM_CMNINFO_RF_ANTENNA_TYPE, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, ODM_CMNINFO_BE_FIX_TX_ANT, @@ -406,27 +451,38 @@ enum odm_cmninfo_e { ODM_CMNINFO_BT_HS_RSSI, ODM_CMNINFO_BT_OPERATION, ODM_CMNINFO_BT_LIMITED_DIG, - ODM_CMNINFO_BT_DIG, - ODM_CMNINFO_BT_BUSY, - ODM_CMNINFO_BT_DISABLE_EDCA, -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) /*for repeater mode add by YuChen 2014.06.23*/ -#ifdef UNIVERSAL_REPEATER - ODM_CMNINFO_VXD_LINK, -#endif -#endif ODM_CMNINFO_AP_TOTAL_NUM, ODM_CMNINFO_POWER_TRAINING, ODM_CMNINFO_DFS_REGION_DOMAIN, - /*------------CALL BY VALUE-------------*/ + ODM_CMNINFO_BT_CONTINUOUS_TURN, + /*@------------CALL BY VALUE-------------*/ - /*Dynamic ptr array hook itms.*/ + /*@Dynamic ptr array hook itms.*/ ODM_CMNINFO_STA_STATUS, ODM_CMNINFO_MAX, }; +enum phydm_rfe_bb_source_sel { + PAPE_2G = 0, + PAPE_5G = 1, + LNA0N_2G = 2, + LNAON_5G = 3, + TRSW = 4, + TRSW_B = 5, + GNT_BT = 6, + ZERO = 7, + ANTSEL_0 = 8, + ANTSEL_1 = 9, + ANTSEL_2 = 0xa, + ANTSEL_3 = 0xb, + ANTSEL_4 = 0xc, + ANTSEL_5 = 0xd, + ANTSEL_6 = 0xe, + ANTSEL_7 = 0xf +}; -enum phydm_info_query_e { +enum phydm_info_query { PHYDM_INFO_FA_OFDM, PHYDM_INFO_FA_CCK, PHYDM_INFO_FA_TOTAL, @@ -444,288 +500,352 @@ enum phydm_info_query_e { PHYDM_INFO_EDCCA_FLAG, PHYDM_INFO_OFDM_ENABLE, PHYDM_INFO_CCK_ENABLE, - PHYDM_INFO_DBG_PORT_0 + PHYDM_INFO_CRC32_OK_HT_AGG, + PHYDM_INFO_CRC32_ERROR_HT_AGG, + PHYDM_INFO_DBG_PORT_0, + PHYDM_INFO_CURR_IGI, + PHYDM_INFO_RSSI_MIN, + PHYDM_INFO_RSSI_MAX, + PHYDM_INFO_CLM_RATIO, + PHYDM_INFO_NHM_RATIO, }; -enum phydm_api_e { - - PHYDM_API_NBI = 1, - PHYDM_API_CSI_MASK, - +enum phydm_api { + PHYDM_API_NBI = 1, + PHYDM_API_CSI_MASK = 2, }; +enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/ + + F00_DIG = 0, + F01_RA_MASK = 1, + F02_DYN_TXPWR = 2, + F03_FA_CNT = 3, + F04_RSSI_MNTR = 4, + F05_CCK_PD = 5, + F06_ANT_DIV = 6, + F07_SMT_ANT = 7, + F08_PWR_TRAIN = 8, + F09_RA = 9, + F10_PATH_DIV = 10, + F11_DFS = 11, + F12_DYN_ARFR = 12, + F13_ADPTVTY = 13, + F14_CFO_TRK = 14, + F15_ENV_MNTR = 15, + F16_PRI_CCA = 16, + F17_ADPTV_SOML = 17, + F18_LNA_SAT_CHK = 18, +}; -/*2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY*/ -enum odm_ability_e { - - /*BB ODM section BIT 0-19*/ - ODM_BB_DIG = BIT(0), - ODM_BB_RA_MASK = BIT(1), - ODM_BB_DYNAMIC_TXPWR = BIT(2), - ODM_BB_FA_CNT = BIT(3), - ODM_BB_RSSI_MONITOR = BIT(4), - ODM_BB_CCK_PD = BIT(5), - ODM_BB_ANT_DIV = BIT(6), - ODM_BB_PWR_TRAIN = BIT(8), - ODM_BB_RATE_ADAPTIVE = BIT(9), - ODM_BB_PATH_DIV = BIT(10), - ODM_BB_ADAPTIVITY = BIT(13), - ODM_BB_CFO_TRACKING = BIT(14), - ODM_BB_NHM_CNT = BIT(15), - ODM_BB_PRIMARY_CCA = BIT(16), - ODM_BB_TXBF = BIT(17), - ODM_BB_DYNAMIC_ARFR = BIT(18), - - ODM_MAC_EDCA_TURBO = BIT(20), - ODM_BB_DYNAMIC_RX_PATH = BIT(21), - - /*RF ODM section BIT 24-31*/ - ODM_RF_TX_PWR_TRACK = BIT(24), - ODM_RF_RX_GAIN_TRACK = BIT(25), - ODM_RF_CALIBRATION = BIT(26), - +/*@=[PHYDM supportability]==========================================*/ +enum odm_ability { + ODM_BB_DIG = BIT(F00_DIG), + ODM_BB_RA_MASK = BIT(F01_RA_MASK), + ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR), + ODM_BB_FA_CNT = BIT(F03_FA_CNT), + ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR), + ODM_BB_CCK_PD = BIT(F05_CCK_PD), + ODM_BB_ANT_DIV = BIT(F06_ANT_DIV), + ODM_BB_SMT_ANT = BIT(F07_SMT_ANT), + ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN), + ODM_BB_RATE_ADAPTIVE = BIT(F09_RA), + ODM_BB_PATH_DIV = BIT(F10_PATH_DIV), + ODM_BB_DFS = BIT(F11_DFS), + ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR), + ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY), + ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK), + ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR), + ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA), + ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML), + ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), }; -enum odm_halmac_ability { - ODM_PHY_PARAM_OFFLOAD = BIT(0) +/*@=[PHYDM Debug Component]=====================================*/ +enum phydm_dbg_comp { + /*@BB Driver Functions*/ + DBG_DIG = BIT(F00_DIG), + DBG_RA_MASK = BIT(F01_RA_MASK), + DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR), + DBG_FA_CNT = BIT(F03_FA_CNT), + DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR), + DBG_CCKPD = BIT(F05_CCK_PD), + DBG_ANT_DIV = BIT(F06_ANT_DIV), + DBG_SMT_ANT = BIT(F07_SMT_ANT), + DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN), + DBG_RA = BIT(F09_RA), + DBG_PATH_DIV = BIT(F10_PATH_DIV), + DBG_DFS = BIT(F11_DFS), + DBG_DYN_ARFR = BIT(F12_DYN_ARFR), + DBG_ADPTVTY = BIT(F13_ADPTVTY), + DBG_CFO_TRK = BIT(F14_CFO_TRK), + DBG_ENV_MNTR = BIT(F15_ENV_MNTR), + DBG_PRI_CCA = BIT(F16_PRI_CCA), + DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML), + DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), + /*BIT(19)*/ + /*Neet to re-arrange*/ + DBG_PHY_STATUS = BIT(20), + DBG_TMP = BIT(21), + DBG_FW_TRACE = BIT(22), + DBG_TXBF = BIT(23), + DBG_COMMON_FLOW = BIT(24), + DBG_COMP_MCC = BIT(25), + /*BIT(26)*/ + DBG_DM_SUMMARY = BIT(27), + ODM_PHY_CONFIG = BIT(28), + ODM_COMP_INIT = BIT(29), + DBG_CMN = BIT(30),/*@common*/ + ODM_COMP_API = BIT(31) }; -/*ODM_CMNINFO_ONE_PATH_CCA*/ -enum odm_cca_path_e { +/*@=========================================================*/ + +/*@ODM_CMNINFO_ONE_PATH_CCA*/ +enum odm_cca_path { ODM_CCA_2R = 0, ODM_CCA_1R_A = 1, ODM_CCA_1R_B = 2, }; -enum cca_pathdiv_en_e { - CCA_PATHDIV_DISABLE = 0, - CCA_PATHDIV_ENABLE = 1, +enum phy_reg_pg_type { + PHY_REG_PG_RELATIVE_VALUE = 0, + PHY_REG_PG_EXACT_VALUE = 1 +}; +enum phydm_offload_ability { + PHYDM_PHY_PARAM_OFFLOAD = BIT(0), + PHYDM_RF_IQK_OFFLOAD = BIT(1), }; +struct phydm_pause_lv { + s8 lv_dig; + s8 lv_cckpd; + s8 lv_antdiv; + s8 lv_adapt; + s8 lv_adsl; +}; -enum phy_reg_pg_type { - PHY_REG_PG_RELATIVE_VALUE = 0, - PHY_REG_PG_EXACT_VALUE = 1 +struct phydm_func_poiner { + void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len); }; -/*2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.*/ +struct pkt_process_info { + u8 phystatus_smp_mode_en; /*@send phystatus every sampling time*/ + u8 pre_ppdu_cnt; + u8 lna_idx; + u8 vga_idx; +}; + +#ifdef ODM_CONFIG_BT_COEXIST +struct phydm_bt_info { + boolean is_bt_enabled; /*@BT is enabled*/ + boolean is_bt_connect_process; /*@BT HS is under connection progress.*/ + u8 bt_hs_rssi; /*@BT HS mode wifi rssi value.*/ + boolean is_bt_hs_operation; /*@BT HS mode is under progress*/ + boolean is_bt_limited_dig; /*@BT is busy.*/ +}; +#endif + +struct phydm_iot_center { + boolean is_linked_cmw500; + u8 win_patch_id; /*@Customer ID*/ + u32 phydm_patch_id; + +}; + +#if (RTL8822B_SUPPORT == 1) +struct drp_rtl8822b_struct { + enum bb_path path_judge; + u16 path_a_cck_fa; + u16 path_b_cck_fa; +}; +#endif + +#ifdef CONFIG_MCC_DM +#define MCC_DM_REG_NUM 32 +struct _phydm_mcc_dm_ { + u8 mcc_status; + u8 mcc_pre_status; + u8 mcc_reg_id[MCC_DM_REG_NUM]; + u16 mcc_dm_reg[MCC_DM_REG_NUM]; + u8 mcc_dm_val[MCC_DM_REG_NUM][2]; + /*mcc DIG*/ + u8 mcc_rssi[2]; + /*u8 mcc_igi[2];*/ + u8 port[2][NUM_STA]; + +}; +#endif + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) #if (RT_PLATFORM != PLATFORM_LINUX) typedef #endif - struct PHY_DM_STRUCT -#else/*for AP,ADSL,CE Team*/ - struct PHY_DM_STRUCT +struct dm_struct { +#else/*for AP, CE Team*/ +struct dm_struct { #endif -{ - /*Add for different team use temporarily*/ - struct _ADAPTER *adapter; /*For CE/NIC team*/ - struct rtl8192cd_priv *priv; /*For AP/ADSL team*/ - /*WHen you use adapter or priv pointer, you must make sure the pointer is ready.*/ + /*@Add for different team use temporarily*/ + void *adapter; /*@For CE/NIC team*/ + struct rtl8192cd_priv *priv; /*@For AP team*/ boolean odm_ready; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) - struct rtl8192cd_priv fake_priv; -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - /* ADSL_AP_BUILD_WORKAROUND */ - struct _ADAPTER fake_adapter; -#endif - - enum phy_reg_pg_type phy_reg_pg_value_type; - u8 phy_reg_pg_version; - - u32 debug_components; + enum phy_reg_pg_type phy_reg_pg_value_type; + u8 phy_reg_pg_version; + u64 support_ability; /*@PHYDM function Supportability*/ + u64 pause_ability; /*@PHYDM function pause Supportability*/ + u64 debug_components; + u8 cmn_dbg_msg_period; + u8 cmn_dbg_msg_cnt; u32 fw_debug_components; - u32 debug_level; - - u32 num_qry_phy_status_all; /*CCK + OFDM*/ + u32 num_qry_phy_status_all; /*@CCK + OFDM*/ u32 last_num_qry_phy_status_all; u32 rx_pwdb_ave; - boolean MPDIG_2G; /*off MPDIG*/ - u8 times_2g; boolean is_init_hw_info_by_rfe; - /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ + /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ boolean is_cck_high_power; u8 rf_path_rx_enable; - u8 control_channel; - /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ + /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ + /* @COMMON INFORMATION */ - /* 1 COMMON INFORMATION */ + /*@Init value*/ + /*@-----------HOOK BEFORE REG INIT-----------*/ - /*Init value*/ - /*-----------HOOK BEFORE REG INIT-----------*/ - /*ODM Platform info AP/ADSL/CE/MP = 1/2/3/4*/ - u8 support_platform; - /* ODM Platform info WIN/AP/CE = 1/2/3 */ + u8 support_platform; /*@PHYDM Platform info WIN/AP/CE = 1/2/3 */ u8 normal_rx_path; - /*ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K*/ - u32 support_ability; - /*ODM PCIE/USB/SDIO = 1/2/3*/ - u8 support_interface; - /*ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...*/ - u32 support_ic_type; - /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ - u8 cut_version; - /*Fab version TSMC/UMC = 0/1*/ - u8 fab_version; - /*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ - u8 rf_type; + boolean brxagcswitch; /* @for rx AGC table switch in Microsoft case */ + u8 support_interface; /*@PHYDM PCIE/USB/SDIO = 1/2/3*/ + u32 support_ic_type; /*@PHYDM supported IC*/ + u8 ic_ip_series; /*N/AC/JGR3*/ + u8 cut_version; /*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ + u8 fab_version; /*@Fab version TSMC/UMC = 0/1*/ + u8 fw_version; + u8 fw_sub_version; + u8 rf_type; /*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ u8 rfe_type; - /*Board type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...*/ - /*Enable Function DPK OFF/ON = 0/1*/ - u8 dpk_en; u8 board_type; u8 package_type; u16 type_glna; u16 type_gpa; u16 type_alna; u16 type_apa; - /*with external LNA NO/Yes = 0/1*/ - u8 ext_lna; /*2G*/ - u8 ext_lna_5g; /*5G*/ - /*with external PA NO/Yes = 0/1*/ - u8 ext_pa; /*2G*/ - u8 ext_pa_5g; /*5G*/ - /*with Efuse number*/ - u8 efuse0x3d7; - u8 efuse0x3d8; - /*with external TRSW NO/Yes = 0/1*/ - u8 ext_trsw; - u8 ext_lna_gain; /*2G*/ - u8 patch_id; /*Customer ID*/ + u8 ext_lna; /*@with 2G external LNA NO/Yes = 0/1*/ + u8 ext_lna_5g; /*@with 5G external LNA NO/Yes = 0/1*/ + u8 ext_pa; /*@with 2G external PNA NO/Yes = 0/1*/ + u8 ext_pa_5g; /*@with 5G external PNA NO/Yes = 0/1*/ + u8 efuse0x3d7; /*@with Efuse number*/ + u8 efuse0x3d8; + u8 ext_trsw; /*@with external TRSW NO/Yes = 0/1*/ + u8 ext_lna_gain; /*@gain of external lna*/ boolean is_in_hct_test; u8 wifi_test; - boolean is_dual_mac_smart_concurrent; - u32 bk_support_ability; - u8 ant_div_type; + u32 bk_support_ability; /*SD4 only*/ u8 with_extenal_ant_switch; - boolean config_bbrf; - u8 odm_regulation_2_4g; - u8 odm_regulation_5g; - u8 iqk_fw_offload; + /*@cck agc relative*/ boolean cck_new_agc; - u8 phydm_period; + s8 cck_lna_gain_table[8]; + /*@-------------------------------------*/ u32 phydm_sys_up_time; - u8 num_rf_path; + u8 num_rf_path; /*@ex: 8821C=1, 8192E=2, 8814B=4*/ u32 soft_ap_special_setting; - u32 halmac_ability; - u8 is_receiver_blocking_en; - /*-----------HOOK BEFORE REG INIT-----------*/ - - /*Dynamic value*/ - - /*--------- POINTER REFERENCE-----------*/ - - u8 u1_byte_temp; + s8 s8_dummy; + u8 u8_dummy; + u16 u16_dummy; + u32 u32_dummy; + u8 rfe_hwsetting_band; + u8 p_advance_ota; + boolean hp_hw_id; boolean BOOLEAN_temp; - struct _ADAPTER *PADAPTER_temp; - - /*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/ - u8 *p_mac_phy_mode; - /*TX Unicast byte count*/ - u64 *p_num_tx_bytes_unicast; - /*RX Unicast byte count*/ - u64 *p_num_rx_bytes_unicast; - /*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/ - u8 *p_wireless_mode; - /*Frequence band 2.4G/5G = 0/1*/ - u8 *p_band_type; - /*Secondary channel offset don't_care/below/above = 0/1/2*/ - u8 *p_sec_ch_offset; - /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/ - u8 *p_security; - /*BW info 20M/40M/80M = 0/1/2*/ - u8 *p_band_width; - /*Central channel location Ch1/Ch2/....*/ - u8 *p_channel; /*central channel number*/ - boolean dpk_done; - /*Common info for 92D DMSP*/ - - boolean *p_is_get_value_from_other_mac; - struct _ADAPTER **p_buddy_adapter; - boolean *p_is_master_of_dmsp; /* MAC0: master, MAC1: slave */ - /*Common info for status*/ - boolean *p_is_scan_in_process; - boolean *p_is_power_saving; - /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path_e.*/ - u8 *p_one_path_cca; - u8 *p_antenna_test; - boolean *p_is_net_closed; - u8 *pu1_forced_igi_lb; - boolean *p_is_fcs_mode_enable; - /*--------- For 8723B IQK-----------*/ - boolean *p_is_1_antenna; - u8 *p_rf_default_path; - /* 0:S1, 1:S0 */ - - /*--------- POINTER REFERENCE-----------*/ - u16 *p_forced_data_rate; - u8 *p_enable_antdiv; - u8 *p_enable_adaptivity; - u8 *hub_usb_mode; /*1: USB 2.0, 2: USB 3.0*/ - boolean *p_is_fw_dw_rsvd_page_in_progress; - u32 *p_current_tx_tp; - u32 *p_current_rx_tp; - u8 *p_sounding_seq; - u32 *p_soft_ap_mode; - /*------------CALL BY VALUE-------------*/ + boolean is_dfs_band; + u8 is_rx_blocking_en; + u16 fw_offload_ability; +/*@-----------HOOK BEFORE REG INIT-----------*/ +/*@===========================================================*/ +/*@====[ CALL BY Reference ]=========================================*/ +/*@===========================================================*/ + + u64 *num_tx_bytes_unicast; /*@TX Unicast byte cnt*/ + u64 *num_rx_bytes_unicast; /*@RX Unicast byte cnt*/ + u8 *band_type; /*@2.4G/5G = 0/1*/ + u8 *sec_ch_offset; /*@Secondary channel offset don't_care/below/above = 0/1/2*/ + u8 *security; /*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/ + u8 *band_width; /*@20M/40M/80M = 0/1/2*/ + u8 *channel; /*@central CH number*/ + boolean *is_scan_in_process; + boolean *is_power_saving; + u8 *one_path_cca; /*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/ + u8 *antenna_test; + boolean *is_net_closed; + boolean *is_fcs_mode_enable; + /*@--------- For 8723B IQK-------------------------------------*/ + boolean *is_1_antenna; + u8 *rf_default_path; /* @0:S1, 1:S0 */ + /*@-----------------------------------------------------------*/ + + u16 *forced_data_rate; + u8 *enable_antdiv; + u8 *en_adap_soml; + u8 *enable_adaptivity; + u8 *hub_usb_mode; /*@1:USB2.0, 2:USB3.0*/ + boolean *is_fw_dw_rsvd_page_in_progress; + u32 *current_tx_tp; + u32 *current_rx_tp; + u8 *sounding_seq; + u32 *soft_ap_mode; + u8 *mp_mode; + u32 *interrupt_mask; + u8 *bb_op_mode; +/*@===========================================================*/ +/*@====[ CALL BY VALUE ]===========================================*/ +/*@===========================================================*/ + + u8 disable_phydm_watchdog; boolean is_link_in_process; boolean is_wifi_direct; boolean is_wifi_display; boolean is_linked; - boolean bLinkedcmw500; - boolean is_in_lps_pg; boolean bsta_state; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) /*for repeater mode add by YuChen 2014.06.23*/ -#ifdef UNIVERSAL_REPEATER - boolean vxd_linked; -#endif -#endif u8 rssi_min; - u8 interface_index; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/ + u8 rssi_min_macid; + u8 pre_rssi_min; + u8 rssi_max; + u8 rssi_max_macid; + u8 rssi_min_by_path; boolean is_mp_chip; boolean is_one_entry_only; - boolean mp_mode; u32 one_entry_macid; + u32 one_entry_tp; + u32 pre_one_entry_tp; u8 pre_number_linked_client; u8 number_linked_client; u8 pre_number_active_client; u8 number_active_client; - /*Common info for BTDM*/ - boolean is_bt_enabled; /*BT is enabled*/ - boolean is_bt_connect_process; /*BT HS is under connection progress.*/ - u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/ - boolean is_bt_hs_operation; /*BT HS mode is under progress*/ - u8 bt_hs_dig_val; /*use BT rssi to decide the DIG value*/ - boolean is_bt_disable_edca_turbo; /*Under some condition, don't enable the EDCA Turbo*/ - boolean is_bt_busy; /*BT is busy.*/ - boolean is_bt_limited_dig; /*BT is busy.*/ boolean is_disable_phy_api; - /*------------CALL BY VALUE-------------*/ - u8 RSSI_A; - u8 RSSI_B; - u8 RSSI_C; - u8 RSSI_D; - u64 RSSI_TRSW; - u64 RSSI_TRSW_H; - u64 RSSI_TRSW_L; - u64 RSSI_TRSW_iso; + u8 rssi_a; + u8 rssi_b; + u8 rssi_c; + u8 rssi_d; + s8 rxsc_80; + s8 rxsc_40; + s8 rxsc_20; + s8 rxsc_l; + u64 rssi_trsw; + u64 rssi_trsw_h; + u64 rssi_trsw_l; + u64 rssi_trsw_iso; u8 tx_ant_status; u8 rx_ant_status; u8 cck_lna_idx; u8 cck_vga_idx; u8 curr_station_id; u8 ofdm_agc_idx[4]; - u8 rx_rate; - boolean is_noisy_state; + u8 rate_ss; u8 tx_rate; u8 linked_interval; u8 pre_channel; @@ -733,262 +853,332 @@ enum phy_reg_pg_type { boolean is_txagc_offset_positive_a; u32 txagc_offset_value_b; boolean is_txagc_offset_positive_b; - u32 tx_tp; - u32 rx_tp; - u32 total_tp; + u8 ap_total_num; + /*@[traffic]*/ + u8 traffic_load; + u8 pre_traffic_load; + u32 tx_tp; /*@Mbps*/ + u32 rx_tp; /*@Mbps*/ + u32 total_tp; /*@Mbps*/ + u8 txrx_state_all; /*@0:tx, 1:rx, 2:bi-dir*/ u64 cur_tx_ok_cnt; u64 cur_rx_ok_cnt; u64 last_tx_ok_cnt; u64 last_rx_ok_cnt; - u16 consecutive_idlel_time; /*unit: second*/ - u32 bb_swing_offset_a; + u16 consecutive_idlel_time; /*@unit: second*/ + /*@---------------------------*/ boolean is_bb_swing_offset_positive_a; - u32 bb_swing_offset_b; boolean is_bb_swing_offset_positive_b; - u8 igi_lower_bound; - u8 igi_upper_bound; + + /*@[DIG]*/ + boolean MPDIG_2G; /*off MPDIG*/ + u8 times_2g; /*@for MP DIG*/ + u8 force_igi; /*@for debug*/ + + /*@[TDMA-DIG]*/ + u8 tdma_dig_timer_ms; + u8 tdma_dig_state_number; + u8 tdma_dig_low_upper_bond; + u8 force_tdma_low_igi; + u8 force_tdma_high_igi; + u8 fix_expire_to_zero; + boolean original_dig_restore; + /*@---------------------------*/ + + /*@[AntDiv]*/ + u8 ant_div_type; u8 antdiv_rssi; u8 fat_comb_a; u8 fat_comb_b; u8 antdiv_intvl; u8 ant_type; + u8 ant_type2; u8 pre_ant_type; + u8 pre_ant_type2; u8 antdiv_period; u8 evm_antdiv_period; u8 antdiv_select; + u8 antdiv_train_num; /*@training time for each antenna in EVM method*/ + u8 stop_antdiv_rssi_th; + u16 stop_antdiv_tp_diff_th; + u16 stop_antdiv_tp_th; + u8 antdiv_tp_period; + u16 tp_active_th; + u8 tp_active_occur; u8 path_select; u8 antdiv_evm_en; u8 bdc_holdstate; + u8 antdiv_counter; + /*@---------------------------*/ + u8 ndpa_period; boolean h2c_rarpt_connect; - boolean cck_agc_report_type; - - u8 dm_dig_max_TH; - u8 dm_dig_min_TH; + boolean cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */ u8 print_agc; - u8 traffic_load; - u8 pre_traffic_load; - /*8821C Antenna and RF Set BTG/WLG/WLA Select*/ + u8 la_mode; + /*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/ u8 current_rf_set_8821c; u8 default_rf_set_8821c; u8 current_ant_num_8821c; u8 default_ant_num_8821c; - /*For Adaptivtiy*/ - u16 nhm_cnt_0; - u16 nhm_cnt_1; + u8 rfe_type_expand; + /*@-----------------------------------------------------------*/ + /*@---For Adaptivtiy---------------------------------------------*/ s8 TH_L2H_default; s8 th_edcca_hl_diff_default; s8 th_l2h_ini; s8 th_edcca_hl_diff; - s8 th_l2h_ini_mode2; - s8 th_edcca_hl_diff_mode2; - boolean carrier_sense_enable; - u8 adaptivity_igi_upper; - boolean adaptivity_flag; - u8 dc_backoff; - boolean adaptivity_enable; - u8 ap_total_num; - boolean edcca_enable; - u8 pre_dbg_priority; - struct _ADAPTIVITY_STATISTICS adaptivity; - /*For Adaptivtiy*/ - u8 last_usb_hub; - u8 tx_bf_data_rate; + boolean carrier_sense_enable; + /*@-----------------------------------------------------------*/ + u8 pre_dbg_priority; u8 nbi_set_result; - u8 c2h_cmd_start; u8 fw_debug_trace[60]; u8 pre_c2h_seq; boolean fw_buff_is_enpty; u32 data_frame_num; - /*for noise detection*/ - boolean noisy_decision; /*b_noisy*/ + /*@--- for noise detection ---------------------------------------*/ + boolean is_noisy_state; + boolean noisy_decision; /*@b_noisy*/ boolean pre_b_noisy; u32 noisy_decision_smooth; - boolean is_disable_dym_ecs; + /*@-----------------------------------------------------------*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) - struct _ODM_NOISE_MONITOR_ noise_level; -#endif - /*Define STA info.*/ - /*_ODM_STA_INFO*/ - /*2012/01/12 MH For MP, we need to reduce one array pointer for default port.??*/ - struct sta_info *p_odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; - u16 platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; - /* platform_macid_table[platform_macid] = phydm_macid */ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM]; -#endif + /*@--- for MCC ant weighting ------------------------------------*/ + boolean is_stop_dym_ant_weighting; + /*@-----------------------------------------------------------*/ + + boolean is_disable_dym_ecs; + boolean is_disable_dym_ant_weighting; + struct sta_info *odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; + struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; + u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/ #if (RATE_ADAPTIVE_SUPPORT == 1) u16 currmin_rpt_time; - struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM]; - /*Use mac_id as array index. STA mac_id=0, VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ + struct _phydm_txstatistic_ hw_stats; + struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM]; +/*Use mac_id as array index. STA mac_id=0*/ +/*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ #endif - - /*2012/02/14 MH Add to share 88E ra with other SW team.*/ + /*@2012/02/14 MH Add to share 88E ra with other SW team*/ /*We need to colelct all support abilit to a proper area.*/ + boolean ra_support88e; + boolean *is_driver_stopped; + boolean *is_driver_is_going_to_pnp_set_power_sleep; + boolean *pinit_adpt_in_progress; + boolean is_user_assign_level; + u8 RSSI_BT; /*@come from BT*/ - boolean ra_support88e; + /*@---PSD Relative ---------------------------------------------*/ + boolean is_psd_in_process; + boolean is_psd_active; + /*@-----------------------------------------------------------*/ - struct _odm_phy_dbg_info_ phy_dbg_info; + boolean bsomlenabled; /* @D-SoML control */ + boolean bhtstfdisabled; /* @dynamic HTSTF gain control*/ + boolean disrxhpsoml; /* @RxHP control with D-SoML*/ + u32 n_iqk_cnt; + u32 n_iqk_ok_cnt; + u32 n_iqk_fail_cnt; - /*ODM Structure*/ - struct _DFS_STATISTICS dfs; -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct _BF_DIV_COEX_ dm_bdc_table; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + boolean config_bbrf; #endif - -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) - struct _SMART_ANTENNA_TRAINNING_ dm_sat_table; + boolean is_disable_power_training; + boolean is_bt_continuous_turn; + u8 enhance_pwr_th[3]; + u8 set_pwr_th[3]; + /*@----------Dyn Tx Pwr ---------------------------------------*/ +#ifdef BB_RAM_SUPPORT + struct phydm_bb_ram_ctrl p_bb_ram_ctrl; #endif + u8 dynamic_tx_high_power_lvl; + void (*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power); + u8 last_dtp_lvl; + u8 min_power_index; + u32 tx_agc_ofdm_18_6; + /*-------------------------------------------------------------*/ + u8 rx_pkt_type; +#ifdef CONFIG_PHYDM_DFS_MASTER + u8 dfs_region_domain; + u8 *dfs_master_enabled; + /*@---phydm_radar_detect_with_dbg_parm start --------------------*/ + u8 radar_detect_dbg_parm_en; + u32 radar_detect_reg_918; + u32 radar_detect_reg_91c; + u32 radar_detect_reg_920; + u32 radar_detect_reg_924; +/*@-----------------------------------------------------------*/ #endif - struct _FAST_ANTENNA_TRAINNING_ dm_fat_table; - struct _dynamic_initial_gain_threshold_ dm_dig_table; -#if (defined(CONFIG_BB_POWER_SAVING)) - struct _dynamic_power_saving dm_ps_table; + +/*@=== PHYDM Timer ========================================== (start)*/ + + struct phydm_timer_list mpt_dig_timer; + struct phydm_timer_list fast_ant_training_timer; +#ifdef ODM_EVM_ENHANCE_ANTDIV + struct phydm_timer_list evm_fast_ant_training_timer; #endif - struct _dynamic_primary_cca dm_pri_cca; - struct _rate_adaptive_table_ dm_ra_table; - struct _FALSE_ALARM_STATISTICS false_alm_cnt; - struct _FALSE_ALARM_STATISTICS flase_alm_cnt_buddy_adapter; - struct _sw_antenna_switch_ dm_swat_table; - struct _CFO_TRACKING_ dm_cfo_track; - struct _ACS_ dm_acs; - struct _CCX_INFO dm_ccx_info; -#if (CONFIG_PSD_TOOL == 1) - struct _PHYDM_PSD_ dm_psd_table; +#ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_timer_list tdma_dig_timer; #endif - -#if (PHYDM_LA_MODE_SUPPORT == 1) - struct _RT_ADCSMP adcsmp; + struct phydm_timer_list sbdcnt_timer; + +/*@=== PHYDM Workitem ======================================= (start)*/ + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM fast_ant_training_workitem; + RT_WORK_ITEM ra_rpt_workitem; + RT_WORK_ITEM sbdcnt_workitem; + RT_WORK_ITEM phydm_evm_antdiv_workitem; #endif -#if (CONFIG_DYNAMIC_RX_PATH == 1) - struct _DYNAMIC_RX_PATH_ dm_drp_table; #endif -#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - struct _IQK_INFORMATION IQK_info; -#endif +/*@=== PHYDM Structure ======================================== (start)*/ + struct phydm_func_poiner phydm_func_handler; + struct phydm_iot_center iot_table; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - /*path Div Struct*/ - struct _path_div_parameter_define_ path_iqk; +#ifdef ODM_CONFIG_BT_COEXIST + struct phydm_bt_info bt_info_table; #endif -#if (defined(CONFIG_PATH_DIVERSITY)) - struct _ODM_PATH_DIVERSITY_ dm_path_div; + + struct pkt_process_info pkt_proc_struct; + struct phydm_adaptivity_struct adaptivity; + struct _DFS_STATISTICS dfs; + struct odm_noise_monitor noise_level; + struct odm_phy_dbg_info phy_dbg_info; + +#ifdef CONFIG_ADAPTIVE_SOML + struct adaptive_soml dm_soml_table; #endif -#if PHYDM_SUPPORT_EDCA - struct _EDCA_TURBO_ dm_edca_table; - u32 WMMEDCA_BE; +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + struct _BF_DIV_COEX_ dm_bdc_table; + #endif + + #if (defined(CONFIG_HL_SMART_ANTENNA)) + struct smt_ant_honbo dm_sat_table; + #endif #endif - boolean *p_is_driver_stopped; - boolean *p_is_driver_is_going_to_pnp_set_power_sleep; - boolean *pinit_adpt_in_progress; +#if (defined(CONFIG_SMART_ANTENNA)) + struct smt_ant smtant_table; +#endif - /*PSD*/ - boolean is_user_assign_level; - u8 RSSI_BT; /*come from BT*/ - boolean is_psd_in_process; - boolean is_psd_active; - boolean is_dm_initial_gain_enable; + struct _hal_rf_ rf_table; /*@for HALRF function*/ + struct dm_rf_calibration_struct rf_calibrate_info; + struct dm_iqk_info IQK_info; + struct dm_dpk_info dpk_info; - /*MPT DIG*/ - struct timer_list mpt_dig_timer; +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + struct phydm_fat_struct dm_fat_table; + struct sw_antenna_switch dm_swat_table; +#endif + struct phydm_dig_struct dm_dig_table; +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + struct phydm_lna_sat_t dm_lna_sat_info; +#endif - /*for rate adaptive, in fact, 88c/92c fw will handle this*/ - u8 is_use_ra_mask; +#ifdef CONFIG_MCC_DM + struct _phydm_mcc_dm_ mcc_dm; +#endif - /* for dynamic SoML control */ - boolean bsomlenabled; +#ifdef PHYDM_SUPPORT_CCKPD + struct phydm_cckpd_struct dm_cckpd_table; +#endif - /* for dynamic HTSTF gain control */ - boolean bhtstfenabled; +#ifdef PHYDM_PRIMARY_CCA + struct phydm_pricca_struct dm_pri_cca; +#endif - struct _ODM_RATE_ADAPTIVE rate_adaptive; -#if (defined(CONFIG_ANT_DETECTION)) - struct _ANT_DETECTED_INFO ant_detected_info; /* Antenna detected information for RSSI tool*/ + struct ra_table dm_ra_table; + struct phydm_fa_struct false_alm_cnt; +#ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_fa_acc_struct false_alm_cnt_acc; +#ifdef IS_USE_NEW_TDMA + struct phydm_fa_acc_struct false_alm_cnt_acc_low; +#endif #endif - struct odm_rf_calibration_structure rf_calibrate_info; - struct odm_power_trim_data power_trim_data; + struct phydm_cfo_track_struct dm_cfo_track; + struct ccx_info dm_ccx_info; - u32 n_iqk_cnt; - u32 n_iqk_ok_cnt; - u32 n_iqk_fail_cnt; + struct odm_power_trim_data power_trim_data; +#if (RTL8822B_SUPPORT == 1) + struct drp_rtl8822b_struct phydm_rtl8822b; +#endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - /*Power Training*/ - u8 force_power_training_state; - boolean is_change_state; - u32 PT_score; - u64 ofdm_rx_cnt; - u64 cck_rx_cnt; +#ifdef CONFIG_PSD_TOOL + struct psd_info dm_psd_table; #endif - boolean is_disable_power_training; - u8 dynamic_tx_high_power_lvl; - u8 last_dtp_lvl; - u32 tx_agc_ofdm_18_6; - u8 rx_pkt_type; - /*ODM relative time.*/ - struct timer_list path_div_switch_timer; - /*2011.09.27 add for path Diversity*/ - struct timer_list cck_path_diversity_timer; - struct timer_list fast_ant_training_timer; -#ifdef ODM_EVM_ENHANCE_ANTDIV - struct timer_list evm_fast_ant_training_timer; +#if (PHYDM_LA_MODE_SUPPORT == 1) + struct rt_adcsmp adcsmp; #endif - struct timer_list sbdcnt_timer; - /*ODM relative workitem.*/ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#if USE_WORKITEM - RT_WORK_ITEM path_div_switch_workitem; - RT_WORK_ITEM cck_path_diversity_workitem; - RT_WORK_ITEM fast_ant_training_workitem; - RT_WORK_ITEM mpt_dig_workitem; - RT_WORK_ITEM ra_rpt_workitem; - RT_WORK_ITEM sbdcnt_workitem; +#if (defined(CONFIG_PATH_DIVERSITY)) + struct _ODM_PATH_DIVERSITY_ dm_path_div; #endif + +#if (defined(CONFIG_ANT_DETECTION)) + struct _ANT_DETECTED_INFO ant_detected_info; #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) #if (BEAMFORMING_SUPPORT == 1) - struct _RT_BEAMFORMING_INFO beamforming_info; + struct _RT_BEAMFORMING_INFO beamforming_info; #endif +#endif +#ifdef PHYDM_AUTO_DEGBUG + struct phydm_auto_dbg_struct auto_dbg_table; #endif -#ifdef CONFIG_PHYDM_DFS_MASTER - u8 dfs_region_domain; - u8 *dfs_master_enabled; - - /*====== phydm_radar_detect_with_dbg_parm start ======*/ - u8 radar_detect_dbg_parm_en; - u32 radar_detect_reg_918; - u32 radar_detect_reg_91c; - u32 radar_detect_reg_920; - u32 radar_detect_reg_924; - /*====== phydm_radar_detect_with_dbg_parm end ======*/ + struct phydm_pause_lv pause_lv_table; + struct phydm_api_stuc api_table; +#ifdef PHYDM_POWER_TRAINING_SUPPORT + struct phydm_pow_train_stuc pow_train_table; #endif +#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT + struct phydm_pmac_tx dm_pmac_tx_table; +#endif + +#ifdef PHYDM_MP_SUPPORT + struct phydm_mp dm_mp_table; +#endif +/*@==========================================================*/ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) #if (RT_PLATFORM != PLATFORM_LINUX) -}PHY_DM_STRUCT; /*DM_Dynamic_Mechanism_Structure*/ +} dm_struct; /*@DM_Dynamic_Mechanism_Structure*/ #else }; #endif -#else /*for AP,ADSL,CE Team*/ +#else /*@for AP,CE Team*/ }; #endif +enum phydm_adv_ota { + PHYDM_PATHB_1RCCA = BIT(0), + PHYDM_HP_OTA_SETTING_A = BIT(1), + PHYDM_HP_OTA_SETTING_B = BIT(2), + PHYDM_ASUS_OTA_SETTING = BIT(3), + PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4), + PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5), + PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6), + +}; + +enum phydm_bb_op_mode { + PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/ + PHYDM_BALANCE_MODE = 1, /*@Service more than one device*/ +}; enum phydm_structure_type { PHYDM_FALSEALMCNT, @@ -999,15 +1189,6 @@ enum phydm_structure_type { }; - - -enum odm_rf_content { - odm_radioa_txt = 0x1000, - odm_radiob_txt = 0x1001, - odm_radioc_txt = 0x1002, - odm_radiod_txt = 0x1003 -}; - enum odm_bb_config_type { CONFIG_BB_PHY_REG, CONFIG_BB_AGC_TAB, @@ -1016,6 +1197,7 @@ enum odm_bb_config_type { CONFIG_BB_PHY_REG_PG, CONFIG_BB_PHY_REG_MP, CONFIG_BB_AGC_TAB_DIFF, + CONFIG_BB_RF_CAL_INIT, }; enum odm_rf_config_type { @@ -1047,317 +1229,112 @@ enum rt_status { RT_STATUS_NOT_SUPPORT, RT_STATUS_OS_API_FAILED, }; -#endif /*end of enum rt_status definition*/ - -#ifdef REMOVE_PACK - #pragma pack() -#endif - -/*===========================================================*/ -/*AGC RX High Power mode*/ -/*===========================================================*/ -#define lna_low_gain_1 0x64 -#define lna_low_gain_2 0x5A -#define lna_low_gain_3 0x58 - -#define FA_RXHP_TH1 5000 -#define FA_RXHP_TH2 1500 -#define FA_RXHP_TH3 800 -#define FA_RXHP_TH4 600 -#define FA_RXHP_TH5 500 - -enum dm_1r_cca_e { - CCA_1R = 0, - CCA_2R = 1, - CCA_MAX = 2, -}; - -enum dm_rf_e { - rf_save = 0, - rf_normal = 1, - RF_MAX = 2, -}; - -/*check Sta pointer valid or not*/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #define IS_STA_VALID(p_sta) (p_sta && p_sta->expire_to) -#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - #define IS_STA_VALID(p_sta) (p_sta && p_sta->bUsed) -#else - #define IS_STA_VALID(p_sta) (p_sta) -#endif +#endif /*@end of enum rt_status definition*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP)) - -boolean -odm_check_power_status( - struct _ADAPTER *adapter -); - -#endif - -u32 odm_convert_to_db(u32 value); - -u32 odm_convert_to_linear(u32 value); - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) void -odm_dm_watchdog_lps( - struct PHY_DM_STRUCT *p_dm_odm -); -#endif - - -s32 -odm_pwdb_conversion( - s32 X, - u32 total_bit, - u32 decimal_bit -); - -s32 -odm_sign_conversion( - s32 value, - u32 total_bit -); +phydm_watchdog_lps(struct dm_struct *dm); void -odm_init_mp_driver_status( - struct PHY_DM_STRUCT *p_dm_odm -); +phydm_watchdog_lps_32k(struct dm_struct *dm); void -phydm_txcurrentcalibration( - struct PHY_DM_STRUCT *p_dm_odm -); +phydm_txcurrentcalibration(struct dm_struct *dm); +void +phydm_dm_early_init(struct dm_struct *dm); void -phydm_seq_sorting( - void *p_dm_void, - u32 *p_value, - u32 *rank_idx, - u32 *p_idx_out, - u8 seq_length -); +odm_dm_init(struct dm_struct *dm); void -odm_dm_init( - struct PHY_DM_STRUCT *p_dm_odm -); +odm_dm_reset(struct dm_struct *dm); void -odm_dm_reset( - struct PHY_DM_STRUCT *p_dm_odm -); +phydm_fwoffload_ability_init(struct dm_struct *dm, + enum phydm_offload_ability offload_ability); void -phydm_support_ability_debug( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -); +phydm_fwoffload_ability_clear(struct dm_struct *dm, + enum phydm_offload_ability offload_ability); void -phydm_config_ofdm_rx_path( - struct PHY_DM_STRUCT *p_dm_odm, - u32 path -); +phydm_supportability_en(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); void -phydm_config_trx_path( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -); +phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type); void -odm_dm_watchdog( - struct PHY_DM_STRUCT *p_dm_odm -); +phydm_watchdog(struct dm_struct *dm); void -phydm_watchdog_mp( - struct PHY_DM_STRUCT *p_dm_odm -); +phydm_watchdog_mp(struct dm_struct *dm); + +u8 +phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf); void -odm_cmn_info_init( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, - u32 value -); +phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); void -odm_cmn_info_hook( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, - void *p_value -); +odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value); void -odm_cmn_info_ptr_array_hook( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_cmninfo_e cmn_info, - u16 index, - void *p_value -); +odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value); void -odm_cmn_info_update( - struct PHY_DM_STRUCT *p_dm_odm, - u32 cmn_info, - u64 value -); +odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value); u32 -phydm_cmn_info_query( - struct PHY_DM_STRUCT *p_dm_odm, - enum phydm_info_query_e info_type -); +phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type); -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) void -odm_init_all_threads( - struct PHY_DM_STRUCT *p_dm_odm -); +odm_init_all_timers(struct dm_struct *dm); void -odm_stop_all_threads( - struct PHY_DM_STRUCT *p_dm_odm -); -#endif +odm_cancel_all_timers(struct dm_struct *dm); void -odm_init_all_timers( - struct PHY_DM_STRUCT *p_dm_odm -); +odm_release_all_timers(struct dm_struct *dm); -void -odm_cancel_all_timers( - struct PHY_DM_STRUCT *p_dm_odm -); +void * +phydm_get_structure(struct dm_struct *dm, u8 structure_type); void -odm_release_all_timers( - struct PHY_DM_STRUCT *p_dm_odm -); +phydm_dc_cancellation(struct dm_struct *dm); +void +phydm_receiver_blocking(void *dm_void); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void odm_init_all_work_items(struct PHY_DM_STRUCT *p_dm_odm); -void odm_free_all_work_items(struct PHY_DM_STRUCT *p_dm_odm); - -u64 -platform_division64( - u64 x, - u64 y -); - -#define dm_change_dynamic_init_gain_thresh odm_change_dynamic_init_gain_thresh - -enum dm_dig_connect_e { - DIG_STA_DISCONNECT = 0, - DIG_STA_CONNECT = 1, - DIG_STA_BEFORE_CONNECT = 2, - DIG_MULTI_STA_DISCONNECT = 3, - DIG_MULTI_STA_CONNECT = 4, - DIG_CONNECT_MAX -}; - -/*2012/01/12 MH Check afapter status. Temp fix BSOD.*/ - -#define HAL_ADAPTER_STS_CHK(p_dm_odm) do {\ - if (p_dm_odm->adapter == NULL) { \ - \ - return;\ - } \ - } while (0) - -#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ - void -odm_asoc_entry_init( - struct PHY_DM_STRUCT *p_dm_odm +odm_init_all_work_items( + struct dm_struct *dm ); - - -void * -phydm_get_structure( - struct PHY_DM_STRUCT *p_dm_odm, - u8 structure_type +void +odm_free_all_work_items( + struct dm_struct *dm ); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) || (DM_ODM_SUPPORT_TYPE == ODM_CE) - /*===========================================================*/ - /* The following is for compile only*/ - /*===========================================================*/ - - #define IS_HARDWARE_TYPE_8723A(_adapter) false - #define IS_HARDWARE_TYPE_8723AE(_adapter) false - #define IS_HARDWARE_TYPE_8192C(_adapter) false - #define IS_HARDWARE_TYPE_8192D(_adapter) false - #define RF_T_METER_92D 0x42 - - - #define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) LE_BITS_TO_1BYTE(__prx_status_desc+12, 0, 6) - - #define REG_CONFIG_RAM64X16 0xb2c - - #define TARGET_CHNL_NUM_2G_5G 59 - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - u8 get_right_chnl_place_for_iqk(u8 chnl); - #endif - - /* *********************************************************** */ -#endif +#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - void odm_dtc(struct PHY_DM_STRUCT *p_dm_odm); -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ - - -void phydm_noisy_detection(struct PHY_DM_STRUCT *p_dm_odm); - - +void +odm_dtc(struct dm_struct *dm); #endif +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) void -phydm_set_ext_switch( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len +odm_init_all_threads( + struct dm_struct *dm ); void -phydm_api_debug( - void *p_dm_void, - u32 function_map, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -); - -u8 -phydm_nbi_setting( - void *p_dm_void, - u32 enable, - u32 channel, - u32 bw, - u32 f_interference, - u32 second_ch +odm_stop_all_threads( + struct dm_struct *dm ); +#endif -void -phydm_receiver_blocking( - void *p_dm_void -); +#endif diff --git a/hal/phydm/phydm.mk b/hal/phydm/phydm.mk new file mode 100644 index 0000000..4fca7e8 --- /dev/null +++ b/hal/phydm/phydm.mk @@ -0,0 +1,217 @@ +EXTRA_CFLAGS += -I$(srctree)/$(src)/hal/phydm + +_PHYDM_FILES := hal/phydm/phydm_debug.o \ + hal/phydm/phydm_antdiv.o\ + hal/phydm/phydm_soml.o\ + hal/phydm/phydm_smt_ant.o\ + hal/phydm/phydm_antdect.o\ + hal/phydm/phydm_interface.o\ + hal/phydm/phydm_phystatus.o\ + hal/phydm/phydm_hwconfig.o\ + hal/phydm/phydm.o\ + hal/phydm/phydm_dig.o\ + hal/phydm/phydm_pathdiv.o\ + hal/phydm/phydm_rainfo.o\ + hal/phydm/phydm_dynamictxpower.o\ + hal/phydm/phydm_adaptivity.o\ + hal/phydm/phydm_cfotracking.o\ + hal/phydm/phydm_noisemonitor.o\ + hal/phydm/phydm_beamforming.o\ + hal/phydm/phydm_dfs.o\ + hal/phydm/txbf/halcomtxbf.o\ + hal/phydm/txbf/haltxbfinterface.o\ + hal/phydm/txbf/phydm_hal_txbf_api.o\ + hal/phydm/phydm_adc_sampling.o\ + hal/phydm/phydm_ccx.o\ + hal/phydm/phydm_psd.o\ + hal/phydm/phydm_primary_cca.o\ + hal/phydm/phydm_cck_pd.o\ + hal/phydm/phydm_rssi_monitor.o\ + hal/phydm/phydm_auto_dbg.o\ + hal/phydm/phydm_math_lib.o\ + hal/phydm/phydm_api.o\ + hal/phydm/phydm_pow_train.o\ + hal/phydm/phydm_lna_sat.o\ + hal/phydm/phydm_pmac_tx_setting.o\ + hal/phydm/phydm_mp.o\ + hal/phydm/halrf/halrf.o\ + hal/phydm/halrf/halrf_debug.o\ + hal/phydm/halrf/halphyrf_ce.o\ + hal/phydm/halrf/halrf_powertracking_ce.o\ + hal/phydm/halrf/halrf_powertracking.o\ + hal/phydm/halrf/halrf_kfree.o + +ifeq ($(CONFIG_RTL8188E), y) +RTL871X = rtl8188e +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\ + hal/phydm/$(RTL871X)/hal8188erateadaptive.o\ + hal/phydm/$(RTL871X)/phydm_rtl8188e.o +endif + +ifeq ($(CONFIG_RTL8192E), y) +RTL871X = rtl8192e +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\ + hal/phydm/$(RTL871X)/phydm_rtl8192e.o +endif + + +ifeq ($(CONFIG_RTL8812A), y) +RTL871X = rtl8812a +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\ + hal/phydm/$(RTL871X)/phydm_rtl8812a.o\ + hal/phydm/txbf/haltxbfjaguar.o +endif + +ifeq ($(CONFIG_RTL8821A), y) +RTL871X = rtl8821a +_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\ + hal/phydm/rtl8821a/halhwimg8821a_bb.o\ + hal/phydm/rtl8821a/halhwimg8821a_rf.o\ + hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\ + hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\ + hal/phydm/rtl8821a/phydm_regconfig8821a.o\ + hal/phydm/rtl8821a/phydm_rtl8821a.o\ + hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\ + hal/phydm/txbf/haltxbfjaguar.o +endif + + +ifeq ($(CONFIG_RTL8723B), y) +RTL871X = rtl8723b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\ + hal/phydm/$(RTL871X)/phydm_rtl8723b.o +endif + + +ifeq ($(CONFIG_RTL8814A), y) +RTL871X = rtl8814a +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\ + hal/phydm/$(RTL871X)/phydm_rtl8814a.o\ + hal/phydm/txbf/haltxbf8814a.o +endif + + +ifeq ($(CONFIG_RTL8723C), y) +RTL871X = rtl8703b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\ + hal/phydm/$(RTL871X)/phydm_rtl8703b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8703b.o +endif + +ifeq ($(CONFIG_RTL8723D), y) +RTL871X = rtl8723d +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\ + hal/phydm/$(RTL871X)/phydm_rtl8723d.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8723d.o +endif + + +ifeq ($(CONFIG_RTL8710B), y) +RTL871X = rtl8710b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\ + hal/phydm/$(RTL871X)/phydm_rtl8710b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8710b.o +endif + + +ifeq ($(CONFIG_RTL8188F), y) +RTL871X = rtl8188f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \ + hal/phydm/$(RTL871X)/phydm_rtl8188f.o +endif + +ifeq ($(CONFIG_RTL8822B), y) +RTL871X = rtl8822b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \ + hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \ + hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \ + hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \ + hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \ + hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \ + hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \ + hal/phydm/$(RTL871X)/phydm_rtl8822b.o + +_PHYDM_FILES += hal/phydm/txbf/haltxbf8822b.o +endif + + +ifeq ($(CONFIG_RTL8821C), y) +RTL871X = rtl8821c +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \ + hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \ + hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \ + hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \ + hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o +endif +ifeq ($(CONFIG_RTL8192F), y) +RTL871X = rtl8192f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\ + hal/phydm/$(RTL871X)/phydm_rtl8192f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8192f.o +endif + +ifeq ($(CONFIG_RTL8198F), y) +RTL871X = rtl8198f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8198f.o +endif + +ifeq ($(CONFIG_RTL8822C), y) +RTL871X = rtl8822c +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8822c_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8822c_rf.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8822c.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8822c.o +endif + +ifeq ($(CONFIG_RTL8814B), y) +RTL871X = rtl8814b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8814b.o +endif diff --git a/hal/phydm/phydm_adaptivity.c b/hal/phydm/phydm_adaptivity.c index fa22237..05817fc 100644 --- a/hal/phydm/phydm_adaptivity.c +++ b/hal/phydm/phydm_adaptivity.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,19 +8,24 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -/* ************************************************************ +/*@************************************************************ * include files - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" @@ -29,516 +34,224 @@ #include "PhyDM_Adaptivity.tmh" #endif #endif - - -void -phydm_check_adaptivity( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); - - if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (p_dm_odm->ap_total_num > adaptivity->ap_num_th) { - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", adaptivity->ap_num_th)); - } else -#endif - { - if (adaptivity->dynamic_link_adaptivity || adaptivity->acs_for_adaptivity) { - if (p_dm_odm->is_linked && adaptivity->is_check == false) { - phydm_nhm_counter_statistics(p_dm_odm); - phydm_check_environment(p_dm_odm); - } else if (!p_dm_odm->is_linked) - adaptivity->is_check = false; - } else { - p_dm_odm->adaptivity_enable = true; - - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) - p_dm_odm->adaptivity_flag = false; - else - p_dm_odm->adaptivity_flag = true; - } - } - } else { - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; - } - - - -} - +#ifdef PHYDM_SUPPORT_ADAPTIVITY #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) boolean -phydm_check_channel_plan( - void *p_dm_void -) +phydm_check_channel_plan(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &(p_adapter->MgntInfo); - - if (p_mgnt_info->RegEnableAdaptivity == 2) { - if (p_dm_odm->carrier_sense_enable == false) { /*check domain Code for adaptivity or CarrierSense*/ - if ((*p_dm_odm->p_band_type == ODM_BAND_5G) && - !(p_dm_odm->odm_regulation_5g == REGULATION_ETSI || p_dm_odm->odm_regulation_5g == REGULATION_WW)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity skip 5G domain code : %d\n", p_dm_odm->odm_regulation_5g)); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; - return true; - } else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) && - !(p_dm_odm->odm_regulation_2_4g == REGULATION_ETSI || p_dm_odm->odm_regulation_2_4g == REGULATION_WW)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity skip 2.4G domain code : %d\n", p_dm_odm->odm_regulation_2_4g)); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; - return true; - - } else if ((*p_dm_odm->p_band_type != ODM_BAND_2_4G) && (*p_dm_odm->p_band_type != ODM_BAND_5G)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity neither 2G nor 5G band, return\n")); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; - return true; - } - } else { - if ((*p_dm_odm->p_band_type == ODM_BAND_5G) && - !(p_dm_odm->odm_regulation_5g == REGULATION_MKK || p_dm_odm->odm_regulation_5g == REGULATION_WW)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", p_dm_odm->odm_regulation_5g)); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; - return true; - } + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; - else if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) && - !(p_dm_odm->odm_regulation_2_4g == REGULATION_MKK || p_dm_odm->odm_regulation_2_4g == REGULATION_WW)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", p_dm_odm->odm_regulation_2_4g)); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; - return true; - - } else if ((*p_dm_odm->p_band_type != ODM_BAND_2_4G) && (*p_dm_odm->p_band_type != ODM_BAND_5G)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n")); - p_dm_odm->adaptivity_enable = false; - p_dm_odm->adaptivity_flag = false; - return true; - } + if (mgnt_info->RegEnableAdaptivity != 2) + return false; + + if (!dm->carrier_sense_enable) { /*@check domain Code for adaptivity or CarrierSense*/ + if ((*dm->band_type == ODM_BAND_5G) && + !(adapt->regulation_5g == REGULATION_ETSI || adapt->regulation_5g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "adaptivity skip 5G domain code : %d\n", + adapt->regulation_5g); + return true; + } else if ((*dm->band_type == ODM_BAND_2_4G) && + !(adapt->regulation_2g == REGULATION_ETSI || adapt->regulation_2g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "adaptivity skip 2.4G domain code : %d\n", + adapt->regulation_2g); + return true; + } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "adaptivity neither 2G nor 5G band, return\n"); + return true; + } + } else { + if ((*dm->band_type == ODM_BAND_5G) && + !(adapt->regulation_5g == REGULATION_MKK || adapt->regulation_5g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "CarrierSense skip 5G domain code : %d\n", + adapt->regulation_5g); + return true; + } else if ((*dm->band_type == ODM_BAND_2_4G) && + !(adapt->regulation_2g == REGULATION_MKK || adapt->regulation_2g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "CarrierSense skip 2.4G domain code : %d\n", + adapt->regulation_2g); + return true; + } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "CarrierSense neither 2G nor 5G band, return\n"); + return true; } } return false; - } -#endif -void -phydm_nhm_counter_statistics_init( - void *p_dm_void -) +boolean +phydm_soft_ap_special_set(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - /*PHY parameters initialize for n series*/ - odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N + 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ - odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_FPGA0_IQK_11N, MASKBYTE0, 0xff); /*0xe28[7:0]=0xff th_8*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10) | BIT9 | BIT8, 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(7), 0x1); /*0xc0c[7]=1 max power among all RX ants*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY); + u8 disable_ap_adapt_setting = false; + + if (dm->soft_ap_mode != NULL) { + if (*dm->soft_ap_mode != 0 && + (dm->soft_ap_special_setting & BIT(0))) + disable_ap_adapt_setting = true; + else + disable_ap_adapt_setting = false; + PHYDM_DBG(dm, DBG_ADPTVTY, + "soft_ap_setting = %x, soft_ap = %d, dis_ap_adapt = %d\n", + dm->soft_ap_special_setting, *dm->soft_ap_mode, + disable_ap_adapt_setting); } -#if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - /*PHY parameters initialize for ac series*/ - odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ - odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/ - odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, 0xff); /*0x9a0[7:0]=0xff th_8*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8) | BIT9 | BIT10, 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_9E8_11AC, BIT(0), 0x1); /*0x9e8[7]=1 max power among all RX ants*/ - } -#endif + return disable_ap_adapt_setting; } - -void -phydm_nhm_counter_statistics( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) - return; - - /*Get NHM report*/ - phydm_get_nhm_counter_statistics(p_dm_odm); - - /*Reset NHM counter*/ - phydm_nhm_counter_statistics_reset(p_dm_odm); -} - -void -phydm_get_nhm_counter_statistics( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 value32 = 0; -#if (RTL8195A_SUPPORT == 0) - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_CNT_11AC, MASKDWORD); - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) #endif - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_CNT_11N, MASKDWORD); - p_dm_odm->nhm_cnt_0 = (u8)(value32 & MASKBYTE0); - p_dm_odm->nhm_cnt_1 = (u8)((value32 & MASKBYTE1) >> 8); - -} - -void -phydm_nhm_counter_statistics_reset( - void *p_dm_void -) +void phydm_dig_up_bound_lmt_en(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1); - } -#if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + + if (!(dm->support_ability & ODM_BB_ADAPTIVITY) || + !dm->is_linked || + !adapt->is_adapt_en) { + adapt->igi_up_bound_lmt_cnt = 0; + adapt->igi_lmt_en = false; + return; } -#endif - -} - -void -phydm_set_edcca_threshold( - void *p_dm_void, - s8 H2L, - s8 L2H -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)L2H | (u8)H2L << 16)); -#if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)L2H | (u8)H2L << 8)); -#endif + if (dm->total_tp > 1) { + adapt->igi_lmt_en = true; + adapt->igi_up_bound_lmt_cnt = adapt->igi_up_bound_lmt_val; + PHYDM_DBG(dm, DBG_ADPTVTY, + "TP >1, Start limit IGI upper bound\n"); + } else { + if (adapt->igi_up_bound_lmt_cnt == 0) + adapt->igi_lmt_en = false; + else + adapt->igi_up_bound_lmt_cnt--; + } + PHYDM_DBG(dm, DBG_ADPTVTY, "IGI_lmt_cnt = %d\n", + adapt->igi_up_bound_lmt_cnt); } -void -phydm_set_lna( - void *p_dm_void, - enum phydm_set_lna type -) +void phydm_check_adaptivity(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) { - if (type == phydm_disable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); - } - } else if (type == phydm_enable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); - } - } - } else if (p_dm_odm->support_ic_type & ODM_RTL8723B) { - if (type == phydm_disable_lna) { - /*S0*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - /*S1*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); - } else if (type == phydm_enable_lna) { - /*S0*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - /*S1*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); - } + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; - } else if (p_dm_odm->support_ic_type & ODM_RTL8812) { - if (type == phydm_disable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); - } - } else if (type == phydm_enable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); - } - } - } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { - if (type == phydm_disable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - } else if (type == phydm_enable_lna) { - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); - } + if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) { + adaptivity->is_adapt_en = false; + return; } -} - - -void -phydm_set_trx_mux( - void *p_dm_void, - enum phydm_trx_mux_type tx_mode, - enum phydm_trx_mux_type rx_mode -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(3) | BIT2 | BIT1, tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(22) | BIT21 | BIT20, rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(3) | BIT2 | BIT1, tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(22) | BIT21 | BIT20, rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ - } - } -#if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(11) | BIT10 | BIT9 | BIT8, tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(7) | BIT6 | BIT5 | BIT4, rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ - if (p_dm_odm->rf_type > ODM_1T1R) { - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC_B, BIT(11) | BIT10 | BIT9 | BIT8, tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC_B, BIT(7) | BIT6 | BIT5 | BIT4, rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ - } +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (phydm_check_channel_plan(dm) || + dm->ap_total_num > adaptivity->ap_num_th || + phydm_soft_ap_special_set(dm)) { + adaptivity->is_adapt_en = false; + PHYDM_DBG(dm, DBG_ADPTVTY, + "AP total num > %d!!, disable adaptivity\n", + adaptivity->ap_num_th); + return; } #endif + adaptivity->is_adapt_en = true; } -void -phydm_mac_edcca_state( - void *p_dm_void, - enum phydm_mac_edcca_type state -) +void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (state == phydm_ignore_edcca) { - odm_set_mac_reg(p_dm_odm, REG_TX_PTCL_CTRL, BIT(15), 1); /*ignore EDCCA reg520[15]=1*/ - /* odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 0); */ /*reg524[11]=0*/ - } else { /*don't set MAC ignore EDCCA signal*/ - odm_set_mac_reg(p_dm_odm, REG_TX_PTCL_CTRL, BIT(15), 0); /*don't ignore EDCCA reg520[15]=0*/ - /* odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 1); */ /*reg524[11]=1 */ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0x84c, MASKBYTE2, (u8)L2H + 128 - 4); + odm_set_bb_reg(dm, R_0x84c, MASKBYTE3, (u8)H2L + 128 - 4); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, (u8)L2H); + odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, (u8)H2L); + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x8a4, MASKBYTE0, (u8)L2H); + odm_set_bb_reg(dm, R_0x8a4, MASKBYTE1, (u8)H2L); } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable state = %d\n", state)); - } -boolean -phydm_cal_nhm_cnt( - void *p_dm_void -) +void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u16 base = 0; - - base = p_dm_odm->nhm_cnt_0 + p_dm_odm->nhm_cnt_1; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (base != 0) { - p_dm_odm->nhm_cnt_0 = ((p_dm_odm->nhm_cnt_0) << 8) / base; - p_dm_odm->nhm_cnt_1 = ((p_dm_odm->nhm_cnt_1) << 8) / base; - } - if ((p_dm_odm->nhm_cnt_0 - p_dm_odm->nhm_cnt_1) >= 100) - return true; /*clean environment*/ - else - return false; /*noisy environment*/ - -} - - -void -phydm_check_environment( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); - boolean is_clean_environment = false; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct rtl8192cd_priv *priv = p_dm_odm->priv; -#endif - - if (adaptivity->is_first_link == true) { - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) - p_dm_odm->adaptivity_flag = false; - else - p_dm_odm->adaptivity_flag = true; - - adaptivity->is_first_link = false; - return; - } else { - if (adaptivity->nhm_wait < 3) { /*Start enter NHM after 4 nhm_wait*/ - adaptivity->nhm_wait++; - phydm_nhm_counter_statistics(p_dm_odm); - return; - } else { - phydm_nhm_counter_statistics(p_dm_odm); - is_clean_environment = phydm_cal_nhm_cnt(p_dm_odm); - if (is_clean_environment == true) { - p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_backup; /*adaptivity mode*/ - p_dm_odm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup; - - p_dm_odm->adaptivity_enable = true; - - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) - p_dm_odm->adaptivity_flag = false; - else - p_dm_odm->adaptivity_flag = true; -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - priv->pshare->rf_ft_var.is_clean_environment = true; + if (state == PHYDM_IGNORE_EDCCA) { + odm_set_mac_reg(dm, R_0x520, BIT(15), 1); /*@ignore EDCCA*/ +#if 0 + /*odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 0);*/ #endif - } else { - if (!adaptivity->acs_for_adaptivity) { - p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; /*mode2*/ - p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2; - - p_dm_odm->adaptivity_flag = false; - p_dm_odm->adaptivity_enable = false; - } -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - priv->pshare->rf_ft_var.is_clean_environment = false; + } else { /*@don't set MAC ignore EDCCA signal*/ + odm_set_mac_reg(dm, R_0x520, BIT(15), 0); /*@don't ignore EDCCA*/ +#if 0 + /*odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);*/ #endif - } - adaptivity->nhm_wait = 0; - adaptivity->is_first_link = true; - adaptivity->is_check = true; - } - } - - + PHYDM_DBG(dm, DBG_ADPTVTY, "EDCCA enable state = %d\n", state); } -void -phydm_search_pwdb_lower_bound( - void *p_dm_void -) +void phydm_search_pwdb_lower_bound(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); - u32 value32 = 0, reg_value32 = 0; - u8 cnt, try_count = 0; - u8 tx_edcca1 = 0, tx_edcca0 = 0; - boolean is_adjust = true; - s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32; - s8 diff; - u8 IGI = adaptivity->igi_base + 30 + (u8)p_dm_odm->th_l2h_ini - (u8)p_dm_odm->th_edcca_hl_diff; - - if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) - phydm_set_lna(p_dm_odm, phydm_disable_lna); - else { - phydm_set_trx_mux(p_dm_odm, phydm_standby_mode, phydm_standby_mode); - odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e); - } - - diff = igi_target - (s8)IGI; - th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + u32 value32 = 0, reg_value32 = 0; + u8 cnt = 0, try_count = 0; + u8 tx_edcca1 = 0; + boolean is_adjust = true; + s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32; + s8 diff = 0; + s8 IGI = adapt->igi_base + 30 + dm->th_l2h_ini - dm->th_edcca_hl_diff; + + if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | + ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) + halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE); + + diff = igi_target - IGI; + th_l2h_dmc = dm->th_l2h_ini + diff; if (th_l2h_dmc > 10) th_l2h_dmc = 10; - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; - phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; + phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc); ODM_delay_ms(30); while (is_adjust) { - - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/ - reg_value32 = phydm_get_bb_dbg_port_value(p_dm_odm); + /*@check CCA status*/ + /*set debug port to 0x0*/ + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) { + reg_value32 = phydm_get_bb_dbg_port_val(dm); while (reg_value32 & BIT(3) && try_count < 3) { ODM_delay_ms(3); try_count = try_count + 1; - reg_value32 = phydm_get_bb_dbg_port_value(p_dm_odm); + reg_value32 = phydm_get_bb_dbg_port_val(dm); } - phydm_release_bb_dbg_port(p_dm_odm); + phydm_release_bb_dbg_port(dm); try_count = 0; } + /*@count EDCCA signal = 1 times*/ for (cnt = 0; cnt < 20; cnt++) { - - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) { - value32 = phydm_get_bb_dbg_port_value(p_dm_odm); - phydm_release_bb_dbg_port(p_dm_odm); + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, + adapt->adaptivity_dbg_port)) { + value32 = phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); } - if (value32 & BIT(30) && (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))) + if (value32 & BIT(30) && dm->support_ic_type & + (ODM_RTL8723B | ODM_RTL8188E)) tx_edcca1 = tx_edcca1 + 1; else if (value32 & BIT(29)) tx_edcca1 = tx_edcca1 + 1; - else - tx_edcca0 = tx_edcca0 + 1; } if (tx_edcca1 > 1) { @@ -546,595 +259,546 @@ phydm_search_pwdb_lower_bound( th_l2h_dmc = th_l2h_dmc + 1; if (th_l2h_dmc > 10) th_l2h_dmc = 10; - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; - - phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); - if (th_l2h_dmc == 10) { - is_adjust = false; - adaptivity->h2l_lb = th_h2l_dmc; - adaptivity->l2h_lb = th_l2h_dmc; - p_dm_odm->adaptivity_igi_upper = IGI; - } + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; + phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc); tx_edcca1 = 0; - tx_edcca0 = 0; + if (th_l2h_dmc == 10) + is_adjust = false; } else { is_adjust = false; - adaptivity->h2l_lb = th_h2l_dmc; - adaptivity->l2h_lb = th_l2h_dmc; - p_dm_odm->adaptivity_igi_upper = IGI; - tx_edcca1 = 0; - tx_edcca0 = 0; } } - p_dm_odm->adaptivity_igi_upper = p_dm_odm->adaptivity_igi_upper - p_dm_odm->dc_backoff; - adaptivity->h2l_lb = adaptivity->h2l_lb + p_dm_odm->dc_backoff; - adaptivity->l2h_lb = adaptivity->l2h_lb + p_dm_odm->dc_backoff; + adapt->adapt_igi_up = IGI - ADAPT_DC_BACKOFF; + adapt->h2l_lb = th_h2l_dmc + ADAPT_DC_BACKOFF; + adapt->l2h_lb = th_l2h_dmc + ADAPT_DC_BACKOFF; - if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) - phydm_set_lna(p_dm_odm, phydm_enable_lna); - else { - phydm_set_trx_mux(p_dm_odm, phydm_tx_mode, phydm_rx_mode); - odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE); - } + if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | + ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) + halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE); - phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); /*resume to no link state*/ + phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/ } boolean -phydm_re_search_condition( - void *p_dm_void -) +phydm_re_search_condition(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - /*struct _ADAPTIVITY_STATISTICS* adaptivity = (struct _ADAPTIVITY_STATISTICS*)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);*/ - u8 adaptivity_igi_upper; - u8 count = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; + u8 adaptivity_igi_upper = adaptivity->adapt_igi_up + ADAPT_DC_BACKOFF; /*s8 TH_L2H_dmc, IGI_target = 0x32;*/ /*s8 diff;*/ - adaptivity_igi_upper = p_dm_odm->adaptivity_igi_upper + p_dm_odm->dc_backoff; - /*TH_L2H_dmc = 10;*/ - /*diff = TH_L2H_dmc - p_dm_odm->TH_L2H_ini;*/ - /*lowest_IGI_upper = IGI_target - diff;*/ + /*@diff = TH_L2H_dmc - dm->TH_L2H_ini;*/ + /*@lowest_IGI_upper = IGI_target - diff;*/ + /*@if ((adaptivity_igi_upper - lowest_IGI_upper) <= 5)*/ - /*if ((adaptivity_igi_upper - lowest_IGI_upper) <= 5)*/ - if (adaptivity_igi_upper <= 0x26 && count < 3) { - count = count + 1; + if (adaptivity_igi_upper <= 0x26) return true; - } else return false; +} +void phydm_set_l2h_th_ini(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & + (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) + dm->th_l2h_ini = 0xf2; + else + dm->th_l2h_ini = 0xef; + } else { + dm->th_l2h_ini = 0xf5; + } } -void -phydm_adaptivity_info_init( - void *p_dm_void, - enum phydm_adapinfo_e cmn_info, - u32 value -) +void phydm_set_forgetting_factor(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct dm_struct *dm = (struct dm_struct *)dm_void; - switch (cmn_info) { - case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE: - p_dm_odm->carrier_sense_enable = (boolean)value; - break; + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) + odm_set_bb_reg(dm, R_0x8a0, BIT(1) | BIT(0), 0); + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + odm_set_bb_reg(dm, R_0x83c, BIT(31) | BIT(30) | BIT(29), 0x7); +} - case PHYDM_ADAPINFO_DCBACKOFF: - p_dm_odm->dc_backoff = (u8)value; - break; +void phydm_set_pwdb_mode(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ability & ODM_BB_ADAPTIVITY) { + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x1); + else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x1); + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x0); + } else { + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x0); + else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x0); + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x2); + } +} - case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY: - adaptivity->dynamic_link_adaptivity = (boolean)value; - break; +void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; + u32 used = *_used; + u32 out_len = *_out_len; + u32 dm_value[10] = {0}; + u8 i = 0, input_idx = 0; + u32 reg_value32 = 0; + s8 h2l_diff = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + if (dm_value[0] == PHYDM_ADAPT_DEBUG) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Adaptivity Debug Mode ===>\n"); + adaptivity->debug_mode = true; + dm->th_l2h_ini = (s8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "th_l2h_ini = %d\n", dm->th_l2h_ini); + } else if (dm_value[0] == PHYDM_ADAPT_RESUME) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "===> Adaptivity Resume\n"); + adaptivity->debug_mode = false; + dm->th_l2h_ini = adaptivity->th_l2h_ini_backup; + } else if (dm_value[0] == PHYDM_EDCCA_TH_PAUSE) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "EDCCA Threshold Pause\n"); + adaptivity->edcca_en = false; + } else if (dm_value[0] == PHYDM_EDCCA_RESUME) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "EDCCA Resume\n"); + adaptivity->edcca_en = true; + } else if (dm_value[0] == PHYDM_ADAPT_MSG) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "debug_mode = %s, th_l2h_ini = %d\n", + (adaptivity->debug_mode ? "TRUE" : "FALSE"), + dm->th_l2h_ini); + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + reg_value32 = odm_get_bb_reg(dm, R_0x84c, MASKDWORD); + h2l_diff = (s8)((0x00ff0000 & reg_value32) >> 16) - + (s8)((0xff000000 & reg_value32) >> 24); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + reg_value32 = odm_get_bb_reg(dm, R_0xc4c, MASKDWORD); + h2l_diff = (s8)(0x000000ff & reg_value32) - + (s8)((0x00ff0000 & reg_value32) >> 16); + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg_value32 = odm_get_bb_reg(dm, R_0x8a4, MASKDWORD); + h2l_diff = (s8)(0x000000ff & reg_value32) - + (s8)((0x0000ff00 & reg_value32) >> 8); + } + + if (h2l_diff == 7) + PDM_SNPF(out_len, used, output + used, out_len - used, + "adaptivity enable\n"); + else + PDM_SNPF(out_len, used, output + used, out_len - used, + "adaptivity disable\n"); + } + *_used = used; + *_out_len = out_len; +} + +void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (val_len != 2) { + PHYDM_DBG(dm, ODM_COMP_API, + "[Error][adaptivity]Need val_len = 2\n"); + return; + } + phydm_set_edcca_threshold(dm, (s8)val_buf[1], (s8)val_buf[0]); +} + +#endif +void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI) +{ +#ifdef PHYDM_SUPPORT_ADAPTIVITY + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; + s8 th_l2h_dmc = 0, th_h2l_dmc = 0; + s8 diff = 0, igi_target = 0x32; + + if (dm->support_ability & ODM_BB_ADAPTIVITY) { + if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) { + if (adaptivity->adajust_igi_level > IGI) + diff = adaptivity->adajust_igi_level - IGI; + th_l2h_dmc = dm->th_l2h_ini - diff + igi_target; + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; + } else { + diff = igi_target - (s8)IGI; + th_l2h_dmc = dm->th_l2h_ini + diff; + if (th_l2h_dmc > 10) + th_l2h_dmc = 10; + + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; + + /*replace lower bound to prevent EDCCA always equal 1*/ + if (th_h2l_dmc < adaptivity->h2l_lb) + th_h2l_dmc = adaptivity->h2l_lb; + if (th_l2h_dmc < adaptivity->l2h_lb) + th_l2h_dmc = adaptivity->l2h_lb; + } + + PHYDM_DBG(dm, DBG_ADPTVTY, + "API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", + IGI, th_l2h_dmc, th_h2l_dmc); + + phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc); + } +#endif +} + +void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info, + u32 value) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; + + switch (cmn_info) { + case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE: + dm->carrier_sense_enable = (boolean)value; + break; case PHYDM_ADAPINFO_TH_L2H_INI: - p_dm_odm->th_l2h_ini = (s8)value; + dm->th_l2h_ini = (s8)value; break; - case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF: - p_dm_odm->th_edcca_hl_diff = (s8)value; + dm->th_edcca_hl_diff = (s8)value; break; - case PHYDM_ADAPINFO_AP_NUM_TH: adaptivity->ap_num_th = (u8)value; break; - default: break; - } - } +void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info, + u32 value) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + /*This init variable may be changed in run time.*/ + switch (cmn_info) { + case PHYDM_ADAPINFO_DOMAIN_CODE_2G: + adapt->regulation_2g = (u8)value; + break; + case PHYDM_ADAPINFO_DOMAIN_CODE_5G: + adapt->regulation_5g = (u8)value; + break; + default: + break; + } +} -void -phydm_adaptivity_init( - void *p_dm_void -) +void phydm_adaptivity_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); - s8 igi_target = 0x32; - /*struct _dynamic_initial_gain_threshold_* p_dm_dig_table = &p_dm_odm->dm_dig_table;*/ +#ifdef PHYDM_SUPPORT_ADAPTIVITY + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) - if (p_dm_odm->carrier_sense_enable == false) { - if (p_dm_odm->th_l2h_ini == 0) - phydm_set_l2h_th_ini(p_dm_odm); - } else - p_dm_odm->th_l2h_ini = 0xa; + if (!dm->carrier_sense_enable) { + if (dm->th_l2h_ini == 0) + phydm_set_l2h_th_ini(dm); + } else { + dm->th_l2h_ini = 0xa; + } - if (p_dm_odm->th_edcca_hl_diff == 0) - p_dm_odm->th_edcca_hl_diff = 7; + if (dm->th_edcca_hl_diff == 0) + dm->th_edcca_hl_diff = 7; #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - if (p_dm_odm->wifi_test == true || p_dm_odm->mp_mode == true) + if (dm->wifi_test || *dm->mp_mode) #else - if ((p_dm_odm->wifi_test & RT_WIFI_LOGO) == true) + if (dm->wifi_test & RT_WIFI_LOGO) /*@AP side use mib control*/ #endif - p_dm_odm->edcca_enable = false; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/ + /*@even no adaptivity, we still enable EDCCA*/ + adaptivity->edcca_en = false; else - p_dm_odm->edcca_enable = true; + adaptivity->edcca_en = true; #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct rtl8192cd_priv *priv = p_dm_odm->priv; - - if (p_dm_odm->carrier_sense_enable) { - p_dm_odm->th_l2h_ini = 0xa; - p_dm_odm->th_edcca_hl_diff = 7; + if (dm->carrier_sense_enable) { + dm->th_l2h_ini = 0xa; + dm->th_edcca_hl_diff = 7; } else { - p_dm_odm->th_l2h_ini = p_dm_odm->TH_L2H_default; /*set by mib*/ - p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_default; + dm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/ + dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default; } - if (priv->pshare->rf_ft_var.adaptivity_enable == 3) - adaptivity->acs_for_adaptivity = true; - else - adaptivity->acs_for_adaptivity = false; - - if (priv->pshare->rf_ft_var.adaptivity_enable == 2) - adaptivity->dynamic_link_adaptivity = true; - else - adaptivity->dynamic_link_adaptivity = false; - - priv->pshare->rf_ft_var.is_clean_environment = false; - + adaptivity->edcca_en = true; #endif - p_dm_odm->adaptivity_igi_upper = 0; - p_dm_odm->adaptivity_enable = false; /*use this flag to decide enable or disable*/ - - p_dm_odm->th_l2h_ini_mode2 = 20; - p_dm_odm->th_edcca_hl_diff_mode2 = 8; - adaptivity->th_l2h_ini_backup = p_dm_odm->th_l2h_ini; - adaptivity->th_edcca_hl_diff_backup = p_dm_odm->th_edcca_hl_diff; - + adaptivity->adapt_igi_up = 0; + adaptivity->is_adapt_en = false; /*@decide enable or not*/ + adaptivity->th_l2h_ini_mode2 = 20; + adaptivity->th_edcca_hl_diff_mode2 = 8; + adaptivity->debug_mode = false; + adaptivity->th_l2h_ini_backup = dm->th_l2h_ini; + adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff; adaptivity->igi_base = 0x32; adaptivity->igi_target = 0x1c; adaptivity->h2l_lb = 0; adaptivity->l2h_lb = 0; - adaptivity->nhm_wait = 0; - adaptivity->is_check = false; - adaptivity->is_first_link = true; adaptivity->adajust_igi_level = 0; - adaptivity->is_stop_edcca = false; - adaptivity->backup_h2l = 0; - adaptivity->backup_l2h = 0; - adaptivity->adaptivity_dbg_port = (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) ? 0x208 : 0x209; - - phydm_mac_edcca_state(p_dm_odm, phydm_dont_ignore_edcca); - - if (p_dm_odm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) { - /*odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT(12) | BIT11 | BIT10, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1); /*set to page B1*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_97F, BIT(27) | BIT26, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0); -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - if (priv->pshare->rf_ft_var.adaptivity_enable == 1) - odm_set_bb_reg(p_dm_odm, 0xce8, BIT(13), 0x1); /*0: mean, 1:max pwdB*/ -#endif - } else - odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_11N, BIT(21) | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ - } -#if (RTL8195A_SUPPORT == 0) - if (p_dm_odm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/ - /*odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DOWN_OPT, BIT(30) | BIT29 | BIT28, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT(29) | BIT28, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ - } + phydm_mac_edcca_state(dm, PHYDM_DONT_IGNORE_EDCCA); - if (!(p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) { - phydm_search_pwdb_lower_bound(p_dm_odm); - if (phydm_re_search_condition(p_dm_odm)) - phydm_search_pwdb_lower_bound(p_dm_odm); - } else - phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); /*resume to no link state*/ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + adaptivity->adaptivity_dbg_port = 0x000; + odm_set_bb_reg(dm, R_0x1d6c, BIT(0), 1); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + adaptivity->adaptivity_dbg_port = 0x208; + } else { + adaptivity->adaptivity_dbg_port = 0x209; + } + if (dm->support_ic_type & ODM_IC_11N_SERIES && + !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) { + /*@interfernce need > 2^x us, and then EDCCA will be 1*/ +#if 0 + /*odm_set_bb_reg(dm, 0x948, 0x1c00, 0x7);*/ #endif - /*forgetting factor setting*/ - phydm_set_forgetting_factor(p_dm_odm); + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) { + /*set to page B1*/ + odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x1); + /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + odm_set_bb_reg(dm, R_0xbc0, BIT(27) | BIT(26), 0x1); + odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x0); + } else { + /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + odm_set_bb_reg(dm, R_0xe24, BIT(21) | BIT(20), 0x1); + } + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES && + !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) { + /*@interfernce need > 2^x us, and then EDCCA will be 1*/ +#if 0 + /*odm_set_bb_reg(dm, 0x900, 0x70000000, 0x7);*/ +#endif + /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + odm_set_bb_reg(dm, R_0x944, BIT(29) | BIT(28), 0x1); + } - /*we need to consider PwdB upper bound for 8814 later IC*/ - adaptivity->adajust_igi_level = (u8)((p_dm_odm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/ + if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) { + phydm_search_pwdb_lower_bound(dm); + if (phydm_re_search_condition(dm)) + phydm_search_pwdb_lower_bound(dm); + } else { + /*resume to no link state*/ + phydm_set_edcca_threshold(dm, 0x7f, 0x7f); + } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("th_l2h_ini = 0x%x, th_edcca_hl_diff = 0x%x, adaptivity->adajust_igi_level = 0x%x\n", p_dm_odm->th_l2h_ini, p_dm_odm->th_edcca_hl_diff, adaptivity->adajust_igi_level)); + /*@forgetting factor setting*/ + phydm_set_forgetting_factor(dm); - /*Check this later on Windows*/ - /*phydm_set_edcca_threshold_api(p_dm_odm, p_dm_dig_table->cur_ig_value);*/ + /*pwdb mode setting with 0: mean, 1:max*/ + phydm_set_pwdb_mode(dm); +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + adaptivity->igi_up_bound_lmt_val = 180; +#else + adaptivity->igi_up_bound_lmt_val = 90; +#endif + adaptivity->igi_up_bound_lmt_cnt = 0; + adaptivity->igi_lmt_en = false; +#endif } - -void -phydm_adaptivity( - void *p_dm_void -) +void phydm_adaptivity(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 IGI = p_dm_dig_table->cur_ig_value; - s8 th_l2h_dmc, th_h2l_dmc; - s8 diff = 0, igi_target; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); +#ifdef PHYDM_SUPPORT_ADAPTIVITY + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 igi = dig_t->cur_ig_value; + s8 th_l2h_dmc = 0, th_h2l_dmc = 0; + s8 diff = 0, igi_target = 0x32; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - boolean is_fw_current_in_ps_mode = false; - u8 disable_ap_adapt_setting; + void *adapter = dm->adapter; + u32 is_fw_current_in_ps_mode = false; + u8 disable_ap_adapt_setting; - p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_FW_PSMODE_STATUS, (u8 *)(&is_fw_current_in_ps_mode)); + ((PADAPTER)adapter)->HalFunc.GetHwRegHandler(adapter, HW_VAR_FW_PSMODE_STATUS, (u8 *)(&is_fw_current_in_ps_mode)); - /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/ + /*@Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/ if (is_fw_current_in_ps_mode) return; #endif + if (dm->pause_ability & ODM_BB_ADAPTIVITY) { + PHYDM_DBG(dm, DBG_ADPTVTY, "Return: Pause ADPTVTY in LV=%d\n", + dm->pause_lv_table.lv_adapt); + return; + } - if ((p_dm_odm->edcca_enable == false) || (adaptivity->is_stop_edcca == true)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n")); + if (!adapt->edcca_en) { + PHYDM_DBG(dm, DBG_ADPTVTY, "Disable EDCCA!!!\n"); return; } - if (!(p_dm_odm->support_ability & ODM_BB_ADAPTIVITY)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n")); - p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; - p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2; + phydm_check_adaptivity(dm); /*@Check adaptivity enable*/ + /*@Limit IGI upper bound for adaptivity*/ + if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) + phydm_dig_up_bound_lmt_en(dm); + + if (!(dm->support_ability & ODM_BB_ADAPTIVITY) && + !adapt->debug_mode) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "adaptivity disable, enable EDCCA mode!!!\n"); + dm->th_l2h_ini = adapt->th_l2h_ini_mode2; + dm->th_edcca_hl_diff = adapt->th_edcca_hl_diff_mode2; } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - else { - disable_ap_adapt_setting = false; - if (p_dm_odm->p_soft_ap_mode != NULL) { - if (*(p_dm_odm->p_soft_ap_mode) != 0 && (p_dm_odm->soft_ap_special_setting & BIT(0))) - disable_ap_adapt_setting = true; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("p_dm_odm->soft_ap_special_setting = %x, *(p_dm_odm->p_soft_ap_mode) = %d, disable_ap_adapt_setting = %d\n", p_dm_odm->soft_ap_special_setting, *(p_dm_odm->p_soft_ap_mode), disable_ap_adapt_setting)); - } - if (phydm_check_channel_plan(p_dm_odm) || (p_dm_odm->ap_total_num > adaptivity->ap_num_th) || disable_ap_adapt_setting) { - p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; - p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2; + else if (!adapt->debug_mode) { + if (!adapt->is_adapt_en) { + dm->th_l2h_ini = adapt->th_l2h_ini_mode2; + dm->th_edcca_hl_diff = adapt->th_edcca_hl_diff_mode2; } else { - p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_backup; - p_dm_odm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup; + dm->th_l2h_ini = adapt->th_l2h_ini_backup; + dm->th_edcca_hl_diff = adapt->th_edcca_hl_diff_backup; } } #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n")); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n", - adaptivity->igi_base, p_dm_odm->th_l2h_ini, p_dm_odm->th_edcca_hl_diff)); -#if (RTL8195A_SUPPORT == 0) - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - /*fix AC series when enable EDCCA hang issue*/ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(10), 1); /*ADC_mask disable*/ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(10), 0); /*ADC_mask enable*/ - } -#endif + PHYDM_DBG(dm, DBG_ADPTVTY, "odm_Adaptivity() =====>\n"); + PHYDM_DBG(dm, DBG_ADPTVTY, + "igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n", + adapt->igi_base, dm->th_l2h_ini, dm->th_edcca_hl_diff); - igi_target = adaptivity->igi_base; - adaptivity->igi_target = (u8) igi_target; + if (dm->support_ic_type & ODM_RTL8812) { + /*@fix AC series when enable EDCCA hang issue*/ + odm_set_bb_reg(dm, R_0x800, BIT(10), 1); /*@ADC_mask disable*/ + odm_set_bb_reg(dm, R_0x800, BIT(10), 0); /*@ADC_mask enable*/ + } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d, acs_for_adaptivity = %d\n", - (*p_dm_odm->p_band_width == ODM_BW80M) ? "80M" : ((*p_dm_odm->p_band_width == ODM_BW40M) ? "40M" : "20M"), igi_target, adaptivity->dynamic_link_adaptivity, adaptivity->acs_for_adaptivity)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, adaptivity->adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n", - p_dm_odm->rssi_min, adaptivity->adajust_igi_level, p_dm_odm->adaptivity_flag, p_dm_odm->adaptivity_enable)); + igi_target = adapt->igi_base; + adapt->igi_target = (u8)igi_target; + /*we need to consider PwdB upper bound for 8814 later IC*/ + adapt->adajust_igi_level = (u8)(dm->th_l2h_ini + igi_target - + PWDB_UPPER_BOUND + DFIR_LOSS); - if ((adaptivity->dynamic_link_adaptivity == true) && (!p_dm_odm->is_linked) && (p_dm_odm->adaptivity_enable == false)) { - phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n")); - return; - } + PHYDM_DBG(dm, DBG_ADPTVTY, + "adajust_igi_level= 0x%x, is_adapt_en = %d\n", + adapt->adajust_igi_level, adapt->is_adapt_en); - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { - if ((adaptivity->adajust_igi_level > IGI) && (p_dm_odm->adaptivity_enable == true)) - diff = adaptivity->adajust_igi_level - IGI; + if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) { + if (adapt->adajust_igi_level > igi && adapt->is_adapt_en) + diff = adapt->adajust_igi_level - igi; + else if (!adapt->is_adapt_en) + diff = 0x3e - igi; - th_l2h_dmc = p_dm_odm->th_l2h_ini - diff + igi_target; - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; - } -#if (RTL8195A_SUPPORT == 0) - else { - diff = igi_target - (s8)IGI; - th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; - if (th_l2h_dmc > 10 && (p_dm_odm->adaptivity_enable == true)) + th_l2h_dmc = dm->th_l2h_ini - diff + igi_target; + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; + } else { + diff = igi_target - (s8)igi; + th_l2h_dmc = dm->th_l2h_ini + diff; + if (th_l2h_dmc > 10 && adapt->is_adapt_en) th_l2h_dmc = 10; - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff; /*replace lower bound to prevent EDCCA always equal 1*/ - if (th_h2l_dmc < adaptivity->h2l_lb) - th_h2l_dmc = adaptivity->h2l_lb; - if (th_l2h_dmc < adaptivity->l2h_lb) - th_l2h_dmc = adaptivity->l2h_lb; + if (th_h2l_dmc < adapt->h2l_lb) + th_h2l_dmc = adapt->h2l_lb; + if (th_l2h_dmc < adapt->l2h_lb) + th_l2h_dmc = adapt->l2h_lb; } -#endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI, th_l2h_dmc, th_h2l_dmc)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", p_dm_odm->adaptivity_igi_upper, adaptivity->h2l_lb, adaptivity->l2h_lb)); - phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); - - if (p_dm_odm->adaptivity_enable == true) - odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 1); + adapt->th_l2h = th_l2h_dmc; + adapt->th_h2l = th_h2l_dmc; + PHYDM_DBG(dm, DBG_ADPTVTY, + "IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", igi, + th_l2h_dmc, th_h2l_dmc); + PHYDM_DBG(dm, DBG_ADPTVTY, + "adapt_igi_up=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", + adapt->adapt_igi_up, adapt->h2l_lb, + adapt->l2h_lb); + PHYDM_DBG(dm, DBG_ADPTVTY, "debug_mode = %d\n", adapt->debug_mode); + phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc); + + if (adapt->is_adapt_en) + odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1); return; +#endif } - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -void -phydm_adaptivity_bsod( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &(p_adapter->MgntInfo); - u8 count = 0; - u32 u4_value; - - /* - 1. turn off RF (TRX Mux in standby mode) - 2. H2C mac id drop - 3. ignore EDCCA - 4. wait for clear FIFO - 5. don't ignore EDCCA - 6. turn on RF (TRX Mux in TRx mdoe) - 7. H2C mac id resume - */ - - RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n")); - - p_adapter->dropPktByMacIdCnt++; - p_mgnt_info->bDropPktInProgress = true; - - p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_MAX_Q_PAGE_NUM, (u8 *)(&u4_value)); - RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page number = 0x%08x\n", u4_value)); - p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_AVBL_Q_PAGE_NUM, (u8 *)(&u4_value)); - RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page number = 0x%08x\n", u4_value)); - - /*Standby mode*/ - phydm_set_trx_mux(p_dm_odm, phydm_standby_mode, phydm_standby_mode); - odm_write_dig(p_dm_odm, 0x20); - - /*H2C mac id drop*/ - MacIdIndicateDisconnect(p_adapter); - - /*Ignore EDCCA*/ - phydm_mac_edcca_state(p_dm_odm, phydm_ignore_edcca); - - delay_ms(50); - count = 5; - - /*Resume EDCCA*/ - phydm_mac_edcca_state(p_dm_odm, phydm_dont_ignore_edcca); - - /*Turn on TRx mode*/ - phydm_set_trx_mux(p_dm_odm, phydm_tx_mode, phydm_rx_mode); - odm_write_dig(p_dm_odm, 0x20); - - /*Resume H2C macid*/ - MacIdRecoverMediaStatus(p_adapter); - - p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_AVBL_Q_PAGE_NUM, (u8 *)(&u4_value)); - RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page number = 0x%08x\n", u4_value)); - - p_mgnt_info->bDropPktInProgress = false; - RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10)); - -} - -#endif - -/*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/ -void -phydm_pause_edcca( - void *p_dm_void, - boolean is_pasue_edcca -) +/*This API is for solving USB can't Tx due to USB3.0 interference in 2.4G*/ +void phydm_pause_edcca(void *dm_void, boolean is_pasue_edcca) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 IGI = p_dm_dig_table->cur_ig_value; - s8 diff = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; if (is_pasue_edcca) { - adaptivity->is_stop_edcca = true; - - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { - if (adaptivity->adajust_igi_level > IGI) - diff = adaptivity->adajust_igi_level - IGI; - - adaptivity->backup_l2h = p_dm_odm->th_l2h_ini - diff + adaptivity->igi_target; - adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm_odm->th_edcca_hl_diff; - } -#if (RTL8195A_SUPPORT == 0) - else { - diff = adaptivity->igi_target - (s8)IGI; - adaptivity->backup_l2h = p_dm_odm->th_l2h_ini + diff; - if (adaptivity->backup_l2h > 10) - adaptivity->backup_l2h = 10; - - adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm_odm->th_edcca_hl_diff; - - /*replace lower bound to prevent EDCCA always equal 1*/ - if (adaptivity->backup_h2l < adaptivity->h2l_lb) - adaptivity->backup_h2l = adaptivity->h2l_lb; - if (adaptivity->backup_l2h < adaptivity->l2h_lb) - adaptivity->backup_l2h = adaptivity->l2h_lb; - } -#endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI)); - - /*Disable EDCCA*/ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (odm_is_work_item_scheduled(&(adaptivity->phydm_pause_edcca_work_item)) == false) - odm_schedule_work_item(&(adaptivity->phydm_pause_edcca_work_item)); -#else - phydm_pause_edcca_work_item_callback(p_dm_odm); -#endif + dm->pause_ability |= ODM_BB_ADAPTIVITY; + PHYDM_DBG(dm, DBG_ADPTVTY, "pauseEDCCA\n"); + /*@Disable EDCCA*/ + if (!odm_is_work_item_scheduled(&adapt->phydm_pause_edcca_work_item)) + odm_schedule_work_item(&adapt->phydm_pause_edcca_work_item); } else { - - adaptivity->is_stop_edcca = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI)); + dm->pause_ability &= ~ODM_BB_ADAPTIVITY; + PHYDM_DBG(dm, DBG_ADPTVTY, + "resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x\n", + adapt->th_l2h, adapt->th_h2l); /*Resume EDCCA*/ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (odm_is_work_item_scheduled(&(adaptivity->phydm_resume_edcca_work_item)) == false) - odm_schedule_work_item(&(adaptivity->phydm_resume_edcca_work_item)); -#else - phydm_resume_edcca_work_item_callback(p_dm_odm); -#endif - + if (!odm_is_work_item_scheduled(&adapt->phydm_resume_edcca_work_item)) + odm_schedule_work_item(&adapt->phydm_resume_edcca_work_item); } - } - -void -phydm_pause_edcca_work_item_callback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter -#else - void *p_dm_void -#endif -) +void phydm_pause_edcca_work_item_callback(void *adapter) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; -#else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#endif - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16)); -#if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)(0x7f | 0x7f << 8)); -#endif - -} - -void -phydm_resume_edcca_work_item_callback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter -#else - void *p_dm_void -#endif -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; -#else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#endif - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 16)); -#if (RTL8195A_SUPPORT == 0) - else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 8)); -#endif - -} - - -void -phydm_set_edcca_threshold_api( - void *p_dm_void, - u8 IGI -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); - s8 th_l2h_dmc, th_h2l_dmc; - s8 diff = 0, igi_target = 0x32; - - if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) { - if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { - if (adaptivity->adajust_igi_level > IGI) - diff = adaptivity->adajust_igi_level - IGI; - - th_l2h_dmc = p_dm_odm->th_l2h_ini - diff + igi_target; - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; - } -#if (RTL8195A_SUPPORT == 0) - else { - diff = igi_target - (s8)IGI; - th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; - if (th_l2h_dmc > 10) - th_l2h_dmc = 10; - - th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; - - /*replace lower bound to prevent EDCCA always equal 1*/ - if (th_h2l_dmc < adaptivity->h2l_lb) - th_h2l_dmc = adaptivity->h2l_lb; - if (th_l2h_dmc < adaptivity->l2h_lb) - th_l2h_dmc = adaptivity->l2h_lb; - } -#endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI, th_l2h_dmc, th_h2l_dmc)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", p_dm_odm->adaptivity_igi_upper, adaptivity->h2l_lb, adaptivity->l2h_lb)); - - phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, 0x7f); + odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, 0x7f); + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x8a4, MASKLWORD, 0x7f7f); } } -void -phydm_set_l2h_th_ini( - void *p_dm_void -) +void phydm_resume_edcca_work_item_callback(void *adapter) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) - p_dm_odm->th_l2h_ini = 0xf2; - else - p_dm_odm->th_l2h_ini = 0xef; - } else - p_dm_odm->th_l2h_ini = 0xf5; -} + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; -void -phydm_set_forgetting_factor( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, (u8)adapt->th_l2h); + odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, (u8)adapt->th_h2l); + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x8a4, MASKBYTE0, (u8)adapt->th_l2h); + odm_set_bb_reg(dm, R_0x8a4, MASKBYTE1, (u8)adapt->th_h2l); + } - if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) - odm_set_bb_reg(p_dm_odm, 0x8a0, BIT(1) | BIT(0), 0); } - +#endif diff --git a/hal/phydm/phydm_adaptivity.h b/hal/phydm/phydm_adaptivity.h index 2db6865..23f9e8b 100644 --- a/hal/phydm/phydm_adaptivity.h +++ b/hal/phydm/phydm_adaptivity.h @@ -1,7 +1,6 @@ - /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -9,223 +8,127 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ - -#ifndef __PHYDMADAPTIVITY_H__ -#define __PHYDMADAPTIVITY_H__ - -#define ADAPTIVITY_VERSION "9.5.2" /*20170420 changed by Kevin, change th_l2h_ini setting for 5G: v2.1.0*/ - -#define pwdb_upper_bound 7 -#define dfir_loss 7 - + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMADAPTIVITY_H__ +#define __PHYDMADAPTIVITY_H__ + +#define ADAPTIVITY_VERSION "9.5.20" /*@20180306 changed by Kevin, + *remove phydm lna set and use halrf part + */ + +#define PWDB_UPPER_BOUND 7 +#define DFIR_LOSS 7 +#define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\ + ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812) + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) + #define ADAPT_DC_BACKOFF 2 +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #define ADAPT_DC_BACKOFF 4 +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + #define ADAPT_DC_BACKOFF 0 +#endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) enum phydm_regulation_type { - REGULATION_FCC = 0, - REGULATION_MKK = 1, - REGULATION_ETSI = 2, - REGULATION_WW = 3, - - MAX_REGULATION_NUM = 4 + REGULATION_FCC = 0, + REGULATION_MKK = 1, + REGULATION_ETSI = 2, + REGULATION_WW = 3, + MAX_REGULATION_NUM = 4 }; #endif -enum phydm_adapinfo_e { +enum phydm_adapinfo { PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0, - PHYDM_ADAPINFO_DCBACKOFF, - PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, PHYDM_ADAPINFO_TH_L2H_INI, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, - PHYDM_ADAPINFO_AP_NUM_TH - -}; - - - -enum phydm_set_lna { - phydm_disable_lna = 0, - phydm_enable_lna = 1, + PHYDM_ADAPINFO_AP_NUM_TH, + PHYDM_ADAPINFO_DOMAIN_CODE_2G, + PHYDM_ADAPINFO_DOMAIN_CODE_5G }; - -enum phydm_trx_mux_type { - phydm_shutdown = 0, - phydm_standby_mode = 1, - phydm_tx_mode = 2, - phydm_rx_mode = 3 +enum phydm_mac_edcca_type { + PHYDM_IGNORE_EDCCA = 0, + PHYDM_DONT_IGNORE_EDCCA = 1 }; -enum phydm_mac_edcca_type { - phydm_ignore_edcca = 0, - phydm_dont_ignore_edcca = 1 +enum phydm_adaptivity_mode { + PHYDM_ADAPT_MSG = 0, + PHYDM_ADAPT_DEBUG = 1, + PHYDM_ADAPT_RESUME = 2, + PHYDM_EDCCA_TH_PAUSE = 3, + PHYDM_EDCCA_RESUME = 4 }; -struct _ADAPTIVITY_STATISTICS { +struct phydm_adaptivity_struct { s8 th_l2h_ini_backup; s8 th_edcca_hl_diff_backup; s8 igi_base; u8 igi_target; - u8 nhm_wait; s8 h2l_lb; s8 l2h_lb; - boolean is_first_link; - boolean is_check; - boolean dynamic_link_adaptivity; u8 ap_num_th; u8 adajust_igi_level; - boolean acs_for_adaptivity; - s8 backup_l2h; - s8 backup_h2l; - boolean is_stop_edcca; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_WORK_ITEM phydm_pause_edcca_work_item; - RT_WORK_ITEM phydm_resume_edcca_work_item; + RT_WORK_ITEM phydm_pause_edcca_work_item; + RT_WORK_ITEM phydm_resume_edcca_work_item; #endif u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/ + u8 debug_mode; + u16 igi_up_bound_lmt_cnt; /*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/ + u16 igi_up_bound_lmt_val; /*@max value of igi_up_bound_lmt_cnt*/ + boolean igi_lmt_en; + u8 adapt_igi_up; + s8 rvrt_val[2]; + s8 th_l2h; + s8 th_h2l; + u8 regulation_2g; + u8 regulation_5g; + boolean is_adapt_en; + boolean edcca_en; + s8 th_l2h_ini_mode2; + s8 th_edcca_hl_diff_mode2; }; -void -phydm_pause_edcca( - void *p_dm_void, - boolean is_pasue_edcca -); - -void -phydm_check_adaptivity( - void *p_dm_void -); - -void -phydm_check_environment( - void *p_dm_void -); - -void -phydm_nhm_counter_statistics_init( - void *p_dm_void -); - -void -phydm_nhm_counter_statistics( - void *p_dm_void -); - -void -phydm_nhm_counter_statistics_reset( - void *p_dm_void -); - -void -phydm_get_nhm_counter_statistics( - void *p_dm_void -); - -void -phydm_mac_edcca_state( - void *p_dm_void, - enum phydm_mac_edcca_type state -); - -void -phydm_set_edcca_threshold( - void *p_dm_void, - s8 H2L, - s8 L2H -); - -void -phydm_set_trx_mux( - void *p_dm_void, - enum phydm_trx_mux_type tx_mode, - enum phydm_trx_mux_type rx_mode -); - -boolean -phydm_cal_nhm_cnt( - void *p_dm_void -); - -void -phydm_search_pwdb_lower_bound( - void *p_dm_void -); - -void -phydm_adaptivity_info_init( - void *p_dm_void, - enum phydm_adapinfo_e cmn_info, - u32 value -); - -void -phydm_adaptivity_init( - void *p_dm_void -); - -void -phydm_adaptivity( - void *p_dm_void -); - -void -phydm_set_edcca_threshold_api( - void *p_dm_void, - u8 IGI -); +#ifdef PHYDM_SUPPORT_ADAPTIVITY +void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -phydm_disable_edcca( - void *p_dm_void -); +void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len); +#endif -void -phydm_dynamic_edcca( - void *p_dm_void -); +void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI); -void -phydm_adaptivity_bsod( - void *p_dm_void -); +void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info, + u32 value); -#endif +void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info, + u32 value); -void -phydm_pause_edcca_work_item_callback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter -#else - void *p_dm_void -#endif -); +void phydm_adaptivity_init(void *dm_void); -void -phydm_resume_edcca_work_item_callback( -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter -#else - void *p_dm_void -#endif -); +void phydm_adaptivity(void *dm_void); +void phydm_pause_edcca(void *dm_void, boolean is_pasue_edcca); -void -phydm_set_l2h_th_ini( - void *p_dm_void -); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_pause_edcca_work_item_callback(void *adapter); -void -phydm_set_forgetting_factor( - void *p_dm_void -); +void phydm_resume_edcca_work_item_callback(void *adapter); +#endif #endif diff --git a/hal/phydm/phydm_adc_sampling.c b/hal/phydm/phydm_adc_sampling.c index b9aeab1..3ac203b 100644 --- a/hal/phydm/phydm_adc_sampling.c +++ b/hal/phydm/phydm_adc_sampling.c @@ -1,262 +1,390 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + #include "mp_precomp.h" #include "phydm_precomp.h" +#if (PHYDM_LA_MODE_SUPPORT) + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - #if ((RTL8197F_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) - #include "rtl8197f/Hal8197FPhyReg.h" - #include "WlanHAL/HalMac88XX/halmac_reg2.h" - #else - #include "WlanHAL/HalHeader/HalComReg.h" - #endif +#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8192F_SUPPORT) +#include "rtl8197f/Hal8197FPhyReg.h" +#include "WlanHAL/HalMac88XX/halmac_reg2.h" +#else +#include "WlanHAL/HalHeader/HalComReg.h" #endif - -#if (PHYDM_LA_MODE_SUPPORT == 1) - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) #if WPP_SOFTWARE_TRACE - #include "phydm_adc_sampling.tmh" +#include "phydm_adc_sampling.tmh" #endif - #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) boolean -phydm_la_buffer_allocate( - void *p_dm_void -) +phydm_la_buffer_allocate(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _ADAPTER *adapter = p_dm_odm->adapter; - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); - boolean ret = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + #endif + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + boolean ret = true; - dbg_print("[LA mode BufferAllocate]\n"); + pr_debug("[LA mode BufferAllocate]\n"); - if (adc_smp_buf->length == 0) { + if (buf->length == 0) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (PlatformAllocateMemoryWithZero(adapter, (void **)& + buf->octet, + buf->buffer_size) != + RT_STATUS_SUCCESS) + ret = false; + #else + odm_allocate_memory(dm, (void **)&buf->octet, buf->buffer_size); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (PlatformAllocateMemoryWithZero(adapter, (void **)&(adc_smp_buf->octet), adc_smp_buf->buffer_size) != RT_STATUS_SUCCESS) { -#else - odm_allocate_memory(p_dm_odm, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size); - if (!adc_smp_buf->octet) { -#endif + if (!buf->octet) ret = false; - } else - adc_smp_buf->length = adc_smp_buf->buffer_size; - ret = true; + #endif + + if (ret) + buf->length = buf->buffer_size; } return ret; } #endif -void -phydm_la_get_tx_pkt_buf( - void *p_dm_void -) +void phydm_la_get_tx_pkt_buf(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); - u32 i = 0, value32, data_l = 0, data_h = 0; - u32 addr, finish_addr; - u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) - 1; /*end_addr = 0x3ffff;*/ - boolean is_round_up; - static u32 page = 0xFF; - u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + u32 i = 0, value32 = 0, data_l = 0, data_h = 0; + u32 addr = 0, finish_addr = 0; + boolean is_round_up = false; + static u32 page = 0xFF; + u32 smp_cnt = 0, smp_number = 10, addr_8byte = 0; + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #if (RTL8197F_SUPPORT || RTL8198F_SUPPORT) + u8 backup_dma = 0; + #endif + #endif - odm_memory_set(p_dm_odm, adc_smp_buf->octet, 0, adc_smp_buf->length); - odm_write_1byte(p_dm_odm, 0x0106, 0x69); + odm_memory_set(dm, buf->octet, 0, buf->length); + pr_debug("GetTxPktBuf\n"); - dbg_print("GetTxPktBuf\n"); + if (dm->support_ic_type & ODM_RTL8192F) { + value32 = odm_read_4byte(dm, 0x7F0); + is_round_up = (boolean)((value32 & BIT(31)) >> 31); + /*Reg7F0[30:15]: finish addr (unit: 8byte)*/ + finish_addr = (value32 & 0x7FFF8000) >> 15; + } else { + odm_write_1byte(dm, 0x0106, 0x69); + value32 = odm_read_4byte(dm, 0x7C0); + is_round_up = (boolean)((value32 & BIT(31)) >> 31); + /*Reg7C0[30:16]: finish addr (unit: 8byte)*/ + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C | + ODM_RTL8821C | ODM_RTL8814A | ODM_RTL8814B)) + finish_addr = (value32 & 0x7FFF0000) >> 16; + /*Reg7C0[30:15]: finish addr (unit: 8byte)*/ + else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8197F)) + finish_addr = (value32 & 0x7FFF8000) >> 15; + } - value32 = odm_read_4byte(p_dm_odm, 0x7c0); - is_round_up = (boolean)((value32 & BIT(31)) >> 31); - finish_addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/ + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #if (RTL8197F_SUPPORT || RTL8198F_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8198F)) { + pr_debug("98F GetTxPktBuf from iMEM\n"); + odm_set_bb_reg(dm, R_0x7c0, BIT(0), 0x0); + /*Stop DMA*/ + backup_dma = odm_get_mac_reg(dm, R_0x300, MASKLWORD); + odm_set_mac_reg(dm, R_0x300, 0x7fff, 0x7fff); + + /*@move LA mode content from IMEM to TxPktBuffer + Source : OCPBASE_IMEM 0x00000000 + Destination : OCPBASE_TXBUF 0x18780000 + Length : 64K*/ + GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv, + OCPBASE_IMEM, + OCPBASE_TXBUF, + 0x10000); + } + #endif + #endif + + pr_debug("start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((%d))\n", + buf->start_pos, buf->end_pos, buf->buffer_size); if (is_round_up) { + pr_debug("buf_start(%d)|----2---->|finish_addr(%d)|----1---->|buf_end(%d)\n", + buf->start_pos, finish_addr << 3, buf->end_pos); addr = (finish_addr + 1) << 3; - dbg_print("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n", is_round_up, finish_addr, value32); - smp_number = ((adc_smp_buf->buffer_size) >> 3); /*Byte to 64Byte*/ - } else { - addr = adc_smp_buf->start_pos; - + pr_debug("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0/0x7F0=((0x%x))\n", + is_round_up, finish_addr, value32); + /*@Byte to 8Byte (64bit)*/ + smp_number = (buf->buffer_size) >> 3; + } else { + pr_debug("buf_start(%d)|------->|finish_addr(%d) |buf_end(%d)\n", + buf->start_pos, finish_addr << 3, buf->end_pos); + addr = buf->start_pos; addr_8byte = addr >> 3; + if (addr_8byte > finish_addr) smp_number = addr_8byte - finish_addr; else smp_number = finish_addr - addr_8byte; - dbg_print("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", is_round_up, finish_addr, addr_8byte, smp_number); - + pr_debug("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", + is_round_up, finish_addr, addr_8byte, smp_number); } - /* - dbg_print("is_round_up = %d, finish_addr=0x%x, value32=0x%x\n", is_round_up, finish_addr, value32); - dbg_print("end_addr = %x, adc_smp_buf->start_pos = 0x%x, adc_smp_buf->buffer_size = 0x%x\n", end_addr, adc_smp_buf->start_pos, adc_smp_buf->buffer_size); - */ -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_stop(p_dm_odm->priv); -#endif + #if 0 + dbg_print("is_round_up = %d, finish_addr=0x%x, value32=0x%x\n", + is_round_up, finish_addr, value32); + dbg_print( + "end_addr = %x, buf->start_pos = 0x%x, buf->buffer_size = 0x%x\n", + end_addr, buf->start_pos, buf->buffer_size); + #endif - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) { /*64K byte*/ + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #if (RTL8197F_SUPPORT || RTL8198F_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8198F)) { + for (addr = 0x0; addr < buf->end_pos; addr += 8) {/*@64K byte*/ if ((addr & 0xfff) == 0) - odm_set_bb_reg(p_dm_odm, 0x0140, MASKLWORD, 0x780 + (addr >> 12)); - data_l = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff), MASKDWORD); - data_h = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD); - - dbg_print("%08x%08x\n", data_h, data_l); + odm_set_bb_reg(dm, R_0x0140, MASKLWORD, 0x780 + + (addr >> 12)); + data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff), + MASKDWORD); + data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + + 4, MASKDWORD); + + pr_debug("%08x%08x\n", data_h, data_l); } - } else { - while (addr != (finish_addr << 3)) { - if (page != (addr >> 12)) { - /*Reg140=0x780+(addr>>12), addr=0x30~0x3F, total 16 pages*/ - page = (addr >> 12); + } else + #endif + #endif + { + for (i = 0; smp_cnt < smp_number; smp_cnt++, i += 2) { + if (dm->support_ic_type & ODM_RTL8192F) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + indirect_access_sdram_8192f(dm->adapter, + TX_PACKET_BUFFER, + TRUE, + (u16)addr >> 3, 0, + &data_h, &data_l); + #else + odm_write_1byte(dm, R_0x0106, 0x69); + odm_set_bb_reg(dm, R_0x0140, MASKDWORD, addr >> 3); + data_l = odm_get_bb_reg(dm, R_0x0144, MASKDWORD); + data_h = odm_get_bb_reg(dm, R_0x0148, MASKDWORD); + odm_write_1byte(dm, R_0x0106, 0x0); + #endif + + } else { + if (page != (addr >> 12)) { + /* Reg140=0x780+(addr>>12), + * addr=0x30~0x3F, total 16 pages + */ + page = addr >> 12; + } + odm_set_bb_reg(dm, R_0x0140, MASKLWORD, 0x780 + + page); + + /*pDataL = 0x8000+(addr&0xfff);*/ + data_l = odm_get_bb_reg(dm, 0x8000 + (addr & + 0xfff), MASKDWORD); + data_h = odm_get_bb_reg(dm, 0x8000 + (addr & + 0xfff) + 4, MASKDWORD); } - odm_set_bb_reg(p_dm_odm, 0x0140, MASKLWORD, 0x780 + page); - - /*pDataL = 0x8000+(addr&0xfff);*/ - data_l = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff), MASKDWORD); - data_h = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - adc_smp_buf->octet[i] = data_h; - adc_smp_buf->octet[i + 1] = data_l; -#endif - -#if DBG - dbg_print("%08x%08x\n", data_h, data_l); -#else -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1])); -#endif -#endif - - i = i + 2; - - if ((addr + 8) >= end_addr) - addr = adc_smp_buf->start_pos; + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + buf->octet[i] = data_h; + buf->octet[i + 1] = data_l; + #endif + #if DBG /*WIN driver check build*/ + pr_debug("%08x%08x\n", data_h, data_l); + #else /*WIN driver free build*/ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, + ("%08x%08x\n", buf->octet[i], + buf->octet[i + 1])); + #endif + #endif + if ((addr + 8) > buf->end_pos) + addr = buf->start_pos; else addr = addr + 8; - - smp_cnt++; - if (smp_cnt >= (smp_number - 1)) - break; } - dbg_print("smp_cnt = ((%d))\n", smp_cnt); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("smp_cnt = ((%d))\n", smp_cnt)); -#endif - } + pr_debug("smp_cnt = ((%d))\n", smp_cnt); -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_resume(p_dm_odm->priv); -#endif + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, + ("smp_cnt = ((%d))\n", smp_cnt)); + #endif + } + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) + odm_set_mac_reg(dm, R_0x300, 0x7fff, backup_dma);/*Resume DMA*/ + #endif + #endif } -void -phydm_la_mode_set_mac_iq_dump( - void *p_dm_void -) +void phydm_la_mode_set_mac_iq_dump(void *dm_void, boolean en_fake_trig) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - u32 reg_value; - - odm_write_1byte(p_dm_odm, 0x7c0, 0); /*clear all 0x7c0*/ - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/ - - if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) { - - adc_smp->is_bb_trigger = 0; - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(2), 1); /*polling bit for MAC mode*/ - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(4) | BIT3, adc_smp->la_trigger_edge); /*trigger mode for MAC*/ - - dbg_print("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", adc_smp->la_mac_ref_mask, adc_smp->la_trig_sig_sel, adc_smp->la_dbg_port); - /*[Set MAC Debug Port]*/ - odm_set_mac_reg(p_dm_odm, 0xF4, BIT(16), 1); - odm_set_mac_reg(p_dm_odm, 0x38, 0xff0000, adc_smp->la_dbg_port); - odm_set_mac_reg(p_dm_odm, 0x7c4, MASKDWORD, adc_smp->la_mac_ref_mask); - odm_set_mac_reg(p_dm_odm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel); - + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + u32 reg_value = 0; + u32 reg1 = 0, reg2 = 0, reg3 = 0; + + if (dm->support_ic_type & ODM_RTL8192F) { + reg1 = 0x7f0; + reg2 = 0x7f4; + reg3 = 0x7f8; } else { + reg1 = 0x7c0; + reg2 = 0x7c4; + reg3 = 0x7c8; + } - adc_smp->is_bb_trigger = 1; - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(1), 1); /*polling bit for BB ADC mode*/ - - if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) { - - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(3), 1); /*polling bit for MAC trigger event*/ - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(7) | BIT(6), adc_smp->la_trig_sig_sel); + odm_write_1byte(dm, reg1, 0); /*@clear all reg1*/ + /*@Enable LA mode HW block*/ + odm_set_mac_reg(dm, reg1, BIT(0), 1); + + if (smp->la_trig_mode == PHYDM_MAC_TRIG) { + smp->is_bb_trigger = 0; + /*polling bit for MAC mode*/ + odm_set_mac_reg(dm, reg1, BIT(2), 1); + /*trigger mode for MAC*/ + odm_set_mac_reg(dm, reg1, BIT(4) | BIT(3), + smp->la_trigger_edge); + pr_debug("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", + smp->la_mac_mask_or_hdr_sel, smp->la_trig_sig_sel, + smp->la_dbg_port); + /*@[Set MAC Debug Port]*/ + odm_set_mac_reg(dm, R_0xf4, BIT(16), 1); + odm_set_mac_reg(dm, R_0x38, 0xff0000, smp->la_dbg_port); + odm_set_mac_reg(dm, reg2, MASKDWORD, + smp->la_mac_mask_or_hdr_sel); + odm_set_mac_reg(dm, reg3, MASKDWORD, smp->la_trig_sig_sel); - if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG) - odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(5), 1); /* manual trigger 0x7C0[5] = 0->1*/ + } else { + smp->is_bb_trigger = 1; + /*polling bit for BB ADC mode*/ + odm_set_mac_reg(dm, reg1, BIT(1), 1); + + if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) { + /*polling bit for MAC trigger event*/ + if (!en_fake_trig) + odm_set_mac_reg(dm, R_0x7c0, BIT(3), 1); + + odm_set_mac_reg(dm, reg1, BIT(7) | BIT(6), + smp->la_trig_sig_sel); + if (smp->la_trig_sig_sel == ADCSMP_TRIG_REG) + /* @manual trigger reg1[5] = 0->1*/ + odm_set_mac_reg(dm, reg1, BIT(5), 1); } } - reg_value = odm_get_bb_reg(p_dm_odm, 0x7c0, 0xff); - dbg_print("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value)); -#endif + reg_value = odm_get_bb_reg(dm, reg1, 0xff); + pr_debug("4. [Set MAC IQ dump] 0x%x[7:0] = ((0x%x))\n", reg1, + reg_value); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, + ("4. [Set MAC IQ dump] 0x%x[7:0] = ((0x%x))\n", reg1, + reg_value)); + #endif } -void -phydm_la_mode_set_dma_type( - void *p_dm_void, - u8 la_dma_type -) +void phydm_adc_smp_start(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + u8 tmp_u1b = 0; + u8 while_cnt = 0; + u8 target_polling_bit = 0; + boolean polling_ok = false; + boolean en_fake_trig = false; + + if (smp->la_dma_type >= 0 && smp->la_dma_type <= 5) + en_fake_trig = true; + + if (en_fake_trig) { + smp->is_fake_trig = true; + phydm_la_mode_bb_setting(dm, en_fake_trig); + } else { + smp->is_fake_trig = false; + phydm_la_mode_bb_setting(dm, en_fake_trig); + } - dbg_print("2. [LA mode DMA setting] Dma_type = ((%d))\n", la_dma_type); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("2. [LA mode DMA setting] Dma_type = ((%d))\n", la_dma_type)); -#endif + phydm_la_mode_set_trigger_time(dm, smp->la_trigger_time); - if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) - odm_set_bb_reg(p_dm_odm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/ - else - odm_set_bb_reg(p_dm_odm, odm_adc_trigger_jaguar2, 0xf00, la_dma_type); /*0x95C[11:8]*/ -} + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, R_0xd00, BIT(26), 0x1); + else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) + odm_set_bb_reg(dm, R_0x1eb4, BIT(23), 0x1); + else /*@for 8814A and 8822B?*/ + odm_write_1byte(dm, 0x8b4, 0x80); +#if 0 + /* odm_set_bb_reg(dm, R_0x8b4, BIT(7), 1); */ +#endif -void -phydm_adc_smp_start( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - u8 tmp_u1b; - u8 backup_DMA, while_cnt = 0; - u8 polling_ok = false, target_polling_bit; - - phydm_la_mode_bb_setting(p_dm_odm); - phydm_la_mode_set_dma_type(p_dm_odm, adc_smp->la_dma_type); - phydm_la_mode_set_trigger_time(p_dm_odm, adc_smp->la_trigger_time); - - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - odm_set_bb_reg(p_dm_odm, 0xd00, BIT(26), 0x1); - else { /*for 8814A and 8822B?*/ - odm_write_1byte(p_dm_odm, 0x8b4, 0x80); - /* odm_set_bb_reg(p_dm_odm, 0x8b4, BIT7, 1); */ - } + phydm_la_mode_set_mac_iq_dump(dm, en_fake_trig); - phydm_la_mode_set_mac_iq_dump(p_dm_odm); + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + watchdog_stop(dm->priv); + #endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_stop(p_dm_odm->priv); -#endif + if (en_fake_trig) { + ODM_delay_ms(100); + if (smp->la_trig_mode == PHYDM_ADC_BB_TRIG) { + smp->is_fake_trig = false; + phydm_la_mode_bb_setting(dm, en_fake_trig); + } + if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) { + if (dm->support_ic_type & ODM_RTL8192F) + odm_set_mac_reg(dm, 0x7f0, BIT(3), 1); + else + odm_set_mac_reg(dm, 0x7c0, BIT(3), 1); + } + } - target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2); - do { /*Polling time always use 100ms, when it exceed 2s, break while loop*/ - tmp_u1b = odm_read_1byte(p_dm_odm, 0x7c0); + target_polling_bit = (smp->is_bb_trigger) ? BIT(1) : BIT(2); + do { /*Polling time always use 100ms, when it exceed 2s, break loop*/ + if (dm->support_ic_type & ODM_RTL8192F) { + tmp_u1b = odm_read_1byte(dm, 0x7F0); + pr_debug("[%d], 0x7F0[7:0] = ((0x%x))\n", while_cnt, + tmp_u1b); + } else { + tmp_u1b = odm_read_1byte(dm, 0x7C0); + pr_debug("[%d], 0x7C0[7:0] = ((0x%x))\n", while_cnt, + tmp_u1b); + } - if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) { - dbg_print("[state Error] adc_smp_state != ADCSMP_STATE_SET\n"); + if (smp->adc_smp_state != ADCSMP_STATE_SET) { + pr_debug("[state Error] adc_smp_state != ADCSMP_STATE_SET\n"); break; } else if (tmp_u1b & target_polling_bit) { @@ -264,454 +392,584 @@ phydm_adc_smp_start( while_cnt = while_cnt + 1; continue; } else { - dbg_print("[LA Query OK] polling_bit=((0x%x))\n", target_polling_bit); + pr_debug("[LA Query OK] polling_bit=((0x%x))\n", + target_polling_bit); polling_ok = true; - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - odm_set_bb_reg(p_dm_odm, 0x7c0, BIT(0), 0x0); break; } } while (while_cnt < 20); -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - watchdog_resume(p_dm_odm->priv); -#if (RTL8197F_SUPPORT) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - /*Stop DMA*/ - backup_DMA = odm_get_mac_reg(p_dm_odm, 0x300, MASKLWORD); - odm_set_mac_reg(p_dm_odm, 0x300, 0x7fff, backup_DMA | 0x7fff); - - /*move LA mode content from IMEM to TxPktBuffer - Src : OCPBASE_IMEM 0x00000000 - Dest : OCPBASE_TXBUF 0x18780000 - Len : 64K*/ - GET_HAL_INTERFACE(p_dm_odm->priv)->init_ddma_handler(p_dm_odm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000); - } -#endif -#endif - - if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) { - + if (smp->adc_smp_state == ADCSMP_STATE_SET) { if (polling_ok) - phydm_la_get_tx_pkt_buf(p_dm_odm); + phydm_la_get_tx_pkt_buf(dm); else - dbg_print("[Polling timeout]\n"); + pr_debug("[Polling timeout]\n"); } -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - odm_set_mac_reg(p_dm_odm, 0x300, 0x7fff, backup_DMA); /*Resume DMA*/ -#endif + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + watchdog_resume(dm->priv); + #endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) - adc_smp->adc_smp_state = ADCSMP_STATE_QUERY; -#endif + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (smp->adc_smp_state == ADCSMP_STATE_SET) + smp->adc_smp_state = ADCSMP_STATE_QUERY; + #endif - dbg_print("[LA mode] LA_pattern_count = ((%d))\n", adc_smp->la_count); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("[LA mode] la_count = ((%d))\n", adc_smp->la_count)); -#endif + pr_debug("[LA mode] LA_pattern_count = ((%d))\n", smp->la_count); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, + ("[LA mode] la_count = ((%d))\n", smp->la_count)); + #endif + adc_smp_stop(dm); - adc_smp_stop(p_dm_odm); + if (smp->la_count == 0) { + pr_debug("LA Dump finished ---------->\n\n\n"); + phydm_release_bb_dbg_port(dm); - if (adc_smp->la_count == 0) { - dbg_print("LA Dump finished ---------->\n\n\n"); - phydm_release_bb_dbg_port(p_dm_odm); - - if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (p_dm_odm->cut_version >= ODM_CUT_B)) { - odm_set_bb_reg(p_dm_odm, 0x95c, BIT(23), 0); - } + if ((dm->support_ic_type & ODM_RTL8821C) && + dm->cut_version >= ODM_CUT_B) + odm_set_bb_reg(dm, R_0x95c, BIT(23), 0); } else { - adc_smp->la_count--; - dbg_print("LA Dump more ---------->\n\n\n"); - adc_smp_set(p_dm_odm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel, adc_smp->la_dma_type, adc_smp->la_trigger_time, 0); + smp->la_count--; + pr_debug("LA Dump more ---------->\n\n\n"); + adc_smp_set(dm, smp->la_trig_mode, smp->la_trig_sig_sel, + smp->la_dma_type, smp->la_trigger_time, 0); } - } #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -void -adc_smp_work_item_callback( - void *p_context -) +void adc_smp_work_item_callback(void *context) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + void *adapter = (void *)context; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct rt_adcsmp *smp = &dm->adcsmp; - dbg_print("[WorkItem Call back] LA_State=((%d))\n", adc_smp->adc_smp_state); - phydm_adc_smp_start(p_dm_odm); + pr_debug("[WorkItem Call back] LA_State=((%d))\n", smp->adc_smp_state); + phydm_adc_smp_start(dm); } #endif -void -adc_smp_set( - void *p_dm_void, - u8 trig_mode, - u32 trig_sig_sel, - u8 dma_data_sig_sel, - u32 trigger_time, - u16 polling_time -) +void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel, + u8 dma_data_sig_sel, u32 trig_time, u16 polling_time) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - boolean is_set_success = true; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean is_set_success = true; + struct rt_adcsmp *smp = &dm->adcsmp; - adc_smp->la_trig_mode = trig_mode; - adc_smp->la_trig_sig_sel = trig_sig_sel; - adc_smp->la_dma_type = dma_data_sig_sel; - adc_smp->la_trigger_time = trigger_time; + smp->la_trig_mode = trig_mode; + smp->la_trig_sig_sel = trig_sig_sel; + smp->la_dma_type = dma_data_sig_sel; + smp->la_trigger_time = trig_time; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE) + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (smp->adc_smp_state != ADCSMP_STATE_IDLE) is_set_success = false; - else if (adc_smp->adc_smp_buf.length == 0) - is_set_success = phydm_la_buffer_allocate(p_dm_odm); -#endif + else if (smp->adc_smp_buf.length == 0) + is_set_success = phydm_la_buffer_allocate(dm); + #endif if (is_set_success) { - adc_smp->adc_smp_state = ADCSMP_STATE_SET; + smp->adc_smp_state = ADCSMP_STATE_SET; - dbg_print("[LA Set Success] LA_State=((%d))\n", adc_smp->adc_smp_state); + pr_debug("[LA Set Success] LA_State=((%d))\n", + smp->adc_smp_state); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - dbg_print("ADCSmp_work_item_index = ((%d))\n", adc_smp->la_work_item_index); - if (adc_smp->la_work_item_index != 0) { - odm_schedule_work_item(&(adc_smp->adc_smp_work_item_1)); - adc_smp->la_work_item_index = 0; + pr_debug("ADCSmp_work_item_index = ((%d))\n", + smp->la_work_item_index); + if (smp->la_work_item_index != 0) { + odm_schedule_work_item(&smp->adc_smp_work_item_1); + smp->la_work_item_index = 0; } else { - odm_schedule_work_item(&(adc_smp->adc_smp_work_item)); - adc_smp->la_work_item_index = 1; + odm_schedule_work_item(&smp->adc_smp_work_item); + smp->la_work_item_index = 1; } -#else - phydm_adc_smp_start(p_dm_odm); -#endif - } else - dbg_print("[LA Set Fail] LA_State=((%d))\n", adc_smp->adc_smp_state); - - + #else + phydm_adc_smp_start(dm); + #endif + } else { + pr_debug("[LA Set Fail] LA_State=((%d))\n", smp->adc_smp_state); + } } #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) enum rt_status -adc_smp_query( - void *p_dm_void, - ULONG information_buffer_length, - void *information_buffer, - PULONG bytes_written -) +adc_smp_query(void *dm_void, ULONG info_buf_length, void *info_buf, + PULONG bytes_written) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - enum rt_status ret_status = RT_STATUS_SUCCESS; - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + enum rt_status ret_status = RT_STATUS_SUCCESS; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; - dbg_print("[%s] LA_State=((%d))", __func__, adc_smp->adc_smp_state); + pr_debug("[%s] LA_State=((%d))", __func__, smp->adc_smp_state); - if (information_buffer_length != adc_smp_buf->buffer_size) { + if (info_buf_length != buf->buffer_size) { *bytes_written = 0; ret_status = RT_STATUS_RESOURCE; - } else if (adc_smp_buf->length != adc_smp_buf->buffer_size) { + } else if (buf->length != buf->buffer_size) { *bytes_written = 0; ret_status = RT_STATUS_RESOURCE; - } else if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) { + } else if (smp->adc_smp_state != ADCSMP_STATE_QUERY) { *bytes_written = 0; ret_status = RT_STATUS_PENDING; } else { - odm_move_memory(p_dm_odm, information_buffer, adc_smp_buf->octet, adc_smp_buf->buffer_size); - *bytes_written = adc_smp_buf->buffer_size; + odm_move_memory(dm, info_buf, buf->octet, buf->buffer_size); + *bytes_written = buf->buffer_size; - adc_smp->adc_smp_state = ADCSMP_STATE_IDLE; + smp->adc_smp_state = ADCSMP_STATE_IDLE; } - dbg_print("Return status %d\n", ret_status); + pr_debug("Return status %d\n", ret_status); return ret_status; } #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) -void -adc_smp_query( - void *p_dm_void, - void *output, - u32 out_len, - u32 *pused -) +void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; u32 used = *pused; - u32 i; + u32 i = 0; +#if 0 /* struct timespec t; */ /* rtw_get_current_timespec(&t); */ +#endif - dbg_print("%s adc_smp_state %d", __func__, adc_smp->adc_smp_state); + pr_debug("%s adc_smp_state %d", __func__, smp->adc_smp_state); - for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) { - PHYDM_SNPRINTF((output + used, out_len - used, - "%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1])); + for (i = 0; i < (buf->length >> 2) - 2; i += 2) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "%08x%08x\n", buf->octet[i], buf->octet[i + 1]); } - PHYDM_SNPRINTF((output + used, out_len - used, "\n")); - /* PHYDM_SNPRINTF((output+used, out_len-used, "\n[%lu.%06lu]\n", t.tv_sec, t.tv_nsec)); */ + PDM_SNPF(out_len, used, output + used, out_len - used, "\n"); + /* PDM_SNPF(output + used, out_len - used, "\n[%lu.%06lu]\n", */ + /* t.tv_sec, t.tv_nsec); */ *pused = used; } -s32 -adc_smp_get_sample_counts( - void *p_dm_void -) +s32 adc_smp_get_sample_counts(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; - return (adc_smp_buf->length >> 2) - 2; + return (buf->length >> 2) - 2; } -s32 -adc_smp_query_single_data( - void *p_dm_void, - void *output, - u32 out_len, - u32 index -) +s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len, u32 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; u32 used = 0; - /* dbg_print("%s adc_smp_state %d\n", __func__, adc_smp->adc_smp_state); */ - if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) { - PHYDM_SNPRINTF((output + used, out_len - used, - "Error: la data is not ready yet ...\n")); + /* @dbg_print("%s adc_smp_state %d\n", __func__,*/ + /* smp->adc_smp_state);*/ + if (smp->adc_smp_state != ADCSMP_STATE_QUERY) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Error: la data is not ready yet ...\n"); return -1; } - if (index < ((adc_smp_buf->length >> 2) - 2)) { - PHYDM_SNPRINTF((output + used, out_len - used, "%08x%08x\n", - adc_smp_buf->octet[index], adc_smp_buf->octet[index + 1])); + if (idx < ((buf->length >> 2) - 2)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "%08x%08x\n", buf->octet[idx], buf->octet[idx + 1]); } return 0; } #endif -void -adc_smp_stop( - void *p_dm_void -) +void adc_smp_stop(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + + smp->adc_smp_state = ADCSMP_STATE_IDLE; - adc_smp->adc_smp_state = ADCSMP_STATE_IDLE; - dbg_print("[LA_Stop] LA_state = ((%d))\n", adc_smp->adc_smp_state); + PHYDM_DBG(dm, DBG_TMP, "[LA_Stop] LA_state = %d\n", smp->adc_smp_state); } -void -adc_smp_init( - void *p_dm_void -) +void adc_smp_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); - - adc_smp->adc_smp_state = ADCSMP_STATE_IDLE; - - if (p_dm_odm->support_ic_type & ODM_RTL8814A) { - adc_smp_buf->start_pos = 0x30000; - adc_smp_buf->buffer_size = 0x10000; - } else if (p_dm_odm->support_ic_type & ODM_RTL8822B) { - adc_smp_buf->start_pos = 0x20000; - adc_smp_buf->buffer_size = 0x20000; - } else if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - adc_smp_buf->start_pos = 0x00000; - adc_smp_buf->buffer_size = 0x10000; - } else if (p_dm_odm->support_ic_type & ODM_RTL8821C) { - adc_smp_buf->start_pos = 0x8000; - adc_smp_buf->buffer_size = 0x8000; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + + smp->adc_smp_state = ADCSMP_STATE_IDLE; + + if (dm->support_ic_type & ODM_RTL8814A) { + buf->start_pos = 0x30000; + buf->buffer_size = 0x10000; + } else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C)) { + buf->start_pos = 0x20000; + buf->buffer_size = 0x20000; + } else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8198F)) { + buf->start_pos = 0x00000; + buf->buffer_size = 0x10000; + } else if (dm->support_ic_type & ODM_RTL8192F) { + buf->start_pos = 0x2000; + buf->buffer_size = 0xE000; + } else if (dm->support_ic_type & ODM_RTL8821C) { + buf->start_pos = 0x8000; + buf->buffer_size = 0x8000; } + buf->end_pos = buf->start_pos + buf->buffer_size; + + PHYDM_DBG(dm, DBG_TMP, + "start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((%d))\n", + buf->start_pos, buf->end_pos, buf->buffer_size); } #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -void -adc_smp_de_init( - void *p_dm_void -) +void adc_smp_de_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; - adc_smp_stop(p_dm_odm); + adc_smp_stop(dm); - if (adc_smp_buf->length != 0x0) { - odm_free_memory(p_dm_odm, adc_smp_buf->octet, adc_smp_buf->length); - adc_smp_buf->length = 0x0; + if (buf->length != 0x0) { + odm_free_memory(dm, buf->octet, buf->length); + buf->length = 0x0; } } #endif - -void -phydm_la_mode_bb_setting( - void *p_dm_void -) +void phydm_la_mode_bb_setting(void *dm_void, boolean en_fake_trig) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - - u8 trig_mode = adc_smp->la_trig_mode; - u32 trig_sig_sel = adc_smp->la_trig_sig_sel; - u32 dbg_port = adc_smp->la_dbg_port; - u8 is_trigger_edge = adc_smp->la_trigger_edge; - u8 sampling_rate = adc_smp->la_smp_rate; - u32 dbg_port_header_sel = 0; - - dbg_print("1. [LA mode bb_setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n", - trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + + u8 trig_mode = smp->la_trig_mode; + u32 trig_sel = smp->la_trig_sig_sel; + u32 dbg_port = smp->la_dbg_port; + u8 edge = smp->la_trigger_edge; + u8 smp_rate = smp->la_smp_rate; + u8 dma_type = smp->la_dma_type; + u8 is_fake_trig = smp->is_fake_trig; + u32 dbg_port_hdr_sel = 0; + #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT) + boolean en_new_bbtrigger = smp->la_en_new_bbtrigger; + boolean ori_bb_dis = smp->la_ori_bb_dis; + u8 and1_sel = smp->la_and1_sel; + u8 and1_val = smp->la_and1_val; + u8 and2_sel = smp->la_and2_sel; + u8 and2_val = smp->la_and2_val; + u8 and3_sel = smp->la_and3_sel; + u8 and3_val = smp->la_and3_val; + u32 and4_en = smp->la_and4_en; + u32 and4_val = smp->la_and4_val; + #endif -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("1. [LA mode bb_setting]trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n", - trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel)); -#endif + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, + ("1. [LA mode bb_setting]trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n", + trig_mode, dbg_port, edge, smp_rate, trig_sel, dma_type)); + #endif if (trig_mode == PHYDM_MAC_TRIG) - trig_sig_sel = 0; /*ignore this setting*/ + trig_sel = 0; /*@ignore this setting*/ /*set BB debug port*/ - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, dbg_port)) { - dbg_print("Set dbg_port((0x%x)) success\n", dbg_port); + if (is_fake_trig) { + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0xf)) + pr_debug("Set fake dbg_port success\n"); + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /*@0x95C[4:0], BB debug port bit*/ + odm_set_bb_reg(dm, R_0x95c, 0x1f, 0x0); + #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT) + } else if (dm->support_ic_type & + (ODM_RTL8198F | ODM_RTL8822C)) { + if (!(en_new_bbtrigger)) + odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, 0x0); + else if (!(ori_bb_dis)) + odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, 0x0); + #endif + } else { + /*@0x9A0[4:0], BB debug port bit*/ + odm_set_bb_reg(dm, R_0x9a0, 0x1f, 0x0); + } + + pr_debug("1. [BB Setting] is_fake\n"); + } else { + if (en_fake_trig) + phydm_release_bb_dbg_port(dm); + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port)) + pr_debug("Set dbg_port((0x%x)) success\n", dbg_port); + else + pr_debug("Set dbg_port fail!\n"); + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /*@0x95C[4:0], BB debug port bit*/ + odm_set_bb_reg(dm, R_0x95c, 0x1f, trig_sel); + #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT) + } else if (dm->support_ic_type & + (ODM_RTL8198F | ODM_RTL8822C)) { + if (!(en_new_bbtrigger)) + odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel); + else if (!(ori_bb_dis)) + odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel); + #endif + } else { + /*@0x9A0[4:0], BB debug port bit*/ + odm_set_bb_reg(dm, R_0x9a0, 0x1f, trig_sel); + } + pr_debug("1. [BB Setting] is_fake = ((%d)), trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n", + is_fake_trig, trig_mode, dbg_port, edge, smp_rate, + trig_sel, dma_type); + if (en_fake_trig) + return; } - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { if (trig_mode == PHYDM_ADC_RF0_TRIG) - dbg_port_header_sel = 9; /*DBGOUT_RFC_a[31:0]*/ + dbg_port_hdr_sel = 9; /*@DBGOUT_RFC_a[31:0]*/ else if (trig_mode == PHYDM_ADC_RF1_TRIG) - dbg_port_header_sel = 8; /*DBGOUT_RFC_b[31:0]*/ - else - dbg_port_header_sel = 0; - - phydm_bb_dbg_port_header_sel(p_dm_odm, dbg_port_header_sel); - - - odm_set_bb_reg(p_dm_odm, 0x95C, 0x1f, trig_sig_sel); /*0x95C[4:0], BB debug port bit*/ - odm_set_bb_reg(p_dm_odm, 0x95C, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/ - odm_set_bb_reg(p_dm_odm, 0x95c, 0xe0, sampling_rate); - /* (0:) '80MHz' - (1:) '40MHz' - (2:) '20MHz' - (3:) '10MHz' - (4:) '5MHz' - (5:) '2.5MHz' - (6:) '1.25MHz' - (7:) '160MHz (for BW160 ic)' - */ - if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (p_dm_odm->cut_version >= ODM_CUT_B)) { - odm_set_bb_reg(p_dm_odm, 0x95c, BIT(23), 1); + dbg_port_hdr_sel = 8; /*@DBGOUT_RFC_b[31:0]*/ + else if ((trig_mode == PHYDM_ADC_BB_TRIG) || + (trig_mode == PHYDM_ADC_MAC_TRIG)) { + if (smp->la_mac_mask_or_hdr_sel <= 0xf) + dbg_port_hdr_sel = smp->la_mac_mask_or_hdr_sel; + else + dbg_port_hdr_sel = 0; } - } else { - odm_set_bb_reg(p_dm_odm, 0x9a0, 0x1f, trig_sig_sel); /*0x9A0[4:0], BB debug port bit*/ - - odm_set_bb_reg(p_dm_odm, 0x9A0, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/ - odm_set_bb_reg(p_dm_odm, 0x9A0, 0xe0, sampling_rate); - /* (0:) '80MHz' - (1:) '40MHz' - (2:) '20MHz' - (3:) '10MHz' - (4:) '5MHz' - (5:) '2.5MHz' - (6:) '1.25MHz' - (7:) '160MHz (for BW160 ic)' - */ - } -} -void -phydm_la_mode_set_trigger_time( - void *p_dm_void, - u32 trigger_time_mu_sec -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 trigger_time_unit_num; - u32 time_unit = 0; - - if (trigger_time_mu_sec < 128) { - time_unit = 0; /*unit: 1mu sec*/ - } else if (trigger_time_mu_sec < 256) { - time_unit = 1; /*unit: 2mu sec*/ - } else if (trigger_time_mu_sec < 512) { - time_unit = 2; /*unit: 4mu sec*/ - } else if (trigger_time_mu_sec < 1024) { - time_unit = 3; /*unit: 8mu sec*/ - } else if (trigger_time_mu_sec < 2048) { - time_unit = 4; /*unit: 16mu sec*/ - } else if (trigger_time_mu_sec < 4096) { - time_unit = 5; /*unit: 32mu sec*/ - } else if (trigger_time_mu_sec < 8192) { - time_unit = 6; /*unit: 64mu sec*/ - } + phydm_bb_dbg_port_header_sel(dm, dbg_port_hdr_sel); + + /*@0x95C[11:8]*/ + odm_set_bb_reg(dm, R_0x95c, 0xf00, dma_type); + /*@0: posedge, 1: negedge*/ + odm_set_bb_reg(dm, R_0x95c, BIT(31), edge); + odm_set_bb_reg(dm, R_0x95c, 0xe0, smp_rate); + /* @(0:) '80MHz' + * (1:) '40MHz' + * (2:) '20MHz' + * (3:) '10MHz' + * (4:) '5MHz' + * (5:) '2.5MHz' + * (6:) '1.25MHz' + * (7:) '160MHz (for BW160 ic)' + */ + if ((dm->support_ic_type & ODM_RTL8821C) && + (dm->cut_version >= ODM_CUT_B)) + odm_set_bb_reg(dm, R_0x95c, BIT(23), 1); + #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT) + } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) { + /*@MAC-PHY timing*/ + odm_set_bb_reg(dm, R_0x1ce4, BIT(7) | BIT(6), 0); + odm_set_bb_reg(dm, R_0x1cf4, BIT(23), 1); /*@LA mode on*/ + odm_set_bb_reg(dm, R_0x1ce4, 0x3f, dma_type); + /*@0: posedge, 1: negedge ??*/ + odm_set_bb_reg(dm, R_0x1ce4, BIT(26), edge); + odm_set_bb_reg(dm, R_0x1ce4, 0x700, smp_rate); + + if (!en_new_bbtrigger) { /*normal LA mode & back to default*/ + + pr_debug("Set bb default setting\n"); + + /*path 1 default: enable ori. BB trigger*/ + odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0); + + /*@AND1~AND4 default: off*/ + odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, 0); /*@AND 1*/ + odm_set_bb_reg(dm, R_0x1ce8, 0x1f, 0); /*@AND 1 val*/ + odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ + + odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); /*@AND 2*/ + odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, 0); /*@AND 2 val*/ + /*@AND 2 inv*/ + odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); + + odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); /*@AND 3*/ + /*@AND 3 val*/ + odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000, 0); + /*@AND 3 inv*/ + odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); + + /*@AND 4 en*/ + odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, 0); + /*@AND 4 val*/ + odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, 0); + /*@AND 4 inv*/ + odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); + + pr_debug("Set bb default setting finished\n"); + + } else if (en_new_bbtrigger) { + /*path 1 default: enable ori. BB trigger*/ + if (ori_bb_dis) + odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 1); + else + odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0); + + /* @AND1 */ + odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@invert*/ + + if (and1_sel == 0x4 || and1_sel == 0x5 || + and1_sel == 0x6) { + /* rx_state, rx_state_freq, field */ + odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, + and1_sel); + odm_set_bb_reg(dm, R_0x1ce8, 0x1f, and1_val); + + } else if (and1_sel == 0x7) { + /* @mux state */ + odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, + and1_sel); + odm_set_bb_reg(dm, R_0x1ce8, 0xf, and1_val); + + } else { + odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, + and1_sel); + } - trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit); + /* @AND2 */ + odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@invert*/ - dbg_print("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit)); -#endif + if (and2_sel == 0x4 || and2_sel == 0x5 || + and2_sel == 0x6) { + /* rx_state, rx_state_freq, field */ + odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, and2_sel); + odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, and2_val); - odm_set_mac_reg(p_dm_odm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit); - odm_set_mac_reg(p_dm_odm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f)); + } else if (and2_sel == 0x7) { + /* @mux state */ + odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, and2_sel); + odm_set_bb_reg(dm, R_0x1ce8, 0x3c00, and2_val); + } else { + odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, and2_sel); + } + + /* @AND3 */ + odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@invert*/ + + if (and3_sel == 0x4 || and3_sel == 0x5 || + and3_sel == 0x6) { + /* rx_state, rx_state_freq, field */ + odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, and3_sel); + odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000, + and3_val); + + } else if (and3_sel == 0x7) { + /* @mux state */ + odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, and3_sel); + odm_set_bb_reg(dm, R_0x1ce8, 0xf00000, + and3_val); + } else { + odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, and3_sel); + } + + /* @AND4 */ + odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@invert*/ + odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, and4_en); + odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, and4_val); + } + #endif + } else { + #if (RTL8192F_SUPPORT) + if ((dm->support_ic_type & ODM_RTL8192F)) + /*@LA reset HW block enable for true-mac asic*/ + odm_set_bb_reg(dm, R_0x9a0, BIT(15), 1); + #endif + /*@0x9A0[11:8]*/ + odm_set_bb_reg(dm, R_0x9a0, 0xf00, dma_type); + /*@0: posedge, 1: negedge*/ + odm_set_bb_reg(dm, R_0x9a0, BIT(31), edge); + odm_set_bb_reg(dm, R_0x9a0, 0xe0, smp_rate); + /* @(0:) '80MHz' + * (1:) '40MHz' + * (2:) '20MHz' + * (3:) '10MHz' + * (4:) '5MHz' + * (5:) '2.5MHz' + * (6:) '1.25MHz' + * (7:) '160MHz (for BW160 ic)' + */ + } } +void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 time_unit_num = 0; + u32 unit = 0; + + if (trigger_time_mu_sec < 128) + unit = 0; /*unit: 1mu sec*/ + else if (trigger_time_mu_sec < 256) + unit = 1; /*unit: 2mu sec*/ + else if (trigger_time_mu_sec < 512) + unit = 2; /*unit: 4mu sec*/ + else if (trigger_time_mu_sec < 1024) + unit = 3; /*unit: 8mu sec*/ + else if (trigger_time_mu_sec < 2048) + unit = 4; /*unit: 16mu sec*/ + else if (trigger_time_mu_sec < 4096) + unit = 5; /*unit: 32mu sec*/ + else if (trigger_time_mu_sec < 8192) + unit = 6; /*unit: 64mu sec*/ + + time_unit_num = (u8)(trigger_time_mu_sec >> unit); + + pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", + time_unit_num, unit); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ( + "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", + time_unit_num, unit)); + #endif -void -phydm_lamode_trigger_setting( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -) + if (dm->support_ic_type & ODM_RTL8192F) { + odm_set_mac_reg(dm, R_0x7fc, BIT(2) | BIT(1) | BIT(0), unit); + odm_set_mac_reg(dm, R_0x7f0, 0x7f00, (time_unit_num & 0x7f)); + #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT) + } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) { + odm_set_mac_reg(dm, R_0x7cc, BIT(18) | BIT(17) | BIT(16), unit); + odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f)); + #endif + } else { + odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit); + odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f)); + } +} + +void phydm_lamode_trigger_cmd(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); - u8 trig_mode, dma_data_sig_sel; - u32 trig_sig_sel; - boolean is_enable_la_mode, is_trigger_edge; - u32 dbg_port, trigger_time_mu_sec; - u32 mac_ref_signal_mask; - u8 sampling_rate = 0, i; - char help[] = "-h"; - u32 var1[10] = {0}; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + u8 trig_mode = 0, dma_data_sig_sel = 0; + u32 trig_sig_sel = 0; + u8 enable_la_mode = 0; + u32 trigger_time_mu_sec = 0; + char help[] = "-h"; + u32 var1[10] = {0}; u32 used = *_used; u32 out_len = *_out_len; - if (p_dm_odm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) { - + if (dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) { PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - is_enable_la_mode = (boolean)var1[0]; - /*dbg_print("echo cmd input_num = %d\n", input_num);*/ + enable_la_mode = (u8)var1[0]; +#if 0 + /*@dbg_print("echo cmd input_num = %d\n", input_num);*/ +#endif if ((strcmp(input[1], help) == 0)) { - PHYDM_SNPRINTF((output + used, out_len - used, "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {polling_time/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n")); - /**/ - } else if ((is_enable_la_mode == 1)) { - + PDM_SNPF(out_len, used, output + used, out_len - used, + "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n"); + } else if (enable_la_mode == 1) { PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); trig_mode = (u8)var1[1]; @@ -733,29 +991,86 @@ phydm_lamode_trigger_setting( dma_data_sig_sel = (u8)var1[3]; trigger_time_mu_sec = var1[4]; /*unit: us*/ - adc_smp->la_mac_ref_mask = var1[5]; - adc_smp->la_dbg_port = var1[6]; - adc_smp->la_trigger_edge = (u8) var1[7]; - adc_smp->la_smp_rate = (u8)(var1[8] & 0x7); - adc_smp->la_count = var1[9]; - - - dbg_print("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9])); -#endif - - PHYDM_SNPRINTF((output + used, out_len - used, "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", trig_mode, trig_sig_sel, dma_data_sig_sel)); - PHYDM_SNPRINTF((output + used, out_len - used, "e.Trig_Time = ((%dus)), f.mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", trigger_time_mu_sec, adc_smp->la_mac_ref_mask, adc_smp->la_dbg_port)); - PHYDM_SNPRINTF((output + used, out_len - used, "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", adc_smp->la_trigger_edge, (80 >> adc_smp->la_smp_rate), adc_smp->la_count)); - - adc_smp_set(p_dm_odm, trig_mode, trig_sig_sel, dma_data_sig_sel, trigger_time_mu_sec, 0); + smp->la_mac_mask_or_hdr_sel = var1[5]; + smp->la_dbg_port = var1[6]; + smp->la_trigger_edge = (u8)var1[7]; + smp->la_smp_rate = (u8)(var1[8] & 0x7); + smp->la_count = var1[9]; + + #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT) + smp->la_en_new_bbtrigger = false; + #endif + + pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n", + var1[0], var1[1], var1[2], var1[3], var1[4], + var1[5], var1[6], var1[7], var1[8], var1[9]); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ( + "echo lamode %d %d %d %d %d %d %x %d %d %d\n", + var1[0], var1[1], var1[2], var1[3], + var1[4], var1[5], var1[6], var1[7], + var1[8], var1[9])); + #endif + + PDM_SNPF(out_len, used, output + used, out_len - used, + "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", + trig_mode, trig_sig_sel, dma_data_sig_sel); + PDM_SNPF(out_len, used, output + used, out_len - used, + "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", + trigger_time_mu_sec, + smp->la_mac_mask_or_hdr_sel, smp->la_dbg_port); + PDM_SNPF(out_len, used, output + used, out_len - used, + "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", + smp->la_trigger_edge, (80 >> smp->la_smp_rate), + smp->la_count); + + #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT) + PDM_SNPF(out_len, used, output + used, out_len - used, + "k.en_new_bbtrigger = ((%d))\n", + smp->la_en_new_bbtrigger); + #endif + + adc_smp_set(dm, trig_mode, trig_sig_sel, + dma_data_sig_sel, trigger_time_mu_sec, 0); + + #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT) + } else if (enable_la_mode == 100) { + smp->la_en_new_bbtrigger = true; + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + PHYDM_SSCANF(input[4], DCMD_HEX, &var1[3]); + PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]); + PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]); + PHYDM_SSCANF(input[7], DCMD_DECIMAL, &var1[6]); + PHYDM_SSCANF(input[8], DCMD_HEX, &var1[7]); + PHYDM_SSCANF(input[9], DCMD_HEX, &var1[8]); + PHYDM_SSCANF(input[10], DCMD_HEX, &var1[9]); + + smp->la_ori_bb_dis = (boolean)var1[1]; + smp->la_and1_sel = (u8)var1[2]; + smp->la_and1_val = (u8)var1[3]; + smp->la_and2_sel = (u8)var1[4]; + smp->la_and2_val = (u8)var1[5]; + smp->la_and3_sel = (u8)var1[6]; + smp->la_and3_val = (u8)var1[7]; + smp->la_and4_en = (u32)var1[8]; + smp->la_and4_val = (u32)var1[9]; + + phydm_adc_smp_start(dm); + + } else if (enable_la_mode == 101) { + smp->la_en_new_bbtrigger = false; + phydm_adc_smp_start(dm); + #endif } else { - adc_smp_stop(p_dm_odm); - PHYDM_SNPRINTF((output + used, out_len - used, "Disable LA mode\n")); + adc_smp_stop(dm); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable LA mode\n"); } } + *_used = used; + *_out_len = out_len; } -#endif /*endif PHYDM_LA_MODE_SUPPORT == 1*/ +#endif /*@endif PHYDM_LA_MODE_SUPPORT*/ diff --git a/hal/phydm/phydm_adc_sampling.h b/hal/phydm/phydm_adc_sampling.h index 2acd0f5..1a0a3fe 100644 --- a/hal/phydm/phydm_adc_sampling.h +++ b/hal/phydm/phydm_adc_sampling.h @@ -1,18 +1,43 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + #ifndef __INC_ADCSMP_H #define __INC_ADCSMP_H -#define DYNAMIC_LA_MODE "1.0" /*2016.07.15 Dino */ +#if (PHYDM_LA_MODE_SUPPORT) -#if (PHYDM_LA_MODE_SUPPORT == 1) +#define DYNAMIC_LA_MODE "2.0" -struct _RT_ADCSMP_STRING { +struct rt_adcsmp_string { u32 *octet; u32 length; u32 buffer_size; u32 start_pos; + u32 end_pos; /*@buf addr*/ }; - enum rt_adcsmp_trig_sel { PHYDM_ADC_BB_TRIG = 0, PHYDM_ADC_MAC_TRIG = 1, @@ -21,7 +46,6 @@ enum rt_adcsmp_trig_sel { PHYDM_MAC_TRIG = 4 }; - enum rt_adcsmp_trig_sig_sel { ADCSMP_TRIG_CRCOK = 0, ADCSMP_TRIG_CRCFAIL = 1, @@ -29,28 +53,41 @@ enum rt_adcsmp_trig_sig_sel { ADCSMP_TRIG_REG = 3 }; - enum rt_adcsmp_state { ADCSMP_STATE_IDLE = 0, ADCSMP_STATE_SET = 1, ADCSMP_STATE_QUERY = 2 }; - -struct _RT_ADCSMP { - struct _RT_ADCSMP_STRING adc_smp_buf; +struct rt_adcsmp { + struct rt_adcsmp_string adc_smp_buf; enum rt_adcsmp_state adc_smp_state; u8 la_trig_mode; u32 la_trig_sig_sel; u8 la_dma_type; u32 la_trigger_time; - u32 la_mac_ref_mask; + /* + * @1.BB mode: for debug port header sel; + * 2.MAC mode: for reference mask + */ + u32 la_mac_mask_or_hdr_sel; u32 la_dbg_port; u8 la_trigger_edge; u8 la_smp_rate; u32 la_count; u8 is_bb_trigger; u8 la_work_item_index; + boolean la_en_new_bbtrigger; + boolean la_ori_bb_dis; + u8 la_and1_sel; + u8 la_and1_val; + u8 la_and2_sel; + u8 la_and2_val; + u8 la_and3_sel; + u8 la_and3_val; + u32 la_and4_en; + u32 la_and4_val; + boolean is_fake_trig; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) RT_WORK_ITEM adc_smp_work_item; @@ -59,89 +96,39 @@ struct _RT_ADCSMP { }; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -void -adc_smp_work_item_callback( - void *p_context -); +void adc_smp_work_item_callback( + void *context); #endif -void -adc_smp_set( - void *p_dm_void, - u8 trig_mode, - u32 trig_sig_sel, - u8 dma_data_sig_sel, - u32 trigger_time, - u16 polling_time -); +void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel, + u8 dma_data_sig_sel, u32 trig_time, u16 polling_time); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) enum rt_status -adc_smp_query( - void *p_dm_void, - ULONG information_buffer_length, - void *information_buffer, - PULONG bytes_written -); +adc_smp_query(void *dm_void, ULONG info_buf_length, void *info_buf, + PULONG bytes_written); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) -void -adc_smp_query( - void *p_dm_void, - void *output, - u32 out_len, - u32 *pused -); - -s32 -adc_smp_get_sample_counts( - void *p_dm_void -); - -s32 -adc_smp_query_single_data( - void *p_dm_void, - void *output, - u32 out_len, - u32 index -); +void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused); + +s32 adc_smp_get_sample_counts(void *dm_void); + +s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len, + u32 idx); #endif -void -adc_smp_stop( - void *p_dm_void -); +void adc_smp_stop(void *dm_void); -void -adc_smp_init( - void *p_dm_void -); +void adc_smp_init(void *dm_void); #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -void -adc_smp_de_init( - void *p_dm_void -); +void adc_smp_de_init(void *dm_void); #endif -void -phydm_la_mode_bb_setting( - void *p_dm_void -); - -void -phydm_la_mode_set_trigger_time( - void *p_dm_void, - u32 trigger_time_mu_sec -); - -void -phydm_lamode_trigger_setting( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -); +void phydm_la_mode_bb_setting(void *dm_void, boolean en_fake_trig); + +void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec); + +void phydm_lamode_trigger_cmd(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); #endif #endif diff --git a/hal/phydm/phydm_antdect.c b/hal/phydm/phydm_antdect.c index e16fd25..5a44a05 100644 --- a/hal/phydm/phydm_antdect.c +++ b/hal/phydm/phydm_antdect.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,15 +8,20 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ /* ************************************************************ * include files @@ -25,47 +30,55 @@ #include "mp_precomp.h" #include "phydm_precomp.h" -/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */ -#if (defined(CONFIG_ANT_DETECTION)) +#ifdef CONFIG_ANT_DETECTION -/* IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter) +/* @IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter) * IS_ANT_DETECT_SUPPORT_RSSI(adapter) * IS_ANT_DETECT_SUPPORT_PSD(adapter) */ -/* 1 [1. Single Tone method] =================================================== */ +/* @1 [1. Single Tone method] =================================================== */ -/* +/*@ * Description: * Set Single/Dual Antenna default setting for products that do not do detection in advance. * * Added by Joseph, 2012.03.22 * */ -void -odm_single_dual_antenna_default_setting( - void *p_dm_void -) +void odm_sw_ant_div_construct_scan_chnl( + void *adapter, + u8 scan_chnl) +{ +} + +u8 odm_sw_ant_div_select_scan_chnl( + void *adapter) +{ + return 0; +} + +void odm_single_dual_antenna_default_setting( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + void *adapter = dm->adapter; - u8 bt_ant_num = BT_GetPgAntNum(p_adapter); + u8 bt_ant_num = BT_GetPgAntNum(adapter); /* Set default antenna A and B status */ if (bt_ant_num == 2) { - p_dm_swat_table->ANTA_ON = true; - p_dm_swat_table->ANTB_ON = true; + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = true; } else if (bt_ant_num == 1) { /* Set antenna A as default */ - p_dm_swat_table->ANTA_ON = true; - p_dm_swat_table->ANTB_ON = false; + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = false; } else RT_ASSERT(false, ("Incorrect antenna number!!\n")); } - -/* 2 8723A ANT DETECT +/* @2 8723A ANT DETECT * * Description: * Implement IQK single tone for RF DPK loopback and BB PSD scanning. @@ -75,769 +88,804 @@ odm_single_dual_antenna_default_setting( * */ boolean odm_single_dual_antenna_detection( - void *p_dm_void, - u8 mode -) + void *dm_void, + u8 mode) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - u32 current_channel, rf_loop_reg; - u8 n; - u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca; - u8 initial_gain = 0x5a; - u32 PSD_report_tmp; - u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0; - boolean is_result = true; - u32 afe_backup[16]; - u32 AFE_REG_8723A[16] = { - REG_RX_WAIT_CCA, REG_TX_CCK_RFON, - REG_TX_CCK_BBON, REG_TX_OFDM_RFON, - REG_TX_OFDM_BBON, REG_TX_TO_RX, - REG_TX_TO_TX, REG_RX_CCK, - REG_RX_OFDM, REG_RX_WAIT_RIFS, - REG_RX_TO_RX, REG_STANDBY, - REG_SLEEP, REG_PMPD_ANAEN, - REG_FPGA0_XCD_SWITCH_CONTROL, REG_BLUE_TOOTH - }; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection()============>\n")); - - - if (!(p_dm_odm->support_ic_type & ODM_RTL8723B)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + u32 current_channel, rf_loop_reg; + u8 n; + u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca; + u8 initial_gain = 0x5a; + u32 PSD_report_tmp; + u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0; + boolean is_result = true; + + PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__); + + if (!(dm->support_ic_type & ODM_RTL8723B)) return is_result; /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */ - if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(p_adapter)) + if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter))) return is_result; - /* 1 Backup Current RF/BB Settings */ - - current_channel = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); - rf_loop_reg = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK); - if (p_dm_odm->support_ic_type & ODM_RTL8723B) { - reg92c = odm_get_bb_reg(p_dm_odm, REG_DPDT_CONTROL, MASKDWORD); - reg930 = odm_get_bb_reg(p_dm_odm, rfe_ctrl_anta_src, MASKDWORD); - reg948 = odm_get_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD); - regb2c = odm_get_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD); - reg064 = odm_get_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29)); - odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, 0x3, 0x1); - odm_set_bb_reg(p_dm_odm, rfe_ctrl_anta_src, 0xff, 0x77); - odm_set_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* dbg 7 */ - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0);/* dbg 8 */ - odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x0); + /* @1 Backup Current RF/BB Settings */ + + current_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); + rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK); + if (dm->support_ic_type & ODM_RTL8723B) { + reg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD); + reg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD); + reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD); + regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD); + reg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29)); + odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1); + odm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77); + odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* @dbg 7 */ + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0); /* @dbg 8 */ + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0); } - odm_stall_execution(10); + ODM_delay_us(10); /* Store A path Register 88c, c08, 874, c50 */ - reg88c = odm_get_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD); - regc08 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD); - reg874 = odm_get_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD); - regc50 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); + reg88c = odm_get_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD); + regc08 = odm_get_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD); + reg874 = odm_get_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD); + regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); /* Store AFE Registers */ - if (p_dm_odm->support_ic_type & ODM_RTL8723B) - afe_rrx_wait_cca = odm_get_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD); + if (dm->support_ic_type & ODM_RTL8723B) + afe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD); /* Set PSD 128 pts */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pts */ + odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* @128 pts */ /* To SET CH1 to do */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* channel 1 */ + odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* @channel 1 */ - /* AFE all on step */ - if (p_dm_odm->support_ic_type & ODM_RTL8723B) - odm_set_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016); + /* @AFE all on step */ + if (dm->support_ic_type & ODM_RTL8723B) + odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016); - /* 3 wire Disable */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0); + /* @3 wire Disable */ + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0); - /* BB IQK setting */ - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4); - odm_set_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000); + /* @BB IQK setting */ + odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4); + odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000); - /* IQK setting tone@ 4.34Mhz */ - odm_set_bb_reg(p_dm_odm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C); - odm_set_bb_reg(p_dm_odm, REG_TX_IQK, MASKDWORD, 0x01007c00); + /* @IQK setting tone@ 4.34Mhz */ + odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C); + odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00); /* Page B init */ - odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000); - odm_set_bb_reg(p_dm_odm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000); - odm_set_bb_reg(p_dm_odm, REG_RX_IQK, MASKDWORD, 0x01004800); - odm_set_bb_reg(p_dm_odm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f); - if (p_dm_odm->support_ic_type & ODM_RTL8723B) { - odm_set_bb_reg(p_dm_odm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016); - odm_set_bb_reg(p_dm_odm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016); + odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000); + odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000); + odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800); + odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f); + if (dm->support_ic_type & ODM_RTL8723B) { + odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016); + odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016); } - odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0); - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain); + odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0); + odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain); - /* IQK Single tone start */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x808000); - odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000); - odm_set_bb_reg(p_dm_odm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000); + /* @IQK Single tone start */ + odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); + odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000); + odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000); - odm_stall_execution(10000); + ODM_delay_us(10000); /* PSD report of antenna A */ PSD_report_tmp = 0x0; for (n = 0; n < 2; n++) { - PSD_report_tmp = phydm_get_psd_data(p_dm_odm, 14, initial_gain); + PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain); if (PSD_report_tmp > ant_a_report) ant_a_report = PSD_report_tmp; } - /* change to Antenna B */ - if (p_dm_odm->support_ic_type & ODM_RTL8723B) { - /* odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, 0x3, 0x2); */ - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); - odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); + /* @change to Antenna B */ + if (dm->support_ic_type & ODM_RTL8723B) { +#if 0 + /* odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x2); */ +#endif + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); } - odm_stall_execution(10); + ODM_delay_us(10); /* PSD report of antenna B */ PSD_report_tmp = 0x0; for (n = 0; n < 2; n++) { - PSD_report_tmp = phydm_get_psd_data(p_dm_odm, 14, initial_gain); + PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain); if (PSD_report_tmp > ant_b_report) ant_b_report = PSD_report_tmp; } - /* Close IQK Single Tone function */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_IQK, 0xffffff00, 0x000000); + /* @Close IQK Single Tone function */ + odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); - /* 1 Return to antanna A */ - if (p_dm_odm->support_ic_type & ODM_RTL8723B) { - /* external DPDT */ - odm_set_bb_reg(p_dm_odm, REG_DPDT_CONTROL, MASKDWORD, reg92c); + /* @1 Return to antanna A */ + if (dm->support_ic_type & ODM_RTL8723B) { + /* @external DPDT */ + odm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c); - /* internal S0/S1 */ - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); - odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); - odm_set_bb_reg(p_dm_odm, rfe_ctrl_anta_src, MASKDWORD, reg930); - odm_set_mac_reg(p_dm_odm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064); + /* @internal S0/S1 */ + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); + odm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930); + odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064); } - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c); - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08); - odm_set_bb_reg(p_dm_odm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874); - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40); - odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_loop_reg); + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c); + odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08); + odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874); + odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40); + odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50); + odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_loop_reg); /* Reload AFE Registers */ - if (p_dm_odm->support_ic_type & ODM_RTL8723B) - odm_set_bb_reg(p_dm_odm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca); + if (dm->support_ic_type & ODM_RTL8723B) + odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca); - if (p_dm_odm->support_ic_type & ODM_RTL8723B) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, ant_a_report)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, ant_b_report)); + if (dm->support_ic_type & ODM_RTL8723B) { + PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416, + ant_a_report); + PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416, + ant_b_report); - /* 2 Test ant B based on ant A is ON */ - if ((ant_a_report >= 100) && (ant_b_report >= 100) && (ant_a_report <= 135) && (ant_b_report <= 135)) { + /* @2 Test ant B based on ant A is ON */ + if (ant_a_report >= 100 && ant_b_report >= 100 && ant_a_report <= 135 && ant_b_report <= 135) { u8 TH1 = 2, TH2 = 6; if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) { - p_dm_swat_table->ANTA_ON = true; - p_dm_swat_table->ANTB_ON = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Dual Antenna\n")); + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual Antenna\n", + __func__); } else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) || - ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) { - p_dm_swat_table->ANTA_ON = false; - p_dm_swat_table->ANTB_ON = false; + ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) { + dm_swat_table->ANTA_ON = false; + dm_swat_table->ANTB_ON = false; is_result = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Need to check again\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Need to check again\n", + __func__); } else { - p_dm_swat_table->ANTA_ON = true; - p_dm_swat_table->ANTB_ON = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection(): Single Antenna\n")); + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = false; + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Single Antenna\n", __func__); } - p_dm_odm->ant_detected_info.is_ant_detected = true; - p_dm_odm->ant_detected_info.db_for_ant_a = ant_a_report; - p_dm_odm->ant_detected_info.db_for_ant_b = ant_b_report; - p_dm_odm->ant_detected_info.db_for_ant_o = ant_0_report; + dm->ant_detected_info.is_ant_detected = true; + dm->ant_detected_info.db_for_ant_a = ant_a_report; + dm->ant_detected_info.db_for_ant_b = ant_b_report; + dm->ant_detected_info.db_for_ant_o = ant_0_report; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("return false!!\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "return false!!\n"); is_result = false; } } return is_result; - } - - -/* 1 [2. Scan AP RSSI method] ================================================== */ - - - +/* @1 [2. Scan AP RSSI method] ================================================== */ boolean odm_sw_ant_div_check_before_link( - void *p_dm_void -) + void *dm_void) { - #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - s8 score = 0; - PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc; - u8 power_target_L = 9, power_target_H = 16; - u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff; - u16 index, counter = 0; - static u8 scan_channel; - u32 tmp_swas_no_link_bk_reg948; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", p_dm_odm->dm_swat_table.ANTA_ON, p_dm_odm->dm_swat_table.ANTB_ON)); - - /* if(HP id) */ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + //PMGNT_INFO mgnt_info = &adapter->MgntInfo; + PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo); + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + s8 score = 0; + PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc; + u8 power_target_L = 9, power_target_H = 16; + u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff; + u16 index, counter = 0; + static u8 scan_channel; + u32 tmp_swas_no_link_bk_reg948; + + PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", + dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON); + + /* @if(HP id) */ { - if (p_dm_odm->dm_swat_table.rssi_ant_dect_result == true && p_dm_odm->support_ic_type == ODM_RTL8723B) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n")); + if (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "8723B RSSI-based Antenna Detection is done\n"); return false; } - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - if (p_dm_swat_table->swas_no_link_bk_reg948 == 0xff) - p_dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(p_dm_odm, REG_S0_S1_PATH_SWITCH); + if (dm->support_ic_type == ODM_RTL8723B) { + if (dm_swat_table->swas_no_link_bk_reg948 == 0xff) + dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH); } } - if (p_dm_odm->adapter == NULL) { /* For BSOD when plug/unplug fast. //By YJ,120413 */ + if (dm->adapter == NULL) { /* @For BSOD when plug/unplug fast. //By YJ,120413 */ /* The ODM structure is not initialized. */ return false; } /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */ - if (!IS_ANT_DETECT_SUPPORT_RSSI(adapter)) + if (!IS_ANT_DETECT_SUPPORT_RSSI(((PADAPTER)adapter))) return false; else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI method\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "Antenna Detection: RSSI method\n"); /* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */ - odm_acquire_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK); - if (p_hal_data->eRFPowerState != eRfOn || p_mgnt_info->RFChangeInProgress || p_mgnt_info->bMediaConnect) { - odm_release_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK); + odm_acquire_spin_lock(dm, RT_RF_STATE_SPINLOCK); + if (hal_data->eRFPowerState != eRfOn || mgnt_info->RFChangeInProgress || mgnt_info->bMediaConnect) { + odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("odm_sw_ant_div_check_before_link(): rf_change_in_progress(%x), e_rf_power_state(%x)\n", - p_mgnt_info->RFChangeInProgress, p_hal_data->eRFPowerState)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: rf_change_in_progress(%x), e_rf_power_state(%x)\n", + __func__, mgnt_info->RFChangeInProgress, + hal_data->eRFPowerState); - p_dm_swat_table->swas_no_link_state = 0; + dm_swat_table->swas_no_link_state = 0; return false; } else - odm_release_spin_lock(p_dm_odm, RT_RF_STATE_SPINLOCK); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->swas_no_link_state = %d\n", p_dm_swat_table->swas_no_link_state)); - /* 1 Run AntDiv mechanism "Before Link" part. */ - if (p_dm_swat_table->swas_no_link_state == 0) { - /* 1 Prepare to do Scan again to check current antenna state. */ + odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK); + PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n", + dm_swat_table->swas_no_link_state); + /* @1 Run AntDiv mechanism "Before Link" part. */ + if (dm_swat_table->swas_no_link_state == 0) { + /* @1 Prepare to do Scan again to check current antenna state. */ /* Set check state to next step. */ - p_dm_swat_table->swas_no_link_state = 1; + dm_swat_table->swas_no_link_state = 1; - /* Copy Current Scan list. */ - p_mgnt_info->tmpNumBssDesc = p_mgnt_info->NumBssDesc; - PlatformMoveMemory((void *)adapter->MgntInfo.tmpbssDesc, (void *)p_mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC); + /* @Copy Current Scan list. */ + mgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc; + PlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC); - /* Go back to scan function again. */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Scan one more time\n")); - p_mgnt_info->ScanStep = 0; - p_mgnt_info->bScanAntDetect = true; + /* @Go back to scan function again. */ + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Scan one more time\n", + __func__); + mgnt_info->ScanStep = 0; + mgnt_info->bScanAntDetect = true; scan_channel = odm_sw_ant_div_select_scan_chnl(adapter); - - if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { - if (p_dm_fat_table->rx_idle_ant == MAIN_ANT) - odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { + if (fat_tab->rx_idle_ant == MAIN_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); else - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); + odm_update_rx_idle_ant(dm, MAIN_ANT); if (scan_channel == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("odm_sw_ant_div_check_before_link(): No AP List Avaiable, Using ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT")); - - if (IS_5G_WIRELESS_MODE(p_mgnt_info->dot11CurrentWirelessMode)) { - p_dm_swat_table->ant_5g = p_dm_fat_table->rx_idle_ant; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_5g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: No AP List Avaiable, Using ant(%s)\n", + __func__, + (fat_tab->rx_idle_ant == MAIN_ANT) ? + "AUX_ANT" : "MAIN_ANT"); + + if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) { + dm_swat_table->ant_5g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); } else { - p_dm_swat_table->ant_2g = p_dm_fat_table->rx_idle_ant; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_2g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + dm_swat_table->ant_2g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); } return false; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("odm_sw_ant_div_check_before_link: Change to %s for testing.\n", ((p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"))); - } else if (p_dm_odm->support_ic_type & (ODM_RTL8723B)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Change to %s for testing.\n", __func__, + ((fat_tab->rx_idle_ant == MAIN_ANT) ? + "MAIN_ANT" : "AUX_ANT")); + } else if (dm->support_ic_type & (ODM_RTL8723B)) { /*Switch Antenna to another one.*/ - tmp_swas_no_link_bk_reg948 = odm_read_4byte(p_dm_odm, REG_S0_S1_PATH_SWITCH); + tmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH); - if ((p_dm_swat_table->cur_antenna == MAIN_ANT) && (tmp_swas_no_link_bk_reg948 == 0x200)) { - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); - odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); - p_dm_swat_table->cur_antenna = AUX_ANT; + if (dm_swat_table->cur_antenna == MAIN_ANT && tmp_swas_no_link_bk_reg948 == 0x200) { + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); + dm_swat_table->cur_antenna = AUX_ANT; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_swas_no_link_bk_reg948)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "Reg[948]= (( %x )) was in wrong state\n", + tmp_swas_no_link_bk_reg948); return false; } - odm_stall_execution(10); + ODM_delay_us(10); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Change to (( %s-ant)) for testing.\n", (p_dm_swat_table->cur_antenna == MAIN_ANT) ? "MAIN" : "AUX")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Change to (( %s-ant)) for testing.\n", + __func__, + (dm_swat_table->cur_antenna == MAIN_ANT) ? + "MAIN" : "AUX"); } odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); - PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5); + PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5); return true; - } else { /* p_dm_swat_table->swas_no_link_state == 1 */ - /* 1 ScanComple() is called after antenna swiched. */ - /* 1 Check scan result and determine which antenna is going */ - /* 1 to be used. */ + } else { /* @dm_swat_table->swas_no_link_state == 1 */ + /* @1 ScanComple() is called after antenna swiched. */ + /* @1 Check scan result and determine which antenna is going */ + /* @1 to be used. */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" tmp_num_bss_desc= (( %d ))\n", p_mgnt_info->tmpNumBssDesc)); /* debug for Dino */ + PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n", + mgnt_info->tmpNumBssDesc); /* @debug for Dino */ - for (index = 0; index < p_mgnt_info->tmpNumBssDesc; index++) { - p_tmp_bss_desc = &(p_mgnt_info->tmpbssDesc[index]); /* Antenna 1 */ - p_test_bss_desc = &(p_mgnt_info->bssDesc[index]); /* Antenna 2 */ + for (index = 0; index < mgnt_info->tmpNumBssDesc; index++) { + p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* @Antenna 1 */ + p_test_bss_desc = &mgnt_info->bssDesc[index]; /* @Antenna 2 */ if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): ERROR!! This shall not happen.\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: ERROR!! This shall not happen.\n", + __func__); continue; } - if (p_dm_odm->support_ic_type != ODM_RTL8723B) { + if (dm->support_ic_type != ODM_RTL8723B) { if (p_tmp_bss_desc->ChannelNumber == scan_channel) { if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Compare scan entry: score++\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score++\n", __func__); RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); + PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); score++; PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS)); } else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link: Compare scan entry: score--\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score--\n", __func__); RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); + PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); score--; } else { if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) { RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("The 2nd Antenna didn't get this AP\n\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_DBG(dm, DBG_ANT_DIV, "The 2nd Antenna didn't get this AP\n\n"); } } } - } else { /* 8723B */ + } else { /* @8723B */ if (p_tmp_bss_desc->ChannelNumber == scan_channel) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber)); + PHYDM_DBG(dm, DBG_ANT_DIV, "channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber); if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */ counter++; tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower); power_diff = power_diff + tmp_power_diff; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf); + PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf); - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff)); */ +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff); */ +#endif if (tmp_power_diff > max_power_diff) max_power_diff = tmp_power_diff; if (tmp_power_diff < min_power_diff) min_power_diff = tmp_power_diff; - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff)); */ +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff); */ +#endif PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS)); } else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */ counter++; tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower); power_diff = power_diff + tmp_power_diff; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf); + PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf); if (tmp_power_diff > max_power_diff) max_power_diff = tmp_power_diff; if (tmp_power_diff < min_power_diff) min_power_diff = tmp_power_diff; } else { /* Pow(Ant1) = Pow(Ant2) */ if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000)); + PHYDM_DBG(dm, DBG_ANT_DIV, "time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000); if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) { counter++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower)); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), p_tmp_bss_desc->bdSsIdBuf); - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), p_tmp_bss_desc->bdSsIdBuf); + PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf); min_power_diff = 0; } } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000)); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000); } } } } - if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { - if (p_mgnt_info->NumBssDesc != 0 && score < 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("odm_sw_ant_div_check_before_link(): Using ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { + if (mgnt_info->NumBssDesc != 0 && score < 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Using ant(%s)\n", __func__, + (fat_tab->rx_idle_ant == MAIN_ANT) ? + "MAIN_ANT" : "AUX_ANT"); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - ("odm_sw_ant_div_check_before_link(): Remain ant(%s)\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Remain ant(%s)\n", __func__, + (fat_tab->rx_idle_ant == MAIN_ANT) ? + "AUX_ANT" : "MAIN_ANT"); - if (p_dm_fat_table->rx_idle_ant == MAIN_ANT) - odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); + if (fat_tab->rx_idle_ant == MAIN_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); else - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); + odm_update_rx_idle_ant(dm, MAIN_ANT); } - if (IS_5G_WIRELESS_MODE(p_mgnt_info->dot11CurrentWirelessMode)) { - p_dm_swat_table->ant_5g = p_dm_fat_table->rx_idle_ant; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_5g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) { + dm_swat_table->ant_5g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, + "dm_swat_table->ant_5g=%s\n", + (fat_tab->rx_idle_ant == MAIN_ANT) ? + "MAIN_ANT" : "AUX_ANT"); } else { - p_dm_swat_table->ant_2g = p_dm_fat_table->rx_idle_ant; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_swat_table->ant_2g=%s\n", (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + dm_swat_table->ant_2g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, + "dm_swat_table->ant_2g=%s\n", + (fat_tab->rx_idle_ant == MAIN_ANT) ? + "MAIN_ANT" : "AUX_ANT"); } - } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + } else if (dm->support_ic_type == ODM_RTL8723B) { if (counter == 0) { - if (p_dm_odm->dm_swat_table.pre_aux_fail_detec == false) { - p_dm_odm->dm_swat_table.pre_aux_fail_detec = true; - p_dm_odm->dm_swat_table.rssi_ant_dect_result = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n")); + if (dm->dm_swat_table.pre_aux_fail_detec == false) { + dm->dm_swat_table.pre_aux_fail_detec = true; + dm->dm_swat_table.rssi_ant_dect_result = false; + PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n"); - /* 3 [ Scan again ] */ + /* @3 [ Scan again ] */ odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); - PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5); + PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5); return true; } else { /* pre_aux_fail_detec == true */ - /* 2 [ Single Antenna ] */ - p_dm_odm->dm_swat_table.pre_aux_fail_detec = false; - p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter=(( 0 )) , [[ Still cannot find any AP ]]\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); + /* @2 [ Single Antenna ] */ + dm->dm_swat_table.pre_aux_fail_detec = false; + dm->dm_swat_table.rssi_ant_dect_result = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Still cannot find any AP ]]\n"); + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__); } - p_dm_odm->dm_swat_table.aux_fail_detec_counter++; + dm->dm_swat_table.aux_fail_detec_counter++; } else { - p_dm_odm->dm_swat_table.pre_aux_fail_detec = false; + dm->dm_swat_table.pre_aux_fail_detec = false; if (counter == 3) { avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff)); + PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff); } else if (counter >= 4) { avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff)); + PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff); - } else { /* counter==1,2 */ + } else { /* @counter==1,2 */ avg_power_diff = power_diff / counter; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff)); + PHYDM_DBG(dm, DBG_ANT_DIV, "avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff); } - /* 2 [ Retry ] */ - if ((avg_power_diff >= power_target_L) && (avg_power_diff <= power_target_H)) { - p_dm_odm->dm_swat_table.retry_counter++; + /* @2 [ Retry ] */ + if (avg_power_diff >= power_target_L && avg_power_diff <= power_target_H) { + dm->dm_swat_table.retry_counter++; - if (p_dm_odm->dm_swat_table.retry_counter <= 3) { - p_dm_odm->dm_swat_table.rssi_ant_dect_result = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff)); + if (dm->dm_swat_table.retry_counter <= 3) { + dm->dm_swat_table.rssi_ant_dect_result = false; + PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff); - /* 3 [ Scan again ] */ + /* @3 [ Scan again ] */ odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); - PlatformSetTimer(adapter, &p_mgnt_info->ScanTimer, 5); + PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5); return true; } else { - p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( retry_counter > 3 ))\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); + dm->dm_swat_table.rssi_ant_dect_result = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Still Low confidence result ]] (( retry_counter > 3 ))\n"); + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__); } - } - /* 2 [ Dual Antenna ] */ - else if ((p_mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) { - p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; - if (p_dm_odm->dm_swat_table.ANTB_ON == false) { - p_dm_odm->dm_swat_table.ANTA_ON = true; - p_dm_odm->dm_swat_table.ANTB_ON = true; + /* @2 [ Dual Antenna ] */ + else if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) { + dm->dm_swat_table.rssi_ant_dect_result = true; + if (dm->dm_swat_table.ANTB_ON == false) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = true; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Dual antenna\n")); - p_dm_odm->dm_swat_table.dual_ant_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual antenna\n", __func__); + dm->dm_swat_table.dual_ant_counter++; /* set bt coexDM from 1ant coexDM to 2ant coexDM */ BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); - /* 3 [ Init antenna diversity ] */ - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; - odm_ant_div_init(p_dm_odm); + /* @3 [ Init antenna diversity ] */ + dm->support_ability |= ODM_BB_ANT_DIV; + odm_ant_div_init(dm); } - /* 2 [ Single Antenna ] */ + /* @2 [ Single Antenna ] */ else if (avg_power_diff > power_target_H) { - p_dm_odm->dm_swat_table.rssi_ant_dect_result = true; - if (p_dm_odm->dm_swat_table.ANTB_ON == true) { - p_dm_odm->dm_swat_table.ANTA_ON = true; - p_dm_odm->dm_swat_table.ANTB_ON = false; - /* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */ + dm->dm_swat_table.rssi_ant_dect_result = true; + if (dm->dm_swat_table.ANTB_ON == true) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = false; +#if 0 + /* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */ +#endif } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); - p_dm_odm->dm_swat_table.single_ant_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__); + dm->dm_swat_table.single_ant_counter++; } } - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_result=(( %d ))\n",p_dm_odm->dm_swat_table.rssi_ant_dect_result)); */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n", - p_dm_odm->dm_swat_table.dual_ant_counter, p_dm_odm->dm_swat_table.single_ant_counter, p_dm_odm->dm_swat_table.retry_counter, p_dm_odm->dm_swat_table.aux_fail_detec_counter)); - - /* 2 recover the antenna setting */ - - if (p_dm_odm->dm_swat_table.ANTB_ON == false) - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, 0xfff, (p_dm_swat_table->swas_no_link_bk_reg948)); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_result=(( %d )), Recover Reg[948]= (( %x )) \n\n", p_dm_odm->dm_swat_table.rssi_ant_dect_result, p_dm_swat_table->swas_no_link_bk_reg948)); - - +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "is_result=(( %d ))\n",dm->dm_swat_table.rssi_ant_dect_result); */ +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n", + dm->dm_swat_table.dual_ant_counter, + dm->dm_swat_table.single_ant_counter, + dm->dm_swat_table.retry_counter, + dm->dm_swat_table.aux_fail_detec_counter); + + /* @2 recover the antenna setting */ + + if (dm->dm_swat_table.ANTB_ON == false) + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948)); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "is_result=(( %d )), Recover Reg[948]= (( %x ))\n\n", + dm->dm_swat_table.rssi_ant_dect_result, + dm_swat_table->swas_no_link_bk_reg948); } - /* Check state reset to default and wait for next time. */ - p_dm_swat_table->swas_no_link_state = 0; - p_mgnt_info->bScanAntDetect = false; + /* @Check state reset to default and wait for next time. */ + dm_swat_table->swas_no_link_state = 0; + mgnt_info->bScanAntDetect = false; return false; } #else - return false; + return false; #endif return false; } - - - - - -/* 1 [3. PSD method] ========================================================== */ -void -odm_single_dual_antenna_detection_psd( - void *p_dm_void -) +/* @1 [3. PSD method] ========================================================== */ +void odm_single_dual_antenna_detection_psd( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 channel_ori; - u8 initial_gain = 0x36; - u8 tone_idx; - u8 tone_lenth_1 = 7, tone_lenth_2 = 4; - u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56}; - u16 tone_idx_2[4] = {8, 24, 40, 56}; - u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0}; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 channel_ori; + u8 initial_gain = 0x36; + u8 tone_idx; + u8 tone_lenth_1 = 7, tone_lenth_2 = 4; + u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56}; + u16 tone_idx_2[4] = {8, 24, 40, 56}; + u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0}; /* u8 tone_lenth_1=4, tone_lenth_2=2; */ /* u16 tone_idx_1[4]={88, 120, 24, 56}; */ /* u16 tone_idx_2[2]={ 24, 56}; */ /* u32 psd_report_main[6]={0}, psd_report_aux[6]={0}; */ - u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0; - u32 PSD_power_threshold; - u32 main_psd_result = 0, aux_psd_result = 0; - u32 regc50, reg948, regb2c, regc14, reg908; - u32 i = 0, test_num = 8; + u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0; + u32 PSD_power_threshold; + u32 main_psd_result = 0, aux_psd_result = 0; + u32 regc50, reg948, regb2c, regc14, reg908; + u32 i = 0, test_num = 8; - - if (p_dm_odm->support_ic_type != ODM_RTL8723B) + if (dm->support_ic_type != ODM_RTL8723B) return; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_single_dual_antenna_detection_psd()============>\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__); - /* 2 [ Backup Current RF/BB Settings ] */ + /* @2 [ Backup Current RF/BB Settings ] */ - channel_ori = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); - reg948 = odm_get_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD); - regb2c = odm_get_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD); - regc50 = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); - regc14 = odm_get_bb_reg(p_dm_odm, 0xc14, MASKDWORD); - reg908 = odm_get_bb_reg(p_dm_odm, 0x908, MASKDWORD); + channel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); + reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD); + regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD); + regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); + regc14 = odm_get_bb_reg(dm, R_0xc14, MASKDWORD); + reg908 = odm_get_bb_reg(dm, R_0x908, MASKDWORD); - /* 2 [ setting for doing PSD function (CH4)] */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, BIT(24), 0); /* disable whole CCK block */ - odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */ - odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ + /* @2 [ setting for doing PSD function (CH4)] */ + odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* @disable whole CCK block */ + odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */ + odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ /* PHYTXON while loop */ - odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, 0x803); - while (odm_get_bb_reg(p_dm_odm, 0xdf4, BIT(6))) { + odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x803); + while (odm_get_bb_reg(dm, R_0xdf4, BIT(6))) { i++; if (i > 1000000) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "Wait in %s() more than %d times!\n", + __FUNCTION__, i); break; } } - odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, initial_gain); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */ - odm_stall_execution(3000); - + odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain); + odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */ + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable 88c[23:20]=0xf */ + odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */ + ODM_delay_us(3000); - /* 2 [ Doing PSD Function in (CH4)] */ + /* @2 [ Doing PSD Function in (CH4)] */ - /* Antenna A */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n")); - odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x200); - odm_stall_execution(10); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n")); + /* @Antenna A */ + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH4)\n"); + odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200); + ODM_delay_us(10); + PHYDM_DBG(dm, DBG_ANT_DIV, "dbg\n"); for (i = 0; i < test_num; i++) { for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) { - PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_1[tone_idx], initial_gain); - /* if( PSD_report_temp>psd_report_main[tone_idx] ) */ + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain); + /* @if( PSD_report_temp>psd_report_main[tone_idx] ) */ psd_report_main[tone_idx] += PSD_report_temp; } } - /* Antenna B */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n")); - odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x280); - odm_stall_execution(10); + /* @Antenna B */ + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH4)\n"); + odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280); + ODM_delay_us(10); for (i = 0; i < test_num; i++) { for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) { - PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_1[tone_idx], initial_gain); - /* if( PSD_report_temp>psd_report_aux[tone_idx] ) */ + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain); + /* @if( PSD_report_temp>psd_report_aux[tone_idx] ) */ psd_report_aux[tone_idx] += PSD_report_temp; } } - /* 2 [ Doing PSD Function in (CH8)] */ + /* @2 [ Doing PSD Function in (CH8)] */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ - odm_stall_execution(3000); + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable 88c[23:20]=0x0 */ + ODM_delay_us(3000); - odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, initial_gain); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */ + odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain); + odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ - odm_stall_execution(3000); + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable 88c[23:20]=0xf */ + ODM_delay_us(3000); - /* Antenna A */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n")); - odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x200); - odm_stall_execution(10); + /* @Antenna A */ + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH8)\n"); + odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200); + ODM_delay_us(10); for (i = 0; i < test_num; i++) { for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) { - PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_2[tone_idx], initial_gain); - /* if( PSD_report_temp>psd_report_main[tone_idx] ) */ + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain); + /* @if( PSD_report_temp>psd_report_main[tone_idx] ) */ psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp; } } - /* Antenna B */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n")); - odm_set_bb_reg(p_dm_odm, 0x948, 0xfff, 0x280); - odm_stall_execution(10); + /* @Antenna B */ + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH8)\n"); + odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280); + ODM_delay_us(10); for (i = 0; i < test_num; i++) { for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) { - PSD_report_temp = phydm_get_psd_data(p_dm_odm, tone_idx_2[tone_idx], initial_gain); - /* if( PSD_report_temp>psd_report_aux[tone_idx] ) */ + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain); + /* @if( PSD_report_temp>psd_report_aux[tone_idx] ) */ psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp; } } - /* 2 [ Calculate Result ] */ + /* @2 [ Calculate Result ] */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL)\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "\nMain PSD Result: (ALL)\n"); for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_main[tone_idx])); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), + psd_report_main[tone_idx]); main_psd_result += psd_report_main[tone_idx]; if (psd_report_main[tone_idx] > max_psd_report_main) max_psd_report_main = psd_report_main[tone_idx]; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", main_psd_result)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", max_psd_report_main)); - + PHYDM_DBG(dm, DBG_ANT_DIV, + "--------------------------- \nTotal_Main= (( %d ))\n", + main_psd_result); + PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n", + max_psd_report_main); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL)\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "\nAux PSD Result: (ALL)\n"); for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_aux[tone_idx])); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), + psd_report_aux[tone_idx]); aux_psd_result += psd_report_aux[tone_idx]; if (psd_report_aux[tone_idx] > max_psd_report_aux) max_psd_report_aux = psd_report_aux[tone_idx]; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", aux_psd_result)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", max_psd_report_aux)); - - /* main_psd_result=main_psd_result-max_psd_report_main; */ - /* aux_psd_result=aux_psd_result-max_psd_report_aux; */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "--------------------------- \nTotal_Aux= (( %d ))\n", + aux_psd_result); + PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n", + max_psd_report_aux); + + /* @main_psd_result=main_psd_result-max_psd_report_main; */ + /* @aux_psd_result=aux_psd_result-max_psd_report_aux; */ PSD_power_threshold = (main_psd_result * 7) >> 3; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", main_psd_result, aux_psd_result, PSD_power_threshold)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", + main_psd_result, aux_psd_result, PSD_power_threshold); - /* 3 [ Dual Antenna ] */ + /* @3 [ Dual Antenna ] */ if (aux_psd_result >= PSD_power_threshold) { - if (p_dm_odm->dm_swat_table.ANTB_ON == false) { - p_dm_odm->dm_swat_table.ANTA_ON = true; - p_dm_odm->dm_swat_table.ANTB_ON = true; + if (dm->dm_swat_table.ANTB_ON == false) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = true; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Dual antenna\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_sw_ant_div_check_before_link(): Dual antenna\n"); +#if 0 /* set bt coexDM from 1ant coexDM to 2ant coexDM */ - /* bt_set_bt_coex_ant_num(p_adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */ + /* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */ +#endif - /* Init antenna diversity */ - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; - odm_ant_div_init(p_dm_odm); + /* @Init antenna diversity */ + dm->support_ability |= ODM_BB_ANT_DIV; + odm_ant_div_init(dm); } - /* 3 [ Single Antenna ] */ + /* @3 [ Single Antenna ] */ else { - if (p_dm_odm->dm_swat_table.ANTB_ON == true) { - p_dm_odm->dm_swat_table.ANTA_ON = true; - p_dm_odm->dm_swat_table.ANTB_ON = false; + if (dm->dm_swat_table.ANTB_ON == true) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = false; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_sw_ant_div_check_before_link(): Single antenna\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_sw_ant_div_check_before_link(): Single antenna\n"); } - /* 2 [ Recover all parameters ] */ + /* @2 [ Recover all parameters ] */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori); - odm_set_bb_reg(p_dm_odm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ - odm_set_bb_reg(p_dm_odm, 0xc50, 0x7f, regc50); + odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori); + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable 88c[23:20]=0x0 */ + odm_set_bb_reg(dm, R_0xc50, 0x7f, regc50); - odm_set_bb_reg(p_dm_odm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); - odm_set_bb_reg(p_dm_odm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); - odm_set_bb_reg(p_dm_odm, REG_FPGA0_RFMOD, BIT(24), 1); /* enable whole CCK block */ - odm_write_1byte(p_dm_odm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */ - odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, regc14); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */ - odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, reg908); + odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* @enable whole CCK block */ + odm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */ + odm_set_bb_reg(dm, R_0xc14, MASKDWORD, regc14); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */ + odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908); return; - } -#endif -void -odm_sw_ant_detect_init( - void *p_dm_void -) +void odm_sw_ant_detect_init(void *dm_void) { -#if (defined(CONFIG_ANT_DETECTION)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - - /* p_dm_swat_table->pre_antenna = MAIN_ANT; */ - /* p_dm_swat_table->cur_antenna = MAIN_ANT; */ - p_dm_swat_table->swas_no_link_state = 0; - p_dm_swat_table->pre_aux_fail_detec = false; - p_dm_swat_table->swas_no_link_bk_reg948 = 0xff; - - #if (CONFIG_PSD_TOOL == 1) - phydm_psd_init(p_dm_odm); - #endif +#if (RTL8723B_SUPPORT == 1) + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + + if (dm->support_ic_type != ODM_RTL8723B) + return; + + /* @dm_swat_table->pre_antenna = MAIN_ANT; */ + /* @dm_swat_table->cur_antenna = MAIN_ANT; */ + dm_swat_table->swas_no_link_state = 0; + dm_swat_table->pre_aux_fail_detec = false; + dm_swat_table->swas_no_link_bk_reg948 = 0xff; + +#ifdef CONFIG_PSD_TOOL + phydm_psd_init(dm); +#endif #endif } +#endif + diff --git a/hal/phydm/phydm_antdect.h b/hal/phydm/phydm_antdect.h index 6d21046..f7fc75f 100644 --- a/hal/phydm/phydm_antdect.h +++ b/hal/phydm/phydm_antdect.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,88 +8,71 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -#ifndef __PHYDMANTDECT_H__ -#define __PHYDMANTDECT_H__ +#ifndef __PHYDMANTDECT_H__ +#define __PHYDMANTDECT_H__ -#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/ +#define ANTDECT_VERSION "2.1" #if (defined(CONFIG_ANT_DETECTION)) -/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */ -/* ANT Test */ -#define ANTTESTALL 0x00 /*ant A or B will be Testing*/ -#define ANTTESTA 0x01 /*ant A will be Testing*/ -#define ANTTESTB 0x02 /*ant B will be testing*/ - -#define MAX_ANTENNA_DETECTION_CNT 10 +/* @#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */ +/* @ANT Test */ +#define ANTTESTALL 0x00 /*@ant A or B will be Testing*/ +#define ANTTESTA 0x01 /*@ant A will be Testing*/ +#define ANTTESTB 0x02 /*@ant B will be testing*/ +#define MAX_ANTENNA_DETECTION_CNT 10 struct _ANT_DETECTED_INFO { - boolean is_ant_detected; - u32 db_for_ant_a; - u32 db_for_ant_b; - u32 db_for_ant_o; + boolean is_ant_detected; + u32 db_for_ant_a; + u32 db_for_ant_b; + u32 db_for_ant_o; }; - -enum dm_swas_e { +enum dm_swas { antenna_a = 1, antenna_b = 2, antenna_max = 3, }; +/* @1 [1. Single Tone method] =================================================== */ - -/* 1 [1. Single Tone method] =================================================== */ - - - -void -odm_single_dual_antenna_default_setting( - void *p_dm_void -); +void odm_single_dual_antenna_default_setting( + void *dm_void); boolean odm_single_dual_antenna_detection( - void *p_dm_void, - u8 mode -); + void *dm_void, + u8 mode); -/* 1 [2. Scan AP RSSI method] ================================================== */ +/* @1 [2. Scan AP RSSI method] ================================================== */ -#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link +#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link boolean odm_sw_ant_div_check_before_link( - void *p_dm_void -); + void *dm_void); +/* @1 [3. PSD method] ========================================================== */ +void odm_single_dual_antenna_detection_psd( + void *dm_void); - -/* 1 [3. PSD method] ========================================================== */ - - -void -odm_single_dual_antenna_detection_psd( - void *p_dm_void -); - +void odm_sw_ant_detect_init(void *dm_void); #endif - -void -odm_sw_ant_detect_init( - void *p_dm_void -); - - #endif diff --git a/hal/phydm/phydm_antdiv.c b/hal/phydm/phydm_antdiv.c index ef41eec..3796825 100644 --- a/hal/phydm/phydm_antdiv.c +++ b/hal/phydm/phydm_antdiv.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,359 +8,447 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -/* ************************************************************ +/************************************************************* * include files - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" -/* ****************************************************** +/******************************************************* * when antenna test utility is on or some testing need to disable antenna diversity * call this function to disable all ODM related mechanisms which will switch antenna. - * ****************************************************** */ -void -odm_stop_antenna_switch_dm( - void *p_dm_void -) + ***************************************************** + */ +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY +void odm_stop_antenna_switch_dm(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - /* disable ODM antenna diversity */ - p_dm_odm->support_ability &= ~ODM_BB_ANT_DIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("STOP Antenna Diversity\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + /* @disable ODM antenna diversity */ + dm->support_ability &= ~ODM_BB_ANT_DIV; + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + PHYDM_DBG(dm, DBG_ANT_DIV, "STOP Antenna Diversity\n"); } -void -phydm_enable_antenna_diversity( - void *p_dm_void -) +void phydm_enable_antenna_diversity(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AntDiv is enabled & Re-Init AntDiv\n")); - odm_antenna_diversity_init(p_dm_odm); + dm->support_ability |= ODM_BB_ANT_DIV; + dm->antdiv_select = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "AntDiv is enabled & Re-Init AntDiv\n"); + odm_antenna_diversity_init(dm); } -void -odm_set_ant_config( - void *p_dm_void, - u8 ant_setting /* 0=A, 1=B, 2=C, .... */ -) +void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C, .... */) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - if (ant_setting == 0) /* ant A*/ - odm_set_bb_reg(p_dm_odm, 0x948, MASKDWORD, 0x00000000); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type == ODM_RTL8723B) { + if (ant_setting == 0) /* @ant A*/ + odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000000); else if (ant_setting == 1) - odm_set_bb_reg(p_dm_odm, 0x948, MASKDWORD, 0x00000280); - } else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - if (ant_setting == 0) /* ant A*/ - odm_set_bb_reg(p_dm_odm, 0x948, MASKLWORD, 0x0000); + odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000280); + } else if (dm->support_ic_type == ODM_RTL8723D) { + if (ant_setting == 0) /* @ant A*/ + odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0000); else if (ant_setting == 1) - odm_set_bb_reg(p_dm_odm, 0x948, MASKLWORD, 0x0280); + odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0280); } } /* ****************************************************** */ - -void -odm_sw_ant_div_rest_after_link( - void *p_dm_void -) +void odm_sw_ant_div_rest_after_link(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u32 i; - - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { - - p_dm_swat_table->try_flag = SWAW_STEP_INIT; - p_dm_swat_table->rssi_trying = 0; - p_dm_swat_table->double_chk_flag = 0; +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 i; - p_dm_fat_table->rx_idle_ant = MAIN_ANT; + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->rssi_trying = 0; + dm_swat_table->double_chk_flag = 0; + fat_tab->rx_idle_ant = MAIN_ANT; -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) - phydm_antdiv_reset_statistic(p_dm_odm, i); -#endif + phydm_antdiv_reset_statistic(dm, i); + } +#endif +} +void phydm_n_on_off(void *dm_void, u8 swch, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + if (path == ANT_PATH_A) { + odm_set_bb_reg(dm, R_0xc50, BIT(7), swch); + } else if (path == ANT_PATH_B) { + odm_set_bb_reg(dm, R_0xc58, BIT(7), swch); + } else if (path == ANT_PATH_AB) { + odm_set_bb_reg(dm, R_0xc50, BIT(7), swch); + odm_set_bb_reg(dm, R_0xc58, BIT(7), swch); } + odm_set_bb_reg(dm, R_0xa00, BIT(15), swch); +#if (RTL8723D_SUPPORT == 1) + /*@Mingzhi 2017-05-08*/ + if (dm->support_ic_type == ODM_RTL8723D) { + if (swch == ANTDIV_ON) { + odm_set_bb_reg(dm, R_0xce0, BIT(1), 1); + odm_set_bb_reg(dm, R_0x948, BIT(6), 1); + /*@1:HW ctrl 0:SW ctrl*/ + } else { + odm_set_bb_reg(dm, R_0xce0, BIT(1), 0); + odm_set_bb_reg(dm, R_0x948, BIT(6), 0); + /*@1:HW ctrl 0:SW ctrl*/ + } + } +#endif } - -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) -void -phydm_antdiv_reset_statistic( - void *p_dm_void, - u32 macid -) +void phydm_ac_on_off(void *dm_void, u8 swch, u8 path) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - - p_dm_fat_table->main_ant_sum[macid] = 0; - p_dm_fat_table->aux_ant_sum[macid] = 0; - p_dm_fat_table->main_ant_cnt[macid] = 0; - p_dm_fat_table->aux_ant_cnt[macid] = 0; - p_dm_fat_table->main_ant_sum_cck[macid] = 0; - p_dm_fat_table->aux_ant_sum_cck[macid] = 0; - p_dm_fat_table->main_ant_cnt_cck[macid] = 0; - p_dm_fat_table->aux_ant_cnt_cck[macid] = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + if (dm->support_ic_type & ODM_RTL8812) { + odm_set_bb_reg(dm, R_0xc50, BIT(7), swch); + /* OFDM AntDiv function block enable */ + odm_set_bb_reg(dm, R_0xa00, BIT(15), swch); + /* @CCK AntDiv function block enable */ + } else if (dm->support_ic_type & ODM_RTL8822B) { + odm_set_bb_reg(dm, R_0x800, BIT(25), swch); + odm_set_bb_reg(dm, R_0xa00, BIT(15), swch); + if (path == ANT_PATH_A) { + odm_set_bb_reg(dm, R_0xc50, BIT(7), swch); + } else if (path == ANT_PATH_B) { + odm_set_bb_reg(dm, R_0xe50, BIT(7), swch); + } else if (path == ANT_PATH_AB) { + odm_set_bb_reg(dm, R_0xc50, BIT(7), swch); + odm_set_bb_reg(dm, R_0xe50, BIT(7), swch); + } + } else { + odm_set_bb_reg(dm, R_0x8d4, BIT(24), swch); + /* OFDM AntDiv function block enable */ + + if (dm->cut_version >= ODM_CUT_C && + dm->support_ic_type == ODM_RTL8821 && + dm->ant_div_type != S0S1_SW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n", + (swch == ANTDIV_ON) ? "ON" : "OFF"); + odm_set_bb_reg(dm, R_0x800, BIT(25), swch); + odm_set_bb_reg(dm, R_0xa00, BIT(15), swch); + /* @CCK AntDiv function block enable */ + } else if (dm->support_ic_type == ODM_RTL8821C) { + PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n", + (swch == ANTDIV_ON) ? "ON" : "OFF"); + odm_set_bb_reg(dm, R_0x800, BIT(25), swch); + odm_set_bb_reg(dm, R_0xa00, BIT(15), swch); + /* @CCK AntDiv function block enable */ + } + } } -void -odm_ant_div_on_off( - void *p_dm_void, - u8 swch -) +void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - if (p_dm_fat_table->ant_div_on_off != swch) { - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) + if (fat_tab->ant_div_on_off != swch) { + if (dm->ant_div_type == S0S1_SW_ANTDIV) return; - if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(7), swch); - odm_set_bb_reg(p_dm_odm, 0xa00, BIT(15), swch); - -#if (RTL8723D_SUPPORT == 1) - /*Mingzhi 2017-05-08*/ - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - if (swch == ANTDIV_ON) { - odm_set_bb_reg(p_dm_odm, 0xce0, BIT(1), 1); - odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 1); /*1:HW ctrl 0:SW ctrl*/ - } else { - odm_set_bb_reg(p_dm_odm, 0xce0, BIT(1), 0); - odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0); /*1:HW ctrl 0:SW ctrl*/ - } - } -#endif - - } else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) { - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(7), swch); /* OFDM AntDiv function block enable */ - odm_set_bb_reg(p_dm_odm, 0xa00, BIT(15), swch); /* CCK AntDiv function block enable */ - } else { - odm_set_bb_reg(p_dm_odm, 0x8D4, BIT(24), swch); /* OFDM AntDiv function block enable */ - - if ((p_dm_odm->cut_version >= ODM_CUT_C) && (p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->ant_div_type != S0S1_SW_ANTDIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); - odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), swch); - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */ - } else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF")); - odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), swch); - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */ - } - } + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "(( Turn %s )) N-Series HW-AntDiv block\n", + (swch == ANTDIV_ON) ? "ON" : "OFF"); + phydm_n_on_off(dm, swch, path); + + } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "(( Turn %s )) AC-Series HW-AntDiv block\n", + (swch == ANTDIV_ON) ? "ON" : "OFF"); + phydm_ac_on_off(dm, swch, path); } } - p_dm_fat_table->ant_div_on_off = swch; - + fat_tab->ant_div_on_off = swch; } -void -phydm_fast_training_enable( - void *p_dm_void, - u8 swch -) +void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 enable; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 enable; - if (swch == FAT_ON) - enable = 1; + if (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT) + enable = (swch == TX_BY_DESC) ? 1 : 0; else - enable = 0; + enable = 0; /*@Force TX by Reg*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fast ant Training_en = ((%d))\n", enable)); - - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - odm_set_bb_reg(p_dm_odm, 0xe08, BIT(16), enable); /*enable fast training*/ - /**/ - } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_bb_reg(p_dm_odm, 0xB34, BIT(28), enable); /*enable fast training (path-A)*/ - /*odm_set_bb_reg(p_dm_odm, 0xB34, BIT(29), enable);*/ /*enable fast training (path-B)*/ - } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) { - odm_set_bb_reg(p_dm_odm, 0x900, BIT(19), enable); /*enable fast training */ - /**/ + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) { + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) + odm_set_bb_reg(dm, R_0x80c, BIT(21), enable); + else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) + odm_set_bb_reg(dm, R_0x900, BIT(18), enable); + + PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv] TX_Ant_BY (( %s ))\n", + (enable == TX_BY_DESC) ? "DESC" : "REG"); } } -void -phydm_keep_rx_ack_ant_by_tx_ant_time( - void *p_dm_void, - u32 time -) +void phydm_antdiv_reset_statistic( + void *dm_void, + u32 macid) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/ - if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { - - odm_set_bb_reg(p_dm_odm, 0xE20, BIT(23) | BIT(22) | BIT(21) | BIT(20), time); - /**/ - } else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { - - odm_set_bb_reg(p_dm_odm, 0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), time); - /**/ - } + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + fat_tab->main_ant_sum[macid] = 0; + fat_tab->aux_ant_sum[macid] = 0; + fat_tab->main_ant_cnt[macid] = 0; + fat_tab->aux_ant_cnt[macid] = 0; + fat_tab->main_ant_sum_cck[macid] = 0; + fat_tab->aux_ant_sum_cck[macid] = 0; + fat_tab->main_ant_cnt_cck[macid] = 0; + fat_tab->aux_ant_cnt_cck[macid] = 0; } -void -odm_tx_by_tx_desc_or_reg( - void *p_dm_void, - u8 swch -) +void phydm_fast_training_enable( + void *dm_void, + u8 swch) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 enable; - if (p_dm_fat_table->b_fix_tx_ant == NO_FIX_TX_ANT) - enable = (swch == TX_BY_DESC) ? 1 : 0; + if (swch == FAT_ON) + enable = 1; else - enable = 0;/*Force TX by Reg*/ + enable = 0; - if (p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) { - if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) - odm_set_bb_reg(p_dm_odm, 0x80c, BIT(21), enable); - else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) - odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), enable); + PHYDM_DBG(dm, DBG_ANT_DIV, "Fast ant Training_en = ((%d))\n", enable); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv] TX_Ant_BY (( %s ))\n", (enable == TX_BY_DESC) ? "DESC" : "REG")); + if (dm->support_ic_type == ODM_RTL8188E) { + odm_set_bb_reg(dm, R_0xe08, BIT(16), enable); /*@enable fast training*/ + } else if (dm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(dm, R_0xb34, BIT(28), enable); /*@enable fast training (path-A)*/ +#if 0 + /*odm_set_bb_reg(dm, R_0xb34, BIT(29), enable);*/ /*enable fast training (path-B)*/ +#endif + } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) { + odm_set_bb_reg(dm, R_0x900, BIT(19), enable); /*@enable fast training */ } } -void -odm_update_rx_idle_ant( - void *p_dm_void, - u8 ant -) +void phydm_keep_rx_ack_ant_by_tx_ant_time( + void *dm_void, + u32 time) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/ + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) + odm_set_bb_reg(dm, R_0xe20, BIT(23) | BIT(22) | BIT(21) | BIT(20), time); + else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) + odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), time); +} + +void odm_update_rx_idle_ant( + void *dm_void, + u8 ant) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u32 default_ant, optional_ant, value32, default_tx_ant; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 default_ant, optional_ant, value32, default_tx_ant; - if (p_dm_fat_table->rx_idle_ant != ant) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + if (fat_tab->rx_idle_ant != ant) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] rx_idle_ant =%s\n", + (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); - if (!(p_dm_odm->support_ic_type & ODM_RTL8723B)) - p_dm_fat_table->rx_idle_ant = ant; + if (!(dm->support_ic_type & ODM_RTL8723B)) + fat_tab->rx_idle_ant = ant; if (ant == MAIN_ANT) { - default_ant = ANT1_2G; - optional_ant = ANT2_2G; + default_ant = ANT1_2G; + optional_ant = ANT2_2G; } else { - default_ant = ANT2_2G; - optional_ant = ANT1_2G; + default_ant = ANT2_2G; + optional_ant = ANT1_2G; } - if (p_dm_fat_table->b_fix_tx_ant != NO_FIX_TX_ANT) - default_tx_ant = (p_dm_fat_table->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1; + if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT) + default_tx_ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1; else default_tx_ant = default_ant; - if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(5) | BIT4 | BIT3, default_ant); /* Default RX */ - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(8) | BIT7 | BIT6, optional_ant); /* Optional RX */ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /* Default TX */ + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { + if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) { + odm_set_bb_reg(dm, R_0xb38, BIT(5) | BIT(4) | BIT(3), default_ant); /* @Default RX */ + odm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), optional_ant); /* Optional RX */ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /* @Default TX */ } #if (RTL8723B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - - value32 = odm_get_bb_reg(p_dm_odm, 0x948, 0xFFF); + else if (dm->support_ic_type == ODM_RTL8723B) { + value32 = odm_get_bb_reg(dm, R_0x948, 0xFFF); if (value32 != 0x280) - odm_update_rx_idle_ant_8723b(p_dm_odm, ant, default_ant, optional_ant); + odm_update_rx_idle_ant_8723b(dm, ant, default_ant, optional_ant); else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n"); } #endif -#if (RTL8723D_SUPPORT == 1) /*Mingzhi 2017-05-08*/ - else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - phydm_set_tx_ant_pwr_8723d(p_dm_odm, ant); - odm_update_rx_idle_ant_8723d(p_dm_odm, ant, default_ant, optional_ant); + +#if (RTL8723D_SUPPORT == 1) /*@Mingzhi 2017-05-08*/ + else if (dm->support_ic_type == ODM_RTL8723D) { + phydm_set_tx_ant_pwr_8723d(dm, ant); + odm_update_rx_idle_ant_8723d(dm, ant, default_ant, optional_ant); } -#endif - else { /*8188E & 8188F*/ -#if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - phydm_update_rx_idle_antenna_8188F(p_dm_odm, default_ant); +#endif + + else { /*@8188E & 8188F*/ +/*@ + if (dm->support_ic_type == ODM_RTL8723D) { +#if (RTL8723D_SUPPORT == 1) + phydm_set_tx_ant_pwr_8723d(dm, ant); +#endif } +*/ +#if (RTL8188F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188F) + phydm_update_rx_idle_antenna_8188F(dm, default_ant); #endif - odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /*Default RX*/ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /*Optional RX*/ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_tx_ant); /*Default TX*/ + odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*@Default RX*/ + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_tx_ant); /*@Default TX*/ } - } else if (p_dm_odm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { - u16 value16 = odm_read_2byte(p_dm_odm, ODM_REG_TRMUX_11AC + 2); - /* */ - /* 2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt */ - /* incorrect 0xc08 bit0-15 .We still not know why it is changed. */ - /* */ + } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { + u16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2); + /* @2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt */ + /* @incorrect 0xc08 bit0-15 .We still not know why it is changed. */ value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3)); value16 |= ((u16)default_ant << 3); value16 |= ((u16)optional_ant << 6); - value16 |= ((u16)default_ant << 9); - odm_write_2byte(p_dm_odm, ODM_REG_TRMUX_11AC + 2, value16); + value16 |= ((u16)default_tx_ant << 9); + odm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16); #if 0 - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(21) | BIT20 | BIT19, default_ant); /* Default RX */ - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(24) | BIT23 | BIT22, optional_ant); /* Optional RX */ - odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(27) | BIT26 | BIT25, default_ant); /* Default TX */ + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(21) | BIT20 | BIT19, default_ant); /* @Default RX */ + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(24) | BIT23 | BIT22, optional_ant); /* Optional RX */ + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(27) | BIT26 | BIT25, default_ant); /* @Default TX */ #endif } - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(7) | BIT6, default_tx_ant); /*PathA Resp Tx*/ - /**/ + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) + odm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant); /*PathA Resp Tx*/ + else if (dm->support_ic_type == ODM_RTL8188E) + odm_set_mac_reg(dm, R_0x6d8, BIT(7) | BIT(6), default_tx_ant); /*PathA Resp Tx*/ + else + odm_set_mac_reg(dm, R_0x6d8, BIT(10) | BIT(9) | BIT(8), default_tx_ant); /*PathA Resp Tx*/ + + } else { /* @fat_tab->rx_idle_ant == ant */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Stay in Ori-ant ] rx_idle_ant =%s\n", + (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + fat_tab->rx_idle_ant = ant; + } +} + +void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 default_ant, optional_ant, value32, default_tx_ant; + + if (fat_tab->rx_idle_ant2 != ant) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant2 ] rx_idle_ant2 =%s\n", + (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + if (ant == MAIN_ANT) { + default_ant = ANT1_2G; + optional_ant = ANT2_2G; } else { - odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(10) | BIT9 | BIT8, default_tx_ant); /*PathA Resp Tx*/ - /**/ + default_ant = ANT2_2G; + optional_ant = ANT1_2G; + } + + if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT) + default_tx_ant = (fat_tab->b_fix_tx_ant == + FIX_TX_AT_MAIN) ? 0 : 1; + else + default_tx_ant = default_ant; + if (dm->support_ic_type & ODM_RTL8822B) { + u16 v16 = odm_read_2byte(dm, ODM_REG_ANT_11AC_B + 2); + + v16 &= ~(0xff8);/*0xE08[11:3]*/ + v16 |= ((u16)default_ant << 3); + v16 |= ((u16)optional_ant << 6); + v16 |= ((u16)default_tx_ant << 9); + odm_write_2byte(dm, ODM_REG_ANT_11AC_B + 2, v16); + odm_set_mac_reg(dm, R_0x6d8, 0x38, default_tx_ant); + /*PathB Resp Tx*/ } + } else { + /* fat_tab->rx_idle_ant2 == ant */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[Stay Ori Ant] rx_idle_ant2 = %s\n", + (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + fat_tab->rx_idle_ant2 = ant; + } +} + +void phydm_set_antdiv_val( + void *dm_void, + u32 *val_buf, + u8 val_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; - } else { /* p_dm_fat_table->rx_idle_ant == ant */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - p_dm_fat_table->rx_idle_ant = ant; + if (val_len != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][antdiv]Need val_len=1\n"); + return; } + + odm_update_rx_idle_ant(dm, (u8)(*val_buf)); } -void -odm_update_tx_ant( - void *p_dm_void, - u8 ant, - u32 mac_id -) +void odm_update_tx_ant( + void *dm_void, + u8 ant, + u32 mac_id) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u8 tx_ant; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 tx_ant; - if (p_dm_fat_table->b_fix_tx_ant != NO_FIX_TX_ANT) - ant = (p_dm_fat_table->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT; + if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT) + ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT; - if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) + if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) tx_ant = ant; else { if (ant == MAIN_ANT) @@ -369,597 +457,606 @@ odm_update_tx_ant( tx_ant = ANT2_2G; } - p_dm_fat_table->antsel_a[mac_id] = tx_ant & BIT(0); - p_dm_fat_table->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1; - p_dm_fat_table->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Set TX-DESC value]: mac_id:(( %d )), tx_ant = (( %s ))\n", mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",p_dm_fat_table->antsel_c[mac_id] , p_dm_fat_table->antsel_b[mac_id] , p_dm_fat_table->antsel_a[mac_id] )); */ + fat_tab->antsel_a[mac_id] = tx_ant & BIT(0); + fat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1; + fat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Set TX-DESC value]: mac_id:(( %d )), tx_ant = (( %s ))\n", + mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=(( 3'b%d%d%d ))\n",fat_tab->antsel_c[mac_id] , fat_tab->antsel_b[mac_id] , fat_tab->antsel_a[mac_id] ); */ +#endif } #ifdef BEAMFORMING_SUPPORT #if (DM_ODM_SUPPORT_TYPE == ODM_AP) -void -odm_bdc_init( - void *p_dm_void -) +void odm_bdc_init( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[ BDC Initialization......]\n")); - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - p_dm_bdc_table->bdc_mode = BDC_MODE_NULL; - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->bd_ccoex_type_wbfer = 0; - p_dm_odm->bdc_holdstate = 0xff; - - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_bb_reg(p_dm_odm, 0xd7c, 0x0FFFFFFF, 0x1081008); - odm_set_bb_reg(p_dm_odm, 0xd80, 0x0FFFFFFF, 0); - } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - odm_set_bb_reg(p_dm_odm, 0x9b0, 0x0FFFFFFF, 0x1081008); /* 0x9b0[30:0] = 01081008 */ - odm_set_bb_reg(p_dm_odm, 0x9b4, 0x0FFFFFFF, 0); /* 0x9b4[31:0] = 00000000 */ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "\n[ BDC Initialization......]\n"); + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + dm_bdc_table->bdc_mode = BDC_MODE_NULL; + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->bd_ccoex_type_wbfer = 0; + dm->bdc_holdstate = 0xff; + + if (dm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(dm, R_0xd7c, 0x0FFFFFFF, 0x1081008); + odm_set_bb_reg(dm, R_0xd80, 0x0FFFFFFF, 0); + } else if (dm->support_ic_type == ODM_RTL8812) { + odm_set_bb_reg(dm, R_0x9b0, 0x0FFFFFFF, 0x1081008); /* @0x9b0[30:0] = 01081008 */ + odm_set_bb_reg(dm, R_0x9b4, 0x0FFFFFFF, 0); /* @0x9b4[31:0] = 00000000 */ } - } - -void -odm_CSI_on_off( - void *p_dm_void, - u8 CSI_en -) +void odm_CSI_on_off( + void *dm_void, + u8 CSI_en) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (CSI_en == CSI_ON) { - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_mac_reg(p_dm_odm, 0xd84, BIT(11), 1); /* 0xd84[11]=1 */ - } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - odm_set_mac_reg(p_dm_odm, 0x9b0, BIT(31), 1); /* 0x9b0[31]=1 */ - } + if (dm->support_ic_type == ODM_RTL8192E) + odm_set_mac_reg(dm, R_0xd84, BIT(11), 1); /* @0xd84[11]=1 */ + else if (dm->support_ic_type == ODM_RTL8812) + odm_set_mac_reg(dm, R_0x9b0, BIT(31), 1); /* @0x9b0[31]=1 */ } else if (CSI_en == CSI_OFF) { - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_mac_reg(p_dm_odm, 0xd84, BIT(11), 0); /* 0xd84[11]=0 */ - } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - odm_set_mac_reg(p_dm_odm, 0x9b0, BIT(31), 0); /* 0x9b0[31]=0 */ - } + if (dm->support_ic_type == ODM_RTL8192E) + odm_set_mac_reg(dm, R_0xd84, BIT(11), 0); /* @0xd84[11]=0 */ + else if (dm->support_ic_type == ODM_RTL8812) + odm_set_mac_reg(dm, R_0x9b0, BIT(31), 0); /* @0x9b0[31]=0 */ } } -void -odm_bd_ccoex_type_with_bfer_client( - void *p_dm_void, - u8 swch -) +void odm_bd_ccoex_type_with_bfer_client( + void *dm_void, + u8 swch) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; - u8 bd_ccoex_type_wbfer; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + u8 bd_ccoex_type_wbfer; if (swch == DIVON_CSIOFF) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 1] {DIV,CSI} ={1,0}\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[BDCcoexType: 1] {DIV,CSI} ={1,0}\n"); bd_ccoex_type_wbfer = 1; - if (bd_ccoex_type_wbfer != p_dm_bdc_table->bd_ccoex_type_wbfer) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - odm_CSI_on_off(p_dm_odm, CSI_OFF); - p_dm_bdc_table->bd_ccoex_type_wbfer = 1; + if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) { + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + odm_CSI_on_off(dm, CSI_OFF); + dm_bdc_table->bd_ccoex_type_wbfer = 1; } } else if (swch == DIVOFF_CSION) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 2] {DIV,CSI} ={0,1}\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[BDCcoexType: 2] {DIV,CSI} ={0,1}\n"); bd_ccoex_type_wbfer = 2; - if (bd_ccoex_type_wbfer != p_dm_bdc_table->bd_ccoex_type_wbfer) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_CSI_on_off(p_dm_odm, CSI_ON); - p_dm_bdc_table->bd_ccoex_type_wbfer = 2; + if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) { + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + odm_CSI_on_off(dm, CSI_ON); + dm_bdc_table->bd_ccoex_type_wbfer = 2; } } } -void -odm_bf_ant_div_mode_arbitration( - void *p_dm_void -) +void odm_bf_ant_div_mode_arbitration( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; - u8 current_bdc_mode; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + u8 current_bdc_mode; #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "\n"); - /* 2 mode 1 */ - if ((p_dm_bdc_table->num_txbfee_client != 0) && (p_dm_bdc_table->num_txbfer_client == 0)) { + /* @2 mode 1 */ + if (dm_bdc_table->num_txbfee_client != 0 && dm_bdc_table->num_txbfer_client == 0) { current_bdc_mode = BDC_MODE_1; - if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { - p_dm_bdc_table->bdc_mode = BDC_MODE_1; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - p_dm_bdc_table->bdc_rx_idle_update_counter = 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode1 ))\n")); + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_1; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + dm_bdc_table->bdc_rx_idle_update_counter = 1; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode1 ))\n"); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode1 ))\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Antdiv + BF coextance mode] : (( Mode1 ))\n"); } - /* 2 mode 2 */ - else if ((p_dm_bdc_table->num_txbfee_client == 0) && (p_dm_bdc_table->num_txbfer_client != 0)) { + /* @2 mode 2 */ + else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client != 0)) { current_bdc_mode = BDC_MODE_2; - if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { - p_dm_bdc_table->bdc_mode = BDC_MODE_2; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - p_dm_bdc_table->bdc_try_flag = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode2 ))\n")); - + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_2; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + dm_bdc_table->bdc_try_flag = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode2 ))\n"); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode2 ))\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Antdiv + BF coextance mode] : (( Mode2 ))\n"); } - /* 2 mode 3 */ - else if ((p_dm_bdc_table->num_txbfee_client != 0) && (p_dm_bdc_table->num_txbfer_client != 0)) { + /* @2 mode 3 */ + else if ((dm_bdc_table->num_txbfee_client != 0) && (dm_bdc_table->num_txbfer_client != 0)) { current_bdc_mode = BDC_MODE_3; - if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { - p_dm_bdc_table->bdc_mode = BDC_MODE_3; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->bdc_rx_idle_update_counter = 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode3 ))\n")); + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_3; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->bdc_rx_idle_update_counter = 1; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode3 ))\n"); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode3 ))\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Antdiv + BF coextance mode] : (( Mode3 ))\n"); } - /* 2 mode 4 */ - else if ((p_dm_bdc_table->num_txbfee_client == 0) && (p_dm_bdc_table->num_txbfer_client == 0)) { + /* @2 mode 4 */ + else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client == 0)) { current_bdc_mode = BDC_MODE_4; - if (current_bdc_mode != p_dm_bdc_table->bdc_mode) { - p_dm_bdc_table->bdc_mode = BDC_MODE_4; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode4 ))\n")); + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_4; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode4 ))\n"); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance mode] : (( Mode4 ))\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Antdiv + BF coextance mode] : (( Mode4 ))\n"); } #endif - } -void -odm_div_train_state_setting( - void *p_dm_void -) +void odm_div_train_state_setting( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE]\n")); - p_dm_bdc_table->bdc_try_counter = 2; - p_dm_bdc_table->bdc_try_flag = 1; - p_dm_bdc_table->BDC_state = bdc_bfer_train_state; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE]\n"); + dm_bdc_table->bdc_try_counter = 2; + dm_bdc_table->bdc_try_flag = 1; + dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); } -void -odm_bd_ccoex_bfee_rx_div_arbitration( - void *p_dm_void -) +void odm_bd_ccoex_bfee_rx_div_arbitration( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; boolean stop_bf_flag; - u8 bdc_active_mode; - + u8 bdc_active_mode; #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BFee, num_BFer, num_client} = (( %d , %d , %d))\n", p_dm_bdc_table->num_txbfee_client, p_dm_bdc_table->num_txbfer_client, p_dm_bdc_table->num_client)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BF_tars, num_DIV_tars } = (( %d , %d ))\n", p_dm_bdc_table->num_bf_tar, p_dm_bdc_table->num_div_tar)); - - /* 2 [ MIB control ] */ - if (p_dm_odm->bdc_holdstate == 2) { - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); - p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ BF STATE]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "***{ num_BFee, num_BFer, num_client} = (( %d , %d , %d))\n", + dm_bdc_table->num_txbfee_client, + dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client); + PHYDM_DBG(dm, DBG_ANT_DIV, + "***{ num_BF_tars, num_DIV_tars } = (( %d , %d ))\n", + dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar); + + /* @2 [ MIB control ] */ + if (dm->bdc_holdstate == 2) { + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ BF STATE]\n"); return; - } else if (p_dm_odm->bdc_holdstate == 1) { - p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE]\n")); + } else if (dm->bdc_holdstate == 1) { + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n"); return; } - /* ------------------------------------------------------------ */ - - - - /* 2 mode 2 & 3 */ - if (p_dm_bdc_table->bdc_mode == BDC_MODE_2 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n{ Try_flag, Try_counter } = { %d , %d }\n", p_dm_bdc_table->bdc_try_flag, p_dm_bdc_table->bdc_try_counter)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDCcoexType = (( %d )) \n\n", p_dm_bdc_table->bd_ccoex_type_wbfer)); - - /* All Client have Bfer-Cap------------------------------- */ - if (p_dm_bdc_table->num_txbfer_client == p_dm_bdc_table->num_client) { /* BFer STA Only?: yes */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( Yes ))\n")); - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + /* @------------------------------------------------------------ */ + + /* @2 mode 2 & 3 */ + if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "\n{ Try_flag, Try_counter } = { %d , %d }\n", + dm_bdc_table->bdc_try_flag, + dm_bdc_table->bdc_try_counter); + PHYDM_DBG(dm, DBG_ANT_DIV, "BDCcoexType = (( %d ))\n\n", + dm_bdc_table->bd_ccoex_type_wbfer); + + /* @All Client have Bfer-Cap------------------------------- */ + if (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) { /* @BFer STA Only?: yes */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "BFer STA only? (( Yes ))\n"); + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); return; } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( No ))\n")); - /* */ - if (p_dm_bdc_table->is_all_bf_sta_idle == false && p_dm_bdc_table->is_all_div_sta_idle == true) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All DIV-STA are idle, but BF-STA not\n")); - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = bdc_bfer_train_state; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + PHYDM_DBG(dm, DBG_ANT_DIV, + "BFer STA only? (( No ))\n"); + if (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "All DIV-STA are idle, but BF-STA not\n"); + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); return; - } else if (p_dm_bdc_table->is_all_bf_sta_idle == true && p_dm_bdc_table->is_all_div_sta_idle == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All BF-STA are idle, but DIV-STA not\n")); - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + } else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "All BF-STA are idle, but DIV-STA not\n"); + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); return; } /* Select active mode-------------------------------------- */ - if (p_dm_bdc_table->num_bf_tar == 0) { /* Selsect_1, Selsect_2 */ - if (p_dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 1 ))\n")); - p_dm_bdc_table->bdc_active_mode = 1; + if (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1, Selsect_2 */ + if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "Select active mode (( 1 ))\n"); + dm_bdc_table->bdc_active_mode = 1; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 2 ))\n")); - p_dm_bdc_table->bdc_active_mode = 2; + PHYDM_DBG(dm, DBG_ANT_DIV, + "Select active mode (( 2 ))\n"); + dm_bdc_table->bdc_active_mode = 2; } - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); return; } else { /* num_bf_tar > 0 */ - if (p_dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 3 ))\n")); - p_dm_bdc_table->bdc_active_mode = 3; - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = bdc_bfer_train_state; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); + if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "Select active mode (( 3 ))\n"); + dm_bdc_table->bdc_active_mode = 3; + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); return; } else { /* Selsect_4 */ bdc_active_mode = 4; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 4 ))\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "Select active mode (( 4 ))\n"); - if (bdc_active_mode != p_dm_bdc_table->bdc_active_mode) { - p_dm_bdc_table->bdc_active_mode = 4; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to active mode (( 4 )) & return!!!\n")); + if (bdc_active_mode != dm_bdc_table->bdc_active_mode) { + dm_bdc_table->bdc_active_mode = 4; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to active mode (( 4 )) & return!!!\n"); return; } } } #if 1 - if (p_dm_odm->bdc_holdstate == 0xff) { - p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE]\n")); + if (dm->bdc_holdstate == 0xff) { + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n"); return; } #endif - /* Does Client number changed ? ------------------------------- */ - if (p_dm_bdc_table->num_client != p_dm_bdc_table->pre_num_client) { - p_dm_bdc_table->bdc_try_flag = 0; - p_dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE ))\n")); + /* @Does Client number changed ? ------------------------------- */ + if (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) { + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE ))\n"); } - p_dm_bdc_table->pre_num_client = p_dm_bdc_table->num_client; - - if (p_dm_bdc_table->bdc_try_flag == 0) { - /* 2 DIV_TRAIN_STATE (mode 2-0) */ - if (p_dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE) - odm_div_train_state_setting(p_dm_odm); - /* 2 BFer_TRAIN_STATE (mode 2-1) */ - else if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-1. BFer_TRAIN_STATE ]*****\n")); - - /* if(p_dm_bdc_table->num_bf_tar==0) */ - /* { */ - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n")); */ - /* odm_div_train_state_setting( p_dm_odm); */ - /* } */ + dm_bdc_table->pre_num_client = dm_bdc_table->num_client; + + if (dm_bdc_table->bdc_try_flag == 0) { + /* @2 DIV_TRAIN_STATE (mode 2-0) */ + if (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE) + odm_div_train_state_setting(dm); + /* @2 BFer_TRAIN_STATE (mode 2-1) */ + else if (dm_bdc_table->BDC_state == bdc_bfer_train_state) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "*****[2-1. BFer_TRAIN_STATE ]*****\n"); + +#if 0 + /* @if(dm_bdc_table->num_bf_tar==0) */ + /* @{ */ + /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n"); */ + /* odm_div_train_state_setting( dm); */ + /* @} */ /* else */ /* num_bf_tar != 0 */ - /* { */ - p_dm_bdc_table->bdc_try_counter = 2; - p_dm_bdc_table->bdc_try_flag = 1; - p_dm_bdc_table->BDC_state = BDC_DECISION_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n")); - /* } */ + /* @{ */ +#endif + dm_bdc_table->bdc_try_counter = 2; + dm_bdc_table->bdc_try_flag = 1; + dm_bdc_table->BDC_state = BDC_DECISION_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + PHYDM_DBG(dm, DBG_ANT_DIV, + "BF_tars exist? : (( Yes )), [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n"); + /* @} */ } - /* 2 DECISION_STATE (mode 2-2) */ - else if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-2. DECISION_STATE]*****\n")); - /* if(p_dm_bdc_table->num_bf_tar==0) */ - /* { */ + /* @2 DECISION_STATE (mode 2-2) */ + else if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "*****[2-2. DECISION_STATE]*****\n"); +#if 0 + /* @if(dm_bdc_table->num_bf_tar==0) */ + /* @{ */ /* ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */ - /* odm_div_train_state_setting( p_dm_odm); */ - /* } */ + /* odm_div_train_state_setting( dm); */ + /* @} */ /* else */ /* num_bf_tar != 0 */ - /* { */ - if (p_dm_bdc_table->BF_pass == false || p_dm_bdc_table->DIV_pass == false) + /* @{ */ +#endif + if (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false) stop_bf_flag = true; else stop_bf_flag = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, stop_bf_flag } = { %d, %d, %d }\n", p_dm_bdc_table->BF_pass, p_dm_bdc_table->DIV_pass, stop_bf_flag)); - - if (stop_bf_flag == true) { /* DIV_en */ - p_dm_bdc_table->bdc_hold_counter = 10; /* 20 */ - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ stop_bf_flag= ((true)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n")); - } else { /* BF_en */ - p_dm_bdc_table->bdc_hold_counter = 10; /* 20 */ - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); - p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[stop_bf_flag= ((false)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, stop_bf_flag } = { %d, %d, %d }\n", + dm_bdc_table->BF_pass, + dm_bdc_table->DIV_pass, stop_bf_flag); + + if (stop_bf_flag == true) { /* @DIV_en */ + dm_bdc_table->bdc_hold_counter = 10; /* @20 */ + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ stop_bf_flag= ((true)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n"); + } else { /* @BF_en */ + dm_bdc_table->bdc_hold_counter = 10; /* @20 */ + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "[stop_bf_flag= ((false)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n"); } - /* } */ + /* @} */ } - /* 2 BF-HOLD_STATE (mode 2-3) */ - else if (p_dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-3. BF_HOLD_STATE ]*****\n")); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bdc_hold_counter = (( %d ))\n", p_dm_bdc_table->bdc_hold_counter)); - - if (p_dm_bdc_table->bdc_hold_counter == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); - odm_div_train_state_setting(p_dm_odm); + /* @2 BF-HOLD_STATE (mode 2-3) */ + else if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "*****[2-3. BF_HOLD_STATE ]*****\n"); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "bdc_hold_counter = (( %d ))\n", + dm_bdc_table->bdc_hold_counter); + + if (dm_bdc_table->bdc_hold_counter == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); + odm_div_train_state_setting(dm); } else { - p_dm_bdc_table->bdc_hold_counter--; + dm_bdc_table->bdc_hold_counter--; - /* if(p_dm_bdc_table->num_bf_tar==0) */ - /* { */ - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */ - /* odm_div_train_state_setting( p_dm_odm); */ - /* } */ +#if 0 + /* @if(dm_bdc_table->num_bf_tar==0) */ + /* @{ */ + /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); */ + /* odm_div_train_state_setting( dm); */ + /* @} */ /* else */ /* num_bf_tar != 0 */ - /* { */ - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes ))\n")); */ - p_dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVOFF_CSION); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n")); - /* } */ + /* @{ */ + /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( Yes ))\n"); */ +#endif + dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n"); + /* @} */ } - } - /* 2 DIV-HOLD_STATE (mode 2-4) */ - else if (p_dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-4. DIV_HOLD_STATE ]*****\n")); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bdc_hold_counter = (( %d ))\n", p_dm_bdc_table->bdc_hold_counter)); - - if (p_dm_bdc_table->bdc_hold_counter == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); - odm_div_train_state_setting(p_dm_odm); + /* @2 DIV-HOLD_STATE (mode 2-4) */ + else if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "*****[2-4. DIV_HOLD_STATE ]*****\n"); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "bdc_hold_counter = (( %d ))\n", + dm_bdc_table->bdc_hold_counter); + + if (dm_bdc_table->bdc_hold_counter == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); + odm_div_train_state_setting(dm); } else { - p_dm_bdc_table->bdc_hold_counter--; - p_dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; - odm_bd_ccoex_type_with_bfer_client(p_dm_odm, DIVON_CSIOFF); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n")); + dm_bdc_table->bdc_hold_counter--; + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n"); } - } - } else if (p_dm_bdc_table->bdc_try_flag == 1) { - /* 2 Set Training counter */ - if (p_dm_bdc_table->bdc_try_counter > 1) { - p_dm_bdc_table->bdc_try_counter--; - if (p_dm_bdc_table->bdc_try_counter == 1) - p_dm_bdc_table->bdc_try_flag = 0; + } else if (dm_bdc_table->bdc_try_flag == 1) { + /* @2 Set Training counter */ + if (dm_bdc_table->bdc_try_counter > 1) { + dm_bdc_table->bdc_try_counter--; + if (dm_bdc_table->bdc_try_counter == 1) + dm_bdc_table->bdc_try_flag = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training !!\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "Training !!\n"); /* return ; */ } - } - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[end]\n")); - -#endif /* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ - - - - - + PHYDM_DBG(dm, DBG_ANT_DIV, "\n[end]\n"); +#endif /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ } #endif -#endif /* #ifdef BEAMFORMING_SUPPORT */ - +#endif /* @#ifdef BEAMFORMING_SUPPORT */ #if (RTL8188E_SUPPORT == 1) - -void -odm_rx_hw_ant_div_init_88e( - void *p_dm_void -) +void odm_rx_hw_ant_div_init_88e( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 value32; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 value32; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; #if 0 - if (p_dm_odm->mp_mode == true) { - odm_set_bb_reg(p_dm_odm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */ - odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* 1:CG, 0:CS */ + if (*dm->mp_mode == true) { + odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* @disable HW AntDiv */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* @1:CG, 0:CS */ return; } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8188E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n"); - /* MAC setting */ - value32 = odm_get_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); - odm_set_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* @MAC setting */ + value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); + odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ /* Pin Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT8, 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ - odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ - odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */ + odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ + odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */ /* OFDM Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); - /* CCK Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); + /* @CCK Settings */ + odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */ - odm_set_bb_reg(p_dm_odm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001); /* antenna mapping table */ + odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001); /* @antenna mapping table */ - p_dm_fat_table->enable_ctrl_frame_antdiv = 1; + fat_tab->enable_ctrl_frame_antdiv = 1; } -void -odm_trx_hw_ant_div_init_88e( - void *p_dm_void -) +void odm_trx_hw_ant_div_init_88e( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 value32; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 value32; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; #if 0 - if (p_dm_odm->mp_mode == true) { - odm_set_bb_reg(p_dm_odm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT4 | BIT3, 0); /* Default RX (0/1) */ + if (*dm->mp_mode == true) { + odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* @disable HW AntDiv */ + odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT4 | BIT3, 0); /* @Default RX (0/1) */ return; } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV (SPDT)]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8188E AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV (SPDT)]\n"); - /* MAC setting */ - value32 = odm_get_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); - odm_set_mac_reg(p_dm_odm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* @MAC setting */ + value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); + odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ /* Pin Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT8, 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ - odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ - odm_set_bb_reg(p_dm_odm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */ + odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ + odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */ /* OFDM Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); - /* CCK Settings */ - odm_set_bb_reg(p_dm_odm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ - - /* antenna mapping table */ - if (!p_dm_odm->is_mp_chip) { /* testchip */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT(10) | BIT9 | BIT8, 1); /* Reg858[10:8]=3'b001 */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RX_DEFUALT_A_11N, BIT(13) | BIT12 | BIT11, 2); /* Reg858[13:11]=3'b010 */ - } else /* MPchip */ - odm_set_bb_reg(p_dm_odm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/ - - p_dm_fat_table->enable_ctrl_frame_antdiv = 1; + odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); + /* @CCK Settings */ + odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */ + + /* @antenna mapping table */ + if (!dm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */ + odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */ + } else /* @MPchip */ + odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/ + + fat_tab->enable_ctrl_frame_antdiv = 1; } - #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) -void -odm_smart_hw_ant_div_init_88e( - void *p_dm_void -) +void odm_smart_hw_ant_div_init_88e( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 value32, i; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 value32, i; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8188E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n"); #if 0 - if (p_dm_odm->mp_mode == true) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("p_dm_odm->ant_div_type: %d\n", p_dm_odm->ant_div_type)); + if (*dm->mp_mode == true) { + PHYDM_DBG(dm, ODM_COMP_INIT, "dm->ant_div_type: %d\n", + dm->ant_div_type); return; } #endif - p_dm_fat_table->train_idx = 0; - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; + fat_tab->train_idx = 0; + fat_tab->fat_state = FAT_PREPARE_STATE; - p_dm_odm->fat_comb_a = 5; - p_dm_odm->antdiv_intvl = 0x64; /* 100ms */ + dm->fat_comb_a = 5; + dm->antdiv_intvl = 0x64; /* @100ms */ for (i = 0; i < 6; i++) - p_dm_fat_table->bssid[i] = 0; - for (i = 0; i < (p_dm_odm->fat_comb_a) ; i++) { - p_dm_fat_table->ant_sum_rssi[i] = 0; - p_dm_fat_table->ant_rssi_cnt[i] = 0; - p_dm_fat_table->ant_ave_rssi[i] = 0; + fat_tab->bssid[i] = 0; + for (i = 0; i < (dm->fat_comb_a); i++) { + fat_tab->ant_sum_rssi[i] = 0; + fat_tab->ant_rssi_cnt[i] = 0; + fat_tab->ant_ave_rssi[i] = 0; } - /* MAC setting */ - value32 = odm_get_mac_reg(p_dm_odm, 0x4c, MASKDWORD); - odm_set_mac_reg(p_dm_odm, 0x4c, MASKDWORD, value32 | (BIT(23) | BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ - value32 = odm_get_mac_reg(p_dm_odm, 0x7B4, MASKDWORD); - odm_set_mac_reg(p_dm_odm, 0x7b4, MASKDWORD, value32 | (BIT(16) | BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */ + /* @MAC setting */ + value32 = odm_get_mac_reg(dm, R_0x4c, MASKDWORD); + odm_set_mac_reg(dm, R_0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD); + odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */ /* value32 = platform_efio_read_4byte(adapter, 0x7B4); */ /* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18)); */ /* append MACID in reponse packet */ - /* Match MAC ADDR */ - odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, 0); - odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, 0); - - odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT8, 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ - odm_set_bb_reg(p_dm_odm, 0xb2c, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ - odm_set_bb_reg(p_dm_odm, 0xb2c, BIT(31), 0); /* regb2c[31]=1'b1 */ /* output at CS only */ - odm_set_bb_reg(p_dm_odm, 0xca4, MASKDWORD, 0x000000a0); - - /* antenna mapping table */ - if (p_dm_odm->fat_comb_a == 2) { - if (!p_dm_odm->is_mp_chip) { /* testchip */ - odm_set_bb_reg(p_dm_odm, 0x858, BIT(10) | BIT9 | BIT8, 1); /* Reg858[10:8]=3'b001 */ - odm_set_bb_reg(p_dm_odm, 0x858, BIT(13) | BIT12 | BIT11, 2); /* Reg858[13:11]=3'b010 */ - } else { /* MPchip */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 1); - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 2); + /* @Match MAC ADDR */ + odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0); + odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0); + + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ + odm_set_bb_reg(dm, R_0x864, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(dm, R_0xb2c, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(dm, R_0xb2c, BIT(31), 0); /* regb2c[31]=1'b1 */ /* output at CS only */ + odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x000000a0); + + /* @antenna mapping table */ + if (dm->fat_comb_a == 2) { + if (!dm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */ + odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */ + } else { /* @MPchip */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 1); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2); } } else { - if (!p_dm_odm->is_mp_chip) { /* testchip */ - odm_set_bb_reg(p_dm_odm, 0x858, BIT(10) | BIT9 | BIT8, 0); /* Reg858[10:8]=3'b000 */ - odm_set_bb_reg(p_dm_odm, 0x858, BIT(13) | BIT12 | BIT11, 1); /* Reg858[13:11]=3'b001 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(16), 0); - odm_set_bb_reg(p_dm_odm, 0x858, BIT(15) | BIT14, 2); /* (Reg878[0],Reg858[14:15])=3'b010 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(19) | BIT18 | BIT17, 3); /* Reg878[3:1]=3b'011 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(22) | BIT21 | BIT20, 4); /* Reg878[6:4]=3b'100 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(25) | BIT24 | BIT23, 5); /* Reg878[9:7]=3b'101 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(28) | BIT27 | BIT26, 6); /* Reg878[12:10]=3b'110 */ - odm_set_bb_reg(p_dm_odm, 0x878, BIT(31) | BIT30 | BIT29, 7); /* Reg878[15:13]=3b'111 */ - } else { /* MPchip */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 4); /* 0: 3b'000 */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 2); /* 1: 3b'001 */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE2, 0); /* 2: 3b'010 */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE3, 1); /* 3: 3b'011 */ - odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE0, 3); /* 4: 3b'100 */ - odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE1, 5); /* 5: 3b'101 */ - odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE2, 6); /* 6: 3b'110 */ - odm_set_bb_reg(p_dm_odm, 0x918, MASKBYTE3, 255); /* 7: 3b'111 */ + if (!dm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */ + odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */ + odm_set_bb_reg(dm, R_0x878, BIT(16), 0); + odm_set_bb_reg(dm, R_0x858, BIT(15) | BIT(14), 2); /* @(Reg878[0],Reg858[14:15])=3'b010 */ + odm_set_bb_reg(dm, R_0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */ + odm_set_bb_reg(dm, R_0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */ + odm_set_bb_reg(dm, R_0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */ + odm_set_bb_reg(dm, R_0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */ + odm_set_bb_reg(dm, R_0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */ + } else { /* @MPchip */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 4); /* @0: 3b'000 */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2); /* @1: 3b'001 */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE2, 0); /* @2: 3b'010 */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE3, 1); /* @3: 3b'011 */ + odm_set_bb_reg(dm, R_0x918, MASKBYTE0, 3); /* @4: 3b'100 */ + odm_set_bb_reg(dm, R_0x918, MASKBYTE1, 5); /* @5: 3b'101 */ + odm_set_bb_reg(dm, R_0x918, MASKBYTE2, 6); /* @6: 3b'110 */ + odm_set_bb_reg(dm, R_0x918, MASKBYTE3, 255); /* @7: 3b'111 */ } } - /* Default ant setting when no fast training */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, 0); /* Default RX */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, 1); /* Optional RX */ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, 0); /* Default TX */ + /* @Default ant setting when no fast training */ + odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), 0); /* @Default RX */ + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), 0); /* @Default TX */ - /* Enter Traing state */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(2) | BIT1 | BIT0, (p_dm_odm->fat_comb_a - 1)); /* reg864[2:0]=3'd6 */ /* ant combination=reg864[2:0]+1 */ + /* @Enter Traing state */ + odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6 */ /* ant combination=reg864[2:0]+1 */ +#if 0 /* SW Control */ /* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */ /* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */ @@ -967,1034 +1064,1130 @@ odm_smart_hw_ant_div_init_88e( /* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */ /* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */ /* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */ +#endif } #endif -#endif /* #if (RTL8188E_SUPPORT == 1) */ - +#endif /* @#if (RTL8188E_SUPPORT == 1) */ #if (RTL8192E_SUPPORT == 1) -void -odm_rx_hw_ant_div_init_92e( - void *p_dm_void -) +void odm_rx_hw_ant_div_init_92e( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; #if 0 - if (p_dm_odm->mp_mode == true) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */ + if (*dm->mp_mode == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ + odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); /* @1:CG, 0:CS */ return; } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8192E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n"); /* Pin Settings */ - odm_set_bb_reg(p_dm_odm, 0x870, BIT(8), 0);/* reg870[8]=1'b0, */ /* "antsel" is controled by HWs */ - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 1); /* regc50[8]=1'b1 */ /* " CS/CG switching" is controled by HWs */ + odm_set_bb_reg(dm, R_0x870, BIT(8), 0); /* reg870[8]=1'b0, */ /* "antsel" is controled by HWs */ + odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); /* regc50[8]=1'b1 */ /* " CS/CG switching" is controled by HWs */ - /* Mapping table */ - odm_set_bb_reg(p_dm_odm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */ + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */ /* OFDM Settings */ - odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF000, 0x0); /* bias */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */ - /* CCK Settings */ - odm_set_bb_reg(p_dm_odm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ - odm_set_bb_reg(p_dm_odm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ - odm_set_bb_reg(p_dm_odm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */ - odm_set_bb_reg(p_dm_odm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + /* @CCK Settings */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */ #ifdef ODM_EVM_ENHANCE_ANTDIV - /* EVM enhance AntDiv method init---------------------------------------------------------------------- */ - p_dm_fat_table->EVM_method_enable = 0; - p_dm_fat_table->fat_state = NORMAL_STATE_MIAN; - p_dm_odm->antdiv_intvl = 0x64; - odm_set_bb_reg(p_dm_odm, 0x910, 0x3f, 0xf); - p_dm_odm->antdiv_evm_en = 1; - /* p_dm_odm->antdiv_period=1; */ - p_dm_odm->evm_antdiv_period = 3; - + phydm_evm_sw_antdiv_init(dm); #endif - } -void -odm_trx_hw_ant_div_init_92e( - void *p_dm_void -) +void odm_trx_hw_ant_div_init_92e( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if 0 - if (p_dm_odm->mp_mode == true) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */ + if (*dm->mp_mode == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ + odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); /* @1:CG, 0:CS */ return; } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n")); - - /* 3 --RFE pin setting--------- */ - /* [MAC] */ - odm_set_mac_reg(p_dm_odm, 0x38, BIT(11), 1); /* DBG PAD Driving control (GPIO 8) */ - odm_set_mac_reg(p_dm_odm, 0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */ - odm_set_mac_reg(p_dm_odm, 0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */ - /* [BB] */ - odm_set_bb_reg(p_dm_odm, 0x944, BIT(3), 1); /* RFE_buffer */ - odm_set_bb_reg(p_dm_odm, 0x944, BIT(8), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(7) | BIT6, 0x0); /* r_rfe_path_sel_ (RFE_CTRL_3) */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(17) | BIT16, 0x0); /* r_rfe_path_sel_ (RFE_CTRL_8) */ - odm_set_bb_reg(p_dm_odm, 0x944, BIT(31), 0); /* RFE_buffer */ - odm_set_bb_reg(p_dm_odm, 0x92C, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */ - odm_set_bb_reg(p_dm_odm, 0x92C, BIT(8), 1); /* rfe_inv (RFE_CTRL_8) */ - odm_set_bb_reg(p_dm_odm, 0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */ - odm_set_bb_reg(p_dm_odm, 0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */ - /* 3 ------------------------- */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8192E AntDiv_Init => ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n"); + + /* @3 --RFE pin setting--------- */ + /* @[MAC] */ + odm_set_mac_reg(dm, R_0x38, BIT(11), 1); /* @DBG PAD Driving control (GPIO 8) */ + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */ + odm_set_mac_reg(dm, R_0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */ + /* @[BB] */ + odm_set_bb_reg(dm, R_0x944, BIT(3), 1); /* RFE_buffer */ + odm_set_bb_reg(dm, R_0x944, BIT(8), 1); + odm_set_bb_reg(dm, R_0x940, BIT(7) | BIT(6), 0x0); /* r_rfe_path_sel_ (RFE_CTRL_3) */ + odm_set_bb_reg(dm, R_0x940, BIT(17) | BIT(16), 0x0); /* r_rfe_path_sel_ (RFE_CTRL_8) */ + odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer */ + odm_set_bb_reg(dm, R_0x92c, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */ + odm_set_bb_reg(dm, R_0x92c, BIT(8), 1); /* rfe_inv (RFE_CTRL_8) */ + odm_set_bb_reg(dm, R_0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */ + odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */ + /* @3 ------------------------- */ /* Pin Settings */ - odm_set_bb_reg(p_dm_odm, 0xC50, BIT(8), 0); /* path-A */ /* disable CS/CG switch */ + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* path-A */ /* disable CS/CG switch */ #if 0 - /* Let it follows PHY_REG for bit9 setting */ - if (p_dm_odm->priv->pshare->rf_ft_var.use_ext_pa || p_dm_odm->priv->pshare->rf_ft_var.use_ext_lna) - odm_set_bb_reg(p_dm_odm, 0xC50, BIT(9), 1);/* path-A //output at CS */ + /* @Let it follows PHY_REG for bit9 setting */ + if (dm->priv->pshare->rf_ft_var.use_ext_pa || dm->priv->pshare->rf_ft_var.use_ext_lna) + odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); /* path-A output at CS */ else - odm_set_bb_reg(p_dm_odm, 0xC50, BIT(9), 0); /* path-A //output at CG ->normal power */ + odm_set_bb_reg(dm, R_0xc50, BIT(9), 0); /* path-A output at CG ->normal power */ #endif - odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT8, 0); /* path-A */ /* antsel antselb by HW */ - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(10), 0); /* path-A */ /* antsel2 by HW */ + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* path-A*/ /* antsel antselb by HW */ + odm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A */ /* antsel2 by HW */ - /* Mapping table */ - odm_set_bb_reg(p_dm_odm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */ + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */ /* OFDM Settings */ - odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0xca4, 0x7FF000, 0x0); /* bias */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */ - /* CCK Settings */ - odm_set_bb_reg(p_dm_odm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ - odm_set_bb_reg(p_dm_odm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ - odm_set_bb_reg(p_dm_odm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */ - odm_set_bb_reg(p_dm_odm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */ + /* @CCK Settings */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */ #ifdef ODM_EVM_ENHANCE_ANTDIV - /* EVM enhance AntDiv method init---------------------------------------------------------------------- */ - p_dm_fat_table->EVM_method_enable = 0; - p_dm_fat_table->fat_state = NORMAL_STATE_MIAN; - p_dm_odm->antdiv_intvl = 0x64; - odm_set_bb_reg(p_dm_odm, 0x910, 0x3f, 0xf); - p_dm_odm->antdiv_evm_en = 1; - /* p_dm_odm->antdiv_period=1; */ - p_dm_odm->evm_antdiv_period = 3; + phydm_evm_sw_antdiv_init(dm); #endif } #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) -void -odm_smart_hw_ant_div_init_92e( - void *p_dm_void -) +void odm_smart_hw_ant_div_init_92e( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8192E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n"); } #endif -#endif /* #if (RTL8192E_SUPPORT == 1) */ +#endif /* @#if (RTL8192E_SUPPORT == 1) */ -#if (RTL8723D_SUPPORT == 1) -void -odm_trx_hw_ant_div_init_8723d( - void *p_dm_void -) +#if (RTL8192F_SUPPORT == 1) +void odm_rx_hw_ant_div_init_92f( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723D] AntDiv_Init => ant_div_type=[S0S1_HW_TRX_AntDiv]\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8192F AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n"); - /*BT Coexistence*/ - /*keep antsel_map when GNT_BT = 1*/ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(12), 1); - /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - odm_set_bb_reg(p_dm_odm, 0x874, BIT(23), 0); - /* Disable hw antsw & fast_train.antsw when BT TX/RX */ - odm_set_bb_reg(p_dm_odm, 0xE64, 0xFFFF0000, 0x000c); + /* Pin Settings */ + odm_set_bb_reg(dm, R_0x870, BIT(8), 0); /* reg870[8]=1'b0, "antsel" is controlled by HWs */ + odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); /* regc50[8]=1'b1, " CS/CG switching" is controlled by HWs */ + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */ - odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT(8), 0); - /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/ - /*odm_set_bb_reg(p_dm_odm, 0x948, BIT6, 0);*/ - /*odm_set_bb_reg(p_dm_odm, 0x948, BIT8, 0);*/ - /*GNT_WL tx*/ - odm_set_bb_reg(p_dm_odm, 0x950, BIT(29), 0); + /* OFDM Settings */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */ + /* @CCK Settings */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */ - /*Mapping Table*/ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 3); - /* odm_set_bb_reg(p_dm_odm, 0x864, BIT5|BIT4|BIT3, 0); */ - /* odm_set_bb_reg(p_dm_odm, 0x864, BIT8|BIT7|BIT6, 1); */ +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); +#endif +} - /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */ - odm_set_bb_reg(p_dm_odm, 0xCcc, BIT(12), 0); - /* Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */ - odm_set_bb_reg(p_dm_odm, 0xCcc, 0x0F, 0x01); - /* High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */ - odm_set_bb_reg(p_dm_odm, 0xCcc, 0xF0, 0x0); - /* b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */ - odm_set_bb_reg(p_dm_odm, 0xAbc, 0xFF, 0x06); - /* High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */ - odm_set_bb_reg(p_dm_odm, 0xAbc, 0xFF00, 0x00); +void odm_trx_hw_ant_div_init_92f( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8192F AntDiv_Init => ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n"); + /* @3 --RFE pin setting--------- */ + /* @[MAC] */ + odm_set_mac_reg(dm, R_0x1048, BIT(0), 1); /* @DBG PAD Driving control (gpioA_0) */ + odm_set_mac_reg(dm, R_0x1048, BIT(1), 1); /* @DBG PAD Driving control (gpioA_1) */ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); + odm_set_mac_reg(dm, R_0x1038, BIT(25) | BIT(24) | BIT(23), 0); /* @gpioA_0,gpioA_1*/ + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); + /* @[BB] */ + odm_set_bb_reg(dm, R_0x944, BIT(8), 1); /* output enable */ + odm_set_bb_reg(dm, R_0x944, BIT(9), 1); + odm_set_bb_reg(dm, R_0x940, BIT(16) | BIT(17), 0x0); /* r_rfe_path_sel_ (RFE_CTRL_8) */ + odm_set_bb_reg(dm, R_0x940, BIT(18) | BIT(19), 0x0); /* r_rfe_path_sel_ (RFE_CTRL_9) */ + odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer_en */ + odm_set_bb_reg(dm, R_0x92c, BIT(8), 0); /* rfe_inv (RFE_CTRL_8) */ + odm_set_bb_reg(dm, R_0x92c, BIT(9), 1); /* rfe_inv (RFE_CTRL_9) */ + odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */ + odm_set_bb_reg(dm, R_0x934, 0xF0, 0x8); /* path-A, RFE_CTRL_9 */ + /* @3 ------------------------- */ - /*OFDM HW AntDiv Parameters*/ - odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF, 0xa0); - odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF000, 0x00); - odm_set_bb_reg(p_dm_odm, 0xC5C, BIT(20) | BIT(19) | BIT(18), 0x04); + /* Pin Settings */ + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);/* path-A,disable CS/CG switch */ + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* path-A*, antsel antselb by HW */ + odm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A ,antsel2 by HW */ - /*CCK HW AntDiv Parameters*/ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); - odm_set_bb_reg(p_dm_odm, 0xAA8, BIT(8), 0); + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */ - odm_set_bb_reg(p_dm_odm, 0xA0C, 0x0F, 0xf); - odm_set_bb_reg(p_dm_odm, 0xA14, 0x1F, 0x8); - odm_set_bb_reg(p_dm_odm, 0xA10, BIT(13), 0x1); - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(8), 0x0); - odm_set_bb_reg(p_dm_odm, 0xB34, BIT(30), 0x1); + /* OFDM Settings */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */ - /*disable antenna training */ - odm_set_bb_reg(p_dm_odm, 0xE08, BIT(16), 0); - odm_set_bb_reg(p_dm_odm, 0xc50, BIT(8), 0); + /* @CCK Settings */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */ +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); +#endif } -/*Mingzhi 2017-05-08*/ -void -odm_update_rx_idle_ant_8723d( - void *p_dm_void, - u8 ant, - u32 default_ant, - u32 optional_ant -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - u8 count = 0; - u8 u1_temp; - u8 h2c_parameter; - - -/* odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0x1); */ - odm_set_bb_reg(p_dm_odm, 0x948, BIT(7), default_ant); - odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*Default TX*/ - p_dm_fat_table->rx_idle_ant = ant; -} +#endif /* @#if (RTL8192F_SUPPORT == 1) */ -void -phydm_set_tx_ant_pwr_8723d( - void *p_dm_void, - u8 ant -) +#if (RTL8822B_SUPPORT == 1) +void phydm_trx_hw_ant_div_init_22b( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct dm_struct *dm = (struct dm_struct *)dm_void; - p_dm_fat_table->rx_idle_ant = ant; + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8822B AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV]\n"); -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_adapter->HalFunc.SetTxPowerLevelHandler(p_adapter, *p_dm_odm->p_channel); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(p_adapter, *p_dm_odm->p_channel); + /* Pin Settings */ + odm_set_bb_reg(dm, R_0xcb8, BIT(21) | BIT(20), 0x1); + odm_set_bb_reg(dm, R_0xcb8, BIT(23) | BIT(22), 0x1); + odm_set_bb_reg(dm, R_0xc1c, BIT(7) | BIT(6), 0x0); + /* @------------------------- */ + + /* @Mapping table */ + /* @antenna mapping table */ + odm_set_bb_reg(dm, R_0xca4, 0xFFFF, 0x0100); + + /* OFDM Settings */ + /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); + /* @bias */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); + odm_set_bb_reg(dm, R_0x668, BIT(3), 0x1); + + /* @CCK Settings */ + /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); + /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* @CCK complete HW AntDiv within 64 samples */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); + /* @BT Coexistence */ + /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, R_0x804, BIT(4), 1); + /* response TX ant by RX ant */ + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); +#if (defined(CONFIG_2T4R_ANTENNA)) + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8822B AntDiv_Init => 2T4R case\n"); + /* Pin Settings */ + odm_set_bb_reg(dm, R_0xeb8, BIT(21) | BIT(20), 0x1); + odm_set_bb_reg(dm, R_0xeb8, BIT(23) | BIT(22), 0x1); + odm_set_bb_reg(dm, R_0xe1c, BIT(7) | BIT(6), 0x0); + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0xeac, BIT(9), 1); + /* @keep antsel_map when GNT_BT = 1 */ + /* Mapping table */ + /* antenna mapping table */ + odm_set_bb_reg(dm, R_0xea4, 0xFFFF, 0x0100); + /*odm_set_bb_reg(dm, R_0x900, 0x30000, 0x3);*/ #endif -} +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); #endif +} +#endif /* @#if (RTL8822B_SUPPORT == 1) */ -#if (RTL8723B_SUPPORT == 1) -void -odm_trx_hw_ant_div_init_8723b( - void *p_dm_void -) +#if (RTL8197F_SUPPORT == 1) +void phydm_rx_hw_ant_div_init_97f( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n")); - - /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 1); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF, 0xa0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0xCA4, 0x7FF000, 0x00); /* bias */ +#if 0 + if (*dm->mp_mode == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ + odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); /* @1:CG, 0:CS */ + return; + } +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8197F AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n"); - /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + /* Pin Settings */ + odm_set_bb_reg(dm, R_0x870, BIT(8), 0); /* reg870[8]=1'b0, */ /* "antsel" is controlled by HWs */ + odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); /* regc50[8]=1'b1 */ /* " CS/CG switching" is controlled by HWs */ - /* BT Coexistence */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(12), 0); /* keep antsel_map when GNT_BT = 1 */ - odm_set_bb_reg(p_dm_odm, 0x874, BIT(23), 0); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */ - /* Output Pin Settings */ - odm_set_bb_reg(p_dm_odm, 0x870, BIT(8), 0); + /* OFDM Settings */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */ - odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0); /* WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) */ - odm_set_bb_reg(p_dm_odm, 0x948, BIT(7), 0); + /* @CCK Settings */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */ - odm_set_mac_reg(p_dm_odm, 0x40, BIT(3), 1); - odm_set_mac_reg(p_dm_odm, 0x38, BIT(11), 1); - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24) | BIT23, 2); /* select DPDT_P and DPDT_N as output pin */ +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); +#endif +} - odm_set_bb_reg(p_dm_odm, 0x944, BIT(0) | BIT1, 3); /* in/out */ - odm_set_bb_reg(p_dm_odm, 0x944, BIT(31), 0); +#endif //#if (RTL8197F_SUPPORT == 1) +#if (RTL8723D_SUPPORT == 1) +void odm_trx_hw_ant_div_init_8723d( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; - odm_set_bb_reg(p_dm_odm, 0x92C, BIT(1), 0); /* DPDT_P non-inverse */ - odm_set_bb_reg(p_dm_odm, 0x92C, BIT(0), 1); /* DPDT_N inverse */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "[8723D] AntDiv_Init => ant_div_type=[S0S1_HW_TRX_AntDiv]\n"); - odm_set_bb_reg(p_dm_odm, 0x930, 0xF0, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0x930, 0xF, 8); /* DPDT_N = ANTSEL[0] */ + /*@BT Coexistence*/ + /*@keep antsel_map when GNT_BT = 1*/ + odm_set_bb_reg(dm, R_0x864, BIT(12), 1); + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, R_0x874, BIT(23), 0); + /* @Disable hw antsw & fast_train.antsw when BT TX/RX */ + odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c); - /* 2 [--For HW Bug setting] */ - if (p_dm_odm->ant_type == ODM_AUTO_ANT) - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); +#if 0 + /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/ + /*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/ + /*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/ +#endif + /*@GNT_WL tx*/ + odm_set_bb_reg(dm, R_0x950, BIT(29), 0); -} + /*@Mapping Table*/ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 3); +#if 0 + /* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */ + /* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */ +#endif + /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */ + odm_set_bb_reg(dm, R_0xccc, BIT(12), 0); + /* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */ + odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01); + /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */ + odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0); + /* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */ + odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06); + /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */ + odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00); + /*OFDM HW AntDiv Parameters*/ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); + odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04); + + /*@CCK HW AntDiv Parameters*/ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); + odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0); + + odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf); + odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8); + odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1); + odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0); + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1); + + /*@disable antenna training */ + odm_set_bb_reg(dm, R_0xe08, BIT(16), 0); + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); +} +/*@Mingzhi 2017-05-08*/ -void -odm_s0s1_sw_ant_div_init_8723b( - void *p_dm_void +void odm_s0s1_sw_ant_div_init_8723d( + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8723D AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); - /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0x914, MASKBYTE1, 1); + /*@keep antsel_map when GNT_BT = 1*/ + odm_set_bb_reg(dm, R_0x864, BIT(12), 1); - /* Output Pin Settings */ - /* odm_set_bb_reg(p_dm_odm, 0x948, BIT6, 0x1); */ - odm_set_bb_reg(p_dm_odm, 0x870, BIT(9) | BIT(8), 0); + /* @Disable antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, R_0x874, BIT(23), 0); + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1); - p_dm_fat_table->is_become_linked = false; - p_dm_swat_table->try_flag = SWAW_STEP_INIT; - p_dm_swat_table->double_chk_flag = 0; + /* Output Pin Settings */ +#if 0 + /* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */ +#endif + odm_set_bb_reg(dm, R_0x870, BIT(8), 1); + odm_set_bb_reg(dm, R_0x870, BIT(9), 1); - /* 2 [--For HW Bug setting] */ - odm_set_bb_reg(p_dm_odm, 0x80C, BIT(21), 0); /* TX ant by Reg */ + /* Status init */ + fat_tab->is_become_linked = false; + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->double_chk_flag = 0; + dm_swat_table->cur_antenna = MAIN_ANT; + dm_swat_table->pre_antenna = MAIN_ANT; + dm->antdiv_counter = CONFIG_ANTENNA_DIVERSITY_PERIOD; + /* @2 [--For HW Bug setting] */ + odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant by Reg */ } -void -odm_update_rx_idle_ant_8723b( - void *p_dm_void, - u8 ant, - u32 default_ant, - u32 optional_ant -) +void odm_update_rx_idle_ant_8723d( + void *dm_void, + u8 ant, + u32 default_ant, + u32 optional_ant) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - u8 count = 0; - u8 u1_temp; - u8 h2c_parameter; - - if ((!p_dm_odm->is_linked) && (p_dm_odm->ant_type == ODM_AUTO_ANT)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n")); - return; - } + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + void *adapter = dm->adapter; + u8 count = 0; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + /*score board to BT ,a002:WL to do ant-div*/ + odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa002); + ODM_delay_us(50); +#endif #if 0 - /* Send H2C command to FW */ - /* Enable wifi calibration */ - h2c_parameter = true; - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); - - /* Check if H2C command sucess or not (0x1e6) */ - u1_temp = odm_read_1byte(p_dm_odm, 0x1e6); - while ((u1_temp != 0x1) && (count < 100)) { - ODM_delay_us(10); - u1_temp = odm_read_1byte(p_dm_odm, 0x1e6); - count++; + /* odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1); */ +#endif + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + odm_set_bb_reg(dm, R_0x860, BIT(8), default_ant); + odm_set_bb_reg(dm, R_0x860, BIT(9), default_ant); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n", u1_temp, count)); + odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*@Default RX*/ + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*@Default TX*/ + fat_tab->rx_idle_ant = ant; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + /*score board to BT ,a000:WL@S1 a001:WL@S0*/ + if (default_ant == ANT1_2G) + odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa000); + else + odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa001); +#endif +} - if (u1_temp == 0x1) { - /* Check if BT is doing IQK (0x1e7) */ - count = 0; - u1_temp = odm_read_1byte(p_dm_odm, 0x1e7); - while ((!(u1_temp & BIT(0))) && (count < 100)) { - ODM_delay_us(50); - u1_temp = odm_read_1byte(p_dm_odm, 0x1e7); - count++; - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n", u1_temp, count)); +void phydm_set_tx_ant_pwr_8723d( + void *dm_void, + u8 ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + void *adapter = dm->adapter; - if (u1_temp & BIT(0)) { - odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0x1); - odm_set_bb_reg(p_dm_odm, 0x948, BIT(9), default_ant); - odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /* Default RX */ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /* Optional RX */ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /* Default TX */ - p_dm_fat_table->rx_idle_ant = ant; + fat_tab->rx_idle_ant = ant; - /* Set TX AGC by S0/S1 */ - /* Need to consider Linux driver */ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_adapter->hal_func.set_tx_power_level_handler(p_adapter, *p_dm_odm->p_channel); + ((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(p_adapter, *p_dm_odm->p_channel); + rtw_hal_set_tx_power_level(adapter, *dm->channel); +#endif +} #endif - /* Set IQC by S0/S1 */ - odm_set_iqc_by_rfpath(p_dm_odm, default_ant); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Sucess to set RX antenna\n")); - } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n")); - } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n")); +#if (RTL8723B_SUPPORT == 1) +void odm_trx_hw_ant_div_init_8723b( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; - /* Send H2C command to FW */ - /* Disable wifi calibration */ - h2c_parameter = false; - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); -#else + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8723B AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n"); - odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0x1); - odm_set_bb_reg(p_dm_odm, 0x948, BIT(9), default_ant); - odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /*Default RX*/ - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /*Optional RX*/ - odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /*Default TX*/ - p_dm_fat_table->rx_idle_ant = ant; + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1); - /* Set TX AGC by S0/S1 */ - /* Need to consider Linux driver */ + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); /* @bias */ + + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ + + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0x864, BIT(12), 0); /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0x874, BIT(23), 0); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + + /* Output Pin Settings */ + odm_set_bb_reg(dm, R_0x870, BIT(8), 0); + + odm_set_bb_reg(dm, R_0x948, BIT(6), 0); /* WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) */ + odm_set_bb_reg(dm, R_0x948, BIT(7), 0); + + odm_set_mac_reg(dm, R_0x40, BIT(3), 1); + odm_set_mac_reg(dm, R_0x38, BIT(11), 1); + odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2); /* select DPDT_P and DPDT_N as output pin */ + + odm_set_bb_reg(dm, R_0x944, BIT(0) | BIT(1), 3); /* @in/out */ + odm_set_bb_reg(dm, R_0x944, BIT(31), 0); + + odm_set_bb_reg(dm, R_0x92c, BIT(1), 0); /* @DPDT_P non-inverse */ + odm_set_bb_reg(dm, R_0x92c, BIT(0), 1); /* @DPDT_N inverse */ + + odm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */ + + /* @2 [--For HW Bug setting] */ + if (dm->ant_type == ODM_AUTO_ANT) + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */ +} + +void odm_s0s1_sw_ant_div_init_8723b( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1); + +#if 0 + /* Output Pin Settings */ + /* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */ +#endif + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); + + fat_tab->is_become_linked = false; + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->double_chk_flag = 0; + + /* @2 [--For HW Bug setting] */ + odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant by Reg */ +} + +void odm_update_rx_idle_ant_8723b( + void *dm_void, + u8 ant, + u32 default_ant, + u32 optional_ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + void *adapter = dm->adapter; + u8 count = 0; + /*u8 u1_temp;*/ + /*u8 h2c_parameter;*/ + + if (!dm->is_linked && dm->ant_type == ODM_AUTO_ANT) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n"); + return; + } + +#if 0 + /* Send H2C command to FW */ + /* @Enable wifi calibration */ + h2c_parameter = true; + odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); + + /* @Check if H2C command sucess or not (0x1e6) */ + u1_temp = odm_read_1byte(dm, 0x1e6); + while ((u1_temp != 0x1) && (count < 100)) { + ODM_delay_us(10); + u1_temp = odm_read_1byte(dm, 0x1e6); + count++; + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n", + u1_temp, count); + + if (u1_temp == 0x1) { + /* @Check if BT is doing IQK (0x1e7) */ + count = 0; + u1_temp = odm_read_1byte(dm, 0x1e7); + while ((!(u1_temp & BIT(0))) && (count < 100)) { + ODM_delay_us(50); + u1_temp = odm_read_1byte(dm, 0x1e7); + count++; + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n", + u1_temp, count); + + if (u1_temp & BIT(0)) { + odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1); + odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant); + odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT4 | BIT3, default_ant); /* @Default RX */ + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT7 | BIT6, optional_ant); /* Optional RX */ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT13 | BIT12, default_ant); /* @Default TX */ + fat_tab->rx_idle_ant = ant; + + /* Set TX AGC by S0/S1 */ + /* Need to consider Linux driver */ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_adapter->HalFunc.SetTxPowerLevelHandler(p_adapter, *p_dm_odm->p_channel); + adapter->hal_func.set_tx_power_level_handler(adapter, *dm->channel); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - rtw_hal_set_tx_power_level(p_adapter, *p_dm_odm->p_channel); + rtw_hal_set_tx_power_level(adapter, *dm->channel); +#endif + + /* Set IQC by S0/S1 */ + odm_set_iqc_by_rfpath(dm, default_ant); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n"); + } else + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n"); + } else + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n"); + + /* Send H2C command to FW */ + /* @Disable wifi calibration */ + h2c_parameter = false; + odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); +#else + + odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1); + odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant); + odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*@Default RX*/ + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*@Default TX*/ + fat_tab->rx_idle_ant = ant; + +/* Set TX AGC by S0/S1 */ +/* Need to consider Linux driver */ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(adapter, *dm->channel); #endif /* Set IQC by S0/S1 */ - odm_set_iqc_by_rfpath(p_dm_odm, default_ant); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n")); + odm_set_iqc_by_rfpath(dm, default_ant); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n"); #endif } boolean phydm_is_bt_enable_8723b( - void *p_dm_void -) + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 bt_state; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 bt_state; +#if 0 /*u32 reg75;*/ - /*reg75 = odm_get_bb_reg(p_dm_odm, 0x74, BIT8);*/ - /*odm_set_bb_reg(p_dm_odm, 0x74, BIT8, 0x0);*/ - odm_set_bb_reg(p_dm_odm, 0xa0, BIT(24) | BIT(25) | BIT(26), 0x5); - bt_state = odm_get_bb_reg(p_dm_odm, 0xa0, (BIT(3) | BIT(2) | BIT(1) | BIT(0))); - /*odm_set_bb_reg(p_dm_odm, 0x74, BIT8, reg75);*/ + /*reg75 = odm_get_bb_reg(dm, R_0x74, BIT8);*/ + /*odm_set_bb_reg(dm, R_0x74, BIT8, 0x0);*/ +#endif + odm_set_bb_reg(dm, R_0xa0, BIT(24) | BIT(25) | BIT(26), 0x5); + bt_state = odm_get_bb_reg(dm, R_0xa0, (BIT(3) | BIT(2) | BIT(1) | BIT(0))); +#if 0 + /*odm_set_bb_reg(dm, R_0x74, BIT8, reg75);*/ +#endif - if ((bt_state == 4) || (bt_state == 7) || (bt_state == 9) || (bt_state == 13)) + if (bt_state == 4 || bt_state == 7 || bt_state == 9 || bt_state == 13) return true; else return false; } -#endif /* #if (RTL8723B_SUPPORT == 1) */ +#endif /* @#if (RTL8723B_SUPPORT == 1) */ #if (RTL8821A_SUPPORT == 1) -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 -void -phydm_hl_smart_ant_type1_init_8821a( - void *p_dm_void -) + +void odm_trx_hw_ant_div_init_8821a( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u32 value32; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A SmartAnt_Init => ant_div_type=[Hong-Lin Smart ant Type1]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8821A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n"); -#if 0 - /* ---------------------------------------- */ - /* GPIO 2-3 for Beam control */ - /* reg0x66[2]=0 */ - /* reg0x44[27:26] = 0 */ - /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ - /* reg0x44[15:8] output_value for P_GPIO[7:0] */ - /* reg0x40[1:0] = 0 GPIO function */ - /* ------------------------------------------ */ -#endif - - /*GPIO setting*/ - odm_set_mac_reg(p_dm_odm, 0x64, BIT(18), 0); - odm_set_mac_reg(p_dm_odm, 0x44, BIT(27) | BIT(26), 0); - odm_set_mac_reg(p_dm_odm, 0x44, BIT(19) | BIT18, 0x3); /*enable_output for P_GPIO[3:2]*/ - /*odm_set_mac_reg(p_dm_odm, 0x44, BIT(11)|BIT10, 0);*/ /*output value*/ - odm_set_mac_reg(p_dm_odm, 0x40, BIT(1) | BIT0, 0); /*GPIO function*/ - - /*Hong_lin smart antenna HW setting*/ - pdm_sat_table->rfu_codeword_total_bit_num = 24;/*max=32*/ - pdm_sat_table->rfu_each_ant_bit_num = 4; - pdm_sat_table->beam_patten_num_each_ant = 4; - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - pdm_sat_table->latch_time = 100; /*mu sec*/ -#elif DEV_BUS_TYPE == RT_USB_INTERFACE - pdm_sat_table->latch_time = 100; /*mu sec*/ -#endif - pdm_sat_table->pkt_skip_statistic_en = 0; - - pdm_sat_table->ant_num = 1;/*max=8*/ - pdm_sat_table->ant_num_total = NUM_ANTENNA_8821A; - pdm_sat_table->first_train_ant = MAIN_ANT; - - pdm_sat_table->rfu_codeword_table[0] = 0x0; - pdm_sat_table->rfu_codeword_table[1] = 0x4; - pdm_sat_table->rfu_codeword_table[2] = 0x8; - pdm_sat_table->rfu_codeword_table[3] = 0xc; - - pdm_sat_table->rfu_codeword_table_5g[0] = 0x1; - pdm_sat_table->rfu_codeword_table_5g[1] = 0x2; - pdm_sat_table->rfu_codeword_table_5g[2] = 0x4; - pdm_sat_table->rfu_codeword_table_5g[3] = 0x8; - - pdm_sat_table->fix_beam_pattern_en = 0; - pdm_sat_table->decision_holding_period = 0; - - /*beam training setting*/ - pdm_sat_table->pkt_counter = 0; - pdm_sat_table->per_beam_training_pkt_num = 10; - - /*set default beam*/ - pdm_sat_table->fast_training_beam_num = 0; - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - phydm_set_all_ant_same_beam_num(p_dm_odm); - - p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; - - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKDWORD, 0x01000100); - odm_set_bb_reg(p_dm_odm, 0xCA8, MASKDWORD, 0x01000100); - - /*[BB] FAT setting*/ - odm_set_bb_reg(p_dm_odm, 0xc08, BIT(18) | BIT(17) | BIT(16), pdm_sat_table->ant_num); - odm_set_bb_reg(p_dm_odm, 0xc08, BIT(31), 0); /*increase ant num every FAT period 0:+1, 1+2*/ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(2) | BIT1, 1); /*change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(0), 1); /*FAT_watchdog_en*/ - - value32 = odm_get_mac_reg(p_dm_odm, 0x7B4, MASKDWORD); - odm_set_mac_reg(p_dm_odm, 0x7b4, MASKDWORD, value32 | (BIT(16) | BIT17)); /*Reg7B4[16]=1 enable antenna training */ - /*Reg7B4[17]=1 enable match MAC addr*/ - odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, 0);/*Match MAC ADDR*/ - odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, 0); + /* Output Pin Settings */ + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); + + odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */ + + odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0); + + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */ + odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */ + odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */ + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */ + + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ + + odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */ + + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ + + /* response TX ant by RX ant */ + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); } -#endif -void -odm_trx_hw_ant_div_init_8821a( - void *p_dm_void -) +void odm_s0s1_sw_ant_div_init_8821a( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8821A AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); /* Output Pin Settings */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); - odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ - odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ + odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB0, MASKDWORD, 0x77775745); - odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0); + odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0); - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /* by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */ + odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */ + odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */ - /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x10); /* bias */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */ - /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ + odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */ - /* BT Coexistence */ - odm_set_bb_reg(p_dm_odm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ - odm_set_bb_reg(p_dm_odm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ /* response TX ant by RX ant */ - odm_set_mac_reg(p_dm_odm, 0x668, BIT(3), 1); + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); + odm_set_bb_reg(dm, R_0x900, BIT(18), 0); + + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->double_chk_flag = 0; + dm_swat_table->cur_antenna = MAIN_ANT; + dm_swat_table->pre_antenna = MAIN_ANT; + dm_swat_table->swas_no_link_state = 0; } +#endif /* @#if (RTL8821A_SUPPORT == 1) */ -void -odm_s0s1_sw_ant_div_init_8821a( - void *p_dm_void -) +#if (RTL8821C_SUPPORT == 1) +void odm_trx_hw_ant_div_init_8821c( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8821C AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n"); /* Output Pin Settings */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); - odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ - odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ + odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB0, MASKDWORD, 0x77775745); - odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0); + odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0); - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /* by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */ + odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */ + odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */ - /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x10); /* bias */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */ - /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ + odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */ - /* BT Coexistence */ - odm_set_bb_reg(p_dm_odm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ - odm_set_bb_reg(p_dm_odm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + /* Timming issue */ + odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0); /*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/ + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ /* response TX ant by RX ant */ - odm_set_mac_reg(p_dm_odm, 0x668, BIT(3), 1); - - - odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), 0); - - p_dm_swat_table->try_flag = SWAW_STEP_INIT; - p_dm_swat_table->double_chk_flag = 0; - p_dm_swat_table->cur_antenna = MAIN_ANT; - p_dm_swat_table->pre_antenna = MAIN_ANT; - p_dm_swat_table->swas_no_link_state = 0; - + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); } -#endif /* #if (RTL8821A_SUPPORT == 1) */ -#if (RTL8822B_SUPPORT == 1) -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 -void -phydm_hl_smart_ant_type2_init_8822b( - void *p_dm_void -) +void phydm_s0s1_sw_ant_div_init_8821c( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u8 j; - u8 rfu_codeword_table_init_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = { - {1, 1},/*0*/ - {1, 2}, - {2, 1}, - {2, 2}, - {4, 0}, - {5, 0}, - {6, 0}, - {7, 0}, - {8, 0},/*8*/ - {9, 0}, - {0xa, 0}, - {0xb, 0}, - {0xc, 0}, - {0xd, 0}, - {0xe, 0}, - {0xf, 0} - }; - u8 rfu_codeword_table_init_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] ={ - #if 1 - {9, 1},/*0*/ - {9, 9}, - {1, 9}, - {9, 6}, - {2, 1}, - {2, 9}, - {9, 2}, - {2, 2},/*8*/ - {6, 1}, - {6, 9}, - {2, 9}, - {2, 2}, - {6, 2}, - {6, 6}, - {2, 6}, - {1, 1} - #else - {1, 1},/*0*/ - {9, 1}, - {9, 9}, - {1, 9}, - {1, 2}, - {9, 2}, - {9, 6}, - {1, 6}, - {2, 1},/*8*/ - {6, 1}, - {6, 9}, - {2, 9}, - {2, 2}, - {6, 2}, - {6, 6}, - {2, 6} - #endif - }; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***RTK 8822B SmartAnt_Init: Hong-Bo SmrtAnt Type2]\n")); - - /* ---------------------------------------- */ - /* GPIO 0-1 for Beam control */ - /* reg0x66[2:0]=0 */ - /* reg0x44[25:24] = 0 */ - /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ - /* reg0x44[15:8] output_value for P_GPIO[7:0] */ - /* reg0x40[1:0] = 0 GPIO function */ - /* ------------------------------------------ */ - - odm_move_memory(p_dm_odm, pdm_sat_table->rfu_codeword_table_2g, rfu_codeword_table_init_2g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); - odm_move_memory(p_dm_odm, pdm_sat_table->rfu_codeword_table_5g, rfu_codeword_table_init_5g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); - - /*GPIO setting*/ - odm_set_mac_reg(p_dm_odm, 0x64, (BIT(18) | BIT(17) | BIT(16)), 0); - odm_set_mac_reg(p_dm_odm, 0x44, BIT(25) | BIT24, 0); /*config P_GPIO[3:2] to data port*/ - odm_set_mac_reg(p_dm_odm, 0x44, BIT(17) | BIT16, 0x3); /*enable_output for P_GPIO[3:2]*/ - /*odm_set_mac_reg(p_dm_odm, 0x44, BIT(9)|BIT8, 0);*/ /*P_GPIO[3:2] output value*/ - odm_set_mac_reg(p_dm_odm, 0x40, BIT(1) | BIT0, 0); /*GPIO function*/ - - /*Hong_lin smart antenna HW setting*/ - pdm_sat_table->rfu_protocol_type = 2; - pdm_sat_table->rfu_protocol_delay_time = 45; - - pdm_sat_table->rfu_codeword_total_bit_num = 16;/*max=32bit*/ - pdm_sat_table->rfu_each_ant_bit_num = 4; - - pdm_sat_table->total_beam_set_num = 4; - pdm_sat_table->total_beam_set_num_2g = 4; - pdm_sat_table->total_beam_set_num_5g = 8; - -#if DEV_BUS_TYPE == RT_SDIO_INTERFACE - pdm_sat_table->latch_time = 100; /*mu sec*/ -#elif DEV_BUS_TYPE == RT_USB_INTERFACE - pdm_sat_table->latch_time = 100; /*mu sec*/ -#endif - pdm_sat_table->pkt_skip_statistic_en = 0; - - pdm_sat_table->ant_num = 2; - pdm_sat_table->ant_num_total = MAX_PATH_NUM_8822B; - pdm_sat_table->first_train_ant = MAIN_ANT; - - - - pdm_sat_table->fix_beam_pattern_en = 0; - pdm_sat_table->decision_holding_period = 0; - - /*beam training setting*/ - pdm_sat_table->pkt_counter = 0; - pdm_sat_table->per_beam_training_pkt_num = 10; - - /*set default beam*/ - pdm_sat_table->fast_training_beam_num = 0; - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - - for (j = 0; j < SUPPORT_BEAM_SET_PATTERN_NUM; j++) { - - pdm_sat_table->beam_set_avg_rssi_pre[j] = 0; - pdm_sat_table->beam_set_train_rssi_diff[j] = 0; - pdm_sat_table->beam_set_train_cnt[j] = 0; - } - phydm_set_rfu_beam_pattern_type2(p_dm_odm); - p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; - -} -#endif -#endif - + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; -#if (RTL8821C_SUPPORT == 1) -void -odm_trx_hw_ant_div_init_8821c( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8821C AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821C AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n")); /* Output Pin Settings */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); - odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */ - odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */ + odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB0, MASKDWORD, 0x77775745); - odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0); + odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0); - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(24), 1); /* by WLAN control */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */ + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */ + odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */ + odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */ - /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x10); /* bias */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x00); /* @bias */ - /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */ - odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */ + odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */ - /* BT Coexistence */ - odm_set_bb_reg(p_dm_odm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */ - odm_set_bb_reg(p_dm_odm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ - /* Timming issue */ - odm_set_bb_reg(p_dm_odm, 0x818, BIT(23) | BIT22 | BIT21 | BIT20, 0); /*keep antidx after tx for ACK ( unit x 3.2 mu sec)*/ - odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ /* response TX ant by RX ant */ - odm_set_mac_reg(p_dm_odm, 0x668, BIT(3), 1); + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); -} -#endif /* #if (RTL8821C_SUPPORT == 1) */ + odm_set_bb_reg(dm, R_0x900, BIT(18), 0); + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->double_chk_flag = 0; + dm_swat_table->cur_antenna = MAIN_ANT; + dm_swat_table->pre_antenna = MAIN_ANT; + dm_swat_table->swas_no_link_state = 0; +} +#endif /* @#if (RTL8821C_SUPPORT == 1) */ #if (RTL8881A_SUPPORT == 1) -void -odm_trx_hw_ant_div_init_8881a( - void *p_dm_void -) +void odm_trx_hw_ant_div_init_8881a( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8881A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n"); /* Output Pin Settings */ - /* [SPDT related] */ - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(25), 0); - odm_set_mac_reg(p_dm_odm, 0x4C, BIT(26), 0); - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(31), 0); /* delay buffer */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(22), 0); - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(24), 1); - odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF00, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF0000, 8); /* DPDT_N = ANTSEL[0] */ - - /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + /* @[SPDT related] */ + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); + odm_set_mac_reg(dm, R_0x4c, BIT(26), 0); + odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */ + odm_set_bb_reg(dm, R_0xcb4, BIT(22), 0); + odm_set_bb_reg(dm, R_0xcb4, BIT(24), 1); + odm_set_bb_reg(dm, R_0xcb0, 0xF00, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb0, 0xF0000, 8); /* @DPDT_N = ANTSEL[0] */ + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x0); /* bias */ - odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */ + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ - /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ - /* 2 [--For HW Bug setting] */ + /* @2 [--For HW Bug setting] */ - odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */ + odm_set_bb_reg(dm, R_0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */ } -#endif /* #if (RTL8881A_SUPPORT == 1) */ - +#endif /* @#if (RTL8881A_SUPPORT == 1) */ #if (RTL8812A_SUPPORT == 1) -void -odm_trx_hw_ant_div_init_8812a( - void *p_dm_void -) +void odm_trx_hw_ant_div_init_8812a( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n")); - - /* 3 */ /* 3 --RFE pin setting--------- */ - /* [BB] */ - odm_set_bb_reg(p_dm_odm, 0x900, BIT(10) | BIT9 | BIT8, 0x0); /* disable SW switch */ - odm_set_bb_reg(p_dm_odm, 0x900, BIT(17) | BIT(16), 0x0); - odm_set_bb_reg(p_dm_odm, 0x974, BIT(7) | BIT6, 0x3); /* in/out */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(31), 0); /* delay buffer */ - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(26), 0); - odm_set_bb_reg(p_dm_odm, 0xCB4, BIT(27), 1); - odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF000000, 8); /* DPDT_P = ANTSEL[0] */ - odm_set_bb_reg(p_dm_odm, 0xCB0, 0xF0000000, 8); /* DPDT_N = ANTSEL[0] */ - /* 3 ------------------------- */ - - /* Mapping Table */ - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE0, 0); - odm_set_bb_reg(p_dm_odm, 0xCA4, MASKBYTE1, 1); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8812A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n"); + + /* @3 */ /* @3 --RFE pin setting--------- */ + /* @[BB] */ + odm_set_bb_reg(dm, R_0x900, BIT(10) | BIT(9) | BIT(8), 0x0); /* @disable SW switch */ + odm_set_bb_reg(dm, R_0x900, BIT(17) | BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x974, BIT(7) | BIT(6), 0x3); /* @in/out */ + odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */ + odm_set_bb_reg(dm, R_0xcb4, BIT(26), 0); + odm_set_bb_reg(dm, R_0xcb4, BIT(27), 1); + odm_set_bb_reg(dm, R_0xcb0, 0xF000000, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb0, 0xF0000000, 8); /* @DPDT_N = ANTSEL[0] */ + /* @3 ------------------------- */ + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); /* OFDM HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF, 0xA0); /* thershold */ - odm_set_bb_reg(p_dm_odm, 0x8D4, 0x7FF000, 0x0); /* bias */ - odm_set_bb_reg(p_dm_odm, 0x8CC, BIT(20) | BIT19 | BIT18, 3); /* settling time of antdiv by RF LNA = 100ns */ - - /* CCK HW AntDiv Parameters */ - odm_set_bb_reg(p_dm_odm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */ - odm_set_bb_reg(p_dm_odm, 0xA0C, BIT(4), 1); /* do 64 samples */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */ + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */ - /* 2 [--For HW Bug setting] */ + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ - odm_set_bb_reg(p_dm_odm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */ + /* @2 [--For HW Bug setting] */ + odm_set_bb_reg(dm, R_0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */ } -#endif /* #if (RTL8812A_SUPPORT == 1) */ +#endif /* @#if (RTL8812A_SUPPORT == 1) */ #if (RTL8188F_SUPPORT == 1) -void -odm_s0s1_sw_ant_div_init_8188f( - void *p_dm_void -) +void odm_s0s1_sw_ant_div_init_8188f( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188F AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8188F AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); - /*GPIO setting*/ - /*odm_set_mac_reg(p_dm_odm, 0x64, BIT18, 0); */ - /*odm_set_mac_reg(p_dm_odm, 0x44, BIT28|BIT27, 0);*/ - odm_set_mac_reg(p_dm_odm, 0x44, BIT(20) | BIT19, 0x3); /*enable_output for P_GPIO[4:3]*/ - /*odm_set_mac_reg(p_dm_odm, 0x44, BIT(12)|BIT11, 0);*/ /*output value*/ - /*odm_set_mac_reg(p_dm_odm, 0x40, BIT(1)|BIT0, 0);*/ /*GPIO function*/ +#if 0 + /*@GPIO setting*/ + /*odm_set_mac_reg(dm, R_0x64, BIT(18), 0); */ + /*odm_set_mac_reg(dm, R_0x44, BIT(28)|BIT(27), 0);*/ + /*odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);*/ /*enable_output for P_GPIO[4:3]*/ + /*odm_set_mac_reg(dm, R_0x44, BIT(12)|BIT(11), 0);*/ /*output value*/ + /*odm_set_mac_reg(dm, R_0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/ +#endif + + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_USB) + odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3); /*@enable_output for P_GPIO[4:3]*/ + else if (dm->support_interface == ODM_ITRF_SDIO) + odm_set_mac_reg(dm, R_0x44, BIT(18), 0x1); /*@enable_output for P_GPIO[2]*/ + } - p_dm_fat_table->is_become_linked = false; - p_dm_swat_table->try_flag = SWAW_STEP_INIT; - p_dm_swat_table->double_chk_flag = 0; + fat_tab->is_become_linked = false; + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->double_chk_flag = 0; } -void -phydm_update_rx_idle_antenna_8188F( - void *p_dm_void, - u32 default_ant -) +void phydm_update_rx_idle_antenna_8188F( + void *dm_void, + u32 default_ant) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 codeword; - - if (default_ant == ANT1_2G) - codeword = 1; /*2'b01*/ - else - codeword = 2;/*2'b10*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 codeword; - odm_set_mac_reg(p_dm_odm, 0x44, (BIT(12) | BIT11), codeword); /*GPIO[4:3] output value*/ + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_USB) { + if (default_ant == ANT1_2G) + codeword = 1; /*@2'b01*/ + else + codeword = 2; /*@2'b10*/ + odm_set_mac_reg(dm, R_0x44, (BIT(12) | BIT(11)), codeword); /*@GPIO[4:3] output value*/ + } else if (dm->support_interface == ODM_ITRF_SDIO) { + if (default_ant == ANT1_2G) { + codeword = 0; /*@1'b0*/ + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0x3); + odm_set_bb_reg(dm, R_0x860, BIT(9) | BIT(8), 0x1); + } else { + codeword = 1; /*@1'b1*/ + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0x3); + odm_set_bb_reg(dm, R_0x860, BIT(9) | BIT(8), 0x2); + } + odm_set_mac_reg(dm, R_0x44, BIT(10), codeword); /*@GPIO[2] output value*/ + } + } } - #endif - - #ifdef ODM_EVM_ENHANCE_ANTDIV - -void -odm_evm_fast_ant_reset( - void *p_dm_void -) +void phydm_evm_sw_antdiv_init( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - - p_dm_fat_table->EVM_method_enable = 0; - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - p_dm_fat_table->fat_state = NORMAL_STATE_MIAN; - p_dm_odm->antdiv_period = 0; - odm_set_mac_reg(p_dm_odm, 0x608, BIT(8), 0); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + /*@EVM enhance AntDiv method init----------------------------------------------------------------------*/ + fat_tab->evm_method_enable = 0; + fat_tab->fat_state = NORMAL_STATE_MIAN; + fat_tab->fat_state_cnt = 0; + fat_tab->pre_antdiv_rssi = 0; + + dm->antdiv_intvl = 30; + dm->antdiv_train_num = 2; + odm_set_bb_reg(dm, R_0x910, 0x3f, 0xf); + dm->antdiv_evm_en = 1; + /*@dm->antdiv_period=1;*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + dm->evm_antdiv_period = 1; +#else + dm->evm_antdiv_period = 3; +#endif + dm->stop_antdiv_rssi_th = 3; + dm->stop_antdiv_tp_th = 80; + dm->antdiv_tp_period = 3; + dm->stop_antdiv_tp_diff_th = 5; } +void odm_evm_fast_ant_reset( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + fat_tab->evm_method_enable = 0; + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB); + fat_tab->fat_state = NORMAL_STATE_MIAN; + fat_tab->fat_state_cnt = 0; + dm->antdiv_period = 0; + odm_set_mac_reg(dm, R_0x608, BIT(8), 0); +} -void -odm_evm_enhance_ant_div( - void *p_dm_void -) +void odm_evm_enhance_ant_div( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 main_rssi, aux_rssi ; - u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1; - u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0; - u8 score_EVM = 0, score_CRC = 0; - u8 rssi_larger_ant = 0; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u32 value32, i; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 main_rssi, aux_rssi; + u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1; + u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0; + u32 main_2ss_evm[2], aux_2ss_evm[2]; + u32 main_1ss_evm, aux_1ss_evm; + u32 main_2ss_evm_sum, aux_2ss_evm_sum; + u8 score_EVM = 0, score_CRC = 0; + u8 rssi_larger_ant = 0; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 value32, i; boolean main_above1 = false, aux_above1 = false; boolean force_antenna = false; - struct sta_info *p_entry; - p_dm_fat_table->target_ant_enhance = 0xFF; - - - if ((p_dm_odm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) { - if (p_dm_odm->is_one_entry_only) { - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[One Client only]\n")); */ - i = p_dm_odm->one_entry_macid; + struct cmn_sta_info *sta; + u32 antdiv_tp_main_avg, antdiv_tp_aux_avg; + u8 curr_rssi, rssi_diff; + u32 tp_diff; + u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0; + u8 target_ant_evm_1ss, target_ant_evm_2ss; + u8 decision_evm_ss; + u8 next_ant; + + fat_tab->target_ant_enhance = 0xFF; + + if ((dm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) { + if (dm->is_one_entry_only) { +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "[One Client only]\n"); */ +#endif + i = dm->one_entry_macid; + sta = dm->phydm_sta_info[i]; - main_rssi = (p_dm_fat_table->main_ant_cnt[i] != 0) ? (p_dm_fat_table->main_ant_sum[i] / p_dm_fat_table->main_ant_cnt[i]) : 0; - aux_rssi = (p_dm_fat_table->aux_ant_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_sum[i] / p_dm_fat_table->aux_ant_cnt[i]) : 0; + main_rssi = (fat_tab->main_ant_cnt[i] != 0) ? (fat_tab->main_ant_sum[i] / fat_tab->main_ant_cnt[i]) : 0; + aux_rssi = (fat_tab->aux_ant_cnt[i] != 0) ? (fat_tab->aux_ant_sum[i] / fat_tab->aux_ant_cnt[i]) : 0; if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF)) diff_rssi = FORCE_RSSI_DIFF; @@ -2006,89 +2199,145 @@ odm_evm_enhance_ant_div( else rssi_larger_ant = AUX_ANT; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", p_dm_fat_table->main_ant_cnt[i], main_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", p_dm_fat_table->aux_ant_cnt[i], aux_rssi)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "Main_Cnt=(( %d )), main_rssi=(( %d ))\n", + fat_tab->main_ant_cnt[i], main_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, + "Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n", + fat_tab->aux_ant_cnt[i], aux_rssi); + + if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || fat_tab->evm_method_enable == 1) + /* @&& (diff_rssi <= FORCE_RSSI_DIFF + 1) */ + ) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "> TH_H || evm_method_enable==1\n"); + + if ((main_rssi >= evm_rssi_th_low || aux_rssi >= evm_rssi_th_low)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_L, fat_state_cnt =((%d))\n", fat_tab->fat_state_cnt); + + /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/ + if (fat_tab->fat_state_cnt < (dm->antdiv_train_num << 1)) { + if (fat_tab->fat_state_cnt == 0) { + /*Reset EVM 1SS Method */ + fat_tab->main_ant_evm_sum[i] = 0; + fat_tab->aux_ant_evm_sum[i] = 0; + fat_tab->main_ant_evm_cnt[i] = 0; + fat_tab->aux_ant_evm_cnt[i] = 0; + /*Reset EVM 2SS Method */ + fat_tab->main_ant_evm_2ss_sum[i][0] = 0; + fat_tab->main_ant_evm_2ss_sum[i][1] = 0; + fat_tab->aux_ant_evm_2ss_sum[i][0] = 0; + fat_tab->aux_ant_evm_2ss_sum[i][1] = 0; + fat_tab->main_ant_evm_2ss_cnt[i] = 0; + fat_tab->aux_ant_evm_2ss_cnt[i] = 0; +#if 0 + /*Reset TP Method */ + fat_tab->antdiv_tp_main = 0; + fat_tab->antdiv_tp_aux = 0; + fat_tab->antdiv_tp_main_cnt = 0; + fat_tab->antdiv_tp_aux_cnt = 0; +#endif + /*Reset CRC Method */ + fat_tab->main_crc32_ok_cnt = 0; + fat_tab->main_crc32_fail_cnt = 0; + fat_tab->aux_crc32_ok_cnt = 0; + fat_tab->aux_crc32_fail_cnt = 0; + +#ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH + if ((*dm->band_width == CHANNEL_WIDTH_20) && sta->mimo_type == RF_2T2R) { + /*@1. Skip training: RSSI*/ +#if 0 + /*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, "TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt);*/ +#endif + curr_rssi = (u8)((fat_tab->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi); + rssi_diff = (curr_rssi > fat_tab->pre_antdiv_rssi) ? (curr_rssi - fat_tab->pre_antdiv_rssi) : (fat_tab->pre_antdiv_rssi - curr_rssi); + + PHYDM_DBG(dm, DBG_ANT_DIV, "[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, fat_tab->pre_antdiv_rssi); - if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || (p_dm_fat_table->EVM_method_enable == 1)) - /* && (diff_rssi <= FORCE_RSSI_DIFF + 1) */ - ) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_H || EVM_method_enable==1] && ")); + fat_tab->pre_antdiv_rssi = curr_rssi; + if (rssi_diff < dm->stop_antdiv_rssi_th && curr_rssi != 0) + rssi_return = 1; - if (((main_rssi >= evm_rssi_th_low) || (aux_rssi >= evm_rssi_th_low))) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_L ]\n")); + /*@2. Skip training: TP Diff*/ + tp_diff = (dm->rx_tp > fat_tab->pre_antdiv_tp) ? (dm->rx_tp - fat_tab->pre_antdiv_tp) : (fat_tab->pre_antdiv_tp - dm->rx_tp); - /* 2 [ Normal state Main] */ - if (p_dm_fat_table->fat_state == NORMAL_STATE_MIAN) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", dm->rx_tp, fat_tab->pre_antdiv_tp); + fat_tab->pre_antdiv_tp = dm->rx_tp; + if ((tp_diff < (u32)(dm->stop_antdiv_tp_diff_th) && dm->rx_tp != 0)) + tp_diff_return = 1; - p_dm_fat_table->EVM_method_enable = 1; - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - p_dm_odm->antdiv_period = p_dm_odm->evm_antdiv_period; + PHYDM_DBG(dm, DBG_ANT_DIV, "[3] tp_return, curr_rx_tp=((%d))\n", dm->rx_tp); + /*@3. Skip training: TP*/ + if (dm->rx_tp >= (u32)(dm->stop_antdiv_tp_th)) + tp_return = 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ start training: MIAN]\n")); - p_dm_fat_table->main_ant_evm_sum[i] = 0; - p_dm_fat_table->aux_ant_evm_sum[i] = 0; - p_dm_fat_table->main_ant_evm_cnt[i] = 0; - p_dm_fat_table->aux_ant_evm_cnt[i] = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return); + /*@4. Joint Return Decision*/ + if (tp_return) { + if (tp_diff_return || rssi_diff) { + PHYDM_DBG(dm, DBG_ANT_DIV, "***Return EVM SW AntDiv\n"); + return; + } + } + } +#endif - p_dm_fat_table->fat_state = NORMAL_STATE_AUX; - odm_set_mac_reg(p_dm_odm, 0x608, BIT(8), 1); /* Accept CRC32 Error packets. */ - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); + fat_tab->evm_method_enable = 1; + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB); + dm->antdiv_period = dm->evm_antdiv_period; + odm_set_mac_reg(dm, R_0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/ + } - p_dm_fat_table->crc32_ok_cnt = 0; - p_dm_fat_table->crc32_fail_cnt = 0; - odm_set_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer, p_dm_odm->antdiv_intvl); /* m */ + fat_tab->fat_state_cnt++; + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(dm, next_ant); + odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_intvl); //ms } - /* 2 [ Normal state Aux ] */ - else if (p_dm_fat_table->fat_state == NORMAL_STATE_AUX) { - p_dm_fat_table->main_crc32_ok_cnt = p_dm_fat_table->crc32_ok_cnt; - p_dm_fat_table->main_crc32_fail_cnt = p_dm_fat_table->crc32_fail_cnt; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ start training: AUX]\n")); - p_dm_fat_table->fat_state = TRAINING_STATE; - odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); - - p_dm_fat_table->crc32_ok_cnt = 0; - p_dm_fat_table->crc32_fail_cnt = 0; - odm_set_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer, p_dm_odm->antdiv_intvl); /* ms */ - } else if (p_dm_fat_table->fat_state == TRAINING_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Training state ]\n")); - p_dm_fat_table->fat_state = NORMAL_STATE_MIAN; - - /* 3 [CRC32 statistic] */ - p_dm_fat_table->aux_crc32_ok_cnt = p_dm_fat_table->crc32_ok_cnt; - p_dm_fat_table->aux_crc32_fail_cnt = p_dm_fat_table->crc32_fail_cnt; - - if ((p_dm_fat_table->main_crc32_ok_cnt > ((p_dm_fat_table->aux_crc32_ok_cnt) << 1)) || ((diff_rssi >= 20) && (rssi_larger_ant == MAIN_ANT))) { - p_dm_fat_table->target_ant_crc32 = MAIN_ANT; + /*@Decision state: 4==============================================================*/ + else { + fat_tab->fat_state_cnt = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "[Decisoin state ]\n"); + +/* @3 [CRC32 statistic] */ +#if 0 + if ((fat_tab->main_crc32_ok_cnt > (fat_tab->aux_crc32_ok_cnt << 1)) || (diff_rssi >= 40 && rssi_larger_ant == MAIN_ANT)) { + fat_tab->target_ant_crc32 = MAIN_ANT; force_antenna = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Main\n")); - } else if ((p_dm_fat_table->aux_crc32_ok_cnt > ((p_dm_fat_table->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 20) && (rssi_larger_ant == AUX_ANT))) { - p_dm_fat_table->target_ant_crc32 = AUX_ANT; + PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Main\n"); + } else if ((fat_tab->aux_crc32_ok_cnt > ((fat_tab->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) { + fat_tab->target_ant_crc32 = AUX_ANT; force_antenna = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Aux\n")); - } else { - if (p_dm_fat_table->main_crc32_fail_cnt <= 5) - p_dm_fat_table->main_crc32_fail_cnt = 5; + PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Aux\n"); + } else +#endif + { + if (fat_tab->main_crc32_fail_cnt <= 5) + fat_tab->main_crc32_fail_cnt = 5; - if (p_dm_fat_table->aux_crc32_fail_cnt <= 5) - p_dm_fat_table->aux_crc32_fail_cnt = 5; + if (fat_tab->aux_crc32_fail_cnt <= 5) + fat_tab->aux_crc32_fail_cnt = 5; - if (p_dm_fat_table->main_crc32_ok_cnt > p_dm_fat_table->main_crc32_fail_cnt) + if (fat_tab->main_crc32_ok_cnt > fat_tab->main_crc32_fail_cnt) main_above1 = true; - if (p_dm_fat_table->aux_crc32_ok_cnt > p_dm_fat_table->aux_crc32_fail_cnt) + if (fat_tab->aux_crc32_ok_cnt > fat_tab->aux_crc32_fail_cnt) aux_above1 = true; if (main_above1 == true && aux_above1 == false) { force_antenna = true; - p_dm_fat_table->target_ant_crc32 = MAIN_ANT; + fat_tab->target_ant_crc32 = MAIN_ANT; } else if (main_above1 == false && aux_above1 == true) { force_antenna = true; - p_dm_fat_table->target_ant_crc32 = AUX_ANT; + fat_tab->target_ant_crc32 = AUX_ANT; } else if (main_above1 == true && aux_above1 == true) { - main_crc_utility = ((p_dm_fat_table->main_crc32_ok_cnt) << 7) / p_dm_fat_table->main_crc32_fail_cnt; - aux_crc_utility = ((p_dm_fat_table->aux_crc32_ok_cnt) << 7) / p_dm_fat_table->aux_crc32_fail_cnt; - p_dm_fat_table->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT); + main_crc_utility = ((fat_tab->main_crc32_ok_cnt) << 7) / fat_tab->main_crc32_fail_cnt; + aux_crc_utility = ((fat_tab->aux_crc32_ok_cnt) << 7) / fat_tab->aux_crc32_fail_cnt; + fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT); if (main_crc_utility != 0 && aux_crc_utility != 0) { if (main_crc_utility >= aux_crc_utility) @@ -2097,14 +2346,14 @@ odm_evm_enhance_ant_div( utility_ratio = (aux_crc_utility << 1) / main_crc_utility; } } else if (main_above1 == false && aux_above1 == false) { - if (p_dm_fat_table->main_crc32_ok_cnt == 0) - p_dm_fat_table->main_crc32_ok_cnt = 1; - if (p_dm_fat_table->aux_crc32_ok_cnt == 0) - p_dm_fat_table->aux_crc32_ok_cnt = 1; + if (fat_tab->main_crc32_ok_cnt == 0) + fat_tab->main_crc32_ok_cnt = 1; + if (fat_tab->aux_crc32_ok_cnt == 0) + fat_tab->aux_crc32_ok_cnt = 1; - main_crc_utility = ((p_dm_fat_table->main_crc32_fail_cnt) << 7) / p_dm_fat_table->main_crc32_ok_cnt; - aux_crc_utility = ((p_dm_fat_table->aux_crc32_fail_cnt) << 7) / p_dm_fat_table->aux_crc32_ok_cnt; - p_dm_fat_table->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT); + main_crc_utility = ((fat_tab->main_crc32_fail_cnt) << 7) / fat_tab->main_crc32_ok_cnt; + aux_crc_utility = ((fat_tab->aux_crc32_fail_cnt) << 7) / fat_tab->aux_crc32_ok_cnt; + fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT); if (main_crc_utility != 0 && aux_crc_utility != 0) { if (main_crc_utility >= aux_crc_utility) @@ -2114,487 +2363,641 @@ odm_evm_enhance_ant_div( } } } - odm_set_mac_reg(p_dm_odm, 0x608, BIT(8), 0);/* NOT Accept CRC32 Error packets. */ - - /* 3 [EVM statistic] */ - main_evm = (p_dm_fat_table->main_ant_evm_cnt[i] != 0) ? (p_dm_fat_table->main_ant_evm_sum[i] / p_dm_fat_table->main_ant_evm_cnt[i]) : 0; - aux_evm = (p_dm_fat_table->aux_ant_evm_cnt[i] != 0) ? (p_dm_fat_table->aux_ant_evm_sum[i] / p_dm_fat_table->aux_ant_evm_cnt[i]) : 0; - p_dm_fat_table->target_ant_evm = (main_evm == aux_evm) ? (p_dm_fat_table->pre_target_ant_enhance) : ((main_evm >= aux_evm) ? MAIN_ANT : AUX_ANT); + odm_set_mac_reg(dm, R_0x608, BIT(8), 0); /* NOT Accept CRC32 Error packets. */ + PHYDM_DBG(dm, DBG_ANT_DIV, "MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->main_crc32_ok_cnt, fat_tab->main_crc32_fail_cnt, main_crc_utility); + PHYDM_DBG(dm, DBG_ANT_DIV, "AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->aux_crc32_ok_cnt, fat_tab->aux_crc32_fail_cnt, aux_crc_utility); + PHYDM_DBG(dm, DBG_ANT_DIV, "***1.TargetAnt_CRC32 = ((%s))\n", (fat_tab->target_ant_crc32 == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + + /* @3 [EVM statistic] */ + /*@1SS EVM*/ + main_1ss_evm = (fat_tab->main_ant_evm_cnt[i] != 0) ? (fat_tab->main_ant_evm_sum[i] / fat_tab->main_ant_evm_cnt[i]) : 0; + aux_1ss_evm = (fat_tab->aux_ant_evm_cnt[i] != 0) ? (fat_tab->aux_ant_evm_sum[i] / fat_tab->aux_ant_evm_cnt[i]) : 0; + target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (fat_tab->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT); + + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main1ss_EVM= (( %d ))\n", fat_tab->main_ant_evm_cnt[i], main_1ss_evm); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_1ss_EVM = (( %d ))\n", fat_tab->main_ant_evm_cnt[i], aux_1ss_evm); + + /*@2SS EVM*/ + main_2ss_evm[0] = (fat_tab->main_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->main_ant_evm_2ss_sum[i][0] / fat_tab->main_ant_evm_2ss_cnt[i]) : 0; + main_2ss_evm[1] = (fat_tab->main_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->main_ant_evm_2ss_sum[i][1] / fat_tab->main_ant_evm_2ss_cnt[i]) : 0; + main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1]; + + aux_2ss_evm[0] = (fat_tab->aux_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->aux_ant_evm_2ss_sum[i][0] / fat_tab->aux_ant_evm_2ss_cnt[i]) : 0; + aux_2ss_evm[1] = (fat_tab->aux_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->aux_ant_evm_2ss_sum[i][1] / fat_tab->aux_ant_evm_2ss_cnt[i]) : 0; + aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1]; + + target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (fat_tab->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT); + + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", + fat_tab->main_ant_evm_2ss_cnt[i], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", + fat_tab->aux_ant_evm_2ss_cnt[i], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum); + + if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) { + decision_evm_ss = 2; + main_evm = main_2ss_evm_sum; + aux_evm = aux_2ss_evm_sum; + fat_tab->target_ant_evm = target_ant_evm_2ss; + } else { + decision_evm_ss = 1; + main_evm = main_1ss_evm; + aux_evm = aux_1ss_evm; + fat_tab->target_ant_evm = target_ant_evm_1ss; + } if ((main_evm == 0 || aux_evm == 0)) - diff_EVM = 0; + diff_EVM = 100; else if (main_evm >= aux_evm) diff_EVM = main_evm - aux_evm; else diff_EVM = aux_evm - main_evm; - /* 2 [ Decision state ] */ - if (p_dm_fat_table->target_ant_evm == p_dm_fat_table->target_ant_crc32) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + PHYDM_DBG(dm, DBG_ANT_DIV, "***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (fat_tab->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + + //3 [TP statistic] + antdiv_tp_main_avg = (fat_tab->antdiv_tp_main_cnt != 0) ? (fat_tab->antdiv_tp_main / fat_tab->antdiv_tp_main_cnt) : 0; + antdiv_tp_aux_avg = (fat_tab->antdiv_tp_aux_cnt != 0) ? (fat_tab->antdiv_tp_aux / fat_tab->antdiv_tp_aux_cnt) : 0; + fat_tab->target_ant_tp = (antdiv_tp_main_avg == antdiv_tp_aux_avg) ? (fat_tab->pre_target_ant_enhance) : ((antdiv_tp_main_avg >= antdiv_tp_aux_avg) ? MAIN_ANT : AUX_ANT); + + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main_TP = ((%d))\n", fat_tab->antdiv_tp_main_cnt, antdiv_tp_main_avg); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_TP = ((%d))\n", fat_tab->antdiv_tp_aux_cnt, antdiv_tp_aux_avg); + PHYDM_DBG(dm, DBG_ANT_DIV, "***3.TargetAnt_TP = ((%s))\n", (fat_tab->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + + /*Reset TP Method */ + fat_tab->antdiv_tp_main = 0; + fat_tab->antdiv_tp_aux = 0; + fat_tab->antdiv_tp_main_cnt = 0; + fat_tab->antdiv_tp_aux_cnt = 0; + + /* @2 [ Decision state ] */ + if (fat_tab->target_ant_evm == fat_tab->target_ant_crc32) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30) - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->pre_target_ant_enhance; + fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance; else - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm; - } else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32; - } else if (diff_EVM >= 100) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm; + fat_tab->target_ant_enhance = fat_tab->target_ant_evm; + } + #if 0 + else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); + fat_tab->target_ant_enhance = fat_tab->target_ant_crc32; + } + #endif + else if (diff_EVM >= 20) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); + fat_tab->target_ant_enhance = fat_tab->target_ant_evm; } else if (utility_ratio >= 6 && force_antenna == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32; + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); + fat_tab->target_ant_enhance = fat_tab->target_ant_crc32; } else { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM)); + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); if (force_antenna == true) - score_CRC = 3; - else if (utility_ratio >= 3) /*>0.5*/ score_CRC = 2; - else if (utility_ratio >= 2) /*>1*/ + else if (utility_ratio >= 5) /*@>2.5*/ + score_CRC = 2; + else if (utility_ratio >= 4) /*@>2*/ score_CRC = 1; else score_CRC = 0; - if (diff_EVM >= 100) + if (diff_EVM >= 15) + score_EVM = 3; + else if (diff_EVM >= 10) score_EVM = 2; - else if (diff_EVM >= 50) + else if (diff_EVM >= 5) score_EVM = 1; else score_EVM = 0; if (score_CRC > score_EVM) - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_crc32; + fat_tab->target_ant_enhance = fat_tab->target_ant_crc32; else if (score_CRC < score_EVM) - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->target_ant_evm; + fat_tab->target_ant_enhance = fat_tab->target_ant_evm; else - p_dm_fat_table->target_ant_enhance = p_dm_fat_table->pre_target_ant_enhance; + fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance; } - p_dm_fat_table->pre_target_ant_enhance = p_dm_fat_table->target_ant_enhance; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MainEVM_Cnt = (( %d )) , main_evm= (( %d ))\n", i, p_dm_fat_table->main_ant_evm_cnt[i], main_evm)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : AuxEVM_Cnt = (( %d )) , aux_evm = (( %d ))\n", i, p_dm_fat_table->aux_ant_evm_cnt[i], aux_evm)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** target_ant_evm = (( %s ))\n", (p_dm_fat_table->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("M_CRC_Ok = (( %d )) , M_CRC_Fail = (( %d )), main_crc_utility = (( %d ))\n", p_dm_fat_table->main_crc32_ok_cnt, p_dm_fat_table->main_crc32_fail_cnt, main_crc_utility)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("A_CRC_Ok = (( %d )) , A_CRC_Fail = (( %d )), aux_crc_utility = (( %d ))\n", p_dm_fat_table->aux_crc32_ok_cnt, p_dm_fat_table->aux_crc32_fail_cnt, aux_crc_utility)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** target_ant_crc32 = (( %s ))\n", (p_dm_fat_table->target_ant_crc32 == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("****** target_ant_enhance = (( %s ))******\n", (p_dm_fat_table->target_ant_enhance == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - + fat_tab->pre_target_ant_enhance = fat_tab->target_ant_enhance; + PHYDM_DBG(dm, DBG_ANT_DIV, "*** 4.TargetAnt_enhance = (( %s ))******\n", (fat_tab->target_ant_enhance == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); } } else { /* RSSI< = evm_rssi_th_low */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ TH_L ]\n")); - odm_evm_fast_ant_reset(p_dm_odm); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ TH_L ]\n"); + odm_evm_fast_ant_reset(dm); } } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[escape from> TH_H || EVM_method_enable==1]\n")); - odm_evm_fast_ant_reset(p_dm_odm); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[escape from> TH_H || evm_method_enable==1]\n"); + odm_evm_fast_ant_reset(dm); } } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[multi-Client]\n")); - odm_evm_fast_ant_reset(p_dm_odm); + PHYDM_DBG(dm, DBG_ANT_DIV, "[multi-Client]\n"); + odm_evm_fast_ant_reset(dm); } } } -void -odm_evm_fast_ant_training_callback( - void *p_dm_void -) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_evm_antdiv_callback( + struct phydm_timer_list *timer) +{ + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + #if USE_WORKITEM + odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem); + #else + { + odm_hw_ant_div(dm); + } + #endif + #else + odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem); + #endif +} + +void phydm_evm_antdiv_workitem_callback( + void *context) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_evm_fast_ant_training_callback******\n")); - odm_hw_ant_div(p_dm_odm); + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + odm_hw_ant_div(dm); } -#endif -void -odm_hw_ant_div( - void *p_dm_void -) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void phydm_evm_antdiv_callback( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0, local_max_rssi; - u32 main_rssi, aux_rssi, mian_cnt, aux_cnt; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u8 rx_idle_ant = p_dm_fat_table->rx_idle_ant, target_ant = 7; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct sta_info *p_entry; + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *padapter = dm->adapter; -#if (BEAMFORMING_SUPPORT == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; - u32 TH1 = 500000; - u32 TH2 = 10000000; - u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp; - u8 monitor_rssi_threshold = 30; + if (*dm->is_net_closed) + return; + if (dm->support_interface == ODM_ITRF_PCIE) { + odm_hw_ant_div(dm); + } else { + /* @Can't do I/O in timer callback*/ + phydm_run_in_thread_cmd(dm, + phydm_evm_antdiv_workitem_callback, + padapter); + } +} - p_dm_bdc_table->BF_pass = true; - p_dm_bdc_table->DIV_pass = true; - p_dm_bdc_table->is_all_div_sta_idle = true; - p_dm_bdc_table->is_all_bf_sta_idle = true; - p_dm_bdc_table->num_bf_tar = 0 ; - p_dm_bdc_table->num_div_tar = 0; - p_dm_bdc_table->num_client = 0; -#endif +void phydm_evm_antdiv_workitem_callback( + void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->odmpriv; + + odm_hw_ant_div(dm); +} + +#else +void phydm_evm_antdiv_callback( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n"); + odm_hw_ant_div(dm); +} #endif - if (!p_dm_odm->is_linked) { /* is_linked==False */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); +#endif - if (p_dm_fat_table->is_become_linked == true) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - p_dm_odm->antdiv_period = 0; +void odm_hw_ant_div( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0, local_max_rssi; + u32 main_rssi, aux_rssi, mian_cnt, aux_cnt; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 rx_idle_ant = fat_tab->rx_idle_ant, target_ant = 7; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct cmn_sta_info *sta; - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + u32 TH1 = 500000; + u32 TH2 = 10000000; + u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp; + u8 monitor_rssi_threshold = 30; + + dm_bdc_table->BF_pass = true; + dm_bdc_table->DIV_pass = true; + dm_bdc_table->is_all_div_sta_idle = true; + dm_bdc_table->is_all_bf_sta_idle = true; + dm_bdc_table->num_bf_tar = 0; + dm_bdc_table->num_div_tar = 0; + dm_bdc_table->num_client = 0; +#endif +#endif + + if (!dm->is_linked) { /* @is_linked==False */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + + if (fat_tab->is_become_linked == true) { + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB); + odm_update_rx_idle_ant(dm, MAIN_ANT); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + dm->antdiv_period = 0; + + fat_tab->is_become_linked = dm->is_linked; } return; } else { - if (p_dm_fat_table->is_become_linked == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - /*odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC);*/ + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB); +#if 0 + /*odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);*/ +#endif - /* if(p_dm_odm->support_ic_type == ODM_RTL8821 ) */ - /* odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); */ /* CCK AntDiv function disable */ +#if 0 + /* @if(dm->support_ic_type == ODM_RTL8821 ) */ + /* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */ /* CCK AntDiv function disable */ +#endif - /* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ - /* else if(p_dm_odm->support_ic_type == ODM_RTL8881A) */ - /* odm_set_bb_reg(p_dm_odm, 0x800, BIT(25), 0); */ /* CCK AntDiv function disable */ - /* #endif */ +#if 0 + /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ + /* @else if(dm->support_ic_type == ODM_RTL8881A) */ + /* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */ /* CCK AntDiv function disable */ + /* @#endif */ +#endif - /* else if(p_dm_odm->support_ic_type == ODM_RTL8723B ||p_dm_odm->support_ic_type == ODM_RTL8812) */ - /* odm_set_bb_reg(p_dm_odm, 0xA00, BIT(15), 0); */ /* CCK AntDiv function disable */ +#if 0 + /* @else if(dm->support_ic_type == ODM_RTL8723B ||dm->support_ic_type == ODM_RTL8812) */ + /* odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); */ /* CCK AntDiv function disable */ +#endif - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + fat_tab->is_become_linked = dm->is_linked; - if (p_dm_odm->support_ic_type == ODM_RTL8723B && p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) { - odm_set_bb_reg(p_dm_odm, 0x930, 0xF0, 8); /* DPDT_P = ANTSEL[0] */ /* for 8723B AntDiv function patch. BB Dino 130412 */ - odm_set_bb_reg(p_dm_odm, 0x930, 0xF, 8); /* DPDT_N = ANTSEL[0] */ + if (dm->support_ic_type == ODM_RTL8723B && dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0] */ /* @for 8723B AntDiv function patch. BB Dino 130412 */ + odm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */ } - /* 2 BDC Init */ +/* @2 BDC Init */ #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - odm_bdc_init(p_dm_odm); + odm_bdc_init(dm); #endif #endif #ifdef ODM_EVM_ENHANCE_ANTDIV - odm_evm_fast_ant_reset(p_dm_odm); + odm_evm_fast_ant_reset(dm); #endif } } - if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { - if (p_dm_odm->is_one_entry_only == true) - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + if (*fat_tab->p_force_tx_ant_by_desc == false) { + if (dm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); else - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); } #ifdef ODM_EVM_ENHANCE_ANTDIV - if (p_dm_odm->antdiv_evm_en == 1) { - odm_evm_enhance_ant_div(p_dm_odm); - if (p_dm_fat_table->fat_state != NORMAL_STATE_MIAN) + if (dm->antdiv_evm_en == 1) { + odm_evm_enhance_ant_div(dm); + if (fat_tab->fat_state_cnt != 0) return; } else - odm_evm_fast_ant_reset(p_dm_odm); + odm_evm_fast_ant_reset(dm); #endif - /* 2 BDC mode Arbitration */ +/* @2 BDC mode Arbitration */ #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_odm->antdiv_evm_en == 0 || p_dm_fat_table->EVM_method_enable == 0) - odm_bf_ant_div_mode_arbitration(p_dm_odm); + if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0) + odm_bf_ant_div_mode_arbitration(dm); #endif #endif for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { - /* 2 Caculate RSSI per Antenna */ - if ((p_dm_fat_table->main_ant_cnt[i] != 0) || (p_dm_fat_table->aux_ant_cnt[i] != 0)) { - mian_cnt = p_dm_fat_table->main_ant_cnt[i]; - aux_cnt = p_dm_fat_table->aux_ant_cnt[i]; - main_rssi = (mian_cnt != 0) ? (p_dm_fat_table->main_ant_sum[i] / mian_cnt) : 0; - aux_rssi = (aux_cnt != 0) ? (p_dm_fat_table->aux_ant_sum[i] / aux_cnt) : 0; - target_ant = (mian_cnt == aux_cnt) ? p_dm_fat_table->rx_idle_ant : ((mian_cnt >= aux_cnt) ? MAIN_ANT : AUX_ANT); /*Use counter number for OFDM*/ - - } else { /*CCK only case*/ - mian_cnt = p_dm_fat_table->main_ant_cnt_cck[i]; - aux_cnt = p_dm_fat_table->aux_ant_cnt_cck[i]; - main_rssi = (mian_cnt != 0) ? (p_dm_fat_table->main_ant_sum_cck[i] / mian_cnt) : 0; - aux_rssi = (aux_cnt != 0) ? (p_dm_fat_table->aux_ant_sum_cck[i] / aux_cnt) : 0; - target_ant = (main_rssi == aux_rssi) ? p_dm_fat_table->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/ + sta = dm->phydm_sta_info[i]; + if (is_sta_active(sta)) { + /* @2 Caculate RSSI per Antenna */ + if (fat_tab->main_ant_cnt[i] != 0 || fat_tab->aux_ant_cnt[i] != 0) { + mian_cnt = fat_tab->main_ant_cnt[i]; + aux_cnt = fat_tab->aux_ant_cnt[i]; + main_rssi = (mian_cnt != 0) ? (fat_tab->main_ant_sum[i] / mian_cnt) : 0; + aux_rssi = (aux_cnt != 0) ? (fat_tab->aux_ant_sum[i] / aux_cnt) : 0; + target_ant = (mian_cnt == aux_cnt) ? fat_tab->rx_idle_ant : ((mian_cnt >= aux_cnt) ? MAIN_ANT : AUX_ANT); /*Use counter number for OFDM*/ + + } else { /*@CCK only case*/ + mian_cnt = fat_tab->main_ant_cnt_cck[i]; + aux_cnt = fat_tab->aux_ant_cnt_cck[i]; + main_rssi = (mian_cnt != 0) ? (fat_tab->main_ant_sum_cck[i] / mian_cnt) : 0; + aux_rssi = (aux_cnt != 0) ? (fat_tab->aux_ant_sum_cck[i] / aux_cnt) : 0; + target_ant = (main_rssi == aux_rssi) ? fat_tab->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/ } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Main_Cnt = (( %d )) , CCK_Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", i, p_dm_fat_table->main_ant_cnt[i], p_dm_fat_table->main_ant_cnt_cck[i], main_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Aux_Cnt = (( %d )) , CCK_Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", i, p_dm_fat_table->aux_ant_cnt[i], p_dm_fat_table->aux_ant_cnt_cck[i], aux_rssi)); - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i ,( target_ant ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** Client[ %d ] : Main_Cnt = (( %d )) , CCK_Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", + i, fat_tab->main_ant_cnt[i], + fat_tab->main_ant_cnt_cck[i], main_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** Client[ %d ] : Aux_Cnt = (( %d )) , CCK_Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", + i, fat_tab->aux_ant_cnt[i], + fat_tab->aux_ant_cnt_cck[i], aux_rssi); +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i ,( target_ant ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"); */ +#endif local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi; - /* 2 Select max_rssi for DIG */ - if ((local_max_rssi > ant_div_max_rssi) && (local_max_rssi < 40)) + /* @2 Select max_rssi for DIG */ + if (local_max_rssi > ant_div_max_rssi && local_max_rssi < 40) ant_div_max_rssi = local_max_rssi; if (local_max_rssi > max_rssi) max_rssi = local_max_rssi; - /* 2 Select RX Idle Antenna */ - if ((local_max_rssi != 0) && (local_max_rssi < min_max_rssi)) { + /* @2 Select RX Idle Antenna */ + if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) { rx_idle_ant = target_ant; min_max_rssi = local_max_rssi; } #ifdef ODM_EVM_ENHANCE_ANTDIV - if (p_dm_odm->antdiv_evm_en == 1) { - if (p_dm_fat_table->target_ant_enhance != 0xFF) { - target_ant = p_dm_fat_table->target_ant_enhance; - rx_idle_ant = p_dm_fat_table->target_ant_enhance; + if (dm->antdiv_evm_en == 1) { + if (fat_tab->target_ant_enhance != 0xFF) { + target_ant = fat_tab->target_ant_enhance; + rx_idle_ant = fat_tab->target_ant_enhance; } } #endif - /* 2 Select TX Antenna */ - if (p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) { + /* @2 Select TX Antenna */ + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) { #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_bdc_table->w_bfee_client[i] == 0) + if (dm_bdc_table->w_bfee_client[i] == 0) #endif #endif { - odm_update_tx_ant(p_dm_odm, target_ant, i); + odm_update_tx_ant(dm, target_ant, i); } } - /* ------------------------------------------------------------ */ +/* @------------------------------------------------------------ */ #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - p_dm_bdc_table->num_client++; + dm_bdc_table->num_client++; - if (p_dm_bdc_table->bdc_mode == BDC_MODE_2 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) { - /* 2 Byte counter */ + if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) { + /* @2 Byte counter */ - ma_rx_temp = (p_entry->rx_byte_cnt_low_maw) << 3 ; /* RX TP ( bit /sec) */ + ma_rx_temp = sta->rx_moving_average_tp; /* RX TP ( bit /sec) */ - if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state) - p_dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp ; + if (dm_bdc_table->BDC_state == bdc_bfer_train_state) + dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp; else - p_dm_bdc_table->MA_rx_TP[i] = ma_rx_temp ; + dm_bdc_table->MA_rx_TP[i] = ma_rx_temp; - if ((ma_rx_temp < TH2) && (ma_rx_temp > TH1) && (local_max_rssi <= monitor_rssi_threshold)) { - if (p_dm_bdc_table->w_bfer_client[i] == 1) { /* Bfer_Target */ - p_dm_bdc_table->num_bf_tar++; + if (ma_rx_temp < TH2 && ma_rx_temp > TH1 && local_max_rssi <= monitor_rssi_threshold) { + if (dm_bdc_table->w_bfer_client[i] == 1) { /* @Bfer_Target */ + dm_bdc_table->num_bf_tar++; - if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE && p_dm_bdc_table->bdc_try_flag == 0) { - improve_TP_temp = (p_dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3 ; /* * 1.125 */ - p_dm_bdc_table->BF_pass = (p_dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d }\n", i, p_dm_bdc_table->MA_rx_TP[i], improve_TP_temp, p_dm_bdc_table->MA_rx_TP_DIV[i], p_dm_bdc_table->BF_pass)); + if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) { + improve_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3; /* @* 1.125 */ + dm_bdc_table->BF_pass = (dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false; + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], improve_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->BF_pass); } - } else { /* DIV_Target */ - p_dm_bdc_table->num_div_tar++; + } else { /* @DIV_Target */ + dm_bdc_table->num_div_tar++; - if (p_dm_bdc_table->BDC_state == BDC_DECISION_STATE && p_dm_bdc_table->bdc_try_flag == 0) { - degrade_TP_temp = (p_dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* * 0.625 */ - p_dm_bdc_table->DIV_pass = (p_dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d }\n", i, p_dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, p_dm_bdc_table->MA_rx_TP_DIV[i], p_dm_bdc_table->DIV_pass)); + if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) { + degrade_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* @* 0.625 */ + dm_bdc_table->DIV_pass = (dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false; + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->DIV_pass); } } } if (ma_rx_temp > TH1) { - if (p_dm_bdc_table->w_bfer_client[i] == 1) /* Bfer_Target */ - p_dm_bdc_table->is_all_bf_sta_idle = false; - else/* DIV_Target */ - p_dm_bdc_table->is_all_div_sta_idle = false; + if (dm_bdc_table->w_bfer_client[i] == 1) /* @Bfer_Target */ + dm_bdc_table->is_all_bf_sta_idle = false; + else /* @DIV_Target */ + dm_bdc_table->is_all_div_sta_idle = false; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { BFmeeCap, BFmerCap} = { %d , %d }\n", i, p_dm_bdc_table->w_bfee_client[i], p_dm_bdc_table->w_bfer_client[i])); + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** Client[ %d ] : { BFmeeCap, BFmerCap} = { %d , %d }\n", + i, dm_bdc_table->w_bfee_client[i], + dm_bdc_table->w_bfer_client[i]); - if (p_dm_bdc_table->BDC_state == bdc_bfer_train_state) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP_DIV = (( %d ))\n", i, p_dm_bdc_table->MA_rx_TP_DIV[i])); + if (dm_bdc_table->BDC_state == bdc_bfer_train_state) + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : MA_rx_TP_DIV = (( %d ))\n", i, dm_bdc_table->MA_rx_TP_DIV[i]); else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP = (( %d ))\n", i, p_dm_bdc_table->MA_rx_TP[i])); - + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : MA_rx_TP = (( %d ))\n", i, dm_bdc_table->MA_rx_TP[i]); } #endif #endif - } #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_bdc_table->bdc_try_flag == 0) + if (dm_bdc_table->bdc_try_flag == 0) #endif #endif { - phydm_antdiv_reset_statistic(p_dm_odm, i); + phydm_antdiv_reset_statistic(dm, i); } } - - - /* 2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */ +/* @2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */ #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** rx_idle_ant = (( %s ))\n\n", (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** rx_idle_ant = (( %s ))\n", + (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_bdc_table->bdc_mode == BDC_MODE_1 || p_dm_bdc_table->bdc_mode == BDC_MODE_3) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** bdc_rx_idle_update_counter = (( %d ))\n", p_dm_bdc_table->bdc_rx_idle_update_counter)); - - if (p_dm_bdc_table->bdc_rx_idle_update_counter == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Update RxIdle Antenna!!!\n")); - p_dm_bdc_table->bdc_rx_idle_update_counter = 30; - odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); + if (dm_bdc_table->bdc_mode == BDC_MODE_1 || dm_bdc_table->bdc_mode == BDC_MODE_3) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** bdc_rx_idle_update_counter = (( %d ))\n", + dm_bdc_table->bdc_rx_idle_update_counter); + + if (dm_bdc_table->bdc_rx_idle_update_counter == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "***Update RxIdle Antenna!!!\n"); + dm_bdc_table->bdc_rx_idle_update_counter = 30; + odm_update_rx_idle_ant(dm, rx_idle_ant); } else { - p_dm_bdc_table->bdc_rx_idle_update_counter--; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n")); + dm_bdc_table->bdc_rx_idle_update_counter--; + PHYDM_DBG(dm, DBG_ANT_DIV, + "***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n"); } } else #endif #endif - odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); + odm_update_rx_idle_ant(dm, rx_idle_ant); #else - odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); - -#endif/* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ + odm_update_rx_idle_ant(dm, rx_idle_ant); +#endif /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ - - /* 2 BDC Main Algorithm */ +/* @2 BDC Main Algorithm */ #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_odm->antdiv_evm_en == 0 || p_dm_fat_table->EVM_method_enable == 0) - odm_bd_ccoex_bfee_rx_div_arbitration(p_dm_odm); + if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0) + odm_bd_ccoex_bfee_rx_div_arbitration(dm); + + dm_bdc_table->num_txbfee_client = 0; + dm_bdc_table->num_txbfer_client = 0; #endif #endif if (ant_div_max_rssi == 0) - p_dm_dig_table->ant_div_rssi_max = p_dm_odm->rssi_min; + dig_t->ant_div_rssi_max = dm->rssi_min; else - p_dm_dig_table->ant_div_rssi_max = ant_div_max_rssi; + dig_t->ant_div_rssi_max = ant_div_max_rssi; - p_dm_dig_table->RSSI_max = max_rssi; + PHYDM_DBG(dm, DBG_ANT_DIV, "***AntDiv End***\n\n"); } - - #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY -void -odm_s0s1_sw_ant_div_reset( - void *p_dm_void -) +void odm_s0s1_sw_ant_div_reset( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - p_dm_fat_table->is_become_linked = false; - p_dm_swat_table->try_flag = SWAW_STEP_INIT; - p_dm_swat_table->double_chk_flag = 0; + fat_tab->is_become_linked = false; + dm_swat_table->try_flag = SWAW_STEP_INIT; + dm_swat_table->double_chk_flag = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_s0s1_sw_ant_div_reset(): p_dm_fat_table->is_become_linked = %d\n", p_dm_fat_table->is_become_linked)); + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: fat_tab->is_become_linked = %d\n", + __func__, fat_tab->is_become_linked); } -void -odm_s0s1_sw_ant_div( - void *p_dm_void, - u8 step -) +void odm_s0s1_sw_ant_div( + void *dm_void, + u8 step) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi; - u32 main_rssi, aux_rssi; - u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0, train_time_temp; - u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0; - u8 rx_idle_ant = p_dm_swat_table->pre_antenna, target_ant, next_ant = 0; - struct sta_info *p_entry = NULL; - u32 value32; - u32 main_ant_sum; - u32 aux_ant_sum; - u32 main_ant_cnt; - u32 aux_ant_cnt; - - - if (!p_dm_odm->is_linked) { /* is_linked==False */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - if (p_dm_fat_table->is_become_linked == true) { - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); - odm_set_bb_reg(p_dm_odm, 0x948, (BIT(9) | BIT(8) | BIT(7) | BIT(6)), 0x0); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi; + u32 main_rssi, aux_rssi; + u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0, train_time_temp; + u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0; + u8 rx_idle_ant = dm_swat_table->pre_antenna, target_ant = dm_swat_table->pre_antenna, next_ant = 0; + struct cmn_sta_info *entry = NULL; + u32 value32; + u32 main_ant_sum = 0; + u32 aux_ant_sum = 0; + u32 main_ant_cnt = 0; + u32 aux_ant_cnt = 0; + + if (!dm->is_linked) { /* @is_linked==False */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + if (fat_tab->is_become_linked == true) { + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + if (dm->support_ic_type == ODM_RTL8723B) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Set REG 948[9:6]=0x0\n"); + odm_set_bb_reg(dm, R_0x948, (BIT(9) | BIT(8) | BIT(7) | BIT(6)), 0x0); } - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + fat_tab->is_become_linked = dm->is_linked; } return; } else { - if (p_dm_fat_table->is_become_linked == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - value32 = odm_get_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT(4) | BIT(3)); + if (dm->support_ic_type == ODM_RTL8723B) { + value32 = odm_get_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3)); #if (RTL8723B_SUPPORT == 1) if (value32 == 0x0) - odm_update_rx_idle_ant_8723b(p_dm_odm, MAIN_ANT, ANT1_2G, ANT2_2G); + odm_update_rx_idle_ant_8723b(dm, MAIN_ANT, ANT1_2G, ANT2_2G); else if (value32 == 0x1) - odm_update_rx_idle_ant_8723b(p_dm_odm, AUX_ANT, ANT2_2G, ANT1_2G); + odm_update_rx_idle_ant_8723b(dm, AUX_ANT, ANT2_2G, ANT1_2G); #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B: First link! Force antenna to %s\n", (value32 == 0x0 ? "MAIN" : "AUX"))); + PHYDM_DBG(dm, DBG_ANT_DIV, + "8723B: First link! Force antenna to %s\n", + (value32 == 0x0 ? "MAIN" : "AUX")); } - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + + if (dm->support_ic_type == ODM_RTL8723D) { + value32 = odm_get_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3)); +#if (RTL8723D_SUPPORT == 1) + if (value32 == 0x0) + odm_update_rx_idle_ant_8723d(dm, MAIN_ANT, ANT1_2G, ANT2_2G); + else if (value32 == 0x1) + odm_update_rx_idle_ant_8723d(dm, AUX_ANT, ANT2_2G, ANT1_2G); + PHYDM_DBG(dm, DBG_ANT_DIV, + "8723D: First link! Force antenna to %s\n", + (value32 == 0x0 ? "MAIN" : "AUX")); +#endif + } + fat_tab->is_become_linked = dm->is_linked; } } - if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { - if (p_dm_odm->is_one_entry_only == true) - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + if (*fat_tab->p_force_tx_ant_by_desc == false) { + if (dm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); else - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n", - __LINE__, p_dm_swat_table->try_flag, step, p_dm_swat_table->double_chk_flag)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n", + __LINE__, dm_swat_table->try_flag, step, + dm_swat_table->double_chk_flag); - /* Handling step mismatch condition. */ + /* @Handling step mismatch condition. */ /* Peak step is not finished at last time. Recover the variable and check again. */ - if (step != p_dm_swat_table->try_flag) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[step != try_flag] Need to Reset After Link\n")); - odm_sw_ant_div_rest_after_link(p_dm_odm); + if (step != dm_swat_table->try_flag) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[step != try_flag] Need to Reset After Link\n"); + odm_sw_ant_div_rest_after_link(dm); } - if (p_dm_swat_table->try_flag == SWAW_STEP_INIT) { - - p_dm_swat_table->try_flag = SWAW_STEP_PEEK; - p_dm_swat_table->train_time_flag = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag = 0] Prepare for peek!\n\n")); + if (dm_swat_table->try_flag == SWAW_STEP_INIT) { + dm_swat_table->try_flag = SWAW_STEP_PEEK; + dm_swat_table->train_time_flag = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[set try_flag = 0] Prepare for peek!\n\n"); return; } else { + /* @1 Normal state (Begin Trying) */ + if (dm_swat_table->try_flag == SWAW_STEP_PEEK) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n", + dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, + dm->traffic_load); - /* 1 Normal state (Begin Trying) */ - if (p_dm_swat_table->try_flag == SWAW_STEP_PEEK) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n", p_dm_odm->cur_tx_ok_cnt, p_dm_odm->cur_rx_ok_cnt, p_dm_odm->traffic_load)); + if (dm->traffic_load == TRAFFIC_HIGH) { + train_time_temp = dm_swat_table->train_time; - if (p_dm_odm->traffic_load == TRAFFIC_HIGH) { - train_time_temp = p_dm_swat_table->train_time ; - - if (p_dm_swat_table->train_time_flag == 3) { + if (dm_swat_table->train_time_flag == 3) { high_traffic_train_time_l = 0xa; if (train_time_temp <= 16) @@ -2602,3087 +3005,1833 @@ odm_s0s1_sw_ant_div( else train_time_temp -= 16; - } else if (p_dm_swat_table->train_time_flag == 2) { + } else if (dm_swat_table->train_time_flag == 2) { train_time_temp -= 8; high_traffic_train_time_l = 0xf; - } else if (p_dm_swat_table->train_time_flag == 1) { + } else if (dm_swat_table->train_time_flag == 1) { train_time_temp -= 4; high_traffic_train_time_l = 0x1e; - } else if (p_dm_swat_table->train_time_flag == 0) { + } else if (dm_swat_table->train_time_flag == 0) { train_time_temp += 8; high_traffic_train_time_l = 0x28; } + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_SDIO) + high_traffic_train_time_l += 0xa; + } - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** train_time_temp = ((%d))\n",train_time_temp)); */ +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "*** train_time_temp = ((%d))\n",train_time_temp); */ +#endif - /* -- */ + /* @-- */ if (train_time_temp > high_traffic_train_time_u) train_time_temp = high_traffic_train_time_u; else if (train_time_temp < high_traffic_train_time_l) train_time_temp = high_traffic_train_time_l; - p_dm_swat_table->train_time = train_time_temp; /*10ms~200ms*/ + dm_swat_table->train_time = train_time_temp; /*@10ms~200ms*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("train_time_flag=((%d)), train_time=((%d))\n", p_dm_swat_table->train_time_flag, p_dm_swat_table->train_time)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "train_time_flag=((%d)), train_time=((%d))\n", + dm_swat_table->train_time_flag, + dm_swat_table->train_time); - } else if ((p_dm_odm->traffic_load == TRAFFIC_MID) || (p_dm_odm->traffic_load == TRAFFIC_LOW)) { + } else if ((dm->traffic_load == TRAFFIC_MID) || (dm->traffic_load == TRAFFIC_LOW)) { + train_time_temp = dm_swat_table->train_time; - train_time_temp = p_dm_swat_table->train_time ; - - if (p_dm_swat_table->train_time_flag == 3) { + if (dm_swat_table->train_time_flag == 3) { low_traffic_train_time_l = 10; if (train_time_temp < 50) train_time_temp = low_traffic_train_time_l; else train_time_temp -= 50; - } else if (p_dm_swat_table->train_time_flag == 2) { + } else if (dm_swat_table->train_time_flag == 2) { train_time_temp -= 30; low_traffic_train_time_l = 36; - } else if (p_dm_swat_table->train_time_flag == 1) { + } else if (dm_swat_table->train_time_flag == 1) { train_time_temp -= 10; low_traffic_train_time_l = 40; } else { - train_time_temp += 10; low_traffic_train_time_l = 50; } - /* -- */ + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_SDIO) + low_traffic_train_time_l += 10; + } + + /* @-- */ if (train_time_temp >= low_traffic_train_time_u) train_time_temp = low_traffic_train_time_u; else if (train_time_temp <= low_traffic_train_time_l) train_time_temp = low_traffic_train_time_l; - p_dm_swat_table->train_time = train_time_temp; /*10ms~200ms*/ + dm_swat_table->train_time = train_time_temp; /*@10ms~200ms*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("train_time_flag=((%d)) , train_time=((%d))\n", p_dm_swat_table->train_time_flag, p_dm_swat_table->train_time)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "train_time_flag=((%d)) , train_time=((%d))\n", + dm_swat_table->train_time_flag, + dm_swat_table->train_time); } else { - p_dm_swat_table->train_time = 0xc8; /*200ms*/ - + dm_swat_table->train_time = 0xc8; /*@200ms*/ } - /* ----------------- */ - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Current min_max_rssi is ((%d))\n", p_dm_fat_table->min_max_rssi)); + /* @----------------- */ - /* ---reset index--- */ - if (p_dm_swat_table->reset_idx >= RSSI_CHECK_RESET_PERIOD) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Current min_max_rssi is ((%d))\n", + fat_tab->min_max_rssi); - p_dm_fat_table->min_max_rssi = 0; - p_dm_swat_table->reset_idx = 0; + /* @---reset index--- */ + if (dm_swat_table->reset_idx >= RSSI_CHECK_RESET_PERIOD) { + fat_tab->min_max_rssi = 0; + dm_swat_table->reset_idx = 0; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reset_idx = (( %d ))\n", p_dm_swat_table->reset_idx)); - - p_dm_swat_table->reset_idx++; - - /* ---double check flag--- */ - if ((p_dm_fat_table->min_max_rssi > RSSI_CHECK_THRESHOLD) && (p_dm_swat_table->double_chk_flag == 0)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" min_max_rssi is ((%d)), and > %d\n", - p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD)); - - p_dm_swat_table->double_chk_flag = 1; - p_dm_swat_table->try_flag = SWAW_STEP_DETERMINE; - p_dm_swat_table->rssi_trying = 0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Test the current ant for (( %d )) ms again\n", p_dm_swat_table->train_time)); - odm_update_rx_idle_ant(p_dm_odm, p_dm_fat_table->rx_idle_ant); - odm_set_timer(p_dm_odm, &(p_dm_swat_table->phydm_sw_antenna_switch_timer), p_dm_swat_table->train_time); /*ms*/ - return; + PHYDM_DBG(dm, DBG_ANT_DIV, "reset_idx = (( %d ))\n", + dm_swat_table->reset_idx); + + dm_swat_table->reset_idx++; + + /* @---double check flag--- */ + if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD && dm_swat_table->double_chk_flag == 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + " min_max_rssi is ((%d)), and > %d\n", + fat_tab->min_max_rssi, + RSSI_CHECK_THRESHOLD); + + dm_swat_table->double_chk_flag = 1; + dm_swat_table->try_flag = SWAW_STEP_DETERMINE; + dm_swat_table->rssi_trying = 0; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Test the current ant for (( %d )) ms again\n", + dm_swat_table->train_time); + odm_update_rx_idle_ant(dm, fat_tab->rx_idle_ant); + odm_set_timer(dm, &dm_swat_table->phydm_sw_antenna_switch_timer, dm_swat_table->train_time); /*@ms*/ + return; } - next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - p_dm_swat_table->try_flag = SWAW_STEP_DETERMINE; + dm_swat_table->try_flag = SWAW_STEP_DETERMINE; - if (p_dm_swat_table->reset_idx <= 1) - p_dm_swat_table->rssi_trying = 2; + if (dm_swat_table->reset_idx <= 1) + dm_swat_table->rssi_trying = 2; else - p_dm_swat_table->rssi_trying = 1; + dm_swat_table->rssi_trying = 1; - odm_s0s1_sw_ant_div_by_ctrl_frame(p_dm_odm, SWAW_STEP_PEEK); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=1] Normal state: Begin Trying!!\n")); + odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_PEEK); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[set try_flag=1] Normal state: Begin Trying!!\n"); - } else if ((p_dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (p_dm_swat_table->double_chk_flag == 0)) { - - next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - p_dm_swat_table->rssi_trying--; + } else if ((dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (dm_swat_table->double_chk_flag == 0)) { + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + dm_swat_table->rssi_trying--; } - /* 1 Decision state */ - if ((p_dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (p_dm_swat_table->rssi_trying == 0)) { - + /* @1 Decision state */ + if (dm_swat_table->try_flag == SWAW_STEP_DETERMINE && dm_swat_table->rssi_trying == 0) { boolean is_by_ctrl_frame = false; - u64 pkt_cnt_total = 0; + u64 pkt_cnt_total = 0; for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { - /* 2 Caculate RSSI per Antenna */ - - main_ant_sum = (u32)p_dm_fat_table->main_ant_sum[i] + (u32)p_dm_fat_table->main_ant_sum_cck[i]; - aux_ant_sum = (u32)p_dm_fat_table->aux_ant_sum[i] + (u32)p_dm_fat_table->aux_ant_sum_cck[i]; - main_ant_cnt = (u32)p_dm_fat_table->main_ant_cnt[i] + (u32)p_dm_fat_table->main_ant_cnt_cck[i]; - aux_ant_cnt = (u32)p_dm_fat_table->aux_ant_cnt[i] + (u32)p_dm_fat_table->aux_ant_cnt_cck[i]; + entry = dm->phydm_sta_info[i]; + if (is_sta_active(entry)) { +/* @2 Caculate RSSI per Antenna */ + #if 0 + main_ant_sum = (u32)fat_tab->main_ant_sum[i] + (u32)fat_tab->main_ant_sum_cck[i]; + aux_ant_sum = (u32)fat_tab->aux_ant_sum[i] + (u32)fat_tab->aux_ant_sum_cck[i]; + main_ant_cnt = (u32)fat_tab->main_ant_cnt[i] + (u32)fat_tab->main_ant_cnt_cck[i]; + aux_ant_cnt = (u32)fat_tab->aux_ant_cnt[i] + (u32)fat_tab->aux_ant_cnt_cck[i]; main_rssi = (main_ant_cnt != 0) ? (main_ant_sum / main_ant_cnt) : 0; aux_rssi = (aux_ant_cnt != 0) ? (aux_ant_sum / aux_ant_cnt) : 0; - if (p_dm_fat_table->main_ant_cnt[i] <= 1 && p_dm_fat_table->main_ant_cnt_cck[i] >= 1) + if (fat_tab->main_ant_cnt[i] <= 1 && fat_tab->main_ant_cnt_cck[i] >= 1) main_rssi = 0; - if (p_dm_fat_table->aux_ant_cnt[i] <= 1 && p_dm_fat_table->aux_ant_cnt_cck[i] >= 1) + if (fat_tab->aux_ant_cnt[i] <= 1 && fat_tab->aux_ant_cnt_cck[i] >= 1) aux_rssi = 0; + #endif + if (fat_tab->main_ant_cnt[i] != 0 || fat_tab->aux_ant_cnt[i] != 0) { + main_ant_cnt = (u32)fat_tab->main_ant_cnt[i]; + aux_ant_cnt = (u32)fat_tab->aux_ant_cnt[i]; + main_rssi = (main_ant_cnt != 0) ? (fat_tab->main_ant_sum[i] / main_ant_cnt) : 0; + aux_rssi = (aux_ant_cnt != 0) ? (fat_tab->aux_ant_sum[i] / aux_ant_cnt) : 0; + if (dm->support_ic_type == ODM_RTL8723D) { + if (dm_swat_table->pre_antenna == MAIN_ANT) { + if (main_ant_cnt == 0) + target_ant = (aux_ant_cnt != 0) ? AUX_ANT : dm_swat_table->pre_antenna; + else + target_ant = ((aux_ant_cnt > main_ant_cnt) && ((main_rssi - aux_rssi < 5) || (aux_rssi > main_rssi))) ? AUX_ANT : dm_swat_table->pre_antenna; + } else { + if (aux_ant_cnt == 0) + target_ant = (main_ant_cnt != 0) ? MAIN_ANT : dm_swat_table->pre_antenna; + else + target_ant = ((main_ant_cnt > aux_ant_cnt) && ((aux_rssi - main_rssi < 5) || (main_rssi > aux_rssi))) ? MAIN_ANT : dm_swat_table->pre_antenna; + } + } else { + if (dm_swat_table->pre_antenna == MAIN_ANT) { + target_ant = ((aux_ant_cnt > 20) && (aux_rssi >= main_rssi)) ? AUX_ANT : dm_swat_table->pre_antenna; + } else if (dm_swat_table->pre_antenna == AUX_ANT) { + target_ant = ((main_ant_cnt > 20) && (main_rssi >= aux_rssi)) ? MAIN_ANT : dm_swat_table->pre_antenna; + } + } + } else { /*@CCK only case*/ + main_ant_cnt = fat_tab->main_ant_cnt_cck[i]; + aux_ant_cnt = fat_tab->aux_ant_cnt_cck[i]; + main_rssi = (main_ant_cnt != 0) ? (fat_tab->main_ant_sum_cck[i] / main_ant_cnt) : 0; + aux_rssi = (aux_ant_cnt != 0) ? (fat_tab->aux_ant_sum_cck[i] / aux_ant_cnt) : 0; + target_ant = (main_rssi == aux_rssi) ? fat_tab->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/ + } + #if 0 + target_ant = (main_rssi == aux_rssi) ? dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); + #endif + local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi; + local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi; + + PHYDM_DBG(dm, DBG_ANT_DIV, "*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d ))\n", fat_tab->main_ant_cnt_cck[i], fat_tab->aux_ant_cnt_cck[i]); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d ))\n", fat_tab->main_ant_cnt[i], fat_tab->aux_ant_cnt[i]); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** main_Cnt = (( %d )) , aux_Cnt = (( %d ))\n", main_ant_cnt, aux_ant_cnt); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** main_rssi= (( %d )) , aux_rssi = (( %d ))\n", main_rssi, aux_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i, (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + + /* @2 Select RX Idle Antenna */ - target_ant = (main_rssi == aux_rssi) ? p_dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); - local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi; - local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d ))\n", p_dm_fat_table->main_ant_cnt_cck[i], p_dm_fat_table->aux_ant_cnt_cck[i])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d ))\n", p_dm_fat_table->main_ant_cnt[i], p_dm_fat_table->aux_ant_cnt[i])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", main_ant_cnt, main_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", aux_ant_cnt, aux_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i, (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT")); - - /* 2 Select RX Idle Antenna */ - if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) { rx_idle_ant = target_ant; min_max_rssi = local_max_rssi; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** local_max_rssi-local_min_rssi = ((%d))\n", (local_max_rssi - local_min_rssi))); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** local_max_rssi-local_min_rssi = ((%d))\n", (local_max_rssi - local_min_rssi)); if ((local_max_rssi - local_min_rssi) > 8) { if (local_min_rssi != 0) - p_dm_swat_table->train_time_flag = 3; + dm_swat_table->train_time_flag = 3; else { if (min_max_rssi > RSSI_CHECK_THRESHOLD) - p_dm_swat_table->train_time_flag = 0; + dm_swat_table->train_time_flag = 0; else - p_dm_swat_table->train_time_flag = 3; + dm_swat_table->train_time_flag = 3; } } else if ((local_max_rssi - local_min_rssi) > 5) - p_dm_swat_table->train_time_flag = 2; + dm_swat_table->train_time_flag = 2; else if ((local_max_rssi - local_min_rssi) > 2) - p_dm_swat_table->train_time_flag = 1; + dm_swat_table->train_time_flag = 1; else - p_dm_swat_table->train_time_flag = 0; - + dm_swat_table->train_time_flag = 0; } - /* 2 Select TX Antenna */ + /* @2 Select TX Antenna */ if (target_ant == MAIN_ANT) - p_dm_fat_table->antsel_a[i] = ANT1_2G; + fat_tab->antsel_a[i] = ANT1_2G; else - p_dm_fat_table->antsel_a[i] = ANT2_2G; - + fat_tab->antsel_a[i] = ANT2_2G; } - phydm_antdiv_reset_statistic(p_dm_odm, i); + phydm_antdiv_reset_statistic(dm, i); pkt_cnt_total += (main_ant_cnt + aux_ant_cnt); } - if (p_dm_swat_table->is_sw_ant_div_by_ctrl_frame) { - odm_s0s1_sw_ant_div_by_ctrl_frame(p_dm_odm, SWAW_STEP_DETERMINE); + if (dm_swat_table->is_sw_ant_div_by_ctrl_frame) { + odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_DETERMINE); is_by_ctrl_frame = true; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Control frame packet counter = %d, data frame packet counter = %llu\n", - p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame, pkt_cnt_total)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "Control frame packet counter = %d, data frame packet counter = %llu\n", + dm_swat_table-> + pkt_cnt_sw_ant_div_by_ctrl_frame, + pkt_cnt_total); - if (min_max_rssi == 0xff || ((pkt_cnt_total < (p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) && p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 2)) { + if (min_max_rssi == 0xff || ((pkt_cnt_total < (dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) && dm->phy_dbg_info.num_qry_beacon_pkt < 2)) { min_max_rssi = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Check RSSI of control frame because min_max_rssi == 0xff\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("is_by_ctrl_frame = %d\n", is_by_ctrl_frame)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "Check RSSI of control frame because min_max_rssi == 0xff\n"); + PHYDM_DBG(dm, DBG_ANT_DIV, + "is_by_ctrl_frame = %d\n", + is_by_ctrl_frame); if (is_by_ctrl_frame) { - main_rssi = (p_dm_fat_table->main_ant_ctrl_frame_cnt != 0) ? (p_dm_fat_table->main_ant_ctrl_frame_sum / p_dm_fat_table->main_ant_ctrl_frame_cnt) : 0; - aux_rssi = (p_dm_fat_table->aux_ant_ctrl_frame_cnt != 0) ? (p_dm_fat_table->aux_ant_ctrl_frame_sum / p_dm_fat_table->aux_ant_ctrl_frame_cnt) : 0; + main_rssi = (fat_tab->main_ant_ctrl_frame_cnt != 0) ? (fat_tab->main_ant_ctrl_frame_sum / fat_tab->main_ant_ctrl_frame_cnt) : 0; + aux_rssi = (fat_tab->aux_ant_ctrl_frame_cnt != 0) ? (fat_tab->aux_ant_ctrl_frame_sum / fat_tab->aux_ant_ctrl_frame_cnt) : 0; - if (p_dm_fat_table->main_ant_ctrl_frame_cnt <= 1 && p_dm_fat_table->cck_ctrl_frame_cnt_main >= 1) + if (fat_tab->main_ant_ctrl_frame_cnt <= 1 && fat_tab->cck_ctrl_frame_cnt_main >= 1) main_rssi = 0; - if (p_dm_fat_table->aux_ant_ctrl_frame_cnt <= 1 && p_dm_fat_table->cck_ctrl_frame_cnt_aux >= 1) + if (fat_tab->aux_ant_ctrl_frame_cnt <= 1 && fat_tab->cck_ctrl_frame_cnt_aux >= 1) aux_rssi = 0; if (main_rssi != 0 || aux_rssi != 0) { - rx_idle_ant = (main_rssi == aux_rssi) ? p_dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); + rx_idle_ant = (main_rssi == aux_rssi) ? dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi; local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi; if ((local_max_rssi - local_min_rssi) > 8) - p_dm_swat_table->train_time_flag = 3; + dm_swat_table->train_time_flag = 3; else if ((local_max_rssi - local_min_rssi) > 5) - p_dm_swat_table->train_time_flag = 2; + dm_swat_table->train_time_flag = 2; else if ((local_max_rssi - local_min_rssi) > 2) - p_dm_swat_table->train_time_flag = 1; + dm_swat_table->train_time_flag = 1; else - p_dm_swat_table->train_time_flag = 0; + dm_swat_table->train_time_flag = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Control frame: main_rssi = %d, aux_rssi = %d\n", main_rssi, aux_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("rx_idle_ant decided by control frame = %s\n", (rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"))); + PHYDM_DBG(dm, DBG_ANT_DIV, "Control frame: main_rssi = %d, aux_rssi = %d\n", main_rssi, aux_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, "rx_idle_ant decided by control frame = %s\n", (rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX")); } } } - p_dm_fat_table->min_max_rssi = min_max_rssi; - p_dm_swat_table->try_flag = SWAW_STEP_PEEK; - - if (p_dm_swat_table->double_chk_flag == 1) { - p_dm_swat_table->double_chk_flag = 0; + fat_tab->min_max_rssi = min_max_rssi; + dm_swat_table->try_flag = SWAW_STEP_PEEK; - if (p_dm_fat_table->min_max_rssi > RSSI_CHECK_THRESHOLD) { + if (dm_swat_table->double_chk_flag == 1) { + dm_swat_table->double_chk_flag = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] min_max_rssi ((%d)) > %d again!!\n", - p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD)); + if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD) { + PHYDM_DBG(dm, DBG_ANT_DIV, " [Double check] min_max_rssi ((%d)) > %d again!!\n", + fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD); - odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); + odm_update_rx_idle_ant(dm, rx_idle_ant); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[reset try_flag = 0] Training accomplished !!!]\n\n\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "[reset try_flag = 0] Training accomplished !!!]\n\n\n"); return; } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] min_max_rssi ((%d)) <= %d !!\n", - p_dm_fat_table->min_max_rssi, RSSI_CHECK_THRESHOLD)); + PHYDM_DBG(dm, DBG_ANT_DIV, " [Double check] min_max_rssi ((%d)) <= %d !!\n", + fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD); - next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - p_dm_swat_table->try_flag = SWAW_STEP_PEEK; - p_dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=0] Normal state: Need to tryg again!!\n\n\n")); + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + dm_swat_table->try_flag = SWAW_STEP_PEEK; + dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD; + PHYDM_DBG(dm, DBG_ANT_DIV, "[set try_flag=0] Normal state: Need to tryg again!!\n\n\n"); return; } } else { - if (p_dm_fat_table->min_max_rssi < RSSI_CHECK_THRESHOLD) - p_dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD; + if (fat_tab->min_max_rssi < RSSI_CHECK_THRESHOLD) + dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD; - p_dm_swat_table->pre_antenna = rx_idle_ant; - odm_update_rx_idle_ant(p_dm_odm, rx_idle_ant); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[reset try_flag = 0] Training accomplished !!!] \n\n\n")); + dm_swat_table->pre_antenna = rx_idle_ant; + odm_update_rx_idle_ant(dm, rx_idle_ant); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[reset try_flag = 0] Training accomplished !!!]\n\n\n"); return; } - } - } - /* 1 4.Change TRX antenna */ + /* @1 4.Change TRX antenna */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("rssi_trying = (( %d )), ant: (( %s )) >>> (( %s ))\n", - p_dm_swat_table->rssi_trying, (p_dm_fat_table->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"), (next_ant == MAIN_ANT ? "MAIN" : "AUX"))); + PHYDM_DBG(dm, DBG_ANT_DIV, + "rssi_trying = (( %d )), ant: (( %s )) >>> (( %s ))\n", + dm_swat_table->rssi_trying, + (fat_tab->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"), + (next_ant == MAIN_ANT ? "MAIN" : "AUX")); - odm_update_rx_idle_ant(p_dm_odm, next_ant); + odm_update_rx_idle_ant(dm, next_ant); - /* 1 5.Reset Statistics */ + /* @1 5.Reset Statistics */ - p_dm_fat_table->rx_idle_ant = next_ant; + fat_tab->rx_idle_ant = next_ant; - /* 1 6.Set next timer (Trying state) */ + if (dm->support_ic_type == ODM_RTL8723D) { + if (fat_tab->rx_idle_ant == MAIN_ANT) { + fat_tab->main_ant_sum[0] = 0; + fat_tab->main_ant_cnt[0] = 0; + fat_tab->main_ant_sum_cck[0] = 0; + fat_tab->main_ant_cnt_cck[0] = 0; + } else { + fat_tab->aux_ant_sum[0] = 0; + fat_tab->aux_ant_cnt[0] = 0; + fat_tab->aux_ant_sum_cck[0] = 0; + fat_tab->aux_ant_cnt_cck[0] = 0; + } + } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test ((%s)) ant for (( %d )) ms\n", (next_ant == MAIN_ANT ? "MAIN" : "AUX"), p_dm_swat_table->train_time)); - odm_set_timer(p_dm_odm, &(p_dm_swat_table->phydm_sw_antenna_switch_timer), p_dm_swat_table->train_time); /*ms*/ -} + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_SDIO) { + ODM_delay_us(200); + if (fat_tab->rx_idle_ant == MAIN_ANT) { + fat_tab->main_ant_sum[0] = 0; + fat_tab->main_ant_cnt[0] = 0; + fat_tab->main_ant_sum_cck[0] = 0; + fat_tab->main_ant_cnt_cck[0] = 0; + } else { + fat_tab->aux_ant_sum[0] = 0; + fat_tab->aux_ant_cnt[0] = 0; + fat_tab->aux_ant_sum_cck[0] = 0; + fat_tab->aux_ant_cnt_cck[0] = 0; + } + } + } + /* @1 6.Set next timer (Trying state) */ + PHYDM_DBG(dm, DBG_ANT_DIV, " Test ((%s)) ant for (( %d )) ms\n", + (next_ant == MAIN_ANT ? "MAIN" : "AUX"), + dm_swat_table->train_time); + odm_set_timer(dm, &dm_swat_table->phydm_sw_antenna_switch_timer, + dm_swat_table->train_time); /*@ms*/ +} #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -odm_sw_antdiv_callback( - struct timer_list *p_timer -) +void odm_sw_antdiv_callback( + struct phydm_timer_list *timer) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct _sw_antenna_switch_ *p_dm_swat_table = &p_hal_data->DM_OutSrc.dm_swat_table; + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct sw_antenna_switch *dm_swat_table = &hal_data->DM_OutSrc.dm_swat_table; #if DEV_BUS_TYPE == RT_PCI_INTERFACE #if USE_WORKITEM - odm_schedule_work_item(&p_dm_swat_table->phydm_sw_antenna_switch_workitem); + odm_schedule_work_item(&dm_swat_table->phydm_sw_antenna_switch_workitem); #else { - /* dbg_print("SW_antdiv_Callback"); */ - odm_s0s1_sw_ant_div(&p_hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); +#if 0 + /* @dbg_print("SW_antdiv_Callback"); */ +#endif + odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); } #endif #else - odm_schedule_work_item(&p_dm_swat_table->phydm_sw_antenna_switch_workitem); + odm_schedule_work_item(&dm_swat_table->phydm_sw_antenna_switch_workitem); #endif } -void -odm_sw_antdiv_workitem_callback( - void *p_context -) +void odm_sw_antdiv_workitem_callback( + void *context) { - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - /* dbg_print("SW_antdiv_Workitem_Callback"); */ - odm_s0s1_sw_ant_div(&p_hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); +#if 0 + /* @dbg_print("SW_antdiv_Workitem_Callback"); */ +#endif + odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); } #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -void -odm_sw_antdiv_workitem_callback( - void *p_context -) +void odm_sw_antdiv_workitem_callback( + void *context) { - struct _ADAPTER * - p_adapter = (struct _ADAPTER *)p_context; + void * + adapter = (void *)context; HAL_DATA_TYPE - *p_hal_data = GET_HAL_DATA(p_adapter); + *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - /*dbg_print("SW_antdiv_Workitem_Callback");*/ - odm_s0s1_sw_ant_div(&p_hal_data->odmpriv, SWAW_STEP_DETERMINE); +#if 0 + /*@dbg_print("SW_antdiv_Workitem_Callback");*/ +#endif + odm_s0s1_sw_ant_div(&hal_data->odmpriv, SWAW_STEP_DETERMINE); } -void -odm_sw_antdiv_callback(void *function_context) +void odm_sw_antdiv_callback(void *function_context) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)function_context; - struct _ADAPTER *padapter = p_dm_odm->adapter; - if (padapter->net_closed == _TRUE) + struct dm_struct *dm = (struct dm_struct *)function_context; + void *padapter = dm->adapter; + if (*dm->is_net_closed == true) return; -#if 0 /* Can't do I/O in timer callback*/ - odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_DETERMINE); +#if 0 /* @Can't do I/O in timer callback*/ + odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE); #else rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter); #endif } - #endif -void -odm_s0s1_sw_ant_div_by_ctrl_frame( - void *p_dm_void, - u8 step -) +void odm_s0s1_sw_ant_div_by_ctrl_frame( + void *dm_void, + u8 step) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; switch (step) { case SWAW_STEP_PEEK: - p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame = 0; - p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = true; - p_dm_fat_table->main_ant_ctrl_frame_cnt = 0; - p_dm_fat_table->aux_ant_ctrl_frame_cnt = 0; - p_dm_fat_table->main_ant_ctrl_frame_sum = 0; - p_dm_fat_table->aux_ant_ctrl_frame_sum = 0; - p_dm_fat_table->cck_ctrl_frame_cnt_main = 0; - p_dm_fat_table->cck_ctrl_frame_cnt_aux = 0; - p_dm_fat_table->ofdm_ctrl_frame_cnt_main = 0; - p_dm_fat_table->ofdm_ctrl_frame_cnt_aux = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n")); + dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame = 0; + dm_swat_table->is_sw_ant_div_by_ctrl_frame = true; + fat_tab->main_ant_ctrl_frame_cnt = 0; + fat_tab->aux_ant_ctrl_frame_cnt = 0; + fat_tab->main_ant_ctrl_frame_sum = 0; + fat_tab->aux_ant_ctrl_frame_sum = 0; + fat_tab->cck_ctrl_frame_cnt_main = 0; + fat_tab->cck_ctrl_frame_cnt_aux = 0; + fat_tab->ofdm_ctrl_frame_cnt_main = 0; + fat_tab->ofdm_ctrl_frame_cnt_aux = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n"); break; case SWAW_STEP_DETERMINE: - p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Stop peek\n")); + dm_swat_table->is_sw_ant_div_by_ctrl_frame = false; + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_S0S1_SwAntDivForAPMode(): Stop peek\n"); break; default: - p_dm_swat_table->is_sw_ant_div_by_ctrl_frame = false; + dm_swat_table->is_sw_ant_div_by_ctrl_frame = false; break; } } -void -odm_antsel_statistics_of_ctrl_frame( - void *p_dm_void, - u8 antsel_tr_mux, - u32 rx_pwdb_all +void odm_antsel_statistics_of_ctrl_frame( + void *dm_void, + u8 antsel_tr_mux, + u32 rx_pwdb_all -) + ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; if (antsel_tr_mux == ANT1_2G) { - p_dm_fat_table->main_ant_ctrl_frame_sum += rx_pwdb_all; - p_dm_fat_table->main_ant_ctrl_frame_cnt++; + fat_tab->main_ant_ctrl_frame_sum += rx_pwdb_all; + fat_tab->main_ant_ctrl_frame_cnt++; } else { - p_dm_fat_table->aux_ant_ctrl_frame_sum += rx_pwdb_all; - p_dm_fat_table->aux_ant_ctrl_frame_cnt++; + fat_tab->aux_ant_ctrl_frame_sum += rx_pwdb_all; + fat_tab->aux_ant_ctrl_frame_cnt++; } } -void -odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void - /* struct _odm_phy_status_info_* p_phy_info, */ - /* struct _odm_per_pkt_info_* p_pktinfo */ -) +void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi( + void *dm_void, + void *phy_info_void, + void *pkt_info_void + /* struct phydm_phyinfo_struct* phy_info, */ + /* struct phydm_perpkt_info_struct* pktinfo */ + ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; - struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - boolean is_cck_rate; - - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + if (!(dm->support_ability & ODM_BB_ANT_DIV)) return; - if (p_dm_odm->ant_div_type != S0S1_SW_ANTDIV) + if (dm->ant_div_type != S0S1_SW_ANTDIV) return; - /* In try state */ - if (!p_dm_swat_table->is_sw_ant_div_by_ctrl_frame) + /* @In try state */ + if (!dm_swat_table->is_sw_ant_div_by_ctrl_frame) return; /* No HW error and match receiver address */ - if (!p_pktinfo->is_to_self) + if (!pktinfo->is_to_self) return; - p_dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame++; - is_cck_rate = ((p_pktinfo->data_rate >= DESC_RATE1M) && (p_pktinfo->data_rate <= DESC_RATE11M)) ? true : false; + dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame++; - if (is_cck_rate) { - p_dm_fat_table->antsel_rx_keep_0 = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; + if (pktinfo->is_cck_rate) { + fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; - if (p_dm_fat_table->antsel_rx_keep_0 == ANT1_2G) - p_dm_fat_table->cck_ctrl_frame_cnt_main++; + if (fat_tab->antsel_rx_keep_0 == ANT1_2G) + fat_tab->cck_ctrl_frame_cnt_main++; else - p_dm_fat_table->cck_ctrl_frame_cnt_aux++; + fat_tab->cck_ctrl_frame_cnt_aux++; - odm_antsel_statistics_of_ctrl_frame(p_dm_odm, p_dm_fat_table->antsel_rx_keep_0, p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]); + odm_antsel_statistics_of_ctrl_frame(dm, fat_tab->antsel_rx_keep_0, phy_info->rx_mimo_signal_strength[RF_PATH_A]); } else { - if (p_dm_fat_table->antsel_rx_keep_0 == ANT1_2G) - p_dm_fat_table->ofdm_ctrl_frame_cnt_main++; + fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; + + if (fat_tab->antsel_rx_keep_0 == ANT1_2G) + fat_tab->ofdm_ctrl_frame_cnt_main++; else - p_dm_fat_table->ofdm_ctrl_frame_cnt_aux++; + fat_tab->ofdm_ctrl_frame_cnt_aux++; - odm_antsel_statistics_of_ctrl_frame(p_dm_odm, p_dm_fat_table->antsel_rx_keep_0, p_phy_info->rx_pwdb_all); + odm_antsel_statistics_of_ctrl_frame(dm, fat_tab->antsel_rx_keep_0, phy_info->rx_pwdb_all); } } -#endif /* #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */ - - +#endif /* @#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */ - -void -odm_set_next_mac_addr_target( - void *p_dm_void -) +void odm_set_next_mac_addr_target( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct sta_info *p_entry; - u32 value32, i; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct cmn_sta_info *entry; + u32 value32, i; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_set_next_mac_addr_target() ==>\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "%s ==>\n", __func__); - if (p_dm_odm->is_linked) { + if (dm->is_linked) { for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - if ((p_dm_fat_table->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM) - p_dm_fat_table->train_idx = 0; + if ((fat_tab->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM) + fat_tab->train_idx = 0; else - p_dm_fat_table->train_idx++; + fat_tab->train_idx++; - p_entry = p_dm_odm->p_odm_sta_info[p_dm_fat_table->train_idx]; + entry = dm->phydm_sta_info[fat_tab->train_idx]; - if (IS_STA_VALID(p_entry)) { + if (is_sta_active(entry)) { + /*@Match MAC ADDR*/ + value32 = (entry->mac_addr[5] << 8) | entry->mac_addr[4]; - /*Match MAC ADDR*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - value32 = (p_entry->hwaddr[5] << 8) | p_entry->hwaddr[4]; -#else - value32 = (p_entry->MacAddr[5] << 8) | p_entry->MacAddr[4]; -#endif + odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, value32); /*@0x7b4~0x7b5*/ - odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, value32);/*0x7b4~0x7b5*/ + value32 = (entry->mac_addr[3] << 24) | (entry->mac_addr[2] << 16) | (entry->mac_addr[1] << 8) | entry->mac_addr[0]; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - value32 = (p_entry->hwaddr[3] << 24) | (p_entry->hwaddr[2] << 16) | (p_entry->hwaddr[1] << 8) | p_entry->hwaddr[0]; -#else - value32 = (p_entry->MacAddr[3] << 24) | (p_entry->MacAddr[2] << 16) | (p_entry->MacAddr[1] << 8) | p_entry->MacAddr[0]; -#endif - odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, value32);/*0x7b0~0x7b3*/ + odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, value32); /*@0x7b0~0x7b3*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_dm_fat_table->train_idx=%d\n", p_dm_fat_table->train_idx)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "fat_tab->train_idx=%d\n", + fat_tab->train_idx); -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC addr = %x:%x:%x:%x:%x:%x\n", - p_entry->hwaddr[5], p_entry->hwaddr[4], p_entry->hwaddr[3], p_entry->hwaddr[2], p_entry->hwaddr[1], p_entry->hwaddr[0])); -#else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC addr = %x:%x:%x:%x:%x:%x\n", - p_entry->MacAddr[5], p_entry->MacAddr[4], p_entry->MacAddr[3], p_entry->MacAddr[2], p_entry->MacAddr[1], p_entry->MacAddr[0])); -#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "Training MAC addr = %x:%x:%x:%x:%x:%x\n", + entry->mac_addr[5], + entry->mac_addr[4], + entry->mac_addr[3], + entry->mac_addr[2], + entry->mac_addr[1], + entry->mac_addr[0]); break; } } } - -#if 0 - /* */ - /* 2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn */ - /* */ -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - { - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - - for (i = 0; i < 6; i++) { - bssid[i] = p_mgnt_info->bssid[i]; - /* dbg_print("bssid[%d]=%x\n", i, bssid[i]); */ - } - } -#endif - - /* odm_set_next_mac_addr_target(p_dm_odm); */ - - /* 1 Select MAC Address Filter */ - for (i = 0; i < 6; i++) { - if (bssid[i] != p_dm_fat_table->bssid[i]) { - is_match_bssid = false; - break; - } - } - if (is_match_bssid == false) { - /* Match MAC ADDR */ - value32 = (bssid[5] << 8) | bssid[4]; - odm_set_mac_reg(p_dm_odm, 0x7b4, 0xFFFF, value32); - value32 = (bssid[3] << 24) | (bssid[2] << 16) | (bssid[1] << 8) | bssid[0]; - odm_set_mac_reg(p_dm_odm, 0x7b0, MASKDWORD, value32); - } - - return is_match_bssid; -#endif - } #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) -void -odm_fast_ant_training( - void *p_dm_void -) +void odm_fast_ant_training( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - u32 max_rssi_path_a = 0, pckcnt_path_a = 0; - u8 i, target_ant_path_a = 0; - boolean is_pkt_filter_macth_path_a = false; + u32 max_rssi_path_a = 0, pckcnt_path_a = 0; + u8 i, target_ant_path_a = 0; + boolean is_pkt_filter_macth_path_a = false; #if (RTL8192E_SUPPORT == 1) - u32 max_rssi_path_b = 0, pckcnt_path_b = 0; - u8 target_ant_path_b = 0; - boolean is_pkt_filter_macth_path_b = false; + u32 max_rssi_path_b = 0, pckcnt_path_b = 0; + u8 target_ant_path_b = 0; + boolean is_pkt_filter_macth_path_b = false; #endif + if (!dm->is_linked) { /* @is_linked==False */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); - if (!p_dm_odm->is_linked) { /* is_linked==False */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - - if (p_dm_fat_table->is_become_linked == true) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - phydm_fast_training_enable(p_dm_odm, FAT_OFF); - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + if (fat_tab->is_become_linked == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + phydm_fast_training_enable(dm, FAT_OFF); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + fat_tab->is_become_linked = dm->is_linked; } return; } else { - if (p_dm_fat_table->is_become_linked == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked!!!]\n")); - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked!!!]\n"); + fat_tab->is_become_linked = dm->is_linked; } } - if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { - if (p_dm_odm->is_one_entry_only == true) - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + if (*fat_tab->p_force_tx_ant_by_desc == false) { + if (dm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); else - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); } - - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - odm_set_bb_reg(p_dm_odm, 0x864, BIT(2) | BIT(1) | BIT(0), ((p_dm_odm->fat_comb_a) - 1)); + if (dm->support_ic_type == ODM_RTL8188E) + odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); #if (RTL8192E_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(2) | BIT1 | BIT0, ((p_dm_odm->fat_comb_a) - 1)); /* path-A */ /* ant combination=regB38[2:0]+1 */ - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(18) | BIT17 | BIT16, ((p_dm_odm->fat_comb_b) - 1)); /* path-B */ /* ant combination=regB38[18:16]+1 */ + else if (dm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(dm, R_0xb38, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); /* path-A */ /* ant combination=regB38[2:0]+1 */ + odm_set_bb_reg(dm, R_0xb38, BIT(18) | BIT(17) | BIT(16), ((dm->fat_comb_b) - 1)); /* path-B */ /* ant combination=regB38[18:16]+1 */ } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_fast_ant_training()\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "==>%s\n", __func__); - /* 1 TRAINING STATE */ - if (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) { - /* 2 Caculate RSSI per Antenna */ + /* @1 TRAINING STATE */ + if (fat_tab->fat_state == FAT_TRAINING_STATE) { + /* @2 Caculate RSSI per Antenna */ - /* 3 [path-A]--------------------------- */ - for (i = 0; i < (p_dm_odm->fat_comb_a); i++) { /* i : antenna index */ - if (p_dm_fat_table->ant_rssi_cnt[i] == 0) - p_dm_fat_table->ant_ave_rssi[i] = 0; + /* @3 [path-A]--------------------------- */ + for (i = 0; i < (dm->fat_comb_a); i++) { /* @i : antenna index */ + if (fat_tab->ant_rssi_cnt[i] == 0) + fat_tab->ant_ave_rssi[i] = 0; else { - p_dm_fat_table->ant_ave_rssi[i] = p_dm_fat_table->ant_sum_rssi[i] / p_dm_fat_table->ant_rssi_cnt[i]; + fat_tab->ant_ave_rssi[i] = fat_tab->ant_sum_rssi[i] / fat_tab->ant_rssi_cnt[i]; is_pkt_filter_macth_path_a = true; } - if (p_dm_fat_table->ant_ave_rssi[i] > max_rssi_path_a) { - max_rssi_path_a = p_dm_fat_table->ant_ave_rssi[i]; - pckcnt_path_a = p_dm_fat_table->ant_rssi_cnt[i]; - target_ant_path_a = i ; - } else if (p_dm_fat_table->ant_ave_rssi[i] == max_rssi_path_a) { - if ((p_dm_fat_table->ant_rssi_cnt[i]) > pckcnt_path_a) { - max_rssi_path_a = p_dm_fat_table->ant_ave_rssi[i]; - pckcnt_path_a = p_dm_fat_table->ant_rssi_cnt[i]; - target_ant_path_a = i ; + if (fat_tab->ant_ave_rssi[i] > max_rssi_path_a) { + max_rssi_path_a = fat_tab->ant_ave_rssi[i]; + pckcnt_path_a = fat_tab->ant_rssi_cnt[i]; + target_ant_path_a = i; + } else if (fat_tab->ant_ave_rssi[i] == max_rssi_path_a) { + if (fat_tab->ant_rssi_cnt[i] > pckcnt_path_a) { + max_rssi_path_a = fat_tab->ant_ave_rssi[i]; + pckcnt_path_a = fat_tab->ant_rssi_cnt[i]; + target_ant_path_a = i; } } - ODM_RT_TRACE("*** ant-index : [ %d ], counter = (( %d )), Avg RSSI = (( %d ))\n", i, p_dm_fat_table->ant_rssi_cnt[i], p_dm_fat_table->ant_ave_rssi[i]); + PHYDM_DBG( + "*** ant-index : [ %d ], counter = (( %d )), Avg RSSI = (( %d ))\n", + i, fat_tab->ant_rssi_cnt[i], + fat_tab->ant_ave_rssi[i]); } - #if 0 #if (RTL8192E_SUPPORT == 1) - /* 3 [path-B]--------------------------- */ - for (i = 0; i < (p_dm_odm->fat_comb_b); i++) { - if (p_dm_fat_table->antRSSIcnt_pathB[i] == 0) - p_dm_fat_table->antAveRSSI_pathB[i] = 0; - else { /* (ant_rssi_cnt[i] != 0) */ - p_dm_fat_table->antAveRSSI_pathB[i] = p_dm_fat_table->antSumRSSI_pathB[i] / p_dm_fat_table->antRSSIcnt_pathB[i]; + /* @3 [path-B]--------------------------- */ + for (i = 0; i < (dm->fat_comb_b); i++) { + if (fat_tab->antRSSIcnt_pathB[i] == 0) + fat_tab->antAveRSSI_pathB[i] = 0; + else { /* @(ant_rssi_cnt[i] != 0) */ + fat_tab->antAveRSSI_pathB[i] = fat_tab->antSumRSSI_pathB[i] / fat_tab->antRSSIcnt_pathB[i]; is_pkt_filter_macth_path_b = true; } - if (p_dm_fat_table->antAveRSSI_pathB[i] > max_rssi_path_b) { - max_rssi_path_b = p_dm_fat_table->antAveRSSI_pathB[i]; - pckcnt_path_b = p_dm_fat_table->antRSSIcnt_pathB[i]; - target_ant_path_b = (u8) i; + if (fat_tab->antAveRSSI_pathB[i] > max_rssi_path_b) { + max_rssi_path_b = fat_tab->antAveRSSI_pathB[i]; + pckcnt_path_b = fat_tab->antRSSIcnt_pathB[i]; + target_ant_path_b = (u8)i; } - if (p_dm_fat_table->antAveRSSI_pathB[i] == max_rssi_path_b) { - if (p_dm_fat_table->antRSSIcnt_pathB > pckcnt_path_b) { - max_rssi_path_b = p_dm_fat_table->antAveRSSI_pathB[i]; - target_ant_path_b = (u8) i; + if (fat_tab->antAveRSSI_pathB[i] == max_rssi_path_b) { + if (fat_tab->antRSSIcnt_pathB > pckcnt_path_b) { + max_rssi_path_b = fat_tab->antAveRSSI_pathB[i]; + target_ant_path_b = (u8)i; } } - if (p_dm_odm->fat_print_rssi == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d ))\n", - i, p_dm_fat_table->antSumRSSI_pathB[i], i, p_dm_fat_table->antRSSIcnt_pathB[i], i, p_dm_fat_table->antAveRSSI_pathB[i])); + if (dm->fat_print_rssi == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "***{path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d ))\n", + i, fat_tab->antSumRSSI_pathB[i], i, + fat_tab->antRSSIcnt_pathB[i], i, + fat_tab->antAveRSSI_pathB[i]); } } #endif #endif - /* 1 DECISION STATE */ + /* @1 DECISION STATE */ - /* 2 Select TRX Antenna */ + /* @2 Select TRX Antenna */ - phydm_fast_training_enable(p_dm_odm, FAT_OFF); + phydm_fast_training_enable(dm, FAT_OFF); - /* 3 [path-A]--------------------------- */ - if (is_pkt_filter_macth_path_a == false) { - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{path-A}: None Packet is matched\n")); */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{path-A}: None Packet is matched\n")); - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + /* @3 [path-A]--------------------------- */ + if (is_pkt_filter_macth_path_a == false) { +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "{path-A}: None Packet is matched\n"); */ +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "{path-A}: None Packet is matched\n"); + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); } else { - ODM_RT_TRACE("target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n", target_ant_path_a, max_rssi_path_a); + PHYDM_DBG( + "target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n", + target_ant_path_a, max_rssi_path_a); - /* 3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT */ - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(8) | BIT7 | BIT6, target_ant_path_a); /* Optional RX [pth-A] */ - } - /* 3 [ update TX ant ] */ - odm_update_tx_ant(p_dm_odm, target_ant_path_a, (p_dm_fat_table->train_idx)); + /* @3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT */ + if (dm->support_ic_type == ODM_RTL8188E) + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); + else if (dm->support_ic_type == ODM_RTL8192E) + odm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); /* Optional RX [pth-A] */ + + /* @3 [ update TX ant ] */ + odm_update_tx_ant(dm, target_ant_path_a, (fat_tab->train_idx)); if (target_ant_path_a == 0) - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); } #if 0 #if (RTL8192E_SUPPORT == 1) - /* 3 [path-B]--------------------------- */ + /* @3 [path-B]--------------------------- */ if (is_pkt_filter_macth_path_b == false) { - if (p_dm_odm->fat_print_rssi == 1) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***[%d]{path-B}: None Packet is matched\n\n\n", __LINE__)); + if (dm->fat_print_rssi == 1) + PHYDM_DBG(dm, DBG_ANT_DIV, + "***[%d]{path-B}: None Packet is matched\n\n\n", + __LINE__); } else { - if (p_dm_odm->fat_print_rssi == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, - (" ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n", target_ant_path_b, max_rssi_path_b)); + if (dm->fat_print_rssi == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, + " ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n", + target_ant_path_b, max_rssi_path_b); } - odm_set_bb_reg(p_dm_odm, 0xB38, BIT(21) | BIT20 | BIT19, target_ant_path_b); /* Default RX is Omni, Optional RX is the best decision by FAT */ - odm_set_bb_reg(p_dm_odm, 0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 //from TX Info */ + odm_set_bb_reg(dm, R_0xb38, BIT(21) | BIT20 | BIT19, target_ant_path_b); /* @Default RX is Omni, Optional RX is the best decision by FAT */ + odm_set_bb_reg(dm, R_0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 //from TX Info */ - p_dm_fat_table->antsel_pathB[p_dm_fat_table->train_idx] = target_ant_path_b; + fat_tab->antsel_pathB[fat_tab->train_idx] = target_ant_path_b; } #endif #endif - /* 2 Reset counter */ - for (i = 0; i < (p_dm_odm->fat_comb_a); i++) { - p_dm_fat_table->ant_sum_rssi[i] = 0; - p_dm_fat_table->ant_rssi_cnt[i] = 0; + /* @2 Reset counter */ + for (i = 0; i < (dm->fat_comb_a); i++) { + fat_tab->ant_sum_rssi[i] = 0; + fat_tab->ant_rssi_cnt[i] = 0; } - /* + /*@ #if (RTL8192E_SUPPORT == 1) - for(i=0; i<=(p_dm_odm->fat_comb_b); i++) + for(i=0; i<=(dm->fat_comb_b); i++) { - p_dm_fat_table->antSumRSSI_pathB[i] = 0; - p_dm_fat_table->antRSSIcnt_pathB[i] = 0; + fat_tab->antSumRSSI_pathB[i] = 0; + fat_tab->antRSSIcnt_pathB[i] = 0; } #endif */ - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; + fat_tab->fat_state = FAT_PREPARE_STATE; return; } - /* 1 NORMAL STATE */ - if (p_dm_fat_table->fat_state == FAT_PREPARE_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Start Prepare state ]\n")); + /* @1 NORMAL STATE */ + if (fat_tab->fat_state == FAT_PREPARE_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Start Prepare state ]\n"); - odm_set_next_mac_addr_target(p_dm_odm); + odm_set_next_mac_addr_target(dm); - /* 2 Prepare Training */ - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - phydm_fast_training_enable(p_dm_odm, FAT_ON); - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); /* enable HW AntDiv */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Start Training state]\n")); + /* @2 Prepare Training */ + fat_tab->fat_state = FAT_TRAINING_STATE; + phydm_fast_training_enable(dm, FAT_ON); + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + /* @enable HW AntDiv */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[Start Training state]\n"); - odm_set_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer, p_dm_odm->antdiv_intvl); /* ms */ + odm_set_timer(dm, &dm->fast_ant_training_timer, dm->antdiv_intvl); /* @ms */ } - } -void -odm_fast_ant_training_callback( - void *p_dm_void -) +void odm_fast_ant_training_callback( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct _ADAPTER *padapter = p_dm_odm->adapter; - if (padapter->net_closed == _TRUE) + if (*(dm->is_net_closed) == true) return; - /* if(*p_dm_odm->p_is_net_closed == true) */ - /* return; */ #endif #if USE_WORKITEM - odm_schedule_work_item(&p_dm_odm->fast_ant_training_workitem); + odm_schedule_work_item(&dm->fast_ant_training_workitem); #else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_fast_ant_training_callback******\n")); - odm_fast_ant_training(p_dm_odm); + PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__); + odm_fast_ant_training(dm); #endif } -void -odm_fast_ant_training_work_item_callback( - void *p_dm_void -) +void odm_fast_ant_training_work_item_callback( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_fast_ant_training_work_item_callback******\n")); - odm_fast_ant_training(p_dm_odm); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__); + odm_fast_ant_training(dm); } #endif -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - -u32 -phydm_construct_hb_rfu_codeword_type2( - void *p_dm_void, - u32 beam_set_idx -) +void odm_ant_div_init( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 sync_codeword = 0x7f; - u32 codeword = 0; - u32 data_tmp = 0; - u32 i; - - for (i = 0; i < pdm_sat_table->ant_num_total; i++) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[beam_set_idx][i]; - else - data_tmp = pdm_sat_table->rfu_codeword_table_2g[beam_set_idx][i]; - - codeword |= (data_tmp << (i * pdm_sat_table->rfu_each_ant_bit_num)); + if (!(dm->support_ability & ODM_BB_ANT_DIV)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] Not Support Antenna Diversity Function\n"); + return; } +/* @--- */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n"); + if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) + return; + } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n"); + if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) + return; + } else if (fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G)) + PHYDM_DBG(dm, DBG_ANT_DIV, + "[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n"); - codeword = (codeword<<8) | sync_codeword; - - return codeword; -} - -void -phydm_update_beam_pattern_type2( - void *p_dm_void, - u32 codeword, - u32 codeword_length -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u8 i; - boolean beam_ctrl_signal; - u32 one = 0x1; - u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; - u8 devide_num = 4; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set codeword = ((0x%x))\n", codeword)); - - reg44_ori = odm_get_mac_reg(p_dm_odm, 0x44, MASKDWORD); - reg44_tmp_p = reg44_ori; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_ori =0x%x\n", reg44_ori));*/ - - /*devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 8 : 4;*/ - - for (i = 0; i <= (codeword_length - 1); i++) { - beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); - - #if 1 - if (p_dm_odm->debug_components & ODM_COMP_ANT_DIV) { - - if (i == (codeword_length - 1)) { - dbg_print("%d ]\n", beam_ctrl_signal); - /**/ - } else if (i == 0) { - dbg_print("Start sending codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); - /**/ - } else if ((i % devide_num) == (devide_num-1)) { - dbg_print("%d | ", beam_ctrl_signal); - /**/ - } else { - dbg_print("%d ", beam_ctrl_signal); - /**/ - } - } - #endif - - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - #if (RTL8821A_SUPPORT == 1) - reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT10)); /*clean bit 10 & 11*/ - reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); - reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n));*/ - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); - #endif - } - #if (RTL8822B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - - if (pdm_sat_table->rfu_protocol_type == 2) { - - reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*clean bit 8*/ - reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*get new clk high/low, exclusive-or*/ +#endif + /* @--- */ - - reg44_tmp_p |= (beam_ctrl_signal << 8); - - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - ODM_delay_us(pdm_sat_table->rfu_protocol_delay_time); - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal));*/ - - } else { - reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT8)); /*clean bit 9 & 8*/ - reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); - reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n)); */ - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - ODM_delay_us(10); - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); - ODM_delay_us(10); - } - } - #endif - } -} + /* @2 [--General---] */ + dm->antdiv_period = 0; -void -phydm_update_rx_idle_beam_type2( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 i; + fat_tab->is_become_linked = false; + fat_tab->ant_div_on_off = 0xff; - pdm_sat_table->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(p_dm_odm, pdm_sat_table->rx_idle_beam_set_idx); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Beam ] BeamSet idx = ((%d))\n", pdm_sat_table->rx_idle_beam_set_idx)); +/* @3 - AP - */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); -#else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_bdc_init(dm); +#endif #endif - pdm_sat_table->pre_codeword = pdm_sat_table->update_beam_codeword; -} +/* @3 - WIN - */ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + dm_swat_table->ant_5g = MAIN_ANT; + dm_swat_table->ant_2g = MAIN_ANT; +#endif + /* @2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */ + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB); -void -phydm_hl_smart_ant_debug_type2( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 used = *_used; - u32 out_len = *_out_len; - u32 one = 0x1; - u32 codeword_length = pdm_sat_table->rfu_codeword_total_bit_num; - u32 beam_ctrl_signal, i; - u8 devide_num = 4; - char help[] = "-h"; - u32 dm_value[10] = {0}; - - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]); - PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]); - PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]); - PHYDM_SSCANF(input[4], DCMD_DECIMAL, &dm_value[3]); - PHYDM_SSCANF(input[5], DCMD_DECIMAL, &dm_value[4]); - - - if (strcmp(input[1], help) == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, " 1 {fix_en} {codeword(Hex)}\n")); - PHYDM_SNPRINTF((output + used, out_len - used, " 3 {Fix_training_num_en} {Per_beam_training_pkt_num} {Decision_holding_period}\n")); - PHYDM_SNPRINTF((output + used, out_len - used, " 5 {0:show, 1:2G, 2:5G} {beam_num} {idxA(Hex)} {idxB(Hex)}\n")); - PHYDM_SNPRINTF((output + used, out_len - used, " 7 {0:show, 1:2G, 2:5G} {total_beam_set_num}\n")); - PHYDM_SNPRINTF((output + used, out_len - used, " 8 {0:show, 1:set} {RFU delay time(us)}\n")); - - } else if (dm_value[0] == 1) { /*fix beam pattern*/ - - pdm_sat_table->fix_beam_pattern_en = dm_value[1]; - - if (pdm_sat_table->fix_beam_pattern_en == 1) { - - PHYDM_SSCANF(input[3], DCMD_HEX, &dm_value[2]); - pdm_sat_table->fix_beam_pattern_codeword = dm_value[2]; - - if (pdm_sat_table->fix_beam_pattern_codeword > (one << codeword_length)) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", - pdm_sat_table->fix_beam_pattern_codeword, codeword_length)); - - (pdm_sat_table->fix_beam_pattern_codeword) &= 0xffffff; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Auto modify to (0x%x)\n", pdm_sat_table->fix_beam_pattern_codeword)); - } + dm->ant_type = ODM_AUTO_ANT; - pdm_sat_table->update_beam_codeword = pdm_sat_table->fix_beam_pattern_codeword; - - /*---------------------------------------------------------*/ - PHYDM_SNPRINTF((output + used, out_len - used, "Fix Beam Pattern\n")); - - /*devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 8 : 4;*/ - - for (i = 0; i <= (codeword_length - 1); i++) { - beam_ctrl_signal = (boolean)((pdm_sat_table->update_beam_codeword & BIT(i)) >> i); - - if (i == (codeword_length - 1)) { - PHYDM_SNPRINTF((output + used, out_len - used, "%d]\n", beam_ctrl_signal)); - /**/ - } else if (i == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "Send Codeword[1:%d] to RFU -> [%d", pdm_sat_table->rfu_codeword_total_bit_num, beam_ctrl_signal)); - /**/ - } else if ((i % devide_num) == (devide_num-1)) { - PHYDM_SNPRINTF((output + used, out_len - used, "%d|", beam_ctrl_signal)); - /**/ - } else { - PHYDM_SNPRINTF((output + used, out_len - used, "%d", beam_ctrl_signal)); - /**/ - } - } - /*---------------------------------------------------------*/ + fat_tab->rx_idle_ant = 0xff; /*to make RX-idle-antenna will be updated absolutly*/ + odm_update_rx_idle_ant(dm, MAIN_ANT); + phydm_keep_rx_ack_ant_by_tx_ant_time(dm, 0); /* Timming issue: keep Rx ant after tx for ACK ( 5 x 3.2 mu = 16mu sec)*/ + /* @2 [---Set TX Antenna---] */ + if (fat_tab->p_force_tx_ant_by_desc == NULL) { + fat_tab->force_tx_ant_by_desc = 0; + fat_tab->p_force_tx_ant_by_desc = &fat_tab->force_tx_ant_by_desc; + } + PHYDM_DBG(dm, DBG_ANT_DIV, "p_force_tx_ant_by_desc = %d\n", + *fat_tab->p_force_tx_ant_by_desc); - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); - #else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ - #endif - } else if (pdm_sat_table->fix_beam_pattern_en == 0) - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Smart Antenna: Enable\n")); + if (*fat_tab->p_force_tx_ant_by_desc == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + else + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); - } else if (dm_value[0] == 2) { /*set latch time*/ + /* @2 [--88E---] */ + if (dm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */ + + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV && dm->ant_div_type != CG_TRX_HW_ANTDIV && dm->ant_div_type != CG_TRX_SMART_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 88E Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } - pdm_sat_table->latch_time = dm_value[1]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] latch_time =0x%x\n", pdm_sat_table->latch_time)); - } else if (dm_value[0] == 3) { + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_rx_hw_ant_div_init_88e(dm); + else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_88e(dm); +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_smart_hw_ant_div_init_88e(dm); +#endif +#endif + } - pdm_sat_table->fix_training_num_en = dm_value[1]; +/* @2 [--92E---] */ +#if (RTL8192E_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8192E) { + /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */ + + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV && dm->ant_div_type != CG_TRX_HW_ANTDIV && dm->ant_div_type != CG_TRX_SMART_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8192E Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } - if (pdm_sat_table->fix_training_num_en == 1) { - pdm_sat_table->per_beam_training_pkt_num = (u8)dm_value[2]; - pdm_sat_table->decision_holding_period = (u8)dm_value[3]; + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_rx_hw_ant_div_init_92e(dm); + else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_92e(dm); +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_smart_hw_ant_div_init_92e(dm); +#endif + } +#endif - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", - pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); + /* @2 [--92F---] */ +#if (RTL8192F_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8192F) { + /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */ - } else if (pdm_sat_table->fix_training_num_en == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] AUTO per_beam_training_pkt_num\n")); - /**/ + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) { + if (dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8192F Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; } - } else if (dm_value[0] == 4) { - #if 0 - if (dm_value[1] == 1) { - pdm_sat_table->ant_num = 1; - pdm_sat_table->first_train_ant = MAIN_ANT; + } + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_rx_hw_ant_div_init_92f(dm); + else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_92f(dm); + } +#endif - } else if (dm_value[1] == 2) { - pdm_sat_table->ant_num = 1; - pdm_sat_table->first_train_ant = AUX_ANT; +#if (RTL8197F_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8197F) { + dm->ant_div_type = CGCS_RX_HW_ANTDIV; - } else if (dm_value[1] == 3) { - pdm_sat_table->ant_num = 2; - pdm_sat_table->first_train_ant = MAIN_ANT; + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8197F Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; } - - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", - pdm_sat_table->ant_num, (pdm_sat_table->first_train_ant - 1))); - #endif - } else if (dm_value[0] == 5) { /*set beam set table*/ - - PHYDM_SSCANF(input[4], DCMD_HEX, &dm_value[3]); - PHYDM_SSCANF(input[5], DCMD_HEX, &dm_value[4]); - - if (dm_value[1] == 1) { /*2G*/ - if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { - pdm_sat_table->rfu_codeword_table_2g[dm_value[2] ][0] = (u8)dm_value[3]; - pdm_sat_table->rfu_codeword_table_2g[dm_value[2] ][1] = (u8)dm_value[4]; - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set 2G Table[%d] = [A:0x%x, B:0x%x]\n",dm_value[2], dm_value[3], dm_value[4])); - } - - } else if (dm_value[1] == 2) { /*5G*/ - if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { - pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3]; - pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4]; - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",dm_value[2], dm_value[3], dm_value[4])); - } - } else if (dm_value[1] == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] 2G Beam Table==============>\n")); - for (i = 0; i < pdm_sat_table->total_beam_set_num_2g; i++) { - PHYDM_SNPRINTF((output + used, out_len - used, "2G Table[%d] = [A:0x%x, B:0x%x]\n", - i, pdm_sat_table->rfu_codeword_table_2g[i][0], pdm_sat_table->rfu_codeword_table_2g[i][1])); - } - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] 5G Beam Table==============>\n")); - for (i = 0; i < pdm_sat_table->total_beam_set_num_5g; i++) { - PHYDM_SNPRINTF((output + used, out_len - used, "5G Table[%d] = [A:0x%x, B:0x%x]\n", - i, pdm_sat_table->rfu_codeword_table_5g[i][0], pdm_sat_table->rfu_codeword_table_5g[i][1])); - } + phydm_rx_hw_ant_div_init_97f(dm); + } +#endif +/* @2 [--8723B---] */ +#if (RTL8723B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8723B) { + dm->ant_div_type = S0S1_SW_ANTDIV; + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + + if (dm->ant_div_type != S0S1_SW_ANTDIV && dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8723B Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; } - } else if (dm_value[0] == 6) { - #if 0 - if (dm_value[1] == 0) { - if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { - pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3]; - pdm_sat_table->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4]; - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n",dm_value[2], dm_value[3], dm_value[4])); - } - } else { - for (i = 0; i < pdm_sat_table->total_beam_set_num_5g; i++) { - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Read 5G Table[%d] = [A:0x%x, B:0x%x]\n", - i, pdm_sat_table->rfu_codeword_table_5g[i][0], pdm_sat_table->rfu_codeword_table_5g[i][1])); - } + if (dm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_init_8723b(dm); + else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8723b(dm); + } +#endif +/*@2 [--8723D---]*/ +#if (RTL8723D_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8723D) { + if (fat_tab->p_default_s0_s1 == NULL) { + fat_tab->default_s0_s1 = 1; + fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1; } - #endif - } else if (dm_value[0] == 7) { - - if (dm_value[1] == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n", + *fat_tab->p_default_s0_s1); - pdm_sat_table->total_beam_set_num_2g = (u8)(dm_value[2]); - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] total_beam_set_num_2g = ((%d))\n", pdm_sat_table->total_beam_set_num_2g)); - - } else if (dm_value[1] == 2) { + if (*fat_tab->p_default_s0_s1 == true) + odm_update_rx_idle_ant(dm, MAIN_ANT); + else + odm_update_rx_idle_ant(dm, AUX_ANT); - pdm_sat_table->total_beam_set_num_5g = (u8)(dm_value[2]); - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] total_beam_set_num_5g = ((%d))\n", pdm_sat_table->total_beam_set_num_5g)); - } else if (dm_value[1] == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show total_beam_set_num{2g,5g} = {%d,%d}\n", - pdm_sat_table->total_beam_set_num_2g, pdm_sat_table->total_beam_set_num_5g)); + if (dm->ant_div_type == S0S1_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8723d(dm); + else if (dm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_init_8723d(dm); + else { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8723D Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; } + } +#endif +/* @2 [--8811A 8821A---] */ +#if (RTL8821A_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8821) { +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + dm->ant_div_type = HL_SW_SMART_ANT_TYPE1; - } else if (dm_value[0] == 8) { + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { + odm_trx_hw_ant_div_init_8821a(dm); + phydm_hl_smart_ant_type1_init_8821a(dm); + } else +#endif + { +#ifdef ODM_CONFIG_BT_COEXIST + dm->ant_div_type = S0S1_SW_ANTDIV; +#else + dm->ant_div_type = CG_TRX_HW_ANTDIV; +#endif - if (dm_value[1] == 1) { - pdm_sat_table->rfu_protocol_delay_time = (u16)(dm_value[2]); - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Set rfu_protocol_delay_time = ((%d))\n", pdm_sat_table->rfu_protocol_delay_time)); - } else if (dm_value[1] == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "[SmtAnt] Read rfu_protocol_delay_time = ((%d))\n", pdm_sat_table->rfu_protocol_delay_time)); + if (dm->ant_div_type != CG_TRX_HW_ANTDIV && dm->ant_div_type != S0S1_SW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8821A & 8811A Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; } + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8821a(dm); + else if (dm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_init_8821a(dm); + } } +#endif -} - -void -phydm_set_rfu_beam_pattern_type2( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - - if (p_dm_odm->ant_div_type != HL_SW_SMART_ANT_TYPE2) - return; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training beam_set index = (( 0x%x ))\n", pdm_sat_table->fast_training_beam_num)); - pdm_sat_table->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(p_dm_odm, pdm_sat_table->fast_training_beam_num); - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); - #else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ - #endif -} - -void -phydm_fast_ant_training_hl_smart_antenna_type2( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &(p_dm_odm->dm_fat_table); - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - u32 codeword = 0; - u8 i = 0, j=0; - u8 avg_rssi_tmp; - u8 avg_rssi_tmp_ma; - u8 max_beam_ant_rssi = 0; - u8 rssi_target_beam = 0, target_beam_max_rssi = 0; - u8 evm1ss_target_beam = 0, evm2ss_target_beam = 0; - u32 target_beam_max_evm1ss = 0, target_beam_max_evm2ss = 0; - u32 beam_tmp; - u8 per_beam_rssi_diff_tmp = 0, training_pkt_num_offset; - u32 avg_evm2ss[2] = {0}, avg_evm2ss_sum = 0; - u32 avg_evm1ss = 0; - u32 beam_path_evm_2ss_cnt_all = 0; /*sum of all 2SS-pattern cnt*/ - u32 beam_path_evm_1ss_cnt_all = 0; /*sum of all 1SS-pattern cnt*/ - u8 decision_type; - - if (!p_dm_odm->is_linked) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - - if (p_dm_fat_table->is_become_linked == true) { - - pdm_sat_table->decision_holding_period = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Link->no Link\n")); - p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; +/* @2 [--8821C---] */ +#if (RTL8821C_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8821C) { + dm->ant_div_type = S0S1_SW_ANTDIV; + if (dm->ant_div_type != S0S1_SW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8821C Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; } - return; + phydm_s0s1_sw_ant_div_init_8821c(dm); + odm_trx_hw_ant_div_init_8821c(dm); + } +#endif - } else { - if (p_dm_fat_table->is_become_linked == false) { +/* @2 [--8881A---] */ +#if (RTL8881A_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8881A) { + /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_trx_hw_ant_div_init_8881a(dm); + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8881A Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); + odm_trx_hw_ant_div_init_8881a(dm); + } +#endif - /*pdm_sat_table->fast_training_beam_num = 0;*/ - /*phydm_set_rfu_beam_pattern_type2(p_dm_odm);*/ +/* @2 [--8812---] */ +#if (RTL8812A_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8812) { + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; + if (dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8812A Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; } + odm_trx_hw_ant_div_init_8812a(dm); } +#endif +/*@[--8188F---]*/ +#if (RTL8188F_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8188F) { + dm->ant_div_type = S0S1_SW_ANTDIV; + odm_s0s1_sw_ant_div_init_8188f(dm); + } +#endif - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("HL Smart ant Training: state (( %d ))\n", p_dm_fat_table->fat_state));*/ - - /* [DECISION STATE] */ - /*=======================================================================================*/ - if (p_dm_fat_table->fat_state == FAT_DECISION_STATE) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 3. In Decision state]\n")); - - /*compute target beam in each antenna*/ - - for (j = 0; j < (pdm_sat_table->total_beam_set_num); j++) { - - /*[Decision1: RSSI]-------------------------------------------------------------------*/ - if (pdm_sat_table->statistic_pkt_cnt[j] == 0) { /*if new RSSI = 0 -> MA_RSSI-=2*/ - avg_rssi_tmp = pdm_sat_table->beam_set_avg_rssi_pre[j]; - avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; - avg_rssi_tmp_ma = avg_rssi_tmp; - } else { - avg_rssi_tmp = (u8)((pdm_sat_table->beam_set_rssi_avg_sum[j]) / (pdm_sat_table->statistic_pkt_cnt[j])); - avg_rssi_tmp_ma = (avg_rssi_tmp + pdm_sat_table->beam_set_avg_rssi_pre[j]) >> 1; - } - - pdm_sat_table->beam_set_avg_rssi_pre[j] = avg_rssi_tmp; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Beam_Set[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n", - j, pdm_sat_table->statistic_pkt_cnt[j], avg_rssi_tmp_ma, avg_rssi_tmp)); - - if (avg_rssi_tmp > target_beam_max_rssi) { - rssi_target_beam = j; - target_beam_max_rssi = avg_rssi_tmp; - } - - /*[Decision2: EVM 2ss]-------------------------------------------------------------------*/ - if (pdm_sat_table->beam_path_evm_2ss_cnt[j] != 0) { - avg_evm2ss[0] = pdm_sat_table->beam_path_evm_2ss_sum[j][0] / pdm_sat_table->beam_path_evm_2ss_cnt[j]; - avg_evm2ss[1] = pdm_sat_table->beam_path_evm_2ss_sum[j][1] / pdm_sat_table->beam_path_evm_2ss_cnt[j]; - avg_evm2ss_sum = avg_evm2ss[0] + avg_evm2ss[1]; - beam_path_evm_2ss_cnt_all += pdm_sat_table->beam_path_evm_2ss_cnt[j]; - } - - if (avg_evm2ss_sum > target_beam_max_evm2ss) { - evm2ss_target_beam = j; - target_beam_max_evm2ss = avg_evm2ss_sum; - } - - /*[Decision3: EVM 1ss]-------------------------------------------------------------------*/ - if (pdm_sat_table->beam_path_evm_1ss_cnt[j] != 0) { - avg_evm1ss = pdm_sat_table->beam_path_evm_1ss_sum[j] / pdm_sat_table->beam_path_evm_1ss_cnt[j]; - beam_path_evm_1ss_cnt_all += pdm_sat_table->beam_path_evm_1ss_cnt[j]; - } - - if (avg_evm1ss > target_beam_max_evm1ss) { - evm1ss_target_beam = j; - target_beam_max_evm1ss = avg_evm1ss; - } +/*@[--8822B---]*/ +#if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) { + dm->ant_div_type = CG_TRX_HW_ANTDIV; - /*reset counter value*/ - pdm_sat_table->beam_set_rssi_avg_sum[j] = 0; - pdm_sat_table->beam_path_rssi_sum[j][0] = 0; - pdm_sat_table->beam_path_rssi_sum[j][1] = 0; - pdm_sat_table->statistic_pkt_cnt[j] = 0; - - pdm_sat_table->beam_path_evm_2ss_sum[j][0] = 0; - pdm_sat_table->beam_path_evm_2ss_sum[j][1] = 0; - pdm_sat_table->beam_path_evm_2ss_cnt[j] = 0; - - pdm_sat_table->beam_path_evm_1ss_sum[j] = 0; - pdm_sat_table->beam_path_evm_1ss_cnt[j] = 0; + if (dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8822B Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; } + phydm_trx_hw_ant_div_init_22b(dm); +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + dm->ant_div_type = HL_SW_SMART_ANT_TYPE2; + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) + phydm_hl_smart_ant_type2_init_8822b(dm); +#endif + } +#endif - if (pdm_sat_table->beam_path_evm_1ss_cnt[j] != 0) { - avg_evm1ss = pdm_sat_table->beam_path_evm_1ss_sum[j] / pdm_sat_table->beam_path_evm_1ss_cnt[j]; - } - - /*[Joint Decision]-------------------------------------------------------------------*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---> [RSSI] Target Beam(( %d )) RSSI_max=((%d))\n", rssi_target_beam, target_beam_max_rssi)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---> [EVM 2SS] Target Beam(( %d )) EVM2SS_max=((%d))\n", evm2ss_target_beam, target_beam_max_evm2ss)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---> [EVM 1SS] Target Beam(( %d )) EVM1SS_max=((%d))\n", evm1ss_target_beam, target_beam_max_evm1ss)); - - if (target_beam_max_rssi <= 20) { - pdm_sat_table->rx_idle_beam_set_idx = rssi_target_beam; - decision_type = 1; - } else { - if (((beam_path_evm_2ss_cnt_all<<2) > (beam_path_evm_1ss_cnt_all)) && (beam_path_evm_2ss_cnt_all != 0)) { - pdm_sat_table->rx_idle_beam_set_idx = evm2ss_target_beam; - decision_type = 2; - } else if (beam_path_evm_1ss_cnt_all != 0) { - pdm_sat_table->rx_idle_beam_set_idx = evm1ss_target_beam; - decision_type = 3; - } else { - pdm_sat_table->rx_idle_beam_set_idx = rssi_target_beam; - decision_type = 4; - } - } + /*@ + PHYDM_DBG(dm, DBG_ANT_DIV, "*** support_ic_type=[%lu]\n",dm->support_ic_type); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv support_ability=[%lu]\n",(dm->support_ability & ODM_BB_ANT_DIV)>>6); + PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv type=[%d]\n",dm->ant_div_type); + */ +} - /*Calculate packet counter offset*/ - for (j = 0; j < (pdm_sat_table->total_beam_set_num); j++) { +void odm_ant_div( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; +#if (defined(CONFIG_HL_SMART_ANTENNA)) + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; +#endif - per_beam_rssi_diff_tmp = target_beam_max_rssi - pdm_sat_table->beam_set_avg_rssi_pre[j]; - pdm_sat_table->beam_set_train_rssi_diff[j] = per_beam_rssi_diff_tmp; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Beam_Set[%d]: RSSI_diff= ((%d))\n", j, per_beam_rssi_diff_tmp)); - } +#ifdef ODM_EVM_ENHANCE_ANTDIV - /*set beam in each antenna*/ - phydm_update_rx_idle_beam_type2(p_dm_odm); - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; + if (dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "tp_active_occur=((%d)), evm_method_enable=((%d))\n", + dm->tp_active_occur, fat_tab->evm_method_enable); + if (dm->tp_active_occur == 1 && fat_tab->evm_method_enable == 1) { + fat_tab->idx_ant_div_counter_5g = dm->antdiv_period; + fat_tab->idx_ant_div_counter_2g = dm->antdiv_period; + } } - /* [TRAINING STATE] */ - else if (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2. In Training state]\n")); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("curr_beam_idx = (( %d )), pre_beam_idx = (( %d ))\n", - pdm_sat_table->fast_training_beam_num, pdm_sat_table->pre_fast_training_beam_num)); +#endif - if (pdm_sat_table->fast_training_beam_num > pdm_sat_table->pre_fast_training_beam_num) - - pdm_sat_table->force_update_beam_en = 0; - - else { - - pdm_sat_table->force_update_beam_en = 1; - - pdm_sat_table->pkt_counter = 0; - beam_tmp = pdm_sat_table->fast_training_beam_num; - if (pdm_sat_table->fast_training_beam_num >= ((u32)pdm_sat_table->total_beam_set_num - 1)) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", pdm_sat_table->fast_training_beam_num)); - p_dm_fat_table->fat_state = FAT_DECISION_STATE; - phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); - - } else { - pdm_sat_table->fast_training_beam_num++; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_rfu_beam_pattern_type2(p_dm_odm); - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - - } - } - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Pre_Beam =(( %d ))\n", pdm_sat_table->pre_fast_training_beam_num)); - } - /* [Prepare state] */ - /*=======================================================================================*/ - else if (p_dm_fat_table->fat_state == FAT_PREPARE_STATE) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n\n[ 1. In Prepare state]\n")); - - if (p_dm_odm->pre_traffic_load == (p_dm_odm->traffic_load)) { - if (pdm_sat_table->decision_holding_period != 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Holding_period = (( %d )), return!!!\n", pdm_sat_table->decision_holding_period)); - pdm_sat_table->decision_holding_period--; - return; - } - } - - /* Set training packet number*/ - if (pdm_sat_table->fix_training_num_en == 0) { - - switch (p_dm_odm->traffic_load) { - - case TRAFFIC_HIGH: - pdm_sat_table->per_beam_training_pkt_num = 8; - pdm_sat_table->decision_holding_period = 2; - break; - case TRAFFIC_MID: - pdm_sat_table->per_beam_training_pkt_num = 6; - pdm_sat_table->decision_holding_period = 3; - break; - case TRAFFIC_LOW: - pdm_sat_table->per_beam_training_pkt_num = 3; /*ping 60000*/ - pdm_sat_table->decision_holding_period = 4; - break; - case TRAFFIC_ULTRA_LOW: - pdm_sat_table->per_beam_training_pkt_num = 1; - pdm_sat_table->decision_holding_period = 6; - break; - default: - break; - } - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TrafficLoad = (( %d )), Fix_beam = (( %d )), per_beam_training_pkt_num = (( %d )), decision_holding_period = ((%d))\n", - p_dm_odm->traffic_load, pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); - - /*Beam_set number*/ - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - pdm_sat_table->total_beam_set_num = pdm_sat_table->total_beam_set_num_5g; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("5G beam_set num = ((%d))\n", pdm_sat_table->total_beam_set_num)); - } else { - pdm_sat_table->total_beam_set_num = pdm_sat_table->total_beam_set_num_2g; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("2G beam_set num = ((%d))\n", pdm_sat_table->total_beam_set_num)); - } - - for (j = 0; j < (pdm_sat_table->total_beam_set_num); j++) { - - training_pkt_num_offset = pdm_sat_table->beam_set_train_rssi_diff[j]; - - if ((pdm_sat_table->per_beam_training_pkt_num) > training_pkt_num_offset) - pdm_sat_table->beam_set_train_cnt[j] = pdm_sat_table->per_beam_training_pkt_num - training_pkt_num_offset; - else - pdm_sat_table->beam_set_train_cnt[j] = 1; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Beam_Set[ %d ] training_pkt_offset = ((%d)), training_pkt_num = ((%d))\n", - j, pdm_sat_table->beam_set_train_rssi_diff[j], pdm_sat_table->beam_set_train_cnt[j])); - } - - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->update_beam_idx = 0; - pdm_sat_table->pkt_counter = 0; - - pdm_sat_table->fast_training_beam_num = 0; - phydm_set_rfu_beam_pattern_type2(p_dm_odm); - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - } - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -void -phydm_beam_switch_workitem_callback( - void *p_context -) -{ - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - -#if DEV_BUS_TYPE != RT_PCI_INTERFACE - pdm_sat_table->pkt_skip_statistic_en = 1; -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en)); - - phydm_update_beam_pattern_type2(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); - -#if DEV_BUS_TYPE != RT_PCI_INTERFACE - /*odm_stall_execution(pdm_sat_table->latch_time);*/ - pdm_sat_table->pkt_skip_statistic_en = 0; -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en, pdm_sat_table->latch_time)); -} - -void -phydm_beam_decision_workitem_callback( - void *p_context -) -{ - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam decision Workitem Callback\n")); - phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); -} -#endif - -#elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) - -u32 -phydm_construct_hl_beam_codeword( - void *p_dm_void, - u32 *beam_pattern_idx, - u32 ant_num -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 codeword = 0; - u32 data_tmp; - u32 i; - u32 break_counter = 0; - - if (ant_num < 8) { - for (i = 0; i < (pdm_sat_table->ant_num_total); i++) { - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] ));*/ - if ((i < (pdm_sat_table->first_train_ant - 1)) || (break_counter >= (pdm_sat_table->ant_num))) { - data_tmp = 0; - /**/ - } else { - - break_counter++; - - if (beam_pattern_idx[i] == 0) { - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[0]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[0]; - - } else if (beam_pattern_idx[i] == 1) { - - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[1]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[1]; - - } else if (beam_pattern_idx[i] == 2) { - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[2]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[2]; - - } else if (beam_pattern_idx[i] == 3) { - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - data_tmp = pdm_sat_table->rfu_codeword_table_5g[3]; - else - data_tmp = pdm_sat_table->rfu_codeword_table[3]; - } - } - - - codeword |= (data_tmp << (i * 4)); - - } - } - - return codeword; -} - -void -phydm_update_beam_pattern( - void *p_dm_void, - u32 codeword, - u32 codeword_length -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u8 i; - boolean beam_ctrl_signal; - u32 one = 0x1; - u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; - u8 devide_num = 4; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set Beam Pattern =0x%x\n", codeword)); - - reg44_ori = odm_get_mac_reg(p_dm_odm, 0x44, MASKDWORD); - reg44_tmp_p = reg44_ori; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_ori =0x%x\n", reg44_ori));*/ - - devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 6 : 4; - - for (i = 0; i <= (codeword_length - 1); i++) { - beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); - - if (p_dm_odm->debug_components & ODM_COMP_ANT_DIV) { - - if (i == (codeword_length - 1)) { - dbg_print("%d ]\n", beam_ctrl_signal); - /**/ - } else if (i == 0) { - dbg_print("Send codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); - /**/ - } else if ((i % devide_num) == (devide_num-1)) { - dbg_print("%d | ", beam_ctrl_signal); - /**/ - } else { - dbg_print("%d ", beam_ctrl_signal); - /**/ - } - } - - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - #if (RTL8821A_SUPPORT == 1) - reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT10)); /*clean bit 10 & 11*/ - reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); - reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n));*/ - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); - #endif - } - #if (RTL8822B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - - if (pdm_sat_table->rfu_protocol_type == 2) { - - reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*clean bit 8*/ - reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*get new clk high/low, exclusive-or*/ - - - reg44_tmp_p |= (beam_ctrl_signal << 8); - - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - ODM_delay_us(10); - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal));*/ - - } else { - reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT8)); /*clean bit 9 & 8*/ - reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); - reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n)); */ - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_p); - ODM_delay_us(10); - odm_set_mac_reg(p_dm_odm, 0x44, MASKDWORD, reg44_tmp_n); - ODM_delay_us(10); - } - } - #endif - } -} - -void -phydm_update_rx_idle_beam( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 i; - - pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(p_dm_odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set target beam_pattern codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); - - for (i = 0; i < (pdm_sat_table->ant_num); i++) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i, pdm_sat_table->rx_idle_beam[i])); - /**/ - } - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); -#else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ -#endif - - pdm_sat_table->pre_codeword = pdm_sat_table->update_beam_codeword; -} - -void -phydm_hl_smart_ant_debug( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 used = *_used; - u32 out_len = *_out_len; - u32 one = 0x1; - u32 codeword_length = pdm_sat_table->rfu_codeword_total_bit_num; - u32 beam_ctrl_signal, i; - u8 devide_num = 4; - - if (dm_value[0] == 1) { /*fix beam pattern*/ - - pdm_sat_table->fix_beam_pattern_en = dm_value[1]; - - if (pdm_sat_table->fix_beam_pattern_en == 1) { - - pdm_sat_table->fix_beam_pattern_codeword = dm_value[2]; - - if (pdm_sat_table->fix_beam_pattern_codeword > (one << codeword_length)) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", - pdm_sat_table->fix_beam_pattern_codeword, codeword_length)); - - (pdm_sat_table->fix_beam_pattern_codeword) &= 0xffffff; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Auto modify to (0x%x)\n", pdm_sat_table->fix_beam_pattern_codeword)); - } - - pdm_sat_table->update_beam_codeword = pdm_sat_table->fix_beam_pattern_codeword; - - /*---------------------------------------------------------*/ - PHYDM_SNPRINTF((output + used, out_len - used, "Fix Beam Pattern\n")); - - devide_num = (pdm_sat_table->rfu_protocol_type == 2) ? 6 : 4; - - for (i = 0; i <= (codeword_length - 1); i++) { - beam_ctrl_signal = (boolean)((pdm_sat_table->update_beam_codeword & BIT(i)) >> i); - - if (i == (codeword_length - 1)) { - PHYDM_SNPRINTF((output + used, out_len - used, "%d]\n", beam_ctrl_signal)); - /**/ - } else if (i == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "Send Codeword[1:24] to RFU -> [%d", beam_ctrl_signal)); - /**/ - } else if ((i % devide_num) == (devide_num-1)) { - PHYDM_SNPRINTF((output + used, out_len - used, "%d|", beam_ctrl_signal)); - /**/ - } else { - PHYDM_SNPRINTF((output + used, out_len - used, "%d", beam_ctrl_signal)); - /**/ - } - } - /*---------------------------------------------------------*/ - - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); -#else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ -#endif - } else if (pdm_sat_table->fix_beam_pattern_en == 0) - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Smart Antenna: Enable\n")); - - } else if (dm_value[0] == 2) { /*set latch time*/ - - pdm_sat_table->latch_time = dm_value[1]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] latch_time =0x%x\n", pdm_sat_table->latch_time)); - } else if (dm_value[0] == 3) { - - pdm_sat_table->fix_training_num_en = dm_value[1]; - - if (pdm_sat_table->fix_training_num_en == 1) { - pdm_sat_table->per_beam_training_pkt_num = (u8)dm_value[2]; - pdm_sat_table->decision_holding_period = (u8)dm_value[3]; - - PHYDM_SNPRINTF((output + used, out_len - used, "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", - pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); - - } else if (pdm_sat_table->fix_training_num_en == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] AUTO per_beam_training_pkt_num\n")); - /**/ - } - } else if (dm_value[0] == 4) { - - if (dm_value[1] == 1) { - pdm_sat_table->ant_num = 1; - pdm_sat_table->first_train_ant = MAIN_ANT; - - } else if (dm_value[1] == 2) { - pdm_sat_table->ant_num = 1; - pdm_sat_table->first_train_ant = AUX_ANT; - - } else if (dm_value[1] == 3) { - pdm_sat_table->ant_num = 2; - pdm_sat_table->first_train_ant = MAIN_ANT; - } - - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", - pdm_sat_table->ant_num, (pdm_sat_table->first_train_ant - 1))); - } else if (dm_value[0] == 5) { - - if (dm_value[1] <= 3) { - pdm_sat_table->rfu_codeword_table[dm_value[1]] = dm_value[2]; - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", - dm_value[1], dm_value[2])); - } else { - for (i = 0; i < 4; i++) { - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", - i, pdm_sat_table->rfu_codeword_table[i])); - } - } - } else if (dm_value[0] == 6) { - - if (dm_value[1] <= 3) { - pdm_sat_table->rfu_codeword_table_5g[dm_value[1]] = dm_value[2]; - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", - dm_value[1], dm_value[2])); - } else { - for (i = 0; i < 4; i++) { - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", - i, pdm_sat_table->rfu_codeword_table_5g[i])); - } - } - } else if (dm_value[0] == 7) { - - if (dm_value[1] <= 4) { - - pdm_sat_table->beam_patten_num_each_ant = dm_value[1]; - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Set Beam number = (( %d ))\n", - pdm_sat_table->beam_patten_num_each_ant)); - } else { - - PHYDM_SNPRINTF((output + used, out_len - used, "[ SmartAnt ] Show Beam number = (( %d ))\n", - pdm_sat_table->beam_patten_num_each_ant)); - } - } - -} - - -void -phydm_set_all_ant_same_beam_num( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { /*2ant for 8821A*/ - - pdm_sat_table->rx_idle_beam[0] = pdm_sat_table->fast_training_beam_num; - pdm_sat_table->rx_idle_beam[1] = pdm_sat_table->fast_training_beam_num; - } - - pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(p_dm_odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); - -#if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); -#else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_workitem); - /*odm_stall_execution(1);*/ -#endif -} - -void -odm_fast_ant_training_hl_smart_antenna_type1( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &(p_dm_odm->dm_fat_table); - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - u32 codeword = 0, i, j; - u32 target_ant; - u32 avg_rssi_tmp, avg_rssi_tmp_ma; - u32 target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0}; - u32 max_beam_ant_rssi = 0; - u32 target_ant_beam[SUPPORT_RF_PATH_NUM] = {0}; - u32 beam_tmp; - u8 next_ant; - u32 rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u32 rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u32 rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0}; - u8 per_beam_rssi_diff_tmp = 0, training_pkt_num_offset; - u32 break_counter = 0; - u32 used_ant; - - - if (!p_dm_odm->is_linked) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); - - if (p_dm_fat_table->is_become_linked == true) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Link->no Link\n")); - p_dm_fat_table->fat_state = FAT_BEFORE_LINK_STATE; - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); - - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; - } - return; - - } else { - if (p_dm_fat_table->is_become_linked == false) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); - - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", p_dm_fat_table->fat_state)); - - /*pdm_sat_table->fast_training_beam_num = 0;*/ - /*phydm_set_all_ant_same_beam_num(p_dm_odm);*/ - - p_dm_fat_table->is_become_linked = p_dm_odm->is_linked; - } - } - - if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == false) { - if (p_dm_odm->is_one_entry_only == true) - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - else - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); - } - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("HL Smart ant Training: state (( %d ))\n", p_dm_fat_table->fat_state));*/ - - /* [DECISION STATE] */ - /*=======================================================================================*/ - if (p_dm_fat_table->fat_state == FAT_DECISION_STATE) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 3. In Decision state]\n")); - phydm_fast_training_enable(p_dm_odm, FAT_OFF); - - break_counter = 0; - /*compute target beam in each antenna*/ - for (i = (pdm_sat_table->first_train_ant - 1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - - if (pdm_sat_table->pkt_rssi_cnt[i][j] == 0) { - avg_rssi_tmp = pdm_sat_table->pkt_rssi_pre[i][j]; - avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; - avg_rssi_tmp_ma = avg_rssi_tmp; - } else { - avg_rssi_tmp = (pdm_sat_table->pkt_rssi_sum[i][j]) / (pdm_sat_table->pkt_rssi_cnt[i][j]); - avg_rssi_tmp_ma = (avg_rssi_tmp + pdm_sat_table->pkt_rssi_pre[i][j]) >> 1; - } - - rssi_sorting_seq[j] = avg_rssi_tmp; - pdm_sat_table->pkt_rssi_pre[i][j] = avg_rssi_tmp; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n", - i, j, pdm_sat_table->pkt_rssi_cnt[i][j], avg_rssi_tmp_ma, avg_rssi_tmp)); - - if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) { - target_ant_beam[i] = j; - target_ant_beam_max_rssi[i] = avg_rssi_tmp; - } - - /*reset counter value*/ - pdm_sat_table->pkt_rssi_sum[i][j] = 0; - pdm_sat_table->pkt_rssi_cnt[i][j] = 0; - - } - pdm_sat_table->rx_idle_beam[i] = target_ant_beam[i]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---------> Target of ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n", - i, target_ant_beam[i], target_ant_beam_max_rssi[i])); - - /*sorting*/ - /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); - */ - - /*phydm_seq_sorting(p_dm_odm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/ - - /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3])); - */ - - if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) { - target_ant = i; - max_beam_ant_rssi = target_ant_beam_max_rssi[i]; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Target of ant = (( %d )) max_beam_ant_rssi = (( %d ))\n", - target_ant, max_beam_ant_rssi));*/ - } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; - } - -#ifdef CONFIG_FAT_PATCH - break_counter = 0; - for (i = (pdm_sat_table->first_train_ant - 1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - - per_beam_rssi_diff_tmp = (u8)(max_beam_ant_rssi - pdm_sat_table->pkt_rssi_pre[i][j]); - pdm_sat_table->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ant[%d], Beam[%d]: RSSI_diff= ((%d))\n", - i, j, per_beam_rssi_diff_tmp)); - } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; - } -#endif - - if (target_ant == 0) - target_ant = MAIN_ANT; - else if (target_ant == 1) - target_ant = AUX_ANT; - - if (pdm_sat_table->ant_num > 1) { - /* [ update RX ant ]*/ - odm_update_rx_idle_ant(p_dm_odm, (u8)target_ant); - - /* [ update TX ant ]*/ - odm_update_tx_ant(p_dm_odm, (u8)target_ant, (p_dm_fat_table->train_idx)); - } - - /*set beam in each antenna*/ - phydm_update_rx_idle_beam(p_dm_odm); - - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - p_dm_fat_table->fat_state = FAT_PREPARE_STATE; - return; - - } - /* [TRAINING STATE] */ - else if (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2. In Training state]\n")); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n", - pdm_sat_table->fast_training_beam_num, pdm_sat_table->pre_fast_training_beam_num)); - - if (pdm_sat_table->fast_training_beam_num > pdm_sat_table->pre_fast_training_beam_num) - - pdm_sat_table->force_update_beam_en = 0; - - else { - - pdm_sat_table->force_update_beam_en = 1; - - pdm_sat_table->pkt_counter = 0; - beam_tmp = pdm_sat_table->fast_training_beam_num; - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant - 1)) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", pdm_sat_table->fast_training_beam_num)); - p_dm_fat_table->fat_state = FAT_DECISION_STATE; - odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); - - } else { - pdm_sat_table->fast_training_beam_num++; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_all_ant_same_beam_num(p_dm_odm); - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - - } - } - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[prepare state] Update Pre_Beam =(( %d ))\n", pdm_sat_table->pre_fast_training_beam_num)); - } - /* [Prepare state] */ - /*=======================================================================================*/ - else if (p_dm_fat_table->fat_state == FAT_PREPARE_STATE) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n\n[ 1. In Prepare state]\n")); - - if (p_dm_odm->pre_traffic_load == (p_dm_odm->traffic_load)) { - if (pdm_sat_table->decision_holding_period != 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Holding_period = (( %d )), return!!!\n", pdm_sat_table->decision_holding_period)); - pdm_sat_table->decision_holding_period--; - return; - } - } - - - /* Set training packet number*/ - if (pdm_sat_table->fix_training_num_en == 0) { - - switch (p_dm_odm->traffic_load) { - - case TRAFFIC_HIGH: - pdm_sat_table->per_beam_training_pkt_num = 8; - pdm_sat_table->decision_holding_period = 2; - break; - case TRAFFIC_MID: - pdm_sat_table->per_beam_training_pkt_num = 6; - pdm_sat_table->decision_holding_period = 3; - break; - case TRAFFIC_LOW: - pdm_sat_table->per_beam_training_pkt_num = 3; /*ping 60000*/ - pdm_sat_table->decision_holding_period = 4; - break; - case TRAFFIC_ULTRA_LOW: - pdm_sat_table->per_beam_training_pkt_num = 1; - pdm_sat_table->decision_holding_period = 6; - break; - default: - break; - } - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n", - pdm_sat_table->fix_training_num_en, pdm_sat_table->per_beam_training_pkt_num, pdm_sat_table->decision_holding_period)); - - -#ifdef CONFIG_FAT_PATCH - break_counter = 0; - for (i = (pdm_sat_table->first_train_ant - 1); i < pdm_sat_table->ant_num_total; i++) { - for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { - - per_beam_rssi_diff_tmp = pdm_sat_table->beam_train_rssi_diff[i][j]; - training_pkt_num_offset = per_beam_rssi_diff_tmp; - - if ((pdm_sat_table->per_beam_training_pkt_num) > training_pkt_num_offset) - pdm_sat_table->beam_train_cnt[i][j] = pdm_sat_table->per_beam_training_pkt_num - training_pkt_num_offset; - else - pdm_sat_table->beam_train_cnt[i][j] = 1; - - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ant[%d]: Beam_num-(( %d )) training_pkt_num = ((%d))\n", - i, j, pdm_sat_table->beam_train_cnt[i][j])); - } - break_counter++; - if (break_counter >= (pdm_sat_table->ant_num)) - break; - } - - - phydm_fast_training_enable(p_dm_odm, FAT_OFF); - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->update_beam_idx = 0; - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 5G ant\n")); - /*used_ant = (pdm_sat_table->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/ - used_ant = pdm_sat_table->first_train_ant; - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set 2.4G ant\n")); - used_ant = pdm_sat_table->first_train_ant; - } - - odm_update_rx_idle_ant(p_dm_odm, (u8)used_ant); - -#else - /* Set training MAC addr. of target */ - odm_set_next_mac_addr_target(p_dm_odm); - phydm_fast_training_enable(p_dm_odm, FAT_ON); -#endif - - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - pdm_sat_table->pkt_counter = 0; - pdm_sat_table->fast_training_beam_num = 0; - phydm_set_all_ant_same_beam_num(p_dm_odm); - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - } - -} - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -void -phydm_beam_switch_workitem_callback( - void *p_context -) -{ - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - -#if DEV_BUS_TYPE != RT_PCI_INTERFACE - pdm_sat_table->pkt_skip_statistic_en = 1; -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en)); - - phydm_update_beam_pattern(p_dm_odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->rfu_codeword_total_bit_num); - -#if DEV_BUS_TYPE != RT_PCI_INTERFACE - /*odm_stall_execution(pdm_sat_table->latch_time);*/ - pdm_sat_table->pkt_skip_statistic_en = 0; -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en, pdm_sat_table->latch_time)); -} - -void -phydm_beam_decision_workitem_callback( - void *p_context -) -{ - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam decision Workitem Callback\n")); - odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); -} -#endif - -#endif /*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ - -void -odm_ant_div_init( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - - - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] Not Support Antenna Diversity Function\n")); - return; - } - /* --- */ -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_2G) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n")); - if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) - return; - } else if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_5G) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n")); - if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) - return; - } else if (p_dm_fat_table->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n")); - -#endif - /* --- */ - - /* 2 [--General---] */ - p_dm_odm->antdiv_period = 0; - - p_dm_fat_table->is_become_linked = false; - p_dm_fat_table->ant_div_on_off = 0xff; - - /* 3 - AP - */ -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - -#if (BEAMFORMING_SUPPORT == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - odm_bdc_init(p_dm_odm); -#endif -#endif - - /* 3 - WIN - */ -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_dm_swat_table->ant_5g = MAIN_ANT; - p_dm_swat_table->ant_2g = MAIN_ANT; -#endif - - /* 2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */ - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - - p_dm_odm->ant_type = ODM_AUTO_ANT; - - p_dm_fat_table->rx_idle_ant = 0xff; /*to make RX-idle-antenna will be updated absolutly*/ - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); - phydm_keep_rx_ack_ant_by_tx_ant_time(p_dm_odm, 0); /* Timming issue: keep Rx ant after tx for ACK ( 5 x 3.2 mu = 16mu sec)*/ - - /* 2 [---Set TX Antenna---] */ - if (p_dm_fat_table->p_force_tx_ant_by_desc == NULL) { - p_dm_fat_table->force_tx_ant_by_desc = 0; - p_dm_fat_table->p_force_tx_ant_by_desc = &(p_dm_fat_table->force_tx_ant_by_desc); - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("p_force_tx_ant_by_desc = %d\n", *p_dm_fat_table->p_force_tx_ant_by_desc)); - - if (*(p_dm_fat_table->p_force_tx_ant_by_desc) == true) - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); - else - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); - - - /* 2 [--88E---] */ - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { -#if (RTL8188E_SUPPORT == 1) - /* p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; */ - /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ - /* p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; */ - - if ((p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_SMART_ANTDIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 88E Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); - return; - } - - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) - odm_rx_hw_ant_div_init_88e(p_dm_odm); - else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_trx_hw_ant_div_init_88e(p_dm_odm); -#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) - odm_smart_hw_ant_div_init_88e(p_dm_odm); -#endif -#endif - } - - /* 2 [--92E---] */ -#if (RTL8192E_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - /* p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; */ - /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ - /* p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; */ - - if ((p_dm_odm->ant_div_type != CGCS_RX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) && (p_dm_odm->ant_div_type != CG_TRX_SMART_ANTDIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8192E Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); - return; - } - - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) - odm_rx_hw_ant_div_init_92e(p_dm_odm); - else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_trx_hw_ant_div_init_92e(p_dm_odm); -#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) - odm_smart_hw_ant_div_init_92e(p_dm_odm); -#endif - - } -#endif - - /* 2 [--8723B---] */ -#if (RTL8723B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ - - if (p_dm_odm->ant_div_type != S0S1_SW_ANTDIV && p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8723B Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + if (*dm->band_type == ODM_BAND_5G) { + if (fat_tab->idx_ant_div_counter_5g < dm->antdiv_period) { + fat_tab->idx_ant_div_counter_5g++; return; - } - - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) - odm_s0s1_sw_ant_div_init_8723b(p_dm_odm); - else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_trx_hw_ant_div_init_8723b(p_dm_odm); - } -#endif - /*2 [--8723D---]*/ -#if (RTL8723D_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - if (p_dm_fat_table->p_default_s0_s1 == NULL) { - p_dm_fat_table->default_s0_s1 = 1; - p_dm_fat_table->p_default_s0_s1 = &(p_dm_fat_table->default_s0_s1); - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("default_s0_s1 = %d\n", *p_dm_fat_table->p_default_s0_s1)); - - if (*(p_dm_fat_table->p_default_s0_s1) == true) - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); - else - odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); - - if (p_dm_odm->ant_div_type == S0S1_TRX_HW_ANTDIV) - odm_trx_hw_ant_div_init_8723d(p_dm_odm); - else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8723D Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); - return; - } - - } -#endif - /* 2 [--8811A 8821A---] */ -#if (RTL8821A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821) { - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - p_dm_odm->ant_div_type = HL_SW_SMART_ANT_TYPE1; - - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { - - odm_trx_hw_ant_div_init_8821a(p_dm_odm); - phydm_hl_smart_ant_type1_init_8821a(p_dm_odm); } else - #endif - { - /*p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV;*/ - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - - if (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV && p_dm_odm->ant_div_type != S0S1_SW_ANTDIV) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821A & 8811A Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); - return; - } - if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_trx_hw_ant_div_init_8821a(p_dm_odm); - else if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) - odm_s0s1_sw_ant_div_init_8821a(p_dm_odm); - } - } -#endif - - /* 2 [--8821C---] */ -#if (RTL8821C_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; - if (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821C Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); - return; - } - odm_trx_hw_ant_div_init_8821c(p_dm_odm); - } -#endif - - /* 2 [--8881A---] */ -#if (RTL8881A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8881A) { - /* p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; */ - /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ - - if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) { - - odm_trx_hw_ant_div_init_8881a(p_dm_odm); - /**/ - } else { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8881A Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); - return; - } - - odm_trx_hw_ant_div_init_8881a(p_dm_odm); - } -#endif - - /* 2 [--8812---] */ -#if (RTL8812A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - /* p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; */ - - if (p_dm_odm->ant_div_type != CG_TRX_HW_ANTDIV) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8812A Not Supprrt This AntDiv type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); - return; - } - odm_trx_hw_ant_div_init_8812a(p_dm_odm); - } -#endif - - /*[--8188F---]*/ -#if (RTL8188F_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - odm_s0s1_sw_ant_div_init_8188f(p_dm_odm); - } -#endif - - /*[--8822B---]*/ -#if (RTL8822B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - p_dm_odm->ant_div_type = HL_SW_SMART_ANT_TYPE2; - - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE2) - phydm_hl_smart_ant_type2_init_8822b(p_dm_odm); - #endif - } -#endif - - /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** support_ic_type=[%lu]\n",p_dm_odm->support_ic_type)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv support_ability=[%lu]\n",(p_dm_odm->support_ability & ODM_BB_ANT_DIV)>>6)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv type=[%d]\n",p_dm_odm->ant_div_type)); - */ -} - -void -odm_ant_div( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); -#endif - - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - if (p_dm_fat_table->idx_ant_div_counter_5g < p_dm_odm->antdiv_period) { - p_dm_fat_table->idx_ant_div_counter_5g++; - return; - } else - p_dm_fat_table->idx_ant_div_counter_5g = 0; - } else if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { - if (p_dm_fat_table->idx_ant_div_counter_2g < p_dm_odm->antdiv_period) { - p_dm_fat_table->idx_ant_div_counter_2g++; + fat_tab->idx_ant_div_counter_5g = 0; + } else if (*dm->band_type == ODM_BAND_2_4G) { + if (fat_tab->idx_ant_div_counter_2g < dm->antdiv_period) { + fat_tab->idx_ant_div_counter_2g++; return; } else - p_dm_fat_table->idx_ant_div_counter_2g = 0; - } - - /* ---------- */ - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] Not Support Antenna Diversity Function\n")); - return; + fat_tab->idx_ant_div_counter_2g = 0; } - /* ---------- */ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +/* @---------- */ - if (p_dm_fat_table->enable_ctrl_frame_antdiv) { +/* @---------- */ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE) - if ((p_dm_odm->data_frame_num <= 10) && (p_dm_odm->is_linked)) - p_dm_fat_table->use_ctrl_frame_antdiv = 1; + if (fat_tab->enable_ctrl_frame_antdiv) { + if (dm->data_frame_num <= 10 && dm->is_linked) + fat_tab->use_ctrl_frame_antdiv = 1; else - p_dm_fat_table->use_ctrl_frame_antdiv = 0; + fat_tab->use_ctrl_frame_antdiv = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n", p_dm_fat_table->use_ctrl_frame_antdiv, p_dm_odm->data_frame_num)); - p_dm_odm->data_frame_num = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, + "use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n", + fat_tab->use_ctrl_frame_antdiv, dm->data_frame_num); + dm->data_frame_num = 0; } - if (p_adapter->MgntInfo.AntennaTest) - return; - { #if (BEAMFORMING_SUPPORT == 1) - enum beamforming_cap beamform_cap = (p_dm_odm->beamforming_info.beamform_cap); - - if (beamform_cap & BEAMFORMEE_CAP) { /* BFmee On && Div On->Div Off */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ AntDiv : OFF ] BFmee ==1\n")); - if (p_dm_fat_table->fix_ant_bfee == 0) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - p_dm_fat_table->fix_ant_bfee = 1; - } - return; - } else { /* BFmee Off && Div Off->Div On */ - if ((p_dm_fat_table->fix_ant_bfee == 1) && p_dm_odm->is_linked) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ AntDiv : ON ] BFmee ==0\n")); - if ((p_dm_odm->ant_div_type != S0S1_SW_ANTDIV)) - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - p_dm_fat_table->fix_ant_bfee = 0; + enum beamforming_cap beamform_cap = phydm_get_beamform_cap(dm); + PHYDM_DBG(dm, DBG_ANT_DIV, "is_bt_continuous_turn = ((%d))\n", + dm->is_bt_continuous_turn); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ AntDiv Beam Cap ] cap= ((%d))\n", beamform_cap); + if (!dm->is_bt_continuous_turn) { + if ((beamform_cap & BEAMFORMEE_CAP) && (!(*fat_tab->is_no_csi_feedback))) { /* @BFmee On && Div On->Div Off */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ AntDiv : OFF ] BFmee ==1; cap= ((%d))\n", + beamform_cap); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ AntDiv BF] is_no_csi_feedback= ((%d))\n", + *(fat_tab->is_no_csi_feedback)); + if (fat_tab->fix_ant_bfee == 0) { + odm_ant_div_on_off(dm, ANTDIV_OFF, + ANT_PATH_A); + fat_tab->fix_ant_bfee = 1; + } + return; + } else { /* @BFmee Off && Div Off->Div On */ + if (fat_tab->fix_ant_bfee == 1 && dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ AntDiv : ON ] BFmee ==0; cap=((%d))\n", beamform_cap); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ AntDiv BF] is_no_csi_feedback= ((%d))\n", *(fat_tab->is_no_csi_feedback)); + if (dm->ant_div_type != S0S1_SW_ANTDIV) + odm_ant_div_on_off(dm, ANTDIV_ON + , ANT_PATH_A) + ; + fat_tab->fix_ant_bfee = 0; + } } + } else { + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB); } #endif } #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - /* ----------just for fool proof */ + /* @----------just for fool proof */ - if (p_dm_odm->antdiv_rssi) - p_dm_odm->debug_components |= ODM_COMP_ANT_DIV; + if (dm->antdiv_rssi) + dm->debug_components |= DBG_ANT_DIV; else - p_dm_odm->debug_components &= ~ODM_COMP_ANT_DIV; + dm->debug_components &= ~DBG_ANT_DIV; - if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_2G) { - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n")); */ - if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) + if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) { +#if 0 + /* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 2G AntDiv Running ]\n"); */ +#endif + if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) return; - } else if (p_dm_fat_table->ant_div_2g_5g == ODM_ANTDIV_5G) { - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n")); */ - if (!(p_dm_odm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) + } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) { +#if 0 + /* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 5G AntDiv Running ]\n"); */ +#endif + if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) return; } - /* else if(p_dm_fat_table->ant_div_2g_5g == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) */ - /* { */ - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n")); */ - /* } */ +#if 0 +/* @else if(fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) */ +/* @{ */ +/* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 2G & 5G AntDiv Running ]\n"); */ +/* @} */ +#endif #endif - /* ---------- */ + /* @---------- */ - if (p_dm_odm->antdiv_select == 1) - p_dm_odm->ant_type = ODM_FIX_MAIN_ANT; - else if (p_dm_odm->antdiv_select == 2) - p_dm_odm->ant_type = ODM_FIX_AUX_ANT; - else /* if (p_dm_odm->antdiv_select==0) */ - p_dm_odm->ant_type = ODM_AUTO_ANT; + if (dm->antdiv_select == 1) + dm->ant_type = ODM_FIX_MAIN_ANT; + else if (dm->antdiv_select == 2) + dm->ant_type = ODM_FIX_AUX_ANT; + else { /* @if (dm->antdiv_select==0) */ + dm->ant_type = ODM_AUTO_ANT; - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("ant_type= (( %d )) , pre_ant_type= (( %d ))\n",p_dm_odm->ant_type,p_dm_odm->pre_ant_type)); */ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /*Stop Antenna diversity for CMW500 testing case*/ + if (dm->consecutive_idlel_time >= 10) { + dm->ant_type = ODM_FIX_MAIN_ANT; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[AntDiv: OFF] No TP case, consecutive_idlel_time=((%d))\n", + dm->consecutive_idlel_time); + } +#endif + } - if (p_dm_odm->ant_type != ODM_AUTO_ANT) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix Antenna at (( %s ))\n", (p_dm_odm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX")); +#if 0 + /* PHYDM_DBG(dm, DBG_ANT_DIV,"ant_type= (( %d )) , pre_ant_type= (( %d ))\n",dm->ant_type,dm->pre_ant_type); */ +#endif - if (p_dm_odm->ant_type != p_dm_odm->pre_ant_type) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_REG); + if (dm->ant_type != ODM_AUTO_ANT) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Fix Antenna at (( %s ))\n", + (dm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX"); - if (p_dm_odm->ant_type == ODM_FIX_MAIN_ANT) - odm_update_rx_idle_ant(p_dm_odm, MAIN_ANT); - else if (p_dm_odm->ant_type == ODM_FIX_AUX_ANT) - odm_update_rx_idle_ant(p_dm_odm, AUX_ANT); + if (dm->ant_type != dm->pre_ant_type) { + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + + if (dm->ant_type == ODM_FIX_MAIN_ANT) + odm_update_rx_idle_ant(dm, MAIN_ANT); + else if (dm->ant_type == ODM_FIX_AUX_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); } - p_dm_odm->pre_ant_type = p_dm_odm->ant_type; + dm->pre_ant_type = dm->ant_type; return; } else { - if (p_dm_odm->ant_type != p_dm_odm->pre_ant_type) { - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); - odm_tx_by_tx_desc_or_reg(p_dm_odm, TX_BY_DESC); + if (dm->ant_type != dm->pre_ant_type) { + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + } + dm->pre_ant_type = dm->ant_type; + } +#if (defined(CONFIG_2T4R_ANTENNA)) + if (dm->ant_type2 != ODM_AUTO_ANT) { + PHYDM_DBG(dm, DBG_ANT_DIV, "PathB Fix Ant at (( %s ))\n", + (dm->ant_type2 == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX"); + + if (dm->ant_type2 != dm->pre_ant_type2) { + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + + if (dm->ant_type2 == ODM_FIX_MAIN_ANT) + phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT); + else if (dm->ant_type2 == ODM_FIX_AUX_ANT) + phydm_update_rx_idle_ant_pathb(dm, AUX_ANT); } - p_dm_odm->pre_ant_type = p_dm_odm->ant_type; + dm->pre_ant_type2 = dm->ant_type2; + return; } + if (dm->ant_type2 != dm->pre_ant_type2) { + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + } + dm->pre_ant_type2 = dm->ant_type2; +#endif - /* 3 ----------------------------------------------------------------------------------------------------------- */ - /* 2 [--88E---] */ - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + /* @3 ----------------------------------------------------------------------------------------------------------- */ + /* @2 [--88E---] */ + if (dm->support_ic_type == ODM_RTL8188E) { #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV || p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) - odm_hw_ant_div(p_dm_odm); + if (dm->ant_div_type == CG_TRX_HW_ANTDIV || dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_hw_ant_div(dm); #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) - odm_fast_ant_training(p_dm_odm); + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_fast_ant_training(dm); #endif #endif - } - /* 2 [--92E---] */ +/* @2 [--92E---] */ #if (RTL8192E_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV || p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_hw_ant_div(p_dm_odm); + else if (dm->support_ic_type == ODM_RTL8192E) { + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV || dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - else if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) - odm_fast_ant_training(p_dm_odm); + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_fast_ant_training(dm); #endif - + } +#endif +/* @2 [--97F---] */ +#if (RTL8197F_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8197F) { + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_hw_ant_div(dm); } #endif #if (RTL8723B_SUPPORT == 1) - /* 2 [--8723B---] */ - else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - if (phydm_is_bt_enable_8723b(p_dm_odm)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BT is enable!!!]\n")); - if (p_dm_fat_table->is_become_linked == true) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); - if (p_dm_odm->support_ic_type == ODM_RTL8723B) - odm_set_bb_reg(p_dm_odm, 0x948, BIT(9) | BIT(8) | BIT(7) | BIT(6), 0x0); - - p_dm_fat_table->is_become_linked = false; + /* @2 [--8723B---] */ + else if (dm->support_ic_type == ODM_RTL8723B) { + if (phydm_is_bt_enable_8723b(dm)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[BT is enable!!!]\n"); + if (fat_tab->is_become_linked == true) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Set REG 948[9:6]=0x0\n"); + if (dm->support_ic_type == ODM_RTL8723B) + odm_set_bb_reg(dm, R_0x948, BIT(9) | BIT(8) | BIT(7) | BIT(6), 0x0); + + fat_tab->is_become_linked = false; } } else { - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { - + if (dm->ant_div_type == S0S1_SW_ANTDIV) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_PEEK); + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); #endif - } else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_hw_ant_div(p_dm_odm); + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); } } #endif - /*8723D*/ +/*@8723D*/ #if (RTL8723D_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - - odm_hw_ant_div(p_dm_odm); - /**/ + else if (dm->support_ic_type == ODM_RTL8723D) { + if (dm->ant_div_type == S0S1_SW_ANTDIV) { +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + if (dm->antdiv_counter == + CONFIG_ANTENNA_DIVERSITY_PERIOD) { + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); + dm->antdiv_counter--; + } else { + dm->antdiv_counter--; + } + if (dm->antdiv_counter == 0) + dm->antdiv_counter = CONFIG_ANTENNA_DIVERSITY_PERIOD; +#endif + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_hw_ant_div(dm); + } } #endif - /* 2 [--8821A---] */ +/* @2 [--8821A---] */ #if (RTL8821A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821) { - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { - - if (pdm_sat_table->fix_beam_pattern_en != 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword)); + else if (dm->support_ic_type == ODM_RTL8821) { +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { + if (sat_tab->fix_beam_pattern_en != 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", + sat_tab->fix_beam_pattern_codeword); /*return;*/ } else { - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] ant_div_type = HL_SW_SMART_ANT_TYPE1\n"));*/ - odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] ant_div_type = HL_SW_SMART_ANT_TYPE1\n");*/ +#endif + odm_fast_ant_training_hl_smart_antenna_type1(dm); } } else - #endif +#endif { - - if (!p_dm_odm->is_bt_enabled) { /*BT disabled*/ - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n")); - /*odm_set_bb_reg(p_dm_odm, 0x8D4, BIT24, 1); */ - if (p_dm_fat_table->is_become_linked == true) - odm_ant_div_on_off(p_dm_odm, ANTDIV_ON); +#ifdef ODM_CONFIG_BT_COEXIST + if (!dm->bt_info_table.is_bt_enabled) { /*@BT disabled*/ + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, " [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n"); +#if 0 + /*odm_set_bb_reg(dm, R_0x8d4, BIT24, 1); */ +#endif + if (fat_tab->is_become_linked == true) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); } - } else { /*BT enabled*/ + } else { /*@BT enabled*/ - if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) { - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n")); - /*odm_set_bb_reg(p_dm_odm, 0x8D4, BIT24, 0);*/ - odm_ant_div_on_off(p_dm_odm, ANTDIV_OFF); + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, " [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n"); +#if 0 + /*odm_set_bb_reg(dm, R_0x8d4, BIT24, 0);*/ +#endif + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); } } +#endif - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { - + if (dm->ant_div_type == S0S1_SW_ANTDIV) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_PEEK); + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); #endif - } else if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV) - odm_hw_ant_div(p_dm_odm); + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); } } #endif - /* 2 [--8821C---] */ +/* @2 [--8821C---] */ #if (RTL8821C_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821C) - odm_hw_ant_div(p_dm_odm); + else if (dm->support_ic_type == ODM_RTL8821C) { + if (!dm->is_bt_continuous_turn) { + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "is_bt_continuous_turn = ((%d)) ==> SW AntDiv\n", + dm->is_bt_continuous_turn); + + } else { + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "is_bt_continuous_turn = ((%d)) ==> HW AntDiv\n", + dm->is_bt_continuous_turn); + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + } + + if (fat_tab->force_antdiv_type) + dm->ant_div_type = fat_tab->antdiv_type_dbg; + + if (dm->ant_div_type == S0S1_SW_ANTDIV) { +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); +#endif + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + odm_hw_ant_div(dm); + } + } #endif - /* 2 [--8881A---] */ +/* @2 [--8881A---] */ #if (RTL8881A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8881A) - odm_hw_ant_div(p_dm_odm); + else if (dm->support_ic_type == ODM_RTL8881A) + odm_hw_ant_div(dm); #endif - /* 2 [--8812A---] */ +/* @2 [--8812A---] */ #if (RTL8812A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8812) - odm_hw_ant_div(p_dm_odm); + else if (dm->support_ic_type == ODM_RTL8812) + odm_hw_ant_div(dm); #endif #if (RTL8188F_SUPPORT == 1) - /* [--8188F---]*/ - else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - + /* @[--8188F---]*/ + else if (dm->support_ic_type == ODM_RTL8188F) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_PEEK); + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); #endif } #endif - /* [--8822B---]*/ +/* @[--8822B---]*/ #if (RTL8822B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE2) { - - if (pdm_sat_table->fix_beam_pattern_en != 0) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword)); + else if (dm->support_ic_type == ODM_RTL8822B) { + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) { + if (sat_tab->fix_beam_pattern_en != 0) + PHYDM_DBG(dm, DBG_ANT_DIV, + " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", + sat_tab->fix_beam_pattern_codeword); else - phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); + phydm_fast_ant_training_hl_smart_antenna_type2(dm); } - #endif +#endif } #endif - - } +void odm_antsel_statistics( + void *dm_void, + void *phy_info_void, + u8 antsel_tr_mux, + u32 mac_id, + u32 utility, + u8 method, + u8 is_cck_rate -void -odm_antsel_statistics( - void *p_dm_void, - u8 antsel_tr_mux, - u32 mac_id, - u32 utility, - u8 method, - u8 is_cck_rate - -) + ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; if (method == RSSI_METHOD) { - if (is_cck_rate) { if (antsel_tr_mux == ANT1_2G) { - if (p_dm_fat_table->main_ant_sum_cck[mac_id] > 65435) /*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/ + if (fat_tab->main_ant_sum_cck[mac_id] > 65435) /*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/ return; - p_dm_fat_table->main_ant_sum_cck[mac_id] += (u16)utility; - p_dm_fat_table->main_ant_cnt_cck[mac_id]++; + fat_tab->main_ant_sum_cck[mac_id] += (u16)utility; + fat_tab->main_ant_cnt_cck[mac_id]++; } else { - if (p_dm_fat_table->aux_ant_sum_cck[mac_id] > 65435) + if (fat_tab->aux_ant_sum_cck[mac_id] > 65435) return; - p_dm_fat_table->aux_ant_sum_cck[mac_id] += (u16)utility; - p_dm_fat_table->aux_ant_cnt_cck[mac_id]++; + fat_tab->aux_ant_sum_cck[mac_id] += (u16)utility; + fat_tab->aux_ant_cnt_cck[mac_id]++; } } else { /*ofdm rate*/ if (antsel_tr_mux == ANT1_2G) { - if (p_dm_fat_table->main_ant_sum[mac_id] > 65435) + if (fat_tab->main_ant_sum[mac_id] > 65435) return; - p_dm_fat_table->main_ant_sum[mac_id] += (u16)utility; - p_dm_fat_table->main_ant_cnt[mac_id]++; + fat_tab->main_ant_sum[mac_id] += (u16)utility; + fat_tab->main_ant_cnt[mac_id]++; } else { - if (p_dm_fat_table->aux_ant_sum[mac_id] > 65435) + if (fat_tab->aux_ant_sum[mac_id] > 65435) return; - p_dm_fat_table->aux_ant_sum[mac_id] += (u16)utility; - p_dm_fat_table->aux_ant_cnt[mac_id]++; + fat_tab->aux_ant_sum[mac_id] += (u16)utility; + fat_tab->aux_ant_cnt[mac_id]++; } } } #ifdef ODM_EVM_ENHANCE_ANTDIV else if (method == EVM_METHOD) { - if (antsel_tr_mux == ANT1_2G) { - p_dm_fat_table->main_ant_evm_sum[mac_id] += (utility << 5); - p_dm_fat_table->main_ant_evm_cnt[mac_id]++; - } else { - p_dm_fat_table->aux_ant_evm_sum[mac_id] += (utility << 5); - p_dm_fat_table->aux_ant_evm_cnt[mac_id]++; - } - } else if (method == CRC32_METHOD) { - if (utility == 0) - p_dm_fat_table->crc32_fail_cnt++; - else - p_dm_fat_table->crc32_ok_cnt += utility; - } -#endif -} - -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 -void -phydm_process_rssi_for_hb_smtant_type2( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void, - u8 rssi_avg -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; - struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u8 train_pkt_number; - u32 beam_tmp; - u8 is_cck_rate; - u8 rate_ss = 1; /*spatial stream*/ - u8 rx_power_ant0 = p_phy_info->rx_mimo_signal_strength[0]; - u8 rx_power_ant1 = p_phy_info->rx_mimo_signal_strength[1]; - u8 rx_evm_ant0 = p_phy_info->rx_mimo_evm_dbm[0]; - u8 rx_evm_ant1 = p_phy_info->rx_mimo_evm_dbm[1]; - - is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? TRUE : FALSE; - - if ((p_pktinfo->data_rate >= ODM_RATEMCS8 && p_pktinfo->data_rate <= ODM_RATEMCS15) || - (p_pktinfo->data_rate >= ODM_RATEVHTSS2MCS0 && p_pktinfo->data_rate <= ODM_RATEVHTSS2MCS9)) { - rate_ss = 2; - } - - /*[Beacon]*/ - if (p_pktinfo->is_packet_beacon) { - - pdm_sat_table->beacon_counter++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MatchBSSID_beacon_counter = ((%d))\n", pdm_sat_table->beacon_counter)); - - if (pdm_sat_table->beacon_counter >= pdm_sat_table->pre_beacon_counter + 2) { - - pdm_sat_table->update_beam_idx++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", - pdm_sat_table->pre_beacon_counter, pdm_sat_table->pkt_counter, pdm_sat_table->update_beam_idx)); - - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->pkt_counter = 0; - } - } - /*[data]*/ - else if (p_pktinfo->is_packet_to_self) { - - if (pdm_sat_table->pkt_skip_statistic_en == 0) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ID[%d] pkt_cnt=((%d)): Beam_set = ((%d)), RSSI{A,B,avg} = {%d, %d, %d}\n", - p_pktinfo->station_id, pdm_sat_table->pkt_counter, pdm_sat_table->fast_training_beam_num, rx_power_ant0, rx_power_ant1, rssi_avg)); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RX Rate = ((0x%x)), rate_ss = ((%d)), EVM{A,B} = {%d, %d}\n", p_pktinfo->data_rate, rate_ss, rx_evm_ant0, rx_evm_ant1)); - - - if (pdm_sat_table->pkt_counter >= 1) /*packet skip count*/ - { - pdm_sat_table->beam_set_rssi_avg_sum[pdm_sat_table->fast_training_beam_num] += rssi_avg; - pdm_sat_table->statistic_pkt_cnt[pdm_sat_table->fast_training_beam_num]++; - - pdm_sat_table->beam_path_rssi_sum[pdm_sat_table->fast_training_beam_num][0] += rx_power_ant0; - pdm_sat_table->beam_path_rssi_sum[pdm_sat_table->fast_training_beam_num][1] += rx_power_ant1; - - if (rate_ss == 2) { - pdm_sat_table->beam_path_evm_2ss_sum[pdm_sat_table->fast_training_beam_num][0] += rx_evm_ant0; - pdm_sat_table->beam_path_evm_2ss_sum[pdm_sat_table->fast_training_beam_num][1] += rx_evm_ant1; - pdm_sat_table->beam_path_evm_2ss_cnt[pdm_sat_table->fast_training_beam_num]++; - } else { - pdm_sat_table->beam_path_evm_1ss_sum[pdm_sat_table->fast_training_beam_num] += rx_evm_ant0; - pdm_sat_table->beam_path_evm_1ss_cnt[pdm_sat_table->fast_training_beam_num]++; - } + if (dm->rate_ss == 1) { + if (antsel_tr_mux == ANT1_2G) { + fat_tab->main_ant_evm_sum[mac_id] += ((phy_info->rx_mimo_evm_dbm[0]) << 5); + fat_tab->main_ant_evm_cnt[mac_id]++; + } else { + fat_tab->aux_ant_evm_sum[mac_id] += ((phy_info->rx_mimo_evm_dbm[0]) << 5); + fat_tab->aux_ant_evm_cnt[mac_id]++; } - - pdm_sat_table->pkt_counter++; - train_pkt_number = pdm_sat_table->beam_set_train_cnt[pdm_sat_table->fast_training_beam_num]; + } else { /*@>= 2SS*/ - if (pdm_sat_table->pkt_counter >= train_pkt_number) { + if (antsel_tr_mux == ANT1_2G) { + fat_tab->main_ant_evm_2ss_sum[mac_id][0] += (phy_info->rx_mimo_evm_dbm[0] << 5); + fat_tab->main_ant_evm_2ss_sum[mac_id][1] += (phy_info->rx_mimo_evm_dbm[1] << 5); + fat_tab->main_ant_evm_2ss_cnt[mac_id]++; - pdm_sat_table->update_beam_idx++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), Update_new_beam = ((%d))\n", - pdm_sat_table->pre_beacon_counter, pdm_sat_table->update_beam_idx)); - - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->pkt_counter = 0; + } else { + fat_tab->aux_ant_evm_2ss_sum[mac_id][0] += (phy_info->rx_mimo_evm_dbm[0] << 5); + fat_tab->aux_ant_evm_2ss_sum[mac_id][1] += (phy_info->rx_mimo_evm_dbm[1] << 5); + fat_tab->aux_ant_evm_2ss_cnt[mac_id]++; } } - } - - if (pdm_sat_table->update_beam_idx > 0) { - - pdm_sat_table->update_beam_idx = 0; - - if (pdm_sat_table->fast_training_beam_num >= ((u32)pdm_sat_table->total_beam_set_num - 1)) { - - p_dm_fat_table->fat_state = FAT_DECISION_STATE; - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - phydm_fast_ant_training_hl_smart_antenna_type2(p_dm_odm); /*go to make decision*/ - #else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_decision_workitem); - #endif - + } else if (method == CRC32_METHOD) { + if (antsel_tr_mux == ANT1_2G) { + fat_tab->main_crc32_ok_cnt += utility; + fat_tab->main_crc32_fail_cnt++; } else { - beam_tmp = pdm_sat_table->fast_training_beam_num; - pdm_sat_table->fast_training_beam_num++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_rfu_beam_pattern_type2(p_dm_odm); - pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; + fat_tab->aux_crc32_ok_cnt += utility; + fat_tab->aux_crc32_fail_cnt++; + } - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; + } else if (method == TP_METHOD) { + if ((utility <= ODM_RATEMCS15 && utility >= ODM_RATEMCS0) && + fat_tab->fat_state_cnt <= dm->antdiv_tp_period) { + if (antsel_tr_mux == ANT1_2G) { + fat_tab->antdiv_tp_main += (phy_rate_table[utility]) << 5; + fat_tab->antdiv_tp_main_cnt++; + } else { + fat_tab->antdiv_tp_aux += (phy_rate_table[utility]) << 5; + fat_tab->antdiv_tp_aux_cnt++; + } } } - -} #endif +} -void -odm_process_rssi_for_ant_div( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void -) +void odm_process_rssi_for_ant_div( + void *dm_void, + void *phy_info_void, + void *pkt_info_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; - struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) - struct _SMART_ANTENNA_TRAINNING_ *pdm_sat_table = &(p_dm_odm->dm_sat_table); - u32 beam_tmp; - u8 next_ant; - u8 train_pkt_number; -#endif - u8 is_cck_rate = FALSE; - u8 rx_power_ant0 = p_phy_info->rx_mimo_signal_strength[0]; - u8 rx_power_ant1 = p_phy_info->rx_mimo_signal_strength[1]; - u8 rx_evm_ant0 = p_phy_info->rx_mimo_signal_quality[0]; - u8 rx_evm_ant1 = p_phy_info->rx_mimo_signal_quality[1]; - u8 rssi_avg; - - is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? TRUE : FALSE; - - if ((p_dm_odm->support_ic_type & ODM_IC_2SS) && (!is_cck_rate)) { - + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; +#if (defined(CONFIG_HL_SMART_ANTENNA)) + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 beam_tmp; + u8 next_ant; + u8 train_pkt_number; +#endif + u8 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0]; + u8 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1]; + u8 rx_evm_ant0 = phy_info->rx_mimo_signal_quality[0]; + u8 rx_evm_ant1 = phy_info->rx_mimo_signal_quality[1]; + u8 rssi_avg; + + if ((dm->support_ic_type & ODM_IC_2SS) && !pktinfo->is_cck_rate) { if (rx_power_ant1 < 100) - rssi_avg = (u8)odm_convert_to_db((odm_convert_to_linear(rx_power_ant0) + odm_convert_to_linear(rx_power_ant1))>>1); /*averaged PWDB*/ - + rssi_avg = (u8)odm_convert_to_db((phydm_db_2_linear(rx_power_ant0) + phydm_db_2_linear(rx_power_ant1)) >> 1); /*@averaged PWDB*/ + } else { - rx_power_ant0 = (u8)p_phy_info->rx_pwdb_all; + rx_power_ant0 = (u8)phy_info->rx_pwdb_all; rssi_avg = rx_power_ant0; } - + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - if ((p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) { - /*for 8822B*/ - phydm_process_rssi_for_hb_smtant_type2(p_dm_odm, p_phy_info, p_pktinfo, rssi_avg); - } else + if ((dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (fat_tab->fat_state == FAT_TRAINING_STATE)) + phydm_process_rssi_for_hb_smtant_type2(dm, phy_info, pktinfo, rssi_avg); /*@for 8822B*/ + else #endif #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 #ifdef CONFIG_FAT_PATCH - if ((p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) { - - /*[Beacon]*/ - if (p_pktinfo->is_packet_beacon) { - - pdm_sat_table->beacon_counter++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MatchBSSID_beacon_counter = ((%d))\n", pdm_sat_table->beacon_counter)); - - if (pdm_sat_table->beacon_counter >= pdm_sat_table->pre_beacon_counter + 2) { - - if (pdm_sat_table->ant_num > 1) { - next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - odm_update_rx_idle_ant(p_dm_odm, next_ant); + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1 && fat_tab->fat_state == FAT_TRAINING_STATE) { + /*@[Beacon]*/ + if (pktinfo->is_packet_beacon) { + sat_tab->beacon_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "MatchBSSID_beacon_counter = ((%d))\n", + sat_tab->beacon_counter); + + if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) { + if (sat_tab->ant_num > 1) { + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(dm, next_ant); } - pdm_sat_table->update_beam_idx++; + sat_tab->update_beam_idx++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", - pdm_sat_table->pre_beacon_counter, pdm_sat_table->pkt_counter, pdm_sat_table->update_beam_idx)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", + sat_tab->pre_beacon_counter, + sat_tab->pkt_counter, + sat_tab->update_beam_idx); - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->pkt_counter = 0; + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; } } - /*[data]*/ - else if (p_pktinfo->is_packet_to_self) { - - if (pdm_sat_table->pkt_skip_statistic_en == 0) { - /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_dm_fat_table->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); + /*@[data]*/ + else if (pktinfo->is_packet_to_self) { + if (sat_tab->pkt_skip_statistic_en == 0) { + /*@ + PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0); */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n", - p_pktinfo->station_id, pdm_sat_table->pkt_counter, p_dm_fat_table->antsel_rx_keep_0, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); - - pdm_sat_table->pkt_rssi_sum[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += rx_power_ant0; - pdm_sat_table->pkt_rssi_cnt[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; - pdm_sat_table->pkt_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n", + pktinfo->station_id, + sat_tab->pkt_counter, + fat_tab->antsel_rx_keep_0, + sat_tab->fast_training_beam_num, + rx_power_ant0); + + sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0; + sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++; + sat_tab->pkt_counter++; - #if 1 - train_pkt_number = pdm_sat_table->beam_train_cnt[p_dm_fat_table->rx_idle_ant - 1][pdm_sat_table->fast_training_beam_num]; - #else - train_pkt_number = pdm_sat_table->per_beam_training_pkt_num; - #endif +#if 1 + train_pkt_number = sat_tab->beam_train_cnt[fat_tab->rx_idle_ant - 1][sat_tab->fast_training_beam_num]; +#else + train_pkt_number = sat_tab->per_beam_training_pkt_num; +#endif /*Swich Antenna erery N pkts*/ - if (pdm_sat_table->pkt_counter == train_pkt_number) { - - if (pdm_sat_table->ant_num > 1) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number)); - next_ant = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; - odm_update_rx_idle_ant(p_dm_odm, next_ant); + if (sat_tab->pkt_counter == train_pkt_number) { + if (sat_tab->ant_num > 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number); + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(dm, next_ant); } - pdm_sat_table->update_beam_idx++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n", - pdm_sat_table->pre_beacon_counter, pdm_sat_table->update_beam_idx)); + sat_tab->update_beam_idx++; + PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n", + sat_tab->pre_beacon_counter, sat_tab->update_beam_idx); - pdm_sat_table->pre_beacon_counter = pdm_sat_table->beacon_counter; - pdm_sat_table->pkt_counter = 0; + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; } } } - /*Swich Beam after switch "pdm_sat_table->ant_num" antennas*/ - if (pdm_sat_table->update_beam_idx == pdm_sat_table->ant_num) { - - pdm_sat_table->update_beam_idx = 0; - pdm_sat_table->pkt_counter = 0; - beam_tmp = pdm_sat_table->fast_training_beam_num; - - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant - 1)) { + /*Swich Beam after switch "sat_tab->ant_num" antennas*/ + if (sat_tab->update_beam_idx == sat_tab->ant_num) { + sat_tab->update_beam_idx = 0; + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; - p_dm_fat_table->fat_state = FAT_DECISION_STATE; - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); - #else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_decision_workitem); - #endif + if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) { + fat_tab->fat_state = FAT_DECISION_STATE; +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + odm_fast_ant_training_hl_smart_antenna_type1(dm); +#else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem); +#endif } else { - pdm_sat_table->fast_training_beam_num++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); - phydm_set_all_ant_same_beam_num(p_dm_odm); - - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; + sat_tab->fast_training_beam_num++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "Update Beam_num (( %d )) -> (( %d ))\n", + beam_tmp, + sat_tab->fast_training_beam_num); + phydm_set_all_ant_same_beam_num(dm); + + fat_tab->fat_state = FAT_TRAINING_STATE; } } - } #else - if (p_dm_odm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { - if ((p_dm_odm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) && - (p_pktinfo->is_packet_to_self) && - (p_dm_fat_table->fat_state == FAT_TRAINING_STATE) - ) { - - if (pdm_sat_table->pkt_skip_statistic_en == 0) { - /* - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_dm_fat_table->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { + if ((dm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) && + pktinfo->is_packet_to_self && + fat_tab->fat_state == FAT_TRAINING_STATE) { + if (sat_tab->pkt_skip_statistic_en == 0) { + /*@ + PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0); */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", - p_pktinfo->station_id, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->is_packet_to_self, pdm_sat_table->fast_training_beam_num, rx_power_ant0)); - - - pdm_sat_table->pkt_rssi_sum[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += rx_power_ant0; - pdm_sat_table->pkt_rssi_cnt[p_dm_fat_table->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; - pdm_sat_table->pkt_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "StaID[%d]: antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pktinfo->station_id, + fat_tab->antsel_rx_keep_0, + pktinfo->is_packet_to_self, + sat_tab->fast_training_beam_num, + rx_power_ant0); + + sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0; + sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++; + sat_tab->pkt_counter++; /*swich beam every N pkt*/ - if ((pdm_sat_table->pkt_counter) >= (pdm_sat_table->per_beam_training_pkt_num)) { - - pdm_sat_table->pkt_counter = 0; - beam_tmp = pdm_sat_table->fast_training_beam_num; - - if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant - 1)) { + if (sat_tab->pkt_counter >= sat_tab->per_beam_training_pkt_num) { + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; - p_dm_fat_table->fat_state = FAT_DECISION_STATE; - - #if DEV_BUS_TYPE == RT_PCI_INTERFACE - odm_fast_ant_training_hl_smart_antenna_type1(p_dm_odm); - #else - odm_schedule_work_item(&pdm_sat_table->hl_smart_antenna_decision_workitem); - #endif + if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) { + fat_tab->fat_state = FAT_DECISION_STATE; +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + odm_fast_ant_training_hl_smart_antenna_type1(dm); +#else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem); +#endif } else { - pdm_sat_table->fast_training_beam_num++; - phydm_set_all_ant_same_beam_num(p_dm_odm); + sat_tab->fast_training_beam_num++; + phydm_set_all_ant_same_beam_num(dm); - p_dm_fat_table->fat_state = FAT_TRAINING_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + fat_tab->fat_state = FAT_TRAINING_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num); } } } @@ -5691,433 +4840,594 @@ odm_process_rssi_for_ant_div( #endif else #endif - if (p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) { - if ((p_dm_odm->support_ic_type & ODM_SMART_ANT_SUPPORT) && (p_pktinfo->is_packet_to_self) && (p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) { /* (p_pktinfo->is_packet_match_bssid && (!p_pktinfo->is_packet_beacon)) */ - u8 antsel_tr_mux; - antsel_tr_mux = (p_dm_fat_table->antsel_rx_keep_2 << 2) | (p_dm_fat_table->antsel_rx_keep_1 << 1) | p_dm_fat_table->antsel_rx_keep_0; - p_dm_fat_table->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0; - p_dm_fat_table->ant_rssi_cnt[antsel_tr_mux]++; - } - } else { /* ant_div_type != CG_TRX_SMART_ANTDIV */ - if ((p_dm_odm->support_ic_type & ODM_ANTDIV_SUPPORT) && (p_pktinfo->is_packet_to_self || p_dm_fat_table->use_ctrl_frame_antdiv)) { - - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { - - if (is_cck_rate || (p_dm_odm->support_ic_type == ODM_RTL8188F)) - p_dm_fat_table->antsel_rx_keep_0 = (p_dm_fat_table->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; - - odm_antsel_statistics(p_dm_odm, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_power_ant0, RSSI_METHOD, is_cck_rate); - - } else { + if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) { + if ((dm->support_ic_type & ODM_SMART_ANT_SUPPORT) && pktinfo->is_packet_to_self && fat_tab->fat_state == FAT_TRAINING_STATE) { /* @(pktinfo->is_packet_match_bssid && (!pktinfo->is_packet_beacon)) */ + u8 antsel_tr_mux; + antsel_tr_mux = (fat_tab->antsel_rx_keep_2 << 2) | (fat_tab->antsel_rx_keep_1 << 1) | fat_tab->antsel_rx_keep_0; + fat_tab->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0; + fat_tab->ant_rssi_cnt[antsel_tr_mux]++; + } + } else { /* @ant_div_type != CG_TRX_SMART_ANTDIV */ + if ((dm->support_ic_type & ODM_ANTDIV_SUPPORT) && (pktinfo->is_packet_to_self || fat_tab->use_ctrl_frame_antdiv)) { + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + if (pktinfo->is_cck_rate || dm->support_ic_type == ODM_RTL8188F) + fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G; - odm_antsel_statistics(p_dm_odm, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_power_ant0, RSSI_METHOD, is_cck_rate); + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_power_ant0, RSSI_METHOD, pktinfo->is_cck_rate); - #ifdef ODM_EVM_ENHANCE_ANTDIV - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - if (!is_cck_rate) - odm_antsel_statistics(p_dm_odm, p_dm_fat_table->antsel_rx_keep_0, p_pktinfo->station_id, rx_evm_ant0, EVM_METHOD, is_cck_rate); + } else { + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_power_ant0, RSSI_METHOD, pktinfo->is_cck_rate); + #ifdef ODM_EVM_ENHANCE_ANTDIV + if (dm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC) { + if (!pktinfo->is_cck_rate) { + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_evm_ant0, EVM_METHOD, pktinfo->is_cck_rate); + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_evm_ant0, TP_METHOD, pktinfo->is_cck_rate); } - #endif } + #endif } } - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("is_cck_rate=%d, PWDB_ALL=%d\n",is_cck_rate, p_phy_info->rx_pwdb_all)); */ - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",p_dm_fat_table->antsel_rx_keep_2, p_dm_fat_table->antsel_rx_keep_1, p_dm_fat_table->antsel_rx_keep_0)); */ + } +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV,"is_cck_rate=%d, pwdb_all=%d\n",pktinfo->is_cck_rate, phy_info->rx_pwdb_all); */ + /* PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=3'b%d%d%d\n",fat_tab->antsel_rx_keep_2, fat_tab->antsel_rx_keep_1, fat_tab->antsel_rx_keep_0); */ +#endif } #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -void -odm_set_tx_ant_by_tx_info( - void *p_dm_void, - u8 *p_desc, - u8 mac_id +void odm_set_tx_ant_by_tx_info( + void *dm_void, + u8 *desc, + u8 mac_id -) + ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) + if (!(dm->support_ability & ODM_BB_ANT_DIV)) return; - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) return; - - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (dm->support_ic_type == ODM_RTL8723B) { #if (RTL8723B_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_8723B(p_desc, p_dm_fat_table->antsel_a[mac_id]); - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", - mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ + SET_TX_DESC_ANTSEL_A_8723B(desc, fat_tab->antsel_a[mac_id]); + /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/ #endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8821) { + } else if (dm->support_ic_type == ODM_RTL8821) { #if (RTL8821A_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_8812(p_desc, p_dm_fat_table->antsel_a[mac_id]); - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", - mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ + SET_TX_DESC_ANTSEL_A_8812(desc, fat_tab->antsel_a[mac_id]); + /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/ #endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + } else if (dm->support_ic_type == ODM_RTL8188E) { #if (RTL8188E_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_88E(p_desc, p_dm_fat_table->antsel_a[mac_id]); - SET_TX_DESC_ANTSEL_B_88E(p_desc, p_dm_fat_table->antsel_b[mac_id]); - SET_TX_DESC_ANTSEL_C_88E(p_desc, p_dm_fat_table->antsel_c[mac_id]); - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", - mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ + SET_TX_DESC_ANTSEL_A_88E(desc, fat_tab->antsel_a[mac_id]); + SET_TX_DESC_ANTSEL_B_88E(desc, fat_tab->antsel_b[mac_id]); + SET_TX_DESC_ANTSEL_C_88E(desc, fat_tab->antsel_c[mac_id]); + /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/ #endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + } else if (dm->support_ic_type == ODM_RTL8821C) { #if (RTL8821C_SUPPORT == 1) - SET_TX_DESC_ANTSEL_A_8821C(p_desc, p_dm_fat_table->antsel_a[mac_id]); - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", - mac_id, p_dm_fat_table->antsel_c[mac_id], p_dm_fat_table->antsel_b[mac_id], p_dm_fat_table->antsel_a[mac_id]));*/ + SET_TX_DESC_ANTSEL_A_8821C(desc, fat_tab->antsel_a[mac_id]); + /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/ #endif + } else if (dm->support_ic_type == ODM_RTL8822B) { +#if (RTL8822B_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_8822B(desc, fat_tab->antsel_a[mac_id]); +#endif + } } #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) -void -odm_set_tx_ant_by_tx_info( - struct rtl8192cd_priv *priv, - struct tx_desc *pdesc, - unsigned short aid -) +void odm_set_tx_ant_by_tx_info( + struct rtl8192cd_priv *priv, + struct tx_desc *pdesc, + unsigned short aid) { - struct PHY_DM_STRUCT *p_dm_odm = &(priv->pshare->_dmodm); - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &priv->pshare->_dmodm.dm_fat_table; - u32 support_ic_type = priv->pshare->_dmodm.support_ic_type; + struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/ + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) + if (!(dm->support_ability & ODM_BB_ANT_DIV)) return; - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) return; - if (support_ic_type == ODM_RTL8881A) { + if (dm->support_ic_type == ODM_RTL8881A) { +#if 0 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__); */ - pdesc->dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16))); - pdesc->dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16); - } else if (support_ic_type == ODM_RTL8192E) { +#endif + pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16))); + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + } else if (dm->support_ic_type == ODM_RTL8192E) { +#if 0 + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */ +#endif + pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16))); + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + } else if (dm->support_ic_type == ODM_RTL8197F) { +#if 0 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */ - pdesc->dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16))); - pdesc->dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16); - } else if (support_ic_type == ODM_RTL8188E) { +#endif + pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16))); + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + } else if (dm->support_ic_type == ODM_RTL8822B) { + pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16))); + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + } else if (dm->support_ic_type == ODM_RTL8188E) { +#if 0 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/ - pdesc->dword2 &= set_desc(~BIT(24)); - pdesc->dword2 &= set_desc(~BIT(25)); - pdesc->dword7 &= set_desc(~BIT(29)); - - pdesc->dword2 |= set_desc(p_dm_fat_table->antsel_a[aid] << 24); - pdesc->dword2 |= set_desc(p_dm_fat_table->antsel_b[aid] << 25); - pdesc->dword7 |= set_desc(p_dm_fat_table->antsel_c[aid] << 29); +#endif + pdesc->Dword2 &= set_desc(~BIT(24)); + pdesc->Dword2 &= set_desc(~BIT(25)); + pdesc->Dword7 &= set_desc(~BIT(29)); + pdesc->Dword2 |= set_desc(fat_tab->antsel_a[aid] << 24); + pdesc->Dword2 |= set_desc(fat_tab->antsel_b[aid] << 25); + pdesc->Dword7 |= set_desc(fat_tab->antsel_c[aid] << 29); - } else if (support_ic_type == ODM_RTL8812) { - /*[path-A]*/ + } else if (dm->support_ic_type == ODM_RTL8812) { + /*@[path-A]*/ +#if 0 /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/ +#endif - pdesc->dword6 &= set_desc(~BIT(16)); - pdesc->dword6 &= set_desc(~BIT(17)); - pdesc->dword6 &= set_desc(~BIT(18)); - - pdesc->dword6 |= set_desc(p_dm_fat_table->antsel_a[aid] << 16); - pdesc->dword6 |= set_desc(p_dm_fat_table->antsel_b[aid] << 17); - pdesc->dword6 |= set_desc(p_dm_fat_table->antsel_c[aid] << 18); + pdesc->Dword6 &= set_desc(~BIT(16)); + pdesc->Dword6 &= set_desc(~BIT(17)); + pdesc->Dword6 &= set_desc(~BIT(18)); + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + pdesc->Dword6 |= set_desc(fat_tab->antsel_b[aid] << 17); + pdesc->Dword6 |= set_desc(fat_tab->antsel_c[aid] << 18); } } - -#if 1 /*def CONFIG_WLAN_HAL*/ -void -odm_set_tx_ant_by_tx_info_hal( - struct rtl8192cd_priv *priv, - void *pdesc_data, - u16 aid -) +#if 1 /*@def CONFIG_WLAN_HAL*/ +void odm_set_tx_ant_by_tx_info_hal( + struct rtl8192cd_priv *priv, + void *pdesc_data, + u16 aid) { - struct PHY_DM_STRUCT *p_dm_odm = &(priv->pshare->_dmodm); - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &priv->pshare->_dmodm.dm_fat_table; - u32 support_ic_type = priv->pshare->_dmodm.support_ic_type; - PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data; + struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/ + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data; - if (!(p_dm_odm->support_ability & ODM_BB_ANT_DIV)) + if (!(dm->support_ability & ODM_BB_ANT_DIV)) return; - if (p_dm_odm->ant_div_type == CGCS_RX_HW_ANTDIV) + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) return; - if (support_ic_type == ODM_RTL8881A || support_ic_type == ODM_RTL8192E || support_ic_type == ODM_RTL8814A) { + if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B)) { +#if 0 /*panic_printk("[%s] [%d] ******odm_set_tx_ant_by_tx_info_hal******\n",__FUNCTION__,__LINE__);*/ +#endif pdescdata->ant_sel = 1; - pdescdata->ant_sel_a = p_dm_fat_table->antsel_a[aid]; + pdescdata->ant_sel_a = fat_tab->antsel_a[aid]; } } -#endif /*#ifdef CONFIG_WLAN_HAL*/ +#endif /*@#ifdef CONFIG_WLAN_HAL*/ #endif - -void -odm_ant_div_config( - void *p_dm_void -) +void odm_ant_div_config( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("WIN Config Antenna Diversity\n")); - /* - if(p_dm_odm->support_ic_type==ODM_RTL8723B) + PHYDM_DBG(dm, DBG_ANT_DIV, "WIN Config Antenna Diversity\n"); + /*@ + if(dm->support_ic_type==ODM_RTL8723B) { - if((!p_dm_odm->dm_swat_table.ANTA_ON || !p_dm_odm->dm_swat_table.ANTB_ON)) - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + if((!dm->dm_swat_table.ANTA_ON || !dm->dm_swat_table.ANTB_ON)) + dm->support_ability &= ~(ODM_BB_ANT_DIV); } */ - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + #if (defined(CONFIG_2T3R_ANTENNA)) + #if (RTL8822B_SUPPORT == 1) + dm->rfe_type = ANT_2T3R_RFE_TYPE; + #endif + #endif - p_dm_odm->ant_div_type = S0S1_TRX_HW_ANTDIV; - /**/ - } -#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + #if (defined(CONFIG_2T4R_ANTENNA)) + #if (RTL8822B_SUPPORT == 1) + dm->rfe_type = ANT_2T4R_RFE_TYPE; + #endif + #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CE Config Antenna Diversity\n")); + if (dm->support_ic_type == ODM_RTL8723D) + dm->ant_div_type = S0S1_TRX_HW_ANTDIV; +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, "CE Config Antenna Diversity\n"); + if (dm->support_ic_type == ODM_RTL8723B) + dm->ant_div_type = S0S1_SW_ANTDIV; + if (dm->support_ic_type == ODM_RTL8723D) + dm->ant_div_type = S0S1_SW_ANTDIV; #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AP Config Antenna Diversity\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, "AP Config Antenna Diversity\n"); - /* 2 [ NOT_SUPPORT_ANTDIV ] */ + /* @2 [ NOT_SUPPORT_ANTDIV ] */ #if (defined(CONFIG_NOT_SUPPORT_ANTDIV)) - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n")); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n"); - /* 2 [ 2G&5G_SUPPORT_ANTDIV ] */ + /* @2 [ 2G&5G_SUPPORT_ANTDIV ] */ #elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n")); - p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n"); + fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G); - if (p_dm_odm->support_ic_type & ODM_ANTDIV_SUPPORT) - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + if (dm->support_ic_type & ODM_ANTDIV_SUPPORT) + dm->support_ability |= ODM_BB_ANT_DIV; + if (*dm->band_type == ODM_BAND_5G) { #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY)) - p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_SMART_ANTDIV\n")); + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n"); #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n")); + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n"); #endif - } else if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { + } else if (*dm->band_type == ODM_BAND_2_4G) { #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY)) - p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n")); + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n"); #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n")); + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n"); #endif } - /* 2 [ 5G_SUPPORT_ANTDIV ] */ + /* @2 [ 5G_SUPPORT_ANTDIV ] */ #elif (defined(CONFIG_5G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"); panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"); - p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_5G); - if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - if (p_dm_odm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC) - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; + fat_tab->ant_div_2g_5g = (ODM_ANTDIV_5G); + if (*dm->band_type == ODM_BAND_5G) { + if (dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC) + dm->support_ability |= ODM_BB_ANT_DIV; #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY)) - p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; + dm->ant_div_type = CG_TRX_HW_ANTDIV; panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = CG_SMART_ANTDIV\n")); + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n"); #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n")); + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n"); #endif - } else if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Not Support 2G ant_div_type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + } else if (*dm->band_type == ODM_BAND_2_4G) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 2G ant_div_type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); } - /* 2 [ 2G_SUPPORT_ANTDIV ] */ + /* @2 [ 2G_SUPPORT_ANTDIV ] */ #elif (defined(CONFIG_2G_SUPPORT_ANTDIV)) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n")); - p_dm_fat_table->ant_div_2g_5g = (ODM_ANTDIV_2G); - if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { - if (p_dm_odm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC) - p_dm_odm->support_ability |= ODM_BB_ANT_DIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n"); + fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G); + if (*dm->band_type == ODM_BAND_2_4G) { + if (dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC) + dm->support_ability |= ODM_BB_ANT_DIV; #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY)) - p_dm_odm->ant_div_type = CGCS_RX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n")); + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_HW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n")); + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = CG_TRX_SMART_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n")); + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n"); #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY)) - p_dm_odm->ant_div_type = S0S1_SW_ANTDIV; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n")); + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n"); #endif - } else if (*p_dm_odm->p_band_type == ODM_BAND_5G) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Not Support 5G ant_div_type\n")); - p_dm_odm->support_ability &= ~(ODM_BB_ANT_DIV); + } else if (*dm->band_type == ODM_BAND_5G) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 5G ant_div_type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); } #endif #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n", ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0))); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv Config Info] be_fix_tx_ant = ((%d))\n", p_dm_odm->dm_fat_table.b_fix_tx_ant)); - + PHYDM_DBG(dm, DBG_ANT_DIV, + "[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n", + ((dm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[AntDiv Config Info] be_fix_tx_ant = ((%d))\n", + dm->dm_fat_table.b_fix_tx_ant); } - -void -odm_ant_div_timers( - void *p_dm_void, - u8 state -) +void odm_ant_div_timers( + void *dm_void, + u8 state) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (state == INIT_ANTDIV_TIMMER) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_initialize_timer(p_dm_odm, &(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_timer), - (void *)odm_sw_antdiv_callback, NULL, "phydm_sw_antenna_switch_timer"); + odm_initialize_timer(dm, + &dm->dm_swat_table.phydm_sw_antenna_switch_timer, + (void *)odm_sw_antdiv_callback, NULL, + "phydm_sw_antenna_switch_timer"); #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - odm_initialize_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer, - (void *)odm_fast_ant_training_callback, NULL, "fast_ant_training_timer"); + odm_initialize_timer(dm, &dm->fast_ant_training_timer, + (void *)odm_fast_ant_training_callback, NULL, "fast_ant_training_timer"); #endif #ifdef ODM_EVM_ENHANCE_ANTDIV - odm_initialize_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer, - (void *)odm_evm_fast_ant_training_callback, NULL, "evm_fast_ant_training_timer"); + odm_initialize_timer(dm, &dm->evm_fast_ant_training_timer, + (void *)phydm_evm_antdiv_callback, NULL, + "evm_fast_ant_training_timer"); #endif } else if (state == CANCEL_ANTDIV_TIMMER) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_cancel_timer(p_dm_odm, &(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_timer)); + odm_cancel_timer(dm, + &dm->dm_swat_table.phydm_sw_antenna_switch_timer); #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - odm_cancel_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer); + odm_cancel_timer(dm, &dm->fast_ant_training_timer); #endif #ifdef ODM_EVM_ENHANCE_ANTDIV - odm_cancel_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer); + odm_cancel_timer(dm, &dm->evm_fast_ant_training_timer); #endif } else if (state == RELEASE_ANTDIV_TIMMER) { #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_release_timer(p_dm_odm, &(p_dm_odm->dm_swat_table.phydm_sw_antenna_switch_timer)); + odm_release_timer(dm, + &dm->dm_swat_table.phydm_sw_antenna_switch_timer); #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - odm_release_timer(p_dm_odm, &p_dm_odm->fast_ant_training_timer); + odm_release_timer(dm, &dm->fast_ant_training_timer); #endif #ifdef ODM_EVM_ENHANCE_ANTDIV - odm_release_timer(p_dm_odm, &p_dm_odm->evm_fast_ant_training_timer); + odm_release_timer(dm, &dm->evm_fast_ant_training_timer); #endif } - } -void -phydm_antdiv_debug( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) +void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - /*struct _FAST_ANTENNA_TRAINNING_* p_dm_fat_table = &p_dm_odm->dm_fat_table;*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; u32 used = *_used; u32 out_len = *_out_len; + u32 dm_value[10] = {0}; + char help[] = "-h"; + u8 i, input_idx = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; - if (dm_value[0] == 1) { /*fixed or auto antenna*/ + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {0:auto, 1:fix main, 2:fix auto}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} {antdiv_period}\n"); + #if (RTL8821C_SUPPORT == 1) + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3} {en} {0:Default, 1:HW_Div, 2:SW_Div}\n"); + #endif + } else if (dm_value[0] == 1) { + /*@fixed or auto antenna*/ if (dm_value[1] == 0) { - p_dm_odm->antdiv_select = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Auto\n")); + dm->ant_type = ODM_AUTO_ANT; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: Auto\n"); } else if (dm_value[1] == 1) { - p_dm_odm->antdiv_select = 1; - PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Fix MAin\n")); + dm->ant_type = ODM_FIX_MAIN_ANT; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: Fix Main\n"); } else if (dm_value[1] == 2) { - p_dm_odm->antdiv_select = 2; - PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv: Fix Aux\n")); + dm->ant_type = ODM_FIX_AUX_ANT; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: Fix Aux\n"); } - } else if (dm_value[0] == 2) { /*dynamic period for AntDiv*/ - p_dm_odm->antdiv_period = (u8)dm_value[1]; - PHYDM_SNPRINTF((output + used, out_len - used, "AntDiv_period = ((%d))\n", p_dm_odm->antdiv_period)); + if (dm->ant_type != ODM_AUTO_ANT) { + odm_stop_antenna_switch_dm(dm); + if (dm->ant_type == ODM_FIX_MAIN_ANT) + odm_update_rx_idle_ant(dm, MAIN_ANT); + else if (dm->ant_type == ODM_FIX_AUX_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); + } else { + phydm_enable_antenna_diversity(dm); + } + dm->pre_ant_type = dm->ant_type; + } else if (dm_value[0] == 2) { + /*@dynamic period for AntDiv*/ + dm->antdiv_period = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv_period=((%d))\n", dm->antdiv_period); } -} + #if (RTL8821C_SUPPORT == 1) + else if (dm_value[0] == 3 && + dm->support_ic_type == ODM_RTL8821C) { + /*Only for 8821C*/ + if (dm_value[1] == 0) { + fat_tab->force_antdiv_type = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[8821C] AntDiv: Default\n"); + } else if (dm_value[1] == 1) { + fat_tab->force_antdiv_type = true; + fat_tab->antdiv_type_dbg = CG_TRX_HW_ANTDIV; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[8821C] AntDiv: HW diversity\n"); + } else if (dm_value[1] == 2) { + fat_tab->force_antdiv_type = true; + fat_tab->antdiv_type_dbg = S0S1_SW_ANTDIV; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[8821C] AntDiv: SW diversity\n"); + } + } + #endif + #ifdef ODM_EVM_ENHANCE_ANTDIV + else if (dm_value[0] == 4) { + if (dm_value[1] == 0) { + /*@init parameters for EVM AntDiv*/ + phydm_evm_sw_antdiv_init(dm); + PDM_SNPF(out_len, used, output + used, out_len - used, + "init evm antdiv parameters\n"); + } else if (dm_value[1] == 1) { + /*training number for EVM AntDiv*/ + dm->antdiv_train_num = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "antdiv_train_num = ((%d))\n", + dm->antdiv_train_num); + } else if (dm_value[1] == 2) { + /*training interval for EVM AntDiv*/ + dm->antdiv_intvl = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "antdiv_intvl = ((%d))\n", + dm->antdiv_intvl); + } else if (dm_value[1] == 3) { + /*@function period for EVM AntDiv*/ + dm->evm_antdiv_period = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "evm_antdiv_period = ((%d))\n", + dm->evm_antdiv_period); + } else if (dm_value[1] == 100) {/*show parameters*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "ant_type = ((%d))\n", dm->ant_type); + PDM_SNPF(out_len, used, output + used, out_len - used, + "antdiv_train_num = ((%d))\n", + dm->antdiv_train_num); + PDM_SNPF(out_len, used, output + used, out_len - used, + "antdiv_intvl = ((%d))\n", + dm->antdiv_intvl); + PDM_SNPF(out_len, used, output + used, out_len - used, + "evm_antdiv_period = ((%d))\n", + dm->evm_antdiv_period); + } + } + #ifdef CONFIG_2T4R_ANTENNA + else if (dm_value[0] == 5) { /*Only for 8822B 2T4R case*/ + + if (dm_value[1] == 0) { + dm->ant_type2 = ODM_AUTO_ANT; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: PathB Auto\n"); + } else if (dm_value[1] == 1) { + dm->ant_type2 = ODM_FIX_MAIN_ANT; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: PathB Fix Main\n"); + } else if (dm_value[1] == 2) { + dm->ant_type2 = ODM_FIX_AUX_ANT; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: PathB Fix Aux\n"); + } -#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ + if (dm->ant_type2 != ODM_AUTO_ANT) { + odm_stop_antenna_switch_dm(dm); + if (dm->ant_type2 == ODM_FIX_MAIN_ANT) + phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT); + else if (dm->ant_type2 == ODM_FIX_AUX_ANT) + phydm_update_rx_idle_ant_pathb(dm, AUX_ANT); + } else { + phydm_enable_antenna_diversity(dm); + } + dm->pre_ant_type2 = dm->ant_type2; + } + #endif + #endif + *_used = used; + *_out_len = out_len; +} -void -odm_ant_div_reset( - void *p_dm_void -) +void odm_ant_div_reset(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { -#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_s0s1_sw_ant_div_reset(p_dm_odm); -#endif - } + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + if (dm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_reset(dm); + #endif +} +void odm_antenna_diversity_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_ant_div_config(dm); + odm_ant_div_init(dm); } -void -odm_antenna_diversity_init( - void *p_dm_void -) +void odm_antenna_diversity(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; -#if 0 - if (p_dm_odm->mp_mode == true) + if (*dm->mp_mode) return; -#endif -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - odm_ant_div_config(p_dm_odm); - odm_ant_div_init(p_dm_odm); -#endif -} + if (!(dm->support_ability & ODM_BB_ANT_DIV)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] Not Support Antenna Diversity Function\n"); + return; + } -void -odm_antenna_diversity( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (p_dm_odm->mp_mode == true) + if (dm->pause_ability & ODM_BB_ANT_DIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Return: Pause AntDIv in LV=%d\n", + dm->pause_lv_table.lv_antdiv); return; + } -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - odm_ant_div(p_dm_odm); -#endif + odm_ant_div(dm); } +#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/ + diff --git a/hal/phydm/phydm_antdiv.h b/hal/phydm/phydm_antdiv.h index 692b58a..a5ed6b7 100644 --- a/hal/phydm/phydm_antdiv.h +++ b/hal/phydm/phydm_antdiv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,44 +8,50 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ - -#ifndef __PHYDMANTDIV_H__ -#define __PHYDMANTDIV_H__ - -/*#define ANTDIV_VERSION "2.0" //2014.11.04*/ -/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ -/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ -/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/ -/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/ -/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT, - because antenna diversity only works when BT is disable or radio off*/ -/*#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/ -/*#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/ -/*#define ANTDIV_VERSION "3.6"*/ /*2015.11.16 Stanley */ -/*#define ANTDIV_VERSION "3.7"*/ /*2015.11.20 Dino Add SmartAnt FAT Patch */ -/*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */ -#define ANTDIV_VERSION "3.9" /*2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */ - -/* 1 ============================================================ + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMANTDIV_H__ +#define __PHYDMANTDIV_H__ + +/*@#define ANTDIV_VERSION "2.0" //2014.11.04*/ +/*@#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ +/*@#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ +/*@#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/ +/*@#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/ +/*@#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT, because antenna diversity only works when BT is disable or radio off*/ +/*@#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/ +/*@#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/ +/*@#define ANTDIV_VERSION "3.6"*/ /*@2015.11.16 Stanley */ +/*@#define ANTDIV_VERSION "3.7"*/ /*@2015.11.20 Dino Add SmartAnt FAT Patch */ +/*@#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */ +/*@#define ANTDIV_VERSION "3.9" 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */ +#define ANTDIV_VERSION "4.0" /*@2017.05.25 Mark, Add SW antenna diversity for 8821c because HW transient issue */ + +/* @1 ============================================================ * 1 Definition - * 1 ============================================================ */ + * 1 ============================================================ + */ #define ANTDIV_INIT 0xff -#define MAIN_ANT 1 /*ant A or ant Main or S1*/ -#define AUX_ANT 2 /*AntB or ant Aux or S0*/ -#define MAX_ANT 3 /* 3 for AP using*/ +#define MAIN_ANT 1 /*@ant A or ant Main or S1*/ +#define AUX_ANT 2 /*@AntB or ant Aux or S0*/ +#define MAX_ANT 3 /* @3 for AP using*/ -#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ -#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ +#define ANT1_2G 0 /* @= ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ +#define ANT2_2G 1 /* @= ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ /*smart antenna*/ #define SUPPORT_RF_PATH_NUM 4 #define SUPPORT_BEAM_PATTERN_NUM 4 @@ -57,21 +63,21 @@ #define FIX_TX_AT_MAIN 1 #define FIX_AUX_AT_MAIN 2 -/* Antenna Diversty Control type */ +/* @Antenna Diversty Control type */ #define ODM_AUTO_ANT 0 #define ODM_FIX_MAIN_ANT 1 #define ODM_FIX_AUX_ANT 2 -#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A) +#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A | ODM_RTL8197F) #define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B) #define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT) #define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E) #define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B) -#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D) -#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C) +#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F) +#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | ODM_RTL8822B) -#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E) +#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B) #define ODM_ANTDIV_2G BIT(0) #define ODM_ANTDIV_5G BIT(1) @@ -79,15 +85,20 @@ #define ANTDIV_ON 1 #define ANTDIV_OFF 0 +#define ANT_PATH_A 0 +#define ANT_PATH_B 1 +#define ANT_PATH_AB 2 + #define FAT_ON 1 #define FAT_OFF 0 #define TX_BY_DESC 1 #define TX_BY_REG 0 -#define RSSI_METHOD 0 +#define RSSI_METHOD 0 #define EVM_METHOD 1 #define CRC32_METHOD 2 +#define TP_METHOD 3 #define INIT_ANTDIV_TIMMER 0 #define CANCEL_ANTDIV_TIMMER 1 @@ -131,16 +142,22 @@ #define RSSI_CHECK_RESET_PERIOD 10 #define RSSI_CHECK_THRESHOLD 50 -/*Hong Lin Smart antenna*/ +/*@Hong Lin Smart antenna*/ #define HL_SMTANT_2WIRE_DATA_LEN 24 -/* 1 ============================================================ +#if (RTL8723D_SUPPORT == 1) + #ifndef CONFIG_ANTENNA_DIVERSITY_PERIOD + #define CONFIG_ANTENNA_DIVERSITY_PERIOD 1 + #endif +#endif +/* @1 ============================================================ * 1 structure - * 1 ============================================================ */ + * 1 ============================================================ + */ -struct _sw_antenna_switch_ { - u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/ +struct sw_antenna_switch { + u8 double_chk_flag; /*@If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/ u8 try_flag; s32 pre_rssi; u8 cur_antenna; @@ -148,8 +165,8 @@ struct _sw_antenna_switch_ { u8 rssi_trying; u8 reset_idx; u8 train_time; - u8 train_time_flag; /*base on RSSI difference between two antennas*/ - struct timer_list phydm_sw_antenna_switch_timer; + u8 train_time_flag; /*@base on RSSI difference between two antennas*/ + struct phydm_timer_list phydm_sw_antenna_switch_timer; u32 pkt_cnt_sw_ant_div_by_ctrl_frame; boolean is_sw_ant_div_by_ctrl_frame; @@ -159,7 +176,7 @@ struct _sw_antenna_switch_ { #endif #endif - /* AntDect (Before link Antenna Switch check) need to be moved*/ + /* @AntDect (Before link Antenna Switch check) need to be moved*/ u16 single_ant_counter; u16 dual_ant_counter; u16 aux_fail_detec_counter; @@ -167,25 +184,22 @@ struct _sw_antenna_switch_ { u8 swas_no_link_state; u32 swas_no_link_bk_reg948; boolean ANTA_ON; /*To indicate ant A is or not*/ - boolean ANTB_ON; /*To indicate ant B is on or not*/ + boolean ANTB_ON; /*@To indicate ant B is on or not*/ boolean pre_aux_fail_detec; boolean rssi_ant_dect_result; u8 ant_5g; u8 ant_2g; - - }; - #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) struct _BF_DIV_COEX_ { boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM]; boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM]; - u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; - u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; + u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; + u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; - u8 bd_ccoex_type_wbfer; + u8 bd_ccoex_type_wbfer; u8 num_txbfee_client; u8 num_txbfer_client; u8 bdc_try_counter; @@ -208,82 +222,7 @@ struct _BF_DIV_COEX_ { #endif #endif -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) -struct _SMART_ANTENNA_TRAINNING_ { - u32 latch_time; - boolean pkt_skip_statistic_en; - u32 fix_beam_pattern_en; - u32 fix_training_num_en; - u32 fix_beam_pattern_codeword; - u32 update_beam_codeword; - u32 ant_num; /*number of "used" smart beam antenna*/ - u32 ant_num_total;/*number of "total" smart beam antenna*/ - u32 first_train_ant; /*decide witch antenna to train first*/ - - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 - u32 pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];/*rssi of each path with a certain beam pattern*/ - u8 beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; - u8 beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; - u32 rfu_codeword_table[4]; /*2G beam truth table*/ - u32 rfu_codeword_table_5g[4]; /*5G beam truth table*/ - u32 beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/ - u32 rx_idle_beam[SUPPORT_RF_PATH_NUM]; - u32 pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM]; - u32 pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM]; - #endif - - u32 fast_training_beam_num;/*current training beam_set index*/ - u32 pre_fast_training_beam_num;/*pre training beam_set index*/ - u32 rfu_codeword_total_bit_num; /* total bit number of RFU protocol*/ - u32 rfu_each_ant_bit_num; /* bit number of RFU protocol for each ant*/ - u8 per_beam_training_pkt_num; - u8 decision_holding_period; - - - u32 pre_codeword; - boolean force_update_beam_en; - u32 beacon_counter; - u32 pre_beacon_counter; - u8 pkt_counter; /*packet number that each beam-set should be colected in training state*/ - u8 update_beam_idx; /*the index announce that the beam can be updated*/ - u8 rfu_protocol_type; - u16 rfu_protocol_delay_time; - - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_WORK_ITEM hl_smart_antenna_workitem; - RT_WORK_ITEM hl_smart_antenna_decision_workitem; - #endif - - - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - u8 beam_set_avg_rssi_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; /*avg pre_rssi of each beam set*/ - u8 beam_set_train_rssi_diff[SUPPORT_BEAM_SET_PATTERN_NUM]; /*rssi of a beam pattern set, ex: a set = {ant1_beam=1, ant2_beam=3}*/ - u8 beam_set_train_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*training pkt num of each beam set*/ - u32 beam_set_rssi_avg_sum[SUPPORT_BEAM_SET_PATTERN_NUM]; /*RSSI_sum of avg(pathA,pathB) for each beam-set)*/ - u32 beam_path_rssi_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*RSSI_sum of each path for each beam-set)*/ - - u32 beam_path_evm_2ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*2SS evm_sum of each path for each beam-set)*/ - u32 beam_path_evm_2ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; - - u32 beam_path_evm_1ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM];/*1SS evm_sum of each path for each beam-set)*/ - u32 beam_path_evm_1ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; - - u32 statistic_pkt_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*statistic_pkt_cnt for SmtAnt make decision*/ - - u8 total_beam_set_num; /*number of beam set can be switched*/ - u8 total_beam_set_num_2g;/*number of beam set can be switched in 2G*/ - u8 total_beam_set_num_5g;/*number of beam set can be switched in 5G*/ - - u8 rfu_codeword_table_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*2G beam truth table*/ - u8 rfu_codeword_table_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*5G beam truth table*/ - u8 rx_idle_beam_set_idx; /*the filanl decsion result*/ - #endif - - -}; -#endif - -struct _FAST_ANTENNA_TRAINNING_ { +struct phydm_fat_struct { u8 bssid[6]; u8 antsel_rx_keep_0; u8 antsel_rx_keep_1; @@ -293,6 +232,7 @@ struct _FAST_ANTENNA_TRAINNING_ { u32 ant_rssi_cnt[7]; u32 ant_ave_rssi[7]; u8 fat_state; + u8 fat_state_cnt; u32 train_idx; u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; @@ -306,7 +246,10 @@ struct _FAST_ANTENNA_TRAINNING_ { u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; u8 rx_idle_ant; + u8 rx_idle_ant2; + u8 rvrt_val; u8 ant_div_on_off; + u8 div_path_type; boolean is_become_linked; u32 min_max_rssi; u8 idx_ant_div_counter_2g; @@ -314,13 +257,22 @@ struct _FAST_ANTENNA_TRAINNING_ { u8 ant_div_2g_5g; #ifdef ODM_EVM_ENHANCE_ANTDIV + /*@For 1SS RX phy rate*/ u32 main_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; u32 aux_ant_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; u32 main_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; u32 aux_ant_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; - boolean EVM_method_enable; + + /*@For 2SS RX phy rate*/ + u32 main_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*@2SS with A1+B*/ + u32 aux_ant_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2]; /*@2SS with A2+B*/ + u32 main_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u32 aux_ant_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + + boolean evm_method_enable; u8 target_ant_evm; u8 target_ant_crc32; + u8 target_ant_tp; u8 target_ant_enhance; u8 pre_target_ant_enhance; u16 main_mpdu_ok_cnt; @@ -332,6 +284,14 @@ struct _FAST_ANTENNA_TRAINNING_ { u32 aux_crc32_ok_cnt; u32 main_crc32_fail_cnt; u32 aux_crc32_fail_cnt; + + u32 antdiv_tp_main; + u32 antdiv_tp_aux; + u32 antdiv_tp_main_cnt; + u32 antdiv_tp_aux_cnt; + + u8 pre_antdiv_rssi; + u8 pre_antdiv_tp; #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) u32 cck_ctrl_frame_cnt_main; @@ -347,21 +307,22 @@ struct _FAST_ANTENNA_TRAINNING_ { boolean fix_ant_bfee; boolean enable_ctrl_frame_antdiv; boolean use_ctrl_frame_antdiv; + boolean *is_no_csi_feedback; + boolean force_antdiv_type; + u8 antdiv_type_dbg; u8 hw_antsw_occur; u8 *p_force_tx_ant_by_desc; - u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's outer parameter later*/ - u8 *p_default_s0_s1; - u8 default_s0_s1; + u8 force_tx_ant_by_desc; /*@A temp value, will hook to driver team's outer parameter later*/ + u8 *p_default_s0_s1; + u8 default_s0_s1; }; - -/* 1 ============================================================ +/* @1 ============================================================ * 1 enumeration - * 1 ============================================================ */ - - + * 1 ============================================================ + */ -enum fat_state_e /*Fast antenna training*/ +enum fat_state /*@Fast antenna training*/ { FAT_BEFORE_LINK_STATE = 0, FAT_PREPARE_STATE = 1, @@ -369,342 +330,215 @@ enum fat_state_e /*Fast antenna training*/ FAT_DECISION_STATE = 3 }; -enum ant_div_type_e { +enum ant_div_type { NO_ANTDIV = 0xFF, CG_TRX_HW_ANTDIV = 0x01, CGCS_RX_HW_ANTDIV = 0x02, FIXED_HW_ANTDIV = 0x03, CG_TRX_SMART_ANTDIV = 0x04, CGCS_RX_SW_ANTDIV = 0x05, - S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/ - S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/ - HL_SW_SMART_ANT_TYPE1 = 0x10, /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and each ant. is equipped with 4 antenna patterns*/ - HL_SW_SMART_ANT_TYPE2 = 0x11 /*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/ + S0S1_SW_ANTDIV = 0x06, /*@8723B intrnal switch S0 S1*/ + S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/ + HL_SW_SMART_ANT_TYPE1 = 0x10, /*@Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and each ant. is equipped with 4 antenna patterns*/ + HL_SW_SMART_ANT_TYPE2 = 0x11 /*@Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/ }; - -/* 1 ============================================================ +/* @1 ============================================================ * 1 function prototype - * 1 ============================================================ */ + * 1 ============================================================ + */ +void odm_stop_antenna_switch_dm(void *dm_void); -void -odm_stop_antenna_switch_dm( - void *p_dm_void -); +void phydm_enable_antenna_diversity(void *dm_void); -void -phydm_enable_antenna_diversity( - void *p_dm_void -); +void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C, .... */ + ); -void -odm_set_ant_config( - void *p_dm_void, - u8 ant_setting /* 0=A, 1=B, 2=C, .... */ -); +#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link +void odm_sw_ant_div_rest_after_link(void *dm_void); -#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link +void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path); -void odm_sw_ant_div_rest_after_link( - void *p_dm_void -); +void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch); #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) -void -phydm_antdiv_reset_statistic( - void *p_dm_void, - u32 macid -); +void phydm_antdiv_reset_statistic( + void *dm_void, + u32 macid); + +void odm_update_rx_idle_ant( + void *dm_void, + u8 ant); + +void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant); -void -odm_update_rx_idle_ant( - void *p_dm_void, - u8 ant -); +void phydm_set_antdiv_val( + void *dm_void, + u32 *val_buf, + u8 val_len); #if (RTL8723B_SUPPORT == 1) -void -odm_update_rx_idle_ant_8723b( - void *p_dm_void, - u8 ant, - u32 default_ant, - u32 optional_ant -); +void odm_update_rx_idle_ant_8723b( + void *dm_void, + u8 ant, + u32 default_ant, + u32 optional_ant); #endif #if (RTL8188F_SUPPORT == 1) -void -phydm_update_rx_idle_antenna_8188F( - void *p_dm_void, - u32 default_ant -); +void phydm_update_rx_idle_antenna_8188F( + void *dm_void, + u32 default_ant); #endif #if (RTL8723D_SUPPORT == 1) -void -phydm_set_tx_ant_pwr_8723d( - void *p_dm_void, - u8 ant -); +void phydm_set_tx_ant_pwr_8723d( + void *dm_void, + u8 ant); -void -odm_update_rx_idle_ant_8723d( - void *p_dm_void, - u8 ant, - u32 default_ant, - u32 optional_ant -); +void odm_update_rx_idle_ant_8723d( + void *dm_void, + u8 ant, + u32 default_ant, + u32 optional_ant); #endif #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -odm_sw_antdiv_callback( - struct timer_list *p_timer -); - -void -odm_sw_antdiv_workitem_callback( - void *p_context -); +void odm_sw_antdiv_callback( + struct phydm_timer_list *timer); +void odm_sw_antdiv_workitem_callback( + void *context); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -void -odm_sw_antdiv_workitem_callback( - void *p_context -); +void odm_sw_antdiv_workitem_callback( + void *context); -void -odm_sw_antdiv_callback( - void *function_context -); +void odm_sw_antdiv_callback( + void *function_context); #endif -void -odm_s0s1_sw_ant_div_by_ctrl_frame( - void *p_dm_void, - u8 step -); - -void -odm_antsel_statistics_of_ctrl_frame( - void *p_dm_void, - u8 antsel_tr_mux, - u32 rx_pwdb_all -); - -void -odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void -); - -#endif +void odm_s0s1_sw_ant_div_by_ctrl_frame( + void *dm_void, + u8 step); -#ifdef ODM_EVM_ENHANCE_ANTDIV -void -odm_evm_fast_ant_training_callback( - void *p_dm_void -); -#endif +void odm_antsel_statistics_of_ctrl_frame( + void *dm_void, + u8 antsel_tr_mux, + u32 rx_pwdb_all); -void -odm_hw_ant_div( - void *p_dm_void -); +void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi( + void *dm_void, + void *phy_info_void, + void *pkt_info_void); -#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) -void -odm_fast_ant_training( - void *p_dm_void -); - -void -odm_fast_ant_training_callback( - void *p_dm_void -); - -void -odm_fast_ant_training_work_item_callback( - void *p_dm_void -); #endif - -#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) +#ifdef ODM_EVM_ENHANCE_ANTDIV +void phydm_evm_sw_antdiv_init( + void *dm_void); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -phydm_beam_switch_workitem_callback( - void *p_context -); +void phydm_evm_antdiv_callback( + struct phydm_timer_list *timer); -void -phydm_beam_decision_workitem_callback( - void *p_context -); - -#endif +void phydm_evm_antdiv_workitem_callback( + void *context); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void phydm_evm_antdiv_callback( + void *dm_void); +void phydm_evm_antdiv_workitem_callback( + void *context); -#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - -void -phydm_update_beam_pattern_type2( - void *p_dm_void, - u32 codeword, - u32 codeword_length -); - -void -phydm_set_rfu_beam_pattern_type2( - void *p_dm_void -); - -void -phydm_hl_smart_ant_debug_type2( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -); - -#elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) - -void -phydm_update_beam_pattern( - void *p_dm_void, - u32 codeword, - u32 codeword_length -); - -void -phydm_set_all_ant_same_beam_num( - void *p_dm_void -); - -void -phydm_hl_smart_ant_debug( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -); +#else +void phydm_evm_antdiv_callback( + void *dm_void); +#endif #endif +void odm_hw_ant_div( + void *dm_void); -#endif/*#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) || (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))*/ +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) +void odm_fast_ant_training( + void *dm_void); -void -odm_ant_div_init( - void *p_dm_void -); +void odm_fast_ant_training_callback( + void *dm_void); -void -odm_ant_div( - void *p_dm_void -); +void odm_fast_ant_training_work_item_callback( + void *dm_void); +#endif -void -odm_antsel_statistics( - void *p_dm_void, - u8 antsel_tr_mux, - u32 mac_id, - u32 utility, - u8 method, - u8 is_cck_rate -); +void odm_ant_div_init( + void *dm_void); -void -odm_process_rssi_for_ant_div( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void -); +void odm_ant_div( + void *dm_void); +void odm_antsel_statistics( + void *dm_void, + void *phy_info_void, + u8 antsel_tr_mux, + u32 mac_id, + u32 utility, + u8 method, + u8 is_cck_rate); +void odm_process_rssi_for_ant_div( + void *dm_void, + void *phy_info_void, + void *pkt_info_void); #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -void -odm_set_tx_ant_by_tx_info( - void *p_dm_void, - u8 *p_desc, - u8 mac_id -); +void odm_set_tx_ant_by_tx_info( + void *dm_void, + u8 *desc, + u8 mac_id); #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) -struct tx_desc; /*declared tx_desc here or compile error happened when enabled 8822B*/ - -void -odm_set_tx_ant_by_tx_info( - struct rtl8192cd_priv *priv, - struct tx_desc *pdesc, - unsigned short aid -); - -#if 1/*def def CONFIG_WLAN_HAL*/ -void -odm_set_tx_ant_by_tx_info_hal( - struct rtl8192cd_priv *priv, - void *pdesc_data, - u16 aid -); -#endif /*#ifdef CONFIG_WLAN_HAL*/ +struct tx_desc; /*@declared tx_desc here or compile error happened when enabled 8822B*/ + +void odm_set_tx_ant_by_tx_info( + struct rtl8192cd_priv *priv, + struct tx_desc *pdesc, + unsigned short aid); + +#if 1 /*@def def CONFIG_WLAN_HAL*/ +void odm_set_tx_ant_by_tx_info_hal( + struct rtl8192cd_priv *priv, + void *pdesc_data, + u16 aid); +#endif /*@#ifdef CONFIG_WLAN_HAL*/ #endif +void odm_ant_div_config( + void *dm_void); + +void odm_ant_div_timers( + void *dm_void, + u8 state); + +void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void odm_ant_div_reset(void *dm_void); + +void odm_antenna_diversity_init(void *dm_void); -void -odm_ant_div_config( - void *p_dm_void -); - -void -odm_ant_div_timers( - void *p_dm_void, - u8 state -); - -void -phydm_antdiv_debug( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -); - -#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ - -void -odm_ant_div_reset( - void *p_dm_void -); - -void -odm_antenna_diversity_init( - void *p_dm_void -); - -void -odm_antenna_diversity( - void *p_dm_void -); - -#endif /*#ifndef __ODMANTDIV_H__*/ +void odm_antenna_diversity(void *dm_void); +#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/ +#endif /*@#ifndef __ODMANTDIV_H__*/ diff --git a/hal/phydm/phydm_api.c b/hal/phydm/phydm_api.c new file mode 100644 index 0000000..8f23e4f --- /dev/null +++ b/hal/phydm/phydm_api.c @@ -0,0 +1,2410 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + * ************************************************************ + */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (ODM_IC_11AC_SERIES_SUPPORT) +void phydm_reset_bb_hw_cnt_ac(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*@ Reset all counter when 1 (including PMAC and PHY)*/ + /* Reset Page F counter*/ + odm_set_bb_reg(dm, R_0xb58, BIT(0), 1); + odm_set_bb_reg(dm, R_0xb58, BIT(0), 0); +} +#endif + +void phydm_dynamic_ant_weighting(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#ifdef DYN_ANT_WEIGHTING_SUPPORT + #if (RTL8197F_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8197F)) + phydm_dynamic_ant_weighting_8197f(dm); + #endif + + #if (RTL8812A_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8812)) { + phydm_dynamic_ant_weighting_8812a(dm); + } + #endif + + #if (RTL8822B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8822B)) + phydm_dynamic_ant_weighting_8822b(dm); + #endif +#endif +} + +#ifdef DYN_ANT_WEIGHTING_SUPPORT +void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "echo dis_dym_ant_weighting {0/1}\n"); + + } else { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 1) { + dm->is_disable_dym_ant_weighting = 1; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable dyn-ant-weighting\n"); + } else { + dm->is_disable_dym_ant_weighting = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Enable dyn-ant-weighting\n"); + } + } + *_used = used; + *_out_len = out_len; +} +#endif + +void phydm_iq_gen_en(void *dm_void) +{ +#ifdef PHYDM_COMPILE_IC_2SS + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + enum rf_path path = RF_PATH_A; + + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (!(dm->support_ic_type & ODM_IC_11AC_SERIES)) + return; + + for (i = RF_PATH_A; i <= RF_PATH_B; i++) { + path = (enum rf_path)i; + + /*RF mode table write enable*/ + odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x1); + /*Select RX mode*/ + odm_set_rf_reg(dm, path, RF_0x33, 0xF, 3); + /*Set Table data*/ + odm_set_rf_reg(dm, path, RF_0x3e, 0xfffff, 0x00036); + /*Set Table data*/ + odm_set_rf_reg(dm, path, RF_0x3f, 0xfffff, 0x5AFCE); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x0); + } + #endif + #if (ODM_IC_11N_SERIES_SUPPORT) + if (!(dm->support_ic_type & ODM_IC_11N_SERIES)) + return; + if (dm->support_ic_type & ODM_RTL8192F) { + /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1); + /* Path A */ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x08000); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0005f); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x01042); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0004f); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2); + /* Path B */ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00050); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00040); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0); + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0); + } + #endif +#endif +} + +void phydm_dis_cdd(void *dm_void) +{ +#ifdef PHYDM_COMPILE_IC_2SS + struct dm_struct *dm = (struct dm_struct *)dm_void; + + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x808, 0x3ffff00, 0); + odm_set_bb_reg(dm, R_0x9ac, 0x1fff, 0); + odm_set_bb_reg(dm, R_0x9ac, BIT(13), 1); + } + #endif + #if (ODM_IC_11N_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0x90c, 0xffffffff, 0x83321333); + /* Set Tx delay setting for CCK pathA,B*/ + odm_set_bb_reg(dm, R_0xa2c, 0xf0000000, 0); + //Enable Tx CDD for HT-portion when spatial expansion is applied + odm_set_bb_reg(dm, R_0xd00, BIT(8), 0); + /* Tx CDD for Legacy*/ + odm_set_bb_reg(dm, R_0xd04, 0xf0000, 0); + /* Tx CDD for non-HT*/ + odm_set_bb_reg(dm, R_0xd0c, 0x3c0, 0); + /* Tx CDD for HT SS1*/ + odm_set_bb_reg(dm, R_0xd0c, 0xf8000, 0); + } + #endif +#endif +} + +void phydm_pathb_q_matrix_rotate_en(void *dm_void) +{ +#ifdef PHYDM_COMPILE_IC_2SS + struct dm_struct *dm = (struct dm_struct *)dm_void; + + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + phydm_iq_gen_en(dm); + + #ifdef PHYDM_COMMON_API_SUPPORT + if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, true)) + return; + #endif + + phydm_dis_cdd(dm); + /*Set Q matrix r_v11 =1*/ + odm_set_bb_reg(dm, R_0x195c, MASKDWORD, 0x40000); + phydm_pathb_q_matrix_rotate(dm, 0); + /*Set Q matrix enable*/ + odm_set_bb_reg(dm, R_0x191c, BIT(7), 1); + } + #endif + #if (ODM_IC_11N_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + phydm_iq_gen_en(dm); + + #ifdef PHYDM_COMMON_API_SUPPORT + if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, true)) + return; + #endif + phydm_dis_cdd(dm); + phydm_pathb_q_matrix_rotate(dm, 0); + } + #endif +#endif +} + +void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx) +{ +#ifdef PHYDM_COMPILE_IC_2SS + struct dm_struct *dm = (struct dm_struct *)dm_void; + #if (ODM_IC_11AC_SERIES_SUPPORT) + u32 phase_table_0[12] = {0x40000, 0x376CF, 0x20000, 0x00000, + 0xFE0000, 0xFC8930, 0xFC0000, 0xFC8930, + 0xFDFFFF, 0x000000, 0x020000, 0x0376CF}; + u32 phase_table_1[12] = {0x00000, 0x1FFFF, 0x376CF, 0x40000, + 0x0376CF, 0x01FFFF, 0x000000, 0xFDFFFF, + 0xFC8930, 0xFC0000, 0xFC8930, 0xFDFFFF}; + #endif + #if (ODM_IC_11N_SERIES_SUPPORT) + u32 phase_table_N_0[12] = {0x00, 0x0B, 0x02, 0x00, 0x02, 0x02, 0x04, + 0x02, 0x0D, 0x09, 0x04, 0x0B}; + u32 phase_table_N_1[12] = {0x40000100, 0x377F00DD, 0x201D8880, + 0x00000000, 0xE01D8B80, 0xC8BF0322, + 0xC000FF00, 0xC8BF0322, 0xDFE2777F, + 0xFFC003FF, 0x20227480, 0x377F00DD}; + u32 phase_table_N_2[12] = {0x00, 0x1E, 0x3C, 0x4C, 0x3C, 0x1E, 0x0F, + 0xD2, 0xC3, 0xC4, 0xC3, 0xD2}; + #endif + if (idx >= 12) { + PHYDM_DBG(dm, ODM_COMP_API, "Phase Set Error: %d\n", idx); + return; + } + + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /*Set Q matrix r_v21*/ + odm_set_bb_reg(dm, R_0x1954, 0xffffff, phase_table_0[idx]); + odm_set_bb_reg(dm, R_0x1950, 0xffffff, phase_table_1[idx]); + } + #endif + #if (ODM_IC_11N_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + /*Set Q matrix r_v21*/ + odm_set_bb_reg(dm, R_0xc4c, 0xff000000, phase_table_N_0[idx]); + odm_set_bb_reg(dm, R_0xc88, 0xffffffff, phase_table_N_1[idx]); + odm_set_bb_reg(dm, R_0xc9c, 0xff000000, phase_table_N_2[idx]); + } + #endif +#endif +} + +void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rx_ant = 0, tx_ant = 0; + u8 path_bitmap = 1; + + path_bitmap = (u8)phydm_gen_bitmask(num_rf_path); +#if 0 + /*PHYDM_DBG(dm, ODM_COMP_INIT, "path_bitmap=0x%x\n", path_bitmap);*/ +#endif + + dm->tx_ant_status = path_bitmap; + dm->rx_ant_status = path_bitmap; + + if (num_rf_path == PDM_1SS) + return; + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & + (ODM_RTL8192F | ODM_RTL8192E | ODM_RTL8197F)) { + dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0xc04, 0x3); + dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x90c, 0x3); + } else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8814A)) { + dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0x808, 0xf); + dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x80c, 0xf); + } + #endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "[%s]ant_status{tx,rx}={0x%x, 0x%x}\n", + __func__, dm->tx_ant_status, dm->rx_ant_status); +} + +void phydm_config_ofdm_tx_path(void *dm_void, u32 path) +{ +#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ofdm_tx_path = 0x33; + + if (dm->num_rf_path == PDM_1SS) + return; + + switch (dm->support_ic_type) { + #if (RTL8192E_SUPPORT) + case ODM_RTL8192E: + if (path == BB_PATH_A) + odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121111); + else if (path == BB_PATH_B) + odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x82221222); + else if (path == BB_PATH_AB) + odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333); + + break; + #endif + + #if (RTL8812A_SUPPORT) + case ODM_RTL8812: + if (path == BB_PATH_A) + ofdm_tx_path = 0x11; + else if (path == BB_PATH_B) + ofdm_tx_path = 0x22; + else if (path == BB_PATH_AB) + ofdm_tx_path = 0x33; + + odm_set_bb_reg(dm, R_0x80c, 0xff00, ofdm_tx_path); + + break; + #endif + + default: + break; + } +#endif +} + +void phydm_config_ofdm_rx_path(void *dm_void, u32 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 val = 0; + + if (dm->support_ic_type & (ODM_RTL8192E)) { +#if (RTL8192E_SUPPORT) + if (path == BB_PATH_A) + val = 1; + else if (path == BB_PATH_B) + val = 2; + else if (path == BB_PATH_AB) + val = 3; + + odm_set_bb_reg(dm, R_0xc04, 0xff, ((val << 4) | val)); + odm_set_bb_reg(dm, R_0xd04, 0xf, val); +#endif + } +#if (RTL8812A_SUPPORT || RTL8822B_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) { + if (path == BB_PATH_A) + val = 1; + else if (path == BB_PATH_B) + val = 2; + else if (path == BB_PATH_AB) + val = 3; + + odm_set_bb_reg(dm, R_0x808, MASKBYTE0, ((val << 4) | val)); + } +#endif +} + +void phydm_config_cck_rx_antenna_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & ODM_IC_1SS) + return; + + /*@CCK 2R CCA parameters*/ + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0x0); /*@Disable Ant diversity*/ + odm_set_bb_reg(dm, R_0xa70, BIT(7), 0); /*@Concurrent CCA at LSB & USB*/ + odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); /*RX path diversity enable*/ + odm_set_bb_reg(dm, R_0xa14, BIT(7), 0); /*r_en_mrc_antsel*/ + odm_set_bb_reg(dm, R_0xa20, (BIT(5) | BIT(4)), 1); /*@MBC weighting*/ + + if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, R_0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/ + else if (dm->support_ic_type & ODM_RTL8814A) + odm_set_bb_reg(dm, R_0xa84, BIT(28), 1); /*@2R CCA only*/ +#endif +} + +void phydm_config_cck_rx_path(void *dm_void, enum bb_path path) +{ +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 path_div_select = 0; + u8 cck_path[2] = {0}; + u8 en_2R_path = 0; + u8 en_2R_mrc = 0; + u8 i = 0, j = 0; + u8 num_enable_path = 0; + u8 cck_mrc_max_path = 2; + + if (dm->support_ic_type & ODM_IC_1SS) + return; + + for (i = 0; i < 4; i++) { + if (path & BIT(i)) { /*@ex: PHYDM_ABCD*/ + num_enable_path++; + cck_path[j] = i; + j++; + } + if (num_enable_path >= cck_mrc_max_path) + break; + } + + if (num_enable_path > 1) { + path_div_select = 1; + en_2R_path = 1; + en_2R_mrc = 1; + } else { + path_div_select = 0; + en_2R_path = 0; + en_2R_mrc = 0; + } + /*@CCK_1 input signal path*/ + odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), cck_path[0]); + /*@CCK_2 input signal path*/ + odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), cck_path[1]); + /*@enable Rx path diversity*/ + odm_set_bb_reg(dm, R_0xa74, BIT(8), path_div_select); + /*@enable 2R Rx path*/ + odm_set_bb_reg(dm, R_0xa2c, BIT(18), en_2R_path); + /*@enable 2R MRC*/ + odm_set_bb_reg(dm, R_0xa2c, BIT(22), en_2R_mrc); + if (dm->support_ic_type & ODM_RTL8192F) { + if (path == BB_PATH_A) { + odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0); + odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0); + odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); + odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0); + odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0); + } else if (path == BB_PATH_B) {/*@for DC cancellation*/ + odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1); + odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1); + odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); + odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0); + odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0); + } else if (path == BB_PATH_AB) { + odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0); + odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1); + odm_set_bb_reg(dm, R_0xa74, BIT(8), 1); + odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 1); + odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 1); + } + } + +#endif +} + +void phydm_config_cck_tx_path(void *dm_void, enum bb_path path) +{ +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (path == BB_PATH_A) + odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8); + else if (path == BB_PATH_B) + odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4); + else if (path == BB_PATH_AB) + odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc); +#endif +} + +void phydm_config_trx_path_v2(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + char help[] = "-h"; + u8 i = 0, input_idx = 0; + enum bb_path tx_path, rx_path; + boolean dbg_mode_en, tx2_path_en; + + if (!(dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F))) + return; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + dbg_mode_en = (boolean)val[0]; + tx_path = (enum bb_path)val[1]; + rx_path = (enum bb_path)val[2]; + tx2_path_en = (boolean)val[3]; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en} {tx_path} {rx_path} {1ss_tx_2_path_en}\n"); + + } else if (dbg_mode_en) { + dm->is_disable_phy_api = false; + phydm_api_trx_mode(dm, tx_path, rx_path, tx2_path_en); + dm->is_disable_phy_api = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "tx_path = 0x%x, rx_path = 0x%x, tx2_path_en = %d\n", + tx_path, rx_path, tx2_path_en); + } else { + dm->is_disable_phy_api = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable API debug mode\n"); + } +#endif +} + +void phydm_config_trx_path_v1(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + char help[] = "-h"; + u8 i = 0, input_idx = 0; + + if (!(dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812))) + return; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0:CCK, 1:OFDM} {1:TX, 2:RX} {1:path_A, 2:path_B, 3:path_AB}\n"); + + *_used = used; + *_out_len = out_len; + return; + + } else if (val[0] == 0) { + /* @CCK */ + if (val[1] == 1) { /*TX*/ + if (val[2] == 1) + phydm_config_cck_tx_path(dm, BB_PATH_A); + else if (val[2] == 2) + phydm_config_cck_tx_path(dm, BB_PATH_B); + else if (val[2] == 3) + phydm_config_cck_tx_path(dm, BB_PATH_AB); + } else if (val[1] == 2) { /*RX*/ + + phydm_config_cck_rx_antenna_init(dm); + + if (val[2] == 1) + phydm_config_cck_rx_path(dm, BB_PATH_A); + else if (val[2] == 2) + phydm_config_cck_rx_path(dm, BB_PATH_B); + else if (val[2] == 3) + phydm_config_cck_rx_path(dm, BB_PATH_AB); + } + } + /* OFDM */ + else if (val[0] == 1) { + if (val[1] == 1) /*TX*/ + phydm_config_ofdm_tx_path(dm, val[2]); + else if (val[1] == 2) /*RX*/ + phydm_config_ofdm_rx_path(dm, val[2]); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n", + (val[0] == 1) ? "OFDM" : "CCK", + (val[1] == 1) ? "TX" : "RX", + (val[2] & 0x1) ? "A" : "", (val[2] & 0x2) ? "B" : "", + (val[2] & 0x4) ? "C" : "", + (val[2] & 0x8) ? "D" : ""); + + *_used = used; + *_out_len = out_len; +#endif +} + +void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) { + #if (RTL8192E_SUPPORT || RTL8812A_SUPPORT) + phydm_config_trx_path_v1(dm, input, _used, output, _out_len); + #endif + } else if (dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) { + #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + phydm_config_trx_path_v2(dm, input, _used, output, _out_len); + #endif + } +} + +void phydm_tx_2path(void *dm_void) +{ +#if (defined(PHYDM_COMPILE_IC_2SS)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum bb_path rx_path = (enum bb_path)dm->rx_ant_status; + + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__); + + + if (!(dm->support_ic_type & ODM_IC_2SS)) + return; + + #if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8197F_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) + phydm_api_trx_mode(dm, BB_PATH_AB, rx_path, true); + #endif + + #if (RTL8812A_SUPPORT || RTL8192E_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) { + phydm_config_cck_tx_path(dm, BB_PATH_AB); + phydm_config_ofdm_tx_path(dm, BB_PATH_AB); + } + #endif +#endif +} + +void phydm_stop_3_wire(void *dm_void, u8 set_type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (set_type == PHYDM_SET) { + /*@[Stop 3-wires]*/ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0xc00, 0xf, 0x4); + odm_set_bb_reg(dm, R_0xe00, 0xf, 0x4); + } else { + odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0xf); + } + + } else { /*@if (set_type == PHYDM_REVERT)*/ + + /*@[Start 3-wires]*/ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0xc00, 0xf, 0x7); + odm_set_bb_reg(dm, R_0xe00, 0xf, 0x7); + } else { + odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0x0); + } + } +} + +u8 phydm_stop_ic_trx(void *dm_void, u8 set_type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_api_stuc *api = &dm->api_table; + u32 i; + u8 trx_idle_success = false; + u32 dbg_port_value = 0; + + if (set_type == PHYDM_SET) { + /*@[Stop TRX]---------------------------------------------------------*/ + /*set debug port to 0x0*/ + if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0)) + return PHYDM_SET_FAIL; + + for (i = 0; i < 10000; i++) { + dbg_port_value = phydm_get_bb_dbg_port_val(dm); + /* PHYTXON && CCA_all */ + if ((dbg_port_value & (BIT(17) | BIT(3))) == 0) { + PHYDM_DBG(dm, ODM_COMP_API, + "Stop trx wait for (%d) times\n", i); + + trx_idle_success = true; + break; + } + } + phydm_release_bb_dbg_port(dm); + + if (trx_idle_success) { + api->tx_queue_bitmap = odm_read_1byte(dm, R_0x522); + + /*pause all TX queue*/ + odm_set_bb_reg(dm, R_0x520, 0xff0000, 0xff); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /*@disable CCK block*/ + odm_set_bb_reg(dm, R_0x808, BIT(28), 0); + /*@disable OFDM RX CCA*/ + odm_set_bb_reg(dm, R_0x838, BIT(1), 1); + } else { + /* @disable whole CCK block */ + odm_set_bb_reg(dm, R_0x800, BIT(24), 0); + + api->rxiqc_reg1 = odm_read_4byte(dm, R_0xc14); + api->rxiqc_reg2 = odm_read_4byte(dm, R_0xc1c); + /* @[ Set IQK Matrix = 0 ] + * equivalent to [ Turn off CCA] + */ + odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0); + odm_set_bb_reg(dm, R_0xc1c, MASKDWORD, 0x0); + } + + } else { + return PHYDM_SET_FAIL; + } + + return PHYDM_SET_SUCCESS; + + } else { /*@if (set_type == PHYDM_REVERT)*/ + /*Release all TX queue*/ + odm_write_1byte(dm, R_0x522, api->tx_queue_bitmap); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /*@enable CCK block*/ + odm_set_bb_reg(dm, R_0x808, BIT(28), 1); + /*@enable OFDM RX CCA*/ + odm_set_bb_reg(dm, R_0x838, BIT(1), 0); + } else { + /* @enable whole CCK block */ + odm_set_bb_reg(dm, R_0x800, BIT(24), 1); + /* @[Set IQK Matrix = 0] equivalent to [ Turn off CCA]*/ + odm_write_4byte(dm, R_0xc14, api->rxiqc_reg1); + odm_write_4byte(dm, R_0xc1c, api->rxiqc_reg2); + } + + return PHYDM_SET_SUCCESS; + } +} + +void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch) +{ +#if (RTL8821A_SUPPORT || RTL8881A_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A))) + return; + + /*Output Pin Settings*/ + + /*select DPDT_P and DPDT_N as output pin*/ + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); + + /*@by WLAN control*/ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); + + /*@DPDT_N = 1b'0*/ /*@DPDT_P = 1b'0*/ + odm_set_bb_reg(dm, R_0xcb4, 0xFF, 77); + + if (ext_ant_switch == 1) { /*@2b'01*/ + odm_set_bb_reg(dm, R_0xcb4, (BIT(29) | BIT(28)), 1); + PHYDM_DBG(dm, ODM_COMP_API, "8821A ant swh=2b'01\n"); + } else if (ext_ant_switch == 2) { /*@2b'10*/ + odm_set_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28), 2); + PHYDM_DBG(dm, ODM_COMP_API, "*8821A ant swh=2b'10\n"); + } +#endif +} + +void phydm_csi_mask_enable(void *dm_void, u32 enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean en = false; + + en = (enable == FUNC_ENABLE) ? true : false; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0xd2c, BIT(28), en); + PHYDM_DBG(dm, ODM_COMP_API, + "Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", en); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if (en) + odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3); + + odm_set_bb_reg(dm, R_0xc0c, BIT(3), en); + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x874, BIT(0), en); + PHYDM_DBG(dm, ODM_COMP_API, + "Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", en); + } +} + +void phydm_clean_all_csi_mask(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0xd40, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0xd44, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0xd48, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0xd4c, MASKDWORD, 0); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + u8 i = 0, idx_lmt = 0; + + if (dm->support_ic_type & ODM_RTL8822C) + idx_lmt = 127; + else/*@for IC supporting 80 + 80*/ + idx_lmt = 255; + + odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1); + for (i = 0; i < idx_lmt; i++) { + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, i); + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE0, 0x0); + } + odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0); + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x880, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x884, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x888, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x88c, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x890, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x894, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x898, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x89c, MASKDWORD, 0); + } +} + +void phydm_set_csi_mask(void *dm_void, u32 tone_idx_tmp, u8 tone_direction) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 byte_offset = 0, bit_offset = 0; + u32 target_reg = 0; + u8 reg_tmp_value = 0; + u32 tone_num = 64; + u32 tone_num_shift = 0; + u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0; + + /* @calculate real tone idx*/ + if ((tone_idx_tmp % 10) >= 5) + tone_idx_tmp += 10; + + tone_idx_tmp = (tone_idx_tmp / 10); + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + tone_num = 64; + csi_mask_reg_p = 0xD40; + csi_mask_reg_n = 0xD48; + + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + tone_num = 128; + csi_mask_reg_p = 0x880; + csi_mask_reg_n = 0x890; + } + + if (tone_direction == FREQ_POSITIVE) { + if (tone_idx_tmp >= (tone_num - 1)) + tone_idx_tmp = (tone_num - 1); + + byte_offset = (u8)(tone_idx_tmp >> 3); + bit_offset = (u8)(tone_idx_tmp & 0x7); + target_reg = csi_mask_reg_p + byte_offset; + + } else { + tone_num_shift = tone_num; + + if (tone_idx_tmp >= tone_num) + tone_idx_tmp = tone_num; + + tone_idx_tmp = tone_num - tone_idx_tmp; + + byte_offset = (u8)(tone_idx_tmp >> 3); + bit_offset = (u8)(tone_idx_tmp & 0x7); + target_reg = csi_mask_reg_n + byte_offset; + } + + reg_tmp_value = odm_read_1byte(dm, target_reg); + PHYDM_DBG(dm, ODM_COMP_API, + "Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", + (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value); + reg_tmp_value |= BIT(bit_offset); + odm_write_1byte(dm, target_reg, reg_tmp_value); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", + (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value); +} + +void phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + /*tone_idx X 10*/ + u32 nbi_128[NBI_128TONE] = {25, 55, 85, 115, 135, + 155, 185, 205, 225, 245, + 265, 285, 305, 335, 355, + 375, 395, 415, 435, 455, + 485, 505, 525, 555, 585, 615, 635}; + /*tone_idx X 10*/ + u32 nbi_256[NBI_256TONE] = {25, 55, 85, 115, 135, + 155, 175, 195, 225, 245, + 265, 285, 305, 325, 345, + 365, 385, 405, 425, 445, + 465, 485, 505, 525, 545, + 565, 585, 605, 625, 645, + 665, 695, 715, 735, 755, + 775, 795, 815, 835, 855, + 875, 895, 915, 935, 955, + 975, 995, 1015, 1035, 1055, + 1085, 1105, 1125, 1145, 1175, + 1195, 1225, 1255, 1275}; + u32 reg_idx = 0; + u32 i; + u8 nbi_table_idx = FFT_128_TYPE; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + nbi_table_idx = FFT_128_TYPE; + } else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) { + nbi_table_idx = FFT_256_TYPE; + } else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) { + if (bw == 80) + nbi_table_idx = FFT_256_TYPE; + else /*@20M, 40M*/ + nbi_table_idx = FFT_128_TYPE; + } + + if (nbi_table_idx == FFT_128_TYPE) { + for (i = 0; i < NBI_128TONE; i++) { + if (tone_idx_tmp < nbi_128[i]) { + reg_idx = i + 1; + break; + } + } + + } else if (nbi_table_idx == FFT_256_TYPE) { + for (i = 0; i < NBI_256TONE; i++) { + if (tone_idx_tmp < nbi_256[i]) { + reg_idx = i + 1; + break; + } + } + } + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0xc40, 0x1f000000, reg_idx); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", + reg_idx); + } else { + odm_set_bb_reg(dm, R_0x87c, 0xfc000, reg_idx); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", + reg_idx); + } +} + +void phydm_nbi_enable(void *dm_void, u32 enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = 0; + + val = (enable == FUNC_ENABLE) ? 1 : 0; + + PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val); + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) { + val = (enable == FUNC_ENABLE) ? 0xf : 0; + odm_set_bb_reg(dm, R_0xc50, 0xf000000, val); + } else { + odm_set_bb_reg(dm, R_0xc40, BIT(9), val); + } + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + odm_set_bb_reg(dm, R_0x87c, BIT(13), val); + odm_set_bb_reg(dm, R_0xc20, BIT(28), val); + if (dm->rf_type > RF_1T1R) + odm_set_bb_reg(dm, R_0xe20, BIT(28), val); + } else { + odm_set_bb_reg(dm, R_0x87c, BIT(13), val); + } + } +} + +u8 phydm_find_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch, u32 *fc_in) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = *fc_in; + u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, + 108, 116, 124, 132, 140, + 149, 157, 165, 173}; + u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, + 149, 165}; + u32 *start_ch = &start_ch_per_40m[0]; + u32 num_start_channel = NUM_START_CH_40M; + u32 channel_offset = 0; + u32 i; + + /*@2.4G*/ + if (channel <= 14 && channel > 0) { + if (bw == 80) + return PHYDM_SET_FAIL; + + fc = 2412 + (channel - 1) * 5; + + if (bw == 40 && second_ch == PHYDM_ABOVE) { + if (channel >= 10) { + PHYDM_DBG(dm, ODM_COMP_API, + "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", + channel, second_ch); + return PHYDM_SET_FAIL; + } + fc += 10; + } else if (bw == 40 && (second_ch == PHYDM_BELOW)) { + if (channel <= 2) { + PHYDM_DBG(dm, ODM_COMP_API, + "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", + channel, second_ch); + return PHYDM_SET_FAIL; + } + fc -= 10; + } + } + /*@5G*/ + else if (channel >= 36 && channel <= 177) { + if (bw != 20) { + if (bw == 40) { + num_start_channel = NUM_START_CH_40M; + start_ch = &start_ch_per_40m[0]; + channel_offset = CH_OFFSET_40M; + } else if (bw == 80) { + num_start_channel = NUM_START_CH_80M; + start_ch = &start_ch_per_80m[0]; + channel_offset = CH_OFFSET_80M; + } + + for (i = 0; i < (num_start_channel - 1); i++) { + if (channel < start_ch[i + 1]) { + channel = start_ch[i] + channel_offset; + break; + } + } + PHYDM_DBG(dm, ODM_COMP_API, "Mod_CH = ((%d))\n", + channel); + } + + fc = 5180 + (channel - 36) * 5; + + } else { + PHYDM_DBG(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n", + channel); + return PHYDM_SET_FAIL; + } + + *fc_in = fc; + + return PHYDM_SET_SUCCESS; +} + +u8 phydm_find_intf_distance(void *dm_void, u32 bw, u32 fc, u32 f_interference, + u32 *tone_idx_tmp_in) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 bw_up = 0, bw_low = 0; + u32 int_distance = 0; + u32 tone_idx_tmp = 0; + u8 set_result = PHYDM_SET_NO_NEED; + + bw_up = fc + bw / 2; + bw_low = fc - bw / 2; + + PHYDM_DBG(dm, ODM_COMP_API, + "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, + fc, bw_up, f_interference); + + if (f_interference >= bw_low && f_interference <= bw_up) { + int_distance = DIFF_2(fc, f_interference); + /*@10*(int_distance /0.3125)*/ + tone_idx_tmp = (int_distance << 5); + PHYDM_DBG(dm, ODM_COMP_API, + "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", + int_distance, tone_idx_tmp / 10, + tone_idx_tmp % 10); + *tone_idx_tmp_in = tone_idx_tmp; + set_result = PHYDM_SET_SUCCESS; + } + + return set_result; +} + +u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, + u32 f_intf, u32 sec_ch) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = 2412; + u8 direction = FREQ_POSITIVE; + u32 tone_idx = 0; + u8 set_result = PHYDM_SET_SUCCESS; + u8 rpt = 0; + + if (enable == FUNC_DISABLE) { + set_result = PHYDM_SET_SUCCESS; + phydm_clean_all_csi_mask(dm); + + } else { + PHYDM_DBG(dm, ODM_COMP_API, + "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + ch, bw, f_intf, + (((bw == 20) || (ch > 14)) ? "Don't care" : + (sec_ch == PHYDM_ABOVE) ? "H" : "L")); + + /*@calculate fc*/ + if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) { + set_result = PHYDM_SET_FAIL; + } else { + /*@calculate interference distance*/ + rpt = phydm_find_intf_distance(dm, bw, fc, f_intf, + &tone_idx); + if (rpt == PHYDM_SET_SUCCESS) { + if (f_intf >= fc) + direction = FREQ_POSITIVE; + else + direction = FREQ_NEGATIVE; + + phydm_set_csi_mask(dm, tone_idx, direction); + set_result = PHYDM_SET_SUCCESS; + } else { + set_result = PHYDM_SET_NO_NEED; + } + } + } + + if (set_result == PHYDM_SET_SUCCESS) + phydm_csi_mask_enable(dm, enable); + else + phydm_csi_mask_enable(dm, FUNC_DISABLE); + + return set_result; +} + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, + u32 f_intf, u32 sec_ch, u8 wgt) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = 2412; + u8 direction = FREQ_POSITIVE; + u32 tone_idx = 0; + u8 set_result = PHYDM_SET_SUCCESS; + u8 rpt = 0; + + if (enable == FUNC_DISABLE) { + phydm_csi_mask_enable(dm, FUNC_ENABLE); + phydm_clean_all_csi_mask(dm); + phydm_csi_mask_enable(dm, FUNC_DISABLE); + set_result = PHYDM_SET_SUCCESS; + } else { + PHYDM_DBG(dm, ODM_COMP_API, + "[Set CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s)), wgt = ((%d))\n", + ch, bw, f_intf, + (((bw == 20) || (ch > 14)) ? "Don't care" : + (sec_ch == PHYDM_ABOVE) ? "H" : "L"), wgt); + + /*@calculate fc*/ + if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) { + set_result = PHYDM_SET_FAIL; + } else { + /*@calculate interference distance*/ + rpt = phydm_find_intf_distance(dm, bw, fc, f_intf, + &tone_idx); + if (rpt == PHYDM_SET_SUCCESS) { + if (f_intf >= fc) + direction = FREQ_POSITIVE; + else + direction = FREQ_NEGATIVE; + + phydm_csi_mask_enable(dm, FUNC_ENABLE); + phydm_set_csi_mask_jgr3(dm, tone_idx, direction, + wgt); + set_result = PHYDM_SET_SUCCESS; + } else { + set_result = PHYDM_SET_NO_NEED; + } + } + if (!(set_result == PHYDM_SET_SUCCESS)) + phydm_csi_mask_enable(dm, FUNC_DISABLE); + } + + return set_result; +} + +void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction, + u8 wgt) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_tmp_value = 0; + u32 tone_num = 64; + u32 tone_num_shift = 0; + u32 table_addr = 0; + u32 addr = 0; + u8 rf_bw = 0; + + /* @calculate real tone idx*/ + if ((tone_idx_tmp % 10) >= 5) + tone_idx_tmp += 10; + + tone_idx_tmp = (tone_idx_tmp / 10); + + rf_bw = odm_read_1byte(dm, R_0x9b0); + if (((rf_bw & 0xc) >> 2) == 0x2) + tone_num = 128; /* RF80 : tone-1 at tone_idx=255 */ + else + tone_num = 64; /* RF20/40 : tone-1 at tone_idx=127 */ + + if (tone_direction == FREQ_POSITIVE) { + if (tone_idx_tmp >= (tone_num - 1)) + tone_idx_tmp = (tone_num - 1); + } else { + tone_num_shift = tone_num; + if (tone_idx_tmp >= tone_num) + tone_idx_tmp = tone_num; + + tone_idx_tmp = (tone_num << 1) - tone_idx_tmp; + } + table_addr = tone_idx_tmp >> 1; + + reg_tmp_value = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "Pre Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n", + (tone_idx_tmp + tone_num_shift), reg_tmp_value); + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, (table_addr & 0xff)); + if (tone_idx_tmp % 2) + addr = 0xf; + else + addr = 0xf0; + + odm_set_bb_reg(dm, R_0x1d94, addr, (BIT(3) | (wgt & 0x7))); + reg_tmp_value = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n", + (tone_idx_tmp + tone_num_shift), reg_tmp_value); + odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0); +} + +u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, + u32 sec_ch, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = 2412; + u8 direction = FREQ_POSITIVE; + u32 tone_idx = 0; + u8 set_result = PHYDM_SET_SUCCESS; + u8 rpt = 0; + + if (enable == FUNC_DISABLE) { + set_result = PHYDM_SET_SUCCESS; + } else { + PHYDM_DBG(dm, ODM_COMP_API, + "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + ch, bw, f_intf, + (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) || + (ch > 14)) ? "Don't care" : + (sec_ch == PHYDM_ABOVE) ? "H" : "L")); + + /*@calculate fc*/ + if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) { + set_result = PHYDM_SET_FAIL; + } else { + /*@calculate interference distance*/ + rpt = phydm_find_intf_distance(dm, bw, fc, f_intf, + &tone_idx); + if (rpt == PHYDM_SET_SUCCESS) { + if (f_intf >= fc) + direction = FREQ_POSITIVE; + else + direction = FREQ_NEGATIVE; + + phydm_set_nbi_reg_jgr3(dm, tone_idx, direction, + path); + set_result = PHYDM_SET_SUCCESS; + } else { + set_result = PHYDM_SET_NO_NEED; + } + } + } + + if (set_result == PHYDM_SET_SUCCESS) + phydm_nbi_enable_jgr3(dm, enable, path); + else + phydm_nbi_enable_jgr3(dm, FUNC_DISABLE, path); + + return set_result; +} + +void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction, + u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_tmp_value = 0; + u32 tone_num = 64; + u32 tone_num_shift = 0; + u32 addr = 0; + u8 rf_bw = 0; + + /* @calculate real tone idx*/ + if ((tone_idx_tmp % 10) >= 5) + tone_idx_tmp += 10; + + tone_idx_tmp = (tone_idx_tmp / 10); + + rf_bw = odm_read_1byte(dm, R_0x9b0); + if (((rf_bw & 0xc) >> 2) == 0x2) + tone_num = 128; /* RF80 : tone-1 at tone_idx=255 */ + else + tone_num = 64; /* RF20/40 : tone-1 at tone_idx=127 */ + + if (tone_direction == FREQ_POSITIVE) { + if (tone_idx_tmp >= (tone_num - 1)) + tone_idx_tmp = (tone_num - 1); + } else { + tone_num_shift = tone_num; + if (tone_idx_tmp >= tone_num) + tone_idx_tmp = tone_num; + + tone_idx_tmp = (tone_num << 1) - tone_idx_tmp; + } + + switch (path) { + case RF_PATH_A: + odm_set_bb_reg(dm, R_0x1944, 0x001FF000, tone_idx_tmp); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx[%d]:PATH-A = ((0x%x))\n", + (tone_idx_tmp + tone_num_shift), tone_idx_tmp); + break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case RF_PATH_B: + odm_set_bb_reg(dm, R_0x4044, 0x001FF000, tone_idx_tmp); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx[%d]:PATH-B = ((0x%x))\n", + (tone_idx_tmp + tone_num_shift), tone_idx_tmp); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case RF_PATH_C: + odm_set_bb_reg(dm, R_0x5044, 0x001FF000, tone_idx_tmp); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx[%d]:PATH-C = ((0x%x))\n", + (tone_idx_tmp + tone_num_shift), tone_idx_tmp); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case RF_PATH_D: + odm_set_bb_reg(dm, R_0x5144, 0x001FF000, tone_idx_tmp); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx[%d]:PATH-D = ((0x%x))\n", + (tone_idx_tmp + tone_num_shift), tone_idx_tmp); + break; + #endif + default: + break; + } +} + +void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = 0; + + val = (enable == FUNC_ENABLE) ? 1 : 0; + + PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val); + + odm_set_bb_reg(dm, R_0x818, BIT(11), val); + if (enable == FUNC_ENABLE) { + switch (path) { + case RF_PATH_A: + odm_set_bb_reg(dm, R_0x1940, BIT(31), val); + break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case RF_PATH_B: + odm_set_bb_reg(dm, R_0x4040, BIT(31), val); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case RF_PATH_C: + odm_set_bb_reg(dm, R_0x5040, BIT(31), val); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case RF_PATH_D: + odm_set_bb_reg(dm, R_0x5140, BIT(31), val); + break; + #endif + default: + break; + } + } else { + odm_set_bb_reg(dm, R_0x1940, BIT(31), val); + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + odm_set_bb_reg(dm, R_0x4040, BIT(31), val); + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + odm_set_bb_reg(dm, R_0x5040, BIT(31), val); + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + odm_set_bb_reg(dm, R_0x5140, BIT(31), val); + #endif + } +} + +#endif +u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, + u32 sec_ch) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = 2412; + u8 direction = FREQ_POSITIVE; + u32 tone_idx = 0; + u8 set_result = PHYDM_SET_SUCCESS; + u8 rpt = 0; + + if (enable == FUNC_DISABLE) { + set_result = PHYDM_SET_SUCCESS; + } else { + PHYDM_DBG(dm, ODM_COMP_API, + "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + ch, bw, f_intf, + (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) || + (ch > 14)) ? "Don't care" : + (sec_ch == PHYDM_ABOVE) ? "H" : "L")); + + /*@calculate fc*/ + if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) { + set_result = PHYDM_SET_FAIL; + } else { + /*@calculate interference distance*/ + rpt = phydm_find_intf_distance(dm, bw, fc, f_intf, + &tone_idx); + if (rpt == PHYDM_SET_SUCCESS) { + if (f_intf >= fc) + direction = FREQ_POSITIVE; + else + direction = FREQ_NEGATIVE; + + phydm_set_nbi_reg(dm, tone_idx, bw); + + set_result = PHYDM_SET_SUCCESS; + } else { + set_result = PHYDM_SET_NO_NEED; + } + } + } + + if (set_result == PHYDM_SET_SUCCESS) + phydm_nbi_enable(dm, enable); + else + phydm_nbi_enable(dm, FUNC_DISABLE); + + return set_result; +} + +void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + char help[] = "-h"; + u8 i = 0, input_idx = 0, idx_lmt = 0; + u32 enable = 0; /*@function enable*/ + u32 ch = 0; + u32 bw = 0; + u32 f_int = 0; /*@interference frequency*/ + u32 sec_ch = 0; /*secondary channel*/ + u8 rpt = 0; + u8 path = 0; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + idx_lmt = 6; + else + idx_lmt = 5; + for (i = 0; i < idx_lmt; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + enable = val[0]; + ch = val[1]; + bw = val[2]; + f_int = val[3]; + sec_ch = val[4]; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + path = (u8)val[5]; + #endif + + if ((strcmp(input[1], help) == 0)) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en:1 Dis all path:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)} {Path:A~D(0~3)}\n"); + else + #endif + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n"); + *_used = used; + *_out_len = out_len; + return; + } else if (val[0] == FUNC_ENABLE) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + ch, bw, f_int, + ((sec_ch == PHYDM_DONT_CARE) || + (bw == 20) || (ch > 14)) ? "Don't care" : + ((sec_ch == PHYDM_ABOVE) ? "H" : "L")); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int, + sec_ch, path); + else + #endif + rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int, + sec_ch); + } else if (val[0] == FUNC_DISABLE) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Disable NBI]\n"); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int, + sec_ch, path); + else + #endif + rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int, + sec_ch); + } else { + rpt = PHYDM_SET_FAIL; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "[NBI set result: %s]\n", + (rpt == PHYDM_SET_SUCCESS) ? "Success" : + ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error")); + + *_used = used; + *_out_len = out_len; +} + +void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + char help[] = "-h"; + u8 i = 0, input_idx = 0, idx_lmt = 0; + u32 enable = 0; /*@function enable*/ + u32 ch = 0; + u32 bw = 0; + u32 f_int = 0; /*@interference frequency*/ + u32 sec_ch = 0; /*secondary channel*/ + u8 rpt = 0; + u8 wgt = 0; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + idx_lmt = 6; + else + idx_lmt = 5; + + for (i = 0; i < idx_lmt; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + enable = val[0]; + ch = val[1]; + bw = val[2]; + f_int = val[3]; + sec_ch = val[4]; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + wgt = (u8)val[5]; + #endif + + if ((strcmp(input[1], help) == 0)) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n{wgt:7:3/4,6:2/1,5:1/4,4:1/8,3:1/16,2:1/32,1:1/64,0:0}\n"); + else + #endif + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n"); + + *_used = used; + *_out_len = out_len; + return; + + } else if (val[0] == FUNC_ENABLE) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + ch, bw, f_int, + (ch > 14) ? "Don't care" : + (((sec_ch == PHYDM_DONT_CARE) || + (bw == 20) || (ch > 14)) ? "H" : "L")); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw, + f_int, sec_ch, wgt); + else + #endif + rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int, + sec_ch); + } else if (val[0] == FUNC_DISABLE) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Disable CSI MASK]\n"); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw, + f_int, sec_ch, wgt); + else + #endif + rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int, + sec_ch); + } else { + rpt = PHYDM_SET_FAIL; + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "[CSI MASK set result: %s]\n", + (rpt == PHYDM_SET_SUCCESS) ? "Success" : + ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error")); + + *_used = used; + *_out_len = out_len; +} + +void phydm_stop_ck320(void *dm_void, u8 enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = enable ? 1 : 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x8b4, BIT(6), val); + } else { + if (dm->support_ic_type & ODM_IC_N_2SS) /*N-2SS*/ + odm_set_bb_reg(dm, R_0x87c, BIT(29), val); + else /*N-1SS*/ + odm_set_bb_reg(dm, R_0x87c, BIT(31), val); + } +} + +boolean +phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, /*@(unit: dB)*/ + u8 add_half_db /*@(+0.5 dB)*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + s8 power_idx = power_offset * 2; + boolean set_success = false; + + PHYDM_DBG(dm, ODM_COMP_API, "power_offset=%d, add_half_db =%d\n", + power_offset, add_half_db); + + #if ODM_IC_11AC_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (power_offset > -16 || power_offset < 15) { + if (add_half_db) + power_idx += 1; + + power_idx &= 0x3f; + + PHYDM_DBG(dm, ODM_COMP_API, "Reg_idx =0x%x\n", + power_idx); + odm_set_bb_reg(dm, R_0x8b4, 0x3f, power_idx); + set_success = true; + } else { + pr_debug("[Warning] TX AGC Offset Setting error!"); + } + } + #endif + + #if ODM_IC_11N_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (power_offset > -8 || power_offset < 7) { + if (add_half_db) + power_idx += 1; + + power_idx &= 0x1f; + + PHYDM_DBG(dm, ODM_COMP_API, "Reg_idx =0x%x\n", + power_idx); + /*r_txagc_offset_a*/ + odm_set_bb_reg(dm, R_0x80c, 0x1f00, power_idx); + /*r_txagc_offset_b*/ + odm_set_bb_reg(dm, R_0x80c, 0x3e000, power_idx); + set_success = true; + } else { + pr_debug("[Warning] TX AGC Offset Setting error!"); + } + } + #endif + + return set_success; +} + +#ifdef PHYDM_COMMON_API_SUPPORT +boolean +phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path, + boolean is_positive) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; + u32 txagc_cck = 0; + u32 txagc_ofdm = 0; + u32 r_txagc_ofdm[4] = {0x18e8, 0x41e8, 0x52e8, 0x53e8}; + u32 r_txagc_cck[4] = {0x18a0, 0x41a0, 0x52a0, 0x53a0}; + + #if (RTL8822C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822C) { + if (path > RF_PATH_B) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n", + path); + return false; + } + txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path], + 0x7F0000); + txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path], + 0x1FC00); + if (is_positive) { + if (((txagc_cck + pwr_offset) > 127) || + ((txagc_ofdm + pwr_offset) > 127)) + return false; + + txagc_cck += pwr_offset; + txagc_ofdm += pwr_offset; + } else { + if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm) + return false; + + txagc_cck -= pwr_offset; + txagc_ofdm -= pwr_offset; + } + + ret = config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_cck, + path, PDM_CCK); + ret &= config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_ofdm, + path, PDM_OFDM); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n", + __func__, path, txagc_cck, txagc_ofdm); + } + #endif + + return ret; +} + +boolean +phydm_api_set_txagc(void *dm_void, u32 pwr_idx, enum rf_path path, + u8 rate, boolean is_single_rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; + #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT) + u8 base = 0; + u8 txagc_tmp = 0; + s8 pw_by_rate_tmp = 0; + s8 pw_by_rate_new = 0; + #endif + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + u8 i = 0; + #endif + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT) + if (dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) { + if (is_single_rate) { + #if (RTL8822B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822B) + ret = phydm_write_txagc_1byte_8822b(dm, pwr_idx, + path, rate); + #endif + + #if (RTL8821C_SUPPORT) + if (dm->support_ic_type == ODM_RTL8821C) + ret = phydm_write_txagc_1byte_8821c(dm, pwr_idx, + path, rate); + #endif + + #if (RTL8195B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8195B) + ret = phydm_write_txagc_1byte_8195b(dm, pwr_idx, + path, rate); + #endif + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + set_current_tx_agc(dm->priv, path, rate, (u8)pwr_idx); + #endif + + } else { + #if (RTL8822B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822B) + ret = config_phydm_write_txagc_8822b(dm, + pwr_idx, + path, + rate); + #endif + + #if (RTL8821C_SUPPORT) + if (dm->support_ic_type == ODM_RTL8821C) + ret = config_phydm_write_txagc_8821c(dm, + pwr_idx, + path, + rate); + #endif + + #if (RTL8195B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8195B) + ret = config_phydm_write_txagc_8195b(dm, + pwr_idx, + path, + rate); + #endif + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + for (i = 0; i < 4; i++) + set_current_tx_agc(dm->priv, path, (rate + i), + (u8)pwr_idx); + #endif + } + } +#endif + +#if (RTL8198F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) { + if (rate < 0x4) + txagc_tmp = config_phydm_read_txagc_8198f(dm, path, + rate, + PDM_CCK); + else + txagc_tmp = config_phydm_read_txagc_8198f(dm, path, + rate, + PDM_OFDM); + + pw_by_rate_tmp = config_phydm_read_txagc_diff_8198f(dm, rate); + base = txagc_tmp - pw_by_rate_tmp; + if (DIFF_2(pwr_idx, base) > 63) + return false; + + pw_by_rate_new = (s8)(pwr_idx - base); + ret = phydm_write_txagc_1byte_8198f(dm, pw_by_rate_new, rate); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n", + __func__, path, rate, base, pw_by_rate_new); + } +#endif + +#if (RTL8822C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822C) { + if (rate < 0x4) + txagc_tmp = config_phydm_read_txagc_8822c(dm, path, + rate, + PDM_CCK); + else + txagc_tmp = config_phydm_read_txagc_8822c(dm, path, + rate, + PDM_OFDM); + + pw_by_rate_tmp = config_phydm_read_txagc_diff_8822c(dm, rate); + base = txagc_tmp - pw_by_rate_tmp; + if (DIFF_2(pwr_idx, base) > 63) + return false; + + pw_by_rate_new = (s8)(pwr_idx - base); + ret = phydm_write_txagc_1byte_8822c(dm, pw_by_rate_new, rate); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n", + __func__, path, rate, base, pw_by_rate_new); + } +#endif + +#if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_write_txagc_8197f(dm, pwr_idx, path, rate); +#endif + +#if (RTL8192F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) + ret = config_phydm_write_txagc_8192f(dm, pwr_idx, path, rate); +#endif + return ret; +} + +u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ret = 0; + +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822B) + ret = config_phydm_read_txagc_8822b(dm, path, hw_rate); +#endif + +#if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_read_txagc_8197f(dm, path, hw_rate); +#endif + +#if (RTL8821C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8821C) + ret = config_phydm_read_txagc_8821c(dm, path, hw_rate); +#endif + +#if (RTL8195B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8195B) + ret = config_phydm_read_txagc_8195b(dm, path, hw_rate); +#endif + +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) + ret = config_phydm_read_txagc_8192f(dm, path, hw_rate); +#endif + +#if (RTL8198F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) { + if (hw_rate < 0x4) { + ret = config_phydm_read_txagc_8198f(dm, path, hw_rate, + PDM_CCK); + } else { + ret = config_phydm_read_txagc_8198f(dm, path, hw_rate, + PDM_OFDM); + } + } +#endif + +#if (RTL8822C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822C) { + if (hw_rate < 0x4) { + ret = config_phydm_read_txagc_8822c(dm, path, hw_rate, + PDM_CCK); + } else { + ret = config_phydm_read_txagc_8822c(dm, path, hw_rate, + PDM_OFDM); + } + } +#endif + return ret; +} + +boolean +phydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch, + enum channel_width bw) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; + +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822B) + ret = config_phydm_switch_channel_bw_8822b(dm, ch, pri_ch, bw); +#endif + +#if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_switch_channel_bw_8197f(dm, ch, pri_ch, bw); +#endif + +#if (RTL8821C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8821C) + ret = config_phydm_switch_channel_bw_8821c(dm, ch, pri_ch, bw); +#endif + +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) + ret = config_phydm_switch_channel_bw_8192f(dm, ch, pri_ch, bw); +#endif + +#if (RTL8198F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) + ret = config_phydm_switch_channel_bw_8198f(dm, ch, pri_ch, bw); +#endif + +#if (RTL8822C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822C) + ret = config_phydm_switch_channel_bw_8822c(dm, ch, pri_ch, bw); +#endif + return ret; +} + +boolean +phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path, + boolean is_2tx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; + +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822B) + ret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path, is_2tx); +#endif + +#if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_trx_mode_8197f(dm, tx_path, rx_path, is_2tx); +#endif + +#if (RTL8192F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) + ret = config_phydm_trx_mode_8192f(dm, tx_path, rx_path, is_2tx); +#endif + +#if (RTL8198F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) + ret = config_phydm_trx_mode_8198f(dm, tx_path, rx_path, is_2tx); +#endif + +#if (RTL8822C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822C) + ret = config_phydm_trx_mode_8822c(dm, tx_path, rx_path, is_2tx); +#endif + return ret; +} +#else +u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 read_back_data = INVALID_TXAGC_DATA; + u32 reg_txagc; + u32 reg_mask; + /* This function is for 92E/88E etc... */ + /* @Input need to be HW rate index, not driver rate index!!!! */ + + /* @Error handling */ + if (path > RF_PATH_B || hw_rate > ODM_RATEMCS15) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: unsupported path (%d)\n", + __func__, path); + return INVALID_TXAGC_DATA; + } + + if (path == RF_PATH_A) { + switch (hw_rate) { + case ODM_RATE1M: + reg_txagc = R_0xe08; + reg_mask = 0x00007f00; + break; + case ODM_RATE2M: + reg_txagc = R_0x86c; + reg_mask = 0x00007f00; + break; + case ODM_RATE5_5M: + reg_txagc = R_0x86c; + reg_mask = 0x007f0000; + break; + case ODM_RATE11M: + reg_txagc = R_0x86c; + reg_mask = 0x7f000000; + break; + + case ODM_RATE6M: + reg_txagc = R_0xe00; + reg_mask = 0x0000007f; + break; + case ODM_RATE9M: + reg_txagc = R_0xe00; + reg_mask = 0x00007f00; + break; + case ODM_RATE12M: + reg_txagc = R_0xe00; + reg_mask = 0x007f0000; + break; + case ODM_RATE18M: + reg_txagc = R_0xe00; + reg_mask = 0x7f000000; + break; + case ODM_RATE24M: + reg_txagc = R_0xe04; + reg_mask = 0x0000007f; + break; + case ODM_RATE36M: + reg_txagc = R_0xe04; + reg_mask = 0x00007f00; + break; + case ODM_RATE48M: + reg_txagc = R_0xe04; + reg_mask = 0x007f0000; + break; + case ODM_RATE54M: + reg_txagc = R_0xe04; + reg_mask = 0x7f000000; + break; + + case ODM_RATEMCS0: + reg_txagc = R_0xe10; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS1: + reg_txagc = R_0xe10; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS2: + reg_txagc = R_0xe10; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS3: + reg_txagc = R_0xe10; + reg_mask = 0x7f000000; + break; + case ODM_RATEMCS4: + reg_txagc = R_0xe14; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS5: + reg_txagc = R_0xe14; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS6: + reg_txagc = R_0xe14; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS7: + reg_txagc = R_0xe14; + reg_mask = 0x7f000000; + break; + + case ODM_RATEMCS8: + reg_txagc = R_0xe18; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS9: + reg_txagc = R_0xe18; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS10: + reg_txagc = R_0xe18; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS11: + reg_txagc = R_0xe18; + reg_mask = 0x7f000000; + break; + case ODM_RATEMCS12: + reg_txagc = R_0xe1c; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS13: + reg_txagc = R_0xe1c; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS14: + reg_txagc = R_0xe1c; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS15: + reg_txagc = R_0xe1c; + reg_mask = 0x7f000000; + break; + + default: + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n"); + break; + } + } else if (path == RF_PATH_B) { + switch (hw_rate) { + case ODM_RATE1M: + reg_txagc = R_0x838; + reg_mask = 0x00007f00; + break; + case ODM_RATE2M: + reg_txagc = R_0x838; + reg_mask = 0x007f0000; + break; + case ODM_RATE5_5M: + reg_txagc = R_0x838; + reg_mask = 0x7f000000; + break; + case ODM_RATE11M: + reg_txagc = R_0x86c; + reg_mask = 0x0000007f; + break; + + case ODM_RATE6M: + reg_txagc = R_0x830; + reg_mask = 0x0000007f; + break; + case ODM_RATE9M: + reg_txagc = R_0x830; + reg_mask = 0x00007f00; + break; + case ODM_RATE12M: + reg_txagc = R_0x830; + reg_mask = 0x007f0000; + break; + case ODM_RATE18M: + reg_txagc = R_0x830; + reg_mask = 0x7f000000; + break; + case ODM_RATE24M: + reg_txagc = R_0x834; + reg_mask = 0x0000007f; + break; + case ODM_RATE36M: + reg_txagc = R_0x834; + reg_mask = 0x00007f00; + break; + case ODM_RATE48M: + reg_txagc = R_0x834; + reg_mask = 0x007f0000; + break; + case ODM_RATE54M: + reg_txagc = R_0x834; + reg_mask = 0x7f000000; + break; + + case ODM_RATEMCS0: + reg_txagc = R_0x83c; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS1: + reg_txagc = R_0x83c; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS2: + reg_txagc = R_0x83c; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS3: + reg_txagc = R_0x83c; + reg_mask = 0x7f000000; + break; + case ODM_RATEMCS4: + reg_txagc = R_0x848; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS5: + reg_txagc = R_0x848; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS6: + reg_txagc = R_0x848; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS7: + reg_txagc = R_0x848; + reg_mask = 0x7f000000; + break; + + case ODM_RATEMCS8: + reg_txagc = R_0x84c; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS9: + reg_txagc = R_0x84c; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS10: + reg_txagc = R_0x84c; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS11: + reg_txagc = R_0x84c; + reg_mask = 0x7f000000; + break; + case ODM_RATEMCS12: + reg_txagc = R_0x868; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS13: + reg_txagc = R_0x868; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS14: + reg_txagc = R_0x868; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS15: + reg_txagc = R_0x868; + reg_mask = 0x7f000000; + break; + + default: + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n"); + break; + } + } else { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid RF path!!\n"); + } + read_back_data = (u8)odm_get_bb_reg(dm, reg_txagc, reg_mask); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: path-%d rate index 0x%x = 0x%x\n", + __func__, path, hw_rate, read_back_data); + return read_back_data; +} +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_normal_driver_rx_sniffer( + struct dm_struct *dm, + u8 *desc, + PRT_RFD_STATUS rt_rfd_status, + u8 *drv_info, + u8 phy_status) +{ +#if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING)) + u32 *msg; + u16 seq_num; + + if (rt_rfd_status->packet_report_type != NORMAL_RX) + return; + + if (!dm->is_linked) { + if (rt_rfd_status->is_hw_error) + return; + } + + if (phy_status == true) { + if (dm->rx_pkt_type == type_block_ack || + dm->rx_pkt_type == type_rts || dm->rx_pkt_type == type_cts) + seq_num = 0; + else + seq_num = rt_rfd_status->seq_num; + + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, + "%04d , %01s, rate=0x%02x, L=%04d , %s , %s", + seq_num, + /*rt_rfd_status->mac_id,*/ + (rt_rfd_status->is_crc ? "C" : + rt_rfd_status->is_ampdu ? "A" : "_"), + rt_rfd_status->data_rate, + rt_rfd_status->length, + ((rt_rfd_status->band_width == 0) ? "20M" : + ((rt_rfd_status->band_width == 1) ? "40M" : "80M")), + (rt_rfd_status->is_ldpc ? "LDP" : "BCC")); + + if (dm->rx_pkt_type == type_asoc_req) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_REQ"); + else if (dm->rx_pkt_type == type_asoc_rsp) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_RSP"); + else if (dm->rx_pkt_type == type_probe_req) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_REQ"); + else if (dm->rx_pkt_type == type_probe_rsp) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_RSP"); + else if (dm->rx_pkt_type == type_deauth) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "DEAUTH"); + else if (dm->rx_pkt_type == type_beacon) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BEACON"); + else if (dm->rx_pkt_type == type_block_ack_req) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BA_REQ"); + else if (dm->rx_pkt_type == type_rts) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__RTS_"); + else if (dm->rx_pkt_type == type_cts) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__CTS_"); + else if (dm->rx_pkt_type == type_ack) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__ACK_"); + else if (dm->rx_pkt_type == type_block_ack) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__BA__"); + else if (dm->rx_pkt_type == type_data) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "_DATA_"); + else if (dm->rx_pkt_type == type_data_ack) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "Data_Ack"); + else if (dm->rx_pkt_type == type_qos_data) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "QoS_Data"); + else + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [0x%x]", + dm->rx_pkt_type); + + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [RSSI=%d,%d,%d,%d ]", + dm->rssi_a, + dm->rssi_b, + dm->rssi_c, + dm->rssi_d); + + msg = (u32 *)drv_info; + + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, + " , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n", + msg[6], msg[5], msg[4], msg[3], + msg[2], msg[1], msg[1]); + } else { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, + "%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n", + rt_rfd_status->seq_num, + /*rt_rfd_status->mac_id,*/ + (rt_rfd_status->is_crc ? "C" : + (rt_rfd_status->is_ampdu) ? "A" : "_"), + rt_rfd_status->data_rate, + rt_rfd_status->length, + ((rt_rfd_status->band_width == 0) ? "20M" : + ((rt_rfd_status->band_width == 1) ? "40M" : "80M")), + (rt_rfd_status->is_ldpc ? "LDP" : "BCC")); + } + +#endif +} +#endif diff --git a/hal/phydm/phydm_api.h b/hal/phydm/phydm_api.h new file mode 100644 index 0000000..835e140 --- /dev/null +++ b/hal/phydm/phydm_api.h @@ -0,0 +1,168 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_API_H__ +#define __PHYDM_API_H__ + +#define PHYDM_API_VERSION "1.0" /* @2017.07.10 Dino, Add phydm_api.h*/ + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ +#define CN_CNT_MAX 10 /*@max condition number threshold*/ + +#define FUNC_ENABLE 1 +#define FUNC_DISABLE 2 + +/*@NBI API------------------------------------*/ +#define NBI_128TONE 27 /*register table size*/ +#define NBI_256TONE 59 /*register table size*/ + +#define NUM_START_CH_80M 7 +#define NUM_START_CH_40M 14 + +#define CH_OFFSET_40M 2 +#define CH_OFFSET_80M 6 + +#define FFT_128_TYPE 1 +#define FFT_256_TYPE 2 + +#define FREQ_POSITIVE 1 +#define FREQ_NEGATIVE 2 +/*@------------------------------------------------*/ + +#ifndef PHYDM_COMMON_API_SUPPORT +#define INVALID_RF_DATA 0xffffffff +#define INVALID_TXAGC_DATA 0xff +#endif + +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +struct phydm_api_stuc { + u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/ + u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/ + u8 tx_queue_bitmap; /*REG0x520[23:16]*/ +}; + +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ +void phydm_reset_bb_hw_cnt_ac(void *dm_void); + +void phydm_dynamic_ant_weighting(void *dm_void); + +#ifdef DYN_ANT_WEIGHTING_SUPPORT +void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif + +void phydm_pathb_q_matrix_rotate_en(void *dm_void); + +void phydm_pathb_q_matrix_rotate(void *dm_void, u16 phase_idx); + +void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path); + +void phydm_config_ofdm_rx_path(void *dm_void, u32 path); + +void phydm_config_cck_rx_path(void *dm_void, enum bb_path path); + +void phydm_config_cck_rx_antenna_init(void *dm_void); + +void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_tx_2path(void *dm_void); + +void phydm_stop_3_wire(void *dm_void, u8 set_type); + +u8 phydm_stop_ic_trx(void *dm_void, u8 set_type); + +void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch); + +void phydm_nbi_enable(void *dm_void, u32 enable); + +u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, + u32 sec_ch); + +u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, + u32 sec_ch); + +void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_stop_ck320(void *dm_void, u8 enable); + +boolean +phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, u8 add_half_db); +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, + u32 f_intf, u32 sec_ch, u8 wgt); + +void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction, + u8 wgt); + +u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, + u32 sec_ch, u8 path); + +void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction, + u8 path); + +void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path); +#endif + +#ifdef PHYDM_COMMON_API_SUPPORT +boolean +phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path, + boolean is_positive); +boolean +phydm_api_set_txagc(void *dm_void, u32 power_index, enum rf_path path, + u8 hw_rate, boolean is_single_rate); + +u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate); + +boolean +phydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx, + enum channel_width bandwidth); + +boolean +phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path, + boolean is_tx2_path); + +#endif + +#endif diff --git a/hal/phydm/phydm_auto_dbg.c b/hal/phydm/phydm_auto_dbg.c new file mode 100644 index 0000000..9102170 --- /dev/null +++ b/hal/phydm/phydm_auto_dbg.c @@ -0,0 +1,671 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_AUTO_DEGBUG + +void phydm_check_hang_reset( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + + atd_t->dbg_step = 0; + atd_t->auto_dbg_type = AUTO_DBG_STOP; + phydm_pause_dm_watchdog(dm, PHYDM_RESUME); + dm->debug_components &= (~ODM_COMP_API); +} + +void phydm_check_hang_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + + atd_t->dbg_step = 0; + atd_t->auto_dbg_type = AUTO_DBG_STOP; + phydm_pause_dm_watchdog(dm, PHYDM_RESUME); +} + +#if (ODM_IC_11N_SERIES_SUPPORT == 1) +void phydm_auto_check_hang_engine_n( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + struct n_dbgport_803 dbgport_803 = {0}; + u32 value32_tmp = 0, value32_tmp_2 = 0; + u8 i; + u32 curr_dbg_port_val[DBGPORT_CHK_NUM]; + u16 curr_ofdm_t_cnt; + u16 curr_ofdm_r_cnt; + u16 curr_cck_t_cnt; + u16 curr_cck_r_cnt; + u16 curr_ofdm_crc_error_cnt; + u16 curr_cck_crc_error_cnt; + u16 diff_ofdm_t_cnt; + u16 diff_ofdm_r_cnt; + u16 diff_cck_t_cnt; + u16 diff_cck_r_cnt; + u16 diff_ofdm_crc_error_cnt; + u16 diff_cck_crc_error_cnt; + u8 rf_mode; + + if (atd_t->auto_dbg_type == AUTO_DBG_STOP) + return; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + phydm_check_hang_reset(dm); + return; + } + + if (atd_t->dbg_step == 0) { + pr_debug("dbg_step=0\n\n"); + + /*Reset all packet counter*/ + odm_set_bb_reg(dm, R_0xf14, BIT(16), 1); + odm_set_bb_reg(dm, R_0xf14, BIT(16), 0); + + } else if (atd_t->dbg_step == 1) { + pr_debug("dbg_step=1\n\n"); + + /*Check packet counter Register*/ + atd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD); + atd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD); + atd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, + MASKHWORD); + + atd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD); + atd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD); + atd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84, + 0x3fff); + + /*Check Debug Port*/ + for (i = 0; i < DBGPORT_CHK_NUM; i++) { + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, + (u32)atd_t->dbg_port_table[i]) + ) { + atd_t->dbg_port_val[i] = + phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); + } + } + + } else if (atd_t->dbg_step == 2) { + pr_debug("dbg_step=2\n\n"); + + /*Check packet counter Register*/ + curr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD); + curr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD); + curr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, + MASKHWORD); + + curr_cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD); + curr_cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD); + curr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84, + 0x3fff); + + /*Check Debug Port*/ + for (i = 0; i < DBGPORT_CHK_NUM; i++) { + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, + (u32)atd_t->dbg_port_table[i]) + ) { + curr_dbg_port_val[i] = + phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); + } + } + + /*=== Make check hang decision ===============================*/ + pr_debug("Check Hang Decision\n\n"); + + /* ----- Check RF Register -----------------------------------*/ + for (i = 0; i < dm->num_rf_path; i++) { + rf_mode = (u8)odm_get_rf_reg(dm, i, RF_0x0, 0xf0000); + pr_debug("RF0x0[%d] = 0x%x\n", i, rf_mode); + if (rf_mode > 3) { + pr_debug("Incorrect RF mode\n"); + pr_debug("ReasonCode:RHN-1\n"); + } + } + value32_tmp = odm_get_rf_reg(dm, 0, RF_0xb0, 0xf0000); + if (dm->support_ic_type == ODM_RTL8188E) { + if (value32_tmp != 0xff8c8) { + pr_debug("ReasonCode:RHN-3\n"); + } + } + /* ----- Check BB Register ----------------------------------*/ + /*BB mode table*/ + value32_tmp = odm_get_bb_reg(dm, R_0x824, 0xe); + value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0xe); + pr_debug("BB TX mode table {A, B}= {%d, %d}\n", + value32_tmp, value32_tmp_2); + + if (value32_tmp > 3 || value32_tmp_2 > 3) { + pr_debug("ReasonCode:RHN-2\n"); + } + + value32_tmp = odm_get_bb_reg(dm, R_0x824, 0x700000); + value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0x700000); + pr_debug("BB RX mode table {A, B}= {%d, %d}\n", value32_tmp, + value32_tmp_2); + + if (value32_tmp > 3 || value32_tmp_2 > 3) { + pr_debug("ReasonCode:RHN-2\n"); + } + + /*BB HW Block*/ + value32_tmp = odm_get_bb_reg(dm, R_0x800, MASKDWORD); + + if (!(value32_tmp & BIT(24))) { + pr_debug("Reg0x800[24] = 0, CCK BLK is disabled\n"); + pr_debug("ReasonCode: THN-3\n"); + } + + if (!(value32_tmp & BIT(25))) { + pr_debug("Reg0x800[24] = 0, OFDM BLK is disabled\n"); + pr_debug("ReasonCode:THN-3\n"); + } + + /*BB Continue TX*/ + value32_tmp = odm_get_bb_reg(dm, R_0xd00, 0x70000000); + pr_debug("Continue TX=%d\n", value32_tmp); + if (value32_tmp != 0) { + pr_debug("ReasonCode: THN-4\n"); + } + + /* ----- Check Packet Counter --------------------------------*/ + diff_ofdm_t_cnt = curr_ofdm_t_cnt - atd_t->ofdm_t_cnt; + diff_ofdm_r_cnt = curr_ofdm_r_cnt - atd_t->ofdm_r_cnt; + diff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt - + atd_t->ofdm_crc_error_cnt; + + diff_cck_t_cnt = curr_cck_t_cnt - atd_t->cck_t_cnt; + diff_cck_r_cnt = curr_cck_r_cnt - atd_t->cck_r_cnt; + diff_cck_crc_error_cnt = curr_cck_crc_error_cnt - + atd_t->cck_crc_error_cnt; + + pr_debug("OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n", + atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt, + atd_t->ofdm_crc_error_cnt); + pr_debug("OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n", + curr_ofdm_t_cnt, curr_ofdm_r_cnt, + curr_ofdm_crc_error_cnt); + pr_debug("OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\n", + diff_ofdm_t_cnt, diff_ofdm_r_cnt, + diff_ofdm_crc_error_cnt); + + pr_debug("CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n", + atd_t->cck_t_cnt, atd_t->cck_r_cnt, + atd_t->cck_crc_error_cnt); + pr_debug("CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n", + curr_cck_t_cnt, curr_cck_r_cnt, + curr_cck_crc_error_cnt); + pr_debug("CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\n", + diff_cck_t_cnt, diff_cck_r_cnt, + diff_cck_crc_error_cnt); + + /* ----- Check Dbg Port --------------------------------*/ + + for (i = 0; i < DBGPORT_CHK_NUM; i++) { + pr_debug("Dbg_port=((0x%x))\n", + atd_t->dbg_port_table[i]); + pr_debug("Val{pre, curr}={0x%x, 0x%x}\n", + atd_t->dbg_port_val[i], curr_dbg_port_val[i]); + + if (atd_t->dbg_port_table[i] == 0) { + if (atd_t->dbg_port_val[i] == + curr_dbg_port_val[i]) { + pr_debug("BB state hang\n"); + pr_debug("ReasonCode:\n"); + } + + } else if (atd_t->dbg_port_table[i] == 0x803) { + if (atd_t->dbg_port_val[i] == + curr_dbg_port_val[i]) { + /* dbgport_803 = */ + /* (struct n_dbgport_803 ) */ + /* (atd_t->dbg_port_val[i]); */ + odm_move_memory(dm, &dbgport_803, + &atd_t->dbg_port_val[i], + sizeof(struct n_dbgport_803)); + pr_debug("RSTB{BB, GLB, OFDM}={%d, %d,%d}\n", + dbgport_803.bb_rst_b, + dbgport_803.glb_rst_b, + dbgport_803.ofdm_rst_b); + pr_debug("{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\n", + dbgport_803.ofdm_tx_en, + dbgport_803.cck_tx_en, + dbgport_803.phy_tx_on); + pr_debug("CCA_PP{OFDM, CCK}={%d, %d}\n", + dbgport_803.ofdm_cca_pp, + dbgport_803.cck_cca_pp); + + if (dbgport_803.phy_tx_on) + pr_debug("Maybe TX Hang\n"); + else if (dbgport_803.ofdm_cca_pp || + dbgport_803.cck_cca_pp) + pr_debug("Maybe RX Hang\n"); + } + + } else if (atd_t->dbg_port_table[i] == 0x208) { + if ((atd_t->dbg_port_val[i] & BIT(30)) && + (curr_dbg_port_val[i] & BIT(30))) { + pr_debug("EDCCA Pause TX\n"); + pr_debug("ReasonCode: THN-2\n"); + } + + } else if (atd_t->dbg_port_table[i] == 0xab0) { + /* atd_t->dbg_port_val[i] & 0xffffff == 0 */ + /* curr_dbg_port_val[i] & 0xffffff == 0 */ + if (((atd_t->dbg_port_val[i] & + MASK24BITS) == 0) || + ((curr_dbg_port_val[i] & + MASK24BITS) == 0)) { + pr_debug("Wrong L-SIG formate\n"); + pr_debug("ReasonCode: THN-1\n"); + } + } + } + + phydm_check_hang_reset(dm); + } + + atd_t->dbg_step++; +} + +void phydm_bb_auto_check_hang_start_n( + void *dm_void, + u32 *_used, + char *output, + u32 *_out_len) +{ + u32 value32 = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + return; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "PHYDM auto check hang (N-series) is started, Please check the system log\n"); + + dm->debug_components |= ODM_COMP_API; + atd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG; + atd_t->dbg_step = 0; + + phydm_pause_dm_watchdog(dm, PHYDM_PAUSE); + + *_used = used; + *_out_len = out_len; +} + +void phydm_bb_rx_hang_info_n( + void *dm_void, + u32 *_used, + char *output, + u32 *_out_len) +{ + u32 value32 = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + return; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "not support now\n"); + + *_used = used; + *_out_len = out_len; +} + +#endif + +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) +void phydm_bb_rx_hang_info_ac( + void *dm_void, + u32 *_used, + char *output, + u32 *_out_len) +{ + u32 value32 = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) + return; + + value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32); + + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, R_0x198c, BIT(2) | BIT(1) | BIT(0), 7); + + /* dbg_port = basic state machine */ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "basic state machine", value32); + } + + /* dbg_port = state machine */ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "state machine", value32); + } + + /* dbg_port = CCA-related*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "CCA-related", value32); + } + + /* dbg_port = edcca/rxd*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "edcca/rxd", value32); + } + + /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", + "rx_state/mux_state/ADC_MASK_OFDM", value32); + } + + /* dbg_port = bf-related*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "bf-related", value32); + } + + /* dbg_port = bf-related*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "bf-related", value32); + } + + /* dbg_port = txon/rxd*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "txon/rxd", value32); + } + + /* dbg_port = l_rate/l_length*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "l_rate/l_length", value32); + } + + /* dbg_port = rxd/rxd_hit*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32); + } + + /* dbg_port = dis_cca*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "dis_cca", value32); + } + + /* dbg_port = tx*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "tx", value32); + } + + /* dbg_port = rx plcp*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + } + *_used = used; + *_out_len = out_len; +} +#endif + +void phydm_auto_dbg_console( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Show dbg port: {1} {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Auto check hang: {1} {2}\n"); + return; + } else if (var1[0] == 1) { + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); + + if (var1[1] == 1) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if (ODM_IC_11AC_SERIES_SUPPORT == 1) + phydm_bb_rx_hang_info_ac(dm, &used, output, + &out_len); + #else + PDM_SNPF(out_len, used, output + used, + out_len - used, "Not support\n"); + #endif + } else { + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + phydm_bb_rx_hang_info_n(dm, &used, output, + &out_len); + #else + PDM_SNPF(out_len, used, output + used, + out_len - used, "Not support\n"); + #endif + } + } else if (var1[1] == 2) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + PDM_SNPF(out_len, used, output + used, + out_len - used, "Not support\n"); + } else { + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + phydm_bb_auto_check_hang_start_n(dm, &used, + output, + &out_len); + #else + PDM_SNPF(out_len, used, output + used, + out_len - used, "Not support\n"); + #endif + } + } + } + + *_used = used; + *_out_len = out_len; +} + +void phydm_auto_dbg_engine(void *dm_void) +{ + u32 value32 = 0; + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + + if (atd_t->auto_dbg_type == AUTO_DBG_STOP) + return; + + pr_debug("%s ======>\n", __func__); + + if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_HANG) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + pr_debug("Not Support\n"); + } else { + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + phydm_auto_check_hang_engine_n(dm); + #else + pr_debug("Not Support\n"); + #endif + } + + } else if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_RA) { + pr_debug("Not Support\n"); + } +} + +void phydm_auto_dbg_engine_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0, + 0xab1, 0xab2}; + + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>n", __func__); + + odm_move_memory(dm, &atd_t->dbg_port_table[0], + &dbg_port_table[0], (DBGPORT_CHK_NUM * 2)); + + phydm_check_hang_init(dm); +} +#endif diff --git a/hal/phydm/phydm_auto_dbg.h b/hal/phydm/phydm_auto_dbg.h new file mode 100644 index 0000000..f6ef51d --- /dev/null +++ b/hal/phydm/phydm_auto_dbg.h @@ -0,0 +1,113 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_AUTO_DBG_H__ +#define __PHYDM_AUTO_DBG_H__ + +#define AUTO_DBG_VERSION "1.0" /* @2017.05.015 Dino, Add phydm_auto_dbg.h*/ + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ + +#define AUTO_CHK_HANG_STEP_MAX 3 +#define DBGPORT_CHK_NUM 6 + +#ifdef PHYDM_AUTO_DEGBUG + +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +enum auto_dbg_type_e { + AUTO_DBG_STOP = 0, + AUTO_DBG_CHECK_HANG = 1, + AUTO_DBG_CHECK_RA = 2, + AUTO_DBG_CHECK_DIG = 3 +}; + +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +struct n_dbgport_803 { + /*@BYTE 3*/ + u8 bb_rst_b : 1; + u8 glb_rst_b : 1; + u8 zero_1bit_1 : 1; + u8 ofdm_rst_b : 1; + u8 cck_txpe : 1; + u8 ofdm_txpe : 1; + u8 phy_tx_on : 1; + u8 tdrdy : 1; + /*@BYTE 2*/ + u8 txd : 8; + /*@BYTE 1*/ + u8 cck_cca_pp : 1; + u8 ofdm_cca_pp : 1; + u8 rx_rst : 1; + u8 rdrdy : 1; + u8 rxd_7_4 : 4; + /*@BYTE 0*/ + u8 rxd_3_0 : 4; + u8 ofdm_tx_en : 1; + u8 cck_tx_en : 1; + u8 zero_1bit_2 : 1; + u8 clk_80m : 1; +}; + +struct phydm_auto_dbg_struct { + enum auto_dbg_type_e auto_dbg_type; + u8 dbg_step; + u16 dbg_port_table[DBGPORT_CHK_NUM]; + u32 dbg_port_val[DBGPORT_CHK_NUM]; + u16 ofdm_t_cnt; + u16 ofdm_r_cnt; + u16 cck_t_cnt; + u16 cck_r_cnt; + u16 ofdm_crc_error_cnt; + u16 cck_crc_error_cnt; +}; + +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ + +void phydm_auto_dbg_console( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len); + +void phydm_auto_dbg_engine(void *dm_void); + +void phydm_auto_dbg_engine_init(void *dm_void); +#endif +#endif diff --git a/hal/phydm/phydm_beamforming.c b/hal/phydm/phydm_beamforming.c index 529e751..ae7fed1 100644 --- a/hal/phydm/phydm_beamforming.c +++ b/hal/phydm/phydm_beamforming.c @@ -1,3 +1,28 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + #include "mp_precomp.h" #include "phydm_precomp.h" @@ -9,115 +34,157 @@ #if (BEAMFORMING_SUPPORT == 1) +void phydm_get_txbf_device_num( + void *dm_void, + u8 macid) +{ +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*@For BDC*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct bf_cmn_info *bf = NULL; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + u8 act_as_bfer = 0; + u8 act_as_bfee = 0; + + if (is_sta_active(sta)) { + bf = &(sta->bf_info); + } else { + PHYDM_DBG(dm, DBG_TXBF, "[Warning] %s invalid sta_info\n", + __func__); + return; + } + + if (sta->support_wireless_set & WIRELESS_VHT) { + if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE) + act_as_bfer = 1; + + if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMER_ENABLE) + act_as_bfee = 1; + + } else if (sta->support_wireless_set & WIRELESS_HT) { + if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) + act_as_bfer = 1; + + if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMER_ENABLE) + act_as_bfee = 1; + } + + if (act_as_bfer)) + { /* Our Device act as BFer */ + dm_bdc_table->w_bfee_client[macid] = true; + dm_bdc_table->num_txbfee_client++; + } + else + dm_bdc_table->w_bfee_client[macid] = false; + + if (act_as_bfee)) + { /* Our Device act as BFee */ + dm_bdc_table->w_bfer_client[macid] = true; + dm_bdc_table->num_txbfer_client++; + } + else + dm_bdc_table->w_bfer_client[macid] = false; + +#endif +#endif +} + struct _RT_BEAMFORM_STAINFO * phydm_sta_info_init( - struct PHY_DM_STRUCT *p_dm_odm, - u16 sta_idx -) + struct dm_struct *dm, + u16 sta_idx) { - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORM_STAINFO *p_entry = &(p_beam_info->beamform_sta_info); - struct sta_info *p_sta = p_dm_odm->p_odm_sta_info[sta_idx]; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORM_STAINFO *entry = &beam_info->beamform_sta_info; + struct sta_info *sta = dm->odm_sta_info[sta_idx]; + struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx]; + //void *adapter = dm->adapter; + ADAPTER * adapter = dm->adapter; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMGNT_INFO p_MgntInfo = &adapter->MgntInfo; - PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo); - PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo); - u1Byte iotpeer = 0; - - iotpeer = p_MgntInfo->IOTPeer; - odm_move_memory(p_dm_odm, p_entry->my_mac_addr, adapter->CurrentAddress, 6); - - p_entry->ht_beamform_cap = p_ht_info->HtBeamformCap; - p_entry->vht_beamform_cap = p_vht_info->VhtBeamformCap; - - /*IBSS, AP mode*/ - if (sta_idx != 0) { - p_entry->aid = p_sta->AID; - p_entry->ra = p_sta->MacAddr; - p_entry->mac_id = p_sta->AssociatedMacId; - p_entry->wireless_mode = p_sta->WirelessMode; - p_entry->bw = p_sta->BandWidth; - p_entry->cur_beamform = p_sta->HTInfo.HtCurBeamform; - } else {/*client mode*/ - p_entry->aid = p_MgntInfo->mAId; - p_entry->ra = p_MgntInfo->Bssid; - p_entry->mac_id = p_MgntInfo->mMacId; - p_entry->wireless_mode = p_MgntInfo->dot11CurrentWirelessMode; - p_entry->bw = p_MgntInfo->dot11CurrentChannelBandWidth; - p_entry->cur_beamform = p_ht_info->HtCurBeamform; - } + PMGNT_INFO p_MgntInfo = &((adapter)->MgntInfo); + PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo); + PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo); +#endif - if ((p_entry->wireless_mode & WIRELESS_MODE_AC_5G) || (p_entry->wireless_mode & WIRELESS_MODE_AC_24G)) { - if (sta_idx != 0) - p_entry->cur_beamform_vht = p_sta->VHTInfo.VhtCurBeamform; - else - p_entry->cur_beamform_vht = p_vht_info->VhtCurBeamform; + if (!is_sta_active(cmn_sta)) { + PHYDM_DBG(dm, DBG_TXBF, "%s => sta_info(mac_id:%d) failed\n", + __func__, sta_idx); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_warn_on(1); + #endif + + return entry; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("p_sta->wireless_mode = 0x%x, staidx = %d\n", p_sta->WirelessMode, sta_idx)); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + odm_move_memory(dm, (PVOID)(entry->my_mac_addr), (PVOID)(adapter->CurrentAddress), 6); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + odm_move_memory(dm, entry->my_mac_addr, adapter_mac_addr(sta->padapter), 6); +#endif - if (!IS_STA_VALID(p_sta)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s => sta_info(mac_id:%d) failed\n", __func__, sta_idx)); - rtw_warn_on(1); - return p_entry; + entry->aid = cmn_sta->aid; + entry->ra = cmn_sta->mac_addr; + entry->mac_id = cmn_sta->mac_id; + entry->bw = cmn_sta->bw_mode; + entry->cur_beamform = cmn_sta->bf_info.ht_beamform_cap; + entry->ht_beamform_cap = cmn_sta->bf_info.ht_beamform_cap; + +#if ODM_IC_11AC_SERIES_SUPPORT + if (cmn_sta->support_wireless_set & WIRELESS_VHT) { + entry->cur_beamform_vht = cmn_sta->bf_info.vht_beamform_cap; + entry->vht_beamform_cap = cmn_sta->bf_info.vht_beamform_cap; } +#endif - odm_move_memory(p_dm_odm, p_entry->my_mac_addr, adapter_mac_addr(p_sta->padapter), 6); - p_entry->ht_beamform_cap = p_sta->htpriv.beamform_cap; - - p_entry->aid = p_sta->aid; - p_entry->ra = p_sta->hwaddr; - p_entry->mac_id = p_sta->mac_id; - p_entry->wireless_mode = p_sta->wireless_mode; - p_entry->bw = p_sta->bw_mode; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*To Be Removed */ + entry->ht_beamform_cap = p_ht_info->HtBeamformCap; /*To Be Removed*/ + entry->vht_beamform_cap = p_vht_info->VhtBeamformCap; /*To Be Removed*/ - p_entry->cur_beamform = p_sta->htpriv.beamform_cap; -#if ODM_IC_11AC_SERIES_SUPPORT - if ((p_entry->wireless_mode & WIRELESS_MODE_AC_5G) || (p_entry->wireless_mode & WIRELESS_MODE_AC_24G)) { - p_entry->cur_beamform_vht = p_sta->vhtpriv.beamform_cap; - p_entry->vht_beamform_cap = p_sta->vhtpriv.beamform_cap; + if (sta_idx == 0) { /*@client mode*/ + #if ODM_IC_11AC_SERIES_SUPPORT + if (cmn_sta->support_wireless_set & WIRELESS_VHT) + entry->cur_beamform_vht = p_vht_info->VhtCurBeamform; + #endif } #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("p_sta->wireless_mode = 0x%x, staidx = %d\n", p_sta->wireless_mode, sta_idx)); -#endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("p_entry->cur_beamform = 0x%x, p_entry->cur_beamform_vht = 0x%x\n", p_entry->cur_beamform, p_entry->cur_beamform_vht)); - return p_entry; + PHYDM_DBG(dm, DBG_TXBF, "wireless_set = 0x%x, staidx = %d\n", + cmn_sta->support_wireless_set, sta_idx); + PHYDM_DBG(dm, DBG_TXBF, + "entry->cur_beamform = 0x%x, entry->cur_beamform_vht = 0x%x\n", + entry->cur_beamform, entry->cur_beamform_vht); + return entry; } void phydm_sta_info_update( - struct PHY_DM_STRUCT *p_dm_odm, - u16 sta_idx, - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry -) + struct dm_struct *dm, + u16 sta_idx, + struct _RT_BEAMFORMEE_ENTRY *beamform_entry) { - struct sta_info *p_sta = p_dm_odm->p_odm_sta_info[sta_idx]; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; - if (!IS_STA_VALID(p_sta)) + if (!is_sta_active(sta)) return; -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - p_sta->txbf_paid = p_beamform_entry->p_aid; - p_sta->txbf_gid = p_beamform_entry->g_id; -#endif + sta->bf_info.p_aid = beamform_entry->p_aid; + sta->bf_info.g_id = beamform_entry->g_id; } struct _RT_BEAMFORMEE_ENTRY * phydm_beamforming_get_bfee_entry_by_addr( - void *p_dm_void, - u8 *RA, - u8 *idx -) + void *dm_void, + u8 *RA, + u8 *idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (p_beam_info->beamformee_entry[i].is_used && (eq_mac_addr(RA, p_beam_info->beamformee_entry[i].mac_addr))) { + if (beam_info->beamformee_entry[i].is_used && (eq_mac_addr(RA, beam_info->beamformee_entry[i].mac_addr))) { *idx = i; - return &(p_beam_info->beamformee_entry[i]); + return &beam_info->beamformee_entry[i]; } } @@ -126,62 +193,57 @@ phydm_beamforming_get_bfee_entry_by_addr( struct _RT_BEAMFORMER_ENTRY * phydm_beamforming_get_bfer_entry_by_addr( - void *p_dm_void, - u8 *TA, - u8 *idx -) + void *dm_void, + u8 *TA, + u8 *idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - if (p_beam_info->beamformer_entry[i].is_used && (eq_mac_addr(TA, p_beam_info->beamformer_entry[i].mac_addr))) { + if (beam_info->beamformer_entry[i].is_used && (eq_mac_addr(TA, beam_info->beamformer_entry[i].mac_addr))) { *idx = i; - return &(p_beam_info->beamformer_entry[i]); + return &beam_info->beamformer_entry[i]; } } return NULL; } - struct _RT_BEAMFORMEE_ENTRY * phydm_beamforming_get_entry_by_mac_id( - void *p_dm_void, - u8 mac_id, - u8 *idx -) + void *dm_void, + u8 mac_id, + u8 *idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (p_beam_info->beamformee_entry[i].is_used && (mac_id == p_beam_info->beamformee_entry[i].mac_id)) { + if (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) { *idx = i; - return &(p_beam_info->beamformee_entry[i]); + return &beam_info->beamformee_entry[i]; } } return NULL; } - enum beamforming_cap phydm_beamforming_get_entry_beam_cap_by_mac_id( - void *p_dm_void, - u8 mac_id -) + void *dm_void, + u8 mac_id) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - enum beamforming_cap beamform_entry_cap = BEAMFORMING_CAP_NONE; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + enum beamforming_cap beamform_entry_cap = BEAMFORMING_CAP_NONE; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (p_beam_info->beamformee_entry[i].is_used && (mac_id == p_beam_info->beamformee_entry[i].mac_id)) { - beamform_entry_cap = p_beam_info->beamformee_entry[i].beamform_entry_cap; + if (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) { + beamform_entry_cap = beam_info->beamformee_entry[i].beamform_entry_cap; i = BEAMFORMEE_ENTRY_NUM; } } @@ -189,21 +251,19 @@ phydm_beamforming_get_entry_beam_cap_by_mac_id( return beamform_entry_cap; } - struct _RT_BEAMFORMEE_ENTRY * phydm_beamforming_get_free_bfee_entry( - void *p_dm_void, - u8 *idx -) + void *dm_void, + u8 *idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (p_beam_info->beamformee_entry[i].is_used == false) { + if (beam_info->beamformee_entry[i].is_used == false) { *idx = i; - return &(p_beam_info->beamformee_entry[i]); + return &beam_info->beamformee_entry[i]; } } return NULL; @@ -211,26 +271,25 @@ phydm_beamforming_get_free_bfee_entry( struct _RT_BEAMFORMER_ENTRY * phydm_beamforming_get_free_bfer_entry( - void *p_dm_void, - u8 *idx -) + void *dm_void, + u8 *idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s ===>\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s ===>\n", __func__); for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - if (p_beam_info->beamformer_entry[i].is_used == false) { + if (beam_info->beamformer_entry[i].is_used == false) { *idx = i; - return &(p_beam_info->beamformer_entry[i]); + return &beam_info->beamformer_entry[i]; } } return NULL; } -/* +/*@ * Description: Get the first entry index of MU Beamformee. * * Return value: index of the first MU sta. @@ -238,19 +297,18 @@ phydm_beamforming_get_free_bfer_entry( * 2015.05.25. Created by tynli. * */ -u8 -phydm_beamforming_get_first_mu_bfee_entry_idx( - void *p_dm_void -) +u8 phydm_beamforming_get_first_mu_bfee_entry_idx( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 idx = 0xFF; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - boolean is_found = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx = 0xFF; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + boolean is_found = false; for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].is_mu_sta) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d!\n", __func__, idx)); + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].is_mu_sta) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] idx=%d!\n", __func__, + idx); is_found = true; break; } @@ -262,137 +320,141 @@ phydm_beamforming_get_first_mu_bfee_entry_idx( return idx; } - -/*Add SU BFee and MU BFee*/ +/*@Add SU BFee and MU BFee*/ struct _RT_BEAMFORMEE_ENTRY * beamforming_add_bfee_entry( - void *p_dm_void, - struct _RT_BEAMFORM_STAINFO *p_sta, - enum beamforming_cap beamform_cap, - u8 num_of_sounding_dim, - u8 comp_steering_num_of_bfer, - u8 *idx -) + void *dm_void, + struct _RT_BEAMFORM_STAINFO *sta, + enum beamforming_cap beamform_cap, + u8 num_of_sounding_dim, + u8 comp_steering_num_of_bfer, + u8 *idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMEE_ENTRY *p_entry = phydm_beamforming_get_free_bfee_entry(p_dm_odm, idx); - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (p_entry != NULL) { - p_entry->is_used = true; - p_entry->aid = p_sta->aid; - p_entry->mac_id = p_sta->mac_id; - p_entry->sound_bw = p_sta->bw; - odm_move_memory(p_dm_odm, p_entry->my_mac_addr, p_sta->my_mac_addr, 6); - - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) { - /*BSSID[44:47] xor BSSID[40:43]*/ - u16 bssid = ((p_sta->my_mac_addr[5] & 0xf0) >> 4) ^ (p_sta->my_mac_addr[5] & 0xf); - /*(dec(A) + dec(B)*32) mod 512*/ - p_entry->p_aid = (p_sta->aid + bssid * 32) & 0x1ff; - p_entry->g_id = 63; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to STA=%d\n", __func__, p_entry->p_aid)); - } else if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) { - /*ad hoc mode*/ - p_entry->p_aid = 0; - p_entry->g_id = 63; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID as IBSS=%d\n", __func__, p_entry->p_aid)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMEE_ENTRY *entry = phydm_beamforming_get_free_bfee_entry(dm, idx); + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + if (entry != NULL) { + entry->is_used = true; + entry->aid = sta->aid; + entry->mac_id = sta->mac_id; + entry->sound_bw = sta->bw; + odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6); + + if (phydm_acting_determine(dm, phydm_acting_as_ap)) { + /*@BSSID[44:47] xor BSSID[40:43]*/ + u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf); + /*@(dec(A) + dec(B)*32) mod 512*/ + entry->p_aid = (sta->aid + bssid * 32) & 0x1ff; + entry->g_id = 63; + PHYDM_DBG(dm, DBG_TXBF, + "%s: BFee P_AID addressed to STA=%d\n", + __func__, entry->p_aid); + } else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) { + /*@ad hoc mode*/ + entry->p_aid = 0; + entry->g_id = 63; + PHYDM_DBG(dm, DBG_TXBF, "%s: BFee P_AID as IBSS=%d\n", + __func__, entry->p_aid); } else { - /*client mode*/ - p_entry->p_aid = p_sta->ra[5]; - /*BSSID[39:47]*/ - p_entry->p_aid = (p_entry->p_aid << 1) | (p_sta->ra[4] >> 7); - p_entry->g_id = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to AP=0x%X\n", __func__, p_entry->p_aid)); + /*@client mode*/ + entry->p_aid = sta->ra[5]; + /*@BSSID[39:47]*/ + entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7); + entry->g_id = 0; + PHYDM_DBG(dm, DBG_TXBF, + "%s: BFee P_AID addressed to AP=0x%X\n", + __func__, entry->p_aid); } - cp_mac_addr(p_entry->mac_addr, p_sta->ra); - p_entry->is_txbf = false; - p_entry->is_sound = false; - p_entry->sound_period = 400; - p_entry->beamform_entry_cap = beamform_cap; - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + cp_mac_addr(entry->mac_addr, sta->ra); + entry->is_txbf = false; + entry->is_sound = false; + entry->sound_period = 400; + entry->beamform_entry_cap = beamform_cap; + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - /* p_entry->log_seq = 0xff; Move to beamforming_add_bfer_entry*/ - /* p_entry->log_retry_cnt = 0; Move to beamforming_add_bfer_entry*/ - /* p_entry->LogSuccessCnt = 0; Move to beamforming_add_bfer_entry*/ + /* @entry->log_seq = 0xff; Move to beamforming_add_bfer_entry*/ + /* @entry->log_retry_cnt = 0; Move to beamforming_add_bfer_entry*/ + /* @entry->LogSuccessCnt = 0; Move to beamforming_add_bfer_entry*/ - p_entry->log_status_fail_cnt = 0; + entry->log_status_fail_cnt = 0; - p_entry->num_of_sounding_dim = num_of_sounding_dim; - p_entry->comp_steering_num_of_bfer = comp_steering_num_of_bfer; + entry->num_of_sounding_dim = num_of_sounding_dim; + entry->comp_steering_num_of_bfer = comp_steering_num_of_bfer; if (beamform_cap & BEAMFORMER_CAP_VHT_MU) { - p_dm_odm->beamforming_info.beamformee_mu_cnt += 1; - p_entry->is_mu_sta = true; - p_dm_odm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(p_dm_odm); + dm->beamforming_info.beamformee_mu_cnt += 1; + entry->is_mu_sta = true; + dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm); } else if (beamform_cap & (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { - p_dm_odm->beamforming_info.beamformee_su_cnt += 1; - p_entry->is_mu_sta = false; + dm->beamforming_info.beamformee_su_cnt += 1; + entry->is_mu_sta = false; } - return p_entry; + return entry; } else return NULL; } -/*Add SU BFee and MU BFer*/ +/*@Add SU BFee and MU BFer*/ struct _RT_BEAMFORMER_ENTRY * beamforming_add_bfer_entry( - void *p_dm_void, - struct _RT_BEAMFORM_STAINFO *p_sta, - enum beamforming_cap beamform_cap, - u8 num_of_sounding_dim, - u8 *idx -) + void *dm_void, + struct _RT_BEAMFORM_STAINFO *sta, + enum beamforming_cap beamform_cap, + u8 num_of_sounding_dim, + u8 *idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMER_ENTRY *p_entry = phydm_beamforming_get_free_bfer_entry(p_dm_odm, idx); - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - - if (p_entry != NULL) { - p_entry->is_used = true; - odm_move_memory(p_dm_odm, p_entry->my_mac_addr, p_sta->my_mac_addr, 6); - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) { - /*BSSID[44:47] xor BSSID[40:43]*/ - u16 bssid = ((p_sta->my_mac_addr[5] & 0xf0) >> 4) ^ (p_sta->my_mac_addr[5] & 0xf); - - p_entry->p_aid = (p_sta->aid + bssid * 32) & 0x1ff; - p_entry->g_id = 63; - /*(dec(A) + dec(B)*32) mod 512*/ - } else if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) { - p_entry->p_aid = 0; - p_entry->g_id = 63; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMER_ENTRY *entry = phydm_beamforming_get_free_bfer_entry(dm, idx); + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + if (entry != NULL) { + entry->is_used = true; + odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6); + if (phydm_acting_determine(dm, phydm_acting_as_ap)) { + /*@BSSID[44:47] xor BSSID[40:43]*/ + u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf); + + entry->p_aid = (sta->aid + bssid * 32) & 0x1ff; + entry->g_id = 63; + /*@(dec(A) + dec(B)*32) mod 512*/ + } else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) { + entry->p_aid = 0; + entry->g_id = 63; } else { - p_entry->p_aid = p_sta->ra[5]; - /*BSSID[39:47]*/ - p_entry->p_aid = (p_entry->p_aid << 1) | (p_sta->ra[4] >> 7); - p_entry->g_id = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: P_AID addressed to AP=0x%X\n", __func__, p_entry->p_aid)); + entry->p_aid = sta->ra[5]; + /*@BSSID[39:47]*/ + entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7); + entry->g_id = 0; + PHYDM_DBG(dm, DBG_TXBF, + "%s: P_AID addressed to AP=0x%X\n", __func__, + entry->p_aid); } - cp_mac_addr(p_entry->mac_addr, p_sta->ra); - p_entry->beamform_entry_cap = beamform_cap; + cp_mac_addr(entry->mac_addr, sta->ra); + entry->beamform_entry_cap = beamform_cap; - p_entry->pre_log_seq = 0; /*Modified by Jeffery @2015-04-13*/ - p_entry->log_seq = 0; /*Modified by Jeffery @2014-10-29*/ - p_entry->log_retry_cnt = 0; /*Modified by Jeffery @2014-10-29*/ - p_entry->log_success = 0; /*log_success is NOT needed to be accumulated, so LogSuccessCnt->log_success, 2015-04-13, Jeffery*/ - p_entry->clock_reset_times = 0; /*Modified by Jeffery @2015-04-13*/ + entry->pre_log_seq = 0; /*@Modified by Jeffery @2015-04-13*/ + entry->log_seq = 0; /*@Modified by Jeffery @2014-10-29*/ + entry->log_retry_cnt = 0; /*@Modified by Jeffery @2014-10-29*/ + entry->log_success = 0; /*@log_success is NOT needed to be accumulated, so LogSuccessCnt->log_success, 2015-04-13, Jeffery*/ + entry->clock_reset_times = 0; /*@Modified by Jeffery @2015-04-13*/ - p_entry->num_of_sounding_dim = num_of_sounding_dim; + entry->num_of_sounding_dim = num_of_sounding_dim; if (beamform_cap & BEAMFORMEE_CAP_VHT_MU) { - p_dm_odm->beamforming_info.beamformer_mu_cnt += 1; - p_entry->is_mu_ap = true; - p_entry->aid = p_sta->aid; + dm->beamforming_info.beamformer_mu_cnt += 1; + entry->is_mu_ap = true; + entry->aid = sta->aid; } else if (beamform_cap & (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { - p_dm_odm->beamforming_info.beamformer_su_cnt += 1; - p_entry->is_mu_ap = false; + dm->beamforming_info.beamformer_su_cnt += 1; + entry->is_mu_ap = false; } - return p_entry; + return entry; } else return NULL; } @@ -400,281 +462,267 @@ beamforming_add_bfer_entry( #if 0 boolean beamforming_remove_entry( - struct _ADAPTER *adapter, + void *adapter, u8 *RA, u8 *idx ) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; - struct _RT_BEAMFORMER_ENTRY *p_bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, RA, idx); - struct _RT_BEAMFORMEE_ENTRY *p_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, idx); + struct _RT_BEAMFORMER_ENTRY *bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, idx); + struct _RT_BEAMFORMEE_ENTRY *entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, idx); boolean ret = false; RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s Start!\n", __func__)); - RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, p_bfer_entry=0x%x\n", __func__, p_bfer_entry)); - RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, p_entry=0x%x\n", __func__, p_entry)); - - if (p_entry != NULL) { - p_entry->is_used = false; - p_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; - /*p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/ - p_entry->is_beamforming_in_progress = false; + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, bfer_entry=0x%x\n", __func__, bfer_entry)); + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, entry=0x%x\n", __func__, entry)); + + if (entry != NULL) { + entry->is_used = false; + entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + /*@entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/ + entry->is_beamforming_in_progress = false; ret = true; } - if (p_bfer_entry != NULL) { - p_bfer_entry->is_used = false; - p_bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + if (bfer_entry != NULL) { + bfer_entry->is_used = false; + bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; ret = true; } return ret; - } #endif /* Used for beamforming_start_v1 */ -void -phydm_beamforming_ndpa_rate( - void *p_dm_void, - CHANNEL_WIDTH BW, - u8 rate -) +void phydm_beamforming_ndpa_rate( + void *dm_void, + enum channel_width BW, + u8 rate) { - u16 ndpa_rate = rate; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u16 ndpa_rate = rate; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); if (ndpa_rate == 0) { - if (p_dm_odm->rssi_min > 30) /* link RSSI > 30% */ + if (dm->rssi_min > 30) /* @link RSSI > 30% */ ndpa_rate = ODM_RATE24M; else ndpa_rate = ODM_RATE6M; } if (ndpa_rate < ODM_RATEMCS0) - BW = (CHANNEL_WIDTH)ODM_BW20M; + BW = (enum channel_width)CHANNEL_WIDTH_20; ndpa_rate = (ndpa_rate << 8) | BW; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); - + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); } - /* Used for beamforming_start_sw and beamforming_start_fw */ -void -phydm_beamforming_dym_ndpa_rate( - void *p_dm_void -) +void phydm_beamforming_dym_ndpa_rate( + void *dm_void) { - u16 ndpa_rate = ODM_RATE6M, BW; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + u16 ndpa_rate = ODM_RATE6M, BW; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->rssi_min > 30) /*link RSSI > 30%*/ - ndpa_rate = ODM_RATE24M; - else - ndpa_rate = ODM_RATE6M; + ndpa_rate = ODM_RATE6M; + BW = CHANNEL_WIDTH_20; - BW = ODM_BW20M; ndpa_rate = ndpa_rate << 8 | BW; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, NDPA rate = 0x%X\n", __func__, ndpa_rate)); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); + PHYDM_DBG(dm, DBG_TXBF, "%s End, NDPA rate = 0x%X\n", __func__, + ndpa_rate); } -/* +/*@ * SW Sounding : SW Timer unit 1ms * HW Timer unit (1/32000) s 32k is clock. * FW Sounding : FW Timer unit 10ms */ -void -beamforming_dym_period( - void *p_dm_void, - u8 status -) +void beamforming_dym_period( + void *dm_void, + u8 status) { - u8 idx; - boolean is_change_period = false; - u16 sound_period_sw, sound_period_fw; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 idx; + boolean is_change_period = false; + u16 sound_period_sw, sound_period_fw; + struct dm_struct *dm = (struct dm_struct *)dm_void; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; - struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); + struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx]; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - /* 3 TODO per-client throughput caculation. */ + /* @3 TODO per-client throughput caculation. */ - if ((*(p_dm_odm->p_current_tx_tp) + *(p_dm_odm->p_current_rx_tp) > 2) && ((p_entry->log_status_fail_cnt <= 20) || status)) { - sound_period_sw = 40; /* 40ms */ - sound_period_fw = 40; /* From H2C cmd, unit = 10ms */ + if ((*dm->current_tx_tp + *dm->current_rx_tp > 2) && (entry->log_status_fail_cnt <= 20 || status)) { + sound_period_sw = 40; /* @40ms */ + sound_period_fw = 40; /* @From H2C cmd, unit = 10ms */ } else { - sound_period_sw = 4000;/* 4s */ + sound_period_sw = 4000; /* @4s */ sound_period_fw = 400; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]sound_period_sw=%d, sound_period_fw=%d\n", __func__, sound_period_sw, sound_period_fw)); + PHYDM_DBG(dm, DBG_TXBF, "[%s]sound_period_sw=%d, sound_period_fw=%d\n", + __func__, sound_period_sw, sound_period_fw); for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_beamform_entry = p_beam_info->beamformee_entry + idx; + beamform_entry = beam_info->beamformee_entry + idx; - if (p_beamform_entry->default_csi_cnt > 20) { - /*Modified by David*/ + if (beamform_entry->default_csi_cnt > 20) { + /*@Modified by David*/ sound_period_sw = 4000; sound_period_fw = 400; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] period = %d\n", __func__, sound_period_sw)); - if (p_beamform_entry->beamform_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { - if (p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER) { - if (p_beamform_entry->sound_period != sound_period_fw) { - p_beamform_entry->sound_period = sound_period_fw; - is_change_period = true; /*Only FW sounding need to send H2C packet to change sound period. */ - } - } else if (p_beamform_entry->sound_period != sound_period_sw) - p_beamform_entry->sound_period = sound_period_sw; - } + PHYDM_DBG(dm, DBG_TXBF, "[%s] period = %d\n", __func__, + sound_period_sw); + if ((beamform_entry->beamform_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) == 0) + continue; + + if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER) { + if (beamform_entry->sound_period != sound_period_fw) { + beamform_entry->sound_period = sound_period_fw; + is_change_period = true; /*Only FW sounding need to send H2C packet to change sound period. */ + } + } else if (beamform_entry->sound_period != sound_period_sw) + beamform_entry->sound_period = sound_period_sw; } if (is_change_period) - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); } - - - boolean beamforming_send_ht_ndpa_packet( - void *p_dm_void, - u8 *RA, - CHANNEL_WIDTH BW, - u8 q_idx -) + void *dm_void, + u8 *RA, + enum channel_width BW, + u8 q_idx) { - boolean ret = true; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + boolean ret = true; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (q_idx == BEACON_QUEUE) - ret = send_fw_ht_ndpa_packet(p_dm_odm, RA, BW); + ret = send_fw_ht_ndpa_packet(dm, RA, BW); else - ret = send_sw_ht_ndpa_packet(p_dm_odm, RA, BW); + ret = send_sw_ht_ndpa_packet(dm, RA, BW); return ret; } - - boolean beamforming_send_vht_ndpa_packet( - void *p_dm_void, - u8 *RA, - u16 AID, - CHANNEL_WIDTH BW, - u8 q_idx -) + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW, + u8 q_idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - boolean ret = true; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + boolean ret = true; - hal_com_txbf_set(p_dm_odm, TXBF_SET_GET_TX_RATE, NULL); + hal_com_txbf_set(dm, TXBF_SET_GET_TX_RATE, NULL); - if ((p_dm_odm->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7) && (p_dm_odm->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9) && (p_beam_info->snding3ss == false)) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: 3SS VHT 789 don't sounding\n", __func__)); + if (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss) + PHYDM_DBG(dm, DBG_TXBF, "@%s: 3SS VHT 789 don't sounding\n", + __func__); - else { + else { if (q_idx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */ - ret = send_fw_vht_ndpa_packet(p_dm_odm, RA, AID, BW); + ret = send_fw_vht_ndpa_packet(dm, RA, AID, BW); else { #ifdef SUPPORT_MU_BF #if (SUPPORT_MU_BF == 1) - p_beam_info->is_mu_sounding = true; - ret = send_sw_vht_mu_ndpa_packet(p_dm_odm, BW); + beam_info->is_mu_sounding = true; + ret = send_sw_vht_mu_ndpa_packet(dm, BW); #else - p_beam_info->is_mu_sounding = false; - ret = send_sw_vht_ndpa_packet(p_dm_odm, RA, AID, BW); + beam_info->is_mu_sounding = false; + ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW); #endif #else - p_beam_info->is_mu_sounding = false; - ret = send_sw_vht_ndpa_packet(p_dm_odm, RA, AID, BW); + beam_info->is_mu_sounding = false; + ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW); #endif } } return ret; } - enum beamforming_notify_state phydm_beamfomring_is_sounding( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info, - u8 *idx -) + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, + u8 *idx) { - enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE; - struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - /*if(( Beamforming_GetBeamCap(p_beam_info) & BEAMFORMER_CAP) == 0)*/ - /*is_sounding = BEAMFORMING_NOTIFY_RESET;*/ - if (beam_oid_info.sound_oid_mode == sounding_stop_all_timer) + /*@if(( Beamforming_GetBeamCap(beam_info) & BEAMFORMER_CAP) == 0)*/ + /*@is_sounding = BEAMFORMING_NOTIFY_RESET;*/ + if (beam_oid_info.sound_oid_mode == sounding_stop_all_timer) { is_sounding = BEAMFORMING_NOTIFY_RESET; - else { - u8 i; + goto out; + } - for (i = 0 ; i < BEAMFORMEE_ENTRY_NUM ; i++) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: BFee Entry %d is_used=%d, is_sound=%d\n", __func__, i, p_beam_info->beamformee_entry[i].is_used, p_beam_info->beamformee_entry[i].is_sound)); - if (p_beam_info->beamformee_entry[i].is_used && (!p_beam_info->beamformee_entry[i].is_sound)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Add BFee entry %d\n", __func__, i)); - *idx = i; - if (p_beam_info->beamformee_entry[i].is_mu_sta) - is_sounding = BEAMFORMEE_NOTIFY_ADD_MU; - else - is_sounding = BEAMFORMEE_NOTIFY_ADD_SU; - } + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + PHYDM_DBG(dm, DBG_TXBF, + "@%s: BFee Entry %d is_used=%d, is_sound=%d\n", + __func__, i, beam_info->beamformee_entry[i].is_used, + beam_info->beamformee_entry[i].is_sound); + if (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) { + PHYDM_DBG(dm, DBG_TXBF, "%s: Add BFee entry %d\n", + __func__, i); + *idx = i; + if (beam_info->beamformee_entry[i].is_mu_sta) + is_sounding = BEAMFORMEE_NOTIFY_ADD_MU; + else + is_sounding = BEAMFORMEE_NOTIFY_ADD_SU; + } - if ((!p_beam_info->beamformee_entry[i].is_used) && p_beam_info->beamformee_entry[i].is_sound) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Delete BFee entry %d\n", __func__, i)); - *idx = i; - if (p_beam_info->beamformee_entry[i].is_mu_sta) - is_sounding = BEAMFORMEE_NOTIFY_DELETE_MU; - else - is_sounding = BEAMFORMEE_NOTIFY_DELETE_SU; - } + if (!beam_info->beamformee_entry[i].is_used && beam_info->beamformee_entry[i].is_sound) { + PHYDM_DBG(dm, DBG_TXBF, "%s: Delete BFee entry %d\n", + __func__, i); + *idx = i; + if (beam_info->beamformee_entry[i].is_mu_sta) + is_sounding = BEAMFORMEE_NOTIFY_DELETE_MU; + else + is_sounding = BEAMFORMEE_NOTIFY_DELETE_SU; } } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, is_sounding = %d\n", __func__, is_sounding)); +out: + PHYDM_DBG(dm, DBG_TXBF, "%s End, is_sounding = %d\n", __func__, + is_sounding); return is_sounding; } - /* This function is unused */ -u8 -phydm_beamforming_sounding_idx( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info -) +u8 phydm_beamforming_sounding_idx( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info) { - u8 idx = 0; - struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 idx = 0; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) idx = beam_oid_info.sound_oid_idx; else { - u8 i; + u8 i; for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - if (p_beam_info->beamformee_entry[i].is_used && (false == p_beam_info->beamformee_entry[i].is_sound)) { + if (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) { idx = i; break; } @@ -684,20 +732,18 @@ phydm_beamforming_sounding_idx( return idx; } - enum sounding_mode phydm_beamforming_sounding_mode( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info, - u8 idx -) + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 support_interface = p_dm_odm->support_interface; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 support_interface = dm->support_interface; - struct _RT_BEAMFORMEE_ENTRY beam_entry = p_beam_info->beamformee_entry[idx]; - struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; - enum sounding_mode mode = beam_oid_info.sound_oid_mode; + struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + enum sounding_mode mode = beam_oid_info.sound_oid_mode; if (beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) { if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) @@ -710,103 +756,100 @@ phydm_beamforming_sounding_mode( else mode = sounding_stop_all_timer; } else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) { - if ((support_interface == ODM_ITRF_USB) && !(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) + if (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) mode = SOUNDING_FW_VHT_TIMER; else mode = SOUNDING_SW_VHT_TIMER; } else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) { - if ((support_interface == ODM_ITRF_USB) && !(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) + if (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) mode = SOUNDING_FW_HT_TIMER; else mode = SOUNDING_SW_HT_TIMER; } else mode = sounding_stop_all_timer; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] support_interface=%d, mode=%d\n", __func__, support_interface, mode)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] support_interface=%d, mode=%d\n", + __func__, support_interface, mode); return mode; } - -u16 -phydm_beamforming_sounding_time( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info, - enum sounding_mode mode, - u8 idx -) +u16 phydm_beamforming_sounding_time( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, + enum sounding_mode mode, + u8 idx) { - u16 sounding_time = 0xffff; - struct _RT_BEAMFORMEE_ENTRY beam_entry = p_beam_info->beamformee_entry[idx]; - struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u16 sounding_time = 0xffff; + struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER) sounding_time = beam_oid_info.sound_oid_period * 32; else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER) - /*Modified by David*/ - sounding_time = beam_entry.sound_period; /*beam_oid_info.sound_oid_period;*/ + /*@Modified by David*/ + sounding_time = beam_entry.sound_period; /*@beam_oid_info.sound_oid_period;*/ else sounding_time = beam_entry.sound_period; return sounding_time; } - -CHANNEL_WIDTH +enum channel_width phydm_beamforming_sounding_bw( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info, - enum sounding_mode mode, - u8 idx -) + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, + enum sounding_mode mode, + u8 idx) { - CHANNEL_WIDTH sounding_bw = CHANNEL_WIDTH_20; - struct _RT_BEAMFORMEE_ENTRY beam_entry = p_beam_info->beamformee_entry[idx]; - struct _RT_BEAMFORMING_OID_INFO beam_oid_info = p_beam_info->beamforming_oid_info; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + enum channel_width sounding_bw = CHANNEL_WIDTH_20; + struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER) sounding_bw = beam_oid_info.sound_oid_bw; else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER) - /*Modified by David*/ - sounding_bw = beam_entry.sound_bw; /*beam_oid_info.sound_oid_bw;*/ + /*@Modified by David*/ + sounding_bw = beam_entry.sound_bw; /*@beam_oid_info.sound_oid_bw;*/ else sounding_bw = beam_entry.sound_bw; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, sounding_bw=0x%X\n", __func__, sounding_bw)); + PHYDM_DBG(dm, DBG_TXBF, "%s, sounding_bw=0x%X\n", __func__, + sounding_bw); return sounding_bw; } - boolean phydm_beamforming_select_beam_entry( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info -) + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info) { - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; - /*p_entry.is_sound is different between first and latter NDPA, and should not be used as BFee entry selection*/ - /*BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed sound_idx.*/ - p_sound_info->sound_idx = phydm_beamforming_sounding_idx(p_dm_odm, p_beam_info); - /*p_sound_info->sound_idx = 0;*/ + /*@entry.is_sound is different between first and latter NDPA, and should not be used as BFee entry selection*/ + /*@BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed sound_idx.*/ + sound_info->sound_idx = phydm_beamforming_sounding_idx(dm, beam_info); + /*sound_info->sound_idx = 0;*/ - if (p_sound_info->sound_idx < BEAMFORMEE_ENTRY_NUM) - p_sound_info->sound_mode = phydm_beamforming_sounding_mode(p_dm_odm, p_beam_info, p_sound_info->sound_idx); + if (sound_info->sound_idx < BEAMFORMEE_ENTRY_NUM) + sound_info->sound_mode = phydm_beamforming_sounding_mode(dm, beam_info, sound_info->sound_idx); else - p_sound_info->sound_mode = sounding_stop_all_timer; + sound_info->sound_mode = sounding_stop_all_timer; - if (sounding_stop_all_timer == p_sound_info->sound_mode) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Return because of sounding_stop_all_timer\n", __func__)); + if (sounding_stop_all_timer == sound_info->sound_mode) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s] Return because of sounding_stop_all_timer\n", + __func__); return false; } else { - p_sound_info->sound_bw = phydm_beamforming_sounding_bw(p_dm_odm, p_beam_info, p_sound_info->sound_mode, p_sound_info->sound_idx); - p_sound_info->sound_period = phydm_beamforming_sounding_time(p_dm_odm, p_beam_info, p_sound_info->sound_mode, p_sound_info->sound_idx); + sound_info->sound_bw = phydm_beamforming_sounding_bw(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx); + sound_info->sound_period = phydm_beamforming_sounding_time(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx); return true; } } @@ -814,182 +857,184 @@ phydm_beamforming_select_beam_entry( /*SU BFee Entry Only*/ boolean phydm_beamforming_start_period( - void *p_dm_void -) + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - boolean ret = true; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = true; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; - phydm_beamforming_dym_ndpa_rate(p_dm_odm); + phydm_beamforming_dym_ndpa_rate(dm); - phydm_beamforming_select_beam_entry(p_dm_odm, p_beam_info); /* Modified */ + phydm_beamforming_select_beam_entry(dm, beam_info); /* @Modified */ - if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) - odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, p_sound_info->sound_period); - else if (p_sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_HW_HT_TIMER || - p_sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) { + if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period); + else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER || + sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) { HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF; - u32 val = (p_sound_info->sound_period | (timer_type << 16)); - - /* HW timer stop: All IC has the same setting */ - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); - /* odm_write_1byte(p_dm_odm, 0x15F, 0); */ - /* HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes */ - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_INIT, (u8 *)(&val)); - /* odm_write_1byte(p_dm_odm, 0x164, 1); */ - /* odm_write_4byte(p_dm_odm, 0x15C, val); */ - /* HW timer start: All IC has the same setting */ - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_START, (u8 *)(&timer_type)); - /* odm_write_1byte(p_dm_odm, 0x15F, 0x5); */ - } else if (p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER) - ret = beamforming_start_fw(p_dm_odm, p_sound_info->sound_idx); + u32 val = (sound_info->sound_period | (timer_type << 16)); + + /* @HW timer stop: All IC has the same setting */ + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); + /* odm_write_1byte(dm, 0x15F, 0); */ + /* @HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes */ + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_INIT, (u8 *)(&val)); + /* odm_write_1byte(dm, 0x164, 1); */ + /* odm_write_4byte(dm, 0x15C, val); */ + /* @HW timer start: All IC has the same setting */ + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_START, (u8 *)(&timer_type)); + /* odm_write_1byte(dm, 0x15F, 0x5); */ + } else if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER) + ret = beamforming_start_fw(dm, sound_info->sound_idx); else ret = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] sound_idx=%d, sound_mode=%d, sound_bw=%d, sound_period=%d\n", __func__, - p_sound_info->sound_idx, p_sound_info->sound_mode, p_sound_info->sound_bw, p_sound_info->sound_period)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] sound_idx=%d, sound_mode=%d, sound_bw=%d, sound_period=%d\n", + __func__, sound_info->sound_idx, sound_info->sound_mode, + sound_info->sound_bw, sound_info->sound_period); return ret; } /* Used after beamforming_leave, and will clear the setting of the "already deleted" entry *SU BFee Entry Only*/ -void -phydm_beamforming_end_period_sw( - void *p_dm_void -) +void phydm_beamforming_end_period_sw( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + /*void *adapter = dm->adapter;*/ + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) - odm_cancel_timer(p_dm_odm, &p_beam_info->beamforming_timer); - else if (p_sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_HW_HT_TIMER || - p_sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) - /*HW timer stop: All IC has the same setting*/ - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); - /*odm_write_1byte(p_dm_odm, 0x15F, 0);*/ + if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_cancel_timer(dm, &beam_info->beamforming_timer); + else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER || + sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) + /*@HW timer stop: All IC has the same setting*/ + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); + /*odm_write_1byte(dm, 0x15F, 0);*/ } -void -phydm_beamforming_end_period_fw( - void *p_dm_void -) +void phydm_beamforming_end_period_fw( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 idx = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx = 0; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]\n", __func__)); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); + PHYDM_DBG(dm, DBG_TXBF, "[%s]\n", __func__); } - /*SU BFee Entry Only*/ -void -phydm_beamforming_clear_entry_sw( - void *p_dm_void, - boolean is_delete, - u8 delete_idx -) +void phydm_beamforming_clear_entry_sw( + void *dm_void, + boolean is_delete, + u8 delete_idx) { - u8 idx = 0; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; if (is_delete) { if (delete_idx < BEAMFORMEE_ENTRY_NUM) { - p_beamform_entry = p_beam_info->beamformee_entry + delete_idx; - if (!((!p_beamform_entry->is_used) && p_beamform_entry->is_sound)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW delete_idx is wrong!!!!!\n", __func__)); + beamform_entry = beam_info->beamformee_entry + delete_idx; + if (!(!beamform_entry->is_used && beamform_entry->is_sound)) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s] SW delete_idx is wrong!!!!!\n", + __func__); return; } } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW delete BFee entry %d\n", __func__, delete_idx)); - if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) { - p_beamform_entry->is_beamforming_in_progress = false; - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - } else if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&delete_idx); + PHYDM_DBG(dm, DBG_TXBF, "[%s] SW delete BFee entry %d\n", + __func__, delete_idx); + if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) { + beamform_entry->is_beamforming_in_progress = false; + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + } else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&delete_idx); } - p_beamform_entry->is_sound = false; - } else { - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_beamform_entry = p_beam_info->beamformee_entry + idx; - - /*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ - /*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/ - /*However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/ - - if (p_beamform_entry->is_sound) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW reset BFee entry %d\n", __func__, idx)); - /* - * If End procedure is - * 1. Between (Send NDPA, C2H packet return), reset state to initialized. - * After C2H packet return , status bit will be set to zero. - * - * 2. After C2H packet, then reset state to initialized and clear status bit. - */ - - if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) - phydm_beamforming_end_sw(p_dm_odm, 0); - else if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); - } + beamform_entry->is_sound = false; + return; + } - p_beamform_entry->is_sound = false; - } + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + beamform_entry = beam_info->beamformee_entry + idx; + + /*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ + /*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/ + /*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/ + + if (!beamform_entry->is_sound) + continue; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] SW reset BFee entry %d\n", + __func__, idx); + /*@ + * If End procedure is + * 1. Between (Send NDPA, C2H packet return), reset state to initialized. + * After C2H packet return , status bit will be set to zero. + * + * 2. After C2H packet, then reset state to initialized and clear status bit. + */ + + if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + phydm_beamforming_end_sw(dm, 0); + else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); } + + beamform_entry->is_sound = false; } } -void -phydm_beamforming_clear_entry_fw( - void *p_dm_void, - boolean is_delete, - u8 delete_idx -) +void phydm_beamforming_clear_entry_fw( + void *dm_void, + boolean is_delete, + u8 delete_idx) { - u8 idx = 0; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; if (is_delete) { if (delete_idx < BEAMFORMEE_ENTRY_NUM) { - p_beamform_entry = p_beam_info->beamformee_entry + delete_idx; + beamform_entry = beam_info->beamformee_entry + delete_idx; - if (!((!p_beamform_entry->is_used) && p_beamform_entry->is_sound)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] FW delete_idx is wrong!!!!!\n", __func__)); + if (!(!beamform_entry->is_used && beamform_entry->is_sound)) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s] FW delete_idx is wrong!!!!!\n", + __func__); return; } } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: FW delete BFee entry %d\n", __func__, delete_idx)); - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; - p_beamform_entry->is_sound = false; + PHYDM_DBG(dm, DBG_TXBF, "%s: FW delete BFee entry %d\n", + __func__, delete_idx); + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + beamform_entry->is_sound = false; } else { for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_beamform_entry = p_beam_info->beamformee_entry + idx; + beamform_entry = beam_info->beamformee_entry + idx; /*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ /*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/ - /*However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/ + /*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/ - if (p_beamform_entry->is_sound) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]FW reset BFee entry %d\n", __func__, idx)); - /* + if (beamform_entry->is_sound) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s]FW reset BFee entry %d\n", + __func__, idx); + /*@ * If End procedure is * 1. Between (Send NDPA, C2H packet return), reset state to initialized. * After C2H packet return , status bit will be set to zero. @@ -997,88 +1042,97 @@ phydm_beamforming_clear_entry_fw( * 2. After C2H packet, then reset state to initialized and clear status bit. */ - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - p_beamform_entry->is_sound = false; + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + beamform_entry->is_sound = false; } } } } -/* +/*@ * Called : * 1. Add and delete entry : beamforming_enter/beamforming_leave * 2. FW trigger : Beamforming_SetTxBFen * 3. Set OID_RT_BEAMFORMING_PERIOD : beamforming_control_v2 */ -void -phydm_beamforming_notify( - void *p_dm_void -) +void phydm_beamforming_notify( + void *dm_void) { - u8 idx = BEAMFORMEE_ENTRY_NUM; - enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + u8 idx = BEAMFORMEE_ENTRY_NUM; + enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; - is_sounding = phydm_beamfomring_is_sounding(p_dm_odm, p_beam_info, &idx); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Before notify, is_sounding=%d, idx=%d\n", __func__, is_sounding, idx)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: p_beam_info->beamformee_su_cnt = %d\n", __func__, p_beam_info->beamformee_su_cnt)); + is_sounding = phydm_beamfomring_is_sounding(dm, beam_info, &idx); + PHYDM_DBG(dm, DBG_TXBF, "%s, Before notify, is_sounding=%d, idx=%d\n", + __func__, is_sounding, idx); + PHYDM_DBG(dm, DBG_TXBF, "%s: beam_info->beamformee_su_cnt = %d\n", + __func__, beam_info->beamformee_su_cnt); switch (is_sounding) { case BEAMFORMEE_NOTIFY_ADD_SU: - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_SU\n", __func__)); - phydm_beamforming_start_period(p_dm_odm); + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_SU\n", + __func__); + phydm_beamforming_start_period(dm); break; case BEAMFORMEE_NOTIFY_DELETE_SU: - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_SU\n", __func__)); - if (p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { - phydm_beamforming_clear_entry_fw(p_dm_odm, true, idx); - if (p_beam_info->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ - phydm_beamforming_end_period_fw(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_SU\n", + __func__); + if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_clear_entry_fw(dm, true, idx); + if (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_end_period_fw(dm); + PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n", + __func__); } } else { - phydm_beamforming_clear_entry_sw(p_dm_odm, true, idx); - if (p_beam_info->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ - phydm_beamforming_end_period_sw(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); + phydm_beamforming_clear_entry_sw(dm, true, idx); + if (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_end_period_sw(dm); + PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n", + __func__); } } break; case BEAMFORMEE_NOTIFY_ADD_MU: - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_MU\n", __func__)); - if (p_beam_info->beamformee_mu_cnt == 2) { - /*if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) - odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, p_sound_info->sound_period);*/ - odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, 1000); /*Do MU sounding every 1sec*/ + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_MU\n", + __func__); + if (beam_info->beamformee_mu_cnt == 2) { + /*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);*/ + odm_set_timer(dm, &beam_info->beamforming_timer, 1000); /*@Do MU sounding every 1sec*/ } else - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less or larger than 2 MU STAs, not to set timer\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, + "%s: Less or larger than 2 MU STAs, not to set timer\n", + __func__); break; case BEAMFORMEE_NOTIFY_DELETE_MU: - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_MU\n", __func__)); - if (p_beam_info->beamformee_mu_cnt == 1) { - /*if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER)*/{ - odm_cancel_timer(p_dm_odm, &p_beam_info->beamforming_timer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less than 2 MU STAs, stop sounding\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_MU\n", + __func__); + if (beam_info->beamformee_mu_cnt == 1) { + /*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)*/ { + odm_cancel_timer(dm, &beam_info->beamforming_timer); + PHYDM_DBG(dm, DBG_TXBF, + "%s: Less than 2 MU STAs, stop sounding\n", + __func__); } } break; case BEAMFORMING_NOTIFY_RESET: - if (p_sound_info->sound_mode == SOUNDING_FW_HT_TIMER || p_sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { - phydm_beamforming_clear_entry_fw(p_dm_odm, false, idx); - phydm_beamforming_end_period_fw(p_dm_odm); + if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_clear_entry_fw(dm, false, idx); + phydm_beamforming_end_period_fw(dm); } else { - phydm_beamforming_clear_entry_sw(p_dm_odm, false, idx); - phydm_beamforming_end_period_sw(p_dm_odm); + phydm_beamforming_clear_entry_sw(dm, false, idx); + phydm_beamforming_end_period_sw(dm); } break; @@ -1086,597 +1140,640 @@ phydm_beamforming_notify( default: break; } - } - - boolean beamforming_init_entry( - void *p_dm_void, - u16 sta_idx, - u8 *bfer_bfee_idx -) + void *dm_void, + u16 sta_idx, + u8 *bfer_bfee_idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; - struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry = NULL; - struct _RT_BEAMFORM_STAINFO *p_sta = NULL; - enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; - u8 bfer_idx = 0xF, bfee_idx = 0xF; - u8 num_of_sounding_dim = 0, comp_steering_num_of_bfer = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx]; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; + struct _RT_BEAMFORM_STAINFO *sta = NULL; + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; + u8 bfer_idx = 0xF, bfee_idx = 0xF; + u8 num_of_sounding_dim = 0, comp_steering_num_of_bfer = 0; + + if (!is_sta_active(cmn_sta)) { + PHYDM_DBG(dm, DBG_TXBF, "%s => sta_info(mac_id:%d) failed\n", + __func__, sta_idx); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_warn_on(1); + #endif + return false; + } - p_sta = phydm_sta_info_init(p_dm_odm, sta_idx); + sta = phydm_sta_info_init(dm, sta_idx); /*The current setting does not support Beaforming*/ - if (BEAMFORMING_CAP_NONE == p_sta->ht_beamform_cap && BEAMFORMING_CAP_NONE == p_sta->vht_beamform_cap) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("The configuration disabled Beamforming! Skip...\n")); + if (BEAMFORMING_CAP_NONE == sta->ht_beamform_cap && BEAMFORMING_CAP_NONE == sta->vht_beamform_cap) { + PHYDM_DBG(dm, DBG_TXBF, + "The configuration disabled Beamforming! Skip...\n"); return false; } - if (p_sta->wireless_mode < WIRELESS_MODE_N_24G) + if (!(cmn_sta->support_wireless_set & (WIRELESS_VHT | WIRELESS_HT))) return false; else { - if (p_sta->wireless_mode & WIRELESS_MODE_N_5G || p_sta->wireless_mode & WIRELESS_MODE_N_24G) {/*HT*/ - if (TEST_FLAG(p_sta->cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {/*We are Beamformee because the STA is Beamformer*/ + if (cmn_sta->support_wireless_set & WIRELESS_HT) { /*@HT*/ + if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { /*We are Beamformee because the STA is Beamformer*/ beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_HT_EXPLICIT); - num_of_sounding_dim = (p_sta->cur_beamform & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6; + num_of_sounding_dim = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6; } /*We are Beamformer because the STA is Beamformee*/ - if (TEST_FLAG(p_sta->cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) || - TEST_FLAG(p_sta->ht_beamform_cap, BEAMFORMING_HT_BEAMFORMER_TEST)) { + if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) || + TEST_FLAG(sta->ht_beamform_cap, BEAMFORMING_HT_BEAMFORMER_TEST)) { beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT); - comp_steering_num_of_bfer = (p_sta->cur_beamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4; + comp_steering_num_of_bfer = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT cur_beamform=0x%X, beamform_cap=0x%X\n", __func__, p_sta->cur_beamform, beamform_cap)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT num_of_sounding_dim=%d, comp_steering_num_of_bfer=%d\n", __func__, num_of_sounding_dim, comp_steering_num_of_bfer)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] HT cur_beamform=0x%X, beamform_cap=0x%X\n", + __func__, sta->cur_beamform, beamform_cap); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] HT num_of_sounding_dim=%d, comp_steering_num_of_bfer=%d\n", + __func__, num_of_sounding_dim, + comp_steering_num_of_bfer); } #if (ODM_IC_11AC_SERIES_SUPPORT == 1) - if (p_sta->wireless_mode & WIRELESS_MODE_AC_5G || p_sta->wireless_mode & WIRELESS_MODE_AC_24G) { /*VHT*/ + if (cmn_sta->support_wireless_set & WIRELESS_VHT) { /*VHT*/ /* We are Beamformee because the STA is SU Beamformer*/ - if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_SU); - num_of_sounding_dim = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; + num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; } /* We are Beamformer because the STA is SU Beamformee*/ - if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) || - TEST_FLAG(p_sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) || + TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_SU); - comp_steering_num_of_bfer = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; + comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; } /* We are Beamformee because the STA is MU Beamformer*/ - if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_MU); - num_of_sounding_dim = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; + num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; } /* We are Beamformer because the STA is MU Beamformee*/ - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) { /* Only AP mode supports to act an MU beamformer */ - if (TEST_FLAG(p_sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) || - TEST_FLAG(p_sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + if (phydm_acting_determine(dm, phydm_acting_as_ap)) { /* Only AP mode supports to act an MU beamformer */ + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) || + TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_MU); - comp_steering_num_of_bfer = (p_sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; + comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; } } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT cur_beamform_vht=0x%X, beamform_cap=0x%X\n", __func__, p_sta->cur_beamform_vht, beamform_cap)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT num_of_sounding_dim=0x%X, comp_steering_num_of_bfer=0x%X\n", __func__, num_of_sounding_dim, comp_steering_num_of_bfer)); - + PHYDM_DBG(dm, DBG_TXBF, + "[%s]VHT cur_beamform_vht=0x%X, beamform_cap=0x%X\n", + __func__, sta->cur_beamform_vht, + beamform_cap); + PHYDM_DBG(dm, DBG_TXBF, + "[%s]VHT num_of_sounding_dim=0x%X, comp_steering_num_of_bfer=0x%X\n", + __func__, num_of_sounding_dim, + comp_steering_num_of_bfer); } #endif } - if (beamform_cap == BEAMFORMING_CAP_NONE) return false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Self BF Entry Cap = 0x%02X\n", __func__, beamform_cap)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Self BF Entry Cap = 0x%02X\n", __func__, + beamform_cap); /*We are BFee, so the entry is BFer*/ if (beamform_cap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { - p_beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, p_sta->ra, &bfer_idx); - - if (p_beamformer_entry == NULL) { - p_beamformer_entry = beamforming_add_bfer_entry(p_dm_odm, p_sta, beamform_cap, num_of_sounding_dim, &bfer_idx); - if (p_beamformer_entry == NULL) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Not enough BFer entry!!!!!\n", __func__)); + beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, sta->ra, &bfer_idx); + + if (beamformer_entry == NULL) { + beamformer_entry = beamforming_add_bfer_entry(dm, sta, beamform_cap, num_of_sounding_dim, &bfer_idx); + if (beamformer_entry == NULL) + PHYDM_DBG(dm, DBG_TXBF, + "[%s]Not enough BFer entry!!!!!\n", + __func__); } } /*We are BFer, so the entry is BFee*/ if (beamform_cap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { - p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, p_sta->ra, &bfee_idx); + beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, sta->ra, &bfee_idx); - /*¦pªGBFeeIdx = 0xF «h¥Nªí¥Ø«eentry·í¤¤¨S¦³¬Û¦PªºMACID¦b¤º*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BFee entry 0x%X by address\n", __func__, bfee_idx)); - if (p_beamform_entry == NULL) { - p_beamform_entry = beamforming_add_bfee_entry(p_dm_odm, p_sta, beamform_cap, num_of_sounding_dim, comp_steering_num_of_bfer, &bfee_idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: p_sta->AID=%d, p_sta->mac_id=%d\n", __func__, p_sta->aid, p_sta->mac_id)); + /*@if BFeeIdx = 0xF, that represent for no matched MACID among all linked entrys */ + PHYDM_DBG(dm, DBG_TXBF, "[%s] Get BFee entry 0x%X by address\n", + __func__, bfee_idx); + if (beamform_entry == NULL) { + beamform_entry = beamforming_add_bfee_entry(dm, sta, beamform_cap, num_of_sounding_dim, comp_steering_num_of_bfer, &bfee_idx); + PHYDM_DBG(dm, DBG_TXBF, + "[%s]: sta->AID=%d, sta->mac_id=%d\n", + __func__, sta->aid, sta->mac_id); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: Add BFee entry %d\n", __func__, bfee_idx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s]: Add BFee entry %d\n", + __func__, bfee_idx); - if (p_beamform_entry == NULL) + if (beamform_entry == NULL) return false; else - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; } else { - /*Entry has been created. If entry is initialing or progressing then errors occur.*/ - if (p_beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && - p_beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) + /*@Entry has been created. If entry is initialing or progressing then errors occur.*/ + if (beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && + beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) return false; else - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; } - p_beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - phydm_sta_info_update(p_dm_odm, sta_idx, p_beamform_entry); + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + phydm_sta_info_update(dm, sta_idx, beamform_entry); } *bfer_bfee_idx = (bfer_idx << 4) | bfee_idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End: bfer_idx=0x%X, bfee_idx=0x%X, bfer_bfee_idx=0x%X\n", __func__, bfer_idx, bfee_idx, *bfer_bfee_idx)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] End: bfer_idx=0x%X, bfee_idx=0x%X, bfer_bfee_idx=0x%X\n", + __func__, bfer_idx, bfee_idx, *bfer_bfee_idx); return true; } - -void -beamforming_deinit_entry( - void *p_dm_void, - u8 *RA -) +void beamforming_deinit_entry( + void *dm_void, + u8 *RA) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 idx = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx = 0; - struct _RT_BEAMFORMER_ENTRY *p_bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, RA, &idx); - struct _RT_BEAMFORMEE_ENTRY *p_bfee_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct _RT_BEAMFORMER_ENTRY *bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, &idx); + struct _RT_BEAMFORMEE_ENTRY *bfee_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); boolean ret = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - if (p_bfee_entry != NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, p_bfee_entry\n", __func__)); - p_bfee_entry->is_used = false; - p_bfee_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; - p_bfee_entry->is_beamforming_in_progress = false; - if (p_bfee_entry->is_mu_sta) { - p_dm_odm->beamforming_info.beamformee_mu_cnt -= 1; - p_dm_odm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(p_dm_odm); + if (bfee_entry != NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s, bfee_entry\n", __func__); + bfee_entry->is_used = false; + bfee_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + bfee_entry->is_beamforming_in_progress = false; + if (bfee_entry->is_mu_sta) { + dm->beamforming_info.beamformee_mu_cnt -= 1; + dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm); } else - p_dm_odm->beamforming_info.beamformee_su_cnt -= 1; + dm->beamforming_info.beamformee_su_cnt -= 1; ret = true; } - if (p_bfer_entry != NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, p_bfer_entry\n", __func__)); - p_bfer_entry->is_used = false; - p_bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; - if (p_bfer_entry->is_mu_ap) - p_dm_odm->beamforming_info.beamformer_mu_cnt -= 1; + if (bfer_entry != NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s, bfer_entry\n", __func__); + bfer_entry->is_used = false; + bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + if (bfer_entry->is_mu_ap) + dm->beamforming_info.beamformer_mu_cnt -= 1; else - p_dm_odm->beamforming_info.beamformer_su_cnt -= 1; + dm->beamforming_info.beamformer_su_cnt -= 1; ret = true; } if (ret == true) - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_LEAVE, (u8 *)&idx); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_LEAVE, (u8 *)&idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, idx = 0x%X\n", __func__, idx)); + PHYDM_DBG(dm, DBG_TXBF, "%s End, idx = 0x%X\n", __func__, idx); } - boolean beamforming_start_v1( - void *p_dm_void, - u8 *RA, - boolean mode, - CHANNEL_WIDTH BW, - u8 rate -) + void *dm_void, + u8 *RA, + boolean mode, + enum channel_width BW, + u8 rate) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 idx = 0; - struct _RT_BEAMFORMEE_ENTRY *p_entry; - boolean ret = true; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *entry; + boolean ret = true; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; - p_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); - if (p_entry->is_used == false) { - p_entry->is_beamforming_in_progress = false; + if (entry->is_used == false) { + entry->is_beamforming_in_progress = false; return false; } else { - if (p_entry->is_beamforming_in_progress) + if (entry->is_beamforming_in_progress) return false; - p_entry->is_beamforming_in_progress = true; + entry->is_beamforming_in_progress = true; if (mode == 1) { - if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { - p_entry->is_beamforming_in_progress = false; + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { + entry->is_beamforming_in_progress = false; return false; } } else if (mode == 0) { - if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { - p_entry->is_beamforming_in_progress = false; + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { + entry->is_beamforming_in_progress = false; return false; } } - if (p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { - p_entry->is_beamforming_in_progress = false; + if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + entry->is_beamforming_in_progress = false; return false; } else { - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; - p_entry->is_sound = true; + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + entry->is_sound = true; } } - p_entry->sound_bw = BW; - p_beam_info->beamformee_cur_idx = idx; - phydm_beamforming_ndpa_rate(p_dm_odm, BW, rate); - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); + entry->sound_bw = BW; + beam_info->beamformee_cur_idx = idx; + phydm_beamforming_ndpa_rate(dm, BW, rate); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); if (mode == 1) - ret = beamforming_send_ht_ndpa_packet(p_dm_odm, RA, BW, NORMAL_QUEUE); + ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE); else - ret = beamforming_send_vht_ndpa_packet(p_dm_odm, RA, p_entry->aid, BW, NORMAL_QUEUE); + ret = beamforming_send_vht_ndpa_packet(dm, RA, entry->aid, BW, NORMAL_QUEUE); if (ret == false) { - beamforming_leave(p_dm_odm, RA); - p_entry->is_beamforming_in_progress = false; + beamforming_leave(dm, RA); + entry->is_beamforming_in_progress = false; return false; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s idx %d\n", __func__, idx)); + PHYDM_DBG(dm, DBG_TXBF, "%s idx %d\n", __func__, idx); return true; } - boolean beamforming_start_sw( - void *p_dm_void, - u8 idx, - u8 mode, - CHANNEL_WIDTH BW -) + void *dm_void, + u8 idx, + u8 mode, + enum channel_width BW) { - u8 *ra = NULL; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMEE_ENTRY *p_entry; - boolean ret = true; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); + u8 *ra = NULL; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMEE_ENTRY *entry; + boolean ret = true; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; +#ifdef SUPPORT_MU_BF +#if (SUPPORT_MU_BF == 1) + u8 i, poll_sta_cnt = 0; + boolean is_get_first_bfee = false; +#endif +#endif - if (p_beam_info->is_mu_sounding) { - p_beam_info->is_mu_sounding_in_progress = true; - p_entry = &(p_beam_info->beamformee_entry[idx]); - ra = p_entry->mac_addr; + if (beam_info->is_mu_sounding) { + beam_info->is_mu_sounding_in_progress = true; + entry = &beam_info->beamformee_entry[idx]; + ra = entry->mac_addr; } else { - p_entry = &(p_beam_info->beamformee_entry[idx]); + entry = &beam_info->beamformee_entry[idx]; - if (p_entry->is_used == false) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for idx =%d\n", idx)); - p_entry->is_beamforming_in_progress = false; + if (entry->is_used == false) { + PHYDM_DBG(dm, DBG_TXBF, + "Skip Beamforming, no entry for idx =%d\n", + idx); + entry->is_beamforming_in_progress = false; return false; - } else { - if (p_entry->is_beamforming_in_progress) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("is_beamforming_in_progress, skip...\n")); - return false; - } + } + + if (entry->is_beamforming_in_progress) { + PHYDM_DBG(dm, DBG_TXBF, + "is_beamforming_in_progress, skip...\n"); + return false; + } - p_entry->is_beamforming_in_progress = true; - ra = p_entry->mac_addr; + entry->is_beamforming_in_progress = true; + ra = entry->mac_addr; - if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) { - if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { - p_entry->is_beamforming_in_progress = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n", __func__)); - return false; - } - } else if (mode == SOUNDING_SW_VHT_TIMER || mode == SOUNDING_HW_VHT_TIMER || mode == SOUNDING_AUTO_VHT_TIMER) { - if (!(p_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { - p_entry->is_beamforming_in_progress = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n", __func__)); - return false; - } + if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) { + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { + entry->is_beamforming_in_progress = false; + PHYDM_DBG(dm, DBG_TXBF, + "%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n", + __func__); + return false; } - if (p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { - p_entry->is_beamforming_in_progress = false; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by incorrect beamform_entry_state(%d) <==\n", __func__, p_entry->beamform_entry_state)); + } else if (mode == SOUNDING_SW_VHT_TIMER || mode == SOUNDING_HW_VHT_TIMER || mode == SOUNDING_AUTO_VHT_TIMER) { + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { + entry->is_beamforming_in_progress = false; + PHYDM_DBG(dm, DBG_TXBF, + "%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n", + __func__); return false; - } else { - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; - p_entry->is_sound = true; } } + if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + entry->is_beamforming_in_progress = false; + PHYDM_DBG(dm, DBG_TXBF, + "%s Return by incorrect beamform_entry_state(%d) <==\n", + __func__, entry->beamform_entry_state); + return false; + } else { + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + entry->is_sound = true; + } - p_beam_info->beamformee_cur_idx = idx; + beam_info->beamformee_cur_idx = idx; } - /*2014.12.22 Luke: Need to be checked*/ - /*GET_TXBF_INFO(adapter)->fTxbfSet(adapter, TXBF_SET_SOUNDING_STATUS, (u8*)&idx);*/ + /*@2014.12.22 Luke: Need to be checked*/ + /*@GET_TXBF_INFO(adapter)->fTxbfSet(adapter, TXBF_SET_SOUNDING_STATUS, (u8*)&idx);*/ if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) - ret = beamforming_send_ht_ndpa_packet(p_dm_odm, ra, BW, NORMAL_QUEUE); + ret = beamforming_send_ht_ndpa_packet(dm, ra, BW, NORMAL_QUEUE); else - ret = beamforming_send_vht_ndpa_packet(p_dm_odm, ra, p_entry->aid, BW, NORMAL_QUEUE); + ret = beamforming_send_vht_ndpa_packet(dm, ra, entry->aid, BW, NORMAL_QUEUE); if (ret == false) { - beamforming_leave(p_dm_odm, ra); - p_entry->is_beamforming_in_progress = false; + beamforming_leave(dm, ra); + entry->is_beamforming_in_progress = false; return false; } - - /*-------------------------- +/*@-------------------------- * Send BF Report Poll for MU BF --------------------------*/ #ifdef SUPPORT_MU_BF #if (SUPPORT_MU_BF == 1) - { - u8 idx, poll_sta_cnt = 0; - boolean is_get_first_bfee = false; - - if (p_beam_info->beamformee_mu_cnt > 1) { /* More than 1 MU STA*/ - - for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_entry = &(p_beam_info->beamformee_entry[idx]); - if (p_entry->is_mu_sta) { - if (is_get_first_bfee) { - poll_sta_cnt++; - if (poll_sta_cnt == (p_beam_info->beamformee_mu_cnt - 1))/* The last STA*/ - send_sw_vht_bf_report_poll(p_dm_odm, p_entry->mac_addr, true); - else - send_sw_vht_bf_report_poll(p_dm_odm, p_entry->mac_addr, false); - } else - is_get_first_bfee = true; - } - } + if (beam_info->beamformee_mu_cnt <= 1) + goto out; + + /* @More than 1 MU STA*/ + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + entry = &beam_info->beamformee_entry[i]; + if (!entry->is_mu_sta) + continue; + + if (!is_get_first_bfee) { + is_get_first_bfee = true; + continue; } + + poll_sta_cnt++; + if (poll_sta_cnt == (beam_info->beamformee_mu_cnt - 1)) /* The last STA*/ + send_sw_vht_bf_report_poll(dm, entry->mac_addr, true); + else + send_sw_vht_bf_report_poll(dm, entry->mac_addr, false); } +out: #endif #endif return true; } - boolean beamforming_start_fw( - void *p_dm_void, - u8 idx -) + void *dm_void, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMEE_ENTRY *p_entry; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - - p_entry = &(p_beam_info->beamformee_entry[idx]); - if (p_entry->is_used == false) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for idx =%d\n", idx)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMEE_ENTRY *entry; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + entry = &beam_info->beamformee_entry[idx]; + if (entry->is_used == false) { + PHYDM_DBG(dm, DBG_TXBF, + "Skip Beamforming, no entry for idx =%d\n", idx); return false; } - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; - p_entry->is_sound = true; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + entry->is_sound = true; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, idx=0x%X\n", __func__, idx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] End, idx=0x%X\n", __func__, idx); return true; } -void -beamforming_check_sounding_success( - void *p_dm_void, - boolean status -) +void beamforming_check_sounding_success( + void *dm_void, + boolean status) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx]; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[David]@%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[David]@%s Start!\n", __func__); if (status == 1) { - if (p_entry->log_status_fail_cnt == 21) - beamforming_dym_period(p_dm_odm, status); - p_entry->log_status_fail_cnt = 0; - } else if (p_entry->log_status_fail_cnt <= 20) { - p_entry->log_status_fail_cnt++; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s log_status_fail_cnt %d\n", __func__, p_entry->log_status_fail_cnt)); + if (entry->log_status_fail_cnt == 21) + beamforming_dym_period(dm, status); + entry->log_status_fail_cnt = 0; + } else if (entry->log_status_fail_cnt <= 20) { + entry->log_status_fail_cnt++; + PHYDM_DBG(dm, DBG_TXBF, "%s log_status_fail_cnt %d\n", __func__, + entry->log_status_fail_cnt); } - if (p_entry->log_status_fail_cnt > 20) { - p_entry->log_status_fail_cnt = 21; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s log_status_fail_cnt > 20, Stop SOUNDING\n", __func__)); - beamforming_dym_period(p_dm_odm, status); + if (entry->log_status_fail_cnt > 20) { + entry->log_status_fail_cnt = 21; + PHYDM_DBG(dm, DBG_TXBF, + "%s log_status_fail_cnt > 20, Stop SOUNDING\n", + __func__); + beamforming_dym_period(dm, status); } } -void -phydm_beamforming_end_sw( - void *p_dm_void, - boolean status -) +void phydm_beamforming_end_sw( + void *dm_void, + boolean status) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); - - if (p_beam_info->is_mu_sounding) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: MU sounding done\n", __func__)); - p_beam_info->is_mu_sounding_in_progress = false; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&(p_beam_info->beamformee_cur_idx)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx]; + + if (beam_info->is_mu_sounding) { + PHYDM_DBG(dm, DBG_TXBF, "%s: MU sounding done\n", __func__); + beam_info->is_mu_sounding_in_progress = false; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, + (u8 *)&beam_info->beamformee_cur_idx); } else { - if (p_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSING) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamformStatus %d\n", __func__, p_entry->beamform_entry_state)); + if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSING) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] BeamformStatus %d\n", + __func__, entry->beamform_entry_state); return; } - if ((p_dm_odm->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7) && (p_dm_odm->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9) && (p_beam_info->snding3ss == false)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] VHT3SS 7,8,9, do not apply V matrix.\n", __func__)); - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&(p_beam_info->beamformee_cur_idx)); + if (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s] VHT3SS 7,8,9, do not apply V matrix.\n", + __func__); + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, + (u8 *)&beam_info->beamformee_cur_idx); } else if (status == 1) { - p_entry->log_status_fail_cnt = 0; - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_STATUS, (u8 *)&(p_beam_info->beamformee_cur_idx)); + entry->log_status_fail_cnt = 0; + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, + (u8 *)&beam_info->beamformee_cur_idx); } else { - p_entry->log_status_fail_cnt++; - p_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; - hal_com_txbf_set(p_dm_odm, TXBF_SET_TX_PATH_RESET, (u8 *)&(p_beam_info->beamformee_cur_idx)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] log_status_fail_cnt %d\n", __func__, p_entry->log_status_fail_cnt)); + entry->log_status_fail_cnt++; + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(dm, TXBF_SET_TX_PATH_RESET, + (u8 *)&beam_info->beamformee_cur_idx); + PHYDM_DBG(dm, DBG_TXBF, "[%s] log_status_fail_cnt %d\n", + __func__, entry->log_status_fail_cnt); } - if (p_entry->log_status_fail_cnt > 50) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s log_status_fail_cnt > 50, Stop SOUNDING\n", __func__)); - p_entry->is_sound = false; - beamforming_deinit_entry(p_dm_odm, p_entry->mac_addr); + if (entry->log_status_fail_cnt > 50) { + PHYDM_DBG(dm, DBG_TXBF, + "%s log_status_fail_cnt > 50, Stop SOUNDING\n", + __func__); + entry->is_sound = false; + beamforming_deinit_entry(dm, entry->mac_addr); - /*Modified by David - Every action of deleting entry should follow by Notify*/ - phydm_beamforming_notify(p_dm_odm); + /*@Modified by David - Every action of deleting entry should follow by Notify*/ + phydm_beamforming_notify(dm); } - p_entry->is_beamforming_in_progress = false; + entry->is_beamforming_in_progress = false; } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: status=%d\n", __func__, status)); + PHYDM_DBG(dm, DBG_TXBF, "%s: status=%d\n", __func__, status); } - -void -beamforming_timer_callback( +void beamforming_timer_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - void *p_dm_void + void *dm_void #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - void *p_context + void *context #endif -) + ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; + void *adapter = (void *)context; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->odmpriv; #endif - boolean ret = false; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); - struct _RT_SOUNDING_INFO *p_sound_info = &(p_beam_info->sounding_info); - boolean is_beamforming_in_progress; + boolean ret = false; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]); + struct _RT_SOUNDING_INFO *sound_info = &(beam_info->sounding_info); + boolean is_beamforming_in_progress; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - if (p_beam_info->is_mu_sounding) - is_beamforming_in_progress = p_beam_info->is_mu_sounding_in_progress; + if (beam_info->is_mu_sounding) + is_beamforming_in_progress = beam_info->is_mu_sounding_in_progress; else - is_beamforming_in_progress = p_entry->is_beamforming_in_progress; + is_beamforming_in_progress = entry->is_beamforming_in_progress; if (is_beamforming_in_progress) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("is_beamforming_in_progress, reset it\n")); - phydm_beamforming_end_sw(p_dm_odm, 0); + PHYDM_DBG(dm, DBG_TXBF, + "is_beamforming_in_progress, reset it\n"); + phydm_beamforming_end_sw(dm, 0); } - ret = phydm_beamforming_select_beam_entry(p_dm_odm, p_beam_info); + ret = phydm_beamforming_select_beam_entry(dm, beam_info); #if (SUPPORT_MU_BF == 1) - if (ret && p_beam_info->beamformee_mu_cnt > 1) + if (ret && beam_info->beamformee_mu_cnt > 1) ret = 1; else ret = 0; #endif if (ret) - ret = beamforming_start_sw(p_dm_odm, p_sound_info->sound_idx, p_sound_info->sound_mode, p_sound_info->sound_bw); + ret = beamforming_start_sw(dm, sound_info->sound_idx, sound_info->sound_mode, sound_info->sound_bw); else - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Error value return from BeamformingStart_V2\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, + "%s, Error value return from BeamformingStart_V2\n", + __func__); - if ((p_beam_info->beamformee_su_cnt != 0) || (p_beam_info->beamformee_mu_cnt > 1)) { - if (p_sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || p_sound_info->sound_mode == SOUNDING_SW_HT_TIMER) - odm_set_timer(p_dm_odm, &p_beam_info->beamforming_timer, p_sound_info->sound_period); + if (beam_info->beamformee_su_cnt != 0 || beam_info->beamformee_mu_cnt > 1) { + if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period); else { - u32 val = (p_sound_info->sound_period << 16) | HAL_TIMER_TXBF; - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_HW_REG_TIMER_RESTART, (u8 *)(&val)); + u32 val = (sound_info->sound_period << 16) | HAL_TIMER_TXBF; + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_RESTART, (u8 *)(&val)); } } } - -void -beamforming_sw_timer_callback( +void beamforming_sw_timer_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct timer_list *p_timer + struct phydm_timer_list *timer #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) void *function_context #endif -) + ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - beamforming_timer_callback(p_dm_odm); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + beamforming_timer_callback(dm); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)function_context; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)function_context; + void *adapter = dm->adapter; - if (adapter->net_closed == true) + if (*dm->is_net_closed == true) return; - rtw_run_in_thread_cmd(adapter, beamforming_timer_callback, adapter); + phydm_run_in_thread_cmd(dm, beamforming_timer_callback, adapter); #endif - } - -void -phydm_beamforming_init( - void *p_dm_void -) +void phydm_beamforming_init( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMING_OID_INFO *p_beam_oid_info = &(p_beam_info->beamforming_oid_info); - - p_beam_oid_info->sound_oid_mode = SOUNDING_STOP_OID_TIMER; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s mode (%d)\n", __func__, p_beam_oid_info->sound_oid_mode)); - - p_beam_info->beamformee_su_cnt = 0; - p_beam_info->beamformer_su_cnt = 0; - p_beam_info->beamformee_mu_cnt = 0; - p_beam_info->beamformer_mu_cnt = 0; - p_beam_info->beamformee_mu_reg_maping = 0; - p_beam_info->mu_ap_index = 0; - p_beam_info->is_mu_sounding = false; - p_beam_info->first_mu_bfee_index = 0xFF; - p_beam_info->apply_v_matrix = true; - p_beam_info->snding3ss = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + +#ifdef BEAMFORMING_VERSION_1 + if (hal_data->beamforming_version != BEAMFORMING_VERSION_1) { + return; + } +#endif +#endif + + beam_oid_info->sound_oid_mode = SOUNDING_STOP_OID_TIMER; + PHYDM_DBG(dm, DBG_TXBF, "%s mode (%d)\n", __func__, + beam_oid_info->sound_oid_mode); + + beam_info->beamformee_su_cnt = 0; + beam_info->beamformer_su_cnt = 0; + beam_info->beamformee_mu_cnt = 0; + beam_info->beamformer_mu_cnt = 0; + beam_info->beamformee_mu_reg_maping = 0; + beam_info->mu_ap_index = 0; + beam_info->is_mu_sounding = false; + beam_info->first_mu_bfee_index = 0xFF; + beam_info->apply_v_matrix = true; + beam_info->snding3ss = false; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_beam_info->source_adapter = p_dm_odm->adapter; + beam_info->source_adapter = dm->adapter; #endif - hal_com_txbf_beamform_init(p_dm_odm); + hal_com_txbf_beamform_init(dm); } - boolean phydm_acting_determine( - void *p_dm_void, - enum phydm_acting_type type -) + void *dm_void, + enum phydm_acting_type type) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - boolean ret = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->beamforming_info.source_adapter; + void *adapter = dm->beamforming_info.source_adapter; #else - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _ADAPTER *adapter = dm->adapter; #endif #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) if (type == phydm_acting_as_ap) ret = ACTING_AS_AP(adapter); else if (type == phydm_acting_as_ibss) - ret = ACTING_AS_IBSS(adapter); + ret = ACTING_AS_IBSS(((PADAPTER)(adapter))); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; if (type == phydm_acting_as_ap) ret = check_fwstate(pmlmepriv, WIFI_AP_STATE); @@ -1685,101 +1782,99 @@ phydm_acting_determine( #endif return ret; - } -void -beamforming_enter( - void *p_dm_void, - u16 sta_idx -) +void beamforming_enter( + void *dm_void, + u16 sta_idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 bfer_bfee_idx = 0xff; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 bfer_bfee_idx = 0xff; - if (beamforming_init_entry(p_dm_odm, sta_idx, &bfer_bfee_idx)) - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_ENTER, (u8 *)&bfer_bfee_idx); + if (beamforming_init_entry(dm, sta_idx, &bfer_bfee_idx)) + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_ENTER, (u8 *)&bfer_bfee_idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] End!\n", __func__); } - -void -beamforming_leave( - void *p_dm_void, - u8 *RA -) +void beamforming_leave( + void *dm_void, + u8 *RA) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (RA != NULL) { - beamforming_deinit_entry(p_dm_odm, RA); - phydm_beamforming_notify(p_dm_odm); + beamforming_deinit_entry(dm, RA); + phydm_beamforming_notify(dm); } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] End!!\n", __func__); } #if 0 /* Nobody calls this function */ void phydm_beamforming_set_txbf_en( - void *p_dm_void, + void *dm_void, u8 mac_id, boolean is_txbf ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 idx = 0; - struct _RT_BEAMFORMEE_ENTRY *p_entry; + struct _RT_BEAMFORMEE_ENTRY *entry; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - p_entry = phydm_beamforming_get_entry_by_mac_id(p_dm_odm, mac_id, &idx); + entry = phydm_beamforming_get_entry_by_mac_id(dm, mac_id, &idx); - if (p_entry == NULL) + if (entry == NULL) return; else - p_entry->is_txbf = is_txbf; + entry->is_txbf = is_txbf; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s mac_id %d TxBF %d\n", __func__, p_entry->mac_id, p_entry->is_txbf)); + PHYDM_DBG(dm, DBG_TXBF, "%s mac_id %d TxBF %d\n", __func__, + entry->mac_id, entry->is_txbf); - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); } #endif enum beamforming_cap phydm_beamforming_get_beam_cap( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info -) + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info) { - u8 i; - boolean is_self_beamformer = false; - boolean is_self_beamformee = false; - struct _RT_BEAMFORMEE_ENTRY beamformee_entry; - struct _RT_BEAMFORMER_ENTRY beamformer_entry; - enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i; + boolean is_self_beamformer = false; + boolean is_self_beamformee = false; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - beamformee_entry = p_beam_info->beamformee_entry[i]; + beamformee_entry = beam_info->beamformee_entry[i]; if (beamformee_entry.is_used) { is_self_beamformer = true; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFee entry %d is_used=true\n", __func__, i)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] BFee entry %d is_used=true\n", __func__, + i); break; } } for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { - beamformer_entry = p_beam_info->beamformer_entry[i]; + beamformer_entry = beam_info->beamformer_entry[i]; if (beamformer_entry.is_used) { is_self_beamformee = true; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: BFer entry %d is_used=true\n", __func__, i)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s]: BFer entry %d is_used=true\n", + __func__, i); break; } } @@ -1792,38 +1887,37 @@ phydm_beamforming_get_beam_cap( return beamform_cap; } - boolean beamforming_control_v1( - void *p_dm_void, - u8 *RA, - u8 AID, - u8 mode, - CHANNEL_WIDTH BW, - u8 rate -) + void *dm_void, + u8 *RA, + u8 AID, + u8 mode, + enum channel_width BW, + u8 rate) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - boolean ret = true; + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = true; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("AID (%d), mode (%d), BW (%d)\n", AID, mode, BW)); + PHYDM_DBG(dm, DBG_TXBF, "AID (%d), mode (%d), BW (%d)\n", AID, mode, + BW); switch (mode) { case 0: - ret = beamforming_start_v1(p_dm_odm, RA, 0, BW, rate); + ret = beamforming_start_v1(dm, RA, 0, BW, rate); break; case 1: - ret = beamforming_start_v1(p_dm_odm, RA, 1, BW, rate); + ret = beamforming_start_v1(dm, RA, 1, BW, rate); break; case 2: - phydm_beamforming_ndpa_rate(p_dm_odm, BW, rate); - ret = beamforming_send_vht_ndpa_packet(p_dm_odm, RA, AID, BW, NORMAL_QUEUE); + phydm_beamforming_ndpa_rate(dm, BW, rate); + ret = beamforming_send_vht_ndpa_packet(dm, RA, AID, BW, NORMAL_QUEUE); break; case 3: - phydm_beamforming_ndpa_rate(p_dm_odm, BW, rate); - ret = beamforming_send_ht_ndpa_packet(p_dm_odm, RA, BW, NORMAL_QUEUE); + phydm_beamforming_ndpa_rate(dm, BW, rate); + ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE); break; } return ret; @@ -1832,48 +1926,129 @@ beamforming_control_v1( /*Only OID uses this function*/ boolean phydm_beamforming_control_v2( - void *p_dm_void, - u8 idx, - u8 mode, - CHANNEL_WIDTH BW, - u16 period -) + void *dm_void, + u8 idx, + u8 mode, + enum channel_width BW, + u16 period) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMING_OID_INFO *p_beam_oid_info = &(p_beam_info->beamforming_oid_info); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("idx (%d), mode (%d), BW (%d), period (%d)\n", idx, mode, BW, period)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + PHYDM_DBG(dm, DBG_TXBF, "idx (%d), mode (%d), BW (%d), period (%d)\n", + idx, mode, BW, period); - p_beam_oid_info->sound_oid_idx = idx; - p_beam_oid_info->sound_oid_mode = (enum sounding_mode) mode; - p_beam_oid_info->sound_oid_bw = BW; - p_beam_oid_info->sound_oid_period = period; + beam_oid_info->sound_oid_idx = idx; + beam_oid_info->sound_oid_mode = (enum sounding_mode)mode; + beam_oid_info->sound_oid_bw = BW; + beam_oid_info->sound_oid_period = period; - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); return true; } - -void -phydm_beamforming_watchdog( - void *p_dm_void -) +void phydm_beamforming_watchdog( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("%s Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); - if (p_beam_info->beamformee_su_cnt == 0) + if (beam_info->beamformee_su_cnt == 0) return; - beamforming_dym_period(p_dm_odm, 0); - phydm_beamforming_dym_ndpa_rate(p_dm_odm); - + beamforming_dym_period(dm, 0); } +enum beamforming_cap +phydm_get_beamform_cap( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct bf_cmn_info *bf_info = NULL; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + void *adapter = dm->adapter; + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; + u8 macid; + u8 ht_curbeamformcap = 0; + u16 vht_curbeamformcap = 0; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMGNT_INFO p_MgntInfo = &(((PADAPTER)(adapter))->MgntInfo); + PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo); + PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo); + + ht_curbeamformcap = p_ht_info->HtCurBeamform; + vht_curbeamformcap = p_vht_info->VhtCurBeamform; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[%s] WIN ht_curcap = %d ; vht_curcap = %d\n", __func__, + ht_curbeamformcap, vht_curbeamformcap); + + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/ + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP)); + + /*We are Beamformer because the STA is Beamformee*/ + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP)); + +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + + /* We are Beamformee because the STA is SU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP)); + + /* We are Beamformer because the STA is SU Beamformee*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP)); + + /* We are Beamformee because the STA is MU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP)); +#endif +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + sta = dm->phydm_sta_info[macid]; + + if (!is_sta_active(sta)) + continue; + + bf_info = &sta->bf_info; + vht_curbeamformcap = bf_info->vht_beamform_cap; + ht_curbeamformcap = bf_info->ht_beamform_cap; + + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/ + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP)); + + /*We are Beamformer because the STA is Beamformee*/ + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP)); + +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + /* We are Beamformee because the STA is SU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP)); + + /* We are Beamformer because the STA is SU Beamformee*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP)); + + /* We are Beamformee because the STA is MU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP)); +#endif + } + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s] CE ht_curcap = %d ; vht_curcap = %d\n", + __func__, ht_curbeamformcap, vht_curbeamformcap); + +#endif + + return beamform_cap; +} #endif diff --git a/hal/phydm/phydm_beamforming.h b/hal/phydm/phydm_beamforming.h index 8a90938..141c8f8 100644 --- a/hal/phydm/phydm_beamforming.h +++ b/hal/phydm/phydm_beamforming.h @@ -1,11 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + #ifndef __INC_PHYDM_BEAMFORMING_H #define __INC_PHYDM_BEAMFORMING_H #ifndef BEAMFORMING_SUPPORT - #define BEAMFORMING_SUPPORT 0 +#define BEAMFORMING_SUPPORT 0 #endif -/*Beamforming Related*/ +/*@Beamforming Related*/ #include "txbf/halcomtxbf.h" #include "txbf/haltxbfjaguar.h" #include "txbf/haltxbf8192e.h" @@ -17,30 +42,30 @@ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define eq_mac_addr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) -#define cp_mac_addr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5]) +#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0) +#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5]) #endif -#define MAX_BEAMFORMEE_SU 2 -#define MAX_BEAMFORMER_SU 2 +#define MAX_BEAMFORMEE_SU 2 +#define MAX_BEAMFORMER_SU 2 #if (RTL8822B_SUPPORT == 1) - #define MAX_BEAMFORMEE_MU 6 - #define MAX_BEAMFORMER_MU 1 +#define MAX_BEAMFORMEE_MU 6 +#define MAX_BEAMFORMER_MU 1 #else - #define MAX_BEAMFORMEE_MU 0 - #define MAX_BEAMFORMER_MU 0 +#define MAX_BEAMFORMEE_MU 0 +#define MAX_BEAMFORMER_MU 0 #endif -#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU) -#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU) +#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU) +#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU) #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - /*for different naming between WIN and CE*/ - #define BEACON_QUEUE BCN_QUEUE_INX - #define NORMAL_QUEUE MGT_QUEUE_INX - #define RT_DISABLE_FUNC RTW_DISABLE_FUNC - #define RT_ENABLE_FUNC RTW_ENABLE_FUNC +/*@for different naming between WIN and CE*/ +#define BEACON_QUEUE BCN_QUEUE_INX +#define NORMAL_QUEUE MGT_QUEUE_INX +#define RT_DISABLE_FUNC RTW_DISABLE_FUNC +#define RT_ENABLE_FUNC RTW_ENABLE_FUNC #endif enum beamforming_entry_state { @@ -51,7 +76,6 @@ enum beamforming_entry_state { BEAMFORMING_ENTRY_STATE_PROGRESSED }; - enum beamforming_notify_state { BEAMFORMING_NOTIFY_NONE, BEAMFORMING_NOTIFY_ADD, @@ -67,15 +91,14 @@ enum beamforming_cap { BEAMFORMING_CAP_NONE = 0x0, BEAMFORMER_CAP_HT_EXPLICIT = BIT(1), BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2), - BEAMFORMER_CAP_VHT_SU = BIT(5), /* Self has er Cap, because Reg er & peer ee */ - BEAMFORMEE_CAP_VHT_SU = BIT(6), /* Self has ee Cap, because Reg ee & peer er */ - BEAMFORMER_CAP_VHT_MU = BIT(7), /* Self has er Cap, because Reg er & peer ee */ - BEAMFORMEE_CAP_VHT_MU = BIT(8), /* Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP_VHT_SU = BIT(5), /* @Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_SU = BIT(6), /* @Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP_VHT_MU = BIT(7), /* @Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_MU = BIT(8), /* @Self has ee Cap, because Reg ee & peer er */ BEAMFORMER_CAP = BIT(9), BEAMFORMEE_CAP = BIT(10), }; - enum sounding_mode { SOUNDING_SW_VHT_TIMER = 0x0, SOUNDING_SW_HT_TIMER = 0x1, @@ -90,130 +113,131 @@ enum sounding_mode { }; struct _RT_BEAMFORM_STAINFO { - u8 *ra; - u16 aid; - u16 mac_id; - u8 my_mac_addr[6]; - WIRELESS_MODE wireless_mode; - CHANNEL_WIDTH bw; - enum beamforming_cap beamform_cap; - u8 ht_beamform_cap; - u16 vht_beamform_cap; - u8 cur_beamform; - u16 cur_beamform_vht; + u8 *ra; + u16 aid; + u16 mac_id; + u8 my_mac_addr[6]; + /*WIRELESS_MODE wireless_mode;*/ + enum channel_width bw; + enum beamforming_cap beamform_cap; + u8 ht_beamform_cap; + u16 vht_beamform_cap; + u8 cur_beamform; + u16 cur_beamform_vht; }; - struct _RT_BEAMFORMEE_ENTRY { boolean is_used; - boolean is_txbf; + boolean is_txbf; boolean is_sound; - u16 aid; /*Used to construct AID field of NDPA packet.*/ - u16 mac_id; /*Used to Set Reg42C in IBSS mode. */ - u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ - u16 g_id; /*Used to fill Tx DESC*/ - u8 my_mac_addr[6]; - u8 mac_addr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/ - CHANNEL_WIDTH sound_bw; /*Sounding band_width*/ - u16 sound_period; - enum beamforming_cap beamform_entry_cap; - enum beamforming_entry_state beamform_entry_state; - boolean is_beamforming_in_progress; - /*u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/ - /*u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/ - /*u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/ - u16 log_status_fail_cnt:5; /* 0~21 */ - u16 default_csi_cnt:5; /* 0~21 */ - u8 csi_matrix[327]; - u16 csi_matrix_len; - u8 num_of_sounding_dim; - u8 comp_steering_num_of_bfer; - u8 su_reg_index; - /*For MU-MIMO*/ - boolean is_mu_sta; - u8 mu_reg_index; - u8 gid_valid[8]; - u8 user_position[16]; + u16 aid; /*Used to construct AID field of NDPA packet.*/ + u16 mac_id; /*Used to Set Reg42C in IBSS mode. */ + u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u8 g_id; /*Used to fill Tx DESC*/ + u8 my_mac_addr[6]; + u8 mac_addr[6]; /*@Used to fill Reg6E4 to fill Mac address of CSI report frame.*/ + enum channel_width sound_bw; /*Sounding band_width*/ + u16 sound_period; + enum beamforming_cap beamform_entry_cap; + enum beamforming_entry_state beamform_entry_state; + boolean is_beamforming_in_progress; + /*@u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/ + /*@u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/ + /*@u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/ + u16 log_status_fail_cnt : 5; /* @0~21 */ + u16 default_csi_cnt : 5; /* @0~21 */ + u8 csi_matrix[327]; + u16 csi_matrix_len; + u8 num_of_sounding_dim; + u8 comp_steering_num_of_bfer; + u8 su_reg_index; + /*@For MU-MIMO*/ + boolean is_mu_sta; + u8 mu_reg_index; + u8 gid_valid[8]; + u8 user_position[16]; }; struct _RT_BEAMFORMER_ENTRY { - boolean is_used; + boolean is_used; /*P_AID of BFer entry is probably not used*/ - u16 p_aid; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ - u16 g_id; - u8 my_mac_addr[6]; - u8 mac_addr[6]; - enum beamforming_cap beamform_entry_cap; - u8 num_of_sounding_dim; - u8 clock_reset_times; /*Modified by Jeffery @2015-04-10*/ - u8 pre_log_seq; /*Modified by Jeffery @2015-03-30*/ - u8 log_seq; /*Modified by Jeffery @2014-10-29*/ - u16 log_retry_cnt:3; /*Modified by Jeffery @2014-10-29*/ - u16 log_success:2; /*Modified by Jeffery @2014-10-29*/ - u8 su_reg_index; - /*For MU-MIMO*/ - boolean is_mu_ap; - u8 gid_valid[8]; - u8 user_position[16]; - u16 aid; + u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u8 g_id; + u8 my_mac_addr[6]; + u8 mac_addr[6]; + enum beamforming_cap beamform_entry_cap; + u8 num_of_sounding_dim; + u8 clock_reset_times; /*@Modified by Jeffery @2015-04-10*/ + u8 pre_log_seq; /*@Modified by Jeffery @2015-03-30*/ + u8 log_seq; /*@Modified by Jeffery @2014-10-29*/ + u16 log_retry_cnt : 3; /*@Modified by Jeffery @2014-10-29*/ + u16 log_success : 2; /*@Modified by Jeffery @2014-10-29*/ + u8 su_reg_index; + /*@For MU-MIMO*/ + boolean is_mu_ap; + u8 gid_valid[8]; + u8 user_position[16]; + u16 aid; }; struct _RT_SOUNDING_INFO { - u8 sound_idx; - CHANNEL_WIDTH sound_bw; - enum sounding_mode sound_mode; - u16 sound_period; + u8 sound_idx; + enum channel_width sound_bw; + enum sounding_mode sound_mode; + u16 sound_period; }; - - struct _RT_BEAMFORMING_OID_INFO { - u8 sound_oid_idx; - CHANNEL_WIDTH sound_oid_bw; - enum sounding_mode sound_oid_mode; - u16 sound_oid_period; + u8 sound_oid_idx; + enum channel_width sound_oid_bw; + enum sounding_mode sound_oid_mode; + u16 sound_oid_period; }; - struct _RT_BEAMFORMING_INFO { - enum beamforming_cap beamform_cap; - struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM]; - struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM]; - struct _RT_BEAMFORM_STAINFO beamform_sta_info; - u8 beamformee_cur_idx; - struct timer_list beamforming_timer; - struct timer_list mu_timer; - struct _RT_SOUNDING_INFO sounding_info; - struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info; - struct _HAL_TXBF_INFO txbf_info; - u8 sounding_sequence; - u8 beamformee_su_cnt; - u8 beamformer_su_cnt; - u32 beamformee_su_reg_maping; - u32 beamformer_su_reg_maping; - /*For MU-MINO*/ - u8 beamformee_mu_cnt; - u8 beamformer_mu_cnt; - u32 beamformee_mu_reg_maping; - u8 mu_ap_index; - boolean is_mu_sounding; - u8 first_mu_bfee_index; - boolean is_mu_sounding_in_progress; - boolean dbg_disable_mu_tx; - boolean apply_v_matrix; - boolean snding3ss; + enum beamforming_cap beamform_cap; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM]; + struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM]; + struct _RT_BEAMFORM_STAINFO beamform_sta_info; + u8 beamformee_cur_idx; + struct phydm_timer_list beamforming_timer; + struct phydm_timer_list mu_timer; + struct _RT_SOUNDING_INFO sounding_info; + struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info; + struct _HAL_TXBF_INFO txbf_info; + u8 sounding_sequence; + u8 beamformee_su_cnt; + u8 beamformer_su_cnt; + u32 beamformee_su_reg_maping; + u32 beamformer_su_reg_maping; + /*@For MU-MINO*/ + u8 beamformee_mu_cnt; + u8 beamformer_mu_cnt; + u32 beamformee_mu_reg_maping; + u8 mu_ap_index; + boolean is_mu_sounding; + u8 first_mu_bfee_index; + boolean is_mu_sounding_in_progress; + boolean dbg_disable_mu_tx; + boolean apply_v_matrix; + boolean snding3ss; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *source_adapter; + void *source_adapter; #endif - /* Control register */ - u32 reg_mu_tx_ctrl; /* For USB/SDIO interfaces aync I/O */ + /* @Control register */ + u32 reg_mu_tx_ctrl; /* @For USB/SDIO interfaces aync I/O */ + u8 tx_bf_data_rate; + u8 last_usb_hub; }; +void phydm_get_txbf_device_num( + void *dm_void, + u8 macid); struct _RT_NDPA_STA_INFO { - u16 aid:12; - u16 feedback_type:1; - u16 nc_index:3; + u16 aid : 12; + u16 feedback_type : 1; + u16 nc_index : 3; }; enum phydm_acting_type { @@ -221,154 +245,125 @@ enum phydm_acting_type { phydm_acting_as_ap = 1 }; - enum beamforming_cap phydm_beamforming_get_entry_beam_cap_by_mac_id( - void *p_dm_void, - u8 mac_id -); + void *dm_void, + u8 mac_id); struct _RT_BEAMFORMEE_ENTRY * phydm_beamforming_get_bfee_entry_by_addr( - void *p_dm_void, - u8 *RA, - u8 *idx -); + void *dm_void, + u8 *RA, + u8 *idx); struct _RT_BEAMFORMER_ENTRY * phydm_beamforming_get_bfer_entry_by_addr( - void *p_dm_void, - u8 *TA, - u8 *idx -); + void *dm_void, + u8 *TA, + u8 *idx); -void -phydm_beamforming_notify( - void *p_dm_void -); +void phydm_beamforming_notify( + void *dm_void); boolean phydm_acting_determine( - void *p_dm_void, - enum phydm_acting_type type -); - -void -beamforming_enter( - void *p_dm_void, - u16 sta_idx -); - -void -beamforming_leave( - void *p_dm_void, - u8 *RA -); + void *dm_void, + enum phydm_acting_type type); -boolean -beamforming_start_fw( - void *p_dm_void, - u8 idx -); +void beamforming_enter( + void *dm_void, + u16 sta_idx); -void -beamforming_check_sounding_success( - void *p_dm_void, - boolean status -); +void beamforming_leave( + void *dm_void, + u8 *RA); -void -phydm_beamforming_end_sw( - void *p_dm_void, - boolean status -); +boolean +beamforming_start_fw( + void *dm_void, + u8 idx); -void -beamforming_timer_callback( - void *p_dm_void -); +void beamforming_check_sounding_success( + void *dm_void, + boolean status); -void -phydm_beamforming_init( - void *p_dm_void -); +void phydm_beamforming_end_sw( + void *dm_void, + boolean status); +void beamforming_timer_callback( + void *dm_void); +void phydm_beamforming_init( + void *dm_void); enum beamforming_cap phydm_beamforming_get_beam_cap( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info -); + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info); +enum beamforming_cap +phydm_get_beamform_cap( + void *dm_void); boolean beamforming_control_v1( - void *p_dm_void, - u8 *RA, - u8 AID, - u8 mode, - CHANNEL_WIDTH BW, - u8 rate -); - + void *dm_void, + u8 *RA, + u8 AID, + u8 mode, + enum channel_width BW, + u8 rate); boolean phydm_beamforming_control_v2( - void *p_dm_void, - u8 idx, - u8 mode, - CHANNEL_WIDTH BW, - u16 period -); - -void -phydm_beamforming_watchdog( - void *p_dm_void -); - -void -beamforming_sw_timer_callback( + void *dm_void, + u8 idx, + u8 mode, + enum channel_width BW, + u16 period); + +void phydm_beamforming_watchdog( + void *dm_void); + +void beamforming_sw_timer_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct timer_list *p_timer + struct phydm_timer_list *timer #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) void *function_context #endif -); + ); boolean beamforming_send_ht_ndpa_packet( - void *p_dm_void, - u8 *RA, - CHANNEL_WIDTH BW, - u8 q_idx -); - + void *dm_void, + u8 *RA, + enum channel_width BW, + u8 q_idx); boolean beamforming_send_vht_ndpa_packet( - void *p_dm_void, - u8 *RA, - u16 AID, - CHANNEL_WIDTH BW, - u8 q_idx -); + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW, + u8 q_idx); #else -#define beamforming_gid_paid(adapter, p_tcb) -#define phydm_acting_determine(p_dm_odm, type) false -#define beamforming_enter(p_dm_odm, sta_idx) -#define beamforming_leave(p_dm_odm, RA) -#define beamforming_end_fw(p_dm_odm) -#define beamforming_control_v1(p_dm_odm, RA, AID, mode, BW, rate) true -#define beamforming_control_v2(p_dm_odm, idx, mode, BW, period) true -#define phydm_beamforming_end_sw(p_dm_odm, _status) -#define beamforming_timer_callback(p_dm_odm) -#define phydm_beamforming_init(p_dm_odm) -#define phydm_beamforming_control_v2(p_dm_odm, _idx, _mode, _BW, _period) false -#define beamforming_watchdog(p_dm_odm) -#define phydm_beamforming_watchdog(p_dm_odm) - - -#endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP)) +#define beamforming_gid_paid(adapter, tcb) +#define phydm_acting_determine(dm, type) false +#define beamforming_enter(dm, sta_idx) +#define beamforming_leave(dm, RA) +#define beamforming_end_fw(dm) +#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true +#define beamforming_control_v2(dm, idx, mode, BW, period) true +#define phydm_beamforming_end_sw(dm, _status) +#define beamforming_timer_callback(dm) +#define phydm_beamforming_init(dm) +#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false +#define beamforming_watchdog(dm) +#define phydm_beamforming_watchdog(dm) +#endif /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/ +#endif /*@(BEAMFORMING_SUPPORT == 1)*/ #endif diff --git a/hal/phydm/phydm_cck_pd.c b/hal/phydm/phydm_cck_pd.c new file mode 100644 index 0000000..0b71d82 --- /dev/null +++ b/hal/phydm/phydm_cck_pd.c @@ -0,0 +1,1076 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_SUPPORT_CCKPD +#ifdef PHYDM_COMPILE_CCKPD_TYPE1 +void phydm_write_cck_pd_type1(void *dm_void, u8 cca_th) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + + PHYDM_DBG(dm, DBG_CCKPD, "[%s] cck_cca_th=((0x%x))\n", + __func__, cca_th); + + odm_write_1byte(dm, R_0xa0a, cca_th); + cckpd_t->cur_cck_cca_thres = cca_th; +} + +void phydm_set_cckpd_lv_type1(void *dm_void, enum cckpd_lv lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 pd_th = 0; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv); + + if (cckpd_t->cck_pd_lv == lv) { + PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv); + return; + } + + cckpd_t->cck_pd_lv = lv; + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + + if (lv == CCK_PD_LV_4) + pd_th = 0xed; + else if (lv == CCK_PD_LV_3) + pd_th = 0xdd; + else if (lv == CCK_PD_LV_2) + pd_th = 0xcd; + else if (lv == CCK_PD_LV_1) + pd_th = 0x83; + else if (lv == CCK_PD_LV_0) + pd_th = 0x40; + + phydm_write_cck_pd_type1(dm, pd_th); +} + +void phydm_cckpd_type1(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_lv lv = CCK_PD_LV_INIT; + boolean is_update = true; + + if (dm->is_linked) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (dm->rssi_min > 60) { + lv = CCK_PD_LV_3; + } else if (dm->rssi_min > 35) { + lv = CCK_PD_LV_2; + } else if (dm->rssi_min > 20) { + if (cckpd_t->cck_fa_ma > 500) + lv = CCK_PD_LV_2; + else if (cckpd_t->cck_fa_ma < 250) + lv = CCK_PD_LV_1; + else + is_update = false; + } else { /*RSSI < 20*/ + lv = CCK_PD_LV_1; + } + #else /*ODM_AP*/ + if (dig_t->cur_ig_value > 0x32) + lv = CCK_PD_LV_4; + else if (dig_t->cur_ig_value > 0x2a) + lv = CCK_PD_LV_3; + else if (dig_t->cur_ig_value > 0x24) + lv = CCK_PD_LV_2; + else + lv = CCK_PD_LV_1; + #endif + } else { + if (cckpd_t->cck_fa_ma > 1000) + lv = CCK_PD_LV_1; + else if (cckpd_t->cck_fa_ma < 500) + lv = CCK_PD_LV_0; + else + is_update = false; + } + + /*[Abnormal case] =================================================*/ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + /*@HP 22B LPS power consumption issue & [PCIE-1596]*/ + if (dm->hp_hw_id && dm->traffic_load == TRAFFIC_ULTRA_LOW) { + lv = CCK_PD_LV_0; + PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case1\n"); + } else if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) && + cckpd_t->cck_fa_ma > 200 && dm->rssi_min <= 20) { + lv = CCK_PD_LV_1; + cckpd_t->cck_pd_lv = lv; + phydm_write_cck_pd_type1(dm, 0xc3); /*@for ASUS OTA test*/ + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case2\n"); + } + #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #ifdef MCR_WIRELESS_EXTEND + lv = CCK_PD_LV_2; + cckpd_t->cck_pd_lv = lv; + phydm_write_cck_pd_type1(dm, 0x43); + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case3\n"); + #endif + #endif + /*=================================================================*/ + + if (is_update) + phydm_set_cckpd_lv_type1(dm, lv); + + PHYDM_DBG(dm, DBG_CCKPD, "is_linked=%d, lv=%d, pd_th=0x%x\n\n", + dm->is_linked, cckpd_t->cck_pd_lv, + cckpd_t->cur_cck_cca_thres); +} +#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE1*/ + +#ifdef PHYDM_COMPILE_CCKPD_TYPE2 +void phydm_write_cck_pd_type2(void *dm_void, u8 cca_th, u8 cca_th_aaa) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + + PHYDM_DBG(dm, DBG_CCKPD, "[%s] pd_th=0x%x, cs_ratio=0x%x\n", + __func__, cca_th, cca_th_aaa); + + odm_set_bb_reg(dm, R_0xa08, 0xf0000, cca_th); + odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, cca_th_aaa); + cckpd_t->cur_cck_cca_thres = cca_th; + cckpd_t->cck_cca_th_aaa = cca_th_aaa; +} + +void phydm_set_cckpd_lv_type2(void *dm_void, enum cckpd_lv lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 pd_th = 0, cs_ratio = 0, cs_2r_offset = 0; + u8 cck_n_rx = 1; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv); + + /*@r_mrx & r_cca_mrc*/ + cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(18)) && + odm_get_bb_reg(dm, R_0xa2c, BIT(22))) ? 2 : 1; + + if (cckpd_t->cck_pd_lv == lv && cckpd_t->cck_n_rx == cck_n_rx) { + PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv); + return; + } + + cckpd_t->cck_n_rx = cck_n_rx; + cckpd_t->cck_pd_lv = lv; + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + + if (lv == CCK_PD_LV_4) { + cs_ratio = cckpd_t->aaa_default + 8; + cs_2r_offset = 5; + pd_th = 0xd; + } else if (lv == CCK_PD_LV_3) { + cs_ratio = cckpd_t->aaa_default + 6; + cs_2r_offset = 4; + pd_th = 0xd; + } else if (lv == CCK_PD_LV_2) { + cs_ratio = cckpd_t->aaa_default + 4; + cs_2r_offset = 3; + pd_th = 0xd; + } else if (lv == CCK_PD_LV_1) { + cs_ratio = cckpd_t->aaa_default + 2; + cs_2r_offset = 1; + pd_th = 0x7; + } else if (lv == CCK_PD_LV_0) { + cs_ratio = cckpd_t->aaa_default; + cs_2r_offset = 0; + pd_th = 0x3; + } + + if (cckpd_t->cck_n_rx == 2) { + if (cs_ratio >= cs_2r_offset) + cs_ratio = cs_ratio - cs_2r_offset; + else + cs_ratio = 0; + } + phydm_write_cck_pd_type2(dm, pd_th, cs_ratio); +} + +void phydm_cckpd_type2(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_lv lv = CCK_PD_LV_INIT; + u8 igi = dig_t->cur_ig_value; + u8 rssi_min = dm->rssi_min; + boolean is_update = true; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + + if (dm->is_linked) { + if (igi > 0x38 && rssi_min > 32) { + lv = CCK_PD_LV_4; + } else if (igi > 0x2a && rssi_min > 32) { + lv = CCK_PD_LV_3; + } else if (igi > 0x24 || (rssi_min > 24 && rssi_min <= 30)) { + lv = CCK_PD_LV_2; + } else if (igi <= 0x24 || rssi_min < 22) { + if (cckpd_t->cck_fa_ma > 1000) { + lv = CCK_PD_LV_1; + } else if (cckpd_t->cck_fa_ma < 500) { + lv = CCK_PD_LV_0; + } else { + is_update = false; + } + } else { + is_update = false; + } + } else { + if (cckpd_t->cck_fa_ma > 1000) { + lv = CCK_PD_LV_1; + } else if (cckpd_t->cck_fa_ma < 500) { + lv = CCK_PD_LV_0; + } else { + is_update = false; + } + } + + if (is_update) { + phydm_set_cckpd_lv_type2(dm, lv); + } + + PHYDM_DBG(dm, DBG_CCKPD, + "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x\n\n", + dm->is_linked, cckpd_t->cck_pd_lv, cckpd_t->cck_n_rx, + cckpd_t->cck_cca_th_aaa, cckpd_t->cur_cck_cca_thres); +} +#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE2*/ + +#ifdef PHYDM_COMPILE_CCKPD_TYPE3 +void phydm_write_cck_pd_type3(void *dm_void, u8 pd_th, u8 cs_ratio, + enum cckpd_mode mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + + PHYDM_DBG(dm, DBG_CCKPD, + "[%s] mode=%d, pd_th=0x%x, cs_ratio=0x%x\n", __func__, + mode, pd_th, cs_ratio); + + switch (mode) { + case CCK_BW20_1R: /*RFBW20_1R*/ + { + cckpd_t->cur_cck_pd_20m_1r = pd_th; + cckpd_t->cur_cck_cs_ratio_20m_1r = cs_ratio; + odm_set_bb_reg(dm, R_0xac8, 0xff, pd_th); + odm_set_bb_reg(dm, R_0xad0, 0x1f, cs_ratio); + } break; + case CCK_BW20_2R: /*RFBW20_2R*/ + { + cckpd_t->cur_cck_pd_20m_2r = pd_th; + cckpd_t->cur_cck_cs_ratio_20m_2r = cs_ratio; + odm_set_bb_reg(dm, R_0xac8, 0xff00, pd_th); + odm_set_bb_reg(dm, R_0xad0, 0x3e0, cs_ratio); + } break; + case CCK_BW40_1R: /*RFBW40_1R*/ + { + cckpd_t->cur_cck_pd_40m_1r = pd_th; + cckpd_t->cur_cck_cs_ratio_40m_1r = cs_ratio; + odm_set_bb_reg(dm, R_0xacc, 0xff, pd_th); + odm_set_bb_reg(dm, R_0xad0, 0x1f00000, cs_ratio); + } break; + case CCK_BW40_2R: /*RFBW40_2R*/ + { + cckpd_t->cur_cck_pd_40m_2r = pd_th; + cckpd_t->cur_cck_cs_ratio_40m_2r = cs_ratio; + odm_set_bb_reg(dm, R_0xacc, 0xff00, pd_th); + odm_set_bb_reg(dm, R_0xad0, 0x3e000000, cs_ratio); + } break; + + default: + /*@pr_debug("[%s] warning!\n", __func__);*/ + break; + } +} + +void phydm_set_cckpd_lv_type3(void *dm_void, enum cckpd_lv lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_mode cck_mode = CCK_BW20_2R; + enum channel_width cck_bw = CHANNEL_WIDTH_20; + u8 cck_n_rx = 1; + u8 pd_th; + u8 cs_ratio; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv); + + /*[Check Nrx]*/ + cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(17))) ? 2 : 1; + + /*[Check BW]*/ + if (odm_get_bb_reg(dm, R_0x800, BIT(0))) + cck_bw = CHANNEL_WIDTH_40; + else + cck_bw = CHANNEL_WIDTH_20; + + /*[Check LV]*/ + if (cckpd_t->cck_pd_lv == lv && + cckpd_t->cck_n_rx == cck_n_rx && + cckpd_t->cck_bw == cck_bw) { + PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv); + return; + } + + cckpd_t->cck_bw = cck_bw; + cckpd_t->cck_n_rx = cck_n_rx; + cckpd_t->cck_pd_lv = lv; + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + + if (cck_n_rx == 2) { + if (cck_bw == CHANNEL_WIDTH_20) { + pd_th = cckpd_t->cck_pd_20m_2r; + cs_ratio = cckpd_t->cck_cs_ratio_20m_2r; + cck_mode = CCK_BW20_2R; + } else { + pd_th = cckpd_t->cck_pd_40m_2r; + cs_ratio = cckpd_t->cck_cs_ratio_40m_2r; + cck_mode = CCK_BW40_2R; + } + } else { + if (cck_bw == CHANNEL_WIDTH_20) { + pd_th = cckpd_t->cck_pd_20m_1r; + cs_ratio = cckpd_t->cck_cs_ratio_20m_1r; + cck_mode = CCK_BW20_1R; + } else { + pd_th = cckpd_t->cck_pd_40m_1r; + cs_ratio = cckpd_t->cck_cs_ratio_40m_1r; + cck_mode = CCK_BW40_1R; + } + } + + if (lv == CCK_PD_LV_4) { + if (cck_n_rx == 2) { + pd_th += 4; + cs_ratio += 2; + } else { + pd_th += 4; + cs_ratio += 3; + } + } else if (lv == CCK_PD_LV_3) { + if (cck_n_rx == 2) { + pd_th += 3; + cs_ratio += 1; + } else { + pd_th += 3; + cs_ratio += 2; + } + } else if (lv == CCK_PD_LV_2) { + pd_th += 2; + cs_ratio += 1; + } else if (lv == CCK_PD_LV_1) { + pd_th += 1; + cs_ratio += 1; + } + #if 0 + else if (lv == CCK_PD_LV_0) { + pd_th += 0; + cs_ratio += 0; + } + #endif + + phydm_write_cck_pd_type3(dm, pd_th, cs_ratio, cck_mode); +} + +void phydm_cckpd_type3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_lv lv = CCK_PD_LV_INIT; + u8 igi = dm->dm_dig_table.cur_ig_value; + boolean is_update = true; + u8 pd_th = 0; + u8 cs_ratio = 0; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + + if (dm->is_linked) { + if (igi > 0x38 && dm->rssi_min > 32) { + lv = CCK_PD_LV_4; + } else if ((igi > 0x2a) && (dm->rssi_min > 32)) { + lv = CCK_PD_LV_3; + } else if ((igi > 0x24) || + (dm->rssi_min > 24 && dm->rssi_min <= 30)) { + lv = CCK_PD_LV_2; + } else if ((igi <= 0x24) || (dm->rssi_min < 22)) { + if (cckpd_t->cck_fa_ma > 1000) + lv = CCK_PD_LV_1; + else if (cckpd_t->cck_fa_ma < 500) + lv = CCK_PD_LV_0; + else + is_update = false; + } + } else { + if (cckpd_t->cck_fa_ma > 1000) + lv = CCK_PD_LV_1; + else if (cckpd_t->cck_fa_ma < 500) + lv = CCK_PD_LV_0; + else + is_update = false; + } + + if (is_update) + phydm_set_cckpd_lv_type3(dm, lv); + + if (cckpd_t->cck_n_rx == 2) { + if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) { + pd_th = cckpd_t->cur_cck_pd_20m_2r; + cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_2r; + } else { + pd_th = cckpd_t->cur_cck_pd_40m_2r; + cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_2r; + } + } else { + if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) { + pd_th = cckpd_t->cur_cck_pd_20m_1r; + cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_1r; + } else { + pd_th = cckpd_t->cur_cck_pd_40m_1r; + cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_1r; + } + } + PHYDM_DBG(dm, DBG_CCKPD, + "[%dR][%dM] is_linked=%d, lv=%d, cs_ratio=0x%x, pd_th=0x%x\n\n", + cckpd_t->cck_n_rx, 20 << cckpd_t->cck_bw, dm->is_linked, + cckpd_t->cck_pd_lv, cs_ratio, pd_th); +} + +void phydm_cck_pd_init_type3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u32 reg_tmp = 0; + + /*Get Default value*/ + cckpd_t->cck_pd_20m_1r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff); + cckpd_t->cck_pd_20m_2r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff00); + cckpd_t->cck_pd_40m_1r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff); + cckpd_t->cck_pd_40m_2r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff00); + + reg_tmp = odm_get_bb_reg(dm, R_0xad0, MASKDWORD); + cckpd_t->cck_cs_ratio_20m_1r = (u8)(reg_tmp & 0x1f); + cckpd_t->cck_cs_ratio_20m_2r = (u8)((reg_tmp & 0x3e0) >> 5); + cckpd_t->cck_cs_ratio_40m_1r = (u8)((reg_tmp & 0x1f00000) >> 20); + cckpd_t->cck_cs_ratio_40m_2r = (u8)((reg_tmp & 0x3e000000) >> 25); + + phydm_set_cckpd_lv_type3(dm, CCK_PD_LV_0); +} +#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE3*/ + +#ifdef PHYDM_COMPILE_CCKPD_TYPE4 +void phydm_write_cck_pd_type4(void *dm_void, enum cckpd_lv lv, + enum cckpd_mode mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u32 val = 0; + + PHYDM_DBG(dm, DBG_CCKPD, "write CCK CCA parameters(CS_ratio & PD)\n"); + switch (mode) { + case CCK_BW20_1R: /*RFBW20_1R*/ + { + val = cckpd_t->cck_pd_table_jgr3[0][0][0][lv]; + odm_set_bb_reg(dm, R_0x1ac8, 0xff, val); + val = cckpd_t->cck_pd_table_jgr3[0][0][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0x1f, val); + } break; + case CCK_BW40_1R: /*RFBW40_1R*/ + { + val = cckpd_t->cck_pd_table_jgr3[1][0][0][lv]; + odm_set_bb_reg(dm, R_0x1acc, 0xff, val); + val = cckpd_t->cck_pd_table_jgr3[1][0][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0x01F00000, val); + } break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case CCK_BW20_2R: /*RFBW20_2R*/ + { + val = cckpd_t->cck_pd_table_jgr3[0][1][0][lv]; + odm_set_bb_reg(dm, R_0x1ac8, 0xff00, val); + val = cckpd_t->cck_pd_table_jgr3[0][1][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0x3e0, val); + } break; + case CCK_BW40_2R: /*RFBW40_2R*/ + { + val = cckpd_t->cck_pd_table_jgr3[1][1][0][lv]; + odm_set_bb_reg(dm, R_0x1acc, 0xff00, val); + val = cckpd_t->cck_pd_table_jgr3[1][1][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0x3E000000, val); + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case CCK_BW20_3R: /*RFBW20_3R*/ + { + val = cckpd_t->cck_pd_table_jgr3[0][2][0][lv]; + odm_set_bb_reg(dm, R_0x1ac8, 0xff0000, val); + val = cckpd_t->cck_pd_table_jgr3[0][2][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0x7c00, val); + } break; + case CCK_BW40_3R: /*RFBW40_3R*/ + { + val = cckpd_t->cck_pd_table_jgr3[1][2][0][lv]; + odm_set_bb_reg(dm, R_0x1acc, 0xff0000, val); + val = cckpd_t->cck_pd_table_jgr3[1][2][1][lv] & 0x3; + odm_set_bb_reg(dm, R_0x1ad0, 0xC0000000, val); + val = (cckpd_t->cck_pd_table_jgr3[1][2][1][lv] & 0x1c) >> 2; + odm_set_bb_reg(dm, R_0x1ad4, 0x7, val); + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case CCK_BW20_4R: /*RFBW20_4R*/ + { + val = cckpd_t->cck_pd_table_jgr3[0][3][0][lv]; + odm_set_bb_reg(dm, R_0x1ac8, 0xff000000, val); + val = cckpd_t->cck_pd_table_jgr3[0][3][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0xF8000, val); + } break; + case CCK_BW40_4R: /*RFBW40_4R*/ + { + val = cckpd_t->cck_pd_table_jgr3[1][3][0][lv]; + odm_set_bb_reg(dm, R_0x1acc, 0xff000000, val); + val = cckpd_t->cck_pd_table_jgr3[1][3][1][lv]; + odm_set_bb_reg(dm, R_0x1ad4, 0xf8, val); + } break; + #endif + default: + /*@pr_debug("[%s] warning!\n", __func__);*/ + break; + } +} + +void phydm_set_cck_pd_lv_type4(void *dm_void, enum cckpd_lv lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_mode cck_mode = CCK_BW20_2R; + enum channel_width cck_bw = CHANNEL_WIDTH_20; + u8 cck_n_rx; + u32 val; + /*u32 val_dbg = 0;*/ + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv); + + /*[Check Nrx]*/ + cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1; + + /*[Check BW]*/ + val = odm_get_bb_reg(dm, R_0x9b0, 0xc); + if (val == 0) + cck_bw = CHANNEL_WIDTH_20; + else if (val == 1) + cck_bw = CHANNEL_WIDTH_40; + else + cck_bw = CHANNEL_WIDTH_80; + + /*[Check LV]*/ + if (cckpd_t->cck_pd_lv == lv && + cckpd_t->cck_n_rx == cck_n_rx && + cckpd_t->cck_bw == cck_bw) { + PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv); + return; + } + + cckpd_t->cck_bw = cck_bw; + cckpd_t->cck_n_rx = cck_n_rx; + cckpd_t->cck_pd_lv = lv; + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + + switch (cck_n_rx) { + case 1: /*1R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_1R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_1R; + } break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case 2: /*2R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_2R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_2R; + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case 3: /*3R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_3R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_3R; + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case 4: /*4R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_4R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_4R; + } break; + #endif + default: + /*@pr_debug("[%s] warning!\n", __func__);*/ + break; + } +phydm_write_cck_pd_type4(dm, lv, cck_mode); +} + +void phydm_read_cckpd_para_type4(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 bw = 0; /*r_RX_RF_BW*/ + u8 n_rx = 0; + u8 curr_cck_pd_t[2][4][2]; + u32 reg0 = 0; + u32 reg1 = 0; + u32 reg2 = 0; + u32 reg3 = 0; + + bw = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc); + n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1; + + reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD); + reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD); + reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD); + reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD); + curr_cck_pd_t[0][0][0] = (u8)(reg0 & 0x000000ff); + curr_cck_pd_t[1][0][0] = (u8)(reg1 & 0x000000ff); + curr_cck_pd_t[0][0][1] = (u8)(reg2 & 0x0000001f); + curr_cck_pd_t[1][0][1] = (u8)((reg2 & 0x01f00000) >> 20); + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) { + curr_cck_pd_t[0][1][0] = (u8)((reg0 & 0x0000ff00) >> 8); + curr_cck_pd_t[1][1][0] = (u8)((reg1 & 0x0000ff00) >> 8); + curr_cck_pd_t[0][1][1] = (u8)((reg2 & 0x000003E0) >> 5); + curr_cck_pd_t[1][1][1] = (u8)((reg2 & 0x3E000000) >> 25); + } + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) { + curr_cck_pd_t[0][2][0] = (u8)((reg0 & 0x00ff0000) >> 16); + curr_cck_pd_t[1][2][0] = (u8)((reg1 & 0x00ff0000) >> 16); + curr_cck_pd_t[0][2][1] = (u8)((reg2 & 0x00007C00) >> 10); + curr_cck_pd_t[1][2][1] = (u8)((reg2 & 0xC0000000) >> 30) | + ((reg3 & 0x7) << 3); + } + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + curr_cck_pd_t[0][3][0] = (u8)((reg0 & 0xff000000) >> 24); + curr_cck_pd_t[1][3][0] = (u8)((reg1 & 0xff000000) >> 24); + curr_cck_pd_t[0][3][1] = (u8)((reg2 & 0x000F8000) >> 15); + curr_cck_pd_t[1][3][1] = (u8)((reg3 & 0x000000F8) >> 3); + } + #endif + + PHYDM_DBG(dm, DBG_CCKPD, "bw=%dM, Nrx=%d\n", 20 << bw, n_rx); + PHYDM_DBG(dm, DBG_CCKPD, "lv=%d, readback CS_th=%x, PD th=%x\n", + cckpd_t->cck_pd_lv, + curr_cck_pd_t[bw][n_rx - 1][1], + curr_cck_pd_t[bw][n_rx - 1][0]); +} + +void phydm_cckpd_type4(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 igi = dm->dm_dig_table.cur_ig_value; + enum cckpd_lv lv = 0; + boolean is_update = true; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + + if (dm->is_linked) { + PHYDM_DBG(dm, DBG_CCKPD, "Linked!!!\n"); + if (igi > 0x38 && dm->rssi_min > 32) { + lv = CCK_PD_LV_4; + PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n"); + } else if ((igi > 0x2a) && (dm->rssi_min > 32)) { + lv = CCK_PD_LV_3; + PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n"); + } else if ((igi > 0x24) || + (dm->rssi_min > 24 && dm->rssi_min <= 30)) { + lv = CCK_PD_LV_2; + PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n"); + } else if ((igi <= 0x24) || (dm->rssi_min < 22)) { + if (cckpd_t->cck_fa_ma > 1000) { + lv = CCK_PD_LV_1; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n"); + } else if (cckpd_t->cck_fa_ma < 500) { + lv = CCK_PD_LV_0; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n"); + } else { + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n"); + } + } else { + is_update = false; + } + } else { + PHYDM_DBG(dm, DBG_CCKPD, "UnLinked!!!\n"); + if (cckpd_t->cck_fa_ma > 1000) { + lv = CCK_PD_LV_1; + PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n"); + } else if (cckpd_t->cck_fa_ma < 500) { + lv = CCK_PD_LV_0; + PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n"); + } else { + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n"); + } + } + + if (is_update) + phydm_set_cck_pd_lv_type4(dm, lv); + + + PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n", + cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw] + [cckpd_t->cck_n_rx - 1][1][lv], + cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw] + [cckpd_t->cck_n_rx - 1][0][lv]); + + phydm_read_cckpd_para_type4(dm); +} + +void phydm_cck_pd_init_type4(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u32 reg0 = 0; + u32 reg1 = 0; + u32 reg2 = 0; + u32 reg3 = 0; + u8 pd_step = 0; + u8 cck_bw = 0; /*r_RX_RF_BW*/ + u8 cck_n_rx = 0; + u8 val = 0; + u8 i = 0; + + PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__); + + #if 0 + /*@ + *cckpd_t[0][0][0][0] = 1ac8[7:0] r_PD_lim_RFBW20_1R + *cckpd_t[0][1][0][0] = 1ac8[15:8] r_PD_lim_RFBW20_2R + *cckpd_t[0][2][0][0] = 1ac8[23:16] r_PD_lim_RFBW20_3R + *cckpd_t[0][3][0][0] = 1ac8[31:24] r_PD_lim_RFBW20_4R + *cckpd_t[1][0][0][0] = 1acc[7:0] r_PD_lim_RFBW40_1R + *cckpd_t[1][1][0][0] = 1acc[15:8] r_PD_lim_RFBW40_2R + *cckpd_t[1][2][0][0] = 1acc[23:16] r_PD_lim_RFBW40_3R + *cckpd_t[1][3][0][0] = 1acc[31:24] r_PD_lim_RFBW40_4R + * + * + *cckpd_t[0][0][1][0] = 1ad0[4:0] r_CS_ratio_RFBW20_1R[4:0] + *cckpd_t[0][1][1][0] = 1ad0[9:5] r_CS_ratio_RFBW20_2R[4:0] + *cckpd_t[0][2][1][0] = 1ad0[14:10] r_CS_ratio_RFBW20_3R[4:0] + *cckpd_t[0][3][1][0] = 1ad0[19:15] r_CS_ratio_RFBW20_4R[4:0] + *cckpd_t[1][0][1][0] = 1ad0[24:20] r_CS_ratio_RFBW40_1R[4:0] + *cckpd_t[1][1][1][0] = 1ad0[29:25] r_CS_ratio_RFBW40_2R[4:0] + *cckpd_t[1][2][1][0] = 1ad0[31:30] r_CS_ratio_RFBW40_3R[1:0] + * 1ad4[2:0] r_CS_ratio_RFBW40_3R[4:2] + *cckpd_t[1][3][1][0] = 1ad4[7:3] r_CS_ratio_RFBW40_4R[4:0] + */ + #endif + /*[Check Nrx]*/ + cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1; + + /*[Check BW]*/ + val = odm_get_bb_reg(dm, R_0x9b0, 0xc); + if (val == 0) + cck_bw = CHANNEL_WIDTH_20; + else if (val == 1) + cck_bw = CHANNEL_WIDTH_40; + else + cck_bw = CHANNEL_WIDTH_80; + + cckpd_t->cck_bw = cck_bw; + cckpd_t->cck_n_rx = cck_n_rx; + reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD); + reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD); + reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD); + reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD); + + for (i = 0 ; i < CCK_PD_LV_MAX ; i++) { + pd_step = i * 2; + + val = (u8)(reg0 & 0x000000ff) + pd_step; + PHYDM_DBG(dm, DBG_CCKPD, "lvl %d val = %x\n\n", i, val); + cckpd_t->cck_pd_table_jgr3[0][0][0][i] = val; + + val = (u8)(reg1 & 0x000000ff) + pd_step; + cckpd_t->cck_pd_table_jgr3[1][0][0][i] = val; + + val = (u8)(reg2 & 0x0000001F) + pd_step; + cckpd_t->cck_pd_table_jgr3[0][0][1][i] = val; + + val = (u8)((reg2 & 0x01F00000) >> 20) + pd_step; + cckpd_t->cck_pd_table_jgr3[1][0][1][i] = val; + + #ifdef PHYDM_COMPILE_ABOVE_2SS + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) { + val = (u8)((reg0 & 0x0000ff00) >> 8) + pd_step; + cckpd_t->cck_pd_table_jgr3[0][1][0][i] = val; + + val = (u8)((reg1 & 0x0000ff00) >> 8) + pd_step; + cckpd_t->cck_pd_table_jgr3[1][1][0][i] = val; + + val = (u8)((reg2 & 0x000003E0) >> 5) + pd_step; + cckpd_t->cck_pd_table_jgr3[0][1][1][i] = val; + + val = (u8)((reg2 & 0x3E000000) >> 25) + pd_step; + cckpd_t->cck_pd_table_jgr3[1][1][1][i] = val; + } + #endif + + #ifdef PHYDM_COMPILE_ABOVE_3SS + if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) { + val = (u8)((reg0 & 0x00ff0000) >> 16) + pd_step; + cckpd_t->cck_pd_table_jgr3[0][2][0][i] = val; + + val = (u8)((reg1 & 0x00ff0000) >> 16) + pd_step; + cckpd_t->cck_pd_table_jgr3[1][2][0][i] = val; + val = (u8)((reg2 & 0x00007C00) >> 10) + pd_step; + cckpd_t->cck_pd_table_jgr3[0][2][1][i] = val; + val = (u8)(((reg2 & 0xC0000000) >> 30) | + ((reg3 & 0x7) << 3)) + pd_step; + cckpd_t->cck_pd_table_jgr3[1][2][1][i] = val; + } + #endif + + #ifdef PHYDM_COMPILE_ABOVE_4SS + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + val = (u8)((reg0 & 0xff000000) >> 24) + pd_step; + cckpd_t->cck_pd_table_jgr3[0][3][0][i] = val; + + val = (u8)((reg1 & 0xff000000) >> 24) + pd_step; + cckpd_t->cck_pd_table_jgr3[1][3][0][i] = val; + + val = (u8)((reg2 & 0x000F8000) >> 15) + pd_step; + cckpd_t->cck_pd_table_jgr3[0][3][1][i] = val; + + val = (u8)((reg3 & 0x000000F8) >> 3) + pd_step; + cckpd_t->cck_pd_table_jgr3[1][3][1][i] = val; + } + #endif + } +} +#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE4*/ + +void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_lv lv; + + if (val_len != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][CCKPD]Need val_len=1\n"); + return; + } + + lv = (enum cckpd_lv)val_buf[0]; + + if (lv > CCK_PD_LV_4) { + pr_debug("[%s] warning! lv=%d\n", __func__, lv); + return; + } + + switch (cckpd_t->cckpd_hw_type) { + #ifdef PHYDM_COMPILE_CCKPD_TYPE1 + case 1: + phydm_set_cckpd_lv_type1(dm, lv); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE2 + case 2: + phydm_set_cckpd_lv_type2(dm, lv); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE3 + case 3: + phydm_set_cckpd_lv_type3(dm, lv); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE4 + case 4: + phydm_set_cck_pd_lv_type4(dm, lv); + break; + #endif + default: + pr_debug("[%s]warning\n", __func__); + break; + } +} + +boolean +phydm_stop_cck_pd_th(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & (ODM_BB_CCK_PD | ODM_BB_FA_CNT))) { + PHYDM_DBG(dm, DBG_CCKPD, "Not Support\n"); + return true; + } + + if (dm->pause_ability & ODM_BB_CCK_PD) { + PHYDM_DBG(dm, DBG_CCKPD, "Return: Pause CCKPD in LV=%d\n", + dm->pause_lv_table.lv_cckpd); + return true; + } + + if (dm->is_linked && (*dm->channel > 36)) { + PHYDM_DBG(dm, DBG_CCKPD, "Return: 5G CH=%d\n", *dm->channel); + return true; + } + return false; +} + +void phydm_cck_pd_th(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u32 cck_fa = fa_t->cnt_cck_fail; + #ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_fa_acc_struct *fa_acc_t = &dm->false_alm_cnt_acc; + #endif + + PHYDM_DBG(dm, DBG_CCKPD, "[%s] ======>\n", __func__); + + if (phydm_stop_cck_pd_th(dm)) + return; + + #ifdef PHYDM_TDMA_DIG_SUPPORT + if (dm->original_dig_restore) + cck_fa = fa_t->cnt_cck_fail; + else + cck_fa = fa_acc_t->cnt_cck_fail_1sec; + #endif + + if (cckpd_t->cck_fa_ma == CCK_FA_MA_RESET) + cckpd_t->cck_fa_ma = cck_fa; + else + cckpd_t->cck_fa_ma = (cckpd_t->cck_fa_ma * 3 + cck_fa) >> 2; + + PHYDM_DBG(dm, DBG_CCKPD, + "IGI=0x%x, rssi_min=%d, cck_fa=%d, cck_fa_ma=%d\n", + dm->dm_dig_table.cur_ig_value, dm->rssi_min, + cck_fa, cckpd_t->cck_fa_ma); + + switch (cckpd_t->cckpd_hw_type) { + #ifdef PHYDM_COMPILE_CCKPD_TYPE1 + case 1: + phydm_cckpd_type1(dm); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE2 + case 2: + phydm_cckpd_type2(dm); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE3 + case 3: + phydm_cckpd_type3(dm); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE4 + case 4: + phydm_cckpd_type4(dm); + break; + #endif + default: + pr_debug("[%s]warning\n", __func__); + break; + } +} + +void phydm_cck_pd_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + + if (dm->support_ic_type & CCK_PD_IC_TYPE1) + cckpd_t->cckpd_hw_type = 1; + else if (dm->support_ic_type & CCK_PD_IC_TYPE2) + cckpd_t->cckpd_hw_type = 2; + else if (dm->support_ic_type & CCK_PD_IC_TYPE3) + cckpd_t->cckpd_hw_type = 3; + else if (dm->support_ic_type & CCK_PD_IC_TYPE4) + cckpd_t->cckpd_hw_type = 4; + + PHYDM_DBG(dm, DBG_CCKPD, "[%s] cckpd_hw_type=%d\n", + __func__, cckpd_t->cckpd_hw_type); + + cckpd_t->cck_pd_lv = CCK_PD_LV_INIT; + cckpd_t->cck_n_rx = 0xff; + cckpd_t->cck_bw = CHANNEL_WIDTH_MAX; + + switch (cckpd_t->cckpd_hw_type) { + #ifdef PHYDM_COMPILE_CCKPD_TYPE1 + case 1: + phydm_set_cckpd_lv_type1(dm, CCK_PD_LV_0); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE2 + case 2: + cckpd_t->aaa_default = odm_read_1byte(dm, 0xaaa) & 0x1f; + phydm_set_cckpd_lv_type2(dm, CCK_PD_LV_0); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE3 + case 3: + phydm_cck_pd_init_type3(dm); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE4 + case 4: + phydm_cck_pd_init_type4(dm); + break; + #endif + default: + pr_debug("[%s]warning\n", __func__); + break; + } +} +#endif /*#ifdef PHYDM_SUPPORT_CCKPD*/ + diff --git a/hal/phydm/phydm_cck_pd.h b/hal/phydm/phydm_cck_pd.h new file mode 100644 index 0000000..a7b5176 --- /dev/null +++ b/hal/phydm/phydm_cck_pd.h @@ -0,0 +1,154 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_CCK_PD_H__ +#define __PHYDM_CCK_PD_H__ + +#define CCK_PD_VERSION "3.0" + +/*@ + * 1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ +#define CCK_FA_MA_RESET 0xffffffff + +/*@Run time flag of CCK_PD HW type*/ +#define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\ + ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\ + ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\ + ODM_RTL8195A | ODM_RTL8188F) + +#define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\ + ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/ + +#define CCK_PD_IC_TYPE3 ODM_RTL8192F /*@extend for different bw & path*/ + +#define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/ + +/*@Compile time flag of CCK_PD HW type*/ +#if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\ + RTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\ + RTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\ + RTL8195A_SUPPORT || RTL8188F_SUPPORT) + #define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/ +#endif + +#if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\ + RTL8710B_SUPPORT || RTL8195B_SUPPORT) + #define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/ +#endif + +#if (RTL8192F_SUPPORT) + #define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/ +#endif + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + #define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/ +#endif +/*@ + * 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ +enum cckpd_lv { + CCK_PD_LV_INIT = 0xff, + CCK_PD_LV_0 = 0, + CCK_PD_LV_1 = 1, + CCK_PD_LV_2 = 2, + CCK_PD_LV_3 = 3, + CCK_PD_LV_4 = 4, + CCK_PD_LV_MAX = 5 +}; + +enum cckpd_mode { + CCK_BW20_1R = 0, + CCK_BW20_2R = 1, + CCK_BW20_3R = 2, + CCK_BW20_4R = 3, + CCK_BW40_1R = 4, + CCK_BW40_2R = 5, + CCK_BW40_3R = 6, + CCK_BW40_4R = 7 +}; + +/*@ + * 1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +#ifdef PHYDM_SUPPORT_CCKPD +struct phydm_cckpd_struct { + u8 cckpd_hw_type; + u8 cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/ + u32 cck_fa_ma; + u8 rvrt_val; + u8 pause_lv; + u8 cck_n_rx; + enum channel_width cck_bw; + enum cckpd_lv cck_pd_lv; + #ifdef PHYDM_COMPILE_CCKPD_TYPE2 + u8 cck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/ + u8 aaa_default; /*@Init cs_ratio value - 0xaaa*/ + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE3 + /*Default value*/ + u8 cck_pd_20m_1r; + u8 cck_pd_20m_2r; + u8 cck_pd_40m_1r; + u8 cck_pd_40m_2r; + u8 cck_cs_ratio_20m_1r; + u8 cck_cs_ratio_20m_2r; + u8 cck_cs_ratio_40m_1r; + u8 cck_cs_ratio_40m_2r; + /*Current value*/ + u8 cur_cck_pd_20m_1r; + u8 cur_cck_pd_20m_2r; + u8 cur_cck_pd_40m_1r; + u8 cur_cck_pd_40m_2r; + u8 cur_cck_cs_ratio_20m_1r; + u8 cur_cck_cs_ratio_20m_2r; + u8 cur_cck_cs_ratio_40m_1r; + u8 cur_cck_cs_ratio_40m_2r; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE4 + /*@[bw][nrx][0:PD/1:CS][lv]*/ + u8 cck_pd_table_jgr3[2][4][2][CCK_PD_LV_MAX]; + #endif +}; +#endif + +/*@ + * 1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ +void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len); + +void phydm_cck_pd_th(void *dm_void); + +void phydm_cck_pd_init(void *dm_void); +#endif diff --git a/hal/phydm/phydm_ccx.c b/hal/phydm/phydm_ccx.c index a6164fb..6a87080 100644 --- a/hal/phydm/phydm_ccx.c +++ b/hal/phydm/phydm_ccx.c @@ -1,392 +1,1839 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + #include "mp_precomp.h" #include "phydm_precomp.h" -/*Set NHM period, threshold, disable ignore cca or not, disable ignore txon or not*/ -void -phydm_nhm_setting( - void *p_dm_void, - u8 nhm_setting -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - if (nhm_setting == SET_NHM_SETTING) { - - /*Set inexclude_cca, inexclude_txon*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->nhm_inexclude_cca); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->nhm_inexclude_txon); - - /*Set NHM period*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period); - - /*Set NHM threshold*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th[0]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th[1]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th[2]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th[3]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th[4]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th[5]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th[6]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th[7]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th[8]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th[9]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th[10]); - - /*CCX EN*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8), CCX_EN); - - } else if (nhm_setting == STORE_NHM_SETTING) { - - /*Store pervious disable_ignore_cca, disable_ignore_txon*/ - ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9)); - ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10)); - - /*Store pervious NHM period*/ - ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD); - - /*Store NHM threshold*/ - ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0); - ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1); - ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2); - ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3); - ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0); - ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1); - ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2); - ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3); - ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0); - ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2); - ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3); - } else if (nhm_setting == RESTORE_NHM_SETTING) { - - /*Set disable_ignore_cca, disable_ignore_txon*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->NHM_inexclude_cca_restore); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->NHM_inexclude_txon_restore); - - /*Set NHM period*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period); - - /*Set NHM threshold*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th_restore[0]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th_restore[1]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th_restore[2]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th_restore[3]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th_restore[4]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th_restore[5]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th_restore[6]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th_restore[7]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th_restore[8]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th_restore[9]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th_restore[10]); - } else - return; +void phydm_ccx_hw_restart(void *dm_void) + /*@Will Restart NHM/CLM/FAHM simultaneously*/ +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg1 = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + reg1 = R_0x994; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + reg1 = R_0x1e60; + #endif + else + reg1 = R_0x890; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + odm_set_bb_reg(dm, reg1, 0x7, 0x0); /*@disable NHM,CLM, FAHM*/ + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x994, BIT(8), 0x0); + odm_set_bb_reg(dm, R_0x994, BIT(8), 0x1); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0x1e60, BIT(8), 0x0); + odm_set_bb_reg(dm, R_0x1e60, BIT(8), 0x1); + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0x890, BIT(8), 0x0); + odm_set_bb_reg(dm, R_0x890, BIT(8), 0x1); + } +} + +#ifdef FAHM_SUPPORT + +u16 phydm_hw_divider(void *dm_void, u16 numerator, u16 denumerator) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 result = DEVIDER_ERROR; + u32 tmp_u32 = ((numerator << 16) | denumerator); + u32 reg_devider_input; + u32 reg; + u8 i; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg_devider_input = 0x1cbc; + reg = 0x1f98; + } else { + reg_devider_input = 0x980; + reg = 0x9f0; } - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - - if (nhm_setting == SET_NHM_SETTING) { - - /*Set disable_ignore_cca, disable_ignore_txon*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->nhm_inexclude_cca); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->nhm_inexclude_txon); - - /*Set NHM period*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period); - - /*Set NHM threshold*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th[0]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th[1]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th[2]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th[3]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th[4]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th[5]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th[6]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th[7]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th[8]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th[9]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th[10]); - - /*CCX EN*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(8), CCX_EN); - } else if (nhm_setting == STORE_NHM_SETTING) { - - /*Store pervious disable_ignore_cca, disable_ignore_txon*/ - ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9)); - ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10)); - - /*Store pervious NHM period*/ - ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD); - - /*Store NHM threshold*/ - ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0); - ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1); - ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2); - ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3); - ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0); - ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1); - ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2); - ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3); - ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0); - ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2); - ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3); - - } else if (nhm_setting == RESTORE_NHM_SETTING) { - - /*Set disable_ignore_cca, disable_ignore_txon*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->NHM_inexclude_cca_restore); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->NHM_inexclude_txon_restore); - - /*Set NHM period*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period_restore); - - /*Set NHM threshold*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th_restore[0]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th_restore[1]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th_restore[2]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th_restore[3]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th_restore[4]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th_restore[5]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th_restore[6]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th_restore[7]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th_restore[8]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th_restore[9]); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th_restore[10]); - } else - return; + odm_set_bb_reg(dm, reg_devider_input, MASKDWORD, tmp_u32); + + for (i = 0; i < 10; i++) { + ODM_delay_ms(1); + if (odm_get_bb_reg(dm, reg, BIT(24))) { + /*@Chk HW rpt is ready*/ + + result = (u16)odm_get_bb_reg(dm, reg, MASKBYTE2); + break; + } + } + return result; +} + +void phydm_fahm_trigger(void *dm_void, u16 tgr_period) +{ /*@unit (4us)*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fahm_reg1; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x1cf8, 0xffff00, tgr_period); + + fahm_reg1 = 0x994; + } else { + odm_set_bb_reg(dm, R_0x978, 0xff000000, (tgr_period & 0xff)); + odm_set_bb_reg(dm, R_0x97c, 0xff, (tgr_period & 0xff00) >> 8); + + fahm_reg1 = 0x890; + } + + odm_set_bb_reg(dm, fahm_reg1, BIT(2), 0); + odm_set_bb_reg(dm, fahm_reg1, BIT(2), 1); +} + +void phydm_fahm_set_valid_cnt(void *dm_void, u8 numerator_sel, + u8 denominator_sel) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u32 fahm_reg1; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (ccx_info->fahm_nume_sel == numerator_sel && + ccx_info->fahm_denom_sel == denominator_sel) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "no need to update\n"); + return; + } + + ccx_info->fahm_nume_sel = numerator_sel; + ccx_info->fahm_denom_sel = denominator_sel; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + fahm_reg1 = 0x994; + else + fahm_reg1 = 0x890; + + odm_set_bb_reg(dm, fahm_reg1, 0xe0, numerator_sel); + odm_set_bb_reg(dm, fahm_reg1, 0x7000, denominator_sel); +} + +void phydm_fahm_get_result(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 fahm_cnt[12]; /*packet count*/ + u16 fahm_rpt[12]; /*percentage*/ + u16 denominator; /*@fahm_denominator packet count*/ + u32 reg_rpt, reg_rpt_2; + u32 reg_tmp; + boolean is_ready = false; + u8 i; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg_rpt = 0x1f80; + reg_rpt_2 = 0x1f98; + } else { + reg_rpt = 0x9d8; + reg_rpt_2 = 0x9f0; + } + + for (i = 0; i < 3; i++) { + if (odm_get_bb_reg(dm, reg_rpt_2, BIT(31))) { + /*@Chk HW rpt is ready*/ + is_ready = true; + break; + } + ODM_delay_ms(1); + } + + if (!is_ready) + return; + /*@Get FAHM Denominator*/ + denominator = (u16)odm_get_bb_reg(dm, reg_rpt_2, MASKLWORD); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "Reg[0x%x] fahm_denmrtr = %d\n", reg_rpt_2, + denominator); + + /*@Get FAHM nemerator*/ + for (i = 0; i < 6; i++) { + reg_tmp = odm_get_bb_reg(dm, reg_rpt + (i << 2), MASKDWORD); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "Reg[0x%x] fahm_denmrtr = %d\n", + reg_rpt + (i * 4), reg_tmp); + + fahm_cnt[i * 2] = (u16)(reg_tmp & MASKLWORD); + fahm_cnt[i * 2 + 1] = (u16)((reg_tmp & MASKHWORD) >> 16); } + + for (i = 0; i < 12; i++) + fahm_rpt[i] = phydm_hw_divider(dm, fahm_cnt[i], denominator); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "FAHM_RPT_cnt[10:0]=[%d, %d, %d, %d, %d(IGI), %d, %d, %d, %d, %d, %d, %d]\n", + fahm_cnt[11], fahm_cnt[10], fahm_cnt[9], + fahm_cnt[8], fahm_cnt[7], fahm_cnt[6], + fahm_cnt[5], fahm_cnt[4], fahm_cnt[3], + fahm_cnt[2], fahm_cnt[1], fahm_cnt[0]); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "FAHM_RPT[10:0]=[%d, %d, %d, %d, %d(IGI), %d, %d, %d, %d, %d, %d, %d]\n", + fahm_rpt[11], fahm_rpt[10], fahm_rpt[9], fahm_rpt[8], + fahm_rpt[7], fahm_rpt[6], fahm_rpt[5], fahm_rpt[4], + fahm_rpt[3], fahm_rpt[2], fahm_rpt[1], fahm_rpt[0]); } -void -phydm_nhm_trigger( - void *p_dm_void -) +void phydm_fahm_set_th_by_igi(void *dm_void, u8 igi) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u32 val = 0; + u8 f_th[11]; /*@FAHM Threshold*/ + u8 rssi_th[11]; /*@in RSSI scale*/ + u8 th_gap = 2 * IGI_TO_NHM_TH_MULTIPLIER; /*unit is 0.5dB for FAHM*/ + u8 i; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (ccx_info->env_mntr_igi == igi) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "No need to update FAHM_th, IGI=0x%x\n", + ccx_info->env_mntr_igi); + return; + } + + ccx_info->env_mntr_igi = igi; /*@bkp IGI*/ - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (igi >= CCA_CAP) + f_th[0] = (igi - CCA_CAP) * IGI_TO_NHM_TH_MULTIPLIER; + else + f_th[0] = 0; - /*Trigger NHM*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1); - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + rssi_th[0] = igi - 10 - CCA_CAP; + + for (i = 1; i <= 10; i++) { + f_th[i] = f_th[0] + th_gap * i; + rssi_th[i] = rssi_th[0] + (i << 1); + } - /*Trigger NHM*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "FAHM_RSSI_th[10:0]=[%d, %d, %d, (IGI)%d, %d, %d, %d, %d, %d, %d, %d]\n", + rssi_th[10], rssi_th[9], rssi_th[8], rssi_th[7], rssi_th[6], + rssi_th[5], rssi_th[4], rssi_th[3], rssi_th[2], rssi_th[1], + rssi_th[0]); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + val = BYTE_2_DWORD(0, f_th[2], f_th[1], f_th[0]); + odm_set_bb_reg(dm, R_0x1c38, 0xffffff00, val); + val = BYTE_2_DWORD(0, f_th[5], f_th[4], f_th[3]); + odm_set_bb_reg(dm, R_0x1c78, 0xffffff00, val); + val = BYTE_2_DWORD(0, 0, f_th[7], f_th[6]); + odm_set_bb_reg(dm, R_0x1c7c, 0xffff0000, val); + val = BYTE_2_DWORD(0, f_th[10], f_th[9], f_th[8]); + odm_set_bb_reg(dm, R_0x1cb8, 0xffffff00, val); + } else { + val = BYTE_2_DWORD(f_th[3], f_th[2], f_th[1], f_th[0]); + odm_set_bb_reg(dm, R_0x970, MASKDWORD, val); + val = BYTE_2_DWORD(f_th[7], f_th[6], f_th[5], f_th[4]); + odm_set_bb_reg(dm, R_0x974, MASKDWORD, val); + BYTE_2_DWORD(0, f_th[10], f_th[9], f_th[8]); + odm_set_bb_reg(dm, R_0x978, 0xffffff, val); } } -void -phydm_get_nhm_result( - void *p_dm_void -) +void phydm_fahm_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 value32; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u32 fahm_reg1; + u8 denumerator_sel = 0; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "IGI=0x%x\n", + dm->dm_dig_table.cur_ig_value); - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC); - ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0); - ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8); - ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24); + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + fahm_reg1 = 0x994; + else + fahm_reg1 = 0x890; - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); - ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0); - ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8); - ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24); + ccx_info->fahm_period = 65535; - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT11_TO_CNT8_11AC); - ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0); - ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8); - ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24); + odm_set_bb_reg(dm, fahm_reg1, 0x6, 3); /*@FAHM HW block enable*/ - /*Get NHM duration*/ - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC); - ccx_info->NHM_duration = (u16)(value32 & MASKLWORD); + denumerator_sel = FAHM_INCLD_FA | FAHM_INCLD_CRC_OK | FAHM_INCLD_CRC_ER; + phydm_fahm_set_valid_cnt(dm, FAHM_INCLD_FA, denumerator_sel); + phydm_fahm_set_th_by_igi(dm, dm->dm_dig_table.cur_ig_value); +} +void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i; + + for (i = 0; i < 2; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); } - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1: trigger, 2:get result}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3: MNTR mode sel} {1: driver, 2. FW}\n"); + return; + } else if (var1[0] == 1) { /* Set & trigger CLM */ + + phydm_fahm_set_th_by_igi(dm, dm->dm_dig_table.cur_ig_value); + phydm_fahm_trigger(dm, ccx_info->fahm_period); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Monitor FAHM for %d * 4us\n", ccx_info->fahm_period); + + } else if (var1[0] == 2) { /* @Get CLM results */ - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N); - ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0); - ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8); - ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24); + phydm_fahm_get_result(dm); + PDM_SNPF(out_len, used, output + used, out_len - used, + "FAHM_result=%d us\n", (ccx_info->clm_result << 2)); - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); - ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0); - ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8); - ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Error\n"); + } + + *_used = used; + *_out_len = out_len; +} - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT9_TO_CNT8_11N); - ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24); +#endif /*@#ifdef FAHM_SUPPORT*/ - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); - ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16); - ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24); +#ifdef NHM_SUPPORT + +void phydm_nhm_racing_release(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 value32; - /*Get NHM duration*/ - value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); - ccx_info->NHM_duration = (u16)(value32 & MASKLWORD); + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->nhm_set_lv); + ccx->nhm_ongoing = false; + ccx->nhm_set_lv = NHM_RELEASE; + + if (!(ccx->nhm_app == NHM_BACKGROUND || ccx->nhm_app == NHM_ACS)) { + phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, + PHYDM_PAUSE_LEVEL_1, 1, &value32); } + ccx->nhm_app = NHM_BACKGROUND; } -boolean -phydm_check_nhm_ready( - void *p_dm_void -) +u8 phydm_nhm_racing_ctrl(void *dm_void, enum phydm_nhm_level nhm_lv) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 value32 = 0; - u8 i; - boolean ret = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 set_result = PHYDM_SET_SUCCESS; + /*@acquire to control NHM API*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_ongoing=%d, lv:(%d)->(%d)\n", + ccx->nhm_ongoing, ccx->nhm_set_lv, nhm_lv); + if (ccx->nhm_ongoing) { + if (nhm_lv <= ccx->nhm_set_lv) { + set_result = PHYDM_SET_FAIL; + } else { + phydm_ccx_hw_restart(dm); + ccx->nhm_ongoing = false; + } + } - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (set_result) + ccx->nhm_set_lv = nhm_lv; - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm racing success=%d\n", set_result); + return set_result; +} - for (i = 0; i < 200; i++) { +void phydm_nhm_trigger(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 nhm_reg1 = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + nhm_reg1 = R_0x994; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + nhm_reg1 = R_0x1e60; + #endif + else + nhm_reg1 = R_0x890; + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + /*Trigger NHM*/ + pdm_set_reg(dm, nhm_reg1, BIT(1), 0); + pdm_set_reg(dm, nhm_reg1, BIT(1), 1); + ccx->nhm_trigger_time = dm->phydm_sys_up_time; + ccx->nhm_rpt_stamp++; + ccx->nhm_ongoing = true; +} - ODM_delay_ms(1); - if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) { - ret = 1; +boolean +phydm_nhm_check_rdy(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean is_ready = false; + u32 reg1 = 0, reg1_bit = 0; +#if (ENV_MNTR_DBG || ENV_MNTR_DBG_1) + u16 i = 0; + u64 start_time, progressing_time; + u32 reg_val_start = 0, reg_val = 0; + u8 print_rpt = 0; +#endif + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = 0xfb4; + reg1_bit = 16; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + reg1 = 0x2d4c; + reg1_bit = 16; + #endif + } else { + reg1 = 0x8b4; + if (dm->support_ic_type == ODM_RTL8710B) { + reg1_bit = 25; + } else { + reg1_bit = 17; + } + } +#if (ENV_MNTR_DBG_1) + start_time = odm_get_current_time(dm); + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM_period = %d\n", + odm_get_bb_reg(dm, R_0x990, MASKDWORD)); + + /*NHM trigger bit*/ + reg_val_start = odm_get_bb_reg(dm, R_0x994, BIT(1)); + PHYDM_DBG(dm, DBG_ENV_MNTR, "reg_val_start = %d\n", + reg_val_start); + + for (i = 0; i <= 400; i++) { + if (print_rpt == 0) { + reg_val = odm_get_bb_reg(dm, R_0x994, BIT(1)); + if (reg_val != reg_val_start) { + print_rpt = 1; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Trig[%d] (%d) -> (%d)\n", + i, reg_val_start, reg_val); + } + } + + if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) { + is_ready = true; break; } + ODM_delay_ms(1); } + } else { + if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) + is_ready = true; } - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + progressing_time = odm_get_progressing_time(dm, start_time); + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d, i=%d, NHM_polling_time=%lld\n", + is_ready, i, progressing_time); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD); +#elif (ENV_MNTR_DBG) + start_time = odm_get_current_time(dm); + for (i = 0; i <= 400; i++) { + if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) { + is_ready = true; + break; + } + ODM_delay_ms(1); + } + progressing_time = odm_get_progressing_time(dm, start_time); + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d, i=%d, NHM_polling_time=%lld\n", + is_ready, i, progressing_time); +#else + if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) + is_ready = true; - for (i = 0; i < 200; i++) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d\n", is_ready); - ODM_delay_ms(1); - if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) { - ret = 1; - break; - } +#endif + return is_ready; +} + +void phydm_nhm_get_utility(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 nhm_rpt_non_0 = 0; + + if (ccx->nhm_rpt_sum >= ccx->nhm_result[0]) { + nhm_rpt_non_0 = ccx->nhm_rpt_sum - ccx->nhm_result[0]; + ccx->nhm_ratio = (nhm_rpt_non_0 * 100) >> 8; + } else { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] nhm_rpt_sum invalid\n"); + ccx->nhm_ratio = 0; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_ratio=%d\n", ccx->nhm_ratio); +} + +boolean +phydm_nhm_get_result(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 value32; + u8 i; + u32 nhm_reg1 = 0; + u16 nhm_rpt_sum_tmp = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + nhm_reg1 = R_0x994; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + nhm_reg1 = R_0x1e60; + #endif + else + nhm_reg1 = R_0x890; + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + pdm_set_reg(dm, nhm_reg1, BIT(1), 0); + +#if (ENV_MNTR_DBG_2) + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[DBG][3] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n", + odm_get_bb_reg(dm, 0xc50, MASKDWORD), + odm_get_bb_reg(dm, 0x994, MASKDWORD), + odm_get_bb_reg(dm, 0x998, MASKDWORD)); +#endif + + if (!(phydm_nhm_check_rdy(dm))) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM report Fail\n"); + phydm_nhm_racing_release(dm); + return false; + } + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + value32 = odm_read_4byte(dm, 0xfa8); + odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4); + + value32 = odm_read_4byte(dm, 0xfac); + odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4); + + value32 = odm_read_4byte(dm, 0xfb0); + odm_move_memory(dm, &ccx->nhm_result[8], &value32, 4); + + /*@Get NHM duration*/ + value32 = odm_read_4byte(dm, 0xfb4); + ccx->nhm_duration = (u16)(value32 & MASKLWORD); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + value32 = odm_read_4byte(dm, 0x2d40); + odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4); + + value32 = odm_read_4byte(dm, 0x2d44); + odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4); + + value32 = odm_read_4byte(dm, 0x2d48); + odm_move_memory(dm, &ccx->nhm_result[8], &value32, 4); + + /*@Get NHM duration*/ + value32 = odm_read_4byte(dm, 0x2d4c); + ccx->nhm_duration = (u16)(value32 & MASKLWORD); + #endif + } else { + value32 = odm_read_4byte(dm, 0x8d8); + odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4); + + value32 = odm_read_4byte(dm, 0x8dc); + odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4); + + value32 = odm_get_bb_reg(dm, R_0x8d0, 0xffff0000); + odm_move_memory(dm, &ccx->nhm_result[8], &value32, 2); + + value32 = odm_read_4byte(dm, 0x8d4); + + ccx->nhm_result[10] = (u8)((value32 & MASKBYTE2) >> 16); + ccx->nhm_result[11] = (u8)((value32 & MASKBYTE3) >> 24); + + /*@Get NHM duration*/ + ccx->nhm_duration = (u16)(value32 & MASKLWORD); + } + + /* sum all nhm_result */ + if (ccx->nhm_period >= 65530) { + value32 = (ccx->nhm_duration * 100) >> 16; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "NHM valid time = %d, valid: %d percent\n", + ccx->nhm_duration, value32); + } + + for (i = 0; i < NHM_RPT_NUM; i++) + nhm_rpt_sum_tmp += (u16)ccx->nhm_result[i]; + + ccx->nhm_rpt_sum = (u8)nhm_rpt_sum_tmp; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "NHM_Rpt[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n", + ccx->nhm_rpt_stamp, ccx->nhm_result[11], ccx->nhm_result[10], + ccx->nhm_result[9], ccx->nhm_result[8], ccx->nhm_result[7], + ccx->nhm_result[6], ccx->nhm_result[5], ccx->nhm_result[4], + ccx->nhm_result[3], ccx->nhm_result[2], ccx->nhm_result[1], + ccx->nhm_result[0]); + + phydm_nhm_racing_release(dm); + +#if (ENV_MNTR_DBG_2) + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[DBG][4] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n", + odm_get_bb_reg(dm, 0xc50, MASKDWORD), + odm_get_bb_reg(dm, 0x994, MASKDWORD), + odm_get_bb_reg(dm, 0x998, MASKDWORD)); +#endif + + if (nhm_rpt_sum_tmp > 255) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[Warning] Invalid NHM RPT, total=%d\n", + nhm_rpt_sum_tmp); + return false; + } + + return true; +} + +void phydm_nhm_set_th_reg(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 reg1 = 0, reg2 = 0, reg3 = 0, reg4 = 0, reg4_bit = 0; + u32 val = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = 0x994; + reg2 = 0x998; + reg3 = 0x99c; + reg4 = 0x9a0; + reg4_bit = MASKBYTE0; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + reg1 = 0x1e60; + reg2 = 0x1e44; + reg3 = 0x1e48; + reg4 = 0x1e5c; + reg4_bit = MASKBYTE2; + #endif + } else { + reg1 = 0x890; + reg2 = 0x898; + reg3 = 0x89c; + reg4 = 0xe28; + reg4_bit = MASKBYTE0; + } + + /*Set NHM threshold*/ /*Unit: PWdB U(8,1)*/ + val = BYTE_2_DWORD(ccx->nhm_th[3], ccx->nhm_th[2], + ccx->nhm_th[1], ccx->nhm_th[0]); + pdm_set_reg(dm, reg2, MASKDWORD, val); + val = BYTE_2_DWORD(ccx->nhm_th[7], ccx->nhm_th[6], + ccx->nhm_th[5], ccx->nhm_th[4]); + pdm_set_reg(dm, reg3, MASKDWORD, val); + pdm_set_reg(dm, reg4, reg4_bit, ccx->nhm_th[8]); + val = BYTE_2_DWORD(0, 0, ccx->nhm_th[10], ccx->nhm_th[9]); + pdm_set_reg(dm, reg1, 0xffff0000, val); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Update NHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n", + ccx->nhm_th[10], ccx->nhm_th[9], ccx->nhm_th[8], + ccx->nhm_th[7], ccx->nhm_th[6], ccx->nhm_th[5], + ccx->nhm_th[4], ccx->nhm_th[3], ccx->nhm_th[2], + ccx->nhm_th[1], ccx->nhm_th[0]); +} + +boolean +phydm_nhm_th_update_chk(void *dm_void, enum nhm_application nhm_app, u8 *nhm_th, + u32 *igi_new) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean is_update = false; + u8 igi_curr = phydm_get_igi(dm, BB_PATH_A); + u8 nhm_igi_th_11k_low[NHM_TH_NUM] = {0x12, 0x15, 0x18, 0x1b, 0x1e, + 0x23, 0x28, 0x2c, 0x78, + 0x78, 0x78}; + u8 nhm_igi_th_11k_high[NHM_TH_NUM] = {0x1e, 0x23, 0x28, 0x2d, 0x32, + 0x37, 0x78, 0x78, 0x78, 0x78, + 0x78}; + u8 nhm_igi_th_xbox[NHM_TH_NUM] = {0x1a, 0x2c, 0x2e, 0x30, 0x32, 0x34, + 0x36, 0x38, 0x3a, 0x3c, 0x3d}; + u8 i; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "App=%d, nhm_igi=0x%x, igi_curr=0x%x\n", + nhm_app, ccx->nhm_igi, igi_curr); + + if (igi_curr < 0x10) /* Protect for invalid IGI*/ + return false; + + switch (nhm_app) { + case NHM_BACKGROUND: /*@Get IGI form driver parameter(cur_ig_value)*/ + case NHM_ACS: + if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) { + is_update = true; + *igi_new = (u32)igi_curr; + nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP); + for (i = 1; i <= 10; i++) + nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(2 * i); + } + break; + + case IEEE_11K_HIGH: + is_update = true; + *igi_new = 0x2c; + for (i = 0; i < NHM_TH_NUM; i++) + nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_high[i]); + break; + + case IEEE_11K_LOW: + is_update = true; + *igi_new = 0x20; + for (i = 0; i < NHM_TH_NUM; i++) + nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_low[i]); + break; + + case INTEL_XBOX: + is_update = true; + *igi_new = 0x36; + for (i = 0; i < NHM_TH_NUM; i++) + nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_xbox[i]); + break; + + case NHM_DBG: /*@Get IGI form register*/ + igi_curr = phydm_get_igi(dm, BB_PATH_A); + if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) { + is_update = true; + *igi_new = (u32)igi_curr; + nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP); + for (i = 1; i <= 10; i++) + nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(2 * i); + } + break; + } + + if (is_update) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[Update NHM_TH] igi_RSSI=%d\n", + IGI_2_RSSI(*igi_new)); + + for (i = 0; i < NHM_TH_NUM; i++) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM_th[%d](RSSI) = %d\n", + i, NTH_TH_2_RSSI(nhm_th[i])); + } + } else { + PHYDM_DBG(dm, DBG_ENV_MNTR, "No need to update NHM_TH\n"); + } + return is_update; +} + +void phydm_nhm_set(void *dm_void, enum nhm_option_txon_all include_tx, + enum nhm_option_cca_all include_cca, + enum nhm_divider_opt_all divi_opt, + enum nhm_application nhm_app, u16 period) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 nhm_th[NHM_TH_NUM] = {0}; + u32 igi = 0x20; + u32 reg1 = 0, reg2 = 0; + u32 val_tmp = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "incld{tx, cca}={%d, %d}, divi_opt=%d, period=%d\n", + include_tx, include_cca, divi_opt, period); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = 0x994; + reg2 = 0x990; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + reg1 = 0x1e60; + reg2 = 0x1e40; + #endif + } else { + reg1 = 0x890; + reg2 = 0x894; + } + + /*Set disable_ignore_cca, disable_ignore_txon, ccx_en*/ + if (include_tx != ccx->nhm_include_txon || + include_cca != ccx->nhm_include_cca || + divi_opt != ccx->nhm_divider_opt) { + /* some old ic is not supported on NHM divider option */ + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B | + ODM_RTL8195A | ODM_RTL8192E)) { + val_tmp = (u32)((include_tx << 2) | + (include_cca << 1) | 1); + pdm_set_reg(dm, reg1, 0x700, val_tmp); + } else { + val_tmp = (u32)BIT_2_BYTE(divi_opt, include_tx, + include_cca, 1); + pdm_set_reg(dm, reg1, 0xf00, val_tmp); + } + ccx->nhm_include_txon = include_tx; + ccx->nhm_include_cca = include_cca; + ccx->nhm_divider_opt = divi_opt; + #if 0 + PHYDM_DBG(dm, DBG_ENV_MNTR, + "val_tmp=%d, incld{tx, cca}={%d, %d}, divi_opt=%d, period=%d\n", + val_tmp, include_tx, include_cca, divi_opt, period); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "0x994=0x%x\n", + odm_get_bb_reg(dm, 0x994, 0xf00)); + #endif + } + + /*Set NHM period*/ + if (period != ccx->nhm_period) { + pdm_set_reg(dm, reg2, MASKHWORD, period); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Update NHM period ((%d)) -> ((%d))\n", + ccx->nhm_period, period); + + ccx->nhm_period = period; + } + + /*Set NHM threshold*/ + if (phydm_nhm_th_update_chk(dm, nhm_app, &(nhm_th[0]), &igi)) { + /*Pause IGI*/ + if (nhm_app == NHM_BACKGROUND || nhm_app == NHM_ACS) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "DIG Free Run\n"); + } else if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, + PHYDM_PAUSE_LEVEL_1, 1, &igi) + == PAUSE_FAIL) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG Fail\n"); + return; + } else { + PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG=0x%x\n", igi); } + ccx->nhm_app = nhm_app; + ccx->nhm_igi = (u8)igi; + odm_move_memory(dm, &ccx->nhm_th[0], &nhm_th, NHM_TH_NUM); + + /*Set NHM th*/ + phydm_nhm_set_th_reg(dm); + } +} + +u8 phydm_nhm_mntr_set(void *dm_void, struct nhm_para_info *nhm_para) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 nhm_time = 0; /*unit: 4us*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (nhm_para->mntr_time == 0) + return PHYDM_SET_FAIL; + + if (nhm_para->nhm_lv >= NHM_MAX_NUM) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Wrong LV=%d\n", nhm_para->nhm_lv); + return PHYDM_SET_FAIL; + } + + if (phydm_nhm_racing_ctrl(dm, nhm_para->nhm_lv) == PHYDM_SET_FAIL) + return PHYDM_SET_FAIL; + + if (nhm_para->mntr_time >= 262) + nhm_time = NHM_PERIOD_MAX; + else + nhm_time = nhm_para->mntr_time * MS_TO_4US_RATIO; + + phydm_nhm_set(dm, nhm_para->incld_txon, nhm_para->incld_cca, + nhm_para->div_opt, nhm_para->nhm_app, nhm_time); + + return PHYDM_SET_SUCCESS; +} + +/*@Environment Monitor*/ +boolean +phydm_nhm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct nhm_para_info nhm_para = {0}; + boolean nhm_chk_result = false; + u32 sys_return_time; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (ccx->nhm_manual_ctrl) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM in manual ctrl\n"); + return nhm_chk_result; + } + sys_return_time = ccx->nhm_trigger_time + MAX_ENV_MNTR_TIME; + if (ccx->nhm_app != NHM_BACKGROUND && + (sys_return_time > dm->phydm_sys_up_time)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "nhm_app=%d, trigger_time %d, sys_time=%d\n", + ccx->nhm_app, ccx->nhm_trigger_time, + dm->phydm_sys_up_time); + + return nhm_chk_result; } - return ret; + + /*@[NHM get result & calculate Utility----------------------------*/ + if (phydm_nhm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n"); + phydm_nhm_get_utility(dm); + } + + /*@[NHM trigger]-------------------------------------------------*/ + nhm_para.incld_txon = NHM_EXCLUDE_TXON; + nhm_para.incld_cca = NHM_EXCLUDE_CCA; + nhm_para.div_opt = NHM_CNT_ALL; + nhm_para.nhm_app = NHM_BACKGROUND; + nhm_para.nhm_lv = NHM_LV_1; + nhm_para.mntr_time = monitor_time; + + nhm_chk_result = phydm_nhm_mntr_set(dm, &nhm_para); + + return nhm_chk_result; } -void -phydm_store_nhm_setting( - void *p_dm_void -) +void phydm_nhm_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "cur_igi=0x%x\n", + dm->dm_dig_table.cur_ig_value); + + ccx->nhm_app = NHM_BACKGROUND; + ccx->nhm_igi = 0xff; + + /*Set NHM threshold*/ + ccx->nhm_ongoing = false; + ccx->nhm_set_lv = NHM_RELEASE; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (phydm_nhm_th_update_chk(dm, ccx->nhm_app, &ccx->nhm_th[0], + (u32 *)&ccx->nhm_igi)) + phydm_nhm_set_th_reg(dm); + ccx->nhm_period = 0; - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + ccx->nhm_include_cca = NHM_CCA_INIT; + ccx->nhm_include_txon = NHM_TXON_INIT; + ccx->nhm_divider_opt = NHM_CNT_INIT; + ccx->nhm_manual_ctrl = 0; + ccx->nhm_rpt_stamp = 0; +} +void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct nhm_para_info nhm_para; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + boolean nhm_rpt_success = true; + u8 result_tmp = 0; + u8 i; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM Basic-Trigger 262ms: {1}\n"); + /* some old ic is not supported on NHM divider option */ + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B | + ODM_RTL8195A | ODM_RTL8192E)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM Adv-Trigger: {2} {Include TXON} {Include CCA}\n{App} {LV} {0~262ms}\n"); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM Adv-Trigger: {2} {Include TXON} {Include CCA}\n{0:Cnt_all, 1:Cnt valid} {App} {LV} {0~262ms}\n"); + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM Get Result: {100}\n"); + } else if (var1[0] == 100) { /*@Get NHM results*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, + "IGI=0x%x, rpt_stamp=%d\n", ccx->nhm_igi, + ccx->nhm_rpt_stamp); + + nhm_rpt_success = phydm_nhm_get_result(dm); + + if (nhm_rpt_success) { + for (i = 0; i <= 11; i++) { + result_tmp = ccx->nhm_result[i]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "nhm_rpt[%d] = %d (%d percent)\n", + i, result_tmp, + (((result_tmp * 100) + 128) >> 8)); + } + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Get NHM_rpt Fail\n"); + } + ccx->nhm_manual_ctrl = 0; + + } else { /*NMH trigger*/ + + ccx->nhm_manual_ctrl = 1; + /* some old ic is not supported on NHM divider option */ + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B | + ODM_RTL8195A | ODM_RTL8192E)) { + for (i = 1; i < 6; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + } + } else { + for (i = 1; i < 7; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + } + } + if (var1[0] == 1) { + nhm_para.incld_txon = NHM_EXCLUDE_TXON; + nhm_para.incld_cca = NHM_EXCLUDE_CCA; + nhm_para.div_opt = NHM_CNT_ALL; + nhm_para.nhm_app = NHM_DBG; + nhm_para.nhm_lv = NHM_LV_4; + nhm_para.mntr_time = 262; + } else { + nhm_para.incld_txon = (enum nhm_option_txon_all)var1[1]; + nhm_para.incld_cca = (enum nhm_option_cca_all)var1[2]; + /* some old ic is not supported on NHM divider option */ + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B | + ODM_RTL8195A | ODM_RTL8192E)) { + nhm_para.nhm_app = (enum nhm_application) + var1[3]; + nhm_para.nhm_lv = (enum phydm_nhm_level)var1[4]; + nhm_para.mntr_time = (u16)var1[5]; + } else { + nhm_para.div_opt = (enum nhm_divider_opt_all) + var1[3]; + nhm_para.nhm_app = (enum nhm_application) + var1[4]; + nhm_para.nhm_lv = (enum phydm_nhm_level)var1[5]; + nhm_para.mntr_time = (u16)var1[6]; + } + } + /* some old ic is not supported on NHM divider option */ + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B | + ODM_RTL8195A | ODM_RTL8192E)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "txon=%d, cca=%d, app=%d, lv=%d, time=%d ms\n", + nhm_para.incld_txon, nhm_para.incld_cca, + nhm_para.nhm_app, nhm_para.nhm_lv, + nhm_para.mntr_time); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "txon=%d, cca=%d, dev=%d, app=%d, lv=%d, time=%d ms\n", + nhm_para.incld_txon, nhm_para.incld_cca, + nhm_para.div_opt, nhm_para.nhm_app, + nhm_para.nhm_lv, nhm_para.mntr_time); + } + if (phydm_nhm_mntr_set(dm, &nhm_para) == PHYDM_SET_SUCCESS) + phydm_nhm_trigger(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "IGI=0x%x, rpt_stamp=%d\n", ccx->nhm_igi, + ccx->nhm_rpt_stamp); + + for (i = 0; i <= 10; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM_th[%d] RSSI = %d\n", i, + NTH_TH_2_RSSI(ccx->nhm_th[i])); + } } + + *_used = used; + *_out_len = out_len; +} +#endif /*@#ifdef NHM_SUPPORT*/ + +#ifdef CLM_SUPPORT + +void phydm_clm_racing_release(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->clm_set_lv); + + ccx->clm_ongoing = false; + ccx->clm_set_lv = CLM_RELEASE; + ccx->clm_app = CLM_BACKGROUND; +} + +u8 phydm_clm_racing_ctrl(void *dm_void, enum phydm_nhm_level clm_lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 set_result = PHYDM_SET_SUCCESS; + /*@acquire to control CLM API*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ongoing=%d, lv:(%d)->(%d)\n", + ccx->clm_ongoing, ccx->clm_set_lv, clm_lv); + if (ccx->clm_ongoing) { + if (clm_lv <= ccx->clm_set_lv) { + set_result = PHYDM_SET_FAIL; + } else { + phydm_ccx_hw_restart(dm); + ccx->clm_ongoing = false; + } + } + + if (set_result) + ccx->clm_set_lv = clm_lv; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm racing success=%d\n", set_result); + return set_result; +} + +void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u8 clm_report = cmd_buf[0]; + /*@u8 clm_report_idx = cmd_buf[1];*/ + + if (cmd_len >= 12) + return; + + ccx_info->clm_fw_result_acc += clm_report; + ccx_info->clm_fw_result_cnt++; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%d] clm_report= %d\n", + ccx_info->clm_fw_result_cnt, clm_report); } -void -phydm_clm_setting( - void *p_dm_void -) +void phydm_clm_h2c(void *dm_void, u16 obs_time, u8 fw_clm_en) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 h2c_val[H2C_MAX_LENGTH] = {0}; + u8 i = 0; + u8 obs_time_idx = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "obs_time_index=%d *4 us\n", obs_time); + + for (i = 1; i <= 16; i++) { + if (obs_time & BIT(16 - i)) { + obs_time_idx = 16 - i; + break; + } + } +#if 0 + obs_time = (2 ^ 16 - 1)~(2 ^ 15) => obs_time_idx = 15 (65535 ~32768) + obs_time = (2 ^ 15 - 1)~(2 ^ 14) => obs_time_idx = 14 + ... + ... + ... + obs_time = (2 ^ 1 - 1)~(2 ^ 0) => obs_time_idx = 0 +#endif - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + h2c_val[0] = obs_time_idx | (((fw_clm_en) ? 1 : 0) << 7); + h2c_val[1] = CLM_MAX_REPORT_TIME; - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(8), 0x1); /*Enable CCX for CLM*/ + PHYDM_DBG(dm, DBG_ENV_MNTR, "PHYDM h2c[0x4d]=0x%x %x %x %x %x %x %x\n", + h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2], + h2c_val[1], h2c_val[0]); - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_CLM_MNTR, H2C_MAX_LENGTH, h2c_val); +} - odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(8), 0x1); /*Enable CCX for CLM*/ +void phydm_clm_setting(void *dm_void, u16 clm_period /*@4us sample 1 time*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + if (ccx->clm_period != clm_period) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(dm, R_0x990, MASKLWORD, clm_period); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + odm_set_bb_reg(dm, R_0x1e40, MASKLWORD, clm_period); + #endif + else if (dm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(dm, R_0x894, MASKLWORD, clm_period); + + ccx->clm_period = clm_period; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Update CLM period ((%d)) -> ((%d))\n", + ccx->clm_period, clm_period); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM period = %dus\n", __func__, ccx_info->CLM_period * 4)); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Set CLM period=%d * 4us\n", + ccx->clm_period); +} + +void phydm_clm_trigger(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 reg1 = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + reg1 = R_0x994; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + reg1 = R_0x1e60; + #endif + else + reg1 = R_0x890; + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + odm_set_bb_reg(dm, reg1, BIT(0), 0x0); + odm_set_bb_reg(dm, reg1, BIT(0), 0x1); + + ccx->clm_trigger_time = dm->phydm_sys_up_time; + ccx->clm_rpt_stamp++; + ccx->clm_ongoing = true; } -void -phydm_clm_trigger( - void *p_dm_void -) +boolean +phydm_clm_check_rdy(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean is_ready = false; + u32 reg1 = 0, reg1_bit = 0; +#if (ENV_MNTR_DBG) + u16 i; + u64 start_time, progressing_time; +#endif + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = ODM_REG_CLM_RESULT_11AC; + reg1_bit = 16; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + reg1 = R_0x2d88; + reg1_bit = 16; + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (dm->support_ic_type == ODM_RTL8710B) { + reg1 = R_0x8b4; + reg1_bit = 24; + } else { + reg1 = R_0x8b4; + reg1_bit = 16; + } + } +#if (ENV_MNTR_DBG) + start_time = odm_get_current_time(dm); + for (i = 0; i <= 400; i++) { + if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) { + is_ready = true; + break; + } + ODM_delay_ms(1); + } + progressing_time = odm_get_progressing_time(dm, start_time); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM rdy=%d, i=%d, CLM_polling_time=%lld\n", + is_ready, i, progressing_time); +#else + if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) + is_ready = true; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x0); /*Trigger CLM*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x1); - } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x0); /*Trigger CLM*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x1); + PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM rdy=%d\n", is_ready); +#endif + return is_ready; +} + +void phydm_clm_get_utility(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 clm_result_tmp; + + if (ccx->clm_period == 0) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] clm_period = 0\n"); + ccx->clm_ratio = 0; + } else if (ccx->clm_period >= 65530) { + clm_result_tmp = (u32)(ccx->clm_result * 100); + ccx->clm_ratio = (u8)((clm_result_tmp + (1 << 15)) >> 16); + } else { + clm_result_tmp = (u32)(ccx->clm_result * 100); + ccx->clm_ratio = (u8)(clm_result_tmp / (u32)ccx->clm_period); } } boolean -phydm_check_cl_mready( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 value32 = 0; - boolean ret = false; - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*make sure CLM calc is ready*/ - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD); /*make sure CLM calc is ready*/ - - if ((p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16))) - ret = true; - else if ((p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) && (value32 & BIT(16))) - ret = true; +phydm_clm_get_result(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u32 reg1 = 0; + u32 val = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + reg1 = R_0x994; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + reg1 = R_0x1e60; + #endif + else + reg1 = R_0x890; + odm_set_bb_reg(dm, reg1, BIT(0), 0x0); + if (phydm_clm_check_rdy(dm) == false) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM report Fail\n"); + phydm_clm_racing_release(dm); + return false; + } + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + val = odm_get_bb_reg(dm, R_0xfa4, MASKLWORD); + ccx_info->clm_result = (u16)val; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + val = odm_get_bb_reg(dm, R_0x2d88, MASKLWORD); + ccx_info->clm_result = (u16)val; + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + val = odm_get_bb_reg(dm, R_0x8d0, MASKLWORD); + ccx_info->clm_result = (u16)val; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM result = %d *4 us\n", + ccx_info->clm_result); + phydm_clm_racing_release(dm); + return true; +} + +void phydm_clm_mntr_fw(void *dm_void, u16 monitor_time /*unit ms*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 val = 0; + + /*@[Get CLM report]*/ + if (ccx->clm_fw_result_cnt != 0) { + val = ccx->clm_fw_result_acc / ccx->clm_fw_result_cnt; + ccx->clm_ratio = (u8)val; + } else { + ccx->clm_ratio = 0; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n", + ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt); + + ccx->clm_fw_result_acc = 0; + ccx->clm_fw_result_cnt = 0; + + /*@[CLM trigger]*/ + if (monitor_time >= 262) + ccx->clm_period = 65535; + else + ccx->clm_period = monitor_time * MS_TO_4US_RATIO; + + phydm_clm_h2c(dm, monitor_time, true); +} + +u8 phydm_clm_mntr_set(void *dm_void, struct clm_para_info *clm_para) +{ + /*@Driver Monitor CLM*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u16 clm_period = 0; + + if (clm_para->mntr_time == 0) + return PHYDM_SET_FAIL; + + if (clm_para->clm_lv >= CLM_MAX_NUM) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[WARNING] Wrong LV=%d\n", + clm_para->clm_lv); + return PHYDM_SET_FAIL; + } + + if (phydm_clm_racing_ctrl(dm, clm_para->clm_lv) == PHYDM_SET_FAIL) + return PHYDM_SET_FAIL; + + if (clm_para->mntr_time >= 262) + clm_period = CLM_PERIOD_MAX; else - ret = false; + clm_period = clm_para->mntr_time * MS_TO_4US_RATIO; + + ccx->clm_app = clm_para->clm_app; + phydm_clm_setting(dm, clm_period); + + return PHYDM_SET_SUCCESS; +} + +boolean +phydm_clm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct clm_para_info clm_para = {0}; + boolean clm_chk_result = false; + u32 sys_return_time = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + if (ccx->clm_manual_ctrl) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM in manual ctrl\n"); + return clm_chk_result; + } + + sys_return_time = ccx->clm_trigger_time + MAX_ENV_MNTR_TIME; + + if (ccx->clm_app != CLM_BACKGROUND && + sys_return_time > dm->phydm_sys_up_time) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "trigger_time %d, sys_time=%d\n", + ccx->clm_trigger_time, dm->phydm_sys_up_time); + + return clm_chk_result; + } + + clm_para.clm_app = CLM_BACKGROUND; + clm_para.clm_lv = CLM_LV_1; + clm_para.mntr_time = monitor_time; + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + /*@[Get CLM report]*/ + if (phydm_clm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n"); + phydm_clm_get_utility(dm); + } + + /*@[CLM trigger]----------------------------------------------*/ + if (phydm_clm_mntr_set(dm, &clm_para) == PHYDM_SET_SUCCESS) + clm_chk_result = true; + } else { +#if 0 + /*PHYDM_DBG(dm, DBG_ENV_MNTR, "enter clm_mntr_fw!!");*/ +#endif + phydm_clm_mntr_fw(dm, monitor_time); + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ratio=%d\n", ccx->clm_ratio); +#if 0 + /*PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_chk_result=%d\n",clm_chk_result);*/ +#endif + return clm_chk_result; +} + +void phydm_set_clm_mntr_mode(void *dm_void, enum clm_monitor_mode mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + + if (ccx_info->clm_mntr_mode != mode) { + ccx_info->clm_mntr_mode = mode; + phydm_ccx_hw_restart(dm); + + if (mode == CLM_DRIVER_MNTR) + phydm_clm_h2c(dm, 0, 0); + } +} + +void phydm_clm_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + ccx->clm_ongoing = false; + ccx->clm_manual_ctrl = 0; + ccx->clm_mntr_mode = CLM_DRIVER_MNTR; + ccx->clm_period = 0; + ccx->clm_rpt_stamp = 0; + phydm_clm_setting(dm, 65535); +} + +void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + struct clm_para_info clm_para = {0}; + u32 i; + + for (i = 0; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "CLM Driver Basic-Trigger 262ms: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "CLM Driver Adv-Trigger: {2} {app} {LV} {0~262ms}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "CLM FW Trigger: {3}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "CLM Get Result: {100}\n"); + } else if (var1[0] == 100) { /* @Get CLM results */ + + if (phydm_clm_get_result(dm)) + phydm_clm_get_utility(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "clm_rpt_stamp=%d\n", ccx->clm_rpt_stamp); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "clm_ratio:((%d percent)) = (%d us/ %d us)\n", + ccx->clm_ratio, ccx->clm_result << 2, + ccx->clm_period << 2); + + ccx->clm_manual_ctrl = 0; + + } else { /* Set & trigger CLM */ + ccx->clm_manual_ctrl = 1; + + if (var1[0] == 1) { + clm_para.clm_app = CLM_BACKGROUND; + clm_para.clm_lv = CLM_LV_4; + clm_para.mntr_time = 262; + ccx->clm_mntr_mode = CLM_DRIVER_MNTR; + + } else if (var1[0] == 2) { + clm_para.clm_app = (enum clm_application)var1[1]; + clm_para.clm_lv = (enum phydm_clm_level)var1[2]; + ccx->clm_mntr_mode = CLM_DRIVER_MNTR; + clm_para.mntr_time = (u16)var1[3]; + + } else if (var1[0] == 3) { + clm_para.clm_app = CLM_BACKGROUND; + clm_para.clm_lv = CLM_LV_4; + ccx->clm_mntr_mode = CLM_FW_MNTR; + clm_para.mntr_time = 262; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "app=%d, lv=%d, mode=%s, time=%d ms\n", + clm_para.clm_app, clm_para.clm_lv, + ((ccx->clm_mntr_mode == CLM_FW_MNTR) ? "FW" : + "driver"), clm_para.mntr_time); + + if (phydm_clm_mntr_set(dm, &clm_para) == PHYDM_SET_SUCCESS) + phydm_clm_trigger(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "clm_rpt_stamp=%d\n", ccx->clm_rpt_stamp); + } + + *_used = used; + *_out_len = out_len; +} + +#endif /*@#ifdef CLM_SUPPORT*/ + +u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para, + struct clm_para_info *clm_para, + struct env_trig_rpt *trig_rpt) +{ +#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean nhm_set_ok = false; + boolean clm_set_ok = false; + u8 trigger_result = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + +#if (ENV_MNTR_DBG_2) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[DBG][2] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n", + odm_get_bb_reg(dm, 0xc50, MASKDWORD), + odm_get_bb_reg(dm, 0x994, MASKDWORD), + odm_get_bb_reg(dm, 0x998, MASKDWORD)); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[DBG][2] 0x1d70=0x%x, 0x1e60=0x%x, 0x1e44=0x%x\n", + odm_get_bb_reg(dm, 0x1d70, MASKDWORD), + odm_get_bb_reg(dm, 0x1e60, MASKDWORD), + odm_get_bb_reg(dm, 0x1e44, MASKDWORD)); + #endif + } +#endif + + /*@[NHM]*/ + nhm_set_ok = phydm_nhm_mntr_set(dm, nhm_para); + + /*@[CLM]*/ + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + clm_set_ok = phydm_clm_mntr_set(dm, clm_para); + } else if (ccx->clm_mntr_mode == CLM_FW_MNTR) { + phydm_clm_h2c(dm, CLM_PERIOD_MAX, true); + trigger_result |= CLM_SUCCESS; + } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret)); + if (nhm_set_ok) { + phydm_nhm_trigger(dm); + trigger_result |= NHM_SUCCESS; + } + + if (clm_set_ok) { + phydm_clm_trigger(dm); + trigger_result |= CLM_SUCCESS; + } + + /*@monitor for the test duration*/ + ccx->start_time = odm_get_current_time(dm); + + trig_rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp; + trig_rpt->clm_rpt_stamp = ccx->clm_rpt_stamp; - return ret; + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\n\n", + trig_rpt->nhm_rpt_stamp, trig_rpt->clm_rpt_stamp); + + return trigger_result; +#endif } -void -phydm_get_cl_mresult( - void *p_dm_void -) +u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; +#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 env_mntr_rpt = 0; + u64 progressing_time; + u32 val_tmp = 0; + + /*@monitor for the test duration*/ + progressing_time = odm_get_progressing_time(dm, ccx->start_time); + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "env_time=%lld\n", progressing_time); + +#if (ENV_MNTR_DBG_2) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[DBG][2] 0xc50=0x%x, 0x994=0x%x, 0x998=0x%x\n", + odm_get_bb_reg(dm, 0xc50, MASKDWORD), + odm_get_bb_reg(dm, 0x994, MASKDWORD), + odm_get_bb_reg(dm, 0x998, MASKDWORD)); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[DBG][2] 0x1d70=0x%x, 0x1e60=0x%x, 0x1e44=0x%x\n", + odm_get_bb_reg(dm, 0x1d70, MASKDWORD), + odm_get_bb_reg(dm, 0x1e60, MASKDWORD), + odm_get_bb_reg(dm, 0x1e44, MASKDWORD)); + #endif + } +#endif + + /*@Get NHM result*/ + if (phydm_nhm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n"); + phydm_nhm_get_utility(dm); + rpt->nhm_ratio = ccx->nhm_ratio; + env_mntr_rpt |= NHM_SUCCESS; + + odm_move_memory(dm, &rpt->nhm_result[0], + &ccx->nhm_result[0], NHM_RPT_NUM); + } else { + rpt->nhm_ratio = ENV_MNTR_FAIL; + } - u32 value32 = 0; - u16 results = 0; + /*@Get CLM result*/ + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + if (phydm_clm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n"); + phydm_clm_get_utility(dm); + env_mntr_rpt |= CLM_SUCCESS; + rpt->clm_ratio = ccx->clm_ratio; + } else { + rpt->clm_ratio = ENV_MNTR_FAIL; + } - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*read CLM calc result*/ - else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11N, MASKDWORD); /*read CLM calc result*/ + } else { + if (ccx->clm_fw_result_cnt != 0) { + val_tmp = ccx->clm_fw_result_acc + / ccx->clm_fw_result_cnt; + ccx->clm_ratio = (u8)val_tmp; + } else { + ccx->clm_ratio = 0; + } - ccx_info->CLM_result = (u16)(value32 & MASKLWORD); + rpt->clm_ratio = ccx->clm_ratio; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n", + ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM result = %dus\n", __func__, ccx_info->CLM_result * 4)); + ccx->clm_fw_result_acc = 0; + ccx->clm_fw_result_cnt = 0; + env_mntr_rpt |= CLM_SUCCESS; + } + + rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp; + rpt->clm_rpt_stamp = ccx->clm_rpt_stamp; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "IGI=0x%x, nhm_ratio=%d, clm_ratio=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n\n", + ccx->nhm_igi, rpt->nhm_ratio, rpt->clm_ratio, + rpt->nhm_rpt_stamp, rpt->clm_rpt_stamp); + + return env_mntr_rpt; +#endif +} +/*@Environment Monitor*/ +void phydm_env_mntr_watchdog(void *dm_void) +{ +#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean nhm_chk_ok = false; + boolean clm_chk_ok = false; + + if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) + return; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + nhm_chk_ok = phydm_nhm_mntr_chk(dm, 262); /*@monitor 262ms*/ + clm_chk_ok = phydm_clm_mntr_chk(dm, 262); /*@monitor 262ms*/ +#if 0 + /*PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_chk_ok %d\n\n",nhm_chk_ok);*/ + /*PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_chk_ok %d\n\n",clm_chk_ok);*/ +#endif + if (nhm_chk_ok) + phydm_nhm_trigger(dm); + + if (clm_chk_ok) + phydm_clm_trigger(dm); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Summary: nhm_ratio=((%d)) clm_ratio=((%d))\n\n", + ccx->nhm_ratio, ccx->clm_ratio); +#endif } + +void phydm_env_monitor_init(void *dm_void) +{ +#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) + return; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + phydm_ccx_hw_restart(dm); + phydm_nhm_init(dm); + phydm_clm_init(dm); +#endif +} + +void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + struct clm_para_info clm_para = {0}; + struct nhm_para_info nhm_para = {0}; + struct env_mntr_rpt rpt = {0}; + struct env_trig_rpt trig_rpt = {0}; + u8 set_result; + u8 i; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Basic-Trigger 262ms: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Get Result: {100}\n"); + } else if (var1[0] == 100) { /* @Get CLM results */ + + set_result = phydm_env_mntr_result(dm, &rpt); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set Result=%d\n nhm_ratio=%d clm_ratio=%d\n nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\n", + set_result, rpt.nhm_ratio, rpt.clm_ratio, + rpt.nhm_rpt_stamp, rpt.clm_rpt_stamp); + + for (i = 0; i <= 11; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "nhm_rpt[%d] = %d (%d percent)\n", i, + rpt.nhm_result[i], + (((rpt.nhm_result[i] * 100) + 128) >> 8)); + } + + } else { /* Set & trigger CLM */ + /*nhm para*/ + nhm_para.incld_txon = NHM_EXCLUDE_TXON; + nhm_para.incld_cca = NHM_EXCLUDE_CCA; + nhm_para.div_opt = NHM_CNT_ALL; + nhm_para.nhm_app = NHM_ACS; + nhm_para.nhm_lv = NHM_LV_2; + nhm_para.mntr_time = 262; + + /*@clm para*/ + clm_para.clm_app = CLM_ACS; + clm_para.clm_lv = CLM_LV_2; + clm_para.mntr_time = 262; + + set_result = phydm_env_mntr_trigger(dm, &nhm_para, + &clm_para, &trig_rpt); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set Result=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n", + set_result, trig_rpt.nhm_rpt_stamp, + trig_rpt.clm_rpt_stamp); + } + + *_used = used; + *_out_len = out_len; +} + diff --git a/hal/phydm/phydm_ccx.h b/hal/phydm/phydm_ccx.h index 5641b73..792e161 100644 --- a/hal/phydm/phydm_ccx.h +++ b/hal/phydm/phydm_ccx.h @@ -1,102 +1,268 @@ -#ifndef __PHYDMCCX_H__ -#define __PHYDMCCX_H__ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMCCX_H__ +#define __PHYDMCCX_H__ + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ +#define ENV_MNTR_DBG 0 /*@debug for the HW processing time from NHM/CLM trigger and get result*/ +#define ENV_MNTR_DBG_1 1 /*@debug 8812A & 8821A P2P Fail to get result*/ +#define ENV_MNTR_DBG_2 1 /*@debug for read reister*/ #define CCX_EN 1 -#define SET_NHM_SETTING 0 -#define STORE_NHM_SETTING 1 -#define RESTORE_NHM_SETTING 2 +#define MAX_ENV_MNTR_TIME 8 /*second*/ +#define IGI_TO_NHM_TH_MULTIPLIER 2 +#define MS_TO_4US_RATIO 250 +#define CCA_CAP 14 +#define CLM_MAX_REPORT_TIME 10 +#define DEVIDER_ERROR 0xffff +#define CLM_PERIOD_MAX 65535 +#define NHM_PERIOD_MAX 65534 +#define NHM_TH_NUM 11 /*threshold number of NHM*/ +#define NHM_RPT_NUM 12 + +#define IGI_2_NHM_TH(igi) ((igi) << 1)/*NHM_threshold = IGI * 2*/ +#define NTH_TH_2_RSSI(th) ((th >> 1) - 10) -/* -#define NHM_EXCLUDE_CCA 0 -#define NHM_INCLUDE_CCA 1 -#define NHM_EXCLUDE_TXON 0 -#define NHM_INCLUDE_TXON 1 -*/ +/*@FAHM*/ +#define FAHM_INCLD_FA BIT(0) +#define FAHM_INCLD_CRC_OK BIT(1) +#define FAHM_INCLD_CRC_ER BIT(2) -enum nhm_inexclude_cca { - NHM_EXCLUDE_CCA, - NHM_INCLUDE_CCA +#define NHM_SUCCESS BIT(0) +#define CLM_SUCCESS BIT(1) +#define FAHM_SUCCESS BIT(2) +#define ENV_MNTR_FAIL 0xff + +/* @1 ============================================================ + * 1 enumrate + * 1 ============================================================ + */ +enum phydm_clm_level { + CLM_RELEASE = 0, + CLM_LV_1 = 1, /* @Low Priority function */ + CLM_LV_2 = 2, /* @Middle Priority function */ + CLM_LV_3 = 3, /* @High priority function (ex: Check hang function) */ + CLM_LV_4 = 4, /* @Debug function (the highest priority) */ + CLM_MAX_NUM = 5 }; -enum nhm_inexclude_txon { - NHM_EXCLUDE_TXON, - NHM_INCLUDE_TXON +enum phydm_nhm_level { + NHM_RELEASE = 0, + NHM_LV_1 = 1, /* @Low Priority function */ + NHM_LV_2 = 2, /* @Middle Priority function */ + NHM_LV_3 = 3, /* @High priority function (ex: Check hang function) */ + NHM_LV_4 = 4, /* @Debug function (the highest priority) */ + NHM_MAX_NUM = 5 }; +enum nhm_divider_opt_all { + NHM_CNT_ALL = 0, /*nhm SUM report <= 255*/ + NHM_VALID = 1, /*nhm SUM report = 255*/ + NHM_CNT_INIT +}; -struct _CCX_INFO { +enum nhm_setting { + SET_NHM_SETTING, + STORE_NHM_SETTING, + RESTORE_NHM_SETTING +}; - /*Settings*/ - u8 NHM_th[11]; - u16 NHM_period; /* 4us per unit */ - u16 CLM_period; /* 4us per unit */ - enum nhm_inexclude_txon nhm_inexclude_txon; - enum nhm_inexclude_cca nhm_inexclude_cca; +enum nhm_option_cca_all { + NHM_EXCLUDE_CCA = 0, + NHM_INCLUDE_CCA = 1, + NHM_CCA_INIT +}; - /*Previous Settings*/ - u8 NHM_th_restore[11]; - u16 NHM_period_restore; /* 4us per unit */ - u16 CLM_period_restore; /* 4us per unit */ - enum nhm_inexclude_txon NHM_inexclude_txon_restore; - enum nhm_inexclude_cca NHM_inexclude_cca_restore; +enum nhm_option_txon_all { + NHM_EXCLUDE_TXON = 0, + NHM_INCLUDE_TXON = 1, + NHM_TXON_INIT +}; - /*Report*/ - u8 NHM_result[12]; - u16 NHM_duration; - u16 CLM_result; +enum nhm_application { + NHM_BACKGROUND = 0,/*@default*/ + NHM_ACS = 1, + IEEE_11K_HIGH = 2, + IEEE_11K_LOW = 3, + INTEL_XBOX = 4, + NHM_DBG = 5, /*@manual trigger*/ +}; +enum clm_application { + CLM_BACKGROUND = 0,/*@default*/ + CLM_ACS = 1, +}; - boolean echo_NHM_en; - boolean echo_CLM_en; - u8 echo_IGI; +enum clm_monitor_mode { + CLM_DRIVER_MNTR = 1, + CLM_FW_MNTR = 2 +}; +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ +struct env_trig_rpt { + u8 nhm_rpt_stamp; + u8 clm_rpt_stamp; }; -/*NHM*/ -void -phydm_nhm_setting( - void *p_dm_void, - u8 nhm_setting -); +struct env_mntr_rpt { + u8 nhm_ratio; + u8 nhm_result[NHM_RPT_NUM]; + u8 clm_ratio; + u8 nhm_rpt_stamp; + u8 clm_rpt_stamp; +}; -void -phydm_nhm_trigger( - void *p_dm_void -); +struct nhm_para_info { + enum nhm_option_txon_all incld_txon; /*@Include TX on*/ + enum nhm_option_cca_all incld_cca; /*@Include CCA*/ + enum nhm_divider_opt_all div_opt; /*@divider option*/ + enum nhm_application nhm_app; + enum phydm_nhm_level nhm_lv; + u16 mntr_time; /*@0~262 unit ms*/ -void -phydm_get_nhm_result( - void *p_dm_void -); +}; + +struct clm_para_info { + enum clm_application clm_app; + enum phydm_clm_level clm_lv; + u16 mntr_time; /*@0~262 unit ms*/ +}; -boolean -phydm_check_nhm_ready( - void *p_dm_void -); +struct ccx_info { + u32 nhm_trigger_time; + u32 clm_trigger_time; + u64 start_time; /*@monitor for the test duration*/ +#ifdef NHM_SUPPORT + enum nhm_application nhm_app; + enum nhm_option_txon_all nhm_include_txon; + enum nhm_option_cca_all nhm_include_cca; + enum nhm_divider_opt_all nhm_divider_opt; + /*Report*/ + u8 nhm_th[NHM_TH_NUM]; + u8 nhm_result[NHM_RPT_NUM]; + u16 nhm_period; /* @4us per unit */ + u8 nhm_igi; + u8 nhm_manual_ctrl; + u8 nhm_ratio; /*@1% per nuit, it means the interference igi can't overcome.*/ + u8 nhm_rpt_sum; + u16 nhm_duration; /*@Real time of NHM_VALID */ + u8 nhm_set_lv; + boolean nhm_ongoing; + u8 nhm_rpt_stamp; +#endif +#ifdef CLM_SUPPORT + enum clm_application clm_app; + u8 clm_manual_ctrl; + u8 clm_set_lv; + boolean clm_ongoing; + u16 clm_period; /* @4us per unit */ + u16 clm_result; + u8 clm_ratio; + u32 clm_fw_result_acc; + u8 clm_fw_result_cnt; + enum clm_monitor_mode clm_mntr_mode; + u8 clm_rpt_stamp; +#endif +#ifdef FAHM_SUPPORT + boolean fahm_ongoing; + u8 env_mntr_igi; + u8 fahm_nume_sel; /*@fahm_numerator_sel: select {FA, CRCOK, CRC_fail} */ + u8 fahm_denom_sel; /*@fahm_denominator_sel: select {FA, CRCOK, CRC_fail} */ + u16 fahm_period; /*unit: 4us*/ +#endif +}; -/*CLM*/ +/* @1 ============================================================ + * 1 Function Prototype + * 1 ============================================================ + */ + +#ifdef FAHM_SUPPORT + +void phydm_fahm_init(void *dm_void); + +void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); + +#endif + +/*@NHM*/ +#ifdef NHM_SUPPORT +void phydm_nhm_trigger(void *dm_void); + +void phydm_nhm_init(void *dm_void); + +void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); +u8 phydm_get_igi(void *dm_void, enum bb_path path); +#endif + +/*@CLM*/ +#ifdef CLM_SUPPORT +void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); + +void phydm_clm_h2c(void *dm_void, u16 obs_time, u8 fw_clm_en); + +void phydm_clm_setting(void *dm_void, u16 clm_period); + +void phydm_clm_trigger(void *dm_void); + +boolean phydm_clm_check_rdy(void *dm_void); + +void phydm_clm_get_utility(void *dm_void); + +boolean phydm_clm_get_result(void *dm_void); + +u8 phydm_clm_mntr_set(void *dm_void, struct clm_para_info *clm_para); + +void phydm_set_clm_mntr_mode(void *dm_void, enum clm_monitor_mode mode); + +void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); +#endif -void -phydm_clm_setting( - void *p_dm_void -); +u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para, + struct clm_para_info *clm_para, + struct env_trig_rpt *rpt); -void -phydm_clm_trigger( - void *p_dm_void -); +u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt); -boolean -phydm_check_cl_mready( - void *p_dm_void -); +void phydm_env_mntr_watchdog(void *dm_void); -void -phydm_get_cl_mresult( - void *p_dm_void -); +void phydm_env_monitor_init(void *dm_void); +void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); #endif diff --git a/hal/phydm/phydm_cfotracking.c b/hal/phydm/phydm_cfotracking.c index c794f37..7434835 100644 --- a/hal/phydm/phydm_cfotracking.c +++ b/hal/phydm/phydm_cfotracking.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,364 +8,494 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" -void -odm_set_crystal_cap( - void *p_dm_void, - u8 crystal_cap -) +s32 phydm_get_cfo_hz(void *dm_void, u32 val, u8 bit_num, u8 frac_num) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - struct _ADAPTER *adapter = p_dm_odm->adapter;/* JJ modified 20161115 */ - - if (p_cfo_track->crystal_cap == crystal_cap) - return; + s32 val_s = 0; - p_cfo_track->crystal_cap = crystal_cap; + val_s = phydm_cnvrt_2_sign(val, bit_num); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) { - /* write 0x24[22:17] = 0x24[16:11] = crystal_cap */ - crystal_cap = crystal_cap & 0x3F; - odm_set_bb_reg(p_dm_odm, REG_AFE_XTAL_CTRL, 0x007ff800, (crystal_cap | (crystal_cap << 6))); - } else if (p_dm_odm->support_ic_type & ODM_RTL8812) { - /* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */ - crystal_cap = crystal_cap & 0x3F; - odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6))); - } else if ((p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8723D))) { - /* 0x2C[23:18] = 0x2C[17:12] = crystal_cap */ - crystal_cap = crystal_cap & 0x3F; - odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6))); - } else if (p_dm_odm->support_ic_type & ODM_RTL8814A) { - /* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */ - crystal_cap = crystal_cap & 0x3F; - odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6))); - } else if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { - /* write 0x24[30:25] = 0x28[6:1] = crystal_cap */ - crystal_cap = crystal_cap & 0x3F; - odm_set_bb_reg(p_dm_odm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); - odm_set_bb_reg(p_dm_odm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_set_crystal_cap(): Use default setting.\n")); - odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0xFFF000, (crystal_cap | (crystal_cap << 6))); - } + if (frac_num == 10) /*@ (X*312500)/1024 ~= X*305*/ + val_s *= 305; + else if (frac_num == 11) /*@ (X*312500)/2048 ~= X*152*/ + val_s *= 152; + else if (frac_num == 12) /*@ (X*312500)/4096 ~= X*76*/ + val_s *= 76; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_set_crystal_cap(): crystal_cap = 0x%x\n", crystal_cap)); -#endif + return val_s; +} -/* JJ modified 20161115 */ -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type & (ODM_RTL8710B)) { - /* write 0x60[29:24] = 0x60[23:18] = crystal_cap */ - crystal_cap = crystal_cap & 0x3F; - HAL_SetSYSOnReg(adapter, REG_SYS_XTAL_CTRL0, 0x3FFC0000, (crystal_cap | (crystal_cap << 6))); +#if (ODM_IC_11AC_SERIES_SUPPORT) +void phydm_get_cfo_info_ac(void *dm_void, struct phydm_cfo_rpt *cfo) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u32 val[4] = {0}; + u32 val_1[4] = {0}; + u32 val_2[4] = {0}; + u32 val_tmp = 0; + + val[0] = odm_read_4byte(dm, R_0xd0c); + val_1[0] = odm_read_4byte(dm, R_0xd10); + val_2[0] = odm_get_bb_reg(dm, R_0xd14, 0x1fff0000); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + val[1] = odm_read_4byte(dm, R_0xd4c); + val_1[1] = odm_read_4byte(dm, R_0xd50); + val_2[1] = odm_get_bb_reg(dm, R_0xd54, 0x1fff0000); + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + val[2] = odm_read_4byte(dm, R_0xd8c); + val_1[2] = odm_read_4byte(dm, R_0xd90); + val_2[2] = odm_get_bb_reg(dm, R_0xd94, 0x1fff0000); + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + val[3] = odm_read_4byte(dm, R_0xdcc); + val_1[3] = odm_read_4byte(dm, R_0xdd0); + val_2[3] = odm_get_bb_reg(dm, R_0xdd4, 0x1fff0000); + #endif + + for (i = 0; i < dm->num_rf_path; i++) { + val_tmp = val[i] & 0xfff; /*@ Short CFO, S(12,11)*/ + cfo->cfo_rpt_s[i] = phydm_get_cfo_hz(dm, val_tmp, 12, 11); + + val_tmp = val[i] >> 16; /*@ Long CFO, S(13,12)*/ + cfo->cfo_rpt_l[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + + val_tmp = val_1[i] & 0x7ff; /*@ SCFO, S(11,10)*/ + cfo->cfo_rpt_sec[i] = phydm_get_cfo_hz(dm, val_tmp, 11, 10); + + val_tmp = val_1[i] >> 16; /*@ Acq CFO, S(13,12)*/ + cfo->cfo_rpt_acq[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + + val_tmp = val_2[i]; /*@ End CFO, S(13,12)*/ + cfo->cfo_rpt_end[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); } +} #endif +#if (ODM_IC_11N_SERIES_SUPPORT) +void phydm_get_cfo_info_n(void *dm_void, struct phydm_cfo_rpt *cfo) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val[5] = {0}; + u32 val_tmp = 0; + + odm_set_bb_reg(dm, R_0xd00, BIT(26), 1); + + val[0] = odm_read_4byte(dm, R_0xdac); /*@ Short CFO*/ + val[1] = odm_read_4byte(dm, R_0xdb0); /*@ Long CFO*/ + val[2] = odm_read_4byte(dm, R_0xdb8); /*@ Sec CFO*/ + val[3] = odm_read_4byte(dm, R_0xde0); /*@ Acq CFO*/ + val[4] = odm_read_4byte(dm, R_0xdbc); /*@ End CFO*/ + + /*@[path-A]*/ + val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/ + cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11); + val_tmp = (val[1] & 0x1fff0000) >> 16; /*@ Long CFO, S(13,12)*/ + cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + val_tmp = (val[2] & 0x7ff0000) >> 16; /*@ Sec CFO, S(11,10)*/ + cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 11, 10); + val_tmp = (val[3] & 0x1fff0000) >> 16; /*@ Acq CFO, S(13,12)*/ + cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + val_tmp = (val[4] & 0x1fff0000) >> 16; /*@ Acq CFO, S(13,12)*/ + cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + /*@[path-B]*/ + val_tmp = val[0] & 0xfff; /*@ Short CFO, S(12,11)*/ + cfo->cfo_rpt_s[1] = phydm_get_cfo_hz(dm, val_tmp, 12, 11); + val_tmp = val[1] & 0x1fff; /*@ Long CFO, S(13,12)*/ + cfo->cfo_rpt_l[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + val_tmp = val[2] & 0x7ff; /*@ Sec CFO, S(11,10)*/ + cfo->cfo_rpt_sec[1] = phydm_get_cfo_hz(dm, val_tmp, 11, 10); + val_tmp = val[3] & 0x1fff; /*@ Acq CFO, S(13,12)*/ + cfo->cfo_rpt_acq[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + val_tmp = val[4] & 0x1fff; /*@ Acq CFO, S(13,12)*/ + cfo->cfo_rpt_end[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + #endif } -u8 -odm_get_default_crytaltal_cap( - void *p_dm_void -) +void phydm_set_atc_status(void *dm_void, boolean atc_status) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 crystal_cap = 0x20; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + u32 reg_tmp = 0; + u32 mask_tmp = 0; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]ATC_en=%d\n", __func__, atc_status); - crystal_cap = p_hal_data->crystal_cap; -#else - struct rtl8192cd_priv *priv = p_dm_odm->priv; + if (cfo_track->is_atc_status == atc_status) + return; - if (priv->pmib->dot11RFEntry.xcap > 0) - crystal_cap = priv->pmib->dot11RFEntry.xcap; -#endif + reg_tmp = ODM_REG(BB_ATC, dm); + mask_tmp = ODM_BIT(BB_ATC, dm); + odm_set_bb_reg(dm, reg_tmp, mask_tmp, atc_status); + cfo_track->is_atc_status = atc_status; +} - crystal_cap = crystal_cap & 0x3f; +boolean +phydm_get_atc_status(void *dm_void) +{ + boolean atc_status = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_tmp = 0; + u32 mask_tmp = 0; + + reg_tmp = ODM_REG(BB_ATC, dm); + mask_tmp = ODM_BIT(BB_ATC, dm); + + atc_status = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp); + + PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]atc_status=%d\n", __func__, atc_status); + return atc_status; +} +#endif - return crystal_cap; +void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + switch (dm->ic_ip_series) { + #if (ODM_IC_11N_SERIES_SUPPORT) + case PHYDM_IC_N: + phydm_get_cfo_info_n(dm, cfo); + break; + #endif + #if (ODM_IC_11AC_SERIES_SUPPORT) + case PHYDM_IC_AC: + phydm_get_cfo_info_ac(dm, cfo); + break; + #endif + default: + break; + } } -void -odm_set_atc_status( - void *p_dm_void, - boolean atc_status -) +void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + u32 reg_val = 0; - if (p_cfo_track->is_atc_status == atc_status) + if (cfo_track->crystal_cap == crystal_cap) return; - odm_set_bb_reg(p_dm_odm, ODM_REG(BB_ATC, p_dm_odm), ODM_BIT(BB_ATC, p_dm_odm), atc_status); - p_cfo_track->is_atc_status = atc_status; -} + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) { + crystal_cap &= 0x7F; + reg_val = crystal_cap | (crystal_cap << 7); + } else { + crystal_cap &= 0x3F; + reg_val = crystal_cap | (crystal_cap << 6); + } -boolean -odm_get_atc_status( - void *p_dm_void -) -{ - boolean atc_status; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + cfo_track->crystal_cap = crystal_cap; - atc_status = (boolean)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_ATC, p_dm_odm), ODM_BIT(BB_ATC, p_dm_odm)); - return atc_status; + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) { + #if (RTL8188E_SUPPORT || RTL8188F_SUPPORT) + /* write 0x24[22:17] = 0x24[16:11] = crystal_cap */ + odm_set_mac_reg(dm, R_0x24, 0x7ff800, reg_val); + #endif + } + #if (RTL8812A_SUPPORT) + else if (dm->support_ic_type & ODM_RTL8812) { + /* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */ + odm_set_mac_reg(dm, R_0x2c, 0x7FF80000, reg_val); + } + #endif + #if (RTL8703B_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\ + RTL8821A_SUPPORT || RTL8723D_SUPPORT) + else if ((dm->support_ic_type & + (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 | + ODM_RTL8723D))) { + /* @0x2C[23:18] = 0x2C[17:12] = crystal_cap */ + odm_set_mac_reg(dm, R_0x2c, 0x00FFF000, reg_val); + } + #endif + #if (RTL8814A_SUPPORT) + else if (dm->support_ic_type & ODM_RTL8814A) { + /* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */ + odm_set_mac_reg(dm, R_0x2c, 0x07FF8000, reg_val); + } + #endif + #if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | + ODM_RTL8197F | ODM_RTL8192F)) { + /* write 0x24[30:25] = 0x28[6:1] = crystal_cap */ + odm_set_mac_reg(dm, R_0x24, 0x7e000000, crystal_cap); + odm_set_mac_reg(dm, R_0x28, 0x7e, crystal_cap); + } + #endif + #if (RTL8710B_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8710B)) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + /* write 0x60[29:24] = 0x60[23:18] = crystal_cap */ + HAL_SetSYSOnReg(dm->adapter, R_0x60, 0x3FFC0000, reg_val); + #endif + } + #endif +#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) { + /* write 0x1040[23:17] = 0x1040[16:10] = crystal_cap */ + odm_set_mac_reg(dm, R_0x1040, 0x00FFFC00, reg_val); + } +#endif + PHYDM_DBG(dm, DBG_CFO_TRK, "Set rystal_cap = 0x%x\n", + cfo_track->crystal_cap); } -void -odm_cfo_tracking_reset( - void *p_dm_void -) +void phydm_cfo_tracking_reset(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - - p_cfo_track->def_x_cap = odm_get_default_crytaltal_cap(p_dm_odm); - p_cfo_track->is_adjust = true; - - if (p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) { - odm_set_crystal_cap(p_dm_odm, p_cfo_track->crystal_cap - 1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, - ("odm_cfo_tracking_reset(): approch default value (0x%x)\n", p_cfo_track->crystal_cap)); - } else if (p_cfo_track->crystal_cap < p_cfo_track->def_x_cap) { - odm_set_crystal_cap(p_dm_odm, p_cfo_track->crystal_cap + 1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, - ("odm_cfo_tracking_reset(): approch default value (0x%x)\n", p_cfo_track->crystal_cap)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + + PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__); + + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) + cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x7F; + else + cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x3f; + + cfo_track->is_adjust = true; + + if (cfo_track->crystal_cap > cfo_track->def_x_cap) { + phydm_set_crystal_cap(dm, cfo_track->crystal_cap - 1); + PHYDM_DBG(dm, DBG_CFO_TRK, "approch to Init-val (0x%x)\n", + cfo_track->crystal_cap); + + } else if (cfo_track->crystal_cap < cfo_track->def_x_cap) { + phydm_set_crystal_cap(dm, cfo_track->crystal_cap + 1); + PHYDM_DBG(dm, DBG_CFO_TRK, "approch to init-val 0x%x\n", + cfo_track->crystal_cap); } +#if ODM_IC_11N_SERIES_SUPPORT #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - odm_set_atc_status(p_dm_odm, true); + if (dm->support_ic_type & ODM_IC_11N_SERIES) + phydm_set_atc_status(dm, true); +#endif #endif } -void -odm_cfo_tracking_init( - void *p_dm_void -) +void phydm_cfo_tracking_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - - p_cfo_track->def_x_cap = p_cfo_track->crystal_cap = odm_get_default_crytaltal_cap(p_dm_odm); - p_cfo_track->is_atc_status = odm_get_atc_status(p_dm_odm); - p_cfo_track->is_adjust = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========>\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): is_atc_status = %d, crystal_cap = 0x%x\n", p_cfo_track->is_atc_status, p_cfo_track->def_x_cap)); - -#if RTL8822B_SUPPORT - /* Crystal cap. control by WiFi */ - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - odm_set_bb_reg(p_dm_odm, 0x10, 0x40, 0x1); -#endif - -#if RTL8821C_SUPPORT - /* Crystal cap. control by WiFi */ - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - odm_set_bb_reg(p_dm_odm, 0x10, 0x40, 0x1); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + + PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]=========>\n", __func__); + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B)) + cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x7F; + else + cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x3f; + + cfo_track->def_x_cap = cfo_track->crystal_cap; + cfo_track->is_adjust = true; + PHYDM_DBG(dm, DBG_CFO_TRK, "crystal_cap=0x%x\n", cfo_track->def_x_cap); + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT) + /* @Crystal cap. control by WiFi */ + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) + odm_set_mac_reg(dm, R_0x10, 0x40, 0x1); #endif } -void -odm_cfo_tracking( - void *p_dm_void -) +void phydm_cfo_tracking(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - s32 CFO_ave = 0; - u32 CFO_rpt_sum, cfo_khz_avg[4] = {0}; - s32 CFO_ave_diff; - s8 crystal_cap = p_cfo_track->crystal_cap; - u8 adjust_xtal = 1, i, valid_path_cnt = 0; - - /* 4 Support ability */ - if (!(p_dm_odm->support_ability & ODM_BB_CFO_TRACKING)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Return: support_ability ODM_BB_CFO_TRACKING is disabled\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + s32 cfo_avg = 0, cfo_path_sum = 0, cfo_abs = 0; + u32 cfo_rpt_sum = 0, cfo_khz_avg[4] = {0}; + s8 crystal_cap = cfo_track->crystal_cap; + u8 i = 0, valid_path_cnt = 0; + + if (!(dm->support_ability & ODM_BB_CFO_TRACKING)) return; - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking()=========>\n")); + PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__); + + if (!dm->is_linked || !dm->is_one_entry_only) { + phydm_cfo_tracking_reset(dm); + PHYDM_DBG(dm, DBG_CFO_TRK, "is_linked=%d, one_entry_only=%d\n", + dm->is_linked, dm->is_one_entry_only); - if (!p_dm_odm->is_linked || !p_dm_odm->is_one_entry_only) { - /* 4 No link or more than one entry */ - odm_cfo_tracking_reset(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Reset: is_linked = %d, is_one_entry_only = %d\n", - p_dm_odm->is_linked, p_dm_odm->is_one_entry_only)); } else { - /* 3 1. CFO Tracking */ - /* 4 1.1 No new packet */ - if (p_cfo_track->packet_count == p_cfo_track->packet_count_pre) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): packet counter doesn't change\n")); + /* No new packet */ + if (cfo_track->packet_count == cfo_track->packet_count_pre) { + PHYDM_DBG(dm, DBG_CFO_TRK, "Pkt cnt doesn't change\n"); return; } - p_cfo_track->packet_count_pre = p_cfo_track->packet_count; + cfo_track->packet_count_pre = cfo_track->packet_count; - /* 4 1.2 Calculate CFO */ - for (i = 0; i < p_dm_odm->num_rf_path; i++) { - - if (p_cfo_track->CFO_cnt[i] == 0) + /*@Calculate CFO */ + for (i = 0; i < dm->num_rf_path; i++) { + if (cfo_track->CFO_cnt[i] == 0) continue; valid_path_cnt++; - CFO_rpt_sum = (u32)((p_cfo_track->CFO_tail[i] < 0) ? (0 - p_cfo_track->CFO_tail[i]) : p_cfo_track->CFO_tail[i]); - cfo_khz_avg[i] = CFO_HW_RPT_2_MHZ(CFO_rpt_sum) / p_cfo_track->CFO_cnt[i]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[path %d] CFO_rpt_sum = (( %d )), CFO_cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n", - i, CFO_rpt_sum, p_cfo_track->CFO_cnt[i], ((p_cfo_track->CFO_tail[i] < 0) ? "-" : " "), cfo_khz_avg[i])); + if (cfo_track->CFO_tail[i] < 0) + cfo_abs = 0 - cfo_track->CFO_tail[i]; + else + cfo_abs = cfo_track->CFO_tail[i]; + + cfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(cfo_abs); + cfo_khz_avg[i] = cfo_rpt_sum / cfo_track->CFO_cnt[i]; + + PHYDM_DBG(dm, DBG_CFO_TRK, + "[Path-%d] CFO_sum=((%d)), cnt=((%d)), CFO_avg=((%s%d))kHz\n", + i, cfo_rpt_sum, cfo_track->CFO_cnt[i], + ((cfo_track->CFO_tail[i] < 0) ? "-" : " "), + cfo_khz_avg[i]); } for (i = 0; i < valid_path_cnt; i++) { - - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("path [%d], p_cfo_track->CFO_tail = %d\n", i, p_cfo_track->CFO_tail[i])); */ - if (p_cfo_track->CFO_tail[i] < 0) { - CFO_ave += (0 - (s32)cfo_khz_avg[i]); - /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("CFO_ave = %d\n", CFO_ave)); */ - } else - CFO_ave += (s32)cfo_khz_avg[i]; + if (cfo_track->CFO_tail[i] < 0) + cfo_path_sum += (0 - (s32)cfo_khz_avg[i]); + else + cfo_path_sum += (s32)cfo_khz_avg[i]; } if (valid_path_cnt >= 2) - CFO_ave = CFO_ave / valid_path_cnt; + cfo_avg = cfo_path_sum / valid_path_cnt; + else + cfo_avg = cfo_path_sum; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("valid_path_cnt = ((%d)), CFO_ave = ((%d kHz))\n", valid_path_cnt, CFO_ave)); + cfo_track->CFO_ave_pre = cfo_avg; + + PHYDM_DBG(dm, DBG_CFO_TRK, "path_cnt=%d, CFO_avg_path=%d kHz\n", + valid_path_cnt, cfo_avg); /*reset counter*/ - for (i = 0; i < p_dm_odm->num_rf_path; i++) { - p_cfo_track->CFO_tail[i] = 0; - p_cfo_track->CFO_cnt[i] = 0; + for (i = 0; i < dm->num_rf_path; i++) { + cfo_track->CFO_tail[i] = 0; + cfo_track->CFO_cnt[i] = 0; } - /* 4 1.3 Avoid abnormal large CFO */ - CFO_ave_diff = (p_cfo_track->CFO_ave_pre >= CFO_ave) ? (p_cfo_track->CFO_ave_pre - CFO_ave) : (CFO_ave - p_cfo_track->CFO_ave_pre); - if (CFO_ave_diff > 20 && p_cfo_track->large_cfo_hit == 0 && !p_cfo_track->is_adjust) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): first large CFO hit\n")); - p_cfo_track->large_cfo_hit = 1; - return; - } else - p_cfo_track->large_cfo_hit = 0; - p_cfo_track->CFO_ave_pre = CFO_ave; - - /* 4 1.4 Dynamic Xtal threshold */ - if (p_cfo_track->is_adjust == false) { - if (CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH)) - p_cfo_track->is_adjust = true; + /* To adjust crystal cap or not */ + if (!cfo_track->is_adjust) { + if (cfo_avg > CFO_TRK_ENABLE_TH || + cfo_avg < (-CFO_TRK_ENABLE_TH)) + cfo_track->is_adjust = true; } else { - if (CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW)) - p_cfo_track->is_adjust = false; + if (cfo_avg < CFO_TRK_STOP_TH && + cfo_avg > (-CFO_TRK_STOP_TH)) + cfo_track->is_adjust = false; } -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - /* 4 1.5 BT case: Disable CFO tracking */ - if (p_dm_odm->is_bt_enabled) { - p_cfo_track->is_adjust = false; - odm_set_crystal_cap(p_dm_odm, p_cfo_track->def_x_cap); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Disable CFO tracking for BT!!\n")); - } -#if 0 - /* 4 1.6 Big jump */ - if (p_cfo_track->is_adjust) { - if (CFO_ave > CFO_TH_XTAL_LOW) - adjust_xtal = adjust_xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2); - else if (CFO_ave < (-CFO_TH_XTAL_LOW)) - adjust_xtal = adjust_xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Crystal cap offset = %d\n", adjust_xtal)); + #ifdef ODM_CONFIG_BT_COEXIST + /*@BT case: Disable CFO tracking */ + if (dm->bt_info_table.is_bt_enabled) { + cfo_track->is_adjust = false; + phydm_set_crystal_cap(dm, cfo_track->def_x_cap); + PHYDM_DBG(dm, DBG_CFO_TRK, "[BT]Disable CFO_track\n"); } -#endif -#endif - - /* 4 1.7 Adjust Crystal Cap. */ - if (p_cfo_track->is_adjust) { - if (CFO_ave > CFO_TH_XTAL_LOW) - crystal_cap = crystal_cap + adjust_xtal; - else if (CFO_ave < (-CFO_TH_XTAL_LOW)) - crystal_cap = crystal_cap - adjust_xtal; - - if (crystal_cap > 0x3f) - crystal_cap = 0x3f; - else if (crystal_cap < 0) + #endif + + /*@Adjust Crystal Cap. */ + if (cfo_track->is_adjust) { + if (cfo_avg > CFO_TRK_STOP_TH) + crystal_cap += 1; + else if (cfo_avg < (-CFO_TRK_STOP_TH)) + crystal_cap -= 1; + + if (dm->support_ic_type & (ODM_RTL8822C | + ODM_RTL8814B)) { + if (crystal_cap > 0x7F) + crystal_cap = 0x7F; + } else { + if (crystal_cap > 0x3F) + crystal_cap = 0x3F; + } + if (crystal_cap < 0) crystal_cap = 0; - odm_set_crystal_cap(p_dm_odm, (u8)crystal_cap); + phydm_set_crystal_cap(dm, (u8)crystal_cap); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n", - p_cfo_track->crystal_cap, p_cfo_track->def_x_cap)); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - return; + PHYDM_DBG(dm, DBG_CFO_TRK, "X_cap{Curr,Default}={0x%x,0x%x}\n", + cfo_track->crystal_cap, cfo_track->def_x_cap); + + /* @Dynamic ATC switch */ + #if ODM_IC_11N_SERIES_SUPPORT + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (cfo_avg < CFO_TH_ATC && cfo_avg > -CFO_TH_ATC) + phydm_set_atc_status(dm, false); + else + phydm_set_atc_status(dm, true); - /* 3 2. Dynamic ATC switch */ - if (CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) { - odm_set_atc_status(p_dm_odm, false); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Disable ATC!!\n")); - } else { - odm_set_atc_status(p_dm_odm, true); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Enable ATC!!\n")); } -#endif + #endif + #endif } } -void -odm_parsing_cfo( - void *p_dm_void, - void *p_pktinfo_void, - s8 *pcfotail, - u8 num_ss -) +void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail, + u8 num_ss) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pktinfo_void; - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - u8 i; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_perpkt_info_struct *pktinfo = NULL; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + boolean valid_info = false; + u8 i = 0; - if (!(p_dm_odm->support_ability & ODM_BB_CFO_TRACKING)) + if (!(dm->support_ability & ODM_BB_CFO_TRACKING)) return; + pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void; + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (p_pktinfo->is_packet_match_bssid) + if (pktinfo->is_packet_match_bssid) + valid_info = true; #else - if (p_pktinfo->station_id != 0) + if (dm->number_active_client == 1) + valid_info = true; #endif - { - if (num_ss > p_dm_odm->num_rf_path) /*For fool proof*/ - num_ss = p_dm_odm->num_rf_path; - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("num_ss = ((%d)), p_dm_odm->num_rf_path = ((%d))\n", num_ss, p_dm_odm->num_rf_path));*/ - - - /* 3 Update CFO report for path-A & path-B */ + if (valid_info) { + if (num_ss > dm->num_rf_path) /*@For fool proof*/ + num_ss = dm->num_rf_path; + #if 0 + PHYDM_DBG(dm, DBG_CFO_TRK, "num_ss=%d, num_rf_path=%d\n", + num_ss, dm->num_rf_path); + #endif + + /* @ Update CFO report for path-A & path-B */ /* Only paht-A and path-B have CFO tail and short CFO */ for (i = 0; i < num_ss; i++) { - p_cfo_track->CFO_tail[i] += pcfotail[i]; - p_cfo_track->CFO_cnt[i]++; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n", - p_pktinfo->station_id, i, p_pktinfo->data_rate, pcfotail[i], p_cfo_track->CFO_tail[i], p_cfo_track->CFO_cnt[i])); - */ + cfo_track->CFO_tail[i] += pcfotail[i]; + cfo_track->CFO_cnt[i]++; + #if 0 + PHYDM_DBG(dm, DBG_CFO_TRK, + "[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n", + pktinfo->station_id, i, pktinfo->data_rate, + pcfotail[i], cfo_track->CFO_tail[i], + cfo_track->CFO_cnt[i]); + #endif } - /* 3 Update packet counter */ - if (p_cfo_track->packet_count == 0xffffffff) - p_cfo_track->packet_count = 0; + /* @ Update packet counter */ + if (cfo_track->packet_count == 0xffffffff) + cfo_track->packet_count = 0; else - p_cfo_track->packet_count++; + cfo_track->packet_count++; } } diff --git a/hal/phydm/phydm_cfotracking.h b/hal/phydm/phydm_cfotracking.h index 1d9a67c..3e31942 100644 --- a/hal/phydm/phydm_cfotracking.h +++ b/hal/phydm/phydm_cfotracking.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,62 +8,60 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -#ifndef __PHYDMCFOTRACK_H__ -#define __PHYDMCFOTRACK_H__ +#ifndef __PHYDMCFOTRACK_H__ +#define __PHYDMCFOTRACK_H__ -#define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/ +#define CFO_TRACKING_VERSION "2.0" -#define CFO_TH_XTAL_HIGH 20 /* kHz */ -#define CFO_TH_XTAL_LOW 10 /* kHz */ -#define CFO_TH_ATC 80 /* kHz */ +#define CFO_TRK_ENABLE_TH 20 /* @kHz enable CFO_Track threshold*/ +#define CFO_TRK_STOP_TH 10 /* @kHz disable CFO_Track threshold*/ +#define CFO_TH_ATC 80 /* @kHz */ -struct _CFO_TRACKING_ { - boolean is_atc_status; - boolean large_cfo_hit; - boolean is_adjust; - u8 crystal_cap; - u8 def_x_cap; - s32 CFO_tail[4]; - u32 CFO_cnt[4]; - s32 CFO_ave_pre; - u32 packet_count; - u32 packet_count_pre; +struct phydm_cfo_track_struct { + boolean is_atc_status; + boolean is_adjust; /*@already modify crystal cap*/ + u8 crystal_cap; + u8 crystal_cap_default; + u8 def_x_cap; + s32 CFO_tail[4]; + u32 CFO_cnt[4]; + s32 CFO_ave_pre; + u32 packet_count; + u32 packet_count_pre; +}; - boolean is_force_xtal_cap; - boolean is_reset; +struct phydm_cfo_rpt { + s32 cfo_rpt_s[PHYDM_MAX_RF_PATH]; + s32 cfo_rpt_l[PHYDM_MAX_RF_PATH]; + s32 cfo_rpt_acq[PHYDM_MAX_RF_PATH]; + s32 cfo_rpt_sec[PHYDM_MAX_RF_PATH]; + s32 cfo_rpt_end[PHYDM_MAX_RF_PATH]; }; -void -odm_cfo_tracking_reset( - void *p_dm_void -); +void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo); + +void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap); -void -odm_cfo_tracking_init( - void *p_dm_void -); +void phydm_cfo_tracking_init(void *dm_void); -void -odm_cfo_tracking( - void *p_dm_void -); +void phydm_cfo_tracking(void *dm_void); -void -odm_parsing_cfo( - void *p_dm_void, - void *p_pktinfo_void, - s8 *pcfotail, - u8 num_ss -); +void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail, + u8 num_ss); #endif diff --git a/hal/phydm/phydm_debug.c b/hal/phydm/phydm_debug.c index 701d6cf..cfc7fb6 100644 --- a/hal/phydm/phydm_debug.c +++ b/hal/phydm/phydm_debug.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,385 +8,191 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -/* ************************************************************ +/*@************************************************************ * include files - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" -void -phydm_init_debug_setting( - struct PHY_DM_STRUCT *p_dm_odm -) +void phydm_init_debug_setting(struct dm_struct *dm) { - p_dm_odm->debug_level = ODM_DBG_TRACE; + dm->fw_debug_components = 0; + dm->debug_components = - p_dm_odm->fw_debug_components = 0; - p_dm_odm->debug_components = - \ #if DBG - /*BB Functions*/ - /* ODM_COMP_DIG |*/ - /* ODM_COMP_RA_MASK |*/ - /* ODM_COMP_DYNAMIC_TXPWR |*/ - /* ODM_COMP_FA_CNT |*/ - /* ODM_COMP_RSSI_MONITOR |*/ - /* ODM_COMP_SNIFFER |*/ - /* ODM_COMP_ANT_DIV |*/ - /* ODM_COMP_NOISY_DETECT |*/ - /* ODM_COMP_RATE_ADAPTIVE |*/ - /* ODM_COMP_PATH_DIV |*/ - /* ODM_COMP_DYNAMIC_PRICCA |*/ - /* ODM_COMP_MP |*/ - /* ODM_COMP_CFO_TRACKING |*/ - /* ODM_COMP_ACS |*/ - /* PHYDM_COMP_ADAPTIVITY |*/ - /* PHYDM_COMP_RA_DBG |*/ - /* PHYDM_COMP_TXBF |*/ - - /*MAC Functions*/ - /* ODM_COMP_EDCA_TURBO |*/ - /* ODM_COMP_DYNAMIC_RX_PATH |*/ - /* ODM_FW_DEBUG_TRACE |*/ - - /*RF Functions*/ - /* ODM_COMP_TX_PWR_TRACK |*/ - /* ODM_COMP_CALIBRATION |*/ - - /*Common*/ - /* ODM_PHY_CONFIG |*/ - /* ODM_COMP_INIT |*/ - /* ODM_COMP_COMMON |*/ - /* ODM_COMP_API |*/ - - -#endif - 0; - - p_dm_odm->fw_buff_is_enpty = true; - p_dm_odm->pre_c2h_seq = 0; + /*@BB Functions*/ + /*@DBG_DIG |*/ + /*@DBG_RA_MASK |*/ + /*@DBG_DYN_TXPWR |*/ + /*@DBG_FA_CNT |*/ + /*@DBG_RSSI_MNTR |*/ + /*@DBG_CCKPD |*/ + /*@DBG_ANT_DIV |*/ + /*@DBG_SMT_ANT |*/ + /*@DBG_PWR_TRAIN |*/ + /*@DBG_RA |*/ + /*@DBG_PATH_DIV |*/ + /*@DBG_DFS |*/ + /*@DBG_DYN_ARFR |*/ + /*@DBG_ADPTVTY |*/ + /*@DBG_CFO_TRK |*/ + /*@DBG_ENV_MNTR |*/ + /*@DBG_PRI_CCA |*/ + /*@DBG_ADPTV_SOML |*/ + /*@DBG_LNA_SAT_CHK |*/ + /*@DBG_PHY_STATUS |*/ + /*@DBG_TMP |*/ + /*@DBG_FW_TRACE |*/ + /*@DBG_TXBF |*/ + /*@DBG_COMMON_FLOW |*/ + /*@ODM_PHY_CONFIG |*/ + /*@ODM_COMP_INIT |*/ + /*@DBG_CMN |*/ + /*@ODM_COMP_API |*/ +#endif + 0; + + dm->fw_buff_is_enpty = true; + dm->pre_c2h_seq = 0; + dm->c2h_cmd_start = 0; + dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD; + dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD; + phydm_reset_rx_rate_distribution(dm); } -void -phydm_bb_dbg_port_header_sel( - void *p_dm_void, - u32 header_idx -) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0x8f8, (BIT(25) | BIT(24) | BIT(23) | BIT(22)), header_idx); - - /* - header_idx: - (0:) '{ofdm_dbg[31:0]}' - (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}' - (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}' - (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}' - (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}' - (5:) '{dbg_iqk_anta}' - (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}' - (7:) '{dbg_iqk_antb}' - (8:) '{DBGOUT_RFC_b[31:0]}' - (9:) '{DBGOUT_RFC_a[31:0]}' - (a:) '{dbg_ofdm}' - (b:) '{dbg_cck}' - */ +void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x8f8, 0x3c00000, header_idx); + + /*@ + * header_idx: + * (0:) '{ofdm_dbg[31:0]}' + * (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}' + * (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}' + * (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}' + * (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}' + * (5:) '{dbg_iqk_anta}' + * (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}' + * (7:) '{dbg_iqk_antb}' + * (8:) '{DBGOUT_RFC_b[31:0]}' + * (9:) '{DBGOUT_RFC_a[31:0]}' + * (a:) '{dbg_ofdm}' + * (b:) '{dbg_cck}' + */ } } -void -phydm_bb_dbg_port_clock_en( - void *p_dm_void, - u8 enable -) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 reg_value = (enable == TRUE) ? 0x7 : 0; - - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814A | ODM_RTL8814B)) { - - odm_set_bb_reg(p_dm_odm, 0x198c, 0x7, reg_value); /*enable/disable debug port clock, for power saving*/ +void phydm_bb_dbg_port_clock_en(void *dm_void, u8 enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_value = 0; + + if (dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814A | ODM_RTL8814B)) { + /*@enable/disable debug port clock, for power saving*/ + reg_value = enable ? 0x7 : 0; + odm_set_bb_reg(dm, R_0x198c, 0x7, reg_value); } } -u8 -phydm_set_bb_dbg_port( - void *p_dm_void, - u8 curr_dbg_priority, - u32 debug_port -) +u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 dbg_port_result = FALSE; - - if (curr_dbg_priority > p_dm_odm->pre_dbg_priority) { - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - phydm_bb_dbg_port_clock_en(p_dm_odm, TRUE); - - odm_set_bb_reg(p_dm_odm, 0x8fc, MASKDWORD, debug_port); - /**/ - } else /*if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)*/ { - odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, debug_port); - /**/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 dbg_port_result = false; + + if (curr_dbg_priority > dm->pre_dbg_priority) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + phydm_bb_dbg_port_clock_en(dm, true); + + odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, debug_port); + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0x1c3c, 0xfff00, debug_port); + + } else { /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/ + odm_set_bb_reg(dm, R_0x908, MASKDWORD, debug_port); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("DbgPort set success, Reg((0x%x)), Cur_priority=((%d)), Pre_priority=((%d))\n", debug_port, curr_dbg_priority, p_dm_odm->pre_dbg_priority)); - p_dm_odm->pre_dbg_priority = curr_dbg_priority; - dbg_port_result = TRUE; + PHYDM_DBG(dm, ODM_COMP_API, + "DbgPort ((0x%x)) set success, Cur_priority=((%d)), Pre_priority=((%d))\n", + debug_port, curr_dbg_priority, dm->pre_dbg_priority); + dm->pre_dbg_priority = curr_dbg_priority; + dbg_port_result = true; } - + return dbg_port_result; } -void -phydm_release_bb_dbg_port( - void *p_dm_void -) +void phydm_release_bb_dbg_port(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - phydm_bb_dbg_port_clock_en(p_dm_odm, FALSE); - phydm_bb_dbg_port_header_sel(p_dm_odm, 0); + phydm_bb_dbg_port_clock_en(dm, false); + phydm_bb_dbg_port_header_sel(dm, 0); - p_dm_odm->pre_dbg_priority = BB_DBGPORT_RELEASE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Release BB dbg_port\n")); + dm->pre_dbg_priority = DBGPORT_RELEASE; + PHYDM_DBG(dm, ODM_COMP_API, "Release BB dbg_port\n"); } -u32 -phydm_get_bb_dbg_port_value( - void *p_dm_void -) +u32 phydm_get_bb_dbg_port_val(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 dbg_port_value = 0; - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - dbg_port_value = odm_get_bb_reg(p_dm_odm, 0xfa0, MASKDWORD); - /**/ - } else /*if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)*/ { - dbg_port_value = odm_get_bb_reg(p_dm_odm, 0xdf4, MASKDWORD); - /**/ - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("dbg_port_value = 0x%x\n", dbg_port_value)); - return dbg_port_value; -} - -#if CONFIG_PHYDM_DEBUG_FUNCTION -void -phydm_bb_rx_hang_info( - void *p_dm_void, - u32 *_used, - char *output, - u32 *_out_len -) -{ - u32 value32 = 0; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 used = *_used; - u32 out_len = *_out_len; - - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - return; - - value32 = odm_get_bb_reg(p_dm_odm, 0xF80, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32)); - - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - odm_set_bb_reg(p_dm_odm, 0x198c, BIT(2) | BIT(1) | BIT(0), 7); - - /* dbg_port = basic state machine */ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "basic state machine", value32)); - } - - /* dbg_port = state machine */ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "state machine", value32)); - } - - /* dbg_port = CCA-related*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "CCA-related", value32)); - } - - - /* dbg_port = edcca/rxd*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "edcca/rxd", value32)); - } - - /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx_state/mux_state/ADC_MASK_OFDM", value32)); - } - - /* dbg_port = bf-related*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "bf-related", value32)); - } - - /* dbg_port = bf-related*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "bf-related", value32)); - } - - /* dbg_port = txon/rxd*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "txon/rxd", value32)); - } - - /* dbg_port = l_rate/l_length*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "l_rate/l_length", value32)); - } - - /* dbg_port = rxd/rxd_hit*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32)); - } - - /* dbg_port = dis_cca*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "dis_cca", value32)); - } - - - /* dbg_port = tx*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "tx", value32)); - } - - /* dbg_port = rx plcp*/ - { - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - - odm_set_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3); - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_DBG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "0x8fc", value32)); - - value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_RPT_11AC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = 0x%x", "rx plcp", value32)); - } - + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 dbg_port_value = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + dbg_port_value = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD); + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + dbg_port_value = odm_get_bb_reg(dm, R_0x2dbc, MASKDWORD); + else /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/ + dbg_port_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD); + + PHYDM_DBG(dm, ODM_COMP_API, "dbg_port_value = 0x%x\n", dbg_port_value); + return dbg_port_value; } -void -phydm_bb_debug_info_n_series( - void *p_dm_void, - u32 *_used, - char *output, - u32 *_out_len -) +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION +#if (ODM_IC_11N_SERIES_SUPPORT) +void phydm_bb_hw_dbg_info_n(void *dm_void, u32 *_used, char *output, + u32 *_out_len) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 used = *_used; u32 out_len = *_out_len; + u32 value32 = 0, value32_1 = 0; + u8 rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0; + u8 rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0; + s8 rxevm_0 = 0, rxevm_1 = 0; + #if 1 + struct phydm_cfo_rpt cfo; + u8 i = 0; + #else + s32 short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0; + s32 scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0; + s32 cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a = 0, acq_cfo_b = 0; + #endif - u32 value32 = 0, value32_1 = 0, value32_2 = 0, value32_3 = 0; - u8 rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0; - u8 rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0; - - s8 rxevm_0 = 0, rxevm_1 = 0; - s32 short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0; - s32 scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0; - s32 cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a = 0, acq_cfo_b = 0; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s\n", "BB Report Info")); + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n", + "BB Report Info"); - /*AGC result*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xdd0, MASKDWORD); + /*@AGC result*/ + value32 = odm_get_bb_reg(dm, R_0xdd0, MASKDWORD); rf_gain_a = (u8)(value32 & 0x3f); rf_gain_a = rf_gain_a << 1; @@ -399,10 +205,12 @@ phydm_bb_debug_info_n_series( rf_gain_d = (u8)((value32 >> 24) & 0x3f); rf_gain_d = rf_gain_d << 1; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", rf_gain_a, rf_gain_b, rf_gain_c, rf_gain_d)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", + rf_gain_a, rf_gain_b, rf_gain_c, rf_gain_d); /*SNR report*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xdd4, MASKDWORD); + value32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD); rx_snr_a = (u8)(value32 & 0xff); rx_snr_a = rx_snr_a >> 1; @@ -415,10 +223,12 @@ phydm_bb_debug_info_n_series( rx_snr_d = (u8)((value32 >> 24) & 0xff); rx_snr_d = rx_snr_d >> 1; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", + rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d); /* PostFFT related info*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xdd8, MASKDWORD); + value32 = odm_get_bb_reg(dm, R_0xdd8, MASKDWORD); rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); rxevm_0 /= 2; @@ -430,19 +240,30 @@ phydm_bb_debug_info_n_series( if (rxevm_1 < -63) rxevm_1 = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "RXEVM (1ss/2ss)", rxevm_0, rxevm_1)); - - /*CFO Report Info*/ - odm_set_bb_reg(p_dm_odm, 0xd00, BIT(26), 1); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "RXEVM (1ss/2ss)", rxevm_0, rxevm_1); + +#if 1 + phydm_get_cfo_info(dm, &cfo); + for (i = 0; i < dm->num_rf_path; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %s[%d] %-28s = {%d, %d, %d, %d, %d}", + "CFO", i, "{S, L, Sec, Acq, End}", + cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i], + cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]); + } +#else + /*@CFO Report Info*/ + odm_set_bb_reg(dm, R_0xd00, BIT(26), 1); /*Short CFO*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xdac, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xdb0, MASKDWORD); + value32 = odm_get_bb_reg(dm, R_0xdac, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, R_0xdb0, MASKDWORD); - short_cfo_b = (s32)(value32 & 0xfff); /*S(12,11)*/ + short_cfo_b = (s32)(value32 & 0xfff); /*S(12,11)*/ short_cfo_a = (s32)((value32 & 0x0fff0000) >> 16); - long_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ + long_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ long_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16); /*SFO 2's to dec*/ @@ -454,7 +275,7 @@ phydm_bb_debug_info_n_series( short_cfo_a = (short_cfo_a * 312500) / 2048; short_cfo_b = (short_cfo_b * 312500) / 2048; - /*LFO 2's to dec*/ + /*@LFO 2's to dec*/ if (long_cfo_a > 4095) long_cfo_a = long_cfo_a - 8192; @@ -465,15 +286,20 @@ phydm_bb_debug_info_n_series( long_cfo_a = long_cfo_a * 312500 / 4096; long_cfo_b = long_cfo_b * 312500 / 4096; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "CFO Report Info")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Short CFO(Hz) ", short_cfo_a, short_cfo_b)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Long CFO(Hz) ", long_cfo_a, long_cfo_b)); + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s", + "CFO Report Info"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "Short CFO(Hz) ", short_cfo_a, + short_cfo_b); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "Long CFO(Hz) ", long_cfo_a, + long_cfo_b); /*SCFO*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xdb8, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xdb4, MASKDWORD); + value32 = odm_get_bb_reg(dm, R_0xdb8, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, R_0xdb4, MASKDWORD); - scfo_b = (s32)(value32 & 0x7ff); /*S(11,10)*/ + scfo_b = (s32)(value32 & 0x7ff); /*S(11,10)*/ scfo_a = (s32)((value32 & 0x07ff0000) >> 16); if (scfo_a > 1023) @@ -485,7 +311,7 @@ phydm_bb_debug_info_n_series( scfo_a = scfo_a * 312500 / 1024; scfo_b = scfo_b * 312500 / 1024; - avg_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ + avg_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ avg_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16); if (avg_cfo_a > 4095) @@ -497,13 +323,17 @@ phydm_bb_debug_info_n_series( avg_cfo_a = avg_cfo_a * 312500 / 4096; avg_cfo_b = avg_cfo_b * 312500 / 4096; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "value SCFO(Hz) ", scfo_a, scfo_b)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "Avg CFO(Hz) ", avg_cfo_a, avg_cfo_b)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "value SCFO(Hz) ", scfo_a, + scfo_b); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "Avg CFO(Hz) ", avg_cfo_a, + avg_cfo_b); - value32 = odm_get_bb_reg(p_dm_odm, 0xdbc, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xde0, MASKDWORD); + value32 = odm_get_bb_reg(dm, R_0xdbc, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, R_0xde0, MASKDWORD); - cfo_end_b = (s32)(value32 & 0x1fff); /*S(13,12)*/ + cfo_end_b = (s32)(value32 & 0x1fff); /*S(13,12)*/ cfo_end_a = (s32)((value32 & 0x1fff0000) >> 16); if (cfo_end_a > 4095) @@ -515,7 +345,7 @@ phydm_bb_debug_info_n_series( cfo_end_a = cfo_end_a * 312500 / 4096; cfo_end_b = cfo_end_b * 312500 / 4096; - acq_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ + acq_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ acq_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16); if (acq_cfo_a > 4095) @@ -527,2354 +357,3769 @@ phydm_bb_debug_info_n_series( acq_cfo_a = acq_cfo_a * 312500 / 4096; acq_cfo_b = acq_cfo_b * 312500 / 4096; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "End CFO(Hz) ", cfo_end_a, cfo_end_b)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "ACQ CFO(Hz) ", acq_cfo_a, acq_cfo_b)); - + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "End CFO(Hz) ", cfo_end_a, + cfo_end_b); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "ACQ CFO(Hz) ", acq_cfo_a, + acq_cfo_b); +#endif } +#endif - -void -phydm_bb_debug_info( - void *p_dm_void, - u32 *_used, - char *output, - u32 *_out_len -) +#if (ODM_IC_11AC_SERIES_SUPPORT) +#if (RTL8822B_SUPPORT) +void phydm_bb_hw_dbg_info_8822b(void *dm_void, u32 *_used, char *output, + u32 *_out_len) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 used = *_used; u32 out_len = *_out_len; + u32 condi_num = 0; + u8 i = 0; - char *tmp_string = NULL; + if (!(dm->support_ic_type == ODM_RTL8822B)) + return; - u8 RX_HT_BW, RX_VHT_BW, RXSC, RX_HT, RX_BW; - static u8 v_rx_bw ; - u32 value32, value32_1, value32_2, value32_3; - s32 SFO_A, SFO_B, SFO_C, SFO_D; - s32 LFO_A, LFO_B, LFO_C, LFO_D; - static u8 MCSS, tail, parity, rsv, vrsv, idx, smooth, htsound, agg, stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts, vtxops, vrsv2, vbrsv, bf, vbcrc; - static u16 h_length, htcrc8, length; - static u16 vpaid; - static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail; - static u8 HMCSS, HRX_BW; + condi_num = phydm_get_condi_num_8822b(dm); + phydm_get_condi_num_acc_8822b(dm); - u8 pwdb; - s8 RXEVM_0, RXEVM_1, RXEVM_2 ; - u8 rf_gain_path_a, rf_gain_path_b, rf_gain_path_c, rf_gain_path_d; - u8 rx_snr_path_a, rx_snr_path_b, rx_snr_path_c, rx_snr_path_d; - s32 sig_power; + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d.%.4d", "condi_num", + condi_num >> 4, phydm_show_fraction_num(condi_num & 0xf, 4)); - const char *L_rate[8] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M"}; + for (i = 0; i < CN_CNT_MAX; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n Tone_num[CN>%d]%-21s = %d", + i, " ", dm->phy_dbg_info.condi_num_cdf[i]); + } -#if 0 - const double evm_comp_20M = 0.579919469776867; /* 10*log10(64.0/56.0) */ - const double evm_comp_40M = 0.503051183113957; /* 10*log10(128.0/114.0) */ - const double evm_comp_80M = 0.244245993314183; /* 10*log10(256.0/242.0) */ - const double evm_comp_160M = 0.244245993314183; /* 10*log10(512.0/484.0) */ + *_used = used; + *_out_len = out_len; +} #endif - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - phydm_bb_debug_info_n_series(p_dm_odm, &used, output, &out_len); - return; +void phydm_bb_hw_dbg_info_ac(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + char *tmp_string = NULL; + u8 rx_ht_bw, rx_vht_bw, rxsc, rx_ht, bw_idx = 0; + static u8 v_rx_bw; + u32 value32, value32_1, value32_2, value32_3; + struct phydm_cfo_rpt cfo; + u8 i = 0; + static u8 tail, parity, rsv, vrsv, smooth, htsound, agg; + static u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts; + static u8 vtxops, vrsv2, vbrsv, bf, vbcrc; + static u16 h_length, htcrc8, length; + static u16 vpaid; + static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail; + static u8 hmcss, hrx_bw; + u8 pwdb; + s8 rxevm_0, rxevm_1, rxevm_2; + u8 rf_gain[4]; + u8 rx_snr[4]; + s32 sig_power; + + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n", + "BB Report Info"); + + /*@ [BW & Mode] =====================================================*/ + + value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD); + rx_ht = (u8)((value32 & 0x180) >> 7); + + if (rx_ht == AD_VHT_MODE) { + tmp_string = "VHT"; + bw_idx = (u8)((value32 >> 1) & 0x3); + } else if (rx_ht == AD_HT_MODE) { + tmp_string = "HT"; + bw_idx = (u8)(value32 & 0x1); + } else { + tmp_string = "Legacy"; + bw_idx = 0; } + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s %s %dM", "mode", tmp_string, (20 << bw_idx)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s\n", "BB Report Info")); - - /*BW & mode Detection*/ - - value32 = odm_get_bb_reg(p_dm_odm, 0xf80, MASKDWORD); - value32_2 = value32; - RX_HT_BW = (u8)(value32 & 0x1); - RX_VHT_BW = (u8)((value32 >> 1) & 0x3); - RXSC = (u8)(value32 & 0x78); - value32_1 = (value32 & 0x180) >> 7; - RX_HT = (u8)(value32_1); + if (rx_ht != AD_LEGACY_MODE) { + rxsc = (u8)(value32 & 0x78); - RX_BW = 0; - - if (RX_HT == 2) { - if (RX_VHT_BW == 0) - tmp_string = "20M"; - else if (RX_VHT_BW == 1) - tmp_string = "40M"; - else - tmp_string = "80M"; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "mode", "VHT", tmp_string)); - RX_BW = RX_VHT_BW; - } else if (RX_HT == 1) { - if (RX_HT_BW == 0) - tmp_string = "20M"; - else if (RX_HT_BW == 1) - tmp_string = "40M"; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s %s", "mode", "HT", tmp_string)); - RX_BW = RX_HT_BW; - } else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s %s", "mode", "Legacy")); - - if (RX_HT != 0) { - if (RXSC == 0) + if (rxsc == 0) tmp_string = "duplicate/full bw"; - else if (RXSC == 1) + else if (rxsc == 1) tmp_string = "usc20-1"; - else if (RXSC == 2) + else if (rxsc == 2) tmp_string = "lsc20-1"; - else if (RXSC == 3) + else if (rxsc == 3) tmp_string = "usc20-2"; - else if (RXSC == 4) + else if (rxsc == 4) tmp_string = "lsc20-2"; - else if (RXSC == 9) + else if (rxsc == 9) tmp_string = "usc40"; - else if (RXSC == 10) + else if (rxsc == 10) tmp_string = "lsc40"; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s", tmp_string)); - } - - /* RX signal power and AGC related info*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xF90, MASKDWORD); - pwdb = (u8)((value32 & MASKBYTE1) >> 8); - pwdb = pwdb >> 1; - sig_power = -110 + pwdb; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power)); - - value32 = odm_get_bb_reg(p_dm_odm, 0xd14, MASKDWORD); - rx_snr_path_a = (u8)(value32 & 0xFF) >> 1; - rf_gain_path_a = (s8)((value32 & MASKBYTE1) >> 8); - rf_gain_path_a *= 2; - value32 = odm_get_bb_reg(p_dm_odm, 0xd54, MASKDWORD); - rx_snr_path_b = (u8)(value32 & 0xFF) >> 1; - rf_gain_path_b = (s8)((value32 & MASKBYTE1) >> 8); - rf_gain_path_b *= 2; - value32 = odm_get_bb_reg(p_dm_odm, 0xd94, MASKDWORD); - rx_snr_path_c = (u8)(value32 & 0xFF) >> 1; - rf_gain_path_c = (s8)((value32 & MASKBYTE1) >> 8); - rf_gain_path_c *= 2; - value32 = odm_get_bb_reg(p_dm_odm, 0xdd4, MASKDWORD); - rx_snr_path_d = (u8)(value32 & 0xFF) >> 1; - rf_gain_path_d = (s8)((value32 & MASKBYTE1) >> 8); - rf_gain_path_d *= 2; - - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", rf_gain_path_a, rf_gain_path_b, rf_gain_path_c, rf_gain_path_d)); - - - /* RX counter related info*/ - - value32 = odm_get_bb_reg(p_dm_odm, 0xF08, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM CCA counter", ((value32 & 0xFFFF0000) >> 16))); - - value32 = odm_get_bb_reg(p_dm_odm, 0xFD0, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "OFDM SBD Fail counter", value32 & 0xFFFF)); - - value32 = odm_get_bb_reg(p_dm_odm, 0xFC4, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail counter", value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16))); - - value32 = odm_get_bb_reg(p_dm_odm, 0xFCC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d", "CCK CCA counter", value32 & 0xFFFF)); - - value32 = odm_get_bb_reg(p_dm_odm, 0xFBC, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "LSIG (parity Fail/rate Illegal) counter", value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16))); - - value32_1 = odm_get_bb_reg(p_dm_odm, 0xFC8, MASKDWORD); - value32_2 = odm_get_bb_reg(p_dm_odm, 0xFC0, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT counter", ((value32_2 & 0xFFFF0000) >> 16), value32_1 & 0xFFFF)); + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s", tmp_string); + } - /* PostFFT related info*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xF8c, MASKDWORD); - RXEVM_0 = (s8)((value32 & MASKBYTE2) >> 16); - RXEVM_0 /= 2; - if (RXEVM_0 < -63) - RXEVM_0 = 0; + /*@ [RX signal power and AGC related info] ==========================*/ - RXEVM_1 = (s8)((value32 & MASKBYTE3) >> 24); - RXEVM_1 /= 2; - value32 = odm_get_bb_reg(p_dm_odm, 0xF88, MASKDWORD); - RXEVM_2 = (s8)((value32 & MASKBYTE2) >> 16); - RXEVM_2 /= 2; + pwdb = (u8)odm_get_bb_reg(dm, R_0xf90, MASKBYTE1); + sig_power = -110 + (pwdb >> 1); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power); - if (RXEVM_1 < -63) - RXEVM_1 = 0; - if (RXEVM_2 < -63) - RXEVM_2 = 0; + value32 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD); + rx_snr[RF_PATH_A] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/ + rf_gain[RF_PATH_A] = (s8)(((value32 & MASKBYTE1) >> 8) * 2); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", RXEVM_0, RXEVM_1, RXEVM_2)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", rx_snr_path_a, rx_snr_path_b, rx_snr_path_c, rx_snr_path_d)); + value32 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD); + rx_snr[RF_PATH_B] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/ + rf_gain[RF_PATH_B] = (s8)(((value32 & MASKBYTE1) >> 8) * 2); - value32 = odm_get_bb_reg(p_dm_odm, 0xF8C, MASKDWORD); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16))); + value32 = odm_get_bb_reg(dm, R_0xd94, MASKDWORD); + rx_snr[RF_PATH_C] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/ + rf_gain[RF_PATH_C] = (s8)(((value32 & MASKBYTE1) >> 8) * 2); - /*BW & mode Detection*/ + value32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD); + rx_snr[RF_PATH_D] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/ + rf_gain[RF_PATH_D] = (s8)(((value32 & MASKBYTE1) >> 8) * 2); - /*Reset Page F counter*/ - odm_set_bb_reg(p_dm_odm, 0xB58, BIT(0), 1); - odm_set_bb_reg(p_dm_odm, 0xB58, BIT(0), 0); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", + rf_gain[RF_PATH_A], rf_gain[RF_PATH_B], + rf_gain[RF_PATH_C], rf_gain[RF_PATH_D]); - /*CFO Report Info*/ - /*Short CFO*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xd0c, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xd4c, MASKDWORD); - value32_2 = odm_get_bb_reg(p_dm_odm, 0xd8c, MASKDWORD); - value32_3 = odm_get_bb_reg(p_dm_odm, 0xdcc, MASKDWORD); + /*@ [RX counter Info] ===============================================*/ - SFO_A = (s32)(value32 & 0xfff); - SFO_B = (s32)(value32_1 & 0xfff); - SFO_C = (s32)(value32_2 & 0xfff); - SFO_D = (s32)(value32_3 & 0xfff); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM CCA cnt", + odm_get_bb_reg(dm, R_0xf08, 0xFFFF0000)); - LFO_A = (s32)(value32 >> 16); - LFO_B = (s32)(value32_1 >> 16); - LFO_C = (s32)(value32_2 >> 16); - LFO_D = (s32)(value32_3 >> 16); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM SBD Fail cnt", + odm_get_bb_reg(dm, R_0xfd0, 0xFFFF)); - /*SFO 2's to dec*/ - if (SFO_A > 2047) - SFO_A = SFO_A - 4096; - SFO_A = (SFO_A * 312500) / 2048; - if (SFO_B > 2047) - SFO_B = SFO_B - 4096; - SFO_B = (SFO_B * 312500) / 2048; - if (SFO_C > 2047) - SFO_C = SFO_C - 4096; - SFO_C = (SFO_C * 312500) / 2048; - if (SFO_D > 2047) - SFO_D = SFO_D - 4096; - SFO_D = (SFO_D * 312500) / 2048; - - /*LFO 2's to dec*/ - - if (LFO_A > 4095) - LFO_A = LFO_A - 8192; - - if (LFO_B > 4095) - LFO_B = LFO_B - 8192; - - if (LFO_C > 4095) - LFO_C = LFO_C - 8192; - - if (LFO_D > 4095) - LFO_D = LFO_D - 8192; - LFO_A = LFO_A * 312500 / 4096; - LFO_B = LFO_B * 312500 / 4096; - LFO_C = LFO_C * 312500 / 4096; - LFO_D = LFO_D * 312500 / 4096; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "CFO Report Info")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Short CFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "Long CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); + value32 = odm_get_bb_reg(dm, R_0xfc4, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail cnt", + value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16)); - /*SCFO*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xd10, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xd50, MASKDWORD); - value32_2 = odm_get_bb_reg(p_dm_odm, 0xd90, MASKDWORD); - value32_3 = odm_get_bb_reg(p_dm_odm, 0xdd0, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "CCK CCA cnt", + odm_get_bb_reg(dm, R_0xfcc, 0xFFFF)); - SFO_A = (s32)(value32 & 0x7ff); - SFO_B = (s32)(value32_1 & 0x7ff); - SFO_C = (s32)(value32_2 & 0x7ff); - SFO_D = (s32)(value32_3 & 0x7ff); + value32 = odm_get_bb_reg(dm, R_0xfbc, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", + "LSIG (parity Fail/rate Illegal) cnt", value32 & 0xFFFF, + ((value32 & 0xFFFF0000) >> 16)); - if (SFO_A > 1023) - SFO_A = SFO_A - 2048; + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT cnt", + odm_get_bb_reg(dm, R_0xfc0, (0xFFFF0000 >> 16)), + odm_get_bb_reg(dm, R_0xfc8, 0xFFFF)); - if (SFO_B > 2047) - SFO_B = SFO_B - 4096; + /*@ [PostFFT Info] =================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD); + rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_0 /= 2; + if (rxevm_0 < -63) + rxevm_0 = 0; - if (SFO_C > 2047) - SFO_C = SFO_C - 4096; + rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24); + rxevm_1 /= 2; + value32 = odm_get_bb_reg(dm, R_0xf88, MASKDWORD); + rxevm_2 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_2 /= 2; - if (SFO_D > 2047) - SFO_D = SFO_D - 4096; + if (rxevm_1 < -63) + rxevm_1 = 0; + if (rxevm_2 < -63) + rxevm_2 = 0; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", rxevm_0, + rxevm_1, rxevm_2); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D dB)", + rx_snr[RF_PATH_A], rx_snr[RF_PATH_B], + rx_snr[RF_PATH_C], rx_snr[RF_PATH_D]); + + value32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32 & 0xFFFF, + ((value32 & 0xFFFF0000) >> 16)); + + /*@ [CFO Report Info] ===============================================*/ + phydm_get_cfo_info(dm, &cfo); + for (i = 0; i < dm->num_rf_path; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %s[%d] %-28s = {%d, %d, %d, %d, %d}", + "CFO", i, "{S, L, Sec, Acq, End}", + cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i], + cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]); + } - SFO_A = SFO_A * 312500 / 1024; - SFO_B = SFO_B * 312500 / 1024; - SFO_C = SFO_C * 312500 / 1024; - SFO_D = SFO_D * 312500 / 1024; + /*@ [L-SIG Content] =================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf20, MASKDWORD); + + tail = (u8)((value32 & 0xfc0000) >> 18);/*@[23:18]*/ + parity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/ + length = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/ + rsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s", + "L-SIG"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d M", "rate", + phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f))); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %d / %d", "Rsv/length/parity", rsv, length, + parity); + + if (rx_ht == AD_HT_MODE) { + /*@ [HT SIG 1] ======================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD); + + hmcss = (u8)(value32 & 0x7F); + hrx_bw = (u8)((value32 & 0x80) >> 7); + h_length = (u16)((value32 & 0x0fff00) >> 8); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "HT-SIG1"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d", "MCS/BW/length", + hmcss, hrx_bw, h_length); + /*@ [HT SIG 2] ======================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD); + smooth = (u8)(value32 & 0x01); + htsound = (u8)((value32 & 0x02) >> 1); + rsv = (u8)((value32 & 0x04) >> 2); + agg = (u8)((value32 & 0x08) >> 3); + stbc = (u8)((value32 & 0x30) >> 4); + fec = (u8)((value32 & 0x40) >> 6); + sgi = (u8)((value32 & 0x80) >> 7); + htltf = (u8)((value32 & 0x300) >> 8); + htcrc8 = (u16)((value32 & 0x3fc00) >> 10); + tail = (u8)((value32 & 0xfc0000) >> 18); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", + "HT-SIG2"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x", + "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", + smooth, htsound, rsv, agg, stbc, fec); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x", + "SGI/E-HT-LTFs/CRC/tail", + sgi, htltf, htcrc8, tail); + } else if (rx_ht == AD_VHT_MODE) { + /*@ [VHT SIG A1] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD); - LFO_A = (s32)(value32 >> 16); - LFO_B = (s32)(value32_1 >> 16); - LFO_C = (s32)(value32_2 >> 16); - LFO_D = (s32)(value32_3 >> 16); + v_rx_bw = (u8)(value32 & 0x03); + vrsv = (u8)((value32 & 0x04) >> 2); + vstbc = (u8)((value32 & 0x08) >> 3); + vgid = (u8)((value32 & 0x3f0) >> 4); + v_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1); + vpaid = (u16)((value32 & 0x3fe000) >> 13); + vtxops = (u8)((value32 & 0x400000) >> 22); + vrsv2 = (u8)((value32 & 0x800000) >> 23); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", + "VHT-SIG-A1"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x", + "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw, + vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2); + + /*@ [VHT SIG A2] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD); + + /* @sgi=(u8)(value32&0x01); */ + sgiext = (u8)(value32 & 0x03); + /* @fec = (u8)(value32&0x04); */ + fecext = (u8)((value32 & 0x0C) >> 2); - if (LFO_A > 4095) - LFO_A = LFO_A - 8192; + v_mcss = (u8)((value32 & 0xf0) >> 4); + bf = (u8)((value32 & 0x100) >> 8); + vrsv = (u8)((value32 & 0x200) >> 9); + vhtcrc8 = (u16)((value32 & 0x3fc00) >> 10); + v_tail = (u8)((value32 & 0xfc0000) >> 18); - if (LFO_B > 4095) - LFO_B = LFO_B - 8192; + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "VHT-SIG-A2"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x", + "SGI/FEC/MCS/BF/Rsv/CRC/tail", + sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail); - if (LFO_C > 4095) - LFO_C = LFO_C - 8192; + /*@ [VHT SIG B] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf34, MASKDWORD); - if (LFO_D > 4095) - LFO_D = LFO_D - 8192; - LFO_A = LFO_A * 312500 / 4096; - LFO_B = LFO_B * 312500 / 4096; - LFO_C = LFO_C * 312500 / 4096; - LFO_D = LFO_D * 312500 / 4096; + #if 0 + v_length = (u16)(value32 & 0x1fffff); + vbrsv = (u8)((value32 & 0x600000) >> 21); + vb_tail = (u16)((value32 & 0x1f800000) >> 23); + vbcrc = (u8)((value32 & 0x80000000) >> 31); + #endif - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "value SCFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "ACQ CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "VHT-SIG-B"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x", + "Codeword", value32); + + #if 0 + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x", + "length/Rsv/tail/CRC", + v_length, vbrsv, vb_tail, vbcrc); + #endif + } - value32 = odm_get_bb_reg(p_dm_odm, 0xd14, MASKDWORD); - value32_1 = odm_get_bb_reg(p_dm_odm, 0xd54, MASKDWORD); - value32_2 = odm_get_bb_reg(p_dm_odm, 0xd94, MASKDWORD); - value32_3 = odm_get_bb_reg(p_dm_odm, 0xdd4, MASKDWORD); + *_used = used; + *_out_len = out_len; +} +#endif - LFO_A = (s32)(value32 >> 16); - LFO_B = (s32)(value32_1 >> 16); - LFO_C = (s32)(value32_2 >> 16); - LFO_D = (s32)(value32_3 >> 16); +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_bb_hw_dbg_info_jgr3(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + char *tmp_string = NULL; + u8 rx_ht_bw = 0, rx_vht_bw = 0, rx_ht = 0; + static u8 v_rx_bw; + u32 value32 = 0; + u8 i = 0; + static u8 tail, parity, rsv, vrsv, smooth, htsound, agg; + static u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts; + static u8 vtxops, vrsv2, vbrsv, bf, vbcrc; + static u16 h_length, htcrc8, length; + static u16 vpaid; + static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail; + static u8 hmcss, hrx_bw; - if (LFO_A > 4095) - LFO_A = LFO_A - 8192; + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n", + "BB Report Info"); - if (LFO_B > 4095) - LFO_B = LFO_B - 8192; + /*@ [Mode] =====================================================*/ - if (LFO_C > 4095) - LFO_C = LFO_C - 8192; + value32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD); + rx_ht = (u8)((value32 & 0xC0000) >> 18); + if (rx_ht == AD_VHT_MODE) + tmp_string = "VHT"; + else if (rx_ht == AD_HT_MODE) + tmp_string = "HT"; + else + tmp_string = "Legacy"; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s %s", "mode", tmp_string); + /*@ [RX counter Info] ===============================================*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM CCA cnt", + odm_get_bb_reg(dm, R_0x2c08, 0xFFFF0000)); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM SBD Fail cnt", + odm_get_bb_reg(dm, R_0x2d20, 0xFFFF0000)); + + value32 = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail cnt", + value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16)); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "CCK CCA cnt", + odm_get_bb_reg(dm, R_0x2c08, 0xFFFF)); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", + "LSIG (parity Fail/rate Illegal) cnt", + odm_get_bb_reg(dm, R_0x2d04, 0xFFFF0000), + odm_get_bb_reg(dm, R_0x2d08, 0xFFFF)); + + value32 = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT cnt", + value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16)); + /*@ [L-SIG Content] =================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD); + + parity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/ + length = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/ + rsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s", + "L-SIG"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d M", "rate", + phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f))); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %d / %d", "Rsv/length/parity", rsv, length, + parity); + + if (rx_ht == AD_HT_MODE) { + /*@ [HT SIG 1] ======================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD); + + hmcss = (u8)(value32 & 0x7F); + hrx_bw = (u8)((value32 & 0x80) >> 7); + h_length = (u16)((value32 & 0x0fff00) >> 8); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "HT-SIG1"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d", "MCS/BW/length", + hmcss, hrx_bw, h_length); + /*@ [HT SIG 2] ======================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD); + smooth = (u8)(value32 & 0x01); + htsound = (u8)((value32 & 0x02) >> 1); + rsv = (u8)((value32 & 0x04) >> 2); + agg = (u8)((value32 & 0x08) >> 3); + stbc = (u8)((value32 & 0x30) >> 4); + fec = (u8)((value32 & 0x40) >> 6); + sgi = (u8)((value32 & 0x80) >> 7); + htltf = (u8)((value32 & 0x300) >> 8); + htcrc8 = (u16)((value32 & 0x3fc00) >> 10); + tail = (u8)((value32 & 0xfc0000) >> 18); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", + "HT-SIG2"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x", + "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", + smooth, htsound, rsv, agg, stbc, fec); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x", + "SGI/E-HT-LTFs/CRC/tail", + sgi, htltf, htcrc8, tail); + } else if (rx_ht == AD_VHT_MODE) { + /*@ [VHT SIG A1] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD); - if (LFO_D > 4095) - LFO_D = LFO_D - 8192; + v_rx_bw = (u8)(value32 & 0x03); + vrsv = (u8)((value32 & 0x04) >> 2); + vstbc = (u8)((value32 & 0x08) >> 3); + vgid = (u8)((value32 & 0x3f0) >> 4); + v_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1); + vpaid = (u16)((value32 & 0x3fe000) >> 13); + vtxops = (u8)((value32 & 0x400000) >> 22); + vrsv2 = (u8)((value32 & 0x800000) >> 23); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", + "VHT-SIG-A1"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x", + "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw, + vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2); + + /*@ [VHT SIG A2] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD); + + /* @sgi=(u8)(value32&0x01); */ + sgiext = (u8)(value32 & 0x03); + /* @fec = (u8)(value32&0x04); */ + fecext = (u8)((value32 & 0x0C) >> 2); - LFO_A = LFO_A * 312500 / 4096; - LFO_B = LFO_B * 312500 / 4096; - LFO_C = LFO_C * 312500 / 4096; - LFO_D = LFO_D * 312500 / 4096; + v_mcss = (u8)((value32 & 0xf0) >> 4); + bf = (u8)((value32 & 0x100) >> 8); + vrsv = (u8)((value32 & 0x200) >> 9); + vhtcrc8 = (u16)((value32 & 0x3fc00) >> 10); + v_tail = (u8)((value32 & 0xfc0000) >> 18); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "VHT-SIG-A2"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x", + "SGI/FEC/MCS/BF/Rsv/CRC/tail", + sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail); + + /*@ [VHT SIG B] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c34, MASKDWORD); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "VHT-SIG-B"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x", + "Codeword", value32); + + if (v_rx_bw == 0) { + v_length = (u16)(value32 & 0x1ffff); + vbrsv = (u8)((value32 & 0xE0000) >> 17); + vb_tail = (u16)((value32 & 0x03F00000) >> 20); + } else if (v_rx_bw == 1) { + v_length = (u16)(value32 & 0x7FFFF); + vbrsv = (u8)((value32 & 180000) >> 19); + vb_tail = (u16)((value32 & 0x07E00000) >> 21); + } else if (v_rx_bw == 2) { + v_length = (u16)(value32 & 0x1fffff); + vbrsv = (u8)((value32 & 0x600000) >> 21); + vb_tail = (u16)((value32 & 0x1f800000) >> 23); + } + vbcrc = (u8)((value32 & 0x80000000) >> 31); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d / %d / %d /%d", "End CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x", + "length/Rsv/tail/CRC", + v_length, vbrsv, vb_tail, vbcrc); + } - value32 = odm_get_bb_reg(p_dm_odm, 0xf20, MASKDWORD); /*L SIG*/ + *_used = used; + *_out_len = out_len; +} +#endif - tail = (u8)((value32 & 0xfc0000) >> 16); - parity = (u8)((value32 & 0x20000) >> 16); - length = (u16)((value32 & 0x1ffe00) >> 8); - rsv = (u8)(value32 & 0x10); - MCSS = (u8)(value32 & 0x0f); +u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig) +{ + u8 rate_idx = 0xff; - switch (MCSS) { + switch (rate_idx_l_sig) { case 0x0b: - idx = 0; + rate_idx = 6; break; case 0x0f: - idx = 1; + rate_idx = 9; break; case 0x0a: - idx = 2; + rate_idx = 12; break; case 0x0e: - idx = 3; + rate_idx = 18; break; case 0x09: - idx = 4; + rate_idx = 24; + break; + case 0x0d: + rate_idx = 36; break; case 0x08: - idx = 5; + rate_idx = 48; break; case 0x0c: - idx = 6; + rate_idx = 54; break; default: - idx = 6; + rate_idx = 0xff; break; - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "L-SIG")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s : %s", "rate", L_rate[idx])); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "Rsv/length/parity", rsv, RX_BW, length)); + return rate_idx; +} - value32 = odm_get_bb_reg(p_dm_odm, 0xf2c, MASKDWORD); /*HT SIG*/ - if (RX_HT == 1) { +void phydm_bb_hw_dbg_info(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; - HMCSS = (u8)(value32 & 0x7F); - HRX_BW = (u8)(value32 & 0x80); - h_length = (u16)((value32 >> 8) & 0xffff); - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "HT-SIG1")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x", "MCS/BW/length", HMCSS, HRX_BW, h_length)); + switch (dm->ic_ip_series) { + #if (ODM_IC_11N_SERIES_SUPPORT) + case PHYDM_IC_N: + phydm_bb_hw_dbg_info_n(dm, &used, output, &out_len); + break; + #endif - value32 = odm_get_bb_reg(p_dm_odm, 0xf30, MASKDWORD); /*HT SIG*/ + #if (ODM_IC_11AC_SERIES_SUPPORT) + case PHYDM_IC_AC: + phydm_bb_hw_dbg_info_ac(dm, &used, output, &out_len); + phydm_reset_bb_hw_cnt_ac(dm); + #if (RTL8822B_SUPPORT) + phydm_bb_hw_dbg_info_8822b(dm, &used, output, &out_len); + #endif + break; + #endif - if (RX_HT == 1) { - smooth = (u8)(value32 & 0x01); - htsound = (u8)(value32 & 0x02); - rsv = (u8)(value32 & 0x04); - agg = (u8)(value32 & 0x08); - stbc = (u8)(value32 & 0x30); - fec = (u8)(value32 & 0x40); - sgi = (u8)(value32 & 0x80); - htltf = (u8)((value32 & 0x300) >> 8); - htcrc8 = (u16)((value32 & 0x3fc00) >> 8); - tail = (u8)((value32 & 0xfc0000) >> 16); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + case PHYDM_IC_JGR3: + phydm_bb_hw_dbg_info_jgr3(dm, &used, output, &out_len); + break; + #endif + default: + break; } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "HT-SIG2")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x", "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", smooth, htsound, rsv, agg, stbc, fec)); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "SGI/E-HT-LTFs/CRC/tail", sgi, htltf, htcrc8, tail)); - value32 = odm_get_bb_reg(p_dm_odm, 0xf2c, MASKDWORD); /*VHT SIG A1*/ - if (RX_HT == 2) { - /* value32 = odm_get_bb_reg(p_dm_odm, 0xf2c,MASKDWORD);*/ - v_rx_bw = (u8)(value32 & 0x03); - vrsv = (u8)(value32 & 0x04); - vstbc = (u8)(value32 & 0x08); - vgid = (u8)((value32 & 0x3f0) >> 4); - v_nsts = (u8)(((value32 & 0x1c00) >> 8) + 1); - vpaid = (u16)(value32 & 0x3fe); - vtxops = (u8)((value32 & 0x400000) >> 20); - vrsv2 = (u8)((value32 & 0x800000) >> 20); - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-A1")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x", "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw, vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2)); + *_used = used; + *_out_len = out_len; +} - value32 = odm_get_bb_reg(p_dm_odm, 0xf30, MASKDWORD); /*VHT SIG*/ +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ - if (RX_HT == 2) { - /*value32 = odm_get_bb_reg(p_dm_odm, 0xf30,MASKDWORD); */ /*VHT SIG*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg->physts_statistic_info; + struct phydm_phystatus_avg *dbg_avg = &dbg->phystatus_statistic_avg; + u16 macid, phydm_macid, client_cnt = 0; + u8 i = 0; + u8 rate_num = dm->num_rf_path; + u8 ss_ofst = 0; + struct cmn_sta_info *entry = NULL; + char dbg_buf[PHYDM_SNPRINT_SIZE] = {0}; + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n PHYDM Common Dbg Msg --------->"); + RT_PRINT(buf); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n System up time=%d", dm->phydm_sys_up_time); + RT_PRINT(buf); + + if (dm->is_linked) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n ID=((%d)), BW=((%d)), fc=((CH-%d))", + dm->curr_station_id, 20 << *dm->band_width, *dm->channel); + RT_PRINT(buf); + + if (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) && + (dm->support_ic_type & ODM_IC_11N_SERIES)) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Primary CCA at ((%s SB))", + (*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? "U" : "L"); + RT_PRINT(buf); + } - /* sgi=(u8)(value32&0x01); */ - sgiext = (u8)(value32 & 0x03); - /* fec = (u8)(value32&0x04); */ - fecext = (u8)(value32 & 0x0C); + if ((dm->support_ic_type & PHYSTS_2ND_TYPE_IC) || dm->rx_rate > ODM_RATE11M) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}", + dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1], + dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]); + RT_PRINT(buf); + } else { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}", + dm->cck_lna_idx, dm->cck_vga_idx); + RT_PRINT(buf); + } - v_mcss = (u8)(value32 & 0xf0); - bf = (u8)((value32 & 0x100) >> 8); - vrsv = (u8)((value32 & 0x200) >> 8); - vhtcrc8 = (u16)((value32 & 0x3fc00) >> 8); - v_tail = (u8)((value32 & 0xfc0000) >> 16); - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-A2")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x", "SGI/FEC/MCS/BF/Rsv/CRC/tail", sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail)); + phydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)", + (dm->rssi_a == 0xff) ? 0 : dm->rssi_a, + (dm->rssi_b == 0xff) ? 0 : dm->rssi_b, + (dm->rssi_c == 0xff) ? 0 : dm->rssi_c, + (dm->rssi_d == 0xff) ? 0 : dm->rssi_d, + dbg_buf, dm->rx_rate); + RT_PRINT(buf); + + phydm_print_rate_2_buff(dm, dm->phy_dbg_info.beacon_phy_rate, dbg_buf, PHYDM_SNPRINT_SIZE); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Beacon_cnt=%d, rate_idx:%s (0x%x)", + dm->phy_dbg_info.beacon_cnt_in_period, + dbg_buf, + dm->phy_dbg_info.beacon_phy_rate); + RT_PRINT(buf); + + /*Show phydm_rx_rate_distribution;*/ + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [RxRate Cnt] =============>"); + RT_PRINT(buf); + + /*@======CCK=================================================*/ + if (*dm->channel <= 14) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * CCK = {%d, %d, %d, %d}", + dbg->num_qry_legacy_pkt[0], dbg->num_qry_legacy_pkt[1], + dbg->num_qry_legacy_pkt[2], dbg->num_qry_legacy_pkt[3]); + RT_PRINT(buf); + } + /*@======OFDM================================================*/ + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}", + dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5], + dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7], + dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9], + dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]); + RT_PRINT(buf); + + /*@======HT==================================================*/ + if (dbg->ht_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = (i << 3); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}", + (ss_ofst), (ss_ofst + 7), + dbg->num_qry_ht_pkt[ss_ofst + 0], dbg->num_qry_ht_pkt[ss_ofst + 1], + dbg->num_qry_ht_pkt[ss_ofst + 2], dbg->num_qry_ht_pkt[ss_ofst + 3], + dbg->num_qry_ht_pkt[ss_ofst + 4], dbg->num_qry_ht_pkt[ss_ofst + 5], + dbg->num_qry_ht_pkt[ss_ofst + 6], dbg->num_qry_ht_pkt[ss_ofst + 7]); + RT_PRINT(buf); + } - value32 = odm_get_bb_reg(p_dm_odm, 0xf34, MASKDWORD); /*VHT SIG*/ - { - v_length = (u16)(value32 & 0x1fffff); - vbrsv = (u8)((value32 & 0x600000) >> 20); - vb_tail = (u16)((value32 & 0x1f800000) >> 20); - vbcrc = (u8)((value32 & 0x80000000) >> 28); + if (dbg->low_bw_20_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = (i << 3); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}", + (ss_ofst), (ss_ofst + 7), + dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1], + dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3], + dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5], + dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7]); + RT_PRINT(buf); + } + } + } - } - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s", "VHT-SIG-B")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %x / %x / %x / %x", "length/Rsv/tail/CRC", v_length, vbrsv, vb_tail, vbcrc)); + #if ODM_IC_11AC_SERIES_SUPPORT + /*@======VHT=================================================*/ + if (dbg->vht_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}", + (i + 1), + dbg->num_qry_vht_pkt[ss_ofst + 0], dbg->num_qry_vht_pkt[ss_ofst + 1], + dbg->num_qry_vht_pkt[ss_ofst + 2], dbg->num_qry_vht_pkt[ss_ofst + 3], + dbg->num_qry_vht_pkt[ss_ofst + 4], dbg->num_qry_vht_pkt[ss_ofst + 5], + dbg->num_qry_vht_pkt[ss_ofst + 6], dbg->num_qry_vht_pkt[ss_ofst + 7], + dbg->num_qry_vht_pkt[ss_ofst + 8], dbg->num_qry_vht_pkt[ss_ofst + 9]); + RT_PRINT(buf); + } - /*for Condition number*/ - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { - s32 condition_num = 0; - char *factor = NULL; + if (dbg->low_bw_20_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n *[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}", + (i + 1), + dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1], + dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3], + dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5], + dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7], + dbg->num_qry_pkt_sc_20m[ss_ofst + 8], dbg->num_qry_pkt_sc_20m[ss_ofst + 9]); + RT_PRINT(buf); + } + } - odm_set_bb_reg(p_dm_odm, 0x1988, BIT(22), 0x1); /*enable report condition number*/ + if (dbg->low_bw_40_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n *[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}", + (i + 1), + dbg->num_qry_pkt_sc_40m[ss_ofst + 0], dbg->num_qry_pkt_sc_40m[ss_ofst + 1], + dbg->num_qry_pkt_sc_40m[ss_ofst + 2], dbg->num_qry_pkt_sc_40m[ss_ofst + 3], + dbg->num_qry_pkt_sc_40m[ss_ofst + 4], dbg->num_qry_pkt_sc_40m[ss_ofst + 5], + dbg->num_qry_pkt_sc_40m[ss_ofst + 6], dbg->num_qry_pkt_sc_40m[ss_ofst + 7], + dbg->num_qry_pkt_sc_40m[ss_ofst + 8], dbg->num_qry_pkt_sc_40m[ss_ofst + 9]); + RT_PRINT(buf); + } + } + } + #endif - condition_num = odm_get_bb_reg(p_dm_odm, 0xf84, MASKDWORD); - condition_num = (condition_num & 0x3ffff) >> 4; + phydm_reset_rx_rate_distribution(dm); - if (*p_dm_odm->p_band_width == ODM_BW80M) - factor = "256/234"; - else if (*p_dm_odm->p_band_width == ODM_BW40M) - factor = "128/108"; - else if (*p_dm_odm->p_band_width == ODM_BW20M) { - if (RX_HT != 2 || RX_HT != 1) - factor = "64/52"; /*HT or VHT*/ - else - factor = "64/48"; /*legacy*/ + //1 Show phydm_avg_phystatus_val + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [Avg PHY Statistic] ==============>"); + RT_PRINT(buf); + + phydm_reset_phystatus_avg(dm); + + /*@CCK*/ + dbg_avg->rssi_cck_avg = (u8)((dbg_s->rssi_cck_cnt != 0) ? (dbg_s->rssi_cck_sum / dbg_s->rssi_cck_cnt) : 0); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * cck Cnt= ((%d)) RSSI:{%d}", + dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg); + RT_PRINT(buf); + + /*OFDM*/ + if (dbg_s->rssi_ofdm_cnt != 0) { + dbg_avg->rssi_ofdm_avg = (u8)(dbg_s->rssi_ofdm_sum / dbg_s->rssi_ofdm_cnt); + dbg_avg->evm_ofdm_avg = (u8)(dbg_s->evm_ofdm_sum / dbg_s->rssi_ofdm_cnt); + dbg_avg->snr_ofdm_avg = (u8)(dbg_s->snr_ofdm_sum / dbg_s->rssi_ofdm_cnt); + } + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * ofdm Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}", + dbg_s->rssi_ofdm_cnt, dbg_avg->rssi_ofdm_avg, + dbg_avg->evm_ofdm_avg, dbg_avg->snr_ofdm_avg); + RT_PRINT(buf); + + if (dbg_s->rssi_1ss_cnt != 0) { + dbg_avg->rssi_1ss_avg = (u8)(dbg_s->rssi_1ss_sum / dbg_s->rssi_1ss_cnt); + dbg_avg->evm_1ss_avg = (u8)(dbg_s->evm_1ss_sum / dbg_s->rssi_1ss_cnt); + dbg_avg->snr_1ss_avg = (u8)(dbg_s->snr_1ss_sum / dbg_s->rssi_1ss_cnt); + } + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * 1-ss Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}", + dbg_s->rssi_1ss_cnt, dbg_avg->rssi_1ss_avg, + dbg_avg->evm_1ss_avg, dbg_avg->snr_1ss_avg); + RT_PRINT(buf); + +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) { + if (dbg_s->rssi_2ss_cnt != 0) { + dbg_avg->rssi_2ss_avg[0] = (u8)(dbg_s->rssi_2ss_sum[0] / dbg_s->rssi_2ss_cnt); + dbg_avg->rssi_2ss_avg[1] = (u8)(dbg_s->rssi_2ss_sum[1] / dbg_s->rssi_2ss_cnt); + + dbg_avg->evm_2ss_avg[0] = (u8)(dbg_s->evm_2ss_sum[0] / dbg_s->rssi_2ss_cnt); + dbg_avg->evm_2ss_avg[1] = (u8)(dbg_s->evm_2ss_sum[1] / dbg_s->rssi_2ss_cnt); + + dbg_avg->snr_2ss_avg[0] = (u8)(dbg_s->snr_2ss_sum[0] / dbg_s->rssi_2ss_cnt); + dbg_avg->snr_2ss_avg[1] = (u8)(dbg_s->snr_2ss_sum[1] / dbg_s->rssi_2ss_cnt); + } + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * 2-ss Cnt= ((%d)) RSSI:{%d, %d}, EVM:{%d, %d}, SNR:{%d, %d}", + dbg_s->rssi_2ss_cnt, dbg_avg->rssi_2ss_avg[0], + dbg_avg->rssi_2ss_avg[1], dbg_avg->evm_2ss_avg[0], + dbg_avg->evm_2ss_avg[1], dbg_avg->snr_2ss_avg[0], + dbg_avg->snr_2ss_avg[1]); + RT_PRINT(buf); + } +#endif + +#if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) { + if (dbg_s->rssi_3ss_cnt != 0) { + dbg_avg->rssi_3ss_avg[0] = (u8)(dbg_s->rssi_3ss_sum[0] / dbg_s->rssi_3ss_cnt); + dbg_avg->rssi_3ss_avg[1] = (u8)(dbg_s->rssi_3ss_sum[1] / dbg_s->rssi_3ss_cnt); + dbg_avg->rssi_3ss_avg[2] = (u8)(dbg_s->rssi_3ss_sum[2] / dbg_s->rssi_3ss_cnt); + + dbg_avg->evm_3ss_avg[0] = (u8)(dbg_s->evm_3ss_sum[0] / dbg_s->rssi_3ss_cnt); + dbg_avg->evm_3ss_avg[1] = (u8)(dbg_s->evm_3ss_sum[1] / dbg_s->rssi_3ss_cnt); + dbg_avg->evm_3ss_avg[2] = (u8)(dbg_s->evm_3ss_sum[2] / dbg_s->rssi_3ss_cnt); + + dbg_avg->snr_3ss_avg[0] = (u8)(dbg_s->snr_3ss_sum[0] / dbg_s->rssi_3ss_cnt); + dbg_avg->snr_3ss_avg[1] = (u8)(dbg_s->snr_3ss_sum[1] / dbg_s->rssi_3ss_cnt); + dbg_avg->snr_3ss_avg[2] = (u8)(dbg_s->snr_3ss_sum[2] / dbg_s->rssi_3ss_cnt); + } + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * 3-ss Cnt= ((%d)) RSSI:{%d, %d, %d} EVM:{%d, %d, %d} SNR:{%d, %d, %d}", + dbg_s->rssi_3ss_cnt, dbg_avg->rssi_3ss_avg[0], + dbg_avg->rssi_3ss_avg[1], dbg_avg->rssi_3ss_avg[2], + dbg_avg->evm_3ss_avg[0], dbg_avg->evm_3ss_avg[1], + dbg_avg->evm_3ss_avg[2], dbg_avg->snr_3ss_avg[0], + dbg_avg->snr_3ss_avg[1], dbg_avg->snr_3ss_avg[2]); + RT_PRINT(buf); + } +#endif + +#if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + if (dbg_s->rssi_4ss_cnt != 0) { + dbg_avg->rssi_4ss_avg[0] = (u8)(dbg_s->rssi_4ss_sum[0] / dbg_s->rssi_4ss_cnt); + dbg_avg->rssi_4ss_avg[1] = (u8)(dbg_s->rssi_4ss_sum[1] / dbg_s->rssi_4ss_cnt); + dbg_avg->rssi_4ss_avg[2] = (u8)(dbg_s->rssi_4ss_sum[2] / dbg_s->rssi_4ss_cnt); + dbg_avg->rssi_4ss_avg[3] = (u8)(dbg_s->rssi_4ss_sum[3] / dbg_s->rssi_4ss_cnt); + + dbg_avg->evm_4ss_avg[0] = (u8)(dbg_s->evm_4ss_sum[0] / dbg_s->rssi_4ss_cnt); + dbg_avg->evm_4ss_avg[1] = (u8)(dbg_s->evm_4ss_sum[1] / dbg_s->rssi_4ss_cnt); + dbg_avg->evm_4ss_avg[2] = (u8)(dbg_s->evm_4ss_sum[2] / dbg_s->rssi_4ss_cnt); + dbg_avg->evm_4ss_avg[3] = (u8)(dbg_s->evm_4ss_sum[3] / dbg_s->rssi_4ss_cnt); + + dbg_avg->snr_4ss_avg[0] = (u8)(dbg_s->snr_4ss_sum[0] / dbg_s->rssi_4ss_cnt); + dbg_avg->snr_4ss_avg[1] = (u8)(dbg_s->snr_4ss_sum[1] / dbg_s->rssi_4ss_cnt); + dbg_avg->snr_4ss_avg[2] = (u8)(dbg_s->snr_4ss_sum[2] / dbg_s->rssi_4ss_cnt); + dbg_avg->snr_4ss_avg[3] = (u8)(dbg_s->snr_4ss_sum[3] / dbg_s->rssi_4ss_cnt); + } + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * 4-ss Cnt= ((%d)) RSSI:{%d, %d, %d, %d} EVM:{%d, %d, %d, %d} SNR:{%d, %d, %d, %d}", + dbg_s->rssi_4ss_cnt, dbg_avg->rssi_4ss_avg[0], + dbg_avg->rssi_4ss_avg[1], dbg_avg->rssi_4ss_avg[2], + dbg_avg->rssi_4ss_avg[3], dbg_avg->evm_4ss_avg[0], + dbg_avg->evm_4ss_avg[1], dbg_avg->evm_4ss_avg[2], + dbg_avg->evm_4ss_avg[3], dbg_avg->snr_4ss_avg[0], + dbg_avg->snr_4ss_avg[1], dbg_avg->snr_4ss_avg[2], + dbg_avg->snr_4ss_avg[3]); + RT_PRINT(buf); + } +#endif + phydm_reset_phystatus_statistic(dm); + /*@----------------------------------------------------------*/ + + /*Print TX rate*/ + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + entry = dm->phydm_sta_info[macid]; + + if (!is_sta_active(entry)) + continue; + + phydm_macid = (dm->phydm_macid_table[macid]); + phydm_print_rate_2_buff(dm, entry->ra_info.curr_tx_rate, dbg_buf, PHYDM_SNPRINT_SIZE); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n TxRate[%d]=%s (0x%x)", macid, dbg_buf, entry->ra_info.curr_tx_rate); + RT_PRINT(buf); + + client_cnt++; + + if (client_cnt >= dm->number_linked_client) + break; + } + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))", + dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load); + RT_PRINT(buf); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n CFO_avg=((%d kHz)), CFO_traking = ((%s%d))", + cfo_t->CFO_ave_pre, + ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"), + DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap)); + RT_PRINT(buf); + + /* @Condition number */ + #if (RTL8822B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822B) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Condi_Num=((%d.%.4d))", + dm->phy_dbg_info.condi_num >> 4, + phydm_show_fraction_num(dm->phy_dbg_info.condi_num & 0xf, 4)); + RT_PRINT(buf); } + #endif - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = %d (factor = %s)", "Condition number", condition_num, factor)); + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) + /*STBC or LDPC pkt*/ + if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Coding: LDPC=((%s)), STBC=((%s))", + (dm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N", + (dm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N"); + RT_PRINT(buf); + #endif + } else { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n No Link !!!"); + RT_PRINT(buf); } + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}", + fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all); + RT_PRINT(buf); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}", + fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all); + RT_PRINT(buf); + + #if (ODM_IC_11N_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n [OFDM FA Detail] Parity_Fail=%d, Rate_Illegal=%d, CRC8=%d, MCS_fail=%d, Fast_sync=%d, SB_Search_fail=%d", + fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal, + fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail, + fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail); + RT_PRINT(buf); + } + #endif + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d", + dm->is_linked, dm->number_linked_client, dm->rssi_min, + dm->dm_dig_table.cur_ig_value, dm->noisy_decision); + RT_PRINT(buf); } -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#if CONFIG_PHYDM_DEBUG_FUNCTION +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION void phydm_sbd_check( - struct PHY_DM_STRUCT *p_dm_odm -) + struct dm_struct *dm) { - static u32 pkt_cnt = 0; - static boolean sbd_state = 0; - u32 sym_count, count, value32; + static u32 pkt_cnt; + static boolean sbd_state; + u32 sym_count, count, value32; if (sbd_state == 0) { pkt_cnt++; - if (pkt_cnt % 5 == 0) { /*read SBD conter once every 5 packets*/ - odm_set_timer(p_dm_odm, &p_dm_odm->sbdcnt_timer, 0); /*ms*/ + /*read SBD conter once every 5 packets*/ + if (pkt_cnt % 5 == 0) { + odm_set_timer(dm, &dm->sbdcnt_timer, 0); /*@ms*/ sbd_state = 1; } } else { /*read counter*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xF98, MASKDWORD); + value32 = odm_get_bb_reg(dm, R_0xf98, MASKDWORD); sym_count = (value32 & 0x7C000000) >> 26; count = (value32 & 0x3F00000) >> 20; - dbg_print("#SBD# sym_count %d count %d\n", sym_count, count); + pr_debug("#SBD# sym_count %d count %d\n", sym_count, count); sbd_state = 0; } } -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +#endif void phydm_sbd_callback( - struct timer_list *p_timer -) + struct phydm_timer_list *timer) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + void *adapter = timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + struct dm_struct *dm = &hal_data->DM_OutSrc; #if USE_WORKITEM - odm_schedule_work_item(&p_dm_odm->sbdcnt_workitem); + odm_schedule_work_item(&dm->sbdcnt_workitem); #else - phydm_sbd_check(p_dm_odm); + phydm_sbd_check(dm); +#endif #endif -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ } void phydm_sbd_workitem_callback( - void *p_context -) + void *context) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + struct dm_struct *dm = &hal_data->DM_OutSrc; - phydm_sbd_check(p_dm_odm); -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ + phydm_sbd_check(dm); +#endif } #endif -void -phydm_basic_dbg_message -( - void *p_dm_void -) + +void phydm_reset_rx_rate_distribution(struct dm_struct *dm) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u16 macid, phydm_macid, client_cnt = 0; - struct sta_info *p_entry; - s32 tmp_val = 0; - u8 tmp_val_u1 = 0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[PHYDM Common MSG] System up time: ((%d sec))----->\n", p_dm_odm->phydm_sys_up_time)); - - if (p_dm_odm->is_linked) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ID=%d, BW=((%d)), CH=((%d))\n", p_dm_odm->curr_station_id, 20<<(*(p_dm_odm->p_band_width)), *(p_dm_odm->p_channel))); - - /*Print RX rate*/ - if (p_dm_odm->rx_rate <= ODM_RATE11M) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCK AGC Report] LNA_idx = 0x%x, VGA_idx = 0x%x\n", - p_dm_odm->cck_lna_idx, p_dm_odm->cck_vga_idx)); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM AGC Report] { 0x%x, 0x%x, 0x%x, 0x%x }\n", - p_dm_odm->ofdm_agc_idx[0], p_dm_odm->ofdm_agc_idx[1], p_dm_odm->ofdm_agc_idx[2], p_dm_odm->ofdm_agc_idx[3])); + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + + odm_memory_set(dm, &dbg->num_qry_legacy_pkt[0], 0, + (LEGACY_RATE_NUM * 2)); + odm_memory_set(dm, &dbg->num_qry_ht_pkt[0], 0, + (HT_RATE_NUM * 2)); + odm_memory_set(dm, &dbg->num_qry_pkt_sc_20m[0], 0, + (LOW_BW_RATE_NUM * 2)); + + dbg->ht_pkt_not_zero = false; + dbg->low_bw_20_occur = false; + +#if ODM_IC_11AC_SERIES_SUPPORT + odm_memory_set(dm, &dbg->num_qry_vht_pkt[0], 0, VHT_RATE_NUM * 2); + odm_memory_set(dm, &dbg->num_qry_pkt_sc_40m[0], 0, LOW_BW_RATE_NUM * 2); + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) + odm_memory_set(dm, &dbg->num_mu_vht_pkt[0], 0, VHT_RATE_NUM * 2); + #endif + dbg->vht_pkt_not_zero = false; + dbg->low_bw_40_occur = false; +#endif +} + +void phydm_rx_rate_distribution(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + u8 i = 0; + u8 rate_num = dm->num_rf_path, ss_ofst = 0; + + PHYDM_DBG(dm, DBG_CMN, "[RxRate Cnt] =============>\n"); + + /*@======CCK=========================================================*/ + if (*dm->channel <= 14) { + PHYDM_DBG(dm, DBG_CMN, "* CCK = {%d, %d, %d, %d}\n", + dbg->num_qry_legacy_pkt[0], + dbg->num_qry_legacy_pkt[1], + dbg->num_qry_legacy_pkt[2], + dbg->num_qry_legacy_pkt[3]); + } + /*@======OFDM========================================================*/ + PHYDM_DBG(dm, DBG_CMN, "* OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5], + dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7], + dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9], + dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]); + + /*@======HT==========================================================*/ + if (dbg->ht_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = (i << 3); + + PHYDM_DBG(dm, DBG_CMN, + "* HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_ofst), (ss_ofst + 7), + dbg->num_qry_ht_pkt[ss_ofst + 0], + dbg->num_qry_ht_pkt[ss_ofst + 1], + dbg->num_qry_ht_pkt[ss_ofst + 2], + dbg->num_qry_ht_pkt[ss_ofst + 3], + dbg->num_qry_ht_pkt[ss_ofst + 4], + dbg->num_qry_ht_pkt[ss_ofst + 5], + dbg->num_qry_ht_pkt[ss_ofst + 6], + dbg->num_qry_ht_pkt[ss_ofst + 7]); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI: { %d, %d, %d, %d }, rx_rate:", - (p_dm_odm->RSSI_A == 0xff) ? 0 : p_dm_odm->RSSI_A, - (p_dm_odm->RSSI_B == 0xff) ? 0 : p_dm_odm->RSSI_B, - (p_dm_odm->RSSI_C == 0xff) ? 0 : p_dm_odm->RSSI_C, - (p_dm_odm->RSSI_D == 0xff) ? 0 : p_dm_odm->RSSI_D)); - - phydm_print_rate(p_dm_odm, p_dm_odm->rx_rate, ODM_COMP_COMMON); + if (dbg->low_bw_20_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = (i << 3); + + PHYDM_DBG(dm, DBG_CMN, + "* [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_ofst), (ss_ofst + 7), + dbg->num_qry_pkt_sc_20m[ss_ofst + 0], + dbg->num_qry_pkt_sc_20m[ss_ofst + 1], + dbg->num_qry_pkt_sc_20m[ss_ofst + 2], + dbg->num_qry_pkt_sc_20m[ss_ofst + 3], + dbg->num_qry_pkt_sc_20m[ss_ofst + 4], + dbg->num_qry_pkt_sc_20m[ss_ofst + 5], + dbg->num_qry_pkt_sc_20m[ss_ofst + 6], + dbg->num_qry_pkt_sc_20m[ss_ofst + 7]); + } + } + } - /*Print TX rate*/ - for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { +#if ODM_IC_11AC_SERIES_SUPPORT + /*@======VHT==========================================================*/ + if (dbg->vht_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + PHYDM_DBG(dm, DBG_CMN, + "* VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + dbg->num_qry_vht_pkt[ss_ofst + 0], + dbg->num_qry_vht_pkt[ss_ofst + 1], + dbg->num_qry_vht_pkt[ss_ofst + 2], + dbg->num_qry_vht_pkt[ss_ofst + 3], + dbg->num_qry_vht_pkt[ss_ofst + 4], + dbg->num_qry_vht_pkt[ss_ofst + 5], + dbg->num_qry_vht_pkt[ss_ofst + 6], + dbg->num_qry_vht_pkt[ss_ofst + 7], + dbg->num_qry_vht_pkt[ss_ofst + 8], + dbg->num_qry_vht_pkt[ss_ofst + 9]); + } - p_entry = p_dm_odm->p_odm_sta_info[macid]; - if (IS_STA_VALID(p_entry)) { + if (dbg->low_bw_20_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + PHYDM_DBG(dm, DBG_CMN, + "*[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + dbg->num_qry_pkt_sc_20m[ss_ofst + 0], + dbg->num_qry_pkt_sc_20m[ss_ofst + 1], + dbg->num_qry_pkt_sc_20m[ss_ofst + 2], + dbg->num_qry_pkt_sc_20m[ss_ofst + 3], + dbg->num_qry_pkt_sc_20m[ss_ofst + 4], + dbg->num_qry_pkt_sc_20m[ss_ofst + 5], + dbg->num_qry_pkt_sc_20m[ss_ofst + 6], + dbg->num_qry_pkt_sc_20m[ss_ofst + 7], + dbg->num_qry_pkt_sc_20m[ss_ofst + 8], + dbg->num_qry_pkt_sc_20m[ss_ofst + 9]); + } + } - phydm_macid = (p_dm_odm->platform2phydm_macid_table[macid]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TXRate [%d]:", macid)); - phydm_print_rate(p_dm_odm, p_ra_table->link_tx_rate[macid], ODM_COMP_COMMON); + if (dbg->low_bw_40_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + PHYDM_DBG(dm, DBG_CMN, + "*[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + dbg->num_qry_pkt_sc_40m[ss_ofst + 0], + dbg->num_qry_pkt_sc_40m[ss_ofst + 1], + dbg->num_qry_pkt_sc_40m[ss_ofst + 2], + dbg->num_qry_pkt_sc_40m[ss_ofst + 3], + dbg->num_qry_pkt_sc_40m[ss_ofst + 4], + dbg->num_qry_pkt_sc_40m[ss_ofst + 5], + dbg->num_qry_pkt_sc_40m[ss_ofst + 6], + dbg->num_qry_pkt_sc_40m[ss_ofst + 7], + dbg->num_qry_pkt_sc_40m[ss_ofst + 8], + dbg->num_qry_pkt_sc_40m[ss_ofst + 9]); + } + } + } +#endif +} - client_cnt++; +void phydm_print_hist_2_buf(void *dm_void, u16 *val, u16 len, char *buf, + u16 buf_size) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (len == PHY_HIST_SIZE) { + PHYDM_SNPRINTF(buf, buf_size, + "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]", + val[0], val[1], val[2], val[3], val[4], + val[5], val[6], val[7], val[8], val[9], + val[10], val[11]); + } else if (len == (PHY_HIST_SIZE - 1)) { + PHYDM_SNPRINTF(buf, buf_size, + "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]", + val[0], val[1], val[2], val[3], val[4], + val[5], val[6], val[7], val[8], val[9], + val[10]); + } +} - if (client_cnt == p_dm_odm->number_linked_client) - break; - } +void phydm_nss_hitogram(void *dm_void, enum PDM_RATE_TYPE rate_type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + char buf[PHYDM_SNPRINT_SIZE] = {0}; + u16 buf_size = PHYDM_SNPRINT_SIZE; + u16 h_size = PHY_HIST_SIZE; + u16 *evm_hist = NULL, *snr_hist = NULL; + u8 i = 0; + u8 ss = phydm_rate_type_2_num_ss(dm, rate_type); + + for (i = 0; i < ss; i++) { + if (rate_type == PDM_1SS) { + evm_hist = &dbg_s->evm_1ss_hist[0]; + snr_hist = &dbg_s->snr_1ss_hist[0]; + } else if (rate_type == PDM_2SS) { + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + evm_hist = &dbg_s->evm_2ss_hist[i][0]; + snr_hist = &dbg_s->snr_2ss_hist[i][0]; + #endif + } else if (rate_type == PDM_3SS) { + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + evm_hist = &dbg_s->evm_3ss_hist[i][0]; + snr_hist = &dbg_s->snr_3ss_hist[i][0]; + #endif + } else if (rate_type == PDM_4SS) { + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + evm_hist = &dbg_s->evm_4ss_hist[i][0]; + snr_hist = &dbg_s->snr_4ss_hist[i][0]; + #endif } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TP { TX, RX, total} = {%d, %d, %d }Mbps, traffic_load = (%d))\n", - p_dm_odm->tx_tp, p_dm_odm->rx_tp, p_dm_odm->total_tp, p_dm_odm->traffic_load)); + phydm_print_hist_2_buf(dm, evm_hist, h_size, buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "[%d-SS][EVM][%d]=%s\n", ss, i, buf); + phydm_print_hist_2_buf(dm, snr_hist, h_size, buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "[%d-SS][SNR][%d]=%s\n", ss, i, buf); + } +} + +void phydm_show_phy_hitogram(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + char buf[PHYDM_SNPRINT_SIZE] = {0}; + u16 buf_size = PHYDM_SNPRINT_SIZE; + u16 th_size = PHY_HIST_SIZE - 1; + u8 i = 0; + + PHYDM_DBG(dm, DBG_CMN, "[PHY Histogram] ==============>\n"); +/*@===[Threshold]=============================================================*/ + phydm_print_hist_2_buf(dm, dbg_i->evm_hist_th, th_size, buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "%-16s=%s\n", "[EVM_TH]", buf); + + phydm_print_hist_2_buf(dm, dbg_i->snr_hist_th, th_size, buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "%-16s=%s\n", "[SNR_TH]", buf); +/*@===[OFDM]==================================================================*/ + if (dbg_s->rssi_ofdm_cnt) { + phydm_print_hist_2_buf(dm, dbg_s->evm_ofdm_hist, PHY_HIST_SIZE, + buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "%-14s=%s\n", "[OFDM][EVM]", buf); + + phydm_print_hist_2_buf(dm, dbg_s->snr_ofdm_hist, PHY_HIST_SIZE, + buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "%-14s=%s\n", "[OFDM][SNR]", buf); + } +/*@===[1-SS]==================================================================*/ + if (dbg_s->rssi_1ss_cnt) + phydm_nss_hitogram(dm, PDM_1SS); +/*@===[2-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if ((dm->support_ic_type & PHYDM_IC_ABOVE_2SS) && dbg_s->rssi_2ss_cnt) + phydm_nss_hitogram(dm, PDM_2SS); + #endif +/*@===[3-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if ((dm->support_ic_type & PHYDM_IC_ABOVE_3SS) && dbg_s->rssi_3ss_cnt) + phydm_nss_hitogram(dm, PDM_3SS); + #endif +/*@===[4-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS && dbg_s->rssi_4ss_cnt) + phydm_nss_hitogram(dm, PDM_4SS); + #endif +} + +void phydm_get_avg_phystatus_val(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + struct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg; + + PHYDM_DBG(dm, DBG_CMN, "[PHY Avg] ==============>\n"); + phydm_reset_phystatus_avg(dm); + +/*@===[CCK]===================================================================*/ + if (dbg_s->rssi_cck_cnt != 0) + dbg_avg->rssi_cck_avg = (u8)(dbg_s->rssi_cck_sum / + dbg_s->rssi_cck_cnt); + else + dbg_avg->rssi_cck_avg = 0; + + PHYDM_DBG(dm, DBG_CMN, "* cck Cnt= ((%d)) RSSI:{%d}\n", + dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg); + +/*@===[OFDM]==================================================================*/ + if (dbg_s->rssi_ofdm_cnt != 0) { + dbg_avg->rssi_ofdm_avg = (u8)(dbg_s->rssi_ofdm_sum / + dbg_s->rssi_ofdm_cnt); + dbg_avg->evm_ofdm_avg = (u8)(dbg_s->evm_ofdm_sum / + dbg_s->rssi_ofdm_cnt); + dbg_avg->snr_ofdm_avg = (u8)(dbg_s->snr_ofdm_sum / + dbg_s->rssi_ofdm_cnt); + } + + PHYDM_DBG(dm, DBG_CMN, + "* ofdm Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}\n", + dbg_s->rssi_ofdm_cnt, dbg_avg->rssi_ofdm_avg, + dbg_avg->evm_ofdm_avg, dbg_avg->snr_ofdm_avg); +/*@===[1-SS]==================================================================*/ + if (dbg_s->rssi_1ss_cnt != 0) { + dbg_avg->rssi_1ss_avg = (u8)(dbg_s->rssi_1ss_sum / + dbg_s->rssi_1ss_cnt); + dbg_avg->evm_1ss_avg = (u8)(dbg_s->evm_1ss_sum / + dbg_s->rssi_1ss_cnt); + dbg_avg->snr_1ss_avg = (u8)(dbg_s->snr_1ss_sum / + dbg_s->rssi_1ss_cnt); + } + + PHYDM_DBG(dm, DBG_CMN, + "* 1-ss Cnt= ((%d)) RSSI:{%d} EVM:{%d} SNR:{%d}\n", + dbg_s->rssi_1ss_cnt, dbg_avg->rssi_1ss_avg, + dbg_avg->evm_1ss_avg, dbg_avg->snr_1ss_avg); + +/*@===[2-SS]==================================================================*/ +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) { + if (dbg_s->rssi_2ss_cnt != 0) { + dbg_avg->rssi_2ss_avg[0] = (u8)(dbg_s->rssi_2ss_sum[0] / + dbg_s->rssi_2ss_cnt); + dbg_avg->rssi_2ss_avg[1] = (u8)(dbg_s->rssi_2ss_sum[1] / + dbg_s->rssi_2ss_cnt); + + dbg_avg->evm_2ss_avg[0] = (u8)(dbg_s->evm_2ss_sum[0] / + dbg_s->rssi_2ss_cnt); + dbg_avg->evm_2ss_avg[1] = (u8)(dbg_s->evm_2ss_sum[1] / + dbg_s->rssi_2ss_cnt); + + dbg_avg->snr_2ss_avg[0] = (u8)(dbg_s->snr_2ss_sum[0] / + dbg_s->rssi_2ss_cnt); + dbg_avg->snr_2ss_avg[1] = (u8)(dbg_s->snr_2ss_sum[1] / + dbg_s->rssi_2ss_cnt); + } - tmp_val_u1 = (p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) ? (p_cfo_track->crystal_cap - p_cfo_track->def_x_cap) : (p_cfo_track->def_x_cap - p_cfo_track->crystal_cap); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CFO_avg = ((%d kHz)) , CrystalCap_tracking = ((%s%d))\n", - p_cfo_track->CFO_ave_pre, ((p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) ? "+" : "-"), tmp_val_u1)); + PHYDM_DBG(dm, DBG_CMN, + "* 2-ss Cnt= ((%d)) RSSI:{%d, %d}, EVM:{%d, %d}, SNR:{%d, %d}\n", + dbg_s->rssi_2ss_cnt, dbg_avg->rssi_2ss_avg[0], + dbg_avg->rssi_2ss_avg[1], dbg_avg->evm_2ss_avg[0], + dbg_avg->evm_2ss_avg[1], dbg_avg->snr_2ss_avg[0], + dbg_avg->snr_2ss_avg[1]); + } +#endif - /* Condition number */ -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - tmp_val = phydm_get_condition_number_8822B(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Condition number = ((%d))\n", tmp_val)); +/*@===[3-SS]==================================================================*/ +#if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) { + if (dbg_s->rssi_3ss_cnt != 0) { + dbg_avg->rssi_3ss_avg[0] = (u8)(dbg_s->rssi_3ss_sum[0] / + dbg_s->rssi_3ss_cnt); + dbg_avg->rssi_3ss_avg[1] = (u8)(dbg_s->rssi_3ss_sum[1] / + dbg_s->rssi_3ss_cnt); + dbg_avg->rssi_3ss_avg[2] = (u8)(dbg_s->rssi_3ss_sum[2] / + dbg_s->rssi_3ss_cnt); + + dbg_avg->evm_3ss_avg[0] = (u8)(dbg_s->evm_3ss_sum[0] / + dbg_s->rssi_3ss_cnt); + dbg_avg->evm_3ss_avg[1] = (u8)(dbg_s->evm_3ss_sum[1] / + dbg_s->rssi_3ss_cnt); + dbg_avg->evm_3ss_avg[2] = (u8)(dbg_s->evm_3ss_sum[2] / + dbg_s->rssi_3ss_cnt); + + dbg_avg->snr_3ss_avg[0] = (u8)(dbg_s->snr_3ss_sum[0] / + dbg_s->rssi_3ss_cnt); + dbg_avg->snr_3ss_avg[1] = (u8)(dbg_s->snr_3ss_sum[1] / + dbg_s->rssi_3ss_cnt); + dbg_avg->snr_3ss_avg[2] = (u8)(dbg_s->snr_3ss_sum[2] / + dbg_s->rssi_3ss_cnt); } + + PHYDM_DBG(dm, DBG_CMN, + "* 3-ss Cnt= ((%d)) RSSI:{%d, %d, %d} EVM:{%d, %d, %d} SNR:{%d, %d, %d}\n", + dbg_s->rssi_3ss_cnt, dbg_avg->rssi_3ss_avg[0], + dbg_avg->rssi_3ss_avg[1], dbg_avg->rssi_3ss_avg[2], + dbg_avg->evm_3ss_avg[0], dbg_avg->evm_3ss_avg[1], + dbg_avg->evm_3ss_avg[2], dbg_avg->snr_3ss_avg[0], + dbg_avg->snr_3ss_avg[1], dbg_avg->snr_3ss_avg[2]); + } #endif -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - /*STBC or LDPC pkt*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("LDPC = %s, STBC = %s\n", (p_dm_odm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N", (p_dm_odm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N")); +/*@===[4-SS]==================================================================*/ +#if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + if (dbg_s->rssi_4ss_cnt != 0) { + dbg_avg->rssi_4ss_avg[0] = (u8)(dbg_s->rssi_4ss_sum[0] / + dbg_s->rssi_4ss_cnt); + dbg_avg->rssi_4ss_avg[1] = (u8)(dbg_s->rssi_4ss_sum[1] / + dbg_s->rssi_4ss_cnt); + dbg_avg->rssi_4ss_avg[2] = (u8)(dbg_s->rssi_4ss_sum[2] / + dbg_s->rssi_4ss_cnt); + dbg_avg->rssi_4ss_avg[3] = (u8)(dbg_s->rssi_4ss_sum[3] / + dbg_s->rssi_4ss_cnt); + + dbg_avg->evm_4ss_avg[0] = (u8)(dbg_s->evm_4ss_sum[0] / + dbg_s->rssi_4ss_cnt); + dbg_avg->evm_4ss_avg[1] = (u8)(dbg_s->evm_4ss_sum[1] / + dbg_s->rssi_4ss_cnt); + dbg_avg->evm_4ss_avg[2] = (u8)(dbg_s->evm_4ss_sum[2] / + dbg_s->rssi_4ss_cnt); + dbg_avg->evm_4ss_avg[3] = (u8)(dbg_s->evm_4ss_sum[3] / + dbg_s->rssi_4ss_cnt); + + dbg_avg->snr_4ss_avg[0] = (u8)(dbg_s->snr_4ss_sum[0] / + dbg_s->rssi_4ss_cnt); + dbg_avg->snr_4ss_avg[1] = (u8)(dbg_s->snr_4ss_sum[1] / + dbg_s->rssi_4ss_cnt); + dbg_avg->snr_4ss_avg[2] = (u8)(dbg_s->snr_4ss_sum[2] / + dbg_s->rssi_4ss_cnt); + dbg_avg->snr_4ss_avg[3] = (u8)(dbg_s->snr_4ss_sum[3] / + dbg_s->rssi_4ss_cnt); + } + + PHYDM_DBG(dm, DBG_CMN, + "* 4-ss Cnt= ((%d)) RSSI:{%d, %d, %d, %d} EVM:{%d, %d, %d, %d} SNR:{%d, %d, %d, %d}\n", + dbg_s->rssi_4ss_cnt, dbg_avg->rssi_4ss_avg[0], + dbg_avg->rssi_4ss_avg[1], dbg_avg->rssi_4ss_avg[2], + dbg_avg->rssi_4ss_avg[3], dbg_avg->evm_4ss_avg[0], + dbg_avg->evm_4ss_avg[1], dbg_avg->evm_4ss_avg[2], + dbg_avg->evm_4ss_avg[3], dbg_avg->snr_4ss_avg[0], + dbg_avg->snr_4ss_avg[1], dbg_avg->snr_4ss_avg[2], + dbg_avg->snr_4ss_avg[3]); + } #endif - } else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("No Link !!!\n")); +} + +void phydm_get_phy_statistic(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_rx_rate_distribution(dm); + phydm_reset_rx_rate_distribution(dm); + + phydm_show_phy_hitogram(dm); + phydm_get_avg_phystatus_val(dm); + phydm_reset_phystatus_statistic(dm); +}; + +void phydm_basic_dbg_msg_linked(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track; + struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info; + u16 macid, phydm_macid, client_cnt = 0; + u8 rate = 0; + struct cmn_sta_info *entry = NULL; + char dbg_buf[PHYDM_SNPRINT_SIZE] = {0}; + struct phydm_cfo_rpt cfo; + u8 i = 0; + + PHYDM_DBG(dm, DBG_CMN, "ID=((%d)), BW=((%d)), fc=((CH-%d))\n", + dm->curr_station_id, 20 << *dm->band_width, *dm->channel); + + #ifdef ODM_IC_11N_SERIES_SUPPORT + #ifdef PHYDM_PRIMARY_CCA + if (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) && + (dm->support_ic_type & ODM_IC_11N_SERIES)) { + PHYDM_DBG(dm, DBG_CMN, "Primary CCA at ((%s SB))\n", + ((*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? "U" : + "L")); + } + #endif + #endif + + if ((dm->support_ic_type & PHYSTS_2ND_TYPE_IC) || + dm->rx_rate > ODM_RATE11M) { + PHYDM_DBG(dm, DBG_CMN, "[AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}\n", + dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1], + dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]); + } else { + PHYDM_DBG(dm, DBG_CMN, "[CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}\n", + dm->cck_lna_idx, dm->cck_vga_idx); + } + + phydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE); + PHYDM_DBG(dm, DBG_CMN, "RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)\n", + (dm->rssi_a == 0xff) ? 0 : dm->rssi_a, + (dm->rssi_b == 0xff) ? 0 : dm->rssi_b, + (dm->rssi_c == 0xff) ? 0 : dm->rssi_c, + (dm->rssi_d == 0xff) ? 0 : dm->rssi_d, + dbg_buf, dm->rx_rate); + + rate = dbg_t->beacon_phy_rate; + phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE); + + PHYDM_DBG(dm, DBG_CMN, "Beacon_cnt=%d, rate_idx=%s (0x%x)\n", + dbg_t->num_qry_beacon_pkt, + dbg_buf, + dbg_t->beacon_phy_rate); + + phydm_get_phy_statistic(dm); + + PHYDM_DBG(dm, DBG_CMN, + "rxsc_idx {Legacy, 20, 40, 80} = {%d, %d, %d, %d}\n", + dm->rxsc_l, dm->rxsc_20, dm->rxsc_40, dm->rxsc_80); + + /*Print TX rate*/ + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + entry = dm->phydm_sta_info[macid]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all)); + if (!is_sta_active(entry)) + continue; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all)); + phydm_macid = (dm->phydm_macid_table[macid]); + rate = entry->ra_info.curr_tx_rate; + phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE); + PHYDM_DBG(dm, DBG_CMN, "TxRate[%d]=%s (0x%x)\n", + macid, dbg_buf, entry->ra_info.curr_tx_rate); -#if (ODM_IC_11N_SERIES_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", - false_alm_cnt->cnt_parity_fail, false_alm_cnt->cnt_rate_illegal, false_alm_cnt->cnt_crc8_fail, false_alm_cnt->cnt_mcs_fail, false_alm_cnt->cnt_fast_fsync, false_alm_cnt->cnt_sb_search_fail)); + client_cnt++; + + if (client_cnt >= dm->number_linked_client) + break; + } + + PHYDM_DBG(dm, DBG_CMN, + "TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))\n", + dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load); + + PHYDM_DBG(dm, DBG_CMN, "CFO_avg=((%d kHz)), CFO_traking = ((%s%d))\n", + cfo_t->CFO_ave_pre, + ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"), + DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap)); + + phydm_get_cfo_info(dm, &cfo); + for (i = 0; i < dm->num_rf_path; i++) { + PHYDM_DBG(dm, DBG_CMN, + "CFO[%d] {S, L, Sec, Acq, End} = {%d, %d, %d, %d, %d}\n", + i, cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], + cfo.cfo_rpt_sec[i], cfo.cfo_rpt_acq[i], + cfo.cfo_rpt_end[i]); + } + +/* @Condition number */ +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822B) { + PHYDM_DBG(dm, DBG_CMN, "Condi_Num=((%d.%.4d)), %d\n", + dbg_t->condi_num >> 4, + phydm_show_fraction_num(dbg_t->condi_num & 0xf, 4), + dbg_t->condi_num); + } +#endif +#ifdef PHYSTS_3RD_TYPE_SUPPORT + if (dm->support_ic_type == ODM_RTL8198F) { + PHYDM_DBG(dm, DBG_CMN, "Condi_Num=((%d.%4d dB))\n", + dbg_t->condi_num >> 1, + phydm_show_fraction_num(dbg_t->condi_num & 0x1, 1)); } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("is_linked = %d, Num_client = %d, rssi_min = %d, current_igi = 0x%x, bNoisy=%d\n\n", - p_dm_odm->is_linked, p_dm_odm->number_linked_client, p_dm_odm->rssi_min, p_dm_dig_table->cur_ig_value, p_dm_odm->noisy_decision)); +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) + /*STBC or LDPC pkt*/ + if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) + PHYDM_DBG(dm, DBG_CMN, "Coding: LDPC=((%s)), STBC=((%s))\n", + (dbg_t->is_ldpc_pkt) ? "Y" : "N", + (dbg_t->is_stbc_pkt) ? "Y" : "N"); +#endif +} + +void phydm_dm_summary(void *dm_void, u8 macid) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; + struct dtp_info *dtp = NULL; + u64 comp = dm->support_ability; + u64 pause_comp = dm->pause_ability; + + if (!(dm->debug_components & DBG_DM_SUMMARY)) + return; + + if (!dm->is_linked) { + pr_debug("[%s]No Link !!!\n", __func__); + return; + } + + sta = dm->phydm_sta_info[macid]; - /* - temp_reg = odm_get_bb_reg(p_dm_odm, 0xDD0, MASKBYTE0); - ODM_RT_TRACE(p_dm_odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDD0 = 0x%x\n",temp_reg)); + if (!is_sta_active(sta)) { + pr_debug("[Warning] %s invalid STA, macid=%d\n", + __func__, macid); + return; + } - temp_reg = odm_get_bb_reg(p_dm_odm, 0xDDc, MASKBYTE1); - ODM_RT_TRACE(p_dm_odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDDD = 0x%x\n",temp_reg)); + ra = &sta->ra_info; + dtp = &sta->dtp_stat; + pr_debug("[%s]===========>\n", __func__); + + pr_debug("00.(%s) %-12s: IGI=0x%x, Dyn_Rng=0x%x~0x%x, FA_th={%d,%d,%d}\n", + ((comp & ODM_BB_DIG) ? + ((pause_comp & ODM_BB_DIG) ? "P" : "V") : "."), + "DIG", + dig_t->cur_ig_value, + dig_t->rx_gain_range_min, dig_t->rx_gain_range_max, + dig_t->fa_th[0], dig_t->fa_th[1], dig_t->fa_th[2]); + + pr_debug("01.(%s) %-12s: rssi_lv=%d, mask=0x%llx\n", + ((comp & ODM_BB_RA_MASK) ? + ((pause_comp & ODM_BB_RA_MASK) ? "P" : "V") : "."), + "RaMask", + ra->rssi_level, ra->ramask); + +#ifdef CONFIG_DYNAMIC_TX_TWR + pr_debug("02.(%s) %-12s: pwr_lv=%d\n", + ((comp & ODM_BB_DYNAMIC_TXPWR) ? + ((pause_comp & ODM_BB_DYNAMIC_TXPWR) ? "P" : "V") : "."), + "DynTxPwr", + dtp->sta_tx_high_power_lvl); +#endif - temp_reg = odm_get_bb_reg(p_dm_odm, 0xc50, MASKBYTE0); - ODM_RT_TRACE(p_dm_odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xC50 = 0x%x\n",temp_reg)); + pr_debug("05.(%s) %-12s: cck_pd_lv=%d\n", + ((comp & ODM_BB_CCK_PD) ? + ((pause_comp & ODM_BB_CCK_PD) ? "P" : "V") : "."), + "CCK_PD", dm->dm_cckpd_table.cck_pd_lv); + +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + pr_debug("06.(%s) %-12s: div_type=%d, curr_ant=%s\n", + ((comp & ODM_BB_ANT_DIV) ? + ((pause_comp & ODM_BB_ANT_DIV) ? "P" : "V") : "."), + "ANT_DIV", + dm->ant_div_type, + (dm->dm_fat_table.rx_idle_ant == MAIN_ANT) ? "MAIN" : "AUX"); +#endif - temp_reg = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, 0x3fe0); - ODM_RT_TRACE(p_dm_odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RF 0x0[13:5] = 0x%x\n\n",temp_reg)); - */ +#ifdef PHYDM_POWER_TRAINING_SUPPORT + pr_debug("08.(%s) %-12s: PT_score=%d, disable_PT=%d\n", + ((comp & ODM_BB_PWR_TRAIN) ? + ((pause_comp & ODM_BB_PWR_TRAIN) ? "P" : "V") : "."), + "PwrTrain", + dm->pow_train_table.pow_train_score, + dm->is_disable_power_training); +#endif +#ifdef CONFIG_PHYDM_DFS_MASTER + pr_debug("11.(%s) %-12s: dbg_mode=%d, region_domain=%d\n", + ((comp & ODM_BB_DFS) ? + ((pause_comp & ODM_BB_DFS) ? "P" : "V") : "."), + "DFS", + dm->dfs.dbg_mode, dm->dfs_region_domain); +#endif +#ifdef PHYDM_SUPPORT_ADAPTIVITY + pr_debug("13.(%s) %-12s: th{l2h, h2l}={%d, %d}, edcca_flag=%d\n", + ((comp & ODM_BB_ADAPTIVITY) ? + ((pause_comp & ODM_BB_ADAPTIVITY) ? "P" : "V") : "."), + "Adaptivity", + dm->adaptivity.th_l2h, dm->adaptivity.th_h2l, + dm->false_alm_cnt.edcca_flag); +#endif + pr_debug("14.(%s) %-12s: CFO_avg=%d kHz, CFO_traking=%s%d\n", + ((comp & ODM_BB_CFO_TRACKING) ? + ((pause_comp & ODM_BB_CFO_TRACKING) ? "P" : "V") : "."), + "CfoTrack", + cfo_t->CFO_ave_pre, + ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"), + DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap)); + + pr_debug("15.(%s) %-12s: ratio{nhm, clm}={%d, %d}\n", + ((comp & ODM_BB_ENV_MONITOR) ? + ((pause_comp & ODM_BB_ENV_MONITOR) ? "P" : "V") : "."), + "EnvMntr", + dm->dm_ccx_info.nhm_ratio, dm->dm_ccx_info.clm_ratio); + +#ifdef PHYDM_PRIMARY_CCA + pr_debug("16.(%s) %-12s: CCA @ (%s SB)\n", + ((comp & ODM_BB_PRIMARY_CCA) ? + ((pause_comp & ODM_BB_PRIMARY_CCA) ? "P" : "V") : "."), + "PriCCA", + ((dm->dm_pri_cca.mf_state == MF_USC_LSC) ? "D" : + ((dm->dm_pri_cca.mf_state == MF_LSC) ? "L" : "U"))); +#endif +#ifdef CONFIG_ADAPTIVE_SOML + pr_debug("17.(%s) %-12s: soml_en = %s\n", + ((comp & ODM_BB_ADAPTIVE_SOML) ? + ((pause_comp & ODM_BB_ADAPTIVE_SOML) ? "P" : "V") : "."), + "A-SOML", + (dm->dm_soml_table.soml_last_state == SOML_ON) ? + "ON" : "OFF"); +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + pr_debug("18.(%s) %-12s:\n", + ((comp & ODM_BB_LNA_SAT_CHK) ? + ((pause_comp & ODM_BB_LNA_SAT_CHK) ? "P" : "V") : "."), + "LNA_SAT_CHK"); #endif } +void phydm_basic_dbg_message(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + + if (!(dm->debug_components & DBG_CMN)) + return; + + if (dm->cmn_dbg_msg_cnt >= dm->cmn_dbg_msg_period) { + dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD; + } else { + dm->cmn_dbg_msg_cnt += PHYDM_WATCH_DOG_PERIOD; + return; + } + + PHYDM_DBG(dm, DBG_CMN, "[%s] System up time: ((%d sec))---->\n", + __func__, dm->phydm_sys_up_time); + + if (dm->is_linked) + phydm_basic_dbg_msg_linked(dm); + else + PHYDM_DBG(dm, DBG_CMN, "No Link !!!\n"); + + PHYDM_DBG(dm, DBG_CMN, "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all); + + PHYDM_DBG(dm, DBG_CMN, "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all); + + PHYDM_DBG(dm, DBG_CMN, + "[OFDM FA Detail] Parity_Fail=%d, Rate_Illegal=%d, CRC8=%d, MCS_fail=%d, Fast_sync=%d, SB_Search_fail=%d\n", + fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal, + fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail, + fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail); -void phydm_basic_profile( - void *p_dm_void, - u32 *_used, - char *output, - u32 *_out_len -) + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + PHYDM_DBG(dm, DBG_CMN, + "[OFDM FA Detail VHT] CRC8_VHT=%d, MCS_Fail_VHT=%d\n", + fa_t->cnt_crc8_fail_vht, fa_t->cnt_mcs_fail_vht); + } + #endif + + PHYDM_DBG(dm, DBG_CMN, + "is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\n\n", + dm->is_linked, dm->number_linked_client, dm->rssi_min, + dm->dm_dig_table.cur_ig_value, dm->noisy_decision); +} + +void phydm_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - char *cut = NULL; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; + char *cut = NULL; char *ic_type = NULL; u32 used = *_used; u32 out_len = *_out_len; - u32 commit_ver = 0; - u32 date = 0; - char *commit_by = NULL; - u32 release_ver = 0; + u32 date = 0; + char *commit_by = NULL; + u32 release_ver = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% Basic Profile %")); + PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n", + "% Basic Profile %"); - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { -#if (RTL8188E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT) ic_type = "RTL8188E"; date = RELEASE_DATE_8188E; commit_by = COMMIT_BY_8188E; release_ver = RELEASE_VERSION_8188E; #endif - } -#if (RTL8812A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8812) { +#if (RTL8812A_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8812) { ic_type = "RTL8812A"; date = RELEASE_DATE_8812A; commit_by = COMMIT_BY_8812A; release_ver = RELEASE_VERSION_8812A; - } #endif -#if (RTL8821A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821) { +#if (RTL8821A_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8821) { ic_type = "RTL8821A"; date = RELEASE_DATE_8821A; commit_by = COMMIT_BY_8821A; release_ver = RELEASE_VERSION_8821A; - } #endif -#if (RTL8192E_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { +#if (RTL8192E_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8192E) { ic_type = "RTL8192E"; date = RELEASE_DATE_8192E; commit_by = COMMIT_BY_8192E; release_ver = RELEASE_VERSION_8192E; - } #endif -#if (RTL8723B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { +#if (RTL8723B_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8723B) { ic_type = "RTL8723B"; date = RELEASE_DATE_8723B; commit_by = COMMIT_BY_8723B; release_ver = RELEASE_VERSION_8723B; - } #endif -#if (RTL8814A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8814A) { +#if (RTL8814A_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8814A) { ic_type = "RTL8814A"; date = RELEASE_DATE_8814A; commit_by = COMMIT_BY_8814A; release_ver = RELEASE_VERSION_8814A; - } #endif -#if (RTL8881A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8881A) { +#if (RTL8881A_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8881A) { ic_type = "RTL8881A"; - /**/ - } #endif -#if (RTL8822B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) { +#if (RTL8822B_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8822B) { ic_type = "RTL8822B"; date = RELEASE_DATE_8822B; commit_by = COMMIT_BY_8822B; release_ver = RELEASE_VERSION_8822B; - } #endif -#if (RTL8197F_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8197F) { +#if (RTL8197F_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8197F) { ic_type = "RTL8197F"; date = RELEASE_DATE_8197F; commit_by = COMMIT_BY_8197F; release_ver = RELEASE_VERSION_8197F; - } #endif - -#if (RTL8703B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8703B) { - +#if (RTL8703B_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8703B) { ic_type = "RTL8703B"; date = RELEASE_DATE_8703B; commit_by = COMMIT_BY_8703B; release_ver = RELEASE_VERSION_8703B; - - } #endif -#if (RTL8195A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8195A) { +#if (RTL8195A_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8195A) { ic_type = "RTL8195A"; - /**/ - } #endif -#if (RTL8188F_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { +#if (RTL8188F_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8188F) { ic_type = "RTL8188F"; date = RELEASE_DATE_8188F; commit_by = COMMIT_BY_8188F; release_ver = RELEASE_VERSION_8188F; - } #endif -#if (RTL8723D_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { +#if (RTL8723D_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8723D) { ic_type = "RTL8723D"; date = RELEASE_DATE_8723D; commit_by = COMMIT_BY_8723D; release_ver = RELEASE_VERSION_8723D; - /**/ - } #endif + } -/* JJ ADD 20161014 */ -#if (RTL8710B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8710B) { +/* @JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8710B) { ic_type = "RTL8710B"; date = RELEASE_DATE_8710B; commit_by = COMMIT_BY_8710B; release_ver = RELEASE_VERSION_8710B; - /**/ } #endif -#if (RTL8821C_SUPPORT == 1) - else if (p_dm_odm->support_ic_type == ODM_RTL8821C) { +#if (RTL8821C_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8821C) { ic_type = "RTL8821C"; date = RELEASE_DATE_8821C; commit_by = COMMIT_BY_8821C; release_ver = RELEASE_VERSION_8821C; } #endif - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s (MP Chip: %s)\n", "IC type", ic_type, p_dm_odm->is_mp_chip ? "Yes" : "No")); - if (p_dm_odm->cut_version == ODM_CUT_A) +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8192F) { + ic_type = "RTL8192F"; + date = RELEASE_DATE_8192F; + commit_by = COMMIT_BY_8192F; + release_ver = RELEASE_VERSION_8192F; + } +#endif + +#if (RTL8198F_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8198F) { + ic_type = "RTL8198F"; + date = RELEASE_DATE_8198F; + commit_by = COMMIT_BY_8198F; + release_ver = RELEASE_VERSION_8198F; + } +#endif + +#if (RTL8822C_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8822C) { + ic_type = "RTL8822C"; + date = RELEASE_DATE_8822C; + commit_by = COMMIT_BY_8822C; + release_ver = RELEASE_VERSION_8822C; + } +#endif + + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s (MP Chip: %s)\n", "IC type", ic_type, + dm->is_mp_chip ? "Yes" : "No"); + + if (dm->cut_version == ODM_CUT_A) cut = "A"; - else if (p_dm_odm->cut_version == ODM_CUT_B) + else if (dm->cut_version == ODM_CUT_B) cut = "B"; - else if (p_dm_odm->cut_version == ODM_CUT_C) + else if (dm->cut_version == ODM_CUT_C) cut = "C"; - else if (p_dm_odm->cut_version == ODM_CUT_D) + else if (dm->cut_version == ODM_CUT_D) cut = "D"; - else if (p_dm_odm->cut_version == ODM_CUT_E) + else if (dm->cut_version == ODM_CUT_E) cut = "E"; - else if (p_dm_odm->cut_version == ODM_CUT_F) + else if (dm->cut_version == ODM_CUT_F) cut = "F"; - else if (p_dm_odm->cut_version == ODM_CUT_I) + else if (dm->cut_version == ODM_CUT_I) cut = "I"; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "cut version", cut)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter version", odm_get_hw_img_version(p_dm_odm))); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Commit date", date)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY Parameter Commit by", commit_by)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Release version", release_ver)); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %d\n", + "RFE type", dm->rfe_type); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Cut Ver", cut); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %d\n", + "PHY Para Ver", odm_get_hw_img_version(dm)); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %d\n", + "PHY Para Commit date", date); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "PHY Para Commit by", commit_by); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %d\n", + "PHY Para Release Ver", release_ver); + + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %d (Subversion: %d)\n", "FW Ver", dm->fw_version, + dm->fw_sub_version); + + /* @1 PHY DM version List */ + PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n", + "% PHYDM version %"); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Code base", PHYDM_CODE_BASE); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Release Date", PHYDM_RELEASE_DATE); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Adaptivity", ADAPTIVITY_VERSION); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "DIG", DIG_VERSION); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "CFO Tracking", CFO_TRACKING_VERSION); +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "AntDiv", ANTDIV_VERSION); +#endif +#ifdef CONFIG_DYNAMIC_TX_TWR + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Dynamic TxPower", DYNAMIC_TXPWR_VERSION); +#endif + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "RA Info", RAINFO_VERSION); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - { - struct _ADAPTER *adapter = p_dm_odm->adapter; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", adapter->MgntInfo.FirmwareVersion, adapter->MgntInfo.FirmwareSubVersion)); - } -#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) - { - struct rtl8192cd_priv *priv = p_dm_odm->priv; - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", priv->pshare->fw_version, priv->pshare->fw_sub_version)); - } -#else - { - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW version", p_hal_data->firmware_version, p_hal_data->firmware_sub_version)); - } -#endif - /* 1 PHY DM version List */ - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% PHYDM version %")); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Code base", PHYDM_CODE_BASE)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Release Date", PHYDM_RELEASE_DATE)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "adaptivity", ADAPTIVITY_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "DIG", DIG_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic BB PowerSaving", DYNAMIC_BBPWRSAV_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "CFO Tracking", CFO_TRACKING_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Diversity", ANTDIV_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Power Tracking", POWRTRACKING_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic TxPower", DYNAMIC_TXPWR_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "RA Info", RAINFO_VERSION)); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Detection", ANTDECT_VERSION)); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "AntDetect", ANTDECT_VERSION); +#endif +#ifdef CONFIG_PATH_DIVERSITY + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "PathDiv", PATHDIV_VERSION); +#endif +#ifdef CONFIG_ADAPTIVE_SOML + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Adaptive SOML", ADAPTIVE_SOML_VERSION); #endif - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Auto channel Selection", ACS_VERSION)); -#if PHYDM_SUPPORT_EDCA - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "EDCA Turbo", EDCATURBO_VERSION)); +#if (PHYDM_LA_MODE_SUPPORT) + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "LA mode", DYNAMIC_LA_MODE); #endif - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "path Diversity", PATHDIV_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "LA mode", DYNAMIC_LA_MODE)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic RX path", DYNAMIC_RX_PATH_VERSION)); - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "DFS", DFS_VERSION)); +#ifdef PHYDM_PRIMARY_CCA + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Primary CCA", PRIMARYCCA_VERSION); +#endif + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "DFS", DFS_VERSION); -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8822B", PHY_CONFIG_VERSION_8822B)); +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822B) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PHY config 8822B", + PHY_CONFIG_VERSION_8822B); #endif -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8197F", PHY_CONFIG_VERSION_8197F)); +#if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PHY config 8197F", + PHY_CONFIG_VERSION_8197F); +#endif + +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PHY config 8192F", + PHY_CONFIG_VERSION_8192F); #endif + *_used = used; *_out_len = out_len; -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ + +#endif /*@#if CONFIG_PHYDM_DEBUG_FUNCTION*/ } -#if CONFIG_PHYDM_DEBUG_FUNCTION -void -phydm_fw_trace_en_h2c( - void *p_dm_void, - boolean enable, - u32 fw_debug_component, - u32 monitor_mode, - u32 macid -) +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION +void phydm_fw_trace_en_h2c(void *dm_void, boolean enable, + u32 fw_dbg_comp, u32 monitor_mode, u32 macid) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 h2c_parameter[7] = {0}; - u8 cmd_length; - - if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 h2c_parameter[7] = {0}; + u8 cmd_length; + if (dm->support_ic_type & PHYDM_IC_3081_SERIES) { h2c_parameter[0] = enable; - h2c_parameter[1] = (u8)(fw_debug_component & MASKBYTE0); - h2c_parameter[2] = (u8)((fw_debug_component & MASKBYTE1) >> 8); - h2c_parameter[3] = (u8)((fw_debug_component & MASKBYTE2) >> 16); - h2c_parameter[4] = (u8)((fw_debug_component & MASKBYTE3) >> 24); + h2c_parameter[1] = (u8)(fw_dbg_comp & MASKBYTE0); + h2c_parameter[2] = (u8)((fw_dbg_comp & MASKBYTE1) >> 8); + h2c_parameter[3] = (u8)((fw_dbg_comp & MASKBYTE2) >> 16); + h2c_parameter[4] = (u8)((fw_dbg_comp & MASKBYTE3) >> 24); h2c_parameter[5] = (u8)monitor_mode; h2c_parameter[6] = (u8)macid; cmd_length = 7; } else { - h2c_parameter[0] = enable; h2c_parameter[1] = (u8)monitor_mode; h2c_parameter[2] = (u8)macid; cmd_length = 3; } - - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("---->\n")); + PHYDM_DBG(dm, DBG_FW_TRACE, "---->\n"); if (monitor_mode == 0) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d ))\n", enable)); + PHYDM_DBG(dm, DBG_FW_TRACE, "[H2C] FW_debug_en: (( %d ))\n", + enable); else - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n", enable, monitor_mode, macid)); - odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n", + enable, monitor_mode, macid); + odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter); } - -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) -boolean -phydm_api_set_txagc( - struct PHY_DM_STRUCT *p_dm_odm, - u32 power_index, - enum odm_rf_radio_path_e path, - u8 hw_rate, - boolean is_single_rate -) +void phydm_get_per_path_txagc(void *dm_void, u8 path, u32 *_used, char *output, + u32 *_out_len) { - boolean ret = false; - -#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { - if (is_single_rate) { -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) - ret = phydm_write_txagc_1byte_8822b(p_dm_odm, power_index, path, hw_rate); -#endif -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - ret = phydm_write_txagc_1byte_8821c(p_dm_odm, power_index, path, hw_rate); -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - set_current_tx_agc(p_dm_odm->priv, path, hw_rate, (u8)power_index); -#endif + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rate_idx; + u8 txagc; + u32 used = *_used; + u32 out_len = *_out_len; - } else { - u8 i; -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) - ret = config_phydm_write_txagc_8822b(p_dm_odm, power_index, path, hw_rate); -#endif -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - ret = config_phydm_write_txagc_8821c(p_dm_odm, power_index, path, hw_rate); -#endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - for (i = 0; i < 4; i++) - set_current_tx_agc(p_dm_odm->priv, path, (hw_rate + i), (u8)power_index); -#endif - } - } -#endif +#ifdef PHYDM_COMMON_API_SUPPORT + if (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) + return; + if (dm->num_rf_path == 1 && path > RF_PATH_A) + return; + else if (dm->num_rf_path == 2 && path > RF_PATH_B) + return; + else if (dm->num_rf_path == 3 && path > RF_PATH_C) + return; + else if (dm->num_rf_path == 4 && path > RF_PATH_D) + return; -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - ret = config_phydm_write_txagc_8197f(p_dm_odm, power_index, path, hw_rate); + for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) { + if (rate_idx == ODM_RATE1M) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s\n", "CCK====>"); + else if (rate_idx == ODM_RATE6M) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "OFDM====>"); + else if (rate_idx == ODM_RATEMCS0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "HT 1ss====>"); + else if (rate_idx == ODM_RATEMCS8) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "HT 2ss====>"); + else if (rate_idx == ODM_RATEMCS16) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "HT 3ss====>"); + else if (rate_idx == ODM_RATEMCS24) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "HT 4ss====>"); + else if (rate_idx == ODM_RATEVHTSS1MCS0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "VHT 1ss====>"); + else if (rate_idx == ODM_RATEVHTSS2MCS0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "VHT 2ss====>"); + else if (rate_idx == ODM_RATEVHTSS3MCS0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "VHT 3ss====>"); + else if (rate_idx == ODM_RATEVHTSS4MCS0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "VHT 4ss====>"); + + txagc = phydm_api_get_txagc(dm, (enum rf_path)path, rate_idx); + if (config_phydm_read_txagc_check(txagc)) + PDM_SNPF(out_len, used, output + used, + out_len - used, " 0x%02x ", txagc); + else + PDM_SNPF(out_len, used, output + used, + out_len - used, " 0x%s ", "xx"); + } #endif - return ret; + *_used = used; + *_out_len = out_len; } -u8 -phydm_api_get_txagc( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e path, - u8 hw_rate -) +void phydm_get_txagc(void *dm_void, u32 *_used, char *output, u32 *_out_len) { - u8 ret = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - ret = config_phydm_read_txagc_8822b(p_dm_odm, path, hw_rate); -#endif + /* path-A */ + PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n", + "path-A===================="); + phydm_get_per_path_txagc(dm, RF_PATH_A, &used, output, &out_len); -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - ret = config_phydm_read_txagc_8197f(p_dm_odm, path, hw_rate); -#endif + /* path-B */ + PDM_SNPF(out_len, used, output + used, out_len - used, "\n%-35s\n", + "path-B===================="); + phydm_get_per_path_txagc(dm, RF_PATH_B, &used, output, &out_len); -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - ret = config_phydm_read_txagc_8821c(p_dm_odm, path, hw_rate); -#endif + /* path-C */ + PDM_SNPF(out_len, used, output + used, out_len - used, "\n%-35s\n", + "path-C===================="); + phydm_get_per_path_txagc(dm, RF_PATH_C, &used, output, &out_len); - return ret; -} + /* path-D */ + PDM_SNPF(out_len, used, output + used, out_len - used, "\n%-35s\n", + "path-D===================="); + phydm_get_per_path_txagc(dm, RF_PATH_D, &used, output, &out_len); + *_used = used; + *_out_len = out_len; +} -boolean -phydm_api_switch_bw_channel( - struct PHY_DM_STRUCT *p_dm_odm, - u8 central_ch, - u8 primary_ch_idx, - enum odm_bw_e bandwidth -) +void phydm_set_txagc(void *dm_void, u32 *const val, u32 *_used, + char *output, u32 *_out_len) { - boolean ret = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + u32 pow = 0; /*power index*/ + u8 vht_start_rate = ODM_RATEVHTSS1MCS0; + boolean rpt = true; + enum rf_path path = RF_PATH_A; + +/*@val[1] = path*/ +/*@val[2] = hw_rate*/ +/*@val[3] = power_index*/ + +#ifdef PHYDM_COMMON_API_SUPPORT + if (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) + return; -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - ret = config_phydm_switch_channel_bw_8822b(p_dm_odm, central_ch, primary_ch_idx, bandwidth); -#endif + path = (enum rf_path)val[1]; -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - ret = config_phydm_switch_channel_bw_8197f(p_dm_odm, central_ch, primary_ch_idx, bandwidth); -#endif + if (val[1] >= dm->num_rf_path) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write path-%d rate_idx-0x%x fail\n", val[1], val[2]); + } else if ((u8)val[2] != 0xff) { + if (phydm_api_set_txagc(dm, val[3], path, (u8)val[2], true)) + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write path-%d rate_idx-0x%x = 0x%x\n", + val[1], val[2], val[3]); + else + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write path-%d rate index-0x%x fail\n", + val[1], val[2]); + } else { -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8821C) - ret = config_phydm_switch_channel_bw_8821c(p_dm_odm, central_ch, primary_ch_idx, bandwidth); -#endif + if (dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) { + pow = (val[3] & 0x3f); + pow = BYTE_DUPLICATE_2_DWORD(pow); + + for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + } else if (dm->support_ic_type & + (ODM_RTL8197F | ODM_RTL8192F)) { + pow = (val[3] & 0x3f); + for (i = 0; i <= ODM_RATEMCS15; i++) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + } else if (dm->support_ic_type & ODM_RTL8198F) { + pow = (val[3] & 0x7f); + for (i = 0; i <= ODM_RATEVHTSS4MCS9; i++) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + } else if (dm->support_ic_type & ODM_RTL8822C) { + pow = (val[3] & 0x7f); + for (i = 0; i <= ODM_RATEMCS15; i++) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + } + + if (rpt) + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write all TXAGC of path-%d = 0x%x\n", + val[1], val[3]); + else + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write all TXAGC of path-%d fail\n", val[1]); + } - return ret; +#endif + *_used = used; + *_out_len = out_len; } -boolean -phydm_api_trx_mode( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_path_e tx_path, - enum odm_rf_path_e rx_path, - boolean is_tx2_path -) +void phydm_shift_txagc(void *dm_void, u32 *const val, u32 *_used, char *output, + u32 *_out_len) { - boolean ret = false; - -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - ret = config_phydm_trx_mode_8822b(p_dm_odm, tx_path, rx_path, is_tx2_path); -#endif + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + u32 pow = 0; /*Power index*/ + boolean rpt = true; + u8 vht_start_rate = ODM_RATEVHTSS1MCS0; + enum rf_path path = RF_PATH_A; + +#ifdef PHYDM_COMMON_API_SUPPORT + if (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) + return; -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - ret = config_phydm_trx_mode_8197f(p_dm_odm, tx_path, rx_path, is_tx2_path); -#endif + if (val[1] >= dm->num_rf_path) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write path-%d fail\n", val[1]); + return; + } - return ret; -} -#endif + path = (enum rf_path)val[1]; -void -phydm_get_per_path_txagc( - void *p_dm_void, - u8 path, - u32 *_used, - char *output, - u32 *_out_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 rate_idx; - u8 txagc; - u32 used = *_used; - u32 out_len = *_out_len; - -#if ((RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - if (((p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) && (path <= ODM_RF_PATH_B)) || - ((p_dm_odm->support_ic_type & (ODM_RTL8821C)) && (path <= ODM_RF_PATH_A))) { - for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) { - if (rate_idx == ODM_RATE1M) - PHYDM_SNPRINTF((output + used, out_len - used, " %-35s\n", "CCK====>")); - else if (rate_idx == ODM_RATE6M) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "OFDM====>")); - else if (rate_idx == ODM_RATEMCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 1ss====>")); - else if (rate_idx == ODM_RATEMCS8) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 2ss====>")); - else if (rate_idx == ODM_RATEMCS16) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 3ss====>")); - else if (rate_idx == ODM_RATEMCS24) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 4ss====>")); - else if (rate_idx == ODM_RATEVHTSS1MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 1ss====>")); - else if (rate_idx == ODM_RATEVHTSS2MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 2ss====>")); - else if (rate_idx == ODM_RATEVHTSS3MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 3ss====>")); - else if (rate_idx == ODM_RATEVHTSS4MCS0) - PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 4ss====>")); - - txagc = phydm_api_get_txagc(p_dm_odm, (enum odm_rf_radio_path_e) path, rate_idx); - if (config_phydm_read_txagc_check(txagc)) - PHYDM_SNPRINTF((output + used, out_len - used, " 0x%02x ", txagc)); - else - PHYDM_SNPRINTF((output + used, out_len - used, " 0x%s ", "xx")); + if ((u8)val[2] == 0) { + /*@{0:-, 1:+} {Pwr Offset}*/ + if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) { + for (i = 0; i <= ODM_RATEMCS7; i++) { + pow = phydm_api_get_txagc(dm, path, i) - val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + for (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) { + pow = phydm_api_get_txagc(dm, path, i) - val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & (ODM_RTL8822B)) { + for (i = 0; i <= ODM_RATEMCS15; i++) { + pow = phydm_api_get_txagc(dm, path, i) - val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) { + pow = phydm_api_get_txagc(dm, path, i) - val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & + (ODM_RTL8197F | ODM_RTL8192F)) { + for (i = 0; i <= ODM_RATEMCS15; i++) { + pow = phydm_api_get_txagc(dm, path, i) - val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & (ODM_RTL8822C)) { + rpt &= phydm_api_shift_txagc(dm, val[3], path, 0); + } + } else if ((u8)val[2] == 1) { + /*@{0:-, 1:+} {Pwr Offset}*/ + if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) { + for (i = 0; i <= ODM_RATEMCS7; i++) { + pow = phydm_api_get_txagc(dm, path, i) + val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + for (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) { + pow = phydm_api_get_txagc(dm, path, i) + val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & (ODM_RTL8822B)) { + for (i = 0; i <= ODM_RATEMCS15; i++) { + pow = phydm_api_get_txagc(dm, path, i) + val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) { + pow = phydm_api_get_txagc(dm, path, i) + val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & + (ODM_RTL8197F | ODM_RTL8192F)) { + for (i = 0; i <= ODM_RATEMCS15; i++) { + pow = phydm_api_get_txagc(dm, path, i) + val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & (ODM_RTL8822C)) { + rpt &= phydm_api_shift_txagc(dm, val[3], path, 1); } } + PDM_SNPF(out_len, used, output + used, out_len - used, + "[All rate] Set Path-%d Pow_idx: %s %d(%d.%s dB)\n", + val[1], (val[2] ? "+" : "-"), val[3], val[3] >> 1, + ((val[3] & 1) ? "5" : "0")); + #endif + *_used = used; + *_out_len = out_len; } - -void -phydm_get_txagc( - void *p_dm_void, - u32 *_used, - char *output, - u32 *_out_len -) +void phydm_set_txagc_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 used = *_used; - u32 out_len = *_out_len; - - /* path-A */ - PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "path-A====================")); - phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_A, _used, output, _out_len); - - /* path-B */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "path-B====================")); - phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_B, _used, output, _out_len); + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 var1[10] = {0}; + char help[] = "-h"; + u8 i = 0, input_idx = 0; - /* path-C */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "path-C====================")); - phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_C, _used, output, _out_len); + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; + } + } - /* path-D */ - PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "path-D====================")); - phydm_get_per_path_txagc(p_dm_odm, ODM_RF_PATH_D, _used, output, _out_len); + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{Dis:0, En:1} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{Pwr Shift(All rate):2} {pathA~D(0~3)} {0:-, 1:+} {Pwr Offset(dec)}\n"); + } else if (var1[0] == 0) { + dm->is_disable_phy_api = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable API debug mode\n"); + } else if (var1[0] == 1) { + dm->is_disable_phy_api = false; + phydm_set_txagc(dm, (u32 *)var1, &used, output, &out_len); + dm->is_disable_phy_api = true; + } else if (var1[0] == 2) { + PHYDM_SSCANF(input[4], DCMD_HEX, &var1[3]); + dm->is_disable_phy_api = false; + phydm_shift_txagc(dm, (u32 *)var1, &used, output, &out_len); + dm->is_disable_phy_api = true; + } + *_used = used; + *_out_len = out_len; } -void -phydm_set_txagc( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) +void phydm_debug_trace(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 used = *_used; - u32 out_len = *_out_len; - - /*dm_value[1] = path*/ - /*dm_value[2] = hw_rate*/ - /*dm_value[3] = power_index*/ - -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)) { - if (dm_value[1] <= 1) { - if ((u8)dm_value[2] != 0xff) { - if (phydm_api_set_txagc(p_dm_odm, dm_value[3], (enum odm_rf_radio_path_e) dm_value[1], (u8)dm_value[2], true)) - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s%x\n", "Write path-", dm_value[1], "rate index-0x", dm_value[2], " = 0x", dm_value[3])); - else - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[1] & 0x1), "rate index-0x", (dm_value[2] & 0x7f), " fail")); - } else { - u8 i; - u32 power_index; - boolean status = true; - - power_index = (dm_value[3] & 0x3f); - - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { - power_index = (power_index << 24) | (power_index << 16) | (power_index << 8) | (power_index); - - for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4) - status = (status & phydm_api_set_txagc(p_dm_odm, power_index, (enum odm_rf_radio_path_e) dm_value[1], i, false)); - } else if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - for (i = 0; i <= ODM_RATEMCS15; i++) - status = (status & phydm_api_set_txagc(p_dm_odm, power_index, (enum odm_rf_radio_path_e) dm_value[1], i, false)); - } + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 pre_debug_components, one = 1; + u64 comp = 0; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + u8 i; - if (status) - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x\n", "Write all TXAGC of path-", dm_value[1], " = 0x", dm_value[3])); - else - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s\n", "Write all TXAGC of path-", dm_value[1], " fail")); - } - } else - PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[1] & 0x1), "rate index-0x", (dm_value[2] & 0x7f), " fail")); + for (i = 0; i < 5; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]); } -#endif -} - -void -phydm_debug_trace( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 pre_debug_components, one = 1; - u32 used = *_used; - u32 out_len = *_out_len; - - pre_debug_components = p_dm_odm->debug_components; - - PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); - if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Debug Message] PhyDM Selection")); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((p_dm_odm->debug_components & ODM_COMP_DIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((p_dm_odm->debug_components & ODM_COMP_RA_MASK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((p_dm_odm->debug_components & ODM_COMP_DYNAMIC_TXPWR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((p_dm_odm->debug_components & ODM_COMP_FA_CNT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((p_dm_odm->debug_components & ODM_COMP_RSSI_MONITOR) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))SNIFFER\n", ((p_dm_odm->debug_components & ODM_COMP_SNIFFER) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((p_dm_odm->debug_components & ODM_COMP_ANT_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "07. (( %s ))DFS\n", ((p_dm_odm->debug_components & ODM_COMP_DFS) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))NOISY_DETECT\n", ((p_dm_odm->debug_components & ODM_COMP_NOISY_DETECT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((p_dm_odm->debug_components & ODM_COMP_RATE_ADAPTIVE) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((p_dm_odm->debug_components & ODM_COMP_PATH_DIV) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "12. (( %s ))DYNAMIC_PRICCA\n", ((p_dm_odm->debug_components & ODM_COMP_DYNAMIC_PRICCA) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))MP\n", ((p_dm_odm->debug_components & ODM_COMP_MP) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))struct _CFO_TRACKING_\n", ((p_dm_odm->debug_components & ODM_COMP_CFO_TRACKING) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))struct _ACS_\n", ((p_dm_odm->debug_components & ODM_COMP_ACS) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))ADAPTIVITY\n", ((p_dm_odm->debug_components & PHYDM_COMP_ADAPTIVITY) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))RA_DBG\n", ((p_dm_odm->debug_components & PHYDM_COMP_RA_DBG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "19. (( %s ))TXBF\n", ((p_dm_odm->debug_components & PHYDM_COMP_TXBF) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))EDCA_TURBO\n", ((p_dm_odm->debug_components & ODM_COMP_EDCA_TURBO) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "22. (( %s ))FW_DEBUG_TRACE\n", ((p_dm_odm->debug_components & ODM_FW_DEBUG_TRACE) ? ("V") : (".")))); - - PHYDM_SNPRINTF((output + used, out_len - used, "24. (( %s ))TX_PWR_TRACK\n", ((p_dm_odm->debug_components & ODM_COMP_TX_PWR_TRACK) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "26. (( %s ))CALIBRATION\n", ((p_dm_odm->debug_components & ODM_COMP_CALIBRATION) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "28. (( %s ))PHY_CONFIG\n", ((p_dm_odm->debug_components & ODM_PHY_CONFIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "29. (( %s ))INIT\n", ((p_dm_odm->debug_components & ODM_COMP_INIT) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "30. (( %s ))COMMON\n", ((p_dm_odm->debug_components & ODM_COMP_COMMON) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "31. (( %s ))API\n", ((p_dm_odm->debug_components & ODM_COMP_API) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - - } else if (dm_value[0] == 101) { - p_dm_odm->debug_components = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Disable all debug components")); + comp = dm->debug_components; + pre_debug_components = dm->debug_components; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n================================\n"); + if (val[0] == 100) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[DBG MSG] Component Selection\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))DIG\n", + ((comp & DBG_DIG) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))RA_MASK\n", + ((comp & DBG_RA_MASK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "02. (( %s ))DYN_TXPWR\n", + ((comp & DBG_DYN_TXPWR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "03. (( %s ))FA_CNT\n", + ((comp & DBG_FA_CNT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "04. (( %s ))RSSI_MNTR\n", + ((comp & DBG_RSSI_MNTR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "05. (( %s ))CCKPD\n", + ((comp & DBG_CCKPD) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "06. (( %s ))ANT_DIV\n", + ((comp & DBG_ANT_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "07. (( %s ))SMT_ANT\n", + ((comp & DBG_SMT_ANT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "08. (( %s ))PWR_TRAIN\n", + ((comp & DBG_PWR_TRAIN) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "09. (( %s ))RA\n", + ((comp & DBG_RA) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "10. (( %s ))PATH_DIV\n", + ((comp & DBG_PATH_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "11. (( %s ))DFS\n", + ((comp & DBG_DFS) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "12. (( %s ))DYN_ARFR\n", + ((comp & DBG_DYN_ARFR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "13. (( %s ))ADAPTIVITY\n", + ((comp & DBG_ADPTVTY) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "14. (( %s ))CFO_TRK\n", + ((comp & DBG_CFO_TRK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "15. (( %s ))ENV_MNTR\n", + ((comp & DBG_ENV_MNTR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "16. (( %s ))PRI_CCA\n", + ((comp & DBG_PRI_CCA) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "17. (( %s ))ADPTV_SOML\n", + ((comp & DBG_ADPTV_SOML) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "18. (( %s ))LNA_SAT_CHK\n", + ((comp & DBG_LNA_SAT_CHK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "20. (( %s ))PHY_STATUS\n", + ((comp & DBG_PHY_STATUS) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "21. (( %s ))TMP\n", + ((comp & DBG_TMP) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "22. (( %s ))FW_DBG_TRACE\n", + ((comp & DBG_FW_TRACE) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "23. (( %s ))TXBF\n", + ((comp & DBG_TXBF) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "24. (( %s ))COMMON_FLOW\n", + ((comp & DBG_COMMON_FLOW) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "28. (( %s ))PHY_CONFIG\n", + ((comp & ODM_PHY_CONFIG) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "29. (( %s ))INIT\n", + ((comp & ODM_COMP_INIT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "30. (( %s ))COMMON\n", + ((comp & DBG_CMN) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "31. (( %s ))API\n", + ((comp & ODM_COMP_API) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + + } else if (val[0] == 101) { + dm->debug_components = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable all debug components\n"); } else { - if (dm_value[1] == 1) /*enable*/ - p_dm_odm->debug_components |= (one << dm_value[0]); - else if (dm_value[1] == 2) /*disable*/ - p_dm_odm->debug_components &= ~(one << dm_value[0]); + if (val[1] == 1) /*@enable*/ + dm->debug_components |= (one << val[0]); + else if (val[1] == 2) /*@disable*/ + dm->debug_components &= ~(one << val[0]); else - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); - } - PHYDM_SNPRINTF((output + used, out_len - used, "pre-DbgComponents = 0x%x\n", pre_debug_components)); - PHYDM_SNPRINTF((output + used, out_len - used, "Curr-DbgComponents = 0x%x\n", p_dm_odm->debug_components)); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); -} + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Warning] 1:on, 2:off\n"); -void -phydm_fw_debug_trace( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 pre_fw_debug_components, one = 1; - u32 used = *_used; - u32 out_len = *_out_len; - - pre_fw_debug_components = p_dm_odm->fw_debug_components; - - PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); - if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[FW Debug Component]")); - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); - PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))RA\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_RA) ? ("V") : (".")))); - - if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { - PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))MU\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_MU) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))path Div\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_PHY_CONFIG) ? ("V") : (".")))); - PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))Phy Config\n", ((p_dm_odm->fw_debug_components & PHYDM_FW_COMP_PHY_CONFIG) ? ("V") : (".")))); - } - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + if ((BIT(val[0]) == DBG_PHY_STATUS) && val[1] == 1) { + dm->phy_dbg_info.show_phy_sts_all_pkt = (u8)val[2]; + dm->phy_dbg_info.show_phy_sts_max_cnt = (u16)val[3]; - } else { - if (dm_value[0] == 101) { - p_dm_odm->fw_debug_components = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Clear all fw debug components")); - } else { - if (dm_value[1] == 1) /*enable*/ - p_dm_odm->fw_debug_components |= (one << dm_value[0]); - else if (dm_value[1] == 2) /*disable*/ - p_dm_odm->fw_debug_components &= ~(one << dm_value[0]); - else - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); - } + PDM_SNPF(out_len, used, output + used, out_len - used, + "show_all_pkt=%d, show_max_num=%d\n\n", + dm->phy_dbg_info.show_phy_sts_all_pkt, + dm->phy_dbg_info.show_phy_sts_max_cnt); - if (p_dm_odm->fw_debug_components == 0) { - p_dm_odm->debug_components &= ~ODM_FW_DEBUG_TRACE; - phydm_fw_trace_en_h2c(p_dm_odm, false, p_dm_odm->fw_debug_components, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ - } else { - p_dm_odm->debug_components |= ODM_FW_DEBUG_TRACE; - phydm_fw_trace_en_h2c(p_dm_odm, true, p_dm_odm->fw_debug_components, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ + } else if ((BIT(val[0]) == DBG_CMN) && (val[1] == 1)) { + dm->cmn_dbg_msg_period = (u8)val[2]; + + if (dm->cmn_dbg_msg_period < PHYDM_WATCH_DOG_PERIOD) + dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "cmn_dbg_msg_period=%d\n", + dm->cmn_dbg_msg_period); } } + PDM_SNPF(out_len, used, output + used, out_len - used, + "pre-DbgComponents = 0x%llx\n", pre_debug_components); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Curr-DbgComponents = 0x%llx\n", dm->debug_components); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + + *_used = used; + *_out_len = out_len; } -void -phydm_dump_bb_reg( - void *p_dm_void, - u32 *_used, - char *output, - u32 *_out_len -) +void phydm_fw_debug_trace(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 addr = 0; - u32 used = *_used; - u32 out_len = *_out_len; - - - /* BB Reg, For Nseries IC we only need to dump page8 to pageF using 3 digits*/ - for (addr = 0x800; addr < 0xfff; addr += 4) { - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%03x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); - else - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + u8 i, input_idx = 0; + u32 pre_fw_debug_components = 0, one = 1; + u32 comp = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]); + input_idx++; + } } - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C)) { + if (input_idx == 0) + return; - if (p_dm_odm->rf_type > ODM_2T2R) { - for (addr = 0x1800; addr < 0x18ff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + pre_fw_debug_components = dm->fw_debug_components; + comp = dm->fw_debug_components; + + PDM_SNPF(out_len, used, output + used, out_len - used, "\n%s\n", + "================================"); + if (val[0] == 100) { + PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n", + "[FW Debug Component]"); + PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n", + "================================"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))RA\n", + ((comp & PHYDM_FW_COMP_RA) ? ("V") : ("."))); + + if (dm->support_ic_type & PHYDM_IC_3081_SERIES) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))MU\n", + ((comp & PHYDM_FW_COMP_MU) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "02. (( %s ))path Div\n", + ((comp & + PHYDM_FW_COMP_PATH_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "03. (( %s ))Power training\n", + ((comp & PHYDM_FW_COMP_PT) ? ("V") : ("."))); } + PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n", + "================================"); - if (p_dm_odm->rf_type > ODM_3T3R) { - for (addr = 0x1a00; addr < 0x1aff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + } else { + if (val[0] == 101) { + dm->fw_debug_components = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "Clear all fw debug components"); + } else { + if (val[1] == 1) /*@enable*/ + dm->fw_debug_components |= (one << val[0]); + else if (val[1] == 2) /*@disable*/ + dm->fw_debug_components &= ~(one << val[0]); + else + PDM_SNPF(out_len, used, output + used, + out_len - used, "%s\n", + "[Warning!!!] 1:enable, 2:disable"); } - for (addr = 0x1900; addr < 0x19ff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); - - for (addr = 0x1c00; addr < 0x1cff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + comp = dm->fw_debug_components; - for (addr = 0x1f00; addr < 0x1fff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + if (comp == 0) { + dm->debug_components &= ~DBG_FW_TRACE; + /*@H2C to enable C2H Msg*/ + phydm_fw_trace_en_h2c(dm, false, comp, val[2], val[3]); + } else { + dm->debug_components |= DBG_FW_TRACE; + /*@H2C to enable C2H Msg*/ + phydm_fw_trace_en_h2c(dm, true, comp, val[2], val[3]); + } } } -void -phydm_dump_all_reg( - void *p_dm_void, - u32 *_used, - char *output, - u32 *_out_len -) +#if (ODM_IC_11N_SERIES_SUPPORT) +void phydm_dump_bb_reg_n(void *dm_void, u32 *_used, char *output, u32 *_out_len) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 addr = 0; - u32 used = *_used; - u32 out_len = *_out_len; - - /* dump MAC register */ - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "MAC==========\n")); - for (addr = 0; addr < 0x7ff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; - for (addr = 0x1000; addr < 0x17ff; addr += 4) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%04x 0x%08x\n", addr, odm_get_bb_reg(p_dm_odm, addr, MASKDWORD))); + /*@For Nseries IC we only need to dump page8 to pageF using 3 digits*/ + for (addr = 0x800; addr < 0xfff; addr += 4) { + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%03x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); + } - /* dump BB register */ - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "BB==========\n")); - phydm_dump_bb_reg(p_dm_odm, &used, output, &out_len); + *_used = used; + *_out_len = out_len; +} +#endif - /* dump RF register */ - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-A==========\n")); - for (addr = 0; addr < 0xFF; addr++) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, addr, RFREGOFFSETMASK))); +#if (ODM_IC_11AC_SERIES_SUPPORT) +void phydm_dump_bb_reg_ac(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; - if (p_dm_odm->rf_type > ODM_1T1R) { - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-B==========\n")); - for (addr = 0; addr < 0xFF; addr++) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_B, addr, RFREGOFFSETMASK))); + for (addr = 0x800; addr < 0xfff; addr += 4) { + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); } - if (p_dm_odm->rf_type > ODM_2T2R) { - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-C==========\n")); - for (addr = 0; addr < 0xFF; addr++) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_C, addr, RFREGOFFSETMASK))); + if (!(dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C))) + goto rpt_reg; + + if (dm->rf_type > RF_2T2R) { + for (addr = 0x1800; addr < 0x18ff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); } - if (p_dm_odm->rf_type > ODM_3T3R) { - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "RF-D==========\n")); - for (addr = 0; addr < 0xFF; addr++) - PHYDM_VAST_INFO_SNPRINTF((output + used, out_len - used, "0x%02x 0x%05x\n", addr, odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_D, addr, RFREGOFFSETMASK))); + if (dm->rf_type > RF_3T3R) { + for (addr = 0x1a00; addr < 0x1aff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); } -} -void -phydm_enable_big_jump( - struct PHY_DM_STRUCT *p_dm_odm, - boolean state -) -{ -#if (RTL8822B_SUPPORT == 1) - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + for (addr = 0x1900; addr < 0x19ff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); - if (state == false) { - p_dm_odm->dm_dig_table.enable_adjust_big_jump = false; - odm_set_bb_reg(p_dm_odm, 0x8c8, 0xfe, ((p_dm_dig_table->big_jump_step3 << 5) | (p_dm_dig_table->big_jump_step2 << 3) | p_dm_dig_table->big_jump_step1)); - } else - p_dm_odm->dm_dig_table.enable_adjust_big_jump = true; -#endif -} + for (addr = 0x1c00; addr < 0x1cff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); -#if (RTL8822B_SUPPORT == 1) + for (addr = 0x1f00; addr < 0x1fff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); -void -phydm_show_rx_rate( - struct PHY_DM_STRUCT *p_dm_odm, - u32 *_used, - char *output, - u32 *_out_len -) -{ - u32 used = *_used; - u32 out_len = *_out_len; - - PHYDM_SNPRINTF((output + used, out_len - used, "=====Rx SU rate Statistics=====\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[0], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[1], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[2], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[3])); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[4], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[5], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[6], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[7])); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[8], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[9])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[10], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[11], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[12], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[13])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[14], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[15], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[16], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[17])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[18], p_dm_odm->phy_dbg_info.num_qry_vht_pkt[19])); - - PHYDM_SNPRINTF((output + used, out_len - used, "=====Rx MU rate Statistics=====\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS0 = %d, 1SS MCS1 = %d, 1SS MCS2 = %d, 1SS MCS 3 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[0], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[1], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[2], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[3])); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS4 = %d, 1SS MCS5 = %d, 1SS MCS6 = %d, 1SS MCS 7 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[4], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[5], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[6], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[7])); - PHYDM_SNPRINTF((output + used, out_len - used, "1SS MCS8 = %d, 1SS MCS9 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[8], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[9])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS0 = %d, 2SS MCS1 = %d, 2SS MCS2 = %d, 2SS MCS 3 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[10], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[11], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[12], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[13])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS4 = %d, 2SS MCS5 = %d, 2SS MCS6 = %d, 2SS MCS 7 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[14], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[15], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[16], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[17])); - PHYDM_SNPRINTF((output + used, out_len - used, "2SS MCS8 = %d, 2SS MCS9 = %d\n", - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[18], p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[19])); +rpt_reg: + *_used = used; + *_out_len = out_len; } #endif +void phydm_dump_bb_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; -struct _PHYDM_COMMAND { - char name[16]; - u8 id; -}; + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "BB==========\n"); -enum PHYDM_CMD_ID { - PHYDM_HELP, - PHYDM_DEMO, - PHYDM_RA, - PHYDM_PROFILE, - PHYDM_ANTDIV, - PHYDM_PATHDIV, - PHYDM_DEBUG, - PHYDM_FW_DEBUG, - PHYDM_SUPPORT_ABILITY, - PHYDM_GET_TXAGC, - PHYDM_SET_TXAGC, - PHYDM_SMART_ANT, - PHYDM_API, - PHYDM_TRX_PATH, - PHYDM_LA_MODE, - PHYDM_DUMP_REG, - PHYDM_MU_MIMO, - PHYDM_HANG, - PHYDM_BIG_JUMP, - PHYDM_SHOW_RXRATE, - PHYDM_NBI_EN, - PHYDM_CSI_MASK_EN, - PHYDM_DFS_DEBUG, - PHYDM_IQK, - PHYDM_NHM, - PHYDM_CLM, - PHYDM_BB_INFO, - PHYDM_TXBF, - PHYDM_PAUSE_DIG_EN, - PHYDM_H2C, - PHYDM_ANT_SWITCH, - PHYDM_DYNAMIC_RA_PATH, - PHYDM_PSD, - PHYDM_DEBUG_PORT, - PHYDM_HTSTF_CONTROL -}; + if (dm->support_ic_type & ODM_IC_11N_SERIES) +#if (ODM_IC_11N_SERIES_SUPPORT) + phydm_dump_bb_reg_n(dm, &used, output, &out_len); +#else + ; +#endif + else +#if (ODM_IC_11AC_SERIES_SUPPORT) + phydm_dump_bb_reg_ac(dm, &used, output, &out_len); +#else + ; +#endif -struct _PHYDM_COMMAND phy_dm_ary[] = { - {"-h", PHYDM_HELP}, /*do not move this element to other position*/ - {"demo", PHYDM_DEMO}, /*do not move this element to other position*/ - {"ra", PHYDM_RA}, - {"profile", PHYDM_PROFILE}, - {"antdiv", PHYDM_ANTDIV}, - {"pathdiv", PHYDM_PATHDIV}, - {"dbg", PHYDM_DEBUG}, - {"fw_dbg", PHYDM_FW_DEBUG}, - {"ability", PHYDM_SUPPORT_ABILITY}, - {"get_txagc", PHYDM_GET_TXAGC}, - {"set_txagc", PHYDM_SET_TXAGC}, - {"smtant", PHYDM_SMART_ANT}, - {"api", PHYDM_API}, - {"trxpath", PHYDM_TRX_PATH}, - {"lamode", PHYDM_LA_MODE}, - {"dumpreg", PHYDM_DUMP_REG}, - {"mu", PHYDM_MU_MIMO}, - {"hang", PHYDM_HANG}, - {"bigjump", PHYDM_BIG_JUMP}, - {"rxrate", PHYDM_SHOW_RXRATE}, - {"nbi", PHYDM_NBI_EN}, - {"csi_mask", PHYDM_CSI_MASK_EN}, - {"dfs", PHYDM_DFS_DEBUG}, - {"iqk", PHYDM_IQK}, - {"nhm", PHYDM_NHM}, - {"clm", PHYDM_CLM}, - {"bbinfo", PHYDM_BB_INFO}, - {"txbf", PHYDM_TXBF}, - {"pause_dig", PHYDM_PAUSE_DIG_EN}, - {"h2c", PHYDM_H2C}, - {"ant_switch", PHYDM_ANT_SWITCH}, - {"drp", PHYDM_DYNAMIC_RA_PATH}, - {"psd", PHYDM_PSD}, - {"dbgport", PHYDM_DEBUG_PORT}, - {"htstf", PHYDM_HTSTF_CONTROL} -}; + *_used = used; + *_out_len = out_len; +} -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ - -void -phydm_cmd_parser( - struct PHY_DM_STRUCT *p_dm_odm, - char input[][MAX_ARGV], - u32 input_num, - u8 flag, - char *output, - u32 out_len -) +void phydm_dump_rf_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - u32 used = 0; - u8 id = 0; - int var1[10] = {0}; - int i, input_idx = 0, phydm_ary_size; - char help[] = "-h"; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; + u32 reg = 0; - if (flag == 0) { - PHYDM_SNPRINTF((output + used, out_len - used, "GET, nothing to print\n")); - return; - } + /* @dump RF register */ + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "RF-A==========\n"); - PHYDM_SNPRINTF((output + used, out_len - used, "\n")); + for (addr = 0; addr < 0xFF; addr++) { + reg = odm_get_rf_reg(dm, RF_PATH_A, addr, RFREG_MASK); + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%02x 0x%05x\n", addr, reg); + } - /* Parsing Cmd ID */ - if (input_num) { +#ifdef PHYDM_COMPILE_ABOVE_2SS + if (dm->rf_type > RF_1T1R) { + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "RF-B==========\n"); - phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct _PHYDM_COMMAND); - for (i = 0; i < phydm_ary_size; i++) { - if (strcmp(phy_dm_ary[i].name, input[0]) == 0) { - id = phy_dm_ary[i].id; - break; - } - } - if (i == phydm_ary_size) { - PHYDM_SNPRINTF((output + used, out_len - used, "SET, command not found!\n")); - return; + for (addr = 0; addr < 0xFF; addr++) { + reg = odm_get_rf_reg(dm, RF_PATH_B, addr, RFREG_MASK); + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%02x 0x%05x\n", + addr, reg); } } +#endif - switch (id) { - - case PHYDM_HELP: - { - PHYDM_SNPRINTF((output + used, out_len - used, "BB cmd ==>\n")); - for (i = 0; i < phydm_ary_size - 2; i++) { +#ifdef PHYDM_COMPILE_ABOVE_3SS + if (dm->rf_type > RF_2T2R) { + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "RF-C==========\n"); - PHYDM_SNPRINTF((output + used, out_len - used, " %-5d: %s\n", i, phy_dm_ary[i + 2].name)); - /**/ + for (addr = 0; addr < 0xFF; addr++) { + reg = odm_get_rf_reg(dm, RF_PATH_C, addr, RFREG_MASK); + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%02x 0x%05x\n", + addr, reg); } } - break; +#endif - case PHYDM_DEMO: { /*echo demo 10 0x3a z abcde >cmd*/ - u32 directory = 0; +#ifdef PHYDM_COMPILE_ABOVE_4SS + if (dm->rf_type > RF_3T3R) { + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "RF-D==========\n"); -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) - char char_temp; -#else - u32 char_temp = ' '; + for (addr = 0; addr < 0xFF; addr++) { + reg = odm_get_rf_reg(dm, RF_PATH_D, addr, RFREG_MASK); + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%02x 0x%05x\n", + addr, reg); + } + } #endif - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory); - PHYDM_SNPRINTF((output + used, out_len - used, "Decimal value = %d\n", directory)); - PHYDM_SSCANF(input[2], DCMD_HEX, &directory); - PHYDM_SNPRINTF((output + used, out_len - used, "Hex value = 0x%x\n", directory)); - PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp); - PHYDM_SNPRINTF((output + used, out_len - used, "Char = %c\n", char_temp)); - PHYDM_SNPRINTF((output + used, out_len - used, "String = %s\n", input[4])); - } - break; + *_used = used; + *_out_len = out_len; +} - case PHYDM_RA: +void phydm_dump_mac_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + /* @dump MAC register */ + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "MAC==========\n"); - /*PHYDM_SNPRINTF((output + used, out_len - used, "new SET, RA_var[%d]= (( %d ))\n", i, var1[i]));*/ - input_idx++; - } - } + for (addr = 0; addr < 0x7ff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_RA_debug\n"));*/ -#if (defined(CONFIG_RA_DBG_CMD)) - odm_RA_debug((void *)p_dm_odm, (u32 *) var1); -#else - phydm_RA_debug_PCR(p_dm_odm, (u32 *)var1, &used, output, &out_len); -#endif - } + for (addr = 0x1000; addr < 0x17ff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); + *_used = used; + *_out_len = out_len; +} - break; +void phydm_dump_reg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; - case PHYDM_ANTDIV: + if (input[1]) + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "dumpreg {0:all, 1:BB, 2:RF, 3:MAC}\n"); + } else if (var1[0] == 0) { + phydm_dump_mac_reg(dm, &used, output, &out_len); + phydm_dump_bb_reg(dm, &used, output, &out_len); + phydm_dump_rf_reg(dm, &used, output, &out_len); + } else if (var1[0] == 1) { + phydm_dump_bb_reg(dm, &used, output, &out_len); + } else if (var1[0] == 2) { + phydm_dump_rf_reg(dm, &used, output, &out_len); + } else if (var1[0] == 3) { + phydm_dump_mac_reg(dm, &used, output, &out_len); + } - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i, var1[i]));*/ - input_idx++; - } - } + *_used = used; + *_out_len = out_len; +} - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - phydm_antdiv_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); -#endif - } +void phydm_enable_big_jump(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if (RTL8822B_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u32 dm_value[10] = {0}; + u8 i, input_idx = 0; + u32 val; + + if (!(dm->support_ic_type & ODM_RTL8822B)) + return; - break; + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + input_idx++; + } + } - case PHYDM_PATHDIV: + if (input_idx == 0) + return; - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + if (dm_value[0] == 0) { + dm->dm_dig_table.enable_adjust_big_jump = false; - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i, var1[i]));*/ - input_idx++; - } - } + val = (dig_t->big_jump_step3 << 5) | + (dig_t->big_jump_step2 << 3) | + dig_t->big_jump_step1; - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ -#if (defined(CONFIG_PATH_DIVERSITY)) - odm_pathdiv_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + odm_set_bb_reg(dm, R_0x8c8, 0xfe, val); + } else { + dm->dm_dig_table.enable_adjust_big_jump = true; + } #endif - } - - break; - - case PHYDM_DEBUG: +} - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); +void phydm_show_rx_rate(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if (RTL8822B_SUPPORT | RTL8821C_SUPPORT | RTL8814B_SUPPORT | RTL8195B_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + u32 used = *_used; + u32 out_len = *_out_len; + u32 var1[10] = {0}; + char help[] = "-h"; + u8 i, input_idx = 0; - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, Debug_var[%d]= (( %d ))\n", i, var1[i]));*/ - input_idx++; - } + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; } + } - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_debug_comp\n"));*/ - phydm_debug_trace(p_dm_odm, (u32 *)var1, &used, output, &out_len); - } + if (input_idx == 0) + return; + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1: show Rx rate, 0:reset counter}\n"); + *_used = used; + *_out_len = out_len; + return; - break; + } else if (var1[0] == 0) { + phydm_reset_rx_rate_distribution(dm); + *_used = used; + *_out_len = out_len; + return; + } - case PHYDM_FW_DEBUG: + /* @==Show SU Rate====================================================*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "=====Rx SU rate Statistics=====\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n", + dbg->num_qry_vht_pkt[0], dbg->num_qry_vht_pkt[1], + dbg->num_qry_vht_pkt[2], dbg->num_qry_vht_pkt[3], + dbg->num_qry_vht_pkt[4], dbg->num_qry_vht_pkt[5], + dbg->num_qry_vht_pkt[6], dbg->num_qry_vht_pkt[7], + dbg->num_qry_vht_pkt[8], dbg->num_qry_vht_pkt[9]); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n", + dbg->num_qry_vht_pkt[10], dbg->num_qry_vht_pkt[11], + dbg->num_qry_vht_pkt[12], dbg->num_qry_vht_pkt[13], + dbg->num_qry_vht_pkt[14], dbg->num_qry_vht_pkt[15], + dbg->num_qry_vht_pkt[16], dbg->num_qry_vht_pkt[17], + dbg->num_qry_vht_pkt[18], dbg->num_qry_vht_pkt[19]); + } + #endif + /* @==Show MU Rate====================================================*/ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) + PDM_SNPF(out_len, used, output + used, out_len - used, + "=====Rx MU rate Statistics=====\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[MU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n", + dbg->num_mu_vht_pkt[0], dbg->num_mu_vht_pkt[1], + dbg->num_mu_vht_pkt[2], dbg->num_mu_vht_pkt[3], + dbg->num_mu_vht_pkt[4], dbg->num_mu_vht_pkt[5], + dbg->num_mu_vht_pkt[6], dbg->num_mu_vht_pkt[7], + dbg->num_mu_vht_pkt[8], dbg->num_mu_vht_pkt[9]); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[MU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n", + dbg->num_mu_vht_pkt[10], dbg->num_mu_vht_pkt[11], + dbg->num_mu_vht_pkt[12], dbg->num_mu_vht_pkt[13], + dbg->num_mu_vht_pkt[14], dbg->num_mu_vht_pkt[15], + dbg->num_mu_vht_pkt[16], dbg->num_mu_vht_pkt[17], + dbg->num_mu_vht_pkt[18], dbg->num_mu_vht_pkt[19]); + } + #endif +#endif + *_used = used; + *_out_len = out_len; +#endif +} - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - input_idx++; - } - } +void phydm_per_tone_evm(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i, j; + u32 used = *_used; + u32 out_len = *_out_len; + u32 var1[4] = {0}; + u32 val, tone_num, round; + s8 rxevm_0, rxevm_1; + s32 avg_num, evm_tone_0[256] = {0}, evm_tone_1[256] = {0}; + s32 rxevm_sum_0, rxevm_sum_1; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + pr_debug("n series not support yet !\n"); + return; + } - if (input_idx >= 1) - phydm_fw_debug_trace(p_dm_odm, (u32 *)var1, &used, output, &out_len); + for (i = 0; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } - break; + avg_num = var1[0]; + round = var1[1]; - case PHYDM_SUPPORT_ABILITY: + if (!dm->is_linked) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "No Link !!\n"); - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + *_used = used; + *_out_len = out_len; - /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, support ablity_var[%d]= (( %d ))\n", i, var1[i]));*/ - input_idx++; - } - } + return; + } - if (input_idx >= 1) { - /*PHYDM_SNPRINTF((output+used, out_len-used, "support ablity\n"));*/ - phydm_support_ability_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); - } + pr_debug("ID=((%d)), BW=((%d)), fc=((CH-%d))\n", dm->curr_station_id, + 20 << *dm->band_width, *dm->channel); + pr_debug("avg_num =((%d)), round =((%d))\n", avg_num, round); +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + watchdog_stop(dm->priv); +#endif + for (j = 0; j < round; j++) { + pr_debug("\nround((%d))\n", (j + 1)); + if (*dm->band_width == CHANNEL_WIDTH_20) { + for (tone_num = 228; tone_num <= 255; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n", + (256 - tone_num), evm_tone_0[tone_num], + evm_tone_1[tone_num]); + } - break; + for (tone_num = 1; tone_num <= 28; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\n", + tone_num, evm_tone_0[tone_num], + evm_tone_1[tone_num]); + } + } else if (*dm->band_width == CHANNEL_WIDTH_40) { + for (tone_num = 198; tone_num <= 254; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n", + (256 - tone_num), evm_tone_0[tone_num], + evm_tone_1[tone_num]); + } - case PHYDM_SMART_ANT: + for (tone_num = 2; tone_num <= 58; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\n", + tone_num, evm_tone_0[tone_num], + evm_tone_1[tone_num]); + } + } else if (*dm->band_width == CHANNEL_WIDTH_80) { + for (tone_num = 134; tone_num <= 254; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n", + (256 - tone_num), evm_tone_0[tone_num], + evm_tone_1[tone_num]); + } - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - input_idx++; + for (tone_num = 2; tone_num <= 122; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(%-3d) RXEVM (1ss/2ss)=%d, %d\n", + tone_num, evm_tone_0[tone_num], + evm_tone_1[tone_num]); } } + } + *_used = used; + *_out_len = out_len; +} - if (input_idx >= 1) { -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) +void phydm_api_adjust(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + boolean is_enable_dbg_mode; + u8 central_ch, primary_ch_idx; + enum channel_width bw; - #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 - phydm_hl_smart_ant_debug_type2(p_dm_odm, &input[0], &used, output, &out_len, input_num); - #elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) - phydm_hl_smart_ant_debug(p_dm_odm, &input[0], &used, output, &out_len, input_num); - #endif -#endif - } +#ifdef PHYDM_COMMON_API_SUPPORT - break; + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en} {CH} {pr_ch 1/2/3/4/9/10} {0:20M,1:40M,2:80M}\n"); + goto out; + } - case PHYDM_API: -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) - { - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)) { - boolean is_enable_dbg_mode; - u8 central_ch, primary_ch_idx, bandwidth; - - for (i = 0; i < 4; i++) { - if (input[i + 1]) - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - } + if (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "This IC doesn't support PHYDM API function\n"); + goto out; + } - is_enable_dbg_mode = (boolean)var1[0]; - central_ch = (u8) var1[1]; - primary_ch_idx = (u8) var1[2]; - bandwidth = (enum odm_bw_e) var1[3]; - - if (is_enable_dbg_mode) { - p_dm_odm->is_disable_phy_api = false; - phydm_api_switch_bw_channel(p_dm_odm, central_ch, primary_ch_idx, (enum odm_bw_e) bandwidth); - p_dm_odm->is_disable_phy_api = true; - PHYDM_SNPRINTF((output + used, out_len - used, "central_ch = %d, primary_ch_idx = %d, bandwidth = %d\n", central_ch, primary_ch_idx, bandwidth)); - } else { - p_dm_odm->is_disable_phy_api = false; - PHYDM_SNPRINTF((output + used, out_len - used, "Disable API debug mode\n")); - } - } else - PHYDM_SNPRINTF((output + used, out_len - used, "This IC doesn't support PHYDM API function\n")); - } + for (i = 0; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + is_enable_dbg_mode = (boolean)var1[0]; + central_ch = (u8)var1[1]; + primary_ch_idx = (u8)var1[2]; + bw = (enum channel_width)var1[3]; + + if (is_enable_dbg_mode) { + dm->is_disable_phy_api = false; + phydm_api_switch_bw_channel(dm, central_ch, primary_ch_idx, bw); + dm->is_disable_phy_api = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "central_ch = %d, primary_ch_idx = %d, bw = %d\n", + central_ch, primary_ch_idx, bw); + } else { + dm->is_disable_phy_api = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable API debug mode\n"); + } +out: #else - PHYDM_SNPRINTF((output + used, out_len - used, "This IC doesn't support PHYDM API function\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "This IC doesn't support PHYDM API function\n"); #endif - break; - - case PHYDM_PROFILE: /*echo profile, >cmd*/ - phydm_basic_profile(p_dm_odm, &used, output, &out_len); - break; - case PHYDM_GET_TXAGC: - phydm_get_txagc(p_dm_odm, &used, output, &out_len); - break; + *_used = used; + *_out_len = out_len; +} - case PHYDM_SET_TXAGC: - { - boolean is_enable_dbg_mode; +void phydm_parameter_adjust(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - input_idx++; - } - } + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "1. X_cap = ((0x%x))\n", cfo_track->crystal_cap); - if ((strcmp(input[1], help) == 0)) { - PHYDM_SNPRINTF((output + used, out_len - used, "{En} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\n")); - /**/ + } else { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - } else { + if (var1[0] == 0) { + PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]); + phydm_set_crystal_cap(dm, (u8)var1[1]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "X_cap = ((0x%x))\n", cfo_track->crystal_cap); + } + } + *_used = used; + *_out_len = out_len; +} - is_enable_dbg_mode = (boolean)var1[0]; - if (is_enable_dbg_mode) { - p_dm_odm->is_disable_phy_api = false; - phydm_set_txagc(p_dm_odm, (u32 *)var1, &used, output, &out_len); - p_dm_odm->is_disable_phy_api = true; - } else { - p_dm_odm->is_disable_phy_api = false; - PHYDM_SNPRINTF((output + used, out_len - used, "Disable API debug mode\n")); - } +void phydm_ext_rf_element_ctrl(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val[10] = {0}; + u8 i = 0, input_idx = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]); + input_idx++; } } - break; - case PHYDM_TRX_PATH: + if (input_idx == 0) + return; - for (i = 0; i < 4; i++) { - if (input[i + 1]) - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - } -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) { - u8 tx_path, rx_path; - boolean is_enable_dbg_mode, is_tx2_path; - - is_enable_dbg_mode = (boolean)var1[0]; - tx_path = (u8) var1[1]; - rx_path = (u8) var1[2]; - is_tx2_path = (boolean) var1[3]; - - if (is_enable_dbg_mode) { - p_dm_odm->is_disable_phy_api = false; - phydm_api_trx_mode(p_dm_odm, (enum odm_rf_path_e) tx_path, (enum odm_rf_path_e) rx_path, is_tx2_path); - p_dm_odm->is_disable_phy_api = true; - PHYDM_SNPRINTF((output + used, out_len - used, "tx_path = 0x%x, rx_path = 0x%x, is_tx2_path = %d\n", tx_path, rx_path, is_tx2_path)); - } else { - p_dm_odm->is_disable_phy_api = false; - PHYDM_SNPRINTF((output + used, out_len - used, "Disable API debug mode\n")); - } - } else -#endif - phydm_config_trx_path(p_dm_odm, (u32 *)var1, &used, output, &out_len); + if (val[0] == 1) /*@ext switch*/ { + phydm_set_ext_switch(dm, val[1]); + } +} - break; +void phydm_print_dbgport(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 dbg_port_value = 0; + u8 val[32]; + u8 tmp = 0; + u8 i; + + if (strcmp(input[1], help) == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{dbg_port_idx}\n"); + goto out; + } - case PHYDM_LA_MODE: + PHYDM_SSCANF(input[1], DCMD_HEX, &var1[0]); -#if (PHYDM_LA_MODE_SUPPORT == 1) - p_dm_odm->support_ability &= ~(ODM_BB_FA_CNT); - phydm_lamode_trigger_setting(p_dm_odm, &input[0], &used, output, &out_len, input_num); - p_dm_odm->support_ability |= ODM_BB_FA_CNT; -#else - PHYDM_SNPRINTF((output + used, out_len - used, "This IC doesn't support LA mode\n")); -#endif + dm->debug_components |= ODM_COMP_API; + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, var1[0])) { + dbg_port_value = phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); - break; + for (i = 0; i < 32; i++) + val[i] = (u8)((dbg_port_value & BIT(i)) >> i); - case PHYDM_DUMP_REG: - { - u8 type = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dbg Port[0x%x] = ((0x%x))\n", var1[0], + dbg_port_value); - if (input[1]) { - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - type = (u8)var1[0]; + for (i = 4; i != 0; i--) { + tmp = 8 * (i - 1); + PDM_SNPF(out_len, used, output + used, out_len - used, + "val[%d:%d] = 8b'%d %d %d %d %d %d %d %d\n", + tmp + 7, tmp, val[tmp + 7], val[tmp + 6], + val[tmp + 5], val[tmp + 4], val[tmp + 3], + val[tmp + 2], val[tmp + 1], val[tmp + 0]); } - - if (type == 0) - phydm_dump_bb_reg(p_dm_odm, &used, output, &out_len); - else if (type == 1) - phydm_dump_all_reg(p_dm_odm, &used, output, &out_len); } - break; - - case PHYDM_MU_MIMO: -#if (RTL8822B_SUPPORT == 1) + dm->debug_components &= (~ODM_COMP_API); +out: + *_used = used; + *_out_len = out_len; +} - if (input[1]) - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - else - var1[0] = 0; +struct phydm_command { + char name[16]; + u8 id; +}; - if (var1[0] == 1) { - int index, ptr; - u32 dword_h, dword_l; - - PHYDM_SNPRINTF((output + used, out_len - used, "Get MU BFee CSI\n")); - odm_set_bb_reg(p_dm_odm, 0x9e8, BIT(17) | BIT16, 2); /*Read BFee*/ - odm_set_bb_reg(p_dm_odm, 0x1910, BIT(15), 1); /*Select BFee's CSI report*/ - odm_set_bb_reg(p_dm_odm, 0x19b8, BIT(6), 1); /*set as CSI report*/ - odm_set_bb_reg(p_dm_odm, 0x19a8, 0xFFFF, 0xFFFF); /*disable gated_clk*/ - - for (index = 0; index < 80; index++) { - ptr = index + 256; - if (ptr > 311) - ptr -= 312; - odm_set_bb_reg(p_dm_odm, 0x1910, 0x03FF0000, ptr); /*Select Address*/ - dword_h = odm_get_bb_reg(p_dm_odm, 0xF74, MASKDWORD); - dword_l = odm_get_bb_reg(p_dm_odm, 0xF5C, MASKDWORD); - if (index % 2 == 0) - PHYDM_SNPRINTF((output + used, out_len - used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - dword_l & MASKBYTE0, (dword_l & MASKBYTE1) >> 8, (dword_l & MASKBYTE2) >> 16, (dword_l & MASKBYTE3) >> 24, - dword_h & MASKBYTE0, (dword_h & MASKBYTE1) >> 8, (dword_h & MASKBYTE2) >> 16, (dword_h & MASKBYTE3) >> 24)); - else - PHYDM_SNPRINTF((output + used, out_len - used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - dword_l & MASKBYTE0, (dword_l & MASKBYTE1) >> 8, (dword_l & MASKBYTE2) >> 16, (dword_l & MASKBYTE3) >> 24, - dword_h & MASKBYTE0, (dword_h & MASKBYTE1) >> 8, (dword_h & MASKBYTE2) >> 16, (dword_h & MASKBYTE3) >> 24)); - } - } else if (var1[0] == 2) { - int index, ptr; - u32 dword_h, dword_l; - - PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); - PHYDM_SNPRINTF((output + used, out_len - used, "Get MU BFer's STA%d CSI\n", var1[1])); - odm_set_bb_reg(p_dm_odm, 0x9e8, BIT(24), 0); /*Read BFer*/ - odm_set_bb_reg(p_dm_odm, 0x9e8, BIT(25), 1); /*enable Read/Write RAM*/ - odm_set_bb_reg(p_dm_odm, 0x9e8, BIT(30) | BIT29 | BIT28, var1[1]); /*read which STA's CSI report*/ - odm_set_bb_reg(p_dm_odm, 0x1910, BIT(15), 0); /*select BFer's CSI*/ - odm_set_bb_reg(p_dm_odm, 0x19e0, 0x00003FC0, 0xFF); /*disable gated_clk*/ - - for (index = 0; index < 80; index++) { - ptr = index + 256; - if (ptr > 311) - ptr -= 312; - odm_set_bb_reg(p_dm_odm, 0x1910, 0x03FF0000, ptr); /*Select Address*/ - dword_h = odm_get_bb_reg(p_dm_odm, 0xF74, MASKDWORD); - dword_l = odm_get_bb_reg(p_dm_odm, 0xF5C, MASKDWORD); - if (index % 2 == 0) - PHYDM_SNPRINTF((output + used, out_len - used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - dword_l & MASKBYTE0, (dword_l & MASKBYTE1) >> 8, (dword_l & MASKBYTE2) >> 16, (dword_l & MASKBYTE3) >> 24, - dword_h & MASKBYTE0, (dword_h & MASKBYTE1) >> 8, (dword_h & MASKBYTE2) >> 16, (dword_h & MASKBYTE3) >> 24)); - else - PHYDM_SNPRINTF((output + used, out_len - used, "%02x %02x %02x %02x %02x %02x %02x %02x\n", - dword_l & MASKBYTE0, (dword_l & MASKBYTE1) >> 8, (dword_l & MASKBYTE2) >> 16, (dword_l & MASKBYTE3) >> 24, - dword_h & MASKBYTE0, (dword_h & MASKBYTE1) >> 8, (dword_h & MASKBYTE2) >> 16, (dword_h & MASKBYTE3) >> 24)); - - PHYDM_SNPRINTF((output + used, out_len - used, "ptr=%d : 0x%8x %8x\n", ptr, dword_h, dword_l)); - } +enum PHYDM_CMD_ID { + PHYDM_HELP, + PHYDM_DEMO, + PHYDM_RF_CMD, + PHYDM_DIG, + PHYDM_RA, + PHYDM_PROFILE, + PHYDM_ANTDIV, + PHYDM_PATHDIV, + PHYDM_DEBUG, + PHYDM_FW_DEBUG, + PHYDM_SUPPORT_ABILITY, + PHYDM_GET_TXAGC, + PHYDM_SET_TXAGC, + PHYDM_SMART_ANT, + PHYDM_API, + PHYDM_TRX_PATH, + PHYDM_LA_MODE, + PHYDM_DUMP_REG, + PHYDM_AUTO_DBG, + PHYDM_BIG_JUMP, + PHYDM_SHOW_RXRATE, + PHYDM_NBI_EN, + PHYDM_CSI_MASK_EN, + PHYDM_DFS_DEBUG, + PHYDM_NHM, + PHYDM_CLM, + PHYDM_FAHM, + PHYDM_ENV_MNTR, + PHYDM_BB_INFO, + PHYDM_TXBF, + PHYDM_H2C, + PHYDM_EXT_RF_E_CTRL, + PHYDM_ADAPTIVE_SOML, + PHYDM_PSD, + PHYDM_DEBUG_PORT, + PHYDM_DIS_HTSTF_CONTROL, + PHYDM_TUNE_PARAMETER, + PHYDM_ADAPTIVITY_DEBUG, + PHYDM_DIS_DYM_ANT_WEIGHTING, + PHYDM_FORECE_PT_STATE, + PHYDM_DIS_RXHP_CTR, + PHYDM_STA_INFO, + PHYDM_PAUSE_FUNC, + PHYDM_PER_TONE_EVM, + PHYDM_DYN_TXPWR, + PHYDM_LNA_SAT +}; - } -#endif - break; +struct phydm_command phy_dm_ary[] = { + {"-h", PHYDM_HELP}, /*@do not move this element to other position*/ + {"demo", PHYDM_DEMO}, /*@do not move this element to other position*/ + {"rf", PHYDM_RF_CMD}, + {"dig", PHYDM_DIG}, + {"ra", PHYDM_RA}, + {"profile", PHYDM_PROFILE}, + {"antdiv", PHYDM_ANTDIV}, + {"pathdiv", PHYDM_PATHDIV}, + {"dbg", PHYDM_DEBUG}, + {"fw_dbg", PHYDM_FW_DEBUG}, + {"ability", PHYDM_SUPPORT_ABILITY}, + {"get_txagc", PHYDM_GET_TXAGC}, + {"set_txagc", PHYDM_SET_TXAGC}, + {"smtant", PHYDM_SMART_ANT}, + {"api", PHYDM_API}, + {"trxpath", PHYDM_TRX_PATH}, + {"lamode", PHYDM_LA_MODE}, + {"dumpreg", PHYDM_DUMP_REG}, + {"auto_dbg", PHYDM_AUTO_DBG}, + {"bigjump", PHYDM_BIG_JUMP}, + {"rxrate", PHYDM_SHOW_RXRATE}, + {"nbi", PHYDM_NBI_EN}, + {"csi_mask", PHYDM_CSI_MASK_EN}, + {"dfs", PHYDM_DFS_DEBUG}, + {"nhm", PHYDM_NHM}, + {"clm", PHYDM_CLM}, + {"fahm", PHYDM_FAHM}, + {"env_mntr", PHYDM_ENV_MNTR}, + {"bbinfo", PHYDM_BB_INFO}, + {"txbf", PHYDM_TXBF}, + {"h2c", PHYDM_H2C}, + {"ext_rfe", PHYDM_EXT_RF_E_CTRL}, + {"soml", PHYDM_ADAPTIVE_SOML}, + {"psd", PHYDM_PSD}, + {"dbgport", PHYDM_DEBUG_PORT}, + {"dis_htstf", PHYDM_DIS_HTSTF_CONTROL}, + {"tune_para", PHYDM_TUNE_PARAMETER}, + {"adapt_debug", PHYDM_ADAPTIVITY_DEBUG}, + {"dis_dym_ant_wgt", PHYDM_DIS_DYM_ANT_WEIGHTING}, + {"force_pt_state", PHYDM_FORECE_PT_STATE}, + {"dis_drxhp", PHYDM_DIS_RXHP_CTR}, + {"sta_info", PHYDM_STA_INFO}, + {"pause", PHYDM_PAUSE_FUNC}, + {"evm", PHYDM_PER_TONE_EVM}, + {"dyn_txpwr", PHYDM_DYN_TXPWR}, + {"lna_sat", PHYDM_LNA_SAT} }; + +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ + +void phydm_cmd_parser(struct dm_struct *dm, char input[][MAX_ARGV], + u32 input_num, u8 flag, char *output, u32 out_len) +{ +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + u32 used = 0; + u8 id = 0; + u32 var1[10] = {0}; + u32 i; + u32 phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct phydm_command); - case PHYDM_BIG_JUMP: - { -#if (RTL8822B_SUPPORT == 1) - if (input[1]) { - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - phydm_enable_big_jump(p_dm_odm, (boolean)(var1[0])); - } else - PHYDM_SNPRINTF((output + used, out_len - used, "unknown command!\n")); -#else - PHYDM_SNPRINTF((output + used, out_len - used, "The command is only for 8822B!\n")); -#endif - break; + if (flag == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "GET, nothing to print\n"); + return; } - case PHYDM_HANG: - phydm_bb_rx_hang_info(p_dm_odm, &used, output, &out_len); - break; - - case PHYDM_SHOW_RXRATE: -#if (RTL8822B_SUPPORT == 1) - { - u8 rate_idx; - - if (input[1]) - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - - if (var1[0] == 1) - phydm_show_rx_rate(p_dm_odm, &used, output, &out_len); - else { - PHYDM_SNPRINTF((output + used, out_len - used, "Reset Rx rate counter\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, "\n"); - for (rate_idx = 0; rate_idx < 40; rate_idx++) { - p_dm_odm->phy_dbg_info.num_qry_vht_pkt[rate_idx] = 0; - p_dm_odm->phy_dbg_info.num_qry_mu_vht_pkt[rate_idx] = 0; - } - } - } -#endif - break; - - case PHYDM_NBI_EN: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - input_idx++; + /* Parsing Cmd ID */ + if (input_num) { + for (i = 0; i < phydm_ary_size; i++) { + if (strcmp(phy_dm_ary[i].name, input[0]) == 0) { + id = phy_dm_ary[i].id; + break; } } - - if (input_idx >= 1) { - - phydm_api_debug(p_dm_odm, PHYDM_API_NBI, (u32 *)var1, &used, output, &out_len); - /**/ + if (i == phydm_ary_size) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "PHYDM command not found!\n"); + return; } + } + switch (id) { + case PHYDM_HELP: { + PDM_SNPF(out_len, used, output + used, out_len - used, + "BB cmd ==>\n"); - break; - - case PHYDM_CSI_MASK_EN: - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - input_idx++; - } - } - - if (input_idx >= 1) { + for (i = 0; i < phydm_ary_size - 2; i++) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-5d: %s\n", i, phy_dm_ary[i + 2].name); + } break; - phydm_api_debug(p_dm_odm, PHYDM_API_CSI_MASK, (u32 *)var1, &used, output, &out_len); - /**/ - } + case PHYDM_DEMO: { /*@echo demo 10 0x3a z abcde >cmd*/ + u32 directory = 0; + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) + char char_temp; + #else + u32 char_temp = ' '; + #endif + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Decimal value = %d\n", directory); + PHYDM_SSCANF(input[2], DCMD_HEX, &directory); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Hex value = 0x%x\n", directory); + PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Char = %c\n", char_temp); + PDM_SNPF(out_len, used, output + used, out_len - used, + "String = %s\n", input[4]); + } break; + case PHYDM_RF_CMD: + halrf_cmd_parser(dm, input, &used, output, &out_len, input_num); break; - case PHYDM_DFS_DEBUG: -#ifdef CONFIG_PHYDM_DFS_MASTER - { - u32 var[4] = {0}; - - for (i = 0; i < 4; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var[i]); - input_idx++; - } - } - - if (input_idx >= 1) - phydm_dfs_debug(p_dm_odm, var, &used, output, &out_len); - } -#endif + case PHYDM_DIG: + phydm_dig_debug(dm, input, &used, output, &out_len); break; - case PHYDM_IQK: -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_iq_calibrate(p_dm_odm->priv); - PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n")); -#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PHY_IQCalibrate(p_dm_odm->adapter, false); - PHYDM_SNPRINTF((output + used, out_len - used, "IQK !!\n")); -#endif + case PHYDM_RA: + phydm_ra_debug(dm, input, &used, output, &out_len); break; - case PHYDM_NHM: - { - u8 target_rssi; - u32 value32; - u16 nhm_period = 0xC350; /* 200ms */ - u8 IGI; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - - if (input_num == 1) { - - ccx_info->echo_NHM_en = false; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger NHM: echo nhm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Exclude CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger NHM: echo nhm 2\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Include CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get NHM results: echo nhm 3\n")); - - return; - } - - /* NMH trigger */ - if ((var1[0] <= 2) && (var1[0] != 0)) { - - ccx_info->echo_NHM_en = true; - ccx_info->echo_IGI = (u8)odm_get_bb_reg(p_dm_odm, 0xC50, MASKBYTE0); - - target_rssi = ccx_info->echo_IGI - 10; - - ccx_info->NHM_th[0] = (target_rssi - 15 + 10) * 2; - - for (i = 1; i <= 10; i++) - ccx_info->NHM_th[i] = ccx_info->NHM_th[0] + 6 * i; + case PHYDM_ANTDIV: + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + phydm_antdiv_debug(dm, input, &used, output, &out_len); + #endif + break; - /* 4 1. store previous NHM setting */ - phydm_nhm_setting(p_dm_odm, STORE_NHM_SETTING); + case PHYDM_PATHDIV: + #if (defined(CONFIG_PATH_DIVERSITY)) + phydm_pathdiv_debug(dm, input, &used, output, &out_len); + #endif + break; - /* 4 2. Set NHM period, 0x990[31:16]=0xC350, Time duration for NHM unit: 4us, 0xC350=200ms */ - ccx_info->NHM_period = nhm_period; + case PHYDM_DEBUG: + phydm_debug_trace(dm, input, &used, output, &out_len); + break; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Monitor NHM for %d us", nhm_period * 4)); + case PHYDM_FW_DEBUG: + phydm_fw_debug_trace(dm, input, &used, output, &out_len); + break; - /* 4 3. Set NHM inexclude_txon, inexclude_cca, ccx_en */ + case PHYDM_SUPPORT_ABILITY: + phydm_supportability_en(dm, input, &used, output, &out_len); + break; + case PHYDM_SMART_ANT: + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - ccx_info->nhm_inexclude_cca = (var1[0] == 1) ? NHM_EXCLUDE_CCA : NHM_INCLUDE_CCA; - ccx_info->nhm_inexclude_txon = NHM_EXCLUDE_TXON; + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + phydm_hl_smt_ant_dbg_type2(dm, input, &used, output, &out_len); + #elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) + phydm_hl_smart_ant_debug(dm, input, &used, output, &out_len); + #endif - phydm_nhm_setting(p_dm_odm, SET_NHM_SETTING); + #elif (defined(CONFIG_CUMITEK_SMART_ANTENNA)) + phydm_cumitek_smt_ant_debug(dm, input, &used, output, &out_len); + #endif - for (i = 0; i <= 10; i++) { + break; - if (i == 5) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x, echo_IGI = 0x%x", i, ccx_info->NHM_th[i], ccx_info->echo_IGI)); - else if (i == 10) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x\n", i, ccx_info->NHM_th[i])); - else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n NHM_th[%d] = 0x%x", i, ccx_info->NHM_th[i])); - } + case PHYDM_API: + phydm_api_adjust(dm, input, &used, output, &out_len); + break; - /* 4 4. Trigger NHM */ - phydm_nhm_trigger(p_dm_odm); + case PHYDM_PROFILE: + phydm_basic_profile(dm, &used, output, &out_len); + break; - } + case PHYDM_GET_TXAGC: + phydm_get_txagc(dm, &used, output, &out_len); + break; - /*Get NHM results*/ - else if (var1[0] == 3) { + case PHYDM_SET_TXAGC: + phydm_set_txagc_dbg(dm, input, &used, output, &out_len); + break; - IGI = (u8)odm_get_bb_reg(p_dm_odm, 0xC50, MASKBYTE0); + case PHYDM_TRX_PATH: + phydm_config_trx_path(dm, input, &used, output, &out_len); + break; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Cur_IGI = 0x%x", IGI)); + case PHYDM_LA_MODE: + #if (PHYDM_LA_MODE_SUPPORT) + phydm_lamode_trigger_cmd(dm, input, &used, output, &out_len); + #endif + break; - phydm_get_nhm_result(p_dm_odm); + case PHYDM_DUMP_REG: + phydm_dump_reg(dm, input, &used, output, &out_len); + break; - /* 4 Resotre NHM setting */ - phydm_nhm_setting(p_dm_odm, RESTORE_NHM_SETTING); + case PHYDM_BIG_JUMP: + phydm_enable_big_jump(dm, input, &used, output, &out_len); + break; - for (i = 0; i <= 11; i++) { + case PHYDM_AUTO_DBG: + #ifdef PHYDM_AUTO_DEGBUG + phydm_auto_dbg_console(dm, input, &used, output, &out_len); + #endif + break; - if (i == 5) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d, echo_IGI = 0x%x", i, ccx_info->NHM_result[i], ccx_info->echo_IGI)); - else if (i == 11) - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d\n", i, ccx_info->NHM_result[i])); - else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n nhm_result[%d] = %d", i, ccx_info->NHM_result[i])); - } + case PHYDM_SHOW_RXRATE: + phydm_show_rx_rate(dm, input, &used, output, &out_len); + break; - ccx_info->echo_NHM_en = false; - } else { + case PHYDM_NBI_EN: + phydm_nbi_debug(dm, input, &used, output, &out_len); + break; - ccx_info->echo_NHM_en = false; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger NHM: echo nhm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Exclude CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger NHM: echo nhm 2\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r (Include CCA)\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get NHM results: echo nhm 3\n")); + case PHYDM_CSI_MASK_EN: + phydm_csi_debug(dm, input, &used, output, &out_len); + break; - return; - } + case PHYDM_DFS_DEBUG: { + #ifdef CONFIG_PHYDM_DFS_MASTER + phydm_dfs_debug(dm, input, &used, output, &out_len); + #endif + break; } - break; - - case PHYDM_CLM: - { - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - - /* PHYDM_SNPRINTF((output + used, out_len - used, "\r\n input_num = %d\n", input_num)); */ - - if (input_num == 1) { - - ccx_info->echo_CLM_en = false; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Trigger CLM: echo clm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get CLM results: echo clm 2\n")); - return; - } - - /* Set & trigger CLM */ - if (var1[0] == 1) { - ccx_info->echo_CLM_en = true; - ccx_info->CLM_period = 0xC350; /*100ms*/ - phydm_clm_setting(p_dm_odm); - phydm_clm_trigger(p_dm_odm); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n Monitor CLM for 200ms\n")); - } - - /* Get CLM results */ - else if (var1[0] == 2) { + case PHYDM_NHM: + #ifdef NHM_SUPPORT + phydm_nhm_dbg(dm, input, &used, output, &out_len); + #endif + break; - ccx_info->echo_CLM_en = false; - phydm_get_cl_mresult(p_dm_odm); - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n CLM_result = %d us\n", ccx_info->CLM_result * 4)); + case PHYDM_CLM: + #ifdef CLM_SUPPORT + phydm_clm_dbg(dm, input, &used, output, &out_len); + #endif + break; - } else { + #ifdef FAHM_SUPPORT + case PHYDM_FAHM: + phydm_fahm_dbg(dm, input, &used, output, &out_len); + break; + #endif - ccx_info->echo_CLM_en = false; - PHYDM_SNPRINTF((output + used, out_len - used, "\n\r Error command !\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Trigger CLM: echo clm 1\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "\r Get CLM results: echo clm 2\n")); - } - } - break; + case PHYDM_ENV_MNTR: + phydm_env_mntr_dbg(dm, input, &used, output, &out_len); + break; case PHYDM_BB_INFO: - { - s32 value32 = 0; - - phydm_bb_debug_info(p_dm_odm, &used, output, &out_len); + phydm_bb_hw_dbg_info(dm, input, &used, output, &out_len); + break; - if (p_dm_odm->support_ic_type & ODM_RTL8822B && input[1]) { - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - odm_set_bb_reg(p_dm_odm, 0x1988, 0x003fff00, var1[0]); - value32 = odm_get_bb_reg(p_dm_odm, 0xf84, MASKDWORD); - value32 = (value32 & 0xff000000) >> 24; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n %-35s = condition num = %d, subcarriers = %d\n", "Over condition num subcarrier", var1[0], value32)); - odm_set_bb_reg(p_dm_odm, 0x1988, BIT(22), 0x0); /*disable report condition number*/ - } - } - break; + case PHYDM_TXBF: { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (BEAMFORMING_SUPPORT) + struct _RT_BEAMFORMING_INFO *beamforming_info = NULL; - case PHYDM_TXBF: - { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (BEAMFORMING_SUPPORT == 1) - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; + beamforming_info = &dm->beamforming_info; PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); if (var1[0] == 0) { - p_beamforming_info->apply_v_matrix = false; - p_beamforming_info->snding3ss = true; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n dont apply V matrix and 3SS 789 snding\n")); + beamforming_info->apply_v_matrix = false; + beamforming_info->snding3ss = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n dont apply V matrix and 3SS 789 snding\n"); } else if (var1[0] == 1) { - p_beamforming_info->apply_v_matrix = true; - p_beamforming_info->snding3ss = true; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n apply V matrix and 3SS 789 snding\n")); + beamforming_info->apply_v_matrix = true; + beamforming_info->snding3ss = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n apply V matrix and 3SS 789 snding\n"); } else if (var1[0] == 2) { - p_beamforming_info->apply_v_matrix = true; - p_beamforming_info->snding3ss = false; - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n default txbf setting\n")); + beamforming_info->apply_v_matrix = true; + beamforming_info->snding3ss = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n default txbf setting\n"); } else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n unknown cmd!!\n")); -#else - PHYDM_SNPRINTF((output + used, out_len - used, "\r\n no TxBF !!\n")); -#endif -#endif - } - break; - - case PHYDM_PAUSE_DIG_EN: - - - for (i = 0; i < 5; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - input_idx++; - } - } + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n unknown cmd!!\n"); + #endif + #endif + } break; - if (input_idx >= 1) { - if (var1[0] == 0) { - odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_7, (u8)var1[1]); - PHYDM_SNPRINTF((output + used, out_len - used, "Set IGI_value = ((%x))\n", var1[1])); - } else if (var1[0] == 1) { - odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_7, (u8)var1[1]); - PHYDM_SNPRINTF((output + used, out_len - used, "Resume IGI_value\n")); - } else - PHYDM_SNPRINTF((output + used, out_len - used, "echo (1:pause, 2resume) (IGI_value)\n")); - } + case PHYDM_H2C: + phydm_h2C_debug(dm, input, &used, output, &out_len); + break; + case PHYDM_EXT_RF_E_CTRL: + phydm_ext_rf_element_ctrl(dm, input, &used, output, &out_len); break; - case PHYDM_H2C: + case PHYDM_ADAPTIVE_SOML: + #ifdef CONFIG_ADAPTIVE_SOML + phydm_soml_debug(dm, input, &used, output, &out_len); + #endif + break; - for (i = 0; i < 8; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); - input_idx++; - } - } + case PHYDM_PSD: - if (input_idx >= 1) - phydm_h2C_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + #ifdef CONFIG_PSD_TOOL + phydm_psd_debug(dm, input, &used, output, &out_len); + #endif + break; + case PHYDM_DEBUG_PORT: + phydm_print_dbgport(dm, input, &used, output, &out_len); break; - case PHYDM_ANT_SWITCH: + case PHYDM_DIS_HTSTF_CONTROL: { + if (input[1]) + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - for (i = 0; i < 8; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - input_idx++; - } + if (var1[0] == 1) { + /* setting being false is for debug */ + dm->bhtstfdisabled = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dynamic HT-STF Gain Control is Disable\n"); + } else { + /* @default setting should be true, + * always be dynamic control + */ + dm->bhtstfdisabled = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dynamic HT-STF Gain Control is Enable\n"); } + } break; - if (input_idx >= 1) { + case PHYDM_TUNE_PARAMETER: + phydm_parameter_adjust(dm, input, &used, output, &out_len); + break; -#if (RTL8821A_SUPPORT == 1) - phydm_set_ext_switch(p_dm_odm, (u32 *)var1, &used, output, &out_len); -#else - PHYDM_SNPRINTF((output + used, out_len - used, "Not Support IC")); -#endif - } + case PHYDM_ADAPTIVITY_DEBUG: + #ifdef PHYDM_SUPPORT_ADAPTIVITY + phydm_adaptivity_debug(dm, input, &used, output, &out_len); + #endif + break; + case PHYDM_DIS_DYM_ANT_WEIGHTING: + #ifdef DYN_ANT_WEIGHTING_SUPPORT + phydm_ant_weight_dbg(dm, input, &used, output, &out_len); + #endif + break; + case PHYDM_FORECE_PT_STATE: { + #ifdef PHYDM_POWER_TRAINING_SUPPORT + phydm_pow_train_debug(dm, input, &used, output, &out_len); + #endif break; + } - case PHYDM_DYNAMIC_RA_PATH: + case PHYDM_DIS_RXHP_CTR: { + if (input[1]) + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); -#if (CONFIG_DYNAMIC_RX_PATH == 1) - for (i = 0; i < 8; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - input_idx++; - } + if (var1[0] == 1) { + /* the setting being on is at debug mode to disconnect + * RxHP seeting with SoML on/odd + */ + dm->disrxhpsoml = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dynamic RxHP Control with SoML on/off is Disable\n"); + } else if (var1[0] == 0) { + /* @default setting, + * RxHP setting will follow SoML on/off setting + */ + dm->disrxhpsoml = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dynamic RxHP Control with SoML on/off is Enable\n"); + } else { + dm->disrxhpsoml = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Default Setting, Dynamic RxHP Control with SoML on/off is Enable\n"); } + } break; - if (input_idx >= 1) - phydm_drp_debug(p_dm_odm, (u32 *)var1, &used, output, &out_len); + case PHYDM_STA_INFO: + phydm_show_sta_info(dm, input, &used, output, &out_len); + break; -#else - PHYDM_SNPRINTF((output + used, out_len - used, "Not Support IC")); -#endif + case PHYDM_PAUSE_FUNC: + phydm_pause_func_console(dm, input, &used, output, &out_len); + break; + case PHYDM_PER_TONE_EVM: + phydm_per_tone_evm(dm, input, &used, output, &out_len); break; - case PHYDM_PSD: + #ifdef CONFIG_DYNAMIC_TX_TWR + case PHYDM_DYN_TXPWR: + phydm_dtp_debug(dm, input, &used, output, &out_len); + break; + #endif - #if (CONFIG_PSD_TOOL== 1) - phydm_psd_debug(p_dm_odm, &input[0], &used, output, &out_len, input_num); + case PHYDM_LNA_SAT: + #ifdef PHYDM_LNA_SAT_CHK_SUPPORT + phydm_lna_sat_debug(dm, input, &used, output, &out_len); #endif - break; - - case PHYDM_DEBUG_PORT: - { - u32 dbg_port_value; - - PHYDM_SSCANF(input[1], DCMD_HEX, &var1[0]); - - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, var1[0])) {/*set debug port to 0x0*/ - dbg_port_value = phydm_get_bb_dbg_port_value(p_dm_odm); - phydm_release_bb_dbg_port(p_dm_odm); - - PHYDM_SNPRINTF((output + used, out_len - used, "Debug Port[0x%x] = ((0x%x))\n", var1[1], dbg_port_value)); - } - } - break; - - case PHYDM_HTSTF_CONTROL: - { - if (input[1]) - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - - if (var1[0] == 1) { - /* phydm_dynamic_switch_htstf_mumimo_8822b(p_dm_odm);*/ - p_dm_odm->bhtstfenabled = TRUE; - PHYDM_SNPRINTF((output + used, out_len - used, "Dynamic HT-STF Gain Control is Enable\n")); - } - else { - p_dm_odm->bhtstfenabled = FALSE; - PHYDM_SNPRINTF((output + used, out_len - used, "Dynamic HT-STF Gain Control is Disable\n")); - } - } - break; default: - PHYDM_SNPRINTF((output + used, out_len - used, "SET, unknown command!\n")); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Do not support this command\n"); break; - } -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ } -#ifdef __ECOS +#if defined __ECOS || defined __ICCARM__ char *strsep(char **s, const char *ct) { char *sbegin = *s; char *end; - if (sbegin == NULL) + if (!sbegin) return NULL; end = strpbrk(sbegin, ct); @@ -2885,317 +4130,365 @@ char *strsep(char **s, const char *ct) } #endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) -s32 -phydm_cmd( - struct PHY_DM_STRUCT *p_dm_odm, - char *input, - u32 in_len, - u8 flag, - char *output, - u32 out_len -) +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP | ODM_IOT)) +s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag, + char *output, u32 out_len) { char *token; - u32 argc = 0; - char argv[MAX_ARGC][MAX_ARGV]; + u32 argc = 0; + char argv[MAX_ARGC][MAX_ARGV]; do { token = strsep(&input, ", "); if (token) { strcpy(argv[argc], token); argc++; - } else + } else { break; + } } while (argc < MAX_ARGC); if (argc == 1) argv[0][strlen(argv[0]) - 1] = '\0'; - phydm_cmd_parser(p_dm_odm, argv, argc, flag, output, out_len); + phydm_cmd_parser(dm, argv, argc, flag, output, out_len); return 0; } #endif - -void -phydm_fw_trace_handler( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len -) +void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; - /*u8 debug_trace_11byte[60];*/ - u8 freg_num, c2h_seq, buf_0 = 0; + /*@u8 debug_trace_11byte[60];*/ + u8 freg_num, c2h_seq, buf_0 = 0; - if (!(p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES)) + if (!(dm->support_ic_type & PHYDM_IC_3081_SERIES)) return; - if (cmd_len > 12) + if (cmd_len > 12 || cmd_len == 0) { + pr_debug("[Warning] Error C2H cmd_len=%d\n", cmd_len); return; + } buf_0 = cmd_buf[0]; freg_num = (buf_0 & 0xf); c2h_seq = (buf_0 & 0xf0) >> 4; - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] freg_num = (( %d )), c2h_seq = (( %d ))\n", freg_num,c2h_seq ));*/ - - /*strncpy(debug_trace_11byte,&cmd_buf[1],(cmd_len-1));*/ - /*debug_trace_11byte[cmd_len-1] = '\0';*/ - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] %s\n", debug_trace_11byte));*/ - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] cmd_len = (( %d ))\n", cmd_len));*/ - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] c2h_cmd_start = (( %d ))\n", p_dm_odm->c2h_cmd_start));*/ - + #if 0 + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW debug message] freg_num = (( %d )), c2h_seq=(( %d ))\n", + freg_num, c2h_seq); + + strncpy(debug_trace_11byte, &cmd_buf[1], (cmd_len - 1)); + debug_trace_11byte[cmd_len - 1] = '\0'; + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] %s\n", + debug_trace_11byte); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] cmd_len = (( %d ))\n", + cmd_len); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] c2h_cmd_start=((%d))\n", + dm->c2h_cmd_start); + + PHYDM_DBG(dm, DBG_FW_TRACE, "pre_seq = (( %d )), current_seq=((%d))\n", + dm->pre_c2h_seq, c2h_seq); + PHYDM_DBG(dm, DBG_FW_TRACE, "fw_buff_is_enpty = (( %d ))\n", + dm->fw_buff_is_enpty); + #endif - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("pre_seq = (( %d )), current_seq = (( %d ))\n", p_dm_odm->pre_c2h_seq, c2h_seq));*/ - /*ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("fw_buff_is_enpty = (( %d ))\n", p_dm_odm->fw_buff_is_enpty));*/ - - if ((c2h_seq != p_dm_odm->pre_c2h_seq) && p_dm_odm->fw_buff_is_enpty == false) { - p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue Overflow] %s\n", p_dm_odm->fw_debug_trace)); - p_dm_odm->c2h_cmd_start = 0; + if (c2h_seq != dm->pre_c2h_seq && dm->fw_buff_is_enpty == false) { + dm->fw_debug_trace[dm->c2h_cmd_start] = '\0'; + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW Dbg Queue Overflow] %s\n", + dm->fw_debug_trace); + dm->c2h_cmd_start = 0; } - if ((cmd_len - 1) > (60 - p_dm_odm->c2h_cmd_start)) { - p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue error: wrong C2H length] %s\n", p_dm_odm->fw_debug_trace)); - p_dm_odm->c2h_cmd_start = 0; + if ((cmd_len - 1) > (60 - dm->c2h_cmd_start)) { + dm->fw_debug_trace[dm->c2h_cmd_start] = '\0'; + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW Dbg Queue error: wrong C2H length] %s\n", + dm->fw_debug_trace); + dm->c2h_cmd_start = 0; return; } - strncpy((char *)&(p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start]), (char *)&cmd_buf[1], (cmd_len - 1)); - p_dm_odm->c2h_cmd_start += (cmd_len - 1); - p_dm_odm->fw_buff_is_enpty = false; + strncpy((char *)&dm->fw_debug_trace[dm->c2h_cmd_start], + (char *)&cmd_buf[1], (cmd_len - 1)); + dm->c2h_cmd_start += (cmd_len - 1); + dm->fw_buff_is_enpty = false; - if (freg_num == 0 || p_dm_odm->c2h_cmd_start >= 60) { - if (p_dm_odm->c2h_cmd_start < 60) - p_dm_odm->fw_debug_trace[p_dm_odm->c2h_cmd_start] = '\0'; + if (freg_num == 0 || dm->c2h_cmd_start >= 60) { + if (dm->c2h_cmd_start < 60) + dm->fw_debug_trace[dm->c2h_cmd_start] = '\0'; else - p_dm_odm->fw_debug_trace[59] = '\0'; + dm->fw_debug_trace[59] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", p_dm_odm->fw_debug_trace)); - /*dbg_print("[FW DBG Msg] %s\n", p_dm_odm->fw_debug_trace);*/ - p_dm_odm->c2h_cmd_start = 0; - p_dm_odm->fw_buff_is_enpty = true; + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s\n", + dm->fw_debug_trace); +#if 0 + /*@dbg_print("[FW DBG Msg] %s\n", dm->fw_debug_trace);*/ +#endif + dm->c2h_cmd_start = 0; + dm->fw_buff_is_enpty = true; } - p_dm_odm->pre_c2h_seq = c2h_seq; -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ + dm->pre_c2h_seq = c2h_seq; +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ } -void -phydm_fw_trace_handler_code( - void *p_dm_void, - u8 *buffer, - u8 cmd_len -) +void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 function = buffer[0]; - u8 dbg_num = buffer[1]; - u16 content_0 = (((u16)buffer[3]) << 8) | ((u16)buffer[2]); - u16 content_1 = (((u16)buffer[5]) << 8) | ((u16)buffer[4]); - u16 content_2 = (((u16)buffer[7]) << 8) | ((u16)buffer[6]); - u16 content_3 = (((u16)buffer[9]) << 8) | ((u16)buffer[8]); - u16 content_4 = (((u16)buffer[11]) << 8) | ((u16)buffer[10]); +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 function = buffer[0]; + u8 dbg_num = buffer[1]; + u16 content_0 = (((u16)buffer[3]) << 8) | ((u16)buffer[2]); + u16 content_1 = (((u16)buffer[5]) << 8) | ((u16)buffer[4]); + u16 content_2 = (((u16)buffer[7]) << 8) | ((u16)buffer[6]); + u16 content_3 = (((u16)buffer[9]) << 8) | ((u16)buffer[8]); + u16 content_4 = (((u16)buffer[11]) << 8) | ((u16)buffer[10]); if (cmd_len > 12) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Msg] Invalid cmd length (( %d )) >12\n", cmd_len)); - - /* ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW Msg] Func=((%d)), num=((%d)), ct_0=((%d)), ct_1=((%d)), ct_2=((%d)), ct_3=((%d)), ct_4=((%d))\n", */ - /* function, dbg_num, content_0, content_1, content_2, content_3, content_4)); */ - - /*--------------------------------------------*/ -#if (CONFIG_RA_FW_DBG_CODE) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW Msg] Invalid cmd length (( %d )) >12\n", + cmd_len); +/*@--------------------------------------------*/ +#ifdef CONFIG_RA_FW_DBG_CODE if (function == RATE_DECISION) { if (dbg_num == 0) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RA_CNT=((%d)) Max_device=((%d))--------------------------->\n", content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] RA_CNT=((%d)) Max_device=((%d))--------------------------->\n", + content_1, content_2); else if (content_0 == 2) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)), try_bit=((0x%x))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)), try_bit=((0x%x))\n", + content_1, content_2, content_3, + content_4); else if (content_0 == 3) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Check RA total=((%d)), drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Check RA total=((%d)), drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n", + content_1, content_2, content_3, + content_4); } else if (dbg_num == 1) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n", + content_1, content_2, content_3, + content_4); else if (content_0 == 2) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))", content_1, content_2, content_3, content_4)); - phydm_print_rate(p_dm_odm, (u8)content_4, ODM_FW_DEBUG_TRACE); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))", + content_1, content_2, content_3, + content_4); + phydm_print_rate(dm, (u8)content_4, + DBG_FW_TRACE); } else if (content_0 == 3) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] penality_idx=(( %d ))\n", content_1)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] penality_idx=(( %d ))\n", + content_1); else if (content_0 == 4) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RSSI=(( %d )), ra_stage = (( %d ))\n", content_1, content_2)); - } - - else if (dbg_num == 3) { + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] RSSI=(( %d )), ra_stage = (( %d ))\n", + content_1, content_2); + } else if (dbg_num == 3) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( DOWN )) total=((%d)), total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Fast_RA (( DOWN )) total=((%d)), total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", + content_1, content_2, content_3, + content_4); else if (content_0 == 2) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) total_acc=((%d)), total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Fast_RA (( UP )) total_acc=((%d)), total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", + content_1, content_2, content_3, + content_4); else if (content_0 == 3) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((rate Down Hold)) RA_CNT=((%d))\n", content_1)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Fast_RA (( UP )) ((rate Down Hold)) RA_CNT=((%d))\n", + content_1); else if (content_0 == 4) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( UP )) ((tota_accl<5 skip)) RA_CNT=((%d))\n", content_1)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Fast_RA (( UP )) ((tota_accl<5 skip)) RA_CNT=((%d))\n", + content_1); else if (content_0 == 8) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n", content_1)); - } - - else if (dbg_num == 4) { - if (content_0 == 3) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] RER_CNT PCR_ori =(( %d )), ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n", content_1, content_2, content_3, content_4)); - /**/ - } else if (content_0 == 4) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n", ((content_1) ? "+" : "-"), content_2, content_3, content_4)); - /**/ - } else if (content_0 == 5) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n", content_1, content_2, content_3, content_4)); - /**/ - } - } - - else if (dbg_num == 5) { + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n", + content_1); + } else if (dbg_num == 4) { + if (content_0 == 3) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] RER_CNT PCR_ori =(( %d )), ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n", + content_1, content_2, content_3, + content_4); + else if (content_0 == 4) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n", + ((content_1) ? "+" : "-"), content_2, + content_3, content_4); + else if (content_0 == 5) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n", + content_1, content_2, content_3, + content_4); + } else if (dbg_num == 5) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] (( UP)) Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] (( UP)) Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n", + content_1, content_2, content_3, + content_4); else if (content_0 == 2) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((DOWN)) Nsc=(( %d )), N_Low=(( %d ))\n", content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] ((DOWN)) Nsc=(( %d )), N_Low=(( %d ))\n", + content_1, content_2); else if (content_0 == 3) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((HOLD)) Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] ((HOLD)) Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n", + content_1, content_2, content_3, + content_4); } else if (dbg_num == 0x60) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) macid=((%d)), BUPDATE[macid]=((%d))\n", content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] ((AP RPT)) macid=((%d)), BUPDATE[macid]=((%d))\n", + content_1, content_2); else if (content_0 == 4) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] ((AP RPT)) pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n", + content_1, content_2, content_3, + content_4); else if (content_0 == 5) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW] ((AP RPT)) PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] ((AP RPT)) PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n", + content_1, content_2, content_3, + content_4); } - } - /*--------------------------------------------*/ - else if (function == INIT_RA_TABLE) { + } else if (function == INIT_RA_TABLE) { if (dbg_num == 3) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n", content_0)); - - } - /*--------------------------------------------*/ - else if (function == RATE_UP) { + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n", + content_0); + } else if (function == RATE_UP) { if (dbg_num == 2) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Highest rate->return)), macid=((%d)) Nsc=((%d))\n", content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][RateUp] ((Highest rate->return)), macid=((%d)) Nsc=((%d))\n", + content_1, content_2); } else if (dbg_num == 5) { if (content_0 == 0) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)), SGI=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][RateUp] ((rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)), SGI=((%d))\n", + content_1, content_2, content_3, + content_4); else if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][RateUp] ((rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n", + content_1, content_2, content_3, + content_4); } - - } - /*--------------------------------------------*/ - else if (function == RATE_DOWN) { + } else if (function == RATE_DOWN) { if (dbg_num == 5) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDownStep] ((rate Down)), macid=((%d)), rate1=((0x%x)), rate2=((0x%x)), BW=((%d))\n", content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][RateDownStep] ((rate Down)), macid=((%d)), rate1=((0x%x)), rate2=((0x%x)), BW=((%d))\n", + content_1, content_2, content_3, + content_4); } } else if (function == TRY_DONE) { if (dbg_num == 1) { - if (content_0 == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n", content_1, content_2)); - /**/ - } + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][Try Done] ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n", + content_1, content_2); } else if (dbg_num == 2) { - if (content_0 == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try)) macid=((%d)), Try_Done_cnt=((%d)), rate_2=((%d)), try_succes=((%d))\n", content_1, content_2, content_3, content_4)); - /**/ - } + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][Try Done] ((try)) macid=((%d)), Try_Done_cnt=((%d)), rate_2=((%d)), try_succes=((%d))\n", + content_1, content_2, content_3, + content_4); } - } - /*--------------------------------------------*/ - else if (function == RA_H2C) { + } else if (function == RA_H2C) { if (dbg_num == 1) { - if (content_0 == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x49] fw_trace_en=((%d)), mode =((%d)), macid=((%d))\n", content_1, content_2, content_3)); - /**/ - /*C2H_RA_Dbg_code(F_RA_H2C,1,0, SysMib.ODM.DEBUG.fw_trace_en, mode, macid, 0); //RA MASK*/ - } -#if 0 - else if (dbg_num == 2) { - - if (content_0 == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] MACID=((%d)), rate ID=((%d)), SGI=((%d)), BW=((%d))\n", content_1, content_2, content_3, content_4)); - /**/ - } else if (content_0 == 2) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] VHT_en=((%d)), Disable_PowerTraining=((%d)), Disable_RA=((%d)), No_Update=((%d))\n", content_1, content_2, content_3, content_4)); - /**/ - } else if (content_0 == 3) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][H2C=0x40] RA_MSK=[%x | %x | %x | %x ]\n", content_1, content_2, content_3, content_4)); - /**/ - } - } -#endif + if (content_0 == 0) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][H2C=0x49] fw_trace_en=((%d)), mode =((%d)), macid=((%d))\n", + content_1, content_2, content_3); } - } - /*--------------------------------------------*/ - else if (function == F_RATE_AP_RPT) { + } else if (function == F_RATE_AP_RPT) { if (dbg_num == 1) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] ((1)), SPE_STATIS=((0x%x))---------->\n", content_3)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] ((1)), SPE_STATIS=((0x%x))---------->\n", + content_3); } else if (dbg_num == 2) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] RTY_all=((%d))\n", content_1)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] RTY_all=((%d))\n", + content_1); } else if (dbg_num == 3) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] MACID1[%d], TOTAL=((%d)), RTY=((%d))\n", + content_3, content_1, content_2); } else if (dbg_num == 4) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] MACID2[%d], TOTAL=((%d)), RTY=((%d))\n", + content_3, content_1, content_2); } else if (dbg_num == 5) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] MACID1[%d], PASS=((%d)), DROP=((%d))\n", + content_3, content_1, content_2); } else if (dbg_num == 6) { if (content_0 == 1) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d],, PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] MACID2[%d],, PASS=((%d)), DROP=((%d))\n", + content_3, content_1, content_2); } + } else if (function == DBC_FW_CLM) { + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][CLM][%d, %d] = {%d, %d, %d, %d}\n", dbg_num, + content_0, content_1, content_2, content_3, + content_4); } else { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); - /**/ + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", + function, dbg_num, content_0, content_1, content_2, + content_3, content_4); } #else - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, dbg_num, content_0, content_1, content_2, content_3, content_4)); + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, + dbg_num, content_0, content_1, content_2, content_3, + content_4); #endif - /*--------------------------------------------*/ +/*@--------------------------------------------*/ -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ } -void -phydm_fw_trace_handler_8051( - void *p_dm_void, - u8 *buffer, - u8 cmd_len -) +void phydm_fw_trace_handler_8051(void *dm_void, u8 *buffer, u8 cmd_len) { -#if CONFIG_PHYDM_DEBUG_FUNCTION - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; #if 0 if (cmd_len >= 3) cmd_buf[cmd_len - 1] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", &(cmd_buf[3]))); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s\n", &cmd_buf[3]); #else int i = 0; - u8 extend_c2h_sub_id = 0, extend_c2h_dbg_len = 0, extend_c2h_dbg_seq = 0; - u8 fw_debug_trace[128]; - u8 *extend_c2h_dbg_content = 0; + u8 extend_c2h_sub_id = 0, extend_c2h_dbg_len = 0; + u8 extend_c2h_dbg_seq = 0; + u8 fw_debug_trace[128]; + u8 *extend_c2h_dbg_content = 0; if (cmd_len > 127) return; extend_c2h_sub_id = buffer[0]; extend_c2h_dbg_len = buffer[1]; - extend_c2h_dbg_content = buffer + 2; /*DbgSeq+DbgContent for show HEX*/ + extend_c2h_dbg_content = buffer + 2; /*@DbgSeq+DbgContent for show HEX*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) RT_DISP(FC2H, C2H_Summary, ("[Extend C2H packet], Extend_c2hSubId=0x%x, extend_c2h_dbg_len=%d\n", @@ -3213,21 +4506,22 @@ phydm_fw_trace_handler_8051( RT_DISP(FC2H, C2H_Summary, ("[RTKFW, SEQ= %d] :", extend_c2h_dbg_seq)); #endif - for (; ; i++) { + for (;; i++) { fw_debug_trace[i] = extend_c2h_dbg_content[i]; if (extend_c2h_dbg_content[i + 1] == '\0') { fw_debug_trace[i + 1] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s", + &fw_debug_trace[0]); break; } else if (extend_c2h_dbg_content[i] == '\n') { fw_debug_trace[i + 1] = '\0'; - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s", + &fw_debug_trace[0]); buffer = extend_c2h_dbg_content + i + 3; goto go_backfor_aggre_dbg_pkt; } } - #endif -#endif /*#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ } diff --git a/hal/phydm/phydm_debug.h b/hal/phydm/phydm_debug.h index 7fb69ab..abb8b9a 100644 --- a/hal/phydm/phydm_debug.h +++ b/hal/phydm/phydm_debug.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,141 +8,95 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ - + * Larry Finger + * + *****************************************************************************/ -#ifndef __ODM_DBG_H__ +#ifndef __ODM_DBG_H__ #define __ODM_DBG_H__ -/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/ -/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/ -#define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/ -/* ----------------------------------------------------------------------------- - * Define the debug levels - * - * 1. DBG_TRACE and DBG_LOUD are used for normal cases. - * So that, they can help SW engineer to develope or trace states changed - * and also help HW enginner to trace every operation to and from HW, - * e.g IO, Tx, Rx. - * - * 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, - * which help us to debug SW or HW. - * - * ----------------------------------------------------------------------------- - * - * Never used in a call to ODM_RT_TRACE()! - * */ -#define ODM_DBG_OFF 1 - -/* - * Fatal bug. - * For example, Tx/Rx/IO locked up, OS hangs, memory access violation, - * resource allocation failed, unexpected HW behavior, HW BUG and so on. - * */ -#define ODM_DBG_SERIOUS 2 - -/* - * Abnormal, rare, or unexpeted cases. - * For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. - * */ -#define ODM_DBG_WARNING 3 - -/* - * Normal case with useful information about current SW or HW state. - * For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, - * SW protocol state change, dynamic mechanism state change and so on. - * */ -#define ODM_DBG_LOUD 4 - -/* - * Normal case with detail execution flow or information. - * */ -#define ODM_DBG_TRACE 5 - -/*FW DBG MSG*/ -#define RATE_DECISION BIT(0) -#define INIT_RA_TABLE BIT(1) -#define RATE_UP BIT(2) -#define RATE_DOWN BIT(3) -#define TRY_DONE BIT(4) -#define RA_H2C BIT(5) -#define F_RATE_AP_RPT BIT(7) - -/* ----------------------------------------------------------------------------- +/*@#define DEBUG_VERSION "1.1"*/ /*@2015.07.29 YuChen*/ +/*@#define DEBUG_VERSION "1.2"*/ /*@2015.08.28 Dino*/ +/*@#define DEBUG_VERSION "1.3"*/ /*@2016.04.28 YuChen*/ +/*@#define DEBUG_VERSION "1.4"*/ /*@2017.03.13 Dino*/ +#define DEBUG_VERSION "2.0" /*@2018.01.10 Dino*/ + +/*@ + * ============================================================ + * Definition + * ============================================================ + */ + +/*@FW DBG MSG*/ +#define RATE_DECISION 1 +#define INIT_RA_TABLE 2 +#define RATE_UP 4 +#define RATE_DOWN 8 +#define TRY_DONE 16 +#define RA_H2C 32 +#define F_RATE_AP_RPT 64 +#define DBC_FW_CLM 9 + +#define PHYDM_SNPRINT_SIZE 64 +/* @---------------------------------------------------------------------------- * Define the tracing components * * ----------------------------------------------------------------------------- - *BB FW Functions*/ -#define PHYDM_FW_COMP_RA BIT(0) -#define PHYDM_FW_COMP_MU BIT(1) -#define PHYDM_FW_COMP_PATH_DIV BIT(2) -#define PHYDM_FW_COMP_PHY_CONFIG BIT(3) - - -/*BB Driver Functions*/ -#define ODM_COMP_DIG BIT(0) -#define ODM_COMP_RA_MASK BIT(1) -#define ODM_COMP_DYNAMIC_TXPWR BIT(2) -#define ODM_COMP_FA_CNT BIT(3) -#define ODM_COMP_RSSI_MONITOR BIT(4) -#define ODM_COMP_SNIFFER BIT(5) -#define ODM_COMP_ANT_DIV BIT(6) -#define ODM_COMP_DFS BIT(7) -#define ODM_COMP_NOISY_DETECT BIT(8) -#define ODM_COMP_RATE_ADAPTIVE BIT(9) -#define ODM_COMP_PATH_DIV BIT(10) -#define ODM_COMP_CCX BIT(11) - -#define ODM_COMP_DYNAMIC_PRICCA BIT(12) -/*BIT13 TBD*/ -#define ODM_COMP_MP BIT(14) -#define ODM_COMP_CFO_TRACKING BIT(15) -#define ODM_COMP_ACS BIT(16) -#define PHYDM_COMP_ADAPTIVITY BIT(17) -#define PHYDM_COMP_RA_DBG BIT(18) -#define PHYDM_COMP_TXBF BIT(19) -/* MAC Functions */ -#define ODM_COMP_EDCA_TURBO BIT(20) -#define ODM_COMP_DYNAMIC_RX_PATH BIT(21) -#define ODM_FW_DEBUG_TRACE BIT(22) -/* RF Functions */ -/*BIT23 TBD*/ -#define ODM_COMP_TX_PWR_TRACK BIT(24) -/*BIT25 TBD*/ -#define ODM_COMP_CALIBRATION BIT(26) -/* Common Functions */ -/*BIT27 TBD*/ -#define ODM_PHY_CONFIG BIT(28) -#define ODM_COMP_INIT BIT(29) -#define ODM_COMP_COMMON BIT(30) -#define ODM_COMP_API BIT(31) - - -/*------------------------Export Marco Definition---------------------------*/ - -#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA) + * BB FW Functions + */ +#define PHYDM_FW_COMP_RA BIT(0) +#define PHYDM_FW_COMP_MU BIT(1) +#define PHYDM_FW_COMP_PATH_DIV BIT(2) +#define PHYDM_FW_COMP_PT BIT(3) + +/*@------------------------Export Marco Definition---------------------------*/ + +#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define dbg_print DbgPrint - #define dcmd_printf DCMD_Printf - #define dcmd_scanf DCMD_Scanf - #define RT_PRINTK dbg_print + #if (DBG_CMD_SUPPORT == 1) + extern VOID DCMD_Printf(const char *pMsg); + #else + #define DCMD_Printf(_pMsg) + #endif + + #define pr_debug DbgPrint + #define dcmd_printf DCMD_Printf + #define dcmd_scanf DCMD_Scanf + #define RT_PRINTK pr_debug + #define PRINT_MAX_SIZE 512 + #define PHYDM_SNPRINTF RT_SPRINTF +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + #define PHYDM_SNPRINTF snprintf #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #define dbg_print printk - #define RT_PRINTK(fmt, args...) dbg_print("%s(): " fmt, __FUNCTION__, ## args); + #undef pr_debug + #define pr_debug printk + #define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args) #define RT_DISP(dbgtype, dbgflag, printstr) + #define RT_TRACE(adapter, comp, drv_level, fmt, args...) \ + RTW_INFO(fmt, ## args) + #define PHYDM_SNPRINTF snprintf +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + #define pr_debug(fmt, args...) RTW_PRINT_MSG(fmt, ## args) + #define RT_DEBUG(comp, drv_level, fmt, args...) \ + RTW_PRINT_MSG(fmt, ## args) + #define PHYDM_SNPRINTF snprintf #else - #define dbg_print panic_printk - /*#define RT_PRINTK(fmt, args...) dbg_print("%s(): " fmt, __FUNCTION__, ## args);*/ - #define RT_PRINTK(fmt, args...) dbg_print(fmt, ## args); + #define pr_debug panic_printk + /*@#define RT_PRINTK(fmt, args...) pr_debug("%s(): " fmt, __FUNCTION__, ## args);*/ + #define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args) + #define PHYDM_SNPRINTF snprintf #endif #ifndef ASSERT @@ -150,238 +104,341 @@ #endif #if DBG -#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt) \ - do { \ - if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level || level == ODM_DBG_SERIOUS)) { \ - \ - if (p_dm_odm->support_ic_type == ODM_RTL8188E) \ - dbg_print("[PhyDM-8188E] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8192E) \ - dbg_print("[PhyDM-8192E] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8812) \ - dbg_print("[PhyDM-8812A] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8821) \ - dbg_print("[PhyDM-8821A] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8814A) \ - dbg_print("[PhyDM-8814A] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8703B) \ - dbg_print("[PhyDM-8703B] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) \ - dbg_print("[PhyDM-8822B] "); \ - else if (p_dm_odm->support_ic_type == ODM_RTL8188F) \ - dbg_print("[PhyDM-8188F] "); \ - RT_PRINTK fmt; \ - } \ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#define PHYDM_DBG(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->debug_components) { \ + pr_debug("[PHYDM] "); \ + RT_PRINTK(fmt, ## args); \ + } \ } while (0) -#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt) do {\ - if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \ - \ - RT_PRINTK fmt; \ - } \ +#define PHYDM_DBG_F(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->debug_components) { \ + RT_PRINTK(fmt, ## args); \ + } \ } while (0) - -#define ODM_RT_ASSERT(p_dm_odm, expr, fmt) do {\ - if (!(expr)) { \ - dbg_print("Assertion failed! %s at ......\n", #expr); \ - dbg_print(" ......%s,%s, line=%d\n", __FILE__, __FUNCTION__, __LINE__); \ - RT_PRINTK fmt; \ - ASSERT(false); \ +#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \ + do { \ + if ((comp) & dm->debug_components) { \ + int __i; \ + u8 *__ptr = (u8 *)addr; \ + pr_debug("[PHYDM] "); \ + pr_debug(title_str); \ + pr_debug(" "); \ + for (__i = 0; __i < 6; __i++) \ + pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");\ + pr_debug("\n"); \ + } \ + } while (0) +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +static __inline void PHYDM_DBG(PDM_ODM_T dm, int comp, char *fmt, ...) +{ + RT_STATUS rt_status; + va_list args; + char buf[PRINT_MAX_SIZE] = {0}; + + if ((comp & dm->debug_components) == 0) + return; + + if (fmt == NULL) + return; + + va_start(args, fmt); + rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args); + va_end(args); + + if (rt_status != RT_STATUS_SUCCESS) { + DbgPrint("Failed (%d) to print message to buffer\n", rt_status); + return; + } + + DbgPrint("[PHYDM] %s", buf); +} + +static __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...) +{ + RT_STATUS rt_status; + va_list args; + char buf[PRINT_MAX_SIZE] = {0}; + + if ((comp & dm->debug_components) == 0) + return; + + if (fmt == NULL) + return; + + va_start(args, fmt); + rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args); + va_end(args); + + if (rt_status != RT_STATUS_SUCCESS) { + /*@DbgPrint("DM Print Fail\n");*/ + return; + } + + DbgPrint("%s", buf); +} + +#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr) \ + do { \ + if ((comp) & p_dm->debug_components) { \ + \ + int __i; \ + u8 *__ptr = (u8 *)ptr; \ + pr_debug("[PHYDM] "); \ + pr_debug(title_str); \ + pr_debug(" "); \ + for (__i = 0; __i < 6; __i++) \ + pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \ + pr_debug("\n"); \ } \ } while (0) +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + +#define PHYDM_DBG(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->debug_components) { \ + RT_DEBUG(COMP_PHYDM, \ + DBG_DMESG, "[PHYDM] " fmt, ##args); \ + } \ + } while (0) -#define ODM_dbg_enter() { dbg_print(" == > %s\n", __FUNCTION__); } -#define ODM_dbg_exit() { dbg_print("< == %s\n", __FUNCTION__); } -#define ODM_dbg_trace(str) { dbg_print("%s:%s\n", __FUNCTION__, str); } - -#define ODM_PRINT_ADDR(p_dm_odm, comp, level, title_str, ptr) do {\ - if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \ - \ - int __i; \ - u8 *__ptr = (u8 *)ptr; \ - dbg_print("[ODM] "); \ - dbg_print(title_str); \ - dbg_print(" "); \ - for (__i = 0; __i < 6; __i++) \ - dbg_print("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \ - dbg_print("\n"); \ +#define PHYDM_DBG_F(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->debug_components) { \ + RT_DEBUG(COMP_PHYDM, \ + DBG_DMESG, fmt, ##args); \ } \ } while (0) -#else -#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt) -#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt) -#define ODM_RT_ASSERT(p_dm_odm, expr, fmt) -#define ODM_dbg_enter() -#define ODM_dbg_exit() -#define ODM_dbg_trace(str) -#define ODM_PRINT_ADDR(p_dm_odm, comp, level, title_str, ptr) -#endif +#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \ + do { \ + if ((comp) & dm->debug_components) { \ + RT_DEBUG(COMP_PHYDM, \ + DBG_DMESG, "[PHYDM] " title_str "%pM\n", \ + addr); \ + } \ + } while (0) -#define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/ -#define BB_DBGPORT_PRIORITY_2 2 /*Check hang function & Strong function*/ -#define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/ -#define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/ +#elif defined(DM_ODM_CE_MAC80211_V2) -void -phydm_init_debug_setting(struct PHY_DM_STRUCT *p_dm_odm); +#define PHYDM_DBG(dm, comp, fmt, args...) +#define PHYDM_DBG_F(dm, comp, fmt, args...) +#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) -void -phydm_bb_dbg_port_header_sel( - void *p_dm_void, - u32 header_idx -); +#else -u8 -phydm_set_bb_dbg_port( - void *p_dm_void, - u8 curr_dbg_priority, - u32 debug_port -); +#define PHYDM_DBG(dm, comp, fmt, args...) \ + do { \ + struct dm_struct *__dm = (dm); \ + if ((comp) & __dm->debug_components) { \ + RT_TRACE(((struct rtl_priv *)__dm->adapter),\ + COMP_PHYDM, DBG_DMESG, \ + "[PHYDM] " fmt, ##args); \ + } \ + } while (0) -void -phydm_release_bb_dbg_port( - void *p_dm_void -); +#define PHYDM_DBG_F(dm, comp, fmt, args...) \ + do { \ + struct dm_struct *__dm = (dm); \ + if ((comp) & __dm->debug_components) { \ + RT_TRACE(((struct rtl_priv *)__dm->adapter),\ + COMP_PHYDM, DBG_DMESG, fmt, ##args); \ + } \ + } while (0) -u32 -phydm_get_bb_dbg_port_value( - void *p_dm_void -); +#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \ + do { \ + struct dm_struct *__dm = (dm); \ + if ((comp) & __dm->debug_components) { \ + RT_TRACE(((struct rtl_priv *)__dm->adapter),\ + COMP_PHYDM, DBG_DMESG, \ + "[PHYDM] " title_str "%pM\n", addr);\ + } \ + } while (0) +#endif -void phydm_basic_dbg_message(void *p_dm_void); +#else /*@#if DBG*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +static __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...) +{ +} +static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...) +{ +} +#else +#define PHYDM_DBG(dm, comp, fmt, args...) +#define PHYDM_DBG_F(dm, comp, fmt, args...) +#endif +#define PHYDM_PRINT_ADDR(dm, comp, title_str, ptr) + +#endif + +#define DBGPORT_PRI_3 3 /*@Debug function (the highest priority)*/ +#define DBGPORT_PRI_2 2 /*@Check hang function & Strong function*/ +#define DBGPORT_PRI_1 1 /*Watch dog function*/ +#define DBGPORT_RELEASE 0 /*@Init value (the lowest priority)*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #define PHYDM_DBGPRINT 0 #define PHYDM_SSCANF(x, y, z) dcmd_scanf(x, y, z) -#define PHYDM_VAST_INFO_SNPRINTF PHYDM_SNPRINTF +#define PDM_VAST_SNPF PDM_SNPF #if (PHYDM_DBGPRINT == 1) -#define PHYDM_SNPRINTF(msg) \ - do {\ - rsprintf msg;\ - dbg_print(output);\ - } while (0) -#else -#define PHYDM_SNPRINTF(msg) \ +#define PDM_SNPF(msg) \ do {\ rsprintf msg;\ - dcmd_printf(output);\ + pr_debug("%s", output);\ } while (0) -#endif #else -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__) - #define PHYDM_DBGPRINT 0 -#else - #define PHYDM_DBGPRINT 1 -#endif -#define MAX_ARGC 20 -#define MAX_ARGV 16 -#define DCMD_DECIMAL "%d" -#define DCMD_CHAR "%c" -#define DCMD_HEX "%x" + +static __inline void PDM_SNPF(u32 out_len, u32 used, char *buff, int len, + char *fmt, ...) +{ + RT_STATUS rt_status; + va_list args; + char buf[PRINT_MAX_SIZE] = {0}; + + if (fmt == NULL) + return; + + va_start(args, fmt); + rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args); + va_end(args); + + if (rt_status != RT_STATUS_SUCCESS) { + /*@DbgPrint("DM Print Fail\n");*/ + return; + } + + DCMD_Printf(buf); +} + + + +#endif /*@#if (PHYDM_DBGPRINT == 1)*/ +#else /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/ + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__) + #define PHYDM_DBGPRINT 0 + #else + #define PHYDM_DBGPRINT 1 + #endif +#define MAX_ARGC 20 +#define MAX_ARGV 16 +#define DCMD_DECIMAL "%d" +#define DCMD_CHAR "%c" +#define DCMD_HEX "%x" #define PHYDM_SSCANF(x, y, z) sscanf(x, y, z) -#define PHYDM_VAST_INFO_SNPRINTF(msg)\ - do {\ - snprintf msg;\ - dbg_print(output);\ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) RT_PRINTK(fmt, ## args) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) +#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) \ + do { \ + RT_DEBUG(COMP_PHYDM, DBG_DMESG, fmt, ##args); \ } while (0) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) +#else +#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) \ + RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \ + DBG_DMESG, fmt, ##args) +#endif #if (PHYDM_DBGPRINT == 1) -#define PHYDM_SNPRINTF(msg)\ - do {\ - snprintf msg;\ - dbg_print(output);\ +#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \ + do { \ + snprintf(buff, len, fmt, ##args); \ + pr_debug("%s", output); \ } while (0) #else -#define PHYDM_SNPRINTF(msg)\ - do {\ - if (out_len > used)\ - used += snprintf msg;\ +#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \ + do { \ + u32 *__pdm_snpf_u = &(used); \ + if (out_len > *__pdm_snpf_u) \ + *__pdm_snpf_u += snprintf(buff, len, fmt, ##args);\ } while (0) #endif #endif +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +enum auto_detection_state { /*@Fast antenna training*/ + AD_LEGACY_MODE = 0, + AD_HT_MODE = 1, + AD_VHT_MODE = 2 +}; + +/*@ + * ============================================================ + * 1 structure + * ============================================================ + */ + +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION +u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig); +#endif +void phydm_init_debug_setting(struct dm_struct *dm); -void phydm_basic_profile( - void *p_dm_void, - u32 *_used, - char *output, - u32 *_out_len -); +void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx); + +u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port); + +void phydm_release_bb_dbg_port(void *dm_void); + +u32 phydm_get_bb_dbg_port_val(void *dm_void); + +void phydm_reset_rx_rate_distribution(struct dm_struct *dm); + +void phydm_rx_rate_distribution(void *dm_void); + +void phydm_show_phy_hitogram(void *dm_void); + +void phydm_get_avg_phystatus_val(void *dm_void); + +void phydm_get_phy_statistic(void *dm_void); + +void phydm_dm_summary(void *dm_void, u8 macid); + +void phydm_basic_dbg_message(void *dm_void); + +void phydm_basic_profile(void *dm_void, u32 *_used, char *output, + u32 *_out_len); #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) -s32 -phydm_cmd( - struct PHY_DM_STRUCT *p_dm_odm, - char *input, - u32 in_len, - u8 flag, - char *output, - u32 out_len -); +s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag, + char *output, u32 out_len); #endif -void -phydm_cmd_parser( - struct PHY_DM_STRUCT *p_dm_odm, - char input[][16], - u32 input_num, - u8 flag, - char *output, - u32 out_len -); - -boolean -phydm_api_trx_mode( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_path_e tx_path, - enum odm_rf_path_e rx_path, - boolean is_tx2_path -); +void phydm_cmd_parser(struct dm_struct *dm, char input[][16], u32 input_num, + u8 flag, char *output, u32 out_len); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf); + void phydm_sbd_check( - struct PHY_DM_STRUCT *p_dm_odm -); + struct dm_struct *dm); void phydm_sbd_callback( - struct timer_list *p_timer -); + struct phydm_timer_list *timer); void phydm_sbd_workitem_callback( - void *p_context -); + void *context); #endif -void -phydm_fw_trace_en_h2c( - void *p_dm_void, - boolean enable, - u32 fw_debug_component, - u32 monitor_mode, - u32 macid -); - -void -phydm_fw_trace_handler( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len -); - -void -phydm_fw_trace_handler_code( - void *p_dm_void, - u8 *buffer, - u8 cmd_len -); - -void -phydm_fw_trace_handler_8051( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len -); - -#endif /* __ODM_DBG_H__ */ +void phydm_fw_trace_en_h2c(void *dm_void, boolean enable, + u32 fw_debug_component, u32 monitor_mode, u32 macid); + +void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); + +void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len); + +void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len); + +#endif /* @__ODM_DBG_H__ */ diff --git a/hal/phydm/phydm_dfs.c b/hal/phydm/phydm_dfs.c index 4e4617a..0a46a7d 100644 --- a/hal/phydm/phydm_dfs.c +++ b/hal/phydm/phydm_dfs.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,458 +8,703 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -/* -============================================================ - include files -============================================================ -*/ +/*@ + * ============================================================ + * include files + * ============================================================ + */ #include "mp_precomp.h" #include "phydm_precomp.h" #if defined(CONFIG_PHYDM_DFS_MASTER) -boolean phydm_dfs_is_meteorology_channel(void *p_dm_void){ +boolean phydm_dfs_is_meteorology_channel(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + u8 ch = *dm->channel; + u8 bw = *dm->band_width; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - u8 c_channel = *(p_dm_odm->p_channel); - u8 band_width = *(p_dm_odm->p_band_width); - - return ( (band_width == CHANNEL_WIDTH_80 && (c_channel) >= 116 && (c_channel) <= 128) || - (band_width == CHANNEL_WIDTH_40 && (c_channel) >= 116 && (c_channel) <= 128) || - (band_width == CHANNEL_WIDTH_20 && (c_channel) >= 120 && (c_channel) <= 128) ); + return ((bw == CHANNEL_WIDTH_80 && (ch) >= 116 && (ch) <= 128) || + (bw == CHANNEL_WIDTH_40 && (ch) >= 116 && (ch) <= 128) || + (bw == CHANNEL_WIDTH_20 && (ch) >= 120 && (ch) <= 128)); } -void phydm_radar_detect_reset(void *p_dm_void) +void phydm_radar_detect_reset(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0); - odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 1); + odm_set_bb_reg(dm, R_0x924, BIT(15), 0); + odm_set_bb_reg(dm, R_0x924, BIT(15), 1); } -void phydm_radar_detect_disable(void *p_dm_void) +void phydm_radar_detect_disable(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("\n")); + odm_set_bb_reg(dm, R_0x924, BIT(15), 0); + PHYDM_DBG(dm, DBG_DFS, "\n"); } -static void phydm_radar_detect_with_dbg_parm(void *p_dm_void) +static void phydm_radar_detect_with_dbg_parm(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, p_dm_odm->radar_detect_reg_918); - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, p_dm_odm->radar_detect_reg_91c); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, p_dm_odm->radar_detect_reg_920); - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, p_dm_odm->radar_detect_reg_924); + odm_set_bb_reg(dm, R_0x918, MASKDWORD, dm->radar_detect_reg_918); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, dm->radar_detect_reg_91c); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, dm->radar_detect_reg_920); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, dm->radar_detect_reg_924); } -/* Init radar detection parameters, called after ch, bw is set */ -void phydm_radar_detect_enable(void *p_dm_void) +/* @Init radar detection parameters, called after ch, bw is set */ + +void phydm_radar_detect_enable(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS); - u8 region_domain = p_dm_odm->dfs_region_domain; - u8 c_channel = *(p_dm_odm->p_channel); - u8 band_width = *(p_dm_odm->p_band_width); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + u8 region_domain = dm->dfs_region_domain; + u8 c_channel = *dm->channel; + u8 band_width = *dm->band_width; u8 enable = 0; + u8 short_pw_upperbound = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("test, region_domain = %d\n", region_domain)); + PHYDM_DBG(dm, DBG_DFS, "test, region_domain = %d\n", region_domain); if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n")); + PHYDM_DBG(dm, DBG_DFS, "PHYDM_DFS_DOMAIN_UNKNOWN\n"); goto exit; } - if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) { - - odm_set_bb_reg(p_dm_odm, 0x814, 0x3fffffff, 0x04cc4d10); - odm_set_bb_reg(p_dm_odm, 0x834, MASKBYTE0, 0x06); + if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) { + odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10); + odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06); - if (p_dm_odm->radar_detect_dbg_parm_en) { - phydm_radar_detect_with_dbg_parm(p_dm_odm); + if (dm->radar_detect_dbg_parm_en) { + phydm_radar_detect_with_dbg_parm(dm); enable = 1; goto exit; } if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c17ecdf); - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500); - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0fa21a20); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0f69204); + odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c17ecdf); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fa21a20); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f69204); } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) { - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67234); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234); if (c_channel >= 52 && c_channel <= 64) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16ecdf); - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0f141a20); + odm_set_bb_reg(dm, R_0x918, MASKDWORD, + 0x1c16ecdf); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x0f141a20); } else { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf); - if (band_width == ODM_BW20M) - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64721a20); + odm_set_bb_reg(dm, R_0x918, MASKDWORD, + 0x1c16acdf); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x64721a20); else - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68721a20); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x68721a20); } } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf); - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x01528500); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67231); - if (band_width == ODM_BW20M) - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64741a20); + odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67231); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x64741a20); else - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68741a20); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x68741a20); } else { /* not supported */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported dfs_region_domain:%d\n", region_domain)); + PHYDM_DBG(dm, DBG_DFS, + "Unsupported dfs_region_domain:%d\n", + region_domain); goto exit; } - } else if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) { + } else if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) { + /*@for 8822B RXHP H2L, since L will always cause DFS FRD + if (dm->support_ic_type & (ODM_RTL8822B)) { + odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x29035612); + odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492); + } + */ - odm_set_bb_reg(p_dm_odm, 0x814, 0x3fffffff, 0x04cc4d10); - odm_set_bb_reg(p_dm_odm, 0x834, MASKBYTE0, 0x06); + odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10); + odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06); - /* 8822B only, when BW = 20M, DFIR output is 40Mhz, but DFS input is 80MMHz, so it need to upgrade to 80MHz */ - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { - if (band_width == ODM_BW20M) - odm_set_bb_reg(p_dm_odm, 0x1984, BIT(26), 1); + /* @8822B only, when BW = 20M, DFIR output is 40Mhz, + * but DFS input is 80MMHz, so it need to upgrade to 80MHz + */ + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, R_0x1984, BIT(26), 1); else - odm_set_bb_reg(p_dm_odm, 0x1984, BIT(26), 0); + odm_set_bb_reg(dm, R_0x1984, BIT(26), 0); } - if (p_dm_odm->radar_detect_dbg_parm_en) { - phydm_radar_detect_with_dbg_parm(p_dm_odm); + if (dm->radar_detect_dbg_parm_en) { + phydm_radar_detect_with_dbg_parm(dm); enable = 1; goto exit; } if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16acdf); - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500); - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0fa21a20); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0f57204); + odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fa21a20); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f57204); } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) { - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67234); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234); if (c_channel >= 52 && c_channel <= 64) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c16ecdf); - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x0f141a20); + odm_set_bb_reg(dm, R_0x918, MASKDWORD, + 0x1c16ecdf); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x0f141a20); } else { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c166cdf); - if (band_width == ODM_BW20M) - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64721a20); + odm_set_bb_reg(dm, R_0x918, MASKDWORD, + 0x1c166cdf); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x64721a20); else - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68721a20); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x68721a20); } } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { - odm_set_bb_reg(p_dm_odm, 0x918, MASKDWORD, 0x1c166cdf); - odm_set_bb_reg(p_dm_odm, 0x924, MASKDWORD, 0x095a8500); - odm_set_bb_reg(p_dm_odm, 0x920, MASKDWORD, 0xe0d67231); - if (band_width == ODM_BW20M) - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x64741a20); + odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c176cdf); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8400); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe076d231); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x64901a20); else - odm_set_bb_reg(p_dm_odm, 0x91c, MASKDWORD, 0x68741a20); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x62901a20); } else { /* not supported */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported dfs_region_domain:%d\n", region_domain)); + PHYDM_DBG(dm, DBG_DFS, + "Unsupported dfs_region_domain:%d\n", + region_domain); goto exit; } + /*RXHP low corner will extend the pulse width, + *so we need to increase the upper bound. + */ + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + if (odm_get_bb_reg(dm, 0x8d8, + BIT28 | BIT27 | BIT26) == 0) { + short_pw_upperbound = + (u8)odm_get_bb_reg(dm, 0x91c, + BIT23 | BIT22 | + BIT21 | BIT20); + if ((short_pw_upperbound + 4) > 15) + odm_set_bb_reg(dm, 0x91c, + BIT23 | BIT22 | + BIT21 | BIT20, 15); + else + odm_set_bb_reg(dm, 0x91c, + BIT23 | BIT22 | + BIT21 | BIT20, + short_pw_upperbound + 4); + } + /*@if peak index -1~+1, use original NB method*/ + odm_set_bb_reg(dm, 0x19e4, 0x003C0000, 13); + odm_set_bb_reg(dm, 0x924, 0x70000, 0); + } + + if (dm->support_ic_type & (ODM_RTL8881A)) + odm_set_bb_reg(dm, 0xb00, 0xc0000000, 3); + + /*@for 8814 new dfs mechanism setting*/ + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) { + /*Turn off dfs scaling factor*/ + odm_set_bb_reg(dm, 0x19e4, 0x1fff, 0x0c00); + /*NonDC peak_th = 2times DC peak_th*/ + odm_set_bb_reg(dm, 0x19e4, 0x30000, 1); + /*power for debug and auto test flow latch after ST*/ + odm_set_bb_reg(dm, 0x9f8, 0xc0000000, 3); + + /*@low pulse width radar pattern will cause wrong drop*/ + /*@disable peak index should the same + *during the same short pulse (new mechan) + */ + odm_set_bb_reg(dm, 0x9f4, 0x80000000, 0); + + /*@disable peak index should the same + *during the same short pulse (old mechan) + */ + odm_set_bb_reg(dm, 0x924, 0x20000000, 0); + + /*@if peak index diff >=2, then drop the result*/ + odm_set_bb_reg(dm, 0x19e4, 0xe000, 2); + if (region_domain == 2) { + if ((c_channel >= 52) && (c_channel <= 64)) { + /*pulse width hist th setting*/ + /*th1=2*04us*/ + odm_set_bb_reg(dm, 0x19e4, + 0xff000000, 2); + /*th2 = 3*0.4us, th3 = 4*0.4us + *th4 = 7*0.4, th5 = 34*0.4 + */ + odm_set_bb_reg(dm, 0x19e8, + MASKDWORD, 0x22070403); + + /*PRI hist th setting*/ + /*th1=42*32us*/ + odm_set_bb_reg(dm, 0x19b8, + 0x00007f80, 42); + /*th2=47*32us, th3=115*32us, + *th4=123*32us, th5=130*32us + */ + odm_set_bb_reg(dm, 0x19ec, + MASKDWORD, 0x827b732f); + } else{ + /*pulse width hist th setting*/ + /*th1=2*04us*/ + odm_set_bb_reg(dm, 0x19e4, + 0xff000000, 1); + /*th2 = 13*0.4us, th3 = 26*0.4us + *th4 = 75*0.4us, th5 = 255*0.4us + */ + odm_set_bb_reg(dm, 0x19e8, + MASKDWORD, 0xff4b1a0d); + /*PRI hist th setting*/ + /*th1=4*32us*/ + + odm_set_bb_reg(dm, 0x19b8, + 0x00007f80, 4); + /*th2=8*32us, th3=16*32us, + *th4=32*32us, th5=128*32=4096us + */ + odm_set_bb_reg(dm, 0x19ec, + MASKDWORD, 0x80201008); + } + } + /*@ETSI*/ + else if (region_domain == 3) { + /*pulse width hist th setting*/ + /*th1=2*04us*/ + odm_set_bb_reg(dm, 0x19e4, 0xff000000, 1); + odm_set_bb_reg(dm, 0x19e8, + MASKDWORD, 0x68260d06); + /*PRI hist th setting*/ + /*th1=7*32us*/ + odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 7); + /*th2=40*32us, th3=80*32us, + *th4=110*32us, th5=157*32=5024 + */ + odm_set_bb_reg(dm, 0x19ec, + MASKDWORD, 0x9d6e2010); + } + /*@FCC*/ + else if (region_domain == 1) { + /*pulse width hist th setting*/ + /*th1=2*04us*/ + odm_set_bb_reg(dm, 0x19e4, 0xff000000, 2); + /*th2 = 13*0.4us, th3 = 26*0.4us, + *th4 = 75*0.4us, th5 = 255*0.4us + */ + odm_set_bb_reg(dm, 0x19e8, + MASKDWORD, 0xff4b1a0d); + + /*PRI hist th setting*/ + /*th1=4*32us*/ + odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 4); + /*th2=8*32us, th3=21*32us, + *th4=32*32us, th5=96*32=3072 + */ + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, 0x19ec, + MASKDWORD, 0x60282010); + else + odm_set_bb_reg(dm, 0x19ec, + MASKDWORD, 0x60282420); + } else { + } + } } else { - /* not supported IC type*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Unsupported IC type:%d\n", p_dm_odm->support_ic_type)); + /*not supported IC type*/ + PHYDM_DBG(dm, DBG_DFS, "Unsupported IC type:%d\n", + dm->support_ic_type); goto exit; } enable = 1; - p_dfs->st_l2h_cur = (u8)odm_get_bb_reg(p_dm_odm, 0x91c, 0x000000ff); - p_dfs->pwdb_th = (u8)odm_get_bb_reg(p_dm_odm, 0x918, 0x00001f00); - p_dfs->peak_th = (u8)odm_get_bb_reg(p_dm_odm, 0x918, 0x00030000); - p_dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(p_dm_odm, 0x920, 0x000f0000); - p_dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(p_dm_odm, 0x920, 0x00f00000); - p_dfs->peak_window = (u8)odm_get_bb_reg(p_dm_odm, 0x920, 0x00000300); - p_dfs->nb2wb_th = (u8)odm_get_bb_reg(p_dm_odm, 0x920, 0x0000e000); + dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff); + dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0x918, 0x00001f00); + dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0x918, 0x00030000); + dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920, 0x000f0000); + dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920, 0x00f00000); + dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0x920, 0x00000300); + dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, 0x924, 0x00000180); + dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, 0x924, 0x00007000); - phydm_dfs_parameter_init(p_dm_odm); + phydm_dfs_parameter_init(dm); exit: if (enable) { - phydm_radar_detect_reset(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("on cch:%u, bw:%u\n", c_channel, band_width)); + phydm_radar_detect_reset(dm); + PHYDM_DBG(dm, DBG_DFS, "on cch:%u, bw:%u\n", c_channel, + band_width); } else - phydm_radar_detect_disable(p_dm_odm); + phydm_radar_detect_disable(dm); } -void phydm_dfs_parameter_init(void *p_dm_void) +void phydm_dfs_parameter_init(void *dm_void) { - - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; u8 i; - - p_dfs->fa_mask_th = 30; - p_dfs->det_print = 1; - p_dfs->det_print2 = 0; - p_dfs->st_l2h_min = 0x20; - p_dfs->st_l2h_max = 0x4e; - p_dfs->pwdb_scalar_factor = 12; - p_dfs->pwdb_th = 8; - for(i=0; i<5;i++){ - p_dfs->pulse_flag_hist[i] = 0; - p_dfs->radar_det_mask_hist[i] = 0; - p_dfs->fa_inc_hist[i] = 0; + + dfs->fa_mask_th = 30; + dfs->force_TP_mode = 0; + dfs->det_print = 0; + dfs->det_print2 = 0; + dfs->print_hist_rpt = 0; + dfs->hist_cond_on = 1; + dfs->st_l2h_min = 0x20; + dfs->st_l2h_max = 0x4e; + dfs->pwdb_scalar_factor = 12; + dfs->pwdb_th = 8; + for (i = 0; i < 5; i++) { + dfs->pulse_flag_hist[i] = 0; + dfs->pulse_type_hist[i] = 0; + dfs->radar_det_mask_hist[i] = 0; + dfs->fa_inc_hist[i] = 0; } + /*@for dfs histogram*/ + dfs->pri_hist_th = 5; + dfs->pri_sum_g1_th = 9; + dfs->pri_sum_g5_th = 4; + dfs->pri_sum_g1_fcc_th = 4; /*@FCC Type6*/ + dfs->pri_sum_g3_fcc_th = 6; + dfs->pri_sum_safe_th = 50; + dfs->pri_sum_safe_fcc_th = 110; /*@30 for AP*/ + dfs->pri_sum_type4_th = 16; + dfs->pri_sum_type6_th = 12; + dfs->pri_sum_g5_under_g1_th = 0; + dfs->pri_pw_diff_th = 4; + dfs->pri_pw_diff_fcc_th = 8; + dfs->pri_pw_diff_fcc_idle_th = 2; + dfs->pri_pw_diff_w53_th = 10; + dfs->pw_std_th = 7; /*@FCC Type4*/ + dfs->pw_std_idle_th = 10; + dfs->pri_std_th = 6; /*@FCC Type3,4,6*/ + dfs->pri_std_idle_th = 10; + dfs->pri_type1_upp_fcc_th = 110; + dfs->pri_type1_low_fcc_th = 50; + dfs->pri_type1_cen_fcc_th = 70; + dfs->pw_g0_th = 8; + dfs->pw_long_lower_th = 6; /*@7->6*/ + dfs->pri_long_upper_th = 30; + dfs->pw_long_lower_20m_th = 7; /*@7 for AP*/ + dfs->pw_long_sum_upper_th = 60; + dfs->type4_pw_max_cnt = 7; + dfs->type4_safe_pri_sum_th = 5; } void phydm_dfs_dynamic_setting( - void *p_dm_void -){ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS); - - u8 peak_th_cur=0, short_pulse_cnt_th_cur=0, long_pulse_cnt_th_cur=0, three_peak_opt_cur=0, three_peak_th2_cur=0; - u8 peak_window_cur=0, nb2wb_th_cur=0; - u8 region_domain = p_dm_odm->dfs_region_domain; - u8 c_channel = *(p_dm_odm->p_channel); - - if (p_dm_odm->rx_tp <= 2) { - p_dfs->idle_mode = 1; - if(p_dfs->force_TP_mode) - p_dfs->idle_mode = 0; - } - else{ - p_dfs->idle_mode = 0; - } - - if ((p_dfs->idle_mode == 1)) { /*idle (no traffic)*/ + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + + u8 peak_th_cur = 0, short_pulse_cnt_th_cur = 0; + u8 long_pulse_cnt_th_cur = 0, three_peak_opt_cur = 0; + u8 three_peak_th2_cur = 0; + u8 peak_window_cur = 0; + u8 region_domain = dm->dfs_region_domain; + u8 c_channel = *dm->channel; + + if (dm->rx_tp + dm->tx_tp <= 2) { + dfs->idle_mode = 1; + if (dfs->force_TP_mode) + dfs->idle_mode = 0; + } else { + dfs->idle_mode = 0; + } + + if (dfs->idle_mode == 1) { /*@idle (no traffic)*/ peak_th_cur = 3; short_pulse_cnt_th_cur = 6; - long_pulse_cnt_th_cur = 13; + long_pulse_cnt_th_cur = 9; peak_window_cur = 2; - nb2wb_th_cur = 6; - three_peak_opt_cur = 1; + three_peak_opt_cur = 0; three_peak_th2_cur = 2; - if(region_domain == PHYDM_DFS_DOMAIN_MKK){ - if ((c_channel >= 52) && (c_channel <= 64)) { + if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + if (c_channel >= 52 && c_channel <= 64) { short_pulse_cnt_th_cur = 14; long_pulse_cnt_th_cur = 15; - nb2wb_th_cur = 3; - three_peak_th2_cur = 0; - } - else { + three_peak_th2_cur = 0; + } else { short_pulse_cnt_th_cur = 6; - nb2wb_th_cur = 3; three_peak_th2_cur = 0; long_pulse_cnt_th_cur = 10; } - } - else if(region_domain == PHYDM_DFS_DOMAIN_FCC){ + } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { three_peak_th2_cur = 0; - } - else if(region_domain == PHYDM_DFS_DOMAIN_ETSI){ + } else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { long_pulse_cnt_th_cur = 15; - if(phydm_dfs_is_meteorology_channel(p_dm_odm)){/*need to add check cac end condition*/ + if (phydm_dfs_is_meteorology_channel(dm)) { + /*need to add check cac end condition*/ peak_th_cur = 2; - nb2wb_th_cur = 3; - three_peak_opt_cur = 1; - three_peak_th2_cur = 0; + three_peak_opt_cur = 0; + three_peak_th2_cur = 0; short_pulse_cnt_th_cur = 7; - } - else{ - three_peak_opt_cur = 1; - three_peak_th2_cur = 0; + } else { + three_peak_opt_cur = 0; + three_peak_th2_cur = 0; short_pulse_cnt_th_cur = 7; - nb2wb_th_cur = 3; } - } - else{ /*default: FCC*/ + } else /*@default: FCC*/ three_peak_th2_cur = 0; - } - } - else{ /*in service (with TP)*/ + + } else { /*@in service (with TP)*/ peak_th_cur = 2; short_pulse_cnt_th_cur = 6; - long_pulse_cnt_th_cur = 9; + long_pulse_cnt_th_cur = 7; peak_window_cur = 2; - nb2wb_th_cur = 3; - three_peak_opt_cur = 1; + three_peak_opt_cur = 0; three_peak_th2_cur = 2; - if(region_domain == PHYDM_DFS_DOMAIN_MKK){ - if ((c_channel >= 52) && (c_channel <= 64)) { + if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + if (c_channel >= 52 && c_channel <= 64) { long_pulse_cnt_th_cur = 15; - short_pulse_cnt_th_cur = 5; /*for high duty cycle*/ - three_peak_th2_cur = 0; - } - else { + /*@for high duty cycle*/ + short_pulse_cnt_th_cur = 5; + three_peak_th2_cur = 0; + } else { three_peak_opt_cur = 0; three_peak_th2_cur = 0; long_pulse_cnt_th_cur = 8; } - } - else if(region_domain == PHYDM_DFS_DOMAIN_FCC){ - } - else if(region_domain == PHYDM_DFS_DOMAIN_ETSI){ + } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { + long_pulse_cnt_th_cur = 5; /*for 80M FCC*/ + short_pulse_cnt_th_cur = 5; /*for 80M FCC*/ + } else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { long_pulse_cnt_th_cur = 15; short_pulse_cnt_th_cur = 5; three_peak_opt_cur = 0; } - else{ - } } - + if (dfs->peak_th != peak_th_cur) + odm_set_bb_reg(dm, 0x918, 0x00030000, peak_th_cur); + if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur) + odm_set_bb_reg(dm, 0x920, 0x000f0000, short_pulse_cnt_th_cur); + if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur) + odm_set_bb_reg(dm, 0x920, 0x00f00000, long_pulse_cnt_th_cur); + if (dfs->peak_window != peak_window_cur) + odm_set_bb_reg(dm, 0x920, 0x00000300, peak_window_cur); + if (dfs->three_peak_opt != three_peak_opt_cur) + odm_set_bb_reg(dm, 0x924, 0x00000180, three_peak_opt_cur); + if (dfs->three_peak_th2 != three_peak_th2_cur) + odm_set_bb_reg(dm, 0x924, 0x00007000, three_peak_th2_cur); + + dfs->peak_th = peak_th_cur; + dfs->short_pulse_cnt_th = short_pulse_cnt_th_cur; + dfs->long_pulse_cnt_th = long_pulse_cnt_th_cur; + dfs->peak_window = peak_window_cur; + dfs->three_peak_opt = three_peak_opt_cur; + dfs->three_peak_th2 = three_peak_th2_cur; } - boolean phydm_radar_detect_dm_check( - void *p_dm_void -){ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS); - u8 region_domain = p_dm_odm->dfs_region_domain, index=0; - - u16 i=0, k=0, fa_count_cur=0, fa_count_inc=0, total_fa_in_hist=0, pre_post_now_acc_fa_in_hist=0, max_fa_in_hist=0, vht_crc_ok_cnt_cur=0; - u16 vht_crc_ok_cnt_inc=0, ht_crc_ok_cnt_cur=0, ht_crc_ok_cnt_inc=0, leg_crc_ok_cnt_cur=0, leg_crc_ok_cnt_inc=0; - u16 total_crc_ok_cnt_inc=0, short_pulse_cnt_cur=0, short_pulse_cnt_inc=0, long_pulse_cnt_cur=0, long_pulse_cnt_inc=0, total_pulse_count_inc=0; - u32 regf98_value=0, reg918_value=0, reg91c_value=0, reg920_value=0, reg924_value=0; - boolean tri_short_pulse=0, tri_long_pulse=0, radar_type=0, fault_flag_det=0, fault_flag_psd=0, fa_flag=0, radar_detected=0; - u8 st_l2h_new=0, fa_mask_th=0, sum=0; - u8 c_channel = *(p_dm_odm->p_channel); - - /*Get FA count during past 100ms*/ - fa_count_cur = (u16)odm_get_bb_reg(p_dm_odm, 0xf48, 0x0000ffff); - - if (p_dfs->fa_count_pre == 0) + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + u8 region_domain = dm->dfs_region_domain, index = 0; + + u16 i = 0, j = 0, k = 0, fa_count_cur = 0, fa_count_inc = 0; + u16 total_fa_in_hist = 0, pre_post_now_acc_fa_in_hist = 0; + u16 max_fa_in_hist = 0, vht_crc_ok_cnt_cur = 0; + u16 vht_crc_ok_cnt_inc = 0, ht_crc_ok_cnt_cur = 0; + u16 ht_crc_ok_cnt_inc = 0, leg_crc_ok_cnt_cur = 0; + u16 leg_crc_ok_cnt_inc = 0; + u16 total_crc_ok_cnt_inc = 0, short_pulse_cnt_cur = 0; + u16 short_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0; + u16 long_pulse_cnt_inc = 0, total_pulse_count_inc = 0; + u32 regf98_value = 0, reg918_value = 0, reg91c_value = 0; + u32 reg920_value = 0, reg924_value = 0; + boolean tri_short_pulse = 0, tri_long_pulse = 0, radar_type = 0; + boolean fault_flag_det = 0, fault_flag_psd = 0, fa_flag = 0; + boolean radar_detected = 0; + u8 st_l2h_new = 0, fa_mask_th = 0, sum = 0; + u8 c_channel = *dm->channel; + + /*@Get FA count during past 100ms*/ + fa_count_cur = (u16)odm_get_bb_reg(dm, R_0xf48, 0x0000ffff); + + if (dfs->fa_count_pre == 0) fa_count_inc = 0; - else if (fa_count_cur >= p_dfs->fa_count_pre) - fa_count_inc = fa_count_cur - p_dfs->fa_count_pre; + else if (fa_count_cur >= dfs->fa_count_pre) + fa_count_inc = fa_count_cur - dfs->fa_count_pre; else fa_count_inc = fa_count_cur; - p_dfs->fa_count_pre = fa_count_cur; - - p_dfs->fa_inc_hist[p_dfs->mask_idx] = fa_count_inc; - - for (i=0; i<5; i++) { - total_fa_in_hist = total_fa_in_hist + p_dfs->fa_inc_hist[i]; - if (p_dfs->fa_inc_hist[i] > max_fa_in_hist) - max_fa_in_hist = p_dfs->fa_inc_hist[i]; - } - if (p_dfs->mask_idx >= 2) - index = p_dfs->mask_idx - 2; - else - index = 5 + p_dfs->mask_idx - 2; - if (index == 0) - pre_post_now_acc_fa_in_hist = p_dfs->fa_inc_hist[index] + p_dfs->fa_inc_hist[index+1] + p_dfs->fa_inc_hist[4]; - else if (index == 4) - pre_post_now_acc_fa_in_hist = p_dfs->fa_inc_hist[index] + p_dfs->fa_inc_hist[0] + p_dfs->fa_inc_hist[index-1]; - else - pre_post_now_acc_fa_in_hist = p_dfs->fa_inc_hist[index] + p_dfs->fa_inc_hist[index+1] + p_dfs->fa_inc_hist[index-1]; - - /*Get VHT CRC32 ok count during past 100ms*/ - vht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(p_dm_odm, 0xf0c, 0x00003fff); - if (vht_crc_ok_cnt_cur >= p_dfs->vht_crc_ok_cnt_pre) - vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur - p_dfs->vht_crc_ok_cnt_pre; + dfs->fa_count_pre = fa_count_cur; + + dfs->fa_inc_hist[dfs->mask_idx] = fa_count_inc; + + for (i = 0; i < 5; i++) { + total_fa_in_hist = total_fa_in_hist + dfs->fa_inc_hist[i]; + if (dfs->fa_inc_hist[i] > max_fa_in_hist) + max_fa_in_hist = dfs->fa_inc_hist[i]; + } + if (dfs->mask_idx >= 2) + index = dfs->mask_idx - 2; else + index = 5 + dfs->mask_idx - 2; + if (index == 0) { + pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] + + dfs->fa_inc_hist[index + 1] + + dfs->fa_inc_hist[4]; + } else if (index == 4) { + pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] + + dfs->fa_inc_hist[0] + + dfs->fa_inc_hist[index - 1]; + } else { + pre_post_now_acc_fa_in_hist = dfs->fa_inc_hist[index] + + dfs->fa_inc_hist[index + 1] + + dfs->fa_inc_hist[index - 1]; + } + + /*@Get VHT CRC32 ok count during past 100ms*/ + vht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf0c, 0x00003fff); + if (vht_crc_ok_cnt_cur >= dfs->vht_crc_ok_cnt_pre) { + vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur - + dfs->vht_crc_ok_cnt_pre; + } else { vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur; - p_dfs->vht_crc_ok_cnt_pre = vht_crc_ok_cnt_cur; + } + dfs->vht_crc_ok_cnt_pre = vht_crc_ok_cnt_cur; - /*Get HT CRC32 ok count during past 100ms*/ - ht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(p_dm_odm, 0xf10, 0x00003fff); - if (ht_crc_ok_cnt_cur >= p_dfs->ht_crc_ok_cnt_pre) - ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur - p_dfs->ht_crc_ok_cnt_pre; + /*@Get HT CRC32 ok count during past 100ms*/ + ht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf10, 0x00003fff); + if (ht_crc_ok_cnt_cur >= dfs->ht_crc_ok_cnt_pre) + ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur - dfs->ht_crc_ok_cnt_pre; else ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur; - p_dfs->ht_crc_ok_cnt_pre = ht_crc_ok_cnt_cur; + dfs->ht_crc_ok_cnt_pre = ht_crc_ok_cnt_cur; - /*Get Legacy CRC32 ok count during past 100ms*/ - leg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(p_dm_odm, 0xf14, 0x00003fff); - if (leg_crc_ok_cnt_cur >= p_dfs->leg_crc_ok_cnt_pre) - leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur - p_dfs->leg_crc_ok_cnt_pre; + /*@Get Legacy CRC32 ok count during past 100ms*/ + leg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(dm, R_0xf14, 0x00003fff); + if (leg_crc_ok_cnt_cur >= dfs->leg_crc_ok_cnt_pre) + leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur - dfs->leg_crc_ok_cnt_pre; else leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur; - p_dfs->leg_crc_ok_cnt_pre = leg_crc_ok_cnt_cur; + dfs->leg_crc_ok_cnt_pre = leg_crc_ok_cnt_cur; - if ((vht_crc_ok_cnt_cur == 0x3fff) || - (ht_crc_ok_cnt_cur == 0x3fff) || - (leg_crc_ok_cnt_cur == 0x3fff)) { - odm_set_bb_reg(p_dm_odm, 0xb58, BIT(0), 1); - odm_set_bb_reg(p_dm_odm, 0xb58, BIT(0), 0); + if (vht_crc_ok_cnt_cur == 0x3fff || + ht_crc_ok_cnt_cur == 0x3fff || + leg_crc_ok_cnt_cur == 0x3fff) { + phydm_reset_bb_hw_cnt_ac(dm); + /*@*/ } - total_crc_ok_cnt_inc = vht_crc_ok_cnt_inc + ht_crc_ok_cnt_inc + leg_crc_ok_cnt_inc; + total_crc_ok_cnt_inc = vht_crc_ok_cnt_inc + + ht_crc_ok_cnt_inc + + leg_crc_ok_cnt_inc; - /*Get short pulse count, need carefully handle the counter overflow*/ - regf98_value = odm_get_bb_reg(p_dm_odm, 0xf98, 0xffffffff); - short_pulse_cnt_cur = (u16)regf98_value & 0x000000ff; - if (short_pulse_cnt_cur >= p_dfs->short_pulse_cnt_pre) - short_pulse_cnt_inc = short_pulse_cnt_cur - p_dfs->short_pulse_cnt_pre; - else + /*@Get short pulse count, need carefully handle the counter overflow*/ + regf98_value = odm_get_bb_reg(dm, R_0xf98, 0xffffffff); + short_pulse_cnt_cur = (u16)(regf98_value & 0x000000ff); + if (short_pulse_cnt_cur >= dfs->short_pulse_cnt_pre) { + short_pulse_cnt_inc = short_pulse_cnt_cur - + dfs->short_pulse_cnt_pre; + } else { short_pulse_cnt_inc = short_pulse_cnt_cur; - p_dfs->short_pulse_cnt_pre = short_pulse_cnt_cur; + } + dfs->short_pulse_cnt_pre = short_pulse_cnt_cur; - /*Get long pulse count, need carefully handle the counter overflow*/ + /*@Get long pulse count, need carefully handle the counter overflow*/ long_pulse_cnt_cur = (u16)((regf98_value & 0x0000ff00) >> 8); - if (long_pulse_cnt_cur >= p_dfs->long_pulse_cnt_pre) - long_pulse_cnt_inc = long_pulse_cnt_cur - p_dfs->long_pulse_cnt_pre; - else + if (long_pulse_cnt_cur >= dfs->long_pulse_cnt_pre) { + long_pulse_cnt_inc = long_pulse_cnt_cur - + dfs->long_pulse_cnt_pre; + } else { long_pulse_cnt_inc = long_pulse_cnt_cur; - p_dfs->long_pulse_cnt_pre = long_pulse_cnt_cur; + } + dfs->long_pulse_cnt_pre = long_pulse_cnt_cur; total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc; - if (p_dfs->det_print){ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("=====================================================================\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d]\n", - total_crc_ok_cnt_inc, vht_crc_ok_cnt_inc, ht_crc_ok_cnt_inc, leg_crc_ok_cnt_inc, fa_count_inc)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n", - p_dfs->igi_cur, p_dfs->st_l2h_cur, regf98_value, short_pulse_cnt_inc, long_pulse_cnt_inc)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Throughput: %dMbps\n", p_dm_odm->rx_tp)); - reg918_value = odm_get_bb_reg(p_dm_odm, 0x918, 0xffffffff); - reg91c_value = odm_get_bb_reg(p_dm_odm, 0x91c, 0xffffffff); - reg920_value = odm_get_bb_reg(p_dm_odm, 0x920, 0xffffffff); - reg924_value = odm_get_bb_reg(p_dm_odm, 0x924, 0xffffffff); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n", reg918_value, reg91c_value, reg920_value, reg924_value)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d\n", region_domain, p_dfs->dbg_mode, p_dfs->idle_mode)); - } - tri_short_pulse = (regf98_value & BIT(17))? 1 : 0; - tri_long_pulse = (regf98_value & BIT(19))? 1 : 0; - - if(tri_short_pulse) - radar_type = 0; - else if(tri_long_pulse) - radar_type = 1; + if (dfs->det_print) { + PHYDM_DBG(dm, DBG_DFS, + "===============================================\n"); + PHYDM_DBG(dm, DBG_DFS, + "Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d]\n", + total_crc_ok_cnt_inc, vht_crc_ok_cnt_inc, + ht_crc_ok_cnt_inc, leg_crc_ok_cnt_inc, fa_count_inc); + PHYDM_DBG(dm, DBG_DFS, + "Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n", + dfs->igi_cur, dfs->st_l2h_cur, regf98_value, + short_pulse_cnt_inc, long_pulse_cnt_inc); + PHYDM_DBG(dm, DBG_DFS, "Throughput: %dMbps\n", + dm->rx_tp + dm->tx_tp); + reg918_value = odm_get_bb_reg(dm, R_0x918, + 0xffffffff); + reg91c_value = odm_get_bb_reg(dm, R_0x91c, + 0xffffffff); + reg920_value = odm_get_bb_reg(dm, R_0x920, + 0xffffffff); + reg924_value = odm_get_bb_reg(dm, R_0x924, + 0xffffffff); + PHYDM_DBG(dm, DBG_DFS, + "0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n", + reg918_value, reg91c_value, + reg920_value, reg924_value); + PHYDM_DBG(dm, DBG_DFS, + "dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d, print_hist_rpt = %d, hist_cond_on = %d\n", + region_domain, dfs->dbg_mode, + dfs->idle_mode, dfs->print_hist_rpt, + dfs->hist_cond_on); + } + tri_short_pulse = (regf98_value & BIT(17)) ? 1 : 0; + tri_long_pulse = (regf98_value & BIT(19)) ? 1 : 0; if (tri_short_pulse) { - odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0); - odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 1); + odm_set_bb_reg(dm, R_0x924, BIT(15), 0); + odm_set_bb_reg(dm, R_0x924, BIT(15), 1); } if (tri_long_pulse) { - odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0); - odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 1); - if (region_domain == PHYDM_DFS_DOMAIN_MKK) { - if ((c_channel >= 52) && (c_channel <= 64)) { + odm_set_bb_reg(dm, R_0x924, BIT(15), 0); + odm_set_bb_reg(dm, R_0x924, BIT(15), 1); + if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + if (c_channel >= 52 && c_channel <= 64) { tri_long_pulse = 0; } } @@ -468,203 +713,987 @@ phydm_radar_detect_dm_check( } } - st_l2h_new = p_dfs->st_l2h_cur; - p_dfs->pulse_flag_hist[p_dfs->mask_idx] = tri_short_pulse | tri_long_pulse; + st_l2h_new = dfs->st_l2h_cur; + dfs->pulse_flag_hist[dfs->mask_idx] = tri_short_pulse | tri_long_pulse; + dfs->pulse_type_hist[dfs->mask_idx] = (tri_long_pulse) ? 1 : 0; /* PSD(not ready) */ fault_flag_det = 0; fault_flag_psd = 0; fa_flag = 0; - if(region_domain == PHYDM_DFS_DOMAIN_ETSI){ - fa_mask_th = p_dfs->fa_mask_th + 20; - } - else{ - fa_mask_th = p_dfs->fa_mask_th; - } - if (max_fa_in_hist >= fa_mask_th || total_fa_in_hist >= fa_mask_th || pre_post_now_acc_fa_in_hist >= fa_mask_th || (p_dfs->igi_cur >= 0x30)){ - st_l2h_new = p_dfs->st_l2h_max; - p_dfs->radar_det_mask_hist[index] = 1; - if (p_dfs->pulse_flag_hist[index] == 1){ - p_dfs->pulse_flag_hist[index] = 0; - if (p_dfs->det_print2){ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Radar is masked : FA mask\n")); + if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { + fa_mask_th = dfs->fa_mask_th + 20; + } else { + fa_mask_th = dfs->fa_mask_th; + } + if (max_fa_in_hist >= fa_mask_th || + total_fa_in_hist >= fa_mask_th || + pre_post_now_acc_fa_in_hist >= fa_mask_th || + dfs->igi_cur >= 0x30) { + st_l2h_new = dfs->st_l2h_max; + dfs->radar_det_mask_hist[index] = 1; + if (dfs->pulse_flag_hist[index] == 1) { + dfs->pulse_flag_hist[index] = 0; + if (dfs->det_print2) { + PHYDM_DBG(dm, DBG_DFS, + "Radar is masked : FA mask\n"); } } fa_flag = 1; + } else { + dfs->radar_det_mask_hist[index] = 0; } - if (p_dfs->det_print) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("mask_idx: %d\n", p_dfs->mask_idx)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("radar_det_mask_hist: ")); - for (i=0; i<5; i++) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("%d ", p_dfs->radar_det_mask_hist[i])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("pulse_flag_hist: ")); - for (i=0; i<5; i++) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("%d ", p_dfs->pulse_flag_hist[i])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("fa_inc_hist: ")); - for (i=0; i<5; i++) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("%d ", p_dfs->fa_inc_hist[i])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("\nmax_fa_in_hist: %d pre_post_now_acc_fa_in_hist: %d ",max_fa_in_hist,pre_post_now_acc_fa_in_hist)); + if (dfs->det_print) { + PHYDM_DBG(dm, DBG_DFS, "mask_idx: %d\n", dfs->mask_idx); + PHYDM_DBG(dm, DBG_DFS, "radar_det_mask_hist: "); + for (i = 0; i < 5; i++) + PHYDM_DBG(dm, DBG_DFS, "%d ", + dfs->radar_det_mask_hist[i]); + PHYDM_DBG(dm, DBG_DFS, "pulse_flag_hist: "); + for (i = 0; i < 5; i++) + PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->pulse_flag_hist[i]); + PHYDM_DBG(dm, DBG_DFS, "fa_inc_hist: "); + for (i = 0; i < 5; i++) + PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->fa_inc_hist[i]); + PHYDM_DBG(dm, DBG_DFS, + "\nfa_mask_th: %d max_fa_in_hist: %d total_fa_in_hist: %d pre_post_now_acc_fa_in_hist: %d ", + fa_mask_th, max_fa_in_hist, total_fa_in_hist, + pre_post_now_acc_fa_in_hist); } sum = 0; - for (k=0; k<5; k++) { - if (p_dfs->radar_det_mask_hist[k] == 1) + for (k = 0; k < 5; k++) { + if (dfs->radar_det_mask_hist[k] == 1) sum++; } - if (p_dfs->mask_hist_checked <= 5) - p_dfs->mask_hist_checked++; + if (dfs->mask_hist_checked <= 5) + dfs->mask_hist_checked++; - if ((p_dfs->mask_hist_checked >= 5) && p_dfs->pulse_flag_hist[index]) - { - if (sum <= 2) - { - radar_detected = 1 ; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Detected type %d radar signal!\n", radar_type)); - } - else { + if (dfs->mask_hist_checked >= 5 && dfs->pulse_flag_hist[index]) { + if (sum <= 2) { + if (dfs->hist_cond_on) { + /*return the value from hist_radar_detected*/ + radar_detected = phydm_dfs_hist_log(dm, index); + } else { + if (dfs->pulse_type_hist[index] == 0) + dfs->radar_type = 0; + else if (dfs->pulse_type_hist[index] == 1) + dfs->radar_type = 1; + radar_detected = 1; + PHYDM_DBG(dm, DBG_DFS, + "Detected type %d radar signal!\n", + dfs->radar_type); + } + } else { fault_flag_det = 1; - if (p_dfs->det_print2){ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Radar is masked : mask_hist large than thd\n")); + if (dfs->det_print2) { + PHYDM_DBG(dm, DBG_DFS, + "Radar is masked : mask_hist large than thd\n"); } } } - p_dfs->mask_idx++; - if (p_dfs->mask_idx == 5) - p_dfs->mask_idx = 0; - - if ((fault_flag_det == 0) && (fault_flag_psd == 0) && (fa_flag ==0)) { - if (p_dfs->igi_cur < 0x30) { - st_l2h_new = p_dfs->st_l2h_min; + dfs->mask_idx++; + if (dfs->mask_idx == 5) + dfs->mask_idx = 0; + + if (fault_flag_det == 0 && fault_flag_psd == 0 && fa_flag == 0) { + if (dfs->igi_cur < 0x30) { + st_l2h_new = dfs->st_l2h_min; } } - - if ((st_l2h_new != p_dfs->st_l2h_cur)) { - if (st_l2h_new < p_dfs->st_l2h_min) { - p_dfs->st_l2h_cur = p_dfs->st_l2h_min; - } - else if (st_l2h_new > p_dfs->st_l2h_max) - p_dfs->st_l2h_cur = p_dfs->st_l2h_max; + + if (st_l2h_new != dfs->st_l2h_cur) { + if (st_l2h_new < dfs->st_l2h_min) { + dfs->st_l2h_cur = dfs->st_l2h_min; + } else if (st_l2h_new > dfs->st_l2h_max) + dfs->st_l2h_cur = dfs->st_l2h_max; else - p_dfs->st_l2h_cur = st_l2h_new; - odm_set_bb_reg(p_dm_odm, 0x91c, 0xff, p_dfs->st_l2h_cur); + dfs->st_l2h_cur = st_l2h_new; + /*odm_set_bb_reg(dm, R_0x91c, 0xff, dfs->st_l2h_cur);*/ + + dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur) + / 2 + dfs->pwdb_scalar_factor; + + /*@limit the pwdb value to absolute lower bound 8*/ + dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th); - p_dfs->pwdb_th = ((int)p_dfs->st_l2h_cur - (int)p_dfs->igi_cur)/2 + p_dfs->pwdb_scalar_factor; - p_dfs->pwdb_th = MAX_2(p_dfs->pwdb_th, (int)p_dfs->pwdb_th); /*limit the pwdb value to absoulte lower bound 8*/ - p_dfs->pwdb_th = MIN_2(p_dfs->pwdb_th, 0x1f); /*limit the pwdb value to absoulte upper bound 0x1f*/ - odm_set_bb_reg(p_dm_odm, 0x918, 0x00001f00, p_dfs->pwdb_th); + /*@limit the pwdb value to absolute upper bound 0x1f*/ + dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f); + odm_set_bb_reg(dm, R_0x918, 0x00001f00, dfs->pwdb_th_cur); } - if (p_dfs->det_print2) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n",fault_flag_det, fault_flag_psd, radar_detected)); + if (dfs->det_print) { + PHYDM_DBG(dm, DBG_DFS, + "fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n", + fault_flag_det, fault_flag_psd, radar_detected); } return radar_detected; +} +void phydm_dfs_histogram_radar_distinguish( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + u8 region_domain = dm->dfs_region_domain; + u8 c_channel = *dm->channel; + u8 band_width = *dm->band_width; + + u8 dfs_pw_thd1 = 0, dfs_pw_thd2 = 0, dfs_pw_thd3 = 0; + u8 dfs_pw_thd4 = 0, dfs_pw_thd5 = 0; + u8 dfs_pri_thd1 = 0, dfs_pri_thd2 = 0, dfs_pri_thd3 = 0; + u8 dfs_pri_thd4 = 0, dfs_pri_thd5 = 0; + u8 pri_th = 0, i = 0; + u8 max_pri_idx = 0, max_pw_idx = 0, max_pri_cnt_th = 0; + u8 max_pri_cnt_fcc_g1_th = 0, max_pri_cnt_fcc_g3_th = 0; + u8 safe_pri_pw_diff_th = 0, safe_pri_pw_diff_fcc_th = 0; + u8 safe_pri_pw_diff_w53_th = 0, safe_pri_pw_diff_fcc_idle_th = 0; + u16 j = 0; + u32 dfs_hist1_peak_index = 0, dfs_hist2_peak_index = 0; + u32 dfs_hist1_pw = 0, dfs_hist2_pw = 0, g_pw[6] = {0}; + u32 g_peakindex[16] = {0}, g_mask_32 = 0, false_peak_hist1 = 0; + u32 false_peak_hist2_above10 = 0, false_peak_hist2_above0 = 0; + u32 dfs_hist1_pri = 0, dfs_hist2_pri = 0, g_pri[6] = {0}; + u32 pw_sum_g0g5 = 0, pw_sum_g1g2g3g4 = 0; + u32 pri_sum_g0g5 = 0, pri_sum_g1g2g3g4 = 0; + u32 pw_sum_ss_g1g2g3g4 = 0, pri_sum_ss_g1g2g3g4 = 0; + u32 max_pri_cnt = 0, max_pw_cnt = 0; + + /*read peak index hist report*/ + odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x0); + dfs_hist1_peak_index = odm_get_bb_reg(dm, 0xf5c, 0xffffffff); + dfs_hist2_peak_index = odm_get_bb_reg(dm, 0xf74, 0xffffffff); + + g_peakindex[15] = ((dfs_hist1_peak_index & 0x0000000f) >> 0); + g_peakindex[14] = ((dfs_hist1_peak_index & 0x000000f0) >> 4); + g_peakindex[13] = ((dfs_hist1_peak_index & 0x00000f00) >> 8); + g_peakindex[12] = ((dfs_hist1_peak_index & 0x0000f000) >> 12); + g_peakindex[11] = ((dfs_hist1_peak_index & 0x000f0000) >> 16); + g_peakindex[10] = ((dfs_hist1_peak_index & 0x00f00000) >> 20); + g_peakindex[9] = ((dfs_hist1_peak_index & 0x0f000000) >> 24); + g_peakindex[8] = ((dfs_hist1_peak_index & 0xf0000000) >> 28); + g_peakindex[7] = ((dfs_hist2_peak_index & 0x0000000f) >> 0); + g_peakindex[6] = ((dfs_hist2_peak_index & 0x000000f0) >> 4); + g_peakindex[5] = ((dfs_hist2_peak_index & 0x00000f00) >> 8); + g_peakindex[4] = ((dfs_hist2_peak_index & 0x0000f000) >> 12); + g_peakindex[3] = ((dfs_hist2_peak_index & 0x000f0000) >> 16); + g_peakindex[2] = ((dfs_hist2_peak_index & 0x00f00000) >> 20); + g_peakindex[1] = ((dfs_hist2_peak_index & 0x0f000000) >> 24); + g_peakindex[0] = ((dfs_hist2_peak_index & 0xf0000000) >> 28); + + /*read pulse width hist report*/ + odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x1); + dfs_hist1_pw = odm_get_bb_reg(dm, 0xf5c, 0xffffffff); + dfs_hist2_pw = odm_get_bb_reg(dm, 0xf74, 0xffffffff); + + g_pw[0] = (unsigned int)((dfs_hist2_pw & 0xff000000) >> 24); + g_pw[1] = (unsigned int)((dfs_hist2_pw & 0x00ff0000) >> 16); + g_pw[2] = (unsigned int)((dfs_hist2_pw & 0x0000ff00) >> 8); + g_pw[3] = (unsigned int)dfs_hist2_pw & 0x000000ff; + g_pw[4] = (unsigned int)((dfs_hist1_pw & 0xff000000) >> 24); + g_pw[5] = (unsigned int)((dfs_hist1_pw & 0x00ff0000) >> 16); + + /*read pulse repetition interval hist report*/ + odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x3); + dfs_hist1_pri = odm_get_bb_reg(dm, 0xf5c, 0xffffffff); + dfs_hist2_pri = odm_get_bb_reg(dm, 0xf74, 0xffffffff); + odm_set_bb_reg(dm, 0x19b4, 0x10000000, 1); /*reset histo report*/ + odm_set_bb_reg(dm, 0x19b4, 0x10000000, 0); /*@continue histo report*/ + + g_pri[0] = (unsigned int)((dfs_hist2_pri & 0xff000000) >> 24); + g_pri[1] = (unsigned int)((dfs_hist2_pri & 0x00ff0000) >> 16); + g_pri[2] = (unsigned int)((dfs_hist2_pri & 0x0000ff00) >> 8); + g_pri[3] = (unsigned int)dfs_hist2_pri & 0x000000ff; + g_pri[4] = (unsigned int)((dfs_hist1_pri & 0xff000000) >> 24); + g_pri[5] = (unsigned int)((dfs_hist1_pri & 0x00ff0000) >> 16); + + dfs->pri_cond1 = 0; + dfs->pri_cond2 = 0; + dfs->pri_cond3 = 0; + dfs->pri_cond4 = 0; + dfs->pri_cond5 = 0; + dfs->pw_cond1 = 0; + dfs->pw_cond2 = 0; + dfs->pw_cond3 = 0; + dfs->pri_type3_4_cond1 = 0; /*@for ETSI*/ + dfs->pri_type3_4_cond2 = 0; /*@for ETSI*/ + dfs->pw_long_cond1 = 0; /*@for long radar*/ + dfs->pw_long_cond2 = 0; /*@for long radar*/ + dfs->pri_long_cond1 = 0; /*@for long radar*/ + dfs->pw_flag = 0; + dfs->pri_flag = 0; + dfs->pri_type3_4_flag = 0; /*@for ETSI*/ + dfs->long_radar_flag = 0; + dfs->pw_std = 0; /*The std(var) of reasonable num of pw group*/ + dfs->pri_std = 0; /*The std(var) of reasonable num of pri group*/ + + for (i = 0; i < 6; i++) { + dfs->pw_hold_sum[i] = 0; + dfs->pri_hold_sum[i] = 0; + dfs->pw_long_hold_sum[i] = 0; + dfs->pri_long_hold_sum[i] = 0; + } + + if (dfs->idle_mode == 1) + pri_th = dfs->pri_hist_th; + else + pri_th = dfs->pri_hist_th - 1; + + for (i = 0; i < 6; i++) { + dfs->pw_hold[dfs->hist_idx][i] = (u8)g_pw[i]; + dfs->pri_hold[dfs->hist_idx][i] = (u8)g_pri[i]; + /*@collect whole histogram report may take some time + *so we add the counter of 2 time slots in FCC and ETSI + */ + if (region_domain == 1 || region_domain == 3) { + dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] + + dfs->pw_hold[(dfs->hist_idx + 1) % 3][i] + + dfs->pw_hold[(dfs->hist_idx + 2) % 3][i]; + dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] + + dfs->pri_hold[(dfs->hist_idx + 1) % 3][i] + + dfs->pri_hold[(dfs->hist_idx + 2) % 3][i]; + } else{ + /*@collect whole histogram report may take some time, + *so we add the counter of 3 time slots in MKK or else + */ + dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] + + dfs->pw_hold[(dfs->hist_idx + 1) % 4][i] + + dfs->pw_hold[(dfs->hist_idx + 2) % 4][i] + + dfs->pw_hold[(dfs->hist_idx + 3) % 4][i]; + dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] + + dfs->pri_hold[(dfs->hist_idx + 1) % 4][i] + + dfs->pri_hold[(dfs->hist_idx + 2) % 4][i] + + dfs->pri_hold[(dfs->hist_idx + 3) % 4][i]; + } + } + /*@For long radar type*/ + for (i = 0; i < 6; i++) { + dfs->pw_long_hold[dfs->hist_long_idx][i] = (u8)g_pw[i]; + dfs->pri_long_hold[dfs->hist_long_idx][i] = (u8)g_pri[i]; + /*@collect whole histogram report may take some time, + *so we add the counter of 299 time slots for long radar + */ + for (j = 1; j < 300; j++) { + dfs->pw_long_hold_sum[i] = dfs->pw_long_hold_sum[i] + + dfs->pw_long_hold[(dfs->hist_long_idx + j) % 300][i]; + dfs->pri_long_hold_sum[i] = dfs->pri_long_hold_sum[i] + + dfs->pri_long_hold[(dfs->hist_long_idx + j) % 300][i]; + } + } + dfs->hist_idx++; + dfs->hist_long_idx++; + if (dfs->hist_long_idx == 300) + dfs->hist_long_idx = 0; + if (region_domain == 1 || region_domain == 3) { + if (dfs->hist_idx == 3) + dfs->hist_idx = 0; + } else if (dfs->hist_idx == 4) { + dfs->hist_idx = 0; + } + + max_pri_cnt = 0; + max_pri_idx = 0; + max_pw_cnt = 0; + max_pw_idx = 0; + max_pri_cnt_th = dfs->pri_sum_g1_th; + max_pri_cnt_fcc_g1_th = dfs->pri_sum_g1_fcc_th; + max_pri_cnt_fcc_g3_th = dfs->pri_sum_g3_fcc_th; + safe_pri_pw_diff_th = dfs->pri_pw_diff_th; + safe_pri_pw_diff_fcc_th = dfs->pri_pw_diff_fcc_th; + safe_pri_pw_diff_fcc_idle_th = dfs->pri_pw_diff_fcc_idle_th; + safe_pri_pw_diff_w53_th = dfs->pri_pw_diff_w53_th; + + /*@g1 to g4 is the reseasonable range of pri and pw*/ + for (i = 1; i <= 4; i++) { + if (dfs->pri_hold_sum[i] > max_pri_cnt) { + max_pri_cnt = dfs->pri_hold_sum[i]; + max_pri_idx = i; + } + if (dfs->pw_hold_sum[i] > max_pw_cnt) { + max_pw_cnt = dfs->pw_hold_sum[i]; + max_pw_idx = i; + } + if (dfs->pri_hold_sum[i] >= pri_th) + dfs->pri_cond1 = 1; + } + + pri_sum_g0g5 = dfs->pri_hold_sum[0]; + if (pri_sum_g0g5 == 0) + pri_sum_g0g5 = 1; + pri_sum_g1g2g3g4 = dfs->pri_hold_sum[1] + dfs->pri_hold_sum[2] + + dfs->pri_hold_sum[3] + dfs->pri_hold_sum[4]; + + /*pw will reduce because of dc, so we do not treat g0 as illegal group*/ + pw_sum_g0g5 = dfs->pw_hold_sum[5]; + if (pw_sum_g0g5 == 0) + pw_sum_g0g5 = 1; + pw_sum_g1g2g3g4 = dfs->pw_hold_sum[1] + dfs->pw_hold_sum[2] + + dfs->pw_hold_sum[3] + dfs->pw_hold_sum[4]; + + /*@Calculate the variation from g1 to g4*/ + for (i = 1; i < 5; i++) { + /*Sum of square*/ + pw_sum_ss_g1g2g3g4 = pw_sum_ss_g1g2g3g4 + + (dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4)) * + (dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4)); + pri_sum_ss_g1g2g3g4 = pri_sum_ss_g1g2g3g4 + + (dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4)) * + (dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4)); + } + /*The value may less than the normal variance, + *since the variable type is int (not float) + */ + dfs->pw_std = (u16)(pw_sum_ss_g1g2g3g4 / 4); + dfs->pri_std = (u16)(pri_sum_ss_g1g2g3g4 / 4); + + if (region_domain == 1) { + dfs->pri_type3_4_flag = 1; /*@ETSI flag*/ + + /*PRI judgment conditions for short radar type*/ + /*ratio of reasonable group and illegal group && + *pri variation of short radar should be large (=6) + */ + if (max_pri_idx != 4 && dfs->pri_hold_sum[5] > 0) + dfs->pri_cond2 = 0; + else + dfs->pri_cond2 = 1; + + /*reasonable group shouldn't large*/ + if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2 && + pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th) + dfs->pri_cond3 = 1; + + /*@Cancel the condition that the abs between pri and pw*/ + if (dfs->pri_std >= dfs->pri_std_th) + dfs->pri_cond4 = 1; + else if (max_pri_idx == 1 && + max_pri_cnt >= max_pri_cnt_fcc_g1_th) + dfs->pri_cond4 = 1; + + /*we set threshold = 7 (>4) for distinguishing type 3,4 (g3)*/ + if (max_pri_idx == 1 && dfs->pri_hold_sum[3] + + dfs->pri_hold_sum[4] + dfs->pri_hold_sum[5] > 0) + dfs->pri_cond5 = 0; + else + dfs->pri_cond5 = 1; + + if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 && + dfs->pri_cond4 && dfs->pri_cond5) + dfs->pri_flag = 1; + + /* PW judgment conditions for short radar type */ + /*ratio of reasonable and illegal group && g5 should be zero*/ + if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) && + (dfs->pw_hold_sum[5] <= 1)) + dfs->pw_cond1 = 1; + /*unreasonable group*/ + if (dfs->pw_hold_sum[4] == 0 && dfs->pw_hold_sum[5] == 0) + dfs->pw_cond2 = 1; + /*pw's std (short radar) should be large(=7)*/ + if (dfs->pw_std >= dfs->pw_std_th) + dfs->pw_cond3 = 1; + if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3) + dfs->pw_flag = 1; + + /* @Judgment conditions of long radar type */ + if (band_width == CHANNEL_WIDTH_20) { + if (dfs->pw_long_hold_sum[4] >= + dfs->pw_long_lower_20m_th) + dfs->pw_long_cond1 = 1; + } else{ + if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th) + dfs->pw_long_cond1 = 1; + } + /* @Disable the condition that dfs->pw_long_hold_sum[1] */ + if (dfs->pw_long_hold_sum[2] + dfs->pw_long_hold_sum[3] + + dfs->pw_long_hold_sum[4] <= dfs->pw_long_sum_upper_th && + dfs->pw_long_hold_sum[2] <= dfs->pw_long_hold_sum[4] && + dfs->pw_long_hold_sum[3] <= dfs->pw_long_hold_sum[4]) + dfs->pw_long_cond2 = 1; + /*@g4 should be large for long radar*/ + if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th) + dfs->pri_long_cond1 = 1; + if (dfs->pw_long_cond1 && dfs->pw_long_cond2 && + dfs->pri_long_cond1) + dfs->long_radar_flag = 1; + } else if (region_domain == 2) { + dfs->pri_type3_4_flag = 1; /*@ETSI flag*/ + + /*PRI judgment conditions for short radar type*/ + if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2) + dfs->pri_cond2 = 1; + + /*reasonable group shouldn't too large*/ + if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th) + dfs->pri_cond3 = 1; + + /*the difference between pri and pw for idle mode (thr=2)*/ + if (dfs->idle_mode == 1) { + if (abs(pw_sum_g1g2g3g4 - pri_sum_g1g2g3g4) <= + safe_pri_pw_diff_fcc_idle_th) + dfs->pri_cond4 = 1; + } else{ + if ((c_channel >= 52) && (c_channel <= 64)) { + /*the difference between pri and pw for w53 TP mode (thr=15)*/ + if (abs(pw_sum_g1g2g3g4 - pri_sum_g1g2g3g4) <= + safe_pri_pw_diff_w53_th) + dfs->pri_cond4 = 1; + } else { + /*the difference between pri and pw for TP mode (thr=8)*/ + if (abs(pw_sum_g1g2g3g4 - pri_sum_g1g2g3g4) <= + safe_pri_pw_diff_fcc_th) + dfs->pri_cond4 = 1; + } + } + + if (dfs->idle_mode == 1) { + if (dfs->pri_std >= dfs->pri_std_idle_th) { + if (max_pw_idx == 3 && + pri_sum_g1g2g3g4 <= dfs->pri_sum_type4_th){ + /*To distinguish between type 4 radar and false detection*/ + dfs->pri_cond5 = 1; + } else if (max_pw_idx == 1 && + pri_sum_g1g2g3g4 >= + dfs->pri_sum_type6_th) { + /*To distinguish between type 6 radar and false detection*/ + dfs->pri_cond5 = 1; + } else { + /*pri variation of short radar should be large (idle mode)*/ + dfs->pri_cond5 = 1; + } + } + } else { + /*pri variation of short radar should be large (TP mode)*/ + if (dfs->pri_std >= dfs->pri_std_th) + dfs->pri_cond5 = 1; + } + + if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 && + dfs->pri_cond4 && dfs->pri_cond5) + dfs->pri_flag = 1; + + /* PW judgment conditions for short radar type */ + if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) && + (dfs->pw_hold_sum[5] <= 1)) + /*ratio of reasonable and illegal group && g5 should be zero*/ + dfs->pw_cond1 = 1; + + if ((c_channel >= 52) && (c_channel <= 64)) + dfs->pw_cond2 = 1; + /*unreasonable group shouldn't too large*/ + else if (dfs->pw_hold_sum[0] <= dfs->pw_g0_th) + dfs->pw_cond2 = 1; + + if (dfs->idle_mode == 1) { + /*pw variation of short radar should be large (idle mode)*/ + if (dfs->pw_std >= dfs->pw_std_idle_th) + dfs->pw_cond3 = 1; + } else { + /*pw variation of short radar should be large (TP mode)*/ + if (dfs->pw_std >= dfs->pw_std_th) + dfs->pw_cond3 = 1; + } + if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3) + dfs->pw_flag = 1; + + /* @Judgment conditions of long radar type */ + if (band_width == CHANNEL_WIDTH_20) { + if (dfs->pw_long_hold_sum[4] >= + dfs->pw_long_lower_20m_th) + dfs->pw_long_cond1 = 1; + } else{ + if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th) + dfs->pw_long_cond1 = 1; + } + if (dfs->pw_long_hold_sum[1] + dfs->pw_long_hold_sum[2] + + dfs->pw_long_hold_sum[3] + dfs->pw_long_hold_sum[4] + <= dfs->pw_long_sum_upper_th) + dfs->pw_long_cond2 = 1; + /*@g4 should be large for long radar*/ + if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th) + dfs->pri_long_cond1 = 1; + if (dfs->pw_long_cond1 && + dfs->pw_long_cond2 && dfs->pri_long_cond1) + dfs->long_radar_flag = 1; + } else if (region_domain == 3) { + /*ratio of reasonable group and illegal group */ + if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2) + dfs->pri_cond2 = 1; + + if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_th) + dfs->pri_cond3 = 1; + + /*@Cancel the condition that the abs between pri and pw*/ + dfs->pri_cond4 = 1; + + if (dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_th) + dfs->pri_cond5 = 1; + + if (band_width == CHANNEL_WIDTH_40) { + if (max_pw_idx == 4) { + if (max_pw_cnt >= dfs->type4_pw_max_cnt && + pri_sum_g1g2g3g4 >= + dfs->type4_safe_pri_sum_th) { + dfs->pri_cond1 = 1; + dfs->pri_cond4 = 1; + dfs->pri_type3_4_cond1 = 1; + } + } + } + + if (dfs->pri_cond1 && dfs->pri_cond2 && + dfs->pri_cond3 && dfs->pri_cond4 && dfs->pri_cond5) + dfs->pri_flag = 1; + + if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) && + (dfs->pw_hold_sum[5] == 0)) + dfs->pw_flag = 1; + + /*@max num pri group is g1 means radar type3 or type4*/ + if (max_pri_idx == 1) { + if (max_pri_cnt >= max_pri_cnt_th) + dfs->pri_type3_4_cond1 = 1; + if (dfs->pri_hold_sum[4] <= + dfs->pri_sum_g5_under_g1_th && + dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_under_g1_th) + dfs->pri_type3_4_cond2 = 1; + } else { + dfs->pri_type3_4_cond1 = 1; + dfs->pri_type3_4_cond2 = 1; + } + if (dfs->pri_type3_4_cond1 && dfs->pri_type3_4_cond2) + dfs->pri_type3_4_flag = 1; + } else { + } + + if (dfs->print_hist_rpt) { + dfs_pw_thd1 = (u8)odm_get_bb_reg(dm, 0x19e4, 0xff000000); + dfs_pw_thd2 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x000000ff); + dfs_pw_thd3 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x0000ff00); + dfs_pw_thd4 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x00ff0000); + dfs_pw_thd5 = (u8)odm_get_bb_reg(dm, 0x19e8, 0xff000000); + + dfs_pri_thd1 = (u8)odm_get_bb_reg(dm, 0x19b8, 0x7F80); + dfs_pri_thd2 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x000000ff); + dfs_pri_thd3 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x0000ff00); + dfs_pri_thd4 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x00ff0000); + dfs_pri_thd5 = (u8)odm_get_bb_reg(dm, 0x19ec, 0xff000000); + + PHYDM_DBG(dm, DBG_DFS, "peak index hist\n"); + PHYDM_DBG(dm, DBG_DFS, "dfs_hist_peak_index=%x %x\n", + dfs_hist1_peak_index, dfs_hist2_peak_index); + PHYDM_DBG(dm, DBG_DFS, "g_peak_index_hist = "); + for (i = 0; i < 16; i++) + PHYDM_DBG(dm, DBG_DFS, " %x", g_peakindex[i]); + PHYDM_DBG(dm, DBG_DFS, "\ndfs_pw_thd=%d %d %d %d %d\n", + dfs_pw_thd1, dfs_pw_thd2, dfs_pw_thd3, + dfs_pw_thd4, dfs_pw_thd5); + PHYDM_DBG(dm, DBG_DFS, "-----pulse width hist-----\n"); + PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pw=%x %x\n", + dfs_hist1_pw, dfs_hist2_pw); + PHYDM_DBG(dm, DBG_DFS, "g_pw_hist = %x %x %x %x %x %x\n", + g_pw[0], g_pw[1], g_pw[2], g_pw[3], + g_pw[4], g_pw[5]); + PHYDM_DBG(dm, DBG_DFS, "dfs_pri_thd=%d %d %d %d %d\n", + dfs_pri_thd1, dfs_pri_thd2, dfs_pri_thd3, + dfs_pri_thd4, dfs_pri_thd5); + PHYDM_DBG(dm, DBG_DFS, "-----pulse interval hist-----\n"); + PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pri=%x %x\n", + dfs_hist1_pri, dfs_hist2_pri); + PHYDM_DBG(dm, DBG_DFS, + "g_pri_hist = %x %x %x %x %x %x, pw_flag = %d, pri_flag = %d\n", + g_pri[0], g_pri[1], g_pri[2], g_pri[3], g_pri[4], + g_pri[5], dfs->pw_flag, dfs->pri_flag); + if (region_domain == 1 || region_domain == 3) { + PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n", + (dfs->hist_idx + 2) % 3); + } else { + PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n", + (dfs->hist_idx + 3) % 4); + } + PHYDM_DBG(dm, DBG_DFS, "hist_long_idx= %d\n", + (dfs->hist_long_idx + 299) % 300); + PHYDM_DBG(dm, DBG_DFS, + "pw_sum_g0g5 = %d, pw_sum_g1g2g3g4 = %d\n", + pw_sum_g0g5, pw_sum_g1g2g3g4); + PHYDM_DBG(dm, DBG_DFS, + "pri_sum_g0g5 = %d, pri_sum_g1g2g3g4 = %d\n", + pri_sum_g0g5, pri_sum_g1g2g3g4); + PHYDM_DBG(dm, DBG_DFS, "pw_hold_sum = %d %d %d %d %d %d\n", + dfs->pw_hold_sum[0], dfs->pw_hold_sum[1], + dfs->pw_hold_sum[2], dfs->pw_hold_sum[3], + dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, "pri_hold_sum = %d %d %d %d %d %d\n", + dfs->pri_hold_sum[0], dfs->pri_hold_sum[1], + dfs->pri_hold_sum[2], dfs->pri_hold_sum[3], + dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, "pw_long_hold_sum = %d %d %d %d %d %d\n", + dfs->pw_long_hold_sum[0], dfs->pw_long_hold_sum[1], + dfs->pw_long_hold_sum[2], dfs->pw_long_hold_sum[3], + dfs->pw_long_hold_sum[4], dfs->pw_long_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, + "pri_long_hold_sum = %d %d %d %d %d %d\n", + dfs->pri_long_hold_sum[0], dfs->pri_long_hold_sum[1], + dfs->pri_long_hold_sum[2], dfs->pri_long_hold_sum[3], + dfs->pri_long_hold_sum[4], dfs->pri_long_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", dfs->idle_mode); + PHYDM_DBG(dm, DBG_DFS, "pw_standard = %d\n", dfs->pw_std); + PHYDM_DBG(dm, DBG_DFS, "pri_standard = %d\n", dfs->pri_std); + for (j = 0; j < 4; j++) { + for (i = 0; i < 6; i++) { + PHYDM_DBG(dm, DBG_DFS, "pri_hold = %d ", + dfs->pri_hold[j][i]); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + PHYDM_DBG(dm, DBG_DFS, + "pri_cond1 = %d, pri_cond2 = %d, pri_cond3 = %d, pri_cond4 = %d, pri_cond5 = %d\n", + dfs->pri_cond1, dfs->pri_cond2, dfs->pri_cond3, + dfs->pri_cond4, dfs->pri_cond5); + PHYDM_DBG(dm, DBG_DFS, + "bandwidth = %d, pri_th = %d, max_pri_cnt_th = %d, safe_pri_pw_diff_th = %d\n", + band_width, pri_th, max_pri_cnt_th, + safe_pri_pw_diff_th); + } } -boolean phydm_radar_detect(void *p_dm_void) +boolean phydm_dfs_hist_log(void *dm_void, u8 index) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + u8 i = 0, j = 0; + boolean hist_radar_detected = 0; + + if (dfs->pulse_type_hist[index] == 0) { + dfs->radar_type = 0; + if (dfs->pw_flag && dfs->pri_flag && + dfs->pri_type3_4_flag) { + hist_radar_detected = 1; + PHYDM_DBG(dm, DBG_DFS, + "Detected type %d radar signal!\n", + dfs->radar_type); + if (dfs->det_print2) { + PHYDM_DBG(dm, DBG_DFS, + "hist_idx= %d\n", + (dfs->hist_idx + 3) % 4); + for (j = 0; j < 4; j++) { + for (i = 0; i < 6; i++) { + PHYDM_DBG(dm, DBG_DFS, + "pri_hold = %d ", + dfs->pri_hold[j][i]); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + for (j = 0; j < 4; j++) { + for (i = 0; i < 6; i++) { + PHYDM_DBG(dm, DBG_DFS, "pw_hold = %d ", + dfs->pw_hold[j][i]); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", + dfs->idle_mode); + PHYDM_DBG(dm, DBG_DFS, + "pw_hold_sum = %d %d %d %d %d %d\n", + dfs->pw_hold_sum[0], + dfs->pw_hold_sum[1], + dfs->pw_hold_sum[2], + dfs->pw_hold_sum[3], + dfs->pw_hold_sum[4], + dfs->pw_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, + "pri_hold_sum = %d %d %d %d %d %d\n", + dfs->pri_hold_sum[0], + dfs->pri_hold_sum[1], + dfs->pri_hold_sum[2], + dfs->pri_hold_sum[3], + dfs->pri_hold_sum[4], + dfs->pri_hold_sum[5]); + } + } else { + if (dfs->det_print2) { + if (dfs->pulse_flag_hist[index] && + dfs->pri_flag == 0) { + PHYDM_DBG(dm, DBG_DFS, "pri_variation = %d\n", + dfs->pri_std); + PHYDM_DBG(dm, DBG_DFS, + "PRI criterion is not satisfied!\n"); + if (dfs->pri_cond1 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_cond1 is not satisfied!\n"); + if (dfs->pri_cond2 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_cond2 is not satisfied!\n"); + if (dfs->pri_cond3 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_cond3 is not satisfied!\n"); + if (dfs->pri_cond4 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_cond4 is not satisfied!\n"); + if (dfs->pri_cond5 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_cond5 is not satisfied!\n"); + } + if (dfs->pulse_flag_hist[index] && + dfs->pw_flag == 0) { + PHYDM_DBG(dm, DBG_DFS, "pw_variation = %d\n", + dfs->pw_std); + PHYDM_DBG(dm, DBG_DFS, + "PW criterion is not satisfied!\n"); + if (dfs->pw_cond1 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pw_cond1 is not satisfied!\n"); + if (dfs->pw_cond2 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pw_cond2 is not satisfied!\n"); + if (dfs->pw_cond3 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pw_cond3 is not satisfied!\n"); + } + if (dfs->pulse_flag_hist[index] && + (dfs->pri_type3_4_flag == 0)) { + PHYDM_DBG(dm, DBG_DFS, + "pri_type3_4 criterion is not satisfied!\n"); + if (dfs->pri_type3_4_cond1 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_type3_4_cond1 is not satisfied!\n"); + if (dfs->pri_type3_4_cond2 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_type3_4_cond2 is not satisfied!\n"); + } + PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n", + (dfs->hist_idx + 3) % 4); + for (j = 0; j < 4; j++) { + for (i = 0; i < 6; i++) { + PHYDM_DBG(dm, DBG_DFS, + "pri_hold = %d ", + dfs->pri_hold[j][i]); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + for (j = 0; j < 4; j++) { + for (i = 0; i < 6; i++) + PHYDM_DBG(dm, DBG_DFS, + "pw_hold = %d ", + dfs->pw_hold[j][i]); + PHYDM_DBG(dm, DBG_DFS, "\n"); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", + dfs->idle_mode); + PHYDM_DBG(dm, DBG_DFS, + "pw_hold_sum = %d %d %d %d %d %d\n", + dfs->pw_hold_sum[0], dfs->pw_hold_sum[1], + dfs->pw_hold_sum[2], dfs->pw_hold_sum[3], + dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, + "pri_hold_sum = %d %d %d %d %d %d\n", + dfs->pri_hold_sum[0], dfs->pri_hold_sum[1], + dfs->pri_hold_sum[2], dfs->pri_hold_sum[3], + dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]); + } + } + } else { + dfs->radar_type = 1; + if (dfs->det_print2) { + PHYDM_DBG(dm, DBG_DFS, "\n"); + PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", + dfs->idle_mode); + PHYDM_DBG(dm, DBG_DFS, + "long_radar_pw_hold_sum = %d %d %d %d %d %d\n", + dfs->pw_long_hold_sum[0], + dfs->pw_long_hold_sum[1], + dfs->pw_long_hold_sum[2], + dfs->pw_long_hold_sum[3], + dfs->pw_long_hold_sum[4], + dfs->pw_long_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, + "long_radar_pri_hold_sum = %d %d %d %d %d %d\n", + dfs->pri_long_hold_sum[0], + dfs->pri_long_hold_sum[1], + dfs->pri_long_hold_sum[2], + dfs->pri_long_hold_sum[3], + dfs->pri_long_hold_sum[4], + dfs->pri_long_hold_sum[5]); + } + /* @Long radar should satisfy three conditions */ + if (dfs->long_radar_flag == 1) { + hist_radar_detected = 1; + PHYDM_DBG(dm, DBG_DFS, + "Detected type %d radar signal!\n", + dfs->radar_type); + } else { + if (dfs->det_print2) { + if (dfs->pw_long_cond1 == 0) + PHYDM_DBG(dm, DBG_DFS, + "--pw_long_cond1 is not satisfied!--\n"); + if (dfs->pw_long_cond2 == 0) + PHYDM_DBG(dm, DBG_DFS, + "--pw_long_cond2 is not satisfied!--\n"); + if (dfs->pri_long_cond1 == 0) + PHYDM_DBG(dm, DBG_DFS, + "--pri_long_cond1 is not satisfied!--\n"); + } + } + } + return hist_radar_detected; +} + +boolean phydm_radar_detect(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; boolean enable_DFS = false; boolean radar_detected = false; - p_dfs->igi_cur = (u8)odm_get_bb_reg(p_dm_odm, 0xc50, 0x0000007f); - p_dfs->st_l2h_cur = (u8)odm_get_bb_reg(p_dm_odm, 0x91c, 0x000000ff); + dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0xc50, 0x0000007f); + + dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff); - /* dynamic pwdb calibration */ - if (p_dfs->igi_pre != p_dfs->igi_cur) { - p_dfs->pwdb_th = ((int)p_dfs->st_l2h_cur - (int)p_dfs->igi_cur)/2 + p_dfs->pwdb_scalar_factor; - p_dfs->pwdb_th = MAX_2(p_dfs->pwdb_th_cur, (int)p_dfs->pwdb_th); /* limit the pwdb value to absoulte lower bound 0xa */ - p_dfs->pwdb_th = MIN_2(p_dfs->pwdb_th_cur, 0x1f); /* limit the pwdb value to absoulte upper bound 0x1f */ - odm_set_bb_reg(p_dm_odm, 0x918, 0x00001f00, p_dfs->pwdb_th); + /* @dynamic pwdb calibration */ + if (dfs->igi_pre != dfs->igi_cur) { + dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur) + / 2 + dfs->pwdb_scalar_factor; + + /* @limit the pwdb value to absolute lower bound 0xa */ + dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th); + /* @limit the pwdb value to absolute upper bound 0x1f */ + dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f); + odm_set_bb_reg(dm, R_0x918, 0x00001f00, dfs->pwdb_th_cur); } - p_dfs->igi_pre = p_dfs->igi_cur; + dfs->igi_pre = dfs->igi_cur; - phydm_dfs_dynamic_setting(p_dm_odm); - radar_detected = phydm_radar_detect_dm_check(p_dm_odm); + phydm_dfs_dynamic_setting(dm); + phydm_dfs_histogram_radar_distinguish(dm); + radar_detected = phydm_radar_detect_dm_check(dm); - if (odm_get_bb_reg(p_dm_odm, 0x924, BIT(15))) + if (odm_get_bb_reg(dm, R_0x924, BIT(15))) enable_DFS = true; if (enable_DFS && radar_detected) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Radar detect: enable_DFS:%d, radar_detected:%d\n", enable_DFS, radar_detected)); - phydm_radar_detect_reset(p_dm_odm); - if (p_dfs->dbg_mode == 1){ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Radar is detected in DFS dbg mode.\n")); + PHYDM_DBG(dm, DBG_DFS, + "Radar detect: enable_DFS:%d, radar_detected:%d\n", + enable_DFS, radar_detected); + phydm_radar_detect_reset(dm); + if (dfs->dbg_mode == 1) { + PHYDM_DBG(dm, DBG_DFS, + "Radar is detected in DFS dbg mode.\n"); radar_detected = 0; } - } + } return enable_DFS && radar_detected; } -void -phydm_dfs_debug( - void *p_dm_void, - u32 *const argv, - u32 *_used, - char *output, - u32 *_out_len -) +void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; u32 used = *_used; u32 out_len = *_out_len; + u32 argv[10] = {0}; + u8 i, input_idx = 0; - p_dfs->dbg_mode = (boolean)argv[0]; - p_dfs->force_TP_mode = (boolean)argv[1]; - p_dfs->det_print = (boolean)argv[2]; - p_dfs->det_print2 = (boolean)argv[3]; + for (i = 0; i < 6; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &argv[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + dfs->dbg_mode = (boolean)argv[0]; + dfs->force_TP_mode = (boolean)argv[1]; + dfs->det_print = (boolean)argv[2]; + dfs->det_print2 = (boolean)argv[3]; + dfs->print_hist_rpt = (boolean)argv[4]; + dfs->hist_cond_on = (boolean)argv[5]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "dbg_mode: %d, force_TP_mode: %d, det_print: %d,det_print2: %d, print_hist_rpt: %d, hist_cond_on: %d\n", + dfs->dbg_mode, dfs->force_TP_mode, dfs->det_print, + dfs->det_print2, dfs->print_hist_rpt, dfs->hist_cond_on); - PHYDM_SNPRINTF((output + used, out_len - used, "dbg_mode: %d, force_TP_mode: %d, det_print: %d, det_print2: %d\n", p_dfs->dbg_mode, p_dfs->force_TP_mode, p_dfs->det_print, p_dfs->det_print2)); - /*switch (argv[0]) { case 1: #if defined(CONFIG_PHYDM_DFS_MASTER) - set dbg parameters for radar detection instead of the default value + set dbg parameters for radar detection instead of the default value if (argv[1] == 1) { - p_dm_odm->radar_detect_reg_918 = argv[2]; - p_dm_odm->radar_detect_reg_91c = argv[3]; - p_dm_odm->radar_detect_reg_920 = argv[4]; - p_dm_odm->radar_detect_reg_924 = argv[5]; - p_dm_odm->radar_detect_dbg_parm_en = 1; - - PHYDM_SNPRINTF((output + used, out_len - used, "Radar detection with dbg parameter\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "reg918:0x%08X\n", p_dm_odm->radar_detect_reg_918)); - PHYDM_SNPRINTF((output + used, out_len - used, "reg91c:0x%08X\n", p_dm_odm->radar_detect_reg_91c)); - PHYDM_SNPRINTF((output + used, out_len - used, "reg920:0x%08X\n", p_dm_odm->radar_detect_reg_920)); - PHYDM_SNPRINTF((output + used, out_len - used, "reg924:0x%08X\n", p_dm_odm->radar_detect_reg_924)); + dm->radar_detect_reg_918 = argv[2]; + dm->radar_detect_reg_91c = argv[3]; + dm->radar_detect_reg_920 = argv[4]; + dm->radar_detect_reg_924 = argv[5]; + dm->radar_detect_dbg_parm_en = 1; + + PDM_SNPF((output + used, out_len - used, "Radar detection with dbg parameter\n")); + PDM_SNPF((output + used, out_len - used, "reg918:0x%08X\n", dm->radar_detect_reg_918)); + PDM_SNPF((output + used, out_len - used, "reg91c:0x%08X\n", dm->radar_detect_reg_91c)); + PDM_SNPF((output + used, out_len - used, "reg920:0x%08X\n", dm->radar_detect_reg_920)); + PDM_SNPF((output + used, out_len - used, "reg924:0x%08X\n", dm->radar_detect_reg_924)); } else { - p_dm_odm->radar_detect_dbg_parm_en = 0; - PHYDM_SNPRINTF((output + used, out_len - used, "Radar detection with default parameter\n")); + dm->radar_detect_dbg_parm_en = 0; + PDM_SNPF((output + used, out_len - used, "Radar detection with default parameter\n")); } - phydm_radar_detect_enable(p_dm_odm); -#endif defined(CONFIG_PHYDM_DFS_MASTER) + phydm_radar_detect_enable(dm); +#endif defined(CONFIG_PHYDM_DFS_MASTER) break; default: break; }*/ - } +} + +u8 phydm_dfs_polling_time(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 dfs_polling_time = 0; + + if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) + dfs_polling_time = 40; + else + dfs_polling_time = 100; + + return dfs_polling_time; +} + +#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */ + +boolean +phydm_is_dfs_band(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; -#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ + if (((*dm->channel >= 52) && (*dm->channel <= 64)) || + ((*dm->channel >= 100) && (*dm->channel <= 144))) + return true; + else + return false; +} boolean -phydm_dfs_master_enabled( - void *p_dm_void -) +phydm_dfs_master_enabled(void *dm_void) { #ifdef CONFIG_PHYDM_DFS_MASTER - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret_val = false; + + if (dm->dfs_master_enabled) /*pointer protection*/ + ret_val = *dm->dfs_master_enabled ? true : false; - return *p_dm_odm->dfs_master_enabled ? true : false; + return ret_val; #else return false; #endif diff --git a/hal/phydm/phydm_dfs.h b/hal/phydm/phydm_dfs.h index 85878c0..d05309e 100644 --- a/hal/phydm/phydm_dfs.h +++ b/hal/phydm/phydm_dfs.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,97 +8,174 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #ifndef __PHYDM_DFS_H__ #define __PHYDM_DFS_H__ -#define DFS_VERSION "1.1" +#define DFS_VERSION "1.1" -/* ============================================================ - Definition - ============================================================ -*/ +/*@ + * ============================================================ + * Definition + * ============================================================ + */ -/* -============================================================ -1 structure - ============================================================ -*/ +/*@ + * ============================================================ + * 1 structure + * ============================================================ + */ struct _DFS_STATISTICS { - u8 mask_idx; - u8 igi_cur; - u8 igi_pre; - u8 st_l2h_cur; - u16 fa_count_pre; - u16 fa_inc_hist[5]; - u16 vht_crc_ok_cnt_pre; - u16 ht_crc_ok_cnt_pre; - u16 leg_crc_ok_cnt_pre; - u16 short_pulse_cnt_pre; - u16 long_pulse_cnt_pre; - u8 pwdb_th; - u8 pwdb_th_cur; - u8 pwdb_scalar_factor; - u8 peak_th; - u8 short_pulse_cnt_th; - u8 long_pulse_cnt_th; - u8 peak_window; - u8 nb2wb_th; - u8 fa_mask_th; - u8 det_flag_offset; - u8 st_l2h_max; - u8 st_l2h_min; - u8 mask_hist_checked; + u8 mask_idx; + u8 igi_cur; + u8 igi_pre; + u8 st_l2h_cur; + u16 fa_count_pre; + u16 fa_inc_hist[5]; + u16 vht_crc_ok_cnt_pre; + u16 ht_crc_ok_cnt_pre; + u16 leg_crc_ok_cnt_pre; + u16 short_pulse_cnt_pre; + u16 long_pulse_cnt_pre; + u8 pwdb_th; + u8 pwdb_th_cur; + u8 pwdb_scalar_factor; + u8 peak_th; + u8 short_pulse_cnt_th; + u8 long_pulse_cnt_th; + u8 peak_window; + u8 three_peak_opt; + u8 three_peak_th2; + u8 fa_mask_th; + u8 det_flag_offset; + u8 st_l2h_max; + u8 st_l2h_min; + u8 mask_hist_checked; boolean pulse_flag_hist[5]; + boolean pulse_type_hist[5]; boolean radar_det_mask_hist[5]; boolean idle_mode; boolean force_TP_mode; boolean dbg_mode; boolean det_print; boolean det_print2; + boolean radar_type; + /*@dfs histogram*/ + boolean print_hist_rpt; + boolean hist_cond_on; + boolean pri_cond1; + boolean pri_cond2; + boolean pri_cond3; + boolean pri_cond4; + boolean pri_cond5; + boolean pw_cond1; + boolean pw_cond2; + boolean pw_cond3; + boolean pri_type3_4_cond1; /*@for ETSI*/ + boolean pri_type3_4_cond2; /*@for ETSI*/ + boolean pw_long_cond1; /*@for long radar*/ + boolean pw_long_cond2; /*@for long radar*/ + boolean pri_long_cond1; /*@for long radar*/ + boolean pw_flag; + boolean pri_flag; + boolean pri_type3_4_flag; /*@for ETSI*/ + boolean long_radar_flag; + u16 pri_hold_sum[6]; + u16 pw_hold_sum[6]; + u16 pri_long_hold_sum[6]; + u16 pw_long_hold_sum[6]; + u8 pri_hist_th; + u8 hist_idx; + u8 hist_long_idx; + u8 pw_hold[4][6]; + u8 pri_hold[4][6]; + u8 pw_long_hold[300][6]; + u8 pri_long_hold[300][6]; + u16 pw_std; /*@The std(var) of reasonable num of pw group*/ + u16 pri_std;/*@The std(var) of reasonable num of pri group*/ + /*@dfs histogram threshold*/ + u8 pri_sum_g1_th; + u8 pri_sum_g5_th; + u8 pri_sum_g1_fcc_th; + u8 pri_sum_g3_fcc_th; + u8 pri_sum_safe_fcc_th; + u8 pri_sum_type4_th; + u8 pri_sum_type6_th; + u8 pri_sum_safe_th; + u8 pri_sum_g5_under_g1_th; + u8 pri_pw_diff_th; + u8 pri_pw_diff_fcc_th; + u8 pri_pw_diff_fcc_idle_th; + u8 pri_pw_diff_w53_th; + u8 pri_type1_low_fcc_th; + u8 pri_type1_upp_fcc_th; + u8 pri_type1_cen_fcc_th; + u8 pw_g0_th; + u8 pw_long_lower_20m_th; + u8 pw_long_lower_th; + u8 pri_long_upper_th; + u8 pw_long_sum_upper_th; + u8 pw_std_th; + u8 pw_std_idle_th; + u8 pri_std_th; + u8 pri_std_idle_th; + u8 type4_pw_max_cnt; + u8 type4_safe_pri_sum_th; }; -/* ============================================================ - enumeration - ============================================================ -*/ +/*@ + * ============================================================ + * enumeration + * ============================================================ + */ enum phydm_dfs_region_domain { - PHYDM_DFS_DOMAIN_UNKNOWN = 0, - PHYDM_DFS_DOMAIN_FCC = 1, - PHYDM_DFS_DOMAIN_MKK = 2, - PHYDM_DFS_DOMAIN_ETSI = 3, + PHYDM_DFS_DOMAIN_UNKNOWN = 0, + PHYDM_DFS_DOMAIN_FCC = 1, + PHYDM_DFS_DOMAIN_MKK = 2, + PHYDM_DFS_DOMAIN_ETSI = 3, }; -/* -============================================================ - function prototype -============================================================ -*/ +/*@ + * ============================================================ + * function prototype + * ============================================================ + */ #if defined(CONFIG_PHYDM_DFS_MASTER) - void phydm_radar_detect_reset(void *p_dm_void); - void phydm_radar_detect_disable(void *p_dm_void); - void phydm_radar_detect_enable(void *p_dm_void); - boolean phydm_radar_detect(void *p_dm_void); - void phydm_dfs_parameter_init(void *p_dm_void); - void phydm_dfs_debug(void *p_dm_void, u32 *const argv, u32 *_used, char *output, u32 *_out_len); -#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */ +void phydm_radar_detect_reset(void *dm_void); +void phydm_radar_detect_disable(void *dm_void); +void phydm_radar_detect_enable(void *dm_void); +boolean phydm_radar_detect(void *dm_void); +void phydm_dfs_histogram_radar_distinguish(void *dm_void); +boolean phydm_dfs_hist_log(void *dm_void, u8 index); +void phydm_dfs_parameter_init(void *dm_void); +void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +u8 phydm_dfs_polling_time(void *dm_void); +#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */ + +boolean +phydm_dfs_is_meteorology_channel(void *dm_void); -boolean phydm_dfs_is_meteorology_channel(void *p_dm_void); +boolean +phydm_is_dfs_band(void *dm_void); boolean -phydm_dfs_master_enabled( - void *p_dm_void -); +phydm_dfs_master_enabled(void *dm_void); -#endif /*#ifndef __PHYDM_DFS_H__ */ +#endif /*@#ifndef __PHYDM_DFS_H__ */ diff --git a/hal/phydm/phydm_dig.c b/hal/phydm/phydm_dig.c index af019c0..814ce90 100644 --- a/hal/phydm/phydm_dig.c +++ b/hal/phydm/phydm_dig.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,2258 +8,2722 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -/* ************************************************************ +/*@************************************************************ * include files - * ************************************************************ */ + * ************************************************************ + */ #include "mp_precomp.h" #include "phydm_precomp.h" - -void -odm_change_dynamic_init_gain_thresh( - void *p_dm_void, - u32 dm_type, - u32 dm_value -) +#ifdef CFG_DIG_DAMPING_CHK +void phydm_dig_recorder_reset(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - - if (dm_type == DIG_TYPE_THRESH_HIGH) - p_dm_dig_table->rssi_high_thresh = dm_value; - else if (dm_type == DIG_TYPE_THRESH_LOW) - p_dm_dig_table->rssi_low_thresh = dm_value; - else if (dm_type == DIG_TYPE_ENABLE) - p_dm_dig_table->dig_enable_flag = true; - else if (dm_type == DIG_TYPE_DISABLE) - p_dm_dig_table->dig_enable_flag = false; - else if (dm_type == DIG_TYPE_BACKOFF) { - if (dm_value > 30) - dm_value = 30; - p_dm_dig_table->backoff_val = (u8)dm_value; - } else if (dm_type == DIG_TYPE_RX_GAIN_MIN) { - if (dm_value == 0) - dm_value = 0x1; - p_dm_dig_table->rx_gain_range_min = (u8)dm_value; - } else if (dm_type == DIG_TYPE_RX_GAIN_MAX) { - if (dm_value > 0x50) - dm_value = 0x50; - p_dm_dig_table->rx_gain_range_max = (u8)dm_value; - } -} /* dm_change_dynamic_init_gain_thresh */ - -int -get_igi_for_diff(int value_IGI) -{ -#define ONERCCA_LOW_TH 0x30 -#define ONERCCA_LOW_DIFF 8 + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; - if (value_IGI < ONERCCA_LOW_TH) { - if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) - return ONERCCA_LOW_TH; - else - return value_IGI + ONERCCA_LOW_DIFF; - } else - return value_IGI; + PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__); + + odm_memory_set(dm, &dig_rc->igi_bitmap, 0, + sizeof(struct phydm_dig_recorder_strcut)); } -void -odm_fa_threshold_check( - void *p_dm_void, - boolean is_dfs_band, - boolean is_performance, - u32 rx_tp, - u32 tx_tp, - u32 *dm_FA_thres -) +void phydm_dig_recorder(void *dm_void, boolean first_connect, u8 igi_curr, + u32 fa_cnt) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; + u8 igi_pre = dig_rc->igi_history[0]; + u8 igi_up = 0; - if (p_dm_odm->is_linked && (is_performance || is_dfs_band)) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - /*For AP*/ -#if (DIG_HW == 1) - dm_FA_thres[0] = p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_th1; - dm_FA_thres[1] = p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_th2; - dm_FA_thres[2] = p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_th3; -#else - if ((rx_tp >> 2) > tx_tp && rx_tp < 10000 && rx_tp > 500) { /*10Mbps & 0.5Mbps*/ - dm_FA_thres[0] = 0x080; - dm_FA_thres[1] = 0x100; - dm_FA_thres[2] = 0x200; - } else { - dm_FA_thres[0] = 0x100; - dm_FA_thres[1] = 0x200; - dm_FA_thres[2] = 0x300; - } -#endif -#else - /*For NIC*/ - dm_FA_thres[0] = DM_DIG_FA_TH0; - dm_FA_thres[1] = DM_DIG_FA_TH1; - dm_FA_thres[2] = DM_DIG_FA_TH2; -#endif - } else { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - if (is_dfs_band) { - /* For DFS band and no link */ - dm_FA_thres[0] = 250; - dm_FA_thres[1] = 1000; - dm_FA_thres[2] = 2000; - } else -#endif - { - dm_FA_thres[0] = 2000; - dm_FA_thres[1] = 4000; - dm_FA_thres[2] = 5000; - } + if (!dm->is_linked) + return; + + PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__); + + if (first_connect) { + phydm_dig_recorder_reset(dm); + dig_rc->igi_history[0] = igi_curr; + dig_rc->fa_history[0] = fa_cnt; + return; } - return; + + igi_pre = dig_rc->igi_history[0]; + igi_up = (igi_curr > igi_pre) ? 1 : 0; + dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up; + + dig_rc->igi_history[3] = dig_rc->igi_history[2]; + dig_rc->igi_history[2] = dig_rc->igi_history[1]; + dig_rc->igi_history[1] = dig_rc->igi_history[0]; + dig_rc->igi_history[0] = igi_curr; + + dig_rc->fa_history[3] = dig_rc->fa_history[2]; + dig_rc->fa_history[2] = dig_rc->fa_history[1]; + dig_rc->fa_history[1] = dig_rc->fa_history[0]; + dig_rc->fa_history[0] = fa_cnt; + + PHYDM_DBG(dm, DBG_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n", + dig_rc->igi_history[3], dig_rc->igi_history[2], + dig_rc->igi_history[1], dig_rc->igi_history[0]); + PHYDM_DBG(dm, DBG_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n", + dig_rc->fa_history[3], dig_rc->fa_history[2], + dig_rc->fa_history[1], dig_rc->fa_history[0]); + PHYDM_DBG(dm, DBG_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n", + (u8)((dig_rc->igi_bitmap & BIT(3)) >> 3), + (u8)((dig_rc->igi_bitmap & BIT(2)) >> 2), + (u8)((dig_rc->igi_bitmap & BIT(1)) >> 1), + (u8)(dig_rc->igi_bitmap & BIT(0)), + dig_rc->igi_bitmap); } -u8 -odm_forbidden_igi_check( - void *p_dm_void, - u8 dig_dynamic_min, - u8 current_igi -) +void phydm_dig_damping_chk(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - u8 rx_gain_range_min = p_dm_dig_table->rx_gain_range_min; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; + u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf; + u8 diff1 = 0, diff2 = 0; + u32 fa_low_th = dig_t->fa_th[0]; + u32 fa_high_th = dig_t->fa_th[1]; + u8 fa_pattern_match = 0; + u32 time_tmp; + + if (!dm->is_linked) + return; - if (p_dm_dig_table->large_fa_timeout) { - if (--p_dm_dig_table->large_fa_timeout == 0) - p_dm_dig_table->large_fa_hit = 0; + PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__); + + /*@== Release Damping ================================================*/ + if (dig_rc->damping_limit_en) { + PHYDM_DBG(dm, DBG_DIG, + "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n", + dig_rc->limit_time, dm->phydm_sys_up_time); + + time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD; + + if (DIFF_2(dm->rssi_min, dig_rc->limit_rssi) > 3 || + time_tmp < dm->phydm_sys_up_time) { + dig_rc->damping_limit_en = 0; + PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, limit_rssi=%d\n", + dm->rssi_min, dig_rc->limit_rssi); + } + return; } - if (p_false_alm_cnt->cnt_all > 10000) { + /*@== Damping Pattern Check===========================================*/ + PHYDM_DBG(dm, DBG_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case.\n")); + switch (igi_bitmap_4bit) { + case 0x5: /*@4b'0101 ex:down(0x24)->up(0x28)->down(0x24)->up(0x28)*/ + if (dig_rc->igi_history[0] > dig_rc->igi_history[1]) + diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1]; - if (p_dm_dig_table->large_fa_hit != 3) - p_dm_dig_table->large_fa_hit++; + if (dig_rc->igi_history[2] > dig_rc->igi_history[3]) + diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3]; - if (p_dm_dig_table->forbidden_igi < current_igi) { /* if(p_dm_dig_table->forbidden_igi < p_dm_dig_table->cur_ig_value) */ - p_dm_dig_table->forbidden_igi = current_igi;/* p_dm_dig_table->forbidden_igi = p_dm_dig_table->cur_ig_value; */ - p_dm_dig_table->large_fa_hit = 1; - p_dm_dig_table->large_fa_timeout = LARGE_FA_TIMEOUT; + if (dig_rc->fa_history[0] < fa_low_th && + dig_rc->fa_history[1] > fa_high_th && + dig_rc->fa_history[2] < fa_low_th && + dig_rc->fa_history[3] > fa_high_th) { + /*@Check each fa element*/ + fa_pattern_match = 1; } - - if (p_dm_dig_table->large_fa_hit >= 3) { - if ((p_dm_dig_table->forbidden_igi + 2) > p_dm_dig_table->rx_gain_range_max) - rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; - else - rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 2); - p_dm_dig_table->recover_cnt = 1800; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case: recover_cnt = %d\n", p_dm_dig_table->recover_cnt)); + break; + case 0x9: /*@4b'1001 ex:up(0x28)->down(0x26)->down(0x24)->up(0x28)*/ + if (dig_rc->igi_history[0] > dig_rc->igi_history[1]) + diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1]; + + if (dig_rc->igi_history[2] < dig_rc->igi_history[3]) + diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2]; + + if (dig_rc->fa_history[0] < fa_low_th && + dig_rc->fa_history[1] > fa_high_th && + dig_rc->fa_history[2] > fa_low_th && + dig_rc->fa_history[3] < fa_high_th) { + /*@Check each fa element*/ + fa_pattern_match = 1; } + break; + default: + break; } - else if (p_false_alm_cnt->cnt_all > 2000) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case.\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cnt_all=%d, cnt_all_pre=%d, current_igi=0x%x, pre_ig_value=0x%x\n", - p_false_alm_cnt->cnt_all, p_false_alm_cnt->cnt_all_pre, current_igi, p_dm_dig_table->pre_ig_value)); + if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) { + dig_rc->damping_limit_en = 1; + dig_rc->damping_limit_val = dig_rc->igi_history[0]; + dig_rc->limit_time = dm->phydm_sys_up_time; + dig_rc->limit_rssi = dm->rssi_min; - /* p_false_alm_cnt->cnt_all = 1.1875*p_false_alm_cnt->cnt_all_pre */ - if ((p_false_alm_cnt->cnt_all > (p_false_alm_cnt->cnt_all_pre + (p_false_alm_cnt->cnt_all_pre >> 3) + (p_false_alm_cnt->cnt_all_pre >> 4))) && (current_igi < p_dm_dig_table->pre_ig_value)) { - if (p_dm_dig_table->large_fa_hit != 3) - p_dm_dig_table->large_fa_hit++; - - if (p_dm_dig_table->forbidden_igi < current_igi) { /*if(p_dm_dig_table->forbidden_igi < p_dm_dig_table->cur_ig_value)*/ + PHYDM_DBG(dm, DBG_DIG, + "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n", + dig_rc->damping_limit_val, + dig_rc->limit_time, dig_rc->limit_rssi); + } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Updating forbidden_igi by current_igi, forbidden_igi=0x%x, current_igi=0x%x\n", - p_dm_dig_table->forbidden_igi, current_igi)); + PHYDM_DBG(dm, DBG_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en); +} +#endif - p_dm_dig_table->forbidden_igi = current_igi; /*p_dm_dig_table->forbidden_igi = p_dm_dig_table->cur_ig_value;*/ - p_dm_dig_table->large_fa_hit = 1; - p_dm_dig_table->large_fa_timeout = LARGE_FA_TIMEOUT; +boolean +phydm_dig_go_up_check(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 cur_ig_value = dig_t->cur_ig_value; + u8 max_cover_bond = 0; + u8 rx_gain_range_max = dig_t->rx_gain_range_max; + u8 i = 0, j = 0; + u8 total_nhm_cnt = ccx_info->nhm_rpt_sum; + u32 dig_cnt = 0; + u32 over_dig_cnt = 0; + boolean ret = true; + + if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) + return ret; + + max_cover_bond = DIG_MAX_BALANCE_MODE - dig_t->upcheck_init_val; + + if (cur_ig_value < max_cover_bond - 6) + dig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_0; + else if (cur_ig_value <= DIG_MAX_BALANCE_MODE) + dig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_1; + else /* @cur_ig_value > DM_DIG_MAX_AP, foolproof */ + dig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_2; + + PHYDM_DBG(dm, DBG_DIG, "check_lv = %d, max_cover_bond = 0x%x\n", + dig_t->go_up_chk_lv, max_cover_bond); + + if (total_nhm_cnt == 0) + return true; + + if (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_0) { + for (i = 3; i <= 11; i++) + dig_cnt += ccx_info->nhm_result[i]; + + if ((dig_t->lv0_ratio_reciprocal * dig_cnt) >= total_nhm_cnt) + ret = true; + else + ret = false; + + } else if (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_1) { + /* search index */ + for (i = 0; i <= 10; i++) { + if ((max_cover_bond * 2) == ccx_info->nhm_th[i]) { + for (j = (i + 1); j <= 11; j++) + over_dig_cnt += ccx_info->nhm_result[j]; + break; } - } - if (p_dm_dig_table->large_fa_hit >= 3) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("FaHit is greater than 3, rx_gain_range_max=0x%x, rx_gain_range_min=0x%x, forbidden_igi=0x%x\n", - p_dm_dig_table->rx_gain_range_max, rx_gain_range_min, p_dm_dig_table->forbidden_igi)); + if (dig_t->lv1_ratio_reciprocal * over_dig_cnt < total_nhm_cnt) + ret = true; + else + ret = false; - if ((p_dm_dig_table->forbidden_igi + 1) > p_dm_dig_table->rx_gain_range_max) - rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; + if (!ret) { + /* update dig_t->rx_gain_range_max */ + if (rx_gain_range_max + 6 >= max_cover_bond) + dig_t->rx_gain_range_max = max_cover_bond - 6; else - rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 1); + dig_t->rx_gain_range_max = rx_gain_range_max; - p_dm_dig_table->recover_cnt = 1200; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case: recover_cnt = %d, rx_gain_range_min = 0x%x\n", p_dm_dig_table->recover_cnt, rx_gain_range_min)); + PHYDM_DBG(dm, DBG_DIG, + "Noise pwr over DIG can filter, lock rx_gain_range_max to 0x%x\n", + dig_t->rx_gain_range_max); } + } else if (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_2) { + /* @cur_ig_value > DM_DIG_MAX_AP, foolproof */ + ret = true; } - else { - if (p_dm_dig_table->recover_cnt != 0) { + return ret; +} - p_dm_dig_table->recover_cnt--; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: recover_cnt = %d\n", p_dm_dig_table->recover_cnt)); +void phydm_fa_threshold_check(void *dm_void, boolean is_dfs_band) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + if (dig_t->is_dbg_fa_th) { + PHYDM_DBG(dm, DBG_DIG, "Manual Fix FA_th\n"); + } else if (dm->is_linked) { + if (dm->rssi_min < 20) { /*@[PHYDM-252]*/ + dig_t->fa_th[0] = 500; + dig_t->fa_th[1] = 750; + dig_t->fa_th[2] = 1000; + } else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/ + (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*TP=1~10Mb*/ + dig_t->fa_th[0] = 125; + dig_t->fa_th[1] = 250; + dig_t->fa_th[2] = 500; } else { - if (p_dm_dig_table->large_fa_hit < 3) { - if ((p_dm_dig_table->forbidden_igi - 2) < dig_dynamic_min) { /* DM_DIG_MIN) */ - p_dm_dig_table->forbidden_igi = dig_dynamic_min; /* DM_DIG_MIN; */ - rx_gain_range_min = dig_dynamic_min; /* DM_DIG_MIN; */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); - } else { - if (p_dm_dig_table->large_fa_hit == 0) { - p_dm_dig_table->forbidden_igi -= 2; - rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 2); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); - } - } - } else - p_dm_dig_table->large_fa_hit = 0; + dig_t->fa_th[0] = 250; + dig_t->fa_th[1] = 500; + dig_t->fa_th[2] = 750; } - } + } else { + if (is_dfs_band) { /* @For DFS band and no link */ - return rx_gain_range_min; + dig_t->fa_th[0] = 250; + dig_t->fa_th[1] = 1000; + dig_t->fa_th[2] = 2000; + } else { + dig_t->fa_th[0] = 2000; + dig_t->fa_th[1] = 4000; + dig_t->fa_th[2] = 5000; + } + } + PHYDM_DBG(dm, DBG_DIG, "FA_th={%d,%d,%d}\n", dig_t->fa_th[0], + dig_t->fa_th[1], dig_t->fa_th[2]); } -void -odm_inband_noise_calculate( - void *p_dm_void -) +void phydm_set_big_jump_step(void *dm_void, u8 curr_igi) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 igi_backup, time_cnt = 0, valid_cnt = 0; - boolean is_timeout = true; - s8 s_noise_a, s_noise_b; - s32 noise_rpt_a = 0, noise_rpt_b = 0; - u32 tmp = 0; - static u8 fail_cnt = 0; - - if (!(p_dm_odm->support_ic_type & (ODM_RTL8192E))) +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90}; + u8 big_jump_lmt = dig_t->big_jump_lmt[dig_t->agc_table_idx]; + u8 i; + + if (dig_t->enable_adjust_big_jump == 0) return; - if (p_dm_odm->rf_type == ODM_1T1R || *(p_dm_odm->p_one_path_cca) != ODM_CCA_2R) - return; + for (i = 0; i <= dig_t->big_jump_step1; i++) { + if ((curr_igi + step1[i]) > big_jump_lmt) { + if (i != 0) + i = i - 1; + break; + } else if (i == dig_t->big_jump_step1) { + break; + } + } + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, R_0x8c8, 0xe, i); + else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i); + + PHYDM_DBG(dm, DBG_DIG, "Bigjump = %d (ori = 0x%x), LMT=0x%x\n", i, + dig_t->big_jump_step1, big_jump_lmt); +#endif +} + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_write_dig_reg_jgr3(void *dm_void, u8 igi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; - if (!p_dm_dig_table->is_noise_est) + PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__); + + /* Set IGI value */ + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) return; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_InbandNoiseEstimate()========>\n")); + odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC, igi); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) + odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3, igi); + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3, igi); + odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3, igi); + } + #endif +} - /* 1 Set initial gain. */ - igi_backup = p_dm_dig_table->cur_ig_value; - p_dm_dig_table->igi_offset_a = 0; - p_dm_dig_table->igi_offset_b = 0; - odm_write_dig(p_dm_odm, 0x24); +u8 phydm_get_igi_reg_val_jgr3(void *dm_void, enum bb_path path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = 0; + + PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__); + + /* Set IGI value */ + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) + return (u8)val; + + if (path == BB_PATH_A) + val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC); + else if (path == BB_PATH_B) + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3); + #else + ; + #endif + else if (path == BB_PATH_C) + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3); + #else + ; + #endif + else if (path == BB_PATH_D) + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3); + #else + ; + #endif - /* 1 Update idle time power report */ - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_set_bb_reg(p_dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(25), 0x0); + return (u8)val; +} - delay_ms(2); +void phydm_fa_cnt_statistics_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + u32 ret_value = 0; + u32 cck_enable = 0; + u16 ofdm_tx_counter = 0; + u16 cck_tx_counter = 0; + + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) + return; - /* 1 Get noise power level */ - while (1) { - /* 2 Read Noise Floor Report */ - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - tmp = odm_get_bb_reg(p_dm_odm, 0x8f8, MASKLWORD); + ofdm_tx_counter = (u16)odm_get_bb_reg(dm, R_0x2de0, MASKLWORD); + cck_tx_counter = (u16)odm_get_bb_reg(dm, R_0x2de4, MASKLWORD); - s_noise_a = (s8)(tmp & 0xff); - s_noise_b = (s8)((tmp & 0xff00) >> 8); + ret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD); + fa_t->cnt_fast_fsync = (ret_value & 0xffff); + fa_t->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("s_noise_a = %d, s_noise_b = %d\n",s_noise_a, s_noise_b)); */ + ret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD); + fa_t->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); - if ((s_noise_a < 20 && s_noise_a >= -70) && (s_noise_b < 20 && s_noise_b >= -70)) { - valid_cnt++; - noise_rpt_a += s_noise_a; - noise_rpt_b += s_noise_b; - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("s_noise_a = %d, s_noise_b = %d\n",s_noise_a, s_noise_b)); */ - } + ret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD); + fa_t->cnt_rate_illegal = (ret_value & 0xffff); + fa_t->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); - time_cnt++; - is_timeout = (time_cnt >= 150) ? true : false; + ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD); + fa_t->cnt_mcs_fail = (ret_value & 0xffff); - if (valid_cnt == 20 || is_timeout) - break; + /* read OFDM FA counter */ + fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0x2d00, MASKLWORD); - delay_ms(2); + /* Read CCK FA counter */ + fa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD); - } + /* read CCK/OFDM CCA counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c08, MASKDWORD); + fa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16); + fa_t->cnt_cck_cca = ret_value & 0xffff; - /* 1 Keep idle time power report */ - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_set_bb_reg(p_dm_odm, ODM_REG_TX_ANT_CTRL_11N, BIT(25), 0x1); + /* read CCK CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD); + fa_t->cnt_cck_crc32_error = ((ret_value & 0xffff0000) >> 16); + fa_t->cnt_cck_crc32_ok = ret_value & 0xffff; - /* 1 Recover IGI */ - odm_write_dig(p_dm_odm, igi_backup); + /* read OFDM CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD); + fa_t->cnt_ofdm_crc32_error = ((ret_value & 0xffff0000) >> 16); + fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff; - /* 1 Calculate Noise Floor */ - if (valid_cnt != 0) { - noise_rpt_a /= (valid_cnt << 1); - noise_rpt_b /= (valid_cnt << 1); - } + /* read HT CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD); + fa_t->cnt_ht_crc32_error = ((ret_value & 0xffff0000) >> 16); + fa_t->cnt_ht_crc32_ok = ret_value & 0xffff; - if (is_timeout) { - noise_rpt_a = 0; - noise_rpt_b = 0; + /* @for VHT part */ + if (dm->support_ic_type & ODM_RTL8822C) { + /* read VHT CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD); + fa_t->cnt_vht_crc32_error = ((ret_value & 0xffff0000) >> 16); + fa_t->cnt_vht_crc32_ok = ret_value & 0xffff; - fail_cnt++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Noise estimate fail time = %d\n", fail_cnt)); + ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD); + fa_t->cnt_mcs_fail_vht = ((ret_value & 0xffff0000) >> 16); - if (fail_cnt == 3) { - fail_cnt = 0; - p_dm_dig_table->is_noise_est = false; - } + ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD); + fa_t->cnt_crc8_fail_vht = ret_value & 0xffff + + ((ret_value & 0xffff0000) >> 16); } else { - noise_rpt_a = -110 + 0x24 + noise_rpt_a - 6; - noise_rpt_b = -110 + 0x24 + noise_rpt_b - 6; - p_dm_dig_table->is_noise_est = false; - fail_cnt = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("noise_rpt_a = %d, noise_rpt_b = %d\n", noise_rpt_a, noise_rpt_b)); - } - - /* 1 Calculate IGI Offset */ - if (noise_rpt_a > noise_rpt_b) { - p_dm_dig_table->igi_offset_a = noise_rpt_a - noise_rpt_b; - p_dm_dig_table->igi_offset_b = 0; + fa_t->cnt_vht_crc32_error = 0; + fa_t->cnt_vht_crc32_ok = 0; + fa_t->cnt_mcs_fail_vht = 0; + fa_t->cnt_crc8_fail_vht = 0; + } + + cck_enable = odm_get_bb_reg(dm, R_0x1c3c, BIT(1)); /* @98f 1C3c[1] */ + if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */ + fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail + - ofdm_tx_counter; + fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca; + PHYDM_DBG(dm, DBG_FA_CNT, "ac3 OFDM FA = %d, CCK FA = %d\n", + fa_t->cnt_ofdm_fail - ofdm_tx_counter, + fa_t->cnt_cck_fail); } else { - p_dm_dig_table->igi_offset_a = 0; - p_dm_dig_table->igi_offset_b = noise_rpt_b - noise_rpt_a; + fa_t->cnt_all = fa_t->cnt_ofdm_fail - ofdm_tx_counter; + fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca; + PHYDM_DBG(dm, DBG_FA_CNT, "ac3 CCK disable OFDM FA = %d\n", + fa_t->cnt_ofdm_fail - ofdm_tx_counter); } -#endif - return; + PHYDM_DBG(dm, DBG_FA_CNT, + "ac3 [OFDM FA Detail] Parity_fail=((%d)), Rate_Illegal=((%d)), CRC8_fail=((%d)), Mcs_fail=((%d)), Fast_Fsync=((%d)), SBD_fail=((%d))\n", + fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal, + fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail, fa_t->cnt_fast_fsync, + fa_t->cnt_sb_search_fail); } -void -odm_dig_for_bt_hs_mode( - void *p_dm_void -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 dig_for_bt_hs = 0; - u8 dig_up_bound = 0x5a; - - if (p_dm_odm->is_bt_connect_process) - dig_for_bt_hs = 0x22; - else { - /* */ - /* Decide DIG value by BT HS RSSI. */ - /* */ - dig_for_bt_hs = p_dm_odm->bt_hs_rssi + 4; - - /* DIG Bound */ - if (dig_for_bt_hs > dig_up_bound) - dig_for_bt_hs = dig_up_bound; - if (dig_for_bt_hs < 0x1c) - dig_for_bt_hs = 0x1c; - - /* update Current IGI */ - p_dm_dig_table->bt30_cur_igi = dig_for_bt_hs; - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_for_bt_hs_mode() : set DigValue=0x%x\n", dig_for_bt_hs)); #endif -} -void -phydm_set_big_jump_step( - void *p_dm_void, - u8 current_igi -) +void phydm_write_dig_reg(void *dm_void, u8 igi) { -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90}; - u8 i; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_dig_table->enable_adjust_big_jump == 0) - return; + PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__); - for (i = 0; i <= p_dm_dig_table->big_jump_step1; i++) { - if ((current_igi + step1[i]) > p_dm_dig_table->big_jump_lmt[p_dm_dig_table->agc_table_idx]) { - if (i != 0) - i = i - 1; - break; - } else if (i == p_dm_dig_table->big_jump_step1) - break; - } - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - odm_set_bb_reg(p_dm_odm, 0x8c8, 0xe, i); - else if (p_dm_odm->support_ic_type & ODM_RTL8197F) - odm_set_bb_reg(p_dm_odm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i); + odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), igi); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_set_big_jump_step(): bigjump = %d (ori = 0x%x), LMT=0x%x\n", i, p_dm_dig_table->big_jump_step1, p_dm_dig_table->big_jump_lmt[p_dm_dig_table->agc_table_idx])); -#endif + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) + odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), igi); + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + odm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), igi); + odm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), igi); + } + #endif } -void -odm_write_dig( - void *p_dm_void, - u8 current_igi -) +void odm_write_dig(void *dm_void, u8 new_igi) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - - if (p_dm_dig_table->is_stop_dig) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_write_dig(): Stop Writing IGI\n")); - return; - } + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): ODM_REG(IGI_A,p_dm_odm)=0x%x, ODM_BIT(IGI,p_dm_odm)=0x%x\n", - ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm))); + PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__); - /* 1 Check initial gain by upper bound */ - if ((!p_dm_dig_table->is_psd_in_progress) && p_dm_odm->is_linked) { - if (current_igi > p_dm_dig_table->rx_gain_range_max) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): current_igi(0x%02x) is larger than upper bound !!\n", current_igi)); - current_igi = p_dm_dig_table->rx_gain_range_max; - } - if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY && p_dm_odm->adaptivity_flag == true) { - if (current_igi > p_dm_odm->adaptivity_igi_upper) - current_igi = p_dm_odm->adaptivity_igi_upper; + /* @1 Check IGI by upper bound */ + if (adaptivity->igi_lmt_en && + new_igi > adaptivity->adapt_igi_up && dm->is_linked) { + new_igi = adaptivity->adapt_igi_up; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_write_dig(): adaptivity case: Force upper bound to 0x%x !!!!!!\n", current_igi)); - } + PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n", + new_igi); } - if (p_dm_dig_table->cur_ig_value != current_igi) { + #if (RTL8192F_SUPPORT) + if ((dm->support_ic_type & ODM_RTL8192F) && + dm->cut_version == ODM_CUT_A && + new_igi > 0x38) { + new_igi = 0x38; + PHYDM_DBG(dm, DBG_DIG, + "Force 92F Adaptivity Up-bound=((0x%x))\n", new_igi); + } + #endif -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - /* Modify big jump step for 8822B and 8197F */ - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) - phydm_set_big_jump_step(p_dm_odm, current_igi); -#endif + if (dig_t->cur_ig_value != new_igi) { + #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + /* @Modify big jump step for 8822B and 8197F */ + if (dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) + phydm_set_big_jump_step(dm, new_igi); + #endif -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) /* Set IGI value of CCK for new CCK AGC */ - if (p_dm_odm->cck_new_agc) { - if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) - odm_set_bb_reg(p_dm_odm, 0xa0c, 0x00003f00, (current_igi >> 1)); - } -#endif - - /*Add by YuChen for USB IO too slow issue*/ - if ((p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) && (current_igi > p_dm_dig_table->cur_ig_value)) { - p_dm_dig_table->cur_ig_value = current_igi; - phydm_adaptivity(p_dm_odm); - } - - /* 1 Set IGI value */ - if (p_dm_odm->support_platform & (ODM_WIN | ODM_CE)) { - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - - if (p_dm_odm->rf_type > ODM_1T1R) - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + if (dm->cck_new_agc && + (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)) + odm_set_bb_reg(dm, R_0xa0c, 0x3f00, (new_igi >> 1)); + #endif -#if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) { - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_C, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_D, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + /*@Add by YuChen for USB IO too slow issue*/ + if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) { + if (dm->support_ability & ODM_BB_ADAPTIVITY && + new_igi < dig_t->cur_ig_value) { + dig_t->cur_ig_value = new_igi; + phydm_adaptivity(dm); } -#endif - } else if (p_dm_odm->support_platform & (ODM_AP)) { - switch (*(p_dm_odm->p_one_path_cca)) { - case ODM_CCA_2R: - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - - if (p_dm_odm->rf_type > ODM_1T1R) - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); -#if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) { - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_C, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_D, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - } -#endif - break; - case ODM_CCA_1R_A: - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - if (p_dm_odm->rf_type != ODM_1T1R) - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), get_igi_for_diff(current_igi)); - break; - case ODM_CCA_1R_B: - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), get_igi_for_diff(current_igi)); - if (p_dm_odm->rf_type != ODM_1T1R) - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); - break; + } else { + if (dm->support_ability & ODM_BB_ADAPTIVITY && + new_igi > dig_t->cur_ig_value) { + dig_t->cur_ig_value = new_igi; + phydm_adaptivity(dm); } } - p_dm_dig_table->cur_ig_value = current_igi; - } + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_write_dig_reg_jgr3(dm, new_igi); + else + #endif + phydm_write_dig_reg(dm, new_igi); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): current_igi(0x%02x).\n", current_igi)); + dig_t->cur_ig_value = new_igi; + } + PHYDM_DBG(dm, DBG_DIG, "New_igi=((0x%x))\n\n", new_igi); } -void -odm_pause_dig( - void *p_dm_void, - enum phydm_pause_type pause_type, - enum phydm_pause_level pause_level, - u8 igi_value -) +u8 phydm_get_igi_reg_val(void *dm_void, enum bb_path path) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = 0; + u32 bit_map = ODM_BIT(IGI, dm); + + switch (path) { + case BB_PATH_A: + val = odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), bit_map); + break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case BB_PATH_B: + val = odm_get_bb_reg(dm, ODM_REG(IGI_B, dm), bit_map); + break; + #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig()=========> level = %d\n", pause_level)); + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case BB_PATH_C: + val = odm_get_bb_reg(dm, ODM_REG(IGI_C, dm), bit_map); + break; + #endif - if ((p_dm_dig_table->pause_dig_level == 0) && (!(p_dm_odm->support_ability & ODM_BB_DIG) || !(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_pause_dig(): Return: support_ability DIG or FA is disabled !!\n")); - return; - } + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case BB_PATH_D: + val = odm_get_bb_reg(dm, ODM_REG(IGI_D, dm), bit_map); + break; + #endif - if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_pause_dig(): Return: Wrong pause level !!\n")); - return; + default: + break; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_dig_level, igi_value)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - p_dm_dig_table->pause_dig_value[7], p_dm_dig_table->pause_dig_value[6], p_dm_dig_table->pause_dig_value[5], p_dm_dig_table->pause_dig_value[4], - p_dm_dig_table->pause_dig_value[3], p_dm_dig_table->pause_dig_value[2], p_dm_dig_table->pause_dig_value[1], p_dm_dig_table->pause_dig_value[0])); + return (u8)val; +} - switch (pause_type) { - /* Pause DIG */ - case PHYDM_PAUSE: - { - /* Disable DIG */ - odm_cmn_info_update(p_dm_odm, ODM_CMNINFO_ABILITY, p_dm_odm->support_ability & (~ODM_BB_DIG)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Pause DIG !!\n")); - - /* Backup IGI value */ - if (p_dm_dig_table->pause_dig_level == 0) { - p_dm_dig_table->igi_backup = p_dm_dig_table->cur_ig_value; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Backup IGI = 0x%x, new IGI = 0x%x\n", p_dm_dig_table->igi_backup, igi_value)); - } +u8 phydm_get_igi(void *dm_void, enum bb_path path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 val; + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + val = phydm_get_igi_reg_val_jgr3(dm, path); + else + #endif + val = phydm_get_igi_reg_val(dm, path); - /* Record IGI value */ - p_dm_dig_table->pause_dig_value[pause_level] = igi_value; + return val; +} - /* Update pause level */ - p_dm_dig_table->pause_dig_level = (p_dm_dig_table->pause_dig_level | BIT(pause_level)); +void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; - /* Write new IGI value */ - if (BIT(pause_level + 1) > p_dm_dig_table->pause_dig_level) { - odm_write_dig(p_dm_odm, igi_value); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): IGI of higher level = 0x%x\n", igi_value)); - } - break; + if (val_len != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][DIG]Need val_len=1\n"); + return; } - /* Resume DIG */ - case PHYDM_RESUME: - { - /* check if the level is illegal or not */ - if ((p_dm_dig_table->pause_dig_level & (BIT(pause_level))) != 0) { - p_dm_dig_table->pause_dig_level = p_dm_dig_table->pause_dig_level & (~(BIT(pause_level))); - p_dm_dig_table->pause_dig_value[pause_level] = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Resume DIG !!\n")); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Wrong resume level !!\n")); - break; - } - /* Resume DIG */ - if (p_dm_dig_table->pause_dig_level == 0) { - /* Write backup IGI value */ - odm_write_dig(p_dm_odm, p_dm_dig_table->igi_backup); - p_dm_dig_table->is_ignore_dig = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Write original IGI = 0x%x\n", p_dm_dig_table->igi_backup)); + odm_write_dig(dm, (u8)(*val_buf)); +} - /* Enable DIG */ - odm_cmn_info_update(p_dm_odm, ODM_CMNINFO_ABILITY, p_dm_odm->support_ability | ODM_BB_DIG); - break; - } +void odm_pause_dig(void *dm_void, enum phydm_pause_type type, + enum phydm_pause_level lv, u8 igi_input) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rpt = false; + u32 igi = (u32)igi_input; - if (BIT(pause_level) > p_dm_dig_table->pause_dig_level) { - s8 max_level; + PHYDM_DBG(dm, DBG_DIG, "[%s]type=%d, LV=%d, igi=0x%x\n", __func__, type, + lv, igi); - /* Calculate the maximum level now */ - for (max_level = (pause_level - 1); max_level >= 0; max_level--) { - if ((p_dm_dig_table->pause_dig_level & BIT(max_level)) > 0) - break; - } + switch (type) { + case PHYDM_PAUSE: + case PHYDM_PAUSE_NO_SET: { + rpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi); + break; + } - /* write IGI of lower level */ - odm_write_dig(p_dm_odm, p_dm_dig_table->pause_dig_value[max_level]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Write IGI (0x%x) of level (%d)\n", - p_dm_dig_table->pause_dig_value[max_level], max_level)); - break; - } + case PHYDM_RESUME: { + rpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi); break; } default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Wrong type !!\n")); + PHYDM_DBG(dm, DBG_DIG, "Wrong type\n"); break; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_dig_level, igi_value)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - p_dm_dig_table->pause_dig_value[7], p_dm_dig_table->pause_dig_value[6], p_dm_dig_table->pause_dig_value[5], p_dm_dig_table->pause_dig_value[4], - p_dm_dig_table->pause_dig_value[3], p_dm_dig_table->pause_dig_value[2], p_dm_dig_table->pause_dig_value[1], p_dm_dig_table->pause_dig_value[0])); - + PHYDM_DBG(dm, DBG_DIG, "pause_result=%d\n", rpt); } boolean -odm_dig_abort( - void *p_dm_void -) +phydm_dig_abort(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; -#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *p_adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; #endif /* support_ability */ - if (!(p_dm_odm->support_ability & ODM_BB_FA_CNT)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: support_ability ODM_BB_FA_CNT is disabled\n")); - return true; - } - - /* support_ability */ - if (!(p_dm_odm->support_ability & ODM_BB_DIG)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: support_ability ODM_BB_DIG is disabled\n")); - return true; - } - - /* ScanInProcess */ - if (*(p_dm_odm->p_is_scan_in_process)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: In Scan Progress\n")); - return true; - } - - if (p_dm_dig_table->is_ignore_dig) { - p_dm_dig_table->is_ignore_dig = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Ignore DIG\n")); - return true; + if ((!(dm->support_ability & ODM_BB_FA_CNT)) || + (!(dm->support_ability & ODM_BB_DIG)) || + *dm->is_scan_in_process) { + PHYDM_DBG(dm, DBG_DIG, "Not Support\n"); + return true; } - /* add by Neil Chen to avoid PSD is processing */ - if (p_dm_odm->is_dm_initial_gain_enable == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: PSD is Processing\n")); - return true; + if (dm->pause_ability & ODM_BB_DIG) { + PHYDM_DBG(dm, DBG_DIG, "Return: Pause DIG in LV=%d\n", + dm->pause_lv_table.lv_dig); + return true; } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #if OS_WIN_FROM_WIN7(OS_VERSION) - if (IsAPModeExist(p_adapter) && p_adapter->bInHctTest) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Is AP mode or In HCT Test\n")); - return true; + if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) { + PHYDM_DBG(dm, DBG_DIG, " Return: Is AP mode or In HCT Test\n"); + return true; } #endif - - if (p_dm_odm->is_bt_hs_operation) - odm_dig_for_bt_hs_mode(p_dm_odm); - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - if ((p_dm_odm->is_linked) && (p_dm_odm->adapter->registrypriv.force_igi != 0)) { - printk("p_dm_odm->rssi_min=%d\n", p_dm_odm->rssi_min); - odm_write_dig(p_dm_odm, p_dm_odm->adapter->registrypriv.force_igi); - return true; - } -#endif -#else - if (!(priv->up_time > 5)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Not In DIG operation period\n")); - return true; - } #endif - return false; + return false; } -void -odm_dig_init( - void *p_dm_void -) +void phydm_dig_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct phydm_fa_struct *false_alm_cnt = &dm->false_alm_cnt; #endif - u32 ret_value; - u8 i; - - p_dm_dig_table->is_stop_dig = false; - p_dm_dig_table->is_ignore_dig = false; - p_dm_dig_table->is_psd_in_progress = false; - p_dm_dig_table->cur_ig_value = (u8) odm_get_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm)); - p_dm_dig_table->pre_ig_value = 0; - p_dm_dig_table->rssi_low_thresh = DM_DIG_THRESH_LOW; - p_dm_dig_table->rssi_high_thresh = DM_DIG_THRESH_HIGH; - p_dm_dig_table->fa_low_thresh = DM_FALSEALARM_THRESH_LOW; - p_dm_dig_table->fa_high_thresh = DM_FALSEALARM_THRESH_HIGH; - p_dm_dig_table->backoff_val = DM_DIG_BACKOFF_DEFAULT; - p_dm_dig_table->backoff_val_range_max = DM_DIG_BACKOFF_MAX; - p_dm_dig_table->backoff_val_range_min = DM_DIG_BACKOFF_MIN; - p_dm_dig_table->pre_cck_cca_thres = 0xFF; - p_dm_dig_table->cur_cck_cca_thres = 0x83; - p_dm_dig_table->forbidden_igi = DM_DIG_MIN_NIC; - p_dm_dig_table->large_fa_hit = 0; - p_dm_dig_table->large_fa_timeout = 0; - p_dm_dig_table->recover_cnt = 0; - p_dm_dig_table->is_media_connect_0 = false; - p_dm_dig_table->is_media_connect_1 = false; - - /* To Initialize p_dm_odm->is_dm_initial_gain_enable == false to avoid DIG error */ - p_dm_odm->is_dm_initial_gain_enable = true; + u32 ret_value = 0; + u8 i; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - p_dm_dig_table->dig_dynamic_min_0 = 0x25; - p_dm_dig_table->dig_dynamic_min_1 = 0x25; + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; + + dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A); - /* For AP\ ADSL modified DIG */ - p_dm_dig_table->is_tp_target = false; - p_dm_dig_table->is_noise_est = true; - p_dm_dig_table->igi_offset_a = 0; - p_dm_dig_table->igi_offset_b = 0; - p_dm_dig_table->tp_train_th_min = 0; + dig_t->is_media_connect = false; - /* For RTL8881A */ + dig_t->fa_th[0] = 250; + dig_t->fa_th[1] = 500; + dig_t->fa_th[2] = 750; + dig_t->is_dbg_fa_th = false; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + /* @For RTL8881A */ false_alm_cnt->cnt_ofdm_fail_pre = 0; +#endif - /* Dyanmic EDCCA */ - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_set_bb_reg(p_dm_odm, 0xC50, 0xFFFF0000, 0xfafd); -#else - p_dm_dig_table->dig_dynamic_min_0 = DM_DIG_MIN_NIC; - p_dm_dig_table->dig_dynamic_min_1 = DM_DIG_MIN_NIC; + dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE; + dig_t->rx_gain_range_min = dig_t->cur_ig_value; - /* To Initi BT30 IGI */ - p_dm_dig_table->bt30_cur_igi = 0x32; +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + dig_t->enable_adjust_big_jump = 1; + if (dm->support_ic_type & ODM_RTL8822B) + ret_value = odm_get_bb_reg(dm, R_0x8c8, MASKLWORD); + else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + ret_value = odm_get_bb_reg(dm, R_0xc74, MASKLWORD); - odm_memory_set(p_dm_odm, p_dm_dig_table->pause_dig_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); - p_dm_dig_table->pause_dig_level = 0; - odm_memory_set(p_dm_odm, p_dm_dig_table->pause_cckpd_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); - p_dm_dig_table->pause_cckpd_level = 0; -#endif + dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1; + dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4; + dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6; - if (p_dm_odm->board_type & (ODM_BOARD_EXT_PA | ODM_BOARD_EXT_LNA)) { - p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_NIC; - p_dm_dig_table->rx_gain_range_min = DM_DIG_MIN_NIC; - } else { - p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_NIC; - p_dm_dig_table->rx_gain_range_min = DM_DIG_MIN_NIC; - } - -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1) - p_dm_dig_table->enable_adjust_big_jump = 1; - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { - ret_value = odm_get_bb_reg(p_dm_odm, 0x8c8, MASKLWORD); - p_dm_dig_table->big_jump_step1 = (u8)(ret_value & 0xe) >> 1; - p_dm_dig_table->big_jump_step2 = (u8)(ret_value & 0x30) >> 4; - p_dm_dig_table->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6; - - } else if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_BB_AGC_SET_2_11N, MASKLWORD); - p_dm_dig_table->big_jump_step1 = (u8)(ret_value & 0xe) >> 1; - p_dm_dig_table->big_jump_step2 = (u8)(ret_value & 0x30) >> 4; - p_dm_dig_table->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6; - } - if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F)) { - for (i = 0; i < sizeof(p_dm_dig_table->big_jump_lmt); i++) { - if (p_dm_dig_table->big_jump_lmt[i] == 0) - p_dm_dig_table->big_jump_lmt[i] = 0x64; /* Set -10dBm as default value */ + if (dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) { + for (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) { + if (dig_t->big_jump_lmt[i] == 0) + dig_t->big_jump_lmt[i] = 0x64; + /* Set -10dBm as default value */ } } #endif - -#if (DIG_HW == 1) - p_dm_dig_table->pre_rssi_min = 0; +#ifdef PHYDM_TDMA_DIG_SUPPORT + dm->original_dig_restore = true; +#endif +#ifdef CFG_DIG_DAMPING_CHK + phydm_dig_recorder_reset(dm); + dig_t->dig_dl_en = 1; #endif } +void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + if (!dm->is_linked) { + dig_t->dm_dig_max = DIG_MAX_COVERAGR; + dig_t->dm_dig_min = DIG_MIN_COVERAGE; + } else if (is_dfs_band) { + if (*dm->band_width == CHANNEL_WIDTH_20) + dig_t->dm_dig_min = DIG_MIN_DFS + 2; + else + dig_t->dm_dig_min = DIG_MIN_DFS; + + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + } else { + if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) { + /*service > 2 devices*/ + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + #if (DIG_HW == 1) + dig_t->dig_max_of_min = DIG_MIN_COVERAGE; + #else + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; + #endif + } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) { + /*service 1 devices*/ + dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE; + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE; + } + + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)) + dig_t->dm_dig_min = 0x1c; + else if (dm->support_ic_type & ODM_RTL8197F) + dig_t->dm_dig_min = 0x1e; /*@For HW setting*/ + else + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; + } + + PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n", + dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min); +} -void -odm_DIG( - void *p_dm_void -) +void phydm_dig_dym_boundary_decision(struct dm_struct *dm) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; - struct sta_info *p_entry; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; +#ifdef CFG_DIG_DAMPING_CHK + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; #endif + u8 offset = 15, tmp_max = 0; + u8 max_of_rssi_min = 0; - /* Common parameters */ - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - boolean first_connect, first_dis_connect; - u8 dig_max_of_min, dig_dynamic_min; - u8 dm_dig_max, dm_dig_min; - u8 current_igi = p_dm_dig_table->cur_ig_value; - u8 offset; - u32 dm_FA_thres[3]; - u32 tx_tp = 0, rx_tp = 0; - boolean is_dfs_band = false; - boolean is_performance = true, is_first_tp_target = false, is_first_coverage = false; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u32 tp_train_th_min = dm_dig_tp_target_th0; - static u8 time_cnt = 0; - u8 i; -#endif -#if (DIG_HW == 1) - boolean dig_go_up_check = true; - u8 step_size_1 = 0, step_size_2 = 0, step_size_3 = 0; -#endif + PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__); + + if (!dm->is_linked) { + /*@if no link, always stay at lower bound*/ + dig_t->rx_gain_range_max = dig_t->dig_max_of_min; + dig_t->rx_gain_range_min = dig_t->dm_dig_min; - if (odm_dig_abort(p_dm_odm) == true) + PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n", + dig_t->rx_gain_range_max, dig_t->rx_gain_range_min); return; + } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG Start===>\n")); + PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", dm->rssi_min, offset); -#if (DIG_HW == 1) - if (p_dm_odm->is_linked) { - if (p_dm_dig_table->pre_rssi_min <= p_dm_odm->rssi_min) { - step_size_1 = 2; - step_size_2 = 1; - step_size_3 = 2; - } else { - step_size_1 = 4; - step_size_2 = 2; - step_size_3 = 2; - } - p_dm_dig_table->pre_rssi_min = p_dm_odm->rssi_min; - } else { - step_size_1 = 2; - step_size_2 = 1; - step_size_3 = 2; + /* @DIG lower bound */ + if (dm->rssi_min > dig_t->dig_max_of_min) + dig_t->rx_gain_range_min = dig_t->dig_max_of_min; + else if (dm->rssi_min < dig_t->dm_dig_min) + dig_t->rx_gain_range_min = dig_t->dm_dig_min; + else + dig_t->rx_gain_range_min = dm->rssi_min; + +#ifdef CFG_DIG_DAMPING_CHK + /*@Limit Dyn min by damping*/ + if (dig_t->dig_dl_en && + dig_rc->damping_limit_en && + dig_t->rx_gain_range_min < dig_rc->damping_limit_val) { + PHYDM_DBG(dm, DBG_DIG, + "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n", + dig_t->rx_gain_range_min, dig_rc->damping_limit_val); + + dig_t->rx_gain_range_min = dig_rc->damping_limit_val; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("rssi_min = %d, pre_rssi_min = %d\n", p_dm_odm->rssi_min, p_dm_dig_table->pre_rssi_min)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("step_size_1 = %d, step_size_2 = %d, step_size_3 = %d\n", step_size_1, step_size_2, step_size_3)); #endif - /* 1 Update status */ - { - dig_dynamic_min = p_dm_dig_table->dig_dynamic_min_0; - first_connect = (p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == false); - first_dis_connect = (!p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == true); + /* @DIG upper bound */ + tmp_max = dig_t->rx_gain_range_min + offset; + if (dig_t->rx_gain_range_min != dm->rssi_min) { + max_of_rssi_min = dm->rssi_min + offset; + if (tmp_max > max_of_rssi_min) + tmp_max = max_of_rssi_min; } -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - /* 1 Noise Floor Estimate */ - /* p_dm_dig_table->is_noise_est = (first_connect)?true:p_dm_dig_table->is_noise_est; */ - /* odm_inband_noise_calculate (p_dm_odm); */ - - /* 1 mode decision */ - if (p_dm_odm->is_linked) { - /* 2 Calculate total TP */ - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { - rx_tp += (u32)(p_entry->rx_byte_cnt_low_maw >> 7); - tx_tp += (u32)(p_entry->tx_byte_cnt_low_maw >> 7); /* Kbps */ - } - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: TX TP = %dkbps, RX TP = %dkbps\n", tx_tp, rx_tp)); - } + if (tmp_max > dig_t->dm_dig_max) + dig_t->rx_gain_range_max = dig_t->dm_dig_max; + else if (tmp_max < dig_t->dm_dig_min) + dig_t->rx_gain_range_max = dig_t->dm_dig_min; + else + dig_t->rx_gain_range_max = tmp_max; + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + /* @1 Force Lower Bound for AntDiv */ + if (!dm->is_one_entry_only && + (dm->support_ability & ODM_BB_ANT_DIV) && + (dm->ant_div_type == CG_TRX_HW_ANTDIV || + dm->ant_div_type == CG_TRX_SMART_ANTDIV)) { + if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min) + dig_t->rx_gain_range_min = dig_t->dig_max_of_min; + else + dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max; - switch (p_dm_odm->priv->pshare->rf_ft_var.dig_cov_enable) { - case 0: - { - is_performance = true; - break; - } - case 1: - { - is_performance = false; - break; + PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n", + dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max); } - case 2: - { - if (p_dm_odm->is_linked) { - if (p_dm_dig_table->tp_train_th_min > dm_dig_tp_target_th0) - tp_train_th_min = p_dm_dig_table->tp_train_th_min; - - if (p_dm_dig_table->tp_train_th_min > dm_dig_tp_target_th1) - tp_train_th_min = dm_dig_tp_target_th1; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: TP training mode lower bound = %dkbps\n", tp_train_th_min)); - - /* 2 Decide DIG mode by total TP */ - if ((tx_tp + rx_tp) > dm_dig_tp_target_th1) { /* change to performance mode */ - is_first_tp_target = (!p_dm_dig_table->is_tp_target) ? true : false; - p_dm_dig_table->is_tp_target = true; - is_performance = true; - } else if ((tx_tp + rx_tp) < tp_train_th_min) { /* change to coverage mode */ - is_first_coverage = (p_dm_dig_table->is_tp_target) ? true : false; - - if (time_cnt < dm_dig_tp_training_period) { - p_dm_dig_table->is_tp_target = false; - is_performance = false; - time_cnt++; - } else { - p_dm_dig_table->is_tp_target = true; - is_performance = true; - is_first_tp_target = true; - time_cnt = 0; - } - } else { /* remain previous mode */ - is_performance = p_dm_dig_table->is_tp_target; - - if (!is_performance) { - if (time_cnt < dm_dig_tp_training_period) - time_cnt++; - else { - p_dm_dig_table->is_tp_target = true; - is_performance = true; - is_first_tp_target = true; - time_cnt = 0; - } - } - } + #endif - if (!is_performance) - p_dm_dig_table->tp_train_th_min = rx_tp + tx_tp; + PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n", + dig_t->rx_gain_range_max, dig_t->rx_gain_range_min); +} - } else { - is_performance = false; - p_dm_dig_table->tp_train_th_min = 0; - } - break; - } - default: - is_performance = true; - } +void phydm_dig_abnormal_case(struct dm_struct *dm) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("====== DIG mode = %d ======\n", p_dm_odm->priv->pshare->rf_ft_var.dig_cov_enable)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("====== is_performance = %d ======\n", is_performance)); -#endif + /* @Abnormal lower bound case */ + if (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max) + dig_t->rx_gain_range_min = dig_t->rx_gain_range_max; - /* 1 Boundary Decision */ - { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - /* 2 For AP\ADSL */ - if (!is_performance) { - dm_dig_max = DM_DIG_MAX_AP_COVERAGR; - dm_dig_min = DM_DIG_MIN_AP_COVERAGE; -#if (DIG_HW == 1) - dig_max_of_min = DM_DIG_MIN_AP_COVERAGE; -#else - dig_max_of_min = DM_DIG_MAX_OF_MIN_COVERAGE; -#endif - - } else { - if (p_dm_odm->rf_type == ODM_1T1R) - dm_dig_max = DM_DIG_MAX_AP - 6; - else - dm_dig_max = DM_DIG_MAX_AP; + PHYDM_DBG(dm, DBG_DIG, "Abnoraml checked {Max, Min}={0x%x, 0x%x}\n", + dig_t->rx_gain_range_max, dig_t->rx_gain_range_min); +} - if ((*p_dm_odm->p_band_type == ODM_BAND_2_4G) && (p_dm_odm->support_ic_type & ODM_RTL8814A)) /* for 2G 8814 */ - dm_dig_min = 0x1c; - else if (p_dm_odm->support_ic_type & ODM_RTL8197F) - dm_dig_min = 0x1e; - else - dm_dig_min = DM_DIG_MIN_AP; +u8 phydm_new_igi_by_fa(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *step_size) +{ + boolean dig_go_up_check = true; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; -#if (DIG_HW == 1) - dig_max_of_min = DM_DIG_MIN_AP_COVERAGE; -#else - dig_max_of_min = DM_DIG_MAX_OF_MIN; +#if 0 + /*@dig_go_up_check = phydm_dig_go_up_check(dm);*/ #endif - } + if (fa_cnt > dig_t->fa_th[2] && dig_go_up_check) + igi = igi + step_size[0]; + else if ((fa_cnt > dig_t->fa_th[1]) && dig_go_up_check) + igi = igi + step_size[1]; + else if (fa_cnt < dig_t->fa_th[0]) + igi = igi - step_size[2]; - /* 4 TX2path */ - if (priv->pmib->dot11RFEntry.tx2path && !is_dfs_band && (*(p_dm_odm->p_wireless_mode) == ODM_WM_B)) - dm_dig_max = 0x2A; + return igi; +} -#if RTL8192E_SUPPORT -#ifdef HIGH_POWER_EXT_LNA - if ((p_dm_odm->support_ic_type & (ODM_RTL8192E)) && (p_dm_odm->ext_lna)) - dm_dig_max = 0x42; -#endif -#endif - if (p_dm_odm->igi_lower_bound) { - if (dm_dig_min < p_dm_odm->igi_lower_bound) - dm_dig_min = p_dm_odm->igi_lower_bound; - if (dig_max_of_min < p_dm_odm->igi_lower_bound) - dig_max_of_min = p_dm_odm->igi_lower_bound; - } - if (p_dm_odm->igi_upper_bound) { - if (dm_dig_max > p_dm_odm->igi_upper_bound) - dm_dig_max = p_dm_odm->igi_upper_bound; - if (dig_max_of_min > p_dm_odm->igi_upper_bound) - dig_max_of_min = p_dm_odm->igi_upper_bound; +u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_cnt, + boolean is_dfs_band) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 step[3] = {0}; + boolean first_connect = false, first_dis_connect = false; + + first_connect = (dm->is_linked) && !dig_t->is_media_connect; + first_dis_connect = (!dm->is_linked) && dig_t->is_media_connect; + + if (dm->is_linked) { + if (dm->pre_rssi_min <= dm->rssi_min) { + PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n"); + step[0] = 2; + step[1] = 1; + step[2] = 2; + } else { + step[0] = 4; + step[1] = 2; + step[2] = 2; } -#else - /* 2 For WIN\CE */ - if (p_dm_odm->support_ic_type >= ODM_RTL8188E) - dm_dig_max = 0x5A; - else - dm_dig_max = DM_DIG_MAX_NIC; + } else { + step[0] = 2; + step[1] = 1; + step[2] = 2; + } - if (p_dm_odm->support_ic_type != ODM_RTL8821) - dm_dig_min = DM_DIG_MIN_NIC; - else - dm_dig_min = 0x1C; + PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1], + step[0]); - dig_max_of_min = DM_DIG_MAX_AP; -#endif + if (first_connect) { + if (is_dfs_band) { + if (dm->rssi_min > DIG_MAX_DFS) + igi = DIG_MAX_DFS; + else + igi = dm->rssi_min; + PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n", + dig_t->rx_gain_range_max); + } else { + igi = dig_t->rx_gain_range_min; + } + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (RTL8812A_SUPPORT) + if (dm->support_ic_type == ODM_RTL8812) + odm_config_bb_with_header_file(dm, + CONFIG_BB_AGC_TAB_DIFF); + #endif + #endif + PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi); + } else if (dm->is_linked) { + PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n"); + /* @4 Abnormal # beacon case */ + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 && + fa_cnt < DM_DIG_FA_TH1 && dm->bsta_state && + dm->support_ic_type != ODM_RTL8723D) { + dig_t->rx_gain_range_min = 0x1c; + igi = dig_t->rx_gain_range_min; + PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n", + dm->phy_dbg_info.num_qry_beacon_pkt, igi); + } else { + igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step); + } + #else + igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step); + #endif + } else { + /* @2 Before link */ + PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n"); -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - /* Modify lower bound for DFS band */ - if ((((*p_dm_odm->p_channel >= 52) && (*p_dm_odm->p_channel <= 64)) || - ((*p_dm_odm->p_channel >= 100) && (*p_dm_odm->p_channel <= 140))) -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - && phydm_dfs_master_enabled(p_dm_odm) == true -#endif - ) { - is_dfs_band = true; - if (*p_dm_odm->p_band_width == ODM_BW20M) - dm_dig_min = DM_DIG_MIN_AP_DFS + 2; - else - dm_dig_min = DM_DIG_MIN_AP_DFS; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: ====== In DFS band ======\n")); + if (first_dis_connect) { + igi = dig_t->dm_dig_min; + PHYDM_DBG(dm, DBG_DIG, + "First disconnect:foce IGI to lower bound\n"); + } else { + PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n", + igi, fa_cnt); + + igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step); } -#endif } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Absolutly upper bound = 0x%x, lower bound = 0x%x\n", dm_dig_max, dm_dig_min)); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (p_dm_odm->pu1_forced_igi_lb && (0 < *p_dm_odm->pu1_forced_igi_lb)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Force IGI lb to: 0x%02x\n", *p_dm_odm->pu1_forced_igi_lb)); - dm_dig_min = *p_dm_odm->pu1_forced_igi_lb; - dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) : (dm_dig_min + 1); - } -#endif + /*@Check IGI by dyn-upper/lower bound */ + if (igi < dig_t->rx_gain_range_min) + igi = dig_t->rx_gain_range_min; - /* 1 Adjust boundary by RSSI */ - if (p_dm_odm->is_linked && is_performance) { - /* 2 Modify DIG upper bound */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - offset = 15; -#else - /* 4 Modify DIG upper bound for 92E, 8723A\B, 8821 & 8812 BT */ - if ((p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821)) && (p_dm_odm->is_bt_limited_dig == 1)) { - offset = 10; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Coex. case: Force upper bound to RSSI + %d\n", offset)); - } else - offset = 15; -#endif + if (igi > dig_t->rx_gain_range_max) + igi = dig_t->rx_gain_range_max; - if ((p_dm_odm->rssi_min + offset) > dm_dig_max) - p_dm_dig_table->rx_gain_range_max = dm_dig_max; - else if ((p_dm_odm->rssi_min + offset) < dm_dig_min) - p_dm_dig_table->rx_gain_range_max = dm_dig_min; - else - p_dm_dig_table->rx_gain_range_max = p_dm_odm->rssi_min + offset; + PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n", + fa_cnt, dig_t->cur_ig_value, igi); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - /* 2 Modify DIG lower bound */ - /* if(p_dm_odm->is_one_entry_only) */ - { - if (p_dm_odm->rssi_min < dm_dig_min) - dig_dynamic_min = dm_dig_min; - else if (p_dm_odm->rssi_min > dig_max_of_min) - dig_dynamic_min = dig_max_of_min; - else - dig_dynamic_min = p_dm_odm->rssi_min; + return igi; +} -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - if (is_dfs_band) { - dig_dynamic_min = dm_dig_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); - } -#endif - } -#else - { - /* 4 For AP */ -#ifdef __ECOS - HAL_REORDER_BARRIER(); -#else - rmb(); -#endif - if (is_dfs_band) { - dig_dynamic_min = dm_dig_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); - } else { - if (p_dm_odm->rssi_min < dm_dig_min) - dig_dynamic_min = dm_dig_min; - else if (p_dm_odm->rssi_min > dig_max_of_min) - dig_dynamic_min = dig_max_of_min; - else - dig_dynamic_min = p_dm_odm->rssi_min; - } - } -#endif - } else { -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - if (is_performance && is_dfs_band) { - p_dm_dig_table->rx_gain_range_max = 0x28; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: Force upper bound to 0x%x before link\n", p_dm_dig_table->rx_gain_range_max)); - } else -#endif - { - if (is_performance) - p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_OF_MIN; - else - p_dm_dig_table->rx_gain_range_max = dm_dig_max; - } - dig_dynamic_min = dm_dig_min; - } - - /* 1 Force Lower Bound for AntDiv */ - if (p_dm_odm->is_linked && !p_dm_odm->is_one_entry_only) { - if ((p_dm_odm->support_ic_type & ODM_ANTDIV_SUPPORT) && (p_dm_odm->support_ability & ODM_BB_ANT_DIV)) { - if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV || p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) { - if (p_dm_dig_table->ant_div_rssi_max > dig_max_of_min) - dig_dynamic_min = dig_max_of_min; - else - dig_dynamic_min = (u8) p_dm_dig_table->ant_div_rssi_max; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: AntDiv case: Force lower bound to 0x%x\n", dig_dynamic_min)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: AntDiv case: RSSI_max = 0x%x\n", p_dm_dig_table->ant_div_rssi_max)); - } - } +boolean phydm_dig_dfs_mode_en(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean dfs_mode_en = false; + + /* @Modify lower bound for DFS band */ + if (dm->is_dfs_band) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + dfs_mode_en = true; + #else + if (phydm_dfs_master_enabled(dm)) + dfs_mode_en = true; + #endif + PHYDM_DBG(dm, DBG_DIG, "In DFS band\n"); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust boundary by RSSI Upper bound = 0x%x, Lower bound = 0x%x\n", - p_dm_dig_table->rx_gain_range_max, dig_dynamic_min)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Link status: is_linked = %d, RSSI = %d, bFirstConnect = %d, bFirsrDisConnect = %d\n", - p_dm_odm->is_linked, p_dm_odm->rssi_min, first_connect, first_dis_connect)); + return dfs_mode_en; +} - /* 1 Modify DIG lower bound, deal with abnormal case */ - /* 2 Abnormal false alarm case */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - if (is_dfs_band) - p_dm_dig_table->rx_gain_range_min = dig_dynamic_min; - else +void phydm_dig(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; +#ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc; #endif - { - if (!p_dm_odm->is_linked) { - p_dm_dig_table->rx_gain_range_min = dig_dynamic_min; + boolean first_connect, first_disconnect; + u8 igi = dig_t->cur_ig_value; + u8 new_igi = 0x20; + u32 fa_cnt = falm_cnt->cnt_all; + boolean dfs_mode_en = false; - if (first_dis_connect) - p_dm_dig_table->forbidden_igi = dig_dynamic_min; - } else - p_dm_dig_table->rx_gain_range_min = odm_forbidden_igi_check(p_dm_odm, dig_dynamic_min, current_igi); - } +#ifdef PHYDM_TDMA_DIG_SUPPORT + if (!(dm->original_dig_restore)) { + if (dig_t->cur_ig_value_tdma == 0) + dig_t->cur_ig_value_tdma = dig_t->cur_ig_value; - /* 2 Abnormal # beacon case */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (p_dm_odm->is_linked && !first_connect) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Beacon Num (%d)\n", p_dm_odm->phy_dbg_info.num_qry_beacon_pkt)); - if ((p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 5) && (p_dm_odm->bsta_state)) { - p_dm_dig_table->rx_gain_range_min = 0x1c; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x\n", - p_dm_odm->phy_dbg_info.num_qry_beacon_pkt, p_dm_dig_table->rx_gain_range_min)); - } + igi = dig_t->cur_ig_value_tdma; + fa_cnt = falm_cnt_acc->cnt_all_1sec; } #endif - /* 2 Abnormal lower bound case */ - if (p_dm_dig_table->rx_gain_range_min > p_dm_dig_table->rx_gain_range_max) { - p_dm_dig_table->rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnrormal lower bound case: Force lower bound to 0x%x\n", p_dm_dig_table->rx_gain_range_min)); + if (phydm_dig_abort(dm)) { + dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A); + return; } + PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__); - /* 1 False alarm threshold decision */ - odm_fa_threshold_check(p_dm_odm, is_dfs_band, is_performance, rx_tp, tx_tp, dm_FA_thres); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: False alarm threshold = %d, %d, %d\n", dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); - - /* 1 Adjust initial gain by false alarm */ - if (p_dm_odm->is_linked && is_performance) { - /* 2 After link */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust IGI after link\n")); + /* @1 Update status */ + first_connect = (dm->is_linked) && !dig_t->is_media_connect; + first_disconnect = (!dm->is_linked) && dig_t->is_media_connect; - if (is_first_tp_target || (first_connect && is_performance)) { - p_dm_dig_table->large_fa_hit = 0; + PHYDM_DBG(dm, DBG_DIG, + "is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\n", + dm->is_linked, dm->rssi_min, first_connect, first_disconnect); -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) - if (is_dfs_band) { - if (p_dm_odm->rssi_min > 0x28) - current_igi = 0x28; - else - current_igi = p_dm_odm->rssi_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: One-shot to 0x28 upmost\n")); - } else -#endif - { - if (p_dm_odm->rssi_min < dig_max_of_min) { - if (current_igi < p_dm_odm->rssi_min) - current_igi = p_dm_odm->rssi_min; - } else { - if (current_igi < dig_max_of_min) - current_igi = dig_max_of_min; - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -#if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - odm_config_bb_with_header_file(p_dm_odm, CONFIG_BB_AGC_TAB_DIFF); -#endif -#endif - } + PHYDM_DBG(dm, DBG_DIG, "DIG ((%s)) mode\n", + (*dm->bb_op_mode ? "Balance" : "Performance")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First connect case: IGI does on-shot to 0x%x\n", current_igi)); + /*@DFS mode enable check*/ + dfs_mode_en = phydm_dig_dfs_mode_en(dm); - } else { +#ifdef CFG_DIG_DAMPING_CHK + /*Record IGI History*/ + phydm_dig_recorder(dm, first_connect, igi, fa_cnt); -#if ((DM_ODM_SUPPORT_TYPE & (ODM_AP)) && (DIG_HW == 1)) - if (priv->pshare->rf_ft_var.dig_upcheck_enable) - dig_go_up_check = phydm_dig_go_up_check(p_dm_odm); + /*@DIG Damping Check*/ + phydm_dig_damping_chk(dm); #endif -#if (DIG_HW == 1) - if ((p_false_alm_cnt->cnt_all > dm_FA_thres[2]) && dig_go_up_check) - current_igi = current_igi + step_size_1; - else if ((p_false_alm_cnt->cnt_all > dm_FA_thres[1]) && dig_go_up_check) - current_igi = current_igi + step_size_2; - else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) - current_igi = current_igi - step_size_3; -#else - if (p_false_alm_cnt->cnt_all > dm_FA_thres[2]) - current_igi = current_igi + 4; - else if (p_false_alm_cnt->cnt_all > dm_FA_thres[1]) - current_igi = current_igi + 2; - else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) - current_igi = current_igi - 2; -#endif + /*@Absolute Boundary Decision */ + phydm_dig_abs_boundary_decision(dm, dfs_mode_en); - /* 4 Abnormal # beacon case */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if ((p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 5) && (p_false_alm_cnt->cnt_all < DM_DIG_FA_TH1) && (p_dm_odm->bsta_state)) { - current_igi = p_dm_dig_table->rx_gain_range_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n", - p_dm_odm->phy_dbg_info.num_qry_beacon_pkt, current_igi)); - } -#endif - } - } else { - /* 2 Before link */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust IGI before link\n")); + /*@Dynamic Boundary Decision*/ + phydm_dig_dym_boundary_decision(dm); - if (first_dis_connect || is_first_coverage) { - current_igi = dm_dig_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First disconnect case: IGI does on-shot to lower bound\n")); - } else { + /*@Abnormal case check*/ + phydm_dig_abnormal_case(dm); -#if ((DM_ODM_SUPPORT_TYPE & (ODM_AP)) && (DIG_HW == 1)) - if (priv->pshare->rf_ft_var.dig_upcheck_enable) - dig_go_up_check = phydm_dig_go_up_check(p_dm_odm); -#endif + /*@FA threshold decision */ + phydm_fa_threshold_check(dm, dfs_mode_en); -#if (DIG_HW == 1) - if ((p_false_alm_cnt->cnt_all > dm_FA_thres[2]) && dig_go_up_check) - current_igi = current_igi + step_size_1; - else if ((p_false_alm_cnt->cnt_all > dm_FA_thres[1]) && dig_go_up_check) - current_igi = current_igi + step_size_2; - else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) - current_igi = current_igi - step_size_3; -#else - if (p_false_alm_cnt->cnt_all > dm_FA_thres[2]) - current_igi = current_igi + 4; - else if (p_false_alm_cnt->cnt_all > dm_FA_thres[1]) - current_igi = current_igi + 2; - else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) - current_igi = current_igi - 2; -#endif - } - } + /*Select new IGI by FA */ + new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en); - /* 1 Check initial gain by upper/lower bound */ - if (current_igi < p_dm_dig_table->rx_gain_range_min) - current_igi = p_dm_dig_table->rx_gain_range_min; + /* @1 Update status */ + #ifdef PHYDM_TDMA_DIG_SUPPORT + if (!(dm->original_dig_restore)) { + dig_t->cur_ig_value_tdma = new_igi; + /*@It is possible fa_acc_1sec_tsf >= */ + /*@1sec while tdma_dig_state == 0*/ + if (dig_t->tdma_dig_state != 0) + odm_write_dig(dm, dig_t->cur_ig_value_tdma); + } else + #endif + odm_write_dig(dm, new_igi); - if (current_igi > p_dm_dig_table->rx_gain_range_max) - current_igi = p_dm_dig_table->rx_gain_range_max; + dig_t->is_media_connect = dm->is_linked; +} - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: cur_ig_value=0x%x, TotalFA = %d\n", current_igi, p_false_alm_cnt->cnt_all)); +void phydm_dig_lps_32k(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 current_igi = dm->rssi_min; - /* 1 Update status */ - { -#if ((DM_ODM_SUPPORT_TYPE & ODM_WIN) || ((DM_ODM_SUPPORT_TYPE & ODM_CE) && (ODM_CONFIG_BT_COEXIST == 1))) - if (p_dm_odm->is_bt_hs_operation) { - if (p_dm_odm->is_linked) { - if (p_dm_dig_table->bt30_cur_igi > (current_igi)) - odm_write_dig(p_dm_odm, current_igi); - else - odm_write_dig(p_dm_odm, p_dm_dig_table->bt30_cur_igi); - - p_dm_dig_table->is_media_connect_0 = p_dm_odm->is_linked; - p_dm_dig_table->dig_dynamic_min_0 = dig_dynamic_min; - } else { - if (p_dm_odm->is_link_in_process) - odm_write_dig(p_dm_odm, 0x1c); - else if (p_dm_odm->is_bt_connect_process) - odm_write_dig(p_dm_odm, 0x28); - else - odm_write_dig(p_dm_odm, p_dm_dig_table->bt30_cur_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ - } - } else /* BT is not using */ -#endif - { - odm_write_dig(p_dm_odm, current_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ - p_dm_dig_table->is_media_connect_0 = p_dm_odm->is_linked; - p_dm_dig_table->dig_dynamic_min_0 = dig_dynamic_min; - } - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG end\n")); + odm_write_dig(dm, current_igi); } -void -odm_dig_by_rssi_lps( - void *p_dm_void -) +void phydm_dig_by_rssi_lps(void *dm_void) { #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt; - u8 rssi_lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */ - u8 current_igi = p_dm_odm->rssi_min; + u8 rssi_lower = DIG_MIN_LPS; /* @0x1E or 0x1C */ + u8 current_igi = dm->rssi_min; - if (odm_dig_abort(p_dm_odm) == true) + falm_cnt = &dm->false_alm_cnt; + if (phydm_dig_abort(dm)) return; - current_igi = current_igi + RSSI_OFFSET_DIG; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps()==>\n")); + current_igi = current_igi + RSSI_OFFSET_DIG_LPS; + PHYDM_DBG(dm, DBG_DIG, "%s==>\n", __func__); /* Using FW PS mode to make IGI */ - /* Adjust by FA in LPS MODE */ - if (p_false_alm_cnt->cnt_all > DM_DIG_FA_TH2_LPS) + /* @Adjust by FA in LPS MODE */ + if (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS) current_igi = current_igi + 4; - else if (p_false_alm_cnt->cnt_all > DM_DIG_FA_TH1_LPS) + else if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS) current_igi = current_igi + 2; - else if (p_false_alm_cnt->cnt_all < DM_DIG_FA_TH0_LPS) + else if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS) current_igi = current_igi - 2; - - /* Lower bound checking */ + /* @Lower bound checking */ /* RSSI Lower bound check */ - if ((p_dm_odm->rssi_min - 10) > DM_DIG_MIN_NIC) - rssi_lower = (p_dm_odm->rssi_min - 10); + if ((dm->rssi_min - 10) > DIG_MIN_LPS) + rssi_lower = (dm->rssi_min - 10); else - rssi_lower = DM_DIG_MIN_NIC; + rssi_lower = DIG_MIN_LPS; /* Upper and Lower Bound checking */ - if (current_igi > DM_DIG_MAX_NIC) - current_igi = DM_DIG_MAX_NIC; + if (current_igi > DIG_MAX_LPS) + current_igi = DIG_MAX_LPS; else if (current_igi < rssi_lower) current_igi = rssi_lower; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): p_false_alm_cnt->cnt_all = %d\n", p_false_alm_cnt->cnt_all)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): p_dm_odm->rssi_min = %d\n", p_dm_odm->rssi_min)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): current_igi = 0x%x\n", current_igi)); - - odm_write_dig(p_dm_odm, current_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ + PHYDM_DBG(dm, DBG_DIG, "fa_cnt_all=%d, rssi_min=%d, curr_igi=0x%x\n", + falm_cnt->cnt_all, dm->rssi_min, current_igi); + odm_write_dig(dm, current_igi); #endif } -/* 3============================================================ +/* @3============================================================ * 3 FASLE ALARM CHECK - * 3============================================================ */ - -void -odm_false_alarm_counter_statistics( - void *p_dm_void -) + * 3============================================================ + */ +void phydm_false_alarm_counter_reg_reset(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); - u32 ret_value; - -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - /* Mark there, and check this in odm_DMWatchDog */ -#if 0 /* (DM_ODM_SUPPORT_TYPE == ODM_AP) */ - struct rtl8192cd_priv *priv = p_dm_odm->priv; - if ((priv->auto_channel != 0) && (priv->auto_channel != 2)) - return; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; +#ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc; #endif + u32 false_alm_cnt; + +#ifdef PHYDM_TDMA_DIG_SUPPORT + if (!(dm->original_dig_restore)) { + if (dig_t->cur_ig_value_tdma == 0) + dig_t->cur_ig_value_tdma = dig_t->cur_ig_value; + + false_alm_cnt = falm_cnt_acc->cnt_all_1sec; + } else #endif + { + false_alm_cnt = falm_cnt->cnt_all; + } - if (!(p_dm_odm->support_ability & ODM_BB_FA_CNT)) - return; +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + /* reset CCK FA counter */ + odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 0); + odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 2); + + /* reset CCK CCA counter */ + odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 0); + odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 2); + + /* reset OFDM CCA counter, OFDM FA counter*/ + odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 1); + odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0); + } +#endif +#if (ODM_IC_11N_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + /*reset false alarm counter registers*/ + odm_set_bb_reg(dm, R_0xc0c, BIT(31), 1); + odm_set_bb_reg(dm, R_0xc0c, BIT(31), 0); + odm_set_bb_reg(dm, R_0xd00, BIT(27), 1); + odm_set_bb_reg(dm, R_0xd00, BIT(27), 0); + + /*update ofdm counter*/ + /*update page C counter*/ + odm_set_bb_reg(dm, R_0xc00, BIT(31), 0); + /*update page D counter*/ + odm_set_bb_reg(dm, R_0xd00, BIT(31), 0); + + /*reset CCK CCA counter*/ + odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 0); + odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 2); + + /*reset CCK FA counter*/ + odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 0); + odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 2); + + /*reset CRC32 counter*/ + odm_set_bb_reg(dm, R_0xf14, BIT(16), 1); + odm_set_bb_reg(dm, R_0xf14, BIT(16), 0); + } +#endif /* @#if (ODM_IC_11N_SERIES_SUPPORT) */ + +#if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if (RTL8881A_SUPPORT) + /* Reset FA counter by enable/disable OFDM */ + if ((dm->support_ic_type == ODM_RTL8881A) && + false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) { + /* reset OFDM */ + odm_set_bb_reg(dm, R_0x808, BIT(29), 0); + odm_set_bb_reg(dm, R_0x808, BIT(29), 1); + false_alm_cnt->cnt_ofdm_fail_pre = 0; + PHYDM_DBG(dm, DBG_FA_CNT, "Reset FA_cnt\n"); + } + #endif /* @#if (RTL8881A_SUPPORT) */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("FA_Counter()======>\n")); + /* reset OFDM FA countner */ + odm_set_bb_reg(dm, R_0x9a4, BIT(17), 1); + odm_set_bb_reg(dm, R_0x9a4, BIT(17), 0); -#if (ODM_IC_11N_SERIES_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + /* reset CCK FA counter */ + odm_set_bb_reg(dm, R_0xa2c, BIT(15), 0); + odm_set_bb_reg(dm, R_0xa2c, BIT(15), 1); - /* hold ofdm counter */ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */ + /* reset CCA counter */ + phydm_reset_bb_hw_cnt_ac(dm); + } +#endif /* @#if (ODM_IC_11AC_SERIES_SUPPORT) */ +} - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD); - false_alm_cnt->cnt_fast_fsync = (ret_value & 0xffff); - false_alm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); +void phydm_false_alarm_counter_reg_hold(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + /* @hold cck counter */ + odm_set_bb_reg(dm, R_0x1a2c, BIT(12), 1); + odm_set_bb_reg(dm, R_0x1a2c, BIT(14), 1); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + /*@hold ofdm counter*/ + /*@hold page C counter*/ + odm_set_bb_reg(dm, R_0xc00, BIT(31), 1); + /*@hold page D counter*/ + odm_set_bb_reg(dm, R_0xd00, BIT(31), 1); + + /*@hold cck counter*/ + odm_set_bb_reg(dm, R_0xa2c, BIT(12), 1); + odm_set_bb_reg(dm, R_0xa2c, BIT(14), 1); + } +} - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD); - false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff); - false_alm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); +#if (ODM_IC_11N_SERIES_SUPPORT) +void phydm_fa_cnt_statistics_n(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + u32 reg = 0; - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD); - false_alm_cnt->cnt_rate_illegal = (ret_value & 0xffff); - false_alm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); + if (!(dm->support_ic_type & ODM_IC_11N_SERIES)) + return; - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD); - false_alm_cnt->cnt_mcs_fail = (ret_value & 0xffff); + /* @hold ofdm & cck counter */ + phydm_false_alarm_counter_reg_hold(dm); - false_alm_cnt->cnt_ofdm_fail = false_alm_cnt->cnt_parity_fail + false_alm_cnt->cnt_rate_illegal + - false_alm_cnt->cnt_crc8_fail + false_alm_cnt->cnt_mcs_fail + - false_alm_cnt->cnt_fast_fsync + false_alm_cnt->cnt_sb_search_fail; + reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD); + fa_t->cnt_fast_fsync = (reg & 0xffff); + fa_t->cnt_sb_search_fail = ((reg & 0xffff0000) >> 16); - /* read CCK CRC32 counter */ - false_alm_cnt->cnt_cck_crc32_error = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CRC32_ERROR_CNT_11N, MASKDWORD); - false_alm_cnt->cnt_cck_crc32_ok = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CRC32_OK_CNT_11N, MASKDWORD); + reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD); + fa_t->cnt_ofdm_cca = (reg & 0xffff); + fa_t->cnt_parity_fail = ((reg & 0xffff0000) >> 16); - /* read OFDM CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD); - false_alm_cnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; - false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff; + reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD); + fa_t->cnt_rate_illegal = (reg & 0xffff); + fa_t->cnt_crc8_fail = ((reg & 0xffff0000) >> 16); - /* read HT CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD); - false_alm_cnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; - false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff; + reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD); + fa_t->cnt_mcs_fail = (reg & 0xffff); - /* read VHT CRC32 counter */ - false_alm_cnt->cnt_vht_crc32_error = 0; - false_alm_cnt->cnt_vht_crc32_ok = 0; - -#if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_SC_CNT_11N, MASKDWORD); - false_alm_cnt->cnt_bw_lsc = (ret_value & 0xffff); - false_alm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16); - } -#endif + fa_t->cnt_ofdm_fail = + fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal + + fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail + + fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail; - { - /* hold cck counter */ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1); + /* read CCK CRC32 counter */ + fa_t->cnt_cck_crc32_error = odm_get_bb_reg(dm, R_0xf84, MASKDWORD); + fa_t->cnt_cck_crc32_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD); - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0); - false_alm_cnt->cnt_cck_fail = ret_value; + /* read OFDM CRC32 counter */ + reg = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD); + fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16; + fa_t->cnt_ofdm_crc32_ok = reg & 0xffff; - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3); - false_alm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; + /* read HT CRC32 counter */ + reg = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD); + fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16; + fa_t->cnt_ht_crc32_ok = reg & 0xffff; - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD); - false_alm_cnt->cnt_cck_cca = ((ret_value & 0xFF) << 8) | ((ret_value & 0xFF00) >> 8); - } + /* read VHT CRC32 counter */ + fa_t->cnt_vht_crc32_error = 0; + fa_t->cnt_vht_crc32_ok = 0; - false_alm_cnt->cnt_all_pre = false_alm_cnt->cnt_all; + #if (RTL8723D_SUPPORT) + if (dm->support_ic_type == ODM_RTL8723D) { + /* read HT CRC32 agg counter */ + reg = odm_get_bb_reg(dm, R_0xfb8, MASKDWORD); + fa_t->cnt_ht_crc32_error_agg = (reg & 0xffff0000) >> 16; + fa_t->cnt_ht_crc32_ok_agg = reg & 0xffff; + } + #endif - false_alm_cnt->cnt_all = (false_alm_cnt->cnt_fast_fsync + - false_alm_cnt->cnt_sb_search_fail + - false_alm_cnt->cnt_parity_fail + - false_alm_cnt->cnt_rate_illegal + - false_alm_cnt->cnt_crc8_fail + - false_alm_cnt->cnt_mcs_fail + - false_alm_cnt->cnt_cck_fail); + #if (RTL8188E_SUPPORT) + if (dm->support_ic_type == ODM_RTL8188E) { + reg = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD); + fa_t->cnt_bw_lsc = (reg & 0xffff); + fa_t->cnt_bw_usc = ((reg & 0xffff0000) >> 16); + } + #endif - false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_ofdm_cca + false_alm_cnt->cnt_cck_cca; + reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0); + fa_t->cnt_cck_fail = reg; - if (p_dm_odm->support_ic_type >= ODM_RTL8188E) { - /*reset false alarm counter registers*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0); + reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3); + fa_t->cnt_cck_fail += (reg & 0xff) << 8; - /*update ofdm counter*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0); /*update page C counter*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0); /*update page D counter*/ + reg = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD); + fa_t->cnt_cck_cca = ((reg & 0xFF) << 8) | ((reg & 0xFF00) >> 8); - /*reset CCK CCA counter*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2); + fa_t->cnt_all_pre = fa_t->cnt_all; - /*reset CCK FA counter*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2); + fa_t->cnt_all = fa_t->cnt_fast_fsync + + fa_t->cnt_sb_search_fail + + fa_t->cnt_parity_fail + + fa_t->cnt_rate_illegal + + fa_t->cnt_crc8_fail + + fa_t->cnt_mcs_fail + + fa_t->cnt_cck_fail; - /*reset CRC32 counter*/ - odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_F_RST_11N, BIT(16), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_F_RST_11N, BIT(16), 0); - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", - false_alm_cnt->cnt_parity_fail, false_alm_cnt->cnt_rate_illegal, false_alm_cnt->cnt_crc8_fail, false_alm_cnt->cnt_mcs_fail, false_alm_cnt->cnt_fast_fsync, false_alm_cnt->cnt_sb_search_fail)); - - } + fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca + fa_t->cnt_cck_cca; + + PHYDM_DBG(dm, DBG_FA_CNT, + "[OFDM FA Detail] Parity_Fail=((%d)), Rate_Illegal=((%d)), CRC8_fail=((%d)), Mcs_fail=((%d)), Fast_Fsync=(( %d )), SBD_fail=((%d))\n", + fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal, + fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail, fa_t->cnt_fast_fsync, + fa_t->cnt_sb_search_fail); +} #endif #if (ODM_IC_11AC_SERIES_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - u32 cck_enable; +void phydm_fa_cnt_statistics_ac(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + u32 ret_value = 0; + u32 cck_enable; - /* read OFDM FA counter */ - false_alm_cnt->cnt_ofdm_fail = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_11AC, MASKLWORD); + if (!(dm->support_ic_type & ODM_IC_11AC_SERIES)) + return; - /* Read CCK FA counter */ - false_alm_cnt->cnt_cck_fail = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_FA_11AC, MASKLWORD); + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD); + fa_t->cnt_fast_fsync = ((ret_value & 0xffff0000) >> 16); - /* read CCK/OFDM CCA counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD); - false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16; - false_alm_cnt->cnt_cck_cca = ret_value & 0xffff; + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD); + fa_t->cnt_sb_search_fail = (ret_value & 0xffff); - /* read CCK CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD); - false_alm_cnt->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16; - false_alm_cnt->cnt_cck_crc32_ok = ret_value & 0xffff; + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD); + fa_t->cnt_parity_fail = (ret_value & 0xffff); + fa_t->cnt_rate_illegal = ((ret_value & 0xffff0000) >> 16); - /* read OFDM CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD); - false_alm_cnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; - false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff; + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD); + fa_t->cnt_crc8_fail = (ret_value & 0xffff); + fa_t->cnt_mcs_fail = ((ret_value & 0xffff0000) >> 16); - /* read HT CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD); - false_alm_cnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; - false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff; + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD); + fa_t->cnt_crc8_fail_vht = (ret_value & 0xffff) + + (ret_value & 0xffff0000 >> 16); - /* read VHT CRC32 counter */ - ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD); - false_alm_cnt->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16; - false_alm_cnt->cnt_vht_crc32_ok = ret_value & 0xffff; - -#if (RTL8881A_SUPPORT == 1) - /* For 8881A */ - if (p_dm_odm->support_ic_type == ODM_RTL8881A) { - u32 cnt_ofdm_fail_temp = 0; - - if (false_alm_cnt->cnt_ofdm_fail >= false_alm_cnt->cnt_ofdm_fail_pre) { - cnt_ofdm_fail_temp = false_alm_cnt->cnt_ofdm_fail_pre; - false_alm_cnt->cnt_ofdm_fail_pre = false_alm_cnt->cnt_ofdm_fail; - false_alm_cnt->cnt_ofdm_fail = false_alm_cnt->cnt_ofdm_fail - cnt_ofdm_fail_temp; - } else - false_alm_cnt->cnt_ofdm_fail_pre = false_alm_cnt->cnt_ofdm_fail; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_false_alarm_counter_statistics(): cnt_ofdm_fail=%d\n", false_alm_cnt->cnt_ofdm_fail_pre)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_false_alarm_counter_statistics(): cnt_ofdm_fail_pre=%d\n", cnt_ofdm_fail_temp)); - - /* Reset FA counter by enable/disable OFDM */ - if (false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) { - /* reset OFDM */ - odm_set_bb_reg(p_dm_odm, ODM_REG_BB_RX_PATH_11AC, BIT(29), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_BB_RX_PATH_11AC, BIT(29), 1); - false_alm_cnt->cnt_ofdm_fail_pre = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_false_alarm_counter_statistics(): Reset false alarm counter\n")); - } - } -#endif + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD); + fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff); - /* reset OFDM FA coutner */ - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0); + /* read OFDM FA counter */ + fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD); - /* reset CCK FA counter */ - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 0); - odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 1); + /* Read CCK FA counter */ + fa_t->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD); - /* reset CCA counter */ - odm_set_bb_reg(p_dm_odm, ODM_REG_RST_RPT_11AC, BIT(0), 1); - odm_set_bb_reg(p_dm_odm, ODM_REG_RST_RPT_11AC, BIT(0), 0); + /* read CCK/OFDM CCA counter */ + ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD); + fa_t->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16; + fa_t->cnt_cck_cca = ret_value & 0xffff; + + /* read CCK CRC32 counter */ + ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD); + fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16; + fa_t->cnt_cck_crc32_ok = ret_value & 0xffff; - cck_enable = odm_get_bb_reg(p_dm_odm, ODM_REG_BB_RX_PATH_11AC, BIT(28)); - if (cck_enable) { /* if(*p_dm_odm->p_band_type == ODM_BAND_2_4G) */ - false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail + false_alm_cnt->cnt_cck_fail; - false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_cck_cca + false_alm_cnt->cnt_ofdm_cca; + /* read OFDM CRC32 counter */ + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD); + fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; + fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff; + + /* read HT CRC32 counter */ + ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD); + fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; + fa_t->cnt_ht_crc32_ok = ret_value & 0xffff; + + /* read VHT CRC32 counter */ + ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD); + fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16; + fa_t->cnt_vht_crc32_ok = ret_value & 0xffff; + + #if (RTL8881A_SUPPORT) + if (dm->support_ic_type == ODM_RTL8881A) { + u32 tmp = 0; + + if (fa_t->cnt_ofdm_fail >= fa_t->cnt_ofdm_fail_pre) { + tmp = fa_t->cnt_ofdm_fail_pre; + fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail; + fa_t->cnt_ofdm_fail = fa_t->cnt_ofdm_fail - tmp; } else { - false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail; - false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_ofdm_cca; + fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail; } - } -#endif - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/ - false_alm_cnt->dbg_port0 = phydm_get_bb_dbg_port_value(p_dm_odm); - phydm_release_bb_dbg_port(p_dm_odm); - } - - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) { - false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(p_dm_odm) & BIT(30))>>30); - phydm_release_bb_dbg_port(p_dm_odm); + PHYDM_DBG(dm, DBG_FA_CNT, + "[8881]cnt_ofdm_fail{curr,pre}={%d,%d}\n", + fa_t->cnt_ofdm_fail_pre, tmp); } + #endif - false_alm_cnt->cnt_crc32_error_all = false_alm_cnt->cnt_vht_crc32_error + false_alm_cnt->cnt_ht_crc32_error + false_alm_cnt->cnt_ofdm_crc32_error + false_alm_cnt->cnt_cck_crc32_error; - false_alm_cnt->cnt_crc32_ok_all = false_alm_cnt->cnt_vht_crc32_ok + false_alm_cnt->cnt_ht_crc32_ok + false_alm_cnt->cnt_ofdm_crc32_ok + false_alm_cnt->cnt_cck_crc32_ok; + cck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28)); + if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */ + fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail; + fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca; + } else { + fa_t->cnt_all = fa_t->cnt_ofdm_fail; + fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca; + } +} +#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all)); +void phydm_get_dbg_port_info(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + u32 dbg_port = dm->adaptivity.adaptivity_dbg_port; + u32 val = 0; + + /*set debug port to 0x0*/ + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) { + fa_t->dbg_port0 = phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); + } + + if (dm->support_ic_type & ODM_RTL8723D) { + val = odm_get_bb_reg(dm, R_0x9a0, BIT(29)); + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + val = odm_get_bb_reg(dm, R_0x2d38, BIT(24)); + } else if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, dbg_port)) { + if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E)) + val = (phydm_get_bb_dbg_port_val(dm) & BIT(30)) >> 30; + else + val = (phydm_get_bb_dbg_port_val(dm) & BIT(29)) >> 29; + phydm_release_bb_dbg_port(dm); + } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", - false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all)); + fa_t->edcca_flag = (boolean)val; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[CCK] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_cck_crc32_error, false_alm_cnt->cnt_cck_crc32_ok)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[OFDM]CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ofdm_crc32_error, false_alm_cnt->cnt_ofdm_crc32_ok)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[ HT ] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ht_crc32_error, false_alm_cnt->cnt_ht_crc32_ok)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[VHT] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_vht_crc32_error, false_alm_cnt->cnt_vht_crc32_ok)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[VHT] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_crc32_error_all, false_alm_cnt->cnt_crc32_ok_all)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n\n", false_alm_cnt->dbg_port0, false_alm_cnt->edcca_flag)); + PHYDM_DBG(dm, DBG_FA_CNT, "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n\n", + fa_t->dbg_port0, fa_t->edcca_flag); } -/* 3============================================================ - * 3 CCK Packet Detect threshold - * 3============================================================ */ - -void -odm_pause_cck_packet_detection( - void *p_dm_void, - enum phydm_pause_type pause_type, - enum phydm_pause_level pause_level, - u8 cck_pd_threshold -) +void phydm_false_alarm_counter_statistics(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection()=========> level = %d\n", pause_level)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; - if ((p_dm_dig_table->pause_cckpd_level == 0) && (!(p_dm_odm->support_ability & ODM_BB_CCK_PD) || !(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Return: support_ability ODM_BB_CCK_PD or ODM_BB_FA_CNT is disabled\n")); + if (!(dm->support_ability & ODM_BB_FA_CNT)) return; - } - if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_pause_cck_packet_detection(): Return: Wrong pause level !!\n")); - return; - } + PHYDM_DBG(dm, DBG_FA_CNT, "%s======>\n", __func__); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_cckpd_level, cck_pd_threshold)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - p_dm_dig_table->pause_cckpd_value[7], p_dm_dig_table->pause_cckpd_value[6], p_dm_dig_table->pause_cckpd_value[5], p_dm_dig_table->pause_cckpd_value[4], - p_dm_dig_table->pause_cckpd_value[3], p_dm_dig_table->pause_cckpd_value[2], p_dm_dig_table->pause_cckpd_value[1], p_dm_dig_table->pause_cckpd_value[0])); + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + phydm_fa_cnt_statistics_jgr3(dm); + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + #if (ODM_IC_11N_SERIES_SUPPORT) + phydm_fa_cnt_statistics_n(dm); + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if (ODM_IC_11AC_SERIES_SUPPORT) + phydm_fa_cnt_statistics_ac(dm); + #endif + } - switch (pause_type) { - /* Pause CCK Packet Detection threshold */ - case PHYDM_PAUSE: - { - /* Disable CCK PD */ - odm_cmn_info_update(p_dm_odm, ODM_CMNINFO_ABILITY, p_dm_odm->support_ability & (~ODM_BB_CCK_PD)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Pause CCK packet detection threshold !!\n")); - - /* Backup original CCK PD threshold decided by CCK PD mechanism */ - if (p_dm_dig_table->pause_cckpd_level == 0) { - p_dm_dig_table->cck_pd_backup = p_dm_dig_table->cur_cck_cca_thres; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, - ("odm_pause_cck_packet_detection(): Backup CCKPD = 0x%x, new CCKPD = 0x%x\n", p_dm_dig_table->cck_pd_backup, cck_pd_threshold)); - } + phydm_get_dbg_port_info(dm); + phydm_false_alarm_counter_reg_reset(dm_void); + + fa_t->time_fa_all = fa_t->cnt_fast_fsync * 12 + + fa_t->cnt_sb_search_fail * 12 + + fa_t->cnt_parity_fail * 28 + + fa_t->cnt_rate_illegal * 28 + + fa_t->cnt_crc8_fail * 36 + + fa_t->cnt_crc8_fail_vht * 36 + + fa_t->cnt_mcs_fail_vht * 36 + + fa_t->cnt_mcs_fail * 32 + + fa_t->cnt_cck_fail * 80; + + fa_t->cnt_crc32_error_all = fa_t->cnt_vht_crc32_error + + fa_t->cnt_ht_crc32_error + + fa_t->cnt_ofdm_crc32_error + + fa_t->cnt_cck_crc32_error; + + fa_t->cnt_crc32_ok_all = fa_t->cnt_vht_crc32_ok + + fa_t->cnt_ht_crc32_ok + + fa_t->cnt_ofdm_crc32_ok + + fa_t->cnt_cck_crc32_ok; + + PHYDM_DBG(dm, DBG_FA_CNT, + "[OFDM FA Detail-1] Parity=((%d)), Rate_Illegal=((%d)), HT_CRC8=((%d)), HT_MCS=((%d))\n", + fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal, + fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail); + PHYDM_DBG(dm, DBG_FA_CNT, + "[OFDM FA Detail-2] Fast_Fsync=((%d)), SBD=((%d)), VHT_CRC8=((%d)), VHT_MCS=((%d))\n", + fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail, + fa_t->cnt_crc8_fail_vht, fa_t->cnt_mcs_fail_vht); + PHYDM_DBG(dm, DBG_FA_CNT, + "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all); + PHYDM_DBG(dm, DBG_FA_CNT, + "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all); + PHYDM_DBG(dm, DBG_FA_CNT, "[CCK] CRC32 {error, ok}= {%d, %d}\n", + fa_t->cnt_cck_crc32_error, fa_t->cnt_cck_crc32_ok); + PHYDM_DBG(dm, DBG_FA_CNT, "[OFDM]CRC32 {error, ok}= {%d, %d}\n", + fa_t->cnt_ofdm_crc32_error, fa_t->cnt_ofdm_crc32_ok); + PHYDM_DBG(dm, DBG_FA_CNT, "[ HT ] CRC32 {error, ok}= {%d, %d}\n", + fa_t->cnt_ht_crc32_error, fa_t->cnt_ht_crc32_ok); + PHYDM_DBG(dm, DBG_FA_CNT, "[VHT] CRC32 {error, ok}= {%d, %d}\n", + fa_t->cnt_vht_crc32_error, fa_t->cnt_vht_crc32_ok); + PHYDM_DBG(dm, DBG_FA_CNT, "[TOTAL] CRC32 {error, ok}= {%d, %d}\n", + fa_t->cnt_crc32_error_all, fa_t->cnt_crc32_ok_all); +} - /* Update pause level */ - p_dm_dig_table->pause_cckpd_level = (p_dm_dig_table->pause_cckpd_level | BIT(pause_level)); +#ifdef PHYDM_TDMA_DIG_SUPPORT +void phydm_set_tdma_dig_timer(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 delta_time_us = dm->tdma_dig_timer_ms * 1000; + struct phydm_dig_struct *dig_t; + u32 timeout; + u32 current_time_stamp, diff_time_stamp, regb0; + + dig_t = &dm->dm_dig_table; + /*some IC has no FREERUN_CUNT register, like 92E*/ + if (dm->support_ic_type & ODM_RTL8197F) + current_time_stamp = odm_get_bb_reg(dm, R_0x568, 0xffffffff); + else + return; - /* Record CCK PD threshold */ - p_dm_dig_table->pause_cckpd_value[pause_level] = cck_pd_threshold; + timeout = current_time_stamp + delta_time_us; - /* Write new CCK PD threshold */ - if (BIT(pause_level + 1) > p_dm_dig_table->pause_cckpd_level) { - odm_write_cck_cca_thres(p_dm_odm, cck_pd_threshold); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): CCKPD of higher level = 0x%x\n", cck_pd_threshold)); - } - break; - } - /* Resume CCK Packet Detection threshold */ - case PHYDM_RESUME: - { - /* check if the level is illegal or not */ - if ((p_dm_dig_table->pause_cckpd_level & (BIT(pause_level))) != 0) { - p_dm_dig_table->pause_cckpd_level = p_dm_dig_table->pause_cckpd_level & (~(BIT(pause_level))); - p_dm_dig_table->pause_cckpd_value[pause_level] = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Resume CCK PD !!\n")); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Wrong resume level !!\n")); - break; - } + diff_time_stamp = current_time_stamp - dig_t->cur_timestamp; + dig_t->pre_timestamp = dig_t->cur_timestamp; + dig_t->cur_timestamp = current_time_stamp; - /* Resume DIG */ - if (p_dm_dig_table->pause_cckpd_level == 0) { - /* Write backup IGI value */ - odm_write_cck_cca_thres(p_dm_odm, p_dm_dig_table->cck_pd_backup); - /* p_dm_dig_table->is_ignore_dig = true; */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Write original CCKPD = 0x%x\n", p_dm_dig_table->cck_pd_backup)); + /*@HIMR0, it shows HW interrupt mask*/ + regb0 = odm_get_bb_reg(dm, R_0xb0, 0xffffffff); - /* Enable DIG */ - odm_cmn_info_update(p_dm_odm, ODM_CMNINFO_ABILITY, p_dm_odm->support_ability | ODM_BB_CCK_PD); - break; - } + PHYDM_DBG(dm, DBG_DIG, "Set next timer\n"); + PHYDM_DBG(dm, DBG_DIG, + "curr_time_stamp=%d, delta_time_us=%d\n", + current_time_stamp, delta_time_us); + PHYDM_DBG(dm, DBG_DIG, + "timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n", + timeout, diff_time_stamp, regb0); - if (BIT(pause_level) > p_dm_dig_table->pause_cckpd_level) { - s8 max_level; + if (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/ + odm_set_bb_reg(dm, R_0x588, 0xffffffff, timeout); + else { + PHYDM_DBG(dm, DBG_DIG, "NOT 97F, NOT start\n"); + return; + } +} - /* Calculate the maximum level now */ - for (max_level = (pause_level - 1); max_level >= 0; max_level--) { - if ((p_dm_dig_table->pause_cckpd_level & BIT(max_level)) > 0) - break; +void phydm_tdma_dig_timer_check(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t; + + dig_t = &dm->dm_dig_table; + + PHYDM_DBG(dm, DBG_DIG, "tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n", + dig_t->tdma_dig_cnt, dig_t->pre_tdma_dig_cnt); + + if (dig_t->tdma_dig_cnt == 0 || + dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt) { + if (dm->support_ability & ODM_BB_DIG) { +#ifdef IS_USE_NEW_TDMA + if (dm->support_ic_type & + (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B)) { + PHYDM_DBG(dm, DBG_DIG, + "Check fail, Restart timer\n\n"); + phydm_false_alarm_counter_reset(dm); + odm_set_timer(dm, &dm->tdma_dig_timer, + dm->tdma_dig_timer_ms); + } else { + PHYDM_DBG(dm, DBG_DIG, + "Not 98F/22C/14B no SW timer\n"); } +#else + /*@if interrupt mask info is got.*/ + /*Reg0xb0 is no longer needed*/ +#if 0 + /*regb0 = odm_get_bb_reg(dm, R_0xb0, bMaskDWord);*/ +#endif + PHYDM_DBG(dm, DBG_DIG, + "Check fail, Mask[0]=0x%x, restart timer\n", + *dm->interrupt_mask); - /* write CCKPD of lower level */ - odm_write_cck_cca_thres(p_dm_odm, p_dm_dig_table->pause_cckpd_value[max_level]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Write CCKPD (0x%x) of level (%d)\n", - p_dm_dig_table->pause_cckpd_value[max_level], max_level)); - break; + phydm_tdma_dig_add_interrupt_mask_handler(dm); + phydm_enable_rx_related_interrupt_handler(dm); + phydm_set_tdma_dig_timer(dm); +#endif } - break; - } - default: - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Wrong type !!\n")); - break; + } else { + PHYDM_DBG(dm, DBG_DIG, "Check pass, update pre_tdma_dig_cnt\n"); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_cckpd_level, cck_pd_threshold)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", - p_dm_dig_table->pause_cckpd_value[7], p_dm_dig_table->pause_cckpd_value[6], p_dm_dig_table->pause_cckpd_value[5], p_dm_dig_table->pause_cckpd_value[4], - p_dm_dig_table->pause_cckpd_value[3], p_dm_dig_table->pause_cckpd_value[2], p_dm_dig_table->pause_cckpd_value[1], p_dm_dig_table->pause_cckpd_value[0])); + dig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt; } - -void -odm_cck_packet_detection_thresh( - void *p_dm_void -) +/*@different IC/team may use different timer for tdma-dig*/ +void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - u8 cur_cck_cca_thres = p_dm_dig_table->cur_cck_cca_thres, RSSI_thd = 35; - u8 pd_th = 0, cs_ration = 0; - + struct dm_struct *dm = (struct dm_struct *)dm_void; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* modify by Guo.Mingzhi 2011-12-29 */ - if (p_dm_odm->is_dual_mac_smart_concurrent == true) - return; - - if (p_dm_odm->is_bt_hs_operation) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: 0xcd for BT HS mode!!\n")); - odm_write_cck_cca_thres(p_dm_odm, 0xcd); - return; +#if (DM_ODM_SUPPORT_TYPE == (ODM_AP)) + if (dm->support_ic_type & ODM_RTL8197F) { + /*@HAL_INT_TYPE_PSTIMEOUT2*/ + phydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2); } +#elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN)) +#elif (DM_ODM_SUPPORT_TYPE == (ODM_CE)) #endif +} - if ((!(p_dm_odm->support_ability & ODM_BB_CCK_PD)) || (!(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: return==========\n")); - #ifdef MCR_WIRELESS_EXTEND - odm_write_cck_cca_thres(p_dm_odm, 0x43); - #endif +/* will be triggered by HW timer*/ +void phydm_tdma_dig(void *dm_void) +{ + struct dm_struct *dm; + struct phydm_dig_struct *dig_t; + struct phydm_fa_struct *falm_cnt; + u32 reg_c50; + +#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT) +#ifdef IS_USE_NEW_TDMA + if (dm->support_ic_type & + (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B)) { + PHYDM_DBG(dm, DBG_DIG, "98F/22C/14B, new tdma\n"); return; } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - if (p_dm_odm->ext_lna) - return; +#endif #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: ==========>\n")); + dm = (struct dm_struct *)dm_void; + dig_t = &dm->dm_dig_table; + falm_cnt = &dm->false_alm_cnt; + reg_c50 = odm_get_bb_reg(dm, R_0xc50, MASKBYTE0); - if (p_dm_dig_table->cck_fa_ma == 0xffffffff) - p_dm_dig_table->cck_fa_ma = false_alm_cnt->cnt_cck_fail; - else - p_dm_dig_table->cck_fa_ma = ((p_dm_dig_table->cck_fa_ma << 1) + p_dm_dig_table->cck_fa_ma + false_alm_cnt->cnt_cck_fail) >> 2; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: CCK FA moving average = %d\n", p_dm_dig_table->cck_fa_ma)); + dig_t->tdma_dig_state = + dig_t->tdma_dig_cnt % dm->tdma_dig_state_number; - if (p_dm_odm->is_linked) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, regc50=0x%x\n", + dig_t->tdma_dig_state, reg_c50); - #if 0 /*for [PCIE-1596]*/ - if (p_dm_odm->rssi_min > (RSSI_thd + 14)) - cur_cck_cca_thres = 0xed; - else if (p_dm_odm->rssi_min > (RSSI_thd + 6)) - cur_cck_cca_thres = 0xdd; - else - #endif - #if 0 /*for LPS power consumption issue*/ - if (p_dm_odm->traffic_load == TRAFFIC_ULTRA_LOW) - cur_cck_cca_thres = 0x40; - else - #endif - { - if (p_dm_odm->rssi_min > RSSI_thd) - cur_cck_cca_thres = 0xcd; - else if (p_dm_odm->rssi_min > 20) { - if (p_dm_dig_table->cck_fa_ma > ((DM_DIG_FA_TH1 >> 1) + (DM_DIG_FA_TH1 >> 3))) - cur_cck_cca_thres = 0xcd; - else if (p_dm_dig_table->cck_fa_ma < (DM_DIG_FA_TH0 >> 1)) - cur_cck_cca_thres = 0x83; - } else if (p_dm_odm->rssi_min > 7) - cur_cck_cca_thres = 0x83; - else - cur_cck_cca_thres = 0x40; - } - -#else /*ODM_AP*/ - - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - if ((p_dm_dig_table->cur_ig_value > (0x24 + 14)) || (p_dm_odm->rssi_min > 32)) - cur_cck_cca_thres = 0xed; - else if ((p_dm_dig_table->cur_ig_value > (0x24 + 6)) || (p_dm_odm->rssi_min > 32)) - cur_cck_cca_thres = 0xdd; - else if ((p_dm_dig_table->cur_ig_value > 0x24) || (p_dm_odm->rssi_min > 24 && p_dm_odm->rssi_min <= 30)) - cur_cck_cca_thres = 0xcd; - else if ((p_dm_dig_table->cur_ig_value <= 0x24) || (p_dm_odm->rssi_min < 22)) { - if (p_dm_dig_table->cck_fa_ma > 0x400) - cur_cck_cca_thres = 0x83; - else if (p_dm_dig_table->cck_fa_ma < 0x200) - cur_cck_cca_thres = 0x40; - } - } else { - if (p_dm_dig_table->cur_ig_value > (0x24 + 14)) - cur_cck_cca_thres = 0xed; - else if (p_dm_dig_table->cur_ig_value > (0x24 + 6)) - cur_cck_cca_thres = 0xdd; - else if (p_dm_dig_table->cur_ig_value > 0x24) - cur_cck_cca_thres = 0xcd; - else { - #if 0 - if (p_dm_dig_table->cck_fa_ma > 0x400) - cur_cck_cca_thres = 0x83; - else if (p_dm_dig_table->cck_fa_ma < 0x200) - cur_cck_cca_thres = 0x40; - #else - cur_cck_cca_thres = 0x83; - #endif - } - } + dig_t->tdma_dig_cnt++; -#endif - } else { - - if (p_dm_dig_table->cck_fa_ma > 0x400) - cur_cck_cca_thres = 0x83; - else if (p_dm_dig_table->cck_fa_ma < 0x200) - cur_cck_cca_thres = 0x40; - } - - #if (RTL8197F_SUPPORT == 1) - /*Add by Yu Chen 20160902, pd_th for 0xa0a, cs_ration for 0xaaa*/ - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - switch (cur_cck_cca_thres) { - case 0xed: - cs_ration = p_dm_dig_table->aaa_default + AAA_BASE + AAA_STEP*2; - pd_th = 0xd; - break; + if (dig_t->tdma_dig_state == 1) { + /* update IGI from tdma_dig_state == 0*/ + if (dig_t->cur_ig_value_tdma == 0) + dig_t->cur_ig_value_tdma = dig_t->cur_ig_value; - case 0xdd: - cs_ration = p_dm_dig_table->aaa_default + AAA_BASE + AAA_STEP; - pd_th = 0xd; - break; - - case 0xcd: - cs_ration = p_dm_dig_table->aaa_default + AAA_BASE; - pd_th = 0xd; - break; + odm_write_dig(dm, dig_t->cur_ig_value_tdma); + phydm_tdma_false_alarm_counter_check(dm); + PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, reset FA counter\n", + dig_t->tdma_dig_state); - case 0x83: - cs_ration = p_dm_dig_table->aaa_default + AAA_STEP; - pd_th = 0x7; - break; + } else if (dig_t->tdma_dig_state == 0) { + /* update dig_t->CurIGValue,*/ + /* @it may different from dig_t->cur_ig_value_tdma */ + /* TDMA IGI upperbond @ L-state = */ + /* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */ - case 0x40: - cs_ration = p_dm_dig_table->aaa_default; - pd_th = 0x3; - break; + if (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond) + dig_t->low_ig_value = dm->tdma_dig_low_upper_bond; + else + dig_t->low_ig_value = dig_t->cur_ig_value; - default: - cs_ration = p_dm_dig_table->aaa_default; - pd_th = 0x3; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cck pd use default\n")); - break; - } + odm_write_dig(dm, dig_t->low_ig_value); + phydm_tdma_false_alarm_counter_check(dm); + } else { + phydm_tdma_false_alarm_counter_check(dm); } - #endif /*#if (RTL8197F_SUPPORT == 1)*/ +} - #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) { - odm_set_bb_reg(p_dm_odm, 0xa08, 0xf0000, pd_th); - odm_set_bb_reg(p_dm_odm, 0xaa8, 0x1f0000, cs_ration); - } else - #endif - { - odm_write_cck_cca_thres(p_dm_odm, cur_cck_cca_thres); +/*@============================================================*/ +/*@FASLE ALARM CHECK*/ +/*@============================================================*/ +void phydm_tdma_false_alarm_counter_check(void *dm_void) +{ + struct dm_struct *dm; + struct phydm_fa_struct *falm_cnt; + struct phydm_fa_acc_struct *falm_cnt_acc; + struct phydm_dig_struct *dig_t; + boolean rssi_dump_en = 0; + u32 timestamp; + u8 tdma_dig_state_number; + u32 start_th = 0; + + dm = (struct dm_struct *)dm_void; + falm_cnt = &dm->false_alm_cnt; + falm_cnt_acc = &dm->false_alm_cnt_acc; + dig_t = &dm->dm_dig_table; + + if (dig_t->tdma_dig_state == 1) + phydm_false_alarm_counter_reset(dm); + /* Reset FalseAlarmCounterStatistics */ + /* @fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */ + /* @fa_end_tsf = fa_start_tsf = TSF */ + else { + phydm_false_alarm_counter_statistics(dm); + if (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/ + timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord); + else { + PHYDM_DBG(dm, DBG_DIG, "NOT 97F! NOT start\n"); + return; + } + dig_t->fa_end_timestamp = timestamp; + dig_t->fa_acc_1sec_timestamp += + (dig_t->fa_end_timestamp - dig_t->fa_start_timestamp); + + /*prevent dumb*/ + if (dm->tdma_dig_state_number == 1) + dm->tdma_dig_state_number = 2; + + tdma_dig_state_number = dm->tdma_dig_state_number; + dig_t->sec_factor = + tdma_dig_state_number / (tdma_dig_state_number - 1); + + /*@1sec = 1000000us*/ + if (dig_t->sec_factor) + start_th = (u32)(1000000 / dig_t->sec_factor); + + if (dig_t->fa_acc_1sec_timestamp >= start_th) { + rssi_dump_en = 1; + phydm_false_alarm_counter_acc(dm, rssi_dump_en); + PHYDM_DBG(dm, DBG_DIG, + "sec_factor=%d, total FA=%d, is_linked=%d\n", + dig_t->sec_factor, falm_cnt_acc->cnt_all, + dm->is_linked); + + phydm_noisy_detection(dm); + #ifdef PHYDM_SUPPORT_CCKPD + phydm_cck_pd_th(dm); + #endif + phydm_dig(dm); + phydm_false_alarm_counter_acc_reset(dm); + + /* Reset FalseAlarmCounterStatistics */ + /* @fa_end_tsf = fa_start_tsf = TSF, keep */ + /* @fa_acc_1sec_tsf = 0 */ + phydm_false_alarm_counter_reset(dm); + } else { + phydm_false_alarm_counter_acc(dm, rssi_dump_en); + } } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: cck_cca_th=((0x%x))\n\n", cur_cck_cca_thres)); } -void -odm_write_cck_cca_thres( - void *p_dm_void, - u8 cur_cck_cca_thres -) +void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - - if (p_dm_dig_table->cur_cck_cca_thres != cur_cck_cca_thres) { /* modify by Guo.Mingzhi 2012-01-03 */ - odm_write_1byte(p_dm_odm, ODM_REG(CCK_CCA, p_dm_odm), cur_cck_cca_thres); - p_dm_dig_table->cck_fa_ma = 0xffffffff; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt; + struct phydm_fa_acc_struct *falm_cnt_acc; + struct phydm_dig_struct *dig_t; + + falm_cnt = &dm->false_alm_cnt; + falm_cnt_acc = &dm->false_alm_cnt_acc; + dig_t = &dm->dm_dig_table; + + falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail; + falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal; + falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail; + falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail; + falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail; + falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail; + falm_cnt_acc->cnt_all += falm_cnt->cnt_all; + falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync; + falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail; + falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca; + falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca; + falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all; + falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error; + falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok; + falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error; + falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok; + falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error; + falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok; + falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error; + falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok; + falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all; + falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all; + + if (rssi_dump_en == 1) { + falm_cnt_acc->cnt_all_1sec = + falm_cnt_acc->cnt_all * dig_t->sec_factor; + falm_cnt_acc->cnt_cca_all_1sec = + falm_cnt_acc->cnt_cca_all * dig_t->sec_factor; + falm_cnt_acc->cnt_cck_fail_1sec = + falm_cnt_acc->cnt_cck_fail * dig_t->sec_factor; } - p_dm_dig_table->pre_cck_cca_thres = p_dm_dig_table->cur_cck_cca_thres; - p_dm_dig_table->cur_cck_cca_thres = cur_cck_cca_thres; } -boolean -phydm_dig_go_up_check( - void *p_dm_void -) +void phydm_false_alarm_counter_acc_reset(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 cur_ig_value = p_dm_dig_table->cur_ig_value; - u8 max_DIG_cover_bond; - u8 current_igi_max_up_resolution; - u8 rx_gain_range_max; - u8 i = 0; - - u32 total_NHM_cnt; - u32 DIG_cover_cnt; - u32 over_DIG_cover_cnt; - boolean ret = true; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_acc_struct *falm_cnt_acc = NULL; + +#ifdef IS_USE_NEW_TDMA + struct phydm_fa_acc_struct *falm_cnt_acc_low = NULL; + u32 tmp_cca_1sec = 0; + u32 tmp_fa_1sec = 0; + + /*@clear L-fa_acc struct*/ + falm_cnt_acc_low = &dm->false_alm_cnt_acc_low; + tmp_cca_1sec = falm_cnt_acc_low->cnt_cca_all_1sec; + tmp_fa_1sec = falm_cnt_acc_low->cnt_all_1sec; + odm_memory_set(dm, falm_cnt_acc_low, 0, sizeof(dm->false_alm_cnt_acc)); + falm_cnt_acc_low->cnt_cca_all_1sec = tmp_cca_1sec; + falm_cnt_acc_low->cnt_all_1sec = tmp_fa_1sec; + + /*@clear H-fa_acc struct*/ + falm_cnt_acc = &dm->false_alm_cnt_acc; + tmp_cca_1sec = falm_cnt_acc->cnt_cca_all_1sec; + tmp_fa_1sec = falm_cnt_acc->cnt_all_1sec; + odm_memory_set(dm, falm_cnt_acc, 0, sizeof(dm->false_alm_cnt_acc)); + falm_cnt_acc->cnt_cca_all_1sec = tmp_cca_1sec; + falm_cnt_acc->cnt_all_1sec = tmp_fa_1sec; +#else + falm_cnt_acc = &dm->false_alm_cnt_acc; + /* @Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */ + /* @do NOT need to be reset */ + odm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc)); +#endif +} -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; +void phydm_false_alarm_counter_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt; + struct phydm_dig_struct *dig_t; + u32 timestamp; - max_DIG_cover_bond = DM_DIG_MAX_AP - priv->pshare->rf_ft_var.dig_upcheck_initial_value; - current_igi_max_up_resolution = cur_ig_value + 6; - rx_gain_range_max = p_dm_dig_table->rx_gain_range_max; + falm_cnt = &dm->false_alm_cnt; + dig_t = &dm->dm_dig_table; - phydm_get_nhm_result(p_dm_odm); + memset(falm_cnt, 0, sizeof(dm->false_alm_cnt)); + phydm_false_alarm_counter_reg_reset(dm); - total_NHM_cnt = ccx_info->NHM_result[0] + ccx_info->NHM_result[1]; +#ifdef IS_USE_NEW_TDMA + return; +#endif + if (dig_t->tdma_dig_state != 1) + dig_t->fa_acc_1sec_timestamp = 0; + else + dig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): *****Get NHM results*****\n")); + /*REG_FREERUN_CNT*/ + timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord); + dig_t->fa_start_timestamp = timestamp; + dig_t->fa_end_timestamp = timestamp; +} - if (total_NHM_cnt != 0) { +#ifdef IS_USE_NEW_TDMA +void phydm_tdma_dig_timers(void *dm_void, u8 state) +{ +#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + if (dm->support_ic_type & + (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B)) { + if (state == INIT_TDMA_DIG_TIMMER) + odm_initialize_timer(dm, &dm->tdma_dig_timer, + (void *)phydm_tdma_dig_cbk, + NULL, "phydm_tdma_dig_timer"); + else if (state == CANCEL_TDMA_DIG_TIMMER) + odm_cancel_timer(dm, &dm->tdma_dig_timer); + else if (state == RELEASE_TDMA_DIG_TIMMER) + odm_release_timer(dm, &dm->tdma_dig_timer); + } +#endif +} - /* cur_ig_value < max_DIG_cover_bond - 6 */ - if (p_dm_dig_table->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_0) { - DIG_cover_cnt = ccx_info->NHM_result[1]; - ret = ((priv->pshare->rf_ft_var.dig_level0_ratio_reciprocal * DIG_cover_cnt) >= total_NHM_cnt) ? true : false; +u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max, + u8 *rx_gain_min, boolean is_dfs_band) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 step[3] = {0}; + u8 cur_igi = igi; + boolean first_connect = false, first_dis_connect = false; + + first_connect = (dm->is_linked) && !dig_t->is_media_connect; + first_dis_connect = (!dm->is_linked) && dig_t->is_media_connect; + + if (dm->is_linked) { + if (dm->pre_rssi_min <= dm->rssi_min) { + PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n"); + step[0] = 2; + step[1] = 1; + step[2] = 2; + } else { + step[0] = 4; + step[1] = 2; + step[2] = 2; } + } else { + step[0] = 2; + step[1] = 1; + step[2] = 2; + } - /* (max_DIG_cover_bond - 6) <= cur_ig_value < DM_DIG_MAX_AP */ - else if (p_dm_dig_table->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_1) { - over_DIG_cover_cnt = ccx_info->NHM_result[1]; - ret = (priv->pshare->rf_ft_var.dig_level1_ratio_reciprocal * over_DIG_cover_cnt < total_NHM_cnt) ? true : false; - - if (!ret) { - /* update p_dm_dig_table->rx_gain_range_max */ - p_dm_dig_table->rx_gain_range_max = (rx_gain_range_max >= max_DIG_cover_bond - 6) ? (max_DIG_cover_bond - 6) : rx_gain_range_max; + PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1], + step[0]); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): Noise power is beyond DIG can filter, lock rx_gain_range_max to 0x%x\n", - p_dm_dig_table->rx_gain_range_max)); - } + if (first_connect) { + if (is_dfs_band) { + if (dm->rssi_min > DIG_MAX_DFS) + igi = DIG_MAX_DFS; + else + igi = dm->rssi_min; + PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n", + *rx_gain_max); + } else { + igi = *rx_gain_min; } - /* cur_ig_value > DM_DIG_MAX_AP, foolproof */ - else if (p_dm_dig_table->dig_go_up_check_level == DIG_GOUPCHECK_LEVEL_2) - ret = true; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): DIG_GoUpCheck_level = %d\n, current_igi_max_up_resolution = 0x%x\n, max_DIG_cover_bond = 0x%x\n, rx_gain_range_max = 0x%x, ret = %d\n", - p_dm_dig_table->dig_go_up_check_level, - current_igi_max_up_resolution, - max_DIG_cover_bond, - p_dm_dig_table->rx_gain_range_max, - ret)); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): NHM_result = %d, %d, %d, %d\n", - ccx_info->NHM_result[0], ccx_info->NHM_result[1], ccx_info->NHM_result[2], ccx_info->NHM_result[3])); - - } else - ret = true; + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (RTL8812A_SUPPORT) + if (dm->support_ic_type == ODM_RTL8812) + odm_config_bb_with_header_file(dm, + CONFIG_BB_AGC_TAB_DIFF); + #endif + #endif + PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi); + } else if (dm->is_linked) { + PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n"); + /* @4 Abnormal # beacon case */ + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 && + fa_cnt < DM_DIG_FA_TH1 && dm->bsta_state && + dm->support_ic_type != ODM_RTL8723D) { + *rx_gain_min = 0x1c; + igi = *rx_gain_min; + PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n", + dm->phy_dbg_info.num_qry_beacon_pkt, igi); + } else { + igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step); + } + #else + igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step); + #endif + } else { + /* @2 Before link */ + PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n"); - for (i = 0 ; i <= 10 ; i++) - ccx_info->NHM_th[i] = 0xFF; + if (first_dis_connect) { + igi = dig_t->dm_dig_min; + PHYDM_DBG(dm, DBG_DIG, + "First disconnect:foce IGI to lower bound\n"); + } else { + PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n", + igi, fa_cnt); - if (cur_ig_value < max_DIG_cover_bond - 6) { - ccx_info->NHM_th[0] = 2 * (cur_ig_value - priv->pshare->rf_ft_var.dig_upcheck_initial_value); - p_dm_dig_table->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_0; - } else if (cur_ig_value <= DM_DIG_MAX_AP) { - ccx_info->NHM_th[0] = 2 * max_DIG_cover_bond; - p_dm_dig_table->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_1; - } - /* cur_ig_value > DM_DIG_MAX_AP, foolproof */ - else { - p_dm_dig_table->dig_go_up_check_level = DIG_GOUPCHECK_LEVEL_2; - ret = true; + igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step); + } } + /*@Check IGI by dyn-upper/lower bound */ + if (igi < *rx_gain_min) + igi = *rx_gain_min; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): *****Set NHM settings*****\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): DIG_GoUpCheck_level = %d\n", - p_dm_dig_table->dig_go_up_check_level)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("phydm_dig_go_up_check(): NHM_th = 0x%x, 0x%x, 0x%x\n", - ccx_info->NHM_th[0], ccx_info->NHM_th[1], ccx_info->NHM_th[2])); + if (igi > *rx_gain_max) + igi = *rx_gain_max; - ccx_info->nhm_inexclude_cca = NHM_EXCLUDE_CCA; - ccx_info->nhm_inexclude_txon = NHM_EXCLUDE_TXON; - ccx_info->NHM_period = 0xC350; + PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n", + fa_cnt, cur_igi, igi); - phydm_nhm_setting(p_dm_odm, SET_NHM_SETTING); - phydm_nhm_trigger(p_dm_odm); -#endif - - return ret; + return igi; } -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -/* <20130108, Kordan> E.g., With LNA used, we make the Rx power smaller to have a better EVM. (Asked by Willis) */ -void -odm_rfe_control( - struct PHY_DM_STRUCT *p_dm_odm, - u64 rssi_val -) +/*@callback function triggered by SW timer*/ +void phydm_tdma_dig_cbk(void *dm_void) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - static u8 trsw_high_pwr = 0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> odm_rfe_control, RSSI = %d, trsw_high_pwr = 0x%X, p_dm_odm->rfe_type = %d\n", - rssi_val, trsw_high_pwr, p_dm_odm->rfe_type)); +#if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; - if (p_dm_odm->rfe_type == 3) { - - p_dm_odm->RSSI_TRSW = rssi_val; - - if (p_dm_odm->RSSI_TRSW >= p_dm_odm->RSSI_TRSW_H) { - trsw_high_pwr = 1; /* Switch to */ - odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(1) | BIT0, 0x1); /* Set ANTSW=1/ANTSWB=0 for SW control */ - odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(9) | BIT8, 0x3); /* Set ANTSW=1/ANTSWB=0 for SW control */ + if (phydm_dig_abort(dm) || (dm->original_dig_restore)) + return; + /*@ + *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n"); + * dig_t->tdma_dig_state); + *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n", + * dig_t->cur_ig_value_tdma, + * dig_t->low_ig_value); + */ + phydm_tdma_fa_cnt_chk(dm); + + /*@prevent dumb*/ + if (dm->tdma_dig_state_number < 2) + dm->tdma_dig_state_number = 2; + + /*@update state*/ + dig_t->tdma_dig_cnt++; + dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number; + + /*@ + *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n", + * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt); + */ + + if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) + odm_write_dig(dm, dig_t->low_ig_value); + else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE) + odm_write_dig(dm, dig_t->cur_ig_value_tdma); + + odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms); +#endif +} - } else if (p_dm_odm->RSSI_TRSW <= p_dm_odm->RSSI_TRSW_L) { - trsw_high_pwr = 0; /* Switched back */ - odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(1) | BIT0, 0x1); /* Set ANTSW=1/ANTSWB=0 for SW control */ - odm_set_bb_reg(p_dm_odm, REG_ANTSEL_SW_JAGUAR, BIT(9) | BIT8, 0x0); /* Set ANTSW=1/ANTSWB=0 for SW control */ +/*@============================================================*/ +/*@FASLE ALARM CHECK*/ +/*@============================================================*/ +void phydm_tdma_fa_cnt_chk(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; + struct phydm_fa_acc_struct *fa_t_acc, *fa_t_acc_low; + struct phydm_dig_struct *dig_t = NULL; + boolean rssi_dump_en = false; + u32 timestamp = 0; + u8 states_per_block = 0; + u8 cur_tdma_dig_state = 0; + u32 start_th = 0; + u8 state_diff = 0; + u32 tdma_dig_block_period_ms = 0; + u32 tdma_dig_block_cnt_thd = 0; + u32 timestamp_diff = 0; + + if (!(dm->support_ic_type & + (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B))) { + PHYDM_DBG(dm, DBG_DIG, "Not 98F/22C/14B\n"); + return; + } + fa_t_acc = &dm->false_alm_cnt_acc; + fa_t_acc_low = &dm->false_alm_cnt_acc_low; + dig_t = &dm->dm_dig_table; + states_per_block = dm->tdma_dig_state_number; + + /*@calculate duration of a tdma block*/ + tdma_dig_block_period_ms = dm->tdma_dig_timer_ms * states_per_block; + + /*@ + *caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms, + *or FA will be fewer. + */ + tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms; + + /*@tdma_dig_state == 0, collect H-state FA, else, collect L-state FA*/ + if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) + cur_tdma_dig_state = TDMA_DIG_LOW_STATE; + else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE) + cur_tdma_dig_state = TDMA_DIG_HIGH_STATE; + /*@ + *PHYDM_DBG(dm, DBG_DIG, "in state %d, dig count %d\n", + * cur_tdma_dig_state, dig_t->tdma_dig_cnt); + */ + if (cur_tdma_dig_state == 0) { + /*@L-state indicates next block*/ + dig_t->tdma_dig_block_cnt++; + + /*@1sec dump check*/ + if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd) + rssi_dump_en = true; + + /*@ + *PHYDM_DBG(dm, DBG_DIG,"[L-state] tdma_dig_block_cnt=%d\n", + * dig_t->tdma_dig_block_cnt); + */ + + /*@collect FA till this block end*/ + phydm_false_alarm_counter_statistics(dm); + phydm_fa_cnt_acc(dm, rssi_dump_en, cur_tdma_dig_state); + /*@1s L-FA collect end*/ + + /*@1sec dump reached*/ + if (rssi_dump_en) { + /*@L-DIG*/ + phydm_noisy_detection(dm); + #ifdef PHYDM_SUPPORT_CCKPD + phydm_cck_pd_th(dm); + #endif + PHYDM_DBG(dm, DBG_DIG, "run tdma L-state dig ====>\n"); + phydm_tdma_low_dig(dm); + PHYDM_DBG(dm, DBG_DIG, "\n\n"); + } + } else if (cur_tdma_dig_state == 1) { + /*@1sec dump check*/ + if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd) + rssi_dump_en = true; + + /*@ + *PHYDM_DBG(dm, DBG_DIG,"[H-state] tdma_dig_block_cnt=%d\n", + * dig_t->tdma_dig_block_cnt); + */ + + /*@collect FA till this block end*/ + phydm_false_alarm_counter_statistics(dm); + phydm_fa_cnt_acc(dm, rssi_dump_en, cur_tdma_dig_state); + /*@1s H-FA collect end*/ + + /*@1sec dump reached*/ + state_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state; + if (rssi_dump_en && (state_diff == 1)) { + /*@H-DIG*/ + phydm_noisy_detection(dm); + #ifdef PHYDM_SUPPORT_CCKPD + phydm_cck_pd_th(dm); + #endif + PHYDM_DBG(dm, DBG_DIG, "run tdma H-state dig ====>\n"); + phydm_tdma_high_dig(dm); + PHYDM_DBG(dm, DBG_DIG, "\n\n"); + PHYDM_DBG(dm, DBG_DIG, "1 sec reached, is_linked=%d\n", + dm->is_linked); + PHYDM_DBG(dm, DBG_DIG, "1 sec L-CCA=%d, L-FA=%d\n", + fa_t_acc_low->cnt_cca_all_1sec, + fa_t_acc_low->cnt_all_1sec); + PHYDM_DBG(dm, DBG_DIG, "1 sec H-CCA=%d, H-FA=%d\n", + fa_t_acc->cnt_cca_all_1sec, + fa_t_acc->cnt_all_1sec); + PHYDM_DBG(dm, DBG_DIG, + "1 sec TOTAL-CCA=%d, TOTAL-FA=%d\n\n", + fa_t_acc->cnt_cca_all + + fa_t_acc_low->cnt_cca_all, + fa_t_acc->cnt_all + fa_t_acc_low->cnt_all); + + /*@Reset AccFalseAlarmCounterStatistics */ + phydm_false_alarm_counter_acc_reset(dm); + dig_t->tdma_dig_block_cnt = 0; } } - - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(p_dm_odm->RSSI_TRSW_H, p_dm_odm->RSSI_TRSW_L) = (%d, %d)\n", p_dm_odm->RSSI_TRSW_H, p_dm_odm->RSSI_TRSW_L)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(rssi_val, rssi_val, p_dm_odm->RSSI_TRSW_iso) = (%d, %d, %d)\n", - rssi_val, p_dm_odm->RSSI_TRSW_iso, p_dm_odm->RSSI_TRSW)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("<=== odm_rfe_control, RSSI = %d, trsw_high_pwr = 0x%X\n", rssi_val, trsw_high_pwr)); + /*@Reset FalseAlarmCounterStatistics */ + phydm_false_alarm_counter_reset(dm); } -void -odm_mpt_dig_work_item_callback( - void *p_context -) +void phydm_tdma_low_dig(void *dm_void) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc_low; +#ifdef CFG_DIG_DAMPING_CHK + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; +#endif + boolean first_connect, first_disconnect; + u8 igi = dig_t->cur_ig_value; + u8 new_igi = 0x20; + u8 tdma_l_igi = dig_t->low_ig_value; + u8 tdma_l_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE]; + u8 tdma_l_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE]; + u32 fa_cnt = falm_cnt->cnt_all; + boolean dfs_mode_en = false, is_performance = true; + u8 rssi_min = dm->rssi_min; + u8 igi_upper_rssi_min = 0; + u8 offset = 15; + + if (!(dm->original_dig_restore)) { + if (tdma_l_igi == 0) + tdma_l_igi = igi; + + fa_cnt = falm_cnt_acc->cnt_all_1sec; + } + + if (phydm_dig_abort(dm)) { + dig_t->low_ig_value = phydm_get_igi(dm, BB_PATH_A); + return; + } - ODM_MPT_DIG(p_dm_odm); -} + /*@Mode Decision*/ + dfs_mode_en = false; + is_performance = true; -void -odm_mpt_dig_callback( - struct timer_list *p_timer -) -{ - struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + /* @Abs Boundary Decision*/ + dig_t->dm_dig_max = DIG_MAX_COVERAGR; //0x26 + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; //0x20 + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; //0x22 + if (dfs_mode_en) { + if (*dm->band_width == CHANNEL_WIDTH_20) + dig_t->dm_dig_min = DIG_MIN_DFS + 2; + else + dig_t->dm_dig_min = DIG_MIN_DFS; -#if DEV_BUS_TYPE == RT_PCI_INTERFACE -#if USE_WORKITEM - odm_schedule_work_item(&p_dm_odm->mpt_dig_workitem); -#else - ODM_MPT_DIG(p_dm_odm); -#endif -#else - odm_schedule_work_item(&p_dm_odm->mpt_dig_workitem); -#endif + } else { + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)) + dig_t->dm_dig_min = 0x1c; + else if (dm->support_ic_type & ODM_RTL8197F) + dig_t->dm_dig_min = 0x1e; /*@For HW setting*/ + } -} + PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n", + dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min); -#endif + /* @Dyn Boundary by RSSI*/ + if (!dm->is_linked) { + /*@if no link, always stay at lower bound*/ + tdma_l_dym_max = 0x26; + tdma_l_dym_min = dig_t->dm_dig_min; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -void -odm_mpt_dig_callback( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#if USE_WORKITEM - odm_schedule_work_item(&p_dm_odm->mpt_dig_workitem); -#else - ODM_MPT_DIG(p_dm_odm); -#endif -} + PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n", + tdma_l_dym_max, tdma_l_dym_min); + } else { + PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", + dm->rssi_min, offset); + + /* @DIG lower bound in L-state*/ + tdma_l_dym_min = dig_t->dm_dig_min; + +#ifdef CFG_DIG_DAMPING_CHK + /*@Limit Dyn min by damping*/ + if (dig_t->dig_dl_en && + dig_rc->damping_limit_en && + tdma_l_dym_min < dig_rc->damping_limit_val) { + PHYDM_DBG(dm, DBG_DIG, + "[Limit by Damping] dyn_min=0x%x -> 0x%x\n", + tdma_l_dym_min, dig_rc->damping_limit_val); + + tdma_l_dym_min = dig_rc->damping_limit_val; + } #endif -#if (DM_ODM_SUPPORT_TYPE != ODM_CE) -void -odm_mpt_write_dig( - void *p_dm_void, - u8 cur_ig_value -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - - odm_write_1byte(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), cur_ig_value); - -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - /* Set IGI value of CCK for new CCK AGC */ - if (p_dm_odm->cck_new_agc) { - if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) - odm_set_bb_reg(p_dm_odm, 0xa0c, 0x00003f00, (cur_ig_value >> 1)); + /*@DIG upper bound in L-state*/ + igi_upper_rssi_min = rssi_min + offset; + if (igi_upper_rssi_min > dig_t->dm_dig_max) + tdma_l_dym_max = dig_t->dm_dig_max; + else if (igi_upper_rssi_min < dig_t->dm_dig_min) + tdma_l_dym_max = dig_t->dm_dig_min; + else + tdma_l_dym_max = igi_upper_rssi_min; + + /* @1 Force Lower Bound for AntDiv */ + /*@ + *if (!dm->is_one_entry_only && + *(dm->support_ability & ODM_BB_ANT_DIV) && + *(dm->ant_div_type == CG_TRX_HW_ANTDIV || + *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) { + *if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min) + * dig_t->rx_gain_range_min = dig_t->dig_max_of_min; + *else + * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max; + * + *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n", + * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max); + *} + */ + + PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n", + tdma_l_dym_max, tdma_l_dym_min); + } + + /*@Abnormal Case Check*/ + /*@Abnormal lower bound case*/ + if (tdma_l_dym_min > tdma_l_dym_max) + tdma_l_dym_min = tdma_l_dym_max; + + PHYDM_DBG(dm, DBG_DIG, + "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n", + tdma_l_dym_max, tdma_l_dym_min); + + /*@False Alarm Threshold Decision*/ + phydm_fa_threshold_check(dm, dfs_mode_en); + + /*@Adjust Initial Gain by False Alarm*/ + /*Select new IGI by FA */ + if (!(dm->original_dig_restore)) { + tdma_l_igi = get_new_igi_bound(dm, tdma_l_igi, fa_cnt, + &tdma_l_dym_max, + &tdma_l_dym_min, + dfs_mode_en); + } else { + new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en); } + /*Update status*/ + if (!(dm->original_dig_restore)) { + dig_t->low_ig_value = tdma_l_igi; + dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_l_dym_min; + dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = tdma_l_dym_max; +#if 0 + /*odm_write_dig(dm, tdma_l_igi);*/ #endif + } else { + odm_write_dig(dm, new_igi); + } - if (p_dm_odm->rf_type > ODM_1T1R) - odm_write_1byte(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), cur_ig_value); + dig_t->is_media_connect = dm->is_linked; +} - if ((p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) && (p_dm_odm->rf_type > ODM_2T2R)) { - odm_write_1byte(p_dm_odm, ODM_REG(IGI_C, p_dm_odm), cur_ig_value); - odm_write_1byte(p_dm_odm, ODM_REG(IGI_D, p_dm_odm), cur_ig_value); +void phydm_tdma_high_dig(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc; +#ifdef CFG_DIG_DAMPING_CHK + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; +#endif + boolean first_connect, first_disconnect; + u8 igi = dig_t->cur_ig_value; + u8 new_igi = 0x20; + u8 tdma_h_igi = dig_t->cur_ig_value_tdma; + u8 tdma_h_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE]; + u8 tdma_h_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE]; + u32 fa_cnt = falm_cnt->cnt_all; + boolean dfs_mode_en = false, is_performance = true; + u8 rssi_min = dm->rssi_min; + u8 igi_upper_rssi_min = 0; + u8 offset = 15; + + if (!(dm->original_dig_restore)) { + if (tdma_h_igi == 0) + tdma_h_igi = igi; + + fa_cnt = falm_cnt_acc->cnt_all_1sec; + } + + if (phydm_dig_abort(dm)) { + dig_t->cur_ig_value_tdma = phydm_get_igi(dm, BB_PATH_A); + return; } - p_dm_dig_table->cur_ig_value = cur_ig_value; + /*@Mode Decision*/ + dfs_mode_en = false; + is_performance = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cur_ig_value = 0x%x\n", cur_ig_value)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("p_dm_odm->rf_type = 0x%x\n", p_dm_odm->rf_type)); -} + /*@Abs Boundary Decision*/ + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; // 0x2a -void -ODM_MPT_DIG( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); - u8 current_igi = p_dm_dig_table->cur_ig_value; - u8 dig_upper = 0x40, dig_lower = 0x20; - u32 rx_ok_cal; - u32 rx_pwdb_ave_final; - u8 IGI_A = 0x20, IGI_B = 0x20; + if (!dm->is_linked) { + dig_t->dm_dig_max = DIG_MAX_COVERAGR; + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; // 0x20 + } else if (dfs_mode_en) { + if (*dm->band_width == CHANNEL_WIDTH_20) + dig_t->dm_dig_min = DIG_MIN_DFS + 2; + else + dig_t->dm_dig_min = DIG_MIN_DFS; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + } else { + if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) { + /*service > 2 devices*/ + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + #if (DIG_HW == 1) + dig_t->dig_max_of_min = DIG_MIN_COVERAGE; + #else + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; + #endif + } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) { + /*service 1 devices*/ + dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE; + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE; + } -#if ODM_FIX_2G_DIG - IGI_A = 0x22; - IGI_B = 0x24; -#endif + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)) + dig_t->dm_dig_min = 0x1c; + else if (dm->support_ic_type & ODM_RTL8197F) + dig_t->dm_dig_min = 0x1e; /*@For HW setting*/ + else + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; + } + PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n", + dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min); -#else - if (!(p_dm_odm->priv->pshare->rf_ft_var.mp_specific && p_dm_odm->priv->pshare->mp_dig_on)) - return; + /*@Dyn Boundary by RSSI*/ + if (!dm->is_linked) { + /*@if no link, always stay at lower bound*/ + tdma_h_dym_max = dig_t->dig_max_of_min; + tdma_h_dym_min = dig_t->dm_dig_min; + + PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n", + tdma_h_dym_max, tdma_h_dym_min); + } else { + PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", + dm->rssi_min, offset); - if (*p_dm_odm->p_band_type == ODM_BAND_5G) - dig_lower = 0x22; + /* @DIG lower bound in H-state*/ + if (rssi_min < dig_t->dm_dig_min) + tdma_h_dym_min = dig_t->dm_dig_min; + else + tdma_h_dym_min = rssi_min; // turbo not considered yet + +#ifdef CFG_DIG_DAMPING_CHK + /*@Limit Dyn min by damping*/ + if (dig_t->dig_dl_en && + dig_rc->damping_limit_en && + tdma_h_dym_min < dig_rc->damping_limit_val) { + PHYDM_DBG(dm, DBG_DIG, + "[Limit by Damping] dyn_min=0x%x -> 0x%x\n", + tdma_h_dym_min, dig_rc->damping_limit_val); + + tdma_h_dym_min = dig_rc->damping_limit_val; + } #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> ODM_MPT_DIG, p_band_type = %d\n", *p_dm_odm->p_band_type)); + /*@DIG upper bound in H-state*/ + igi_upper_rssi_min = rssi_min + offset; + if (igi_upper_rssi_min > dig_t->dm_dig_max) + tdma_h_dym_max = dig_t->dm_dig_max; + else + tdma_h_dym_max = igi_upper_rssi_min; + + /* @1 Force Lower Bound for AntDiv */ + /*@ + *if (!dm->is_one_entry_only && + *(dm->support_ability & ODM_BB_ANT_DIV) && + *(dm->ant_div_type == CG_TRX_HW_ANTDIV || + *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) { + * if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min) + * dig_t->rx_gain_range_min = dig_t->dig_max_of_min; + * else + * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max; + */ + /*@ + *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n", + * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max); + *} + */ + PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n", + tdma_h_dym_max, tdma_h_dym_min); + } + + /*@Abnormal Case Check*/ + /*@Abnormal low higher bound case*/ + if (tdma_h_dym_max < dig_t->dm_dig_min) + tdma_h_dym_max = dig_t->dm_dig_min; + /*@Abnormal lower bound case*/ + if (tdma_h_dym_min > tdma_h_dym_max) + tdma_h_dym_min = tdma_h_dym_max; + + PHYDM_DBG(dm, DBG_DIG, "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n", + tdma_h_dym_max, tdma_h_dym_min); + + /*@False Alarm Threshold Decision*/ + phydm_fa_threshold_check(dm, dfs_mode_en); + + /*@Adjust Initial Gain by False Alarm*/ + /*Select new IGI by FA */ + if (!(dm->original_dig_restore)) { + tdma_h_igi = get_new_igi_bound(dm, tdma_h_igi, fa_cnt, + &tdma_h_dym_max, + &tdma_h_dym_min, + dfs_mode_en); + } else { + new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en); + } -#if (ODM_FIX_2G_DIG || (DM_ODM_SUPPORT_TYPE & ODM_AP)) - if (*p_dm_odm->p_band_type == ODM_BAND_5G || (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) /* for 5G or 8814 */ -#else - if (1) /* for both 2G/5G */ + /*Update status*/ + if (!(dm->original_dig_restore)) { + dig_t->cur_ig_value_tdma = tdma_h_igi; + dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_h_dym_min; + dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = tdma_h_dym_max; +#if 0 + /*odm_write_dig(dm, tdma_h_igi);*/ #endif - { - odm_false_alarm_counter_statistics(p_dm_odm); + } else { + odm_write_dig(dm, new_igi); + } - rx_ok_cal = p_dm_odm->phy_dbg_info.num_qry_phy_status_cck + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm; - rx_pwdb_ave_final = (rx_ok_cal != 0) ? p_dm_odm->rx_pwdb_ave / rx_ok_cal : 0; + dig_t->is_media_connect = dm->is_linked; +} - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; - p_dm_odm->rx_pwdb_ave = 0; - p_dm_odm->MPDIG_2G = false; +void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en, + u8 cur_tdma_dig_state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt = NULL; + struct phydm_fa_acc_struct *falm_cnt_acc = NULL; + struct phydm_dig_struct *dig_t = NULL; + u8 factor_num = 0; + u8 factor_denum = 1; + u8 total_state_number; + + dig_t = &dm->dm_dig_table; + falm_cnt = &dm->false_alm_cnt; +#ifdef IS_USE_NEW_TDMA + if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) + falm_cnt_acc = &dm->false_alm_cnt_acc_low; + else if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) +#endif + falm_cnt_acc = &dm->false_alm_cnt_acc; + /*@ + *PHYDM_DBG(dm, DBG_DIG, + * "[%s] ==> dig_state=%d, one_sec=%d\n", __func__, + * cur_tdma_dig_state, rssi_dump_en); + */ + falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail; + falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal; + falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail; + falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail; + falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail; + falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail; + falm_cnt_acc->cnt_all += falm_cnt->cnt_all; + falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync; + falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail; + falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca; + falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca; + falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all; + falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error; + falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok; + falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error; + falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok; + falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error; + falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok; + falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error; + falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok; + falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all; + falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all; + + /*@ + *PHYDM_DBG(dm, DBG_DIG, + * "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + * falm_cnt->cnt_cck_cca, + * falm_cnt->cnt_ofdm_cca, + * falm_cnt->cnt_cca_all); + *PHYDM_DBG(dm, DBG_DIG, + * "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + * falm_cnt->cnt_cck_fail, + * falm_cnt->cnt_ofdm_fail, + * falm_cnt->cnt_all); + */ + if (rssi_dump_en == 1) { + total_state_number = dm->tdma_dig_state_number; + + if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) { + factor_num = total_state_number; + factor_denum = total_state_number - 1; + } else if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) { + factor_num = total_state_number; + factor_denum = 1; + } -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_dm_odm->times_2g = 0; -#endif + falm_cnt_acc->cnt_all_1sec = + falm_cnt_acc->cnt_all * factor_num / factor_denum; + falm_cnt_acc->cnt_cca_all_1sec = + falm_cnt_acc->cnt_cca_all * factor_num / factor_denum; + falm_cnt_acc->cnt_cck_fail_1sec = + falm_cnt_acc->cnt_cck_fail * factor_num / factor_denum; + /*@ + *PHYDM_DBG(dm, DBG_DIG, + * "[ACC CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + * falm_cnt_acc->cnt_cck_cca, + * falm_cnt_acc->cnt_ofdm_cca, + * falm_cnt_acc->cnt_cca_all); + *PHYDM_DBG(dm, DBG_DIG, + * "[ACC FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n\n", + * falm_cnt_acc->cnt_cck_fail, + * falm_cnt_acc->cnt_ofdm_fail, + * falm_cnt_acc->cnt_all); + */ + } +} +#endif /*@#ifdef IS_USE_NEW_TDMA*/ +#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("RX OK = %d\n", rx_ok_cal)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("RSSI = %d\n", rx_pwdb_ave_final)); +void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + char help[] = "-h"; + char monitor[] = "-m"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0} {en} fa_th[0] fa_th[1] fa_th[2]\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {Damping Limit en}\n"); + } else if ((strcmp(input[1], monitor) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Read DIG fa_th[0:2]= {%d, %d, %d}\n", dig_t->fa_th[0], + dig_t->fa_th[1], dig_t->fa_th[2]); - if (rx_ok_cal >= 70 && rx_pwdb_ave_final <= 40) { - if (current_igi > 0x24) - odm_mpt_write_dig(p_dm_odm, 0x24); - } else { - if (p_false_alm_cnt->cnt_all > 1000) - current_igi = current_igi + 8; - else if (p_false_alm_cnt->cnt_all > 200) - current_igi = current_igi + 4; - else if (p_false_alm_cnt->cnt_all > 50) - current_igi = current_igi + 2; - else if (p_false_alm_cnt->cnt_all < 2) - current_igi = current_igi - 2; - - if (current_igi < dig_lower) - current_igi = dig_lower; - - if (current_igi > dig_upper) - current_igi = dig_upper; - - odm_mpt_write_dig(p_dm_odm, current_igi); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG = 0x%x, cnt_all = %d, cnt_ofdm_fail = %d, cnt_cck_fail = %d\n", - current_igi, p_false_alm_cnt->cnt_all, p_false_alm_cnt->cnt_ofdm_fail, p_false_alm_cnt->cnt_cck_fail)); - } } else { - if (p_dm_odm->MPDIG_2G == false) { - if ((p_dm_odm->support_platform & ODM_WIN) && !(p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> Fix IGI\n")); - odm_write_1byte(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), IGI_A); - odm_write_1byte(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), IGI_B); - p_dm_dig_table->cur_ig_value = IGI_B; - } else - odm_mpt_write_dig(p_dm_odm, IGI_A); + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + for (i = 1; i < 10; i++) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + + if (var1[0] == 0) { + if (var1[1] == 1) { + dig_t->is_dbg_fa_th = true; + dig_t->fa_th[0] = (u16)var1[2]; + dig_t->fa_th[1] = (u16)var1[3]; + dig_t->fa_th[2] = (u16)var1[4]; + + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Set DIG fa_th[0:2]= {%d, %d, %d}\n", + dig_t->fa_th[0], dig_t->fa_th[1], + dig_t->fa_th[2]); + } else { + dig_t->is_dbg_fa_th = false; + } } - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_dm_odm->times_2g++; - - if (p_dm_odm->times_2g == 3) -#endif - { - p_dm_odm->MPDIG_2G = true; + #ifdef CFG_DIG_DAMPING_CHK + else if (var1[0] == 1) { + dig_t->dig_dl_en = (u8)var1[1]; + /*@*/ } + #endif } + *_used = used; + *_out_len = out_len; +} -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - odm_rfe_control(p_dm_odm, rx_pwdb_ave_final); -#endif +#ifdef CONFIG_MCC_DM +#if (RTL8822B_SUPPORT) +void phydm_mcc_igi_clr(void *dm_void, u8 clr_port) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + mcc_dm->mcc_rssi[clr_port] = 0xff; + mcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */ + mcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */ +} + +void phydm_mcc_igi_chk(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; - odm_set_timer(p_dm_odm, &p_dm_odm->mpt_dig_timer, 700); + if (mcc_dm->mcc_dm_val[0][0] == 0xff && + mcc_dm->mcc_dm_val[0][1] == 0xff) { + mcc_dm->mcc_dm_reg[0] = 0xffff; + mcc_dm->mcc_reg_id[0] = 0xff; + } + if (mcc_dm->mcc_dm_val[1][0] == 0xff && + mcc_dm->mcc_dm_val[1][1] == 0xff) { + mcc_dm->mcc_dm_reg[1] = 0xffff; + mcc_dm->mcc_reg_id[1] = 0xff; + } } -#endif + +void phydm_mcc_igi_cal(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 shift = 0; + u8 igi_val0, igi_val1; + if (mcc_dm->mcc_rssi[0] == 0xff) + phydm_mcc_igi_clr(dm, 0); + if (mcc_dm->mcc_rssi[1] == 0xff) + phydm_mcc_igi_clr(dm, 1); + phydm_mcc_igi_chk(dm); + igi_val0 = mcc_dm->mcc_rssi[0] - shift; + igi_val1 = mcc_dm->mcc_rssi[1] - shift; + phydm_fill_mcccmd(dm, 0, 0xc50, igi_val0, igi_val1); + phydm_fill_mcccmd(dm, 1, 0xe50, igi_val0, igi_val1); + PHYDM_DBG(dm, DBG_COMP_MCC, "RSSI_min: %d %d, MCC_igi: %d %d\n", + mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1], + mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]); +} +#endif /*#if (RTL8822B_SUPPORT)*/ +#endif /*#ifdef CONFIG_MCC_DM*/ diff --git a/hal/phydm/phydm_dig.h b/hal/phydm/phydm_dig.h index 3594ce9..b9a2d08 100644 --- a/hal/phydm/phydm_dig.h +++ b/hal/phydm/phydm_dig.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,103 +8,142 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -#ifndef __PHYDMDIG_H__ -#define __PHYDMDIG_H__ +#ifndef __PHYDMDIG_H__ +#define __PHYDMDIG_H__ -#define DIG_VERSION "1.32" /* 2016.09.02 YuChen. add CCK PD for 8197F*/ -#define DIG_HW 0 +#define DIG_VERSION "2.3" -/* Pause DIG & CCKPD */ -#define DM_DIG_MAX_PAUSE_TYPE 0x7 +#define DIG_HW 0 +#define DIG_LIMIT_PERIOD 60 /*@60 sec*/ -enum dig_goupcheck_level { +/*@--------------------Define ---------------------------------------*/ - DIG_GOUPCHECK_LEVEL_0, - DIG_GOUPCHECK_LEVEL_1, - DIG_GOUPCHECK_LEVEL_2 +/*@=== [DIG Boundary] ========================================*/ +/*@DIG coverage mode*/ +#define DIG_MAX_COVERAGR 0x26 +#define DIG_MIN_COVERAGE 0x1c +#define DIG_MAX_OF_MIN_COVERAGE 0x22 -}; +/*@[DIG Balance mode]*/ +#if (DIG_HW == 1) +#define DIG_MAX_BALANCE_MODE 0x32 +#else +#define DIG_MAX_BALANCE_MODE 0x3e +#endif +#define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a + +/*@[DIG Performance mode]*/ +#define DIG_MAX_PERFORMANCE_MODE 0x5a +#define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*@[WLANBB-871]*/ +#define DIG_MIN_PERFORMANCE 0x20 -struct _dynamic_initial_gain_threshold_ { - boolean is_stop_dig; /* for debug */ - boolean is_ignore_dig; - boolean is_psd_in_progress; +/*@DIG DFS function*/ +#define DIG_MAX_DFS 0x28 +#define DIG_MIN_DFS 0x20 - u8 dig_enable_flag; - u8 dig_ext_port_stage; +/*@DIG LPS function*/ +#define DIG_MAX_LPS 0x3e +#define DIG_MIN_LPS 0x20 - int rssi_low_thresh; - int rssi_high_thresh; +#ifdef PHYDM_TDMA_DIG_SUPPORT +#define DIG_NUM_OF_TDMA_STATES 2 /*@L, H state*/ +#endif - u32 fa_low_thresh; - u32 fa_high_thresh; +/*@=== [DIG FA Threshold] ======================================*/ - u8 cur_sta_connect_state; - u8 pre_sta_connect_state; - u8 cur_multi_sta_connect_state; +/*Normal*/ +#define DM_DIG_FA_TH0 500 +#define DM_DIG_FA_TH1 750 - u8 pre_ig_value; - u8 cur_ig_value; - u8 backup_ig_value; /* MP DIG */ - u8 bt30_cur_igi; - u8 igi_backup; +/*@LPS*/ +#define DM_DIG_FA_TH0_LPS 4 /* @-> 4 lps */ +#define DM_DIG_FA_TH1_LPS 15 /* @-> 15 lps */ +#define DM_DIG_FA_TH2_LPS 30 /* @-> 30 lps */ - s8 backoff_val; - s8 backoff_val_range_max; - s8 backoff_val_range_min; - u8 rx_gain_range_max; - u8 rx_gain_range_min; - u8 rssi_val_min; - - u8 pre_cck_cca_thres; - u8 cur_cck_cca_thres; - u8 pre_cck_pd_state; - u8 cur_cck_pd_state; - u8 cck_pd_backup; - u8 pause_cckpd_level; - u8 pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1]; - - u8 large_fa_hit; - u8 large_fa_timeout; /*if (large_fa_hit), monitor "large_fa_timeout" sec, if timeout, large_fa_hit=0*/ - u8 forbidden_igi; - u32 recover_cnt; - - u8 dig_dynamic_min_0; - u8 dig_dynamic_min_1; - boolean is_media_connect_0; - boolean is_media_connect_1; +#define RSSI_OFFSET_DIG_LPS 5 +#define DIG_RECORD_NUM 4 - u32 ant_div_rssi_max; - u32 RSSI_max; +/*@--------------------Enum-----------------------------------*/ +enum dig_goupcheck_level { + DIG_GOUPCHECK_LEVEL_0, + DIG_GOUPCHECK_LEVEL_1, + DIG_GOUPCHECK_LEVEL_2 +}; - u8 *is_p2p_in_process; +enum phydm_dig_mode { + PHYDM_DIG_PERFORAMNCE_MODE = 0, + PHYDM_DIG_COVERAGE_MODE = 1, +}; - u8 pause_dig_level; - u8 pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1]; +#ifdef IS_USE_NEW_TDMA +enum tdma_dig_timer { + INIT_TDMA_DIG_TIMMER, + CANCEL_TDMA_DIG_TIMMER, + RELEASE_TDMA_DIG_TIMMER +}; - u32 cck_fa_ma; - enum dig_goupcheck_level dig_go_up_check_level; - u8 aaa_default; +enum tdma_dig_state { + TDMA_DIG_LOW_STATE = 0, + TDMA_DIG_HIGH_STATE = 1, + NORMAL_DIG = 2 +}; +#endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - boolean is_tp_target; - boolean is_noise_est; - u32 tp_train_th_min; - u8 igi_offset_a; - u8 igi_offset_b; +/*@--------------------Define Struct-----------------------------------*/ +#ifdef CFG_DIG_DAMPING_CHK +struct phydm_dig_recorder_strcut { + u8 igi_bitmap; /*@Don't add any new parameter before this*/ + u8 igi_history[DIG_RECORD_NUM]; + u32 fa_history[DIG_RECORD_NUM]; + u8 damping_limit_en; + u8 damping_limit_val; /*@Limit IGI_dyn_min*/ + u32 limit_time; + u8 limit_rssi; +}; #endif -#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1) +struct phydm_mcc_dig { + u8 mcc_rssi_A; + u8 mcc_rssi_B; +}; + +struct phydm_dig_struct { +#ifdef CFG_DIG_DAMPING_CHK + struct phydm_dig_recorder_strcut dig_recorder_t; + u8 dig_dl_en; /*@damping limit function enable*/ +#endif + boolean is_dbg_fa_th; + u8 cur_ig_value; + u8 rvrt_val; + u8 igi_backup; + u8 rx_gain_range_max; /*@dig_dynamic_max*/ + u8 rx_gain_range_min; /*@dig_dynamic_min*/ + u8 dm_dig_max; /*@Absolutly upper bound*/ + u8 dm_dig_min; /*@Absolutly lower bound*/ + u8 dig_max_of_min; /*@Absolutly max of min*/ + boolean is_media_connect; + u32 ant_div_rssi_max; + u8 *is_p2p_in_process; + enum dig_goupcheck_level go_up_chk_lv; + u16 fa_th[3]; +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT) u8 rf_gain_idx; u8 agc_table_idx; u8 big_jump_lmt[16]; @@ -113,19 +152,41 @@ struct _dynamic_initial_gain_threshold_ { u8 big_jump_step2:2; u8 big_jump_step3:2; #endif - -#if (DIG_HW == 1) - u8 pre_rssi_min; + u8 upcheck_init_val; + u8 lv0_ratio_reciprocal; + u8 lv1_ratio_reciprocal; +#ifdef PHYDM_TDMA_DIG_SUPPORT + u8 cur_ig_value_tdma; + u8 low_ig_value; + u8 tdma_dig_state; /*@To distinguish which state is now.(L-sate or H-state)*/ + u8 tdma_dig_cnt; /*@for phydm_tdma_dig_timer_check use*/ + u8 pre_tdma_dig_cnt; + u8 sec_factor; + u32 cur_timestamp; + u32 pre_timestamp; + u32 fa_start_timestamp; + u32 fa_end_timestamp; + u32 fa_acc_1sec_timestamp; +#ifdef IS_USE_NEW_TDMA + u8 tdma_dig_block_cnt;/*@for 1 second dump indicator use*/ + /*@dynamic upper bound for L/H state*/ + u8 tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES]; + /*@dynamic lower bound for L/H state*/ + u8 tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES]; + /*To distinguish current state(L-sate or H-state)*/ +#endif #endif }; -struct _FALSE_ALARM_STATISTICS { +struct phydm_fa_struct { u32 cnt_parity_fail; u32 cnt_rate_illegal; u32 cnt_crc8_fail; + u32 cnt_crc8_fail_vht; u32 cnt_mcs_fail; + u32 cnt_mcs_fail_vht; u32 cnt_ofdm_fail; - u32 cnt_ofdm_fail_pre; /* For RTL8881A */ + u32 cnt_ofdm_fail_pre; /* @For RTL8881A */ u32 cnt_cck_fail; u32 cnt_all; u32 cnt_all_pre; @@ -134,257 +195,120 @@ struct _FALSE_ALARM_STATISTICS { u32 cnt_ofdm_cca; u32 cnt_cck_cca; u32 cnt_cca_all; - u32 cnt_bw_usc; /* Gary */ - u32 cnt_bw_lsc; /* Gary */ + u32 cnt_bw_usc; + u32 cnt_bw_lsc; u32 cnt_cck_crc32_error; u32 cnt_cck_crc32_ok; u32 cnt_ofdm_crc32_error; u32 cnt_ofdm_crc32_ok; u32 cnt_ht_crc32_error; u32 cnt_ht_crc32_ok; + u32 cnt_ht_crc32_error_agg; + u32 cnt_ht_crc32_ok_agg; u32 cnt_vht_crc32_error; u32 cnt_vht_crc32_ok; u32 cnt_crc32_error_all; u32 cnt_crc32_ok_all; + u32 time_fa_all; boolean cck_block_enable; boolean ofdm_block_enable; u32 dbg_port0; boolean edcca_flag; }; -enum dm_dig_op_e { - DIG_TYPE_THRESH_HIGH = 0, - DIG_TYPE_THRESH_LOW = 1, - DIG_TYPE_BACKOFF = 2, - DIG_TYPE_RX_GAIN_MIN = 3, - DIG_TYPE_RX_GAIN_MAX = 4, - DIG_TYPE_ENABLE = 5, - DIG_TYPE_DISABLE = 6, - DIG_OP_TYPE_MAX +#ifdef PHYDM_TDMA_DIG_SUPPORT +struct phydm_fa_acc_struct { + u32 cnt_parity_fail; + u32 cnt_rate_illegal; + u32 cnt_crc8_fail; + u32 cnt_mcs_fail; + u32 cnt_ofdm_fail; + u32 cnt_ofdm_fail_pre; /*@For RTL8881A*/ + u32 cnt_cck_fail; + u32 cnt_all; + u32 cnt_all_pre; + u32 cnt_fast_fsync; + u32 cnt_sb_search_fail; + u32 cnt_ofdm_cca; + u32 cnt_cck_cca; + u32 cnt_cca_all; + u32 cnt_cck_crc32_error; + u32 cnt_cck_crc32_ok; + u32 cnt_ofdm_crc32_error; + u32 cnt_ofdm_crc32_ok; + u32 cnt_ht_crc32_error; + u32 cnt_ht_crc32_ok; + u32 cnt_vht_crc32_error; + u32 cnt_vht_crc32_ok; + u32 cnt_crc32_error_all; + u32 cnt_crc32_ok_all; + u32 cnt_all_1sec; + u32 cnt_cca_all_1sec; + u32 cnt_cck_fail_1sec; }; -/* -enum dm_cck_pdth_e -{ - CCK_PD_STAGE_LowRssi = 0, - CCK_PD_STAGE_HighRssi = 1, - CCK_PD_STAGE_MAX = 3, -}; +#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ -enum dm_dig_ext_port_alg_e -{ - DIG_EXT_PORT_STAGE_0 = 0, - DIG_EXT_PORT_STAGE_1 = 1, - DIG_EXT_PORT_STAGE_2 = 2, - DIG_EXT_PORT_STAGE_3 = 3, - DIG_EXT_PORT_STAGE_MAX = 4, -}; +/*@--------------------Function declaration-----------------------------*/ +void odm_write_dig(void *dm_void, u8 current_igi); -enum dm_dig_connect_e -{ - DIG_STA_DISCONNECT = 0, - DIG_STA_CONNECT = 1, - DIG_STA_BEFORE_CONNECT = 2, - dig_multi_sta_disconnect = 3, - dig_multi_sta_connect = 4, - DIG_CONNECT_MAX -}; +u8 phydm_get_igi(void *dm_void, enum bb_path path); +void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len); -#define DM_MultiSTA_InitGainChangeNotify(Event) {dm_dig_table.cur_multi_sta_connect_state = Event;} +void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type, + enum phydm_pause_level pause_level, u8 igi_value); -#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \ - DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_connect) +void phydm_dig_init(void *dm_void); -#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \ - DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_disconnect) -*/ +void phydm_dig(void *dm_void); -enum phydm_pause_type { - PHYDM_PAUSE = BIT(0), - PHYDM_RESUME = BIT(1) -}; +void phydm_dig_lps_32k(void *dm_void); -enum phydm_pause_level { - /* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */ - PHYDM_PAUSE_LEVEL_0 = 0, - PHYDM_PAUSE_LEVEL_1 = 1, - PHYDM_PAUSE_LEVEL_2 = 2, - PHYDM_PAUSE_LEVEL_3 = 3, - PHYDM_PAUSE_LEVEL_4 = 4, - PHYDM_PAUSE_LEVEL_5 = 5, - PHYDM_PAUSE_LEVEL_6 = 6, - PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */ -}; +void phydm_dig_by_rssi_lps(void *dm_void); -/*CCK PD*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #if (RTL8197F_SUPPORT == 1) - #define AAA_BASE p_dm_odm->priv->pshare->rf_ft_var.dbg_aaa_base /*4*/ - #define AAA_STEP p_dm_odm->priv->pshare->rf_ft_var.dbg_aaa_step /*2*/ - #endif -#endif +void phydm_false_alarm_counter_statistics(void *dm_void); -#define DM_DIG_THRESH_HIGH 40 -#define DM_DIG_THRESH_LOW 35 +#ifdef PHYDM_TDMA_DIG_SUPPORT +void phydm_set_tdma_dig_timer(void *dm_void); -#define DM_FALSEALARM_THRESH_LOW 400 -#define DM_FALSEALARM_THRESH_HIGH 1000 +void phydm_tdma_dig_timer_check(void *dm_void); -#define DM_DIG_MAX_NIC 0x3e -#define DM_DIG_MIN_NIC 0x20 -#define DM_DIG_MAX_OF_MIN_NIC 0x3e +void phydm_tdma_dig(void *dm_void); -#if (DIG_HW == 1) -#define DM_DIG_MAX_AP p_dm_odm->priv->pshare->rf_ft_var.dbg_dig_upper /* 0x3e */ -#define DM_DIG_MIN_AP ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) ? 0x1c : 0x20)/* 0x1c */ -#else -#define DM_DIG_MAX_AP 0x3e -#define DM_DIG_MIN_AP 0x20 -#endif -#define DM_DIG_MAX_OF_MIN 0x2A /* 0x32 */ -#define DM_DIG_MIN_AP_DFS 0x20 +void phydm_tdma_false_alarm_counter_check(void *dm_void); -#define DM_DIG_MAX_NIC_HP 0x46 -#define DM_DIG_MIN_NIC_HP 0x2e +void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void); -#define DM_DIG_MAX_AP_HP 0x42 -#define DM_DIG_MIN_AP_HP 0x30 +void phydm_false_alarm_counter_reset(void *dm_void); -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #define DM_DIG_MAX_AP_COVERAGR 0x26 -#if (DIG_HW == 1) - #define DM_DIG_MIN_AP_COVERAGE ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) ? 0x1c : 0x20) -#else - #define DM_DIG_MIN_AP_COVERAGE 0x1c -#endif - #define DM_DIG_MAX_OF_MIN_COVERAGE 0x22 +void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en); - #define dm_dig_tp_target_th0 500 - #define dm_dig_tp_target_th1 1000 - #define dm_dig_tp_training_period 10 -#endif +void phydm_false_alarm_counter_acc_reset(void *dm_void); -/* vivi 92c&92d has different definition, 20110504 - * this is for 92c */ -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - #define DM_DIG_FA_TH0 0x80/* 0x20 */ - #else - #define DM_DIG_FA_TH0 0x200/* 0x20 */ - #endif -#else - #define DM_DIG_FA_TH0 0x200/* 0x20 */ -#endif +#ifdef IS_USE_NEW_TDMA +void phydm_tdma_dig_timers(void *dm_void, u8 state); -#define DM_DIG_FA_TH1 0x300 -#define DM_DIG_FA_TH2 0x400 -/* this is for 92d */ -#define DM_DIG_FA_TH0_92D 0x100 -#define DM_DIG_FA_TH1_92D 0x400 -#define DM_DIG_FA_TH2_92D 0x600 - -#define DM_DIG_BACKOFF_MAX 12 -#define DM_DIG_BACKOFF_MIN -4 -#define DM_DIG_BACKOFF_DEFAULT 10 - -#define DM_DIG_FA_TH0_LPS 4 /* -> 4 in lps */ -#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */ -#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */ -#define RSSI_OFFSET_DIG 0x05 -#define LARGE_FA_TIMEOUT 60 - - -void -odm_change_dynamic_init_gain_thresh( - void *p_dm_void, - u32 dm_type, - u32 dm_value -); - -void -odm_write_dig( - void *p_dm_void, - u8 current_igi -); - -void -odm_pause_dig( - void *p_dm_void, - enum phydm_pause_type pause_type, - enum phydm_pause_level pause_level, - u8 igi_value -); - -void -odm_dig_init( - void *p_dm_void -); - -void -odm_DIG( - void *p_dm_void -); - -void -odm_dig_by_rssi_lps( - void *p_dm_void -); - -void -odm_false_alarm_counter_statistics( - void *p_dm_void -); - -void -odm_pause_cck_packet_detection( - void *p_dm_void, - enum phydm_pause_type pause_type, - enum phydm_pause_level pause_level, - u8 cck_pd_threshold -); - -void -odm_cck_packet_detection_thresh( - void *p_dm_void -); - -void -odm_write_cck_cca_thres( - void *p_dm_void, - u8 cur_cck_cca_thres -); - -boolean -phydm_dig_go_up_check( - void *p_dm_void -); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -odm_mpt_dig_callback( - struct timer_list *p_timer -); - -void -odm_mpt_dig_work_item_callback( - void *p_context -); +void phydm_tdma_dig_cbk(void *dm_void); -#endif +void phydm_tdma_fa_cnt_chk(void *dm_void); -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -void -odm_mpt_dig_callback( - void *p_dm_void -); -#endif +void phydm_tdma_low_dig(void *dm_void); + +void phydm_tdma_high_dig(void *dm_void); + +void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en, + u8 cur_tdma_dig_state); +#endif /*@#ifdef IS_USE_NEW_TDMA*/ +#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ + +void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel); + +void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); -#if (DM_ODM_SUPPORT_TYPE != ODM_CE) -void -ODM_MPT_DIG( - void *p_dm_void -); +#ifdef CONFIG_MCC_DM +void phydm_mcc_igi_cal(void *dm_void); #endif diff --git a/hal/phydm/phydm_dynamictxpower.c b/hal/phydm/phydm_dynamictxpower.c index 4cd8dd7..ed67ec9 100644 --- a/hal/phydm/phydm_dynamictxpower.c +++ b/hal/phydm/phydm_dynamictxpower.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,528 +8,500 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -/* ************************************************************ +/************************************************************* * include files - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" +#ifdef CONFIG_DYNAMIC_TX_TWR + +#ifdef BB_RAM_SUPPORT void -odm_dynamic_tx_power_init( - void *p_dm_void -) +phydm_2ndtype_dtp_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - - /*if (!IS_HARDWARE_TYPE_8814A(adapter)) {*/ - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, */ - /* ("odm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->is_dynamic_tx_power_enable));*/ - /* return;*/ - /*} else*/ - { - p_mgnt_info->bDynamicTxPowerEnable = true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("odm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->bDynamicTxPowerEnable)); - } + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 pwr_offset_minus3, pwr_offset_minus7; + /*@ 2's com, for offset 3dB and 7dB, which 1 step will be 0.25dB*/ + pwr_offset_minus3 = BIT(7) | 0x74; + pwr_offset_minus7 = BIT(7) | 0x64; + odm_set_bb_reg(dm, 0x1e70, 0x00ff0000, pwr_offset_minus3); + odm_set_bb_reg(dm, 0x1e70, 0xff000000, pwr_offset_minus7); +}; -#if DEV_BUS_TYPE == RT_USB_INTERFACE - if (RT_GetInterfaceSelection(adapter) == INTF_SEL1_USB_High_Power) { - odm_dynamic_tx_power_save_power_index(p_dm_odm); - p_mgnt_info->bDynamicTxPowerEnable = true; - } else -#else - /* so 92c pci do not need dynamic tx power? vivi check it later */ - p_mgnt_info->bDynamicTxPowerEnable = false; -#endif - - - p_hal_data->LastDTPLvl = tx_high_pwr_level_normal; - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; +void +phdm_2ndtype_rd_ram_pwr(void *dm_void, u8 macid) +{ +}; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void +phdm_2ndtype_wt_ram_pwr(void *dm_void, u8 macid, boolean pwr_offset0_en, + boolean pwr_offset1_en, s8 pwr_offset0, s8 pwr_offset1) +{ + u32 reg_io_0x1e84 = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL; + dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid]; + dm_ram_per_sta->tx_pwr_offset0_en = pwr_offset0_en; + dm_ram_per_sta->tx_pwr_offset1_en = pwr_offset1_en; + dm_ram_per_sta->tx_pwr_offset0 = pwr_offset0; + dm_ram_per_sta->tx_pwr_offset1 = pwr_offset1; + reg_io_0x1e84 = (dm_ram_per_sta->hw_igi_en<<7) + dm_ram_per_sta->hw_igi; + reg_io_0x1e84 |= (pwr_offset0_en<<15) + ((pwr_offset0&0x7f)<<8); + reg_io_0x1e84 |= (pwr_offset1_en<<23) + ((pwr_offset1&0x7f)<<16); + reg_io_0x1e84 |= (macid&0x3f)<<24; + reg_io_0x1e84 |= BIT(30); + odm_set_bb_reg(dm, 0x1e84, 0xffffffff, reg_io_0x1e84); +}; + +u8 phydm_pwr_lv_mapping_2ndtype(u8 tx_pwr_lv) +{ + if (tx_pwr_lv == tx_high_pwr_level_level3) + /*PHYDM_2ND_OFFSET_MINUS_11DB;*/ + return PHYDM_2ND_OFFSET_MINUS_7DB; + else if (tx_pwr_lv == tx_high_pwr_level_level2) + return PHYDM_2ND_OFFSET_MINUS_7DB; + else if (tx_pwr_lv == tx_high_pwr_level_level1) + return PHYDM_2ND_OFFSET_MINUS_3DB; + else + return PHYDM_2ND_OFFSET_ZERO; +} - p_dm_odm->last_dtp_lvl = tx_high_pwr_level_normal; - p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal; - p_dm_odm->tx_agc_ofdm_18_6 = odm_get_bb_reg(p_dm_odm, 0xC24, MASKDWORD); /*TXAGC {18M 12M 9M 6M}*/ +void phydm_dtp_fill_cmninfo_2ndtype(void *dm_void, u8 macid, u8 dtp_lvl) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dtp_info *dtp = NULL; + dtp = &dm->phydm_sta_info[macid]->dtp_stat; + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; + dtp->dyn_tx_power = phydm_pwr_lv_mapping_2ndtype(dtp_lvl); + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\n", macid, + dtp->dyn_tx_power); + /* dyn_tx_power is 2 bit at 8822C/14B/98F/12F*/ +} #endif -} - -void -odm_dynamic_tx_power_save_power_index( - void *p_dm_void -) +boolean +phydm_check_rates(void *dm_void, u8 rate_idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) - u8 index; - u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 check_rate_bitmap0 = 0x08080808; /* @check CCK11M, OFDM54M, MCS7, MCS15*/ + u32 check_rate_bitmap1 = 0x80200808; /* @check MCS23, MCS31, VHT1SS M9, VHT2SS M9*/ + u32 check_rate_bitmap2 = 0x00080200; /* @check VHT3SS M9, VHT4SS M9*/ + u32 bitmap_result; + +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8822B) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0xfffff000; + check_rate_bitmap0 &= 0x0fffffff; + } +#endif -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - for (index = 0; index < 6; index++) - p_hal_data->PowerIndex_backup[index] = PlatformEFIORead1Byte(adapter, power_index_reg[index]); +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8197F) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0; + check_rate_bitmap0 &= 0x0fffffff; + } +#endif +#if (RTL8192E_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8192E) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0; + check_rate_bitmap0 &= 0x0fffffff; + } +#endif +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8192F) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0; + check_rate_bitmap0 &= 0x0fffffff; + } #endif +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821C) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0x003ff000; + check_rate_bitmap0 &= 0x000fffff; + } #endif + + if (rate_idx >= 64) + bitmap_result = BIT(rate_idx - 64) & check_rate_bitmap2; + else if (rate_idx >= 32) + bitmap_result = BIT(rate_idx - 32) & check_rate_bitmap1; + else if (rate_idx <= 31) + bitmap_result = BIT(rate_idx) & check_rate_bitmap0; + + if (bitmap_result != 0) + return true; + else + return false; } -void -odm_dynamic_tx_power_restore_power_index( - void *p_dm_void -) +enum rf_path +phydm_check_paths(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) - u8 index; - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - for (index = 0; index < 6; index++) - PlatformEFIOWrite1Byte(adapter, power_index_reg[index], p_hal_data->PowerIndex_backup[index]); + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum rf_path max_path = RF_PATH_A; + + if (dm->num_rf_path == 1) + max_path = RF_PATH_A; + if (dm->num_rf_path == 2) + max_path = RF_PATH_B; + if (dm->num_rf_path == 3) + max_path = RF_PATH_C; + if (dm->num_rf_path == 4) + max_path = RF_PATH_D; + + return max_path; +} +#ifndef PHYDM_COMMON_API_SUPPORT +u8 phydm_dtp_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ret = 0xff; +#if (RTL8192E_SUPPORT == 1) + ret = config_phydm_read_txagc_n(dm, path, hw_rate); #endif -#endif + return ret; } +#endif -void -odm_dynamic_tx_power_write_power_index( - void *p_dm_void, - u8 value) +u8 phydm_search_min_power_index(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 index; - u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; - - for (index = 0; index < 6; index++) - /* platform_efio_write_1byte(adapter, power_index_reg[index], value); */ - odm_write_1byte(p_dm_odm, power_index_reg[index], value); + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum rf_path path; + enum rf_path max_path; + u8 min_gain_index = 0x3f; + u8 gain_index; + u8 rate_idx; + + PHYDM_DBG(dm, DBG_DYN_TXPWR, "%s\n", __func__); + max_path = phydm_check_paths(dm); + for (path = 0; path <= max_path; path++) + for (rate_idx = 0; rate_idx < 84; rate_idx++) + if (phydm_check_rates(dm, rate_idx)) { +#ifdef PHYDM_COMMON_API_SUPPORT + /*This is for API support IC : 97F,8822B,92F,8821C*/ + gain_index = phydm_api_get_txagc(dm, path, rate_idx); +#else + /*This is for API non-support IC : 92E */ + gain_index = phydm_dtp_get_txagc(dm, path, rate_idx); +#endif + if (gain_index == 0xff) { + min_gain_index = 0x20; + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "Error Gain idx!! Rewite to: ((%d))\n", min_gain_index); + break; + } + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "Support Rate: ((%d)) -> Gain idx: ((%d))\n", + rate_idx, gain_index); + if (gain_index < min_gain_index) + min_gain_index = gain_index; + } + return min_gain_index; } -void -odm_dynamic_tx_power_nic_ce( - void *p_dm_void -) +void phydm_dynamic_tx_power_init(void *dm_void) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -#if (RTL8821A_SUPPORT == 1) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 val; - u8 rssi_tmp = p_dm_odm->rssi_min; - - if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR)) - return; - - if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { - p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level2; - /**/ - } else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) { - p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level1; - /**/ - } else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { - p_dm_odm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal; - /**/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i; + dm->last_dtp_lvl = tx_high_pwr_level_normal; + dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal; + for (i = 0; i < 3; i++) { + dm->enhance_pwr_th[i] = 0xff; } + dm->set_pwr_th[0] = TX_POWER_NEAR_FIELD_THRESH_LVL1; + dm->set_pwr_th[1] = TX_POWER_NEAR_FIELD_THRESH_LVL2; + dm->set_pwr_th[2] = 0xff; + dm->min_power_index = phydm_search_min_power_index(dm); + PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain idx: ((%d))\n", + dm->min_power_index); +} - if (p_dm_odm->last_dtp_lvl != p_dm_odm->dynamic_tx_high_power_lvl) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("update_DTP_lv: ((%d)) -> ((%d))\n", p_dm_odm->last_dtp_lvl, p_dm_odm->dynamic_tx_high_power_lvl)); - - p_dm_odm->last_dtp_lvl = p_dm_odm->dynamic_tx_high_power_lvl; - - if (p_dm_odm->support_ic_type & (ODM_RTL8821)) { - - if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level2) { - - odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/ - - val = p_dm_odm->tx_agc_ofdm_18_6 & 0xff; - if (val >= 0x20) - val -= 0x16; - - odm_set_bb_reg(p_dm_odm, 0xC24, 0xff, val); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 2\n")); - } else if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level1) { - - odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/ - - val = p_dm_odm->tx_agc_ofdm_18_6 & 0xff; - if (val >= 0x20) - val -= 0x10; - - odm_set_bb_reg(p_dm_odm, 0xC24, 0xff, val); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: level 1\n")); - } else if (p_dm_odm->dynamic_tx_high_power_lvl == tx_high_pwr_level_normal) { - - odm_set_mac_reg(p_dm_odm, 0x6D8, BIT(20) | BIT19 | BIT18, 0); /* Resp TXAGC offset = 0dB*/ - odm_set_bb_reg(p_dm_odm, 0xC24, MASKDWORD, p_dm_odm->tx_agc_ofdm_18_6); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, ODM_DBG_LOUD, ("Set TX power: normal\n")); - } - } +void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + if (noisy_state == 0) { + dm->enhance_pwr_th[0] = dm->set_pwr_th[0]; + dm->enhance_pwr_th[1] = dm->set_pwr_th[1]; + dm->enhance_pwr_th[2] = dm->set_pwr_th[2]; + } else { + dm->enhance_pwr_th[0] = dm->set_pwr_th[0] + 8; + dm->enhance_pwr_th[1] = dm->set_pwr_th[1] + 5; + dm->enhance_pwr_th[2] = dm->set_pwr_th[2]; } + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "DTP hp_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n", + dm->enhance_pwr_th[0], dm->enhance_pwr_th[1], + dm->enhance_pwr_th[2]); +} -#endif -#endif +u8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 th0,th1,th2; + th2 = dm->enhance_pwr_th[2]; + th1 = dm->enhance_pwr_th[1]; + th0 = dm->enhance_pwr_th[0]; + if (input_rssi >= th2) + return tx_high_pwr_level_level3; + else if (input_rssi < (th2 - 3) && input_rssi >= th1) + return tx_high_pwr_level_level2; + else if (input_rssi < (th1 - 3) && input_rssi >= th0) + return tx_high_pwr_level_level1; + else if (input_rssi < (th0 - 3)) + return tx_high_pwr_level_normal; + else + return tx_high_pwr_level_unchange; } +u8 phydm_pwr_lv_mapping(u8 tx_pwr_lv) +{ + if (tx_pwr_lv == tx_high_pwr_level_level3) + return PHYDM_OFFSET_MINUS_11DB; + else if (tx_pwr_lv == tx_high_pwr_level_level2) + return PHYDM_OFFSET_MINUS_7DB; + else if (tx_pwr_lv == tx_high_pwr_level_level1) + return PHYDM_OFFSET_MINUS_3DB; + else + return PHYDM_OFFSET_ZERO; +} -void -odm_dynamic_tx_power( - void *p_dm_void -) +void phydm_dynamic_response_power(void *dm_void) { - /* */ - /* For AP/ADSL use struct rtl8192cd_priv* */ - /* For CE/NIC use struct _ADAPTER* */ - /* */ - /* struct _ADAPTER* p_adapter = p_dm_odm->adapter; - * struct rtl8192cd_priv* priv = p_dm_odm->priv; */ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rpwr; + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; + if (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_unchange) { + dm->dynamic_tx_high_power_lvl = dm->last_dtp_lvl; + PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr not change\n"); return; - /* */ - /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ - /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ - /* HW dynamic mechanism. */ - /* */ - switch (p_dm_odm->support_platform) { - case ODM_WIN: - odm_dynamic_tx_power_nic(p_dm_odm); - break; - case ODM_CE: - odm_dynamic_tx_power_nic_ce(p_dm_odm); - break; - case ODM_AP: - odm_dynamic_tx_power_ap(p_dm_odm); - break; - default: - break; } - + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "RespPwr update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl, + dm->dynamic_tx_high_power_lvl); + dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl; + rpwr = phydm_pwr_lv_mapping(dm->dynamic_tx_high_power_lvl); + odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT(19) | BIT(18), rpwr); + PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr Set TxPwr: Lv (%d)\n", + dm->dynamic_tx_high_power_lvl); } - -void -odm_dynamic_tx_power_nic( - void *p_dm_void -) +void phydm_dtp_fill_cmninfo(void *dm_void, u8 macid, u8 dtp_lvl) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dtp_info *dtp = NULL; + dtp = &dm->phydm_sta_info[macid]->dtp_stat; + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) return; - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - if (p_dm_odm->support_ic_type == ODM_RTL8814A) - odm_dynamic_tx_power_8814a(p_dm_odm); - else if (p_dm_odm->support_ic_type & ODM_RTL8821) { - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(adapter); - - if (p_mgnt_info->RegRspPwr == 1) { - if (p_dm_odm->rssi_min > 60) - odm_set_mac_reg(p_dm_odm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 1); /*Resp TXAGC offset = -3dB*/ - else if (p_dm_odm->rssi_min < 55) - odm_set_mac_reg(p_dm_odm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 0); /*Resp TXAGC offset = 0dB*/ - } - } -#endif + dtp->dyn_tx_power = phydm_pwr_lv_mapping(dtp_lvl); + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\n", macid, + dtp->dyn_tx_power); } -void -odm_dynamic_tx_power_ap( - void *p_dm_void - -) +void phydm_dtp_per_sta(void *dm_void, u8 macid) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - - /* #if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1)) */ - - - struct rtl8192cd_priv *priv = p_dm_odm->priv; - s32 i; - s16 pwr_thd = 63; - - if (!priv->pshare->rf_ft_var.tx_pwr_ctrl) - return; - -#if ((RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8822B)) - pwr_thd = TX_POWER_NEAR_FIELD_THRESH_LVL1; -#endif - - /* - * Check if station is near by to use lower tx power - */ - - if ((priv->up_time % 3) == 0) { - int disable_pwr_ctrl = ((p_dm_odm->false_alm_cnt.cnt_all > 1000) || ((p_dm_odm->false_alm_cnt.cnt_all > 300) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - struct sta_info *pstat = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(pstat)) { - if (disable_pwr_ctrl) - pstat->hp_level = 0; - else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd)) - pstat->hp_level = 1; - else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd - 8))) - pstat->hp_level = 0; - } + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct dtp_info *dtp = NULL; + struct rssi_info *rssi = NULL; + if (is_sta_active(sta)) { + dtp = &sta->dtp_stat; + rssi = &sta->rssi_stat; + dtp->sta_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi->rssi); + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "STA=%d , RSSI: %d , GetPwrLv: %d\n", macid, + rssi->rssi, dtp->sta_tx_high_power_lvl); + if (dtp->sta_tx_high_power_lvl == tx_high_pwr_level_unchange + || dtp->sta_tx_high_power_lvl == dtp->sta_last_dtp_lvl) { + dtp->sta_tx_high_power_lvl = dtp->sta_last_dtp_lvl; + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "DTP_lv not change: ((%d))\n", + dtp->sta_tx_high_power_lvl); + return; } -#if defined(CONFIG_WLAN_HAL_8192EE) - if (GET_CHIP_VER(priv) == VERSION_8192E) { - if (!disable_pwr_ctrl && (p_dm_odm->rssi_min != 0xff)) { - if (p_dm_odm->rssi_min > pwr_thd) - RRSR_power_control_11n(priv, 1); - else if (p_dm_odm->rssi_min < (pwr_thd - 8)) - RRSR_power_control_11n(priv, 0); - } else - RRSR_power_control_11n(priv, 0); - } + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "DTP_lv update: ((%d)) -> ((%d))\n", dm->last_dtp_lvl, + dm->dynamic_tx_high_power_lvl); + dtp->sta_last_dtp_lvl = dtp->sta_tx_high_power_lvl; +#ifdef BB_RAM_SUPPORT + phydm_dtp_fill_cmninfo_2ndtype(dm, macid, dtp->sta_tx_high_power_lvl); +#else + phydm_dtp_fill_cmninfo(dm, macid, dtp->sta_tx_high_power_lvl); #endif + } +} -#ifdef CONFIG_WLAN_HAL_8814AE - if (GET_CHIP_VER(priv) == VERSION_8814A) { - if (!disable_pwr_ctrl && (p_dm_odm->rssi_min != 0xff)) { - if (p_dm_odm->rssi_min > pwr_thd) - RRSR_power_control_14(priv, 1); - else if (p_dm_odm->rssi_min < (pwr_thd - 8)) - RRSR_power_control_14(priv, 0); - } else - RRSR_power_control_14(priv, 0); - } -#endif +void odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 macid) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct dtp_info *dtp = NULL; + dtp = &dm->phydm_sta_info[macid]->dtp_stat; + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; + if (dm->fill_desc_dyntxpwr) + dm->fill_desc_dyntxpwr(dm, desc, dtp->dyn_tx_power); + else + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "%s: fill_desc_dyntxpwr is null!\n", __func__); + if (dtp->last_tx_power != dtp->dyn_tx_power) { + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "%s: last_offset=%d, txpwr_offset=%d\n", __func__, + dtp->last_tx_power, dtp->dyn_tx_power); + dtp->last_tx_power = dtp->dyn_tx_power; } - /* #endif */ - -#endif } -void -odm_dynamic_tx_power_8821( - void *p_dm_void, - u8 *p_desc, - u8 mac_id -) +void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) { -#if (RTL8821A_SUPPORT == 1) -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct sta_info *p_entry; - u8 reg0xc56_byte; - u8 txpwr_offset = 0; - - p_entry = p_dm_odm->p_odm_sta_info[mac_id]; - - reg0xc56_byte = odm_read_1byte(p_dm_odm, 0xc56); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte)); - - if (p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb > 85) { - - /* Avoid TXAGC error after TX power offset is applied. - For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB ) - Total power = 6-11= -5( overflow!! ), PA may be burned ! - so txpwr_offset should be adjusted by Reg0xc56*/ - - if (reg0xc56_byte < 7) - txpwr_offset = 1; - else if (reg0xc56_byte < 11) - txpwr_offset = 2; - else - txpwr_offset = 3; - - SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb, txpwr_offset)); - + u32 used = *_used; + u32 out_len = *_out_len; + + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[3] = {0}; + u8 set_pwr_th1, set_pwr_th2, set_pwr_th3; + u8 i; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{DynTxPwr} {TH1 TH2 TH3}\n"); } else { - SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.undecorated_smoothed_pwdb, txpwr_offset)); - + for (i = 0; i < 3; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + } + for (i = 0; i < 3; i++) + if (var1[i] == 0 || var1[i] > 100) + dm->set_pwr_th[i] = 0xff; + else + dm->set_pwr_th[i] = (u8)var1[i]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Phydm Set DTP : TH1 = (( 0x%x)), TH2 = (( 0x%x)), TH3 = (( 0x%x))\n", + dm->set_pwr_th[0], dm->set_pwr_th[1], + dm->set_pwr_th[2]); } -#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ -#endif /*#if (RTL8821A_SUPPORT==1)*/ + *_used = used; + *_out_len = out_len; } -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -odm_dynamic_tx_power_8814a( - void *p_dm_void -) + +void phydm_dynamic_tx_power(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - s32 undecorated_smoothed_pwdb; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("TxLevel=%d p_mgnt_info->iot_action=%x p_mgnt_info->is_dynamic_tx_power_enable=%d\n", - p_hal_data->DynamicTxHighPowerLvl, p_mgnt_info->IOTAction, p_mgnt_info->bDynamicTxPowerEnable)); - - /*STA not connected and AP not connected*/ - if ((!p_mgnt_info->bMediaConnect) && (p_hal_data->EntryMinUndecoratedSmoothedPWDB == 0)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any reset power lvl\n")); - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; - return; - } + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + u8 i; + u8 cnt = 0; + u8 rssi_min = dm->rssi_min; + u8 rssi_tmp = 0; - if ((p_mgnt_info->bDynamicTxPowerEnable != true) || p_mgnt_info->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; - else { - if (p_mgnt_info->bMediaConnect) { /*Default port*/ - if (ACTING_AS_AP(adapter) || ACTING_AS_IBSS(adapter)) { - undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x\n", undecorated_smoothed_pwdb)); - } else { - undecorated_smoothed_pwdb = p_hal_data->UndecoratedSmoothedPWDB; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", undecorated_smoothed_pwdb)); - } - } else {/*associated entry pwdb*/ - undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x\n", undecorated_smoothed_pwdb)); - } + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; - /*Should we separate as 2.4G/5G band?*/ - - if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_level1 (TxPwr=0x0)\n")); - } else if ((undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) && - (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) { - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_level1 (TxPwr=0x10)\n")); - } else if (undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { - p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("tx_high_pwr_level_normal\n")); - } + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "[%s] RSSI_min = %d, Noisy_dec = %d\n", __func__, rssi_min, + dm->noisy_decision); + phydm_noisy_enhance_hp_th(dm, dm->noisy_decision); +#ifndef BB_RAM_SUPPORT + /* Response Power */ + dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi_min); + phydm_dynamic_response_power(dm); +#endif /* #ifndef BB_RAM_SUPPORT */ + /* Per STA Tx power */ + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + phydm_dtp_per_sta(dm, i); + cnt++; + if (cnt >= dm->number_linked_client) + break; } +} +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_dynamic_tx_power_init_win(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); - if (p_hal_data->DynamicTxHighPowerLvl != p_hal_data->LastDTPLvl) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_dynamic_tx_power_8814a() channel = %d\n", p_hal_data->CurrentChannel)); - odm_set_tx_power_level8814(adapter, p_hal_data->CurrentChannel, p_hal_data->DynamicTxHighPowerLvl); - } - + mgnt_info->bDynamicTxPowerEnable = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, - ("odm_dynamic_tx_power_8814a() channel = %d TXpower lvl=%d/%d\n", - p_hal_data->CurrentChannel, p_hal_data->LastDTPLvl, p_hal_data->DynamicTxHighPowerLvl)); + #if DEV_BUS_TYPE == RT_USB_INTERFACE + if (RT_GetInterfaceSelection((PADAPTER)adapter) == + INTF_SEL1_USB_High_Power) { + mgnt_info->bDynamicTxPowerEnable = true; + } + #endif - p_hal_data->LastDTPLvl = p_hal_data->DynamicTxHighPowerLvl; + hal_data->LastDTPLvl = tx_high_pwr_level_normal; + hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; + PHYDM_DBG(dm, DBG_DYN_TXPWR, "[%s] DTP=%d\n", __func__, + mgnt_info->bDynamicTxPowerEnable); } - - -/**/ -/*For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/ -/**/ -/**/ -void -odm_set_tx_power_level8814( - struct _ADAPTER *adapter, - u8 channel, - u8 pwr_lvl -) +void phydm_dynamic_tx_power_win(void *dm_void) { -#if (DEV_BUS_TYPE == RT_USB_INTERFACE) - u32 i, j, k = 0; - u32 value[264] = {0}; - u32 path = 0, power_index, txagc_table_wd = 0x00801000; - - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - - u8 jaguar2_rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}, - {MGN_6M, MGN_9M, MGN_12M, MGN_18M}, - {MGN_24M, MGN_36M, MGN_48M, MGN_54M}, - {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3}, - {MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}, - {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11}, - {MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}, - {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19}, - {MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}, - {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3}, - {MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7}, - {MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1}, - {MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5}, - {MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9}, - {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3}, - {MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7}, - {MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0} - }; - - for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { - - u8 usb_host = UsbModeQueryHubUsbType(adapter); - u8 usb_rfset = UsbModeQueryRfSet(adapter); - u8 usb_rf_type = RT_GetRFType(adapter); - - for (i = 0; i <= 16; i++) { - for (j = 0; j <= 3; j++) { - if (jaguar2_rates[i][j] == 0) - continue; - - txagc_table_wd = 0x00801000; - power_index = (u32) PHY_GetTxPowerIndex(adapter, (u8)path, jaguar2_rates[i][j], p_hal_data->CurrentChannelBW, channel); - - /*for Query bus type to recude tx power.*/ - if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(adapter) && usb_rf_type == RF_3T3R) { - if (channel <= 14) { - if (power_index >= 16) - power_index -= 16; - else - power_index = 0; - } else - power_index = 0; - } - - if (pwr_lvl == tx_high_pwr_level_level1) { - if (power_index >= 0x10) - power_index -= 0x10; - else - power_index = 0; - } else if (pwr_lvl == tx_high_pwr_level_level2) - power_index = 0; - - txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2_rates[i][j]) | (power_index << 24); + struct dm_struct *dm = (struct dm_struct *)dm_void; - PHY_SetTxPowerIndexShadow(adapter, (u8)power_index, (u8)path, jaguar2_rates[i][j]); + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; - value[k++] = txagc_table_wd; + #if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8814A) + odm_dynamic_tx_power_8814a(dm); + #endif + + #if (RTL8821A_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8821) { + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter); + + if (mgnt_info->RegRspPwr == 1) { + if (dm->rssi_min > 60) { + /*Resp TXAGC offset = -3dB*/ + odm_set_mac_reg(dm, 0x6d8, 0x1C0000, 1); + } else if (dm->rssi_min < 55) { + /*Resp TXAGC offset = 0dB*/ + odm_set_mac_reg(dm, 0x6d8, 0x1C0000, 0); } } } - - if (adapter->MgntInfo.bScanInProgress == false && adapter->MgntInfo.RegFWOffload == 2) - HalDownloadTxPowerLevel8814(adapter, value); -#endif + #endif } -#endif +#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ +#endif /* @#ifdef CONFIG_DYNAMIC_TX_TWR */ diff --git a/hal/phydm/phydm_dynamictxpower.h b/hal/phydm/phydm_dynamictxpower.h index badae89..3906b72 100644 --- a/hal/phydm/phydm_dynamictxpower.h +++ b/hal/phydm/phydm_dynamictxpower.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,103 +8,96 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMDYNAMICTXPOWER_H__ +#define __PHYDMDYNAMICTXPOWER_H__ -#ifndef __PHYDMDYNAMICTXPOWER_H__ -#define __PHYDMDYNAMICTXPOWER_H__ +#ifdef CONFIG_DYNAMIC_TX_TWR +/* @============================================================ + * Definition + * ============================================================ + */ -/*#define DYNAMIC_TXPWR_VERSION "1.0"*/ -/*#define DYNAMIC_TXPWR_VERSION "1.3" */ /*2015.08.26, Add 8814 Dynamic TX power*/ -#define DYNAMIC_TXPWR_VERSION "1.4" /*2015.11.06, Add CE 8821A Dynamic TX power*/ +/*@#define DYNAMIC_TXPWR_VERSION "1.0"*/ +/*@#define DYNAMIC_TXPWR_VERSION "1.3" */ /*@2015.08.26, Add 8814 Dynamic TX power*/ +#define DYNAMIC_TXPWR_VERSION "1.4" /*@2015.11.06, Add CE 8821A Dynamic TX power*/ #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 - #define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 - #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 +#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 - #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 - #define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 #endif -#define tx_high_pwr_level_normal 0 -#define tx_high_pwr_level_level1 1 -#define tx_high_pwr_level_level2 2 - -#define tx_high_pwr_level_bt1 3 -#define tx_high_pwr_level_bt2 4 -#define tx_high_pwr_level_15 5 -#define tx_high_pwr_level_35 6 -#define tx_high_pwr_level_50 7 -#define tx_high_pwr_level_70 8 -#define tx_high_pwr_level_100 9 - -void -odm_dynamic_tx_power_init( - void *p_dm_void -); - -void -odm_dynamic_tx_power_restore_power_index( - void *p_dm_void -); - -void -odm_dynamic_tx_power_nic( - void *p_dm_void -); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -void -odm_dynamic_tx_power_save_power_index( - void *p_dm_void -); - -void -odm_dynamic_tx_power_write_power_index( - void *p_dm_void, - u8 value); - -void -odm_dynamic_tx_power_8821( - void *p_dm_void, - u8 *p_desc, - u8 mac_id -); +#define tx_high_pwr_level_normal 0 +#define tx_high_pwr_level_level1 1 +#define tx_high_pwr_level_level2 2 +#define tx_high_pwr_level_level3 3 +#define tx_high_pwr_level_unchange 4 + +/* @============================================================ + * enumrate + * ============================================================ + */ +enum phydm_dtp_power_offset { + PHYDM_OFFSET_ZERO = 0, + PHYDM_OFFSET_MINUS_3DB = 1, + PHYDM_OFFSET_MINUS_7DB = 2, + PHYDM_OFFSET_MINUS_11DB = 3, + PHYDM_OFFSET_ADD_3DB = 4, + PHYDM_OFFSET_ADD_6DB = 5 +}; + +enum phydm_dtp_power_offset_2ndtype { + PHYDM_2ND_OFFSET_ZERO = 0, + PHYDM_2ND_OFFSET_MINUS_3DB = 2, + PHYDM_2ND_OFFSET_MINUS_7DB = 3, + PHYDM_2ND_OFFSET_MINUS_11DB = 1 +}; + + +/* @============================================================ + * structure + * ============================================================ + */ + +/* @============================================================ + * Function Prototype + * ============================================================ + */ + +extern void +odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 mac_id); + +void phydm_dynamic_tx_power(void *dm_void); + +void phydm_dynamic_tx_power_init(void *dm_void); + +void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -odm_dynamic_tx_power_8814a( - void *p_dm_void -); - - -void -odm_set_tx_power_level8814( - struct _ADAPTER *adapter, - u8 channel, - u8 pwr_lvl -); -#endif +void odm_dynamic_tx_power_win(void *dm_void); #endif -void -odm_dynamic_tx_power( - void *p_dm_void -); - -void -odm_dynamic_tx_power_ap( - void *p_dm_void -); - +#endif #endif diff --git a/hal/phydm/phydm_features.h b/hal/phydm/phydm_features.h index bc072b3..ec87680 100644 --- a/hal/phydm/phydm_features.h +++ b/hal/phydm/phydm_features.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,191 +8,51 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ - -#ifndef __PHYDM_FEATURES_H__ -#define __PHYDM_FEATURES - -#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812) -#if ((RTL8814A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - #define PHYDM_LA_MODE_SUPPORT 1 -#else - #define PHYDM_LA_MODE_SUPPORT 0 -#endif + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_H__ +#define __PHYDM_FEATURES_H__ + +#define CONFIG_RUN_IN_DRV +#define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8821C) +#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E) + +/*@20170103 YuChen add for FW API*/ +#define PHYDM_FW_API_ENABLE_8822B 1 +#define PHYDM_FW_API_FUNC_ENABLE_8822B 1 +#define PHYDM_FW_API_ENABLE_8821C 1 +#define PHYDM_FW_API_FUNC_ENABLE_8821C 1 +#define PHYDM_FW_API_ENABLE_8195B 1 +#define PHYDM_FW_API_FUNC_ENABLE_8195B 1 +#define PHYDM_FW_API_ENABLE_8198F 1 +#define PHYDM_FW_API_FUNC_ENABLE_8198F 1 +#define PHYDM_FW_API_ENABLE_8822C 1 +#define PHYDM_FW_API_FUNC_ENABLE_8822C 1 +#define PHYDM_FW_API_ENABLE_8814B 1 +#define PHYDM_FW_API_FUNC_ENABLE_8814B 1 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - - #define CONFIG_PSD_TOOL 1 - /*phydm debyg report & tools*/ - #define CONFIG_PHYDM_DEBUG_FUNCTION 1 - - /*Antenna Diversity*/ - #define CONFIG_PHYDM_ANTENNA_DIVERSITY - #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY - - #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) - #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY - #endif - - #if (RTL8821A_SUPPORT == 1) - /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ - #define CONFIG_FAT_PATCH - #endif - - #if (RTL8822B_SUPPORT == 1) - /*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ - #endif - - #endif - - #if (RTL8822B_SUPPORT == 1) - #define CONFIG_DYNAMIC_RX_PATH 0 - #else - #define CONFIG_DYNAMIC_RX_PATH 0 - #endif - - #if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1 || RTL8812A_SUPPORT == 1) - #define CONFIG_RECEIVER_BLOCKING - #endif - #define PHYDM_SUPPORT_EDCA 0 - #define SUPPORTABLITY_PHYDMLIZE 1 - #define RA_MASK_PHYDMLIZE_WIN 1 - /*#define CONFIG_PATH_DIVERSITY*/ - /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ - #define CONFIG_ANT_DETECTION - /*#define CONFIG_RA_DBG_CMD*/ - #define CONFIG_RA_FW_DBG_CODE 1 - /*#define CONFIG_PHYDM_RX_SNIFFER_PARSING*/ - #define CONFIG_BB_POWER_SAVING - #define CONFIG_BB_TXBF_API - #define CONFIG_PHYDM_DFS_MASTER - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - #define CONFIG_PSD_TOOL 0 - /*phydm debyg report & tools*/ - #if defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION) - #define CONFIG_PHYDM_DEBUG_FUNCTION 0 - #else - #define CONFIG_PHYDM_DEBUG_FUNCTION 1 - #endif - - #if (RTL8822B_SUPPORT == 1) - #define CONFIG_DYNAMIC_RX_PATH 0 - #else - #define CONFIG_DYNAMIC_RX_PATH 0 - #endif - - #define PHYDM_SUPPORT_EDCA 1 - #define SUPPORTABLITY_PHYDMLIZE 0 - #define RA_MASK_PHYDMLIZE_AP 1 - - /* #define CONFIG_RA_DBG_CMD*/ - #define CONFIG_RA_FW_DBG_CODE 0 - - /*#define CONFIG_PATH_DIVERSITY*/ - /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ - #define CONFIG_RA_DYNAMIC_RATE_ID - /*#define CONFIG_BB_POWER_SAVING*/ - #define CONFIG_BB_TXBF_API - - /* [ Configure Antenna Diversity ] */ - #if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) - #define CONFIG_PHYDM_ANTENNA_DIVERSITY - #define ODM_EVM_ENHANCE_ANTDIV - - /*----------*/ - - #if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) - #define CONFIG_NO_2G_DIVERSITY - #endif - - #ifdef CONFIG_NO_5G_DIVERSITY_8881A - #define CONFIG_NO_5G_DIVERSITY - #elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A) - #define CONFIG_5G_CGCS_RX_DIVERSITY - #elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A) - #define CONFIG_5G_CG_TRX_DIVERSITY - #elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) - #define CONFIG_2G5G_CG_TRX_DIVERSITY - #endif - #if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) - #define CONFIG_NO_5G_DIVERSITY - #endif - /*----------*/ - #if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) - #define CONFIG_NOT_SUPPORT_ANTDIV - #elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) - #define CONFIG_2G_SUPPORT_ANTDIV - #elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) - #define CONFIG_5G_SUPPORT_ANTDIV - #elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY)) - #define CONFIG_2G5G_SUPPORT_ANTDIV - #endif - /*----------*/ - #endif - + #include "phydm_features_win.h" #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - #define CONFIG_PSD_TOOL 1 - /*phydm debyg report & tools*/ - #define CONFIG_PHYDM_DEBUG_FUNCTION 1 - - #if (RTL8822B_SUPPORT == 1) - #define CONFIG_DYNAMIC_RX_PATH 0 - #else - #define CONFIG_DYNAMIC_RX_PATH 0 - #endif - - #define PHYDM_SUPPORT_EDCA 0 - #define SUPPORTABLITY_PHYDMLIZE 1 - #define RA_MASK_PHYDMLIZE_CE 1 - - /*Antenna Diversity*/ - #ifdef CONFIG_ANTENNA_DIVERSITY - #define CONFIG_PHYDM_ANTENNA_DIVERSITY - - #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY - - #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) - #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY - #endif - - #if (RTL8821A_SUPPORT == 1) - /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ - #endif - #endif - #endif - - #ifdef CONFIG_DFS_MASTER - #define CONFIG_PHYDM_DFS_MASTER - #endif - - #if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1) - #define CONFIG_RECEIVER_BLOCKING - #endif - /*#define CONFIG_RA_DBG_CMD*/ - #define CONFIG_RA_FW_DBG_CODE 0 - /*#define CONFIG_ANT_DETECTION*/ - /*#define CONFIG_PATH_DIVERSITY*/ - /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ - #define CONFIG_BB_POWER_SAVING - #define CONFIG_BB_TXBF_API - - #ifdef CONFIG_BT_COEXIST - #define BT_SUPPORT 1 - #endif - - + #include "phydm_features_ce.h" + /*@#include "phydm_features_ce2_kernel.h"*/ +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "phydm_features_ap.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + #include "phydm_features_iot.h" #endif - #endif diff --git a/hal/phydm/phydm_features_ap.h b/hal/phydm/phydm_features_ap.h new file mode 100644 index 0000000..0f49382 --- /dev/null +++ b/hal/phydm/phydm_features_ap.h @@ -0,0 +1,196 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_AP_H__ +#define __PHYDM_FEATURES_AP_H__ + +#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT) + #define PHYDM_LA_MODE_SUPPORT 1 +#else + #define PHYDM_LA_MODE_SUPPORT 0 +#endif + +#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT) + #define FAHM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8822B_SUPPORT) + /*#define PHYDM_PHYSTAUS_SMP_MODE*/ +#endif + +#if (RTL8197F_SUPPORT) + /*#define PHYDM_TDMA_DIG_SUPPORT*/ +#endif + +#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + /*#define PHYDM_TDMA_DIG_SUPPORT 1*/ + #ifdef PHYDM_TDMA_DIG_SUPPORT + /*#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/ + #endif +#endif + +#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8198F_SUPPORT || RTL8814B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_SUPPORT*/ + #ifdef PHYDM_LNA_SAT_CHK_SUPPORT + + #if (RTL8197F_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_TYPE2*/ + #endif + + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_TYPE1*/ + #endif + #endif +#endif + +#if (RTL8822B_SUPPORT) + /*#define PHYDM_POWER_TRAINING_SUPPORT*/ +#endif + +#if (RTL8822C_SUPPORT) + /* #define PHYDM_PMAC_TX_SETTING_SUPPORT */ +#endif + +#if (RTL8822C_SUPPORT) + /* #define PHYDM_MP_SUPPORT */ +#endif + +#if (RTL8822B_SUPPORT) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + #define PHYDM_PRIMARY_CCA +#endif + +#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8192F_SUPPORT) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + #define CONFIG_ADAPTIVE_SOML +#endif + +#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\ + RTL8192E_SUPPORT || RTL8723B_SUPPORT) + /*#define CONFIG_RA_FW_DBG_CODE*/ +#endif + +#if (RTL8192F_SUPPORT == 1) + /*#define CONFIG_8912F_SPUR_CALIBRATION*/ +#endif + +#if (RTL8822B_SUPPORT == 1) + /* #define CONFIG_8822B_SPUR_CALIBRATION */ +#endif + +#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR +#define CONFIG_DYNAMIC_TX_TWR +#endif +/*#define CONFIG_PSD_TOOL*/ +#define PHYDM_SUPPORT_CCKPD +#define PHYDM_SUPPORT_ADAPTIVITY +/*#define CONFIG_PATH_DIVERSITY*/ +/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ +/*#define CONFIG_RA_DYNAMIC_RATE_ID*/ +#define CONFIG_BB_TXBF_API +/*#define ODM_CONFIG_BT_COEXIST*/ +#define PHYDM_SUPPORT_RSSI_MONITOR +#if !defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION) + #define CONFIG_PHYDM_DEBUG_FUNCTION +#endif + +/* [ Configure Antenna Diversity ] */ +#if (RTL8188F_SUPPORT) + #ifdef CONFIG_ANTENNA_DIVERSITY + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif +#endif + +#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH) + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + #define ODM_EVM_ENHANCE_ANTDIV + #define SKIP_EVM_ANTDIV_TRAINING_PATCH + + /*----------*/ + #ifdef CONFIG_NO_2G_DIVERSITY_8197F + #define CONFIG_NO_2G_DIVERSITY + #elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197F) + #define CONFIG_2G_CGCS_RX_DIVERSITY + #elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197F) + #define CONFIG_2G_CG_TRX_DIVERSITY + #endif + + #if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_2G_DIVERSITY + #endif + + #ifdef CONFIG_NO_5G_DIVERSITY_8881A + #define CONFIG_NO_5G_DIVERSITY + #elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A) + #define CONFIG_5G_CGCS_RX_DIVERSITY + #elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_5G_CG_TRX_DIVERSITY + #elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_2G5G_CG_TRX_DIVERSITY + #endif + #if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_5G_DIVERSITY + #endif + /*----------*/ + #if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_NOT_SUPPORT_ANTDIV + #elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_2G_SUPPORT_ANTDIV + #elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_5G_SUPPORT_ANTDIV + #elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY)) + #define CONFIG_2G5G_SUPPORT_ANTDIV + #endif + /*----------*/ +#endif /*Antenna Diveristy*/ + +/*[SmartAntenna]*/ +/*#define CONFIG_SMART_ANTENNA*/ +#ifdef CONFIG_SMART_ANTENNA + /*#define CONFIG_CUMITEK_SMART_ANTENNA*/ +#endif +#define CFG_DIG_DAMPING_CHK +/* --------------------------------------------------*/ +#ifdef BEAMFORMING_SUPPORT + #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT) + #define DRIVER_BEAMFORMING_VERSION2 + #endif +#endif + +#endif diff --git a/hal/phydm/phydm_features_ce.h b/hal/phydm/phydm_features_ce.h new file mode 100644 index 0000000..52cb34d --- /dev/null +++ b/hal/phydm/phydm_features_ce.h @@ -0,0 +1,205 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_CE_H__ +#define __PHYDM_FEATURES_CE_H__ + +#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT) + #define PHYDM_LA_MODE_SUPPORT 1 +#else + #define PHYDM_LA_MODE_SUPPORT 0 +#endif + +#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT) + #define FAHM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8822B_SUPPORT) + /*@#define PHYDM_PHYSTAUS_SMP_MODE*/ +#endif + +/*@#define PHYDM_TDMA_DIG_SUPPORT*/ + +#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT) + /*@#define PHYDM_TDMA_DIG_SUPPORT*/ + #ifdef PHYDM_TDMA_DIG_SUPPORT + /*@#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/ + #endif +#endif + +#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT) + /*@#define PHYDM_LNA_SAT_CHK_SUPPORT*/ + #ifdef PHYDM_LNA_SAT_CHK_SUPPORT + + #if (RTL8197F_SUPPORT) + /*@#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*@#define PHYDM_LNA_SAT_CHK_TYPE2*/ + #endif + + #if (RTL8814B_SUPPORT) + /*@#define PHYDM_LNA_SAT_CHK_TYPE1*/ + #endif + #endif +#endif + +#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT) + #define PHYDM_POWER_TRAINING_SUPPORT +#endif + +#if (RTL8822C_SUPPORT) + /* #define PHYDM_PMAC_TX_SETTING_SUPPORT */ +#endif + +#if (RTL8822C_SUPPORT) + /* #define PHYDM_MP_SUPPORT */ +#endif + +#if (RTL8822B_SUPPORT) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188E_SUPPORT) + #define PHYDM_PRIMARY_CCA +#endif + +#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8192F_SUPPORT) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + #define CONFIG_ADAPTIVE_SOML +#endif + +#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT) + #define CONFIG_RECEIVER_BLOCKING +#endif + +#if (RTL8192F_SUPPORT == 1) + /*#define CONFIG_8912F_SPUR_CALIBRATION*/ +#endif + +#if (RTL8822B_SUPPORT == 1) + #define CONFIG_8822B_SPUR_CALIBRATION +#endif + +#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR +#define CONFIG_DYNAMIC_TX_TWR +#endif +#define PHYDM_SUPPORT_CCKPD +#define PHYDM_SUPPORT_ADAPTIVITY + +/*@Antenna Diversity*/ +#ifdef CONFIG_ANTENNA_DIVERSITY + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\ + RTL8188F_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8723D_SUPPORT) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8821A_SUPPORT) + /*@#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*@#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ + #endif + + #endif +#endif + +/*@[SmartAntenna]*/ +/*@#define CONFIG_SMART_ANTENNA*/ +#ifdef CONFIG_SMART_ANTENNA + /*@#define CONFIG_CUMITEK_SMART_ANTENNA*/ +#endif +/* @--------------------------------------------------*/ + +#ifdef CONFIG_DFS_MASTER + #define CONFIG_PHYDM_DFS_MASTER +#endif + +#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\ + RTL8192E_SUPPORT || RTL8723B_SUPPORT) + /*@#define CONFIG_RA_FW_DBG_CODE*/ +#endif + +#define CONFIG_PSD_TOOL +/*@#define CONFIG_ANT_DETECTION*/ +/*@#define CONFIG_PATH_DIVERSITY*/ +/*@#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ +#define CONFIG_BB_TXBF_API +#define CONFIG_PHYDM_DEBUG_FUNCTION + +#ifdef CONFIG_BT_COEXIST + #define ODM_CONFIG_BT_COEXIST +#endif +#define PHYDM_SUPPORT_RSSI_MONITOR +/*@#define PHYDM_AUTO_DEGBUG*/ +#define CFG_DIG_DAMPING_CHK + + +#ifdef BEAMFORMING_SUPPORT + #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\ + RTL8814A_SUPPORT || RTL8881A_SUPPORT) + #define PHYDM_BEAMFORMING_VERSION1 + #endif + #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT) + #define DRIVER_BEAMFORMING_VERSION2 + #endif +#endif + +#if (RTL8822B_SUPPORT) + #ifdef CONFIG_MCC_MODE + #define CONFIG_MCC_DM + #endif +#endif + +#if (RTL8822B_SUPPORT) + #ifdef CONFIG_DYNAMIC_BYPASS_MODE + #define CONFIG_DYNAMIC_BYPASS + #endif +#endif + + +#endif diff --git a/hal/phydm/phydm_features_ce2_kernel.h b/hal/phydm/phydm_features_ce2_kernel.h new file mode 100644 index 0000000..1578e4d --- /dev/null +++ b/hal/phydm/phydm_features_ce2_kernel.h @@ -0,0 +1,84 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_CE_H__ +#define __PHYDM_FEATURES_CE_H__ + +#define PHYDM_LA_MODE_SUPPORT 0 + +#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT) + #define FAHM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8822B_SUPPORT) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8192F_SUPPORT) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8192F_SUPPORT == 1) + /*#define CONFIG_8912F_SPUR_CALIBRATION*/ +#endif + +#if (RTL8822B_SUPPORT == 1) + /* #define CONFIG_8822B_SPUR_CALIBRATION */ +#endif + +#define PHYDM_SUPPORT_CCKPD +#define PHYDM_SUPPORT_ADAPTIVITY + +#ifdef CONFIG_DFS_MASTER + #define CONFIG_PHYDM_DFS_MASTER +#endif + +#define CONFIG_BB_TXBF_API +#define CONFIG_PHYDM_DEBUG_FUNCTION + +#ifdef CONFIG_BT_COEXIST + #define ODM_CONFIG_BT_COEXIST +#endif +#define PHYDM_SUPPORT_RSSI_MONITOR +#define CFG_DIG_DAMPING_CHK + + +#ifdef BEAMFORMING_SUPPORT + #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT) + #define DRIVER_BEAMFORMING_VERSION2 + #endif +#endif + +#endif diff --git a/hal/phydm/phydm_features_iot.h b/hal/phydm/phydm_features_iot.h new file mode 100644 index 0000000..cee95ef --- /dev/null +++ b/hal/phydm/phydm_features_iot.h @@ -0,0 +1,174 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_IOT_H__ +#define __PHYDM_FEATURES_IOT_H__ + +#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT) + #define PHYDM_LA_MODE_SUPPORT 1 +#else + #define PHYDM_LA_MODE_SUPPORT 0 +#endif + +#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT) + #define FAHM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8822B_SUPPORT) + /*#define PHYDM_PHYSTAUS_SMP_MODE*/ +#endif + +/*#define PHYDM_TDMA_DIG_SUPPORT*/ + +#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_SUPPORT*/ + #ifdef PHYDM_LNA_SAT_CHK_SUPPORT + #if (RTL8197F_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_TYPE2*/ + #endif + #endif +#endif + +#if (RTL8822B_SUPPORT) + #define PHYDM_POWER_TRAINING_SUPPORT +#endif + +#if (RTL8822C_SUPPORT) + /* #define PHYDM_PMAC_TX_SETTING_SUPPORT */ +#endif + +#if (RTL8822C_SUPPORT) + /* #define PHYDM_MP_SUPPORT */ +#endif + +#if (RTL8822B_SUPPORT) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188E_SUPPORT) + #define PHYDM_PRIMARY_CCA +#endif + +#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + #define CONFIG_ADAPTIVE_SOML +#endif + +#if (RTL8822B_SUPPORT) + /*#define CONFIG_DYNAMIC_RX_PATH*/ +#endif + +#if (RTL8822B_SUPPORT == 1) + /* #define CONFIG_8822B_SPUR_CALIBRATION */ +#endif + +#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT) + #define CONFIG_RECEIVER_BLOCKING +#endif + +#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR +#define CONFIG_DYNAMIC_TX_TWR +#endif +#define PHYDM_SUPPORT_CCKPD +#define PHYDM_SUPPORT_ADAPTIVITY + +/*Antenna Diversity*/ +#ifdef CONFIG_ANTENNA_DIVERSITY + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\ + RTL8188F_SUPPORT || RTL8821C_SUPPORT) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8821A_SUPPORT) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ + #endif + #endif +#endif + +/*[SmartAntenna]*/ +/*#define CONFIG_SMART_ANTENNA*/ +#ifdef CONFIG_SMART_ANTENNA + /*#define CONFIG_CUMITEK_SMART_ANTENNA*/ +#endif +/* --------------------------------------------------*/ + +#ifdef CONFIG_DFS_MASTER + #define CONFIG_PHYDM_DFS_MASTER +#endif + +#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\ + RTL8192E_SUPPORT || RTL8723B_SUPPORT) + /*#define CONFIG_RA_FW_DBG_CODE*/ +#endif + +#define CONFIG_PSD_TOOL +/*#define CONFIG_RA_DBG_CMD*/ +/*#define CONFIG_ANT_DETECTION*/ +/*#define CONFIG_PATH_DIVERSITY*/ +/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ +#define CONFIG_BB_TXBF_API +#define CONFIG_PHYDM_DEBUG_FUNCTION + +#ifdef CONFIG_BT_COEXIST + #define ODM_CONFIG_BT_COEXIST +#endif +#define PHYDM_SUPPORT_RSSI_MONITOR +/*#define PHYDM_AUTO_DEGBUG*/ +#define CFG_DIG_DAMPING_CHK + +#ifdef BEAMFORMING_SUPPORT + #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT) + #define DRIVER_BEAMFORMING_VERSION2 + #endif +#endif + +#endif diff --git a/hal/phydm/phydm_features_win.h b/hal/phydm/phydm_features_win.h new file mode 100644 index 0000000..281f01b --- /dev/null +++ b/hal/phydm/phydm_features_win.h @@ -0,0 +1,185 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_WIN_H__ +#define __PHYDM_FEATURES_WIN_H__ + +#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT) + #define PHYDM_LA_MODE_SUPPORT 1 +#else + #define PHYDM_LA_MODE_SUPPORT 0 +#endif + +#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT) + #define FAHM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8822B_SUPPORT) + /*#define PHYDM_PHYSTAUS_SMP_MODE*/ +#endif + +/*#define PHYDM_TDMA_DIG_SUPPORT*/ + +#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT) + /*#define PHYDM_TDMA_DIG_SUPPORT*/ + #ifdef PHYDM_TDMA_DIG_SUPPORT + /*#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/ + #endif +#endif + +#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_SUPPORT*/ + #ifdef PHYDM_LNA_SAT_CHK_SUPPORT + + #if (RTL8197F_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_TYPE2*/ + #endif + + #if (RTL8814B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_TYPE1*/ + #endif + #endif +#endif + +#if (RTL8822B_SUPPORT || RTL8710B_SUPPORT || RTL8723D_SUPPORT ||\ + RTL8192F_SUPPORT) + #define PHYDM_POWER_TRAINING_SUPPORT +#endif + +#if (RTL8822C_SUPPORT) + #define PHYDM_PMAC_TX_SETTING_SUPPORT +#endif + +#if (RTL8822C_SUPPORT) + #define PHYDM_MP_SUPPORT +#endif + +#if (RTL8822B_SUPPORT) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT) + #define PHYDM_PRIMARY_CCA +#endif + +#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8192F_SUPPORT) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + #define CONFIG_ADAPTIVE_SOML +#endif + +#if (RTL8192F_SUPPORT == 1) + #define CONFIG_8912F_SPUR_CALIBRATION +#endif + +#if (RTL8822B_SUPPORT == 1) + /* #define CONFIG_8822B_SPUR_CALIBRATION */ +#endif + +/*Antenna Diversity*/ +#define CONFIG_PHYDM_ANTENNA_DIVERSITY +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT || RTL8821A_SUPPORT || RTL8188F_SUPPORT ||\ + RTL8821C_SUPPORT) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8822B_SUPPORT) + /*#define ODM_EVM_ENHANCE_ANTDIV*/ + /*#define CONFIG_2T3R_ANTENNA*/ + /*#define CONFIG_2T4R_ANTENNA*/ + #endif + + /* --[SmtAnt]-----------------------------------------*/ + #if (RTL8821A_SUPPORT) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #define CONFIG_FAT_PATCH + #endif + + #if (RTL8822B_SUPPORT) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ + #endif + + #if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1) || defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) + #define CONFIG_HL_SMART_ANTENNA + #endif + + /* --------------------------------------------------*/ + +#endif + +/*[SmartAntenna]*/ +#define CONFIG_SMART_ANTENNA +#ifdef CONFIG_SMART_ANTENNA + /*#define CONFIG_CUMITEK_SMART_ANTENNA*/ +#endif + /* --------------------------------------------------*/ + +#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT) + #define CONFIG_RECEIVER_BLOCKING +#endif + +#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\ + RTL8192E_SUPPORT || RTL8723B_SUPPORT) + #define CONFIG_RA_FW_DBG_CODE +#endif + +/* #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR */ +#define CONFIG_DYNAMIC_TX_TWR +/* #endif */ +#define CONFIG_PSD_TOOL +#define PHYDM_SUPPORT_ADAPTIVITY +#define PHYDM_SUPPORT_CCKPD +/*#define CONFIG_PATH_DIVERSITY*/ +/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ +#define CONFIG_ANT_DETECTION +#define CONFIG_BB_TXBF_API +#define ODM_CONFIG_BT_COEXIST +#define CONFIG_PHYDM_DFS_MASTER +#define PHYDM_SUPPORT_RSSI_MONITOR +#define PHYDM_AUTO_DEGBUG +#define CONFIG_PHYDM_DEBUG_FUNCTION +#define CFG_DIG_DAMPING_CHK + +#ifdef BEAMFORMING_SUPPORT + #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\ + RTL8814A_SUPPORT || RTL8881A_SUPPORT) + #define PHYDM_BEAMFORMING_VERSION1 + #endif + #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT) + #define DRIVER_BEAMFORMING_VERSION2 + #endif +#endif + +#endif diff --git a/hal/phydm/phydm_hwconfig.c b/hal/phydm/phydm_hwconfig.c index b5631ad..8c4dfe2 100644 --- a/hal/phydm/phydm_hwconfig.c +++ b/hal/phydm/phydm_hwconfig.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,1974 +8,84 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ - -/* ************************************************************ - * include files - * ************************************************************ */ - -#include "mp_precomp.h" -#include "phydm_precomp.h" - -#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(p_dm_odm)) -#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(p_dm_odm)) - - -#if (PHYDM_TESTCHIP_SUPPORT == 1) -#define READ_AND_CONFIG(ic, txt) do {\ - if (p_dm_odm->is_mp_chip)\ - READ_AND_CONFIG_MP(ic, txt);\ - else\ - READ_AND_CONFIG_TC(ic, txt);\ - } while (0) -#else -#define READ_AND_CONFIG READ_AND_CONFIG_MP -#endif - - -#define READ_FIRMWARE_MP(ic, txt) (odm_read_firmware_mp_##ic##txt(p_dm_odm, p_firmware, p_size)) -#define READ_FIRMWARE_TC(ic, txt) (odm_read_firmware_tc_##ic##txt(p_dm_odm, p_firmware, p_size)) - -#if (PHYDM_TESTCHIP_SUPPORT == 1) -#define READ_FIRMWARE(ic, txt) do {\ - if (p_dm_odm->is_mp_chip)\ - READ_FIRMWARE_MP(ic, txt);\ - else\ - READ_FIRMWARE_TC(ic, txt);\ - } while (0) -#else -#define READ_FIRMWARE READ_FIRMWARE_MP -#endif - -#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt()) -#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt()) - -#if (PHYDM_TESTCHIP_SUPPORT == 1) - #define GET_VERSION(ic, txt) (p_dm_odm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt)) -#else - #define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt) -#endif - -u8 -odm_query_rx_pwr_percentage( - s8 ant_power -) -{ - if ((ant_power <= -100) || (ant_power >= 20)) - return 0; - else if (ant_power >= 0) - return 100; - else - return 100 + ant_power; -} - - -/* - * 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. - * IF other SW team do not support the feature, remove this section.?? - * */ -s32 -odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_lenovo( - struct PHY_DM_STRUCT *p_dm_odm, - s32 curr_sig -) -{ - s32 ret_sig = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* if(p_dm_odm->support_interface == ODM_ITRF_PCIE) */ - { - /* step 1. Scale mapping. */ - /* 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. */ - /* 20100426 Joseph: Modify Signal strength mapping. */ - /* This modification makes the RSSI indication similar to Intel solution. */ - /* 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. */ - if (curr_sig >= 54 && curr_sig <= 100) - ret_sig = 100; - else if (curr_sig >= 42 && curr_sig <= 53) - ret_sig = 95; - else if (curr_sig >= 36 && curr_sig <= 41) - ret_sig = 74 + ((curr_sig - 36) * 20) / 6; - else if (curr_sig >= 33 && curr_sig <= 35) - ret_sig = 65 + ((curr_sig - 33) * 8) / 2; - else if (curr_sig >= 18 && curr_sig <= 32) - ret_sig = 62 + ((curr_sig - 18) * 2) / 15; - else if (curr_sig >= 15 && curr_sig <= 17) - ret_sig = 33 + ((curr_sig - 15) * 28) / 2; - else if (curr_sig >= 10 && curr_sig <= 14) - ret_sig = 39; - else if (curr_sig >= 8 && curr_sig <= 9) - ret_sig = 33; - else if (curr_sig <= 8) - ret_sig = 19; - } -#endif /* ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ - return ret_sig; -} - -s32 -odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_netcore( - struct PHY_DM_STRUCT *p_dm_odm, - s32 curr_sig -) -{ - s32 ret_sig = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* if(p_dm_odm->support_interface == ODM_ITRF_USB) */ - { - /* Netcore request this modification because 2009.04.13 SU driver use it. */ - if (curr_sig >= 31 && curr_sig <= 100) - ret_sig = 100; - else if (curr_sig >= 21 && curr_sig <= 30) - ret_sig = 90 + ((curr_sig - 20) / 1); - else if (curr_sig >= 11 && curr_sig <= 20) - ret_sig = 80 + ((curr_sig - 10) / 1); - else if (curr_sig >= 7 && curr_sig <= 10) - ret_sig = 69 + (curr_sig - 7); - else if (curr_sig == 6) - ret_sig = 54; - else if (curr_sig == 5) - ret_sig = 45; - else if (curr_sig == 4) - ret_sig = 36; - else if (curr_sig == 3) - ret_sig = 27; - else if (curr_sig == 2) - ret_sig = 18; - else if (curr_sig == 1) - ret_sig = 9; - else - ret_sig = curr_sig; - } -#endif /* ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ - return ret_sig; -} - - -s32 -odm_signal_scale_mapping_92c_series( - struct PHY_DM_STRUCT *p_dm_odm, - s32 curr_sig -) -{ - s32 ret_sig = 0; -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) { - /* step 1. Scale mapping. */ - if (curr_sig >= 61 && curr_sig <= 100) - ret_sig = 90 + ((curr_sig - 60) / 4); - else if (curr_sig >= 41 && curr_sig <= 60) - ret_sig = 78 + ((curr_sig - 40) / 2); - else if (curr_sig >= 31 && curr_sig <= 40) - ret_sig = 66 + (curr_sig - 30); - else if (curr_sig >= 21 && curr_sig <= 30) - ret_sig = 54 + (curr_sig - 20); - else if (curr_sig >= 5 && curr_sig <= 20) - ret_sig = 42 + (((curr_sig - 5) * 2) / 3); - else if (curr_sig == 4) - ret_sig = 36; - else if (curr_sig == 3) - ret_sig = 27; - else if (curr_sig == 2) - ret_sig = 18; - else if (curr_sig == 1) - ret_sig = 9; - else - ret_sig = curr_sig; - } -#endif - -#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - if ((p_dm_odm->support_interface == ODM_ITRF_USB) || (p_dm_odm->support_interface == ODM_ITRF_SDIO)) { - if (curr_sig >= 51 && curr_sig <= 100) - ret_sig = 100; - else if (curr_sig >= 41 && curr_sig <= 50) - ret_sig = 80 + ((curr_sig - 40) * 2); - else if (curr_sig >= 31 && curr_sig <= 40) - ret_sig = 66 + (curr_sig - 30); - else if (curr_sig >= 21 && curr_sig <= 30) - ret_sig = 54 + (curr_sig - 20); - else if (curr_sig >= 10 && curr_sig <= 20) - ret_sig = 42 + (((curr_sig - 10) * 2) / 3); - else if (curr_sig >= 5 && curr_sig <= 9) - ret_sig = 22 + (((curr_sig - 5) * 3) / 2); - else if (curr_sig >= 1 && curr_sig <= 4) - ret_sig = 6 + (((curr_sig - 1) * 3) / 2); - else - ret_sig = curr_sig; - } - -#endif - return ret_sig; -} -s32 -odm_signal_scale_mapping( - struct PHY_DM_STRUCT *p_dm_odm, - s32 curr_sig -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->support_interface != ODM_ITRF_PCIE) && /* USB & SDIO */ - (p_dm_odm->patch_id == 10)) /* p_mgnt_info->customer_id == RT_CID_819x_Netcore */ - return odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_netcore(p_dm_odm, curr_sig); - else if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->support_interface == ODM_ITRF_PCIE) && - (p_dm_odm->patch_id == 19)) /* p_mgnt_info->customer_id == RT_CID_819X_LENOVO) */ - return odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_lenovo(p_dm_odm, curr_sig); - else -#endif - { -#ifdef CONFIG_SIGNAL_SCALE_MAPPING - return odm_signal_scale_mapping_92c_series(p_dm_odm, curr_sig); -#else - return curr_sig; -#endif - } - -} - - - -static u8 odm_sq_process_patch_rt_cid_819x_lenovo( - struct PHY_DM_STRUCT *p_dm_odm, - u8 is_cck_rate, - u8 PWDB_ALL, - u8 path, - u8 RSSI -) -{ - u8 SQ = 0; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - if (is_cck_rate) { - - if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) { - - /* */ - /* Expected signal strength and bars indication at Lenovo lab. 2013.04.11 */ - /* 802.11n, 802.11b, 802.11g only at channel 6 */ - /* */ - /* Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) */ - /* 50 5 -49 */ - /* 55 5 -49 */ - /* 60 5 -50 */ - /* 65 5 -51 */ - /* 70 5 -52 */ - /* 75 5 -54 */ - /* 80 5 -55 */ - /* 85 4 -60 */ - /* 90 3 -63 */ - /* 95 3 -65 */ - /* 100 2 -67 */ - /* 102 2 -67 */ - /* 104 1 -70 */ - /* */ - - if (PWDB_ALL >= 50) - SQ = 100; - else if (PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if (PWDB_ALL >= 31 && PWDB_ALL < 35) - SQ = 60; - else if (PWDB_ALL >= 22 && PWDB_ALL < 31) - SQ = 40; - else if (PWDB_ALL >= 18 && PWDB_ALL < 22) - SQ = 20; - else - SQ = 10; - } else { - if (PWDB_ALL >= 50) - SQ = 100; - else if (PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if (PWDB_ALL >= 22 && PWDB_ALL < 35) - SQ = 60; - else if (PWDB_ALL >= 18 && PWDB_ALL < 22) - SQ = 40; - else - SQ = 10; - } - - } else { - /* OFDM rate */ - - if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) { - if (RSSI >= 45) - SQ = 100; - else if (RSSI >= 22 && RSSI < 45) - SQ = 80; - else if (RSSI >= 18 && RSSI < 22) - SQ = 40; - else - SQ = 20; - } else { - if (RSSI >= 45) - SQ = 100; - else if (RSSI >= 22 && RSSI < 45) - SQ = 80; - else if (RSSI >= 18 && RSSI < 22) - SQ = 40; - else - SQ = 20; - } - } - - RT_TRACE(COMP_DBG, DBG_TRACE, ("is_cck_rate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", is_cck_rate, PWDB_ALL, RSSI, SQ)); - -#endif - return SQ; -} - -static u8 odm_sq_process_patch_rt_cid_819x_acer( - struct PHY_DM_STRUCT *p_dm_odm, - u8 is_cck_rate, - u8 PWDB_ALL, - u8 path, - u8 RSSI -) -{ - u8 SQ = 0; - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - - if (is_cck_rate) { - - RT_TRACE(COMP_DBG, DBG_WARNING, ("odm_SQ_process_patch_RT_Acer\n")); - -#if OS_WIN_FROM_WIN8(OS_VERSION) - - if (PWDB_ALL >= 50) - SQ = 100; - else if (PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if (PWDB_ALL >= 30 && PWDB_ALL < 35) - SQ = 60; - else if (PWDB_ALL >= 25 && PWDB_ALL < 30) - SQ = 40; - else if (PWDB_ALL >= 20 && PWDB_ALL < 25) - SQ = 20; - else - SQ = 10; -#else - if (PWDB_ALL >= 50) - SQ = 100; - else if (PWDB_ALL >= 35 && PWDB_ALL < 50) - SQ = 80; - else if (PWDB_ALL >= 30 && PWDB_ALL < 35) - SQ = 60; - else if (PWDB_ALL >= 25 && PWDB_ALL < 30) - SQ = 40; - else if (PWDB_ALL >= 20 && PWDB_ALL < 25) - SQ = 20; - else - SQ = 10; - - if (PWDB_ALL == 0) /* Abnormal case, do not indicate the value above 20 on Win7 */ - SQ = 20; -#endif - - - - } else { - /* OFDM rate */ - - if (IS_HARDWARE_TYPE_8192E(p_dm_odm->adapter)) { - if (RSSI >= 45) - SQ = 100; - else if (RSSI >= 22 && RSSI < 45) - SQ = 80; - else if (RSSI >= 18 && RSSI < 22) - SQ = 40; - else - SQ = 20; - } else { - if (RSSI >= 35) - SQ = 100; - else if (RSSI >= 30 && RSSI < 35) - SQ = 80; - else if (RSSI >= 25 && RSSI < 30) - SQ = 40; - else - SQ = 20; - } - } - - RT_TRACE(COMP_DBG, DBG_LOUD, ("is_cck_rate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", is_cck_rate, PWDB_ALL, RSSI, SQ)); - -#endif - return SQ; -} - -static u8 -odm_evm_db_to_percentage( - s8 value -) -{ - /* */ - /* -33dB~0dB to 0%~99% */ - /* */ - s8 ret_val; - - ret_val = value; - ret_val /= 2; - - /*dbg_print("value=%d\n", value);*/ - /*ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C value=%d / %x\n", ret_val, ret_val));*/ -#ifdef ODM_EVM_ENHANCE_ANTDIV - if (ret_val >= 0) - ret_val = 0; - - if (ret_val <= -40) - ret_val = -40; - - ret_val = 0 - ret_val; - ret_val *= 3; -#else - if (ret_val >= 0) - ret_val = 0; - - if (ret_val <= -33) - ret_val = -33; - - ret_val = 0 - ret_val; - ret_val *= 3; - - if (ret_val == 99) - ret_val = 100; -#endif - - return (u8)ret_val; -} - -static u8 -odm_evm_dbm_jaguar_series( - s8 value -) -{ - s8 ret_val = value; - - /* -33dB~0dB to 33dB ~ 0dB */ - if (ret_val == -128) - ret_val = 127; - else if (ret_val < 0) - ret_val = 0 - ret_val; - - ret_val = ret_val >> 1; - return (u8)ret_val; -} - -static s16 -odm_cfo( - s8 value -) -{ - s16 ret_val; - - if (value < 0) { - ret_val = 0 - value; - ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */ - ret_val = ret_val | BIT(12); /* set bit12 as 1 for negative cfo */ - } else { - ret_val = value; - ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */ - } - return ret_val; -} - -u8 -phydm_rate_to_num_ss( - struct PHY_DM_STRUCT *p_dm_odm, - u8 data_rate -) -{ - u8 num_ss = 1; - - if (data_rate <= ODM_RATE54M) - num_ss = 1; - else if (data_rate <= ODM_RATEMCS31) - num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1; - else if (data_rate <= ODM_RATEVHTSS1MCS9) - num_ss = 1; - else if (data_rate <= ODM_RATEVHTSS2MCS9) - num_ss = 2; - else if (data_rate <= ODM_RATEVHTSS3MCS9) - num_ss = 3; - else if (data_rate <= ODM_RATEVHTSS4MCS9) - num_ss = 4; - - return num_ss; -} - -#if (ODM_IC_11N_SERIES_SUPPORT == 1) - -#if (RTL8703B_SUPPORT == 1) -s8 -odm_CCKRSSI_8703B( - u16 LNA_idx, - u8 VGA_idx -) -{ - s8 rx_pwr_all = 0x00; - - switch (LNA_idx) { - case 0xf: - rx_pwr_all = -48 - (2 * VGA_idx); - break; - case 0xb: - rx_pwr_all = -42 - (2 * VGA_idx); /*TBD*/ - break; - case 0xa: - rx_pwr_all = -36 - (2 * VGA_idx); - break; - case 8: - rx_pwr_all = -32 - (2 * VGA_idx); - break; - case 7: - rx_pwr_all = -19 - (2 * VGA_idx); - break; - case 4: - rx_pwr_all = -6 - (2 * VGA_idx); - break; - case 0: - rx_pwr_all = -2 - (2 * VGA_idx); - break; - default: - /*rx_pwr_all = -53+(2*(31-VGA_idx));*/ - /*dbg_print("wrong LNA index\n");*/ - break; - - } - return rx_pwr_all; -} -#endif - -#if (RTL8195A_SUPPORT == 1) -s8 -odm_CCKRSSI_8195A( - struct PHY_DM_STRUCT *p_dm_odm, - u16 LNA_idx, - u8 VGA_idx -) -{ - s8 rx_pwr_all = 0; - s8 lna_gain = 0; - s8 lna_gain_table_0[8] = {0, -8, -15, -22, -29, -36, -45, -54}; - s8 lna_gain_table_1[8] = {0, -8, -15, -22, -29, -36, -45, -54};/*use 8195A to calibrate this table. 2016.06.24, Dino*/ - - if (p_dm_odm->cck_agc_report_type == 0) - lna_gain = lna_gain_table_0[LNA_idx]; - else - lna_gain = lna_gain_table_1[LNA_idx]; - - rx_pwr_all = lna_gain - (2 * VGA_idx); - - return rx_pwr_all; -} -#endif - -#if (RTL8192E_SUPPORT == 1) -s8 -odm_CCKRSSI_8192E( - struct PHY_DM_STRUCT *p_dm_odm, - u16 LNA_idx, - u8 VGA_idx -) -{ - s8 rx_pwr_all = 0; - s8 lna_gain = 0; - s8 lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44}; - s8 lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36};/*use 8192EU to calibrate this table. 2015.12.15, Dino*/ - - if (p_dm_odm->cck_agc_report_type == 0) - lna_gain = lna_gain_table_0[LNA_idx]; - else - lna_gain = lna_gain_table_1[LNA_idx]; - - rx_pwr_all = lna_gain - (2 * VGA_idx); - - return rx_pwr_all; -} -#endif - -#if (RTL8188E_SUPPORT == 1) -s8 -odm_CCKRSSI_8188E( - struct PHY_DM_STRUCT *p_dm_odm, - u16 LNA_idx, - u8 VGA_idx -) -{ - s8 rx_pwr_all = 0; - s8 lna_gain = 0; - s8 lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41};/*only use lna0/1/2/3/7*/ - s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; /*only use lna3 /7*/ - - if (p_dm_odm->cut_version >= ODM_CUT_I) /*SMIC*/ - lna_gain = lna_gain_table_0[LNA_idx]; - else /*TSMC*/ - lna_gain = lna_gain_table_1[LNA_idx]; - - rx_pwr_all = lna_gain - (2 * VGA_idx); - - return rx_pwr_all; -} -#endif - -void -odm_rx_phy_status92c_series_parsing( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; - u8 i, max_spatial_stream; - s8 rx_pwr[4], rx_pwr_all = 0; - u8 EVM, PWDB_ALL = 0, PWDB_ALL_BT; - u8 RSSI, total_rssi = 0; - boolean is_cck_rate = false; - u8 rf_rx_num = 0; - u8 cck_highpwr = 0; - u8 LNA_idx = 0; - u8 VGA_idx = 0; - u8 cck_agc_rpt; - u8 num_ss; - struct _phy_status_rpt_8192cd *p_phy_sta_rpt = (struct _phy_status_rpt_8192cd *)p_phy_status; - - is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false; - - if (p_pktinfo->is_to_self) - p_dm_odm->curr_station_id = p_pktinfo->station_id; - - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; - - - if (is_cck_rate) { - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++; - cck_agc_rpt = p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a ; - - if (p_dm_odm->support_ic_type & (ODM_RTL8703B)) { - -#if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->cck_agc_report_type == 1) { /*4 bit LNA*/ - - u8 cck_agc_rpt_b = (p_phy_sta_rpt->cck_rpt_b_ofdm_cfosho_b & BIT(7)) ? 1 : 0; - - LNA_idx = (cck_agc_rpt_b << 3) | ((cck_agc_rpt & 0xE0) >> 5); - VGA_idx = (cck_agc_rpt & 0x1F); - - rx_pwr_all = odm_CCKRSSI_8703B(LNA_idx, VGA_idx); - } -#endif - } else { /*3 bit LNA*/ - - LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); - VGA_idx = (cck_agc_rpt & 0x1F); - - if (p_dm_odm->support_ic_type & (ODM_RTL8188E)) { - -#if (RTL8188E_SUPPORT == 1) - rx_pwr_all = odm_CCKRSSI_8188E(p_dm_odm, LNA_idx, VGA_idx); - /**/ -#endif - } -#if (RTL8192E_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { - - rx_pwr_all = odm_CCKRSSI_8192E(p_dm_odm, LNA_idx, VGA_idx); - /**/ - } -#endif -#if (RTL8723B_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & (ODM_RTL8723B)) { - - rx_pwr_all = odm_CCKRSSI_8723B(LNA_idx, VGA_idx); - /**/ - } -#endif -#if (RTL8188F_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & (ODM_RTL8188F)) { - - rx_pwr_all = odm_CCKRSSI_8188F(LNA_idx, VGA_idx); - /**/ - } -#endif -#if (RTL8195A_SUPPORT == 1) - else if (p_dm_odm->support_ic_type & (ODM_RTL8195A)) { - - rx_pwr_all = odm_CCKRSSI_8195A(LNA_idx, VGA_idx); - /**/ - } -#endif - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ext_lna_gain (( %d )), LNA_idx: (( 0x%x )), VGA_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n", - p_dm_odm->ext_lna_gain, LNA_idx, VGA_idx, rx_pwr_all)); - - if (p_dm_odm->board_type & ODM_BOARD_EXT_LNA) - rx_pwr_all -= p_dm_odm->ext_lna_gain; - - PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - - if (p_pktinfo->is_to_self) { - p_dm_odm->cck_lna_idx = LNA_idx; - p_dm_odm->cck_vga_idx = VGA_idx; - } - p_phy_info->rx_pwdb_all = PWDB_ALL; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->bt_rx_rssi_percentage = PWDB_ALL; - p_phy_info->recv_signal_power = rx_pwr_all; -#endif - /* */ - /* (3) Get Signal Quality (EVM) */ - /* */ - /* if(p_pktinfo->is_packet_match_bssid) */ - { - u8 SQ, SQ_rpt; - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) - SQ = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0); - else if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_ACER)) - SQ = odm_sq_process_patch_rt_cid_819x_acer(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0); - else -#endif - if (p_phy_info->rx_pwdb_all > 40 && !p_dm_odm->is_in_hct_test) - SQ = 100; - else { - SQ_rpt = p_phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all; - - if (SQ_rpt > 64) - SQ = 0; - else if (SQ_rpt < 20) - SQ = 100; - else - SQ = ((64 - SQ_rpt) * 100) / 44; - - } - - /* dbg_print("cck SQ = %d\n", SQ); */ - p_phy_info->signal_quality = SQ; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = SQ; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; - } - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) { - if (i == 0) - p_phy_info->rx_mimo_signal_strength[0] = PWDB_ALL; - else - p_phy_info->rx_mimo_signal_strength[1] = 0; - } - } else { /* 2 is OFDM rate */ - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; - - /* */ - /* (1)Get RSSI for HT rate */ - /* */ - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) { - /* 2008/01/30 MH we will judge RF RX path now. */ - if (p_dm_odm->rf_path_rx_enable & BIT(i)) - rf_rx_num++; - /* else */ - /* continue; */ - - rx_pwr[i] = ((p_phy_sta_rpt->path_agc[i].gain & 0x3F) * 2) - 110; - - if (p_pktinfo->is_to_self) { - p_dm_odm->ofdm_agc_idx[i] = (p_phy_sta_rpt->path_agc[i].gain & 0x3F); - /**/ - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->rx_pwr[i] = rx_pwr[i]; -#endif - - /* Translate DBM to percentage. */ - RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]); - total_rssi += RSSI; - /* RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); */ - - p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI; - -#if (DM_ODM_SUPPORT_TYPE & (/*ODM_WIN|*/ODM_CE|ODM_AP)) - /* Get Rx snr value in DB */ - p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = (s32)(p_phy_sta_rpt->path_rxsnr[i] / 2); -#endif - - /* Record Signal Strength for next packet */ - /* if(p_pktinfo->is_packet_match_bssid) */ - { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) { - if (i == ODM_RF_PATH_A) - p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, i, RSSI); - - } else if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_ACER)) - p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_acer(p_dm_odm, is_cck_rate, PWDB_ALL, 0, RSSI); -#endif - } - } - - - /* */ - /* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */ - /* */ - rx_pwr_all = (((p_phy_sta_rpt->cck_sig_qual_ofdm_pwdb_all) >> 1) & 0x7f) - 110; - - PWDB_ALL_BT = PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - - - p_phy_info->rx_pwdb_all = PWDB_ALL; - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all)); */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->bt_rx_rssi_percentage = PWDB_ALL_BT; - p_phy_info->rx_power = rx_pwr_all; - p_phy_info->recv_signal_power = rx_pwr_all; -#endif - - if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 19)) { - /* do nothing */ - } else if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 25)) { - /* do nothing */ - } else { /* p_mgnt_info->customer_id != RT_CID_819X_LENOVO */ - /* */ - /* (3)EVM of HT rate */ - /* */ - if (p_pktinfo->data_rate >= ODM_RATEMCS8 && p_pktinfo->data_rate <= ODM_RATEMCS15) - max_spatial_stream = 2; /* both spatial stream make sense */ - else - max_spatial_stream = 1; /* only spatial stream 1 makes sense */ - - for (i = 0; i < max_spatial_stream; i++) { - /* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */ - /* fill most significant bit to "zero" when doing shifting operation which may change a negative */ - /* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */ - EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->stream_rxevm[i])); /* dbm */ - - /* GET_RX_STATUS_DESC_RX_MCS(p_desc), p_drv_info->rxevm[i], "%", EVM)); */ - - /* if(p_pktinfo->is_packet_match_bssid) */ - { - if (i == ODM_RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */ - p_phy_info->signal_quality = (u8)(EVM & 0xff); - p_phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff); - } - } - } - - num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->path_cfotail, num_ss); - - } -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - /* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */ - /* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */ - if (is_cck_rate) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */ - p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, PWDB_ALL, true, true); -#else - p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, PWDB_ALL));/*PWDB_ALL;*/ -#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ - } else { - if (rf_rx_num != 0) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ */ - p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, (total_rssi /= rf_rx_num), true, false); -#else - p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, total_rssi /= rf_rx_num)); -#endif - } - } -#endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))*/ - - /* dbg_print("is_cck_rate = %d, p_phy_info->rx_pwdb_all = %d, p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a = 0x%x\n", */ - /* is_cck_rate, p_phy_info->rx_pwdb_all, p_phy_sta_rpt->cck_agc_rpt_ofdm_cfosho_a); */ - - /* For 92C/92D HW (Hybrid) Antenna Diversity */ -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - /* For 88E HW Antenna Diversity */ - p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->ant_sel; - p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->ant_sel_b; - p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antsel_rx_keep_2; -#endif -} -#endif - -#if ODM_IC_11AC_SERIES_SUPPORT - -void -odm_rx_phy_bw_jaguar_series_parsing( - struct _odm_phy_status_info_ *p_phy_info, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _phy_status_rpt_8812 *p_phy_sta_rpt -) -{ - - if (p_pktinfo->data_rate <= ODM_RATE54M) { - switch (p_phy_sta_rpt->r_RFMOD) { - case 1: - if (p_phy_sta_rpt->sub_chnl == 0) - p_phy_info->band_width = 1; - else - p_phy_info->band_width = 0; - break; - - case 2: - if (p_phy_sta_rpt->sub_chnl == 0) - p_phy_info->band_width = 2; - else if (p_phy_sta_rpt->sub_chnl == 9 || p_phy_sta_rpt->sub_chnl == 10) - p_phy_info->band_width = 1; - else - p_phy_info->band_width = 0; - break; - - default: - case 0: - p_phy_info->band_width = 0; - break; - } - } - -} - -void -odm_rx_phy_status_jaguar_series_parsing( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - u8 i, max_spatial_stream; - s8 rx_pwr[4], rx_pwr_all = 0; - u8 EVM, evm_dbm, PWDB_ALL = 0, PWDB_ALL_BT; - u8 RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0; - u8 is_cck_rate = 0; - u8 rf_rx_num = 0; - u8 cck_highpwr = 0; - u8 LNA_idx, VGA_idx; - struct _phy_status_rpt_8812 *p_phy_sta_rpt = (struct _phy_status_rpt_8812 *)p_phy_status; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - u8 num_ss; - - odm_rx_phy_bw_jaguar_series_parsing(p_phy_info, p_pktinfo, p_phy_sta_rpt); - - if (p_pktinfo->data_rate <= ODM_RATE11M) - is_cck_rate = true; - else - is_cck_rate = false; - - if (p_pktinfo->is_to_self) - p_dm_odm->curr_station_id = p_pktinfo->station_id; - else - p_dm_odm->curr_station_id = 0xff; - - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_C] = -1; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_D] = -1; - - if (is_cck_rate) { - u8 cck_agc_rpt; - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++; - - /*(1)Hardware does not provide RSSI for CCK*/ - /*(2)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ - - /*if(p_hal_data->e_rf_power_state == e_rf_on)*/ - cck_highpwr = p_dm_odm->is_cck_high_power; - /*else*/ - /*cck_highpwr = false;*/ - - cck_agc_rpt = p_phy_sta_rpt->cfosho[0] ; - LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); - VGA_idx = (cck_agc_rpt & 0x1F); - - if (p_dm_odm->support_ic_type == ODM_RTL8812) { - switch (LNA_idx) { - case 7: - if (VGA_idx <= 27) - rx_pwr_all = -100 + 2 * (27 - VGA_idx); /*VGA_idx = 27~2*/ - else - rx_pwr_all = -100; - break; - case 6: - rx_pwr_all = -48 + 2 * (2 - VGA_idx); /*VGA_idx = 2~0*/ - break; - case 5: - rx_pwr_all = -42 + 2 * (7 - VGA_idx); /*VGA_idx = 7~5*/ - break; - case 4: - rx_pwr_all = -36 + 2 * (7 - VGA_idx); /*VGA_idx = 7~4*/ - break; - case 3: - /*rx_pwr_all = -28 + 2*(7-VGA_idx); VGA_idx = 7~0*/ - rx_pwr_all = -24 + 2 * (7 - VGA_idx); /*VGA_idx = 7~0*/ - break; - case 2: - if (cck_highpwr) - rx_pwr_all = -12 + 2 * (5 - VGA_idx); /*VGA_idx = 5~0*/ - else - rx_pwr_all = -6 + 2 * (5 - VGA_idx); - break; - case 1: - rx_pwr_all = 8 - 2 * VGA_idx; - break; - case 0: - rx_pwr_all = 14 - 2 * VGA_idx; - break; - default: - /*dbg_print("CCK Exception default\n");*/ - break; - } - rx_pwr_all += 6; - PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - - if (cck_highpwr == false) { - if (PWDB_ALL >= 80) - PWDB_ALL = ((PWDB_ALL - 80) << 1) + ((PWDB_ALL - 80) >> 1) + 80; - else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20)) - PWDB_ALL += 3; - if (PWDB_ALL > 100) - PWDB_ALL = 100; - } - } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { - s8 pout = -6; - - switch (LNA_idx) { - case 5: - rx_pwr_all = pout - 32 - (2 * VGA_idx); - break; - case 4: - rx_pwr_all = pout - 24 - (2 * VGA_idx); - break; - case 2: - rx_pwr_all = pout - 11 - (2 * VGA_idx); - break; - case 1: - rx_pwr_all = pout + 5 - (2 * VGA_idx); - break; - case 0: - rx_pwr_all = pout + 21 - (2 * VGA_idx); - break; - } - PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - } else if (p_dm_odm->support_ic_type == ODM_RTL8814A || p_dm_odm->support_ic_type == ODM_RTL8822B) { - s8 pout = -6; - - switch (LNA_idx) { - /*CCK only use LNA: 2, 3, 5, 7*/ - case 7: - rx_pwr_all = pout - 32 - (2 * VGA_idx); - break; - case 5: - rx_pwr_all = pout - 22 - (2 * VGA_idx); - break; - case 3: - rx_pwr_all = pout - 2 - (2 * VGA_idx); - break; - case 2: - rx_pwr_all = pout + 5 - (2 * VGA_idx); - break; - /*case 6:*/ - /*rx_pwr_all = pout -26 - (2*VGA_idx);*/ - /*break;*/ - /*case 4:*/ - /*rx_pwr_all = pout - 8 - (2*VGA_idx);*/ - /*break;*/ - /*case 1:*/ - /*rx_pwr_all = pout + 21 - (2*VGA_idx);*/ - /*break;*/ - /*case 0:*/ - /*rx_pwr_all = pout + 10 - (2*VGA_idx);*/ - /* break; */ - default: - /* dbg_print("CCK Exception default\n"); */ - break; - } - PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - } - - p_dm_odm->cck_lna_idx = LNA_idx; - p_dm_odm->cck_vga_idx = VGA_idx; - p_phy_info->rx_pwdb_all = PWDB_ALL; - /* if(p_pktinfo->station_id == 0) */ - /* { */ - /* dbg_print("CCK: LNA_idx = %d, VGA_idx = %d, p_phy_info->rx_pwdb_all = %d\n", */ - /* LNA_idx, VGA_idx, p_phy_info->rx_pwdb_all); */ - /* } */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->bt_rx_rssi_percentage = PWDB_ALL; - p_phy_info->recv_signal_power = rx_pwr_all; -#endif - /*(3) Get Signal Quality (EVM)*/ - /*if (p_pktinfo->is_packet_match_bssid)*/ - { - u8 SQ, SQ_rpt; - - if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) - SQ = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, 0, 0); - else if (p_phy_info->rx_pwdb_all > 40 && !p_dm_odm->is_in_hct_test) - SQ = 100; - else { - SQ_rpt = p_phy_sta_rpt->pwdb_all; - - if (SQ_rpt > 64) - SQ = 0; - else if (SQ_rpt < 20) - SQ = 100; - else - SQ = ((64 - SQ_rpt) * 100) / 44; - } - - /* dbg_print("cck SQ = %d\n", SQ); */ - p_phy_info->signal_quality = SQ; - p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = SQ; - } - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (i == 0) - p_phy_info->rx_mimo_signal_strength[0] = PWDB_ALL; - else - p_phy_info->rx_mimo_signal_strength[i] = 0; - } - } else { - /*is OFDM rate*/ - p_dm_fat_table->hw_antsw_occur = p_phy_sta_rpt->hw_antsw_occur; - - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; - - /*(1)Get RSSI for OFDM rate*/ - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - /*2008/01/30 MH we will judge RF RX path now.*/ - /* dbg_print("p_dm_odm->rf_path_rx_enable = %x\n", p_dm_odm->rf_path_rx_enable); */ - if (p_dm_odm->rf_path_rx_enable & BIT(i)) - rf_rx_num++; - /* else */ - /* continue; */ - /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ - /* if((p_dm_odm->support_ic_type & (ODM_RTL8812|ODM_RTL8821)) && (!p_dm_odm->is_mp_chip)) */ - if (i < ODM_RF_PATH_C) - rx_pwr[i] = (p_phy_sta_rpt->gain_trsw[i] & 0x7F) - 110; - else - rx_pwr[i] = (p_phy_sta_rpt->gain_trsw_cd[i - 2] & 0x7F) - 110; - /* else */ - /*rx_pwr[i] = ((p_phy_sta_rpt->gain_trsw[i]& 0x3F)*2) - 110; OLD FORMULA*/ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->rx_pwr[i] = rx_pwr[i]; -#endif - - /* Translate DBM to percentage. */ - RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]); - - /*total_rssi += RSSI;*/ - /*Get the best two RSSI*/ - if (RSSI > best_rssi && RSSI > second_rssi) { - second_rssi = best_rssi; - best_rssi = RSSI; - } else if (RSSI > second_rssi && RSSI <= best_rssi) - second_rssi = RSSI; - - /*RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI));*/ - - p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI; - - - /*Get Rx snr value in DB*/ - if (i < ODM_RF_PATH_C) - p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->rxsnr[i] / 2; - else if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) - p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->csi_current[i - 2] / 2; - -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - /*(2) CFO_short & CFO_tail*/ - if (i < ODM_RF_PATH_C) { - p_phy_info->cfo_short[i] = odm_cfo((p_phy_sta_rpt->cfosho[i])); - p_phy_info->cfo_tail[i] = odm_cfo((p_phy_sta_rpt->cfotail[i])); - } -#endif - /* Record Signal Strength for next packet */ - if (p_pktinfo->is_packet_match_bssid) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if ((p_dm_odm->support_platform == ODM_WIN) && - (p_dm_odm->patch_id == RT_CID_819X_LENOVO)) { - if (i == ODM_RF_PATH_A) - p_phy_info->signal_quality = odm_sq_process_patch_rt_cid_819x_lenovo(p_dm_odm, is_cck_rate, PWDB_ALL, i, RSSI); - - } -#endif - } - } - - /*(3)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ - - /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ - if ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) && (!p_dm_odm->is_mp_chip)) - rx_pwr_all = (p_phy_sta_rpt->pwdb_all & 0x7f) - 110; - else - rx_pwr_all = (((p_phy_sta_rpt->pwdb_all) >> 1) & 0x7f) - 110; /*OLD FORMULA*/ - - PWDB_ALL_BT = PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); - - p_phy_info->rx_pwdb_all = PWDB_ALL; - /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all));*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->bt_rx_rssi_percentage = PWDB_ALL_BT; - p_phy_info->rx_power = rx_pwr_all; - p_phy_info->recv_signal_power = rx_pwr_all; -#endif - - if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 19)) { - /*do nothing*/ - } else { - /*p_mgnt_info->customer_id != RT_CID_819X_LENOVO*/ - - /*(4)EVM of OFDM rate*/ - - if ((p_pktinfo->data_rate >= ODM_RATEMCS8) && - (p_pktinfo->data_rate <= ODM_RATEMCS15)) - max_spatial_stream = 2; - else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS2MCS0) && - (p_pktinfo->data_rate <= ODM_RATEVHTSS2MCS9)) - max_spatial_stream = 2; - else if ((p_pktinfo->data_rate >= ODM_RATEMCS16) && - (p_pktinfo->data_rate <= ODM_RATEMCS23)) - max_spatial_stream = 3; - else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS3MCS0) && - (p_pktinfo->data_rate <= ODM_RATEVHTSS3MCS9)) - max_spatial_stream = 3; - else - max_spatial_stream = 1; - - /*if (p_pktinfo->is_packet_match_bssid) */ - { - /*dbg_print("p_pktinfo->data_rate = %d\n", p_pktinfo->data_rate);*/ - - for (i = 0; i < max_spatial_stream; i++) { - /*Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment*/ - /*fill most significant bit to "zero" when doing shifting operation which may change a negative*/ - /*value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.*/ - - if (p_pktinfo->data_rate >= ODM_RATE6M && p_pktinfo->data_rate <= ODM_RATE54M) { - if (i == ODM_RF_PATH_A) { - EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->sigevm)); /*dbm*/ - EVM += 20; - if (EVM > 100) - EVM = 100; - } - } else { - if (i < ODM_RF_PATH_C) { - if (p_phy_sta_rpt->rxevm[i] == -128) - p_phy_sta_rpt->rxevm[i] = -25; - EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->rxevm[i])); /*dbm*/ - } else { - if (p_phy_sta_rpt->rxevm_cd[i - 2] == -128) - p_phy_sta_rpt->rxevm_cd[i - 2] = -25; - EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->rxevm_cd[i - 2])); /*dbm*/ - } - } - - if (i < ODM_RF_PATH_C) - evm_dbm = odm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm[i]); - else - evm_dbm = odm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm_cd[i - 2]); - /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/ - /*p_pktinfo->data_rate, p_phy_sta_rpt->rxevm[i], "%", EVM));*/ - - { - if (i == ODM_RF_PATH_A) { - /*Fill value in RFD, Get the first spatial stream only*/ - p_phy_info->signal_quality = EVM; - } - p_phy_info->rx_mimo_signal_quality[i] = EVM; -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) - p_phy_info->rx_mimo_evm_dbm[i] = evm_dbm; -#endif - } - } - } - } - - num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->cfotail, num_ss); - - } - /* dbg_print("is_cck_rate= %d, p_phy_info->signal_strength=%d % PWDB_AL=%d rf_rx_num=%d\n", is_cck_rate, p_phy_info->signal_strength, PWDB_ALL, rf_rx_num); */ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - /*UI BSS List signal strength(in percentage), make it good looking, from 0~100.*/ - /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/ - if (is_cck_rate) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /*2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ - p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, PWDB_ALL, false, true); -#else - p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, PWDB_ALL));/*PWDB_ALL;*/ -#endif - } else { - if (rf_rx_num != 0) { - /* 2015/01 Sean, use the best two RSSI only, suggested by Ynlin and ChenYu.*/ - if (rf_rx_num == 1) - avg_rssi = best_rssi; - else - avg_rssi = (best_rssi + second_rssi) / 2; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ - p_phy_info->signal_strength = SignalScaleProc(p_dm_odm->adapter, avg_rssi, false, false); -#else - p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, avg_rssi)); -#endif - } - } -#endif - p_dm_odm->rx_pwdb_ave = p_dm_odm->rx_pwdb_ave + p_phy_info->rx_pwdb_all; - - p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_anta; - p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_antb; - p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_antc; - p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_antd; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antidx_anta = ((%d)), MatchBSSID = ((%d))\n", p_pktinfo->station_id, p_phy_sta_rpt->antidx_anta, p_pktinfo->is_packet_match_bssid));*/ - - - /* dbg_print("p_phy_sta_rpt->antidx_anta = %d, p_phy_sta_rpt->antidx_antb = %d\n",*/ - /* p_phy_sta_rpt->antidx_anta, p_phy_sta_rpt->antidx_antb);*/ - /* dbg_print("----------------------------\n");*/ - /* dbg_print("p_pktinfo->station_id=%d, p_pktinfo->data_rate=0x%x\n",p_pktinfo->station_id, p_pktinfo->data_rate);*/ - /* dbg_print("p_phy_sta_rpt->r_RFMOD = %d\n", p_phy_sta_rpt->r_RFMOD);*/ - /* dbg_print("p_phy_sta_rpt->gain_trsw[0]=0x%x, p_phy_sta_rpt->gain_trsw[1]=0x%x\n",*/ - /* p_phy_sta_rpt->gain_trsw[0],p_phy_sta_rpt->gain_trsw[1]);*/ - /* dbg_print("p_phy_sta_rpt->gain_trsw[2]=0x%x, p_phy_sta_rpt->gain_trsw[3]=0x%x\n",*/ - /* p_phy_sta_rpt->gain_trsw_cd[0],p_phy_sta_rpt->gain_trsw_cd[1]);*/ - /* dbg_print("p_phy_sta_rpt->pwdb_all = 0x%x, p_phy_info->rx_pwdb_all = %d\n", p_phy_sta_rpt->pwdb_all, p_phy_info->rx_pwdb_all);*/ - /* dbg_print("p_phy_sta_rpt->cfotail[i] = 0x%x, p_phy_sta_rpt->CFO_tail[i] = 0x%x\n", p_phy_sta_rpt->cfotail[0], p_phy_sta_rpt->cfotail[1]);*/ - /* dbg_print("p_phy_sta_rpt->rxevm[0] = %d, p_phy_sta_rpt->rxevm[1] = %d\n", p_phy_sta_rpt->rxevm[0], p_phy_sta_rpt->rxevm[1]);*/ - /* dbg_print("p_phy_sta_rpt->rxevm[2] = %d, p_phy_sta_rpt->rxevm[3] = %d\n", p_phy_sta_rpt->rxevm_cd[0], p_phy_sta_rpt->rxevm_cd[1]);*/ - /* dbg_print("p_phy_info->rx_mimo_signal_strength[0]=%d, p_phy_info->rx_mimo_signal_strength[1]=%d, rx_pwdb_all=%d\n",*/ - /* p_phy_info->rx_mimo_signal_strength[0], p_phy_info->rx_mimo_signal_strength[1], p_phy_info->rx_pwdb_all);*/ - /* dbg_print("p_phy_info->rx_mimo_signal_strength[2]=%d, p_phy_info->rx_mimo_signal_strength[3]=%d\n",*/ - /* p_phy_info->rx_mimo_signal_strength[2], p_phy_info->rx_mimo_signal_strength[3]);*/ - /* dbg_print("ppPhyInfo->rx_mimo_signal_quality[0]=%d, p_phy_info->rx_mimo_signal_quality[1]=%d\n",*/ - /* p_phy_info->rx_mimo_signal_quality[0], p_phy_info->rx_mimo_signal_quality[1]);*/ - /* dbg_print("ppPhyInfo->rx_mimo_signal_quality[2]=%d, p_phy_info->rx_mimo_signal_quality[3]=%d\n",*/ - /* p_phy_info->rx_mimo_signal_quality[2], p_phy_info->rx_mimo_signal_quality[3]);*/ - -} - -#endif - -void -phydm_reset_rssi_for_dm( - struct PHY_DM_STRUCT *p_dm_odm, - u8 station_id -) -{ - struct sta_info *p_entry; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); -#endif - - p_entry = p_dm_odm->p_odm_sta_info[station_id]; - - if (!IS_STA_VALID(p_entry)) { - /**/ - return; - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("Reset RSSI for macid = (( %d ))\n", station_id)); - - - p_entry->rssi_stat.undecorated_smoothed_cck = -1; - p_entry->rssi_stat.undecorated_smoothed_ofdm = -1; - p_entry->rssi_stat.undecorated_smoothed_pwdb = -1; - p_entry->rssi_stat.ofdm_pkt = 0; - p_entry->rssi_stat.cck_pkt = 0; - p_entry->rssi_stat.cck_sum_power = 0; - p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT; - p_entry->rssi_stat.packet_map = 0; - p_entry->rssi_stat.valid_bit = 0; - - /*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - p_entry->bUsed = 0; - if (station_id == 0) { - - p_hal_data->UndecoratedSmoothedPWDB = -1; - /**/ - } -#endif - -} - -void -odm_init_rssi_for_dm( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - -} - -void -odm_process_rssi_for_dm( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - - s32 undecorated_smoothed_pwdb, undecorated_smoothed_cck, undecorated_smoothed_ofdm, rssi_ave, cck_pkt; - u8 i, is_cck_rate = 0; - u8 RSSI_max, RSSI_min; - u32 weighting = 0; - u8 send_rssi_2_fw = 0; - struct sta_info *p_entry; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); -#endif - - if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) - return; - -#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY - odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(p_dm_odm, p_phy_info, p_pktinfo); -#endif - - /* */ - /* 2012/05/30 MH/Luke.Lee Add some description */ - /* In windows driver: AP/IBSS mode STA */ - /* */ - /* if (p_dm_odm->support_platform == ODM_WIN) */ - /* { */ - /* p_entry = p_dm_odm->p_odm_sta_info[p_dm_odm->pAidMap[p_pktinfo->station_id-1]]; */ - /* } */ - /* else */ - p_entry = p_dm_odm->p_odm_sta_info[p_pktinfo->station_id]; - - if (!IS_STA_VALID(p_entry)) { - return; - /**/ - } - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - if ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) && - (p_dm_fat_table->enable_ctrl_frame_antdiv) - ) { - if (p_pktinfo->is_packet_match_bssid) - p_dm_odm->data_frame_num++; - - if ((p_dm_fat_table->use_ctrl_frame_antdiv)) { - if (!p_pktinfo->is_to_self)/*data frame + CTRL frame*/ - return; - } else { - if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/ - return; - } - } else -#endif - { - if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/ - return; - } - - if (p_pktinfo->is_packet_beacon) - p_dm_odm->phy_dbg_info.num_qry_beacon_pkt++; - - is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false; - p_dm_odm->rx_rate = p_pktinfo->data_rate; - - /* --------------Statistic for antenna/path diversity------------------ */ - if (p_dm_odm->support_ability & ODM_BB_ANT_DIV) { -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - odm_process_rssi_for_ant_div(p_dm_odm, p_phy_info, p_pktinfo); -#endif - } -#if (defined(CONFIG_PATH_DIVERSITY)) - else if (p_dm_odm->support_ability & ODM_BB_PATH_DIV) - phydm_process_rssi_for_path_div(p_dm_odm, p_phy_info, p_pktinfo); -#endif - /* -----------------Smart Antenna Debug Message------------------ */ - - undecorated_smoothed_cck = p_entry->rssi_stat.undecorated_smoothed_cck; - undecorated_smoothed_ofdm = p_entry->rssi_stat.undecorated_smoothed_ofdm; - undecorated_smoothed_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - - if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) { - - if (!is_cck_rate) { /* ofdm rate */ -#if (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) { - u8 RX_count = 0; - u32 RSSI_linear = 0; - - if (p_dm_odm->rx_ant_status & ODM_RF_A) { - p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - RX_count++; - RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]); - } else - p_dm_odm->RSSI_A = 0; - - if (p_dm_odm->rx_ant_status & ODM_RF_B) { - p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; - RX_count++; - RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]); - } else - p_dm_odm->RSSI_B = 0; - - if (p_dm_odm->rx_ant_status & ODM_RF_C) { - p_dm_odm->RSSI_C = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C]; - RX_count++; - RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C]); - } else - p_dm_odm->RSSI_C = 0; - - if (p_dm_odm->rx_ant_status & ODM_RF_D) { - p_dm_odm->RSSI_D = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D]; - RX_count++; - RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D]); - } else - p_dm_odm->RSSI_D = 0; - - /* Calculate average RSSI */ - switch (RX_count) { - case 2: - RSSI_linear = (RSSI_linear >> 1); - break; - case 3: - RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */ - break; - case 4: - RSSI_linear = (RSSI_linear >> 2); - break; - } - rssi_ave = odm_convert_to_db(RSSI_linear); - } else -#endif - { - if (p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B] == 0) { - rssi_ave = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - p_dm_odm->RSSI_B = 0; - } else { - /*dbg_print("p_rfd->status.rx_mimo_signal_strength[0] = %d, p_rfd->status.rx_mimo_signal_strength[1] = %d\n",*/ - /*p_rfd->status.rx_mimo_signal_strength[0], p_rfd->status.rx_mimo_signal_strength[1]);*/ - p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; - - if (p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A] > p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]) { - RSSI_max = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - RSSI_min = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; - } else { - RSSI_max = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; - RSSI_min = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - } - if ((RSSI_max - RSSI_min) < 3) - rssi_ave = RSSI_max; - else if ((RSSI_max - RSSI_min) < 6) - rssi_ave = RSSI_max - 1; - else if ((RSSI_max - RSSI_min) < 10) - rssi_ave = RSSI_max - 2; - else - rssi_ave = RSSI_max - 3; - } - } - - /* 1 Process OFDM RSSI */ - if (undecorated_smoothed_ofdm <= 0) { /* initialize */ - undecorated_smoothed_ofdm = p_phy_info->rx_pwdb_all; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_INIT: (( %d ))\n", undecorated_smoothed_ofdm)); - } else { - if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_ofdm) { - undecorated_smoothed_ofdm = - (((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) + - (rssi_ave)) / (RX_SMOOTH_FACTOR); - undecorated_smoothed_ofdm = undecorated_smoothed_ofdm + 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_1: (( %d ))\n", undecorated_smoothed_ofdm)); - } else { - undecorated_smoothed_ofdm = - (((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) + - (rssi_ave)) / (RX_SMOOTH_FACTOR); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_2: (( %d ))\n", undecorated_smoothed_ofdm)); - } - } - if (p_entry->rssi_stat.ofdm_pkt != 64) { - i = 63; - p_entry->rssi_stat.ofdm_pkt -= (u8)(((p_entry->rssi_stat.packet_map >> i) & BIT(0)) - 1); - } - p_entry->rssi_stat.packet_map = (p_entry->rssi_stat.packet_map << 1) | BIT(0); - - } else { - rssi_ave = p_phy_info->rx_pwdb_all; - p_dm_odm->RSSI_A = (u8) p_phy_info->rx_pwdb_all; - p_dm_odm->RSSI_B = 0xFF; - p_dm_odm->RSSI_C = 0xFF; - p_dm_odm->RSSI_D = 0xFF; - - if (p_entry->rssi_stat.cck_pkt <= 63) - p_entry->rssi_stat.cck_pkt++; - - /* 1 Process CCK RSSI */ - if (undecorated_smoothed_cck <= 0) { /* initialize */ - undecorated_smoothed_cck = p_phy_info->rx_pwdb_all; - p_entry->rssi_stat.cck_sum_power = (u16)p_phy_info->rx_pwdb_all ; /*reset*/ - p_entry->rssi_stat.cck_pkt = 1; /*reset*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_INIT: (( %d ))\n", undecorated_smoothed_cck)); - } else if (p_entry->rssi_stat.cck_pkt <= CCK_RSSI_INIT_COUNT) { - - p_entry->rssi_stat.cck_sum_power = p_entry->rssi_stat.cck_sum_power + (u16)p_phy_info->rx_pwdb_all; - undecorated_smoothed_cck = p_entry->rssi_stat.cck_sum_power / p_entry->rssi_stat.cck_pkt; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_0: (( %d )), SumPow = (( %d )), cck_pkt = (( %d ))\n", - undecorated_smoothed_cck, p_entry->rssi_stat.cck_sum_power, p_entry->rssi_stat.cck_pkt)); - } else { - if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_cck) { - undecorated_smoothed_cck = - (((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) + - (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); - undecorated_smoothed_cck = undecorated_smoothed_cck + 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_1: (( %d ))\n", undecorated_smoothed_cck)); - } else { - undecorated_smoothed_cck = - (((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) + - (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_2: (( %d ))\n", undecorated_smoothed_cck)); - } - } - i = 63; - p_entry->rssi_stat.ofdm_pkt -= (u8)((p_entry->rssi_stat.packet_map >> i) & BIT(0)); - p_entry->rssi_stat.packet_map = p_entry->rssi_stat.packet_map << 1; - } - - /* if(p_entry) */ - { - /* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */ - if (p_entry->rssi_stat.ofdm_pkt == 64) { /* speed up when all packets are OFDM*/ - undecorated_smoothed_pwdb = undecorated_smoothed_ofdm; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_0[%d] = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck)); - } else { - if (p_entry->rssi_stat.valid_bit < 64) - p_entry->rssi_stat.valid_bit++; - - if (p_entry->rssi_stat.valid_bit == 64) { - weighting = ((p_entry->rssi_stat.ofdm_pkt) > 4) ? 64 : (p_entry->rssi_stat.ofdm_pkt << 4); - undecorated_smoothed_pwdb = (weighting * undecorated_smoothed_ofdm + (64 - weighting) * undecorated_smoothed_cck) >> 6; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_1[%d] = (( %d )), W = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck, weighting)); - } else { - if (p_entry->rssi_stat.valid_bit != 0) - undecorated_smoothed_pwdb = (p_entry->rssi_stat.ofdm_pkt * undecorated_smoothed_ofdm + (p_entry->rssi_stat.valid_bit - p_entry->rssi_stat.ofdm_pkt) * undecorated_smoothed_cck) / p_entry->rssi_stat.valid_bit; - else - undecorated_smoothed_pwdb = 0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_2[%d] = (( %d )), ofdm_pkt = (( %d )), Valid_Bit = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck, p_entry->rssi_stat.ofdm_pkt, p_entry->rssi_stat.valid_bit)); - } - } - - - if ((p_entry->rssi_stat.ofdm_pkt >= 1 || p_entry->rssi_stat.cck_pkt >= 5) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_INIT)) { - - send_rssi_2_fw = 1; - p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_SEND; - } - - p_entry->rssi_stat.undecorated_smoothed_cck = undecorated_smoothed_cck; - p_entry->rssi_stat.undecorated_smoothed_ofdm = undecorated_smoothed_ofdm; - p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb; - - - - if (send_rssi_2_fw) { /* Trigger init rate by RSSI */ - - if (p_entry->rssi_stat.ofdm_pkt != 0) - p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_ofdm; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("[Send to FW] PWDB = (( %d )), ofdm_pkt = (( %d )), cck_pkt = (( %d ))\n", - undecorated_smoothed_pwdb, p_entry->rssi_stat.ofdm_pkt, p_entry->rssi_stat.cck_pkt)); - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - phydm_ra_rssi_rpt_wk(p_dm_odm); -#endif - } - - - /*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - - if (p_pktinfo->station_id == 0) { - /**/ - p_hal_data->UndecoratedSmoothedPWDB = undecorated_smoothed_pwdb; - } -#endif - - /* dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt, weighting); */ - /* dbg_print("undecorated_smoothed_ofdm=%d, undecorated_smoothed_pwdb=%d, undecorated_smoothed_cck=%d\n", */ - /* undecorated_smoothed_ofdm, undecorated_smoothed_pwdb, undecorated_smoothed_cck); */ - - } - - } -} - - -#if (ODM_IC_11N_SERIES_SUPPORT == 1) -/* - * Endianness before calling this API - * */ -void -odm_phy_status_query_92c_series( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - odm_rx_phy_status92c_series_parsing(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); - odm_process_rssi_for_dm(p_dm_odm, p_phy_info, p_pktinfo); -} -#endif - - -/* - * Endianness before calling this API - * */ -#if ODM_IC_11AC_SERIES_SUPPORT - -void -odm_phy_status_query_jaguar_series( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - odm_rx_phy_status_jaguar_series_parsing(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); - odm_process_rssi_for_dm(p_dm_odm, p_phy_info, p_pktinfo); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - /*phydm_sbd_check(p_dm_odm);*/ -#endif -} -#endif - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -phydm_normal_driver_rx_sniffer( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_desc, - PRT_RFD_STATUS p_rt_rfd_status, - u8 *p_drv_info, - u8 phy_status -) -{ -#if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING)) - u32 *p_msg; - u16 seq_num; - struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; - - if (p_rt_rfd_status->packet_report_type != NORMAL_RX) - return; - - if (!p_dm_odm->is_linked) { - if (p_rt_rfd_status->is_hw_error) - return; - } - - if (!(p_dm_fat_table->fat_state == FAT_TRAINING_STATE)) - return; - - if (phy_status == true) { - - if ((p_dm_odm->rx_pkt_type == type_block_ack) || (p_dm_odm->rx_pkt_type == type_rts) || (p_dm_odm->rx_pkt_type == type_cts)) - seq_num = 0; - else - seq_num = p_rt_rfd_status->seq_num; - - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s, rate=0x%02x, L=%04d , %s , %s", - seq_num, - /*p_rt_rfd_status->mac_id,*/ - ((p_rt_rfd_status->is_crc) ? "C" : (p_rt_rfd_status->is_ampdu) ? "A" : "_"), - p_rt_rfd_status->data_rate, - p_rt_rfd_status->length, - ((p_rt_rfd_status->band_width == 0) ? "20M" : ((p_rt_rfd_status->band_width == 1) ? "40M" : "80M")), - ((p_rt_rfd_status->is_ldpc) ? "LDP" : "BCC") - )); - - if (p_dm_odm->rx_pkt_type == type_asoc_req) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_REQ")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_asoc_rsp) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "AS_RSP")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_probe_req) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_REQ")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_probe_rsp) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "PR_RSP")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_deauth) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "DEAUTH")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_beacon) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BEACON")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_block_ack_req) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "BA_REQ")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_rts) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__RTS_")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_cts) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__CTS_")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_ack) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__ACK_")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_block_ack) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "__BA__")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_data) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "_DATA_")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_data_ack) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "Data_Ack")); - /**/ - } else if (p_dm_odm->rx_pkt_type == type_qos_data) { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [%s]", "QoS_Data")); - /**/ - } else { - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [0x%x]", p_dm_odm->rx_pkt_type)); - /**/ - } - - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , [RSSI=%d,%d,%d,%d ]", - p_dm_odm->RSSI_A, - p_dm_odm->RSSI_B, - p_dm_odm->RSSI_C, - p_dm_odm->RSSI_D - )); - - p_msg = (u32 *)p_drv_info; - - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, (" , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n", - p_msg[6], p_msg[5], p_msg[4], p_msg[3], p_msg[2], p_msg[1], p_msg[1])); - } else { + * Larry Finger + * + *****************************************************************************/ - ODM_RT_TRACE_F(p_dm_odm, ODM_COMP_SNIFFER, ODM_DBG_LOUD, ("%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n", - p_rt_rfd_status->seq_num, - /*p_rt_rfd_status->mac_id,*/ - ((p_rt_rfd_status->is_crc) ? "C" : (p_rt_rfd_status->is_ampdu) ? "A" : "_"), - p_rt_rfd_status->data_rate, - p_rt_rfd_status->length, - ((p_rt_rfd_status->band_width == 0) ? "20M" : ((p_rt_rfd_status->band_width == 1) ? "40M" : "80M")), - ((p_rt_rfd_status->is_ldpc) ? "LDP" : "BCC") - )); - } +/*@************************************************************ + * include files + ************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" -#endif -} -#endif +#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(dm)) +#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(dm)) -void -odm_phy_status_query( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) { - phydm_rx_phy_status_new_type(p_dm_odm, p_phy_status, p_pktinfo, p_phy_info); - return; - } +#if (PHYDM_TESTCHIP_SUPPORT == 1) +#define READ_AND_CONFIG(ic, txt) \ + do { \ + if (dm->is_mp_chip) \ + READ_AND_CONFIG_MP(ic, txt); \ + else \ + READ_AND_CONFIG_TC(ic, txt); \ + } while (0) +#else +#define READ_AND_CONFIG READ_AND_CONFIG_MP #endif -#if ODM_IC_11AC_SERIES_SUPPORT - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - odm_phy_status_query_jaguar_series(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); -#endif +#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt()) +#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt()) -#if ODM_IC_11N_SERIES_SUPPORT - if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) - odm_phy_status_query_92c_series(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); +#if (PHYDM_TESTCHIP_SUPPORT == 1) +#define GET_VERSION(ic, txt) (dm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt)) +#else +#define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt) #endif -} - -/* For future use. */ -void -odm_mac_status_query( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_mac_status, - u8 mac_id, - boolean is_packet_match_bssid, - boolean is_packet_to_self, - boolean is_packet_beacon -) -{ - /* 2011/10/19 Driver team will handle in the future. */ - -} - - -/* - * If you want to add a new IC, Please follow below template and generate a new one. - * - * */ enum hal_status -odm_config_rf_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_config_type config_type, - enum odm_rf_radio_path_e e_rf_path -) +odm_config_rf_with_header_file(struct dm_struct *dm, + enum odm_rf_config_type config_type, + u8 e_rf_path) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; #endif - enum hal_status ret = HAL_STATUS_SUCCESS; + enum hal_status result = HAL_STATUS_SUCCESS; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>odm_config_rf_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n", - p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); + PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__, + (dm->is_mp_chip) ? "MPChip" : "TestChip"); + PHYDM_DBG(dm, ODM_COMP_INIT, + "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", + dm->support_platform, dm->support_interface, dm->board_type); - /* 1 AP doesn't use PHYDM power tracking table in these ICs */ +/* @1 AP doesn't use PHYDM power tracking table in these ICs */ #if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) { + if (dm->support_ic_type == ODM_RTL8812) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8812a, _radioa); - else if (e_rf_path == ODM_RF_PATH_B) + else if (e_rf_path == RF_PATH_B) READ_AND_CONFIG_MP(8812a, _radiob); } else if (config_type == CONFIG_RF_TXPWR_LMT) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - if ((p_hal_data->EEPROMSVID == 0x17AA && p_hal_data->EEPROMSMID == 0xA811) || - (p_hal_data->EEPROMSVID == 0x10EC && p_hal_data->EEPROMSMID == 0xA812) || - (p_hal_data->EEPROMSVID == 0x10EC && p_hal_data->EEPROMSMID == 0x8812)) + HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + if ((hal_data->EEPROMSVID == 0x17AA && hal_data->EEPROMSMID == 0xA811) || + (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0xA812) || + (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0x8812)) READ_AND_CONFIG_MP(8812a, _txpwr_lmt_hm812a03); else #endif @@ -1984,43 +94,42 @@ odm_config_rf_with_header_file( } #endif #if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821) { + if (dm->support_ic_type == ODM_RTL8821) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8821a, _radioa); } else if (config_type == CONFIG_RF_TXPWR_LMT) { - if (p_dm_odm->support_interface == ODM_ITRF_USB) { - if (p_dm_odm->ext_pa_5g || p_dm_odm->ext_lna_5g) + if (dm->support_interface == ODM_ITRF_USB) { + if (dm->ext_pa_5g || dm->ext_lna_5g) READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_fem); else READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_ipa); } else { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB) + if (mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB) READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_8mm); - else if (p_mgnt_info->CustomerID == RT_CID_ASUS_NB) + else if (mgnt_info->CustomerID == RT_CID_ASUS_NB) READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_5mm); else #endif READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a); } } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigRFWithHeaderFile\n")); } #endif #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + if (dm->support_ic_type == ODM_RTL8192E) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8192e, _radioa); - else if (e_rf_path == ODM_RF_PATH_B) + else if (e_rf_path == RF_PATH_B) READ_AND_CONFIG_MP(8192e, _radiob); } else if (config_type == CONFIG_RF_TXPWR_LMT) { -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/ - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/ + HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - if ((p_hal_data->EEPROMSVID == 0x11AD && p_hal_data->EEPROMSMID == 0x8192) || - (p_hal_data->EEPROMSVID == 0x11AD && p_hal_data->EEPROMSMID == 0x8193)) + if ((hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8192) || + (hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8193)) READ_AND_CONFIG_MP(8192e, _txpwr_lmt_8192e_sar_5mm); else #endif @@ -2029,39 +138,39 @@ odm_config_rf_with_header_file( } #endif #if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (dm->support_ic_type == ODM_RTL8723D) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8723d, _radioa); - } else if (config_type == CONFIG_RF_TXPWR_LMT) + } else if (config_type == CONFIG_RF_TXPWR_LMT) { READ_AND_CONFIG_MP(8723d, _txpwr_lmt); + } } #endif -/* JJ ADD 20161014 */ +/* @JJ ADD 20161014 */ #if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + if (dm->support_ic_type == ODM_RTL8710B) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8710b, _radioa); } else if (config_type == CONFIG_RF_TXPWR_LMT) READ_AND_CONFIG_MP(8710b, _txpwr_lmt); } #endif -#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ - - /* 1 All platforms support */ +#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */ +/* @1 All platforms support */ #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + if (dm->support_ic_type == ODM_RTL8188E) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8188e, _radioa); } else if (config_type == CONFIG_RF_TXPWR_LMT) READ_AND_CONFIG_MP(8188e, _txpwr_lmt); } #endif #if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (dm->support_ic_type == ODM_RTL8723B) { if (config_type == CONFIG_RF_RADIO) READ_AND_CONFIG_MP(8723b, _radioa); else if (config_type == CONFIG_RF_TXPWR_LMT) @@ -2069,71 +178,79 @@ odm_config_rf_with_header_file( } #endif #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) { + if (dm->support_ic_type == ODM_RTL8814A) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8814a, _radioa); - else if (e_rf_path == ODM_RF_PATH_B) + else if (e_rf_path == RF_PATH_B) READ_AND_CONFIG_MP(8814a, _radiob); - else if (e_rf_path == ODM_RF_PATH_C) + else if (e_rf_path == RF_PATH_C) READ_AND_CONFIG_MP(8814a, _radioc); - else if (e_rf_path == ODM_RF_PATH_D) + else if (e_rf_path == RF_PATH_D) READ_AND_CONFIG_MP(8814a, _radiod); } else if (config_type == CONFIG_RF_TXPWR_LMT) { - if (p_dm_odm->rfe_type == 0) - READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type0); - else if (p_dm_odm->rfe_type == 1) - READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type1); - else if (p_dm_odm->rfe_type == 2) - READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type2); - else if (p_dm_odm->rfe_type == 3) - READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type3); - else if (p_dm_odm->rfe_type == 5) - READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type5); - else if (p_dm_odm->rfe_type == 7) - READ_AND_CONFIG_MP(8814a,_txpwr_lmt_type7); + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type1); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type3); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type5); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type8); else - READ_AND_CONFIG_MP(8814a,_txpwr_lmt); + READ_AND_CONFIG_MP(8814a, _txpwr_lmt); } } #endif #if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + if (dm->support_ic_type == ODM_RTL8703B) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8703b, _radioa); } } #endif #if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (dm->support_ic_type == ODM_RTL8188F) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8188f, _radioa); } else if (config_type == CONFIG_RF_TXPWR_LMT) READ_AND_CONFIG_MP(8188f, _txpwr_lmt); } #endif #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { + if (dm->support_ic_type == ODM_RTL8822B) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8822b, _radioa); - else if (e_rf_path == ODM_RF_PATH_B) + else if (e_rf_path == RF_PATH_B) READ_AND_CONFIG_MP(8822b, _radiob); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if(p_dm_odm->halmac_ability & ODM_PHY_PARAM_OFFLOAD) - { - RT_STATUS status = RT_STATUS_SUCCESS; - status = HAL_MAC_Config_PHY_WriteNByte(&GET_HAL_MAC_INFO(p_dm_odm->adapter),HALMAC_PARAMETER_CMD_END,0,0,FALSE,0,TRUE,0,0); - if(status != RT_STATUS_SUCCESS) - ret = HAL_STATUS_FAILURE; - RT_TRACE(COMP_INIT, DBG_LOUD, ("RF param. offload status = %x\n",status)); - } -#endif } else if (config_type == CONFIG_RF_TXPWR_LMT) { - if (p_dm_odm->rfe_type == 5) + if (dm->rfe_type == 5) READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type5); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type4); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type12); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type18); else READ_AND_CONFIG_MP(8822b, _txpwr_lmt); } @@ -2141,143 +258,258 @@ odm_config_rf_with_header_file( #endif #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8197F) { + if (dm->support_ic_type == ODM_RTL8197F) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG_MP(8197f, _radioa); - else if (e_rf_path == ODM_RF_PATH_B) + else if (e_rf_path == RF_PATH_B) READ_AND_CONFIG_MP(8197f, _radiob); } } #endif - +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8192f, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8192f, _radiob); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type1); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type5); + else if (dm->rfe_type == 6) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type6); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type8); + else if (dm->rfe_type == 9) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type9); + else if (dm->rfe_type == 10) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type10); + else if (dm->rfe_type == 11) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type11); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type12); + else if (dm->rfe_type == 13) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type13); + else if (dm->rfe_type == 14) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type14); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type18); + else if (dm->rfe_type == 19) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type19); + else if (dm->rfe_type == 20) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type20); + else if (dm->rfe_type == 21) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type21); + else if (dm->rfe_type == 22) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type22); + else if (dm->rfe_type == 23) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type23); + else if (dm->rfe_type == 24) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type24); + else if (dm->rfe_type == 25) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type25); + else if (dm->rfe_type == 26) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type26); + else if (dm->rfe_type == 27) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type27); + else if (dm->rfe_type == 28) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type28); + else if (dm->rfe_type == 29) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type29); + else if (dm->rfe_type == 30) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type30); + else if (dm->rfe_type == 31) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type31); + else + READ_AND_CONFIG_MP(8192f, _txpwr_lmt); + } + } +#endif #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + if (dm->support_ic_type == ODM_RTL8821C) { if (config_type == CONFIG_RF_RADIO) { - if (e_rf_path == ODM_RF_PATH_A) + if (e_rf_path == RF_PATH_A) READ_AND_CONFIG(8821c, _radioa); - } else if (config_type == CONFIG_RF_TXPWR_LMT) + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + READ_AND_CONFIG(8821c, _txpwr_lmt); + } + } +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG(8195b, _radioa); + } + #if 0 + else if (config_type == CONFIG_RF_TXPWR_LMT) { READ_AND_CONFIG(8821c, _txpwr_lmt); + /*@*/ + } + #endif + } +#endif +#if (RTL8198F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8198F) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8198f, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8198f, _radiob); + else if (e_rf_path == RF_PATH_C) + READ_AND_CONFIG_MP(8198f, _radioc); + else if (e_rf_path == RF_PATH_D) + READ_AND_CONFIG_MP(8198f, _radiod); + } } #endif - return ret; + if (config_type == CONFIG_RF_RADIO) { + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + result = phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_END, + 0, + 0, + 0, + (enum rf_path)0, + 0); + PHYDM_DBG(dm, ODM_COMP_INIT, + "rf param offload end!result = %d", result); + } + } + + return result; } enum hal_status -odm_config_rf_with_tx_pwr_track_header_file( - struct PHY_DM_STRUCT *p_dm_odm -) +odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>odm_config_rf_with_tx_pwr_track_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n", - p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); - + PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__, + (dm->is_mp_chip) ? "MPChip" : "TestChip"); + PHYDM_DBG(dm, ODM_COMP_INIT, + "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", + dm->support_platform, dm->support_interface, dm->board_type); - /* 1 AP doesn't use PHYDM power tracking table in these ICs */ +/* @1 AP doesn't use PHYDM power tracking table in these ICs */ #if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if RTL8821A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8821) { + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8821a, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8821a, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8821a, _txpowertrack_sdio); } #endif #if RTL8812A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8812) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8812) { + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8812a, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) { - if (p_dm_odm->rfe_type == 3 && p_dm_odm->is_mp_chip) + else if (dm->support_interface == ODM_ITRF_USB) { + if (dm->rfe_type == 3 && dm->is_mp_chip) READ_AND_CONFIG_MP(8812a, _txpowertrack_rfe3); else READ_AND_CONFIG_MP(8812a, _txpowertrack_usb); } - } #endif #if RTL8192E_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8192E) { + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8192e, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8192e, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8192e, _txpowertrack_sdio); } #endif #if RTL8723D_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8723D) { + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8723d, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8723d, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8723d, _txpowertrack_sdio); READ_AND_CONFIG_MP(8723d, _txxtaltrack); } #endif -/* JJ ADD 20161014 */ +/* @JJ ADD 20161014 */ #if RTL8710B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8710B) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) - READ_AND_CONFIG_MP(8710b, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) - READ_AND_CONFIG_MP(8710b, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) - READ_AND_CONFIG_MP(8710b, _txpowertrack_sdio); + if (dm->support_ic_type == ODM_RTL8710B) { + if (dm->package_type == 1) + READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_smic); + else if (dm->package_type == 5) + READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_umc); READ_AND_CONFIG_MP(8710b, _txxtaltrack); } #endif - #if RTL8188E_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - if (odm_get_mac_reg(p_dm_odm, 0xF0, 0xF000) >= 8) { /*if 0xF0[15:12] >= 8, SMIC*/ - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8188E) { + if (odm_get_mac_reg(dm, R_0xf0, 0xF000) >= 8) { /*@if 0xF0[15:12] >= 8, SMIC*/ + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie_icut); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8188e, _txpowertrack_usb_icut); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio_icut); - } else { /*else 0xF0[15:12] < 8, TSMC*/ - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + } else { /*@else 0xF0[15:12] < 8, TSMC*/ + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8188e, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio); } - } #endif -#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ - - /* 1 All platforms support */ +#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */ +/* @1 All platforms support */ #if RTL8723B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - if (p_dm_odm->support_interface == ODM_ITRF_PCIE) + if (dm->support_ic_type == ODM_RTL8723B) { + if (dm->support_interface == ODM_ITRF_PCIE) READ_AND_CONFIG_MP(8723b, _txpowertrack_pcie); - else if (p_dm_odm->support_interface == ODM_ITRF_USB) + else if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8723b, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8723b, _txpowertrack_sdio); } #endif #if RTL8814A_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8814A) { - if (p_dm_odm->rfe_type == 0) + if (dm->support_ic_type == ODM_RTL8814A) { + if (dm->rfe_type == 0) READ_AND_CONFIG_MP(8814a, _txpowertrack_type0); - else if (p_dm_odm->rfe_type == 2) + else if (dm->rfe_type == 2) READ_AND_CONFIG_MP(8814a, _txpowertrack_type2); - else if (p_dm_odm->rfe_type == 5) + else if (dm->rfe_type == 5) READ_AND_CONFIG_MP(8814a, _txpowertrack_type5); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type8); else READ_AND_CONFIG_MP(8814a, _txpowertrack); @@ -2285,111 +517,205 @@ odm_config_rf_with_tx_pwr_track_header_file( } #endif #if RTL8703B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8703B) { - if (p_dm_odm->support_interface == ODM_ITRF_USB) + if (dm->support_ic_type == ODM_RTL8703B) { + if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8703b, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8703b, _txpowertrack_sdio); READ_AND_CONFIG_MP(8703b, _txxtaltrack); } #endif - #if RTL8188F_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - if (p_dm_odm->support_interface == ODM_ITRF_USB) + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_USB) READ_AND_CONFIG_MP(8188f, _txpowertrack_usb); - else if (p_dm_odm->support_interface == ODM_ITRF_SDIO) + else if (dm->support_interface == ODM_ITRF_SDIO) READ_AND_CONFIG_MP(8188f, _txpowertrack_sdio); } #endif - #if RTL8822B_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - if (p_dm_odm->rfe_type == 0) + if (dm->support_ic_type == ODM_RTL8822B) { + if (dm->rfe_type == 0) READ_AND_CONFIG_MP(8822b, _txpowertrack_type0); - else if (p_dm_odm->rfe_type == 1) + else if (dm->rfe_type == 1) READ_AND_CONFIG_MP(8822b, _txpowertrack_type1); - else if (p_dm_odm->rfe_type == 2) + else if (dm->rfe_type == 2) READ_AND_CONFIG_MP(8822b, _txpowertrack_type2); - else if ((p_dm_odm->rfe_type == 3) || (p_dm_odm->rfe_type == 5)) + else if ((dm->rfe_type == 3) || (dm->rfe_type == 5)) READ_AND_CONFIG_MP(8822b, _txpowertrack_type3_type5); - else if (p_dm_odm->rfe_type == 4) + else if (dm->rfe_type == 4) READ_AND_CONFIG_MP(8822b, _txpowertrack_type4); - else if (p_dm_odm->rfe_type == 6) + else if (dm->rfe_type == 6) READ_AND_CONFIG_MP(8822b, _txpowertrack_type6); - else if (p_dm_odm->rfe_type == 7) + else if (dm->rfe_type == 7) READ_AND_CONFIG_MP(8822b, _txpowertrack_type7); - else if (p_dm_odm->rfe_type == 8) + else if (dm->rfe_type == 8) READ_AND_CONFIG_MP(8822b, _txpowertrack_type8); - else if (p_dm_odm->rfe_type == 9) + else if (dm->rfe_type == 9) READ_AND_CONFIG_MP(8822b, _txpowertrack_type9); - else if (p_dm_odm->rfe_type == 10) + else if (dm->rfe_type == 10) READ_AND_CONFIG_MP(8822b, _txpowertrack_type10); - else if (p_dm_odm->rfe_type == 11) + else if (dm->rfe_type == 11) READ_AND_CONFIG_MP(8822b, _txpowertrack_type11); - else if (p_dm_odm->rfe_type == 12) + else if (dm->rfe_type == 12) READ_AND_CONFIG_MP(8822b, _txpowertrack_type12); - else if (p_dm_odm->rfe_type == 13) + else if (dm->rfe_type == 13) READ_AND_CONFIG_MP(8822b, _txpowertrack_type13); + else if (dm->rfe_type == 14) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type14); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type18); else READ_AND_CONFIG_MP(8822b, _txpowertrack); } #endif - #if RTL8197F_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8197F) { - if (p_dm_odm->rfe_type == 0) + if (dm->support_ic_type == ODM_RTL8197F) { + if (dm->rfe_type == 0) READ_AND_CONFIG_MP(8197f, _txpowertrack_type0); - else if (p_dm_odm->rfe_type == 1) + else if (dm->rfe_type == 1) READ_AND_CONFIG_MP(8197f, _txpowertrack_type1); else READ_AND_CONFIG_MP(8197f, _txpowertrack); } #endif +/*@jj add 20170822*/ +#if RTL8192F_SUPPORT + if (dm->support_ic_type == ODM_RTL8192F) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type1); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type5); + else if (dm->rfe_type == 6) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type6); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type8); + else if (dm->rfe_type == 9) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type9); + else if (dm->rfe_type == 10) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type10); + else if (dm->rfe_type == 11) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type11); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type12); + else if (dm->rfe_type == 13) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type13); + else if (dm->rfe_type == 14) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type14); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type18); + else if (dm->rfe_type == 19) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type19); + else if (dm->rfe_type == 20) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type20); + else if (dm->rfe_type == 21) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type21); + else if (dm->rfe_type == 22) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type22); + else if (dm->rfe_type == 23) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type23); + else if (dm->rfe_type == 24) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type24); + else if (dm->rfe_type == 25) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type25); + else if (dm->rfe_type == 26) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type26); + else if (dm->rfe_type == 27) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type27); + else if (dm->rfe_type == 28) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type28); + else if (dm->rfe_type == 29) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type29); + else if (dm->rfe_type == 30) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type30); + else if (dm->rfe_type == 31) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type31); + else + READ_AND_CONFIG_MP(8192f, _txpowertrack); + READ_AND_CONFIG_MP(8192f, _txxtaltrack); + } +#endif #if RTL8821C_SUPPORT - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - READ_AND_CONFIG(8821c, _txpowertrack); + if (dm->support_ic_type == ODM_RTL8821C) { + if (dm->rfe_type == 0x5) + READ_AND_CONFIG(8821c, _txpowertrack_type0x28); + else if (dm->rfe_type == 0x4) + READ_AND_CONFIG(8821c, _txpowertrack_type0x20); + else + READ_AND_CONFIG(8821c, _txpowertrack); + } +#endif + +#if RTL8198F_SUPPORT + if (dm->support_ic_type == ODM_RTL8198F) + READ_AND_CONFIG_MP(8198f, _txpowertrack); +#endif + +#if RTL8195B_SUPPORT + if (dm->support_ic_type == ODM_RTL8195B) { + READ_AND_CONFIG_MP(8195b, _txpowertrack); + READ_AND_CONFIG_MP(8195b, _txxtaltrack); + } #endif return HAL_STATUS_SUCCESS; } enum hal_status -odm_config_bb_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_bb_config_type config_type -) +odm_config_bb_with_header_file(struct dm_struct *dm, + enum odm_bb_config_type config_type) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; #endif - enum hal_status ret = HAL_STATUS_SUCCESS; - + enum hal_status result = HAL_STATUS_SUCCESS; - /* 1 AP doesn't use PHYDM initialization in these ICs */ +/* @1 AP doesn't use PHYDM initialization in these ICs */ #if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) { + if (dm->support_ic_type == ODM_RTL8812) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8812a, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) READ_AND_CONFIG_MP(8812a, _agc_tab); else if (config_type == CONFIG_BB_PHY_REG_PG) { - if (p_dm_odm->rfe_type == 3 && p_dm_odm->is_mp_chip) + if (dm->rfe_type == 3 && dm->is_mp_chip) READ_AND_CONFIG_MP(8812a, _phy_reg_pg_asus); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - else if (p_mgnt_info->CustomerID == RT_CID_WNC_NEC && p_dm_odm->is_mp_chip) + else if (mgnt_info->CustomerID == RT_CID_WNC_NEC && dm->is_mp_chip) READ_AND_CONFIG_MP(8812a, _phy_reg_pg_nec); #if RT_PLATFORM == PLATFORM_MACOSX - /*{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/ - else if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) + /*@{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/ + else if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) READ_AND_CONFIG_MP(8812a, _phy_reg_pg_dni); /* TP-Link T4UH, Isaiah 2015-03-16*/ - else if (p_mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) { - dbg_print("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n"); + else if (mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) { + pr_debug("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n"); READ_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink); } #endif @@ -2399,17 +725,17 @@ odm_config_bb_with_header_file( } else if (config_type == CONFIG_BB_PHY_REG_MP) READ_AND_CONFIG_MP(8812a, _phy_reg_mp); else if (config_type == CONFIG_BB_AGC_TAB_DIFF) { - if ((36 <= *p_dm_odm->p_channel) && (*p_dm_odm->p_channel <= 64)) + dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD; + /*@AGC_TAB DIFF dont support FW offload*/ + if ((*dm->channel >= 36) && (*dm->channel <= 64)) AGC_DIFF_CONFIG_MP(8812a, lb); - else if (100 <= *p_dm_odm->p_channel) + else if (*dm->channel >= 100) AGC_DIFF_CONFIG_MP(8812a, hb); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8812AGCTABArray\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8812PHY_REGArray\n")); } #endif #if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821) { + if (dm->support_ic_type == ODM_RTL8821) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8821a, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2417,31 +743,29 @@ odm_config_bb_with_header_file( else if (config_type == CONFIG_BB_PHY_REG_PG) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - if ((p_hal_data->EEPROMSVID == 0x1043 && p_hal_data->EEPROMSMID == 0x207F)) + if ((hal_data->EEPROMSVID == 0x1043 && hal_data->EEPROMSMID == 0x207F)) READ_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa); else #endif #if (RT_PLATFORM == PLATFORM_MACOSX) - /*{1827}{1022} for BUFFALO power by rate table. Isaiah 2013-10-18*/ - if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) { - /*{1024} for BUFFALO power by rate table. (JP/US)*/ - if (p_mgnt_info->channel_plan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G) - READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us); - else - READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp); - } else + /*@ for BUFFALO pwr by rate table */ + if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) { + /*@ for BUFFALO pwr by rate table (JP/US)*/ + if (mgnt_info->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G) + READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us); + else + READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp); + } else #endif #endif - READ_AND_CONFIG_MP(8821a, _phy_reg_pg); + READ_AND_CONFIG_MP(8821a, _phy_reg_pg); } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8821AGCTABArray\n")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8821PHY_REGArray\n")); } #endif #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { + if (dm->support_ic_type == ODM_RTL8192E) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8192e, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2451,7 +775,7 @@ odm_config_bb_with_header_file( } #endif #if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + if (dm->support_ic_type == ODM_RTL8723D) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8723d, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2460,9 +784,9 @@ odm_config_bb_with_header_file( READ_AND_CONFIG_MP(8723d, _phy_reg_pg); } #endif -/* JJ ADD 20161014 */ +/* @JJ ADD 20161014 */ #if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + if (dm->support_ic_type == ODM_RTL8710B) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8710b, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2472,12 +796,10 @@ odm_config_bb_with_header_file( } #endif -#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ - - - /* 1 All platforms support */ +#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */ +/* @1 All platforms support */ #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { + if (dm->support_ic_type == ODM_RTL8188E) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8188e, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2487,7 +809,7 @@ odm_config_bb_with_header_file( } #endif #if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { + if (dm->support_ic_type == ODM_RTL8723B) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8723b, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2497,33 +819,34 @@ odm_config_bb_with_header_file( } #endif #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) { + if (dm->support_ic_type == ODM_RTL8814A) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8814a, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) READ_AND_CONFIG_MP(8814a, _agc_tab); else if (config_type == CONFIG_BB_PHY_REG_PG) { - if (p_dm_odm->rfe_type == 0) - READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type0); - else if (p_dm_odm->rfe_type == 2) - READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type2); - else if (p_dm_odm->rfe_type == 3) - READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type3); - else if (p_dm_odm->rfe_type == 4) - READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type4); - else if (p_dm_odm->rfe_type == 5) - READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type5); - else if (p_dm_odm->rfe_type == 7) - READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type7); + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type0); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type5); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type8); else - READ_AND_CONFIG_MP(8814a,_phy_reg_pg); - } - else if (config_type == CONFIG_BB_PHY_REG_MP) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg); + } else if (config_type == CONFIG_BB_PHY_REG_MP) READ_AND_CONFIG_MP(8814a, _phy_reg_mp); } #endif #if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + if (dm->support_ic_type == ODM_RTL8703B) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8703b, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2533,7 +856,7 @@ odm_config_bb_with_header_file( } #endif #if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { + if (dm->support_ic_type == ODM_RTL8188F) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG_MP(8188f, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2543,95 +866,152 @@ odm_config_bb_with_header_file( } #endif #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - if (config_type == CONFIG_BB_PHY_REG) - { + if (dm->support_ic_type == ODM_RTL8822B) { + if (config_type == CONFIG_BB_PHY_REG) { READ_AND_CONFIG_MP(8822b, _phy_reg); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if(p_dm_odm->halmac_ability & ODM_PHY_PARAM_OFFLOAD) - { - RT_STATUS status = RT_STATUS_SUCCESS; - status = HAL_MAC_Config_PHY_WriteNByte(&GET_HAL_MAC_INFO(p_dm_odm->adapter), - HALMAC_PARAMETER_CMD_END, - 0, - 0, - FALSE, - 0, - TRUE, - 0, - 0); - if(status != RT_STATUS_SUCCESS) - ret = HAL_STATUS_FAILURE; - RT_TRACE(COMP_INIT, DBG_LOUD, ("BB PHY REG param. offload status = %x\n",status)); - } -#endif - } - else if (config_type == CONFIG_BB_AGC_TAB) - { + } else if (config_type == CONFIG_BB_AGC_TAB) { READ_AND_CONFIG_MP(8822b, _agc_tab); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if(p_dm_odm->halmac_ability & ODM_PHY_PARAM_OFFLOAD) - { - RT_STATUS status = RT_STATUS_SUCCESS; - status = HAL_MAC_Config_PHY_WriteNByte(&GET_HAL_MAC_INFO(p_dm_odm->adapter), - HALMAC_PARAMETER_CMD_END, - 0, - 0, - FALSE, - 0, - TRUE, - 0, - 0); - if(status != RT_STATUS_SUCCESS) - ret = HAL_STATUS_FAILURE; - RT_TRACE(COMP_INIT, DBG_LOUD, ("BB AGC TABLE param. offload status = %x\n",status)); - } -#endif + } else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type5); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type12); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type18); + else + READ_AND_CONFIG_MP(8822b, _phy_reg_pg); } - else if (config_type == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8822b, _phy_reg_pg); - /*else if (config_type == CONFIG_BB_PHY_REG_MP)*/ - /*READ_AND_CONFIG_MP(8822b, _phy_reg_mp);*/ } #endif #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8197F) { + if (dm->support_ic_type == ODM_RTL8197F) { if (config_type == CONFIG_BB_PHY_REG) { READ_AND_CONFIG_MP(8197f, _phy_reg); - if (p_dm_odm->cut_version == ODM_CUT_A) - phydm_phypara_a_cut(p_dm_odm); + if (dm->cut_version == ODM_CUT_A) + phydm_phypara_a_cut(dm); } else if (config_type == CONFIG_BB_AGC_TAB) READ_AND_CONFIG_MP(8197f, _agc_tab); - /* else if(config_type == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG_MP(8197f, _phy_reg_pg); - else if(config_type == CONFIG_BB_PHY_REG_MP) - READ_AND_CONFIG_MP(8197f, _phy_reg_mp); */ } #endif - +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) { + if (config_type == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG_MP(8192f, _phy_reg); + } else if (config_type == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG_MP(8192f, _agc_tab); + } else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type1); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type5); + else if (dm->rfe_type == 6) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type6); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type8); + else if (dm->rfe_type == 9) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type9); + else if (dm->rfe_type == 10) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type10); + else if (dm->rfe_type == 11) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type11); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type12); + else if (dm->rfe_type == 13) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type13); + else if (dm->rfe_type == 14) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type14); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type18); + else if (dm->rfe_type == 19) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type19); + else if (dm->rfe_type == 20) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type20); + else if (dm->rfe_type == 21) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type21); + else if (dm->rfe_type == 22) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type22); + else if (dm->rfe_type == 23) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type23); + else if (dm->rfe_type == 24) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type24); + else if (dm->rfe_type == 25) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type25); + else if (dm->rfe_type == 26) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type26); + else if (dm->rfe_type == 27) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type27); + else if (dm->rfe_type == 28) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type28); + else if (dm->rfe_type == 29) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type29); + else if (dm->rfe_type == 30) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type30); + else if (dm->rfe_type == 31) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type31); + else + READ_AND_CONFIG_MP(8192f, _phy_reg_pg); + } + } +#endif #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) { - if (config_type == CONFIG_BB_PHY_REG) + if (dm->support_ic_type == ODM_RTL8821C) { + if (config_type == CONFIG_BB_PHY_REG) { READ_AND_CONFIG(8821c, _phy_reg); - else if (config_type == CONFIG_BB_AGC_TAB) { + } else if (config_type == CONFIG_BB_AGC_TAB) { READ_AND_CONFIG(8821c, _agc_tab); - /* According to RFEtype, choosing correct AGC table*/ - if (p_dm_odm->default_rf_set_8821c == SWITCH_TO_BTG) + /* @According to RFEtype, choosing correct AGC table*/ + if (dm->default_rf_set_8821c == SWITCH_TO_BTG) AGC_DIFF_CONFIG_MP(8821c, btg); - } else if (config_type == CONFIG_BB_PHY_REG_PG) - READ_AND_CONFIG(8821c, _phy_reg_pg); - else if (config_type == CONFIG_BB_AGC_TAB_DIFF) { - if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_BTG) + } else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->rfe_type == 0x5) + READ_AND_CONFIG(8821c, _phy_reg_pg_type0x28); + else + READ_AND_CONFIG(8821c, _phy_reg_pg); + } else if (config_type == CONFIG_BB_AGC_TAB_DIFF) { + dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD; + /*@AGC_TAB DIFF dont support FW offload*/ + if (dm->current_rf_set_8821c == SWITCH_TO_BTG) AGC_DIFF_CONFIG_MP(8821c, btg); - else if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_WLG) + else if (dm->current_rf_set_8821c == SWITCH_TO_WLG) AGC_DIFF_CONFIG_MP(8821c, wlg); + } else if (config_type == CONFIG_BB_PHY_REG_MP) { + READ_AND_CONFIG(8821c, _phy_reg_mp); } } #endif #if (RTL8195A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8195A) { + if (dm->support_ic_type == ODM_RTL8195A) { if (config_type == CONFIG_BB_PHY_REG) READ_AND_CONFIG(8195a, _phy_reg); else if (config_type == CONFIG_BB_AGC_TAB) @@ -2640,1161 +1020,296 @@ odm_config_bb_with_header_file( READ_AND_CONFIG(8195a, _phy_reg_pg); } #endif - - return ret; -} - -enum hal_status -odm_config_mac_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; -#endif - enum hal_status ret = HAL_STATUS_SUCCESS; - - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("===>odm_config_mac_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, - ("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n", - p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); - - /* 1 AP doesn't use PHYDM initialization in these ICs */ -#if (DM_ODM_SUPPORT_TYPE != ODM_AP) -#if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - READ_AND_CONFIG_MP(8812a, _mac_reg); -#endif -#if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - READ_AND_CONFIG_MP(8821a, _mac_reg); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigMACwithHeaderFile\n")); +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG(8195b, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG(8195b, _agc_tab); + /*@else if (config_type == CONFIG_BB_PHY_REG_PG)*/ + /* READ_AND_CONFIG(8195b, _phy_reg_pg);*/ } #endif -#if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) - READ_AND_CONFIG_MP(8192e, _mac_reg); -#endif -#if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723D) - READ_AND_CONFIG_MP(8723d, _mac_reg); -#endif -/* JJ ADD 20161014 */ -#if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8710B) - READ_AND_CONFIG_MP(8710b, _mac_reg); -#endif - -#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ - - /* 1 All platforms support */ -#if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - READ_AND_CONFIG_MP(8188e, _mac_reg); -#endif -#if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) - READ_AND_CONFIG_MP(8723b, _mac_reg); -#endif -#if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) - READ_AND_CONFIG_MP(8814a, _mac_reg); -#endif -#if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8703B) - READ_AND_CONFIG_MP(8703b, _mac_reg); -#endif -#if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) - READ_AND_CONFIG_MP(8188f, _mac_reg); -#endif -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) - { - READ_AND_CONFIG_MP(8822b, _mac_reg); -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if(p_dm_odm->halmac_ability & ODM_PHY_PARAM_OFFLOAD) - { - RT_STATUS status = RT_STATUS_SUCCESS; - status = HAL_MAC_Config_PHY_WriteNByte(&GET_HAL_MAC_INFO(p_dm_odm->adapter), - HALMAC_PARAMETER_CMD_END, - 0, - 0, - FALSE, - 0, - TRUE, - 0, - 0); - if(status != RT_STATUS_SUCCESS) - ret = HAL_STATUS_FAILURE; - RT_TRACE(COMP_INIT, DBG_LOUD, ("MAC param. offload status = %x\n",status)); +#if (RTL8198F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8198F) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8198f, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8198f, _agc_tab); + } +#endif + + if (config_type == CONFIG_BB_PHY_REG || + config_type == CONFIG_BB_AGC_TAB) + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + result = phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_END, + 0, + 0, + 0, + (enum rf_path)0, + 0); + PHYDM_DBG(dm, ODM_COMP_INIT, + "phy param offload end!result = %d", result); } -#endif - } -#endif - -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8197F) - READ_AND_CONFIG_MP(8197f, _mac_reg); -#endif - -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - READ_AND_CONFIG(8821c, _mac_reg); -#endif - -#if (RTL8195A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8195A) - READ_AND_CONFIG_MP(8195a, _mac_reg); -#endif - return ret; + return result; } enum hal_status -odm_config_fw_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_fw_config_type config_type, - u8 *p_firmware, - u32 *p_size -) +odm_config_mac_with_header_file(struct dm_struct *dm) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + enum hal_status result = HAL_STATUS_SUCCESS; -#if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { -#ifdef CONFIG_SFW_SUPPORTED - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188e_t, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8188e_t, _fw_wowlan); - else if (config_type == CONFIG_FW_NIC_2) - READ_FIRMWARE_MP(8188e_s, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN_2) - READ_FIRMWARE_MP(8188e_s, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - if (config_type == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188e_t, _fw_ap); - else if (config_type == CONFIG_FW_AP_2) - READ_FIRMWARE_MP(8188e_s, _fw_ap); -#endif /* CONFIG_AP_WOWLAN */ -#else - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188e_t, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8188e_t, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188e_t, _fw_ap); -#endif /* CONFIG_AP_WOWLAN */ -#endif - } -#endif -#if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8723b, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8723b, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE(8723b, _fw_ap); -#endif + PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__, + (dm->is_mp_chip) ? "MPChip" : "TestChip"); + PHYDM_DBG(dm, ODM_COMP_INIT, + "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", + dm->support_platform, dm->support_interface, dm->board_type); - } -#endif /* #if (RTL8723B_SUPPORT == 1) */ +/* @1 AP doesn't use PHYDM initialization in these ICs */ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8812a, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8812a, _fw_wowlan); - else if (config_type == CONFIG_FW_BT) - READ_FIRMWARE_MP(8812a, _fw_nic_bt); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE(8812a, _fw_ap); -#endif - } + if (dm->support_ic_type == ODM_RTL8812) + READ_AND_CONFIG_MP(8812a, _mac_reg); #endif #if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8821a, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8821a, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8821a, _fw_ap); -#endif /*CONFIG_AP_WOWLAN*/ - else if (config_type == CONFIG_FW_BT) - READ_FIRMWARE_MP(8821a, _fw_nic_bt); - } + if (dm->support_ic_type == ODM_RTL8821) + READ_AND_CONFIG_MP(8821a, _mac_reg); #endif #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8192e, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8192e, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8192e, _fw_ap); -#endif - } + if (dm->support_ic_type == ODM_RTL8192E) + READ_AND_CONFIG_MP(8192e, _mac_reg); #endif #if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723D) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8723d, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) { - READ_FIRMWARE_MP(8723d, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8723d, _fw_ap); -#endif - } - } + if (dm->support_ic_type == ODM_RTL8723D) + READ_AND_CONFIG_MP(8723d, _mac_reg); #endif -/* JJ ADD 20161014 */ +/* @JJ ADD 20161014 */ #if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8710B) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8710b, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) { - READ_FIRMWARE_MP(8710b, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8710b, _fw_ap); + if (dm->support_ic_type == ODM_RTL8710B) + READ_AND_CONFIG_MP(8710b, _mac_reg); #endif - } - } +#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */ +/* @1 All platforms support */ +#if (RTL8188E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) + READ_AND_CONFIG_MP(8188e, _mac_reg); #endif - - /*#if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) - { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8814a, _fw_nic); - else if (config_type == config_fw_wowlan) - READ_FIRMWARE_MP(8814a, _fw_wowlan); - #ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8814a, _fw_ap); - #endif - } - #endif */ - -#if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8814a, _fw_nic); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8814a, _fw_ap); +#if (RTL8723B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8723B) + READ_AND_CONFIG_MP(8723b, _mac_reg); #endif - } +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8814A) + READ_AND_CONFIG_MP(8814a, _mac_reg); #endif - #if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8703B) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8703b, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8703b, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE(8703b, _fw_ap); -#endif - } + if (dm->support_ic_type == ODM_RTL8703B) + READ_AND_CONFIG_MP(8703b, _mac_reg); #endif - #if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8188f, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8188f, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == CONFIG_FW_AP) - READ_FIRMWARE_MP(8188f, _fw_ap); -#endif - } + if (dm->support_ic_type == ODM_RTL8188F) + READ_AND_CONFIG_MP(8188f, _mac_reg); #endif - #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8822b, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8822b, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE(8822b, _fw_ap); -#endif - } + if (dm->support_ic_type == ODM_RTL8822B) + READ_AND_CONFIG_MP(8822b, _mac_reg); #endif - #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8197F) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8197f, _fw_nic); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE(8197f, _fw_ap); -#endif - } + if (dm->support_ic_type == ODM_RTL8197F) + READ_AND_CONFIG_MP(8197f, _mac_reg); #endif -#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN)) +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) + READ_AND_CONFIG_MP(8192f, _mac_reg); +#endif #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) { - if (config_type == CONFIG_FW_NIC) - READ_FIRMWARE_MP(8821c, _fw_nic); - else if (config_type == CONFIG_FW_WOWLAN) - READ_FIRMWARE_MP(8821c, _fw_wowlan); -#ifdef CONFIG_AP_WOWLAN - else if (config_type == config_fw_ap_wowlan) - READ_FIRMWARE_MP(8821c, _fw_ap); -#endif /*CONFIG_AP_WOWLAN*/ - } + if (dm->support_ic_type == ODM_RTL8821C) + READ_AND_CONFIG(8821c, _mac_reg); +#endif +#if (RTL8195A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195A) + READ_AND_CONFIG_MP(8195a, _mac_reg); #endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + READ_AND_CONFIG_MP(8195b, _mac_reg); +#endif +#if (RTL8198F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8198F) + READ_AND_CONFIG_MP(8198f, _mac_reg); #endif -#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ - return HAL_STATUS_SUCCESS; + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + result = phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_END, + 0, + 0, + 0, + (enum rf_path)0, + 0); + PHYDM_DBG(dm, ODM_COMP_INIT, + "mac param offload end!result = %d", result); + } + + return result; } -u32 -odm_get_hw_img_version( - struct PHY_DM_STRUCT *p_dm_odm -) +u32 odm_get_hw_img_version(struct dm_struct *dm) { - u32 version = 0; + u32 version = 0; - /* 1 AP doesn't use PHYDM initialization in these ICs */ +/* @1 AP doesn't use PHYDM initialization in these ICs */ #if (DM_ODM_SUPPORT_TYPE != ODM_AP) #if (RTL8821A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821) + if (dm->support_ic_type == ODM_RTL8821) version = GET_VERSION_MP(8821a, _mac_reg); #endif #if (RTL8192E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8192E) + if (dm->support_ic_type == ODM_RTL8192E) version = GET_VERSION_MP(8192e, _mac_reg); #endif #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) + if (dm->support_ic_type == ODM_RTL8812) version = GET_VERSION_MP(8812a, _mac_reg); #endif #if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723D) + if (dm->support_ic_type == ODM_RTL8723D) version = GET_VERSION_MP(8723d, _mac_reg); #endif -/* JJ ADD 20161014 */ +/* @JJ ADD 20161014 */ #if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8710B) + if (dm->support_ic_type == ODM_RTL8710B) version = GET_VERSION_MP(8710b, _mac_reg); #endif +#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */ -#endif /* (DM_ODM_SUPPORT_TYPE != ODM_AP) */ - - /*1 All platforms support*/ +/*@1 All platforms support*/ #if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) + if (dm->support_ic_type == ODM_RTL8188E) version = GET_VERSION_MP(8188e, _mac_reg); #endif #if (RTL8723B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8723B) + if (dm->support_ic_type == ODM_RTL8723B) version = GET_VERSION_MP(8723b, _mac_reg); #endif #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) + if (dm->support_ic_type == ODM_RTL8814A) version = GET_VERSION_MP(8814a, _mac_reg); #endif #if (RTL8703B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8703B) + if (dm->support_ic_type == ODM_RTL8703B) version = GET_VERSION_MP(8703b, _mac_reg); #endif #if (RTL8188F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188F) + if (dm->support_ic_type == ODM_RTL8188F) version = GET_VERSION_MP(8188f, _mac_reg); #endif #if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) + if (dm->support_ic_type == ODM_RTL8822B) version = GET_VERSION_MP(8822b, _mac_reg); #endif - #if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8197F) + if (dm->support_ic_type == ODM_RTL8197F) version = GET_VERSION_MP(8197f, _mac_reg); #endif -#if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - version = GET_VERSION(8821c, _mac_reg); -#endif - - return version; -} - -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) -/* For 8822B only!! need to move to FW finally */ -/*==============================================*/ - -boolean -phydm_query_is_mu_api( - struct PHY_DM_STRUCT *p_phydm, - u8 ppdu_idx, - u8 *p_data_rate, - u8 *p_gid -) -{ - u8 data_rate = 0, gid = 0; - boolean is_mu = FALSE; - - data_rate = p_phydm->phy_dbg_info.num_of_ppdu[ppdu_idx]; - gid = p_phydm->phy_dbg_info.gid_num[ppdu_idx]; - - if (data_rate & BIT(7)) { - is_mu = TRUE; - data_rate = data_rate & ~(BIT(7)); - } else - is_mu = FALSE; - - *p_data_rate = data_rate; - *p_gid = gid; - - return is_mu; - -} - -VOID -phydm_rx_statistic_cal( - struct PHY_DM_STRUCT *p_phydm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - struct _phy_status_rpt_jaguar2_type1 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status; - u8 date_rate = p_pktinfo->data_rate & ~(BIT(7)); - - if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63)) { - if (date_rate >= ODM_RATEVHTSS1MCS0) { - p_phydm->phy_dbg_info.num_qry_mu_vht_pkt[date_rate - 0x2C]++; - if (p_pktinfo->ppdu_cnt < 4) { - p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate | BIT(7); - p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid; - } - } - - } else { - if (date_rate >= ODM_RATEVHTSS1MCS0) { - p_phydm->phy_dbg_info.num_qry_vht_pkt[date_rate - 0x2C]++; - if (p_pktinfo->ppdu_cnt < 4) { - p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate; - p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid; - } - } - } - -} - -void -phydm_reset_phy_info( - struct PHY_DM_STRUCT *p_phydm, - struct _odm_phy_status_info_ *p_phy_info -) -{ - p_phy_info->rx_pwdb_all = 0; - p_phy_info->signal_quality = 0; - p_phy_info->band_width = 0; - p_phy_info->rx_count = 0; - odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_quality, 0, 4); - odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_strength, 0, 4); - odm_memory_set(p_phydm, p_phy_info->rx_snr, 0, 4); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->rx_power = -110; - p_phy_info->recv_signal_power = -110; - p_phy_info->bt_rx_rssi_percentage = 0; - p_phy_info->signal_strength = 0; - p_phy_info->bt_coex_pwr_adjust = 0; - p_phy_info->channel = 0; - p_phy_info->is_mu_packet = 0; - p_phy_info->is_beamformed = 0; - p_phy_info->rxsc = 0; - odm_memory_set(p_phydm, p_phy_info->rx_pwr, -110, 4); - /*odm_memory_set(p_phydm, p_phy_info->rx_mimo_evm_dbm, 0, 4);*/ - odm_memory_set(p_phydm, p_phy_info->cfo_short, 0, 8); - odm_memory_set(p_phydm, p_phy_info->cfo_tail, 0, 8); -#endif - odm_memory_set(p_phydm, p_phy_info->rx_mimo_evm_dbm, 0, 4); -} - -void -phydm_set_per_path_phy_info( - u8 rx_path, - s8 rx_pwr, - s8 rx_evm, - s8 cfo_tail, - s8 rx_snr, - struct _odm_phy_status_info_ *p_phy_info -) -{ - u8 evm_dbm = 0; - u8 evm_percentage = 0; - - /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ - - if (rx_evm < 0) { - /* Calculate EVM in dBm */ - evm_dbm = ((u8)(0 - rx_evm) >> 1); - - /* Calculate EVM in percentage */ - if (evm_dbm >= 34) - evm_percentage = 100; - else - evm_percentage = (evm_dbm << 1) + (evm_dbm); - } - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->rx_pwr[rx_path] = rx_pwr; - /*p_phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;*/ - - /* CFO = CFO_tail * 312.5 / 2^7 ~= CFO tail * 39/512 (kHz)*/ - p_phy_info->cfo_tail[rx_path] = cfo_tail; - p_phy_info->cfo_tail[rx_path] = ((p_phy_info->cfo_tail[rx_path] << 5) + (p_phy_info->cfo_tail[rx_path] << 2) + - (p_phy_info->cfo_tail[rx_path] << 1) + (p_phy_info->cfo_tail[rx_path])) >> 9; -#endif - if (evm_dbm == 64) - evm_dbm = 0; /*if 1SS rate, evm_dbm [2nd stream] =64*/ - - p_phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm; - - p_phy_info->rx_mimo_signal_strength[rx_path] = odm_query_rx_pwr_percentage(rx_pwr); - p_phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage; - p_phy_info->rx_snr[rx_path] = rx_snr >> 1; - -#if 0 - /* if (p_pktinfo->is_packet_match_bssid) */ - { - dbg_print("path (%d)--------\n", rx_path); - dbg_print("rx_pwr = %d, Signal strength = %d\n", p_phy_info->rx_pwr[rx_path], p_phy_info->rx_mimo_signal_strength[rx_path]); - dbg_print("evm_dbm = %d, Signal quality = %d\n", p_phy_info->rx_mimo_evm_dbm[rx_path], p_phy_info->rx_mimo_signal_quality[rx_path]); - dbg_print("CFO = %d, SNR = %d\n", p_phy_info->cfo_tail[rx_path], p_phy_info->rx_snr[rx_path]); - } -#endif -} - -void -phydm_set_common_phy_info( - s8 rx_power, - u8 channel, - boolean is_beamformed, - boolean is_mu_packet, - u8 bandwidth, - u8 signal_quality, - u8 rxsc, - struct _odm_phy_status_info_ *p_phy_info -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - p_phy_info->rx_power = rx_power; /* RSSI in dB */ - p_phy_info->recv_signal_power = rx_power; /* RSSI in dB */ - p_phy_info->channel = channel; /* channel number */ - p_phy_info->is_beamformed = is_beamformed; /* apply BF */ - p_phy_info->is_mu_packet = is_mu_packet; /* MU packet */ - p_phy_info->rxsc = rxsc; -#endif - p_phy_info->rx_pwdb_all = odm_query_rx_pwr_percentage(rx_power); /* RSSI in percentage */ - p_phy_info->signal_quality = signal_quality; /* signal quality */ - p_phy_info->band_width = bandwidth; /* bandwidth */ - -#if 0 - /* if (p_pktinfo->is_packet_match_bssid) */ - { - dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", p_phy_info->rx_pwdb_all, p_phy_info->rx_power, p_phy_info->recv_signal_power); - dbg_print("signal_quality = %d\n", p_phy_info->signal_quality); - dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", p_phy_info->is_beamformed, p_phy_info->is_mu_packet, p_phy_info->rx_count + 1); - dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, rxsc, bandwidth); - } -#endif -} - -void -phydm_get_rx_phy_status_type0( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _odm_phy_status_info_ *p_phy_info -) -{ - /* type 0 is used for cck packet */ - - struct _phy_status_rpt_jaguar2_type0 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type0 *)p_phy_status; - u8 i, SQ = 0; - s8 rx_power = p_phy_sta_rpt->pwdb - 110; - - -#if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8723D) - rx_power = p_phy_sta_rpt->pwdb - 97; -#endif - -/* RTL8710B do not need recalculate the offset By James Liao@20170527 */ -#if (RTL8710B_SUPPORT == 1) - //if (p_dm_odm->support_ic_type & ODM_RTL8710B) - //rx_power = p_phy_sta_rpt->pwdb - 97; +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) + version = GET_VERSION_MP(8192f, _mac_reg); #endif - #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8821C) { - if (p_phy_sta_rpt->pwdb >= -57) - rx_power = p_phy_sta_rpt->pwdb - 100; - else - rx_power = p_phy_sta_rpt->pwdb - 102; - } -#endif - /* Calculate Signal Quality*/ - if (p_pktinfo->is_packet_match_bssid) { - if (p_phy_sta_rpt->signal_quality >= 64) - SQ = 0; - else if (p_phy_sta_rpt->signal_quality <= 20) - SQ = 100; - else { - /* mapping to 2~99% */ - SQ = 64 - p_phy_sta_rpt->signal_quality; - SQ = ((SQ << 3) + SQ) >> 2; - } - } - - /* Modify CCK PWDB if old AGC */ - if (p_dm_odm->cck_new_agc == false) { - u8 lna_idx, vga_idx; - -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - lna_idx = p_phy_sta_rpt->lna_l; - else -#endif - lna_idx = ((p_phy_sta_rpt->lna_h << 3) | p_phy_sta_rpt->lna_l); - vga_idx = p_phy_sta_rpt->vga; - -#if (RTL8723D_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8723D) - rx_power = odm_cckrssi_8723d(lna_idx, vga_idx); -#endif -/* JJ ADD 20161014 */ -#if (RTL8710B_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8710B) - rx_power = odm_cckrssi_8710b(lna_idx, vga_idx); -#endif - -#if (RTL8822B_SUPPORT == 1) - /* Need to do !! */ - /*if (p_dm_odm->support_ic_type & ODM_RTL8822B) */ - /*rx_power = odm_CCKRSSI_8822B(LNA_idx, VGA_idx);*/ -#endif -#if (RTL8197F_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8197F) - rx_power = odm_cckrssi_8197f(p_dm_odm, lna_idx, vga_idx); -#endif - } - - /* Update CCK packet counter */ - p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++; - - /*CCK no STBC and LDPC*/ - p_dm_odm->phy_dbg_info.is_ldpc_pkt = false; - p_dm_odm->phy_dbg_info.is_stbc_pkt = false; - - /* Update Common information */ - phydm_set_common_phy_info(rx_power, p_phy_sta_rpt->channel, false, - false, ODM_BW20M, SQ, p_phy_sta_rpt->rxsc, p_phy_info); - - /* Update CCK pwdb */ - phydm_set_per_path_phy_info(ODM_RF_PATH_A, rx_power, 0, 0, 0, p_phy_info); /* Update per-path information */ - - p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a; - p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b; - p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c; - p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d; -#if 0 - /* if (p_pktinfo->is_packet_match_bssid) */ - { - dbg_print("pwdb = 0x%x, MP gain index = 0x%x, TRSW = 0x%x\n", p_phy_sta_rpt->pwdb, p_phy_sta_rpt->gain, p_phy_sta_rpt->trsw); - dbg_print("channel = %d, band = %d, rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->rxsc); - dbg_print("agc_table = 0x%x, agc_rpt 0x%x, bb_power = 0x%x\n", p_phy_sta_rpt->agc_table, p_phy_sta_rpt->agc_rpt, p_phy_sta_rpt->bb_power); - dbg_print("length = %d, SQ = %d\n", p_phy_sta_rpt->length, p_phy_sta_rpt->signal_quality); - dbg_print("antidx a = 0x%x, b = 0x%x, c = 0x%x, d = 0x%x\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d); - dbg_print("rsvd_0 = 0x%x, rsvd_1 = 0x%x, rsvd_2 = 0x%x\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2); - dbg_print("rsvd_3 = 0x%x, rsvd_4 = 0x%x, rsvd_5 = 0x%x\n", p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5); - dbg_print("rsvd_6 = 0x%x, rsvd_7 = 0x%x, rsvd_8 = 0x%x\n", p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7, p_phy_sta_rpt->rsvd_8); - } -#endif -} - -void -phydm_get_rx_phy_status_type1( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _odm_phy_status_info_ *p_phy_info -) -{ - /* type 1 is used for ofdm packet */ - - struct _phy_status_rpt_jaguar2_type1 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status; - s8 rx_pwr_db = -120; - u8 i, rxsc, bw = ODM_BW20M, rx_count = 0; - boolean is_mu; - u8 num_ss; - - /* Update OFDM packet counter */ - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; - - /* Update per-path information */ - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (p_dm_odm->rx_ant_status & BIT(i)) { - s8 rx_path_pwr_db; - - /* RX path counter */ - rx_count++; - - /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ - /* EVM report is reported by stream, not path */ - rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ - phydm_set_per_path_phy_info(i, rx_path_pwr_db, p_phy_sta_rpt->rxevm[rx_count - 1], - p_phy_sta_rpt->cfo_tail[i], p_phy_sta_rpt->rxsnr[i], p_phy_info); - - /* search maximum pwdb */ - if (rx_path_pwr_db > rx_pwr_db) - rx_pwr_db = rx_path_pwr_db; - } - } - - /* mapping RX counter from 1~4 to 0~3 */ - if (rx_count > 0) - p_phy_info->rx_count = rx_count - 1; - - /* Check if MU packet or not */ - if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63)) { - is_mu = true; - p_dm_odm->phy_dbg_info.num_qry_mu_pkt++; - } else - is_mu = false; - - /* count BF packet */ - p_dm_odm->phy_dbg_info.num_qry_bf_pkt = p_dm_odm->phy_dbg_info.num_qry_bf_pkt + p_phy_sta_rpt->beamformed; - - /*STBC or LDPC pkt*/ - p_dm_odm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc; - p_dm_odm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc; - - /* Check sub-channel */ - if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0)) - rxsc = p_phy_sta_rpt->l_rxsc; - else - rxsc = p_phy_sta_rpt->ht_rxsc; - - /* Check RX bandwidth */ - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { - if ((rxsc >= 1) && (rxsc <= 8)) - bw = ODM_BW20M; - else if ((rxsc >= 9) && (rxsc <= 12)) - bw = ODM_BW40M; - else if (rxsc >= 13) - bw = ODM_BW80M; - else - bw = p_phy_sta_rpt->rf_mode; - } else if (p_dm_odm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {/* JJ ADD 20161014 */ - if (p_phy_sta_rpt->rf_mode == 0) - bw = ODM_BW20M; - else if ((rxsc == 1) || (rxsc == 2)) - bw = ODM_BW20M; - else - bw = ODM_BW40M; - } - - /* Update packet information */ - phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed, - is_mu, bw, odm_evm_db_to_percentage(p_phy_sta_rpt->rxevm[0]), rxsc, p_phy_info); - - num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); - - odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->cfo_tail, num_ss); - p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a; - p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b; - p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c; - p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d; - - if (p_pktinfo->is_packet_match_bssid) { - /* - dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d, rf_mode = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc, p_phy_sta_rpt->rf_mode); - dbg_print("Antidx A = %d, B = %d, C = %d, D = %d\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d); - dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]); - dbg_print("EVM A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxevm[0], p_phy_sta_rpt->rxevm[1], p_phy_sta_rpt->rxevm[2], p_phy_sta_rpt->rxevm[3]); - dbg_print("SNR A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxsnr[0], p_phy_sta_rpt->rxsnr[1], p_phy_sta_rpt->rxsnr[2], p_phy_sta_rpt->rxsnr[3]); - dbg_print("CFO A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->cfo_tail[0], p_phy_sta_rpt->cfo_tail[1], p_phy_sta_rpt->cfo_tail[2], p_phy_sta_rpt->cfo_tail[3]); - dbg_print("paid = %d, gid = %d, length = %d\n", (p_phy_sta_rpt->paid + (p_phy_sta_rpt->paid_msb<<8)), p_phy_sta_rpt->gid, p_phy_sta_rpt->lsig_length); - dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu); - dbg_print("NBI: %d, pos: %d\n", p_phy_sta_rpt->nb_intf_flag, (p_phy_sta_rpt->intf_pos + (p_phy_sta_rpt->intf_pos_msb<<8))); - dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5); - */ - phydm_rx_statistic_cal(p_dm_odm, p_phy_status, p_pktinfo); - } - /* - dbg_print("phydm_get_rx_phy_status_type1 p_pktinfo->is_packet_match_bssid = %d\n", p_pktinfo->is_packet_match_bssid); - dbg_print("p_pktinfo->data_rate = 0x%x\n", p_pktinfo->data_rate); - */ -} - -void -phydm_get_rx_phy_status_type2( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _odm_phy_status_info_ *p_phy_info -) -{ - struct _phy_status_rpt_jaguar2_type2 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type2 *)p_phy_status; - s8 rx_pwr_db = -120; - u8 i, rxsc, bw = ODM_BW20M, rx_count = 0; - - /* Update OFDM packet counter */ - p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; - - /* Update per-path information */ - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (p_dm_odm->rx_ant_status & BIT(i)) { - s8 rx_path_pwr_db; - - /* RX path counter */ - rx_count++; - - /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ -#if (RTL8197F_SUPPORT == 1) - if ((p_dm_odm->support_ic_type & ODM_RTL8197F) && (p_phy_sta_rpt->pwdb[i] == 0x7f)) { /*for 97f workaround*/ - - if (i == ODM_RF_PATH_A) { - rx_path_pwr_db = (p_phy_sta_rpt->gain_a) << 1; - rx_path_pwr_db = rx_path_pwr_db - 110; - } else if (i == ODM_RF_PATH_B) { - rx_path_pwr_db = (p_phy_sta_rpt->gain_b) << 1; - rx_path_pwr_db = rx_path_pwr_db - 110; - } else - rx_path_pwr_db = 0; - } else -#endif - rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ - - phydm_set_per_path_phy_info(i, rx_path_pwr_db, 0, 0, 0, p_phy_info); - - /* search maximum pwdb */ - if (rx_path_pwr_db > rx_pwr_db) - rx_pwr_db = rx_path_pwr_db; - } - } - - /* mapping RX counter from 1~4 to 0~3 */ - if (rx_count > 0) - p_phy_info->rx_count = rx_count - 1; - - /* Check RX sub-channel */ - if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0)) - rxsc = p_phy_sta_rpt->l_rxsc; - else - rxsc = p_phy_sta_rpt->ht_rxsc; - - /*STBC or LDPC pkt*/ - p_dm_odm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc; - p_dm_odm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc; - - /* Check RX bandwidth */ - /* the BW information of sc=0 is useless, because there is no information of RF mode*/ - - if (p_dm_odm->support_ic_type & ODM_RTL8822B) { - if ((rxsc >= 1) && (rxsc <= 8)) - bw = ODM_BW20M; - else if ((rxsc >= 9) && (rxsc <= 12)) - bw = ODM_BW40M; - else if (rxsc >= 13) - bw = ODM_BW80M; - else - bw = ODM_BW20M; - } else if (p_dm_odm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {/* JJ ADD 20161014 */ - if (rxsc == 3) - bw = ODM_BW40M; - else if ((rxsc == 1) || (rxsc == 2)) - bw = ODM_BW20M; - else - bw = ODM_BW20M; - } - - /* Update packet information */ - phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed, - false, bw, 0, rxsc, p_phy_info); - -#if 0 - /* if (p_pktinfo->is_packet_match_bssid) */ - { - dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc); - dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]); - dbg_print("Agc table A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->agc_table_a, p_phy_sta_rpt->agc_table_b, p_phy_sta_rpt->agc_table_c, p_phy_sta_rpt->agc_table_d); - dbg_print("Gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->gain_a, p_phy_sta_rpt->gain_b, p_phy_sta_rpt->gain_c, p_phy_sta_rpt->gain_d); - dbg_print("TRSW A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->trsw_a, p_phy_sta_rpt->trsw_b, p_phy_sta_rpt->trsw_c, p_phy_sta_rpt->trsw_d); - dbg_print("AAGC step A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->aagc_step_a, p_phy_sta_rpt->aagc_step_b, p_phy_sta_rpt->aagc_step_c, p_phy_sta_rpt->aagc_step_d); - dbg_print("HT AAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->ht_aagc_gain[0], p_phy_sta_rpt->ht_aagc_gain[1], p_phy_sta_rpt->ht_aagc_gain[2], p_phy_sta_rpt->ht_aagc_gain[3]); - dbg_print("DAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->dagc_gain[0], p_phy_sta_rpt->dagc_gain[1], p_phy_sta_rpt->dagc_gain[2], p_phy_sta_rpt->dagc_gain[3]); - dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu); - dbg_print("counter: %d, syn_count: %d\n", p_phy_sta_rpt->counter, p_phy_sta_rpt->syn_count); - dbg_print("cnt_cca2agc_rdy: %d, cnt_pw2cca: %d, shift_l_map\n", p_phy_sta_rpt->cnt_cca2agc_rdy, p_phy_sta_rpt->cnt_pw2cca, p_phy_sta_rpt->shift_l_map); - dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4); - dbg_print("rsvd_5 = %d, rsvd_6 = %d, rsvd_6 = %d\n", p_phy_sta_rpt->rsvd_5, p_phy_sta_rpt->rsvd_6, p_phy_sta_rpt->rsvd_7); - } -#endif -} - -void -phydm_get_rx_phy_status_type5( - u8 *p_phy_status -) -{ - /* - dbg_print("DW0: 0x%02x%02x%02x%02x\n", *(p_phy_status + 3), *(p_phy_status + 2), *(p_phy_status + 1), *(p_phy_status + 0)); - dbg_print("DW1: 0x%02x%02x%02x%02x\n", *(p_phy_status + 7), *(p_phy_status + 6), *(p_phy_status + 5), *(p_phy_status + 4)); - dbg_print("DW2: 0x%02x%02x%02x%02x\n", *(p_phy_status + 11), *(p_phy_status + 10), *(p_phy_status + 9), *(p_phy_status + 8)); - dbg_print("DW3: 0x%02x%02x%02x%02x\n", *(p_phy_status + 15), *(p_phy_status + 14), *(p_phy_status + 13), *(p_phy_status + 12)); - dbg_print("DW4: 0x%02x%02x%02x%02x\n", *(p_phy_status + 19), *(p_phy_status + 18), *(p_phy_status + 17), *(p_phy_status + 16)); - dbg_print("DW5: 0x%02x%02x%02x%02x\n", *(p_phy_status + 23), *(p_phy_status + 22), *(p_phy_status + 21), *(p_phy_status + 20)); - dbg_print("DW6: 0x%02x%02x%02x%02x\n", *(p_phy_status + 27), *(p_phy_status + 26), *(p_phy_status + 25), *(p_phy_status + 24)); - */ -} - -void -phydm_process_rssi_for_dm_new_type( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - struct _odm_per_pkt_info_ *p_pktinfo -) -{ - s32 undecorated_smoothed_pwdb, accumulate_pwdb; - u32 rssi_ave; - u8 i; - struct sta_info *p_entry; - u8 scaling_factor = 4; - - if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) - return; - - p_entry = p_dm_odm->p_odm_sta_info[p_pktinfo->station_id]; - - if (!IS_STA_VALID(p_entry)) - return; - - if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/ - return; - - if (p_pktinfo->is_packet_beacon) - p_dm_odm->phy_dbg_info.num_qry_beacon_pkt++; - -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - if (p_dm_odm->support_ability & ODM_BB_ANT_DIV) - odm_process_rssi_for_ant_div(p_dm_odm, p_phy_info, p_pktinfo); -#endif - -#if (CONFIG_DYNAMIC_RX_PATH == 1) - phydm_process_phy_status_for_dynamic_rx_path(p_dm_odm, p_phy_info, p_pktinfo); - dbg_print("====>\n"); -#endif - - if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) { - u32 RSSI_linear = 0; - - p_dm_odm->rx_rate = p_pktinfo->data_rate; - undecorated_smoothed_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - accumulate_pwdb = p_dm_odm->accumulate_pwdb[p_pktinfo->station_id]; - p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; - p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; - p_dm_odm->RSSI_C = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C]; - p_dm_odm->RSSI_D = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D]; - - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { - if (p_phy_info->rx_mimo_signal_strength[i] != 0) - RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[i]); - } - - switch (p_phy_info->rx_count + 1) { - case 2: - RSSI_linear = (RSSI_linear >> 1); - break; - case 3: - RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */ - break; - case 4: - RSSI_linear = (RSSI_linear >> 2); - break; - } - rssi_ave = odm_convert_to_db(RSSI_linear); - - if (undecorated_smoothed_pwdb <= 0) { - accumulate_pwdb = (p_phy_info->rx_pwdb_all << scaling_factor); - undecorated_smoothed_pwdb = p_phy_info->rx_pwdb_all; - } else { - accumulate_pwdb = accumulate_pwdb - (accumulate_pwdb >> scaling_factor) + rssi_ave; - undecorated_smoothed_pwdb = (accumulate_pwdb + (1 << (scaling_factor - 1))) >> scaling_factor; - } - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - if (p_entry->rssi_stat.undecorated_smoothed_pwdb == -1) - phydm_ra_rssi_rpt_wk(p_dm_odm); -#endif - p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb; - p_dm_odm->accumulate_pwdb[p_pktinfo->station_id] = accumulate_pwdb; - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - if (p_pktinfo->station_id == 0) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); - - p_hal_data->UndecoratedSmoothedPWDB = undecorated_smoothed_pwdb; - } + if (dm->support_ic_type == ODM_RTL8821C) + version = GET_VERSION(8821c, _mac_reg); #endif - } -} - -void -phydm_rx_phy_status_new_type( - struct PHY_DM_STRUCT *p_phydm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _odm_phy_status_info_ *p_phy_info -) -{ - u8 phy_status_type = (*p_phy_status & 0xf); - - /*dbg_print("phydm_rx_phy_status_new_type================> (page: %d)\n", phy_status_type);*/ - - /* Memory reset */ - phydm_reset_phy_info(p_phydm, p_phy_info); - - /* Phy status parsing */ - switch (phy_status_type) { - case 0: - { - phydm_get_rx_phy_status_type0(p_phydm, p_phy_status, p_pktinfo, p_phy_info); - break; - } - case 1: - { - phydm_get_rx_phy_status_type1(p_phydm, p_phy_status, p_pktinfo, p_phy_info); - break; - } - case 2: - { - phydm_get_rx_phy_status_type2(p_phydm, p_phy_status, p_pktinfo, p_phy_info); - break; - } -#if 0 - case 5: - { - phydm_get_rx_phy_status_type5(p_phy_status); - return; - } +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + version = GET_VERSION(8195b, _mac_reg); #endif - default: - return; - } - - /* Update signal strength to UI, and p_phy_info->rx_pwdb_all is the maximum RSSI of all path */ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - p_phy_info->signal_strength = SignalScaleProc(p_phydm->adapter, p_phy_info->rx_pwdb_all, false, false); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_phydm, p_phy_info->rx_pwdb_all)); +#if (RTL8198F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8198F) + version = GET_VERSION_MP(8198f, _mac_reg); #endif - /* Calculate average RSSI and smoothed RSSI */ - phydm_process_rssi_for_dm_new_type(p_phydm, p_phy_info, p_pktinfo); - + return version; } -/*==============================================*/ -#endif -u32 -query_phydm_trx_capability( - struct PHY_DM_STRUCT *p_dm_odm -) +u32 query_phydm_trx_capability(struct dm_struct *dm) { u32 value32 = 0xFFFFFFFF; #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - value32 = query_phydm_trx_capability_8821c(p_dm_odm); + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_trx_capability_8821c(dm); +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + value32 = query_phydm_trx_capability_8195b(dm); #endif - return value32; } -u32 -query_phydm_stbc_capability( - struct PHY_DM_STRUCT *p_dm_odm -) +u32 query_phydm_stbc_capability(struct dm_struct *dm) { u32 value32 = 0xFFFFFFFF; #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - value32 = query_phydm_stbc_capability_8821c(p_dm_odm); + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_stbc_capability_8821c(dm); +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + value32 = query_phydm_stbc_capability_8195b(dm); #endif return value32; } -u32 -query_phydm_ldpc_capability( - struct PHY_DM_STRUCT *p_dm_odm -) +u32 query_phydm_ldpc_capability(struct dm_struct *dm) { u32 value32 = 0xFFFFFFFF; #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - value32 = query_phydm_ldpc_capability_8821c(p_dm_odm); + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_ldpc_capability_8821c(dm); +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + value32 = query_phydm_ldpc_capability_8195b(dm); #endif - return value32; } -u32 -query_phydm_txbf_parameters( - struct PHY_DM_STRUCT *p_dm_odm -) +u32 query_phydm_txbf_parameters(struct dm_struct *dm) { u32 value32 = 0xFFFFFFFF; #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - value32 = query_phydm_txbf_parameters_8821c(p_dm_odm); + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_txbf_parameters_8821c(dm); +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + value32 = query_phydm_txbf_parameters_8195b(dm); #endif - return value32; } -u32 -query_phydm_txbf_capability( - struct PHY_DM_STRUCT *p_dm_odm -) +u32 query_phydm_txbf_capability(struct dm_struct *dm) { u32 value32 = 0xFFFFFFFF; #if (RTL8821C_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8821C) - value32 = query_phydm_txbf_capability_8821c(p_dm_odm); + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_txbf_capability_8821c(dm); +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + value32 = query_phydm_txbf_capability_8195b(dm); #endif - return value32; } diff --git a/hal/phydm/phydm_hwconfig.h b/hal/phydm/phydm_hwconfig.h index e413034..7c4d1e3 100644 --- a/hal/phydm/phydm_hwconfig.h +++ b/hal/phydm/phydm_hwconfig.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,567 +8,72 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ - + * Larry Finger + * + *****************************************************************************/ -#ifndef __HALHWOUTSRC_H__ +#ifndef __HALHWOUTSRC_H__ #define __HALHWOUTSRC_H__ - -/*--------------------------Define -------------------------------------------*/ -#define CCK_RSSI_INIT_COUNT 5 - -#define RA_RSSI_STATE_INIT 0 -#define RA_RSSI_STATE_SEND 1 -#define RA_RSSI_STATE_HOLD 2 - -#define CFO_HW_RPT_2_MHZ(val) ((val<<1) + (val>>1)) -/* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */ - -#define AGC_DIFF_CONFIG_MP(ic, band) (odm_read_and_config_mp_##ic##_agc_tab_diff(p_dm_odm, array_mp_##ic##_agc_tab_diff_##band, \ - sizeof(array_mp_##ic##_agc_tab_diff_##band)/sizeof(u32))) -#define AGC_DIFF_CONFIG_TC(ic, band) (odm_read_and_config_tc_##ic##_agc_tab_diff(p_dm_odm, array_tc_##ic##_agc_tab_diff_##band, \ - sizeof(array_tc_##ic##_agc_tab_diff_##band)/sizeof(u32))) - -#define AGC_DIFF_CONFIG(ic, band) do {\ - if (p_dm_odm->is_mp_chip)\ - AGC_DIFF_CONFIG_MP(ic, band);\ - else\ - AGC_DIFF_CONFIG_TC(ic, band);\ +/*@--------------------------Define -------------------------------------------*/ +#define AGC_DIFF_CONFIG_MP(ic, band) \ + (odm_read_and_config_mp_##ic##_agc_tab_diff(dm, \ + array_mp_##ic##_agc_tab_diff_##band, \ + sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32))) +#define AGC_DIFF_CONFIG_TC(ic, band) \ + (odm_read_and_config_tc_##ic##_agc_tab_diff(dm, \ + array_tc_##ic##_agc_tab_diff_##band, \ + sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32))) +#if defined(DM_ODM_CE_MAC80211) +#else +#define AGC_DIFF_CONFIG(ic, band) \ + do { \ + if (dm->is_mp_chip) \ + AGC_DIFF_CONFIG_MP(ic, band); \ + else \ + AGC_DIFF_CONFIG_TC(ic, band); \ } while (0) - - -/* ************************************************************ - * structure and define - * ************************************************************ */ - -__PACK struct _phy_rx_agc_info { -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 gain: 7, trsw: 1; -#else - u8 trsw: 1, gain: 7; -#endif -}; - -__PACK struct _phy_status_rpt_8192cd { - struct _phy_rx_agc_info path_agc[2]; - u8 ch_corr[2]; - u8 cck_sig_qual_ofdm_pwdb_all; - u8 cck_agc_rpt_ofdm_cfosho_a; - u8 cck_rpt_b_ofdm_cfosho_b; - u8 rsvd_1;/*ch_corr_msb;*/ - u8 noise_power_db_msb; - s8 path_cfotail[2]; - u8 pcts_mask[2]; - s8 stream_rxevm[2]; - u8 path_rxsnr[2]; - u8 noise_power_db_lsb; - u8 rsvd_2[3]; - u8 stream_csi[2]; - u8 stream_target_csi[2]; - s8 sig_evm; - u8 rsvd_3; - -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/ - u8 sgi_en: 1; - u8 rxsc: 2; - u8 idle_long: 1; - u8 r_ant_train_en: 1; - u8 ant_sel_b: 1; - u8 ant_sel: 1; -#else /*_BIG_ENDIAN_ */ - u8 ant_sel: 1; - u8 ant_sel_b: 1; - u8 r_ant_train_en: 1; - u8 idle_long: 1; - u8 rxsc: 2; - u8 sgi_en: 1; - u8 antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/ -#endif -}; - - -struct _phy_status_rpt_8812 { - /* DWORD 0*/ - u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ - u8 chl_num_LSB; /*channel number[7:0]*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 chl_num_MSB: 2; /*channel number[9:8]*/ - u8 sub_chnl: 4; /*sub-channel location[3:0]*/ - u8 r_RFMOD: 2; /*RF mode[1:0]*/ -#else /*_BIG_ENDIAN_ */ - u8 r_RFMOD: 2; - u8 sub_chnl: 4; - u8 chl_num_MSB: 2; -#endif - - /* DWORD 1*/ - u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/ - s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - /*this should be checked again because the definition of 8812 and 8814 is different*/ - /* u8 r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/ - /* u8 cck_rx_path:4; cck rx path[3:0]*/ - u8 resvd_0: 6; - u8 bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/ -#else /*_BIG_ENDIAN_*/ - u8 bt_RF_ch_MSB: 2; - u8 resvd_0: 6; -#endif - - /* DWORD 2*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/ - u8 ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/ - u8 bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ -#else /*_BIG_ENDIAN_ */ - u8 bt_RF_ch_LSB: 6; - u8 ant_div_sw_b: 1; - u8 ant_div_sw_a: 1; #endif - s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ - u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ - u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ - - /* DWORD 3*/ - s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ - s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ - - /* DWORD 4*/ - u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/ - u8 pcts_rpt_valid: 1; /*pcts_rpt_valid*/ - u8 resvd_1: 1; /*1'b0*/ -#else /*_BIG_ENDIAN_*/ - u8 resvd_1: 1; - u8 pcts_rpt_valid: 1; - u8 PCTS_MSK_RPT_3: 6; -#endif - s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/ - - /* DWORD 5*/ - u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/ - u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/ - - /* DWORD 6*/ - s8 sigevm; /*signal field EVM*/ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/ - u8 antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/ - u8 dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/ - u8 GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/ -#else /*_BIG_ENDIAN_*/ - u8 GNT_BT_keep: 1; - u8 dpdt_ctrl_keep: 1; - u8 antidx_antd: 3; - u8 antidx_antc: 3; -#endif -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 antidx_anta: 3; /*antidx_anta[2:0]*/ - u8 antidx_antb: 3; /*antidx_antb[2:0]*/ - u8 hw_antsw_occur: 2; /*1'b0*/ -#else /*_BIG_ENDIAN_*/ - u8 hw_antsw_occur: 2; - u8 antidx_antb: 3; - u8 antidx_anta: 3; -#endif -}; - -void -phydm_reset_rssi_for_dm( - struct PHY_DM_STRUCT *p_dm_odm, - u8 station_id -); - -void -odm_init_rssi_for_dm( - struct PHY_DM_STRUCT *p_dm_odm -); - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -phydm_normal_driver_rx_sniffer( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_desc, - PRT_RFD_STATUS p_rt_rfd_status, - u8 *p_drv_info, - u8 phy_status -); -#endif - -void -odm_phy_status_query( - struct PHY_DM_STRUCT *p_dm_odm, - struct _odm_phy_status_info_ *p_phy_info, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo -); - -void -odm_mac_status_query( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *p_mac_status, - u8 mac_id, - boolean is_packet_match_bssid, - boolean is_packet_to_self, - boolean is_packet_beacon -); - -enum hal_status -odm_config_rf_with_tx_pwr_track_header_file( - struct PHY_DM_STRUCT *p_dm_odm -); +/*@************************************************************ + * structure and define + ************************************************************/ enum hal_status -odm_config_rf_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_config_type config_type, - enum odm_rf_radio_path_e e_rf_path -); +odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm); enum hal_status -odm_config_bb_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_bb_config_type config_type -); +odm_config_rf_with_header_file(struct dm_struct *dm, + enum odm_rf_config_type config_type, + u8 e_rf_path); enum hal_status -odm_config_mac_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm -); +odm_config_bb_with_header_file(struct dm_struct *dm, + enum odm_bb_config_type config_type); enum hal_status -odm_config_fw_with_header_file( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_fw_config_type config_type, - u8 *p_firmware, - u32 *p_size -); - -u32 -odm_get_hw_img_version( - struct PHY_DM_STRUCT *p_dm_odm -); +odm_config_mac_with_header_file(struct dm_struct *dm); -s32 -odm_signal_scale_mapping( - struct PHY_DM_STRUCT *p_dm_odm, - s32 curr_sig -); - -#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) -/*For 8822B only!! need to move to FW finally */ -/*==============================================*/ -void -phydm_rx_phy_status_new_type( - struct PHY_DM_STRUCT *p_phydm, - u8 *p_phy_status, - struct _odm_per_pkt_info_ *p_pktinfo, - struct _odm_phy_status_info_ *p_phy_info -); - -boolean -phydm_query_is_mu_api( - struct PHY_DM_STRUCT *p_phydm, - u8 ppdu_idx, - u8 *p_data_rate, - u8 *p_gid -); - -struct _phy_status_rpt_jaguar2_type0 { - /* DW0 */ - u8 page_num; - u8 pwdb; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 gain: 6; - u8 rsvd_0: 1; - u8 trsw: 1; -#else - u8 trsw: 1; - u8 rsvd_0: 1; - u8 gain: 6; -#endif - u8 rsvd_1; - - /* DW1 */ - u8 rsvd_2; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 rxsc: 4; - u8 agc_table: 4; -#else - u8 agc_table: 4; - u8 rxsc: 4; -#endif - u8 channel; - u8 band; - - /* DW2 */ - u16 length; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 antidx_a: 3; - u8 antidx_b: 3; - u8 rsvd_3: 2; - u8 antidx_c: 3; - u8 antidx_d: 3; - u8 rsvd_4:2; -#else - u8 rsvd_3: 2; - u8 antidx_b: 3; - u8 antidx_a: 3; - u8 rsvd_4:2; - u8 antidx_d: 3; - u8 antidx_c: 3; -#endif - - /* DW3 */ - u8 signal_quality; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 vga:5; - u8 lna_l:3; - u8 bb_power:6; - u8 rsvd_9:1; - u8 lna_h:1; -#else - u8 lna_l:3; - u8 vga:5; - u8 lna_h:1; - u8 rsvd_9:1; - u8 bb_power:6; -#endif - u8 rsvd_5; - - /* DW4 */ - u32 rsvd_6; - - /* DW5 */ - u32 rsvd_7; - - /* DW6 */ - u32 rsvd_8; -}; - -struct _phy_status_rpt_jaguar2_type1 { - /* DW0 and DW1 */ - u8 page_num; - u8 pwdb[4]; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 l_rxsc: 4; - u8 ht_rxsc: 4; -#else - u8 ht_rxsc: 4; - u8 l_rxsc: 4; -#endif - u8 channel; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 band: 2; - u8 rsvd_0: 1; - u8 hw_antsw_occu: 1; - u8 gnt_bt: 1; - u8 ldpc: 1; - u8 stbc: 1; - u8 beamformed: 1; -#else - u8 beamformed: 1; - u8 stbc: 1; - u8 ldpc: 1; - u8 gnt_bt: 1; - u8 hw_antsw_occu: 1; - u8 rsvd_0: 1; - u8 band: 2; -#endif - - /* DW2 */ - u16 lsig_length; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 antidx_a: 3; - u8 antidx_b: 3; - u8 rsvd_1: 2; - u8 antidx_c: 3; - u8 antidx_d: 3; - u8 rsvd_2: 2; -#else - u8 rsvd_1: 2; - u8 antidx_b: 3; - u8 antidx_a: 3; - u8 rsvd_2: 2; - u8 antidx_d: 3; - u8 antidx_c: 3; -#endif - - /* DW3 */ - u8 paid; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 paid_msb: 1; - u8 gid: 6; - u8 rsvd_3: 1; -#else - u8 rsvd_3: 1; - u8 gid: 6; - u8 paid_msb: 1; -#endif - u8 intf_pos; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 intf_pos_msb: 1; - u8 rsvd_4: 2; - u8 nb_intf_flag: 1; - u8 rf_mode: 2; - u8 rsvd_5: 2; -#else - u8 rsvd_5: 2; - u8 rf_mode: 2; - u8 nb_intf_flag: 1; - u8 rsvd_4: 2; - u8 intf_pos_msb: 1; -#endif - - /* DW4 */ - s8 rxevm[4]; /* s(8,1) */ - - /* DW5 */ - s8 cfo_tail[4]; /* s(8,7) */ - - /* DW6 */ - s8 rxsnr[4]; /* s(8,1) */ -}; - -struct _phy_status_rpt_jaguar2_type2 { - /* DW0 ane DW1 */ - u8 page_num; - u8 pwdb[4]; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 l_rxsc: 4; - u8 ht_rxsc: 4; -#else - u8 ht_rxsc: 4; - u8 l_rxsc: 4; -#endif - u8 channel; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 band: 2; - u8 rsvd_0: 1; - u8 hw_antsw_occu: 1; - u8 gnt_bt: 1; - u8 ldpc: 1; - u8 stbc: 1; - u8 beamformed: 1; -#else - u8 beamformed: 1; - u8 stbc: 1; - u8 ldpc: 1; - u8 gnt_bt: 1; - u8 hw_antsw_occu: 1; - u8 rsvd_0: 1; - u8 band: 2; -#endif - - /* DW2 */ -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 shift_l_map: 6; - u8 rsvd_1: 2; -#else - u8 rsvd_1: 2; - u8 shift_l_map: 6; -#endif - u8 cnt_pw2cca; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 agc_table_a: 4; - u8 agc_table_b: 4; - u8 agc_table_c: 4; - u8 agc_table_d: 4; -#else - u8 agc_table_b: 4; - u8 agc_table_a: 4; - u8 agc_table_d: 4; - u8 agc_table_c: 4; -#endif - - /* DW3 ~ DW6*/ - u8 cnt_cca2agc_rdy; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 gain_a: 6; - u8 rsvd_2: 1; - u8 trsw_a: 1; - u8 gain_b: 6; - u8 rsvd_3: 1; - u8 trsw_b: 1; - u8 gain_c: 6; - u8 rsvd_4: 1; - u8 trsw_c: 1; - u8 gain_d: 6; - u8 rsvd_5: 1; - u8 trsw_d: 1; - u8 aagc_step_a: 2; - u8 aagc_step_b: 2; - u8 aagc_step_c: 2; - u8 aagc_step_d: 2; -#else - u8 trsw_a: 1; - u8 rsvd_2: 1; - u8 gain_a: 6; - u8 trsw_b: 1; - u8 rsvd_3: 1; - u8 gain_b: 6; - u8 trsw_c: 1; - u8 rsvd_4: 1; - u8 gain_c: 6; - u8 trsw_d: 1; - u8 rsvd_5: 1; - u8 gain_d: 6; - u8 aagc_step_d: 2; - u8 aagc_step_c: 2; - u8 aagc_step_b: 2; - u8 aagc_step_a: 2; -#endif - u8 ht_aagc_gain[4]; - u8 dagc_gain[4]; -#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) - u8 counter: 6; - u8 rsvd_6: 2; - u8 syn_count: 5; - u8 rsvd_7:3; -#else - u8 rsvd_6: 2; - u8 counter: 6; - u8 rsvd_7:3; - u8 syn_count: 5; -#endif -}; -/*==============================================*/ -#endif /*#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)*/ +u32 odm_get_hw_img_version(struct dm_struct *dm); -u32 -query_phydm_trx_capability( - struct PHY_DM_STRUCT *p_dm_odm -); +u32 query_phydm_trx_capability(struct dm_struct *dm); -u32 -query_phydm_stbc_capability( - struct PHY_DM_STRUCT *p_dm_odm -); +u32 query_phydm_stbc_capability(struct dm_struct *dm); -u32 -query_phydm_ldpc_capability( - struct PHY_DM_STRUCT *p_dm_odm -); +u32 query_phydm_ldpc_capability(struct dm_struct *dm); -u32 -query_phydm_txbf_parameters( - struct PHY_DM_STRUCT *p_dm_odm -); +u32 query_phydm_txbf_parameters(struct dm_struct *dm); -u32 -query_phydm_txbf_capability( - struct PHY_DM_STRUCT *p_dm_odm -); +u32 query_phydm_txbf_capability(struct dm_struct *dm); -#endif /*#ifndef __HALHWOUTSRC_H__*/ +#endif /*@#ifndef __HALHWOUTSRC_H__*/ diff --git a/hal/phydm/phydm_interface.c b/hal/phydm/phydm_interface.c index 277e109..265758d 100644 --- a/hal/phydm/phydm_interface.c +++ b/hal/phydm/phydm_interface.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,417 +8,522 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -/* ************************************************************ +/*@************************************************************ * include files - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" -/* +/*@ * ODM IO Relative API. - * */ + */ -u8 -odm_read_1byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr -) +u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; - return RTL_R8(reg_addr); + struct rtl8192cd_priv *priv = dm->priv; + return RTL_R8(reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_read_byte(rtlpriv, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_read8(rtwdev, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; return rtw_read8(adapter, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - return PlatformEFIORead1Byte(adapter, reg_addr); -#endif + void *adapter = dm->adapter; + return PlatformEFIORead1Byte(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + return rtw_read8(adapter, reg_addr); +#endif } - -u16 -odm_read_2byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr -) +u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; - return RTL_R16(reg_addr); + struct rtl8192cd_priv *priv = dm->priv; + return RTL_R16(reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_read_word(rtlpriv, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_read16(rtwdev, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; return rtw_read16(adapter, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - return PlatformEFIORead2Byte(adapter, reg_addr); -#endif + void *adapter = dm->adapter; + return PlatformEFIORead2Byte(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + return rtw_read16(adapter, reg_addr); +#endif } - -u32 -odm_read_4byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr -) +u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; - return RTL_R32(reg_addr); + struct rtl8192cd_priv *priv = dm->priv; + return RTL_R32(reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_read_dword(rtlpriv, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_read32(rtwdev, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; return rtw_read32(adapter, reg_addr); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - return PlatformEFIORead4Byte(adapter, reg_addr); -#endif + void *adapter = dm->adapter; + return PlatformEFIORead4Byte(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + return rtw_read32(adapter, reg_addr); +#endif } - -void -odm_write_1byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u8 data -) +void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; RTL_W8(reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_write_byte(rtlpriv, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_write8(rtwdev, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; rtw_write8(adapter, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PlatformEFIOWrite1Byte(adapter, reg_addr, data); -#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + rtw_write8(adapter, reg_addr, data); +#endif } - -void -odm_write_2byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u16 data -) +void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; RTL_W16(reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_write_word(rtlpriv, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_write16(rtwdev, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; rtw_write16(adapter, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PlatformEFIOWrite2Byte(adapter, reg_addr, data); -#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + rtw_write16(adapter, reg_addr, data); +#endif } - -void -odm_write_4byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u32 data -) +void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - struct rtl8192cd_priv *priv = p_dm_odm->priv; + struct rtl8192cd_priv *priv = dm->priv; RTL_W32(reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_write_dword(rtlpriv, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_write32(rtwdev, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; rtw_write32(adapter, reg_addr, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PlatformEFIOWrite4Byte(adapter, reg_addr, data); -#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + rtw_write32(adapter, reg_addr, data); +#endif } - -void -odm_set_mac_reg( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u32 bit_mask, - u32 data -) +void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - phy_set_bb_reg(p_dm_odm->priv, reg_addr, bit_mask, data); + phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PHY_SetBBReg(adapter, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data); #else - phy_set_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask, data); + phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data); #endif } - -u32 -odm_get_mac_reg( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u32 bit_mask -) +u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return phy_query_bb_reg(p_dm_odm->priv, reg_addr, bit_mask); + return phy_query_bb_reg(dm->priv, reg_addr, bit_mask); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - return PHY_QueryMacReg(p_dm_odm->adapter, reg_addr, bit_mask); + return PHY_QueryMacReg(dm->adapter, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask); #else - return phy_query_mac_reg(p_dm_odm->adapter, reg_addr, bit_mask); + return phy_query_mac_reg(dm->adapter, reg_addr, bit_mask); #endif } - -void -odm_set_bb_reg( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u32 bit_mask, - u32 data -) +void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - phy_set_bb_reg(p_dm_odm->priv, reg_addr, bit_mask, data); + phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PHY_SetBBReg(adapter, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data); #else - phy_set_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask, data); + phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data); #endif } - -u32 -odm_get_bb_reg( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u32 bit_mask -) +u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return phy_query_bb_reg(p_dm_odm->priv, reg_addr, bit_mask); + return phy_query_bb_reg(dm->priv, reg_addr, bit_mask); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; return PHY_QueryBBReg(adapter, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask); #else - return phy_query_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask); + return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask); #endif } - -void -odm_set_rf_reg( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e e_rf_path, - u32 reg_addr, - u32 bit_mask, - u32 data -) +void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr, + u32 bit_mask, u32 data) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - phy_set_rf_reg(p_dm_odm->priv, e_rf_path, reg_addr, bit_mask, data); + phy_set_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PHY_SetRFReg(adapter, e_rf_path, reg_addr, bit_mask, data); ODM_delay_us(2); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_set_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_write_rf(rtwdev, e_rf_path, reg_addr, bit_mask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - phy_set_rf_reg(p_dm_odm->adapter, e_rf_path, reg_addr, bit_mask, data); + phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data); #endif } -u32 -odm_get_rf_reg( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e e_rf_path, - u32 reg_addr, - u32 bit_mask -) +u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr, + u32 bit_mask) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return phy_query_rf_reg(p_dm_odm->priv, e_rf_path, reg_addr, bit_mask, 1); + return phy_query_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, 1); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; return PHY_QueryRFReg(adapter, e_rf_path, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_get_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_read_rf(rtwdev, e_rf_path, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask); #else - return phy_query_rf_reg(p_dm_odm->adapter, e_rf_path, reg_addr, bit_mask); + return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask); #endif } +enum hal_status +phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type, + u32 offset, u32 data, u32 mask, enum rf_path e_rf_path, + u32 delay_time) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + return HAL_MAC_Config_PHY_WriteNByte(dm, + config_type, + offset, + data, + mask, + e_rf_path, + delay_time); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n"); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + return -ENOTSUPP; +#else + return rtw_phydm_cfg_phy_para(dm, + config_type, + offset, + data, + mask, + e_rf_path, + delay_time); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n"); +#endif +} - - -/* +/*@ * ODM Memory relative API. - * */ -void -odm_allocate_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void **p_ptr, - u32 length -) + */ +void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - *p_ptr = kmalloc(length, GFP_ATOMIC); + *ptr = kmalloc(length, GFP_ATOMIC); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + *ptr = kmalloc(length, GFP_ATOMIC); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + *ptr = kmalloc(length, GFP_ATOMIC); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - *p_ptr = rtw_zvmalloc(length); + *ptr = rtw_zvmalloc(length); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PlatformAllocateMemory(adapter, p_ptr, length); + void *adapter = dm->adapter; + PlatformAllocateMemory(adapter, ptr, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + *ptr = rtw_zvmalloc(length); #endif } -/* length could be ignored, used to detect memory leakage. */ -void -odm_free_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_ptr, - u32 length -) +/* @length could be ignored, used to detect memory leakage. */ +void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - kfree(p_ptr); + kfree(ptr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + kfree(ptr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + kfree(ptr); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_vmfree(p_ptr, length); + rtw_vmfree(ptr, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - /* struct _ADAPTER* adapter = p_dm_odm->adapter; */ - PlatformFreeMemory(p_ptr, length); + /* struct void* adapter = dm->adapter; */ + PlatformFreeMemory(ptr, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_vmfree(ptr, length); #endif } -void -odm_move_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_dest, - void *p_src, - u32 length -) +void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - memcpy(p_dest, p_src, length); + memcpy(dest, src, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + memcpy(dest, src, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + memcpy(dest, src, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - _rtw_memcpy(p_dest, p_src, length); + _rtw_memcpy(dest, src, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformMoveMemory(p_dest, p_src, length); + PlatformMoveMemory(dest, src, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_memcpy(dest, src, length); #endif } -void odm_memory_set( - struct PHY_DM_STRUCT *p_dm_odm, - void *pbuf, - s8 value, - u32 length -) +void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) memset(pbuf, value, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + memset(pbuf, value, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + memset(pbuf, value, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) _rtw_memset(pbuf, value, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) PlatformFillMemory(pbuf, length, value); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_memset(pbuf, value, length); #endif } -s32 odm_compare_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_buf1, - void *p_buf2, - u32 length -) + +s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2, u32 length) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return memcmp(p_buf1, p_buf2, length); + return memcmp(buf1, buf2, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + return memcmp(buf1, buf2, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + return memcmp(buf1, buf2, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - return _rtw_memcmp(p_buf1, p_buf2, length); + return _rtw_memcmp(buf1, buf2, length); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - return PlatformCompareMemory(p_buf1, p_buf2, length); + return PlatformCompareMemory(buf1, buf2, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return rtw_memcmp(buf1, buf2, length); #endif } - - -/* +/*@ * ODM MISC relative API. - * */ -void -odm_acquire_spin_lock( - struct PHY_DM_STRUCT *p_dm_odm, - enum rt_spinlock_type type -) + */ +void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_odm_acquirespinlock(rtlpriv, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + spin_lock(&rtwdev->hal.dm_lock); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; rtw_odm_acquirespinlock(adapter, type); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PlatformAcquireSpinLock(adapter, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + rtw_odm_acquirespinlock(adapter, type); #endif } -void -odm_release_spin_lock( - struct PHY_DM_STRUCT *p_dm_odm, - enum rt_spinlock_type type -) + +void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_odm_releasespinlock(rtlpriv, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + spin_unlock(&rtwdev->hal.dm_lock); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; rtw_odm_releasespinlock(adapter, type); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; PlatformReleaseSpinLock(adapter, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + rtw_odm_releasespinlock(adapter, type); #endif } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -/* +/*@ * Work item relative API. FOr MP driver only~! * */ -void -odm_initialize_work_item( - struct PHY_DM_STRUCT *p_dm_odm, - PRT_WORK_ITEM p_rt_work_item, - RT_WORKITEM_CALL_BACK rt_work_item_callback, - void *p_context, - const char *sz_id -) +void odm_initialize_work_item( + struct dm_struct *dm, + PRT_WORK_ITEM work_item, + RT_WORKITEM_CALL_BACK callback, + void *context, + const char *id) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PlatformInitializeWorkItem(adapter, p_rt_work_item, rt_work_item_callback, p_context, sz_id); + void *adapter = dm->adapter; + PlatformInitializeWorkItem(adapter, work_item, callback, context, id); #endif } - -void -odm_start_work_item( - PRT_WORK_ITEM p_rt_work_item -) +void odm_start_work_item( + PRT_WORK_ITEM p_rt_work_item) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) @@ -429,11 +534,8 @@ odm_start_work_item( #endif } - -void -odm_stop_work_item( - PRT_WORK_ITEM p_rt_work_item -) +void odm_stop_work_item( + PRT_WORK_ITEM p_rt_work_item) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) @@ -444,11 +546,8 @@ odm_stop_work_item( #endif } - -void -odm_free_work_item( - PRT_WORK_ITEM p_rt_work_item -) +void odm_free_work_item( + PRT_WORK_ITEM p_rt_work_item) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) @@ -459,11 +558,8 @@ odm_free_work_item( #endif } - -void -odm_schedule_work_item( - PRT_WORK_ITEM p_rt_work_item -) +void odm_schedule_work_item( + PRT_WORK_ITEM p_rt_work_item) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) @@ -474,11 +570,9 @@ odm_schedule_work_item( #endif } - boolean odm_is_work_item_scheduled( - PRT_WORK_ITEM p_rt_work_item -) + PRT_WORK_ITEM p_rt_work_item) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) @@ -490,138 +584,144 @@ odm_is_work_item_scheduled( } #endif - -/* +/*@ * ODM Timer relative API. - * */ -void -odm_stall_execution( - u32 us_delay -) -{ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_udelay_os(us_delay); -#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PlatformStallExecution(us_delay); -#endif -} + */ -void -ODM_delay_ms(u32 ms) +void ODM_delay_ms(u32 ms) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) delay_ms(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + mdelay(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + mdelay(ms); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) rtw_mdelay_os(ms); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) delay_ms(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_mdelay_os(ms); #endif } -void -ODM_delay_us(u32 us) +void ODM_delay_us(u32 us) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) delay_us(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + udelay(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + udelay(us); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) rtw_udelay_os(us); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) PlatformStallExecution(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_udelay_os(us); #endif } -void -ODM_sleep_ms(u32 ms) +void ODM_sleep_ms(u32 ms) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - + delay_ms(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + msleep(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + msleep(ms); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) rtw_msleep_os(ms); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + delay_ms(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_msleep_os(ms); #endif } -void -ODM_sleep_us(u32 us) +void ODM_sleep_us(u32 us) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - + delay_us(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + usleep_range(us, us + 1); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + usleep_range(us, us + 1); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) rtw_usleep_os(us); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStallExecution(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_usleep_os(us); #endif } -void -odm_set_timer( - struct PHY_DM_STRUCT *p_dm_odm, - struct timer_list *p_timer, - u32 ms_delay -) +void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer, + u32 ms_delay) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - mod_timer(p_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay)); + mod_timer(timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay)); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + mod_timer(timer, jiffies + msecs_to_jiffies(ms_delay)); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + mod_timer(&timer->timer, jiffies + msecs_to_jiffies(ms_delay)); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - _set_timer(p_timer, ms_delay); /* ms */ + _set_timer(timer, ms_delay); /* @ms */ #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PlatformSetTimer(adapter, p_timer, ms_delay); + void *adapter = dm->adapter; + PlatformSetTimer(adapter, timer, ms_delay); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_set_timer(timer, ms_delay); /* @ms */ #endif - } -#if 0 -/* Disabled because all users would need to be converted to the Linux 4.15 -* timer API change. However it has no users so just get rid of this helper. - */ -void -odm_initialize_timer( - struct PHY_DM_STRUCT *p_dm_odm, - struct timer_list *p_timer, - void *call_back_func, - void *p_context, - const char *sz_id -) +void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer, + void *call_back_func, void *context, + const char *sz_id) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - init_timer(p_timer); - p_timer->function = call_back_func; - p_timer->data = (unsigned long)p_dm_odm; - /*mod_timer(p_timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */ + init_timer(timer); + timer->function = call_back_func; + timer->data = (unsigned long)dm; +#if 0 + /*@mod_timer(timer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); */ +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + timer_setup(timer, call_back_func, 0); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - struct _ADAPTER *adapter = p_dm_odm->adapter; - _init_timer(p_timer, adapter->pnetdev, call_back_func, p_dm_odm); + struct _ADAPTER *adapter = dm->adapter; + + _init_timer(timer, adapter->pnetdev, call_back_func, dm); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PlatformInitializeTimer(adapter, p_timer, call_back_func, p_context, sz_id); + void *adapter = dm->adapter; + + PlatformInitializeTimer(adapter, timer, (RT_TIMER_CALL_BACK)call_back_func, context, sz_id); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + struct _ADAPTER *adapter = dm->adapter; + + rtw_init_timer(timer, adapter->pnetdev, (TIMER_FUN)call_back_func, dm, NULL); #endif } -#endif -void -odm_cancel_timer( - struct PHY_DM_STRUCT *p_dm_odm, - struct timer_list *p_timer -) +void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer) { #if (DM_ODM_SUPPORT_TYPE & ODM_AP) - del_timer(p_timer); + del_timer(timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + del_timer(timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + del_timer(&timer->timer); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - _cancel_timer_ex(p_timer); + _cancel_timer_ex(timer); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PlatformCancelTimer(adapter, p_timer); + void *adapter = dm->adapter; + PlatformCancelTimer(adapter, timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_cancel_timer(timer); #endif } - -void -odm_release_timer( - struct PHY_DM_STRUCT *p_dm_odm, - struct timer_list *p_timer -) +void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) @@ -629,60 +729,64 @@ odm_release_timer( #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; - /* <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. - * Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. */ - if (p_timer == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>odm_release_timer(), The timer is NULL! Please check it!\n")); + /* @<20120301, Kordan> If the initilization fails, + * InitializeAdapterXxx will return regardless of InitHalDm. + * Hence, uninitialized timers cause BSOD when the driver + * releases resources since the init fail. + */ + if (timer == 0) { + PHYDM_DBG(dm, ODM_COMP_INIT, + "[%s] Timer is NULL! Please check!\n", __func__); return; } - PlatformReleaseTimer(adapter, p_timer); + PlatformReleaseTimer(adapter, timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_del_timer(timer); #endif } - -u8 -phydm_trans_h2c_id( - struct PHY_DM_STRUCT *p_dm_odm, - u8 phydm_h2c_id -) +u8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id) { u8 platform_h2c_id = phydm_h2c_id; switch (phydm_h2c_id) { - /* 1 [0] */ + /* @1 [0] */ case ODM_H2C_RSSI_REPORT: #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) + #if (RTL8188E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) platform_h2c_id = H2C_88E_RSSI_REPORT; - else if (p_dm_odm->support_ic_type == ODM_RTL8814A) - platform_h2c_id = H2C_8814A_RSSI_REPORT; else + #endif platform_h2c_id = H2C_RSSI_REPORT; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) platform_h2c_id = H2C_RSSI_SETTING; #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) -#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) +#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/ + if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES) platform_h2c_id = H2C_88XX_RSSI_REPORT; else #endif #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - platform_h2c_id = H2C_8812_RSSI_REPORT; - else + if (dm->support_ic_type == ODM_RTL8812) + platform_h2c_id = H2C_8812_RSSI_REPORT; + else #endif - {} + { + } #endif break; - /* 1 [3] */ + /* @1 [3] */ case ODM_H2C_WIFI_CALIBRATION: #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) platform_h2c_id = H2C_WIFI_CALIBRATION; @@ -696,8 +800,7 @@ phydm_trans_h2c_id( #endif break; - - /* 1 [4] */ + /* @1 [4] */ case ODM_H2C_IQ_CALIBRATION: #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) platform_h2c_id = H2C_IQ_CALIBRATION; @@ -710,14 +813,13 @@ phydm_trans_h2c_id( #endif break; - /* 1 [5] */ + /* @1 [5] */ case ODM_H2C_RA_PARA_ADJUST: #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) - platform_h2c_id = H2C_8814A_RA_PARA_ADJUST; - else - platform_h2c_id = H2C_RA_PARA_ADJUST; + platform_h2c_id = H2C_RA_PARA_ADJUST; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) platform_h2c_id = H2C_8812_RA_PARA_ADJUST; @@ -730,36 +832,38 @@ phydm_trans_h2c_id( #endif #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) -#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) +#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/ + if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES) platform_h2c_id = H2C_88XX_RA_PARA_ADJUST; else #endif #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - platform_h2c_id = H2C_8812_RA_PARA_ADJUST; - else + if (dm->support_ic_type == ODM_RTL8812) + platform_h2c_id = H2C_8812_RA_PARA_ADJUST; + else #endif - {} + { + } #endif break; - - /* 1 [6] */ + /* @1 [6] */ case PHYDM_H2C_DYNAMIC_TX_PATH: #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) + #if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8814A) platform_h2c_id = H2C_8814A_DYNAMIC_TX_PATH; + #endif #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) + if (dm->support_ic_type == ODM_RTL8814A) platform_h2c_id = H2C_DYNAMIC_TX_PATH; #endif #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8814A) + if (dm->support_ic_type == ODM_RTL8814A) platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH; #endif @@ -767,31 +871,30 @@ phydm_trans_h2c_id( break; - /* [7]*/ + /* @[7]*/ case PHYDM_H2C_FW_TRACE_EN: #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) - platform_h2c_id = H2C_8814A_FW_TRACE_EN; - else - platform_h2c_id = H2C_FW_TRACE_EN; + + platform_h2c_id = H2C_FW_TRACE_EN; #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) platform_h2c_id = 0x49; #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) -#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) - platform_h2c_id = H2C_88XX_FW_TRACE_EN; +#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/ + if (dm->support_ic_type == ODM_RTL8881A || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type & PHYDM_IC_3081_SERIES) + platform_h2c_id = H2C_88XX_FW_TRACE_EN; else #endif #if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - platform_h2c_id = H2C_8812_FW_TRACE_EN; - else + if (dm->support_ic_type == ODM_RTL8812) + platform_h2c_id = H2C_8812_FW_TRACE_EN; + else #endif - {} + { + } #endif @@ -799,13 +902,13 @@ phydm_trans_h2c_id( case PHYDM_H2C_TXBF: #if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) - platform_h2c_id = 0x41; /*H2C_TxBF*/ + platform_h2c_id = 0x41; /*@H2C_TxBF*/ #endif break; case PHYDM_H2C_MU: #if (RTL8822B_SUPPORT == 1) - platform_h2c_id = 0x4a; /*H2C_MU*/ + platform_h2c_id = 0x4a; /*@H2C_MU*/ #endif break; @@ -815,114 +918,133 @@ phydm_trans_h2c_id( } return platform_h2c_id; - } -/*ODM FW relative API.*/ +/*@ODM FW relative API.*/ -void -odm_fill_h2c_cmd( - struct PHY_DM_STRUCT *p_dm_odm, - u8 phydm_h2c_id, - u32 cmd_len, - u8 *p_cmd_buffer -) +void odm_fill_h2c_cmd(struct dm_struct *dm, u8 phydm_h2c_id, u32 cmd_len, + u8 *cmd_buf) { - struct _ADAPTER *adapter = p_dm_odm->adapter; - u8 platform_h2c_id; - - platform_h2c_id = phydm_trans_h2c_id(p_dm_odm, phydm_h2c_id); +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + u8 cmd_id, cmd_class; + u8 h2c_pkt[8]; +#else + void *adapter = dm->adapter; +#endif + u8 h2c_id = phydm_trans_h2c_id(dm, phydm_h2c_id); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] platform_h2c_id = ((0x%x))\n", platform_h2c_id)); + PHYDM_DBG(dm, DBG_RA, "[H2C] h2c_id=((0x%x))\n", h2c_id); #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - if (!p_dm_odm->ra_support88e) - FillH2CCmd88E(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); - } else if (p_dm_odm->support_ic_type == ODM_RTL8814A) - FillH2CCmd8814A(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); - else if (p_dm_odm->support_ic_type == ODM_RTL8822B) -#if (RTL8822B_SUPPORT == 1) - FillH2CCmd8822B(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); -#endif + if (dm->support_ic_type == ODM_RTL8188E) { + if (!dm->ra_support88e) + FillH2CCmd88E(adapter, h2c_id, cmd_len, cmd_buf); + } else if (dm->support_ic_type == ODM_RTL8814A) + FillH2CCmd8814A(adapter, h2c_id, cmd_len, cmd_buf); + else if (dm->support_ic_type == ODM_RTL8822B) + FillH2CCmd8822B(adapter, h2c_id, cmd_len, cmd_buf); else - FillH2CCmd(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); + FillH2CCmd(adapter, h2c_id, cmd_len, cmd_buf); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - rtw_hal_fill_h2c_cmd(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); + + #ifdef DM_ODM_CE_MAC80211 + rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, h2c_id, cmd_len, cmd_buf); + #elif defined(DM_ODM_CE_MAC80211_V2) + cmd_id = phydm_h2c_id & 0x1f; + cmd_class = (phydm_h2c_id >> RTW_H2C_CLASS_OFFSET) & 0x7; + memcpy(h2c_pkt + 1, cmd_buf, 7); + h2c_pkt[0] = phydm_h2c_id; + rtw_fw_send_h2c_packet(rtwdev, h2c_pkt, cmd_id, cmd_class); + /* TODO: implement fill h2c command for rtwlan */ + #else + rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf); + #endif #elif (DM_ODM_SUPPORT_TYPE & ODM_AP) -#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1)) - if (p_dm_odm->support_ic_type == ODM_RTL8881A || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) - GET_HAL_INTERFACE(p_dm_odm->priv)->fill_h2c_cmd_handler(p_dm_odm->priv, platform_h2c_id, cmd_len, p_cmd_buffer); - else -#endif -#if (RTL8812A_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - fill_h2c_cmd8812(p_dm_odm->priv, platform_h2c_id, cmd_len, p_cmd_buffer); - else -#endif - {} + + #if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8812) { + fill_h2c_cmd8812(dm->priv, h2c_id, cmd_len, cmd_buf); + } else + #endif + { + GET_HAL_INTERFACE(dm->priv)->fill_h2c_cmd_handler(dm->priv, h2c_id, cmd_len, cmd_buf); + } + +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf); + #endif } -u8 -phydm_c2H_content_parsing( - void *p_dm_void, - u8 c2h_cmd_id, - u8 c2h_cmd_len, - u8 *tmp_buf -) +u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len, + u8 *tmp_buf) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; #endif - u8 extend_c2h_sub_id = 0; - u8 find_c2h_cmd = true; + u8 extend_c2h_sub_id = 0; + u8 find_c2h_cmd = true; + + if (c2h_cmd_len > 12 || c2h_cmd_len == 0) { + pr_debug("[Warning] Error C2H ID=%d, len=%d\n", + c2h_cmd_id, c2h_cmd_len); + + find_c2h_cmd = false; + return find_c2h_cmd; + } switch (c2h_cmd_id) { case PHYDM_C2H_DBG: - phydm_fw_trace_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + phydm_fw_trace_handler(dm, tmp_buf, c2h_cmd_len); break; case PHYDM_C2H_RA_RPT: - phydm_c2h_ra_report_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + phydm_c2h_ra_report_handler(dm, tmp_buf, c2h_cmd_len); break; case PHYDM_C2H_RA_PARA_RPT: - odm_c2h_ra_para_report_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + odm_c2h_ra_para_report_handler(dm, tmp_buf, c2h_cmd_len); break; - +#ifdef CONFIG_PATH_DIVERSITY case PHYDM_C2H_DYNAMIC_TX_PATH_RPT: - if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) - phydm_c2h_dtp_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + if (dm->support_ic_type & (ODM_RTL8814A)) + phydm_c2h_dtp_handler(dm, tmp_buf, c2h_cmd_len); break; +#endif case PHYDM_C2H_IQK_FINISH: #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) { - + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) { RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n")); - odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false; - odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); - p_dm_odm->rf_calibrate_info.iqk_progressing_time = 0; - p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.iqk_progressing_time = 0; + dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time); } #endif break; + case PHYDM_C2H_CLM_MONITOR: + phydm_clm_c2h_report_handler(dm, tmp_buf, c2h_cmd_len); + break; + case PHYDM_C2H_DBG_CODE: - phydm_fw_trace_handler_code(p_dm_odm, tmp_buf, c2h_cmd_len); + phydm_fw_trace_handler_code(dm, tmp_buf, c2h_cmd_len); break; case PHYDM_C2H_EXTEND: extend_c2h_sub_id = tmp_buf[0]; if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT) - phydm_fw_trace_handler_8051(p_dm_odm, tmp_buf, c2h_cmd_len); + phydm_fw_trace_handler_8051(dm, tmp_buf, c2h_cmd_len); break; @@ -932,74 +1054,71 @@ phydm_c2H_content_parsing( } return find_c2h_cmd; - } -u64 -odm_get_current_time( - struct PHY_DM_STRUCT *p_dm_odm -) +u64 odm_get_current_time(struct dm_struct *dm) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return 0; -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) return (u64)rtw_get_current_time(); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + return jiffies; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + return jiffies; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return rtw_get_current_time(); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - return PlatformGetCurrentTime(); + return PlatformGetCurrentTime(); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return rtw_get_current_time(); #endif } -u64 -odm_get_progressing_time( - struct PHY_DM_STRUCT *p_dm_odm, - u64 start_time -) +u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time) { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - return 0; -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) return rtw_get_passing_time_ms((u32)start_time); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + return jiffies_to_msecs(jiffies - start_time); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + return jiffies_to_msecs(jiffies - start_time); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return rtw_get_passing_time_ms((systime)start_time); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) return ((PlatformGetCurrentTime() - start_time) >> 10); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return rtw_get_passing_time_ms(start_time); #endif } -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \ + (!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2)) -void -phydm_set_hw_reg_handler_interface ( - struct PHY_DM_STRUCT *p_dm_odm, - u8 RegName, - u8 *val - ) +void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 RegName, + u8 *val) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - struct _ADAPTER *adapter = p_dm_odm->adapter; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct _ADAPTER *adapter = dm->adapter; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - adapter->HalFunc.SetHwRegHandler(adapter, RegName, val); + ((PADAPTER)adapter)->HalFunc.SetHwRegHandler(adapter, RegName, val); #else adapter->hal_func.set_hw_reg_handler(adapter, RegName, val); #endif #endif - } -void -phydm_get_hal_def_var_handler_interface ( - struct PHY_DM_STRUCT *p_dm_odm, - enum _HAL_DEF_VARIABLE e_variable, - void *p_value - ) +void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm, + enum _HAL_DEF_VARIABLE e_variable, + void *value) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - struct _ADAPTER *adapter = p_dm_odm->adapter; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct _ADAPTER *adapter = dm->adapter; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - adapter->HalFunc.GetHalDefVarHandler(adapter, e_variable, p_value); + ((PADAPTER)adapter)->HalFunc.GetHalDefVarHandler(adapter, e_variable, value); #else - adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, p_value); + adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, value); #endif #endif @@ -1007,85 +1126,300 @@ phydm_get_hal_def_var_handler_interface ( #endif -void -odm_set_tx_power_index_by_rate_section ( - struct PHY_DM_STRUCT *p_dm_odm, - u8 RFPath, - u8 Channel, - u8 RateSection - ) +void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm, + enum rf_path path, u8 ch, + u8 section) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - PHY_SetTxPowerIndexByRateSection(adapter, RFPath, Channel, RateSection); + void *adapter = dm->adapter; + PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; + + phy_set_tx_power_index_by_rs(adapter, ch, path, section); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - phy_set_tx_power_index_by_rate_section(p_dm_odm->adapter, RFPath, Channel, RateSection); + phy_set_tx_power_index_by_rate_section(dm->adapter, path, ch, section); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section); #endif } -u8 -odm_get_tx_power_index ( - struct PHY_DM_STRUCT *p_dm_odm, - u8 RFPath, - u8 tx_rate, - u8 band_width, - u8 Channel - ) +u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 rate, + u8 bw, u8 ch) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - return PHY_GetTxPowerIndex(p_dm_odm->adapter, RFPath, tx_rate, band_width, Channel); + void *adapter = dm->adapter; + + return PHY_GetTxPowerIndex(dm->adapter, path, rate, (CHANNEL_WIDTH)bw, ch); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; + + return phy_get_tx_power_index(adapter, path, rate, bw, ch); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + void *adapter = dm->adapter; + + return phy_get_tx_power_index(adapter, path, rate, bw, ch); #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - return phy_get_tx_power_index(p_dm_odm->adapter, RFPath, tx_rate, band_width, Channel); + return phy_get_tx_power_index(dm->adapter, path, rate, bw, ch); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + return PHY_GetTxPowerIndex(dm->adapter, path, rate, bw, ch); #endif } +u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data, + boolean b_pseu_do_test) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + return (u8)EFUSE_OneByteRead(adapter, addr, data, b_pseu_do_test); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; + + return rtl_efuse_onebyte_read(adapter, addr, data, b_pseu_do_test); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + return -1; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return efuse_onebyte_read(dm->adapter, addr, data, b_pseu_do_test); +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +/*ReadEFuseByte(dm->priv, addr, data);*/ +/*return true;*/ +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + return (u8)efuse_OneByteRead(adapter, addr, data, b_pseu_do_test); +#endif +} -u8 -odm_efuse_one_byte_read( - struct PHY_DM_STRUCT *p_dm_odm, - u16 addr, - u8 *data, - boolean bPseudoTest - ) +void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset, + u32 *data) { #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + void *adapter = dm->adapter; - return (u8)EFUSE_OneByteRead(adapter, addr, data, bPseudoTest); + EFUSE_ShadowRead(adapter, type, offset, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; + + rtl_efuse_logical_map_read(adapter, type, offset, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - return efuse_OneByteRead(p_dm_odm->adapter, addr, data, bPseudoTest); + efuse_logical_map_read(dm->adapter, type, offset, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + EFUSE_ShadowRead(adapter, type, offset, data); #endif } enum hal_status -odm_iq_calibrate_by_fw( - struct PHY_DM_STRUCT *p_dm_odm, - u8 clear, - u8 segment - ) +odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment) { enum hal_status iqk_result = HAL_STATUS_FAILURE; #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _ADAPTER *adapter = dm->adapter; if (HAL_MAC_FWIQK_Trigger(&GET_HAL_MAC_INFO(adapter), clear, segment) == 0) iqk_result = HAL_STATUS_SUCCESS; - #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; + + iqk_result = rtl_phydm_fw_iqk(adapter, clear, segment); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#else + iqk_result = rtw_phydm_fw_iqk(dm, clear, segment); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + iqk_result = rtw_phydm_fw_iqk(dm, clear, segment); +#endif + return iqk_result; +} + +void odm_cmn_info_ptr_array_hook(struct dm_struct *dm, + enum odm_cmninfo cmn_info, u16 index, + void *value) +{ + switch (cmn_info) { + /*@Dynamic call by reference pointer. */ + case ODM_CMNINFO_STA_STATUS: + dm->odm_sta_info[index] = (struct sta_info *)value; + break; + /* To remove the compiler warning, + * must add an empty default statement to handle the other values. + */ + default: + /* @do nothing */ + break; + } +} + +void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 mac_id, + struct cmn_sta_info *pcmn_sta_info) +{ + dm->phydm_sta_info[mac_id] = pcmn_sta_info; + + if (is_sta_active(pcmn_sta_info)) + dm->phydm_macid_table[pcmn_sta_info->mac_id] = mac_id; +} + +void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx, + struct cmn_sta_info *pcmn_sta_info) +{ + if (is_sta_active(pcmn_sta_info)) + dm->phydm_macid_table[pcmn_sta_info->mac_id] = entry_idx; +} + +void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + struct rtl8192cd_priv *priv = dm->priv; + + #if IS_EXIST_PCI || IS_EXIST_EMBEDDED + GET_HAL_INTERFACE(priv)->AddInterruptMaskHandler(priv, interrupt_type); + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#endif +} + +void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + struct rtl8192cd_priv *priv = dm->priv; + + #if IS_EXIST_PCI || IS_EXIST_EMBEDDED + GET_HAL_INTERFACE(priv)->EnableRxRelatedInterruptHandler(priv); + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#endif +} + #if 0 - #ifdef RTW_HALMAC - #include "../hal_halmac.h" - struct _ADAPTER *adapter = p_dm_odm->adapter; - - if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0) - iqk_result = HAL_STATUS_SUCCESS; +boolean +phydm_get_txbf_en( + struct dm_struct *dm, + u16 mac_id, + u8 i +) +{ + boolean txbf_en = false; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && !defined(DM_ODM_CE_MAC80211) + +#ifdef CONFIG_BEAMFORMING + enum beamforming_cap beamform_cap; + void *adapter = dm->adapter; + #if (BEAMFORMING_SUPPORT == 1) + beamform_cap = + phydm_beamforming_get_entry_beam_cap_by_mac_id(dm, mac_id); + #else/*@for drv beamforming*/ + beamform_cap = + beamforming_get_entry_beam_cap_by_mac_id(&adapter->mlmepriv, mac_id); + #endif + if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + txbf_en = true; + else + txbf_en = false; +#endif /*@#ifdef CONFIG_BEAMFORMING*/ + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) + +#if (BEAMFORMING_SUPPORT == 1) + u8 idx = 0xff; + boolean act_bfer = false; + BEAMFORMING_CAP beamform_cap = BEAMFORMING_CAP_NONE; + PRT_BEAMFORMING_ENTRY entry = NULL; + struct rtl8192cd_priv *priv = dm->priv; + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + + dm_bdc_table->num_txbfee_client = 0; + dm_bdc_table->num_txbfer_client = 0; + #endif +#endif + +#if (BEAMFORMING_SUPPORT == 1) + beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, mac_id); + entry = Beamforming_GetEntryByMacId(priv, mac_id, &idx); + if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { + if (entry->Sounding_En) + txbf_en = true; + else + txbf_en = false; + act_bfer = true; + } + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*@BDC*/ + if (act_bfer == true) { + dm_bdc_table->w_bfee_client[i] = true; /* @AP act as BFer */ + dm_bdc_table->num_txbfee_client++; + } else + dm_bdc_table->w_bfee_client[i] = false; /* @AP act as BFer */ + + if (beamform_cap & (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP_VHT_SU)) { + dm_bdc_table->w_bfer_client[i] = true; /* @AP act as BFee */ + dm_bdc_table->num_txbfer_client++; + } else + dm_bdc_table->w_bfer_client[i] = false; /* @AP act as BFer */ + #endif #endif + #endif - return iqk_result; + return txbf_en; +} +#endif + +void phydm_iqk_wait(struct dm_struct *dm, u32 timeout) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n"); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#else + void *adapter = dm->adapter; + + rtl8812_iqk_wait(adapter, timeout); +#endif +#endif +} + +u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + return HwRateToMRate(rate); +#endif + return 0; } +void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + ROM_odm_SetCrystalCap(dm, crystal_cap); +#endif +} + +void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *), + void *context) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n"); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *adapter = dm->adapter; + + rtw_run_in_thread_cmd(adapter, func, context); +#endif +} diff --git a/hal/phydm/phydm_interface.h b/hal/phydm/phydm_interface.h index d37a959..f76f7b4 100644 --- a/hal/phydm/phydm_interface.h +++ b/hal/phydm/phydm_interface.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,440 +8,333 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ - + * Larry Finger + * + *****************************************************************************/ -#ifndef __ODM_INTERFACE_H__ +#ifndef __ODM_INTERFACE_H__ #define __ODM_INTERFACE_H__ -#define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/ +#define INTERFACE_VERSION "1.2" + +#define pdm_set_reg odm_set_bb_reg + +/*@=========== Constant/Structure/Enum/... Define*/ + +enum phydm_h2c_cmd { + PHYDM_H2C_RA_MASK = 0x40, + PHYDM_H2C_TXBF = 0x41, + ODM_H2C_RSSI_REPORT = 0x42, + ODM_H2C_IQ_CALIBRATION = 0x45, + PHYDM_RA_MASK_ABOVE_3SS = 0x46, + ODM_H2C_RA_PARA_ADJUST = 0x47, + PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, + PHYDM_H2C_FW_TRACE_EN = 0x49, + ODM_H2C_WIFI_CALIBRATION = 0x6d, + PHYDM_H2C_MU = 0x4a, + PHYDM_H2C_FW_GENERAL_INIT = 0x4c, + PHYDM_H2C_FW_CLM_MNTR = 0x4d, + PHYDM_H2C_MCC = 0x4f, + ODM_MAX_H2CCMD +}; + +enum phydm_c2h_evt { + PHYDM_C2H_DBG = 0, + PHYDM_C2H_LB = 1, + PHYDM_C2H_XBF = 2, + PHYDM_C2H_TX_REPORT = 3, + PHYDM_C2H_INFO = 9, + PHYDM_C2H_BT_MP = 11, + PHYDM_C2H_RA_RPT = 12, + PHYDM_C2H_RA_PARA_RPT = 14, + PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, + PHYDM_C2H_IQK_FINISH = 17, /*@0x11*/ + PHYDM_C2H_CLM_MONITOR = 0x2a, + PHYDM_C2H_DBG_CODE = 0xFE, + PHYDM_C2H_EXTEND = 0xFF, +}; -/* - * =========== Constant/Structure/Enum/... Define - * */ +enum phydm_extend_c2h_evt { + PHYDM_EXTEND_C2H_DBG_PRINT = 0 +}; +enum phydm_halmac_param { + PHYDM_HALMAC_CMD_MAC_W8 = 0, + PHYDM_HALMAC_CMD_MAC_W16 = 1, + PHYDM_HALMAC_CMD_MAC_W32 = 2, + PHYDM_HALMAC_CMD_BB_W8, + PHYDM_HALMAC_CMD_BB_W16, + PHYDM_HALMAC_CMD_BB_W32, + PHYDM_HALMAC_CMD_RF_W, + PHYDM_HALMAC_CMD_DELAY_US, + PHYDM_HALMAC_CMD_DELAY_MS, + PHYDM_HALMAC_CMD_END = 0XFF, +}; -/* - * =========== Macro Define - * */ +/*@=========== Macro Define*/ #define _reg_all(_name) ODM_##_name #define _reg_ic(_name, _ic) ODM_##_name##_ic #define _bit_all(_name) BIT_##_name #define _bit_ic(_name, _ic) BIT_##_name##_ic -/* _cat: implemented by Token-Pasting Operator. */ +/* @_cat: implemented by Token-Pasting Operator. */ #if 0 -#define _cat(_name, _ic_type, _func) \ - (\ - _func##_all(_name) \ - ) +#define _cat(_name, _ic_type, _func) \ + ( \ + _func##_all(_name)) #endif -/*=================================== +#if 0 #define ODM_REG_DIG_11N 0xC50 #define ODM_REG_DIG_11AC 0xDDD ODM_REG(DIG,_pdm_odm) -=====================================*/ +#endif + +#if defined(DM_ODM_CE_MAC80211) +#define ODM_BIT(name, dm) \ + ((dm->support_ic_type & ODM_IC_11N_SERIES) ? \ + ODM_BIT_##name##_11N : ODM_BIT_##name##_11AC) +#define ODM_REG(name, dm) \ + ((dm->support_ic_type & ODM_IC_11N_SERIES) ? \ + ODM_REG_##name##_11N : ODM_REG_##name##_11AC) +#else #define _reg_11N(_name) ODM_REG_##_name##_11N #define _reg_11AC(_name) ODM_REG_##_name##_11AC #define _bit_11N(_name) ODM_BIT_##_name##_11N #define _bit_11AC(_name) ODM_BIT_##_name##_11AC #ifdef __ECOS -#define _rtk_cat(_name, _ic_type, _func) \ - (\ - ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ - _func##_11AC(_name) \ - ) +#define _rtk_cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ + _func##_11AC(_name)) #else -#define _cat(_name, _ic_type, _func) \ - (\ - ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ - _func##_11AC(_name) \ - ) +#define _cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ + _func##_11AC(_name)) #endif -/* +/*@ * only sample code - *#define _cat(_name, _ic_type, _func) \ - * ( \ - * ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) : \ - * _func##_ic(_name, _8195) \ + *#define _cat(_name, _ic_type, _func) \ + * ( \ + * ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) :\ + * _func##_ic(_name, _8195) \ * ) */ -/* _name: name of register or bit. - * Example: "ODM_REG(R_A_AGC_CORE1, p_dm_odm)" - * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on support_ic_type. */ +/* @_name: name of register or bit. + * Example: "ODM_REG(R_A_AGC_CORE1, dm)" + * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", + * depends on support_ic_type. + */ #ifdef __ECOS - #define ODM_REG(_name, _pdm_odm) _rtk_cat(_name, _pdm_odm->support_ic_type, _reg) - #define ODM_BIT(_name, _pdm_odm) _rtk_cat(_name, _pdm_odm->support_ic_type, _bit) + #define ODM_REG(_name, _pdm_odm) \ + _rtk_cat(_name, _pdm_odm->support_ic_type, _reg) + #define ODM_BIT(_name, _pdm_odm) \ + _rtk_cat(_name, _pdm_odm->support_ic_type, _bit) #else - #define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg) - #define ODM_BIT(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _bit) + #define ODM_REG(_name, _pdm_odm) \ + _cat(_name, _pdm_odm->support_ic_type, _reg) + #define ODM_BIT(_name, _pdm_odm) \ + _cat(_name, _pdm_odm->support_ic_type, _bit) #endif -enum phydm_h2c_cmd { - PHYDM_H2C_TXBF = 0x41, - ODM_H2C_RSSI_REPORT = 0x42, - ODM_H2C_IQ_CALIBRATION = 0x45, - ODM_H2C_RA_PARA_ADJUST = 0x47, - PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, - PHYDM_H2C_FW_TRACE_EN = 0x49, - ODM_H2C_WIFI_CALIBRATION = 0x6d, - PHYDM_H2C_MU = 0x4a, - PHYDM_H2C_FW_GENERAL_INIT = 0x4c, - ODM_MAX_H2CCMD -}; - -enum phydm_c2h_evt { - PHYDM_C2H_DBG = 0, - PHYDM_C2H_LB = 1, - PHYDM_C2H_XBF = 2, - PHYDM_C2H_TX_REPORT = 3, - PHYDM_C2H_INFO = 9, - PHYDM_C2H_BT_MP = 11, - PHYDM_C2H_RA_RPT = 12, - PHYDM_C2H_RA_PARA_RPT = 14, - PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, - PHYDM_C2H_IQK_FINISH = 17, /*0x11*/ - PHYDM_C2H_DBG_CODE = 0xFE, - PHYDM_C2H_EXTEND = 0xFF, -}; - -enum phydm_extend_c2h_evt { - PHYDM_EXTEND_C2H_DBG_PRINT = 0 -}; - - -/* +#endif +/*@ * =========== Extern Variable ??? It should be forbidden. - * */ - + */ -/* +/*@ * =========== EXtern Function Prototype - * */ - - -u8 -odm_read_1byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr -); + */ -u16 -odm_read_2byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr -); +u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr); -u32 -odm_read_4byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr -); +u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr); -void -odm_write_1byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u8 data -); +u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr); -void -odm_write_2byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u16 data -); +void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data); -void -odm_write_4byte( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u32 data -); +void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data); -void -odm_set_mac_reg( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u32 bit_mask, - u32 data -); +void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data); -u32 -odm_get_mac_reg( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u32 bit_mask -); +void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, + u32 data); -void -odm_set_bb_reg( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u32 bit_mask, - u32 data -); +u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask); -u32 -odm_get_bb_reg( - struct PHY_DM_STRUCT *p_dm_odm, - u32 reg_addr, - u32 bit_mask -); +void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data); -void -odm_set_rf_reg( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e e_rf_path, - u32 reg_addr, - u32 bit_mask, - u32 data -); +u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask); -u32 -odm_get_rf_reg( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e e_rf_path, - u32 reg_addr, - u32 bit_mask -); +void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr, + u32 bit_mask, u32 data); +u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr, + u32 bit_mask); -/* +/*@ * Memory Relative Function. - * */ -void -odm_allocate_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void **p_ptr, - u32 length -); -void -odm_free_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_ptr, - u32 length -); + */ +void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length); +void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length); -void -odm_move_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_dest, - void *p_src, - u32 length -); +void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length); -s32 odm_compare_memory( - struct PHY_DM_STRUCT *p_dm_odm, - void *p_buf1, - void *p_buf2, - u32 length -); +s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2, + u32 length); -void odm_memory_set -(struct PHY_DM_STRUCT *p_dm_odm, - void *pbuf, - s8 value, - u32 length); +void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length); -/* +/*@ * ODM MISC-spin lock relative API. - * */ -void -odm_acquire_spin_lock( - struct PHY_DM_STRUCT *p_dm_odm, - enum rt_spinlock_type type -); + */ +void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type); -void -odm_release_spin_lock( - struct PHY_DM_STRUCT *p_dm_odm, - enum rt_spinlock_type type -); +void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -/* +/*@ * ODM MISC-workitem relative API. - * */ -void -odm_initialize_work_item( - struct PHY_DM_STRUCT *p_dm_odm, - PRT_WORK_ITEM p_rt_work_item, - RT_WORKITEM_CALL_BACK rt_work_item_callback, - void *p_context, - const char *sz_id -); + */ +void odm_initialize_work_item( + struct dm_struct *dm, + PRT_WORK_ITEM p_rt_work_item, + RT_WORKITEM_CALL_BACK rt_work_item_callback, + void *context, + const char *sz_id); -void -odm_start_work_item( - PRT_WORK_ITEM p_rt_work_item -); +void odm_start_work_item( + PRT_WORK_ITEM p_rt_work_item); -void -odm_stop_work_item( - PRT_WORK_ITEM p_rt_work_item -); +void odm_stop_work_item( + PRT_WORK_ITEM p_rt_work_item); -void -odm_free_work_item( - PRT_WORK_ITEM p_rt_work_item -); +void odm_free_work_item( + PRT_WORK_ITEM p_rt_work_item); -void -odm_schedule_work_item( - PRT_WORK_ITEM p_rt_work_item -); +void odm_schedule_work_item( + PRT_WORK_ITEM p_rt_work_item); boolean odm_is_work_item_scheduled( - PRT_WORK_ITEM p_rt_work_item -); + PRT_WORK_ITEM p_rt_work_item); #endif -/* +/*@ * ODM Timer relative API. - * */ -void -odm_stall_execution( - u32 us_delay -); - -void -ODM_delay_ms(u32 ms); + */ +void ODM_delay_ms(u32 ms); +void ODM_delay_us(u32 us); +void ODM_sleep_ms(u32 ms); -void -ODM_delay_us(u32 us); +void ODM_sleep_us(u32 us); -void -ODM_sleep_ms(u32 ms); +void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer, + u32 ms_delay); -void -ODM_sleep_us(u32 us); +void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer, + void *call_back_func, void *context, + const char *sz_id); -void -odm_set_timer( - struct PHY_DM_STRUCT *p_dm_odm, - struct timer_list *p_timer, - u32 ms_delay -); +void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer); -void -odm_initialize_timer( - struct PHY_DM_STRUCT *p_dm_odm, - struct timer_list *p_timer, - void *call_back_func, - void *p_context, - const char *sz_id -); +void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer); -void -odm_cancel_timer( - struct PHY_DM_STRUCT *p_dm_odm, - struct timer_list *p_timer -); +/*ODM FW relative API.*/ -void -odm_release_timer( - struct PHY_DM_STRUCT *p_dm_odm, - struct timer_list *p_timer -); +enum hal_status +phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type, + u32 offset, u32 data, u32 mask, enum rf_path e_rf_path, + u32 delay_time); -/* - * ODM FW relative API. - * */ -void -odm_fill_h2c_cmd( - struct PHY_DM_STRUCT *p_dm_odm, - u8 element_id, - u32 cmd_len, - u8 *p_cmd_buffer -); +void odm_fill_h2c_cmd(struct dm_struct *dm, u8 element_id, u32 cmd_len, + u8 *cmd_buffer); -u8 -phydm_c2H_content_parsing( - void *p_dm_void, - u8 c2h_cmd_id, - u8 c2h_cmd_len, - u8 *tmp_buf -); +u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len, + u8 *tmp_buf); -u64 -odm_get_current_time( - struct PHY_DM_STRUCT *p_dm_odm -); -u64 -odm_get_progressing_time( - struct PHY_DM_STRUCT *p_dm_odm, - u64 start_time -); +u64 odm_get_current_time(struct dm_struct *dm); +u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \ + (!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2)) -void -phydm_set_hw_reg_handler_interface ( - struct PHY_DM_STRUCT *p_dm_odm, - u8 reg_Name, - u8 *val - ); +void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 reg_Name, + u8 *val); -void -phydm_get_hal_def_var_handler_interface ( - struct PHY_DM_STRUCT *p_dm_odm, - enum _HAL_DEF_VARIABLE e_variable, - void *p_value - ); +void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm, + enum _HAL_DEF_VARIABLE e_variable, + void *value); #endif -void -odm_set_tx_power_index_by_rate_section ( - struct PHY_DM_STRUCT *p_dm_odm, - u8 RFPath, - u8 Channel, - u8 RateSection -); +void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm, + enum rf_path path, u8 channel, + u8 rate_section); -u8 -odm_get_tx_power_index ( - struct PHY_DM_STRUCT *p_dm_odm, - u8 RFPath, - u8 tx_rate, - u8 band_width, - u8 Channel -); +u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 tx_rate, + u8 band_width, u8 channel); -u8 -odm_efuse_one_byte_read( - struct PHY_DM_STRUCT *p_dm_odm, - u16 addr, - u8 *data, - boolean bPseudoTest -); +u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data, + boolean b_pseu_do_test); + +void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset, + u32 *data); enum hal_status -odm_iq_calibrate_by_fw( - struct PHY_DM_STRUCT *p_dm_odm, - u8 clear, - u8 segment +odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment); + +void odm_cmn_info_ptr_array_hook(struct dm_struct *dm, + enum odm_cmninfo cmn_info, u16 index, + void *value); + +void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 index, + struct cmn_sta_info *pcmn_sta_info); + +void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx, + struct cmn_sta_info *pcmn_sta_info); + +void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type); + +void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm); + +#if 0 +boolean +phydm_get_txbf_en( + struct dm_struct *dm, + u16 mac_id, + u8 i ); -#endif /* __ODM_INTERFACE_H__ */ +#endif + +void phydm_iqk_wait(struct dm_struct *dm, u32 timeout); + +u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate); +void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap); +void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *), + void *context); +#endif /* @__ODM_INTERFACE_H__ */ diff --git a/hal/phydm/phydm_lna_sat.c b/hal/phydm/phydm_lna_sat.c new file mode 100644 index 0000000..03be697 --- /dev/null +++ b/hal/phydm/phydm_lna_sat.c @@ -0,0 +1,1354 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + * *************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 +void phydm_lna_sat_chk_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + + lna_info->check_time = 0; + lna_info->sat_cnt_acc_patha = 0; + lna_info->sat_cnt_acc_pathb = 0; + #ifdef PHYDM_IC_ABOVE_3SS + lna_info->sat_cnt_acc_pathc = 0; + #endif + #ifdef PHYDM_IC_ABOVE_4SS + lna_info->sat_cnt_acc_pathd = 0; + #endif + lna_info->cur_sat_status = 0; + lna_info->pre_sat_status = 0; + lna_info->cur_timer_check_cnt = 0; + lna_info->pre_timer_check_cnt = 0; + + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & + (ODM_RTL8198F | ODM_RTL8814B)) + phydm_lna_sat_chk_bb_init(dm); + #endif +} + +#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) +void phydm_lna_sat_chk_bb_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info; + + boolean disable_bb_switch_tab = false; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + + /*@set table switch mux r_6table_sel_anten*/ + odm_set_bb_reg(dm, 0x18ac, BIT(8), 0); + + /*@tab decision when idle*/ + odm_set_bb_reg(dm, 0x18ac, BIT(16), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x41ac, BIT(16), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x52ac, BIT(16), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x53ac, BIT(16), disable_bb_switch_tab); + /*@tab decision when ofdmcca*/ + odm_set_bb_reg(dm, 0x18ac, BIT(17), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x41ac, BIT(17), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x52ac, BIT(17), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x53ac, BIT(17), disable_bb_switch_tab); +} + +void phydm_set_ofdm_agc_tab_path( + void *dm_void, + u8 tab_sel, + enum rf_path path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "set AGC Tab%d\n", tab_sel); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "r_6table_sel_anten = 0x%x\n", + odm_get_bb_reg(dm, 0x18ac, BIT(8))); + } + + if (dm->support_ic_type & ODM_RTL8198F) { + /*@table sel:0/2, mapping 2 to 1 */ + if (tab_sel == OFDM_AGC_TAB_0) { + odm_set_bb_reg(dm, 0x18ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x41ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x52ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x53ac, BIT(4), 0); + } else if (tab_sel == OFDM_AGC_TAB_2) { + odm_set_bb_reg(dm, 0x18ac, BIT(4), 1); + odm_set_bb_reg(dm, 0x41ac, BIT(4), 1); + odm_set_bb_reg(dm, 0x52ac, BIT(4), 1); + odm_set_bb_reg(dm, 0x53ac, BIT(4), 1); + } else { + odm_set_bb_reg(dm, 0x18ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x41ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x52ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x53ac, BIT(4), 0); + } + } else if (dm->support_ic_type & ODM_RTL8814B) { + if (tab_sel == OFDM_AGC_TAB_0) { + odm_set_bb_reg(dm, 0x18ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x41ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x52ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x53ac, 0xf0, 0); + } else if (tab_sel == OFDM_AGC_TAB_2) { + odm_set_bb_reg(dm, 0x18ac, 0xf0, 2); + odm_set_bb_reg(dm, 0x41ac, 0xf0, 2); + odm_set_bb_reg(dm, 0x52ac, 0xf0, 2); + odm_set_bb_reg(dm, 0x53ac, 0xf0, 2); + } else { + odm_set_bb_reg(dm, 0x18ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x41ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x52ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x53ac, 0xf0, 0); + } + } +} + +u8 phydm_get_ofdm_agc_tab_path( + void *dm_void, + enum rf_path path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 tab_sel = 0; + + if (dm->support_ic_type & ODM_RTL8198F) { + tab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, BIT(4)); + if (tab_sel == 0) + tab_sel = OFDM_AGC_TAB_0; + else if (tab_sel == 1) + tab_sel = OFDM_AGC_TAB_2; + } else if (dm->support_ic_type & ODM_RTL8814B) { + tab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, 0xf0); + if (tab_sel == 0) + tab_sel = OFDM_AGC_TAB_0; + else if (tab_sel == 2) + tab_sel = OFDM_AGC_TAB_2; + } + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "get path %d AGC Tab %d\n", + path, tab_sel); + return tab_sel; +} +#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/ + +void phydm_set_ofdm_agc_tab( + void *dm_void, + u8 tab_sel) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*@table sel:0/2, 1 is used for CCK */ + if (tab_sel == OFDM_AGC_TAB_0) + odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0); + else if (tab_sel == OFDM_AGC_TAB_2) + odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_2); + else + odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0); +} + +u8 phydm_get_ofdm_agc_tab( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + return (u8)odm_get_bb_reg(dm, R_0xc70, 0x1e00); +} + +void phydm_lna_sat_chk( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info; + u8 igi_rssi_min; + u8 rssi_min = dm->rssi_min; + u32 sat_status_a, sat_status_b; + #ifdef PHYDM_IC_ABOVE_3SS + u32 sat_status_c; + #endif + #ifdef PHYDM_IC_ABOVE_4SS + u32 sat_status_d; + #endif + u8 igi_restore = dig_t->cur_ig_value; + u8 i, chk_cnt = lna_info->chk_cnt; + u32 lna_sat_cnt_thd = 0; + u8 agc_tab; + u32 max_check_time = 0; + /*@use rssi_max if rssi_min is not stable;*/ + /*@rssi_min = dm->rssi_max;*/ + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__); + + if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Func disable\n"); + return; + } + + if (lna_info->is_disable_lna_sat_chk) { + phydm_lna_sat_chk_init(dm); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "disable_lna_sat_chk\n"); + return; + } + + /*@move igi to target pin of rssi_min */ + if (rssi_min == 0 || rssi_min == 0xff) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "rssi_min=%d, set AGC Tab0\n", rssi_min); + /*@adapt agc table 0*/ + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + phydm_lna_sat_chk_init(dm); + return; + } else if (rssi_min % 2 != 0) { + igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI - 1; + } else { + igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI; + } + + if ((lna_info->chk_period > 0) && (lna_info->chk_period <= ONE_SEC_MS)) + max_check_time = chk_cnt * (ONE_SEC_MS / (lna_info->chk_period)) * 5; + else + max_check_time = chk_cnt * 5; + + lna_sat_cnt_thd = (max_check_time * lna_info->chk_duty_cycle) / 100; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "check_time=%d, rssi_min=%d, igi_rssi_min=0x%x\nchk_cnt=%d, chk_period=%d, max_check_time=%d, lna_sat_cnt_thd=%d\n", + lna_info->check_time, + rssi_min, + igi_rssi_min, + chk_cnt, + lna_info->chk_period, + max_check_time, + lna_sat_cnt_thd); + + odm_write_dig(dm, igi_rssi_min); + + /*@adapt agc table 0 check saturation status*/ + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + phydm_set_ofdm_agc_tab_path(dm, OFDM_AGC_TAB_0, RF_PATH_A); + else + #endif + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + /*@open rf power detection ckt & set detection range */ + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) { + /*@set rf detection range (threshold)*/ + config_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x85, + 0x3f, 0x3f); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x85, + 0x3f, 0x3f); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x85, + 0x3f, 0x3f); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x85, + 0x3f, 0x3f); + /*@open rf power detection ckt*/ + config_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x86, 0x10, 1); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x86, 0x10, 1); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x86, 0x10, 1); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x86, 0x10, 1); + } else if (dm->support_ic_type & ODM_RTL8814B) { + /*@set rf detection range (threshold)*/ +#if 0 + config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x85, + 0x3f, 0x3f); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x85, + 0x3f, 0x3f); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x85, + 0x3f, 0x3f); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x85, + 0x3f, 0x3f); +#endif + /*@open rf power detection ckt*/ +#if 0 + config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x86, 0x10, 1); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x86, 0x10, 1); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x86, 0x10, 1); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x86, 0x10, 1); +#endif + } else + #endif + { + odm_set_rf_reg(dm, RF_PATH_A, RF_0x86, 0x1f, 0x10); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x86, 0x1f, 0x10); + #ifdef PHYDM_IC_ABOVE_3SS + odm_set_rf_reg(dm, RF_PATH_C, RF_0x86, 0x1f, 0x10); + #endif + #ifdef PHYDM_IC_ABOVE_4SS + odm_set_rf_reg(dm, RF_PATH_D, RF_0x86, 0x1f, 0x10); + #endif + } + + /*@check saturation status*/ + for (i = 0; i < chk_cnt; i++) { + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) { + sat_status_a = config_phydm_read_rf_reg_8198f(dm, RF_PATH_A, + RF_0xae, + 0xe0000); + sat_status_b = config_phydm_read_rf_reg_8198f(dm, RF_PATH_B, + RF_0xae, + 0xe0000); + sat_status_c = config_phydm_read_rf_reg_8198f(dm, RF_PATH_C, + RF_0xae, + 0xe0000); + sat_status_d = config_phydm_read_rf_reg_8198f(dm, RF_PATH_D, + RF_0xae, + 0xe0000); + } else if (dm->support_ic_type & ODM_RTL8814B) { + /*@read peak detector info from 8814B rf reg*/ +#if 0 + sat_status_a = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A, + RF_0xae, + 0xe0000); + sat_status_b = config_phydm_read_rf_reg_8814b(dm, RF_PATH_B, + RF_0xae, + 0xe0000); + sat_status_c = config_phydm_read_rf_reg_8814b(dm, RF_PATH_C, + RF_0xae, + 0xe0000); + sat_status_d = config_phydm_read_rf_reg_8814b(dm, RF_PATH_D, + RF_0xae, + 0xe0000); +#endif + } else + #endif + { + sat_status_a = odm_get_rf_reg(dm, RF_PATH_A, RF_0xae, 0xc0000); + sat_status_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0xae, 0xc0000); + #ifdef PHYDM_IC_ABOVE_3SS + sat_status_c = odm_get_rf_reg(dm, RF_PATH_C, RF_0xae, 0xc0000); + #endif + #ifdef PHYDM_IC_ABOVE_4SS + sat_status_d = odm_get_rf_reg(dm, RF_PATH_D, RF_0xae, 0xc0000); + #endif + } + + if (sat_status_a != 0) + lna_info->sat_cnt_acc_patha++; + if (sat_status_b != 0) + lna_info->sat_cnt_acc_pathb++; + #ifdef PHYDM_IC_ABOVE_3SS + if (sat_status_c != 0) + lna_info->sat_cnt_acc_pathc++; + #endif + #ifdef PHYDM_IC_ABOVE_4SS + if (sat_status_d != 0) + lna_info->sat_cnt_acc_pathd++; + #endif + + if (lna_info->sat_cnt_acc_patha >= lna_sat_cnt_thd || + lna_info->sat_cnt_acc_pathb >= lna_sat_cnt_thd || + #ifdef PHYDM_IC_ABOVE_3SS + lna_info->sat_cnt_acc_pathc >= lna_sat_cnt_thd || + #endif + #ifdef PHYDM_IC_ABOVE_4SS + lna_info->sat_cnt_acc_pathd >= lna_sat_cnt_thd || + #endif + 0) { + lna_info->cur_sat_status = 1; + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "cur_sat_status=%d, check_time=%d\n", + lna_info->cur_sat_status, + lna_info->check_time); + break; + } + lna_info->cur_sat_status = 0; + } + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_patha=%d, sat_cnt_acc_pathb=%d\n", + lna_info->cur_sat_status, + lna_info->pre_sat_status, + lna_info->sat_cnt_acc_patha, + lna_info->sat_cnt_acc_pathb); + + #ifdef PHYDM_IC_ABOVE_4SS + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_pathc=%d, sat_cnt_acc_pathd=%d\n", + lna_info->cur_sat_status, + lna_info->pre_sat_status, + lna_info->sat_cnt_acc_pathc, + lna_info->sat_cnt_acc_pathd); + #endif + /*@agc table decision*/ + if (lna_info->cur_sat_status) { + if (!lna_info->dis_agc_table_swh) + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + phydm_set_ofdm_agc_tab_path(dm, + OFDM_AGC_TAB_2, + RF_PATH_A); + else + #endif + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2); + else + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "disable set to AGC Tab%d\n", OFDM_AGC_TAB_2); + lna_info->check_time = 0; + lna_info->sat_cnt_acc_patha = 0; + lna_info->sat_cnt_acc_pathb = 0; + #ifdef PHYDM_IC_ABOVE_3SS + lna_info->sat_cnt_acc_pathc = 0; + #endif + #ifdef PHYDM_IC_ABOVE_4SS + lna_info->sat_cnt_acc_pathd = 0; + #endif + lna_info->pre_sat_status = lna_info->cur_sat_status; + + } else if (lna_info->check_time <= (max_check_time - 1)) { + if (lna_info->pre_sat_status && !lna_info->dis_agc_table_swh) + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + phydm_set_ofdm_agc_tab_path(dm, + OFDM_AGC_TAB_2, + RF_PATH_A); + else + #endif + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2); + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ckeck time not reached\n"); + if (lna_info->dis_agc_table_swh) + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "disable set to AGC Tab%d\n", OFDM_AGC_TAB_2); + lna_info->check_time++; + + } else if (lna_info->check_time >= max_check_time) { + if (!lna_info->dis_agc_table_swh) + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + phydm_set_ofdm_agc_tab_path(dm, + OFDM_AGC_TAB_0, + RF_PATH_A); + else + #endif + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ckeck time reached\n"); + if (lna_info->dis_agc_table_swh) + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "disable set to AGC Tab%d\n", OFDM_AGC_TAB_0); + lna_info->check_time = 0; + lna_info->sat_cnt_acc_patha = 0; + lna_info->sat_cnt_acc_pathb = 0; + #ifdef PHYDM_IC_ABOVE_3SS + lna_info->sat_cnt_acc_pathc = 0; + #endif + #ifdef PHYDM_IC_ABOVE_4SS + lna_info->sat_cnt_acc_pathd = 0; + #endif + lna_info->pre_sat_status = lna_info->cur_sat_status; + } + + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + agc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A); + else + #endif + agc_tab = phydm_get_ofdm_agc_tab(dm); + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "use AGC tab %d\n", agc_tab); + + /*@restore previous igi*/ + odm_write_dig(dm, igi_restore); + lna_info->cur_timer_check_cnt++; + odm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer, + lna_info->chk_period); +} + +void phydm_lna_sat_chk_callback( + void *dm_void + + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__); + phydm_lna_sat_chk(dm); +} + +void phydm_lna_sat_chk_timers( + void *dm_void, + u8 state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info; + + if (state == INIT_LNA_SAT_CHK_TIMMER) { + odm_initialize_timer(dm, + &lna_info->phydm_lna_sat_chk_timer, + (void *)phydm_lna_sat_chk_callback, NULL, + "phydm_lna_sat_chk_timer"); + } else if (state == CANCEL_LNA_SAT_CHK_TIMMER) { + odm_cancel_timer(dm, &lna_info->phydm_lna_sat_chk_timer); + } else if (state == RELEASE_LNA_SAT_CHK_TIMMER) { + odm_release_timer(dm, &lna_info->phydm_lna_sat_chk_timer); + } +} + +void phydm_lna_sat_chk_watchdog_type1( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info; + + u8 rssi_min = dm->rssi_min; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__); + + if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "func disable\n"); + return; + } + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "pre_timer_check_cnt=%d, cur_timer_check_cnt=%d\n", + lna_info->pre_timer_check_cnt, + lna_info->cur_timer_check_cnt); + + if (lna_info->is_disable_lna_sat_chk) { + phydm_lna_sat_chk_init(dm); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "is_disable_lna_sat_chk=%d, return\n", + lna_info->is_disable_lna_sat_chk); + return; + } + + if (!(dm->support_ic_type & + (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8814B))) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "support_ic_type not 97F/98F/14B, return\n"); + return; + } + + if (rssi_min == 0 || rssi_min == 0xff) { + /*@adapt agc table 0 */ + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + phydm_lna_sat_chk_init(dm); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "rssi_min=%d, return\n", rssi_min); + return; + } + + if (lna_info->cur_timer_check_cnt == lna_info->pre_timer_check_cnt) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "fail, restart timer\n"); + odm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer, + lna_info->chk_period); + } else { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Timer check pass\n"); + } + lna_info->pre_timer_check_cnt = lna_info->cur_timer_check_cnt; +} + +#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE1*/ + +#ifdef PHYDM_LNA_SAT_CHK_TYPE2 + +void phydm_bubble_sort( + void *dm_void, + u8 *array, + u16 array_length) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 i, j; + u8 temp; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + for (i = 0; i < (array_length - 1); i++) { + for (j = (i + 1); j < (array_length); j++) { + if (array[i] > array[j]) { + temp = array[i]; + array[i] = array[j]; + array[j] = temp; + } + } + } +} + +void phydm_lna_sat_chk_type2_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + u8 real_shift = pinfo->total_bit_shift; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + + pinfo->total_cnt_snr = 1 << real_shift; + pinfo->is_sm_done = TRUE; + pinfo->is_snr_done = FALSE; + pinfo->cur_snr_mean = 0; + pinfo->cur_snr_var = 0; + pinfo->cur_lower_snr_mean = 0; + pinfo->pre_snr_mean = 0; + pinfo->pre_snr_var = 0; + pinfo->pre_lower_snr_mean = 0; + pinfo->nxt_state = ORI_TABLE_MONITOR; + pinfo->pre_state = ORI_TABLE_MONITOR; +} + +void phydm_snr_collect( + void *dm_void, + u8 rx_snr) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + if (pinfo->is_sm_done) { +#if 0 + /*PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__);*/ +#endif + + /* @adapt only path-A for calculation */ + pinfo->snr_statistic[pinfo->cnt_snr_statistic] = rx_snr; + + if (pinfo->cnt_snr_statistic == (pinfo->total_cnt_snr - 1)) { + pinfo->is_snr_done = TRUE; + pinfo->cnt_snr_statistic = 0; + } else { + pinfo->cnt_snr_statistic++; + } + } else { + return; + } +} + +void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_t = &dm->dm_lna_sat_info; + struct phydm_perpkt_info_struct *pktinfo = NULL; + u8 target_macid = dm->rssi_min_macid; + + if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) + return; + + pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void; + + if (!pktinfo->is_packet_match_bssid) + return; + + if (lna_t->force_traget_macid != 0) + target_macid = lna_t->force_traget_macid; + + if (target_macid != pktinfo->station_id) + return; + + phydm_snr_collect(dm, rx_snr[0]); /*path-A B C D???*/ +} + +void phydm_snr_data_processing( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + u8 real_shift = pinfo->total_bit_shift; + u16 total_snr_cnt = pinfo->total_cnt_snr; + u16 total_loop_cnt = (total_snr_cnt - 1), i; + u32 temp; + u32 sum_snr_statistic = 0; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "total_loop_cnt=%d\n", total_loop_cnt); + + for (i = 0; (i <= total_loop_cnt); i++) { + if (pinfo->is_snr_detail_en) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "snr[%d]=%d\n", i, pinfo->snr_statistic[i]); + } + + sum_snr_statistic += (u32)(pinfo->snr_statistic[i]); + + pinfo->snr_statistic_sqr[i] = (u16)(pinfo->snr_statistic[i] * pinfo->snr_statistic[i]); + } + + phydm_bubble_sort(dm, pinfo->snr_statistic, pinfo->total_cnt_snr); + + /*update SNR's cur mean*/ + pinfo->cur_snr_mean = (sum_snr_statistic >> real_shift); + + for (i = 0; (i <= total_loop_cnt); i++) { + if (pinfo->snr_statistic[i] >= pinfo->cur_snr_mean) + temp = pinfo->snr_statistic[i] - pinfo->cur_snr_mean; + else + temp = pinfo->cur_snr_mean - pinfo->snr_statistic[i]; + + pinfo->cur_snr_var += (temp * temp); + } + + /*update SNR's VAR*/ + pinfo->cur_snr_var = (pinfo->cur_snr_var >> real_shift); + + /*@acquire lower SNR's statistics*/ + temp = 0; + pinfo->cnt_lower_snr_statistic = (total_snr_cnt >> pinfo->lwr_snr_ratio_bit_shift); + pinfo->cnt_lower_snr_statistic = MAX_2(pinfo->cnt_lower_snr_statistic, SNR_RPT_MAX); + + for (i = 0; i < pinfo->cnt_lower_snr_statistic; i++) + temp += pinfo->snr_statistic[i]; + + pinfo->cur_lower_snr_mean = temp >> (real_shift - pinfo->lwr_snr_ratio_bit_shift); +} + +boolean phydm_is_snr_improve( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + boolean is_snr_improve; + u8 cur_state = pinfo->nxt_state; + u32 cur_mean = pinfo->cur_snr_mean; + u32 pre_mean = pinfo->pre_snr_mean; + u32 cur_lower_mean = pinfo->cur_lower_snr_mean; + u32 pre_lower_mean = pinfo->pre_lower_snr_mean; + u32 cur_var = pinfo->cur_snr_var; + + /*special case, zero VAR, interference is gone*/ + /*@make sure pre_var is larger enough*/ + if (cur_state == SAT_TABLE_MONITOR || + cur_state == ORI_TABLE_TRAINING) { + if (cur_mean >= pre_mean) { + if (cur_var == 0) + return true; + } + } +#if 0 + /*special case, mean degrade less than VAR improvement*/ + /*@make sure pre_var is larger enough*/ + if (cur_state == ORI_TABLE_MONITOR && + cur_mean < pre_mean && + cur_var < pre_var) { + diff_mean = pre_mean - cur_mean; + diff_var = pre_var - cur_var; + return (diff_var > (2 * diff_mean * diff_mean)) ? true : false; + } + +#endif + if (cur_lower_mean >= (pre_lower_mean + pinfo->delta_snr_mean)) + is_snr_improve = true; + else + is_snr_improve = false; +#if 0 +/* @condition refine, mean is bigger enough or VAR is smaller enough*/ +/* @1. from mean's view, mean improve delta_snr_mean(2), VAR not degrade lot*/ + if (cur_mean > (pre_mean + pinfo->delta_snr_mean)) { + is_mean_improve = TRUE; + is_var_improve = (cur_var <= pre_var + dm->delta_snr_var) + ? TRUE : FALSE; + + } else if (cur_var + dm->delta_snr_var <= pre_var) { + is_var_improve = TRUE; + is_mean_improve = ((cur_mean + 1) >= pre_mean) ? TRUE : FALSE; + } else { + return false; + } +#endif + return is_snr_improve; +} + +boolean phydm_is_snr_degrade( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + u32 cur_lower_mean = pinfo->cur_lower_snr_mean; + u32 pre_lower_mean = pinfo->pre_lower_snr_mean; + boolean is_degrade; + + if (cur_lower_mean <= (pre_lower_mean - pinfo->delta_snr_mean)) + is_degrade = TRUE; + else + is_degrade = FALSE; +#if 0 + is_mean_dgrade = (pinfo->cur_snr_mean + pinfo->delta_snr_mean <= pinfo->pre_snr_mean) ? TRUE : FALSE; + is_var_degrade = (pinfo->cur_snr_var > (pinfo->pre_snr_var + pinfo->delta_snr_mean)) ? TRUE : FALSE; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d\n", + __func__, + pinfo->cur_snr_mean, + pinfo->pre_snr_mean, + pinfo->cur_snr_var, + pinfo->pre_snr_var); + + return (is_mean_dgrade & is_var_degrade); +#endif + return is_degrade; +} + +boolean phydm_is_large_var( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + boolean is_large_var = (pinfo->cur_snr_var >= pinfo->snr_var_thd) ? TRUE : FALSE; + + return is_large_var; +} + +void phydm_update_pre_status( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + pinfo->pre_lower_snr_mean = pinfo->cur_lower_snr_mean; + pinfo->pre_snr_mean = pinfo->cur_snr_mean; + pinfo->pre_snr_var = pinfo->cur_snr_var; +} + +void phydm_ori_table_monitor( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + if (phydm_is_large_var(dm)) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } else { + pinfo->nxt_state = ORI_TABLE_MONITOR; + /*switch to anti-sat table*/ + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + } + phydm_update_pre_status(dm); + pinfo->pre_state = ORI_TABLE_MONITOR; +} + +void phydm_sat_table_training( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + #if 0 + if pre_state = ORI_TABLE_MONITOR || SAT_TABLE_TRY_FAIL, + /*@"pre" adapt ori-table, "cur" adapt sat-table*/ + /*@adapt ori table*/ + if (pinfo->pre_state == ORI_TABLE_MONITOR) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } else { + #endif + if (phydm_is_snr_improve(dm)) { + pinfo->nxt_state = SAT_TABLE_MONITOR; + } else { + pinfo->nxt_state = SAT_TABLE_TRY_FAIL; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + } + /*@}*/ + + phydm_update_pre_status(dm); + pinfo->pre_state = SAT_TABLE_TRAINING; +} + +void phydm_sat_table_try_fail( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + /* @if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt ori-table */ + /* @if pre_state = SAT_TABLE_TRY_FAIL, "pre" adapt ori-table, "cur" adapt ori-table */ + + if (phydm_is_large_var(dm)) { + if (phydm_is_snr_degrade(dm)) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } else { + pinfo->nxt_state = SAT_TABLE_TRY_FAIL; + } + } else { + pinfo->nxt_state = ORI_TABLE_MONITOR; + } + phydm_update_pre_status(dm); + pinfo->pre_state = SAT_TABLE_TRY_FAIL; +} + +void phydm_sat_table_monitor( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + if (phydm_is_snr_improve(dm)) { + pinfo->sat_table_monitor_times = 0; + + /* @if pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt sat-table */ + if (pinfo->pre_state == SAT_TABLE_MONITOR) { + pinfo->nxt_state = ORI_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + //phydm_update_pre_status(dm); + } else { + pinfo->nxt_state = SAT_TABLE_MONITOR; + } + + /* @if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt sat-table */ + /* @if pre_state = ORI_TABLE_TRAINING, "pre" adapt ori-table, "cur" adapt sat-table */ + /*pre_state above is no need to update*/ + } else { + if (pinfo->sat_table_monitor_times == pinfo->force_change_period) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s: sat_table_monitor_times=%d\n", + __func__, pinfo->sat_table_monitor_times); + + pinfo->nxt_state = ORI_TABLE_TRAINING; + pinfo->sat_table_monitor_times = 0; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + } else { + pinfo->nxt_state = SAT_TABLE_MONITOR; + pinfo->sat_table_monitor_times++; + } + } + phydm_update_pre_status(dm); + pinfo->pre_state = SAT_TABLE_MONITOR; +} + +void phydm_ori_table_training( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + /* pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt ori-table */ + + if (phydm_is_snr_degrade(dm) == FALSE) { + pinfo->nxt_state = ORI_TABLE_MONITOR; + } else { + if (pinfo->pre_snr_var == 0) + pinfo->nxt_state = ORI_TABLE_TRY_FAIL; + else + pinfo->nxt_state = SAT_TABLE_MONITOR; + + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } + phydm_update_pre_status(dm); + pinfo->pre_state = ORI_TABLE_TRAINING; +} + +void phydm_ori_table_try_fail( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + if (pinfo->pre_state == ORI_TABLE_TRY_FAIL) { + if (phydm_is_snr_improve(dm)) { + pinfo->nxt_state = ORI_TABLE_TRAINING; + pinfo->ori_table_try_fail_times = 0; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + } else { + if (pinfo->ori_table_try_fail_times == pinfo->force_change_period) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "%s: ori_table_try_fail_times=%d\n", __func__, pinfo->ori_table_try_fail_times); + + pinfo->nxt_state = ORI_TABLE_TRY_FAIL; + pinfo->ori_table_try_fail_times = 0; + phydm_update_pre_status(dm); + } else { + pinfo->nxt_state = ORI_TABLE_TRY_FAIL; + pinfo->ori_table_try_fail_times++; + phydm_update_pre_status(dm); + //config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } + } + } else { + pinfo->nxt_state = ORI_TABLE_TRY_FAIL; + pinfo->ori_table_try_fail_times = 0; + phydm_update_pre_status(dm); + //config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } + +#if 0 + if (phydm_is_large_var(dm)) { + if (phydm_is_snr_degrade(dm)) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } else { + pinfo->nxt_state = SAT_TABLE_TRY_FAIL; + } + } else { + pinfo->nxt_state = ORI_TABLE_MONITOR; + } + + phydm_update_pre_status(dm); +#endif + pinfo->pre_state = ORI_TABLE_TRY_FAIL; +} + +char *phydm_lna_sat_state_msg( + void *dm_void, + IN u8 state) +{ + char *dbg_message; + + switch (state) { + case ORI_TABLE_MONITOR: + dbg_message = "ORI_TABLE_MONITOR"; + break; + + case SAT_TABLE_TRAINING: + dbg_message = "SAT_TABLE_TRAINING"; + break; + + case SAT_TABLE_TRY_FAIL: + dbg_message = "SAT_TABLE_TRY_FAIL"; + break; + + case SAT_TABLE_MONITOR: + dbg_message = "SAT_TABLE_MONITOR"; + break; + + case ORI_TABLE_TRAINING: + dbg_message = "ORI_TABLE_TRAINING"; + break; + + case ORI_TABLE_TRY_FAIL: + dbg_message = "ORI_TABLE_TRY_FAIL"; + break; + + default: + dbg_message = "ORI_TABLE_MONITOR"; + break; + } + + return dbg_message; +} + +void phydm_lna_sat_type2_sm( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + u8 state = pinfo->nxt_state; + u8 agc_tab = (u8)odm_get_bb_reg(dm, 0x958, 0x1f); + char *dbg_message, *nxt_dbg_message; + u8 real_shift = pinfo->total_bit_shift; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n\n%s ==>\n", __func__); + + if ((dm->support_ic_type & ODM_RTL8822B) == FALSE) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ODM_BB_LNA_SAT_CHK_TYPE2 only support 22B.\n"); + return; + } + + if ((dm->support_ability & ODM_BB_LNA_SAT_CHK) == FALSE) { + phydm_lna_sat_chk_type2_init(dm); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ODM_BB_LNA_SAT_CHK_TYPE2 is NOT supported, cur table=%d\n", agc_tab); + return; + } + + if (pinfo->is_snr_done) + phydm_snr_data_processing(dm); + else + return; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "cur agc table %d\n", agc_tab); + + if (pinfo->is_force_lna_sat_table != AUTO_AGC_TABLE) { + /*reset state machine*/ + pinfo->nxt_state = ORI_TABLE_MONITOR; + if (pinfo->is_snr_done) { + if (pinfo->is_force_lna_sat_table == DEFAULT_AGC_TABLE) + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + else if (pinfo->is_force_lna_sat_table == LNA_SAT_AGC_TABLE) + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + else + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n", + __func__, + pinfo->cur_snr_mean, + pinfo->pre_snr_mean, + pinfo->cur_snr_var, + pinfo->pre_snr_var, + pinfo->cur_lower_snr_mean, + pinfo->pre_lower_snr_mean, + pinfo->cnt_lower_snr_statistic); + + pinfo->is_snr_done = FALSE; + pinfo->is_sm_done = TRUE; + phydm_update_pre_status(dm); + } else { + return; + } + } else if (pinfo->is_snr_done) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n", + __func__, + pinfo->cur_snr_mean, + pinfo->pre_snr_mean, + pinfo->cur_snr_var, + pinfo->pre_snr_var, + pinfo->cur_lower_snr_mean, + pinfo->pre_lower_snr_mean, + pinfo->cnt_lower_snr_statistic); + + switch (state) { + case ORI_TABLE_MONITOR: + dbg_message = "ORI_TABLE_MONITOR"; + phydm_ori_table_monitor(dm); + break; + + case SAT_TABLE_TRAINING: + dbg_message = "SAT_TABLE_TRAINING"; + phydm_sat_table_training(dm); + break; + + case SAT_TABLE_TRY_FAIL: + dbg_message = "SAT_TABLE_TRY_FAIL"; + phydm_sat_table_try_fail(dm); + break; + + case SAT_TABLE_MONITOR: + dbg_message = "SAT_TABLE_MONITOR"; + phydm_sat_table_monitor(dm); + break; + + case ORI_TABLE_TRAINING: + dbg_message = "ORI_TABLE_TRAINING"; + phydm_ori_table_training(dm); + break; + + case ORI_TABLE_TRY_FAIL: + dbg_message = "ORI_TABLE_TRAINING"; + phydm_ori_table_try_fail(dm); + break; + + default: + dbg_message = "ORI_TABLE_MONITOR"; + phydm_ori_table_monitor(dm); + break; + } + + dbg_message = phydm_lna_sat_state_msg(dm, state); + nxt_dbg_message = phydm_lna_sat_state_msg(dm, pinfo->nxt_state); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "state: [%s]->[%s]\n", + dbg_message, nxt_dbg_message); + + pinfo->is_snr_done = FALSE; + pinfo->is_sm_done = TRUE; + pinfo->total_cnt_snr = 1 << real_shift; + + } else { + return; + } +} + + +#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE2*/ + +void phydm_lna_sat_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_t = &dm->dm_lna_sat_info; + char help[] = "-h"; + char monitor[] = "-m"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + u8 agc_tab = 0; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "help content:\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "monitor: -m\n"); + #ifdef PHYDM_LNA_SAT_CHK_TYPE1 + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0} {lna_sat_chk_en}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {agc_table_switch_en}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} {chk_cnt per callback}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3} {chk_period(ms)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{4} {chk_duty_cycle(percentage)}\n"); + #endif + } else if ((strcmp(input[1], monitor) == 0)) { +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + agc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A); + else + #endif + agc_tab = phydm_get_ofdm_agc_tab(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s%d, %s%d, %s%d, %s%d\n", + "check_time = ", lna_t->check_time, + "pre_sat_status = ", lna_t->pre_sat_status, + "cur_sat_status = ", lna_t->cur_sat_status, + "current AGC tab = ", agc_tab); +#endif + } else { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + for (i = 1; i < 10; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + #ifdef PHYDM_LNA_SAT_CHK_TYPE1 + if (var1[0] == 0) { + if (var1[1] == 1) { + lna_t->is_disable_lna_sat_chk = false; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "enable lna_sat_chk\n"); + } else if (var1[1] == 0) { + lna_t->is_disable_lna_sat_chk = true; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "disable lna_sat_chk\n"); + } + } else if (var1[0] == 1) { + if (var1[1] == 1) { + lna_t->dis_agc_table_swh = false; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "enable agc_table_switch\n"); + } else if (var1[1] == 0) { + lna_t->dis_agc_table_swh = true; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "disable agc_table_switch\n"); + } + } else if (var1[0] == 2) { + lna_t->chk_cnt = (u8)var1[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "set chk_cnt to %d\n", lna_t->chk_cnt); + } else if (var1[0] == 3) { + lna_t->chk_period = var1[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "set chk_period to %d\n", lna_t->chk_period); + } else if (var1[0] == 4) { + lna_t->chk_duty_cycle = (u8)var1[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "set chk_duty_cycle to %d\n", + lna_t->chk_duty_cycle); + } + #endif + #ifdef PHYDM_LNA_SAT_CHK_TYPE2 + if (var1[0] == 1) + lna_t->force_traget_macid = var1[1]; + #endif + } + *_used = used; + *_out_len = out_len; +} + +void phydm_lna_sat_chk_watchdog( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + + if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) { + #ifdef PHYDM_LNA_SAT_CHK_TYPE1 + phydm_lna_sat_chk_watchdog_type1(dm); + #endif + } else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) { + #ifdef PHYDM_LNA_SAT_CHK_TYPE2 + + #endif + } + +} + +void phydm_lna_sat_config( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info; + + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8822B)) + lna_sat->lna_sat_type = LNA_SAT_WITH_TRAIN; + #endif + + #if (RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\ + RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & + (ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8198F | ODM_RTL8814B)) + lna_sat->lna_sat_type = LNA_SAT_WITH_PEAK_DET; + #endif + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "[%s] lna_sat_type=%d\n", + __func__, lna_sat->lna_sat_type); +} + +void phydm_lna_sat_check_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info; + + if ((dm->support_ability & ODM_BB_LNA_SAT_CHK)) + return; + + /*@2018.04.17 Johnson*/ + phydm_lna_sat_config(dm); + #ifdef PHYDM_LNA_SAT_CHK_TYPE1 + lna_sat->chk_period = LNA_CHK_PERIOD; + lna_sat->chk_cnt = LNA_CHK_CNT; + lna_sat->chk_duty_cycle = LNA_CHK_DUTY_CYCLE; + lna_sat->dis_agc_table_swh = false; + #endif + /*@2018.04.17 Johnson end*/ + + if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) { + #ifdef PHYDM_LNA_SAT_CHK_TYPE1 + phydm_lna_sat_chk_init(dm); + #endif + } else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) { + #ifdef PHYDM_LNA_SAT_CHK_TYPE2 + phydm_lna_sat_chk_type2_init(dm); + #endif + } +} + +#endif /*@#ifdef PHYDM_LNA_SAT_CHK_SUPPORT*/ diff --git a/hal/phydm/phydm_lna_sat.h b/hal/phydm/phydm_lna_sat.h new file mode 100644 index 0000000..c9345b8 --- /dev/null +++ b/hal/phydm/phydm_lna_sat.h @@ -0,0 +1,173 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_LNA_SAT_H__ +#define __PHYDM_LNA_SAT_H__ +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ + +#define LNA_SAT_VERSION "1.0" + +/*@LNA saturation check*/ +#define OFDM_AGC_TAB_0 0 +#define OFDM_AGC_TAB_2 2 + +#define DIFF_RSSI_TO_IGI 10 +#define ONE_SEC_MS 1000 + +#define LNA_CHK_PERIOD 100 /*@ms*/ +#define LNA_CHK_CNT 10 /*@checks per callback*/ +#define LNA_CHK_DUTY_CYCLE 5 /*@percentage*/ + +#define DELTA_STD 2 +#define DELTA_MEAN 2 +#define SNR_STATISTIC_SHIFT 8 +#define SNR_RPT_MAX 256 + +/* @1 ============================================================ + * 1 enumrate + * 1 ============================================================ + */ + +enum lna_sat_timer_state { + INIT_LNA_SAT_CHK_TIMMER, + CANCEL_LNA_SAT_CHK_TIMMER, + RELEASE_LNA_SAT_CHK_TIMMER +}; + +#ifdef PHYDM_LNA_SAT_CHK_TYPE2 +enum lna_sat_chk_type2_status { + ORI_TABLE_MONITOR, + ORI_TABLE_TRAINING, + SAT_TABLE_MONITOR, + SAT_TABLE_TRAINING, + SAT_TABLE_TRY_FAIL, + ORI_TABLE_TRY_FAIL +}; + +#endif + +enum lna_sat_type { + LNA_SAT_WITH_PEAK_DET = 1, /*type1*/ + LNA_SAT_WITH_TRAIN = 2, /*type2*/ +}; + +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +struct phydm_lna_sat_t { +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 + u8 chk_cnt; + u8 chk_duty_cycle; + u32 chk_period;/*@ms*/ + boolean is_disable_lna_sat_chk; + boolean dis_agc_table_swh; +#endif +#ifdef PHYDM_LNA_SAT_CHK_TYPE2 + u8 force_traget_macid; + u32 snr_var_thd; + u32 delta_snr_mean; + u16 ori_table_try_fail_times; + u16 cnt_lower_snr_statistic; + u16 sat_table_monitor_times; + u16 force_change_period; + u8 is_snr_detail_en; + u8 is_force_lna_sat_table; + u8 lwr_snr_ratio_bit_shift; + u8 cnt_snr_statistic; + u16 snr_statistic_sqr[SNR_RPT_MAX]; + u8 snr_statistic[SNR_RPT_MAX]; + u8 is_sm_done; + u8 is_snr_done; + u32 cur_snr_var; + u8 total_bit_shift; + u8 total_cnt_snr; + u32 cur_snr_mean; + u8 cur_snr_var0; + u32 cur_lower_snr_mean; + u32 pre_snr_mean; + u32 pre_snr_var; + u32 pre_lower_snr_mean; + u8 nxt_state; + u8 pre_state; +#endif + enum lna_sat_type lna_sat_type; + u32 sat_cnt_acc_patha; + u32 sat_cnt_acc_pathb; +#ifdef PHYDM_IC_ABOVE_3SS + u32 sat_cnt_acc_pathc; +#endif +#ifdef PHYDM_IC_ABOVE_4SS + u32 sat_cnt_acc_pathd; +#endif + u32 check_time; + boolean pre_sat_status; + boolean cur_sat_status; + struct phydm_timer_list phydm_lna_sat_chk_timer; + u32 cur_timer_check_cnt; + u32 pre_timer_check_cnt; +}; + +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ +void phydm_lna_sat_chk_init(void *dm_void); + +u8 phydm_get_ofdm_agc_tab(void *dm_void); + +void phydm_lna_sat_chk(void *dm_void); + +void phydm_lna_sat_chk_timers(void *dm_void, u8 state); + +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 +#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) +void phydm_lna_sat_chk_bb_init(void *dm_void); + +void phydm_set_ofdm_agc_tab_path(void *dm_void, + u8 tab_sel, enum rf_path path); + +u8 phydm_get_ofdm_agc_tab_path(void *dm_void, enum rf_path path); +#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/ +#endif + +#ifdef PHYDM_LNA_SAT_CHK_TYPE2 +void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr); +#endif + +void phydm_lna_sat_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_lna_sat_chk_watchdog(void *dm_void); + +void phydm_lna_sat_check_init(void *dm_void); + +#endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/ +#endif diff --git a/hal/phydm/phydm_math_lib.c b/hal/phydm/phydm_math_lib.c new file mode 100644 index 0000000..0a3da79 --- /dev/null +++ b/hal/phydm/phydm_math_lib.c @@ -0,0 +1,211 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +const u16 db_invert_table[12][8] = { + {1, 1, 1, 2, 2, 2, 2, 3}, + {3, 3, 4, 4, 4, 5, 6, 6}, + {7, 8, 9, 10, 11, 13, 14, 16}, + {18, 20, 22, 25, 28, 32, 35, 40}, + {45, 50, 56, 63, 71, 79, 89, 100}, + {112, 126, 141, 158, 178, 200, 224, 251}, + {282, 316, 355, 398, 447, 501, 562, 631}, + {708, 794, 891, 1000, 1122, 1259, 1413, 1585}, + {1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, + {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000}, + {11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119}, + {28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} }; + +/*Y = 10*log(X)*/ +s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit) +{ + s32 Y, integer = 0, decimal = 0; + u32 i; + + if (X == 0) + X = 1; /* @log2(x), x can't be 0 */ + + for (i = (total_bit - 1); i > 0; i--) { + if (X & BIT(i)) { + integer = i; + if (i > 0) { + /*decimal is 0.5dB*3=1.5dB~=2dB */ + decimal = (X & BIT(i - 1)) ? 2 : 0; + } + break; + } + } + + Y = 3 * (integer - decimal_bit) + decimal; /* @10*log(x)=3*log2(x), */ + + return Y; +} + +s32 odm_sign_conversion(s32 value, u32 total_bit) +{ + if (value & BIT(total_bit - 1)) + value -= BIT(total_bit); + + return value; +} + +/*threshold must form low to high*/ +u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 i = 0; + u16 ret_val = 0; + u16 max_th = threshold[th_len - 1]; + + for (i = 0; i < th_len; i++) { + if (val < threshold[i]) { + ret_val = i; + break; + } else if (val >= max_th) { + ret_val = th_len; + break; + } + } + + return ret_val; +} + +void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out, + u8 seq_length) +{ + u8 i = 0, j = 0; + u32 tmp_a, tmp_b; + u32 tmp_idx_a, tmp_idx_b; + + for (i = 0; i < seq_length; i++) + rank_idx[i] = i; + + for (i = 0; i < (seq_length - 1); i++) { + for (j = 0; j < (seq_length - 1 - i); j++) { + tmp_a = value[j]; + tmp_b = value[j + 1]; + + tmp_idx_a = rank_idx[j]; + tmp_idx_b = rank_idx[j + 1]; + + if (tmp_a < tmp_b) { + value[j] = tmp_b; + value[j + 1] = tmp_a; + + rank_idx[j] = tmp_idx_b; + rank_idx[j + 1] = tmp_idx_a; + } + } + } + + for (i = 0; i < seq_length; i++) + idx_out[rank_idx[i]] = i + 1; +} + +u32 odm_convert_to_db(u32 value) +{ + u8 i; + u8 j; + u32 dB; + + value = value & 0xFFFF; + + for (i = 0; i < 12; i++) { + if (value <= db_invert_table[i][7]) + break; + } + + if (i >= 12) + return 96; /* @maximum 96 dB */ + + for (j = 0; j < 8; j++) { + if (value <= db_invert_table[i][j]) + break; + } + + dB = (i << 3) + j + 1; + + return dB; +} + +u32 phydm_db_2_linear(u32 value) +{ + u8 i; + u8 j; + u32 linear; + + /* @1dB~96dB */ + + value = value & 0xFF; + + i = (u8)((value - 1) >> 3); + j = (u8)(value - 1) - (i << 3); + + linear = db_invert_table[i][j]; + + return linear; +} + +u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num) +{ + u8 i = 0; + u16 val = 0; + u16 base = 5000; + + for (i = bit_num; i > 0; i--) { + if (frac_val & BIT(i - 1)) + val += (base >> (bit_num - i)); + } + return val; +} + +u32 phydm_gen_bitmask(u8 mask_num) +{ + u8 i = 0; + u32 bitmask = 0; + + if (mask_num > 32) + return 1; + + for (i = 0; i < mask_num; i++) + bitmask = (bitmask << 1) | BIT(0); + + return bitmask; +} + +s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num) +{ + if (val & BIT(bit_num - 1)) /*Sign BIT*/ + val -= (1 << bit_num); /*@2's*/ + + return val; +} + diff --git a/hal/phydm/phydm_math_lib.h b/hal/phydm/phydm_math_lib.h new file mode 100644 index 0000000..42a44bf --- /dev/null +++ b/hal/phydm/phydm_math_lib.h @@ -0,0 +1,114 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_MATH_LIB_H__ +#define __PHYDM_MATH_LIB_H__ + +#define AUTO_MATH_LIB_VERSION "1.0" /* @2017.06.06*/ + +/*@ + * 1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ + +#define DIVIDED_2(X) ((X) >> 1) +/*@1/3 ~ 11/32*/ +#if defined(DM_ODM_CE_MAC80211) +#define DIVIDED_3(X) ({ \ + u32 div_3_tmp = (X); \ + (((div_3_tmp) + ((div_3_tmp) << 1) + ((div_3_tmp) << 3)) >> 5); }) +#else +#define DIVIDED_3(X) (((X) + ((X) << 1) + ((X) << 3)) >> 5) +#endif +#define DIVIDED_4(X) ((X) >> 2) + +/*Store Ori Value*/ +#if defined(DM_ODM_CE_MAC80211) +#define WEIGHTING_AVG(v1, w1, v2, w2) \ + __WEIGHTING_AVG(v1, w1, v2, w2, typeof(v1), typeof(w1), typeof(v2), \ + typeof(w2)) +#define __WEIGHTING_AVG(v1, w1, v2, w2, t1, t2, t3, t4) ({ \ + t1 __w_a_v1 = (v1); \ + t2 __w_a_w1 = (w1); \ + t3 __w_a_v2 = (v2); \ + t4 __w_a_w2 = (w2); \ + ((__w_a_v1) * (__w_a_w1) + (__w_a_v2) * (__w_a_w2)) \ + / ((__w_a_w2) + (__w_a_w1)); }) +#else +#define WEIGHTING_AVG(v1, w1, v2, w2) \ + (((v1) * (w1) + (v2) * (w2)) / ((w2) + (w1))) +#endif + +/*Store 2^ma x Value*/ +#if defined(DM_ODM_CE_MAC80211) +#define MA_ACC(old, new_val, ma) ({ \ + s16 __ma_acc_o = (old); \ + (__ma_acc_o) - ((__ma_acc_o) >> (ma)) + (new_val); }) +#define GET_MA_VAL(val, ma) ({ \ + s16 __get_ma_tmp = (ma);\ + ((val) + (1 << ((__get_ma_tmp) - 1))) >> (__get_ma_tmp); }) +#else +#define MA_ACC(old, new_val, ma) ((old) - ((old) >> (ma)) + (new_val)) +#define GET_MA_VAL(val, ma) (((val) + (1 << ((ma) - 1))) >> (ma)) +#endif + +/*@ + * 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +/*@ + * 1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +/*@ + * 1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ + +s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit); + +s32 odm_sign_conversion(s32 value, u32 total_bit); + +u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len); + +void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out, + u8 seq_length); + +u32 odm_convert_to_db(u32 value); + +u32 phydm_db_2_linear(u32 value); + +u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num); + +u32 phydm_gen_bitmask(u8 mask_num); + +s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num); +#endif diff --git a/hal/phydm/phydm_mp.c b/hal/phydm/phydm_mp.c new file mode 100644 index 0000000..75b3c1c --- /dev/null +++ b/hal/phydm/phydm_mp.c @@ -0,0 +1,317 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_MP_SUPPORT +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + +void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone, + u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_mp *mp = &dm->dm_mp_table; + u8 start = RF_PATH_A, end = RF_PATH_A; + + switch (path) { + case RF_PATH_A: + case RF_PATH_B: + case RF_PATH_C: + case RF_PATH_D: + start = path; + end = path; + break; + case RF_PATH_AB: + start = RF_PATH_A; + end = RF_PATH_B; + break; + case RF_PATH_BC: + start = RF_PATH_B; + end = RF_PATH_C; + break; + case RF_PATH_ABC: + start = RF_PATH_A; + end = RF_PATH_C; + break; + case RF_PATH_BCD: + start = RF_PATH_B; + end = RF_PATH_D; + break; + case RF_PATH_ABCD: + start = RF_PATH_A; + end = RF_PATH_D; + break; + } + if (is_single_tone) { + mp->rf_reg0 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, 0xfffff); +#if 0 + mp->rfe_sel_a_0 = odm_get_bb_reg(dm, R_0x1840, MASKDWORD); + mp->rfe_sel_b_0 = odm_get_bb_reg(dm, R_0x4140, MASKDWORD); + mp->rfe_sel_c_0 = odm_get_bb_reg(dm, R_0x5240, MASKDWORD); + mp->rfe_sel_d_0 = odm_get_bb_reg(dm, R_0x5340, MASKDWORD); + mp->rfe_sel_a_1 = odm_get_bb_reg(dm, R_0x1844, MASKDWORD); + mp->rfe_sel_b_1 = odm_get_bb_reg(dm, R_0x4144, MASKDWORD); + mp->rfe_sel_c_1 = odm_get_bb_reg(dm, R_0x5244, MASKDWORD); + mp->rfe_sel_d_1 = odm_get_bb_reg(dm, R_0x5344, MASKDWORD); +#endif + /* Disable CCK and OFDM */ + odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x0); + if (!(dm->support_ic_type & ODM_RTL8814B)) { + for (start; start <= end; start++) { + /* Tx mode: RF0x00[19:16]=4'b0010 */ + odm_set_rf_reg(dm, start, RF_0x00, 0xF0000, + 0x2); + /* Lowest RF gain idx: RF_0x0[4:0] = 0 */ + odm_set_rf_reg(dm, start, RF_0x00, 0x1F, 0x0); + /* RF LO enabled */ + odm_set_rf_reg(dm, start, RF_0x58, BIT(1), + 0x1); + } + } + } else { + /* Eable CCK and OFDM */ + odm_set_bb_reg(dm, R_0x1c3c, 0x3, 0x3); + if (!(dm->support_ic_type & ODM_RTL8814B)) { + for (start; start <= end; start++) { + odm_set_rf_reg(dm, start, RF_0x00, 0xfffff, + mp->rf_reg0); + /* RF LO disabled */ + odm_set_rf_reg(dm, start, RF_0x58, BIT(1), + 0x0); + } + } +#if 0 + odm_set_bb_reg(dm, R_0x1840, MASKDWORD, mp->rfe_sel_a_0); + odm_set_bb_reg(dm, R_0x4140, MASKDWORD, mp->rfe_sel_b_0); + odm_set_bb_reg(dm, R_0x5240, MASKDWORD, mp->rfe_sel_c_0); + odm_set_bb_reg(dm, R_0x5340, MASKDWORD, mp->rfe_sel_d_0); + odm_set_bb_reg(dm, R_0x1844, MASKDWORD, mp->rfe_sel_a_1); + odm_set_bb_reg(dm, R_0x4144, MASKDWORD, mp->rfe_sel_b_1); + odm_set_bb_reg(dm, R_0x5244, MASKDWORD, mp->rfe_sel_c_1); + odm_set_bb_reg(dm, R_0x5344, MASKDWORD, mp->rfe_sel_d_1); +#endif + } +} + +void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp, + u32 rate_index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_mp *mp = &dm->dm_mp_table; + + if (is_carrier_supp) { + if (phydm_is_cck_rate(dm, (u8)rate_index)) { + /* @if CCK block on? */ + if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1))) + odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1); + + /* @Turn Off All Test mode */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0); + + /* @transmit mode */ + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); + /* @turn off scramble setting */ + odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x0); + /* @Set CCK Tx Test Rate, set FTxRate to 1Mbps */ + odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0); + } + } else { /* @Stop Carrier Suppression. */ + if (phydm_is_cck_rate(dm, (u8)rate_index)) { + /* @normal mode */ + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); + /* @turn on scramble setting */ + odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1); + /* @BB Reset */ + odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0); + odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1); + } + } +} +#endif + +void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_set_crystal_cap(dm, crystal_cap); +} + +void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path); +} + +void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp, + u32 rate_index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index); +} + +void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_mp *mp = &dm->dm_mp_table; + + if (is_single_carrier) { + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + /* @1. if OFDM block on? */ + if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0))) + odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1); + + /* @2. set CCK test mode off, set to CCK normal mode */ + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0); + + /* @3. turn on scramble setting */ + odm_set_bb_reg(dm, R_0x1a00, 0x8, 1); + + /* @4. Turn On single carrier. */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER); + } else { + /* @1. if OFDM block on? */ + if (!odm_get_bb_reg(dm, R_0x800, 0x2000000)) + odm_set_bb_reg(dm, R_0x800, 0x2000000, 1); + + /* @2. set CCK test mode off, set to CCK normal mode */ + odm_set_bb_reg(dm, R_0xa00, 0x3, 0); + + /* @3. turn on scramble setting */ + odm_set_bb_reg(dm, R_0xa00, 0x8, 1); + + /* @4. Turn On single carrier. */ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(dm, R_0x914, 0x70000, + OFDM_SINGLE_CARRIER); + else if (dm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(dm, R_0xd00, 0x70000000, + OFDM_SINGLE_CARRIER); + } + } else { /* @Stop Single Carrier. */ + /* @Turn off all test modes. */ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF); + else if (dm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(dm, R_0x914, 0x70000, OFDM_OFF); + else if (dm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(dm, R_0xd00, 0x70000000, OFDM_OFF); + /* @Delay 10 ms */ + ODM_delay_ms(10); + + /* @BB Reset */ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0); + odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1); + } else { + odm_set_bb_reg(dm, R_0x100, 0x100, 0x0); + odm_set_bb_reg(dm, R_0x100, 0x100, 0x1); + } + } +} +void phydm_mp_reset_rx_counters_phy(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0x1); + odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0x0); + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0xb58, BIT(0), 0x1); + odm_set_bb_reg(dm, R_0xb58, BIT(0), 0x0); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES){ + odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x1); + odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x0); + } +} + +void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_mp *mp = &dm->dm_mp_table; + u32 reg = 0; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + reg = R_0x2de4; + else + reg = R_0xf50; + + if (phydm_is_cck_rate(dm, (u8)rate_index)) + mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, reg, 0xffff); + else + mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, reg, 0xffff0000); +} + +void phydm_mp_get_rx_ok(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_mp *mp = &dm->dm_mp_table; + + u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0; + u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + cck_ok = odm_get_bb_reg(dm, R_0x2c04, 0xffff); + ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, 0xffff); + ht_ok = odm_get_bb_reg(dm, R_0x2c10, 0xffff); + vht_ok = odm_get_bb_reg(dm, R_0x2c0c, 0xffff); + + cck_err = odm_get_bb_reg(dm, R_0x2c04, 0xffff0000); + ofdm_err = odm_get_bb_reg(dm, R_0x2c14, 0xffff0000); + ht_err = odm_get_bb_reg(dm, R_0x2c10, 0xffff0000); + vht_err = odm_get_bb_reg(dm, R_0x2c0c, 0xffff0000); + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + cck_ok = odm_get_bb_reg(dm, R_0xf04, 0x3FFF); + ofdm_ok = odm_get_bb_reg(dm, R_0xf14, 0x3FFF); + ht_ok = odm_get_bb_reg(dm, R_0xf10, 0x3FFF); + vht_ok = odm_get_bb_reg(dm, R_0xf0c, 0x3FFF); + + cck_err = odm_get_bb_reg(dm, R_0xf04, 0x3FFF0000); + ofdm_err = odm_get_bb_reg(dm, R_0xf14, 0x3FFF0000); + ht_err = odm_get_bb_reg(dm, R_0xf10, 0x3FFF0000); + vht_err = odm_get_bb_reg(dm, R_0xf0c, 0x3FFF0000); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + cck_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD); + ofdm_ok = odm_get_bb_reg(dm, R_0xf94, 0xffff); + ht_ok = odm_get_bb_reg(dm, R_0xf90, 0xffff); + + cck_err = odm_get_bb_reg(dm, R_0xf84, MASKDWORD); + ofdm_err = odm_get_bb_reg(dm, R_0xf94, 0xffff0000); + ht_err = odm_get_bb_reg(dm, R_0xf90, 0xffff0000); + } + + mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok; + mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err; + mp->io_value = (u32)mp->rx_phy_ok_cnt; +} +#endif diff --git a/hal/phydm/phydm_mp.h b/hal/phydm/phydm_mp.h new file mode 100644 index 0000000..40088c6 --- /dev/null +++ b/hal/phydm/phydm_mp.h @@ -0,0 +1,94 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_MP_H__ +#define __PHYDM_MP_H__ + +#define MP_VERSION "1.0" + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ +struct phydm_mp { + /* @Rx OK count, statistics used in Mass Production Test.*/ + u64 tx_phy_ok_cnt; + u64 rx_phy_ok_cnt; + /* @Rx CRC32 error count, statistics used in Mass Production Test.*/ + u64 rx_phy_crc_err_cnt; + /* @The Value of IO operation is depend of MptActType.*/ + u32 io_value; + u32 rf_reg0; + /* @u32 rfe_sel_a_0;*/ + /* @u32 rfe_sel_b_0;*/ + /* @u32 rfe_sel_c_0;*/ + /* @u32 rfe_sel_d_0;*/ + /* @u32 rfe_sel_a_1;*/ + /* @u32 rfe_sel_b_1;*/ + /* @u32 rfe_sel_c_1;*/ + /* @u32 rfe_sel_d_1;*/ +}; + +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ +enum TX_MODE_OFDM { + OFDM_OFF = 0, + OFDM_CONT_TX = 1, + OFDM_SINGLE_CARRIER = 2, + OFDM_SINGLE_TONE = 4, +}; +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone, + u8 path); + +void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp, + u32 rate_index); +#endif + +void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap); + +void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path); + +void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp, + u32 rate_index); + +void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier); + +void phydm_mp_reset_rx_counters_phy(void *dm_void); + +void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index); + +void phydm_mp_get_rx_ok(void *dm_void); +#endif diff --git a/hal/phydm/phydm_noisemonitor.c b/hal/phydm/phydm_noisemonitor.c index a19cc06..aeeb255 100644 --- a/hal/phydm/phydm_noisemonitor.c +++ b/hal/phydm/phydm_noisemonitor.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,24 +8,28 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -/* ************************************************************ +/************************************************************* * include files - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" -#include "phydm_noisemonitor.h" -/* ************************************************* +/************************************************** * This function is for inband noise test utility only * To obtain the inband noise level(dbm), do the following. * 1. disable DIG and Power Saving @@ -33,260 +37,421 @@ * 3. Stop updating idle time pwer report (for driver read) * - 0x80c[25] * - * ************************************************* */ + *************************************************/ -#define VALID_MIN -35 -#define VALID_MAX 10 -#define VALID_CNT 5 +void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path) +{ + u8 i = 0; -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN)) + for (i = RF_PATH_A; i < max_rf_path; i++) { + if (noise_data->valid_cnt[i]) + noise_data->sum[i] /= noise_data->valid_cnt[i]; + else + noise_data->sum[i] = 0; + } +} -s16 odm_inband_noise_monitor_n_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_dig, u8 igi_value, u32 max_time) +#if (ODM_IC_11N_SERIES_SUPPORT) +s16 odm_inband_noise_monitor_n(struct dm_struct *dm, u8 is_pause_dig, u8 igi, + u32 max_time) { - u32 tmp4b; - u8 max_rf_path = 0, rf_path; - u8 reg_c50, reg_c58, valid_done = 0; - struct noise_level noise_data; - u64 start = 0, func_start = 0, func_end = 0; + u32 tmp4b; + u8 max_rf_path = 0, i = 0; + u8 reg_c50, reg_c58, valid_done = 0; + struct noise_level noise_data; + u64 start = 0, func_start = 0, func_end = 0; + s8 val_s8 = 0; - func_start = odm_get_current_time(p_dm_odm); - p_dm_odm->noise_level.noise_all = 0; + func_start = odm_get_current_time(dm); + dm->noise_level.noise_all = 0; - if ((p_dm_odm->rf_type == ODM_1T2R) || (p_dm_odm->rf_type == ODM_2T2R)) + if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R) max_rf_path = 2; else max_rf_path = 1; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() ==>\n")); - - odm_memory_set(p_dm_odm, &noise_data, 0, sizeof(struct noise_level)); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "odm_DebugControlInbandNoise_Nseries() ==>\n"); - /* */ + odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level)); /* step 1. Disable DIG && Set initial gain. */ - /* */ if (is_pause_dig) - odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value); - /* */ - /* step 2. Disable all power save for read registers */ - /* */ - /* dcmd_DebugControlPowerSave(p_adapter, PSDisable); */ + odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi); - /* */ /* step 3. Get noise power level */ - /* */ - start = odm_get_current_time(p_dm_odm); + start = odm_get_current_time(dm); while (1) { - /* Stop updating idle time pwer report (for driver read) */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1); + odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1); /* Read Noise Floor Report */ - tmp4b = odm_get_bb_reg(p_dm_odm, 0x8f8, MASKDWORD); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b)); - - /* odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0, TestInitialGain); */ - /* if(max_rf_path == 2) */ - /* odm_set_bb_reg(p_dm_odm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0, TestInitialGain); */ + tmp4b = odm_get_bb_reg(dm, R_0x8f8, MASKDWORD); /* update idle time pwer report per 5us */ - odm_set_bb_reg(p_dm_odm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0); + odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0); - noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b & 0xff); - noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8); + ODM_delay_us(5); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n", - noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B])); + noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff); + noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8); - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { - noise_data.sval[rf_path] = (s8)noise_data.value[rf_path]; - noise_data.sval[rf_path] /= 2; + for (i = RF_PATH_A; i < max_rf_path; i++) { + noise_data.sval[i] = (s8)noise_data.value[i]; + noise_data.sval[i] /= 2; } + for (i = RF_PATH_A; i < max_rf_path; i++) { + if (noise_data.valid_cnt[i] >= VALID_CNT) + continue; + + noise_data.valid_cnt[i]++; + noise_data.sum[i] += noise_data.sval[i]; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "rf_path:%d Valid sval=%d\n", i, + noise_data.sval[i]); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", + noise_data.sum[i]); + if (noise_data.valid_cnt[i] == VALID_CNT) + valid_done++; + } + if (valid_done == max_rf_path || + (odm_get_progressing_time(dm, start) > max_time)) { + phydm_set_noise_data_sum(&noise_data, max_rf_path); + break; + } + } + reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0); + reg_c50 &= ~BIT(7); + val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]); + dm->noise_level.noise[RF_PATH_A] = val_s8; + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("sval_a = %d, sval_b = %d\n", - noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B])); - /* ODM_delay_ms(10); */ - /* ODM_sleep_ms(10); */ + if (max_rf_path == 2) { + reg_c58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0); + reg_c58 &= ~BIT(7); + val_s8 = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]); + dm->noise_level.noise[RF_PATH_B] = val_s8; + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B]; + } + dm->noise_level.noise_all /= max_rf_path; - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { - if ((noise_data.valid_cnt[rf_path] < VALID_CNT) && (noise_data.sval[rf_path] < VALID_MAX && noise_data.sval[rf_path] >= VALID_MIN)) { - noise_data.valid_cnt[rf_path]++; - noise_data.sum[rf_path] += noise_data.sval[rf_path]; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("rf_path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path])); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", noise_data.sum[rf_path])); - if (noise_data.valid_cnt[rf_path] == VALID_CNT) { - valid_done++; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, rf_path:%d,sum = %d\n", rf_path, noise_data.sum[rf_path])); - } + PHYDM_DBG(dm, DBG_ENV_MNTR, + "noise_a = %d, noise_b = %d, noise_all = %d\n", + dm->noise_level.noise[RF_PATH_A], + dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all); - } + /* step 4. Recover the Dig */ + if (is_pause_dig) + odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi); + func_end = odm_get_progressing_time(dm, func_start); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n"); + return dm->noise_level.noise_all; +} +#endif + +#if (ODM_IC_11AC_SERIES_SUPPORT) +s16 phydm_idle_noise_measure_ac(struct dm_struct *dm, u8 pause_dig, + u8 igi, u32 max_time) +{ + u32 tmp4b; + u8 max_rf_path = 0, i = 0; + u8 reg_c50, reg_e50, valid_done = 0; + u64 start = 0, func_start = 0, func_end = 0; + struct noise_level noise_data; + s8 val_s8 = 0; + + func_start = odm_get_current_time(dm); + dm->noise_level.noise_all = 0; + + if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R) + max_rf_path = 2; + else + max_rf_path = 1; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "%s==>\n", __func__); + + odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level)); + + /*Step 1. Disable DIG && Set initial gain.*/ + + if (pause_dig) + odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi); + + /*Step 2. Get noise power level*/ + start = odm_get_current_time(dm); + + while (1) { + /*Stop updating idle time pwer report (for driver read)*/ + odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x1); + + /*Read Noise Floor Report*/ + tmp4b = odm_get_bb_reg(dm, R_0xff0, MASKDWORD); + + /*update idle time pwer report per 5us*/ + odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x0); + + ODM_delay_us(5); + + noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff); + noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8); + for (i = RF_PATH_A; i < max_rf_path; i++) { + noise_data.sval[i] = (s8)noise_data.value[i]; + noise_data.sval[i] = noise_data.sval[i] >> 1; } - /* printk("####### valid_done:%d #############\n",valid_done); */ - if ((valid_done == max_rf_path) || (odm_get_progressing_time(p_dm_odm, start) > max_time)) { - for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) { - /* printk("%s PATH_%d - sum = %d, VALID_CNT = %d\n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]); */ - if (noise_data.valid_cnt[rf_path]) - noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path]; - else - noise_data.sum[rf_path] = 0; - } + for (i = RF_PATH_A; i < max_rf_path; i++) { + if (noise_data.valid_cnt[i] >= VALID_CNT) + continue; + + noise_data.valid_cnt[i]++; + noise_data.sum[i] += noise_data.sval[i]; + PHYDM_DBG(dm, DBG_ENV_MNTR, "Path:%d Valid sval = %d\n", + i, noise_data.sval[i]); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d\n", + noise_data.sum[i]); + if (noise_data.valid_cnt[i] == VALID_CNT) + valid_done++; + } + + if (valid_done == max_rf_path || + (odm_get_progressing_time(dm, start) > max_time)) { + phydm_set_noise_data_sum(&noise_data, max_rf_path); break; } } - reg_c50 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0); + reg_c50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0); reg_c50 &= ~BIT(7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XA_AGC_CORE1, reg_c50, reg_c50)); - p_dm_odm->noise_level.noise[ODM_RF_PATH_A] = (u8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]); - p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_A]; + val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]); + dm->noise_level.noise[RF_PATH_A] = val_s8; + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A]; if (max_rf_path == 2) { - reg_c58 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0); - reg_c58 &= ~BIT(7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XB_AGC_CORE1, reg_c58, reg_c58)); - p_dm_odm->noise_level.noise[ODM_RF_PATH_B] = (u8)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]); - p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_B]; + reg_e50 = (u8)odm_get_bb_reg(dm, R_0xe50, MASKBYTE0); + reg_e50 &= ~BIT(7); + val_s8 = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]); + dm->noise_level.noise[RF_PATH_B] = val_s8; + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B]; } - p_dm_odm->noise_level.noise_all /= max_rf_path; + dm->noise_level.noise_all /= max_rf_path; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise_a = %d, noise_b = %d\n", - p_dm_odm->noise_level.noise[ODM_RF_PATH_A], - p_dm_odm->noise_level.noise[ODM_RF_PATH_B])); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "noise_a = %d, noise_b = %d, noise_all = %d\n", + dm->noise_level.noise[RF_PATH_A], + dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all); - /* */ - /* step 4. Recover the Dig */ - /* */ - if (is_pause_dig) - odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value); - func_end = odm_get_progressing_time(p_dm_odm, func_start) ; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n")); - return p_dm_odm->noise_level.noise_all; + /*Step 3. Recover the Dig*/ + if (pause_dig) + odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi); + func_end = odm_get_progressing_time(dm, func_start); + PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n"); + return dm->noise_level.noise_all; } -s16 -odm_inband_noise_monitor_ac_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_pause_dig, u8 igi_value, u32 max_time - ) +s16 odm_inband_noise_monitor_ac(struct dm_struct *dm, u8 pause_dig, u8 igi, + u32 max_time) { - s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/ - s32 value32, pwdb_A = 0, sval, noise, sum; - boolean pd_flag; - u8 i, valid_cnt; - u64 start = 0, func_start = 0, func_end = 0; - + s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/ + s32 value32, pwdb_A = 0, sval, noise, sum = 0; + boolean pd_flag; + u8 valid_cnt = 0; + u64 start = 0, func_start = 0, func_end = 0; + s32 val_s32 = 0; + s16 rpt = 0; + u8 val_u8 = 0; + + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + rpt = phydm_idle_noise_measure_ac(dm, pause_dig, igi, max_time); + return rpt; + } - if (!(p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A))) + if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A))) return 0; - func_start = odm_get_current_time(p_dm_odm); - p_dm_odm->noise_level.noise_all = 0; + func_start = odm_get_current_time(dm); + dm->noise_level.noise_all = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_inband_noise_monitor_ac_series() ==>\n")); + PHYDM_DBG(dm, DBG_ENV_MNTR, "%s ==>\n", __func__); /* step 1. Disable DIG && Set initial gain. */ - if (is_pause_dig) - odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi_value); - - /* step 2. Disable all power save for read registers */ - /*dcmd_DebugControlPowerSave(p_adapter, PSDisable); */ + if (pause_dig) + odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi); /* step 3. Get noise power level */ - start = odm_get_current_time(p_dm_odm); - - /* reset counters */ - sum = 0; - valid_cnt = 0; + start = odm_get_current_time(dm); /* step 3. Get noise power level */ while (1) { /*Set IGI=0x1C */ - odm_write_dig(p_dm_odm, 0x1C); + odm_write_dig(dm, 0x1C); /*stop CK320&CK88 */ - odm_set_bb_reg(p_dm_odm, 0x8B4, BIT(6), 1); + odm_set_bb_reg(dm, R_0x8b4, BIT(6), 1); /*Read path-A */ - odm_set_bb_reg(p_dm_odm, 0x8FC, MASKDWORD, 0x200); /*set debug port*/ - value32 = odm_get_bb_reg(p_dm_odm, 0xFA0, MASKDWORD); /*read debug port*/ - - rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/ + /*set debug port*/ + odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, 0x200); + /*read debug port*/ + value32 = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD); + /*rxi_buf_anta=RegFA0[19:10]*/ + rxi_buf_anta = (value32 & 0xFFC00) >> 10; rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/ pd_flag = (boolean)((value32 & BIT(31)) >> 31); /*Not in packet detection period or Tx state */ - if ((!pd_flag) || (rxi_buf_anta != 0x200)) { + if (!pd_flag || rxi_buf_anta != 0x200) { /*sign conversion*/ rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10); rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10); - pwdb_A = odm_pwdb_conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/ + val_s32 = rxi_buf_anta * rxi_buf_anta + + rxq_buf_anta * rxq_buf_anta; + /*S(10,9)*S(10,9)=S(20,18)*/ + pwdb_A = odm_pwdb_conversion(val_s32, 20, 18); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF)); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", + pwdb_A, rxi_buf_anta & 0x3FF, + rxq_buf_anta & 0x3FF); } /*Start CK320&CK88*/ - odm_set_bb_reg(p_dm_odm, 0x8B4, BIT(6), 0); - /*BB Reset*/ - odm_write_1byte(p_dm_odm, 0x02, odm_read_1byte(p_dm_odm, 0x02) & (~BIT(0))); - odm_write_1byte(p_dm_odm, 0x02, odm_read_1byte(p_dm_odm, 0x02) | BIT(0)); + odm_set_bb_reg(dm, R_0x8b4, BIT(6), 0); + /*@BB Reset*/ + val_u8 = odm_read_1byte(dm, 0x02) & (~BIT(0)); + odm_write_1byte(dm, 0x02, val_u8); + val_u8 = odm_read_1byte(dm, 0x02) | BIT(0); + odm_write_1byte(dm, 0x02, val_u8); /*PMAC Reset*/ - odm_write_1byte(p_dm_odm, 0xB03, odm_read_1byte(p_dm_odm, 0xB03) & (~BIT(0))); - odm_write_1byte(p_dm_odm, 0xB03, odm_read_1byte(p_dm_odm, 0xB03) | BIT(0)); - /*CCK Reset*/ - if (odm_read_1byte(p_dm_odm, 0x80B) & BIT(4)) { - odm_write_1byte(p_dm_odm, 0x80B, odm_read_1byte(p_dm_odm, 0x80B) & (~BIT(4))); - odm_write_1byte(p_dm_odm, 0x80B, odm_read_1byte(p_dm_odm, 0x80B) | BIT(4)); + val_u8 = odm_read_1byte(dm, 0xB03) & (~BIT(0)); + odm_write_1byte(dm, 0xB03, val_u8); + val_u8 = odm_read_1byte(dm, 0xB03) | BIT(0); + odm_write_1byte(dm, 0xB03, val_u8); + /*@CCK Reset*/ + if (odm_read_1byte(dm, 0x80B) & BIT(4)) { + val_u8 = odm_read_1byte(dm, 0x80B) & (~BIT(4)); + odm_write_1byte(dm, 0x80B, val_u8); + val_u8 = odm_read_1byte(dm, 0x80B) | BIT(4); + odm_write_1byte(dm, 0x80B, val_u8); } sval = pwdb_A; - if (sval < 0 && sval >= -27) { - if (valid_cnt < VALID_CNT) { - valid_cnt++; - sum += sval; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum)); - if ((valid_cnt >= VALID_CNT) || (odm_get_progressing_time(p_dm_odm, start) > max_time)) { - sum /= VALID_CNT; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum)); - break; - } + if ((sval < 0 && sval >= -27) && valid_cnt < VALID_CNT) { + valid_cnt++; + sum += sval; + PHYDM_DBG(dm, DBG_ENV_MNTR, "Valid sval = %d\n", sval); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", sum); + if (valid_cnt >= VALID_CNT || + (odm_get_progressing_time(dm, start) > max_time)) { + sum /= VALID_CNT; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "After divided, sum = %d\n", sum); + break; } } } - /*ADC backoff is 12dB,*/ + /*@ADC backoff is 12dB,*/ /*Ptarget=0x1C-110=-82dBm*/ noise = sum + 12 + 0x1C - 110; /*Offset*/ noise = noise - 3; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise)); - p_dm_odm->noise_level.noise_all = (s16)noise; + PHYDM_DBG(dm, DBG_ENV_MNTR, "noise = %d\n", noise); + dm->noise_level.noise_all = (s16)noise; /* step 4. Recover the Dig*/ - if (is_pause_dig) - odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi_value); + if (pause_dig) + odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi); - func_end = odm_get_progressing_time(p_dm_odm, func_start); + func_end = odm_get_progressing_time(dm, func_start); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_inband_noise_monitor_ac_series() <==\n")); + PHYDM_DBG(dm, DBG_ENV_MNTR, "%s <==\n", __func__); - return p_dm_odm->noise_level.noise_all; + return dm->noise_level.noise_all; } +#endif +s16 odm_inband_noise_monitor(void *dm_void, u8 pause_dig, u8 igi, + u32 max_time) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + s16 val = 0; + igi = 0x32; -s16 -odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max_time) -{ + /* since HW ability is about +15~-35, + * we fix IGI = -60 for maximum coverage + */ + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + val = odm_inband_noise_monitor_ac(dm, pause_dig, igi, max_time); + #endif - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) - return odm_inband_noise_monitor_ac_series(p_dm_odm, is_pause_dig, igi_value, max_time); - else - return odm_inband_noise_monitor_n_series(p_dm_odm, is_pause_dig, igi_value, max_time); + #if (ODM_IC_11N_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11N_SERIES) + val = odm_inband_noise_monitor_n(dm, pause_dig, igi, max_time); + #endif + + return val; } +void phydm_noisy_detection(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 total_fa_cnt, total_cca_cnt; + u32 score = 0, i, score_smooth; + + total_cca_cnt = dm->false_alm_cnt.cnt_cca_all; + total_fa_cnt = dm->false_alm_cnt.cnt_all; + +#if 0 + if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* @87.5 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* @75 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* @56.25 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* @50 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* @43.75 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* @37.5 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* @31.25% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* @25% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* @18.75% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* @12.5% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* @6.25% */ + ; #endif + for (i = 0; i <= 16; i++) { + if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) { + score = 16 - i; + break; + } + } + + /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */ + dm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) + + (score << 2); + + /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */ + if (total_cca_cnt >= 300) + score_smooth = (dm->noisy_decision_smooth + 3) >> 3; + else + score_smooth = 0; + + dm->noisy_decision = (score_smooth >= 3) ? 1 : 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\n", + total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score, + score_smooth, dm->noisy_decision); +} diff --git a/hal/phydm/phydm_noisemonitor.h b/hal/phydm/phydm_noisemonitor.h index 3dbf1e8..507285a 100644 --- a/hal/phydm/phydm_noisemonitor.h +++ b/hal/phydm/phydm_noisemonitor.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,40 +8,41 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger * *****************************************************************************/ -#ifndef __ODMNOISEMONITOR_H__ +#ifndef __ODMNOISEMONITOR_H__ #define __ODMNOISEMONITOR_H__ -#define ODM_MAX_CHANNEL_NUM 38/* 14+24 */ -struct noise_level { - /* u8 value_a, value_b; */ - u8 value[MAX_RF_PATH]; - /* s8 sval_a, sval_b; */ - s8 sval[MAX_RF_PATH]; - - /* s32 noise_a=0, noise_b=0,sum_a=0, sum_b=0; */ - /* s32 noise[ODM_RF_PATH_MAX]; */ - s32 sum[MAX_RF_PATH]; - /* u8 valid_cnt_a=0, valid_cnt_b=0, */ - u8 valid[MAX_RF_PATH]; - u8 valid_cnt[MAX_RF_PATH]; +#define VALID_CNT 5 +struct noise_level { + u8 value[PHYDM_MAX_RF_PATH]; + s8 sval[PHYDM_MAX_RF_PATH]; + s32 sum[PHYDM_MAX_RF_PATH]; + u8 valid[PHYDM_MAX_RF_PATH]; + u8 valid_cnt[PHYDM_MAX_RF_PATH]; }; - -struct _ODM_NOISE_MONITOR_ { - s8 noise[MAX_RF_PATH]; - s16 noise_all; +struct odm_noise_monitor { + s8 noise[PHYDM_MAX_RF_PATH]; + s16 noise_all; }; -s16 odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max_time); +s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value, + u32 max_time); + +void phydm_noisy_detection(void *dm_void); #endif diff --git a/hal/phydm/phydm_pathdiv.c b/hal/phydm/phydm_pathdiv.c index 91526ed..788413a 100644 --- a/hal/phydm/phydm_pathdiv.c +++ b/hal/phydm/phydm_pathdiv.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,686 +8,621 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -/* ************************************************************ +/************************************************************* * include files - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" -#if (defined(CONFIG_PATH_DIVERSITY)) +#ifdef CONFIG_PATH_DIVERSITY #if RTL8814A_SUPPORT - -void -phydm_dtp_fix_tx_path( - void *p_dm_void, - u8 path -) +void phydm_dtp_fix_tx_path( + void *dm_void, + u8 path) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; - u8 i, num_enable_path = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; + u8 i, num_enable_path = 0; - if (path == p_dm_path_div->pre_tx_path) + if (path == dm_path_div->pre_tx_path) return; else - p_dm_path_div->pre_tx_path = path; + dm_path_div->pre_tx_path = path; - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(18) | BIT(19), 3); + odm_set_bb_reg(dm, R_0x93c, BIT(18) | BIT(19), 3); for (i = 0; i < 4; i++) { if (path & BIT(i)) num_enable_path++; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" number of trun-on path : (( %d ))\n", num_enable_path)); + PHYDM_DBG(dm, DBG_PATH_DIV, " number of turn-on path : (( %d ))\n", + num_enable_path); if (num_enable_path == 1) { - odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path); - - if (path == PHYDM_A) { /* 1-1 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A ))\n")); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - } else if (path == PHYDM_B) { /* 1-2 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B ))\n")); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); - } else if (path == PHYDM_C) { /* 1-3 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C ))\n")); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 0); - - } else if (path == PHYDM_D) { /* 1-4 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( D ))\n")); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 0); + odm_set_bb_reg(dm, R_0x93c, 0xf00000, path); + + if (path == BB_PATH_A) { /* @1-1 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A ))\n"); + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + } else if (path == BB_PATH_B) { /* @1-2 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B ))\n"); + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0); + } else if (path == BB_PATH_C) { /* @1-3 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( C ))\n"); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0); + + } else if (path == BB_PATH_D) { /* @1-4 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( D ))\n"); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 0); } - } else if (num_enable_path == 2) { - odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path); - odm_set_bb_reg(p_dm_odm, 0x940, 0xf0, path); + } else if (num_enable_path == 2) { + odm_set_bb_reg(dm, R_0x93c, 0xf00000, path); + odm_set_bb_reg(dm, R_0x940, 0xf0, path); - if (path == PHYDM_AB) { /* 2-1 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B ))\n")); + if (path == (BB_PATH_AB)) { /* @2-1 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A B ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1); - } else if (path == PHYDM_AC) { /* 2-2 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C ))\n")); + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1); + } else if (path == BB_PATH_AC) { /* @2-2 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A C ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); - } else if (path == PHYDM_AD) { /* 2-3 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A D ))\n")); + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1); + } else if (path == BB_PATH_AD) { /* @2-3 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A D ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1); - } else if (path == PHYDM_BC) { /* 2-4 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C ))\n")); + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1); + } else if (path == BB_PATH_BC) { /* @2-4 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( B C ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); - } else if (path == PHYDM_BD) { /* 2-5 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B D ))\n")); + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1); + } else if (path == BB_PATH_BD) { /* @2-5 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( B D ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1); - } else if (path == PHYDM_CD) { /* 2-6 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C D ))\n")); + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1); + } else if (path == BB_PATH_CD) { /* @2-6 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( C D ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 1); + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 0); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1); } - } else if (num_enable_path == 3) { - odm_set_bb_reg(p_dm_odm, 0x93c, 0xf00000, path); - odm_set_bb_reg(p_dm_odm, 0x940, 0xf0, path); - odm_set_bb_reg(p_dm_odm, 0x940, 0xf0000, path); + } else if (num_enable_path == 3) { + odm_set_bb_reg(dm, R_0x93c, 0xf00000, path); + odm_set_bb_reg(dm, R_0x940, 0xf0, path); + odm_set_bb_reg(dm, R_0x940, 0xf0000, path); - if (path == PHYDM_ABC) { /* 3-1 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B C))\n")); + if (path == BB_PATH_ABC) { /* @3-1 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A B C))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 2); + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 2); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 2); + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1); + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 2); /* set for 3ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 2); - } else if (path == PHYDM_ABD) { /* 3-2 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B D ))\n")); + odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1); + odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 2); + } else if (path == BB_PATH_ABD) { /* @3-2 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A B D ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 1); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2); + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2); + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2); /* set for 3ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2); + odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1); + odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2); - } else if (path == PHYDM_ACD) { /* 3-3 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C D ))\n")); + } else if (path == BB_PATH_ACD) { /* @3-3 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A C D ))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(25) | BIT(24), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2); + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(9) | BIT(8), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2); + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2); /* set for 3ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(21) | BIT(20), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2); - } else if (path == PHYDM_BCD) { /* 3-4 */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C D))\n")); + odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1); + odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2); + } else if (path == BB_PATH_BCD) { /* @3-4 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( B C D))\n"); /* set for 1ss */ - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(27) | BIT(26), 0); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(29) | BIT(28), 1); - odm_set_bb_reg(p_dm_odm, 0x93c, BIT(31) | BIT(30), 2); + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2); /* set for 2ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(11) | BIT(10), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(13) | BIT(12), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(15) | BIT(14), 2); + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2); /* set for 3ss */ - odm_set_bb_reg(p_dm_odm, 0x940, BIT(23) | BIT(22), 0); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(25) | BIT(24), 1); - odm_set_bb_reg(p_dm_odm, 0x940, BIT(27) | BIT(26), 2); + odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 0); + odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1); + odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2); } - } else if (num_enable_path == 4) - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path ((A B C D))\n")); - + } else if (num_enable_path == 4) + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path ((A B C D))\n"); } -void -phydm_find_default_path( - void *p_dm_void -) +void phydm_find_default_path( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; - u32 rssi_avg_a = 0, rssi_avg_b = 0, rssi_avg_c = 0, rssi_avg_d = 0, rssi_avg_bcd = 0; - u32 rssi_total_a = 0, rssi_total_b = 0, rssi_total_c = 0, rssi_total_d = 0; - - /* 2 Default path Selection By RSSI */ - - rssi_avg_a = (p_dm_path_div->path_a_cnt_all > 0) ? (p_dm_path_div->path_a_sum_all / p_dm_path_div->path_a_cnt_all) : 0 ; - rssi_avg_b = (p_dm_path_div->path_b_cnt_all > 0) ? (p_dm_path_div->path_b_sum_all / p_dm_path_div->path_b_cnt_all) : 0 ; - rssi_avg_c = (p_dm_path_div->path_c_cnt_all > 0) ? (p_dm_path_div->path_c_sum_all / p_dm_path_div->path_c_cnt_all) : 0 ; - rssi_avg_d = (p_dm_path_div->path_d_cnt_all > 0) ? (p_dm_path_div->path_d_sum_all / p_dm_path_div->path_d_cnt_all) : 0 ; - - - p_dm_path_div->path_a_sum_all = 0; - p_dm_path_div->path_a_cnt_all = 0; - p_dm_path_div->path_b_sum_all = 0; - p_dm_path_div->path_b_cnt_all = 0; - p_dm_path_div->path_c_sum_all = 0; - p_dm_path_div->path_c_cnt_all = 0; - p_dm_path_div->path_d_sum_all = 0; - p_dm_path_div->path_d_cnt_all = 0; - - if (p_dm_path_div->use_path_a_as_default_ant == 1) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; + u32 rssi_avg_a = 0, rssi_avg_b = 0, rssi_avg_c = 0, rssi_avg_d = 0, rssi_avg_bcd = 0; + u32 rssi_total_a = 0, rssi_total_b = 0, rssi_total_c = 0, rssi_total_d = 0; + + /* @2 Default path Selection By RSSI */ + + rssi_avg_a = (dm_path_div->path_a_cnt_all > 0) ? (dm_path_div->path_a_sum_all / dm_path_div->path_a_cnt_all) : 0; + rssi_avg_b = (dm_path_div->path_b_cnt_all > 0) ? (dm_path_div->path_b_sum_all / dm_path_div->path_b_cnt_all) : 0; + rssi_avg_c = (dm_path_div->path_c_cnt_all > 0) ? (dm_path_div->path_c_sum_all / dm_path_div->path_c_cnt_all) : 0; + rssi_avg_d = (dm_path_div->path_d_cnt_all > 0) ? (dm_path_div->path_d_sum_all / dm_path_div->path_d_cnt_all) : 0; + + dm_path_div->path_a_sum_all = 0; + dm_path_div->path_a_cnt_all = 0; + dm_path_div->path_b_sum_all = 0; + dm_path_div->path_b_cnt_all = 0; + dm_path_div->path_c_sum_all = 0; + dm_path_div->path_c_cnt_all = 0; + dm_path_div->path_d_sum_all = 0; + dm_path_div->path_d_cnt_all = 0; + + if (dm_path_div->use_path_a_as_default_ant == 1) { rssi_avg_bcd = (rssi_avg_b + rssi_avg_c + rssi_avg_d) / 3; if ((rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd) { - p_dm_path_div->is_path_a_exist = true; - p_dm_path_div->default_path = PATH_A; + dm_path_div->is_path_a_exist = true; + dm_path_div->default_path = PATH_A; } else - p_dm_path_div->is_path_a_exist = false; + dm_path_div->is_path_a_exist = false; } else { - if ((rssi_avg_a >= rssi_avg_b) && (rssi_avg_a >= rssi_avg_c) && (rssi_avg_a >= rssi_avg_d)) - p_dm_path_div->default_path = PATH_A; + if (rssi_avg_a >= rssi_avg_b && rssi_avg_a >= rssi_avg_c && rssi_avg_a >= rssi_avg_d) + dm_path_div->default_path = PATH_A; else if ((rssi_avg_b >= rssi_avg_c) && (rssi_avg_b >= rssi_avg_d)) - p_dm_path_div->default_path = PATH_B; + dm_path_div->default_path = PATH_B; else if (rssi_avg_c >= rssi_avg_d) - p_dm_path_div->default_path = PATH_C; + dm_path_div->default_path = PATH_C; else - p_dm_path_div->default_path = PATH_D; + dm_path_div->default_path = PATH_D; } - - } - -void -phydm_candidate_dtp_update( - void *p_dm_void -) +void phydm_candidate_dtp_update( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; - p_dm_path_div->num_candidate = 3; + dm_path_div->num_candidate = 3; - if (p_dm_path_div->use_path_a_as_default_ant == 1) { - if (p_dm_path_div->num_tx_path == 3) { - if (p_dm_path_div->is_path_a_exist) { - p_dm_path_div->ant_candidate_1 = PHYDM_ABC; - p_dm_path_div->ant_candidate_2 = PHYDM_ABD; - p_dm_path_div->ant_candidate_3 = PHYDM_ACD; + if (dm_path_div->use_path_a_as_default_ant == 1) { + if (dm_path_div->num_tx_path == 3) { + if (dm_path_div->is_path_a_exist) { + dm_path_div->ant_candidate_1 = BB_PATH_ABC; + dm_path_div->ant_candidate_2 = BB_PATH_ABD; + dm_path_div->ant_candidate_3 = BB_PATH_ACD; } else { /* use path BCD */ - p_dm_path_div->num_candidate = 1; - phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BCD); + dm_path_div->num_candidate = 1; + phydm_dtp_fix_tx_path(dm, BB_PATH_BCD); return; } - } else if (p_dm_path_div->num_tx_path == 2) { - if (p_dm_path_div->is_path_a_exist) { - p_dm_path_div->ant_candidate_1 = PHYDM_AB; - p_dm_path_div->ant_candidate_2 = PHYDM_AC; - p_dm_path_div->ant_candidate_3 = PHYDM_AD; + } else if (dm_path_div->num_tx_path == 2) { + if (dm_path_div->is_path_a_exist) { + dm_path_div->ant_candidate_1 = BB_PATH_AB; + dm_path_div->ant_candidate_2 = BB_PATH_AC; + dm_path_div->ant_candidate_3 = BB_PATH_AD; } else { - p_dm_path_div->ant_candidate_1 = PHYDM_BC; - p_dm_path_div->ant_candidate_2 = PHYDM_BD; - p_dm_path_div->ant_candidate_3 = PHYDM_CD; + dm_path_div->ant_candidate_1 = BB_PATH_BC; + dm_path_div->ant_candidate_2 = BB_PATH_BD; + dm_path_div->ant_candidate_3 = BB_PATH_CD; } } } else { - /* 2 3 TX mode */ - if (p_dm_path_div->num_tx_path == 3) { /* choose 3 ant form 4 */ - if (p_dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */ - p_dm_path_div->ant_candidate_1 = PHYDM_ABC; - p_dm_path_div->ant_candidate_2 = PHYDM_ABD; - p_dm_path_div->ant_candidate_3 = PHYDM_ACD; - } else if (p_dm_path_div->default_path == PATH_B) { - p_dm_path_div->ant_candidate_1 = PHYDM_ABC; - p_dm_path_div->ant_candidate_2 = PHYDM_ABD; - p_dm_path_div->ant_candidate_3 = PHYDM_BCD; - } else if (p_dm_path_div->default_path == PATH_C) { - p_dm_path_div->ant_candidate_1 = PHYDM_ABC; - p_dm_path_div->ant_candidate_2 = PHYDM_ACD; - p_dm_path_div->ant_candidate_3 = PHYDM_BCD; - } else if (p_dm_path_div->default_path == PATH_D) { - p_dm_path_div->ant_candidate_1 = PHYDM_ABD; - p_dm_path_div->ant_candidate_2 = PHYDM_ACD; - p_dm_path_div->ant_candidate_3 = PHYDM_BCD; + /* @2 3 TX mode */ + if (dm_path_div->num_tx_path == 3) { /* @choose 3 ant form 4 */ + if (dm_path_div->default_path == PATH_A) { /* @choose 2 ant form 3 */ + dm_path_div->ant_candidate_1 = BB_PATH_ABC; + dm_path_div->ant_candidate_2 = BB_PATH_ABD; + dm_path_div->ant_candidate_3 = BB_PATH_ACD; + } else if (dm_path_div->default_path == PATH_B) { + dm_path_div->ant_candidate_1 = BB_PATH_ABC; + dm_path_div->ant_candidate_2 = BB_PATH_ABD; + dm_path_div->ant_candidate_3 = BB_PATH_BCD; + } else if (dm_path_div->default_path == PATH_C) { + dm_path_div->ant_candidate_1 = BB_PATH_ABC; + dm_path_div->ant_candidate_2 = BB_PATH_ACD; + dm_path_div->ant_candidate_3 = BB_PATH_BCD; + } else if (dm_path_div->default_path == PATH_D) { + dm_path_div->ant_candidate_1 = BB_PATH_ABD; + dm_path_div->ant_candidate_2 = BB_PATH_ACD; + dm_path_div->ant_candidate_3 = BB_PATH_BCD; } } - /* 2 2 TX mode */ - else if (p_dm_path_div->num_tx_path == 2) { /* choose 2 ant form 4 */ - if (p_dm_path_div->default_path == PATH_A) { /* choose 2 ant form 3 */ - p_dm_path_div->ant_candidate_1 = PHYDM_AB; - p_dm_path_div->ant_candidate_2 = PHYDM_AC; - p_dm_path_div->ant_candidate_3 = PHYDM_AD; - } else if (p_dm_path_div->default_path == PATH_B) { - p_dm_path_div->ant_candidate_1 = PHYDM_AB; - p_dm_path_div->ant_candidate_2 = PHYDM_BC; - p_dm_path_div->ant_candidate_3 = PHYDM_BD; - } else if (p_dm_path_div->default_path == PATH_C) { - p_dm_path_div->ant_candidate_1 = PHYDM_AC; - p_dm_path_div->ant_candidate_2 = PHYDM_BC; - p_dm_path_div->ant_candidate_3 = PHYDM_CD; - } else if (p_dm_path_div->default_path == PATH_D) { - p_dm_path_div->ant_candidate_1 = PHYDM_AD; - p_dm_path_div->ant_candidate_2 = PHYDM_BD; - p_dm_path_div->ant_candidate_3 = PHYDM_CD; + /* @2 2 TX mode */ + else if (dm_path_div->num_tx_path == 2) { /* @choose 2 ant form 4 */ + if (dm_path_div->default_path == PATH_A) { /* @choose 2 ant form 3 */ + dm_path_div->ant_candidate_1 = BB_PATH_AB; + dm_path_div->ant_candidate_2 = BB_PATH_AC; + dm_path_div->ant_candidate_3 = BB_PATH_AD; + } else if (dm_path_div->default_path == PATH_B) { + dm_path_div->ant_candidate_1 = BB_PATH_AB; + dm_path_div->ant_candidate_2 = BB_PATH_BC; + dm_path_div->ant_candidate_3 = BB_PATH_BD; + } else if (dm_path_div->default_path == PATH_C) { + dm_path_div->ant_candidate_1 = BB_PATH_AC; + dm_path_div->ant_candidate_2 = BB_PATH_BC; + dm_path_div->ant_candidate_3 = BB_PATH_CD; + } else if (dm_path_div->default_path == PATH_D) { + dm_path_div->ant_candidate_1 = BB_PATH_AD; + dm_path_div->ant_candidate_2 = BB_PATH_BD; + dm_path_div->ant_candidate_3 = BB_PATH_CD; } } } } - -void -phydm_dynamic_tx_path( - void *p_dm_void -) +void phydm_dynamic_tx_path( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &p_dm_odm->dm_path_div; - - struct sta_info *p_entry; - u32 i; - u8 num_client = 0; - u8 h2c_parameter[6] = {0}; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; + struct sta_info *entry; + u32 i; + u8 num_client = 0; + u8 h2c_parameter[6] = {0}; - if (!p_dm_odm->is_linked) { /* is_linked==False */ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("DTP_8814 [No Link!!!]\n")); + if (!dm->is_linked) { /* @is_linked==False */ + PHYDM_DBG(dm, DBG_PATH_DIV, "DTP_8814 [No Link!!!]\n"); - if (p_dm_path_div->is_become_linked == true) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be disconnected]----->\n")); - p_dm_path_div->is_become_linked = p_dm_odm->is_linked; + if (dm_path_div->is_become_linked == true) { + PHYDM_DBG(dm, DBG_PATH_DIV, + " [Be disconnected]----->\n"); + dm_path_div->is_become_linked = dm->is_linked; } return; } else { - if (p_dm_path_div->is_become_linked == false) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be Linked !!!]----->\n")); - p_dm_path_div->is_become_linked = p_dm_odm->is_linked; + if (dm_path_div->is_become_linked == false) { + PHYDM_DBG(dm, DBG_PATH_DIV, " [Be Linked !!!]----->\n"); + dm_path_div->is_become_linked = dm->is_linked; } } - /* 2 [period CTRL] */ - if (p_dm_path_div->dtp_period >= 2) - p_dm_path_div->dtp_period = 0; + /* @2 [period CTRL] */ + if (dm_path_div->dtp_period >= 2) + dm_path_div->dtp_period = 0; else { - /* ODM_RT_TRACE(p_dm_odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",p_dm_path_div->dtp_period)); */ - p_dm_path_div->dtp_period++; +#if 0 + /* PHYDM_DBG(dm,DBG_PATH_DIV, "Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",dm_path_div->dtp_period); */ +#endif + dm_path_div->dtp_period++; return; } - - /* 2 [Fix path] */ - if (p_dm_odm->path_select != PHYDM_AUTO_PATH) + /* @2 [Fix path] */ + if (dm->path_select != PHYDM_AUTO_PATH) return; - /* 2 [Check Bfer] */ +/* @2 [Check Bfer] */ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #if (BEAMFORMING_SUPPORT == 1) { - enum beamforming_cap beamform_cap = (p_dm_odm->beamforming_info.beamform_cap); + enum beamforming_cap beamform_cap = (dm->beamforming_info.beamform_cap); - if (beamform_cap & BEAMFORMER_CAP) { /* BFmer On && Div On->Div Off */ - if (p_dm_path_div->fix_path_bfer == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[ PathDiv : OFF ] BFmer ==1\n")); - p_dm_path_div->fix_path_bfer = 1 ; + if (beamform_cap & BEAMFORMER_CAP) { /* @BFmer On && Div On->Div Off */ + if (dm_path_div->fix_path_bfer == 0) { + PHYDM_DBG(dm, DBG_PATH_DIV, + "[ PathDiv : OFF ] BFmer ==1\n"); + dm_path_div->fix_path_bfer = 1; } return; - } else { /* BFmer Off && Div Off->Div On */ - if (p_dm_path_div->fix_path_bfer == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[ PathDiv : ON ] BFmer ==0\n")); - p_dm_path_div->fix_path_bfer = 0; + } else { /* @BFmer Off && Div Off->Div On */ + if (dm_path_div->fix_path_bfer == 1) { + PHYDM_DBG(dm, DBG_PATH_DIV, + "[ PathDiv : ON ] BFmer ==0\n"); + dm_path_div->fix_path_bfer = 0; } } } #endif #endif - if (p_dm_path_div->use_path_a_as_default_ant == 1) { - phydm_find_default_path(p_dm_odm); - phydm_candidate_dtp_update(p_dm_odm); + if (dm_path_div->use_path_a_as_default_ant == 1) { + phydm_find_default_path(dm); + phydm_candidate_dtp_update(dm); } else { - if (p_dm_path_div->phydm_dtp_state == PHYDM_DTP_INIT) { - phydm_find_default_path(p_dm_odm); - phydm_candidate_dtp_update(p_dm_odm); - p_dm_path_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1; + if (dm_path_div->phydm_dtp_state == PHYDM_DTP_INIT) { + phydm_find_default_path(dm); + phydm_candidate_dtp_update(dm); + dm_path_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1; } - else if (p_dm_path_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) { - p_dm_path_div->dtp_check_patha_counter++; + else if (dm_path_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) { + dm_path_div->dtp_check_patha_counter++; - if (p_dm_path_div->dtp_check_patha_counter >= NUM_RESET_DTP_PERIOD) { - p_dm_path_div->dtp_check_patha_counter = 0; - p_dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT; + if (dm_path_div->dtp_check_patha_counter >= NUM_RESET_DTP_PERIOD) { + dm_path_div->dtp_check_patha_counter = 0; + dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT; } - /* 2 Search space update */ +#if 0 + /* @2 Search space update */ else { - /* 1. find the worst candidate */ + /* @1. find the worst candidate */ - /* 2. repalce the worst candidate */ + /* @2. repalce the worst candidate */ } +#endif } } - /* 2 Dynamic path Selection H2C */ + /* @2 Dynamic path Selection H2C */ - if (p_dm_path_div->num_candidate == 1) + if (dm_path_div->num_candidate == 1) return; else { - h2c_parameter[0] = p_dm_path_div->num_candidate; - h2c_parameter[1] = p_dm_path_div->num_tx_path; - h2c_parameter[2] = p_dm_path_div->ant_candidate_1; - h2c_parameter[3] = p_dm_path_div->ant_candidate_2; - h2c_parameter[4] = p_dm_path_div->ant_candidate_3; + h2c_parameter[0] = dm_path_div->num_candidate; + h2c_parameter[1] = dm_path_div->num_tx_path; + h2c_parameter[2] = dm_path_div->ant_candidate_1; + h2c_parameter[3] = dm_path_div->ant_candidate_2; + h2c_parameter[4] = dm_path_div->ant_candidate_3; - odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter); + odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter); } - } - - -void -phydm_dynamic_tx_path_init( - void *p_dm_void -) +void phydm_dynamic_tx_path_init( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - u8 search_space_2[NUM_CHOOSE2_FROM4] = {PHYDM_AB, PHYDM_AC, PHYDM_AD, PHYDM_BC, PHYDM_BD, PHYDM_CD }; - u8 search_space_3[NUM_CHOOSE3_FROM4] = {PHYDM_BCD, PHYDM_ACD, PHYDM_ABD, PHYDM_ABC}; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; + void *adapter = dm->adapter; + u8 search_space_2[NUM_CHOOSE2_FROM4] = {BB_PATH_AB, BB_PATH_AC, BB_PATH_AD, BB_PATH_BC, BB_PATH_BD, BB_PATH_CD}; + u8 search_space_3[NUM_CHOOSE3_FROM4] = {BB_PATH_BCD, BB_PATH_ACD, BB_PATH_ABD, BB_PATH_ABC}; #if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT) - p_dm_path_div->is_u3_mode = (*p_dm_odm->hub_usb_mode == 2) ? 1 : 0 ; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("[WIN USB] is_u3_mode = (( %d ))\n", p_dm_path_div->is_u3_mode)); + dm_path_div->is_u3_mode = (*dm->hub_usb_mode == 2) ? 1 : 0; + PHYDM_DBG(dm, DBG_PATH_DIV, "[WIN USB] is_u3_mode = (( %d ))\n", + dm_path_div->is_u3_mode); #else - p_dm_path_div->is_u3_mode = 1; + dm_path_div->is_u3_mode = 1; #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Dynamic TX path Init 8814\n")); - - memcpy(&(p_dm_path_div->search_space_2[0]), &(search_space_2[0]), NUM_CHOOSE2_FROM4); - memcpy(&(p_dm_path_div->search_space_3[0]), &(search_space_3[0]), NUM_CHOOSE3_FROM4); + PHYDM_DBG(dm, DBG_PATH_DIV, "Dynamic TX path Init 8814\n"); - p_dm_path_div->use_path_a_as_default_ant = 1; - p_dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT; - p_dm_odm->path_select = PHYDM_AUTO_PATH; - p_dm_path_div->phydm_path_div_type = PHYDM_4R_PATH_DIV; + memcpy(&dm_path_div->search_space_2[0], &search_space_2[0], + NUM_CHOOSE2_FROM4); + memcpy(&dm_path_div->search_space_3[0], &search_space_3[0], + NUM_CHOOSE3_FROM4); + dm_path_div->use_path_a_as_default_ant = 1; + dm_path_div->phydm_dtp_state = PHYDM_DTP_INIT; + dm->path_select = PHYDM_AUTO_PATH; + dm_path_div->phydm_path_div_type = PHYDM_4R_PATH_DIV; - if (p_dm_path_div->is_u3_mode) { - p_dm_path_div->num_tx_path = 3; - phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BCD);/* 3TX Set Init TX path*/ + if (dm_path_div->is_u3_mode) { + dm_path_div->num_tx_path = 3; + phydm_dtp_fix_tx_path(dm, BB_PATH_BCD); /* @3TX Set Init TX path*/ } else { - p_dm_path_div->num_tx_path = 2; - phydm_dtp_fix_tx_path(p_dm_odm, PHYDM_BC);/* 2TX // Set Init TX path*/ + dm_path_div->num_tx_path = 2; + phydm_dtp_fix_tx_path(dm, BB_PATH_BC); /* @2TX // Set Init TX path*/ } - } - -void -phydm_process_rssi_for_path_div( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void -) +void phydm_process_rssi_for_path_div( + void *dm_void, + void *phy_info_void, + void *pkt_info_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void; - struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); - - if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_match_bssid) { - if (p_pktinfo->data_rate > ODM_RATE11M) { - if (p_dm_path_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; + + if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid)) + return; + + if (pktinfo->data_rate <= ODM_RATE11M) + return; + + if (dm_path_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) { #if RTL8814A_SUPPORT - if (p_dm_odm->support_ic_type & ODM_RTL8814A) { - p_dm_path_div->path_a_sum_all += p_phy_info->rx_mimo_signal_strength[0]; - p_dm_path_div->path_a_cnt_all++; + if (dm->support_ic_type & ODM_RTL8814A) { + dm_path_div->path_a_sum_all += phy_info->rx_mimo_signal_strength[0]; + dm_path_div->path_a_cnt_all++; - p_dm_path_div->path_b_sum_all += p_phy_info->rx_mimo_signal_strength[1]; - p_dm_path_div->path_b_cnt_all++; + dm_path_div->path_b_sum_all += phy_info->rx_mimo_signal_strength[1]; + dm_path_div->path_b_cnt_all++; - p_dm_path_div->path_c_sum_all += p_phy_info->rx_mimo_signal_strength[2]; - p_dm_path_div->path_c_cnt_all++; + dm_path_div->path_c_sum_all += phy_info->rx_mimo_signal_strength[2]; + dm_path_div->path_c_cnt_all++; - p_dm_path_div->path_d_sum_all += p_phy_info->rx_mimo_signal_strength[3]; - p_dm_path_div->path_d_cnt_all++; - } + dm_path_div->path_d_sum_all += phy_info->rx_mimo_signal_strength[3]; + dm_path_div->path_d_cnt_all++; + } #endif - } else { - p_dm_path_div->path_a_sum[p_pktinfo->station_id] += p_phy_info->rx_mimo_signal_strength[0]; - p_dm_path_div->path_a_cnt[p_pktinfo->station_id]++; + } else { + dm_path_div->path_a_sum[pktinfo->station_id] += phy_info->rx_mimo_signal_strength[0]; + dm_path_div->path_a_cnt[pktinfo->station_id]++; - p_dm_path_div->path_b_sum[p_pktinfo->station_id] += p_phy_info->rx_mimo_signal_strength[1]; - p_dm_path_div->path_b_cnt[p_pktinfo->station_id]++; - } - } + dm_path_div->path_b_sum[pktinfo->station_id] += phy_info->rx_mimo_signal_strength[1]; + dm_path_div->path_b_cnt[pktinfo->station_id]++; } - - } -#endif /* #if RTL8814A_SUPPORT */ +#endif /* @#if RTL8814A_SUPPORT */ -void -odm_pathdiv_debug( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) +void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; u32 used = *_used; u32 out_len = *_out_len; + u32 dm_value[10] = {0}; + u8 i, input_idx = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; - p_dm_odm->path_select = (dm_value[0] & 0xf); - PHYDM_SNPRINTF((output + used, out_len - used, "Path_select = (( 0x%x ))\n", p_dm_odm->path_select)); + dm->path_select = (dm_value[0] & 0xf); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Path_select = (( 0x%x ))\n", dm->path_select); - /* 2 [Fix path] */ - if (p_dm_odm->path_select != PHYDM_AUTO_PATH) { - PHYDM_SNPRINTF((output + used, out_len - used, "Trun on path [%s%s%s%s]\n", - ((p_dm_odm->path_select) & 0x1) ? "A" : "", - ((p_dm_odm->path_select) & 0x2) ? "B" : "", - ((p_dm_odm->path_select) & 0x4) ? "C" : "", - ((p_dm_odm->path_select) & 0x8) ? "D" : "")); + /* @2 [Fix path] */ + if (dm->path_select != PHYDM_AUTO_PATH) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Trun on path [%s%s%s%s]\n", + ((dm->path_select) & 0x1) ? "A" : "", + ((dm->path_select) & 0x2) ? "B" : "", + ((dm->path_select) & 0x4) ? "C" : "", + ((dm->path_select) & 0x8) ? "D" : ""); - phydm_dtp_fix_tx_path(p_dm_odm, p_dm_odm->path_select); + phydm_dtp_fix_tx_path(dm, dm->path_select); } else - PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Auto path")); -} + PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n", + "Auto path"); -#endif /* #if(defined(CONFIG_PATH_DIVERSITY)) */ + *_used = used; + *_out_len = out_len; +} -void -phydm_c2h_dtp_handler( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len -) +void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len) { -#if (defined(CONFIG_PATH_DIVERSITY)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_PATH_DIVERSITY_ *p_dm_path_div = &(p_dm_odm->dm_path_div); - - u8 macid = cmd_buf[0]; - u8 target = cmd_buf[1]; - u8 nsc_1 = cmd_buf[2]; - u8 nsc_2 = cmd_buf[3]; - u8 nsc_3 = cmd_buf[4]; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Target_candidate = (( %d ))\n", target)); - /* + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *dm_path_div = &dm->dm_path_div; + + u8 macid = cmd_buf[0]; + u8 target = cmd_buf[1]; + u8 nsc_1 = cmd_buf[2]; + u8 nsc_2 = cmd_buf[3]; + u8 nsc_3 = cmd_buf[4]; + + PHYDM_DBG(dm, DBG_PATH_DIV, "Target_candidate = (( %d ))\n", target); +/*@ if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3)) { - phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_1); + phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_1); } else if( nsc_2 >= nsc_3) { - phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_2); + phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_2); } else { - phydm_dtp_fix_tx_path(p_dm_odm, p_dm_path_div->ant_candidate_3); + phydm_dtp_fix_tx_path(dm, dm_path_div->ant_candidate_3); } */ -#endif } -void -odm_path_diversity( - void *p_dm_void -) +void odm_path_diversity(void *dm_void) { -#if (defined(CONFIG_PATH_DIVERSITY)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - if (!(p_dm_odm->support_ability & ODM_BB_PATH_DIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Return: Not Support PathDiv\n")); + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_PATH_DIV)) { + PHYDM_DBG(dm, DBG_PATH_DIV, "Return: Not Support PathDiv\n"); return; } -#if RTL8812A_SUPPORT + #if RTL8812A_SUPPORT + if (dm->support_ic_type & ODM_RTL8812) + odm_path_diversity_8812a(dm); + #endif - if (p_dm_odm->support_ic_type & ODM_RTL8812) - odm_path_diversity_8812a(p_dm_odm); - else -#endif + #if RTL8814A_SUPPORT + if (dm->support_ic_type & ODM_RTL8814A) + phydm_dynamic_tx_path(dm); + #endif -#if RTL8814A_SUPPORT - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - phydm_dynamic_tx_path(p_dm_odm); - else -#endif - {} -#endif } -void -odm_path_diversity_init( - void *p_dm_void -) +void phydm_path_diversity_init(void *dm_void) { -#if (defined(CONFIG_PATH_DIVERSITY)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - /*p_dm_odm->support_ability |= ODM_BB_PATH_DIV;*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->mp_mode == true) + if (*dm->mp_mode) return; - if (!(p_dm_odm->support_ability & ODM_BB_PATH_DIV)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Return: Not Support PathDiv\n")); + if (!(dm->support_ability & ODM_BB_PATH_DIV)) { + PHYDM_DBG(dm, DBG_PATH_DIV, "Return: Not Support PathDiv\n"); return; } -#if RTL8812A_SUPPORT - if (p_dm_odm->support_ic_type & ODM_RTL8812) - odm_path_diversity_init_8812a(p_dm_odm); - else -#endif + #if RTL8812A_SUPPORT + if (dm->support_ic_type & ODM_RTL8812) + odm_path_diversity_init_8812a(dm); + #endif -#if RTL8814A_SUPPORT - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - phydm_dynamic_tx_path_init(p_dm_odm); - else -#endif - {} -#endif + #if RTL8814A_SUPPORT + if (dm->support_ic_type & ODM_RTL8814A) + phydm_dynamic_tx_path_init(dm); + #endif } - - - -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -/* - * 2011/12/02 MH Copy from MP oursrc for temporarily test. - * */ - -void -odm_path_div_chk_ant_switch_callback( - struct timer_list *p_timer -) -{ -} - -void -odm_path_div_chk_ant_switch_workitem_callback( - void *p_context -) -{ -} - -void -odm_cck_tx_path_diversity_callback( - struct timer_list *p_timer -) -{ -} - -void -odm_cck_tx_path_diversity_work_item_callback( - void *p_context -) -{ -} -u8 -odm_sw_ant_div_select_scan_chnl( - struct _ADAPTER *adapter -) -{ - return 0; -} -void -odm_sw_ant_div_construct_scan_chnl( - struct _ADAPTER *adapter, - u8 scan_chnl -) -{ -} - -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ +#endif /* @#ifdef CONFIG_PATH_DIVERSITY */ diff --git a/hal/phydm/phydm_pathdiv.h b/hal/phydm/phydm_pathdiv.h index e21e10d..8f998b6 100644 --- a/hal/phydm/phydm_pathdiv.h +++ b/hal/phydm/phydm_pathdiv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,58 +8,43 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMPATHDIV_H__ +#define __PHYDMPATHDIV_H__ -#ifndef __PHYDMPATHDIV_H__ -#define __PHYDMPATHDIV_H__ -/*#define PATHDIV_VERSION "2.0" //2014.11.04*/ -#define PATHDIV_VERSION "3.1" /*2015.07.29 by YuChen*/ +#ifdef CONFIG_PATH_DIVERSITY +#define PATHDIV_VERSION "3.1" -#if (defined(CONFIG_PATH_DIVERSITY)) -#define USE_PATH_A_AS_DEFAULT_ANT /* for 8814 dynamic TX path selection */ +#define USE_PATH_A_AS_DEFAULT_ANT /* @for 8814 dynamic TX path selection */ -#define NUM_RESET_DTP_PERIOD 5 -#define ANT_DECT_RSSI_TH 3 +#define NUM_RESET_DTP_PERIOD 5 +#define ANT_DECT_RSSI_TH 3 #define PATH_A 1 #define PATH_B 2 #define PATH_C 3 #define PATH_D 4 -#define PHYDM_AUTO_PATH 0 -#define PHYDM_FIX_PATH 1 +#define PHYDM_AUTO_PATH 0 +#define PHYDM_FIX_PATH 1 #define NUM_CHOOSE2_FROM4 6 #define NUM_CHOOSE3_FROM4 4 - -#define PHYDM_A BIT(0) -#define PHYDM_B BIT(1) -#define PHYDM_C BIT(2) -#define PHYDM_D BIT(3) -#define PHYDM_AB (BIT(0) | BIT1) /* 0 */ -#define PHYDM_AC (BIT(0) | BIT2) /* 1 */ -#define PHYDM_AD (BIT(0) | BIT3) /* 2 */ -#define PHYDM_BC (BIT(1) | BIT2) /* 3 */ -#define PHYDM_BD (BIT(1) | BIT3) /* 4 */ -#define PHYDM_CD (BIT(2) | BIT3) /* 5 */ - -#define PHYDM_ABC (BIT(0) | BIT1 | BIT2) /* 0*/ -#define PHYDM_ABD (BIT(0) | BIT1 | BIT3) /* 1*/ -#define PHYDM_ACD (BIT(0) | BIT2 | BIT3) /* 2*/ -#define PHYDM_BCD (BIT(1) | BIT2 | BIT3) /* 3*/ - -#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3)) - - enum phydm_dtp_state { PHYDM_DTP_INIT = 1, PHYDM_DTP_RUNNING_1 @@ -71,12 +56,10 @@ enum phydm_path_div_type { PHYDM_4R_PATH_DIV = 2 }; -void -phydm_process_rssi_for_path_div( - void *p_dm_void, - void *p_phy_info_void, - void *p_pkt_info_void -); +void phydm_process_rssi_for_path_div( + void *dm_void, + void *phy_info_void, + void *pkt_info_void); struct _ODM_PATH_DIVERSITY_ { u8 resp_tx_path; @@ -115,205 +98,20 @@ struct _ODM_PATH_DIVERSITY_ { u8 pre_tx_path; u8 use_path_a_as_default_ant; - boolean is_path_a_exist; + boolean is_path_a_exist; #endif }; +void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); -#endif /* #if(defined(CONFIG_PATH_DIVERSITY)) */ - -void -phydm_c2h_dtp_handler( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len -); - -void -odm_path_diversity_init( - void *p_dm_void -); - -void -odm_path_diversity( - void *p_dm_void -); - -void -odm_pathdiv_debug( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -); - - - -/* 1 [OLD IC]-------------------------------------------------------------------------------- */ - - - - - - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - -/* #define PATHDIV_ENABLE 1 */ -#define dm_path_div_rssi_check odm_path_div_chk_per_pkt_rssi -#define path_div_check_before_link8192c odm_path_diversity_before_link92c - - - - -struct _path_div_parameter_define_ { - u32 org_5g_rege30; - u32 org_5g_regc14; - u32 org_5g_regca0; - u32 swt_5g_rege30; - u32 swt_5g_regc14; - u32 swt_5g_regca0; - /* for 2G IQK information */ - u32 org_2g_regc80; - u32 org_2g_regc4c; - u32 org_2g_regc94; - u32 org_2g_regc14; - u32 org_2g_regca0; - - u32 swt_2g_regc80; - u32 swt_2g_regc4c; - u32 swt_2g_regc94; - u32 swt_2g_regc14; - u32 swt_2g_regca0; -}; - -void -odm_path_diversity_init_92c( - struct _ADAPTER *adapter -); - -void -odm_2t_path_diversity_init_92c( - struct _ADAPTER *adapter -); - -void -odm_1t_path_diversity_init_92c( - struct _ADAPTER *adapter -); - -boolean -odm_is_connected_92c( - struct _ADAPTER *adapter -); - -boolean -odm_path_diversity_before_link92c( - /* struct _ADAPTER* adapter */ - struct PHY_DM_STRUCT *p_dm_odm -); - -void -odm_path_diversity_after_link_92c( - struct _ADAPTER *adapter -); - -void -odm_set_resp_path_92c( - struct _ADAPTER *adapter, - u8 default_resp_path -); - -void -odm_ofdm_tx_path_diversity_92c( - struct _ADAPTER *adapter -); - -void -odm_cck_tx_path_diversity_92c( - struct _ADAPTER *adapter -); - -void -odm_reset_path_diversity_92c( - struct _ADAPTER *adapter -); - -void -odm_cck_tx_path_diversity_callback( - struct timer_list *p_timer -); - -void -odm_cck_tx_path_diversity_work_item_callback( - void *p_context -); - -void -odm_path_div_chk_ant_switch_callback( - struct timer_list *p_timer -); - -void -odm_path_div_chk_ant_switch_workitem_callback( - void *p_context -); - - -void -odm_path_div_chk_ant_switch( - struct PHY_DM_STRUCT *p_dm_odm -); - -void -odm_cck_path_diversity_chk_per_pkt_rssi( - struct _ADAPTER *adapter, - boolean is_def_port, - boolean is_match_bssid, - struct _WLAN_STA *p_entry, - PRT_RFD p_rfd, - u8 *p_desc -); - -void -odm_path_div_chk_per_pkt_rssi( - struct _ADAPTER *adapter, - boolean is_def_port, - boolean is_match_bssid, - struct _WLAN_STA *p_entry, - PRT_RFD p_rfd -); - -void -odm_path_div_rest_after_link( - struct PHY_DM_STRUCT *p_dm_odm -); - -void -odm_fill_tx_path_in_txdesc( - struct _ADAPTER *adapter, - PRT_TCB p_tcb, - u8 *p_desc -); - -void -odm_path_div_init_92d( - struct PHY_DM_STRUCT *p_dm_odm -); - -u8 -odm_sw_ant_div_select_scan_chnl( - struct _ADAPTER *adapter -); +void phydm_path_diversity_init(void *dm_void); -void -odm_sw_ant_div_construct_scan_chnl( - struct _ADAPTER *adapter, - u8 scan_chnl -); +void odm_path_diversity(void *dm_void); -#endif /* #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) */ +void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif /* @#ifdef CONFIG_PATH_DIVERSITY */ +#endif /* @#ifndef __ODMPATHDIV_H__ */ -#endif /* #ifndef __ODMPATHDIV_H__ */ diff --git a/hal/phydm/phydm_phystatus.c b/hal/phydm/phydm_phystatus.c new file mode 100644 index 0000000..384c232 --- /dev/null +++ b/hal/phydm/phydm_phystatus.c @@ -0,0 +1,3089 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void phydm_rx_statistic_cal(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo) +{ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + struct phy_status_rpt_jaguar2_type1 *phy_sts = NULL; + u8 phy_status_type = 0; + u8 val = 0; +#endif + u8 is_mu_pkt = 0; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + u8 rate = (pktinfo->data_rate & 0x7f); + u8 bw_idx = phy_info->band_width; + u8 offset = 0; + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + phy_sts = (struct phy_status_rpt_jaguar2_type1 *)phy_status_inf; + phy_status_type = (*phy_status_inf & 0xf); +#endif + if (rate <= ODM_RATE54M) { + dbg_i->num_qry_legacy_pkt[rate]++; + } else if (rate <= ODM_RATEMCS31) { + dbg_i->ht_pkt_not_zero = true; + offset = rate - ODM_RATEMCS0; + + if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) { + if (bw_idx == *dm->band_width) { + dbg_i->num_qry_ht_pkt[offset]++; + + } else if (bw_idx == CHANNEL_WIDTH_20) { + dbg_i->num_qry_pkt_sc_20m[offset]++; + dbg_i->low_bw_20_occur = true; + } + } else { + dbg_i->num_qry_ht_pkt[offset]++; + } + } +#if ODM_IC_11AC_SERIES_SUPPORT + else if (rate <= ODM_RATEVHTSS4MCS9) { + offset = rate - ODM_RATEVHTSS1MCS0; + + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + if ((dm->support_ic_type & PHYSTS_2ND_TYPE_IC) && + phy_status_type == 1 && + phy_sts->gid != 0 && + phy_sts->gid != 63) { + is_mu_pkt = 1; + /*@*/ + } + #endif + + if (is_mu_pkt) { + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + dbg_i->num_mu_vht_pkt[offset]++; + #else + dbg_i->num_qry_vht_pkt[offset]++; /*@for debug*/ + #endif + } else { + dbg_i->vht_pkt_not_zero = true; + + if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) { + if (bw_idx == *dm->band_width) { + dbg_i->num_qry_vht_pkt[offset]++; + + } else if (bw_idx == CHANNEL_WIDTH_20) { + dbg_i->num_qry_pkt_sc_20m[offset]++; + dbg_i->low_bw_20_occur = true; + } else {/*@if (bw_idx == CHANNEL_WIDTH_40)*/ + dbg_i->num_qry_pkt_sc_40m[offset]++; + dbg_i->low_bw_40_occur = true; + } + } else { + dbg_i->num_qry_vht_pkt[offset]++; + } + } + + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + if (pktinfo->ppdu_cnt < 4) { + if (is_mu_pkt) + val = rate | BIT(7); + else + val = rate; + + dbg_i->num_of_ppdu[pktinfo->ppdu_cnt] = val; + dbg_i->gid_num[pktinfo->ppdu_cnt] = phy_sts->gid; + } + #endif + } +#endif +} + +void phydm_reset_phystatus_avg(struct dm_struct *dm) +{ + struct phydm_phystatus_avg *dbg_avg = NULL; + + dbg_avg = &dm->phy_dbg_info.phystatus_statistic_avg; + odm_memory_set(dm, &dbg_avg->rssi_cck_avg, 0, + sizeof(struct phydm_phystatus_avg)); +} + +void phydm_reset_phystatus_statistic(struct dm_struct *dm) +{ + struct phydm_phystatus_statistic *dbg_s = NULL; + + dbg_s = &dm->phy_dbg_info.physts_statistic_info; + + odm_memory_set(dm, &dbg_s->rssi_cck_sum, 0, + sizeof(struct phydm_phystatus_statistic)); +} + +void phydm_avg_phystatus_index(void *dm_void, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + u8 rssi[PHYSTS_PATH_NUM] = {0}; + u8 evm[PHYSTS_PATH_NUM] = {0}; + s8 snr[PHYSTS_PATH_NUM] = {0}; + u32 size = PHYSTS_PATH_NUM; /*size of path=4*/ + u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/ + u16 val = 0, intvl = 0; + u8 i = 0; + + odm_move_memory(dm, rssi, phy_info->rx_mimo_signal_strength, size); + odm_move_memory(dm, evm, phy_info->rx_mimo_evm_dbm, size); + odm_move_memory(dm, snr, phy_info->rx_snr, size); + + if (pktinfo->data_rate <= ODM_RATE11M) { + /*RSSI*/ + dbg_s->rssi_cck_sum += rssi[0]; + dbg_s->rssi_cck_cnt++; + return; + } else if (pktinfo->data_rate <= ODM_RATE54M) { + /*@evm*/ + dbg_s->evm_ofdm_sum += evm[0]; + + /*SNR*/ + dbg_s->snr_ofdm_sum += snr[0]; + + /*RSSI*/ + dbg_s->rssi_ofdm_sum += rssi[0]; + dbg_s->rssi_ofdm_cnt++; + + val = (u16)evm[0]; + intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th); + dbg_s->evm_ofdm_hist[intvl]++; + + val = (u16)snr[0]; + intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th); + dbg_s->snr_ofdm_hist[intvl]++; + + } else if (pktinfo->rate_ss == 1) { +/*@===[1-SS]==================================================================*/ + /*@evm*/ + dbg_s->evm_1ss_sum += evm[0]; + + /*SNR*/ + dbg_s->snr_1ss_sum += snr[0]; + + /*RSSI*/ + dbg_s->rssi_1ss_sum += rssi[0]; + + /*@EVM Histogram*/ + val = (u16)evm[0]; + intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th); + dbg_s->evm_1ss_hist[intvl]++; + + /*SNR Histogram*/ + val = (u16)snr[0]; + intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th); + dbg_s->snr_1ss_hist[intvl]++; + + dbg_s->rssi_1ss_cnt++; + } else if (pktinfo->rate_ss == 2) { +/*@===[2-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + for (i = 0; i < pktinfo->rate_ss; i++) { + /*@evm*/ + dbg_s->evm_2ss_sum[i] += evm[i]; + /*SNR*/ + dbg_s->snr_2ss_sum[i] += snr[i]; + /*RSSI*/ + dbg_s->rssi_2ss_sum[i] += rssi[i]; + /*@EVM Histogram*/ + val = (u16)evm[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, + size_th); + dbg_s->evm_2ss_hist[i][intvl]++; + + /*SNR Histogram*/ + val = (u16)snr[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, + size_th); + dbg_s->snr_2ss_hist[i][intvl]++; + } + dbg_s->rssi_2ss_cnt++; + #endif + } else if (pktinfo->rate_ss == 3) { +/*@===[3-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + for (i = 0; i < pktinfo->rate_ss; i++) { + /*@evm*/ + dbg_s->evm_3ss_sum[i] += evm[i]; + /*SNR*/ + dbg_s->snr_3ss_sum[i] += snr[i]; + /*RSSI*/ + dbg_s->rssi_3ss_sum[i] += rssi[i]; + /*@EVM Histogram*/ + val = (u16)evm[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, + size_th); + dbg_s->evm_3ss_hist[i][intvl]++; + + /*SNR Histogram*/ + val = (u16)snr[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, + size_th); + dbg_s->snr_3ss_hist[i][intvl]++; + } + dbg_s->rssi_3ss_cnt++; + #endif + } else if (pktinfo->rate_ss == 4) { +/*@===[4-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + for (i = 0; i < pktinfo->rate_ss; i++) { + /*@evm*/ + dbg_s->evm_4ss_sum[i] += evm[i]; + /*SNR*/ + dbg_s->snr_4ss_sum[i] += snr[i]; + /*RSSI*/ + dbg_s->rssi_4ss_sum[i] += rssi[i]; + /*@EVM Histogram*/ + val = (u16)evm[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, + size_th); + dbg_s->evm_4ss_hist[i][intvl]++; + + /*SNR Histogram*/ + val = (u16)snr[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, + size_th); + dbg_s->snr_4ss_hist[i][intvl]++; + } + dbg_s->rssi_4ss_cnt++; + #endif + } +} + +void phydm_avg_phystatus_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + u16 snr_hist_th[PHY_HIST_SIZE - 1] = {5, 8, 11, 14, 17, 20, 23, 26, + 29, 32, 35}; + u16 evm_hist_th[PHY_HIST_SIZE - 1] = {5, 8, 11, 14, 17, 20, 23, 26, + 29, 32, 35}; + u32 size = (PHY_HIST_SIZE - 1) * 2; + + odm_move_memory(dm, dbg_i->snr_hist_th, snr_hist_th, size); + odm_move_memory(dm, dbg_i->evm_hist_th, evm_hist_th, size); +} + +u8 phydm_get_signal_quality(struct phydm_phyinfo_struct *phy_info, + struct dm_struct *dm, + struct phy_status_rpt_8192cd *phy_sts) +{ + u8 sq_rpt; + u8 result = 0; + + if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test) { + result = 100; + } else { + sq_rpt = phy_sts->cck_sig_qual_ofdm_pwdb_all; + + if (sq_rpt > 64) + result = 0; + else if (sq_rpt < 20) + result = 100; + else + result = ((64 - sq_rpt) * 100) / 44; + } + + return result; +} + +u8 phydm_pwr_2_percent(s8 ant_power) +{ + if ((ant_power <= -100) || ant_power >= 20) + return 0; + else if (ant_power >= 0) + return 100; + else + return 100 + ant_power; +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#if 0 /*(DM_ODM_SUPPORT_TYPE == ODM_CE)*/ +s32 phydm_signal_scale_mapping_92c_series(struct dm_struct *dm, s32 curr_sig) +{ + s32 ret_sig = 0; + +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + if (dm->support_interface == ODM_ITRF_PCIE) { + /* step 1. Scale mapping. */ + if (curr_sig >= 61 && curr_sig <= 100) + ret_sig = 90 + ((curr_sig - 60) / 4); + else if (curr_sig >= 41 && curr_sig <= 60) + ret_sig = 78 + ((curr_sig - 40) / 2); + else if (curr_sig >= 31 && curr_sig <= 40) + ret_sig = 66 + (curr_sig - 30); + else if (curr_sig >= 21 && curr_sig <= 30) + ret_sig = 54 + (curr_sig - 20); + else if (curr_sig >= 5 && curr_sig <= 20) + ret_sig = 42 + (((curr_sig - 5) * 2) / 3); + else if (curr_sig == 4) + ret_sig = 36; + else if (curr_sig == 3) + ret_sig = 27; + else if (curr_sig == 2) + ret_sig = 18; + else if (curr_sig == 1) + ret_sig = 9; + else + ret_sig = curr_sig; + } +#endif + +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + if (dm->support_interface == ODM_ITRF_USB || + dm->support_interface == ODM_ITRF_SDIO) { + if (curr_sig >= 51 && curr_sig <= 100) + ret_sig = 100; + else if (curr_sig >= 41 && curr_sig <= 50) + ret_sig = 80 + ((curr_sig - 40) * 2); + else if (curr_sig >= 31 && curr_sig <= 40) + ret_sig = 66 + (curr_sig - 30); + else if (curr_sig >= 21 && curr_sig <= 30) + ret_sig = 54 + (curr_sig - 20); + else if (curr_sig >= 10 && curr_sig <= 20) + ret_sig = 42 + (((curr_sig - 10) * 2) / 3); + else if (curr_sig >= 5 && curr_sig <= 9) + ret_sig = 22 + (((curr_sig - 5) * 3) / 2); + else if (curr_sig >= 1 && curr_sig <= 4) + ret_sig = 6 + (((curr_sig - 1) * 3) / 2); + else + ret_sig = curr_sig; + } + +#endif + return ret_sig; +} + +s32 phydm_signal_scale_mapping(struct dm_struct *dm, s32 curr_sig) +{ +#ifdef CONFIG_SIGNAL_SCALE_MAPPING + return phydm_signal_scale_mapping_92c_series(dm, curr_sig); +#else + return curr_sig; +#endif +} +#endif + +void phydm_process_signal_strength(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo) +{ + u8 avg_rssi = 0, tmp_rssi = 0, best_rssi = 0, second_rssi = 0; + u8 ss = 0; /*signal strenth after scale mapping*/ + u8 pwdb = phy_info->rx_pwdb_all; + u8 i; + + /*use the best two RSSI only*/ + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + tmp_rssi = phy_info->rx_mimo_signal_strength[i]; + + /*@Get the best two RSSI*/ + if (tmp_rssi > best_rssi && tmp_rssi > second_rssi) { + second_rssi = best_rssi; + best_rssi = tmp_rssi; + } else if (tmp_rssi > second_rssi && tmp_rssi <= best_rssi) { + second_rssi = tmp_rssi; + } + } + + if (best_rssi == 0) + return; + + if (pktinfo->rate_ss == 1) + avg_rssi = best_rssi; + else + avg_rssi = (best_rssi + second_rssi) >> 1; + + if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) { + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + /* Update signal strength to UI, + * and phy_info->rx_pwdb_all is the maximum RSSI of all path + */ + #if 1 /*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + ss = SignalScaleProc(dm->adapter, pwdb, false, false); + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + ss = (u8)phydm_signal_scale_mapping(dm, pwdb); + #endif + + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if ODM_IC_11AC_SERIES_SUPPORT + if (pktinfo->is_cck_rate) + #if 1/*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + ss = SignalScaleProc(dm->adapter, pwdb, 0, 1); + #else + ss = (u8)phydm_signal_scale_mapping(dm, pwdb); + #endif + else + #if 1 /*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + ss = SignalScaleProc(dm->adapter, avg_rssi, 0, 1); + #else + ss = (u8)phydm_signal_scale_mapping(dm, avg_rssi); + #endif + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + #if ODM_IC_11N_SERIES_SUPPORT + if (pktinfo->is_cck_rate) + #if 1/*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + ss = SignalScaleProc(dm->adapter, pwdb, 1, 1); + #else + ss = (u8)phydm_signal_scale_mapping(dm, pwdb); + #endif + else + #if 1 /*(DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + ss = SignalScaleProc(dm->adapter, avg_rssi, 1, 0); + #else + ss = (u8)phydm_signal_scale_mapping(dm, avg_rssi); + #endif + #endif + } + phy_info->signal_strength = ss; +} +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +static u8 phydm_sq_patch_lenovo( + struct dm_struct *dm, + u8 is_cck_rate, + u8 pwdb_all, + u8 path, + u8 RSSI) +{ + u8 sq = 0; + + if (is_cck_rate) { + if (dm->support_ic_type & ODM_RTL8192E) { +/*@ + * + * Expected signal strength and bars indication at Lenovo lab. 2013.04.11 + * 802.11n, 802.11b, 802.11g only at channel 6 + * + * Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) + * 50 5 -49 + * 55 5 -49 + * 60 5 -50 + * 65 5 -51 + * 70 5 -52 + * 75 5 -54 + * 80 5 -55 + * 85 4 -60 + * 90 3 -63 + * 95 3 -65 + * 100 2 -67 + * 102 2 -67 + * 104 1 -70 + */ + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 31 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 22 && pwdb_all < 31) + sq = 40; + else if (pwdb_all >= 18 && pwdb_all < 22) + sq = 20; + else + sq = 10; + } else { + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 22 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 18 && pwdb_all < 22) + sq = 40; + else + sq = 10; + } + + } else { + /* OFDM rate */ + + if (dm->support_ic_type & ODM_RTL8192E) { + if (RSSI >= 45) + sq = 100; + else if (RSSI >= 22 && RSSI < 45) + sq = 80; + else if (RSSI >= 18 && RSSI < 22) + sq = 40; + else + sq = 20; + } else { + if (RSSI >= 45) + sq = 100; + else if (RSSI >= 22 && RSSI < 45) + sq = 80; + else if (RSSI >= 18 && RSSI < 22) + sq = 40; + else + sq = 20; + } + } + return sq; +} + +static u8 phydm_sq_patch_rt_cid_819x_acer( + struct dm_struct *dm, + u8 is_cck_rate, + u8 pwdb_all, + u8 path, + u8 RSSI) +{ + u8 sq = 0; + + if (is_cck_rate) { +#if OS_WIN_FROM_WIN8(OS_VERSION) + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 30 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 25 && pwdb_all < 30) + sq = 40; + else if (pwdb_all >= 20 && pwdb_all < 25) + sq = 20; + else + sq = 10; +#else + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 30 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 25 && pwdb_all < 30) + sq = 40; + else if (pwdb_all >= 20 && pwdb_all < 25) + sq = 20; + else + sq = 10; + + /* @Abnormal case, do not indicate the value above 20 on Win7 */ + if (pwdb_all == 0) + sq = 20; +#endif + + } else { + /* OFDM rate */ + if (dm->support_ic_type & ODM_RTL8192E) { + if (RSSI >= 45) + sq = 100; + else if (RSSI >= 22 && RSSI < 45) + sq = 80; + else if (RSSI >= 18 && RSSI < 22) + sq = 40; + else + sq = 20; + } else { + if (RSSI >= 35) + sq = 100; + else if (RSSI >= 30 && RSSI < 35) + sq = 80; + else if (RSSI >= 25 && RSSI < 30) + sq = 40; + else + sq = 20; + } + } + return sq; +} +#endif + +static u8 +phydm_evm_2_percent(s8 value) +{ + /* @-33dB~0dB to 0%~99% */ + s8 ret_val; + + ret_val = value; + ret_val /= 2; + +/*@dbg_print("value=%d\n", value);*/ +#ifdef ODM_EVM_ENHANCE_ANTDIV + if (ret_val >= 0) + ret_val = 0; + + if (ret_val <= -40) + ret_val = -40; + + ret_val = 0 - ret_val; + ret_val *= 3; +#else + if (ret_val >= 0) + ret_val = 0; + + if (ret_val <= -33) + ret_val = -33; + + ret_val = 0 - ret_val; + ret_val *= 3; + + if (ret_val == 99) + ret_val = 100; +#endif + + return (u8)ret_val; +} + +static u8 +phydm_evm_dbm(s8 value) +{ + s8 ret_val = value; + + /* @-33dB~0dB to 33dB ~ 0dB */ + if (ret_val == -128) + ret_val = 127; + else if (ret_val < 0) + ret_val = 0 - ret_val; + + ret_val = ret_val >> 1; + return (u8)ret_val; +} + +static s16 +phydm_cfo(s8 value) +{ + s16 ret_val; + + if (value < 0) { + ret_val = 0 - value; + ret_val = (ret_val << 1) + (ret_val >> 1); /*@2.5~=312.5/2^7 */ + ret_val = ret_val | BIT(12); /*set bit12 as 1 for negative cfo*/ + } else { + ret_val = value; + ret_val = (ret_val << 1) + (ret_val >> 1); /* @*2.5~=312.5/2^7*/ + } + return ret_val; +} + +s8 phydm_cck_rssi_convert(struct dm_struct *dm, u16 lna_idx, u8 vga_idx) +{ + /*@phydm_get_cck_rssi_table_from_reg*/ + return (dm->cck_lna_gain_table[lna_idx] - (vga_idx << 1)); +} + +void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm) +{ + u8 used_lna_idx_tmp; + u32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd; + u32 val = 0; + u8 i; + + /*@example: {-53, -43, -33, -27, -19, -13, -3, 1}*/ + /*@{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/ + + PHYDM_DBG(dm, ODM_COMP_INIT, "CCK LNA Gain table init\n"); + + if (!(dm->support_ic_type & (ODM_RTL8197F))) + return; + + reg_0xa80 = odm_get_bb_reg(dm, R_0xa80, 0xFFFF); + reg_0xabc = odm_get_bb_reg(dm, R_0xabc, MASKDWORD); + + PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xa80 = 0x%x\n", reg_0xa80); + PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xabc = 0x%x\n", reg_0xabc); + + for (i = 0; i <= 3; i++) { + used_lna_idx_tmp = (u8)((reg_0xa80 >> (4 * i)) & 0x7); + val = (reg_0xabc >> (8 * i)) & 0xff; + dm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)val; + } + + PHYDM_DBG(dm, ODM_COMP_INIT, + "cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\n", + dm->cck_lna_gain_table[0], dm->cck_lna_gain_table[1], + dm->cck_lna_gain_table[2], dm->cck_lna_gain_table[3], + dm->cck_lna_gain_table[4], dm->cck_lna_gain_table[5], + dm->cck_lna_gain_table[6], dm->cck_lna_gain_table[7]); +} + +s8 phydm_get_cck_rssi(void *dm_void, u8 lna_idx, u8 vga_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + s8 rx_pow = 0; + + switch (dm->support_ic_type) { + #if (RTL8197F_SUPPORT == 1) + case ODM_RTL8197F: + rx_pow = phydm_cck_rssi_convert(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8723D_SUPPORT == 1) + case ODM_RTL8723D: + rx_pow = phydm_cckrssi_8723d(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8710B_SUPPORT == 1) + case ODM_RTL8710B: + rx_pow = phydm_cckrssi_8710b(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8192F_SUPPORT == 1) + case ODM_RTL8192F: + rx_pow = phydm_cckrssi_8192f(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8821C_SUPPORT == 1) + case ODM_RTL8821C: + rx_pow = phydm_cck_rssi_8821c(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8195B_SUPPORT == 1) + case ODM_RTL8195B: + rx_pow = phydm_cck_rssi_8195B(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8188E_SUPPORT == 1) + case ODM_RTL8188E: + rx_pow = phydm_cck_rssi_8188e(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8192E_SUPPORT == 1) + case ODM_RTL8192E: + rx_pow = phydm_cck_rssi_8192e(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8723B_SUPPORT == 1) + case ODM_RTL8723B: + rx_pow = phydm_cck_rssi_8723b(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8703B_SUPPORT == 1) + case ODM_RTL8703B: + rx_pow = phydm_cck_rssi_8703b(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8188F_SUPPORT == 1) + case ODM_RTL8188F: + rx_pow = phydm_cck_rssi_8188f(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8195A_SUPPORT == 1) + case ODM_RTL8195A: + rx_pow = phydm_cck_rssi_8195a(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8812A_SUPPORT == 1) + case ODM_RTL8812: + rx_pow = phydm_cck_rssi_8812a(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) + case ODM_RTL8821: + case ODM_RTL8881A: + rx_pow = phydm_cck_rssi_8821a(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8814A_SUPPORT == 1) + case ODM_RTL8814A: + rx_pow = phydm_cck_rssi_8814a(dm, lna_idx, vga_idx); + break; + #endif + + default: + break; + } + + return rx_pow; +} + +#if (ODM_IC_11N_SERIES_SUPPORT == 1) +void phydm_phy_sts_n_parsing(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo) +{ + u8 i = 0; + s8 rx_pwr[4], rx_pwr_all = 0; + u8 EVM, pwdb_all = 0, pwdb_all_bt = 0; + u8 RSSI, total_rssi = 0; + u8 rf_rx_num = 0; + u8 lna_idx = 0; + u8 vga_idx = 0; + u8 cck_agc_rpt; + s8 evm_tmp = 0; + u8 sq = 0; + u8 val_tmp = 0; + s8 val_s8 = 0; + struct phy_status_rpt_8192cd *phy_sts = NULL; + + phy_sts = (struct phy_status_rpt_8192cd *)phy_status_inf; + + if (pktinfo->is_cck_rate) { + cck_agc_rpt = phy_sts->cck_agc_rpt_ofdm_cfosho_a; + + /*@3 bit LNA*/ + lna_idx = ((cck_agc_rpt & 0xE0) >> 5); + vga_idx = (cck_agc_rpt & 0x1F); + + #if (RTL8703B_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8703B) && + dm->cck_agc_report_type == 1) { + /*@4 bit LNA*/ + if (phy_sts->cck_rpt_b_ofdm_cfosho_b & BIT(7)) + val_tmp = 1; + else + val_tmp = 0; + lna_idx = (val_tmp << 3) | lna_idx; + } + #endif + + rx_pwr_all = phydm_get_cck_rssi(dm, lna_idx, vga_idx); + + PHYDM_DBG(dm, DBG_RSSI_MNTR, + "ext_lna_gain (( %d )), lna_idx: (( 0x%x )), vga_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n", + dm->ext_lna_gain, lna_idx, vga_idx, rx_pwr_all); + + if (dm->board_type & ODM_BOARD_EXT_LNA) + rx_pwr_all -= dm->ext_lna_gain; + + pwdb_all = phydm_pwr_2_percent(rx_pwr_all); + + if (pktinfo->is_to_self) { + dm->cck_lna_idx = lna_idx; + dm->cck_vga_idx = vga_idx; + } + + phy_info->rx_pwdb_all = pwdb_all; + phy_info->bt_rx_rssi_percentage = pwdb_all; + phy_info->recv_signal_power = rx_pwr_all; + + /* @(3) Get Signal Quality (EVM) */ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) + sq = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0); + else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER) + sq = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0); + else + #endif + sq = phydm_get_signal_quality(phy_info, dm, phy_sts); + +#if 0 + /* @dbg_print("cck sq = %d\n", sq); */ +#endif + phy_info->signal_quality = sq; + phy_info->rx_mimo_signal_quality[RF_PATH_A] = sq; + phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1; + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (i == 0) + phy_info->rx_mimo_signal_strength[0] = pwdb_all; + else + phy_info->rx_mimo_signal_strength[i] = 0; + } + } else { /* @2 is OFDM rate */ + + /* @(1)Get RSSI for HT rate */ + + for (i = RF_PATH_A; i < dm->num_rf_path; i++) { + if (dm->rf_path_rx_enable & BIT(i)) + rf_rx_num++; + + val_s8 = phy_sts->path_agc[i].gain & 0x3F; + rx_pwr[i] = (val_s8 * 2) - 110; + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = val_s8; + + phy_info->rx_pwr[i] = rx_pwr[i]; + RSSI = phydm_pwr_2_percent(rx_pwr[i]); + total_rssi += RSSI; + + phy_info->rx_mimo_signal_strength[i] = (u8)RSSI; + + /* @Get Rx snr value in DB */ + val_s8 = (s8)(phy_sts->path_rxsnr[i] / 2); + phy_info->rx_snr[i] = val_s8; + + /* Record Signal Strength for next packet */ + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (i == RF_PATH_A) { + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) { + phy_info->signal_quality = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, i, RSSI); + } else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER) + phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, RSSI); + } + #endif + } + + /* @(2)PWDB, Average PWDB calculated by hardware (for RA) */ + val_s8 = phy_sts->cck_sig_qual_ofdm_pwdb_all >> 1; + rx_pwr_all = (val_s8 & 0x7f) - 110; + + pwdb_all = phydm_pwr_2_percent(rx_pwr_all); + pwdb_all_bt = pwdb_all; + + phy_info->rx_pwdb_all = pwdb_all; + phy_info->bt_rx_rssi_percentage = pwdb_all_bt; + phy_info->rx_power = rx_pwr_all; + phy_info->recv_signal_power = rx_pwr_all; + + /* @(3)EVM of HT rate */ + for (i = 0; i < pktinfo->rate_ss; i++) { + /* @Do not use shift operation like "rx_evmX >>= 1" + * because the compilor of free build environment + * fill most significant bit to "zero" when doing shifting + * operation which may change a negative + * value to positive one, then the dbm value + * (which is supposed to be negative) is not correct anymore. + */ + EVM = phydm_evm_2_percent(phy_sts->stream_rxevm[i]); + + /*@Fill value in RFD, Get the 1st spatial stream only*/ + if (i == RF_PATH_A) + phy_info->signal_quality = (u8)(EVM & 0xff); + + phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff); + + if (phy_sts->stream_rxevm[i] < 0) + evm_tmp = 0 - phy_sts->stream_rxevm[i]; + + if (evm_tmp == 64) + evm_tmp = 0; + + phy_info->rx_mimo_evm_dbm[i] = (u8)evm_tmp; + } + phydm_parsing_cfo(dm, pktinfo, + phy_sts->path_cfotail, pktinfo->rate_ss); + } + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->ant_sel; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->ant_sel_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antsel_rx_keep_2; + #endif +} +#endif + +#if ODM_IC_11AC_SERIES_SUPPORT + +void phydm_rx_physts_bw_parsing(struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct * + pktinfo, + struct phy_status_rpt_8812 * + phy_sts) +{ + if (pktinfo->data_rate <= ODM_RATE54M) { + switch (phy_sts->r_RFMOD) { + case 1: + if (phy_sts->sub_chnl == 0) + phy_info->band_width = 1; + else + phy_info->band_width = 0; + break; + + case 2: + if (phy_sts->sub_chnl == 0) + phy_info->band_width = 2; + else if (phy_sts->sub_chnl == 9 || + phy_sts->sub_chnl == 10) + phy_info->band_width = 1; + else + phy_info->band_width = 0; + break; + + default: + case 0: + phy_info->band_width = 0; + break; + } + } +} + +void phydm_get_sq(struct dm_struct *dm, struct phydm_phyinfo_struct *phy_info, + u8 is_cck_rate) +{ + u8 sq = 0; + u8 pwdb_all = phy_info->rx_pwdb_all; /*precentage*/ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u8 rssi = phy_info->rx_mimo_signal_strength[0]; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) { + if (is_cck_rate) + sq = phydm_sq_patch_lenovo(dm, 1, pwdb_all, 0, 0); + else + sq = phydm_sq_patch_lenovo(dm, 0, pwdb_all, 0, rssi); + } else + #endif + { + if (is_cck_rate) { + if (pwdb_all > 40 && !dm->is_in_hct_test) { + sq = 100; + } else { + if (pwdb_all > 64) + sq = 0; + else if (pwdb_all < 20) + sq = 100; + else + sq = ((64 - pwdb_all) * 100) / 44; + } + } else { + sq = phy_info->rx_mimo_signal_quality[0]; + } + } + +#if 0 + /* @dbg_print("cck sq = %d\n", sq); */ +#endif + phy_info->signal_quality = sq; +} + +void phydm_rx_physts_1st_type(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo) +{ + u8 i = 0; + s8 rx_pwr_db = 0; + u8 val = 0; /*tmp value*/ + s8 val_s8 = 0; /*tmp value*/ + u8 rssi = 0; /*pre path RSSI*/ + u8 rf_rx_num = 0; + u8 lna_idx = 0, vga_idx = 0; + u8 cck_agc_rpt = 0; + struct phy_status_rpt_8812 *phy_sts = NULL; + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + #endif + + phy_sts = (struct phy_status_rpt_8812 *)phy_status_inf; + phydm_rx_physts_bw_parsing(phy_info, pktinfo, phy_sts); + + /* @== [CCK rate] ====================================================*/ + if (pktinfo->is_cck_rate) { + cck_agc_rpt = phy_sts->cfosho[0]; + lna_idx = (cck_agc_rpt & 0xE0) >> 5; + vga_idx = cck_agc_rpt & 0x1F; + + rx_pwr_db = phydm_get_cck_rssi(dm, lna_idx, vga_idx); + rssi = phydm_pwr_2_percent(rx_pwr_db); + + if (dm->support_ic_type == ODM_RTL8812 && + !dm->is_cck_high_power) { + if (rssi >= 80) { + rssi = ((rssi - 80) << 1) + + ((rssi - 80) >> 1) + 80; + } else if ((rssi <= 78) && (rssi >= 20)) { + rssi += 3; + } + } + dm->cck_lna_idx = lna_idx; + dm->cck_vga_idx = vga_idx; + + phy_info->rx_pwdb_all = rssi; + phy_info->rx_mimo_signal_strength[0] = rssi; + } else { + /* @== [OFDM rate] ===================================================*/ + for (i = RF_PATH_A; i < dm->num_rf_path; i++) { + /*@[RSSI]*/ + if (dm->rf_path_rx_enable & BIT(i)) + rf_rx_num++; + + if (i < RF_PATH_C) + val = phy_sts->gain_trsw[i]; + else + val = phy_sts->gain_trsw_cd[i - 2]; + + phy_info->rx_pwr[i] = (val & 0x7F) - 110; + rssi = phydm_pwr_2_percent(phy_info->rx_pwr[i]); + phy_info->rx_mimo_signal_strength[i] = rssi; + + /*@[SNR]*/ + if (i < RF_PATH_C) + val_s8 = phy_sts->rxsnr[i]; + else if (dm->support_ic_type & (ODM_RTL8814A)) + val_s8 = (s8)phy_sts->csi_current[i - 2]; + + phy_info->rx_snr[i] = val_s8 >> 1; + + /*@[CFO_short & CFO_tail]*/ + if (i < RF_PATH_C) { + val_s8 = phy_sts->cfosho[i]; + phy_info->cfo_short[i] = phydm_cfo(val_s8); + val_s8 = phy_sts->cfotail[i]; + phy_info->cfo_tail[i] = phydm_cfo(val_s8); + } + + if (i < RF_PATH_C && pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = phy_sts->gain_trsw[i]; + } + + /* @== [PWDB] ========================================================*/ + + /*@(Avg PWDB calculated by hardware*/ + if (!dm->is_mp_chip) /*@8812, 8821*/ + val = phy_sts->pwdb_all; + else + val = phy_sts->pwdb_all >> 1; /*old fomula*/ + + rx_pwr_db = (val & 0x7f) - 110; + phy_info->rx_pwdb_all = phydm_pwr_2_percent(rx_pwr_db); + + /*@(4)EVM of OFDM rate*/ + for (i = 0; i < pktinfo->rate_ss; i++) { + if (!pktinfo->is_cck_rate && + pktinfo->data_rate <= ODM_RATE54M) { + val_s8 = phy_sts->sigevm; + } else if (i < RF_PATH_C) { + if (phy_sts->rxevm[i] == -128) + phy_sts->rxevm[i] = -25; + + val_s8 = phy_sts->rxevm[i]; + } else { + if (phy_sts->rxevm_cd[i - 2] == -128) + phy_sts->rxevm_cd[i - 2] = -25; + + val_s8 = phy_sts->rxevm_cd[i - 2]; + } + /*@[EVM to 0~100%]*/ + val = phydm_evm_2_percent(val_s8); + phy_info->rx_mimo_signal_quality[i] = val; + /*@[EVM dBm]*/ + phy_info->rx_mimo_evm_dbm[i] = phydm_evm_dbm(val_s8); + } + phydm_parsing_cfo(dm, pktinfo, + phy_sts->cfotail, pktinfo->rate_ss); + } + + /* @== [General Info] ================================================*/ + + phy_info->rx_power = rx_pwr_db; + phy_info->bt_rx_rssi_percentage = phy_info->rx_pwdb_all; + phy_info->recv_signal_power = phy_info->rx_power; + phydm_get_sq(dm, phy_info, pktinfo->is_cck_rate); + + dm->rx_pwdb_ave = dm->rx_pwdb_ave + phy_info->rx_pwdb_all; + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + fat_tab->hw_antsw_occur = phy_sts->hw_antsw_occur; + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_anta; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_antb; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_antc; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_antd; + #endif +} + +#endif + +void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id) +{ + struct cmn_sta_info *sta; + + sta = dm->phydm_sta_info[station_id]; + + if (!is_sta_active(sta)) + return; + PHYDM_DBG(dm, DBG_RSSI_MNTR, "Reset RSSI for macid = (( %d ))\n", + station_id); + + sta->rssi_stat.rssi_cck = -1; + sta->rssi_stat.rssi_ofdm = -1; + sta->rssi_stat.rssi = -1; + sta->rssi_stat.ofdm_pkt_cnt = 0; + sta->rssi_stat.cck_pkt_cnt = 0; + sta->rssi_stat.cck_sum_power = 0; + sta->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT; + sta->rssi_stat.packet_map = 0; + sta->rssi_stat.valid_bit = 0; +} + +#if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT) + +s32 phydm_get_rssi_8814_ofdm(struct dm_struct *dm, u8 *rssi_in) +{ + s32 rssi_avg; + u8 rx_count = 0; + u32 rssi_linear = 0; + + if (dm->rx_ant_status & BB_PATH_A) { + rx_count++; + rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_A]); + } + + if (dm->rx_ant_status & BB_PATH_B) { + rx_count++; + rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_B]); + } + + if (dm->rx_ant_status & BB_PATH_C) { + rx_count++; + rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_C]); + } + + if (dm->rx_ant_status & BB_PATH_D) { + rx_count++; + rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_D]); + } + + /* @Calculate average RSSI */ + switch (rx_count) { + case 2: + rssi_linear = DIVIDED_2(rssi_linear); + break; + case 3: + rssi_linear = DIVIDED_3(rssi_linear); + break; + case 4: + rssi_linear = DIVIDED_4(rssi_linear); + break; + } + rssi_avg = odm_convert_to_db(rssi_linear); + + return rssi_avg; +} + +void phydm_process_rssi_for_dm(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo) +{ + s32 rssi_ave = 0; /*@average among all paths*/ + s8 rssi_all = 0; /*@average value of CCK & OFDM*/ + s8 rssi_cck_tmp = 0, rssi_ofdm_tmp = 0; + u8 i = 0; + u8 rssi_max = 0, rssi_min = 0; + u32 w1 = 0, w2 = 0; /*weighting*/ + u8 send_rssi_2_fw = 0; + u8 *rssi_tmp = NULL; + u8 val_tmp = 0; + struct cmn_sta_info *sta = NULL; + struct rssi_info *rssi_t = NULL; + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + #endif + #endif + + if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(dm, phy_info, pktinfo); + #endif + + sta = dm->phydm_sta_info[pktinfo->station_id]; + + if (!is_sta_active(sta)) + return; + + rssi_t = &sta->rssi_stat; + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if ((dm->support_ability & ODM_BB_ANT_DIV) && + fat_tab->enable_ctrl_frame_antdiv) { + if (pktinfo->is_packet_match_bssid) + dm->data_frame_num++; + + if (fat_tab->use_ctrl_frame_antdiv) { + if (!pktinfo->is_to_self) /*@data frame + CTRL frame*/ + return; + } else { + /*@data frame only*/ + if (!pktinfo->is_packet_match_bssid) + return; + } + } else + #endif + #endif + { + if (!pktinfo->is_packet_match_bssid) /*@data frame only*/ + return; + } + + if (pktinfo->is_packet_beacon) { + dm->phy_dbg_info.num_qry_beacon_pkt++; + dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate; + } + + /* @--------------Statistic for antenna/path diversity--------------- */ + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + if (dm->support_ability & ODM_BB_ANT_DIV) + odm_process_rssi_for_ant_div(dm, phy_info, pktinfo); + #endif + + #if (defined(CONFIG_PATH_DIVERSITY)) + if (dm->support_ability & ODM_BB_PATH_DIV) + phydm_process_rssi_for_path_div(dm, phy_info, pktinfo); + #endif + /* @----------------------------------------------------------------- */ + + rssi_cck_tmp = rssi_t->rssi_cck; + rssi_ofdm_tmp = rssi_t->rssi_ofdm; + rssi_all = rssi_t->rssi; + + if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_beacon)) + return; + + if (!pktinfo->is_cck_rate) { +/* @=== [ofdm RSSI] ======================================================== */ + rssi_tmp = phy_info->rx_mimo_signal_strength; + + #if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8814A)) { + rssi_ave = phydm_get_rssi_8814_ofdm(dm, rssi_tmp); + } else + #endif + { + if (rssi_tmp[RF_PATH_B] == 0) { + rssi_ave = rssi_tmp[RF_PATH_A]; + } else { + if (rssi_tmp[RF_PATH_A] > rssi_tmp[RF_PATH_B]) { + rssi_max = rssi_tmp[RF_PATH_A]; + rssi_min = rssi_tmp[RF_PATH_B]; + } else { + rssi_max = rssi_tmp[RF_PATH_B]; + rssi_min = rssi_tmp[RF_PATH_A]; + } + if ((rssi_max - rssi_min) < 3) + rssi_ave = rssi_max; + else if ((rssi_max - rssi_min) < 6) + rssi_ave = rssi_max - 1; + else if ((rssi_max - rssi_min) < 10) + rssi_ave = rssi_max - 2; + else + rssi_ave = rssi_max - 3; + } + } + + /* OFDM MA RSSI */ + if (rssi_ofdm_tmp <= 0) { /* @initialize */ + rssi_ofdm_tmp = (s8)phy_info->rx_pwdb_all; + } else { + rssi_ofdm_tmp = (s8)WEIGHTING_AVG(rssi_ofdm_tmp, + RX_SMOOTH_FACTOR - 1, + rssi_ave, 1); + if (phy_info->rx_pwdb_all > (u32)rssi_ofdm_tmp) + rssi_ofdm_tmp++; + } + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_ofdm=%d\n", rssi_ofdm_tmp); + + if (rssi_t->ofdm_pkt_cnt != 64) { + i = 63; + val_tmp = (u8)((rssi_t->packet_map >> i) & BIT(0)); + rssi_t->ofdm_pkt_cnt -= val_tmp - 1; + } + rssi_t->packet_map = (rssi_t->packet_map << 1) | BIT(0); + + } else { +/* @=== [cck RSSI] ========================================================= */ + rssi_ave = phy_info->rx_pwdb_all; + + if (rssi_t->cck_pkt_cnt <= 63) + rssi_t->cck_pkt_cnt++; + + /* @1 Process CCK RSSI */ + if (rssi_cck_tmp <= 0) { /* @initialize */ + rssi_cck_tmp = (s8)phy_info->rx_pwdb_all; + rssi_t->cck_sum_power = (u16)phy_info->rx_pwdb_all; + rssi_t->cck_pkt_cnt = 1; /*reset*/ + PHYDM_DBG(dm, DBG_RSSI_MNTR, "[1]CCK_INIT\n"); + } else if (rssi_t->cck_pkt_cnt <= CCK_RSSI_INIT_COUNT) { + rssi_t->cck_sum_power = rssi_t->cck_sum_power + + (u16)phy_info->rx_pwdb_all; + + rssi_cck_tmp = rssi_t->cck_sum_power / + rssi_t->cck_pkt_cnt; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, + "[2]SumPow=%d, cck_pkt=%d\n", + rssi_t->cck_sum_power, rssi_t->cck_pkt_cnt); + } else { + rssi_cck_tmp = (s8)WEIGHTING_AVG(rssi_cck_tmp, + RX_SMOOTH_FACTOR - 1, + phy_info->rx_pwdb_all, + 1); + if (phy_info->rx_pwdb_all > (u32)rssi_cck_tmp) + rssi_cck_tmp++; + } + PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_cck=%d\n", rssi_cck_tmp); + i = 63; + val_tmp = (u8)((rssi_t->packet_map >> i) & BIT(0)); + rssi_t->ofdm_pkt_cnt -= val_tmp; + rssi_t->packet_map = rssi_t->packet_map << 1; + } +/* @=== [ofdm + cck weighting RSSI] ========================================= */ + if (rssi_t->ofdm_pkt_cnt == 64) { + rssi_all = rssi_ofdm_tmp; + } else { + if (rssi_t->valid_bit < 64) + rssi_t->valid_bit++; + + if (rssi_t->valid_bit == 64) { + if (rssi_t->ofdm_pkt_cnt > 4) + w1 = 64; + else + w1 = (u32)(rssi_t->ofdm_pkt_cnt << 4); + + w2 = 64 - w1; + + rssi_all = (s8)((w1 * (u32)rssi_ofdm_tmp + + w2 * (u32)rssi_cck_tmp) >> 6); + } else if (rssi_t->valid_bit != 0) { /*@(valid_bit > 64)*/ + w1 = (u32)rssi_t->ofdm_pkt_cnt; + w2 = (u32)(rssi_t->valid_bit - rssi_t->ofdm_pkt_cnt); + rssi_all = (s8)WEIGHTING_AVG((u32)rssi_ofdm_tmp, w1, + (u32)rssi_cck_tmp, w2); + } else { + rssi_all = 0; + } + } + PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi=%d,w1=%d,w2=%d\n", rssi_all, w1, w2); + + if ((rssi_t->ofdm_pkt_cnt >= 1 || rssi_t->cck_pkt_cnt >= 5) && + rssi_t->is_send_rssi == RA_RSSI_STATE_INIT) { + send_rssi_2_fw = 1; + rssi_t->is_send_rssi = RA_RSSI_STATE_SEND; + } + + rssi_t->rssi_cck = rssi_cck_tmp; + rssi_t->rssi_ofdm = rssi_ofdm_tmp; + rssi_t->rssi = rssi_all; + + if (send_rssi_2_fw) { /* Trigger init rate by RSSI */ + if (rssi_t->ofdm_pkt_cnt != 0) + rssi_t->rssi = rssi_ofdm_tmp; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, + "[Send to FW] PWDB=%d, ofdm_pkt=%d, cck_pkt=%d\n", + rssi_all, rssi_t->ofdm_pkt_cnt, rssi_t->cck_pkt_cnt); + } + +#if 0 + /* @dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt_cnt, weighting);*/ + /* @dbg_print("rssi_ofdm_tmp=%d, rssi_all=%d, rssi_cck_tmp=%d\n", */ + /* rssi_ofdm_tmp, rssi_all, rssi_cck_tmp); */ +#endif +} +#endif + +#ifdef PHYSTS_3RD_TYPE_SUPPORT +void phydm_print_phystat_jaguar3(struct dm_struct *dm, u8 *phy_sts, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct phy_status_rpt_jaguar3_type0 *rpt0 = NULL; + struct phy_status_rpt_jaguar3_type1 *rpt1 = NULL; + struct phy_status_rpt_jaguar3_type2_type3 *rpt2 = NULL; + struct phy_status_rpt_jaguar3_type4 *rpt3 = NULL; + struct phy_status_rpt_jaguar3_type5 *rpt4 = NULL; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + u8 phy_status_page_num = (*phy_sts & 0xf); + u32 phy_status_tmp[PHY_STATUS_JRGUAR3_DW_LEN] = {0}; + u8 i; + u32 size = PHY_STATUS_JRGUAR3_DW_LEN << 2; + + rpt0 = (struct phy_status_rpt_jaguar3_type0 *)phy_sts; + rpt1 = (struct phy_status_rpt_jaguar3_type1 *)phy_sts; + rpt2 = (struct phy_status_rpt_jaguar3_type2_type3 *)phy_sts; + rpt3 = (struct phy_status_rpt_jaguar3_type4 *)phy_sts; + rpt4 = (struct phy_status_rpt_jaguar3_type5 *)phy_sts; + + odm_move_memory(dm, phy_status_tmp, phy_sts, size); + if (!(dm->debug_components & DBG_PHY_STATUS)) + return; + + if (dbg->show_phy_sts_all_pkt == 0) { + if (!pktinfo->is_packet_match_bssid) + return; + } + + dbg->show_phy_sts_cnt++; + + if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) { + if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt) + return; + } + + pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num); + pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d\n", + pktinfo->station_id, pktinfo->data_rate, + pktinfo->is_packet_match_bssid); + + for (i = 0; i < PHY_STATUS_JRGUAR3_DW_LEN; i++) + pr_debug("Offset[%d:%d] = 0x%x\n", + ((4 * i) + 3), (4 * i), phy_status_tmp[i]); + + if (phy_status_page_num == 0) { /* @CCK(default) */ + pr_debug("[0] Pkt_cnt=%d, Channel_msb=%d, Pwdb_a=%d, Gain_a=%d, TRSW=%d, AGC_table_b=%d, AGC_table_c=%d,\n", + rpt0->pkt_cnt, rpt0->channel_msb, rpt0->pwdb_a, + rpt0->gain_a, rpt0->trsw, rpt0->agc_table_b, + rpt0->agc_table_c); + pr_debug("[4] Path_Sel_o=%d, Gnt_BT_keep_cnt=%d, HW_AntSW_occur_keep_cck=%d,\n Band=%d, Channel=%d, AGC_table_a=%d, l_RXSC=%d, AGC_table_d=%d\n", + rpt0->path_sel_o, rpt0->gnt_bt_keep_cck, + rpt0->hw_antsw_occur_keep_cck, rpt0->band, + rpt0->channel, rpt0->agc_table_a, rpt0->l_rxsc, + rpt0->agc_table_d); + pr_debug("[8] AntIdx={%d, %d, %d, %d}, Length=%d\n", + rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b, + rpt0->antidx_a, rpt0->length); + pr_debug("[12] MF_off=%d, SQloss=%d, lockbit=%d, raterr=%d, rxrate=%d, lna_h_a=%d, CCK_BB_power_a=%d, lna_l_a=%d, vga_a=%d, sq=%d\n", + rpt0->mf_off, rpt0->sqloss, rpt0->lockbit, + rpt0->raterr, rpt0->rxrate, rpt0->lna_h_a, + rpt0->bb_power_a, rpt0->lna_l_a, rpt0->vga_a, + rpt0->signal_quality); + pr_debug("[16] Gain_b=%d, lna_h_b=%d, CCK_BB_power_b=%d, lna_l_b=%d, vga_b=%d, Pwdb_b=%d\n", + rpt0->gain_b, rpt0->lna_h_b, rpt0->bb_power_b, + rpt0->lna_l_b, rpt0->vga_b, rpt0->pwdb_b); + pr_debug("[20] Gain_c=%d, lna_h_c=%d, CCK_BB_power_c=%d, lna_l_c=%d, vga_c=%d, Pwdb_c=%d\n", + rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c, + rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c); + pr_debug("[24] Gain_d=%d, lna_h_d=%d, CCK_BB_power_d=%d, lna_l_d=%d, vga_d=%d, Pwdb_d=%d\n", + rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c, + rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c); + } else if (phy_status_page_num == 1) { + pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_pri_msb=%d, Pkt_cnt=%d,\n", + rpt1->pwdb_c, rpt1->pwdb_b, rpt1->pwdb_a, + rpt1->channel_pri_msb, rpt1->pkt_cnt); + pr_debug("[4] BF: %d, stbc=%d, ldpc=%d, gnt_bt=%d, band=%d, Ch_pri_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb[D]=%d\n", + rpt1->beamformed, rpt1->stbc, rpt1->ldpc, rpt1->gnt_bt, + rpt1->band, rpt1->channel_pri_lsb, rpt1->ht_rxsc, + rpt1->l_rxsc, rpt1->pwdb_d); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d,%d}, Channel_sec[msb,lsb]={%d, %d}\n", + rpt1->antidx_d, rpt1->antidx_c, + rpt1->antidx_b, rpt1->antidx_a, + rpt1->hw_antsw_occur_d, rpt1->hw_antsw_occur_c, + rpt1->hw_antsw_occur_b, rpt1->hw_antsw_occur_a, + rpt1->channel_sec_msb, rpt1->channel_sec_lsb); + pr_debug("[12] GID=%d, PAID[msb,lsb]={%d,%d}\n", + rpt1->gid, rpt1->paid_msb, rpt1->paid); + pr_debug("[16] RX_EVM[D:A]={%d, %d, %d, %d}\n", + rpt1->rxevm[3], rpt1->rxevm[2], + rpt1->rxevm[1], rpt1->rxevm[0]); + pr_debug("[20] CFO_tail[D:A]={%d, %d, %d, %d}\n", + rpt1->cfo_tail[3], rpt1->cfo_tail[2], + rpt1->cfo_tail[1], rpt1->cfo_tail[0]); + pr_debug("[24] RX_SNR[D:A]={%d, %d, %d, %d}\n\n", + rpt1->rxsnr[3], rpt1->rxsnr[2], + rpt1->rxsnr[1], rpt1->rxsnr[0]); + } else if (phy_status_page_num == 2 || phy_status_page_num == 3) { + pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n", + rpt2->pwdb[2], rpt2->pwdb[1], rpt2->pwdb[0], + rpt2->channel_msb, rpt2->pkt_cnt); + pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, Gnt_BT=%d, band=%d, CH_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n", + rpt2->beamformed, rpt2->stbc, rpt2->ldpc, rpt2->gnt_bt, + rpt2->band, rpt2->channel_lsb, + rpt2->ht_rxsc, rpt2->l_rxsc, rpt2->pwdb[3]); + pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, pwed_th=%d, shift_l_map=%d\n", + rpt2->agc_table_d, rpt2->agc_table_c, + rpt2->agc_table_b, rpt2->agc_table_a, + rpt2->pwed_th, rpt2->shift_l_map); + pr_debug("[12] AvgNoisePowerdB=%d, mp_gain_c[msb, lsb]={%d, %d}, mp_gain_b[msb, lsb]={%d, %d}, mp_gain_a=%d, cnt_cca2agc_rdy=%d\n", + rpt2->avg_noise_pwr_lsb, rpt2->mp_gain_c_msb, + rpt2->mp_gain_c_lsb, rpt2->mp_gain_b_msb, + rpt2->mp_gain_b_lsb, rpt2->mp_gain_a, + rpt2->cnt_cca2agc_rdy); + pr_debug("[16] HT AAGC gain[B:A]={%d, %d}, AAGC step[D:A]={%d, %d, %d, %d}, IsFreqSelectFadimg=%d, mp_gain_d=%d\n", + rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0], + rpt2->aagc_step_d, rpt2->aagc_step_c, + rpt2->aagc_step_b, rpt2->aagc_step_a, + rpt2->is_freq_select_fading, rpt2->mp_gain_d); + pr_debug("[20] DAGC gain ant[B:A]={%d, %d}, HT AAGC gain[D:C]={%d, %d}\n", + rpt2->dagc_gain[1], rpt2->dagc_gain[0], + rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2]); + pr_debug("[24] AvgNoisePwerdB=%d, syn_count[msb, lsb]={%d, %d}, counter=%d, DAGC gain ant[D:C]={%d, %d}\n", + rpt2->avg_noise_pwr_msb, rpt2->syn_count_msb, + rpt2->syn_count_lsb, rpt2->counter, + rpt2->dagc_gain[3], rpt2->dagc_gain[2]); + } else if (phy_status_page_num == 4) { /*type 4*/ + pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n", + rpt3->pwdb[2], rpt3->pwdb[1], rpt3->pwdb[0], + rpt3->channel_msb, rpt3->pkt_cnt); + pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n", + rpt3->beamformed, rpt3->stbc, rpt3->ldpc, rpt3->gnt_bt, + rpt3->band, rpt3->channel_lsb, rpt3->ht_rxsc, + rpt3->l_rxsc, rpt3->pwdb[3]); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Training_done[D:A]={%d, %d, %d, %d},\n BadToneCnt_CN_excess_0=%d, BadToneCnt_min_eign_0=%d\n", + rpt3->antidx_d, rpt3->antidx_c, + rpt3->antidx_b, rpt3->antidx_a, + rpt3->hw_antsw_occur_d, rpt3->hw_antsw_occur_c, + rpt3->hw_antsw_occur_b, rpt3->hw_antsw_occur_a, + rpt3->training_done_d, rpt3->training_done_c, + rpt3->training_done_b, rpt3->training_done_a, + rpt3->bad_tone_cnt_cn_excess_0, + rpt3->bad_tone_cnt_min_eign_0); + pr_debug("[12] avg_cond_num_1_msb=%d, avg_cond_num_1_lsb=%d, avg_cond_num_0=%d, bad_tone_cnt_cn_excess_1=%d, bad_tone_cnt_min_eign_1=%d, Tx_pkt_cnt=%d\n", + rpt3->avg_cond_num_1_msb, rpt3->avg_cond_num_1_lsb, + rpt3->avg_cond_num_0, rpt3->bad_tone_cnt_cn_excess_1, + rpt3->bad_tone_cnt_min_eign_1, rpt3->tx_pkt_cnt); + pr_debug("[16] Stream RXEVM[D:A]={%d, %d, %d, %d}\n", + rpt3->rxevm[3], rpt3->rxevm[2], + rpt3->rxevm[1], rpt3->rxevm[0]); + pr_debug("[20] Eigenvalue[D:A]={%d, %d, %d, %d}\n", + rpt3->eigenvalue[3], rpt3->eigenvalue[2], + rpt3->eigenvalue[1], rpt3->eigenvalue[0]); + pr_debug("[24] RX SNR[D:A]={%d, %d, %d, %d}\n", + rpt3->rxsnr[3], rpt3->rxsnr[2], + rpt3->rxsnr[1], rpt3->rxsnr[0]); + } else if (phy_status_page_num == 5) { /*type 5*/ + pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n", + rpt4->pwdb[2], rpt4->pwdb[1], rpt4->pwdb[0], + rpt4->channel_msb, rpt4->pkt_cnt); + pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n", + rpt4->beamformed, rpt4->stbc, rpt4->ldpc, rpt4->gnt_bt, + rpt4->band, rpt4->channel_lsb, rpt4->ht_rxsc, + rpt4->l_rxsc, rpt4->pwdb[3]); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}\n", + rpt4->antidx_d, rpt4->antidx_c, + rpt4->antidx_b, rpt4->antidx_a, + rpt4->hw_antsw_occur_d, rpt4->hw_antsw_occur_c, + rpt4->hw_antsw_occur_b, rpt4->hw_antsw_occur_a); + pr_debug("[12] Inf_posD[1,0]={%d, %d}, Inf_posC[1,0]={%d, %d}, Inf_posB[1,0]={%d, %d}, Inf_posA[1,0]={%d, %d}, Tx_pkt_cnt=%d\n", + rpt4->inf_pos_1_D_flg, rpt4->inf_pos_0_D_flg, + rpt4->inf_pos_1_C_flg, rpt4->inf_pos_0_C_flg, + rpt4->inf_pos_1_B_flg, rpt4->inf_pos_0_B_flg, + rpt4->inf_pos_1_A_flg, rpt4->inf_pos_0_A_flg, + rpt4->tx_pkt_cnt); + pr_debug("[16] Inf_pos_B[1,0]={%d, %d}, Inf_pos_A[1,0]={%d, %d}\n", + rpt4->inf_pos_1_b, rpt4->inf_pos_0_b, + rpt4->inf_pos_1_a, rpt4->inf_pos_0_a); + pr_debug("[20] Inf_pos_D[1,0]={%d, %d}, Inf_pos_C[1,0]={%d, %d}\n", + rpt4->inf_pos_1_d, rpt4->inf_pos_0_d, + rpt4->inf_pos_1_c, rpt4->inf_pos_0_c); + } +} + +void phydm_reset_phy_info_3rd(struct dm_struct *phydm, + struct phydm_phyinfo_struct *phy_info) +{ + phy_info->rx_pwdb_all = 0; + phy_info->signal_quality = 0; + phy_info->band_width = 0; + phy_info->rx_count = 0; + odm_memory_set(phydm, phy_info->rx_mimo_signal_quality, 0, 4); + odm_memory_set(phydm, phy_info->rx_mimo_signal_strength, 0, 4); + odm_memory_set(phydm, phy_info->rx_snr, 0, 4); + + phy_info->rx_power = -110; + phy_info->recv_signal_power = -110; + phy_info->bt_rx_rssi_percentage = 0; + phy_info->signal_strength = 0; + phy_info->channel = 0; + phy_info->is_mu_packet = 0; + phy_info->is_beamformed = 0; + phy_info->rxsc = 0; + odm_memory_set(phydm, phy_info->rx_pwr, -110, 4); + odm_memory_set(phydm, phy_info->cfo_short, 0, 8); + odm_memory_set(phydm, phy_info->cfo_tail, 0, 8); + + odm_memory_set(phydm, phy_info->rx_mimo_evm_dbm, 0, 4); +} + +phydm_per_path_info_3rd(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail, s8 rx_snr, + struct phydm_phyinfo_struct *phy_info) +{ + u8 evm_dbm = 0; + u8 evm_percentage = 0; + + /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ + + if (rx_evm < 0) { + /* @Calculate EVM in dBm */ + evm_dbm = ((u8)(0 - rx_evm) >> 1); + + if (evm_dbm == 64) + evm_dbm = 0; /*@if 1SS rate, evm_dbm [2nd stream] =64*/ + + if (evm_dbm != 0) { + /* @Convert EVM to 0%~100% percentage */ + if (evm_dbm >= 34) + evm_percentage = 100; + else + evm_percentage = (evm_dbm << 1) + (evm_dbm); + } + } + + phy_info->rx_pwr[rx_path] = pwr; + + /*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/ + phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1; + phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm; + phy_info->rx_mimo_signal_strength[rx_path] = phydm_pwr_2_percent(pwr); + phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage; + phy_info->rx_snr[rx_path] = rx_snr >> 1; +} + +void phydm_common_phy_info_3rd(s8 rx_power, u8 channel, boolean is_beamformed, + boolean is_mu_packet, u8 bandwidth, + u8 signal_quality, u8 rxsc, + struct phydm_phyinfo_struct *phy_info) +{ + phy_info->rx_power = rx_power; /* RSSI in dB */ + phy_info->recv_signal_power = rx_power; /* RSSI in dB */ + phy_info->channel = channel; /* @channel number */ + phy_info->is_beamformed = is_beamformed; /* @apply BF */ + phy_info->is_mu_packet = is_mu_packet; /* @MU packet */ + phy_info->rxsc = rxsc; + + phy_info->rx_pwdb_all = phydm_pwr_2_percent(rx_power); /*percentage */ + phy_info->signal_quality = signal_quality; /* signal quality */ + phy_info->band_width = bandwidth; /* @bandwidth */ + +#if 0 + /* @if (pktinfo->is_packet_match_bssid) */ + { + dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", phy_info->rx_pwdb_all, phy_info->rx_power, phy_info->recv_signal_power); + dbg_print("signal_quality = %d\n", phy_info->signal_quality); + dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", phy_info->is_beamformed, phy_info->is_mu_packet, phy_info->rx_count + 1); + dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, rxsc, bandwidth); + } +#endif +} + +void phydm_get_physts_jarguar3_0(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 0 is used for cck packet */ + struct phy_status_rpt_jaguar3_type0 *phy_sts = NULL; + u8 sq = 0, i; + s8 rx_power[4]; + s8 rx_pwr_db_max = -120; + + phy_sts = (struct phy_status_rpt_jaguar3_type0 *)phy_status_inf; + + /* Setting the RX power: agc_idx -110 dBm*/ + rx_power[0] = phy_sts->pwdb_a - 110; + rx_power[1] = phy_sts->pwdb_b - 110; + rx_power[2] = phy_sts->pwdb_c - 110; + rx_power[3] = phy_sts->pwdb_d - 110; + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (rx_power[i] > rx_pwr_db_max) + rx_pwr_db_max = rx_power[0]; /*only one path*/ + } + if (pktinfo->is_to_self) { + dm->ofdm_agc_idx[0] = phy_sts->pwdb_a; + dm->ofdm_agc_idx[1] = phy_sts->pwdb_b; + dm->ofdm_agc_idx[2] = phy_sts->pwdb_c; + dm->ofdm_agc_idx[3] = phy_sts->pwdb_d; + } + + /* @Calculate Signal Quality*/ + if (phy_sts->signal_quality >= 64) { + sq = 0; + } else if (phy_sts->signal_quality <= 20) { + sq = 100; + } else { + /* @mapping to 2~99% */ + sq = 64 - phy_sts->signal_quality; + sq = ((sq << 3) + sq) >> 2; + } + + /* @Modify CCK PWDB if old AGC */ + if (!dm->cck_new_agc) { + u8 lna_idx[4], vga_idx[4]; + + lna_idx[0] = ((phy_sts->lna_h_a << 3) | phy_sts->lna_l_a); + vga_idx[0] = phy_sts->vga_a; + lna_idx[1] = ((phy_sts->lna_h_b << 3) | phy_sts->lna_l_b); + vga_idx[1] = phy_sts->vga_b; + lna_idx[2] = ((phy_sts->lna_h_c << 3) | phy_sts->lna_l_c); + vga_idx[2] = phy_sts->vga_c; + lna_idx[3] = ((phy_sts->lna_h_d << 3) | phy_sts->lna_l_d); + vga_idx[3] = phy_sts->vga_d; + #if (RTL8198F_SUPPORT) + /*phydm_cck_rssi_8198f*/ + #endif + } + + /*@CCK no STBC and LDPC*/ + dm->phy_dbg_info.is_ldpc_pkt = false; + dm->phy_dbg_info.is_stbc_pkt = false; + + /* Update Common information */ + phydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel, false, + false, CHANNEL_WIDTH_20, sq, + phy_sts->l_rxsc, phy_info); + + /* Update CCK pwdb */ + /* Update per-path information */ + phydm_per_path_info_3rd(RF_PATH_A, rx_power[0], 0, 0, 0, phy_info); + phydm_per_path_info_3rd(RF_PATH_B, rx_power[1], 0, 0, 0, phy_info); + phydm_per_path_info_3rd(RF_PATH_C, rx_power[2], 0, 0, 0, phy_info); + phydm_per_path_info_3rd(RF_PATH_D, rx_power[3], 0, 0, 0, phy_info); + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d; + #endif +} + +void phydm_get_physts_jarguar3_1(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 1 is used for ofdm packet */ + struct phy_status_rpt_jaguar3_type1 *phy_sts = NULL; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + s8 rx_pwr_db = -120; + s8 rx_path_pwr_db; + u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_cnt = 0; + u8 pwdb[4]; + boolean is_mu; + + phy_sts = (struct phy_status_rpt_jaguar3_type1 *)phy_status_inf; + + pwdb[0] = phy_sts->pwdb_a; + pwdb[1] = phy_sts->pwdb_b; + pwdb[2] = phy_sts->pwdb_c; + pwdb[3] = phy_sts->pwdb_d; + + /* Update per-path information */ + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (dm->rx_ant_status & BIT(i)) { + rx_cnt++; /* @check the number of the ant */ + + if (rx_cnt > dm->num_rf_path) + break; + + /* Update per-path information + * (RSSI_dB RSSI_percentage EVM SNR CFO sq) + */ + /* @EVM report is reported by stream, not path */ + rx_path_pwr_db = pwdb[i] - 110; /* per-path pw (dB)*/ + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = pwdb[i]; + + phydm_per_path_info_3rd(i, rx_path_pwr_db, + phy_sts->rxevm[rx_cnt - 1], + phy_sts->cfo_tail[i], + phy_sts->rxsnr[i], phy_info); + + /* search maximum pwdb */ + if (rx_path_pwr_db > rx_pwr_db) + rx_pwr_db = rx_path_pwr_db; + } + } + + /* @mapping RX counter from 1~4 to 0~3 */ + if (rx_cnt > 0) + phy_info->rx_count = rx_cnt - 1; + + /* @Check if MU packet or not */ + if (phy_sts->gid != 0 && phy_sts->gid != 63) { + is_mu = true; + dbg_i->num_qry_mu_pkt++; + } else { + is_mu = false; + } + + /* @count BF packet */ + dbg_i->num_qry_bf_pkt = dbg_i->num_qry_bf_pkt + phy_sts->beamformed; + + /*STBC or LDPC pkt*/ + dbg_i->is_ldpc_pkt = phy_sts->ldpc; + dbg_i->is_stbc_pkt = phy_sts->stbc; + + /* @Check sub-channel */ + if (pktinfo->data_rate > ODM_RATE11M && + pktinfo->data_rate < ODM_RATEMCS0) + rxsc = phy_sts->l_rxsc; /*@Legacy*/ + else + rxsc = phy_sts->ht_rxsc; /* @HT and VHT */ + + /* @Check RX bandwidth */ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if (rxsc >= 1 && rxsc <= 8) + bw = CHANNEL_WIDTH_20; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = CHANNEL_WIDTH_40; + else if (rxsc >= 13) + bw = CHANNEL_WIDTH_80; + } + + /* Update packet information */ + /* RX power choose the path with the maximum power */ + phydm_common_phy_info_3rd(rx_pwr_db, phy_sts->channel_pri_lsb, + (boolean)phy_sts->beamformed, is_mu, + bw, phy_info->rx_mimo_signal_quality[0], + rxsc, phy_info); + + phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss); + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d; +#endif +} + +void phydm_get_physts_jarguar3_2_3(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 2 & 3 is used for ofdm packet */ + struct phy_status_rpt_jaguar3_type2_type3 *phy_sts = NULL; + s8 rx_pwr_db_max = -120; + s8 rx_path_pwr_db; + u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0; + + phy_sts = (struct phy_status_rpt_jaguar3_type2_type3 *)phy_status_inf; + + /* Update per-path information */ + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (dm->rx_ant_status & BIT(i)) { + rx_count++; /* @check the number of the ant */ + + if (rx_count > dm->num_rf_path) + break; + + /* Update per-path information + * (RSSI_dB RSSI_percentage EVM SNR CFO sq) + */ + /* @EVM report is reported by stream, not path */ + rx_path_pwr_db = phy_sts->pwdb[i] - 110; /*@dB*/ + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = phy_sts->pwdb[i]; + + phydm_per_path_info_3rd(i, rx_path_pwr_db, 0, + 0, 0, phy_info); + + /* search maximum pwdb */ + if (rx_path_pwr_db > rx_pwr_db_max) + rx_pwr_db_max = rx_path_pwr_db; + } + } + + /* @mapping RX counter from 1~4 to 0~3 */ + if (rx_count > 0) + phy_info->rx_count = rx_count - 1; + + /* @count BF packet */ + dm->phy_dbg_info.num_qry_bf_pkt = dm->phy_dbg_info.num_qry_bf_pkt + + phy_sts->beamformed; + + /*STBC or LDPC pkt*/ + dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc; + dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc; + + /* @Check sub-channel */ + if (pktinfo->data_rate > ODM_RATE11M && + pktinfo->data_rate < ODM_RATEMCS0) + rxsc = phy_sts->l_rxsc; /*@Legacy*/ + else + rxsc = phy_sts->ht_rxsc; /* @HT and VHT */ + + /* @Check RX bandwidth */ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if (rxsc >= 1 && rxsc <= 8) + bw = CHANNEL_WIDTH_20; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = CHANNEL_WIDTH_40; + else if (rxsc >= 13) + bw = CHANNEL_WIDTH_80; + } + + /* Update packet information */ + /* RX power choose the path with the maximum power */ + phydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel_lsb, + (boolean)phy_sts->beamformed, + false, bw, 0, rxsc, phy_info); +} + +void phydm_get_physts_jarguar3_4(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 4 is used for ofdm packet */ + struct phy_status_rpt_jaguar3_type4 *phy_sts = NULL; + s8 rx_pwr_db_max = -120; + s8 rx_path_pwr_db; + u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_cnt = 0; + + phy_sts = (struct phy_status_rpt_jaguar3_type4 *)phy_status_inf; + + /* Update per-path information */ + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (dm->rx_ant_status & BIT(i)) { + rx_cnt++; /* @check the number of the ant */ + + if (rx_cnt > dm->num_rf_path) + break; + + /* Update per-path information + * (RSSI_dB RSSI_percentage EVM SNR CFO sq) + */ + /* @EVM report is reported by stream, not path */ + rx_path_pwr_db = phy_sts->pwdb[i] - 110; /*@dB*/ + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = phy_sts->pwdb[i]; + + phydm_per_path_info_3rd(i, rx_path_pwr_db, + phy_sts->rxevm[rx_cnt - 1], + 0, phy_sts->rxsnr[i], + phy_info); + + /* search maximum pwdb */ + if (rx_path_pwr_db > rx_pwr_db_max) + rx_pwr_db_max = rx_path_pwr_db; + } + } + + /* @mapping RX counter from 1~4 to 0~3 */ + if (rx_cnt > 0) + phy_info->rx_count = rx_cnt - 1; + + /* @count BF packet */ + dm->phy_dbg_info.num_qry_bf_pkt = dm->phy_dbg_info.num_qry_bf_pkt + + phy_sts->beamformed; + + /*STBC or LDPC pkt*/ + dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc; + dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc; + + /* @Check sub-channel */ + if (pktinfo->data_rate > ODM_RATE11M && + pktinfo->data_rate < ODM_RATEMCS0) + rxsc = phy_sts->l_rxsc; /*@Legacy*/ + else + rxsc = phy_sts->ht_rxsc; /* @HT and VHT */ + + /* @Check RX bandwidth */ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if (rxsc >= 1 && rxsc <= 8) + bw = CHANNEL_WIDTH_20; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = CHANNEL_WIDTH_40; + else if (rxsc >= 13) + bw = CHANNEL_WIDTH_80; + } + + /* @Conditional number */ + if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) { + dm->phy_dbg_info.condi_num = (u32)phy_sts->avg_cond_num_0; + } + + /* Update packet information */ + /* RX power choose the path with the maximum power */ + phydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel_lsb, + (boolean)phy_sts->beamformed, + false, bw, 0, rxsc, phy_info); +} + +void phydm_get_physts_jarguar3_5(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 5 is used for ofdm packet */ + struct phy_status_rpt_jaguar3_type5 *phy_sts = NULL; + s8 rx_pwr_db_max = -120; + s8 rx_path_pwr_db; + u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0; + + phy_sts = (struct phy_status_rpt_jaguar3_type5 *)phy_status_inf; + + /* Update per-path information */ + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (dm->rx_ant_status & BIT(i)) { + rx_count++; /* @check the number of the ant */ + + if (rx_count > dm->num_rf_path) + break; + + /* Update per-path information + * (RSSI_dB RSSI_percentage EVM SNR CFO sq) + */ + /* @EVM report is reported by stream, not path */ + rx_path_pwr_db = phy_sts->pwdb[i] - 110; /*@dB*/ + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = phy_sts->pwdb[i]; + + phydm_per_path_info_3rd(i, rx_path_pwr_db, + 0, 0, 0, phy_info); + + /* search maximum pwdb */ + if (rx_path_pwr_db > rx_pwr_db_max) + rx_pwr_db_max = rx_path_pwr_db; + } + } + + /* @mapping RX counter from 1~4 to 0~3 */ + if (rx_count > 0) + phy_info->rx_count = rx_count - 1; + + /* @count BF packet */ + dm->phy_dbg_info.num_qry_bf_pkt = dm->phy_dbg_info.num_qry_bf_pkt + + phy_sts->beamformed; + + /*STBC or LDPC pkt*/ + dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc; + dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc; + + /* @Check sub-channel */ + if (pktinfo->data_rate > ODM_RATE11M && + pktinfo->data_rate < ODM_RATEMCS0) + rxsc = phy_sts->l_rxsc; /*@Legacy*/ + else + rxsc = phy_sts->ht_rxsc; /* @HT and VHT */ + + /* @Check RX bandwidth */ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if (rxsc >= 1 && rxsc <= 8) + bw = CHANNEL_WIDTH_20; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = CHANNEL_WIDTH_40; + else if (rxsc >= 13) + bw = CHANNEL_WIDTH_80; + } + + /* Update packet information */ + /* RX power choose the path with the maximum power */ + phydm_common_phy_info_3rd(rx_pwr_db_max, phy_sts->channel_lsb, + (boolean)phy_sts->beamformed, + false, bw, 0, rxsc, phy_info); +} + +void phydm_process_dm_rssi_3rd_type(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo) +{ + struct cmn_sta_info *sta = NULL; + struct rssi_info *rssi_t = NULL; + u8 rssi_tmp = 0; + u32 rssi_linear = 0; + s16 rssi_db = 0; + u8 i = 0; + + /*@[Step4]*/ + + if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + sta = dm->phydm_sta_info[pktinfo->station_id]; + + if (!is_sta_active(sta)) + return; + + if (!pktinfo->is_packet_match_bssid) /*@data frame only*/ + return; + + if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon)) + return; + + if (pktinfo->is_packet_beacon) { + dm->phy_dbg_info.num_qry_beacon_pkt++; + dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate; + } + + rssi_t = &sta->rssi_stat; + + if (pktinfo->is_cck_rate) { + rssi_db = phy_info->rx_mimo_signal_strength[0]; /*Path-A*/ + if (rssi_t->rssi_acc == 0) { + rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA); + rssi_t->rssi = (s8)(rssi_db); + } else { + rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, + rssi_db, RSSI_MA); + rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, + RSSI_MA); + } + rssi_t->rssi_cck = (s8)rssi_db; + } else { + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + rssi_tmp = phy_info->rx_mimo_signal_strength[i]; + if (rssi_tmp != 0) + rssi_linear += phydm_db_2_linear(rssi_tmp); + } + switch (phy_info->rx_count + 1) { + case 2: + rssi_linear = DIVIDED_2(rssi_linear); + break; + case 3: + rssi_linear = DIVIDED_3(rssi_linear); + break; + case 4: + rssi_linear = DIVIDED_4(rssi_linear); + break; + } + rssi_db = (s16)odm_convert_to_db(rssi_linear); + + if (rssi_t->rssi_acc == 0) { + rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA); + rssi_t->rssi = (s8)(rssi_db); + } else { + rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, + rssi_db, RSSI_MA); + rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, + RSSI_MA); + } + rssi_t->rssi_ofdm = (s8)rssi_db; + } +} + +void phydm_rx_physts_3rd_type(void *dm_void, u8 *phy_sts, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#ifdef PHYDM_PHYSTAUS_SMP_MODE + struct pkt_process_info *pkt_process = &dm->pkt_proc_struct; +#endif + u8 phy_status_type = (*phy_sts & 0xf); + +#ifdef PHYDM_PHYSTAUS_SMP_MODE + if (pkt_process->phystatus_smp_mode_en && phy_status_type != 0) { + if (pkt_process->pre_ppdu_cnt == pktinfo->ppdu_cnt) + return; + pkt_process->pre_ppdu_cnt = pktinfo->ppdu_cnt; + } +#endif + + /*@[Step 2]*/ + phydm_reset_phy_info_3rd(dm, phy_info); /* @Memory reset */ + + /* Phy status parsing */ + switch (phy_status_type) { + case 0: /*@CCK*/ + phydm_get_physts_jarguar3_0(dm, phy_sts, pktinfo, phy_info); + break; + case 1: + phydm_get_physts_jarguar3_1(dm, phy_sts, pktinfo, phy_info); + break; + case 2: + case 3: + phydm_get_physts_jarguar3_2_3(dm, phy_sts, pktinfo, phy_info); + break; + case 4: + phydm_get_physts_jarguar3_4(dm, phy_sts, pktinfo, phy_info); + break; + case 5: + phydm_get_physts_jarguar3_5(dm, phy_sts, pktinfo, phy_info); + break; + default: + break; + } + + + /*@[Step 1]*/ + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_print_phystat_jaguar3(dm, phy_sts, pktinfo, phy_info); + #endif +} + +#endif + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) +/* @For 8822B only!! need to move to FW finally */ +/*@==============================================*/ + +boolean +phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate, + u8 *p_gid) +{ + u8 data_rate = 0, gid = 0; + boolean is_mu = false; + + data_rate = phydm->phy_dbg_info.num_of_ppdu[ppdu_idx]; + gid = phydm->phy_dbg_info.gid_num[ppdu_idx]; + + if (data_rate & BIT(7)) { + is_mu = true; + data_rate = data_rate & ~(BIT(7)); + } else { + is_mu = false; + } + + *p_data_rate = data_rate; + *p_gid = gid; + + return is_mu; +} + +void phydm_reset_phy_info(struct dm_struct *phydm, + struct phydm_phyinfo_struct *phy_info) +{ + phy_info->rx_pwdb_all = 0; + phy_info->signal_quality = 0; + phy_info->band_width = 0; + phy_info->rx_count = 0; + odm_memory_set(phydm, phy_info->rx_mimo_signal_quality, 0, 4); + odm_memory_set(phydm, phy_info->rx_mimo_signal_strength, 0, 4); + odm_memory_set(phydm, phy_info->rx_snr, 0, 4); + + phy_info->rx_power = -110; + phy_info->recv_signal_power = -110; + phy_info->bt_rx_rssi_percentage = 0; + phy_info->signal_strength = 0; + phy_info->channel = 0; + phy_info->is_mu_packet = 0; + phy_info->is_beamformed = 0; + phy_info->rxsc = 0; + odm_memory_set(phydm, phy_info->rx_pwr, -110, 4); + odm_memory_set(phydm, phy_info->cfo_short, 0, 8); + odm_memory_set(phydm, phy_info->cfo_tail, 0, 8); + + odm_memory_set(phydm, phy_info->rx_mimo_evm_dbm, 0, 4); +} + +void phydm_print_phy_sts_jgr2(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct phy_status_rpt_jaguar2_type0 *rpt0 = NULL; + struct phy_status_rpt_jaguar2_type1 *rpt = NULL; + struct phy_status_rpt_jaguar2_type2 *rpt2 = NULL; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + u8 phy_status_page_num = (*phy_status_inf & 0xf); + u32 phy_status[PHY_STATUS_JRGUAR2_DW_LEN] = {0}; + u8 i; + u32 size = PHY_STATUS_JRGUAR2_DW_LEN << 2; + + rpt0 = (struct phy_status_rpt_jaguar2_type0 *)phy_status_inf; + rpt = (struct phy_status_rpt_jaguar2_type1 *)phy_status_inf; + rpt2 = (struct phy_status_rpt_jaguar2_type2 *)phy_status_inf; + + odm_move_memory(dm, phy_status, phy_status_inf, size); + + if (!(dm->debug_components & DBG_PHY_STATUS)) + return; + + if (dbg->show_phy_sts_all_pkt == 0) { + if (!pktinfo->is_packet_match_bssid) + return; + } + + dbg->show_phy_sts_cnt++; + #if 0 + dbg_print("cnt=%d, max=%d\n", + dbg->show_phy_sts_cnt, dbg->show_phy_sts_max_cnt); + #endif + + if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) { + if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt) + return; + } + + pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num); + pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d\n", + pktinfo->station_id, pktinfo->data_rate, + pktinfo->is_packet_match_bssid); + + for (i = 0; i < PHY_STATUS_JRGUAR2_DW_LEN; i++) + pr_debug("Offset[%d:%d] = 0x%x\n", + ((4 * i) + 3), (4 * i), phy_status[i]); + + if (phy_status_page_num == 0) { + pr_debug("[0] TRSW=%d, MP_gain_idx=%d, pwdb=%d\n", + rpt0->trsw, rpt0->gain, rpt0->pwdb); + pr_debug("[4] band=%d, CH=%d, agc_table = %d, rxsc = %d\n", + rpt0->band, rpt0->channel, + rpt0->agc_table, rpt0->rxsc); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n", + rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b, + rpt0->antidx_a, rpt0->length); + pr_debug("[12] lna_h=%d, bb_pwr=%d, lna_l=%d, vga=%d, sq=%d\n", + rpt0->lna_h, rpt0->bb_power, rpt0->lna_l, + rpt0->vga, rpt0->signal_quality); + + } else if (phy_status_page_num == 1) { + pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n", + rpt->pwdb[3], rpt->pwdb[2], + rpt->pwdb[1], rpt->pwdb[0]); + pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht, l]={%d, %d}\n", + rpt->beamformed, rpt->ldpc, rpt->stbc, rpt->gnt_bt, + rpt->hw_antsw_occu, rpt->band, rpt->channel, + rpt->ht_rxsc, rpt->l_rxsc); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n", + rpt->antidx_d, rpt->antidx_c, rpt->antidx_b, + rpt->antidx_a, rpt->lsig_length); + pr_debug("[12] rf_mode=%d, NBI=%d, Intf_pos=%d, GID=%d, PAID=%d\n", + rpt->rf_mode, rpt->nb_intf_flag, + (rpt->intf_pos + (rpt->intf_pos_msb << 8)), rpt->gid, + (rpt->paid + (rpt->paid_msb << 8))); + pr_debug("[16] EVM[D:A]={%d, %d, %d, %d}\n", + rpt->rxevm[3], rpt->rxevm[2], + rpt->rxevm[1], rpt->rxevm[0]); + pr_debug("[20] CFO[D:A]={%d, %d, %d, %d}\n", + rpt->cfo_tail[3], rpt->cfo_tail[2], rpt->cfo_tail[1], + rpt->cfo_tail[0]); + pr_debug("[24] SNR[D:A]={%d, %d, %d, %d}\n\n", + rpt->rxsnr[3], rpt->rxsnr[2], rpt->rxsnr[1], + rpt->rxsnr[0]); + + } else if (phy_status_page_num == 2) { + pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n", + rpt2->pwdb[3], rpt2->pwdb[2], rpt2->pwdb[1], + rpt2->pwdb[0]); + pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht,l]={%d, %d}\n", + rpt2->beamformed, rpt2->ldpc, rpt2->stbc, rpt2->gnt_bt, + rpt2->hw_antsw_occu, rpt2->band, rpt2->channel, + rpt2->ht_rxsc, rpt2->l_rxsc); + pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, cnt_pw2cca=%d, shift_l_map=%d\n", + rpt2->agc_table_d, rpt2->agc_table_c, + rpt2->agc_table_b, rpt2->agc_table_a, + rpt2->cnt_pw2cca, rpt2->shift_l_map); + pr_debug("[12] (TRSW|Gain)[D:A]={%d %d, %d %d, %d %d, %d %d}, cnt_cca2agc_rdy=%d\n", + rpt2->trsw_d, rpt2->gain_d, rpt2->trsw_c, rpt2->gain_c, + rpt2->trsw_b, rpt2->gain_b, rpt2->trsw_a, + rpt2->gain_a, rpt2->cnt_cca2agc_rdy); + pr_debug("[16] AAGC step[D:A]={%d, %d, %d, %d} HT AAGC gain[D:A]={%d, %d, %d, %d}\n", + rpt2->aagc_step_d, rpt2->aagc_step_c, + rpt2->aagc_step_b, rpt2->aagc_step_a, + rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2], + rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0]); + pr_debug("[20] DAGC gain[D:A]={%d, %d, %d, %d}\n", + rpt2->dagc_gain[3], + rpt2->dagc_gain[2], rpt2->dagc_gain[1], + rpt2->dagc_gain[0]); + pr_debug("[24] syn_cnt: %d, Cnt=%d\n\n", + rpt2->syn_count, rpt2->counter); + } +} + +void phydm_set_per_path_phy_info(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail, + s8 rx_snr, + struct phydm_phyinfo_struct *phy_info) +{ + u8 evm_dbm = 0; + u8 evm_percentage = 0; + + /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ + + if (rx_evm < 0) { + /* @Calculate EVM in dBm */ + evm_dbm = ((u8)(0 - rx_evm) >> 1); + + if (evm_dbm == 64) + evm_dbm = 0; /*@if 1SS rate, evm_dbm [2nd stream] =64*/ + + if (evm_dbm != 0) { + /* @Convert EVM to 0%~100% percentage */ + if (evm_dbm >= 34) + evm_percentage = 100; + else + evm_percentage = (evm_dbm << 1) + (evm_dbm); + } + } + + phy_info->rx_pwr[rx_path] = pwr; + + /*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/ + phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1; + phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm; + phy_info->rx_mimo_signal_strength[rx_path] = phydm_pwr_2_percent(pwr); + phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage; + phy_info->rx_snr[rx_path] = rx_snr >> 1; + +#if 0 + if (!pktinfo->is_packet_match_bssid) + return; + + dbg_print("path (%d)--------\n", rx_path); + dbg_print("rx_pwr = %d, Signal strength = %d\n", + phy_info->rx_pwr[rx_path], + phy_info->rx_mimo_signal_strength[rx_path]); + dbg_print("evm_dbm = %d, Signal quality = %d\n", + phy_info->rx_mimo_evm_dbm[rx_path], + phy_info->rx_mimo_signal_quality[rx_path]); + dbg_print("CFO = %d, SNR = %d\n", + phy_info->cfo_tail[rx_path], phy_info->rx_snr[rx_path]); + +#endif +} + +void phydm_set_common_phy_info(s8 rx_power, u8 channel, boolean is_beamformed, + boolean is_mu_packet, u8 bandwidth, + u8 signal_quality, u8 rxsc, + struct phydm_phyinfo_struct *phy_info) +{ + phy_info->rx_power = rx_power; /* RSSI in dB */ + phy_info->recv_signal_power = rx_power; /* RSSI in dB */ + phy_info->channel = channel; /* @channel number */ + phy_info->is_beamformed = is_beamformed; /* @apply BF */ + phy_info->is_mu_packet = is_mu_packet; /* @MU packet */ + phy_info->rxsc = rxsc; + + /* RSSI in percentage */ + phy_info->rx_pwdb_all = phydm_pwr_2_percent(rx_power); + phy_info->signal_quality = signal_quality; /* signal quality */ + phy_info->band_width = bandwidth; /* @bandwidth */ + +#if 0 + if (!pktinfo->is_packet_match_bssid) + return; + + dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", + phy_info->rx_pwdb_all, phy_info->rx_power, + phy_info->recv_signal_power); + dbg_print("signal_quality = %d\n", phy_info->signal_quality); + dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", + phy_info->is_beamformed, phy_info->is_mu_packet, + phy_info->rx_count + 1); + dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, + rxsc, bandwidth); + +#endif +} + +void phydm_get_phy_sts_type0(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 0 is used for cck packet */ + struct phy_status_rpt_jaguar2_type0 *phy_sts = NULL; + u8 sq = 0; + s8 rx_pow = 0; + u8 lna_idx = 0, vga_idx = 0; + + phy_sts = (struct phy_status_rpt_jaguar2_type0 *)phy_status_inf; + rx_pow = phy_sts->pwdb - 110; + + if (dm->support_ic_type & ODM_RTL8723D) { + #if (RTL8723D_SUPPORT) + rx_pow = phy_sts->pwdb - 97; + #endif + } + #if (RTL8821C_SUPPORT) + else if (dm->support_ic_type & ODM_RTL8821C) { + if (phy_sts->pwdb >= -57) + rx_pow = phy_sts->pwdb - 100; + else + rx_pow = phy_sts->pwdb - 102; + } + #endif + + if (pktinfo->is_to_self) { + dm->ofdm_agc_idx[0] = phy_sts->pwdb; + dm->ofdm_agc_idx[1] = 0; + dm->ofdm_agc_idx[2] = 0; + dm->ofdm_agc_idx[3] = 0; + } + + /* @Calculate Signal Quality*/ + if (phy_sts->signal_quality >= 64) { + sq = 0; + } else if (phy_sts->signal_quality <= 20) { + sq = 100; + } else { + /* @mapping to 2~99% */ + sq = 64 - phy_sts->signal_quality; + sq = ((sq << 3) + sq) >> 2; + } + + /* @Get RSSI for old CCK AGC */ + if (!dm->cck_new_agc) { + vga_idx = phy_sts->vga; + + if (dm->support_ic_type & ODM_RTL8197F) { + /*@3bit LNA*/ + lna_idx = phy_sts->lna_l; + } else { + /*@4bit LNA*/ + lna_idx = (phy_sts->lna_h << 3) | phy_sts->lna_l; + } + rx_pow = phydm_get_cck_rssi(dm, lna_idx, vga_idx); + } + + /* @Confirm CCK RSSI */ + #if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) { + u8 bb_pwr_th_l = 5; /* round( 31*0.15 ) */ + u8 bb_pwr_th_h = 27; /* round( 31*0.85 ) */ + + if (phy_sts->bb_power < bb_pwr_th_l || + phy_sts->bb_power > bb_pwr_th_h) + rx_pow = 0; /* @Error RSSI for CCK ; set 100*/ + } + #endif + + /*@CCK no STBC and LDPC*/ + dm->phy_dbg_info.is_ldpc_pkt = false; + dm->phy_dbg_info.is_stbc_pkt = false; + + /* Update Common information */ + phydm_set_common_phy_info(rx_pow, phy_sts->channel, false, + false, CHANNEL_WIDTH_20, sq, + phy_sts->rxsc, phy_info); + /* Update CCK pwdb */ + phydm_set_per_path_phy_info(RF_PATH_A, rx_pow, 0, 0, 0, phy_info); + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d; + #endif +} + +void phydm_get_phy_sts_type1(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 1 is used for ofdm packet */ + struct phy_status_rpt_jaguar2_type1 *phy_sts = NULL; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + s8 rx_pwr_db = -120; + s8 rx_pwr = 0; + u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0; + boolean is_mu; + + phy_sts = (struct phy_status_rpt_jaguar2_type1 *)phy_status_inf; + + /* Update per-path information */ + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (!(dm->rx_ant_status & BIT(i))) + continue; + rx_count++; + + if (rx_count > dm->num_rf_path) + break; + + /* Update per-path information + * (RSSI_dB RSSI_percentage EVM SNR CFO sq) + */ + /* @EVM report is reported by stream, not path */ + rx_pwr = phy_sts->pwdb[i] - 110; /* per-path pwdb(dB)*/ + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = phy_sts->pwdb[i]; + + phydm_set_per_path_phy_info(i, rx_pwr, + phy_sts->rxevm[rx_count - 1], + phy_sts->cfo_tail[i], + phy_sts->rxsnr[i], phy_info); + /* search maximum pwdb */ + if (rx_pwr > rx_pwr_db) + rx_pwr_db = rx_pwr; + } + + /* @mapping RX counter from 1~4 to 0~3 */ + if (rx_count > 0) + phy_info->rx_count = rx_count - 1; + + /* @Check if MU packet or not */ + if (phy_sts->gid != 0 && phy_sts->gid != 63) { + is_mu = true; + dbg_i->num_qry_mu_pkt++; + } else { + is_mu = false; + } + + /* @count BF packet */ + dbg_i->num_qry_bf_pkt = dbg_i->num_qry_bf_pkt + phy_sts->beamformed; + + /*STBC or LDPC pkt*/ + dbg_i->is_ldpc_pkt = phy_sts->ldpc; + dbg_i->is_stbc_pkt = phy_sts->stbc; + + /* @Check sub-channel */ + if (pktinfo->data_rate > ODM_RATE11M && + pktinfo->data_rate < ODM_RATEMCS0) + rxsc = phy_sts->l_rxsc; + else + rxsc = phy_sts->ht_rxsc; + + /* @Check RX bandwidth */ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (rxsc >= 1 && rxsc <= 8) + bw = CHANNEL_WIDTH_20; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = CHANNEL_WIDTH_40; + else if (rxsc >= 13) + bw = CHANNEL_WIDTH_80; + else + bw = phy_sts->rf_mode; + + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (phy_sts->rf_mode == 0) + bw = CHANNEL_WIDTH_20; + else if ((rxsc == 1) || (rxsc == 2)) + bw = CHANNEL_WIDTH_20; + else + bw = CHANNEL_WIDTH_40; + } + + /* Update packet information */ + phydm_set_common_phy_info(rx_pwr_db, phy_sts->channel, + (boolean)phy_sts->beamformed, is_mu, bw, + phy_info->rx_mimo_signal_quality[0], + rxsc, phy_info); + + phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss); + #ifdef PHYDM_LNA_SAT_CHK_TYPE2 + phydm_parsing_snr(dm, pktinfo, phy_sts->rxsnr); + #endif + + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d; + #endif +} + +void phydm_get_phy_sts_type2(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct phy_status_rpt_jaguar2_type2 *phy_sts = NULL; + s8 rx_pwr_db_max = -120; + s8 rx_pwr = 0; + u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0; + + phy_sts = (struct phy_status_rpt_jaguar2_type2 *)phy_status_inf; + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (!(dm->rx_ant_status & BIT(i))) + continue; + rx_count++; + + if (rx_count > dm->num_rf_path) + break; + + /* Update per-path information*/ + /* RSSI_dB, RSSI_percentage, EVM, SNR, CFO, sq */ + #if (RTL8197F_SUPPORT) + if ((dm->support_ic_type & ODM_RTL8197F) && + phy_sts->pwdb[i] == 0x7f) { /*@97f workaround*/ + + if (i == RF_PATH_A) { + rx_pwr = (phy_sts->gain_a) << 1; + rx_pwr = rx_pwr - 110; + } else if (i == RF_PATH_B) { + rx_pwr = (phy_sts->gain_b) << 1; + rx_pwr = rx_pwr - 110; + } else { + rx_pwr = 0; + } + } else + #endif + rx_pwr = phy_sts->pwdb[i] - 110; /*@dBm*/ + + phydm_set_per_path_phy_info(i, rx_pwr, 0, 0, 0, phy_info); + + if (rx_pwr > rx_pwr_db_max) /* search max pwdb */ + rx_pwr_db_max = rx_pwr; + } + + /* @mapping RX counter from 1~4 to 0~3 */ + if (rx_count > 0) + phy_info->rx_count = rx_count - 1; + + /* @Check RX sub-channel */ + if (pktinfo->data_rate > ODM_RATE11M && + pktinfo->data_rate < ODM_RATEMCS0) + rxsc = phy_sts->l_rxsc; + else + rxsc = phy_sts->ht_rxsc; + + /*STBC or LDPC pkt*/ + dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc; + dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc; + + /* @Check RX bandwidth */ + /* @BW information of sc=0 is useless, + *because there is no information of RF mode + */ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (rxsc >= 1 && rxsc <= 8) + bw = CHANNEL_WIDTH_20; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = CHANNEL_WIDTH_40; + else if (rxsc >= 13) + bw = CHANNEL_WIDTH_80; + + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (rxsc == 3) + bw = CHANNEL_WIDTH_40; + else if ((rxsc == 1) || (rxsc == 2)) + bw = CHANNEL_WIDTH_20; + } + + /* Update packet information */ + phydm_set_common_phy_info(rx_pwr_db_max, phy_sts->channel, + (boolean)phy_sts->beamformed, + false, bw, 0, rxsc, phy_info); +} + +void phydm_process_rssi_for_dm_2nd_type(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo + ) +{ + struct cmn_sta_info *sta = NULL; + struct rssi_info *rssi_t = NULL; + u8 rssi_tmp = 0; + u32 rssi_linear = 0; + s16 rssi_db = 0; + u8 i = 0; + + if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + sta = dm->phydm_sta_info[pktinfo->station_id]; + + if (!is_sta_active(sta)) + return; + + if (!pktinfo->is_packet_match_bssid) /*@data frame only*/ + return; + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + if (dm->support_ability & ODM_BB_ANT_DIV) + odm_process_rssi_for_ant_div(dm, phy_info, pktinfo); +#endif + +#ifdef CONFIG_ADAPTIVE_SOML + phydm_rx_qam_for_soml(dm, pktinfo); + phydm_rx_rate_for_soml(dm, pktinfo); +#endif + + if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon)) + return; + + if (pktinfo->is_packet_beacon) { + dm->phy_dbg_info.num_qry_beacon_pkt++; + dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate; + } + + rssi_t = &sta->rssi_stat; + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + rssi_tmp = phy_info->rx_mimo_signal_strength[i]; + if (rssi_tmp != 0) + rssi_linear += phydm_db_2_linear(rssi_tmp); + } + + switch (phy_info->rx_count + 1) { + case 2: + rssi_linear = DIVIDED_2(rssi_linear); + break; + case 3: + rssi_linear = DIVIDED_3(rssi_linear); + break; + case 4: + rssi_linear = DIVIDED_4(rssi_linear); + break; + } + + rssi_db = (s16)odm_convert_to_db(rssi_linear); + + if (rssi_t->rssi_acc == 0) { + rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA); + rssi_t->rssi = (s8)(rssi_db); + } else { + rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA); + rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA); + } + + #if 0 + PHYDM_DBG(dm, DBG_TMP, "RSSI[%d]{A,B,C,D}={%d, %d, %d, %d} AVG=%d\n", + pktinfo->station_id, + phy_info->rx_mimo_signal_strength[0], + phy_info->rx_mimo_signal_strength[1], + phy_info->rx_mimo_signal_strength[2], + phy_info->rx_mimo_signal_strength[3], rssi_db); + PHYDM_DBG(dm, DBG_TMP, "rssi_acc = %d, rssi=%d\n", + rssi_t->rssi_acc, rssi_t->rssi); + #endif + + if (pktinfo->is_cck_rate) + rssi_t->rssi_cck = (s8)rssi_db; + else + rssi_t->rssi_ofdm = (s8)rssi_db; +} + +void phydm_rx_physts_2nd_type(void *dm_void, u8 *phy_sts, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#ifdef PHYDM_PHYSTAUS_SMP_MODE + struct pkt_process_info *pkt_process = &dm->pkt_proc_struct; +#endif + u8 page = (*phy_sts & 0xf); + +#ifdef PHYDM_PHYSTAUS_SMP_MODE + if (pkt_process->phystatus_smp_mode_en && page != 0) { + if (pkt_process->pre_ppdu_cnt == pktinfo->ppdu_cnt) + return; + + pkt_process->pre_ppdu_cnt = pktinfo->ppdu_cnt; + } +#endif + + phydm_reset_phy_info(dm, phy_info); /* @Memory reset */ + + /* Phy status parsing */ + switch (page) { + case 0: /*@CCK*/ + phydm_get_phy_sts_type0(dm, phy_sts, pktinfo, phy_info); + break; + case 1: + phydm_get_phy_sts_type1(dm, phy_sts, pktinfo, phy_info); + break; + case 2: + phydm_get_phy_sts_type2(dm, phy_sts, pktinfo, phy_info); + break; + default: + break; + } + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) + phydm_print_phy_sts_jgr2(dm, phy_sts, pktinfo, phy_info); +#endif +} + +/*@==============================================*/ +#endif + +void odm_phy_status_query(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo) +{ + u8 rate = pktinfo->data_rate; + + pktinfo->is_cck_rate = (rate <= ODM_RATE11M) ? true : false; + pktinfo->rate_ss = phydm_rate_to_num_ss(dm, rate); + dm->rate_ss = pktinfo->rate_ss; /*@For AP EVM SW antenna diversity use*/ + + if (pktinfo->is_cck_rate) + dm->phy_dbg_info.num_qry_phy_status_cck++; + else + dm->phy_dbg_info.num_qry_phy_status_ofdm++; + + /*Reset phy_info*/ + odm_memory_set(dm, phy_info->rx_mimo_signal_strength, 0, 4); + odm_memory_set(dm, phy_info->rx_mimo_signal_quality, 0, 4); + if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) { + #ifdef PHYSTS_3RD_TYPE_SUPPORT + phydm_rx_physts_3rd_type(dm, phy_status_inf, pktinfo, phy_info); + phydm_process_dm_rssi_3rd_type(dm, phy_info, pktinfo); + #endif + } else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) { + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + phydm_rx_physts_2nd_type(dm, phy_status_inf, pktinfo, phy_info); + phydm_process_rssi_for_dm_2nd_type(dm, phy_info, pktinfo); + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if ODM_IC_11AC_SERIES_SUPPORT + phydm_rx_physts_1st_type(dm, phy_info, phy_status_inf, pktinfo); + phydm_process_rssi_for_dm(dm, phy_info, pktinfo); + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + #if ODM_IC_11N_SERIES_SUPPORT + phydm_phy_sts_n_parsing(dm, phy_info, phy_status_inf, pktinfo); + phydm_process_rssi_for_dm(dm, phy_info, pktinfo); + #endif + } + phy_info->signal_strength = phy_info->rx_pwdb_all; + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + phydm_process_signal_strength(dm, phy_info, pktinfo); + #endif + + if (pktinfo->is_packet_match_bssid) { + dm->curr_station_id = pktinfo->station_id; + dm->rx_rate = rate; + dm->rssi_a = phy_info->rx_mimo_signal_strength[RF_PATH_A]; + dm->rssi_b = phy_info->rx_mimo_signal_strength[RF_PATH_B]; + dm->rssi_c = phy_info->rx_mimo_signal_strength[RF_PATH_C]; + dm->rssi_d = phy_info->rx_mimo_signal_strength[RF_PATH_D]; + + if (rate >= ODM_RATE6M && rate <= ODM_RATE54M) + dm->rxsc_l = (s8)phy_info->rxsc; + else if (phy_info->band_width == CHANNEL_WIDTH_20) + dm->rxsc_20 = (s8)phy_info->rxsc; + else if (phy_info->band_width == CHANNEL_WIDTH_40) + dm->rxsc_40 = (s8)phy_info->rxsc; + else if (phy_info->band_width == CHANNEL_WIDTH_80) + dm->rxsc_80 = (s8)phy_info->rxsc; + + phydm_avg_phystatus_index(dm, phy_info, pktinfo); + phydm_rx_statistic_cal(dm, phy_info, phy_status_inf, pktinfo); + } +} + +void phydm_rx_phy_status_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; +#ifdef PHYDM_PHYSTAUS_SMP_MODE + struct pkt_process_info *pkt_process = &dm->pkt_proc_struct; + + if (dm->support_ic_type & ODM_RTL8822B) { + pkt_process->phystatus_smp_mode_en = 1; + pkt_process->pre_ppdu_cnt = 0xff; + /*phystatus sampling mode enable*/ + odm_set_mac_reg(dm, R_0x60f, BIT(7), 1); + /*@First update timming*/ + odm_set_bb_reg(dm, R_0x9e4, 0x3ff, 0x0); + /*Update Sampling time*/ + odm_set_bb_reg(dm, R_0x9e4, 0xfc00, 0x0); + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + /*@First update timming*/ + odm_set_bb_reg(dm, R_0x8c0, 0x3ff0, 0x0); + /*Update Sampling time*/ + odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 0x0); + } +#endif + + dbg->show_phy_sts_all_pkt = 0; + dbg->show_phy_sts_max_cnt = 1; + dbg->show_phy_sts_cnt = 0; + + phydm_avg_phystatus_init(dm); +} diff --git a/hal/phydm/phydm_phystatus.h b/hal/phydm/phydm_phystatus.h new file mode 100644 index 0000000..045402e --- /dev/null +++ b/hal/phydm/phydm_phystatus.h @@ -0,0 +1,1137 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_PHYSTATUS_H__ +#define __PHYDM_PHYSTATUS_H__ + +/*@--------------------------Define ------------------------------------------*/ +#define CCK_RSSI_INIT_COUNT 5 + +#define RA_RSSI_STATE_INIT 0 +#define RA_RSSI_STATE_SEND 1 +#define RA_RSSI_STATE_HOLD 2 + +#if defined(DM_ODM_CE_MAC80211) +#define CFO_HW_RPT_2_KHZ(val) ({ \ + s32 cfo_hw_rpt_2_khz_tmp = (val); \ + (cfo_hw_rpt_2_khz_tmp << 1) + (cfo_hw_rpt_2_khz_tmp >> 1); \ + }) +#else +#define CFO_HW_RPT_2_KHZ(val) ((val << 1) + (val >> 1)) +#endif + +/* @(X* 312.5 Khz)>>7 ~= X*2.5 Khz= (X<<1 + X>>1)Khz */ + +#define IGI_2_RSSI(igi) (igi - 10) + +#define PHY_STATUS_JRGUAR2_DW_LEN 7 /* @7*4 = 28 Byte */ +#define PHY_STATUS_JRGUAR3_DW_LEN 7 /* @7*4 = 28 Byte */ +#define SHOW_PHY_STATUS_UNLIMITED 0 +#define RSSI_MA 4 + +#define PHYSTS_PATH_NUM 4 + +/*@************************************************************ + * structure and define + ************************************************************/ + +__PACK struct phy_rx_agc_info { +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain : 7, trsw : 1; +#else + u8 trsw : 1, gain : 7; +#endif +}; + +__PACK struct phy_status_rpt_8192cd { + struct phy_rx_agc_info path_agc[2]; + u8 ch_corr[2]; + u8 cck_sig_qual_ofdm_pwdb_all; + u8 cck_agc_rpt_ofdm_cfosho_a; + u8 cck_rpt_b_ofdm_cfosho_b; + u8 rsvd_1;/*@ch_corr_msb;*/ + u8 noise_power_db_msb; + s8 path_cfotail[2]; + u8 pcts_mask[2]; + s8 stream_rxevm[2]; + u8 path_rxsnr[2]; + u8 noise_power_db_lsb; + u8 rsvd_2[3]; + u8 stream_csi[2]; + u8 stream_target_csi[2]; + s8 sig_evm; + u8 rsvd_3; + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antsel_rx_keep_2: 1; /*@ex_intf_flg:1;*/ + u8 sgi_en: 1; + u8 rxsc: 2; + u8 idle_long: 1; + u8 r_ant_train_en: 1; + u8 ant_sel_b: 1; + u8 ant_sel: 1; +#else /*@_BIG_ENDIAN_ */ + u8 ant_sel: 1; + u8 ant_sel_b: 1; + u8 r_ant_train_en: 1; + u8 idle_long: 1; + u8 rxsc: 2; + u8 sgi_en: 1; + u8 antsel_rx_keep_2: 1;/*@ex_intf_flg:1;*/ +#endif +}; + +struct phy_status_rpt_8812 { + /* @DWORD 0*/ + u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ + u8 chl_num_LSB; /*@channel number[7:0]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 chl_num_MSB : 2; /*@channel number[9:8]*/ + u8 sub_chnl : 4; /*sub-channel location[3:0]*/ + u8 r_RFMOD : 2; /*RF mode[1:0]*/ +#else /*@_BIG_ENDIAN_ */ + u8 r_RFMOD : 2; + u8 sub_chnl : 4; + u8 chl_num_MSB : 2; +#endif + + /* @DWORD 1*/ + u8 pwdb_all; /*@CCK signal quality / OFDM pwdb all*/ + s8 cfosho[2]; /*@CCK AGC report and CCK_BB_Power*/ + /*OFDM path-A and path-B short CFO*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 resvd_0 : 6; + u8 bt_RF_ch_MSB : 2; /*@8812A:2'b0 8814A: bt rf channel keep[7:6]*/ +#else /*@_BIG_ENDIAN_*/ + u8 bt_RF_ch_MSB : 2; + u8 resvd_0 : 6; +#endif + +/* @DWORD 2*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 ant_div_sw_a : 1; /*@8812A: ant_div_sw_a 8814A: 1'b0*/ + u8 ant_div_sw_b : 1; /*@8812A: ant_div_sw_b 8814A: 1'b0*/ + u8 bt_RF_ch_LSB : 6; /*@8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ +#else /*@_BIG_ENDIAN_ */ + u8 bt_RF_ch_LSB : 6; + u8 ant_div_sw_b : 1; + u8 ant_div_sw_a : 1; +#endif + s8 cfotail[2]; /*@DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ + u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ + u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ + + /* @DWORD 3*/ + s8 rxevm[2]; /*@DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ + s8 rxsnr[2]; /*@DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ + + /* @DWORD 4*/ + u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/ + u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/ + u8 resvd_1 : 1; /*@1'b0*/ +#else /*@_BIG_ENDIAN_*/ + u8 resvd_1 : 1; + u8 pcts_rpt_valid : 1; + u8 PCTS_MSK_RPT_3 : 6; +#endif + s8 rxevm_cd[2]; /*@8812A: 16'b0*/ + /*@8814A: stream 3 and stream 4 RX EVM*/ + /* @DWORD 5*/ + u8 csi_current[2]; /*@8812A: stream 1 and 2 CSI*/ + /*@8814A: path-C and path-D RX SNR*/ + u8 gain_trsw_cd[2]; /*path-C and path-D {TRSW, gain[6:0] }*/ + + /* @DWORD 6*/ + s8 sigevm; /*signal field EVM*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_antc : 3; /*@8812A: 3'b0 8814A: antidx_antc[2:0]*/ + u8 antidx_antd : 3; /*@8812A: 3'b0 8814A: antidx_antd[2:0]*/ + u8 dpdt_ctrl_keep : 1; /*@8812A: 1'b0 8814A: dpdt_ctrl_keep*/ + u8 GNT_BT_keep : 1; /*@8812A: 1'b0 8814A: GNT_BT_keep*/ +#else /*@_BIG_ENDIAN_*/ + u8 GNT_BT_keep : 1; + u8 dpdt_ctrl_keep : 1; + u8 antidx_antd : 3; + u8 antidx_antc : 3; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_anta : 3; /*@antidx_anta[2:0]*/ + u8 antidx_antb : 3; /*@antidx_antb[2:0]*/ + u8 hw_antsw_occur : 2; /*@1'b0*/ +#else /*@_BIG_ENDIAN_*/ + u8 hw_antsw_occur : 2; + u8 antidx_antb : 3; + u8 antidx_anta : 3; +#endif +}; + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + +__PACK struct phy_status_rpt_jaguar2_type0 { + /* @DW0 */ + u8 page_num; + u8 pwdb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain : 6; + u8 rsvd_0 : 1; + u8 trsw : 1; +#else + u8 trsw : 1; + u8 rsvd_0 : 1; + u8 gain : 6; +#endif + u8 rsvd_1; + + /* @DW1 */ + u8 rsvd_2; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rxsc : 4; + u8 agc_table : 4; +#else + u8 agc_table : 4; + u8 rxsc : 4; +#endif + u8 channel; + u8 band; + + /* @DW2 */ + u16 length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 3; + u8 antidx_b : 3; + u8 rsvd_3 : 2; + u8 antidx_c : 3; + u8 antidx_d : 3; + u8 rsvd_4 : 2; +#else + u8 rsvd_3 : 2; + u8 antidx_b : 3; + u8 antidx_a : 3; + u8 rsvd_4 : 2; + u8 antidx_d : 3; + u8 antidx_c : 3; +#endif + + /* @DW3 */ + u8 signal_quality; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga : 5; + u8 lna_l : 3; + u8 bb_power : 6; + u8 rsvd_9 : 1; + u8 lna_h : 1; +#else + u8 lna_l : 3; + u8 vga : 5; + u8 lna_h : 1; + u8 rsvd_9 : 1; + u8 bb_power : 6; +#endif + u8 rsvd_5; + + /* @DW4 */ + u32 rsvd_6; + + /* @DW5 */ + u32 rsvd_7; + + /* @DW6 */ + u32 rsvd_8; +}; + +__PACK struct phy_status_rpt_jaguar2_type1 { + /* @DW0 and DW1 */ + u8 page_num; + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 1; + u8 hw_antsw_occu : 1; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 hw_antsw_occu : 1; + u8 rsvd_0 : 1; + u8 band : 2; +#endif + + /* @DW2 */ + u16 lsig_length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 3; + u8 antidx_b : 3; + u8 rsvd_1 : 2; + u8 antidx_c : 3; + u8 antidx_d : 3; + u8 rsvd_2 : 2; +#else + u8 rsvd_1 : 2; + u8 antidx_b : 3; + u8 antidx_a : 3; + u8 rsvd_2 : 2; + u8 antidx_d : 3; + u8 antidx_c : 3; +#endif + + /* @DW3 */ + u8 paid; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 paid_msb : 1; + u8 gid : 6; + u8 rsvd_3 : 1; +#else + u8 rsvd_3 : 1; + u8 gid : 6; + u8 paid_msb : 1; +#endif + u8 intf_pos; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 intf_pos_msb : 1; + u8 rsvd_4 : 2; + u8 nb_intf_flag : 1; + u8 rf_mode : 2; + u8 rsvd_5 : 2; +#else + u8 rsvd_5 : 2; + u8 rf_mode : 2; + u8 nb_intf_flag : 1; + u8 rsvd_4 : 2; + u8 intf_pos_msb : 1; +#endif + + /* @DW4 */ + s8 rxevm[4]; /* s(8,1) */ + + /* @DW5 */ + s8 cfo_tail[4]; /* s(8,7) */ + + /* @DW6 */ + s8 rxsnr[4]; /* s(8,1) */ +}; + +__PACK struct phy_status_rpt_jaguar2_type2 { + /* @DW0 ane DW1 */ + u8 page_num; + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 1; + u8 hw_antsw_occu : 1; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 hw_antsw_occu : 1; + u8 rsvd_0 : 1; + u8 band : 2; +#endif + +/* @DW2 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 shift_l_map : 6; + u8 rsvd_1 : 2; +#else + u8 rsvd_1 : 2; + u8 shift_l_map : 6; +#endif + u8 cnt_pw2cca; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_a : 4; + u8 agc_table_b : 4; + u8 agc_table_c : 4; + u8 agc_table_d : 4; +#else + u8 agc_table_b : 4; + u8 agc_table_a : 4; + u8 agc_table_d : 4; + u8 agc_table_c : 4; +#endif + + /* @DW3 ~ DW6*/ + u8 cnt_cca2agc_rdy; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_a : 6; + u8 rsvd_2 : 1; + u8 trsw_a : 1; + u8 gain_b : 6; + u8 rsvd_3 : 1; + u8 trsw_b : 1; + u8 gain_c : 6; + u8 rsvd_4 : 1; + u8 trsw_c : 1; + u8 gain_d : 6; + u8 rsvd_5 : 1; + u8 trsw_d : 1; + u8 aagc_step_a : 2; + u8 aagc_step_b : 2; + u8 aagc_step_c : 2; + u8 aagc_step_d : 2; +#else + u8 trsw_a : 1; + u8 rsvd_2 : 1; + u8 gain_a : 6; + u8 trsw_b : 1; + u8 rsvd_3 : 1; + u8 gain_b : 6; + u8 trsw_c : 1; + u8 rsvd_4 : 1; + u8 gain_c : 6; + u8 trsw_d : 1; + u8 rsvd_5 : 1; + u8 gain_d : 6; + u8 aagc_step_d : 2; + u8 aagc_step_c : 2; + u8 aagc_step_b : 2; + u8 aagc_step_a : 2; +#endif + u8 ht_aagc_gain[4]; + u8 dagc_gain[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 counter : 6; + u8 rsvd_6 : 2; + u8 syn_count : 5; + u8 rsvd_7 : 3; +#else + u8 rsvd_6 : 2; + u8 counter : 6; + u8 rsvd_7 : 3; + u8 syn_count : 5; +#endif +}; +#endif + +/*@==============================================*/ +#ifdef PHYSTS_3RD_TYPE_SUPPORT +__PACK struct phy_status_rpt_jaguar3_type0 { +/* @DW0 : Offset 0 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num : 4; + u8 pkt_cnt : 2; + u8 channel_msb : 2; +#else + u8 channel_msb : 2; + u8 pkt_cnt : 2; + u8 page_num : 4; +#endif + u8 pwdb_a; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_a : 6; + u8 rsvd_0 : 1; + u8 trsw : 1; +#else + u8 trsw : 1; + u8 rsvd_0 : 1; + u8 gain_a : 6; +#endif + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_b : 4; + u8 agc_table_c : 4; +#else + u8 agc_table_c : 4; + u8 agc_table_b : 4; +#endif + +/* @DW1 : Offset 4 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rsvd_1 : 4; + u8 agc_table_d : 4; +#else + u8 agc_table_d : 4; + u8 rsvd_1 : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 agc_table_a : 4; +#else + u8 agc_table_a : 4; + u8 l_rxsc : 4; +#endif + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_2_1 : 1; + u8 hw_antsw_occur_keep_cck : 1; + u8 gnt_bt_keep_cck : 1; + u8 rsvd_2_2 : 1; + u8 path_sel_o : 2; +#else + u8 path_sel_o : 2; + u8 rsvd_2_2 : 1; + u8 gnt_bt_keep_cck : 1; + u8 hw_antsw_occur_keep_cck : 1; + u8 rsvd_2_1 : 1; + u8 band : 2; +#endif + + /* @DW2 : Offset 8 */ + u16 length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 4; + u8 antidx_b : 4; +#else + u8 antidx_b : 4; + u8 antidx_a : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_c : 4; + u8 antidx_d : 4; +#else + u8 antidx_d : 4; + u8 antidx_c : 4; +#endif + + /* @DW3 : Offset 12 */ + u8 signal_quality; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_a : 5; + u8 lna_l_a : 3; +#else + u8 lna_l_a : 3; + u8 vga_a : 5; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bb_power_a : 6; + u8 rsvd_3_1 : 1; + u8 lna_h_a : 1; +#else + + u8 lna_h_a : 1; + u8 rsvd_3_1 : 1; + u8 bb_power_a : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rxrate : 2; + u8 raterr : 1; + u8 lockbit : 1; + u8 sqloss : 1; + u8 mf_off : 1; + u8 rsvd_3_2 : 2; +#else + u8 rsvd_3_2 : 2; + u8 mf_off : 1; + u8 sqloss : 1; + u8 lockbit : 1; + u8 raterr : 1; + u8 rxrate : 2; +#endif + + /* @DW4 : Offset 16 */ + u8 pwdb_b; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_b : 5; + u8 lna_l_b : 3; +#else + u8 lna_l_b : 3; + u8 vga_b : 5; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bb_power_b : 6; + u8 rsvd_4_1 : 1; + u8 lna_h_b : 1; +#else + u8 lna_h_b : 1; + u8 rsvd_4_1 : 1; + u8 bb_power_b : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_b : 6; + u8 rsvd_4_2 : 2; +#else + u8 rsvd_4_2 : 2; + u8 gain_b : 6; +#endif + + /* @DW5 : Offset 20 */ + u8 pwdb_c; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_c : 5; + u8 lna_l_c : 3; +#else + u8 lna_l_c : 3; + u8 vga_c : 5; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bb_power_c : 6; + u8 rsvd_5_1 : 1; + u8 lna_h_c : 1; +#else + u8 lna_h_c : 1; + u8 rsvd_5_1 : 1; + u8 bb_power_c : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_c : 6; + u8 rsvd_5_2 : 2; +#else + u8 rsvd_5_2 : 2; + u8 gain_c : 6; +#endif + + /* @DW6 : Offset 24 */ + u8 pwdb_d; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_d : 5; + u8 lna_l_d : 3; +#else + u8 lna_l_d : 3; + u8 vga_d : 5; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bb_power_d : 6; + u8 rsvd_6_1 : 1; + u8 lna_h_d : 1; +#else + u8 lna_h_d : 1; + u8 rsvd_6_1 : 1; + u8 bb_power_d : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_d : 6; + u8 rsvd_6_2 : 2; +#else + u8 rsvd_6_2 : 2; + u8 gain_d : 6; +#endif +}; + +__PACK struct phy_status_rpt_jaguar3_type1 { +/* @DW0 : Offset 0 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num : 4; + u8 pkt_cnt : 2; + u8 channel_pri_msb : 2; +#else + u8 channel_pri_msb : 2; + u8 pkt_cnt : 2; + u8 page_num : 4; +#endif + u8 pwdb_a; + u8 pwdb_b; + u8 pwdb_c; + + /* @DW1 : Offset 4 */ + u8 pwdb_d; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel_pri_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 2; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 rsvd_0 : 2; + u8 band : 2; +#endif + + /* @DW2 : Offset 8 */ + u8 channel_sec_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 channel_sec_msb : 2; + u8 rsvd_1 : 2; + u8 hw_antsw_occur_a : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_d : 1; +#else + u8 hw_antsw_occur_d : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_a : 1; + u8 rsvd_1 : 2; + u8 channel_sec_msb : 2; + +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 4; + u8 antidx_b : 4; +#else + u8 antidx_b : 4; + u8 antidx_a : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_c : 4; + u8 antidx_d : 4; +#else + u8 antidx_d : 4; + u8 antidx_c : 4; +#endif + + /* @DW3 : Offset 12 */ + u8 paid; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 paid_msb : 1; + u8 gid : 6; + u8 rsvd_3 : 1; +#else + u8 rsvd_3 : 1; + u8 gid : 6; + u8 paid_msb : 1; +#endif + u16 rsvd_4; +#if 0 + /*@ + u8 rsvd_4; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rsvd_5: 6; + u8 rf_mode: 2; +#else + u8 rf_mode: 2; + u8 rsvd_5: 6; +#endif +*/ +#endif + /* @DW4 : Offset 16 */ + s8 rxevm[4]; /* s(8,1) */ + + /* @DW5 : Offset 20 */ + s8 cfo_tail[4]; /* s(8,7) */ + + /* @DW6 : Offset 24 */ + s8 rxsnr[4]; /* s(8,1) */ +}; + +__PACK struct phy_status_rpt_jaguar3_type2_type3 { +/* Type2 is primary channel & type3 is secondary channel */ +/* @DW0 and DW1: Offest 0 and Offset 4 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num : 4; + u8 pkt_cnt : 2; + u8 channel_msb : 2; +#else + u8 channel_msb : 2; + u8 pkt_cnt : 2; + u8 page_num : 4; +#endif + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 2; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 rsvd_0 : 2; + u8 band : 2; +#endif + +/* @DW2 : Offset 8 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 shift_l_map : 6; + u8 rsvd_1 : 2; +#else + u8 rsvd_1 : 2; + u8 shift_l_map : 6; +#endif + s8 pwed_th; /* @dynamic energy threshold S(8,2) */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_a : 4; + u8 agc_table_b : 4; +#else + u8 agc_table_b : 4; + u8 agc_table_a : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_c : 4; + u8 agc_table_d : 4; +#else + u8 agc_table_d : 4; + u8 agc_table_c : 4; +#endif + + /* @DW3 : Offset 12 */ + u8 cnt_cca2agc_rdy; /* Time(ns) = cnt_cca2agc_ready*25 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 mp_gain_a : 6; + u8 mp_gain_b_lsb : 2; +#else + u8 mp_gain_b_lsb : 2; + u8 mp_gain_a : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 mp_gain_b_msb : 4; + u8 mp_gain_c_lsb : 4; +#else + u8 mp_gain_c_lsb : 4; + u8 mp_gain_b_msb : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 mp_gain_c_msb : 2; + u8 avg_noise_pwr_lsb : 4; + u8 rsvd_3 : 2; + /* u8 r_rfmod:2; */ +#else + /* u8 r_rfmod:2; */ + u8 rsvd_3 : 2; + u8 avg_noise_pwr_lsb : 4; + u8 mp_gain_c_msb : 2; +#endif + /* @DW4 ~ 5: offset 16 ~20 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 mp_gain_d : 6; + u8 is_freq_select_fading : 1; + u8 rsvd_2 : 1; +#else + u8 rsvd_2 : 1; + u8 is_freq_select_fading : 1; + u8 mp_gain_d : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 aagc_step_a : 2; + u8 aagc_step_b : 2; + u8 aagc_step_c : 2; + u8 aagc_step_d : 2; +#else + u8 aagc_step_d : 2; + u8 aagc_step_c : 2; + u8 aagc_step_b : 2; + u8 aagc_step_a : 2; +#endif + u8 ht_aagc_gain[4]; + u8 dagc_gain[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 counter : 6; + u8 syn_count_lsb : 2; +#else + u8 syn_count_lsb : 2; + u8 counter : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 syn_count_msb : 3; + u8 avg_noise_pwr_msb : 5; +#else + u8 avg_noise_pwr_msb : 5; + u8 syn_count_msb : 3; +#endif +}; + +__PACK struct phy_status_rpt_jaguar3_type4 { +/* smart antenna */ +/* @DW0 and DW1 : offset 0 and 4 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num : 4; + u8 pkt_cnt : 2; + u8 channel_msb : 2; +#else + u8 channel_msb : 2; + u8 pkt_cnt : 2; + u8 page_num : 4; +#endif + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 2; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 rsvd_0 : 1; + u8 band : 2; +#endif + +/* @DW2 : offset 8 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bad_tone_cnt_min_eign_0 : 4; + u8 bad_tone_cnt_cn_excess_0 : 4; +#else + u8 bad_tone_cnt_cn_excess_0 : 4; + u8 bad_tone_cnt_min_eign_0 : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 training_done_a : 1; + u8 training_done_b : 1; + u8 training_done_c : 1; + u8 training_done_d : 1; + u8 hw_antsw_occur_a : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_d : 1; +#else + u8 hw_antsw_occur_d : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_a : 1; + u8 training_done_d : 1; + u8 training_done_c : 1; + u8 training_done_b : 1; + u8 training_done_a : 1; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 4; + u8 antidx_b : 4; +#else + u8 antidx_b : 4; + u8 antidx_a : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_c : 4; + u8 antidx_d : 4; +#else + u8 antidx_d : 4; + u8 antidx_c : 4; +#endif +/* @DW3 : offset 12 */ + u8 tx_pkt_cnt; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bad_tone_cnt_min_eign_1 : 4; + u8 bad_tone_cnt_cn_excess_1 : 4; +#else + u8 bad_tone_cnt_cn_excess_1 : 4; + u8 bad_tone_cnt_min_eign_1 : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 avg_cond_num_0 : 7; + u8 avg_cond_num_1_lsb : 1; +#else + u8 avg_cond_num_1_lsb : 1; + u8 avg_cond_num_0 : 7; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 avg_cond_num_1_msb : 6; + u8 rsvd_1 : 2; +#else + u8 rsvd_1 : 2; + u8 avg_cond_num_1_msb : 6; +#endif + + /* @DW4 : offset 16 */ + s8 rxevm[4]; /* s(8,1) */ + + /* @DW5 : offset 20 */ + u8 eigenvalue[4]; /* @eigenvalue or eigenvalue of seg0 (in dB) */ + + /* @DW6 : ofset 24 */ + s8 rxsnr[4]; /* s(8,1) */ +}; + +__PACK struct phy_status_rpt_jaguar3_type5 { +/* @Debug */ +/* @DW0 ane DW1 : offset 0 and 4 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num : 4; + u8 pkt_cnt : 2; + u8 channel_msb : 2; +#else + u8 channel_msb : 2; + u8 pkt_cnt : 2; + u8 page_num : 4; +#endif + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 2; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 rsvd_0 : 2; + u8 band : 2; +#endif + /* @DW2 : offset 8 */ + u8 rsvd_1; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rsvd_2 : 4; + u8 hw_antsw_occur_a : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_d : 1; +#else + u8 hw_antsw_occur_d : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_a : 1; + u8 rsvd_2 : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 4; + u8 antidx_b : 4; +#else + u8 antidx_b : 4; + u8 antidx_a : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_c : 4; + u8 antidx_d : 4; +#else + u8 antidx_d : 4; + u8 antidx_c : 4; +#endif + /* @DW3 : offset 12 */ + u8 tx_pkt_cnt; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 inf_pos_0_A_flg : 1; + u8 inf_pos_1_A_flg : 1; + u8 inf_pos_0_B_flg : 1; + u8 inf_pos_1_B_flg : 1; + u8 inf_pos_0_C_flg : 1; + u8 inf_pos_1_C_flg : 1; + u8 inf_pos_0_D_flg : 1; + u8 inf_pos_1_D_flg : 1; +#else + u8 inf_pos_1_D_flg : 1; + u8 inf_pos_0_D_flg : 1; + u8 inf_pos_1_C_flg : 1; + u8 inf_pos_0_C_flg : 1; + u8 inf_pos_1_B_flg : 1; + u8 inf_pos_0_B_flg : 1; + u8 inf_pos_1_A_flg : 1; + u8 inf_pos_0_A_flg : 1; +#endif + u8 rsvd_3; + u8 rsvd_4; + /* @DW4 : offset 16 */ + u8 inf_pos_0_a; + u8 inf_pos_1_a; + u8 inf_pos_0_b; + u8 inf_pos_1_b; + /* @DW5 : offset 20 */ + u8 inf_pos_0_c; + u8 inf_pos_1_c; + u8 inf_pos_0_d; + u8 inf_pos_1_d; +}; +#endif /*@#ifdef PHYSTS_3RD_TYPE_SUPPORT*/ + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) +boolean +phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate, + u8 *p_gid); +#endif + +#ifdef PHYSTS_3RD_TYPE_SUPPORT +void phydm_rx_physts_3rd_type(void *dm_void, u8 *phy_sts, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info); +#endif + +void phydm_reset_phystatus_avg(struct dm_struct *dm); + +void phydm_reset_phystatus_statistic(struct dm_struct *dm); + +void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id); + +void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_normal_driver_rx_sniffer( + struct dm_struct *dm, + u8 *desc, + PRT_RFD_STATUS rt_rfd_status, + u8 *drv_info, + u8 phy_status); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +s32 phydm_signal_scale_mapping(struct dm_struct *dm, s32 curr_sig); +#endif + +void odm_phy_status_query(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo); + +void phydm_rx_phy_status_init(void *dm_void); + +#endif /*@#ifndef __HALHWOUTSRC_H__*/ diff --git a/hal/phydm/phydm_pmac_tx_setting.c b/hal/phydm/phydm_pmac_tx_setting.c new file mode 100644 index 0000000..9aade53 --- /dev/null +++ b/hal/phydm/phydm_pmac_tx_setting.c @@ -0,0 +1,522 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + +void phydm_start_cck_cont_tx_jgr3(void *dm_void, + struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u8 rate = tx_info->tx_rate; /* @HW rate */ + + /* @if CCK block on? */ + if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1))) + odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1); + + /* @Turn Off All Test mode */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0); + + odm_set_bb_reg(dm, R_0x1a00, 0x3000, rate); + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* @transmit mode */ + odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1); /* @turn on scramble setting */ + + /* @Fix rate selection issue */ + odm_set_bb_reg(dm, R_0x1a70, 0x4000, 0x1); + /* @set RX weighting for path I & Q to 0 */ + odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3); + /* @set loopback mode */ + odm_set_bb_reg(dm, R_0x1c3c, 0x10, 0x1); + + pmac_tx->cck_cont_tx = true; + pmac_tx->ofdm_cont_tx = false; +} + +void phydm_stop_cck_cont_tx_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + pmac_tx->cck_cont_tx = false; + pmac_tx->ofdm_cont_tx = false; + + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* @normal mode */ + odm_set_bb_reg(dm, R_0x1a00, 0x8, 0x1); /* @turn on scramble setting */ + + /* @back to default */ + odm_set_bb_reg(dm, R_0x1a70, 0x4000, 0x0); + odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0); + odm_set_bb_reg(dm, R_0x1c3c, 0x10, 0x0); + /* @BB Reset */ + odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0); + odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1); +} + +void phydm_start_ofdm_cont_tx_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + /* @1. if OFDM block on */ + if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0))) + odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1); + + /* @2. set CCK test mode off, set to CCK normal mode */ + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0); + + /* @3. turn on scramble setting */ + odm_set_bb_reg(dm, R_0x1a00, 0x8, 1); + + /* @4. Turn On Continue Tx and turn off the other test modes. */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1); + + pmac_tx->cck_cont_tx = false; + pmac_tx->ofdm_cont_tx = true; +} + +void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + pmac_tx->cck_cont_tx = false; + pmac_tx->ofdm_cont_tx = false; + + /* @Turn Off All Test mode */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0); + + /* @Delay 10 ms */ + ODM_delay_ms(10); + + /* @BB Reset */ + odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x0); + odm_set_bb_reg(dm, R_0x1d0c, 0x10000, 0x1); +} + +void phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone, + boolean en_pmac_tx, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u8 start = RF_PATH_A, end = RF_PATH_A; + + switch (path) { + case RF_PATH_A: + case RF_PATH_B: + case RF_PATH_C: + case RF_PATH_D: + start = path; + end = path; + break; + case RF_PATH_AB: + start = RF_PATH_A; + end = RF_PATH_B; + break; + case RF_PATH_BC: + start = RF_PATH_B; + end = RF_PATH_C; + break; + case RF_PATH_ABC: + start = RF_PATH_A; + end = RF_PATH_C; + break; + case RF_PATH_BCD: + start = RF_PATH_B; + end = RF_PATH_D; + break; + case RF_PATH_ABCD: + start = RF_PATH_A; + end = RF_PATH_D; + break; + } + + if (is_single_tone) { + pmac_tx->tx_scailing = odm_get_bb_reg(dm, R_0x81c, MASKDWORD); + + if (!en_pmac_tx) { + phydm_start_ofdm_cont_tx_jgr3(dm); + /*SendPSPoll(pAdapter);*/ + } + + odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x1); /* @Disable CCA */ + + if (!(dm->support_ic_type & ODM_RTL8814B)) { + for (start; start <= end; start++) { + /* @Tx mode: RF0x00[19:16]=4'b0010 */ + odm_set_rf_reg(dm, start, RF_0x0, 0xF0000, 0x2); + /* @Lowest RF gain index: RF_0x0[4:0] = 0*/ + odm_set_rf_reg(dm, start, RF_0x0, 0x1F, 0x0); + /* @RF LO enabled */ + odm_set_rf_reg(dm, start, RF_0x58, BIT(1), 0x1); + } + } + odm_set_bb_reg(dm, R_0x81c, 0x001FC000, 0); + } else { + for (start; start <= end; start++) + /* @RF LO disabled */ + if (!(dm->support_ic_type & ODM_RTL8814B)) + odm_set_rf_reg(dm, start, RF_0x58, BIT(1), 0x0); + + odm_set_bb_reg(dm, R_0x1c68, BIT(24), 0x0); /* @Enable CCA */ + + if (!en_pmac_tx) + phydm_stop_ofdm_cont_tx_jgr3(dm); + + odm_set_bb_reg(dm, R_0x81c, MASKDWORD, pmac_tx->tx_scailing); + } +} + +void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u32 tmp = 0; + + if (tx_info->mode == CONT_TX) { + odm_set_bb_reg(dm, R_0x1e70, 0xf, 2); /* TX Stop */ + if (pmac_tx->is_cck_rate) + phydm_stop_cck_cont_tx_jgr3(dm); + else + phydm_stop_ofdm_cont_tx_jgr3(dm); + } else { + if (pmac_tx->is_cck_rate) { + tmp = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD); + odm_set_bb_reg(dm, R_0x1e64, MASKLWORD, tmp + 50); + } + odm_set_bb_reg(dm, R_0x1e70, 0xf, 2); /* TX Stop */ + } + + if (tx_info->mode == OFDM_SINGLE_TONE_TX) { + /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting */ + if (pmac_tx->is_cck_rate) + phydm_stop_cck_cont_tx_jgr3(dm); + else + phydm_stop_ofdm_cont_tx_jgr3(dm); + + phydm_set_single_tone_jgr3(dm, false, true, pmac_tx->path); + } +} + +void phydm_set_mac_phy_txinfo_jgr3(void *dm_void, + struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u32 tmp = 0; + + odm_set_bb_reg(dm, R_0xa58, 0x003F8000, tx_info->tx_rate); + + /* @0x900[1] ndp_sound */ + odm_set_bb_reg(dm, R_0x900, 0x2, tx_info->ndp_sound); + /* @0x900[27:24] txsc [29:28] bw [31:30] m_stbc */ + tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) | + ((tx_info->m_stbc - 1) << 6); + odm_set_bb_reg(dm, R_0x900, 0xFF000000, tmp); + + if (pmac_tx->is_ofdm_rate) { + odm_set_bb_reg(dm, R_0x900, 0x1, 0); + odm_set_bb_reg(dm, R_0x900, 0x4, 0); + } else if (pmac_tx->is_ht_rate) { + odm_set_bb_reg(dm, R_0x900, 0x1, 1); + odm_set_bb_reg(dm, R_0x900, 0x4, 0); + } else if (pmac_tx->is_vht_rate) { + odm_set_bb_reg(dm, R_0x900, 0x1, 0); + odm_set_bb_reg(dm, R_0x900, 0x4, 1); + } + + tmp = tx_info->packet_period; /* @for TX interval */ + odm_set_bb_reg(dm, R_0x9b8, 0xffff0000, tmp); +} + +void phydm_set_mac_hdr_jgr3(void *dm_void, struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u32 tmp = 0; + u32 tmp1 = 0; + + if (pmac_tx->is_vht_rate) { + tmp = BYTE_2_DWORD(tx_info->vht_delimiter[3], + tx_info->vht_delimiter[2], + tx_info->vht_delimiter[1], + tx_info->vht_delimiter[0]); + odm_set_bb_reg(dm, R_0x950, MASKDWORD, tmp); + + /* 0x954 - 0x960 24 byte Probe Request MAC Header */ + /* & Duration & Frame control */ + odm_set_bb_reg(dm, R_0x954, MASKDWORD, 0x00000040); + + /* MAC_Addr1[5:0] , the value has no meaning */ + tmp = BYTE_2_DWORD(0x33, 0x22, 0x11, 0x00); + tmp1 = BYTE_2_DWORD(0, 0, 0x55, 0x44); + odm_set_bb_reg(dm, R_0x958, MASKDWORD, tmp); + odm_set_bb_reg(dm, R_0x95c, 0xffff, tmp1); + + /* MAC_Addr3[3:0], [5:4] drop for DD design*/ + odm_set_bb_reg(dm, R_0x964, MASKDWORD, tmp); + + /* MAC_Addr2[5:0] */ + tmp = BYTE_2_DWORD(0, 0, 0x11, 0x00); + tmp1 = BYTE_2_DWORD(0x55, 0x44, 0x33, 0x22); + odm_set_bb_reg(dm, R_0x95c, 0xffff0000, tmp); + odm_set_bb_reg(dm, R_0x960, MASKDWORD, tmp1); + + } else { + /* 0x950 - 0x964 24 byte Probe Request MAC Header */ + /* & Duration & Frame control */ + odm_set_bb_reg(dm, R_0x950, MASKDWORD, 0x00000040); + + /* MAC_Addr1[5:0] , the value has no meaning */ + tmp = BYTE_2_DWORD(0x33, 0x22, 0x11, 0x00); + tmp1 = BYTE_2_DWORD(0, 0, 0x55, 0x44); + odm_set_bb_reg(dm, R_0x954, MASKDWORD, tmp); + odm_set_bb_reg(dm, R_0x958, 0xffff, tmp1); + + /* Sequence Control & Address3[5:0] */ + odm_set_bb_reg(dm, R_0x960, MASKDWORD, tmp); + odm_set_bb_reg(dm, R_0x964, MASKDWORD, tmp1); + + /* MAC_Addr2[5:0] */ + tmp = BYTE_2_DWORD(0, 0, 0x11, 0x00); + tmp1 = BYTE_2_DWORD(0x55, 0x44, 0x33, 0x22); + odm_set_bb_reg(dm, R_0x958, 0xffff0000, tmp); + odm_set_bb_reg(dm, R_0x95c, MASKDWORD, tmp1); + } +} + +void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u32 tmp = 0; + + if (pmac_tx->is_cck_rate) + return; + + /* @L-SIG */ + odm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count); + + tmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1], + tx_info->lsig[0]); + odm_set_bb_reg(dm, R_0x908, 0xffffff, tmp); + + /* @0x924[7:0] = Data init octet */ + tmp = tx_info->packet_pattern; + odm_set_bb_reg(dm, R_0x924, 0xff, tmp); + + if (tx_info->packet_pattern == RANDOM_BY_PN32) + tmp = 0x3; + else + tmp = 0; + + odm_set_bb_reg(dm, R_0x914, 0xE0000000, tmp); + + if (pmac_tx->is_ht_rate) { + /* @HT SIG */ + tmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1], + tx_info->ht_sig[0]); + odm_set_bb_reg(dm, 0x90c, 0xffffff, tmp); + tmp = BYTE_2_DWORD(0, tx_info->ht_sig[5], tx_info->ht_sig[4], + tx_info->ht_sig[3]); + odm_set_bb_reg(dm, 0x910, 0xffffff, tmp); + } else if (pmac_tx->is_vht_rate) { + /* @VHT SIG A/B/serv_field */ + tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2], + tx_info->vht_sig_a[1], + tx_info->vht_sig_a[0]); + odm_set_bb_reg(dm, 0x90c, 0xffffff, tmp); + tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[5], + tx_info->vht_sig_a[4], + tx_info->vht_sig_a[3]); + odm_set_bb_reg(dm, 0x910, 0xffffff, tmp); + tmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2], + tx_info->vht_sig_b[1], + tx_info->vht_sig_b[0]); + odm_set_bb_reg(dm, 0x914, 0x1FFFFFFF, tmp); + + tmp = tx_info->vht_sig_b_crc << 8; + odm_set_bb_reg(dm, R_0x938, 0xffff, tmp); + } +} + +void phydm_set_cck_preamble_hdr_jgr3(void *dm_void, + struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u32 tmp = 0; + + if (!pmac_tx->is_cck_rate) + return; + + tmp = tx_info->packet_count | (tx_info->sfd << 16); + odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp); + tmp = tx_info->signal_field | (tx_info->service_field << 8) | + (tx_info->length << 16); + odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp); + tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]); + odm_set_bb_reg(dm, R_0x1e6c, 0xffff, tmp); + + if (tx_info->is_short_preamble) + odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0); + else + odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 1); +} + +void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info, + enum phydm_pmac_mode mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + if (mode == CONT_TX) { + tx_info->packet_count = 1; + + if (pmac_tx->is_cck_rate) + phydm_start_cck_cont_tx_jgr3(dm, tx_info); + else + phydm_start_ofdm_cont_tx_jgr3(dm); + } else if (mode == OFDM_SINGLE_TONE_TX) { + /* Continuous TX -> HW TX -> RF Setting */ + tx_info->packet_count = 1; + + if (pmac_tx->is_cck_rate) + phydm_start_cck_cont_tx_jgr3(dm, tx_info); + else + phydm_start_ofdm_cont_tx_jgr3(dm); + } else if (mode == PKTS_TX) { + if (pmac_tx->is_cck_rate && tx_info->packet_count == 0) + tx_info->packet_count = 0xffff; + } +} + +void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + odm_set_bb_reg(dm, R_0x1d08, BIT(0), 1); /* Turn on PMAC */ + + if (pmac_tx->is_cck_rate) { + odm_set_bb_reg(dm, R_0x1e70, 0xf, 8); /* TX CCK ON */ + odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0); + } else { + odm_set_bb_reg(dm, R_0x1e70, 0xf, 4); /* TX Ofdm ON */ + } + + if (tx_info->mode == OFDM_SINGLE_TONE_TX) + phydm_set_single_tone_jgr3(dm, true, true, pmac_tx->path); +} + +void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info, + enum rf_path mpt_rf_path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + pmac_tx->is_cck_rate = phydm_is_cck_rate(dm, tx_info->tx_rate); + pmac_tx->is_ofdm_rate = phydm_is_ofdm_rate(dm, tx_info->tx_rate); + pmac_tx->is_ht_rate = phydm_is_ht_rate(dm, tx_info->tx_rate); + pmac_tx->is_vht_rate = phydm_is_vht_rate(dm, tx_info->tx_rate); + pmac_tx->path = mpt_rf_path; + + if (!tx_info->en_pmac_tx) { + phydm_stop_pmac_tx_jgr3(dm, tx_info); + return; + } + + phydm_set_mode_jgr3(dm, tx_info, tx_info->mode); + + if (pmac_tx->is_cck_rate) + phydm_set_cck_preamble_hdr_jgr3(dm, tx_info); + else + phydm_set_sig_jgr3(dm, tx_info); + + phydm_set_mac_phy_txinfo_jgr3(dm, tx_info); + phydm_set_mac_hdr_jgr3(dm, tx_info); + phydm_set_pmac_txon_jgr3(dm, tx_info); +} +#endif + +void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_start_cck_cont_tx_jgr3(dm, tx_info); +} + +void phydm_stop_cck_cont_tx(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_stop_cck_cont_tx_jgr3(dm); +} + +void phydm_start_ofdm_cont_tx(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_start_ofdm_cont_tx_jgr3(dm); +} + +void phydm_stop_ofdm_cont_tx(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_stop_ofdm_cont_tx_jgr3(dm); +} + +void phydm_set_single_tone(void *dm_void, boolean is_single_tone, + boolean en_pmac_tx, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_set_single_tone_jgr3(dm, is_single_tone, + en_pmac_tx, path); +} + +void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info, + enum rf_path mpt_rf_path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path); +} + +#endif diff --git a/hal/phydm/phydm_pmac_tx_setting.h b/hal/phydm/phydm_pmac_tx_setting.h new file mode 100644 index 0000000..9568c91 --- /dev/null +++ b/hal/phydm/phydm_pmac_tx_setting.h @@ -0,0 +1,149 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_PMAC_TX_SETTING_H__ +#define __PHYDM_PMAC_TX_SETTING_H__ + +#define PMAC_TX_SETTING_VERSION "1.0" + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ +#define RANDOM_BY_PN32 0x12 +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ +struct phydm_pmac_info { + u8 en_pmac_tx:1; /*@ disable pmac 1: enable pmac */ + u8 mode:3; /*@ 0: Packet TX 3:Continuous TX */ + /* @u8 Ntx:4; */ + u8 tx_rate; /* @should be HW rate*/ + /* @u8 TX_RATE_HEX; */ + u8 tx_sc; + /* @u8 bSGI:1; */ + u8 is_short_preamble:1; + /* @u8 bSTBC:1; */ + /* @u8 bLDPC:1; */ + u8 ndp_sound:1; + u8 bw:3; /* @0:20 1:40 2:80Mhz */ + u8 m_stbc; /* @bSTBC + 1 */ + u16 packet_period; + u32 packet_count; + /* @u32 PacketLength; */ + u8 packet_pattern; + u16 sfd; + u8 signal_field; + u8 service_field; + u16 length; + u8 crc16[2]; + u8 lsig[3]; + u8 ht_sig[6]; + u8 vht_sig_a[6]; + u8 vht_sig_b[4]; + u8 vht_sig_b_crc; + u8 vht_delimiter[4]; + /* @u8 mac_addr[6]; */ +}; + +struct phydm_pmac_tx { + boolean is_cck_rate; + boolean is_ofdm_rate; + boolean is_ht_rate; + boolean is_vht_rate; + boolean cck_cont_tx; + boolean ofdm_cont_tx; + u8 path; + u32 tx_scailing; +}; + +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +enum phydm_pmac_mode { + NONE_TEST, + PKTS_TX, + PKTS_RX, + CONT_TX, + OFDM_SINGLE_TONE_TX, + CCK_CARRIER_SIPPRESSION_TX +}; + +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_start_cck_cont_tx_jgr3(void *dm_void, + struct phydm_pmac_info *tx_info); + +void phydm_stop_cck_cont_tx_jgr3(void *dm_void); + +void phydm_start_ofdm_cont_tx_jgr3(void *dm_void); + +void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void); + +void phydm_set_single_tone_jgr3(void *dm_void, boolean is_single_tone, + boolean en_pmac_tx, u8 path); + +void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info); + +void phydm_set_mac_phy_txinfo_jgr3(void *dm_void, + struct phydm_pmac_info *tx_info); + +void phydm_set_mac_hdr_jgr3(void *dm_void, struct phydm_pmac_info *tx_info); + +void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info); + +void phydm_set_cck_preamble_hdr_jgr3(void *dm_void, + struct phydm_pmac_info *tx_info); + +void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info, + enum phydm_pmac_mode mode); + +void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info); + +void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info, + enum rf_path mpt_rf_path); +#endif + +void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info); + +void phydm_stop_cck_cont_tx(void *dm_void); + +void phydm_start_ofdm_cont_tx(void *dm_void); + +void phydm_stop_ofdm_cont_tx(void *dm_void); + +void phydm_set_single_tone(void *dm_void, boolean is_single_tone, + boolean en_pmac_tx, u8 path); + +void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info, + enum rf_path mpt_rf_path); + +#endif diff --git a/hal/phydm/phydm_pow_train.c b/hal/phydm/phydm_pow_train.c new file mode 100644 index 0000000..5339515 --- /dev/null +++ b/hal/phydm/phydm_pow_train.c @@ -0,0 +1,183 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_POWER_TRAINING_SUPPORT +void phydm_reset_pt_para(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table; + + pt_t->pow_train_score = 0; +} + +void phydm_update_power_training_state(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table; + struct phydm_fa_struct *fa_cnt = &dm->false_alm_cnt; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 pt_score_tmp = ENABLE_PT_SCORE; + u32 crc_ok_cnt = 0; + u32 cca_cnt = 0; + + /*@is_disable_power_training is the key to H2C to disable/enable PT*/ + /*@if is_disable_power_training == 1, it will use largest power*/ + if (!(dm->support_ability & ODM_BB_PWR_TRAIN) || !dm->is_linked) { + dm->is_disable_power_training = true; + phydm_reset_pt_para(dm); + return; + } + + PHYDM_DBG(dm, DBG_PWR_TRAIN, "%s ======>\n", __func__); + + if (pt_t->pt_state == DISABLE_POW_TRAIN) { + dm->is_disable_power_training = true; + phydm_reset_pt_para(dm); + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT\n"); + return; + + } else if (pt_t->pt_state == ENABLE_POW_TRAIN) { + dm->is_disable_power_training = false; + phydm_reset_pt_para(dm); + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable PT\n"); + return; + + } else if (pt_t->pt_state == DYNAMIC_POW_TRAIN) { + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Dynamic PT\n"); + + /* @Compute score */ + crc_ok_cnt = dm->phy_dbg_info.num_qry_phy_status_ofdm + + dm->phy_dbg_info.num_qry_phy_status_cck; + cca_cnt = fa_cnt->cnt_cca_all; +#if 0 + if (crc_ok_cnt > cca_cnt) { /*invalid situation*/ + pt_score_tmp = KEEP_PRE_PT_SCORE; + return; + } else if ((crc_ok_cnt + (crc_ok_cnt >> 1)) <= cca_cnt) { + /* @???crc_ok <= (2/3)*cca */ + pt_score_tmp = DISABLE_PT_SCORE; + dm->is_disable_power_training = true; + } else if ((crc_ok_cnt + (crc_ok_cnt >> 2)) <= cca_cnt) { + /* @???crc_ok <= (4/5)*cca */ + pt_score_tmp = KEEP_PRE_PT_SCORE; + } else { + /* @???crc_ok > (4/5)*cca */ + pt_score_tmp = ENABLE_PT_SCORE; + dm->is_disable_power_training = false; + } +#endif + if (ccx->nhm_ratio > 10) { + pt_score_tmp = DISABLE_PT_SCORE; + dm->is_disable_power_training = true; + } else if (ccx->nhm_ratio < 5) { + pt_score_tmp = ENABLE_PT_SCORE; + dm->is_disable_power_training = false; + } else { + pt_score_tmp = KEEP_PRE_PT_SCORE; + } + + PHYDM_DBG(dm, DBG_PWR_TRAIN, + "pkt_cnt{ofdm,cck,all} = {%d, %d, %d}, cnt_cca_all=%d\n", + dm->phy_dbg_info.num_qry_phy_status_ofdm, + dm->phy_dbg_info.num_qry_phy_status_cck, + crc_ok_cnt, cca_cnt); + + PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp=%d\n", pt_score_tmp); + + /* smoothing */ + pt_t->pow_train_score = (pt_score_tmp << 4) + + (pt_t->pow_train_score >> 1) + + (pt_t->pow_train_score >> 2); + + pt_score_tmp = (pt_t->pow_train_score + 32) >> 6; + + PHYDM_DBG(dm, DBG_PWR_TRAIN, + "pow_train_score = %d, score after smoothing = %d, is_disable_PT = %d\n", + pt_t->pow_train_score, pt_score_tmp, + dm->is_disable_power_training); + } else { + PHYDM_DBG(dm, DBG_PWR_TRAIN, "[%s]warning\n", __func__); + } +} + +void phydm_pow_train_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "0: Dynamic state\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "1: Enable PT\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "2: Disable PT\n"); + + } else { + for (i = 0; i < 10; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + } + + if (var1[0] == 0) { + pt_t->pt_state = DYNAMIC_POW_TRAIN; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dynamic state\n"); + } else if (var1[0] == 1) { + pt_t->pt_state = ENABLE_POW_TRAIN; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Enable PT\n"); + } else if (var1[0] == 2) { + pt_t->pt_state = DISABLE_POW_TRAIN; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable PT\n"); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set Error\n"); + } + } + + *_used = used; + *_out_len = out_len; +} + +#endif diff --git a/hal/phydm/phydm_pow_train.h b/hal/phydm/phydm_pow_train.h new file mode 100644 index 0000000..f966607 --- /dev/null +++ b/hal/phydm/phydm_pow_train.h @@ -0,0 +1,84 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_POW_TRAIN_H__ +#define __PHYDM_POW_TRAIN_H__ + +#define POW_TRAIN_VERSION "1.0" /* @2017.07.0141 Dino, Add phydm_pow_train.h*/ + +/**************************************************************** + * 1 ============================================================ + * 1 Definition + * 1 ============================================================ + ***************************************************************/ + +#ifdef PHYDM_POWER_TRAINING_SUPPORT +/**************************************************************** + * 1 ============================================================ + * 1 structure + * 1 ============================================================ + ***************************************************************/ + +struct phydm_pow_train_stuc { + u8 pt_state; + u32 pow_train_score; +}; + +/**************************************************************** + * 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + ***************************************************************/ + +enum pow_train_state { + DYNAMIC_POW_TRAIN = 0, + ENABLE_POW_TRAIN = 1, + DISABLE_POW_TRAIN = 2 +}; + +enum power_training_score { + DISABLE_PT_SCORE = 0, + KEEP_PRE_PT_SCORE = 1, + ENABLE_PT_SCORE = 2 +}; + +/**************************************************************** + * 1 ============================================================ + * 1 function prototype + * 1 ============================================================ + ***************************************************************/ + +void phydm_update_power_training_state( + void *dm_void); + +void phydm_pow_train_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len); + +#endif +#endif diff --git a/hal/phydm/phydm_pre_define.h b/hal/phydm/phydm_pre_define.h index 97b1c8e..9567254 100644 --- a/hal/phydm/phydm_pre_define.h +++ b/hal/phydm/phydm_pre_define.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,100 +8,126 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ - + * Larry Finger + * + *****************************************************************************/ -#ifndef __PHYDMPREDEFINE_H__ -#define __PHYDMPREDEFINE_H__ +#ifndef __PHYDMPREDEFINE_H__ +#define __PHYDMPREDEFINE_H__ -/* 1 ============================================================ +/**************************************************************** + * 1 ============================================================ * 1 Definition - * 1 ============================================================ */ + * 1 ============================================================ + ***************************************************************/ + +#define PHYDM_CODE_BASE "PHYDM_V030" +#define PHYDM_RELEASE_DATE "20180605.0" -#define PHYDM_CODE_BASE "PHYDM_V014" -#define PHYDM_RELEASE_DATE "00000000" +/*PHYDM API status*/ +#define PHYDM_SET_FAIL 0 +#define PHYDM_SET_SUCCESS 1 +#define PHYDM_SET_NO_NEED 3 -/* Max path of IC */ +/*PHYDM Set/Revert*/ +#define PHYDM_SET 1 +#define PHYDM_REVERT 2 + +/* @Max path of IC */ +/*N-IC*/ #define MAX_PATH_NUM_8188E 1 -#define MAX_PATH_NUM_8192E 2 -#define MAX_PATH_NUM_8723B 1 -#define MAX_PATH_NUM_8812A 2 -#define MAX_PATH_NUM_8821A 1 -#define MAX_PATH_NUM_8814A 4 -#define MAX_PATH_NUM_8822B 2 -#define MAX_PATH_NUM_8821B 2 -#define MAX_PATH_NUM_8703B 1 #define MAX_PATH_NUM_8188F 1 +#define MAX_PATH_NUM_8710B 1 +#define MAX_PATH_NUM_8723B 1 #define MAX_PATH_NUM_8723D 1 +#define MAX_PATH_NUM_8703B 1 +#define MAX_PATH_NUM_8192E 2 +#define MAX_PATH_NUM_8192F 2 #define MAX_PATH_NUM_8197F 2 +#define MAX_PATH_NUM_8198F 4 +/*@AC-IC*/ +#define MAX_PATH_NUM_8821A 1 +#define MAX_PATH_NUM_8881A 1 #define MAX_PATH_NUM_8821C 1 -/* JJ ADD 20161014 */ -#define MAX_PATH_NUM_8710B 1 +#define MAX_PATH_NUM_8195B 1 +#define MAX_PATH_NUM_8812A 2 +#define MAX_PATH_NUM_8822B 2 +#define MAX_PATH_NUM_8822C 2 +#define MAX_PATH_NUM_8814A 4 +#define MAX_PATH_NUM_8814B 4 +#define MAX_PATH_NUM_8814C 4 +#define MAX_PATH_NUM_8195B 1 -/* Max RF path */ -#define ODM_RF_PATH_MAX 2 -#define ODM_RF_PATH_MAX_JAGUAR 4 - -/*Bit define path*/ -#define PHYDM_A BIT(0) -#define PHYDM_B BIT(1) -#define PHYDM_C BIT(2) -#define PHYDM_D BIT(3) -#define PHYDM_AB (BIT(0) | BIT(1)) -#define PHYDM_AC (BIT(0) | BIT(2)) -#define PHYDM_AD (BIT(0) | BIT(3)) -#define PHYDM_BC (BIT(1) | BIT(2)) -#define PHYDM_BD (BIT(1) | BIT(3)) -#define PHYDM_CD (BIT(2) | BIT(3)) -#define PHYDM_ABC (BIT(0) | BIT(1) | BIT(2)) -#define PHYDM_ABD (BIT(0) | BIT(1) | BIT(3)) -#define PHYDM_ACD (BIT(0) | BIT(2) | BIT(3)) -#define PHYDM_BCD (BIT(1) | BIT(2) | BIT(3)) -#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +/* @Max RF path */ +#define PHYDM_MAX_RF_PATH_N 2 /*@For old N-series IC*/ +#define PHYDM_MAX_RF_PATH 4 /* number of entry */ #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) - #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of asoc_entry[].*/ - #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM - #elif(DM_ODM_SUPPORT_TYPE & (ODM_AP)) - #define ASSOCIATE_ENTRY_NUM NUM_STAT - #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1) + #ifdef DM_ODM_CE_MAC80211 + /* @defined in wifi.h (32+1) */ + #else + #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* @Max size of asoc_entry[].*/ + #endif + #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM +#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #define ASSOCIATE_ENTRY_NUM NUM_STAT + #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM + 1) +#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) + #ifdef CONFIG_CONCURRENT_MODE + #define ASSOCIATE_ENTRY_NUM NUM_STA + 2 /*@2 is for station mod*/ + #else + #define ASSOCIATE_ENTRY_NUM NUM_STA /*@8 is for max size of asoc_entry[].*/ + #endif + #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM #else - #define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1) + #define ODM_ASSOCIATE_ENTRY_NUM (((ASSOCIATE_ENTRY_NUM + 1) * 3) + 1) #endif -/* -----MGN rate--------------------------------- */ +/* @-----MGN rate--------------------------------- */ + +enum PDM_RATE_TYPE { + PDM_1SS = 1, /*VHT/HT 1SS*/ + PDM_2SS = 2, /*VHT/HT 2SS*/ + PDM_3SS = 3, /*VHT/HT 3SS*/ + PDM_4SS = 4, /*VHT/HT 4SS*/ + PDM_CCK = 11, /*@B*/ + PDM_OFDM = 12 /*@G*/ +}; enum ODM_MGN_RATE { ODM_MGN_1M = 0x02, ODM_MGN_2M = 0x04, - ODM_MGN_5_5M = 0x0B, + ODM_MGN_5_5M = 0x0B, ODM_MGN_6M = 0x0C, ODM_MGN_9M = 0x12, - ODM_MGN_11M = 0x16, - ODM_MGN_12M = 0x18, - ODM_MGN_18M = 0x24, - ODM_MGN_24M = 0x30, - ODM_MGN_36M = 0x48, - ODM_MGN_48M = 0x60, - ODM_MGN_54M = 0x6C, - ODM_MGN_MCS32 = 0x7F, - ODM_MGN_MCS0, + ODM_MGN_11M = 0x16, + ODM_MGN_12M = 0x18, + ODM_MGN_18M = 0x24, + ODM_MGN_24M = 0x30, + ODM_MGN_36M = 0x48, + ODM_MGN_48M = 0x60, + ODM_MGN_54M = 0x6C, + ODM_MGN_MCS32 = 0x7F, + ODM_MGN_MCS0 = 0x80, ODM_MGN_MCS1, ODM_MGN_MCS2, ODM_MGN_MCS3, ODM_MGN_MCS4, ODM_MGN_MCS5, ODM_MGN_MCS6, - ODM_MGN_MCS7, + ODM_MGN_MCS7 = 0x87, ODM_MGN_MCS8, ODM_MGN_MCS9, ODM_MGN_MCS10, @@ -110,7 +136,7 @@ enum ODM_MGN_RATE { ODM_MGN_MCS13, ODM_MGN_MCS14, ODM_MGN_MCS15, - ODM_MGN_MCS16, + ODM_MGN_MCS16 = 0x90, ODM_MGN_MCS17, ODM_MGN_MCS18, ODM_MGN_MCS19, @@ -118,7 +144,7 @@ enum ODM_MGN_RATE { ODM_MGN_MCS21, ODM_MGN_MCS22, ODM_MGN_MCS23, - ODM_MGN_MCS24, + ODM_MGN_MCS24 = 0x98, ODM_MGN_MCS25, ODM_MGN_MCS26, ODM_MGN_MCS27, @@ -126,7 +152,7 @@ enum ODM_MGN_RATE { ODM_MGN_MCS29, ODM_MGN_MCS30, ODM_MGN_MCS31, - ODM_MGN_VHT1SS_MCS0, + ODM_MGN_VHT1SS_MCS0 = 0xa0, ODM_MGN_VHT1SS_MCS1, ODM_MGN_VHT1SS_MCS2, ODM_MGN_VHT1SS_MCS3, @@ -136,27 +162,27 @@ enum ODM_MGN_RATE { ODM_MGN_VHT1SS_MCS7, ODM_MGN_VHT1SS_MCS8, ODM_MGN_VHT1SS_MCS9, - ODM_MGN_VHT2SS_MCS0, - ODM_MGN_VHT2SS_MCS1, + ODM_MGN_VHT2SS_MCS0 = 0xaa, + ODM_MGN_VHT2SS_MCS1 = 0xab, ODM_MGN_VHT2SS_MCS2, ODM_MGN_VHT2SS_MCS3, ODM_MGN_VHT2SS_MCS4, - ODM_MGN_VHT2SS_MCS5, - ODM_MGN_VHT2SS_MCS6, + ODM_MGN_VHT2SS_MCS5 = 0xaf, + ODM_MGN_VHT2SS_MCS6 = 0xb0, ODM_MGN_VHT2SS_MCS7, ODM_MGN_VHT2SS_MCS8, - ODM_MGN_VHT2SS_MCS9, - ODM_MGN_VHT3SS_MCS0, + ODM_MGN_VHT2SS_MCS9 = 0xb3, + ODM_MGN_VHT3SS_MCS0 = 0xb4, ODM_MGN_VHT3SS_MCS1, ODM_MGN_VHT3SS_MCS2, ODM_MGN_VHT3SS_MCS3, ODM_MGN_VHT3SS_MCS4, ODM_MGN_VHT3SS_MCS5, ODM_MGN_VHT3SS_MCS6, - ODM_MGN_VHT3SS_MCS7, - ODM_MGN_VHT3SS_MCS8, - ODM_MGN_VHT3SS_MCS9, - ODM_MGN_VHT4SS_MCS0, + ODM_MGN_VHT3SS_MCS7 = 0xbb, + ODM_MGN_VHT3SS_MCS8 = 0xbc, + ODM_MGN_VHT3SS_MCS9 = 0xbd, + ODM_MGN_VHT4SS_MCS0 = 0xbe, ODM_MGN_VHT4SS_MCS1, ODM_MGN_VHT4SS_MCS2, ODM_MGN_VHT4SS_MCS3, @@ -165,7 +191,7 @@ enum ODM_MGN_RATE { ODM_MGN_VHT4SS_MCS6, ODM_MGN_VHT4SS_MCS7, ODM_MGN_VHT4SS_MCS8, - ODM_MGN_VHT4SS_MCS9, + ODM_MGN_VHT4SS_MCS9 = 0xc7, ODM_MGN_UNKNOWN }; @@ -179,122 +205,122 @@ enum ODM_MGN_RATE { #define ODM_MGN_MCS7_SG 0xc7 #define ODM_MGN_MCS8_SG 0xc8 #define ODM_MGN_MCS9_SG 0xc9 -#define ODM_MGN_MCS10_SG 0xca -#define ODM_MGN_MCS11_SG 0xcb -#define ODM_MGN_MCS12_SG 0xcc -#define ODM_MGN_MCS13_SG 0xcd -#define ODM_MGN_MCS14_SG 0xce -#define ODM_MGN_MCS15_SG 0xcf - -/* -----DESC rate--------------------------------- */ - -#define ODM_RATEMCS15_SG 0x1c -#define ODM_RATEMCS32 0x20 - - -/* CCK Rates, TxHT = 0 */ -#define ODM_RATE1M 0x00 -#define ODM_RATE2M 0x01 -#define ODM_RATE5_5M 0x02 -#define ODM_RATE11M 0x03 +#define ODM_MGN_MCS10_SG 0xca +#define ODM_MGN_MCS11_SG 0xcb +#define ODM_MGN_MCS12_SG 0xcc +#define ODM_MGN_MCS13_SG 0xcd +#define ODM_MGN_MCS14_SG 0xce +#define ODM_MGN_MCS15_SG 0xcf + +/* @-----DESC rate--------------------------------- */ + +#define ODM_RATEMCS15_SG 0x1c +#define ODM_RATEMCS32 0x20 + +enum phydm_ctrl_info_rate { + ODM_RATE1M = 0x00, + ODM_RATE2M = 0x01, + ODM_RATE5_5M = 0x02, + ODM_RATE11M = 0x03, /* OFDM Rates, TxHT = 0 */ -#define ODM_RATE6M 0x04 -#define ODM_RATE9M 0x05 -#define ODM_RATE12M 0x06 -#define ODM_RATE18M 0x07 -#define ODM_RATE24M 0x08 -#define ODM_RATE36M 0x09 -#define ODM_RATE48M 0x0A -#define ODM_RATE54M 0x0B -/* MCS Rates, TxHT = 1 */ -#define ODM_RATEMCS0 0x0C -#define ODM_RATEMCS1 0x0D -#define ODM_RATEMCS2 0x0E -#define ODM_RATEMCS3 0x0F -#define ODM_RATEMCS4 0x10 -#define ODM_RATEMCS5 0x11 -#define ODM_RATEMCS6 0x12 -#define ODM_RATEMCS7 0x13 -#define ODM_RATEMCS8 0x14 -#define ODM_RATEMCS9 0x15 -#define ODM_RATEMCS10 0x16 -#define ODM_RATEMCS11 0x17 -#define ODM_RATEMCS12 0x18 -#define ODM_RATEMCS13 0x19 -#define ODM_RATEMCS14 0x1A -#define ODM_RATEMCS15 0x1B -#define ODM_RATEMCS16 0x1C -#define ODM_RATEMCS17 0x1D -#define ODM_RATEMCS18 0x1E -#define ODM_RATEMCS19 0x1F -#define ODM_RATEMCS20 0x20 -#define ODM_RATEMCS21 0x21 -#define ODM_RATEMCS22 0x22 -#define ODM_RATEMCS23 0x23 -#define ODM_RATEMCS24 0x24 -#define ODM_RATEMCS25 0x25 -#define ODM_RATEMCS26 0x26 -#define ODM_RATEMCS27 0x27 -#define ODM_RATEMCS28 0x28 -#define ODM_RATEMCS29 0x29 -#define ODM_RATEMCS30 0x2A -#define ODM_RATEMCS31 0x2B -#define ODM_RATEVHTSS1MCS0 0x2C -#define ODM_RATEVHTSS1MCS1 0x2D -#define ODM_RATEVHTSS1MCS2 0x2E -#define ODM_RATEVHTSS1MCS3 0x2F -#define ODM_RATEVHTSS1MCS4 0x30 -#define ODM_RATEVHTSS1MCS5 0x31 -#define ODM_RATEVHTSS1MCS6 0x32 -#define ODM_RATEVHTSS1MCS7 0x33 -#define ODM_RATEVHTSS1MCS8 0x34 -#define ODM_RATEVHTSS1MCS9 0x35 -#define ODM_RATEVHTSS2MCS0 0x36 -#define ODM_RATEVHTSS2MCS1 0x37 -#define ODM_RATEVHTSS2MCS2 0x38 -#define ODM_RATEVHTSS2MCS3 0x39 -#define ODM_RATEVHTSS2MCS4 0x3A -#define ODM_RATEVHTSS2MCS5 0x3B -#define ODM_RATEVHTSS2MCS6 0x3C -#define ODM_RATEVHTSS2MCS7 0x3D -#define ODM_RATEVHTSS2MCS8 0x3E -#define ODM_RATEVHTSS2MCS9 0x3F -#define ODM_RATEVHTSS3MCS0 0x40 -#define ODM_RATEVHTSS3MCS1 0x41 -#define ODM_RATEVHTSS3MCS2 0x42 -#define ODM_RATEVHTSS3MCS3 0x43 -#define ODM_RATEVHTSS3MCS4 0x44 -#define ODM_RATEVHTSS3MCS5 0x45 -#define ODM_RATEVHTSS3MCS6 0x46 -#define ODM_RATEVHTSS3MCS7 0x47 -#define ODM_RATEVHTSS3MCS8 0x48 -#define ODM_RATEVHTSS3MCS9 0x49 -#define ODM_RATEVHTSS4MCS0 0x4A -#define ODM_RATEVHTSS4MCS1 0x4B -#define ODM_RATEVHTSS4MCS2 0x4C -#define ODM_RATEVHTSS4MCS3 0x4D -#define ODM_RATEVHTSS4MCS4 0x4E -#define ODM_RATEVHTSS4MCS5 0x4F -#define ODM_RATEVHTSS4MCS6 0x50 -#define ODM_RATEVHTSS4MCS7 0x51 -#define ODM_RATEVHTSS4MCS8 0x52 -#define ODM_RATEVHTSS4MCS9 0x53 + ODM_RATE6M = 0x04, + ODM_RATE9M = 0x05, + ODM_RATE12M = 0x06, + ODM_RATE18M = 0x07, + ODM_RATE24M = 0x08, + ODM_RATE36M = 0x09, + ODM_RATE48M = 0x0A, + ODM_RATE54M = 0x0B, +/* @MCS Rates, TxHT = 1 */ + ODM_RATEMCS0 = 0x0C, + ODM_RATEMCS1 = 0x0D, + ODM_RATEMCS2 = 0x0E, + ODM_RATEMCS3 = 0x0F, + ODM_RATEMCS4 = 0x10, + ODM_RATEMCS5 = 0x11, + ODM_RATEMCS6 = 0x12, + ODM_RATEMCS7 = 0x13, + ODM_RATEMCS8 = 0x14, + ODM_RATEMCS9 = 0x15, + ODM_RATEMCS10 = 0x16, + ODM_RATEMCS11 = 0x17, + ODM_RATEMCS12 = 0x18, + ODM_RATEMCS13 = 0x19, + ODM_RATEMCS14 = 0x1A, + ODM_RATEMCS15 = 0x1B, + ODM_RATEMCS16 = 0x1C, + ODM_RATEMCS17 = 0x1D, + ODM_RATEMCS18 = 0x1E, + ODM_RATEMCS19 = 0x1F, + ODM_RATEMCS20 = 0x20, + ODM_RATEMCS21 = 0x21, + ODM_RATEMCS22 = 0x22, + ODM_RATEMCS23 = 0x23, + ODM_RATEMCS24 = 0x24, + ODM_RATEMCS25 = 0x25, + ODM_RATEMCS26 = 0x26, + ODM_RATEMCS27 = 0x27, + ODM_RATEMCS28 = 0x28, + ODM_RATEMCS29 = 0x29, + ODM_RATEMCS30 = 0x2A, + ODM_RATEMCS31 = 0x2B, + ODM_RATEVHTSS1MCS0 = 0x2C, + ODM_RATEVHTSS1MCS1 = 0x2D, + ODM_RATEVHTSS1MCS2 = 0x2E, + ODM_RATEVHTSS1MCS3 = 0x2F, + ODM_RATEVHTSS1MCS4 = 0x30, + ODM_RATEVHTSS1MCS5 = 0x31, + ODM_RATEVHTSS1MCS6 = 0x32, + ODM_RATEVHTSS1MCS7 = 0x33, + ODM_RATEVHTSS1MCS8 = 0x34, + ODM_RATEVHTSS1MCS9 = 0x35, + ODM_RATEVHTSS2MCS0 = 0x36, + ODM_RATEVHTSS2MCS1 = 0x37, + ODM_RATEVHTSS2MCS2 = 0x38, + ODM_RATEVHTSS2MCS3 = 0x39, + ODM_RATEVHTSS2MCS4 = 0x3A, + ODM_RATEVHTSS2MCS5 = 0x3B, + ODM_RATEVHTSS2MCS6 = 0x3C, + ODM_RATEVHTSS2MCS7 = 0x3D, + ODM_RATEVHTSS2MCS8 = 0x3E, + ODM_RATEVHTSS2MCS9 = 0x3F, + ODM_RATEVHTSS3MCS0 = 0x40, + ODM_RATEVHTSS3MCS1 = 0x41, + ODM_RATEVHTSS3MCS2 = 0x42, + ODM_RATEVHTSS3MCS3 = 0x43, + ODM_RATEVHTSS3MCS4 = 0x44, + ODM_RATEVHTSS3MCS5 = 0x45, + ODM_RATEVHTSS3MCS6 = 0x46, + ODM_RATEVHTSS3MCS7 = 0x47, + ODM_RATEVHTSS3MCS8 = 0x48, + ODM_RATEVHTSS3MCS9 = 0x49, + ODM_RATEVHTSS4MCS0 = 0x4A, + ODM_RATEVHTSS4MCS1 = 0x4B, + ODM_RATEVHTSS4MCS2 = 0x4C, + ODM_RATEVHTSS4MCS3 = 0x4D, + ODM_RATEVHTSS4MCS4 = 0x4E, + ODM_RATEVHTSS4MCS5 = 0x4F, + ODM_RATEVHTSS4MCS6 = 0x50, + ODM_RATEVHTSS4MCS7 = 0x51, + ODM_RATEVHTSS4MCS8 = 0x52, + ODM_RATEVHTSS4MCS9 = 0x53, +}; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1) #else - #if (RTL8192E_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) - #define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1) - #elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) - #define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1) - #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) - #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1) - #elif (RTL8812A_SUPPORT == 1) - #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1) - #elif (RTL8814A_SUPPORT == 1) - #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1) + #if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + #define ODM_NUM_RATE_IDX (ODM_RATEMCS15 + 1) + #elif (RTL8723B_SUPPORT || RTL8188E_SUPPORT || RTL8188F_SUPPORT) + #define ODM_NUM_RATE_IDX (ODM_RATEMCS7 + 1) + #elif (RTL8821A_SUPPORT || RTL8881A_SUPPORT) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9 + 1) + #elif (RTL8812A_SUPPORT) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9 + 1) + #elif (RTL8814A_SUPPORT) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9 + 1) #else - #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1) #endif #endif @@ -302,21 +328,23 @@ enum ODM_MGN_RATE { #define CONFIG_SFW_SUPPORTED #endif -/* 1 ============================================================ +/**************************************************************** + * 1 ============================================================ * 1 enumeration - * 1 ============================================================ */ - + * 1 ============================================================ + ***************************************************************/ /* ODM_CMNINFO_INTERFACE */ -enum odm_interface_e { +enum odm_interface { ODM_ITRF_PCIE = 0x1, ODM_ITRF_USB = 0x2, ODM_ITRF_SDIO = 0x4, ODM_ITRF_ALL = 0x7, }; -/* ODM_CMNINFO_IC_TYPE */ -enum odm_ic_type_e { +/*@========[Run time IC flag] ===================================*/ + +enum phydm_ic { ODM_RTL8188E = BIT(0), ODM_RTL8812 = BIT(1), ODM_RTL8821 = BIT(2), @@ -333,350 +361,457 @@ enum odm_ic_type_e { ODM_RTL8821C = BIT(13), ODM_RTL8814B = BIT(14), ODM_RTL8198F = BIT(15), - /* JJ ADD 20161014 */ ODM_RTL8710B = BIT(16), + ODM_RTL8192F = BIT(17), + ODM_RTL8822C = BIT(18), + ODM_RTL8195B = BIT(19) }; -/* JJ ADD 20161014 */ -#define ODM_IC_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | ODM_RTL8195A | ODM_RTL8710B) -#define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B) -#define ODM_IC_3SS (ODM_RTL8814A) -#define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F) +#define ODM_IC_N_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B |\ + ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A |\ + ODM_RTL8710B) +#define ODM_IC_N_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F) +#define ODM_IC_N_3SS 0 +#define ODM_IC_N_4SS 0 + +#define ODM_IC_AC_1SS (ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C |\ + ODM_RTL8195B) +#define ODM_IC_AC_2SS (ODM_RTL8812 | ODM_RTL8822B) +#define ODM_IC_AC_3SS 0 +#define ODM_IC_AC_4SS (ODM_RTL8814A) + +#define ODM_IC_JGR3_1SS 0 +#define ODM_IC_JGR3_2SS (ODM_RTL8822C) +#define ODM_IC_JGR3_3SS 0 +#define ODM_IC_JGR3_4SS (ODM_RTL8198F | ODM_RTL8814B) + +/*@====the following macro DO NOT need to update when adding a new IC======= */ +#define ODM_IC_1SS (ODM_IC_N_1SS | ODM_IC_AC_1SS | ODM_IC_JGR3_1SS) +#define ODM_IC_2SS (ODM_IC_N_2SS | ODM_IC_AC_2SS | ODM_IC_JGR3_2SS) +#define ODM_IC_3SS (ODM_IC_N_3SS | ODM_IC_AC_3SS | ODM_IC_JGR3_3SS) +#define ODM_IC_4SS (ODM_IC_N_4SS | ODM_IC_AC_4SS | ODM_IC_JGR3_4SS) + +#define PHYDM_IC_ABOVE_1SS (ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS |\ + ODM_IC_4SS) +#define PHYDM_IC_ABOVE_2SS (ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS) +#define PHYDM_IC_ABOVE_3SS (ODM_IC_3SS | ODM_IC_4SS) +#define PHYDM_IC_ABOVE_4SS ODM_IC_4SS + +#define ODM_IC_11N_SERIES (ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS |\ + ODM_IC_N_4SS) +#define ODM_IC_11AC_SERIES (ODM_IC_AC_1SS | ODM_IC_AC_2SS |\ + ODM_IC_AC_3SS | ODM_IC_AC_4SS) +#define ODM_IC_JGR3_SERIES (ODM_IC_JGR3_1SS | ODM_IC_JGR3_2SS |\ + ODM_IC_JGR3_3SS | ODM_IC_JGR3_4SS) +/*@====================================================*/ + +#define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A) +#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C |\ + ODM_RTL8195B) + +/*@[Phy status type]*/ +#define PHYSTS_2ND_TYPE_IC (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D |\ + ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B |\ + ODM_RTL8192F) +#define PHYSTS_3RD_TYPE_IC (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C) +/*@[FW Type]*/ +#define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 |\ + ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |\ + ODM_RTL8188F | ODM_RTL8192F) +#define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\ + ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\ + ODM_RTL8822C) +/*@[LA mode]*/ +#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\ + ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\ + ODM_RTL8192F | ODM_RTL8822C) +/*@[BF]*/ +#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 |\ + ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B |\ + ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B |\ + ODM_RTL8198F | ODM_RTL8822C) +#define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B |\ + ODM_RTL8195B | ODM_RTL8198F | ODM_RTL8822C) +#define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F |\ + ODM_RTL8822C) +/*@[PHYDM API]*/ +#define CMN_API_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\ + ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\ + ODM_RTL8198F) + +/*@========[Compile time IC flag] ========================*/ +/*@========[AC-3/AC/N Support] ===========================*/ + +#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT) + #define PHYDM_IC_JGR3_SERIES_SUPPORT + #if (RTL8814B_SUPPORT || RTL8822C_SUPPORT) + #define PHYDM_IC_JGR3_80M_SUPPORT + #endif +#endif -/* JJ ADD 20161014 */ -#define ODM_IC_11N_SERIES (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B) -#define ODM_IC_11AC_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8821C) -#define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A) -#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C) -#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) -#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B) -#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C) -#define ODM_IC_PHY_STATUE_NEW_TYPE (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B) +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + + #ifdef RTK_AC_SUPPORT + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #else + #define ODM_IC_11AC_SERIES_SUPPORT 0 + #endif -#define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F) -#define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) + #define ODM_IC_11N_SERIES_SUPPORT 1 -#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #define ODM_IC_11N_SERIES_SUPPORT 1 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #define ODM_IC_11N_SERIES_SUPPORT 1 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) -#ifdef RTK_AC_SUPPORT #define ODM_IC_11AC_SERIES_SUPPORT 1 -#else - #define ODM_IC_11AC_SERIES_SUPPORT 0 + #define ODM_IC_11N_SERIES_SUPPORT 1 + +#else /*ODM_CE*/ + + #if (RTL8188E_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\ + RTL8195A_SUPPORT || RTL8703B_SUPPORT || RTL8188F_SUPPORT ||\ + RTL8723D_SUPPORT || RTL8197F_SUPPORT || RTL8710B_SUPPORT ||\ + RTL8192F_SUPPORT) + #define ODM_IC_11N_SERIES_SUPPORT 1 + #define ODM_IC_11AC_SERIES_SUPPORT 0 + #else + #define ODM_IC_11N_SERIES_SUPPORT 0 + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #endif #endif -#define ODM_IC_11N_SERIES_SUPPORT 1 -#define ODM_CONFIG_BT_COEXIST 0 +/*@===IC SS Compile Flag, prepare for code size reduction==============*/ +#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT || RTL8723B_SUPPORT ||\ + RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8881A_SUPPORT ||\ + RTL8821A_SUPPORT || RTL8821C_SUPPORT || RTL8195A_SUPPORT ||\ + RTL8710B_SUPPORT || RTL8195B_SUPPORT) -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define PHYDM_COMPILE_IC_1SS +#endif + +#if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8812A_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8822C_SUPPORT) + #define PHYDM_COMPILE_IC_2SS +#endif -#define ODM_IC_11AC_SERIES_SUPPORT 1 -#define ODM_IC_11N_SERIES_SUPPORT 1 -#define ODM_CONFIG_BT_COEXIST 1 +/*@#define PHYDM_COMPILE_IC_3SS*/ -#else -/* JJ ADD 20161014 */ -#if ((RTL8188E_SUPPORT == 1) || \ -(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \ -(RTL8188F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8710B_SUPPORT == 1)) -#define ODM_IC_11N_SERIES_SUPPORT 1 -#define ODM_IC_11AC_SERIES_SUPPORT 0 -#else -#define ODM_IC_11N_SERIES_SUPPORT 0 -#define ODM_IC_11AC_SERIES_SUPPORT 1 +#if ((RTL8814B_SUPPORT) || (RTL8814A_SUPPORT) || (RTL8198F_SUPPORT)) + #define PHYDM_COMPILE_IC_4SS #endif -#ifdef CONFIG_BT_COEXIST - #define ODM_CONFIG_BT_COEXIST 1 -#else - #define ODM_CONFIG_BT_COEXIST 0 +/*@==[ABOVE N-SS COMPILE FLAG]=================================================*/ +#if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) ||\ + defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_1SS +#endif + +#if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) ||\ + defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_2SS #endif +#if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_3SS #endif -/* JJ ADD 20161014 */ -#if ((RTL8197F_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8710B_SUPPORT == 1) ) +#if (defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_4SS +#endif + +/*@========[New Phy-Status Support] ========================*/ +#if (RTL8197F_SUPPORT || RTL8723D_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8821C_SUPPORT || RTL8710B_SUPPORT || RTL8195B_SUPPORT ||\ + RTL8192F_SUPPORT) #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1 #else #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0 #endif -/* ODM_CMNINFO_CUT_VER */ -enum odm_cut_version_e { - ODM_CUT_A = 0, - ODM_CUT_B = 1, - ODM_CUT_C = 2, - ODM_CUT_D = 3, - ODM_CUT_E = 4, - ODM_CUT_F = 5, - - ODM_CUT_I = 8, - ODM_CUT_J = 9, - ODM_CUT_K = 10, - ODM_CUT_TEST = 15, -}; +#if (RTL8198F_SUPPORT) || (RTL8814B_SUPPORT) || (RTL8822C_SUPPORT) + #define PHYSTS_3RD_TYPE_SUPPORT +#endif -/* ODM_CMNINFO_FAB_VER */ -enum odm_fab_e { - ODM_TSMC = 0, - ODM_UMC = 1, -}; +#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT) + #define BB_RAM_SUPPORT +#endif -/* ODM_CMNINFO_RF_TYPE - * - * For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5)) - * */ -enum odm_rf_path_e { - ODM_RF_A = BIT(0), - ODM_RF_B = BIT(1), - ODM_RF_C = BIT(2), - ODM_RF_D = BIT(3), -}; +/*@============================================================================*/ -enum odm_rf_tx_num_e { - ODM_1T = 1, - ODM_2T = 2, - ODM_3T = 3, - ODM_4T = 4, -}; +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8198F_SUPPORT) +#define PHYDM_COMMON_API_SUPPORT +#endif -enum odm_rf_type_e { - ODM_1T1R, - ODM_1T2R, - ODM_2T2R, - ODM_2T2R_GREEN, - ODM_2T3R, - ODM_2T4R, - ODM_3T3R, - ODM_3T4R, - ODM_4T4R, - ODM_XTXR -}; +#define CCK_RATE_NUM 4 +#define OFDM_RATE_NUM 8 + +#define LEGACY_RATE_NUM 12 + +#define HT_RATE_NUM_4SS 32 +#define VHT_RATE_NUM_4SS 40 + +#define HT_RATE_NUM_3SS 24 +#define VHT_RATE_NUM_3SS 30 + +#define HT_RATE_NUM_2SS 16 +#define VHT_RATE_NUM_2SS 20 -enum odm_mac_phy_mode_e { - ODM_SMSP = 0, - ODM_DMSP = 1, - ODM_DMDP = 2, +#define HT_RATE_NUM_1SS 8 +#define VHT_RATE_NUM_1SS 10 +#if (defined(PHYDM_COMPILE_ABOVE_4SS)) + #define HT_RATE_NUM HT_RATE_NUM_4SS + #define VHT_RATE_NUM VHT_RATE_NUM_4SS +#elif (defined(PHYDM_COMPILE_ABOVE_3SS)) + #define HT_RATE_NUM HT_RATE_NUM_3SS + #define VHT_RATE_NUM VHT_RATE_NUM_3SS +#elif (defined(PHYDM_COMPILE_ABOVE_2SS)) + #define HT_RATE_NUM HT_RATE_NUM_2SS + #define VHT_RATE_NUM VHT_RATE_NUM_2SS +#else + #define HT_RATE_NUM HT_RATE_NUM_1SS + #define VHT_RATE_NUM VHT_RATE_NUM_1SS +#endif + +#define LOW_BW_RATE_NUM VHT_RATE_NUM + +enum phydm_ic_ip { + PHYDM_IC_N = 0, + PHYDM_IC_AC = 1, + PHYDM_IC_JGR3 = 2 }; +/* ODM_CMNINFO_CUT_VER */ +enum odm_cut_version { + ODM_CUT_A = 0, + ODM_CUT_B = 1, + ODM_CUT_C = 2, + ODM_CUT_D = 3, + ODM_CUT_E = 4, + ODM_CUT_F = 5, + ODM_CUT_G = 6, + ODM_CUT_H = 7, + ODM_CUT_I = 8, + ODM_CUT_J = 9, + ODM_CUT_K = 10, + ODM_CUT_TEST = 15, +}; -enum odm_bt_coexist_e { - ODM_BT_BUSY = 1, - ODM_BT_ON = 2, - ODM_BT_OFF = 3, - ODM_BT_NONE = 4, +/* ODM_CMNINFO_FAB_VER */ +enum odm_fab { + ODM_TSMC = 0, + ODM_UMC = 1, }; /* ODM_CMNINFO_OP_MODE */ -enum odm_operation_mode_e { +enum odm_operation_mode { ODM_NO_LINK = BIT(0), - ODM_LINK = BIT(1), - ODM_SCAN = BIT(2), - ODM_POWERSAVE = BIT(3), + ODM_LINK = BIT(1), + ODM_SCAN = BIT(2), + ODM_POWERSAVE = BIT(3), ODM_AP_MODE = BIT(4), - ODM_CLIENT_MODE = BIT(5), + ODM_CLIENT_MODE = BIT(5), ODM_AD_HOC = BIT(6), - ODM_WIFI_DIRECT = BIT(7), + ODM_WIFI_DIRECT = BIT(7), ODM_WIFI_DISPLAY = BIT(8), }; /* ODM_CMNINFO_WM_MODE */ #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -enum odm_wireless_mode_e { - ODM_WM_UNKNOW = 0x0, - ODM_WM_B = BIT(0), - ODM_WM_G = BIT(1), - ODM_WM_A = BIT(2), +enum odm_wireless_mode { + ODM_WM_UNKNOW = 0x0, + ODM_WM_B = BIT(0), + ODM_WM_G = BIT(1), + ODM_WM_A = BIT(2), ODM_WM_N24G = BIT(3), ODM_WM_N5G = BIT(4), ODM_WM_AUTO = BIT(5), ODM_WM_AC = BIT(6), }; #else -enum odm_wireless_mode_e { - ODM_WM_UNKNOWN = 0x00,/*0x0*/ - ODM_WM_A = BIT(0), /* 0x1*/ - ODM_WM_B = BIT(1), /* 0x2*/ - ODM_WM_G = BIT(2),/* 0x4*/ - ODM_WM_AUTO = BIT(3),/* 0x8*/ - ODM_WM_N24G = BIT(4),/* 0x10*/ - ODM_WM_N5G = BIT(5),/* 0x20*/ - ODM_WM_AC_5G = BIT(6),/* 0x40*/ - ODM_WM_AC_24G = BIT(7),/* 0x80*/ - ODM_WM_AC_ONLY = BIT(8),/* 0x100*/ - ODM_WM_MAX = BIT(11)/* 0x800*/ +enum odm_wireless_mode { + ODM_WM_UNKNOWN = 0x00,/*@0x0*/ + ODM_WM_A = BIT(0), /* @0x1*/ + ODM_WM_B = BIT(1), /* @0x2*/ + ODM_WM_G = BIT(2),/* @0x4*/ + ODM_WM_AUTO = BIT(3),/* @0x8*/ + ODM_WM_N24G = BIT(4),/* @0x10*/ + ODM_WM_N5G = BIT(5),/* @0x20*/ + ODM_WM_AC_5G = BIT(6),/* @0x40*/ + ODM_WM_AC_24G = BIT(7),/* @0x80*/ + ODM_WM_AC_ONLY = BIT(8),/* @0x100*/ + ODM_WM_MAX = BIT(11)/* @0x800*/ }; #endif /* ODM_CMNINFO_BAND */ -enum odm_band_type_e { +enum odm_band_type { #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - ODM_BAND_2_4G = BIT(0), + ODM_BAND_2_4G = BIT(0), ODM_BAND_5G = BIT(1), #else - ODM_BAND_2_4G = 0, + ODM_BAND_2_4G = 0, ODM_BAND_5G, ODM_BAND_ON_BOTH, ODM_BANDMAX #endif }; - /* ODM_CMNINFO_SEC_CHNL_OFFSET */ -enum phydm_sec_chnl_offset_e { - - PHYDM_DONT_CARE = 0, +enum phydm_sec_chnl_offset { + PHYDM_DONT_CARE = 0, PHYDM_BELOW = 1, PHYDM_ABOVE = 2 }; /* ODM_CMNINFO_SEC_MODE */ -enum odm_security_e { - ODM_SEC_OPEN = 0, +enum odm_security { + ODM_SEC_OPEN = 0, ODM_SEC_WEP40 = 1, - ODM_SEC_TKIP = 2, + ODM_SEC_TKIP = 2, ODM_SEC_RESERVE = 3, ODM_SEC_AESCCMP = 4, ODM_SEC_WEP104 = 5, - ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ - ODM_SEC_SMS4 = 7, -}; - -/* ODM_CMNINFO_BW */ -enum odm_bw_e { - ODM_BW20M = 0, - ODM_BW40M = 1, - ODM_BW80M = 2, - ODM_BW160M = 3, - ODM_BW5M = 4, - ODM_BW10M = 5, - ODM_BW_MAX = 6 + ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ + ODM_SEC_SMS4 = 7, }; /* ODM_CMNINFO_CHNL */ /* ODM_CMNINFO_BOARD_TYPE */ -enum odm_board_type_e { - ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ - ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */ - ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ - ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */ - ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */ - ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ - ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */ - ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */ - ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ +enum odm_board_type { + ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ + ODM_BOARD_MINICARD = BIT(0), /* @0 = non-mini card, 1= mini card. */ + ODM_BOARD_SLIM = BIT(1), /* @0 = non-slim card, 1 = slim card */ + ODM_BOARD_BT = BIT(2), /* @0 = without BT card, 1 = with BT */ + ODM_BOARD_EXT_PA = BIT(3), /* @0 = no 2G ext-PA, 1 = existing 2G ext-PA */ + ODM_BOARD_EXT_LNA = BIT(4), /* @0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ + ODM_BOARD_EXT_TRSW = BIT(5), /* @0 = no ext-TRSW, 1 = existing ext-TRSW */ + ODM_BOARD_EXT_PA_5G = BIT(6), /* @0 = no 5G ext-PA, 1 = existing 5G ext-PA */ + ODM_BOARD_EXT_LNA_5G = BIT(7), /* @0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ }; -enum odm_package_type_e { - ODM_PACKAGE_DEFAULT = 0, - ODM_PACKAGE_QFN68 = BIT(0), - ODM_PACKAGE_TFBGA90 = BIT(1), - ODM_PACKAGE_TFBGA79 = BIT(2), +enum odm_package_type { + ODM_PACKAGE_DEFAULT = 0, + ODM_PACKAGE_QFN68 = BIT(0), + ODM_PACKAGE_TFBGA90 = BIT(1), + ODM_PACKAGE_TFBGA79 = BIT(2), }; -enum odm_type_gpa_e { - TYPE_GPA0 = 0x0000, - TYPE_GPA1 = 0x0055, - TYPE_GPA2 = 0x00AA, - TYPE_GPA3 = 0x00FF, - TYPE_GPA4 = 0x5500, - TYPE_GPA5 = 0x5555, - TYPE_GPA6 = 0x55AA, - TYPE_GPA7 = 0x55FF, - TYPE_GPA8 = 0xAA00, - TYPE_GPA9 = 0xAA55, - TYPE_GPA10 = 0xAAAA, - TYPE_GPA11 = 0xAAFF, - TYPE_GPA12 = 0xFF00, - TYPE_GPA13 = 0xFF55, - TYPE_GPA14 = 0xFFAA, - TYPE_GPA15 = 0xFFFF, +enum odm_type_gpa { + TYPE_GPA0 = 0x0000, + TYPE_GPA1 = 0x0055, + TYPE_GPA2 = 0x00AA, + TYPE_GPA3 = 0x00FF, + TYPE_GPA4 = 0x5500, + TYPE_GPA5 = 0x5555, + TYPE_GPA6 = 0x55AA, + TYPE_GPA7 = 0x55FF, + TYPE_GPA8 = 0xAA00, + TYPE_GPA9 = 0xAA55, + TYPE_GPA10 = 0xAAAA, + TYPE_GPA11 = 0xAAFF, + TYPE_GPA12 = 0xFF00, + TYPE_GPA13 = 0xFF55, + TYPE_GPA14 = 0xFFAA, + TYPE_GPA15 = 0xFFFF, }; -enum odm_type_apa_e { - TYPE_APA0 = 0x0000, - TYPE_APA1 = 0x0055, - TYPE_APA2 = 0x00AA, - TYPE_APA3 = 0x00FF, - TYPE_APA4 = 0x5500, - TYPE_APA5 = 0x5555, - TYPE_APA6 = 0x55AA, - TYPE_APA7 = 0x55FF, - TYPE_APA8 = 0xAA00, - TYPE_APA9 = 0xAA55, - TYPE_APA10 = 0xAAAA, - TYPE_APA11 = 0xAAFF, - TYPE_APA12 = 0xFF00, - TYPE_APA13 = 0xFF55, - TYPE_APA14 = 0xFFAA, - TYPE_APA15 = 0xFFFF, +enum odm_type_apa { + TYPE_APA0 = 0x0000, + TYPE_APA1 = 0x0055, + TYPE_APA2 = 0x00AA, + TYPE_APA3 = 0x00FF, + TYPE_APA4 = 0x5500, + TYPE_APA5 = 0x5555, + TYPE_APA6 = 0x55AA, + TYPE_APA7 = 0x55FF, + TYPE_APA8 = 0xAA00, + TYPE_APA9 = 0xAA55, + TYPE_APA10 = 0xAAAA, + TYPE_APA11 = 0xAAFF, + TYPE_APA12 = 0xFF00, + TYPE_APA13 = 0xFF55, + TYPE_APA14 = 0xFFAA, + TYPE_APA15 = 0xFFFF, }; -enum odm_type_glna_e { - TYPE_GLNA0 = 0x0000, - TYPE_GLNA1 = 0x0055, - TYPE_GLNA2 = 0x00AA, - TYPE_GLNA3 = 0x00FF, - TYPE_GLNA4 = 0x5500, - TYPE_GLNA5 = 0x5555, - TYPE_GLNA6 = 0x55AA, - TYPE_GLNA7 = 0x55FF, - TYPE_GLNA8 = 0xAA00, - TYPE_GLNA9 = 0xAA55, - TYPE_GLNA10 = 0xAAAA, - TYPE_GLNA11 = 0xAAFF, - TYPE_GLNA12 = 0xFF00, - TYPE_GLNA13 = 0xFF55, - TYPE_GLNA14 = 0xFFAA, - TYPE_GLNA15 = 0xFFFF, +enum odm_type_glna { + TYPE_GLNA0 = 0x0000, + TYPE_GLNA1 = 0x0055, + TYPE_GLNA2 = 0x00AA, + TYPE_GLNA3 = 0x00FF, + TYPE_GLNA4 = 0x5500, + TYPE_GLNA5 = 0x5555, + TYPE_GLNA6 = 0x55AA, + TYPE_GLNA7 = 0x55FF, + TYPE_GLNA8 = 0xAA00, + TYPE_GLNA9 = 0xAA55, + TYPE_GLNA10 = 0xAAAA, + TYPE_GLNA11 = 0xAAFF, + TYPE_GLNA12 = 0xFF00, + TYPE_GLNA13 = 0xFF55, + TYPE_GLNA14 = 0xFFAA, + TYPE_GLNA15 = 0xFFFF, }; -enum odm_type_alna_e { - TYPE_ALNA0 = 0x0000, - TYPE_ALNA1 = 0x0055, - TYPE_ALNA2 = 0x00AA, - TYPE_ALNA3 = 0x00FF, - TYPE_ALNA4 = 0x5500, - TYPE_ALNA5 = 0x5555, - TYPE_ALNA6 = 0x55AA, - TYPE_ALNA7 = 0x55FF, - TYPE_ALNA8 = 0xAA00, - TYPE_ALNA9 = 0xAA55, - TYPE_ALNA10 = 0xAAAA, - TYPE_ALNA11 = 0xAAFF, - TYPE_ALNA12 = 0xFF00, - TYPE_ALNA13 = 0xFF55, - TYPE_ALNA14 = 0xFFAA, - TYPE_ALNA15 = 0xFFFF, +enum odm_type_alna { + TYPE_ALNA0 = 0x0000, + TYPE_ALNA1 = 0x0055, + TYPE_ALNA2 = 0x00AA, + TYPE_ALNA3 = 0x00FF, + TYPE_ALNA4 = 0x5500, + TYPE_ALNA5 = 0x5555, + TYPE_ALNA6 = 0x55AA, + TYPE_ALNA7 = 0x55FF, + TYPE_ALNA8 = 0xAA00, + TYPE_ALNA9 = 0xAA55, + TYPE_ALNA10 = 0xAAAA, + TYPE_ALNA11 = 0xAAFF, + TYPE_ALNA12 = 0xFF00, + TYPE_ALNA13 = 0xFF55, + TYPE_ALNA14 = 0xFFAA, + TYPE_ALNA15 = 0xFFFF, }; +#define PAUSE_FAIL 0 +#define PAUSE_SUCCESS 1 -enum odm_rf_radio_path_e { - ODM_RF_PATH_A = 0, /* Radio path A */ - ODM_RF_PATH_B = 1, /* Radio path B */ - ODM_RF_PATH_C = 2, /* Radio path C */ - ODM_RF_PATH_D = 3, /* Radio path D */ - ODM_RF_PATH_AB, - ODM_RF_PATH_AC, - ODM_RF_PATH_AD, - ODM_RF_PATH_BC, - ODM_RF_PATH_BD, - ODM_RF_PATH_CD, - ODM_RF_PATH_ABC, - ODM_RF_PATH_ACD, - ODM_RF_PATH_BCD, - ODM_RF_PATH_ABCD, - /* ODM_RF_PATH_MAX, */ /* Max RF number 90 support */ +enum odm_parameter_init { + ODM_PRE_SETTING = 0, + ODM_POST_SETTING = 1, + ODM_INIT_FW_SETTING }; -enum odm_parameter_init_e { - ODM_PRE_SETTING = 0, - ODM_POST_SETTING = 1, - ODM_INIT_FW_SETTING +enum phydm_pause_type { + PHYDM_PAUSE = 1, /*Pause & Set new value*/ + PHYDM_PAUSE_NO_SET = 2, /*Pause & Stay in current value*/ + PHYDM_RESUME = 3 +}; + +enum phydm_pause_level { + PHYDM_PAUSE_RELEASE = -1, + PHYDM_PAUSE_LEVEL_0 = 0, /* @Low Priority function */ + PHYDM_PAUSE_LEVEL_1 = 1, /* @Middle Priority function */ + PHYDM_PAUSE_LEVEL_2 = 2, /* @High priority function (ex: Check hang function) */ + PHYDM_PAUSE_LEVEL_3 = 3, /* @Debug function (the highest priority) */ + PHYDM_PAUSE_MAX_NUM = 4 +}; + +enum phydm_dis_hw_fun { + HW_FUN_DIS = 0, /*@Disable a cetain HW function & backup the original value*/ + HW_FUN_RESUME = 1 /*Revert */ }; #endif diff --git a/hal/phydm/phydm_precomp.h b/hal/phydm/phydm_precomp.h index c7c2bc7..5d44a30 100644 --- a/hal/phydm/phydm_precomp.h +++ b/hal/phydm/phydm_precomp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,28 +8,34 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -#ifndef __ODM_PRECOMP_H__ +#ifndef __ODM_PRECOMP_H__ #define __ODM_PRECOMP_H__ #include "phydm_types.h" +#include "halrf/halrf_features.h" #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "Precomp.h" /* We need to include mp_precomp.h due to batch file setting. */ + #include "Precomp.h" /* @We need to include mp_precomp.h due to batch file setting. */ #else #define TEST_FALG___ 1 #endif -/* 2 Config Flags and Structs - defined by each ODM type */ +/* @2 Config Flags and Structs - defined by each ODM type */ #if (DM_ODM_SUPPORT_TYPE == ODM_AP) #include "../8192cd_cfg.h" @@ -37,18 +43,25 @@ #include "../8192cd.h" #include "../8192cd_util.h" + #include "../8192cd_hw.h" #ifdef _BIG_ENDIAN_ #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG #else #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE #endif - #ifdef AP_BUILD_WORKAROUND - #include "../8192cd_headers.h" - #include "../8192cd_debug.h" - #endif + #include "../8192cd_headers.h" + #include "../8192cd_debug.h" #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef DM_ODM_CE_MAC80211 + #include "../wifi.h" + #include "rtl_phydm.h" + #elif defined(DM_ODM_CE_MAC80211_V2) + #include "../main.h" + #include "../hw.h" + #include "../fw.h" + #endif #define __PACK #define __WLAN_ATTRIB_PACK__ #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) @@ -56,44 +69,58 @@ #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE #define __PACK #define __WLAN_ATTRIB_PACK__ +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + #include + #include + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #define __PACK #endif -/* 2 OutSrc Header Files */ +/* @2 OutSrc Header Files */ #include "phydm.h" #include "phydm_hwconfig.h" +#include "phydm_phystatus.h" #include "phydm_debug.h" #include "phydm_regdefine11ac.h" #include "phydm_regdefine11n.h" #include "phydm_interface.h" #include "phydm_reg.h" - -#include "phydm_adc_sampling.h" - -#if (DM_ODM_SUPPORT_TYPE & ODM_CE) - -void -phy_set_tx_power_limit( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *regulation, - u8 *band, - u8 *bandwidth, - u8 *rate_section, - u8 *rf_path, - u8 *channel, - u8 *power_limit -); +#include "halrf/halrf_debug.h" + +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && \ + (!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2)) + +void phy_set_tx_power_limit( + struct dm_struct *dm, + u8 *regulation, + u8 *band, + u8 *bandwidth, + u8 *rate_section, + u8 *rf_path, + u8 *channel, + u8 *power_limit); + +enum hal_status +rtw_phydm_fw_iqk( + struct dm_struct *dm, + u8 clear, + u8 segment); + +enum hal_status +rtw_phydm_cfg_phy_para( + struct dm_struct *dm, + enum phydm_halmac_param config_type, + u32 offset, + u32 data, + u32 mask, + enum rf_path e_rf_path, + u32 delay_time); #endif -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - #define RTL8703B_SUPPORT 0 - #define RTL8188F_SUPPORT 0 - #define RTL8723D_SUPPORT 0 -#endif - -/* JJ ADD 20161014 */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_ADSL|ODM_AP|ODM_IOT)) +/* @Judy ADD 20180125 */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_IOT)) #define RTL8710B_SUPPORT 0 #endif @@ -106,80 +133,82 @@ phy_set_tx_power_limit( #endif #endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#define RTL8197F_SUPPORT 0 /*@Just for PHYDM API development*/ +#define RTL8195B_SUPPORT 0 /*@Just for PHYDM API development*/ +#define RTL8198F_SUPPORT 0 /*@Just for PHYDM API development*/ +#endif + #if (RTL8188E_SUPPORT == 1) - #include "rtl8188e/hal8188erateadaptive.h" /* for RA,Power training */ + #include "rtl8188e/hal8188erateadaptive.h" /* @for RA,Power training */ #include "rtl8188e/halhwimg8188e_mac.h" #include "rtl8188e/halhwimg8188e_rf.h" #include "rtl8188e/halhwimg8188e_bb.h" - #include "rtl8188e/halhwimg8188e_t_fw.h" - #include "rtl8188e/halhwimg8188e_s_fw.h" #include "rtl8188e/phydm_regconfig8188e.h" #include "rtl8188e/phydm_rtl8188e.h" #include "rtl8188e/hal8188ereg.h" #include "rtl8188e/version_rtl8188e.h" #if (DM_ODM_SUPPORT_TYPE == ODM_CE) #include "rtl8188e_hal.h" - #include "rtl8188e/halphyrf_8188e_ce.h" + #include "halrf/rtl8188e/halrf_8188e_ce.h" #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8188e/halphyrf_8188e_win.h" + #include "halrf/rtl8188e/halrf_8188e_win.h" #endif #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8188e/halphyrf_8188e_ap.h" + #include "halrf/rtl8188e/halrf_8188e_ap.h" #endif -#endif /* 88E END */ +#endif /* @88E END */ #if (RTL8192E_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8192e/halphyrf_8192e_win.h" /*FOR_8192E_IQK*/ + #include "halrf/rtl8192e/halrf_8192e_win.h" /*@FOR_8192E_IQK*/ #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8192e/halphyrf_8192e_ap.h" /*FOR_8192E_IQK*/ + #include "halrf/rtl8192e/halrf_8192e_ap.h" /*@FOR_8192E_IQK*/ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8192e/halphyrf_8192e_ce.h" /*FOR_8192E_IQK*/ + #include "halrf/rtl8192e/halrf_8192e_ce.h" /*@FOR_8192E_IQK*/ #endif - #include "rtl8192e/phydm_rtl8192e.h" /* FOR_8192E_IQK */ + #include "rtl8192e/phydm_rtl8192e.h" /* @FOR_8192E_IQK */ #include "rtl8192e/version_rtl8192e.h" #if (DM_ODM_SUPPORT_TYPE != ODM_AP) #include "rtl8192e/halhwimg8192e_bb.h" #include "rtl8192e/halhwimg8192e_mac.h" #include "rtl8192e/halhwimg8192e_rf.h" #include "rtl8192e/phydm_regconfig8192e.h" - #include "rtl8192e/halhwimg8192e_fw.h" #include "rtl8192e/hal8192ereg.h" #endif #if (DM_ODM_SUPPORT_TYPE == ODM_CE) #include "rtl8192e_hal.h" #endif -#endif /* 92E END */ +#endif /* @92E END */ #if (RTL8812A_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8812a/halphyrf_8812a_win.h" + #include "halrf/rtl8812a/halrf_8812a_win.h" #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8812a/halphyrf_8812a_ap.h" + #include "halrf/rtl8812a/halrf_8812a_ap.h" #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8812a/halphyrf_8812a_ce.h" + #include "halrf/rtl8812a/halrf_8812a_ce.h" #endif - /* #include "rtl8812a/HalPhyRf_8812A.h" */ /* FOR_8812_IQK */ + /* @#include "halrf/rtl8812a/halrf_8812a.h" */ /* @FOR_8812_IQK */ #if (DM_ODM_SUPPORT_TYPE != ODM_AP) #include "rtl8812a/halhwimg8812a_bb.h" #include "rtl8812a/halhwimg8812a_mac.h" #include "rtl8812a/halhwimg8812a_rf.h" #include "rtl8812a/phydm_regconfig8812a.h" - #include "rtl8812a/halhwimg8812a_fw.h" - #include "rtl8812a/phydm_rtl8812a.h" #endif + #include "rtl8812a/phydm_rtl8812a.h" #if (DM_ODM_SUPPORT_TYPE == ODM_CE) #include "rtl8812a_hal.h" #endif #include "rtl8812a/version_rtl8812a.h" -#endif /* 8812 END */ +#endif /* @8812 END */ #if (RTL8814A_SUPPORT == 1) @@ -188,54 +217,50 @@ phy_set_tx_power_limit( #include "rtl8814a/halhwimg8814a_bb.h" #include "rtl8814a/version_rtl8814a.h" #include "rtl8814a/phydm_rtl8814a.h" - #if (DM_ODM_SUPPORT_TYPE != ODM_AP) - #include "rtl8814a/halhwimg8814a_fw.h" - #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8814a/halphyrf_8814a_win.h" + #include "halrf/rtl8814a/halrf_8814a_win.h" #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8814a/halphyrf_8814a_ce.h" + #include "halrf/rtl8814a/halrf_8814a_ce.h" #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - #include "rtl8814a/halphyrf_8814a_ap.h" + #include "halrf/rtl8814a/halrf_8814a_ap.h" #endif #include "rtl8814a/phydm_regconfig8814a.h" #if (DM_ODM_SUPPORT_TYPE == ODM_CE) #include "rtl8814a_hal.h" - #include "rtl8814a/phydm_iqk_8814a.h" + #include "halrf/rtl8814a/halrf_iqk_8814a.h" #endif -#endif /* 8814 END */ +#endif /* @8814 END */ -#if (RTL8881A_SUPPORT == 1)/* FOR_8881_IQK */ +#if (RTL8881A_SUPPORT == 1)/* @FOR_8881_IQK */ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8821a/phydm_iqk_8821a_win.h" + #include "halrf/rtl8821a/halrf_iqk_8821a_win.h" #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8821a/phydm_iqk_8821a_ce.h" + #include "halrf/rtl8821a/halrf_iqk_8821a_ce.h" #else - #include "rtl8821a/phydm_iqk_8821a_ap.h" + #include "halrf/rtl8821a/halrf_iqk_8821a_ap.h" #endif - /* #include "rtl8881a/HalHWImg8881A_BB.h" */ - /* #include "rtl8881a/HalHWImg8881A_MAC.h" */ - /* #include "rtl8881a/HalHWImg8881A_RF.h" */ - /* #include "rtl8881a/odm_RegConfig8881A.h" */ + /* @#include "rtl8881a/HalHWImg8881A_BB.h" */ + /* @#include "rtl8881a/HalHWImg8881A_MAC.h" */ + /* @#include "rtl8881a/HalHWImg8881A_RF.h" */ + /* @#include "rtl8881a/odm_RegConfig8881A.h" */ #endif #if (RTL8723B_SUPPORT == 1) #include "rtl8723b/halhwimg8723b_mac.h" #include "rtl8723b/halhwimg8723b_rf.h" #include "rtl8723b/halhwimg8723b_bb.h" - #include "rtl8723b/halhwimg8723b_fw.h" #include "rtl8723b/phydm_regconfig8723b.h" #include "rtl8723b/phydm_rtl8723b.h" #include "rtl8723b/hal8723breg.h" #include "rtl8723b/version_rtl8723b.h" #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8723b/halphyrf_8723b_win.h" + #include "halrf/rtl8723b/halrf_8723b_win.h" #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8723b/halphyrf_8723b_ce.h" + #include "halrf/rtl8723b/halrf_8723b_ce.h" #include "rtl8723b/halhwimg8723b_mp.h" #include "rtl8723b_hal.h" #else - #include "rtl8723b/halphyrf_8723b_ap.h" + #include "halrf/rtl8723b/halrf_8723b_ap.h" #endif #endif @@ -243,48 +268,59 @@ phy_set_tx_power_limit( #include "rtl8821a/halhwimg8821a_mac.h" #include "rtl8821a/halhwimg8821a_rf.h" #include "rtl8821a/halhwimg8821a_bb.h" - #include "rtl8821a/halhwimg8821a_fw.h" #include "rtl8821a/phydm_regconfig8821a.h" #include "rtl8821a/phydm_rtl8821a.h" #include "rtl8821a/version_rtl8821a.h" #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #include "rtl8821a/halphyrf_8821a_win.h" + #include "halrf/rtl8821a/halrf_8821a_win.h" #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include "rtl8821a/halphyrf_8821a_ce.h" - #include "rtl8821a/phydm_iqk_8821a_ce.h"/*for IQK*/ - #include "rtl8812a/halphyrf_8812a_ce.h"/*for IQK,LCK,Power-tracking*/ + #include "halrf/rtl8821a/halrf_8821a_ce.h" + #include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"/*@for IQK*/ + #include "halrf/rtl8812a/halrf_8812a_ce.h"/*@for IQK,LCK,Power-tracking*/ #include "rtl8812a_hal.h" #else #endif #endif +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#include "../halmac/halmac_reg2.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#include "../halmac/halmac_reg2.h" +#endif + + #if (RTL8822B_SUPPORT == 1) #include "rtl8822b/halhwimg8822b_mac.h" #include "rtl8822b/halhwimg8822b_rf.h" #include "rtl8822b/halhwimg8822b_bb.h" - #include "rtl8822b/halhwimg8822b_fw.h" #include "rtl8822b/phydm_regconfig8822b.h" - #include "rtl8822b/halphyrf_8822b.h" + #include "halrf/rtl8822b/halrf_8822b.h" #include "rtl8822b/phydm_rtl8822b.h" #include "rtl8822b/phydm_hal_api8822b.h" #include "rtl8822b/version_rtl8822b.h" #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include /* struct HAL_DATA_TYPE */ - #include /* RX_SMOOTH_FACTOR, reg definition and etc.*/ + #ifdef DM_ODM_CE_MAC80211 + #include "../halmac/halmac_reg_8822b.h" + #elif defined(DM_ODM_CE_MAC80211_V2) + #include "../halmac/halmac_reg_8822b.h" + #else + #include /* @struct HAL_DATA_TYPE */ + #include /* @RX_SMOOTH_FACTOR, reg definition and etc.*/ + #endif #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) #endif #endif #if (RTL8703B_SUPPORT == 1) + #include "rtl8703b/phydm_rtl8703b.h" #include "rtl8703b/phydm_regconfig8703b.h" #include "rtl8703b/halhwimg8703b_mac.h" #include "rtl8703b/halhwimg8703b_rf.h" #include "rtl8703b/halhwimg8703b_bb.h" - #include "rtl8703b/halhwimg8703b_fw.h" - #include "rtl8703b/halphyrf_8703b.h" + #include "halrf/rtl8703b/halrf_8703b.h" #include "rtl8703b/version_rtl8703b.h" #if (DM_ODM_SUPPORT_TYPE == ODM_CE) #include "rtl8703b_hal.h" @@ -295,11 +331,10 @@ phy_set_tx_power_limit( #include "rtl8188f/halhwimg8188f_mac.h" #include "rtl8188f/halhwimg8188f_rf.h" #include "rtl8188f/halhwimg8188f_bb.h" - #include "rtl8188f/halhwimg8188f_fw.h" #include "rtl8188f/hal8188freg.h" #include "rtl8188f/phydm_rtl8188f.h" #include "rtl8188f/phydm_regconfig8188f.h" - #include "rtl8188f/halphyrf_8188f.h" /* for IQK,LCK,Power-tracking */ + #include "halrf/rtl8188f/halrf_8188f.h" /*@for IQK,LCK,Power-tracking*/ #include "rtl8188f/version_rtl8188f.h" #if (DM_ODM_SUPPORT_TYPE == ODM_CE) #include "rtl8188f_hal.h" @@ -313,18 +348,19 @@ phy_set_tx_power_limit( #include "rtl8723d/halhwimg8723d_mac.h" #include "rtl8723d/halhwimg8723d_rf.h" #include "rtl8723d/phydm_regconfig8723d.h" - #include "rtl8723d/halhwimg8723d_fw.h" #include "rtl8723d/hal8723dreg.h" #include "rtl8723d/phydm_rtl8723d.h" - #include "rtl8723d/halphyrf_8723d.h" + #include "halrf/rtl8723d/halrf_8723d.h" #include "rtl8723d/version_rtl8723d.h" #endif #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef DM_ODM_CE_MAC80211 + #else #include "rtl8723d_hal.h" + #endif #endif -#endif /* 8723D End */ +#endif /* @8723D End */ -/* JJ ADD 20161014 */ #if (RTL8710B_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE != ODM_AP) @@ -332,16 +368,15 @@ phy_set_tx_power_limit( #include "rtl8710b/halhwimg8710b_mac.h" #include "rtl8710b/halhwimg8710b_rf.h" #include "rtl8710b/phydm_regconfig8710b.h" - #include "rtl8710b/halhwimg8710b_fw.h" #include "rtl8710b/hal8710breg.h" #include "rtl8710b/phydm_rtl8710b.h" - #include "rtl8710b/halphyrf_8710b.h" + #include "halrf/rtl8710b/halrf_8710b.h" #include "rtl8710b/version_rtl8710b.h" #endif #if (DM_ODM_SUPPORT_TYPE == ODM_CE) #include "rtl8710b_hal.h" #endif -#endif /* 8710B End */ +#endif /* @8710B End */ #if (RTL8197F_SUPPORT == 1) #include "rtl8197f/halhwimg8197f_mac.h" @@ -351,25 +386,84 @@ phy_set_tx_power_limit( #include "rtl8197f/version_rtl8197f.h" #include "rtl8197f/phydm_rtl8197f.h" #include "rtl8197f/phydm_regconfig8197f.h" - #include "rtl8197f/halphyrf_8197f.h" - #include "rtl8197f/phydm_iqk_8197f.h" + #include "halrf/rtl8197f/halrf_8197f.h" + #include "halrf/rtl8197f/halrf_iqk_8197f.h" + #include "halrf/rtl8197f/halrf_dpk_8197f.h" #endif #if (RTL8821C_SUPPORT == 1) #include "rtl8821c/phydm_hal_api8821c.h" - #include "rtl8821c/halhwimg8821c_testchip_mac.h" - #include "rtl8821c/halhwimg8821c_testchip_rf.h" - #include "rtl8821c/halhwimg8821c_testchip_bb.h" #include "rtl8821c/halhwimg8821c_mac.h" #include "rtl8821c/halhwimg8821c_rf.h" #include "rtl8821c/halhwimg8821c_bb.h" - #include "rtl8821c/halhwimg8821c_fw.h" #include "rtl8821c/phydm_regconfig8821c.h" - #include "rtl8821c/halphyrf_8821c.h" + #include "halrf/rtl8821c/halrf_8821c.h" #include "rtl8821c/version_rtl8821c.h" #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef DM_ODM_CE_MAC80211 + #include "../halmac/halmac_reg_8821c.h" + #else #include "rtl8821c_hal.h" + #endif + #endif +#endif + +#if (RTL8192F_SUPPORT == 1) + #include "rtl8192f/halhwimg8192f_mac.h" + #include "rtl8192f/halhwimg8192f_rf.h" + #include "rtl8192f/halhwimg8192f_bb.h" + #include "rtl8192f/phydm_hal_api8192f.h" + #include "rtl8192f/version_rtl8192f.h" + #include "rtl8192f/phydm_rtl8192f.h" + #include "rtl8192f/phydm_regconfig8192f.h" + #include "halrf/rtl8192f/halrf_8192f.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "halrf/rtl8192f/halrf_dpk_8192f.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8192f_hal.h" #endif #endif -#endif /* __ODM_PRECOMP_H__ */ +#if (RTL8195B_SUPPORT == 1) + #include "halrf/rtl8195b/halrf_8195b.h" + #include "rtl8195b/phydm_hal_api8195b.h" + #include "rtl8195b/phydm_regconfig8195b.h" + #include "rtl8195b/halhwimg8195b_mac.h" + #include "rtl8195b/halhwimg8195b_rf.h" + #include "rtl8195b/halhwimg8195b_bb.h" + #include "rtl8195b/version_rtl8195b.h" + #include /*@HAL_DATA_TYPE*/ +#endif + +#if (RTL8198F_SUPPORT == 1) + #include "rtl8198f/phydm_regconfig8198f.h" + #include "rtl8198f/phydm_hal_api8198f.h" + #include "rtl8198f/halhwimg8198f_mac.h" + #include "rtl8198f/halhwimg8198f_rf.h" + #include "rtl8198f/halhwimg8198f_bb.h" + #include "rtl8198f/version_rtl8198f.h" + #include "halrf/rtl8198f/halrf_8198f.h" + #include "halrf/rtl8198f/halrf_iqk_8198f.h" +#endif + +#if (RTL8822C_SUPPORT) + #include "rtl8822c/halhwimg8822c_mac.h" + #include "rtl8822c/halhwimg8822c_rf.h" + #include "rtl8822c/halhwimg8822c_bb.h" + #include "rtl8822c/phydm_regconfig8822c.h" + /*@#include "halrf/rtl8822c/halrf_8822c.h"*/ + #include "rtl8822c/phydm_hal_api8822c.h" + #include "rtl8822c/version_rtl8822c.h" +#endif +#if (RTL8814B_SUPPORT == 1) + /*#include "rtl8814b/halhwimg8814b_mac.h"*/ + /*#include "rtl8814b/halhwimg8814b_rf.h"*/ + /*#include "rtl8814b/halhwimg8814b_bb.h"*/ + /*#include "rtl8814b/phydm_regconfig8814b.h"*/ + /*@#include "halrf/rtl8814b/halrf_8814b.h"*/ + #include "rtl8814b/phydm_hal_api8814b.h" + /*#include "rtl8814b/version_rtl8814b.h"*/ +#endif + +#endif /* @__ODM_PRECOMP_H__ */ diff --git a/hal/phydm/phydm_primary_cca.c b/hal/phydm/phydm_primary_cca.c new file mode 100644 index 0000000..dec6c53 --- /dev/null +++ b/hal/phydm/phydm_primary_cca.c @@ -0,0 +1,173 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" +#ifdef PHYDM_PRIMARY_CCA + +void phydm_write_dynamic_cca( + void *dm_void, + u8 curr_mf_state + + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca; + + if (pri_cca->mf_state == curr_mf_state) + return; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (curr_mf_state == MF_USC_LSC) { + odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC); + /*@40M OFDM MF CCA threshold*/ + odm_set_bb_reg(dm, R_0xc84, 0xf0000000, + pri_cca->cca_th_40m_bkp); + } else { + odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state); + /*@40M OFDM MF CCA threshold*/ + odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0); + } + } + + pri_cca->mf_state = curr_mf_state; + PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n", + ((curr_mf_state == MF_USC_LSC) ? "D" : + ((curr_mf_state == MF_LSC) ? "L" : "U")), curr_mf_state); +} + +void phydm_primary_cca_reset( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca; + + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Reset\n"); + pri_cca->mf_state = 0xff; + pri_cca->pre_bw = (enum channel_width)0xff; + phydm_write_dynamic_cca(dm, MF_USC_LSC); +} + +void phydm_primary_cca_11n( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca; + enum channel_width curr_bw = (enum channel_width)*dm->band_width; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + if (!dm->is_linked) { + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][No Link!!!]\n"); + + if (pri_cca->pri_cca_is_become_linked) { + phydm_primary_cca_reset(dm); + pri_cca->pri_cca_is_become_linked = dm->is_linked; + } + return; + } else { + if (!pri_cca->pri_cca_is_become_linked) { + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][Linked !!!]\n"); + pri_cca->pri_cca_is_become_linked = dm->is_linked; + } + } + + if (curr_bw != pri_cca->pre_bw) { + PHYDM_DBG(dm, DBG_PRI_CCA, "[Primary CCA] start ==>\n"); + pri_cca->pre_bw = curr_bw; + + if (curr_bw == CHANNEL_WIDTH_40) { + if (*dm->sec_ch_offset == SECOND_CH_AT_LSB) { + /* Primary CH @ upper sideband*/ + PHYDM_DBG(dm, DBG_PRI_CCA, + "BW40M, Primary CH at USB\n"); + phydm_write_dynamic_cca(dm, MF_USC); + } else { + /*Primary CH @ lower sideband*/ + PHYDM_DBG(dm, DBG_PRI_CCA, + "BW40M, Primary CH at LSB\n"); + phydm_write_dynamic_cca(dm, MF_LSC); + } + } else { + PHYDM_DBG(dm, DBG_PRI_CCA, "Not BW40M, USB + LSB\n"); + phydm_primary_cca_reset(dm); + } + } +} + +boolean +odm_dynamic_primary_cca_dup_rts(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca; + + return pri_cca->dup_rts_flag; +} + +void phydm_primary_cca_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + if (!(dm->support_ic_type & ODM_IC_11N_SERIES)) + return; + + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Init ==>\n"); +#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) + pri_cca->dup_rts_flag = 0; + pri_cca->intf_flag = 0; + pri_cca->intf_type = 0; + pri_cca->monitor_flag = 0; + pri_cca->pri_cca_flag = 0; + pri_cca->ch_offset = 0; +#endif + pri_cca->mf_state = 0xff; + pri_cca->pre_bw = (enum channel_width)0xff; + pri_cca->cca_th_40m_bkp = (u8)odm_get_bb_reg(dm, R_0xc84, 0xf0000000); +} + +void phydm_primary_cca(void *dm_void) +{ +#ifdef PHYDM_PRIMARY_CCA + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ic_type & ODM_IC_11N_SERIES)) + return; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + phydm_primary_cca_11n(dm); + +#endif +} +#endif diff --git a/hal/phydm/phydm_primary_cca.h b/hal/phydm/phydm_primary_cca.h new file mode 100644 index 0000000..9a64750 --- /dev/null +++ b/hal/phydm/phydm_primary_cca.h @@ -0,0 +1,87 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_PRIMARYCCA_H__ +#define __PHYDM_PRIMARYCCA_H__ + +#ifdef PHYDM_PRIMARY_CCA +#define PRIMARYCCA_VERSION "2.0" + +/*@============================================================*/ +/*@Definition */ +/*@============================================================*/ + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define SECOND_CH_AT_LSB 2 /*@primary CH @ MSB, SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/ +#define SECOND_CH_AT_USB 1 /*@primary CH @ LSB, SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define SECOND_CH_AT_LSB 2 /*@primary CH @ MSB, SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/ +#define SECOND_CH_AT_USB 1 /*@primary CH @ LSB, SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/ +#else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/ +#define SECOND_CH_AT_LSB 1 /*@primary CH @ MSB, SD8: HT_2NDCH_OFFSET_BELOW*/ +#define SECOND_CH_AT_USB 2 /*@primary CH @ LSB, SD8: HT_2NDCH_OFFSET_ABOVE*/ +#endif + +#define OFDMCCA_TH 500 +#define bw_ind_bias 500 +#define PRI_CCA_MONITOR_TIME 30 + +/*@============================================================*/ +/*structure and define*/ +/*@============================================================*/ +enum primary_cca_ch_position { /*N-series REG0xc6c[8:7]*/ + MF_USC_LSC = 0, + MF_LSC = 1, + MF_USC = 2 +}; + +struct phydm_pricca_struct { + #if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) + u8 pri_cca_flag; + u8 intf_flag; + u8 intf_type; + u8 monitor_flag; + u8 ch_offset; + #endif + u8 dup_rts_flag; + u8 cca_th_40m_bkp; /*@c84[31:28]*/ + enum channel_width pre_bw; + u8 pri_cca_is_become_linked; + u8 mf_state; +}; + +/*@============================================================*/ +/*@function prototype*/ +/*@============================================================*/ +void phydm_write_dynamic_cca(void *dm_void, u8 curr_mf_state); + +boolean odm_dynamic_primary_cca_dup_rts(void *dm_void); + +void phydm_primary_cca_init(void *dm_void); + +void phydm_primary_cca(void *dm_void); +#endif /*@#ifdef PHYDM_PRIMARY_CCA*/ +#endif /*@#ifndef __PHYDM_PRIMARYCCA_H__*/ + diff --git a/hal/phydm/phydm_psd.c b/hal/phydm/phydm_psd.c index 91246ce..7f54bb1 100644 --- a/hal/phydm/phydm_psd.c +++ b/hal/phydm/phydm_psd.c @@ -1,448 +1,380 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -//============================================================ -// include files -//============================================================ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/****************************************************************************** + * include files + *****************************************************************************/ #include "mp_precomp.h" -#include "phydm_precomp.h" - -#if (CONFIG_PSD_TOOL == 1) - -u32 -phydm_get_psd_data( - void *p_dm_void, - u32 psd_tone_idx, - u32 igi - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); - u32 psd_report = 0; - - odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, 0x3ff, psd_tone_idx); - - odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, BIT(22), 1); /*PSD trigger start*/ - ODM_delay_us(10); - odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, BIT(22), 0); /*PSD trigger stop*/ - - psd_report = odm_get_bb_reg(p_dm_odm, p_dm_psd_table->psd_report_reg, 0xffff); - psd_report = odm_convert_to_db(psd_report) + igi; - - return psd_report; -} - -u8 -phydm_psd_stop_trx( - void *p_dm_void - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); - u32 i; - u8 trx_idle_success = FALSE; - u32 dbg_port_value = 0; - - /*[Stop TRX]---------------------------------------------------------------------*/ - if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, 0x0) == FALSE) /*set debug port to 0x0*/ - return STOP_TRX_FAIL; - - for (i = 0; i<10000; i++) { - dbg_port_value = phydm_get_bb_dbg_port_value(p_dm_odm); - if ((dbg_port_value & (BIT(17) | BIT(3))) == 0) /* PHYTXON && CCA_all */ { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD wait for ((%d)) times\n", i)); - - trx_idle_success = TRUE; - break; - } - } - - if (trx_idle_success) { - - odm_set_bb_reg(p_dm_odm, 0x520, 0xff0000, 0xff); /*pause all TX queue*/ - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0); /*disable CCK block*/ - odm_set_bb_reg(p_dm_odm, 0x838, BIT(1), 1); /*disable OFDM RX CCA*/ - } else { - /*TBD*/ - odm_set_bb_reg(p_dm_odm, 0x800, BIT(24), 0); /* disable whole CCK block */ - odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ - } - - } else { - return STOP_TRX_FAIL; - } - - phydm_release_bb_dbg_port(p_dm_odm); - - return STOP_TRX_SUCCESS; - -} - -u8 psd_result_cali_tone_8821[7]= {21, 28, 33, 93, 98, 105, 127}; -u8 psd_result_cali_val_8821[7] = {67,69,71,72,71,69,67}; - -void -phydm_psd( - void *p_dm_void, - u32 igi, - u16 start_point, - u16 stop_point - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); - u32 i = 0, mod_tone_idx; - u32 t = 0; - u16 fft_max_half_bw; - u32 psd_igi_a_reg; - u32 psd_igi_b_reg; - u16 psd_fc_channel = p_dm_psd_table->psd_fc_channel; - u8 ag_rf_mode_reg = 0; - u8 rf_reg18_9_8 = 0; - u32 psd_result_tmp = 0; - u8 psd_result = 0; - u8 psd_result_cali_tone[7] = {0}; - u8 psd_result_cali_val[7] = {0}; - u8 noise_table_idx = 0; - u8 psd_result_cali_tmp = 0; - - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - odm_move_memory(p_dm_odm, psd_result_cali_tone, psd_result_cali_tone_8821, 7); - odm_move_memory(p_dm_odm, psd_result_cali_val, psd_result_cali_val_8821, 7); - } - - p_dm_psd_table->psd_in_progress = 1; - - /*[Stop DIG]*/ - p_dm_odm->support_ability &= ~(ODM_BB_DIG); - p_dm_odm->support_ability &= ~(ODM_BB_FA_CNT); - - - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD Start =>\n")); - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - psd_igi_a_reg = 0xc50; - psd_igi_b_reg = 0xe50; - } else { - psd_igi_a_reg = 0xc50; - psd_igi_b_reg = 0xc58; - } - - /*[back up IGI]*/ - p_dm_psd_table->initial_gain_backup = odm_get_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff); - odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/ - odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/ - ODM_delay_us(10); - - if (phydm_psd_stop_trx(p_dm_odm) == STOP_TRX_FAIL) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("STOP_TRX_FAIL\n")); - return; - } - - /*[Set IGI]*/ - odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, igi); - odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, igi); - - /*[Backup RF Reg]*/ - p_dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); - - if (psd_fc_channel > 14) { - - rf_reg18_9_8 = 1; - - if (36 <= psd_fc_channel && psd_fc_channel <= 64) - ag_rf_mode_reg = 0x1; - else if (100 <= psd_fc_channel && psd_fc_channel <= 140) - ag_rf_mode_reg = 0x3; - else if (140 < psd_fc_channel) - ag_rf_mode_reg = 0x5; - } - - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xff, psd_fc_channel); /* Set RF fc*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0x300, rf_reg18_9_8); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xc00, p_dm_psd_table->psd_bw_rf_reg); /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xf0000, ag_rf_mode_reg); /* Set RF ag fc mode*/ - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("0xc50=((0x%x))\n", odm_get_bb_reg(p_dm_odm, 0xc50, MASKDWORD))); - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("RF0x0=((0x%x))\n", odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, RFREGOFFSETMASK)));*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("RF0x18=((0x%x))\n", odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK))); - - /*[Stop 3-wires]*/ - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, 0xc00, 0xf, 0x4);/* hardware 3-wire off */ - odm_set_bb_reg(p_dm_odm, 0xe00, 0xf, 0x4);/* hardware 3-wire off */ - } else { - odm_set_bb_reg(p_dm_odm, 0x88c, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ - } - ODM_delay_us(10); - - if (stop_point > (p_dm_psd_table->fft_smp_point-1)) - stop_point = (p_dm_psd_table->fft_smp_point-1); - - if (start_point > (p_dm_psd_table->fft_smp_point-1)) - start_point = (p_dm_psd_table->fft_smp_point-1); - - if (start_point > stop_point) - stop_point = start_point; - - - for (i = start_point; i <= stop_point; i++ ) { - - fft_max_half_bw = (p_dm_psd_table->fft_smp_point)>>1; - - if (i < fft_max_half_bw) { - mod_tone_idx = i + fft_max_half_bw; - } else { - mod_tone_idx = i - fft_max_half_bw; - } - - psd_result_tmp = 0; - for (t = 0; t < p_dm_psd_table->sw_avg_time; t++) { - psd_result_tmp += phydm_get_psd_data(p_dm_odm, mod_tone_idx, igi); - /**/ - } - psd_result = (u8)((psd_result_tmp/p_dm_psd_table->sw_avg_time)) - p_dm_psd_table->psd_pwr_common_offset; - - if( p_dm_psd_table->fft_smp_point == 128) { - - if (p_dm_psd_table->noise_k_en) { - if (i > psd_result_cali_tone[noise_table_idx]) { - noise_table_idx ++; - } - - if (noise_table_idx > 6) - noise_table_idx = 6; - - if (psd_result >= psd_result_cali_val[noise_table_idx]) - psd_result = psd_result - psd_result_cali_val[noise_table_idx]; - else - psd_result = 0; - } - - p_dm_psd_table->psd_result[i] = psd_result; - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[%d] N_cali = %d, PSD = %d\n", mod_tone_idx, psd_result_cali_val[noise_table_idx], psd_result)); - - } - - /*[Start 3-wires]*/ - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - odm_set_bb_reg(p_dm_odm, 0xc00, 0xf, 0x7);/* hardware 3-wire on */ - odm_set_bb_reg(p_dm_odm, 0xe00, 0xf, 0x7);/* hardware 3-wire on */ - } else { - odm_set_bb_reg(p_dm_odm, 0x88c, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ - } - ODM_delay_us(10); - - /*[Revert Reg]*/ - odm_set_bb_reg(p_dm_odm, 0x520, 0xff0000, 0x0); /*start all TX queue*/ - odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 1); /*enable CCK block*/ - odm_set_bb_reg(p_dm_odm, 0x838, BIT(1), 0); /*enable OFDM RX CCA*/ - - odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, p_dm_psd_table->initial_gain_backup); - odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, p_dm_psd_table->initial_gain_backup); - - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, p_dm_psd_table->rf_0x18_bkp); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD finished\n\n")); - - p_dm_odm->support_ability |= ODM_BB_DIG; - p_dm_odm->support_ability |= ODM_BB_FA_CNT; - p_dm_psd_table->psd_in_progress = 0; - - -} - -void -phydm_psd_para_setting( - void *p_dm_void, - u8 sw_avg_time, - u8 hw_avg_time, - u8 i_q_setting, - u16 fft_smp_point, - u8 ant_sel, - u8 psd_input, - u8 channel, - u8 noise_k_en - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); - u32 avg_temp; - u8 fft_smp_point_idx = 0; - - p_dm_psd_table->fft_smp_point = fft_smp_point; - - if (sw_avg_time == 0) - sw_avg_time = 1; - - p_dm_psd_table->sw_avg_time = sw_avg_time; - p_dm_psd_table->psd_fc_channel = channel; - p_dm_psd_table->noise_k_en = noise_k_en; - - if (fft_smp_point == 128) - fft_smp_point_idx = 0; - else if (fft_smp_point == 256) - fft_smp_point_idx = 1; - else if (fft_smp_point == 512) - fft_smp_point_idx = 2; - else if (fft_smp_point == 1024) - fft_smp_point_idx = 3; - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - odm_set_bb_reg(p_dm_odm, 0x910, BIT(11) | BIT(10), i_q_setting); - odm_set_bb_reg(p_dm_odm, 0x910, BIT(13) | BIT(12), hw_avg_time); - odm_set_bb_reg(p_dm_odm, 0x910, BIT(15) | BIT(14), fft_smp_point_idx); - odm_set_bb_reg(p_dm_odm, 0x910, BIT(17) | BIT(16), ant_sel); - odm_set_bb_reg(p_dm_odm, 0x910, BIT(23), psd_input); - - } else { - - } - - /*bw = (*p_dm_odm->p_band_width); //ODM_BW20M */ - /*channel = *(p_dm_odm->p_channel);*/ - - - - -} - -void -phydm_psd_init( - void *p_dm_void - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD para init\n")); - - p_dm_psd_table->psd_in_progress = FALSE; - - if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { - - p_dm_psd_table->psd_reg = 0x910; - p_dm_psd_table->psd_report_reg = 0xF44; - - if (ODM_IC_11AC_2_SERIES) - p_dm_psd_table->psd_bw_rf_reg = 1; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ - else - p_dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ - - } else { - - p_dm_psd_table->psd_reg = 0x808; - p_dm_psd_table->psd_report_reg = 0x8B4; - p_dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ - } - - if (p_dm_odm->support_ic_type == ODM_RTL8812) - p_dm_psd_table->psd_pwr_common_offset = 0; - else if (p_dm_odm->support_ic_type == ODM_RTL8821) - p_dm_psd_table->psd_pwr_common_offset = 0; - else - p_dm_psd_table->psd_pwr_common_offset = 0; - - phydm_psd_para_setting(p_dm_odm, 1, 2, 3, 128, 0, 0, 7, 0); - /*phydm_psd(p_dm_odm, 0x3c, 0, 127);*/ /* target at -50dBm */ - - -} - -void -phydm_psd_debug( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -) +#include "phydm_precomp.h" + +#ifdef CONFIG_PSD_TOOL +u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - char help[] = "-h"; - u32 var1[10] = {0}; - u32 used = *_used; - u32 out_len = *_out_len; - u8 i; - - if ((strcmp(input[1], help) == 0)) { - PHYDM_SNPRINTF((output + used, out_len - used, "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n")); - PHYDM_SNPRINTF((output + used, out_len - used, "{1} {IGI(hex)} {start_point} {stop_point}\n")); - - } else { - - - PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); - - if (var1[0] == 0) { - - for (i = 1; i < 10; i++) { - if (input[i + 1]) { - PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); - } - } - - PHYDM_SNPRINTF((output + used, out_len - used, "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n", - var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], (u8)var1[7], (u8)var1[8])); - phydm_psd_para_setting(p_dm_odm, (u8)var1[1], (u8)var1[2], (u8)var1[3], (u16)var1[4], (u8)var1[5], (u8)var1[6], (u8)var1[7], (u8)var1[8]); - - } else if (var1[0] == 1) { - - PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]); - PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); - PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); - PHYDM_SNPRINTF((output + used, out_len - used, "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n", var1[1], var1[2], var1[3])); - p_dm_odm->debug_components |= ODM_COMP_API; - phydm_psd(p_dm_odm, var1[1], (u16)var1[2], (u16)var1[3]); - p_dm_odm->debug_components &= (~ODM_COMP_API); - } - - } - - - -} - -u8 -phydm_get_psd_result_table( - void *p_dm_void, - int index - ) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); - u8 temp_result = 0; - - if(index<128) - temp_result = p_dm_psd_table->psd_result[index]; - - return temp_result; - -} - -#endif - + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u32 psd_report = 0; + + odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx); + + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1); /*PSD trigger start*/ + ODM_delay_us(10); + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0); /*PSD trigger stop*/ + + if (dm->support_ic_type & ODM_RTL8821C) { + psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg, + 0xffffff); + psd_report = psd_report >> 5; + } else { + psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg, + 0xffff); + } + psd_report = odm_convert_to_db(psd_report) + igi; + + return psd_report; +} + +u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127}; +u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67}; + +void phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u32 i = 0, mod_tone_idx; + u32 t = 0; + u16 fft_max_half_bw; + u32 psd_igi_a_reg; + u32 psd_igi_b_reg; + u16 psd_fc_channel = dm_psd_table->psd_fc_channel; + u8 ag_rf_mode_reg = 0; + u8 rf_reg18_9_8 = 0; + u32 psd_result_tmp = 0; + u8 psd_result = 0; + u8 psd_result_cali_tone[7] = {0}; + u8 psd_result_cali_val[7] = {0}; + u8 noise_table_idx = 0; + u8 set_result; + + if (dm->support_ic_type == ODM_RTL8821) { + odm_move_memory(dm, psd_result_cali_tone, + psd_result_cali_tone_8821, 7); + odm_move_memory(dm, psd_result_cali_val, + psd_result_cali_val_8821, 7); + } + + dm_psd_table->psd_in_progress = 1; + + /*@[Stop DIG]*/ + dm->support_ability &= ~(ODM_BB_DIG); + dm->support_ability &= ~(ODM_BB_FA_CNT); + + PHYDM_DBG(dm, ODM_COMP_API, "PSD Start =>\n"); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + psd_igi_a_reg = 0xc50; + psd_igi_b_reg = 0xe50; + } else { + psd_igi_a_reg = 0xc50; + psd_igi_b_reg = 0xc58; + } + + /*@[back up IGI]*/ + dm_psd_table->initial_gain_backup = odm_get_bb_reg(dm, psd_igi_a_reg, + 0xff); + odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, 0x6e); /*@IGI target at 0dBm & make it can't CCA*/ + odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, 0x6e); /*@IGI target at 0dBm & make it can't CCA*/ + ODM_delay_us(10); + + if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) { + PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n"); + return; + } + + /*@[Set IGI]*/ + odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, igi); + odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, igi); + + /*@[Backup RF Reg]*/ + dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, + RFREGOFFSETMASK); + dm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18, + RFREGOFFSETMASK); + + if (psd_fc_channel > 14) { + rf_reg18_9_8 = 1; + if (psd_fc_channel >= 36 && psd_fc_channel <= 64) + ag_rf_mode_reg = 0x1; + else if (psd_fc_channel >= 100 && psd_fc_channel <= 140) + ag_rf_mode_reg = 0x3; + else if (psd_fc_channel > 140) + ag_rf_mode_reg = 0x5; + } + + /* RF path-a */ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff, psd_fc_channel); /* Set RF fc*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x300, rf_reg18_9_8); + /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xc00, + dm_psd_table->psd_bw_rf_reg); + /* Set RF ag fc mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xf0000, ag_rf_mode_reg); + + /* RF path-b */ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xff, psd_fc_channel); /* Set RF fc*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, rf_reg18_9_8); + /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xc00, + dm_psd_table->psd_bw_rf_reg); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xf0000, ag_rf_mode_reg); /* Set RF ag fc mode*/ + + PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n", + odm_get_bb_reg(dm, R_0xc50, MASKDWORD)); +#if 0 + /*PHYDM_DBG(dm, ODM_COMP_API, "RF0x0=((0x%x))\n", odm_get_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK));*/ +#endif + PHYDM_DBG(dm, ODM_COMP_API, "RF0x18=((0x%x))\n", + odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK)); + + /*@[Stop 3-wires]*/ + phydm_stop_3_wire(dm, PHYDM_SET); + + ODM_delay_us(10); + + if (stop_point > (dm_psd_table->fft_smp_point - 1)) + stop_point = (dm_psd_table->fft_smp_point - 1); + + if (start_point > (dm_psd_table->fft_smp_point - 1)) + start_point = (dm_psd_table->fft_smp_point - 1); + + if (start_point > stop_point) + stop_point = start_point; + + for (i = start_point; i <= stop_point; i++) { + fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1; + + if (i < fft_max_half_bw) + mod_tone_idx = i + fft_max_half_bw; + else + mod_tone_idx = i - fft_max_half_bw; + + psd_result_tmp = 0; + for (t = 0; t < dm_psd_table->sw_avg_time; t++) + psd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx, + igi); + psd_result = + (u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) - + dm_psd_table->psd_pwr_common_offset; + + if (dm_psd_table->fft_smp_point == 128 && + dm_psd_table->noise_k_en) { + if (i > psd_result_cali_tone[noise_table_idx]) + noise_table_idx++; + + if (noise_table_idx > 6) + noise_table_idx = 6; + + if (psd_result >= psd_result_cali_val[noise_table_idx]) + psd_result = + psd_result - + psd_result_cali_val[noise_table_idx]; + else + psd_result = 0; + + dm_psd_table->psd_result[i] = psd_result; + } + + PHYDM_DBG(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n", + mod_tone_idx, psd_result_cali_val[noise_table_idx], + psd_result); + } + + /*@[Start 3-wires]*/ + phydm_stop_3_wire(dm, PHYDM_REVERT); + + ODM_delay_us(10); + + /*@[Revert Reg]*/ + set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT); + + odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, + dm_psd_table->initial_gain_backup); + odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, + dm_psd_table->initial_gain_backup); + + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, + dm_psd_table->rf_0x18_bkp); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREGOFFSETMASK, + dm_psd_table->rf_0x18_bkp_b); + + PHYDM_DBG(dm, ODM_COMP_API, "PSD finished\n\n"); + + dm->support_ability |= ODM_BB_DIG; + dm->support_ability |= ODM_BB_FA_CNT; + dm_psd_table->psd_in_progress = 0; +} + +void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, + u8 hw_avg_time, u8 i_q_setting, + u16 fft_smp_point, u8 ant_sel, + u8 psd_input, u8 channel, u8 noise_k_en) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u8 fft_smp_point_idx = 0; + + dm_psd_table->fft_smp_point = fft_smp_point; + + if (sw_avg_time == 0) + sw_avg_time = 1; + + dm_psd_table->sw_avg_time = sw_avg_time; + dm_psd_table->psd_fc_channel = channel; + dm_psd_table->noise_k_en = noise_k_en; + + if (fft_smp_point == 128) + fft_smp_point_idx = 0; + else if (fft_smp_point == 256) + fft_smp_point_idx = 1; + else if (fft_smp_point == 512) + fft_smp_point_idx = 2; + else if (fft_smp_point == 1024) + fft_smp_point_idx = 3; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x910, BIT(11) | BIT(10), i_q_setting); + odm_set_bb_reg(dm, R_0x910, BIT(13) | BIT(12), hw_avg_time); + odm_set_bb_reg(dm, R_0x910, BIT(15) | BIT(14), + fft_smp_point_idx); + odm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel); + odm_set_bb_reg(dm, R_0x910, BIT(23), psd_input); +#if 0 + } else { /*ODM_IC_11N_SERIES*/ +#endif + } + + /*@bw = (*dm->band_width); //ODM_BW20M */ + /*@channel = *(dm->channel);*/ +} + +void phydm_psd_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + + PHYDM_DBG(dm, ODM_COMP_API, "PSD para init\n"); + + dm_psd_table->psd_in_progress = false; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + dm_psd_table->psd_reg = 0x910; + dm_psd_table->psd_report_reg = 0xF44; + + if (ODM_IC_11AC_2_SERIES) + /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + dm_psd_table->psd_bw_rf_reg = 1; + else + /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + dm_psd_table->psd_bw_rf_reg = 2; + + } else { + dm_psd_table->psd_reg = 0x808; + dm_psd_table->psd_report_reg = 0x8B4; + /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + dm_psd_table->psd_bw_rf_reg = 2; + } + + dm_psd_table->psd_pwr_common_offset = 0; + + phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0); +#if 0 + /*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */ +#endif +} + +void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {IGI(hex)} {start_point} {stop_point}\n"); + goto out; + } + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 0) { + for (i = 1; i < 10; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n", + var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], + (u8)var1[7], (u8)var1[8]); + phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2], + (u8)var1[3], (u16)var1[4], (u8)var1[5], + (u8)var1[6], (u8)var1[7], (u8)var1[8]); + + } else if (var1[0] == 1) { + PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n", + var1[1], var1[2], var1[3]); + dm->debug_components |= ODM_COMP_API; + phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]); + dm->debug_components &= (~ODM_COMP_API); + } + +out: + *_used = used; + *_out_len = out_len; +} + +u8 phydm_get_psd_result_table(void *dm_void, int index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u8 result = 0; + + if (index < 128) + result = dm_psd_table->psd_result[index]; + + return result; +} + +#endif diff --git a/hal/phydm/phydm_psd.h b/hal/phydm/phydm_psd.h index f305cd2..e4ee7f7 100644 --- a/hal/phydm/phydm_psd.h +++ b/hal/phydm/phydm_psd.h @@ -1,101 +1,68 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __PHYDMPSD_H__ -#define __PHYDMPSD_H__ - -/*#define PSD_VERSION "1.0"*/ /*2016.09.22 Dino*/ -#define PSD_VERSION "1.1" /*2016.10.07 Dino, Add Option for PSD Tone index Selection */ - -#if (CONFIG_PSD_TOOL == 1) - - -#define STOP_TRX_SUCCESS 1 -#define STOP_TRX_FAIL 0 - - -struct _PHYDM_PSD_ { - - u8 psd_in_progress; - u32 psd_reg; - u32 psd_report_reg; - u8 psd_pwr_common_offset; - u16 sw_avg_time; - u16 fft_smp_point; - u32 initial_gain_backup; - u32 rf_0x18_bkp; - u16 psd_fc_channel; - u32 psd_bw_rf_reg; - u8 psd_result[128]; - u8 noise_k_en; -}; - -u32 -phydm_get_psd_data( - void *p_dm_void, - u32 psd_tone_idx, - u32 igi -); - -void -phydm_psd_debug( - void *p_dm_void, - char input[][16], - u32 *_used, - char *output, - u32 *_out_len, - u32 input_num -); - -void -phydm_psd( - void *p_dm_void, - u32 igi, - u16 start_point, - u16 stop_point -); - -void -phydm_psd_para_setting( - void *p_dm_void, - u8 sw_avg_time, - u8 hw_avg_time, - u8 i_q_setting, - u16 fft_smp_point, - u8 ant_sel, - u8 psd_input, - u8 channel, - u8 noise_k_en -); - -void -phydm_psd_init( - void *p_dm_void -); - -u8 -phydm_get_psd_result_table( - void *p_dm_void, - int index -); - -#endif -#endif - +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMPSD_H__ +#define __PHYDMPSD_H__ + +/*@#define PSD_VERSION "1.0"*/ /*@2016.09.22 Dino*/ +#define PSD_VERSION "1.1" /*@2016.10.07 Dino, Add Option for PSD Tone index Selection */ + +#ifdef CONFIG_PSD_TOOL + + +struct psd_info { + u8 psd_in_progress; + u32 psd_reg; + u32 psd_report_reg; + u8 psd_pwr_common_offset; + u16 sw_avg_time; + u16 fft_smp_point; + u32 initial_gain_backup; + u32 rf_0x18_bkp; + u32 rf_0x18_bkp_b; + u16 psd_fc_channel; + u32 psd_bw_rf_reg; + u8 psd_result[128]; + u8 noise_k_en; +}; + +u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi); + +void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point); + +void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, + u8 hw_avg_time, u8 i_q_setting, + u16 fft_smp_point, u8 ant_sel, + u8 psd_input, u8 channel, u8 noise_k_en); + +void phydm_psd_init(void *dm_void); + +u8 phydm_get_psd_result_table(void *dm_void, int index); + +#endif +#endif diff --git a/hal/phydm/phydm_rainfo.c b/hal/phydm/phydm_rainfo.c index 409616d..c8da020 100644 --- a/hal/phydm/phydm_rainfo.c +++ b/hal/phydm/phydm_rainfo.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,2634 +8,1780 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -/* ************************************************************ +/*@************************************************************ * include files - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "phydm_precomp.h" -void -phydm_h2C_debug( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) +boolean phydm_is_vht_rate(void *dm_void, u8 rate) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 h2c_parameter[H2C_MAX_LENGTH] = {0}; - u8 phydm_h2c_id = (u8)dm_value[0]; - u8 i; - u32 used = *_used; - u32 out_len = *_out_len; - - PHYDM_SNPRINTF((output + used, out_len - used, "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id)); - for (i = 0; i < H2C_MAX_LENGTH; i++) { - - h2c_parameter[i] = (u8)dm_value[i + 1]; - PHYDM_SNPRINTF((output + used, out_len - used, "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i])); - } - - odm_fill_h2c_cmd(p_dm_odm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter); - + return ((rate & 0x7f) >= ODM_RATEVHTSS1MCS0) ? true : false; } -#if (defined(CONFIG_RA_DBG_CMD)) -void -odm_ra_para_adjust_send_h2c( - void *p_dm_void -) +boolean phydm_is_ht_rate(void *dm_void, u8 rate) { - - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 h2c_parameter[6] = {0}; - - h2c_parameter[0] = RA_FIRST_MACID; - - if (p_ra_table->ra_para_feedback_req) { /*h2c_parameter[5]=1 ; ask FW for all RA parameters*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Ask FW for RA parameter\n")); - h2c_parameter[5] |= BIT(1); /*ask FW to report RA parameters*/ - h2c_parameter[1] = p_ra_table->para_idx; /*p_ra_table->para_idx;*/ - p_ra_table->ra_para_feedback_req = 0; - } else { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Send H2C to FW for modifying RA parameter\n")); - - h2c_parameter[1] = p_ra_table->para_idx; - h2c_parameter[2] = p_ra_table->rate_idx; - /* [8 bit]*/ - if (p_ra_table->para_idx == RADBG_RTY_PENALTY || p_ra_table->para_idx == RADBG_RATE_UP_RTY_RATIO || p_ra_table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - h2c_parameter[3] = p_ra_table->value; - h2c_parameter[4] = 0; - } - /* [16 bit]*/ - else { - h2c_parameter[3] = (u8)(((p_ra_table->value_16) & 0xf0) >> 4); /*byte1*/ - h2c_parameter[4] = (u8)((p_ra_table->value_16) & 0x0f); /*byte0*/ - } - } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[1] = 0x%x\n", h2c_parameter[1])); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[2] = 0x%x\n", h2c_parameter[2])); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[3] = 0x%x\n", h2c_parameter[3])); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[4] = 0x%x\n", h2c_parameter[4])); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" h2c_parameter[5] = 0x%x\n", h2c_parameter[5])); - - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RA_PARA_ADJUST, 6, h2c_parameter); - + return (((rate & 0x7f) >= ODM_RATEMCS0) && + ((rate & 0x7f) <= ODM_RATEMCS31)) ? true : false; } - -void -odm_ra_para_adjust( - void *p_dm_void -) +boolean phydm_is_ofdm_rate(void *dm_void, u8 rate) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 rate_idx = p_ra_table->rate_idx; - u8 value = p_ra_table->value; - u8 pre_value = 0xff; - - if (p_ra_table->para_idx == RADBG_RTY_PENALTY) { - pre_value = p_ra_table->RTY_P[rate_idx]; - p_ra_table->RTY_P[rate_idx] = value; - p_ra_table->RTY_P_modify_note[rate_idx] = 1; - } else if (p_ra_table->para_idx == RADBG_N_HIGH) { - - } else if (p_ra_table->para_idx == RADBG_N_LOW) { - - } else if (p_ra_table->para_idx == RADBG_RATE_UP_RTY_RATIO) { - pre_value = p_ra_table->RATE_UP_RTY_RATIO[rate_idx]; - p_ra_table->RATE_UP_RTY_RATIO[rate_idx] = value; - p_ra_table->RATE_UP_RTY_RATIO_modify_note[rate_idx] = 1; - } else if (p_ra_table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - pre_value = p_ra_table->RATE_DOWN_RTY_RATIO[rate_idx]; - p_ra_table->RATE_DOWN_RTY_RATIO[rate_idx] = value; - p_ra_table->RATE_DOWN_RTY_RATIO_modify_note[rate_idx] = 1; - } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("Change RA Papa[%d], rate[ %d ], ((%d)) -> ((%d))\n", p_ra_table->para_idx, rate_idx, pre_value, value)); - odm_ra_para_adjust_send_h2c(p_dm_odm); + return (((rate & 0x7f) >= ODM_RATE6M) && + ((rate & 0x7f) <= ODM_RATE54M)) ? true : false; } -void -phydm_ra_print_msg( - void *p_dm_void, - u8 *value, - u8 *value_default, - u8 *modify_note -) +boolean phydm_is_cck_rate(void *dm_void, u8 rate) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u32 i; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |Current-value| |Default-value| |Modify?|\n")); - for (i = 0 ; i <= (p_ra_table->rate_length); i++) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %20d %25d %20s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); -#else - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %10d %14d %14s\n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); -#endif - } - + return ((rate & 0x7f) <= ODM_RATE11M) ? true : false; } -void -odm_RA_debug( - void *p_dm_void, - u32 *const dm_value -) +u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - - p_ra_table->is_ra_dbg_init = false; - - if (dm_value[0] == 100) { /*1 Print RA Parameters*/ - u8 default_pointer_value; - u8 *pvalue; - u8 *pvalue_default; - u8 *pmodify_note; - - pvalue = pvalue_default = pmodify_note = &default_pointer_value; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n")); - - if (dm_value[1] == RADBG_RTY_PENALTY) { /* [1]*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [1] RTY_PENALTY\n")); - pvalue = &(p_ra_table->RTY_P[0]); - pvalue_default = &(p_ra_table->RTY_P_default[0]); - pmodify_note = (u8 *)&(p_ra_table->RTY_P_modify_note[0]); - } else if (dm_value[1] == RADBG_N_HIGH) /* [2]*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [2] N_HIGH\n")); - - else if (dm_value[1] == RADBG_N_LOW) /*[3]*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [3] N_LOW\n")); - - else if (dm_value[1] == RADBG_RATE_UP_RTY_RATIO) { /* [8]*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [8] RATE_UP_RTY_RATIO\n")); - pvalue = &(p_ra_table->RATE_UP_RTY_RATIO[0]); - pvalue_default = &(p_ra_table->RATE_UP_RTY_RATIO_default[0]); - pmodify_note = (u8 *)&(p_ra_table->RATE_UP_RTY_RATIO_modify_note[0]); - } else if (dm_value[1] == RADBG_RATE_DOWN_RTY_RATIO) { /* [9]*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [9] RATE_DOWN_RTY_RATIO\n")); - pvalue = &(p_ra_table->RATE_DOWN_RTY_RATIO[0]); - pvalue_default = &(p_ra_table->RATE_DOWN_RTY_RATIO_default[0]); - pmodify_note = (u8 *)&(p_ra_table->RATE_DOWN_RTY_RATIO_modify_note[0]); - } - - phydm_ra_print_msg(p_dm_odm, pvalue, pvalue_default, pmodify_note); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n\n")); - - } else if (dm_value[0] == 101) { - p_ra_table->para_idx = (u8)dm_value[1]; - - p_ra_table->ra_para_feedback_req = 1; - odm_ra_para_adjust_send_h2c(p_dm_odm); - } else { - p_ra_table->para_idx = (u8)dm_value[0]; - p_ra_table->rate_idx = (u8)dm_value[1]; - p_ra_table->value = (u8)dm_value[2]; - - odm_ra_para_adjust(p_dm_odm); - } + u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 rate_digit = 0; + + if (rate_idx >= ODM_RATEVHTSS1MCS0) + rate_digit = (rate_idx - ODM_RATEVHTSS1MCS0) % 10; + else if (rate_idx >= ODM_RATEMCS0) + rate_digit = (rate_idx - ODM_RATEMCS0); + else if (rate_idx <= ODM_RATE54M) + rate_digit = legacy_table[rate_idx]; + + return rate_digit; } -void -odm_ra_para_adjust_init( - void *p_dm_void -) +u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 i; - u8 ra_para_pool_u8[3] = { RADBG_RTY_PENALTY, RADBG_RATE_UP_RTY_RATIO, RADBG_RATE_DOWN_RTY_RATIO}; - u8 rate_size_ht_1ss = 20, rate_size_ht_2ss = 28, rate_size_ht_3ss = 36; /*4+8+8+8+8 =36*/ - u8 rate_size_vht_1ss = 10, rate_size_vht_2ss = 20, rate_size_vht_3ss = 30; /*10 + 10 +10 =30*/ -#if 0 - /* RTY_PENALTY = 1, u8 */ - /* N_HIGH = 2, */ - /* N_LOW = 3, */ - /* RATE_UP_TABLE = 4, */ - /* RATE_DOWN_TABLE = 5, */ - /* TRYING_NECESSARY = 6, */ - /* DROPING_NECESSARY = 7, */ - /* RATE_UP_RTY_RATIO = 8, u8 */ - /* RATE_DOWN_RTY_RATIO= 9, u8 */ - /* ALL_PARA = 0xff */ - -#endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("odm_ra_para_adjust_init\n")); - -/* JJ ADD 20161014 */ - if (p_dm_odm->support_ic_type & (ODM_RTL8188F | ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8723D | ODM_RTL8710B)) - p_ra_table->rate_length = rate_size_ht_1ss; - else if (p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) - p_ra_table->rate_length = rate_size_ht_2ss; - else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8821C)) - p_ra_table->rate_length = rate_size_ht_1ss + rate_size_vht_1ss; - else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) - p_ra_table->rate_length = rate_size_ht_2ss + rate_size_vht_2ss; - else if (p_dm_odm->support_ic_type == ODM_RTL8814A) - p_ra_table->rate_length = rate_size_ht_3ss + rate_size_vht_3ss; - else - p_ra_table->rate_length = rate_size_ht_1ss; + u8 num_ss = 1; - p_ra_table->is_ra_dbg_init = true; - for (i = 0; i < 3; i++) { - p_ra_table->ra_para_feedback_req = 1; - p_ra_table->para_idx = ra_para_pool_u8[i]; - odm_ra_para_adjust_send_h2c(p_dm_odm); + switch (type) { + case PDM_CCK: + case PDM_OFDM: + case PDM_1SS: + num_ss = 1; + break; + case PDM_2SS: + num_ss = 2; + break; + case PDM_3SS: + num_ss = 3; + break; + case PDM_4SS: + num_ss = 4; + break; + default: + break; } + + return num_ss; } -#else +u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate) +{ + u8 num_ss = 1; + + if (data_rate <= ODM_RATE54M) + num_ss = 1; + else if (data_rate <= ODM_RATEMCS31) + num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1; + else if (data_rate <= ODM_RATEVHTSS1MCS9) + num_ss = 1; + else if (data_rate <= ODM_RATEVHTSS2MCS9) + num_ss = 2; + else if (data_rate <= ODM_RATEVHTSS3MCS9) + num_ss = 3; + else if (data_rate <= ODM_RATEVHTSS4MCS9) + num_ss = 4; + + return num_ss; +} -void -phydm_RA_debug_PCR( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -) +void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; u32 used = *_used; u32 out_len = *_out_len; - - if (dm_value[0] == 100) { - PHYDM_SNPRINTF((output + used, out_len - used, "[Get] PCR RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - /**/ - } else if (dm_value[0] == 0) { - p_ra_table->RA_offset_direction = 0; - p_ra_table->RA_threshold_offset = (u8)dm_value[1]; - PHYDM_SNPRINTF((output + used, out_len - used, "[Set] PCR RA_threshold_offset = (( -%d ))\n", p_ra_table->RA_threshold_offset)); - } else if (dm_value[0] == 1) { - p_ra_table->RA_offset_direction = 1; - p_ra_table->RA_threshold_offset = (u8)dm_value[1]; - PHYDM_SNPRINTF((output + used, out_len - used, "[Set] PCR RA_threshold_offset = (( +%d ))\n", p_ra_table->RA_threshold_offset)); - } else { - PHYDM_SNPRINTF((output + used, out_len - used, "[Set] Error\n")); - /**/ + u32 dm_value[10] = {0}; + u8 i = 0, input_idx = 0; + u8 h2c_parameter[H2C_MAX_LENGTH] = {0}; + u8 phydm_h2c_id = 0; + + for (i = 0; i < 8; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + input_idx++; + } } -} + if (input_idx == 0) + return; -#endif /*#if (defined(CONFIG_RA_DBG_CMD))*/ + phydm_h2c_id = (u8)dm_value[0]; -void -odm_c2h_ra_para_report_handler( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id); - u8 para_idx = cmd_buf[0]; /*Retry Penalty, NH, NL*/ - u8 rate_type_start = cmd_buf[1]; - u8 rate_type_length = cmd_len - 2; - u8 i; + for (i = 0; i < H2C_MAX_LENGTH; i++) { + h2c_parameter[i] = (u8)dm_value[i + 1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i]); + } + odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[ From FW C2H RA Para ] cmd_buf[0]= (( %d ))\n", cmd_buf[0])); + *_used = used; + *_out_len = out_len; +} -#if (defined(CONFIG_RA_DBG_CMD)) - if (para_idx == RADBG_RTY_PENALTY) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |RTY Penality index|\n")); +void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_u32_tmp; - for (i = 0 ; i < (rate_type_length) ; i++) { - if (p_ra_table->is_ra_dbg_init) - p_ra_table->RTY_P_default[rate_type_start + i] = cmd_buf[2 + i]; + if (dm->support_ic_type & PHYDM_IC_8051_SERIES) { + reg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en; + odm_set_bb_reg(dm, R_0x4a0, MASKDWORD, reg_u32_tmp); - p_ra_table->RTY_P[rate_type_start + i] = cmd_buf[2 + i]; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RTY_P[rate_type_start + i])); - } + } else { + if (en == 1) + reg_u32_tmp = BYTE_2_DWORD(0x60, macid, bw, rate); + else + reg_u32_tmp = 0x40000000; - } else if (para_idx == RADBG_N_HIGH) { - /**/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |N-High|\n")); + odm_set_bb_reg(dm, R_0x450, MASKDWORD, reg_u32_tmp); + } + if (en == 1) { + PHYDM_DBG(dm, ODM_COMP_API, + "FW fix TX rate[id =%d], %dM, Rate(%d)=", macid, + (20 << bw), rate); + phydm_print_rate(dm, rate, ODM_COMP_API); + } else { + PHYDM_DBG(dm, ODM_COMP_API, "Auto Rate\n"); + } +} +void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u32 used = *_used; + u32 out_len = *_out_len; + char help[] = "-h"; + u32 var[5] = {0}; + u8 macid = 0, bw = 0, rate = 0; + u8 i = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]); + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {0:-,1:+} {ofst}: set offset\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {100}: show offset\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} {en} {macid} {bw} {rate}: fw fix rate\n"); + + } else if (var[0] == 1) { /*@Adjust PCR offset*/ + + if (var[1] == 100) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Get] RA_ofst=((%s%d))\n", + ((ra_tab->ra_ofst_direc) ? "+" : "-"), + ra_tab->ra_th_ofst); + + } else if (var[1] == 0) { + ra_tab->ra_ofst_direc = 0; + ra_tab->ra_th_ofst = (u8)var[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Set] RA_ofst=((-%d))\n", ra_tab->ra_th_ofst); + } else if (var[1] == 1) { + ra_tab->ra_ofst_direc = 1; + ra_tab->ra_th_ofst = (u8)var[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Set] RA_ofst=((+%d))\n", ra_tab->ra_th_ofst); + } - } else if (para_idx == RADBG_N_LOW) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |N-Low|\n")); - /**/ - } else if (para_idx == RADBG_RATE_UP_RTY_RATIO) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |rate Up RTY Ratio|\n")); + } else if (var[0] == 2) { /*@FW fix rate*/ + macid = (u8)var[2]; + bw = (u8)var[3]; + rate = (u8)var[4]; - for (i = 0; i < (rate_type_length); i++) { - if (p_ra_table->is_ra_dbg_init) - p_ra_table->RATE_UP_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[FW fix TX Rate] {en, macid,bw,rate}={%d, %d, %d, 0x%x}", + var[1], macid, bw, rate); - p_ra_table->RATE_UP_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i]; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RATE_UP_RTY_RATIO[rate_type_start + i])); - } - } else if (para_idx == RADBG_RATE_DOWN_RTY_RATIO) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |rate index| |rate Down RTY Ratio|\n")); + phydm_fw_fix_rate(dm, (u8)var[1], macid, bw, rate); - for (i = 0; i < (rate_type_length); i++) { - if (p_ra_table->is_ra_dbg_init) - p_ra_table->RATE_DOWN_RTY_RATIO_default[rate_type_start + i] = cmd_buf[2 + i]; + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Set] Error\n"); + } + *_used = used; + *_out_len = out_len; +} - p_ra_table->RATE_DOWN_RTY_RATIO[rate_type_start + i] = cmd_buf[2 + i]; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d\n", (rate_type_start + i), p_ra_table->RATE_DOWN_RTY_RATIO[rate_type_start + i])); +void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 mode = cmd_buf[0]; /*Retry Penalty, NH, NL*/ + u8 i; + + PHYDM_DBG(dm, DBG_FW_TRACE, "[%s] [mode: %d]----------------------->\n", + __func__, mode); + + if (mode == RADBG_DEBUG_MONITOR1) { + if (dm->support_ic_type & PHYDM_IC_3081_SERIES) { + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =", + cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "rate =", + cmd_buf[2] & 0x7f); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "SGI =", + (cmd_buf[2] & 0x80) >> 7); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW =", + cmd_buf[3]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW_max =", + cmd_buf[4]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "multi_rate0 =", cmd_buf[5]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "multi_rate1 =", cmd_buf[6]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =", + cmd_buf[7]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =", + cmd_buf[8]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", + "SGI_support =", cmd_buf[9]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "try_ness =", + cmd_buf[10]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "pre_rate =", + cmd_buf[11]); + } else { + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =", + cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %x\n", "BW =", + cmd_buf[2]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =", + cmd_buf[3]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =", + cmd_buf[4]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", + "Hightest rate =", cmd_buf[5]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "Lowest rate =", cmd_buf[6]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "SGI_support =", cmd_buf[7]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Rate_ID =", + cmd_buf[8]); } - } else -#endif - if (para_idx == RADBG_DEBUG_MONITOR1) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { - - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", cmd_buf[1])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "rate =", cmd_buf[2] & 0x7f)); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI =", (cmd_buf[2] & 0x80) >> 7)); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW =", cmd_buf[3])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW_max =", cmd_buf[4])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate0 =", cmd_buf[5])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate1 =", cmd_buf[6])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", cmd_buf[7])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", cmd_buf[8])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI_support =", cmd_buf[9])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "try_ness =", cmd_buf[10])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "pre_rate =", cmd_buf[11])); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", cmd_buf[1])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x\n", "BW =", cmd_buf[2])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", cmd_buf[3])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", cmd_buf[4])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Hightest rate =", cmd_buf[5])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Lowest rate =", cmd_buf[6])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "SGI_support =", cmd_buf[7])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Rate_ID =", cmd_buf[8]));; - } - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - } else if (para_idx == RADBG_DEBUG_MONITOR2) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "rate_id =", cmd_buf[1])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest_rate =", cmd_buf[2])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "lowest_rate =", cmd_buf[3])); - - for (i = 4; i <= 11; i++) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("RAMASK = 0x%x\n", cmd_buf[i])); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x%x %x%x %x%x %x%x\n", "RA Mask:", - cmd_buf[8], cmd_buf[7], cmd_buf[6], cmd_buf[5], cmd_buf[4], cmd_buf[3], cmd_buf[2], cmd_buf[1])); - } - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); - } else if (para_idx == RADBG_DEBUG_MONITOR3) { - - for (i = 0; i < (cmd_len - 1); i++) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("content[%d] = %d\n", i, cmd_buf[1 + i])); - } else if (para_idx == RADBG_DEBUG_MONITOR4) - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {%d.%d}\n", "RA version =", cmd_buf[1], cmd_buf[2])); - else if (para_idx == RADBG_DEBUG_MONITOR5) { - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Current rate =", cmd_buf[1])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Retry ratio =", cmd_buf[2])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "rate down ratio =", cmd_buf[3])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest rate =", cmd_buf[4])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {0x%x 0x%x}\n", "Muti-try =", cmd_buf[5], cmd_buf[6])); - ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x%x%x%x%x\n", "RA mask =", cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8], cmd_buf[7])); + } else if (mode == RADBG_DEBUG_MONITOR2) { + if (dm->support_ic_type & PHYDM_IC_3081_SERIES) { + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate_id =", + cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "highest_rate =", cmd_buf[2]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "lowest_rate =", cmd_buf[3]); + + for (i = 4; i <= 11; i++) + PHYDM_DBG(dm, DBG_FW_TRACE, "RAMASK = 0x%x\n", + cmd_buf[i]); + } else { + PHYDM_DBG(dm, DBG_FW_TRACE, + "%5s %x%x %x%x %x%x %x%x\n", "RA Mask:", + cmd_buf[8], cmd_buf[7], cmd_buf[6], + cmd_buf[5], cmd_buf[4], cmd_buf[3], + cmd_buf[2], cmd_buf[1]); } + } else if (mode == RADBG_DEBUG_MONITOR3) { + for (i = 0; i < (cmd_len - 1); i++) + PHYDM_DBG(dm, DBG_FW_TRACE, "content[%d] = %d\n", i, + cmd_buf[1 + i]); + } else if (mode == RADBG_DEBUG_MONITOR4) + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {%d.%d}\n", "RA version =", + cmd_buf[1], cmd_buf[2]); + else if (mode == RADBG_DEBUG_MONITOR5) { + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "Current rate =", + cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Retry ratio =", + cmd_buf[2]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate down ratio =", + cmd_buf[3]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "highest rate =", + cmd_buf[4]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {0x%x 0x%x}\n", "Muti-try =", + cmd_buf[5], cmd_buf[6]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x%x%x%x%x\n", "RA mask =", + cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8], + cmd_buf[7]); + } + PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n"); } -void -phydm_ra_dynamic_retry_count( - void *p_dm_void -) +void phydm_ra_dynamic_retry_count(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - struct sta_info *p_entry; - u8 i, retry_offset; - u32 ma_rx_tp; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_ARFR)) + if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR)) return; - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("p_dm_odm->pre_b_noisy = %d\n", p_dm_odm->pre_b_noisy ));*/ - if (p_dm_odm->pre_b_noisy != p_dm_odm->noisy_decision) { - - if (p_dm_odm->noisy_decision) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Noisy Env. RA fallback value\n")); - odm_set_mac_reg(p_dm_odm, 0x430, MASKDWORD, 0x0); - odm_set_mac_reg(p_dm_odm, 0x434, MASKDWORD, 0x04030201); +#if 0 + /*PHYDM_DBG(dm, DBG_RA, "dm->pre_b_noisy = %d\n", dm->pre_b_noisy );*/ +#endif + if (dm->pre_b_noisy != dm->noisy_decision) { + if (dm->noisy_decision) { + PHYDM_DBG(dm, DBG_DYN_ARFR, "Noisy Env. RA fallback\n"); + odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x0); + odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x04030201); } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Clean Env. RA fallback value\n")); - odm_set_mac_reg(p_dm_odm, 0x430, MASKDWORD, 0x01000000); - odm_set_mac_reg(p_dm_odm, 0x434, MASKDWORD, 0x06050402); + PHYDM_DBG(dm, DBG_DYN_ARFR, "Clean Env. RA fallback\n"); + odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x01000000); + odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x06050402); } - p_dm_odm->pre_b_noisy = p_dm_odm->noisy_decision; + dm->pre_b_noisy = dm->noisy_decision; } } -#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - -void -phydm_retry_limit_table_bound( - void *p_dm_void, - u8 *retry_limit, - u8 offset -) +void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - - if (*retry_limit > offset) { - - *retry_limit -= offset; - - if (*retry_limit < p_ra_table->retrylimit_low) - *retry_limit = p_ra_table->retrylimit_low; - else if (*retry_limit > p_ra_table->retrylimit_high) - *retry_limit = p_ra_table->retrylimit_high; - } else - *retry_limit = p_ra_table->retrylimit_low; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + boolean vht_en = phydm_is_vht_rate(dm, rate_idx); + u8 b_sgi = (rate & 0x80) >> 7; + u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx); + u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx); + + PHYDM_DBG_F(dm, dbg_component, "( %s%s%s%s%d%s%s)\n", + (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "", + (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "", + (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "", + (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", + rate_digit, + (b_sgi) ? "-S" : " ", + (rate_idx >= ODM_RATEMCS0) ? "" : "M"); } -void -phydm_reset_retry_limit_table( - void *p_dm_void -) +void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 i; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + boolean vht_en = phydm_is_vht_rate(dm, rate_idx); + u8 b_sgi = (rate & 0x80) >> 7; + u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx); + u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx); + + PHYDM_SNPRINTF(buf, buf_size, "( %s%s%s%s%d%s%s)", + (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "", + (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "", + (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "", + (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", + rate_digit, + (b_sgi) ? "-S" : " ", + (rate_idx >= ODM_RATEMCS0) ? "" : "M"); +} -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*support all IC platform*/ +void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; + u8 macid = cmd_buf[1]; + u8 rate = cmd_buf[0]; + u8 curr_ra_ratio = 0xff; + u8 curr_bw = 0xff; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 rate_order; -#else -#if ((RTL8192E_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1)) - u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = { - 1, 1, 2, 4, /*CCK*/ - 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ - 2, 4, 6, 8, 12, 18, 20, 22, /*20M HT-1SS*/ - 2, 4, 6, 8, 12, 18, 20, 22 /*20M HT-2SS*/ - }; - u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = { - 1, 1, 2, 4, /*CCK*/ - 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ - 4, 8, 12, 16, 24, 32, 32, 32, /*40M HT-1SS*/ - 4, 8, 12, 16, 24, 32, 32, 32 /*40M HT-2SS*/ - }; + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + sta = dm->phydm_sta_info[dm->phydm_macid_table[macid]]; + #else + sta = dm->phydm_sta_info[macid]; + #endif -#elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) + if (cmd_len >= 7) { + curr_ra_ratio = cmd_buf[5]; + curr_bw = cmd_buf[6]; + PHYDM_DBG(dm, DBG_RA, "RA retry ratio: [%d]:", curr_ra_ratio); + } -#elif (RTL8812A_SUPPORT == 1) + if (cmd_buf[3] != 0) { + if (cmd_buf[3] == 0xff) + PHYDM_DBG(dm, DBG_RA, "FW Level: Fix rate[%d]:", macid); + else if (cmd_buf[3] == 1) + PHYDM_DBG(dm, DBG_RA, "Try Success[%d]:", macid); + else if (cmd_buf[3] == 2) + PHYDM_DBG(dm, DBG_RA, "Try Fail & Again[%d]:", macid); + else if (cmd_buf[3] == 3) + PHYDM_DBG(dm, DBG_RA, "rate Back[%d]:", macid); + else if (cmd_buf[3] == 4) + PHYDM_DBG(dm, DBG_RA, "start rate by RSSI[%d]:", macid); + else if (cmd_buf[3] == 5) + PHYDM_DBG(dm, DBG_RA, "Try rate[%d]:", macid); + } -#elif (RTL8814A_SUPPORT == 1) + PHYDM_DBG(dm, DBG_RA, "Tx rate Update[%d]:", macid); + phydm_print_rate(dm, rate, DBG_RA); -#else + if (macid >= 128) { + u8 gid_index = macid - 128; -#endif -#endif + ra_tab->mu1_rate[gid_index] = rate; + } - memcpy(&(p_ra_table->per_rate_retrylimit_20M[0]), &(per_rate_retrylimit_table_20M[0]), ODM_NUM_RATE_IDX); - memcpy(&(p_ra_table->per_rate_retrylimit_40M[0]), &(per_rate_retrylimit_table_40M[0]), ODM_NUM_RATE_IDX); + /*@ra_tab->link_tx_rate[macid] = rate;*/ - for (i = 0; i < ODM_NUM_RATE_IDX; i++) { - phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_20M[i]), 0); - phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_40M[i]), 0); + if (is_sta_active(sta)) { + sta->ra_info.curr_tx_rate = rate; + sta->ra_info.curr_tx_bw = (enum channel_width)curr_bw; + sta->ra_info.curr_retry_ratio = curr_ra_ratio; } -} - -void -phydm_ra_dynamic_retry_limit_init( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - p_ra_table->retry_descend_num = RA_RETRY_DESCEND_NUM; - p_ra_table->retrylimit_low = RA_RETRY_LIMIT_LOW; - p_ra_table->retrylimit_high = RA_RETRY_LIMIT_HIGH; + /*trigger power training*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - phydm_reset_retry_limit_table(p_dm_odm); + rate_order = phydm_rate_order_compute(dm, rate_idx); -} + if (dm->is_one_entry_only || + (rate_order > ra_tab->highest_client_tx_order && + ra_tab->power_tracking_flag == 1)) { + halrf_update_pwr_track(dm, rate_idx); + ra_tab->power_tracking_flag = 0; + } #endif -void -phydm_ra_dynamic_retry_limit( - void *p_dm_void -) -{ -#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - struct sta_info *p_entry; - u8 i, retry_offset; - u32 ma_rx_tp; - - - if (p_dm_odm->pre_number_active_client == p_dm_odm->number_active_client) { - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" pre_number_active_client == number_active_client\n")); - return; - - } else { - if (p_dm_odm->number_active_client == 1) { - phydm_reset_retry_limit_table(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("one client only->reset to default value\n")); - } else { - - retry_offset = p_dm_odm->number_active_client * p_ra_table->retry_descend_num; - - for (i = 0; i < ODM_NUM_RATE_IDX; i++) { - - phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_20M[i]), retry_offset); - phydm_retry_limit_table_bound(p_dm_odm, &(p_ra_table->per_rate_retrylimit_40M[i]), retry_offset); - } - } - } +#if 0 + /*trigger dynamic rate ID*/ + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) + phydm_update_rate_id(dm, rate, macid); #endif } -#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) -void -phydm_ra_dynamic_rate_id_on_assoc( - void *p_dm_void, - u8 wireless_mode, - u8 init_rate_id -) +void odm_ra_post_action_on_assoc(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", p_dm_odm->rf_type, wireless_mode, init_rate_id)); - - if ((p_dm_odm->rf_type == ODM_2T2R) | (p_dm_odm->rf_type == ODM_2T2R_GREEN) | (p_dm_odm->rf_type == ODM_2T3R) | (p_dm_odm->rf_type == ODM_2T4R)) { - - if ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) && - (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) - ) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set N-2SS ARFR5 table\n")); - odm_set_mac_reg(p_dm_odm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ - odm_set_mac_reg(p_dm_odm, 0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ - } else if ((p_dm_odm->support_ic_type & (ODM_RTL8812)) && - (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) - ) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set AC-2SS ARFR0 table\n")); - odm_set_mac_reg(p_dm_odm, 0x444, MASKDWORD, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ - odm_set_mac_reg(p_dm_odm, 0x448, MASKDWORD, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ - } - } +#if 0 + struct dm_struct *dm = (struct dm_struct *)dm_void; + dm->h2c_rarpt_connect = 1; + phydm_rssi_monitor_check(dm); + dm->h2c_rarpt_connect = 0; +#endif } -void -phydm_ra_dynamic_rate_id_init( - void *p_dm_void -) +void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc, + u8 ra_th_ofst) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) { + ra_tab->ra_ofst_direc = ra_ofst_direc; + ra_tab->ra_th_ofst = ra_th_ofst; + PHYDM_DBG(dm, DBG_RA_MASK, "Set ra_th_offset=(( %s%d ))\n", + ((ra_ofst_direc) ? "+" : "-"), ra_th_ofst); +} - odm_set_mac_reg(p_dm_odm, 0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ - odm_set_mac_reg(p_dm_odm, 0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - odm_set_mac_reg(p_dm_odm, 0x444, MASKDWORD, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ - odm_set_mac_reg(p_dm_odm, 0x448, MASKDWORD, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ +void phydm_gen_ramask_h2c_AP( + void *dm_void, + struct rtl8192cd_priv *priv, + struct sta_info *entry, + u8 rssi_level) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type == ODM_RTL8812) { + #if (RTL8812A_SUPPORT == 1) + UpdateHalRAMask8812(priv, entry, rssi_level); + #endif + } else if (dm->support_ic_type == ODM_RTL8188E) { + #if (RTL8188E_SUPPORT == 1) + #ifdef TXREPORT + add_RATid(priv, entry); + #endif + #endif + } else { + #ifdef CONFIG_WLAN_HAL + GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, entry, rssi_level); + #endif } } -void -phydm_update_rate_id( - void *p_dm_void, - u8 rate, - u8 platform_macid -) +void phydm_update_hal_ra_mask( + void *dm_void, + u32 wireless_mode, + u8 rf_type, + u8 bw, + u8 mimo_ps_enable, + u8 disable_cck_rate, + u32 *ratr_bitmap_msb_in, + u32 *ratr_bitmap_lsb_in, + u8 tx_rate_level) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 current_tx_ss; - u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u8 wireless_mode; - u8 phydm_macid; - struct sta_info *p_entry; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 ratr_bitmap = *ratr_bitmap_lsb_in; + u32 ratr_bitmap_msb = *ratr_bitmap_msb_in; - -#if 0 - if (rate_idx >= ODM_RATEVHTSS2MCS0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( VHT2SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0))); - /*dummy for SD4 check patch*/ - } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( VHT1SS-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0))); - /*dummy for SD4 check patch*/ - } else if (rate_idx >= ODM_RATEMCS0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( HT-MCS%d ))\n", platform_macid, (rate_idx - ODM_RATEMCS0))); - /*dummy for SD4 check patch*/ - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate[%d]: (( HT-MCS%d ))\n", platform_macid, rate_idx)); - /*dummy for SD4 check patch*/ - } +#if 0 + /*PHYDM_DBG(dm, DBG_RA_MASK, "phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type);*/ #endif + PHYDM_DBG(dm, DBG_RA_MASK, + "Platfoem original RA Mask = (( 0x %x | %x ))\n", + ratr_bitmap_msb, ratr_bitmap); - phydm_macid = p_dm_odm->platform2phydm_macid_table[platform_macid]; - p_entry = p_dm_odm->p_odm_sta_info[phydm_macid]; + switch (wireless_mode) { + case PHYDM_WIRELESS_MODE_B: { + ratr_bitmap &= 0x0000000f; + } break; - if (IS_STA_VALID(p_entry)) { - wireless_mode = p_entry->wireless_mode; + case PHYDM_WIRELESS_MODE_G: { + ratr_bitmap &= 0x00000ff5; + } break; - if ((p_dm_odm->rf_type == ODM_2T2R) | (p_dm_odm->rf_type == ODM_2T2R_GREEN) | (p_dm_odm->rf_type == ODM_2T3R) | (p_dm_odm->rf_type == ODM_2T4R)) { + case PHYDM_WIRELESS_MODE_A: { + ratr_bitmap &= 0x00000ff0; + } break; - p_entry->ratr_idx = p_entry->ratr_idx_init; - if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/ - if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*2SS mode*/ + case PHYDM_WIRELESS_MODE_N_24G: + case PHYDM_WIRELESS_MODE_N_5G: { + if (mimo_ps_enable) + rf_type = RF_1T1R; - p_entry->ratr_idx = ARFR_5_RATE_ID; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_5\n")); - } - } else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*AC mode*/ - if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*2SS mode*/ + if (rf_type == RF_1T1R) { + if (bw == CHANNEL_WIDTH_40) + ratr_bitmap &= 0x000ff015; + else + ratr_bitmap &= 0x000ff005; + } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) { + if (bw == CHANNEL_WIDTH_40) + ratr_bitmap &= 0x0ffff015; + else + ratr_bitmap &= 0x0ffff005; + } else { /*@3T*/ - p_entry->ratr_idx = ARFR_0_RATE_ID; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_0\n")); - } - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("UPdate_RateID[%d]: (( 0x%x ))\n", platform_macid, p_entry->ratr_idx)); + ratr_bitmap &= 0xfffff015; + ratr_bitmap_msb &= 0xf; } - } + } break; -} -#endif - -void -phydm_print_rate( - void *p_dm_void, - u8 rate, - u32 dbg_component -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; - u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u8 vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0; - u8 b_sgi = (rate & 0x80) >> 7; - - ODM_RT_TRACE_F(p_dm_odm, dbg_component, ODM_DBG_LOUD, ("( %s%s%s%s%d%s%s)\n", - ((rate_idx >= ODM_RATEVHTSS1MCS0) && (rate_idx <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss " : "", - ((rate_idx >= ODM_RATEVHTSS2MCS0) && (rate_idx <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "", - ((rate_idx >= ODM_RATEVHTSS3MCS0) && (rate_idx <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "", - (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", - (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0) % 10) : ((rate_idx >= ODM_RATEMCS0) ? (rate_idx - ODM_RATEMCS0) : ((rate_idx <= ODM_RATE54M) ? legacy_table[rate_idx] : 0)), - (b_sgi) ? "-S" : " ", - (rate_idx >= ODM_RATEMCS0) ? "" : "M")); -} - -void -phydm_c2h_ra_report_handler( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; - u8 macid = cmd_buf[1]; - u8 rate = cmd_buf[0]; - u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ - u8 pre_rate = p_ra_table->link_tx_rate[macid]; - u8 rate_order; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - - GET_HAL_DATA(adapter)->CurrentRARate = HwRateToMRate(rate_idx); -#endif + case PHYDM_WIRELESS_MODE_AC_24G: { + if (rf_type == RF_1T1R) { + ratr_bitmap &= 0x003ff015; + } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) { + ratr_bitmap &= 0xfffff015; + } else { /*@3T*/ + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } - if (cmd_len >= 4) { - if (cmd_buf[3] == 0) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("TX Init-rate Update[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 0xff) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("FW Level: Fix rate[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 1) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Success[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 2) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Fail & Try Again[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 3) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate Back[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 4) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("start rate by RSSI[%d]:", macid)); - /**/ - } else if (cmd_buf[3] == 5) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try rate[%d]:", macid)); - /**/ + if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; } - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Tx rate Update[%d]:", macid)); - /**/ - } + } break; - /*phydm_print_rate(p_dm_odm, pre_rate_idx, ODM_COMP_RATE_ADAPTIVE);*/ - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (">\n",macid );*/ - phydm_print_rate(p_dm_odm, rate, ODM_COMP_RATE_ADAPTIVE); + case PHYDM_WIRELESS_MODE_AC_5G: { + if (rf_type == RF_1T1R) { + ratr_bitmap &= 0x003ff010; + } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) { + ratr_bitmap &= 0xfffff010; + } else { /*@3T*/ - p_ra_table->link_tx_rate[macid] = rate; + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } - /*trigger power training*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; + } + } break; - rate_order = phydm_rate_order_compute(p_dm_odm, rate_idx); + default: + break; + } - if ((p_dm_odm->is_one_entry_only) || - ((rate_order > p_ra_table->highest_client_tx_order) && (p_ra_table->power_tracking_flag == 1)) - ) { - phydm_update_pwr_track(p_dm_odm, rate_idx); - p_ra_table->power_tracking_flag = 0; + if (wireless_mode != PHYDM_WIRELESS_MODE_B) { + if (tx_rate_level == 0) + ratr_bitmap &= 0xffffffff; + else if (tx_rate_level == 1) + ratr_bitmap &= 0xfffffff0; + else if (tx_rate_level == 2) + ratr_bitmap &= 0xffffefe0; + else if (tx_rate_level == 3) + ratr_bitmap &= 0xffffcfc0; + else if (tx_rate_level == 4) + ratr_bitmap &= 0xffff8f80; + else if (tx_rate_level >= 5) + ratr_bitmap &= 0xffff0f00; } -#endif + if (disable_cck_rate) + ratr_bitmap &= 0xfffffff0; - /*trigger dynamic rate ID*/ -#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) - phydm_update_rate_id(p_dm_odm, rate, macid); + PHYDM_DBG(dm, DBG_RA_MASK, + "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n", + wireless_mode, rf_type, bw, mimo_ps_enable, tx_rate_level); + +#if 0 + /*PHYDM_DBG(dm, DBG_RA_MASK, "111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap);*/ #endif + *ratr_bitmap_lsb_in = ratr_bitmap; + *ratr_bitmap_msb_in = ratr_bitmap_msb; + PHYDM_DBG(dm, DBG_RA_MASK, + "Phydm modified RA Mask = (( 0x %x | %x ))\n", + *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in); } -void -odm_rssi_monitor_init( - void *p_dm_void -) +#if 0 +void odm_refresh_rate_adaptive_mask_ap( + void *dm_void) { -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + struct rtl8192cd_priv *priv = dm->priv; + struct aid_obj *aidarray; + u32 i; + struct sta_info *entry; + struct cmn_sta_info *sta; + u8 ratr_state_new; - p_ra_table->PT_collision_pre = true; /*used in odm_dynamic_arfb_select(WIN only)*/ + if (priv->up_time % 2) + return; - p_hal_data->UndecoratedSmoothedPWDB = -1; - p_hal_data->ra_rpt_linked = false; -#endif + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + entry = dm->odm_sta_info[i]; + sta = dm->phydm_sta_info[i]; - p_ra_table->firstconnect = false; + if (!is_sta_active(sta)) + continue; + #if defined(UNIVERSAL_REPEATER) || defined(MBSSID) + aidarray = container_of(entry, struct aid_obj, station); + priv = aidarray->priv; + #endif -#endif -} + if (!priv->pmib->dot11StationConfigEntry.autoRate) + continue; -void -odm_ra_post_action_on_assoc( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - /* - p_dm_odm->h2c_rarpt_connect = 1; - odm_rssi_monitor_check(p_dm_odm); - p_dm_odm->h2c_rarpt_connect = 0; - */ + ratr_state_new = phydm_rssi_lv_dec(dm, (u32)sta->rssi_stat.rssi, sta->ra_info.rssi_level); + + if (sta->ra_info.rssi_level != ratr_state_new || ra_tab->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) { + ra_tab->up_ramask_cnt = 0; + PHYDM_PRINT_ADDR(dm, DBG_RA_MASK, "Target AP addr :", sta->mac_addr); + PHYDM_DBG(dm, DBG_RA_MASK, + "Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", + sta->ra_info.rssi_level, ratr_state_new, + sta->rssi_stat.rssi); + + sta->ra_info.rssi_level = ratr_state_new; + phydm_gen_ramask_h2c_AP(dm, priv, entry, sta->ra_info.rssi_level); + } else { + PHYDM_DBG(dm, DBG_RA_MASK, + "Stay in RA level = (( %d ))\n\n", + ratr_state_new); + } + } } +#endif +#endif -void -phydm_init_ra_info( - void *p_dm_void -) +void phydm_rate_adaptive_mask_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; -#if (RTL8822B_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8822B) { - u32 ret_value; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER adapter = dm->adapter; + PMGNT_INFO mgnt_info = &(adapter->MgntInfo); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)dm->adapter)); + + if (mgnt_info->DM_Type == dm_type_by_driver) + hal_data->bUseRAMask = true; + else + hal_data->bUseRAMask = false; - ret_value = odm_get_bb_reg(p_dm_odm, 0x4c8, MASKBYTE2); - odm_set_bb_reg(p_dm_odm, 0x4cc, MASKBYTE3, (ret_value - 1)); - } #endif -} -void -phydm_modify_RA_PCR_threshold( - void *p_dm_void, - u8 RA_offset_direction, - u8 RA_threshold_offset + ra_t->ldpc_thres = 35; + ra_t->up_ramask_cnt = 0; + ra_t->up_ramask_cnt_tmp = 0; +} -) +void phydm_refresh_rate_adaptive_mask(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; +/*@Will be removed*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; - p_ra_table->RA_offset_direction = RA_offset_direction; - p_ra_table->RA_threshold_offset = RA_threshold_offset; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Set RA_threshold_offset = (( %s%d ))\n", ((RA_threshold_offset == 0) ? " " : ((RA_offset_direction) ? "+" : "-")), RA_threshold_offset)); + phydm_ra_mask_watchdog(dm); } -void -odm_rssi_monitor_check_mp( - void *p_dm_void -) +void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; - u32 i; - boolean is_ext_ra_info = true; - u8 cmdlen = H2C_0X42_LENGTH; - u8 tx_bf_en = 0, stbc_en = 0; - - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct sta_info *p_entry = NULL; - s32 tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff; - PMGNT_INFO p_mgnt_info = &adapter->MgntInfo; - PMGNT_INFO p_default_mgnt_info = &adapter->MgntInfo; - u64 cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0; -#if (BEAMFORMING_SUPPORT == 1) -#ifndef BEAMFORMING_VERSION_1 - enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; -#endif + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; +#ifdef CONFIG_BEAMFORMING + struct bf_cmn_info *bf = NULL; #endif - struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(adapter); - - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - is_ext_ra_info = false; - cmdlen = 3; - } + char help[] = "-h"; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i, sta_idx_start, sta_idx_end; + u8 tatal_sta_num = 0; - while (p_loop_adapter) { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]); - if (p_loop_adapter != NULL) { - p_mgnt_info = &p_loop_adapter->MgntInfo; - cur_tx_ok_cnt = p_loop_adapter->TxStats.NumTxBytesUnicast - p_mgnt_info->lastTxOkCnt; - cur_rx_ok_cnt = p_loop_adapter->RxStats.NumRxBytesUnicast - p_mgnt_info->lastRxOkCnt; - p_mgnt_info->lastTxOkCnt = cur_tx_ok_cnt; - p_mgnt_info->lastRxOkCnt = cur_rx_ok_cnt; - } + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "All STA: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "STA[macid]: {2} {macid}\n"); + return; + } else if (var[0] == 1) { + sta_idx_start = 0; + sta_idx_end = ODM_ASSOCIATE_ENTRY_NUM; + } else if (var[0] == 2) { + sta_idx_start = var[1]; + sta_idx_end = var[1]; + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Warning input value!\n"); + return; + } - for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) { - - if (IsAPModeExist(p_loop_adapter)) { - if (GetFirstExtAdapter(p_loop_adapter) != NULL && - GetFirstExtAdapter(p_loop_adapter) == p_loop_adapter) - p_entry = AsocEntry_EnumStation(p_loop_adapter, i); - else if (GetFirstGOPort(p_loop_adapter) != NULL && - IsFirstGoAdapter(p_loop_adapter)) - p_entry = AsocEntry_EnumStation(p_loop_adapter, i); - } else { - if (GetDefaultAdapter(p_loop_adapter) == p_loop_adapter) - p_entry = AsocEntry_EnumStation(p_loop_adapter, i); - } + for (i = sta_idx_start; i < sta_idx_end; i++) { + sta = dm->phydm_sta_info[i]; + + if (!is_sta_active(sta)) + continue; + + ra = &sta->ra_info; + #ifdef CONFIG_BEAMFORMING + bf = &sta->bf_info; + #endif + + tatal_sta_num++; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "==[sta_idx: %d][MACID: %d]============>\n", i, + sta->mac_id); + PDM_SNPF(out_len, used, output + used, out_len - used, + "AID:%d\n", sta->aid); + PDM_SNPF(out_len, used, output + used, out_len - used, + "ADDR:%x-%x-%x-%x-%x-%x\n", sta->mac_addr[5], + sta->mac_addr[4], sta->mac_addr[3], sta->mac_addr[2], + sta->mac_addr[1], sta->mac_addr[0]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "DM_ctrl:0x%x\n", sta->dm_ctrl); + PDM_SNPF(out_len, used, output + used, out_len - used, + "BW:%d, MIMO_Type:0x%x\n", sta->bw_mode, + sta->mimo_type); + PDM_SNPF(out_len, used, output + used, out_len - used, + "STBC_en:%d, LDPC_en=%d\n", sta->stbc_en, + sta->ldpc_en); + + /*@[RSSI Info]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "RSSI{All, OFDM, CCK}={%d, %d, %d}\n", + sta->rssi_stat.rssi, sta->rssi_stat.rssi_ofdm, + sta->rssi_stat.rssi_cck); + + /*@[RA Info]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "Rate_ID:%d, RSSI_LV:%d, ra_bw:%d, SGI_en:%d\n", + ra->rate_id, ra->rssi_level, ra->ra_bw_mode, + ra->is_support_sgi); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "VHT_en:%d, Wireless_set=0x%x, sm_ps=%d\n", + ra->is_vht_enable, sta->support_wireless_set, + sta->sm_ps); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dis{RA, PT}={%d, %d}, TxRx:%d, Noisy:%d\n", + ra->disable_ra, ra->disable_pt, ra->txrx_state, + ra->is_noisy); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "TX{Rate, BW}={0x%x, %d}, RTY:%d\n", ra->curr_tx_rate, + ra->curr_tx_bw, ra->curr_retry_ratio); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "RA_Mask:0x%llx\n", ra->ramask); + + /*@[TP]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "TP{TX,RX}={%d, %d}\n", sta->tx_moving_average_tp, + sta->rx_moving_average_tp); - if (p_entry != NULL) { - if (p_entry->bAssociated) { - - RT_DISP_ADDR(FDM, DM_PWDB, ("p_entry->mac_addr ="), p_entry->MacAddr); - RT_DISP(FDM, DM_PWDB, ("p_entry->rssi = 0x%x(%d)\n", - p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_stat.undecorated_smoothed_pwdb)); - - /* 2 BF_en */ -#if (BEAMFORMING_SUPPORT == 1) -#ifndef BEAMFORMING_VERSION_1 - beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_entry->AssociatedMacId); - if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - tx_bf_en = 1; -#else - if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), p_entry)) - tx_bf_en = 1; -#endif -#endif - /* 2 STBC_en */ - if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(p_entry->VHTInfo.STBC, STBC_VHT_ENABLE_TX)) || - TEST_FLAG(p_entry->HTInfo.STBC, STBC_HT_ENABLE_TX)) - stbc_en = 1; - - if (p_entry->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb) - tmp_entry_min_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - if (p_entry->rssi_stat.undecorated_smoothed_pwdb > tmp_entry_max_pwdb) - tmp_entry_max_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; - - h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - - if (is_ext_ra_info) { - if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6)) - h2c_parameter[3] |= RAINFO_BE_RX_STATE; - - if (tx_bf_en) - h2c_parameter[3] |= RAINFO_BF_STATE; - else { - if (stbc_en) - h2c_parameter[3] |= RAINFO_STBC_STATE; - } - - if (p_dm_odm->noisy_decision) - h2c_parameter[3] |= RAINFO_NOISY_STATE; - else - h2c_parameter[3] &= (~RAINFO_NOISY_STATE); -#if 1 - if (p_dm_odm->h2c_rarpt_connect) { - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("h2c_rarpt_connect = (( %d ))\n", p_dm_odm->h2c_rarpt_connect)); - } -#else - - if (p_entry->rssi_stat.ra_rpt_linked == false) { - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - p_entry->rssi_stat.ra_rpt_linked = true; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("RA First Link, RSSI[%d] = ((%d))\n", - p_entry->associated_mac_id, p_entry->rssi_stat.undecorated_smoothed_pwdb)); - } +#ifdef CONFIG_BEAMFORMING + /*@[Beamforming]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "BF CAP{HT,VHT}={0x%x, 0x%x}\n", bf->ht_beamform_cap, + bf->vht_beamform_cap); + PDM_SNPF(out_len, used, output + used, out_len - used, + "BF {p_aid,g_id}={0x%x, 0x%x}\n\n", bf->p_aid, + bf->g_id); #endif - } - - h2c_parameter[2] = (u8)(p_entry->rssi_stat.undecorated_smoothed_pwdb & 0xFF); - /* h2c_parameter[1] = 0x20; */ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 */ - h2c_parameter[0] = (p_entry->AssociatedMacId); - - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); - } - } else - break; - } + } - p_loop_adapter = GetNextExtAdapter(p_loop_adapter); + if (tatal_sta_num == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "No Linked STA\n"); } + *_used = used; + *_out_len = out_len; +} - /*Default port*/ - if (tmp_entry_max_pwdb != 0) { /* If associated entry is found */ - p_hal_data->EntryMaxUndecoratedSmoothedPWDB = tmp_entry_max_pwdb; - RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n", tmp_entry_max_pwdb, tmp_entry_max_pwdb)); - } else - p_hal_data->EntryMaxUndecoratedSmoothedPWDB = 0; - - if (tmp_entry_min_pwdb != 0xff) { /* If associated entry is found */ - p_hal_data->EntryMinUndecoratedSmoothedPWDB = tmp_entry_min_pwdb; - RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmp_entry_min_pwdb, tmp_entry_min_pwdb)); - - } else - p_hal_data->EntryMinUndecoratedSmoothedPWDB = 0; - - /* Default porti sent RSSI to FW */ - if (p_hal_data->bUseRAMask) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("1 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, p_hal_data->UndecoratedSmoothedPWDB, p_hal_data->ra_rpt_linked)); - if (p_hal_data->UndecoratedSmoothedPWDB > 0) { - - PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_default_mgnt_info); - PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_default_mgnt_info); - - /* BF_en*/ -#if (BEAMFORMING_SUPPORT == 1) -#ifndef BEAMFORMING_VERSION_1 - beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_default_mgnt_info->m_mac_id); - - if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - tx_bf_en = 1; -#else - if (Beamform_GetSupportBeamformerCap(GetDefaultAdapter(adapter), NULL)) - tx_bf_en = 1; -#endif -#endif - - /* STBC_en*/ - if ((IS_WIRELESS_MODE_AC(adapter) && TEST_FLAG(p_vht_info->VhtCurStbc, STBC_VHT_ENABLE_TX)) || - TEST_FLAG(p_ht_info->HtCurStbc, STBC_HT_ENABLE_TX)) - stbc_en = 1; - - h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - - if (is_ext_ra_info) { - if (tx_bf_en) - h2c_parameter[3] |= RAINFO_BF_STATE; - else { - if (stbc_en) - h2c_parameter[3] |= RAINFO_STBC_STATE; - } - -#if 1 - if (p_dm_odm->h2c_rarpt_connect) { - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("h2c_rarpt_connect = (( %d ))\n", p_dm_odm->h2c_rarpt_connect)); - } -#else - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("2 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, p_hal_data->undecorated_smoothed_pwdb, p_hal_data->ra_rpt_linked)); - - if (p_hal_data->ra_rpt_linked == false) { - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("3 RA First Link, RSSI[%d] = ((%d)) , ra_rpt_linked = ((%d))\n", - WIN_DEFAULT_PORT_MACID, p_hal_data->undecorated_smoothed_pwdb, p_hal_data->ra_rpt_linked)); - - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - p_hal_data->ra_rpt_linked = true; - - - } -#endif - - if (p_dm_odm->noisy_decision == 1) { - h2c_parameter[3] |= RAINFO_NOISY_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] Send H2C to FW\n")); - } else - h2c_parameter[3] &= (~RAINFO_NOISY_STATE); - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] h2c_parameter=%x\n", h2c_parameter[3])); - } +u8 phydm_get_tx_stream_num(void *dm_void, enum rf_type type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 tx_num = 1; + + if (type == RF_1T1R || type == RF_1T2R) + tx_num = 1; + else if (type == RF_2T2R || type == RF_2T3R || type == RF_2T4R) + tx_num = 2; + else if (type == RF_3T3R || type == RF_3T4R) + tx_num = 3; + else if (type == RF_4T4R) + tx_num = 4; + else + PHYDM_DBG(dm, DBG_RA, "[Warrning] no mimo_type is found\n"); - h2c_parameter[2] = (u8)(p_hal_data->UndecoratedSmoothedPWDB & 0xFF); - /*h2c_parameter[1] = 0x20;*/ /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ - h2c_parameter[0] = WIN_DEFAULT_PORT_MACID; /* fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1*/ + return tx_num; +} - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); +u64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + enum channel_width bw = 0; + enum wireless_set wrls_mode = 0; + u8 tx_stream_num = 1; + u8 rssi_lv = 0; + u64 ra_mask_bitmap = 0; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + bw = ra->ra_bw_mode; + wrls_mode = sta->support_wireless_set; + tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type); + rssi_lv = ra->rssi_level; + ra_mask_bitmap = ra->ramask; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__); + return 0; + } + + PHYDM_DBG(dm, DBG_RA, "macid=%d ori_RA_Mask= 0x%llx\n", sta->mac_id, + ra_mask_bitmap); + PHYDM_DBG(dm, DBG_RA, + "wireless_mode=0x%x, tx_ss=%d, BW=%d, MimoPs=%d, rssi_lv=%d\n", + wrls_mode, tx_stream_num, bw, sta->sm_ps, rssi_lv); + + if (sta->sm_ps == SM_PS_STATIC) /*@mimo_ps_enable*/ + tx_stream_num = 1; + + /*@[Modify RA Mask by Wireless Mode]*/ + + if (wrls_mode == WIRELESS_CCK) { /*@B mode*/ + ra_mask_bitmap &= 0x0000000f; + } else if (wrls_mode == WIRELESS_OFDM) { /*@G mode*/ + ra_mask_bitmap &= 0x00000ff0; + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) { /*@BG mode*/ + ra_mask_bitmap &= 0x00000ff5; + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) { + /*N_2G*/ + if (tx_stream_num == 1) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x000ff015; + else + ra_mask_bitmap &= 0x000ff005; + } else if (tx_stream_num == 2) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x0ffff015; + else + ra_mask_bitmap &= 0x0ffff005; + } else if (tx_stream_num == 3) { + ra_mask_bitmap &= 0xffffff015; + } else { + ra_mask_bitmap &= 0xffffffff015; } + } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*N_5G*/ - /* BT 3.0 HS mode rssi */ - if (p_dm_odm->is_bt_hs_operation) { - h2c_parameter[2] = p_dm_odm->bt_hs_rssi; - /* h2c_parameter[1] = 0x0; */ - h2c_parameter[0] = WIN_BT_PORT_MACID; - - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); + if (tx_stream_num == 1) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x000ff030; + else + ra_mask_bitmap &= 0x000ff010; + } else if (tx_stream_num == 2) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x0ffff030; + else + ra_mask_bitmap &= 0x0ffff010; + } else if (tx_stream_num == 3) { + ra_mask_bitmap &= 0xffffff010; + } else { + ra_mask_bitmap &= 0xffffffff010; } - } else - PlatformEFIOWrite1Byte(adapter, 0x4fe, (u8)p_hal_data->UndecoratedSmoothedPWDB); - - if ((p_dm_odm->support_ic_type == ODM_RTL8812) || (p_dm_odm->support_ic_type == ODM_RTL8192E)) - odm_rssi_dump_to_register(p_dm_odm); - - - { - struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(adapter); - boolean default_pointer_value, *p_is_link_temp = &default_pointer_value; - s32 global_rssi_min = 0xFF, local_rssi_min; - boolean is_link = false; - - while (p_loop_adapter) { - local_rssi_min = phydm_find_minimum_rssi(p_dm_odm, p_loop_adapter, p_is_link_temp); - /* dbg_print("p_hal_data->is_linked=%d, local_rssi_min=%d\n", p_hal_data->is_linked, local_rssi_min); */ - - if (*p_is_link_temp) - is_link = true; - - if ((local_rssi_min < global_rssi_min) && (*p_is_link_temp)) - global_rssi_min = local_rssi_min; - - p_loop_adapter = GetNextExtAdapter(p_loop_adapter); + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) { + /*@AC_2G*/ + if (tx_stream_num == 1) + ra_mask_bitmap &= 0x003ff015; + else if (tx_stream_num == 2) + ra_mask_bitmap &= 0xfffff015; + else if (tx_stream_num == 3) + ra_mask_bitmap &= 0x3fffffff015; + else /*@AC_4SS 2G*/ + ra_mask_bitmap &= 0x000ffffffffff015; + if (bw == CHANNEL_WIDTH_20) { + /* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/ + ra_mask_bitmap &= 0x0007ffff7fdff015; + } else if (bw == CHANNEL_WIDTH_80) { + /* @AC 80MHz doesn't support 3SS MCS6*/ + ra_mask_bitmap &= 0x000fffbffffff015; } + } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*@AC_5G*/ + + if (tx_stream_num == 1) + ra_mask_bitmap &= 0x003ff010; + else if (tx_stream_num == 2) + ra_mask_bitmap &= 0xfffff010; + else if (tx_stream_num == 3) + ra_mask_bitmap &= 0x3fffffff010; + else /*@AC_4SS 5G*/ + ra_mask_bitmap &= 0x000ffffffffff010; + + if (bw == CHANNEL_WIDTH_20) { + /* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/ + ra_mask_bitmap &= 0x0007ffff7fdff010; + } else if (bw == CHANNEL_WIDTH_80) { + /* @AC 80MHz doesn't support 3SS MCS6*/ + ra_mask_bitmap &= 0x000fffbffffff010; + } + } else { + PHYDM_DBG(dm, DBG_RA, "[Warrning] RA mask is Not found\n"); + } - p_hal_data->bLinked = is_link; - odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_LINK, (u64)is_link); - - if (is_link) - odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, (u64)global_rssi_min); - else - odm_cmn_info_update(&p_hal_data->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, 0); + PHYDM_DBG(dm, DBG_RA, "Mod by mode=0x%llx\n", ra_mask_bitmap); + /*@[Modify RA Mask by RSSI level]*/ + if (wrls_mode != WIRELESS_CCK) { + if (rssi_lv == 0) + ra_mask_bitmap &= 0xffffffffffffffff; + else if (rssi_lv == 1) + ra_mask_bitmap &= 0xfffffffffffffff0; + else if (rssi_lv == 2) + ra_mask_bitmap &= 0xffffffffffffefe0; + else if (rssi_lv == 3) + ra_mask_bitmap &= 0xffffffffffffcfc0; + else if (rssi_lv == 4) + ra_mask_bitmap &= 0xffffffffffff8f80; + else if (rssi_lv >= 5) + ra_mask_bitmap &= 0xffffffffffff0f00; } + PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap); -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ + return ra_mask_bitmap; } -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) -/*H2C_RSSI_REPORT*/ -s8 phydm_rssi_report(struct PHY_DM_STRUCT *p_dm_odm, u8 mac_id) +u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx) { - struct _ADAPTER *adapter = p_dm_odm->adapter; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter); - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; - u8 UL_DL_STATE = 0, STBC_TX = 0, tx_bf_en = 0; - u8 cmdlen = H2C_0X42_LENGTH, first_connect = _FALSE; - u64 cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0; - struct sta_info *p_entry = p_dm_odm->p_odm_sta_info[mac_id]; - - if (!IS_STA_VALID(p_entry)) - return _FAIL; - - if (mac_id != p_entry->mac_id) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u:%u invalid\n", __func__, mac_id, p_entry->mac_id)); - rtw_warn_on(1); - return _FAIL; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + enum wireless_set wrls_set = 0; + u8 rssi_lv = 0; + u8 rate_idx = 0; + u8 rate_ofst = 0; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + wrls_set = sta->support_wireless_set; + rssi_lv = ra->rssi_level; + } else { + pr_debug("[Warning] %s: invalid STA\n", __func__); + return 0; } - if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ - return _FAIL; - - if (p_dm_odm->is_in_lps_pg) - return _FAIL; - - if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi == -1\n", __func__, p_entry->mac_id, MAC_ARG(p_entry->hwaddr))); - return _FAIL; - } + PHYDM_DBG(dm, DBG_RA, "[%s]macid=%d, wireless_set=0x%x, rssi_lv=%d\n", + __func__, sta->mac_id, wrls_set, rssi_lv); - cur_tx_ok_cnt = pdvobjpriv->traffic_stat.cur_tx_bytes; - cur_rx_ok_cnt = pdvobjpriv->traffic_stat.cur_rx_bytes; - if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6)) - UL_DL_STATE = 1; - else - UL_DL_STATE = 0; + rate_ofst = (rssi_lv <= 1) ? 0 : (rssi_lv - 1); -#ifdef CONFIG_BEAMFORMING - { -#if (BEAMFORMING_SUPPORT == 1) - enum beamforming_cap beamform_cap = phydm_beamforming_get_entry_beam_cap_by_mac_id(p_dm_odm, p_entry->mac_id); -#else/*for drv beamforming*/ - enum beamforming_cap beamform_cap = beamforming_get_entry_beam_cap_by_mac_id(&adapter->mlmepriv, p_entry->mac_id); -#endif + if (wrls_set & WIRELESS_VHT) { + rate_idx = ODM_RATEVHTSS1MCS0 + rate_ofst; + } else if (wrls_set & WIRELESS_HT) { + rate_idx = ODM_RATEMCS0 + rate_ofst; + } else if (wrls_set & WIRELESS_OFDM) { + rate_idx = ODM_RATE6M + rate_ofst; + } else { + rate_idx = ODM_RATE1M + rate_ofst; - if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) - tx_bf_en = 1; - else - tx_bf_en = 0; - } -#endif /*#ifdef CONFIG_BEAMFORMING*/ - - if (tx_bf_en) - STBC_TX = 0; - else { -#ifdef CONFIG_80211AC_VHT - if (is_supported_vht(p_entry->wireless_mode)) - STBC_TX = TEST_FLAG(p_entry->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX); - else -#endif - STBC_TX = TEST_FLAG(p_entry->htpriv.stbc_cap, STBC_HT_ENABLE_TX); + if (rate_idx > ODM_RATE11M) + rate_idx = ODM_RATE11M; } + return rate_idx; +} - h2c_parameter[0] = (u8)(p_entry->mac_id & 0xFF); - h2c_parameter[2] = p_entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F; - - if (UL_DL_STATE) - h2c_parameter[3] |= RAINFO_BE_RX_STATE; - - if (tx_bf_en) - h2c_parameter[3] |= RAINFO_BF_STATE; - if (STBC_TX) - h2c_parameter[3] |= RAINFO_STBC_STATE; - if (p_dm_odm->noisy_decision) - h2c_parameter[3] |= RAINFO_NOISY_STATE; +u8 phydm_get_rate_id(void *dm_void, u8 sta_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + enum channel_width bw = 0; + enum wireless_set wrls_mode = 0; + u8 tx_stream_num = 1; + u8 rate_id_idx = PHYDM_BGN_20M_1SS; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + bw = ra->ra_bw_mode; + wrls_mode = sta->support_wireless_set; + tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type); - if ((p_entry->ra_rpt_linked == _FALSE) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_SEND)) { - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - p_entry->ra_rpt_linked = _TRUE; - p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_HOLD; - first_connect = _TRUE; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s: invalid STA\n", __func__); + return 0; } - h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); - -#if 1 - if (first_connect) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__, - p_entry->mac_id, MAC_ARG(p_entry->hwaddr), p_entry->rssi_stat.undecorated_smoothed_pwdb)); + PHYDM_DBG(dm, DBG_RA, "macid=%d,wireless_set=0x%x,tx_SS_num=%d,BW=%d\n", + sta->mac_id, wrls_mode, tx_stream_num, bw); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s RAINFO - TP:%s, TxBF:%s, STBC:%s, Noisy:%s, Firstcont:%s\n", __func__, - (UL_DL_STATE) ? "DL" : "UL", (tx_bf_en) ? "EN" : "DIS", (STBC_TX) ? "EN" : "DIS", - (p_dm_odm->noisy_decision) ? "True" : "False", (first_connect) ? "True" : "False")); - } -#endif + if (wrls_mode == WIRELESS_CCK) { + /*@B mode*/ + rate_id_idx = PHYDM_B_20M; + } else if (wrls_mode == WIRELESS_OFDM) { + /*@G mode*/ + rate_id_idx = PHYDM_G; + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) { + /*@BG mode*/ + rate_id_idx = PHYDM_BG; + } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) { + /*@GN mode*/ + if (tx_stream_num == 1) + rate_id_idx = PHYDM_GN_N1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_GN_N2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR5_N_3SS; + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) { + /*@BGN mode*/ + if (bw == CHANNEL_WIDTH_40) { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_BGN_40M_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_BGN_40M_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR5_N_3SS; + else if (tx_stream_num == 4) + rate_id_idx = PHYDM_ARFR7_N_4SS; - if (p_hal_data->fw_ractrl == _TRUE) { -#if (RTL8188E_SUPPORT == 1) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - cmdlen = 3; -#endif - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); + } else { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_BGN_20M_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_BGN_20M_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR5_N_3SS; + else if (tx_stream_num == 4) + rate_id_idx = PHYDM_ARFR7_N_4SS; + } + } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { + /*@AC mode*/ + if (tx_stream_num == 1) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR4_AC_3SS; + else if (tx_stream_num == 4) + rate_id_idx = PHYDM_ARFR6_AC_4SS; + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) { + /*@AC 2.4G mode*/ + if (bw >= CHANNEL_WIDTH_80) { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR4_AC_3SS; + else if (tx_stream_num == 4) + rate_id_idx = PHYDM_ARFR6_AC_4SS; + } else { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR4_AC_3SS; + else if (tx_stream_num == 4) + rate_id_idx = PHYDM_ARFR6_AC_4SS; + } } else { -#if ((RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)) - if (p_dm_odm->support_ic_type == ODM_RTL8188E) - odm_ra_set_rssi_8188e(p_dm_odm, (u8)(p_entry->mac_id & 0xFF), p_entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F); -#endif + PHYDM_DBG(dm, DBG_RA, "[Warrning] No rate_id is found\n"); + rate_id_idx = 0; } - return _SUCCESS; -} - -void phydm_ra_rssi_rpt_wk_hdl(void *p_context) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_context; - int i; - u8 mac_id = 0xFF; - struct sta_info *p_entry = NULL; - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { - if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ - continue; - if (p_entry->ra_rpt_linked == _FALSE) { - mac_id = i; - break; - } - } - } - if (mac_id != 0xFF) - phydm_rssi_report(p_dm_odm, mac_id); -} -void phydm_ra_rssi_rpt_wk(void *p_context) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_context; + PHYDM_DBG(dm, DBG_RA, "Rate_ID=((0x%x))\n", rate_id_idx); - rtw_run_in_thread_cmd(p_dm_odm->adapter, phydm_ra_rssi_rpt_wk_hdl, p_dm_odm); + return rate_id_idx; } -#endif -void -odm_rssi_monitor_check_ce( - void *p_dm_void -) +void phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt, + u8 no_update_bw, u8 init_ra_lv, u64 ra_mask) { -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct sta_info *p_entry; - int i; - int tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff; - u8 sta_cnt = 0; - - if (p_dm_odm->is_linked != _TRUE) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + u8 h2c_val[H2C_MAX_LENGTH] = {0}; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid sta_info\n", + __func__); return; + } - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - if (IS_STA_VALID(p_entry)) { - if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ - continue; + PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id); - if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1)) - continue; + if (dm->is_disable_power_training) + dis_pt = true; + else if (!dm->is_disable_power_training) + dis_pt = false; - if (p_entry->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb) - tmp_entry_min_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; + h2c_val[0] = sta->mac_id; + h2c_val[1] = (ra->rate_id & 0x1f) | ((init_ra_lv & 0x3) << 5) | + (ra->is_support_sgi << 7); + h2c_val[2] = (u8)((ra->ra_bw_mode) | (((sta->ldpc_en) ? 1 : 0) << 2) | + ((no_update_bw & 0x1) << 3) | + (ra->is_vht_enable << 4) | + ((dis_pt & 0x1) << 6) | ((dis_ra & 0x1) << 7)); - if (p_entry->rssi_stat.undecorated_smoothed_pwdb > tmp_entry_max_pwdb) - tmp_entry_max_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; + h2c_val[3] = (u8)(ra_mask & 0xff); + h2c_val[4] = (u8)((ra_mask & 0xff00) >> 8); + h2c_val[5] = (u8)((ra_mask & 0xff0000) >> 16); + h2c_val[6] = (u8)((ra_mask & 0xff000000) >> 24); - if (phydm_rssi_report(p_dm_odm, i)) - sta_cnt++; - } - } + PHYDM_DBG(dm, DBG_RA, "PHYDM h2c[0x40]=0x%x %x %x %x %x %x %x\n", + h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2], + h2c_val[1], h2c_val[0]); - if (tmp_entry_max_pwdb != 0) /* If associated entry is found */ - p_hal_data->entry_max_undecorated_smoothed_pwdb = tmp_entry_max_pwdb; - else - p_hal_data->entry_max_undecorated_smoothed_pwdb = 0; + odm_fill_h2c_cmd(dm, PHYDM_H2C_RA_MASK, H2C_MAX_LENGTH, h2c_val); - if (tmp_entry_min_pwdb != 0xff) /* If associated entry is found */ - p_hal_data->entry_min_undecorated_smoothed_pwdb = tmp_entry_min_pwdb; - else - p_hal_data->entry_min_undecorated_smoothed_pwdb = 0; + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) { + h2c_val[3] = (u8)((ra_mask >> 32) & 0x000000ff); + h2c_val[4] = (u8)(((ra_mask >> 32) & 0x0000ff00) >> 8); + h2c_val[5] = (u8)(((ra_mask >> 32) & 0x00ff0000) >> 16); + h2c_val[6] = (u8)(((ra_mask >> 32) & 0xff000000) >> 24); - find_minimum_rssi(adapter);/* get pdmpriv->min_undecorated_pwdb_for_dm */ + PHYDM_DBG(dm, DBG_RA, "h2c[0x46]=0x%x %x %x %x %x %x %x\n", + h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], + h2c_val[2], h2c_val[1], h2c_val[0]); - p_dm_odm->rssi_min = p_hal_data->min_undecorated_pwdb_for_dm; - /* odm_cmn_info_update(&p_hal_data->odmpriv,ODM_CMNINFO_RSSI_MIN, pdmpriv->min_undecorated_pwdb_for_dm); */ -#endif/* if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ + odm_fill_h2c_cmd(dm, PHYDM_RA_MASK_ABOVE_3SS, 5, h2c_val); + } + #endif } - -void -odm_rssi_monitor_check_ap( - void *p_dm_void -) +void phydm_ra_registed(void *dm_void, u8 sta_idx, + /*@index of sta_info array, not MACID*/ + u8 rssi_from_assoc) { -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) -#if (RTL8812A_SUPPORT || RTL8881A_SUPPORT || RTL8192E_SUPPORT || RTL8814A_SUPPORT || RTL8197F_SUPPORT) - - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; - u32 i; - boolean is_ext_ra_info = true; - u8 cmdlen = H2C_0X42_LENGTH; - u8 tx_bf_en = 0, stbc_en = 0; - - struct rtl8192cd_priv *priv = p_dm_odm->priv; - struct sta_info *pstat; - boolean act_bfer = false; - -#if (BEAMFORMING_SUPPORT == 1) - u8 idx = 0xff; -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) - struct _BF_DIV_COEX_ *p_dm_bdc_table = &p_dm_odm->dm_bdc_table; - p_dm_bdc_table->num_txbfee_client = 0; - p_dm_bdc_table->num_txbfer_client = 0; -#endif -#endif - if (!p_dm_odm->h2c_rarpt_connect && (priv->up_time % 2)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + u8 init_ra_lv = 0; + u64 ra_mask = 0; + /*@SD7 STA_idx != macid*/ + /*@SD4,8 STA_idx == macid, */ + + PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__); + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx, + sta->mac_id); + } else { + PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid STA\n", + __func__); + PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d\n", sta_idx); return; - - if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - is_ext_ra_info = false; - cmdlen = 3; } - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - pstat = p_dm_odm->p_odm_sta_info[i]; - - if (IS_STA_VALID(pstat)) { - if (pstat->sta_in_firmware != 1) - continue; + #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) + ra->rate_id = phydm_get_rate_id_88e(dm, sta_idx); + else + #endif + { + ra->rate_id = phydm_get_rate_id(dm, sta_idx); + } - /* 2 BF_en */ -#if (BEAMFORMING_SUPPORT == 1) - BEAMFORMING_CAP beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, pstat->aid); - PRT_BEAMFORMING_ENTRY p_entry = Beamforming_GetEntryByMacId(priv, pstat->aid, &idx); + ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx); - if (beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { + PHYDM_DBG(dm, DBG_RA_MASK, "rssi_assoc=%d\n", rssi_from_assoc); - if (p_entry->Sounding_En) - tx_bf_en = 1; - else - tx_bf_en = 0; + if (rssi_from_assoc > 40) + init_ra_lv = 1; + else if (rssi_from_assoc > 20) + init_ra_lv = 2; + else if (rssi_from_assoc > 1) + init_ra_lv = 3; + else + init_ra_lv = 0; - act_bfer = true; - } + if (ra_t->record_ra_info) + ra_t->record_ra_info(dm, sta_idx, sta, ra_mask); -#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*BDC*/ - if (act_bfer == true) { - p_dm_bdc_table->w_bfee_client[i] = 1; /* AP act as BFer */ - p_dm_bdc_table->num_txbfee_client++; - } else { - p_dm_bdc_table->w_bfee_client[i] = 0; /* AP act as BFer */ - } + #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) + /*@Driver RA*/ + phydm_ra_update_8188e(dm, sta_idx, ra->rate_id, + (u32)ra_mask, ra->is_support_sgi); + else + #endif + { + /*@FW RA*/ + phydm_ra_h2c(dm, sta_idx, ra->disable_ra, ra->disable_pt, 0, + init_ra_lv, ra_mask); + } +} - if ((beamform_cap & BEAMFORMEE_CAP_HT_EXPLICIT) || (beamform_cap & BEAMFORMEE_CAP_VHT_SU)) { - p_dm_bdc_table->w_bfer_client[i] = 1; /* AP act as BFee */ - p_dm_bdc_table->num_txbfer_client++; - } else { - p_dm_bdc_table->w_bfer_client[i] = 0; /* AP act as BFer */ - } -#endif -#endif +void phydm_ra_offline(void *dm_void, u8 sta_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; - /* 2 STBC_en */ - if ((priv->pmib->dot11nConfigEntry.dot11nSTBC) && - ((pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_RX_STBC_CAP_)) -#ifdef RTK_AC_SUPPORT - || (pstat->vht_cap_buf.vht_cap_info & cpu_to_le32(_VHTCAP_RX_STBC_CAP_)) -#endif - )) - stbc_en = 1; + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__); + return; + } - /* 2 RAINFO */ + PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id); - h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); + odm_memory_set(dm, &ra->rate_id, 0, sizeof(struct ra_sta_info)); + ra->disable_ra = 1; + ra->disable_pt = 1; - if (is_ext_ra_info) { - if ((pstat->rx_avarage) > ((pstat->tx_avarage) * 6)) - h2c_parameter[3] |= RAINFO_BE_RX_STATE; + if (ra_t->record_ra_info) + ra_t->record_ra_info(dm, sta->mac_id, sta, 0); - if (tx_bf_en) - h2c_parameter[3] |= RAINFO_BF_STATE; - else { - if (stbc_en) - h2c_parameter[3] |= RAINFO_STBC_STATE; - } + if (dm->support_ic_type != ODM_RTL8188E) + phydm_ra_h2c(dm, sta->mac_id, 1, 1, 0, 0, 0); +} - if (p_dm_odm->noisy_decision) - h2c_parameter[3] |= RAINFO_NOISY_STATE; - else - h2c_parameter[3] &= (~RAINFO_NOISY_STATE); +void phydm_ra_mask_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; + u8 sta_idx; + u64 ra_mask; + u8 rssi_lv_new; + u8 rssi = 0; + + if (!(dm->support_ability & ODM_BB_RA_MASK)) + return; - if (pstat->H2C_rssi_rpt) { - h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[RA Init] set Init rate by RSSI, STA %d\n", pstat->aid)); - } + if (!dm->is_linked || (dm->phydm_sys_up_time % 2) == 1) + return; - /*ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RAINFO] H2C_Para[3] = %x\n",h2c_parameter[3]));*/ + PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__); + + ra_t->up_ramask_cnt++; + + for (sta_idx = 0; sta_idx < ODM_ASSOCIATE_ENTRY_NUM; sta_idx++) { + sta = dm->phydm_sta_info[sta_idx]; + + if (!is_sta_active(sta)) + continue; + + ra = &sta->ra_info; + + if (ra->disable_ra) + continue; + + PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx, + sta->mac_id); + + rssi = (u8)(sta->rssi_stat.rssi); + + /*@to be modified*/ + #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + if (dm->support_ic_type == ODM_RTL8812 || + (dm->support_ic_type == ODM_RTL8821 && + dm->cut_version == ODM_CUT_A) + ) { + if (rssi < ra_t->ldpc_thres) { + /*@LDPC TX enable*/ + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + set_ra_ldpc_8812(sta, true); + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + MgntSet_TX_LDPC(sta->mac_id, true); + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + /*to be added*/ + #endif + PHYDM_DBG(dm, DBG_RA_MASK, + "RSSI=%d, ldpc_en =TRUE\n", rssi); + + } else if (rssi > (ra_t->ldpc_thres + 3)) { + /*@LDPC TX disable*/ + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + set_ra_ldpc_8812(sta, false); + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + MgntSet_TX_LDPC(sta->mac_id, false); + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + /*to be added*/ + #endif + PHYDM_DBG(dm, DBG_RA_MASK, + "RSSI=%d, ldpc_en =FALSE\n", rssi); } + } + #endif - h2c_parameter[2] = (u8)(pstat->rssi & 0xFF); - h2c_parameter[0] = REMAP_AID(pstat); + rssi_lv_new = phydm_rssi_lv_dec(dm, (u32)rssi, ra->rssi_level); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("h2c_parameter[3]=%d\n", h2c_parameter[3])); + if (ra->rssi_level != rssi_lv_new || + ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) { + PHYDM_DBG(dm, DBG_RA_MASK, "RSSI LV:((%d))->((%d))\n", + ra->rssi_level, rssi_lv_new); - /* ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RSSI] H2C_Para[2] = %x,\n",h2c_parameter[2])); */ - /* ODM_RT_TRACE(p_dm_odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[MACID] H2C_Para[0] = %x,\n",h2c_parameter[0])); */ + ra->rssi_level = rssi_lv_new; + ra_t->up_ramask_cnt = 0; - odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); + ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx); + if (ra_t->record_ra_info) + ra_t->record_ra_info(dm, sta_idx, sta, ra_mask); + + #if (RTL8188E_SUPPORT) && (RATE_ADAPTIVE_SUPPORT) + if (dm->support_ic_type == ODM_RTL8188E) + /*@Driver RA*/ + phydm_ra_update_8188e(dm, sta_idx, ra->rate_id, + (u32)ra_mask, + ra->is_support_sgi); + else + #endif + { + /*@FW RA*/ + phydm_ra_h2c(dm, sta_idx, ra->disable_ra, + ra->disable_pt, 1, 0, ra_mask); + } } } - -#endif -#endif - } -void -odm_rssi_monitor_check( - void *p_dm_void -) +u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (!(p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR)) - return; - - switch (p_dm_odm->support_platform) { - case ODM_WIN: - odm_rssi_monitor_check_mp(p_dm_odm); - break; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 vht_en_out = 0; - case ODM_CE: - odm_rssi_monitor_check_ce(p_dm_odm); - break; + if (wireless_mode == PHYDM_WIRELESS_MODE_AC_5G || + wireless_mode == PHYDM_WIRELESS_MODE_AC_24G || + wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY) + vht_en_out = 1; - case ODM_AP: - odm_rssi_monitor_check_ap(p_dm_odm); - break; + PHYDM_DBG(dm, DBG_RA, "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n", + wireless_mode, vht_en_out); + return vht_en_out; +} - default: - break; - } +u8 phydm_rftype2rateid_2g_n20(void *dm_void, u8 rf_type) +{ + u8 rate_id_idx = 0; + if (rf_type == RF_1T1R) + rate_id_idx = PHYDM_BGN_20M_1SS; + else if (rf_type == RF_2T2R) + rate_id_idx = PHYDM_BGN_20M_2SS; + else if (rf_type == RF_3T3R) + rate_id_idx = PHYDM_ARFR5_N_3SS; + else + rate_id_idx = PHYDM_ARFR7_N_4SS; + return rate_id_idx; } -void -odm_rate_adaptive_mask_init( - void *p_dm_void -) +u8 phydm_rftype2rateid_2g_n40(void *dm_void, u8 rf_type) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_RATE_ADAPTIVE *p_odm_ra = &p_dm_odm->rate_adaptive; + u8 rate_id_idx = 0; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PMGNT_INFO p_mgnt_info = &p_dm_odm->adapter->MgntInfo; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); + if (rf_type == RF_1T1R) + rate_id_idx = PHYDM_BGN_40M_1SS; + else if (rf_type == RF_2T2R) + rate_id_idx = PHYDM_BGN_40M_2SS; + else if (rf_type == RF_3T3R) + rate_id_idx = PHYDM_ARFR5_N_3SS; + else + rate_id_idx = PHYDM_ARFR7_N_4SS; + return rate_id_idx; +} - p_mgnt_info->Ratr_State = DM_RATR_STA_INIT; +u8 phydm_rftype2rateid_5g_n(void *dm_void, u8 rf_type) +{ + u8 rate_id_idx = 0; - if (p_mgnt_info->DM_Type == dm_type_by_driver) - p_hal_data->bUseRAMask = true; + if (rf_type == RF_1T1R) + rate_id_idx = PHYDM_GN_N1SS; + else if (rf_type == RF_2T2R) + rate_id_idx = PHYDM_GN_N2SS; + else if (rf_type == RF_3T3R) + rate_id_idx = PHYDM_ARFR5_N_3SS; else - p_hal_data->bUseRAMask = false; + rate_id_idx = PHYDM_ARFR7_N_4SS; + return rate_id_idx; +} + +u8 phydm_rftype2rateid_ac80(void *dm_void, u8 rf_type) +{ + u8 rate_id_idx = 0; -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - p_odm_ra->type = dm_type_by_driver; - if (p_odm_ra->type == dm_type_by_driver) - p_dm_odm->is_use_ra_mask = _TRUE; + if (rf_type == RF_1T1R) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (rf_type == RF_2T2R) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else if (rf_type == RF_3T3R) + rate_id_idx = PHYDM_ARFR4_AC_3SS; else - p_dm_odm->is_use_ra_mask = _FALSE; -#endif + rate_id_idx = PHYDM_ARFR6_AC_4SS; + return rate_id_idx; +} - p_odm_ra->ratr_state = DM_RATR_STA_INIT; +u8 phydm_rftype2rateid_ac40(void *dm_void, u8 rf_type) +{ + u8 rate_id_idx = 0; -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - if (p_dm_odm->support_ic_type == ODM_RTL8812) - p_odm_ra->ldpc_thres = 50; + if (rf_type == RF_1T1R) + rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; + else if (rf_type == RF_2T2R) + rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; + else if (rf_type == RF_3T3R) + rate_id_idx = PHYDM_ARFR4_AC_3SS; else - p_odm_ra->ldpc_thres = 35; + rate_id_idx = PHYDM_ARFR6_AC_4SS; + return rate_id_idx; +} - p_odm_ra->rts_thres = 35; +u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rate_id_idx = 0; -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - p_odm_ra->ldpc_thres = 35; - p_odm_ra->is_use_ldpc = false; + PHYDM_DBG(dm, DBG_RA, + "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n", + wireless_mode, rf_type, bw); -#else - p_odm_ra->ultra_low_rssi_thresh = 9; + switch (wireless_mode) { + case PHYDM_WIRELESS_MODE_N_24G: + if (bw == CHANNEL_WIDTH_40) + rate_id_idx = phydm_rftype2rateid_2g_n40(dm, rf_type); + else + rate_id_idx = phydm_rftype2rateid_2g_n20(dm, rf_type); + break; -#endif + case PHYDM_WIRELESS_MODE_N_5G: + rate_id_idx = phydm_rftype2rateid_5g_n(dm, rf_type); + break; - p_odm_ra->high_rssi_thresh = 50; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ - ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - p_odm_ra->low_rssi_thresh = 23; -#else - p_odm_ra->low_rssi_thresh = 20; -#endif -} -/*----------------------------------------------------------------------------- - * Function: odm_refresh_rate_adaptive_mask() - * - * Overview: Update rate table mask according to rssi - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 05/27/2009 hpfan Create version 0. - * - *---------------------------------------------------------------------------*/ -void -odm_refresh_rate_adaptive_mask( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + case PHYDM_WIRELESS_MODE_G: + rate_id_idx = PHYDM_BG; + break; - if (!p_dm_odm->is_linked) - return; + case PHYDM_WIRELESS_MODE_A: + rate_id_idx = PHYDM_G; + break; - if (!(p_dm_odm->support_ability & ODM_BB_RA_MASK)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_refresh_rate_adaptive_mask(): Return cos not supported\n")); - return; - } + case PHYDM_WIRELESS_MODE_B: + rate_id_idx = PHYDM_B_20M; + break; - p_ra_table->force_update_ra_mask_count++; - /* */ - /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ - /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ - /* HW dynamic mechanism. */ - /* */ - switch (p_dm_odm->support_platform) { - case ODM_WIN: - odm_refresh_rate_adaptive_mask_mp(p_dm_odm); + case PHYDM_WIRELESS_MODE_AC_5G: + case PHYDM_WIRELESS_MODE_AC_ONLY: + rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type); break; - case ODM_CE: - odm_refresh_rate_adaptive_mask_ce(p_dm_odm); + case PHYDM_WIRELESS_MODE_AC_24G: +/*@Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/ + if (bw >= CHANNEL_WIDTH_80) + rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type); + else + rate_id_idx = phydm_rftype2rateid_ac40(dm, rf_type); break; - case ODM_AP: - odm_refresh_rate_adaptive_mask_apadsl(p_dm_odm); + default: + rate_id_idx = 0; break; } + PHYDM_DBG(dm, DBG_RA, "RA rate ID = (( 0x%x ))\n", rate_id_idx); + + return rate_id_idx; } -u8 -phydm_trans_platform_bw( - void *p_dm_void, - u8 BW -) +u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state) { -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (BW == CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == CHANNEL_WIDTH_40) - BW = PHYDM_BW_40; - - else if (BW == CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == CHANNEL_WIDTH_80_80) - BW = PHYDM_BW_80_80; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - if (BW == HT_CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == HT_CHANNEL_WIDTH_20_40) - BW = PHYDM_BW_40; - - else if (BW == HT_CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == HT_CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == HT_CHANNEL_WIDTH_10) - BW = PHYDM_BW_10; - - else if (BW == HT_CHANNEL_WIDTH_5) - BW = PHYDM_BW_5; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (BW == CHANNEL_WIDTH_20) - BW = PHYDM_BW_20; - - else if (BW == CHANNEL_WIDTH_40) - BW = PHYDM_BW_40; - - else if (BW == CHANNEL_WIDTH_80) - BW = PHYDM_BW_80; - - else if (BW == CHANNEL_WIDTH_160) - BW = PHYDM_BW_160; - - else if (BW == CHANNEL_WIDTH_80_80) - BW = PHYDM_BW_80_80; -#endif - - return BW; - -} - -u8 -phydm_trans_platform_rf_type( - void *p_dm_void, - u8 rf_type -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (rf_type == RF_1T2R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == RF_2T4R) - rf_type = PHYDM_RF_2T4R; - - else if (rf_type == RF_2T2R) - rf_type = PHYDM_RF_2T2R; - - else if (rf_type == RF_1T1R) - rf_type = PHYDM_RF_1T1R; - - else if (rf_type == RF_2T2R_GREEN) - rf_type = PHYDM_RF_2T2R_GREEN; - - else if (rf_type == RF_3T3R) - rf_type = PHYDM_RF_3T3R; - - else if (rf_type == RF_4T4R) - rf_type = PHYDM_RF_4T4R; - - else if (rf_type == RF_2T3R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == RF_3T4R) - rf_type = PHYDM_RF_3T4R; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - if (rf_type == MIMO_1T2R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == MIMO_2T4R) - rf_type = PHYDM_RF_2T4R; - - else if (rf_type == MIMO_2T2R) - rf_type = PHYDM_RF_2T2R; - - else if (rf_type == MIMO_1T1R) - rf_type = PHYDM_RF_1T1R; - - else if (rf_type == MIMO_3T3R) - rf_type = PHYDM_RF_3T3R; - - else if (rf_type == MIMO_4T4R) - rf_type = PHYDM_RF_4T4R; - - else if (rf_type == MIMO_2T3R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == MIMO_3T4R) - rf_type = PHYDM_RF_3T4R; - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (rf_type == RF_1T2R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == RF_2T4R) - rf_type = PHYDM_RF_2T4R; - - else if (rf_type == RF_2T2R) - rf_type = PHYDM_RF_2T2R; - - else if (rf_type == RF_1T1R) - rf_type = PHYDM_RF_1T1R; - - else if (rf_type == RF_2T2R_GREEN) - rf_type = PHYDM_RF_2T2R_GREEN; - - else if (rf_type == RF_3T3R) - rf_type = PHYDM_RF_3T3R; - - else if (rf_type == RF_4T4R) - rf_type = PHYDM_RF_4T4R; - - else if (rf_type == RF_2T3R) - rf_type = PHYDM_RF_1T2R; - - else if (rf_type == RF_3T4R) - rf_type = PHYDM_RF_3T4R; - -#endif - - return rf_type; - -} - -u32 -phydm_trans_platform_wireless_mode( - void *p_dm_void, - u32 wireless_mode -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - - if (wireless_mode == WIRELESS_11A) - wireless_mode = PHYDM_WIRELESS_MODE_A; - - else if (wireless_mode == WIRELESS_11B) - wireless_mode = PHYDM_WIRELESS_MODE_B; - - else if ((wireless_mode == WIRELESS_11G) || (wireless_mode == WIRELESS_11BG)) - wireless_mode = PHYDM_WIRELESS_MODE_G; - - else if (wireless_mode == WIRELESS_AUTO) - wireless_mode = PHYDM_WIRELESS_MODE_AUTO; - - else if ((wireless_mode == WIRELESS_11_24N) || (wireless_mode == WIRELESS_11G_24N) || (wireless_mode == WIRELESS_11B_24N) || - (wireless_mode == WIRELESS_11BG_24N) || (wireless_mode == WIRELESS_MODE_24G) || (wireless_mode == WIRELESS_11ABGN) || (wireless_mode == WIRELESS_11AGN)) - wireless_mode = PHYDM_WIRELESS_MODE_N_24G; - - else if ((wireless_mode == WIRELESS_11_5N) || (wireless_mode == WIRELESS_11A_5N)) - wireless_mode = PHYDM_WIRELESS_MODE_N_5G; - - else if ((wireless_mode == WIRELESS_11AC) || (wireless_mode == WIRELESS_11_5AC) || (wireless_mode == WIRELESS_MODE_5G)) - wireless_mode = PHYDM_WIRELESS_MODE_AC_5G; - - else if (wireless_mode == WIRELESS_11_24AC) - wireless_mode = PHYDM_WIRELESS_MODE_AC_24G; - - else if (wireless_mode == WIRELESS_11AC) - wireless_mode = PHYDM_WIRELESS_MODE_AC_ONLY; - - else if (wireless_mode == WIRELESS_MODE_MAX) - wireless_mode = PHYDM_WIRELESS_MODE_MAX; - else - wireless_mode = PHYDM_WIRELESS_MODE_UNKNOWN; -#endif - - return wireless_mode; - -} - -u8 -phydm_vht_en_mapping( - void *p_dm_void, - u32 wireless_mode -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 vht_en_out = 0; - - if ((wireless_mode == PHYDM_WIRELESS_MODE_AC_5G) || - (wireless_mode == PHYDM_WIRELESS_MODE_AC_24G) || - (wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY) - ) { - vht_en_out = 1; - /**/ - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n", wireless_mode, vht_en_out)); - return vht_en_out; -} - -u8 -phydm_rate_id_mapping( - void *p_dm_void, - u32 wireless_mode, - u8 rf_type, - u8 bw -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 rate_id_idx = 0; - u8 phydm_BW; - u8 phydm_rf_type; - - phydm_BW = phydm_trans_platform_bw(p_dm_odm, bw); - phydm_rf_type = phydm_trans_platform_rf_type(p_dm_odm, rf_type); -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - wireless_mode = phydm_trans_platform_wireless_mode(p_dm_odm, wireless_mode); -#endif - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n", - wireless_mode, phydm_rf_type, phydm_BW)); - - - switch (wireless_mode) { - - case PHYDM_WIRELESS_MODE_N_24G: - { - - if (phydm_BW == PHYDM_BW_40) { - - if (phydm_rf_type == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_BGN_40M_1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_BGN_40M_2SS; - else - rate_id_idx = PHYDM_ARFR5_N_3SS; - - } else { - - if (phydm_rf_type == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_BGN_20M_1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_BGN_20M_2SS; - else - rate_id_idx = PHYDM_ARFR5_N_3SS; - } - } - break; - - case PHYDM_WIRELESS_MODE_N_5G: - { - if (phydm_rf_type == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_GN_N1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_GN_N2SS; - else - rate_id_idx = PHYDM_ARFR5_N_3SS; - } - - break; - - case PHYDM_WIRELESS_MODE_G: - rate_id_idx = PHYDM_BG; - break; - - case PHYDM_WIRELESS_MODE_A: - rate_id_idx = PHYDM_G; - break; - - case PHYDM_WIRELESS_MODE_B: - rate_id_idx = PHYDM_B_20M; - break; - - - case PHYDM_WIRELESS_MODE_AC_5G: - case PHYDM_WIRELESS_MODE_AC_ONLY: - { - if (phydm_rf_type == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_ARFR1_AC_1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_ARFR0_AC_2SS; - else - rate_id_idx = PHYDM_ARFR4_AC_3SS; - } - break; - - case PHYDM_WIRELESS_MODE_AC_24G: - { - /*Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/ - if (phydm_BW >= PHYDM_BW_80) { - if (phydm_rf_type == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_ARFR1_AC_1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_ARFR0_AC_2SS; - else - rate_id_idx = PHYDM_ARFR4_AC_3SS; - } else { - - if (phydm_rf_type == PHYDM_RF_1T1R) - rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; - else if (phydm_rf_type == PHYDM_RF_2T2R) - rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; - else - rate_id_idx = PHYDM_ARFR4_AC_3SS; - } - } - break; - - default: - rate_id_idx = 0; - break; - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA rate ID = (( 0x%x ))\n", rate_id_idx)); - - return rate_id_idx; -} - -void -phydm_update_hal_ra_mask( - void *p_dm_void, - u32 wireless_mode, - u8 rf_type, - u8 BW, - u8 mimo_ps_enable, - u8 disable_cck_rate, - u32 *ratr_bitmap_msb_in, - u32 *ratr_bitmap_lsb_in, - u8 tx_rate_level -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 mask_rate_threshold; - u8 phydm_rf_type; - u8 phydm_BW; - u32 ratr_bitmap = *ratr_bitmap_lsb_in, ratr_bitmap_msb = *ratr_bitmap_msb_in; - /*struct _ODM_RATE_ADAPTIVE* p_ra = &(p_dm_odm->rate_adaptive);*/ - -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - wireless_mode = phydm_trans_platform_wireless_mode(p_dm_odm, wireless_mode); -#endif - - phydm_rf_type = phydm_trans_platform_rf_type(p_dm_odm, rf_type); - phydm_BW = phydm_trans_platform_bw(p_dm_odm, BW); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type));*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Platfoem original RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap)); - - switch (wireless_mode) { - - case PHYDM_WIRELESS_MODE_B: - { - ratr_bitmap &= 0x0000000f; - } - break; - - case PHYDM_WIRELESS_MODE_G: - { - ratr_bitmap &= 0x00000ff5; - } - break; - - case PHYDM_WIRELESS_MODE_A: - { - ratr_bitmap &= 0x00000ff0; - } - break; - - case PHYDM_WIRELESS_MODE_N_24G: - case PHYDM_WIRELESS_MODE_N_5G: - { - if (mimo_ps_enable) - phydm_rf_type = PHYDM_RF_1T1R; - - if (phydm_rf_type == PHYDM_RF_1T1R) { - - if (phydm_BW == PHYDM_BW_40) - ratr_bitmap &= 0x000ff015; - else - ratr_bitmap &= 0x000ff005; - } else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) { - - if (phydm_BW == PHYDM_BW_40) - ratr_bitmap &= 0x0ffff015; - else - ratr_bitmap &= 0x0ffff005; - } else { /*3T*/ - - ratr_bitmap &= 0xfffff015; - ratr_bitmap_msb &= 0xf; - } - } - break; - - case PHYDM_WIRELESS_MODE_AC_24G: - { - if (phydm_rf_type == PHYDM_RF_1T1R) - ratr_bitmap &= 0x003ff015; - else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) - ratr_bitmap &= 0xfffff015; - else {/*3T*/ - - ratr_bitmap &= 0xfffff010; - ratr_bitmap_msb &= 0x3ff; - } - - if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ - ratr_bitmap &= 0x7fdfffff; - ratr_bitmap_msb &= 0x1ff; - } - } - break; - - case PHYDM_WIRELESS_MODE_AC_5G: - { - if (phydm_rf_type == PHYDM_RF_1T1R) - ratr_bitmap &= 0x003ff010; - else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) - ratr_bitmap &= 0xfffff010; - else {/*3T*/ - - ratr_bitmap &= 0xfffff010; - ratr_bitmap_msb &= 0x3ff; - } - - if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ - ratr_bitmap &= 0x7fdfffff; - ratr_bitmap_msb &= 0x1ff; - } - } - break; - - default: - break; - } - - if (wireless_mode != PHYDM_WIRELESS_MODE_B) { - - if (tx_rate_level == 0) - ratr_bitmap &= 0xffffffff; - else if (tx_rate_level == 1) - ratr_bitmap &= 0xfffffff0; - else if (tx_rate_level == 2) - ratr_bitmap &= 0xffffefe0; - else if (tx_rate_level == 3) - ratr_bitmap &= 0xffffcfc0; - else if (tx_rate_level == 4) - ratr_bitmap &= 0xffff8f80; - else if (tx_rate_level >= 5) - ratr_bitmap &= 0xffff0f00; - - } - - if (disable_cck_rate) - ratr_bitmap &= 0xfffffff0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n", - wireless_mode, phydm_rf_type, phydm_BW, mimo_ps_enable, tx_rate_level)); - - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap));*/ - - *ratr_bitmap_lsb_in = ratr_bitmap; - *ratr_bitmap_msb_in = ratr_bitmap_msb; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Phydm modified RA Mask = (( 0x %x | %x ))\n", *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in)); - -} - -u8 -phydm_RA_level_decision( - void *p_dm_void, - u32 rssi, - u8 ratr_state -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 ra_lowest_rate; - u8 ra_rate_floor_table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/ - u8 new_ratr_state = 0; - u8 i; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("curr RA level = ((%d)), Rate_floor_table ori [ %d , %d, %d , %d, %d, %d]\n", ratr_state, - ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); - - for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { - - if (i >= (ratr_state)) - ra_rate_floor_table[i] += RA_FLOOR_UP_GAP; - } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI = ((%d)), Rate_floor_table_mod [ %d , %d, %d , %d, %d, %d]\n", - rssi, ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); - - for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { - - if (rssi < ra_rate_floor_table[i]) { - new_ratr_state = i; - break; - } - } - - - - return new_ratr_state; - -} - -void -odm_refresh_rate_adaptive_mask_mp( - void *p_dm_void -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - struct _ADAPTER *p_target_adapter = NULL; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(p_adapter); - struct _ADAPTER *p_loop_adapter = GetDefaultAdapter(p_adapter); - PMGNT_INFO p_loop_mgnt_info = &(p_loop_adapter->MgntInfo); - HAL_DATA_TYPE *p_loop_hal_data = GET_HAL_DATA(p_loop_adapter); - - u32 i; - struct sta_info *p_entry; - u8 ratr_state_new; - - if (p_adapter->bDriverStopped) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_refresh_rate_adaptive_mask(): driver is going to unload\n")); - return; - } - - if (!p_hal_data->bUseRAMask) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_refresh_rate_adaptive_mask(): driver does not control rate adaptive mask\n")); - return; - } - - /* if default port is connected, update RA table for default port (infrastructure mode only) */ - /* Need to consider other ports for P2P cases*/ - - while(p_loop_adapter){ - - p_loop_mgnt_info = &(p_loop_adapter->MgntInfo); - p_loop_hal_data = GET_HAL_DATA(p_loop_adapter); - - if (p_loop_mgnt_info->mAssoc && (!ACTING_AS_AP(p_loop_adapter))) { - odm_refresh_ldpc_rts_mp(p_loop_adapter, p_dm_odm, p_loop_mgnt_info->mMacId, p_loop_mgnt_info->IOTPeer, p_loop_hal_data->UndecoratedSmoothedPWDB); - /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Infrasture mode\n"));*/ - -#if RA_MASK_PHYDMLIZE_WIN - ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_loop_hal_data->UndecoratedSmoothedPWDB, p_loop_mgnt_info->Ratr_State); - - if ((p_loop_mgnt_info->Ratr_State != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { - - p_ra_table->force_update_ra_mask_count = 0; - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_loop_mgnt_info->Bssid); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n\n", - p_mgnt_info->Ratr_State, ratr_state_new, p_loop_hal_data->UndecoratedSmoothedPWDB)); - - p_loop_mgnt_info->Ratr_State = ratr_state_new; - p_adapter->HalFunc.UpdateHalRAMaskHandler(p_loop_adapter, p_loop_mgnt_info->mMacId, NULL, ratr_state_new); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); - /**/ - } - -#else - if (odm_ra_state_check(p_dm_odm, p_hal_data->UndecoratedSmoothedPWDB, p_mgnt_info->bSetTXPowerTrainingByOid, &p_mgnt_info->Ratr_State)) { - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), p_mgnt_info->Bssid); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_hal_data->UndecoratedSmoothedPWDB, p_mgnt_info->Ratr_State)); - p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State); - } else if (p_dm_odm->is_change_state) { - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), p_mgnt_info->Bssid); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training)); - p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State); - } -#endif - - } - - p_loop_adapter = GetNextExtAdapter(p_loop_adapter); - } - - /* */ - /* The following part configure AP/VWifi/IBSS rate adaptive mask. */ - /* */ - - if (p_mgnt_info->mIbss) /* Target: AP/IBSS peer. */ - p_target_adapter = GetDefaultAdapter(p_adapter); - else - p_target_adapter = GetFirstAPAdapter(p_adapter); - - /* if extension port (softap) is started, updaet RA table for more than one clients associate */ - if (p_target_adapter != NULL) { - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - p_entry = AsocEntry_EnumStation(p_target_adapter, i); - - if (IS_STA_VALID(p_entry)) { - - odm_refresh_ldpc_rts_mp(p_target_adapter, p_dm_odm, p_entry->AssociatedMacId, p_entry->IOTPeer, p_entry->rssi_stat.undecorated_smoothed_pwdb); - -#if RA_MASK_PHYDMLIZE_WIN - ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->Ratr_State); - - if ((p_entry->Ratr_State != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { - - p_ra_table->force_update_ra_mask_count = 0; - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_entry->MacAddr); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", - p_entry->Ratr_State, ratr_state_new, p_entry->rssi_stat.undecorated_smoothed_pwdb)); - - p_entry->Ratr_State = ratr_state_new; - p_adapter->HalFunc.UpdateHalRAMaskHandler(p_target_adapter, p_entry->AssociatedMacId, p_entry, ratr_state_new); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); - /**/ - } - - -#else - - if (odm_ra_state_check(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_mgnt_info->bSetTXPowerTrainingByOid, &p_entry->Ratr_State)) { - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), p_entry->mac_addr); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->Ratr_State)); - p_adapter->hal_func.update_hal_ra_mask_handler(p_target_adapter, p_entry->AssociatedMacId, p_entry, p_entry->Ratr_State); - } else if (p_dm_odm->is_change_state) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training)); - p_adapter->HalFunc.UpdateHalRAMaskHandler(p_adapter, p_mgnt_info->mMacId, NULL, p_mgnt_info->Ratr_State); - } -#endif - - } - } - } - -#if RA_MASK_PHYDMLIZE_WIN - -#else - if (p_mgnt_info->bSetTXPowerTrainingByOid) - p_mgnt_info->bSetTXPowerTrainingByOid = false; -#endif -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) */ -} - - -void -odm_refresh_rate_adaptive_mask_ce( - void *p_dm_void -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive; - u32 i; - struct sta_info *p_entry; - u8 ratr_state_new; - - if (RTW_CANNOT_RUN(p_adapter)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_refresh_rate_adaptive_mask(): driver is going to unload\n")); - return; - } - - if (!p_dm_odm->is_use_ra_mask) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_refresh_rate_adaptive_mask(): driver does not control rate adaptive mask\n")); - return; - } - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - - p_entry = p_dm_odm->p_odm_sta_info[i]; - - if (IS_STA_VALID(p_entry)) { - - if (IS_MCAST(p_entry->hwaddr)) - continue; - -#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) - if ((p_dm_odm->support_ic_type == ODM_RTL8812) || (p_dm_odm->support_ic_type == ODM_RTL8821)) { - if (p_entry->rssi_stat.undecorated_smoothed_pwdb < p_ra->ldpc_thres) { - p_ra->is_use_ldpc = true; - p_ra->is_lower_rts_rate = true; - if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A)) - set_ra_ldpc_8812(p_entry, true); - /* dbg_print("RSSI=%d, is_use_ldpc = true\n", p_hal_data->undecorated_smoothed_pwdb); */ - } else if (p_entry->rssi_stat.undecorated_smoothed_pwdb > (p_ra->ldpc_thres - 5)) { - p_ra->is_use_ldpc = false; - p_ra->is_lower_rts_rate = false; - if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A)) - set_ra_ldpc_8812(p_entry, false); - /* dbg_print("RSSI=%d, is_use_ldpc = false\n", p_hal_data->undecorated_smoothed_pwdb); */ - } - } -#endif - -#if RA_MASK_PHYDMLIZE_CE - ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_level); - - if ((p_entry->rssi_level != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { - - p_ra_table->force_update_ra_mask_count = 0; - /*ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pstat->hwaddr);*/ - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", - p_entry->rssi_level, ratr_state_new, p_entry->rssi_stat.undecorated_smoothed_pwdb)); - - p_entry->rssi_level = ratr_state_new; - rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); - /**/ - } -#else - if (true == odm_ra_state_check(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, false, &p_entry->rssi_level)) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_level)); - /* printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.undecorated_smoothed_pwdb, pstat->rssi_level); */ - rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE); - } else if (p_dm_odm->is_change_state) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training state, is_disable_power_training = %d\n", p_dm_odm->is_disable_power_training)); - rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE); - } -#endif - - } - } - -#endif -} - -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) -void -phydm_gen_ramask_h2c_AP( - void *p_dm_void, - struct rtl8192cd_priv *priv, - struct sta_info *p_entry, - u8 rssi_level -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - if (p_dm_odm->support_ic_type == ODM_RTL8812) { - -#if (RTL8812A_SUPPORT == 1) - UpdateHalRAMask8812(priv, p_entry, rssi_level); - /**/ -#endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - -#if (RTL8188E_SUPPORT == 1) -#ifdef TXREPORT - add_RATid(priv, p_entry); - /**/ -#endif -#endif - } else { - -#ifdef CONFIG_WLAN_HAL - GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, p_entry, rssi_level); -#endif - - } -} - -#endif - -void -odm_refresh_rate_adaptive_mask_apadsl( - void *p_dm_void -) -{ -#if (DM_ODM_SUPPORT_TYPE & ODM_AP) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - struct rtl8192cd_priv *priv = p_dm_odm->priv; - struct aid_obj *aidarray; - u32 i; - struct sta_info *p_entry; - u8 ratr_state_new; - - if (priv->up_time % 2) - return; - - for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { - p_entry = p_dm_odm->p_odm_sta_info[i]; - - if (IS_STA_VALID(p_entry)) { - -#if defined(UNIVERSAL_REPEATER) || defined(MBSSID) - aidarray = container_of(p_entry, struct aid_obj, station); - priv = aidarray->priv; -#endif - - if (!priv->pmib->dot11StationConfigEntry.autoRate) - continue; - -#if RA_MASK_PHYDMLIZE_AP - ratr_state_new = phydm_RA_level_decision(p_dm_odm, (u32)p_entry->rssi, p_entry->rssi_level); - - if ((p_entry->rssi_level != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { - - p_ra_table->force_update_ra_mask_count = 0; - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), p_entry->hwaddr); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", p_entry->rssi_level, ratr_state_new, p_entry->rssi)); - - p_entry->rssi_level = ratr_state_new; - phydm_gen_ramask_h2c_AP(p_dm_odm, priv, p_entry, p_entry->rssi_level); - } else { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); - /**/ - } - -#else - if (odm_ra_state_check(p_dm_odm, (s32)p_entry->rssi, false, &p_entry->rssi_level)) { - ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), p_entry->hwaddr); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", p_entry->rssi, p_entry->rssi_level)); - -#ifdef CONFIG_WLAN_HAL - if (IS_HAL_CHIP(priv)) { -#ifdef WDS - /*if(!(pstat->state & WIFI_WDS))*/ /*if WDS donot setting*/ -#endif - GET_HAL_INTERFACE(priv)->update_hal_ra_mask_handler(priv, p_entry, p_entry->rssi_level); - } else -#endif - -#ifdef CONFIG_RTL_8812_SUPPORT - if (GET_CHIP_VER(priv) == VERSION_8812E) - update_hal_ra_mask8812(priv, p_entry, 3); - else -#endif - { -#ifdef CONFIG_RTL_88E_SUPPORT - if (GET_CHIP_VER(priv) == VERSION_8188E) { -#ifdef TXREPORT - add_ra_tid(priv, p_entry); -#endif - } -#endif - - - } - } -#endif /*#ifdef RA_MASK_PHYDMLIZE*/ - - } - } -#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_AP)*/ -} - -void -odm_refresh_basic_rate_mask( - void *p_dm_void -) -{ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - static u8 stage = 0; - u8 cur_stage = 0; - OCTET_STRING os_rate_set; - PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(adapter); - u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M}; - - if (p_dm_odm->support_ic_type != ODM_RTL8812 && p_dm_odm->support_ic_type != ODM_RTL8821) - return; - - if (p_dm_odm->is_linked == false) /* unlink Default port information */ - cur_stage = 0; - else if (p_dm_odm->rssi_min < 40) /* link RSSI < 40% */ - cur_stage = 1; - else if (p_dm_odm->rssi_min > 45) /* link RSSI > 45% */ - cur_stage = 3; - else - cur_stage = 2; /* link 25% <= RSSI <= 30% */ - - if (cur_stage != stage) { - if (cur_stage == 1) { - FillOctetString(os_rate_set, rate_set, 5); - FilterSupportRate(p_mgnt_info->mBrates, &os_rate_set, false); - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set); - } else if (cur_stage == 3 && (stage == 1 || stage == 2)) - phydm_set_hw_reg_handler_interface(p_dm_odm, HW_VAR_BASIC_RATE, (u8 *)(&p_mgnt_info->mBrates)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + /*@MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/ + u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; + u8 new_rssi_lv = 0; + u8 i; + + PHYDM_DBG(dm, DBG_RA_MASK, + "curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n", + ratr_state, rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], + rssi_lv_t[3], rssi_lv_t[4], rssi_lv_t[5]); + + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + if (i >= (ratr_state)) + rssi_lv_t[i] += RA_FLOOR_UP_GAP; } - stage = cur_stage; -#endif + PHYDM_DBG(dm, DBG_RA_MASK, + "RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n", rssi, + rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], rssi_lv_t[3], + rssi_lv_t[4], rssi_lv_t[5]); + + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + if (rssi < rssi_lv_t[i]) { + new_rssi_lv = i; + break; + } + } + return new_rssi_lv; } -u8 -phydm_rate_order_compute( - void *p_dm_void, - u8 rate_idx -) +u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 rate_order = 0; - - if (rate_idx >= ODM_RATEVHTSS4MCS0) { + u8 rate_order = 0; + if (rate_idx >= ODM_RATEVHTSS4MCS0) rate_idx -= ODM_RATEVHTSS4MCS0; - /**/ - } else if (rate_idx >= ODM_RATEVHTSS3MCS0) { - + else if (rate_idx >= ODM_RATEVHTSS3MCS0) rate_idx -= ODM_RATEVHTSS3MCS0; - /**/ - } else if (rate_idx >= ODM_RATEVHTSS2MCS0) { - + else if (rate_idx >= ODM_RATEVHTSS2MCS0) rate_idx -= ODM_RATEVHTSS2MCS0; - /**/ - } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { - + else if (rate_idx >= ODM_RATEVHTSS1MCS0) rate_idx -= ODM_RATEVHTSS1MCS0; - /**/ - } else if (rate_idx >= ODM_RATEMCS24) { - + else if (rate_idx >= ODM_RATEMCS24) rate_idx -= ODM_RATEMCS24; - /**/ - } else if (rate_idx >= ODM_RATEMCS16) { - + else if (rate_idx >= ODM_RATEMCS16) rate_idx -= ODM_RATEMCS16; - /**/ - } else if (rate_idx >= ODM_RATEMCS8) { - + else if (rate_idx >= ODM_RATEMCS8) rate_idx -= ODM_RATEMCS8; - /**/ - } rate_order = rate_idx; return rate_order; +} +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +u8 phydm_rate2ss(void *dm_void, u8 rate_idx) +{ + u8 ret = 0xff; + u8 i, j; + u8 search_idx; + u32 ss_mapping_tab[4][3] = {{0x00000000, 0x003ff000, 0x000ff000}, + {0x00000000, 0xffc00000, 0x0ff00000}, + {0x000003ff, 0x0000000f, 0xf0000000}, + {0x000ffc00, 0x00000ff0, 0x00000000} }; + if (rate_idx < 32) { + search_idx = rate_idx; + j = 0; + } else if (rate_idx < 64) { + search_idx = rate_idx - 32; + j = 1; + } else { + search_idx = rate_idx - 64; + j = 2; + } + for (i = 0; i < 4; i++) + if (ss_mapping_tab[i][j] & BIT(search_idx)) + ret = i; + return ret; } -void -phydm_ra_common_info_update( - void *p_dm_void -) +u8 phydm_rate2plcp(void *dm_void, u8 rate_idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - u16 macid; - u8 rate_order_tmp; - u8 cnt = 0; + u8 rate2ss = 0; + u8 ltftime = 0; + u8 plcptime = 0xff; + + if (rate_idx < ODM_RATE6M) { + plcptime = 192; + /* @CCK PLCP = 192us (long preamble) */ + } else if (rate_idx < ODM_RATEMCS0) { + plcptime = 20; + /* @LegOFDM PLCP = 20us */ + } else { + if (rate_idx < ODM_RATEVHTSS1MCS0) + plcptime = 32; + /* @HT mode PLCP = 20us + 12us + 4us x Nss */ + else + plcptime = 36; + /* VHT mode PLCP = 20us + 16us + 4us x Nss */ + rate2ss = phydm_rate2ss(dm_void, rate_idx); + if (rate2ss != 0xff) + ltftime = (rate2ss + 1) * 4; + else + return 0xff; - p_ra_table->highest_client_tx_order = 0; - p_ra_table->power_tracking_flag = 1; + plcptime += ltftime; + } + return plcptime; +} + +u8 phydm_get_plcp(void *dm_void, u16 macid) +{ + u8 plcp_time = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; + + sta = dm->phydm_sta_info[macid]; + ra = &sta->ra_info; + plcp_time = phydm_rate2plcp(dm, ra->curr_tx_rate); + return plcp_time; +} +#endif - if (p_dm_odm->number_linked_client != 0) { - for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { +void phydm_ra_common_info_update(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; + u16 macid; + u8 rate_order_tmp; + u8 rate_idx = 0; + u8 cnt = 0; + + ra_tab->highest_client_tx_order = 0; + ra_tab->power_tracking_flag = 1; + + if (!dm->number_linked_client) + return; - rate_order_tmp = phydm_rate_order_compute(p_dm_odm, ((p_ra_table->link_tx_rate[macid]) & 0x7f)); + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + sta = dm->phydm_sta_info[macid]; - if (rate_order_tmp >= (p_ra_table->highest_client_tx_order)) { - p_ra_table->highest_client_tx_order = rate_order_tmp; - p_ra_table->highest_client_tx_rate_order = macid; - } + if (!is_sta_active(sta)) + continue; - cnt++; + rate_idx = sta->ra_info.curr_tx_rate & 0x7f; + rate_order_tmp = phydm_rate_order_compute(dm, rate_idx); - if (cnt == p_dm_odm->number_linked_client) - break; + if (rate_order_tmp >= ra_tab->highest_client_tx_order) { + ra_tab->highest_client_tx_order = rate_order_tmp; + ra_tab->highest_client_tx_rate_order = macid; } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("MACID[%d], Highest Tx order Update for power traking: %d\n", (p_ra_table->highest_client_tx_rate_order), (p_ra_table->highest_client_tx_order))); + + cnt++; + + if (cnt == dm->number_linked_client) + break; } + PHYDM_DBG(dm, DBG_RA, + "MACID[%d], Highest Tx order Update for power traking: %d\n", + ra_tab->highest_client_tx_rate_order, + ra_tab->highest_client_tx_order); } -void -phydm_ra_info_watchdog( - void *p_dm_void -) +void phydm_ra_info_watchdog(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - phydm_ra_common_info_update(p_dm_odm); - phydm_ra_dynamic_retry_limit(p_dm_odm); - phydm_ra_dynamic_retry_count(p_dm_odm); - odm_refresh_rate_adaptive_mask(p_dm_odm); - odm_refresh_basic_rate_mask(p_dm_odm); + phydm_ra_common_info_update(dm); + phydm_ra_dynamic_retry_count(dm); + phydm_ra_mask_watchdog(dm); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + odm_refresh_basic_rate_mask(dm); +#endif } -void -phydm_ra_info_init( - void *p_dm_void -) +void phydm_ra_info_init(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; - p_ra_table->highest_client_tx_rate_order = 0; - p_ra_table->highest_client_tx_order = 0; - p_ra_table->RA_threshold_offset = 0; - p_ra_table->RA_offset_direction = 0; + ra_tab->highest_client_tx_rate_order = 0; + ra_tab->highest_client_tx_order = 0; + ra_tab->ra_th_ofst = 0; + ra_tab->ra_ofst_direc = 0; -#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - phydm_ra_dynamic_retry_limit_init(p_dm_odm); -#endif +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + u32 ret_value; -#if (defined(CONFIG_RA_DYNAMIC_RATE_ID)) - phydm_ra_dynamic_rate_id_init(p_dm_odm); -#endif -#if (defined(CONFIG_RA_DBG_CMD)) - odm_ra_para_adjust_init(p_dm_odm); + ret_value = odm_get_bb_reg(dm, R_0x4c8, MASKBYTE2); + odm_set_bb_reg(dm, R_0x4cc, MASKBYTE3, (ret_value - 1)); + } #endif -} + #if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + phydm_ra_dynamic_retry_limit_init(dm); + #endif + #if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/ + phydm_ra_dynamic_rate_id_init(dm); + #endif -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) -u8 -odm_find_rts_rate( - void *p_dm_void, - u8 tx_rate, - boolean is_erp_protect -) + phydm_rate_adaptive_mask_init(dm); +} + +u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 rts_ini_rate = ODM_RATE6M; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rts_ini_rate = ODM_RATE6M; - if (is_erp_protect) /* use CCK rate as RTS*/ + if (is_erp_protect) { /* use CCK rate as RTS*/ rts_ini_rate = ODM_RATE1M; - else { + } else { switch (tx_rate) { + case ODM_RATEVHTSS4MCS9: + case ODM_RATEVHTSS4MCS8: + case ODM_RATEVHTSS4MCS7: + case ODM_RATEVHTSS4MCS6: + case ODM_RATEVHTSS4MCS5: + case ODM_RATEVHTSS4MCS4: + case ODM_RATEVHTSS4MCS3: case ODM_RATEVHTSS3MCS9: case ODM_RATEVHTSS3MCS8: case ODM_RATEVHTSS3MCS7: @@ -2657,6 +1803,16 @@ odm_find_rts_rate( case ODM_RATEVHTSS1MCS5: case ODM_RATEVHTSS1MCS4: case ODM_RATEVHTSS1MCS3: + case ODM_RATEMCS31: + case ODM_RATEMCS30: + case ODM_RATEMCS29: + case ODM_RATEMCS28: + case ODM_RATEMCS27: + case ODM_RATEMCS23: + case ODM_RATEMCS22: + case ODM_RATEMCS21: + case ODM_RATEMCS20: + case ODM_RATEMCS19: case ODM_RATEMCS15: case ODM_RATEMCS14: case ODM_RATEMCS13: @@ -2673,12 +1829,18 @@ odm_find_rts_rate( case ODM_RATE24M: rts_ini_rate = ODM_RATE24M; break; + case ODM_RATEVHTSS4MCS2: + case ODM_RATEVHTSS4MCS1: case ODM_RATEVHTSS3MCS2: case ODM_RATEVHTSS3MCS1: case ODM_RATEVHTSS2MCS2: case ODM_RATEVHTSS2MCS1: case ODM_RATEVHTSS1MCS2: case ODM_RATEVHTSS1MCS1: + case ODM_RATEMCS26: + case ODM_RATEMCS25: + case ODM_RATEMCS18: + case ODM_RATEMCS17: case ODM_RATEMCS10: case ODM_RATEMCS9: case ODM_RATEMCS2: @@ -2687,9 +1849,12 @@ odm_find_rts_rate( case ODM_RATE12M: rts_ini_rate = ODM_RATE12M; break; + case ODM_RATEVHTSS4MCS0: case ODM_RATEVHTSS3MCS0: case ODM_RATEVHTSS2MCS0: case ODM_RATEVHTSS1MCS0: + case ODM_RATEMCS24: + case ODM_RATEMCS16: case ODM_RATEMCS8: case ODM_RATEMCS0: case ODM_RATE9M: @@ -2708,742 +1873,262 @@ odm_find_rts_rate( } } - if (*p_dm_odm->p_band_type == 1) { + if (*dm->band_type == ODM_BAND_5G) { if (rts_ini_rate < ODM_RATE6M) rts_ini_rate = ODM_RATE6M; } return rts_ini_rate; - } -void -odm_set_ra_dm_arfb_by_noisy( - struct PHY_DM_STRUCT *p_dm_odm -) -{ -#if 0 - - /*dbg_print("DM_ARFB ====>\n");*/ - if (p_dm_odm->is_noisy_state) { - odm_write_4byte(p_dm_odm, 0x430, 0x00000000); - odm_write_4byte(p_dm_odm, 0x434, 0x05040200); - /*dbg_print("DM_ARFB ====> Noisy state\n");*/ - } else { - odm_write_4byte(p_dm_odm, 0x430, 0x02010000); - odm_write_4byte(p_dm_odm, 0x434, 0x07050403); - /*dbg_print("DM_ARFB ====> Clean state\n");*/ - } -#endif -} +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -odm_update_noisy_state( - void *p_dm_void, - boolean is_noisy_state_from_c2h -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - -/* JJ ADD 20161014 */ - /*dbg_print("Get C2H Command! NoisyState=0x%x\n ", is_noisy_state_from_c2h);*/ - if (p_dm_odm->support_ic_type == ODM_RTL8821 || p_dm_odm->support_ic_type == ODM_RTL8812 || - p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) - p_dm_odm->is_noisy_state = is_noisy_state_from_c2h; - odm_set_ra_dm_arfb_by_noisy(p_dm_odm); -}; - -void -phydm_update_pwr_track( - void *p_dm_void, - u8 rate -) +void odm_refresh_basic_rate_mask( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 path_idx = 0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Pwr Track Get rate=0x%x\n", rate)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + static u8 stage = 0; + u8 cur_stage = 0; + OCTET_STRING os_rate_set; + PMGNT_INFO mgnt_info = GetDefaultMgntInfo(((PADAPTER)adapter)); + u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M}; + + if (dm->support_ic_type != ODM_RTL8812 && dm->support_ic_type != ODM_RTL8821) + return; - p_dm_odm->tx_rate = rate; + if (dm->is_linked == false) /* unlink Default port information */ + cur_stage = 0; + else if (dm->rssi_min < 40) /* @link RSSI < 40% */ + cur_stage = 1; + else if (dm->rssi_min > 45) /* @link RSSI > 45% */ + cur_stage = 3; + else + cur_stage = 2; /* @link 25% <= RSSI <= 30% */ -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#if DEV_BUS_TYPE == RT_PCI_INTERFACE -#if USE_WORKITEM - odm_schedule_work_item(&p_dm_odm->ra_rpt_workitem); -#else - if (p_dm_odm->support_ic_type == ODM_RTL8821) { -#if (RTL8821A_SUPPORT == 1) - odm_tx_pwr_track_set_pwr8821a(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); -#endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - for (path_idx = ODM_RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) { -#if (RTL8812A_SUPPORT == 1) - odm_tx_pwr_track_set_pwr8812a(p_dm_odm, MIX_MODE, path_idx, 0); -#endif - } - } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { -#if (RTL8723B_SUPPORT == 1) - odm_tx_pwr_track_set_pwr_8723b(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); -#endif - } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - for (path_idx = ODM_RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) { -#if (RTL8192E_SUPPORT == 1) - odm_tx_pwr_track_set_pwr92_e(p_dm_odm, MIX_MODE, path_idx, 0); -#endif - } - } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { -#if (RTL8188E_SUPPORT == 1) - odm_tx_pwr_track_set_pwr88_e(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); -#endif + if (cur_stage != stage) { + if (cur_stage == 1) { + FillOctetString(os_rate_set, rate_set, 5); + FilterSupportRate(mgnt_info->mBrates, &os_rate_set, false); + phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set); + } else if (cur_stage == 3 && (stage == 1 || stage == 2)) + phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)(&mgnt_info->mBrates)); } -#endif -#else - odm_schedule_work_item(&p_dm_odm->ra_rpt_workitem); -#endif -#endif + stage = cur_stage; } -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#endif -s32 -phydm_find_minimum_rssi( - struct PHY_DM_STRUCT *p_dm_odm, - struct _ADAPTER *p_adapter, - OUT boolean *p_is_link_temp +#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/ -) +void phydm_retry_limit_table_bound( + void *dm_void, + u8 *retry_limit, + u8 offset) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - PMGNT_INFO p_mgnt_info = &(p_adapter->MgntInfo); - boolean act_as_ap = ACTING_AS_AP(p_adapter); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; - /* 1.Determine the minimum RSSI */ - if ((!p_mgnt_info->bMediaConnect) || - (act_as_ap && (p_hal_data->EntryMinUndecoratedSmoothedPWDB == 0))) {/* We should check AP mode and Entry info.into consideration, revised by Roger, 2013.10.18*/ - - p_hal_data->MinUndecoratedPWDBForDM = 0; - *p_is_link_temp = false; + if (*retry_limit > offset) { + *retry_limit -= offset; + if (*retry_limit < ra_tab->retrylimit_low) + *retry_limit = ra_tab->retrylimit_low; + else if (*retry_limit > ra_tab->retrylimit_high) + *retry_limit = ra_tab->retrylimit_high; } else - *p_is_link_temp = true; - - - if (p_mgnt_info->bMediaConnect) { /* Default port*/ - - if (act_as_ap || p_mgnt_info->mIbss) { - p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->EntryMinUndecoratedSmoothedPWDB; - /**/ - } else { - p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->UndecoratedSmoothedPWDB; - /**/ - } - } else { /* associated entry pwdb*/ - p_hal_data->MinUndecoratedPWDBForDM = p_hal_data->EntryMinUndecoratedSmoothedPWDB; - /**/ - } - - return p_hal_data->MinUndecoratedPWDBForDM; + *retry_limit = ra_tab->retrylimit_low; } -void -odm_update_init_rate_work_item_callback( - void *p_context -) +void phydm_reset_retry_limit_table( + void *dm_void) { - struct _ADAPTER *adapter = (struct _ADAPTER *)p_context; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - u8 p = 0; - - if (p_dm_odm->support_ic_type == ODM_RTL8821) { - odm_tx_pwr_track_set_pwr8821a(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); - /**/ - } else if (p_dm_odm->support_ic_type == ODM_RTL8812) { - for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) { /*DOn't know how to include &c*/ - - odm_tx_pwr_track_set_pwr8812a(p_dm_odm, MIX_MODE, p, 0); - /**/ - } - } else if (p_dm_odm->support_ic_type == ODM_RTL8723B) { - odm_tx_pwr_track_set_pwr_8723b(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); - /**/ - } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) { /*DOn't know how to include &c*/ - odm_tx_pwr_track_set_pwr92_e(p_dm_odm, MIX_MODE, p, 0); - /**/ - } - } else if (p_dm_odm->support_ic_type == ODM_RTL8188E) { - odm_tx_pwr_track_set_pwr88_e(p_dm_odm, MIX_MODE, ODM_RF_PATH_A, 0); - /**/ - } -} + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + u8 i; -void -odm_rssi_dump_to_register( - void *p_dm_void -) -{ - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - - if (p_dm_odm->support_ic_type == ODM_RTL8812) { - PlatformEFIOWrite1Byte(adapter, REG_A_RSSI_DUMP_JAGUAR, adapter->RxStats.RxRSSIPercentage[0]); - PlatformEFIOWrite1Byte(adapter, REG_B_RSSI_DUMP_JAGUAR, adapter->RxStats.RxRSSIPercentage[1]); - - /* Rx EVM*/ - PlatformEFIOWrite1Byte(adapter, REG_S1_RXEVM_DUMP_JAGUAR, adapter->RxStats.RxEVMdbm[0]); - PlatformEFIOWrite1Byte(adapter, REG_S2_RXEVM_DUMP_JAGUAR, adapter->RxStats.RxEVMdbm[1]); - - /* Rx SNR*/ - PlatformEFIOWrite1Byte(adapter, REG_A_RX_SNR_DUMP_JAGUAR, (u8)(adapter->RxStats.RxSNRdB[0])); - PlatformEFIOWrite1Byte(adapter, REG_B_RX_SNR_DUMP_JAGUAR, (u8)(adapter->RxStats.RxSNRdB[1])); - - /* Rx Cfo_Short*/ - PlatformEFIOWrite2Byte(adapter, REG_A_CFO_SHORT_DUMP_JAGUAR, adapter->RxStats.RxCfoShort[0]); - PlatformEFIOWrite2Byte(adapter, REG_B_CFO_SHORT_DUMP_JAGUAR, adapter->RxStats.RxCfoShort[1]); - - /* Rx Cfo_Tail*/ - PlatformEFIOWrite2Byte(adapter, REG_A_CFO_LONG_DUMP_JAGUAR, adapter->RxStats.RxCfoTail[0]); - PlatformEFIOWrite2Byte(adapter, REG_B_CFO_LONG_DUMP_JAGUAR, adapter->RxStats.RxCfoTail[1]); - } else if (p_dm_odm->support_ic_type == ODM_RTL8192E) { - PlatformEFIOWrite1Byte(adapter, REG_A_RSSI_DUMP_92E, adapter->RxStats.RxRSSIPercentage[0]); - PlatformEFIOWrite1Byte(adapter, REG_B_RSSI_DUMP_92E, adapter->RxStats.RxRSSIPercentage[1]); - /* Rx EVM*/ - PlatformEFIOWrite1Byte(adapter, REG_S1_RXEVM_DUMP_92E, adapter->RxStats.RxEVMdbm[0]); - PlatformEFIOWrite1Byte(adapter, REG_S2_RXEVM_DUMP_92E, adapter->RxStats.RxEVMdbm[1]); - /* Rx SNR*/ - PlatformEFIOWrite1Byte(adapter, REG_A_RX_SNR_DUMP_92E, (u8)(adapter->RxStats.RxSNRdB[0])); - PlatformEFIOWrite1Byte(adapter, REG_B_RX_SNR_DUMP_92E, (u8)(adapter->RxStats.RxSNRdB[1])); - /* Rx Cfo_Short*/ - PlatformEFIOWrite2Byte(adapter, REG_A_CFO_SHORT_DUMP_92E, adapter->RxStats.RxCfoShort[0]); - PlatformEFIOWrite2Byte(adapter, REG_B_CFO_SHORT_DUMP_92E, adapter->RxStats.RxCfoShort[1]); - /* Rx Cfo_Tail*/ - PlatformEFIOWrite2Byte(adapter, REG_A_CFO_LONG_DUMP_92E, adapter->RxStats.RxCfoTail[0]); - PlatformEFIOWrite2Byte(adapter, REG_B_CFO_LONG_DUMP_92E, adapter->RxStats.RxCfoTail[1]); + u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = { + 1, 1, 2, 4, /*@CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 2, 4, 6, 8, 12, 18, 20, 22, /*@20M HT-1SS*/ + 2, 4, 6, 8, 12, 18, 20, 22 /*@20M HT-2SS*/ + }; + u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = { + 1, 1, 2, 4, /*@CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 4, 8, 12, 16, 24, 32, 32, 32, /*@40M HT-1SS*/ + 4, 8, 12, 16, 24, 32, 32, 32 /*@40M HT-2SS*/ + }; + + memcpy(&ra_t->per_rate_retrylimit_20M[0], + &per_rate_retrylimit_table_20M[0], ODM_NUM_RATE_IDX); + memcpy(&ra_t->per_rate_retrylimit_40M[0], + &per_rate_retrylimit_table_40M[0], ODM_NUM_RATE_IDX); + + for (i = 0; i < ODM_NUM_RATE_IDX; i++) { + phydm_retry_limit_table_bound(dm, + &ra_t->per_rate_retrylimit_20M[i], + 0); + phydm_retry_limit_table_bound(dm, + &ra_t->per_rate_retrylimit_40M[i], + 0); } } -void -odm_refresh_ldpc_rts_mp( - struct _ADAPTER *p_adapter, - struct PHY_DM_STRUCT *p_dm_odm, - u8 m_mac_id, - u8 iot_peer, - s32 undecorated_smoothed_pwdb -) +void phydm_ra_dynamic_retry_limit_init( + void *dm_void) { - boolean is_ctl_ldpc = false; - struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive; - - if (p_dm_odm->support_ic_type != ODM_RTL8821 && p_dm_odm->support_ic_type != ODM_RTL8812) - return; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; - if ((p_dm_odm->support_ic_type == ODM_RTL8821) && (p_dm_odm->cut_version == ODM_CUT_A)) - is_ctl_ldpc = true; - else if (p_dm_odm->support_ic_type == ODM_RTL8812 && - iot_peer == HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP) - is_ctl_ldpc = true; - - if (is_ctl_ldpc) { - if (undecorated_smoothed_pwdb < (p_ra->ldpc_thres - 5)) - MgntSet_TX_LDPC(p_adapter, m_mac_id, true); - else if (undecorated_smoothed_pwdb > p_ra->ldpc_thres) - MgntSet_TX_LDPC(p_adapter, m_mac_id, false); - } + ra_tab->retry_descend_num = RA_RETRY_DESCEND_NUM; + ra_tab->retrylimit_low = RA_RETRY_LIMIT_LOW; + ra_tab->retrylimit_high = RA_RETRY_LIMIT_HIGH; - if (undecorated_smoothed_pwdb < (p_ra->rts_thres - 5)) - p_ra->is_lower_rts_rate = true; - else if (undecorated_smoothed_pwdb > p_ra->rts_thres) - p_ra->is_lower_rts_rate = false; + phydm_reset_retry_limit_table(dm); } -#if 0 -void -odm_dynamic_arfb_select( - void *p_dm_void, - u8 rate, - boolean collision_state -) +void phydm_ra_dynamic_retry_limit( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; - - if (p_dm_odm->support_ic_type != ODM_RTL8192E) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 i, retry_offset; + u32 ma_rx_tp; + + if (dm->pre_number_active_client == dm->number_active_client) { + PHYDM_DBG(dm, DBG_RA, + "pre_number_active_client == number_active_client\n"); return; - if (collision_state == p_ra_table->PT_collision_pre) - return; - - if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS12) { - if (collision_state == 1) { - if (rate == DESC_RATEMCS12) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060501); - } else if (rate == DESC_RATEMCS11) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07070605); - } else if (rate == DESC_RATEMCS10) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08080706); - } else if (rate == DESC_RATEMCS9) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08080707); - } else { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x0); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09090808); - } - } else { /* collision_state == 0*/ - if (rate == DESC_RATEMCS12) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x05010000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080706); - } else if (rate == DESC_RATEMCS11) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x06050000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080807); - } else if (rate == DESC_RATEMCS10) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x07060000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0a090908); - } else if (rate == DESC_RATEMCS9) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x07070000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0a090808); - } else { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x08080000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x0b0a0909); - } - } - } else { /* MCS13~MCS15, 1SS, G-mode*/ - if (collision_state == 1) { - if (rate == DESC_RATEMCS15) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x05040302); - } else if (rate == DESC_RATEMCS14) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x06050302); - } else if (rate == DESC_RATEMCS13) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060502); - } else { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x00000000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x06050402); - } - } else { /* collision_state == 0 */ - if (rate == DESC_RATEMCS15) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x03020000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x07060504); - } else if (rate == DESC_RATEMCS14) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x03020000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08070605); - } else if (rate == DESC_RATEMCS13) { - - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x05020000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x09080706); - } else { + } else { + if (dm->number_active_client == 1) { + phydm_reset_retry_limit_table(dm); + PHYDM_DBG(dm, DBG_RA, + "one client only->reset to default value\n"); + } else { + retry_offset = dm->number_active_client * ra_tab->retry_descend_num; - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E, 0x04020000); - odm_write_4byte(p_dm_odm, REG_DARFRC_8192E+4, 0x08070605); + for (i = 0; i < ODM_NUM_RATE_IDX; i++) { + phydm_retry_limit_table_bound(dm, + &ra_tab->per_rate_retrylimit_20M[i], + retry_offset); + phydm_retry_limit_table_bound(dm, + &ra_tab->per_rate_retrylimit_40M[i], + retry_offset); } } } - p_ra_table->PT_collision_pre = collision_state; } #endif -void -odm_rate_adaptive_state_ap_init( - void *PADAPTER_VOID, - struct sta_info *p_entry -) -{ - struct _ADAPTER *adapter = (struct _ADAPTER *)PADAPTER_VOID; - p_entry->Ratr_State = DM_RATR_STA_INIT; -} -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ - -static void -find_minimum_rssi( - struct _ADAPTER *p_adapter -) -{ - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); - struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->odmpriv); - - /*Determine the minimum RSSI*/ - - if ((p_dm_odm->is_linked != _TRUE) && - (p_hal_data->entry_min_undecorated_smoothed_pwdb == 0)) { - p_hal_data->min_undecorated_pwdb_for_dm = 0; - /*ODM_RT_TRACE(p_dm_odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any\n"));*/ - } else - p_hal_data->min_undecorated_pwdb_for_dm = p_hal_data->entry_min_undecorated_smoothed_pwdb; - - /*DBG_8192C("%s=>min_undecorated_pwdb_for_dm(%d)\n",__FUNCTION__,pdmpriv->min_undecorated_pwdb_for_dm);*/ - /*ODM_RT_TRACE(p_dm_odm,COMP_DIG, DBG_LOUD, ("min_undecorated_pwdb_for_dm =%d\n",p_hal_data->min_undecorated_pwdb_for_dm));*/ -} - -u64 -phydm_get_rate_bitmap_ex( - void *p_dm_void, - u32 macid, - u64 ra_mask, - u8 rssi_level, - u64 *dm_ra_mask, - u8 *dm_rte_id -) +#if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/ +void phydm_ra_dynamic_rate_id_on_assoc( + void *dm_void, + u8 wireless_mode, + u8 init_rate_id) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct sta_info *p_entry; - u64 rate_bitmap = 0; - u8 wireless_mode; - - p_entry = p_dm_odm->p_odm_sta_info[macid]; - if (!IS_STA_VALID(p_entry)) - return ra_mask; - wireless_mode = p_entry->wireless_mode; - switch (wireless_mode) { - case ODM_WM_B: - if (ra_mask & 0x000000000000000c) /* 11M or 5.5M enable */ - rate_bitmap = 0x000000000000000d; - else - rate_bitmap = 0x000000000000000f; - break; - - case (ODM_WM_G): - case (ODM_WM_A): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0000000000000f00; - else - rate_bitmap = 0x0000000000000ff0; - break; - - case (ODM_WM_B|ODM_WM_G): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0000000000000f00; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x0000000000000ff0; - else - rate_bitmap = 0x0000000000000ff5; - break; - - case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): - case (ODM_WM_B|ODM_WM_N24G): - case (ODM_WM_G|ODM_WM_N24G): - case (ODM_WM_A|ODM_WM_N5G): - { - if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x00000000000f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x00000000000ff000; - else { - if (*(p_dm_odm->p_band_width) == ODM_BW40M) - rate_bitmap = 0x00000000000ff015; - else - rate_bitmap = 0x00000000000ff005; - } - } else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x000000000f8f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x000000000f8ff000; - else { - if (*(p_dm_odm->p_band_width) == ODM_BW40M) - rate_bitmap = 0x000000000f8ff015; - else - rate_bitmap = 0x000000000f8ff005; - } - } else { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0000000f0f0f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x0000000fcfcfe000; - else { - if (*(p_dm_odm->p_band_width) == ODM_BW40M) - rate_bitmap = 0x0000000ffffff015; - else - rate_bitmap = 0x0000000ffffff005; - } - } - } - break; - - case (ODM_WM_AC|ODM_WM_G): - if (rssi_level == 1) - rate_bitmap = 0x00000000fc3f0000; - else if (rssi_level == 2) - rate_bitmap = 0x00000000fffff000; - else - rate_bitmap = 0x00000000ffffffff; - break; - - case (ODM_WM_AC|ODM_WM_A): - - if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0x00000000003f8000; - else if (rssi_level == 2) - rate_bitmap = 0x00000000003fe000; - else - rate_bitmap = 0x00000000003ff010; - } else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0x00000000fe3f8000; /* VHT 2SS MCS3~9 */ - else if (rssi_level == 2) - rate_bitmap = 0x00000000fffff000; /* VHT 2SS MCS0~9 */ - else - rate_bitmap = 0x00000000fffff010; /* All */ - } else { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0x000003f8fe3f8000ULL; /* VHT 3SS MCS3~9 */ - else if (rssi_level == 2) - rate_bitmap = 0x000003fffffff000ULL; /* VHT3SS MCS0~9 */ - else - rate_bitmap = 0x000003fffffff010ULL; /* All */ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_RA, + "[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", + dm->rf_type, wireless_mode, init_rate_id); + + if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) { + if ((dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) && + (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G))) { + PHYDM_DBG(dm, DBG_RA, + "[ON ASSOC] set N-2SS ARFR5 table\n"); + odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + } else if ((dm->support_ic_type & (ODM_RTL8812)) && + (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY))) { + PHYDM_DBG(dm, DBG_RA, + "[ON ASSOC] set AC-2SS ARFR0 table\n"); + odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/ + odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/ } - break; - - default: - if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) - rate_bitmap = 0x00000000000fffff; - else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) - rate_bitmap = 0x000000000fffffff; - else - rate_bitmap = 0x0000003fffffffffULL; - break; - } - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%016llx\n", rssi_level, wireless_mode, rate_bitmap)); - - return ra_mask & rate_bitmap; } - -u32 -odm_get_rate_bitmap( - void *p_dm_void, - u32 macid, - u32 ra_mask, - u8 rssi_level -) +void phydm_ra_dynamic_rate_id_init( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct sta_info *p_entry; - u32 rate_bitmap = 0; - u8 wireless_mode; - /* u8 wireless_mode =*(p_dm_odm->p_wireless_mode); */ - - - p_entry = p_dm_odm->p_odm_sta_info[macid]; - if (!IS_STA_VALID(p_entry)) - return ra_mask; - - wireless_mode = p_entry->wireless_mode; - - switch (wireless_mode) { - case ODM_WM_B: - if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ - rate_bitmap = 0x0000000d; - else - rate_bitmap = 0x0000000f; - break; - - case (ODM_WM_G): - case (ODM_WM_A): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x00000f00; - else - rate_bitmap = 0x00000ff0; - break; + struct dm_struct *dm = (struct dm_struct *)dm_void; - case (ODM_WM_B|ODM_WM_G): - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x00000f00; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x00000ff0; - else - rate_bitmap = 0x00000ff5; - break; - - case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): - case (ODM_WM_B|ODM_WM_N24G): - case (ODM_WM_G|ODM_WM_N24G): - case (ODM_WM_A|ODM_WM_N5G): - { - if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x000f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x000ff000; - else { - if (*(p_dm_odm->p_band_width) == ODM_BW40M) - rate_bitmap = 0x000ff015; - else - rate_bitmap = 0x000ff005; - } - } else { - if (rssi_level == DM_RATR_STA_HIGH) - rate_bitmap = 0x0f8f0000; - else if (rssi_level == DM_RATR_STA_MIDDLE) - rate_bitmap = 0x0f8ff000; - else { - if (*(p_dm_odm->p_band_width) == ODM_BW40M) - rate_bitmap = 0x0f8ff015; - else - rate_bitmap = 0x0f8ff005; - } - } - } - break; - - case (ODM_WM_AC|ODM_WM_G): - if (rssi_level == 1) - rate_bitmap = 0xfc3f0000; - else if (rssi_level == 2) - rate_bitmap = 0xfffff000; - else - rate_bitmap = 0xffffffff; - break; - - case (ODM_WM_AC|ODM_WM_A): - - if (p_dm_odm->rf_type == RF_1T1R) { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0x003f8000; - else if (rssi_level == 2) - rate_bitmap = 0x003ff000; - else - rate_bitmap = 0x003ff010; - } else { - if (rssi_level == 1) /* add by Gary for ac-series */ - rate_bitmap = 0xfe3f8000; /* VHT 2SS MCS3~9 */ - else if (rssi_level == 2) - rate_bitmap = 0xfffff000; /* VHT 2SS MCS0~9 */ - else - rate_bitmap = 0xfffff010; /* All */ - } - break; - - default: - if (p_dm_odm->rf_type == RF_1T2R) - rate_bitmap = 0x000fffff; - else - rate_bitmap = 0x0fffffff; - break; + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) { + odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/ + odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/ } - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%08x\n", __func__, rssi_level, wireless_mode, rate_bitmap)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%08x\n", rssi_level, wireless_mode, rate_bitmap)); - - return ra_mask & rate_bitmap; - } -#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ - -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - - -#endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ - - -/* RA_MASK_PHYDMLIZE, will delete it later*/ - -#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN) - -boolean -odm_ra_state_check( - void *p_dm_void, - s32 RSSI, - boolean is_force_update, - u8 *p_ra_tr_state -) +void phydm_update_rate_id( + void *dm_void, + u8 rate, + u8 platform_macid) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive; - const u8 go_up_gap = 5; - u8 high_rssi_thresh_for_ra = p_ra->high_rssi_thresh; - u8 low_rssi_thresh_for_ra = p_ra->low_rssi_thresh; - u8 ratr_state; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", RSSI, *p_ra_tr_state)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Ori RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", high_rssi_thresh_for_ra, low_rssi_thresh_for_ra)); - /* threshold Adjustment:*/ - /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough.*/ - /* Here go_up_gap is added to solve the boundary's level alternation issue.*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - u8 ultra_low_rssi_thresh_for_ra = p_ra->ultra_low_rssi_thresh; - - if (p_dm_odm->support_ic_type == ODM_RTL8881A) - low_rssi_thresh_for_ra = 30; /* for LDPC / BCC switch*/ -#endif +#if 0 - switch (*p_ra_tr_state) { - case DM_RATR_STA_INIT: - case DM_RATR_STA_HIGH: - break; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 current_tx_ss; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 wireless_mode; + u8 phydm_macid; + struct sta_info *entry; + struct cmn_sta_info *sta; - case DM_RATR_STA_MIDDLE: - high_rssi_thresh_for_ra += go_up_gap; - break; +#if 0 + if (rate_idx >= ODM_RATEVHTSS2MCS0) { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT2SS-MCS%d ))\n", + platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0)); + /*@dummy for SD4 check patch*/ + } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT1SS-MCS%d ))\n", + platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0)); + /*@dummy for SD4 check patch*/ + } else if (rate_idx >= ODM_RATEMCS0) { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n", + platform_macid, (rate_idx - ODM_RATEMCS0)); + /*@dummy for SD4 check patch*/ + } else { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n", + platform_macid, rate_idx); + /*@dummy for SD4 check patch*/ + } +#endif - case DM_RATR_STA_LOW: - high_rssi_thresh_for_ra += go_up_gap; - low_rssi_thresh_for_ra += go_up_gap; - break; + phydm_macid = dm->phydm_macid_table[platform_macid]; + entry = dm->odm_sta_info[phydm_macid]; + sta = dm->phydm_sta_info[phydm_macid]; -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - case DM_RATR_STA_ULTRA_LOW: - high_rssi_thresh_for_ra += go_up_gap; - low_rssi_thresh_for_ra += go_up_gap; - ultra_low_rssi_thresh_for_ra += go_up_gap; - break; -#endif + if (is_sta_active(sta)) { + wireless_mode = entry->wireless_mode; - default: - ODM_RT_ASSERT(p_dm_odm, false, ("wrong rssi level setting %d !", *p_ra_tr_state)); - break; - } + if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) { + if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/ + if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*@2SS mode*/ - /* Decide ratr_state by RSSI.*/ - if (RSSI > high_rssi_thresh_for_ra) - ratr_state = DM_RATR_STA_HIGH; - else if (RSSI > low_rssi_thresh_for_ra) - ratr_state = DM_RATR_STA_MIDDLE; + sta->ra_info.rate_id = ARFR_5_RATE_ID; + PHYDM_DBG(dm, DBG_RA, "ARFR_5\n"); + } + } else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*@AC mode*/ + if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*@2SS mode*/ -#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) - else if (RSSI > ultra_low_rssi_thresh_for_ra) - ratr_state = DM_RATR_STA_LOW; - else - ratr_state = DM_RATR_STA_ULTRA_LOW; -#else - else - ratr_state = DM_RATR_STA_LOW; -#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Mod RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", high_rssi_thresh_for_ra, low_rssi_thresh_for_ra)); - /*printk("==>%s,ratr_state:0x%02x,RSSI:%d\n",__FUNCTION__,ratr_state,RSSI);*/ + sta->ra_info.rate_id = ARFR_0_RATE_ID; + PHYDM_DBG(dm, DBG_RA, "ARFR_0\n"); + } + } else + sta->ra_info.rate_id = ARFR_0_RATE_ID; - if (*p_ra_tr_state != ratr_state || is_force_update) { - ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[RSSI Level Update] %d->%d\n", *p_ra_tr_state, ratr_state)); - *p_ra_tr_state = ratr_state; - return true; + PHYDM_DBG(dm, DBG_RA, "UPdate_RateID[%d]: (( 0x%x ))\n", + platform_macid, sta->ra_info.rate_id); + } } - - return false; +#endif } #endif diff --git a/hal/phydm/phydm_rainfo.h b/hal/phydm/phydm_rainfo.h index 1a0df73..a840880 100644 --- a/hal/phydm/phydm_rainfo.h +++ b/hal/phydm/phydm_rainfo.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,117 +8,71 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -#ifndef __PHYDMRAINFO_H__ -#define __PHYDMRAINFO_H__ +#ifndef __PHYDMRAINFO_H__ +#define __PHYDMRAINFO_H__ -/*#define RAINFO_VERSION "2.0" //2014.11.04*/ -/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/ -/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/ -/*#define RAINFO_VERSION "3.3" 2015.07.29 YuChen*/ -/*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/ -/*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */ -/*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */ -/*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */ -#define RAINFO_VERSION "4.3" /*2016.07.11 Dino, Fix RA hang in CCK 1M problem */ +#define RAINFO_VERSION "8.0" #define FORCED_UPDATE_RAMASK_PERIOD 5 -#define H2C_0X42_LENGTH 5 -#define H2C_MAX_LENGTH 7 +#define H2C_MAX_LENGTH 7 #define RA_FLOOR_UP_GAP 3 #define RA_FLOOR_TABLE_SIZE 7 -#define ACTIVE_TP_THRESHOLD 150 +#define ACTIVE_TP_THRESHOLD 1 #define RA_RETRY_DESCEND_NUM 2 #define RA_RETRY_LIMIT_LOW 4 #define RA_RETRY_LIMIT_HIGH 32 -#define RAINFO_BE_RX_STATE BIT(0) /* 1:RX */ /* ULDL */ -#define RAINFO_STBC_STATE BIT(1) -/* #define RAINFO_LDPC_STATE BIT2 */ -#define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */ -#define RAINFO_SHURTCUT_STATE BIT(3) -#define RAINFO_SHURTCUT_FLAG BIT(4) -#define RAINFO_INIT_RSSI_RATE_STATE BIT(5) -#define RAINFO_BF_STATE BIT(6) -#define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */ - -#define RA_MASK_CCK 0xf -#define RA_MASK_OFDM 0xff0 -#define RA_MASK_HT1SS 0xff000 -#define RA_MASK_HT2SS 0xff00000 -/*#define RA_MASK_MCS3SS */ -#define RA_MASK_HT4SS 0xff0 -#define RA_MASK_VHT1SS 0x3ff000 -#define RA_MASK_VHT2SS 0xffc00000 - #if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #define RA_FIRST_MACID 1 -#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define RA_FIRST_MACID 0 - #define WIN_DEFAULT_PORT_MACID 0 - #define WIN_BT_PORT_MACID 2 -#else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ - #define RA_FIRST_MACID 0 -#endif - -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) -#define AP_InitRateAdaptiveState odm_rate_adaptive_state_ap_init + #define FIRST_MACID 1 #else -#define ap_init_rate_adaptive_state odm_rate_adaptive_state_ap_init -#endif - -#if (RA_MASK_PHYDMLIZE_CE || RA_MASK_PHYDMLIZE_AP || RA_MASK_PHYDMLIZE_WIN) - #define DM_RATR_STA_INIT 0 - #define DM_RATR_STA_HIGH 1 - #define DM_RATR_STA_MIDDLE 2 - #define DM_RATR_STA_LOW 3 - #define DM_RATR_STA_ULTRA_LOW 4 + #define FIRST_MACID 0 #endif -enum phydm_ra_arfr_num_e { - ARFR_0_RATE_ID = 0x9, - ARFR_1_RATE_ID = 0xa, - ARFR_2_RATE_ID = 0xb, - ARFR_3_RATE_ID = 0xc, - ARFR_4_RATE_ID = 0xd, - ARFR_5_RATE_ID = 0xe -}; - -enum phydm_ra_dbg_para_e { - RADBG_PCR_TH_OFFSET = 0, - RADBG_RTY_PENALTY = 1, - RADBG_N_HIGH = 2, - RADBG_N_LOW = 3, - RADBG_TRATE_UP_TABLE = 4, - RADBG_TRATE_DOWN_TABLE = 5, - RADBG_TRYING_NECESSARY = 6, - RADBG_TDROPING_NECESSARY = 7, - RADBG_RATE_UP_RTY_RATIO = 8, - RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */ - - RADBG_DEBUG_MONITOR1 = 0xc, - RADBG_DEBUG_MONITOR2 = 0xd, - RADBG_DEBUG_MONITOR3 = 0xe, - RADBG_DEBUG_MONITOR4 = 0xf, - RADBG_DEBUG_MONITOR5 = 0x10, +/* @1 ============================================================ + * 1 enumrate + * 1 ============================================================ + */ + +enum phydm_ra_dbg_para { + RADBG_PCR_TH_OFFSET = 0, + RADBG_RTY_PENALTY = 1, + RADBG_N_HIGH = 2, + RADBG_N_LOW = 3, + RADBG_TRATE_UP_TABLE = 4, + RADBG_TRATE_DOWN_TABLE = 5, + RADBG_TRYING_NECESSARY = 6, + RADBG_TDROPING_NECESSARY = 7, + RADBG_RATE_UP_RTY_RATIO = 8, + RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */ + + RADBG_DEBUG_MONITOR1 = 0xc, + RADBG_DEBUG_MONITOR2 = 0xd, + RADBG_DEBUG_MONITOR3 = 0xe, + RADBG_DEBUG_MONITOR4 = 0xf, + RADBG_DEBUG_MONITOR5 = 0x10, NUM_RA_PARA }; -enum phydm_wireless_mode_e { - - PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, +enum phydm_wireless_mode { + PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, PHYDM_WIRELESS_MODE_A = 0x01, PHYDM_WIRELESS_MODE_B = 0x02, PHYDM_WIRELESS_MODE_G = 0x04, @@ -132,458 +86,191 @@ enum phydm_wireless_mode_e { PHYDM_WIRELESS_MODE_ALL = 0xFFFF }; -enum phydm_rateid_idx_e { - +enum phydm_rateid_idx { PHYDM_BGN_40M_2SS = 0, PHYDM_BGN_40M_1SS = 1, PHYDM_BGN_20M_2SS = 2, PHYDM_BGN_20M_1SS = 3, - PHYDM_GN_N2SS = 4, - PHYDM_GN_N1SS = 5, - PHYDM_BG = 6, - PHYDM_G = 7, - PHYDM_B_20M = 8, + PHYDM_GN_N2SS = 4, + PHYDM_GN_N1SS = 5, + PHYDM_BG = 6, + PHYDM_G = 7, + PHYDM_B_20M = 8, PHYDM_ARFR0_AC_2SS = 9, PHYDM_ARFR1_AC_1SS = 10, PHYDM_ARFR2_AC_2G_1SS = 11, PHYDM_ARFR3_AC_2G_2SS = 12, PHYDM_ARFR4_AC_3SS = 13, - PHYDM_ARFR5_N_3SS = 14 + PHYDM_ARFR5_N_3SS = 14, + PHYDM_ARFR7_N_4SS = 15, + PHYDM_ARFR6_AC_4SS = 16 }; -enum phydm_rf_type_def_e { - PHYDM_RF_1T1R = 0, - PHYDM_RF_1T2R, - PHYDM_RF_2T2R, - PHYDM_RF_2T2R_GREEN, - PHYDM_RF_2T3R, - PHYDM_RF_2T4R, - PHYDM_RF_3T3R, - PHYDM_RF_3T4R, - PHYDM_RF_4T4R, - PHYDM_RF_MAX_TYPE -}; +#if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */ -enum phydm_bw_e { - PHYDM_BW_20 = 0, - PHYDM_BW_40, - PHYDM_BW_80, - PHYDM_BW_80_80, - PHYDM_BW_160, - PHYDM_BW_10, - PHYDM_BW_5 +struct _phydm_txstatistic_ { + u32 hw_total_tx; + u32 hw_tx_success; + u32 hw_tx_rty; + u32 hw_tx_drop; }; - -#if (RATE_ADAPTIVE_SUPPORT == 1)/* 88E RA */ +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ struct _odm_ra_info_ { - u8 rate_id; - u32 rate_mask; - u32 ra_use_rate; - u8 rate_sgi; - u8 rssi_sta_ra; - u8 pre_rssi_sta_ra; - u8 sgi_enable; - u8 decision_rate; - u8 pre_rate; - u8 highest_rate; - u8 lowest_rate; - u32 nsc_up; - u32 nsc_down; - u16 RTY[5]; - u32 TOTAL; - u16 DROP; - u8 active; - u16 rpt_time; - u8 ra_waiting_counter; - u8 ra_pending_counter; - u8 ra_drop_after_down; + u8 rate_id; + u32 rate_mask; + u32 ra_use_rate; + u8 rate_sgi; + u8 rssi_sta_ra; + u8 pre_rssi_sta_ra; + u8 sgi_enable; + u8 decision_rate; + u8 pre_rate; + u8 highest_rate; + u8 lowest_rate; + u32 nsc_up; + u32 nsc_down; + u16 RTY[5]; + u32 TOTAL; + u16 DROP; + u8 active; + u16 rpt_time; + u8 ra_waiting_counter; + u8 ra_pending_counter; + u8 ra_drop_after_down; #if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */ - u8 pt_active; /* on or off */ - u8 pt_try_state; /* 0 trying state, 1 for decision state */ - u8 pt_stage; /* 0~6 */ - u8 pt_stop_count; /* Stop PT counter */ - u8 pt_pre_rate; /* if rate change do PT */ - u8 pt_pre_rssi; /* if RSSI change 5% do PT */ - u8 pt_mode_ss; /* decide whitch rate should do PT */ - u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */ - u8 pt_smooth_factor; + u8 pt_active; /* on or off */ + u8 pt_try_state; /* @0 trying state, 1 for decision state */ + u8 pt_stage; /* @0~6 */ + u8 pt_stop_count; /* Stop PT counter */ + u8 pt_pre_rate; /* @if rate change do PT */ + u8 pt_pre_rssi; /* @if RSSI change 5% do PT */ + u8 pt_mode_ss; /* @decide whitch rate should do PT */ + u8 ra_stage; /* @StageRA, decide how many times RA will be done between PT */ + u8 pt_smooth_factor; #endif #if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) - u8 rate_down_counter; - u8 rate_up_counter; - u8 rate_direction; - u8 bounding_type; - u8 bounding_counter; - u8 bounding_learning_time; - u8 rate_down_start_time; + u8 rate_down_counter; + u8 rate_up_counter; + u8 rate_direction; + u8 bounding_type; + u8 bounding_counter; + u8 bounding_learning_time; + u8 rate_down_start_time; #endif }; #endif -struct _rate_adaptive_table_ { - u8 firstconnect; -#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - boolean PT_collision_pre; +struct ra_table { + u8 firstconnect; + /*@u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];*/ + u8 mu1_rate[30]; + u8 highest_client_tx_order; + u16 highest_client_tx_rate_order; + u8 power_tracking_flag; + u8 ra_th_ofst; /*RA_threshold_offset*/ + u8 ra_ofst_direc; /*RA_offset_direction*/ + u8 up_ramask_cnt; /*@force update_ra_mask counter*/ + u8 up_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/ +#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + u8 per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; + u8 per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; + u8 retry_descend_num; + u8 retrylimit_low; + u8 retrylimit_high; #endif + u8 ldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */ + void (*record_ra_info)(void *dm_void, u8 macid, + struct cmn_sta_info *sta, u64 ra_mask); +}; -#if (defined(CONFIG_RA_DBG_CMD)) - boolean is_ra_dbg_init; +/* @1 ============================================================ + * 1 Function Prototype + * 1 ============================================================ + */ +boolean phydm_is_cck_rate(void *dm_void, u8 rate); - u8 RTY_P[ODM_NUM_RATE_IDX]; - u8 RTY_P_default[ODM_NUM_RATE_IDX]; - boolean RTY_P_modify_note[ODM_NUM_RATE_IDX]; +boolean phydm_is_ofdm_rate(void *dm_void, u8 rate); - u8 RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX]; - u8 RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX]; - boolean RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; +boolean phydm_is_ht_rate(void *dm_void, u8 rate); - u8 RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX]; - u8 RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX]; - boolean RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; +boolean phydm_is_vht_rate(void *dm_void, u8 rate); - boolean ra_para_feedback_req; +u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type); - u8 para_idx; - u8 rate_idx; - u8 value; - u16 value_16; - u8 rate_length; -#endif - u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; - u8 highest_client_tx_order; - u16 highest_client_tx_rate_order; - u8 power_tracking_flag; - u8 RA_threshold_offset; - u8 RA_offset_direction; - u8 force_update_ra_mask_count; - -#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) - u8 per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; - u8 per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; - u8 retry_descend_num; - u8 retrylimit_low; - u8 retrylimit_high; -#endif +u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate); +void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); -}; +void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); + +void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); + +void phydm_ra_dynamic_retry_count(void *dm_void); + + +void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component); + +void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size); + +void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); + +u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx); -struct _ODM_RATE_ADAPTIVE { - u8 type; /* dm_type_by_fw/dm_type_by_driver */ - u8 high_rssi_thresh; /* if RSSI > high_rssi_thresh => ratr_state is DM_RATR_STA_HIGH */ - u8 low_rssi_thresh; /* if RSSI <= low_rssi_thresh => ratr_state is DM_RATR_STA_LOW */ - u8 ratr_state; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ +void phydm_ra_info_watchdog(void *dm_void); -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - u8 ldpc_thres; /* if RSSI > ldpc_thres => switch from LPDC to BCC */ - boolean is_lower_rts_rate; +void phydm_ra_info_init(void *dm_void); + +void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc, + u8 ra_th_ofst); + +u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode); + +u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw); +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +void phydm_update_hal_ra_mask( + void *dm_void, + u32 wireless_mode, + u8 rf_type, + u8 BW, + u8 mimo_ps_enable, + u8 disable_cck_rate, + u32 *ratr_bitmap_msb_in, + u32 *ratr_bitmap_in, + u8 tx_rate_level); #endif -#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) - u8 rts_thres; -#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) - boolean is_use_ldpc; -#else - u8 ultra_low_rssi_thresh; - u32 last_ratr; /* RATR Register Content */ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +u8 phydm_get_plcp(void *dm_void, u16 macid); #endif -}; +void phydm_refresh_rate_adaptive_mask(void *dm_void); -void -phydm_h2C_debug( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -); +u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state); -#if (defined(CONFIG_RA_DBG_CMD)) +void odm_ra_post_action_on_assoc(void *dm); -void -odm_RA_debug( - void *p_dm_void, - u32 *const dm_value -); +u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect); -void -odm_ra_para_adjust_init( - void *p_dm_void -); +void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); -#else +u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx); -void -phydm_RA_debug_PCR( - void *p_dm_void, - u32 *const dm_value, - u32 *_used, - char *output, - u32 *_out_len -); +void phydm_ra_registed(void *dm_void, u8 macid, u8 rssi_from_assoc); -#endif +void phydm_ra_offline(void *dm_void, u8 macid); -void -odm_c2h_ra_para_report_handler( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len -); - -void -odm_ra_para_adjust( - void *p_dm_void -); - -void -phydm_ra_dynamic_retry_count( - void *p_dm_void -); - -void -phydm_ra_dynamic_retry_limit( - void *p_dm_void -); - -void -phydm_ra_dynamic_rate_id_on_assoc( - void *p_dm_void, - u8 wireless_mode, - u8 init_rate_id -); - -void -phydm_print_rate( - void *p_dm_void, - u8 rate, - u32 dbg_component -); - -void -phydm_c2h_ra_report_handler( - void *p_dm_void, - u8 *cmd_buf, - u8 cmd_len -); - -u8 -phydm_rate_order_compute( - void *p_dm_void, - u8 rate_idx -); - -void -phydm_ra_info_watchdog( - void *p_dm_void -); - -void -phydm_ra_info_init( - void *p_dm_void -); - -void -odm_rssi_monitor_init( - void *p_dm_void -); - -void -phydm_modify_RA_PCR_threshold( - void *p_dm_void, - u8 RA_offset_direction, - u8 RA_threshold_offset -); - -void -odm_rssi_monitor_check( - void *p_dm_void -); - -void -phydm_init_ra_info( - void *p_dm_void -); - -u8 -phydm_vht_en_mapping( - void *p_dm_void, - u32 wireless_mode -); - -u8 -phydm_rate_id_mapping( - void *p_dm_void, - u32 wireless_mode, - u8 rf_type, - u8 bw -); - -void -phydm_update_hal_ra_mask( - void *p_dm_void, - u32 wireless_mode, - u8 rf_type, - u8 BW, - u8 mimo_ps_enable, - u8 disable_cck_rate, - u32 *ratr_bitmap_msb_in, - u32 *ratr_bitmap_in, - u8 tx_rate_level -); - -void -odm_rate_adaptive_mask_init( - void *p_dm_void -); - -void -odm_refresh_rate_adaptive_mask( - void *p_dm_void -); - -void -odm_refresh_rate_adaptive_mask_mp( - void *p_dm_void -); - -void -odm_refresh_rate_adaptive_mask_ce( - void *p_dm_void -); - -void -odm_refresh_rate_adaptive_mask_apadsl( - void *p_dm_void -); - -u8 -phydm_RA_level_decision( - void *p_dm_void, - u32 rssi, - u8 ratr_state -); - -boolean -odm_ra_state_check( - void *p_dm_void, - s32 RSSI, - boolean is_force_update, - u8 *p_ra_tr_state -); - -void -odm_refresh_basic_rate_mask( - void *p_dm_void -); -void -odm_ra_post_action_on_assoc( - void *p_dm_odm -); - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) - -u8 -odm_find_rts_rate( - void *p_dm_void, - u8 tx_rate, - boolean is_erp_protect -); - -void -odm_update_noisy_state( - void *p_dm_void, - boolean is_noisy_state_from_c2h -); - -void -phydm_update_pwr_track( - void *p_dm_void, - u8 rate -); +void phydm_ra_mask_watchdog(void *dm_void); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - -s32 -phydm_find_minimum_rssi( - struct PHY_DM_STRUCT *p_dm_odm, - struct _ADAPTER *p_adapter, - OUT boolean *p_is_link_temp -); - -void -odm_update_init_rate_work_item_callback( - void *p_context -); - -void -odm_rssi_dump_to_register( - void *p_dm_void -); - -void -odm_refresh_ldpc_rts_mp( - struct _ADAPTER *p_adapter, - struct PHY_DM_STRUCT *p_dm_odm, - u8 m_mac_id, - u8 iot_peer, - s32 undecorated_smoothed_pwdb -); - -#if 0 -void -odm_dynamic_arfb_select( - void *p_dm_void, - u8 rate, - boolean collision_state -); +void odm_refresh_basic_rate_mask( + void *dm_void); #endif - -void -odm_rate_adaptive_state_ap_init( - void *PADAPTER_VOID, - struct sta_info *p_entry -); -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - -static void -find_minimum_rssi( - struct _ADAPTER *p_adapter -); - -u64 -phydm_get_rate_bitmap_ex( - void *p_dm_void, - u32 macid, - u64 ra_mask, - u8 rssi_level, - u64 *dm_ra_mask, - u8 *dm_rte_id -); -u32 -odm_get_rate_bitmap( - void *p_dm_void, - u32 macid, - u32 ra_mask, - u8 rssi_level -); - -void phydm_ra_rssi_rpt_wk(void *p_context); -#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ - -#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) -/* -void -phydm_gen_ramask_h2c_AP( - void *p_dm_void, - struct rtl8192cd_priv *priv, - struct sta_info *p_entry, - u8 rssi_level -); -*/ -#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ - -#endif /*#ifndef __ODMRAINFO_H__*/ +#endif /*@#ifndef __PHYDMRAINFO_H__*/ diff --git a/hal/phydm/phydm_reg.h b/hal/phydm/phydm_reg.h index 16328fe..1078eaa 100644 --- a/hal/phydm/phydm_reg.h +++ b/hal/phydm/phydm_reg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,16 +8,21 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ -/* ************************************************************ + * Larry Finger + * + *****************************************************************************/ +/************************************************************* * File Name: odm_reg.h * * Description: @@ -25,17 +30,18 @@ * This file is for general register definition. * * - * ************************************************************ */ -#ifndef __HAL_ODM_REG_H__ + ************************************************************/ +#ifndef __HAL_ODM_REG_H__ #define __HAL_ODM_REG_H__ -/* +/*@ * Register Definition - * */ + * + */ -/* MAC REG */ -#define ODM_BB_RESET 0x002 -#define ODM_DUMMY 0x4fe +/* @MAC REG */ +#define ODM_BB_RESET 0x002 +#define ODM_DUMMY 0x4fe #define RF_T_METER_OLD 0x24 #define RF_T_METER_NEW 0x42 @@ -43,159 +49,159 @@ #define ODM_EDCA_VI_PARAM 0x504 #define ODM_EDCA_BE_PARAM 0x508 #define ODM_EDCA_BK_PARAM 0x50C -#define ODM_TXPAUSE 0x522 +#define ODM_TXPAUSE 0x522 -/* LTE_COEX */ +/* @LTE_COEX */ #define REG_LTECOEX_CTRL 0x07C0 -#define REG_LTECOEX_WRITE_DATA 0x07C4 -#define REG_LTECOEX_READ_DATA 0x07C8 -#define REG_LTECOEX_PATH_CONTROL 0x70 +#define REG_LTECOEX_WRITE_DATA 0x07C4 +#define REG_LTECOEX_READ_DATA 0x07C8 +#define REG_LTECOEX_PATH_CONTROL 0x70 -/* BB REG */ +/* @BB REG */ #define ODM_FPGA_PHY0_PAGE8 0x800 #define ODM_PSD_SETTING 0x808 #define ODM_AFE_SETTING 0x818 -#define ODM_TXAGC_B_6_18 0x830 +#define ODM_TXAGC_B_6_18 0x830 #define ODM_TXAGC_B_24_54 0x834 #define ODM_TXAGC_B_MCS32_5 0x838 -#define ODM_TXAGC_B_MCS0_MCS3 0x83c -#define ODM_TXAGC_B_MCS4_MCS7 0x848 -#define ODM_TXAGC_B_MCS8_MCS11 0x84c +#define ODM_TXAGC_B_MCS0_MCS3 0x83c +#define ODM_TXAGC_B_MCS4_MCS7 0x848 +#define ODM_TXAGC_B_MCS8_MCS11 0x84c #define ODM_ANALOG_REGISTER 0x85c -#define ODM_RF_INTERFACE_OUTPUT 0x860 -#define ODM_TXAGC_B_MCS12_MCS15 0x868 -#define ODM_TXAGC_B_11_A_2_11 0x86c +#define ODM_RF_INTERFACE_OUTPUT 0x860 +#define ODM_TXAGC_B_MCS12_MCS15 0x868 +#define ODM_TXAGC_B_11_A_2_11 0x86c #define ODM_AD_DA_LSB_MASK 0x874 #define ODM_ENABLE_3_WIRE 0x88c #define ODM_PSD_REPORT 0x8b4 -#define ODM_R_ANT_SELECT 0x90c +#define ODM_R_ANT_SELECT 0x90c #define ODM_CCK_ANT_SELECT 0xa07 #define ODM_CCK_PD_THRESH 0xa0a #define ODM_CCK_RF_REG1 0xa11 #define ODM_CCK_MATCH_FILTER 0xa20 -#define ODM_CCK_RAKE_MAC 0xa2e +#define ODM_CCK_RAKE_MAC 0xa2e #define ODM_CCK_CNT_RESET 0xa2d #define ODM_CCK_TX_DIVERSITY 0xa2f #define ODM_CCK_FA_CNT_MSB 0xa5b #define ODM_CCK_FA_CNT_LSB 0xa5c -#define ODM_CCK_NEW_FUNCTION 0xa75 -#define ODM_OFDM_PHY0_PAGE_C 0xc00 +#define ODM_CCK_NEW_FUNCTION 0xa75 +#define ODM_OFDM_PHY0_PAGE_C 0xc00 #define ODM_OFDM_RX_ANT 0xc04 -#define ODM_R_A_RXIQI 0xc14 +#define ODM_R_A_RXIQI 0xc14 #define ODM_R_A_AGC_CORE1 0xc50 #define ODM_R_A_AGC_CORE2 0xc54 #define ODM_R_B_AGC_CORE1 0xc58 -#define ODM_R_AGC_PAR 0xc70 +#define ODM_R_AGC_PAR 0xc70 #define ODM_R_HTSTF_AGC_PAR 0xc7c -#define ODM_TX_PWR_TRAINING_A 0xc90 -#define ODM_TX_PWR_TRAINING_B 0xc98 -#define ODM_OFDM_FA_CNT1 0xcf0 -#define ODM_OFDM_PHY0_PAGE_D 0xd00 -#define ODM_OFDM_FA_CNT2 0xda0 -#define ODM_OFDM_FA_CNT3 0xda4 -#define ODM_OFDM_FA_CNT4 0xda8 -#define ODM_TXAGC_A_6_18 0xe00 +#define ODM_TX_PWR_TRAINING_A 0xc90 +#define ODM_TX_PWR_TRAINING_B 0xc98 +#define ODM_OFDM_FA_CNT1 0xcf0 +#define ODM_OFDM_PHY0_PAGE_D 0xd00 +#define ODM_OFDM_FA_CNT2 0xda0 +#define ODM_OFDM_FA_CNT3 0xda4 +#define ODM_OFDM_FA_CNT4 0xda8 +#define ODM_TXAGC_A_6_18 0xe00 #define ODM_TXAGC_A_24_54 0xe04 #define ODM_TXAGC_A_1_MCS32 0xe08 -#define ODM_TXAGC_A_MCS0_MCS3 0xe10 -#define ODM_TXAGC_A_MCS4_MCS7 0xe14 -#define ODM_TXAGC_A_MCS8_MCS11 0xe18 -#define ODM_TXAGC_A_MCS12_MCS15 0xe1c +#define ODM_TXAGC_A_MCS0_MCS3 0xe10 +#define ODM_TXAGC_A_MCS4_MCS7 0xe14 +#define ODM_TXAGC_A_MCS8_MCS11 0xe18 +#define ODM_TXAGC_A_MCS12_MCS15 0xe1c /* RF REG */ -#define ODM_GAIN_SETTING 0x00 -#define ODM_CHANNEL 0x18 +#define ODM_GAIN_SETTING 0x00 +#define ODM_CHANNEL 0x18 #define ODM_RF_T_METER 0x24 #define ODM_RF_T_METER_92D 0x42 #define ODM_RF_T_METER_88E 0x42 #define ODM_RF_T_METER_92E 0x42 #define ODM_RF_T_METER_8812 0x42 -#define REG_RF_TX_GAIN_OFFSET 0x55 +#define REG_RF_TX_GAIN_OFFSET 0x55 -/* ant Detect Reg */ -#define ODM_DPDT 0x300 +/* @ant Detect Reg */ +#define ODM_DPDT 0x300 /* PSD Init */ -#define ODM_PSDREG 0x808 +#define ODM_PSDREG 0x808 -/* 92D path Div */ -#define PATHDIV_REG 0xB30 -#define PATHDIV_TRI 0xBA0 +/* @92D path Div */ +#define PATHDIV_REG 0xB30 +#define PATHDIV_TRI 0xBA0 -/* +/*@ * Bitmap Definition - * */ + */ #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) /* TX AGC */ - #define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR 0xc20 - #define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR 0xc24 - #define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR 0xc28 - #define REG_TX_AGC_A_MCS3_MCS0_JAGUAR 0xc2c - #define REG_TX_AGC_A_MCS7_MCS4_JAGUAR 0xc30 - #define REG_TX_AGC_A_MCS11_MCS8_JAGUAR 0xc34 - #define REG_TX_AGC_A_MCS15_MCS12_JAGUAR 0xc38 + #define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR 0xc20 + #define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR 0xc24 + #define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR 0xc28 + #define REG_TX_AGC_A_MCS3_MCS0_JAGUAR 0xc2c + #define REG_TX_AGC_A_MCS7_MCS4_JAGUAR 0xc30 + #define REG_TX_AGC_A_MCS11_MCS8_JAGUAR 0xc34 + #define REG_TX_AGC_A_MCS15_MCS12_JAGUAR 0xc38 #define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xc3c #define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xc40 #define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xc44 #define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xc48 #define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xc4c #if defined(CONFIG_WLAN_HAL_8814AE) - #define REG_TX_AGC_A_MCS19_MCS16_JAGUAR 0xcd8 - #define REG_TX_AGC_A_MCS23_MCS20_JAGUAR 0xcdc + #define REG_TX_AGC_A_MCS19_MCS16_JAGUAR 0xcd8 + #define REG_TX_AGC_A_MCS23_MCS20_JAGUAR 0xcdc #define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xce0 #define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xce4 #define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xce8 #endif - #define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR 0xe20 - #define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR 0xe24 - #define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR 0xe28 - #define REG_TX_AGC_B_MCS3_MCS0_JAGUAR 0xe2c - #define REG_TX_AGC_B_MCS7_MCS4_JAGUAR 0xe30 - #define REG_TX_AGC_B_MCS11_MCS8_JAGUAR 0xe34 - #define REG_TX_AGC_B_MCS15_MCS12_JAGUAR 0xe38 + #define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR 0xe20 + #define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR 0xe24 + #define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR 0xe28 + #define REG_TX_AGC_B_MCS3_MCS0_JAGUAR 0xe2c + #define REG_TX_AGC_B_MCS7_MCS4_JAGUAR 0xe30 + #define REG_TX_AGC_B_MCS11_MCS8_JAGUAR 0xe34 + #define REG_TX_AGC_B_MCS15_MCS12_JAGUAR 0xe38 #define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xe3c #define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xe40 #define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xe44 #define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xe48 #define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xe4c #if defined(CONFIG_WLAN_HAL_8814AE) - #define REG_TX_AGC_B_MCS19_MCS16_JAGUAR 0xed8 - #define REG_TX_AGC_B_MCS23_MCS20_JAGUAR 0xedc + #define REG_TX_AGC_B_MCS19_MCS16_JAGUAR 0xed8 + #define REG_TX_AGC_B_MCS23_MCS20_JAGUAR 0xedc #define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xee0 #define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xee4 #define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xee8 #define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR 0x1820 #define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR 0x1824 #define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR 0x1828 - #define REG_TX_AGC_C_MCS3_MCS0_JAGUAR 0x182c - #define REG_TX_AGC_C_MCS7_MCS4_JAGUAR 0x1830 - #define REG_TX_AGC_C_MCS11_MCS8_JAGUAR 0x1834 - #define REG_TX_AGC_C_MCS15_MCS12_JAGUAR 0x1838 + #define REG_TX_AGC_C_MCS3_MCS0_JAGUAR 0x182c + #define REG_TX_AGC_C_MCS7_MCS4_JAGUAR 0x1830 + #define REG_TX_AGC_C_MCS11_MCS8_JAGUAR 0x1834 + #define REG_TX_AGC_C_MCS15_MCS12_JAGUAR 0x1838 #define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x183c #define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1840 #define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1844 #define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1848 #define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x184c - #define REG_TX_AGC_C_MCS19_MCS16_JAGUAR 0x18d8 - #define REG_TX_AGC_C_MCS23_MCS20_JAGUAR 0x18dc + #define REG_TX_AGC_C_MCS19_MCS16_JAGUAR 0x18d8 + #define REG_TX_AGC_C_MCS23_MCS20_JAGUAR 0x18dc #define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x18e0 #define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x18e4 #define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x18e8 #define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR 0x1a20 #define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR 0x1a24 #define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR 0x1a28 - #define REG_TX_AGC_D_MCS3_MCS0_JAGUAR 0x1a2c - #define REG_TX_AGC_D_MCS7_MCS4_JAGUAR 0x1a30 - #define REG_TX_AGC_D_MCS11_MCS8_JAGUAR 0x1a34 - #define REG_TX_AGC_D_MCS15_MCS12_JAGUAR 0x1a38 + #define REG_TX_AGC_D_MCS3_MCS0_JAGUAR 0x1a2c + #define REG_TX_AGC_D_MCS7_MCS4_JAGUAR 0x1a30 + #define REG_TX_AGC_D_MCS11_MCS8_JAGUAR 0x1a34 + #define REG_TX_AGC_D_MCS15_MCS12_JAGUAR 0x1a38 #define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x1a3c #define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1a40 #define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1a44 #define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1a48 #define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x1a4c - #define REG_TX_AGC_D_MCS19_MCS16_JAGUAR 0x1ad8 - #define REG_TX_AGC_D_MCS23_MCS20_JAGUAR 0x1adc + #define REG_TX_AGC_D_MCS19_MCS16_JAGUAR 0x1ad8 + #define REG_TX_AGC_D_MCS23_MCS20_JAGUAR 0x1adc #define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x1ae0 #define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x1ae4 #define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x1ae8 @@ -205,10 +211,31 @@ #define is_tx_agc_byte1_jaguar 0xff00 #define is_tx_agc_byte2_jaguar 0xff0000 #define is_tx_agc_byte3_jaguar 0xff000000 + #if defined(CONFIG_WLAN_HAL_8198F) + #define REG_TX_AGC_CCK_11_CCK_1_JAGUAR3 0x3a00 + #define REG_TX_AGC_OFDM_18_CCK_6_JAGUAR3 0x3a04 + #define REG_TX_AGC_OFDM_54_CCK_24_JAGUAR3 0x3a08 + #define REG_TX_AGC_MCS3_0_JAGUAR3 0x3a0c + #define REG_TX_AGC_MCS7_4_JAGUAR3 0x3a10 + #define REG_TX_AGC_MCS11_8_JAGUAR3 0x3a14 + #define REG_TX_AGC_MCS15_12_JAGUAR3 0x3a18 + #define REG_TX_AGC_MCS19_16_JAGUAR3 0x3a1c + #define REG_TX_AGC_MCS23_20_JAGUAR3 0x3a20 + #define REG_TX_AGC_MCS27_24_JAGUAR3 0x3a24 + #define REG_TX_AGC_MCS31_28_JAGUAR3 0x3a28 + #define REG_TX_AGC_VHT_Nss1_MCS3_0_JAGUAR3 0x3a2c + #define REG_TX_AGC_VHT_Nss1_MCS7_4_JAGUAR3 0x3a30 + #define REG_TX_AGC_VHT_NSS2_MCS1_NSS1_MCS8_JAGUAR3 0x3a34 + #define REG_TX_AGC_VHT_Nss2_MCS5_2_JAGUAR3 0x3a38 + #define REG_TX_AGC_VHT_Nss2_MCS9_6_JAGUAR3 0x3a3c + #define REG_TX_AGC_VHT_Nss3_MCS3_0_JAGUAR3 0x3a40 + #define REG_TX_AGC_VHT_Nss3_MCS7_4_JAGUAR3 0x3a44 + #define REG_TX_AGC_VHT_Nss4_MCS1_Nss3_MCS8_JAGUAR3 0x3a48 + #define REG_TX_AGC_VHT_Nss4_MCS5_2_JAGUAR3 0x3a4c + #define REG_TX_AGC_VHT_Nss4_MCS9_6_JAGUAR3 0x3a50 + #endif #endif #define BIT_FA_RESET BIT(0) - - #endif diff --git a/hal/phydm/phydm_regdefine11ac.h b/hal/phydm/phydm_regdefine11ac.h index 171348c..7824ac2 100644 --- a/hal/phydm/phydm_regdefine11ac.h +++ b/hal/phydm/phydm_regdefine11ac.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,86 +8,102 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -#ifndef __ODM_REGDEFINE11AC_H__ +#ifndef __ODM_REGDEFINE11AC_H__ #define __ODM_REGDEFINE11AC_H__ -/* 2 RF REG LIST */ +/* @2 RF REG LIST */ -/* 2 BB REG LIST - * PAGE 8 */ -#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 +/* @2 BB REG LIST */ +/* PAGE 8 */ +#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 #define ODM_REG_BB_RX_PATH_11AC 0x808 #define ODM_REG_BB_TX_PATH_11AC 0x80c -#define ODM_REG_BB_ATC_11AC 0x860 -#define ODM_REG_EDCCA_POWER_CAL 0x8dc +#define ODM_REG_BB_ATC_11AC 0x860 +#define ODM_REG_EDCCA_POWER_CAL 0x8dc #define ODM_REG_DBG_RPT_11AC 0x8fc /* PAGE 9 */ #define ODM_REG_EDCCA_DOWN_OPT 0x900 #define ODM_REG_ACBB_EDCCA_ENHANCE 0x944 -#define odm_adc_trigger_jaguar2 0x95C /*ADC sample mode*/ +#define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/ #define ODM_REG_OFDM_FA_RST_11AC 0x9A4 #define ODM_REG_CCX_PERIOD_11AC 0x990 #define ODM_REG_NHM_TH9_TH10_11AC 0x994 -#define ODM_REG_CLM_11AC 0x994 -#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998 -#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c +#define ODM_REG_CLM_11AC 0x994 +#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998 +#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c #define ODM_REG_NHM_TH8_11AC 0x9a0 #define ODM_REG_NHM_9E8_11AC 0x9e8 #define ODM_REG_CSI_CONTENT_VALUE 0x9b4 /* PAGE A */ #define ODM_REG_CCK_CCA_11AC 0xA0A #define ODM_REG_CCK_FA_RST_11AC 0xA2C -#define ODM_REG_CCK_FA_11AC 0xA5C +#define ODM_REG_CCK_FA_11AC 0xA5C /* PAGE B */ -#define ODM_REG_RST_RPT_11AC 0xB58 +#define ODM_REG_RST_RPT_11AC 0xB58 /* PAGE C */ -#define ODM_REG_TRMUX_11AC 0xC08 -#define ODM_REG_IGI_A_11AC 0xC50 +#define ODM_REG_TRMUX_11AC 0xC08 +#define ODM_REG_IGI_A_11AC 0xC50 /* PAGE E */ -#define ODM_REG_IGI_B_11AC 0xE50 -#define ODM_REG_TRMUX_11AC_B 0xE08 +#define ODM_REG_IGI_B_11AC 0xE50 +#define ODM_REG_ANT_11AC_B 0xE08 /* PAGE F */ #define ODM_REG_CCK_CRC32_CNT_11AC 0xF04 #define ODM_REG_CCK_CCA_CNT_11AC 0xF08 #define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c #define ODM_REG_HT_CRC32_CNT_11AC 0xF10 -#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14 +#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14 #define ODM_REG_OFDM_FA_11AC 0xF48 -#define ODM_REG_RPT_11AC 0xfa0 +#define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC +#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 +#define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC +#define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0 +#define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4 +#define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8 +#define ODM_REG_RPT_11AC 0xfa0 #define ODM_REG_CLM_RESULT_11AC 0xfa4 #define ODM_REG_NHM_CNT_11AC 0xfa8 -#define ODM_REG_NHM_DUR_READY_11AC 0xfb4 +#define ODM_REG_NHM_DUR_READY_11AC 0xfb4 -#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac -#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 -#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 +#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac +#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 /* PAGE 18 */ -#define ODM_REG_IGI_C_11AC 0x1850 +#define ODM_REG_IGI_C_11AC 0x1850 /* PAGE 1A */ -#define ODM_REG_IGI_D_11AC 0x1A50 +#define ODM_REG_IGI_D_11AC 0x1A50 + +/* PAGE 1D */ +#define ODM_REG_IGI_11AC3 0x1D70 -/* 2 MAC REG LIST */ -#define ODM_REG_RESP_TX_11AC 0x6D8 +/* @2 MAC REG LIST */ +#define ODM_REG_RESP_TX_11AC 0x6D8 -/* DIG Related */ -#define ODM_BIT_IGI_11AC 0xFFFFFFFF +/* @DIG Related */ +#define ODM_BIT_IGI_11AC 0x0000007F +#define ODM_BIT_IGI_B_11AC3 0x00007F00 +#define ODM_BIT_IGI_C_11AC3 0x007F0000 +#define ODM_BIT_IGI_D_11AC3 0x7F000000 #define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16) #define ODM_BIT_BB_RX_PATH_11AC 0xF #define ODM_BIT_BB_TX_PATH_11AC 0xF -#define ODM_BIT_BB_ATC_11AC BIT(14) +#define ODM_BIT_BB_ATC_11AC BIT(14) #endif diff --git a/hal/phydm/phydm_regdefine11n.h b/hal/phydm/phydm_regdefine11n.h index 643f8b4..e36f37d 100644 --- a/hal/phydm/phydm_regdefine11n.h +++ b/hal/phydm/phydm_regdefine11n.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,95 +8,101 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ -#ifndef __ODM_REGDEFINE11N_H__ +#ifndef __ODM_REGDEFINE11N_H__ #define __ODM_REGDEFINE11N_H__ - -/* 2 RF REG LIST */ -#define ODM_REG_RF_MODE_11N 0x00 -#define ODM_REG_RF_0B_11N 0x0B -#define ODM_REG_CHNBW_11N 0x18 -#define ODM_REG_T_METER_11N 0x24 -#define ODM_REG_RF_25_11N 0x25 -#define ODM_REG_RF_26_11N 0x26 -#define ODM_REG_RF_27_11N 0x27 -#define ODM_REG_RF_2B_11N 0x2B -#define ODM_REG_RF_2C_11N 0x2C -#define ODM_REG_RXRF_A3_11N 0x3C +/* @2 RF REG LIST */ +#define ODM_REG_RF_MODE_11N 0x00 +#define ODM_REG_RF_0B_11N 0x0B +#define ODM_REG_CHNBW_11N 0x18 +#define ODM_REG_T_METER_11N 0x24 +#define ODM_REG_RF_25_11N 0x25 +#define ODM_REG_RF_26_11N 0x26 +#define ODM_REG_RF_27_11N 0x27 +#define ODM_REG_RF_2B_11N 0x2B +#define ODM_REG_RF_2C_11N 0x2C +#define ODM_REG_RXRF_A3_11N 0x3C #define ODM_REG_T_METER_92D_11N 0x42 #define ODM_REG_T_METER_88E_11N 0x42 -/* 2 BB REG LIST - * PAGE 8 */ -#define ODM_REG_BB_CTRL_11N 0x800 -#define ODM_REG_RF_PIN_11N 0x804 -#define ODM_REG_PSD_CTRL_11N 0x808 +/* @2 BB REG LIST + * PAGE 8 + */ +#define ODM_REG_BB_CTRL_11N 0x800 +#define ODM_REG_RF_PIN_11N 0x804 +#define ODM_REG_PSD_CTRL_11N 0x808 #define ODM_REG_TX_ANT_CTRL_11N 0x80C #define ODM_REG_BB_PWR_SAV5_11N 0x818 #define ODM_REG_CCK_RPT_FORMAT_11N 0x824 -#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C -#define ODM_REG_RX_DEFUALT_A_11N 0x858 -#define ODM_REG_RX_DEFUALT_B_11N 0x85A +#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C +#define ODM_REG_RX_DEFAULT_A_11N 0x858 +#define ODM_REG_RX_DEFAULT_B_11N 0x85A #define ODM_REG_BB_PWR_SAV3_11N 0x85C #define ODM_REG_ANTSEL_CTRL_11N 0x860 #define ODM_REG_RX_ANT_CTRL_11N 0x864 -#define ODM_REG_PIN_CTRL_11N 0x870 +#define ODM_REG_PIN_CTRL_11N 0x870 #define ODM_REG_BB_PWR_SAV1_11N 0x874 #define ODM_REG_ANTSEL_PATH_11N 0x878 #define ODM_REG_BB_3WIRE_11N 0x88C -#define ODM_REG_SC_CNT_11N 0x8C4 -#define ODM_REG_PSD_DATA_11N 0x8B4 +#define ODM_REG_SC_CNT_11N 0x8C4 +#define ODM_REG_PSD_DATA_11N 0x8B4 #define ODM_REG_CCX_PERIOD_11N 0x894 #define ODM_REG_NHM_TH9_TH10_11N 0x890 -#define ODM_REG_CLM_11N 0x890 +#define ODM_REG_CLM_11N 0x890 #define ODM_REG_NHM_TH3_TO_TH0_11N 0x898 #define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c -#define ODM_REG_NHM_TH8_11N 0xe28 +#define ODM_REG_NHM_TH8_11N 0xe28 #define ODM_REG_CLM_READY_11N 0x8b4 #define ODM_REG_CLM_RESULT_11N 0x8d0 -#define ODM_REG_NHM_CNT_11N 0x8d8 +#define ODM_REG_NHM_CNT_11N 0x8d8 -/* For struct _ACS_, Jeffery, 2014-12-26 */ +/* @For struct acs_info, Jeffery, 2014-12-26 */ #define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc #define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 -#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4 +#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4 /* PAGE 9 */ #define ODM_REG_BB_CTRL_PAGE9_11N 0x900 -#define ODM_REG_DBG_RPT_11N 0x908 +#define ODM_REG_DBG_RPT_11N 0x908 #define ODM_REG_BB_TX_PATH_11N 0x90c #define ODM_REG_ANT_MAPPING1_11N 0x914 #define ODM_REG_ANT_MAPPING2_11N 0x918 -#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 +#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 #define ODM_REG_RX_DFIR_MOD_97F 0x948 +#define ODM_REG_SOML_97F 0x998 /* PAGE A */ -#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 +#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 #define ODM_REG_CCK_ANT_SEL_11N 0xA04 -#define ODM_REG_CCK_CCA_11N 0xA0A -#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C -#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 -#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 -#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 -#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 -#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 -#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 -#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 -#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 -#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 -#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 +#define ODM_REG_CCK_CCA_11N 0xA0A +#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C +#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 +#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 +#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 +#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 +#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 +#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 +#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 +#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 +#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 +#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 #define ODM_REG_CCK_FA_RST_11N 0xA2C #define ODM_REG_CCK_FA_MSB_11N 0xA58 #define ODM_REG_CCK_FA_LSB_11N 0xA5C @@ -107,60 +113,60 @@ #define ODM_REG_PATH_SWITCH_11N 0xB30 #define ODM_REG_RSSI_CTRL_11N 0xB38 #define ODM_REG_CONFIG_ANTA_11N 0xB68 -#define ODM_REG_RSSI_BT_11N 0xB9C -#define ODM_REG_RXCK_RFMOD 0xBB0 +#define ODM_REG_RSSI_BT_11N 0xB9C +#define ODM_REG_RXCK_RFMOD 0xBB0 #define ODM_REG_EDCCA_DCNF_97F 0xBC0 /* PAGE C */ #define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 #define ODM_REG_BB_RX_PATH_11N 0xC04 -#define ODM_REG_TRMUX_11N 0xC08 +#define ODM_REG_TRMUX_11N 0xC08 #define ODM_REG_OFDM_FA_RSTC_11N 0xC0C -#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10 +#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10 #define ODM_REG_RXIQI_MATRIX_11N 0xC14 -#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C -#define ODM_REG_IGI_A_11N 0xC50 +#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C +#define ODM_REG_IGI_A_11N 0xC50 #define ODM_REG_ANTDIV_PARA2_11N 0xC54 -#define ODM_REG_IGI_B_11N 0xC58 +#define ODM_REG_IGI_B_11N 0xC58 #define ODM_REG_ANTDIV_PARA3_11N 0xC5C -#define ODM_REG_L1SBD_PD_CH_11N 0XC6C -#define ODM_REG_BB_PWR_SAV2_11N 0xC70 +#define ODM_REG_L1SBD_PD_CH_11N 0XC6C +#define ODM_REG_BB_PWR_SAV2_11N 0xC70 #define ODM_REG_BB_AGC_SET_2_11N 0xc74 -#define ODM_REG_RX_OFF_11N 0xC7C +#define ODM_REG_RX_OFF_11N 0xC7C #define ODM_REG_TXIQK_MATRIXA_11N 0xC80 #define ODM_REG_TXIQK_MATRIXB_11N 0xC88 -#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 -#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C -#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 +#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 +#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C +#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 #define ODM_REG_ANTDIV_PARA1_11N 0xCA4 -#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4 +#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4 #define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 /* PAGE D */ #define ODM_REG_OFDM_FA_RSTD_11N 0xD00 #define ODM_REG_BB_RX_ANT_11N 0xD04 -#define ODM_REG_BB_ATC_11N 0xD2C +#define ODM_REG_BB_ATC_11N 0xD2C #define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 #define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 #define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 -#define ODM_REG_RPT_11N 0xDF4 +#define ODM_REG_RPT_11N 0xDF4 /* PAGE E */ #define ODM_REG_TXAGC_A_6_18_11N 0xE00 #define ODM_REG_TXAGC_A_24_54_11N 0xE04 -#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 +#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 #define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 #define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 -#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 -#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C +#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 +#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C #define ODM_REG_EDCCA_DCNF_11N 0xE24 -#define ODM_REG_TAP_UPD_97F 0xE24 +#define ODM_REG_TAP_UPD_97F 0xE24 #define ODM_REG_FPGA0_IQK_11N 0xE28 -#define ODM_REG_PAGE_B1_97F 0xE28 +#define ODM_REG_PAGE_B1_97F 0xE28 #define ODM_REG_TXIQK_TONE_A_11N 0xE30 #define ODM_REG_RXIQK_TONE_A_11N 0xE34 #define ODM_REG_TXIQK_PI_A_11N 0xE38 #define ODM_REG_RXIQK_PI_A_11N 0xE3C -#define ODM_REG_TXIQK_11N 0xE40 -#define ODM_REG_RXIQK_11N 0xE44 +#define ODM_REG_TXIQK_11N 0xE40 +#define ODM_REG_RXIQK_11N 0xE44 #define ODM_REG_IQK_AGC_PTS_11N 0xE48 #define ODM_REG_IQK_AGC_RSP_11N 0xE4C #define ODM_REG_BLUETOOTH_11N 0xE6C @@ -169,44 +175,45 @@ #define ODM_REG_TX_CCK_BBON_11N 0xE78 #define ODM_REG_OFDM_RFON_11N 0xE7C #define ODM_REG_OFDM_BBON_11N 0xE80 -#define ODM_REG_TX2RX_11N 0xE84 -#define ODM_REG_TX2TX_11N 0xE88 -#define ODM_REG_RX_CCK_11N 0xE8C -#define ODM_REG_RX_OFDM_11N 0xED0 +#define ODM_REG_TX2RX_11N 0xE84 +#define ODM_REG_TX2TX_11N 0xE88 +#define ODM_REG_RX_CCK_11N 0xE8C +#define ODM_REG_RX_OFDM_11N 0xED0 #define ODM_REG_RX_WAIT_RIFS_11N 0xED4 -#define ODM_REG_RX2RX_11N 0xED8 -#define ODM_REG_STANDBY_11N 0xEDC -#define ODM_REG_SLEEP_11N 0xEE0 +#define ODM_REG_RX2RX_11N 0xED8 +#define ODM_REG_STANDBY_11N 0xEDC +#define ODM_REG_SLEEP_11N 0xEE0 #define ODM_REG_PMPD_ANAEN_11N 0xEEC /* PAGE F */ #define ODM_REG_PAGE_F_RST_11N 0xF14 -#define ODM_REG_IGI_C_11N 0xF84 -#define ODM_REG_IGI_D_11N 0xF88 -#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84 +#define ODM_REG_IGI_C_11N 0xF84 +#define ODM_REG_IGI_D_11N 0xF88 +#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84 #define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88 #define ODM_REG_HT_CRC32_CNT_11N 0xF90 #define ODM_REG_OFDM_CRC32_CNT_11N 0xF94 +#define ODM_REG_HT_CRC32_CNT_11N_AGG 0xFB8 -/* 2 MAC REG LIST */ -#define ODM_REG_BB_RST_11N 0x02 +/* @2 MAC REG LIST */ +#define ODM_REG_BB_RST_11N 0x02 #define ODM_REG_ANTSEL_PIN_11N 0x4C #define ODM_REG_EARLY_MODE_11N 0x4D0 #define ODM_REG_RSSI_MONITOR_11N 0x4FE -#define ODM_REG_EDCA_VO_11N 0x500 -#define ODM_REG_EDCA_VI_11N 0x504 -#define ODM_REG_EDCA_BE_11N 0x508 -#define ODM_REG_EDCA_BK_11N 0x50C -#define ODM_REG_TXPAUSE_11N 0x522 -#define ODM_REG_RESP_TX_11N 0x6D8 -#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 -#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 +#define ODM_REG_EDCA_VO_11N 0x500 +#define ODM_REG_EDCA_VI_11N 0x504 +#define ODM_REG_EDCA_BE_11N 0x508 +#define ODM_REG_EDCA_BK_11N 0x50C +#define ODM_REG_TXPAUSE_11N 0x522 +#define ODM_REG_RESP_TX_11N 0x6D8 +#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 +#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 -/* DIG Related */ -#define ODM_BIT_IGI_11N 0x0000007F +/* @DIG Related */ +#define ODM_BIT_IGI_11N 0x0000007F #define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9) #define ODM_BIT_BB_RX_PATH_11N 0xF #define ODM_BIT_BB_TX_PATH_11N 0xF -#define ODM_BIT_BB_ATC_11N BIT(11) - +#define ODM_BIT_BB_ATC_11N BIT(11) #endif + diff --git a/hal/phydm/phydm_regtable.h b/hal/phydm/phydm_regtable.h new file mode 100644 index 0000000..cad786c --- /dev/null +++ b/hal/phydm/phydm_regtable.h @@ -0,0 +1,725 @@ +#define R_0x0 0x0 +#define R_0x00 0x00 +#define R_0x0106 0x0106 +#define R_0x0140 0x0140 +#define R_0x0144 0x0144 +#define R_0x0148 0x0148 +#define R_0x040 0x040 +#define R_0x10 0x10 +#define R_0x100 0x100 +#define R_0x1038 0x1038 +#define R_0x103c 0x103c +#define R_0x1040 0x1040 +#define R_0x1048 0x1048 +#define R_0x1080 0x1080 +#define R_0x14c0 0x14c0 +#define R_0x14c4 0x14c4 +#define R_0x14c8 0x14c8 +#define R_0x14cc 0x14cc +#define R_0x1518 0x1518 +#define R_0x1684 0x1684 +#define R_0x1688 0x1688 +#define R_0x168c 0x168c +#define R_0x1700 0x1700 +#define R_0x1704 0x1704 +#define R_0x1800 0x1800 +#define R_0x1830 0x1830 +#define R_0x1838 0x1838 +#define R_0x183c 0x183c +#define R_0x1840 0x1840 +#define R_0x1844 0x1844 +#define R_0x1848 0x1848 +#define R_0x186c 0x186c +#define R_0x1870 0x1870 +#define R_0x1884 0x1884 +#define R_0x188c 0x188c +#define R_0x1894 0x1894 +#define R_0x18a0 0x18a0 +#define R_0x18a4 0x18a4 +#define R_0x18ac 0x18ac +#define R_0x1900 0x1900 +#define R_0x1904 0x1904 +#define R_0x1908 0x1908 +#define R_0x1918 0x1918 +#define R_0x191c 0x191c +#define R_0x1928 0x1928 +#define R_0x1940 0x1940 +#define R_0x1944 0x1944 +#define R_0x1950 0x1950 +#define R_0x1954 0x1954 +#define R_0x195c 0x195c +#define R_0x1970 0x1970 +#define R_0x1984 0x1984 +#define R_0x1988 0x1988 +#define R_0x198c 0x198c +#define R_0x1990 0x1990 +#define R_0x1991 0x1991 +#define R_0x1998 0x1998 +#define R_0x19a8 0x19a8 +#define R_0x19d4 0x19d4 +#define R_0x19d8 0x19d8 +#define R_0x19e0 0x19e0 +#define R_0x19f0 0x19f0 +#define R_0x19f8 0x19f8 +#define R_0x1a00 0x1a00 +#define R_0x1a04 0x1a04 +#define R_0x1a14 0x1a14 +#define R_0x1a24 0x1a24 +#define R_0x1a28 0x1a28 +#define R_0x1a2c 0x1a2c +#define R_0x1a5c 0x1a5c +#define R_0x1a70 0x1a70 +#define R_0x1a80 0x1a80 +#define R_0x1a84 0x1a84 +#define R_0x1a8c 0x1a8c +#define R_0x1a94 0x1a94 +#define R_0x1a9c 0x1a9c +#define R_0x1aac 0x1aac +#define R_0x1abc 0x1abc +#define R_0x1ac0 0x1ac0 +#define R_0x1ac8 0x1ac8 +#define R_0x1acc 0x1acc +#define R_0x1ad0 0x1ad0 +#define R_0x1ad4 0x1ad4 +#define R_0x1b00 0x1b00 +#define R_0x1b08 0x1b08 +#define R_0x1b0c 0x1b0c +#define R_0x1b20 0x1b20 +#define R_0x1b2c 0x1b2c +#define R_0x1b38 0x1b38 +#define R_0x1b3c 0x1b3c +#define R_0x1b40 0x1b40 +#define R_0x1b44 0x1b44 +#define R_0x1b48 0x1b48 +#define R_0x1b4c 0x1b4c +#define R_0x1b50 0x1b50 +#define R_0x1b54 0x1b54 +#define R_0x1b58 0x1b58 +#define R_0x1b5c 0x1b5c +#define R_0x1b60 0x1b60 +#define R_0x1b64 0x1b64 +#define R_0x1b68 0x1b68 +#define R_0x1b6c 0x1b6c +#define R_0x1b70 0x1b70 +#define R_0x1b74 0x1b74 +#define R_0x1b78 0x1b78 +#define R_0x1b7c 0x1b7c +#define R_0x1b80 0x1b80 +#define R_0x1b8c 0x1b8c +#define R_0x1b90 0x1b90 +#define R_0x1b92 0x1b92 +#define R_0x1b94 0x1b94 +#define R_0x1b98 0x1b98 +#define R_0x1b9c 0x1b9c +#define R_0x1ba0 0x1ba0 +#define R_0x1ba4 0x1ba4 +#define R_0x1ba8 0x1ba8 +#define R_0x1bac 0x1bac +#define R_0x1bb0 0x1bb0 +#define R_0x1bb4 0x1bb4 +#define R_0x1bb8 0x1bb8 +#define R_0x1bbc 0x1bbc +#define R_0x1bc8 0x1bc8 +#define R_0x1bcc 0x1bcc +#define R_0x1bd0 0x1bd0 +#define R_0x1bd4 0x1bd4 +#define R_0x1bd8 0x1bd8 +#define R_0x1bdc 0x1bdc +#define R_0x1bf0 0x1bf0 +#define R_0x1bfc 0x1bfc +#define R_0x1c28 0x1c28 +#define R_0x1c2c 0x1c2c +#define R_0x1c30 0x1c30 +#define R_0x1c38 0x1c38 +#define R_0x1c3c 0x1c3c +#define R_0x1c68 0x1c68 +#define R_0x1c74 0x1c74 +#define R_0x1c78 0x1c78 +#define R_0x1c7c 0x1c7c +#define R_0x1c80 0x1c80 +#define R_0x1c90 0x1c90 +#define R_0x1c94 0x1c94 +#define R_0x1c98 0x1c98 +#define R_0x1c9c 0x1c9c +#define R_0x1ca0 0x1ca0 +#define R_0x1ca4 0x1ca4 +#define R_0x1cb8 0x1cb8 +#define R_0x1cd0 0x1cd0 +#define R_0x1ce4 0x1ce4 +#define R_0x1ce8 0x1ce8 +#define R_0x1cec 0x1cec +#define R_0x1cf0 0x1cf0 +#define R_0x1cf4 0x1cf4 +#define R_0x1cf8 0x1cf8 +#define R_0x1d08 0x1d08 +#define R_0x1d0c 0x1d0c +#define R_0x1d30 0x1d30 +#define R_0x1d44 0x1d44 +#define R_0x1d48 0x1d48 +#define R_0x1d60 0x1d60 +#define R_0x1d6c 0x1d6c +#define R_0x1d70 0x1d70 +#define R_0x1d94 0x1d94 +#define R_0x1d9c 0x1d9c +#define R_0x1da4 0x1da4 +#define R_0x1da8 0x1da8 +#define R_0x1e14 0x1e14 +#define R_0x1e18 0x1e18 +#define R_0x1e24 0x1e24 +#define R_0x1e2c 0x1e2c +#define R_0x1e30 0x1e30 +#define R_0x1e40 0x1e40 +#define R_0x1e44 0x1e44 +#define R_0x1e48 0x1e48 +#define R_0x1e5c 0x1e5c +#define R_0x1e60 0x1e60 +#define R_0x1e64 0x1e64 +#define R_0x1e68 0x1e68 +#define R_0x1e6c 0x1e6c +#define R_0x1e70 0x1e70 +#define R_0x1ea4 0x1ea4 +#define R_0x1eb4 0x1eb4 +#define R_0x1ee8 0x1ee8 +#define R_0x24 0x24 +#define R_0x28 0x28 +#define R_0x2c 0x2c +#define R_0x2c04 0x2c04 +#define R_0x2c08 0x2c08 +#define R_0x2c0c 0x2c0c +#define R_0x2c10 0x2c10 +#define R_0x2c14 0x2c14 +#define R_0x2c20 0x2c20 +#define R_0x2c2c 0x2c2c +#define R_0x2c30 0x2c30 +#define R_0x2c34 0x2c34 +#define R_0x2d00 0x2d00 +#define R_0x2d04 0x2d04 +#define R_0x2d08 0x2d08 +#define R_0x2d0c 0x2d0c +#define R_0x2d10 0x2d10 +#define R_0x2d20 0x2d20 +#define R_0x2d38 0x2d38 +#define R_0x2d40 0x2d40 +#define R_0x2d44 0x2d44 +#define R_0x2d48 0x2d48 +#define R_0x2d4c 0x2d4c +#define R_0x2d88 0x2d88 +#define R_0x2dbc 0x2dbc +#define R_0x2de0 0x2de0 +#define R_0x2de4 0x2de4 +#define R_0x2de8 0x2de8 +#define R_0x300 0x300 +#define R_0x38 0x38 +#define R_0x40 0x40 +#define R_0x4000 0x4000 +#define R_0x4008 0x4008 +#define R_0x4018 0x4018 +#define R_0x401c 0x401c +#define R_0x4028 0x4028 +#define R_0x4040 0x4040 +#define R_0x4044 0x4044 +#define R_0x4100 0x4100 +#define R_0x4130 0x4130 +#define R_0x413c 0x413c +#define R_0x4140 0x4140 +#define R_0x4144 0x4144 +#define R_0x4148 0x4148 +#define R_0x41a0 0x41a0 +#define R_0x41a4 0x41a4 +#define R_0x41ac 0x41ac +#define R_0x42 0x42 +#define R_0x430 0x430 +#define R_0x434 0x434 +#define R_0x44 0x44 +#define R_0x444 0x444 +#define R_0x448 0x448 +#define R_0x450 0x450 +#define R_0x454 0x454 +#define R_0x49c 0x49c +#define R_0x4a0 0x4a0 +#define R_0x4a4 0x4a4 +#define R_0x4a8 0x4a8 +#define R_0x4c 0x4c +#define R_0x4c8 0x4c8 +#define R_0x4cc 0x4cc +#define R_0x5000 0x5000 +#define R_0x5008 0x5008 +#define R_0x5018 0x5018 +#define R_0x501c 0x501c +#define R_0x5028 0x5028 +#define R_0x5040 0x5040 +#define R_0x5044 0x5044 +#define R_0x5100 0x5100 +#define R_0x5108 0x5108 +#define R_0x5118 0x5118 +#define R_0x511c 0x511c +#define R_0x5128 0x5128 +#define R_0x5140 0x5140 +#define R_0x5144 0x5144 +#define R_0x520 0x520 +#define R_0x5200 0x5200 +#define R_0x522 0x522 +#define R_0x5230 0x5230 +#define R_0x523c 0x523c +#define R_0x5240 0x5240 +#define R_0x5244 0x5244 +#define R_0x5248 0x5248 +#define R_0x52a0 0x52a0 +#define R_0x52a4 0x52a4 +#define R_0x52ac 0x52ac +#define R_0x5300 0x5300 +#define R_0x5330 0x5330 +#define R_0x533c 0x533c +#define R_0x5340 0x5340 +#define R_0x5344 0x5344 +#define R_0x5348 0x5348 +#define R_0x53a0 0x53a0 +#define R_0x53a4 0x53a4 +#define R_0x53ac 0x53ac +#define R_0x550 0x550 +#define R_0x551 0x551 +#define R_0x568 0x568 +#define R_0x588 0x588 +#define R_0x60 0x60 +#define R_0x604 0x604 +#define R_0x608 0x608 +#define R_0x60f 0x60f +#define R_0x64 0x64 +#define R_0x66 0x66 +#define R_0x660 0x660 +#define R_0x668 0x668 +#define R_0x688 0x688 +#define R_0x6a0 0x6a0 +#define R_0x6d8 0x6d8 +#define R_0x6dc 0x6dc +#define R_0x70 0x70 +#define R_0x74 0x74 +#define R_0x764 0x764 +#define R_0x7b0 0x7b0 +#define R_0x7b4 0x7b4 +#define R_0x7c0 0x7c0 +#define R_0x7c4 0x7c4 +#define R_0x7c8 0x7c8 +#define R_0x7cc 0x7cc +#define R_0x7f0 0x7f0 +#define R_0x7f4 0x7f4 +#define R_0x7f8 0x7f8 +#define R_0x7fc 0x7fc +#define R_0x800 0x800 +#define R_0x804 0x804 +#define R_0x808 0x808 +#define R_0x80c 0x80c +#define R_0x810 0x810 +#define R_0x814 0x814 +#define R_0x818 0x818 +#define R_0x81c 0x81c +#define R_0x820 0x820 +#define R_0x824 0x824 +#define R_0x828 0x828 +#define R_0x82c 0x82c +#define R_0x830 0x830 +#define R_0x834 0x834 +#define R_0x838 0x838 +#define R_0x83c 0x83c +#define R_0x840 0x840 +#define R_0x844 0x840 +#define R_0x848 0x848 +#define R_0x84c 0x84c +#define R_0x850 0x850 +#define R_0x854 0x854 +#define R_0x858 0x858 +#define R_0x85c 0x85c +#define R_0x860 0x860 +#define R_0x864 0x864 +#define R_0x868 0x868 +#define R_0x86c 0x86c +#define R_0x870 0x870 +#define R_0x874 0x874 +#define R_0x878 0x878 +#define R_0x87c 0x87c +#define R_0x880 0x880 +#define R_0x884 0x884 +#define R_0x888 0x888 +#define R_0x88c 0x88c +#define R_0x890 0x890 +#define R_0x894 0x894 +#define R_0x898 0x898 +#define R_0x89c 0x89c +#define R_0x8a0 0x8a0 +#define R_0x8a4 0x8a4 +#define R_0x8ac 0x8ac +#define R_0x8b4 0x8b4 +#define R_0x8c0 0x8c0 +#define R_0x8c4 0x8c4 +#define R_0x8c8 0x8c8 +#define R_0x8cc 0x8cc +#define R_0x8d0 0x8d0 +#define R_0x8d4 0x8d4 +#define R_0x8d8 0x8d8 +#define R_0x8dc 0x8dc +#define R_0x8f0 0x8f0 +#define R_0x8f8 0x8f8 +#define R_0x8fc 0x8fc +#define R_0x900 0x900 +#define R_0x908 0x908 +#define R_0x90c 0x90c +#define R_0x910 0x910 +#define R_0x914 0x914 +#define R_0x918 0x918 +#define R_0x91c 0x91c +#define R_0x920 0x920 +#define R_0x924 0x924 +#define R_0x92c 0x92c +#define R_0x930 0x930 +#define R_0x934 0x934 +#define R_0x938 0x938 +#define R_0x93c 0x93c +#define R_0x940 0x940 +#define R_0x944 0x944 +#define R_0x948 0x948 +#define R_0x94c 0x94c +#define R_0x950 0x950 +#define R_0x954 0x954 +#define R_0x958 0x958 +#define R_0x95c 0x95c +#define R_0x960 0x960 +#define R_0x964 0x964 +#define R_0x968 0x968 +#define R_0x970 0x970 +#define R_0x974 0x974 +#define R_0x978 0x978 +#define R_0x97c 0x97c +#define R_0x98c 0x98c +#define R_0x990 0x990 +#define R_0x994 0x994 +#define R_0x998 0x998 +#define R_0x9a0 0x9a0 +#define R_0x9a4 0x9a4 +#define R_0x9ac 0x9ac +#define R_0x9b0 0x9b0 +#define R_0x9b4 0x9b4 +#define R_0x9b8 0x9b8 +#define R_0x9cc 0x9cc +#define R_0x9d0 0x9d0 +#define R_0x9e4 0x9e4 +#define R_0xa0 0xa0 +#define R_0xa00 0xa00 +#define R_0xa04 0xa04 +#define R_0xa08 0xa08 +#define R_0xa0a 0xa0a +#define R_0xa0c 0xa0c +#define R_0xa10 0xa10 +#define R_0xa14 0xa14 +#define R_0xa20 0xa20 +#define R_0xa24 0xa24 +#define R_0xa28 0xa28 +#define R_0xa2c 0xa2c +#define R_0xa58 0xa58 +#define R_0xa70 0xa70 +#define R_0xa74 0xa74 +#define R_0xa78 0xa78 +#define R_0xa8 0xa8 +#define R_0xa80 0xa80 +#define R_0xa84 0xa84 +#define R_0xa98 0xa98 +#define R_0xa9c 0xa9c +#define R_0xaa8 0xaa8 +#define R_0xaac 0xaac +#define R_0xab4 0xab4 +#define R_0xabc 0xabc +#define R_0xac8 0xac8 +#define R_0xacc 0xacc +#define R_0xad0 0xad0 +#define R_0xb0 0xb0 +#define R_0xb00 0xb00 +#define R_0xb04 0xb04 +#define R_0xb07 0xb07 +#define R_0xb08 0xb08 +#define R_0xb0c 0xb0c +#define R_0xb10 0xb10 +#define R_0xb14 0xb14 +#define R_0xb18 0xb18 +#define R_0xb1c 0xb1c +#define R_0xb20 0xb20 +#define R_0xb24 0xb24 +#define R_0xb28 0xb28 +#define R_0xb2b 0xb2b +#define R_0xb2c 0xb2c +#define R_0xb30 0xb30 +#define R_0xb34 0xb34 +#define R_0xb38 0xb38 +#define R_0xb3c 0xb3c +#define R_0xb40 0xb40 +#define R_0xb44 0xb44 +#define R_0xb48 0xb48 +#define R_0xb54 0xb54 +#define R_0xb58 0xb58 +#define R_0xb60 0xb60 +#define R_0xb64 0xb64 +#define R_0xb68 0xb68 +#define R_0xb6a 0xb6a +#define R_0xb6c 0xb6c +#define R_0xb6e 0xb6e +#define R_0xb70 0xb70 +#define R_0xb74 0xb74 +#define R_0xb77 0xb77 +#define R_0xb78 0xb78 +#define R_0xb7c 0xb7c +#define R_0xb80 0xb80 +#define R_0xb84 0xb84 +#define R_0xb88 0xb88 +#define R_0xb8c 0xb8c +#define R_0xb90 0xb90 +#define R_0xb94 0xb94 +#define R_0xb98 0xb98 +#define R_0xb9b 0xb9b +#define R_0xb9c 0xb9c +#define R_0xba0 0xba0 +#define R_0xba4 0xba4 +#define R_0xba8 0xba8 +#define R_0xbac 0xbac +#define R_0xbad 0xbad +#define R_0xbc0 0xbc0 +#define R_0xbc4 0xbc4 +#define R_0xbc8 0xbc8 +#define R_0xbcc 0xbcc +#define R_0xbd8 0xbd8 +#define R_0xbdc 0xbdc +#define R_0xbe0 0xbe0 +#define R_0xbe4 0xbe4 +#define R_0xbe8 0xbe8 +#define R_0xbec 0xbec +#define R_0xbf0 0xbf0 +#define R_0xbf4 0xbf4 +#define R_0xbf8 0xbf8 +#define R_0xc00 0xc00 +#define R_0xc04 0xc04 +#define R_0xc08 0xc08 +#define R_0xc0c 0xc0c +#define R_0xc10 0xc10 +#define R_0xc14 0xc14 +#define R_0xc18 0xc18 +#define R_0xc1c 0xc1c +#define R_0xc20 0xc20 +#define R_0xc24 0xc24 +#define R_0xc30 0xc30 +#define R_0xc38 0xc38 +#define R_0xc3c 0xc3c +#define R_0xc40 0xc40 +#define R_0xc44 0xc44 +#define R_0xc4c 0xc4c +#define R_0xc50 0xc50 +#define R_0xc54 0xc54 +#define R_0xc58 0xc58 +#define R_0xc5c 0xc5c +#define R_0xc6c 0xc6c +#define R_0xc70 0xc70 +#define R_0xc74 0xc74 +#define R_0xc78 0xc78 +#define R_0xc7c 0xc7c +#define R_0xc80 0xc80 +#define R_0xc84 0xc84 +#define R_0xc88 0xc88 +#define R_0xc8c 0xc8c +#define R_0xc90 0xc90 +#define R_0xc94 0xc94 +#define R_0xc9c 0xc9c +#define R_0xca0 0xca0 +#define R_0xca4 0xca4 +#define R_0xca8 0xca8 +#define R_0xcac 0xcac +#define R_0xcb0 0xcb0 +#define R_0xcb4 0xcb4 +#define R_0xcb8 0xcb8 +#define R_0xcbc 0xcbc +#define R_0xcbd 0xcbd +#define R_0xcbe 0xcbe +#define R_0xcc4 0xcc4 +#define R_0xcc8 0xcc8 +#define R_0xccc 0xccc +#define R_0xcd0 0xcd0 +#define R_0xcd4 0xcd4 +#define R_0xcd8 0xcd8 +#define R_0xce0 0xce0 +#define R_0xce4 0xce4 +#define R_0xce8 0xce8 +#define R_0xd00 0xd00 +#define R_0xd04 0xd04 +#define R_0xd08 0xd08 +#define R_0xd0c 0xd0c +#define R_0xd10 0xd10 +#define R_0xd14 0xd14 +#define R_0xd2c 0xd2c +#define R_0xd30 0xd30 +#define R_0xd40 0xd40 +#define R_0xd44 0xd44 +#define R_0xd48 0xd48 +#define R_0xd4c 0xd4c +#define R_0xd50 0xd50 +#define R_0xd54 0xd54 +#define R_0xd5c 0xd5c +#define R_0xd6c 0xd6c +#define R_0xd7c 0xd7c +#define R_0xd80 0xd80 +#define R_0xd84 0xd84 +#define R_0xd8c 0xd8c +#define R_0xd90 0xd90 +#define R_0xd94 0xd94 +#define R_0xdac 0xdac +#define R_0xdb0 0xdb0 +#define R_0xdb4 0xdb4 +#define R_0xdb8 0xdb8 +#define R_0xdbc 0xdbc +#define R_0xdcc 0xdcc +#define R_0xdd0 0xdd0 +#define R_0xdd4 0xdd4 +#define R_0xdd8 0xdd8 +#define R_0xde0 0xde0 +#define R_0xdec 0xdec +#define R_0xdf4 0xdf4 +#define R_0xe00 0xe00 +#define R_0xe04 0xe04 +#define R_0xe08 0xe08 +#define R_0xe10 0xe10 +#define R_0xe14 0xe14 +#define R_0xe18 0xe18 +#define R_0xe1c 0xe1c +#define R_0xe20 0xe20 +#define R_0xe24 0xe24 +#define R_0xe28 0xe28 +#define R_0xe30 0xe30 +#define R_0xe34 0xe34 +#define R_0xe38 0xe38 +#define R_0xe3c 0xe3c +#define R_0xe40 0xe40 +#define R_0xe44 0xe44 +#define R_0xe48 0xe48 +#define R_0xe4c 0xe4c +#define R_0xe50 0xe50 +#define R_0xe54 0xe54 +#define R_0xe5c 0xe5c +#define R_0xe64 0xe64 +#define R_0xe6c 0xe6c +#define R_0xe70 0xe70 +#define R_0xe74 0xe74 +#define R_0xe78 0xe78 +#define R_0xe7c 0xe7c +#define R_0xe80 0xe80 +#define R_0xe84 0xe84 +#define R_0xe88 0xe88 +#define R_0xe8c 0xe8c +#define R_0xe90 0xe90 +#define R_0xe94 0xe94 +#define R_0xe98 0xe98 +#define R_0xe9c 0xe9c +#define R_0xea0 0xea0 +#define R_0xea4 0xea4 +#define R_0xea8 0xea8 +#define R_0xeac 0xeac +#define R_0xeb0 0xeb0 +#define R_0xeb4 0xeb4 +#define R_0xeb8 0xeb8 +#define R_0xebc 0xebc +#define R_0xec0 0xec0 +#define R_0xec4 0xec4 +#define R_0xec8 0xec8 +#define R_0xecc 0xecc +#define R_0xed0 0xed0 +#define R_0xed4 0xed4 +#define R_0xed8 0xed8 +#define R_0xedc 0xedc +#define R_0xee0 0xee0 +#define R_0xee8 0xee8 +#define R_0xeec 0xeec +#define R_0xf0 0xf0 +#define R_0xf04 0xf04 +#define R_0xf08 0xf08 +#define R_0xf0c 0xf0c +#define R_0xf10 0xf10 +#define R_0xf14 0xf14 +#define R_0xf20 0xf20 +#define R_0xf2c 0xf2c +#define R_0xf30 0xf30 +#define R_0xf34 0xf34 +#define R_0xf4 0xf4 +#define R_0xf44 0xf44 +#define R_0xf48 0xf48 +#define R_0xf4c 0xf4c +#define R_0xf50 0xf50 +#define R_0xf80 0xf80 +#define R_0xf84 0xf84 +#define R_0xf87 0xf87 +#define R_0xf88 0xf88 +#define R_0xf8c 0xf8c +#define R_0xf90 0xf90 +#define R_0xf94 0xf94 +#define R_0xf98 0xf98 +#define R_0xfa0 0xfa0 +#define R_0xfa4 0xfa4 +#define R_0xfb8 0xfb8 +#define R_0xfbc 0xfbc +#define R_0xfc0 0xfc0 +#define R_0xfc4 0xfc4 +#define R_0xfc8 0xfc8 +#define R_0xfcc 0xfcc +#define R_0xfd0 0xfd0 +#define R_0xff0 0xff0 +#define RF_0x0 0x0 +#define RF_0x00 0x00 +#define RF_0x08 0x08 +#define RF_0x0c 0x0c +#define RF_0x0d 0x0d +#define RF_0x1 0x1 +#define RF_0x18 0x18 +#define RF_0x1bf0 0x1bf0 +#define RF_0x2 0x2 +#define RF_0x3 0x3 +#define RF_0x30 0x30 +#define RF_0x31 0x31 +#define RF_0x32 0x32 +#define RF_0x33 0x33 +#define RF_0x35 0x35 +#define RF_0x3e 0x3e +#define RF_0x3f 0x3f +#define RF_0x4 0x4 +#define RF_0x42 0x42 +#define RF_0x43 0x43 +#define RF_0x51 0x51 +#define RF_0x52 0x52 +#define RF_0x54 0x54 +#define RF_0x55 0x55 +#define RF_0x56 0x56 +#define RF_0x58 0x58 +#define RF_0x5c 0x5c +#define RF_0x61 0x61 +#define RF_0x64 0x64 +#define RF_0x65 0x65 +#define RF_0x66 0x66 +#define RF_0x75 0x75 +#define RF_0x76 0x76 +#define RF_0x78 0x78 +#define RF_0x7f 0x7f +#define RF_0x8 0x8 +#define RF_0x80 0x80 +#define RF_0x81 0x81 +#define RF_0x86 0x86 +#define RF_0x8d 0x8d +#define RF_0x8f 0x8f +#define RF_0xae 0xae +#define RF_0xb0 0xb0 +#define RF_0xb3 0xb3 +#define RF_0xb8 0xb8 +#define RF_0xbc 0xbc +#define RF_0xbe 0xbe +#define RF_0xc4 0xc4 +#define RF_0xc9 0xc9 +#define RF_0xca 0xca +#define RF_0xcc 0xcc +#define RF_0xd 0xd +#define RF_0xdd 0xdd +#define RF_0xde 0xde +#define RF_0xdf 0xdf +#define RF_0xed 0xed +#define RF_0xee 0xee +#define RF_0xef 0xef +#define RF_0xf5 0xf5 diff --git a/hal/phydm/phydm_rssi_monitor.c b/hal/phydm/phydm_rssi_monitor.c new file mode 100644 index 0000000..0d5e417 --- /dev/null +++ b/hal/phydm/phydm_rssi_monitor.c @@ -0,0 +1,170 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_SUPPORT_RSSI_MONITOR + +void phydm_rssi_monitor_h2c(void *dm_void, u8 macid) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct ra_sta_info *ra = NULL; + #ifdef CONFIG_BEAMFORMING + struct bf_cmn_info *bf = NULL; + #endif + u8 h2c[H2C_MAX_LENGTH] = {0}; + u8 stbc_en, ldpc_en; + u8 bf_en = 0; + u8 is_rx, is_tx; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RSSI_MNTR, "[Warning] %s\n", __func__); + return; + } + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RSSI_MNTR, "MACID=%d\n", sta->mac_id); + + is_rx = (ra->txrx_state == RX_STATE) ? 1 : 0; + is_tx = (ra->txrx_state == TX_STATE) ? 1 : 0; + stbc_en = (sta->stbc_en) ? 1 : 0; + ldpc_en = (sta->ldpc_en) ? 1 : 0; + + #ifdef CONFIG_BEAMFORMING + bf = &sta->bf_info; + + if ((bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) || + (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) + bf_en = 1; + #endif + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_th_ofst=(( %s%d ))\n", + ((ra_t->ra_ofst_direc) ? "+" : "-"), ra_t->ra_th_ofst); + + h2c[0] = sta->mac_id; + h2c[1] = 0; + h2c[2] = sta->rssi_stat.rssi; + h2c[3] = is_rx | (stbc_en << 1) | + ((dm->noisy_decision & 0x1) << 2) | (bf_en << 6); + h2c[4] = (ra_t->ra_th_ofst & 0x7f) | + ((ra_t->ra_ofst_direc & 0x1) << 7); + h2c[5] = 0; + h2c[6] = 0; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "PHYDM h2c[0x42]=0x%x %x %x %x %x %x %x\n", + h2c[6], h2c[5], h2c[4], h2c[3], h2c[2], h2c[1], h2c[0]); + + #if (RTL8188E_SUPPORT) + if (dm->support_ic_type == ODM_RTL8188E) + odm_ra_set_rssi_8188e(dm, sta->mac_id, sta->rssi_stat.rssi); + else + #endif + { + odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, H2C_MAX_LENGTH, h2c); + } +} + +void phydm_calculate_rssi_min_max(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta; + s8 rssi_max_tmp = 0, rssi_min_tmp = 100; + u8 i; + u8 sta_cnt = 0; + + if (!dm->is_linked) + return; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__); + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + sta = dm->phydm_sta_info[i]; + if (is_sta_active(sta)) { + sta_cnt++; + + if (sta->rssi_stat.rssi < rssi_min_tmp) { + rssi_min_tmp = sta->rssi_stat.rssi; + dm->rssi_min_macid = i; + } + + if (sta->rssi_stat.rssi > rssi_max_tmp) { + rssi_max_tmp = sta->rssi_stat.rssi; + dm->rssi_max_macid = i; + } + + /*@[Send RSSI to FW]*/ + if (!sta->ra_info.disable_ra) + phydm_rssi_monitor_h2c(dm, i); + + if (sta_cnt == dm->number_linked_client) + break; + } + } + dm->pre_rssi_min = dm->rssi_min; + + dm->rssi_max = (u8)rssi_max_tmp; + dm->rssi_min = (u8)rssi_min_tmp; +} + +void phydm_rssi_monitor_check(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_RSSI_MONITOR)) + return; + + /*@for AP watchdog period = 1 sec*/ + if ((dm->phydm_sys_up_time % 2) == 1) + return; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__); + + phydm_calculate_rssi_min_max(dm); + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "RSSI {max, min} = {%d, %d}\n", + dm->rssi_max, dm->rssi_min); +} + +void phydm_rssi_monitor_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + + ra_tab->firstconnect = false; + dm->pre_rssi_min = 0; + dm->rssi_max = 0; + dm->rssi_min = 0; +} + +#endif diff --git a/hal/phydm/phydm_rssi_monitor.h b/hal/phydm/phydm_rssi_monitor.h new file mode 100644 index 0000000..ac997e3 --- /dev/null +++ b/hal/phydm/phydm_rssi_monitor.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_RSSI_MONITOR_H__ +#define __PHYDM_RSSI_MONITOR_H__ + +#define RSSI_MONITOR_VERSION "2.0" + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ + +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ + +void phydm_rssi_monitor_check(void *dm_void); + +void phydm_rssi_monitor_init(void *dm_void); + +#endif diff --git a/hal/phydm/phydm_smt_ant.c b/hal/phydm/phydm_smt_ant.c new file mode 100644 index 0000000..52773b8 --- /dev/null +++ b/hal/phydm/phydm_smt_ant.c @@ -0,0 +1,2253 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/******************************************************* + * when antenna test utility is on or some testing need to disable antenna diversity + * call this function to disable all ODM related mechanisms which will switch antenna. + ******************************************************/ +#if (defined(CONFIG_SMART_ANTENNA)) + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +#if (RTL8198F_SUPPORT == 1) +void phydm_smt_ant_init_98f(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = 0; + + #if 0 + odm_set_bb_reg(dm, R_0x1da4, 0x3c, 4); /*6.25*4 = 25ms*/ + odm_set_bb_reg(dm, R_0x1da4, BIT(6), 1); + odm_set_bb_reg(dm, R_0x1da4, BIT(7), 1); + #endif +} +#endif +#endif + +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) +void phydm_cumitek_smt_ant_mapping_table_8822b( + void *dm_void, + u8 *table_path_a, + u8 *table_path_b) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 path_a_0to3_idx = 0; + u32 path_b_0to3_idx = 0; + u32 path_a_4to7_idx = 0; + u32 path_b_4to7_idx = 0; + + path_a_0to3_idx = ((table_path_a[3] & 0xf) << 24) | ((table_path_a[2] & 0xf) << 16) | ((table_path_a[1] & 0xf) << 8) | (table_path_a[0] & 0xf); + + path_b_0to3_idx = ((table_path_b[3] & 0xf) << 28) | ((table_path_b[2] & 0xf) << 20) | ((table_path_b[1] & 0xf) << 12) | ((table_path_b[0] & 0xf) << 4); + + path_a_4to7_idx = ((table_path_a[7] & 0xf) << 24) | ((table_path_a[6] & 0xf) << 16) | ((table_path_a[5] & 0xf) << 8) | (table_path_a[4] & 0xf); + + path_b_4to7_idx = ((table_path_b[7] & 0xf) << 28) | ((table_path_b[6] & 0xf) << 20) | ((table_path_b[5] & 0xf) << 12) | ((table_path_b[4] & 0xf) << 4); + +#if 0 + /*PHYDM_DBG(dm, DBG_SMT_ANT, "mapping table{A, B} = {0x%x, 0x%x}\n", path_a_0to3_idx, path_b_0to3_idx);*/ +#endif + + /*pathA*/ + odm_set_bb_reg(dm, R_0xca4, MASKDWORD, path_a_0to3_idx); /*@ant map 1*/ + odm_set_bb_reg(dm, R_0xca8, MASKDWORD, path_a_4to7_idx); /*@ant map 2*/ + + /*pathB*/ + odm_set_bb_reg(dm, R_0xea4, MASKDWORD, path_b_0to3_idx); /*@ant map 1*/ + odm_set_bb_reg(dm, R_0xea8, MASKDWORD, path_b_4to7_idx); /*@ant map 2*/ +} + +void phydm_cumitek_smt_ant_init_8822b( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + u32 value32; + + PHYDM_DBG(dm, DBG_SMT_ANT, "[8822B Cumitek SmtAnt Int]\n"); + + /*@========= MAC GPIO setting =================================*/ + + /* Pin, pin_name, RFE_CTRL_NUM*/ + + /* @A0, 55, 5G_TRSW, 3*/ + /* @A1, 52, 5G_TRSW, 0*/ + /* @A2, 25, 5G_TRSW, 8*/ + + /* @B0, 16, 5G_TRSW, 4*/ + /* @B1, 13, 5G_TRSW, 11*/ + /* @B2, 24, 5G_TRSW, 9*/ + + /*@for RFE_CTRL 8 & 9*/ + odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2); + odm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0); + + /*@for RFE_CTRL 0*/ + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); + odm_set_mac_reg(dm, R_0x64, BIT(29), 1); + + /*@for RFE_CTRL 2 & 3*/ + odm_set_mac_reg(dm, R_0x4c, BIT(26), 0); + odm_set_mac_reg(dm, R_0x64, BIT(28), 1); + + /*@for RFE_CTRL 11*/ + odm_set_mac_reg(dm, R_0x40, BIT(3), 1); + + /*@0x604[25]=1 : 2bit mode for pathA&B&C&D*/ + /*@0x604[25]=0 : 3bit mode for pathA&B*/ + smtant_table->tx_desc_mode = 0; + odm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode); + + /*@========= BB RFE setting =================================*/ +#if 0 + /*path A*/ + odm_set_bb_reg(dm, R_0x1990, BIT(3), 0); /*RFE_CTRL_3*/ /*A_0*/ + odm_set_bb_reg(dm, R_0xcbc, BIT(3), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xcb0, 0xf000, 8); + + odm_set_bb_reg(dm, R_0x1990, BIT(0), 0); /*RFE_CTRL_0*/ /*A_1*/ + odm_set_bb_reg(dm, R_0xcbc, BIT(0), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xcb0, 0xf, 0x9); + + odm_set_bb_reg(dm, R_0x1990, BIT(8), 0); /*RFE_CTRL_8*/ /*A_2*/ + odm_set_bb_reg(dm, R_0xcbc, BIT(8), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xcb4, 0xf, 0xa); + + + /*path B*/ + odm_set_bb_reg(dm, R_0x1990, BIT(4), 1); /*RFE_CTRL_4*/ /*B_0*/ + odm_set_bb_reg(dm, R_0xdbc, BIT(4), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xdb0, 0xf0000, 0xb); + + odm_set_bb_reg(dm, R_0x1990, BIT(11), 1); /*RFE_CTRL_11*/ /*B_1*/ + odm_set_bb_reg(dm, R_0xdbc, BIT(11), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xdb4, 0xf000, 0xc); + + odm_set_bb_reg(dm, R_0x1990, BIT(9), 1); /*RFE_CTRL_9*/ /*B_2*/ + odm_set_bb_reg(dm, R_0xdbc, BIT(9), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xdb4, 0xf0, 0xd); +#endif + /*@========= BB SmtAnt setting =================================*/ + odm_set_mac_reg(dm, R_0x6d8, BIT(22) | BIT(21), 2); /*resp tx by register*/ + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); + odm_set_bb_reg(dm, R_0x804, BIT(4), 0); /*@lathch antsel*/ + odm_set_bb_reg(dm, R_0x818, 0xf00000, 0); /*@keep tx by rx*/ + odm_set_bb_reg(dm, R_0x900, BIT(19), 0); /*@fast train*/ + odm_set_bb_reg(dm, R_0x900, BIT(18), 1); /*@1: by TXDESC*/ + + /*pathA*/ + odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x03020100); /*@ant map 1*/ + odm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x07060504); /*@ant map 2*/ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 0); /*@keep antsel map by GNT_BT*/ + + /*pathB*/ + odm_set_bb_reg(dm, R_0xea4, MASKDWORD, 0x30201000); /*@ant map 1*/ + odm_set_bb_reg(dm, R_0xea8, MASKDWORD, 0x70605040); /*@ant map 2*/ + odm_set_bb_reg(dm, R_0xeac, BIT(9), 0); /*@keep antsel map by GNT_BT*/ +} + +void phydm_cumitek_smt_ant_init_8197f( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + u32 value32; + + PHYDM_DBG(dm, DBG_SMT_ANT, "[8197F Cumitek SmtAnt Int]\n"); + + /*@GPIO setting*/ +} + +void phydm_cumitek_smt_ant_init_8192f( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + u32 value32; + PHYDM_DBG(dm, DBG_SMT_ANT, "[8192F Cumitek SmtAnt Int]\n"); + + /*@GPIO setting*/ +} + +void phydm_cumitek_smt_tx_ant_update( + void *dm_void, + u8 tx_ant_idx_path_a, + u8 tx_ant_idx_path_b, + u32 mac_id) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Cumitek] Set TX-ANT[%d] = (( A:0x%x , B:0x%x ))\n", mac_id, + tx_ant_idx_path_a, tx_ant_idx_path_b); + + /*path-A*/ + cumi_smtant_table->tx_ant_idx[0][mac_id] = tx_ant_idx_path_a; /*@fill this value into TXDESC*/ + + /*path-B*/ + cumi_smtant_table->tx_ant_idx[1][mac_id] = tx_ant_idx_path_b; /*@fill this value into TXDESC*/ +} + +void phydm_cumitek_smt_rx_default_ant_update( + void *dm_void, + u8 rx_ant_idx_path_a, + u8 rx_ant_idx_path_b) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Cumitek] Set RX-ANT = (( A:0x%x, B:0x%x ))\n", + rx_ant_idx_path_a, rx_ant_idx_path_b); + + /*path-A*/ + if (cumi_smtant_table->rx_default_ant_idx[0] != rx_ant_idx_path_a) { + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + odm_set_bb_reg(dm, R_0xc08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_a); /*@default RX antenna*/ + odm_set_mac_reg(dm, R_0x6d8, BIT(2) | BIT(1) | BIT(0), rx_ant_idx_path_a); /*@default response TX antenna*/ + } + #endif + + #if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) { + } + #endif + + /*@jj add 20170822*/ + #if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) { + } + #endif + cumi_smtant_table->rx_default_ant_idx[0] = rx_ant_idx_path_a; + } + + /*path-B*/ + if (cumi_smtant_table->rx_default_ant_idx[1] != rx_ant_idx_path_b) { + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + odm_set_bb_reg(dm, R_0xe08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_b); /*@default antenna*/ + odm_set_mac_reg(dm, R_0x6d8, BIT(5) | BIT(4) | BIT(3), rx_ant_idx_path_b); /*@default response TX antenna*/ + } + #endif + + #if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) { + } + #endif + + /*@jj add 20170822*/ + #if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) { + } + #endif + cumi_smtant_table->rx_default_ant_idx[1] = rx_ant_idx_path_b; + } +} + +void phydm_cumitek_smt_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + u32 used = *_used; + u32 out_len = *_out_len; + char help[] = "-h"; + u32 dm_value[10] = {0}; + u8 i; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]); + + if (strcmp(input[1], help) == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {PathA rx_ant_idx} {pathB rx_ant_idx}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} {PathA tx_ant_idx} {pathB tx_ant_idx} {macid}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3} {PathA mapping table} {PathB mapping table}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{4} {txdesc_mode 0:3bit, 1:2bit}\n"); + + } else if (dm_value[0] == 1) { /*@fix rx_idle pattern*/ + + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]); + + phydm_cumitek_smt_rx_default_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "RX Ant{A, B}={%d, %d}\n", dm_value[1], dm_value[2]); + + } else if (dm_value[0] == 2) { /*@fix tx pattern*/ + + for (i = 1; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "STA[%d] TX Ant{A, B}={%d, %d}\n", dm_value[3], + dm_value[1], dm_value[2]); + phydm_cumitek_smt_tx_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2], (u8)dm_value[3]); + + } else if (dm_value[0] == 3) { + u8 table_path_a[8] = {0}; + u8 table_path_b[8] = {0}; + + for (i = 1; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set Path-AB mapping table={%d, %d}\n", dm_value[1], + dm_value[2]); + + for (i = 0; i < 8; i++) { + table_path_a[i] = (u8)((dm_value[1] >> (4 * i)) & 0xf); + table_path_b[i] = (u8)((dm_value[2] >> (4 * i)) & 0xf); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Ant_Table_A[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n", + table_path_a[7], table_path_a[6], table_path_a[5], + table_path_a[4], table_path_a[3], table_path_a[2], + table_path_a[1], table_path_a[0]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Ant_Table_B[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n", + table_path_b[7], table_path_b[6], table_path_b[5], + table_path_b[4], table_path_b[3], table_path_b[2], + table_path_b[1], table_path_b[0]); + + phydm_cumitek_smt_ant_mapping_table_8822b(dm, &table_path_a[0], &table_path_b[0]); + + } else if (dm_value[0] == 4) { + smtant_table->tx_desc_mode = (u8)dm_value[1]; + odm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode); + } + *_used = used; + *_out_len = out_len; +} + +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA)) +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + +#if (RTL8822B_SUPPORT == 1) +void phydm_hl_smart_ant_type2_init_8822b( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 j; + u8 rfu_codeword_table_init_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = { + {1, 1}, /*@0*/ + {1, 2}, + {2, 1}, + {2, 2}, + {4, 0}, + {5, 0}, + {6, 0}, + {7, 0}, + {8, 0}, /*@8*/ + {9, 0}, + {0xa, 0}, + {0xb, 0}, + {0xc, 0}, + {0xd, 0}, + {0xe, 0}, + {0xf, 0}}; + u8 rfu_codeword_table_init_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = { +#if 1 + {9, 1}, /*@0*/ + {9, 9}, + {1, 9}, + {9, 6}, + {2, 1}, + {2, 9}, + {9, 2}, + {2, 2}, /*@8*/ + {6, 1}, + {6, 9}, + {2, 9}, + {2, 2}, + {6, 2}, + {6, 6}, + {2, 6}, + {1, 1} +#else + {1, 1}, /*@0*/ + {9, 1}, + {9, 9}, + {1, 9}, + {1, 2}, + {9, 2}, + {9, 6}, + {1, 6}, + {2, 1}, /*@8*/ + {6, 1}, + {6, 9}, + {2, 9}, + {2, 2}, + {6, 2}, + {6, 6}, + {2, 6} +#endif + }; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***RTK 8822B SmartAnt_Init: Hong-Bo SmrtAnt Type2]\n"); + + /* @---------------------------------------- */ + /* @GPIO 0-1 for Beam control */ + /* reg0x66[2:0]=0 */ + /* reg0x44[25:24] = 0 */ + /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ + /* reg0x44[15:8] output_value for P_GPIO[7:0] */ + /* reg0x40[1:0] = 0 GPIO function */ + /* @------------------------------------------ */ + + odm_move_memory(dm, sat_tab->rfu_codeword_table_2g, rfu_codeword_table_init_2g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); + odm_move_memory(dm, sat_tab->rfu_codeword_table_5g, rfu_codeword_table_init_5g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); + + /*@GPIO setting*/ + odm_set_mac_reg(dm, R_0x64, (BIT(18) | BIT(17) | BIT(16)), 0); + odm_set_mac_reg(dm, R_0x44, BIT(25) | BIT(24), 0); /*@config P_GPIO[3:2] to data port*/ + odm_set_mac_reg(dm, R_0x44, BIT(17) | BIT(16), 0x3); /*@enable_output for P_GPIO[3:2]*/ +#if 0 + /*odm_set_mac_reg(dm, R_0x44, BIT(9)|BIT(8), 0);*/ /*P_GPIO[3:2] output value*/ +#endif + odm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/ + + /*@Hong_lin smart antenna HW setting*/ + sat_tab->rfu_protocol_type = 2; + sat_tab->rfu_protocol_delay_time = 45; + + sat_tab->rfu_codeword_total_bit_num = 16; /*@max=32bit*/ + sat_tab->rfu_each_ant_bit_num = 4; + + sat_tab->total_beam_set_num = 4; + sat_tab->total_beam_set_num_2g = 4; + sat_tab->total_beam_set_num_5g = 8; + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + sat_tab->latch_time = 100; /*@mu sec*/ +#elif DEV_BUS_TYPE == RT_USB_INTERFACE + sat_tab->latch_time = 100; /*@mu sec*/ +#endif + sat_tab->pkt_skip_statistic_en = 0; + + sat_tab->ant_num = 2; + sat_tab->ant_num_total = MAX_PATH_NUM_8822B; + sat_tab->first_train_ant = MAIN_ANT; + + sat_tab->fix_beam_pattern_en = 0; + sat_tab->decision_holding_period = 0; + + /*@beam training setting*/ + sat_tab->pkt_counter = 0; + sat_tab->per_beam_training_pkt_num = 10; + + /*set default beam*/ + sat_tab->fast_training_beam_num = 0; + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + + for (j = 0; j < SUPPORT_BEAM_SET_PATTERN_NUM; j++) { + sat_tab->beam_set_avg_rssi_pre[j] = 0; + sat_tab->beam_set_train_val_diff[j] = 0; + sat_tab->beam_set_train_cnt[j] = 0; + } + phydm_set_rfu_beam_pattern_type2(dm); + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; +} +#endif + +u32 phydm_construct_hb_rfu_codeword_type2( + void *dm_void, + u32 beam_set_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 sync_codeword = 0x7f; + u32 codeword = 0; + u32 data_tmp = 0; + u32 i; + + for (i = 0; i < sat_tab->ant_num_total; i++) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[beam_set_idx][i]; + else + data_tmp = sat_tab->rfu_codeword_table_2g[beam_set_idx][i]; + + codeword |= (data_tmp << (i * sat_tab->rfu_each_ant_bit_num)); + } + + codeword = (codeword << 8) | sync_codeword; + + return codeword; +} + +void phydm_update_beam_pattern_type2( + void *dm_void, + u32 codeword, + u32 codeword_length) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u8 i; + boolean beam_ctrl_signal; + u32 one = 0x1; + u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; + u8 devide_num = 4; + + PHYDM_DBG(dm, DBG_ANT_DIV, "Set codeword = ((0x%x))\n", codeword); + + reg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD); + reg44_tmp_p = reg44_ori; +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/ +#endif + + /*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/ + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); + + #if 1 + if (dm->debug_components & DBG_ANT_DIV) { + if (i == (codeword_length - 1)) + pr_debug("%d ]\n", beam_ctrl_signal); + else if (i == 0) + pr_debug("Start sending codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); + else if ((i % devide_num) == (devide_num - 1)) + pr_debug("%d | ", beam_ctrl_signal); + else + pr_debug("%d ", beam_ctrl_signal); + } + #endif + + if (dm->support_ic_type == ODM_RTL8821) { + #if (RTL8821A_SUPPORT == 1) + reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/ + reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); + reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/ +#endif + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n); + #endif + } + #if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) { + if (sat_tab->rfu_protocol_type == 2) { + reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/ + reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/ + + reg44_tmp_p |= (beam_ctrl_signal << 8); + + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(sat_tab->rfu_protocol_delay_time); +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/ +#endif + + } else { + reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/ + reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); + reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */ +#endif + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n); + ODM_delay_us(10); + } + } + #endif + } +} + +void phydm_update_rx_idle_beam_type2( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 i; + + sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->rx_idle_beam_set_idx); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-Beam ] BeamSet idx = ((%d))\n", + sat_tab->rx_idle_beam_set_idx); + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); +#else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +#if 0 + /*odm_stall_execution(1);*/ +#endif +#endif + + sat_tab->pre_codeword = sat_tab->update_beam_codeword; +} + +void phydm_hl_smt_ant_dbg_type2( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 used = *_used; + u32 out_len = *_out_len; + u32 one = 0x1; + u32 codeword_length = sat_tab->rfu_codeword_total_bit_num; + u32 beam_ctrl_signal, i; + u8 devide_num = 4; + char help[] = "-h"; + u32 dm_value[10] = {0}; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]); + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]); + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &dm_value[3]); + PHYDM_SSCANF(input[5], DCMD_DECIMAL, &dm_value[4]); + + if (strcmp(input[1], help) == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + " 1 {fix_en} {codeword(Hex)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 3 {Fix_training_num_en} {Per_beam_training_pkt_num} {Decision_holding_period}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 5 {0:show, 1:2G, 2:5G} {beam_num} {idxA(Hex)} {idxB(Hex)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 7 {0:show, 1:2G, 2:5G} {total_beam_set_num}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 8 {0:show, 1:set} {RFU delay time(us)}\n"); + + } else if (dm_value[0] == 1) { /*@fix beam pattern*/ + + sat_tab->fix_beam_pattern_en = dm_value[1]; + + if (sat_tab->fix_beam_pattern_en == 1) { + PHYDM_SSCANF(input[3], DCMD_HEX, &dm_value[2]); + sat_tab->fix_beam_pattern_codeword = dm_value[2]; + + if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", + sat_tab->fix_beam_pattern_codeword, + codeword_length); + + (sat_tab->fix_beam_pattern_codeword) &= 0xffffff; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Auto modify to (0x%x)\n", + sat_tab->fix_beam_pattern_codeword); + } + + sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword; + + /*@---------------------------------------------------------*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "Fix Beam Pattern\n"); + + /*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/ + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i); + + if (i == (codeword_length - 1)) + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "%d]\n", + beam_ctrl_signal); + else if (i == 0) + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "Send Codeword[1:%d] to RFU -> [%d", + sat_tab->rfu_codeword_total_bit_num, + beam_ctrl_signal); + else if ((i % devide_num) == (devide_num - 1)) + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d|", + beam_ctrl_signal); + else + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d", + beam_ctrl_signal); + } +/*@---------------------------------------------------------*/ + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + #else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +#if 0 + /*odm_stall_execution(1);*/ +#endif + #endif + } else if (sat_tab->fix_beam_pattern_en == 0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Smart Antenna: Enable\n"); + + } else if (dm_value[0] == 2) { /*set latch time*/ + + sat_tab->latch_time = dm_value[1]; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] latch_time =0x%x\n", + sat_tab->latch_time); + } else if (dm_value[0] == 3) { + sat_tab->fix_training_num_en = dm_value[1]; + + if (sat_tab->fix_training_num_en == 1) { + sat_tab->per_beam_training_pkt_num = (u8)dm_value[2]; + sat_tab->decision_holding_period = (u8)dm_value[3]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmtAnt] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", + sat_tab->fix_training_num_en, + sat_tab->per_beam_training_pkt_num, + sat_tab->decision_holding_period); + + } else if (sat_tab->fix_training_num_en == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] AUTO per_beam_training_pkt_num\n"); + } + } else if (dm_value[0] == 4) { + #if 0 + if (dm_value[1] == 1) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = MAIN_ANT; + + } else if (dm_value[1] == 2) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = AUX_ANT; + + } else if (dm_value[1] == 3) { + sat_tab->ant_num = 2; + sat_tab->first_train_ant = MAIN_ANT; + } + + PDM_SNPF((output + used, out_len - used, + "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", + sat_tab->ant_num, (sat_tab->first_train_ant - 1))); + #endif + } else if (dm_value[0] == 5) { /*set beam set table*/ + + PHYDM_SSCANF(input[4], DCMD_HEX, &dm_value[3]); + PHYDM_SSCANF(input[5], DCMD_HEX, &dm_value[4]); + + if (dm_value[1] == 1) { /*@2G*/ + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + sat_tab->rfu_codeword_table_2g[dm_value[2]][0] = (u8)dm_value[3]; + sat_tab->rfu_codeword_table_2g[dm_value[2]][1] = (u8)dm_value[4]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmtAnt] Set 2G Table[%d] = [A:0x%x, B:0x%x]\n", + dm_value[2], dm_value[3], dm_value[4]); + } + + } else if (dm_value[1] == 2) { /*@5G*/ + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + sat_tab->rfu_codeword_table_5g[dm_value[2]][0] = (u8)dm_value[3]; + sat_tab->rfu_codeword_table_5g[dm_value[2]][1] = (u8)dm_value[4]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n", + dm_value[2], dm_value[3], dm_value[4]); + } + } else if (dm_value[1] == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmtAnt] 2G Beam Table==============>\n"); + for (i = 0; i < sat_tab->total_beam_set_num_2g; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "2G Table[%d] = [A:0x%x, B:0x%x]\n", i, + sat_tab->rfu_codeword_table_2g[i][0], + sat_tab->rfu_codeword_table_2g[i][1]); + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmtAnt] 5G Beam Table==============>\n"); + for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "5G Table[%d] = [A:0x%x, B:0x%x]\n", i, + sat_tab->rfu_codeword_table_5g[i][0], + sat_tab->rfu_codeword_table_5g[i][1]); + } + } + + } else if (dm_value[0] == 6) { +#if 0 + if (dm_value[1] == 0) { + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + sat_tab->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3]; + sat_tab->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4]; + PDM_SNPF((output + used, out_len - used, + "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n", + dm_value[2], dm_value[3], + dm_value[4])); + } + } else { + for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) { + PDM_SNPF((output + used, out_len - used, + "[SmtAnt] Read 5G Table[%d] = [A:0x%x, B:0x%x]\n", + i, + sat_tab->rfu_codeword_table_5g[i][0], + sat_tab->rfu_codeword_table_5g[i][1])); + } + } +#endif + } else if (dm_value[0] == 7) { + if (dm_value[1] == 1) { + sat_tab->total_beam_set_num_2g = (u8)(dm_value[2]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] total_beam_set_num_2g = ((%d))\n", + sat_tab->total_beam_set_num_2g); + + } else if (dm_value[1] == 2) { + sat_tab->total_beam_set_num_5g = (u8)(dm_value[2]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] total_beam_set_num_5g = ((%d))\n", + sat_tab->total_beam_set_num_5g); + } else if (dm_value[1] == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Show total_beam_set_num{2g,5g} = {%d,%d}\n", + sat_tab->total_beam_set_num_2g, + sat_tab->total_beam_set_num_5g); + } + + } else if (dm_value[0] == 8) { + if (dm_value[1] == 1) { + sat_tab->rfu_protocol_delay_time = (u16)(dm_value[2]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmtAnt] Set rfu_protocol_delay_time = ((%d))\n", + sat_tab->rfu_protocol_delay_time); + } else if (dm_value[1] == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmtAnt] Read rfu_protocol_delay_time = ((%d))\n", + sat_tab->rfu_protocol_delay_time); + } + } + + *_used = used; + *_out_len = out_len; +} + +void phydm_set_rfu_beam_pattern_type2( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + + if (dm->ant_div_type != HL_SW_SMART_ANT_TYPE2) + return; + + PHYDM_DBG(dm, DBG_ANT_DIV, "Training beam_set index = (( 0x%x ))\n", + sat_tab->fast_training_beam_num); + sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->fast_training_beam_num); + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + #else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +#if 0 + /*odm_stall_execution(1);*/ +#endif + #endif +} + +void phydm_fast_ant_training_hl_smart_antenna_type2( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + u32 codeword = 0; + u8 i = 0, j = 0; + u8 avg_rssi_tmp; + u8 avg_rssi_tmp_ma; + u8 max_beam_ant_rssi = 0; + u8 rssi_target_beam = 0, target_beam_max_rssi = 0; + u8 evm1ss_target_beam = 0, evm2ss_target_beam = 0; + u32 target_beam_max_evm1ss = 0, target_beam_max_evm2ss = 0; + u32 beam_tmp; + u8 per_beam_val_diff_tmp = 0, training_pkt_num_offset; + u32 avg_evm2ss[2] = {0}, avg_evm2ss_sum = 0; + u32 avg_evm1ss = 0; + u32 beam_path_evm_2ss_cnt_all = 0; /*sum of all 2SS-pattern cnt*/ + u32 beam_path_evm_1ss_cnt_all = 0; /*sum of all 1SS-pattern cnt*/ + u8 decision_type; + + if (!dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + + if (fat_tab->is_become_linked == true) { + sat_tab->decision_holding_period = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n"); + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, + "change to (( %d )) FAT_state\n", + fat_tab->fat_state); + fat_tab->is_become_linked = dm->is_linked; + } + return; + + } else { + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); + + fat_tab->fat_state = FAT_PREPARE_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, + "change to (( %d )) FAT_state\n", + fat_tab->fat_state); + + /*sat_tab->fast_training_beam_num = 0;*/ + /*phydm_set_rfu_beam_pattern_type2(dm);*/ + + fat_tab->is_become_linked = dm->is_linked; + } + } + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/ +#endif + + /* @[DECISION STATE] */ + /*@=======================================================================================*/ + if (fat_tab->fat_state == FAT_DECISION_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n"); + + /*@compute target beam in each antenna*/ + + for (j = 0; j < (sat_tab->total_beam_set_num); j++) { + /*@[Decision1: RSSI]-------------------------------------------------------------------*/ + if (sat_tab->statistic_pkt_cnt[j] == 0) { /*@if new RSSI = 0 -> MA_RSSI-=2*/ + avg_rssi_tmp = sat_tab->beam_set_avg_rssi_pre[j]; + avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; + avg_rssi_tmp_ma = avg_rssi_tmp; + } else { + avg_rssi_tmp = (u8)((sat_tab->beam_set_rssi_avg_sum[j]) / (sat_tab->statistic_pkt_cnt[j])); + avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->beam_set_avg_rssi_pre[j]) >> 1; + } + + sat_tab->beam_set_avg_rssi_pre[j] = avg_rssi_tmp; + + if (avg_rssi_tmp > target_beam_max_rssi) { + rssi_target_beam = j; + target_beam_max_rssi = avg_rssi_tmp; + } + + /*@[Decision2: EVM 2ss]-------------------------------------------------------------------*/ + if (sat_tab->beam_path_evm_2ss_cnt[j] != 0) { + avg_evm2ss[0] = sat_tab->beam_path_evm_2ss_sum[j][0] / sat_tab->beam_path_evm_2ss_cnt[j]; + avg_evm2ss[1] = sat_tab->beam_path_evm_2ss_sum[j][1] / sat_tab->beam_path_evm_2ss_cnt[j]; + avg_evm2ss_sum = avg_evm2ss[0] + avg_evm2ss[1]; + beam_path_evm_2ss_cnt_all += sat_tab->beam_path_evm_2ss_cnt[j]; + + sat_tab->beam_set_avg_evm_2ss_pre[j] = (u8)avg_evm2ss_sum; + } + + if (avg_evm2ss_sum > target_beam_max_evm2ss) { + evm2ss_target_beam = j; + target_beam_max_evm2ss = avg_evm2ss_sum; + } + + /*@[Decision3: EVM 1ss]-------------------------------------------------------------------*/ + if (sat_tab->beam_path_evm_1ss_cnt[j] != 0) { + avg_evm1ss = sat_tab->beam_path_evm_1ss_sum[j] / sat_tab->beam_path_evm_1ss_cnt[j]; + beam_path_evm_1ss_cnt_all += sat_tab->beam_path_evm_1ss_cnt[j]; + + sat_tab->beam_set_avg_evm_1ss_pre[j] = (u8)avg_evm1ss; + } + + if (avg_evm1ss > target_beam_max_evm1ss) { + evm1ss_target_beam = j; + target_beam_max_evm1ss = avg_evm1ss; + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Beam[%d] Pkt_cnt=(( %d )), avg{MA,rssi}={%d, %d}, EVM1={%d}, EVM2={%d, %d, %d}\n", + j, sat_tab->statistic_pkt_cnt[j], + avg_rssi_tmp_ma, avg_rssi_tmp, avg_evm1ss, + avg_evm2ss[0], avg_evm2ss[1], avg_evm2ss_sum); + + /*reset counter value*/ + sat_tab->beam_set_rssi_avg_sum[j] = 0; + sat_tab->beam_path_rssi_sum[j][0] = 0; + sat_tab->beam_path_rssi_sum[j][1] = 0; + sat_tab->statistic_pkt_cnt[j] = 0; + + sat_tab->beam_path_evm_2ss_sum[j][0] = 0; + sat_tab->beam_path_evm_2ss_sum[j][1] = 0; + sat_tab->beam_path_evm_2ss_cnt[j] = 0; + + sat_tab->beam_path_evm_1ss_sum[j] = 0; + sat_tab->beam_path_evm_1ss_cnt[j] = 0; + } + + /*@[Joint Decision]-------------------------------------------------------------------*/ + PHYDM_DBG(dm, DBG_ANT_DIV, + "--->1.[RSSI] Target Beam(( %d )) RSSI_max=((%d))\n", + rssi_target_beam, target_beam_max_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, + "--->2.[Evm2SS] Target Beam(( %d )) EVM2SS_max=((%d))\n", + evm2ss_target_beam, target_beam_max_evm2ss); + PHYDM_DBG(dm, DBG_ANT_DIV, + "--->3.[Evm1SS] Target Beam(( %d )) EVM1SS_max=((%d))\n", + evm1ss_target_beam, target_beam_max_evm1ss); + + if (target_beam_max_rssi <= 10) { + sat_tab->rx_idle_beam_set_idx = rssi_target_beam; + decision_type = 1; + } else { + if (beam_path_evm_2ss_cnt_all != 0) { + sat_tab->rx_idle_beam_set_idx = evm2ss_target_beam; + decision_type = 2; + } else if (beam_path_evm_1ss_cnt_all != 0) { + sat_tab->rx_idle_beam_set_idx = evm1ss_target_beam; + decision_type = 3; + } else { + sat_tab->rx_idle_beam_set_idx = rssi_target_beam; + decision_type = 1; + } + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "---> Decision_type=((%d)), Final Target Beam(( %d ))\n", + decision_type, sat_tab->rx_idle_beam_set_idx); + + /*@Calculate packet counter offset*/ + for (j = 0; j < (sat_tab->total_beam_set_num); j++) { + if (decision_type == 1) { + per_beam_val_diff_tmp = target_beam_max_rssi - sat_tab->beam_set_avg_rssi_pre[j]; + + } else if (decision_type == 2) { + per_beam_val_diff_tmp = ((u8)target_beam_max_evm2ss - sat_tab->beam_set_avg_evm_2ss_pre[j]) >> 1; + } else if (decision_type == 3) { + per_beam_val_diff_tmp = (u8)target_beam_max_evm1ss - sat_tab->beam_set_avg_evm_1ss_pre[j]; + } + sat_tab->beam_set_train_val_diff[j] = per_beam_val_diff_tmp; + PHYDM_DBG(dm, DBG_ANT_DIV, + "Beam_Set[%d]: diff= ((%d))\n", j, + per_beam_val_diff_tmp); + } + + /*set beam in each antenna*/ + phydm_update_rx_idle_beam_type2(dm); + fat_tab->fat_state = FAT_PREPARE_STATE; + } + /* @[TRAINING STATE] */ + else if (fat_tab->fat_state == FAT_TRAINING_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n"); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "curr_beam_idx = (( %d )), pre_beam_idx = (( %d ))\n", + sat_tab->fast_training_beam_num, + sat_tab->pre_fast_training_beam_num); + + if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num) + + sat_tab->force_update_beam_en = 0; + + else { + sat_tab->force_update_beam_en = 1; + + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; + if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", + sat_tab->fast_training_beam_num); + fat_tab->fat_state = FAT_DECISION_STATE; + phydm_fast_ant_training_hl_smart_antenna_type2(dm); + + } else { + sat_tab->fast_training_beam_num++; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", + beam_tmp, + sat_tab->fast_training_beam_num); + phydm_set_rfu_beam_pattern_type2(dm); + fat_tab->fat_state = FAT_TRAINING_STATE; + } + } + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + PHYDM_DBG(dm, DBG_ANT_DIV, "Update Pre_Beam =(( %d ))\n", + sat_tab->pre_fast_training_beam_num); + } + /* @[Prepare state] */ + /*@=======================================================================================*/ + else if (fat_tab->fat_state == FAT_PREPARE_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n"); + + if (dm->pre_traffic_load == dm->traffic_load) { + if (sat_tab->decision_holding_period != 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Holding_period = (( %d )), return!!!\n", + sat_tab->decision_holding_period); + sat_tab->decision_holding_period--; + return; + } + } + + /* Set training packet number*/ + if (sat_tab->fix_training_num_en == 0) { + switch (dm->traffic_load) { + case TRAFFIC_HIGH: + sat_tab->per_beam_training_pkt_num = 8; + sat_tab->decision_holding_period = 2; + break; + case TRAFFIC_MID: + sat_tab->per_beam_training_pkt_num = 6; + sat_tab->decision_holding_period = 3; + break; + case TRAFFIC_LOW: + sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/ + sat_tab->decision_holding_period = 4; + break; + case TRAFFIC_ULTRA_LOW: + sat_tab->per_beam_training_pkt_num = 1; + sat_tab->decision_holding_period = 6; + break; + default: + break; + } + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "TrafficLoad = (( %d )), Fix_beam = (( %d )), per_beam_training_pkt_num = (( %d )), decision_holding_period = ((%d))\n", + dm->traffic_load, sat_tab->fix_training_num_en, + sat_tab->per_beam_training_pkt_num, + sat_tab->decision_holding_period); + + /*@Beam_set number*/ + if (*dm->band_type == ODM_BAND_5G) { + sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_5g; + PHYDM_DBG(dm, DBG_ANT_DIV, "5G beam_set num = ((%d))\n", + sat_tab->total_beam_set_num); + } else { + sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_2g; + PHYDM_DBG(dm, DBG_ANT_DIV, "2G beam_set num = ((%d))\n", + sat_tab->total_beam_set_num); + } + + for (j = 0; j < (sat_tab->total_beam_set_num); j++) { + training_pkt_num_offset = sat_tab->beam_set_train_val_diff[j]; + + if (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset) + sat_tab->beam_set_train_cnt[j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset; + else + sat_tab->beam_set_train_cnt[j] = 1; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Beam_Set[ %d ] training_pkt_offset = ((%d)), training_pkt_num = ((%d))\n", + j, sat_tab->beam_set_train_val_diff[j], + sat_tab->beam_set_train_cnt[j]); + } + + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->update_beam_idx = 0; + sat_tab->pkt_counter = 0; + + sat_tab->fast_training_beam_num = 0; + phydm_set_rfu_beam_pattern_type2(dm); + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + fat_tab->fat_state = FAT_TRAINING_STATE; + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void phydm_beam_switch_workitem_callback( + void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE + sat_tab->pkt_skip_statistic_en = 1; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", + sat_tab->pkt_skip_statistic_en); + + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE +#if 0 + /*odm_stall_execution(sat_tab->latch_time);*/ +#endif + sat_tab->pkt_skip_statistic_en = 0; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", + sat_tab->pkt_skip_statistic_en, sat_tab->latch_time); +} + +void phydm_beam_decision_workitem_callback( + void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Beam decision Workitem Callback\n"); + phydm_fast_ant_training_hl_smart_antenna_type2(dm); +} +#endif + +void phydm_process_rssi_for_hb_smtant_type2( + void *dm_void, + void *phy_info_void, + void *pkt_info_void, + u8 rssi_avg) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u8 train_pkt_number; + u32 beam_tmp; + u8 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0]; + u8 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1]; + u8 rx_evm_ant0 = phy_info->rx_mimo_evm_dbm[0]; + u8 rx_evm_ant1 = phy_info->rx_mimo_evm_dbm[1]; + + /*@[Beacon]*/ + if (pktinfo->is_packet_beacon) { + sat_tab->beacon_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "MatchBSSID_beacon_counter = ((%d))\n", + sat_tab->beacon_counter); + + if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) { + sat_tab->update_beam_idx++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", + sat_tab->pre_beacon_counter, + sat_tab->pkt_counter, + sat_tab->update_beam_idx); + + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; + } + } + /*@[data]*/ + else if (pktinfo->is_packet_to_self) { + if (sat_tab->pkt_skip_statistic_en == 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "ID[%d] pkt_cnt=((%d)): Beam_set = ((%d)), RSSI{A,B,avg} = {%d, %d, %d}\n", + pktinfo->station_id, sat_tab->pkt_counter, + sat_tab->fast_training_beam_num, + rx_power_ant0, rx_power_ant1, rssi_avg); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Rate_ss = ((%d)), EVM{A,B} = {%d, %d}, RX Rate =", + pktinfo->rate_ss, rx_evm_ant0, rx_evm_ant1); + phydm_print_rate(dm, dm->rx_rate, DBG_ANT_DIV); + + if (sat_tab->pkt_counter >= 1) /*packet skip count*/ + { + sat_tab->beam_set_rssi_avg_sum[sat_tab->fast_training_beam_num] += rssi_avg; + sat_tab->statistic_pkt_cnt[sat_tab->fast_training_beam_num]++; + + sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][0] += rx_power_ant0; + sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][1] += rx_power_ant1; + + if (pktinfo->rate_ss == 2) { + sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][0] += rx_evm_ant0; + sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][1] += rx_evm_ant1; + sat_tab->beam_path_evm_2ss_cnt[sat_tab->fast_training_beam_num]++; + } else { + sat_tab->beam_path_evm_1ss_sum[sat_tab->fast_training_beam_num] += rx_evm_ant0; + sat_tab->beam_path_evm_1ss_cnt[sat_tab->fast_training_beam_num]++; + } + } + + sat_tab->pkt_counter++; + + train_pkt_number = sat_tab->beam_set_train_cnt[sat_tab->fast_training_beam_num]; + + if (sat_tab->pkt_counter >= train_pkt_number) { + sat_tab->update_beam_idx++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "pre_beacon_counter = ((%d)), Update_new_beam = ((%d))\n", + sat_tab->pre_beacon_counter, + sat_tab->update_beam_idx); + + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; + } + } + } + + if (sat_tab->update_beam_idx > 0) { + sat_tab->update_beam_idx = 0; + + if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) { + fat_tab->fat_state = FAT_DECISION_STATE; + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_fast_ant_training_hl_smart_antenna_type2(dm); /*@go to make decision*/ + #else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem); + #endif + + } else { + beam_tmp = sat_tab->fast_training_beam_num; + sat_tab->fast_training_beam_num++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "Update Beam_num (( %d )) -> (( %d ))\n", + beam_tmp, sat_tab->fast_training_beam_num); + phydm_set_rfu_beam_pattern_type2(dm); + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + + fat_tab->fat_state = FAT_TRAINING_STATE; + } + } +} +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) + +void phydm_hl_smart_ant_type1_init_8821a( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 value32; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8821A SmartAnt_Init => ant_div_type=[Hong-Lin Smart ant Type1]\n"); + +#if 0 + /* @---------------------------------------- */ + /* @GPIO 2-3 for Beam control */ + /* reg0x66[2]=0 */ + /* reg0x44[27:26] = 0 */ + /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ + /* reg0x44[15:8] output_value for P_GPIO[7:0] */ + /* reg0x40[1:0] = 0 GPIO function */ + /* @------------------------------------------ */ +#endif + + /*@GPIO setting*/ + odm_set_mac_reg(dm, R_0x64, BIT(18), 0); + odm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0); + odm_set_mac_reg(dm, R_0x44, BIT(19) | BIT(18), 0x3); /*@enable_output for P_GPIO[3:2]*/ +#if 0 + /*odm_set_mac_reg(dm, R_0x44, BIT(11)|BIT(10), 0);*/ /*output value*/ +#endif + odm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/ + + /*@Hong_lin smart antenna HW setting*/ + sat_tab->rfu_codeword_total_bit_num = 24; /*@max=32*/ + sat_tab->rfu_each_ant_bit_num = 4; + sat_tab->beam_patten_num_each_ant = 4; + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + sat_tab->latch_time = 100; /*@mu sec*/ +#elif DEV_BUS_TYPE == RT_USB_INTERFACE + sat_tab->latch_time = 100; /*@mu sec*/ +#endif + sat_tab->pkt_skip_statistic_en = 0; + + sat_tab->ant_num = 1; /*@max=8*/ + sat_tab->ant_num_total = NUM_ANTENNA_8821A; + sat_tab->first_train_ant = MAIN_ANT; + + sat_tab->rfu_codeword_table[0] = 0x0; + sat_tab->rfu_codeword_table[1] = 0x4; + sat_tab->rfu_codeword_table[2] = 0x8; + sat_tab->rfu_codeword_table[3] = 0xc; + + sat_tab->rfu_codeword_table_5g[0] = 0x1; + sat_tab->rfu_codeword_table_5g[1] = 0x2; + sat_tab->rfu_codeword_table_5g[2] = 0x4; + sat_tab->rfu_codeword_table_5g[3] = 0x8; + + sat_tab->fix_beam_pattern_en = 0; + sat_tab->decision_holding_period = 0; + + /*@beam training setting*/ + sat_tab->pkt_counter = 0; + sat_tab->per_beam_training_pkt_num = 10; + + /*set default beam*/ + sat_tab->fast_training_beam_num = 0; + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + phydm_set_all_ant_same_beam_num(dm); + + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; + + odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x01000100); + odm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x01000100); + + /*@[BB] FAT setting*/ + odm_set_bb_reg(dm, R_0xc08, BIT(18) | BIT(17) | BIT(16), sat_tab->ant_num); + odm_set_bb_reg(dm, R_0xc08, BIT(31), 0); /*@increase ant num every FAT period 0:+1, 1+2*/ + odm_set_bb_reg(dm, R_0x8c4, BIT(2) | BIT(1), 1); /*@change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/ + odm_set_bb_reg(dm, R_0x8c4, BIT(0), 1); /*@FAT_watchdog_en*/ + + value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD); + odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /*Reg7B4[16]=1 enable antenna training */ + /*Reg7B4[17]=1 enable match MAC addr*/ + odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0); /*@Match MAC ADDR*/ + odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0); +} + +u32 phydm_construct_hl_beam_codeword( + void *dm_void, + u32 *beam_pattern_idx, + u32 ant_num) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 codeword = 0; + u32 data_tmp; + u32 i; + u32 break_counter = 0; + + if (ant_num < 8) { + for (i = 0; i < (sat_tab->ant_num_total); i++) { +#if 0 + /*PHYDM_DBG(dm,DBG_ANT_DIV, "beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] );*/ +#endif + if ((i < (sat_tab->first_train_ant - 1)) || break_counter >= sat_tab->ant_num) { + data_tmp = 0; + } else { + break_counter++; + + if (beam_pattern_idx[i] == 0) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[0]; + else + data_tmp = sat_tab->rfu_codeword_table[0]; + + } else if (beam_pattern_idx[i] == 1) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[1]; + else + data_tmp = sat_tab->rfu_codeword_table[1]; + + } else if (beam_pattern_idx[i] == 2) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[2]; + else + data_tmp = sat_tab->rfu_codeword_table[2]; + + } else if (beam_pattern_idx[i] == 3) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[3]; + else + data_tmp = sat_tab->rfu_codeword_table[3]; + } + } + + codeword |= (data_tmp << (i * 4)); + } + } + + return codeword; +} + +void phydm_update_beam_pattern( + void *dm_void, + u32 codeword, + u32 codeword_length) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u8 i; + boolean beam_ctrl_signal; + u32 one = 0x1; + u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; + u8 devide_num = 4; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Set Beam Pattern =0x%x\n", + codeword); + + reg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD); + reg44_tmp_p = reg44_ori; +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/ +#endif + + devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4; + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); + + if (dm->debug_components & DBG_ANT_DIV) { + if (i == (codeword_length - 1)) + pr_debug("%d ]\n", beam_ctrl_signal); + else if (i == 0) + pr_debug("Send codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); + else if ((i % devide_num) == (devide_num - 1)) + pr_debug("%d | ", beam_ctrl_signal); + else + pr_debug("%d ", beam_ctrl_signal); + } + + if (dm->support_ic_type == ODM_RTL8821) { + #if (RTL8821A_SUPPORT == 1) + reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/ + reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); + reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/ +#endif + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n); + #endif + } + #if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) { + if (sat_tab->rfu_protocol_type == 2) { + reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/ + reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/ + + reg44_tmp_p |= (beam_ctrl_signal << 8); + + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/ +#endif + + } else { + reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/ + reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); + reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */ +#endif + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n); + ODM_delay_us(10); + } + } + #endif + } +} + +void phydm_update_rx_idle_beam( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 i; + + sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm, + &sat_tab->rx_idle_beam[0], + sat_tab->ant_num); + PHYDM_DBG(dm, DBG_ANT_DIV, + "Set target beam_pattern codeword = (( 0x%x ))\n", + sat_tab->update_beam_codeword); + + for (i = 0; i < (sat_tab->ant_num); i++) + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i, + sat_tab->rx_idle_beam[i]); + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); +#else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +#if 0 + /*odm_stall_execution(1);*/ +#endif +#endif + + sat_tab->pre_codeword = sat_tab->update_beam_codeword; +} + +void phydm_hl_smart_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 used = *_used; + u32 out_len = *_out_len; + u32 one = 0x1; + u32 codeword_length = sat_tab->rfu_codeword_total_bit_num; + u32 beam_ctrl_signal, i; + u8 devide_num = 4; + + if (dm_value[0] == 1) { /*@fix beam pattern*/ + + sat_tab->fix_beam_pattern_en = dm_value[1]; + + if (sat_tab->fix_beam_pattern_en == 1) { + sat_tab->fix_beam_pattern_codeword = dm_value[2]; + + if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", + sat_tab->fix_beam_pattern_codeword, + codeword_length); + + (sat_tab->fix_beam_pattern_codeword) &= 0xffffff; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Auto modify to (0x%x)\n", + sat_tab->fix_beam_pattern_codeword); + } + + sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword; + + /*@---------------------------------------------------------*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "Fix Beam Pattern\n"); + + devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4; + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i); + + if (i == (codeword_length - 1)) + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "%d]\n", + beam_ctrl_signal); + else if (i == 0) + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "Send Codeword[1:24] to RFU -> [%d", + beam_ctrl_signal); + else if ((i % devide_num) == (devide_num - 1)) + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d|", + beam_ctrl_signal); + else + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d", + beam_ctrl_signal); + } +/*@---------------------------------------------------------*/ + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + #else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +#if 0 + /*odm_stall_execution(1);*/ +#endif + #endif + } else if (sat_tab->fix_beam_pattern_en == 0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Smart Antenna: Enable\n"); + + } else if (dm_value[0] == 2) { /*set latch time*/ + + sat_tab->latch_time = dm_value[1]; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] latch_time =0x%x\n", + sat_tab->latch_time); + } else if (dm_value[0] == 3) { + sat_tab->fix_training_num_en = dm_value[1]; + + if (sat_tab->fix_training_num_en == 1) { + sat_tab->per_beam_training_pkt_num = (u8)dm_value[2]; + sat_tab->decision_holding_period = (u8)dm_value[3]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", + sat_tab->fix_training_num_en, + sat_tab->per_beam_training_pkt_num, + sat_tab->decision_holding_period); + + } else if (sat_tab->fix_training_num_en == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] AUTO per_beam_training_pkt_num\n"); + } + } else if (dm_value[0] == 4) { + if (dm_value[1] == 1) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = MAIN_ANT; + + } else if (dm_value[1] == 2) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = AUX_ANT; + + } else if (dm_value[1] == 3) { + sat_tab->ant_num = 2; + sat_tab->first_train_ant = MAIN_ANT; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", + sat_tab->ant_num, (sat_tab->first_train_ant - 1)); + } else if (dm_value[0] == 5) { + if (dm_value[1] <= 3) { + sat_tab->rfu_codeword_table[dm_value[1]] = dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", + dm_value[1], dm_value[2]); + } else { + for (i = 0; i < 4; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", + i, sat_tab->rfu_codeword_table[i]); + } + } + } else if (dm_value[0] == 6) { + if (dm_value[1] <= 3) { + sat_tab->rfu_codeword_table_5g[dm_value[1]] = dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", + dm_value[1], dm_value[2]); + } else { + for (i = 0; i < 4; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", + i, sat_tab->rfu_codeword_table_5g[i]); + } + } + } else if (dm_value[0] == 7) { + if (dm_value[1] <= 4) { + sat_tab->beam_patten_num_each_ant = dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Set Beam number = (( %d ))\n", + sat_tab->beam_patten_num_each_ant); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Show Beam number = (( %d ))\n", + sat_tab->beam_patten_num_each_ant); + } + } + *_used = used; + *_out_len = out_len; +} + +void phydm_set_all_ant_same_beam_num( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { /*@2ant for 8821A*/ + + sat_tab->rx_idle_beam[0] = sat_tab->fast_training_beam_num; + sat_tab->rx_idle_beam[1] = sat_tab->fast_training_beam_num; + } + + sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm, + &sat_tab->rx_idle_beam[0], + sat_tab->ant_num); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n", + sat_tab->update_beam_codeword); + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); +#else + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +/*odm_stall_execution(1);*/ +#endif +} + +void odm_fast_ant_training_hl_smart_antenna_type1( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + u32 codeword = 0, i, j; + u32 target_ant; + u32 avg_rssi_tmp, avg_rssi_tmp_ma; + u32 target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0}; + u32 max_beam_ant_rssi = 0; + u32 target_ant_beam[SUPPORT_RF_PATH_NUM] = {0}; + u32 beam_tmp; + u8 next_ant; + u32 rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u32 rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u32 rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u8 per_beam_rssi_diff_tmp = 0, training_pkt_num_offset; + u32 break_counter = 0; + u32 used_ant; + + if (!dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + + if (fat_tab->is_become_linked == true) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n"); + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + PHYDM_DBG(dm, DBG_ANT_DIV, + "change to (( %d )) FAT_state\n", + fat_tab->fat_state); + + fat_tab->is_become_linked = dm->is_linked; + } + return; + + } else { + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); + + fat_tab->fat_state = FAT_PREPARE_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, + "change to (( %d )) FAT_state\n", + fat_tab->fat_state); + +#if 0 + /*sat_tab->fast_training_beam_num = 0;*/ + /*phydm_set_all_ant_same_beam_num(dm);*/ +#endif + + fat_tab->is_become_linked = dm->is_linked; + } + } + + if (*fat_tab->p_force_tx_ant_by_desc == false) { + if (dm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + else + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + } + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/ +#endif + + /* @[DECISION STATE] */ + /*@=======================================================================================*/ + if (fat_tab->fat_state == FAT_DECISION_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n"); + phydm_fast_training_enable(dm, FAT_OFF); + + break_counter = 0; + /*@compute target beam in each antenna*/ + for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) { + for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) { + if (sat_tab->pkt_rssi_cnt[i][j] == 0) { + avg_rssi_tmp = sat_tab->pkt_rssi_pre[i][j]; + avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; + avg_rssi_tmp_ma = avg_rssi_tmp; + } else { + avg_rssi_tmp = (sat_tab->pkt_rssi_sum[i][j]) / (sat_tab->pkt_rssi_cnt[i][j]); + avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->pkt_rssi_pre[i][j]) >> 1; + } + + rssi_sorting_seq[j] = avg_rssi_tmp; + sat_tab->pkt_rssi_pre[i][j] = avg_rssi_tmp; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n", + i, j, sat_tab->pkt_rssi_cnt[i][j], + avg_rssi_tmp_ma, avg_rssi_tmp); + + if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) { + target_ant_beam[i] = j; + target_ant_beam_max_rssi[i] = avg_rssi_tmp; + } + + /*reset counter value*/ + sat_tab->pkt_rssi_sum[i][j] = 0; + sat_tab->pkt_rssi_cnt[i][j] = 0; + } + sat_tab->rx_idle_beam[i] = target_ant_beam[i]; + PHYDM_DBG(dm, DBG_ANT_DIV, + "---------> Target of ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n", + i, target_ant_beam[i], + target_ant_beam_max_rssi[i]); + +#if 0 + /*sorting*/ + /*@ + PHYDM_DBG(dm, DBG_ANT_DIV, "[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]); + */ + + /*phydm_seq_sorting(dm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/ + + /*@ + PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3]); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3]); + */ +#endif + + if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) { + target_ant = i; + max_beam_ant_rssi = target_ant_beam_max_rssi[i]; +#if + /*PHYDM_DBG(dm, DBG_ANT_DIV, "Target of ant = (( %d )) max_beam_ant_rssi = (( %d ))\n", + target_ant, max_beam_ant_rssi);*/ +#endif + } + break_counter++; + if (break_counter >= sat_tab->ant_num) + break; + } + +#ifdef CONFIG_FAT_PATCH + break_counter = 0; + for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) { + for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) { + per_beam_rssi_diff_tmp = (u8)(max_beam_ant_rssi - sat_tab->pkt_rssi_pre[i][j]); + sat_tab->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "ant[%d], Beam[%d]: RSSI_diff= ((%d))\n", + i, j, per_beam_rssi_diff_tmp); + } + break_counter++; + if (break_counter >= sat_tab->ant_num) + break; + } +#endif + + if (target_ant == 0) + target_ant = MAIN_ANT; + else if (target_ant == 1) + target_ant = AUX_ANT; + + if (sat_tab->ant_num > 1) { + /* @[ update RX ant ]*/ + odm_update_rx_idle_ant(dm, (u8)target_ant); + + /* @[ update TX ant ]*/ + odm_update_tx_ant(dm, (u8)target_ant, (fat_tab->train_idx)); + } + + /*set beam in each antenna*/ + phydm_update_rx_idle_beam(dm); + + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + fat_tab->fat_state = FAT_PREPARE_STATE; + return; + } + /* @[TRAINING STATE] */ + else if (fat_tab->fat_state == FAT_TRAINING_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n"); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n", + sat_tab->fast_training_beam_num, + sat_tab->pre_fast_training_beam_num); + + if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num) + + sat_tab->force_update_beam_en = 0; + + else { + sat_tab->force_update_beam_en = 1; + + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; + if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", + sat_tab->fast_training_beam_num); + fat_tab->fat_state = FAT_DECISION_STATE; + odm_fast_ant_training_hl_smart_antenna_type1(dm); + + } else { + sat_tab->fast_training_beam_num++; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", + beam_tmp, + sat_tab->fast_training_beam_num); + phydm_set_all_ant_same_beam_num(dm); + fat_tab->fat_state = FAT_TRAINING_STATE; + } + } + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[prepare state] Update Pre_Beam =(( %d ))\n", + sat_tab->pre_fast_training_beam_num); + } + /* @[Prepare state] */ + /*@=======================================================================================*/ + else if (fat_tab->fat_state == FAT_PREPARE_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n"); + + if (dm->pre_traffic_load == dm->traffic_load) { + if (sat_tab->decision_holding_period != 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Holding_period = (( %d )), return!!!\n", + sat_tab->decision_holding_period); + sat_tab->decision_holding_period--; + return; + } + } + + /* Set training packet number*/ + if (sat_tab->fix_training_num_en == 0) { + switch (dm->traffic_load) { + case TRAFFIC_HIGH: + sat_tab->per_beam_training_pkt_num = 8; + sat_tab->decision_holding_period = 2; + break; + case TRAFFIC_MID: + sat_tab->per_beam_training_pkt_num = 6; + sat_tab->decision_holding_period = 3; + break; + case TRAFFIC_LOW: + sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/ + sat_tab->decision_holding_period = 4; + break; + case TRAFFIC_ULTRA_LOW: + sat_tab->per_beam_training_pkt_num = 1; + sat_tab->decision_holding_period = 6; + break; + default: + break; + } + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n", + sat_tab->fix_training_num_en, + sat_tab->per_beam_training_pkt_num, + sat_tab->decision_holding_period); + +#ifdef CONFIG_FAT_PATCH + break_counter = 0; + for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) { + for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) { + per_beam_rssi_diff_tmp = sat_tab->beam_train_rssi_diff[i][j]; + training_pkt_num_offset = per_beam_rssi_diff_tmp; + + if (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset) + sat_tab->beam_train_cnt[i][j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset; + else + sat_tab->beam_train_cnt[i][j] = 1; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "ant[%d]: Beam_num-(( %d )) training_pkt_num = ((%d))\n", + i, j, sat_tab->beam_train_cnt[i][j]); + } + break_counter++; + if (break_counter >= sat_tab->ant_num) + break; + } + + phydm_fast_training_enable(dm, FAT_OFF); + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->update_beam_idx = 0; + + if (*dm->band_type == ODM_BAND_5G) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Set 5G ant\n"); + /*used_ant = (sat_tab->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/ + used_ant = sat_tab->first_train_ant; + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, "Set 2.4G ant\n"); + used_ant = sat_tab->first_train_ant; + } + + odm_update_rx_idle_ant(dm, (u8)used_ant); + +#else + /* Set training MAC addr. of target */ + odm_set_next_mac_addr_target(dm); + phydm_fast_training_enable(dm, FAT_ON); +#endif + + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + sat_tab->pkt_counter = 0; + sat_tab->fast_training_beam_num = 0; + phydm_set_all_ant_same_beam_num(dm); + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + fat_tab->fat_state = FAT_TRAINING_STATE; + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void phydm_beam_switch_workitem_callback( + void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE + sat_tab->pkt_skip_statistic_en = 1; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", + sat_tab->pkt_skip_statistic_en); + + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE +#if 0 + /*odm_stall_execution(sat_tab->latch_time);*/ +#endif + sat_tab->pkt_skip_statistic_en = 0; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", + sat_tab->pkt_skip_statistic_en, sat_tab->latch_time); +} + +void phydm_beam_decision_workitem_callback( + void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Beam decision Workitem Callback\n"); + odm_fast_ant_training_hl_smart_antenna_type1(dm); +} +#endif + +#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ + +#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA*/ + +void phydm_smt_ant_config( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) + + dm->support_ability |= ODM_BB_SMT_ANT; + smtant_table->smt_ant_vendor = SMTANT_CUMITEK; + smtant_table->smt_ant_type = 1; +#if (RTL8822B_SUPPORT == 1) + dm->rfe_type = SMTANT_TMP_RFE_TYPE; +#endif +#elif (defined(CONFIG_HL_SMART_ANTENNA)) + + dm->support_ability |= ODM_BB_SMT_ANT; + smtant_table->smt_ant_vendor = SMTANT_HON_BO; + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + smtant_table->smt_ant_type = 1; +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + smtant_table->smt_ant_type = 2; +#endif +#endif + + PHYDM_DBG(dm, DBG_SMT_ANT, + "[SmtAnt Config] Vendor=((%d)), Smt_ant_type =((%d))\n", + smtant_table->smt_ant_vendor, smtant_table->smt_ant_type); +} + +void phydm_smt_ant_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + + phydm_smt_ant_config(dm); + + if (smtant_table->smt_ant_vendor == SMTANT_CUMITEK) { +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) + phydm_cumitek_smt_ant_init_8822b(dm); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) + phydm_cumitek_smt_ant_init_8197f(dm); +#endif +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) + phydm_cumitek_smt_ant_init_8192f(dm); +#endif +#endif /*@#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))*/ + + } else if (smtant_table->smt_ant_vendor == SMTANT_HON_BO) { +#if (defined(CONFIG_HL_SMART_ANTENNA)) +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + if (dm->support_ic_type == ODM_RTL8821) + phydm_hl_smart_ant_type1_init_8821a(dm); +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + if (dm->support_ic_type == ODM_RTL8822B) + phydm_hl_smart_ant_type2_init_8822b(dm); +#endif +#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/ + } +} +#endif diff --git a/hal/phydm/phydm_smt_ant.h b/hal/phydm/phydm_smt_ant.h new file mode 100644 index 0000000..3a408c4 --- /dev/null +++ b/hal/phydm/phydm_smt_ant.h @@ -0,0 +1,210 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMSMTANT_H__ +#define __PHYDMSMTANT_H__ + +/*@#define SMT_ANT_VERSION "1.1"*/ /*@2017.03.13*/ +/*@#define SMT_ANT_VERSION "1.2"*/ /*@2017.03.28*/ +#define SMT_ANT_VERSION "2.0" /* @Add Cumitek SmtAnt 2017.05.25*/ + +#define SMTANT_RTK 1 +#define SMTANT_HON_BO 2 +#define SMTANT_CUMITEK 3 + +#if (defined(CONFIG_SMART_ANTENNA)) + +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) +struct smt_ant_cumitek { + u8 tx_ant_idx[2][ODM_ASSOCIATE_ENTRY_NUM]; /*@[pathA~B] [MACID 0~128]*/ + u8 rx_default_ant_idx[2]; /*@[pathA~B]*/ +}; +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA)) +struct smt_ant_honbo { + u32 latch_time; + boolean pkt_skip_statistic_en; + u32 fix_beam_pattern_en; + u32 fix_training_num_en; + u32 fix_beam_pattern_codeword; + u32 update_beam_codeword; + u32 ant_num; /*number of "used" smart beam antenna*/ + u32 ant_num_total;/*number of "total" smart beam antenna*/ + u32 first_train_ant; /*@decide witch antenna to train first*/ + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + u32 pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];/*@rssi of each path with a certain beam pattern*/ + u8 beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u8 beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u32 rfu_codeword_table[4]; /*@2G beam truth table*/ + u32 rfu_codeword_table_5g[4]; /*@5G beam truth table*/ + u32 beam_patten_num_each_ant;/*@number of beam can be switched in each antenna*/ + u32 rx_idle_beam[SUPPORT_RF_PATH_NUM]; + u32 pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM]; + u32 pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM]; + #endif + + u32 fast_training_beam_num;/*@current training beam_set index*/ + u32 pre_fast_training_beam_num;/*pre training beam_set index*/ + u32 rfu_codeword_total_bit_num; /* @total bit number of RFU protocol*/ + u32 rfu_each_ant_bit_num; /* @bit number of RFU protocol for each ant*/ + u8 per_beam_training_pkt_num; + u8 decision_holding_period; + + + u32 pre_codeword; + boolean force_update_beam_en; + u32 beacon_counter; + u32 pre_beacon_counter; + u8 pkt_counter; /*@packet number that each beam-set should be colected in training state*/ + u8 update_beam_idx; /*@the index announce that the beam can be updated*/ + u8 rfu_protocol_type; + u16 rfu_protocol_delay_time; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM hl_smart_antenna_workitem; + RT_WORK_ITEM hl_smart_antenna_decision_workitem; + #endif + + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + u8 beam_set_avg_rssi_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@avg pre_rssi of each beam set*/ + u8 beam_set_train_val_diff[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@rssi of a beam pattern set, ex: a set = {ant1_beam=1, ant2_beam=3}*/ + u8 beam_set_train_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@training pkt num of each beam set*/ + u32 beam_set_rssi_avg_sum[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@RSSI_sum of avg(pathA,pathB) for each beam-set)*/ + u32 beam_path_rssi_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@RSSI_sum of each path for each beam-set)*/ + + u8 beam_set_avg_evm_2ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; + u32 beam_path_evm_2ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@2SS evm_sum of each path for each beam-set)*/ + u32 beam_path_evm_2ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; + + u8 beam_set_avg_evm_1ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; + u32 beam_path_evm_1ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM];/*@1SS evm_sum of each path for each beam-set)*/ + u32 beam_path_evm_1ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; + + u32 statistic_pkt_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@statistic_pkt_cnt for SmtAnt make decision*/ + + u8 total_beam_set_num; /*@number of beam set can be switched*/ + u8 total_beam_set_num_2g;/*@number of beam set can be switched in 2G*/ + u8 total_beam_set_num_5g;/*@number of beam set can be switched in 5G*/ + + u8 rfu_codeword_table_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@2G beam truth table*/ + u8 rfu_codeword_table_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@5G beam truth table*/ + u8 rx_idle_beam_set_idx; /*the filanl decsion result*/ + #endif + + +}; +#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/ + +struct smt_ant { + u8 smt_ant_vendor; + u8 smt_ant_type; + u8 tx_desc_mode; /*@0:3 bit mode, 1:2 bit mode*/ + #if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) + struct smt_ant_cumitek cumi_smtant_table; + #endif +}; + +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) +void phydm_cumitek_smt_tx_ant_update( + void *dm_void, + u8 tx_ant_idx_path_a, + u8 tx_ant_idx_path_b, + u32 mac_id); + +void phydm_cumitek_smt_rx_default_ant_update( + void *dm_void, + u8 rx_ant_idx_path_a, + u8 rx_ant_idx_path_b); + +void phydm_cumitek_smt_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len); + +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA)) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_beam_switch_workitem_callback( + void *context); + +void phydm_beam_decision_workitem_callback( + void *context); +#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 +void phydm_hl_smart_ant_type2_init_8822b( + void *dm_void); + +void phydm_update_beam_pattern_type2( + void *dm_void, + u32 codeword, + u32 codeword_length); + +void phydm_set_rfu_beam_pattern_type2( + void *dm_void); + +void phydm_hl_smt_ant_dbg_type2( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len); + +void phydm_process_rssi_for_hb_smtant_type2( + void *dm_void, + void *phy_info_void, + void *pkt_info_void, + u8 rssi_avg); + +#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))*/ + +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) + +void phydm_update_beam_pattern( + void *dm_void, + u32 codeword, + u32 codeword_length); + +void phydm_set_all_ant_same_beam_num( + void *dm_void); + +void phydm_hl_smart_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len); + +#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))*/ +#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/ +void phydm_smt_ant_init(void *dm_void); +#endif /*@#if (defined(CONFIG_SMART_ANTENNA))*/ +#endif \ No newline at end of file diff --git a/hal/phydm/phydm_soml.c b/hal/phydm/phydm_soml.c new file mode 100644 index 0000000..2aa183a --- /dev/null +++ b/hal/phydm/phydm_soml.c @@ -0,0 +1,963 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef CONFIG_ADAPTIVE_SOML + +void phydm_dynamicsoftmletting(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 ret_val; + +#if (RTL8822B_SUPPORT == 1) + if (!*dm->mp_mode) { + if (dm->support_ic_type & ODM_RTL8822B) { + if (!dm->is_linked | dm->iot_table.is_linked_cmw500) + return; + + if (dm->bsomlenabled) { + PHYDM_DBG(dm, ODM_COMP_API, + "PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\n"); + return; + } + + ret_val = odm_get_bb_reg(dm, R_0xf8c, MASKBYTE0); + PHYDM_DBG(dm, ODM_COMP_API, + "PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\n", + ret_val); + + if (ret_val < 0x16) { + PHYDM_DBG(dm, ODM_COMP_API, + "PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\n", + ret_val); + phydm_somlrxhp_setting(dm, true); +#if 0 + /*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xc10a0000);*/ +#endif + dm->bsomlenabled = true; + } + } + } +#endif +} + +void phydm_soml_on_off( + void *dm_void, + u8 swch) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + if (swch == SOML_ON) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn on )) SOML\n"); + + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, R_0x998, BIT(6), swch); +#if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) + phydm_somlrxhp_setting(dm, true); +#endif + + } else if (swch == SOML_OFF) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn off )) SOML\n"); + + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, R_0x998, BIT(6), swch); +#if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) + phydm_somlrxhp_setting(dm, false); +#endif + } + dm_soml_table->soml_on_off = swch; +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_adaptive_soml_callback( + struct phydm_timer_list *timer) +{ + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + #if USE_WORKITEM + odm_schedule_work_item(&dm_soml_table->phydm_adaptive_soml_workitem); + #else + { +#if 0 + /*@dbg_print("%s\n",__func__);*/ +#endif + phydm_adsl(dm); + } + #endif + #else + odm_schedule_work_item(&dm_soml_table->phydm_adaptive_soml_workitem); + #endif +} + +void phydm_adaptive_soml_workitem_callback( + void *context) +{ +#ifdef CONFIG_ADAPTIVE_SOML + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + +#if 0 + /*@dbg_print("%s\n",__func__);*/ +#endif + phydm_adsl(dm); +#endif +} + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void phydm_adaptive_soml_callback( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *padapter = dm->adapter; + + if (*dm->is_net_closed == true) + return; + if (dm->support_interface == ODM_ITRF_PCIE) + phydm_adsl(dm); + else { + /* @Can't do I/O in timer callback*/ + phydm_run_in_thread_cmd(dm, + phydm_adaptive_soml_workitem_callback, + dm); + } +} + +void phydm_adaptive_soml_workitem_callback( + void *context) +{ + struct dm_struct *dm = (void *)context; + +#if 0 + /*@dbg_print("%s\n",__func__);*/ +#endif + phydm_adsl(dm); +} + +#else +void phydm_adaptive_soml_callback( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "******SOML_Callback******\n"); + phydm_adsl(dm); +} +#endif + +void phydm_rx_rate_for_soml( + void *dm_void, + void *pkt_info_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + u8 data_rate = (pktinfo->data_rate & 0x7f); + + if (pktinfo->data_rate >= ODM_RATEMCS0 && pktinfo->data_rate <= ODM_RATEMCS31) + dm_soml_table->num_ht_cnt[data_rate - ODM_RATEMCS0]++; + else if ((pktinfo->data_rate >= ODM_RATEVHTSS1MCS0) && (pktinfo->data_rate <= ODM_RATEVHTSS4MCS9)) + dm_soml_table->num_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++; +} + +void phydm_rx_qam_for_soml( + void *dm_void, + void *pkt_info_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + u8 date_rate = (pktinfo->data_rate & 0x7f); + + if (dm_soml_table->soml_state_cnt < (dm_soml_table->soml_train_num << 1)) { + if (dm_soml_table->soml_on_off == SOML_ON) + return; + else if (dm_soml_table->soml_on_off == SOML_OFF) { + if (date_rate >= ODM_RATEMCS8 && date_rate <= ODM_RATEMCS10) + dm_soml_table->num_ht_qam[BPSK_QPSK]++; + + else if ((date_rate >= ODM_RATEMCS11) && (date_rate <= ODM_RATEMCS12)) + dm_soml_table->num_ht_qam[QAM16]++; + + else if ((date_rate >= ODM_RATEMCS13) && (date_rate <= ODM_RATEMCS15)) + dm_soml_table->num_ht_qam[QAM64]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS0) && (date_rate <= ODM_RATEVHTSS2MCS2)) + dm_soml_table->num_vht_qam[BPSK_QPSK]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS3) && (date_rate <= ODM_RATEVHTSS2MCS4)) + dm_soml_table->num_vht_qam[QAM16]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS5) && (date_rate <= ODM_RATEVHTSS2MCS5)) + dm_soml_table->num_vht_qam[QAM64]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS8) && (date_rate <= ODM_RATEVHTSS2MCS9)) + dm_soml_table->num_vht_qam[QAM256]++; + } + } +} + +void phydm_soml_reset_rx_rate( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + u8 order; + + for (order = 0; order < HT_RATE_IDX; order++) + dm_soml_table->num_ht_cnt[order] = 0; + + for (order = 0; order < VHT_RATE_IDX; order++) + dm_soml_table->num_vht_cnt[order] = 0; +} + +void phydm_soml_reset_qam( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + u8 order; + + for (order = 0; order < HT_ORDER_TYPE; order++) + dm_soml_table->num_ht_qam[order] = 0; + + for (order = 0; order < VHT_ORDER_TYPE; order++) + dm_soml_table->num_vht_qam[order] = 0; +} + +void phydm_soml_cfo_process( + void *dm_void, + s32 *diff_a, + s32 *diff_b) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 value32, value32_1, value32_2, value32_3; + s32 cfo_acq_a, cfo_acq_b, cfo_end_a, cfo_end_b; + + value32 = odm_get_bb_reg(dm, R_0xd10, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD); + value32_2 = odm_get_bb_reg(dm, R_0xd50, MASKDWORD); + value32_3 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD); + + cfo_acq_a = (s32)((value32 & 0x1fff0000) >> 16); + cfo_end_a = (s32)((value32_1 & 0x1fff0000) >> 16); + cfo_acq_b = (s32)((value32_2 & 0x1fff0000) >> 16); + cfo_end_b = (s32)((value32_3 & 0x1fff0000) >> 16); + + *diff_a = ((cfo_acq_a >= cfo_end_a) ? (cfo_acq_a - cfo_end_a) : (cfo_end_a - cfo_acq_a)); + *diff_b = ((cfo_acq_b >= cfo_end_b) ? (cfo_acq_b - cfo_end_b) : (cfo_end_b - cfo_acq_b)); + + *diff_a = ((*diff_a * 312) + (*diff_a >> 1)) >> 12; /* @312.5/2^12 */ + *diff_b = ((*diff_b * 312) + (*diff_b >> 1)) >> 12; /* @312.5/2^12 */ +} + +void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + u32 used = *_used; + u32 out_len = *_out_len; + u32 dm_value[10] = {0}; + u8 i = 0, input_idx = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + if (dm_value[0] == 1) { /*Turn on/off SOML*/ + dm_soml_table->soml_select = (u8)dm_value[1]; + + } else if (dm_value[0] == 2) { /*training number for SOML*/ + + dm_soml_table->soml_train_num = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_train_num = ((%d))\n", + dm_soml_table->soml_train_num); + } else if (dm_value[0] == 3) { /*training interval for SOML*/ + + dm_soml_table->soml_intvl = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_intvl = ((%d))\n", dm_soml_table->soml_intvl); + } else if (dm_value[0] == 4) { /*@function period for SOML*/ + + dm_soml_table->soml_period = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_period = ((%d))\n", dm_soml_table->soml_period); + } else if (dm_value[0] == 5) { /*@delay_time for SOML*/ + + dm_soml_table->soml_delay_time = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_delay_time = ((%d))\n", + dm_soml_table->soml_delay_time); + } else if (dm_value[0] == 6) { /* @for SOML Rx QAM distribution th*/ + if (dm_value[1] == 256) { + dm_soml_table->qam256_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam256_dist_th = ((%d))\n", + dm_soml_table->qam256_dist_th); + } else if (dm_value[1] == 64) { + dm_soml_table->qam64_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam64_dist_th = ((%d))\n", + dm_soml_table->qam64_dist_th); + } else if (dm_value[1] == 16) { + dm_soml_table->qam16_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam16_dist_th = ((%d))\n", + dm_soml_table->qam16_dist_th); + } else if (dm_value[1] == 4) { + dm_soml_table->bpsk_qpsk_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "bpsk_qpsk_dist_th = ((%d))\n", + dm_soml_table->bpsk_qpsk_dist_th); + } + } else if (dm_value[0] == 7) { /* @for SOML cfo th*/ + if (dm_value[1] == 256) { + dm_soml_table->cfo_qam256_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam256_th = ((%d KHz))\n", + dm_soml_table->cfo_qam256_th); + } else if (dm_value[1] == 64) { + dm_soml_table->cfo_qam64_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam64_th = ((%d KHz))\n", + dm_soml_table->cfo_qam64_th); + } else if (dm_value[1] == 16) { + dm_soml_table->cfo_qam16_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam16_th = ((%d KHz))\n", + dm_soml_table->cfo_qam16_th); + } else if (dm_value[1] == 4) { + dm_soml_table->cfo_qpsk_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qpsk_th = ((%d KHz))\n", + dm_soml_table->cfo_qpsk_th); + } + } else if (dm_value[0] == 100) { /*show parameters*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_select = ((%d))\n", dm_soml_table->soml_select); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_train_num = ((%d))\n", + dm_soml_table->soml_train_num); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_intvl = ((%d))\n", dm_soml_table->soml_intvl); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_period = ((%d))\n", dm_soml_table->soml_period); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_delay_time = ((%d))\n\n", + dm_soml_table->soml_delay_time); + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam256_dist_th = ((%d)), qam64_dist_th = ((%d)), ", + dm_soml_table->qam256_dist_th, + dm_soml_table->qam64_dist_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam16_dist_th = ((%d)), bpsk_qpsk_dist_th = ((%d))\n", + dm_soml_table->qam16_dist_th, + dm_soml_table->bpsk_qpsk_dist_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam256_th = ((%d KHz)), cfo_qam64_th = ((%d KHz)), ", + dm_soml_table->cfo_qam256_th, + dm_soml_table->cfo_qam64_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam16_th = ((%d KHz)), cfo_qpsk_th = ((%d KHz))\n", + dm_soml_table->cfo_qam16_th, + dm_soml_table->cfo_qpsk_th); + } + *_used = used; + *_out_len = out_len; +} + +void phydm_soml_statistics( + void *dm_void, + u8 on_off_state + + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + u8 i, j; + u32 num_bytes_diff, num_rate_diff; + + if (on_off_state == SOML_ON) { + if (*dm->channel <= 14) { + for (i = ODM_RATEMCS0; i <= ODM_RATEMCS15; i++) { + num_rate_diff = dm_soml_table->num_ht_cnt[i - ODM_RATEMCS0] - dm_soml_table->pre_num_ht_cnt[i - ODM_RATEMCS0]; + dm_soml_table->num_ht_cnt_on[i - ODM_RATEMCS0] += num_rate_diff; + dm_soml_table->pre_num_ht_cnt[i - ODM_RATEMCS0] = dm_soml_table->num_ht_cnt[i - ODM_RATEMCS0]; + num_bytes_diff = dm_soml_table->num_ht_bytes[i - ODM_RATEMCS0] - dm_soml_table->pre_num_ht_bytes[i - ODM_RATEMCS0]; + dm_soml_table->num_ht_bytes_on[i - ODM_RATEMCS0] += num_bytes_diff; + dm_soml_table->pre_num_ht_bytes[i - ODM_RATEMCS0] = dm_soml_table->num_ht_bytes[i - ODM_RATEMCS0]; + } + } + if (dm->support_ic_type == ODM_RTL8822B) { + for (j = ODM_RATEVHTSS1MCS0; j <= ODM_RATEVHTSS2MCS9; j++) { + num_rate_diff = dm_soml_table->num_vht_cnt[j - ODM_RATEVHTSS1MCS0] - dm_soml_table->pre_num_vht_cnt[j - ODM_RATEVHTSS1MCS0]; + dm_soml_table->num_vht_cnt_on[j - ODM_RATEVHTSS1MCS0] += num_rate_diff; + dm_soml_table->pre_num_vht_cnt[j - ODM_RATEVHTSS1MCS0] = dm_soml_table->num_vht_cnt[j - ODM_RATEVHTSS1MCS0]; + num_bytes_diff = dm_soml_table->num_vht_bytes[j - ODM_RATEVHTSS1MCS0] - dm_soml_table->pre_num_vht_bytes[j - ODM_RATEVHTSS1MCS0]; + dm_soml_table->num_vht_bytes_on[j - ODM_RATEVHTSS1MCS0] += num_bytes_diff; + dm_soml_table->pre_num_vht_bytes[j - ODM_RATEVHTSS1MCS0] = dm_soml_table->num_vht_bytes[j - ODM_RATEVHTSS1MCS0]; + } + } + } else if (on_off_state == SOML_OFF) { + if (*dm->channel <= 14) { + for (i = ODM_RATEMCS0; i <= ODM_RATEMCS15; i++) { + num_rate_diff = dm_soml_table->num_ht_cnt[i - ODM_RATEMCS0] - dm_soml_table->pre_num_ht_cnt[i - ODM_RATEMCS0]; + dm_soml_table->num_ht_cnt_off[i - ODM_RATEMCS0] += num_rate_diff; + dm_soml_table->pre_num_ht_cnt[i - ODM_RATEMCS0] = dm_soml_table->num_ht_cnt[i - ODM_RATEMCS0]; + num_bytes_diff = dm_soml_table->num_ht_bytes[i - ODM_RATEMCS0] - dm_soml_table->pre_num_ht_bytes[i - ODM_RATEMCS0]; + dm_soml_table->num_ht_bytes_off[i - ODM_RATEMCS0] += num_bytes_diff; + dm_soml_table->pre_num_ht_bytes[i - ODM_RATEMCS0] = dm_soml_table->num_ht_bytes[i - ODM_RATEMCS0]; + } + } + if (dm->support_ic_type == ODM_RTL8822B) { + for (j = ODM_RATEVHTSS1MCS0; j <= ODM_RATEVHTSS2MCS9; j++) { + num_rate_diff = dm_soml_table->num_vht_cnt[j - ODM_RATEVHTSS1MCS0] - dm_soml_table->pre_num_vht_cnt[j - ODM_RATEVHTSS1MCS0]; + dm_soml_table->num_vht_cnt_off[j - ODM_RATEVHTSS1MCS0] += num_rate_diff; + dm_soml_table->pre_num_vht_cnt[j - ODM_RATEVHTSS1MCS0] = dm_soml_table->num_vht_cnt[j - ODM_RATEVHTSS1MCS0]; + num_bytes_diff = dm_soml_table->num_vht_bytes[j - ODM_RATEVHTSS1MCS0] - dm_soml_table->pre_num_vht_bytes[j - ODM_RATEVHTSS1MCS0]; + dm_soml_table->num_vht_bytes_off[j - ODM_RATEVHTSS1MCS0] += num_bytes_diff; + dm_soml_table->pre_num_vht_bytes[j - ODM_RATEVHTSS1MCS0] = dm_soml_table->num_vht_bytes[j - ODM_RATEVHTSS1MCS0]; + } + } + } +} + +void phydm_adsl( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + u8 i; + u8 next_on_off; + u8 rate_num = 1, rate_ss_shift = 0; + u32 num_total_qam = 0; + u32 num_ht_total_cnt_on = 0, num_ht_total_cnt_off = 0, total_ht_rate_on = 0, total_ht_rate_off = 0; + u32 num_vht_total_cnt_on = 0, num_vht_total_cnt_off = 0, total_vht_rate_on = 0, total_vht_rate_off = 0; + u32 rate_per_pkt_on = 0, rate_per_pkt_off = 0; + u32 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0}; + u8 size = sizeof(ht_reset[0]); + u16 vht_phy_rate_table[] = { + /*@20M*/ + 6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1SS MCS0~9*/ + 13, 26, 39, 52, 78, 104, 117, 130, 156, 180 /*@2SSMCS0~9*/ + }; + + if (dm->support_ic_type & ODM_IC_4SS) + rate_num = 4; + else if (dm->support_ic_type & ODM_IC_3SS) + rate_num = 3; + else if (dm->support_ic_type & ODM_IC_2SS) + rate_num = 2; + + if (dm->support_ic_type & ODM_ADAPTIVE_SOML_SUPPORT_IC) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "soml_state_cnt =((%d))\n", + dm_soml_table->soml_state_cnt); + /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/ + if (dm_soml_table->soml_state_cnt < (dm_soml_table->soml_train_num << 1)) { + if (dm_soml_table->soml_state_cnt == 0) { + phydm_soml_reset_rx_rate(dm); + odm_move_memory(dm, dm_soml_table->num_ht_bytes, ht_reset, HT_RATE_IDX * size); + odm_move_memory(dm, dm_soml_table->num_ht_bytes_on, ht_reset, HT_RATE_IDX * size); + odm_move_memory(dm, dm_soml_table->num_ht_bytes_off, ht_reset, HT_RATE_IDX * size); + odm_move_memory(dm, dm_soml_table->num_vht_bytes, vht_reset, VHT_RATE_IDX * size); + odm_move_memory(dm, dm_soml_table->num_vht_bytes_on, vht_reset, VHT_RATE_IDX * size); + odm_move_memory(dm, dm_soml_table->num_vht_bytes_off, vht_reset, VHT_RATE_IDX * size); + if (dm->support_ic_type == ODM_RTL8822B) { + dm_soml_table->cfo_counter++; + phydm_soml_cfo_process(dm, + &dm_soml_table->cfo_diff_a, + &dm_soml_table->cfo_diff_b); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", dm_soml_table->cfo_counter, dm_soml_table->cfo_diff_a, dm_soml_table->cfo_diff_b); + dm_soml_table->cfo_diff_sum_a += dm_soml_table->cfo_diff_a; + dm_soml_table->cfo_diff_sum_b += dm_soml_table->cfo_diff_b; + } + + dm_soml_table->is_soml_method_enable = 1; + dm_soml_table->soml_state_cnt++; + next_on_off = (dm_soml_table->soml_on_off == SOML_ON) ? SOML_ON : SOML_OFF; + phydm_soml_on_off(dm, next_on_off); + odm_set_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer, dm_soml_table->soml_delay_time); /*@ms*/ + } else if ((dm_soml_table->soml_state_cnt % 2) != 0) { + dm_soml_table->soml_state_cnt++; + odm_move_memory(dm, dm_soml_table->pre_num_ht_cnt, dm_soml_table->num_ht_cnt, HT_RATE_IDX * size); + odm_move_memory(dm, dm_soml_table->pre_num_vht_cnt, dm_soml_table->num_vht_cnt, VHT_RATE_IDX * size); + odm_move_memory(dm, dm_soml_table->pre_num_ht_bytes, dm_soml_table->num_ht_bytes, HT_RATE_IDX * size); + odm_move_memory(dm, dm_soml_table->pre_num_vht_bytes, dm_soml_table->num_vht_bytes, VHT_RATE_IDX * size); + + if (dm->support_ic_type == ODM_RTL8822B) { + dm_soml_table->cfo_counter++; + phydm_soml_cfo_process(dm, + &dm_soml_table->cfo_diff_a, + &dm_soml_table->cfo_diff_b); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", dm_soml_table->cfo_counter, dm_soml_table->cfo_diff_a, dm_soml_table->cfo_diff_b); + dm_soml_table->cfo_diff_sum_a += dm_soml_table->cfo_diff_a; + dm_soml_table->cfo_diff_sum_b += dm_soml_table->cfo_diff_b; + } + odm_set_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer, dm_soml_table->soml_intvl); /*@ms*/ + } else if ((dm_soml_table->soml_state_cnt % 2) == 0) { + if (dm->support_ic_type == ODM_RTL8822B) { + dm_soml_table->cfo_counter++; + phydm_soml_cfo_process(dm, + &dm_soml_table->cfo_diff_a, + &dm_soml_table->cfo_diff_b); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", dm_soml_table->cfo_counter, dm_soml_table->cfo_diff_a, dm_soml_table->cfo_diff_b); + dm_soml_table->cfo_diff_sum_a += dm_soml_table->cfo_diff_a; + dm_soml_table->cfo_diff_sum_b += dm_soml_table->cfo_diff_b; + } + dm_soml_table->soml_state_cnt++; + phydm_soml_statistics(dm, dm_soml_table->soml_on_off); + next_on_off = (dm_soml_table->soml_on_off == SOML_ON) ? SOML_OFF : SOML_ON; + phydm_soml_on_off(dm, next_on_off); + odm_set_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer, dm_soml_table->soml_delay_time); /*@ms*/ + } + } + /*@Decision state: ==============================================================*/ + else { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[Decisoin state ]\n"); + phydm_soml_statistics(dm, dm_soml_table->soml_on_off); + if (*dm->channel <= 14) { + /* @[Search 1st and 2nd rate by counter] */ + for (i = 0; i < rate_num; i++) { + rate_ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "*num_ht_cnt_on HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (rate_ss_shift), (rate_ss_shift + 7), + dm_soml_table->num_ht_cnt_on[rate_ss_shift + 0], dm_soml_table->num_ht_cnt_on[rate_ss_shift + 1], + dm_soml_table->num_ht_cnt_on[rate_ss_shift + 2], dm_soml_table->num_ht_cnt_on[rate_ss_shift + 3], + dm_soml_table->num_ht_cnt_on[rate_ss_shift + 4], dm_soml_table->num_ht_cnt_on[rate_ss_shift + 5], + dm_soml_table->num_ht_cnt_on[rate_ss_shift + 6], dm_soml_table->num_ht_cnt_on[rate_ss_shift + 7]); + } + + for (i = 0; i < rate_num; i++) { + rate_ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "*num_ht_bytes_off HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (rate_ss_shift), (rate_ss_shift + 7), + dm_soml_table->num_ht_cnt_off[rate_ss_shift + 0], dm_soml_table->num_ht_cnt_off[rate_ss_shift + 1], + dm_soml_table->num_ht_cnt_off[rate_ss_shift + 2], dm_soml_table->num_ht_cnt_off[rate_ss_shift + 3], + dm_soml_table->num_ht_cnt_off[rate_ss_shift + 4], dm_soml_table->num_ht_cnt_off[rate_ss_shift + 5], + dm_soml_table->num_ht_cnt_off[rate_ss_shift + 6], dm_soml_table->num_ht_cnt_off[rate_ss_shift + 7]); + } + + for (i = ODM_RATEMCS8; i <= ODM_RATEMCS15; i++) { + num_ht_total_cnt_on += dm_soml_table->num_ht_cnt_on[i - ODM_RATEMCS0]; + num_ht_total_cnt_off += dm_soml_table->num_ht_cnt_off[i - ODM_RATEMCS0]; + total_ht_rate_on += (dm_soml_table->num_ht_cnt_on[i - ODM_RATEMCS0] * phy_rate_table[i]); + total_ht_rate_off += (dm_soml_table->num_ht_cnt_off[i - ODM_RATEMCS0] * phy_rate_table[i]); + } + rate_per_pkt_on = (num_ht_total_cnt_on != 0) ? ((total_ht_rate_on << 3) / num_ht_total_cnt_on) : 0; + rate_per_pkt_off = (num_ht_total_cnt_off != 0) ? ((total_ht_rate_off << 3) / num_ht_total_cnt_off) : 0; + } +#if 0 + if (*dm->channel <= 14) { + /* @[Search 1st and 2ed rate by counter] */ + for (i = 0; i < rate_num; i++) { + rate_ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "*num_ht_bytes_on HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (rate_ss_shift), (rate_ss_shift + 7), + dm_soml_table->num_ht_bytes_on[rate_ss_shift + 0], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 1], + dm_soml_table->num_ht_bytes_on[rate_ss_shift + 2], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 3], + dm_soml_table->num_ht_bytes_on[rate_ss_shift + 4], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 5], + dm_soml_table->num_ht_bytes_on[rate_ss_shift + 6], dm_soml_table->num_ht_bytes_on[rate_ss_shift + 7]); + } + + for (i = 0; i < rate_num; i++) { + rate_ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "*num_ht_bytes_off HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (rate_ss_shift), (rate_ss_shift + 7), + dm_soml_table->num_ht_bytes_off[rate_ss_shift + 0], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 1], + dm_soml_table->num_ht_bytes_off[rate_ss_shift + 2], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 3], + dm_soml_table->num_ht_bytes_off[rate_ss_shift + 4], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 5], + dm_soml_table->num_ht_bytes_off[rate_ss_shift + 6], dm_soml_table->num_ht_bytes_off[rate_ss_shift + 7]); + } + + for (i = ODM_RATEMCS8; i <= ODM_RATEMCS15; i++) { + byte_total_on += dm_soml_table->num_ht_bytes_on[i - ODM_RATEMCS0]; + byte_total_off += dm_soml_table->num_ht_bytes_off[i - ODM_RATEMCS0]; + } + } +#endif + + if (dm->support_ic_type == ODM_RTL8822B) { + dm_soml_table->cfo_diff_avg_a = (dm_soml_table->cfo_counter != 0) ? (dm_soml_table->cfo_diff_sum_a / dm_soml_table->cfo_counter) : 0; + dm_soml_table->cfo_diff_avg_b = (dm_soml_table->cfo_counter != 0) ? (dm_soml_table->cfo_diff_sum_b / dm_soml_table->cfo_counter) : 0; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ cfo_diff_avg_a = %d KHz; cfo_diff_avg_b = %d KHz]\n", + dm_soml_table->cfo_diff_avg_a, + dm_soml_table->cfo_diff_avg_b); + for (i = 0; i < VHT_ORDER_TYPE; i++) + num_total_qam += dm_soml_table->num_vht_qam[i]; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ ((2SS)) BPSK_QPSK_count = %d ; 16QAM_count = %d ; 64QAM_count = %d ; 256QAM_count = %d ; num_total_qam = %d]\n", + dm_soml_table->num_vht_qam[BPSK_QPSK], + dm_soml_table->num_vht_qam[QAM16], + dm_soml_table->num_vht_qam[QAM64], + dm_soml_table->num_vht_qam[QAM256], + num_total_qam); + if (((dm_soml_table->num_vht_qam[QAM256] * 100) > (num_total_qam * dm_soml_table->qam256_dist_th)) && dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qam256_th && dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qam256_th) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ QAM256_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->qam256_dist_th, dm_soml_table->cfo_qam256_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } else if (((dm_soml_table->num_vht_qam[QAM64] * 100) > (num_total_qam * dm_soml_table->qam64_dist_th)) && (dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qam64_th) && (dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qam64_th)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ QAM64_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->qam64_dist_th, dm_soml_table->cfo_qam64_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } else if (((dm_soml_table->num_vht_qam[QAM16] * 100) > (num_total_qam * dm_soml_table->qam16_dist_th)) && (dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qam16_th) && (dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qam16_th)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ QAM16_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->qam16_dist_th, dm_soml_table->cfo_qam16_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } else if (((dm_soml_table->num_vht_qam[BPSK_QPSK] * 100) > (num_total_qam * dm_soml_table->bpsk_qpsk_dist_th)) && (dm_soml_table->cfo_diff_avg_a > dm_soml_table->cfo_qpsk_th) && (dm_soml_table->cfo_diff_avg_b > dm_soml_table->cfo_qpsk_th)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ BPSK_QPSK_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", dm_soml_table->bpsk_qpsk_dist_th, dm_soml_table->cfo_qpsk_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } + + for (i = 0; i < rate_num; i++) { + rate_ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ num_vht_cnt_on VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n", + (i + 1), + dm_soml_table->num_vht_cnt_on[rate_ss_shift + 0], dm_soml_table->num_vht_cnt_on[rate_ss_shift + 1], + dm_soml_table->num_vht_cnt_on[rate_ss_shift + 2], dm_soml_table->num_vht_cnt_on[rate_ss_shift + 3], + dm_soml_table->num_vht_cnt_on[rate_ss_shift + 4], dm_soml_table->num_vht_cnt_on[rate_ss_shift + 5], + dm_soml_table->num_vht_cnt_on[rate_ss_shift + 6], dm_soml_table->num_vht_cnt_on[rate_ss_shift + 7], + dm_soml_table->num_vht_cnt_on[rate_ss_shift + 8], dm_soml_table->num_vht_cnt_on[rate_ss_shift + 9]); + } + + for (i = 0; i < rate_num; i++) { + rate_ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ num_vht_cnt_off VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n", + (i + 1), + dm_soml_table->num_vht_cnt_off[rate_ss_shift + 0], dm_soml_table->num_vht_cnt_off[rate_ss_shift + 1], + dm_soml_table->num_vht_cnt_off[rate_ss_shift + 2], dm_soml_table->num_vht_cnt_off[rate_ss_shift + 3], + dm_soml_table->num_vht_cnt_off[rate_ss_shift + 4], dm_soml_table->num_vht_cnt_off[rate_ss_shift + 5], + dm_soml_table->num_vht_cnt_off[rate_ss_shift + 6], dm_soml_table->num_vht_cnt_off[rate_ss_shift + 7], + dm_soml_table->num_vht_cnt_off[rate_ss_shift + 8], dm_soml_table->num_vht_cnt_off[rate_ss_shift + 9]); + } + + for (i = ODM_RATEVHTSS2MCS0; i <= ODM_RATEVHTSS2MCS9; i++) { + num_vht_total_cnt_on += dm_soml_table->num_vht_cnt_on[i - ODM_RATEVHTSS1MCS0]; + num_vht_total_cnt_off += dm_soml_table->num_vht_cnt_off[i - ODM_RATEVHTSS1MCS0]; + total_vht_rate_on += (dm_soml_table->num_vht_cnt_on[i - ODM_RATEVHTSS1MCS0] * vht_phy_rate_table[i - ODM_RATEVHTSS1MCS0]); + total_vht_rate_off += (dm_soml_table->num_vht_cnt_off[i - ODM_RATEVHTSS1MCS0] * vht_phy_rate_table[i - ODM_RATEVHTSS1MCS0]); + } + rate_per_pkt_on = (num_vht_total_cnt_on != 0) ? ((total_vht_rate_on << 3) / num_vht_total_cnt_on) : 0; + rate_per_pkt_off = (num_vht_total_cnt_off != 0) ? ((total_vht_rate_off << 3) / num_vht_total_cnt_off) : 0; + + #if 0 + for (i = 0; i < rate_num; i++) { + rate_ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ num_vht_bytes_on VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n", + (i + 1), + dm_soml_table->num_vht_bytes_on[rate_ss_shift + 0], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 1], + dm_soml_table->num_vht_bytes_on[rate_ss_shift + 2], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 3], + dm_soml_table->num_vht_bytes_on[rate_ss_shift + 4], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 5], + dm_soml_table->num_vht_bytes_on[rate_ss_shift + 6], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 7], + dm_soml_table->num_vht_bytes_on[rate_ss_shift + 8], dm_soml_table->num_vht_bytes_on[rate_ss_shift + 9]); + } + + for (i = 0; i < rate_num; i++) { + rate_ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ num_vht_bytes_off VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n", + (i + 1), + dm_soml_table->num_vht_bytes_off[rate_ss_shift + 0], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 1], + dm_soml_table->num_vht_bytes_off[rate_ss_shift + 2], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 3], + dm_soml_table->num_vht_bytes_off[rate_ss_shift + 4], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 5], + dm_soml_table->num_vht_bytes_off[rate_ss_shift + 6], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 7], + dm_soml_table->num_vht_bytes_off[rate_ss_shift + 8], dm_soml_table->num_vht_bytes_off[rate_ss_shift + 9]); + } + + for (i = ODM_RATEVHTSS2MCS0; i <= ODM_RATEVHTSS2MCS9; i++) { + byte_total_on += dm_soml_table->num_vht_bytes_on[i - ODM_RATEVHTSS1MCS0]; + byte_total_off += dm_soml_table->num_vht_bytes_off[i - ODM_RATEVHTSS1MCS0]; + } + #endif + } + + /* @[Decision] */ + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ rate_per_pkt_on = %d ; rate_per_pkt_off = %d ]\n", + rate_per_pkt_on, rate_per_pkt_off); + if (rate_per_pkt_on > rate_per_pkt_off) { + next_on_off = SOML_ON; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ rate_per_pkt_on > rate_per_pkt_off ==> SOML_ON ]\n"); + } else if (rate_per_pkt_on < rate_per_pkt_off) { + next_on_off = SOML_OFF; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ rate_per_pkt_on < rate_per_pkt_off ==> SOML_OFF ]\n"); + } else { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ stay at soml_last_state ]\n"); + next_on_off = dm_soml_table->soml_last_state; + } + #if 0 + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ byte_total_on = %d ; byte_total_off = %d ]\n", + byte_total_on, byte_total_off); + if (byte_total_on > byte_total_off) { + next_on_off = SOML_ON; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ byte_total_on > byte_total_off ==> SOML_ON ]\n"); + } else if (byte_total_on < byte_total_off) { + next_on_off = SOML_OFF; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ byte_total_on < byte_total_off ==> SOML_OFF ]\n"); + } else { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ stay at soml_last_state ]\n"); + next_on_off = dm_soml_table->soml_last_state; + } + #endif + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, next_on_off); + dm_soml_table->soml_last_state = next_on_off; + } + } +} +void phydm_adaptive_soml_reset( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + dm_soml_table->soml_state_cnt = 0; + dm_soml_table->is_soml_method_enable = 0; + dm_soml_table->soml_counter = 0; +} + +void phydm_set_adsl_val( + void *dm_void, + u32 *val_buf, + u8 val_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (val_len != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][ADSL]Need val_len=1\n"); + return; + } + + phydm_soml_on_off(dm, (u8)val_buf[1]); +} + +void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS31) + dm_soml_table->num_ht_bytes[rate_id - ODM_RATEMCS0] += length; + else if ((rate_id >= ODM_RATEVHTSS1MCS0) && (rate_id <= ODM_RATEVHTSS4MCS9)) + dm_soml_table->num_vht_bytes[rate_id - ODM_RATEVHTSS1MCS0] += length; + +} + +void phydm_adaptive_soml_timers(void *dm_void, u8 state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + if (state == INIT_SOML_TIMMER) { + odm_initialize_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer, + (void *)phydm_adaptive_soml_callback, NULL, "phydm_adaptive_soml_timer"); + } else if (state == CANCEL_SOML_TIMMER) { + odm_cancel_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer); + } else if (state == RELEASE_SOML_TIMMER) { + odm_release_timer(dm, &dm_soml_table->phydm_adaptive_soml_timer); + } +} + +void phydm_adaptive_soml_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; +#if 0 + if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[Return] Not Support Adaptive SOML\n"); + return; + } +#endif + PHYDM_DBG(dm, DBG_ADPTV_SOML, "%s\n", __func__); + + dm_soml_table->soml_state_cnt = 0; + dm_soml_table->soml_delay_time = 40; + dm_soml_table->soml_intvl = 150; + dm_soml_table->soml_train_num = 4; + dm_soml_table->is_soml_method_enable = 0; + dm_soml_table->soml_counter = 0; + dm_soml_table->soml_period = 1; + dm_soml_table->soml_select = 0; + dm_soml_table->cfo_counter = 0; + dm_soml_table->cfo_diff_sum_a = 0; + dm_soml_table->cfo_diff_sum_b = 0; + + dm_soml_table->cfo_qpsk_th = 94; + dm_soml_table->cfo_qam16_th = 38; + dm_soml_table->cfo_qam64_th = 17; + dm_soml_table->cfo_qam256_th = 7; + + dm_soml_table->bpsk_qpsk_dist_th = 20; + dm_soml_table->qam16_dist_th = 20; + dm_soml_table->qam64_dist_th = 20; + dm_soml_table->qam256_dist_th = 20; + + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, 0x988, BIT(25), 1); +} + +void phydm_adaptive_soml(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[Return!!!] Not Support Adaptive SOML Function\n"); + return; + } + + if (dm->pause_ability & ODM_BB_ADAPTIVE_SOML) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "Return: Pause ADSL in LV=%d\n", + dm->pause_lv_table.lv_adsl); + return; + } + + if (dm_soml_table->soml_counter < dm_soml_table->soml_period) { + dm_soml_table->soml_counter++; + return; + } + dm_soml_table->soml_counter = 0; + dm_soml_table->soml_state_cnt = 0; + dm_soml_table->cfo_counter = 0; + dm_soml_table->cfo_diff_sum_a = 0; + dm_soml_table->cfo_diff_sum_b = 0; + + phydm_soml_reset_qam(dm); + + if (dm_soml_table->soml_select == 0) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ Adaptive SOML Training !!!]\n"); + } else if (dm_soml_table->soml_select == 1) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n"); + phydm_soml_on_off(dm, SOML_ON); + return; + } else if (dm_soml_table->soml_select == 2) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n"); + phydm_soml_on_off(dm, SOML_OFF); + return; + } + + if (dm->support_ic_type & ODM_ADAPTIVE_SOML_SUPPORT_IC) + phydm_adsl(dm); +} + +void phydm_enable_adaptive_soml(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s]\n", __func__); + dm->support_ability |= ODM_BB_ADAPTIVE_SOML; + phydm_soml_on_off(dm, SOML_ON); +} + +void phydm_stop_adaptive_soml(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s]\n", __func__); + dm->support_ability &= ~ODM_BB_ADAPTIVE_SOML; + phydm_soml_on_off(dm, SOML_ON); +} + +void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl, + u8 period, u8 delay_time) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *dm_soml_table = &dm->dm_soml_table; + + dm_soml_table->soml_train_num = train_num; + dm_soml_table->soml_intvl = intvl; + dm_soml_table->soml_period = period; + dm_soml_table->soml_delay_time = delay_time; +} +#endif /* @end of CONFIG_ADAPTIVE_SOML*/ + +void phydm_init_soft_ml_setting(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 soml_mask = BIT(31) | BIT(30) | BIT(29) | BIT(28); + +#if (RTL8822B_SUPPORT == 1) + if (!*dm->mp_mode) { + if (dm->support_ic_type & ODM_RTL8822B) { +#if 0 + /*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xd10a0000);*/ +#endif + phydm_somlrxhp_setting(dm, true); + dm->bsomlenabled = true; + } + } +#endif +#if (RTL8821C_SUPPORT == 1) + if (!*dm->mp_mode) { + if (dm->support_ic_type & ODM_RTL8821C) + odm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd); + } +#endif +#if (RTL8195B_SUPPORT == 1) + if (!*dm->mp_mode) { + if (dm->support_ic_type & ODM_RTL8195B) + odm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd); + } +#endif +} diff --git a/hal/phydm/phydm_soml.h b/hal/phydm/phydm_soml.h new file mode 100644 index 0000000..5c44c69 --- /dev/null +++ b/hal/phydm/phydm_soml.h @@ -0,0 +1,210 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __PHYDMSOML_H__ +#define __PHYDMSOML_H__ + +/*@#define ADAPTIVE_SOML_VERSION "1.0" Byte counter version*/ +#define ADAPTIVE_SOML_VERSION "2.0" /*@add avg. phy rate decision 20180126*/ + +#define ODM_ADAPTIVE_SOML_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)/*@jj add 20170822*/ + +#define INIT_SOML_TIMMER 0 +#define CANCEL_SOML_TIMMER 1 +#define RELEASE_SOML_TIMMER 2 + +#define SOML_RSSI_TH_HIGH 25 +#define SOML_RSSI_TH_LOW 20 + +#define HT_RATE_IDX 32 +#define VHT_RATE_IDX 40 + +#define HT_ORDER_TYPE 3 +#define VHT_ORDER_TYPE 4 + +#if 0 +#define CFO_QPSK_TH 20 +#define CFO_QAM16_TH 20 +#define CFO_QAM64_TH 20 +#define CFO_QAM256_TH 20 + +#define BPSK_QPSK_DIST 20 +#define QAM16_DIST 30 +#define QAM64_DIST 30 +#define QAM256_DIST 20 +#endif +#define HT_TYPE 1 +#define VHT_TYPE 2 + +#define SOML_ON 1 +#define SOML_OFF 0 + +#ifdef CONFIG_ADAPTIVE_SOML + +struct adaptive_soml { + u8 rvrt_val; + boolean is_soml_method_enable; + u8 soml_on_off; + u8 soml_state_cnt; + u8 soml_delay_time; + u8 soml_intvl; + u8 soml_train_num; + u8 soml_counter; + u8 soml_period; + u8 soml_select; + u8 soml_last_state; + u8 cfo_qpsk_th; + u8 cfo_qam16_th; + u8 cfo_qam64_th; + u8 cfo_qam256_th; + u8 bpsk_qpsk_dist_th; + u8 qam16_dist_th; + u8 qam64_dist_th; + u8 qam256_dist_th; + u8 cfo_counter; + s32 cfo_diff_a; + s32 cfo_diff_b; + s32 cfo_diff_sum_a; + s32 cfo_diff_sum_b; + s32 cfo_diff_avg_a; + s32 cfo_diff_avg_b; + u32 num_ht_cnt[HT_RATE_IDX]; + u32 pre_num_ht_cnt[HT_RATE_IDX]; + u32 num_ht_cnt_on[HT_RATE_IDX]; + u32 num_ht_cnt_off[HT_RATE_IDX]; + + u32 num_vht_cnt[VHT_RATE_IDX]; + u32 pre_num_vht_cnt[VHT_RATE_IDX]; + u32 num_vht_cnt_on[VHT_RATE_IDX]; + u32 num_vht_cnt_off[VHT_RATE_IDX]; + + u32 num_ht_qam[HT_ORDER_TYPE]; + u32 num_ht_bytes[HT_RATE_IDX]; + u32 pre_num_ht_bytes[HT_RATE_IDX]; + u32 num_ht_bytes_on[HT_RATE_IDX]; + u32 num_ht_bytes_off[HT_RATE_IDX]; + u32 num_vht_qam[VHT_ORDER_TYPE]; + u32 num_qry_mu_vht_pkt[VHT_RATE_IDX]; + u32 num_vht_bytes[VHT_RATE_IDX]; + u32 pre_num_vht_bytes[VHT_RATE_IDX]; + u32 num_vht_bytes_on[VHT_RATE_IDX]; + u32 num_vht_bytes_off[VHT_RATE_IDX]; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM phydm_adaptive_soml_workitem; +#endif +#endif + struct phydm_timer_list phydm_adaptive_soml_timer; + +}; + +enum qam_order { + BPSK_QPSK = 0, + QAM16 = 1, + QAM64 = 2, + QAM256 = 3 +}; + +void phydm_dynamicsoftmletting(void *dm_void); + +void phydm_soml_on_off( + void *dm_void, + u8 swch); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_adaptive_soml_callback( + struct phydm_timer_list *timer); + +void phydm_adaptive_soml_workitem_callback( + void *context); + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void phydm_adaptive_soml_callback( + void *dm_void); + +void phydm_adaptive_soml_workitem_callback( + void *context); + +#else +void phydm_adaptive_soml_callback( + void *dm_void); +#endif + +void phydm_rx_rate_for_soml( + void *dm_void, + void *pkt_info_void); + +void phydm_rx_qam_for_soml( + void *dm_void, + void *pkt_info_void); + +void phydm_soml_reset_rx_rate( + void *dm_void); + +void phydm_soml_reset_qam( + void *dm_void); + +void phydm_soml_cfo_process( + void *dm_void, + s32 *diff_a, + s32 *diff_b); + +void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_soml_statistics( + void *dm_void, + u8 on_off_state + + ); + +void phydm_adsl( + void *dm_void); + +void phydm_adaptive_soml_reset( + void *dm_void); + +void phydm_set_adsl_val( + void *dm_void, + u32 *val_buf, + u8 val_len); + +void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length); + +void phydm_adaptive_soml_timers(void *dm_void, u8 state); + +void phydm_adaptive_soml_init(void *dm_void); + +void phydm_adaptive_soml(void *dm_void); + +void phydm_enable_adaptive_soml(void *dm_void); + +void phydm_stop_adaptive_soml(void *dm_void); + +void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl, + u8 period, u8 delay_time); +#endif +void phydm_init_soft_ml_setting(void *dm_void); +#endif /*@#ifndef __PHYDMSOML_H__*/ diff --git a/hal/phydm/phydm_types.h b/hal/phydm/phydm_types.h index ee7a15e..820394c 100644 --- a/hal/phydm/phydm_types.h +++ b/hal/phydm/phydm_types.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -8,34 +8,44 @@ * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. * - ******************************************************************************/ + * Larry Finger + * + *****************************************************************************/ #ifndef __ODM_TYPES_H__ #define __ODM_TYPES_H__ - /*Define Different SW team support*/ -#define ODM_AP 0x01 /*BIT0*/ -#define ODM_CE 0x04 /*BIT2*/ -#define ODM_WIN 0x08 /*BIT3*/ -#define ODM_ADSL 0x10 /*BIT4*/ -#define ODM_IOT 0x20 /*BIT5*/ +#define ODM_AP 0x01 /*BIT(0)*/ +#define ODM_CE 0x04 /*BIT(2)*/ +#define ODM_WIN 0x08 /*BIT(3)*/ +#define ODM_ADSL 0x10 +/*BIT(4)*/ /*already combine with ODM_AP, and is nouse now*/ +#define ODM_IOT 0x20 /*BIT(5)*/ + +/*For FW API*/ +#define __iram_odm_func__ /*Deifne HW endian support*/ #define ODM_ENDIAN_BIG 0 #define ODM_ENDIAN_LITTLE 1 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->DM_OutSrc))) + #define GET_PDM_ODM(__padapter) ((struct dm_struct*)(&(GET_HAL_DATA(__padapter))->DM_OutSrc)) #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->odmpriv))) + #define GET_PDM_ODM(__padapter) ((struct dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv)) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #define GET_PDM_ODM(__padapter) ((struct dm_struct*)(&__padapter->pshare->_dmODM)) #endif #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) @@ -47,24 +57,23 @@ enum hal_status { HAL_STATUS_SUCCESS, HAL_STATUS_FAILURE, - /*RT_STATUS_PENDING, +#if 0 + RT_STATUS_PENDING, RT_STATUS_RESOURCE, RT_STATUS_INVALID_CONTEXT, RT_STATUS_INVALID_PARAMETER, RT_STATUS_NOT_SUPPORT, - RT_STATUS_OS_API_FAILED,*/ + RT_STATUS_OS_API_FAILED, +#endif }; -#if (DM_ODM_SUPPORT_TYPE == ODM_AP) - #define MP_DRIVER 0 -#endif #if (DM_ODM_SUPPORT_TYPE != ODM_WIN) #define VISTA_USB_RX_REVISE 0 /* - * Declare for ODM spin lock defintion temporarily fro compile pass. - * */ + * Declare for ODM spin lock definition temporarily fro compile pass. + */ enum rt_spinlock_type { RT_TX_SPINLOCK = 1, RT_RX_SPINLOCK = 2, @@ -76,16 +85,19 @@ enum rt_spinlock_type { RT_CHNLOP_SPINLOCK = 9, RT_RF_OPERATE_SPINLOCK = 10, RT_INITIAL_SPINLOCK = 11, - RT_RF_STATE_SPINLOCK = 12, /* For RF state. Added by Bruce, 2007-10-30. */ + RT_RF_STATE_SPINLOCK = 12, + /* For RF state. Added by Bruce, 2007-10-30. */ #if VISTA_USB_RX_REVISE RT_USBRX_CONTEXT_SPINLOCK = 13, - RT_USBRX_POSTPROC_SPINLOCK = 14, /* protect data of adapter->IndicateW/ IndicateR */ + RT_USBRX_POSTPROC_SPINLOCK = 14, + /* protect data of adapter->IndicateW/ IndicateR */ #endif /* Shall we define Ndis 6.2 SpinLock Here ? */ RT_PORT_SPINLOCK = 16, RT_VNIC_SPINLOCK = 17, RT_HVL_SPINLOCK = 18, - RT_H2C_SPINLOCK = 20, /* For H2C cmd. Added by tynli. 2009.11.09. */ + RT_H2C_SPINLOCK = 20, + /* For H2C cmd. Added by tynli. 2009.11.09. */ rt_bt_data_spinlock = 25, @@ -114,7 +126,6 @@ enum rt_spinlock_type { #endif - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) #define sta_info _RT_WLAN_STA #define __func__ __FUNCTION__ @@ -135,44 +146,16 @@ enum rt_spinlock_type { #define u64 u8Byte #define s64 s8Byte - #define timer_list _RT_TIMER - - -#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) - - /* To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. */ - #define ADSL_AP_BUILD_WORKAROUND - #define AP_BUILD_WORKAROUND + #define phydm_timer_list _RT_TIMER - #ifdef AP_BUILD_WORKAROUND - #include "../typedef.h" - #else - typedef void void, *void *; - typedef unsigned char boolean, *boolean *; - typedef unsigned char u8, *u8 *; - typedef unsigned short u16, *u16 *; - typedef unsigned int u32, *u32 *; - typedef unsigned long long u64, *u64 *; - #if 1 - /* In ARM platform, system would use the type -- "char" as "unsigned char" - * And we only use s8/s8* as INT8 now, so changes the type of s8.*/ - typedef signed char s8, *s8 *; - #else - typedef char s8, *s8 *; - #endif - typedef short s16, *s16 *; - typedef long s32, *s32 *; - typedef long long s64, *s64 *; - #endif +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "../typedef.h" #ifdef CONFIG_PCI_HCI #define DEV_BUS_TYPE RT_PCI_INTERFACE #endif - #define _TRUE 1 - #define _FALSE 0 - #if (defined(TESTCHIP_SUPPORT)) #define PHYDM_TESTCHIP_SUPPORT 1 #else @@ -182,43 +165,41 @@ enum rt_spinlock_type { #define sta_info stat_info #define boolean bool -#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - #include - #if 0 - typedef u8 u8, *u8 *; - typedef u16 u16, *u16 *; - typedef u32 u32, *u32 *; - typedef u64 u64, *u64 *; - typedef s8 s8, *s8 *; - typedef s16 s16, *s16 *; - typedef s32 s32, *s32 *; - typedef s64 s64, *s64 *; - #elif 0 - #define u8 u8 - #define u8 *u8* + #define phydm_timer_list timer_list - #define u16 u16 - #define u16 *u16* +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) - #define u32 u32 - #define u32 *u32* + #include - #define u64 u64 - #define u64* u64* + #define DEV_BUS_TYPE RT_PCI_INTERFACE - #define s8 s8 - #define s8* s8* + #if defined(__LITTLE_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #elif defined(__BIG_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #else + #error + #endif - #define s16 s16 - #define s16* s16* + /* define useless flag to avoid compile warning */ + #define USE_WORKITEM 0 + #define FOR_BRAZIL_PRETEST 0 + #define FPGA_TWO_MAC_VERIFICATION 0 + #define RTL8881A_SUPPORT 0 + #define PHYDM_TESTCHIP_SUPPORT 0 - #define s32 s32 - #define s32* s32* - #define s64 s64 - #define s64* s64* + #define RATE_ADAPTIVE_SUPPORT 0 + #define POWER_TRAINING_ACTIVE 0 + + #define sta_info rtl_sta_info + #define boolean bool + + #define phydm_timer_list timer_list + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include - #endif #ifdef CONFIG_USB_HCI #define DEV_BUS_TYPE RT_USB_INTERFACE #elif defined(CONFIG_PCI_HCI) @@ -232,19 +213,15 @@ enum rt_spinlock_type { #if defined(CONFIG_LITTLE_ENDIAN) #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE - #elif defined (CONFIG_BIG_ENDIAN) + #elif defined(CONFIG_BIG_ENDIAN) #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG #endif #define boolean bool - #define true _TRUE - #define false _FALSE - - - #define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 24, 1, __value) - #define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 25, 1, __value) - #define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+28, 29, 1, __value) + #define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 24, 1, __value) + #define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 25, 1, __value) + #define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 28, 29, 1, __value) /* define useless flag to avoid compile warning */ #define USE_WORKITEM 0 @@ -257,9 +234,57 @@ enum rt_spinlock_type { #else #define PHYDM_TESTCHIP_SUPPORT 0 #endif + + #define phydm_timer_list rtw_timer_list + +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + #define boolean bool + #define true _TRUE + #define false _FALSE + + // for power limit table + enum odm_pw_lmt_regulation_type { + PW_LMT_REGU_NULL = 0, + PW_LMT_REGU_FCC = 1, + PW_LMT_REGU_ETSI = 2, + PW_LMT_REGU_MKK = 3, + PW_LMT_REGU_WW13 = 4 + }; + + enum odm_pw_lmt_band_type { + PW_LMT_BAND_NULL = 0, + PW_LMT_BAND_2_4G = 1, + PW_LMT_BAND_5G = 2 + }; + + enum odm_pw_lmt_bandwidth_type { + PW_LMT_BW_NULL = 0, + PW_LMT_BW_20M = 1, + PW_LMT_BW_40M = 2, + PW_LMT_BW_80M = 3 + }; + + enum odm_pw_lmt_ratesection_type { + PW_LMT_RS_NULL = 0, + PW_LMT_RS_CCK = 1, + PW_LMT_RS_OFDM = 2, + PW_LMT_RS_HT = 3, + PW_LMT_RS_VHT = 4 + }; + + enum odm_pw_lmt_rfpath_type { + PW_LMT_PH_NULL = 0, + PW_LMT_PH_1T = 1, + PW_LMT_PH_2T = 2, + PW_LMT_PH_3T = 3, + PW_LMT_PH_4T = 4 + }; + + #define phydm_timer_list timer_list + #endif -#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i+1]; } while (0) +#define READ_NEXT_PAIR(v1, v2, i) do { if (i + 2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i + 1]; } while (0) #define COND_ELSE 2 #define COND_ENDIF 3 @@ -270,21 +295,22 @@ enum rt_spinlock_type { #define MASKHWORD 0xffff0000 #define MASKLWORD 0x0000ffff #define MASKDWORD 0xffffffff + #define MASK7BITS 0x7f #define MASK12BITS 0xfff #define MASKH4BITS 0xf0000000 #define MASK20BITS 0xfffff +#define MASK24BITS 0xffffff #define MASKOFDM_D 0xffc00000 #define MASKCCK 0x3f3f3f3f -#define RFREGOFFSETMASK 0xfffff -#define MASKH3BYTES 0xffffff00 -#define MASKL3BYTES 0x00ffffff -#define MASKBYTE2HIGHNIBBLE 0x00f00000 -#define MASKBYTE3LOWNIBBLE 0x0f000000 -#define MASKL3BYTES 0x00ffffff -#define RFREGOFFSETMASK 0xfffff +#define RFREGOFFSETMASK 0xfffff +#define RFREG_MASK 0xfffff -#include "phydm_features.h" +#define MASKH3BYTES 0xffffff00 +#define MASKL3BYTES 0x00ffffff +#define MASKBYTE2HIGHNIBBLE 0x00f00000 +#define MASKBYTE3LOWNIBBLE 0x0f000000 +#define MASKL3BYTES 0x00ffffff #endif /* __ODM_TYPES_H__ */ diff --git a/hal/phydm/rtl8821c/halhwimg8821c_bb.c b/hal/phydm/rtl8821c/halhwimg8821c_bb.c index ac57619..63eeba6 100644 --- a/hal/phydm/rtl8821c/halhwimg8821c_bb.c +++ b/hal/phydm/rtl8821c/halhwimg8821c_bb.c @@ -1,118 +1,106 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ -/*Image2HeaderVersion: 3.4*/ +/*Image2HeaderVersion: R3 1.0*/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (RTL8821C_SUPPORT == 1) static boolean check_positive( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2, const u32 condition3, const u32 condition4 ) { - u8 _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ - ((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/ - ((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/ - ((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */ - ((p_dm_odm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/ - ((p_dm_odm->board_type & BIT(1)) >> 1) << 5; /* _NGFF*/ - u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; - u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; - u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; + u8 cut_version_for_para = (dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version; + u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; u32 driver1 = cut_version_for_para << 24 | - (p_dm_odm->support_interface & 0xF0) << 16 | - p_dm_odm->support_platform << 16 | + (dm->support_interface & 0xF0) << 16 | + dm->support_platform << 16 | pkg_type_for_para << 12 | - (p_dm_odm->support_interface & 0x0F) << 8 | - _board_type; + (dm->support_interface & 0x0F) << 8 | + dm->rfe_type; - u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | - (p_dm_odm->type_gpa & 0xFF) << 8 | - (p_dm_odm->type_alna & 0xFF) << 16 | - (p_dm_odm->type_apa & 0xFF) << 24; + u32 driver2 = (dm->type_glna & 0xFF) << 0 | + (dm->type_gpa & 0xFF) << 8 | + (dm->type_alna & 0xFF) << 16 | + (dm->type_apa & 0xFF) << 24; u32 driver3 = 0; - u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | - (p_dm_odm->type_gpa & 0xFF00) | - (p_dm_odm->type_alna & 0xFF00) << 8 | - (p_dm_odm->type_apa & 0xFF00) << 16; + u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | + (dm->type_gpa & 0xFF00) | + (dm->type_alna & 0xFF00) << 8 | + (dm->type_apa & 0xFF00) << 16; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, cond1, cond2, cond3, cond4); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, driver1, driver2, driver3, driver4); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type)); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Platform, Interface) = (0x%X, 0x%X)\n", + dm->support_platform, dm->support_interface); + PHYDM_DBG(dm, ODM_COMP_INIT, " (RFE, Package) = (0x%X, 0x%X)\n", + dm->rfe_type, dm->package_type); /*============== value Defined Check ===============*/ - /*QFN type [15:12] and cut version [27:24] need to do value check*/ + /*cut version [27:24] need to do value check*/ + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return false; + /*pkg type [15:12] need to do value check*/ if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) return false; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return false; + /*interface [11:8] need to do value check*/ + if (((cond1 & 0x00000F00) != 0) && ((cond1 & 0x00000F00) != (driver1 & 0x00000F00))) + return false; /*=============== Bit Defined Check ================*/ /* We don't care [31:28] */ - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u32 bit_mask = 0; - - if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/ - return true; - - if ((cond1 & BIT(0)) != 0) /*GLNA*/ - bit_mask |= 0x000000FF; - if ((cond1 & BIT(1)) != 0) /*GPA*/ - bit_mask |= 0x0000FF00; - if ((cond1 & BIT(2)) != 0) /*ALNA*/ - bit_mask |= 0x00FF0000; - if ((cond1 & BIT(3)) != 0) /*APA*/ - bit_mask |= 0xFF000000; - - if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/ - return true; - else - return false; - } else + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return true; + else return false; } static boolean check_negative( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2 ) @@ -125,7 +113,72 @@ check_negative( ******************************************************************************/ u32 array_mp_8821c_agc_tab[] = { - 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x80001004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000003, + 0x81C, 0xFA020003, + 0x81C, 0xF9040003, + 0x81C, 0xF8060003, + 0x81C, 0xF7080003, + 0x81C, 0xF60A0003, + 0x81C, 0xF50C0003, + 0x81C, 0xF40E0003, + 0x81C, 0xF3100003, + 0x81C, 0xF2120003, + 0x81C, 0xF1140003, + 0x81C, 0xF0160003, + 0x81C, 0xEF180003, + 0x81C, 0xEE1A0003, + 0x81C, 0xED1C0003, + 0x81C, 0xEC1E0003, + 0x81C, 0xEB200003, + 0x81C, 0xEA220003, + 0x81C, 0xE9240003, + 0x81C, 0xE8260003, + 0x81C, 0xE7280003, + 0x81C, 0xE62A0003, + 0x81C, 0xE52C0003, + 0x81C, 0xE42E0003, + 0x81C, 0xE3300003, + 0x81C, 0xE2320003, + 0x81C, 0xE1340003, + 0x81C, 0xC4360003, + 0x81C, 0xC3380003, + 0x81C, 0xC23A0003, + 0x81C, 0xC13C0003, + 0x81C, 0x883E0003, + 0x81C, 0x87400003, + 0x81C, 0x86420003, + 0x81C, 0x85440003, + 0x81C, 0x84460003, + 0x81C, 0x83480003, + 0x81C, 0x824A0003, + 0x81C, 0x814C0003, + 0x81C, 0x804E0003, + 0x81C, 0x64500003, + 0x81C, 0x63520003, + 0x81C, 0x62540003, + 0x81C, 0x61560003, + 0x81C, 0x60580003, + 0x81C, 0x475A0003, + 0x81C, 0x465C0003, + 0x81C, 0x455E0003, + 0x81C, 0x44600003, + 0x81C, 0x43620003, + 0x81C, 0x42640003, + 0x81C, 0x41660003, + 0x81C, 0x40680003, + 0x81C, 0x236A0003, + 0x81C, 0x226C0003, + 0x81C, 0x056E0003, + 0x81C, 0x04700003, + 0x81C, 0x03720003, + 0x81C, 0x02740003, + 0x81C, 0x01760003, + 0x81C, 0x01780003, + 0x81C, 0x017A0003, + 0x81C, 0x017C0003, + 0x81C, 0x017E0003, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFB000003, 0x81C, 0xFA020003, 0x81C, 0xF9040003, @@ -256,7 +309,7 @@ u32 array_mp_8821c_agc_tab[] = { 0x81C, 0x017C0003, 0x81C, 0x017E0003, 0xB0000000, 0x00000000, - 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x80001004, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFD000103, 0x81C, 0xFC020103, 0x81C, 0xFB040103, @@ -321,6 +374,71 @@ u32 array_mp_8821c_agc_tab[] = { 0x81C, 0x017A0103, 0x81C, 0x017C0103, 0x81C, 0x017E0103, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF6000103, + 0x81C, 0xF5020103, + 0x81C, 0xF4040103, + 0x81C, 0xF3060103, + 0x81C, 0xF2080103, + 0x81C, 0xF10A0103, + 0x81C, 0xF00C0103, + 0x81C, 0xEF0E0103, + 0x81C, 0xEE100103, + 0x81C, 0xED120103, + 0x81C, 0xEC140103, + 0x81C, 0xCE160103, + 0x81C, 0xEA180103, + 0x81C, 0xE91A0103, + 0x81C, 0xE81C0103, + 0x81C, 0xE71E0103, + 0x81C, 0xE6200103, + 0x81C, 0xE5220103, + 0x81C, 0xE4240103, + 0x81C, 0xE3260103, + 0x81C, 0xE2280103, + 0x81C, 0xE12A0103, + 0x81C, 0xC32C0103, + 0x81C, 0xA62E0103, + 0x81C, 0xC1300103, + 0x81C, 0xA4320103, + 0x81C, 0xA3340103, + 0x81C, 0xA2360103, + 0x81C, 0xA1380103, + 0x81C, 0x833A0103, + 0x81C, 0x823C0103, + 0x81C, 0x813E0103, + 0x81C, 0x63400103, + 0x81C, 0x62420103, + 0x81C, 0x61440103, + 0x81C, 0x60460103, + 0x81C, 0x25480103, + 0x81C, 0x244A0103, + 0x81C, 0x234C0103, + 0x81C, 0x064E0103, + 0x81C, 0x21500103, + 0x81C, 0x04520103, + 0x81C, 0x03540103, + 0x81C, 0x02560103, + 0x81C, 0x01580103, + 0x81C, 0x005A0103, + 0x81C, 0x005C0103, + 0x81C, 0x005E0103, + 0x81C, 0x00600103, + 0x81C, 0x00620103, + 0x81C, 0x00640103, + 0x81C, 0x00660103, + 0x81C, 0x00680103, + 0x81C, 0x006A0103, + 0x81C, 0x006C0103, + 0x81C, 0x006E0103, + 0x81C, 0x00700103, + 0x81C, 0x00720103, + 0x81C, 0x00740103, + 0x81C, 0x00760103, + 0x81C, 0x00780103, + 0x81C, 0x007A0103, + 0x81C, 0x007C0103, + 0x81C, 0x007E0103, 0xA0000000, 0x00000000, 0x81C, 0xFD000103, 0x81C, 0xFC020103, @@ -387,7 +505,7 @@ u32 array_mp_8821c_agc_tab[] = { 0x81C, 0x017C0103, 0x81C, 0x017E0103, 0xB0000000, 0x00000000, - 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x80001004, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFB000203, 0x81C, 0xFA020203, 0x81C, 0xF9040203, @@ -452,6 +570,71 @@ u32 array_mp_8821c_agc_tab[] = { 0x81C, 0x017A0203, 0x81C, 0x017C0203, 0x81C, 0x017E0203, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF6000203, + 0x81C, 0xF5020203, + 0x81C, 0xF4040203, + 0x81C, 0xF3060203, + 0x81C, 0xF2080203, + 0x81C, 0xF10A0203, + 0x81C, 0xF00C0203, + 0x81C, 0xEF0E0203, + 0x81C, 0xEE100203, + 0x81C, 0xED120203, + 0x81C, 0xEC140203, + 0x81C, 0xEB160203, + 0x81C, 0xEA180203, + 0x81C, 0xE91A0203, + 0x81C, 0xE81C0203, + 0x81C, 0xE71E0203, + 0x81C, 0xE6200203, + 0x81C, 0xE5220203, + 0x81C, 0xE4240203, + 0x81C, 0xE3260203, + 0x81C, 0xE2280203, + 0x81C, 0xE12A0203, + 0x81C, 0xE02C0203, + 0x81C, 0xC22E0203, + 0x81C, 0xC1300203, + 0x81C, 0xC0320203, + 0x81C, 0xA3340203, + 0x81C, 0xA2360203, + 0x81C, 0xA1380203, + 0x81C, 0xA03A0203, + 0x81C, 0x833C0203, + 0x81C, 0x823E0203, + 0x81C, 0x81400203, + 0x81C, 0x80420203, + 0x81C, 0x62440203, + 0x81C, 0x61460203, + 0x81C, 0x42480203, + 0x81C, 0x414A0203, + 0x81C, 0x234C0203, + 0x81C, 0x224E0203, + 0x81C, 0x21500203, + 0x81C, 0x20520203, + 0x81C, 0x03540203, + 0x81C, 0x02560203, + 0x81C, 0x01580203, + 0x81C, 0x005A0203, + 0x81C, 0x005C0203, + 0x81C, 0x005E0203, + 0x81C, 0x00600203, + 0x81C, 0x00620203, + 0x81C, 0x00640203, + 0x81C, 0x00660203, + 0x81C, 0x00680203, + 0x81C, 0x006A0203, + 0x81C, 0x006C0203, + 0x81C, 0x006E0203, + 0x81C, 0x00700203, + 0x81C, 0x00720203, + 0x81C, 0x00740203, + 0x81C, 0x00760203, + 0x81C, 0x00780203, + 0x81C, 0x007A0203, + 0x81C, 0x007C0203, + 0x81C, 0x007E0203, 0xA0000000, 0x00000000, 0x81C, 0xFC000203, 0x81C, 0xFB020203, @@ -518,7 +701,7 @@ u32 array_mp_8821c_agc_tab[] = { 0x81C, 0x017C0203, 0x81C, 0x017E0203, 0xB0000000, 0x00000000, - 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x80001004, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFB000303, 0x81C, 0xFA020303, 0x81C, 0xF9040303, @@ -583,6 +766,71 @@ u32 array_mp_8821c_agc_tab[] = { 0x81C, 0x017A0303, 0x81C, 0x017C0303, 0x81C, 0x017E0303, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xF5000303, + 0x81C, 0xF4020303, + 0x81C, 0xF3040303, + 0x81C, 0xF2060303, + 0x81C, 0xF1080303, + 0x81C, 0xF00A0303, + 0x81C, 0xEF0C0303, + 0x81C, 0xEE0E0303, + 0x81C, 0xED100303, + 0x81C, 0xEC120303, + 0x81C, 0xEB140303, + 0x81C, 0xEA160303, + 0x81C, 0xE9180303, + 0x81C, 0xE81A0303, + 0x81C, 0xE71C0303, + 0x81C, 0xE61E0303, + 0x81C, 0xE5200303, + 0x81C, 0xE4220303, + 0x81C, 0xE3240303, + 0x81C, 0xE2260303, + 0x81C, 0xE1280303, + 0x81C, 0xE02A0303, + 0x81C, 0xA72C0303, + 0x81C, 0xA62E0303, + 0x81C, 0xA5300303, + 0x81C, 0xA4320303, + 0x81C, 0xA3340303, + 0x81C, 0xA2360303, + 0x81C, 0xA1380303, + 0x81C, 0xA03A0303, + 0x81C, 0x823C0303, + 0x81C, 0x643E0303, + 0x81C, 0x63400303, + 0x81C, 0x62420303, + 0x81C, 0x61440303, + 0x81C, 0x60460303, + 0x81C, 0x24480303, + 0x81C, 0x234A0303, + 0x81C, 0x224C0303, + 0x81C, 0x054E0303, + 0x81C, 0x04500303, + 0x81C, 0x03520303, + 0x81C, 0x02540303, + 0x81C, 0x01560303, + 0x81C, 0x00580303, + 0x81C, 0x005A0303, + 0x81C, 0x005C0303, + 0x81C, 0x005E0303, + 0x81C, 0x00600303, + 0x81C, 0x00620303, + 0x81C, 0x00640303, + 0x81C, 0x00660303, + 0x81C, 0x00680303, + 0x81C, 0x006A0303, + 0x81C, 0x006C0303, + 0x81C, 0x006E0303, + 0x81C, 0x00700303, + 0x81C, 0x00720303, + 0x81C, 0x00740303, + 0x81C, 0x00760303, + 0x81C, 0x00780303, + 0x81C, 0x007A0303, + 0x81C, 0x007C0303, + 0x81C, 0x007E0303, 0xA0000000, 0x00000000, 0x81C, 0xFC000303, 0x81C, 0xFB020303, @@ -649,7 +897,72 @@ u32 array_mp_8821c_agc_tab[] = { 0x81C, 0x017C0303, 0x81C, 0x017E0303, 0xB0000000, 0x00000000, - 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x80001004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000803, + 0x81C, 0xFB020803, + 0x81C, 0xFA040803, + 0x81C, 0xF9060803, + 0x81C, 0xF8080803, + 0x81C, 0xF70A0803, + 0x81C, 0xF60C0803, + 0x81C, 0xF50E0803, + 0x81C, 0xF4100803, + 0x81C, 0xF3120803, + 0x81C, 0xF2140803, + 0x81C, 0xF1160803, + 0x81C, 0xF0180803, + 0x81C, 0xEF1A0803, + 0x81C, 0xEE1C0803, + 0x81C, 0xED1E0803, + 0x81C, 0xB5200803, + 0x81C, 0xB4220803, + 0x81C, 0xB3240803, + 0x81C, 0xB2260803, + 0x81C, 0xB1280803, + 0x81C, 0xB02A0803, + 0x81C, 0xAF2C0803, + 0x81C, 0xAE2E0803, + 0x81C, 0xAD300803, + 0x81C, 0xAC320803, + 0x81C, 0xAB340803, + 0x81C, 0xAA360803, + 0x81C, 0xA9380803, + 0x81C, 0xA83A0803, + 0x81C, 0xA73C0803, + 0x81C, 0xA63E0803, + 0x81C, 0x88400803, + 0x81C, 0x87420803, + 0x81C, 0x86440803, + 0x81C, 0x85460803, + 0x81C, 0x84480803, + 0x81C, 0x834A0803, + 0x81C, 0x674C0803, + 0x81C, 0x664E0803, + 0x81C, 0x65500803, + 0x81C, 0x64520803, + 0x81C, 0x63540803, + 0x81C, 0x62560803, + 0x81C, 0x61580803, + 0x81C, 0x455A0803, + 0x81C, 0x445C0803, + 0x81C, 0x435E0803, + 0x81C, 0x42600803, + 0x81C, 0x41620803, + 0x81C, 0x25640803, + 0x81C, 0x24660803, + 0x81C, 0x23680803, + 0x81C, 0x226A0803, + 0x81C, 0x216C0803, + 0x81C, 0x016E0803, + 0x81C, 0x01700803, + 0x81C, 0x01720803, + 0x81C, 0x01740803, + 0x81C, 0x01760803, + 0x81C, 0x01780803, + 0x81C, 0x017A0803, + 0x81C, 0x017C0803, + 0x81C, 0x017E0803, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFC000803, 0x81C, 0xFB020803, 0x81C, 0xFA040803, @@ -780,7 +1093,72 @@ u32 array_mp_8821c_agc_tab[] = { 0x81C, 0x017C0803, 0x81C, 0x017E0803, 0xB0000000, 0x00000000, - 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x80001004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000913, + 0x81C, 0xFE020913, + 0x81C, 0xFD040913, + 0x81C, 0xFC060913, + 0x81C, 0xFB080913, + 0x81C, 0xFA0A0913, + 0x81C, 0xF90C0913, + 0x81C, 0xF80E0913, + 0x81C, 0xF7100913, + 0x81C, 0xF6120913, + 0x81C, 0xF5140913, + 0x81C, 0xF4160913, + 0x81C, 0xF3180913, + 0x81C, 0xF21A0913, + 0x81C, 0xF11C0913, + 0x81C, 0x941E0913, + 0x81C, 0x93200913, + 0x81C, 0x92220913, + 0x81C, 0x91240913, + 0x81C, 0x90260913, + 0x81C, 0x8F280913, + 0x81C, 0x8E2A0913, + 0x81C, 0x8D2C0913, + 0x81C, 0x8C2E0913, + 0x81C, 0x8B300913, + 0x81C, 0x8A320913, + 0x81C, 0x89340913, + 0x81C, 0x88360913, + 0x81C, 0x87380913, + 0x81C, 0x863A0913, + 0x81C, 0x853C0913, + 0x81C, 0x843E0913, + 0x81C, 0x83400913, + 0x81C, 0x82420913, + 0x81C, 0x81440913, + 0x81C, 0x07460913, + 0x81C, 0x06480913, + 0x81C, 0x054A0913, + 0x81C, 0x044C0913, + 0x81C, 0x034E0913, + 0x81C, 0x02500913, + 0x81C, 0x01520913, + 0x81C, 0x88540903, + 0x81C, 0x87560903, + 0x81C, 0x86580903, + 0x81C, 0x855A0903, + 0x81C, 0x845C0903, + 0x81C, 0x835E0903, + 0x81C, 0x82600903, + 0x81C, 0x81620903, + 0x81C, 0x07640903, + 0x81C, 0x06660903, + 0x81C, 0x05680903, + 0x81C, 0x046A0903, + 0x81C, 0x036C0903, + 0x81C, 0x026E0903, + 0x81C, 0x01700903, + 0x81C, 0x01720903, + 0x81C, 0x01740903, + 0x81C, 0x01760903, + 0x81C, 0x01780903, + 0x81C, 0x017A0903, + 0x81C, 0x017C0903, + 0x81C, 0x017E0903, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000913, 0x81C, 0xFE020913, 0x81C, 0xFD040913, @@ -911,9 +1289,12 @@ u32 array_mp_8821c_agc_tab[] = { 0x81C, 0x017C0903, 0x81C, 0x017E0903, 0xB0000000, 0x00000000, - 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x80001004, 0x00000000, 0x40000000, 0x00000000, 0xC50, 0x00000022, 0xC50, 0x00000020, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000022, 0xA0000000, 0x00000000, 0xC50, 0x00000022, 0xC50, 0x00000020, @@ -922,19 +1303,17 @@ u32 array_mp_8821c_agc_tab[] = { }; void -odm_read_and_config_mp_8821c_agc_tab( - struct PHY_DM_STRUCT *p_dm_odm -) +odm_read_and_config_mp_8821c_agc_tab(struct dm_struct *dm) { u32 i = 0; u8 c_cond; boolean is_matched = true, is_skipped = false; - u32 array_len = sizeof(array_mp_8821c_agc_tab)/sizeof(u32); + u32 array_len = sizeof(array_mp_8821c_agc_tab) / sizeof(u32); u32 *array = array_mp_8821c_agc_tab; u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_agc_tab\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); while ((i + 1) < array_len) { v1 = array[i]; @@ -942,22 +1321,22 @@ odm_read_and_config_mp_8821c_agc_tab( if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ if (v1 & BIT(31)) {/* positive condition*/ - c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); if (c_cond == COND_ENDIF) {/*end*/ is_matched = true; is_skipped = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); } else if (c_cond == COND_ELSE) { /*else*/ - is_matched = is_skipped?false:true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + is_matched = is_skipped ? false : true; + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); } } else if (v1 & BIT(30)) { /*negative condition*/ if (is_skipped == false) { - if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { is_matched = true; is_skipped = true; } else { @@ -969,7 +1348,7 @@ odm_read_and_config_mp_8821c_agc_tab( } } else { if (is_matched) - odm_config_bb_agc_8821c(p_dm_odm, v1, MASKDWORD, v2); + odm_config_bb_agc_8821c(dm, v1, MASKDWORD, v2); } i = i + 2; } @@ -978,7 +1357,7 @@ odm_read_and_config_mp_8821c_agc_tab( u32 odm_get_version_mp_8821c_agc_tab(void) { - return 36; + return 49; } /****************************************************************************** @@ -986,7 +1365,136 @@ odm_get_version_mp_8821c_agc_tab(void) ******************************************************************************/ u32 array_mp_8821c_agc_tab_diff_wlg[] = { - 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x80001004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000003, + 0x81C, 0xFA020003, + 0x81C, 0xF9040003, + 0x81C, 0xF8060003, + 0x81C, 0xF7080003, + 0x81C, 0xF60A0003, + 0x81C, 0xF50C0003, + 0x81C, 0xF40E0003, + 0x81C, 0xF3100003, + 0x81C, 0xF2120003, + 0x81C, 0xF1140003, + 0x81C, 0xF0160003, + 0x81C, 0xEF180003, + 0x81C, 0xEE1A0003, + 0x81C, 0xED1C0003, + 0x81C, 0xEC1E0003, + 0x81C, 0xEB200003, + 0x81C, 0xEA220003, + 0x81C, 0xE9240003, + 0x81C, 0xE8260003, + 0x81C, 0xE7280003, + 0x81C, 0xE62A0003, + 0x81C, 0xE52C0003, + 0x81C, 0xE42E0003, + 0x81C, 0xE3300003, + 0x81C, 0xE2320003, + 0x81C, 0xE1340003, + 0x81C, 0xC4360003, + 0x81C, 0xC3380003, + 0x81C, 0xC23A0003, + 0x81C, 0xC13C0003, + 0x81C, 0x883E0003, + 0x81C, 0x87400003, + 0x81C, 0x86420003, + 0x81C, 0x85440003, + 0x81C, 0x84460003, + 0x81C, 0x83480003, + 0x81C, 0x824A0003, + 0x81C, 0x814C0003, + 0x81C, 0x804E0003, + 0x81C, 0x64500003, + 0x81C, 0x63520003, + 0x81C, 0x62540003, + 0x81C, 0x61560003, + 0x81C, 0x60580003, + 0x81C, 0x475A0003, + 0x81C, 0x465C0003, + 0x81C, 0x455E0003, + 0x81C, 0x44600003, + 0x81C, 0x43620003, + 0x81C, 0x42640003, + 0x81C, 0x41660003, + 0x81C, 0x40680003, + 0x81C, 0x236A0003, + 0x81C, 0x226C0003, + 0x81C, 0x056E0003, + 0x81C, 0x04700003, + 0x81C, 0x03720003, + 0x81C, 0x02740003, + 0x81C, 0x01760003, + 0x81C, 0x01780003, + 0x81C, 0x017A0003, + 0x81C, 0x017C0003, + 0x81C, 0x017E0003, + 0x81C, 0xFF000803, + 0x81C, 0xFE020803, + 0x81C, 0xFD040803, + 0x81C, 0xFC060803, + 0x81C, 0xFB080803, + 0x81C, 0xFA0A0803, + 0x81C, 0xF90C0803, + 0x81C, 0xF80E0803, + 0x81C, 0xF7100803, + 0x81C, 0xF6120803, + 0x81C, 0xF5140803, + 0x81C, 0xF4160803, + 0x81C, 0xF3180803, + 0x81C, 0xF21A0803, + 0x81C, 0xF11C0803, + 0x81C, 0xF01E0803, + 0x81C, 0xB7200803, + 0x81C, 0xB6220803, + 0x81C, 0xB5240803, + 0x81C, 0xB4260803, + 0x81C, 0xB3280803, + 0x81C, 0xB22A0803, + 0x81C, 0xB12C0803, + 0x81C, 0xAF2E0803, + 0x81C, 0xAE300803, + 0x81C, 0xAD320803, + 0x81C, 0xAC340803, + 0x81C, 0xAB360803, + 0x81C, 0xAA380803, + 0x81C, 0xA93A0803, + 0x81C, 0xA83C0803, + 0x81C, 0xA73E0803, + 0x81C, 0x88400803, + 0x81C, 0x87420803, + 0x81C, 0x86440803, + 0x81C, 0x85460803, + 0x81C, 0x84480803, + 0x81C, 0x834A0803, + 0x81C, 0x674C0803, + 0x81C, 0x664E0803, + 0x81C, 0x65500803, + 0x81C, 0x64520803, + 0x81C, 0x63540803, + 0x81C, 0x62560803, + 0x81C, 0x61580803, + 0x81C, 0x455A0803, + 0x81C, 0x445C0803, + 0x81C, 0x435E0803, + 0x81C, 0x42600803, + 0x81C, 0x41620803, + 0x81C, 0x25640803, + 0x81C, 0x24660803, + 0x81C, 0x23680803, + 0x81C, 0x226A0803, + 0x81C, 0x216C0803, + 0x81C, 0x016E0803, + 0x81C, 0x01700803, + 0x81C, 0x01720803, + 0x81C, 0x01740803, + 0x81C, 0x01760803, + 0x81C, 0x01780803, + 0x81C, 0x017A0803, + 0x81C, 0x017C0803, + 0x81C, 0x017E0803, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFB000003, 0x81C, 0xFA020003, 0x81C, 0xF9040003, @@ -1248,7 +1756,136 @@ u32 array_mp_8821c_agc_tab_diff_wlg[] = { }; u32 array_mp_8821c_agc_tab_diff_btg[] = { - 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x80001004, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000013, + 0x81C, 0xFE020013, + 0x81C, 0xFD040013, + 0x81C, 0xFC060013, + 0x81C, 0xFB080013, + 0x81C, 0xFA0A0013, + 0x81C, 0xF90C0013, + 0x81C, 0xF80E0013, + 0x81C, 0xF7100013, + 0x81C, 0xF6120013, + 0x81C, 0xF5140013, + 0x81C, 0xF4160013, + 0x81C, 0xF3180013, + 0x81C, 0xF21A0013, + 0x81C, 0xF11C0013, + 0x81C, 0xF01E0013, + 0x81C, 0xEF200013, + 0x81C, 0xEE220013, + 0x81C, 0xED240013, + 0x81C, 0xEC260013, + 0x81C, 0xEB280013, + 0x81C, 0xEA2A0013, + 0x81C, 0xE92C0013, + 0x81C, 0xE82E0013, + 0x81C, 0xE7300013, + 0x81C, 0x8B320013, + 0x81C, 0x8A340013, + 0x81C, 0x89360013, + 0x81C, 0x88380013, + 0x81C, 0x873A0013, + 0x81C, 0x863C0013, + 0x81C, 0x853E0013, + 0x81C, 0x84400013, + 0x81C, 0x83420013, + 0x81C, 0x82440013, + 0x81C, 0x81460013, + 0x81C, 0x08480013, + 0x81C, 0x074A0013, + 0x81C, 0x064C0013, + 0x81C, 0x054E0013, + 0x81C, 0x04500013, + 0x81C, 0x03520013, + 0x81C, 0x88540003, + 0x81C, 0x87560003, + 0x81C, 0x86580003, + 0x81C, 0x855A0003, + 0x81C, 0x845C0003, + 0x81C, 0x835E0003, + 0x81C, 0x82600003, + 0x81C, 0x81620003, + 0x81C, 0x07640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x01720003, + 0x81C, 0x01740003, + 0x81C, 0x01760003, + 0x81C, 0x01780003, + 0x81C, 0x017A0003, + 0x81C, 0x017C0003, + 0x81C, 0x017E0003, + 0x81C, 0xFF000813, + 0x81C, 0xFE020813, + 0x81C, 0xFD040813, + 0x81C, 0xFC060813, + 0x81C, 0xFB080813, + 0x81C, 0xFA0A0813, + 0x81C, 0xF90C0813, + 0x81C, 0xF80E0813, + 0x81C, 0xF7100813, + 0x81C, 0xF6120813, + 0x81C, 0xF5140813, + 0x81C, 0xF4160813, + 0x81C, 0xF3180813, + 0x81C, 0xF21A0813, + 0x81C, 0xF11C0813, + 0x81C, 0x941E0813, + 0x81C, 0x93200813, + 0x81C, 0x92220813, + 0x81C, 0x91240813, + 0x81C, 0x90260813, + 0x81C, 0x8F280813, + 0x81C, 0x8E2A0813, + 0x81C, 0x8D2C0813, + 0x81C, 0x8C2E0813, + 0x81C, 0x8B300813, + 0x81C, 0x8A320813, + 0x81C, 0x89340813, + 0x81C, 0x88360813, + 0x81C, 0x87380813, + 0x81C, 0x863A0813, + 0x81C, 0x853C0813, + 0x81C, 0x843E0813, + 0x81C, 0x83400813, + 0x81C, 0x82420813, + 0x81C, 0x81440813, + 0x81C, 0x07460813, + 0x81C, 0x06480813, + 0x81C, 0x054A0813, + 0x81C, 0x044C0813, + 0x81C, 0x034E0813, + 0x81C, 0x02500813, + 0x81C, 0x01520813, + 0x81C, 0x88540803, + 0x81C, 0x87560803, + 0x81C, 0x86580803, + 0x81C, 0x855A0803, + 0x81C, 0x845C0803, + 0x81C, 0x835E0803, + 0x81C, 0x82600803, + 0x81C, 0x81620803, + 0x81C, 0x07640803, + 0x81C, 0x06660803, + 0x81C, 0x05680803, + 0x81C, 0x046A0803, + 0x81C, 0x036C0803, + 0x81C, 0x026E0803, + 0x81C, 0x01700803, + 0x81C, 0x01720803, + 0x81C, 0x01740803, + 0x81C, 0x01760803, + 0x81C, 0x01780803, + 0x81C, 0x017A0803, + 0x81C, 0x017C0803, + 0x81C, 0x017E0803, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, 0x81C, 0xFF000013, 0x81C, 0xFE020013, 0x81C, 0xFD040013, @@ -1510,11 +2147,8 @@ u32 array_mp_8821c_agc_tab_diff_btg[] = { }; void -odm_read_and_config_mp_8821c_agc_tab_diff( - struct PHY_DM_STRUCT *p_dm_odm, - u32 array[], - u32 array_len -) +odm_read_and_config_mp_8821c_agc_tab_diff(struct dm_struct *dm, u32 array[], + u32 array_len) { u32 i = 0; u8 c_cond; @@ -1522,7 +2156,7 @@ odm_read_and_config_mp_8821c_agc_tab_diff( u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_agc_tab_diff\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); while ((i + 1) < array_len) { v1 = array[i]; @@ -1530,22 +2164,22 @@ odm_read_and_config_mp_8821c_agc_tab_diff( if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ if (v1 & BIT(31)) {/* positive condition*/ - c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); if (c_cond == COND_ENDIF) {/*end*/ is_matched = true; is_skipped = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); } else if (c_cond == COND_ELSE) { /*else*/ - is_matched = is_skipped?false:true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + is_matched = is_skipped ? false : true; + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); } } else if (v1 & BIT(30)) { /*negative condition*/ if (is_skipped == false) { - if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { is_matched = true; is_skipped = true; } else { @@ -1557,7 +2191,7 @@ odm_read_and_config_mp_8821c_agc_tab_diff( } } else { if (is_matched) - odm_config_bb_agc_8821c(p_dm_odm, v1, MASKDWORD, v2); + odm_config_bb_agc_8821c(dm, v1, MASKDWORD, v2); } i = i + 2; } @@ -1566,7 +2200,7 @@ odm_read_and_config_mp_8821c_agc_tab_diff( u32 odm_get_version_mp_8821c_agc_tab_diff(void) { - return 36; + return 49; } /****************************************************************************** @@ -1586,7 +2220,7 @@ u32 array_mp_8821c_phy_reg[] = { 0x824, 0x00030FE0, 0x828, 0x0000CCCC, 0x82C, 0x75CB7010, - 0x830, 0x79A0EA2A, + 0x830, 0x79A0EAAA, 0x834, 0x072E698A, 0x838, 0x87766461, 0x83C, 0x9194B2B6, @@ -1621,7 +2255,7 @@ u32 array_mp_8821c_phy_reg[] = { 0x8B0, 0x00000600, 0x8B4, 0x000FC080, 0x8B8, 0xEC0057FF, - 0x8BC, 0xACB520A3, + 0x8BC, 0x2CB520A3, 0x8C0, 0xFFE04020, 0x8C4, 0x47C00000, 0x8C8, 0x00025165, @@ -1658,13 +2292,7 @@ u32 array_mp_8821c_phy_reg[] = { 0x944, 0x00000000, 0x948, 0xAC000000, 0x94C, 0x10000083, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x950, 0xB2010080, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x950, 0xB2010080, - 0xA0000000, 0x00000000, - 0x950, 0xF2010080, - 0xB0000000, 0x00000000, 0x954, 0x86510080, 0x958, 0x00000181, 0x95C, 0x04248000, @@ -1711,7 +2339,7 @@ u32 array_mp_8821c_phy_reg[] = { 0xA00, 0x00D040C8, 0xA04, 0x80FF800C, 0xA08, 0x9C838300, - 0xA0C, 0x2E20200F, + 0xA0C, 0x297E000F, 0xA10, 0x9500BB78, 0xA14, 0x1114D028, 0xA18, 0x00881117, @@ -1725,13 +2353,13 @@ u32 array_mp_8821c_phy_reg[] = { 0xA78, 0x00008900, 0xA7C, 0x225B0606, 0xA80, 0x21807532, - 0xA84, 0x80200000, + 0xA84, 0x80120000, 0xA88, 0x048C0000, 0xA8C, 0x12345678, 0xA90, 0xABCDEF00, 0xA94, 0x001B1B89, 0xA98, 0x00000000, - 0xA9C, 0x00060000, + 0xA9C, 0x3F000000, 0xAA0, 0x00000000, 0xAA4, 0x00080000, 0xAA8, 0xEACF0004, @@ -1774,13 +2402,7 @@ u32 array_mp_8821c_phy_reg[] = { 0xB88, 0x00000000, 0xB8C, 0x00000000, 0xC00, 0x00000007, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0xC04, 0x03010020, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, 0xC04, 0x03010020, - 0xA0000000, 0x00000000, - 0xC04, 0x03000020, - 0xB0000000, 0x00000000, 0xC08, 0x60403231, 0xC0C, 0x00012345, 0xC10, 0x00000100, @@ -1803,7 +2425,7 @@ u32 array_mp_8821c_phy_reg[] = { 0xC54, 0x00000000, 0xC58, 0xD8020402, 0xC5C, 0xDE000120, - 0xC68, 0x00000079, + 0xC68, 0x0000003F, 0xC6C, 0x0000122A, 0xC70, 0x00000000, 0xC74, 0x00000000, @@ -1820,8 +2442,13 @@ u32 array_mp_8821c_phy_reg[] = { 0xCA4, 0x08040201, 0xCA8, 0x80402010, 0xCAC, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0xCB0, 0x77777717, + 0xCB4, 0x00000073, + 0xA0000000, 0x00000000, 0xCB0, 0x77775747, 0xCB4, 0x10000077, + 0xB0000000, 0x00000000, 0xCB8, 0x00000000, 0xCBC, 0x00000000, 0xCC0, 0x00000000, @@ -1937,7 +2564,7 @@ u32 array_mp_8821c_phy_reg[] = { 0x19A4, 0x00000000, 0x19A8, 0x010A0000, 0x19AC, 0x0E47E47F, - 0x19B0, 0x00000000, + 0x19B0, 0x00008000, 0x19B4, 0x0E47E47F, 0x19B8, 0x00000000, 0x19BC, 0x00000000, @@ -1972,7 +2599,7 @@ u32 array_mp_8821c_phy_reg[] = { 0x1C30, 0x00000100, 0x1C34, 0x01000000, 0x1C38, 0x00000000, - 0x1C3C, 0x00000000, + 0x1C3C, 0x00008000, 0x1C40, 0x000C0100, 0x1C44, 0x000000F3, 0x1C48, 0x1A8249A8, @@ -2121,8 +2748,6 @@ u32 array_mp_8821c_phy_reg[] = { 0x1B74, 0x00C200C5, 0x1B78, 0x00BB00BE, 0x1B7C, 0x00B500B8, - 0x1BB8, 0x000FFFFF, - 0x1BBC, 0x00000000, 0x1BDC, 0x40CAFFE1, 0x1BDC, 0x4080A1E3, 0x1BDC, 0x405165E5, @@ -2139,6 +2764,22 @@ u32 array_mp_8821c_phy_reg[] = { 0x1BDC, 0x400101FB, 0x1BDC, 0x400101FD, 0x1BDC, 0x400101FF, + 0x1BDC, 0x40CAFF81, + 0x1BDC, 0x4080A183, + 0x1BDC, 0x40516585, + 0x1BDC, 0x40334087, + 0x1BDC, 0x40202889, + 0x1BDC, 0x4014198B, + 0x1BDC, 0x400D108D, + 0x1BDC, 0x40080A8F, + 0x1BDC, 0x40050691, + 0x1BDC, 0x40030493, + 0x1BDC, 0x40020395, + 0x1BDC, 0x40010297, + 0x1BDC, 0x40010199, + 0x1BDC, 0x4001019B, + 0x1BDC, 0x4001019D, + 0x1BDC, 0x4001019F, 0x1BDC, 0x00000000, 0x1BDC, 0xD0000001, 0x1BDC, 0xD0000003, @@ -2269,18 +2910,7 @@ u32 array_mp_8821c_phy_reg[] = { 0x1BDC, 0x900000FD, 0x1BDC, 0x900000FF, 0x1BDC, 0x00000000, - 0x1B00, 0xF800000A, - 0x1B1C, 0xA2193C32, - 0x1B20, 0x01840008, - 0x1B24, 0x01860008, - 0x1B28, 0x80060300, - 0x1B2C, 0x00000003, - 0x1B30, 0x20000000, - 0x1B34, 0x00000800, - 0x1B3C, 0x20000000, - 0x1BC0, 0x01000000, - 0x1BCC, 0x00000000, - 0x1B00, 0xF8000008, + 0x1B00, 0xF8000000, 0x1B80, 0x00000007, 0x1B80, 0x090A0005, 0x1B80, 0x090A0007, @@ -2312,959 +2942,973 @@ u32 array_mp_8821c_phy_reg[] = { 0x1B80, 0x000400D7, 0x1B80, 0x05C000E5, 0x1B80, 0x05C000E7, - 0x1B80, 0x48C000F5, - 0x1B80, 0x48C000F7, - 0x1B80, 0x00060105, - 0x1B80, 0x00060107, - 0x1B80, 0x510A0115, - 0x1B80, 0x510A0117, - 0x1B80, 0x00070125, - 0x1B80, 0x00070127, - 0x1B80, 0x64020135, - 0x1B80, 0x64020137, - 0x1B80, 0x56000145, - 0x1B80, 0x56000147, - 0x1B80, 0x00020155, - 0x1B80, 0x00020157, - 0x1B80, 0x00040165, - 0x1B80, 0x00040167, - 0x1B80, 0x4A000175, - 0x1B80, 0x4A000177, - 0x1B80, 0x4B040185, - 0x1B80, 0x4B040187, - 0x1B80, 0x85030195, - 0x1B80, 0x85030197, - 0x1B80, 0x400901A5, - 0x1B80, 0x400901A7, - 0x1B80, 0xE02D01B5, - 0x1B80, 0xE02D01B7, - 0x1B80, 0x4B0501C5, - 0x1B80, 0x4B0501C7, - 0x1B80, 0x860301D5, - 0x1B80, 0x860301D7, - 0x1B80, 0x400B01E5, - 0x1B80, 0x400B01E7, - 0x1B80, 0xE02D01F5, - 0x1B80, 0xE02D01F7, - 0x1B80, 0x4B000205, - 0x1B80, 0x4B000207, - 0x1B80, 0x00070215, - 0x1B80, 0x00070217, - 0x1B80, 0x4C000225, - 0x1B80, 0x4C000227, - 0x1B80, 0x09090235, - 0x1B80, 0x09090237, - 0x1B80, 0x0F020245, - 0x1B80, 0x0F020247, - 0x1B80, 0x00220255, - 0x1B80, 0x00220257, - 0x1B80, 0x00040265, - 0x1B80, 0x00040267, - 0x1B80, 0x05C00275, - 0x1B80, 0x05C00277, - 0x1B80, 0x00070285, - 0x1B80, 0x00070287, - 0x1B80, 0x4B000295, - 0x1B80, 0x4B000297, - 0x1B80, 0x000202A5, - 0x1B80, 0x000202A7, - 0x1B80, 0x000402B5, - 0x1B80, 0x000402B7, - 0x1B80, 0x300002C5, - 0x1B80, 0x300002C7, - 0x1B80, 0xE1D402D5, - 0x1B80, 0xE1D402D7, - 0x1B80, 0xF01002E5, - 0x1B80, 0xF01002E7, - 0x1B80, 0xF11002F5, - 0x1B80, 0xF11002F7, - 0x1B80, 0xF2100305, - 0x1B80, 0xF2100307, - 0x1B80, 0xF3100315, - 0x1B80, 0xF3100317, - 0x1B80, 0xF4100325, - 0x1B80, 0xF4100327, - 0x1B80, 0xF5100335, - 0x1B80, 0xF5100337, - 0x1B80, 0xF6100345, - 0x1B80, 0xF6100347, - 0x1B80, 0xF7100355, - 0x1B80, 0xF7100357, - 0x1B80, 0xF8100365, - 0x1B80, 0xF8100367, - 0x1B80, 0xF9100375, - 0x1B80, 0xF9100377, - 0x1B80, 0xFA100385, - 0x1B80, 0xFA100387, - 0x1B80, 0xFB100395, - 0x1B80, 0xFB100397, - 0x1B80, 0xFD1003A5, - 0x1B80, 0xFD1003A7, - 0x1B80, 0xFE1003B5, - 0x1B80, 0xFE1003B7, - 0x1B80, 0xFF1003C5, - 0x1B80, 0xFF1003C7, - 0x1B80, 0x000103D5, - 0x1B80, 0x000103D7, - 0x1B80, 0x304D03E5, - 0x1B80, 0x304D03E7, - 0x1B80, 0x306503F5, - 0x1B80, 0x306503F7, - 0x1B80, 0x30B00405, - 0x1B80, 0x30B00407, - 0x1B80, 0x30B30415, - 0x1B80, 0x30B30417, - 0x1B80, 0x30670425, - 0x1B80, 0x30670427, - 0x1B80, 0x30720435, - 0x1B80, 0x30720437, - 0x1B80, 0x307D0445, - 0x1B80, 0x307D0447, - 0x1B80, 0x30BD0455, - 0x1B80, 0x30BD0457, - 0x1B80, 0x30B70465, - 0x1B80, 0x30B70467, - 0x1B80, 0x30CB0475, - 0x1B80, 0x30CB0477, - 0x1B80, 0x30D60485, - 0x1B80, 0x30D60487, - 0x1B80, 0x30E10495, - 0x1B80, 0x30E10497, - 0x1B80, 0x311004A5, - 0x1B80, 0x311004A7, - 0x1B80, 0x312104B5, - 0x1B80, 0x312104B7, - 0x1B80, 0x313604C5, - 0x1B80, 0x313604C7, - 0x1B80, 0xE16104D5, - 0x1B80, 0xE16104D7, - 0x1B80, 0x4D0404E5, - 0x1B80, 0x4D0404E7, - 0x1B80, 0x208004F5, - 0x1B80, 0x208004F7, + 0x1B80, 0x000700F5, + 0x1B80, 0x000700F7, + 0x1B80, 0x64020105, + 0x1B80, 0x64020107, + 0x1B80, 0x00020115, + 0x1B80, 0x00020117, + 0x1B80, 0x00040125, + 0x1B80, 0x00040127, + 0x1B80, 0x4A000135, + 0x1B80, 0x4A000137, + 0x1B80, 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0xE17716B5, + 0x1B80, 0xE17716B7, + 0x1B80, 0x548016C5, + 0x1B80, 0x548016C7, + 0x1B80, 0x540016D5, + 0x1B80, 0x540016D7, + 0x1B80, 0xE17716E5, + 0x1B80, 0xE17716E7, + 0x1B80, 0x548116F5, + 0x1B80, 0x548116F7, + 0x1B80, 0x54001705, + 0x1B80, 0x54001707, + 0x1B80, 0xE1771715, + 0x1B80, 0xE1771717, + 0x1B80, 0x54821725, + 0x1B80, 0x54821727, + 0x1B80, 0x54001735, + 0x1B80, 0x54001737, + 0x1B80, 0xE1821745, + 0x1B80, 0xE1821747, + 0x1B80, 0xBF1D1755, + 0x1B80, 0xBF1D1757, + 0x1B80, 0x301D1765, + 0x1B80, 0x301D1767, + 0x1B80, 0xE1551775, + 0x1B80, 0xE1551777, + 0x1B80, 0xE15A1785, + 0x1B80, 0xE15A1787, + 0x1B80, 0xE15E1795, + 0x1B80, 0xE15E1797, + 0x1B80, 0xE16517A5, + 0x1B80, 0xE16517A7, + 0x1B80, 0xE1CB17B5, + 0x1B80, 0xE1CB17B7, + 0x1B80, 0x551317C5, + 0x1B80, 0x551317C7, + 0x1B80, 0xE16117D5, + 0x1B80, 0xE16117D7, + 0x1B80, 0x551517E5, + 0x1B80, 0x551517E7, + 0x1B80, 0xE16517F5, + 0x1B80, 0xE16517F7, + 0x1B80, 0xE1CB1805, + 0x1B80, 0xE1CB1807, + 0x1B80, 0x00011815, + 0x1B80, 0x00011817, + 0x1B80, 0x54BF1825, + 0x1B80, 0x54BF1827, + 0x1B80, 0x54C01835, + 0x1B80, 0x54C01837, + 0x1B80, 0x54A31845, + 0x1B80, 0x54A31847, + 0x1B80, 0x54C11855, + 0x1B80, 0x54C11857, + 0x1B80, 0x54A41865, + 0x1B80, 0x54A41867, + 0x1B80, 0x4C181875, + 0x1B80, 0x4C181877, + 0x1B80, 0xBF071885, + 0x1B80, 0xBF071887, + 0x1B80, 0x54C21895, + 0x1B80, 0x54C21897, + 0x1B80, 0x54A418A5, + 0x1B80, 0x54A418A7, + 0x1B80, 0xBF0418B5, + 0x1B80, 0xBF0418B7, + 0x1B80, 0x54C118C5, + 0x1B80, 0x54C118C7, + 0x1B80, 0x54A318D5, + 0x1B80, 0x54A318D7, + 0x1B80, 0xBF0118E5, + 0x1B80, 0xBF0118E7, + 0x1B80, 0xE1D918F5, + 0x1B80, 0xE1D918F7, + 0x1B80, 0x54DF1905, + 0x1B80, 0x54DF1907, + 0x1B80, 0x00011915, + 0x1B80, 0x00011917, + 0x1B80, 0x54BF1925, + 0x1B80, 0x54BF1927, + 0x1B80, 0x54E51935, + 0x1B80, 0x54E51937, + 0x1B80, 0x050A1945, + 0x1B80, 0x050A1947, + 0x1B80, 0x54DF1955, + 0x1B80, 0x54DF1957, + 0x1B80, 0x00011965, + 0x1B80, 0x00011967, + 0x1B80, 0x7F201975, + 0x1B80, 0x7F201977, + 0x1B80, 0x7E001985, + 0x1B80, 0x7E001987, + 0x1B80, 0x7D001995, + 0x1B80, 0x7D001997, + 0x1B80, 0x550119A5, + 0x1B80, 0x550119A7, + 0x1B80, 0x5C3119B5, + 0x1B80, 0x5C3119B7, + 0x1B80, 0xE16119C5, + 0x1B80, 0xE16119C7, + 0x1B80, 0xE16519D5, + 0x1B80, 0xE16519D7, + 0x1B80, 0x548019E5, + 0x1B80, 0x548019E7, 0x1B80, 0x540019F5, 0x1B80, 0x540019F7, - 0x1B80, 0xE17A1A05, - 0x1B80, 0xE17A1A07, - 0x1B80, 0xBFE91A15, - 0x1B80, 0xBFE91A17, - 0x1B80, 0x30211A25, - 0x1B80, 0x30211A27, - 0x1B80, 0x00231A35, - 0x1B80, 0x00231A37, - 0x1B80, 0x7B201A45, - 0x1B80, 0x7B201A47, - 0x1B80, 0x7A001A55, - 0x1B80, 0x7A001A57, - 0x1B80, 0x79001A65, - 0x1B80, 0x79001A67, - 0x1B80, 0xE1C71A75, - 0x1B80, 0xE1C71A77, - 0x1B80, 0x00021A85, - 0x1B80, 0x00021A87, - 0x1B80, 0x00011A95, - 0x1B80, 0x00011A97, - 0x1B80, 0x00221AA5, - 0x1B80, 0x00221AA7, - 0x1B80, 0x7B201AB5, - 0x1B80, 0x7B201AB7, - 0x1B80, 0x7A001AC5, - 0x1B80, 0x7A001AC7, - 0x1B80, 0x79001AD5, - 0x1B80, 0x79001AD7, - 0x1B80, 0xE1C71AE5, - 0x1B80, 0xE1C71AE7, - 0x1B80, 0x00021AF5, - 0x1B80, 0x00021AF7, - 0x1B80, 0x00011B05, - 0x1B80, 0x00011B07, - 0x1B80, 0x74021B15, - 0x1B80, 0x74021B17, - 0x1B80, 0x003F1B25, - 0x1B80, 0x003F1B27, - 0x1B80, 0x74001B35, - 0x1B80, 0x74001B37, - 0x1B80, 0x00021B45, - 0x1B80, 0x00021B47, - 0x1B80, 0x00011B55, - 0x1B80, 0x00011B57, - 0x1B80, 0x4D041B65, - 0x1B80, 0x4D041B67, - 0x1B80, 0x2EF81B75, - 0x1B80, 0x2EF81B77, - 0x1B80, 0x00001B85, - 0x1B80, 0x00001B87, - 0x1B80, 0x23301B95, - 0x1B80, 0x23301B97, - 0x1B80, 0x00241BA5, - 0x1B80, 0x00241BA7, - 0x1B80, 0x23E01BB5, - 0x1B80, 0x23E01BB7, - 0x1B80, 0x003F1BC5, - 0x1B80, 0x003F1BC7, - 0x1B80, 0x23FC1BD5, - 0x1B80, 0x23FC1BD7, - 0x1B80, 0xBFCE1BE5, - 0x1B80, 0xBFCE1BE7, - 0x1B80, 0x2EF01BF5, - 0x1B80, 0x2EF01BF7, + 0x1B80, 0xE1611A05, + 0x1B80, 0xE1611A07, + 0x1B80, 0xE1651A15, + 0x1B80, 0xE1651A17, + 0x1B80, 0x54811A25, + 0x1B80, 0x54811A27, + 0x1B80, 0x54001A35, + 0x1B80, 0x54001A37, + 0x1B80, 0xE1611A45, + 0x1B80, 0xE1611A47, + 0x1B80, 0xE1651A55, + 0x1B80, 0xE1651A57, + 0x1B80, 0x54821A65, + 0x1B80, 0x54821A67, + 0x1B80, 0x54001A75, + 0x1B80, 0x54001A77, + 0x1B80, 0xE1821A85, + 0x1B80, 0xE1821A87, + 0x1B80, 0xBFE91A95, + 0x1B80, 0xBFE91A97, + 0x1B80, 0x301D1AA5, + 0x1B80, 0x301D1AA7, + 0x1B80, 0x00231AB5, + 0x1B80, 0x00231AB7, + 0x1B80, 0x7B201AC5, + 0x1B80, 0x7B201AC7, + 0x1B80, 0x7A001AD5, + 0x1B80, 0x7A001AD7, + 0x1B80, 0x79001AE5, + 0x1B80, 0x79001AE7, + 0x1B80, 0xE1CF1AF5, + 0x1B80, 0xE1CF1AF7, + 0x1B80, 0x00021B05, + 0x1B80, 0x00021B07, + 0x1B80, 0x00011B15, + 0x1B80, 0x00011B17, + 0x1B80, 0x00221B25, + 0x1B80, 0x00221B27, + 0x1B80, 0x7B201B35, + 0x1B80, 0x7B201B37, + 0x1B80, 0x7A001B45, + 0x1B80, 0x7A001B47, + 0x1B80, 0x79001B55, + 0x1B80, 0x79001B57, + 0x1B80, 0xE1CF1B65, + 0x1B80, 0xE1CF1B67, + 0x1B80, 0x00021B75, + 0x1B80, 0x00021B77, + 0x1B80, 0x00011B85, + 0x1B80, 0x00011B87, + 0x1B80, 0x74021B95, + 0x1B80, 0x74021B97, + 0x1B80, 0x003F1BA5, + 0x1B80, 0x003F1BA7, + 0x1B80, 0x74001BB5, + 0x1B80, 0x74001BB7, + 0x1B80, 0x00021BC5, + 0x1B80, 0x00021BC7, + 0x1B80, 0x00011BD5, + 0x1B80, 0x00011BD7, + 0x1B80, 0x4D041BE5, + 0x1B80, 0x4D041BE7, + 0x1B80, 0x2EF81BF5, + 0x1B80, 0x2EF81BF7, 0x1B80, 0x00001C05, 0x1B80, 0x00001C07, - 0x1B80, 0x4D001C15, - 0x1B80, 0x4D001C17, - 0x1B80, 0x00011C25, - 0x1B80, 0x00011C27, - 0x1B80, 0x549F1C35, - 0x1B80, 0x549F1C37, - 0x1B80, 0x54FF1C45, - 0x1B80, 0x54FF1C47, - 0x1B80, 0x54001C55, - 0x1B80, 0x54001C57, - 0x1B80, 0x00011C65, - 0x1B80, 0x00011C67, - 0x1B80, 0x5C311C75, - 0x1B80, 0x5C311C77, - 0x1B80, 0x07141C85, - 0x1B80, 0x07141C87, - 0x1B80, 0x54001C95, - 0x1B80, 0x54001C97, - 0x1B80, 0x5C321CA5, - 0x1B80, 0x5C321CA7, - 0x1B80, 0x00011CB5, - 0x1B80, 0x00011CB7, - 0x1B80, 0x5C321CC5, - 0x1B80, 0x5C321CC7, - 0x1B80, 0x07141CD5, - 0x1B80, 0x07141CD7, - 0x1B80, 0x54001CE5, - 0x1B80, 0x54001CE7, + 0x1B80, 0x23301C15, + 0x1B80, 0x23301C17, + 0x1B80, 0x00241C25, + 0x1B80, 0x00241C27, + 0x1B80, 0x23E01C35, + 0x1B80, 0x23E01C37, + 0x1B80, 0x003F1C45, + 0x1B80, 0x003F1C47, + 0x1B80, 0x23FC1C55, + 0x1B80, 0x23FC1C57, + 0x1B80, 0xBFCE1C65, + 0x1B80, 0xBFCE1C67, + 0x1B80, 0x2EF01C75, + 0x1B80, 0x2EF01C77, + 0x1B80, 0x00001C85, + 0x1B80, 0x00001C87, + 0x1B80, 0x4D001C95, + 0x1B80, 0x4D001C97, + 0x1B80, 0x00011CA5, + 0x1B80, 0x00011CA7, + 0x1B80, 0x549F1CB5, + 0x1B80, 0x549F1CB7, + 0x1B80, 0x54FF1CC5, + 0x1B80, 0x54FF1CC7, + 0x1B80, 0x54001CD5, + 0x1B80, 0x54001CD7, + 0x1B80, 0x00011CE5, + 0x1B80, 0x00011CE7, 0x1B80, 0x5C311CF5, 0x1B80, 0x5C311CF7, - 0x1B80, 0x00011D05, - 0x1B80, 0x00011D07, - 0x1B80, 0x4C981D15, - 0x1B80, 0x4C981D17, - 0x1B80, 0x4C181D25, - 0x1B80, 0x4C181D27, + 0x1B80, 0x07141D05, + 0x1B80, 0x07141D07, + 0x1B80, 0x54001D15, + 0x1B80, 0x54001D17, + 0x1B80, 0x5C321D25, + 0x1B80, 0x5C321D27, 0x1B80, 0x00011D35, 0x1B80, 0x00011D37, 0x1B80, 0x5C321D45, 0x1B80, 0x5C321D47, - 0x1B80, 0x62841D55, - 0x1B80, 0x62841D57, - 0x1B80, 0x66861D65, - 0x1B80, 0x66861D67, - 0x1B80, 0x6C031D75, - 0x1B80, 0x6C031D77, - 0x1B80, 0x7B201D85, - 0x1B80, 0x7B201D87, - 0x1B80, 0x7A001D95, - 0x1B80, 0x7A001D97, - 0x1B80, 0x79001DA5, - 0x1B80, 0x79001DA7, - 0x1B80, 0x7F201DB5, - 0x1B80, 0x7F201DB7, - 0x1B80, 0x7E001DC5, - 0x1B80, 0x7E001DC7, - 0x1B80, 0x7D001DD5, - 0x1B80, 0x7D001DD7, - 0x1B80, 0x09011DE5, - 0x1B80, 0x09011DE7, - 0x1B80, 0x0C011DF5, - 0x1B80, 0x0C011DF7, - 0x1B80, 0x0BA61E05, - 0x1B80, 0x0BA61E07, - 0x1B80, 0x00011E15, - 0x1B80, 0x00011E17, + 0x1B80, 0x07141D55, + 0x1B80, 0x07141D57, + 0x1B80, 0x54001D65, + 0x1B80, 0x54001D67, + 0x1B80, 0x5C311D75, + 0x1B80, 0x5C311D77, + 0x1B80, 0x00011D85, + 0x1B80, 0x00011D87, + 0x1B80, 0x4C981D95, + 0x1B80, 0x4C981D97, + 0x1B80, 0x4C181DA5, + 0x1B80, 0x4C181DA7, + 0x1B80, 0x00011DB5, + 0x1B80, 0x00011DB7, + 0x1B80, 0x5C321DC5, + 0x1B80, 0x5C321DC7, + 0x1B80, 0x62841DD5, + 0x1B80, 0x62841DD7, + 0x1B80, 0x66861DE5, + 0x1B80, 0x66861DE7, + 0x1B80, 0x6C031DF5, + 0x1B80, 0x6C031DF7, + 0x1B80, 0x7B201E05, + 0x1B80, 0x7B201E07, + 0x1B80, 0x7A001E15, + 0x1B80, 0x7A001E17, + 0x1B80, 0x79001E25, + 0x1B80, 0x79001E27, + 0x1B80, 0x7F201E35, + 0x1B80, 0x7F201E37, + 0x1B80, 0x7E001E45, + 0x1B80, 0x7E001E47, + 0x1B80, 0x7D001E55, + 0x1B80, 0x7D001E57, + 0x1B80, 0x09011E65, + 0x1B80, 0x09011E67, + 0x1B80, 0x0C011E75, + 0x1B80, 0x0C011E77, + 0x1B80, 0x0BA61E85, + 0x1B80, 0x0BA61E87, + 0x1B80, 0x00011E95, + 0x1B80, 0x00011E97, 0x1B80, 0x00000006, 0x1B80, 0x00000002, }; void -odm_read_and_config_mp_8821c_phy_reg( - struct PHY_DM_STRUCT *p_dm_odm -) +odm_read_and_config_mp_8821c_phy_reg(struct dm_struct *dm) { u32 i = 0; u8 c_cond; boolean is_matched = true, is_skipped = false; - u32 array_len = sizeof(array_mp_8821c_phy_reg)/sizeof(u32); + u32 array_len = sizeof(array_mp_8821c_phy_reg) / sizeof(u32); u32 *array = array_mp_8821c_phy_reg; u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_phy_reg\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); while ((i + 1) < array_len) { v1 = array[i]; @@ -3272,22 +3916,22 @@ odm_read_and_config_mp_8821c_phy_reg( if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ if (v1 & BIT(31)) {/* positive condition*/ - c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); if (c_cond == COND_ENDIF) {/*end*/ is_matched = true; is_skipped = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); } else if (c_cond == COND_ELSE) { /*else*/ - is_matched = is_skipped?false:true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + is_matched = is_skipped ? false : true; + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); } } else if (v1 & BIT(30)) { /*negative condition*/ if (is_skipped == false) { - if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { is_matched = true; is_skipped = true; } else { @@ -3299,7 +3943,7 @@ odm_read_and_config_mp_8821c_phy_reg( } } else { if (is_matched) - odm_config_bb_phy_8821c(p_dm_odm, v1, MASKDWORD, v2); + odm_config_bb_phy_8821c(dm, v1, MASKDWORD, v2); } i = i + 2; } @@ -3308,7 +3952,7 @@ odm_read_and_config_mp_8821c_phy_reg( u32 odm_get_version_mp_8821c_phy_reg(void) { - return 36; + return 49; } /****************************************************************************** @@ -3317,23 +3961,22 @@ odm_get_version_mp_8821c_phy_reg(void) u32 array_mp_8821c_phy_reg_mp[] = { 0x810, 0x21104285, + 0xAA8, 0xEAD30004, }; void -odm_read_and_config_mp_8821c_phy_reg_mp( - struct PHY_DM_STRUCT *p_dm_odm -) +odm_read_and_config_mp_8821c_phy_reg_mp(struct dm_struct *dm) { u32 i = 0; u8 c_cond; boolean is_matched = true, is_skipped = false; - u32 array_len = sizeof(array_mp_8821c_phy_reg_mp)/sizeof(u32); + u32 array_len = sizeof(array_mp_8821c_phy_reg_mp) / sizeof(u32); u32 *array = array_mp_8821c_phy_reg_mp; u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_phy_reg_mp\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); while ((i + 1) < array_len) { v1 = array[i]; @@ -3341,22 +3984,22 @@ odm_read_and_config_mp_8821c_phy_reg_mp( if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ if (v1 & BIT(31)) {/* positive condition*/ - c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); if (c_cond == COND_ENDIF) {/*end*/ is_matched = true; is_skipped = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); } else if (c_cond == COND_ELSE) { /*else*/ - is_matched = is_skipped?false:true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + is_matched = is_skipped ? false : true; + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); } } else if (v1 & BIT(30)) { /*negative condition*/ if (is_skipped == false) { - if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { is_matched = true; is_skipped = true; } else { @@ -3368,7 +4011,7 @@ odm_read_and_config_mp_8821c_phy_reg_mp( } } else { if (is_matched) - odm_config_bb_phy_8821c(p_dm_odm, v1, MASKDWORD, v2); + odm_config_bb_phy_8821c(dm, v1, MASKDWORD, v2); } i = i + 2; } @@ -3377,7 +4020,7 @@ odm_read_and_config_mp_8821c_phy_reg_mp( u32 odm_get_version_mp_8821c_phy_reg_mp(void) { - return 36; + return 49; } /****************************************************************************** @@ -3403,40 +4046,99 @@ u32 array_mp_8821c_phy_reg_pg[] = { }; void -odm_read_and_config_mp_8821c_phy_reg_pg( - struct PHY_DM_STRUCT *p_dm_odm -) +odm_read_and_config_mp_8821c_phy_reg_pg(struct dm_struct *dm) { u32 i = 0; - u32 array_len = sizeof(array_mp_8821c_phy_reg_pg)/sizeof(u32); + u32 array_len = sizeof(array_mp_8821c_phy_reg_pg) / sizeof(u32); u32 *array = array_mp_8821c_phy_reg_pg; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len / 6; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); + + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i + 1]; + u32 v3 = array[i + 2]; + u32 v4 = array[i + 3]; + u32 v5 = array[i + 4]; + u32 v6 = array[i + 5]; + + odm_config_bb_phy_reg_pg_8821c(dm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0 ? "2.4G" : " 5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6); +#endif + } +} + + + +/****************************************************************************** +* phy_reg_pg_type0x28.TXT +******************************************************************************/ + +u32 array_mp_8821c_phy_reg_pg_type0x28[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36363636, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363636, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363636, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x22222224, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x40404040, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x32343638, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x38383838, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x36363636, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x30323436, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x26262628 +}; + +void +odm_read_and_config_mp_8821c_phy_reg_pg_type0x28(struct dm_struct *dm) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8821c_phy_reg_pg_type0x28) / sizeof(u32); + u32 *array = array_mp_8821c_phy_reg_pg_type0x28; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - PlatformZeroMemory(p_hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - p_hal_data->nLinesReadPwrByRate = array_len/6; + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len / 6; #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_phy_reg_pg\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); - p_dm_odm->phy_reg_pg_version = 1; - p_dm_odm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; for (i = 0; i < array_len; i += 6) { u32 v1 = array[i]; - u32 v2 = array[i+1]; - u32 v3 = array[i+2]; - u32 v4 = array[i+3]; - u32 v5 = array[i+4]; - u32 v6 = array[i+5]; + u32 v2 = array[i + 1]; + u32 v3 = array[i + 2]; + u32 v4 = array[i + 3]; + u32 v5 = array[i + 4]; + u32 v6 = array[i + 5]; - odm_config_bb_phy_reg_pg_8821c(p_dm_odm, v1, v2, v3, v4, v5, v6); + odm_config_bb_phy_reg_pg_8821c(dm, v1, v2, v3, v4, v5, v6); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)p_hal_data->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", - (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0 ? "2.4G" : " 5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6); #endif } } diff --git a/hal/phydm/rtl8821c/halhwimg8821c_bb.h b/hal/phydm/rtl8821c/halhwimg8821c_bb.h index 5656feb..baffb1d 100644 --- a/hal/phydm/rtl8821c/halhwimg8821c_bb.h +++ b/hal/phydm/rtl8821c/halhwimg8821c_bb.h @@ -1,24 +1,29 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ -/*Image2HeaderVersion: 3.4*/ +/*Image2HeaderVersion: R3 1.0*/ #if (RTL8821C_SUPPORT == 1) #ifndef __INC_MP_BB_HW_IMG_8821C_H #define __INC_MP_BB_HW_IMG_8821C_H @@ -29,55 +34,58 @@ ******************************************************************************/ void -odm_read_and_config_mp_8821c_agc_tab(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm -); -u32 odm_get_version_mp_8821c_agc_tab(void); +odm_read_and_config_mp_8821c_agc_tab( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8821c_agc_tab(void); /****************************************************************************** * agc_tab_diff.TXT ******************************************************************************/ -extern u32 array_mp_8821c_agc_tab_diff_wlg[520]; -extern u32 array_mp_8821c_agc_tab_diff_btg[520]; +extern u32 array_mp_8821c_agc_tab_diff_wlg[780]; +extern u32 array_mp_8821c_agc_tab_diff_btg[780]; void -odm_read_and_config_mp_8821c_agc_tab_diff( - struct PHY_DM_STRUCT *p_dm_odm, - u32 array[], - u32 array_len -); -u32 odm_get_version_mp_8821c_agc_tab_diff(void); +odm_read_and_config_mp_8821c_agc_tab_diff(struct dm_struct *dm, u32 array[], + u32 array_len); +u32 odm_get_version_mp_8821c_agc_tab_diff(void); /****************************************************************************** * phy_reg.TXT ******************************************************************************/ void -odm_read_and_config_mp_8821c_phy_reg(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm -); -u32 odm_get_version_mp_8821c_phy_reg(void); +odm_read_and_config_mp_8821c_phy_reg( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8821c_phy_reg(void); /****************************************************************************** * phy_reg_mp.TXT ******************************************************************************/ void -odm_read_and_config_mp_8821c_phy_reg_mp(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm -); -u32 odm_get_version_mp_8821c_phy_reg_mp(void); +odm_read_and_config_mp_8821c_phy_reg_mp( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8821c_phy_reg_mp(void); /****************************************************************************** * phy_reg_pg.TXT ******************************************************************************/ void -odm_read_and_config_mp_8821c_phy_reg_pg(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm -); +odm_read_and_config_mp_8821c_phy_reg_pg( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); u32 odm_get_version_mp_8821c_phy_reg_pg(void); +/****************************************************************************** +* phy_reg_pg_type0x28.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_phy_reg_pg_type0x28( + /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8821c_phy_reg_pg_type0x28(void); + #endif #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8821c/halhwimg8821c_mac.c b/hal/phydm/rtl8821c/halhwimg8821c_mac.c index 31fa779..1ad56f2 100644 --- a/hal/phydm/rtl8821c/halhwimg8821c_mac.c +++ b/hal/phydm/rtl8821c/halhwimg8821c_mac.c @@ -1,118 +1,106 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ -/*Image2HeaderVersion: 3.4*/ +/*Image2HeaderVersion: R3 1.0*/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (RTL8821C_SUPPORT == 1) static boolean check_positive( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2, const u32 condition3, const u32 condition4 ) { - u8 _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ - ((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/ - ((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/ - ((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */ - ((p_dm_odm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/ - ((p_dm_odm->board_type & BIT(1)) >> 1) << 5; /* _NGFF*/ - u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; - u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; - u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; + u8 cut_version_for_para = (dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version; + u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; u32 driver1 = cut_version_for_para << 24 | - (p_dm_odm->support_interface & 0xF0) << 16 | - p_dm_odm->support_platform << 16 | + (dm->support_interface & 0xF0) << 16 | + dm->support_platform << 16 | pkg_type_for_para << 12 | - (p_dm_odm->support_interface & 0x0F) << 8 | - _board_type; + (dm->support_interface & 0x0F) << 8 | + dm->rfe_type; - u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | - (p_dm_odm->type_gpa & 0xFF) << 8 | - (p_dm_odm->type_alna & 0xFF) << 16 | - (p_dm_odm->type_apa & 0xFF) << 24; + u32 driver2 = (dm->type_glna & 0xFF) << 0 | + (dm->type_gpa & 0xFF) << 8 | + (dm->type_alna & 0xFF) << 16 | + (dm->type_apa & 0xFF) << 24; u32 driver3 = 0; - u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | - (p_dm_odm->type_gpa & 0xFF00) | - (p_dm_odm->type_alna & 0xFF00) << 8 | - (p_dm_odm->type_apa & 0xFF00) << 16; + u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | + (dm->type_gpa & 0xFF00) | + (dm->type_alna & 0xFF00) << 8 | + (dm->type_apa & 0xFF00) << 16; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, cond1, cond2, cond3, cond4); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, driver1, driver2, driver3, driver4); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type)); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Platform, Interface) = (0x%X, 0x%X)\n", + dm->support_platform, dm->support_interface); + PHYDM_DBG(dm, ODM_COMP_INIT, " (RFE, Package) = (0x%X, 0x%X)\n", + dm->rfe_type, dm->package_type); /*============== value Defined Check ===============*/ - /*QFN type [15:12] and cut version [27:24] need to do value check*/ + /*cut version [27:24] need to do value check*/ + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return false; + /*pkg type [15:12] need to do value check*/ if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) return false; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return false; + /*interface [11:8] need to do value check*/ + if (((cond1 & 0x00000F00) != 0) && ((cond1 & 0x00000F00) != (driver1 & 0x00000F00))) + return false; /*=============== Bit Defined Check ================*/ /* We don't care [31:28] */ - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u32 bit_mask = 0; - - if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/ - return true; + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; - if ((cond1 & BIT(0)) != 0) /*GLNA*/ - bit_mask |= 0x000000FF; - if ((cond1 & BIT(1)) != 0) /*GPA*/ - bit_mask |= 0x0000FF00; - if ((cond1 & BIT(2)) != 0) /*ALNA*/ - bit_mask |= 0x00FF0000; - if ((cond1 & BIT(3)) != 0) /*APA*/ - bit_mask |= 0xFF000000; - - if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/ - return true; - else - return false; - } else + if (cond1 == driver1) + return true; + else return false; } static boolean check_negative( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2 ) @@ -190,8 +178,6 @@ u32 array_mp_8821c_mac_reg[] = { 0x144E, 0x00000006, 0x4C8, 0x000000FF, 0x4C9, 0x00000008, - 0x4CA, 0x0000002B, - 0x4CB, 0x0000002B, 0x4CC, 0x000000FF, 0x4CD, 0x000000FF, 0x4CE, 0x00000001, @@ -269,19 +255,17 @@ u32 array_mp_8821c_mac_reg[] = { }; void -odm_read_and_config_mp_8821c_mac_reg( - struct PHY_DM_STRUCT *p_dm_odm -) +odm_read_and_config_mp_8821c_mac_reg(struct dm_struct *dm) { u32 i = 0; u8 c_cond; boolean is_matched = true, is_skipped = false; - u32 array_len = sizeof(array_mp_8821c_mac_reg)/sizeof(u32); + u32 array_len = sizeof(array_mp_8821c_mac_reg) / sizeof(u32); u32 *array = array_mp_8821c_mac_reg; u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_mac_reg\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); while ((i + 1) < array_len) { v1 = array[i]; @@ -289,22 +273,22 @@ odm_read_and_config_mp_8821c_mac_reg( if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ if (v1 & BIT(31)) {/* positive condition*/ - c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); if (c_cond == COND_ENDIF) {/*end*/ is_matched = true; is_skipped = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); } else if (c_cond == COND_ELSE) { /*else*/ - is_matched = is_skipped?false:true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + is_matched = is_skipped ? false : true; + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); } else {/*if , else if*/ pre_v1 = v1; pre_v2 = v2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); } } else if (v1 & BIT(30)) { /*negative condition*/ if (is_skipped == false) { - if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { is_matched = true; is_skipped = true; } else { @@ -316,7 +300,7 @@ odm_read_and_config_mp_8821c_mac_reg( } } else { if (is_matched) - odm_config_mac_8821c(p_dm_odm, v1, (u8)v2); + odm_config_mac_8821c(dm, v1, (u8)v2); } i = i + 2; } @@ -325,7 +309,7 @@ odm_read_and_config_mp_8821c_mac_reg( u32 odm_get_version_mp_8821c_mac_reg(void) { - return 36; + return 49; } #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8821c/halhwimg8821c_mac.h b/hal/phydm/rtl8821c/halhwimg8821c_mac.h index 5742282..54beda8 100644 --- a/hal/phydm/rtl8821c/halhwimg8821c_mac.h +++ b/hal/phydm/rtl8821c/halhwimg8821c_mac.h @@ -1,24 +1,29 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ -/*Image2HeaderVersion: 3.4*/ +/*Image2HeaderVersion: R3 1.0*/ #if (RTL8821C_SUPPORT == 1) #ifndef __INC_MP_MAC_HW_IMG_8821C_H #define __INC_MP_MAC_HW_IMG_8821C_H @@ -29,10 +34,9 @@ ******************************************************************************/ void -odm_read_and_config_mp_8821c_mac_reg(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm -); -u32 odm_get_version_mp_8821c_mac_reg(void); +odm_read_and_config_mp_8821c_mac_reg( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8821c_mac_reg(void); #endif #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8821c/halhwimg8821c_rf.c b/hal/phydm/rtl8821c/halhwimg8821c_rf.c index 597c6ca..76509e4 100644 --- a/hal/phydm/rtl8821c/halhwimg8821c_rf.c +++ b/hal/phydm/rtl8821c/halhwimg8821c_rf.c @@ -1,118 +1,106 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ -/*Image2HeaderVersion: 3.4*/ +/*Image2HeaderVersion: R3 1.0*/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (RTL8821C_SUPPORT == 1) static boolean check_positive( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2, const u32 condition3, const u32 condition4 ) { - u8 _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ - ((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/ - ((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/ - ((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */ - ((p_dm_odm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/ - ((p_dm_odm->board_type & BIT(1)) >> 1) << 5; /* _NGFF*/ - u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; - u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; - u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; + u8 cut_version_for_para = (dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version; + u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; u32 driver1 = cut_version_for_para << 24 | - (p_dm_odm->support_interface & 0xF0) << 16 | - p_dm_odm->support_platform << 16 | + (dm->support_interface & 0xF0) << 16 | + dm->support_platform << 16 | pkg_type_for_para << 12 | - (p_dm_odm->support_interface & 0x0F) << 8 | - _board_type; + (dm->support_interface & 0x0F) << 8 | + dm->rfe_type; - u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | - (p_dm_odm->type_gpa & 0xFF) << 8 | - (p_dm_odm->type_alna & 0xFF) << 16 | - (p_dm_odm->type_apa & 0xFF) << 24; + u32 driver2 = (dm->type_glna & 0xFF) << 0 | + (dm->type_gpa & 0xFF) << 8 | + (dm->type_alna & 0xFF) << 16 | + (dm->type_apa & 0xFF) << 24; u32 driver3 = 0; - u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | - (p_dm_odm->type_gpa & 0xFF00) | - (p_dm_odm->type_alna & 0xFF00) << 8 | - (p_dm_odm->type_apa & 0xFF00) << 16; + u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | + (dm->type_gpa & 0xFF00) | + (dm->type_alna & 0xFF00) << 8 | + (dm->type_apa & 0xFF00) << 16; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, cond1, cond2, cond3, cond4); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, driver1, driver2, driver3, driver4); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, - (" (Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type)); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Platform, Interface) = (0x%X, 0x%X)\n", + dm->support_platform, dm->support_interface); + PHYDM_DBG(dm, ODM_COMP_INIT, " (RFE, Package) = (0x%X, 0x%X)\n", + dm->rfe_type, dm->package_type); /*============== value Defined Check ===============*/ - /*QFN type [15:12] and cut version [27:24] need to do value check*/ + /*cut version [27:24] need to do value check*/ + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return false; + /*pkg type [15:12] need to do value check*/ if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) return false; - if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) - return false; + /*interface [11:8] need to do value check*/ + if (((cond1 & 0x00000F00) != 0) && ((cond1 & 0x00000F00) != (driver1 & 0x00000F00))) + return false; /*=============== Bit Defined Check ================*/ /* We don't care [31:28] */ - cond1 &= 0x00FF0FFF; - driver1 &= 0x00FF0FFF; - - if ((cond1 & driver1) == cond1) { - u32 bit_mask = 0; - - if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/ - return true; - - if ((cond1 & BIT(0)) != 0) /*GLNA*/ - bit_mask |= 0x000000FF; - if ((cond1 & BIT(1)) != 0) /*GPA*/ - bit_mask |= 0x0000FF00; - if ((cond1 & BIT(2)) != 0) /*ALNA*/ - bit_mask |= 0x00FF0000; - if ((cond1 & BIT(3)) != 0) /*APA*/ - bit_mask |= 0xFF000000; - - if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/ - return true; - else - return false; - } else + cond1 &= 0x000000FF; + driver1 &= 0x000000FF; + + if (cond1 == driver1) + return true; + else return false; } static boolean check_negative( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, const u32 condition1, const u32 condition2 ) @@ -125,8 +113,44 @@ check_negative( ******************************************************************************/ u32 array_mp_8821c_radioa[] = { + 0x80001005, 0x00000000, 0x40000000, 0x00000000, 0x000, 0x00010000, 0x018, 0x00010D24, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x000, 0x00010000, + 0x018, 0x00010D24, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x000, 0x00010000, + 0x018, 0x00010D24, + 0xA0000000, 0x00000000, + 0x000, 0x00010000, + 0x018, 0x00010D24, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000002, + 0x03E, 0x0000003F, + 0x03F, 0x000C0F4E, + 0x033, 0x00000001, + 0x03E, 0x00000034, + 0x03F, 0x0004080E, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000002, + 0x03E, 0x0000003F, + 0x03F, 0x000C0F4E, + 0x033, 0x00000001, + 0x03E, 0x00000034, + 0x03F, 0x0004080E, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000002, + 0x03E, 0x0000003F, + 0x03F, 0x000C0F4E, + 0x033, 0x00000001, + 0x03E, 0x00000034, + 0x03F, 0x0004080E, + 0xA0000000, 0x00000000, 0x0EF, 0x00080000, 0x033, 0x00000002, 0x03E, 0x0000003F, @@ -134,14 +158,152 @@ u32 array_mp_8821c_radioa[] = { 0x033, 0x00000001, 0x03E, 0x00000034, 0x03F, 0x0004080E, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x00000000, + 0x03F, 0x000005DF, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x00000000, + 0x03F, 0x000005DF, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00002000, + 0x033, 0x00000000, + 0x03F, 0x000005DF, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, 0x0EF, 0x00002000, 0x033, 0x00000000, 0x03F, 0x000005DF, 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x000005DF, + 0x0EE, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x000005DF, + 0x0EE, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x000005DF, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, 0x0EE, 0x00000400, 0x033, 0x00000000, 0x03F, 0x000005DF, 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x0B1, 0x0007DBE4, + 0x0B2, 0x000225D1, + 0x0B3, 0x000FC760, + 0x0B4, 0x00099DD0, + 0x0B5, 0x000400FC, + 0x0B6, 0x000187F0, + 0x0B7, 0x00030018, + 0x0B8, 0x00080800, + 0x0B9, 0x00000000, + 0x0BA, 0x00008000, + 0x0BB, 0x00000004, + 0x0BC, 0x00040000, + 0x0BD, 0x00000000, + 0x0BE, 0x00000000, + 0x0BF, 0x00000000, + 0x0C0, 0x00000000, + 0x0C1, 0x00000000, + 0x0C2, 0x00000000, + 0x0C3, 0x00000000, + 0x0C4, 0x00002402, + 0x0C5, 0x00000009, + 0x0C6, 0x00040299, + 0x0C7, 0x00055555, + 0x0C8, 0x0000C16C, + 0x0C9, 0x0001C140, + 0x0CA, 0x00000000, + 0x0CB, 0x00000000, + 0x0CC, 0x00000000, + 0x0CD, 0x00000000, + 0x0CE, 0x00090C00, + 0x0CF, 0x0006D200, + 0x0DF, 0x00000009, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x0B1, 0x0007DBE4, + 0x0B2, 0x000225D1, + 0x0B3, 0x000FC760, + 0x0B4, 0x00099DD0, + 0x0B5, 0x000400FC, + 0x0B6, 0x000187F0, + 0x0B7, 0x00030018, + 0x0B8, 0x00080800, + 0x0B9, 0x00000000, + 0x0BA, 0x00008000, + 0x0BB, 0x00000004, + 0x0BC, 0x00040000, + 0x0BD, 0x00000000, + 0x0BE, 0x00000000, + 0x0BF, 0x00000000, + 0x0C0, 0x00000000, + 0x0C1, 0x00000000, + 0x0C2, 0x00000000, + 0x0C3, 0x00000000, + 0x0C4, 0x00002402, + 0x0C5, 0x00000009, + 0x0C6, 0x00040299, + 0x0C7, 0x00055555, + 0x0C8, 0x0000C16C, + 0x0C9, 0x0001C140, + 0x0CA, 0x00000000, + 0x0CB, 0x00000000, + 0x0CC, 0x00000000, + 0x0CD, 0x00000000, + 0x0CE, 0x00090C00, + 0x0CF, 0x0006D200, + 0x0DF, 0x00000009, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x0B1, 0x0007DBE4, + 0x0B2, 0x000225D1, + 0x0B3, 0x000FC760, + 0x0B4, 0x00099DD0, + 0x0B5, 0x000400FC, + 0x0B6, 0x000187F0, + 0x0B7, 0x00030018, + 0x0B8, 0x00080800, + 0x0B9, 0x00000000, + 0x0BA, 0x00008000, + 0x0BB, 0x00000004, + 0x0BC, 0x00040000, + 0x0BD, 0x00000000, + 0x0BE, 0x00000000, + 0x0BF, 0x00000000, + 0x0C0, 0x00000000, + 0x0C1, 0x00000000, + 0x0C2, 0x00000000, + 0x0C3, 0x00000000, + 0x0C4, 0x00002402, + 0x0C5, 0x00000009, + 0x0C6, 0x00040299, + 0x0C7, 0x00055555, + 0x0C8, 0x0000C16C, + 0x0C9, 0x0001C140, + 0x0CA, 0x00000000, + 0x0CB, 0x00000000, + 0x0CC, 0x00000000, + 0x0CD, 0x00000000, + 0x0CE, 0x00090C00, + 0x0CF, 0x0006D200, + 0x0DF, 0x00000009, + 0xA0000000, 0x00000000, 0x0B0, 0x000FF0F8, 0x0B1, 0x0007DBE4, 0x0B2, 0x000225D1, @@ -175,12 +337,18 @@ u32 array_mp_8821c_radioa[] = { 0x0CE, 0x00090C00, 0x0CF, 0x0006D200, 0x0DF, 0x00000009, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, 0x0EE, 0x00010000, 0x033, 0x00000058, 0x03F, 0x0000001C, 0x0EE, 0x00000000, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00010000, + 0x033, 0x00000058, + 0x03F, 0x0000001C, + 0x0EE, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, 0x0EE, 0x00010000, 0x033, 0x00000058, 0x03F, 0x0000001C, @@ -188,253 +356,376 @@ u32 array_mp_8821c_radioa[] = { 0xA0000000, 0x00000000, 0x0EE, 0x00010000, 0x033, 0x00000058, - 0x03F, 0x0000002C, + 0x03F, 0x0000001C, 0x0EE, 0x00000000, 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, 0x018, 0x00010524, 0x081, 0x0000FCC1, 0x089, 0x00000004, 0x08A, 0x0008A186, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x08B, 0x0006FFFC, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x08C, 0x000312C7, + 0x08D, 0x00020888, + 0x08E, 0x00064140, + 0x08F, 0x000A8010, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00010524, + 0x081, 0x0000FCC1, + 0x089, 0x00000004, + 0x08A, 0x0008A186, 0x08B, 0x0006FFFC, - 0xA0000000, 0x00000000, - 0x08B, 0x0007060C, - 0xB0000000, 0x00000000, 0x08C, 0x000312C7, 0x08D, 0x00020888, - 0x81000000, 0x00000000, 0x40000000, 0x00000000, 0x08E, 0x00064140, - 0xA0000000, 0x00000000, - 0x08E, 0x00064540, - 0xB0000000, 0x00000000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x08F, 0x000A8010, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00010524, + 0x081, 0x0000FCC1, + 0x089, 0x00000004, + 0x08A, 0x0008A186, + 0x08B, 0x0007060C, + 0x08C, 0x000312C7, + 0x08D, 0x00020888, + 0x08E, 0x00064140, 0x08F, 0x000A8010, 0xA0000000, 0x00000000, - 0x08F, 0x000A8018, + 0x018, 0x00010524, + 0x081, 0x0000FCC1, + 0x089, 0x00000004, + 0x08A, 0x0008A186, + 0x08B, 0x0007060C, + 0x08C, 0x000312C7, + 0x08D, 0x00020888, + 0x08E, 0x00064140, + 0x08F, 0x000A8010, 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0DD, 0x00000020, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x0DD, 0x00000020, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0DD, 0x00000020, + 0xA0000000, 0x00000000, + 0x0DD, 0x00000020, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00020000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00020000, - 0x033, 0x00000007, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038000, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038000, 0xA0000000, 0x00000000, - 0x03E, 0x0003C000, + 0x0EF, 0x00020000, 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000007, + 0x03E, 0x00038000, 0x03F, 0x000C3186, 0x033, 0x00000006, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00038080, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038080, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C080, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000005, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x000380C8, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x000380C8, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C0C8, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000004, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00038190, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038190, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C190, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000003, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038998, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00038998, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C998, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000002, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00039840, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00039840, - 0xA0000000, 0x00000000, - 0x03E, 0x0003D840, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000001, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x000398C4, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x000398C4, - 0xA0000000, 0x00000000, - 0x03E, 0x0003D8C4, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00039930, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00039930, - 0xA0000000, 0x00000000, - 0x03E, 0x0003D930, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, - 0x033, 0x0000000F, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038000, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000007, 0x03E, 0x00038000, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C000, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, - 0x033, 0x0000000E, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038080, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000006, 0x03E, 0x00038080, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C080, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, - 0x033, 0x0000000D, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x000380C8, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000005, 0x03E, 0x000380C8, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C0C8, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, - 0x033, 0x0000000C, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038190, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000004, 0x03E, 0x00038190, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C190, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, - 0x033, 0x0000000B, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000003, 0x03E, 0x00038998, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000002, + 0x03E, 0x00039840, + 0x03F, 0x000C3186, + 0x033, 0x00000001, + 0x03E, 0x000398C4, + 0x03F, 0x000C3186, + 0x033, 0x00000000, + 0x03E, 0x00039930, + 0x03F, 0x000C3186, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000007, + 0x03E, 0x00038000, + 0x03F, 0x000C3186, + 0x033, 0x00000006, + 0x03E, 0x00038080, + 0x03F, 0x000C3186, + 0x033, 0x00000005, + 0x03E, 0x000380C8, + 0x03F, 0x000C3186, + 0x033, 0x00000004, + 0x03E, 0x00038190, + 0x03F, 0x000C3186, + 0x033, 0x00000003, 0x03E, 0x00038998, + 0x03F, 0x000C3186, + 0x033, 0x00000002, + 0x03E, 0x00039840, + 0x03F, 0x000C3186, + 0x033, 0x00000001, + 0x03E, 0x000398C4, + 0x03F, 0x000C3186, + 0x033, 0x00000000, + 0x03E, 0x00039930, + 0x03F, 0x000C3186, 0xA0000000, 0x00000000, - 0x03E, 0x0003C998, + 0x033, 0x00000007, + 0x03E, 0x00038000, + 0x03F, 0x000C3186, + 0x033, 0x00000006, + 0x03E, 0x00038080, + 0x03F, 0x000C3186, + 0x033, 0x00000005, + 0x03E, 0x000380C8, + 0x03F, 0x000C3186, + 0x033, 0x00000004, + 0x03E, 0x00038190, + 0x03F, 0x000C3186, + 0x033, 0x00000003, + 0x03E, 0x00038998, + 0x03F, 0x000C3186, + 0x033, 0x00000002, + 0x03E, 0x00039840, + 0x03F, 0x000C3186, + 0x033, 0x00000001, + 0x03E, 0x000398C4, + 0x03F, 0x000C3186, + 0x033, 0x00000000, + 0x03E, 0x00039930, + 0x03F, 0x000C3186, 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x0000000F, + 0x03E, 0x00038000, + 0x03F, 0x000C3186, + 0x033, 0x0000000E, + 0x03E, 0x00038080, + 0x03F, 0x000C3186, + 0x033, 0x0000000D, + 0x03E, 0x000380C8, + 0x03F, 0x000C3186, + 0x033, 0x0000000C, + 0x03E, 0x00038190, + 0x03F, 0x000C3186, + 0x033, 0x0000000B, + 0x03E, 0x00038998, 0x03F, 0x000C3186, 0x033, 0x0000000A, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00039840, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00039840, - 0xA0000000, 0x00000000, - 0x03E, 0x0003D840, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000009, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x000398C4, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000008, + 0x03E, 0x00039930, + 0x03F, 0x000C3186, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x0000000F, + 0x03E, 0x00038000, + 0x03F, 0x000C3186, + 0x033, 0x0000000E, + 0x03E, 0x00038080, + 0x03F, 0x000C3186, + 0x033, 0x0000000D, + 0x03E, 0x000380C8, + 0x03F, 0x000C3186, + 0x033, 0x0000000C, + 0x03E, 0x00038190, + 0x03F, 0x000C3186, + 0x033, 0x0000000B, + 0x03E, 0x00038998, + 0x03F, 0x000C3186, + 0x033, 0x0000000A, + 0x03E, 0x00039840, + 0x03F, 0x000C3186, + 0x033, 0x00000009, 0x03E, 0x000398C4, - 0xA0000000, 0x00000000, - 0x03E, 0x0003D8C4, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000008, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00039930, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x0000000F, + 0x03E, 0x00038000, + 0x03F, 0x000C3186, + 0x033, 0x0000000E, + 0x03E, 0x00038080, + 0x03F, 0x000C3186, + 0x033, 0x0000000D, + 0x03E, 0x000380C8, + 0x03F, 0x000C3186, + 0x033, 0x0000000C, + 0x03E, 0x00038190, + 0x03F, 0x000C3186, + 0x033, 0x0000000B, + 0x03E, 0x00038998, + 0x03F, 0x000C3186, + 0x033, 0x0000000A, + 0x03E, 0x00039840, + 0x03F, 0x000C3186, + 0x033, 0x00000009, + 0x03E, 0x000398C4, + 0x03F, 0x000C3186, + 0x033, 0x00000008, 0x03E, 0x00039930, + 0x03F, 0x000C3186, 0xA0000000, 0x00000000, - 0x03E, 0x0003D930, - 0xB0000000, 0x00000000, + 0x033, 0x0000000F, + 0x03E, 0x00038000, + 0x03F, 0x000C3186, + 0x033, 0x0000000E, + 0x03E, 0x00038080, + 0x03F, 0x000C3186, + 0x033, 0x0000000D, + 0x03E, 0x000380C8, + 0x03F, 0x000C3186, + 0x033, 0x0000000C, + 0x03E, 0x00038190, + 0x03F, 0x000C3186, + 0x033, 0x0000000B, + 0x03E, 0x00038998, + 0x03F, 0x000C3186, + 0x033, 0x0000000A, + 0x03E, 0x00039840, 0x03F, 0x000C3186, + 0x033, 0x00000009, + 0x03E, 0x000398C4, + 0x03F, 0x000C3186, + 0x033, 0x00000008, + 0x03E, 0x00039930, + 0x03F, 0x000C3186, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x00000017, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038000, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00038000, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C000, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000016, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00038080, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038080, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C080, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000015, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x000380C8, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x000380C8, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C0C8, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000014, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00038190, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038190, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C190, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000013, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00038998, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00038998, - 0xA0000000, 0x00000000, - 0x03E, 0x0003C998, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000012, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00039840, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03E, 0x00039840, - 0xA0000000, 0x00000000, - 0x03E, 0x0003D840, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000011, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x000398C4, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000010, + 0x03E, 0x00039930, + 0x03F, 0x000C3186, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000017, + 0x03E, 0x00038000, + 0x03F, 0x000C3186, + 0x033, 0x00000016, + 0x03E, 0x00038080, + 0x03F, 0x000C3186, + 0x033, 0x00000015, + 0x03E, 0x000380C8, + 0x03F, 0x000C3186, + 0x033, 0x00000014, + 0x03E, 0x00038190, + 0x03F, 0x000C3186, + 0x033, 0x00000013, + 0x03E, 0x00038998, + 0x03F, 0x000C3186, + 0x033, 0x00000012, + 0x03E, 0x00039840, + 0x03F, 0x000C3186, + 0x033, 0x00000011, 0x03E, 0x000398C4, - 0xA0000000, 0x00000000, - 0x03E, 0x0003D8C4, - 0xB0000000, 0x00000000, 0x03F, 0x000C3186, 0x033, 0x00000010, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03E, 0x00039930, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C3186, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000017, + 0x03E, 0x00038000, + 0x03F, 0x000C3186, + 0x033, 0x00000016, + 0x03E, 0x00038080, + 0x03F, 0x000C3186, + 0x033, 0x00000015, + 0x03E, 0x000380C8, + 0x03F, 0x000C3186, + 0x033, 0x00000014, + 0x03E, 0x00038190, + 0x03F, 0x000C3186, + 0x033, 0x00000013, + 0x03E, 0x00038998, + 0x03F, 0x000C3186, + 0x033, 0x00000012, + 0x03E, 0x00039840, + 0x03F, 0x000C3186, + 0x033, 0x00000011, + 0x03E, 0x000398C4, + 0x03F, 0x000C3186, + 0x033, 0x00000010, 0x03E, 0x00039930, + 0x03F, 0x000C3186, + 0x0EF, 0x00000000, 0xA0000000, 0x00000000, - 0x03E, 0x0003D930, - 0xB0000000, 0x00000000, + 0x033, 0x00000017, + 0x03E, 0x00038000, + 0x03F, 0x000C3186, + 0x033, 0x00000016, + 0x03E, 0x00038080, + 0x03F, 0x000C3186, + 0x033, 0x00000015, + 0x03E, 0x000380C8, + 0x03F, 0x000C3186, + 0x033, 0x00000014, + 0x03E, 0x00038190, + 0x03F, 0x000C3186, + 0x033, 0x00000013, + 0x03E, 0x00038998, + 0x03F, 0x000C3186, + 0x033, 0x00000012, + 0x03E, 0x00039840, + 0x03F, 0x000C3186, + 0x033, 0x00000011, + 0x03E, 0x000398C4, + 0x03F, 0x000C3186, + 0x033, 0x00000010, + 0x03E, 0x00039930, 0x03F, 0x000C3186, 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00004000, 0x033, 0x00000000, 0x03F, 0x0000000F, @@ -443,17 +734,174 @@ u32 array_mp_8821c_radioa[] = { 0x033, 0x00000002, 0x03F, 0x00000005, 0x0EF, 0x00000000, - 0x018, 0x00000401, - 0x084, 0x00001209, - 0x086, 0x000001A0, - 0x087, 0x000E8180, - 0x088, 0x00047020, - 0x0DF, 0x00008009, - 0x0EF, 0x00008000, - 0x033, 0x0000000F, - 0x03F, 0x0000003C, - 0x033, 0x0000000E, - 0x03F, 0x00000038, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x0000000F, + 0x033, 0x00000001, + 0x03F, 0x0000000A, + 0x033, 0x00000002, + 0x03F, 0x00000005, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x0000000F, + 0x033, 0x00000001, + 0x03F, 0x0000000A, + 0x033, 0x00000002, + 0x03F, 0x00000005, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x0000000F, + 0x033, 0x00000001, + 0x03F, 0x0000000A, + 0x033, 0x00000002, + 0x03F, 0x00000005, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00000401, + 0x084, 0x00001209, + 0x086, 0x000001A0, + 0x087, 0x000E8180, + 0x088, 0x00006020, + 0x0DF, 0x00008009, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00000401, + 0x084, 0x00001209, + 0x086, 0x000001A0, + 0x087, 0x000E8180, + 0x088, 0x00006020, + 0x0DF, 0x00008009, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00000401, + 0x084, 0x00001209, + 0x086, 0x000001A0, + 0x087, 0x000E8180, + 0x088, 0x00006020, + 0x0DF, 0x00008009, + 0xA0000000, 0x00000000, + 0x018, 0x00000401, + 0x084, 0x00001209, + 0x086, 0x000001A0, + 0x087, 0x000E8180, + 0x088, 0x00006020, + 0x0DF, 0x00008009, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00008000, + 0x033, 0x0000000F, + 0x03F, 0x0000003C, + 0x033, 0x0000000E, + 0x03F, 0x00000038, + 0x033, 0x0000000D, + 0x03F, 0x00000030, + 0x033, 0x0000000C, + 0x03F, 0x00000028, + 0x033, 0x0000000B, + 0x03F, 0x00000020, + 0x033, 0x0000000A, + 0x03F, 0x00000018, + 0x033, 0x00000009, + 0x03F, 0x00000010, + 0x033, 0x00000008, + 0x03F, 0x00000008, + 0x033, 0x00000007, + 0x03F, 0x0000003C, + 0x033, 0x00000006, + 0x03F, 0x00000038, + 0x033, 0x00000005, + 0x03F, 0x00000030, + 0x033, 0x00000004, + 0x03F, 0x00000028, + 0x033, 0x00000003, + 0x03F, 0x00000020, + 0x033, 0x00000002, + 0x03F, 0x00000018, + 0x033, 0x00000001, + 0x03F, 0x00000010, + 0x033, 0x00000000, + 0x03F, 0x00000008, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00008000, + 0x033, 0x0000000F, + 0x03F, 0x0000003C, + 0x033, 0x0000000E, + 0x03F, 0x00000038, + 0x033, 0x0000000D, + 0x03F, 0x00000030, + 0x033, 0x0000000C, + 0x03F, 0x00000028, + 0x033, 0x0000000B, + 0x03F, 0x00000020, + 0x033, 0x0000000A, + 0x03F, 0x00000018, + 0x033, 0x00000009, + 0x03F, 0x00000010, + 0x033, 0x00000008, + 0x03F, 0x00000008, + 0x033, 0x00000007, + 0x03F, 0x0000003C, + 0x033, 0x00000006, + 0x03F, 0x00000038, + 0x033, 0x00000005, + 0x03F, 0x00000030, + 0x033, 0x00000004, + 0x03F, 0x00000028, + 0x033, 0x00000003, + 0x03F, 0x00000020, + 0x033, 0x00000002, + 0x03F, 0x00000018, + 0x033, 0x00000001, + 0x03F, 0x00000010, + 0x033, 0x00000000, + 0x03F, 0x00000008, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00008000, + 0x033, 0x0000000F, + 0x03F, 0x0000003C, + 0x033, 0x0000000E, + 0x03F, 0x00000038, + 0x033, 0x0000000D, + 0x03F, 0x00000030, + 0x033, 0x0000000C, + 0x03F, 0x00000028, + 0x033, 0x0000000B, + 0x03F, 0x00000020, + 0x033, 0x0000000A, + 0x03F, 0x00000018, + 0x033, 0x00000009, + 0x03F, 0x00000010, + 0x033, 0x00000008, + 0x03F, 0x00000008, + 0x033, 0x00000007, + 0x03F, 0x0000003C, + 0x033, 0x00000006, + 0x03F, 0x00000038, + 0x033, 0x00000005, + 0x03F, 0x00000030, + 0x033, 0x00000004, + 0x03F, 0x00000028, + 0x033, 0x00000003, + 0x03F, 0x00000020, + 0x033, 0x00000002, + 0x03F, 0x00000018, + 0x033, 0x00000001, + 0x03F, 0x00000010, + 0x033, 0x00000000, + 0x03F, 0x00000008, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00008000, + 0x033, 0x0000000F, + 0x03F, 0x0000003C, + 0x033, 0x0000000E, + 0x03F, 0x00000038, 0x033, 0x0000000D, 0x03F, 0x00000030, 0x033, 0x0000000C, @@ -483,39 +931,21 @@ u32 array_mp_8821c_radioa[] = { 0x033, 0x00000000, 0x03F, 0x00000008, 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, 0x0EE, 0x00000002, 0x033, 0x0000001E, 0x03F, 0x00000000, 0x033, 0x0000001C, - 0x81000000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00000000, - 0xA0000000, 0x00000000, - 0x03F, 0x00000006, - 0xB0000000, 0x00000000, 0x033, 0x0000000E, - 0x81000000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00000000, - 0xA0000000, 0x00000000, - 0x03F, 0x00000006, - 0xB0000000, 0x00000000, 0x033, 0x0000000C, - 0x81000000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00000000, - 0xA0000000, 0x00000000, - 0x03F, 0x00000006, - 0xB0000000, 0x00000000, 0x033, 0x0000000A, - 0x81000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00000000, - 0xA0000000, 0x00000000, - 0x03F, 0x00000006, - 0xB0000000, 0x00000000, + 0x03F, 0x00000002, 0x033, 0x00000008, - 0x81000000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00000000, - 0xA0000000, 0x00000000, - 0x03F, 0x00000006, - 0xB0000000, 0x00000000, 0x033, 0x00000036, 0x03F, 0x00000000, 0x033, 0x00000037, @@ -543,395 +973,695 @@ u32 array_mp_8821c_radioa[] = { 0x033, 0x00000000, 0x03F, 0x00000006, 0x0EE, 0x00000000, - 0x0A0, 0x000F0005, - 0x0A1, 0x0006C000, - 0x0A2, 0x0000161B, - 0x0A3, 0x000B9D3D, - 0x0AF, 0x00070000, - 0x0DE, 0x00000200, - 0x0EE, 0x00000100, - 0x033, 0x00000007, - 0x03F, 0x00000043, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00000002, + 0x033, 0x0000001E, + 0x03F, 0x00000000, + 0x033, 0x0000001C, + 0x03F, 0x00000000, + 0x033, 0x0000000E, + 0x03F, 0x00000000, + 0x033, 0x0000000C, + 0x03F, 0x00000000, + 0x033, 0x0000000A, + 0x03F, 0x00000002, + 0x033, 0x00000008, + 0x03F, 0x00000000, + 0x033, 0x00000036, + 0x03F, 0x00000000, + 0x033, 0x00000037, + 0x03F, 0x00000000, + 0x033, 0x00000034, + 0x03F, 0x00000000, + 0x033, 0x00000026, + 0x03F, 0x00000006, + 0x033, 0x00000027, + 0x03F, 0x00000006, + 0x033, 0x00000024, + 0x03F, 0x00000006, + 0x033, 0x00000022, + 0x03F, 0x00000006, + 0x033, 0x00000020, + 0x03F, 0x00000006, 0x033, 0x00000006, - 0x03F, 0x0000007A, - 0x033, 0x00000005, - 0x03F, 0x00000041, + 0x03F, 0x00000000, + 0x033, 0x00000007, + 0x03F, 0x00000006, 0x033, 0x00000004, - 0x03F, 0x00000079, - 0x033, 0x00000003, - 0x03F, 0x00000043, + 0x03F, 0x00000006, 0x033, 0x00000002, - 0x03F, 0x0000007A, - 0x033, 0x00000001, - 0x03F, 0x00000041, + 0x03F, 0x00000006, 0x033, 0x00000000, - 0x03F, 0x00000079, + 0x03F, 0x00000006, + 0x0EE, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00000002, + 0x033, 0x0000001E, + 0x03F, 0x00000000, + 0x033, 0x0000001C, + 0x03F, 0x00000000, + 0x033, 0x0000000E, + 0x03F, 0x00000000, + 0x033, 0x0000000C, + 0x03F, 0x00000000, + 0x033, 0x0000000A, + 0x03F, 0x00000002, + 0x033, 0x00000008, + 0x03F, 0x00000000, + 0x033, 0x00000036, + 0x03F, 0x00000000, + 0x033, 0x00000037, + 0x03F, 0x00000000, + 0x033, 0x00000034, + 0x03F, 0x00000000, + 0x033, 0x00000026, + 0x03F, 0x00000006, + 0x033, 0x00000027, + 0x03F, 0x00000006, + 0x033, 0x00000024, + 0x03F, 0x00000006, + 0x033, 0x00000022, + 0x03F, 0x00000006, + 0x033, 0x00000020, + 0x03F, 0x00000006, + 0x033, 0x00000006, + 0x03F, 0x00000000, + 0x033, 0x00000007, + 0x03F, 0x00000006, + 0x033, 0x00000004, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000006, + 0x033, 0x00000000, + 0x03F, 0x00000006, 0x0EE, 0x00000000, - 0x0B8, 0x00080A00, - 0x0B0, 0x000FF0FA, - 0xFFE, 0x00000000, - 0x0CA, 0x00080000, - 0x0C9, 0x0001C141, - 0xFFE, 0x00000000, - 0x0B0, 0x000FF0F8, - 0x018, 0x00018D24, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0xFFE, 0x00000000, - 0x018, 0x00010D24, - 0x01B, 0x00003A40, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x0004D3A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x061, 0x0004D3A3, - 0xA0000000, 0x00000000, - 0x061, 0x0004D3A1, - 0xB0000000, 0x00000000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x062, 0x0000D303, - 0xA0000000, 0x00000000, - 0x062, 0x0000D3A3, - 0xB0000000, 0x00000000, - 0x063, 0x00000002, - 0x0EF, 0x00000200, - 0x030, 0x00000000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A0, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, - 0x030, 0x00001000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A0, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, + 0x0EE, 0x00000002, + 0x033, 0x0000001E, + 0x03F, 0x00000000, + 0x033, 0x0000001C, + 0x03F, 0x00000000, + 0x033, 0x0000000E, + 0x03F, 0x00000000, + 0x033, 0x0000000C, + 0x03F, 0x00000000, + 0x033, 0x0000000A, + 0x03F, 0x00000002, + 0x033, 0x00000008, + 0x03F, 0x00000000, + 0x033, 0x00000036, + 0x03F, 0x00000000, + 0x033, 0x00000037, + 0x03F, 0x00000000, + 0x033, 0x00000034, + 0x03F, 0x00000000, + 0x033, 0x00000026, + 0x03F, 0x00000006, + 0x033, 0x00000027, + 0x03F, 0x00000006, + 0x033, 0x00000024, + 0x03F, 0x00000006, + 0x033, 0x00000022, + 0x03F, 0x00000006, + 0x033, 0x00000020, + 0x03F, 0x00000006, + 0x033, 0x00000006, + 0x03F, 0x00000000, + 0x033, 0x00000007, + 0x03F, 0x00000006, + 0x033, 0x00000004, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000006, + 0x033, 0x00000000, + 0x03F, 0x00000006, + 0x0EE, 0x00000000, 0xB0000000, 0x00000000, - 0x030, 0x00002000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000331A0, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0A0, 0x000F0005, + 0x0A1, 0x0006C000, + 0x0A2, 0x0000161B, + 0x0A3, 0x000B9CBD, + 0x0AF, 0x00070000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0A0, 0x000F0005, + 0x0A1, 0x0006C000, + 0x0A2, 0x0000161B, + 0x0A3, 0x000B9CBD, + 0x0AF, 0x00070000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0A0, 0x000F0005, + 0x0A1, 0x0006C000, + 0x0A2, 0x0000161B, + 0x0A3, 0x000B9CBD, + 0x0AF, 0x00070000, 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, + 0x0A0, 0x000F0005, + 0x0A1, 0x0006C000, + 0x0A2, 0x0000161B, + 0x0A3, 0x000B9CBD, + 0x0AF, 0x00070000, 0xB0000000, 0x00000000, - 0x030, 0x00003000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A0, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0DE, 0x00000200, + 0x0EE, 0x00000100, + 0x033, 0x00000007, + 0x03F, 0x00000043, + 0x033, 0x00000006, + 0x03F, 0x0000007A, + 0x033, 0x00000005, + 0x03F, 0x00000041, + 0x033, 0x00000004, + 0x03F, 0x00000079, + 0x033, 0x00000003, + 0x03F, 0x00000043, + 0x033, 0x00000002, + 0x03F, 0x0000007A, + 0x033, 0x00000001, + 0x03F, 0x00000041, + 0x033, 0x00000000, + 0x03F, 0x00000079, + 0x0EE, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0DE, 0x00000200, + 0x0EE, 0x00000100, + 0x033, 0x00000007, + 0x03F, 0x00000043, + 0x033, 0x00000006, + 0x03F, 0x0000007A, + 0x033, 0x00000005, + 0x03F, 0x00000041, + 0x033, 0x00000004, + 0x03F, 0x00000079, + 0x033, 0x00000003, + 0x03F, 0x00000043, + 0x033, 0x00000002, + 0x03F, 0x0000007A, + 0x033, 0x00000001, + 0x03F, 0x00000041, + 0x033, 0x00000000, + 0x03F, 0x00000079, + 0x0EE, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0DE, 0x00000200, + 0x0EE, 0x00000100, + 0x033, 0x00000007, + 0x03F, 0x00000043, + 0x033, 0x00000006, + 0x03F, 0x0000007A, + 0x033, 0x00000005, + 0x03F, 0x00000041, + 0x033, 0x00000004, + 0x03F, 0x00000079, + 0x033, 0x00000003, + 0x03F, 0x00000043, + 0x033, 0x00000002, + 0x03F, 0x0000007A, + 0x033, 0x00000001, + 0x03F, 0x00000041, + 0x033, 0x00000000, + 0x03F, 0x00000079, + 0x0EE, 0x00000000, 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, + 0x0DE, 0x00000200, + 0x0EE, 0x00000100, + 0x033, 0x00000007, + 0x03F, 0x00000043, + 0x033, 0x00000006, + 0x03F, 0x0000007A, + 0x033, 0x00000005, + 0x03F, 0x00000041, + 0x033, 0x00000004, + 0x03F, 0x00000079, + 0x033, 0x00000003, + 0x03F, 0x00000043, + 0x033, 0x00000002, + 0x03F, 0x0000007A, + 0x033, 0x00000001, + 0x03F, 0x00000041, + 0x033, 0x00000000, + 0x03F, 0x00000079, + 0x0EE, 0x00000000, 0xB0000000, 0x00000000, - 0x030, 0x00004000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00080A00, + 0x0B0, 0x000FF0FA, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00080A00, + 0x0B0, 0x000FF0FA, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0B8, 0x00080A00, + 0x0B0, 0x000FF0FA, 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, + 0x0B8, 0x00080A00, + 0x0B0, 0x000FF0FA, 0xB0000000, 0x00000000, - 0x030, 0x00005000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, + 0xFFE, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0CA, 0x00080000, + 0x0C9, 0x0001C141, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0CA, 0x00080000, + 0x0C9, 0x0001C141, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0CA, 0x00080000, + 0x0C9, 0x0001C141, 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, + 0x0CA, 0x00080000, + 0x0C9, 0x0001C141, 0xB0000000, 0x00000000, - 0x030, 0x00006000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, + 0xFFE, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0B0, 0x000FF0F8, 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, + 0x0B0, 0x000FF0F8, 0xB0000000, 0x00000000, - 0x030, 0x00007000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00018D24, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00018D24, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00018D24, 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, + 0x018, 0x00018D24, 0xB0000000, 0x00000000, - 0x030, 0x00008000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00010D24, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00010D24, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x018, 0x00010D24, 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, + 0x018, 0x00010D24, 0xB0000000, 0x00000000, - 0x030, 0x00009000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00003A40, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00003A40, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00003A40, 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, + 0x01B, 0x00003A40, 0xB0000000, 0x00000000, - 0x030, 0x0000A000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0004D3A3, + 0x062, 0x0000D303, + 0x063, 0x00000002, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0004D3A3, + 0x062, 0x0000D303, + 0x063, 0x00000002, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0004D3A1, + 0x062, 0x0000D3A3, + 0x063, 0x00000002, 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, + 0x061, 0x0004D3A1, + 0x062, 0x0000D3A3, + 0x063, 0x00000002, 0xB0000000, 0x00000000, - 0x030, 0x0000B000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x00000000, + 0x03F, 0x00033303, + 0x030, 0x00001000, + 0x03F, 0x00033303, + 0x030, 0x00002000, + 0x03F, 0x00033303, + 0x030, 0x00003000, + 0x03F, 0x00033303, + 0x030, 0x00004000, + 0x03F, 0x00033303, + 0x030, 0x00005000, + 0x03F, 0x00033303, + 0x030, 0x00006000, + 0x03F, 0x00033303, + 0x030, 0x00007000, + 0x03F, 0x00033303, + 0x030, 0x00008000, + 0x03F, 0x00033303, + 0x030, 0x00009000, + 0x03F, 0x00033303, + 0x030, 0x0000A000, + 0x03F, 0x00033303, + 0x030, 0x0000B000, + 0x03F, 0x00033303, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000200, + 0x030, 0x00000000, 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0x030, 0x0000A000, + 0x03F, 0x000335A3, + 0x030, 0x0000B000, + 0x03F, 0x000335A3, + 0x0EF, 0x00000000, 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, + 0x0EF, 0x00000200, + 0x030, 0x00000000, + 0x03F, 0x000335A3, + 0x030, 0x00001000, + 0x03F, 0x000335A3, + 0x030, 0x00002000, + 0x03F, 0x000335A3, + 0x030, 0x00003000, + 0x03F, 0x000335A3, + 0x030, 0x00004000, + 0x03F, 0x000335A3, + 0x030, 0x00005000, + 0x03F, 0x000335A3, + 0x030, 0x00006000, + 0x03F, 0x000335A3, + 0x030, 0x00007000, + 0x03F, 0x000335A3, + 0x030, 0x00008000, + 0x03F, 0x000335A3, + 0x030, 0x00009000, + 0x03F, 0x000335A3, + 0x030, 0x0000A000, + 0x03F, 0x000335A3, + 0x030, 0x0000B000, + 0x03F, 0x000335A3, + 0x0EF, 0x00000000, 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x033, 0x00000000, + 0x03F, 0x00033303, + 0x033, 0x00000001, + 0x03F, 0x00033303, + 0x033, 0x00000002, + 0x03F, 0x00033303, + 0x033, 0x00000003, + 0x03F, 0x00033303, + 0x033, 0x00000004, + 0x03F, 0x00033303, + 0x033, 0x00000005, + 0x03F, 0x00033303, + 0x033, 0x00000006, + 0x03F, 0x00033303, + 0x033, 0x00000007, + 0x03F, 0x00033303, + 0x033, 0x00000008, + 0x03F, 0x00033303, + 0x033, 0x00000009, + 0x03F, 0x00033303, + 0x033, 0x0000000A, + 0x03F, 0x00033303, + 0x033, 0x0000000B, + 0x03F, 0x00033303, + 0x033, 0x0000000C, + 0x03F, 0x00033303, + 0x033, 0x0000000D, + 0x03F, 0x00033303, + 0x033, 0x0000000E, + 0x03F, 0x00033303, + 0x033, 0x0000000F, + 0x03F, 0x00033303, + 0x033, 0x00000010, + 0x03F, 0x00033303, + 0x033, 0x00000011, + 0x03F, 0x00033303, + 0x033, 0x00000012, + 0x03F, 0x00033303, 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000080, 0x033, 0x00000000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A0, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x033, 0x00000001, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A0, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x033, 0x00000002, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A0, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x033, 0x00000003, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A0, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x033, 0x00000004, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A0, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x033, 0x00000005, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A0, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x033, 0x00000006, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A0, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x033, 0x00000007, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00033303, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000313A0, - 0x91000000, 0x00000000, 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0x00000000, 0x03F, 0x000333A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x033, 0x0000000F, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000333A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x033, 0x00000010, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000333A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x033, 0x00000011, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000333A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x033, 0x00000012, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x000333A3, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x000333A1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000080, + 0x033, 0x00000000, + 0x03F, 0x000335A3, + 0x033, 0x00000001, + 0x03F, 0x000335A3, + 0x033, 0x00000002, + 0x03F, 0x000335A3, + 0x033, 0x00000003, + 0x03F, 0x000335A3, + 0x033, 0x00000004, + 0x03F, 0x000335A3, + 0x033, 0x00000005, + 0x03F, 0x000335A3, + 0x033, 0x00000006, + 0x03F, 0x000335A3, + 0x033, 0x00000007, + 0x03F, 0x000335A3, + 0x033, 0x00000008, + 0x03F, 0x000335A3, + 0x033, 0x00000009, + 0x03F, 0x000335A3, + 0x033, 0x0000000A, + 0x03F, 0x000335A3, + 0x033, 0x0000000B, + 0x03F, 0x000335A3, + 0x033, 0x0000000C, + 0x03F, 0x000335A3, + 0x033, 0x0000000D, + 0x03F, 0x000335A3, + 0x033, 0x0000000E, + 0x03F, 0x000335A3, + 0x033, 0x0000000F, + 0x03F, 0x000335A3, + 0x033, 0x00000010, + 0x03F, 0x000335A3, + 0x033, 0x00000011, + 0x03F, 0x000335A3, + 0x033, 0x00000012, 0x03F, 0x000335A3, - 0xA0000000, 0x00000000, - 0x03F, 0x000335A1, - 0xB0000000, 0x00000000, 0x0EF, 0x00000000, - 0x0EF, 0x00000040, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x030, 0x00000644, - 0x030, 0x00001412, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x030, 0x00000743, - 0x030, 0x00001412, 0xA0000000, 0x00000000, - 0x030, 0x00000640, - 0x030, 0x00001512, - 0xB0000000, 0x00000000, - 0x030, 0x00002202, - 0x030, 0x00004000, - 0x030, 0x00005000, - 0x030, 0x00006000, - 0x0EF, 0x00000000, - 0x0EF, 0x00000800, - 0x033, 0x00000020, - 0x03F, 0x00000E42, - 0x033, 0x00000021, - 0x03F, 0x00000E45, - 0x033, 0x00000022, + 0x0EF, 0x00000080, + 0x033, 0x00000000, + 0x03F, 0x000335A3, + 0x033, 0x00000001, + 0x03F, 0x000335A3, + 0x033, 0x00000002, + 0x03F, 0x000335A3, + 0x033, 0x00000003, + 0x03F, 0x000335A3, + 0x033, 0x00000004, + 0x03F, 0x000335A3, + 0x033, 0x00000005, + 0x03F, 0x000335A3, + 0x033, 0x00000006, + 0x03F, 0x000335A3, + 0x033, 0x00000007, + 0x03F, 0x000335A3, + 0x033, 0x00000008, + 0x03F, 0x000335A3, + 0x033, 0x00000009, + 0x03F, 0x000335A3, + 0x033, 0x0000000A, + 0x03F, 0x000335A3, + 0x033, 0x0000000B, + 0x03F, 0x000335A3, + 0x033, 0x0000000C, + 0x03F, 0x000335A3, + 0x033, 0x0000000D, + 0x03F, 0x000335A3, + 0x033, 0x0000000E, + 0x03F, 0x000335A3, + 0x033, 0x0000000F, + 0x03F, 0x000335A3, + 0x033, 0x00000010, + 0x03F, 0x000335A3, + 0x033, 0x00000011, + 0x03F, 0x000335A3, + 0x033, 0x00000012, + 0x03F, 0x000335A3, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000644, + 0x030, 0x00001135, + 0x030, 0x00002133, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000644, + 0x030, 0x00001412, + 0x030, 0x00002202, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000640, + 0x030, 0x00001512, + 0x030, 0x00002202, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000040, + 0x030, 0x00000640, + 0x030, 0x00001512, + 0x030, 0x00002202, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000800, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000800, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000800, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000800, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000001, + 0x033, 0x00000021, + 0x03F, 0x00000004, + 0x033, 0x00000022, + 0x03F, 0x00000007, + 0x033, 0x00000023, + 0x03F, 0x00000024, + 0x033, 0x00000024, + 0x03F, 0x00000027, + 0x033, 0x00000025, + 0x03F, 0x0000002A, + 0x033, 0x00000026, + 0x03F, 0x0000002D, + 0x033, 0x00000027, + 0x03F, 0x00000030, + 0x033, 0x00000028, + 0x03F, 0x00000033, + 0x033, 0x00000029, + 0x03F, 0x00000036, + 0x033, 0x0000002A, + 0x03F, 0x00000039, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000E42, + 0x033, 0x00000021, + 0x03F, 0x00000E45, + 0x033, 0x00000022, + 0x03F, 0x00000E65, + 0x033, 0x00000023, + 0x03F, 0x00000E68, + 0x033, 0x00000024, + 0x03F, 0x00000EE4, + 0x033, 0x00000025, + 0x03F, 0x00000EE7, + 0x033, 0x00000026, + 0x03F, 0x00000EEA, + 0x033, 0x00000027, + 0x03F, 0x00000EED, + 0x033, 0x00000028, + 0x03F, 0x00000EF0, + 0x033, 0x00000029, + 0x03F, 0x00000EF3, + 0x033, 0x0000002A, + 0x03F, 0x00000EF6, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000020, + 0x03F, 0x00000E42, + 0x033, 0x00000021, + 0x03F, 0x00000E45, + 0x033, 0x00000022, 0x03F, 0x00000E48, 0x033, 0x00000023, 0x03F, 0x00000E68, @@ -949,34 +1679,112 @@ u32 array_mp_8821c_radioa[] = { 0x03F, 0x00000EF3, 0x033, 0x0000002A, 0x03F, 0x00000EF6, - 0x033, 0x00000060, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00000E0A, 0xA0000000, 0x00000000, - 0x03F, 0x00000E09, + 0x033, 0x00000020, + 0x03F, 0x00000E42, + 0x033, 0x00000021, + 0x03F, 0x00000E45, + 0x033, 0x00000022, + 0x03F, 0x00000E65, + 0x033, 0x00000023, + 0x03F, 0x00000E68, + 0x033, 0x00000024, + 0x03F, 0x00000EE4, + 0x033, 0x00000025, + 0x03F, 0x00000EE7, + 0x033, 0x00000026, + 0x03F, 0x00000EEA, + 0x033, 0x00000027, + 0x03F, 0x00000EED, + 0x033, 0x00000028, + 0x03F, 0x00000EF0, + 0x033, 0x00000029, + 0x03F, 0x00000EF3, + 0x033, 0x0000002A, + 0x03F, 0x00000EF6, 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000001, + 0x033, 0x00000061, + 0x03F, 0x00000004, + 0x033, 0x00000062, + 0x03F, 0x00000007, + 0x033, 0x00000063, + 0x03F, 0x00000024, + 0x033, 0x00000064, + 0x03F, 0x00000027, + 0x033, 0x00000065, + 0x03F, 0x0000002A, + 0x033, 0x00000066, + 0x03F, 0x0000002D, + 0x033, 0x00000067, + 0x03F, 0x00000030, + 0x033, 0x00000068, + 0x03F, 0x00000033, + 0x033, 0x00000069, + 0x03F, 0x00000036, + 0x033, 0x0000006A, + 0x03F, 0x00000039, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000E42, + 0x033, 0x00000061, + 0x03F, 0x00000E45, + 0x033, 0x00000062, + 0x03F, 0x00000E65, + 0x033, 0x00000063, + 0x03F, 0x00000E68, + 0x033, 0x00000064, + 0x03F, 0x00000EE5, + 0x033, 0x00000065, + 0x03F, 0x00000EE8, + 0x033, 0x00000066, + 0x03F, 0x00000EEB, + 0x033, 0x00000067, + 0x03F, 0x00000EEE, + 0x033, 0x00000068, + 0x03F, 0x00000EF1, + 0x033, 0x00000069, + 0x03F, 0x00000EF4, + 0x033, 0x0000006A, + 0x03F, 0x00000EF7, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000E09, 0x033, 0x00000061, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00000E44, - 0xA0000000, 0x00000000, 0x03F, 0x00000E43, - 0xB0000000, 0x00000000, 0x033, 0x00000062, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00000E47, - 0xA0000000, 0x00000000, 0x03F, 0x00000E46, - 0xB0000000, 0x00000000, 0x033, 0x00000063, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00000E4A, - 0xA0000000, 0x00000000, 0x03F, 0x00000E49, - 0xB0000000, 0x00000000, 0x033, 0x00000064, - 0x03F, 0x00000E6A, + 0x03F, 0x00000E88, 0x033, 0x00000065, - 0x03F, 0x00000EAA, + 0x03F, 0x00000E8B, + 0x033, 0x00000066, + 0x03F, 0x00000ECB, + 0x033, 0x00000067, + 0x03F, 0x00000ECE, + 0x033, 0x00000068, + 0x03F, 0x00000EF0, + 0x033, 0x00000069, + 0x03F, 0x00000EF3, + 0x033, 0x0000006A, + 0x03F, 0x00000EF6, + 0xA0000000, 0x00000000, + 0x033, 0x00000060, + 0x03F, 0x00000E42, + 0x033, 0x00000061, + 0x03F, 0x00000E45, + 0x033, 0x00000062, + 0x03F, 0x00000E65, + 0x033, 0x00000063, + 0x03F, 0x00000E68, + 0x033, 0x00000064, + 0x03F, 0x00000EE5, + 0x033, 0x00000065, + 0x03F, 0x00000EE8, 0x033, 0x00000066, 0x03F, 0x00000EEB, 0x033, 0x00000067, @@ -987,12 +1795,58 @@ u32 array_mp_8821c_radioa[] = { 0x03F, 0x00000EF4, 0x033, 0x0000006A, 0x03F, 0x00000EF7, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000001, + 0x033, 0x000000A1, + 0x03F, 0x00000004, + 0x033, 0x000000A2, + 0x03F, 0x00000007, + 0x033, 0x000000A3, + 0x03F, 0x00000025, + 0x033, 0x000000A4, + 0x03F, 0x00000028, + 0x033, 0x000000A5, + 0x03F, 0x0000002B, + 0x033, 0x000000A6, + 0x03F, 0x0000002E, + 0x033, 0x000000A7, + 0x03F, 0x00000031, + 0x033, 0x000000A8, + 0x03F, 0x00000034, + 0x033, 0x000000A9, + 0x03F, 0x00000037, + 0x033, 0x000000AA, + 0x03F, 0x0000003A, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, 0x033, 0x000000A0, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00000E08, - 0xA0000000, 0x00000000, 0x03F, 0x00000E09, - 0xB0000000, 0x00000000, + 0x033, 0x000000A1, + 0x03F, 0x00000E43, + 0x033, 0x000000A2, + 0x03F, 0x00000E64, + 0x033, 0x000000A3, + 0x03F, 0x00000E67, + 0x033, 0x000000A4, + 0x03F, 0x00000EE4, + 0x033, 0x000000A5, + 0x03F, 0x00000EE7, + 0x033, 0x000000A6, + 0x03F, 0x00000EEA, + 0x033, 0x000000A7, + 0x03F, 0x00000EED, + 0x033, 0x000000A8, + 0x03F, 0x00000EF0, + 0x033, 0x000000A9, + 0x03F, 0x00000EF3, + 0x033, 0x000000AA, + 0x03F, 0x00000EF6, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000E08, 0x033, 0x000000A1, 0x03F, 0x00000E42, 0x033, 0x000000A2, @@ -1000,9 +1854,33 @@ u32 array_mp_8821c_radioa[] = { 0x033, 0x000000A3, 0x03F, 0x00000E48, 0x033, 0x000000A4, - 0x03F, 0x00000E69, + 0x03F, 0x00000EA5, + 0x033, 0x000000A5, + 0x03F, 0x00000EA8, + 0x033, 0x000000A6, + 0x03F, 0x00000ECA, + 0x033, 0x000000A7, + 0x03F, 0x00000ECD, + 0x033, 0x000000A8, + 0x03F, 0x00000EEF, + 0x033, 0x000000A9, + 0x03F, 0x00000EF2, + 0x033, 0x000000AA, + 0x03F, 0x00000EF5, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x033, 0x000000A0, + 0x03F, 0x00000E09, + 0x033, 0x000000A1, + 0x03F, 0x00000E43, + 0x033, 0x000000A2, + 0x03F, 0x00000E64, + 0x033, 0x000000A3, + 0x03F, 0x00000E67, + 0x033, 0x000000A4, + 0x03F, 0x00000EE4, 0x033, 0x000000A5, - 0x03F, 0x00000EA9, + 0x03F, 0x00000EE7, 0x033, 0x000000A6, 0x03F, 0x00000EEA, 0x033, 0x000000A7, @@ -1014,30 +1892,53 @@ u32 array_mp_8821c_radioa[] = { 0x033, 0x000000AA, 0x03F, 0x00000EF6, 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000400, 0x033, 0x00000000, - 0x81000000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x0006AC00, - 0xA0000000, 0x00000000, - 0x03F, 0x00086A00, - 0xB0000000, 0x00000000, 0x033, 0x00000001, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00060C00, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00060C00, - 0xA0000000, 0x00000000, - 0x03F, 0x00086A00, - 0xB0000000, 0x00000000, 0x033, 0x00000002, - 0x81000000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x0006AC00, - 0xA0000000, 0x00000000, - 0x03F, 0x00086A00, - 0xB0000000, 0x00000000, 0x033, 0x00000003, 0x03F, 0x00086A00, 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x0006AC00, + 0x033, 0x00000001, + 0x03F, 0x00060C00, + 0x033, 0x00000002, + 0x03F, 0x0006AC00, + 0x033, 0x00000003, + 0x03F, 0x00086A00, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x0006AC00, + 0x033, 0x00000001, + 0x03F, 0x00060C00, + 0x033, 0x00000002, + 0x03F, 0x0006AC00, + 0x033, 0x00000003, + 0x03F, 0x00086A00, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x0006AC00, + 0x033, 0x00000001, + 0x03F, 0x00060C00, + 0x033, 0x00000002, + 0x03F, 0x0006AC00, + 0x033, 0x00000003, + 0x03F, 0x00086A00, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000100, 0x033, 0x00000000, 0x03F, 0x00000040, @@ -1048,6 +1949,98 @@ u32 array_mp_8821c_radioa[] = { 0x033, 0x00000003, 0x03F, 0x00000040, 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000000, + 0x03F, 0x00000040, + 0x033, 0x00000001, + 0x03F, 0x00000040, + 0x033, 0x00000002, + 0x03F, 0x00000040, + 0x033, 0x00000003, + 0x03F, 0x00000040, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000000, + 0x03F, 0x00000040, + 0x033, 0x00000001, + 0x03F, 0x00000040, + 0x033, 0x00000002, + 0x03F, 0x00000040, + 0x033, 0x00000003, + 0x03F, 0x00000040, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000000, + 0x03F, 0x00000040, + 0x033, 0x00000001, + 0x03F, 0x00000040, + 0x033, 0x00000002, + 0x03F, 0x00000040, + 0x033, 0x00000003, + 0x03F, 0x00000040, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00040000, + 0x033, 0x00000000, + 0x03F, 0x00086A40, + 0x033, 0x00000001, + 0x03F, 0x00086A40, + 0x033, 0x00000002, + 0x03F, 0x00086A40, + 0x033, 0x00000003, + 0x03F, 0x00086A40, + 0x033, 0x00000004, + 0x03F, 0x00086A40, + 0x033, 0x00000005, + 0x03F, 0x00086A40, + 0x033, 0x00000006, + 0x03F, 0x00084A40, + 0x033, 0x00000007, + 0x03F, 0x00084A40, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00040000, + 0x033, 0x00000000, + 0x03F, 0x00086A40, + 0x033, 0x00000001, + 0x03F, 0x00086A40, + 0x033, 0x00000002, + 0x03F, 0x00086A40, + 0x033, 0x00000003, + 0x03F, 0x00086A40, + 0x033, 0x00000004, + 0x03F, 0x00086A40, + 0x033, 0x00000005, + 0x03F, 0x00086A40, + 0x033, 0x00000006, + 0x03F, 0x00084A40, + 0x033, 0x00000007, + 0x03F, 0x00084A40, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00040000, + 0x033, 0x00000000, + 0x03F, 0x00086A40, + 0x033, 0x00000001, + 0x03F, 0x00086A40, + 0x033, 0x00000002, + 0x03F, 0x00086A40, + 0x033, 0x00000003, + 0x03F, 0x00086A40, + 0x033, 0x00000004, + 0x03F, 0x00086A40, + 0x033, 0x00000005, + 0x03F, 0x00086A40, + 0x033, 0x00000006, + 0x03F, 0x00084A40, + 0x033, 0x00000007, + 0x03F, 0x00084A40, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, 0x0EF, 0x00040000, 0x033, 0x00000000, 0x03F, 0x00086A40, @@ -1066,6 +2059,38 @@ u32 array_mp_8821c_radioa[] = { 0x033, 0x00000007, 0x03F, 0x00084A40, 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x051, 0x000801A8, + 0x052, 0x000972E3, + 0x053, 0x00008069, + 0x054, 0x00030032, + 0x055, 0x00082003, + 0x056, 0x00051CCB, + 0x057, 0x0000CFC2, + 0x058, 0x00000010, + 0x059, 0x00030000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x051, 0x000801A8, + 0x052, 0x000972E3, + 0x053, 0x00008069, + 0x054, 0x00030032, + 0x055, 0x00082003, + 0x056, 0x00051CCB, + 0x057, 0x0000CFC2, + 0x058, 0x00000010, + 0x059, 0x00030000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x051, 0x000801A8, + 0x052, 0x000972E3, + 0x053, 0x00008069, + 0x054, 0x00030032, + 0x055, 0x00082003, + 0x056, 0x00051CCB, + 0x057, 0x0000CFC2, + 0x058, 0x00000010, + 0x059, 0x00030000, + 0xA0000000, 0x00000000, 0x051, 0x000801A8, 0x052, 0x000972E3, 0x053, 0x00008069, @@ -1075,146 +2100,59 @@ u32 array_mp_8821c_radioa[] = { 0x057, 0x0000CFC2, 0x058, 0x00000010, 0x059, 0x00030000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, 0x0EF, 0x00000800, 0x033, 0x00000000, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051429, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00051429, - 0xA0000000, 0x00000000, - 0x03F, 0x00051427, - 0xB0000000, 0x00000000, 0x033, 0x00000001, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051449, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00051449, - 0xA0000000, 0x00000000, - 0x03F, 0x00051446, - 0xB0000000, 0x00000000, 0x033, 0x00000002, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x0005144C, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x0005144C, - 0xA0000000, 0x00000000, - 0x03F, 0x00051449, - 0xB0000000, 0x00000000, 0x033, 0x00000003, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051C66, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00051C66, - 0xA0000000, 0x00000000, - 0x03F, 0x0005144C, - 0xB0000000, 0x00000000, 0x033, 0x00000004, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051C69, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051C67, - 0xA0000000, 0x00000000, 0x03F, 0x00051C69, - 0xB0000000, 0x00000000, 0x033, 0x00000005, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051C6C, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051C6A, - 0xA0000000, 0x00000000, 0x03F, 0x00051C6C, - 0xB0000000, 0x00000000, 0x033, 0x00000006, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, 0x03F, 0x00051CE8, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051C8B, - 0xA0000000, 0x00000000, - 0x03F, 0x00051C8D, - 0xB0000000, 0x00000000, 0x033, 0x00000007, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051CEB, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051CE9, - 0xA0000000, 0x00000000, 0x03F, 0x00051CEB, - 0xB0000000, 0x00000000, 0x033, 0x00000008, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051CEE, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051CEC, - 0xA0000000, 0x00000000, 0x03F, 0x00051CEE, - 0xB0000000, 0x00000000, 0x033, 0x00000009, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051CF1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051CEF, - 0xA0000000, 0x00000000, 0x03F, 0x00051CF1, - 0xB0000000, 0x00000000, 0x033, 0x0000000A, - 0x81001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051CF4, - 0x90001000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051CF1, - 0x91000000, 0x00000000, 0x40000000, 0x00000000, - 0x03F, 0x00051CF2, - 0xA0000000, 0x00000000, 0x03F, 0x00051CF4, - 0xB0000000, 0x00000000, 0x0EF, 0x00000000, - 0x0EE, 0x00004000, - 0x033, 0x00000000, - 0x03F, 0x00048400, - 0x033, 0x00000001, - 0x03F, 0x00086E00, - 0x033, 0x00000002, - 0x03F, 0x00048400, - 0x033, 0x00000003, - 0x03F, 0x00048400, - 0x0EE, 0x00000000, - 0x0EE, 0x00002000, - 0x033, 0x00000000, - 0x03F, 0x00000000, - 0x033, 0x00000001, - 0x03F, 0x00000000, - 0x033, 0x00000002, - 0x03F, 0x00000000, - 0x033, 0x00000003, - 0x03F, 0x00000000, - 0x0EE, 0x00000000, - 0x0EE, 0x00080000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000800, 0x033, 0x00000000, - 0x03F, 0x00048400, + 0x03F, 0x00051429, 0x033, 0x00000001, - 0x03F, 0x00048400, + 0x03F, 0x00051449, 0x033, 0x00000002, - 0x03F, 0x00048400, + 0x03F, 0x0005144C, 0x033, 0x00000003, - 0x03F, 0x00048400, + 0x03F, 0x00051C66, 0x033, 0x00000004, - 0x03F, 0x00048400, + 0x03F, 0x00051C69, 0x033, 0x00000005, - 0x03F, 0x00048400, + 0x03F, 0x00051C6C, 0x033, 0x00000006, - 0x03F, 0x00048400, + 0x03F, 0x00051CE8, 0x033, 0x00000007, - 0x03F, 0x00048400, - 0x0EE, 0x00000000, - 0x070, 0x00008000, - 0x075, 0x000027DA, - 0x076, 0x00006997, - 0x077, 0x00070418, - 0x078, 0x000BB000, - 0x07D, 0x00007600, - 0x07F, 0x00000000, - 0x06A, 0x000F4C00, - 0x065, 0x00082030, - 0x0EE, 0x00008000, + 0x03F, 0x00051CEB, + 0x033, 0x00000008, + 0x03F, 0x00051CEE, + 0x033, 0x00000009, + 0x03F, 0x00051CF1, + 0x033, 0x0000000A, + 0x03F, 0x00051CF4, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000800, 0x033, 0x00000000, 0x03F, 0x00051427, 0x033, 0x00000001, @@ -1224,614 +2162,2600 @@ u32 array_mp_8821c_radioa[] = { 0x033, 0x00000003, 0x03F, 0x0005144C, 0x033, 0x00000004, - 0x03F, 0x00051C69, + 0x03F, 0x00051C67, 0x033, 0x00000005, - 0x03F, 0x00051C6C, + 0x03F, 0x00051C6A, 0x033, 0x00000006, - 0x03F, 0x00051C8D, + 0x03F, 0x00051C8B, 0x033, 0x00000007, - 0x03F, 0x00051CEB, + 0x03F, 0x00051CE9, 0x033, 0x00000008, - 0x03F, 0x00051CEE, + 0x03F, 0x00051CEC, 0x033, 0x00000009, - 0x03F, 0x00051CF1, + 0x03F, 0x00051CEF, 0x033, 0x0000000A, - 0x03F, 0x00051CF4, - 0x0EE, 0x00000000, - 0x0EF, 0x00000010, + 0x03F, 0x00051CF2, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000800, 0x033, 0x00000000, - 0x008, 0x0009C060, + 0x03F, 0x00051427, 0x033, 0x00000001, - 0x008, 0x0009C060, - 0x0EF, 0x00000000, - 0x033, 0x000000A2, - 0x0EF, 0x00080000, - 0x03E, 0x0000593F, - 0x03F, 0x000C0F4F, - 0x0EF, 0x00000000, - 0x033, 0x000000A3, - 0x0EF, 0x00080000, - 0x03E, 0x00005934, - 0x03F, 0x0005AFCF, - 0x0EF, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000024, - 0x03E, 0x0000003F, - 0x03F, 0x00060FDE, - 0x0EF, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000025, - 0x03E, 0x00000037, - 0x03F, 0x0007EFCE, - 0x0EF, 0x00000000, - 0x0EF, 0x00080000, - 0x033, 0x00000026, - 0x03E, 0x00000037, - 0x03F, 0x0005EFCE, + 0x03F, 0x00051446, + 0x033, 0x00000002, + 0x03F, 0x00051449, + 0x033, 0x00000003, + 0x03F, 0x0005144C, + 0x033, 0x00000004, + 0x03F, 0x00051C67, + 0x033, 0x00000005, + 0x03F, 0x00051C6A, + 0x033, 0x00000006, + 0x03F, 0x00051C8B, + 0x033, 0x00000007, + 0x03F, 0x00051CE9, + 0x033, 0x00000008, + 0x03F, 0x00051CEC, + 0x033, 0x00000009, + 0x03F, 0x00051CEF, + 0x033, 0x0000000A, + 0x03F, 0x00051CF2, 0x0EF, 0x00000000, - 0x0EE, 0x00001000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x00048400, + 0x033, 0x00000001, + 0x03F, 0x00086E00, + 0x033, 0x00000002, + 0x03F, 0x00048400, + 0x033, 0x00000003, + 0x03F, 0x00048400, + 0x0EE, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x00048400, + 0x033, 0x00000001, + 0x03F, 0x00086E00, + 0x033, 0x00000002, + 0x03F, 0x00048400, + 0x033, 0x00000003, + 0x03F, 0x00048400, + 0x0EE, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x00048400, + 0x033, 0x00000001, + 0x03F, 0x00086E00, + 0x033, 0x00000002, + 0x03F, 0x00048400, + 0x033, 0x00000003, + 0x03F, 0x00048400, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EE, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x00048400, + 0x033, 0x00000001, + 0x03F, 0x00086E00, + 0x033, 0x00000002, + 0x03F, 0x00048400, + 0x033, 0x00000003, + 0x03F, 0x00048400, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00002000, + 0x033, 0x00000000, + 0x03F, 0x00000000, + 0x033, 0x00000001, + 0x03F, 0x00000000, + 0x033, 0x00000002, + 0x03F, 0x00000000, + 0x033, 0x00000003, + 0x03F, 0x00000000, + 0x0EE, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00002000, + 0x033, 0x00000000, + 0x03F, 0x00000000, + 0x033, 0x00000001, + 0x03F, 0x00000000, + 0x033, 0x00000002, + 0x03F, 0x00000000, + 0x033, 0x00000003, + 0x03F, 0x00000000, + 0x0EE, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00002000, + 0x033, 0x00000000, + 0x03F, 0x00000000, + 0x033, 0x00000001, + 0x03F, 0x00000000, + 0x033, 0x00000002, + 0x03F, 0x00000000, + 0x033, 0x00000003, + 0x03F, 0x00000000, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EE, 0x00002000, + 0x033, 0x00000000, + 0x03F, 0x00000000, + 0x033, 0x00000001, + 0x03F, 0x00000000, + 0x033, 0x00000002, + 0x03F, 0x00000000, + 0x033, 0x00000003, + 0x03F, 0x00000000, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00080000, + 0x033, 0x00000000, + 0x03F, 0x00048400, + 0x033, 0x00000001, + 0x03F, 0x00048400, + 0x033, 0x00000002, + 0x03F, 0x00048400, + 0x033, 0x00000003, + 0x03F, 0x00048400, 0x033, 0x00000004, - 0x03F, 0x00001EC1, + 0x03F, 0x00048400, + 0x033, 0x00000005, + 0x03F, 0x00048400, + 0x033, 0x00000006, + 0x03F, 0x00048400, + 0x033, 0x00000007, + 0x03F, 0x00048400, 0x0EE, 0x00000000, - 0x0EE, 0x00001000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00080000, + 0x033, 0x00000000, + 0x03F, 0x00048400, + 0x033, 0x00000001, + 0x03F, 0x00048400, + 0x033, 0x00000002, + 0x03F, 0x00048400, + 0x033, 0x00000003, + 0x03F, 0x00048400, + 0x033, 0x00000004, + 0x03F, 0x00048400, 0x033, 0x00000005, - 0x03F, 0x00001ECF, + 0x03F, 0x00048400, + 0x033, 0x00000006, + 0x03F, 0x00048400, + 0x033, 0x00000007, + 0x03F, 0x00048400, 0x0EE, 0x00000000, - 0x0EE, 0x00001000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00080000, + 0x033, 0x00000000, + 0x03F, 0x00048400, + 0x033, 0x00000001, + 0x03F, 0x00048400, + 0x033, 0x00000002, + 0x03F, 0x00048400, + 0x033, 0x00000003, + 0x03F, 0x00048400, + 0x033, 0x00000004, + 0x03F, 0x00048400, + 0x033, 0x00000005, + 0x03F, 0x00048400, 0x033, 0x00000006, - 0x03F, 0x00001F9D, + 0x03F, 0x00048400, + 0x033, 0x00000007, + 0x03F, 0x00048400, 0x0EE, 0x00000000, - + 0xA0000000, 0x00000000, + 0x0EE, 0x00080000, + 0x033, 0x00000000, + 0x03F, 0x00048400, + 0x033, 0x00000001, + 0x03F, 0x00048400, + 0x033, 0x00000002, + 0x03F, 0x00048400, + 0x033, 0x00000003, + 0x03F, 0x00048400, + 0x033, 0x00000004, + 0x03F, 0x00048400, + 0x033, 0x00000005, + 0x03F, 0x00048400, + 0x033, 0x00000006, + 0x03F, 0x00048400, + 0x033, 0x00000007, + 0x03F, 0x00048400, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x070, 0x00008000, + 0x075, 0x000027DA, + 0x076, 0x00006997, + 0x077, 0x00070418, + 0x078, 0x000BB000, + 0x07D, 0x00007600, + 0x07F, 0x00000000, + 0x06A, 0x000F4C00, + 0x065, 0x00082030, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x070, 0x00008000, + 0x075, 0x000027DA, + 0x076, 0x00006997, + 0x077, 0x00070418, + 0x078, 0x000BB000, + 0x07D, 0x00007600, + 0x07F, 0x00000000, + 0x06A, 0x000F4C00, + 0x065, 0x00082030, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x070, 0x00008000, + 0x075, 0x000027DA, + 0x076, 0x00006997, + 0x077, 0x00070418, + 0x078, 0x000BB000, + 0x07D, 0x00007600, + 0x07F, 0x00000000, + 0x06A, 0x000F4C00, + 0x065, 0x00082030, + 0xA0000000, 0x00000000, + 0x070, 0x00008000, + 0x075, 0x000027DA, + 0x076, 0x00006997, + 0x077, 0x00070418, + 0x078, 0x000BB000, + 0x07D, 0x00007600, + 0x07F, 0x00000000, + 0x06A, 0x000F4C00, + 0x065, 0x00082030, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00008000, + 0x033, 0x00000000, + 0x03F, 0x00051427, + 0x033, 0x00000001, + 0x03F, 0x00051446, + 0x033, 0x00000002, + 0x03F, 0x00051449, + 0x033, 0x00000003, + 0x03F, 0x0005144C, + 0x033, 0x00000004, + 0x03F, 0x00051C69, + 0x033, 0x00000005, + 0x03F, 0x00051C6C, + 0x033, 0x00000006, + 0x03F, 0x00051C8D, + 0x033, 0x00000007, + 0x03F, 0x00051CEB, + 0x033, 0x00000008, + 0x03F, 0x00051CEE, + 0x033, 0x00000009, + 0x03F, 0x00051CF1, + 0x033, 0x0000000A, + 0x03F, 0x00051CF4, + 0x0EE, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00008000, + 0x033, 0x00000000, + 0x03F, 0x00051427, + 0x033, 0x00000001, + 0x03F, 0x00051446, + 0x033, 0x00000002, + 0x03F, 0x00051449, + 0x033, 0x00000003, + 0x03F, 0x0005144C, + 0x033, 0x00000004, + 0x03F, 0x00051C69, + 0x033, 0x00000005, + 0x03F, 0x00051C6C, + 0x033, 0x00000006, + 0x03F, 0x00051C8D, + 0x033, 0x00000007, + 0x03F, 0x00051CEB, + 0x033, 0x00000008, + 0x03F, 0x00051CEE, + 0x033, 0x00000009, + 0x03F, 0x00051CF1, + 0x033, 0x0000000A, + 0x03F, 0x00051CF4, + 0x0EE, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00008000, + 0x033, 0x00000000, + 0x03F, 0x00051427, + 0x033, 0x00000001, + 0x03F, 0x00051446, + 0x033, 0x00000002, + 0x03F, 0x00051449, + 0x033, 0x00000003, + 0x03F, 0x0005144C, + 0x033, 0x00000004, + 0x03F, 0x00051C69, + 0x033, 0x00000005, + 0x03F, 0x00051C6C, + 0x033, 0x00000006, + 0x03F, 0x00051C8D, + 0x033, 0x00000007, + 0x03F, 0x00051CEB, + 0x033, 0x00000008, + 0x03F, 0x00051CEE, + 0x033, 0x00000009, + 0x03F, 0x00051CF1, + 0x033, 0x0000000A, + 0x03F, 0x00051CF4, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EE, 0x00008000, + 0x033, 0x00000000, + 0x03F, 0x00051427, + 0x033, 0x00000001, + 0x03F, 0x00051446, + 0x033, 0x00000002, + 0x03F, 0x00051449, + 0x033, 0x00000003, + 0x03F, 0x0005144C, + 0x033, 0x00000004, + 0x03F, 0x00051C69, + 0x033, 0x00000005, + 0x03F, 0x00051C6C, + 0x033, 0x00000006, + 0x03F, 0x00051C8D, + 0x033, 0x00000007, + 0x03F, 0x00051CEB, + 0x033, 0x00000008, + 0x03F, 0x00051CEE, + 0x033, 0x00000009, + 0x03F, 0x00051CF1, + 0x033, 0x0000000A, + 0x03F, 0x00051CF4, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000010, + 0x033, 0x00000000, + 0x008, 0x0009C060, + 0x033, 0x00000001, + 0x008, 0x0009C060, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000010, + 0x033, 0x00000000, + 0x008, 0x0009C060, + 0x033, 0x00000001, + 0x008, 0x0009C060, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00000010, + 0x033, 0x00000000, + 0x008, 0x0009C060, + 0x033, 0x00000001, + 0x008, 0x0009C060, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00000010, + 0x033, 0x00000000, + 0x008, 0x0009C060, + 0x033, 0x00000001, + 0x008, 0x0009C060, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000024, + 0x03E, 0x0000003F, + 0x03F, 0x00060FDE, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000024, + 0x03E, 0x0000003F, + 0x03F, 0x00060FDE, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000024, + 0x03E, 0x0000003F, + 0x03F, 0x00060FDE, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000024, + 0x03E, 0x0000003F, + 0x03F, 0x00060FDE, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000025, + 0x03E, 0x00000037, + 0x03F, 0x0007EFCE, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000025, + 0x03E, 0x00000037, + 0x03F, 0x0007EFCE, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000025, + 0x03E, 0x00000037, + 0x03F, 0x0007EFCE, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000025, + 0x03E, 0x00000037, + 0x03F, 0x0007EFCE, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000026, + 0x03E, 0x00000037, + 0x03F, 0x0005EFCE, + 0x0EF, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000026, + 0x03E, 0x00000037, + 0x03F, 0x0005EFCE, + 0x0EF, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000026, + 0x03E, 0x00000037, + 0x03F, 0x0005EFCE, + 0x0EF, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000026, + 0x03E, 0x00000037, + 0x03F, 0x0005EFCE, + 0x0EF, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000004, + 0x03F, 0x00001EC1, + 0x0EE, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000004, + 0x03F, 0x00001EC1, + 0x0EE, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000004, + 0x03F, 0x00001EC1, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000004, + 0x03F, 0x00001EC1, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000005, + 0x03F, 0x00001ECF, + 0x0EE, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000005, + 0x03F, 0x00001ECF, + 0x0EE, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000005, + 0x03F, 0x00001ECF, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000005, + 0x03F, 0x00001ECF, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x80001005, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000006, + 0x03F, 0x00001F9D, + 0x0EE, 0x00000000, + 0x90001004, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000006, + 0x03F, 0x00001F9D, + 0x0EE, 0x00000000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000006, + 0x03F, 0x00001F9D, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000006, + 0x03F, 0x00001F9D, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + +}; + +void +odm_read_and_config_mp_8821c_radioa(struct dm_struct *dm) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8821c_radioa) / sizeof(u32); + u32 *array = array_mp_8821c_radioa; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped ? false : true; + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); + } + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; + } else { + is_matched = false; + is_skipped = false; + } + } else + is_matched = false; + } + } else { + if (is_matched) + odm_config_rf_radio_a_8821c(dm, v1, v2); + } + i = i + 2; + } +} + +u32 +odm_get_version_mp_8821c_radioa(void) +{ + return 49; +} + +/****************************************************************************** +* txpowertrack.TXT +******************************************************************************/ + +u8 delta_swingidx_mp_5gb_n_txpwrtrk_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}, +}; +u8 delta_swingidx_mp_5gb_p_txpwrtrk_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, +}; +u8 delta_swingidx_mp_5ga_n_txpwrtrk_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}, +}; +u8 delta_swingidx_mp_5ga_p_txpwrtrk_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, +}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_8821c[] = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_8821c[] = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9}; + +void +odm_read_and_config_mp_8821c_txpowertrack(struct dm_struct *dm) +{ + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8821c\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_8821c, DELTA_SWINGIDX_SIZE * 3); +} + +/****************************************************************************** +* txpowertrack_type0x20.TXT +******************************************************************************/ + +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type0x20_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}, +}; +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type0x20_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, +}; +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type0x20_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 0, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12}, + {0, 0, 1, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, +}; +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type0x20_8821c[][DELTA_SWINGIDX_SIZE] = { + {1, 1, 2, 2, 2, 3, 3, 4, 5, 5, 5, 6, 6, 7, 8, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 2, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, +}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type0x20_8821c[] = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type0x20_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type0x20_8821c[] = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type0x20_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type0x20_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type0x20_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type0x20_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type0x20_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9}; + +void +odm_read_and_config_mp_8821c_txpowertrack_type0x20(struct dm_struct *dm) +{ + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8821c\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type0x20_8821c, DELTA_SWINGIDX_SIZE * 3); +} + +/****************************************************************************** +* txpowertrack_type0x28.TXT +******************************************************************************/ + +u8 delta_swingidx_mp_5gb_n_txpwrtrk_type0x28_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}, +}; +u8 delta_swingidx_mp_5gb_p_txpwrtrk_type0x28_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, +}; +u8 delta_swingidx_mp_5ga_n_txpwrtrk_type0x28_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 3, 3, 4, 5, 5, 6, 7, 8, 8, 9, 10, 10, 11, 12, 12, 12, 14, 15, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 4, 4, 5, 7, 7, 8, 8, 9, 10, 10, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 4, 6, 6, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 14, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18}, +}; +u8 delta_swingidx_mp_5ga_p_txpwrtrk_type0x28_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 3, 4, 5, 7, 7, 8, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17}, + {0, 1, 2, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 10, 11, 13, 13, 14, 15, 15, 16, 16, 17, 17, 17, 17, 17, 17, 17, 17}, + {0, 1, 2, 2, 3, 4, 4, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 12, 13, 14, 14, 14, 14, 15, 16, 16, 16, 16, 16, 16}, +}; +u8 delta_swingidx_mp_2gb_n_txpwrtrk_type0x28_8821c[] = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9}; +u8 delta_swingidx_mp_2gb_p_txpwrtrk_type0x28_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9}; +u8 delta_swingidx_mp_2ga_n_txpwrtrk_type0x28_8821c[] = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9}; +u8 delta_swingidx_mp_2ga_p_txpwrtrk_type0x28_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type0x28_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type0x28_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type0x28_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9}; +u8 delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type0x28_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9}; + +void +odm_read_and_config_mp_8821c_txpowertrack_type0x28(struct dm_struct *dm) +{ + struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8821c\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, delta_swingidx_mp_2ga_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, delta_swingidx_mp_2ga_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, delta_swingidx_mp_2gb_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, delta_swingidx_mp_2gb_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, delta_swingidx_mp_2g_cck_a_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, delta_swingidx_mp_2g_cck_a_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, delta_swingidx_mp_2g_cck_b_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, delta_swingidx_mp_2g_cck_b_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, delta_swingidx_mp_5ga_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, delta_swingidx_mp_5ga_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, delta_swingidx_mp_5gb_p_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, delta_swingidx_mp_5gb_n_txpwrtrk_type0x28_8821c, DELTA_SWINGIDX_SIZE * 3); +} + +/****************************************************************************** +* txpwr_lmt.TXT +******************************************************************************/ + +const char *array_mp_8821c_txpwr_lmt[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "34", + "IC", "2.4G", "20M", "CCK", "1T", "01", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "01", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "01", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "01", "30", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "34", + "IC", "2.4G", "20M", "CCK", "1T", "02", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "02", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "02", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "34", + "IC", "2.4G", "20M", "CCK", "1T", "03", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "03", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "03", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "34", + "IC", "2.4G", "20M", "CCK", "1T", "04", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "04", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "04", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "34", + "IC", "2.4G", "20M", "CCK", "1T", "05", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "05", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "05", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "34", + "IC", "2.4G", "20M", "CCK", "1T", "06", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "06", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "06", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "34", + "IC", "2.4G", "20M", "CCK", "1T", "07", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "07", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "07", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "34", + "IC", "2.4G", "20M", "CCK", "1T", "08", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "08", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "08", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "34", + "IC", "2.4G", "20M", "CCK", "1T", "09", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "09", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "09", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "34", + "IC", "2.4G", "20M", "CCK", "1T", "10", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "10", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "10", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "34", + "IC", "2.4G", "20M", "CCK", "1T", "11", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "11", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "11", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "24", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "34", + "IC", "2.4G", "20M", "CCK", "1T", "12", "24", + "KCC", "2.4G", "20M", "CCK", "1T", "12", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "12", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "12", "24", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "16", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "34", + "IC", "2.4G", "20M", "CCK", "1T", "13", "16", + "KCC", "2.4G", "20M", "CCK", "1T", "13", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "13", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "13", "16", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "34", + "IC", "2.4G", "20M", "CCK", "1T", "14", "63", + "KCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ACMA", "2.4G", "20M", "CCK", "1T", "14", "63", + "CHILE", "2.4G", "20M", "CCK", "1T", "14", "63", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "KCC", "2.4G", "20M", "OFDM", "1T", "01", "32", + "ACMA", "2.4G", "20M", "OFDM", "1T", "01", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "01", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "02", "32", + "KCC", "2.4G", "20M", "OFDM", "1T", "02", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "02", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "02", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "03", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "03", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "03", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "04", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "05", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "06", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "07", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "08", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "09", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "09", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "09", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "10", "32", + "KCC", "2.4G", "20M", "OFDM", "1T", "10", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "10", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "10", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "11", "30", + "KCC", "2.4G", "20M", "OFDM", "1T", "11", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "11", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "11", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "12", "28", + "KCC", "2.4G", "20M", "OFDM", "1T", "12", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "12", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "12", "28", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "16", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "13", "16", + "KCC", "2.4G", "20M", "OFDM", "1T", "13", "32", + "ACMA", "2.4G", "20M", "OFDM", "1T", "13", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "13", "16", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "IC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "KCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ACMA", "2.4G", "20M", "OFDM", "1T", "14", "63", + "CHILE", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "IC", "2.4G", "20M", "HT", "1T", "01", "26", + "KCC", "2.4G", "20M", "HT", "1T", "01", "32", + "ACMA", "2.4G", "20M", "HT", "1T", "01", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "01", "26", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "IC", "2.4G", "20M", "HT", "1T", "02", "30", + "KCC", "2.4G", "20M", "HT", "1T", "02", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "02", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "02", "30", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "IC", "2.4G", "20M", "HT", "1T", "03", "32", + "KCC", "2.4G", "20M", "HT", "1T", "03", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "03", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "03", "32", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "IC", "2.4G", "20M", "HT", "1T", "04", "34", + "KCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "04", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "IC", "2.4G", "20M", "HT", "1T", "05", "34", + "KCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "05", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "IC", "2.4G", "20M", "HT", "1T", "06", "34", + "KCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "06", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "IC", "2.4G", "20M", "HT", "1T", "07", "34", + "KCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "07", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "IC", "2.4G", "20M", "HT", "1T", "08", "34", + "KCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "08", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "IC", "2.4G", "20M", "HT", "1T", "09", "32", + "KCC", "2.4G", "20M", "HT", "1T", "09", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "09", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "09", "32", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "IC", "2.4G", "20M", "HT", "1T", "10", "30", + "KCC", "2.4G", "20M", "HT", "1T", "10", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "10", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "10", "30", + "FCC", "2.4G", "20M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "IC", "2.4G", "20M", "HT", "1T", "11", "28", + "KCC", "2.4G", "20M", "HT", "1T", "11", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "11", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "11", "28", + "FCC", "2.4G", "20M", "HT", "1T", "12", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "IC", "2.4G", "20M", "HT", "1T", "12", "26", + "KCC", "2.4G", "20M", "HT", "1T", "12", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "12", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "12", "26", + "FCC", "2.4G", "20M", "HT", "1T", "13", "12", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "IC", "2.4G", "20M", "HT", "1T", "13", "12", + "KCC", "2.4G", "20M", "HT", "1T", "13", "32", + "ACMA", "2.4G", "20M", "HT", "1T", "13", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "13", "12", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "IC", "2.4G", "20M", "HT", "1T", "14", "63", + "KCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ACMA", "2.4G", "20M", "HT", "1T", "14", "63", + "CHILE", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "IC", "2.4G", "40M", "HT", "1T", "01", "63", + "KCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "01", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "IC", "2.4G", "40M", "HT", "1T", "02", "63", + "KCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "02", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "30", + "IC", "2.4G", "40M", "HT", "1T", "03", "26", + "KCC", "2.4G", "40M", "HT", "1T", "03", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "03", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "03", "26", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "30", + "IC", "2.4G", "40M", "HT", "1T", "04", "26", + "KCC", "2.4G", "40M", "HT", "1T", "04", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "04", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "04", "26", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "30", + "IC", "2.4G", "40M", "HT", "1T", "05", "30", + "KCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "05", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "05", "30", + "FCC", "2.4G", "40M", "HT", "1T", "06", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "30", + "IC", "2.4G", "40M", "HT", "1T", "06", "30", + "KCC", "2.4G", "40M", "HT", "1T", "06", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "06", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "06", "30", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "30", + "IC", "2.4G", "40M", "HT", "1T", "07", "30", + "KCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "07", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "07", "30", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "30", + "IC", "2.4G", "40M", "HT", "1T", "08", "26", + "KCC", "2.4G", "40M", "HT", "1T", "08", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "08", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "08", "26", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "30", + "IC", "2.4G", "40M", "HT", "1T", "09", "26", + "KCC", "2.4G", "40M", "HT", "1T", "09", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "09", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "09", "26", + "FCC", "2.4G", "40M", "HT", "1T", "10", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "30", + "IC", "2.4G", "40M", "HT", "1T", "10", "28", + "KCC", "2.4G", "40M", "HT", "1T", "10", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "10", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "10", "28", + "FCC", "2.4G", "40M", "HT", "1T", "11", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "30", + "IC", "2.4G", "40M", "HT", "1T", "11", "20", + "KCC", "2.4G", "40M", "HT", "1T", "11", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "11", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "11", "20", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "IC", "2.4G", "40M", "HT", "1T", "12", "63", + "KCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "12", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "IC", "2.4G", "40M", "HT", "1T", "13", "63", + "KCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "13", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "IC", "2.4G", "40M", "HT", "1T", "14", "63", + "KCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "14", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "31", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "33", + "IC", "5G", "20M", "OFDM", "1T", "36", "31", + "KCC", "5G", "20M", "OFDM", "1T", "36", "29", + "ACMA", "5G", "20M", "OFDM", "1T", "36", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "36", "29", + "FCC", "5G", "20M", "OFDM", "1T", "40", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "33", + "IC", "5G", "20M", "OFDM", "1T", "40", "31", + "KCC", "5G", "20M", "OFDM", "1T", "40", "28", + "ACMA", "5G", "20M", "OFDM", "1T", "40", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "40", "29", + "FCC", "5G", "20M", "OFDM", "1T", "44", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "33", + "IC", "5G", "20M", "OFDM", "1T", "44", "31", + "KCC", "5G", "20M", "OFDM", "1T", "44", "28", + "ACMA", "5G", "20M", "OFDM", "1T", "44", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "44", "30", + "FCC", "5G", "20M", "OFDM", "1T", "48", "31", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "33", + "IC", "5G", "20M", "OFDM", "1T", "48", "31", + "KCC", "5G", "20M", "OFDM", "1T", "48", "27", + "ACMA", "5G", "20M", "OFDM", "1T", "48", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "48", "30", + "FCC", "5G", "20M", "OFDM", "1T", "52", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "33", + "IC", "5G", "20M", "OFDM", "1T", "52", "32", + "KCC", "5G", "20M", "OFDM", "1T", "52", "16", + "ACMA", "5G", "20M", "OFDM", "1T", "52", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "52", "30", + "FCC", "5G", "20M", "OFDM", "1T", "56", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "33", + "IC", "5G", "20M", "OFDM", "1T", "56", "32", + "KCC", "5G", "20M", "OFDM", "1T", "56", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "56", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "56", "30", + "FCC", "5G", "20M", "OFDM", "1T", "60", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "33", + "IC", "5G", "20M", "OFDM", "1T", "60", "32", + "KCC", "5G", "20M", "OFDM", "1T", "60", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "60", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "60", "30", + "FCC", "5G", "20M", "OFDM", "1T", "64", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "33", + "IC", "5G", "20M", "OFDM", "1T", "64", "30", + "KCC", "5G", "20M", "OFDM", "1T", "64", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "64", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "64", "29", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "33", + "IC", "5G", "20M", "OFDM", "1T", "100", "30", + "KCC", "5G", "20M", "OFDM", "1T", "100", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "100", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "100", "30", + "FCC", "5G", "20M", "OFDM", "1T", "104", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "33", + "IC", "5G", "20M", "OFDM", "1T", "104", "33", + "KCC", "5G", "20M", "OFDM", "1T", "104", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "104", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "104", "30", + "FCC", "5G", "20M", "OFDM", "1T", "108", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "33", + "IC", "5G", "20M", "OFDM", "1T", "108", "33", + "KCC", "5G", "20M", "OFDM", "1T", "108", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "108", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "108", "30", + "FCC", "5G", "20M", "OFDM", "1T", "112", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "33", + "IC", "5G", "20M", "OFDM", "1T", "112", "33", + "KCC", "5G", "20M", "OFDM", "1T", "112", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "112", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "112", "30", + "FCC", "5G", "20M", "OFDM", "1T", "116", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "33", + "IC", "5G", "20M", "OFDM", "1T", "116", "33", + "KCC", "5G", "20M", "OFDM", "1T", "116", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "116", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "116", "30", + "FCC", "5G", "20M", "OFDM", "1T", "120", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "33", + "IC", "5G", "20M", "OFDM", "1T", "120", "63", + "KCC", "5G", "20M", "OFDM", "1T", "120", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "120", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "120", "30", + "FCC", "5G", "20M", "OFDM", "1T", "124", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "33", + "IC", "5G", "20M", "OFDM", "1T", "124", "63", + "KCC", "5G", "20M", "OFDM", "1T", "124", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "124", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "124", "30", + "FCC", "5G", "20M", "OFDM", "1T", "128", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "33", + "IC", "5G", "20M", "OFDM", "1T", "128", "63", + "KCC", "5G", "20M", "OFDM", "1T", "128", "63", + "ACMA", "5G", "20M", "OFDM", "1T", "128", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "128", "30", + "FCC", "5G", "20M", "OFDM", "1T", "132", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "33", + "IC", "5G", "20M", "OFDM", "1T", "132", "33", + "KCC", "5G", "20M", "OFDM", "1T", "132", "63", + "ACMA", "5G", "20M", "OFDM", "1T", "132", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "132", "30", + "FCC", "5G", "20M", "OFDM", "1T", "136", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "33", + "IC", "5G", "20M", "OFDM", "1T", "136", "33", + "KCC", "5G", "20M", "OFDM", "1T", "136", "63", + "ACMA", "5G", "20M", "OFDM", "1T", "136", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "136", "30", + "FCC", "5G", "20M", "OFDM", "1T", "140", "31", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "33", + "IC", "5G", "20M", "OFDM", "1T", "140", "31", + "KCC", "5G", "20M", "OFDM", "1T", "140", "63", + "ACMA", "5G", "20M", "OFDM", "1T", "140", "32", + "CHILE", "5G", "20M", "OFDM", "1T", "140", "30", + "FCC", "5G", "20M", "OFDM", "1T", "144", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "63", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "IC", "5G", "20M", "OFDM", "1T", "144", "30", + "KCC", "5G", "20M", "OFDM", "1T", "144", "63", + "ACMA", "5G", "20M", "OFDM", "1T", "144", "63", + "CHILE", "5G", "20M", "OFDM", "1T", "144", "30", + "FCC", "5G", "20M", "OFDM", "1T", "149", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "IC", "5G", "20M", "OFDM", "1T", "149", "30", + "KCC", "5G", "20M", "OFDM", "1T", "149", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "149", "33", + "CHILE", "5G", "20M", "OFDM", "1T", "149", "30", + "FCC", "5G", "20M", "OFDM", "1T", "153", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "IC", "5G", "20M", "OFDM", "1T", "153", "33", + "KCC", "5G", "20M", "OFDM", "1T", "153", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "153", "33", + "CHILE", "5G", "20M", "OFDM", "1T", "153", "30", + "FCC", "5G", "20M", "OFDM", "1T", "157", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "IC", "5G", "20M", "OFDM", "1T", "157", "33", + "KCC", "5G", "20M", "OFDM", "1T", "157", "33", + "ACMA", "5G", "20M", "OFDM", "1T", "157", "33", + "CHILE", "5G", "20M", "OFDM", "1T", "157", "30", + "FCC", "5G", "20M", "OFDM", "1T", "161", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "IC", "5G", "20M", "OFDM", "1T", "161", "33", + "KCC", "5G", "20M", "OFDM", "1T", "161", "31", + "ACMA", "5G", "20M", "OFDM", "1T", "161", "33", + "CHILE", "5G", "20M", "OFDM", "1T", "161", "30", + "FCC", "5G", "20M", "OFDM", "1T", "165", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "IC", "5G", "20M", "OFDM", "1T", "165", "33", + "KCC", "5G", "20M", "OFDM", "1T", "165", "63", + "ACMA", "5G", "20M", "OFDM", "1T", "165", "33", + "CHILE", "5G", "20M", "OFDM", "1T", "165", "30", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "33", + "IC", "5G", "20M", "HT", "1T", "36", "30", + "KCC", "5G", "20M", "HT", "1T", "36", "27", + "ACMA", "5G", "20M", "HT", "1T", "36", "32", + "CHILE", "5G", "20M", "HT", "1T", "36", "30", + "FCC", "5G", "20M", "HT", "1T", "40", "33", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "33", + "IC", "5G", "20M", "HT", "1T", "40", "31", + "KCC", "5G", "20M", "HT", "1T", "40", "29", + "ACMA", "5G", "20M", "HT", "1T", "40", "32", + "CHILE", "5G", "20M", "HT", "1T", "40", "30", + "FCC", "5G", "20M", "HT", "1T", "44", "33", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "33", + "IC", "5G", "20M", "HT", "1T", "44", "31", + "KCC", "5G", "20M", "HT", "1T", "44", "29", + "ACMA", "5G", "20M", "HT", "1T", "44", "32", + "CHILE", "5G", "20M", "HT", "1T", "44", "30", + "FCC", "5G", "20M", "HT", "1T", "48", "33", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "33", + "IC", "5G", "20M", "HT", "1T", "48", "31", + "KCC", "5G", "20M", "HT", "1T", "48", "26", + "ACMA", "5G", "20M", "HT", "1T", "48", "32", + "CHILE", "5G", "20M", "HT", "1T", "48", "30", + "FCC", "5G", "20M", "HT", "1T", "52", "33", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "33", + "IC", "5G", "20M", "HT", "1T", "52", "32", + "KCC", "5G", "20M", "HT", "1T", "52", "7", + "ACMA", "5G", "20M", "HT", "1T", "52", "32", + "CHILE", "5G", "20M", "HT", "1T", "52", "30", + "FCC", "5G", "20M", "HT", "1T", "56", "33", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "33", + "IC", "5G", "20M", "HT", "1T", "56", "32", + "KCC", "5G", "20M", "HT", "1T", "56", "33", + "ACMA", "5G", "20M", "HT", "1T", "56", "32", + "CHILE", "5G", "20M", "HT", "1T", "56", "30", + "FCC", "5G", "20M", "HT", "1T", "60", "33", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "33", + "IC", "5G", "20M", "HT", "1T", "60", "32", + "KCC", "5G", "20M", "HT", "1T", "60", "33", + "ACMA", "5G", "20M", "HT", "1T", "60", "32", + "CHILE", "5G", "20M", "HT", "1T", "60", "30", + "FCC", "5G", "20M", "HT", "1T", "64", "30", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "33", + "IC", "5G", "20M", "HT", "1T", "64", "30", + "KCC", "5G", "20M", "HT", "1T", "64", "33", + "ACMA", "5G", "20M", "HT", "1T", "64", "32", + "CHILE", "5G", "20M", "HT", "1T", "64", "30", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "33", + "IC", "5G", "20M", "HT", "1T", "100", "30", + "KCC", "5G", "20M", "HT", "1T", "100", "33", + "ACMA", "5G", "20M", "HT", "1T", "100", "32", + "CHILE", "5G", "20M", "HT", "1T", "100", "30", + "FCC", "5G", "20M", "HT", "1T", "104", "33", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "33", + "IC", "5G", "20M", "HT", "1T", "104", "33", + "KCC", "5G", "20M", "HT", "1T", "104", "33", + "ACMA", "5G", "20M", "HT", "1T", "104", "32", + "CHILE", "5G", "20M", "HT", "1T", "104", "30", + "FCC", "5G", "20M", "HT", "1T", "108", "33", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "33", + "IC", "5G", "20M", "HT", "1T", "108", "33", + "KCC", "5G", "20M", "HT", "1T", "108", "33", + "ACMA", "5G", "20M", "HT", "1T", "108", "32", + "CHILE", "5G", "20M", "HT", "1T", "108", "30", + "FCC", "5G", "20M", "HT", "1T", "112", "33", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "33", + "IC", "5G", "20M", "HT", "1T", "112", "33", + "KCC", "5G", "20M", "HT", "1T", "112", "33", + "ACMA", "5G", "20M", "HT", "1T", "112", "32", + "CHILE", "5G", "20M", "HT", "1T", "112", "30", + "FCC", "5G", "20M", "HT", "1T", "116", "33", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "33", + "IC", "5G", "20M", "HT", "1T", "116", "33", + "KCC", "5G", "20M", "HT", "1T", "116", "33", + "ACMA", "5G", "20M", "HT", "1T", "116", "32", + "CHILE", "5G", "20M", "HT", "1T", "116", "30", + "FCC", "5G", "20M", "HT", "1T", "120", "33", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "33", + "IC", "5G", "20M", "HT", "1T", "120", "63", + "KCC", "5G", "20M", "HT", "1T", "120", "33", + "ACMA", "5G", "20M", "HT", "1T", "120", "32", + "CHILE", "5G", "20M", "HT", "1T", "120", "30", + "FCC", "5G", "20M", "HT", "1T", "124", "33", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "33", + "IC", "5G", "20M", "HT", "1T", "124", "63", + "KCC", "5G", "20M", "HT", "1T", "124", "33", + "ACMA", "5G", "20M", "HT", "1T", "124", "32", + "CHILE", "5G", "20M", "HT", "1T", "124", "30", + "FCC", "5G", "20M", "HT", "1T", "128", "33", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "33", + "IC", "5G", "20M", "HT", "1T", "128", "63", + "KCC", "5G", "20M", "HT", "1T", "128", "63", + "ACMA", "5G", "20M", "HT", "1T", "128", "32", + "CHILE", "5G", "20M", "HT", "1T", "128", "30", + "FCC", "5G", "20M", "HT", "1T", "132", "33", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "33", + "IC", "5G", "20M", "HT", "1T", "132", "33", + "KCC", "5G", "20M", "HT", "1T", "132", "63", + "ACMA", "5G", "20M", "HT", "1T", "132", "32", + "CHILE", "5G", "20M", "HT", "1T", "132", "30", + "FCC", "5G", "20M", "HT", "1T", "136", "33", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "33", + "IC", "5G", "20M", "HT", "1T", "136", "33", + "KCC", "5G", "20M", "HT", "1T", "136", "63", + "ACMA", "5G", "20M", "HT", "1T", "136", "32", + "CHILE", "5G", "20M", "HT", "1T", "136", "30", + "FCC", "5G", "20M", "HT", "1T", "140", "29", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "33", + "IC", "5G", "20M", "HT", "1T", "140", "29", + "KCC", "5G", "20M", "HT", "1T", "140", "63", + "ACMA", "5G", "20M", "HT", "1T", "140", "32", + "CHILE", "5G", "20M", "HT", "1T", "140", "30", + "FCC", "5G", "20M", "HT", "1T", "144", "27", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "IC", "5G", "20M", "HT", "1T", "144", "27", + "KCC", "5G", "20M", "HT", "1T", "144", "63", + "ACMA", "5G", "20M", "HT", "1T", "144", "63", + "CHILE", "5G", "20M", "HT", "1T", "144", "30", + "FCC", "5G", "20M", "HT", "1T", "149", "33", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "IC", "5G", "20M", "HT", "1T", "149", "33", + "KCC", "5G", "20M", "HT", "1T", "149", "33", + "ACMA", "5G", "20M", "HT", "1T", "149", "33", + "CHILE", "5G", "20M", "HT", "1T", "149", "30", + "FCC", "5G", "20M", "HT", "1T", "153", "33", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "IC", "5G", "20M", "HT", "1T", "153", "33", + "KCC", "5G", "20M", "HT", "1T", "153", "33", + "ACMA", "5G", "20M", "HT", "1T", "153", "33", + "CHILE", "5G", "20M", "HT", "1T", "153", "30", + "FCC", "5G", "20M", "HT", "1T", "157", "33", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "IC", "5G", "20M", "HT", "1T", "157", "33", + "KCC", "5G", "20M", "HT", "1T", "157", "33", + "ACMA", "5G", "20M", "HT", "1T", "157", "33", + "CHILE", "5G", "20M", "HT", "1T", "157", "30", + "FCC", "5G", "20M", "HT", "1T", "161", "33", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "IC", "5G", "20M", "HT", "1T", "161", "33", + "KCC", "5G", "20M", "HT", "1T", "161", "31", + "ACMA", "5G", "20M", "HT", "1T", "161", "33", + "CHILE", "5G", "20M", "HT", "1T", "161", "30", + "FCC", "5G", "20M", "HT", "1T", "165", "33", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "IC", "5G", "20M", "HT", "1T", "165", "33", + "KCC", "5G", "20M", "HT", "1T", "165", "63", + "ACMA", "5G", "20M", "HT", "1T", "165", "33", + "CHILE", "5G", "20M", "HT", "1T", "165", "30", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "IC", "5G", "40M", "HT", "1T", "38", "22", + "KCC", "5G", "40M", "HT", "1T", "38", "26", + "ACMA", "5G", "40M", "HT", "1T", "38", "32", + "CHILE", "5G", "40M", "HT", "1T", "38", "22", + "FCC", "5G", "40M", "HT", "1T", "46", "32", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "IC", "5G", "40M", "HT", "1T", "46", "32", + "KCC", "5G", "40M", "HT", "1T", "46", "28", + "ACMA", "5G", "40M", "HT", "1T", "46", "32", + "CHILE", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "IC", "5G", "40M", "HT", "1T", "54", "32", + "KCC", "5G", "40M", "HT", "1T", "54", "22", + "ACMA", "5G", "40M", "HT", "1T", "54", "32", + "CHILE", "5G", "40M", "HT", "1T", "54", "30", + "FCC", "5G", "40M", "HT", "1T", "62", "23", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "IC", "5G", "40M", "HT", "1T", "62", "23", + "KCC", "5G", "40M", "HT", "1T", "62", "31", + "ACMA", "5G", "40M", "HT", "1T", "62", "32", + "CHILE", "5G", "40M", "HT", "1T", "62", "23", + "FCC", "5G", "40M", "HT", "1T", "102", "21", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "IC", "5G", "40M", "HT", "1T", "102", "21", + "KCC", "5G", "40M", "HT", "1T", "102", "31", + "ACMA", "5G", "40M", "HT", "1T", "102", "32", + "CHILE", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "IC", "5G", "40M", "HT", "1T", "110", "32", + "KCC", "5G", "40M", "HT", "1T", "110", "32", + "ACMA", "5G", "40M", "HT", "1T", "110", "32", + "CHILE", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "32", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "IC", "5G", "40M", "HT", "1T", "118", "63", + "KCC", "5G", "40M", "HT", "1T", "118", "32", + "ACMA", "5G", "40M", "HT", "1T", "118", "32", + "CHILE", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "32", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "IC", "5G", "40M", "HT", "1T", "126", "63", + "KCC", "5G", "40M", "HT", "1T", "126", "63", + "ACMA", "5G", "40M", "HT", "1T", "126", "32", + "CHILE", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "IC", "5G", "40M", "HT", "1T", "134", "32", + "KCC", "5G", "40M", "HT", "1T", "134", "63", + "ACMA", "5G", "40M", "HT", "1T", "134", "32", + "CHILE", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "29", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "IC", "5G", "40M", "HT", "1T", "142", "29", + "KCC", "5G", "40M", "HT", "1T", "142", "63", + "ACMA", "5G", "40M", "HT", "1T", "142", "63", + "CHILE", "5G", "40M", "HT", "1T", "142", "30", + "FCC", "5G", "40M", "HT", "1T", "151", "32", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "IC", "5G", "40M", "HT", "1T", "151", "32", + "KCC", "5G", "40M", "HT", "1T", "151", "27", + "ACMA", "5G", "40M", "HT", "1T", "151", "32", + "CHILE", "5G", "40M", "HT", "1T", "151", "30", + "FCC", "5G", "40M", "HT", "1T", "159", "32", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "IC", "5G", "40M", "HT", "1T", "159", "32", + "KCC", "5G", "40M", "HT", "1T", "159", "26", + "ACMA", "5G", "40M", "HT", "1T", "159", "32", + "CHILE", "5G", "40M", "HT", "1T", "159", "30", + "FCC", "5G", "80M", "VHT", "1T", "42", "19", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "IC", "5G", "80M", "VHT", "1T", "42", "19", + "KCC", "5G", "80M", "VHT", "1T", "42", "25", + "ACMA", "5G", "80M", "VHT", "1T", "42", "32", + "CHILE", "5G", "80M", "VHT", "1T", "42", "19", + "FCC", "5G", "80M", "VHT", "1T", "58", "22", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "IC", "5G", "80M", "VHT", "1T", "58", "22", + "KCC", "5G", "80M", "VHT", "1T", "58", "28", + "ACMA", "5G", "80M", "VHT", "1T", "58", "32", + "CHILE", "5G", "80M", "VHT", "1T", "58", "22", + "FCC", "5G", "80M", "VHT", "1T", "106", "18", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "IC", "5G", "80M", "VHT", "1T", "106", "18", + "KCC", "5G", "80M", "VHT", "1T", "106", "30", + "ACMA", "5G", "80M", "VHT", "1T", "106", "32", + "CHILE", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "32", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "IC", "5G", "80M", "VHT", "1T", "122", "63", + "KCC", "5G", "80M", "VHT", "1T", "122", "26", + "ACMA", "5G", "80M", "VHT", "1T", "122", "32", + "CHILE", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "28", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "IC", "5G", "80M", "VHT", "1T", "138", "28", + "KCC", "5G", "80M", "VHT", "1T", "138", "63", + "ACMA", "5G", "80M", "VHT", "1T", "138", "63", + "CHILE", "5G", "80M", "VHT", "1T", "138", "30", + "FCC", "5G", "80M", "VHT", "1T", "155", "32", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "IC", "5G", "80M", "VHT", "1T", "155", "32", + "KCC", "5G", "80M", "VHT", "1T", "155", "27", + "ACMA", "5G", "80M", "VHT", "1T", "155", "32", + "CHILE", "5G", "80M", "VHT", "1T", "155", "30" }; void -odm_read_and_config_mp_8821c_radioa( - struct PHY_DM_STRUCT *p_dm_odm -) +odm_read_and_config_mp_8821c_txpwr_lmt(struct dm_struct *dm) { u32 i = 0; - u8 c_cond; - boolean is_matched = true, is_skipped = false; - u32 array_len = sizeof(array_mp_8821c_radioa)/sizeof(u32); - u32 *array = array_mp_8821c_radioa; - - u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; - - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_radioa\n")); - - while ((i + 1) < array_len) { - v1 = array[i]; - v2 = array[i + 1]; - - if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ - if (v1 & BIT(31)) {/* positive condition*/ - c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); - if (c_cond == COND_ENDIF) {/*end*/ - is_matched = true; - is_skipped = false; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); - } else if (c_cond == COND_ELSE) { /*else*/ - is_matched = is_skipped?false:true; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); - } else {/*if , else if*/ - pre_v1 = v1; - pre_v2 = v2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); - } - } else if (v1 & BIT(30)) { /*negative condition*/ - if (is_skipped == false) { - if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { - is_matched = true; - is_skipped = true; - } else { - is_matched = false; - is_skipped = false; - } - } else - is_matched = false; - } - } else { - if (is_matched) - odm_config_rf_radio_a_8821c(p_dm_odm, v1, v2); - } - i = i + 2; - } -} - -u32 -odm_get_version_mp_8821c_radioa(void) -{ - return 36; -} - -/****************************************************************************** -* txpowertrack.TXT -******************************************************************************/ - -u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_8821c[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12}, - {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, - {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}, -}; -u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_8821c[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, -}; -u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_8821c[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12}, - {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, - {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}, -}; -u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_8821c[][DELTA_SWINGIDX_SIZE] = { - {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, - {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}, - {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, -}; -u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_8821c[] = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9}; -u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9}; -u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_8821c[] = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9}; -u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9}; -u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9}; -u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9}; - -void -odm_read_and_config_mp_8821c_txpowertrack( - struct PHY_DM_STRUCT *p_dm_odm -) -{ - struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8821c_txpwr_lmt) / sizeof(u8); + u8 *array = (u8 *)array_mp_8821c_txpwr_lmt; +#else + u32 array_len = sizeof(array_mp_8821c_txpwr_lmt) / sizeof(u8 *); + u8 **array = (u8 **)array_mp_8821c_txpwr_lmt; +#endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8821c\n")); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len / 7; +#endif - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i + 1]; + u8 bandwidth = array[i + 2]; + u8 rate = array[i + 3]; + u8 rf_path = array[i + 4]; + u8 chnl = array[i + 5]; + u8 val = array[i + 6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i + 1]; + u8 *bandwidth = array[i + 2]; + u8 *rate = array[i + 3]; + u8 *rf_path = array[i + 4]; + u8 *chnl = array[i + 5]; + u8 *val = array[i + 6]; +#endif - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE*3); - odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE*3); + odm_config_bb_txpwr_lmt_8821c(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i / 7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } } /****************************************************************************** -* txpwr_lmt.TXT +* txpwr_lmt_fccsar.TXT ******************************************************************************/ -const char *array_mp_8821c_txpwr_lmt[] = { +const char *array_mp_8821c_txpwr_lmt_fccsar[] = { "FCC", "2.4G", "20M", "CCK", "1T", "01", "30", "ETSI", "2.4G", "20M", "CCK", "1T", "01", "30", "MKK", "2.4G", "20M", "CCK", "1T", "01", "34", + "IC", "2.4G", "20M", "CCK", "1T", "01", "30", + "KCC", "2.4G", "20M", "CCK", "1T", "01", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "01", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "01", "30", "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "02", "30", "MKK", "2.4G", "20M", "CCK", "1T", "02", "34", + "IC", "2.4G", "20M", "CCK", "1T", "02", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "02", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "02", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "02", "32", "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "03", "30", "MKK", "2.4G", "20M", "CCK", "1T", "03", "34", + "IC", "2.4G", "20M", "CCK", "1T", "03", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "03", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "03", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "03", "32", "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "04", "30", "MKK", "2.4G", "20M", "CCK", "1T", "04", "34", + "IC", "2.4G", "20M", "CCK", "1T", "04", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "04", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "04", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "04", "32", "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "05", "30", "MKK", "2.4G", "20M", "CCK", "1T", "05", "34", + "IC", "2.4G", "20M", "CCK", "1T", "05", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "05", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "05", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "05", "32", "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "06", "30", "MKK", "2.4G", "20M", "CCK", "1T", "06", "34", + "IC", "2.4G", "20M", "CCK", "1T", "06", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "06", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "06", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "06", "32", "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "07", "30", "MKK", "2.4G", "20M", "CCK", "1T", "07", "34", + "IC", "2.4G", "20M", "CCK", "1T", "07", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "07", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "07", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "07", "32", "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "08", "30", "MKK", "2.4G", "20M", "CCK", "1T", "08", "34", + "IC", "2.4G", "20M", "CCK", "1T", "08", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "08", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "08", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "08", "32", "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "09", "30", "MKK", "2.4G", "20M", "CCK", "1T", "09", "34", + "IC", "2.4G", "20M", "CCK", "1T", "09", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "09", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "09", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "09", "32", "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "10", "30", "MKK", "2.4G", "20M", "CCK", "1T", "10", "34", + "IC", "2.4G", "20M", "CCK", "1T", "10", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "10", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "10", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "10", "32", "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "11", "30", "MKK", "2.4G", "20M", "CCK", "1T", "11", "34", + "IC", "2.4G", "20M", "CCK", "1T", "11", "32", + "KCC", "2.4G", "20M", "CCK", "1T", "11", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "11", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "11", "32", "FCC", "2.4G", "20M", "CCK", "1T", "12", "24", "ETSI", "2.4G", "20M", "CCK", "1T", "12", "30", "MKK", "2.4G", "20M", "CCK", "1T", "12", "34", + "IC", "2.4G", "20M", "CCK", "1T", "12", "24", + "KCC", "2.4G", "20M", "CCK", "1T", "12", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "12", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "12", "24", "FCC", "2.4G", "20M", "CCK", "1T", "13", "16", "ETSI", "2.4G", "20M", "CCK", "1T", "13", "30", "MKK", "2.4G", "20M", "CCK", "1T", "13", "34", + "IC", "2.4G", "20M", "CCK", "1T", "13", "16", + "KCC", "2.4G", "20M", "CCK", "1T", "13", "34", + "ACMA", "2.4G", "20M", "CCK", "1T", "13", "30", + "CHILE", "2.4G", "20M", "CCK", "1T", "13", "16", "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", "MKK", "2.4G", "20M", "CCK", "1T", "14", "34", + "IC", "2.4G", "20M", "CCK", "1T", "14", "63", + "KCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ACMA", "2.4G", "20M", "CCK", "1T", "14", "63", + "CHILE", "2.4G", "20M", "CCK", "1T", "14", "63", "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "KCC", "2.4G", "20M", "OFDM", "1T", "01", "32", + "ACMA", "2.4G", "20M", "OFDM", "1T", "01", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "01", "30", "FCC", "2.4G", "20M", "OFDM", "1T", "02", "32", "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "02", "32", + "KCC", "2.4G", "20M", "OFDM", "1T", "02", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "02", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "02", "32", "FCC", "2.4G", "20M", "OFDM", "1T", "03", "34", "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "03", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "03", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "03", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "03", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "04", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "04", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "05", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "05", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "06", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "06", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "07", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "07", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "08", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "08", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "09", "34", "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "09", "34", + "KCC", "2.4G", "20M", "OFDM", "1T", "09", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "09", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "09", "34", "FCC", "2.4G", "20M", "OFDM", "1T", "10", "32", "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "10", "32", + "KCC", "2.4G", "20M", "OFDM", "1T", "10", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "10", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "10", "32", "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "11", "30", + "KCC", "2.4G", "20M", "OFDM", "1T", "11", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "11", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "11", "30", "FCC", "2.4G", "20M", "OFDM", "1T", "12", "28", "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "12", "28", + "KCC", "2.4G", "20M", "OFDM", "1T", "12", "34", + "ACMA", "2.4G", "20M", "OFDM", "1T", "12", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "12", "28", "FCC", "2.4G", "20M", "OFDM", "1T", "13", "16", "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "IC", "2.4G", "20M", "OFDM", "1T", "13", "16", + "KCC", "2.4G", "20M", "OFDM", "1T", "13", "32", + "ACMA", "2.4G", "20M", "OFDM", "1T", "13", "30", + "CHILE", "2.4G", "20M", "OFDM", "1T", "13", "16", "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "IC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "KCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ACMA", "2.4G", "20M", "OFDM", "1T", "14", "63", + "CHILE", "2.4G", "20M", "OFDM", "1T", "14", "63", "FCC", "2.4G", "20M", "HT", "1T", "01", "26", "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "IC", "2.4G", "20M", "HT", "1T", "01", "26", + "KCC", "2.4G", "20M", "HT", "1T", "01", "32", + "ACMA", "2.4G", "20M", "HT", "1T", "01", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "01", "26", "FCC", "2.4G", "20M", "HT", "1T", "02", "30", "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "IC", "2.4G", "20M", "HT", "1T", "02", "30", + "KCC", "2.4G", "20M", "HT", "1T", "02", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "02", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "02", "30", "FCC", "2.4G", "20M", "HT", "1T", "03", "32", "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "IC", "2.4G", "20M", "HT", "1T", "03", "32", + "KCC", "2.4G", "20M", "HT", "1T", "03", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "03", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "03", "32", "FCC", "2.4G", "20M", "HT", "1T", "04", "34", "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "IC", "2.4G", "20M", "HT", "1T", "04", "34", + "KCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "04", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "04", "34", "FCC", "2.4G", "20M", "HT", "1T", "05", "34", "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "IC", "2.4G", "20M", "HT", "1T", "05", "34", + "KCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "05", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "05", "34", "FCC", "2.4G", "20M", "HT", "1T", "06", "34", "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "IC", "2.4G", "20M", "HT", "1T", "06", "34", + "KCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "06", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "06", "34", "FCC", "2.4G", "20M", "HT", "1T", "07", "34", "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "IC", "2.4G", "20M", "HT", "1T", "07", "34", + "KCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "07", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "07", "34", "FCC", "2.4G", "20M", "HT", "1T", "08", "34", "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "IC", "2.4G", "20M", "HT", "1T", "08", "34", + "KCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "08", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "08", "34", "FCC", "2.4G", "20M", "HT", "1T", "09", "32", "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "IC", "2.4G", "20M", "HT", "1T", "09", "32", + "KCC", "2.4G", "20M", "HT", "1T", "09", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "09", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "09", "32", "FCC", "2.4G", "20M", "HT", "1T", "10", "30", "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "IC", "2.4G", "20M", "HT", "1T", "10", "30", + "KCC", "2.4G", "20M", "HT", "1T", "10", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "10", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "10", "30", "FCC", "2.4G", "20M", "HT", "1T", "11", "28", "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "IC", "2.4G", "20M", "HT", "1T", "11", "28", + "KCC", "2.4G", "20M", "HT", "1T", "11", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "11", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "11", "28", "FCC", "2.4G", "20M", "HT", "1T", "12", "26", "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "IC", "2.4G", "20M", "HT", "1T", "12", "26", + "KCC", "2.4G", "20M", "HT", "1T", "12", "34", + "ACMA", "2.4G", "20M", "HT", "1T", "12", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "12", "26", "FCC", "2.4G", "20M", "HT", "1T", "13", "12", "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "IC", "2.4G", "20M", "HT", "1T", "13", "12", + "KCC", "2.4G", "20M", "HT", "1T", "13", "32", + "ACMA", "2.4G", "20M", "HT", "1T", "13", "30", + "CHILE", "2.4G", "20M", "HT", "1T", "13", "12", "FCC", "2.4G", "20M", "HT", "1T", "14", "63", "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "IC", "2.4G", "20M", "HT", "1T", "14", "63", + "KCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ACMA", "2.4G", "20M", "HT", "1T", "14", "63", + "CHILE", "2.4G", "20M", "HT", "1T", "14", "63", "FCC", "2.4G", "40M", "HT", "1T", "01", "63", "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "IC", "2.4G", "40M", "HT", "1T", "01", "63", + "KCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "01", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "01", "63", "FCC", "2.4G", "40M", "HT", "1T", "02", "63", "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "IC", "2.4G", "40M", "HT", "1T", "02", "63", + "KCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "02", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "02", "63", "FCC", "2.4G", "40M", "HT", "1T", "03", "26", "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", "MKK", "2.4G", "40M", "HT", "1T", "03", "30", + "IC", "2.4G", "40M", "HT", "1T", "03", "26", + "KCC", "2.4G", "40M", "HT", "1T", "03", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "03", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "03", "26", "FCC", "2.4G", "40M", "HT", "1T", "04", "26", "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", "MKK", "2.4G", "40M", "HT", "1T", "04", "30", + "IC", "2.4G", "40M", "HT", "1T", "04", "26", + "KCC", "2.4G", "40M", "HT", "1T", "04", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "04", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "04", "26", "FCC", "2.4G", "40M", "HT", "1T", "05", "30", "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", "MKK", "2.4G", "40M", "HT", "1T", "05", "30", + "IC", "2.4G", "40M", "HT", "1T", "05", "30", + "KCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "05", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "05", "30", "FCC", "2.4G", "40M", "HT", "1T", "06", "30", "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", "MKK", "2.4G", "40M", "HT", "1T", "06", "30", + "IC", "2.4G", "40M", "HT", "1T", "06", "30", + "KCC", "2.4G", "40M", "HT", "1T", "06", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "06", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "06", "30", "FCC", "2.4G", "40M", "HT", "1T", "07", "30", "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", "MKK", "2.4G", "40M", "HT", "1T", "07", "30", + "IC", "2.4G", "40M", "HT", "1T", "07", "30", + "KCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "07", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "07", "30", "FCC", "2.4G", "40M", "HT", "1T", "08", "26", "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", "MKK", "2.4G", "40M", "HT", "1T", "08", "30", + "IC", "2.4G", "40M", "HT", "1T", "08", "26", + "KCC", "2.4G", "40M", "HT", "1T", "08", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "08", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "08", "26", "FCC", "2.4G", "40M", "HT", "1T", "09", "26", "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", "MKK", "2.4G", "40M", "HT", "1T", "09", "30", + "IC", "2.4G", "40M", "HT", "1T", "09", "26", + "KCC", "2.4G", "40M", "HT", "1T", "09", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "09", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "09", "26", "FCC", "2.4G", "40M", "HT", "1T", "10", "28", "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", "MKK", "2.4G", "40M", "HT", "1T", "10", "30", + "IC", "2.4G", "40M", "HT", "1T", "10", "28", + "KCC", "2.4G", "40M", "HT", "1T", "10", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "10", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "10", "28", "FCC", "2.4G", "40M", "HT", "1T", "11", "20", "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", "MKK", "2.4G", "40M", "HT", "1T", "11", "30", + "IC", "2.4G", "40M", "HT", "1T", "11", "20", + "KCC", "2.4G", "40M", "HT", "1T", "11", "30", + "ACMA", "2.4G", "40M", "HT", "1T", "11", "30", + "CHILE", "2.4G", "40M", "HT", "1T", "11", "20", "FCC", "2.4G", "40M", "HT", "1T", "12", "63", "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "IC", "2.4G", "40M", "HT", "1T", "12", "63", + "KCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ACMA", "2.4G", "40M", "HT", "1T", "12", "63", + "CHILE", "2.4G", "40M", "HT", "1T", "12", "63", "FCC", "2.4G", "40M", "HT", "1T", "13", "63", "ETSI", "2.4G", "40M", "HT", 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"FCC", "5G", "20M", "HT", "1T", "64", "27", "ETSI", "5G", "20M", "HT", "1T", "64", "32", "MKK", "5G", "20M", "HT", "1T", "64", "33", - "FCC", "5G", "20M", "HT", "1T", "100", "30", + "IC", "5G", "20M", "HT", "1T", "64", "30", + "KCC", "5G", "20M", "HT", "1T", "64", "33", + "ACMA", "5G", "20M", "HT", "1T", "64", "32", + "CHILE", "5G", "20M", "HT", "1T", "64", "30", + "FCC", "5G", "20M", "HT", "1T", "100", "27", "ETSI", "5G", "20M", "HT", "1T", "100", "32", "MKK", "5G", "20M", "HT", "1T", "100", "33", - "FCC", "5G", "20M", "HT", "1T", "104", "33", + "IC", "5G", "20M", "HT", "1T", "100", "30", + "KCC", "5G", "20M", "HT", "1T", "100", "33", + "ACMA", "5G", "20M", "HT", "1T", "100", "32", + "CHILE", "5G", "20M", "HT", "1T", "100", "30", + "FCC", "5G", "20M", "HT", "1T", "104", "27", "ETSI", "5G", "20M", "HT", "1T", "104", "32", "MKK", "5G", "20M", "HT", "1T", "104", "33", - "FCC", "5G", "20M", "HT", "1T", "108", "33", + "IC", "5G", "20M", "HT", "1T", "104", "33", + "KCC", "5G", "20M", "HT", "1T", "104", "33", + "ACMA", "5G", "20M", "HT", "1T", "104", "32", + "CHILE", "5G", "20M", "HT", "1T", "104", "30", + "FCC", "5G", "20M", "HT", "1T", "108", "27", "ETSI", "5G", "20M", "HT", "1T", "108", "32", "MKK", "5G", "20M", "HT", "1T", "108", "33", - "FCC", "5G", "20M", "HT", "1T", "112", "33", + "IC", "5G", "20M", "HT", "1T", "108", "33", + "KCC", "5G", "20M", "HT", "1T", "108", "33", + "ACMA", "5G", "20M", "HT", "1T", "108", "32", + "CHILE", "5G", "20M", "HT", "1T", "108", "30", + "FCC", "5G", "20M", "HT", "1T", "112", "27", "ETSI", "5G", "20M", "HT", "1T", "112", "32", "MKK", "5G", "20M", "HT", "1T", "112", "33", - "FCC", "5G", "20M", "HT", "1T", "116", "33", + "IC", "5G", "20M", "HT", "1T", "112", "33", + "KCC", "5G", "20M", "HT", "1T", "112", "33", + "ACMA", "5G", "20M", "HT", "1T", "112", "32", + "CHILE", "5G", "20M", "HT", "1T", "112", "30", + "FCC", "5G", "20M", "HT", "1T", "116", "27", "ETSI", "5G", "20M", "HT", "1T", "116", "32", "MKK", "5G", "20M", "HT", "1T", "116", "33", - "FCC", "5G", "20M", "HT", "1T", "120", "33", + "IC", "5G", "20M", "HT", "1T", "116", "33", + "KCC", "5G", "20M", "HT", "1T", "116", "33", + "ACMA", "5G", "20M", "HT", "1T", "116", "32", + "CHILE", "5G", "20M", "HT", "1T", "116", "30", + "FCC", "5G", "20M", "HT", "1T", "120", "27", "ETSI", "5G", "20M", "HT", "1T", "120", "32", "MKK", "5G", "20M", "HT", "1T", "120", "33", - "FCC", "5G", "20M", "HT", "1T", "124", "33", + "IC", "5G", "20M", "HT", "1T", "120", "63", + "KCC", "5G", "20M", "HT", "1T", "120", "33", + "ACMA", "5G", "20M", "HT", "1T", "120", "32", + "CHILE", "5G", "20M", "HT", "1T", "120", "30", + "FCC", "5G", "20M", "HT", "1T", "124", "27", "ETSI", "5G", "20M", "HT", "1T", "124", "32", "MKK", "5G", "20M", "HT", "1T", "124", "33", - "FCC", "5G", "20M", "HT", "1T", "128", "33", + "IC", "5G", "20M", "HT", "1T", "124", "63", + "KCC", "5G", "20M", "HT", "1T", "124", "33", + "ACMA", "5G", "20M", "HT", "1T", "124", "32", + "CHILE", "5G", "20M", "HT", "1T", "124", "30", + "FCC", "5G", "20M", "HT", "1T", "128", "27", "ETSI", "5G", "20M", "HT", "1T", "128", "32", "MKK", "5G", "20M", "HT", "1T", "128", "33", - "FCC", "5G", "20M", "HT", "1T", "132", "33", + "IC", "5G", "20M", "HT", "1T", "128", "63", + "KCC", "5G", "20M", "HT", "1T", "128", "63", + "ACMA", "5G", "20M", "HT", "1T", "128", "32", + "CHILE", "5G", "20M", "HT", "1T", "128", "30", + "FCC", "5G", "20M", "HT", "1T", "132", "27", "ETSI", "5G", "20M", "HT", "1T", "132", "32", "MKK", "5G", "20M", "HT", "1T", "132", "33", - "FCC", "5G", "20M", "HT", "1T", "136", "33", + "IC", "5G", "20M", "HT", "1T", "132", "33", + "KCC", "5G", "20M", "HT", "1T", "132", "63", + "ACMA", "5G", "20M", "HT", "1T", "132", "32", + "CHILE", "5G", "20M", "HT", "1T", "132", "30", + "FCC", "5G", "20M", "HT", "1T", "136", "27", "ETSI", "5G", "20M", "HT", "1T", "136", "32", "MKK", "5G", "20M", "HT", "1T", "136", "33", - "FCC", "5G", "20M", "HT", "1T", "140", "29", + "IC", "5G", "20M", "HT", "1T", "136", "33", + "KCC", "5G", "20M", "HT", "1T", "136", "63", + "ACMA", "5G", "20M", "HT", "1T", "136", "32", + "CHILE", "5G", "20M", "HT", "1T", "136", "30", + "FCC", "5G", "20M", "HT", "1T", "140", "27", "ETSI", "5G", "20M", "HT", "1T", "140", "32", "MKK", "5G", "20M", "HT", "1T", "140", "33", + "IC", "5G", "20M", "HT", "1T", "140", "29", + "KCC", "5G", "20M", "HT", "1T", "140", "63", + "ACMA", "5G", "20M", "HT", "1T", "140", "32", + "CHILE", "5G", "20M", "HT", "1T", "140", "30", "FCC", "5G", "20M", "HT", "1T", "144", "27", "ETSI", "5G", "20M", "HT", "1T", "144", "63", "MKK", "5G", "20M", "HT", "1T", "144", "63", - "FCC", "5G", "20M", "HT", "1T", "149", "33", + "IC", "5G", "20M", "HT", "1T", "144", "27", + "KCC", "5G", "20M", "HT", "1T", "144", "63", + "ACMA", "5G", "20M", "HT", "1T", "144", "63", + "CHILE", "5G", "20M", "HT", "1T", "144", "30", + "FCC", "5G", "20M", "HT", "1T", "149", "28", "ETSI", "5G", "20M", "HT", "1T", "149", "63", "MKK", "5G", "20M", "HT", "1T", "149", "63", - "FCC", "5G", "20M", "HT", "1T", "153", "33", + "IC", "5G", "20M", "HT", "1T", "149", "33", + "KCC", "5G", "20M", "HT", "1T", "149", "33", + "ACMA", "5G", "20M", "HT", "1T", "149", "33", + "CHILE", "5G", "20M", "HT", "1T", "149", "30", + "FCC", "5G", "20M", "HT", "1T", "153", "28", "ETSI", "5G", "20M", "HT", "1T", "153", "63", "MKK", "5G", "20M", "HT", "1T", "153", "63", - "FCC", "5G", "20M", "HT", "1T", "157", "33", + "IC", "5G", "20M", "HT", "1T", "153", "33", + "KCC", "5G", "20M", "HT", "1T", "153", "33", + "ACMA", "5G", "20M", "HT", "1T", "153", "33", + "CHILE", "5G", "20M", "HT", "1T", "153", "30", + "FCC", "5G", "20M", "HT", "1T", "157", "28", "ETSI", "5G", "20M", "HT", "1T", "157", "63", "MKK", "5G", "20M", "HT", "1T", "157", "63", - "FCC", "5G", "20M", "HT", "1T", "161", "33", + "IC", "5G", "20M", "HT", "1T", "157", "33", + "KCC", "5G", "20M", "HT", "1T", "157", "33", + "ACMA", "5G", "20M", "HT", "1T", "157", "33", + "CHILE", "5G", "20M", "HT", "1T", "157", "30", + "FCC", "5G", "20M", "HT", "1T", "161", "28", "ETSI", "5G", "20M", "HT", "1T", "161", "63", "MKK", "5G", "20M", "HT", "1T", "161", "63", - "FCC", "5G", "20M", "HT", "1T", "165", "33", + "IC", "5G", "20M", "HT", "1T", "161", "33", + "KCC", "5G", "20M", "HT", "1T", "161", "31", + "ACMA", "5G", "20M", "HT", "1T", "161", "33", + "CHILE", "5G", "20M", "HT", "1T", "161", "30", + "FCC", "5G", "20M", "HT", "1T", "165", "28", "ETSI", "5G", "20M", "HT", "1T", "165", "63", "MKK", "5G", "20M", "HT", "1T", "165", "63", + "IC", "5G", "20M", "HT", "1T", "165", "33", + "KCC", "5G", "20M", "HT", "1T", "165", "63", + "ACMA", "5G", "20M", "HT", "1T", "165", "33", + "CHILE", "5G", "20M", "HT", "1T", "165", "30", "FCC", "5G", "40M", "HT", "1T", "38", "22", "ETSI", "5G", "40M", "HT", "1T", "38", "32", "MKK", "5G", "40M", "HT", "1T", "38", "32", - "FCC", "5G", "40M", "HT", "1T", "46", "32", + "IC", "5G", "40M", "HT", "1T", "38", "22", + "KCC", "5G", "40M", "HT", "1T", "38", "26", + "ACMA", "5G", "40M", "HT", "1T", "38", "32", + "CHILE", "5G", "40M", "HT", "1T", "38", "22", + "FCC", "5G", "40M", "HT", "1T", "46", "24", "ETSI", "5G", "40M", "HT", "1T", "46", "32", "MKK", "5G", "40M", "HT", "1T", "46", "32", - "FCC", "5G", "40M", "HT", "1T", "54", "32", + "IC", "5G", "40M", "HT", "1T", "46", "32", + "KCC", "5G", "40M", "HT", "1T", "46", "28", + "ACMA", "5G", "40M", "HT", "1T", "46", "32", + "CHILE", "5G", "40M", "HT", "1T", "46", "30", + "FCC", "5G", "40M", "HT", "1T", "54", "27", "ETSI", "5G", "40M", "HT", "1T", "54", "32", "MKK", "5G", "40M", "HT", "1T", "54", "32", + "IC", "5G", "40M", "HT", "1T", "54", "32", + "KCC", "5G", "40M", "HT", "1T", "54", "22", + "ACMA", "5G", "40M", "HT", "1T", "54", "32", + "CHILE", "5G", "40M", "HT", "1T", "54", "30", "FCC", "5G", "40M", "HT", "1T", "62", "23", "ETSI", "5G", "40M", "HT", "1T", "62", "32", "MKK", "5G", "40M", "HT", "1T", "62", "32", + "IC", "5G", "40M", "HT", "1T", "62", "23", + "KCC", "5G", "40M", "HT", "1T", "62", "31", + "ACMA", "5G", "40M", "HT", "1T", "62", "32", + "CHILE", "5G", "40M", "HT", "1T", "62", "23", "FCC", "5G", "40M", "HT", "1T", "102", "21", "ETSI", "5G", "40M", "HT", "1T", "102", "32", "MKK", "5G", "40M", "HT", "1T", "102", "32", - "FCC", "5G", "40M", "HT", "1T", "110", "32", + "IC", "5G", "40M", "HT", "1T", "102", "21", + "KCC", "5G", "40M", "HT", "1T", "102", "31", + "ACMA", "5G", "40M", "HT", "1T", "102", "32", + "CHILE", "5G", "40M", "HT", "1T", "102", "30", + "FCC", "5G", "40M", "HT", "1T", "110", "27", "ETSI", "5G", "40M", "HT", "1T", "110", "32", "MKK", "5G", "40M", "HT", "1T", "110", "32", - "FCC", "5G", "40M", "HT", "1T", "118", "32", + "IC", "5G", "40M", "HT", "1T", "110", "32", + "KCC", "5G", "40M", "HT", "1T", "110", "32", + "ACMA", "5G", "40M", "HT", "1T", "110", "32", + "CHILE", "5G", "40M", "HT", "1T", "110", "30", + "FCC", "5G", "40M", "HT", "1T", "118", "27", "ETSI", "5G", "40M", "HT", "1T", "118", "32", "MKK", "5G", "40M", "HT", "1T", "118", "32", - "FCC", "5G", "40M", "HT", "1T", "126", "32", + "IC", "5G", "40M", "HT", "1T", "118", "63", + "KCC", "5G", "40M", "HT", "1T", "118", "32", + "ACMA", "5G", "40M", "HT", "1T", "118", "32", + "CHILE", "5G", "40M", "HT", "1T", "118", "30", + "FCC", "5G", "40M", "HT", "1T", "126", "27", "ETSI", "5G", "40M", "HT", "1T", "126", "32", "MKK", "5G", "40M", "HT", "1T", "126", "32", - "FCC", "5G", "40M", "HT", "1T", "134", "32", + "IC", "5G", "40M", "HT", "1T", "126", "63", + "KCC", "5G", "40M", "HT", "1T", "126", "63", + "ACMA", "5G", "40M", "HT", "1T", "126", "32", + "CHILE", "5G", "40M", "HT", "1T", "126", "30", + "FCC", "5G", "40M", "HT", "1T", "134", "27", "ETSI", "5G", "40M", "HT", "1T", "134", "32", "MKK", "5G", "40M", "HT", "1T", "134", "32", - "FCC", "5G", "40M", "HT", "1T", "142", "29", + "IC", "5G", "40M", "HT", "1T", "134", "32", + "KCC", "5G", "40M", "HT", "1T", "134", "63", + "ACMA", "5G", "40M", "HT", "1T", "134", "32", + "CHILE", "5G", "40M", "HT", "1T", "134", "30", + "FCC", "5G", "40M", "HT", "1T", "142", "27", "ETSI", "5G", "40M", "HT", "1T", "142", "63", "MKK", "5G", "40M", "HT", "1T", "142", "63", - "FCC", "5G", "40M", "HT", "1T", "151", "32", + "IC", "5G", "40M", "HT", "1T", "142", "29", + "KCC", "5G", "40M", "HT", "1T", "142", "63", + "ACMA", "5G", "40M", "HT", "1T", "142", "63", + "CHILE", "5G", "40M", "HT", "1T", "142", "30", + "FCC", "5G", "40M", "HT", "1T", "151", "28", "ETSI", "5G", "40M", "HT", "1T", "151", "63", "MKK", "5G", "40M", "HT", "1T", "151", "63", - "FCC", "5G", "40M", "HT", "1T", "159", "32", + "IC", "5G", "40M", "HT", "1T", "151", "32", + "KCC", "5G", "40M", "HT", "1T", "151", "27", + "ACMA", "5G", "40M", "HT", "1T", "151", "32", + "CHILE", "5G", "40M", "HT", "1T", "151", "30", + "FCC", "5G", "40M", "HT", "1T", "159", "28", "ETSI", "5G", "40M", "HT", "1T", "159", "63", "MKK", "5G", "40M", "HT", "1T", "159", "63", + "IC", "5G", "40M", "HT", "1T", "159", "32", + "KCC", "5G", "40M", "HT", "1T", "159", "26", + "ACMA", "5G", "40M", "HT", "1T", "159", "32", + "CHILE", "5G", "40M", "HT", "1T", "159", "30", "FCC", "5G", "80M", "VHT", "1T", "42", "19", "ETSI", "5G", "80M", "VHT", "1T", "42", "32", "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "IC", "5G", "80M", "VHT", "1T", "42", "19", + "KCC", "5G", "80M", "VHT", "1T", "42", "25", + "ACMA", "5G", "80M", "VHT", "1T", "42", "32", + "CHILE", "5G", "80M", "VHT", "1T", "42", "19", "FCC", "5G", "80M", "VHT", "1T", "58", "22", "ETSI", "5G", "80M", "VHT", "1T", "58", "32", "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "IC", "5G", "80M", "VHT", "1T", "58", "22", + "KCC", "5G", "80M", "VHT", "1T", "58", "28", + "ACMA", "5G", "80M", "VHT", "1T", "58", "32", + "CHILE", "5G", "80M", "VHT", "1T", "58", "22", "FCC", "5G", "80M", "VHT", "1T", "106", "18", "ETSI", "5G", "80M", "VHT", "1T", "106", "32", "MKK", "5G", "80M", "VHT", "1T", "106", "32", - "FCC", "5G", "80M", "VHT", "1T", "122", "32", + "IC", "5G", "80M", "VHT", "1T", "106", "18", + "KCC", "5G", "80M", "VHT", "1T", "106", "30", + "ACMA", "5G", "80M", "VHT", "1T", "106", "32", + "CHILE", "5G", "80M", "VHT", "1T", "106", "30", + "FCC", "5G", "80M", "VHT", "1T", "122", "27", "ETSI", "5G", "80M", "VHT", "1T", "122", "32", "MKK", "5G", "80M", "VHT", "1T", "122", "32", - "FCC", "5G", "80M", "VHT", "1T", "138", "28", + "IC", "5G", "80M", "VHT", "1T", "122", "63", + "KCC", "5G", "80M", "VHT", "1T", "122", "26", + "ACMA", "5G", "80M", "VHT", "1T", "122", "32", + "CHILE", "5G", "80M", "VHT", "1T", "122", "30", + "FCC", "5G", "80M", "VHT", "1T", "138", "27", "ETSI", "5G", "80M", "VHT", "1T", "138", "63", "MKK", "5G", "80M", "VHT", "1T", "138", "63", - "FCC", "5G", "80M", "VHT", "1T", "155", "32", + "IC", "5G", "80M", "VHT", "1T", "138", "28", + "KCC", "5G", "80M", "VHT", "1T", "138", "63", + "ACMA", "5G", "80M", "VHT", "1T", "138", "63", + "CHILE", "5G", "80M", "VHT", "1T", "138", "30", + "FCC", "5G", "80M", "VHT", "1T", "155", "28", "ETSI", "5G", "80M", "VHT", "1T", "155", "63", - "MKK", "5G", "80M", "VHT", "1T", "155", "63" + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "IC", "5G", "80M", "VHT", "1T", "155", "32", + "KCC", "5G", "80M", "VHT", "1T", "155", "27", + "ACMA", "5G", "80M", "VHT", "1T", "155", "32", + "CHILE", "5G", "80M", "VHT", "1T", "155", "30" }; void -odm_read_and_config_mp_8821c_txpwr_lmt( - struct PHY_DM_STRUCT *p_dm_odm -) +odm_read_and_config_mp_8821c_txpwr_lmt_fccsar(struct dm_struct *dm) { u32 i = 0; #if (DM_ODM_SUPPORT_TYPE == ODM_IOT) - u32 array_len = sizeof(array_mp_8821c_txpwr_lmt)/sizeof(u8); - u8 *array = (u8 *)array_mp_8821c_txpwr_lmt; + u32 array_len = sizeof(array_mp_8821c_txpwr_lmt_fccsar) / sizeof(u8); + u8 *array = (u8 *)array_mp_8821c_txpwr_lmt_fccsar; #else - u32 array_len = sizeof(array_mp_8821c_txpwr_lmt)/sizeof(u8 *); - u8 **array = (u8 **)array_mp_8821c_txpwr_lmt; + u32 array_len = sizeof(array_mp_8821c_txpwr_lmt_fccsar) / sizeof(u8 *); + u8 **array = (u8 **)array_mp_8821c_txpwr_lmt_fccsar; #endif #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter = p_dm_odm->adapter; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); - PlatformZeroMemory(p_hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - p_hal_data->nLinesReadPwrLmt = array_len/7; + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len / 7; #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_txpwr_lmt\n")); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); for (i = 0; i < array_len; i += 7) { #if (DM_ODM_SUPPORT_TYPE == ODM_IOT) u8 regulation = array[i]; - u8 band = array[i+1]; - u8 bandwidth = array[i+2]; - u8 rate = array[i+3]; - u8 rf_path = array[i+4]; - u8 chnl = array[i+5]; - u8 val = array[i+6]; + u8 band = array[i + 1]; + u8 bandwidth = array[i + 2]; + u8 rate = array[i + 3]; + u8 rf_path = array[i + 4]; + u8 chnl = array[i + 5]; + u8 val = array[i + 6]; #else u8 *regulation = array[i]; - u8 *band = array[i+1]; - u8 *bandwidth = array[i+2]; - u8 *rate = array[i+3]; - u8 *rf_path = array[i+4]; - u8 *chnl = array[i+5]; - u8 *val = array[i+6]; + u8 *band = array[i + 1]; + u8 *bandwidth = array[i + 2]; + u8 *rate = array[i + 3]; + u8 *rf_path = array[i + 4]; + u8 *chnl = array[i + 5]; + u8 *val = array[i + 6]; #endif - odm_config_bb_txpwr_lmt_8821c(p_dm_odm, regulation, band, bandwidth, rate, rf_path, chnl, val); + odm_config_bb_txpwr_lmt_8821c(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - rsprintf((char *)p_hal_data->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i / 7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", regulation, band, bandwidth, rate, rf_path, chnl, val); #endif } - } #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8821c/halhwimg8821c_rf.h b/hal/phydm/rtl8821c/halhwimg8821c_rf.h index 711b601..1df1853 100644 --- a/hal/phydm/rtl8821c/halhwimg8821c_rf.h +++ b/hal/phydm/rtl8821c/halhwimg8821c_rf.h @@ -1,24 +1,29 @@ /****************************************************************************** -* -* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ -/*Image2HeaderVersion: 3.4*/ +/*Image2HeaderVersion: R3 1.0*/ #if (RTL8821C_SUPPORT == 1) #ifndef __INC_MP_RF_HW_IMG_8821C_H #define __INC_MP_RF_HW_IMG_8821C_H @@ -29,31 +34,57 @@ ******************************************************************************/ void -odm_read_and_config_mp_8821c_radioa(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm -); -u32 odm_get_version_mp_8821c_radioa(void); +odm_read_and_config_mp_8821c_radioa( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8821c_radioa(void); /****************************************************************************** * txpowertrack.TXT ******************************************************************************/ void -odm_read_and_config_mp_8821c_txpowertrack(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm -); +odm_read_and_config_mp_8821c_txpowertrack( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); u32 odm_get_version_mp_8821c_txpowertrack(void); +/****************************************************************************** +* txpowertrack_type0x20.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_txpowertrack_type0x20( + /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8821c_txpowertrack_type0x20(void); + +/****************************************************************************** +* txpowertrack_type0x28.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_txpowertrack_type0x28( + /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8821c_txpowertrack_type0x28(void); + /****************************************************************************** * txpwr_lmt.TXT ******************************************************************************/ void -odm_read_and_config_mp_8821c_txpwr_lmt(/* tc: Test Chip, mp: mp Chip*/ - struct PHY_DM_STRUCT *p_dm_odm -); +odm_read_and_config_mp_8821c_txpwr_lmt( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); u32 odm_get_version_mp_8821c_txpwr_lmt(void); +/****************************************************************************** +* txpwr_lmt_fccsar.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_txpwr_lmt_fccsar( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8821c_txpwr_lmt_fccsar(void); + #endif #endif /* end of HWIMG_SUPPORT*/ diff --git a/hal/phydm/rtl8821c/mp_precomp.h b/hal/phydm/rtl8821c/mp_precomp.h new file mode 100644 index 0000000..e938c5f --- /dev/null +++ b/hal/phydm/rtl8821c/mp_precomp.h @@ -0,0 +1,14 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ diff --git a/hal/phydm/rtl8821c/phydm_hal_api8821c.c b/hal/phydm/rtl8821c/phydm_hal_api8821c.c index 84ac605..4dbaa12 100644 --- a/hal/phydm/rtl8821c/phydm_hal_api8821c.c +++ b/hal/phydm/rtl8821c/phydm_hal_api8821c.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,90 +11,98 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (RTL8821C_SUPPORT == 1) - +#if (PHYDM_FW_API_ENABLE_8821C == 1) /* ======================================================================== */ /* These following functions can be used for PHY DM only*/ -u32 reg82c_8821c; -u32 reg838_8821c; -u32 reg830_8821c; -u32 rega24_8821c; -u32 rega28_8821c; -u32 regaac_8821c; +u32 rega24_8821c; +u32 rega28_8821c; +u32 regaac_8821c; -enum odm_bw_e bw_8821c; -u8 central_ch_8821c; +enum channel_width bw_8821c; +u8 central_ch_8821c; + +__iram_odm_func__ +s8 phydm_cck_rssi_8821c(struct dm_struct *dm, u8 lna_idx, u8 vga_idx) +{ + s8 rx_pwr_all = 0; + s8 lna_gain = 0; + /*only use lna2/3/5/7*/ + s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52}; + /*only use lna4/8/C/F*/ + s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17, + -20, -24, -28, -31, -34, -37, -40, -44}; + + if (dm->cck_agc_report_type == 0) + lna_gain = lna_gain_table_0[lna_idx]; + else + lna_gain = lna_gain_table_1[lna_idx]; + rx_pwr_all = lna_gain - (2 * vga_idx); + return rx_pwr_all; +} + +__iram_odm_func__ boolean -phydm_rfe_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 channel -) +phydm_rfe_8821c(struct dm_struct *dm, u8 channel) { #if 0 /* Efuse is not wrote now */ /* Need to check RFE type finally */ - /*if (p_dm_odm->rfe_type == 1) {*/ + /*if (dm->rfe_type == 1) {*/ if (channel <= 14) { /* signal source */ - odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x704570); - odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x704570); - odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x45); - odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x45); + odm_set_bb_reg(dm, R_0xcb0, (MASKBYTE2 | MASKLWORD), 0x704570); + odm_set_bb_reg(dm, R_0xeb0, (MASKBYTE2 | MASKLWORD), 0x704570); + odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x45); + odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x45); } else if (channel > 35) { - odm_set_bb_reg(p_dm_odm, 0xcb0, (MASKBYTE2 | MASKLWORD), 0x174517); - odm_set_bb_reg(p_dm_odm, 0xeb0, (MASKBYTE2 | MASKLWORD), 0x174517); - odm_set_bb_reg(p_dm_odm, 0xcb4, MASKBYTE1, 0x45); - odm_set_bb_reg(p_dm_odm, 0xeb4, MASKBYTE1, 0x45); + odm_set_bb_reg(dm, R_0xcb0, (MASKBYTE2 | MASKLWORD), 0x174517); + odm_set_bb_reg(dm, R_0xeb0, (MASKBYTE2 | MASKLWORD), 0x174517); + odm_set_bb_reg(dm, R_0xcb4, MASKBYTE1, 0x45); + odm_set_bb_reg(dm, R_0xeb4, MASKBYTE1, 0x45); } else return false; /* chip top mux */ - odm_set_bb_reg(p_dm_odm, 0x64, BIT(29) | BIT(28), 0x3); - odm_set_bb_reg(p_dm_odm, 0x4c, BIT(26) | BIT(25), 0x0); - odm_set_bb_reg(p_dm_odm, 0x40, BIT(2), 0x1); + odm_set_bb_reg(dm, R_0x64, BIT(29) | BIT(28), 0x3); + odm_set_bb_reg(dm, R_0x4c, BIT(26) | BIT(25), 0x0); + odm_set_bb_reg(dm, R_0x40, BIT(2), 0x1); /* from s0 or s1 */ - odm_set_bb_reg(p_dm_odm, 0x1990, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x30); - odm_set_bb_reg(p_dm_odm, 0x1990, (BIT(11) | BIT(10)), 0x3); + odm_set_bb_reg(dm, R_0x1990, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x30); + odm_set_bb_reg(dm, R_0x1990, (BIT(11) | BIT(10)), 0x3); /* input or output */ - odm_set_bb_reg(p_dm_odm, 0x974, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x3f); - odm_set_bb_reg(p_dm_odm, 0x974, (BIT(11) | BIT(10)), 0x3); + odm_set_bb_reg(dm, R_0x974, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x3f); + odm_set_bb_reg(dm, R_0x974, (BIT(11) | BIT(10)), 0x3); /* delay 400ns for PAPE */ - odm_set_bb_reg(p_dm_odm, 0x810, MASKBYTE3 | BIT(20) | BIT(21) | BIT(22) | BIT(23), 0x211); + odm_set_bb_reg(dm, R_0x810, MASKBYTE3 | BIT(20) | BIT(21) | BIT(22) | BIT(23), 0x211); /* antenna switch table */ - odm_set_bb_reg(p_dm_odm, 0xca0, MASKLWORD, 0xa555); - odm_set_bb_reg(p_dm_odm, 0xea0, MASKLWORD, 0xa555); + odm_set_bb_reg(dm, R_0xca0, MASKLWORD, 0xa555); + odm_set_bb_reg(dm, R_0xea0, MASKLWORD, 0xa555); /* inverse or not */ - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xcbc, (BIT(11) | BIT(10)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); - odm_set_bb_reg(p_dm_odm, 0xebc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, R_0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); + odm_set_bb_reg(dm, R_0xcbc, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, R_0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)), 0x0); + odm_set_bb_reg(dm, R_0xebc, (BIT(11) | BIT(10)), 0x0); /*}*/ #endif return true; } -void -phydm_ccapar_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +void phydm_ccapar_8821c(struct dm_struct *dm) { #if 0 u32 cca_ifem[9][4] = { @@ -130,29 +138,29 @@ phydm_ccapar_8821c( u8 row, col; u32 reg82c, reg830, reg838; - if (p_dm_odm->cut_version != ODM_CUT_B) + if (dm->cut_version != ODM_CUT_B) return; - if (bw_8821c == ODM_BW20M) + if (bw_8821c == CHANNEL_WIDTH_20) row = 0; - else if (bw_8821c == ODM_BW40M) + else if (bw_8821c == CHANNEL_WIDTH_40) row = 3; else row = 6; if (central_ch_8821c <= 14) { - if ((p_dm_odm->rx_ant_status == ODM_RF_A) || (p_dm_odm->rx_ant_status == ODM_RF_B)) + if (dm->rx_ant_status == BB_PATH_A || dm->rx_ant_status == BB_PATH_B) col = 0; else col = 1; } else { - if ((p_dm_odm->rx_ant_status == ODM_RF_A) || (p_dm_odm->rx_ant_status == ODM_RF_B)) + if (dm->rx_ant_status == BB_PATH_A || dm->rx_ant_status == BB_PATH_B) col = 2; else col = 3; } - if (p_dm_odm->rfe_type == 0) {/*iFEM*/ + if (dm->rfe_type == 0) {/*iFEM*/ reg82c = (cca_ifem[row][col] != 0) ? cca_ifem[row][col] : reg82c_8821c; reg830 = (cca_ifem[row + 1][col] != 0) ? cca_ifem[row + 1][col] : reg830_8821c; reg838 = (cca_ifem[row + 2][col] != 0) ? cca_ifem[row + 2][col] : reg838_8821c; @@ -162,46 +170,46 @@ phydm_ccapar_8821c( reg838 = (cca_efem[row + 2][col] != 0) ? cca_efem[row + 2][col] : reg838_8821c; } - odm_set_bb_reg(p_dm_odm, 0x82c, MASKDWORD, reg82c); - odm_set_bb_reg(p_dm_odm, 0x830, MASKDWORD, reg830); - odm_set_bb_reg(p_dm_odm, 0x838, MASKDWORD, reg838); + odm_set_bb_reg(dm, R_0x82c, MASKDWORD, reg82c); + odm_set_bb_reg(dm, R_0x830, MASKDWORD, reg830); + odm_set_bb_reg(dm, R_0x838, MASKDWORD, reg838); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Update CCA parameters for Bcut (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n", - __func__, p_dm_odm->package_type, p_dm_odm->support_interface, p_dm_odm->rfe_type, row, col)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Update CCA parameters for Bcut (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n", + __func__, dm->package_type, dm->support_interface, + dm->rfe_type, row, col); #endif } -void -phydm_ccapar_by_bw_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_bw_e bandwidth -) +__iram_odm_func__ +void phydm_ccapar_by_bw_8821c(struct dm_struct *dm, + enum channel_width bandwidth) { #if 0 u32 reg82c; - if (p_dm_odm->cut_version != ODM_CUT_A) + if (dm->cut_version != ODM_CUT_A) return; /* A-cut */ - reg82c = odm_get_bb_reg(p_dm_odm, 0x82c, MASKDWORD); + reg82c = odm_get_bb_reg(dm, R_0x82c, MASKDWORD); - if (bandwidth == ODM_BW20M) { + if (bandwidth == CHANNEL_WIDTH_20) { /* 82c[15:12] = 4 */ /* 82c[27:24] = 6 */ reg82c &= (~(0x0f00f000)); reg82c |= ((0x4) << 12); reg82c |= ((0x6) << 24); - } else if (bandwidth == ODM_BW40M) { + } else if (bandwidth == CHANNEL_WIDTH_40) { /* 82c[19:16] = 9 */ /* 82c[27:24] = 6 */ reg82c &= (~(0x0f0f0000)); reg82c |= ((0x9) << 16); reg82c |= ((0x6) << 24); - } else if (bandwidth == ODM_BW80M) { + } else if (bandwidth == CHANNEL_WIDTH_80) { /* 82c[15:12] 7 */ /* 82c[19:16] b */ /* 82c[23:20] d */ @@ -212,28 +220,27 @@ phydm_ccapar_by_bw_8821c( reg82c |= ((0x3) << 24); } - odm_set_bb_reg(p_dm_odm, 0x82c, MASKDWORD, reg82c); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Update CCA parameters for Acut\n", __func__)); + odm_set_bb_reg(dm, R_0x82c, MASKDWORD, reg82c); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: Update CCA parameters for Acut\n", + __func__); #endif } -void -phydm_ccapar_by_rxpath_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +void phydm_ccapar_by_rxpath_8821c(struct dm_struct *dm) { #if 0 - if (p_dm_odm->cut_version != ODM_CUT_A) + if (dm->cut_version != ODM_CUT_A) return; - if ((p_dm_odm->rx_ant_status == ODM_RF_A) || (p_dm_odm->rx_ant_status == ODM_RF_B)) { + if (dm->rx_ant_status == BB_PATH_A || dm->rx_ant_status == BB_PATH_B) { /* 838[7:4] = 8 */ /* 838[11:8] = 7 */ /* 838[15:12] = 6 */ /* 838[19:16] = 7 */ /* 838[23:20] = 7 */ /* 838[27:24] = 7 */ - odm_set_bb_reg(p_dm_odm, 0x838, 0x0ffffff0, 0x777678); + odm_set_bb_reg(dm, R_0x838, 0x0ffffff0, 0x777678); } else { /* 838[7:4] = 3 */ /* 838[11:8] = 3 */ @@ -241,58 +248,56 @@ phydm_ccapar_by_rxpath_8821c( /* 838[19:16] = 6 */ /* 838[23:20] = 7 */ /* 838[27:24] = 7 */ - odm_set_bb_reg(p_dm_odm, 0x838, 0x0ffffff0, 0x776633); + odm_set_bb_reg(dm, R_0x838, 0x0ffffff0, 0x776633); } - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Update CCA parameters for Acut\n", __func__)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: Update CCA parameters for Acut\n", + __func__); #endif } -void -phydm_rxdfirpar_by_bw_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_bw_e bandwidth -) +__iram_odm_func__ +void phydm_rxdfirpar_by_bw_8821c(struct dm_struct *dm, + enum channel_width bandwidth) { - if (bandwidth == ODM_BW40M) { + if (bandwidth == CHANNEL_WIDTH_40) { /* RX DFIR for BW40 */ - odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x2); - odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x2); - odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8f0, BIT(31), 0x0); - } else if (bandwidth == ODM_BW80M) { + odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x0); + odm_set_bb_reg(dm, R_0x8f0, BIT(31), 0x0); + } else if (bandwidth == CHANNEL_WIDTH_80) { /* RX DFIR for BW80 */ - odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x2); - odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x1); - odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8f0, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x1); + odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x0); + odm_set_bb_reg(dm, R_0x8f0, BIT(31), 0x1); } else { /* RX DFIR for BW20, BW10 and BW5*/ - odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x2); - odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x2); - odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x1); - odm_set_bb_reg(p_dm_odm, 0x8f0, BIT(31), 0x0); + odm_set_bb_reg(dm, R_0x948, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(dm, R_0x94c, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(dm, R_0xc20, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0x8f0, BIT(31), 0x0); } + /* PHYDM_DBG(dm, ODM_PHY_CONFIG, "phydm_rxdfirpar_by_bw_8821c\n");*/ } +__iram_odm_func__ boolean -phydm_write_txagc_1byte_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 power_index, - enum odm_rf_radio_path_e path, - u8 hw_rate -) +phydm_write_txagc_1byte_8821c(struct dm_struct *dm, u32 power_index, + enum rf_path path, u8 hw_rate) { - u32 offset_txagc[2] = {0x1d00, 0x1d80}; - u8 rate_idx = (hw_rate & 0xfc), i; - u8 rate_offset = (hw_rate & 0x3); - u32 rate_mask = (0xff << (rate_offset << 3)); - u32 txagc_content = 0x0; +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + u32 offset_txagc[2] = {0x1d00, 0x1d80}; + u8 rate_idx = (hw_rate & 0xfc), i; + u8 rate_offset = (hw_rate & 0x3); + u32 txagc_content = 0x0; /* For debug command only!!!! */ /* Error handling */ - if ((path > ODM_RF_PATH_A) || (hw_rate > 0x53)) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, path)); + if (path > RF_PATH_A || hw_rate > 0x53) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n", + __func__, path); return false; } @@ -300,58 +305,78 @@ phydm_write_txagc_1byte_8821c( /* For HW limitation, We can't write TXAGC once a byte. */ for (i = 0; i < 4; i++) { if (i != rate_offset) - txagc_content = txagc_content | (config_phydm_read_txagc_8821c(p_dm_odm, path, rate_idx + i) << (i << 3)); + txagc_content = txagc_content | (config_phydm_read_txagc_8821c(dm, path, rate_idx + i) << (i << 3)); else txagc_content = txagc_content | ((power_index & 0x3f) << (i << 3)); } - odm_set_bb_reg(p_dm_odm, (offset_txagc[path] + rate_idx), MASKDWORD, txagc_content); + odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD, txagc_content); #else - odm_write_1byte(p_dm_odm, (offset_txagc[path] + hw_rate), (power_index & 0x3f)); + odm_write_1byte(dm, (offset_txagc[path] + hw_rate), (power_index & 0x3f)); #endif - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: path-%d rate index 0x%x (0x%x) = 0x%x\n", - __func__, path, hw_rate, (offset_txagc[path] + hw_rate), power_index)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__, + path, hw_rate, (offset_txagc[path] + hw_rate), power_index); return true; +#else + return false; +#endif } -void -phydm_init_hw_info_by_rfe_type_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +void phydm_init_hw_info_by_rfe_type_8821c(struct dm_struct *dm) { - p_dm_odm->is_init_hw_info_by_rfe = false; +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + dm->is_init_hw_info_by_rfe = false; + /* + * Let original variable rfe_type to be rfe_type_8821c. + * Varible rfe_type as symbol is used to identify PHY parameter. + */ + dm->rfe_type = dm->rfe_type_expand >> 3; + /*2.4G default rf set with wlg or btg*/ - if (p_dm_odm->rfe_type == 2 || p_dm_odm->rfe_type == 4 || p_dm_odm->rfe_type == 7) - p_dm_odm->default_rf_set_8821c = SWITCH_TO_BTG; - else if (p_dm_odm->rfe_type == 0 || p_dm_odm->rfe_type == 1 || p_dm_odm->rfe_type == 3 || p_dm_odm->rfe_type == 5 || p_dm_odm->rfe_type == 6) - p_dm_odm->default_rf_set_8821c = SWITCH_TO_WLG; - else if (p_dm_odm->rfe_type == 0x22 || p_dm_odm->rfe_type == 0x24 || p_dm_odm->rfe_type == 0x27) { - p_dm_odm->default_rf_set_8821c = SWITCH_TO_BTG; - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); - } else if (p_dm_odm->rfe_type == 0x20 || p_dm_odm->rfe_type == 0x21 || p_dm_odm->rfe_type == 0x23 || p_dm_odm->rfe_type == 0x25 || p_dm_odm->rfe_type == 0x26) { - p_dm_odm->default_rf_set_8821c = SWITCH_TO_WLG; - odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + if (dm->rfe_type_expand == 2 || dm->rfe_type_expand == 4 || dm->rfe_type_expand == 7) { + dm->default_rf_set_8821c = SWITCH_TO_BTG; + } else if (dm->rfe_type_expand == 0 || dm->rfe_type_expand == 1 || + dm->rfe_type_expand == 3 || dm->rfe_type_expand == 5 || + dm->rfe_type_expand == 6) { + dm->default_rf_set_8821c = SWITCH_TO_WLG; + } else if (dm->rfe_type_expand == 0x22 || dm->rfe_type_expand == 0x24 || + dm->rfe_type_expand == 0x27 || dm->rfe_type_expand == 0x2a || + dm->rfe_type_expand == 0x2c || dm->rfe_type_expand == 0x2f) { + dm->default_rf_set_8821c = SWITCH_TO_BTG; + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1); + } else if (dm->rfe_type_expand == 0x20 || dm->rfe_type_expand == 0x21 || + dm->rfe_type_expand == 0x23 || dm->rfe_type_expand == 0x25 || + dm->rfe_type_expand == 0x26 || dm->rfe_type_expand == 0x28 || + dm->rfe_type_expand == 0x29 || dm->rfe_type_expand == 0x2b || + dm->rfe_type_expand == 0x2d || dm->rfe_type_expand == 0x2e) { + dm->default_rf_set_8821c = SWITCH_TO_WLG; + odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1); } - if (p_dm_odm->rfe_type == 3 || p_dm_odm->rfe_type == 4 || p_dm_odm->rfe_type == 0x23 || p_dm_odm->rfe_type == 0x24) - p_dm_odm->default_ant_num_8821c = SWITCH_TO_ANT2; + if (dm->rfe_type_expand == 3 || dm->rfe_type_expand == 4 || + dm->rfe_type_expand == 0x23 || dm->rfe_type_expand == 0x24 || + dm->rfe_type_expand == 0x2b || dm->rfe_type_expand == 0x2c) + dm->default_ant_num_8821c = SWITCH_TO_ANT2; else - p_dm_odm->default_ant_num_8821c = SWITCH_TO_ANT1; + dm->default_ant_num_8821c = SWITCH_TO_ANT1; - p_dm_odm->is_init_hw_info_by_rfe = true; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: RFE type (%d), rf set (%s)\n", __FUNCTION__, p_dm_odm->rfe_type, (p_dm_odm->default_rf_set_8821c == 0 ? "BTG" : "WLG"))); + dm->is_init_hw_info_by_rfe = true; + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: RFE type (%d), rf set (%s)\n", + __FUNCTION__, dm->rfe_type_expand, + dm->default_rf_set_8821c == 0 ? "BTG" : "WLG"); +#endif } -void -phydm_set_gnt_state_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - boolean gnt_wl_state, - boolean gnt_bt_state -) +__iram_odm_func__ +void phydm_set_gnt_state_8821c(struct dm_struct *dm, boolean gnt_wl_state, + boolean gnt_bt_state) { - u32 gnt_val = 0; +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + u32 gnt_val = 0; - odm_set_mac_reg(p_dm_odm, 0x70, BIT(26), 0x1); + odm_set_bb_reg(dm, R_0x70, BIT(26), 0x1); if (gnt_wl_state) gnt_val = 0x3300; @@ -363,71 +388,58 @@ phydm_set_gnt_state_8821c( else gnt_val = gnt_val | 0x4400; - odm_set_mac_reg(p_dm_odm, 0x1704, MASKLWORD, gnt_val); + odm_set_bb_reg(dm, R_0x1704, MASKLWORD, gnt_val); ODM_delay_us(50); /*waiting before access 0x1700 */ - odm_set_mac_reg(p_dm_odm, 0x1700, MASKDWORD, 0xc00f0038); + odm_set_bb_reg(dm, R_0x1700, MASKDWORD, 0xc00f0038); +#endif } /* ======================================================================== */ /* ======================================================================== */ /* These following functions can be used by driver*/ -u32 -config_phydm_read_rf_reg_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e rf_path, - u32 reg_addr, - u32 bit_mask -) +__iram_odm_func__ +u32 config_phydm_read_rf_reg_8821c(struct dm_struct *dm, enum rf_path path, + u32 reg_addr, u32 bit_mask) { - u32 readback_value, direct_addr; - u32 offset_read_rf[2] = {0x2800, 0x2c00}; - u32 power_RF[2] = {0x1c, 0xec}; + u32 readback_value, direct_addr; + u32 offset_read_rf[2] = {0x2800, 0x2c00}; /* Error handling.*/ - if (rf_path > ODM_RF_PATH_A) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, rf_path)); - return INVALID_RF_DATA; - } - - /* Error handling. Check if RF power is enable or not */ - /* 0xffffffff means RF power is disable */ - if (odm_get_mac_reg(p_dm_odm, power_RF[rf_path], MASKBYTE3) != 0x7) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Read fail, RF is disabled\n", __func__)); + if (path > RF_PATH_A) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n", + __func__, path); return INVALID_RF_DATA; } /* Calculate offset */ reg_addr &= 0xff; - direct_addr = offset_read_rf[rf_path] + (reg_addr << 2); + direct_addr = offset_read_rf[path] + (reg_addr << 2); /* RF register only has 20bits */ bit_mask &= RFREGOFFSETMASK; /* Read RF register directly */ - readback_value = odm_get_bb_reg(p_dm_odm, direct_addr, bit_mask); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", - __func__, rf_path, reg_addr, readback_value, bit_mask)); + readback_value = odm_get_bb_reg(dm, direct_addr, bit_mask); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", __func__, path, + reg_addr, readback_value, bit_mask); return readback_value; } +__iram_odm_func__ boolean -config_phydm_write_rf_reg_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e rf_path, - u32 reg_addr, - u32 bit_mask, - u32 data -) +config_phydm_write_rf_reg_8821c(struct dm_struct *dm, enum rf_path path, + u32 reg_addr, u32 bit_mask, u32 data) { - u32 data_and_addr = 0, data_original = 0; - u32 offset_write_rf[2] = {0xc90, 0xe90}; - u32 power_RF[2] = {0x1c, 0xec}; - u8 bit_shift; + u32 data_and_addr = 0, data_original = 0; + u32 offset_write_rf[2] = {0xc90, 0xe90}; + u8 bit_shift; /* Error handling.*/ - if (rf_path > ODM_RF_PATH_A) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, rf_path)); + if (path > RF_PATH_A) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n", + __func__, path); return false; } @@ -436,11 +448,13 @@ config_phydm_write_rf_reg_8821c( bit_mask = bit_mask & RFREGOFFSETMASK; if (bit_mask != RFREGOFFSETMASK) { - data_original = config_phydm_read_rf_reg_8821c(p_dm_odm, rf_path, reg_addr, RFREGOFFSETMASK); + data_original = config_phydm_read_rf_reg_8821c(dm, path, reg_addr, RFREGOFFSETMASK); /* Error handling. RF is disabled */ if (config_phydm_read_rf_check_8821c(data_original) == false) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Write fail, RF is disable\n", __func__)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Write fail, RF is disable\n", + __func__); return false; } @@ -450,209 +464,225 @@ config_phydm_write_rf_reg_8821c( if (((bit_mask >> bit_shift) & 0x1) == 1) break; } - data = ((data_original)&(~bit_mask)) | (data << bit_shift); + data = ((data_original) & (~bit_mask)) | (data << bit_shift); } - } else if (odm_get_mac_reg(p_dm_odm, power_RF[rf_path], MASKBYTE3) != 0x7) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Write fail, RF is disabled\n", __func__)); - return false; } /* Put write addr in [27:20] and write data in [19:00] */ data_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff; /* Write operation */ - odm_set_bb_reg(p_dm_odm, offset_write_rf[rf_path], MASKDWORD, data_and_addr); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", - __func__, rf_path, reg_addr, data, data_original, bit_mask)); + odm_set_bb_reg(dm, offset_write_rf[path], MASKDWORD, data_and_addr); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", + __func__, path, reg_addr, data, data_original, bit_mask); + +#if (defined(CONFIG_RUN_IN_DRV)) + if (dm->support_interface == ODM_ITRF_PCIE) + ODM_delay_us(13); +#elif (defined(CONFIG_RUN_IN_FW)) + ODM_delay_us(13); +#endif + return true; } +__iram_odm_func__ boolean -config_phydm_write_txagc_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 power_index, - enum odm_rf_radio_path_e path, - u8 hw_rate -) +config_phydm_write_txagc_8821c(struct dm_struct *dm, u32 power_index, + enum rf_path path, u8 hw_rate) { - u32 offset_txagc[2] = {0x1d00, 0x1d80}; - u8 rate_idx = (hw_rate & 0xfc), i; - u32 txagc_content = 0x0; +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + u32 offset_txagc[2] = {0x1d00, 0x1d80}; + u8 rate_idx = (hw_rate & 0xfc); /* Input need to be HW rate index, not driver rate index!!!! */ - if (p_dm_odm->is_disable_phy_api) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + if (dm->is_disable_phy_api) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: disable PHY API for debug!!\n", __func__); return true; } /* Error handling */ - if ((path > ODM_RF_PATH_A) || (hw_rate > 0x53)) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, path)); + if (path > RF_PATH_A || hw_rate > 0x53) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n", + __func__, path); return false; } /* driver need to construct a 4-byte power index */ - odm_set_bb_reg(p_dm_odm, (offset_txagc[path] + rate_idx), MASKDWORD, power_index); + odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD, power_index); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: path-%d rate index 0x%x (0x%x) = 0x%x\n", - __func__, path, hw_rate, (offset_txagc[path] + hw_rate), power_index)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__, + path, hw_rate, (offset_txagc[path] + hw_rate), power_index); return true; +#else + return false; +#endif } -u8 -config_phydm_read_txagc_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e path, - u8 hw_rate -) +__iram_odm_func__ +u8 config_phydm_read_txagc_8821c(struct dm_struct *dm, enum rf_path path, + u8 hw_rate) { - u8 read_back_data; +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + u8 read_back_data; /* Input need to be HW rate index, not driver rate index!!!! */ /* Error handling */ - if ((path > ODM_RF_PATH_A) || (hw_rate > 0x53)) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, path)); + if (path > RF_PATH_A || hw_rate > 0x53) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: unsupported path (%d)\n", + __func__, path); return INVALID_TXAGC_DATA; } /* Disable TX AGC report */ - odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x0); /* need to check */ + odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x0); /* need to check */ /* Set data rate index (bit0~6) and path index (bit7) */ - odm_set_bb_reg(p_dm_odm, 0x1998, MASKBYTE0, (hw_rate | (path << 7))); + odm_set_bb_reg(dm, R_0x1998, MASKBYTE0, (hw_rate | (path << 7))); /* Enable TXAGC report */ - odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x1); + odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x1); /* Read TX AGC report */ - read_back_data = (u8)odm_get_bb_reg(p_dm_odm, 0xd30, 0x7f0000); + read_back_data = (u8)odm_get_bb_reg(dm, R_0xd30, 0x7f0000); /* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */ - odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x1998, BIT(16), 0x0); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: path-%d rate index 0x%x = 0x%x\n", __func__, path, hw_rate, read_back_data)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: path-%d rate index 0x%x = 0x%x\n", + __func__, path, hw_rate, read_back_data); return read_back_data; +#else + return 0; +#endif } +__iram_odm_func__ boolean -config_phydm_switch_band_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 central_ch -) +config_phydm_switch_band_8821c(struct dm_struct *dm, u8 central_ch) { - u32 rf_reg18; - boolean rf_reg_status = true; + u32 rf_reg18; + boolean rf_reg_status = true; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]======================>\n", __func__)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]======================>\n", + __func__); - if (p_dm_odm->is_disable_phy_api) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + if (dm->is_disable_phy_api) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: disable PHY API for debug!!\n", __func__); return true; } - rf_reg18 = config_phydm_read_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + rf_reg18 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK); rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); if (central_ch <= 14) { /* 2.4G */ /* Enable CCK block */ - odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0x1); + odm_set_bb_reg(dm, R_0x808, BIT(28), 0x1); /* Disable MAC CCK check */ - odm_set_bb_reg(p_dm_odm, 0x454, BIT(7), 0x0); + odm_set_bb_reg(dm, R_0x454, BIT(7), 0x0); /* Disable BB CCK check */ - odm_set_bb_reg(p_dm_odm, 0xa80, BIT(18), 0x0); + odm_set_bb_reg(dm, R_0xa80, BIT(18), 0x0); /*CCA Mask*/ - odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 15); /*default value*/ + odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 15); /*default value*/ /* RF band */ rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8)))); - +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) /* Switch WLG/BTG*/ - if (p_dm_odm->default_rf_set_8821c == SWITCH_TO_BTG) - config_phydm_switch_rf_set_8821c(p_dm_odm, SWITCH_TO_BTG); - else if (p_dm_odm->default_rf_set_8821c == SWITCH_TO_WLG) - config_phydm_switch_rf_set_8821c(p_dm_odm, SWITCH_TO_WLG); - + if (dm->default_rf_set_8821c == SWITCH_TO_BTG) + config_phydm_switch_rf_set_8821c(dm, SWITCH_TO_BTG); + else if (dm->default_rf_set_8821c == SWITCH_TO_WLG) + config_phydm_switch_rf_set_8821c(dm, SWITCH_TO_WLG); +#endif /*RF TXA_TANK LUT mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, BIT(6), 0x1); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, BIT(6), 0x1); /*RF TXA_PA_TANK*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x64, 0x0000f, 0xf); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x64, 0x0000f, 0xf); } else if (central_ch > 35) { /* 5G */ /* Enable BB CCK check */ - odm_set_bb_reg(p_dm_odm, 0xa80, BIT(18), 0x1); + odm_set_bb_reg(dm, R_0xa80, BIT(18), 0x1); /* Enable CCK check */ - odm_set_bb_reg(p_dm_odm, 0x454, BIT(7), 0x1); + odm_set_bb_reg(dm, R_0x454, BIT(7), 0x1); /* Disable CCK block */ - odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0x0); + odm_set_bb_reg(dm, R_0x808, BIT(28), 0x0); /*CCA Mask*/ - odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 15); /*default value*/ - /*odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 34); CCA mask = 13.6us*/ + odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 15); /*default value*/ + /*odm_set_bb_reg(dm, R_0x814, 0x0000FC00, 34); CCA mask = 13.6us*/ /* RF band */ rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8)))); rf_reg18 = (rf_reg18 | BIT(8) | BIT(16)); - +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) /* Switch WLA */ - config_phydm_switch_rf_set_8821c(p_dm_odm, SWITCH_TO_WLA); - + config_phydm_switch_rf_set_8821c(dm, SWITCH_TO_WLA); +#endif /*RF TXA_TANK LUT mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, BIT(6), 0x0); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, BIT(6), 0x0); } else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d)\n", __func__, central_ch)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Fail to switch band (ch: %d)\n", __func__, + central_ch); return false; } - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18); - if (phydm_rfe_8821c(p_dm_odm, central_ch) == false) + if (phydm_rfe_8821c(dm, central_ch) == false) return false; - if (rf_reg_status == false) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d), because writing RF register is fail\n", __func__, central_ch)); + if (!rf_reg_status) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Fail to switch band (ch: %d), because writing RF register is fail\n", + __func__, central_ch); return false; } - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch band (ch: %d)\n", __func__, central_ch)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: Success to switch band (ch: %d)\n", + __func__, central_ch); return true; } +__iram_odm_func__ boolean -config_phydm_switch_channel_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 central_ch -) +config_phydm_switch_channel_8821c(struct dm_struct *dm, u8 central_ch) { - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u32 rf_reg18, rf_reg_b8 = 0; - boolean rf_reg_status = true; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u32 rf_reg18, rf_reg_b8 = 0; + boolean rf_reg_status = true; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]====================>\n", __func__)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]====================>\n", __func__); - if (p_dm_odm->is_disable_phy_api) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + if (dm->is_disable_phy_api) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: disable PHY API for debug!!\n", __func__); return true; } central_ch_8821c = central_ch; - rf_reg18 = config_phydm_read_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + rf_reg18 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK); rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); - if (p_dm_odm->cut_version == ODM_CUT_A) { - rf_reg_b8 = config_phydm_read_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0xb8, RFREGOFFSETMASK); + if (dm->cut_version == ODM_CUT_A) { + rf_reg_b8 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0xb8, RFREGOFFSETMASK); rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg_b8); } @@ -665,25 +695,25 @@ config_phydm_switch_channel_8821c( rf_reg18 = (rf_reg18 | central_ch); /* 2. AGC table selection */ - odm_set_bb_reg(p_dm_odm, 0xc1c, 0x00000F00, 0x0); - p_dm_dig_table->agc_table_idx = 0x0; + odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x0); + dig_t->agc_table_idx = 0x0; /* 3. Set central frequency for clock offset tracking */ - odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x96a); + odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x96a); /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ - if (p_dm_odm->cut_version == ODM_CUT_A) + if (dm->cut_version == ODM_CUT_A) rf_reg_b8 = rf_reg_b8 | BIT(19); /* CCK TX filter parameters */ if (central_ch == 14) { - odm_set_bb_reg(p_dm_odm, 0xa24, MASKDWORD, 0x0000b81c); - odm_set_bb_reg(p_dm_odm, 0xa28, MASKLWORD, 0x0000); - odm_set_bb_reg(p_dm_odm, 0xaac, MASKDWORD, 0x00003667); + odm_set_bb_reg(dm, R_0xa24, MASKDWORD, 0x0000b81c); + odm_set_bb_reg(dm, R_0xa28, MASKLWORD, 0x0000); + odm_set_bb_reg(dm, R_0xaac, MASKDWORD, 0x00003667); } else { - odm_set_bb_reg(p_dm_odm, 0xa24, MASKDWORD, rega24_8821c); - odm_set_bb_reg(p_dm_odm, 0xa28, MASKLWORD, (rega28_8821c & MASKLWORD)); - odm_set_bb_reg(p_dm_odm, 0xaac, MASKDWORD, regaac_8821c); + odm_set_bb_reg(dm, R_0xa24, MASKDWORD, rega24_8821c); + odm_set_bb_reg(dm, R_0xa28, MASKLWORD, (rega28_8821c & MASKLWORD)); + odm_set_bb_reg(dm, R_0xaac, MASKDWORD, regaac_8821c); } } else if (central_ch > 35) { @@ -693,145 +723,183 @@ config_phydm_switch_channel_8821c( rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0))); rf_reg18 = (rf_reg18 | central_ch); - if (central_ch >= 36 && central_ch <= 64) + if (central_ch >= 36 && central_ch <= 64) { ; - else if ((central_ch >= 100) && (central_ch <= 140)) + } else if ((central_ch >= 100) && (central_ch <= 140)) { rf_reg18 = (rf_reg18 | BIT(17)); - else if (central_ch > 140) + } else if (central_ch > 140) { rf_reg18 = (rf_reg18 | BIT(18)); - else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (RF18) (ch: %d)\n", __func__, central_ch)); + } else { + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Fail to switch channel (RF18) (ch: %d)\n", + __func__, central_ch); return false; } /* 2. AGC table selection */ - if ((central_ch >= 36) && (central_ch <= 64)) { - odm_set_bb_reg(p_dm_odm, 0xc1c, 0x00000F00, 0x1); - p_dm_dig_table->agc_table_idx = 0x1; + if (central_ch >= 36 && central_ch <= 64) { + odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x1); + dig_t->agc_table_idx = 0x1; } else if ((central_ch >= 100) && (central_ch <= 144)) { - odm_set_bb_reg(p_dm_odm, 0xc1c, 0x00000F00, 0x2); - p_dm_dig_table->agc_table_idx = 0x2; + odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x2); + dig_t->agc_table_idx = 0x2; } else if (central_ch >= 149) { - odm_set_bb_reg(p_dm_odm, 0xc1c, 0x00000F00, 0x3); - p_dm_dig_table->agc_table_idx = 0x3; + odm_set_bb_reg(dm, R_0xc1c, 0x00000F00, 0x3); + dig_t->agc_table_idx = 0x3; } else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (AGC) (ch: %d)\n", __func__, central_ch)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Fail to switch channel (AGC) (ch: %d)\n", + __func__, central_ch); return false; } /* 3. Set central frequency for clock offset tracking */ - if ((central_ch >= 36) && (central_ch <= 48)) - odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x494); - else if ((central_ch >= 52) && (central_ch <= 64)) - odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x453); - else if ((central_ch >= 100) && (central_ch <= 116)) - odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x452); - else if ((central_ch >= 118) && (central_ch <= 177)) - odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x412); - else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (fc_area) (ch: %d)\n", __func__, central_ch)); + if (central_ch >= 36 && central_ch <= 48) { + odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x494); + } else if ((central_ch >= 52) && (central_ch <= 64)) { + odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x453); + } else if ((central_ch >= 100) && (central_ch <= 116)) { + odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x452); + } else if ((central_ch >= 118) && (central_ch <= 177)) { + odm_set_bb_reg(dm, R_0x860, 0x1ffe0000, 0x412); + } else { + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Fail to switch channel (fc_area) (ch: %d)\n", + __func__, central_ch); return false; } /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ - if (p_dm_odm->cut_version == ODM_CUT_A) { - if ((central_ch >= 57) && (central_ch <= 75)) + if (dm->cut_version == ODM_CUT_A) { + if (central_ch >= 57 && central_ch <= 75) rf_reg_b8 = rf_reg_b8 & (~BIT(19)); else rf_reg_b8 = rf_reg_b8 | BIT(19); } +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + /*notch 5760 spur by CSI_MASK*/ + if (central_ch == 153) + phydm_csi_mask_setting(dm, FUNC_ENABLE, (u32)central_ch, 20, 5760, PHYDM_DONT_CARE); + else if (central_ch == 151) + phydm_csi_mask_setting(dm, FUNC_ENABLE, (u32)central_ch, 40, 5760, PHYDM_DONT_CARE); + else if (central_ch == 155) + phydm_csi_mask_setting(dm, FUNC_ENABLE, (u32)central_ch, 80, 5760, PHYDM_DONT_CARE); + else + phydm_csi_mask_setting(dm, FUNC_DISABLE, (u32)central_ch, 80, 5760, PHYDM_DONT_CARE); +#endif + } else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d)\n", __func__, central_ch)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Fail to switch band (ch: %d)\n", __func__, + central_ch); return false; } - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18); - if (p_dm_odm->cut_version == ODM_CUT_A) - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0xb8, RFREGOFFSETMASK, rf_reg_b8); + if (dm->cut_version == ODM_CUT_A) + odm_set_rf_reg(dm, RF_PATH_A, RF_0xb8, RFREGOFFSETMASK, rf_reg_b8); - if (rf_reg_status == false) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (ch: %d), because writing RF register is fail\n", __func__, central_ch)); + if (!rf_reg_status) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Fail to switch channel (ch: %d), because writing RF register is fail\n", + __func__, central_ch); return false; } - phydm_ccapar_8821c(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch channel (ch: %d)\n", __func__, central_ch)); + phydm_ccapar_8821c(dm); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Success to switch channel (ch: %d)\n", __func__, + central_ch); return true; } +__iram_odm_func__ boolean -config_phydm_switch_bandwidth_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 primary_ch_idx, - enum odm_bw_e bandwidth -) +config_phydm_switch_bandwidth_8821c(struct dm_struct *dm, u8 primary_ch_idx, + enum channel_width bandwidth) { - u32 rf_reg18; - boolean rf_reg_status = true; + u32 rf_reg18; + boolean rf_reg_status = true; + u32 bb_reg8ac; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]===================>\n", __func__)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]===================>\n", __func__); - if (p_dm_odm->is_disable_phy_api) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + if (dm->is_disable_phy_api) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: disable PHY API for debug!!\n", __func__); return true; } /* Error handling */ - if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); + if (bandwidth >= CHANNEL_WIDTH_MAX || (bandwidth == CHANNEL_WIDTH_40 && primary_ch_idx > 2) || (bandwidth == CHANNEL_WIDTH_80 && primary_ch_idx > 4)) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n", + __func__, bandwidth, primary_ch_idx); return false; } + /*Make protection*/ + if (central_ch_8821c == 165 && !(*dm->mp_mode)) + bandwidth = CHANNEL_WIDTH_20; bw_8821c = bandwidth; - rf_reg18 = config_phydm_read_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + rf_reg18 = config_phydm_read_rf_reg_8821c(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK); rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); /* Switch bandwidth */ switch (bandwidth) { - case ODM_BW20M: - { - /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, ODM_BW20M); + case CHANNEL_WIDTH_20: { +/* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ +#if 0 + odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, CHANNEL_WIDTH_20); /* ADC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x1); + odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x0); + odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x1); /* DAC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x1); + odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x0); + odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x1); +#endif + bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD); + bb_reg8ac &= 0xffcffc00; + bb_reg8ac |= 0x10010000; + odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac); /* ADC buffer clock */ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); + odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1); /* RF bandwidth */ rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); break; } - case ODM_BW40M: - { + case CHANNEL_WIDTH_40: { /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */ - odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | ODM_BW40M)); + /*odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_40));*/ /* CCK primary channel */ if (primary_ch_idx == 1) - odm_set_bb_reg(p_dm_odm, 0xa00, BIT(4), primary_ch_idx); + odm_set_bb_reg(dm, R_0xa00, BIT(4), primary_ch_idx); else - odm_set_bb_reg(p_dm_odm, 0xa00, BIT(4), 0); - + odm_set_bb_reg(dm, R_0xa00, BIT(4), 0); +#if 0 /* ADC clock = 160M clock for BW40 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(11) | BIT(10)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(17), 0x1); + odm_set_bb_reg(dm, R_0x8ac, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(dm, R_0x8ac, BIT(17), 0x1); /* DAC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(23) | BIT(22)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(29), 0x1); + odm_set_bb_reg(dm, R_0x8ac, (BIT(23) | BIT(22)), 0x0); + odm_set_bb_reg(dm, R_0x8ac, BIT(29), 0x1); +#endif + bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD); + bb_reg8ac &= 0xff3ff300; + bb_reg8ac |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_40; + odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac); /* ADC buffer clock */ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); + odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1); /* RF bandwidth */ rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10)))); @@ -839,21 +907,26 @@ config_phydm_switch_bandwidth_8821c( break; } - case ODM_BW80M: - { - /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */ - odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | ODM_BW80M)); + case CHANNEL_WIDTH_80: { +/* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */ +#if 0 + odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_80)); /* ADC clock = 160M clock for BW80 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(13) | BIT(12)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(18), 0x1); + odm_set_bb_reg(dm, R_0x8ac, (BIT(13) | BIT(12)), 0x0); + odm_set_bb_reg(dm, R_0x8ac, BIT(18), 0x1); /* DAC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(25) | BIT(24)), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(30), 0x1); + odm_set_bb_reg(dm, R_0x8ac, (BIT(25) | BIT(24)), 0x0); + odm_set_bb_reg(dm, R_0x8ac, BIT(30), 0x1); +#endif + bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD); + bb_reg8ac &= 0xfcffcf00; + bb_reg8ac |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | CHANNEL_WIDTH_80; + odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac); /* ADC buffer clock */ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); + odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x1); /* RF bandwidth */ rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10)))); @@ -861,44 +934,54 @@ config_phydm_switch_bandwidth_8821c( break; } - case ODM_BW5M: - { - /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (BIT(6) | ODM_BW20M)); + case CHANNEL_WIDTH_5: { +/* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ +#if 0 + odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (BIT(6) | CHANNEL_WIDTH_20)); /* ADC clock = 40M clock */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x2); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x2); + odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x0); /* DAC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x2); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x0); + odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x2); + odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x0); +#endif + bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD); + bb_reg8ac &= 0xefcefc00; + bb_reg8ac |= (0x2 << 20) | (0x2 << 8) | BIT(6); + odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac); /* ADC buffer clock */ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8c8, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x0); + odm_set_bb_reg(dm, R_0x8c8, BIT(31), 0x1); /* RF bandwidth */ rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); break; } - case ODM_BW10M: - { - /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ - odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (BIT(7) | ODM_BW20M)); + case CHANNEL_WIDTH_10: { +/* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ +#if 0 + odm_set_bb_reg(dm, R_0x8ac, MASKBYTE0, (BIT(7) | CHANNEL_WIDTH_20)); /* ADC clock = 80M clock */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x3); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x8ac, (BIT(9) | BIT(8)), 0x3); + odm_set_bb_reg(dm, R_0x8ac, BIT(16), 0x0); /* DAC clock = 160M clock for BW20 */ - odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x3); - odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x0); + odm_set_bb_reg(dm, R_0x8ac, (BIT(21) | BIT(20)), 0x3); + odm_set_bb_reg(dm, R_0x8ac, BIT(28), 0x0); +#endif + bb_reg8ac = odm_get_bb_reg(dm, R_0x8ac, MASKDWORD); + bb_reg8ac &= 0xefcefc00; + bb_reg8ac |= (0x3 << 20) | (0x3 << 8) | BIT(7); + odm_set_bb_reg(dm, R_0x8ac, MASKDWORD, bb_reg8ac); /* ADC buffer clock */ - odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x0); - odm_set_bb_reg(p_dm_odm, 0x8c8, BIT(31), 0x1); + odm_set_bb_reg(dm, R_0x8c4, BIT(30), 0x0); + odm_set_bb_reg(dm, R_0x8c8, BIT(31), 0x1); /* RF bandwidth */ rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); @@ -906,158 +989,168 @@ config_phydm_switch_bandwidth_8821c( break; } default: - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n", + __func__, bandwidth, primary_ch_idx); } /* Write RF register */ - rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK, rf_reg18); - if (rf_reg_status == false) { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", __func__, bandwidth, primary_ch_idx)); + if (!rf_reg_status) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", + __func__, bandwidth, primary_ch_idx); return false; } /* Modify RX DFIR parameters */ - phydm_rxdfirpar_by_bw_8821c(p_dm_odm, bandwidth); + phydm_rxdfirpar_by_bw_8821c(dm, bandwidth); /* Modify CCA parameters */ - phydm_ccapar_by_bw_8821c(p_dm_odm, bandwidth); - phydm_ccapar_8821c(p_dm_odm); + phydm_ccapar_by_bw_8821c(dm, bandwidth); + phydm_ccapar_8821c(dm); /* Toggle RX path to avoid RX dead zone issue */ - /*odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, 0x0);*/ - /*odm_set_bb_reg(p_dm_odm, 0x808, MASKBYTE0, 0x11);*/ - + /*odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x0);*/ + /*odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x11);*/ - - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Success to switch bandwidth (bw: %d, primary ch: %d)\n", + __func__, bandwidth, primary_ch_idx); return true; } +__iram_odm_func__ boolean -config_phydm_switch_channel_bw_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 central_ch, - u8 primary_ch_idx, - enum odm_bw_e bandwidth -) +config_phydm_switch_channel_bw_8821c(struct dm_struct *dm, u8 central_ch, + u8 primary_ch_idx, + enum channel_width bandwidth) { - u8 e_rf_path = 0; - u32 rf_val_to_wr, rf_tmp_val, bit_shift, bit_mask; - /* Switch band */ - if (config_phydm_switch_band_8821c(p_dm_odm, central_ch) == false) + if (config_phydm_switch_band_8821c(dm, central_ch) == false) return false; /* Switch channel */ - if (config_phydm_switch_channel_8821c(p_dm_odm, central_ch) == false) + if (config_phydm_switch_channel_8821c(dm, central_ch) == false) return false; /* Switch bandwidth */ - if (config_phydm_switch_bandwidth_8821c(p_dm_odm, primary_ch_idx, bandwidth) == false) + if (config_phydm_switch_bandwidth_8821c(dm, primary_ch_idx, bandwidth) == false) return false; return true; } +__iram_odm_func__ boolean -config_phydm_trx_mode_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_path_e tx_path, - enum odm_rf_path_e rx_path, - boolean is_tx2_path -) +config_phydm_trx_mode_8821c(struct dm_struct *dm, enum bb_path tx_path, + enum bb_path rx_path, boolean is_tx2_path) { return true; } +__iram_odm_func__ boolean -config_phydm_parameter_init_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_parameter_init_e type -) +config_phydm_parameter_init_8821c(struct dm_struct *dm, + enum odm_parameter_init type) { if (type == ODM_PRE_SETTING) { - odm_set_bb_reg(p_dm_odm, 0x808, (BIT(28) | BIT(29)), 0x0); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Pre setting: disable OFDM and CCK block\n", __func__)); + odm_set_bb_reg(dm, R_0x808, (BIT(28) | BIT(29)), 0x0); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Pre setting: disable OFDM and CCK block\n", + __func__); } else if (type == ODM_POST_SETTING) { - odm_set_bb_reg(p_dm_odm, 0x808, (BIT(28) | BIT(29)), 0x3); - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Post setting: enable OFDM and CCK block\n", __func__)); - reg82c_8821c = odm_get_bb_reg(p_dm_odm, 0x82c, MASKDWORD); - reg838_8821c = odm_get_bb_reg(p_dm_odm, 0x838, MASKDWORD); - reg830_8821c = odm_get_bb_reg(p_dm_odm, 0x830, MASKDWORD); - rega24_8821c = odm_get_bb_reg(p_dm_odm, 0xa24, MASKDWORD); - rega28_8821c = odm_get_bb_reg(p_dm_odm, 0xa28, MASKDWORD); - regaac_8821c = odm_get_bb_reg(p_dm_odm, 0xaac, MASKDWORD); + odm_set_bb_reg(dm, R_0x808, (BIT(28) | BIT(29)), 0x3); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "[%s]: Post setting: enable OFDM and CCK block\n", + __func__); + rega24_8821c = odm_get_bb_reg(dm, R_0xa24, MASKDWORD); + rega28_8821c = odm_get_bb_reg(dm, R_0xa28, MASKDWORD); + regaac_8821c = odm_get_bb_reg(dm, R_0xaac, MASKDWORD); +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + } else if (type == ODM_INIT_FW_SETTING) { + u8 h2c_content[4] = {0}; + + h2c_content[0] = dm->rfe_type_expand; + h2c_content[1] = dm->rf_type; + h2c_content[2] = dm->cut_version; + h2c_content[3] = (dm->tx_ant_status << 4) | dm->rx_ant_status; + + odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_GENERAL_INIT, 4, h2c_content); +#endif } else { - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Wrong type!!\n", __func__)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: Wrong type!!\n", __func__); return false; } return true; } -void -config_phydm_switch_rf_set_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 rf_set -) +__iram_odm_func__ +void config_phydm_switch_rf_set_8821c(struct dm_struct *dm, u8 rf_set) { +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *p_adapter = p_dm_odm->adapter; - PMGNT_INFO p_mgnt_info = &(p_adapter->MgntInfo); + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo); #endif - u32 bb_reg32; + u32 bb_reg32; - odm_set_mac_reg(p_dm_odm, 0x1080, BIT(16), 0x1); - odm_set_mac_reg(p_dm_odm, 0x00, BIT(26), 0x1); - /*odm_set_mac_reg(p_dm_odm, 0x70, BIT(26), 0x1);*/ - /*odm_set_mac_reg(p_dm_odm, 0x1704, MASKLWORD, 0x4000);*/ - /*odm_set_mac_reg(p_dm_odm, 0x1700, (BIT(31) | BIT(30)), 0x3); */ + odm_set_bb_reg(dm, R_0x1080, BIT(16), 0x1); + odm_set_bb_reg(dm, R_0x00, BIT(26), 0x1); + /*odm_set_mac_reg(dm, R_0x70, BIT(26), 0x1);*/ + /*odm_set_mac_reg(dm, R_0x1704, MASKLWORD, 0x4000);*/ + /*odm_set_mac_reg(dm, R_0x1700, (BIT(31) | BIT(30)), 0x3); */ - bb_reg32 = odm_get_bb_reg(p_dm_odm, 0xcb8, MASKDWORD); + bb_reg32 = odm_get_bb_reg(dm, R_0xcb8, MASKDWORD); switch (rf_set) { - case SWITCH_TO_BTG: - p_dm_odm->current_rf_set_8821c = SWITCH_TO_BTG; + dm->current_rf_set_8821c = SWITCH_TO_BTG; bb_reg32 = (bb_reg32 | BIT(16)); bb_reg32 &= (~(BIT(18) | BIT(20) | BIT(21) | BIT(22) | BIT(23))); + odm_set_bb_reg(dm, R_0xa84, MASKBYTE2, 0xe); + odm_set_bb_reg(dm, R_0xa80, MASKLWORD, 0xfc84); + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (p_dm_odm->mp_mode == true && p_mgnt_info->RegPHYParaFromFolder == 0) + if (*dm->mp_mode == true && mgnt_info->RegPHYParaFromFolder == 0) { #else - if (p_dm_odm->mp_mode == true) + if (*dm->mp_mode == true) { #endif - { - odm_config_bb_with_header_file(p_dm_odm, CONFIG_BB_AGC_TAB_DIFF); + odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x14); + odm_config_bb_with_header_file(dm, CONFIG_BB_AGC_TAB_DIFF); /*Toggle initial gain twice for valid gain table*/ - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), 0x22); - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), 0x20); + odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x22); + odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x20); } break; case SWITCH_TO_WLG: - p_dm_odm->current_rf_set_8821c = SWITCH_TO_WLG; + dm->current_rf_set_8821c = SWITCH_TO_WLG; bb_reg32 = (bb_reg32 | BIT(20) | BIT(21) | BIT(22)); bb_reg32 &= (~(BIT(16) | BIT(18) | BIT(23))); + odm_set_bb_reg(dm, R_0xa84, MASKBYTE2, 0x12); + odm_set_bb_reg(dm, R_0xa80, MASKLWORD, 0x7532); + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - if (p_dm_odm->mp_mode == true && p_mgnt_info->RegPHYParaFromFolder == 0) + if (*dm->mp_mode == true && mgnt_info->RegPHYParaFromFolder == 0) { #else - if (p_dm_odm->mp_mode == true) + if (*dm->mp_mode == true) { #endif - { - odm_config_bb_with_header_file(p_dm_odm, CONFIG_BB_AGC_TAB_DIFF); + odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x13); + odm_config_bb_with_header_file(dm, CONFIG_BB_AGC_TAB_DIFF); /*Toggle initial gain twice for valid gain table*/ - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), 0x22); - odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), 0x20); + odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x22); + odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), 0x20); } break; case SWITCH_TO_WLA: - p_dm_odm->current_rf_set_8821c = SWITCH_TO_WLA; + dm->current_rf_set_8821c = SWITCH_TO_WLA; bb_reg32 = (bb_reg32 | BIT(20) | BIT(22) | BIT(23)); bb_reg32 &= (~(BIT(16) | BIT(18) | BIT(21))); @@ -1065,185 +1158,213 @@ config_phydm_switch_rf_set_8821c( break; case SWITCH_TO_BT: - p_dm_odm->current_rf_set_8821c = SWITCH_TO_BT; + dm->current_rf_set_8821c = SWITCH_TO_BT; break; default: break; - } - odm_set_bb_reg(p_dm_odm, 0xcb8, MASKDWORD, bb_reg32); - + odm_set_bb_reg(dm, R_0xcb8, MASKDWORD, bb_reg32); +#endif } -void -config_phydm_set_ant_path( - struct PHY_DM_STRUCT *p_dm_odm, - u8 rf_set, - u8 ant_num -) +__iram_odm_func__ +void config_phydm_set_ant_path(struct dm_struct *dm, u8 rf_set, u8 ant_num) { - boolean switch_polarity_inverse = false; - u8 regval_0xcb7 = 0; +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + boolean switch_polarity_inverse = false; + u8 regval_0xcb7 = 0; - p_dm_odm->current_ant_num_8821c = ant_num; - config_phydm_switch_rf_set_8821c(p_dm_odm, rf_set); + dm->current_ant_num_8821c = ant_num; + config_phydm_switch_rf_set_8821c(dm, rf_set); if (rf_set == SWITCH_TO_BT) - phydm_set_gnt_state_8821c(p_dm_odm, false, true); /* GNT_WL=0, GNT_BT=1 for BT test */ + phydm_set_gnt_state_8821c(dm, false, true); /* GNT_WL=0, GNT_BT=1 for BT test */ else - phydm_set_gnt_state_8821c(p_dm_odm, true, false); /* GNT_WL=1, GNT_BT=0 for WL test */ + phydm_set_gnt_state_8821c(dm, true, false); /* GNT_WL=1, GNT_BT=0 for WL test */ - if (p_dm_odm->rfe_type == 0x5 || p_dm_odm->rfe_type == 0x6 || p_dm_odm->rfe_type == 0x25 || p_dm_odm->rfe_type == 0x26) /*switch does not exist*/ + /*switch does not exist*/ + if (dm->rfe_type_expand == 0x5 || dm->rfe_type_expand == 0x6 || + dm->rfe_type_expand == 0x25 || dm->rfe_type_expand == 0x26 || + dm->rfe_type_expand == 0x2a || dm->rfe_type_expand == 0x2d || + dm->rfe_type_expand == 0x2e) return; - if (p_dm_odm->current_ant_num_8821c) /*Ant1 = 0, Ant2 = 1*/ + if (dm->current_ant_num_8821c) /*Ant1 = 0, Ant2 = 1*/ switch_polarity_inverse = !switch_polarity_inverse; if (rf_set == SWITCH_TO_WLG) switch_polarity_inverse = !switch_polarity_inverse; /*set antenna control by WL 0xcb4[29:28]*/ - odm_set_mac_reg(p_dm_odm, 0x4c, BIT(24)|BIT(23), 0x2); + odm_set_bb_reg(dm, R_0x4c, BIT(24) | BIT(23), 0x2); /*set RFE_ctrl8 and RFE_ctrl9 as antenna control pins by software*/ - odm_set_bb_reg(p_dm_odm, 0xcb4, 0x000000ff, 0x77); + odm_set_bb_reg(dm, R_0xcb4, 0x000000ff, 0x77); /*0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0*/ - regval_0xcb7 = (switch_polarity_inverse == false ? 0x1 : 0x2); - - odm_set_bb_reg(p_dm_odm, 0xcb4, 0x30000000, regval_0xcb7); + regval_0xcb7 = (!switch_polarity_inverse ? 0x1 : 0x2); + odm_set_bb_reg(dm, R_0xcb4, 0x30000000, regval_0xcb7); +#endif } -u32 -query_phydm_trx_capability_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +u32 query_phydm_trx_capability_8821c(struct dm_struct *dm) { +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) u32 value32 = 0x00000000; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: trx_capability = 0x%x\n", __func__, value32)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: trx_capability = 0x%x\n", __func__, + value32); return value32; +#else + return 0; +#endif } -u32 -query_phydm_stbc_capability_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +u32 query_phydm_stbc_capability_8821c(struct dm_struct *dm) { +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) u32 value32 = 0x00010001; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: stbc_capability = 0x%x\n", __func__, value32)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: stbc_capability = 0x%x\n", + __func__, value32); return value32; +#else + return 0; +#endif } -u32 -query_phydm_ldpc_capability_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +u32 query_phydm_ldpc_capability_8821c(struct dm_struct *dm) { +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) u32 value32 = 0x01000100; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: ldpc_capability = 0x%x\n", __func__, value32)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: ldpc_capability = 0x%x\n", + __func__, value32); return value32; +#else + return 0; +#endif } -u32 -query_phydm_txbf_parameters_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +u32 query_phydm_txbf_parameters_8821c(struct dm_struct *dm) { +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) u32 value32 = 0x00030003; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: txbf_parameters = 0x%x\n", __func__, value32)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: txbf_parameters = 0x%x\n", + __func__, value32); return value32; +#else + return 0; +#endif } -u32 -query_phydm_txbf_capability_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +u32 query_phydm_txbf_capability_8821c(struct dm_struct *dm) { +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) u32 value32 = 0x01010001; - ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: txbf_capability = 0x%x\n", __func__, value32)); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "[%s]: txbf_capability = 0x%x\n", + __func__, value32); return value32; +#else + return 0; +#endif } -u8 -query_phydm_default_rf_set_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +u8 query_phydm_default_rf_set_8821c(struct dm_struct *dm) { - return p_dm_odm->default_rf_set_8821c; +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + return dm->default_rf_set_8821c; +#else + return 0; +#endif } -u8 -query_phydm_current_rf_set_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +u8 query_phydm_current_rf_set_8821c(struct dm_struct *dm) { - return p_dm_odm->current_rf_set_8821c; +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + return dm->current_rf_set_8821c; +#else + return 0; +#endif } -u8 -query_phydm_rfetype_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +u8 query_phydm_rfetype_8821c(struct dm_struct *dm) { - return p_dm_odm->rfe_type; +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + return dm->rfe_type_expand; +#else + return 0; +#endif } -u8 -query_phydm_current_ant_num_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +u8 query_phydm_current_ant_num_8821c(struct dm_struct *dm) { - u32 regval_0xcb4 = odm_get_bb_reg(p_dm_odm, 0xcb4, BIT(29)|BIT(28)); +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + u32 regval_0xcb4 = odm_get_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28)); - if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_BTG || p_dm_odm->current_rf_set_8821c == SWITCH_TO_WLA || p_dm_odm->current_rf_set_8821c == SWITCH_TO_BT) { + if (dm->current_rf_set_8821c == SWITCH_TO_BTG || dm->current_rf_set_8821c == SWITCH_TO_WLA || dm->current_rf_set_8821c == SWITCH_TO_BT) { if (regval_0xcb4 == 1) - p_dm_odm->current_ant_num_8821c = SWITCH_TO_ANT1; + dm->current_ant_num_8821c = SWITCH_TO_ANT1; else if (regval_0xcb4 == 2) - p_dm_odm->current_ant_num_8821c = SWITCH_TO_ANT2; - else - if (regval_0xcb4 == 1) - p_dm_odm->current_ant_num_8821c = SWITCH_TO_ANT2; + dm->current_ant_num_8821c = SWITCH_TO_ANT2; + else if (regval_0xcb4 == 1) + dm->current_ant_num_8821c = SWITCH_TO_ANT2; else if (regval_0xcb4 == 2) - p_dm_odm->current_ant_num_8821c = SWITCH_TO_ANT1; + dm->current_ant_num_8821c = SWITCH_TO_ANT1; } - return p_dm_odm->current_ant_num_8821c; + return dm->current_ant_num_8821c; +#else + return 0; +#endif } -u8 -query_phydm_ant_num_map_8821c( - struct PHY_DM_STRUCT *p_dm_odm -) +__iram_odm_func__ +u8 query_phydm_ant_num_map_8821c(struct dm_struct *dm) { - - u8 mapping_table = 0; +#if (PHYDM_FW_API_FUNC_ENABLE_8821C == 1) + u8 mapping_table = 0; /* mapping table meaning - 1: choose ant1 or ant2 - 2: only ant1 - 3: only ant2 - 4: cannot choose - */ - - if (p_dm_odm->rfe_type == 0 || p_dm_odm->rfe_type == 7 || p_dm_odm->rfe_type == 0x20 || p_dm_odm->rfe_type == 0x27) + * 1: choose ant1 or ant2 + * 2: only ant1 + * 3: only ant2 + * 4: cannot choose + */ + + if (dm->rfe_type_expand == 0 || dm->rfe_type_expand == 7 || dm->rfe_type_expand == 0x20 || + dm->rfe_type_expand == 0x27 || dm->rfe_type_expand == 0x28 || dm->rfe_type_expand == 0x2f) mapping_table = 1; - else if (p_dm_odm->rfe_type == 1 || p_dm_odm->rfe_type == 2 || p_dm_odm->rfe_type == 0x21 || p_dm_odm->rfe_type == 0x22) + else if (dm->rfe_type_expand == 1 || dm->rfe_type_expand == 2 || dm->rfe_type_expand == 0x21 || + dm->rfe_type_expand == 0x22 || dm->rfe_type_expand == 0x29 || dm->rfe_type_expand == 0x2a) mapping_table = 2; - else if (p_dm_odm->rfe_type == 3 || p_dm_odm->rfe_type == 4 || p_dm_odm->rfe_type == 0x23 || p_dm_odm->rfe_type == 0x24) + else if (dm->rfe_type_expand == 3 || dm->rfe_type_expand == 4 || dm->rfe_type_expand == 0x23 || + dm->rfe_type_expand == 0x24 || dm->rfe_type_expand == 0x2b || dm->rfe_type_expand == 0x2c) mapping_table = 3; - else if (p_dm_odm->rfe_type == 5 || p_dm_odm->rfe_type == 6 || p_dm_odm->rfe_type == 0x25 || p_dm_odm->rfe_type == 0x26) + else if (dm->rfe_type_expand == 5 || dm->rfe_type_expand == 6 || dm->rfe_type_expand == 0x25 || + dm->rfe_type_expand == 0x26 || dm->rfe_type_expand == 0x2d || dm->rfe_type_expand == 0x2e) mapping_table = 4; return mapping_table; +#else + return 0; +#endif } /* ======================================================================== */ -#endif /* RTL8821C_SUPPORT == 1 */ +#endif /*PHYDM_FW_API_ENABLE_8821C == 1*/ +#endif /* RTL8821C_SUPPORT == 1 */ diff --git a/hal/phydm/rtl8821c/phydm_hal_api8821c.h b/hal/phydm/rtl8821c/phydm_hal_api8821c.h index 9426c7d..39a3c7b 100644 --- a/hal/phydm/rtl8821c/phydm_hal_api8821c.h +++ b/hal/phydm/rtl8821c/phydm_hal_api8821c.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,204 +11,115 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_PHYDM_API_H_8821C__ #define __INC_PHYDM_API_H_8821C__ #if (RTL8821C_SUPPORT == 1) -#define PHY_CONFIG_VERSION_8821C "3.1.20" /*2016.11.21 (HW user guide version: R03, SW user guide version: R01, Modification: R20)*/ +#define PHY_CONFIG_VERSION_8821C "3.1.27" /*2017.08.08 (HW user guide version: R03, SW user guide version: R01, Modification: R27)*/ -#define INVALID_RF_DATA 0xffffffff -#define INVALID_TXAGC_DATA 0xff +#define INVALID_RF_DATA 0xffffffff +#define INVALID_TXAGC_DATA 0xff -#define config_phydm_read_rf_check_8821c(data) (data != INVALID_RF_DATA) -#define config_phydm_read_txagc_check_8821c(data) (data != INVALID_TXAGC_DATA) +#define config_phydm_read_rf_check_8821c(data) (data != INVALID_RF_DATA) +#define config_phydm_read_txagc_check_8821c(data) (data != INVALID_TXAGC_DATA) enum rf_set_8821c { - SWITCH_TO_BTG = 0x0, - SWITCH_TO_WLG = 0x1, - SWITCH_TO_WLA = 0x2, - SWITCH_TO_BT = 0x3 + SWITCH_TO_BTG = 0x0, + SWITCH_TO_WLG = 0x1, + SWITCH_TO_WLA = 0x2, + SWITCH_TO_BT = 0x3 }; enum ant_num_8821c { - SWITCH_TO_ANT1 = 0x0, - SWITCH_TO_ANT2 = 0x1 + SWITCH_TO_ANT1 = 0x0, + SWITCH_TO_ANT2 = 0x1 }; enum ant_num_map_8821c { - BOTH_AVAILABLE = 0x1, - ONLY_ANT1 = 0x2, - ONLY_ANT2 = 0x3, - DONT_CARE = 0x4 + BOTH_AVAILABLE = 0x1, + ONLY_ANT1 = 0x2, + ONLY_ANT2 = 0x3, + DONT_CARE = 0x4 }; -u32 -config_phydm_read_rf_reg_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e rf_path, - u32 reg_addr, - u32 bit_mask -); +s8 phydm_cck_rssi_8821c(struct dm_struct *dm, u8 lna_idx, u8 vga_idx); + +u32 config_phydm_read_rf_reg_8821c(struct dm_struct *dm, enum rf_path path, + u32 reg_addr, u32 bit_mask); boolean -config_phydm_write_rf_reg_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e rf_path, - u32 reg_addr, - u32 bit_mask, - u32 data -); +config_phydm_write_rf_reg_8821c(struct dm_struct *dm, enum rf_path path, + u32 reg_addr, u32 bit_mask, u32 data); boolean -config_phydm_write_txagc_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 power_index, - enum odm_rf_radio_path_e path, - u8 hw_rate -); - -u8 -config_phydm_read_txagc_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_radio_path_e path, - u8 hw_rate -); +config_phydm_write_txagc_8821c(struct dm_struct *dm, u32 power_index, + enum rf_path path, u8 hw_rate); + +u8 config_phydm_read_txagc_8821c(struct dm_struct *dm, enum rf_path path, + u8 hw_rate); boolean -config_phydm_switch_band_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 central_ch -); +config_phydm_switch_band_8821c(struct dm_struct *dm, u8 central_ch); boolean -config_phydm_switch_channel_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 central_ch -); +config_phydm_switch_channel_8821c(struct dm_struct *dm, u8 central_ch); boolean -config_phydm_switch_bandwidth_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 primary_ch_idx, - enum odm_bw_e bandwidth -); +config_phydm_switch_bandwidth_8821c(struct dm_struct *dm, u8 primary_ch_idx, + enum channel_width bandwidth); boolean -config_phydm_switch_channel_bw_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 central_ch, - u8 primary_ch_idx, - enum odm_bw_e bandwidth -); +config_phydm_switch_channel_bw_8821c(struct dm_struct *dm, u8 central_ch, + u8 primary_ch_idx, + enum channel_width bandwidth); boolean -config_phydm_trx_mode_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_rf_path_e tx_path, - enum odm_rf_path_e rx_path, - boolean is_tx2_path -); +config_phydm_trx_mode_8821c(struct dm_struct *dm, enum bb_path tx_path, + enum bb_path rx_path, boolean is_tx2_path); boolean -config_phydm_parameter_init_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - enum odm_parameter_init_e type -); - -void -config_phydm_switch_rf_set_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 rf_set -); - -void -config_phydm_set_ant_path( - struct PHY_DM_STRUCT *p_dm_odm, - u8 rf_set, - u8 ant_num -); +config_phydm_parameter_init_8821c(struct dm_struct *dm, + enum odm_parameter_init type); + +void config_phydm_switch_rf_set_8821c(struct dm_struct *dm, u8 rf_set); + +void config_phydm_set_ant_path(struct dm_struct *dm, u8 rf_set, u8 ant_num); /* ======================================================================== */ /* These following functions can be used for PHY DM only*/ boolean -phydm_write_txagc_1byte_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 power_index, - enum odm_rf_radio_path_e path, - u8 hw_rate -); - -void -phydm_init_hw_info_by_rfe_type_8821c( - struct PHY_DM_STRUCT *p_dm_odm -); - -void -phydm_set_gnt_state_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - boolean gnt_wl_state, - boolean gnt_bt_state -); +phydm_write_txagc_1byte_8821c(struct dm_struct *dm, u32 power_index, + enum rf_path path, u8 hw_rate); + +void phydm_init_hw_info_by_rfe_type_8821c(struct dm_struct *dm); + +void phydm_set_gnt_state_8821c(struct dm_struct *dm, boolean gnt_wl_state, + boolean gnt_bt_state); /* ======================================================================== */ -u32 -query_phydm_trx_capability_8821c( - struct PHY_DM_STRUCT *p_dm_odm -); - -u32 -query_phydm_stbc_capability_8821c( - struct PHY_DM_STRUCT *p_dm_odm -); - -u32 -query_phydm_ldpc_capability_8821c( - struct PHY_DM_STRUCT *p_dm_odm -); - -u32 -query_phydm_txbf_parameters_8821c( - struct PHY_DM_STRUCT *p_dm_odm -); - -u32 -query_phydm_txbf_capability_8821c( - struct PHY_DM_STRUCT *p_dm_odm -); - -u8 -query_phydm_default_rf_set_8821c( - struct PHY_DM_STRUCT *p_dm_odm -); - -u8 -query_phydm_current_rf_set_8821c( - struct PHY_DM_STRUCT *p_dm_odm -); - -u8 -query_phydm_rfetype_8821c( - struct PHY_DM_STRUCT *p_dm_odm -); - -u8 -query_phydm_current_ant_num_8821c( - struct PHY_DM_STRUCT *p_dm_odm -); - -u8 -query_phydm_ant_num_map_8821c( - struct PHY_DM_STRUCT *p_dm_odm -); - -#endif /* RTL8821C_SUPPORT == 1 */ -#endif /* __INC_PHYDM_API_H_8821C__ */ +u32 query_phydm_trx_capability_8821c(struct dm_struct *dm); + +u32 query_phydm_stbc_capability_8821c(struct dm_struct *dm); + +u32 query_phydm_ldpc_capability_8821c(struct dm_struct *dm); + +u32 query_phydm_txbf_parameters_8821c(struct dm_struct *dm); + +u32 query_phydm_txbf_capability_8821c(struct dm_struct *dm); + +u8 query_phydm_default_rf_set_8821c(struct dm_struct *dm); + +u8 query_phydm_current_rf_set_8821c(struct dm_struct *dm); + +u8 query_phydm_rfetype_8821c(struct dm_struct *dm); + +u8 query_phydm_current_ant_num_8821c(struct dm_struct *dm); + +u8 query_phydm_ant_num_map_8821c(struct dm_struct *dm); + +#endif /* RTL8821C_SUPPORT == 1 */ +#endif /* __INC_PHYDM_API_H_8821C__ */ diff --git a/hal/phydm/rtl8821c/phydm_regconfig8821c.c b/hal/phydm/rtl8821c/phydm_regconfig8821c.c index bb63387..68bcfc4 100644 --- a/hal/phydm/rtl8821c/phydm_regconfig8821c.c +++ b/hal/phydm/rtl8821c/phydm_regconfig8821c.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,178 +11,237 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (RTL8821C_SUPPORT == 1) -void -odm_config_rf_reg_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u32 data, - enum odm_rf_radio_path_e RF_PATH, - u32 reg_addr -) +void odm_config_rf_reg_8821c(struct dm_struct *dm, u32 addr, u32 data, + enum rf_path rf_path, u32 reg_addr) { - if (addr == 0xffe) { + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + if (addr == 0xffe) { + phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_DELAY_MS, + reg_addr, + data, + RFREGOFFSETMASK, + rf_path, + 50); + } else if (addr == 0xfe) { + phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_DELAY_US, + reg_addr, + data, + RFREGOFFSETMASK, + rf_path, + 100); + } else { + phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_RF_W, + reg_addr, + data, + RFREGOFFSETMASK, + rf_path, + 0); + phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_DELAY_US, + reg_addr, + data, + RFREGOFFSETMASK, + rf_path, + 1); + } + } else { + if (addr == 0xffe) { #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); + ODM_sleep_ms(50); #else - ODM_delay_ms(50); + ODM_delay_ms(50); #endif - } else { - odm_set_rf_reg(p_dm_odm, RF_PATH, reg_addr, RFREGOFFSETMASK, data); + } else if (addr == 0xfe) { +#ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_us(100); +#else + ODM_delay_us(100); +#endif + } else { + odm_set_rf_reg(dm, rf_path, reg_addr, RFREGOFFSETMASK, data); - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + } } } -void -odm_config_rf_radio_a_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u32 data -) +void odm_config_rf_radio_a_8821c(struct dm_struct *dm, u32 addr, u32 data) { - u32 content = 0x1000; /* RF_Content: radioa_txt */ - u32 maskfor_phy_set = (u32)(content & 0xE000); + u32 content = 0x1000; /* RF_Content: radioa_txt */ + u32 maskfor_phy_set = (u32)(content & 0xE000); - odm_config_rf_reg_8821c(p_dm_odm, addr, data, ODM_RF_PATH_A, addr | maskfor_phy_set); + odm_config_rf_reg_8821c(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", + addr, data); } -void -odm_config_mac_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u8 data -) +void odm_config_mac_8821c(struct dm_struct *dm, u32 addr, u8 data) { - odm_write_1byte(p_dm_odm, addr, data); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", addr, data)); + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) + phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_MAC_W8, + addr, + data, + 0, + (enum rf_path)0, + 0); + else + odm_write_1byte(dm, addr, data); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_mac: [MAC_REG] %08X %08X\n", + addr, data); } -void -odm_update_agc_big_jump_lmt_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u32 data -) +void odm_update_agc_big_jump_lmt_8821c(struct dm_struct *dm, u32 addr, u32 data) { - struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; - u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24); - u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16); - u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8); - static boolean is_limit; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24); + u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16); + u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8); + static boolean is_limit; if (addr != 0x81c) return; /*dbg_print("data = 0x%x, rf_gain_idx = 0x%x, bb_gain_idx = 0x%x, agc_table_idx = 0x%x\n", data, rf_gain_idx, bb_gain_idx, agc_table_idx);*/ - /*dbg_print("rf_gain_idx = 0x%x, p_dm_dig_table->rf_gain_idx = 0x%x\n", rf_gain_idx, p_dm_dig_table->rf_gain_idx);*/ + /*dbg_print("rf_gain_idx = 0x%x, dig_t->rf_gain_idx = 0x%x\n", rf_gain_idx, dig_t->rf_gain_idx);*/ if (bb_gain_idx > 0x3c) { - if ((rf_gain_idx == p_dm_dig_table->rf_gain_idx) && (is_limit == false)) { + if (rf_gain_idx == dig_t->rf_gain_idx && is_limit == false) { is_limit = true; - p_dm_dig_table->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2; - ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n", agc_table_idx, p_dm_dig_table->big_jump_lmt[agc_table_idx])); + dig_t->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2; + PHYDM_DBG(dm, DBG_DIG, + "===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n", + agc_table_idx, + dig_t->big_jump_lmt[agc_table_idx]); } - } else + } else { is_limit = false; + } - p_dm_dig_table->rf_gain_idx = rf_gain_idx; - + dig_t->rf_gain_idx = rf_gain_idx; } -void -odm_config_bb_agc_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u32 bitmask, - u32 data -) +void odm_config_bb_agc_8821c(struct dm_struct *dm, u32 addr, u32 bitmask, + u32 data) { - odm_update_agc_big_jump_lmt_8821c(p_dm_odm, addr, data); - - odm_set_bb_reg(p_dm_odm, addr, bitmask, data); - - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); + odm_update_agc_big_jump_lmt_8821c(dm, addr, data); + + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) + phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_BB_W32, + addr, + data, + bitmask, + (enum rf_path)0, + 0); + else + odm_set_bb_reg(dm, addr, bitmask, data); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data)); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [AGC_TAB] %08X %08X\n", + addr, data); } -void -odm_config_bb_phy_reg_pg_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 band, - u32 rf_path, - u32 tx_num, - u32 addr, - u32 bitmask, - u32 data -) +void odm_config_bb_phy_reg_pg_8821c(struct dm_struct *dm, u32 band, u32 rf_path, + u32 tx_num, u32 addr, u32 bitmask, u32 data) { - #if (DM_ODM_SUPPORT_TYPE & ODM_CE) - phy_store_tx_power_by_rate(p_dm_odm->adapter, band, rf_path, tx_num, addr, bitmask, data); + phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PHY_StoreTxPowerByRate(p_dm_odm->adapter, band, rf_path, tx_num, addr, bitmask, data); + PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data); #endif - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data)); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", + addr, bitmask, data); } -void -odm_config_bb_phy_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u32 bitmask, - u32 data -) +void odm_config_bb_phy_8821c(struct dm_struct *dm, u32 addr, u32 bitmask, + u32 data) { - if (addr == 0xffe) + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + u32 delay_time = 0; + + if (addr >= 0xf9 && addr <= 0xfe) { + if (addr == 0xfe || addr == 0xfb) + delay_time = 50; + else if (addr == 0xfd || addr == 0xfa) + delay_time = 5; + else + delay_time = 1; + + if (addr >= 0xfc && addr <= 0xfe) + phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_DELAY_MS, + addr, + data, + bitmask, + (enum rf_path)0, + delay_time); + else + phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_DELAY_US, + addr, + data, + bitmask, + (enum rf_path)0, + delay_time); + } else { + phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_BB_W32, + addr, + data, + bitmask, + (enum rf_path)0, + 0); + } + } else { + if (addr == 0xfe) #ifdef CONFIG_LONG_DELAY_ISSUE - ODM_sleep_ms(50); + ODM_sleep_ms(50); #else - ODM_delay_ms(50); + ODM_delay_ms(50); #endif - else - odm_set_bb_reg(p_dm_odm, addr, bitmask, data); + else if (addr == 0xfd) + ODM_delay_ms(5); + else if (addr == 0xfc) + ODM_delay_ms(1); + else if (addr == 0xfb) + ODM_delay_us(50); + else if (addr == 0xfa) + ODM_delay_us(5); + else if (addr == 0xf9) + ODM_delay_us(1); + else + odm_set_bb_reg(dm, addr, bitmask, data); + } - /* Add 1us delay between BB/RF register setting. */ - ODM_delay_us(1); - ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n", addr, data)); + PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [PHY_REG] %08X %08X\n", + addr, data); } -void -odm_config_bb_txpwr_lmt_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *regulation, - u8 *band, - u8 *bandwidth, - u8 *rate_section, - u8 *rf_path, - u8 *channel, - u8 *power_limit -) +void odm_config_bb_txpwr_lmt_8821c(struct dm_struct *dm, u8 *regulation, + u8 *band, u8 *bandwidth, u8 *rate_section, + u8 *rf_path, u8 *channel, u8 *power_limit) { #if (DM_ODM_SUPPORT_TYPE & ODM_CE) - phy_set_tx_power_limit(p_dm_odm, regulation, band, - bandwidth, rate_section, rf_path, channel, power_limit); + phy_set_tx_power_limit(dm, regulation, band, + bandwidth, rate_section, rf_path, channel, power_limit); #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) - PHY_SetTxPowerLimit(p_dm_odm, regulation, band, - bandwidth, rate_section, rf_path, channel, power_limit); + PHY_SetTxPowerLimit(dm, regulation, band, + bandwidth, rate_section, rf_path, channel, power_limit); #endif } diff --git a/hal/phydm/rtl8821c/phydm_regconfig8821c.h b/hal/phydm/rtl8821c/phydm_regconfig8821c.h index 4fe1b9a..2e9e576 100644 --- a/hal/phydm/rtl8821c/phydm_regconfig8821c.h +++ b/hal/phydm/rtl8821c/phydm_regconfig8821c.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,92 +11,40 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_ODM_REGCONFIG_H_8821C #define __INC_ODM_REGCONFIG_H_8821C #if (RTL8821C_SUPPORT == 1) -void -odm_config_rf_reg_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u32 data, - enum odm_rf_radio_path_e RF_PATH, - u32 reg_addr -); +void odm_config_rf_reg_8821c(struct dm_struct *dm, u32 addr, u32 data, + enum rf_path rf_path, u32 reg_addr); -void -odm_config_rf_radio_a_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u32 data -); +void odm_config_rf_radio_a_8821c(struct dm_struct *dm, u32 addr, u32 data); -void -odm_config_rf_radio_b_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u32 data -); +void odm_config_rf_radio_b_8821c( + struct dm_struct *dm, + u32 addr, + u32 data); -void -odm_config_mac_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u8 data -); +void odm_config_mac_8821c(struct dm_struct *dm, u32 addr, u8 data); -void -odm_update_agc_big_jump_lmt_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u32 data -); +void odm_update_agc_big_jump_lmt_8821c(struct dm_struct *dm, u32 addr, + u32 data); -void -odm_config_bb_agc_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u32 bitmask, - u32 data -); +void odm_config_bb_agc_8821c(struct dm_struct *dm, u32 addr, u32 bitmask, + u32 data); -void -odm_config_bb_phy_reg_pg_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 band, - u32 rf_path, - u32 tx_num, - u32 addr, - u32 bitmask, - u32 data -); +void odm_config_bb_phy_reg_pg_8821c(struct dm_struct *dm, u32 band, u32 rf_path, + u32 tx_num, u32 addr, u32 bitmask, + u32 data); -void -odm_config_bb_phy_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u32 addr, - u32 bitmask, - u32 data -); +void odm_config_bb_phy_8821c(struct dm_struct *dm, u32 addr, u32 bitmask, + u32 data); -void -odm_config_bb_txpwr_lmt_8821c( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *regulation, - u8 *band, - u8 *bandwidth, - u8 *rate_section, - u8 *rf_path, - u8 *channel, - u8 *power_limit -); +void odm_config_bb_txpwr_lmt_8821c(struct dm_struct *dm, u8 *regulation, + u8 *band, u8 *bandwidth, u8 *rate_section, + u8 *rf_path, u8 *channel, u8 *power_limit); #endif #endif /* RTL8822B_SUPPORT == 1*/ diff --git a/hal/phydm/rtl8821c/version_rtl8821c.h b/hal/phydm/rtl8821c/version_rtl8821c.h index d6b0123..38f6f8b 100644 --- a/hal/phydm/rtl8821c/version_rtl8821c.h +++ b/hal/phydm/rtl8821c/version_rtl8821c.h @@ -1,9 +1,33 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ /*RTL8821C PHY Parameters*/ -/* -[Caution] - Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore, - only the maintenance supervisor fills it before formal release. -*/ -#define RELEASE_DATE_8821C 20170206 +/* + * [Caution] + * Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore, + * only the maintenance supervisor fills it before formal release. + */ +#define RELEASE_DATE_8821C 20180209 #define COMMIT_BY_8821C "Coiln" -#define RELEASE_VERSION_8821C 36 +#define RELEASE_VERSION_8821C 49 diff --git a/hal/phydm/sd4_phydm_2_kernel.mk b/hal/phydm/sd4_phydm_2_kernel.mk new file mode 100644 index 0000000..f11c6ac --- /dev/null +++ b/hal/phydm/sd4_phydm_2_kernel.mk @@ -0,0 +1,188 @@ +EXTRA_CFLAGS += -I$(src)/hal/phydm + +_PHYDM_FILES := hal/phydm/phydm_debug.o \ + hal/phydm/phydm_interface.o\ + hal/phydm/phydm_phystatus.o\ + hal/phydm/phydm_hwconfig.o\ + hal/phydm/phydm.o\ + hal/phydm/phydm_dig.o\ + hal/phydm/phydm_rainfo.o\ + hal/phydm/phydm_adaptivity.o\ + hal/phydm/phydm_cfotracking.o\ + hal/phydm/phydm_noisemonitor.o\ + hal/phydm/phydm_beamforming.o\ + hal/phydm/phydm_dfs.o\ + hal/phydm/txbf/halcomtxbf.o\ + hal/phydm/txbf/haltxbfinterface.o\ + hal/phydm/txbf/phydm_hal_txbf_api.o\ + hal/phydm/phydm_ccx.o\ + hal/phydm/phydm_cck_pd.o\ + hal/phydm/phydm_rssi_monitor.o\ + hal/phydm/phydm_math_lib.o\ + hal/phydm/phydm_api.o\ + hal/phydm/halrf/halrf.o\ + hal/phydm/halrf/halrf_debug.o\ + hal/phydm/halrf/halphyrf_ce.o\ + hal/phydm/halrf/halrf_powertracking_ce.o\ + hal/phydm/halrf/halrf_powertracking.o\ + hal/phydm/halrf/halrf_kfree.o + +ifeq ($(CONFIG_RTL8188E), y) +RTL871X = rtl8188e +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\ + hal/phydm/$(RTL871X)/hal8188erateadaptive.o\ + hal/phydm/$(RTL871X)/phydm_rtl8188e.o +endif + +ifeq ($(CONFIG_RTL8192E), y) +RTL871X = rtl8192e +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\ + hal/phydm/$(RTL871X)/phydm_rtl8192e.o +endif + + +ifeq ($(CONFIG_RTL8812A), y) +RTL871X = rtl8812a +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\ + hal/phydm/$(RTL871X)/phydm_rtl8812a.o\ + hal/phydm/txbf/haltxbfjaguar.o +endif + +ifeq ($(CONFIG_RTL8821A), y) +RTL871X = rtl8821a +_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\ + hal/phydm/rtl8821a/halhwimg8821a_bb.o\ + hal/phydm/rtl8821a/halhwimg8821a_rf.o\ + hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\ + hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\ + hal/phydm/rtl8821a/phydm_regconfig8821a.o\ + hal/phydm/rtl8821a/phydm_rtl8821a.o\ + hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\ + hal/phydm/txbf/haltxbfjaguar.o +endif + + +ifeq ($(CONFIG_RTL8723B), y) +RTL871X = rtl8723b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\ + hal/phydm/$(RTL871X)/phydm_rtl8723b.o +endif + + +ifeq ($(CONFIG_RTL8814A), y) +RTL871X = rtl8814a +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\ + hal/phydm/$(RTL871X)/phydm_rtl8814a.o\ + hal/phydm/txbf/haltxbf8814a.o +endif + + +ifeq ($(CONFIG_RTL8723C), y) +RTL871X = rtl8703b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\ + hal/phydm/$(RTL871X)/phydm_rtl8703b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8703b.o +endif + +ifeq ($(CONFIG_RTL8723D), y) +RTL871X = rtl8723d +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\ + hal/phydm/$(RTL871X)/phydm_rtl8723d.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8723d.o +endif + + +ifeq ($(CONFIG_RTL8710B), y) +RTL871X = rtl8710b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\ + hal/phydm/$(RTL871X)/phydm_rtl8710b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8710b.o +endif + + +ifeq ($(CONFIG_RTL8188F), y) +RTL871X = rtl8188f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \ + hal/phydm/$(RTL871X)/phydm_rtl8188f.o +endif + +ifeq ($(CONFIG_RTL8822B), y) +RTL871X = rtl8822b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \ + hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \ + hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \ + hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \ + hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \ + hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \ + hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \ + hal/phydm/$(RTL871X)/phydm_rtl8822b.o + +_PHYDM_FILES += hal/phydm/txbf/haltxbf8822b.o +endif + + +ifeq ($(CONFIG_RTL8821C), y) +RTL871X = rtl8821c +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \ + hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \ + hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \ + hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \ + hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o +endif +ifeq ($(CONFIG_RTL8192F), y) +RTL871X = rtl8192f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\ + hal/phydm/$(RTL871X)/phydm_rtl8192f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8192f.o +endif + +ifeq ($(CONFIG_RTL8198F), y) +RTL871X = rtl8198f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8198f.o +endif diff --git a/hal/phydm/txbf/halcomtxbf.c b/hal/phydm/txbf/halcomtxbf.c index 1536778..6d66107 100644 --- a/hal/phydm/txbf/halcomtxbf.c +++ b/hal/phydm/txbf/halcomtxbf.c @@ -1,475 +1,448 @@ -/* ************************************************************ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/*@************************************************************ * Description: * * This file is for TXBF mechanism * - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (BEAMFORMING_SUPPORT == 1) -/*Beamforming halcomtxbf API create by YuChen 2015/05*/ +/*@Beamforming halcomtxbf API create by YuChen 2015/05*/ -void -hal_com_txbf_beamform_init( - void *p_dm_void -) +void hal_com_txbf_beamform_init( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - boolean is_iqgen_setting_ok = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean is_iqgen_setting_ok = false; - if (p_dm_odm->support_ic_type & ODM_RTL8814A) { - is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(p_dm_odm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] is_iqgen_setting_ok = %d\n", __func__, is_iqgen_setting_ok)); + if (dm->support_ic_type & ODM_RTL8814A) { + is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(dm); + PHYDM_DBG(dm, DBG_TXBF, "[%s] is_iqgen_setting_ok = %d\n", + __func__, is_iqgen_setting_ok); } } -/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ -void -hal_com_txbf_config_gtab( - void *p_dm_void -) +/*Only used for MU BFer Entry when get GID management frame (self as MU STA)*/ +void hal_com_txbf_config_gtab( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->support_ic_type & ODM_RTL8822B) - hal_txbf_8822b_config_gtab(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_config_gtab(dm); } -void -phydm_beamform_set_sounding_enter( - void *p_dm_void -) +void phydm_beamform_set_sounding_enter( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_enter_work_item)) == false) - odm_schedule_work_item(&(p_txbf_info->txbf_enter_work_item)); + if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_enter_work_item)) + odm_schedule_work_item(&p_txbf_info->txbf_enter_work_item); #else - hal_com_txbf_enter_work_item_callback(p_dm_odm); + hal_com_txbf_enter_work_item_callback(dm); #endif } -void -phydm_beamform_set_sounding_leave( - void *p_dm_void -) +void phydm_beamform_set_sounding_leave( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_leave_work_item)) == false) - odm_schedule_work_item(&(p_txbf_info->txbf_leave_work_item)); + if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_leave_work_item)) + odm_schedule_work_item(&p_txbf_info->txbf_leave_work_item); #else - hal_com_txbf_leave_work_item_callback(p_dm_odm); + hal_com_txbf_leave_work_item_callback(dm); #endif } -void -phydm_beamform_set_sounding_rate( - void *p_dm_void -) +void phydm_beamform_set_sounding_rate( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_rate_work_item)) == false) - odm_schedule_work_item(&(p_txbf_info->txbf_rate_work_item)); + if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_rate_work_item)) + odm_schedule_work_item(&p_txbf_info->txbf_rate_work_item); #else - hal_com_txbf_rate_work_item_callback(p_dm_odm); + hal_com_txbf_rate_work_item_callback(dm); #endif } -void -phydm_beamform_set_sounding_status( - void *p_dm_void -) +void phydm_beamform_set_sounding_status( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_status_work_item)) == false) - odm_schedule_work_item(&(p_txbf_info->txbf_status_work_item)); + if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_status_work_item)) + odm_schedule_work_item(&p_txbf_info->txbf_status_work_item); #else - hal_com_txbf_status_work_item_callback(p_dm_odm); + hal_com_txbf_status_work_item_callback(dm); #endif } -void -phydm_beamform_set_sounding_fw_ndpa( - void *p_dm_void -) +void phydm_beamform_set_sounding_fw_ndpa( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - if (*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress) - odm_set_timer(p_dm_odm, &(p_txbf_info->txbf_fw_ndpa_timer), 5); + if (*dm->is_fw_dw_rsvd_page_in_progress) + odm_set_timer(dm, &p_txbf_info->txbf_fw_ndpa_timer, 5); else - odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item)); + odm_schedule_work_item(&p_txbf_info->txbf_fw_ndpa_work_item); #else - hal_com_txbf_fw_ndpa_work_item_callback(p_dm_odm); + hal_com_txbf_fw_ndpa_work_item_callback(dm); #endif } -void -phydm_beamform_set_sounding_clk( - void *p_dm_void -) +void phydm_beamform_set_sounding_clk( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_clk_work_item)) == false) - odm_schedule_work_item(&(p_txbf_info->txbf_clk_work_item)); + if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_clk_work_item)) + odm_schedule_work_item(&p_txbf_info->txbf_clk_work_item); #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - struct _ADAPTER *padapter = p_dm_odm->adapter; - - rtw_run_in_thread_cmd(padapter, hal_com_txbf_clk_work_item_callback, padapter); + phydm_run_in_thread_cmd(dm, hal_com_txbf_clk_work_item_callback, dm); #else - hal_com_txbf_clk_work_item_callback(p_dm_odm); + hal_com_txbf_clk_work_item_callback(dm); #endif } -void -phydm_beamform_set_reset_tx_path( - void *p_dm_void -) +void phydm_beamform_set_reset_tx_path( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_reset_tx_path_work_item; - if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_reset_tx_path_work_item)) == false) - odm_schedule_work_item(&(p_txbf_info->txbf_reset_tx_path_work_item)); + if (!odm_is_work_item_scheduled(pwi)) + odm_schedule_work_item(pwi); #else - hal_com_txbf_reset_tx_path_work_item_callback(p_dm_odm); + hal_com_txbf_reset_tx_path_work_item_callback(dm); #endif } -void -phydm_beamform_set_get_tx_rate( - void *p_dm_void -) +void phydm_beamform_set_get_tx_rate( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_get_tx_rate_work_item; - if (odm_is_work_item_scheduled(&(p_txbf_info->txbf_get_tx_rate_work_item)) == false) - odm_schedule_work_item(&(p_txbf_info->txbf_get_tx_rate_work_item)); + if (!odm_is_work_item_scheduled(pwi)) + odm_schedule_work_item(pwi); #else - hal_com_txbf_get_tx_rate_work_item_callback(p_dm_odm); + hal_com_txbf_get_tx_rate_work_item_callback(dm); #endif } -void -hal_com_txbf_enter_work_item_callback( +void hal_com_txbf_enter_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -) + ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - u8 idx = p_txbf_info->txbf_idx; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) - hal_txbf_jaguar_enter(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8192E) - hal_txbf_8192e_enter(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_enter(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8822B) - hal_txbf_8822b_enter(p_dm_odm, idx); + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + u8 idx = p_txbf_info->txbf_idx; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_enter(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_enter(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_enter(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_enter(dm, idx); } -void -hal_com_txbf_leave_work_item_callback( +void hal_com_txbf_leave_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -) + ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - u8 idx = p_txbf_info->txbf_idx; + u8 idx = p_txbf_info->txbf_idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) - hal_txbf_jaguar_leave(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8192E) - hal_txbf_8192e_leave(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_leave(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8822B) - hal_txbf_8822b_leave(p_dm_odm, idx); + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_leave(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_leave(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_leave(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_leave(dm, idx); } - -void -hal_com_txbf_fw_ndpa_work_item_callback( +void hal_com_txbf_fw_ndpa_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -) + ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - u8 idx = p_txbf_info->ndpa_idx; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) - hal_txbf_jaguar_fw_txbf(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8192E) - hal_txbf_8192e_fw_tx_bf(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_fw_txbf(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8822B) - hal_txbf_8822b_fw_txbf(p_dm_odm, idx); + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + u8 idx = p_txbf_info->ndpa_idx; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_fw_txbf(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_fw_tx_bf(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_fw_txbf(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_fw_txbf(dm, idx); } -void -hal_com_txbf_clk_work_item_callback( +void hal_com_txbf_clk_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -) + ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_dm_odm->support_ic_type & ODM_RTL8812) - hal_txbf_jaguar_clk_8812a(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8812) + hal_txbf_jaguar_clk_8812a(dm); } - - -void -hal_com_txbf_rate_work_item_callback( +void hal_com_txbf_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -) + ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; - u8 BW = p_txbf_info->BW; - u8 rate = p_txbf_info->rate; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (p_dm_odm->support_ic_type & ODM_RTL8812) - hal_txbf_8812a_set_ndpa_rate(p_dm_odm, BW, rate); - else if (p_dm_odm->support_ic_type & ODM_RTL8192E) - hal_txbf_8192e_set_ndpa_rate(p_dm_odm, BW, rate); - else if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_set_ndpa_rate(p_dm_odm, BW, rate); - + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + u8 BW = p_txbf_info->BW; + u8 rate = p_txbf_info->rate; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (dm->support_ic_type & ODM_RTL8812) + hal_txbf_8812a_set_ndpa_rate(dm, BW, rate); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_set_ndpa_rate(dm, BW, rate); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_set_ndpa_rate(dm, BW, rate); } - #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -hal_com_txbf_fw_ndpa_timer_callback( - struct timer_list *p_timer -) +void hal_com_txbf_fw_ndpa_timer_callback( + struct phydm_timer_list *timer) { + void *adapter = (void *)timer->Adapter; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; - struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->Adapter; - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (*p_dm_odm->p_is_fw_dw_rsvd_page_in_progress) - odm_set_timer(p_dm_odm, &(p_txbf_info->txbf_fw_ndpa_timer), 5); + if (*dm->is_fw_dw_rsvd_page_in_progress) + odm_set_timer(dm, &(p_txbf_info->txbf_fw_ndpa_timer), 5); else odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item)); } #endif - -void -hal_com_txbf_status_work_item_callback( +void hal_com_txbf_status_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -) + ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - u8 idx = p_txbf_info->txbf_idx; + u8 idx = p_txbf_info->txbf_idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) - hal_txbf_jaguar_status(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8192E) - hal_txbf_8192e_status(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_status(p_dm_odm, idx); - else if (p_dm_odm->support_ic_type & ODM_RTL8822B) - hal_txbf_8822b_status(p_dm_odm, idx); + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_status(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_status(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_status(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_status(dm, idx); } -void -hal_com_txbf_reset_tx_path_work_item_callback( +void hal_com_txbf_reset_tx_path_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -) + ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - u8 idx = p_txbf_info->txbf_idx; - - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_reset_tx_path(p_dm_odm, idx); + u8 idx = p_txbf_info->txbf_idx; + if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_reset_tx_path(dm, idx); } -void -hal_com_txbf_get_tx_rate_work_item_callback( +void hal_com_txbf_get_tx_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -) + ) { #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; #else - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #endif - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - hal_txbf_8814a_get_tx_rate(p_dm_odm); + if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_get_tx_rate(dm); } - boolean hal_com_txbf_set( - void *p_dm_void, - u8 set_type, - void *p_in_buf -) + void *dm_void, + u8 set_type, + void *p_in_buf) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 *p_u1_tmp = (u8 *)p_in_buf; - struct _HAL_TXBF_INFO *p_txbf_info = &p_dm_odm->beamforming_info.txbf_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 *p_u1_tmp = (u8 *)p_in_buf; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set_type = 0x%X\n", __func__, set_type)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] set_type = 0x%X\n", __func__, set_type); switch (set_type) { case TXBF_SET_SOUNDING_ENTER: p_txbf_info->txbf_idx = *p_u1_tmp; - phydm_beamform_set_sounding_enter(p_dm_odm); + phydm_beamform_set_sounding_enter(dm); break; case TXBF_SET_SOUNDING_LEAVE: p_txbf_info->txbf_idx = *p_u1_tmp; - phydm_beamform_set_sounding_leave(p_dm_odm); + phydm_beamform_set_sounding_leave(dm); break; case TXBF_SET_SOUNDING_RATE: p_txbf_info->BW = p_u1_tmp[0]; p_txbf_info->rate = p_u1_tmp[1]; - phydm_beamform_set_sounding_rate(p_dm_odm); + phydm_beamform_set_sounding_rate(dm); break; case TXBF_SET_SOUNDING_STATUS: p_txbf_info->txbf_idx = *p_u1_tmp; - phydm_beamform_set_sounding_status(p_dm_odm); + phydm_beamform_set_sounding_status(dm); break; case TXBF_SET_SOUNDING_FW_NDPA: p_txbf_info->ndpa_idx = *p_u1_tmp; - phydm_beamform_set_sounding_fw_ndpa(p_dm_odm); + phydm_beamform_set_sounding_fw_ndpa(dm); break; case TXBF_SET_SOUNDING_CLK: - phydm_beamform_set_sounding_clk(p_dm_odm); + phydm_beamform_set_sounding_clk(dm); break; case TXBF_SET_TX_PATH_RESET: p_txbf_info->txbf_idx = *p_u1_tmp; - phydm_beamform_set_reset_tx_path(p_dm_odm); + phydm_beamform_set_reset_tx_path(dm); break; case TXBF_SET_GET_TX_RATE: - phydm_beamform_set_get_tx_rate(p_dm_odm); + phydm_beamform_set_get_tx_rate(dm); break; - } return true; @@ -478,35 +451,39 @@ hal_com_txbf_set( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) boolean hal_com_txbf_get( - struct _ADAPTER *adapter, - u8 get_type, - void *p_out_buf -) + void *adapter, + u8 get_type, + void *p_out_buf) { - PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - boolean *p_boolean = (boolean *)p_out_buf; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + boolean *p_boolean = (boolean *)p_out_buf; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); if (get_type == TXBF_GET_EXPLICIT_BEAMFORMEE) { if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter)) *p_boolean = false; - else if (/*IS_HARDWARE_TYPE_8822B(adapter) ||*/ - IS_HARDWARE_TYPE_8821B(adapter) || - IS_HARDWARE_TYPE_8192E(adapter) || - IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + else if (/*@IS_HARDWARE_TYPE_8822B(adapter) ||*/ + IS_HARDWARE_TYPE_8821B(adapter) || + IS_HARDWARE_TYPE_8192E(adapter) || + IS_HARDWARE_TYPE_8192F(adapter) || + IS_HARDWARE_TYPE_JAGUAR(adapter) || + IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) *p_boolean = true; else *p_boolean = false; } else if (get_type == TXBF_GET_EXPLICIT_BEAMFORMER) { if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter)) *p_boolean = false; - else if (/*IS_HARDWARE_TYPE_8822B(adapter) ||*/ - IS_HARDWARE_TYPE_8821B(adapter) || - IS_HARDWARE_TYPE_8192E(adapter) || - IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) { - if (p_hal_data->RF_Type == RF_2T2R || p_hal_data->RF_Type == RF_3T3R) + else if (/*@IS_HARDWARE_TYPE_8822B(adapter) ||*/ + IS_HARDWARE_TYPE_8821B(adapter) || + IS_HARDWARE_TYPE_8192E(adapter) || + IS_HARDWARE_TYPE_8192F(adapter) || + IS_HARDWARE_TYPE_JAGUAR(adapter) || + IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) { + if (hal_data->RF_Type == RF_2T2R || + hal_data->RF_Type == RF_3T3R) *p_boolean = true; else *p_boolean = false; @@ -514,13 +491,13 @@ hal_com_txbf_get( *p_boolean = false; } else if (get_type == TXBF_GET_MU_MIMO_STA) { #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - if (IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8821C(adapter)) + if (IS_HARDWARE_TYPE_8822B(adapter) || + IS_HARDWARE_TYPE_8821C(adapter)) *p_boolean = true; else #endif *p_boolean = false; - } else if (get_type == TXBF_GET_MU_MIMO_AP) { #if (RTL8822B_SUPPORT == 1) if (IS_HARDWARE_TYPE_8822B(adapter)) @@ -534,5 +511,4 @@ hal_com_txbf_get( } #endif - #endif diff --git a/hal/phydm/txbf/halcomtxbf.h b/hal/phydm/txbf/halcomtxbf.h index 0ce056d..d6a983f 100644 --- a/hal/phydm/txbf/halcomtxbf.h +++ b/hal/phydm/txbf/halcomtxbf.h @@ -1,21 +1,45 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ #ifndef __HAL_COM_TXBF_H__ #define __HAL_COM_TXBF_H__ -/* +#if 0 typedef bool (*TXBF_GET)( - void* p_adapter, + void* adapter, u8 get_type, void* p_out_buf ); typedef bool (*TXBF_SET)( - void* p_adapter, + void* adapter, u8 set_type, void* p_in_buf ); -*/ +#endif enum txbf_set_type { TXBF_SET_SOUNDING_ENTER, @@ -28,7 +52,6 @@ enum txbf_set_type { TXBF_SET_GET_TX_RATE }; - enum txbf_get_type { TXBF_GET_EXPLICIT_BEAMFORMEE, TXBF_GET_EXPLICIT_BEAMFORMER, @@ -36,144 +59,125 @@ enum txbf_get_type { TXBF_GET_MU_MIMO_AP }; - - -/* 2 HAL TXBF related */ +/* @2 HAL TXBF related */ struct _HAL_TXBF_INFO { - u8 txbf_idx; - u8 ndpa_idx; - u8 BW; - u8 rate; + u8 txbf_idx; + u8 ndpa_idx; + u8 BW; + u8 rate; - struct timer_list txbf_fw_ndpa_timer; + struct phydm_timer_list txbf_fw_ndpa_timer; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_WORK_ITEM txbf_enter_work_item; - RT_WORK_ITEM txbf_leave_work_item; - RT_WORK_ITEM txbf_fw_ndpa_work_item; - RT_WORK_ITEM txbf_clk_work_item; - RT_WORK_ITEM txbf_status_work_item; - RT_WORK_ITEM txbf_rate_work_item; - RT_WORK_ITEM txbf_reset_tx_path_work_item; - RT_WORK_ITEM txbf_get_tx_rate_work_item; + RT_WORK_ITEM txbf_enter_work_item; + RT_WORK_ITEM txbf_leave_work_item; + RT_WORK_ITEM txbf_fw_ndpa_work_item; + RT_WORK_ITEM txbf_clk_work_item; + RT_WORK_ITEM txbf_status_work_item; + RT_WORK_ITEM txbf_rate_work_item; + RT_WORK_ITEM txbf_reset_tx_path_work_item; + RT_WORK_ITEM txbf_get_tx_rate_work_item; #endif - }; #if (BEAMFORMING_SUPPORT == 1) -void -hal_com_txbf_beamform_init( - void *p_dm_void -); +void hal_com_txbf_beamform_init( + void *dm_void); -void -hal_com_txbf_config_gtab( - void *p_dm_void -); +void hal_com_txbf_config_gtab( + void *dm_void); -void -hal_com_txbf_enter_work_item_callback( +void hal_com_txbf_enter_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -); + ); -void -hal_com_txbf_leave_work_item_callback( +void hal_com_txbf_leave_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -); + ); -void -hal_com_txbf_fw_ndpa_work_item_callback( +void hal_com_txbf_fw_ndpa_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -); + ); -void -hal_com_txbf_clk_work_item_callback( +void hal_com_txbf_clk_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -); + ); -void -hal_com_txbf_reset_tx_path_work_item_callback( +void hal_com_txbf_reset_tx_path_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -); + ); -void -hal_com_txbf_get_tx_rate_work_item_callback( +void hal_com_txbf_get_tx_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -); + ); -void -hal_com_txbf_rate_work_item_callback( +void hal_com_txbf_rate_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -); + ); -void -hal_com_txbf_fw_ndpa_timer_callback( - struct timer_list *p_timer -); +void hal_com_txbf_fw_ndpa_timer_callback( + struct phydm_timer_list *timer); -void -hal_com_txbf_status_work_item_callback( +void hal_com_txbf_status_work_item_callback( #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - struct _ADAPTER *adapter + void *adapter #else - void *p_dm_void + void *dm_void #endif -); + ); boolean hal_com_txbf_set( - void *p_dm_void, - u8 set_type, - void *p_in_buf -); + void *dm_void, + u8 set_type, + void *p_in_buf); boolean hal_com_txbf_get( - struct _ADAPTER *adapter, - u8 get_type, - void *p_out_buf -); + void *adapter, + u8 get_type, + void *p_out_buf); #else -#define hal_com_txbf_beamform_init(p_dm_void) NULL -#define hal_com_txbf_config_gtab(p_dm_void) NULL -#define hal_com_txbf_enter_work_item_callback(_adapter) NULL -#define hal_com_txbf_leave_work_item_callback(_adapter) NULL -#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL -#define hal_com_txbf_clk_work_item_callback(_adapter) NULL -#define hal_com_txbf_rate_work_item_callback(_adapter) NULL -#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL -#define hal_com_txbf_status_work_item_callback(_adapter) NULL +#define hal_com_txbf_beamform_init(dm_void) NULL +#define hal_com_txbf_config_gtab(dm_void) NULL +#define hal_com_txbf_enter_work_item_callback(_adapter) NULL +#define hal_com_txbf_leave_work_item_callback(_adapter) NULL +#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL +#define hal_com_txbf_clk_work_item_callback(_adapter) NULL +#define hal_com_txbf_rate_work_item_callback(_adapter) NULL +#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL +#define hal_com_txbf_status_work_item_callback(_adapter) NULL #define hal_com_txbf_get(_adapter, _get_type, _pout_buf) #endif -#endif /* #ifndef __HAL_COM_TXBF_H__ */ +#endif /* @#ifndef __HAL_COM_TXBF_H__ */ diff --git a/hal/phydm/txbf/haltxbf8192e.c b/hal/phydm/txbf/haltxbf8192e.c index eee0729..d96213f 100644 --- a/hal/phydm/txbf/haltxbf8192e.c +++ b/hal/phydm/txbf/haltxbf8192e.c @@ -1,104 +1,106 @@ -/* ************************************************************ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/************************************************************* * Description: * * This file is for 8192E TXBF mechanism * - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (BEAMFORMING_SUPPORT == 1) #if (RTL8192E_SUPPORT == 1) -void -hal_txbf_8192e_set_ndpa_rate( - void *p_dm_void, - u8 BW, - u8 rate -) +void hal_txbf_8192e_set_ndpa_rate( + void *dm_void, + u8 BW, + u8 rate) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW)); } -void -hal_txbf_8192e_rf_mode( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info -) +void hal_txbf_8192e_rf_mode( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - boolean is_self_beamformer = false; - boolean is_self_beamformee = false; - enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; + struct dm_struct *dm = (struct dm_struct *)dm_void; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_dm_odm->rf_type == ODM_1T1R) + if (dm->rf_type == RF_1T1R) return; - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ - if (p_beam_info->beamformee_su_cnt > 0) { + if (beam_info->beamformee_su_cnt > 0) { /*Path_A*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/ /*Path_B*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/ } else { /*Path_A*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/ /*Path_B*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/ } - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ - if (p_beam_info->beamformee_su_cnt > 0) { - odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x83321333); - odm_set_bb_reg(p_dm_odm, 0xa04, MASKBYTE3, 0xc1); + if (beam_info->beamformee_su_cnt > 0) { + odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333); + odm_set_bb_reg(dm, R_0xa04, MASKBYTE3, 0xc1); } else - odm_set_bb_reg(p_dm_odm, 0x90c, MASKDWORD, 0x81121313); + odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313); } - - -void -hal_txbf_8192e_fw_txbf_cmd( - void *p_dm_void -) +void hal_txbf_8192e_fw_txbf_cmd( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 idx, period0 = 0, period1 = 0; - u8 PageNum0 = 0xFF, PageNum1 = 0xFF; - u8 u1_tx_bf_parm[3] = {0}; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx, period0 = 0, period1 = 0; + u8 PageNum0 = 0xFF, PageNum1 = 0xFF; + u8 u1_tx_bf_parm[3] = {0}; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - if (p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { if (idx == 0) { - if (p_beam_info->beamformee_entry[idx].is_sound) + if (beam_info->beamformee_entry[idx].is_sound) PageNum0 = 0xFE; else PageNum0 = 0xFF; /* stop sounding */ - period0 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period0 = (u8)(beam_info->beamformee_entry[idx].sound_period); } else if (idx == 1) { - if (p_beam_info->beamformee_entry[idx].is_sound) + if (beam_info->beamformee_entry[idx].is_sound) PageNum1 = 0xFE; else PageNum1 = 0xFF; /* stop sounding */ - period1 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period1 = (u8)(beam_info->beamformee_entry[idx].sound_period); } } } @@ -106,243 +108,233 @@ hal_txbf_8192e_fw_txbf_cmd( u1_tx_bf_parm[0] = PageNum0; u1_tx_bf_parm[1] = PageNum1; u1_tx_bf_parm[2] = (period1 << 4) | period0; - odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); + odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", + __func__, PageNum0, period0, PageNum1, period1); } - -void -hal_txbf_8192e_download_ndpa( - void *p_dm_void, - u8 idx -) +void hal_txbf_8192e_download_ndpa( + void *dm_void, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 u1b_tmp = 0, tmp_reg422 = 0, head_page; - u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; - boolean is_send_beacon = false; - struct _ADAPTER *adapter = p_dm_odm->adapter; - u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; - /*default reseved 1 page for the IC type which is undefined.*/ - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 u1b_tmp = 0, tmp_reg422 = 0, head_page; + u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; + boolean is_send_beacon = false; + u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; + /*@default reseved 1 page for the IC type which is undefined.*/ + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true; + *dm->is_fw_dw_rsvd_page_in_progress = true; #endif if (idx == 0) head_page = 0xFE; else head_page = 0xFE; - phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8192E+1); - odm_write_1byte(p_dm_odm, REG_CR_8192E+1, (u1b_tmp | BIT(0))); + u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1); + odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp | BIT(0))); /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2); - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422 & (~BIT(6))); + tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422 & (~BIT(6))); if (tmp_reg422 & BIT(6)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an adapter is sending beacon.\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, + "%s There is an adapter is sending beacon.\n", + __func__); is_send_beacon = true; } /*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/ - odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+1, head_page); + odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, head_page); do { - /*Clear beacon valid check bit.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2); - odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2, (bcn_valid_reg | BIT(0))); + /*@Clear beacon valid check bit.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2); + odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 2, (bcn_valid_reg | BIT(0))); - /* download NDPA rsvd page. */ - beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + /* @download NDPA rsvd page. */ + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) - u1b_tmp = odm_read_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3); + u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3); count = 0; while ((count < 20) && (u1b_tmp & BIT(4))) { count++; ODM_delay_us(10); - u1b_tmp = odm_read_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3); + u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3); } - odm_write_1byte(p_dm_odm, REG_MGQ_TXBD_NUM_8192E+3, u1b_tmp | BIT(4)); + odm_write_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3, u1b_tmp | BIT(4)); #endif - /*check rsvd page download OK.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2); + /*@check rsvd page download OK.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2); count = 0; while (!(bcn_valid_reg & BIT(0)) && count < 20) { count++; ODM_delay_us(10); - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+2); + bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2); } dl_bcn_count++; } while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5); if (!(bcn_valid_reg & BIT(0))) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", + __func__); /*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/ - odm_write_1byte(p_dm_odm, REG_DWBCN0_CTRL_8192E+1, tx_page_bndy); + odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, tx_page_bndy); /*To make sure that if there exists an adapter which would like to send beacon.*/ - /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ /*the beacon cannot be sent by HW.*/ - /*2010.06.23. Added by tynli.*/ + /*@2010.06.23. Added by tynli.*/ if (is_send_beacon) - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8192E+2, tmp_reg422); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422); - /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ - /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8192E+1); - odm_write_1byte(p_dm_odm, REG_CR_8192E+1, (u1b_tmp & (~BIT(0)))); + /*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1); + odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp & (~BIT(0)))); p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false; + *dm->is_fw_dw_rsvd_page_in_progress = false; #endif } - -void -hal_txbf_8192e_enter( - void *p_dm_void, - u8 bfer_bfee_idx -) +void hal_txbf_8192e_enter( + void *dm_void, + u8 bfer_bfee_idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i = 0; - u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; - u8 bfee_idx = (bfer_bfee_idx & 0xF); - u32 csi_param; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY beamformee_entry; - struct _RT_BEAMFORMER_ENTRY beamformer_entry; - u16 sta_id = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + u32 csi_param; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + u16 sta_id = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - hal_txbf_8192e_rf_mode(p_dm_odm, p_beamforming_info); + hal_txbf_8192e_rf_mode(dm, beamforming_info); - if (p_dm_odm->rf_type == ODM_2T2R) - odm_write_4byte(p_dm_odm, 0xd80, 0x00000000); /*nc =2*/ + if (dm->rf_type == RF_2T2R) + odm_write_4byte(dm, 0xd80, 0x00000000); /*nc =2*/ - if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { - beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx]; + if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = beamforming_info->beamformer_entry[bfer_idx]; /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E, 0xCB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xCB); - /*MAC address/Partial AID of Beamformer*/ + /*@MAC address/Partial AID of Beamformer*/ if (bfer_idx == 0) { - for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), beamformer_entry.mac_addr[i]); + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8192E + i), beamformer_entry.mac_addr[i]); } else { - for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), beamformer_entry.mac_addr[i]); + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8192E + i), beamformer_entry.mac_addr[i]); } - /*CSI report parameters of Beamformer Default use nc = 2*/ + /*@CSI report parameters of Beamformer Default use nc = 2*/ csi_param = 0x03090309; - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param); - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param); - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param); /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E+3, 0x50); - + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E + 3, 0x50); } - if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { - beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx]; + if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) { + beamformee_entry = beamforming_info->beamformee_entry[bfee_idx]; - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) sta_id = beamformee_entry.mac_id; else sta_id = beamformee_entry.p_aid; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], sta_id=0x%X\n", __func__, sta_id)); + PHYDM_DBG(dm, DBG_TXBF, "[%s], sta_id=0x%X\n", __func__, + sta_id); /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ if (bfee_idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E, sta_id); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_TXBF_CTRL_8192E, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8192E + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 3) | BIT(4) | BIT(6) | BIT(7)); } else - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E+2, sta_id | BIT(12) | BIT(14) | BIT(15)); + odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, sta_id | BIT(12) | BIT(14) | BIT(15)); - /*CSI report parameters of Beamformee*/ + /*@CSI report parameters of Beamformee*/ if (bfee_idx == 0) { - /*Get BIT24 & BIT25*/ - u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3; + /*@Get BIT24 & BIT25*/ + u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3) & 0x3; - odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9)); + odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3, tmp | 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9)); } else { /*Set BIT25*/ - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, sta_id | 0xE200); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, sta_id | 0xE200); } - phydm_beamforming_notify(p_dm_odm); - + phydm_beamforming_notify(dm); } } - -void -hal_txbf_8192e_leave( - void *p_dm_void, - u8 idx -) +void hal_txbf_8192e_leave( + void *dm_void, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; - hal_txbf_8192e_rf_mode(p_dm_odm, p_beam_info); + hal_txbf_8192e_rf_mode(dm, beam_info); - /* Clear P_AID of Beamformee + /* @Clear P_AID of Beamformee * Clear MAC addresss of Beamformer * Clear Associated Bfmee Sel */ - if (p_beam_info->beamform_cap == BEAMFORMING_CAP_NONE) - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8192E, 0xC8); + if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE) + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xC8); if (idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E, 0); - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0); + odm_write_2byte(dm, REG_TXBF_CTRL_8192E, 0); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E + 4, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0); } else { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8192E+2, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8192E+2) & 0xF000); - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60); + odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 2) & 0xF000); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E + 4, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2) & 0x60); } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx %d\n", __func__, idx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] idx %d\n", __func__, idx); } - -void -hal_txbf_8192e_status( - void *p_dm_void, - u8 idx -) +void hal_txbf_8192e_status( + void *dm_void, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u16 beam_ctrl_val; - u32 beam_ctrl_reg; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY beamform_entry = p_beam_info->beamformee_entry[idx]; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 beam_ctrl_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx]; - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) beam_ctrl_val = beamform_entry.mac_id; else beam_ctrl_val = beamform_entry.p_aid; @@ -350,11 +342,11 @@ hal_txbf_8192e_status( if (idx == 0) beam_ctrl_reg = REG_TXBF_CTRL_8192E; else { - beam_ctrl_reg = REG_TXBF_CTRL_8192E+2; + beam_ctrl_reg = REG_TXBF_CTRL_8192E + 2; beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beam_info->apply_v_matrix == true)) { + if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) { if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) beam_ctrl_val |= BIT(9); else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) @@ -362,30 +354,29 @@ hal_txbf_8192e_status( } else beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); - odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__, idx, beam_ctrl_reg, beam_ctrl_val)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__, + idx, beam_ctrl_reg, beam_ctrl_val); } - -void -hal_txbf_8192e_fw_tx_bf( - void *p_dm_void, - u8 idx -) +void hal_txbf_8192e_fw_tx_bf( + void *dm_void, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) - hal_txbf_8192e_download_ndpa(p_dm_odm, idx); + hal_txbf_8192e_download_ndpa(dm, idx); - hal_txbf_8192e_fw_txbf_cmd(p_dm_odm); + hal_txbf_8192e_fw_txbf_cmd(dm); } -#endif /* #if (RTL8192E_SUPPORT == 1)*/ +#endif /* @#if (RTL8192E_SUPPORT == 1)*/ #endif diff --git a/hal/phydm/txbf/haltxbf8192e.h b/hal/phydm/txbf/haltxbf8192e.h index 618ca80..4579ea1 100644 --- a/hal/phydm/txbf/haltxbf8192e.h +++ b/hal/phydm/txbf/haltxbf8192e.h @@ -1,59 +1,70 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ #ifndef __HAL_TXBF_8192E_H__ #define __HAL_TXBF_8192E_H__ #if (RTL8192E_SUPPORT == 1) #if (BEAMFORMING_SUPPORT == 1) -void -hal_txbf_8192e_set_ndpa_rate( - void *p_dm_void, - u8 BW, - u8 rate -); +void hal_txbf_8192e_set_ndpa_rate( + void *dm_void, + u8 BW, + u8 rate); -void -hal_txbf_8192e_enter( - void *p_dm_void, - u8 idx -); +void hal_txbf_8192e_enter( + void *dm_void, + u8 idx); +void hal_txbf_8192e_leave( + void *dm_void, + u8 idx); -void -hal_txbf_8192e_leave( - void *p_dm_void, - u8 idx -); +void hal_txbf_8192e_status( + void *dm_void, + u8 idx); - -void -hal_txbf_8192e_status( - void *p_dm_void, - u8 idx -); - - -void -hal_txbf_8192e_fw_tx_bf( - void *p_dm_void, - u8 idx -); +void hal_txbf_8192e_fw_tx_bf( + void *dm_void, + u8 idx); #else -#define hal_txbf_8192e_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_8192e_enter(p_dm_void, idx) -#define hal_txbf_8192e_leave(p_dm_void, idx) -#define hal_txbf_8192e_status(p_dm_void, idx) -#define hal_txbf_8192e_fw_tx_bf(p_dm_void, idx) +#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8192e_enter(dm_void, idx) +#define hal_txbf_8192e_leave(dm_void, idx) +#define hal_txbf_8192e_status(dm_void, idx) +#define hal_txbf_8192e_fw_tx_bf(dm_void, idx) #endif #else -#define hal_txbf_8192e_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_8192e_enter(p_dm_void, idx) -#define hal_txbf_8192e_leave(p_dm_void, idx) -#define hal_txbf_8192e_status(p_dm_void, idx) -#define hal_txbf_8192e_fw_tx_bf(p_dm_void, idx) +#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8192e_enter(dm_void, idx) +#define hal_txbf_8192e_leave(dm_void, idx) +#define hal_txbf_8192e_status(dm_void, idx) +#define hal_txbf_8192e_fw_tx_bf(dm_void, idx) #endif diff --git a/hal/phydm/txbf/haltxbf8814a.c b/hal/phydm/txbf/haltxbf8814a.c index ffb5e00..4efb553 100644 --- a/hal/phydm/txbf/haltxbf8814a.c +++ b/hal/phydm/txbf/haltxbf8814a.c @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ /* ************************************************************ * Description: * @@ -12,71 +26,60 @@ #if (RTL8814A_SUPPORT == 1) boolean -phydm_beamforming_set_iqgen_8814A( - void *p_dm_void -) +phydm_beamforming_set_iqgen_8814A(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i = 0; u16 counter = 0; u32 rf_mode[4]; - for (i = ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++) - odm_set_rf_reg(p_dm_odm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) + odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ while (1) { counter++; - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) - odm_set_rf_reg(p_dm_odm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/ + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) + odm_set_rf_reg(dm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/ ODM_delay_us(2); - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) - rf_mode[i] = odm_get_rf_reg(p_dm_odm, i, RF_RCK_OS, 0xfffff); + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) + rf_mode[i] = odm_get_rf_reg(dm, i, RF_RCK_OS, 0xfffff); - if ((rf_mode[0] == 0x18000) && (rf_mode[1] == 0x18000) && (rf_mode[2] == 0x18000) && (rf_mode[3] == 0x18000)) + if (rf_mode[0] == 0x18000 && rf_mode[1] == 0x18000 && rf_mode[2] == 0x18000 && rf_mode[3] == 0x18000) break; else if (counter == 100) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("iqgen setting fail:8814A\n")); + PHYDM_DBG(dm, DBG_TXBF, "iqgen setting fail:8814A\n"); return false; } } - for (i = ODM_RF_PATH_A ; i < MAX_RF_PATH ; i++) { - odm_set_rf_reg(p_dm_odm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*Enable TXIQGEN in Rx mode*/ + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) { + odm_set_rf_reg(dm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/ + odm_set_rf_reg(dm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*@Enable TXIQGEN in Rx mode*/ } - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*Enable TXIQGEN in Rx mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in Rx mode*/ - for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) - odm_set_rf_reg(p_dm_odm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) + odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ return true; - } - - -void -hal_txbf_8814a_set_ndpa_rate( - void *p_dm_void, - u8 BW, - u8 rate -) +void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8814A, BW); - odm_write_1byte(p_dm_odm, REG_NDPA_RATE_8814A, (u8) rate); + struct dm_struct *dm = (struct dm_struct *)dm_void; + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8814A, BW); + odm_write_1byte(dm, REG_NDPA_RATE_8814A, (u8)rate); } - -#define PHYDM_MEMORY_MAP_BUF_READ 0x8000 -#define PHYDM_CTRL_INFO_PAGE 0x660 +#if 0 +#define PHYDM_MEMORY_MAP_BUF_READ 0x8000 +#define PHYDM_CTRL_INFO_PAGE 0x660 void phydm_data_rate_8814a( - struct PHY_DM_STRUCT *p_dm_odm, + struct dm_struct *dm, u8 mac_id, u32 *data, u8 data_len @@ -85,83 +88,83 @@ phydm_data_rate_8814a( u8 i = 0; u16 x_read_data_addr = 0; - odm_write_2byte(p_dm_odm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE); - x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*Ctrl Info: 32Bytes for each macid(n)*/ + odm_write_2byte(dm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE); + x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*@Ctrl Info: 32Bytes for each macid(n)*/ - if ((x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ) || (x_read_data_addr > 0x8FFF)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("x_read_data_addr(0x%x) is not correct!\n", x_read_data_addr)); + if (x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ || x_read_data_addr > 0x8FFF) { + PHYDM_DBG(dm, DBG_TXBF, + "x_read_data_addr(0x%x) is not correct!\n", + x_read_data_addr); return; } /* Read data */ for (i = 0; i < data_len; i++) - *(data + i) = odm_read_2byte(p_dm_odm, x_read_data_addr + i); - + *(data + i) = odm_read_2byte(dm, x_read_data_addr + i); } +#endif -void -hal_txbf_8814a_get_tx_rate( - void *p_dm_void -) +void hal_txbf_8814a_get_tx_rate(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_entry; - u32 tx_rpt_data = 0; - u8 data_rate = 0xFF; - - p_entry = &(p_beam_info->beamformee_entry[p_beam_info->beamformee_cur_idx]); - - phydm_data_rate_8814a(p_dm_odm, (u8)p_entry->mac_id, &tx_rpt_data, 1); - data_rate = (u8)tx_rpt_data; - data_rate &= 0x7f; /*Bit7 indicates SGI*/ - - p_dm_odm->tx_bf_data_rate = data_rate; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *entry; + struct ra_table *ra_tab = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; + u8 data_rate = 0xFF; + u8 macid = 0; + + entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]); + macid = (u8)entry->mac_id; + + sta = dm->phydm_sta_info[macid]; + + if (is_sta_active(sta)) { + data_rate = (sta->ra_info.curr_tx_rate) & 0x7f; /*@Bit7 indicates SGI*/ + beam_info->tx_bf_data_rate = data_rate; + } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] p_dm_odm->tx_bf_data_rate = 0x%x\n", __func__, p_dm_odm->tx_bf_data_rate)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] dm->tx_bf_data_rate = 0x%x\n", __func__, + beam_info->tx_bf_data_rate); } -void -hal_txbf_8814a_reset_tx_path( - void *p_dm_void, - u8 idx -) +void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; #if DEV_BUS_TYPE == RT_USB_INTERFACE - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY beamformee_entry; - u8 nr_index = 0, tx_ss = 0; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + u8 nr_index = 0, tx_ss = 0; if (idx < BEAMFORMEE_ENTRY_NUM) - beamformee_entry = p_beamforming_info->beamformee_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; else return; - if ((p_dm_odm->last_usb_hub) != (*p_dm_odm->hub_usb_mode)) { - nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), beamformee_entry.comp_steering_num_of_bfer); + if (beamforming_info->last_usb_hub != (*dm->hub_usb_mode)) { + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer); - if (*p_dm_odm->hub_usb_mode == 2) { - if (p_dm_odm->rf_type == ODM_4T4R) + if (*dm->hub_usb_mode == 2) { + if (dm->rf_type == RF_4T4R) tx_ss = 0xf; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) tx_ss = 0xe; else tx_ss = 0x6; - } else if (*p_dm_odm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ + } else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ tx_ss = 0x6; else tx_ss = 0x6; if (tx_ss == 0xf) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); } else if (tx_ss == 0xe) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); } else if (tx_ss == 0x6) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); } if (idx == 0) { @@ -169,169 +172,159 @@ hal_txbf_8814a_reset_tx_path( case 0: break; - case 1: /*Nsts = 2 BC*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + case 1: /*Nsts = 2 BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ break; - case 2: /*Nsts = 3 BCD*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + case 2: /*Nsts = 3 BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ break; - default: /*nr>3, same as Case 3*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ break; } - } else { + } else { switch (nr_index) { case 0: break; - case 1: /*Nsts = 2 BC*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + case 1: /*Nsts = 2 BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ break; - case 2: /*Nsts = 3 BCD*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + case 2: /*Nsts = 3 BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ break; - default: /*nr>3, same as Case 3*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ break; } } - p_dm_odm->last_usb_hub = *p_dm_odm->hub_usb_mode; + beamforming_info->last_usb_hub = *dm->hub_usb_mode; } else return; #endif } - -u8 -hal_txbf_8814a_get_ntx( - void *p_dm_void -) +u8 hal_txbf_8814a_get_ntx(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 ntx = 0, tx_ss = 3; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ntx = 0, tx_ss = 3; #if DEV_BUS_TYPE == RT_USB_INTERFACE - tx_ss = *p_dm_odm->hub_usb_mode; + tx_ss = *dm->hub_usb_mode; #endif if (tx_ss == 3 || tx_ss == 2) { - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->rf_type == RF_4T4R) ntx = 3; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) ntx = 2; else ntx = 1; - } else if (tx_ss == 1) /*USB 2.0 always 2Tx*/ + } else if (tx_ss == 1) /*USB 2.0 always 2Tx*/ ntx = 1; else ntx = 1; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ntx = %d\n", __func__, ntx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ntx = %d\n", __func__, ntx); return ntx; } -u8 -hal_txbf_8814a_get_nrx( - void *p_dm_void -) +u8 hal_txbf_8814a_get_nrx(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 nrx = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 nrx = 0; - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->rf_type == RF_4T4R) nrx = 3; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) nrx = 2; - else if (p_dm_odm->rf_type == ODM_2T2R) + else if (dm->rf_type == RF_2T2R) nrx = 1; - else if (p_dm_odm->rf_type == ODM_2T3R) + else if (dm->rf_type == RF_2T3R) nrx = 2; - else if (p_dm_odm->rf_type == ODM_2T4R) + else if (dm->rf_type == RF_2T4R) nrx = 3; - else if (p_dm_odm->rf_type == ODM_1T1R) + else if (dm->rf_type == RF_1T1R) nrx = 0; - else if (p_dm_odm->rf_type == ODM_1T2R) + else if (dm->rf_type == RF_1T2R) nrx = 1; else nrx = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] nrx = %d\n", __func__, nrx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] nrx = %d\n", __func__, nrx); return nrx; } -void -hal_txbf_8814a_rf_mode( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beamforming_info, - u8 idx -) +void hal_txbf_8814a_rf_mode(void *dm_void, + struct _RT_BEAMFORMING_INFO *beamforming_info, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i, nr_index = 0; - u8 tx_ss = 3; /*default use 3 Tx*/ - struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 nr_index = 0; + u8 tx_ss = 3; /*@default use 3 Tx*/ + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; if (idx < BEAMFORMEE_ENTRY_NUM) - beamformee_entry = p_beamforming_info->beamformee_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; else return; - nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), beamformee_entry.comp_steering_num_of_bfer); + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer); - if (p_dm_odm->rf_type == ODM_1T1R) + if (dm->rf_type == RF_1T1R) return; - if (p_beamforming_info->beamformee_su_cnt > 0) { + if (beamforming_info->beamformee_su_cnt > 0) { #if DEV_BUS_TYPE == RT_USB_INTERFACE - p_dm_odm->last_usb_hub = *p_dm_odm->hub_usb_mode; - tx_ss = *p_dm_odm->hub_usb_mode; + beamforming_info->last_usb_hub = *dm->hub_usb_mode; + tx_ss = *dm->hub_usb_mode; #endif if (tx_ss == 3 || tx_ss == 2) { - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->rf_type == RF_4T4R) tx_ss = 0xf; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) tx_ss = 0xe; else tx_ss = 0x6; - } else if (tx_ss == 1) /*USB 2.0 always 2Tx*/ + } else if (tx_ss == 1) /*USB 2.0 always 2Tx*/ tx_ss = 0x6; else tx_ss = 0x6; if (tx_ss == 0xf) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); } else if (tx_ss == 0xe) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); } else if (tx_ss == 0x6) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); } - /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*if Nsts > Nc don't apply V matrix*/ + /*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*@if Nsts > Nc don't apply V matrix*/ if (idx == 0) { switch (nr_index) { case 0: break; - case 1: /*Nsts = 2 BC*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + case 1: /*Nsts = 2 BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ break; - case 2: /*Nsts = 3 BCD*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + case 2: /*Nsts = 3 BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ break; - default: /*nr>3, same as Case 3*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ break; } @@ -340,132 +333,135 @@ hal_txbf_8814a_rf_mode( case 0: break; - case 1: /*Nsts = 2 BC*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + case 1: /*Nsts = 2 BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ break; - case 2: /*Nsts = 3 BCD*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + case 2: /*Nsts = 3 BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ break; - default: /*nr>3, same as Case 3*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ break; } } } - if ((p_beamforming_info->beamformee_su_cnt == 0) && (p_beamforming_info->beamformer_su_cnt == 0)) { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360); + if (beamforming_info->beamformee_su_cnt == 0 && beamforming_info->beamformer_su_cnt == 0) { + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360); } } #if 0 void hal_txbf_8814a_download_ndpa( - void *p_dm_void, + void *dm_void, u8 idx ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 u1b_tmp = 0, tmp_reg422 = 0; u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; u16 head_page = 0x7FE; boolean is_send_beacon = false; - u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; - struct _ADAPTER *adapter = p_dm_odm->adapter; + u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/ + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + void *adapter = dm->adapter; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true; + *dm->is_fw_dw_rsvd_page_in_progress = true; #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8814A + 1); - odm_write_1byte(p_dm_odm, REG_CR_8814A + 1, (u1b_tmp | BIT(0))); + u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1); + odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp | BIT(0))); /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2); - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422 & (~BIT(6))); + tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422 & (~BIT(6))); if (tmp_reg422 & BIT(6)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: There is an adapter is sending beacon.\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, + "%s: There is an adapter is sending beacon.\n", + __func__); is_send_beacon = true; } - /*0x204[11:0] Beacon Head for TXDMA*/ - odm_write_2byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A, head_page); + /*@0x204[11:0] Beacon Head for TXDMA*/ + odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, head_page); do { - /*Clear beacon valid check bit.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1); - odm_write_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7))); + /*@Clear beacon valid check bit.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1); + odm_write_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7))); - /*download NDPA rsvd page.*/ + /*@download NDPA rsvd page.*/ if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) - beamforming_send_vht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); else - beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); - /*check rsvd page download OK.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 1); + /*@check rsvd page download OK.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1); count = 0; while (!(bcn_valid_reg & BIT(7)) && count < 20) { count++; ODM_delay_ms(10); - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A + 2); + bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 2); } dl_bcn_count++; } while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5); if (!(bcn_valid_reg & BIT(7))) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", + __func__); - /*0x204[11:0] Beacon Head for TXDMA*/ - odm_write_2byte(p_dm_odm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy); + /*@0x204[11:0] Beacon Head for TXDMA*/ + odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy); /*To make sure that if there exists an adapter which would like to send beacon.*/ - /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ /*the beacon cannot be sent by HW.*/ - /*2010.06.23. Added by tynli.*/ + /*@2010.06.23. Added by tynli.*/ if (is_send_beacon) - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422); - /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ - /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8814A + 1); - odm_write_1byte(p_dm_odm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0)))); + /*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1); + odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0)))); p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false; + *dm->is_fw_dw_rsvd_page_in_progress = false; #endif } void hal_txbf_8814a_fw_txbf_cmd( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 idx, period = 0; u8 PageNum0 = 0xFF, PageNum1 = 0xFF; u8 u1_tx_bf_parm[3] = {0}; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (p_beam_info->beamformee_entry[idx].is_sound) { + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beam_info->beamformee_entry[idx].is_sound) { PageNum0 = 0xFE; PageNum1 = 0x07; - period = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period = (u8)(beam_info->beamformee_entry[idx].sound_period); } else if (PageNum0 == 0xFF) { PageNum0 = 0xFF; /*stop sounding*/ PageNum1 = 0x0F; @@ -476,52 +472,50 @@ hal_txbf_8814a_fw_txbf_cmd( u1_tx_bf_parm[0] = PageNum0; u1_tx_bf_parm[1] = PageNum1; u1_tx_bf_parm[2] = period; - odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); + odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__, PageNum0, PageNum1, period)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__, + PageNum0, PageNum1, period); } #endif -void -hal_txbf_8814a_enter( - void *p_dm_void, - u8 bfer_bfee_idx -) +void hal_txbf_8814a_enter(void *dm_void, u8 bfer_bfee_idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i = 0; - u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; - u8 bfee_idx = (bfer_bfee_idx & 0xF); - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY beamformee_entry; - struct _RT_BEAMFORMER_ENTRY beamformer_entry; - u16 sta_id = 0, csi_param = 0; - u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_idx, bfee_idx)); - odm_set_mac_reg(p_dm_odm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202); - - if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { - beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx]; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + u16 sta_id = 0, csi_param = 0; + u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] bfer_idx=%d, bfee_idx=%d\n", __func__, + bfer_idx, bfee_idx); + odm_set_mac_reg(dm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202); + + if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = beamforming_info->beamformer_entry[bfer_idx]; /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A, 0xDB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xDB); - /*MAC address/Partial AID of Beamformer*/ + /*@MAC address/Partial AID of Beamformer*/ if (bfer_idx == 0) { - for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]); + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]); } else { - for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]); + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]); } - /*CSI report parameters of Beamformer*/ - nc_index = hal_txbf_8814a_get_nrx(p_dm_odm); /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/ - nr_index = beamformer_entry.num_of_sounding_dim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ + /*@CSI report parameters of Beamformer*/ + nc_index = hal_txbf_8814a_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/ + nr_index = beamformer_entry.num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ grouping = 0; - /*for ac = 1, for n = 3*/ + /*@for ac = 1, for n = 3*/ if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) codebookinfo = 1; else if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT) @@ -532,118 +526,108 @@ hal_txbf_8814a_enter( csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); if (bfer_idx == 0) - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param); else - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param); /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A + 3, 0x40); - + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A + 3, 0x40); } - if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { - beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx]; + if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) { + beamformee_entry = beamforming_info->beamformee_entry[bfee_idx]; - hal_txbf_8814a_rf_mode(p_dm_odm, p_beamforming_info, bfee_idx); + hal_txbf_8814a_rf_mode(dm, beamforming_info, bfee_idx); - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) sta_id = beamformee_entry.mac_id; else sta_id = beamformee_entry.p_aid; /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ if (bfee_idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, sta_id); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_TXBF_CTRL_8814A, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); } else - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); + odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); - /*CSI report parameters of Beamformee*/ + /*@CSI report parameters of Beamformee*/ if (bfee_idx == 0) { - /*Get BIT24 & BIT25*/ - u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3; + /*@Get BIT24 & BIT25*/ + u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3; - odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9)); + odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9)); } else - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/ + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/ - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); } - } - -void -hal_txbf_8814a_leave( - void *p_dm_void, - u8 idx -) +void hal_txbf_8814a_leave(void *dm_void, u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMER_ENTRY beamformer_entry; - struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; if (idx < BEAMFORMER_ENTRY_NUM) { - beamformer_entry = p_beamforming_info->beamformer_entry[idx]; - beamformee_entry = p_beamforming_info->beamformee_entry[idx]; + beamformer_entry = beamforming_info->beamformer_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; } else return; - /*Clear P_AID of Beamformee*/ - /*Clear MAC address of Beamformer*/ - /*Clear Associated Bfmee Sel*/ + /*@Clear P_AID of Beamformee*/ + /*@Clear MAC address of Beamformer*/ + /*@Clear Associated Bfmee Sel*/ if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8814A, 0xD8); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xD8); if (idx == 0) { - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A, 0); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, 0); } else { - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0); } } if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { - hal_txbf_8814a_rf_mode(p_dm_odm, p_beamforming_info, idx); + hal_txbf_8814a_rf_mode(dm, beamforming_info, idx); if (idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, 0x0); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0); + odm_write_2byte(dm, REG_TXBF_CTRL_8814A, 0x0); + odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0); } else { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); + odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60); } } } -void -hal_txbf_8814a_status( - void *p_dm_void, - u8 idx -) +void hal_txbf_8814a_status(void *dm_void, u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u16 beam_ctrl_val, tmp_val; - u32 beam_ctrl_reg; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY beamform_entry; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 beam_ctrl_val, tmp_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamform_entry; if (idx < BEAMFORMEE_ENTRY_NUM) - beamform_entry = p_beamforming_info->beamformee_entry[idx]; + beamform_entry = beamforming_info->beamformee_entry[idx]; else return; - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) beam_ctrl_val = beamform_entry.mac_id; else beam_ctrl_val = beamform_entry.p_aid; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, beamform_entry.beamform_entry_state = %d", __func__, beamform_entry.beamform_entry_state)); + PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d", + __func__, beamform_entry.beamform_entry_state); if (idx == 0) beam_ctrl_reg = REG_TXBF_CTRL_8814A; @@ -652,7 +636,7 @@ hal_txbf_8814a_status( beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beamforming_info->apply_v_matrix == true)) { + if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beamforming_info->apply_v_matrix == true) { if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) beam_ctrl_val |= BIT(9); else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) @@ -660,41 +644,32 @@ hal_txbf_8814a_status( else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80) beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11)); } else { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__); beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); } - odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); - /*disable NDP packet use beamforming */ - tmp_val = odm_read_2byte(p_dm_odm, REG_TXBF_CTRL_8814A); - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15)); - + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); + /*@disable NDP packet use beamforming */ + tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8814A); + odm_write_2byte(dm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15)); } - - - - -void -hal_txbf_8814a_fw_txbf( - void *p_dm_void, - u8 idx -) +void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx) { #if 0 - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) - hal_txbf_8814a_download_ndpa(p_dm_odm, idx); + hal_txbf_8814a_download_ndpa(dm, idx); - hal_txbf_8814a_fw_txbf_cmd(p_dm_odm); + hal_txbf_8814a_fw_txbf_cmd(dm); #endif } -#endif /* (RTL8814A_SUPPORT == 1)*/ +#endif /* @(RTL8814A_SUPPORT == 1)*/ #endif diff --git a/hal/phydm/txbf/haltxbf8814a.h b/hal/phydm/txbf/haltxbf8814a.h index bb72401..bf360f7 100644 --- a/hal/phydm/txbf/haltxbf8814a.h +++ b/hal/phydm/txbf/haltxbf8814a.h @@ -1,3 +1,27 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ #ifndef __HAL_TXBF_8814A_H__ #define __HAL_TXBF_8814A_H__ @@ -5,85 +29,49 @@ #if (BEAMFORMING_SUPPORT == 1) boolean -phydm_beamforming_set_iqgen_8814A( - void *p_dm_void -); - -void -hal_txbf_8814a_set_ndpa_rate( - void *p_dm_void, - u8 BW, - u8 rate -); - -u8 -hal_txbf_8814a_get_ntx( - void *p_dm_void -); - -void -hal_txbf_8814a_enter( - void *p_dm_void, - u8 idx -); - - -void -hal_txbf_8814a_leave( - void *p_dm_void, - u8 idx -); - - -void -hal_txbf_8814a_status( - void *p_dm_void, - u8 idx -); - -void -hal_txbf_8814a_reset_tx_path( - void *p_dm_void, - u8 idx -); - - -void -hal_txbf_8814a_get_tx_rate( - void *p_dm_void -); - -void -hal_txbf_8814a_fw_txbf( - void *p_dm_void, - u8 idx -); +phydm_beamforming_set_iqgen_8814A(void *dm_void); + +void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate); + +u8 hal_txbf_8814a_get_ntx(void *dm_void); + +void hal_txbf_8814a_enter(void *dm_void, u8 idx); + +void hal_txbf_8814a_leave(void *dm_void, u8 idx); + +void hal_txbf_8814a_status(void *dm_void, u8 idx); + +void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx); + +void hal_txbf_8814a_get_tx_rate(void *dm_void); + +void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx); #else -#define hal_txbf_8814a_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_8814a_get_ntx(p_dm_void) 0 -#define hal_txbf_8814a_enter(p_dm_void, idx) -#define hal_txbf_8814a_leave(p_dm_void, idx) -#define hal_txbf_8814a_status(p_dm_void, idx) -#define hal_txbf_8814a_reset_tx_path(p_dm_void, idx) -#define hal_txbf_8814a_get_tx_rate(p_dm_void) -#define hal_txbf_8814a_fw_txbf(p_dm_void, idx) -#define phydm_beamforming_set_iqgen_8814A(p_dm_void) 0 +#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8814a_get_ntx(dm_void) 0 +#define hal_txbf_8814a_enter(dm_void, idx) +#define hal_txbf_8814a_leave(dm_void, idx) +#define hal_txbf_8814a_status(dm_void, idx) +#define hal_txbf_8814a_reset_tx_path(dm_void, idx) +#define hal_txbf_8814a_get_tx_rate(dm_void) +#define hal_txbf_8814a_fw_txbf(dm_void, idx) +#define phydm_beamforming_set_iqgen_8814A(dm_void) 0 #endif #else -#define hal_txbf_8814a_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_8814a_get_ntx(p_dm_void) 0 -#define hal_txbf_8814a_enter(p_dm_void, idx) -#define hal_txbf_8814a_leave(p_dm_void, idx) -#define hal_txbf_8814a_status(p_dm_void, idx) -#define hal_txbf_8814a_reset_tx_path(p_dm_void, idx) -#define hal_txbf_8814a_get_tx_rate(p_dm_void) -#define hal_txbf_8814a_fw_txbf(p_dm_void, idx) -#define phydm_beamforming_set_iqgen_8814A(p_dm_void) 0 +#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8814a_get_ntx(dm_void) 0 +#define hal_txbf_8814a_enter(dm_void, idx) +#define hal_txbf_8814a_leave(dm_void, idx) +#define hal_txbf_8814a_status(dm_void, idx) +#define hal_txbf_8814a_reset_tx_path(dm_void, idx) +#define hal_txbf_8814a_get_tx_rate(dm_void) +#define hal_txbf_8814a_fw_txbf(dm_void, idx) +#define phydm_beamforming_set_iqgen_8814A(dm_void) 0 #endif #endif diff --git a/hal/phydm/txbf/haltxbf8822b.c b/hal/phydm/txbf/haltxbf8822b.c index df72b55..bcb9b47 100644 --- a/hal/phydm/txbf/haltxbf8822b.c +++ b/hal/phydm/txbf/haltxbf8822b.c @@ -1,9 +1,23 @@ -/*============================================================*/ -/* Description: */ -/* */ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/*@============================================================*/ +/* @Description: */ +/* @*/ /* This file is for 8814A TXBF mechanism */ -/* */ -/*============================================================*/ +/* @*/ +/*@============================================================*/ #include "mp_precomp.h" #include "phydm_precomp.h" @@ -11,150 +25,141 @@ #if (RTL8822B_SUPPORT == 1) #if (BEAMFORMING_SUPPORT == 1) -u8 -hal_txbf_8822b_get_ntx( - void *p_dm_void -) +u8 hal_txbf_8822b_get_ntx( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 ntx = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ntx = 0; #if DEV_BUS_TYPE == RT_USB_INTERFACE - if (p_dm_odm->support_interface == ODM_ITRF_USB) { - if (*p_dm_odm->hub_usb_mode == 2) {/*USB3.0*/ - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->support_interface == ODM_ITRF_USB) { + if (*dm->hub_usb_mode == 2) { /*USB3.0*/ + if (dm->rf_type == RF_4T4R) ntx = 3; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) ntx = 2; else ntx = 1; - } else if (*p_dm_odm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ + } else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ ntx = 1; else ntx = 1; } else #endif { - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->rf_type == RF_4T4R) ntx = 3; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) ntx = 2; else ntx = 1; } return ntx; - } -u8 -hal_txbf_8822b_get_nrx( - void *p_dm_void -) +u8 hal_txbf_8822b_get_nrx( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 nrx = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 nrx = 0; - if (p_dm_odm->rf_type == ODM_4T4R) + if (dm->rf_type == RF_4T4R) nrx = 3; - else if (p_dm_odm->rf_type == ODM_3T3R) + else if (dm->rf_type == RF_3T3R) nrx = 2; - else if (p_dm_odm->rf_type == ODM_2T2R) + else if (dm->rf_type == RF_2T2R) nrx = 1; - else if (p_dm_odm->rf_type == ODM_2T3R) + else if (dm->rf_type == RF_2T3R) nrx = 2; - else if (p_dm_odm->rf_type == ODM_2T4R) + else if (dm->rf_type == RF_2T4R) nrx = 3; - else if (p_dm_odm->rf_type == ODM_1T1R) + else if (dm->rf_type == RF_1T1R) nrx = 0; - else if (p_dm_odm->rf_type == ODM_1T2R) + else if (dm->rf_type == RF_1T2R) nrx = 1; else nrx = 0; return nrx; - } /***************SU & MU BFee Entry********************/ -void -hal_txbf_8822b_rf_mode( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beamforming_info, - u8 idx -) +void hal_txbf_8822b_rf_mode( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beamforming_info, + u8 idx) { #if 0 - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 i, nr_index = 0; boolean is_self_beamformer = false; boolean is_self_beamformee = false; struct _RT_BEAMFORMEE_ENTRY beamformee_entry; if (idx < BEAMFORMEE_ENTRY_NUM) - beamformee_entry = p_beamforming_info->beamformee_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; else return; - if (p_dm_odm->rf_type == ODM_1T1R) + if (dm->rf_type == RF_1T1R) return; - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_welut_jaguar, 0x80000, 0x1); + for (i = RF_PATH_A; i < RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x1); /*RF mode table write enable*/ } - if ((p_beamforming_info->beamformee_su_cnt > 0) || (p_beamforming_info->beamformee_mu_cnt > 0)) { - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_mode_table_addr, 0xfffff, 0x18000); + if (beamforming_info->beamformee_su_cnt > 0 || beamforming_info->beamformee_mu_cnt > 0) { + for (i = RF_PATH_A; i < RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_addr, 0xfffff, 0x18000); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_mode_table_data0, 0xfffff, 0xBE77F); + odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data0, 0xfffff, 0xBE77F); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_mode_table_data1, 0xfffff, 0x226BF); - /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data1, 0xfffff, 0x226BF); + /*@Enable TXIQGEN in RX mode*/ } - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, rf_mode_table_data1, 0xfffff, 0xE26BF); - /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, rf_mode_table_data1, 0xfffff, 0xE26BF); + /*@Enable TXIQGEN in RX mode*/ } - for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, rf_welut_jaguar, 0x80000, 0x0); + for (i = RF_PATH_A; i < RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x0); /*RF mode table write disable*/ } - if (p_beamforming_info->beamformee_su_cnt > 0) { - - /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + if (beamforming_info->beamformee_su_cnt > 0) { + /*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/ if (idx == 0) { /*Nsts = 2 AB*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - /*odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430);*/ - - } else {/*IDX =1*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); - /*odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430;*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + /*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430);*/ + + } else {/*@IDX =1*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + /*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430;*/ } } else { - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*2SS by path-A,B*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/ } - if (p_beamforming_info->beamformee_mu_cnt > 0) { - /*MU STAs share the common setting*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + if (beamforming_info->beamformee_mu_cnt > 0) { + /*@MU STAs share the common setting*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); } #endif } #if 0 void hal_txbf_8822b_download_ndpa( - struct _ADAPTER *adapter, + void *adapter, u8 idx ) { @@ -162,13 +167,13 @@ hal_txbf_8822b_download_ndpa( u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; u16 head_page = 0x7FE; boolean is_send_beacon = false; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ - struct _RT_BEAMFORMING_INFO *p_beam_info = GET_BEAMFORM_INFO(adapter); - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/ + struct _RT_BEAMFORMING_INFO *beam_info = GET_BEAMFORM_INFO(adapter); + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; - p_hal_data->is_fw_dw_rsvd_page_in_progress = true; - phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); + hal_data->is_fw_dw_rsvd_page_in_progress = true; + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); /*Set REG_CR bit 8. DMA beacon by SW.*/ u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1); @@ -184,21 +189,21 @@ hal_txbf_8822b_download_ndpa( is_send_beacon = true; } - /*0x204[11:0] Beacon Head for TXDMA*/ + /*@0x204[11:0] Beacon Head for TXDMA*/ platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, head_page); do { - /*Clear beacon valid check bit.*/ + /*@Clear beacon valid check bit.*/ bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); platform_efio_write_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7))); - /*download NDPA rsvd page.*/ + /*@download NDPA rsvd page.*/ if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) - beamforming_send_vht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); else - beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); - /*check rsvd page download OK.*/ + /*@check rsvd page download OK.*/ bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); count = 0; while (!(bcn_valid_reg & BIT(7)) && count < 20) { @@ -212,45 +217,45 @@ hal_txbf_8822b_download_ndpa( if (!(bcn_valid_reg & BIT(0))) RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__)); - /*0x204[11:0] Beacon Head for TXDMA*/ + /*@0x204[11:0] Beacon Head for TXDMA*/ platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy); /*To make sure that if there exists an adapter which would like to send beacon.*/ - /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ /*the beacon cannot be sent by HW.*/ - /*2010.06.23. Added by tynli.*/ + /*@2010.06.23. Added by tynli.*/ if (is_send_beacon) platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422); - /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ - /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + /*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1); platform_efio_write_1byte(adapter, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0)))); p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; - p_hal_data->is_fw_dw_rsvd_page_in_progress = false; + hal_data->is_fw_dw_rsvd_page_in_progress = false; } void hal_txbf_8822b_fw_txbf_cmd( - struct _ADAPTER *adapter + void *adapter ) { u8 idx, period = 0; u8 PageNum0 = 0xFF, PageNum1 = 0xFF; u8 u1_tx_bf_parm[3] = {0}; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); - struct _RT_BEAMFORMING_INFO *p_beam_info = GET_BEAMFORM_INFO(adapter); + PMGNT_INFO mgnt_info = &(adapter->MgntInfo); + struct _RT_BEAMFORMING_INFO *beam_info = GET_BEAMFORM_INFO(adapter); for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (p_beam_info->beamformee_entry[idx].is_sound) { + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beam_info->beamformee_entry[idx].is_sound) { PageNum0 = 0xFE; PageNum1 = 0x07; - period = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period = (u8)(beam_info->beamformee_entry[idx].sound_period); } else if (PageNum0 == 0xFF) { PageNum0 = 0xFF; /*stop sounding*/ PageNum1 = 0x0F; @@ -270,108 +275,107 @@ hal_txbf_8822b_fw_txbf_cmd( #if 0 void hal_txbf_8822b_init( - void *p_dm_void + void *dm_void ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 u1b_tmp; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + void *adapter = dm->adapter; - odm_set_bb_reg(p_dm_odm, 0x14c0, BIT(16), 1); /*Enable P1 aggr new packet according to P0 transfer time*/ - odm_set_bb_reg(p_dm_odm, 0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*MU Retry Limit*/ - odm_set_bb_reg(p_dm_odm, 0x14c0, BIT(7), 0); /*Disable Tx MU-MIMO until sounding done*/ - odm_set_bb_reg(p_dm_odm, 0x14c0, 0x3F, 0); /* Clear validity of MU STAs */ - odm_write_1byte(p_dm_odm, 0x167c, 0x70); /*MU-MIMO Option as default value*/ - odm_write_2byte(p_dm_odm, 0x1680, 0); /*MU-MIMO Control as default value*/ + odm_set_bb_reg(dm, R_0x14c0, BIT(16), 1); /*@Enable P1 aggr new packet according to P0 transfer time*/ + odm_set_bb_reg(dm, R_0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*@MU Retry Limit*/ + odm_set_bb_reg(dm, R_0x14c0, BIT(7), 0); /*@Disable Tx MU-MIMO until sounding done*/ + odm_set_bb_reg(dm, R_0x14c0, 0x3F, 0); /* @Clear validity of MU STAs */ + odm_write_1byte(dm, 0x167c, 0x70); /*@MU-MIMO Option as default value*/ + odm_write_2byte(dm, 0x1680, 0); /*@MU-MIMO Control as default value*/ /* Set MU NDPA rate & BW source */ - /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ - u1b_tmp = odm_read_1byte(p_dm_odm, 0x42C); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B, (u1b_tmp | BIT(6))); - /* 0x45F[7:0] = 0x10 (rate=OFDM_6M, BW20) */ - odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8822B, 0x10); + /* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ + u1b_tmp = odm_read_1byte(dm, 0x42C); + odm_write_1byte(dm, REG_TXBF_CTRL_8822B, (u1b_tmp | BIT(6))); + /* @0x45F[7:0] = 0x10 (rate=OFDM_6M, BW20) */ + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, 0x10); /*Temp Settings*/ - odm_set_bb_reg(p_dm_odm, 0x6DC, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/ - odm_set_bb_reg(p_dm_odm, 0x1C94, MASKDWORD, 0xAFFFAFFF); /*Grouping bitmap parameters*/ + odm_set_bb_reg(dm, R_0x6dc, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/ + odm_set_bb_reg(dm, R_0x1c94, MASKDWORD, 0xAFFFAFFF); /*@Grouping bitmap parameters*/ - /* Init HW variable */ - p_beamforming_info->reg_mu_tx_ctrl = odm_read_4byte(p_dm_odm, 0x14c0); + /* @Init HW variable */ + beamforming_info->reg_mu_tx_ctrl = odm_read_4byte(dm, 0x14c0); - if (p_dm_odm->rf_type == ODM_2T2R) { /*2T2R*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: rf_type is 2T2R\n", __func__)); - config_phydm_trx_mode_8822b(p_dm_odm, (enum odm_rf_path_e)3, (enum odm_rf_path_e)3, true);/*Tx2path*/ + if (dm->rf_type == RF_2T2R) { /*@2T2R*/ + PHYDM_DBG(dm, DBG_TXBF, "%s: rf_type is 2T2R\n", __func__); + config_phydm_trx_mode_8822b(dm, (enum bb_path)3, (enum bb_path)3, true);/*Tx2path*/ } #if (OMNIPEEK_SNIFFER_ENABLED == 1) - /* Config HW to receive packet on the user position from registry for sniffer mode. */ - /* odm_set_bb_reg(p_dm_odm, 0xB00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */ - odm_set_bb_reg(p_dm_odm, 0xB54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */ - odm_set_bb_reg(p_dm_odm, 0xB54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Set adapter->MgntInfo.sniff_user_position=%#X\n", adapter->MgntInfo.sniff_user_position)); + /* @Config HW to receive packet on the user position from registry for sniffer mode. */ + /* odm_set_bb_reg(dm, R_0xb00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */ + odm_set_bb_reg(dm, R_0xb54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */ + odm_set_bb_reg(dm, R_0xb54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */ + PHYDM_DBG(dm, DBG_TXBF, + "Set adapter->MgntInfo.sniff_user_position=%#X\n", + adapter->MgntInfo.sniff_user_position); #endif } #endif -void -hal_txbf_8822b_enter( - void *p_dm_void, - u8 bfer_bfee_idx -) +void hal_txbf_8822b_enter( + void *dm_void, + u8 bfer_bfee_idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i = 0; - u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; - u8 bfee_idx = (bfer_bfee_idx & 0xF); - u16 csi_param = 0; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry; - struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry; - u16 value16, sta_id = 0; - u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; - u32 gid_valid, user_position_l, user_position_h; - u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; - u8 u1b_tmp; - u32 u4b_tmp; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + u16 csi_param = 0; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry; + u16 value16, sta_id = 0; + u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; + u32 gid_valid, user_position_l, user_position_h; + u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; + u8 u1b_tmp; + u32 u4b_tmp; RT_DISP(FBEAM, FBEAM_FUN, ("%s: bfer_bfee_idx=%d, bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_bfee_idx, bfer_idx, bfee_idx)); /*************SU BFer Entry Init*************/ - if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { - p_beamformer_entry = &p_beamforming_info->beamformer_entry[bfer_idx]; - p_beamformer_entry->is_mu_ap = false; + if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx]; + beamformer_entry->is_mu_ap = false; /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xDB); - + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB); for (i = 0; i < MAX_BEAMFORMER_SU; i++) { - if ((p_beamforming_info->beamformer_su_reg_maping & BIT(i)) == 0) { - p_beamforming_info->beamformer_su_reg_maping |= BIT(i); - p_beamformer_entry->su_reg_index = i; + if ((beamforming_info->beamformer_su_reg_maping & BIT(i)) == 0) { + beamforming_info->beamformer_su_reg_maping |= BIT(i); + beamformer_entry->su_reg_index = i; break; } } - /*MAC address/Partial AID of Beamformer*/ - if (p_beamformer_entry->su_reg_index == 0) { - for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), p_beamformer_entry->mac_addr[i]); + /*@MAC address/Partial AID of Beamformer*/ + if (beamformer_entry->su_reg_index == 0) { + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]); } else { - for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER1_INFO_8822B + i), p_beamformer_entry->mac_addr[i]); + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8822B + i), beamformer_entry->mac_addr[i]); } - /*CSI report parameters of Beamformer*/ - nc_index = hal_txbf_8822b_get_nrx(p_dm_odm); /*for 8814A nrx = 3(4 ant), min=0(1 ant)*/ - nr_index = p_beamformer_entry->num_of_sounding_dim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ + /*@CSI report parameters of Beamformer*/ + nc_index = hal_txbf_8822b_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/ + nr_index = beamformer_entry->num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ grouping = 0; - /*for ac = 1, for n = 3*/ - if (p_beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) + /*@for ac = 1, for n = 3*/ + if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) codebookinfo = 1; - else if (p_beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT) + else if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT) codebookinfo = 3; coefficientsize = 3; @@ -379,28 +383,27 @@ hal_txbf_8822b_enter( csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); if (bfer_idx == 0) - odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param); + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param); else - odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, csi_param); + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, csi_param); /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B + 3, 0x70); - + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B + 3, 0x70); } /*************SU BFee Entry Init*************/ - if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { - p_beamformee_entry = &p_beamforming_info->beamformee_entry[bfee_idx]; + if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) { + p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx]; p_beamformee_entry->is_mu_sta = false; - hal_txbf_8822b_rf_mode(p_dm_odm, p_beamforming_info, bfee_idx); + hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx); - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) sta_id = p_beamformee_entry->mac_id; else sta_id = p_beamformee_entry->p_aid; for (i = 0; i < MAX_BEAMFORMEE_SU; i++) { - if ((p_beamforming_info->beamformee_su_reg_maping & BIT(i)) == 0) { - p_beamforming_info->beamformee_su_reg_maping |= BIT(i); + if ((beamforming_info->beamformee_su_reg_maping & BIT(i)) == 0) { + beamforming_info->beamformee_su_reg_maping |= BIT(i); p_beamformee_entry->su_reg_index = i; break; } @@ -408,83 +411,82 @@ hal_txbf_8822b_enter( /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ if (p_beamformee_entry->su_reg_index == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B, sta_id); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_TXBF_CTRL_8822B, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); } else - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); + odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); - /*CSI report parameters of Beamformee*/ + /*@CSI report parameters of Beamformee*/ if (p_beamformee_entry->su_reg_index == 0) { - /*Get BIT24 & BIT25*/ - u8 tmp = odm_read_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3; + /*@Get BIT24 & BIT25*/ + u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3; - odm_write_1byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B, sta_id | BIT(9)); + odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, sta_id | BIT(9)); } else - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/ + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/ - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); } /*************MU BFer Entry Init*************/ - if ((p_beamforming_info->beamformer_mu_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { - p_beamformer_entry = &p_beamforming_info->beamformer_entry[bfer_idx]; - p_beamforming_info->mu_ap_index = bfer_idx; - p_beamformer_entry->is_mu_ap = true; + if (beamforming_info->beamformer_mu_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx]; + beamforming_info->mu_ap_index = bfer_idx; + beamformer_entry->is_mu_ap = true; for (i = 0; i < 8; i++) - p_beamformer_entry->gid_valid[i] = 0; + beamformer_entry->gid_valid[i] = 0; for (i = 0; i < 16; i++) - p_beamformer_entry->user_position[i] = 0; + beamformer_entry->user_position[i] = 0; /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB); - /* MAC address */ - for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), p_beamformer_entry->mac_addr[i]); + /* @MAC address */ + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]); /* Set partial AID */ - odm_write_2byte(p_dm_odm, (REG_ASSOCIATED_BFMER0_INFO_8822B + 6), p_beamformer_entry->p_aid); + odm_write_2byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + 6), beamformer_entry->p_aid); - /* Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/ - u1b_tmp = odm_read_1byte(p_dm_odm, 0x1680); - u1b_tmp = (p_beamformer_entry->p_aid) & 0xFFF; - odm_write_1byte(p_dm_odm, 0x1680, u1b_tmp); + /* @Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/ + u1b_tmp = odm_read_1byte(dm, 0x1680); + u1b_tmp = (beamformer_entry->p_aid) & 0xFFF; + odm_write_1byte(dm, 0x1680, u1b_tmp); /* Set 80us for leaving ndp_rx_standby_state */ - odm_write_1byte(p_dm_odm, 0x71B, 0x50); + odm_write_1byte(dm, 0x71B, 0x50); /* Set 0x6A0[14] = 1 to accept action_no_ack */ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1); + u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1); u1b_tmp |= 0x40; - odm_write_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); + odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_RXFLTMAP1_8822B); + u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP1_8822B); u1b_tmp |= 0x30; - odm_write_1byte(p_dm_odm, REG_RXFLTMAP1_8822B, u1b_tmp); + odm_write_1byte(dm, REG_RXFLTMAP1_8822B, u1b_tmp); - /*CSI report parameters of Beamformer*/ - nc_index = hal_txbf_8822b_get_nrx(p_dm_odm); /* Depend on RF type */ - nr_index = 1; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ + /*@CSI report parameters of Beamformer*/ + nc_index = hal_txbf_8822b_get_nrx(dm); /* @Depend on RF type */ + nr_index = 1; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ grouping = 0; /*no grouping*/ - codebookinfo = 1; /*7 bit for psi, 9 bit for phi*/ + codebookinfo = 1; /*@7 bit for psi, 9 bit for phi*/ coefficientsize = 0; /*This is nothing really matter*/ csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); - odm_write_2byte(p_dm_odm, 0x6F4, csi_param); - - /*for B-cut*/ - odm_set_bb_reg(p_dm_odm, 0x6A0, BIT(20), 0); - odm_set_bb_reg(p_dm_odm, 0x688, BIT(20), 0); + odm_write_2byte(dm, 0x6F4, csi_param); + /*@for B-cut*/ + odm_set_bb_reg(dm, R_0x6a0, BIT(20), 0); + odm_set_bb_reg(dm, R_0x688, BIT(20), 0); } /*************MU BFee Entry Init*************/ - if ((p_beamforming_info->beamformee_mu_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { - p_beamformee_entry = &p_beamforming_info->beamformee_entry[bfee_idx]; + if (beamforming_info->beamformee_mu_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) { + p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx]; p_beamformee_entry->is_mu_sta = true; for (i = 0; i < MAX_BEAMFORMEE_MU; i++) { - if ((p_beamforming_info->beamformee_mu_reg_maping & BIT(i)) == 0) { - p_beamforming_info->beamformee_mu_reg_maping |= BIT(i); + if ((beamforming_info->beamformee_mu_reg_maping & BIT(i)) == 0) { + beamforming_info->beamformee_mu_reg_maping |= BIT(i); p_beamformee_entry->mu_reg_index = i; break; } @@ -547,259 +549,264 @@ hal_txbf_8822b_enter( } /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB); /*select MU STA table*/ - p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); - p_beamforming_info->reg_mu_tx_ctrl |= (p_beamformee_entry->mu_reg_index << 8) & (BIT(8) | BIT(9) | BIT(10)); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + beamforming_info->reg_mu_tx_ctrl |= (p_beamformee_entry->mu_reg_index << 8) & (BIT(8) | BIT(9) | BIT(10)); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); - odm_set_bb_reg(p_dm_odm, 0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/ - odm_set_bb_reg(p_dm_odm, 0x14c8, MASKDWORD, user_position_l); - odm_set_bb_reg(p_dm_odm, 0x14cc, MASKDWORD, user_position_h); + odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/ + odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h); /*set validity of MU STAs*/ - p_beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; - p_beamforming_info->reg_mu_tx_ctrl |= p_beamforming_info->beamformee_mu_reg_maping & 0x3F; - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, p_beamforming_info->reg_mu_tx_ctrl, user_position_l, user_position_h)); - - value16 = odm_read_2byte(p_dm_odm, mu_reg[p_beamformee_entry->mu_reg_index]); - value16 &= 0xFE00; /*Clear PAID*/ - value16 |= BIT(9); /*Enable MU BFee*/ + beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + beamforming_info->reg_mu_tx_ctrl |= beamforming_info->beamformee_mu_reg_maping & 0x3F; + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + + PHYDM_DBG(dm, DBG_TXBF, + "@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, beamforming_info->reg_mu_tx_ctrl, + user_position_l, user_position_h); + + value16 = odm_read_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index]); + value16 &= 0xFE00; /*@Clear PAID*/ + value16 |= BIT(9); /*@Enable MU BFee*/ value16 |= p_beamformee_entry->p_aid; - odm_write_2byte(p_dm_odm, mu_reg[p_beamformee_entry->mu_reg_index], value16); + odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], value16); - /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3); + /* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ + u1b_tmp = odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3); u1b_tmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/ - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3, u1b_tmp); + odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, u1b_tmp); /* Set NDPA to 6M*/ - odm_write_1byte(p_dm_odm, REG_NDPA_RATE_8822B, 0x4); + odm_write_1byte(dm, REG_NDPA_RATE_8822B, 0x4); - u1b_tmp = odm_read_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8822B); - u1b_tmp &= 0xFC; /* Clear bit 0, 1*/ - odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8822B, u1b_tmp); + u1b_tmp = odm_read_1byte(dm, REG_NDPA_OPT_CTRL_8822B); + u1b_tmp &= 0xFC; /* @Clear bit 0, 1*/ + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, u1b_tmp); - u4b_tmp = odm_read_4byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B); + u4b_tmp = odm_read_4byte(dm, REG_SND_PTCL_CTRL_8822B); u4b_tmp = ((u4b_tmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202*/ - odm_write_4byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, u4b_tmp); + odm_write_4byte(dm, REG_SND_PTCL_CTRL_8822B, u4b_tmp); /* Set 0x6A0[14] = 1 to accept action_no_ack */ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1); + u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1); u1b_tmp |= 0x40; - odm_write_1byte(p_dm_odm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); - /* End of MAC registers setting */ + odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); + /* @End of MAC registers setting */ - hal_txbf_8822b_rf_mode(p_dm_odm, p_beamforming_info, bfee_idx); + hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx); #if (SUPPORT_MU_BF == 1) /*Special for plugfest*/ delay_ms(50); /* wait for 4-way handshake ending*/ - send_sw_vht_gid_mgnt_frame(p_dm_odm, p_beamformee_entry->mac_addr, bfee_idx); + send_sw_vht_gid_mgnt_frame(dm, p_beamformee_entry->mac_addr, bfee_idx); #endif - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); #if 1 { u32 ctrl_info_offset, index; /*Set Ctrl Info*/ - odm_write_2byte(p_dm_odm, 0x140, 0x660); + odm_write_2byte(dm, 0x140, 0x660); ctrl_info_offset = 0x8000 + 32 * p_beamformee_entry->mac_id; /*Reset Ctrl Info*/ for (index = 0; index < 8; index++) - odm_write_4byte(p_dm_odm, ctrl_info_offset + index * 4, 0); + odm_write_4byte(dm, ctrl_info_offset + index * 4, 0); - odm_write_4byte(p_dm_odm, ctrl_info_offset, (p_beamformee_entry->mu_reg_index + 1) << 16); - odm_write_1byte(p_dm_odm, 0x81, 0x80); /*RPTBUF ready*/ + odm_write_4byte(dm, ctrl_info_offset, (p_beamformee_entry->mu_reg_index + 1) << 16); + odm_write_1byte(dm, 0x81, 0x80); /*RPTBUF ready*/ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n", - __func__, p_beamformee_entry->mac_id, ctrl_info_offset, p_beamformee_entry->mu_reg_index)); + PHYDM_DBG(dm, DBG_TXBF, + "@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n", + __func__, p_beamformee_entry->mac_id, + ctrl_info_offset, + p_beamformee_entry->mu_reg_index); } #endif } - } - -void -hal_txbf_8822b_leave( - void *p_dm_void, - u8 idx -) +void hal_txbf_8822b_leave( + void *dm_void, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry; - struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry; - u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry; + struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry; + u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; if (idx < BEAMFORMER_ENTRY_NUM) { - p_beamformer_entry = &p_beamforming_info->beamformer_entry[idx]; - p_beamformee_entry = &p_beamforming_info->beamformee_entry[idx]; + beamformer_entry = &beamforming_info->beamformer_entry[idx]; + p_beamformee_entry = &beamforming_info->beamformee_entry[idx]; } else return; - /*Clear P_AID of Beamformee*/ - /*Clear MAC address of Beamformer*/ - /*Clear Associated Bfmee Sel*/ - - if (p_beamformer_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) { - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8822B, 0xD8); - if (p_beamformer_entry->is_mu_ap == 0) { /*SU BFer */ - if (p_beamformer_entry->su_reg_index == 0) { - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER0_INFO_8822B + 4, 0); - odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); + /*@Clear P_AID of Beamformee*/ + /*@Clear MAC address of Beamformer*/ + /*@Clear Associated Bfmee Sel*/ + + if (beamformer_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) { + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xD8); + if (beamformer_entry->is_mu_ap == 0) { /*SU BFer */ + if (beamformer_entry->su_reg_index == 0) { + odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B + 4, 0); + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); } else { - odm_write_4byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMER1_INFO_8822B + 4, 0); - odm_write_2byte(p_dm_odm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, 0); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B + 4, 0); + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, 0); } - p_beamforming_info->beamformer_su_reg_maping &= ~(BIT(p_beamformer_entry->su_reg_index)); - p_beamformer_entry->su_reg_index = 0xFF; - } else { /*MU BFer */ + beamforming_info->beamformer_su_reg_maping &= ~(BIT(beamformer_entry->su_reg_index)); + beamformer_entry->su_reg_index = 0xFF; + } else { /*@MU BFer */ /*set validity of MU STA0 and MU STA1*/ - p_beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); - odm_memory_set(p_dm_odm, p_beamformer_entry->gid_valid, 0, 8); - odm_memory_set(p_dm_odm, p_beamformer_entry->user_position, 0, 16); - p_beamformer_entry->is_mu_ap = false; + odm_memory_set(dm, beamformer_entry->gid_valid, 0, 8); + odm_memory_set(dm, beamformer_entry->user_position, 0, 16); + beamformer_entry->is_mu_ap = false; } } if (p_beamformee_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) { - hal_txbf_8822b_rf_mode(p_dm_odm, p_beamforming_info, idx); + hal_txbf_8822b_rf_mode(dm, beamforming_info, idx); if (p_beamformee_entry->is_mu_sta == 0) { /*SU BFee*/ if (p_beamformee_entry->su_reg_index == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B, 0x0); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); + odm_write_2byte(dm, REG_TXBF_CTRL_8822B, 0x0); + odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); } else { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); + odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); - odm_write_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, - odm_read_2byte(p_dm_odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, + odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60); } - p_beamforming_info->beamformee_su_reg_maping &= ~(BIT(p_beamformee_entry->su_reg_index)); + beamforming_info->beamformee_su_reg_maping &= ~(BIT(p_beamformee_entry->su_reg_index)); p_beamformee_entry->su_reg_index = 0xFF; - } else { /*MU BFee */ - /*Disable sending NDPA & BF-rpt-poll to this BFee*/ - odm_write_2byte(p_dm_odm, mu_reg[p_beamformee_entry->mu_reg_index], 0); + } else { /*@MU BFee */ + /*@Disable sending NDPA & BF-rpt-poll to this BFee*/ + odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], 0); /*set validity of MU STA*/ - p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(p_beamformee_entry->mu_reg_index)); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(p_beamformee_entry->mu_reg_index)); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); p_beamformee_entry->is_mu_sta = false; - p_beamforming_info->beamformee_mu_reg_maping &= ~(BIT(p_beamformee_entry->mu_reg_index)); + beamforming_info->beamformee_mu_reg_maping &= ~(BIT(p_beamformee_entry->mu_reg_index)); p_beamformee_entry->mu_reg_index = 0xFF; } } } - /***********SU & MU BFee Entry Only when souding done****************/ -void -hal_txbf_8822b_status( - void *p_dm_void, - u8 beamform_idx -) +void hal_txbf_8822b_status( + void *dm_void, + u8 beamform_idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u16 beam_ctrl_val, tmp_val; - u32 beam_ctrl_reg; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry; - boolean is_mu_sounding = p_beamforming_info->is_mu_sounding, is_bitmap_ready = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 beam_ctrl_val, tmp_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry; + boolean is_mu_sounding = beamforming_info->is_mu_sounding, is_bitmap_ready = false; u16 bitmap; u8 idx, gid, i; u8 id1, id0; u32 gid_valid[6] = {0}; - u32 user_position_lsb[6] = {0}; - u32 user_position_msb[6] = {0}; u32 value32; boolean is_sounding_success[6] = {false}; if (beamform_idx < BEAMFORMEE_ENTRY_NUM) - p_beamform_entry = &p_beamforming_info->beamformee_entry[beamform_idx]; + beamform_entry = &beamforming_info->beamformee_entry[beamform_idx]; else return; /*SU sounding done */ if (is_mu_sounding == false) { - - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) - beam_ctrl_val = p_beamform_entry->mac_id; + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) + beam_ctrl_val = beamform_entry->mac_id; else - beam_ctrl_val = p_beamform_entry->p_aid; + beam_ctrl_val = beamform_entry->p_aid; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, beamform_entry.beamform_entry_state = %d", __func__, p_beamform_entry->beamform_entry_state)); + PHYDM_DBG(dm, DBG_TXBF, + "@%s, beamform_entry.beamform_entry_state = %d", + __func__, beamform_entry->beamform_entry_state); - if (p_beamform_entry->su_reg_index == 0) + if (beamform_entry->su_reg_index == 0) beam_ctrl_reg = REG_TXBF_CTRL_8822B; else { beam_ctrl_reg = REG_TXBF_CTRL_8822B + 2; beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { - if (p_beamform_entry->sound_bw == CHANNEL_WIDTH_20) + if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beamform_entry->sound_bw == CHANNEL_WIDTH_20) beam_ctrl_val |= BIT(9); - else if (p_beamform_entry->sound_bw == CHANNEL_WIDTH_40) + else if (beamform_entry->sound_bw == CHANNEL_WIDTH_40) beam_ctrl_val |= (BIT(9) | BIT(10)); - else if (p_beamform_entry->sound_bw == CHANNEL_WIDTH_80) + else if (beamform_entry->sound_bw == CHANNEL_WIDTH_80) beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11)); } else { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", + __func__); beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); } - odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); - /*disable NDP packet use beamforming */ - tmp_val = odm_read_2byte(p_dm_odm, REG_TXBF_CTRL_8822B); - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8822B, tmp_val | BIT(15)); + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); + /*@disable NDP packet use beamforming */ + tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8822B); + odm_write_2byte(dm, REG_TXBF_CTRL_8822B, tmp_val | BIT(15)); } else { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, MU Sounding Done\n", __func__)); - /*MU sounding done */ - if (1) { /* (p_beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */ - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n", __func__)); - - value32 = odm_get_bb_reg(p_dm_odm, 0x1684, MASKDWORD); + PHYDM_DBG(dm, DBG_TXBF, "@%s, MU Sounding Done\n", __func__); + /*@MU sounding done */ + if (1) { /* @(beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */ + PHYDM_DBG(dm, DBG_TXBF, + "@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n", + __func__); + + value32 = odm_get_bb_reg(dm, R_0x1684, MASKDWORD); is_sounding_success[0] = (value32 & BIT(10)) ? 1 : 0; is_sounding_success[1] = (value32 & BIT(26)) ? 1 : 0; - value32 = odm_get_bb_reg(p_dm_odm, 0x1688, MASKDWORD); + value32 = odm_get_bb_reg(dm, R_0x1688, MASKDWORD); is_sounding_success[2] = (value32 & BIT(10)) ? 1 : 0; is_sounding_success[3] = (value32 & BIT(26)) ? 1 : 0; - value32 = odm_get_bb_reg(p_dm_odm, 0x168C, MASKDWORD); + value32 = odm_get_bb_reg(dm, R_0x168c, MASKDWORD); is_sounding_success[4] = (value32 & BIT(10)) ? 1 : 0; is_sounding_success[5] = (value32 & BIT(26)) ? 1 : 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n", - __func__, is_sounding_success[0], is_sounding_success[1], is_sounding_success[2], is_sounding_success[3], is_sounding_success[4], is_sounding_success[5])); + PHYDM_DBG(dm, DBG_TXBF, + "@%s, is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n", + __func__, is_sounding_success[0], + is_sounding_success[1], + is_sounding_success[2], + is_sounding_success[3], + is_sounding_success[4], + is_sounding_success[5]); - value32 = odm_get_bb_reg(p_dm_odm, 0xF4C, 0xFFFF0000); - /* odm_set_bb_reg(p_dm_odm, 0x19E0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */ + value32 = odm_get_bb_reg(dm, R_0xf4c, 0xFFFF0000); + /* odm_set_bb_reg(dm, R_0x19e0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */ is_bitmap_ready = (boolean)((value32 & BIT(15)) >> 15); bitmap = (u16)(value32 & 0x3FFF); for (idx = 0; idx < 15; idx++) { - if (idx < 5) {/*bit0~4*/ + if (idx < 5) { /*@bit0~4*/ id0 = 0; id1 = (u8)(idx + 1); - } else if (idx < 9) { /*bit5~8*/ + } else if (idx < 9) { /*@bit5~8*/ id0 = 1; id1 = (u8)(idx - 3); - } else if (idx < 12) { /*bit9~11*/ + } else if (idx < 12) { /*@bit9~11*/ id0 = 2; id1 = (u8)(idx - 6); - } else if (idx < 14) { /*bit12~13*/ + } else if (idx < 14) { /*@bit12~13*/ id0 = 3; id1 = (u8)(idx - 8); - } else { /*bit14*/ + } else { /*@bit14*/ id0 = 4; id1 = (u8)(idx - 9); } @@ -825,108 +832,105 @@ hal_txbf_8822b_status( } for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { - p_beamform_entry = &p_beamforming_info->beamformee_entry[i]; - if ((p_beamform_entry->is_mu_sta) && (p_beamform_entry->mu_reg_index < 6)) { - value32 = gid_valid[p_beamform_entry->mu_reg_index]; + beamform_entry = &beamforming_info->beamformee_entry[i]; + if (beamform_entry->is_mu_sta && beamform_entry->mu_reg_index < 6) { + value32 = gid_valid[beamform_entry->mu_reg_index]; for (idx = 0; idx < 4; idx++) { - p_beamform_entry->gid_valid[idx] = (u8)(value32 & 0xFF); + beamform_entry->gid_valid[idx] = (u8)(value32 & 0xFF); value32 = (value32 >> 8); } } } for (idx = 0; idx < 6; idx++) { - p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); - p_beamforming_info->reg_mu_tx_ctrl |= ((idx << 8) & (BIT(8) | BIT(9) | BIT(10))); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - odm_set_mac_reg(p_dm_odm, 0x14C4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/ + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + beamforming_info->reg_mu_tx_ctrl |= ((idx << 8) & (BIT(8) | BIT(9) | BIT(10))); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + odm_set_mac_reg(dm, R_0x14c4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/ } - /*Enable TxMU PPDU*/ - if (p_beamforming_info->dbg_disable_mu_tx == false) - p_beamforming_info->reg_mu_tx_ctrl |= BIT(7); + /*@Enable TxMU PPDU*/ + if (beamforming_info->dbg_disable_mu_tx == false) + beamforming_info->reg_mu_tx_ctrl |= BIT(7); else - p_beamforming_info->reg_mu_tx_ctrl &= ~BIT(7); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); + beamforming_info->reg_mu_tx_ctrl &= ~BIT(7); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); } } } /*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ -void -hal_txbf_8822b_config_gtab( - void *p_dm_void -) +void hal_txbf_8822b_config_gtab( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry = NULL; - u32 gid_valid = 0, user_position_l = 0, user_position_h = 0, i; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; + u32 gid_valid = 0, user_position_l = 0, user_position_h = 0, i; - if (p_beamforming_info->mu_ap_index < BEAMFORMER_ENTRY_NUM) - p_beamformer_entry = &p_beamforming_info->beamformer_entry[p_beamforming_info->mu_ap_index]; + if (beamforming_info->mu_ap_index < BEAMFORMER_ENTRY_NUM) + beamformer_entry = &beamforming_info->beamformer_entry[beamforming_info->mu_ap_index]; else return; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s==>\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s==>\n", __func__); - /*For GID 0~31*/ + /*@For GID 0~31*/ for (i = 0; i < 4; i++) - gid_valid |= (p_beamformer_entry->gid_valid[i] << (i << 3)); + gid_valid |= (beamformer_entry->gid_valid[i] << (i << 3)); for (i = 0; i < 8; i++) { if (i < 4) - user_position_l |= (p_beamformer_entry->user_position[i] << (i << 3)); + user_position_l |= (beamformer_entry->user_position[i] << (i << 3)); else - user_position_h |= (p_beamformer_entry->user_position[i] << ((i - 4) << 3)); + user_position_h |= (beamformer_entry->user_position[i] << ((i - 4) << 3)); } /*select MU STA0 table*/ - p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - odm_set_bb_reg(p_dm_odm, 0x14c4, MASKDWORD, gid_valid); - odm_set_bb_reg(p_dm_odm, 0x14c8, MASKDWORD, user_position_l); - odm_set_bb_reg(p_dm_odm, 0x14cc, MASKDWORD, user_position_h); + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid); + odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, gid_valid, user_position_l, user_position_h)); + PHYDM_DBG(dm, DBG_TXBF, + "%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h); gid_valid = 0; user_position_l = 0; user_position_h = 0; - /*For GID 32~64*/ + /*@For GID 32~64*/ for (i = 4; i < 8; i++) - gid_valid |= (p_beamformer_entry->gid_valid[i] << ((i - 4) << 3)); + gid_valid |= (beamformer_entry->gid_valid[i] << ((i - 4) << 3)); for (i = 8; i < 16; i++) { if (i < 4) - user_position_l |= (p_beamformer_entry->user_position[i] << ((i - 8) << 3)); + user_position_l |= (beamformer_entry->user_position[i] << ((i - 8) << 3)); else - user_position_h |= (p_beamformer_entry->user_position[i] << ((i - 12) << 3)); + user_position_h |= (beamformer_entry->user_position[i] << ((i - 12) << 3)); } /*select MU STA1 table*/ - p_beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); - p_beamforming_info->reg_mu_tx_ctrl |= BIT(8); - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - odm_set_bb_reg(p_dm_odm, 0x14c4, MASKDWORD, gid_valid); - odm_set_bb_reg(p_dm_odm, 0x14c8, MASKDWORD, user_position_l); - odm_set_bb_reg(p_dm_odm, 0x14cc, MASKDWORD, user_position_h); + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + beamforming_info->reg_mu_tx_ctrl |= BIT(8); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid); + odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", - __func__, gid_valid, user_position_l, user_position_h)); + PHYDM_DBG(dm, DBG_TXBF, + "%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h); /* Set validity of MU STA0 and MU STA1*/ - p_beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; - p_beamforming_info->reg_mu_tx_ctrl |= 0x3; /* STA0, STA1*/ - odm_write_4byte(p_dm_odm, 0x14c0, p_beamforming_info->reg_mu_tx_ctrl); - + beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + beamforming_info->reg_mu_tx_ctrl |= 0x3; /* STA0, STA1*/ + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); } - - #if 0 /*This function translate the bitmap to GTAB*/ void haltxbf8822b_gtab_translation( - struct PHY_DM_STRUCT *p_dm_odm + struct dm_struct *dm ) { u8 idx, gid; @@ -936,19 +940,19 @@ haltxbf8822b_gtab_translation( u32 user_position_msb[6] = {0}; for (idx = 0; idx < 15; idx++) { - if (idx < 5) {/*bit0~4*/ + if (idx < 5) {/*@bit0~4*/ id0 = 0; id1 = (u8)(idx + 1); - } else if (idx < 9) { /*bit5~8*/ + } else if (idx < 9) { /*@bit5~8*/ id0 = 1; id1 = (u8)(idx - 3); - } else if (idx < 12) { /*bit9~11*/ + } else if (idx < 12) { /*@bit9~11*/ id0 = 2; id1 = (u8)(idx - 6); - } else if (idx < 14) { /*bit12~13*/ + } else if (idx < 14) { /*@bit12~13*/ id0 = 3; id1 = (u8)(idx - 8); - } else { /*bit14*/ + } else { /*@bit14*/ id0 = 4; id1 = (u8)(idx - 9); } @@ -976,26 +980,23 @@ haltxbf8822b_gtab_translation( user_position_msb[id0] |= (1 << ((gid - 16) << 1)); /*user_position_msb[id1] |= (0 << ((gid - 16) << 1));*/ } - } for (idx = 0; idx < 6; idx++) { - /*dbg_print("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]); + /*@dbg_print("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]); dbg_print("user_position[%d] = 0x%x %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/ } } #endif -void -hal_txbf_8822b_fw_txbf( - void *p_dm_void, - u8 idx -) +void hal_txbf_8822b_fw_txbf( + void *dm_void, + u8 idx) { #if 0 - struct _RT_BEAMFORMING_INFO *p_beam_info = GET_BEAMFORM_INFO(adapter); - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct _RT_BEAMFORMING_INFO *beam_info = GET_BEAMFORM_INFO(adapter); + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) hal_txbf_8822b_download_ndpa(adapter, idx); @@ -1008,93 +1009,79 @@ hal_txbf_8822b_fw_txbf( #if (defined(CONFIG_BB_TXBF_API)) /*this function is only used for BFer*/ -void -phydm_8822btxbf_rfmode( - void *p_dm_void, - u8 su_bfee_cnt, - u8 mu_bfee_cnt -) +void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i, nr_index = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i; - if (p_dm_odm->rf_type == ODM_1T1R) + if (dm->rf_type == RF_1T1R) return; - if ((su_bfee_cnt > 0) || (mu_bfee_cnt > 0)) { - for (i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++) { - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0xEF, BIT(19), 0x1); /*RF mode table write enable*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0x33, 0xF, 3); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0x3E, 0xfffff, 0x00036); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0x3F, 0xfffff, 0x5AFCE); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)i, 0xEF, BIT(19), 0x0); /*RF mode table write disable*/ + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + for (i = RF_PATH_A; i <= RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3); /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff, 0x00036); /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, 0x5AFCE); /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x0); /*RF mode table write disable*/ } } - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*if Nsts > Nc, don't apply V matrix*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*@if Nsts > Nc, don't apply V matrix*/ if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { - /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*ignore user since 8822B only 2Tx*/ - + /*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*@ignore user since 8822B only 2Tx*/ /*Nsts = 2 AB*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); } else { - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*enable BB TxBF ant mapping register*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*ignore user since 8822B only 2Tx*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*@ignore user since 8822B only 2Tx*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*1SS by path-A*/ - odm_set_bb_reg(p_dm_odm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*2SS by path-A,B*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/ } - } - /*this function is for BFer bug workaround*/ -void -phydm_8822b_sutxbfer_workaroud( - void *p_dm_void, - boolean enable_su_bfer, - u8 nc, - u8 nr, - u8 ng, - u8 CB, - u8 BW, - boolean is_vht -) +void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer, + u8 nc, u8 nr, u8 ng, u8 CB, u8 BW, + boolean is_vht) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; if (enable_su_bfer) { - odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1); - odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0); - odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(16), 0x1); + odm_set_bb_reg(dm, R_0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1); + odm_set_bb_reg(dm, R_0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0); + odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x1); if (is_vht) - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f); + odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f); else - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22); - - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(7) | BIT(6), nc); - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(9) | BIT(8), nr); - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(11) | BIT(10), ng); - odm_set_bb_reg(p_dm_odm, 0x19f0, BIT(13) | BIT(12), CB); - - odm_set_bb_reg(p_dm_odm, 0xb58, BIT(3) | BIT(2), BW); - odm_set_bb_reg(p_dm_odm, 0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0); - odm_set_bb_reg(p_dm_odm, 0xb58, BIT(9) | BIT(8), BW); - odm_set_bb_reg(p_dm_odm, 0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0); - } else - odm_set_bb_reg(p_dm_odm, 0x19f8, BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] enable_su_bfer = %d, is_vht = %d\n", __func__, enable_su_bfer, is_vht)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\n", __func__, nc, nr, ng, CB, BW)); + odm_set_bb_reg(dm, R_0x19f0, BIT(7) | BIT(6), nc); + odm_set_bb_reg(dm, R_0x19f0, BIT(9) | BIT(8), nr); + odm_set_bb_reg(dm, R_0x19f0, BIT(11) | BIT(10), ng); + odm_set_bb_reg(dm, R_0x19f0, BIT(13) | BIT(12), CB); + odm_set_bb_reg(dm, R_0xb58, BIT(3) | BIT(2), BW); + odm_set_bb_reg(dm, R_0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0); + odm_set_bb_reg(dm, R_0xb58, BIT(9) | BIT(8), BW); + odm_set_bb_reg(dm, R_0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0); + } else { + odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x0); + } + PHYDM_DBG(dm, DBG_TXBF, "[%s] enable_su_bfer = %d, is_vht = %d\n", + __func__, enable_su_bfer, is_vht); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\n", + __func__, nc, nr, ng, CB, BW); } #endif -#endif /* (RTL8822B_SUPPORT == 1)*/ +#endif /* @(RTL8822B_SUPPORT == 1)*/ diff --git a/hal/phydm/txbf/haltxbf8822b.h b/hal/phydm/txbf/haltxbf8822b.h index 6d2af54..4e9d447 100644 --- a/hal/phydm/txbf/haltxbf8822b.h +++ b/hal/phydm/txbf/haltxbf8822b.h @@ -1,79 +1,78 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ #ifndef __HAL_TXBF_8822B_H__ #define __HAL_TXBF_8822B_H__ #if (RTL8822B_SUPPORT == 1) #if (BEAMFORMING_SUPPORT == 1) -void -hal_txbf_8822b_enter( - void *p_dm_void, - u8 idx -); +void hal_txbf_8822b_enter( + void *dm_void, + u8 idx); +void hal_txbf_8822b_leave( + void *dm_void, + u8 idx); -void -hal_txbf_8822b_leave( - void *p_dm_void, - u8 idx -); +void hal_txbf_8822b_status( + void *dm_void, + u8 beamform_idx); +void hal_txbf_8822b_config_gtab( + void *dm_void); -void -hal_txbf_8822b_status( - void *p_dm_void, - u8 beamform_idx -); - -void -hal_txbf_8822b_config_gtab( - void *p_dm_void -); - -void -hal_txbf_8822b_fw_txbf( - void *p_dm_void, - u8 idx -); +void hal_txbf_8822b_fw_txbf( + void *dm_void, + u8 idx); #else -#define hal_txbf_8822b_enter(p_dm_void, idx) -#define hal_txbf_8822b_leave(p_dm_void, idx) -#define hal_txbf_8822b_status(p_dm_void, idx) -#define hal_txbf_8822b_fw_txbf(p_dm_void, idx) -#define hal_txbf_8822b_config_gtab(p_dm_void) +#define hal_txbf_8822b_enter(dm_void, idx) +#define hal_txbf_8822b_leave(dm_void, idx) +#define hal_txbf_8822b_status(dm_void, idx) +#define hal_txbf_8822b_fw_txbf(dm_void, idx) +#define hal_txbf_8822b_config_gtab(dm_void) #endif #if (defined(CONFIG_BB_TXBF_API)) -void -phydm_8822btxbf_rfmode( - void *p_dm_void, - u8 su_bfee_cnt, - u8 mu_bfee_cnt -); +void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt); -void -phydm_8822b_sutxbfer_workaroud( - void *p_dm_void, - boolean enable_su_bfer, - u8 nc, - u8 nr, - u8 ng, - u8 CB, - u8 BW, - boolean is_vht -); +void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer, + u8 nc, u8 nr, u8 ng, u8 CB, u8 BW, + boolean is_vht); #else -#define phydm_8822btxbf_rfmode(p_dm_void, su_bfee_cnt, mu_bfee_cnt) -#define phydm_8822b_sutxbfer_workaroud(p_dm_void, enable_su_bfer, nc, nr, ng, CB, BW, is_vht) +#define phydm_8822btxbf_rfmode(dm_void, su_bfee_cnt, mu_bfee_cnt) +#define phydm_8822b_sutxbfer_workaroud(dm_void, enable_su_bfer, nc, nr, ng, CB, BW, is_vht) #endif #else -#define hal_txbf_8822b_enter(p_dm_void, idx) -#define hal_txbf_8822b_leave(p_dm_void, idx) -#define hal_txbf_8822b_status(p_dm_void, idx) -#define hal_txbf_8822b_fw_txbf(p_dm_void, idx) -#define hal_txbf_8822b_config_gtab(p_dm_void) +#define hal_txbf_8822b_enter(dm_void, idx) +#define hal_txbf_8822b_leave(dm_void, idx) +#define hal_txbf_8822b_status(dm_void, idx) +#define hal_txbf_8822b_fw_txbf(dm_void, idx) +#define hal_txbf_8822b_config_gtab(dm_void) #endif #endif diff --git a/hal/phydm/txbf/haltxbfinterface.c b/hal/phydm/txbf/haltxbfinterface.c index cce430e..5861e0a 100644 --- a/hal/phydm/txbf/haltxbfinterface.c +++ b/hal/phydm/txbf/haltxbfinterface.c @@ -1,146 +1,160 @@ -/* ************************************************************ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/************************************************************* * Description: * * This file is for TXBF interface mechanism * - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -void -beamforming_gid_paid( - struct _ADAPTER *adapter, - PRT_TCB p_tcb -) +void beamforming_gid_paid( + void *adapter, + PRT_TCB tcb) { - u8 idx = 0; - u8 RA[6] = {0}; - u8 *p_header = GET_FRAME_OF_FIRST_FRAG(adapter, p_tcb); - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - - if (adapter->HardwareType < HARDWARE_TYPE_RTL8192EE) + u8 RA[6] = {0}; + u8 *p_header = GET_FRAME_OF_FIRST_FRAG(adapter, tcb); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + + if (((PADAPTER)adapter)->HardwareType < HARDWARE_TYPE_RTL8192EE) return; - else if (IS_WIRELESS_MODE_N(adapter) == false) + else if (IS_WIRELESS_MODE_N((PADAPTER)adapter) == false) return; #if (SUPPORT_MU_BF == 1) - if (p_tcb->tx_bf_pkt_type == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* MU NDPA */ + if (tcb->tx_bf_pkt_type == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* @MU NDPA */ #else if (0) { #endif - /* Fill G_ID and P_AID */ - p_tcb->G_ID = 63; - if (p_beam_info->first_mu_bfee_index < BEAMFORMEE_ENTRY_NUM) { - p_tcb->P_AID = p_beam_info->beamformee_entry[p_beam_info->first_mu_bfee_index].p_aid; - RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, p_tcb->G_ID, p_tcb->P_AID)); + /* @Fill G_ID and P_AID */ + tcb->G_ID = 63; + if (beam_info->first_mu_bfee_index < BEAMFORMEE_ENTRY_NUM) { + tcb->P_AID = beam_info->beamformee_entry[beam_info->first_mu_bfee_index].p_aid; + RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID)); } } else { GET_80211_HDR_ADDRESS1(p_header, &RA); /* VHT SU PPDU carrying one or more group addressed MPDUs or */ /* Transmitting a VHT NDP intended for multiple recipients */ - if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || p_tcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) { - p_tcb->G_ID = 63; - p_tcb->P_AID = 0; + if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || tcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) { + tcb->G_ID = 63; + tcb->P_AID = 0; } else if (ACTING_AS_AP(adapter)) { - u16 AID = (u16)(MacIdGetOwnerAssociatedClientAID(adapter, p_tcb->macId) & 0x1ff); /*AID[0:8]*/ + u16 AID = (u16)(MacIdGetOwnerAssociatedClientAID(adapter, tcb->macId) & 0x1ff); /*@AID[0:8]*/ - /*RT_DISP(FBEAM, FBEAM_FUN, ("@%s p_tcb->mac_id=0x%X, AID=0x%X\n", __func__, p_tcb->mac_id, AID));*/ - p_tcb->G_ID = 63; + /*RT_DISP(FBEAM, FBEAM_FUN, ("@%s tcb->mac_id=0x%X, AID=0x%X\n", __func__, tcb->mac_id, AID));*/ + tcb->G_ID = 63; - if (AID == 0) /*A PPDU sent by an AP to a non associated STA*/ - p_tcb->P_AID = 0; - else { /*Sent by an AP and addressed to a STA associated with that AP*/ - u16 BSSID = 0; + if (AID == 0) /*@A PPDU sent by an AP to a non associated STA*/ + tcb->P_AID = 0; + else { /*Sent by an AP and addressed to a STA associated with that AP*/ + u16 BSSID = 0; GET_80211_HDR_ADDRESS2(p_header, &RA); - BSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*BSSID[44:47] xor BSSID[40:43]*/ - p_tcb->P_AID = (AID + BSSID * 32) & 0x1ff; /*(dec(A) + dec(B)*32) mod 512*/ + BSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*@BSSID[44:47] xor BSSID[40:43]*/ + tcb->P_AID = (AID + BSSID * 32) & 0x1ff; /*@(dec(A) + dec(B)*32) mod 512*/ } - } else if (ACTING_AS_IBSS(adapter)) { - p_tcb->G_ID = 63; + } else if (ACTING_AS_IBSS(((PADAPTER)adapter))) { + tcb->G_ID = 63; /*P_AID for infrasturcture mode; MACID for ad-hoc mode. */ - p_tcb->P_AID = p_tcb->macId; - } else if (MgntLinkStatusQuery(adapter)) { /*Addressed to AP*/ - p_tcb->G_ID = 0; + tcb->P_AID = tcb->macId; + } else if (MgntLinkStatusQuery(adapter)) { /*@Addressed to AP*/ + tcb->G_ID = 0; GET_80211_HDR_ADDRESS1(p_header, &RA); - p_tcb->P_AID = RA[5]; /*RA[39:47]*/ - p_tcb->P_AID = (p_tcb->P_AID << 1) | (RA[4] >> 7); + tcb->P_AID = RA[5]; /*RA[39:47]*/ + tcb->P_AID = (tcb->P_AID << 1) | (RA[4] >> 7); } else { - p_tcb->G_ID = 63; - p_tcb->P_AID = 0; + tcb->G_ID = 63; + tcb->P_AID = 0; } - /*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, p_tcb->G_ID, p_tcb->P_AID));*/ + /*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID));*/ } } - enum rt_status beamforming_get_report_frame( - struct _ADAPTER *adapter, - PRT_RFD p_rfd, - POCTET_STRING p_pdu_os -) + void *adapter, + PRT_RFD rfd, + POCTET_STRING p_pdu_os) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; - u8 *p_mimo_ctrl_field, p_csi_report, p_csi_matrix; - u8 idx, nc, nr, CH_W; - u16 csi_matrix_len = 0; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + u8 *p_mimo_ctrl_field, p_csi_matrix; + u8 idx, nc, nr, CH_W; + u16 csi_matrix_len = 0; - ACT_PKT_TYPE pkt_type = ACT_PKT_TYPE_UNKNOWN; + ACT_PKT_TYPE pkt_type = ACT_PKT_TYPE_UNKNOWN; - /* Memory comparison to see if CSI report is the same with previous one */ - p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, Frame_Addr2(*p_pdu_os), &idx); + /* @Memory comparison to see if CSI report is the same with previous one */ + beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, Frame_Addr2(*p_pdu_os), &idx); - if (p_beamform_entry == NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("beamforming_get_report_frame: Cannot find entry by addr\n")); + if (beamform_entry == NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s: Cannot find entry by addr\n", + __func__); return RT_STATUS_FAILURE; } pkt_type = PacketGetActionFrameType(p_pdu_os); - /* -@ Modified by David */ + /* @-@ Modified by David */ if (pkt_type == ACT_PKT_VHT_COMPRESSED_BEAMFORMING) { p_mimo_ctrl_field = p_pdu_os->Octet + 26; nc = ((*p_mimo_ctrl_field) & 0x7) + 1; nr = (((*p_mimo_ctrl_field) & 0x38) >> 3) + 1; CH_W = (((*p_mimo_ctrl_field) & 0xC0) >> 6); /*p_csi_matrix = p_mimo_ctrl_field + 3 + nc;*/ /* 24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */ - csi_matrix_len = p_pdu_os->Length - 26 - 3 - nc; + csi_matrix_len = p_pdu_os->Length - 26 - 3 - nc; } else if (pkt_type == ACT_PKT_HT_COMPRESSED_BEAMFORMING) { p_mimo_ctrl_field = p_pdu_os->Octet + 26; nc = ((*p_mimo_ctrl_field) & 0x3) + 1; nr = (((*p_mimo_ctrl_field) & 0xC) >> 2) + 1; CH_W = (((*p_mimo_ctrl_field) & 0x10) >> 4); - /*p_csi_matrix = p_mimo_ctrl_field + 6 + nr;*/ /* 24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */ - csi_matrix_len = p_pdu_os->Length - 26 - 6 - nr; + /*p_csi_matrix = p_mimo_ctrl_field + 6 + nr;*/ /* 24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */ + csi_matrix_len = p_pdu_os->Length - 26 - 6 - nr; } else return RT_STATUS_SUCCESS; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d, pkt type=%d, nc=%d, nr=%d, CH_W=%d\n", __func__, idx, pkt_type, nc, nr, CH_W)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] idx=%d, pkt type=%d, nc=%d, nr=%d, CH_W=%d\n", __func__, + idx, pkt_type, nc, nr, CH_W); return RT_STATUS_SUCCESS; } - -void -construct_ht_ndpa_packet( - struct _ADAPTER *adapter, - u8 *RA, - u8 *buffer, - u32 *p_length, - CHANNEL_WIDTH BW -) +void construct_ht_ndpa_packet( + // 2017/11 MH PHYDM compile. But why need to use windows maco? + // For all linux code, it should be useless? + //void *adapter = dm->adapter; + ADAPTER * adapter, + //void *adapter, + u8 *RA, + u8 *buffer, + u32 *p_length, + enum channel_width BW) { - u16 duration = 0; - PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo); - OCTET_STRING p_ndpa_frame, action_content; - u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u16 duration = 0; + PMGNT_INFO mgnt_info = &(((PADAPTER)adapter)->MgntInfo); + //PMGNT_INFO mgnt_info = &((MGNT_INFO)(((PADAPTER)adapter)->MgntInfo)); + OCTET_STRING p_ndpa_frame, action_content; + u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; PlatformZeroMemory(buffer, 32); @@ -150,8 +164,8 @@ construct_ht_ndpa_packet( SET_80211_HDR_TYPE_AND_SUBTYPE(buffer, Type_Action_No_Ack); SET_80211_HDR_ADDRESS1(buffer, RA); - SET_80211_HDR_ADDRESS2(buffer, adapter->CurrentAddress); - SET_80211_HDR_ADDRESS3(buffer, p_mgnt_info->Bssid); + SET_80211_HDR_ADDRESS2(buffer, ((PADAPTER)adapter)->CurrentAddress); + SET_80211_HDR_ADDRESS3(buffer, ((PMGNT_INFO)mgnt_info)->Bssid); duration = 2 * a_SifsTime + 40; @@ -162,7 +176,7 @@ construct_ht_ndpa_packet( SET_80211_HDR_DURATION(buffer, duration); - /* HT control field */ + /* @HT control field */ SET_HT_CTRL_CSI_STEERING(buffer + sMacHdrLng, 3); SET_HT_CTRL_NDP_ANNOUNCEMENT(buffer + sMacHdrLng, 1); @@ -174,41 +188,37 @@ construct_ht_ndpa_packet( *p_length = 32; } - - - boolean send_fw_ht_ndpa_packet( - void *p_dm_void, - u8 *RA, - CHANNEL_WIDTH BW -) + void *dm_void, + u8 *RA, + enum channel_width BW) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - PRT_TCB p_tcb; - PRT_TX_LOCAL_BUFFER p_buf; - boolean ret = true; - u32 buf_len; - u8 *buf_addr; - u8 desc_len = 0, idx = 0, ndp_tx_rate; - struct _ADAPTER *p_def_adapter = GetDefaultAdapter(adapter); - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (p_beamform_entry == NULL) + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u32 buf_len; + u8 *buf_addr; + u8 desc_len = 0, idx = 0, ndp_tx_rate; + void *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter)); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (beamform_entry == NULL) return false; - ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetFWBuffer(p_def_adapter, &p_tcb, &p_buf)) { + if (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) { #if (DEV_BUS_TYPE != RT_PCI_INTERFACE) - desc_len = adapter->HWDescHeadLength - p_hal_data->USBALLDummyLength; + desc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength; #endif buf_addr = p_buf->Buffer.VirtualAddress + desc_len; @@ -217,108 +227,105 @@ send_fw_ht_ndpa_packet( RA, buf_addr, &buf_len, - BW - ); + BW); - p_tcb->PacketLength = buf_len + desc_len; + tcb->PacketLength = buf_len + desc_len; - p_tcb->bTxEnableSwCalcDur = true; + tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; + tcb->BWOfPacket = BW; - if (ACTING_AS_IBSS(adapter) || ACTING_AS_AP(adapter)) - p_tcb->G_ID = 63; + if (ACTING_AS_IBSS(((PADAPTER)adapter)) || ACTING_AS_AP(((PADAPTER)adapter))) + tcb->G_ID = 63; - p_tcb->P_AID = p_beamform_entry->p_aid; - p_tcb->DataRate = ndp_tx_rate; /*rate of NDP decide by nr*/ + tcb->P_AID = beamform_entry->p_aid; + tcb->DataRate = ndp_tx_rate; /*rate of NDP decide by nr*/ - adapter->HalFunc.CmdSendPacketHandler(adapter, p_tcb, p_buf, p_tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); + ((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(((PADAPTER)adapter), tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } - boolean send_sw_ht_ndpa_packet( - void *p_dm_void, - u8 *RA, - CHANNEL_WIDTH BW -) + void *dm_void, + u8 *RA, + enum channel_width BW) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - PRT_TCB p_tcb; - PRT_TX_LOCAL_BUFFER p_buf; - boolean ret = true; - u8 idx = 0, ndp_tx_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 idx = 0, ndp_tx_rate = 0; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { construct_ht_ndpa_packet( adapter, RA, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength, - BW - ); + &tcb->PacketLength, + BW); - p_tcb->bTxEnableSwCalcDur = true; + tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; + tcb->BWOfPacket = BW; - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } - - -void -construct_vht_ndpa_packet( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *RA, - u16 AID, - u8 *buffer, - u32 *p_length, - CHANNEL_WIDTH BW -) +void construct_vht_ndpa_packet( + struct dm_struct *dm, + u8 *RA, + u16 AID, + u8 *buffer, + u32 *p_length, + enum channel_width BW) { - u16 duration = 0; - u8 sequence = 0; - u8 *p_ndpa_frame = buffer; - struct _RT_NDPA_STA_INFO sta_info; - struct _ADAPTER *adapter = p_dm_odm->adapter; - u8 idx = 0; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); - /* Frame control. */ + u16 duration = 0; + u8 sequence = 0; + u8 *p_ndpa_frame = buffer; + struct _RT_NDPA_STA_INFO sta_info; + // 2017/11 MH PHYDM compile. But why need to use windows maco? + // For all linux code, it should be useless? + //void *adapter = dm->adapter; + ADAPTER * adapter = (PADAPTER)(dm->adapter); + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + /* @Frame control. */ SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0); SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); SET_80211_HDR_ADDRESS1(p_ndpa_frame, RA); - SET_80211_HDR_ADDRESS2(p_ndpa_frame, p_beamform_entry->my_mac_addr); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, beamform_entry->my_mac_addr); + // 2017/11 MH PHYDM compile. But why need to use windows maco? + // For all linux code, it should be useless? duration = 2 * a_SifsTime + 44; if (BW == CHANNEL_WIDTH_80) @@ -330,180 +337,174 @@ construct_vht_ndpa_packet( SET_80211_HDR_DURATION(p_ndpa_frame, duration); - sequence = *(p_dm_odm->p_sounding_seq) << 2; - odm_move_memory(p_dm_odm, p_ndpa_frame + 16, &sequence, 1); + sequence = *(dm->sounding_seq) << 2; + odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1); - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss) || phydm_acting_determine(p_dm_odm, phydm_acting_as_ap) == false) + if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap) == false) AID = 0; sta_info.aid = AID; sta_info.feedback_type = 0; sta_info.nc_index = 0; - odm_move_memory(p_dm_odm, p_ndpa_frame + 17, (u8 *)&sta_info, 2); + odm_move_memory(dm, p_ndpa_frame + 17, (u8 *)&sta_info, 2); *p_length = 19; } - boolean send_fw_vht_ndpa_packet( - void *p_dm_void, - u8 *RA, - u16 AID, - CHANNEL_WIDTH BW -) + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - PRT_TCB p_tcb; - PRT_TX_LOCAL_BUFFER p_buf; - boolean ret = true; - u32 buf_len; - u8 *buf_addr; - u8 desc_len = 0, idx = 0, ndp_tx_rate = 0; - struct _ADAPTER *p_def_adapter = GetDefaultAdapter(adapter); - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); - - if (p_beamform_entry == NULL) + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u32 buf_len; + u8 *buf_addr; + u8 desc_len = 0, idx = 0, ndp_tx_rate = 0; + void *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter)); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (beamform_entry == NULL) return false; - ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetFWBuffer(p_def_adapter, &p_tcb, &p_buf)) { + if (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) { #if (DEV_BUS_TYPE != RT_PCI_INTERFACE) - desc_len = adapter->HWDescHeadLength - p_hal_data->USBALLDummyLength; + desc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength; #endif buf_addr = p_buf->Buffer.VirtualAddress + desc_len; construct_vht_ndpa_packet( - p_dm_odm, + dm, RA, AID, buf_addr, &buf_len, - BW - ); + BW); - p_tcb->PacketLength = buf_len + desc_len; + tcb->PacketLength = buf_len + desc_len; - p_tcb->bTxEnableSwCalcDur = true; + tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; + tcb->BWOfPacket = BW; - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss) || phydm_acting_determine(p_dm_odm, phydm_acting_as_ap)) - p_tcb->G_ID = 63; + if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap)) + tcb->G_ID = 63; - p_tcb->P_AID = p_beamform_entry->p_aid; - p_tcb->DataRate = ndp_tx_rate; /*decide by nr*/ + tcb->P_AID = beamform_entry->p_aid; + tcb->DataRate = ndp_tx_rate; /*@decide by nr*/ - adapter->HalFunc.CmdSendPacketHandler(adapter, p_tcb, p_buf, p_tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); + ((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(adapter, tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, ret=%d\n", __func__, ret)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] End, ret=%d\n", __func__, ret); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } - - boolean send_sw_vht_ndpa_packet( - void *p_dm_void, - u8 *RA, - u16 AID, - CHANNEL_WIDTH BW -) + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - PRT_TCB p_tcb; - PRT_TX_LOCAL_BUFFER p_buf; - boolean ret = true; - u8 idx = 0, ndp_tx_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); - - ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 idx = 0, ndp_tx_rate = 0; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { construct_vht_ndpa_packet( - p_dm_odm, + dm, RA, AID, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength, - BW - ); + &tcb->PacketLength, + BW); - p_tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; + tcb->bTxEnableSwCalcDur = true; + tcb->BWOfPacket = BW; /*rate of NDP decide by nr*/ - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } #ifdef SUPPORT_MU_BF #if (SUPPORT_MU_BF == 1) -/* +/*@ * Description: On VHT GID management frame by an MU beamformee. * * 2015.05.20. Created by tynli. */ enum rt_status beamforming_get_vht_gid_mgnt_frame( - struct _ADAPTER *adapter, - PRT_RFD p_rfd, - POCTET_STRING p_pdu_os -) + void *adapter, + PRT_RFD rfd, + POCTET_STRING p_pdu_os) { - HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->DM_OutSrc; - enum rt_status rt_status = RT_STATUS_SUCCESS; - u8 *p_buffer = NULL; - u8 *p_raddr = NULL; - u8 mem_status[8] = {0}, user_pos[16] = {0}; - u8 idx; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMER_ENTRY *p_beamform_entry = &p_beam_info->beamformer_entry[p_beam_info->mu_ap_index]; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] On VHT GID mgnt frame!\n", __func__)); - - /* Check length*/ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + enum rt_status rt_status = RT_STATUS_SUCCESS; + u8 *p_buffer = NULL; + u8 *p_raddr = NULL; + u8 mem_status[8] = {0}, user_pos[16] = {0}; + u8 idx; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMER_ENTRY *beamform_entry = &beam_info->beamformer_entry[beam_info->mu_ap_index]; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] On VHT GID mgnt frame!\n", __func__); + + /* @Check length*/ if (p_pdu_os->length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY + 16)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("beamforming_get_vht_gid_mgnt_frame(): Invalid length (%d)\n", p_pdu_os->length)); + PHYDM_DBG(dm, DBG_TXBF, "%s: Invalid length (%d)\n", __func__, + p_pdu_os->length); return RT_STATUS_INVALID_LENGTH; } - /* Check RA*/ + /* @Check RA*/ p_raddr = (u8 *)(p_pdu_os->Octet) + 4; if (!eq_mac_addr(p_raddr, adapter->CurrentAddress)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("beamforming_get_vht_gid_mgnt_frame(): Drop because of RA error.\n")); + PHYDM_DBG(dm, DBG_TXBF, "%s: Drop because of RA error.\n", + __func__); return RT_STATUS_PKT_DROP; } @@ -513,7 +514,7 @@ beamforming_get_vht_gid_mgnt_frame( p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY; for (idx = 0; idx < 8; idx++) { mem_status[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx); - p_beamform_entry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx); + beamform_entry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx); } RT_DISP_DATA(FBEAM, FBEAM_DATA, "mem_status: ", mem_status, 8); @@ -522,37 +523,37 @@ beamforming_get_vht_gid_mgnt_frame( p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY; for (idx = 0; idx < 16; idx++) { user_pos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx); - p_beamform_entry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx); + beamform_entry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx); } RT_DISP_DATA(FBEAM, FBEAM_DATA, "user_pos: ", user_pos, 16); - /* Group ID detail printed*/ + /* @Group ID detail printed*/ { - u8 i, j; - u8 tmp_val; - u16 tmp_val2; + u8 i, j; + u8 tmp_val; + u16 tmp_val2; for (i = 0; i < 8; i++) { tmp_val = mem_status[i]; tmp_val2 = ((user_pos[i * 2 + 1] << 8) & 0xFF00) + (user_pos[i * 2] & 0xFF); for (j = 0; j < 8; j++) { if ((tmp_val >> j) & BIT(0)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Use Group ID (%d), User Position (%d)\n", - (i * 8 + j), (tmp_val2 >> 2 * j) & 0x3)); + PHYDM_DBG(dm, DBG_TXBF, "Use Group ID (%d), User Position (%d)\n", + (i * 8 + j), (tmp_val2 >> 2 * j) & 0x3); } } } } - /* Indicate GID frame to IHV service. */ + /* @Indicate GID frame to IHV service. */ { - u8 indibuffer[24] = {0}; - u8 indioffset = 0; + u8 indibuffer[24] = {0}; + u8 indioffset = 0; - PlatformMoveMemory(indibuffer + indioffset, p_beamform_entry->gid_valid, 8); + PlatformMoveMemory(indibuffer + indioffset, beamform_entry->gid_valid, 8); indioffset += 8; - PlatformMoveMemory(indibuffer + indioffset, p_beamform_entry->user_position, 16); + PlatformMoveMemory(indibuffer + indioffset, beamform_entry->user_position, 16); indioffset += 16; PlatformIndicateCustomStatus( @@ -563,30 +564,29 @@ beamforming_get_vht_gid_mgnt_frame( indioffset); } - /* Config HW GID table */ - hal_com_txbf_config_gtab(p_dm_odm); + /* @Config HW GID table */ + hal_com_txbf_config_gtab(dm); return rt_status; } -/* +/*@ * Description: Construct VHT Group ID (GID) management frame. * * 2015.05.20. Created by tynli. */ -void -construct_vht_gid_mgnt_frame( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *RA, - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry, - u8 *buffer, - u32 *p_length - -) +void construct_vht_gid_mgnt_frame( + struct dm_struct *dm, + u8 *RA, + struct _RT_BEAMFORMEE_ENTRY *beamform_entry, + u8 *buffer, + u32 *p_length + + ) { - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; - OCTET_STRING os_ftm_frame, tmp; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; + OCTET_STRING os_ftm_frame, tmp; FillOctetString(os_ftm_frame, buffer, 0); *p_length = 0; @@ -598,12 +598,12 @@ construct_vht_gid_mgnt_frame( ACT_VHT_GROUPID_MANAGEMENT, &os_ftm_frame); - /* Membership status array*/ - FillOctetString(tmp, p_beamform_entry->gid_valid, 8); + /* @Membership status array*/ + FillOctetString(tmp, beamform_entry->gid_valid, 8); PacketAppendData(&os_ftm_frame, tmp); /* User Position array*/ - FillOctetString(tmp, p_beamform_entry->user_position, 16); + FillOctetString(tmp, beamform_entry->user_position, 16); PacketAppendData(&os_ftm_frame, tmp); *p_length = os_ftm_frame.length; @@ -613,70 +613,65 @@ construct_vht_gid_mgnt_frame( boolean send_sw_vht_gid_mgnt_frame( - void *p_dm_void, - u8 *RA, - u8 idx -) + void *dm_void, + u8 *RA, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - PRT_TCB p_tcb; - PRT_TX_LOCAL_BUFFER p_buf; - boolean ret = true; - u8 data_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = &p_beam_info->beamformee_entry[idx]; - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 data_rate = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = &beam_info->beamformee_entry[idx]; + void *adapter = beam_info->source_adapter; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { construct_vht_gid_mgnt_frame( - p_dm_odm, + dm, RA, - p_beamform_entry, + beamform_entry, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength - ); + &tcb->PacketLength); - p_tcb->bw_of_packet = CHANNEL_WIDTH_20; + tcb->bw_of_packet = CHANNEL_WIDTH_20; data_rate = MGN_6M; - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, data_rate); + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } - -/* +/*@ * Description: Construct VHT beamforming report poll. * * 2015.05.20. Created by tynli. */ -void -construct_vht_bf_report_poll( - struct PHY_DM_STRUCT *p_dm_odm, - u8 *RA, - u8 *buffer, - u32 *p_length -) +void construct_vht_bf_report_poll( + struct dm_struct *dm, + u8 *RA, + u8 *buffer, + u32 *p_length) { - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; - u8 *p_bf_rpt_poll = buffer; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; + u8 *p_bf_rpt_poll = buffer; - /* Frame control*/ + /* @Frame control*/ SET_80211_HDR_FRAME_CONTROL(p_bf_rpt_poll, 0); SET_80211_HDR_TYPE_AND_SUBTYPE(p_bf_rpt_poll, Type_Beamforming_Report_Poll); - /* duration*/ + /* @duration*/ SET_80211_HDR_DURATION(p_bf_rpt_poll, 100); /* RA*/ @@ -685,111 +680,105 @@ construct_vht_bf_report_poll( /* TA*/ SET_VHT_BF_REPORT_POLL_TA(p_bf_rpt_poll, adapter->CurrentAddress); - /* Feedback Segment Retransmission Bitmap*/ + /* @Feedback Segment Retransmission Bitmap*/ SET_VHT_BF_REPORT_POLL_FEEDBACK_SEG_RETRAN_BITMAP(p_bf_rpt_poll, 0xFF); *p_length = 17; RT_DISP_DATA(FBEAM, FBEAM_DATA, "construct_vht_bf_report_poll():\n", buffer, *p_length); - } boolean send_sw_vht_bf_report_poll( - void *p_dm_void, - u8 *RA, - boolean is_final_poll -) + void *dm_void, + u8 *RA, + boolean is_final_poll) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - PRT_TCB p_tcb; - PRT_TX_LOCAL_BUFFER p_buf; - boolean ret = true; - u8 idx = 0, data_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 idx = 0, data_rate = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + void *adapter = beam_info->source_adapter; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { construct_vht_bf_report_poll( - p_dm_odm, + dm, RA, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength - ); + &tcb->PacketLength); - p_tcb->bTxEnableSwCalcDur = true; /* need?*/ - p_tcb->BWOfPacket = CHANNEL_WIDTH_20; + tcb->bTxEnableSwCalcDur = true; /* @ need?*/ + tcb->BWOfPacket = CHANNEL_WIDTH_20; if (is_final_poll) - p_tcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL; + tcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL; else - p_tcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL; + tcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL; - data_rate = MGN_6M; /* Legacy OFDM rate*/ - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, data_rate); + data_rate = MGN_6M; /* @Legacy OFDM rate*/ + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "send_sw_vht_bf_report_poll():\n", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "send_sw_vht_bf_report_poll:\n", + p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; - } - -/* +/*@ * Description: Construct VHT MU NDPA packet. * We should combine this function with construct_vht_ndpa_packet() in the future. * * 2015.05.21. Created by tynli. */ -void -construct_vht_mu_ndpa_packet( - struct PHY_DM_STRUCT *p_dm_odm, - CHANNEL_WIDTH BW, - u8 *buffer, - u32 *p_length -) +void construct_vht_mu_ndpa_packet( + struct dm_struct *dm, + enum channel_width BW, + u8 *buffer, + u32 *p_length) { - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; - u16 duration = 0; - u8 sequence = 0; - u8 *p_ndpa_frame = buffer; - struct _RT_NDPA_STA_INFO sta_info; - u8 idx; - u8 dest_addr[6] = {0}; - struct _RT_BEAMFORMEE_ENTRY *p_entry = NULL; - - /* Fill the first MU BFee entry (STA1) MAC addr to destination address then + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; + u16 duration = 0; + u8 sequence = 0; + u8 *p_ndpa_frame = buffer; + struct _RT_NDPA_STA_INFO sta_info; + u8 idx; + u8 dest_addr[6] = {0}; + struct _RT_BEAMFORMEE_ENTRY *entry = NULL; + + /* @Fill the first MU BFee entry (STA1) MAC addr to destination address then HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_entry = &(p_beam_info->beamformee_entry[idx]); - if (p_entry->is_mu_sta) { - cp_mac_addr(dest_addr, p_entry->mac_addr); + entry = &(beam_info->beamformee_entry[idx]); + if (entry->is_mu_sta) { + cp_mac_addr(dest_addr, entry->mac_addr); break; } } - if (p_entry == NULL) + if (entry == NULL) return; - /* Frame control.*/ + /* @Frame control.*/ SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0); SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr); - SET_80211_HDR_ADDRESS2(p_ndpa_frame, p_entry->my_mac_addr); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, entry->my_mac_addr); - /*--------------------------------------------*/ - /* Need to modify "duration" to MU consideration. */ + /*@--------------------------------------------*/ + /* @ Need to modify "duration" to MU consideration. */ duration = 2 * a_SifsTime + 44; if (BW == CHANNEL_WIDTH_80) @@ -798,122 +787,118 @@ construct_vht_mu_ndpa_packet( duration += 87; else duration += 180; - /*--------------------------------------------*/ + /*@--------------------------------------------*/ SET_80211_HDR_DURATION(p_ndpa_frame, duration); - sequence = *(p_dm_odm->p_sounding_seq) << 2; - odm_move_memory(p_dm_odm, p_ndpa_frame + 16, &sequence, 1); + sequence = *(dm->sounding_seq) << 2; + odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1); *p_length = 17; - /* Construct STA info. for multiple STAs*/ + /* @Construct STA info. for multiple STAs*/ for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_entry = &(p_beam_info->beamformee_entry[idx]); - if (p_entry->is_mu_sta) { - sta_info.aid = p_entry->AID; - sta_info.feedback_type = 1; /* 1'b1: MU*/ + entry = &(beam_info->beamformee_entry[idx]); + if (entry->is_mu_sta) { + sta_info.aid = entry->AID; + sta_info.feedback_type = 1; /* @1'b1: MU*/ sta_info.nc_index = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get beamformee_entry idx(%d), AID =%d\n", __func__, idx, p_entry->AID)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] Get beamformee_entry idx(%d), AID =%d\n", + __func__, idx, entry->AID); - odm_move_memory(p_dm_odm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); + odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); *p_length += 2; } } - } boolean send_sw_vht_mu_ndpa_packet( - void *p_dm_void, - CHANNEL_WIDTH BW -) + void *dm_void, + enum channel_width BW) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - PRT_TCB p_tcb; - PRT_TX_LOCAL_BUFFER p_buf; - boolean ret = true; - u8 ndp_tx_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 ndp_tx_rate = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; ndp_tx_rate = MGN_VHT2SS_MCS0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { construct_vht_mu_ndpa_packet( - p_dm_odm, + dm, BW, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength - ); + &tcb->PacketLength); - p_tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; - p_tcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA; + tcb->bTxEnableSwCalcDur = true; + tcb->BWOfPacket = BW; + tcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA; /*rate of NDP decide by nr*/ - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } - -void -dbg_construct_vht_mundpa_packet( - struct PHY_DM_STRUCT *p_dm_odm, - CHANNEL_WIDTH BW, - u8 *buffer, - u32 *p_length -) +void dbg_construct_vht_mundpa_packet( + struct dm_struct *dm, + enum channel_width BW, + u8 *buffer, + u32 *p_length) { - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; - u16 duration = 0; - u8 sequence = 0; - u8 *p_ndpa_frame = buffer; - struct _RT_NDPA_STA_INFO sta_info; - u8 idx; - u8 dest_addr[6] = {0}; - struct _RT_BEAMFORMEE_ENTRY *p_entry = NULL; - - boolean is_STA1 = false; - - - /* Fill the first MU BFee entry (STA1) MAC addr to destination address then + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; + u16 duration = 0; + u8 sequence = 0; + u8 *p_ndpa_frame = buffer; + struct _RT_NDPA_STA_INFO sta_info; + u8 idx; + u8 dest_addr[6] = {0}; + struct _RT_BEAMFORMEE_ENTRY *entry = NULL; + + boolean is_STA1 = false; + + /* @Fill the first MU BFee entry (STA1) MAC addr to destination address then HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - p_entry = &(p_beam_info->beamformee_entry[idx]); - if (p_entry->is_mu_sta) { + entry = &(beam_info->beamformee_entry[idx]); + if (entry->is_mu_sta) { if (is_STA1 == false) { is_STA1 = true; continue; } else { - cp_mac_addr(dest_addr, p_entry->mac_addr); + cp_mac_addr(dest_addr, entry->mac_addr); break; } } } - /* Frame control.*/ + /* @Frame control.*/ SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0); SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr); - SET_80211_HDR_ADDRESS2(p_ndpa_frame, p_dm_odm->CurrentAddress); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, dm->CurrentAddress); - /*--------------------------------------------*/ - /* Need to modify "duration" to MU consideration. */ + /*@--------------------------------------------*/ + /* @ Need to modify "duration" to MU consideration. */ duration = 2 * a_SifsTime + 44; if (BW == CHANNEL_WIDTH_80) @@ -922,136 +907,128 @@ dbg_construct_vht_mundpa_packet( duration += 87; else duration += 180; - /*--------------------------------------------*/ + /*@--------------------------------------------*/ SET_80211_HDR_DURATION(p_ndpa_frame, duration); - sequence = *(p_dm_odm->p_sounding_seq) << 2; - odm_move_memory(p_dm_odm, p_ndpa_frame + 16, &sequence, 1); + sequence = *(dm->sounding_seq) << 2; + odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1); *p_length = 17; /*STA2's STA Info*/ - sta_info.aid = p_entry->aid; - sta_info.feedback_type = 1; /* 1'b1: MU */ + sta_info.aid = entry->aid; + sta_info.feedback_type = 1; /* @1'b1: MU */ sta_info.nc_index = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get beamformee_entry idx(%d), AID =%d\n", __func__, idx, p_entry->aid)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Get beamformee_entry idx(%d), AID =%d\n", + __func__, idx, entry->aid); - odm_move_memory(p_dm_odm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); + odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); *p_length += 2; - } boolean dbg_send_sw_vht_mundpa_packet( - void *p_dm_void, - CHANNEL_WIDTH BW -) + void *dm_void, + enum channel_width BW) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - PRT_TCB p_tcb; - PRT_TX_LOCAL_BUFFER p_buf; - boolean ret = true; - u8 ndp_tx_rate = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _ADAPTER *adapter = p_beam_info->source_adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 ndp_tx_rate = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; ndp_tx_rate = MGN_VHT2SS_MCS0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); - if (MgntGetBuffer(adapter, &p_tcb, &p_buf)) { + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { dbg_construct_vht_mundpa_packet( - p_dm_odm, + dm, BW, p_buf->Buffer.VirtualAddress, - &p_tcb->PacketLength - ); + &tcb->PacketLength); - p_tcb->bTxEnableSwCalcDur = true; - p_tcb->BWOfPacket = BW; - p_tcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA; + tcb->bTxEnableSwCalcDur = true; + tcb->BWOfPacket = BW; + tcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA; /*rate of NDP decide by nr*/ - MgntSendPacket(adapter, p_tcb, p_buf, p_tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); } else ret = false; PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); if (ret) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, p_tcb->PacketLength); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); return ret; } - -#endif /*#if (SUPPORT_MU_BF == 1)*/ -#endif /*#ifdef SUPPORT_MU_BF*/ - +#endif /*@#if (SUPPORT_MU_BF == 1)*/ +#endif /*@#ifdef SUPPORT_MU_BF*/ #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -u32 -beamforming_get_report_frame( - void *p_dm_void, - union recv_frame *precv_frame -) +u32 beamforming_get_report_frame( + void *dm_void, + union recv_frame *precv_frame) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u32 ret = _SUCCESS; - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = NULL; - u8 *pframe = precv_frame->u.hdr.rx_data; - u32 frame_len = precv_frame->u.hdr.len; - u8 *TA; - u8 idx, offset; - - - /*Memory comparison to see if CSI report is the same with previous one*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 ret = _SUCCESS; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + u8 *pframe = precv_frame->u.hdr.rx_data; + u32 frame_len = precv_frame->u.hdr.len; + u8 *TA; + u8 idx, offset; + + /*@Memory comparison to see if CSI report is the same with previous one*/ TA = get_addr2_ptr(pframe); - p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, TA, &idx); - if (p_beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) - offset = 31; /*24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/ - else if (p_beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) - offset = 34; /*24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/ + beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, TA, &idx); + if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + offset = 31; /*@24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/ + else if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) + offset = 34; /*@24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/ else return ret; - return ret; } - boolean send_fw_ht_ndpa_packet( - void *p_dm_void, - u8 *RA, - CHANNEL_WIDTH BW -) + void *dm_void, + u8 *RA, + enum channel_width BW) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; - u8 *pframe; - u16 *fctrl; - u16 duration = 0; - u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", + __func__); + return false; } /* update attribute */ @@ -1059,8 +1036,9 @@ send_fw_ht_ndpa_packet( update_mgntframe_attrib(adapter, pattrib); pattrib->qsel = QSLT_BEACON; - ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); pattrib->rate = ndp_tx_rate; pattrib->bwmode = BW; pattrib->order = 1; @@ -1079,7 +1057,7 @@ send_fw_ht_ndpa_packet( set_frame_sub_type(pframe, WIFI_ACTION_NOACK); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); if (pmlmeext->cur_wireless_mode == WIRELESS_11B) @@ -1096,7 +1074,7 @@ send_fw_ht_ndpa_packet( set_duration(pframe, duration); - /* HT control field */ + /* @HT control field */ SET_HT_CTRL_CSI_STEERING(pframe + 24, 3); SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1); @@ -1108,40 +1086,39 @@ send_fw_ht_ndpa_packet( dump_mgntframe(adapter, pmgntframe); - return _TRUE; + return true; } - boolean send_sw_ht_ndpa_packet( - void *p_dm_void, - u8 *RA, - CHANNEL_WIDTH BW -) + void *dm_void, + u8 *RA, + enum channel_width BW) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; - u8 *pframe; - u16 *fctrl; - u16 duration = 0; - u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); - - ndp_tx_rate = beamforming_get_htndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", + __func__); + return false; } /*update attribute*/ @@ -1166,7 +1143,7 @@ send_sw_ht_ndpa_packet( set_frame_sub_type(pframe, WIFI_ACTION_NOACK); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); if (pmlmeext->cur_wireless_mode == WIRELESS_11B) @@ -1183,7 +1160,7 @@ send_sw_ht_ndpa_packet( set_duration(pframe, duration); - /*HT control field*/ + /*@HT control field*/ SET_HT_CTRL_CSI_STEERING(pframe + 24, 3); SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1); @@ -1195,40 +1172,39 @@ send_sw_ht_ndpa_packet( dump_mgntframe(adapter, pmgntframe); - return _TRUE; + return true; } - boolean send_fw_vht_ndpa_packet( - void *p_dm_void, - u8 *RA, - u16 AID, - CHANNEL_WIDTH BW -) + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - u8 *pframe; - u16 *fctrl; - u16 duration = 0; - u8 sequence = 0, a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); - struct _RT_NDPA_STA_INFO sta_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 sequence = 0, a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + struct _RT_NDPA_STA_INFO sta_info; pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", + __func__); + return false; } /* update attribute */ @@ -1237,8 +1213,9 @@ send_fw_vht_ndpa_packet( update_mgntframe_attrib(adapter, pattrib); pattrib->qsel = QSLT_BEACON; - ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); pattrib->rate = ndp_tx_rate; pattrib->bwmode = BW; pattrib->subtype = WIFI_NDPA; @@ -1255,7 +1232,7 @@ send_fw_vht_ndpa_packet( set_frame_sub_type(pframe, WIFI_NDPA); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) a_sifs_time = 16; @@ -1273,11 +1250,11 @@ send_fw_vht_ndpa_packet( set_duration(pframe, duration); - sequence = p_beam_info->sounding_sequence << 2; - if (p_beam_info->sounding_sequence >= 0x3f) - p_beam_info->sounding_sequence = 0; + sequence = beam_info->sounding_sequence << 2; + if (beam_info->sounding_sequence >= 0x3f) + beam_info->sounding_sequence = 0; else - p_beam_info->sounding_sequence++; + beam_info->sounding_sequence++; _rtw_memcpy(pframe + 16, &sequence, 1); @@ -1296,44 +1273,43 @@ send_fw_vht_ndpa_packet( dump_mgntframe(adapter, pmgntframe); - return _TRUE; + return true; } - - boolean send_sw_vht_ndpa_packet( - void *p_dm_void, - u8 *RA, - u16 AID, - CHANNEL_WIDTH BW -) + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - struct rtw_ieee80211_hdr *pwlanhdr; - struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); - struct _RT_NDPA_STA_INFO ndpa_sta_info; - u8 ndp_tx_rate = 0, sequence = 0, a_sifs_time = 0, idx = 0; - u8 *pframe; - u16 *fctrl; - u16 duration = 0; - struct _RT_BEAMFORMING_INFO *p_beam_info = &(p_dm_odm->beamforming_info); - struct _RT_BEAMFORMEE_ENTRY *p_beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(p_dm_odm, RA, &idx); - - ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(p_dm_odm, p_beamform_entry->comp_steering_num_of_bfer); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] ndp_tx_rate =%d\n", __func__, ndp_tx_rate)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct _RT_NDPA_STA_INFO ndpa_sta_info; + u8 ndp_tx_rate = 0, sequence = 0, a_sifs_time = 0, idx = 0; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); pmgntframe = alloc_mgtxmitframe(pxmitpriv); if (pmgntframe == NULL) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, alloc mgnt frame fail\n", __func__)); - return _FALSE; + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", + __func__); + return false; } /*update attribute*/ @@ -1357,7 +1333,7 @@ send_sw_vht_ndpa_packet( set_frame_sub_type(pframe, WIFI_NDPA); _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, p_beamform_entry->my_mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) a_sifs_time = 16; @@ -1375,11 +1351,11 @@ send_sw_vht_ndpa_packet( set_duration(pframe, duration); - sequence = p_beam_info->sounding_sequence << 2; - if (p_beam_info->sounding_sequence >= 0x3f) - p_beam_info->sounding_sequence = 0; + sequence = beam_info->sounding_sequence << 2; + if (beam_info->sounding_sequence >= 0x3f) + beam_info->sounding_sequence = 0; else - p_beam_info->sounding_sequence++; + beam_info->sounding_sequence++; _rtw_memcpy(pframe + 16, &sequence, 1); if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) @@ -1396,46 +1372,43 @@ send_sw_vht_ndpa_packet( pattrib->last_txcmdsz = pattrib->pktlen; dump_mgntframe(adapter, pmgntframe); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] [%d]\n", __func__, __LINE__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] [%d]\n", __func__, __LINE__); - return _TRUE; + return true; } - #endif - -void -beamforming_get_ndpa_frame( - void *p_dm_void, +void beamforming_get_ndpa_frame( + void *dm_void, #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - OCTET_STRING pdu_os + OCTET_STRING pdu_os #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) union recv_frame *precv_frame #endif -) + ) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _ADAPTER *adapter = p_dm_odm->adapter; - u8 *TA ; - u8 idx, sequence; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 *TA; + u8 idx, sequence; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - u8 *p_ndpa_frame = pdu_os.Octet; + u8 *p_ndpa_frame = pdu_os.Octet; #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) - u8 *p_ndpa_frame = precv_frame->u.hdr.rx_data; + u8 *p_ndpa_frame = precv_frame->u.hdr.rx_data; #endif - struct _RT_BEAMFORMER_ENTRY *p_beamformer_entry = NULL; /*Modified By Jeffery @2014-10-29*/ - + struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; /*@Modified By Jeffery @2014-10-29*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_DISP_DATA(FBEAM, FBEAM_DATA, "beamforming_get_ndpa_frame\n", pdu_os.Octet, pdu_os.Length); + RT_DISP_DATA(FBEAM, FBEAM_DATA, "beamforming_get_ndpa_frame\n", + pdu_os.Octet, pdu_os.Length); if (IsCtrlNDPA(p_ndpa_frame) == false) #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) if (get_frame_sub_type(p_ndpa_frame) != WIFI_NDPA) #endif return; - else if (!(p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] not 8812 or 8821A, return\n", __func__)); + else if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] not 8812 or 8821A, return\n", + __func__); return; } #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) @@ -1446,57 +1419,66 @@ beamforming_get_ndpa_frame( /*Remove signaling TA. */ TA[0] = TA[0] & 0xFE; - p_beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(p_dm_odm, TA, &idx); /* Modified By Jeffery @2014-10-29 */ + beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, TA, &idx); /* @Modified By Jeffery @2014-10-29 */ - /*Break options for Clock Reset*/ - if (p_beamformer_entry == NULL) + /*@Break options for Clock Reset*/ + if (beamformer_entry == NULL) return; - else if (!(p_beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)) + else if (!(beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)) return; - /*log_success: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/ - /*clock_reset_times: While BFer entry always doesn't receive our CSI, clock will reset again and again.So clock_reset_times is limited to 5 times.2015-04-13, Jeffery*/ - else if ((p_beamformer_entry->log_success == 1) || (p_beamformer_entry->clock_reset_times == 5)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, log_success=%d, clock_reset_times=%d, clock reset is no longer needed.\n", - __func__, p_beamformer_entry->log_seq, p_beamformer_entry->pre_log_seq, p_beamformer_entry->log_retry_cnt, p_beamformer_entry->log_success, p_beamformer_entry->clock_reset_times)); + /*@log_success: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/ + /*@clock_reset_times: While BFer entry always doesn't receive our CSI, clock will reset again and again.So clock_reset_times is limited to 5 times.2015-04-13, Jeffery*/ + else if ((beamformer_entry->log_success == 1) || (beamformer_entry->clock_reset_times == 5)) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s] log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, log_success=%d, clock_reset_times=%d, clock reset is no longer needed.\n", + __func__, beamformer_entry->log_seq, + beamformer_entry->pre_log_seq, + beamformer_entry->log_retry_cnt, + beamformer_entry->log_success, + beamformer_entry->clock_reset_times); return; } sequence = (p_ndpa_frame[16]) >> 2; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start, sequence=%d, log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, clock_reset_times=%d, log_success=%d\n", - __func__, sequence, p_beamformer_entry->log_seq, p_beamformer_entry->pre_log_seq, p_beamformer_entry->log_retry_cnt, p_beamformer_entry->clock_reset_times, p_beamformer_entry->log_success)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] Start, sequence=%d, log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, clock_reset_times=%d, log_success=%d\n", + __func__, sequence, beamformer_entry->log_seq, + beamformer_entry->pre_log_seq, + beamformer_entry->log_retry_cnt, + beamformer_entry->clock_reset_times, + beamformer_entry->log_success); - if ((p_beamformer_entry->log_seq != 0) && (p_beamformer_entry->pre_log_seq != 0)) { + if (beamformer_entry->log_seq != 0 && beamformer_entry->pre_log_seq != 0) { /*Success condition*/ - if ((p_beamformer_entry->log_seq != sequence) && (p_beamformer_entry->pre_log_seq != p_beamformer_entry->log_seq)) { - /* break option for clcok reset, 2015-03-30, Jeffery */ - p_beamformer_entry->log_retry_cnt = 0; - /*As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/ + if (beamformer_entry->log_seq != sequence && beamformer_entry->pre_log_seq != beamformer_entry->log_seq) { + /* @break option for clcok reset, 2015-03-30, Jeffery */ + beamformer_entry->log_retry_cnt = 0; + /*@As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/ /*That is, log_success is NOT needed to be reset to zero, 2015-04-13, Jeffery*/ - p_beamformer_entry->log_success = 1; + beamformer_entry->log_success = 1; - } else {/*Fail condition*/ + } else { /*@Fail condition*/ - if (p_beamformer_entry->log_retry_cnt == 5) { - p_beamformer_entry->clock_reset_times++; - p_beamformer_entry->log_retry_cnt = 0; + if (beamformer_entry->log_retry_cnt == 5) { + beamformer_entry->clock_reset_times++; + beamformer_entry->log_retry_cnt = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Clock Reset!!! clock_reset_times=%d\n", - __func__, p_beamformer_entry->clock_reset_times)); - hal_com_txbf_set(p_dm_odm, TXBF_SET_SOUNDING_CLK, NULL); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] Clock Reset!!! clock_reset_times=%d\n", + __func__, + beamformer_entry->clock_reset_times); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_CLK, NULL); } else - p_beamformer_entry->log_retry_cnt++; + beamformer_entry->log_retry_cnt++; } } /*Update log_seq & pre_log_seq*/ - p_beamformer_entry->pre_log_seq = p_beamformer_entry->log_seq; - p_beamformer_entry->log_seq = sequence; - + beamformer_entry->pre_log_seq = beamformer_entry->log_seq; + beamformer_entry->log_seq = sequence; } - - #endif diff --git a/hal/phydm/txbf/haltxbfinterface.h b/hal/phydm/txbf/haltxbfinterface.h index e888724..3905973 100644 --- a/hal/phydm/txbf/haltxbfinterface.h +++ b/hal/phydm/txbf/haltxbfinterface.h @@ -1,165 +1,167 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ #ifndef __HAL_TXBF_INTERFACE_H__ #define __HAL_TXBF_INTERFACE_H__ #if (BEAMFORMING_SUPPORT == 1) #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) -#define a_SifsTime ((IS_WIRELESS_MODE_5G(adapter)|| IS_WIRELESS_MODE_N_24G(adapter))? 16 : 10) +#define a_SifsTime ((IS_WIRELESS_MODE_5G(adapter) || IS_WIRELESS_MODE_N_24G(adapter)) ? 16 : 10) -void -beamforming_gid_paid( - struct _ADAPTER *adapter, - PRT_TCB p_tcb -); +void beamforming_gid_paid( + void *adapter, + PRT_TCB tcb); enum rt_status beamforming_get_report_frame( - struct _ADAPTER *adapter, - PRT_RFD p_rfd, - POCTET_STRING p_pdu_os -); + void *adapter, + PRT_RFD rfd, + POCTET_STRING p_pdu_os); -void -beamforming_get_ndpa_frame( - void *p_dm_void, - OCTET_STRING pdu_os -); +void beamforming_get_ndpa_frame( + void *dm_void, + OCTET_STRING pdu_os); boolean send_fw_ht_ndpa_packet( - void *p_dm_void, - u8 *RA, - CHANNEL_WIDTH BW -); + void *dm_void, + u8 *RA, + enum channel_width BW); boolean send_fw_vht_ndpa_packet( - void *p_dm_void, - u8 *RA, - u16 AID, - CHANNEL_WIDTH BW -); + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW); boolean send_sw_vht_ndpa_packet( - void *p_dm_void, - u8 *RA, - u16 AID, - CHANNEL_WIDTH BW -); + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW); boolean send_sw_ht_ndpa_packet( - void *p_dm_void, - u8 *RA, - CHANNEL_WIDTH BW -); + void *dm_void, + u8 *RA, + enum channel_width BW); #if (SUPPORT_MU_BF == 1) enum rt_status beamforming_get_vht_gid_mgnt_frame( - struct _ADAPTER *adapter, - PRT_RFD p_rfd, - POCTET_STRING p_pdu_os -); + void *adapter, + PRT_RFD rfd, + POCTET_STRING p_pdu_os); boolean send_sw_vht_gid_mgnt_frame( - void *p_dm_void, - u8 *RA, - u8 idx -); + void *dm_void, + u8 *RA, + u8 idx); boolean send_sw_vht_bf_report_poll( - void *p_dm_void, - u8 *RA, - boolean is_final_poll -); + void *dm_void, + u8 *RA, + boolean is_final_poll); boolean send_sw_vht_mu_ndpa_packet( - void *p_dm_void, - CHANNEL_WIDTH BW -); + void *dm_void, + enum channel_width BW); #else -#define beamforming_get_vht_gid_mgnt_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE -#define send_sw_vht_gid_mgnt_frame(p_dm_void, RA) -#define send_sw_vht_bf_report_poll(p_dm_void, RA, is_final_poll) -#define send_sw_vht_mu_ndpa_packet(p_dm_void, BW) +#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE +#define send_sw_vht_gid_mgnt_frame(dm_void, RA) +#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll) +#define send_sw_vht_mu_ndpa_packet(dm_void, BW) #endif - #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) -u32 -beamforming_get_report_frame( - void *p_dm_void, - union recv_frame *precv_frame -); +u32 beamforming_get_report_frame( + void *dm_void, + union recv_frame *precv_frame); boolean send_fw_ht_ndpa_packet( - void *p_dm_void, - u8 *RA, - CHANNEL_WIDTH BW -); + void *dm_void, + u8 *RA, + enum channel_width BW); boolean send_sw_ht_ndpa_packet( - void *p_dm_void, - u8 *RA, - CHANNEL_WIDTH BW -); + void *dm_void, + u8 *RA, + enum channel_width BW); boolean send_fw_vht_ndpa_packet( - void *p_dm_void, - u8 *RA, - u16 AID, - CHANNEL_WIDTH BW -); + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW); boolean send_sw_vht_ndpa_packet( - void *p_dm_void, - u8 *RA, - u16 AID, - CHANNEL_WIDTH BW -); + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW); #endif -void -beamforming_get_ndpa_frame( - void *p_dm_void, +void beamforming_get_ndpa_frame( + void *dm_void, #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - OCTET_STRING pdu_os + OCTET_STRING pdu_os #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) union recv_frame *precv_frame #endif -); + ); boolean dbg_send_sw_vht_mundpa_packet( - void *p_dm_void, - CHANNEL_WIDTH BW -); + void *dm_void, + enum channel_width BW); #else -#define beamforming_get_ndpa_frame(p_dm_odm, _pdu_os) +#define beamforming_get_ndpa_frame(dm, _pdu_os) #if (DM_ODM_SUPPORT_TYPE == ODM_CE) - #define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE +#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) - #define beamforming_get_report_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE - #define beamforming_get_vht_gid_mgnt_frame(adapter, p_rfd, p_pdu_os) RT_STATUS_FAILURE +#define beamforming_get_report_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE +#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE #endif -#define send_fw_ht_ndpa_packet(p_dm_void, RA, BW) -#define send_sw_ht_ndpa_packet(p_dm_void, RA, BW) -#define send_fw_vht_ndpa_packet(p_dm_void, RA, AID, BW) -#define send_sw_vht_ndpa_packet(p_dm_void, RA, AID, BW) -#define send_sw_vht_gid_mgnt_frame(p_dm_void, RA, idx) -#define send_sw_vht_bf_report_poll(p_dm_void, RA, is_final_poll) -#define send_sw_vht_mu_ndpa_packet(p_dm_void, BW) +#define send_fw_ht_ndpa_packet(dm_void, RA, BW) +#define send_sw_ht_ndpa_packet(dm_void, RA, BW) +#define send_fw_vht_ndpa_packet(dm_void, RA, AID, BW) +#define send_sw_vht_ndpa_packet(dm_void, RA, AID, BW) +#define send_sw_vht_gid_mgnt_frame(dm_void, RA, idx) +#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll) +#define send_sw_vht_mu_ndpa_packet(dm_void, BW) #endif #endif diff --git a/hal/phydm/txbf/haltxbfjaguar.c b/hal/phydm/txbf/haltxbfjaguar.c index 379c26e..1f53db3 100644 --- a/hal/phydm/txbf/haltxbfjaguar.c +++ b/hal/phydm/txbf/haltxbfjaguar.c @@ -1,190 +1,194 @@ -/* ************************************************************ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/************************************************************* * Description: * * This file is for 8812/8821/8811 TXBF mechanism * - * ************************************************************ */ + ************************************************************/ #include "mp_precomp.h" #include "../phydm_precomp.h" #if (BEAMFORMING_SUPPORT == 1) #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) -void -hal_txbf_8812a_set_ndpa_rate( - void *p_dm_void, - u8 BW, - u8 rate -) +void hal_txbf_8812a_set_ndpa_rate( + void *dm_void, + u8 BW, + u8 rate) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - - odm_write_1byte(p_dm_odm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW)); + struct dm_struct *dm = (struct dm_struct *)dm_void; + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW)); } -void -hal_txbf_jaguar_rf_mode( - void *p_dm_void, - struct _RT_BEAMFORMING_INFO *p_beam_info -) +void hal_txbf_jaguar_rf_mode( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; - if (p_dm_odm->rf_type == ODM_1T1R) + if (dm->rf_type == RF_1T1R) return; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] set TxIQGen\n", __func__); - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); /*RF mode table write enable*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/ - if (p_beam_info->beamformee_su_cnt > 0) { + if (beam_info->beamformee_su_cnt > 0) { /* Paath_A */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0x78000, 0x3); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/ /* Path_B */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0x78000, 0x3); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/ } else { /* Paath_A */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0x78000, 0x3); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/ /* Path_B */ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0x78000, 0x3); /*Select RX mode*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/ } - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); /*RF mode table write disable*/ - odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/ - if (p_beam_info->beamformee_su_cnt > 0) - odm_set_bb_reg(p_dm_odm, 0x80c, MASKBYTE1, 0x33); + if (beam_info->beamformee_su_cnt > 0) + odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x33); else - odm_set_bb_reg(p_dm_odm, 0x80c, MASKBYTE1, 0x11); + odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x11); } - -void -hal_txbf_jaguar_download_ndpa( - void *p_dm_void, - u8 idx -) +void hal_txbf_jaguar_download_ndpa( + void *dm_void, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 u1b_tmp = 0, tmp_reg422 = 0, head_page; - u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; - boolean is_send_beacon = false; - u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/ - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 u1b_tmp = 0, tmp_reg422 = 0, head_page; + u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; + boolean is_send_beacon = false; + u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*@default reseved 1 page for the IC type which is undefined.*/ + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + void *adapter = dm->adapter; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = true; + *dm->is_fw_dw_rsvd_page_in_progress = true; #endif - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); if (idx == 0) head_page = 0xFE; else head_page = 0xFE; - phydm_get_hal_def_var_handler_interface(p_dm_odm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); /*Set REG_CR bit 8. DMA beacon by SW.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8812A + 1); - odm_write_1byte(p_dm_odm, REG_CR_8812A + 1, (u1b_tmp | BIT(0))); - + u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1); + odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp | BIT(0))); /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ - tmp_reg422 = odm_read_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8812A + 2); - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6))); + tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6))); if (tmp_reg422 & BIT(6)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n")); + PHYDM_DBG(dm, DBG_TXBF, + "SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n"); is_send_beacon = true; } /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ - odm_write_1byte(p_dm_odm, REG_TDECTRL_8812A + 1, head_page); + odm_write_1byte(dm, REG_TDECTRL_8812A + 1, head_page); do { - /*Clear beacon valid check bit.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_TDECTRL_8812A + 2); - odm_write_1byte(p_dm_odm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0))); + /*@Clear beacon valid check bit.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2); + odm_write_1byte(dm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0))); - /*download NDPA rsvd page.*/ + /*@download NDPA rsvd page.*/ if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) - beamforming_send_vht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE); else - beamforming_send_ht_ndpa_packet(p_dm_odm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); - /*check rsvd page download OK.*/ - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_TDECTRL_8812A + 2); + /*@check rsvd page download OK.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2); count = 0; while (!(bcn_valid_reg & BIT(0)) && count < 20) { count++; ODM_delay_ms(10); - bcn_valid_reg = odm_read_1byte(p_dm_odm, REG_TDECTRL_8812A + 2); + bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2); } dl_bcn_count++; } while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5); if (!(bcn_valid_reg & BIT(0))) - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", + __func__); /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ - odm_write_1byte(p_dm_odm, REG_TDECTRL_8812A + 1, tx_page_bndy); + odm_write_1byte(dm, REG_TDECTRL_8812A + 1, tx_page_bndy); /*To make sure that if there exists an adapter which would like to send beacon.*/ - /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ /*the beacon cannot be sent by HW.*/ - /*2010.06.23. Added by tynli.*/ + /*@2010.06.23. Added by tynli.*/ if (is_send_beacon) - odm_write_1byte(p_dm_odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422); - /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ - /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ - u1b_tmp = odm_read_1byte(p_dm_odm, REG_CR_8812A + 1); - odm_write_1byte(p_dm_odm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0)))); + /*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1); + odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0)))); p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - *p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = false; + *dm->is_fw_dw_rsvd_page_in_progress = false; #endif } - -void -hal_txbf_jaguar_fw_txbf_cmd( - void *p_dm_void -) +void hal_txbf_jaguar_fw_txbf_cmd( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 idx, period0 = 0, period1 = 0; - u8 PageNum0 = 0xFF, PageNum1 = 0xFF; - u8 u1_tx_bf_parm[3] = {0}; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx, period0 = 0, period1 = 0; + u8 PageNum0 = 0xFF, PageNum1 = 0xFF; + u8 u1_tx_bf_parm[3] = {0}; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { - /*Modified by David*/ - if (p_beam_info->beamformee_entry[idx].is_used && p_beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + /*@Modified by David*/ + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { if (idx == 0) { - if (p_beam_info->beamformee_entry[idx].is_sound) + if (beam_info->beamformee_entry[idx].is_sound) PageNum0 = 0xFE; else PageNum0 = 0xFF; /*stop sounding*/ - period0 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period0 = (u8)(beam_info->beamformee_entry[idx].sound_period); } else if (idx == 1) { - if (p_beam_info->beamformee_entry[idx].is_sound) + if (beam_info->beamformee_entry[idx].is_sound) PageNum1 = 0xFE; else PageNum1 = 0xFF; /*stop sounding*/ - period1 = (u8)(p_beam_info->beamformee_entry[idx].sound_period); + period1 = (u8)(beam_info->beamformee_entry[idx].sound_period); } } } @@ -192,177 +196,167 @@ hal_txbf_jaguar_fw_txbf_cmd( u1_tx_bf_parm[0] = PageNum0; u1_tx_bf_parm[1] = PageNum1; u1_tx_bf_parm[2] = (period1 << 4) | period0; - odm_fill_h2c_cmd(p_dm_odm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); + odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, - ("[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", __func__, PageNum0, period0, PageNum1, period1)); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", + __func__, PageNum0, period0, PageNum1, period1); } - -void -hal_txbf_jaguar_enter( - void *p_dm_void, - u8 bfer_bfee_idx -) +void hal_txbf_jaguar_enter( + void *dm_void, + u8 bfer_bfee_idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 i = 0; - u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; - u8 bfee_idx = (bfer_bfee_idx & 0xF); - u32 csi_param; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY beamformee_entry; - struct _RT_BEAMFORMER_ENTRY beamformer_entry; - u16 sta_id = 0; - - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__)); - - hal_txbf_jaguar_rf_mode(p_dm_odm, p_beamforming_info); - - if (p_dm_odm->rf_type == ODM_2T2R) - odm_set_bb_reg(p_dm_odm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + u32 csi_param; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + u16 sta_id = 0; + + PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!\n", __func__); + + hal_txbf_jaguar_rf_mode(dm, beamforming_info); + + if (dm->rf_type == RF_2T2R) + odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/ else - odm_set_bb_reg(p_dm_odm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/ + odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/ - if ((p_beamforming_info->beamformer_su_cnt > 0) && (bfer_idx < BEAMFORMER_ENTRY_NUM)) { - beamformer_entry = p_beamforming_info->beamformer_entry[bfer_idx]; + if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = beamforming_info->beamformer_entry[bfer_idx]; /*Sounding protocol control*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xCB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB); - /*MAC address/Partial AID of Beamformer*/ + /*@MAC address/Partial AID of Beamformer*/ if (bfer_idx == 0) { - for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]); - /*CSI report use legacy ofdm so don't need to fill P_AID. */ + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]); + /*@CSI report use legacy ofdm so don't need to fill P_AID. */ /*platform_efio_write_2byte(adapter, REG_BFMER0_INFO_8812A+6, beamform_entry.P_AID); */ } else { - for (i = 0; i < 6 ; i++) - odm_write_1byte(p_dm_odm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]); - /*CSI report use legacy ofdm so don't need to fill P_AID.*/ + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]); + /*@CSI report use legacy ofdm so don't need to fill P_AID.*/ /*platform_efio_write_2byte(adapter, REG_BFMER1_INFO_8812A+6, beamform_entry.P_AID);*/ } - /*CSI report parameters of Beamformee*/ + /*@CSI report parameters of Beamformee*/ if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) { - if (p_dm_odm->rf_type == ODM_2T2R) + if (dm->rf_type == RF_2T2R) csi_param = 0x01090109; else csi_param = 0x01080108; } else { - if (p_dm_odm->rf_type == ODM_2T2R) + if (dm->rf_type == RF_2T2R) csi_param = 0x03090309; else csi_param = 0x03080308; } - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8812A, csi_param); - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8812A, csi_param); - odm_write_4byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8812A, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, csi_param); /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A + 3, 0x50); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A + 3, 0x50); } + if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) { + beamformee_entry = beamforming_info->beamformee_entry[bfee_idx]; - if ((p_beamforming_info->beamformee_su_cnt > 0) && (bfee_idx < BEAMFORMEE_ENTRY_NUM)) { - beamformee_entry = p_beamforming_info->beamformee_entry[bfee_idx]; - - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) sta_id = beamformee_entry.mac_id; else sta_id = beamformee_entry.p_aid; /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ if (bfee_idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A, sta_id); - odm_write_1byte(p_dm_odm, REG_TXBF_CTRL_8812A + 3, odm_read_1byte(p_dm_odm, REG_TXBF_CTRL_8812A + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_TXBF_CTRL_8812A, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8812A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8812A + 3) | BIT(4) | BIT(6) | BIT(7)); } else - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15)); + odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15)); - /*CSI report parameters of Beamformee*/ + /*@CSI report parameters of Beamformee*/ if (bfee_idx == 0) { - /*Get BIT24 & BIT25*/ - u8 tmp = odm_read_1byte(p_dm_odm, REG_BFMEE_SEL_8812A + 3) & 0x3; + /*@Get BIT24 & BIT25*/ + u8 tmp = odm_read_1byte(dm, REG_BFMEE_SEL_8812A + 3) & 0x3; - odm_write_1byte(p_dm_odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60); - odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A, sta_id | BIT(9)); + odm_write_1byte(dm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60); + odm_write_2byte(dm, REG_BFMEE_SEL_8812A, sta_id | BIT(9)); } else { /*Set BIT25*/ - odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A + 2, sta_id | 0xE200); + odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, sta_id | 0xE200); } - phydm_beamforming_notify(p_dm_odm); + phydm_beamforming_notify(dm); } } - -void -hal_txbf_jaguar_leave( - void *p_dm_void, - u8 idx -) +void hal_txbf_jaguar_leave( + void *dm_void, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beamforming_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMER_ENTRY beamformer_entry; - struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; if (idx < BEAMFORMER_ENTRY_NUM) { - beamformer_entry = p_beamforming_info->beamformer_entry[idx]; - beamformee_entry = p_beamforming_info->beamformee_entry[idx]; + beamformer_entry = beamforming_info->beamformer_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; } else return; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, idx)); + PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!, IDx = %d\n", __func__, idx); - /*Clear P_AID of Beamformee*/ - /*Clear MAC address of Beamformer*/ - /*Clear Associated Bfmee Sel*/ + /*@Clear P_AID of Beamformee*/ + /*@Clear MAC address of Beamformer*/ + /*@Clear Associated Bfmee Sel*/ if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xC8); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8); if (idx == 0) { - odm_write_4byte(p_dm_odm, REG_BFMER0_INFO_8812A, 0); - odm_write_2byte(p_dm_odm, REG_BFMER0_INFO_8812A + 4, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + odm_write_4byte(dm, REG_BFMER0_INFO_8812A, 0); + odm_write_2byte(dm, REG_BFMER0_INFO_8812A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0); } else { - odm_write_4byte(p_dm_odm, REG_BFMER1_INFO_8812A, 0); - odm_write_2byte(p_dm_odm, REG_BFMER1_INFO_8812A + 4, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); - odm_write_2byte(p_dm_odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + odm_write_4byte(dm, REG_BFMER1_INFO_8812A, 0); + odm_write_2byte(dm, REG_BFMER1_INFO_8812A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0); } } if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { - hal_txbf_jaguar_rf_mode(p_dm_odm, p_beamforming_info); + hal_txbf_jaguar_rf_mode(dm, beamforming_info); if (idx == 0) { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A, 0x0); - odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A, 0); + odm_write_2byte(dm, REG_TXBF_CTRL_8812A, 0x0); + odm_write_2byte(dm, REG_BFMEE_SEL_8812A, 0); } else { - odm_write_2byte(p_dm_odm, REG_TXBF_CTRL_8812A + 2, odm_read_2byte(p_dm_odm, REG_TXBF_CTRL_8812A + 2) & 0xF000); - odm_write_2byte(p_dm_odm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(p_dm_odm, REG_BFMEE_SEL_8812A + 2) & 0x60); + odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, odm_read_2byte(dm, REG_TXBF_CTRL_8812A + 2) & 0xF000); + odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(dm, REG_BFMEE_SEL_8812A + 2) & 0x60); } } - } - -void -hal_txbf_jaguar_status( - void *p_dm_void, - u8 idx -) +void hal_txbf_jaguar_status( + void *dm_void, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u16 beam_ctrl_val; - u32 beam_ctrl_reg; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY beamform_entry = p_beam_info->beamformee_entry[idx]; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 beam_ctrl_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx]; - if (phydm_acting_determine(p_dm_odm, phydm_acting_as_ibss)) + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) beam_ctrl_val = beamform_entry.mac_id; else beam_ctrl_val = beamform_entry.p_aid; @@ -374,7 +368,7 @@ hal_txbf_jaguar_status( beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); } - if ((beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) && (p_beam_info->apply_v_matrix == true)) { + if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) { if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) beam_ctrl_val |= BIT(9); else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) @@ -384,77 +378,69 @@ hal_txbf_jaguar_status( } else beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] beam_ctrl_val = 0x%x!\n", __func__, beam_ctrl_val)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] beam_ctrl_val = 0x%x!\n", __func__, + beam_ctrl_val); - odm_write_2byte(p_dm_odm, beam_ctrl_reg, beam_ctrl_val); + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); } - - -void -hal_txbf_jaguar_fw_txbf( - void *p_dm_void, - u8 idx -) +void hal_txbf_jaguar_fw_txbf( + void *dm_void, + u8 idx) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; - struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = p_beam_info->beamformee_entry + idx; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) - hal_txbf_jaguar_download_ndpa(p_dm_odm, idx); + hal_txbf_jaguar_download_ndpa(dm, idx); - hal_txbf_jaguar_fw_txbf_cmd(p_dm_odm); + hal_txbf_jaguar_fw_txbf_cmd(dm); } - -void -hal_txbf_jaguar_patch( - void *p_dm_void, - u8 operation -) +void hal_txbf_jaguar_patch( + void *dm_void, + u8 operation) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - struct _RT_BEAMFORMING_INFO *p_beam_info = &p_dm_odm->beamforming_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (p_beam_info->beamform_cap == BEAMFORMING_CAP_NONE) + if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE) return; #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) if (operation == SCAN_OPT_BACKUP_BAND0) - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xC8); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8); else if (operation == SCAN_OPT_RESTORE) - odm_write_1byte(p_dm_odm, REG_SND_PTCL_CTRL_8812A, 0xCB); + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB); #endif } -void -hal_txbf_jaguar_clk_8812a( - void *p_dm_void -) +void hal_txbf_jaguar_clk_8812a( + void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u16 u2btmp; - u8 count = 0, u1btmp; - struct _ADAPTER *adapter = p_dm_odm->adapter; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 u2btmp; + u8 count = 0, u1btmp; + void *adapter = dm->adapter; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); - if (*(p_dm_odm->p_is_scan_in_process)) { - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] return by Scan\n", __func__)); + if (*dm->is_scan_in_process) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] return by Scan\n", __func__); return; } #if DEV_BUS_TYPE == RT_PCI_INTERFACE /*Stop PCIe TxDMA*/ - odm_write_1byte(p_dm_odm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE); + odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE); #endif - /*Stop Usb TxDMA*/ +/*Stop Usb TxDMA*/ #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) - RT_DISABLE_FUNC(adapter, DF_TX_BIT); + RT_DISABLE_FUNC((PADAPTER)adapter, DF_TX_BIT); PlatformReturnAllPendingTxPackets(adapter); #else rtw_write_port_cancel(adapter); @@ -462,7 +448,7 @@ hal_txbf_jaguar_clk_8812a( /*Wait TXFF empty*/ for (count = 0; count < 100; count++) { - u2btmp = odm_read_2byte(p_dm_odm, REG_TXPKT_EMPTY_8812A); + u2btmp = odm_read_2byte(dm, REG_TXPKT_EMPTY_8812A); u2btmp = u2btmp & 0xfff; if (u2btmp != 0xfff) { ODM_delay_ms(10); @@ -472,55 +458,51 @@ hal_txbf_jaguar_clk_8812a( } /*TX pause*/ - odm_write_1byte(p_dm_odm, REG_TXPAUSE_8812A, 0xFF); + odm_write_1byte(dm, REG_TXPAUSE_8812A, 0xFF); /*Wait TX state Machine OK*/ for (count = 0; count < 100; count++) { - if (odm_read_4byte(p_dm_odm, REG_SCH_TXCMD_8812A) != 0) + if (odm_read_4byte(dm, REG_SCH_TXCMD_8812A) != 0) continue; else break; } - /*Stop RX DMA path*/ - u1btmp = odm_read_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A); - odm_write_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2)); + u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A); + odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2)); for (count = 0; count < 100; count++) { - u1btmp = odm_read_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A); + u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A); if (u1btmp & BIT(1)) break; else ODM_delay_ms(10); } - /*Disable clock*/ - odm_write_1byte(p_dm_odm, REG_SYS_CLKR_8812A + 1, 0xf0); - /*Disable 320M*/ - odm_write_1byte(p_dm_odm, REG_AFE_PLL_CTRL_8812A + 3, 0x8); - /*Enable 320M*/ - odm_write_1byte(p_dm_odm, REG_AFE_PLL_CTRL_8812A + 3, 0xa); - /*Enable clock*/ - odm_write_1byte(p_dm_odm, REG_SYS_CLKR_8812A + 1, 0xfc); - + /*@Disable clock*/ + odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xf0); + /*@Disable 320M*/ + odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0x8); + /*@Enable 320M*/ + odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0xa); + /*@Enable clock*/ + odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xfc); /*Release Tx pause*/ - odm_write_1byte(p_dm_odm, REG_TXPAUSE_8812A, 0); + odm_write_1byte(dm, REG_TXPAUSE_8812A, 0); - /*Enable RX DMA path*/ - u1btmp = odm_read_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A); - odm_write_1byte(p_dm_odm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2))); + /*@Enable RX DMA path*/ + u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A); + odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2))); #if DEV_BUS_TYPE == RT_PCI_INTERFACE - /*Enable PCIe TxDMA*/ - odm_write_1byte(p_dm_odm, REG_PCIE_CTRL_REG_8812A + 1, 0); + /*@Enable PCIe TxDMA*/ + odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0); #endif /*Start Usb TxDMA*/ - RT_ENABLE_FUNC(adapter, DF_TX_BIT); + RT_ENABLE_FUNC((PADAPTER)adapter, DF_TX_BIT); } #endif - - #endif diff --git a/hal/phydm/txbf/haltxbfjaguar.h b/hal/phydm/txbf/haltxbfjaguar.h index 7c7f73e..ab82fd7 100644 --- a/hal/phydm/txbf/haltxbfjaguar.h +++ b/hal/phydm/txbf/haltxbfjaguar.h @@ -1,74 +1,78 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ #ifndef __HAL_TXBF_JAGUAR_H__ #define __HAL_TXBF_JAGUAR_H__ #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) #if (BEAMFORMING_SUPPORT == 1) -void -hal_txbf_8812a_set_ndpa_rate( - void *p_dm_void, - u8 BW, - u8 rate -); +void hal_txbf_8812a_set_ndpa_rate( + void *dm_void, + u8 BW, + u8 rate); +void hal_txbf_jaguar_enter( + void *dm_void, + u8 idx); -void -hal_txbf_jaguar_enter( - void *p_dm_void, - u8 idx -); +void hal_txbf_jaguar_leave( + void *dm_void, + u8 idx); +void hal_txbf_jaguar_status( + void *dm_void, + u8 idx); -void -hal_txbf_jaguar_leave( - void *p_dm_void, - u8 idx -); +void hal_txbf_jaguar_fw_txbf( + void *dm_void, + u8 idx); +void hal_txbf_jaguar_patch( + void *dm_void, + u8 operation); -void -hal_txbf_jaguar_status( - void *p_dm_void, - u8 idx -); - - -void -hal_txbf_jaguar_fw_txbf( - void *p_dm_void, - u8 idx -); - - -void -hal_txbf_jaguar_patch( - void *p_dm_void, - u8 operation -); - - -void -hal_txbf_jaguar_clk_8812a( - void *p_dm_void -); +void hal_txbf_jaguar_clk_8812a( + void *dm_void); #else -#define hal_txbf_8812a_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_jaguar_enter(p_dm_void, idx) -#define hal_txbf_jaguar_leave(p_dm_void, idx) -#define hal_txbf_jaguar_status(p_dm_void, idx) -#define hal_txbf_jaguar_fw_txbf(p_dm_void, idx) -#define hal_txbf_jaguar_patch(p_dm_void, operation) -#define hal_txbf_jaguar_clk_8812a(p_dm_void) +#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_jaguar_enter(dm_void, idx) +#define hal_txbf_jaguar_leave(dm_void, idx) +#define hal_txbf_jaguar_status(dm_void, idx) +#define hal_txbf_jaguar_fw_txbf(dm_void, idx) +#define hal_txbf_jaguar_patch(dm_void, operation) +#define hal_txbf_jaguar_clk_8812a(dm_void) #endif #else -#define hal_txbf_8812a_set_ndpa_rate(p_dm_void, BW, rate) -#define hal_txbf_jaguar_enter(p_dm_void, idx) -#define hal_txbf_jaguar_leave(p_dm_void, idx) -#define hal_txbf_jaguar_status(p_dm_void, idx) -#define hal_txbf_jaguar_fw_txbf(p_dm_void, idx) -#define hal_txbf_jaguar_patch(p_dm_void, operation) -#define hal_txbf_jaguar_clk_8812a(p_dm_void) +#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_jaguar_enter(dm_void, idx) +#define hal_txbf_jaguar_leave(dm_void, idx) +#define hal_txbf_jaguar_status(dm_void, idx) +#define hal_txbf_jaguar_fw_txbf(dm_void, idx) +#define hal_txbf_jaguar_patch(dm_void, operation) +#define hal_txbf_jaguar_clk_8812a(dm_void) #endif -#endif /* #ifndef __HAL_TXBF_JAGUAR_H__ */ +#endif /* @#ifndef __HAL_TXBF_JAGUAR_H__ */ diff --git a/hal/phydm/txbf/phydm_hal_txbf_api.c b/hal/phydm/txbf/phydm_hal_txbf_api.c index 317204d..8cbd3e4 100644 --- a/hal/phydm/txbf/phydm_hal_txbf_api.c +++ b/hal/phydm/txbf/phydm_hal_txbf_api.c @@ -1,68 +1,83 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + #include "mp_precomp.h" #include "phydm_precomp.h" #if (defined(CONFIG_BB_TXBF_API)) -#if (RTL8822B_SUPPORT == 1) -/*Add by YuChen for 8822B MU-MIMO API*/ +#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\ + RTL8822C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1) +/*@Add by YuChen for 8822B MU-MIMO API*/ /*this function is only used for BFer*/ -u8 -phydm_get_ndpa_rate( - void *p_dm_void -) +u8 phydm_get_ndpa_rate(void *dm_void) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; - u8 ndpa_rate = ODM_RATE6M; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ndpa_rate = ODM_RATE6M; - if (p_dm_odm->rssi_min >= 30) /*link RSSI > 30%*/ + if (dm->rssi_min >= 30) /*@link RSSI > 30%*/ ndpa_rate = ODM_RATE24M; - else if (p_dm_odm->rssi_min <= 25) + else if (dm->rssi_min <= 25) ndpa_rate = ODM_RATE6M; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] ndpa_rate = 0x%x\n", __func__, ndpa_rate)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndpa_rate = 0x%x\n", __func__, ndpa_rate); return ndpa_rate; - } /*this function is only used for BFer*/ -u8 -phydm_get_beamforming_sounding_info( - void *p_dm_void, - u16 *troughput, - u8 total_bfee_num, - u8 *tx_rate -) +u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput, + u8 total_bfee_num, u8 *tx_rate) { - u8 idx = 0; - u8 soundingdecision = 0xff; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 idx = 0; + u8 snddecision = 0xff; + struct dm_struct *dm = (struct dm_struct *)dm_void; for (idx = 0; idx < total_bfee_num; idx++) { - if (((tx_rate[idx] >= ODM_RATEVHTSS3MCS7) && (tx_rate[idx] <= ODM_RATEVHTSS3MCS9))) - soundingdecision = soundingdecision & ~(1 << idx); + if (dm->support_ic_type & (ODM_RTL8814A)) { + if ((tx_rate[idx] >= ODM_RATEVHTSS3MCS7 && + tx_rate[idx] <= ODM_RATEVHTSS3MCS9)) + snddecision = snddecision & ~(1 << idx); + } else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C | + ODM_RTL8812 | ODM_RTL8192F)) { + if ((tx_rate[idx] >= ODM_RATEVHTSS2MCS7 && + tx_rate[idx] <= ODM_RATEVHTSS2MCS9)) + snddecision = snddecision & ~(1 << idx); + } else if (dm->support_ic_type & (ODM_RTL8814B)) { + if ((tx_rate[idx] >= ODM_RATEVHTSS4MCS7 && + tx_rate[idx] <= ODM_RATEVHTSS4MCS9)) + snddecision = snddecision & ~(1 << idx); + } } for (idx = 0; idx < total_bfee_num; idx++) { - if (troughput[idx] <= 10) - soundingdecision = soundingdecision & ~(1 << idx); + if (throughput[idx] <= 10) + snddecision = snddecision & ~(1 << idx); } - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] soundingdecision = 0x%x\n", __func__, soundingdecision)); - - return soundingdecision; + PHYDM_DBG(dm, DBG_TXBF, "[%s] soundingdecision = 0x%x\n", __func__, + snddecision); + return snddecision; } /*this function is only used for BFer*/ -u8 -phydm_get_mu_bfee_snding_decision( - void *p_dm_void, - u16 throughput -) +u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput) { - u8 snding_score = 0; - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 snding_score = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; /*throughput unit is Mbps*/ if (throughput >= 500) @@ -88,31 +103,26 @@ phydm_get_mu_bfee_snding_decision( else snding_score = 0; - ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("[%s] snding_score = 0x%x\n", __func__, snding_score)); + PHYDM_DBG(dm, DBG_TXBF, "[%s] snding_score = 0x%x\n", __func__, + snding_score); return snding_score; - } - #endif #if (DM_ODM_SUPPORT_TYPE != ODM_AP) -u8 -beamforming_get_htndp_tx_rate( - void *p_dm_void, - u8 comp_steering_num_of_bfer -) +u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 nr_index = 0; u8 ndp_tx_rate; - /*Find nr*/ +/*@Find nr*/ #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), comp_steering_num_of_bfer); + if (dm->support_ic_type & ODM_RTL8814A) + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num); else #endif - nr_index = tx_bf_nr(1, comp_steering_num_of_bfer); + nr_index = tx_bf_nr(1, bfer_str_num); switch (nr_index) { case 1: @@ -133,25 +143,20 @@ beamforming_get_htndp_tx_rate( } return ndp_tx_rate; - } -u8 -beamforming_get_vht_ndp_tx_rate( - void *p_dm_void, - u8 comp_steering_num_of_bfer -) +u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num) { - struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct dm_struct *dm = (struct dm_struct *)dm_void; u8 nr_index = 0; u8 ndp_tx_rate; - /*Find nr*/ +/*@Find nr*/ #if (RTL8814A_SUPPORT == 1) - if (p_dm_odm->support_ic_type & ODM_RTL8814A) - nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(p_dm_odm), comp_steering_num_of_bfer); + if (dm->support_ic_type & ODM_RTL8814A) + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num); else #endif - nr_index = tx_bf_nr(1, comp_steering_num_of_bfer); + nr_index = tx_bf_nr(1, bfer_str_num); switch (nr_index) { case 1: @@ -172,7 +177,6 @@ beamforming_get_vht_ndp_tx_rate( } return ndp_tx_rate; - } #endif diff --git a/hal/phydm/txbf/phydm_hal_txbf_api.h b/hal/phydm/txbf/phydm_hal_txbf_api.h index 93fb784..4dd82c9 100644 --- a/hal/phydm/txbf/phydm_hal_txbf_api.h +++ b/hal/phydm/txbf/phydm_hal_txbf_api.h @@ -1,67 +1,61 @@ -/********************************************************************************/ -/**/ -/*Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.*/ -/**/ -/*This program is free software; you can redistribute it and/or modify it*/ -/*under the terms of version 2 of the GNU General Public License as*/ -/*published by the Free Software Foundation.*/ -/**/ -/*This program is distributed in the hope that it will be useful, but WITHOUT*/ -/*ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or*/ -/*FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for*/ -/*more details.*/ -/*You should have received a copy of the GNU General Public License along with*/ -/*this program; if not, write to the Free Software Foundation, Inc.,*/ -/*51 Franklin Street, Fifth Floor, Boston, MA 02110, USA*/ -/**/ -/**/ -/********************************************************************************/ -#ifndef __PHYDM_HAL_TXBF_API_H__ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __PHYDM_HAL_TXBF_API_H__ #define __PHYDM_HAL_TXBF_API_H__ #if (defined(CONFIG_BB_TXBF_API)) #if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if defined(DM_ODM_CE_MAC80211) +#define tx_bf_nr(a, b) ({ \ + u8 __tx_bf_nr_a = (a); \ + u8 __tx_bf_nr_b = (b); \ + ((__tx_bf_nr_a > __tx_bf_nr_b) ? (__tx_bf_nr_b) : (__tx_bf_nr_a)); }) +#else #define tx_bf_nr(a, b) ((a > b) ? (b) : (a)) +#endif -u8 -beamforming_get_htndp_tx_rate( - void *p_dm_void, - u8 comp_steering_num_of_bfer -); +u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num); -u8 -beamforming_get_vht_ndp_tx_rate( - void *p_dm_void, - u8 comp_steering_num_of_bfer -); +u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num); #endif -#if (RTL8822B_SUPPORT == 1) -u8 -phydm_get_beamforming_sounding_info( - void *p_dm_void, - u16 *troughput, - u8 total_bfee_num, - u8 *tx_rate -); +#if (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\ + RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1) +u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput, + u8 total_bfee_num, u8 *tx_rate); -u8 -phydm_get_ndpa_rate( - void *p_dm_void -); +u8 phydm_get_ndpa_rate(void *dm_void); -u8 -phydm_get_mu_bfee_snding_decision( - void *p_dm_void, - u16 throughput -); +u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput); #else -#define phydm_get_beamforming_sounding_info(p_dm_void, troughput, total_bfee_num, tx_rate) -#define phydm_get_ndpa_rate(p_dm_void) -#define phydm_get_mu_bfee_snding_decision(p_dm_void, troughput) +#define phydm_get_beamforming_sounding_info(dm, tp, bfee_num, rate) 0 +#define phydm_get_ndpa_rate(dm) +#define phydm_get_mu_bfee_snding_decision(dm, tp) #endif diff --git a/hal/rtl8821c/hal8821c_fw.c b/hal/rtl8821c/hal8821c_fw.c index bb03336..ec54647 100644 --- a/hal/rtl8821c/hal8821c_fw.c +++ b/hal/rtl8821c/hal8821c_fw.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. +* Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,6 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* ******************************************************************************/ #ifdef CONFIG_RTL8821C @@ -27,13 +22,13 @@ #if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) u8 array_mp_8821c_fw_ap[] = { -0x21, 0x88, 0x00, 0x00, 0x09, 0x00, 0x07, 0x00, -0x42, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x03, 0x0C, 0x12, 0x03, 0xE1, 0x07, 0x00, 0x00, -0x18, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, -0x00, 0x00, 0x20, 0x80, 0x08, 0x7D, 0x00, 0x00, +0x21, 0x88, 0x00, 0x00, 0x14, 0x00, 0x01, 0x00, +0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, +0x07, 0x01, 0x0E, 0x33, 0xE2, 0x07, 0x00, 0x00, +0x18, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, +0x00, 0x00, 0x20, 0x80, 0x38, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, -0x70, 0x6C, 0x00, 0x00, 0x10, 0x72, 0x00, 0x00, +0x40, 0xC3, 0x00, 0x00, 0x50, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, @@ -84,7 +79,7 @@ u8 array_mp_8821c_fw_ap[] = { 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x01, 0x00, 0x03, 0x80, 0xA1, 0x01, 0x03, 0x80, 0xA1, 0x01, 0x03, 0x80, -0xCD, 0x2B, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, +0xF5, 0x5A, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -3880,7 +3875,7 @@ u8 array_mp_8821c_fw_ap[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x7D, 0x2B, 0x03, 0x80, 0x01, 0x00, 0x00, 0x00, +0xA5, 0x5A, 0x03, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -3888,7 +3883,8 @@ u8 array_mp_8821c_fw_ap[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x24, 0x7F, 0x20, 0x80, 0x81, 0x00, 0x88, 0x00, +0xF8, 0x81, 0x20, 0x80, 0x41, 0x4E, 0x59, 0x00, +0x61, 0x6E, 0x79, 0x00, 0x81, 0x00, 0x88, 0x00, 0x90, 0x00, 0x99, 0x00, 0xA2, 0x00, 0xAC, 0x00, 0xB6, 0x00, 0xC0, 0x00, 0xCC, 0x00, 0xD8, 0x00, 0xE5, 0x00, 0xF2, 0x00, 0x01, 0x01, 0x10, 0x01, @@ -3898,151 +3894,156 @@ u8 array_mp_8821c_fw_ap[] = { 0x3E, 0x02, 0x61, 0x02, 0x85, 0x02, 0xAB, 0x02, 0xD3, 0x02, 0xFE, 0x02, 0x2B, 0x03, 0x5C, 0x03, 0x8E, 0x03, 0xC4, 0x03, 0xFE, 0x03, 0x00, 0x00, -0x06, 0x09, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x36, -0x01, 0x02, 0x05, 0x0B, 0x00, 0x00, 0x00, 0x00, -0x01, 0x02, 0x03, 0x06, 0x05, 0x06, 0x07, 0x08, -0x09, 0x0A, 0x0B, 0x2C, 0xFF, 0x00, 0x01, 0x02, -0x02, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, -0x28, 0x28, 0x32, 0x28, 0x1E, 0x19, 0x19, 0x19, -0x18, 0x18, 0x12, 0x0F, 0x1E, 0x1E, 0x19, 0x1E, -0x18, 0x16, 0x0C, 0x0C, 0x1E, 0x1E, 0x19, 0x1E, -0x18, 0x16, 0x0C, 0x0C, 0x1E, 0x1E, 0x19, 0x1C, -0x18, 0x14, 0x0C, 0x0A, 0x1E, 0x1E, 0x19, 0x1E, -0x19, 0x18, 0x0F, 0x0E, 0x1E, 0x1E, 0x1E, 0x1E, -0x1C, 0x16, 0x14, 0x12, 0x0C, 0x0A, 0x1E, 0x1E, -0x1E, 0x1E, 0x1A, 0x16, 0x12, 0x10, 0x0C, 0x0A, -0x1E, 0x1E, 0x1E, 0x1E, 0x18, 0x16, 0x0D, 0x0E, -0x0C, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, -0x0A, 0x0A, 0x0A, 0x0A, 0x12, 0x12, 0x14, 0x12, -0x0F, 0x0F, 0x0C, 0x0C, 0x09, 0x08, 0x08, 0x07, +0x22, 0x05, 0x50, 0x05, 0x51, 0x05, 0x1A, 0x15, +0x08, 0x08, 0x0C, 0x09, 0x00, 0x0C, 0xB0, 0x0C, +0xB4, 0x0C, 0xBC, 0x0C, 0x90, 0x19, 0xA4, 0x09, +0x04, 0x0A, 0x00, 0x0B, 0xDF, 0xDE, 0x8F, 0x00, +0x01, 0x00, 0x00, 0x00, 0x06, 0x09, 0x0C, 0x12, +0x18, 0x24, 0x30, 0x36, 0x01, 0x02, 0x05, 0x0B, +0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 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0x18, 0xAC, 0xC3, 0x00, 0x18, 0xCC, 0xC3, -0x00, 0x18, 0x35, 0xC6, 0x00, 0x18, 0xE9, 0xC3, -0x00, 0x18, 0x50, 0xC6, 0x00, 0x18, 0x34, 0xC7, +0x00, 0x1C, 0x94, 0x00, 0x00, 0x18, 0x2F, 0xCB, +0x00, 0x18, 0x73, 0xC8, 0x00, 0x18, 0x96, 0xC8, +0x00, 0x18, 0x04, 0xCB, 0x00, 0x18, 0xC3, 0xC8, +0x00, 0x18, 0x20, 0xCB, 0x00, 0x18, 0x2A, 0xCC, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF7, 0x54, 0x9A, 0x30, 0xF0, 0x20, 0x68, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6C, 0x30, 0xF0, 0x21, 0x6A, 0x80, 0xF1, @@ -4072,13 +4073,13 @@ u8 array_mp_8821c_fw_ap[] = { 0x30, 0xF0, 0x20, 0x6A, 0xEE, 0xF7, 0x50, 0x9A, 0x30, 0xF0, 0x20, 0x6C, 0x6F, 0xF0, 0x08, 0x4C, 0x01, 0x6D, 0x40, 0xEA, 0x30, 0xF0, 0x21, 0x6B, -0x70, 0xF0, 0x44, 0xDB, 0x30, 0xF0, 0x20, 0x6C, +0x30, 0xF3, 0x54, 0xDB, 0x30, 0xF0, 0x20, 0x6C, 0x30, 0xF0, 0x21, 0x6A, 0x2F, 0xF0, 0x08, 0x4C, 0x15, 0xF4, 0x00, 0x4A, 0x43, 0xDC, 0xCE, 0xF7, 0x40, 0x98, 0x00, 0x6D, 0x40, 0xEA, 0x30, 0xF0, -0x21, 0x6B, 0x50, 0xF0, 0x5C, 0xDB, 0x00, 0x18, -0x0D, 0xC5, 0x10, 0xF0, 0x23, 0x6A, 0x6B, 0xF5, -0x64, 0x9A, 0xFF, 0xF7, 0x1F, 0x6C, 0x10, 0xF0, +0x21, 0x6B, 0x30, 0xF3, 0x4C, 0xDB, 0x00, 0x18, +0xDB, 0xC9, 0x10, 0xF0, 0x24, 0x6A, 0x16, 0xF4, +0x74, 0x9A, 0xFF, 0xF7, 0x1F, 0x6C, 0x10, 0xF0, 0x00, 0x6D, 0x40, 0xAB, 0xAB, 0xED, 0x8C, 0xEA, 0xAD, 0xEA, 0x8C, 0xEA, 0x40, 0xCB, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF7, 0x58, 0x9A, 0x40, 0xEA, @@ -4087,7 +4088,7 @@ u8 array_mp_8821c_fw_ap[] = { 0x2D, 0xF1, 0x40, 0x9B, 0x01, 0x4A, 0x10, 0x72, 0x2D, 0xF1, 0x40, 0xDB, 0x09, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x30, 0xF0, 0x21, 0x6B, 0xEE, 0xF7, -0x58, 0x9A, 0x70, 0xF0, 0x88, 0x9B, 0x40, 0xEA, +0x58, 0x9A, 0x30, 0xF3, 0x98, 0x9B, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0x6D, 0xB8, 0x00, 0x65, 0x00, 0xF0, 0x20, 0x6A, 0x7C, 0x4A, 0x6C, 0xEA, 0x1C, 0x22, 0x00, 0xF0, @@ -4097,7 +4098,7 @@ u8 array_mp_8821c_fw_ap[] = { 0x1A, 0x6A, 0x6A, 0xEA, 0x31, 0x60, 0x77, 0xF0, 0x24, 0x6A, 0xA0, 0xF1, 0x1C, 0x4A, 0x1D, 0xF4, 0x00, 0x6B, 0x60, 0xDA, 0x10, 0xF0, 0x23, 0x6A, -0x83, 0xF4, 0x01, 0x4A, 0x00, 0xEA, 0x00, 0xF0, +0x46, 0xF0, 0x19, 0x4A, 0x00, 0xEA, 0x00, 0xF0, 0x20, 0x6A, 0x1F, 0xF7, 0x00, 0x6A, 0x4C, 0xEB, 0x4C, 0xB8, 0x00, 0x65, 0x6C, 0xEA, 0x42, 0x32, 0x30, 0xF0, 0x20, 0x6B, 0x00, 0xF0, 0x00, 0x4B, @@ -4133,7 +4134,7 @@ u8 array_mp_8821c_fw_ap[] = { 0x6A, 0x9B, 0xCF, 0xF7, 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, -0x10, 0xF0, 0x23, 0x6C, 0x83, 0xF4, 0x01, 0x4C, +0x10, 0xF0, 0x23, 0x6C, 0x46, 0xF0, 0x19, 0x4C, 0x00, 0xEC, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6B, 0x2D, 0xF1, 0x18, 0x4B, 0x41, 0x9B, 0x40, 0xDB, 0x89, 0x9A, 0xBC, 0x65, 0x7D, 0x67, 0xDF, 0xF7, @@ -4181,7 +4182,7 @@ u8 array_mp_8821c_fw_ap[] = { 0x6A, 0x9B, 0xCF, 0xF7, 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, -0x10, 0xF0, 0x23, 0x6C, 0x83, 0xF4, 0x01, 0x4C, +0x10, 0xF0, 0x23, 0x6C, 0x46, 0xF0, 0x19, 0x4C, 0x00, 0xEC, 0x00, 0x65, 0x40, 0x9A, 0x30, 0xF0, 0x20, 0x6C, 0xAD, 0xF1, 0x08, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, 0x82, 0x67, 0x40, 0xEA, @@ -4218,737 +4219,1372 @@ u8 array_mp_8821c_fw_ap[] = { 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0xB0, 0xC1, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, -0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x44, 0xC2, +0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x58, 0xC2, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, -0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x52, 0xC2, +0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x6A, 0xC2, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x76, 0xC1, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, -0x10, 0xF0, 0x23, 0x6B, 0xAB, 0xF4, 0x64, 0x9B, +0x10, 0xF0, 0x24, 0x6B, 0x16, 0xF2, 0x70, 0x9B, 0x10, 0xF0, 0x23, 0x6A, 0xC0, 0xF5, 0x19, 0x4A, 0x40, 0xDB, 0x01, 0x4A, 0x40, 0xDB, 0x20, 0xE8, -0x10, 0xF0, 0x23, 0x6B, 0xAB, 0xF4, 0x64, 0x9B, +0x10, 0xF0, 0x24, 0x6B, 0x16, 0xF2, 0x70, 0x9B, 0x10, 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0xF0, 0x23, 0x6A, 0x03, 0xF4, +0x6F, 0xDA, 0x10, 0xF0, 0x23, 0x6A, 0xA5, 0xF7, 0x15, 0x4A, 0x00, 0xEA, 0x00, 0x65, 0x00, 0x65, 0x10, 0xF0, 0x23, 0x6A, 0x40, 0xF2, 0x0D, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x44, 0xDB, @@ -4967,11 +5603,11 @@ u8 array_mp_8821c_fw_ap[] = { 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x23, 0x6A, 0x20, 0xF5, 0x15, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x50, 0xDB, -0x10, 0xF0, 0x23, 0x6A, 0x03, 0xF4, 0x15, 0x4A, +0x10, 0xF0, 0x23, 0x6A, 0xA5, 0xF7, 0x15, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x54, 0xDB, -0x10, 0xF0, 0x23, 0x6A, 0x83, 0xF4, 0x01, 0x4A, +0x10, 0xF0, 0x23, 0x6A, 0x46, 0xF0, 0x19, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x58, 0xDB, -0x10, 0xF0, 0x23, 0x6A, 0xE3, 0xF3, 0x1D, 0x4A, +0x10, 0xF0, 0x23, 0x6A, 0x85, 0xF7, 0x1D, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0xE2, 0xF5, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xEE, 0xF6, 0x40, 0xDB, @@ -5027,7 +5663,7 @@ u8 array_mp_8821c_fw_ap[] = { 0x30, 0xF0, 0x20, 0x6B, 0x4E, 0xF7, 0x44, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0xA1, 0xF1, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0x4E, 0xF7, 0x48, 0xDB, -0x10, 0xF0, 0x23, 0x6A, 0xC3, 0xF3, 0x0D, 0x4A, +0x10, 0xF0, 0x23, 0x6A, 0x65, 0xF7, 0x0D, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0x4E, 0xF7, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0xFF, 0xF7, 0x1C, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0x4E, 0xF7, 0x50, 0xDB, @@ -5120,1786 +5756,3871 @@ u8 array_mp_8821c_fw_ap[] = { 0x20, 0xE8, 0x00, 0x65, 0xFF, 0x63, 0x01, 0xD0, 0xFF, 0x6A, 0x4C, 0xEC, 0x4C, 0xED, 0x8E, 0x37, 0x4C, 0xEF, 0x07, 0x6E, 0x01, 0x75, 0x8C, 0xEE, -0x52, 0xF4, 0x60, 0x47, 0x42, 0x61, 0x30, 0xF0, -0x20, 0x6C, 0xC0, 0xF1, 0x08, 0x4C, 0x9D, 0xE7, -0xE8, 0xF2, 0x8F, 0xA7, 0x01, 0x6D, 0xA4, 0xEE, -0xAD, 0xEC, 0xE8, 0xF2, 0x8F, 0xC7, 0x1F, 0xF7, -0x00, 0x6C, 0x6C, 0xEC, 0x02, 0xF0, 0x00, 0x74, -0x01, 0x60, 0x22, 0x2C, 0x1F, 0xF7, 0x00, 0x6A, +0x52, 0xF4, 0x60, 0x47, 0x59, 0x61, 0x30, 0xF0, +0x20, 0x6D, 0xC0, 0xF1, 0x08, 0x4D, 0xBD, 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0xB8, @@ -7097,120 +9887,125 @@ u8 array_mp_8821c_fw_ap[] = { 0x84, 0x04, 0x60, 0xB8, 0x84, 0x04, 0x64, 0xB8, 0xC8, 0x04, 0x60, 0xB8, 0xC8, 0x04, 0x64, 0xB8, 0x78, 0x04, 0x60, 0xB8, 0x78, 0x04, 0x64, 0xB8, +0xCF, 0x01, 0x64, 0xB8, 0x34, 0x01, 0x64, 0xB8, +0x64, 0x05, 0x64, 0xB8, 0x44, 0x00, 0x60, 0xB8, +0x60, 0x00, 0x60, 0xB8, 0xBE, 0x05, 0x64, 0xB8, 0x01, 0xEA, 0xEF, 0xFD, 0x02, 0xEA, 0xEF, 0xFD, 0xC8, 0x01, 0x64, 0xB8, 0xC9, 0x01, 0x64, 0xB8, -0xA0, 0x01, 0x64, 0xB8, 0x00, 0x00, 0x00, 0x05, -0x64, 0x01, 0x64, 0xB8, 0x53, 0x05, 0x64, 0xB8, -0x77, 0x05, 0x64, 0xB8, 0x94, 0x01, 0x64, 0xB8, +0xA0, 0x01, 0x64, 0xB8, 0xFF, 0xFF, 0xFF, 0x00, +0x00, 0x00, 0x00, 0x05, 0x64, 0x01, 0x64, 0xB8, +0x53, 0x05, 0x64, 0xB8, 0x77, 0x05, 0x64, 0xB8, +0x94, 0x01, 0x64, 0xB8, 0x00, 0x10, 0x66, 0xB8, 0x9A, 0x01, 0x64, 0xB8, 0x99, 0x01, 0x64, 0xB8, -0xC7, 0x01, 0x64, 0xB8, 0xC6, 0x01, 0x64, 0xB8, -0x34, 0x01, 0x64, 0xB8, 0x30, 0x01, 0x64, 0xB8, +0xC6, 0x01, 0x64, 0xB8, 0x30, 0x01, 0x64, 0xB8, 0x24, 0x01, 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array_mp_8821c_fw_ap[] = { 0x6F, 0x72, 0x74, 0x65, 0x64, 0x20, 0x70, 0x61, 0x74, 0x68, 0x20, 0x28, 0x25, 0x64, 0x29, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x5B, 0x25, 0x73, 0x5D, -0x3A, 0x20, 0x52, 0x65, 0x61, 0x64, 0x20, 0x66, -0x61, 0x69, 0x6C, 0x2C, 0x20, 0x52, 0x46, 0x20, -0x69, 0x73, 0x20, 0x64, 0x69, 0x73, 0x61, 0x62, -0x6C, 0x65, 0x64, 0x0A, 0x00, 0x00, 0x00, 0x00, -0x5B, 0x25, 0x73, 0x5D, 0x3A, 0x20, 0x52, 0x46, -0x2D, 0x25, 0x64, 0x20, 0x30, 0x78, 0x25, 0x78, -0x20, 0x3D, 0x20, 0x30, 0x78, 0x25, 0x78, 0x2C, -0x20, 0x62, 0x69, 0x74, 0x20, 0x6D, 0x61, 0x73, -0x6B, 0x20, 0x3D, 0x20, 0x30, 0x78, 0x25, 0x78, -0x0A, 0x00, 0x00, 0x00, 0x5B, 0x25, 0x73, 0x5D, -0x3A, 0x20, 0x57, 0x72, 0x69, 0x74, 0x65, 0x20, -0x66, 0x61, 0x69, 0x6C, 0x2C, 0x20, 0x52, 0x46, -0x20, 0x69, 0x73, 0x20, 0x64, 0x69, 0x73, 0x61, -0x62, 0x6C, 0x65, 0x0A, 0x00, 0x00, 0x00, 0x00, +0x3A, 0x20, 0x52, 0x46, 0x2D, 0x25, 0x64, 0x20, +0x30, 0x78, 0x25, 0x78, 0x20, 0x3D, 0x20, 0x30, +0x78, 0x25, 0x78, 0x2C, 0x20, 0x62, 0x69, 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0x3F, 0x6A, @@ -8077,19 +10911,23 @@ u8 array_mp_8821c_fw_ap[] = { 0x76, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0x4E, 0xF5, 0x48, 0x9A, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A, 0x4E, 0xF5, 0x54, 0x9A, 0x40, 0xEA, 0x10, 0xF0, -0x23, 0x6A, 0x4B, 0xF6, 0x58, 0x9A, 0x32, 0x6B, +0x24, 0x6A, 0x76, 0xF5, 0x5C, 0x9A, 0x32, 0x6B, 0x30, 0xF0, 0x20, 0x6C, 0x60, 0xC2, 0x10, 0xF0, -0x23, 0x6A, 0x4B, 0xF6, 0x5C, 0x9A, 0x10, 0xF0, -0x23, 0x6B, 0x6B, 0xF6, 0x60, 0x9B, 0x40, 0xA2, -0x04, 0x05, 0xA5, 0xF3, 0x1C, 0x4C, 0x0C, 0xEA, +0x24, 0x6A, 0x96, 0xF5, 0x40, 0x9A, 0x10, 0xF0, +0x24, 0x6B, 0x96, 0xF5, 0x64, 0x9B, 0x40, 0xA2, +0x05, 0xF4, 0x10, 0x4C, 0x1C, 0x05, 0x0C, 0xEA, 0xFF, 0x4A, 0x0C, 0xEA, 0x40, 0xC3, 0x30, 0xF0, 0x20, 0x68, 0x4E, 0xF2, 0x50, 0x98, 0x54, 0x6E, 0x40, 0xEA, 0x4E, 0xF2, 0x50, 0x98, 0x30, 0xF0, -0x20, 0x6C, 0x2E, 0x05, 0x05, 0xF4, 0x10, 0x4C, +0x20, 0x6C, 0x65, 0xF4, 0x04, 0x4C, 0x07, 0x05, 0x54, 0x6E, 0x40, 0xEA, 0x4E, 0xF2, 0x50, 0x98, -0x30, 0xF0, 0x20, 0x6C, 0x65, 0xF4, 0x04, 0x4C, -0x19, 0x05, 0x54, 0x6E, 0x40, 0xEA, 0x47, 0x97, -0x46, 0x91, 0x45, 0x90, 0x24, 0x63, 0x00, 0xEF, +0x30, 0xF0, 0x20, 0x6C, 0x05, 0xF6, 0x1A, 0x4C, +0x04, 0x05, 0x0A, 0x6E, 0x40, 0xEA, 0x30, 0xF0, +0x20, 0x6A, 0x30, 0xF0, 0x20, 0x6B, 0xC5, 0xF4, +0x0A, 0x4A, 0x65, 0xF5, 0x12, 0x4B, 0x0A, 0x6C, +0x80, 0xCA, 0x00, 0x6C, 0xA0, 0xF0, 0x88, 0xCA, +0x02, 0x4A, 0x6A, 0xEA, 0xF8, 0x61, 0x35, 0x97, +0x34, 0x91, 0x33, 0x90, 0x1B, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF2, 0x58, 0x9A, 0x06, 0xD4, 0x09, 0xD7, 0x07, 0xD5, 0x08, 0xD6, 0x06, 0x04, 0x40, 0xEA, @@ -8098,137 +10936,221 @@ u8 array_mp_8821c_fw_ap[] = { 0x46, 0x67, 0x01, 0x4A, 0x05, 0x67, 0x0C, 0xD6, 0x27, 0x67, 0x1F, 0x22, 0x1F, 0xF7, 0x00, 0x6A, 0xAC, 0xEA, 0x02, 0xF0, 0x00, 0x72, 0x01, 0x60, -0x05, 0x2A, 0x10, 0xF0, 0x23, 0x6A, 0xCB, 0xF4, -0x44, 0x9A, 0x04, 0x10, 0x10, 0xF0, 0x23, 0x6A, -0xCB, 0xF4, 0x48, 0x9A, 0x49, 0xE0, 0x40, 0x9A, +0x05, 0x2A, 0x10, 0xF0, 0x24, 0x6A, 0x36, 0xF2, +0x58, 0x9A, 0x04, 0x10, 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0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x45, 0xE1, 0x85, 0xF2, 0x1C, 0xC1, 0x0F, 0x10, 0x0A, 0x74, 0x0D, 0x61, -0x10, 0xF0, 0x23, 0x6A, 0x2B, 0xF6, 0xEC, 0x9A, -0x10, 0xF0, 0x23, 0x6C, 0xCC, 0xF3, 0x14, 0x4C, +0x10, 0xF0, 0x24, 0x6A, 0x56, 0xF5, 0xF0, 0x9A, +0x10, 0xF0, 0x24, 0x6C, 0x17, 0xF3, 0x18, 0x4C, 0xF9, 0x6D, 0x28, 0xF3, 0x01, 0x6E, 0x80, 0x18, -0xBA, 0x0C, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, +0x70, 0x0F, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, 0xFF, 0x6A, 0x4C, 0xEC, 0x52, 0x6B, 0x78, 0xEC, 0x30, 0xF0, 0x20, 0x6E, 0x60, 0xF2, 0x08, 0x4E, @@ -9249,7 +12355,7 @@ u8 array_mp_8821c_fw_ap[] = { 0x07, 0x97, 0x04, 0x94, 0x54, 0xC6, 0x20, 0xF0, 0x5E, 0xA3, 0x55, 0xC6, 0x20, 0xF0, 0x5F, 0xA3, 0x56, 0xC6, 0x05, 0x95, 0x06, 0x96, 0x80, 0x18, -0x8C, 0x04, 0x09, 0x97, 0x05, 0x63, 0x00, 0xEF, +0x02, 0x05, 0x09, 0x97, 0x05, 0x63, 0x00, 0xEF, 0xF8, 0x63, 0x0F, 0x62, 0x0E, 0xD1, 0x0D, 0xD0, 0x14, 0x92, 0x15, 0x93, 0x16, 0x90, 0x0A, 0xD2, 0xFF, 0x6A, 0x1A, 0x65, 0xAC, 0xEA, 0x08, 0xD2, @@ -9270,7 +12376,7 @@ u8 array_mp_8821c_fw_ap[] = { 0x02, 0x30, 0x22, 0x31, 0x0C, 0x6A, 0x79, 0xC4, 0x1B, 0xC4, 0x3D, 0xC4, 0x4F, 0xCC, 0x05, 0x95, 0x04, 0x94, 0x06, 0x96, 0x07, 0x97, 0x80, 0x18, -0x8C, 0x04, 0x0F, 0x97, 0x0E, 0x91, 0x0D, 0x90, +0x02, 0x05, 0x0F, 0x97, 0x0E, 0x91, 0x0D, 0x90, 0x08, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, 0x20, 0xA4, 0x52, 0x68, 0x30, 0xF0, 0x20, 0x6A, 0x18, 0xE9, 0x60, 0xF2, @@ -9287,13 +12393,13 @@ u8 array_mp_8821c_fw_ap[] = { 0x80, 0x4A, 0xFF, 0x4A, 0x6C, 0xEA, 0xAD, 0xEA, 0x20, 0xF0, 0x55, 0xC0, 0x64, 0xA4, 0xCC, 0xEA, 0x40, 0xF0, 0x60, 0xC0, 0x0F, 0x22, 0x91, 0x67, -0x80, 0x18, 0xCF, 0x16, 0x20, 0xF0, 0xC5, 0xA0, +0x80, 0x18, 0xBE, 0x19, 0x20, 0xF0, 0xC5, 0xA0, 0x03, 0x6A, 0x20, 0xF0, 0xB2, 0xA0, 0xCA, 0x36, 0x4C, 0xEE, 0xFF, 0x6A, 0x91, 0x67, 0x4C, 0xEE, -0x80, 0x18, 0x15, 0x16, 0x20, 0xF0, 0xF5, 0xA0, +0x80, 0x18, 0x08, 0x19, 0x20, 0xF0, 0xF5, 0xA0, 0x20, 0xF0, 0xD2, 0xA0, 0x04, 0x95, 0x01, 0x6A, 0xF6, 0x37, 0x91, 0x67, 0x4C, 0xEF, 0x80, 0x18, -0xF6, 0x0F, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, +0x6D, 0x13, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x03, 0xA4, 0x44, 0xA4, 0xC0, 0xA4, 0x00, 0x30, 0x00, 0x30, 0x00, 0xF6, 0x40, 0x32, @@ -9303,7 +12409,7 @@ u8 array_mp_8821c_fw_ap[] = { 0x65, 0xF4, 0x40, 0xDB, 0xE5, 0xF2, 0xD8, 0xC3, 0x0A, 0x26, 0x01, 0x6C, 0x4C, 0xEC, 0x07, 0x24, 0xE5, 0xF2, 0xB9, 0xC3, 0xE5, 0xF2, 0xFA, 0xC3, -0x02, 0x25, 0x80, 0x18, 0x23, 0x16, 0x05, 0x97, +0x02, 0x25, 0x80, 0x18, 0x16, 0x19, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFA, 0x63, 0x0B, 0x62, 0x0A, 0xD1, 0x09, 0xD0, 0x20, 0xA4, 0x52, 0x68, 0x62, 0xA4, 0x18, 0xE9, @@ -9326,78 +12432,119 @@ u8 array_mp_8821c_fw_ap[] = { 0x46, 0xC0, 0x62, 0xA4, 0x20, 0xF0, 0xA5, 0xA0, 0x30, 0x6A, 0x4C, 0xEB, 0x9F, 0x4A, 0xAC, 0xEA, 0x6D, 0xEA, 0x20, 0xF0, 0x45, 0xC0, 0x10, 0xF0, -0x23, 0x6D, 0x10, 0xF0, 0x23, 0x6A, 0x2B, 0xF6, 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0xAA, 0xFF, 0xF7, 0x1F, 0x6C, +0x13, 0xE4, 0x63, 0xEC, 0x03, 0x61, 0x61, 0xE0, +0x02, 0xCA, 0x03, 0x10, 0x01, 0x6B, 0x6B, 0xEB, +0x62, 0xCA, 0x01, 0x91, 0x00, 0x90, 0x01, 0x63, +0x20, 0xE8, 0x00, 0x65, 0x10, 0xF0, 0x24, 0x6A, +0x76, 0xF5, 0xB8, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x80, 0xA5, 0xE5, 0xF2, 0xDB, 0xA2, 0x10, 0x6B, 0x8C, 0xEB, 0x02, 0x6C, 0x8B, 0xEC, 0x72, 0x33, 0xCC, 0xEC, 0x6D, 0xEC, @@ -9414,23 +12561,23 @@ u8 array_mp_8821c_fw_ap[] = { 0x4C, 0xED, 0x0A, 0xD6, 0x06, 0xD7, 0x12, 0xE8, 0x01, 0xE3, 0x7F, 0x6B, 0x6C, 0xEC, 0x1D, 0x2D, 0x0C, 0x5C, 0x05, 0x60, 0x30, 0xF0, 0x20, 0x6A, -0xCF, 0xF0, 0x08, 0x4A, 0x1C, 0x10, 0x06, 0x93, +0xEF, 0xF0, 0x14, 0x4A, 0x1C, 0x10, 0x06, 0x93, 0xF4, 0x4C, 0x4C, 0xEC, 0x08, 0x2B, 0x03, 0x6A, -0x58, 0xEC, 0x30, 0xF0, 0x20, 0x6A, 0xAF, 0xF2, -0x00, 0x4A, 0x12, 0xEC, 0x36, 0x10, 0xE0, 0x4C, +0x58, 0xEC, 0x30, 0xF0, 0x20, 0x6A, 0xCF, 0xF2, +0x0C, 0x4A, 0x12, 0xEC, 0x36, 0x10, 0xE0, 0x4C, 0x4C, 0xEC, 0x03, 0x6A, 0x58, 0xEC, 0x30, 0xF0, -0x20, 0x6A, 0x4F, 0xF2, 0x04, 0x4A, 0x12, 0xEC, +0x20, 0x6A, 0x6F, 0xF2, 0x10, 0x4A, 0x12, 0xEC, 0x2C, 0x10, 0x0C, 0x5C, 0x15, 0x60, 0x30, 0xF0, -0x20, 0x6A, 0xCF, 0xF0, 0x14, 0x4A, 0x91, 0xE2, +0x20, 0x6A, 0x0F, 0xF1, 0x00, 0x4A, 0x91, 0xE2, 0x30, 0xF0, 0x20, 0x6A, 0x80, 0xA4, 0x4E, 0xF5, 0x58, 0x9A, 0x0A, 0x95, 0x06, 0x96, 0x40, 0xEA, 0x20, 0xF0, 0x86, 0xA0, 0x19, 0x6B, 0x6B, 0xEB, 0x8C, 0xEB, 0x20, 0xF0, 0x66, 0xC0, 0xB5, 0x10, 0x06, 0x93, 0xF4, 0x4C, 0x4C, 0xEC, 0x08, 0x2B, 0x03, 0x6A, 0x58, 0xEC, 0x30, 0xF0, 0x20, 0x6A, -0x4F, 0xF3, 0x04, 0x4A, 0x12, 0xEC, 0x09, 0x10, +0x6F, 0xF3, 0x10, 0x4A, 0x12, 0xEC, 0x09, 0x10, 0xE0, 0x4C, 0x4C, 0xEC, 0x03, 0x6A, 0x58, 0xEC, -0x30, 0xF0, 0x20, 0x6A, 0xEF, 0xF2, 0x08, 0x4A, +0x30, 0xF0, 0x20, 0x6A, 0x0F, 0xF3, 0x14, 0x4A, 0x12, 0xEC, 0x91, 0xE2, 0x01, 0x6A, 0x4B, 0xEA, 0x7D, 0x67, 0x09, 0xD4, 0x00, 0x6C, 0x50, 0xC3, 0x51, 0xC3, 0x52, 0xC3, 0x07, 0xD4, 0x24, 0x67, @@ -9452,16 +12599,16 @@ u8 array_mp_8821c_fw_ap[] = { 0x20, 0xF0, 0x67, 0xA0, 0x02, 0x6A, 0x76, 0x33, 0x8C, 0xEB, 0x20, 0xF0, 0x95, 0xA0, 0x8C, 0xEA, 0x18, 0x22, 0x06, 0x94, 0x05, 0x24, 0x30, 0xF0, -0x20, 0x6A, 0xCF, 0xF4, 0x0C, 0x4A, 0x04, 0x10, -0x30, 0xF0, 0x20, 0x6A, 0xCF, 0xF4, 0x04, 0x4A, +0x20, 0x6A, 0xEF, 0xF4, 0x18, 0x4A, 0x04, 0x10, +0x30, 0xF0, 0x20, 0x6A, 0xEF, 0xF4, 0x10, 0x4A, 0xAF, 0x43, 0x01, 0x6C, 0xA3, 0xEC, 0x09, 0x61, 0xDD, 0x67, 0xB1, 0xA6, 0x40, 0x9A, 0x84, 0xED, 0x4C, 0xEC, 0x03, 0x24, 0x50, 0xA6, 0xB0, 0xC6, 0x51, 0xC6, 0x20, 0xF0, 0x95, 0xA0, 0x40, 0x6A, 0x8C, 0xEA, 0x19, 0x22, 0x06, 0x92, 0x05, 0x22, -0x30, 0xF0, 0x20, 0x6A, 0xCF, 0xF4, 0x1C, 0x4A, -0x04, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0xCF, 0xF4, -0x14, 0x4A, 0xFF, 0x4B, 0x01, 0x6C, 0x63, 0xEC, +0x30, 0xF0, 0x20, 0x6A, 0x0F, 0xF5, 0x08, 0x4A, +0x04, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0x0F, 0xF5, +0x00, 0x4A, 0xFF, 0x4B, 0x01, 0x6C, 0x63, 0xEC, 0x0A, 0x61, 0xBD, 0x67, 0x71, 0xA5, 0x40, 0x9A, 0x84, 0xEB, 0x4C, 0xEC, 0x04, 0x24, 0x01, 0x6A, 0x4B, 0xEA, 0x70, 0xC5, 0x51, 0xC5, 0xDD, 0x67, @@ -9474,278 +12621,365 @@ u8 array_mp_8821c_fw_ap[] = { 0x50, 0xA5, 0x0F, 0x97, 0x0E, 0x91, 0x0D, 0x90, 0x08, 0x63, 0x00, 0xEF, 0xFA, 0x63, 0x0B, 0x62, 0x0A, 0xD1, 0x09, 0xD0, 0xFF, 0x6A, 0x4C, 0xEC, +0x4C, 0xEE, 0x52, 0x6A, 0x58, 0xEC, 0x30, 0xF0, +0x20, 0x6A, 0x60, 0xF2, 0x08, 0x4A, 0xFF, 0xF7, +0x1F, 0x6B, 0x6C, 0xED, 0x0F, 0xD7, 0x04, 0xD5, +0x05, 0xD6, 0x12, 0xEC, 0x89, 0xE2, 0x86, 0x67, +0x06, 0xD2, 0x62, 0xF5, 0x1C, 0x4C, 0x30, 0xF0, +0x20, 0x6A, 0x84, 0x34, 0xC0, 0xF1, 0x08, 0x4A, +0x49, 0xE4, 0x05, 0xAA, 0x03, 0xED, 0x0B, 0xE5, +0x02, 0x60, 0x04, 0x94, 0x8B, 0xE0, 0x6C, 0xEA, +0xFF, 0x4A, 0xFF, 0xF7, 0x1F, 0x6B, 0x6C, 0xEA, +0x07, 0x5A, 0x1B, 0x60, 0x04, 0x92, 0x03, 0xEA, +0x0C, 0x60, 0x05, 0x93, 0x30, 0xF0, 0x20, 0x6A, +0xC0, 0xF1, 0x08, 0x4A, 0x62, 0xF5, 0x1C, 0x4B, +0x64, 0x33, 0x49, 0xE3, 0x65, 0xAA, 0xFF, 0x4B, +0x1A, 0x10, 0x05, 0x93, 0x30, 0xF0, 0x20, 0x6A, +0xC0, 0xF1, 0x08, 0x4A, 0x62, 0xF5, 0x1C, 0x4B, +0x64, 0x33, 0x49, 0xE3, 0x65, 0xAA, 0x01, 0x4B, +0x0E, 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0xF4, 0x10, 0x4C, 0x80, 0x18, +0x70, 0x0F, 0x05, 0x6B, 0x78, 0xE8, 0x30, 0xF0, +0x20, 0x6A, 0x2F, 0xF5, 0x18, 0x4A, 0x12, 0xEB, +0x49, 0xE3, 0x00, 0x6B, 0x00, 0xF2, 0x71, 0xC2, 0x01, 0x48, 0xFF, 0x6A, 0x4C, 0xE8, 0x80, 0x70, -0x83, 0x61, 0x80, 0x18, 0x20, 0x10, 0x30, 0xF0, +0x89, 0x61, 0x80, 0x18, 0x91, 0x13, 0x30, 0xF0, 0x20, 0x6A, 0x4E, 0xF5, 0x48, 0x9A, 0x40, 0xEA, 0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90, 0x06, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFB, 0x63, 0x09, 0x62, @@ -9757,116 +12991,103 @@ u8 array_mp_8821c_fw_ap[] = { 0x68, 0x34, 0x0D, 0x6B, 0x6B, 0xEB, 0xAC, 0xEB, 0x8D, 0xEB, 0x40, 0xA0, 0x20, 0xF0, 0x65, 0xC0, 0x7F, 0x6B, 0x2C, 0xEB, 0x63, 0xEA, 0x01, 0x60, -0x22, 0x67, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, -0x08, 0x4A, 0x65, 0xF4, 0x60, 0x9A, 0x04, 0x6C, -0x8C, 0xEB, 0x10, 0x23, 0x65, 0xF4, 0x44, 0x9A, -0x05, 0x5A, 0x0C, 0x61, 0x20, 0xF0, 0xC5, 0xA0, -0x10, 0xF0, 0x23, 0x6C, 0x03, 0x6A, 0xCA, 0x36, -0x0C, 0xF5, 0x00, 0x4C, 0xB1, 0x67, 0x4C, 0xEE, -0x80, 0x18, 0xBA, 0x0C, 0x5F, 0xA0, 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0x10, 0x10, 0x10, 0xF0, 0x24, 0x6A, +0x96, 0xF4, 0x18, 0x9A, 0x00, 0x6C, 0x01, 0x6D, +0xD0, 0x67, 0x00, 0x18, 0xF8, 0xE3, 0x0E, 0x6B, +0x6B, 0xEB, 0x4C, 0xEB, 0x00, 0x6C, 0x01, 0x6D, +0xD0, 0x67, 0x05, 0x6F, 0x6D, 0xEF, 0x0F, 0x10, +0x10, 0xF0, 0x24, 0x6A, 0x96, 0xF4, 0x18, 0x9A, +0x00, 0x6C, 0x01, 0x6D, 0xD0, 0x67, 0x00, 0x18, +0xF8, 0xE3, 0x02, 0x6F, 0xEB, 0xEF, 0x00, 0x6C, +0x01, 0x6D, 0xD0, 0x67, 0x4C, 0xEF, 0x00, 0x18, +0x0B, 0xE4, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, +0x04, 0x63, 0x00, 0xEF, 0x10, 0xF0, 0x21, 0x6A, 0x84, 0xF4, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0x8E, 0xF6, 0x48, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0x24, 0xF5, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B, @@ -11158,23 +14297,23 @@ u8 array_mp_8821c_fw_ap[] = { 0xAE, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0xC6, 0xF1, 0x0C, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x40, 0xDB, 0x20, 0xE8, 0x00, 0x65, -0x25, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +0x46, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -u32 array_length_mp_8821c_fw_ap = 89056; +u32 array_length_mp_8821c_fw_ap = 114208; #endif /*defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))*/ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) u8 array_mp_8821c_fw_nic[] = { -0x21, 0x88, 0x00, 0x00, 0x09, 0x00, 0x07, 0x00, -0x42, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x03, 0x0C, 0x12, 0x03, 0xE1, 0x07, 0x00, 0x00, -0x18, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, -0x00, 0x00, 0x20, 0x80, 0xC0, 0x7C, 0x00, 0x00, +0x21, 0x88, 0x00, 0x00, 0x14, 0x00, 0x01, 0x00, +0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, +0x07, 0x01, 0x0E, 0x32, 0xE2, 0x07, 0x00, 0x00, +0x18, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, +0x00, 0x00, 0x20, 0x80, 0xE0, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, -0xD8, 0xED, 0x00, 0x00, 0x98, 0x56, 0x00, 0x00, +0xC8, 0xFF, 0x00, 0x00, 0x90, 0x9C, 0x00, 0x00, 0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, @@ -11225,7 +14364,7 @@ u8 array_mp_8821c_fw_nic[] = { 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x01, 0x00, 0x03, 0x80, 0xA1, 0x01, 0x03, 0x80, 0xA1, 0x01, 0x03, 0x80, -0xA1, 0x64, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, +0xD1, 0x6F, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -15021,7 +18160,7 @@ u8 array_mp_8821c_fw_nic[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x51, 0x64, 0x03, 0x80, 0x01, 0x00, 0x00, 0x00, +0x81, 0x6F, 0x03, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -15029,146 +18168,150 @@ u8 array_mp_8821c_fw_nic[] = { 0x00, 0x00, 0x00, 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0x6C, 0x8C, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x77, 0xF0, @@ -15183,18 +18326,18 @@ u8 array_mp_8821c_fw_nic[] = { 0x20, 0x6C, 0xC0, 0xF1, 0x08, 0x4C, 0x00, 0x6E, 0x30, 0xF0, 0x20, 0x6F, 0x2F, 0xF0, 0x08, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, 0xE3, 0xEC, 0xB8, 0x67, -0xFB, 0x2D, 0x30, 0xF0, 0x21, 0x6C, 0xD0, 0xF2, -0x04, 0x4C, 0x00, 0x6E, 0x30, 0xF0, 0x21, 0x6F, -0x10, 0xF4, 0x10, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, +0xFB, 0x2D, 0x30, 0xF0, 0x21, 0x6C, 0x50, 0xF5, +0x18, 0x4C, 0x00, 0x6E, 0x30, 0xF0, 0x21, 0x6F, +0xB0, 0xF6, 0x00, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, 0xE3, 0xEC, 0xB8, 0x67, 0xFB, 0x2D, 0x10, 0xF0, 0x23, 0x6C, 0x80, 0xF0, 0x19, 0x4C, 0x00, 0xEC, 0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x10, 0xF0, -0x24, 0x6B, 0xFB, 0xF6, 0x6C, 0x9B, 0x10, 0xF0, +0x24, 0x6B, 0xFD, 0xF5, 0x64, 0x9B, 0x10, 0xF0, 0x23, 0x6A, 0x80, 0xF0, 0x19, 0x4A, 0x40, 0xDB, -0x00, 0x1C, 0x94, 0x00, 0x00, 0x18, 0x56, 0xC9, -0x00, 0x18, 0x92, 0xC6, 0x00, 0x18, 0xB2, 0xC6, -0x00, 0x18, 0x2C, 0xC9, 0x00, 0x18, 0xCD, 0xC6, -0x00, 0x18, 0x47, 0xC9, 0x00, 0x18, 0x8B, 0xCA, +0x00, 0x1C, 0x94, 0x00, 0x00, 0x18, 0x9C, 0xCA, +0x00, 0x18, 0xDA, 0xC7, 0x00, 0x18, 0xFD, 0xC7, +0x00, 0x18, 0x71, 0xCA, 0x00, 0x18, 0x28, 0xC8, +0x00, 0x18, 0x8D, 0xCA, 0x00, 0x18, 0xF3, 0xCB, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF7, 0x54, 0x9A, 0x30, 0xF0, 0x20, 0x68, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6C, 0x30, 0xF0, 0x21, 0x6A, 0x80, 0xF1, @@ -15204,13 +18347,13 @@ u8 array_mp_8821c_fw_nic[] = { 0x30, 0xF0, 0x20, 0x6A, 0xEE, 0xF7, 0x50, 0x9A, 0x30, 0xF0, 0x20, 0x6C, 0x6F, 0xF0, 0x08, 0x4C, 0x01, 0x6D, 0x40, 0xEA, 0x30, 0xF0, 0x21, 0x6B, -0x10, 0xF4, 0x44, 0xDB, 0x30, 0xF0, 0x20, 0x6C, +0x90, 0xF6, 0x54, 0xDB, 0x30, 0xF0, 0x20, 0x6C, 0x30, 0xF0, 0x21, 0x6A, 0x2F, 0xF0, 0x08, 0x4C, 0x15, 0xF4, 0x00, 0x4A, 0x43, 0xDC, 0xCE, 0xF7, 0x40, 0x98, 0x00, 0x6D, 0x40, 0xEA, 0x30, 0xF0, -0x21, 0x6B, 0xF0, 0xF3, 0x5C, 0xDB, 0x00, 0x18, -0x03, 0xC8, 0x10, 0xF0, 0x24, 0x6A, 0x3C, 0xF0, -0x6C, 0x9A, 0xFF, 0xF7, 0x1F, 0x6C, 0x10, 0xF0, +0x21, 0x6B, 0x90, 0xF6, 0x4C, 0xDB, 0x00, 0x18, +0x48, 0xC9, 0x10, 0xF0, 0x24, 0x6A, 0x1D, 0xF7, +0x64, 0x9A, 0xFF, 0xF7, 0x1F, 0x6C, 0x10, 0xF0, 0x00, 0x6D, 0x40, 0xAB, 0xAB, 0xED, 0x8C, 0xEA, 0xAD, 0xEA, 0x8C, 0xEA, 0x40, 0xCB, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF7, 0x58, 0x9A, 0x40, 0xEA, @@ -15219,7 +18362,7 @@ u8 array_mp_8821c_fw_nic[] = { 0x2D, 0xF1, 0x40, 0x9B, 0x01, 0x4A, 0x10, 0x72, 0x2D, 0xF1, 0x40, 0xDB, 0x09, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x30, 0xF0, 0x21, 0x6B, 0xEE, 0xF7, -0x58, 0x9A, 0x10, 0xF4, 0x88, 0x9B, 0x40, 0xEA, +0x58, 0x9A, 0x90, 0xF6, 0x98, 0x9B, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0x6D, 0xB8, 0x00, 0x65, 0x00, 0xF0, 0x20, 0x6A, 0x7C, 0x4A, 0x6C, 0xEA, 0x1C, 0x22, 0x00, 0xF0, @@ -15229,7 +18372,7 @@ u8 array_mp_8821c_fw_nic[] = { 0x1A, 0x6A, 0x6A, 0xEA, 0x31, 0x60, 0x77, 0xF0, 0x24, 0x6A, 0xA0, 0xF1, 0x1C, 0x4A, 0x1D, 0xF4, 0x00, 0x6B, 0x60, 0xDA, 0x10, 0xF0, 0x23, 0x6A, -0xC5, 0xF1, 0x1D, 0x4A, 0x00, 0xEA, 0x00, 0xF0, +0x65, 0xF7, 0x1D, 0x4A, 0x00, 0xEA, 0x00, 0xF0, 0x20, 0x6A, 0x1F, 0xF7, 0x00, 0x6A, 0x4C, 0xEB, 0x4C, 0xB8, 0x00, 0x65, 0x6C, 0xEA, 0x42, 0x32, 0x30, 0xF0, 0x20, 0x6B, 0x00, 0xF0, 0x00, 0x4B, @@ -15265,7 +18408,7 @@ u8 array_mp_8821c_fw_nic[] = { 0x6A, 0x9B, 0xCF, 0xF7, 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, -0x10, 0xF0, 0x23, 0x6C, 0xC5, 0xF1, 0x1D, 0x4C, +0x10, 0xF0, 0x23, 0x6C, 0x65, 0xF7, 0x1D, 0x4C, 0x00, 0xEC, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6B, 0x2D, 0xF1, 0x18, 0x4B, 0x41, 0x9B, 0x40, 0xDB, 0x89, 0x9A, 0xBC, 0x65, 0x7D, 0x67, 0xDF, 0xF7, @@ -15313,7 +18456,7 @@ u8 array_mp_8821c_fw_nic[] = { 0x6A, 0x9B, 0xCF, 0xF7, 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, -0x10, 0xF0, 0x23, 0x6C, 0xC5, 0xF1, 0x1D, 0x4C, +0x10, 0xF0, 0x23, 0x6C, 0x65, 0xF7, 0x1D, 0x4C, 0x00, 0xEC, 0x00, 0x65, 0x40, 0x9A, 0x30, 0xF0, 0x20, 0x6C, 0xAD, 0xF1, 0x08, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, 0x82, 0x67, 0x40, 0xEA, @@ -15350,392 +18493,541 @@ u8 array_mp_8821c_fw_nic[] = { 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0xB7, 0xC1, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, -0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x82, 0xC2, +0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0xFC, 0xC2, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, -0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x94, 0xC2, +0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x0E, 0xC3, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x76, 0xC1, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, -0x10, 0xF0, 0x24, 0x6B, 0xFB, 0xF6, 0x6C, 0x9B, +0x10, 0xF0, 0x24, 0x6B, 0xFD, 0xF5, 0x64, 0x9B, 0x10, 0xF0, 0x23, 0x6A, 0xC0, 0xF5, 0x19, 0x4A, 0x40, 0xDB, 0x01, 0x4A, 0x40, 0xDB, 0x20, 0xE8, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, -0x10, 0xF0, 0x24, 0x6A, 0xFB, 0xF6, 0x2C, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0xFD, 0xF5, 0x24, 0x9A, 0x10, 0xF0, 0x23, 0x68, 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0x9B, 0x6D, 0xEA, +0x10, 0xF0, 0x24, 0x6B, 0x1E, 0xF2, 0x60, 0x9B, +0x13, 0x10, 0x10, 0xF0, 0x24, 0x6B, 0x1E, 0xF2, +0x64, 0x9B, 0x6D, 0xEA, 0x10, 0xF0, 0x24, 0x6B, +0x1E, 0xF2, 0x68, 0x9B, 0x09, 0x10, 0x10, 0xF0, +0x24, 0x6B, 0x1E, 0xF2, 0x6C, 0x9B, 0x6D, 0xEA, +0x10, 0xF0, 0x24, 0x6B, 0x1E, 0xF2, 0x70, 0x9B, +0x6C, 0xEA, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF4, +0x70, 0x9B, 0x01, 0x6D, 0xA1, 0xF4, 0x18, 0x6C, +0xAB, 0xED, 0xC2, 0x67, 0x40, 0xEB, 0x07, 0x97, +0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0xFF, 0x6A, 0x4C, 0xED, 0xFF, 0x75, 0x4C, 0xEC, 0xCC, 0xEA, 0x06, 0x61, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x71, 0xE4, 0x0B, 0x10, @@ -15747,37 +19039,37 @@ u8 array_mp_8821c_fw_nic[] = { 0x08, 0x93, 0x1F, 0x6A, 0x4C, 0xEB, 0x08, 0xD3, 0x42, 0xA4, 0x61, 0xA4, 0x0B, 0xD2, 0x43, 0xA4, 0x84, 0xA4, 0x09, 0xD4, 0x08, 0x94, 0x08, 0x5C, -0x80, 0xF0, 0x11, 0x60, 0xFF, 0x69, 0x84, 0x30, -0x29, 0x22, 0x09, 0x94, 0x27, 0x24, 0x2C, 0xEA, +0x80, 0xF0, 0x11, 0x60, 0x84, 0x30, 0x09, 0x94, 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0x6A, 0xBC, 0xF2, -0x54, 0x9A, 0x2F, 0x10, 0x80, 0xF4, 0x44, 0x40, +0x10, 0xF0, 0x24, 0x6A, 0xDE, 0xF2, 0x48, 0x9A, +0x34, 0x10, 0x10, 0xF0, 0x24, 0x6A, 0xFD, 0xF7, +0x44, 0x9A, 0x2F, 0x10, 0x80, 0xF4, 0x44, 0x40, 0x1F, 0xF7, 0x00, 0x6B, 0x6C, 0xEA, 0x05, 0x2A, -0x10, 0xF0, 0x24, 0x6A, 0xBC, 0xF2, 0x58, 0x9A, -0x24, 0x10, 0x10, 0xF0, 0x24, 0x6A, 0xBC, 0xF2, -0x5C, 0x9A, 0x1F, 0x10, 0xC0, 0xF4, 0x48, 0x40, +0x10, 0xF0, 0x24, 0x6A, 0xDE, 0xF2, 0x4C, 0x9A, +0x24, 0x10, 0x10, 0xF0, 0x24, 0x6A, 0xFD, 0xF7, +0x50, 0x9A, 0x1F, 0x10, 0xC0, 0xF4, 0x48, 0x40, 0x1F, 0xF7, 0x00, 0x6B, 0x6C, 0xEA, 0x05, 0x2A, -0x10, 0xF0, 0x24, 0x6A, 0xDC, 0xF2, 0x40, 0x9A, -0x14, 0x10, 0x10, 0xF0, 0x24, 0x6A, 0xDC, 0xF2, -0x44, 0x9A, 0x0F, 0x10, 0x70, 0xF4, 0x48, 0x40, +0x10, 0xF0, 0x24, 0x6A, 0xDE, 0xF2, 0x50, 0x9A, +0x14, 0x10, 0x10, 0xF0, 0x24, 0x6A, 0xDE, 0xF2, +0x54, 0x9A, 0x0F, 0x10, 0x70, 0xF4, 0x48, 0x40, 0x1F, 0xF7, 0x00, 0x6B, 0x6C, 0xEA, 0x05, 0x2A, -0x10, 0xF0, 0x24, 0x6A, 0xDC, 0xF2, 0x48, 0x9A, -0x04, 0x10, 0x10, 0xF0, 0x24, 0x6A, 0xDC, 0xF2, -0x4C, 0x9A, 0x49, 0xE0, 0x60, 0xAA, 0xFF, 0xF7, +0x10, 0xF0, 0x24, 0x6A, 0xDE, 0xF2, 0x58, 0x9A, +0x04, 0x10, 0x10, 0xF0, 0x24, 0x6A, 0xDE, 0xF2, +0x5C, 0x9A, 0x49, 0xE0, 0x60, 0xAA, 0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA, 0x7D, 0x67, 0x53, 0xC3, 0x42, 0x32, 0x54, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x41, 0xE0, 0x0C, 0xF7, @@ -15797,200 +19089,211 @@ u8 array_mp_8821c_fw_nic[] = { 0x2C, 0xF7, 0x5E, 0xC3, 0x20, 0xE8, 0x00, 0x65, 0xFA, 0x63, 0x0B, 0x62, 0x0A, 0xD1, 0x09, 0xD0, 0x01, 0xA4, 0x20, 0xA4, 0x0C, 0x20, 0x90, 0x67, -0xB1, 0x67, 0x00, 0x18, 0xD8, 0xC4, 0x30, 0xF0, +0xB1, 0x67, 0x00, 0x18, 0x02, 0xC6, 0x30, 0xF0, 0x20, 0x6A, 0x6E, 0xF2, 0x58, 0x9A, 0x90, 0x67, 0xB1, 0x67, 0x53, 0x6E, 0x40, 0xEA, 0x7D, 0x67, 0x20, 0x6A, 0x50, 0xC3, 0x03, 0x6A, 0x4F, 0xCB, -0x10, 0xF0, 0x24, 0x6A, 0x7C, 0xF0, 0x54, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0x3D, 0xF7, 0x5C, 0x9A, 0x9D, 0x67, 0x40, 0xA2, 0x52, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x2C, 0xF7, 0x7E, 0xA2, 0x2C, 0xF7, 0x5F, 0xA2, 0x73, 0xC4, 0x54, 0xC4, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF2, 0x58, 0x9A, 0x04, 0x04, 0x40, 0xEA, 0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90, 0x06, 0x63, 0x00, 0xEF, -0xFC, 0x63, 0x07, 0x62, 0x06, 0xD0, 0x30, 0xF0, -0x20, 0x6A, 0x4E, 0xF2, 0x50, 0x9A, 0xA4, 0x67, -0x30, 0xF0, 0x21, 0x6C, 0x90, 0xF0, 0x0A, 0x4C, -0x07, 0x6E, 0x40, 0xEA, 0x30, 0xF0, 0x21, 0x6A, -0x90, 0xF0, 0x4A, 0xA2, 0x05, 0x5A, 0x13, 0x60, -0x10, 0xF0, 0x24, 0x6B, 0x48, 0x32, 0x9B, 0xF5, -0x10, 0x4B, 0x4D, 0xE3, 0x40, 0x9B, 0x00, 0xEA, -0x00, 0x6C, 0x07, 0x10, 0x01, 0x6C, 0x05, 0x10, -0x02, 0x6C, 0x03, 0x10, 0x03, 0x6C, 0x01, 0x10, -0x04, 0x6C, 0x00, 0x18, 0x02, 0xE2, 0x30, 0xF0, -0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x69, 0xF3, -0x48, 0xA3, 0x1F, 0x6C, 0x01, 0x6D, 0x4A, 0x32, -0x8C, 0xEA, 0x30, 0xF0, 0x21, 0x6C, 0x90, 0xF0, -0x8A, 0xA4, 0x47, 0xEC, 0xAC, 0xEA, 0x03, 0x22, -0x69, 0xF3, 0x89, 0xC3, 0x04, 0x10, 0x01, 0x6A, -0x4B, 0xEA, 0x69, 0xF3, 0x49, 0xC3, 0x30, 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0xE0, 0x40, 0xC0, 0x30, 0xF0, 0x20, 0x6A, 0xE8, 0xF2, 0x3B, 0xC2, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0x10, 0xF0, 0x23, 0x6B, 0x30, 0xF0, 0x20, 0x6A, -0xC5, 0xF1, 0x1D, 0x4B, 0x40, 0xF1, 0x68, 0xDA, +0x65, 0xF7, 0x1D, 0x4B, 0x40, 0xF1, 0x68, 0xDA, 0x10, 0xF0, 0x23, 0x6B, 0x40, 0xF1, 0x08, 0x4A, 0x40, 0xF5, 0x0D, 0x4B, 0x61, 0xDA, 0x10, 0xF0, 0x23, 0x6B, 0xC0, 0xF5, 0x09, 0x4B, 0x62, 0xDA, @@ -16006,508 +19309,528 @@ u8 array_mp_8821c_fw_nic[] = { 0xFB, 0x61, 0x42, 0xF4, 0x10, 0x6A, 0x1F, 0xF7, 0x00, 0x6B, 0x4C, 0xEB, 0x02, 0xF0, 0x00, 0x73, 0x01, 0x60, 0x05, 0x2B, 0x10, 0xF0, 0x24, 0x6B, -0x1B, 0xF7, 0x6C, 0x9B, 0x04, 0x10, 0x10, 0xF0, -0x24, 0x6B, 0x1B, 0xF7, 0x70, 0x9B, 0x6D, 0xE2, +0x1D, 0xF6, 0x6C, 0x9B, 0x04, 0x10, 0x10, 0xF0, +0x24, 0x6B, 0x1D, 0xF6, 0x70, 0x9B, 0x6D, 0xE2, 0x04, 0x4A, 0x00, 0x6C, 0x62, 0xF4, 0x00, 0x72, 0x80, 0xDB, 0xE9, 0x61, 0x20, 0xE8, 0x00, 0x65, +0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, +0x4E, 0xF2, 0x4C, 0x9A, 0x30, 0xF0, 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0x18, 0x08, 0xDD, 0x00, 0x1C, 0x96, 0x45, 0xFF, 0x17, 0x30, 0xF0, 0x20, 0x6A, 0x00, 0xF1, 0x00, 0x4A, 0x60, 0xDA, 0x81, 0xDA, 0xA2, 0xDA, 0xC3, 0xDA, 0xE4, 0xDA, 0x05, 0xDA, @@ -16517,7 +19840,7 @@ u8 array_mp_8821c_fw_nic[] = { 0x00, 0x65, 0x6C, 0xDA, 0x68, 0xB8, 0x00, 0x65, 0x6D, 0xDA, 0x6C, 0xB8, 0x00, 0x65, 0x6E, 0xDA, 0x6E, 0xB8, 0x00, 0x65, 0x6F, 0xDA, 0x10, 0xF0, -0x23, 0x6A, 0x65, 0xF1, 0x11, 0x4A, 0x00, 0xEA, +0x23, 0x6A, 0xC5, 0xF6, 0x19, 0x4A, 0x00, 0xEA, 0x00, 0x65, 0x00, 0x65, 0x10, 0xF0, 0x23, 0x6A, 0x40, 0xF2, 0x0D, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x44, 0xDB, 0x10, 0xF0, 0x23, 0x6A, @@ -16527,11 +19850,11 @@ u8 array_mp_8821c_fw_nic[] = { 0xCE, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x23, 0x6A, 0x20, 0xF5, 0x15, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x23, 0x6A, -0x65, 0xF1, 0x11, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xC5, 0xF6, 0x19, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x23, 0x6A, -0xC5, 0xF1, 0x1D, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0x65, 0xF7, 0x1D, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x23, 0x6A, -0x45, 0xF1, 0x19, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xC5, 0xF6, 0x01, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0xE2, 0xF5, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xEE, 0xF6, 0x40, 0xDB, 0x10, 0xF0, 0x21, 0x6A, @@ -16587,7 +19910,7 @@ u8 array_mp_8821c_fw_nic[] = { 0x4E, 0xF7, 0x44, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0xA1, 0xF1, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0x4E, 0xF7, 0x48, 0xDB, 0x10, 0xF0, 0x23, 0x6A, -0x25, 0xF1, 0x09, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0x85, 0xF6, 0x11, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0x4E, 0xF7, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0xFF, 0xF7, 0x1C, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0x4E, 0xF7, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A, @@ -16687,19 +20010,19 @@ u8 array_mp_8821c_fw_nic[] = { 0x02, 0xF0, 0x00, 0x75, 0x01, 0x60, 0x25, 0x2D, 0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA, 0x02, 0xF0, 0x00, 0x72, 0x01, 0x60, 0x07, 0x2A, 0x10, 0xF0, -0x24, 0x6A, 0x1B, 0xF7, 0xAC, 0x9A, 0xB5, 0xE3, +0x24, 0x6A, 0x1D, 0xF6, 0xAC, 0x9A, 0xB5, 0xE3, 0x60, 0xA5, 0x0B, 0x10, 0x10, 0xF0, 0x24, 0x6A, -0x1B, 0xF7, 0xAC, 0x9A, 0x10, 0xF0, 0x24, 0x6A, -0x1B, 0xF7, 0x50, 0x9A, 0xB5, 0xE3, 0x4D, 0xE3, +0x1D, 0xF6, 0xAC, 0x9A, 0x10, 0xF0, 0x24, 0x6A, +0x1D, 0xF6, 0x50, 0x9A, 0xB5, 0xE3, 0x4D, 0xE3, 0x60, 0xA3, 0x01, 0x6A, 0x00, 0xF6, 0x60, 0x33, 0x44, 0xEE, 0x00, 0xF6, 0x63, 0x33, 0x4F, 0xEA, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x40, 0xC5, -0x0E, 0x10, 0x10, 0xF0, 0x24, 0x6D, 0x1B, 0xF7, +0x0E, 0x10, 0x10, 0xF0, 0x24, 0x6D, 0x1D, 0xF6, 0xB0, 0x9D, 0x0F, 0xE8, 0xAD, 0xE3, 0xA0, 0xA3, 0x00, 0xF6, 0xA0, 0x35, 0x00, 0xF6, 0xA3, 0x35, 0x0C, 0xED, 0x4C, 0xED, 0xA0, 0xC3, 0x30, 0xF0, -0x21, 0x6A, 0x90, 0xF0, 0x4B, 0xA2, 0x4E, 0xEC, -0x52, 0x2C, 0x10, 0xF0, 0x24, 0x6A, 0x1B, 0xF7, +0x21, 0x6A, 0x90, 0xF2, 0x41, 0xA2, 0x4E, 0xEC, +0x52, 0x2C, 0x10, 0xF0, 0x24, 0x6A, 0x1D, 0xF6, 0x54, 0x9A, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x70, 0x33, 0x00, 0xF5, 0x62, 0x33, 0x48, 0xF5, 0x68, 0xCA, 0x45, 0x10, 0x30, 0xF0, 0x20, 0x6C, @@ -16709,116 +20032,116 @@ u8 array_mp_8821c_fw_nic[] = { 0x00, 0x6C, 0x6C, 0xEC, 0x02, 0xF0, 0x00, 0x74, 0x01, 0x60, 0x24, 0x2C, 0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA, 0x02, 0xF0, 0x00, 0x72, 0x01, 0x60, -0x07, 0x2A, 0x10, 0xF0, 0x24, 0x6A, 0x1B, 0xF7, +0x07, 0x2A, 0x10, 0xF0, 0x24, 0x6A, 0x1D, 0xF6, 0x8C, 0x9A, 0x91, 0xE3, 0x60, 0xA4, 0x0B, 0x10, -0x10, 0xF0, 0x24, 0x6A, 0x1B, 0xF7, 0x8C, 0x9A, -0x10, 0xF0, 0x24, 0x6A, 0x1B, 0xF7, 0x50, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0x1D, 0xF6, 0x8C, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0x1D, 0xF6, 0x50, 0x9A, 0x91, 0xE3, 0x4D, 0xE3, 0x60, 0xA3, 0x00, 0xF6, 0x60, 0x33, 0x01, 0x6A, 0x00, 0xF6, 0x63, 0x33, 0x44, 0xEE, 0x6D, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x40, 0xC4, 0x0D, 0x10, 0x10, 0xF0, 0x24, 0x6C, -0x1B, 0xF7, 0x90, 0x9C, 0x8D, 0xE3, 0x80, 0xA3, +0x1D, 0xF6, 0x90, 0x9C, 0x8D, 0xE3, 0x80, 0xA3, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xAD, 0xEC, 0x4C, 0xEC, 0x80, 0xC3, 0x01, 0x90, 0x01, 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0xEC, 0x01, 0x74, 0xAC, 0xEA, 0x13, 0x60, 0x03, 0x24, 0x02, 0x74, 0x15, 0x60, 0x18, 0x10, 0x30, 0xF0, @@ -16828,25 +20151,25 @@ u8 array_mp_8821c_fw_nic[] = { 0x59, 0xC3, 0x09, 0x10, 0x30, 0xF0, 0x20, 0x6B, 0x48, 0xF5, 0x44, 0xC3, 0x04, 0x10, 0x30, 0xF0, 0x20, 0x6B, 0x48, 0xF5, 0x40, 0xC3, 0x10, 0xF0, -0x24, 0x6A, 0x7B, 0xF7, 0x48, 0x9A, 0x60, 0xA2, +0x24, 0x6A, 0x7D, 0xF6, 0x48, 0x9A, 0x60, 0xA2, 0x10, 0x6A, 0x6C, 0xEA, 0x24, 0x22, 0x02, 0x5C, 0x03, 0x61, 0x02, 0x74, 0x17, 0x60, 0x20, 0xE8, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x68, 0xF3, 0x99, 0xA3, 0x01, 0x6A, 0x8C, 0xEA, 0x68, 0xF3, 0x9C, 0xA3, 0x7F, 0x6B, 0x5C, 0x32, 0x8C, 0xEB, 0x6D, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, -0x10, 0xF0, 0x24, 0x6B, 0x7B, 0xF7, 0x6C, 0x9B, +0x10, 0xF0, 0x24, 0x6B, 0x7D, 0xF6, 0x6C, 0x9B, 0x40, 0xC3, 0x20, 0xE8, 0x30, 0xF0, 0x20, 0x6A, 0x48, 0xF5, 0x60, 0xA2, 0x10, 0xF0, 0x24, 0x6A, -0x7B, 0xF7, 0x50, 0x9A, 0x60, 0xC2, 0x20, 0xE8, +0x7D, 0xF6, 0x50, 0x9A, 0x60, 0xC2, 0x20, 0xE8, 0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, 0x4E, 0xF2, 0x4C, 0x9A, 0x30, 0xF0, 0x21, 0x6C, -0x90, 0xF0, 0x0A, 0x4C, 0x00, 0x6D, 0x07, 0x6E, +0x90, 0xF2, 0x00, 0x4C, 0x00, 0x6D, 0x07, 0x6E, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, -0x10, 0xF0, 0x24, 0x6A, 0x7B, 0xF7, 0x54, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0x7D, 0xF6, 0x54, 0x9A, 0x60, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0xFF, 0x72, 0x00, 0x6A, 0x0B, 0x61, 0x10, 0xF0, 0x24, 0x6A, -0x7B, 0xF7, 0x58, 0x9A, 0x60, 0xA2, 0x07, 0x6A, +0x7D, 0xF6, 0x58, 0x9A, 0x60, 0xA2, 0x07, 0x6A, 0x6C, 0xEA, 0x07, 0x6B, 0x6E, 0xEA, 0x01, 0x5A, 0x58, 0x67, 0x20, 0xE8, 0xFF, 0x6A, 0x4C, 0xEC, 0x01, 0x74, 0xAC, 0xEA, 0x03, 0x60, 0x02, 0x74, @@ -16860,22 +20183,19 @@ u8 array_mp_8821c_fw_nic[] = { 0x08, 0x4A, 0x88, 0xF3, 0x62, 0xA2, 0x68, 0xF3, 0x99, 0xA2, 0x88, 0xF3, 0x63, 0xC2, 0x40, 0x6B, 0x8D, 0xEB, 0x68, 0xF3, 0x79, 0xC2, 0x20, 0xE8, -0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x14, 0xCD, -0x01, 0x72, 0x00, 0x6A, 0x19, 0x61, 0x30, 0xF0, -0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x68, 0xF3, -0xB9, 0xA2, 0x04, 0x6B, 0xFF, 0x6C, 0xAC, 0xEB, -0x0B, 0x23, 0x10, 0xF0, 0x24, 0x6A, 0x7B, 0xF7, -0x7C, 0x9A, 0x40, 0xA3, 0x8C, 0xEA, 0x01, 0x4A, -0x8C, 0xEA, 0x40, 0xC3, 0x00, 0x6A, 0x04, 0x10, -0x68, 0xF3, 0x58, 0xA2, 0x05, 0x5A, 0x58, 0x67, -0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, +0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x7C, 0xCE, +0x01, 0x72, 0x0E, 0x61, 0x30, 0xF0, 0x20, 0x6A, +0xC0, 0xF1, 0x08, 0x4A, 0x68, 0xF3, 0x99, 0xA2, +0x04, 0x6B, 0x8C, 0xEB, 0x05, 0x2B, 0x68, 0xF3, +0x58, 0xA2, 0x05, 0x5A, 0x58, 0x67, 0x01, 0x10, +0x00, 0x6A, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x20, 0x68, 0xC0, 0xF1, 0x08, 0x48, 0xA9, 0xF0, 0x68, 0xA0, 0x01, 0x6A, 0xFF, 0x69, 0x4C, 0xEB, 0x09, 0x23, 0xC9, 0xF0, 0x65, 0xA0, 0x6C, 0xEA, 0x2C, 0xEA, 0x21, 0x2A, 0x68, 0xF3, 0x58, 0xA0, 0x1E, 0x2A, 0x18, 0x10, 0x00, 0x18, -0x14, 0xCD, 0x01, 0x72, 0x19, 0x61, 0x68, 0xF3, +0x7C, 0xCE, 0x01, 0x72, 0x19, 0x61, 0x68, 0xF3, 0x7D, 0xA0, 0x03, 0x6A, 0x6C, 0xEA, 0x14, 0x2A, 0x68, 0xF3, 0x58, 0xA0, 0x11, 0x2A, 0x04, 0x6A, 0x6C, 0xEA, 0x0E, 0x2A, 0x10, 0x6A, 0x6C, 0xEA, @@ -16884,154 +20204,147 @@ u8 array_mp_8821c_fw_nic[] = { 0x52, 0xA0, 0x01, 0x5A, 0x58, 0x67, 0x01, 0x10, 0x00, 0x6A, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, -0x10, 0xF0, 0x24, 0x6A, 0x9B, 0xF7, 0x40, 0x9A, -0x40, 0xA2, 0x1E, 0x2A, 0x10, 0xF0, 0x24, 0x6A, -0x9B, 0xF7, 0x44, 0x9A, 0x40, 0xA2, 0x18, 0x2A, -0x10, 0xF0, 0x24, 0x6A, 0x9B, 0xF7, 0x48, 0x9A, -0x60, 0xA2, 0x02, 0x6A, 0x6C, 0xEA, 0x10, 0x22, -0x00, 0x18, 0x14, 0xCD, 0x01, 0x72, 0x01, 0x6A, -0x0C, 0x60, 0x10, 0xF0, 0x24, 0x6A, 0x9B, 0xF7, -0x6C, 0x9A, 0x10, 0xF0, 0x24, 0x6C, 0x9B, 0xF7, -0x90, 0x9C, 0x40, 0x9B, 0x8D, 0xEA, 0x40, 0xDB, -0x00, 0x6A, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, -0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, -0x30, 0xF0, 0x20, 0x68, 0xC0, 0xF1, 0x08, 0x48, -0x68, 0xF3, 0x7D, 0xA0, 0x10, 0x6A, 0xFF, 0x69, -0x6D, 0xEA, 0x88, 0xF3, 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0xD7, 0xA2, 0x03, 0x6F, +0x00, 0x18, 0xDF, 0xCE, 0x00, 0x6C, 0x00, 0x18, +0x5D, 0xCF, 0x09, 0x10, 0x30, 0xF0, 0x20, 0x6C, +0x00, 0x6B, 0xE8, 0xF3, 0xC0, 0xA2, 0x68, 0xF5, +0x04, 0x4C, 0x43, 0x67, 0x7E, 0x17, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, 0x30, 0xF0, 0x20, 0x6B, 0x28, 0xF5, 0xBF, 0xA3, 0x04, 0x6B, 0xFF, 0x6A, 0xAC, 0xEB, 0x4C, 0xEB, @@ -17042,7 +20355,7 @@ u8 array_mp_8821c_fw_nic[] = { 0x00, 0xEF, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x21, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x24, 0x67, 0x6E, 0xF5, -0x58, 0x9A, 0x90, 0xF0, 0x8B, 0xA3, 0xFF, 0x68, +0x58, 0x9A, 0x90, 0xF2, 0x81, 0xA3, 0xFF, 0x68, 0x0C, 0xE9, 0x40, 0xEA, 0x01, 0x72, 0x35, 0x61, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x68, 0xF3, 0x94, 0xA3, 0x7F, 0x6A, 0x8C, 0xEA, @@ -17050,360 +20363,463 @@ u8 array_mp_8821c_fw_nic[] = { 0x0F, 0x6A, 0x6C, 0xEA, 0x01, 0x72, 0x25, 0x61, 0x05, 0x59, 0x03, 0x61, 0xA0, 0xF6, 0x08, 0x6A, 0x07, 0x10, 0x10, 0xF0, 0x24, 0x6A, 0x24, 0x31, -0x3B, 0xF2, 0x04, 0x4A, 0x49, 0xE1, 0x40, 0xAA, +0x9D, 0xF0, 0x14, 0x4A, 0x49, 0xE1, 0x40, 0xAA, 0x61, 0x42, 0x1F, 0xF7, 0x00, 0x6C, 0x8C, 0xEB, 0x02, 0xF0, 0x00, 0x73, 0x01, 0x60, 0x05, 0x2B, -0x10, 0xF0, 0x24, 0x6B, 0xBB, 0xF7, 0x60, 0x9B, -0x04, 0x10, 0x10, 0xF0, 0x24, 0x6B, 0xBB, 0xF7, -0x64, 0x9B, 0x69, 0xE2, 0x60, 0xA2, 0x20, 0x6A, +0x10, 0xF0, 0x24, 0x6B, 0x9D, 0xF6, 0x7C, 0x9B, +0x04, 0x10, 0x10, 0xF0, 0x24, 0x6B, 0xBD, 0xF6, +0x60, 0x9B, 0x69, 0xE2, 0x60, 0xA2, 0x20, 0x6A, 0x6C, 0xEA, 0x4B, 0xEA, 0xC0, 0xF7, 0x42, 0x32, 0x01, 0x10, 0x01, 0x6A, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65, -0xFF, 0x63, 0x01, 0xD1, 0x00, 0xD0, 0x30, 0xF0, -0x20, 0x6B, 0xE8, 0xF2, 0x7C, 0xA3, 0xFF, 0x6A, -0x8C, 0xEA, 0x02, 0x73, 0x66, 0x61, 0x43, 0x2A, -0x10, 0xF0, 0x24, 0x6A, 0xBB, 0xF7, 0xE8, 0x9A, -0x30, 0xF0, 0x20, 0x6A, 0xCF, 0xF4, 0x00, 0x4A, -0x60, 0x9F, 0x65, 0xDA, 0x10, 0xF0, 0x24, 0x6B, -0xBB, 0xF7, 0xCC, 0x9B, 0x60, 0x9E, 0x62, 0xDA, -0x10, 0xF0, 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array_mp_8821c_fw_nic[] = { 0x42, 0xC0, 0x7F, 0x6A, 0xFF, 0x69, 0x6C, 0xEA, 0x2C, 0xEC, 0x2C, 0xEA, 0x04, 0xD4, 0x47, 0x22, 0x30, 0xF0, 0x21, 0x6B, 0x30, 0xF0, 0x20, 0x6A, -0x6E, 0xF5, 0x58, 0x9A, 0x90, 0xF0, 0x8B, 0xA3, +0x6E, 0xF5, 0x58, 0x9A, 0x90, 0xF2, 0x81, 0xA3, 0x40, 0xEA, 0x01, 0x72, 0x3C, 0x61, 0x04, 0x94, -0x00, 0x6D, 0x00, 0x18, 0xA3, 0xCC, 0x68, 0xF3, +0x00, 0x6D, 0x00, 0x18, 0x0B, 0xCE, 0x68, 0xF3, 0x7A, 0xA0, 0xC8, 0xF3, 0x54, 0xD8, 0x20, 0x6A, 0x6D, 0xEA, 0x68, 0xF3, 0x75, 0xA0, 0x68, 0xF3, 0x5A, 0xC0, 0x0F, 0x6A, 0x6C, 0xEA, 0x2C, 0xEA, @@ -17456,162 +20872,127 @@ u8 array_mp_8821c_fw_nic[] = { 0x01, 0x6A, 0x32, 0x31, 0x4E, 0xE9, 0x4C, 0xE9, 0x30, 0xF0, 0x20, 0x6A, 0xC8, 0xF4, 0x72, 0xA2, 0x01, 0x6A, 0x4C, 0xEB, 0x08, 0x2B, 0x30, 0xF0, -0x21, 0x6B, 0xB0, 0xF2, 0x68, 0xA3, 0x6C, 0xEA, +0x21, 0x6B, 0x30, 0xF5, 0x7C, 0xA3, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x10, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0xC8, 0xF4, 0x56, 0xA2, 0x02, 0x72, -0x06, 0x60, 0x30, 0xF0, 0x21, 0x6A, 0xD0, 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0xED, 0xFF, 0x6A, 0x90, 0x67, 0x4C, 0xED, 0x00, 0x18, -0x39, 0xF1, 0x04, 0x6C, 0x00, 0x18, 0x2A, 0xF3, +0xEF, 0xF2, 0x04, 0x6C, 0x00, 0x18, 0xE0, 0xF4, 0x30, 0xF0, 0x20, 0x6A, 0x6E, 0xF2, 0x58, 0x9A, 0x00, 0x6D, 0xFF, 0x6C, 0xC5, 0x67, 0x40, 0xEA, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, @@ -17619,43 +21000,43 @@ u8 array_mp_8821c_fw_nic[] = { 0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x20, 0x6B, 0x48, 0xF5, 0xA2, 0xA3, 0x04, 0x6B, 0xFF, 0x6A, 0xAC, 0xEB, 0x4C, 0xEB, 0x4C, 0xEC, 0x08, 0x2B, -0x03, 0x6D, 0x00, 0x18, 0x34, 0xD6, 0x01, 0x6C, -0x04, 0x6D, 0x00, 0x18, 0xE5, 0xCC, 0x22, 0x10, +0x03, 0x6D, 0x00, 0x18, 0x32, 0xD9, 0x01, 0x6C, +0x04, 0x6D, 0x00, 0x18, 0x4D, 0xCE, 0x22, 0x10, 0x00, 0x6D, 0x30, 0xF0, 0x20, 0x69, 0x00, 0x18, -0x34, 0xD6, 0xCF, 0xF4, 0x00, 0x49, 0x0C, 0x6D, -0x01, 0x6C, 0x00, 0x18, 0xE5, 0xCC, 0xE0, 0xF5, -0x0A, 0xA1, 0x90, 0x67, 0x00, 0x18, 0x46, 0xF1, +0x32, 0xD9, 0xEF, 0xF4, 0x00, 0x49, 0x0C, 0x6D, +0x01, 0x6C, 0x00, 0x18, 0x4D, 0xCE, 0x41, 0xF0, +0x1E, 0xA1, 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0x48, 0xE8, 0xF3, 0xC6, 0xA0, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF2, 0x50, 0x9A, 0xFF, 0x6C, @@ -17819,24 +21154,28 @@ u8 array_mp_8821c_fw_nic[] = { 0x68, 0xF3, 0x39, 0xC0, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, -0x08, 0x4B, 0xA9, 0xF0, 0xA8, 0xA3, 0x04, 0x67, -0x01, 0x6C, 0xFF, 0x6A, 0xAC, 0xEC, 0x4C, 0xEC, -0x4C, 0xE8, 0x2C, 0x2C, 0x68, 0xF3, 0xB4, 0xA3, -0x7F, 0x6C, 0xAC, 0xEC, 0x01, 0x74, 0x26, 0x61, -0x68, 0xF3, 0xB5, 0xA3, 0x10, 0x6C, 0x8B, 0xEC, -0xAC, 0xEC, 0x4C, 0xEC, 0x14, 0x24, 0x30, 0xF0, -0x20, 0x6A, 0x2E, 0xF4, 0x48, 0x9A, 0xD0, 0x67, -0x0C, 0x6C, 0x00, 0x6D, 0x40, 0xEA, 0x30, 0xF0, -0x20, 0x6A, 0x6E, 0xF2, 0x58, 0x9A, 0x00, 0x6D, -0xFF, 0x6C, 0xC5, 0x67, 0x40, 0xEA, 0x90, 0x67, -0x00, 0x18, 0x96, 0xD4, 0x0B, 0x10, 0x68, 0xF3, -0x5C, 0xA3, 0x08, 0x2A, 0x30, 0xF0, 0x20, 0x6A, -0x2E, 0xF4, 0x48, 0x9A, 0x04, 0x6C, 0x01, 0x6D, -0xD0, 0x67, 0x40, 0xEA, 0x05, 0x97, 0x04, 0x90, -0x03, 0x63, 0x00, 0xEF, 0xFC, 0x63, 0x07, 0x62, +0x08, 0x4B, 0x68, 0xF3, 0xB4, 0xA3, 0x04, 0x67, +0x7F, 0x6C, 0xFF, 0x6A, 0xAC, 0xEC, 0x4C, 0xEC, +0x01, 0x74, 0x4C, 0xE8, 0x1B, 0x61, 0x68, 0xF3, +0xB5, 0xA3, 0x10, 0x6C, 0x8B, 0xEC, 0xAC, 0xEC, +0x4C, 0xEC, 0x16, 0x24, 0x30, 0xF0, 0x20, 0x6A, +0x2E, 0xF4, 0x48, 0x9A, 0xD0, 0x67, 0x0C, 0x6C, +0x00, 0x6D, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A, +0x6E, 0xF2, 0x58, 0x9A, 0x00, 0x6D, 0xFF, 0x6C, +0xC5, 0x67, 0x40, 0xEA, 0x90, 0x67, 0x00, 0x18, +0x16, 0xD6, 0x0D, 0x10, 0x02, 0x74, 0x0B, 0x61, +0x68, 0xF3, 0x5C, 0xA3, 0x08, 0x2A, 0x30, 0xF0, +0x20, 0x6A, 0x2E, 0xF4, 0x48, 0x9A, 0x04, 0x6C, +0x01, 0x6D, 0xD0, 0x67, 0x40, 0xEA, 0x05, 0x97, +0x04, 0x90, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, +0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6B, +0x69, 0xF2, 0xB0, 0xA3, 0x01, 0x6B, 0xFF, 0x6A, +0xAC, 0xEB, 0x4C, 0xEB, 0x4C, 0xEC, 0x02, 0x2B, +0x00, 0x18, 0x31, 0xD6, 0x05, 0x97, 0x03, 0x63, +0x00, 0xEF, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0xFF, 0x69, 0x8C, 0xE9, 0x30, 0xF0, 0x20, 0x68, 0x91, 0x67, 0xC0, 0xF1, -0x08, 0x48, 0x00, 0x18, 0x96, 0xD4, 0x68, 0xF3, +0x08, 0x48, 0x00, 0x18, 0x16, 0xD6, 0x68, 0xF3, 0x5C, 0xA0, 0x0C, 0x72, 0x20, 0x60, 0x30, 0xF0, 0x20, 0x6A, 0x2E, 0xF4, 0x48, 0x9A, 0x0C, 0x6C, 0x00, 0x6D, 0xD1, 0x67, 0x40, 0xEA, 0x30, 0xF0, @@ -17847,444 +21186,606 @@ u8 array_mp_8821c_fw_nic[] = { 0x20, 0x6A, 0x2E, 0xF4, 0x50, 0x9A, 0x00, 0x6D, 0x08, 0x6E, 0xF1, 0x67, 0x40, 0xEA, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, -0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, -0x24, 0x67, 0x30, 0xF0, 0x20, 0x6C, 0xC0, 0xF1, +0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, +0x04, 0x67, 0x30, 0xF0, 0x20, 0x6C, 0xC0, 0xF1, 0x08, 0x4C, 0x68, 0xF3, 0xB9, 0xA4, 0x40, 0x6B, -0xFF, 0x6A, 0xAC, 0xEB, 0x4C, 0xEB, 0x4C, 0xE9, +0xFF, 0x6A, 0xAC, 0xEB, 0x4C, 0xEB, 0x4C, 0xE8, 0x09, 0x23, 0x68, 0xF3, 0x9A, 0xA4, 0x10, 0x6B, -0x8C, 0xEB, 0x4C, 0xEB, 0x03, 0x23, 0x91, 0x67, -0x00, 0x18, 0x6B, 0xEB, 0x30, 0xF0, 0x20, 0x68, -0xC0, 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0xF0, -0x24, 0x6A, 0x1B, 0xF7, 0x50, 0x9A, 0x49, 0xE1, +0x1D, 0xF6, 0x4C, 0x9A, 0x04, 0x10, 0x10, 0xF0, +0x24, 0x6A, 0x1D, 0xF6, 0x50, 0x9A, 0x49, 0xE1, 0x0B, 0x93, 0x40, 0x9A, 0x6C, 0xEA, 0x0C, 0x93, 0x6E, 0xEA, 0x04, 0x22, 0x40, 0xA8, 0x04, 0x93, 0x63, 0xEA, 0xDC, 0x61, 0x40, 0xA8, 0x04, 0x93, 0x63, 0xEA, 0x58, 0x67, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x00, 0x65, -0x10, 0xF0, 0x24, 0x6B, 0x5C, 0xF1, 0x60, 0x9B, +0x10, 0xF0, 0x24, 0x6B, 0x1E, 0xF0, 0x78, 0x9B, 0xFF, 0x6A, 0xCC, 0xEA, 0x6D, 0xEA, 0xE0, 0xF1, 0x1F, 0x6B, 0xAC, 0xEB, 0x10, 0xF0, 0x24, 0x6C, -0x5C, 0xF1, 0x84, 0x9C, 0x60, 0x33, 0x60, 0x33, +0x1E, 0xF0, 0x9C, 0x9C, 0x60, 0x33, 0x60, 0x33, 0x6D, 0xEA, 0x40, 0xDC, 0x10, 0xF0, 0x24, 0x6A, -0x5B, 0xF7, 0x5C, 0x9A, 0x6D, 0xEA, 0x40, 0xDC, +0x5D, 0xF6, 0x5C, 0x9A, 0x6D, 0xEA, 0x40, 0xDC, 0x20, 0xE8, 0x00, 0x65, 0xE0, 0xF1, 0x1F, 0x6A, -0x10, 0xF0, 0x24, 0x6B, 0x5B, 0xF7, 0x7C, 0x9B, +0x10, 0xF0, 0x24, 0x6B, 0x5D, 0xF6, 0x7C, 0x9B, 0xAC, 0xEA, 0x40, 0x32, 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-18330,191 +21831,287 @@ u8 array_mp_8821c_fw_nic[] = { 0x0F, 0x91, 0x04, 0xD2, 0x04, 0x93, 0xFF, 0x6A, 0x4C, 0xE8, 0x4C, 0xEB, 0x90, 0x67, 0x0B, 0xD5, 0x0C, 0xD6, 0x0D, 0xD7, 0x04, 0xD3, 0x4C, 0xE9, -0x00, 0x18, 0x93, 0xD8, 0x80, 0xF0, 0x07, 0x22, +0x00, 0x18, 0x5F, 0xDB, 0x80, 0xF0, 0x07, 0x22, 0x06, 0x58, 0x80, 0xF0, 0x04, 0x60, 0x10, 0xF0, -0x24, 0x6A, 0x08, 0x30, 0x5B, 0xF2, 0x18, 0x4A, +0x24, 0x6A, 0x08, 0x30, 0xDD, 0xF0, 0x08, 0x4A, 0x09, 0xE2, 0x40, 0x9A, 0x00, 0xEA, 0x02, 0xF2, 0x10, 0x6A, 0x0E, 0x10, 0x02, 0xF2, 0x00, 0x6A, 0x0B, 0x10, 0x22, 0xF2, 0x00, 0x6A, 0x08, 0x10, 0x22, 0xF2, 0x10, 0x6A, 0x05, 0x10, 0x42, 0xF2, 0x00, 0x6A, 0x02, 0x10, 0x42, 0xF2, 0x10, 0x6A, -0x10, 0xF0, 0x24, 0x6B, 0x0D, 0x94, 0x5C, 0xF1, -0x70, 0x9B, 0x8C, 0xEB, 0x10, 0xF0, 0x24, 0x6C, -0x1B, 0xF7, 0x98, 0x9C, 0x8D, 0xEB, 0x06, 0x21, -0x10, 0xF0, 0x24, 0x6C, 0x1C, 0xF0, 0x84, 0x9C, +0x10, 0xF0, 0x24, 0x6B, 0x0D, 0x94, 0x3E, 0xF0, +0x68, 0x9B, 0x8C, 0xEB, 0x10, 0xF0, 0x24, 0x6C, +0x1D, 0xF6, 0x98, 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0x80, 0xF4, 0x44, 0xA2, 0x76, 0xC4, +0x57, 0xC4, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF2, +0x58, 0x9A, 0x04, 0x04, 0x40, 0xEA, 0x09, 0x97, +0x05, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF3, 0x48, 0x9A, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, @@ -18549,344 +22146,371 @@ u8 array_mp_8821c_fw_nic[] = { 0xC4, 0x67, 0x01, 0x6D, 0x28, 0x6C, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, 0x61, 0xA4, 0xBD, 0x67, -0x40, 0xA4, 0x70, 0xC5, 0x62, 0xA4, 0x08, 0x5A, +0x40, 0xA4, 0x70, 0xC5, 0x62, 0xA4, 0x0C, 0x5A, 0x71, 0xC5, 0x63, 0xA4, 0x72, 0xC5, 0x64, 0xA4, 0x73, 0xC5, 0x65, 0xA4, 0x74, 0xC5, 0x66, 0xA4, -0xFF, 0x6C, 0x75, 0xC5, 0x47, 0x60, 0x10, 0xF0, -0x24, 0x6B, 0x48, 0x32, 0x3B, 0xF5, 0x14, 0x4B, -0x4D, 0xE3, 0x40, 0x9B, 0x00, 0xEA, 0x2A, 0x6C, -0x08, 0x10, 0x29, 0x6C, 0x02, 0x6D, 0x3B, 0x10, -0x31, 0x6C, 0x38, 0x10, 0x32, 0x6C, 0x36, 0x10, -0x33, 0x6C, 0x06, 0x6D, 0x34, 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0x9A, 0x02, 0x6D, 0xAD, 0xEC, 0x80, 0xF0, @@ -18982,717 +22594,714 @@ u8 array_mp_8821c_fw_nic[] = { 0x40, 0xF0, 0x80, 0xAA, 0x00, 0xF7, 0x00, 0x74, 0x05, 0x60, 0x40, 0xF0, 0x01, 0xA2, 0x00, 0x94, 0x8A, 0xE8, 0x0A, 0x61, 0x10, 0xF0, 0x24, 0x6A, -0x9B, 0xF7, 0x6C, 0x9A, 0xFF, 0x6C, 0x01, 0x4C, +0x9D, 0xF6, 0x68, 0x9A, 0xFF, 0x6C, 0x01, 0x4C, 0x40, 0x9B, 0x8D, 0xEA, 0x40, 0xDB, 0xCC, 0x10, -0x30, 0xF0, 0x21, 0x6D, 0xF0, 0xF3, 0x92, 0xA5, +0x30, 0xF0, 0x21, 0x6D, 0x90, 0xF6, 0x86, 0xA5, 0xC3, 0x67, 0xC7, 0xEC, 0x86, 0x67, 0x01, 0x6E, 0xCC, 0xEC, 0xA0, 0xF0, 0x08, 0x24, 0x0C, 0x35, 0x04, 0x4D, 0xB5, 0xE2, 0x00, 0x6A, 0x30, 0xF0, -0x21, 0x6E, 0xF0, 0xF3, 0xF2, 0xA6, 0xFF, 0x6C, +0x21, 0x6E, 0x90, 0xF6, 0xE6, 0xA6, 0xFF, 0x6C, 0x1F, 0xF7, 0x00, 0x69, 0x8C, 0xEF, 0x74, 0x4F, 0xE8, 0x37, 0xFD, 0xE2, 0x2C, 0xEF, 0x02, 0xF0, -0x00, 0x77, 0x08, 0x60, 0xF0, 0xF3, 0xF2, 0xA6, +0x00, 0x77, 0x08, 0x60, 0x90, 0xF6, 0xE6, 0xA6, 0x8C, 0xEF, 0x74, 0x4F, 0xE8, 0x37, 0xFD, 0xE2, 0x2C, 0xEF, 0x0F, 0x2F, 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0x9C, 0x34, 0x4C, 0xEF, 0x8D, 0xEB, 0xED, 0xEB, @@ -19702,16 +23311,20 @@ u8 array_mp_8821c_fw_nic[] = { 0x20, 0xE8, 0x00, 0x65, 0x20, 0xE8, 0x00, 0x65, 0x20, 0xE8, 0x00, 0x65, 0x20, 0xE8, 0x00, 0x65, 0x20, 0xE8, 0x00, 0x65, 0x20, 0xE8, 0x00, 0x65, +0x20, 0xE8, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6A, +0xC0, 0xF1, 0x08, 0x4A, 0x68, 0xF3, 0x9D, 0xA2, +0x04, 0x6B, 0x8D, 0xEB, 0x68, 0xF3, 0x7D, 0xC2, +0x20, 0xE8, 0x00, 0x65, 0x20, 0xE8, 0x00, 0x65, 0x20, 0xE8, 0x00, 0x65, 0x10, 0xF0, 0x24, 0x6A, -0x7C, 0xF3, 0x48, 0x9A, 0x40, 0xA2, 0x10, 0xF0, -0x24, 0x6A, 0x7C, 0xF3, 0x4C, 0x9A, 0x40, 0xA2, -0x10, 0xF0, 0x24, 0x6A, 0x7C, 0xF3, 0x50, 0x9A, -0x40, 0xA2, 0x10, 0xF0, 0x24, 0x6A, 0xDC, 0xF2, -0x50, 0x9A, 0x40, 0xA2, 0x10, 0xF0, 0x24, 0x6A, -0x7C, 0xF3, 0x54, 0x9A, 0x40, 0xA2, 0x10, 0xF0, -0x24, 0x6A, 0x7C, 0xF3, 0x58, 0x9A, 0x40, 0xA2, -0x10, 0xF0, 0x24, 0x6A, 0x7C, 0xF3, 0x5C, 0x9A, -0x40, 0xA2, 0x10, 0xF0, 0x24, 0x6A, 0x5B, 0xF7, +0x9E, 0xF3, 0x48, 0x9A, 0x40, 0xA2, 0x10, 0xF0, +0x24, 0x6A, 0x9E, 0xF3, 0x4C, 0x9A, 0x40, 0xA2, +0x10, 0xF0, 0x24, 0x6A, 0x9E, 0xF3, 0x50, 0x9A, +0x40, 0xA2, 0x10, 0xF0, 0x24, 0x6A, 0xFE, 0xF2, +0x48, 0x9A, 0x40, 0xA2, 0x10, 0xF0, 0x24, 0x6A, +0x9E, 0xF3, 0x54, 0x9A, 0x40, 0xA2, 0x10, 0xF0, +0x24, 0x6A, 0x9E, 0xF3, 0x58, 0x9A, 0x40, 0xA2, +0x10, 0xF0, 0x24, 0x6A, 0x9E, 0xF3, 0x5C, 0x9A, +0x40, 0xA2, 0x10, 0xF0, 0x24, 0x6A, 0x5D, 0xF6, 0x54, 0x9A, 0x40, 0xA2, 0x20, 0xE8, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x08, 0xF3, 0x8A, 0xA2, 0x01, 0x6B, 0x8C, 0xEB, @@ -19726,17 +23339,17 @@ u8 array_mp_8821c_fw_nic[] = { 0x05, 0x23, 0x00, 0x6B, 0x08, 0xF3, 0x6B, 0xC2, 0x08, 0xF3, 0x6C, 0xC2, 0x20, 0xE8, 0x00, 0x65, 0x20, 0xE8, 0x00, 0x65, 0x10, 0xF0, 0x24, 0x6A, -0x9B, 0xF7, 0x6C, 0x9A, 0x10, 0xF0, 0x24, 0x6C, -0x7C, 0xF0, 0x98, 0x9C, 0x40, 0x9B, 0x8D, 0xEA, +0x9D, 0xF6, 0x68, 0x9A, 0x10, 0xF0, 0x24, 0x6C, +0x5D, 0xF7, 0x80, 0x9C, 0x40, 0x9B, 0x8D, 0xEA, 0x40, 0xDB, 0x20, 0xE8, 0x20, 0xE8, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x21, 0x6B, -0x30, 0xF0, 0x20, 0x6A, 0x90, 0xF0, 0x8B, 0xA3, +0x30, 0xF0, 0x20, 0x6A, 0x90, 0xF2, 0x81, 0xA3, 0x6E, 0xF5, 0x58, 0x9A, 0x40, 0xEA, 0x01, 0x6B, 0x6E, 0xEA, 0x1E, 0x2A, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x68, 0xF3, 0xB4, 0xA3, 0x7F, 0x6C, 0xAC, 0xEC, 0x15, 0x24, 0x10, 0xF0, -0x24, 0x6C, 0x9C, 0xF0, 0x94, 0x9C, 0x00, 0x6D, -0x40, 0xC4, 0x10, 0xF0, 0x24, 0x6A, 0x9C, 0xF0, +0x24, 0x6C, 0x9D, 0xF7, 0x9C, 0x9C, 0x00, 0x6D, +0x40, 0xC4, 0x10, 0xF0, 0x24, 0x6A, 0x3D, 0xF7, 0x58, 0x9A, 0x02, 0x6C, 0x80, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF2, 0x50, 0x9A, 0xE8, 0xF3, 0xC5, 0xA3, 0xFF, 0x6C, 0x55, 0x4C, 0x40, 0xEA, @@ -19749,46 +23362,51 @@ u8 array_mp_8821c_fw_nic[] = { 0xCC, 0xEB, 0x4C, 0xEB, 0x4C, 0xEC, 0x0D, 0x2B, 0x08, 0xF3, 0xAA, 0xA5, 0x01, 0x6B, 0x6C, 0xED, 0x4C, 0xED, 0x07, 0x2D, 0x30, 0xF0, 0x21, 0x6D, -0xB0, 0xF2, 0xA8, 0xA5, 0xAC, 0xEB, 0x4C, 0xEB, +0x30, 0xF5, 0xBC, 0xA5, 0xAC, 0xEB, 0x4C, 0xEB, 0x18, 0x23, 0x30, 0xF0, 0x20, 0x6A, 0xC8, 0xF4, 0x72, 0xA2, 0x01, 0x6A, 0x4C, 0xEB, 0x08, 0x2B, -0x30, 0xF0, 0x21, 0x6B, 0xB0, 0xF2, 0x68, 0xA3, +0x30, 0xF0, 0x21, 0x6B, 0x30, 0xF5, 0x7C, 0xA3, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x07, 0x22, -0x00, 0x18, 0x62, 0xF1, 0x01, 0x72, 0x05, 0x61, -0x00, 0x18, 0x37, 0xF3, 0x02, 0x10, 0x00, 0x18, -0xB1, 0xD4, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, +0x00, 0x18, 0x18, 0xF3, 0x01, 0x72, 0x05, 0x61, +0x00, 0x18, 0xED, 0xF4, 0x02, 0x10, 0x00, 0x18, +0x50, 0xD6, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x21, 0x6B, 0x30, 0xF0, 0x20, 0x6A, -0x24, 0x67, 0x6E, 0xF5, 0x58, 0x9A, 0x90, 0xF0, -0x8B, 0xA3, 0xFF, 0x68, 0x0C, 0xE9, 0x40, 0xEA, +0x24, 0x67, 0x6E, 0xF5, 0x58, 0x9A, 0x90, 0xF2, +0x81, 0xA3, 0xFF, 0x68, 0x0C, 0xE9, 0x40, 0xEA, 0x01, 0x72, 0x19, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x68, 0xF3, 0x94, 0xA2, 0x7F, 0x6B, 0x8C, 0xEB, 0x0C, 0xEB, 0x0F, 0x23, 0x68, 0xF3, 0x9D, 0xA2, 0x02, 0x6B, 0x6B, 0xEB, 0x8C, 0xEB, 0x68, 0xF3, 0x7D, 0xC2, 0x68, 0xF3, 0x5D, 0xA2, 0x07, 0x6B, 0x6C, 0xEA, 0x03, 0x2A, -0x91, 0x67, 0x00, 0x18, 0xEE, 0xD1, 0x07, 0x97, +0x91, 0x67, 0x00, 0x18, 0x10, 0xD4, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x21, 0x6B, 0x30, 0xF0, 0x20, 0x6A, -0x24, 0x67, 0x6E, 0xF5, 0x58, 0x9A, 0x90, 0xF0, -0x8B, 0xA3, 0xFF, 0x68, 0x0C, 0xE9, 0x40, 0xEA, +0x24, 0x67, 0x6E, 0xF5, 0x58, 0x9A, 0x90, 0xF2, +0x81, 0xA3, 0xFF, 0x68, 0x0C, 0xE9, 0x40, 0xEA, 0x01, 0x6B, 0x6E, 0xEA, 0x29, 0x2A, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x68, 0xF3, 0xB4, 0xA3, 0x7F, 0x6C, 0xAC, 0xEC, 0x0C, 0xEC, -0x1F, 0x24, 0x10, 0xF0, 0x24, 0x6C, 0x9C, 0xF0, -0x94, 0x9C, 0x40, 0xC4, 0x10, 0xF0, 0x24, 0x6A, -0x9C, 0xF0, 0x58, 0x9A, 0x02, 0x6C, 0x80, 0xC2, +0x1F, 0x24, 0x10, 0xF0, 0x24, 0x6C, 0x9D, 0xF7, +0x9C, 0x9C, 0x40, 0xC4, 0x10, 0xF0, 0x24, 0x6A, +0x3D, 0xF7, 0x58, 0x9A, 0x02, 0x6C, 0x80, 0xC2, 0x68, 0xF3, 0x99, 0xA3, 0x03, 0x6A, 0x4B, 0xEA, 0x4C, 0xEC, 0x68, 0xF3, 0x99, 0xC3, 0x68, 0xF3, 0x9D, 0xA3, 0x8C, 0xEA, 0x68, 0xF3, 0x5D, 0xC3, 0x68, 0xF3, 0x5D, 0xA3, 0x07, 0x6B, 0x6C, 0xEA, -0x03, 0x2A, 0x91, 0x67, 0x00, 0x18, 0xEE, 0xD1, +0x03, 0x2A, 0x91, 0x67, 0x00, 0x18, 0x10, 0xD4, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, -0x00, 0xEF, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, +0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, +0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, +0x68, 0xF3, 0xBD, 0xA2, 0x05, 0x6B, 0x6B, 0xEB, +0xAC, 0xEB, 0x68, 0xF3, 0x7D, 0xC2, 0xFF, 0x6A, +0x4C, 0xEC, 0x00, 0x18, 0x10, 0xD4, 0x05, 0x97, +0x03, 0x63, 0x00, 0xEF, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x21, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x24, 0x67, 0x6E, 0xF5, -0x58, 0x9A, 0x90, 0xF0, 0x8B, 0xA3, 0xFF, 0x68, +0x58, 0x9A, 0x90, 0xF2, 0x81, 0xA3, 0xFF, 0x68, 0x0C, 0xE9, 0x40, 0xEA, 0x01, 0x72, 0x1B, 0x61, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x68, 0xF3, 0x94, 0xA3, 0x7F, 0x6A, 0x8C, 0xEA, @@ -19796,41 +23414,33 @@ u8 array_mp_8821c_fw_nic[] = { 0x10, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0x0C, 0xEA, 0x20, 0x72, 0x06, 0x60, 0x30, 0xF0, 0x20, 0x6A, 0x2E, 0xF4, 0x54, 0x9A, 0x40, 0xEA, 0x03, 0x10, -0x91, 0x67, 0x00, 0x18, 0xD1, 0xD4, 0x07, 0x97, -0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, -0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, -0xFF, 0x68, 0x24, 0x67, 0x0C, 0xE9, 0x91, 0x67, -0x00, 0x18, 0x9D, 0xCE, 0x70, 0x22, 0x30, 0xF0, -0x20, 0x6A, 0xC8, 0xF4, 0x72, 0xA2, 0x01, 0x6A, -0x4C, 0xEB, 0x0C, 0xEB, 0x07, 0x2B, 0x30, 0xF0, -0x21, 0x6B, 0xB0, 0xF2, 0x68, 0xA3, 0x6C, 0xEA, -0x0C, 0xEA, 0x0C, 0x22, 0x30, 0xF0, 0x20, 0x6A, -0xC8, 0xF4, 0x56, 0xA2, 0x02, 0x72, 0x5B, 0x60, -0x30, 0xF0, 0x21, 0x6A, 0xD0, 0xF2, 0x43, 0xA2, -0x02, 0x72, 0x55, 0x60, 0x30, 0xF0, 0x20, 0x6A, -0xC0, 0xF1, 0x08, 0x4A, 0x68, 0xF3, 0xB4, 0xA2, -0x7F, 0x6B, 0xFF, 0x6C, 0xAC, 0xEB, 0x0D, 0x2B, -0x08, 0xF3, 0x6A, 0xA2, 0x01, 0x6A, 0x4C, 0xEB, -0x8C, 0xEB, 0x07, 0x2B, 0x30, 0xF0, 0x21, 0x6B, -0xB0, 0xF2, 0x68, 0xA3, 0x6C, 0xEA, 0x8C, 0xEA, -0x09, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0x48, 0xF5, -0x44, 0xA2, 0x02, 0x72, 0x38, 0x60, 0x91, 0x67, -0x00, 0x18, 0x89, 0xD5, 0x30, 0xF0, 0x20, 0x6B, -0xCF, 0xF4, 0x00, 0x4B, 0xC0, 0xF3, 0x92, 0xA3, -0x92, 0x32, 0x4E, 0xE9, 0x2C, 0x29, 0x01, 0x6A, -0x4C, 0xEC, 0xFF, 0x6D, 0xAC, 0xEC, 0x27, 0x24, -0xC0, 0xF3, 0x73, 0xA3, 0x08, 0x5B, 0x07, 0x60, -0x10, 0xF0, 0x24, 0x6C, 0xBB, 0xF7, 0x94, 0x9C, -0x08, 0x4B, 0xA0, 0x9C, 0x05, 0x10, 0x10, 0xF0, -0x24, 0x6C, 0xBB, 0xF7, 0x98, 0x9C, 0xA0, 0x9C, -0x44, 0xEB, 0xAE, 0xEA, 0x30, 0xF0, 0x20, 0x68, -0xCF, 0xF4, 0x00, 0x48, 0x40, 0xDC, 0xC0, 0xF3, -0x92, 0xA0, 0x00, 0x6D, 0x92, 0x34, 0x00, 0x18, -0xA3, 0xCC, 0xC0, 0xF3, 0x92, 0xA0, 0xC0, 0xF3, -0x5C, 0xD8, 0x01, 0x6D, 0x92, 0x34, 0x00, 0x18, -0xA3, 0xCC, 0xE0, 0xF3, 0x40, 0xD8, 0x07, 0x97, +0x91, 0x67, 0x00, 0x18, 0x59, 0xD6, 0x30, 0xF0, +0x21, 0x6A, 0x50, 0xF1, 0x7D, 0xA2, 0x07, 0x6A, +0x6C, 0xEA, 0x4E, 0xE9, 0x02, 0x29, 0x80, 0x18, +0xEB, 0x0A, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, +0x04, 0x63, 0x00, 0xEF, 0xFC, 0x63, 0x07, 0x62, +0x06, 0xD1, 0x05, 0xD0, 0xFF, 0x69, 0x04, 0x67, +0x2C, 0xE8, 0x90, 0x67, 0x00, 0x18, 0xF1, 0xCF, +0x46, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0xC8, 0xF4, +0x72, 0xA2, 0x01, 0x6A, 0x4C, 0xEB, 0x2C, 0xEB, +0x07, 0x2B, 0x30, 0xF0, 0x21, 0x6B, 0x30, 0xF5, +0x7C, 0xA3, 0x6C, 0xEA, 0x2C, 0xEA, 0x0C, 0x22, +0x30, 0xF0, 0x20, 0x6A, 0xC8, 0xF4, 0x56, 0xA2, +0x02, 0x72, 0x31, 0x60, 0x30, 0xF0, 0x21, 0x6A, +0x50, 0xF5, 0x57, 0xA2, 0x02, 0x72, 0x2B, 0x60, +0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, +0x68, 0xF3, 0xB4, 0xA2, 0x7F, 0x6B, 0xFF, 0x6C, +0xAC, 0xEB, 0x0D, 0x2B, 0x08, 0xF3, 0x6A, 0xA2, +0x01, 0x6A, 0x4C, 0xEB, 0x8C, 0xEB, 0x07, 0x2B, +0x30, 0xF0, 0x21, 0x6B, 0x30, 0xF5, 0x7C, 0xA3, +0x6C, 0xEA, 0x8C, 0xEA, 0x09, 0x22, 0x30, 0xF0, +0x20, 0x6A, 0x48, 0xF5, 0x44, 0xA2, 0x02, 0x72, +0x0E, 0x60, 0x90, 0x67, 0x00, 0x18, 0x28, 0xD7, +0x30, 0xF0, 0x21, 0x6A, 0x50, 0xF1, 0x7D, 0xA2, +0x07, 0x6A, 0x6C, 0xEA, 0x0E, 0xEA, 0x03, 0x2A, +0x90, 0x67, 0x80, 0x18, 0x0B, 0x0B, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, -0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x4E, 0xDD, +0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0xF1, 0xE0, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, 0xFF, 0x6A, 0x30, 0xF0, 0x20, 0x68, 0x4C, 0xEC, @@ -19838,10 +23448,10 @@ u8 array_mp_8821c_fw_nic[] = { 0x9A, 0xA0, 0x01, 0x69, 0x64, 0x67, 0x2C, 0xEB, 0x4C, 0xEB, 0x16, 0x23, 0xFF, 0xF6, 0x1F, 0x4A, 0x8C, 0xEA, 0x04, 0x94, 0x00, 0x6D, 0x68, 0xF3, -0x5A, 0xC0, 0x00, 0x18, 0xCE, 0xE1, 0x4C, 0xE9, +0x5A, 0xC0, 0x00, 0x18, 0x5F, 0xE5, 0x4C, 0xE9, 0x68, 0xF3, 0x5A, 0xA0, 0x05, 0x6B, 0x6B, 0xEB, 0x04, 0x94, 0x28, 0x31, 0x4C, 0xEB, 0x2D, 0xEB, -0x68, 0xF3, 0x7A, 0xC0, 0x00, 0x18, 0xEE, 0xD1, +0x68, 0xF3, 0x7A, 0xC0, 0x00, 0x18, 0x10, 0xD4, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x20, 0x68, @@ -19849,31 +23459,48 @@ u8 array_mp_8821c_fw_nic[] = { 0xFF, 0x69, 0x02, 0x6A, 0x8C, 0xE9, 0x6C, 0xEA, 0xFF, 0x6C, 0x8C, 0xEA, 0x1E, 0x22, 0x03, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0x91, 0x67, 0x01, 0x6D, -0x68, 0xF3, 0x5A, 0xC0, 0x00, 0x18, 0xCE, 0xE1, +0x68, 0xF3, 0x5A, 0xC0, 0x00, 0x18, 0x5F, 0xE5, 0x68, 0xF3, 0x9A, 0xA0, 0x01, 0x6B, 0x4C, 0xEB, 0x09, 0x6A, 0x4B, 0xEA, 0x6C, 0x33, 0x8C, 0xEA, 0x6D, 0xEA, 0x68, 0xF3, 0x74, 0xA0, 0x68, 0xF3, 0x5A, 0xC0, 0x7F, 0x6A, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x03, 0x22, 0x91, 0x67, 0x00, 0x18, -0xEE, 0xD1, 0x30, 0xF0, 0x20, 0x68, 0xC0, 0xF1, +0x10, 0xD4, 0x30, 0xF0, 0x20, 0x68, 0xC0, 0xF1, 0x08, 0x48, 0xA9, 0xF0, 0x68, 0xA0, 0x11, 0x6A, -0x6C, 0xEA, 0x11, 0x72, 0x1B, 0x61, 0xC9, 0xF0, +0x6C, 0xEA, 0x11, 0x72, 0x29, 0x61, 0xC9, 0xF0, 0x64, 0xA0, 0x02, 0x6A, 0xFF, 0x6C, 0x6C, 0xEA, -0x8C, 0xEA, 0x14, 0x22, 0x03, 0x6A, 0x4B, 0xEA, +0x8C, 0xEA, 0x22, 0x22, 0x03, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 0x91, 0x67, 0x01, 0x6D, 0xC9, 0xF0, -0x44, 0xC0, 0x00, 0x18, 0xCE, 0xE1, 0xC9, 0xF0, +0x44, 0xC0, 0x00, 0x18, 0x5F, 0xE5, 0xC9, 0xF0, 0x84, 0xA0, 0x01, 0x6B, 0x4C, 0xEB, 0x05, 0x6A, 0x4B, 0xEA, 0x68, 0x33, 0x8C, 0xEA, 0x6D, 0xEA, -0xC9, 0xF0, 0x44, 0xC0, 0x91, 0x67, 0x00, 0x18, -0x74, 0xED, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, -0x04, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, +0x04, 0x6B, 0x4C, 0xEB, 0xC9, 0xF0, 0x44, 0xC0, +0xFF, 0x6A, 0x4C, 0xEB, 0x09, 0x23, 0x30, 0xF0, +0x20, 0x6A, 0xEF, 0xF4, 0x00, 0x4A, 0x80, 0xF4, +0x66, 0xA2, 0x01, 0x4B, 0x80, 0xF4, 0x66, 0xC2, +0x91, 0x67, 0x80, 0x18, 0x8F, 0x08, 0x07, 0x97, +0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, +0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x30, 0xF0, +0x20, 0x68, 0xC0, 0xF1, 0x08, 0x48, 0x08, 0xF3, +0x6A, 0xA0, 0x01, 0x6A, 0x6C, 0xEA, 0x25, 0x22, +0x08, 0xF3, 0x4D, 0xA0, 0x04, 0x72, 0x21, 0x60, +0x08, 0xF3, 0x4E, 0xA0, 0x02, 0x72, 0x1D, 0x60, +0x02, 0x6A, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, +0x03, 0x22, 0x00, 0x18, 0x54, 0xC5, 0x15, 0x10, +0x00, 0x18, 0x0C, 0xF5, 0x08, 0xF3, 0x4E, 0xA0, +0x08, 0x72, 0x06, 0x61, 0x30, 0xF0, 0x20, 0x6A, +0x2E, 0xF4, 0x48, 0x9A, 0x0C, 0x6C, 0x06, 0x10, +0x08, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0x2E, 0xF4, +0x48, 0x9A, 0x04, 0x6C, 0x00, 0x6D, 0xC5, 0x67, +0x40, 0xEA, 0x05, 0x97, 0x04, 0x90, 0x03, 0x63, +0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x30, 0xF0, 0x20, 0x68, 0xC0, 0xF1, 0x08, 0x48, 0x08, 0xF3, 0x6A, 0xA0, 0x01, 0x6A, 0x6C, 0xEA, 0x25, 0x22, 0x08, 0xF3, 0x4D, 0xA0, 0x04, 0x72, 0x21, 0x60, 0x08, 0xF3, 0x4E, 0xA0, 0x02, 0x72, 0x1D, 0x60, 0x02, 0x6A, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x03, 0x22, 0x00, 0x18, -0x67, 0xC4, 0x15, 0x10, 0x00, 0x18, 0x56, 0xF3, +0x54, 0xC5, 0x15, 0x10, 0x00, 0x18, 0x0C, 0xF5, 0x08, 0xF3, 0x4E, 0xA0, 0x08, 0x72, 0x06, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x2E, 0xF4, 0x48, 0x9A, 0x0C, 0x6C, 0x06, 0x10, 0x08, 0x2A, 0x30, 0xF0, @@ -19886,8 +23513,8 @@ u8 array_mp_8821c_fw_nic[] = { 0x08, 0xF3, 0x4D, 0xA0, 0x04, 0x72, 0x21, 0x60, 0x08, 0xF3, 0x4E, 0xA0, 0x02, 0x72, 0x1D, 0x60, 0x02, 0x6A, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, -0x03, 0x22, 0x00, 0x18, 0x67, 0xC4, 0x15, 0x10, -0x00, 0x18, 0x56, 0xF3, 0x08, 0xF3, 0x4E, 0xA0, +0x03, 0x22, 0x00, 0x18, 0x54, 0xC5, 0x15, 0x10, +0x00, 0x18, 0x0C, 0xF5, 0x08, 0xF3, 0x4E, 0xA0, 0x08, 0x72, 0x06, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x2E, 0xF4, 0x48, 0x9A, 0x0C, 0x6C, 0x06, 0x10, 0x08, 0x2A, 0x30, 0xF0, 0x20, 0x6A, 0x2E, 0xF4, @@ -19896,90 +23523,76 @@ u8 array_mp_8821c_fw_nic[] = { 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x30, 0xF0, 0x20, 0x68, 0xC0, 0xF1, 0x08, 0x48, 0x08, 0xF3, 0x6A, 0xA0, 0x01, 0x6A, -0x6C, 0xEA, 0x25, 0x22, 0x08, 0xF3, 0x4D, 0xA0, -0x04, 0x72, 0x21, 0x60, 0x08, 0xF3, 0x4E, 0xA0, -0x02, 0x72, 0x1D, 0x60, 0x02, 0x6A, 0x6C, 0xEA, +0x6C, 0xEA, 0x2F, 0x22, 0x08, 0xF3, 0x4D, 0xA0, +0x04, 0x72, 0x2B, 0x60, 0x08, 0xF3, 0x4E, 0xA0, +0x02, 0x72, 0x27, 0x60, 0x02, 0x6A, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x03, 0x22, 0x00, 0x18, -0x67, 0xC4, 0x15, 0x10, 0x00, 0x18, 0x56, 0xF3, -0x08, 0xF3, 0x4E, 0xA0, 0x08, 0x72, 0x06, 0x61, +0x54, 0xC5, 0x1F, 0x10, 0x30, 0xF0, 0x20, 0x6A, +0x6E, 0xF2, 0x58, 0x9A, 0xFF, 0x6C, 0xA4, 0x67, +0xC4, 0x67, 0x40, 0xEA, 0x00, 0x18, 0x9D, 0xC4, +0x08, 0xF3, 0x4E, 0xA0, 0x0C, 0x72, 0x07, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x2E, 0xF4, 0x48, 0x9A, -0x0C, 0x6C, 0x06, 0x10, 0x08, 0x2A, 0x30, 0xF0, -0x20, 0x6A, 0x2E, 0xF4, 0x48, 0x9A, 0x04, 0x6C, -0x00, 0x6D, 0xC5, 0x67, 0x40, 0xEA, 0x05, 0x97, -0x04, 0x90, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, -0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x30, 0xF0, -0x20, 0x68, 0xC0, 0xF1, 0x08, 0x48, 0x08, 0xF3, -0x6A, 0xA0, 0x01, 0x6A, 0x6C, 0xEA, 0x2F, 0x22, -0x08, 0xF3, 0x4D, 0xA0, 0x04, 0x72, 0x2B, 0x60, -0x08, 0xF3, 0x4E, 0xA0, 0x02, 0x72, 0x27, 0x60, -0x02, 0x6A, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, -0x03, 0x22, 0x00, 0x18, 0x67, 0xC4, 0x1F, 0x10, -0x30, 0xF0, 0x20, 0x6A, 0x6E, 0xF2, 0x58, 0x9A, -0xFF, 0x6C, 0xA4, 0x67, 0xC4, 0x67, 0x40, 0xEA, -0x00, 0x18, 0xD8, 0xC3, 0x08, 0xF3, 0x4E, 0xA0, -0x0C, 0x72, 0x07, 0x61, 0x30, 0xF0, 0x20, 0x6A, -0x2E, 0xF4, 0x48, 0x9A, 0x08, 0x6C, 0x00, 0x6D, -0x08, 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u8 array_mp_8821c_fw_nic[] = { 0x30, 0xF0, 0x20, 0x68, 0xC0, 0xF1, 0x08, 0x48, 0x68, 0xF3, 0x74, 0xA0, 0x7F, 0x6A, 0xFF, 0x69, 0x6C, 0xEA, 0x1E, 0x22, 0x68, 0xF3, 0x97, 0xA0, -0x96, 0x34, 0x2C, 0xEC, 0x00, 0x18, 0xBE, 0xE7, +0x96, 0x34, 0x2C, 0xEC, 0x00, 0x18, 0x36, 0xED, 0x02, 0x6B, 0x4C, 0xEB, 0x2C, 0xEB, 0x07, 0x23, 0x68, 0xF3, 0x97, 0xA0, 0x96, 0x34, 0x2C, 0xEC, -0x00, 0x18, 0x96, 0xD4, 0x0D, 0x10, 0x68, 0xF3, +0x00, 0x18, 0x16, 0xD6, 0x0D, 0x10, 0x68, 0xF3, 0x97, 0xA0, 0x68, 0xF3, 0x79, 0xA0, 0x05, 0x6A, 0x4B, 0xEA, 0x96, 0x34, 0x6C, 0xEA, 0x2C, 0xEC, -0x68, 0xF3, 0x59, 0xC0, 0x00, 0x18, 0xEE, 0xD1, +0x68, 0xF3, 0x59, 0xC0, 0x00, 0x18, 0x10, 0xD4, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x68, 0xF3, 0x94, 0xA2, 0x7F, 0x6B, 0x8C, 0xEB, 0x07, 0x23, 0x68, 0xF3, 0x97, 0xA2, 0xFF, 0x6A, -0x96, 0x34, 0x4C, 0xEC, 0x00, 0x18, 0xEC, 0xD4, +0x96, 0x34, 0x4C, 0xEC, 0x00, 0x18, 0x74, 0xD6, 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0x00, 0x4A, 0xE0, 0xF5, 0x88, 0xA2, +0xEF, 0xF4, 0x00, 0x4A, 0x41, 0xF0, 0x9C, 0xA2, 0x02, 0x6B, 0x8C, 0xEB, 0x03, 0x23, 0x03, 0x6B, -0x00, 0xF6, 0x62, 0xC2, 0x05, 0x97, 0x03, 0x63, +0x61, 0xF0, 0x76, 0xC2, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x08, 0xF3, 0x8A, 0xA2, 0x02, 0x6B, 0x8C, 0xEB, 0x03, 0x23, 0x01, 0x6B, 0x08, 0xF3, 0x6D, 0xC2, 0x30, 0xF0, 0x20, 0x6A, -0xCF, 0xF4, 0x00, 0x4A, 0xE0, 0xF5, 0x88, 0xA2, +0xEF, 0xF4, 0x00, 0x4A, 0x41, 0xF0, 0x9C, 0xA2, 0x02, 0x6B, 0x8C, 0xEB, 0x03, 0x23, 0x01, 0x6B, -0x00, 0xF6, 0x62, 0xC2, 0x20, 0xE8, 0x00, 0x65, -0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0xD7, 0xF1, -0x00, 0x18, 0x8C, 0xF1, 0x05, 0x97, 0x03, 0x63, +0x61, 0xF0, 0x76, 0xC2, 0x20, 0xE8, 0x00, 0x65, +0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x8D, 0xF3, +0x00, 0x18, 0x42, 0xF3, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, -0x00, 0x18, 0xD7, 0xF1, 0x00, 0x18, 0xC4, 0xF1, +0x00, 0x18, 0x8D, 0xF3, 0x00, 0x18, 0x7A, 0xF3, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x20, 0x6A, 0x6E, 0xF2, 0x58, 0x9A, @@ -21566,68 +24928,68 @@ u8 array_mp_8821c_fw_nic[] = { 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x08, 0xF3, 0x8A, 0xA3, 0x02, 0x6A, 0xFF, 0x6D, 0x8C, 0xEA, 0x0D, 0x22, 0x10, 0xF0, 0x24, 0x6A, -0xDC, 0xF2, 0x94, 0x9A, 0x40, 0x6E, 0x40, 0xA4, +0xFE, 0xF2, 0x94, 0x9A, 0x40, 0x6E, 0x40, 0xA4, 0xAC, 0xEA, 0xCD, 0xEA, 0xAC, 0xEA, 0x40, 0xC4, 0x01, 0x6A, 0x08, 0xF3, 0x4D, 0xC3, 0x30, 0xF0, -0x20, 0x68, 0xCF, 0xF4, 0x00, 0x48, 0xE0, 0xF5, -0x68, 0xA0, 0x02, 0x6A, 0x6C, 0xEA, 0x0F, 0x22, -0xE0, 0xF5, 0x2A, 0xA0, 0x91, 0x67, 0x00, 0x18, -0x46, 0xF1, 0x40, 0x6B, 0x4D, 0xEB, 0xFF, 0x6D, -0x91, 0x67, 0x6C, 0xED, 0x00, 0x18, 0x39, 0xF1, -0x01, 0x6A, 0x00, 0xF6, 0x42, 0xC0, 0x07, 0x97, +0x20, 0x68, 0xEF, 0xF4, 0x00, 0x48, 0x41, 0xF0, +0x7C, 0xA0, 0x02, 0x6A, 0x6C, 0xEA, 0x0F, 0x22, +0x41, 0xF0, 0x3E, 0xA0, 0x91, 0x67, 0x00, 0x18, +0xFC, 0xF2, 0x40, 0x6B, 0x4D, 0xEB, 0xFF, 0x6D, +0x91, 0x67, 0x6C, 0xED, 0x00, 0x18, 0xEF, 0xF2, +0x01, 0x6A, 0x61, 0xF0, 0x56, 0xC0, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, -0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0xEE, 0xF1, -0x00, 0x18, 0xAA, 0xF1, 0x05, 0x97, 0x03, 0x63, +0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0xA4, 0xF3, +0x00, 0x18, 0x60, 0xF3, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x20, 0x6A, 0x6E, 0xF2, 0x58, 0x9A, 0xFF, 0x6C, 0xA4, 0x67, 0x22, 0x6E, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x08, 0xF3, 0x8A, 0xA3, 0x02, 0x6A, 0xFF, 0x6D, 0x8C, 0xEA, 0x0D, 0x22, -0x10, 0xF0, 0x24, 0x6A, 0xDC, 0xF2, 0x94, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0xFE, 0xF2, 0x94, 0x9A, 0x40, 0x6E, 0x40, 0xA4, 0xAC, 0xEA, 0xCD, 0xEA, 0xAC, 0xEA, 0x40, 0xC4, 0x03, 0x6A, 0x08, 0xF3, -0x4D, 0xC3, 0x30, 0xF0, 0x20, 0x68, 0xCF, 0xF4, -0x00, 0x48, 0xE0, 0xF5, 0x68, 0xA0, 0x02, 0x6A, -0x6C, 0xEA, 0x0F, 0x22, 0xE0, 0xF5, 0x2A, 0xA0, -0x91, 0x67, 0x00, 0x18, 0x46, 0xF1, 0x40, 0x6B, +0x4D, 0xC3, 0x30, 0xF0, 0x20, 0x68, 0xEF, 0xF4, +0x00, 0x48, 0x41, 0xF0, 0x7C, 0xA0, 0x02, 0x6A, +0x6C, 0xEA, 0x0F, 0x22, 0x41, 0xF0, 0x3E, 0xA0, +0x91, 0x67, 0x00, 0x18, 0xFC, 0xF2, 0x40, 0x6B, 0x4D, 0xEB, 0xFF, 0x6D, 0x91, 0x67, 0x6C, 0xED, -0x00, 0x18, 0x39, 0xF1, 0x03, 0x6A, 0x00, 0xF6, -0x42, 0xC0, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, +0x00, 0x18, 0xEF, 0xF2, 0x03, 0x6A, 0x61, 0xF0, +0x56, 0xC0, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, 0x6E, 0xF2, 0x58, 0x9A, 0x00, 0x6D, 0xFF, 0x6C, 0xC5, 0x67, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x08, 0xF3, 0x8A, 0xA2, 0x02, 0x6B, 0x8C, 0xEB, 0x03, 0x23, 0x01, 0x6B, 0x08, 0xF3, 0x6D, 0xC2, -0x30, 0xF0, 0x20, 0x6A, 0xCF, 0xF4, 0x00, 0x4A, -0xE0, 0xF5, 0x88, 0xA2, 0x02, 0x6B, 0x8C, 0xEB, -0x03, 0x23, 0x01, 0x6B, 0x00, 0xF6, 0x62, 0xC2, +0x30, 0xF0, 0x20, 0x6A, 0xEF, 0xF4, 0x00, 0x4A, +0x41, 0xF0, 0x9C, 0xA2, 0x02, 0x6B, 0x8C, 0xEB, +0x03, 0x23, 0x01, 0x6B, 0x61, 0xF0, 0x76, 0xC2, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, -0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0x33, 0xF2, -0x00, 0x18, 0xAA, 0xF1, 0x05, 0x97, 0x03, 0x63, +0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 0xE9, 0xF3, +0x00, 0x18, 0x60, 0xF3, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x20, 0x6A, 0x6E, 0xF2, 0x58, 0x9A, 0xFF, 0x6C, 0x6F, 0x6D, 0x25, 0x6E, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x08, 0xF3, 0x8A, 0xA2, 0x02, 0x6B, 0x8C, 0xEB, 0x0B, 0x23, 0x10, 0xF0, -0x24, 0x6B, 0xDC, 0xF2, 0x94, 0x9B, 0xBF, 0x6B, +0x24, 0x6B, 0xFE, 0xF2, 0x94, 0x9B, 0xBF, 0x6B, 0xA0, 0xA4, 0xAC, 0xEB, 0x60, 0xC4, 0x04, 0x6B, 0x08, 0xF3, 0x6D, 0xC2, 0x30, 0xF0, 0x20, 0x69, -0xCF, 0xF4, 0x00, 0x49, 0xE0, 0xF5, 0x68, 0xA1, -0x02, 0x6A, 0x6C, 0xEA, 0x0D, 0x22, 0xE0, 0xF5, -0x0A, 0xA1, 0x90, 0x67, 0x00, 0x18, 0x46, 0xF1, +0xEF, 0xF4, 0x00, 0x49, 0x41, 0xF0, 0x7C, 0xA1, +0x02, 0x6A, 0x6C, 0xEA, 0x0D, 0x22, 0x41, 0xF0, +0x1E, 0xA1, 0x90, 0x67, 0x00, 0x18, 0xFC, 0xF2, 0xBF, 0x6D, 0x4C, 0xED, 0x90, 0x67, 0x00, 0x18, -0x39, 0xF1, 0x04, 0x6A, 0x00, 0xF6, 0x42, 0xC1, +0xEF, 0xF2, 0x04, 0x6A, 0x61, 0xF0, 0x56, 0xC1, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x08, 0xF3, 0x8A, 0xA2, 0x01, 0x6B, 0x8C, 0xEB, 0x05, 0x23, 0x08, 0xF3, 0x4D, 0xA2, 0x02, 0x72, 0x00, 0x6A, 0x10, 0x61, -0x30, 0xF0, 0x20, 0x6B, 0xCF, 0xF4, 0x00, 0x4B, -0xE0, 0xF5, 0x48, 0xA3, 0x01, 0x6C, 0x4C, 0xEC, -0x01, 0x6A, 0x06, 0x24, 0x00, 0xF6, 0x42, 0xA3, +0x30, 0xF0, 0x20, 0x6B, 0xEF, 0xF4, 0x00, 0x4B, +0x41, 0xF0, 0x5C, 0xA3, 0x01, 0x6C, 0x4C, 0xEC, +0x01, 0x6A, 0x06, 0x24, 0x61, 0xF0, 0x56, 0xA3, 0x02, 0x6B, 0x6E, 0xEA, 0x01, 0x5A, 0x58, 0x67, 0x20, 0xE8, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x20, 0x6B, @@ -21635,109 +24997,109 @@ u8 array_mp_8821c_fw_nic[] = { 0x8A, 0xA3, 0x01, 0x6D, 0xFF, 0x6A, 0xAC, 0xEC, 0x4C, 0xEC, 0x4C, 0xE9, 0x00, 0x68, 0x05, 0x24, 0x08, 0xF3, 0x0A, 0xA3, 0x1A, 0x30, 0xAC, 0xE8, -0x4C, 0xE8, 0x30, 0xF0, 0x20, 0x6A, 0xCF, 0xF4, -0x00, 0x4A, 0xE0, 0xF5, 0x88, 0xA2, 0x01, 0x6B, -0x6C, 0xEC, 0x06, 0x24, 0xE0, 0xF5, 0x08, 0xA2, +0x4C, 0xE8, 0x30, 0xF0, 0x20, 0x6A, 0xEF, 0xF4, +0x00, 0x4A, 0x41, 0xF0, 0x9C, 0xA2, 0x01, 0x6B, +0x6C, 0xEC, 0x06, 0x24, 0x41, 0xF0, 0x1C, 0xA2, 0xFF, 0x6A, 0x1A, 0x30, 0x6C, 0xE8, 0x4C, 0xE8, -0x00, 0x18, 0x62, 0xF1, 0x01, 0x72, 0x25, 0x61, +0x00, 0x18, 0x18, 0xF3, 0x01, 0x72, 0x25, 0x61, 0x24, 0x28, 0x30, 0xF0, 0x20, 0x6A, 0xC8, 0xF4, 0x72, 0xA2, 0x01, 0x6A, 0x6C, 0xEA, 0x08, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0x2E, 0xF4, 0x48, 0x9A, 0x91, 0x67, 0x01, 0x6D, 0x00, 0x6E, 0x40, 0xEA, -0x30, 0xF0, 0x20, 0x6B, 0xCF, 0xF4, 0x00, 0x4B, -0xE0, 0xF5, 0x48, 0xA3, 0x01, 0x6C, 0x4C, 0xEC, +0x30, 0xF0, 0x20, 0x6B, 0xEF, 0xF4, 0x00, 0x4B, +0x41, 0xF0, 0x5C, 0xA3, 0x01, 0x6C, 0x4C, 0xEC, 0x01, 0x6A, 0x0C, 0x24, 0x30, 0xF0, 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0x03, 0x80, 0x77, 0xB9, 0x03, 0x80, +0x81, 0xB9, 0x03, 0x80, 0x8B, 0xB9, 0x03, 0x80, +0x9D, 0xB9, 0x03, 0x80, 0x99, 0xC7, 0x03, 0x80, +0xC1, 0xC7, 0x03, 0x80, 0xA3, 0xC7, 0x03, 0x80, +0xCB, 0xC7, 0x03, 0x80, 0xAD, 0xC7, 0x03, 0x80, +0xD7, 0xC7, 0x03, 0x80, 0xB7, 0xC7, 0x03, 0x80, +0x4B, 0x2C, 0x10, 0x80, 0x55, 0x2C, 0x10, 0x80, +0x5F, 0x2C, 0x10, 0x80, 0x69, 0x2C, 0x10, 0x80, +0x73, 0x2C, 0x10, 0x80, 0x87, 0xD1, 0x03, 0x80, +0xD7, 0xD1, 0x03, 0x80, 0x2F, 0xD2, 0x03, 0x80, +0x87, 0xD2, 0x03, 0x80, 0xED, 0xD2, 0x03, 0x80, +0xC9, 0xDA, 0x03, 0x80, 0xF1, 0xDA, 0x03, 0x80, +0x17, 0xDB, 0x03, 0x80, 0x3D, 0xDB, 0x03, 0x80, +0x63, 0xDB, 0x03, 0x80, 0xFC, 0x10, 0x60, 0xB8, 0xFA, 0xFA, 0xFA, 0xFA, 0x8C, 0x04, 0x64, 0xB8, 0x90, 0x04, 0x64, 0xB8, 0x94, 0x04, 0x64, 0xB8, 0x98, 0x04, 0x64, 0xB8, 0x9C, 0x04, 0x64, 0xB8, -0xA0, 0x04, 0x64, 0xB8, 0x00, 0x00, 0x60, 0xB8, +0xA0, 0x04, 0x64, 0xB8, 0xAC, 0x98, 0x78, 0xB8, +0xAC, 0x80, 0x78, 0xB8, 0x00, 0x00, 0x60, 0xB8, 0x00, 0x00, 0x64, 0xB8, 0x54, 0x05, 0x64, 0xB8, 0x00, 0x00, 0x00, 0x80, 0x70, 0x06, 0x64, 0xB8, 0x78, 0x06, 0x64, 0xB8, 0x00, 0x00, 0x01, 0x80, @@ -22320,19 +25943,14 @@ u8 array_mp_8821c_fw_nic[] = { 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x40, 0xBF, 0x01, 0x64, 0xB8, 0x89, 0x00, 0x60, 0xB8, 0x8A, 0x00, 0x60, 0xB8, 0x1A, 0x04, 0x64, 0xB8, -0x1B, 0x04, 0x64, 0xB8, 0xA6, 0x01, 0x64, 0xB8, -0x87, 0x02, 0x64, 0xB8, 0x96, 0x02, 0x64, 0xB8, -0x86, 0x02, 0x64, 0xB8, 0xF8, 0x10, 0x60, 0xB8, -0x00, 0x00, 0x40, 0x00, 0xF0, 0x11, 0x64, 0xB8, -0xF1, 0x11, 0x64, 0xB8, 0x58, 0x05, 0x64, 0xB8, -0x01, 0x00, 0x60, 0xB8, 0x01, 0x00, 0x64, 0xB8, -0x64, 0x00, 0x60, 0xB8, 0x40, 0x00, 0x60, 0xB8, -0x4C, 0x00, 0x60, 0xB8, 0x44, 0x00, 0x60, 0xB8, -0x60, 0x00, 0x60, 0xB8, 0x00, 0x00, 0xC0, 0x00, -0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x24, 0x00, -0x82, 0x82, 0x62, 0x00, 0x88, 0x10, 0x60, 0xB8, -0x87, 0x00, 0x60, 0xB8, 0x86, 0x00, 0x60, 0xB8, -0x84, 0x00, 0x60, 0xB8, 0x30, 0x01, 0x64, 0xB8, +0x1B, 0x04, 0x64, 0xB8, 0x87, 0x02, 0x64, 0xB8, +0x96, 0x02, 0x64, 0xB8, 0x86, 0x02, 0x64, 0xB8, +0xF8, 0x10, 0x60, 0xB8, 0x00, 0x00, 0x40, 0x00, +0x01, 0x00, 0xFF, 0x00, 0xF0, 0x11, 0x64, 0xB8, +0x58, 0x05, 0x64, 0xB8, 0x01, 0x00, 0x60, 0xB8, +0x01, 0x00, 0x64, 0xB8, 0x88, 0x10, 0x60, 0xB8, +0xFB, 0x11, 0x64, 0xB8, 0xFA, 0x11, 0x64, 0xB8, +0xF8, 0x11, 0x64, 0xB8, 0x30, 0x01, 0x64, 0xB8, 0x20, 0x01, 0x64, 0xB8, 0x20, 0x11, 0x64, 0xB8, 0x28, 0x11, 0x64, 0xB8, 0x30, 0x11, 0x64, 0xB8, 0x38, 0x01, 0x64, 0xB8, 0x38, 0x11, 0x64, 0xB8, @@ -22343,49 +25961,83 @@ u8 array_mp_8821c_fw_nic[] = { 0x44, 0x02, 0x64, 0xB8, 0x4C, 0x02, 0x64, 0xB8, 0x54, 0x02, 0x64, 0xB8, 0xD8, 0x04, 0x64, 0xB8, 0xDC, 0x04, 0x64, 0xB8, 0x80, 0x00, 0x60, 0xB8, -0x00, 0x00, 0x80, 0x00, 0xAF, 0x01, 0x64, 0xB8, -0xCB, 0x01, 0x64, 0xB8, 0xFA, 0x11, 0x64, 0xB8, +0x00, 0x00, 0x80, 0x00, 0xCB, 0x01, 0x64, 0xB8, 0xF2, 0x11, 0x64, 0xB8, 0xFF, 0xFF, 0x7F, 0xFF, -0x24, 0x09, 0x64, 0xB8, 0x4C, 0x09, 0x64, 0xB8, -0x58, 0x09, 0x64, 0xB8, 0x10, 0x19, 0x64, 0xB8, -0x8C, 0x19, 0x64, 0xB8, 0x24, 0x04, 0x64, 0xB8, +0x24, 0x04, 0x64, 0xB8, 0x30, 0x00, 0x78, 0xB8, 0x00, 0x00, 0x78, 0xB8, 0xA4, 0x04, 0x64, 0xB8, 0xA8, 0x04, 0x64, 0xB8, 0x00, 0x00, 0x20, 0x00, -0x30, 0x00, 0x78, 0xB8, 0x22, 0x05, 0x64, 0xB8, +0xAF, 0x01, 0x64, 0xB8, 0x5B, 0x01, 0x64, 0xB8, +0x3C, 0x01, 0x64, 0xB8, 0x22, 0x05, 0x64, 0xB8, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x08, 0x00, -0x00, 0x00, 0x1E, 0x00, 0x0A, 0x06, 0x64, 0xB8, -0xB1, 0x05, 0x64, 0xB8, 0x57, 0x01, 0x64, 0xB8, -0x3C, 0x01, 0x64, 0xB8, 0xCA, 0x01, 0x64, 0xB8, -0x5B, 0x01, 0x64, 0xB8, 0xFE, 0x11, 0x64, 0xB8, -0xA8, 0x06, 0x64, 0xB8, 0x10, 0x07, 0x64, 0xB8, -0x00, 0x16, 0x64, 0xB8, 0x04, 0x16, 0x64, 0xB8, -0x08, 0x16, 0x64, 0xB8, 0xAB, 0x06, 0x64, 0xB8, -0xAA, 0x06, 0x64, 0xB8, 0x13, 0x07, 0x64, 0xB8, -0x12, 0x07, 0x64, 0xB8, 0x03, 0x16, 0x64, 0xB8, -0x02, 0x16, 0x64, 0xB8, 0x07, 0x16, 0x64, 0xB8, -0x06, 0x16, 0x64, 0xB8, 0x0B, 0x16, 0x64, 0xB8, -0x0A, 0x16, 0x64, 0xB8, 0xFC, 0x11, 0x64, 0xB8, +0x0A, 0x06, 0x64, 0xB8, 0xCA, 0x01, 0x64, 0xB8, +0xFE, 0x11, 0x64, 0xB8, 0xA8, 0x06, 0x64, 0xB8, +0x10, 0x07, 0x64, 0xB8, 0x00, 0x16, 0x64, 0xB8, +0x04, 0x16, 0x64, 0xB8, 0x08, 0x16, 0x64, 0xB8, +0xAB, 0x06, 0x64, 0xB8, 0xAA, 0x06, 0x64, 0xB8, +0x13, 0x07, 0x64, 0xB8, 0x12, 0x07, 0x64, 0xB8, +0x03, 0x16, 0x64, 0xB8, 0x02, 0x16, 0x64, 0xB8, +0x07, 0x16, 0x64, 0xB8, 0x06, 0x16, 0x64, 0xB8, +0x0B, 0x16, 0x64, 0xB8, 0x0A, 0x16, 0x64, 0xB8, +0xFC, 0x11, 0x64, 0xB8, 0x57, 0x01, 0x64, 0xB8, +0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x06, 0x00, +0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x30, 0x00, +0x00, 0x00, 0x00, 0x03, 0xB1, 0x05, 0x64, 0xB8, 0x04, 0x06, 0x64, 0xB8, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x01, 0x60, 0x16, 0x64, 0xB8, -0x0D, 0x00, 0x78, 0xB8, 0x12, 0x00, 0x78, 0xB8, -0x11, 0x00, 0x78, 0xB8, 0x06, 0x00, 0x78, 0xB8, -0xA7, 0x04, 0x64, 0xB8, 0xA6, 0x04, 0x64, 0xB8, -0xA5, 0x04, 0x64, 0xB8, 0x14, 0x00, 0x78, 0xB8, 0x09, 0x00, 0x78, 0xB8, 0x31, 0x00, 0x78, 0xB8, -0x1D, 0x04, 0x64, 0xB8, 0x32, 0x00, 0x78, 0xB8, -0x33, 0x00, 0x78, 0xB8, 0x7A, 0x04, 0x64, 0xB8, -0x10, 0x05, 0x64, 0xB8, 0x11, 0x05, 0x64, 0xB8, +0x14, 0x00, 0x78, 0xB8, 0x1D, 0x04, 0x64, 0xB8, +0x32, 0x00, 0x78, 0xB8, 0x33, 0x00, 0x78, 0xB8, +0x7A, 0x04, 0x64, 0xB8, 0xD4, 0x04, 0x64, 0xB8, +0x88, 0x04, 0x64, 0xB8, 0xD0, 0x04, 0x64, 0xB8, +0x84, 0x04, 0x64, 0xB8, 0x56, 0x04, 0x64, 0xB8, +0x1C, 0x04, 0x64, 0xB8, 0x20, 0x04, 0x64, 0xB8, +0xFF, 0xFF, 0xEF, 0xFF, 0x00, 0x00, 0x10, 0x00, 0x88, 0x00, 0x60, 0xB8, 0x8B, 0x00, 0x60, 0xB8, +0x84, 0x00, 0x60, 0xB8, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x60, 0xE0, 0x00, 0x60, 0xB8, 0xE1, 0x00, 0x60, 0xB8, 0xE8, 0x12, 0x64, 0xB8, 0xFF, 0xFF, 0x03, 0x00, 0xFF, 0xFF, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xDF, 0xFF, 0xFF, 0xFF, 0x1F, 0x04, 0x00, 0x60, 0xB8, 0x04, 0x00, 0x64, 0xB8, 0x08, 0x00, 0x60, 0xB8, 0x08, 0x00, 0x64, 0xB8, -0x24, 0x00, 0x60, 0xB8, 0xCC, 0x07, 0x64, 0xB8, -0x82, 0x10, 0x60, 0xB8, 0x42, 0x34, 0x00, 0xB8, -0x00, 0x0C, 0x01, 0x00, 0x01, 0x00, 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0xC0, 0x0A, 0x00, 0x08, 0x00, 0x44, 0x01, +0xF3, 0x0E, 0x05, 0x00, 0x18, 0xDC, 0x0A, 0x00, +0x4E, 0x00, 0x05, 0x00, 0x18, 0x9C, 0x0A, 0x00, +0x00, 0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x0F, +0x62, 0x06, 0x64, 0xB8, 0xB4, 0x06, 0x64, 0xB8, +0x06, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x50, +0x40, 0x00, 0x0F, 0x70, 0x02, 0x04, 0x00, 0xD8, +0x20, 0x01, 0x00, 0xD1, 0x40, 0x80, 0x0B, 0x70, +0x02, 0x04, 0x02, 0xD8, 0x20, 0x01, 0x00, 0xDE, +0x48, 0x00, 0x46, 0x01, 0x60, 0x10, 0x05, 0x00, +0xDE, 0x0F, 0x0E, 0x00, 0xCE, 0xEF, 0x0D, 0x00, +0xCE, 0xEF, 0x05, 0x00, 0xFF, 0x3F, 0x0E, 0x00, +0x1F, 0xFF, 0x0F, 0x00, 0xE8, 0x0E, 0x05, 0x00, +0x45, 0x23, 0x01, 0x00, 0x08, 0x08, 0x00, 0xF8, +0x08, 0x07, 0x00, 0xF8, 0x08, 0x02, 0x00, 0xF8, +0x08, 0x03, 0x00, 0xF8, 0x18, 0x00, 0x00, 0xF8, +0xDE, 0xBC, 0x0A, 0x00, 0x01, 0x00, 0x66, 0xB8, 0x00, 0x00, 0x66, 0xB8, 0xCD, 0x9B, 0x78, 0x56, 0x00, 0x1C, 0x66, 0xB8, 0x04, 0x1C, 0x66, 0xB8, 0xFF, 0xFF, 0x3F, 0x00, 0x1F, 0x00, 0x60, 0xB8, @@ -22403,31 +26055,38 @@ u8 array_mp_8821c_fw_nic[] = { 0x03, 0x10, 0x66, 0xB8, 0x09, 0x10, 0x66, 0xB8, 0x04, 0x10, 0x66, 0xB8, 0x05, 0x10, 0x66, 0xB8, 0x0C, 0x10, 0x66, 0xB8, 0x0D, 0x10, 0x66, 0xB8, -0x06, 0x10, 0x66, 0xB8, 0xF0, 0x02, 0x64, 0xB8, -0x00, 0x10, 0x66, 0xB8, 0x00, 0x00, 0x00, 0xFF, -0xFF, 0xFF, 0x0F, 0x00, 0xFF, 0xFF, 0xFF, 0x0F, -0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x07, -0x00, 0x00, 0x00, 0x03, 0x00, 0xFF, 0xF9, 0xFF, -0x00, 0x00, 0xFE, 0x1F, 0xFF, 0xFF, 0xF7, 0xFF, -0xFF, 0xFC, 0xFE, 0xFF, 0x00, 0x01, 0x01, 0x00, +0x06, 0x10, 0x66, 0xB8, 0x00, 0x00, 0x7F, 0x00, +0xFF, 0xFF, 0x0B, 0xFF, 0x00, 0x00, 0x70, 0x00, +0xFF, 0xFF, 0x7A, 0xFF, 0x00, 0x00, 0xD0, 0x00, +0xFF, 0xFF, 0xDA, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, +0x00, 0xFF, 0xF9, 0xFF, 0x00, 0x00, 0xFE, 0x1F, +0x1C, 0x0C, 0xB8, 0x64, 0x67, 0x56, 0x23, 0x01, +0xFF, 0xFF, 0xF7, 0xFF, 0xFF, 0xFC, 0xFE, 0xFF, +0x00, 0x01, 0x01, 0x00, 0x00, 0xFC, 0xCF, 0xFF, +0x00, 0x00, 0x01, 0x10, 0x00, 0xF3, 0x3F, 0xFF, +0x01, 0x00, 0x02, 0x20, 0x00, 0xCF, 0xFF, 0xFC, +0x02, 0x00, 0x04, 0x40, 0x00, 0xFC, 0xCE, 0xEF, +0x40, 0x02, 0x20, 0x00, 0x80, 0x03, 0x30, 0x00, +0x00, 0x00, 0x80, 0x01, 0xCC, 0x06, 0x64, 0xB8, 0xA3, 0x00, 0x60, 0xB8, 0xA0, 0x00, 0x60, 0xB8, -0x65, 0x07, 0x64, 0xB8, 0x68, 0x00, 0x60, 0xB8, -0x6E, 0x07, 0x64, 0xB8, 0xCC, 0x06, 0x64, 0xB8, -0x64, 0x07, 0x64, 0xB8, 0x23, 0x05, 0x64, 0xB8, -0xFF, 0xFF, 0x40, 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, -0x28, 0x00, 0x60, 0xB8, 0xFF, 0xFF, 0xFF, 0x81, -0x00, 0x00, 0x70, 0xB8, 0x18, 0x00, 0x70, 0xB8, -0x0B, 0x00, 0x70, 0xB8, 0x02, 0x00, 0x70, 0xB8, -0x1C, 0x01, 0x64, 0xB8, 0x94, 0x02, 0x64, 0xB8, -0x97, 0x02, 0x64, 0xB8, 0x1C, 0x04, 0x64, 0xB8, +0x65, 0x07, 0x64, 0xB8, 0x40, 0x00, 0x60, 0xB8, +0x68, 0x00, 0x60, 0xB8, 0x6E, 0x07, 0x64, 0xB8, +0x64, 0x07, 0x64, 0xB8, 0x23, 0x05, 0x64, 0xB8, +0x64, 0x00, 0x60, 0xB8, 0xFF, 0xFF, 0x40, 0xFF, +0xFF, 0xFF, 0xFF, 0xE0, 0x28, 0x00, 0x60, 0xB8, +0xFF, 0xFF, 0xFF, 0x81, 0x00, 0x00, 0x70, 0xB8, +0x18, 0x00, 0x70, 0xB8, 0x0B, 0x00, 0x70, 0xB8, +0x02, 0x00, 0x70, 0xB8, 0x1C, 0x01, 0x64, 0xB8, +0x94, 0x02, 0x64, 0xB8, 0x97, 0x02, 0x64, 0xB8, 0x50, 0x02, 0x64, 0xB8, 0x04, 0x00, 0x78, 0xB8, 0x48, 0x02, 0x64, 0xB8, 0xCC, 0x01, 0x64, 0xB8, 0xF4, 0x11, 0x64, 0xB8, 0xF5, 0x11, 0x64, 0xB8, -0xD4, 0x04, 0x60, 0xB8, 0xD4, 0x04, 0x64, 0xB8, -0x84, 0x04, 0x60, 0xB8, 0x84, 0x04, 0x64, 0xB8, +0xD4, 0x04, 0x60, 0xB8, 0x84, 0x04, 0x60, 0xB8, 0xC8, 0x04, 0x60, 0xB8, 0xC8, 0x04, 0x64, 0xB8, 0x78, 0x04, 0x60, 0xB8, 0x78, 0x04, 0x64, 0xB8, -0x64, 0x05, 0x64, 0xB8, 0x27, 0x05, 0x64, 0xB8, +0xCF, 0x01, 0x64, 0xB8, 0x34, 0x01, 0x64, 0xB8, +0x64, 0x05, 0x64, 0xB8, 0x44, 0x00, 0x60, 0xB8, +0x60, 0x00, 0x60, 0xB8, 0x27, 0x05, 0x64, 0xB8, 0xB5, 0x05, 0x64, 0xB8, 0x1D, 0x05, 0x64, 0xB8, 0x1C, 0x05, 0x64, 0xB8, 0xB7, 0x05, 0x64, 0xB8, 0x31, 0x05, 0x64, 0xB8, 0x3C, 0x11, 0x64, 0xB8, @@ -22437,9 +26096,9 @@ u8 array_mp_8821c_fw_nic[] = { 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x05, 0x64, 0x01, 0x64, 0xB8, 0x53, 0x05, 0x64, 0xB8, 0x77, 0x05, 0x64, 0xB8, 0x68, 0x05, 0x64, 0xB8, -0x94, 0x01, 0x64, 0xB8, 0x9A, 0x01, 0x64, 0xB8, -0x99, 0x01, 0x64, 0xB8, 0xC7, 0x01, 0x64, 0xB8, -0xC6, 0x01, 0x64, 0xB8, 0x34, 0x01, 0x64, 0xB8, +0x94, 0x01, 0x64, 0xB8, 0x00, 0x10, 0x66, 0xB8, +0x9A, 0x01, 0x64, 0xB8, 0x99, 0x01, 0x64, 0xB8, +0xC7, 0x01, 0x64, 0xB8, 0xC6, 0x01, 0x64, 0xB8, 0x24, 0x01, 0x64, 0xB8, 0x24, 0x11, 0x64, 0xB8, 0x2C, 0x11, 0x64, 0xB8, 0x34, 0x11, 0x64, 0xB8, 0xE4, 0x11, 0x64, 0xB8, 0x54, 0x00, 0x60, 0xB8, @@ -22449,55 +26108,117 @@ u8 array_mp_8821c_fw_nic[] = { 0x67, 0x05, 0x64, 0xB8, 0x66, 0x05, 0x64, 0xB8, 0x65, 0x05, 0x64, 0xB8, 0x63, 0x05, 0x64, 0xB8, 0x62, 0x05, 0x64, 0xB8, 0x61, 0x05, 0x64, 0xB8, -0x2F, 0x01, 0x64, 0xB8, 0xCF, 0x01, 0x64, 0xB8, -0x00, 0x28, 0x64, 0xB8, 0x00, 0x2C, 0x64, 0xB8, -0x00, 0x38, 0x64, 0xB8, 0x00, 0x3C, 0x64, 0xB8, +0x2F, 0x01, 0x64, 0xB8, 0x00, 0x28, 0x64, 0xB8, +0x00, 0x2C, 0x64, 0xB8, 0x00, 0x38, 0x64, 0xB8, +0x00, 0x3C, 0x64, 0xB8, 0x00, 0x03, 0x07, 0x00, +0xFF, 0x03, 0x07, 0x00, 0x54, 0x04, 0x64, 0xB8, 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array_mp_8821c_fw_nic[] = { 0x6F, 0x55, 0x70, 0x42, 0x77, 0x3D, 0x25, 0x62, 0x78, 0x2C, 0x53, 0x47, 0x49, 0x3D, 0x25, 0x62, 0x78, 0x2C, 0x56, 0x48, 0x54, 0x3D, 0x25, 0x62, -0x78, 0x00, 0x00, 0x00, 0x4D, 0x74, 0x42, 0x77, +0x78, 0x00, 0x00, 0x00, 0x50, 0x45, 0x52, 0x3A, +0x25, 0x62, 0x78, 0x20, 0x43, 0x75, 0x72, 0x3A, +0x25, 0x62, 0x78, 0x20, 0x4F, 0x3A, 0x25, 0x62, +0x78, 0x00, 0x00, 0x00, 0x4D, 0x61, 0x70, 0x3A, +0x25, 0x62, 0x78, 0x20, 0x44, 0x69, 0x66, 0x3A, +0x25, 0x62, 0x78, 0x20, 0x6F, 0x66, 0x74, 0x3A, +0x25, 0x62, 0x78, 0x00, 0x56, 0x61, 0x72, 0x3A, +0x20, 0x25, 0x62, 0x78, 0x2D, 0x3E, 0x25, 0x62, +0x78, 0x00, 0x00, 0x00, 0x44, 0x65, 0x63, 0x5F, +0x6F, 0x66, 0x73, 0x74, 0x7B, 0x50, 0x2C, 0x4E, +0x7D, 0x3A, 0x20, 0x25, 0x62, 0x78, 0x2C, 0x25, +0x62, 0x78, 0x00, 0x00, 0x4D, 0x74, 0x42, 0x77, 0x20, 0x55, 0x70, 0x44, 0x77, 0x25, 0x62, 0x78, 0x20, 0x42, 0x57, 0x25, 0x62, 0x78, 0x20, 0x52, 0x74, 0x25, 0x62, 0x78, 0x00, 0x00, 0x00, 0x00, @@ -22577,106 +26309,96 @@ u8 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0x30, 0xF0, 0x20, 0x6B, +0xFF, 0x6A, 0xAF, 0xF4, 0x18, 0x4B, 0x8C, 0xEA, +0x60, 0xF4, 0x81, 0xA3, 0x55, 0x24, 0x60, 0xF4, +0x63, 0xA3, 0x00, 0x69, 0x01, 0x23, 0x01, 0x69, +0x30, 0xF0, 0x21, 0x6B, 0x10, 0xF1, 0x7C, 0xA3, +0x02, 0x2B, 0x01, 0x6B, 0x6E, 0xE9, 0x29, 0x2A, +0x23, 0x10, 0x10, 0xF0, 0x23, 0x6B, 0x30, 0xF0, +0x20, 0x68, 0x6F, 0xF1, 0xA4, 0x9B, 0xCE, 0xF4, +0x50, 0x98, 0x4C, 0x6C, 0x02, 0x6E, 0x40, 0xEA, +0xCE, 0xF4, 0x50, 0x98, 0xA1, 0xF4, 0x14, 0x6C, +0xFF, 0x6D, 0x66, 0x6E, 0x40, 0xEA, 0x01, 0x6A, +0x4E, 0xE9, 0x2B, 0xEB, 0x2D, 0xEB, 0xC0, 0xF7, +0x62, 0x33, 0x10, 0xF0, 0x23, 0x6D, 0x02, 0x6E, +0xCE, 0xF4, 0x50, 0x98, 0xA1, 0xF4, 0x14, 0x6C, +0xEF, 0xF0, 0xBC, 0x9D, 0x7B, 0xE6, 0x23, 0x10, +0x30, 0xF0, 0x21, 0x6A, 0x10, 0xF1, 0x5D, 0xA2, +0xD8, 0x22, 0x10, 0xF0, 0x23, 0x6B, 0x30, 0xF0, +0x20, 0x68, 0x6F, 0xF1, 0xA4, 0x9B, 0xCE, 0xF4, +0x50, 0x98, 0x4C, 0x6C, 0x02, 0x6E, 0x40, 0xEA, +0xCE, 0xF4, 0x50, 0x98, 0xA1, 0xF4, 0x14, 0x6C, +0xFF, 0x6D, 0x77, 0x6E, 0x40, 0xEA, 0x10, 0xF0, +0x23, 0x6B, 0x2B, 0xE9, 0xCE, 0xF4, 0x50, 0x98, +0xEF, 0xF0, 0xBC, 0x9B, 0xC0, 0xF7, 0x22, 0x36, +0xA1, 0xF4, 0x14, 0x6C, 0x01, 0x4E, 0x40, 0xEA, +0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, +0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, +0xFF, 0x6A, 0x4C, 0xEC, 0x0F, 0x5C, 0x0A, 0x60, +0x10, 0xF0, 0x23, 0x6A, 0x6F, 0xF1, 0x68, 0x9A, +0xFC, 0x6A, 0x80, 0xA3, 0x8C, 0xEA, 0x40, 0xC3, +0x00, 0x6C, 0x0E, 0x10, 0x24, 0x5C, 0x00, 0x6C, +0x0B, 0x61, 0x10, 0xF0, 0x23, 0x6B, 0x6F, 0xF1, +0x88, 0x9B, 0x03, 0x6D, 0x60, 0xA4, 0x4C, 0xEB, +0xAD, 0xEB, 0x4C, 0xEB, 0x60, 0xC4, 0x01, 0x6C, +0x80, 0x18, 0xE9, 0x06, 0x05, 0x97, 0x03, 0x63, +0x00, 0xEF, 0x00, 0x65, 0x10, 0xF0, 0x21, 0x6A, 0x84, 0xF4, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0x8E, 0xF6, 0x48, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0x24, 0xF5, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B, @@ -25552,19 +40421,21 @@ u8 array_mp_8821c_fw_nic[] = { 0xAE, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0xC6, 0xF1, 0x0C, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x40, 0xDB, 0x20, 0xE8, 0x00, 0x65, -0x19, 0xEE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +0xBA, 0xE1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -u32 array_length_mp_8821c_fw_nic = 115080; +u32 array_length_mp_8821c_fw_spic = 71264; + +#ifdef CONFIG_WOWLAN u8 array_mp_8821c_fw_wowlan[] = { -0x21, 0x88, 0x00, 0x00, 0x09, 0x00, 0x07, 0x00, -0x42, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x03, 0x0C, 0x12, 0x03, 0xE1, 0x07, 0x00, 0x00, -0x18, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, +0x21, 0x88, 0x00, 0x00, 0x14, 0x00, 0x01, 0x00, +0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, +0x07, 0x01, 0x0E, 0x33, 0xE2, 0x07, 0x00, 0x00, +0x18, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x80, 0xC0, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, -0x90, 0xD1, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, +0x28, 0xF6, 0x00, 0x00, 0xD0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, @@ -25615,7 +40486,7 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x01, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x01, 0x10, 0x00, 0x01, 0x00, 0x03, 0x80, 0x9D, 0x01, 0x03, 0x80, 0x9D, 0x01, 0x03, 0x80, -0x51, 0x81, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, +0x61, 0x96, 0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -29411,7 +44282,7 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x81, 0x82, 0x03, 0x80, 0x01, 0x00, 0x00, 0x00, +0x55, 0x98, 0x03, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -29419,7 +44290,7 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x44, 0x7F, 0x20, 0x80, 0x00, 0x50, 0xF2, 0x01, +0x10, 0x82, 0x20, 0x80, 0x00, 0x50, 0xF2, 0x01, 0x06, 0x09, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x36, 0x01, 0x02, 0x05, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x06, 0x05, 0x06, 0x07, 0x08, @@ -29558,7 +44429,7 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x00, 0x0C, 0x0E, 0x38, 0x18, 0x00, 0x00, 0x00, 0x00, 0x83, 0x01, 0x06, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x70, 0xE0, 0x00, 0x00, 0x00, 0x00, -0xC4, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x74, 0xC8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0xF0, 0x21, 0x6C, 0x18, 0xF0, 0x00, 0x4C, 0xBC, 0x65, 0x1F, 0xF7, 0x00, 0x6C, 0x8C, 0xB9, 0x00, 0x65, 0x00, 0x65, 0x00, 0x65, 0x77, 0xF0, @@ -29573,18 +44444,18 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x20, 0x6C, 0xC0, 0xF1, 0x08, 0x4C, 0x00, 0x6E, 0x30, 0xF0, 0x20, 0x6F, 0x2F, 0xF0, 0x08, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, 0xE3, 0xEC, 0xB8, 0x67, -0xFB, 0x2D, 0x30, 0xF0, 0x20, 0x6C, 0x4F, 0xF7, -0x04, 0x4C, 0x00, 0x6E, 0x30, 0xF0, 0x20, 0x6F, -0x8F, 0xF7, 0x10, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, +0xFB, 0x2D, 0x30, 0xF0, 0x21, 0x6C, 0x10, 0xF2, +0x10, 0x4C, 0x00, 0x6E, 0x30, 0xF0, 0x21, 0x6F, +0xB0, 0xF3, 0x00, 0x4F, 0xC0, 0xDC, 0x04, 0x4C, 0xE3, 0xEC, 0xB8, 0x67, 0xFB, 0x2D, 0x10, 0xF0, 0x23, 0x6C, 0x80, 0xF0, 0x19, 0x4C, 0x00, 0xEC, 0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x10, 0xF0, -0x24, 0x6B, 0x59, 0xF4, 0x60, 0x9B, 0x10, 0xF0, +0x24, 0x6B, 0x3E, 0xF0, 0x74, 0x9B, 0x10, 0xF0, 0x23, 0x6A, 0x80, 0xF0, 0x19, 0x4A, 0x40, 0xDB, -0x00, 0x1C, 0x94, 0x00, 0x00, 0x18, 0x96, 0xC7, -0x00, 0x18, 0xE0, 0xC4, 0x00, 0x18, 0x00, 0xC5, -0x00, 0x18, 0x6A, 0xC7, 0x00, 0x18, 0x1B, 0xC5, -0x00, 0x18, 0x87, 0xC7, 0x00, 0x18, 0xA9, 0xC8, +0x00, 0x1C, 0x94, 0x00, 0x00, 0x18, 0xD2, 0xC7, +0x00, 0x18, 0x28, 0xC5, 0x00, 0x18, 0x4B, 0xC5, +0x00, 0x18, 0xA6, 0xC7, 0x00, 0x18, 0x76, 0xC5, +0x00, 0x18, 0xC3, 0xC7, 0x00, 0x18, 0x03, 0xC9, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF7, 0x54, 0x9A, 0x30, 0xF0, 0x20, 0x68, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6C, 0x30, 0xF0, 0x21, 0x6A, 0x80, 0xF1, @@ -29593,13 +44464,13 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x30, 0xF0, 0x20, 0x6B, 0x2D, 0xF1, 0x50, 0xDB, 0x30, 0xF0, 0x20, 0x6A, 0xEE, 0xF7, 0x50, 0x9A, 0x30, 0xF0, 0x20, 0x6C, 0x6F, 0xF0, 0x08, 0x4C, -0x01, 0x6D, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6B, -0x8F, 0xF7, 0x44, 0xDB, 0x30, 0xF0, 0x20, 0x6C, +0x01, 0x6D, 0x40, 0xEA, 0x30, 0xF0, 0x21, 0x6B, +0x50, 0xF2, 0x4C, 0xDB, 0x30, 0xF0, 0x20, 0x6C, 0x30, 0xF0, 0x21, 0x6A, 0x2F, 0xF0, 0x08, 0x4C, 0x15, 0xF4, 0x00, 0x4A, 0x43, 0xDC, 0xCE, 0xF7, 0x40, 0x98, 0x00, 0x6D, 0x40, 0xEA, 0x30, 0xF0, -0x20, 0x6B, 0x6F, 0xF7, 0x5C, 0xDB, 0x10, 0xF0, -0x24, 0x6A, 0x19, 0xF7, 0x60, 0x9A, 0xFF, 0xF7, +0x21, 0x6B, 0x50, 0xF2, 0x44, 0xDB, 0x10, 0xF0, +0x24, 0x6A, 0xFE, 0xF2, 0x78, 0x9A, 0xFF, 0xF7, 0x1F, 0x6C, 0x10, 0xF0, 0x00, 0x6D, 0x40, 0xAB, 0xAB, 0xED, 0x8C, 0xEA, 0xAD, 0xEA, 0x8C, 0xEA, 0x40, 0xCB, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF7, @@ -29608,8 +44479,8 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x30, 0xF0, 0x20, 0x6B, 0x2D, 0xF1, 0x40, 0x9B, 0x01, 0x4A, 0x10, 0x72, 0x2D, 0xF1, 0x40, 0xDB, 0x09, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x30, 0xF0, -0x20, 0x6B, 0xEE, 0xF7, 0x58, 0x9A, 0x8F, 0xF7, -0x88, 0x9B, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, +0x21, 0x6B, 0xEE, 0xF7, 0x58, 0x9A, 0x50, 0xF2, +0x90, 0x9B, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0x6D, 0xB8, 0x00, 0x65, 0x00, 0xF0, 0x20, 0x6A, 0x7C, 0x4A, 0x6C, 0xEA, 0x1C, 0x22, 0x00, 0xF0, 0x20, 0x6B, 0x28, 0x4B, @@ -29618,7 +44489,7 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x60, 0xAA, 0xBF, 0xF6, 0x1A, 0x6A, 0x6A, 0xEA, 0x31, 0x60, 0x77, 0xF0, 0x24, 0x6A, 0xA0, 0xF1, 0x1C, 0x4A, 0x1D, 0xF4, 0x00, 0x6B, 0x60, 0xDA, -0x10, 0xF0, 0x23, 0x6A, 0x44, 0xF2, 0x15, 0x4A, +0x10, 0xF0, 0x23, 0x6A, 0xA4, 0xF3, 0x1D, 0x4A, 0x00, 0xEA, 0x00, 0xF0, 0x20, 0x6A, 0x1F, 0xF7, 0x00, 0x6A, 0x4C, 0xEB, 0x4C, 0xB8, 0x00, 0x65, 0x6C, 0xEA, 0x42, 0x32, 0x30, 0xF0, 0x20, 0x6B, @@ -29655,7 +44526,7 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, 0x10, 0xF0, 0x23, 0x6C, -0x44, 0xF2, 0x15, 0x4C, 0x00, 0xEC, 0x00, 0x65, +0xA4, 0xF3, 0x1D, 0x4C, 0x00, 0xEC, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6B, 0x2D, 0xF1, 0x18, 0x4B, 0x41, 0x9B, 0x40, 0xDB, 0x89, 0x9A, 0xBC, 0x65, 0x7D, 0x67, 0xDF, 0xF7, 0x00, 0x03, 0x4C, 0xB8, @@ -29703,7 +44574,7 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x80, 0x44, 0x62, 0xEC, 0x0D, 0x60, 0x77, 0xF0, 0x24, 0x6C, 0xA0, 0xF1, 0x1C, 0x4C, 0x1D, 0xF4, 0x01, 0x6B, 0x60, 0xDC, 0x10, 0xF0, 0x23, 0x6C, -0x44, 0xF2, 0x15, 0x4C, 0x00, 0xEC, 0x00, 0x65, +0xA4, 0xF3, 0x1D, 0x4C, 0x00, 0xEC, 0x00, 0x65, 0x40, 0x9A, 0x30, 0xF0, 0x20, 0x6C, 0xAD, 0xF1, 0x08, 0x4C, 0x00, 0xF4, 0x00, 0x4C, 0xBC, 0x65, 0x82, 0x67, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6C, @@ -29746,266 +44617,290 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x00, 0x18, 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+0x04, 0x63, 0x00, 0xEF, 0xFF, 0x6A, 0x4C, 0xED, 0xFF, 0x75, 0x4C, 0xEC, 0xCC, 0xEA, 0x06, 0x61, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x71, 0xE4, 0x0B, 0x10, 0x30, 0xF0, 0x20, 0x6B, @@ -30017,36 +44912,36 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x4C, 0xEB, 0x08, 0xD3, 0x42, 0xA4, 0x61, 0xA4, 0x0B, 0xD2, 0x43, 0xA4, 0x84, 0xA4, 0x09, 0xD4, 0x08, 0x94, 0x08, 0x5C, 0x80, 0xF0, 0x11, 0x60, -0xFF, 0x69, 0x84, 0x30, 0x29, 0x22, 0x09, 0x94, -0x27, 0x24, 0x2C, 0xEA, 0x2C, 0xEB, 0xA2, 0x67, +0x84, 0x30, 0x09, 0x94, 0x01, 0x2C, 0x28, 0x22, +0xFF, 0x69, 0x2C, 0xEA, 0x2C, 0xEB, 0xA2, 0x67, 0xC3, 0x67, 0x90, 0x67, 0x0C, 0xD2, 0x0D, 0xD3, -0x00, 0x18, 0x7D, 0xC3, 0x0B, 0x94, 0x09, 0x93, +0x00, 0x18, 0xAD, 0xC3, 0x0B, 0x94, 0x09, 0x93, 0x41, 0x40, 0x2C, 0xEC, 0x0B, 0xD4, 0x0B, 0x96, 0x2C, 0xEA, 0x2C, 0xEB, 0x82, 0x67, 0xA3, 0x67, 0x30, 0xF0, 0x20, 0x69, 0x0A, 0xD2, 0x09, 0xD3, -0x00, 0x18, 0x7D, 0xC3, 0xCE, 0xF2, 0x44, 0x99, +0x00, 0x18, 0xAD, 0xC3, 0xCE, 0xF2, 0x44, 0x99, 0x0C, 0x95, 0x0D, 0x96, 0x90, 0x67, 0x01, 0x6F, 0x40, 0xEA, 0xCE, 0xF2, 0x44, 0x99, 0x0A, 0x94, 0x09, 0x95, 0x0B, 0x96, 0x02, 0x6F, 0x40, 0xEA, 0x0F, 0x58, 0x08, 0x60, 0x10, 0xF0, 0x24, 0x6A, -0x08, 0x33, 0x99, 0xF2, 0x04, 0x4A, 0x69, 0xE2, +0x08, 0x33, 0x7D, 0xF6, 0x1C, 0x4A, 0x69, 0xE2, 0x40, 0x9A, 0x00, 0xEA, 0x00, 0x6A, 0x44, 0x10, 0xD0, 0xF4, 0x44, 0x40, 0x1F, 0xF7, 0x00, 0x6B, 0x6C, 0xEA, 0x05, 0x2A, 0x10, 0xF0, 0x24, 0x6A, -0x99, 0xF7, 0x40, 0x9A, 0x34, 0x10, 0x10, 0xF0, -0x24, 0x6A, 0x99, 0xF7, 0x44, 0x9A, 0x2F, 0x10, +0xDE, 0xF3, 0x58, 0x9A, 0x34, 0x10, 0x10, 0xF0, +0x24, 0x6A, 0xDE, 0xF3, 0x5C, 0x9A, 0x2F, 0x10, 0x80, 0xF4, 0x44, 0x40, 0x1F, 0xF7, 0x00, 0x6B, 0x6C, 0xEA, 0x05, 0x2A, 0x10, 0xF0, 0x24, 0x6A, -0x99, 0xF7, 0x48, 0x9A, 0x24, 0x10, 0x10, 0xF0, -0x24, 0x6A, 0x99, 0xF7, 0x4C, 0x9A, 0x1F, 0x10, +0xFE, 0xF3, 0x40, 0x9A, 0x24, 0x10, 0x10, 0xF0, +0x24, 0x6A, 0xFE, 0xF3, 0x44, 0x9A, 0x1F, 0x10, 0xC0, 0xF4, 0x48, 0x40, 0x1F, 0xF7, 0x00, 0x6B, 0x6C, 0xEA, 0x05, 0x2A, 0x10, 0xF0, 0x24, 0x6A, -0x99, 0xF7, 0x50, 0x9A, 0x14, 0x10, 0x10, 0xF0, -0x24, 0x6A, 0x99, 0xF7, 0x54, 0x9A, 0x0F, 0x10, +0xFE, 0xF3, 0x48, 0x9A, 0x14, 0x10, 0x10, 0xF0, +0x24, 0x6A, 0xFE, 0xF3, 0x4C, 0x9A, 0x0F, 0x10, 0x70, 0xF4, 0x48, 0x40, 0x1F, 0xF7, 0x00, 0x6B, 0x6C, 0xEA, 0x05, 0x2A, 0x10, 0xF0, 0x24, 0x6A, -0x99, 0xF7, 0x58, 0x9A, 0x04, 0x10, 0x10, 0xF0, -0x24, 0x6A, 0x99, 0xF7, 0x5C, 0x9A, 0x49, 0xE0, +0xFE, 0xF3, 0x50, 0x9A, 0x04, 0x10, 0x10, 0xF0, +0x24, 0x6A, 0xFE, 0xF3, 0x54, 0x9A, 0x49, 0xE0, 0x60, 0xAA, 0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA, 0x7D, 0x67, 0x53, 0xC3, 0x42, 0x32, 0x54, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, @@ -30067,11 +44962,11 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x20, 0xE8, 0x00, 0x65, 0xFA, 0x63, 0x0B, 0x62, 0x0A, 0xD1, 0x09, 0xD0, 0x01, 0xA4, 0x20, 0xA4, 0x0C, 0x20, 0x90, 0x67, 0xB1, 0x67, 0x00, 0x18, -0xE7, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0x6E, 0xF2, +0x17, 0xC4, 0x30, 0xF0, 0x20, 0x6A, 0x6E, 0xF2, 0x58, 0x9A, 0x90, 0x67, 0xB1, 0x67, 0x53, 0x6E, 0x40, 0xEA, 0x7D, 0x67, 0x20, 0x6A, 0x50, 0xC3, 0x03, 0x6A, 0x4F, 0xCB, 0x10, 0xF0, 0x24, 0x6A, -0x19, 0xF5, 0x40, 0x9A, 0x9D, 0x67, 0x40, 0xA2, +0xDE, 0xF0, 0x5C, 0x9A, 0x9D, 0x67, 0x40, 0xA2, 0x52, 0xC3, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x2C, 0xF7, 0x7E, 0xA2, 0x2C, 0xF7, 0x5F, 0xA2, 0x73, 0xC4, 0x54, 0xC4, 0x30, 0xF0, @@ -30101,69 +44996,81 @@ u8 array_mp_8821c_fw_wowlan[] = { 0xB8, 0xA3, 0x4C, 0xEC, 0x84, 0x34, 0xBA, 0x35, 0x8D, 0xEF, 0x4E, 0xED, 0x86, 0x67, 0x0C, 0xEC, 0x4C, 0xED, 0x0C, 0xF5, 0xF9, 0xC3, 0x00, 0x18, -0x0B, 0xE6, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, +0x00, 0xED, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0xFC, 0x63, 0x07, 0x62, -0x06, 0xD0, 0x30, 0xF0, 0x20, 0x6A, 0x30, 0xF0, -0x20, 0x68, 0x4E, 0xF2, 0x50, 0x9A, 0x2F, 0xF5, -0x06, 0x48, 0xA4, 0x67, 0x07, 0x6E, 0x90, 0x67, -0x40, 0xEA, 0x40, 0xA0, 0x05, 0x5A, 0x13, 0x60, -0x10, 0xF0, 0x24, 0x6B, 0x48, 0x32, 0xF9, 0xF2, -0x10, 0x4B, 0x4D, 0xE3, 0x40, 0x9B, 0x00, 0xEA, -0x00, 0x6C, 0x07, 0x10, 0x01, 0x6C, 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0x6B, 0xC0, 0xF5, 0x05, 0x4B, 0x62, 0xDA, @@ -30179,484 +45086,493 @@ u8 array_mp_8821c_fw_wowlan[] = { 0xFB, 0x61, 0x42, 0xF4, 0x10, 0x6A, 0x1F, 0xF7, 0x00, 0x6B, 0x4C, 0xEB, 0x02, 0xF0, 0x00, 0x73, 0x01, 0x60, 0x05, 0x2B, 0x10, 0xF0, 0x24, 0x6B, -0x79, 0xF4, 0x60, 0x9B, 0x04, 0x10, 0x10, 0xF0, -0x24, 0x6B, 0x79, 0xF4, 0x64, 0x9B, 0x6D, 0xE2, +0x5E, 0xF0, 0x7C, 0x9B, 0x04, 0x10, 0x10, 0xF0, +0x24, 0x6B, 0x7E, 0xF0, 0x60, 0x9B, 0x6D, 0xE2, 0x04, 0x4A, 0x00, 0x6C, 0x62, 0xF4, 0x00, 0x72, 0x80, 0xDB, 0xE9, 0x61, 0x20, 0xE8, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, 0x10, 0xF0, 0x24, 0x6A, -0xF9, 0xF6, 0x5C, 0x9A, 0x03, 0x6D, 0xFF, 0x6B, -0x80, 0x9A, 0x10, 0xF0, 0x24, 0x6A, 0x19, 0xF7, -0x40, 0x9A, 0x00, 0xF5, 0x82, 0x34, 0xAC, 0xEC, +0xFE, 0xF2, 0x54, 0x9A, 0x03, 0x6D, 0xFF, 0x6B, +0x80, 0x9A, 0x10, 0xF0, 0x24, 0x6A, 0xFE, 0xF2, +0x58, 0x9A, 0x00, 0xF5, 0x82, 0x34, 0xAC, 0xEC, 0x40, 0x9A, 0x01, 0x74, 0x42, 0x32, 0x52, 0x32, 0xAC, 0xEA, 0x06, 0x60, 0x0A, 0x2C, 0x02, 0x5A, 0x28, 0x6C, 0x0D, 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0x9A, 0xE0, 0xDB, +0x10, 0xF0, 0x24, 0x6B, 0x5E, 0xF0, 0x60, 0x9B, +0xC0, 0xDB, 0x10, 0xF0, 0x24, 0x6B, 0x5E, 0xF0, +0x64, 0x9B, 0x4C, 0xF7, 0x14, 0x6E, 0xA0, 0xDB, +0x10, 0xF0, 0x24, 0x6B, 0x5E, 0xF0, 0x68, 0x9B, +0x80, 0xDB, 0x10, 0xF0, 0x24, 0x6B, 0x89, 0x9A, +0x5E, 0xF0, 0x6C, 0x9B, 0x80, 0xDB, 0x68, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0x5E, 0xF0, 0x50, 0x9A, +0x30, 0xF0, 0x20, 0x6C, 0xC0, 0xF1, 0x08, 0x4C, +0x60, 0xDA, 0x10, 0xF0, 0x24, 0x6A, 0x5E, 0xF0, +0xB4, 0x9A, 0x00, 0x18, 0xC1, 0xE6, 0x10, 0xF0, +0x24, 0x6A, 0x5E, 0xF0, 0xB8, 0x9A, 0x30, 0xF0, +0x21, 0x6C, 0x15, 0xF0, 0x00, 0x4C, 0x03, 0xF0, +0x00, 0x6E, 0x00, 0x18, 0xC1, 0xE6, 0x00, 0x1C, 0x96, 0x45, 0xFF, 0x17, 0x30, 0xF0, 0x20, 0x6A, 0x00, 0xF1, 0x00, 0x4A, 0x60, 0xDA, 0x81, 0xDA, 0xA2, 0xDA, 0xC3, 0xDA, 0xE4, 0xDA, 0x05, 0xDA, @@ -30666,7 +45582,7 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x00, 0x65, 0x6C, 0xDA, 0x68, 0xB8, 0x00, 0x65, 0x6D, 0xDA, 0x6C, 0xB8, 0x00, 0x65, 0x6E, 0xDA, 0x6E, 0xB8, 0x00, 0x65, 0x6F, 0xDA, 0x10, 0xF0, -0x23, 0x6A, 0xE4, 0xF1, 0x09, 0x4A, 0x00, 0xEA, +0x23, 0x6A, 0x04, 0xF3, 0x19, 0x4A, 0x00, 0xEA, 0x00, 0x65, 0x00, 0x65, 0x10, 0xF0, 0x23, 0x6A, 0x40, 0xF2, 0x09, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x44, 0xDB, 0x10, 0xF0, 0x23, 0x6A, @@ -30676,11 +45592,11 @@ u8 array_mp_8821c_fw_wowlan[] = { 0xCE, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x23, 0x6A, 0x20, 0xF5, 0x11, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x23, 0x6A, -0xE4, 0xF1, 0x09, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0x04, 0xF3, 0x19, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x23, 0x6A, -0x44, 0xF2, 0x15, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xA4, 0xF3, 0x1D, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x23, 0x6A, -0xC4, 0xF1, 0x11, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0x04, 0xF3, 0x01, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xCE, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0xE2, 0xF5, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0xEE, 0xF6, 0x40, 0xDB, 0x10, 0xF0, 0x21, 0x6A, @@ -30736,7 +45652,7 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x4E, 0xF7, 0x44, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0xA1, 0xF1, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0x4E, 0xF7, 0x48, 0xDB, 0x10, 0xF0, 0x23, 0x6A, -0xA4, 0xF1, 0x01, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xC4, 0xF2, 0x11, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0x4E, 0xF7, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, 0xFF, 0xF7, 0x1C, 0x4A, 0x30, 0xF0, 0x20, 0x6B, 0x4E, 0xF7, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A, @@ -30836,20 +45752,20 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x02, 0xF0, 0x00, 0x75, 0x01, 0x60, 0x25, 0x2D, 0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA, 0x02, 0xF0, 0x00, 0x72, 0x01, 0x60, 0x07, 0x2A, 0x10, 0xF0, -0x24, 0x6A, 0x79, 0xF4, 0xA0, 0x9A, 0xB5, 0xE3, +0x24, 0x6A, 0x5E, 0xF0, 0xBC, 0x9A, 0xB5, 0xE3, 0x60, 0xA5, 0x0B, 0x10, 0x10, 0xF0, 0x24, 0x6A, -0x79, 0xF4, 0xA0, 0x9A, 0x10, 0xF0, 0x24, 0x6A, -0x79, 0xF4, 0x44, 0x9A, 0xB5, 0xE3, 0x4D, 0xE3, +0x5E, 0xF0, 0xBC, 0x9A, 0x10, 0xF0, 0x24, 0x6A, +0x7E, 0xF0, 0x40, 0x9A, 0xB5, 0xE3, 0x4D, 0xE3, 0x60, 0xA3, 0x01, 0x6A, 0x00, 0xF6, 0x60, 0x33, 0x44, 0xEE, 0x00, 0xF6, 0x63, 0x33, 0x4F, 0xEA, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x40, 0xC5, -0x0E, 0x10, 0x10, 0xF0, 0x24, 0x6D, 0x79, 0xF4, -0xA4, 0x9D, 0x0F, 0xE8, 0xAD, 0xE3, 0xA0, 0xA3, +0x0E, 0x10, 0x10, 0xF0, 0x24, 0x6D, 0x7E, 0xF0, +0xA0, 0x9D, 0x0F, 0xE8, 0xAD, 0xE3, 0xA0, 0xA3, 0x00, 0xF6, 0xA0, 0x35, 0x00, 0xF6, 0xA3, 0x35, 0x0C, 0xED, 0x4C, 0xED, 0xA0, 0xC3, 0x30, 0xF0, -0x20, 0x6A, 0x2F, 0xF5, 0x47, 0xA2, 0x4E, 0xEC, -0x52, 0x2C, 0x10, 0xF0, 0x24, 0x6A, 0x79, 0xF4, -0x48, 0x9A, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A, +0x20, 0x6A, 0x4F, 0xF7, 0x55, 0xA2, 0x4E, 0xEC, +0x52, 0x2C, 0x10, 0xF0, 0x24, 0x6A, 0x7E, 0xF0, +0x44, 0x9A, 0x60, 0x9A, 0x30, 0xF0, 0x20, 0x6A, 0x70, 0x33, 0x00, 0xF5, 0x62, 0x33, 0x48, 0xF5, 0x68, 0xCA, 0x45, 0x10, 0x30, 0xF0, 0x20, 0x6C, 0xC0, 0xF1, 0x08, 0x4C, 0x9D, 0xE7, 0xE8, 0xF2, @@ -30858,71 +45774,71 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x00, 0x6C, 0x6C, 0xEC, 0x02, 0xF0, 0x00, 0x74, 0x01, 0x60, 0x24, 0x2C, 0x1F, 0xF7, 0x00, 0x6A, 0x6C, 0xEA, 0x02, 0xF0, 0x00, 0x72, 0x01, 0x60, -0x07, 0x2A, 0x10, 0xF0, 0x24, 0x6A, 0x79, 0xF4, -0x80, 0x9A, 0x91, 0xE3, 0x60, 0xA4, 0x0B, 0x10, -0x10, 0xF0, 0x24, 0x6A, 0x79, 0xF4, 0x80, 0x9A, -0x10, 0xF0, 0x24, 0x6A, 0x79, 0xF4, 0x44, 0x9A, +0x07, 0x2A, 0x10, 0xF0, 0x24, 0x6A, 0x5E, 0xF0, +0x9C, 0x9A, 0x91, 0xE3, 0x60, 0xA4, 0x0B, 0x10, +0x10, 0xF0, 0x24, 0x6A, 0x5E, 0xF0, 0x9C, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0x7E, 0xF0, 0x40, 0x9A, 0x91, 0xE3, 0x4D, 0xE3, 0x60, 0xA3, 0x00, 0xF6, 0x60, 0x33, 0x01, 0x6A, 0x00, 0xF6, 0x63, 0x33, 0x44, 0xEE, 0x6D, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x40, 0xC4, 0x0D, 0x10, 0x10, 0xF0, 0x24, 0x6C, -0x79, 0xF4, 0x84, 0x9C, 0x8D, 0xE3, 0x80, 0xA3, +0x7E, 0xF0, 0x80, 0x9C, 0x8D, 0xE3, 0x80, 0xA3, 0x00, 0xF6, 0x80, 0x34, 0x00, 0xF6, 0x83, 0x34, 0xAD, 0xEC, 0x4C, 0xEC, 0x80, 0xC3, 0x01, 0x90, 0x01, 0x63, 0x20, 0xE8, 0xFF, 0x6A, 0x4C, 0xEC, 0x05, 0x5C, 0xAC, 0xEA, 0x4B, 0x60, 0x10, 0xF0, -0x24, 0x6B, 0x88, 0x34, 0xF9, 0xF0, 0x00, 0x4B, +0x24, 0x6B, 0x88, 0x34, 0xBD, 0xF4, 0x08, 0x4B, 0x8D, 0xE3, 0x60, 0x9B, 0x00, 0xEB, 0x05, 0x22, -0x10, 0xF0, 0x24, 0x6A, 0x79, 0xF4, 0x6C, 0x9A, -0x2D, 0x10, 0x10, 0xF0, 0x24, 0x6A, 0x79, 0xF4, -0x6C, 0x9A, 0x20, 0x10, 0x05, 0x22, 0x10, 0xF0, -0x24, 0x6A, 0x79, 0xF4, 0x70, 0x9A, 0x22, 0x10, -0x10, 0xF0, 0x24, 0x6A, 0x79, 0xF4, 0x70, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0x7E, 0xF0, 0x68, 0x9A, +0x2D, 0x10, 0x10, 0xF0, 0x24, 0x6A, 0x7E, 0xF0, +0x68, 0x9A, 0x20, 0x10, 0x05, 0x22, 0x10, 0xF0, +0x24, 0x6A, 0x7E, 0xF0, 0x6C, 0x9A, 0x22, 0x10, +0x10, 0xF0, 0x24, 0x6A, 0x7E, 0xF0, 0x6C, 0x9A, 0x15, 0x10, 0x05, 0x22, 0x10, 0xF0, 0x24, 0x6A, -0x79, 0xF4, 0x74, 0x9A, 0x17, 0x10, 0x10, 0xF0, -0x24, 0x6A, 0x79, 0xF4, 0x74, 0x9A, 0x0A, 0x10, -0x05, 0x22, 0x10, 0xF0, 0x24, 0x6A, 0x79, 0xF4, -0x78, 0x9A, 0x0C, 0x10, 0x10, 0xF0, 0x24, 0x6A, -0x79, 0xF4, 0x78, 0x9A, 0x80, 0xA3, 0xF7, 0x6A, +0x7E, 0xF0, 0x70, 0x9A, 0x17, 0x10, 0x10, 0xF0, +0x24, 0x6A, 0x7E, 0xF0, 0x70, 0x9A, 0x0A, 0x10, +0x05, 0x22, 0x10, 0xF0, 0x24, 0x6A, 0x7E, 0xF0, +0x74, 0x9A, 0x0C, 0x10, 0x10, 0xF0, 0x24, 0x6A, +0x7E, 0xF0, 0x74, 0x9A, 0x80, 0xA3, 0xF7, 0x6A, 0x0A, 0x10, 0x0C, 0x22, 0x10, 0xF0, 0x24, 0x6A, -0x79, 0xF4, 0x7C, 0x9A, 0x40, 0xA3, 0xFF, 0x6C, +0x7E, 0xF0, 0x78, 0x9A, 0x40, 0xA3, 0xFF, 0x6C, 0x08, 0x6D, 0x8C, 0xEA, 0xAD, 0xEA, 0x8C, 0xEA, 0x40, 0xC3, 0x20, 0xE8, 0x10, 0xF0, 0x24, 0x6A, -0x79, 0xF4, 0x7C, 0x9A, 0xF7, 0x6A, 0x80, 0xA3, +0x7E, 0xF0, 0x78, 0x9A, 0xF7, 0x6A, 0x80, 0xA3, 0x8C, 0xEA, 0x40, 0xC3, 0x20, 0xE8, 0x00, 0x65, 0xFF, 0x6A, 0x4C, 0xEC, 0x01, 0x6B, 0xAC, 0xEA, 0x6E, 0xEA, 0x01, 0x5A, 0x58, 0x67, 0x05, 0x5C, 0x48, 0x32, 0x08, 0x60, 0x10, 0xF0, 0x24, 0x6B, -0x88, 0x34, 0xF9, 0xF0, 0x14, 0x4B, 0x8D, 0xE3, +0x88, 0x34, 0xBD, 0xF4, 0x1C, 0x4B, 0x8D, 0xE3, 0x60, 0x9B, 0x00, 0xEB, 0x01, 0x6A, 0x4B, 0xEA, -0x20, 0xE8, 0x10, 0xF0, 0x24, 0x6B, 0x79, 0xF4, -0x88, 0x9B, 0x10, 0xF0, 0x24, 0x6D, 0x99, 0xF4, -0xA0, 0x9D, 0x60, 0x9C, 0xAC, 0xEB, 0x1E, 0x10, -0x10, 0xF0, 0x24, 0x6B, 0x79, 0xF4, 0x88, 0x9B, -0x10, 0xF0, 0x24, 0x6D, 0x99, 0xF4, 0xA0, 0x9D, +0x20, 0xE8, 0x10, 0xF0, 0x24, 0x6B, 0x7E, 0xF0, +0x84, 0x9B, 0x10, 0xF0, 0x24, 0x6D, 0x7E, 0xF0, +0xBC, 0x9D, 0x60, 0x9C, 0xAC, 0xEB, 0x1E, 0x10, +0x10, 0xF0, 0x24, 0x6B, 0x7E, 0xF0, 0x84, 0x9B, +0x10, 0xF0, 0x24, 0x6D, 0x7E, 0xF0, 0xBC, 0x9D, 0x60, 0x9C, 0xAC, 0xEB, 0x10, 0xF0, 0x24, 0x6D, -0x99, 0xF4, 0xAC, 0x9D, 0x0E, 0x10, 0x10, 0xF0, -0x24, 0x6B, 0x79, 0xF4, 0x88, 0x9B, 0x10, 0xF0, -0x24, 0x6D, 0x99, 0xF4, 0xA0, 0x9D, 0x60, 0x9C, -0xAC, 0xEB, 0x10, 0xF0, 0x24, 0x6D, 0x99, 0xF4, -0xB0, 0x9D, 0xAD, 0xEB, 0x60, 0xDC, 0x60, 0xF5, +0x9E, 0xF0, 0xA8, 0x9D, 0x0E, 0x10, 0x10, 0xF0, +0x24, 0x6B, 0x7E, 0xF0, 0x84, 0x9B, 0x10, 0xF0, +0x24, 0x6D, 0x7E, 0xF0, 0xBC, 0x9D, 0x60, 0x9C, +0xAC, 0xEB, 0x10, 0xF0, 0x24, 0x6D, 0x9E, 0xF0, +0xAC, 0x9D, 0xAD, 0xEB, 0x60, 0xDC, 0x60, 0xF5, 0x60, 0x42, 0x1F, 0xF7, 0x00, 0x6C, 0x8C, 0xEB, 0x02, 0xF0, 0x00, 0x73, 0x10, 0x61, 0x2E, 0x10, -0x10, 0xF0, 0x24, 0x6B, 0x79, 0xF4, 0x88, 0x9B, -0x10, 0xF0, 0x24, 0x6D, 0x99, 0xF4, 0xA0, 0x9D, +0x10, 0xF0, 0x24, 0x6B, 0x7E, 0xF0, 0x84, 0x9B, +0x10, 0xF0, 0x24, 0x6D, 0x7E, 0xF0, 0xBC, 0x9D, 0x60, 0x9C, 0xAC, 0xEB, 0x10, 0xF0, 0x24, 0x6D, -0x99, 0xF4, 0xB4, 0x9D, 0xE6, 0x17, 0x1E, 0x23, -0x10, 0xF0, 0x24, 0x6B, 0x99, 0xF4, 0x68, 0x9B, -0x1D, 0x10, 0x10, 0xF0, 0x24, 0x6B, 0x79, 0xF4, -0x88, 0x9B, 0x10, 0xF0, 0x24, 0x6D, 0x99, 0xF4, -0xA0, 0x9D, 0x60, 0x9C, 0xAC, 0xEB, 0x10, 0xF0, -0x24, 0x6D, 0x99, 0xF4, 0xB8, 0x9D, 0xAD, 0xEB, +0x9E, 0xF0, 0xB0, 0x9D, 0xE6, 0x17, 0x1E, 0x23, +0x10, 0xF0, 0x24, 0x6B, 0x9E, 0xF0, 0x64, 0x9B, +0x1D, 0x10, 0x10, 0xF0, 0x24, 0x6B, 0x7E, 0xF0, +0x84, 0x9B, 0x10, 0xF0, 0x24, 0x6D, 0x7E, 0xF0, +0xBC, 0x9D, 0x60, 0x9C, 0xAC, 0xEB, 0x10, 0xF0, +0x24, 0x6D, 0x9E, 0xF0, 0xB4, 0x9D, 0xAD, 0xEB, 0x60, 0xDC, 0x60, 0xF5, 0x60, 0x42, 0x1F, 0xF7, 0x00, 0x6C, 0x8C, 0xEB, 0x02, 0xF0, 0x00, 0x73, 0x01, 0x60, 0x07, 0x2B, 0x10, 0xF0, 0x24, 0x6B, -0x99, 0xF4, 0x64, 0x9B, 0x69, 0xE2, 0x40, 0x9A, -0x20, 0xE8, 0x10, 0xF0, 0x24, 0x6B, 0x99, 0xF4, -0x68, 0x9B, 0x69, 0xE2, 0x40, 0x9A, 0x20, 0xE8, +0x9E, 0xF0, 0x60, 0x9B, 0x69, 0xE2, 0x40, 0x9A, +0x20, 0xE8, 0x10, 0xF0, 0x24, 0x6B, 0x9E, 0xF0, +0x64, 0x9B, 0x69, 0xE2, 0x40, 0x9A, 0x20, 0xE8, 0xFF, 0x6A, 0x4C, 0xEC, 0x01, 0x74, 0xAC, 0xEA, 0x13, 0x60, 0x03, 0x24, 0x02, 0x74, 0x15, 0x60, 0x18, 0x10, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, @@ -30931,25 +45847,25 @@ u8 array_mp_8821c_fw_wowlan[] = { 0xAD, 0xEA, 0x68, 0xF3, 0x59, 0xC3, 0x09, 0x10, 0x30, 0xF0, 0x20, 0x6B, 0x48, 0xF5, 0x44, 0xC3, 0x04, 0x10, 0x30, 0xF0, 0x20, 0x6B, 0x48, 0xF5, -0x40, 0xC3, 0x10, 0xF0, 0x24, 0x6A, 0x99, 0xF4, -0x5C, 0x9A, 0x60, 0xA2, 0x10, 0x6A, 0x6C, 0xEA, +0x40, 0xC3, 0x10, 0xF0, 0x24, 0x6A, 0x9E, 0xF0, +0x58, 0x9A, 0x60, 0xA2, 0x10, 0x6A, 0x6C, 0xEA, 0x24, 0x22, 0x02, 0x5C, 0x03, 0x61, 0x02, 0x74, 0x17, 0x60, 0x20, 0xE8, 0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x68, 0xF3, 0x99, 0xA3, 0x01, 0x6A, 0x8C, 0xEA, 0x68, 0xF3, 0x9C, 0xA3, 0x7F, 0x6B, 0x5C, 0x32, 0x8C, 0xEB, 0x6D, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, 0x10, 0xF0, 0x24, 0x6B, -0xB9, 0xF4, 0x60, 0x9B, 0x40, 0xC3, 0x20, 0xE8, +0x9E, 0xF0, 0x7C, 0x9B, 0x40, 0xC3, 0x20, 0xE8, 0x30, 0xF0, 0x20, 0x6A, 0x48, 0xF5, 0x60, 0xA2, -0x10, 0xF0, 0x24, 0x6A, 0xB9, 0xF4, 0x44, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0xBE, 0xF0, 0x40, 0x9A, 0x60, 0xC2, 0x20, 0xE8, 0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, 0x4E, 0xF2, 0x4C, 0x9A, -0x30, 0xF0, 0x20, 0x6C, 0x2F, 0xF5, 0x06, 0x4C, +0x30, 0xF0, 0x20, 0x6C, 0x4F, 0xF7, 0x14, 0x4C, 0x00, 0x6D, 0x07, 0x6E, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x10, 0xF0, 0x24, 0x6A, -0xB9, 0xF4, 0x48, 0x9A, 0x60, 0xA2, 0xFF, 0x6A, +0xBE, 0xF0, 0x44, 0x9A, 0x60, 0xA2, 0xFF, 0x6A, 0x6C, 0xEA, 0xFF, 0x72, 0x00, 0x6A, 0x0B, 0x61, -0x10, 0xF0, 0x24, 0x6A, 0xB9, 0xF4, 0x4C, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0xBE, 0xF0, 0x48, 0x9A, 0x60, 0xA2, 0x07, 0x6A, 0x6C, 0xEA, 0x07, 0x6B, 0x6E, 0xEA, 0x01, 0x5A, 0x58, 0x67, 0x20, 0xE8, 0xFF, 0x6A, 0x4C, 0xEC, 0x01, 0x74, 0xAC, 0xEA, @@ -30964,16 +45880,13 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x62, 0xA2, 0x68, 0xF3, 0x99, 0xA2, 0x88, 0xF3, 0x63, 0xC2, 0x40, 0x6B, 0x8D, 0xEB, 0x68, 0xF3, 0x79, 0xC2, 0x20, 0xE8, 0xFD, 0x63, 0x05, 0x62, -0x00, 0x18, 0xD7, 0xCA, 0x01, 0x72, 0x00, 0x6A, -0x19, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, -0x08, 0x4A, 0x68, 0xF3, 0xB9, 0xA2, 0x04, 0x6B, -0xFF, 0x6C, 0xAC, 0xEB, 0x0B, 0x23, 0x10, 0xF0, -0x24, 0x6A, 0xB9, 0xF4, 0x70, 0x9A, 0x40, 0xA3, -0x8C, 0xEA, 0x01, 0x4A, 0x8C, 0xEA, 0x40, 0xC3, -0x00, 0x6A, 0x04, 0x10, 0x68, 0xF3, 0x58, 0xA2, -0x05, 0x5A, 0x58, 0x67, 0x05, 0x97, 0x03, 0x63, -0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, -0x00, 0x18, 0xD7, 0xCA, 0x01, 0x72, 0x1C, 0x61, +0x00, 0x18, 0x31, 0xCB, 0x01, 0x72, 0x0E, 0x61, +0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, +0x68, 0xF3, 0x99, 0xA2, 0x04, 0x6B, 0x8C, 0xEB, +0x05, 0x2B, 0x68, 0xF3, 0x58, 0xA2, 0x05, 0x5A, +0x58, 0x67, 0x01, 0x10, 0x00, 0x6A, 0x05, 0x97, +0x03, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, +0x00, 0x18, 0x31, 0xCB, 0x01, 0x72, 0x1C, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x68, 0xF3, 0x9D, 0xA2, 0x03, 0x6B, 0x8C, 0xEB, 0x13, 0x2B, 0x68, 0xF3, 0x78, 0xA2, 0x10, 0x2B, @@ -30982,86 +45895,56 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x20, 0x6B, 0x8C, 0xEB, 0x05, 0x23, 0xE8, 0xF3, 0x52, 0xA2, 0x01, 0x5A, 0x58, 0x67, 0x01, 0x10, 0x00, 0x6A, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, -0xFD, 0x63, 0x05, 0x62, 0x10, 0xF0, 0x24, 0x6A, -0xB9, 0xF4, 0x54, 0x9A, 0x40, 0xA2, 0x2A, 0x2A, -0x30, 0xF0, 0x20, 0x6A, 0xC8, 0xF5, 0x69, 0xA2, -0x01, 0x6A, 0x6C, 0xEA, 0xFF, 0x6B, 0x6C, 0xEA, -0x21, 0x2A, 0x10, 0xF0, 0x24, 0x6A, 0xB9, 0xF4, -0x58, 0x9A, 0x60, 0xA2, 0x02, 0x6A, 0x6C, 0xEA, -0x19, 0x22, 0x10, 0xF0, 0x24, 0x6A, 0xB9, 0xF4, -0x5C, 0x9A, 0x60, 0xAA, 0x02, 0xF0, 0x00, 0x6A, -0x6C, 0xEA, 0x10, 0x2A, 0x00, 0x18, 0xD7, 0xCA, -0x01, 0x72, 0x01, 0x6A, 0x0C, 0x60, 0x10, 0xF0, -0x24, 0x6A, 0xD9, 0xF4, 0x60, 0x9A, 0x10, 0xF0, -0x24, 0x6C, 0xD9, 0xF4, 0x84, 0x9C, 0x40, 0x9B, -0x8D, 0xEA, 0x40, 0xDB, 0x00, 0x6A, 0x05, 0x97, -0x03, 0x63, 0x00, 0xEF, 0xFC, 0x63, 0x07, 0x62, -0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x20, 0x6B, -0xFF, 0x69, 0x30, 0xF0, 0x20, 0x6A, 0x8C, 0xE9, -0x6E, 0xF5, 0x58, 0x9A, 0x2F, 0xF5, 0x87, 0xA3, -0x40, 0xEA, 0x01, 0x72, 0x29, 0x61, 0x30, 0xF0, -0x20, 0x68, 0xC0, 0xF1, 0x08, 0x48, 0x68, 0xF3, -0x7A, 0xA0, 0x09, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, -0x68, 0xF3, 0x5A, 0xC0, 0x30, 0xF0, 0x20, 0x6A, -0x6E, 0xF2, 0x58, 0x9A, 0xFF, 0x6C, 0x6F, 0x6D, -0x2C, 0x6E, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A, -0x2E, 0xF4, 0x50, 0x9A, 0xC8, 0xF2, 0x9F, 0xA0, -0x01, 0x6D, 0x08, 0x6E, 0xF1, 0x67, 0x40, 0xEA, -0x01, 0x72, 0x0A, 0x61, 0x68, 0xF3, 0x7A, 0xA0, -0x02, 0x6A, 0x01, 0x6C, 0x6D, 0xEA, 0x0E, 0x6D, -0x68, 0xF3, 0x5A, 0xC0, 0x00, 0x18, 0xA8, 0xCA, -0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, -0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, +0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, +0x8F, 0xF5, 0x48, 0xA2, 0x02, 0x6B, 0x6C, 0xEA, +0x16, 0x2A, 0x10, 0xF0, 0x24, 0x6A, 0xBE, 0xF0, +0x4C, 0x9A, 0x40, 0xA2, 0x29, 0x2A, 0x30, 0xF0, +0x20, 0x6A, 0xC8, 0xF5, 0x89, 0xA2, 0x01, 0x6A, +0x8C, 0xEA, 0xFF, 0x6C, 0x8C, 0xEA, 0x20, 0x2A, +0x10, 0xF0, 0x24, 0x6A, 0xBE, 0xF0, 0x50, 0x9A, +0x40, 0xA2, 0x4C, 0xEB, 0x19, 0x23, 0x10, 0xF0, +0x24, 0x6A, 0xBE, 0xF0, 0x54, 0x9A, 0x60, 0xAA, +0x02, 0xF0, 0x00, 0x6A, 0x6C, 0xEA, 0x10, 0x2A, +0x00, 0x18, 0x31, 0xCB, 0x01, 0x72, 0x01, 0x6A, +0x0C, 0x60, 0x10, 0xF0, 0x24, 0x6A, 0xBE, 0xF0, +0x78, 0x9A, 0x10, 0xF0, 0x24, 0x6C, 0xBE, 0xF0, +0x9C, 0x9C, 0x40, 0x9B, 0x8D, 0xEA, 0x40, 0xDB, +0x00, 0x6A, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, +0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, +0x30, 0xF0, 0x20, 0x6B, 0xFF, 0x69, 0x30, 0xF0, +0x20, 0x6A, 0x8C, 0xE9, 0x6E, 0xF5, 0x58, 0x9A, +0x4F, 0xF7, 0x95, 0xA3, 0x40, 0xEA, 0x01, 0x72, +0x29, 0x61, 0x30, 0xF0, 0x20, 0x68, 0xC0, 0xF1, +0x08, 0x48, 0x68, 0xF3, 0x7A, 0xA0, 0x09, 0x6A, +0x4B, 0xEA, 0x6C, 0xEA, 0x68, 0xF3, 0x5A, 0xC0, 0x30, 0xF0, 0x20, 0x6A, 0x6E, 0xF2, 0x58, 0x9A, -0x2E, 0x6E, 0xFF, 0x6C, 0x6F, 0x6D, 0x40, 0xEA, -0x01, 0x6C, 0x02, 0x6D, 0x00, 0x18, 0xA8, 0xCA, +0xFF, 0x6C, 0x6F, 0x6D, 0x2C, 0x6E, 0x40, 0xEA, +0x30, 0xF0, 0x20, 0x6A, 0x2E, 0xF4, 0x50, 0x9A, +0xC8, 0xF2, 0x9F, 0xA0, 0x01, 0x6D, 0x08, 0x6E, +0xF1, 0x67, 0x40, 0xEA, 0x01, 0x72, 0x0A, 0x61, +0x68, 0xF3, 0x7A, 0xA0, 0x02, 0x6A, 0x01, 0x6C, +0x6D, 0xEA, 0x0E, 0x6D, 0x68, 0xF3, 0x5A, 0xC0, +0x00, 0x18, 0x02, 0xCB, 0x07, 0x97, 0x06, 0x91, +0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0x00, 0x65, +0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6A, +0x6E, 0xF2, 0x58, 0x9A, 0x2E, 0x6E, 0xFF, 0x6C, +0x6F, 0x6D, 0x40, 0xEA, 0x01, 0x6C, 0x02, 0x6D, +0x00, 0x18, 0x02, 0xCB, 0x05, 0x97, 0x03, 0x63, +0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, +0x30, 0xF0, 0x20, 0x6B, 0xFF, 0x6E, 0x30, 0xF0, +0x20, 0x6A, 0x8C, 0xEE, 0x2E, 0xF4, 0x48, 0x9A, +0x48, 0xF5, 0x80, 0xA3, 0x01, 0x6D, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, -0xFD, 0x63, 0x05, 0x62, 0x30, 0xF0, 0x20, 0x6B, -0xFF, 0x6E, 0x30, 0xF0, 0x20, 0x6A, 0x8C, 0xEE, -0x2E, 0xF4, 0x48, 0x9A, 0x48, 0xF5, 0x80, 0xA3, -0x01, 0x6D, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, -0x00, 0xEF, 0x00, 0x65, 0xFC, 0x63, 0x07, 0x62, -0x06, 0xD1, 0x05, 0xD0, 0x30, 0xF0, 0x20, 0x68, -0xC0, 0xF1, 0x08, 0x48, 0x68, 0xF3, 0x7D, 0xA0, -0x10, 0x6A, 0xFF, 0x69, 0x6D, 0xEA, 0x88, 0xF3, -0x65, 0xA0, 0x8C, 0xE9, 0x68, 0xF3, 0x5D, 0xC0, -0x02, 0x5B, 0x10, 0x60, 0x88, 0xF3, 0xC4, 0xA0, -0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF2, 0x50, 0x9A, -0xFF, 0x6C, 0xD9, 0xE3, 0x55, 0x4C, 0x00, 0x6D, -0x40, 0xEA, 0x88, 0xF3, 0x65, 0xA0, 0x88, 0xF3, -0x44, 0xA0, 0x17, 0x10, 0x03, 0x6A, 0x58, 0xEB, -0x88, 0xF3, 0xC4, 0xA0, 0x30, 0xF0, 0x20, 0x6A, -0xAE, 0xF2, 0x50, 0x9A, 0xFE, 0x4E, 0xFF, 0x6C, -0x55, 0x4C, 0x00, 0x6D, 0x12, 0xEB, 0x79, 0xE6, -0x40, 0xEA, 0x88, 0xF3, 0x45, 0xA0, 0x03, 0x6C, -0x88, 0xF3, 0x64, 0xA0, 0x98, 0xEA, 0xFE, 0x4B, -0x12, 0xEA, 0x49, 0xE3, 0x88, 0xF3, 0x57, 0xC0, -0x30, 0xF0, 0x20, 0x6A, 0x48, 0xF5, 0x44, 0xA2, -0x04, 0x6B, 0x6C, 0xEA, 0x08, 0x2A, 0x30, 0xF0, -0x20, 0x6A, 0x2E, 0xF4, 0x48, 0x9A, 0x83, 0x67, -0x01, 0x6D, 0xD1, 0x67, 0x40, 0xEA, 0x07, 0x97, -0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, -0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, -0x30, 0xF0, 0x20, 0x68, 0xC0, 0xF1, 0x08, 0x48, -0x68, 0xF3, 0x74, 0xA0, 0x00, 0x6A, 0xE8, 0xF3, -0x42, 0xC0, 0x7F, 0x6A, 0xFF, 0x69, 0x6C, 0xEA, -0x2C, 0xEC, 0x2C, 0xEA, 0x04, 0xD4, 0x24, 0x22, -0x30, 0xF0, 0x20, 0x6B, 0x30, 0xF0, 0x20, 0x6A, -0x6E, 0xF5, 0x58, 0x9A, 0x2F, 0xF5, 0x87, 0xA3, -0x40, 0xEA, 0x01, 0x72, 0x19, 0x61, 0x04, 0x94, -0x00, 0x6D, 0x00, 0x18, 0x66, 0xCA, 0xC8, 0xF3, -0x54, 0xD8, 0x68, 0xF3, 0x5A, 0xA0, 0x68, 0xF3, -0x95, 0xA0, 0x20, 0x6B, 0x4D, 0xEB, 0x0F, 0x6A, -0x8C, 0xEA, 0x2C, 0xEA, 0x68, 0xF3, 0x7A, 0xC0, -0x04, 0x22, 0x10, 0x6A, 0x6C, 0xEA, 0x2C, 0xEA, -0x03, 0x2A, 0x04, 0x94, 0x00, 0x18, 0x6B, 0xCB, -0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, -0x00, 0xEF, 0x00, 0x65, 0xFF, 0x63, 0x01, 0xD0, -0x30, 0xF0, 0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, -0x68, 0xF3, 0x1A, 0xA3, 0x20, 0x6F, 0xFF, 0x6A, -0x0C, 0xEF, 0x4C, 0xEF, 0x4C, 0xEC, 0x4C, 0xED, -0x4C, 0xEE, 0x80, 0xF0, 0x04, 0x2F, 0x68, 0xF3, -0x19, 0xA3, 0x01, 0x6F, 0x0C, 0xEF, 0x4C, 0xEF, +0xFF, 0x63, 0x01, 0xD1, 0x00, 0xD0, 0x10, 0xF0, +0x24, 0x6B, 0x30, 0xF0, 0x20, 0x69, 0xDE, 0xF0, +0xE0, 0x9B, 0xCF, 0xF4, 0x60, 0x99, 0xFF, 0x6A, +0x4C, 0xEC, 0xEC, 0xEB, 0xEE, 0xEB, 0x4C, 0xED, +0x4C, 0xEE, 0x80, 0xF0, 0x1E, 0x23, 0x30, 0xF0, +0x20, 0x6B, 0xC0, 0xF1, 0x08, 0x4B, 0x68, 0xF3, +0x1A, 0xA3, 0x20, 0x6F, 0x0C, 0xEF, 0x4C, 0xEF, +0x80, 0xF0, 0x0F, 0x2F, 0xCF, 0xF4, 0x00, 0xA1, +0x01, 0x6F, 0xEC, 0xE8, 0x4C, 0xE8, 0x61, 0x28, +0x68, 0xF3, 0x19, 0xA3, 0x0C, 0xEF, 0x4C, 0xEF, 0x09, 0x27, 0x88, 0xF3, 0x5B, 0xA3, 0xE4, 0x42, 0x03, 0x4A, 0x88, 0xF3, 0xF3, 0xC3, 0x88, 0xF3, 0x52, 0xC3, 0x08, 0x10, 0x05, 0x6F, 0x88, 0xF3, @@ -31081,21 +45964,23 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x76, 0xA2, 0x88, 0xF3, 0x84, 0xA2, 0x23, 0x4B, 0x82, 0xEB, 0x02, 0x60, 0x88, 0xF3, 0x64, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, -0x88, 0xF3, 0x76, 0xA2, 0x88, 0xF3, 0x6A, 0xCA, -0x10, 0xF0, 0x24, 0x6B, 0xD9, 0xF4, 0x68, 0x9B, -0x80, 0xA3, 0x05, 0x24, 0x80, 0xA3, 0xFF, 0x6B, -0x8C, 0xEB, 0x88, 0xF3, 0x6A, 0xCA, 0x30, 0xF0, -0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x10, 0xF0, -0x24, 0x6B, 0x88, 0xF3, 0xAA, 0xA2, 0xD9, 0xF4, -0x6C, 0x9B, 0xFF, 0x6C, 0xA0, 0xC3, 0x10, 0xF0, -0x24, 0x6B, 0xD9, 0xF4, 0x70, 0x9B, 0x88, 0xF3, -0x4A, 0xAA, 0xA0, 0xA3, 0x8C, 0xED, 0x4E, 0xED, -0x02, 0x25, 0x4C, 0xEC, 0x80, 0xC3, 0x30, 0xF0, -0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x68, 0xF3, -0x9A, 0xA2, 0x41, 0x6B, 0x6B, 0xEB, 0x8C, 0xEB, -0x68, 0xF3, 0x7A, 0xC2, 0x04, 0x10, 0x40, 0x6A, -0x0D, 0xEA, 0x68, 0xF3, 0x5A, 0xC3, 0x01, 0x90, -0x01, 0x63, 0x20, 0xE8, 0x30, 0xF0, 0x20, 0x6A, +0x88, 0xF3, 0x76, 0xA2, 0x68, 0xF3, 0x97, 0xA2, +0x88, 0xF3, 0x6A, 0xCA, 0x18, 0x6B, 0x8C, 0xEB, +0x10, 0x73, 0x07, 0x61, 0xC8, 0xF3, 0x79, 0xA2, +0x03, 0x6C, 0x76, 0x33, 0x8C, 0xEB, 0x88, 0xF3, +0x64, 0xC2, 0x10, 0xF0, 0x24, 0x6A, 0xDE, 0xF0, +0x44, 0x9A, 0x60, 0xA2, 0x07, 0x23, 0x60, 0xA2, +0xFF, 0x6A, 0x4C, 0xEB, 0x30, 0xF0, 0x20, 0x6A, +0x48, 0xF5, 0x72, 0xCA, 0x10, 0xF0, 0x24, 0x6A, +0xDE, 0xF0, 0x48, 0x9A, 0x30, 0xF0, 0x20, 0x6C, +0x48, 0xF5, 0x92, 0xAC, 0xA0, 0xA2, 0xFF, 0x6B, +0x6C, 0xED, 0x8E, 0xED, 0x02, 0x25, 0x8C, 0xEB, +0x60, 0xC2, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, +0x08, 0x4A, 0x68, 0xF3, 0x9A, 0xA2, 0x41, 0x6B, +0x6B, 0xEB, 0x8C, 0xEB, 0x68, 0xF3, 0x7A, 0xC2, +0x04, 0x10, 0x40, 0x6A, 0x0D, 0xEA, 0x68, 0xF3, +0x5A, 0xC3, 0x01, 0x91, 0x00, 0x90, 0x01, 0x63, +0x20, 0xE8, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x04, 0x6B, 0xC8, 0xF3, 0x7C, 0xC2, 0x03, 0x6B, 0xC8, 0xF3, 0x7D, 0xC2, 0x64, 0x6B, 0xC8, 0xF3, 0x7E, 0xCA, 0x05, 0x6B, @@ -31111,7 +45996,7 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x01, 0x4C, 0x88, 0xF3, 0x90, 0xC2, 0x88, 0xF3, 0x84, 0xA2, 0xFE, 0x4C, 0x12, 0xEB, 0x6D, 0xE4, 0x88, 0xF3, 0x77, 0xC2, 0x88, 0xF3, 0x90, 0xA2, -0x88, 0xF3, 0xD7, 0xA2, 0x00, 0x18, 0xB3, 0xCB, +0x88, 0xF3, 0xD7, 0xA2, 0x00, 0x18, 0xC2, 0xCB, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0x00, 0x65, 0x30, 0xF0, 0x20, 0x6B, 0x68, 0xF5, 0x04, 0x4B, 0xFF, 0x6A, 0xA7, 0x43, 0x8C, 0xEA, 0x26, 0x4D, @@ -31122,269 +46007,322 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x01, 0x6C, 0x8E, 0xEA, 0x05, 0x2A, 0x2D, 0x6C, 0x88, 0xF3, 0x99, 0xC3, 0x88, 0xF3, 0x5A, 0xC3, 0x20, 0xE8, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, -0x04, 0xD0, 0xFF, 0x68, 0x0C, 0xEC, 0x00, 0x6D, -0x00, 0x18, 0x66, 0xCA, 0x30, 0xF0, 0x20, 0x6B, -0xC0, 0xF1, 0x08, 0x4B, 0xC8, 0xF3, 0x94, 0x9B, -0xC8, 0xF3, 0x50, 0xDB, 0x83, 0xEA, 0x31, 0x61, -0x68, 0xF3, 0xD9, 0xA3, 0x01, 0x6D, 0xCC, 0xED, -0x0C, 0xED, 0x0E, 0x25, 0x88, 0xF3, 0xDB, 0xA3, -0x88, 0xF3, 0xB6, 0xA3, 0x93, 0xE2, 0x0E, 0x4E, -0xBB, 0xE6, 0xC8, 0xF3, 0xBC, 0xA3, 0x82, 0x34, -0x8A, 0x34, 0xAF, 0xE6, 0x89, 0xE3, 0x0B, 0x10, -0xC8, 0xF3, 0xDD, 0xA3, 0x88, 0xF3, 0xB6, 0xA3, -0x8B, 0xE2, 0xCB, 0xEE, 0xAF, 0xE6, 0x42, 0x32, -0x0A, 0x4B, 0x4A, 0x32, 0x49, 0xE3, 0x0C, 0xEA, -0x2D, 0x5A, 0x0F, 0x60, 0x30, 0xF0, 0x20, 0x6B, -0xC0, 0xF1, 0x08, 0x4B, 0x69, 0xE2, 0x88, 0xF3, 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0x55, 0xE5, +0x40, 0x9D, 0x4D, 0xEE, 0xC0, 0xDD, 0x01, 0x90, +0x01, 0x63, 0x20, 0xE8, 0xFD, 0x63, 0x05, 0x62, +0x10, 0xF0, 0x24, 0x6A, 0x7E, 0xF1, 0x50, 0x9A, 0xFF, 0x6B, 0x40, 0xA2, 0x6C, 0xEA, 0x52, 0x32, 0x6C, 0xEA, 0x11, 0x2A, 0x30, 0xF0, 0x20, 0x6B, 0x30, 0xF0, 0x20, 0x6A, 0x6E, 0xF2, 0x5C, 0x9A, @@ -31867,581 +46889,850 @@ u8 array_mp_8821c_fw_wowlan[] = { 0xE5, 0x67, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A, 0x8E, 0xF2, 0x5C, 0x9A, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, -0x04, 0xD0, 0x10, 0xF0, 0x24, 0x6E, 0x64, 0x67, -0x85, 0x67, 0x10, 0xF0, 0x24, 0x6D, 0xB9, 0xF5, -0xB0, 0x9D, 0xB9, 0xF5, 0xD4, 0x9E, 0x30, 0xF0, -0x20, 0x68, 0xE0, 0xAD, 0xC0, 0xAE, 0xFF, 0xF7, -0x1F, 0x6D, 0xAC, 0xEF, 0xC0, 0xF1, 0x08, 0x48, -0xCC, 0xED, 0xBB, 0xE7, 0xC8, 0xF2, 0xBF, 0xA0, -0xFF, 0x6A, 0x4C, 0xEE, 0xAE, 0xEE, 0x4C, 0xEB, -0x4C, 0xEC, 0x2C, 0x2E, 0x68, 0xF3, 0x5C, 0xA0, -0x0E, 0x72, 0x10, 0x61, 0x27, 0x2B, 0x68, 0xF3, -0x7A, 0xA0, 0x03, 0x6A, 0x4B, 0xEA, 0x6C, 0xEA, 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0x00, 0x18, 0x55, 0xD5, -0x01, 0x72, 0x33, 0x61, 0x30, 0xF0, 0x20, 0x68, +0x00, 0x18, 0xF0, 0xDA, 0x00, 0x18, 0x3A, 0xD9, +0x01, 0x72, 0x31, 0x61, 0x30, 0xF0, 0x20, 0x68, 0xC0, 0xF1, 0x08, 0x48, 0x08, 0xF4, 0x50, 0xA0, 0x01, 0x4A, 0x08, 0xF4, 0x50, 0xC0, 0x30, 0xF0, 0x20, 0x6A, 0xEE, 0xF4, 0x5C, 0x9A, 0x40, 0xEA, @@ -33186,190 +48706,149 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x01, 0x6B, 0x02, 0x72, 0x8D, 0xEB, 0x08, 0xF4, 0x61, 0xC0, 0x42, 0x6B, 0x03, 0x60, 0x04, 0x72, 0x06, 0x61, 0x43, 0x6B, 0x10, 0xF0, 0x24, 0x6A, -0xF9, 0xF5, 0x48, 0x9A, 0x60, 0xC2, 0x01, 0x6C, -0x00, 0x18, 0xBF, 0xDA, 0x1F, 0x10, 0x30, 0xF0, -0x20, 0x6A, 0x0E, 0xF5, 0x40, 0x9A, 0x91, 0x67, -0x40, 0xEA, 0x48, 0x92, 0x01, 0x4A, 0x48, 0xD2, -0x48, 0x93, 0xFF, 0x6A, 0x4C, 0xEB, 0x48, 0xD3, -0x0C, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, -0x08, 0x4A, 0xE8, 0xF3, 0x93, 0xA2, 0x02, 0x6B, -0x6B, 0xEB, 0x8C, 0xEB, 0xE8, 0xF3, 0x73, 0xC2, -0x05, 0x10, 0x48, 0x94, 0x4C, 0x95, 0xA3, 0xEC, -0x3F, 0xF6, 0x11, 0x61, 0x10, 0xF0, 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0x10, 0x10, 0xF0, -0x24, 0x6D, 0xD9, 0xF5, 0xB4, 0x9D, 0xB5, 0xE4, +0x24, 0x6D, 0xBE, 0xF1, 0xA4, 0x9D, 0xB5, 0xE4, 0x55, 0xE5, 0xC0, 0xA5, 0x30, 0xF0, 0x20, 0x6D, 0xC0, 0xF1, 0x08, 0x4D, 0xB5, 0xE2, 0x08, 0xF6, 0xC8, 0xC5, 0x01, 0x4A, 0xFF, 0x6D, 0xAC, 0xEA, @@ -33532,32 +49045,32 @@ u8 array_mp_8821c_fw_wowlan[] = { 0xFB, 0x61, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, 0xFF, 0x6A, 0x8C, 0xEA, 0x04, 0x22, 0x00, 0x18, -0x37, 0xDE, 0x00, 0x18, 0xA3, 0xDE, 0x05, 0x97, +0x1E, 0xE3, 0x00, 0x18, 0xA7, 0xE3, 0x05, 0x97, 0x03, 0x63, 0x00, 0xEF, 0xFA, 0x63, 0x0B, 0x62, 0x0A, 0xD1, 0x09, 0xD0, 0x10, 0xF0, 0x24, 0x6A, -0xB9, 0xF6, 0x70, 0x9A, 0xFF, 0x68, 0x20, 0x6C, +0x9E, 0xF2, 0x7C, 0x9A, 0xFF, 0x68, 0x20, 0x6C, 0x40, 0xA3, 0x0C, 0xEA, 0x8D, 0xEA, 0x0C, 0xEA, -0x40, 0xC3, 0x10, 0xF0, 0x24, 0x6A, 0xB9, 0xF5, -0x54, 0x9A, 0x60, 0xAA, 0xE1, 0xF7, 0x1F, 0x6A, +0x40, 0xC3, 0x10, 0xF0, 0x24, 0x6A, 0x7E, 0xF1, +0x58, 0x9A, 0x60, 0xAA, 0xE1, 0xF7, 0x1F, 0x6A, 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0x00, 0x6C, 0x40, 0xEA, 0x04, 0x93, 0x0E, 0xF5, 0x48, 0x99, 0x05, 0x95, 0x89, 0xF0, 0xC6, 0xA3, 0x11, 0x6C, 0x40, 0xEA, -0x10, 0xF0, 0x24, 0x6A, 0xB9, 0xF4, 0x5C, 0x9A, +0x10, 0xF0, 0x24, 0x6A, 0xBE, 0xF0, 0x54, 0x9A, 0xFF, 0x6C, 0xA4, 0x67, 0x40, 0x9A, 0x10, 0xF0, -0x24, 0x6A, 0x19, 0xF5, 0x40, 0x9A, 0x26, 0x6E, +0x24, 0x6A, 0xDE, 0xF0, 0x5C, 0x9A, 0x26, 0x6E, 0x20, 0xA2, 0x0C, 0xE9, 0x30, 0xF0, 0x20, 0x68, 0x6E, 0xF2, 0x58, 0x98, 0x40, 0xEA, 0x30, 0xF0, 0x20, 0x6A, 0xCE, 0xF2, 0x40, 0x9A, 0x40, 0xEA, @@ -33569,40 +49082,72 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x69, 0xF0, 0x74, 0xA2, 0x02, 0x73, 0x07, 0x61, 0x89, 0xF0, 0x86, 0xA2, 0x06, 0x92, 0xFF, 0x6D, 0x4C, 0xED, -0x00, 0x18, 0xE7, 0xD5, 0x30, 0xF0, 0x20, 0x6A, -0x8E, 0xF2, 0x5C, 0x9A, 0x40, 0xEA, 0x30, 0xF0, -0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0xE8, 0xF5, -0x66, 0xAA, 0x01, 0x4B, 0xE8, 0xF5, 0x66, 0xCA, -0x0B, 0x97, 0x0A, 0x91, 0x09, 0x90, 0x06, 0x63, -0x00, 0xEF, 0x00, 0x65, 0xFD, 0x63, 0x05, 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0x9C, 0x9C, 0x40, 0x9B, +0x8D, 0xEA, 0x40, 0xDB, 0x20, 0xE8, 0x80, 0xC3, +0x0B, 0x25, 0x10, 0xF0, 0x24, 0x6B, 0xDE, 0xF2, +0x80, 0x9B, 0x80, 0x6D, 0xAB, 0xED, 0x60, 0xA4, +0x4C, 0xEB, 0xAE, 0xEB, 0x4C, 0xEB, 0x60, 0xC4, 0x20, 0xE8, 0x00, 0x65, 0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, 0xFF, 0xF7, 0x1F, 0x6A, 0x0E, 0x90, 0x24, 0x67, 0x4C, 0xE9, 0x03, 0x6B, @@ -33613,34 +49158,34 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x40, 0xA8, 0x01, 0x4A, 0x40, 0xC8, 0x1F, 0xF7, 0x00, 0x6A, 0x2C, 0xEA, 0x02, 0xF0, 0x00, 0x72, 0x01, 0x60, 0x05, 0x2A, 0x10, 0xF0, 0x24, 0x6A, -0x79, 0xF4, 0x40, 0x9A, 0x04, 0x10, 0x10, 0xF0, -0x24, 0x6A, 0x79, 0xF4, 0x44, 0x9A, 0x49, 0xE1, +0x5E, 0xF0, 0x5C, 0x9A, 0x04, 0x10, 0x10, 0xF0, +0x24, 0x6A, 0x7E, 0xF0, 0x40, 0x9A, 0x49, 0xE1, 0x0B, 0x93, 0x40, 0x9A, 0x6C, 0xEA, 0x0C, 0x93, 0x6E, 0xEA, 0x04, 0x22, 0x40, 0xA8, 0x04, 0x93, 0x63, 0xEA, 0xDC, 0x61, 0x40, 0xA8, 0x04, 0x93, 0x63, 0xEA, 0x58, 0x67, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x00, 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0xD0, 0x01, 0x68, 0x04, 0xEC, 0x04, 0xF7, 0x10, 0x69, 0x13, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0xCE, 0xF4, 0x5C, 0x9A, 0x01, 0x6C, 0xFF, 0x49, 0x40, 0xEA, 0x0B, 0x29, 0x10, 0xF0, -0x24, 0x6A, 0xD9, 0xF4, 0x60, 0x9A, 0x08, 0xF0, +0x24, 0x6A, 0xBE, 0xF0, 0x78, 0x9A, 0x08, 0xF0, 0x00, 0x6C, 0x40, 0x9B, 0x8D, 0xEA, 0x40, 0xDB, 0x00, 0x6A, 0x0B, 0x10, 0x10, 0xF0, 0x24, 0x6A, -0xD9, 0xF6, 0x54, 0x9A, 0x60, 0xAA, 0xFF, 0xF7, +0xDE, 0xF2, 0x50, 0x9A, 0x60, 0xAA, 0xFF, 0xF7, 0x1F, 0x6A, 0x6C, 0xEA, 0x0C, 0xEA, 0xE3, 0x2A, 0x01, 0x6A, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, @@ -33648,1238 +49193,1512 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x0F, 0x91, 0x04, 0xD2, 0x04, 0x93, 0xFF, 0x6A, 0x4C, 0xE8, 0x4C, 0xEB, 0x90, 0x67, 0x0B, 0xD5, 0x0C, 0xD6, 0x0D, 0xD7, 0x04, 0xD3, 0x4C, 0xE9, -0x00, 0x18, 0xD3, 0xDF, 0x80, 0xF0, 0x07, 0x22, +0x00, 0x18, 0x17, 0xE5, 0x80, 0xF0, 0x07, 0x22, 0x06, 0x58, 0x80, 0xF0, 0x04, 0x60, 0x10, 0xF0, -0x24, 0x6A, 0x08, 0x30, 0xD9, 0xF1, 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array_mp_8821c_fw_wowlan[] = { 0xFF, 0x6A, 0x8C, 0xEB, 0x4C, 0xEB, 0x4C, 0xE9, 0x16, 0x23, 0xFF, 0xF6, 0x1F, 0x4A, 0x8C, 0xEA, 0x00, 0x6D, 0x91, 0x67, 0x68, 0xF3, 0x5A, 0xC0, -0x00, 0x18, 0x22, 0xE7, 0x68, 0xF3, 0x9A, 0xA0, +0x00, 0x18, 0x93, 0xEE, 0x68, 0xF3, 0x9A, 0xA0, 0x01, 0x6B, 0x6C, 0xEA, 0xFA, 0x4B, 0x8C, 0xEB, 0x48, 0x32, 0x4D, 0xEB, 0x91, 0x67, 0x68, 0xF3, -0x7A, 0xC0, 0x00, 0x18, 0x62, 0xCB, 0xB1, 0x67, -0x00, 0x6C, 0x00, 0x18, 0xF2, 0xDA, 0x07, 0x97, +0x7A, 0xC0, 0x00, 0x18, 0xB9, 0xCB, 0xB1, 0x67, +0x00, 0x6C, 0x00, 0x18, 0x83, 0xE1, 0x07, 0x97, 0x06, 0x91, 0x05, 0x90, 0x04, 0x63, 0x00, 0xEF, 0xFD, 0x63, 0x05, 0x62, 0x04, 0xD0, 0x00, 0x18, -0x6D, 0xEC, 0x02, 0x67, 0x01, 0x6A, 0x0C, 0xEA, +0xEF, 0xF3, 0x02, 0x67, 0x01, 0x6A, 0x0C, 0xEA, 0x03, 0x22, 0x00, 0x6C, 0x01, 0x6D, 0x02, 0x10, -0x00, 0x6C, 0xA4, 0x67, 0x00, 0x18, 0xA8, 0xCA, +0x00, 0x6C, 0xA4, 0x67, 0x00, 0x18, 0x02, 0xCB, 0x40, 0x6A, 0x0C, 0xEA, 0x0F, 0x22, 0x10, 0xF0, -0x24, 0x6A, 0x5A, 0xF0, 0x4C, 0x9A, 0x60, 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0xF0, 0x24, 0x6B, 0x79, 0xF4, 0x64, 0x9B, +0x10, 0xF0, 0x24, 0x6B, 0x7E, 0xF0, 0x60, 0x9B, 0xFF, 0xF7, 0x1F, 0x6A, 0x8C, 0xEA, 0x69, 0xE2, 0x00, 0x9A, 0x41, 0x45, 0x25, 0x67, 0x08, 0x22, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF4, 0x50, 0x9A, @@ -35001,39 +50820,39 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x04, 0x63, 0x00, 0xEF, 0xFB, 0x63, 0x09, 0x62, 0x08, 0xD1, 0x07, 0xD0, 0xFF, 0xF7, 0x1F, 0x68, 0x41, 0x45, 0x25, 0x67, 0x0C, 0xD6, 0x8C, 0xE8, -0x07, 0x2A, 0x10, 0xF0, 0x24, 0x6A, 0x79, 0xF4, -0x44, 0x9A, 0x41, 0xE0, 0xC0, 0xD8, 0x1A, 0x10, +0x07, 0x2A, 0x10, 0xF0, 0x24, 0x6A, 0x7E, 0xF0, +0x40, 0x9A, 0x41, 0xE0, 0xC0, 0xD8, 0x1A, 0x10, 0x01, 0x6D, 0x90, 0x67, 0xAB, 0xED, 0x00, 0x18, -0x70, 0xEA, 0x04, 0xD2, 0x30, 0xF0, 0x20, 0x6A, +0xD8, 0xF1, 0x04, 0xD2, 0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF4, 0x50, 0x9A, 0x91, 0x67, 0x40, 0xEA, 0x0C, 0x93, 0x64, 0xEA, 0x43, 0x67, 0x04, 0x93, 0x2C, 0xEA, 0x2F, 0xE9, 0x6C, 0xE9, 0x10, 0xF0, -0x24, 0x6B, 0x79, 0xF4, 0x64, 0x9B, 0x2D, 0xEA, +0x24, 0x6B, 0x7E, 0xF0, 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0x2A, 0x90, 0x67, 0xB1, 0x67, 0xC7, 0x67, 0x15, 0x10, 0xB1, 0x67, 0x90, 0x67, -0x00, 0x18, 0x98, 0xEA, 0x04, 0xD2, 0x30, 0xF0, +0x00, 0x18, 0x00, 0xF2, 0x04, 0xD2, 0x30, 0xF0, 0x20, 0x6A, 0x0C, 0x94, 0xAE, 0xF4, 0x50, 0x9A, 0x40, 0xEA, 0x0D, 0x96, 0x90, 0x67, 0xB1, 0x67, 0xC4, 0xEA, 0x0C, 0x92, 0x4C, 0xEE, 0x4F, 0xEB, 0x04, 0x92, 0x4C, 0xEB, 0x6D, 0xEE, 0x00, 0x18, -0xAB, 0xEA, 0x30, 0xF0, 0x20, 0x6A, 0xCE, 0xF4, -0x5C, 0x9A, 0x01, 0x6C, 0x40, 0xEA, 0x09, 0x97, +0x13, 0xF2, 0x30, 0xF0, 0x20, 0x6A, 0xCE, 0xF4, +0x5C, 0x9A, 0x0A, 0x6C, 0x40, 0xEA, 0x09, 0x97, 0x08, 0x91, 0x07, 0x90, 0x05, 0x63, 0x00, 0xEF, 0x30, 0xF0, 0x20, 0x6A, 0xC0, 0xF1, 0x08, 0x4A, 0x81, 0xF4, 0x10, 0x6B, 0x28, 0xF1, 0x78, 0xDA, @@ -35061,24 +50880,24 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x4C, 0xE8, 0x68, 0x40, 0xE4, 0x4B, 0x4C, 0xEB, 0x0D, 0x5B, 0x10, 0x60, 0x30, 0xF0, 0x20, 0x6A, 0x10, 0xF0, 0x24, 0x6B, 0xCE, 0xF4, 0x50, 0x9A, -0x39, 0xF7, 0xB4, 0x9B, 0x61, 0xF0, 0x00, 0x6C, +0x5E, 0xF3, 0xB8, 0x9B, 0x61, 0xF0, 0x00, 0x6C, 0x80, 0xF4, 0x14, 0x6E, 0x40, 0xEA, 0x00, 0x6A, 0x04, 0xD2, 0x40, 0x10, 0x68, 0x40, 0xD6, 0x4B, 0x4C, 0xEB, 0x0F, 0x5B, 0x0D, 0x60, 0x30, 0xF0, 0x20, 0x6A, 0x10, 0xF0, 0x24, 0x6B, 0xCE, 0xF4, -0x50, 0x9A, 0x61, 0xF0, 0x00, 0x6C, 0x39, 0xF7, -0xB4, 0x9B, 0x40, 0xF4, 0x13, 0x6E, 0xEA, 0x17, +0x50, 0x9A, 0x61, 0xF0, 0x00, 0x6C, 0x5E, 0xF3, +0xB8, 0x9B, 0x40, 0xF4, 0x13, 0x6E, 0xEA, 0x17, 0x68, 0x40, 0xA4, 0x4B, 0x4C, 0xEB, 0x11, 0x5B, 0x0D, 0x60, 0x30, 0xF0, 0x20, 0x6A, 0x10, 0xF0, 0x24, 0x6B, 0xCE, 0xF4, 0x50, 0x9A, 0x61, 0xF0, -0x00, 0x6C, 0x39, 0xF7, 0xB4, 0x9B, 0x40, 0xF4, +0x00, 0x6C, 0x5E, 0xF3, 0xB8, 0x9B, 0x40, 0xF4, 0x12, 0x6E, 0xD8, 0x17, 0x76, 0x58, 0x0D, 0x61, 0x30, 0xF0, 0x20, 0x6A, 0x10, 0xF0, 0x24, 0x6B, 0xCE, 0xF4, 0x50, 0x9A, 0x61, 0xF0, 0x00, 0x6C, -0x39, 0xF7, 0xB4, 0x9B, 0x00, 0xF4, 0x12, 0x6E, +0x5E, 0xF3, 0xB8, 0x9B, 0x00, 0xF4, 0x12, 0x6E, 0xC9, 0x17, 0x30, 0xF0, 0x20, 0x6A, 0x10, 0xF0, 0x24, 0x6B, 0xCE, 0xF4, 0x50, 0x9A, 0x61, 0xF0, -0x00, 0x6C, 0x39, 0xF7, 0xB4, 0x9B, 0x61, 0xF1, +0x00, 0x6C, 0x5E, 0xF3, 0xB8, 0x9B, 0x61, 0xF1, 0x0A, 0x6E, 0xBC, 0x17, 0x68, 0x40, 0xE4, 0x4B, 0xFF, 0x6A, 0x4C, 0xEB, 0x1D, 0x5B, 0x03, 0x60, 0xFF, 0x69, 0x02, 0x49, 0x0D, 0x10, 0x68, 0x40, @@ -35086,10 +50905,10 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x00, 0xF3, 0x01, 0x69, 0x05, 0x10, 0x8D, 0x58, 0x00, 0x69, 0x02, 0x61, 0x00, 0xF5, 0x01, 0x49, 0x10, 0xF0, 0x24, 0x6B, 0x30, 0xF0, 0x20, 0x6A, -0x7A, 0xF0, 0x8C, 0x9B, 0xAE, 0xF4, 0x50, 0x9A, +0xDE, 0xF4, 0x80, 0x9B, 0xAE, 0xF4, 0x50, 0x9A, 0x40, 0xEA, 0xF1, 0x67, 0xE4, 0xEA, 0x10, 0xF0, -0x24, 0x6A, 0x7A, 0xF0, 0xD0, 0x9A, 0x04, 0x94, -0x18, 0x6D, 0x0D, 0xEF, 0x00, 0x18, 0xCE, 0xEA, +0x24, 0x6A, 0xDE, 0xF4, 0xC4, 0x9A, 0x04, 0x94, +0x18, 0x6D, 0x0D, 0xEF, 0x00, 0x18, 0x36, 0xF2, 0x04, 0x92, 0x01, 0x4A, 0x04, 0x72, 0x04, 0xD2, 0xD1, 0x61, 0x68, 0x40, 0xE4, 0x4B, 0xFF, 0x6A, 0x4C, 0xEB, 0x1D, 0x5B, 0x09, 0x60, 0x30, 0xF0, @@ -35103,267 +50922,280 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x41, 0xF1, 0x18, 0x6C, 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@@ -36791,381 +52813,525 @@ u8 array_mp_8821c_fw_wowlan[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x30, 0xF0, 0x20, 0x6A, -0xC0, 0xF1, 0x08, 0x4A, 0x05, 0x6B, 0x65, 0xF4, -0x64, 0xDA, 0x00, 0x6B, 0x65, 0xF4, 0x60, 0xDA, -0x20, 0xE8, 0x00, 0x65, 0xFD, 0x63, 0x05, 0x62, -0x30, 0xF0, 0x20, 0x6A, 0xAE, 0xF2, 0x58, 0x9A, -0x06, 0xD4, 0x09, 0xD7, 0x07, 0xD5, 0x08, 0xD6, -0x06, 0x04, 0x40, 0xEA, 0x05, 0x97, 0x03, 0x63, -0x00, 0xEF, 0x00, 0x65, 0xFB, 0x63, 0x09, 0x62, -0x08, 0xD1, 0x07, 0xD0, 0x46, 0x67, 0x01, 0x4A, -0x05, 0x67, 0x0C, 0xD6, 0x27, 0x67, 0x1F, 0x22, +0x20, 0xE8, 0x00, 0x65, 0x20, 0xE8, 0x00, 0x65, +0x20, 0xE8, 0x00, 0x65, 0x10, 0xF0, 0x24, 0x6B, +0xDE, 0xF5, 0x60, 0x9B, 0xFF, 0x6A, 0x8C, 0xEA, +0x60, 0x9B, 0x80, 0xF1, 0x01, 0x6C, 0x8B, 0xEC, +0x8C, 0xEB, 0x10, 0xF0, 0x24, 0x6C, 0xFE, 0xF2, +0x94, 0x9C, 0x01, 0x72, 0x80, 0x9C, 0x05, 0x60, +0x02, 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0xCF, 0xF4, 0x00, 0x4A, 0x00, 0x6B, +0x02, 0x6C, 0x40, 0xF5, 0x69, 0xC2, 0x40, 0xF5, +0x6D, 0xC2, 0x40, 0xF5, 0x8A, 0xC2, 0x01, 0x6B, +0x0C, 0x10, 0x30, 0xF0, 0x20, 0x6A, 0xCF, 0xF4, +0x00, 0x4A, 0x01, 0x6B, 0x00, 0x6C, 0x40, 0xF5, +0x69, 0xC2, 0x40, 0xF5, 0x8A, 0xC2, 0x40, 0xF5, +0x6D, 0xC2, 0x40, 0xF5, 0x6C, 0xC2, 0x20, 0xE8, +0xFC, 0x63, 0x07, 0x62, 0x06, 0xD1, 0x05, 0xD0, +0x30, 0xF0, 0x20, 0x6B, 0xFF, 0x6A, 0xCF, 0xF4, +0x00, 0x4B, 0x8C, 0xEA, 0x40, 0xF5, 0x89, 0xA3, +0x55, 0x24, 0x40, 0xF5, 0x6B, 0xA3, 0x00, 0x69, +0x01, 0x23, 0x01, 0x69, 0x30, 0xF0, 0x21, 0x6B, +0x10, 0xF2, 0x6C, 0xA3, 0x02, 0x2B, 0x01, 0x6B, +0x6E, 0xE9, 0x29, 0x2A, 0x23, 0x10, 0x10, 0xF0, +0x24, 0x6B, 0x30, 0xF0, 0x20, 0x68, 0x9E, 0xF3, +0xB4, 0x9B, 0xCE, 0xF4, 0x50, 0x98, 0x4C, 0x6C, +0x02, 0x6E, 0x40, 0xEA, 0xCE, 0xF4, 0x50, 0x98, +0xA1, 0xF4, 0x14, 0x6C, 0xFF, 0x6D, 0x66, 0x6E, +0x40, 0xEA, 0x01, 0x6A, 0x4E, 0xE9, 0x2B, 0xEB, +0x2D, 0xEB, 0xC0, 0xF7, 0x62, 0x33, 0x10, 0xF0, +0x24, 0x6D, 0x02, 0x6E, 0xCE, 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0xEF, 0x10, 0xF0, 0x21, 0x6A, +0x84, 0xF4, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0x8E, 0xF6, 0x48, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0x24, 0xF5, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0x8E, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0xC4, 0xF5, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0x8E, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0x24, 0xF6, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0x8E, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0x64, 0xF6, 0x04, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0x8E, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0xE4, 0xF6, 0x00, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0x8E, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0xE4, 0xF7, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xAE, 0xF6, 0x40, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0x65, 0xF1, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xAE, 0xF6, 0x44, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0x45, 0xF2, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xAE, 0xF6, 0x48, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0x45, 0xF3, 0x08, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xAE, 0xF6, 0x4C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0xC5, 0xF5, 0x10, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xAE, 0xF6, 0x50, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0xA5, 0xF7, 0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xAE, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0xA5, 0xF7, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xAE, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0x06, 0xF1, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xAE, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0xC6, 0xF1, 0x0C, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xCE, 0xF6, 0x40, 0xDB, 0x20, 0xE8, 0x00, 0x65, +0xF3, 0x59, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -u32 array_length_mp_8821c_fw_wowlan = 92840; +u32 array_length_mp_8821c_fw_wowlan = 103184; + +#endif /*CONFIG_WOWLAN*/ #endif diff --git a/hal/rtl8821c/hal8821c_fw.h b/hal/rtl8821c/hal8821c_fw.h index e14c4cf..f41c416 100644 --- a/hal/rtl8821c/hal8821c_fw.h +++ b/hal/rtl8821c/hal8821c_fw.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. +* Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,6 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* ******************************************************************************/ #ifdef CONFIG_RTL8821C @@ -25,15 +20,19 @@ #ifdef LOAD_FW_HEADER_FROM_DRIVER #if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP))) -extern u8 array_mp_8821c_fw_ap[89056]; +extern u8 array_mp_8821c_fw_ap[114208]; extern u32 array_length_mp_8821c_fw_ap; #endif #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) -extern u8 array_mp_8821c_fw_nic[115080]; +extern u8 array_mp_8821c_fw_nic[137616]; extern u32 array_length_mp_8821c_fw_nic; -extern u8 array_mp_8821c_fw_wowlan[92840]; +extern u8 array_mp_8821c_fw_spic[71264]; +extern u32 array_length_mp_8821c_fw_spic; +#ifdef CONFIG_WOWLAN +extern u8 array_mp_8821c_fw_wowlan[103184]; extern u32 array_length_mp_8821c_fw_wowlan; +#endif /*CONFIG_WOWLAN*/ #endif #endif /* end of LOAD_FW_HEADER_FROM_DRIVER */ diff --git a/hal/rtl8821c/pci/rtl8821ce.h b/hal/rtl8821c/pci/rtl8821ce.h index 86dc96c..22dd5e6 100755 --- a/hal/rtl8821c/pci/rtl8821ce.h +++ b/hal/rtl8821c/pci/rtl8821ce.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,17 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8821CE_H_ #define _RTL8821CE_H_ #include /* PADAPTER */ -#include "../../hal_halmac.h" /* HALMAC_RX_FIFO_SIZE_8821C */ #define TX_BD_NUM_8821CE 128 #define RX_BD_NUM_8821CE 128 @@ -44,8 +38,18 @@ #define TX_BUFFER_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */ -#define MAX_RECVBUF_SZ_8821C HALMAC_RX_FIFO_SIZE_8821C +#define MAX_RECVBUF_SZ_8821C 16384 /* 16k */ +#ifdef CONFIG_64BIT_DMA +#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu) +#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu) +#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu) +#define SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu) +#else /* TX BD */ #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu) @@ -53,10 +57,18 @@ SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu) #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu) +#define SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) 0 +#endif /* RX BD */ #define SET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd, __Value) \ SET_BITS_TO_LE_4BYTE(__pRxBd + 0x04, 0, 32, __Value) +#ifdef CONFIG_64BIT_DMA +#define SET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxBd + 0x08, 0, 32, __Value) +#else +#define SET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd, __Value) 0 +#endif #define SET_RX_BD_RXBUFFSIZE(__pRxBd, __Value) \ SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 0, 14, __Value) #define SET_RX_BD_LS(__pRxBd, __Value) \ diff --git a/hal/rtl8821c/pci/rtl8821ce_halinit.c b/hal/rtl8821c/pci/rtl8821ce_halinit.c index 23ce491..67fa0a1 100755 --- a/hal/rtl8821c/pci/rtl8821ce_halinit.c +++ b/hal/rtl8821c/pci/rtl8821ce_halinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8821CE_HALINIT_C_ #include /* PADAPTER, basic_types.h and etc. */ @@ -104,7 +99,7 @@ u32 InitMAC_TRXBD_8821CE(PADAPTER Adapter) rtw_write32(Adapter, REG_RXQ_RXBD_DESA_8821C + 4, ((u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma) >> 32); - +#if 0 /* 2009/10/28 MH If RX descriptor address is not equal to zero. * We will enable DMA 64 bit functuion. * Note: We never saw thd consition which the descripto address are @@ -119,10 +114,12 @@ u32 InitMAC_TRXBD_8821CE(PADAPTER Adapter) if (((u64)pxmitpriv->tx_ring[MGT_QUEUE_INX].dma) >> 32) RTW_INFO("MGNT_QUEUE HA=0\n"); - PlatformEnableDMA64(Adapter); } else RTW_INFO("Enable DMA32 bit\n"); #endif + if (adapter_to_dvobj(Adapter)->bdma64) + PlatformEnableDMA64(Adapter); +#endif /* pci buffer descriptor mode: Reset the Read/Write point to 0 */ PlatformEFIOWrite4Byte(Adapter, REG_TSFTIMER_HCI_8821C, 0x3fffffff); @@ -183,16 +180,15 @@ u32 InitMAC_TRXBD_8821CE(PADAPTER Adapter) /* rx. support 32 bits in linux */ - - /* using 64bit - * rtw_write16(Adapter, REG_RX_RXBD_NUM_8821C, - * RX_BD_NUM_8821CE |((RTL8821CE_SEG_NUM<<13 ) & 0x6000) |0x8000); - */ - - +#ifdef CONFIG_64BIT_DMA + /* using 64bit */ + rtw_write16(Adapter, REG_RX_RXBD_NUM_8821C, + RX_BD_NUM_8821CE |((RTL8821CE_SEG_NUM<<13 ) & 0x6000) |0x8000); +#else /* using 32bit */ rtw_write16(Adapter, REG_RX_RXBD_NUM_8821C, RX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 13) & 0x6000)); +#endif /* reset read/write point */ rtw_write32(Adapter, REG_TSFTIMER_HCI_8821C, 0XFFFFFFFF); @@ -256,6 +252,9 @@ u32 rtl8821ce_hal_init(PADAPTER padapter) rtw_write8(padapter, REG_RX_DRVINFO_SZ_8821C, 0x4); + /* MAX AMPDU Number = 43, Reg0x4C8[21:16] = 0x2B */ + rtw_write16(padapter, REG_PROT_MODE_CTRL_8821C + 2, 0x2B2B); + hal->pci_backdoor_ctrl = registry_par->pci_aspm_config; rtw_pci_aspm_config(padapter); @@ -310,6 +309,9 @@ void rtl8821ce_init_default_value(PADAPTER padapter) BIT_BCNDMAINT0_MSK | BIT_HSISR_IND_ON_INT_MSK | BIT_C2HCMD_MSK | + #ifdef CONFIG_LPS_LCLK + BIT_CPWM_MSK | + #endif BIT_HIGHDOK_MSK | BIT_MGTDOK_MSK | BIT_BKDOK_MSK | @@ -326,6 +328,7 @@ void rtl8821ce_init_default_value(PADAPTER padapter) pHalData->IntrMaskDefault[1] = (u32)( BIT(9) | /* TXFOVW */ BIT_FOVW_MSK | + BIT_PRETXERR_HANDLE_IMR | 0); /* diff --git a/hal/rtl8821c/pci/rtl8821ce_halmac.c b/hal/rtl8821c/pci/rtl8821ce_halmac.c index 4b34a74..1100cdf 100755 --- a/hal/rtl8821c/pci/rtl8821ce_halmac.c +++ b/hal/rtl8821c/pci/rtl8821ce_halmac.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2018 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,22 +11,18 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8821CE_HALMAC_C_ #include /* struct dvobj_priv and etc. */ #include "../../hal_halmac.h" #include "rtl8821ce.h" -static u8 pci_write_port_not_xmitframe(void *d, u32 size, u8 *pBuf) +static u8 pci_write_port_not_xmitframe(void *d, u32 size, u8 *pBuf, u8 qsel) { struct dvobj_priv *pobj = (struct dvobj_priv *)d; struct pci_dev *pdev = pobj->ppcidev; PADAPTER padapter = dvobj_get_primary_adapter(pobj); + u32 page_size = 0; u8 *txbd; u64 txbd_dma; u8 ret = _SUCCESS; @@ -35,6 +31,13 @@ static u8 pci_write_port_not_xmitframe(void *d, u32 size, u8 *pBuf) u16 seg_num = 2 << TX_BUFFER_SEG_NUM; u16 page_size_length = 0; +#ifdef CONFIG_64BIT_DMA + u16 tmp = rtw_read16(padapter, REG_RX_RXBD_NUM_8821C); + /* using 64bit */ + rtw_write16(padapter, REG_RX_RXBD_NUM_8821C, tmp | 0x8000); +#endif + + rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, &page_size); /* map TX DESC buf_addr (including TX DESC + tx data) */ mapping = pci_map_single(pdev, pBuf, @@ -45,9 +48,9 @@ static u8 pci_write_port_not_xmitframe(void *d, u32 size, u8 *pBuf) * Total buffer length including TX_WIFI_INFO and PacketLen */ page_size_length = - (size + TX_WIFI_INFO_SIZE) / HALMAC_TX_PAGE_SIZE_8821C; + (size + TX_WIFI_INFO_SIZE) / page_size; - if (((size + TX_WIFI_INFO_SIZE) % HALMAC_TX_PAGE_SIZE_8821C) > 0) + if (((size + TX_WIFI_INFO_SIZE) % page_size) > 0) page_size_length++; txbd = pci_alloc_consistent(pdev, @@ -59,6 +62,25 @@ static u8 pci_write_port_not_xmitframe(void *d, u32 size, u8 *pBuf) return _FALSE; } + if (qsel == HALMAC_TXDESC_QSEL_H2C_CMD) { + rtw_write32(padapter, REG_H2CQ_TXBD_DESA_8821C, + txbd_dma & DMA_BIT_MASK(32)); + #ifdef CONFIG_64BIT_DMA + rtw_write32(padapter, REG_H2CQ_TXBD_DESA_8821C + 4, + txbd_dma >> 32); + #endif + + rtw_write32(padapter, REG_H2CQ_TXBD_NUM_8821C, + 2 | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + } else { + /* Set BCN BD Reg */ + rtw_write32(padapter, REG_BCNQ_TXBD_DESA_8821C, + txbd_dma & DMA_BIT_MASK(32)); + #ifdef CONFIG_64BIT_DMA + rtw_write32(padapter, REG_BCNQ_TXBD_DESA_8821C + 4, + txbd_dma >> 32); + #endif + } /* * Reset all tx buffer desciprtor content @@ -76,6 +98,9 @@ static u8 pci_write_port_not_xmitframe(void *d, u32 size, u8 *pBuf) SET_TX_BD_PSB(txbd, page_size_length); /* starting addr of TXDESC */ SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, mapping); +#ifdef CONFIG_64BIT_DMA + SET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd, mapping>>32); +#endif /* * It is assumed that in linux implementation, packet is coalesced @@ -86,23 +111,28 @@ static u8 pci_write_port_not_xmitframe(void *d, u32 size, u8 *pBuf) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(txbd, 1, mapping + TX_WIFI_INFO_SIZE); /* pkt */ - /* Set BCN BD Reg */ - rtw_write32(padapter, REG_BCNQ_TXBD_DESA_8821C, - txbd_dma & DMA_BIT_MASK(32)); +#ifdef CONFIG_64BIT_DMA + SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(txbd, 1, + (mapping + TX_WIFI_INFO_SIZE) >> 32); /* pkt */ +#endif + /* Need Comment */ wmb(); - /* fill_txbd_own*/ - SET_TX_BD_OWN(txbd, 1); - - /* kick start */ - rtw_write8(padapter, REG_RX_RXBD_NUM + 1, - rtw_read8(padapter, REG_RX_RXBD_NUM + 1) | BIT(4)); + if (qsel == HALMAC_TXDESC_QSEL_H2C_CMD) + rtw_write16(padapter, REG_H2CQ_TXBD_IDX, 1); + else { + /* fill_txbd_own*/ + SET_TX_BD_OWN(txbd, 1); + /* kick start */ + rtw_write8(padapter, REG_RX_RXBD_NUM + 1, + rtw_read8(padapter, REG_RX_RXBD_NUM + 1) | BIT(4)); + } udelay(100); - pci_free_consistent(pdev, sizeof(*txbd), txbd, txbd_dma); + pci_free_consistent(pdev, sizeof(struct tx_buf_desc), txbd, txbd_dma); pci_unmap_single(pdev, mapping, size + TX_WIFI_INFO_SIZE, PCI_DMA_FROMDEVICE); @@ -115,9 +145,9 @@ static u8 pci_write_data_not_xmitframe(void *d, u8 *pBuf, u32 size, u8 qsel) { struct dvobj_priv *pobj = (struct dvobj_priv *)d; PADAPTER padapter = dvobj_get_primary_adapter(pobj); - PHALMAC_ADAPTER halmac = dvobj_to_halmac((struct dvobj_priv *)d); - PHALMAC_API api = HALMAC_GET_API(halmac); - u8 desclen = 0; + struct halmac_adapter *halmac = dvobj_to_halmac((struct dvobj_priv *)d); + struct halmac_api *api = HALMAC_GET_API(halmac); + u32 desclen = 0; u8 *buf = NULL; u8 ret = _FALSE; @@ -127,7 +157,7 @@ static u8 pci_write_data_not_xmitframe(void *d, u8 *pBuf, u32 size, u8 qsel) return _FALSE; } - desclen = HALMAC_TX_DESC_SIZE_8821C; + rtw_halmac_get_tx_desc_size(pobj, &desclen); buf = rtw_zmalloc(desclen + size); @@ -139,12 +169,22 @@ static u8 pci_write_data_not_xmitframe(void *d, u8 *pBuf, u32 size, u8 qsel) _rtw_memcpy(buf + desclen, pBuf, size); SET_TX_DESC_TXPKTSIZE_8821C(buf, size); - SET_TX_DESC_OFFSET_8821C(buf, desclen); + + /* TX_DESC is not included in the data, + * driver needs to fill in the TX_DESC with qsel=h2c + * Offset in TX_DESC should be set to 0. + */ + if (qsel == HALMAC_TXDESC_QSEL_H2C_CMD) + SET_TX_DESC_OFFSET_8821C(buf, 0); + else + SET_TX_DESC_OFFSET_8821C(buf, desclen); + SET_TX_DESC_QSEL_8821C(buf, qsel); api->halmac_fill_txdesc_checksum(halmac, buf); - ret = pci_write_port_not_xmitframe(d, size, buf); + ret = pci_write_port_not_xmitframe(d, size, buf, qsel); + if (ret == _SUCCESS) ret = _TRUE; @@ -160,13 +200,19 @@ static u8 pci_write_data_rsvd_page_xmitframe(void *d, u8 *pBuf, u32 size) { struct dvobj_priv *pobj = (struct dvobj_priv *)d; PADAPTER padapter = dvobj_get_primary_adapter(pobj); - PHALMAC_ADAPTER halmac = dvobj_to_halmac((struct dvobj_priv *)d); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct xmit_frame *pcmdframe = NULL; struct pkt_attrib *pattrib = NULL; - PHALMAC_API api = HALMAC_GET_API(halmac); - u8 desclen = 0; + u32 desclen = 0; + struct rtw_tx_ring *ring = &pxmitpriv->tx_ring[BCN_QUEUE_INX]; + struct pci_dev *pdev = pobj->ppcidev; + struct xmit_buf *pxmitbuf = NULL; + u8 DLBcnCount = 0; + u32 poll = 0; + u8 *txbd; + bool bcn_valid = _FALSE; u8 *txdesc = NULL; + dma_addr_t mapping; if (size + TXDESC_OFFSET > MAX_CMDBUF_SZ) { RTW_INFO("%s: total buffer size(%d) > MAX_CMDBUF_SZ(%d)\n" @@ -181,7 +227,8 @@ static u8 pci_write_data_rsvd_page_xmitframe(void *d, u8 *pBuf, u32 size) return _FALSE; } - desclen = HALMAC_TX_DESC_SIZE_8821C; + pxmitbuf = pcmdframe->pxmitbuf; + rtw_halmac_get_tx_desc_size(pobj, &desclen); txdesc = pcmdframe->buf_addr; _rtw_memcpy((txdesc + desclen), pBuf, size); /* shift desclen */ @@ -193,8 +240,35 @@ static u8 pci_write_data_rsvd_page_xmitframe(void *d, u8 *pBuf, u32 size) pattrib->pktlen = size; pattrib->last_txcmdsz = size; + /* Clear beacon valid check bit. */ + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); + dump_mgntframe(padapter, pcmdframe); + DLBcnCount = 0; + poll = 0; + do { + DLBcnCount++; + do { + rtw_yield_os(); + /* does rsvd page download OK. */ + rtw_hal_get_hwreg(padapter, + HW_VAR_BCN_VALID,(u8 *)(&bcn_valid)); + poll++; + } while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(padapter)); + } while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(padapter)); + + txbd = (u8 *)(&ring->buf_desc[0]); + + mapping = GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd); + #ifdef CONFIG_64BIT_DMA + mapping |= (dma_addr_t)GET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd) << 32; + #endif + + /*To patch*/ + + pci_unmap_single(pdev, mapping, pxmitbuf->len, PCI_DMA_TODEVICE); + return _TRUE; } @@ -202,11 +276,11 @@ static u8 pci_write_data_h2c_normal(void *d, u8 *pBuf, u32 size) { struct dvobj_priv *pobj = (struct dvobj_priv *)d; PADAPTER padapter = dvobj_get_primary_adapter(pobj); - PHALMAC_ADAPTER halmac = dvobj_to_halmac((struct dvobj_priv *)d); + struct halmac_adapter *halmac = dvobj_to_halmac((struct dvobj_priv *)d); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct xmit_frame *pcmdframe = NULL; struct pkt_attrib *pattrib = NULL; - PHALMAC_API api; + struct halmac_api *api; u32 desclen; u8 *buf; @@ -225,13 +299,13 @@ static u8 pci_write_data_h2c_normal(void *d, u8 *pBuf, u32 size) api = HALMAC_GET_API(halmac); - desclen = HALMAC_TX_DESC_SIZE_8821C; + rtw_halmac_get_tx_desc_size(pobj, &desclen); buf = pcmdframe->buf_addr; _rtw_memcpy(buf + desclen, pBuf, size); /* shift desclen */ SET_TX_DESC_TXPKTSIZE_8821C(buf, size); SET_TX_DESC_OFFSET_8821C(buf, 0); - SET_TX_DESC_QSEL_8821C(buf, HALMAC_QUEUE_SELECT_CMD); + SET_TX_DESC_QSEL_8821C(buf, HALMAC_TXDESC_QSEL_H2C_CMD); SET_TX_DESC_TXDESC_CHECKSUM_8821C(buf, 0); api->halmac_fill_txdesc_checksum(halmac, buf); @@ -253,11 +327,16 @@ static u8 pci_write_data_rsvd_page(void *d, u8 *pBuf, u32 size) struct dvobj_priv *pobj = (struct dvobj_priv *)d; PADAPTER padapter = dvobj_get_primary_adapter(pobj); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 ret; if (pHalData->not_xmitframe_fw_dl) - return pci_write_data_not_xmitframe(d, pBuf, size, HALMAC_TXDESC_QSEL_BEACON); + ret = pci_write_data_not_xmitframe(d, pBuf, size, HALMAC_TXDESC_QSEL_BEACON); else - return pci_write_data_rsvd_page_xmitframe(d, pBuf, size); + ret = pci_write_data_rsvd_page_xmitframe(d, pBuf, size); + + if (ret == _TRUE) + return 1; + return 0; } static u8 pci_write_data_h2c(void *d, u8 *pBuf, u32 size) @@ -265,19 +344,29 @@ static u8 pci_write_data_h2c(void *d, u8 *pBuf, u32 size) struct dvobj_priv *pobj = (struct dvobj_priv *)d; PADAPTER padapter = dvobj_get_primary_adapter(pobj); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 ret; if (pHalData->not_xmitframe_fw_dl) - return pci_write_data_not_xmitframe(d, pBuf, size, HALMAC_TXDESC_QSEL_H2C_CMD); + ret = pci_write_data_not_xmitframe(d, pBuf, size, HALMAC_TXDESC_QSEL_H2C_CMD); else - return pci_write_data_h2c_normal(d, pBuf, size); + ret = pci_write_data_h2c_normal(d, pBuf, size); + + if (ret == _TRUE) + return 1; + return 0; } int rtl8821ce_halmac_init_adapter(PADAPTER padapter) { struct dvobj_priv *d; - PHALMAC_PLATFORM_API api; + struct halmac_platform_api *api; int err; +#ifdef CONFIG_64BIT_DMA + if (adapter_to_dvobj(padapter)->bdma64) + PlatformEnableDMA64(padapter); +#endif + d = adapter_to_dvobj(padapter); api = &rtw_halmac_platform_api; api->SEND_RSVD_PAGE = pci_write_data_rsvd_page; diff --git a/hal/rtl8821c/pci/rtl8821ce_io.c b/hal/rtl8821c/pci/rtl8821ce_io.c index 4585c2b..7d3ca07 100755 --- a/hal/rtl8821c/pci/rtl8821ce_io.c +++ b/hal/rtl8821c/pci/rtl8821ce_io.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8821CE_IO_C_ #include /* PADAPTER and etc. */ diff --git a/hal/rtl8821c/pci/rtl8821ce_led.c b/hal/rtl8821c/pci/rtl8821ce_led.c index a0324a2..6fd37c6 100755 --- a/hal/rtl8821c/pci/rtl8821ce_led.c +++ b/hal/rtl8821c/pci/rtl8821ce_led.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,17 +11,13 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include /* PADAPTER */ #include /* PHAL_DATA_TYPE */ #include /* PLED_PCIE */ +#ifdef CONFIG_RTW_SW_LED /* *============================================================================== @@ -44,7 +40,7 @@ static void SwLedOn_8821ce(PADAPTER adapter, PLED_PCIE pLed) #if 0 u16 LedReg = REG_LEDCFG0; u8 LedCfg = 0; - struct led_priv *ledpriv = &(adapter->ledpriv); + struct led_priv *ledpriv = adapter_to_led(adapter); if (RTW_CANNOT_RUN(adapter)) return; @@ -90,7 +86,7 @@ static void SwLedOff_8821ce(PADAPTER adapter, PLED_PCIE pLed) #if 0 u16 LedReg = REG_LEDCFG0; PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct led_priv *ledpriv = &adapter->ledpriv; + struct led_priv *ledpriv = adapter_to_led(adapter); if (RTW_CANNOT_RUN(adapter)) return; @@ -139,7 +135,7 @@ static void SwLedOff_8821ce(PADAPTER adapter, PLED_PCIE pLed) */ void rtl8821ce_InitSwLeds(PADAPTER adapter) { - struct led_priv *pledpriv = &adapter->ledpriv; + struct led_priv *pledpriv = adapter_to_led(adapter); pledpriv->LedControlHandler = LedControlPCIE; @@ -157,8 +153,9 @@ void rtl8821ce_InitSwLeds(PADAPTER adapter) */ void rtl8821ce_DeInitSwLeds(PADAPTER adapter) { - struct led_priv *ledpriv = &adapter->ledpriv; + struct led_priv *ledpriv = adapter_to_led(adapter); DeInitLed(&ledpriv->SwLed0); DeInitLed(&ledpriv->SwLed1); } +#endif diff --git a/hal/rtl8821c/pci/rtl8821ce_ops.c b/hal/rtl8821c/pci/rtl8821ce_ops.c index 561d148..87d1a85 100755 --- a/hal/rtl8821c/pci/rtl8821ce_ops.c +++ b/hal/rtl8821c/pci/rtl8821ce_ops.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HCI_OPS_OS_C_ @@ -59,6 +54,7 @@ static void rtl8821ce_reset_bd(_adapter *padapter) struct xmit_buf *pxmitbuf = NULL; u8 *tx_bd, *rx_bd; int i, rx_queue_idx; + dma_addr_t mapping; for (rx_queue_idx = 0; rx_queue_idx < 1; rx_queue_idx++) { if (r_priv->rx_ring[rx_queue_idx].buf_desc) { @@ -86,8 +82,12 @@ static void rtl8821ce_reset_bd(_adapter *padapter) pxmitbuf = rtl8821ce_dequeue_xmitbuf(ring); if (pxmitbuf) { + mapping = GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_bd); + #ifdef CONFIG_64BIT_DMA + mapping |= (dma_addr_t)GET_TX_BD_PHYSICAL_ADDR0_HIGH(tx_bd) << 32; + #endif pci_unmap_single(pdvobjpriv->ppcidev, - GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_bd), + mapping, pxmitbuf->len, PCI_DMA_TODEVICE); rtw_free_xmitbuf(t_priv, pxmitbuf); } else { @@ -104,7 +104,40 @@ static void rtl8821ce_reset_bd(_adapter *padapter) static void intf_chip_configure(PADAPTER padapter) { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv); + + /* close ASPM for AMD defaultly */ + pdvobjpriv->const_amdpci_aspm = 0; + + /* ASPM PS mode. */ + /* 0 - Disable ASPM, 1 - Enable ASPM without Clock Req, */ + /* 2 - Enable ASPM with Clock Req, 3- Alwyas Enable ASPM with Clock Req, */ + /* 4- Always Enable ASPM without Clock Req. */ + /* set default to rtl8188ee:3 RTL8192E:2 */ + pdvobjpriv->const_pci_aspm = 0; + + /* Setting for PCI-E device */ + pdvobjpriv->const_devicepci_aspm_setting = 0x03; + + /* Setting for PCI-E bridge */ + pdvobjpriv->const_hostpci_aspm_setting = 0x03; + /* In Hw/Sw Radio Off situation. */ + /* 0 - Default, 1 - From ASPM setting without low Mac Pwr, */ + /* 2 - From ASPM setting with low Mac Pwr, 3 - Bus D3 */ + /* set default to RTL8192CE:0 RTL8192SE:2 */ + pdvobjpriv->const_hwsw_rfoff_d3 = 0; + + /* This setting works for those device with backdoor ASPM setting such as EPHY setting. */ + /* 0: Not support ASPM, 1: Support ASPM, 2: According to chipset. */ + pdvobjpriv->const_support_pciaspm = 1; + + pwrpriv->reg_rfoff = 0; + pwrpriv->rfoff_reason = 0; + + pHalData->bL1OffSupport = _FALSE; } /* @@ -118,10 +151,13 @@ static void intf_chip_configure(PADAPTER padapter) */ static u8 read_adapter_info(PADAPTER padapter) { + u8 ret = _FAIL; + /* * 1. Read Efuse/EEPROM to initialize */ - rtl8821c_read_efuse(padapter); + if (rtl8821c_read_efuse(padapter) != _SUCCESS) + goto exit; /* * 2. Read registers to initialize @@ -131,7 +167,10 @@ static u8 read_adapter_info(PADAPTER padapter) * 3. Other Initialization */ - return _SUCCESS; + ret = _SUCCESS; + +exit: + return ret; } static BOOLEAN rtl8821ce_InterruptRecognized(PADAPTER Adapter) @@ -408,9 +447,23 @@ static s32 rtl8821ce_interrupt(PADAPTER Adapter) handled[1] |= BIT_TXFOVW; } + if (pHalData->IntArray[1] & BIT_PRETXERR_HANDLE_ISR) { + RTW_ERR("[PRE-TX HANG]\n"); + handled[1] |= BIT_PRETXERR_HANDLE_ISR; + } + /* <4> Cmd related */ rtl8821ce_cmd_handler(Adapter, handled); +#ifdef CONFIG_LPS_LCLK + if (pHalData->IntArray[0] & BIT_CPWM) { + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); + + _set_workitem(&(pwrpriv->cpwm_event)); + handled[0] |= BIT_CPWM; + } +#endif + if ((pHalData->IntArray[0] & (~handled[0])) || (pHalData->IntArray[1] & (~handled[1])) || (pHalData->IntArray[3] & (~handled[3]))) { /*if (printk_ratelimit()) */ { @@ -610,9 +663,10 @@ static u8 sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE eVariable, void *pval) * If variable not handled here, * some variables will be processed in rtl8821c_sethwreg() */ -static void sethwreg(PADAPTER adapter, u8 variable, u8 *val) +static u8 sethwreg(PADAPTER adapter, u8 variable, u8 *val) { PHAL_DATA_TYPE hal; + u8 ret = _SUCCESS; u8 val8; @@ -636,11 +690,28 @@ static void sethwreg(PADAPTER adapter, u8 variable, u8 *val) hal_mdio_write_8821ce(adapter, (u8)pCmd[0], pCmd[1]); break; } +#ifdef CONFIG_LPS_LCLK + case HW_VAR_SET_RPWM: + { + u8 ps_state = *((u8 *)val); + /* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e. */ + /* BIT0 value - 1: 32k, 0:40MHz. */ + /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */ + /* BIT7 value - Toggle bit change. */ + /* modify by Thomas. 2012/4/2. */ + ps_state = ps_state & 0xC1; + /* RTW_INFO("##### Change RPWM value to = %x for switch clk #####\n",ps_state); */ + rtw_write8(adapter, REG_PCIE_HRPWM1_V1_8821C, ps_state); + break; + } +#endif + default: - rtl8821c_sethwreg(adapter, variable, val); + ret = rtl8821c_sethwreg(adapter, variable, val); break; } + return ret; } /* @@ -682,6 +753,13 @@ static void gethwreg(PADAPTER adapter, u8 variable, u8 *val) *val = _FALSE; } break; + +#ifdef CONFIG_LPS_LCLK + case HW_VAR_CPWM: + *val = rtw_read8(adapter, REG_PCIE_HCPWM1_V1_8821C); + break; +#endif + default: rtl8821c_gethwreg(adapter, variable, val); break; @@ -713,12 +791,9 @@ void rtl8821ce_set_hal_ops(PADAPTER padapter) ops->init_recv_priv = rtl8821ce_init_recv_priv; ops->free_recv_priv = rtl8821ce_free_recv_priv; -#ifdef CONFIG_SW_LED +#ifdef CONFIG_RTW_SW_LED ops->InitSwLeds = rtl8821ce_InitSwLeds; ops->DeInitSwLeds = rtl8821ce_DeInitSwLeds; -#else /* case of hw led or no led */ - ops->InitSwLeds = NULL; - ops->DeInitSwLeds = NULL; #endif ops->init_default_value = rtl8821ce_init_default_value; diff --git a/hal/rtl8821c/pci/rtl8821ce_recv.c b/hal/rtl8821c/pci/rtl8821ce_recv.c index 0da3fe5..2dadf19 100755 --- a/hal/rtl8821c/pci/rtl8821ce_recv.c +++ b/hal/rtl8821c/pci/rtl8821ce_recv.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,16 +11,12 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8821CE_RECV_C_ #include /* PADAPTER and etc. */ #include /* HAL_DATA_TYPE */ +#include "../../hal_halmac.h" /* rtw_halmac_get_rx_desc_size() */ #include "../rtl8821c.h" #include "rtl8821ce.h" @@ -162,13 +158,15 @@ static void rtl8821ce_rx_mpdu(_adapter *padapter) _queue *pfree_recv_queue = &r_priv->free_recv_queue; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); union recv_frame *precvframe = NULL; - u8 *pphy_info = NULL; struct rx_pkt_attrib *pattrib = NULL; int rx_q_idx = RX_MPDU_QUEUE; u32 count = r_priv->rxringcount; u16 remaing_rxdesc = 0; u8 *rx_bd; struct sk_buff *skb; + u32 desc_size; + + rtw_halmac_get_rx_desc_size(adapter_to_dvobj(padapter), &desc_size); /* RX NORMAL PKT */ @@ -237,7 +235,7 @@ static void rtl8821ce_rx_mpdu(_adapter *padapter) pattrib->shift_sz); if (rtw_os_alloc_recvframe(padapter, precvframe, - (skb->data + HALMAC_RX_DESC_SIZE_8821C + + (skb->data + desc_size + pattrib->drvinfo_sz + pattrib->shift_sz), skb) == _FAIL) { @@ -257,25 +255,13 @@ static void rtl8821ce_rx_mpdu(_adapter *padapter) if (pattrib->pkt_rpt_type == NORMAL_RX) { /* Normal rx packet */ - if (pattrib->physt) - pphy_info = (u8 *)(skb->data) + - HALMAC_RX_DESC_SIZE_8821C; - -#ifdef CONFIG_CONCURRENT_MODE - pre_recv_entry(precvframe, pphy_info); -#endif - - if (pattrib->physt && pphy_info) - rx_query_phy_status(precvframe, - pphy_info); + pre_recv_entry(precvframe, pattrib->physt ? ((u8 *)(skb->data) + desc_size) : NULL); - rtw_recv_entry(precvframe); } else { if (pattrib->pkt_rpt_type == C2H_PACKET) + c2h_pre_handler_rtl8821c(padapter, skb->data, desc_size + pattrib->pkt_len); - /*To be checked for 8821CE*/ - c2h_pre_handler_rtl8821c(padapter, skb->data, HALMAC_RX_DESC_SIZE_8821C + pattrib->pkt_len); - rtw_free_recvframe(precvframe, pfree_recv_queue); + rtw_free_recvframe(precvframe, pfree_recv_queue); } *((dma_addr_t *) skb->cb) = pci_map_single(pdvobjpriv->ppcidev, @@ -287,6 +273,9 @@ static void rtl8821ce_rx_mpdu(_adapter *padapter) SET_RX_BD_PHYSICAL_ADDR_LOW(rx_bd, *((dma_addr_t *)skb->cb)); +#ifdef CONFIG_64BIT_DMA + SET_RX_BD_PHYSICAL_ADDR_HIGH(rx_bd, (*((dma_addr_t *)skb->cb)>>32)); +#endif SET_RX_BD_RXBUFFSIZE(rx_bd, r_priv->rxbuffersize); r_priv->rx_ring[rx_q_idx].idx = @@ -324,7 +313,7 @@ static void rtl8821ce_xmit_beacon(PADAPTER Adapter) #if defined(CONFIG_AP_MODE) && defined(CONFIG_NATIVEAP_MLME) struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + if (MLME_IS_AP(Adapter) || MLME_IS_MESH(Adapter)) { /* send_beacon(Adapter); */ if (pmlmepriv->update_bcn == _TRUE) tx_beacon_hdl(Adapter, NULL); @@ -422,6 +411,9 @@ int rtl8821ce_init_rxbd_ring(_adapter *padapter) SET_RX_BD_TOTALRXPKTSIZE(rx_desc, 0); SET_RX_BD_RXBUFFSIZE(rx_desc, r_priv->rxbuffersize); SET_RX_BD_PHYSICAL_ADDR_LOW(rx_desc, *mapping); +#ifdef CONFIG_64BIT_DMA + SET_RX_BD_PHYSICAL_ADDR_HIGH(rx_desc, *mapping >> 32); +#endif buf_desc_debug("RX:rx buffer desc addr[%d] = %x, skb(rx_buf) = %x, buffer addr (virtual = %x, physical = %x)\n", i, (u32)&r_priv->rx_ring[rx_queue_idx].buf_desc[i], diff --git a/hal/rtl8821c/pci/rtl8821ce_xmit.c b/hal/rtl8821c/pci/rtl8821ce_xmit.c index 60209eb..5d6a87f 100755 --- a/hal/rtl8821c/pci/rtl8821ce_xmit.c +++ b/hal/rtl8821c/pci/rtl8821ce_xmit.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8821CE_XMIT_C_ #include /* PADAPTER, rtw_xmit.h and etc. */ @@ -59,7 +54,7 @@ s32 rtl8821ce_init_xmit_priv(_adapter *padapter) (void(*)(unsigned long))rtl8821ce_xmit_tasklet, (unsigned long)padapter); #endif - + rtl8821c_init_xmit_priv(padapter); return ret; } @@ -141,7 +136,7 @@ static u8 *get_txbd(_adapter *padapter, u8 q_idx) /* * Get txbd reg addr according to q_sel */ -static u16 get_txbd_rw_reg(u16 q_idx) +u16 get_txbd_rw_reg(u16 q_idx) { u16 txbd_reg_addr = REG_BEQ_TXBD_IDX; @@ -311,7 +306,6 @@ static void rtl8821ce_update_txbd(struct xmit_frame *pxmitframe, page_size_length++; } -#if 1 /* * Reset all tx buffer desciprtor content * -- Reset first element @@ -338,6 +332,10 @@ static void rtl8821ce_update_txbd(struct xmit_frame *pxmitframe, /* starting addr of TXDESC */ SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, mapping); +#ifdef CONFIG_64BIT_DMA + SET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd, mapping >> 32); +#endif + /* * It is assumed that in linux implementation, packet is coalesced * in only one buffer. Extension mode is not supported here @@ -347,6 +345,9 @@ static void rtl8821ce_update_txbd(struct xmit_frame *pxmitframe, SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(txbd, 1, 0); SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(txbd, 1, mapping + TX_WIFI_INFO_SIZE); /* pkt */ +#ifdef CONFIG_64BIT_DMA + SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(txbd, 1, + (mapping + TX_WIFI_INFO_SIZE) >> 32); /* pkt */ #endif /*buf_desc_debug("TX:%s, txbd = 0x%p\n", __FUNCTION__, txbd);*/ @@ -373,6 +374,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, s32 sz) sint bmcst = IS_MCAST(pattrib->ra); u16 SWDefineContent = 0x0; u8 DriverFixedRate = 0x0; + u8 hw_port = rtw_hal_get_port(padapter); ptxdesc = pxmitframe->buf_addr; _rtw_memset(ptxdesc, 0, TXDESC_SIZE); @@ -383,11 +385,22 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, s32 sz) /*SET_TX_DESC_OWN_8812(ptxdesc, 1);*/ SET_TX_DESC_TXPKTSIZE_8821C(ptxdesc, sz); - SET_TX_DESC_OFFSET_8821C(ptxdesc, TXDESC_SIZE); - + /* TX_DESC is not included in the data, + * driver needs to fill in the TX_DESC with qsel=h2c + * Offset in TX_DESC should be set to 0. + */ #ifdef CONFIG_TX_EARLY_MODE SET_TX_DESC_PKT_OFFSET_8812(ptxdesc, 1); - SET_TX_DESC_OFFSET_8821C(ptxdesc, TXDESC_SIZE + EARLY_MODE_INFO_SIZE); + if (pattrib->qsel == HALMAC_TXDESC_QSEL_H2C_CMD) + SET_TX_DESC_OFFSET_8821C(ptxdesc, 0); + else + SET_TX_DESC_OFFSET_8821C(ptxdesc, + TXDESC_SIZE + EARLY_MODE_INFO_SIZE); +#else + if (pattrib->qsel == HALMAC_TXDESC_QSEL_H2C_CMD) + SET_TX_DESC_OFFSET_8821C(ptxdesc, 0); + else + SET_TX_DESC_OFFSET_8821C(ptxdesc, TXDESC_SIZE); #endif if (bmcst) @@ -400,10 +413,10 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, s32 sz) if (!pattrib->qos_en) { /* Hw set sequence number */ + SET_TX_DESC_DISQSELSEQ_8821C(ptxdesc, 1); SET_TX_DESC_EN_HWSEQ_8821C(ptxdesc, 1); + SET_TX_DESC_HW_SSN_SEL_8821C(ptxdesc, pattrib->hw_ssn_sel); SET_TX_DESC_EN_HWEXSEQ_8821C(ptxdesc, 0); - SET_TX_DESC_DISQSELSEQ_8821C(ptxdesc, 1); - SET_TX_DESC_HW_SSN_SEL_8821C(ptxdesc, 0); } else SET_TX_DESC_SW_SEQ_8821C(ptxdesc, pattrib->seqnum); @@ -415,6 +428,9 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, s32 sz) if (bmcst) fill_txdesc_force_bmc_camid(pattrib, ptxdesc); #endif +#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR + rtw_phydm_set_dyntxpwr(padapter, ptxdesc, pattrib->mac_id); +#endif if ((pattrib->ether_type != 0x888e) && (pattrib->ether_type != 0x0806) && @@ -466,6 +482,10 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, s32 sz) pHalData->INIDATA_RATE[pattrib->mac_id] & 0x7F); } + if (bmcst) { + DriverFixedRate = 0x01; + fill_txdesc_bmc_tx_rate(pattrib, ptxdesc); + } if (padapter->fix_rate != 0xFF) { /* modify data rate by iwpriv */ @@ -486,6 +506,12 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, s32 sz) SET_TX_DESC_DATA_LDPC_8821C(ptxdesc, 1); if (pattrib->stbc) SET_TX_DESC_DATA_STBC_8821C(ptxdesc, 1); + +#ifdef CONFIG_WMMPS_STA + if (pattrib->trigger_frame) + SET_TX_DESC_TRI_FRAME_8821C (ptxdesc, 1); +#endif /* CONFIG_WMMPS_STA */ + } else { /* * EAP data packet and ARP packet and DHCP. @@ -519,6 +545,7 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, s32 sz) #endif /* CONFIG_XMIT_ACK */ #endif } else if ((pxmitframe->frame_tag & 0x0f) == MGNT_FRAMETAG) { + SET_TX_DESC_MBSSID_8821C(ptxdesc, pattrib->mbssid & 0xF); SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1); DriverFixedRate = 0x01; @@ -572,8 +599,8 @@ static s32 update_txdesc(struct xmit_frame *pxmitframe, s32 sz) SET_TX_DESC_SW_DEFINE_8821C(ptxdesc, SWDefineContent); - SET_TX_DESC_PORT_ID_8821C(ptxdesc, get_hw_port(padapter)); - SET_TX_DESC_MULTIPLE_PORT_8821C(ptxdesc, get_hw_port(padapter)); + SET_TX_DESC_PORT_ID_8821C(ptxdesc, hw_port); + SET_TX_DESC_MULTIPLE_PORT_8821C(ptxdesc, hw_port); rtl8821c_cal_txdesc_chksum(padapter, ptxdesc); rtl8821c_dbg_dump_tx_desc(padapter, pxmitframe->frame_tag, ptxdesc); @@ -596,13 +623,13 @@ s32 rtl8821ce_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe) struct rtw_tx_ring *ptx_ring; - +#ifdef CONFIG_80211N_HT if ((pxmitframe->frame_tag == DATA_FRAMETAG) && (pxmitframe->attrib.ether_type != 0x0806) && (pxmitframe->attrib.ether_type != 0x888e) && (pxmitframe->attrib.dhcp_pkt != 1)) rtw_issue_addbareq_cmd(padapter, pxmitframe); - +#endif /* CONFIG_80211N_HT */ for (t = 0; t < pattrib->nr_frags; t++) { if (inner_ret != _SUCCESS && ret == _SUCCESS) @@ -659,6 +686,10 @@ s32 rtl8821ce_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe) wmb(); fill_txbd_own(padapter, txbd, ff_hwaddr, ptx_ring); +#ifdef DBG_TXBD_DESC_DUMP + if (pxmitpriv->dump_txbd_desc) + rtw_tx_desc_backup(padapter, pxmitframe, TX_WIFI_INFO_SIZE, ff_hwaddr); +#endif _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz, @@ -709,14 +740,126 @@ static u8 check_nic_enough_desc_all(_adapter *padapter) return status; } +static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib) +{ + u32 prio; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_tx_ring *ring; + + switch (pattrib->qsel) { + case 0: + case 3: + prio = BE_QUEUE_INX; + break; + case 1: + case 2: + prio = BK_QUEUE_INX; + break; + case 4: + case 5: + prio = VI_QUEUE_INX; + break; + case 6: + case 7: + prio = VO_QUEUE_INX; + break; + default: + prio = BE_QUEUE_INX; + break; + } + + ring = &pxmitpriv->tx_ring[prio]; + + /* + * for now we reserve two free descriptor as a safety boundary + * between the tail and the head + */ + if ((ring->entries - ring->qlen) >= 2) + return _TRUE; + else + return _FALSE; +} + +#ifdef CONFIG_XMIT_THREAD_MODE +/* + * Description + * Transmit xmitbuf to hardware tx fifo + * + * Return + * _SUCCESS ok + * _FAIL something error + */ +s32 rtl8821ce_xmit_buf_handler(_adapter *padapter) +{ + PHAL_DATA_TYPE phal; + struct xmit_priv *pxmitpriv; + struct xmit_buf *pxmitbuf; + struct xmit_frame *pxmitframe; + s32 ret; + + phal = GET_HAL_DATA(padapter); + pxmitpriv = &padapter->xmitpriv; + + ret = _rtw_down_sema(&pxmitpriv->xmit_sema); + + if (ret == _FAIL) { + RTW_ERR("%s: down XmitBufSema fail!\n", __FUNCTION__); + return _FAIL; + } + + if (RTW_CANNOT_RUN(padapter)) { + RTW_INFO("%s: bDriverStopped(%s) bSurpriseRemoved(%s)!\n" + , __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False"); + return _FAIL; + } + + if (check_pending_xmitbuf(pxmitpriv) == _FALSE) + return _SUCCESS; + +#ifdef CONFIG_LPS_LCLK + ret = rtw_register_tx_alive(padapter); + if (ret != _SUCCESS) { + RTW_INFO("%s: wait to leave LPS_LCLK\n", __FUNCTION__); + return _SUCCESS; + } +#endif + + do { + pxmitbuf = select_and_dequeue_pending_xmitbuf(padapter); + + if (pxmitbuf == NULL) + break; + pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; + + if (check_nic_enough_desc(padapter, &pxmitframe->attrib) == _FALSE) { + enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf); + break; + } + rtl8821ce_dump_xframe(padapter, pxmitframe); + } while (1); + + + return _SUCCESS; +} +#endif + static s32 xmitframe_direct(_adapter *padapter, struct xmit_frame *pxmitframe) { +#ifdef CONFIG_XMIT_THREAD_MODE + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; +#endif s32 res = _SUCCESS; res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); - if (res == _SUCCESS) + if (res == _SUCCESS) { + #ifdef CONFIG_XMIT_THREAD_MODE + enqueue_pending_xmitbuf(pxmitpriv, pxmitframe->pxmitbuf); + #else rtl8821ce_dump_xframe(padapter, pxmitframe); - + #endif + } return res; } @@ -729,18 +872,16 @@ static s32 xmitframe_amsdu_direct(_adapter *padapter, struct xmit_frame *pxmitfr res = rtw_xmitframe_coalesce_amsdu(padapter, pxmitframe, NULL); - if (res == _FAIL) - goto free_frame; - res = rtl8821ce_dump_xframe(padapter, pxmitframe); - - if (res == _FAIL) - goto free_frame; - - return res; - -free_frame: - rtw_free_xmitbuf(pxmitpriv, pxmitbuf); - rtw_free_xmitframe(pxmitpriv, pxmitframe); + if (res == _SUCCESS) { + #ifdef CONFIG_XMIT_THREAD_MODE + enqueue_pending_xmitbuf(pxmitpriv, pxmitframe->pxmitbuf); + #else + res = rtl8821ce_dump_xframe(padapter, pxmitframe); + #endif + } else { + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + } return res; } @@ -778,8 +919,10 @@ void rtl8821ce_xmitframe_resume(_adapter *padapter) break; } + #ifndef CONFIG_XMIT_THREAD_MODE if (!check_nic_enough_desc_all(padapter)) break; + #endif pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); if (!pxmitbuf) @@ -799,9 +942,6 @@ void rtl8821ce_xmitframe_resume(_adapter *padapter) pattrib = &pxmitframe->attrib; - if (IS_AMSDU_AMPDU_NOT_VALID(pattrib)) - goto dump_pkt; - if (tx_amsdu == 1) { pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); @@ -887,14 +1027,6 @@ void rtl8821ce_xmitframe_resume(_adapter *padapter) xmitframe_amsdu_direct(padapter, pxmitframe); pxmitpriv->amsdu_debug_coalesce_one++; continue; - } else { - pattrib = &pxmitframe->attrib; - if (IS_AMSDU_AMPDU_NOT_VALID(pattrib)) { - rtw_free_xmitbuf(pxmitpriv, pxmitbuf_next); - xmitframe_amsdu_direct(padapter, pxmitframe); - pxmitpriv->amsdu_debug_coalesce_one++; - continue; - } } pxmitframe_next->pxmitbuf = pxmitbuf_next; @@ -906,7 +1038,11 @@ void rtl8821ce_xmitframe_resume(_adapter *padapter) rtw_free_xmitframe(pxmitpriv, pxmitframe); rtw_free_xmitbuf(pxmitpriv, pxmitbuf); +#ifdef CONFIG_XMIT_THREAD_MODE + enqueue_pending_xmitbuf(pxmitpriv, pxmitframe_next->pxmitbuf); +#else rtl8821ce_dump_xframe(padapter, pxmitframe_next); +#endif pxmitpriv->amsdu_debug_coalesce_two++; continue; @@ -940,9 +1076,13 @@ void rtl8821ce_xmitframe_resume(_adapter *padapter) } - if (res == _SUCCESS) + if (res == _SUCCESS) { + #ifdef CONFIG_XMIT_THREAD_MODE + enqueue_pending_xmitbuf(pxmitpriv, pxmitframe->pxmitbuf); + #else rtl8821ce_dump_xframe(padapter, pxmitframe); - else { + #endif + } else { rtw_free_xmitbuf(pxmitpriv, pxmitbuf); rtw_free_xmitframe(pxmitpriv, pxmitframe); } @@ -955,46 +1095,6 @@ void rtl8821ce_xmitframe_resume(_adapter *padapter) } } -static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib) -{ - u32 prio; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct rtw_tx_ring *ring; - - switch (pattrib->qsel) { - case 0: - case 3: - prio = BE_QUEUE_INX; - break; - case 1: - case 2: - prio = BK_QUEUE_INX; - break; - case 4: - case 5: - prio = VI_QUEUE_INX; - break; - case 6: - case 7: - prio = VO_QUEUE_INX; - break; - default: - prio = BE_QUEUE_INX; - break; - } - - ring = &pxmitpriv->tx_ring[prio]; - - /* - * for now we reserve two free descriptor as a safety boundary - * between the tail and the head - */ - if ((ring->entries - ring->qlen) >= 2) - return _TRUE; - else - return _FALSE; -} - /* * Return * _TRUE dump packet directly @@ -1015,12 +1115,16 @@ static s32 pre_xmitframe(_adapter *padapter, struct xmit_frame *pxmitframe) #endif _enter_critical_bh(&pxmitpriv->lock, &irqL); - if ((rtw_txframes_sta_ac_pending(padapter, pattrib) > 0) || - (check_nic_enough_desc(padapter, pattrib) == _FALSE)) + if (rtw_txframes_sta_ac_pending(padapter, pattrib) > 0) + goto enqueue; + +#ifndef CONFIG_XMIT_THREAD_MODE + if (check_nic_enough_desc(padapter, pattrib) == _FALSE) goto enqueue; if (rtw_xmit_ac_blocked(padapter) == _TRUE) goto enqueue; +#endif if (DEV_STA_LG_NUM(padapter->dvobj)) goto enqueue; @@ -1081,7 +1185,22 @@ static s32 pre_xmitframe(_adapter *padapter, struct xmit_frame *pxmitframe) s32 rtl8821ce_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) { + +#ifdef CONFIG_XMIT_THREAD_MODE + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct pkt_attrib *pattrib = &pmgntframe->attrib; + s32 ret = _SUCCESS; + + /* For FW download rsvd page and H2C pkt */ + if ((pattrib->qsel == QSLT_CMD) || (pattrib->qsel == QSLT_BEACON)) + ret = rtl8821ce_dump_xframe(padapter, pmgntframe); + else + enqueue_pending_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + return ret; + +#else return rtl8821ce_dump_xframe(padapter, pmgntframe); +#endif } /* @@ -1158,6 +1277,7 @@ void rtl8821ce_free_txbd_ring(_adapter *padapter, unsigned int prio) struct rtw_tx_ring *ring = &t_priv->tx_ring[prio]; u8 *txbd; struct xmit_buf *pxmitbuf; + dma_addr_t mapping; while (ring->qlen) { @@ -1170,8 +1290,12 @@ void rtl8821ce_free_txbd_ring(_adapter *padapter, unsigned int prio) pxmitbuf = rtl8821ce_dequeue_xmitbuf(ring); if (pxmitbuf) { + mapping = GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd); + #ifdef CONFIG_64BIT_DMA + mapping |= (dma_addr_t)GET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd) << 32; + #endif pci_unmap_single(pdev, - GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd), + mapping, pxmitbuf->len, PCI_DMA_TODEVICE); rtw_free_xmitbuf(t_priv, pxmitbuf); @@ -1291,7 +1415,13 @@ void rtl8821ce_tx_isr(PADAPTER Adapter, int prio) u8 *tx_desc; u16 tmp_4bytes; u16 desc_idx_hw = 0, desc_idx_host = 0; + dma_addr_t mapping; +#ifdef CONFIG_LPS_LCLK + int index; + s32 enter32k = _SUCCESS; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); +#endif while (ring->qlen) { tx_desc = (u8 *)&ring->buf_desc[ring->idx]; @@ -1308,8 +1438,12 @@ void rtl8821ce_tx_isr(PADAPTER Adapter, int prio) pxmitbuf = rtl8821ce_dequeue_xmitbuf(ring); if (pxmitbuf) { + mapping = GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc); + #ifdef CONFIG_64BIT_DMA + mapping |= (dma_addr_t)GET_TX_BD_PHYSICAL_ADDR0_HIGH(tx_desc) << 32; + #endif pci_unmap_single(pdvobjpriv->ppcidev, - GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc), + mapping, pxmitbuf->len, PCI_DMA_TODEVICE); rtw_sctx_done(&pxmitbuf->sctx); rtw_free_xmitbuf(&(pxmitbuf->padapter->xmitpriv), @@ -1320,6 +1454,19 @@ void rtl8821ce_tx_isr(PADAPTER Adapter, int prio) } } +#ifdef CONFIG_LPS_LCLK + for (index = 0; index < HW_QUEUE_ENTRY; index++) { + if (index != BCN_QUEUE_INX) { + if (_rtw_queue_empty(&(Adapter->xmitpriv.tx_ring[index].queue)) == _FALSE) { + enter32k = _FAIL; + break; + } + } + } + if (enter32k) + _set_workitem(&(pwrpriv->dma_event)); +#endif + if (check_tx_desc_resource(Adapter, prio) && rtw_xmit_ac_blocked(Adapter) != _TRUE) rtw_mi_xmit_tasklet_schedule(Adapter); @@ -1336,6 +1483,11 @@ void rtl8821ce_tx_isr(PADAPTER Adapter, int prio) u16 tmp_4bytes; u16 desc_idx_hw = 0, desc_idx_host = 0; +#ifdef CONFIG_LPS_LCLK + int index; + s32 enter32k = _SUCCESS; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); +#endif while (ring->qlen) { tx_desc = (u8 *)&ring->buf_desc[ring->idx]; @@ -1362,8 +1514,13 @@ void rtl8821ce_tx_isr(PADAPTER Adapter, int prio) pxmitbuf = rtl8821ce_dequeue_xmitbuf(ring); if (pxmitbuf) { + dma_addr_t mapping; + mapping = GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc); + #ifdef CONFIG_64BIT_DMA + mapping |= (dma_addr_t)GET_TX_BD_PHYSICAL_ADDR0_HIGH(tx_desc) << 32; + #endif pci_unmap_single(pdvobjpriv->ppcidev, - GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc), + mapping, pxmitbuf->len, PCI_DMA_TODEVICE); rtw_sctx_done(&pxmitbuf->sctx); rtw_free_xmitbuf(&(pxmitbuf->padapter->xmitpriv), @@ -1374,6 +1531,19 @@ void rtl8821ce_tx_isr(PADAPTER Adapter, int prio) } } +#ifdef CONFIG_LPS_LCLK + for (index = 0; index < HW_QUEUE_ENTRY; index++) { + if (index != BCN_QUEUE_INX) { + if (_rtw_queue_empty(&(Adapter->xmitpriv.tx_ring[index].queue)) == _FALSE) { + enter32k = _FAIL; + break; + } + } + } + if (enter32k) + _set_workitem(&(pwrpriv->dma_event)); +#endif + if ((prio != BCN_QUEUE_INX) && check_tx_desc_resource(Adapter, prio) && rtw_xmit_ac_blocked(Adapter) != _TRUE) rtw_mi_xmit_tasklet_schedule(Adapter); diff --git a/hal/rtl8821c/rtl8821c.h b/hal/rtl8821c/rtl8821c.h index 25baa38..13e25ed 100644 --- a/hal/rtl8821c/rtl8821c.h +++ b/hal/rtl8821c/rtl8821c.h @@ -1,22 +1,17 @@ /****************************************************************************** -* -* Copyright(c) 2016 Realtek Corporation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of version 2 of the GNU General Public License as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License along with -* this program; if not, write to the Free Software Foundation, Inc., -* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA -* -* -******************************************************************************/ + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef _RTL8821C_H_ #define _RTL8821C_H_ @@ -25,6 +20,7 @@ #include /* struct pkt_attrib, struct xmit_frame */ #include /* struct recv_frame */ #include /* HAL_DEF_VARIABLE */ +#include #define DRIVER_EARLY_INT_TIME_8821C 0x05 #define BCN_DMA_ATIME_INT_TIME_8821C 0x02 @@ -43,11 +39,6 @@ u8 rtl8821c_phy_init(PADAPTER adapter); u8 rtl8821c_init_phy_parameter_mac(PADAPTER adapter); /* rtl8821c_mac.c */ -u8 rtl8821c_rcr_config(PADAPTER, u32 rcr); -u8 rtl8821c_rcr_get(PADAPTER, u32 *rcr); -u8 rtl8821c_rcr_check(PADAPTER, u32 check_bit); -u8 rtl8821c_rcr_add(PADAPTER, u32 add); -u8 rtl8821c_rcr_clear(PADAPTER, u32 clear); #ifdef CONFIG_XMIT_ACK u8 rtl8821c_set_mgnt_xmit_ack(_adapter *adapter); #endif @@ -58,17 +49,23 @@ u8 rtl8821c_rx_tsf_addr_filter_config(_adapter *adapter, u8 config); s32 rtl8821c_fw_dl(PADAPTER, u8 wowlan); s32 rtl8821c_fw_mem_dl(PADAPTER adapter, enum fw_mem mem); +#define BIT_PRETXERR_HANDLE_IMR BIT(31) +#define BIT_PRETXERR_HANDLE_ISR BIT(31) + +#ifdef CONFIG_AMPDU_PRETX_CD +#define BIT_PRETXERR BIT(7) + +void rtl8821c_pretx_cd_config(_adapter *adapter); +#endif /* rtl8821c_ops.c */ u8 rtl8821c_read_efuse(PADAPTER); void rtl8821c_run_thread(PADAPTER); void rtl8821c_cancel_thread(PADAPTER); -void rtl8821c_sethwreg(PADAPTER, u8 variable, u8 *pval); +u8 rtl8821c_sethwreg(PADAPTER, u8 variable, u8 *pval); void rtl8821c_gethwreg(PADAPTER, u8 variable, u8 *pval); u8 rtl8821c_sethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval); u8 rtl8821c_gethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval); void rtl8821c_set_hal_ops(PADAPTER); -void rtl8821c_resume_tx_beacon(PADAPTER); -void rtl8821c_stop_tx_beacon(PADAPTER); /* tx */ void rtl8821c_init_xmit_priv(_adapter *adapter); @@ -83,6 +80,7 @@ void rtl8821c_dbg_dump_tx_desc(PADAPTER, int frame_tag, u8 *ptxdesc); #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); /* rx */ void rtl8821c_rxdesc2attribute(struct rx_pkt_attrib *a, u8 *desc); @@ -90,11 +88,8 @@ void rtl8821c_query_rx_desc(union recv_frame *, u8 *pdesc); /* rtl8821c_cmd.c */ s32 rtl8821c_fillh2ccmd(PADAPTER, u8 id, u32 buf_len, u8 *pbuf); -void rtl8821c_set_FwMacIdConfig_cmd(PADAPTER , u64 bitmap, u8 *arg, u8 bw); -void rtl8821c_set_FwRssiSetting_cmd(PADAPTER, u8 *param); void rtl8821c_set_FwPwrMode_cmd(PADAPTER, u8 psmode); void rtl8821c_set_FwPwrModeInIPS_cmd(PADAPTER adapter, u8 cmd_param); -void rtl8821c_fw_update_beacon_cmd(PADAPTER); void c2h_handler_rtl8821c(_adapter *adapter, u8 *pbuf, u16 length); void c2h_pre_handler_rtl8821c(_adapter *adapter, u8 *pbuf, s32 length); #ifdef CONFIG_BT_COEXIST @@ -104,13 +99,18 @@ void rtl8821c_download_BTCoex_AP_mode_rsvd_page(PADAPTER); /* rtl8821c_phy.c */ u32 rtl8821c_read_bb_reg(PADAPTER, u32 addr, u32 mask); void rtl8821c_write_bb_reg(PADAPTER, u32 addr, u32 mask, u32 val); -u32 rtl8821c_read_rf_reg(PADAPTER, u8 path, u32 addr, u32 mask); -void rtl8821c_write_rf_reg(PADAPTER, u8 path, u32 addr, u32 mask, u32 val); -void rtl8821c_set_channel_bw(PADAPTER, u8 center_ch, CHANNEL_WIDTH, u8 offset40, u8 offset80); +u32 rtl8821c_read_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask); +void rtl8821c_write_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask, u32 val); +void rtl8821c_set_channel_bw(PADAPTER adapter, u8 center_ch, enum channel_width, u8 offset40, u8 offset80); void rtl8821c_set_tx_power_level(PADAPTER, u8 channel); void rtl8821c_get_tx_power_level(PADAPTER, s32 *power); -void rtl8821c_set_tx_power_index(PADAPTER, u32 powerindex, u8 rfpath, u8 rate); -u8 rtl8821c_get_tx_power_index(PADAPTER, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); +void rtl8821c_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate); +u8 rtl8821c_get_tx_power_index(PADAPTER adapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); void rtl8821c_notch_filter_switch(PADAPTER, bool enable); - +#ifdef CONFIG_BEAMFORMING +void rtl8821c_phy_bf_init(PADAPTER); +void rtl8821c_phy_bf_enter(PADAPTER, struct sta_info*); +void rtl8821c_phy_bf_leave(PADAPTER, u8 *addr); +void rtl8821c_phy_bf_set_gid_table(PADAPTER, struct beamformer_entry*); +#endif /* CONFIG_BEAMFORMING */ #endif /* _RTL8821C_H_ */ diff --git a/hal/rtl8821c/rtl8821c_cmd.c b/hal/rtl8821c/rtl8821c_cmd.c index 11c77a8..5974b10 100644 --- a/hal/rtl8821c/rtl8821c_cmd.c +++ b/hal/rtl8821c/rtl8821c_cmd.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8821C_CMD_C_ #include /* HAL_DATA_TYPE */ @@ -73,7 +68,7 @@ s32 rtl8821c_fillh2ccmd(PADAPTER adapter, u8 id, u32 buf_len, u8 *pbuf) _rtw_memcpy(h2c + 1, pbuf, buf_len); err = rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); - if (_SUCCESS == err) + if (!err) ret = _SUCCESS; exit: @@ -81,117 +76,6 @@ s32 rtl8821c_fillh2ccmd(PADAPTER adapter, u8 id, u32 buf_len, u8 *pbuf) return ret; } -static void rtl8821c_set_FwRsvdPage_cmd(PADAPTER adapter, PRSVDPAGE_LOC rsvdpageloc) -{ - u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; - - - RTW_INFO(FUNC_ADPT_FMT ": ProbeRsp=%d PsPoll=%d Null=%d QoSNull=%d BTNull=%d\n", - FUNC_ADPT_ARG(adapter), - rsvdpageloc->LocProbeRsp, rsvdpageloc->LocPsPoll, - rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull, - rsvdpageloc->LocBTQosNull); - - RSVD_PAGE_SET_CMD_ID(h2c, CMD_ID_RSVD_PAGE); - RSVD_PAGE_SET_CLASS(h2c, CLASS_RSVD_PAGE); - RSVD_PAGE_SET_LOC_PROBE_RSP(h2c, rsvdpageloc->LocProbeRsp); - RSVD_PAGE_SET_LOC_PS_POLL(h2c, rsvdpageloc->LocPsPoll); - RSVD_PAGE_SET_LOC_NULL_DATA(h2c, rsvdpageloc->LocNullData); - RSVD_PAGE_SET_LOC_QOS_NULL(h2c, rsvdpageloc->LocQosNull); - RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c, rsvdpageloc->LocBTQosNull); - - RTW_DBG_DUMP("H2C-RsvdPage Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); - rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); -} - -static void rtl8821c_set_FwAoacRsvdPage_cmd(PADAPTER adapter, PRSVDPAGE_LOC rsvdpageloc) -{ -#ifdef CONFIG_WOWLAN - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - u8 res = 0, count = 0; - u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; - - - RTW_INFO(FUNC_ADPT_FMT ": RWC=%d ArpRsp=%d NbrAdv=%d GtkRsp=%d GtkInfo=%d ProbeReq=%d NetworkList=%d\n", - FUNC_ADPT_ARG(adapter), - rsvdpageloc->LocRemoteCtrlInfo, rsvdpageloc->LocArpRsp, - rsvdpageloc->LocNbrAdv, rsvdpageloc->LocGTKRsp, - rsvdpageloc->LocGTKInfo, rsvdpageloc->LocProbeReq, - rsvdpageloc->LocNetList); - - if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { - AOAC_RSVD_PAGE_SET_CMD_ID(h2c, CMD_ID_AOAC_RSVD_PAGE); - AOAC_RSVD_PAGE_SET_CLASS(h2c, CLASS_AOAC_RSVD_PAGE); - AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(h2c, rsvdpageloc->LocRemoteCtrlInfo); - AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(h2c, rsvdpageloc->LocArpRsp); - AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(h2c, rsvdpageloc->LocGTKRsp); - AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(h2c, rsvdpageloc->LocGTKInfo); -#ifdef CONFIG_GTK_OL - AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(h2c, rsvdpageloc->LocGTKEXTMEM); -#endif /* CONFIG_GTK_OL */ - RTW_DBG_DUMP("H2C-AoacRsvdPage Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); - rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); - } else { -#ifdef CONFIG_PNO_SUPPORT - if (!pwrpriv->wowlan_in_resume) { - RTW_INFO("%s: NLO_INFO=%d\n", __FUNCTION__, rsvdpageloc->LocPNOInfo); - AOAC_RSVD_PAGE3_SET_CMD_ID(h2c, CMD_ID_AOAC_RSVD_PAGE3); - AOAC_RSVD_PAGE3_SET_CLASS(h2c, CLASS_AOAC_RSVD_PAGE3); - AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(h2c, rsvdpageloc->LocPNOInfo); - RTW_DBG_DUMP("H2C-AoacRsvdPage3 Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); - rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); - rtw_msleep_os(10); - } -#endif /* CONFIG_PNO_SUPPORT */ - } -#endif /* CONFIG_WOWLAN */ -} - -static void rtl8821c_set_FwKeepAlive_cmd(PADAPTER adapter, u8 benable, u8 pkt_type) -{ - u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; - u8 adopt = 1; -#ifdef CONFIG_PLATFORM_INTEL_BYT - u8 check_period = 10; -#else - u8 check_period = 5; -#endif - - - RTW_INFO(FUNC_ADPT_FMT ": benable=%d\n", FUNC_ADPT_ARG(adapter), benable); - - KEEP_ALIVE_SET_CMD_ID(h2c, CMD_ID_KEEP_ALIVE); - KEEP_ALIVE_SET_CLASS(h2c, CLASS_KEEP_ALIVE); - KEEP_ALIVE_SET_ENABLE(h2c, benable); - KEEP_ALIVE_SET_ADOPT_USER_SETTING(h2c, adopt); - KEEP_ALIVE_SET_PKT_TYPE(h2c, pkt_type); - KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(h2c, check_period); - - RTW_DBG_DUMP("H2C-KeepAlive Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); - rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); -} - -static void rtl8821c_set_FwDisconDecision_cmd(PADAPTER adapter, u8 benable) -{ - u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; - u8 adopt = 1, check_period = 10, trypkt_num = 0; - - - RTW_INFO(FUNC_ADPT_FMT ": benable=%d\n", - FUNC_ADPT_ARG(adapter), benable); - - DISCONNECT_DECISION_SET_CMD_ID(h2c, CMD_ID_DISCONNECT_DECISION); - DISCONNECT_DECISION_SET_CLASS(h2c, CLASS_DISCONNECT_DECISION); - DISCONNECT_DECISION_SET_ENABLE(h2c, benable); - DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(h2c, adopt); - DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(h2c, check_period); - DISCONNECT_DECISION_SET_TRY_PKT_NUM(h2c, trypkt_num); - - RTW_DBG_DUMP("H2C-DisconDecision Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); - rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); -} - static u8 get_ra_vht_en(u32 wirelessMode, u32 bitmap) { u8 ret = 0; @@ -207,218 +91,86 @@ static u8 get_ra_vht_en(u32 wirelessMode, u32 bitmap) return ret; } -static u8 get_ra_ldpc(struct sta_info *psta) -{ - u8 en_ldpc = 0; - - if (psta != NULL) { - if (psta->mac_id == 1) - en_ldpc = 0; - else { -#ifdef CONFIG_80211AC_VHT - if (is_supported_vht(psta->wireless_mode)) { - if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_CAP_TX)) - en_ldpc = 1; - else - en_ldpc = 0; - } else if (is_supported_ht(psta->wireless_mode)) { - if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_CAP_TX)) - en_ldpc = 1; - else - en_ldpc = 0; - } else -#endif - en_ldpc = 0; - } - } - - return en_ldpc; -} - - -/* - * arg[0] = macid - * arg[1] = raid - * arg[2] = shortGIrate - * arg[3] = init_rate - */ -void rtl8821c_set_FwMacIdConfig_cmd(PADAPTER adapter, u64 mask, u8 *arg, u8 bw) -{ - HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); - struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; - struct sta_info *psta = NULL; - u8 mac_id, init_rate, raid, sgi = _FALSE; - u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; - u8 ignore_bw = _FALSE; - - if (hal->fw_ractrl == _FALSE) { - RTW_INFO(FUNC_ADPT_FMT" fw ractrl = _FALSE\n", - FUNC_ADPT_ARG(adapter)); - return; - } - - mac_id = arg[0]; - raid = arg[1]; - sgi = arg[2] & 0x0F; - ignore_bw = arg[2] >> 4; - init_rate = arg[3]; - - if (mac_id < macid_ctl->num) - psta = macid_ctl->sta[mac_id]; - - if (!psta) { - RTW_INFO(FUNC_ADPT_FMT" macid:%u, sta is NULL\n", - FUNC_ADPT_ARG(adapter), mac_id); - return; - } - - RTW_INFO(FUNC_ADPT_FMT ": mac_id=%d raid=0x%x bw=%d mask=0x%016llx\n", - FUNC_ADPT_ARG(adapter), mac_id, raid, bw, mask); - - - MACID_CFG_SET_CMD_ID(h2c, CMD_ID_MACID_CFG); - MACID_CFG_SET_CLASS(h2c, CLASS_MACID_CFG); - - /* common for h2c cmd 0x40 */ - MACID_CFG_SET_MAC_ID(h2c, mac_id); - MACID_CFG_SET_RATE_ID(h2c, raid); - -#ifdef CONFIG_LPS_PG - MACID_CFG_SET_INIT_RATE_LV(h2c, psta->lps_pg_rssi_lv); -#endif - MACID_CFG_SET_SGI(h2c, (sgi) ? 1 : 0); - MACID_CFG_SET_NO_UPDATE(h2c, (ignore_bw) ? 1 : 0); - MACID_CFG_SET_BW(h2c, bw); - MACID_CFG_SET_LDPC_CAP(h2c, get_ra_ldpc(psta)); - MACID_CFG_SET_WHT_EN(h2c, get_ra_vht_en(psta->wireless_mode, mask)); - - - /* DisableTXPowerTraining */ - if (hal->bDisableTXPowerTraining) { - MACID_CFG_SET_DISPT(h2c, 1); - RTW_INFO("%s: Disable PWT by driver\n", __FUNCTION__); - } else { - struct PHY_DM_STRUCT *pDM_OutSrc = &hal->odmpriv; - - if (pDM_OutSrc->is_disable_power_training) { - MACID_CFG_SET_DISPT(h2c, 1); - RTW_INFO("%s: Disable PWT by DM\n", __FUNCTION__); - } - } - - MACID_CFG_SET_RATE_MASK7_0(h2c, (u8)(mask & 0x000000ff)); - MACID_CFG_SET_RATE_MASK15_8(h2c, (u8)((mask & 0x0000ff00) >> 8)); - MACID_CFG_SET_RATE_MASK23_16(h2c, (u8)((mask & 0x00ff0000) >> 16)); - MACID_CFG_SET_RATE_MASK31_24(h2c, (u8)((mask & 0xff000000) >> 24)); - - RTW_INFO("%s, mask=0x%016llx, mac_id=0x%x, raid=0x%x, shortGIrate=%x, power training=%02x\n" - , __FUNCTION__, mask, mac_id, raid, sgi, h2c[2] & BIT(6)); -#ifdef CONFIG_LPS_PG - RTW_INFO("lps_pg_rssi_lv:%d\n", psta->lps_pg_rssi_lv); -#endif - RTW_DBG_DUMP("H2C-MACIDConfig Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); - rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); - - /* update initial rate */ - if (sgi) - init_rate |= BIT(7); - - hal->INIDATA_RATE[mac_id] = init_rate; -} - -void rtl8821c_set_FwRssiSetting_cmd(PADAPTER adapter, u8 *param) -{ - u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; - u8 mac_id = *param; - u8 rssi = *(param + 2); - u8 ra_info = 0; - - - RTW_INFO(FUNC_ADPT_FMT ": mac_id=%d rssi=%d param=%.2x-%.2x-%.2x\n", - FUNC_ADPT_ARG(adapter), - mac_id, rssi, *param, *(param + 1), *(param + 2)); - - RSSI_SETTING_SET_CMD_ID(h2c, CMD_ID_RSSI_SETTING); - RSSI_SETTING_SET_CLASS(h2c, CLASS_RSSI_SETTING); - RSSI_SETTING_SET_MAC_ID(h2c, mac_id); - RSSI_SETTING_SET_RSSI(h2c, rssi); - RSSI_SETTING_SET_RA_INFO(h2c, ra_info); - - RTW_DBG_DUMP("H2C-RssiSetting Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); - rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); -} - -void rtl8821c_set_FwAPReqRPT_cmd(PADAPTER adapter, u32 need_ack) -{ - u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; - u8 macid1 = 1, macid2 = 0; - - - RTW_INFO(FUNC_ADPT_FMT ": need_ack = %d\n", - FUNC_ADPT_ARG(adapter), need_ack); - - AP_REQ_TXRPT_SET_CMD_ID(h2c, CMD_ID_AP_REQ_TXRPT); - AP_REQ_TXRPT_SET_CLASS(h2c, CLASS_AP_REQ_TXRPT); - AP_REQ_TXRPT_SET_STA1_MACID(h2c, macid1); - AP_REQ_TXRPT_SET_STA2_MACID(h2c, macid2); - - RTW_DBG_DUMP("H2C-ApReqRpt Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); - rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); -} +#define SET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 5, value) +#define SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c_pkt, value) \ + SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 31, 1, value) void rtl8821c_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) { - int i; u8 mode = 0, smart_ps = 0; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); +#ifdef CONFIG_BCN_RECV_TIME + u8 bcn_recv_time; struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; +#endif +#ifdef CONFIG_WMMPS_STA + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct qos_priv *pqospriv = &pmlmepriv->qospriv; +#endif /* CONFIG_WMMPS_STA */ u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; u8 PowerState = 0, awake_intvl = 1, rlbm = 0; - u8 pwrmode_data5 = 0; + u8 allQueueUAPSD = 0; + char *fw_psmode_str = ""; #ifdef CONFIG_P2P struct wifidirect_info *wdinfo = &adapter->wdinfo; #endif /* CONFIG_P2P */ - + u8 hw_port = rtw_hal_get_port(adapter); if (pwrpriv->dtim > 0) - RTW_INFO(FUNC_ADPT_FMT ": FW LPS mode = %d, SmartPS=%d, dtim=%d, HW port id=%d\n", - FUNC_ADPT_ARG(adapter), psmode, pwrpriv->smart_ps, pwrpriv->dtim, - psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id:get_hw_port(adapter)); + RTW_INFO(FUNC_ADPT_FMT ": dtim=%d, HW port id=%d\n", FUNC_ADPT_ARG(adapter), + pwrpriv->dtim, psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id : hw_port); else - RTW_INFO(FUNC_ADPT_FMT ": FW LPS mode = %d, SmartPS=%d, HW port id=%d\n", - FUNC_ADPT_ARG(adapter), psmode, pwrpriv->smart_ps, - psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id:get_hw_port(adapter)); + RTW_INFO(FUNC_ADPT_FMT ": HW port id=%d\n", FUNC_ADPT_ARG(adapter), + psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id : hw_port); smart_ps = pwrpriv->smart_ps; switch (psmode) { case PS_MODE_MIN: - mode = 1; - rlbm = 0; - awake_intvl = 2; - break; case PS_MODE_MAX: - mode = 1; - rlbm = 1; - awake_intvl = 2; + { +#ifdef CONFIG_WMMPS_STA + if (rtw_is_wmmps_mode(adapter)) { + mode = 2; + + smart_ps = pwrpriv->wmm_smart_ps; + + /* (WMMPS) allQueueUAPSD: 0: PSPoll, 1: QosNullData (if wmm_smart_ps=1) or do nothing (if wmm_smart_ps=2) */ + if ((pqospriv->uapsd_tid & BIT_MASK_TID_TC) == ALL_TID_TC_SUPPORTED_UAPSD) + allQueueUAPSD = 1; + } else +#endif /* CONFIG_WMMPS_STA */ + { + mode = 1; +#ifdef CONFIG_WMMPS_STA + /* For WMMPS test case, the station must retain sleep mode to capture buffered data on LPS mechanism */ + if ((pqospriv->uapsd_tid & BIT_MASK_TID_TC) != 0) + smart_ps = 0; + else +#endif /* CONFIG_WMMPS_STA */ + { + smart_ps = pwrpriv->smart_ps; + } + } + + if (psmode == PS_MODE_MIN) + rlbm = 0; + else + rlbm = 1; + } break; case PS_MODE_DTIM: { mode = 1; rlbm = 2; - /* For WOWLAN LPS, DTIM = (awake_intvl - 1) */ + /* For WOWLAN LPS, DTIM = (awake_intvl - 1) */ if (pwrpriv->dtim > 0 && pwrpriv->dtim < 16) /* DTIM = (awake_intvl - 1) */ - awake_intvl = pwrpriv->dtim + 1; + awake_intvl = pwrpriv->dtim + 1; else /* DTIM = 3 */ - awake_intvl = 4; + awake_intvl = 4; } break; - case PS_MODE_UAPSD_WMM: - mode = 2; - rlbm = 0; /*1*/ - /*(WMM)smart_ps: 0:PS_Poll, 1:NullData*/ - smart_ps = (pwrpriv->smart_ps) ? 1 : 0; - break; case PS_MODE_ACTIVE: default: mode = 0; @@ -439,28 +191,25 @@ void rtl8821c_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) if (psmode > 0) { #ifdef CONFIG_BT_COEXIST - if (rtw_btcoex_IsBtControlLps(adapter) == _TRUE) { + if (rtw_btcoex_IsBtControlLps(adapter) == _TRUE) PowerState = rtw_btcoex_RpwmVal(adapter); - pwrmode_data5 = rtw_btcoex_LpsVal(adapter); - - if ((rlbm == 2) && (pwrmode_data5 & BIT(4))) { - /* - * Keep awake interval to 1 to prevent from - * decreasing coex performance - */ - awake_intvl = 2; - rlbm = 2; - } - } else + else #endif /* CONFIG_BT_COEXIST */ - { PowerState = 0x00; /* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ - pwrmode_data5 = 0x40; - } - } else { + } else PowerState = 0x0C; /* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ - pwrmode_data5 = 0x40; - } + + if (mode == 0) + fw_psmode_str = "ACTIVE"; + else if (mode == 1) + fw_psmode_str = "LPS"; + else if (mode == 2) + fw_psmode_str = "WMMPS"; + else + fw_psmode_str = "UNSPECIFIED"; + + RTW_INFO(FUNC_ADPT_FMT": fw ps mode = %s, drv ps mode = %d, rlbm = %d , smart_ps = %d, allQueueUAPSD = %d\n", + FUNC_ADPT_ARG(adapter), fw_psmode_str, psmode, rlbm, smart_ps, allQueueUAPSD); SET_PWR_MODE_SET_CMD_ID(h2c, CMD_ID_SET_PWR_MODE); SET_PWR_MODE_SET_CLASS(h2c, CLASS_SET_PWR_MODE); @@ -468,74 +217,31 @@ void rtl8821c_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) SET_PWR_MODE_SET_SMART_PS(h2c, smart_ps); SET_PWR_MODE_SET_RLBM(h2c, rlbm); SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c, awake_intvl); - SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c, adapter->registrypriv.uapsd_enable); + SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c, allQueueUAPSD); SET_PWR_MODE_SET_PWR_STATE(h2c, PowerState); if (psmode == PS_MODE_ACTIVE) { /* Leave LPS, set the same HW port ID */ SET_PWR_MODE_SET_PORT_ID(h2c, pwrpriv->current_lps_hw_port_id); } else { /* Enter LPS, record HW port ID */ - SET_PWR_MODE_SET_PORT_ID(h2c, get_hw_port(adapter)); - pwrpriv->current_lps_hw_port_id = get_hw_port(adapter); + SET_PWR_MODE_SET_PORT_ID(h2c, hw_port); + pwrpriv->current_lps_hw_port_id = hw_port; } - if (pwrmode_data5) - h2c[6] = pwrmode_data5; - else { - /* pwrmode_data5 section*/ - SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c, 0);/*bit-16*/ - SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c, 0);/*bit-17*/ - SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c, 0);/*bit-18*/ - SET_PWR_MODE_SET_PROTECT_BCN(h2c, 0);/*bit-19*/ - SET_PWR_MODE_SET_SILENCE_PERIOD(h2c, 0);/*bit-20*/ - SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c, 0);/*bit-21*/ - SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c, 0);/*bit-22*/ - } - /* pwrmode_data6 section*/ - SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c, 0);/*bit-24*/ - SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c, 0);/*bit-25:3*/ - SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c, 0);/*bit-28:4*/ +#ifdef CONFIG_BCN_RECV_TIME + if (pmlmeext->bcn_rx_time) { + bcn_recv_time = pmlmeext->bcn_rx_time / 128; + if (pmlmeext->bcn_rx_time % 128) + bcn_recv_time += 1; + if (bcn_recv_time >= 31) + bcn_recv_time = 31; + SET_PWR_MODE_SET_ADOPT_BCN_RECEIVING_TIME(h2c, 1); + SET_PWR_MODE_SET_BCN_RECEIVING_TIME(h2c, bcn_recv_time); + } +#endif RTW_INFO("%s=> psmode:%02x, smart_ps:%02x, PowerState:%02x\n", __func__, psmode, smart_ps, PowerState); -#ifdef CONFIG_LPS_LCLK - if (psmode != PS_MODE_ACTIVE) { - if ((pmlmeext->adaptive_tsf_done == _FALSE) - && (pmlmeext->bcn_cnt > 0)) { - u8 ratio_20_delay, ratio_80_delay; - - /* - * byte 6 for adaptive_early_32k - * [0:3] = DrvBcnEarly (ms), [4:7] = DrvBcnTimeOut (ms) - * 20% for DrvBcnEarly, 80% for DrvBcnTimeOut - */ - ratio_20_delay = 0; - ratio_80_delay = 0; - pmlmeext->DrvBcnEarly = 0xff; - pmlmeext->DrvBcnTimeOut = 0xff; - - for (i = 0; i < 9; i++) { - pmlmeext->bcn_delay_ratio[i] = (pmlmeext->bcn_delay_cnt[i] * 100) / pmlmeext->bcn_cnt; - - ratio_20_delay += pmlmeext->bcn_delay_ratio[i]; - ratio_80_delay += pmlmeext->bcn_delay_ratio[i]; - - if (ratio_20_delay > 20 && pmlmeext->DrvBcnEarly == 0xff) - pmlmeext->DrvBcnEarly = i; - - if (ratio_80_delay > 80 && pmlmeext->DrvBcnTimeOut == 0xff) - pmlmeext->DrvBcnTimeOut = i; - - /* reset adaptive_early_32k cnt */ - pmlmeext->bcn_delay_cnt[i] = 0; - pmlmeext->bcn_delay_ratio[i] = 0; - } - - pmlmeext->bcn_cnt = 0; - pmlmeext->adaptive_tsf_done = _TRUE; - } - } -#endif /* CONFIG_LPS_LCLK */ #ifdef CONFIG_BT_COEXIST rtw_btcoex_RecordPwrMode(adapter, h2c + 1, RTW_HALMAC_H2C_MAX_SIZE - 1); @@ -562,661 +268,21 @@ void rtl8821c_set_FwPwrModeInIPS_cmd(PADAPTER adapter, u8 cmd_param) } #ifdef CONFIG_BT_COEXIST -static void ConstructBeacon(PADAPTER adapter, u8 *pframe, u32 *pLength) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u32 rate_len, pktlen; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; - WLAN_BSSID_EX *cur_network = &pmlmeinfo->network; - u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); - - SetSeqNum(pwlanhdr, 0); - set_frame_sub_type(pframe, WIFI_BEACON); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - - /* timestamp will be inserted by hardware */ - pframe += 8; - pktlen += 8; - - /* beacon interval: 2 bytes */ - _rtw_memcpy(pframe, (u8 *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); - - pframe += 2; - pktlen += 2; - - /* capability info: 2 bytes */ - _rtw_memcpy(pframe, (u8 *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); - - pframe += 2; - pktlen += 2; - - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { - pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs); - _rtw_memcpy(pframe, cur_network->IEs + sizeof(NDIS_802_11_FIXED_IEs), pktlen); - - goto _ConstructBeacon; - } - - /* below for ad-hoc mode */ - - /* SSID */ - pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); - - /* supported rates... */ - rate_len = rtw_get_rateset_len(cur_network->SupportedRates); - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen); - - /* DS parameter set */ - pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); - - if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { - u32 ATIMWindow; - /* IBSS Parameter Set... */ - ATIMWindow = 0; - pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); - } - - /* todo: ERP IE */ - - /* EXTERNDED SUPPORTED RATE */ - if (rate_len > 8) - pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); - - - /* todo:HT for adhoc */ - -_ConstructBeacon: - - if ((pktlen + TXDESC_SIZE) > 512) { - RTW_INFO("beacon frame too large\n"); - return; - } - - *pLength = pktlen; -} - -static void ConstructPSPoll(PADAPTER adapter, u8 *pframe, u32 *pLength) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u32 pktlen; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; - - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - /* Frame control. */ - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - SetPwrMgt(fctrl); - set_frame_sub_type(pframe, WIFI_PSPOLL); - - /* AID. */ - set_duration(pframe, (pmlmeinfo->aid | 0xc000)); - - /* BSSID. */ - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - - /* TA. */ - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); - - *pLength = 16; -} - -static void ConstructNullFunctionData( - PADAPTER adapter, - u8 *pframe, - u32 *pLength, - u8 *StaAddr, - u8 bQoS, - u8 AC, - u8 bEosp, - u8 bForcePowerSave) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u32 pktlen; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct wlan_network *cur_network = &pmlmepriv->cur_network; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; - - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &pwlanhdr->frame_ctl; - *(fctrl) = 0; - if (bForcePowerSave) - SetPwrMgt(fctrl); - - switch (cur_network->network.InfrastructureMode) { - case Ndis802_11Infrastructure: - SetToDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN); - break; - case Ndis802_11APMode: - SetFrDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); - break; - case Ndis802_11IBSS: - default: - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - break; - } - - SetSeqNum(pwlanhdr, 0); - - if (bQoS == _TRUE) { - struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; - - set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); - - pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; - SetPriority(&pwlanqoshdr->qc, AC); - SetEOSP(&pwlanqoshdr->qc, bEosp); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); - } else { - set_frame_sub_type(pframe, WIFI_DATA_NULL); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - } - - *pLength = pktlen; -} - -static void ConstructProbeRsp(PADAPTER adapter, u8 *pframe, u32 *pLength, u8 *StaAddr, BOOLEAN bHideSSID) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u8 *mac, *bssid; - u32 pktlen; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; - WLAN_BSSID_EX *cur_network = &pmlmeinfo->network; -#if defined(CONFIG_AP_MODE) && defined(CONFIG_NATIVEAP_MLME) - u8 *pwps_ie; - uint wps_ielen; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; -#endif /* CONFIG_AP_MODE && CONFIG_NATIVEAP_MLME */ -#ifdef CONFIG_P2P - struct wifidirect_info *pwdinfo = &adapter->wdinfo; -#ifdef CONFIG_WFD - u32 wfdielen = 0; -#endif /* CONFIG_WFD */ -#endif /* CONFIG_P2P */ - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - mac = adapter_mac_addr(adapter); - bssid = cur_network->MacAddress; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); - - RTW_INFO("%s FW Mac Addr:" MAC_FMT "\n", __FUNCTION__, MAC_ARG(mac)); - RTW_INFO("%s FW IP Addr" IP_FMT "\n", __FUNCTION__, IP_ARG(StaAddr)); - - SetSeqNum(pwlanhdr, 0); - set_frame_sub_type(fctrl, WIFI_PROBERSP); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - pframe += pktlen; - - if (cur_network->IELength > MAX_IE_SZ) - return; - - pwps_ie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, - cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen); - - /* inerset & update wps_probe_resp_ie */ - if ((pmlmepriv->wps_probe_resp_ie != NULL) && pwps_ie && (wps_ielen > 0)) { - uint wps_offset, remainder_ielen; - u8 *premainder_ie; - - wps_offset = (uint)(pwps_ie - cur_network->IEs); - - premainder_ie = pwps_ie + wps_ielen; - - remainder_ielen = cur_network->IELength - wps_offset - wps_ielen; - - _rtw_memcpy(pframe, cur_network->IEs, wps_offset); - pframe += wps_offset; - pktlen += wps_offset; - - wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];/* to get ie data len */ - if ((wps_offset + wps_ielen + 2) <= MAX_IE_SZ) { - _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen + 2); - pframe += wps_ielen + 2; - pktlen += wps_ielen + 2; - } - - if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) { - _rtw_memcpy(pframe, premainder_ie, remainder_ielen); - pframe += remainder_ielen; - pktlen += remainder_ielen; - } - } else { - _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); - pframe += cur_network->IELength; - pktlen += cur_network->IELength; - } - - /* retrieve SSID IE from cur_network->Ssid */ - { - u8 *ssid_ie; - sint ssid_ielen = 0; - sint ssid_ielen_diff; - u8 buf[MAX_IE_SZ]; - u8 *ies = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); - - ssid_ie = rtw_get_ie(ies + _FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen, - (pframe - ies) - _FIXED_IE_LENGTH_); - - ssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen; - - if (ssid_ie && cur_network->Ssid.SsidLength) { - uint remainder_ielen; - u8 *remainder_ie; - remainder_ie = ssid_ie + 2; - remainder_ielen = (pframe - remainder_ie); - - if (remainder_ielen > MAX_IE_SZ) { - RTW_WARN(FUNC_ADPT_FMT" remainder_ielen > MAX_IE_SZ\n", FUNC_ADPT_ARG(adapter)); - remainder_ielen = MAX_IE_SZ; - } - - _rtw_memcpy(buf, remainder_ie, remainder_ielen); - _rtw_memcpy(remainder_ie + ssid_ielen_diff, buf, remainder_ielen); - *(ssid_ie + 1) = cur_network->Ssid.SsidLength; - _rtw_memcpy(ssid_ie + 2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength); - pframe += ssid_ielen_diff; - pktlen += ssid_ielen_diff; - } - } - -#ifdef CONFIG_P2P - if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { - u32 len; -#ifdef CONFIG_IOCTL_CFG80211 - if (adapter_wdev_data(adapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) { - /* if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p() */ - len = pmlmepriv->p2p_go_probe_resp_ie_len; - if (pmlmepriv->p2p_go_probe_resp_ie && len > 0) - _rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len); - } else -#endif /* CONFIG_IOCTL_CFG80211 */ - { - len = build_probe_resp_p2p_ie(pwdinfo, pframe); - } - - pframe += len; - pktlen += len; - -#ifdef CONFIG_WFD -#ifdef CONFIG_IOCTL_CFG80211 - if (_TRUE == pwdinfo->wfd_info->wfd_enable) -#endif /* CONFIG_IOCTL_CFG80211 */ - { - len = build_probe_resp_wfd_ie(pwdinfo, pframe, 0); - } -#ifdef CONFIG_IOCTL_CFG80211 - else { - len = 0; - if (pmlmepriv->wfd_probe_resp_ie && pmlmepriv->wfd_probe_resp_ie_len > 0) { - len = pmlmepriv->wfd_probe_resp_ie_len; - _rtw_memcpy(pframe, pmlmepriv->wfd_probe_resp_ie, len); - } - } -#endif /* CONFIG_IOCTL_CFG80211 */ - pframe += len; - pktlen += len; -#endif /* CONFIG_WFD */ - } -#endif /* CONFIG_P2P */ - - *pLength = pktlen; -} - -static void ConstructBtNullFunctionData( - PADAPTER adapter, - u8 *pframe, - u32 *pLength, - u8 *StaAddr, - u8 bQoS, - u8 AC, - u8 bEosp, - u8 bForcePowerSave) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u32 pktlen; - struct mlme_ext_priv *pmlmeext; - struct mlme_ext_info *pmlmeinfo; - u8 bssid[ETH_ALEN]; - - - RTW_INFO("+" FUNC_ADPT_FMT ": qos=%d eosp=%d ps=%d\n", - FUNC_ADPT_ARG(adapter), bQoS, bEosp, bForcePowerSave); - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - pmlmeext = &adapter->mlmeextpriv; - pmlmeinfo = &pmlmeext->mlmext_info; - - if (NULL == StaAddr) { - _rtw_memcpy(bssid, adapter_mac_addr(adapter), ETH_ALEN); - StaAddr = bssid; - } - - fctrl = &pwlanhdr->frame_ctl; - *fctrl = 0; - if (bForcePowerSave) - SetPwrMgt(fctrl); - - SetFrDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); - - set_duration(pwlanhdr, 0); - SetSeqNum(pwlanhdr, 0); - - if (bQoS == _TRUE) { - struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; - - set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); - - pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; - SetPriority(&pwlanqoshdr->qc, AC); - SetEOSP(&pwlanqoshdr->qc, bEosp); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); - } else { - set_frame_sub_type(pframe, WIFI_DATA_NULL); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - } - - *pLength = pktlen; -} - -static void SetFwRsvdPagePkt_BTCoex(PADAPTER adapter) -{ - PHAL_DATA_TYPE hal; - struct xmit_frame *pcmdframe; - struct pkt_attrib *pattrib; - struct xmit_priv *pxmitpriv; - struct mlme_ext_priv *pmlmeext; - struct mlme_ext_info *pmlmeinfo; - u32 BeaconLength = 0; - u32 BTQosNullLength = 0; - u8 *ReservedPagePacket; - u8 TxDescLen, TxDescOffset; - u8 TotalPageNum = 0, CurtPktPageNum = 0, RsvdPageNum = 0; - u16 BufIndex, PageSize; - u32 TotalPacketLen, MaxRsvdPageBufSize = 0; - RSVDPAGE_LOC RsvdPageLoc; - - - hal = GET_HAL_DATA(adapter); - pxmitpriv = &adapter->xmitpriv; - pmlmeext = &adapter->mlmeextpriv; - pmlmeinfo = &pmlmeext->mlmext_info; - TxDescLen = TXDESC_SIZE; - TxDescOffset = TXDESC_OFFSET; - PageSize = HALMAC_TX_PAGE_SIZE_8821C; - - RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE); - MaxRsvdPageBufSize = RsvdPageNum * PageSize; - - pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv); - if (pcmdframe == NULL) { - RTW_INFO("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); - return; - } - - ReservedPagePacket = pcmdframe->buf_addr; - _rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC)); - - /* beacon */ - BufIndex = TxDescOffset; - ConstructBeacon(adapter, &ReservedPagePacket[BufIndex], &BeaconLength); - - /* - * When we count the first page size, we need to reserve description size for the RSVD - * packet, it will be filled in front of the packet in TXPKTBUF. - */ - CurtPktPageNum = (u8)PageNum_128(TxDescLen + BeaconLength); - /* - * If we don't add 1 more page, the WOWLAN function has a problem. - * Maybe it's a bug of firmware? - */ - if (CurtPktPageNum == 1) - CurtPktPageNum += 1; - TotalPageNum += CurtPktPageNum; - - BufIndex += (CurtPktPageNum * PageSize); - - /* Jump to lastest page */ - if (BufIndex < (MaxRsvdPageBufSize - PageSize)) { - BufIndex = TxDescOffset + (MaxRsvdPageBufSize - PageSize); - TotalPageNum = RsvdPageNum - 1; - } - - /* BT Qos null data */ - RsvdPageLoc.LocBTQosNull = TotalPageNum; - ConstructBtNullFunctionData( - adapter, - &ReservedPagePacket[BufIndex], - &BTQosNullLength, - NULL, - _TRUE, 0, 0, _FALSE); - rtw_hal_fill_fake_txdesc(adapter, &ReservedPagePacket[BufIndex - TxDescLen], BTQosNullLength, _FALSE, _TRUE, _FALSE); - - CurtPktPageNum = (u8)PageNum_128(TxDescLen + BTQosNullLength); - - TotalPageNum += CurtPktPageNum; - - TotalPacketLen = BufIndex + BTQosNullLength; - if (TotalPacketLen > MaxRsvdPageBufSize) { - RTW_INFO(FUNC_ADPT_FMT ": ERROR: The rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n", - FUNC_ADPT_ARG(adapter), TotalPacketLen, MaxRsvdPageBufSize); - goto error; - } - - /* update attribute */ - pattrib = &pcmdframe->attrib; - update_mgntframe_attrib(adapter, pattrib); - pattrib->qsel = QSLT_BEACON; - pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TxDescOffset; -#ifdef CONFIG_PCI_HCI - dump_mgntframe(adapter, pcmdframe); -#else /* !CONFIG_PCI_HCI */ - dump_mgntframe_and_wait(adapter, pcmdframe, 100); -#endif /* !CONFIG_PCI_HCI */ - - rtl8821c_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc); - rtl8821c_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc); - - return; - -error: - rtw_free_xmitframe(pxmitpriv, pcmdframe); -} - void rtl8821c_download_BTCoex_AP_mode_rsvd_page(PADAPTER adapter) { - PHAL_DATA_TYPE hal; - struct mlme_ext_priv *pmlmeext; - struct mlme_ext_info *pmlmeinfo; - u8 bRecover = _FALSE; - u8 bcn_valid = _FALSE; - u8 DLBcnCount = 0; - u32 poll = 0; - u8 val8; - - - RTW_INFO("+" FUNC_ADPT_FMT ": hw_port=%d fw_state=0x%08X\n", - FUNC_ADPT_ARG(adapter), get_hw_port(adapter), get_fwstate(&adapter->mlmepriv)); - -#ifdef CONFIG_RTW_DEBUG - if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _FALSE) { - RTW_INFO(FUNC_ADPT_FMT ": [WARNING] not in AP mode!!\n", - FUNC_ADPT_ARG(adapter)); - } -#endif /* CONFIG_RTW_DEBUG */ - - hal = GET_HAL_DATA(adapter); - pmlmeext = &adapter->mlmeextpriv; - pmlmeinfo = &pmlmeext->mlmext_info; - - /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */ - rtw_write16(adapter, REG_BCN_PSR_RPT, (0xC000 | pmlmeinfo->aid)); - - /* set REG_CR bit 8 */ - val8 = rtw_read8(adapter, REG_CR + 1); - val8 |= BIT(0); /* ENSWBCN */ - rtw_write8(adapter, REG_CR + 1, val8); - - /* - * Disable Hw protection for a time which revserd for Hw sending beacon. - * Fix download reserved page packet fail that access collision with the protection time. - */ - val8 = rtw_read8(adapter, REG_BCN_CTRL); - val8 &= ~EN_BCN_FUNCTION; - val8 |= DIS_TSF_UDT; - rtw_write8(adapter, REG_BCN_CTRL, val8); - - /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ - if (hal->RegFwHwTxQCtrl & BIT(6)) - bRecover = _TRUE; - - /* To tell Hw the packet is not a real beacon frame. */ - hal->RegFwHwTxQCtrl &= ~BIT(6); - rtw_write8(adapter, REG_FWHW_TXQ_CTRL + 2, hal->RegFwHwTxQCtrl); - - /* Clear beacon valid check bit. */ - rtw_hal_set_hwreg(adapter, HW_VAR_BCN_VALID, NULL); - rtw_hal_set_hwreg(adapter, HW_VAR_DL_BCN_SEL, NULL); - - DLBcnCount = 0; - poll = 0; - do { - SetFwRsvdPagePkt_BTCoex(adapter); - DLBcnCount++; - do { - rtw_yield_os(); - - /* check rsvd page download OK. */ - rtw_hal_get_hwreg(adapter, HW_VAR_BCN_VALID, &bcn_valid); - poll++; - } while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(adapter)); - } while (!bcn_valid && (DLBcnCount <= 100) && !RTW_CANNOT_RUN(adapter)); - - if (_TRUE == bcn_valid) { - struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); - - pwrctl->fw_psmode_iface_id = adapter->iface_id; - RTW_INFO(ADPT_FMT": DL RSVD page success! DLBcnCount:%d, poll:%d\n", - ADPT_ARG(adapter), DLBcnCount, poll); - } else { - RTW_INFO(ADPT_FMT": DL RSVD page fail! DLBcnCount:%d, poll:%d\n", - ADPT_ARG(adapter), DLBcnCount, poll); - RTW_INFO(ADPT_FMT": DL RSVD page fail! bSurpriseRemoved=%s\n", - ADPT_ARG(adapter), rtw_is_surprise_removed(adapter) ? "True" : "False"); - RTW_INFO(ADPT_FMT": DL RSVD page fail! bDriverStopped=%s\n", - ADPT_ARG(adapter), rtw_is_drv_stopped(adapter) ? "True" : "False"); - } - - val8 = rtw_read8(adapter, REG_BCN_CTRL); - val8 |= EN_BCN_FUNCTION; - val8 &= ~DIS_TSF_UDT; - rtw_write8(adapter, REG_BCN_CTRL, val8); - - /* - * To make sure that if there exists an adapter which would like to send beacon. - * If exists, the origianl value of 0x422[6] will be 1, we should check this to - * prevent from setting 0x422[6] to 0 after download reserved page, or it will cause - * the beacon cannot be sent by HW. - */ - if (bRecover) { - hal->RegFwHwTxQCtrl |= BIT(6); - rtw_write8(adapter, REG_FWHW_TXQ_CTRL + 2, hal->RegFwHwTxQCtrl); - } - - /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ -#ifndef CONFIG_PCI_HCI - val8 = rtw_read8(adapter, REG_CR + 1); - val8 &= ~BIT(0); /* ~ENSWBCN*/ - rtw_write8(adapter, REG_CR + 1, val8); -#endif /* !CONFIG_PCI_HCI */ + rtl8821c_dl_rsvd_page(adapter, RT_MEDIA_CONNECT); } #endif /* CONFIG_BT_COEXIST */ -#ifdef CONFIG_TSF_RESET_OFFLOAD -/* -* ask FW to Reset sync register at Beacon early interrupt -*/ -u8 rtl8821c_reset_tsf(_adapter *adapter, u8 reset_port) -{ - u8 buf[2]; - u8 res = _SUCCESS; - - - if (HW_PORT0 == reset_port) { - buf[0] = 0x1; - buf[1] = 0; - - } else { - buf[0] = 0x0; - buf[1] = 0x1; - } - rtl8821c_fillh2ccmd(adapter, H2C_RESET_TSF, 2, buf); - - - return res; -} -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - - -void rtl8821c_fw_update_beacon_cmd(PADAPTER adapter) -{ -} - /* * Below functions are for C2H */ static void c2h_ccx_rpt(PADAPTER adapter, u8 *pdata) { #ifdef CONFIG_XMIT_ACK -#define C2H_CCX_RPT_GET_TX_STATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 30, 2) - u8 tx_state = _FALSE; + u8 tx_state; - tx_state = C2H_CCX_RPT_GET_TX_STATE(pdata); + tx_state = CCX_RPT_GET_TX_STATE(pdata); /* 0 means success, 1 means retry drop */ if (tx_state == 0) @@ -1225,11 +291,47 @@ static void c2h_ccx_rpt(PADAPTER adapter, u8 *pdata) rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); #endif /* CONFIG_XMIT_ACK */ } +#ifdef CONFIG_FW_HANDLE_TXBCN +#define C2H_SUB_CMD_ID_FW_TBTT_RPT 0X23 +#define TBTT_RPT_GET_SN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X01, 0, 8) +#define TBTT_RPT_GET_PORT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8) + +#define TBTT_ROOT 0x00 +#define TBTT_VAP1 0x10 +#define TBTT_VAP2 0x20 +#define TBTT_VAP3 0x30 + +static void c2h_tbtt_rpt(PADAPTER adapter, u8 *pdata) +{ + u8 ap_id, c2h_sn; + + ap_id = TBTT_RPT_GET_PORT_ID(pdata); + c2h_sn = TBTT_RPT_GET_SN(pdata); +#ifdef DBG_FW_TBTT_RPT + if (ap_id == TBTT_ROOT) + RTW_INFO("== TBTT ROOT SN:%d==\n", c2h_sn); + else if (ap_id == TBTT_VAP1) + RTW_INFO("== TBTT_VAP1 SN:%d==\n", c2h_sn); + else if (ap_id == TBTT_VAP2) + RTW_INFO("== TBTT_VAP2 SN:%d==\n", c2h_sn); + else if (ap_id == TBTT_VAP3) + RTW_INFO("== TBTT_VAP3 SN:%d==\n", c2h_sn); + else + RTW_ERR("TBTT RPT INFO ERROR\n"); +#endif +} +#endif /** * pbuf = RXDESC + c2h packet * length = RXDESC_SIZE + c2h packet size * c2h format => ID(1B) | SN(1B) | Payload +* C2H - 0xFF format +* u8 CMD_ID +* u8 CMD_SEQ +* u8 SUB_CMD_ID +* u8 CMD_LEN +* u8 *pContent */ void c2h_handler_rtl8821c(PADAPTER adapter, u8 *pbuf, u16 length) { @@ -1238,29 +340,34 @@ void c2h_handler_rtl8821c(PADAPTER adapter, u8 *pbuf, u16 length) u8 *pc2h_hdr; u8 *pc2h_data; u8 c2h_sub_cmd_id = 0; + u32 desc_size = 0; #ifdef CONFIG_WOWLAN struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); +#endif /* CONFIG_WOWLAN*/ + rtw_halmac_get_rx_desc_size(adapter_to_dvobj(adapter), &desc_size); + +#ifdef CONFIG_WOWLAN if (pwrpriv->wowlan_mode == _TRUE) { RTW_INFO("%s: return because wowolan_mode==TRUE! CMDID=%d\n", - __FUNCTION__, C2H_GET_CMD_ID(pbuf + RXDESC_SIZE)); + __FUNCTION__, C2H_GET_CMD_ID(pbuf + desc_size)); return; } #endif /* CONFIG_WOWLAN*/ if (pbuf == NULL) return; - if (length < HALMAC_RX_DESC_SIZE_8821C) { + if (length < desc_size) { RTW_INFO("%s: [ERROR] c2h length(%d) is smaller than RXDESC_SIZE(%d)!!\n", - __func__, length, HALMAC_RX_DESC_SIZE_8821C); + __func__, length, desc_size); return; } - pc2h_hdr = pbuf + HALMAC_RX_DESC_SIZE_8821C; - pc2h_data = pbuf + HALMAC_RX_DESC_SIZE_8821C + 2; /* cmd ID not 0xFF original C2H have 2 bytes C2H header */ + pc2h_hdr = pbuf + desc_size; + pc2h_data = pbuf + desc_size + 2; /* cmd ID not 0xFF original C2H have 2 bytes C2H header */ c2h_id = C2H_GET_CMD_ID(pc2h_hdr); c2h_sn = C2H_GET_SEQ(pc2h_hdr); - c2h_len = length - HALMAC_RX_DESC_SIZE_8821C - 2; + c2h_len = length - desc_size - 2; if ((c2h_len < 0) || (c2h_len > C2H_DBG_CONTENT_MAX_LENGTH)) { RTW_ERR("%s: [ERROR] C2H_ID(%02x) C2H_SN(%d) warn c2h_len :%d (length:%d)\n", __func__, c2h_id, c2h_sn, c2h_len, length); @@ -1279,10 +386,14 @@ void c2h_handler_rtl8821c(PADAPTER adapter, u8 *pbuf, u16 length) /* Get C2H sub cmd ID */ c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(pc2h_hdr); if (c2h_sub_cmd_id == C2H_SUB_CMD_ID_CCX_RPT) - c2h_ccx_rpt(adapter, pbuf + HALMAC_RX_DESC_SIZE_8821C + 4); /* cmd ID 0xFF new C2H have 4 bytes C2H header */ + c2h_ccx_rpt(adapter, pbuf + desc_size); + #ifdef CONFIG_FW_HANDLE_TXBCN + else if (c2h_sub_cmd_id == C2H_SUB_CMD_ID_FW_TBTT_RPT) + c2h_tbtt_rpt(adapter, pbuf + desc_size); + #endif else /* indicate rx desc + c2h pkt to halmac */ - if (rtw_halmac_c2h_handle(adapter_to_dvobj(adapter), pbuf, length == (-1))) + if (rtw_halmac_c2h_handle(adapter_to_dvobj(adapter), pbuf, length) == -1) RTW_ERR("%s "ADPT_FMT" C2H, ID=%d, SubID=%d seq=%d len=%d ,HALMAC not to handle\n", __func__, ADPT_ARG(adapter), c2h_id, c2h_sub_cmd_id, c2h_sn, length); break; @@ -1300,6 +411,7 @@ static inline u8 is_c2h_id_handle_directly(u8 c2h_id, u8 c2h_sub_cmd_id) switch (c2h_id) { case CMD_ID_C2H_CCX_RPT: case C2H_IQK_FINISH: + case C2H_EXTEND: #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) case C2H_BCN_EARLY_RPT: @@ -1314,13 +426,6 @@ static inline u8 is_c2h_id_handle_directly(u8 c2h_id, u8 c2h_sub_cmd_id) case C2H_MCC: #endif return _TRUE; - case 0xFF: - switch (c2h_sub_cmd_id) { - case C2H_SUB_CMD_ID_CCX_RPT: - return _TRUE; - default: - return _FALSE; - } default: return _FALSE; } @@ -1335,15 +440,18 @@ void c2h_pre_handler_rtl8821c(_adapter *adapter, u8 *pbuf, s32 length) { u8 c2h_id; u8 c2h_sub_cmd_id = 0; + u32 desc_size = 0; if ((length <= 0) || (!pbuf)) return; - c2h_id = C2H_GET_CMD_ID(pbuf + HALMAC_RX_DESC_SIZE_8821C); + rtw_halmac_get_rx_desc_size(adapter_to_dvobj(adapter), &desc_size); + + c2h_id = C2H_GET_CMD_ID(pbuf + desc_size); /* Get C2H sub cmd ID */ if (c2h_id == 0xFF) - c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(pbuf + HALMAC_RX_DESC_SIZE_8821C); + c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(pbuf + desc_size); if (is_c2h_id_handle_directly(c2h_id, c2h_sub_cmd_id)) c2h_handler_rtl8821c(adapter, pbuf, length); diff --git a/hal/rtl8821c/rtl8821c_dm.c b/hal/rtl8821c/rtl8821c_dm.c index 0ec6bb3..dd67877 100644 --- a/hal/rtl8821c/rtl8821c_dm.c +++ b/hal/rtl8821c/rtl8821c_dm.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* ************************************************************ * Description: * @@ -41,9 +36,6 @@ static void dm_CheckProtection(PADAPTER adapter) { } -static void dm_CheckStatistics(PADAPTER adapter) -{ -} #ifdef CONFIG_SUPPORT_HW_WPS_PBC static void dm_CheckPbcGPIO(PADAPTER adapter) @@ -156,15 +148,10 @@ void dm_InterruptMigration(PADAPTER adapter) */ static void init_phydm_cominfo(PADAPTER adapter) { - PHAL_DATA_TYPE hal; - struct PHY_DM_STRUCT *pDM_Odm; - u32 SupportAbility = 0; + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct dm_struct *pDM_Odm = &hal->odmpriv; u8 cut_ver = ODM_CUT_A, fab_ver = ODM_TSMC; - - hal = GET_HAL_DATA(adapter); - pDM_Odm = &hal->odmpriv; - Init_ODM_ComInfo(adapter); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, hal->PackageType); @@ -205,60 +192,39 @@ static void init_phydm_cominfo(PADAPTER adapter) odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_FAB_VER, fab_ver); odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_CUT_VER, cut_ver); - SupportAbility = ODM_RF_CALIBRATION | ODM_RF_TX_PWR_TRACK; - -#ifdef CONFIG_DISABLE_ODM - SupportAbility = 0; -#endif - odm_cmn_info_update(pDM_Odm, ODM_CMNINFO_ABILITY, SupportAbility); } void rtl8821c_phy_init_dm_priv(PADAPTER adapter) { - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *podmpriv = &hal->odmpriv; + struct dm_struct *phydm = adapter_to_phydm(adapter); init_phydm_cominfo(adapter); - odm_init_all_timers(podmpriv); - - /*PHYDM API - thermal trim*/ - phydm_get_thermal_trim_offset(podmpriv); - /*PHYDM API - power trim*/ - phydm_get_power_trim_offset(podmpriv); + odm_init_all_timers(phydm); } void rtl8821c_phy_deinit_dm_priv(PADAPTER adapter) { - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *podmpriv = &hal->odmpriv; + struct dm_struct *phydm = adapter_to_phydm(adapter); - - odm_cancel_all_timers(podmpriv); + odm_cancel_all_timers(phydm); } void rtl8821c_phy_init_haldm(PADAPTER adapter) { - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &hal->odmpriv; - - hal->DM_Type = dm_type_by_driver; - odm_dm_init(pDM_Odm); + rtw_phydm_init(adapter); } void rtl8821c_phy_haldm_watchdog(PADAPTER Adapter) { BOOLEAN bFwCurrentInPSMode = _FALSE; - BOOLEAN bFwPSAwake = _TRUE; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); - + u8 bFwPSAwake = _TRUE; if (!rtw_is_hw_init_completed(Adapter)) goto skip_dm; #ifdef CONFIG_LPS bFwCurrentInPSMode = adapter_to_pwrctl(Adapter)->bFwCurrentInPSMode; - rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake)); + rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, &bFwPSAwake); #endif #ifdef CONFIG_P2P_PS @@ -270,8 +236,6 @@ void rtl8821c_phy_haldm_watchdog(PADAPTER Adapter) if ((rtw_is_hw_init_completed(Adapter)) && ((!bFwCurrentInPSMode) && bFwPSAwake)) { - /* Calculate Tx/Rx statistics. */ - dm_CheckStatistics(Adapter); /* Dynamically switch RTS/CTS protection.*/ /*dm_CheckProtection(Adapter);*/ @@ -280,44 +244,17 @@ void rtl8821c_phy_haldm_watchdog(PADAPTER Adapter) #ifdef CONFIG_DISABLE_ODM goto skip_dm; #endif + rtw_phydm_watchdog(Adapter); - if (rtw_is_hw_init_completed(Adapter)) { - u8 bLinked = _FALSE; - u8 bsta_state = _FALSE; - u8 bBtDisabled = _TRUE; +skip_dm: -#ifdef CONFIG_LPS_PG - u8 is_in_lpspg = _FALSE; - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 + if (check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) && + check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) + rtw_hal_beamforming_config_csirate(Adapter); #endif - if (rtw_mi_check_status(Adapter, MI_STA_LINKED) || rtw_mi_check_status(Adapter, MI_AP_ASSOC)) { - bLinked = _TRUE; - if (rtw_mi_check_status(Adapter, MI_STA_LINKED)) - bsta_state = _TRUE; - } - - odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked); - odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state); - -#ifdef CONFIG_BT_COEXIST - bBtDisabled = rtw_btcoex_IsBtDisabled(Adapter); - odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, ((bBtDisabled == _TRUE) ? _FALSE : _TRUE)); -#else - odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, _FALSE); -#endif /* CONFIG_BT_COEXIST*/ - - -#ifdef CONFIG_LPS_PG - if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2)) - is_in_lpspg = _TRUE; - odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LPSPG, is_in_lpspg); #endif - odm_dm_watchdog(&pHalData->odmpriv); - - } - -skip_dm: - #ifdef CONFIG_SUPPORT_HW_WPS_PBC /* Check GPIO to determine current Pbc status.*/ dm_CheckPbcGPIO(Adapter); @@ -325,92 +262,3 @@ void rtl8821c_phy_haldm_watchdog(PADAPTER Adapter) return; } -void rtl8821c_phy_haldm_in_lps(PADAPTER adapter) -{ -#if 0 /* phydm not ready */ - u32 PWDB_rssi = 0; - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &hal->odmpriv; - struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &pDM_Odm->dm_dig_table; - struct sta_priv *pstapriv = &adapter->stapriv; - struct sta_info *psta = NULL; - - - RTW_INFO("%s: rssi_min=%d\n", __FUNCTION__, pDM_Odm->rssi_min); - - /* update IGI */ - odm_write_dig(pDM_Odm, pDM_Odm->rssi_min); - - /* set rssi to fw */ - psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); - if (psta && (psta->rssi_stat.undecorated_smoothed_pwdb > 0)) { - PWDB_rssi = (psta->mac_id | (psta->rssi_stat.undecorated_smoothed_pwdb << 16)); - rtl8821c_set_FwRssiSetting_cmd(adapter, (u8 *)&PWDB_rssi); - } -#endif -} - -void rtl8821c_phy_haldm_watchdog_in_lps(PADAPTER adapter) -{ -#if 0 /* phydm not ready */ - u8 bLinked = _FALSE; - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct mlme_priv *pmlmepriv = &adapter->mlmepriv; - struct PHY_DM_STRUCT *pDM_Odm = &hal->odmpriv; - struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &pDM_Odm->dm_dig_table; - struct sta_priv *pstapriv = &adapter->stapriv; - struct sta_info *psta = NULL; -#ifdef CONFIG_CONCURRENT_MODE - PADAPTER pbuddy_adapter = adapter->pbuddy_adapter; -#endif /* CONFIG_CONCURRENT_MODE */ - - - if (!rtw_is_hw_init_completed(adapter)) - goto skip_lps_dm; - - if (rtw_linked_check(adapter)) - bLinked = _TRUE; - -#ifdef CONFIG_CONCURRENT_MODE - if (pbuddy_adapter && rtw_linked_check(pbuddy_adapter)) - bLinked = _TRUE; -#endif /* CONFIG_CONCURRENT_MODE */ - - odm_cmn_info_update(&hal->odmpriv, ODM_CMNINFO_LINK, bLinked); - - if (bLinked == _FALSE) - goto skip_lps_dm; - - if (!(pDM_Odm->support_ability & ODM_BB_RSSI_MONITOR)) - goto skip_lps_dm; - - /* Do DIG by RSSI In LPS-32K */ - - /* 1. Find MIN-RSSI */ - psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); - if (psta == NULL) - goto skip_lps_dm; - - hal->entry_min_undecorated_smoothed_pwdb = psta->rssi_stat.undecorated_smoothed_pwdb; - - RTW_INFO("cur_ig_value=%d, entry_min_undecorated_smoothed_pwdb=%d\n", - pDM_DigTable->cur_ig_value, hal->entry_min_undecorated_smoothed_pwdb); - - if (hal->entry_min_undecorated_smoothed_pwdb <= 0) - goto skip_lps_dm; - - hal->min_undecorated_pwdb_for_dm = hal->entry_min_undecorated_smoothed_pwdb; - - pDM_Odm->rssi_min = hal->min_undecorated_pwdb_for_dm; - -#ifdef CONFIG_LPS - if ((pDM_DigTable->cur_ig_value > pDM_Odm->rssi_min + 5) - || (pDM_DigTable->cur_ig_value < pDM_Odm->rssi_min - 5)) - rtw_dm_in_lps_wk_cmd(adapter); -#endif - -skip_lps_dm: -#endif - return; -} diff --git a/hal/rtl8821c/rtl8821c_halinit.c b/hal/rtl8821c/rtl8821c_halinit.c index 3e9174f..c15aef1 100644 --- a/hal/rtl8821c/rtl8821c_halinit.c +++ b/hal/rtl8821c/rtl8821c_halinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8821C_HALINIT_C_ #include /* PADAPTER, basic_types.h and etc. */ @@ -37,6 +32,8 @@ void init_hal_spec_rtl8821c(PADAPTER adapter) hal_spec->rfpath_num_2g = 2; hal_spec->rfpath_num_5g = 1; + hal_spec->txgi_max = 63; + hal_spec->txgi_pdbm = 2; hal_spec->max_tx_cnt = 1; hal_spec->tx_nss_num = 1; hal_spec->rx_nss_num = 1; @@ -47,16 +44,21 @@ void init_hal_spec_rtl8821c(PADAPTER adapter) hal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC; hal_spec->wl_func = 0 -#ifdef CONFIG_P2P | WL_FUNC_P2P -#ifdef CONFIG_WFD | WL_FUNC_MIRACAST -#endif /* CONFIG_WFD */ -#endif /* CONFIG_P2P */ -#ifdef CONFIG_TDLS | WL_FUNC_TDLS -#endif /* CONFIG_TDLS */ ; + + hal_spec->rx_tsf_filter = 1; + + hal_spec->pg_txpwr_saddr = 0x10; + hal_spec->pg_txgi_diff_factor = 1; + + rtw_macid_ctl_init_sleep_reg(adapter_to_macidctl(adapter) + , REG_MACID_SLEEP_8821C + , REG_MACID_SLEEP1_8821C + , REG_MACID_SLEEP2_8821C + , REG_MACID_SLEEP3_8821C); } u32 rtl8821c_power_on(PADAPTER adapter) @@ -124,7 +126,7 @@ void rtl8821c_power_off(PADAPTER adapter) bMacPwrCtrlOn = _FALSE; rtw_hal_set_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); - adapter->bFWReady = _FALSE; + GET_HAL_DATA(adapter)->bFWReady = _FALSE; out: return; @@ -137,7 +139,7 @@ u8 rtl8821c_hal_init_main(PADAPTER adapter) int err; s32 ret; - adapter->bFWReady = _FALSE; + hal->bFWReady = _FALSE; hal->fw_ractrl = _FALSE; #ifdef CONFIG_NO_FW @@ -151,7 +153,7 @@ u8 rtl8821c_hal_init_main(PADAPTER adapter) #endif if (!err) { - adapter->bFWReady = _TRUE; + hal->bFWReady = _TRUE; hal->fw_ractrl = _TRUE; } RTW_INFO("FW Version:%d SubVersion:%d\n", hal->firmware_version, hal->firmware_sub_version); @@ -198,7 +200,7 @@ void rtl8821c_hal_init_misc(PADAPTER adapter) { PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); u8 drv_info_sz = 0; - + u32 rcr_bits; /* * Sync driver status and hardware setting */ @@ -209,28 +211,30 @@ void rtl8821c_hal_init_misc(PADAPTER adapter) /* enable to rx ps-poll ,disable Control frame filter*/ rtw_write16(adapter, REG_RXFLTMAP1_8821C, 0x0400); /* Accept all data frames */ - rtw_write16(adapter, REG_RXFLTMAP_8821C, 0xFFFF); + rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0xFFFF); /* Accept all management frames */ rtw_write16(adapter, REG_RXFLTMAP0_8821C, 0xFFFF); /*RCR setting - Sync driver status with hardware setting */ - rtl8821c_rcr_get(adapter, NULL); + rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_bits); - rtl8821c_rcr_clear(adapter, BIT_AICV_8821C | BIT_ACRC32_8821C | BIT_APP_FCS_8821C | BIT_APWRMGT_8821C); + rcr_bits &= ~(BIT_AICV_8821C | BIT_ACRC32_8821C | BIT_APP_FCS_8821C | BIT_APWRMGT_8821C); - rtw_halmac_get_drv_info_sz(adapter_to_dvobj(adapter), &drv_info_sz); + rtw_halmac_get_rx_drv_info_sz(adapter_to_dvobj(adapter), &drv_info_sz); if (drv_info_sz) - rtl8821c_rcr_add(adapter, BIT_APP_PHYSTS_8821C); + rcr_bits |= BIT_APP_PHYSTS_8821C; #ifdef CONFIG_RX_PACKET_APPEND_FCS - rtl8821c_rcr_add(adapter, BIT_APP_FCS_8821C); + rcr_bits |= BIT_APP_FCS_8821C; #endif #ifdef CONFIG_RX_PACKET_APPEND_ICV_ERROR - rtl8821c_rcr_add(adapter, BIT_AICV_8821C); + rcr_bits |= BIT_AICV_8821C; #endif + rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_bits); + #ifdef CONFIG_XMIT_ACK rtl8821c_set_mgnt_xmit_ack(adapter); #endif /*CONFIG_XMIT_ACK*/ @@ -248,22 +252,9 @@ void rtl8821c_hal_init_misc(PADAPTER adapter) /*for 1212 module - 5G RX issue*/ if (hal_data->rfe_type == 2) rtw_write8(adapter, REG_PAD_CTRL1 + 3, 0x36); - -#ifdef CONFIG_CHECK_AC_LIFETIME - /* Enable lifetime check for the four ACs */ - rtw_write8(adapter, REG_LIFETIME_EN_8821C, rtw_read8(adapter, REG_LIFETIME_EN_8821C) | 0x0f); -#endif /* CONFIG_CHECK_AC_LIFETIME */ - -#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI) -#ifdef CONFIG_TX_MCAST2UNI - rtw_write16(adapter, REG_PKT_LIFE_TIME_8821C, 0x0400); /* unit: 256us. 256ms */ - rtw_write16(adapter, REG_PKT_LIFE_TIME_8821C+2, 0x0400); /* unit: 256us. 256ms */ -#else /* CONFIG_TX_MCAST2UNI */ - rtw_write16(adapter, REG_PKT_LIFE_TIME_8821C, 0x3000); /* unit: 256us. 3s */ - rtw_write16(adapter, REG_PKT_LIFE_TIME_8821C+2, 0x3000); /* unit: 256us. 3s */ -#endif /* CONFIG_TX_MCAST2UNI */ -#endif /* CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI */ - +#ifdef CONFIG_AMPDU_PRETX_CD + rtl8821c_pretx_cd_config(adapter); +#endif } u32 rtl8821c_hal_init(PADAPTER adapter) @@ -278,16 +269,25 @@ u32 rtl8821c_hal_init(PADAPTER adapter) rtl8821c_hal_init_misc(adapter); rtl8821c_phy_init_haldm(adapter); +#ifdef CONFIG_BEAMFORMING + rtl8821c_phy_bf_init(adapter); +#endif + +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT + /*HW / FW init*/ + rtw_hal_set_default_port_id_cmd(adapter, 0); +#endif #ifdef CONFIG_BT_COEXIST /* Init BT hw config. */ - if (_TRUE == hal->EEPROMBluetoothCoexist) + if (_TRUE == hal->EEPROMBluetoothCoexist) { rtw_btcoex_HAL_Initialize(adapter, _FALSE); - else - rtw_btcoex_wifionly_hw_config(adapter); -#else /* CONFIG_BT_COEXIST */ - rtw_btcoex_wifionly_hw_config(adapter); + #ifdef CONFIG_FW_MULTI_PORT_SUPPORT + rtw_hal_set_wifi_btc_port_id_cmd(adapter); + #endif + } else #endif /* CONFIG_BT_COEXIST */ + rtw_btcoex_wifionly_hw_config(adapter); rtl8821c_hal_init_channel_setting(adapter); @@ -304,7 +304,7 @@ u32 rtl8821c_hal_deinit(PADAPTER adapter) d = adapter_to_dvobj(adapter); hal = GET_HAL_DATA(adapter); - adapter->bFWReady = _FALSE; + hal->bFWReady = _FALSE; hal->fw_ractrl = _FALSE; err = rtw_halmac_deinit_hal(d); @@ -322,7 +322,6 @@ void rtl8821c_init_default_value(PADAPTER adapter) hal = GET_HAL_DATA(adapter); - adapter->registrypriv.wireless_mode = WIRELESS_MODE_24G | WIRELESS_MODE_5G; /* init default value */ hal->fw_ractrl = _FALSE; @@ -332,10 +331,6 @@ void rtl8821c_init_default_value(PADAPTER adapter) /* init phydm default value */ hal->bIQKInitialized = _FALSE; - hal->odmpriv.rf_calibrate_info.tm_trigger = 0; /* for IQK */ - hal->odmpriv.rf_calibrate_info.thermal_value_hp_index = 0; - for (i = 0; i < HP_THERMAL_NUM; i++) - hal->odmpriv.rf_calibrate_info.thermal_value_hp[i] = 0; /* init Efuse variables */ hal->EfuseUsedBytes = 0; diff --git a/hal/rtl8821c/rtl8821c_mac.c b/hal/rtl8821c/rtl8821c_mac.c index f1a1954..f21fe10 100644 --- a/hal/rtl8821c/rtl8821c_mac.c +++ b/hal/rtl8821c/rtl8821c_mac.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,86 +11,13 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8821C_MAC_C_ #include /* PADAPTER, basic_types.h and etc. */ #include /* HAL_DATA_TYPE */ #include "../hal_halmac.h" /* Register Definition and etc. */ -inline u8 rtl8821c_rcr_config(PADAPTER p, u32 rcr) -{ - int err; - - err = rtw_write32(p, REG_RCR_8821C, rcr); - if (_FAIL == err) - return _FALSE; - - GET_HAL_DATA(p)->ReceiveConfig = rcr; - return _TRUE; -} - -inline u8 rtl8821c_rcr_get(PADAPTER p, u32 *rcr) -{ - u32 v32; - - v32 = rtw_read32(p, REG_RCR_8821C); - if (rcr) - *rcr = v32; - GET_HAL_DATA(p)->ReceiveConfig = v32; - return _TRUE; -} - -inline u8 rtl8821c_rcr_check(PADAPTER p, u32 check_bit) -{ - PHAL_DATA_TYPE hal; - u32 rcr; - - hal = GET_HAL_DATA(p); - rcr = hal->ReceiveConfig; - if ((rcr & check_bit) == check_bit) - return _TRUE; - - return _FALSE; -} - -inline u8 rtl8821c_rcr_add(PADAPTER p, u32 add) -{ - PHAL_DATA_TYPE hal; - u32 rcr; - u8 ret = _TRUE; - - hal = GET_HAL_DATA(p); - - rcr = hal->ReceiveConfig; - rcr |= add; - if (rcr != hal->ReceiveConfig) - ret = rtl8821c_rcr_config(p, rcr); - - return ret; -} - -inline u8 rtl8821c_rcr_clear(PADAPTER p, u32 clear) -{ - PHAL_DATA_TYPE hal; - u32 rcr; - u8 ret = _TRUE; - - hal = GET_HAL_DATA(p); - - rcr = hal->ReceiveConfig; - rcr &= ~clear; - if (rcr != hal->ReceiveConfig) - ret = rtl8821c_rcr_config(p, rcr); - - return ret; -} - #ifdef CONFIG_XMIT_ACK inline u8 rtl8821c_set_mgnt_xmit_ack(_adapter *adapter) { @@ -107,7 +34,7 @@ inline u8 rtl8821c_set_mgnt_xmit_ack(_adapter *adapter) inline u8 rtl8821c_rx_ba_ssn_appended(PADAPTER p) { - return rtl8821c_rcr_check(p, BIT_APP_BASSN_8821C); + return rtw_hal_rcr_check(p, BIT_APP_BASSN_8821C); } inline u8 rtl8821c_rx_fcs_append_switch(PADAPTER p, u8 enable) @@ -117,16 +44,16 @@ inline u8 rtl8821c_rx_fcs_append_switch(PADAPTER p, u8 enable) rcr_bit = BIT_APP_FCS_8821C; if (_TRUE == enable) - ret = rtl8821c_rcr_add(p, rcr_bit); + ret = rtw_hal_rcr_add(p, rcr_bit); else - ret = rtl8821c_rcr_clear(p, rcr_bit); + ret = rtw_hal_rcr_clear(p, rcr_bit); return ret; } inline u8 rtl8821c_rx_fcs_appended(PADAPTER p) { - return rtl8821c_rcr_check(p, BIT_APP_FCS_8821C); + return rtw_hal_rcr_check(p, BIT_APP_FCS_8821C); } u8 rtl8821c_rx_tsf_addr_filter_config(_adapter *adapter, u8 config) @@ -170,14 +97,16 @@ s32 rtl8821c_fw_dl(PADAPTER adapter, u8 wowlan) } #else fw_bin = _FALSE; + #ifdef CONFIG_WOWLAN if (_TRUE == wowlan) err = rtw_halmac_dlfw(d, array_mp_8821c_fw_wowlan, array_length_mp_8821c_fw_wowlan); else + #endif err = rtw_halmac_dlfw(d, array_mp_8821c_fw_nic, array_length_mp_8821c_fw_nic); #endif if (!err) { - adapter->bFWReady = _TRUE; + hal_data->bFWReady = _TRUE; hal_data->fw_ractrl = _TRUE; RTW_INFO("%s Download Firmware from %s success\n", __func__, (fw_bin) ? "file" : "array"); RTW_INFO("%s FW Version:%d SubVersion:%d\n", (wowlan) ? "WOW" : "NIC", hal_data->firmware_version, hal_data->firmware_sub_version); @@ -218,4 +147,36 @@ s32 rtl8821c_fw_mem_dl(PADAPTER adapter, enum fw_mem mem) return _SUCCESS; } +#ifdef CONFIG_AMPDU_PRETX_CD +#include "rtl8821c.h" +#define AMPDU_NUMBER 0x3F3F /*MAX AMPDU Number = 63*/ +#define REG_PRECNT_CTRL_8821C 0x04E5 +#define BIT_EN_PRECNT_8821C BIT(11) +#define PRECNT_TH 0x1E4 /*6.05us*/ + +/* pre-tx count-down mechanism */ +void rtl8821c_pretx_cd_config(_adapter *adapter) +{ + u8 burst_mode; + u16 pre_cnt = PRECNT_TH | BIT_EN_PRECNT_8821C; + + /*Enable AMPDU PRE-TX, Reg0x4BC[6] = 1*/ + burst_mode = rtw_read8(adapter, REG_SW_AMPDU_BURST_MODE_CTRL_8821C); + if (!(burst_mode & BIT_PRE_TX_CMD_8821C)) { + burst_mode |= BIT_PRE_TX_CMD_8821C; + rtw_write8(adapter, REG_SW_AMPDU_BURST_MODE_CTRL_8821C, burst_mode); + } + + /*MAX AMPDU Number = 63, Reg0x4C8[21:16] = 0x3F*/ + rtw_write16(adapter, REG_PROT_MODE_CTRL_8821C + 2, AMPDU_NUMBER); + /*Reg0x4E5[11] = 1, Reg0x4E5[10:0] = 0x1E4 */ + rtw_write8(adapter, REG_PRECNT_CTRL_8821C, (u8)(pre_cnt & 0xFF)); + rtw_write8(adapter, (REG_PRECNT_CTRL_8821C + 1), (u8)(pre_cnt >> 8)); + + #if (defined(DBG_PRE_TX_HANG) && (defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI))) + rtw_write32(adapter, REG_HIMR1_8821C , + (rtw_read32(adapter, REG_HIMR1_8821C) | BIT_PRETXERR_HANDLE_IMR)); + #endif +} +#endif /*CONFIG_AMPDU_PRETX_CD*/ diff --git a/hal/rtl8821c/rtl8821c_ops.c b/hal/rtl8821c/rtl8821c_ops.c index 1b4865f..666c3f9 100644 --- a/hal/rtl8821c/rtl8821c_ops.c +++ b/hal/rtl8821c/rtl8821c_ops.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8821C_OPS_C_ #include /* basic_types.h, rtw_io.h and etc. */ @@ -32,7 +27,9 @@ #include "rtl8821ce_hal.h" #endif #include "rtl8821c_dm.h" - +#ifdef CONFIG_SDIO_HCI +#include "sdio/rtl8821cs.h" +#endif static void read_chip_version(PADAPTER adapter) { @@ -141,20 +138,15 @@ static void Hal_EfuseParseBoardType(PADAPTER adapter, u8 *map, u8 mapvalid) static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); u8 setting; u32 tmpu4; + u32 tmp_u32; -#ifdef CONFIG_RTW_MAC_HIDDEN_RPT - if (hal_spec->hci_type <= 3 && hal_spec->hci_type >= 1) { - hal->EEPROMBluetoothCoexist = _FALSE; - goto exit; - } -#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */ + if ((mapvalid == _TRUE) && (map[EEPROM_RF_BOARD_OPTION_8821C] != 0xFF)) { - if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8821C] != 0xFF)) { + tmp_u32 = rtw_read32(adapter, REG_WL_BT_PWR_CTRL_8821C); /* 0xc1[7:5] = 0x01 */ - if (((map[EEPROM_RF_BOARD_OPTION_8821C] & 0xe0) >> 5) == 0x01) + if ((((map[EEPROM_RF_BOARD_OPTION_8821C] & 0xe0) >> 5) == 0x01) && (tmp_u32 & BIT_BT_FUNC_EN_8821C)) hal->EEPROMBluetoothCoexist = _TRUE; else hal->EEPROMBluetoothCoexist = _FALSE; @@ -173,10 +165,10 @@ static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid) * 0: Ant2(aux.) * 1: Ant1(main), default */ - hal->ant_path = (setting & BIT(6)) ? ODM_RF_PATH_B : ODM_RF_PATH_A; + hal->ant_path = (setting & BIT(6)) ? RF_PATH_B : RF_PATH_A; } else { hal->EEPROMBluetoothAntNum = Ant_x1; - hal->ant_path = ODM_RF_PATH_A; + hal->ant_path = RF_PATH_A; } exit: @@ -187,17 +179,15 @@ static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid) static void Hal_EfuseParseChnlPlan(PADAPTER adapter, u8 *map, u8 autoloadfail) { - adapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan( - adapter, - map ? &map[EEPROM_COUNTRY_CODE_8821C] : NULL, - map ? map[EEPROM_CHANNEL_PLAN_8821C] : 0xFF, - adapter->registrypriv.alpha2, - adapter->registrypriv.channel_plan, - RTW_CHPLAN_REALTEK_DEFINE, - autoloadfail - ); - - RTW_INFO("EEPROM ChannelPlan=0x%02x\n", adapter->mlmepriv.ChannelPlan); + hal_com_config_channel_plan( + adapter, + map ? &map[EEPROM_COUNTRY_CODE_8821C] : NULL, + map ? map[EEPROM_CHANNEL_PLAN_8821C] : 0xFF, + adapter->registrypriv.alpha2, + adapter->registrypriv.channel_plan, + RTW_CHPLAN_REALTEK_DEFINE, + autoloadfail + ); } static void Hal_EfuseParseXtal(PADAPTER adapter, u8 *map, u8 mapvalid) @@ -247,7 +237,7 @@ static void Hal_EfuseParseAntennaDiversity(PADAPTER adapter, u8 *map, u8 mapvali /*hal->TRxAntDivType = S0S1_TRX_HW_ANTDIV;*/ hal->with_extenal_ant_switch = ((map[EEPROM_RF_BT_SETTING_8821C] & BIT7) >> 7); - RTW_INFO("EEPROM AntDivCfg=%d, AntDivType=%d, extenal_ant_switch:%d\n", + RTW_INFO("%s:EEPROM AntDivCfg=%d, AntDivType=%d, extenal_ant_switch:%d\n", __func__, hal->AntDivCfg, hal->TRxAntDivType, hal->with_extenal_ant_switch); #endif /* CONFIG_ANTENNA_DIVERSITY */ } @@ -387,7 +377,7 @@ static void Hal_ReadAmplifierType(PADAPTER adapter, u8 *map, u8 mapvalid) RTW_INFO("EEPROM TypeALNA = 0x%X\n", hal_data->TypeALNA); } -static void Hal_ReadRFEType(PADAPTER adapter, u8 *map, u8 mapvalid) +static u8 Hal_ReadRFEType(PADAPTER adapter, u8 *map, u8 mapvalid) { /* [20160-06-22 -R15] Type 0 - (2-Ant, DPDT), (2G_WLG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW) @@ -417,10 +407,14 @@ static void Hal_ReadRFEType(PADAPTER adapter, u8 *map, u8 mapvalid) /* error handle */ hal->rfe_type = 0; - RTW_ERR("please pg efuse or change RFE_Type of registrypriv!!\n"); + RTW_ERR("\n\nEmpty EFUSE with unknown REF type!!\n\n"); + RTW_ERR("please program efuse or specify correct RFE type.\n"); + RTW_ERR("cmd: insmod rtl8821cx.ko rtw_RFE_type=\n\n"); + return _FAIL; exit: RTW_INFO("EEPROM rfe_type=0x%x\n", hal->rfe_type); + return _SUCCESS; } @@ -441,6 +435,23 @@ static void Hal_ReadUsbModeSwitch(PADAPTER adapter, u8 *map, u8 mapvalid) RTW_INFO("EEPROM USB Switch=%d\n", hal->EEPROMUsbSwitch); } + +static void hal_read_usb_pid_vid(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + if (mapvalid == _TRUE) { + /* VID, PID */ + hal->EEPROMVID = ReadLE2Byte(&map[EEPROM_VID_8821CU]); + hal->EEPROMPID = ReadLE2Byte(&map[EEPROM_PID_8821CU]); + } else { + hal->EEPROMVID = EEPROM_Default_VID; + hal->EEPROMPID = EEPROM_Default_PID; + } + + RTW_INFO("EEPROM VID = 0x%04X, PID = 0x%04X\n", hal->EEPROMVID, hal->EEPROMPID); +} + #endif /* CONFIG_USB_HCI */ /* @@ -458,14 +469,11 @@ u8 rtl8821c_read_efuse(PADAPTER adapter) u8 val8; u8 *efuse_map = NULL; u8 valid; + u8 ret = _FAIL; hal = GET_HAL_DATA(adapter); efuse_map = hal->efuse_eeprom_data; -#ifdef CONFIG_RTW_MAC_HIDDEN_RPT - hal_read_mac_hidden_rpt(adapter); -#endif - /* 1. Read registers to check hardware eFuse available or not */ val8 = rtw_read8(adapter, REG_SYS_EEPROM_CTRL_8821C); hal->bautoload_fail_flag = (val8 & BIT_AUTOLOAD_SUS_8821C) ? _FALSE : _TRUE; @@ -502,7 +510,8 @@ u8 rtl8821c_read_efuse(PADAPTER adapter) Hal_EfuseParseAntennaDiversity(adapter, efuse_map, valid); Hal_EfuseParseCustomerID(adapter, efuse_map, valid); Hal_DetectWoWMode(adapter); - Hal_ReadRFEType(adapter, efuse_map, valid); + if (Hal_ReadRFEType(adapter, efuse_map, valid) != _SUCCESS) + goto exit; Hal_ReadAmplifierType(adapter, efuse_map, valid); Hal_EfuseTxBBSwing(adapter, efuse_map, valid); @@ -511,9 +520,31 @@ u8 rtl8821c_read_efuse(PADAPTER adapter) #ifdef CONFIG_USB_HCI Hal_ReadUsbModeSwitch(adapter, efuse_map, valid); + hal_read_usb_pid_vid(adapter, efuse_map, valid); #endif /* CONFIG_USB_HCI */ - return _SUCCESS; + /* set coex. ant info once efuse parsing is done */ + rtw_btcoex_set_ant_info(adapter); + +#ifdef CONFIG_RTW_MAC_HIDDEN_RPT + if (hal_read_mac_hidden_rpt(adapter) != _SUCCESS) + goto exit; + { + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + + if (hal_spec->hci_type <= 3 && hal_spec->hci_type >= 1) { + hal->EEPROMBluetoothCoexist = _FALSE; + RTW_INFO("EEPROM Disable BT-coex by hal_spec\n"); + rtw_btcoex_wifionly_AntInfoSetting(adapter); + } + } +#endif + rtw_phydm_read_efuse(adapter); + + ret = _SUCCESS; + +exit: + return ret; } void rtl8821c_run_thread(PADAPTER adapter) @@ -544,25 +575,141 @@ static u8 check_ips_status(PADAPTER adapter) return _FALSE; } -static void update_ra_mask_8821c(_adapter *adapter, struct sta_info *psta, struct macid_cfg *h2c_macid_cfg) +#ifdef DBG_CONFIG_ERROR_DETECT +static void xmit_status_check(PADAPTER p) { - u8 arg[4] = {0}; + PHAL_DATA_TYPE hal = GET_HAL_DATA(p); + struct sreset_priv *psrtpriv = &hal->srestpriv; + struct xmit_priv *pxmitpriv = &p->xmitpriv; + systime current_time = 0; + unsigned int diff_time = 0; + u32 txdma_status = 0; + + txdma_status = rtw_read32(p, REG_TXDMA_STATUS_8821C); + if (txdma_status != 0x00) { + RTW_INFO("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status); + psrtpriv->tx_dma_status_cnt++; + psrtpriv->self_dect_case = 4; + rtw_hal_sreset_reset(p); + } + #ifdef DBG_PRE_TX_HANG + #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) + { + u8 hisr = rtw_read8(p, REG_HISR1_8821C + 3); + if (hisr & BIT_PRETXERR) { + RTW_ERR("PRE_TX_HANG\n"); + rtw_write8(p, REG_HISR1_8821C + 3, BIT_PRETXERR); + } + } + #endif + #endif/*DBG_PRE_TX_HANG*/ + +#ifdef CONFIG_USB_HCI + current_time = rtw_get_current_time(); + + if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) { + diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time); + + if (diff_time > 2000) { + if (psrtpriv->last_tx_complete_time == 0) + psrtpriv->last_tx_complete_time = current_time; + else { + diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time); + if (diff_time > 4000) { + u32 ability = 0; + + ability = rtw_phydm_ability_get(p); + + RTW_INFO("%s tx hang %s\n", __FUNCTION__, + (ability & ODM_BB_ADAPTIVITY) ? "ODM_BB_ADAPTIVITY" : ""); + + if (!(ability & ODM_BB_ADAPTIVITY)) { + psrtpriv->self_dect_tx_cnt++; + psrtpriv->self_dect_case = 1; + rtw_hal_sreset_reset(p); + } + } + } + } + } - arg[0] = h2c_macid_cfg->mac_id; - arg[1] = h2c_macid_cfg->rate_id; - arg[2] = (h2c_macid_cfg->ignore_bw << 4) | h2c_macid_cfg->short_gi; - arg[3] = psta->init_rate; +#endif /* CONFIG_USB_HCI */ - rtl8821c_set_FwMacIdConfig_cmd(adapter, h2c_macid_cfg->ra_mask, arg, h2c_macid_cfg->bandwidth); + if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) { + psrtpriv->dbg_trigger_point = SRESET_TGP_NULL; + rtw_hal_sreset_reset(p); + return; + } } -static void xmit_status_check(PADAPTER p) +static void check_rx_count(PADAPTER p) { + PHAL_DATA_TYPE hal = GET_HAL_DATA(p); + struct sreset_priv *psrtpriv = &hal->srestpriv; + u16 cur_mac_rxff_ptr; + + cur_mac_rxff_ptr = rtw_read16(p, REG_RXFF_PTR_V1_8821C); + +#if 0 + RTW_INFO("%s,psrtpriv->last_mac_rxff_ptr = %d , cur_mac_rxff_ptr = %d\n", __func__, psrtpriv->last_mac_rxff_ptr, cur_mac_rxff_ptr); +#endif + + if (psrtpriv->last_mac_rxff_ptr == cur_mac_rxff_ptr) { + psrtpriv->rx_cnt++; +#if 0 + RTW_INFO("%s,MAC case rx_cnt=%d\n", __func__, psrtpriv->rx_cnt); +#endif + goto exit; + } + + psrtpriv->rx_cnt = 0; + +exit: + + psrtpriv->last_mac_rxff_ptr = cur_mac_rxff_ptr; + + if (psrtpriv->rx_cnt > 3) { + psrtpriv->self_dect_case = 2; + psrtpriv->self_dect_rx_cnt++; + rtw_hal_sreset_reset(p); + } } static void linked_status_check(PADAPTER p) { + PHAL_DATA_TYPE hal = GET_HAL_DATA(p); + struct sreset_priv *psrtpriv = &hal->srestpriv; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(p); + u32 rx_dma_status = 0; + + rx_dma_status = rtw_read32(p, REG_RXDMA_STATUS_8821C); + if (rx_dma_status != 0x00) { + RTW_INFO("%s REG_RXDMA_STATUS:0x%08x\n", __FUNCTION__, rx_dma_status); + psrtpriv->rx_dma_status_cnt++; + psrtpriv->self_dect_case = 5; +#ifdef CONFIG_USB_HCI + rtw_hal_sreset_reset(p); +#endif /* CONFIG_USB_HCI */ + } + + if (psrtpriv->self_dect_fw) { + psrtpriv->self_dect_case = 3; +#ifdef CONFIG_USB_HCI + rtw_hal_sreset_reset(p); +#endif /* CONFIG_USB_HCI */ + } + +#ifdef CONFIG_USB_HCI + check_rx_count(p); +#endif /* CONFIG_USB_HCI */ + + if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) { + psrtpriv->dbg_trigger_point = SRESET_TGP_NULL; + rtw_hal_sreset_reset(p); + return; + } } +#endif /* DBG_CONFIG_ERROR_DETECT */ static const struct hw_port_reg port_cfg[] = { /*port 0*/ @@ -578,6 +725,7 @@ static const struct hw_port_reg port_cfg[] = { .bcn_space_shift = 0, .bcn_space_mask = 0xffff, .ps_aid = REG_BCN_PSR_RPT_8821C, + .ta = REG_TRANSMIT_ADDRSS_0_8821C, }, /*port 1*/ { @@ -592,6 +740,7 @@ static const struct hw_port_reg port_cfg[] = { .bcn_space_shift = 16, .bcn_space_mask = 0xfff, .ps_aid = REG_BCN_PSR_RPT1_8821C, + .ta = REG_TRANSMIT_ADDRSS_1_8821C, }, /*port 2*/ { @@ -606,6 +755,7 @@ static const struct hw_port_reg port_cfg[] = { .bcn_space_shift = 0, .bcn_space_mask = 0xfff, .ps_aid = REG_BCN_PSR_RPT2_8821C, + .ta = REG_TRANSMIT_ADDRSS_2_8821C, }, /*port 3*/ { @@ -620,6 +770,7 @@ static const struct hw_port_reg port_cfg[] = { .bcn_space_shift = 16, .bcn_space_mask = 0xfff, .ps_aid = REG_BCN_PSR_RPT3_8821C, + .ta = REG_TRANSMIT_ADDRSS_3_8821C, }, /*port 4*/ { @@ -634,13 +785,29 @@ static const struct hw_port_reg port_cfg[] = { .bcn_space_shift = 0, .bcn_space_mask = 0xfff, .ps_aid = REG_BCN_PSR_RPT4_8821C, + .ta = REG_TRANSMIT_ADDRSS_4_8821C, }, }; +static u32 hw_bcn_ctrl_addr(_adapter *adapter, u8 hw_port) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u32 addr = 0; + + if (hw_port >= hal_spec->port_num) { + RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port); + rtw_warn_on(1); + goto exit; + } + + addr = port_cfg[hw_port].bcn_ctl; + +exit: + return addr; +} -static void hw_bcn_ctrl_set(_adapter *adapter, u8 bcn_ctl_val) +static void hw_bcn_ctrl_set(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val) { - u8 hw_port = get_hw_port(adapter); u32 bcn_ctl_addr = 0; if (hw_port >= MAX_HW_PORT) { @@ -653,9 +820,8 @@ static void hw_bcn_ctrl_set(_adapter *adapter, u8 bcn_ctl_val) rtw_write8(adapter, bcn_ctl_addr, bcn_ctl_val); } -static void hw_bcn_ctrl_add(_adapter *adapter, u8 bcn_ctl_val) +static void hw_bcn_ctrl_add(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val) { - u8 hw_port = get_hw_port(adapter); u32 bcn_ctl_addr = 0; u8 val8 = 0; @@ -670,9 +836,8 @@ static void hw_bcn_ctrl_add(_adapter *adapter, u8 bcn_ctl_val) rtw_write8(adapter, bcn_ctl_addr, val8); } -static void hw_bcn_ctrl_clr(_adapter *adapter, u8 bcn_ctl_val) +static void hw_bcn_ctrl_clr(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val) { - u8 hw_port = get_hw_port(adapter); u32 bcn_ctl_addr = 0; u8 val8 = 0; @@ -692,105 +857,19 @@ static void hw_bcn_ctrl_clr(_adapter *adapter, u8 bcn_ctl_val) static void hw_bcn_func(_adapter *adapter, u8 enable) { if (enable) - hw_bcn_ctrl_add(adapter, BIT_EN_BCN_FUNCTION); - else - hw_bcn_ctrl_clr(adapter, BIT_EN_BCN_FUNCTION); -} -static void hw_bcn_ctrl_tsf(_adapter *adapter, u8 tsf_udt) -{ - if (tsf_udt) - hw_bcn_ctrl_clr(adapter, BIT_DIS_TSF_UDT); + hw_bcn_ctrl_add(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION); else - hw_bcn_ctrl_add(adapter, BIT_DIS_TSF_UDT); -} - -void hw_port0_tsf_sync_sel(_adapter *adapter, u8 hw_port, u8 benable, u16 tr_offset) -{ - u8 val8; - u8 client_id = 0; - - if (adapter->tsf.sync_port != MAX_HW_PORT) - return; - - if (benable && hw_port == HW_PORT0) { - RTW_ERR(FUNC_ADPT_FMT ": hw_port is port0 under enable\n", FUNC_ADPT_ARG(adapter)); - rtw_warn_on(1); - return; - } - - /*Disable Port0's beacon function*/ - hw_bcn_func(adapter, _FALSE); - - /*Reg 0x518[15:0]: TSFTR_SYN_OFFSET*/ - if (tr_offset) - rtw_write16(adapter, REG_TSFTR_SYN_OFFSET, tr_offset); - - /*reg 0x577[6]=1*/ /*auto sync by tbtt*/ - rtw_write8(adapter, REG_MISC_CTRL, rtw_read8(adapter, REG_MISC_CTRL) | BIT(6)); - - if (HW_PORT1 == hw_port) - client_id = 0; - else if (HW_PORT2 == hw_port) - client_id = 1; - else if (HW_PORT3 == hw_port) - client_id = 2; - else if (HW_PORT4 == hw_port) - client_id = 3; - - /*0x5B4 [6:4] :SYNC_CLI_SEL - The selector for the CLINT port of sync tsft source for port 0*/ - /* Bit[5:4] : 0 for clint0, 1 for clint1, 2 for clint2, 3 for clint3. - Bit6 : 1= enable sync to port 0. 0=disable sync to port 0.*/ - val8 = rtw_read8(adapter, REG_TIMER0_SRC_SEL); - if (benable) { - val8 &= 0x8F; - val8 |= (BIT(6) | (client_id << 4)); - } else { - val8 &= ~BIT(6); - } - rtw_write8(adapter, REG_TIMER0_SRC_SEL, val8); - - /*Enable Port0's beacon function*/ - hw_bcn_func(adapter, _TRUE); - - adapter->tsf.sync_port = hw_port; - adapter->tsf.offset = tr_offset; + hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION); } void hw_port0_tsf_sync(_adapter *adapter) { - rtw_write8(adapter, REG_SCHEDULER_RST, rtw_read8(adapter, REG_SCHEDULER_RST) | BIT_SYNC_CLI); -} -void get_tsf_by_port(_adapter *adapter, u8 *tsftr, u8 hw_port) -{ - u8 i; - u8 val8 = 0; - if (hw_port >= MAX_HW_PORT) { - RTW_ERR("%s hw port(%d) invalid\n", __func__, hw_port); - return; - } - /*0x554[30:28] -BIT_BCN_TIMER_SEL_FWRD*/ - val8 = rtw_read8(adapter, REG_MBSSID_BCN_SPACE + 3); - val8 &= 0x8F; - val8 |= hw_port << 4; - rtw_write8(adapter, REG_MBSSID_BCN_SPACE + 3, val8); - - for (i = 0; i < 8; i++) - tsftr[i] = rtw_read8(adapter, REG_TSFTR+i); -} - -void hw_get_tsftr(_adapter *adapter, u8 *tsftr) -{ - if (!tsftr) { - RTW_ERR("%s tsftr is NULL\n", __func__); - return; - } - - get_tsf_by_port(adapter, tsftr, adapter->hw_port); + rtw_write8(adapter, REG_SCHEDULER_RST, rtw_read8(adapter, REG_SCHEDULER_RST) | BIT_SYNC_CLI_ONCE_BY_TBTT_8821C); } void hw_tsf_reset(_adapter *adapter) { - u8 hw_port = get_hw_port(adapter); + u8 hw_port = rtw_hal_get_port(adapter); u32 tsf_rst_addr = 0; u8 tsf_rst_bit = 0; @@ -805,49 +884,6 @@ void hw_tsf_reset(_adapter *adapter) rtw_write8(adapter, tsf_rst_addr, tsf_rst_bit); } -#ifdef CONFIG_TSF_RESET_OFFLOAD -static int reset_tsf(PADAPTER adapter, u8 reset_port) -{ - u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0; - u32 reg_reset_tsf_cnt = (HW_PORT0 == reset_port) ? - REG_FW_RESET_TSF_CNT_0 : REG_FW_RESET_TSF_CNT_1; - - - /* site survey will cause reset_tsf fail */ - rtw_mi_buddy_scan_abort(adapter, _FALSE); - reset_cnt_after = reset_cnt_before = rtw_read8(adapter, reg_reset_tsf_cnt); - rtl8821c_reset_tsf(adapter, reset_port); - - while ((reset_cnt_after == reset_cnt_before) && (loop_cnt < 10)) { - rtw_msleep_os(100); - loop_cnt++; - reset_cnt_after = rtw_read8(adapter, reg_reset_tsf_cnt); - } - - return (loop_cnt >= 10) ? _FAIL : _TRUE; -} -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - -static void hw_var_set_macaddr(PADAPTER adapter, u8 *val) -{ - if (!val) { - RTW_INFO(ADPT_FMT "set mac address(NULL) failed\n", ADPT_ARG(adapter)); - rtw_warn_on(1); - } - rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), adapter->hw_port, val); -} - -static void hw_var_set_bssid(PADAPTER adapter, u8 *val) -{ - if (!val) { - RTW_INFO(ADPT_FMT "set bssid (NULL) failed\n", ADPT_ARG(adapter)); - rtw_warn_on(1); - } - - rtw_halmac_set_bssid(adapter_to_dvobj(adapter), adapter->hw_port, val); -} - - static void hw_var_set_monitor(PADAPTER Adapter, u8 *val) { u32 rcr_bits; @@ -863,21 +899,25 @@ static void hw_var_set_monitor(PADAPTER Adapter, u8 *val) } /* Receive all type */ - rcr_bits = RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_APWRMGT | RCR_ADF | RCR_ACF | RCR_AMF | RCR_APP_PHYST_RXFF; + rcr_bits = BIT_AAP_8821C | BIT_APM_8821C | BIT_AM_8821C + | BIT_AB_8821C | BIT_APWRMGT_8821C + | BIT_APP_PHYSTS_8821C; #ifdef CONFIG_RX_PACKET_APPEND_FCS /* Append FCS */ - rcr_bits |= RCR_APPFCS; + rcr_bits |= BIT_APP_FCS_8821C; #endif #ifdef CONFIG_RX_PACKET_APPEND_CRC /*CRC and ICV packet will drop in rx func*/ - rcr_bits |= (RCR_ACRC32 | RCR_AICV); + rcr_bits |= (BIT_ACRC32_8821C | BIT_AICV_8821C); #endif - rtl8821c_rcr_config(Adapter, rcr_bits); + rtw_hal_get_hwreg(Adapter, HW_VAR_RCR, (u8 *)&pHalData->rcr_backup); + rtw_hal_set_hwreg(Adapter, HW_VAR_RCR, (u8 *)&rcr_bits); + /* Receive all data frames */ - rtw_write16(Adapter, REG_RXFLTMAP_8821C, 0xFFFF); + rtw_write16(Adapter, REG_RXFLTMAP2_8821C, 0xFFFF); #if 0 /* tx pause */ @@ -885,6 +925,85 @@ static void hw_var_set_monitor(PADAPTER Adapter, u8 *val) #endif } +void hw_set_ta(_adapter *adapter, u8 hw_port, u8 *val) +{ + u8 idx = 0; + u32 reg = port_cfg[hw_port].ta; + + for (idx = 0 ; idx < ETH_ALEN; idx++) + rtw_write8(adapter, (reg + idx), val[idx]); + + RTW_INFO("%s("ADPT_FMT") hw port -%d TA: "MAC_FMT"\n", + __func__, ADPT_ARG(adapter), hw_port, MAC_ARG(val)); +} +void hw_set_aid(_adapter *adapter, u8 hw_port, u8 aid) +{ + rtw_write16(adapter, port_cfg[hw_port].ps_aid, (0xF800 | aid)); + RTW_INFO("%s("ADPT_FMT") hw port -%d AID: %d\n", + __func__, ADPT_ARG(adapter), hw_port, aid); +} +#ifdef CONFIG_CLIENT_PORT_CFG +void rtw_hw_client_port_cfg(_adapter *adapter) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 clt_port = get_clt_port(adapter); + + if (clt_port == CLT_PORT_INVALID) + return; + RTW_INFO("%s ("ADPT_FMT")\n", __func__, ADPT_ARG(adapter)); + + /*Network type*/ + rtw_halmac_set_network_type(adapter_to_dvobj(adapter), clt_port, _HW_STATE_STATION_); + /*A1*/ + rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), clt_port, adapter_mac_addr(adapter)); + /*A2*/ + hw_set_ta(adapter, clt_port, pmlmeinfo->network.MacAddress); + /*A3*/ + rtw_halmac_set_bssid(adapter_to_dvobj(adapter), clt_port, pmlmeinfo->network.MacAddress); + /*Beacon space*/ + rtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), clt_port, pmlmeinfo->bcn_interval); + /*AID*/ + hw_set_aid(adapter, clt_port, pmlmeinfo->aid); + /*Beacon control*/ + hw_bcn_ctrl_set(adapter, clt_port, (BIT_P0_EN_RXBCN_RPT | BIT_EN_BCN_FUNCTION)); + + RTW_INFO("%s ("ADPT_FMT") clt_port:%d\n", __func__, ADPT_ARG(adapter), clt_port); +} + +/*#define DBG_TSF_MONITOR*/ +void rtw_hw_client_port_clr(_adapter *adapter) +{ + u8 null_addr[ETH_ALEN] = {0}; + u8 clt_port = get_clt_port(adapter); + + if (clt_port == CLT_PORT_INVALID) + return; + RTW_INFO("%s ("ADPT_FMT") ==> \n", __func__, ADPT_ARG(adapter)); + #ifdef DBG_TSF_MONITOR + /*Beacon control*/ + hw_bcn_ctrl_clr(adapter, clt_port, BIT_EN_BCN_FUNCTION); + hw_tsf_reset(adapter); + #endif + /*Network type*/ + rtw_halmac_set_network_type(adapter_to_dvobj(adapter), clt_port, _HW_STATE_NOLINK_); + /*A1*/ + rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), clt_port, null_addr); + /*A2*/ + hw_set_ta(adapter, clt_port, null_addr); + /*A3*/ + rtw_halmac_set_bssid(adapter_to_dvobj(adapter), clt_port, null_addr); + #ifdef DBG_TSF_MONITOR + if (0) + #endif + /*Beacon control*/ + hw_bcn_ctrl_set(adapter, clt_port, (BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION)); + /*AID*/ + hw_set_aid(adapter, clt_port, 0); + RTW_INFO("%s("ADPT_FMT") clt_port:%d\n", __func__, ADPT_ARG(adapter), clt_port); +} +#endif + static void hw_var_set_opmode(PADAPTER Adapter, u8 *val) { u8 mode = *((u8 *)val); @@ -892,8 +1011,9 @@ static void hw_var_set_opmode(PADAPTER Adapter, u8 *val) HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); if (isMonitor == _TRUE) { - /* reset RCR */ - rtl8821c_rcr_config(Adapter, pHalData->ReceiveConfig); + /* reset RCR from backup */ + rtw_hal_set_hwreg(Adapter, HW_VAR_RCR, (u8 *)&pHalData->rcr_backup); + rtw_hal_rcr_set_chk_bssid(Adapter, MLME_ACTION_NONE); isMonitor = _FALSE; } @@ -906,9 +1026,6 @@ static void hw_var_set_opmode(PADAPTER Adapter, u8 *val) return; } - Adapter->tsf.sync_port = MAX_HW_PORT; - Adapter->tsf.offset = 0; - rtw_hal_set_hwreg(Adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(Adapter)); /* set mac addr to mac register */ RTW_INFO(ADPT_FMT ": hw_port(%d) set mode=%d\n", ADPT_ARG(Adapter), get_hw_port(Adapter), mode); @@ -920,79 +1037,71 @@ static void hw_var_set_opmode(PADAPTER Adapter, u8 *val) hw_var_set_opmode_mbid(Adapter, mode); #else + rtw_iface_disable_tsf_update(Adapter); + /* set net_type */ Set_MSR(Adapter, mode); if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) { - #ifdef CONFIG_CONCURRENT_MODE - if (!rtw_mi_check_status(Adapter, MI_AP_MODE)) - #endif -#ifdef CONFIG_INTERRUPT_BASED_TXBCN -#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + #ifdef CONFIG_INTERRUPT_BASED_TXBCN + if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter)) { + /*CONFIG_INTERRUPT_BASED_TXBCN*/ + #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT rtw_write8(Adapter, REG_DRVERLYINT, 0x05);/* restore early int time to 5ms */ -#if defined(CONFIG_SDIO_HCI) + #if defined(CONFIG_SDIO_HCI) rtl8821cs_update_interrupt_mask(Adapter, 0, SDIO_HIMR_BCNERLY_INT_MSK); -#endif -#endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ + #endif + #endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ -#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR -#if defined(CONFIG_SDIO_HCI) + #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + #if defined(CONFIG_SDIO_HCI) rtl8821cs_update_interrupt_mask(Adapter, 0, (SDIO_HIMR_TXBCNOK_MSK | SDIO_HIMR_TXBCNERR_MSK)); -#endif -#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ -#endif /* CONFIG_INTERRUPT_BASED_TXBCN */ + #endif + #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ + } + #endif /* CONFIG_INTERRUPT_BASED_TXBCN */ + if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter)) StopTxBeacon(Adapter); - hw_bcn_ctrl_set(Adapter, BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C); + hw_bcn_ctrl_set(Adapter, get_hw_port(Adapter), BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C); - } else if ((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/) { + } else if (mode == _HW_STATE_ADHOC_) { ResumeTxBeacon(Adapter); - hw_bcn_ctrl_set(Adapter, BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C); + hw_bcn_ctrl_set(Adapter, get_hw_port(Adapter), BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C); } else if (mode == _HW_STATE_AP_) { if (Adapter->hw_port == HW_PORT0) { -#ifdef CONFIG_INTERRUPT_BASED_TXBCN -#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT -#if defined(CONFIG_SDIO_HCI) + #ifdef CONFIG_INTERRUPT_BASED_TXBCN + #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + #if defined(CONFIG_SDIO_HCI) rtl8821cs_update_interrupt_mask(Adapter, SDIO_HIMR_BCNERLY_INT_MSK, 0); -#endif -#endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ + #endif + #endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ -#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR -#if defined(CONFIG_SDIO_HCI) + #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + #if defined(CONFIG_SDIO_HCI) rtl8821cs_update_interrupt_mask(Adapter, (SDIO_HIMR_TXBCNOK_MSK | SDIO_HIMR_TXBCNERR_MSK), 0); -#endif -#endif/* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ -#endif /* CONFIG_INTERRUPT_BASED_TXBCN */ - ResumeTxBeacon(Adapter); - rtl8821c_rcr_clear(Adapter, RCR_CBSSID_DATA);/* Clear CBSSID_DATA */ - - /* for 11n Logo 4.2.31/4.2.32, disable BSSID BCN check for AP mode */ - if (Adapter->registrypriv.wifi_spec) - rtl8821c_rcr_clear(Adapter, RCR_CBSSID_BCN); + #endif + #endif/* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ + #endif /* CONFIG_INTERRUPT_BASED_TXBCN */ /* enable to rx data frame */ - rtw_write16(Adapter, REG_RXFLTMAP_8821C, 0xFFFF); + rtw_write16(Adapter, REG_RXFLTMAP2_8821C, 0xFFFF); /* Beacon Control related register for first time */ rtw_write8(Adapter, REG_BCNDMATIM_8821C, 0x02); /* 2ms */ - rtw_write8(Adapter, REG_ATIMWND_8821C, 0x0a); /* 10ms */ - rtw_write16(Adapter, REG_BCNTCFG_8821C, 0x00); - rtw_write16(Adapter, REG_TBTT_PROHIBIT_8821C, 0xff04); + rtw_write8(Adapter, REG_ATIMWND_8821C, 0x0c); /* ATIM:12ms */ + /*rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET_8821C, 0x7fff);*//* +32767 (~32ms) */ hw_tsf_reset(Adapter); /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */ -#if defined(CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR) - hw_bcn_ctrl_set(Adapter, BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C | BIT_P0_EN_TXBCN_RPT_8821C); -#else - hw_bcn_ctrl_set(Adapter, BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C); -#endif - /*TODO hw_port0_tsf_sync_sel must modify for multi-interface && multi-port*/ - if (rtw_mi_buddy_check_fwstate(Adapter, (WIFI_STATION_STATE | WIFI_ASOC_STATE))) - hw_port0_tsf_sync_sel(Adapter, HW_PORT1, _TRUE, 0x32);/* About offset = 50ms*/ - + #if defined(CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR) + hw_bcn_ctrl_set(Adapter, get_hw_port(Adapter), BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C | BIT_P0_EN_TXBCN_RPT_8821C); + #else + hw_bcn_ctrl_set(Adapter, get_hw_port(Adapter), BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C); + #endif } else { RTW_ERR(ADPT_FMT ": set AP mode on HW_PORT%d\n", ADPT_ARG(Adapter), Adapter->hw_port); rtw_warn_on(1); @@ -1005,8 +1114,6 @@ static void hw_var_set_opmode(PADAPTER Adapter, u8 *val) void rtw_hal_port_reconfig(_adapter *adapter, u8 port) { struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); u32 bssid_offset = 0; u8 bssid[6] = {0}; u8 vnet_type = 0; @@ -1025,8 +1132,7 @@ void rtw_hal_port_reconfig(_adapter *adapter, u8 port) /*backup*/ vnet_type = (rtw_read8(adapter, port_cfg[adapter->hw_port].net_type) >> port_cfg[adapter->hw_port].net_type_shift) & 0x03; vbcn_ctrl = rtw_read8(adapter, port_cfg[adapter->hw_port].bcn_ctl); - - if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)) { + if (is_client_associated_to_ap(adapter)) { RTW_INFO("port0-iface is STA mode and linked\n"); bssid_offset = port_cfg[adapter->hw_port].bssid; for (i = 0; i < 6; i++) @@ -1034,13 +1140,20 @@ void rtw_hal_port_reconfig(_adapter *adapter, u8 port) } /*reconfigure*/ adapter->hw_port = port; - hw_var_set_macaddr(adapter, adapter_mac_addr(adapter)); + rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter)); Set_MSR(adapter, vnet_type); - if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)) { - hw_var_set_bssid(adapter, bssid); + if (is_client_associated_to_ap(adapter)) { + rtw_hal_set_hwreg(adapter, HW_VAR_BSSID, bssid); hw_tsf_reset(adapter); + #ifdef CONFIG_FW_MULTI_PORT_SUPPORT + rtw_set_default_port_id(adapter); + #endif } +#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) + if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == _TRUE) + rtw_hal_set_wifi_btc_port_id_cmd(adapter); +#endif rtw_write8(adapter, port_cfg[adapter->hw_port].bcn_ctl, vbcn_ctrl); } @@ -1166,6 +1279,13 @@ static void hw_var_set_basic_rate(PADAPTER adapter, u8 *ratetbl) val32 = rtw_write32(adapter, REG_RRSR_8821C, val32); } +static void hw_var_hw_port_cfg(_adapter *adapter, u8 enable) +{ + if (enable) + hw_bcn_ctrl_add(adapter, get_hw_port(adapter), (BIT_P0_EN_RXBCN_RPT | BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION)); + else + hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION); +} static void hw_var_set_bcn_func(PADAPTER adapter, u8 enable) { u8 val8; @@ -1180,9 +1300,9 @@ static void hw_var_set_bcn_func(PADAPTER adapter, u8 enable) rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C, val8); if (adapter->hw_port == HW_PORT0) - hw_bcn_ctrl_add(adapter, BIT_EN_BCN_FUNCTION_8821C | BIT_P0_EN_TXBCN_RPT_8821C); + hw_bcn_ctrl_add(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION_8821C | BIT_P0_EN_TXBCN_RPT_8821C); else - hw_bcn_ctrl_add(adapter, BIT_EN_BCN_FUNCTION_8821C); + hw_bcn_ctrl_add(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION_8821C); } else { if (adapter->hw_port == HW_PORT0) { val8 = BIT_EN_BCN_FUNCTION_8821C | BIT_P0_EN_TXBCN_RPT_8821C; @@ -1192,143 +1312,41 @@ static void hw_var_set_bcn_func(PADAPTER adapter, u8 enable) if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist) val8 = BIT_P0_EN_TXBCN_RPT_8821C; #endif - hw_bcn_ctrl_clr(adapter, val8); + hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), val8); } else - hw_bcn_ctrl_clr(adapter, BIT_EN_BCN_FUNCTION_8821C); - } -} - -static void hw_var_set_correct_tsf(PADAPTER Adapter) -{ -#ifdef CONFIG_MI_WITH_MBSSID_CAM - /*do nothing*/ -#else -#if 1 - /*hw_tsf_reset(Adapter);*/ - - #ifdef CONFIG_CONCURRENT_MODE - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - /* Update buddy port's TSF if it is SoftAP for beacon TX issue!*/ - if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE - && rtw_mi_check_status(Adapter, MI_AP_MODE)) { - - struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter); - int i; - _adapter *iface; - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; - if (iface == Adapter) - continue; - - if ( check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE - && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE - ) { - hw_port0_tsf_sync_sel(Adapter, Adapter->hw_port, _TRUE, 0x32);/* About offset = 50ms*/ - break; - } - } - } else if (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) - && (Adapter->hw_port == HW_PORT0)) - #endif /*CONFIG_CONCURRENT_MODE*/ - /* disable func of port0 TSF sync from another port*/ - hw_port0_tsf_sync_sel(Adapter, Adapter->hw_port, _FALSE, 0); -#else - u64 tsf; - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - /*tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; */ - tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval * 1024)) - 1024; /*us*/ - - if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { - /*pHalData->RegTxPause |= STOP_BCNQ;BIT(6) - rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6)));*/ - StopTxBeacon(Adapter); - } - - rtw_hal_correct_tsf(Adapter, Adapter->hw_port, tsf); - -#ifdef CONFIG_CONCURRENT_MODE - /* Update buddy port's TSF if it is SoftAP for beacon TX issue!*/ - if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE - && rtw_mi_check_status(Adapter, MI_AP_MODE)) { - - struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter); - int i; - _adapter *iface; - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; - if (iface == Adapter) - continue; - - if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE - && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE - ) { - rtw_hal_correct_tsf(iface, iface->hw_port, tsf); -#ifdef CONFIG_TSF_RESET_OFFLOAD - if (reset_tsf(iface, iface->hw_port) == _FALSE) - RTW_INFO("%s-[ERROR] "ADPT_FMT" Reset port%d TSF fail\n", __func__, ADPT_ARG(iface), iface->hw_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD*/ - } - } - } -#endif /*CONFIG_CONCURRENT_MODE*/ - - if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { - /*pHalData->RegTxPause &= (~STOP_BCNQ); - rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6))));*/ - ResumeTxBeacon(Adapter); + hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION_8821C); } -#endif -#endif/*CONFIG_MI_WITH_MBSSID_CAM*/ -} - -static void hw_var_set_check_bssid(PADAPTER adapter, u8 enable) -{ - u32 rcr; - - rcr = BIT_CBSSID_DATA_8821C | BIT_CBSSID_BCN_8821C; - if (enable) - rtl8821c_rcr_add(adapter, rcr); - else - rtl8821c_rcr_clear(adapter, rcr); - - RTW_INFO("%s: [HW_VAR_CHECK_BSSID] 0x%x=0x%x\n", __FUNCTION__, - REG_RCR_8821C, rtw_read32(adapter, REG_RCR_8821C)); } static void hw_var_set_mlme_disconnect(PADAPTER adapter) { u8 val8; +#ifdef DBG_IFACE_STATUS + DBG_IFACE_STATUS_DUMP(adapter); +#endif + #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE) #endif /* reject all data frames under not link state */ - rtw_write16(adapter, REG_RXFLTMAP_8821C, 0); + rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0); /* reset TSF*/ hw_tsf_reset(adapter); /* disable update TSF*/ - hw_bcn_ctrl_tsf(adapter, _FALSE); + rtw_iface_disable_tsf_update(adapter); - /* disable Port's beacon function */ - hw_bcn_func(adapter, _FALSE); + #ifdef CONFIG_CLIENT_PORT_CFG + if (MLME_IS_STA(adapter)) + rtw_hw_client_port_clr(adapter); + #endif } static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable) { struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - u32 rcr_bit; u16 value_rxfltmap2; u8 val8; PHAL_DATA_TYPE hal; @@ -1345,26 +1363,12 @@ static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable) pmlmepriv = &adapter->mlmepriv; #ifdef CONFIG_FIND_BEST_CHANNEL - rcr_bit = BIT_CBSSID_BCN_8821C | BIT_CBSSID_DATA_8821C; - /* Receive all data frames */ value_rxfltmap2 = 0xFFFF; -#else /* CONFIG_FIND_BEST_CHANNEL */ - - rcr_bit = BIT_CBSSID_BCN_8821C; - - /* config RCR to receive different BSSID & not to receive data frame */ +#else + /* not to receive data frame */ value_rxfltmap2 = 0; -#endif /* CONFIG_FIND_BEST_CHANNEL */ - - if (rtw_mi_check_fwstate(adapter, WIFI_AP_STATE)) - rcr_bit = BIT_CBSSID_BCN_8821C; - -#ifdef CONFIG_TDLS - /* TDLS will clear RCR_CBSSID_DATA bit for connection. */ - else if (adapter->tdlsinfo.link_established == _TRUE) - rcr_bit = BIT_CBSSID_BCN_8821C; -#endif /* CONFIG_TDLS */ +#endif if (enable) { /* @@ -1373,72 +1377,31 @@ static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable) * 3. config RCR to receive different BSSID BCN or probe rsp */ - rtw_write16(adapter, REG_RXFLTMAP_8821C, value_rxfltmap2); - - -#ifdef CONFIG_MI_WITH_MBSSID_CAM - /*do nothing~~*/ -#else - - /* disable update TSF */ - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; - - if (rtw_linked_check(iface) && - check_fwstate(&(iface->mlmepriv), WIFI_AP_STATE) != _TRUE) { - hw_bcn_ctrl_tsf(iface, _FALSE); - iface->mlmeextpriv.en_hw_update_tsf = _FALSE; - } + rtw_write16(adapter, REG_RXFLTMAP2_8821C, value_rxfltmap2); - } -#endif/*CONFIG_MI_WITH_MBSSID_CAM*/ - - rtl8821c_rcr_clear(adapter, rcr_bit); + rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER); /* Save orignal RRSR setting. */ hal->RegRRSR = rtw_read16(adapter, REG_RRSR_8821C); - if (rtw_mi_check_status(adapter, MI_AP_MODE)) - rtl8821c_stop_tx_beacon(adapter); + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) + StopTxBeacon(adapter); } else { /* sitesurvey done * 1. enable rx data frame * 2. config RCR not to receive different BSSID BCN or probe rsp * 3. can enable TSF update & buddy TSF right now due to HW support(IC before 8821C not support ex:8812A/8814A/8192E...) */ - if (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE))/* enable to rx data frame */ - rtw_write16(adapter, REG_RXFLTMAP_8821C, 0xFFFF); - - /* for 11n Logo 4.2.31/4.2.32, disable BSSID BCN check for AP mode */ - if (adapter->registrypriv.wifi_spec && MLME_IS_AP(adapter)) - rcr_bit &= ~(BIT_CBSSID_BCN_8821C); - - rtl8821c_rcr_add(adapter, rcr_bit); -#ifdef CONFIG_MI_WITH_MBSSID_CAM - /*if ((rtw_mi_get_assoced_sta_num(Adapter) == 1) && (!rtw_mi_check_status(Adapter, MI_AP_MODE))) - rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~DIS_TSF_UDT));*/ -#else + if (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE))/* enable to rx data frame */ + rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0xFFFF); - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (!iface) - continue; - if (rtw_linked_check(iface) && - check_fwstate(&(iface->mlmepriv), WIFI_AP_STATE) != _TRUE) { - /* enable HW TSF update when receive beacon*/ - hw_bcn_ctrl_tsf(iface, _TRUE); - iface->mlmeextpriv.en_hw_update_tsf = _FALSE; - } - } -#endif + rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE); /* Restore orignal RRSR setting. */ rtw_write16(adapter, REG_RRSR_8821C, hal->RegRRSR); - if (rtw_mi_check_status(adapter, MI_AP_MODE)) { - rtl8821c_resume_tx_beacon(adapter); + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) { + ResumeTxBeacon(adapter); rtw_mi_tx_beacon_hdl(adapter); } } @@ -1452,7 +1415,7 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) PHAL_DATA_TYPE hal; struct mlme_priv *pmlmepriv; - RetryLimit = 0x30; + RetryLimit = RL_VAL_STA; hal = GET_HAL_DATA(adapter); pmlmepriv = &adapter->mlmepriv; @@ -1460,62 +1423,50 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) #ifdef CONFIG_CONCURRENT_MODE if (type == 0) { /* prepare to join */ - if (rtw_mi_check_status(adapter, MI_AP_MODE)) - rtl8821c_stop_tx_beacon(adapter); + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) + StopTxBeacon(adapter); /* enable to rx data frame.Accept all data frame */ - rtw_write16(adapter, REG_RXFLTMAP_8821C, 0xFFFF); -#ifdef CONFIG_MI_WITH_MBSSID_CAM - /* - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && (rtw_mi_get_assoced_sta_num(Adapter) == 1)) - rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); - else if ((rtw_mi_get_ap_num(Adapter) == 1) && (rtw_mi_get_assoced_sta_num(Adapter) == 1)) - rtw_write32(adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN); - else*/ + rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0xFFFF); - rtl8821c_rcr_clear(adapter, BIT_CBSSID_DATA_8821C | BIT_CBSSID_BCN_8821C); -#else - - if (rtw_mi_check_status(adapter, MI_AP_MODE)) - val32 = BIT_CBSSID_BCN_8821C; - else - val32 = BIT_CBSSID_DATA_8821C | BIT_CBSSID_BCN_8821C; - rtl8821c_rcr_add(adapter, val32); -#endif hw_bcn_func(adapter, _TRUE); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) - RetryLimit = (hal->CustomerID == RT_CID_CCX) ? 7 : 48; + RetryLimit = (hal->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA; else /* Ad-hoc Mode */ - RetryLimit = 0x7; + RetryLimit = RL_VAL_AP; + #ifdef CONFIG_CLIENT_PORT_CFG + rtw_hw_client_port_cfg(adapter); + #endif + + rtw_iface_enable_tsf_update(adapter); } else if (type == 1) { /* joinbss_event call back when join res < 0 */ if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE) - rtw_write16(adapter, REG_RXFLTMAP_8821C, 0x00); + rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0x00); + + rtw_iface_disable_tsf_update(adapter); - if (rtw_mi_check_status(adapter, MI_AP_MODE)) { - rtl8821c_resume_tx_beacon(adapter); + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) { + ResumeTxBeacon(adapter); /* reset TSF 1/2 after resume_tx_beacon */ val8 = BIT_TSFTR_RST_8821C | BIT_TSFTR_CLI0_RST_8821C; rtw_write8(adapter, REG_DUAL_TSF_RST_8821C, val8); } + #ifdef CONFIG_CLIENT_PORT_CFG + if (MLME_IS_STA(adapter)) + rtw_hw_client_port_clr(adapter); + #endif } else if (type == 2) { /* sta add event callback */ -#ifdef CONFIG_MI_WITH_MBSSID_CAM - /*if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && (rtw_mi_get_assoced_sta_num(padapter) == 1)) - rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~DIS_TSF_UDT));*/ -#else - /* enable update TSF */ - hw_bcn_ctrl_tsf(adapter, _TRUE); -#endif if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { rtw_write8(adapter, 0x542, 0x02); - RetryLimit = 0x7; + RetryLimit = RL_VAL_AP; } - if (rtw_mi_check_status(adapter, MI_AP_MODE)) { - rtl8821c_resume_tx_beacon(adapter); + if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) { + ResumeTxBeacon(adapter); /* reset TSF 1/2 after resume_tx_beacon */ rtw_write8(adapter, REG_DUAL_TSF_RST_8821C, BIT_TSFTR_RST_8821C | BIT_TSFTR_CLI0_RST_8821C); @@ -1529,26 +1480,26 @@ static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) /* prepare to join */ /* enable to rx data frame.Accept all data frame */ - rtw_write16(adapter, REG_RXFLTMAP_8821C, 0xFFFF); - - hw_var_set_check_bssid(adapter, !adapter->in_cta_test); + rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0xFFFF); if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) - RetryLimit = (hal->CustomerID == RT_CID_CCX) ? 7 : 48; + RetryLimit = (hal->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA; else /* Ad-hoc Mode */ - RetryLimit = 0x7; + RetryLimit = RL_VAL_AP; hw_bcn_func(adapter, _TRUE); + + rtw_iface_enable_tsf_update(adapter); + } else if (type == 1) { /* joinbss_event call back when join res < 0 */ - rtw_write16(adapter, REG_RXFLTMAP_8821C, 0x00); - } else if (type == 2) { - /* sta add event callback */ + rtw_write16(adapter, REG_RXFLTMAP2_8821C, 0x00); - /* enable update TSF */ - hw_bcn_ctrl_tsf(adapter, _TRUE); + rtw_iface_disable_tsf_update(adapter); + } else if (type == 2) { + /* sta add event callback */ if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) - RetryLimit = 0x7; + RetryLimit = RL_VAL_AP; } val16 = BIT_LRL_8821C(RetryLimit) | BIT_SRL_8821C(RetryLimit); @@ -1583,49 +1534,6 @@ static void hw_var_set_acm_ctrl(PADAPTER adapter, u8 ctrl) rtw_write8(adapter, REG_ACMHWCTRL_8821C, hwctrl); } -static void hw_var_set_rcr_am(PADAPTER adapter, u8 enable) -{ - u32 rcr; - - rcr = BIT_AM_8821C; - if (enable) - rtl8821c_rcr_add(adapter, rcr); - else - rtl8821c_rcr_clear(adapter, rcr); - - RTW_INFO("%s: [HW_VAR_ON_RCR_AM] RCR(0x%x)=0x%x\n", - __FUNCTION__, REG_RCR_8821C, rtw_read32(adapter, REG_RCR_8821C)); -} - -static void hw_var_set_bcn_interval(PADAPTER adapter, u16 bcn_interval) -{ - - u8 hw_port = get_hw_port(adapter); - u32 bcn_interval_addr = 0; - u8 bcn_interval_shift = 0; - u16 bcn_interval_mask = 0; - u32 val32 = 0; - - if (hw_port >= MAX_HW_PORT) { - RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port); - rtw_warn_on(1); - return; - } - - bcn_interval_addr = port_cfg[hw_port].bcn_space; - bcn_interval_shift = port_cfg[hw_port].bcn_space_shift; - bcn_interval_mask = port_cfg[hw_port].bcn_space_mask; - - val32 = rtw_read32(adapter, bcn_interval_addr); - val32 &= (~(bcn_interval_mask << bcn_interval_shift)); - val32 |= (bcn_interval & bcn_interval_mask) << bcn_interval_shift; - - rtw_write32(adapter, bcn_interval_addr, val32); - - RTW_INFO(ADPT_FMT" BEACON_INTERVAL : 0x%x = 0x%x\n", ADPT_ARG(adapter), - bcn_interval_addr, (rtw_read32(adapter, bcn_interval_addr) >> bcn_interval_shift) & bcn_interval_mask); -} - static void hw_var_set_sec_cfg(PADAPTER adapter, u8 cfg) { u16 reg_scr_ori; @@ -1717,7 +1625,7 @@ static void hw_var_set_ack_preamble(PADAPTER adapter, u8 bShortPreamble) rtw_write8(adapter, REG_WMAC_TRXPTCL_CTL_8821C + 2, val8); } -void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) +void rtl8821c_dl_rsvd_page(PADAPTER adapter, u8 mstatus) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; @@ -1726,21 +1634,24 @@ void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) BOOLEAN bcn_valid = _FALSE; u8 DLBcnCount = 0; u32 poll = 0; - u8 val8; - + u8 val8, org_bcn, org_cr; + u8 hw_port = rtw_hal_get_port(adapter); RTW_INFO(FUNC_ADPT_FMT ":+ hw_port=%d mstatus(%x)\n", - FUNC_ADPT_ARG(adapter), get_hw_port(adapter), mstatus); + FUNC_ADPT_ARG(adapter), hw_port, mstatus); if (mstatus == RT_MEDIA_CONNECT) { +#if 0 BOOLEAN bRecover = _FALSE; +#endif u8 v8; /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 8821C -bit 10:0 */ - rtw_write16(adapter, port_cfg[get_hw_port(adapter)].ps_aid, (0xF800 | pmlmeinfo->aid)); + rtw_write16(adapter, port_cfg[hw_port].ps_aid, (0xF800 | pmlmeinfo->aid)); /* Enable SW TX beacon - Set REG_CR bit 8. DMA beacon by SW */ v8 = rtw_read8(adapter, REG_CR_8821C + 1); + org_cr = v8; v8 |= (BIT_ENSWBCN_8821C >> 8); rtw_write8(adapter, REG_CR_8821C + 1, v8); @@ -1749,30 +1660,31 @@ void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) * Fix download reserved page packet fail that access collision with the protection time. */ val8 = rtw_read8(adapter, REG_BCN_CTRL_8821C); + org_bcn = val8; val8 &= ~BIT_EN_BCN_FUNCTION_8821C; val8 |= BIT_DIS_TSF_UDT_8821C; rtw_write8(adapter, REG_BCN_CTRL_8821C, val8); #if 0 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ - if (hal->RegFwHwTxQCtrl & BIT(6)) + RegFwHwTxQCtrl = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2); + + if (RegFwHwTxQCtrl & BIT(6)) bRecover = _TRUE; /* To tell Hw the packet is not a real beacon frame. */ - val8 = hal->RegFwHwTxQCtrl & ~BIT(6); - rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2, val8); - hal->RegFwHwTxQCtrl &= ~BIT(6); + RegFwHwTxQCtrl &= ~BIT(6); + rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2, RegFwHwTxQCtrl); #endif /* Clear beacon valid check bit. */ rtw_hal_set_hwreg(adapter, HW_VAR_BCN_VALID, NULL); - rtw_hal_set_hwreg(adapter, HW_VAR_DL_BCN_SEL, NULL); DLBcnCount = 0; poll = 0; do { /* download rsvd page. */ - rtw_hal_set_fw_rsvd_page(adapter, 0); + rtw_hal_set_fw_rsvd_page(adapter, _FALSE); DLBcnCount++; do { rtw_yield_os(); @@ -1787,19 +1699,19 @@ void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) if (RTW_CANNOT_RUN(adapter)) ; else if (!bcn_valid) - RTW_INFO(FUNC_ADPT_FMT ": DL RSVD page failed! DLBcnCount:%u, poll:%u\n", + RTW_ERR(FUNC_ADPT_FMT ": DL RSVD page failed! DLBcnCount:%u, poll:%u\n", FUNC_ADPT_ARG(adapter), DLBcnCount, poll); else { struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + pwrctl->fw_psmode_iface_id = adapter->iface_id; + rtw_hal_set_fw_rsvd_page(adapter, _TRUE); RTW_INFO(ADPT_FMT ": DL RSVD page success! DLBcnCount:%u, poll:%u\n", ADPT_ARG(adapter), DLBcnCount, poll); } - val8 = rtw_read8(adapter, REG_BCN_CTRL_8821C); - val8 |= BIT_EN_BCN_FUNCTION_8821C; - val8 &= ~BIT_DIS_TSF_UDT_8821C; - rtw_write8(adapter, REG_BCN_CTRL_8821C, val8); + rtw_write8(adapter, REG_CR_8821C + 1, org_cr); + rtw_write8(adapter, REG_BCN_CTRL_8821C, org_bcn); #if 0 /* * To make sure that if there exists an adapter which would like to send beacon. @@ -1808,8 +1720,8 @@ void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) * the beacon cannot be sent by HW. */ if (bRecover) { - rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2, hal->RegFwHwTxQCtrl | BIT(6)); - hal->RegFwHwTxQCtrl |= BIT(6); + RegFwHwTxQCtrl |= BIT(6); + rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2, RegFwHwTxQCtrl); } #endif #ifndef CONFIG_PCI_HCI @@ -1822,27 +1734,12 @@ void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) } -static void hw_var_set_h2c_fw_joinbssrpt(PADAPTER adapter, u8 mstatus) +static void rtl8821c_set_h2c_fw_joinbssrpt(PADAPTER adapter, u8 mstatus) { if (mstatus == RT_MEDIA_CONNECT) - hw_var_set_dl_rsvd_page(adapter, RT_MEDIA_CONNECT); -} - -/* - * Description: Get the reserved page number in Tx packet buffer. - * Retrun value: the page number. - */ -u8 get_txbuffer_rsvdpagenum(PADAPTER adapter, bool wowlan) -{ - u8 RsvdPageNum = HALMAC_RSVD_DRV_PGNUM_8821C; - -#ifdef CONFIG_PNO_SUPPORT - RsvdPageNum = 32; -#endif - return RsvdPageNum; + rtl8821c_dl_rsvd_page(adapter, RT_MEDIA_CONNECT); } - /* * Parameters: * adapter @@ -1856,9 +1753,10 @@ static u8 rx_agg_switch(PADAPTER adapter, u8 enable) return _FAIL; } -void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) +u8 rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + u8 ret = _SUCCESS; u8 val8; u16 val16; u32 val32; @@ -1868,14 +1766,6 @@ void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_SET_OPMODE: hw_var_set_opmode(adapter, val); break; - - case HW_VAR_MAC_ADDR: - hw_var_set_macaddr(adapter, val); - break; - - case HW_VAR_BSSID: - hw_var_set_bssid(adapter, val); - break; /* case HW_VAR_INIT_RTS_RATE: break; @@ -1892,12 +1782,8 @@ void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) hw_var_set_bcn_func(adapter, *val); break; - case HW_VAR_CORRECT_TSF: - hw_var_set_correct_tsf(adapter); - break; - - case HW_VAR_CHECK_BSSID: - hw_var_set_check_bssid(adapter, *val); + case HW_VAR_PORT_CFG: + hw_var_hw_port_cfg(adapter, *val); break; case HW_VAR_MLME_DISCONNECT: @@ -1910,54 +1796,18 @@ void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) if (hal->EEPROMBluetoothCoexist) rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE); else - rtw_btcoex_wifionly_scan_notify(adapter); -#else /* !CONFIG_BT_COEXIST */ - rtw_btcoex_wifionly_scan_notify(adapter); #endif /* CONFIG_BT_COEXIST */ - + rtw_btcoex_wifionly_scan_notify(adapter); break; case HW_VAR_MLME_JOIN: hw_var_set_mlme_join(adapter, *val); - #ifdef CONFIG_BT_COEXIST - if (hal->EEPROMBluetoothCoexist) { - switch (*val) { - case 0: - /* Notify coex. mechanism before join */ - rtw_btcoex_ConnectNotify(adapter, _TRUE); - break; - case 1: - case 2: - /* Notify coex. mechanism after join, whether successful or failed */ - rtw_btcoex_ConnectNotify(adapter, _FALSE); - break; - } - } + if (hal->EEPROMBluetoothCoexist) + rtw_btcoex_ConnectNotify(adapter, *val ? _FALSE : _TRUE); + else #endif /* CONFIG_BT_COEXIST */ - break; - - case HW_VAR_ON_RCR_AM: - hw_var_set_rcr_am(adapter, 1); - break; - - case HW_VAR_OFF_RCR_AM: - hw_var_set_rcr_am(adapter, 0); - break; - - case HW_VAR_BEACON_INTERVAL: - hw_var_set_bcn_interval(adapter, *(u16 *)val); -#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT - { - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - u16 bcn_interval = *((u16 *)val); - if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { - RTW_INFO("%s==> bcn_interval:%d, eraly_int:%d\n", __FUNCTION__, bcn_interval, bcn_interval >> 1); - rtw_write8(adapter, REG_DRVERLYINT, bcn_interval >> 1); /* 50ms for sdio */ - } - } -#endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ + rtw_btcoex_wifionly_connect_notify(adapter); break; case HW_VAR_SLOT_TIME: @@ -2028,6 +1878,7 @@ void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_AMPDU_MIN_SPACE: break; */ +#ifdef CONFIG_80211N_HT case HW_VAR_AMPDU_FACTOR: { u32 AMPDULen = *val; /* enum AGGRE_SIZE */ @@ -2035,7 +1886,7 @@ void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) rtw_write32(adapter, REG_AMPDU_MAX_LENGTH_8821C, AMPDULen); } break; - +#endif /* CONFIG_80211N_HT */ case HW_VAR_RXDMA_AGG_PG_TH: /* * TH=1 => invalidate RX DMA aggregation @@ -2057,39 +1908,34 @@ void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) break; */ case HW_VAR_H2C_FW_JOINBSSRPT: - hw_var_set_h2c_fw_joinbssrpt(adapter, *val); + rtl8821c_set_h2c_fw_joinbssrpt(adapter, *val); break; - /* + case HW_VAR_DL_RSVD_PAGE: + #ifdef CONFIG_BT_COEXIST + if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + rtl8821c_download_BTCoex_AP_mode_rsvd_page(adapter); + #endif + break; /* case HW_VAR_FWLPS_RF_ON: break; */ #ifdef CONFIG_P2P case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: + #ifdef CONFIG_FW_MULTI_PORT_SUPPORT + if (*val == P2P_PS_ENABLE) + rtw_set_default_port_id(adapter); + #endif rtw_set_p2p_ps_offload_cmd(adapter, *val); break; #endif -#ifdef CONFIG_TDLS - case HW_VAR_TDLS_WRCR: - rtl8821c_rcr_clear(adapter, BIT_CBSSID_DATA_8821C); - break; - - case HW_VAR_TDLS_RS_RCR: - rtl8821c_rcr_add(adapter, BIT_CBSSID_DATA_8821C); - break; -#endif /* case HW_VAR_TRIGGER_GPIO_0: case HW_VAR_BT_SET_COEXIST: case HW_VAR_BT_ISSUE_DELBA: - case HW_VAR_CURRENT_ANTENNA: break; */ -#ifdef CONFIG_SW_ANTENNA_DIVERSITY - case HW_VAR_ANTENNA_DIVERSITY_SELECT: - ODM_SetAntConfig(&hal->odmpriv, *val); - break; -#endif + /* case HW_VAR_SWITCH_EPHY_WoWLAN: case HW_VAR_EFUSE_USAGE: @@ -2163,7 +2009,8 @@ void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_CHECK_TXBUF: { u16 rtylmtorg; u8 RetryLimit = 0x01; - u32 start, passtime; + systime start; + u32 passtime; u32 timelmt = 2000; /* ms */ u32 waittime = 10; /* ms */ u32 high, low, normal, extra, publc; @@ -2240,6 +2087,7 @@ void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) RTW_INFO("[HW_VAR_CHECK_TXBUF] NOT empty in %d ms\n", passtime); RTW_INFO("[HW_VAR_CHECK_TXBUF] 0x230=0x%08x 0x234=0x%08x 0x238=0x%08x 0x23c=0x%08x 0x240=0x%08x\n", high, low, normal, extra, publc); + } rtw_write16(adapter, REG_RETRY_LIMIT_8821C, rtylmtorg); @@ -2254,6 +2102,27 @@ void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_SYS_CLKR: break; */ +#ifdef CONFIG_GPIO_WAKEUP + case HW_SET_GPIO_WL_CTRL: { + u8 enable = *val; + u8 value = 0; + u8 addr = REG_PAD_CTRL1_8821C + 3; + + if (WAKEUP_GPIO_IDX == 6) { + value = rtw_read8(adapter, addr); + + if (enable == _TRUE && (value & BIT(1))) + /* set 0x64[25] = 0 to control GPIO 6 */ + rtw_write8(adapter, addr, value & (~BIT(1))); + else if (enable == _FALSE) + rtw_write8(adapter, addr, value | BIT(1)); + + RTW_INFO("[HW_SET_GPIO_WL_CTRL] 0x%02X=0x%02X\n", + addr, rtw_read8(adapter, addr)); + } + } + break; +#endif case HW_VAR_NAV_UPPER: { #define HAL_NAV_UPPER_UNIT 128 /* micro-second */ u32 usNavUpper = *(u32 *)val; @@ -2291,136 +2160,58 @@ void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) } break; #endif - case HW_VAR_DO_IQK: - if (*val) - hal->bNeedIQK = _TRUE; - else - hal->bNeedIQK = _FALSE; - break; - case HW_VAR_DM_IN_LPS: - rtl8821c_phy_haldm_in_lps(adapter); - break; /* - case HW_VAR_SET_REQ_FW_PS: - case HW_VAR_FW_PS_STATE: - case HW_VAR_SOUNDING_ENTER: - case HW_VAR_SOUNDING_LEAVE: case HW_VAR_SOUNDING_RATE: case HW_VAR_SOUNDING_STATUS: case HW_VAR_SOUNDING_FW_NDPA: case HW_VAR_SOUNDING_CLK: break; */ - case HW_VAR_DL_RSVD_PAGE: -#ifdef CONFIG_BT_COEXIST - if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) - rtl8821c_download_BTCoex_AP_mode_rsvd_page(adapter); - else -#endif - { - hw_var_set_dl_rsvd_page(adapter, RT_MEDIA_CONNECT); - } - break; - - case HW_VAR_MACID_SLEEP: { - u32 reg_macid_sleep; - u8 bit_shift; - u8 id = *(u8 *)val; - - if (id < 32) { - reg_macid_sleep = REG_MACID_SLEEP_8821C; - bit_shift = id; - } else if (id < 64) { - reg_macid_sleep = REG_MACID_SLEEP1_8821C; - bit_shift = id - 32; - } else if (id < 96) { - reg_macid_sleep = REG_MACID_SLEEP2_8821C; - bit_shift = id - 64; - } else if (id < 128) { - reg_macid_sleep = REG_MACID_SLEEP3_8821C; - bit_shift = id - 96; - } else { - rtw_warn_on(1); - break; - } - - val32 = rtw_read32(adapter, reg_macid_sleep); - RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] macid=%d, org reg_0x%03x=0x%08X\n", - FUNC_ADPT_ARG(adapter), id, reg_macid_sleep, val32); - - if (val32 & BIT(bit_shift)) - break; - - val32 |= BIT(bit_shift); - rtw_write32(adapter, reg_macid_sleep, val32); - } - break; - - case HW_VAR_MACID_WAKEUP: { - u32 reg_macid_sleep; - u8 bit_shift; - u8 id = *(u8 *)val; - - if (id < 32) { - reg_macid_sleep = REG_MACID_SLEEP_8821C; - bit_shift = id; - } else if (id < 64) { - reg_macid_sleep = REG_MACID_SLEEP1_8821C; - bit_shift = id - 32; - } else if (id < 96) { - reg_macid_sleep = REG_MACID_SLEEP2_8821C; - bit_shift = id - 64; - } else if (id < 128) { - reg_macid_sleep = REG_MACID_SLEEP3_8821C; - bit_shift = id - 96; - } else { - rtw_warn_on(1); - break; - } - - val32 = rtw_read32(adapter, reg_macid_sleep); - RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] macid=%d, org reg_0x%03x=0x%08X\n", - FUNC_ADPT_ARG(adapter), id, reg_macid_sleep, val32); +#ifdef CONFIG_BEAMFORMING + case HW_VAR_SOUNDING_ENTER: + rtl8821c_phy_bf_enter(adapter, (struct sta_info*)val); + break; - if (!(val32 & BIT(bit_shift))) - break; - - val32 &= ~BIT(bit_shift); - rtw_write32(adapter, reg_macid_sleep, val32); - } - break; + case HW_VAR_SOUNDING_LEAVE: + rtl8821c_phy_bf_leave(adapter, val); + break; + case HW_VAR_SOUNDING_SET_GID_TABLE: + rtl8821c_phy_bf_set_gid_table(adapter, (struct beamformer_entry*)val); + break; +#endif default: - SetHwReg(adapter, variable, val); + ret = SetHwReg(adapter, variable, val); break; } + return ret; } struct qinfo { - u32 head:8; - u32 pkt_num:7; - u32 tail:8; + u32 head:11; + u32 tail:11; + u32 empty:1; u32 ac:2; u32 macid:7; }; struct bcn_qinfo { - u16 head:8; - u16 pkt_num:8; + u16 head:12; + u16 rsvd:4; }; -static void dump_qinfo(void *sel, struct qinfo *info, const char *tag) +static void dump_qinfo(void *sel, struct qinfo *info, u32 pkt_num, const char *tag) { RTW_PRINT_SEL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n", - tag ? tag : "", info->head, info->tail, info->pkt_num, info->macid, info->ac); + tag ? tag : "", info->head, info->tail, pkt_num, info->macid, info->ac); } -static void dump_bcn_qinfo(void *sel, struct bcn_qinfo *info, const char *tag) +static void dump_bcn_qinfo(void *sel, struct bcn_qinfo *info, u32 pkt_num, const char *tag) { RTW_PRINT_SEL(sel, "%shead:0x%02x, pkt_num:%u\n", - tag ? tag : "", info->head, info->pkt_num); + tag ? tag : "", info->head, pkt_num); } static void dump_mac_qinfo(void *sel, _adapter *adapter) @@ -2436,6 +2227,13 @@ static void dump_mac_qinfo(void *sel, _adapter *adapter) u32 mg_q_info; u32 hi_q_info; u16 bcn_q_info; + u32 q0_q1_info; + u32 q2_q3_info; + u32 q4_q5_info; + u32 q6_q7_info; + u32 mg_hi_q_info; + u32 cmd_bcn_q_info; + q0_info = rtw_read32(adapter, REG_Q0_INFO_8821C); q1_info = rtw_read32(adapter, REG_Q1_INFO_8821C); @@ -2449,17 +2247,49 @@ static void dump_mac_qinfo(void *sel, _adapter *adapter) hi_q_info = rtw_read32(adapter, REG_HIQ_INFO_8821C); bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO_8821C); - dump_qinfo(sel, (struct qinfo *)&q0_info, "Q0 "); - dump_qinfo(sel, (struct qinfo *)&q1_info, "Q1 "); - dump_qinfo(sel, (struct qinfo *)&q2_info, "Q2 "); - dump_qinfo(sel, (struct qinfo *)&q3_info, "Q3 "); - dump_qinfo(sel, (struct qinfo *)&q4_info, "Q4 "); - dump_qinfo(sel, (struct qinfo *)&q5_info, "Q5 "); - dump_qinfo(sel, (struct qinfo *)&q6_info, "Q6 "); - dump_qinfo(sel, (struct qinfo *)&q7_info, "Q7 "); - dump_qinfo(sel, (struct qinfo *)&mg_q_info, "MG "); - dump_qinfo(sel, (struct qinfo *)&hi_q_info, "HI "); - dump_bcn_qinfo(sel, (struct bcn_qinfo *)&bcn_q_info, "BCN "); + q0_q1_info = rtw_read32(adapter, REG_Q0_Q1_INFO_8821C); + q2_q3_info = rtw_read32(adapter, REG_Q2_Q3_INFO_8821C); + q4_q5_info = rtw_read32(adapter, REG_Q4_Q5_INFO_8821C); + q6_q7_info = rtw_read32(adapter, REG_Q6_Q7_INFO_8821C); + mg_hi_q_info = rtw_read32(adapter, REG_MGQ_HIQ_INFO_8821C); + cmd_bcn_q_info = rtw_read32(adapter, REG_CMDQ_BCNQ_INFO_8821C); + + dump_qinfo(sel, (struct qinfo *)&q0_info, q0_q1_info&0xFFF, "Q0 "); + dump_qinfo(sel, (struct qinfo *)&q1_info, (q0_q1_info>>15)&0xFFF, "Q1 "); + dump_qinfo(sel, (struct qinfo *)&q2_info, q2_q3_info&0xFFF, "Q2 "); + dump_qinfo(sel, (struct qinfo *)&q3_info, (q2_q3_info>>15)&0xFFF, "Q3 "); + dump_qinfo(sel, (struct qinfo *)&q4_info, q4_q5_info&0xFFF, "Q4 "); + dump_qinfo(sel, (struct qinfo *)&q5_info, (q4_q5_info>>15)&0xFFF, "Q5 "); + dump_qinfo(sel, (struct qinfo *)&q6_info, q6_q7_info&0xFFF, "Q6 "); + dump_qinfo(sel, (struct qinfo *)&q7_info, (q6_q7_info>>15)&0xFFF, "Q7 "); + dump_qinfo(sel, (struct qinfo *)&mg_q_info, mg_hi_q_info&0xFFF, "MG "); + dump_qinfo(sel, (struct qinfo *)&hi_q_info, (mg_hi_q_info>>15)&0xFFF, "HI "); + dump_bcn_qinfo(sel, (struct bcn_qinfo *)&bcn_q_info, cmd_bcn_q_info&0xFFF, "BCN "); + +} + +static void dump_mac_txfifo(void *sel, _adapter *adapter) +{ + u32 hpq, lpq, npq, epq, pubq; + + hpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_1_8821C); + lpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_2_8821C); + npq = rtw_read32(adapter, REG_FIFOPAGE_INFO_3_8821C); + epq = rtw_read32(adapter, REG_FIFOPAGE_INFO_4_8821C); + pubq = rtw_read32(adapter, REG_FIFOPAGE_INFO_5_8821C); + + hpq = (hpq & 0xFFF0000)>>16; + lpq = (lpq & 0xFFF0000)>>16; + npq = (npq & 0xFFF0000)>>16; + epq = (epq & 0xFFF0000)>>16; + pubq = (pubq & 0xFFF0000)>>16; + + RTW_PRINT_SEL(sel, "Tx: available page num: "); + if ((hpq == 0xAEA) && (hpq == lpq) && (hpq == pubq)) + RTW_PRINT_SEL(sel, "N/A (reg val = 0xea)\n"); + else + RTW_PRINT_SEL(sel, "HPQ: %d, LPQ: %d, NPQ: %d, EPQ: %d, PUBQ: %d\n" + , hpq, lpq, npq, epq, pubq); } static u8 hw_var_get_bcn_valid(PADAPTER adapter) @@ -2474,6 +2304,48 @@ static u8 hw_var_get_bcn_valid(PADAPTER adapter) return ret; } +void rtl8821c_read_wmmedca_reg(PADAPTER adapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params) +{ + u8 vo_reg_params[4]; + u8 vi_reg_params[4]; + u8 be_reg_params[4]; + u8 bk_reg_params[4]; + + rtl8821c_gethwreg(adapter, HW_VAR_AC_PARAM_VO, vo_reg_params); + rtl8821c_gethwreg(adapter, HW_VAR_AC_PARAM_VI, vi_reg_params); + rtl8821c_gethwreg(adapter, HW_VAR_AC_PARAM_BE, be_reg_params); + rtl8821c_gethwreg(adapter, HW_VAR_AC_PARAM_BK, bk_reg_params); + + vo_params[0] = vo_reg_params[0]; + vo_params[1] = vo_reg_params[1] & 0x0F; + vo_params[2] = (vo_reg_params[1] & 0xF0) >> 4; + vo_params[3] = ((vo_reg_params[3] << 8) | (vo_reg_params[2])) * 32; + + vi_params[0] = vi_reg_params[0]; + vi_params[1] = vi_reg_params[1] & 0x0F; + vi_params[2] = (vi_reg_params[1] & 0xF0) >> 4; + vi_params[3] = ((vi_reg_params[3] << 8) | (vi_reg_params[2])) * 32; + + be_params[0] = be_reg_params[0]; + be_params[1] = be_reg_params[1] & 0x0F; + be_params[2] = (be_reg_params[1] & 0xF0) >> 4; + be_params[3] = ((be_reg_params[3] << 8) | (be_reg_params[2])) * 32; + + bk_params[0] = bk_reg_params[0]; + bk_params[1] = bk_reg_params[1] & 0x0F; + bk_params[2] = (bk_reg_params[1] & 0xF0) >> 4; + bk_params[3] = ((bk_reg_params[3] << 8) | (bk_reg_params[2])) * 32; + + vo_params[1] = (1 << vo_params[1]) - 1; + vo_params[2] = (1 << vo_params[2]) - 1; + vi_params[1] = (1 << vi_params[1]) - 1; + vi_params[2] = (1 << vi_params[2]) - 1; + be_params[1] = (1 << be_params[1]) - 1; + be_params[2] = (1 << be_params[2]) - 1; + bk_params[1] = (1 << bk_params[1]) - 1; + bk_params[2] = (1 << bk_params[2]) - 1; +} + void rtl8821c_gethwreg(PADAPTER adapter, u8 variable, u8 *val) { PHAL_DATA_TYPE hal; @@ -2486,9 +2358,6 @@ void rtl8821c_gethwreg(PADAPTER adapter, u8 variable, u8 *val) switch (variable) { /* - case HW_VAR_SET_OPMODE: - case HW_VAR_MAC_ADDR: - case HW_VAR_BSSID: case HW_VAR_INIT_RTS_RATE: case HW_VAR_BASIC_RATE: break; @@ -2498,13 +2367,9 @@ void rtl8821c_gethwreg(PADAPTER adapter, u8 variable, u8 *val) break; /* case HW_VAR_BCN_FUNC: - case HW_VAR_CORRECT_TSF: - case HW_VAR_CHECK_BSSID: case HW_VAR_MLME_DISCONNECT: case HW_VAR_MLME_SITESURVEY: case HW_VAR_MLME_JOIN: - case HW_VAR_ON_RCR_AM: - case HW_VAR_OFF_RCR_AM: case HW_VAR_BEACON_INTERVAL: case HW_VAR_SLOT_TIME: case HW_VAR_RESP_SIFS: @@ -2520,10 +2385,39 @@ void rtl8821c_gethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_RF_TYPE: case HW_VAR_CAM_EMPTY_ENTRY: case HW_VAR_CAM_INVALID_ALL: - case HW_VAR_AC_PARAM_VO: - case HW_VAR_AC_PARAM_VI: - case HW_VAR_AC_PARAM_BE: - case HW_VAR_AC_PARAM_BK: + */ + case HW_VAR_AC_PARAM_VO: + val32 = rtw_read32(adapter, REG_EDCA_VO_PARAM); + val[0] = val32 & 0xFF; + val[1] = (val32 >> 8) & 0xFF; + val[2] = (val32 >> 16) & 0xFF; + val[3] = (val32 >> 24) & 0x07; + break; + + case HW_VAR_AC_PARAM_VI: + val32 = rtw_read32(adapter, REG_EDCA_VI_PARAM); + val[0] = val32 & 0xFF; + val[1] = (val32 >> 8) & 0xFF; + val[2] = (val32 >> 16) & 0xFF; + val[3] = (val32 >> 24) & 0x07; + break; + + case HW_VAR_AC_PARAM_BE: + val32 = rtw_read32(adapter, REG_EDCA_BE_PARAM); + val[0] = val32 & 0xFF; + val[1] = (val32 >> 8) & 0xFF; + val[2] = (val32 >> 16) & 0xFF; + val[3] = (val32 >> 24) & 0x07; + break; + + case HW_VAR_AC_PARAM_BK: + val32 = rtw_read32(adapter, REG_EDCA_BK_PARAM); + val[0] = val32 & 0xFF; + val[1] = (val32 >> 8) & 0xFF; + val[2] = (val32 >> 16) & 0xFF; + val[3] = (val32 >> 24) & 0x07; + break; + /* case HW_VAR_ACM_CTRL: case HW_VAR_AMPDU_MIN_SPACE: case HW_VAR_AMPDU_FACTOR: @@ -2533,39 +2427,14 @@ void rtl8821c_gethwreg(PADAPTER adapter, u8 variable, u8 *val) case HW_VAR_H2C_FW_JOINBSSRPT: break; */ - case HW_VAR_FWLPS_RF_ON: - /* When we halt NIC, we should check if FW LPS is leave. */ - if (rtw_is_surprise_removed(adapter) || - (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off)) { - /* - * If it is in HW/SW Radio OFF or IPS state, - * we do not check Fw LPS Leave, - * because Fw is unload. - */ - *val = _TRUE; - } else { - rtl8821c_rcr_get(adapter, &val32); - val32 &= (BIT_UC_MD_EN_8821C | BIT_BC_MD_EN_8821C | BIT_TIM_PARSER_EN_8821C); - if (val32) - *val = _FALSE; - else - *val = _TRUE; - } - break; /* case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: - case HW_VAR_TDLS_WRCR: - case HW_VAR_TDLS_RS_RCR: case HW_VAR_TRIGGER_GPIO_0: case HW_VAR_BT_SET_COEXIST: case HW_VAR_BT_ISSUE_DELBA: break; */ -#ifdef CONFIG_ANTENNA_DIVERSITY - case HW_VAR_CURRENT_ANTENNA: - *val = hal->CurAntenna; - break; -#endif + /* case HW_VAR_ANTENNA_DIVERSITY_SELECT: case HW_VAR_SWITCH_EPHY_WoWLAN: @@ -2580,10 +2449,6 @@ void rtl8821c_gethwreg(PADAPTER adapter, u8 variable, u8 *val) break; */ - /* - case HW_VAR_HCI_SUS_STATE: - break; - */ #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) @@ -2601,33 +2466,45 @@ void rtl8821c_gethwreg(PADAPTER adapter, u8 variable, u8 *val) val16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8821C); *val = (val16 & BIT_HQQ_EMPTY_8821C) ? _TRUE : _FALSE; break; + case HW_VAR_CHK_MGQ_CPU_EMPTY: + val16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8821C); + *val = (val16 & BIT_MGQ_CPU_EMPTY_8821C) ? _TRUE : _FALSE; + break; /* case HW_VAR_AMPDU_MAX_TIME: case HW_VAR_WIRELESS_MODE: case HW_VAR_USB_MODE: case HW_VAR_DO_IQK: - case HW_VAR_DM_IN_LPS: - case HW_VAR_SET_REQ_FW_PS: - case HW_VAR_FW_PS_STATE: case HW_VAR_SOUNDING_ENTER: case HW_VAR_SOUNDING_LEAVE: case HW_VAR_SOUNDING_RATE: case HW_VAR_SOUNDING_STATUS: case HW_VAR_SOUNDING_FW_NDPA: case HW_VAR_SOUNDING_CLK: - case HW_VAR_DL_RSVD_PAGE: - case HW_VAR_MACID_SLEEP: - case HW_VAR_MACID_WAKEUP: break; */ + case HW_VAR_FW_PS_STATE: + /* driver read REG_SYS_CFG5 - BIT_LPS_STATUS REG_1070[3] to get hw ps state */ + *((u16 *)val) = rtw_read8(adapter, REG_SYS_CFG5); + break; + case HW_VAR_DUMP_MAC_QUEUE_INFO: dump_mac_qinfo(val, adapter); break; + + case HW_VAR_DUMP_MAC_TXFIFO: + dump_mac_txfifo(val, adapter); + break; /* case HW_VAR_ASIX_IOT: case HW_VAR_H2C_BT_MP_OPER: break; */ + + case HW_VAR_BCN_CTRL_ADDR: + *((u32 *)val) = hw_bcn_ctrl_addr(adapter, adapter->hw_port); + break; + default: GetHwReg(adapter, variable, val); break; @@ -2641,7 +2518,7 @@ void rtl8821c_gethwreg(PADAPTER adapter, u8 variable, u8 *val) u8 rtl8821c_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval) { PHAL_DATA_TYPE hal; - u8 bResult; + u8 bResult, val8; hal = GET_HAL_DATA(adapter); @@ -2662,7 +2539,6 @@ u8 rtl8821c_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval case HAL_DEF_RA_SGI: case HAL_DEF_PT_PWR_STATUS: case HW_VAR_MAX_RX_AMPDU_FACTOR: - case HW_DEF_RA_INFO_DUMP: case HAL_DEF_DBG_DUMP_TXPKT: case HAL_DEF_TX_PAGE_BOUNDARY: case HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN: @@ -2670,13 +2546,44 @@ u8 rtl8821c_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR: case HAL_DEF_PCI_AMD_L1_SUPPORT: case HAL_DEF_PCI_ASPM_OSC: - case HAL_DEF_MACID_SLEEP: - case HAL_DEF_DBG_DIS_PWT: case HAL_DEF_EFUSE_USAGE: case HAL_DEF_EFUSE_BYTES: case HW_VAR_BEST_AMPDU_DENSITY: break; */ + case HW_VAR_FREECNT: + + val8 = *((u8*)pval); + + if (val8 == 0) { + /* disable free run counter set 0x577[3]=0 */ + rtw_write8(adapter, REG_MISC_CTRL, + rtw_read8(adapter, REG_MISC_CTRL)&(~BIT_EN_FREECNT)); + + /* reset FREE_RUN_COUNTER set 0x553[5]=1 */ + val8 = rtw_read8(adapter, REG_DUAL_TSF_RST); + val8 |= BIT_FREECNT_RST; + rtw_write8(adapter, REG_DUAL_TSF_RST, val8); + + } else if (val8 == 1){ + + /* enable free run counter */ + + /* disable first set 0x577[3]=0 */ + rtw_write8(adapter, REG_MISC_CTRL, + rtw_read8(adapter, REG_MISC_CTRL)&(~BIT_EN_FREECNT)); + + /* reset FREE_RUN_COUNTER set 0x553[5]=1 */ + val8 = rtw_read8(adapter, REG_DUAL_TSF_RST); + val8 |= BIT_FREECNT_RST; + rtw_write8(adapter, REG_DUAL_TSF_RST, val8); + + /* enable free run counter 0x577[3]=1 */ + rtw_write8(adapter, REG_MISC_CTRL, + rtw_read8(adapter, REG_MISC_CTRL)|BIT_EN_FREECNT); + } + break; + default: bResult = SetHalDefVar(adapter, variable, pval); break; @@ -2685,6 +2592,28 @@ u8 rtl8821c_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval return bResult; } +void rtl8821c_ra_info_dump(_adapter *padapter, void *sel) +{ + u8 mac_id; + struct sta_info *psta; + u32 rate_mask1, rate_mask2; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) { + if (rtw_macid_is_used(macid_ctl, mac_id) && !rtw_macid_is_bmc(macid_ctl, mac_id)) { + psta = macid_ctl->sta[mac_id]; + if (!psta) + continue; + + dump_sta_info(sel, psta); + rate_mask1 = macid_ctl->rate_bmp0[mac_id]; + rate_mask2 = macid_ctl->rate_bmp1[mac_id]; + _RTW_PRINT_SEL(sel, "rate_mask2:0x%08x, rate_mask1:0x%08x\n", rate_mask2, rate_mask1); + } + } +} + /* * Description: * Query setting of specified variable. @@ -2694,6 +2623,7 @@ u8 rtl8821c_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval PHAL_DATA_TYPE hal; u8 bResult; u8 val8 = 0; + u32 val32 = 0; hal = GET_HAL_DATA(adapter); @@ -2715,12 +2645,13 @@ u8 rtl8821c_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval *((u32 *)pval) = MAX_RECVBUF_SZ; break; case HAL_DEF_RX_PACKET_OFFSET: - rtw_halmac_get_drv_info_sz(adapter_to_dvobj(adapter), &val8); - *((u32 *)pval) = HALMAC_RX_DESC_SIZE_8821C + val8; + rtw_halmac_get_rx_desc_size(adapter_to_dvobj(adapter), &val32); + rtw_halmac_get_rx_drv_info_sz(adapter_to_dvobj(adapter), &val8); + *((u32 *)pval) = val32 + val8; break; /* case HAL_DEF_DRVINFO_SZ: - rtw_halmac_get_drv_info_sz(adapter_to_dvobj(adapter), &val8); + rtw_halmac_get_rx_drv_info_sz(adapter_to_dvobj(adapter), &val8); *((u32 *)pval) = val8; break; case HAL_DEF_RX_DMA_SZ_WOW: @@ -2754,80 +2685,54 @@ u8 rtl8821c_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval /* support Explicit TxBF for HT/VHT */ case HAL_DEF_EXPLICIT_BEAMFORMER: +#ifdef CONFIG_BEAMFORMING + *(u8 *)pval = ((hal->phy_spec.txbf_cap >> 20)& 0xF) ? _TRUE : _FALSE; +#else *(u8 *)pval = _FALSE; +#endif break; case HAL_DEF_EXPLICIT_BEAMFORMEE: #ifdef CONFIG_BEAMFORMING - *(u8 *)pval = _TRUE; + *(u8 *)pval = ((hal->phy_spec.txbf_cap >> 16) & 0xF) ? _TRUE : _FALSE; #else *(u8 *)pval = _FALSE; #endif break; - /* - case HAL_DEF_BEAMFORMER_CAP: - case HAL_DEF_BEAMFORMEE_CAP: - break; - */ - case HW_DEF_RA_INFO_DUMP: -#if 0 - { - u8 mac_id = *(u8 *)pval; - u32 cmd; - u32 ra_info1, ra_info2; - u32 rate_mask1, rate_mask2; - u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate; - - RTW_INFO("============ RA status check Mac_id:%d ===================\n", mac_id); - - cmd = 0x40000100 | mac_id; - rtw_write32(adapter, REG_HMEBOX_DBG_2_8723B, cmd); - rtw_msleep_os(10); - ra_info1 = rtw_read32(adapter, 0x2F0); - curr_tx_rate = ra_info1 & 0x7F; - curr_tx_sgi = (ra_info1 >> 7) & 0x01; - RTW_INFO("[ ra_info1:0x%08x ] =>cur_tx_rate=%s, cur_sgi:%d, PWRSTS=0x%02x\n", - ra_info1, - HDATA_RATE(curr_tx_rate), - curr_tx_sgi, - (ra_info1 >> 8) & 0x07); - - cmd = 0x40000400 | mac_id; - rtw_write32(adapter, REG_HMEBOX_DBG_2_8723B, cmd); - rtw_msleep_os(10); - ra_info1 = rtw_read32(adapter, 0x2F0); - ra_info2 = rtw_read32(adapter, 0x2F4); - rate_mask1 = rtw_read32(adapter, 0x2F8); - rate_mask2 = rtw_read32(adapter, 0x2FC); - hight_rate = ra_info2 & 0xFF; - lowest_rate = (ra_info2 >> 8) & 0xFF; - - RTW_INFO("[ ra_info1:0x%08x ] =>RSSI=%d, BW_setting=0x%02x, DISRA=0x%02x, VHT_EN=0x%02x\n", - ra_info1, - ra_info1 & 0xFF, - (ra_info1 >> 8) & 0xFF, - (ra_info1 >> 16) & 0xFF, - (ra_info1 >> 24) & 0xFF); - - RTW_INFO("[ ra_info2:0x%08x ] =>hight_rate=%s, lowest_rate=%s, SGI=0x%02x, RateID=%d\n", - ra_info2, - HDATA_RATE(hight_rate), - HDATA_RATE(lowest_rate), - (ra_info2 >> 16) & 0xFF, - (ra_info2 >> 24) & 0xFF); - - RTW_INFO("rate_mask2=0x%08x, rate_mask1=0x%08x\n", rate_mask2, rate_mask1); - } + + case HAL_DEF_VHT_MU_BEAMFORMER: +#ifdef CONFIG_BEAMFORMING + *(u8 *)pval = ((hal->phy_spec.txbf_cap >> 28)& 0xF) ? _TRUE : _FALSE; +#else + *(u8 *)pval = _FALSE; +#endif + break; + + case HAL_DEF_VHT_MU_BEAMFORMEE: +#ifdef CONFIG_BEAMFORMING + *(u8 *)pval = ((hal->phy_spec.txbf_cap >> 24)& 0xF) ? _TRUE : _FALSE; +#else + *(u8 *)pval = _FALSE; #endif break; + + case HAL_DEF_BEAMFORMER_CAP: + *(u8 *)pval = (hal->phy_spec.txbf_param >> 24)& 0xFF ; + break; + + case HAL_DEF_BEAMFORMEE_CAP: + *(u8 *)pval = (hal->phy_spec.txbf_param >> 16) & 0xFF ; + break; + + case HW_DEF_RA_INFO_DUMP: + rtl8821c_ra_info_dump(adapter, pval); + break; /* case HAL_DEF_DBG_DUMP_TXPKT: + case HAL_DEF_TX_PAGE_SIZE: break; */ - case HAL_DEF_TX_PAGE_SIZE: - *(u32 *)pval = HALMAC_TX_PAGE_SIZE_8821C; - break; case HAL_DEF_TX_PAGE_BOUNDARY: rtw_halmac_get_rsvd_drv_pg_bndy(adapter_to_dvobj(adapter), (u16 *)pval); break; @@ -2836,13 +2741,6 @@ u8 rtl8821c_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR: case HAL_DEF_PCI_AMD_L1_SUPPORT: case HAL_DEF_PCI_ASPM_OSC: - break; - */ - case HAL_DEF_MACID_SLEEP: - *(u8 *)pval = _TRUE; /* support macid sleep */ - break; - /* - case HAL_DEF_DBG_DIS_PWT: case HAL_DEF_EFUSE_USAGE: case HAL_DEF_EFUSE_BYTES: break; @@ -2881,6 +2779,13 @@ void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc) } #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc) +{ + SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1); + SET_TX_DESC_DATARATE_8821C(ptxdesc, MRateToHwRate(pattrib->rate)); + SET_TX_DESC_DISDATAFB_8821C(ptxdesc, 1); +} + void rtl8821c_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc) { if ((pattrib->encrypt > 0) && !pattrib->bswenc) { @@ -3015,8 +2920,8 @@ void rtl8821c_fill_txdesc_phy(PADAPTER adapter, struct pkt_attrib *pattrib, u8 * void rtl8821c_cal_txdesc_chksum(PADAPTER adapter, u8 *ptxdesc) { - PHALMAC_ADAPTER halmac; - PHALMAC_API api; + struct halmac_adapter *halmac; + struct halmac_api *api; halmac = adapter_to_halmac(adapter); @@ -3029,12 +2934,14 @@ void rtl8821c_cal_txdesc_chksum(PADAPTER adapter, u8 *ptxdesc) #ifdef CONFIG_MP_INCLUDED void rtl8821c_prepare_mp_txdesc(PADAPTER adapter, struct mp_priv *pmp_priv) { + u32 desc_size = 0; u8 *desc; struct pkt_attrib *attrib; u32 pkt_size; s32 bmcast; u8 data_rate, pwr_status, offset; + rtw_halmac_get_tx_desc_size(adapter_to_dvobj(adapter), &desc_size); desc = pmp_priv->tx.desc; attrib = &pmp_priv->tx.attrib; @@ -3044,7 +2951,7 @@ void rtl8821c_prepare_mp_txdesc(PADAPTER adapter, struct mp_priv *pmp_priv) SET_TX_DESC_LS_8821C(desc, 1); SET_TX_DESC_TXPKTSIZE_8821C(desc, pkt_size); - offset = HALMAC_TX_DESC_SIZE_8821C; + offset = desc_size; SET_TX_DESC_OFFSET_8821C(desc, offset); #if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) @@ -3091,10 +2998,11 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct pkt_attrib *pattrib = &pxmitframe->attrib; s32 bmcst = IS_MCAST(pattrib->ra); + u32 desc_size = 0; u8 offset, pkt_offset = 0; - #define RA_SW_DEFINE_CONT 0x01 u8 drv_fixed_reate = _FALSE; + u8 hw_port = rtw_hal_get_port(adapter); #if 0 #ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX @@ -3108,13 +3016,15 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) } #endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX*/ #endif - _rtw_memset(pbuf, 0, HALMAC_TX_DESC_SIZE_8821C); + rtw_halmac_get_tx_desc_size(adapter_to_dvobj(adapter), &desc_size); + + _rtw_memset(pbuf, 0, desc_size); /*SET_TX_DESC_LS_8821C(pbuf, 1);*/ /*for USB only*/ SET_TX_DESC_TXPKTSIZE_8821C(pbuf, pattrib->last_txcmdsz); - offset = HALMAC_TX_DESC_SIZE_8821C + OFFSET_SZ; + offset = desc_size + OFFSET_SZ; #ifdef CONFIG_TX_EARLY_MODE if (pxmitframe->frame_tag == DATA_FRAMETAG) @@ -3127,8 +3037,6 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) if (bmcst) SET_TX_DESC_BMC_8821C(pbuf, 1); - SET_TX_DESC_MULTIPLE_PORT_8821C(pbuf, adapter->hw_port); - #if 0 #ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX if (adapter->registrypriv.mp_mode == 0) { @@ -3188,11 +3096,13 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) rtl8821c_fill_txdesc_vcs(adapter, pattrib, pbuf); +#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR + rtw_phydm_set_dyntxpwr(adapter, pbuf, pattrib->mac_id); +#endif if ((pattrib->ether_type != 0x888e) && (pattrib->ether_type != 0x0806) && (pattrib->ether_type != 0x88B4) && - (pattrib->dhcp_pkt != 1) && - (!bmcst) + (pattrib->dhcp_pkt != 1) #ifdef CONFIG_AUTO_AP_MODE && (pattrib->pctrl != _TRUE) #endif @@ -3216,20 +3126,16 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) else SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(pbuf, 0); - if (phal_data->fw_ractrl == _FALSE) { - SET_TX_DESC_USE_RATE_8821C(pbuf, 1); + if (bmcst) { drv_fixed_reate = _TRUE; - - if (phal_data->INIDATA_RATE[pattrib->mac_id] & BIT(7)) - SET_TX_DESC_DATA_SHORT_8821C(pbuf, 1); - - SET_TX_DESC_DATARATE_8821C(pbuf, phal_data->INIDATA_RATE[pattrib->mac_id] & 0x7F); + fill_txdesc_bmc_tx_rate(pattrib, pbuf); } /* modify data rate by iwpriv*/ if (adapter->fix_rate != 0xFF) { - SET_TX_DESC_USE_RATE_8821C(pbuf, 1); drv_fixed_reate = _TRUE; + SET_TX_DESC_USE_RATE_8821C(pbuf, 1); + if (adapter->fix_rate & BIT(7)) SET_TX_DESC_DATA_SHORT_8821C(pbuf, 1); SET_TX_DESC_DATARATE_8821C(pbuf, adapter->fix_rate & 0x7F); @@ -3245,6 +3151,11 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) #ifdef CONFIG_CMCC_TEST SET_TX_DESC_DATA_SHORT_8821C(pbuf, 1); /* use cck short premble */ #endif + +#ifdef CONFIG_WMMPS_STA + if (pattrib->trigger_frame) + SET_TX_DESC_TRI_FRAME_8821C (pbuf, 1); +#endif /* CONFIG_WMMPS_STA */ } else { /* @@ -3252,9 +3163,9 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) * Use the 1M data rate to send the EAP/ARP packet. * This will maybe make the handshake smooth. */ - SET_TX_DESC_USE_RATE_8821C(pbuf, 1); - drv_fixed_reate = _TRUE; SET_TX_DESC_BK_8821C(pbuf, 1); + drv_fixed_reate = _TRUE; + SET_TX_DESC_USE_RATE_8821C(pbuf, 1); /* HW will ignore this setting if the transmission rate is legacy OFDM.*/ if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT) @@ -3262,11 +3173,8 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) SET_TX_DESC_DATARATE_8821C(pbuf, MRateToHwRate(pmlmeext->tx_rate)); - if (bmcst) - SET_TX_DESC_DISDATAFB_8821C(pbuf, 1); - - /*RTW_INFO(FUNC_ADPT_FMT ": SP Packet(0x%04X) rate=0x%x\n", - FUNC_ADPT_ARG(adapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate));*/ + RTW_INFO(FUNC_ADPT_FMT ": SP Packet(0x%04X) rate=0x%x\n", + FUNC_ADPT_ARG(adapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate)); } #ifdef CONFIG_TDLS #ifdef CONFIG_XMIT_ACK @@ -3281,7 +3189,7 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) #endif } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) { - + SET_TX_DESC_MBSSID_8821C(pbuf, pattrib->mbssid & 0xF); SET_TX_DESC_USE_RATE_8821C(pbuf, 1); drv_fixed_reate = _TRUE; @@ -3294,8 +3202,8 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) SET_TX_DESC_NAVUSEHDR_8821C(pbuf, 1); SET_TX_DESC_DATA_BW_8821C(pbuf, rtl8821c_bw_mapping(adapter, pattrib)); - SET_TX_DESC_DATA_SC_8821C(pbuf, rtl8821c_sc_mapping(adapter, pattrib)); - /*SET_TX_DESC_RTS_SC_8821C(pbuf, rtl8821c_sc_mapping(adapter,pattrib)); ??????*/ + /*SET_TX_DESC_DATA_SC_8821C(pbuf, rtl8821c_sc_mapping(adapter, pattrib));*/ + SET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(pbuf, rtl8821c_sc_mapping(adapter,pattrib)); SET_TX_DESC_RTY_LMT_EN_8821C(pbuf, 1); SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(pbuf, 5); @@ -3346,13 +3254,18 @@ static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) if (adapter->power_offset != 0) SET_TX_DESC_TXPWR_OFSET_8821C(pbuf, adapter->power_offset); +#ifdef CONFIG_ANTENNA_DIVERSITY + if (!bmcst && pattrib->psta) + odm_set_tx_ant_by_tx_info(adapter_to_phydm(adapter), pbuf, pattrib->psta->cmn.mac_id); +#endif #ifdef CONFIG_BEAMFORMING SET_TX_DESC_G_ID_8821C(pbuf, pattrib->txbf_g_id); SET_TX_DESC_P_AID_8821C(pbuf, pattrib->txbf_p_aid); #endif - SET_TX_DESC_PORT_ID_8821C(pbuf, get_hw_port(adapter)); + SET_TX_DESC_PORT_ID_8821C(pbuf, hw_port); + SET_TX_DESC_MULTIPLE_PORT_8821C(pbuf, hw_port); } void rtl8821c_dbg_dump_tx_desc(PADAPTER adapter, int frame_tag, u8 *ptxdesc) @@ -3403,11 +3316,6 @@ void rtl8821c_dbg_dump_tx_desc(PADAPTER adapter, int frame_tag, u8 *ptxdesc) void rtl8821c_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) { fill_default_txdesc(pxmitframe, pbuf); - -#ifdef CONFIG_ANTENNA_DIVERSITY - odm_set_tx_ant_by_tx_info(&GET_HAL_DATA(pxmitframe->padapter)->odmpriv, pbuf, pxmitframe->attrib.mac_id); -#endif /* CONFIG_ANTENNA_DIVERSITY */ - rtl8821c_cal_txdesc_chksum(pxmitframe->padapter, pbuf); rtl8821c_dbg_dump_tx_desc(pxmitframe->padapter, pxmitframe->frame_tag, pbuf); } @@ -3423,13 +3331,18 @@ static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame) { struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct xmit_priv *pxmitpriv = &adapter->xmitpriv; + u32 desc_size = 0; + u8 hw_port = rtw_hal_get_port(adapter); + + rtw_halmac_get_tx_desc_size(adapter_to_dvobj(adapter), &desc_size); /* Clear all status */ - _rtw_memset(pDesc, 0, HALMAC_TX_DESC_SIZE_8821C); + _rtw_memset(pDesc, 0, desc_size); SET_TX_DESC_LS_8821C(pDesc, 1); - SET_TX_DESC_OFFSET_8821C(pDesc, HALMAC_TX_DESC_SIZE_8821C); + SET_TX_DESC_OFFSET_8821C(pDesc, desc_size); SET_TX_DESC_TXPKTSIZE_8821C(pDesc, BufferLen); SET_TX_DESC_QSEL_8821C(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */ @@ -3445,7 +3358,7 @@ static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen, else { SET_TX_DESC_DISQSELSEQ_8821C(pDesc, 1); SET_TX_DESC_EN_HWSEQ_8821C(pDesc, 1); - SET_TX_DESC_HW_SSN_SEL_8821C(pDesc, 0);/*pattrib->hw_ssn_sel*/ + SET_TX_DESC_HW_SSN_SEL_8821C(pDesc, pxmitpriv->hw_ssn_seq_no);/*pattrib->hw_ssn_sel*/ SET_TX_DESC_EN_HWEXSEQ_8821C(pDesc, 0); } @@ -3455,6 +3368,19 @@ static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen, SET_TX_DESC_USE_RATE_8821C(pDesc, 1); SET_TX_DESC_DATARATE_8821C(pDesc, MRateToHwRate(pmlmeext->tx_rate)); +#ifdef CONFIG_MCC_MODE + /* config Null data retry number */ + if (IsPsPoll == _FALSE && IsBTQosNull == _FALSE && bDataFrame == _FALSE) { + if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) { + u8 rty_num = adapter->mcc_adapterpriv.null_rty_num; + if (rty_num != 0) { + SET_TX_DESC_RTY_LMT_EN_8821C(pDesc, 1); + SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(pDesc, rty_num); + } + } + } +#endif + /* * Encrypt the data frame if under security mode excepct null data. */ @@ -3482,8 +3408,8 @@ static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen, break; } } - SET_TX_DESC_PORT_ID_8821C(pDesc, get_hw_port(adapter)); - SET_TX_DESC_MULTIPLE_PORT_8821C(pDesc, get_hw_port(adapter)); + SET_TX_DESC_PORT_ID_8821C(pDesc, hw_port); + SET_TX_DESC_MULTIPLE_PORT_8821C(pDesc, hw_port); #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) /* @@ -3496,36 +3422,37 @@ static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen, void rtl8821c_rxdesc2attribute(struct rx_pkt_attrib *pattrib, u8 *desc) { + /* initial value */ _rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib)); pattrib->pkt_len = (u16)GET_RX_DESC_PKT_LEN_8821C(desc); - pattrib->crc_err = (u8)GET_RX_DESC_CRC32_8821C(desc); - pattrib->icv_err = (u8)GET_RX_DESC_ICV_ERR_8821C(desc); - - pattrib->drvinfo_sz = (u8)GET_RX_DESC_DRV_INFO_SIZE_8821C(desc) << 3; - pattrib->encrypt = (u8)GET_RX_DESC_SECURITY_8821C(desc); - pattrib->qos = (u8)GET_RX_DESC_QOS_8821C(desc); - pattrib->shift_sz = (u8)GET_RX_DESC_SHIFT_8821C(desc); - pattrib->physt = (u8)GET_RX_DESC_PHYST_8821C(desc); - pattrib->bdecrypted = (u8)GET_RX_DESC_SWDEC_8821C(desc) ? 0 : 1; - - pattrib->priority = (u8)GET_RX_DESC_TID_8821C(desc); - pattrib->amsdu = (u8)GET_RX_DESC_AMSDU_8821C(desc); - pattrib->mdata = (u8)GET_RX_DESC_MD_8821C(desc); - pattrib->mfrag = (u8)GET_RX_DESC_MF_8821C(desc); - - pattrib->seq_num = (u16)GET_RX_DESC_SEQ_8821C(desc); - pattrib->frag_num = (u8)GET_RX_DESC_FRAG_8821C(desc); - pattrib->ppdu_cnt = (u8)GET_RX_DESC_PPDU_CNT_8821C(desc); - - if (GET_RX_DESC_C2H_8821C(desc)) - pattrib->pkt_rpt_type = C2H_PACKET; - else - pattrib->pkt_rpt_type = NORMAL_RX; + pattrib->pkt_rpt_type = (GET_RX_DESC_C2H_8821C(desc)) ? C2H_PACKET : NORMAL_RX; + + if (pattrib->pkt_rpt_type == NORMAL_RX) { + /* Get from RX DESC */ + pattrib->crc_err = (u8)GET_RX_DESC_CRC32_8821C(desc); + pattrib->icv_err = (u8)GET_RX_DESC_ICV_ERR_8821C(desc); + pattrib->drvinfo_sz = (u8)GET_RX_DESC_DRV_INFO_SIZE_8821C(desc) << 3; + pattrib->encrypt = (u8)GET_RX_DESC_SECURITY_8821C(desc); + pattrib->qos = (u8)GET_RX_DESC_QOS_8821C(desc); + pattrib->shift_sz = (u8)GET_RX_DESC_SHIFT_8821C(desc); + pattrib->physt = (u8)GET_RX_DESC_PHYST_8821C(desc); + pattrib->bdecrypted = (u8)GET_RX_DESC_SWDEC_8821C(desc) ? 0 : 1; - pattrib->data_rate = (u8)GET_RX_DESC_RX_RATE_8821C(desc); + pattrib->priority = (u8)GET_RX_DESC_TID_8821C(desc); + pattrib->amsdu = (u8)GET_RX_DESC_AMSDU_8821C(desc); + pattrib->mdata = (u8)GET_RX_DESC_MD_8821C(desc); + pattrib->mfrag = (u8)GET_RX_DESC_MF_8821C(desc); + pattrib->seq_num = (u16)GET_RX_DESC_SEQ_8821C(desc); + pattrib->frag_num = (u8)GET_RX_DESC_FRAG_8821C(desc); + pattrib->ppdu_cnt = (u8)GET_RX_DESC_PPDU_CNT_8821C(desc); + pattrib->free_cnt = (u32)GET_RX_DESC_TSFL_8821C(desc); + + pattrib->bw = CHANNEL_WIDTH_MAX; + pattrib->data_rate = (u8)GET_RX_DESC_RX_RATE_8821C(desc); + } } void rtl8821c_query_rx_desc(union recv_frame *precvframe, u8 *pdesc) @@ -3537,7 +3464,13 @@ static void InitBeaconParameters(PADAPTER adapter) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - rtw_write16(adapter, REG_TBTT_PROHIBIT_8821C, 0x6404); /* ms */ + /* TBTT setup time */ + rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C, TBTT_PROHIBIT_SETUP_TIME); + + /* TBTT hold time: 0x540[19:8] */ + rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF); + rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 2, + (rtw_read8(adapter, REG_TBTT_PROHIBIT_8821C + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8)); rtw_write8(adapter, REG_DRVERLYINT_8821C, DRIVER_EARLY_INT_TIME_8821C); /* 5ms */ rtw_write8(adapter, REG_BCNDMATIM_8821C, BCN_DMA_ATIME_INT_TIME_8821C); /* 2ms */ @@ -3546,44 +3479,12 @@ static void InitBeaconParameters(PADAPTER adapter) * Suggested by designer timchen. Change beacon AIFS to the largest number * beacause test chip does not contension before sending beacon. */ - rtw_write16(adapter, REG_BCNTCFG_8821C, 0x660F); - - hal->RegBcnCtrlVal = rtw_read8(adapter, REG_BCN_CTRL_8821C); - hal->RegTxPause = rtw_read8(adapter, REG_TXPAUSE_8821C); - hal->RegFwHwTxQCtrl = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2); - hal->RegReg542 = rtw_read8(adapter, REG_TBTT_PROHIBIT_8821C + 2); - hal->RegCR_1 = rtw_read8(adapter, REG_CR_8821C + 1); -} - -void rtl8821c_resume_tx_beacon(PADAPTER adapter) -{ - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - - - hal->RegFwHwTxQCtrl |= (BIT_EN_BCNQ_DL_8821C >> 16); - rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2, hal->RegFwHwTxQCtrl); - - rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 1, 0xff); - hal->RegReg542 |= BIT(0); - rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 2, hal->RegReg542); -} - -void rtl8821c_stop_tx_beacon(PADAPTER adapter) -{ - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - - - hal->RegFwHwTxQCtrl &= ~(BIT_EN_BCNQ_DL_8821C >> 16); - rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2, hal->RegFwHwTxQCtrl); - - rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 1, 0x64); - hal->RegReg542 &= ~BIT(0); - rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 2, hal->RegReg542); + rtw_write16(adapter, REG_BCNTCFG_8821C, 0x4413); } static void beacon_function_enable(PADAPTER adapter, u8 Enable, u8 Linked) { - hw_bcn_ctrl_add(adapter, BIT_DIS_TSF_UDT_8821C | BIT_EN_BCN_FUNCTION_8821C); + hw_bcn_ctrl_add(adapter, get_hw_port(adapter), BIT_DIS_TSF_UDT_8821C | BIT_EN_BCN_FUNCTION_8821C); } static void set_beacon_related_registers(PADAPTER adapter) @@ -3593,7 +3494,7 @@ static void set_beacon_related_registers(PADAPTER adapter) /* reset TSF, enable update TSF, correcting TSF On Beacon */ #if 0 - /* * REG_BCN_INTERVAL */ + /* * REG_MBSSID_BCN_SPACE */ /* * REG_BCNDMATIM */ /* * REG_ATIMWND */ /* * REG_TBTT_PROHIBIT */ @@ -3608,7 +3509,7 @@ static void set_beacon_related_registers(PADAPTER adapter) rtw_write16(adapter, REG_ATIMWND_8821C, 2); /* Beacon interval (in unit of TU). */ - hw_var_set_bcn_interval(adapter, pmlmeinfo->bcn_interval); + rtw_hal_set_hwreg(adapter, HW_VAR_BEACON_INTERVAL, (u8 *)&pmlmeinfo->bcn_interval); InitBeaconParameters(adapter); @@ -3622,7 +3523,7 @@ static void set_beacon_related_registers(PADAPTER adapter) beacon_function_enable(adapter, _TRUE, _TRUE); - rtl8821c_resume_tx_beacon(adapter); + ResumeTxBeacon(adapter); } void rtl8821c_set_hal_ops(PADAPTER adapter) @@ -3684,10 +3585,6 @@ void rtl8821c_set_hal_ops(PADAPTER adapter) */ /*** DM section ***/ - /* - ops->InitSwLeds = NULL; - ops->DeInitSwLeds = NULL; - */ ops_func->set_chnl_bw_handler = rtl8821c_set_channel_bw; ops_func->set_tx_power_level_handler = rtl8821c_set_tx_power_level; @@ -3697,14 +3594,10 @@ void rtl8821c_set_hal_ops(PADAPTER adapter) ops_func->get_tx_power_index_handler = rtl8821c_get_tx_power_index; ops_func->hal_dm_watchdog = rtl8821c_phy_haldm_watchdog; -#ifdef CONFIG_LPS_LCLK_WD_TIMER - ops_func->hal_dm_watchdog_in_lps = rtl8821c_phy_haldm_watchdog_in_lps; -#endif ops_func->GetHalODMVarHandler = GetHalODMVar; ops_func->SetHalODMVarHandler = SetHalODMVar; - ops_func->update_ra_mask_handler = update_ra_mask_8821c; ops_func->SetBeaconRelatedRegistersHandler = set_beacon_related_registers; #ifdef CONFIG_ANTENNA_DIVERSITY @@ -3721,6 +3614,7 @@ void rtl8821c_set_hal_ops(PADAPTER adapter) ops_func->write_bbreg = rtl8821c_write_bb_reg; ops_func->read_rfreg = rtl8821c_read_rf_reg; ops_func->write_rfreg = rtl8821c_write_rf_reg; + ops_func->read_wmmedca_reg = rtl8821c_read_wmmedca_reg; #ifdef CONFIG_HOSTAPD_MLME /* @@ -3768,17 +3662,15 @@ void rtl8821c_set_hal_ops(PADAPTER adapter) ops->clear_interrupt = NULL; */ #endif - - ops_func->hal_get_tx_buff_rsvd_page_num = get_txbuffer_rsvdpagenum; - + /* + ops_func->hal_get_tx_buff_rsvd_page_num = NULL; + */ #ifdef CONFIG_GPIO_API /* ops->update_hisr_hsisr_ind = NULL; */ #endif - ops_func->fw_correct_bcn = rtl8821c_fw_update_beacon_cmd; - /* HALMAC related functions */ ops_func->init_mac_register = rtl8821c_init_phy_parameter_mac; ops_func->init_phy = rtl8821c_phy_init; diff --git a/hal/rtl8821c/rtl8821c_phy.c b/hal/rtl8821c/rtl8821c_phy.c index c94afb1..4f0222c 100644 --- a/hal/rtl8821c/rtl8821c_phy.c +++ b/hal/rtl8821c/rtl8821c_phy.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RTL8821C_PHY_C_ #include /* HAL_DATA_TYPE */ @@ -35,28 +30,28 @@ static void bb_rf_register_definition(PADAPTER adapter) /* RF Interface Sowrtware Control */ - hal->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; - hal->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; + hal->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; + hal->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* RF Interface Output (and Enable) */ - hal->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; - hal->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; + hal->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; + hal->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* RF Interface (Output and) Enable */ - hal->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; - hal->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; + hal->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; + hal->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; - hal->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rA_LSSIWrite_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rB_LSSIWrite_Jaguar; + hal->PHYRegDef[RF_PATH_A].rf3wireOffset = rA_LSSIWrite_Jaguar; + hal->PHYRegDef[RF_PATH_B].rf3wireOffset = rB_LSSIWrite_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rHSSIRead_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rHSSIRead_Jaguar; + hal->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rHSSIRead_Jaguar; + hal->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rHSSIRead_Jaguar; /* Tranceiver Readback LSSI/HSPI mode */ - hal->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rA_SIRead_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rB_SIRead_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = rA_PIRead_Jaguar; - hal->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = rB_PIRead_Jaguar; + hal->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rA_SIRead_Jaguar; + hal->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rB_SIRead_Jaguar; + hal->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = rA_PIRead_Jaguar; + hal->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = rB_PIRead_Jaguar; } static void init_bb_rf(PADAPTER adapter) @@ -142,7 +137,7 @@ static u8 _init_phy_parameter_bb(PADAPTER Adapter) goto exit; } -#if 0 /* def CONFIG_MP_INCLUDED */ /* No parameter with MP using currently by BB@Stanley.*/ +#ifdef CONFIG_MP_INCLUDED if (Adapter->registrypriv.mp_mode == 1) { /* * 1.1 Read PHY_REG_MP.TXT BB INIT!! @@ -201,14 +196,14 @@ static u8 init_bb_reg(PADAPTER adapter) hal_set_crystal_cap(adapter, hal->crystal_cap); - phy_set_bb_reg(adapter, rCCK0_FalseAlarmReport + 2, BIT2 | BIT6, 0); + phy_set_bb_reg(adapter, rCCK0_FalseAlarmReport, BIT18 | BIT22, 0); return ret; } static u8 _init_phy_parameter_rf(PADAPTER adapter) { u32 val32 = 0; - u8 eRFPath; + enum rf_path eRFPath; PBB_REGISTER_DEFINITION_T pPhyReg; PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); enum hal_status status; @@ -219,7 +214,7 @@ static u8 _init_phy_parameter_rf(PADAPTER adapter) /* * Initialize RF */ - for (eRFPath = 0; eRFPath < hal->NumTotalRFPath; eRFPath++) { + for (eRFPath = RF_PATH_A; eRFPath < hal->NumTotalRFPath; eRFPath++) { pPhyReg = &hal->PHYRegDef[eRFPath]; /* Initialize RF from configuration file */ @@ -231,7 +226,7 @@ static u8 _init_phy_parameter_rf(PADAPTER adapter) #endif { ret = _FALSE; - status = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, (enum odm_rf_radio_path_e)eRFPath); + status = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, eRFPath); if (HAL_STATUS_SUCCESS == status) ret = _TRUE; } @@ -243,14 +238,13 @@ static u8 _init_phy_parameter_rf(PADAPTER adapter) #endif { ret = _FALSE; - status = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, (enum odm_rf_radio_path_e)eRFPath); + status = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, eRFPath); if (HAL_STATUS_SUCCESS == status) ret = _TRUE; } break; - case RF_PATH_C: - break; - case RF_PATH_D: + default: + RTW_INFO("Unknown RF path!! %d\r\n", eRFPath); break; } @@ -289,11 +283,8 @@ static u8 init_rf_reg(PADAPTER adapter) } u8 rtl8821c_phy_init(PADAPTER adapter) { - PHAL_DATA_TYPE hal; - struct PHY_DM_STRUCT *phydm; - - hal = GET_HAL_DATA(adapter); - phydm = &hal->odmpriv; + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct dm_struct *phydm = &hal->odmpriv; bb_rf_register_definition(adapter); @@ -372,15 +363,11 @@ void rtl8821c_write_bb_reg(PADAPTER adapter, u32 addr, u32 mask, u32 val) rtw_write32(adapter, addr, val); } -u32 rtl8821c_read_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask) +u32 rtl8821c_read_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask) { - PHAL_DATA_TYPE hal; - struct PHY_DM_STRUCT *phydm; + struct dm_struct *phydm = adapter_to_phydm(adapter); u32 val = 0; - hal = GET_HAL_DATA(adapter); - phydm = &hal->odmpriv; - val = config_phydm_read_rf_reg_8821c(phydm, path, addr, mask); if (!config_phydm_read_rf_check_8821c(val)) RTW_INFO(FUNC_ADPT_FMT ": read RF reg path=%d addr=0x%x mask=0x%x FAIL!\n", @@ -388,16 +375,11 @@ u32 rtl8821c_read_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask) return val; } -void rtl8821c_write_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask, u32 val) +void rtl8821c_write_rf_reg(PADAPTER adapter, enum rf_path path, u32 addr, u32 mask, u32 val) { - PHAL_DATA_TYPE hal; - struct PHY_DM_STRUCT *phydm; + struct dm_struct *phydm = adapter_to_phydm(adapter); u8 ret; - - hal = GET_HAL_DATA(adapter); - phydm = &hal->odmpriv; - ret = config_phydm_write_rf_reg_8821c(phydm, path, addr, mask, val); if (_FALSE == ret) RTW_INFO(FUNC_ADPT_FMT ": write RF reg path=%d addr=0x%x mask=0x%x val=0x%x FAIL!\n", @@ -407,21 +389,25 @@ void rtl8821c_write_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask, u32 va void rtl8821c_set_tx_power_level(PADAPTER adapter, u8 channel) { + u8 path = RF_PATH_A; + struct dm_struct *phydm = adapter_to_phydm(adapter); PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - u8 path = ODM_RF_PATH_A; - struct PHY_DM_STRUCT *phydm = &hal->odmpriv; - struct _FAST_ANTENNA_TRAINNING_ *pDM_FatTable = &phydm->dm_fat_table; + u8 under_survey_ch = phy_check_under_survey_ch(adapter); + u8 under_24g = (hal->current_band_type == BAND_ON_2_4G); /*((hal->RFEType == 2) || (hal->RFEType == 4) || (hal->RFEType == 7))*/ if ((channel <= 14) && (SWITCH_TO_BTG == query_phydm_default_rf_set_8821c(phydm))) - path = ODM_RF_PATH_B; + path = RF_PATH_B; /*if (adapter->registrypriv.mp_mode == 1)*/ + if (under_24g) + phy_set_tx_power_index_by_rate_section(adapter, path, channel, CCK); - phy_set_tx_power_index_by_rate_section(adapter, path, channel, CCK); phy_set_tx_power_index_by_rate_section(adapter, path, channel, OFDM); - phy_set_tx_power_index_by_rate_section(adapter, path, channel, HT_MCS0_MCS7); - phy_set_tx_power_index_by_rate_section(adapter, path, channel, VHT_1SSMCS0_1SSMCS9); + if (!under_survey_ch) { + phy_set_tx_power_index_by_rate_section(adapter, path, channel, HT_MCS0_MCS7); + phy_set_tx_power_index_by_rate_section(adapter, path, channel, VHT_1SSMCS0_1SSMCS9); + } } void rtl8821c_get_tx_power_level(PADAPTER adapter, s32 *power) @@ -432,14 +418,13 @@ void rtl8821c_get_tx_power_level(PADAPTER adapter, s32 *power) * Parameters: * padatper * powerindex power index for rate - * rfpath Antenna(RF) path, type "enum odm_rf_radio_path_e" + * rfpath Antenna(RF) path, type "enum rf_path" * rate data rate, type "enum MGN_RATE" */ /*#define DBG_SET_TX_POWER_IDX*/ -void rtl8821c_set_tx_power_index(PADAPTER adapter, u32 powerindex, u8 rfpath, u8 rate) +void rtl8821c_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate) { - PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *phydm = &hal->odmpriv; + struct dm_struct *phydm = adapter_to_phydm(adapter); u8 shift = 0; u8 hw_rate_idx; static u32 index = 0; @@ -452,11 +437,11 @@ void rtl8821c_set_tx_power_index(PADAPTER adapter, u32 powerindex, u8 rfpath, u8 rtw_warn_on(1); } - if (rfpath > ODM_RF_PATH_A) { + if (rfpath > RF_PATH_A) { #ifdef DBG_SET_TX_POWER_IDX - RTW_INFO(FUNC_ADPT_FMT" rfpath(%d) power index to ODM_RF_PATH_A\n", FUNC_ADPT_ARG(adapter), rfpath); + RTW_INFO(FUNC_ADPT_FMT" rfpath(%d) power index to RF_PATH_A\n", FUNC_ADPT_ARG(adapter), rfpath); #endif - rfpath = ODM_RF_PATH_A; + rfpath = RF_PATH_A; } /* * For 8821C, phydm api use 4 bytes txagc value @@ -494,23 +479,10 @@ void rtl8821c_set_tx_power_index(PADAPTER adapter, u32 powerindex, u8 rfpath, u8 } -static u8 rtl8821c_phy_get_current_tx_num(PADAPTER adapter, u8 rate) -{ - u8 tx_num = 0; - - if ((rate >= MGN_MCS8 && rate <= MGN_MCS15) || - (rate >= MGN_VHT2SS_MCS0 && rate <= MGN_VHT2SS_MCS9)) - tx_num = RF_2TX; - else - tx_num = RF_1TX; - - return tx_num; -} - /* * Parameters: * padatper - * rfpath Antenna(RF) path, type "enum odm_rf_radio_path_e" + * rfpath Antenna(RF) path, type "enum rf_path" * rate data rate, type "enum MGN_RATE" * bandwidth Bandwidth, type "enum _CHANNEL_WIDTH" * channel Channel number @@ -518,23 +490,25 @@ static u8 rtl8821c_phy_get_current_tx_num(PADAPTER adapter, u8 rate) * Rteurn: * tx_power power index for rate */ -u8 rtl8821c_get_tx_power_index(PADAPTER adapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) +u8 rtl8821c_get_tx_power_index(PADAPTER adapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - u8 base_idx = 0, power_idx = 0; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + s16 power_idx; + u8 base_idx = 0; s8 by_rate_diff = 0, limit = 0, tpt_offset = 0, extra_bias = 0; - u8 tx_num = rtl8821c_phy_get_current_tx_num(adapter, rate); u8 bIn24G = _FALSE; - base_idx = PHY_GetTxPowerIndexBase(adapter, rfpath, rate, bandwidth, channel, &bIn24G); + base_idx = PHY_GetTxPowerIndexBase(adapter, rfpath, rate, RF_1TX, bandwidth, channel, &bIn24G); - by_rate_diff = PHY_GetTxPowerByRate(adapter, (u8)(!bIn24G), rfpath, tx_num, rate); - limit = PHY_GetTxPowerLimit(adapter, adapter->registrypriv.RegPwrTblSel, (BAND_TYPE)(!bIn24G), - hal->current_channel_bw, rfpath, rate, hal->current_channel); + by_rate_diff = PHY_GetTxPowerByRate(adapter, (u8)(!bIn24G), rfpath, rate); + limit = PHY_GetTxPowerLimit(adapter, NULL, (BAND_TYPE)(!bIn24G), + hal->current_channel_bw, rfpath, rate, RF_1TX, hal->current_channel); /* tpt_offset += PHY_GetTxPowerTrackingOffset(adapter, rfpath, rate); */ if (tic) { + tic->ntx_idx = RF_1TX; tic->base = base_idx; tic->by_rate = by_rate_diff; tic->limit = limit; @@ -551,8 +525,10 @@ u8 rtl8821c_get_tx_power_index(PADAPTER adapter, u8 rfpath, u8 rate, u8 bandwidt #endif #endif - if (power_idx > MAX_POWER_INDEX) - power_idx = MAX_POWER_INDEX; + if (power_idx < 0) + power_idx = 0; + else if (power_idx > hal_spec->txgi_max) + power_idx = hal_spec->txgi_max; return power_idx; } @@ -648,8 +624,8 @@ static void mac_switch_bandwidth(PADAPTER adapter, u8 pri_ch_idx) u32 phy_get_tx_bbswing_8812c(_adapter *adapter, BAND_TYPE band, u8 rf_path) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = &pHalData->odmpriv; + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); s8 bbSwing_2G = -1 * GetRegTxBBSwing_2G(adapter); s8 bbSwing_5G = -1 * GetRegTxBBSwing_5G(adapter); u32 out = 0x200; @@ -730,7 +706,7 @@ u32 phy_get_tx_bbswing_8812c(_adapter *adapter, BAND_TYPE band, u8 rf_path) swing = 0x00; } - if (rf_path == ODM_RF_PATH_A) + if (rf_path == RF_PATH_A) onePathSwing = (swing & 0x3) >> 0; /* 0xC6/C7[1:0] */ if (onePathSwing == 0x0) { @@ -767,13 +743,12 @@ u32 phy_get_tx_bbswing_8812c(_adapter *adapter, BAND_TYPE band, u8 rf_path) void phy_set_bb_swing_by_band_8812c(_adapter *adapter, u8 band, u8 previous_band) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); s8 BBDiffBetweenBand = 0; - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + struct dm_struct *pDM_Odm = adapter_to_phydm(adapter); + struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); phy_set_bb_reg(adapter, rA_TxScale_Jaguar, 0xFFE00000, - phy_get_tx_bbswing_8812c(adapter, (BAND_TYPE)band, ODM_RF_PATH_A)); /* 0xC1C[31:21] */ + phy_get_tx_bbswing_8812c(adapter, (BAND_TYPE)band, RF_PATH_A)); /* 0xC1C[31:21] */ /* When TxPowerTrack is ON, we should take care of the change of BB swing. */ /* That is, reset all info to trigger Tx power tracking. */ @@ -794,7 +769,7 @@ void phy_switch_wireless_band_8821c(_adapter *adapter) { u8 ret = 0; PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &hal_data->odmpriv; + struct dm_struct *pDM_Odm = &hal_data->odmpriv; u8 current_band = hal_data->current_band_type; if (need_switch_band(adapter, hal_data->current_channel) == _TRUE) { @@ -833,7 +808,7 @@ void phy_switch_wireless_band_8821c(_adapter *adapter) void rtl8821c_switch_chnl_and_set_bw(PADAPTER adapter) { PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &hal->odmpriv; + struct dm_struct *pDM_Odm = &hal->odmpriv; u8 center_ch = 0, ret = 0; if (adapter->bNotifyChannelChange) { @@ -894,10 +869,11 @@ void rtl8821c_switch_chnl_and_set_bw(PADAPTER adapter) if ((hal->bNeedIQK == _TRUE) || (adapter->registrypriv.mp_mode == 1)) { #ifdef CONFIG_IQK_MONITOR - u32 iqk_start_time = rtw_get_current_time(); + systime iqk_start_time = rtw_get_current_time(); #endif - phy_iq_calibrate_8821c(pDM_Odm, _FALSE); + /*phy_iq_calibrate_8821c(pDM_Odm, _FALSE);*/ + rtw_phydm_iqk_trigger(adapter); #ifdef CONFIG_IQK_MONITOR RTW_INFO(ADPT_FMT" switch CH(%d) DO IQK : %d ms\n", @@ -922,12 +898,12 @@ void rtl8821c_switch_chnl_and_set_bw(PADAPTER adapter) void rtl8821c_handle_sw_chnl_and_set_bw( PADAPTER Adapter, u8 bSwitchChannel, u8 bSetBandWidth, - u8 ChannelNum, CHANNEL_WIDTH ChnlWidth, u8 ChnlOffsetOf40MHz, + u8 ChannelNum, enum channel_width ChnlWidth, u8 ChnlOffsetOf40MHz, u8 ChnlOffsetOf80MHz, u8 CenterFrequencyIndex1) { PHAL_DATA_TYPE hal = GET_HAL_DATA(Adapter); u8 tmpChannel = hal->current_channel; - CHANNEL_WIDTH tmpBW = hal->current_channel_bw; + enum channel_width tmpBW = hal->current_channel_bw; u8 tmpnCur40MhzPrimeSC = hal->nCur40MhzPrimeSC; u8 tmpnCur80MhzPrimeSC = hal->nCur80MhzPrimeSC; u8 tmpCenterFrequencyIndex1 = hal->CurrentCenterFrequencyIndex1; @@ -1008,7 +984,7 @@ void rtl8821c_handle_sw_chnl_and_set_bw( * offset40 channel offset for 40MHz Bandwidth * offset80 channel offset for 80MHz Bandwidth */ -void rtl8821c_set_channel_bw(PADAPTER adapter, u8 center_ch, CHANNEL_WIDTH bw, u8 offset40, u8 offset80) +void rtl8821c_set_channel_bw(PADAPTER adapter, u8 center_ch, enum channel_width bw, u8 offset40, u8 offset80) { rtl8821c_handle_sw_chnl_and_set_bw(adapter, _TRUE, _TRUE, center_ch, bw, offset40, offset80, center_ch); } @@ -1020,7 +996,410 @@ void rtl8821c_notch_filter_switch(PADAPTER adapter, bool enable) else RTW_INFO("%s: Disable notch filter\n", __FUNCTION__); } +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 +/* REG_TXBF_CTRL (Offset 0x42C) */ +#define BITS_R_TXBF1_AID_8821C (BIT_MASK_R_TXBF1_AID_8821C << BIT_SHIFT_R_TXBF1_AID_8821C) +#define BIT_CLEAR_R_TXBF1_AID_8821C(x) ((x) & (~BITS_R_TXBF1_AID_8821C)) +#define BIT_SET_R_TXBF1_AID_8821C(x, v) (BIT_CLEAR_R_TXBF1_AID_8821C(x) | BIT_R_TXBF1_AID_8821C(v)) + +#define BITS_R_TXBF0_AID_8821C (BIT_MASK_R_TXBF0_AID_8821C << BIT_SHIFT_R_TXBF0_AID_8821C) +#define BIT_CLEAR_R_TXBF0_AID_8821C(x) ((x) & (~BITS_R_TXBF0_AID_8821C)) +#define BIT_SET_R_TXBF0_AID_8821C(x, v) (BIT_CLEAR_R_TXBF0_AID_8821C(x) | BIT_R_TXBF0_AID_8821C(v)) + +/* REG_NDPA_OPT_CTRL (Offset 0x45F) */ +#define BITS_R_NDPA_BW_8821C (BIT_MASK_R_NDPA_BW_8821C << BIT_SHIFT_R_NDPA_BW_8821C) +#define BIT_CLEAR_R_NDPA_BW_8821C(x) ((x) & (~BITS_R_NDPA_BW_8821C)) +#define BIT_SET_R_NDPA_BW_8821C(x, v) (BIT_CLEAR_R_NDPA_BW_8821C(x) | BIT_R_NDPA_BW_8821C(v)) + +/* REG_ASSOCIATED_BFMEE_SEL (Offset 0x714) */ +#define BITS_AID1_8821C (BIT_MASK_AID1_8821C << BIT_SHIFT_AID1_8821C) +#define BIT_CLEAR_AID1_8821C(x) ((x) & (~BITS_AID1_8821C)) +#define BIT_SET_AID1_8821C(x, v) (BIT_CLEAR_AID1_8821C(x) | BIT_AID1_8821C(v)) + +#define BITS_AID0_8821C (BIT_MASK_AID0_8821C << BIT_SHIFT_AID0_8821C) +#define BIT_CLEAR_AID0_8821C(x) ((x) & (~BITS_AID0_8821C)) +#define BIT_SET_AID0_8821C(x, v) (BIT_CLEAR_AID0_8821C(x) | BIT_AID0_8821C(v)) + +/* REG_MU_TX_CTL (Offset 0x14C0) */ +#define BIT_R_MU_P1_WAIT_STATE_EN_8821C BIT(16) + +#define BIT_SHIFT_R_MU_RL_8821C 12 +#define BITS_R_MU_RL_8821C (BIT_MASK_R_MU_RL_8821C << BIT_SHIFT_R_MU_RL_8821C) +#define BIT_R_MU_RL_8821C(x) (((x) & BIT_MASK_R_MU_RL_8821C) << BIT_SHIFT_R_MU_RL_8821C) +#define BIT_CLEAR_R_MU_RL_8821C(x) ((x) & (~BITS_R_MU_RL_8821C)) +#define BIT_SET_R_MU_RL_8821C(x, v) (BIT_CLEAR_R_MU_RL_8821C(x) | BIT_R_MU_RL_8821C(v)) + +#define BIT_SHIFT_R_MU_TAB_SEL_8821C 8 +#define BIT_MASK_R_MU_TAB_SEL_8821C 0x7 +#define BITS_R_MU_TAB_SEL_8821C (BIT_MASK_R_MU_TAB_SEL_8821C << BIT_SHIFT_R_MU_TAB_SEL_8821C) +#define BIT_R_MU_TAB_SEL_8821C(x) (((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C) +#define BIT_CLEAR_R_MU_TAB_SEL_8821C(x) ((x) & (~BITS_R_MU_TAB_SEL_8821C)) +#define BIT_SET_R_MU_TAB_SEL_8821C(x, v) (BIT_CLEAR_R_MU_TAB_SEL_8821C(x) | BIT_R_MU_TAB_SEL_8821C(v)) + +#define BIT_R_EN_MU_MIMO_8821C BIT(7) + +#define BITS_R_MU_TABLE_VALID_8821C (BIT_MASK_R_MU_TABLE_VALID_8821C << BIT_SHIFT_R_MU_TABLE_VALID_8821C) +#define BIT_CLEAR_R_MU_TABLE_VALID_8821C(x) ((x) & (~BITS_R_MU_TABLE_VALID_8821C)) +#define BIT_SET_R_MU_TABLE_VALID_8821C(x, v) (BIT_CLEAR_R_MU_TABLE_VALID_8821C(x) | BIT_R_MU_TABLE_VALID_8821C(v)) + +/* REG_WMAC_MU_BF_CTL (Offset 0x1680) */ +#define BITS_WMAC_MU_BFRPTSEG_SEL_8821C (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) +#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x) ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8821C)) +#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8821C(x, v) (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x) | BIT_WMAC_MU_BFRPTSEG_SEL_8821C(v)) + +#define BITS_WMAC_MU_BF_MYAID_8821C (BIT_MASK_WMAC_MU_BF_MYAID_8821C << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) +#define BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x) ((x) & (~BITS_WMAC_MU_BF_MYAID_8821C)) +#define BIT_SET_WMAC_MU_BF_MYAID_8821C(x, v) (BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x) | BIT_WMAC_MU_BF_MYAID_8821C(v)) + +/* REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ +#define BIT_STATUS_BFEE7_8821C BIT(10) + + +static u8 _bf_get_nrx(PADAPTER adapter) +{ + u8 rf; + u8 nrx = 0; + + + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &rf); + switch (rf) { + case RF_1T1R: + nrx = 0; + break; + default: + case RF_1T2R: + case RF_2T2R: + nrx = 1; + break; + } + + return nrx; +} + + +static void _config_beamformer_su(PADAPTER adapter, struct beamformer_entry *bfer) +{ + /* Beamforming */ + u8 nc_index = 0, nr_index = 0; + u8 grouping = 0, codebookinfo = 0, coefficientsize = 0; + u32 addr_bfer_info, addr_csi_rpt; + u32 csi_param; + /* Misc */ + u8 i; + + + RTW_INFO("%s: Config SU BFer entry HW setting\n", __FUNCTION__); + + if (bfer->su_reg_index == 0) { + addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO_8821C; + addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20_8821C; + } else { + addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO_8821C; + addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20_8821C + 2; + } + + /* Sounding protocol control */ + rtw_write8(adapter, REG_SND_PTCL_CTRL_8821C, 0xDB); + + /* MAC address/Partial AID of Beamformer */ + for (i = 0; i < ETH_ALEN; i++) + rtw_write8(adapter, addr_bfer_info+i, bfer->mac_addr[i]); + + /* CSI report parameters of Beamformer */ + nc_index = _bf_get_nrx(adapter); + /* + * 0x718[7] = 1 use Nsts + * 0x718[7] = 0 use reg setting + * As Bfee, we use Nsts, so nr_index don't care + */ + nr_index = bfer->NumofSoundingDim; + grouping = 0; + /* for ac = 1, for n = 3 */ + if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU)) + codebookinfo = 1; + else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_HT_EXPLICIT)) + codebookinfo = 3; + coefficientsize = 3; + csi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(nr_index<<3)|(nc_index)); + rtw_write16(adapter, addr_csi_rpt, csi_param); + RTW_INFO("%s: nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n", + __FUNCTION__, nc_index, nr_index, grouping, codebookinfo, coefficientsize); + RTW_INFO("%s: csi=0x%04x\n", __FUNCTION__, csi_param); + + /* ndp_rx_standby_timer */ + rtw_write8(adapter, REG_SND_PTCL_CTRL_8821C+3, 0x70); +} + +static void _config_beamformer_mu(PADAPTER adapter, struct beamformer_entry *bfer) +{ + /* General */ + PHAL_DATA_TYPE hal; + /* Beamforming */ + struct beamforming_info *bf_info; + u8 nc_index = 0, nr_index = 0; + u8 grouping = 0, codebookinfo = 0, coefficientsize = 0; + u32 csi_param; + /* Misc */ + u8 i, val8; + u16 val16; + + RTW_INFO("%s: Config MU BFer entry HW setting\n", __FUNCTION__); + + hal = GET_HAL_DATA(adapter); + bf_info = GET_BEAMFORM_INFO(adapter); + + /* Reset GID table */ + for (i = 0; i < 8; i++) + bfer->gid_valid[i] = 0; + for (i = 0; i < 16; i++) + bfer->user_position[i] = 0; + + /* CSI report parameters of Beamformer */ + nc_index = _bf_get_nrx(adapter); + nr_index = 1; /* 0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care */ + grouping = 0; /* no grouping */ + codebookinfo = 1; /* 7 bit for psi, 9 bit for phi */ + coefficientsize = 0; /* This is nothing really matter */ + csi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)| + (grouping<<6)|(nr_index<<3)|(nc_index)); + + RTW_INFO("%s: nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n", + __func__, nc_index, nr_index, grouping, codebookinfo, + coefficientsize); + RTW_INFO("%s: csi=0x%04x\n", __func__, csi_param); + + rtw_halmac_bf_add_mu_bfer(adapter_to_dvobj(adapter), bfer->p_aid, + csi_param, bfer->aid & 0xfff, HAL_CSI_SEG_4K, + bfer->mac_addr); + + bf_info->cur_csi_rpt_rate = HALMAC_OFDM6; + rtw_halmac_bf_cfg_sounding(adapter_to_dvobj(adapter), HAL_BFEE, + bf_info->cur_csi_rpt_rate); + + /* Set 0x6A0[14] = 1 to accept action_no_ack */ + val8 = rtw_read8(adapter, REG_RXFLTMAP0_8821C+1); + val8 |= (BIT_MGTFLT14EN_8821C >> 8); + rtw_write8(adapter, REG_RXFLTMAP0_8821C+1, val8); + + /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */ + val8 = rtw_read8(adapter, REG_RXFLTMAP1_8821C); + val8 |= BIT_CTRLFLT4EN_8821C | BIT_CTRLFLT5EN_8821C; + rtw_write8(adapter, REG_RXFLTMAP1_8821C, val8); + + /* for B-Cut */ + if (IS_B_CUT(hal->version_id)) { + phy_set_bb_reg(adapter, REG_RXFLTMAP0_8821C, BIT(20), 0); + phy_set_bb_reg(adapter, REG_RXFLTMAP3_8821C, BIT(20), 0); + } +} + + + +static void _reset_beamformer_su(PADAPTER adapter, struct beamformer_entry *bfer) +{ + /* Beamforming */ + struct beamforming_info *info; + u8 idx; + + + info = GET_BEAMFORM_INFO(adapter); + /* SU BFer */ + idx = bfer->su_reg_index; + + if (idx == 0) { + rtw_write32(adapter, REG_ASSOCIATED_BFMER0_INFO_8821C, 0); + rtw_write16(adapter, REG_ASSOCIATED_BFMER0_INFO_8821C+4, 0); + rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8821C, 0); + } else { + rtw_write32(adapter, REG_ASSOCIATED_BFMER1_INFO_8821C, 0); + rtw_write16(adapter, REG_ASSOCIATED_BFMER1_INFO_8821C+4, 0); + rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8821C+2, 0); + } + + info->beamformer_su_reg_maping &= ~BIT(idx); + bfer->su_reg_index = 0xFF; + + RTW_INFO("%s: Clear SU BFer entry(%d) HW setting\n", __FUNCTION__, idx); +} + +static void _reset_beamformer_mu(PADAPTER adapter, struct beamformer_entry *bfer) +{ + struct beamforming_info *bf_info; + + bf_info = GET_BEAMFORM_INFO(adapter); + + rtw_halmac_bf_del_mu_bfer(adapter_to_dvobj(adapter)); + + if (bf_info->beamformer_su_cnt == 0 && + bf_info->beamformer_mu_cnt == 0) + rtw_halmac_bf_del_sounding(adapter_to_dvobj(adapter), HAL_BFEE); + + RTW_INFO("%s: Clear MU BFer entry HW setting\n", __FUNCTION__); +} + +void rtl8821c_phy_bf_init(PADAPTER adapter) +{ + u8 v8; + u32 v32; + + v32 = rtw_read32(adapter, REG_MU_TX_CTL_8821C); + /* Enable P1 aggr new packet according to P0 transfer time */ + v32 |= BIT_R_MU_P1_WAIT_STATE_EN_8821C; + /* MU Retry Limit */ + v32 = BIT_SET_R_MU_RL_8821C(v32, 0xA); + /* Disable Tx MU-MIMO until sounding done */ + v32 &= ~BIT_R_EN_MU_MIMO_8821C; + /* Clear validity of MU STAs */ + v32 = BIT_SET_R_MU_TABLE_VALID_8821C(v32, 0); + rtw_write32(adapter, REG_MU_TX_CTL_8821C, v32); + + /* MU-MIMO Option as default value */ + v8 = BIT_WMAC_TXMU_ACKPOLICY_8821C(3); + v8 |= BIT_WMAC_TXMU_ACKPOLICY_EN_8821C; + rtw_write8(adapter, REG_MU_BF_OPTION_8821C, v8); + /* MU-MIMO Control as default value */ + rtw_write16(adapter, REG_WMAC_MU_BF_CTL_8821C, 0); + + /* Set MU NDPA rate & BW source */ + /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ + v8 = rtw_read8(adapter, REG_TXBF_CTRL_8821C+3); + v8 |= (BIT_USE_NDPA_PARAMETER_8821C >> 24); + rtw_write8(adapter, REG_TXBF_CTRL_8821C+3, v8); + /* 0x45F[7:0] = 0x10 (Rate=OFDM_6M, BW20) */ + rtw_write8(adapter, REG_NDPA_OPT_CTRL_8821C, 0x10); + + /* Temp Settings */ + /* STA2's CSI rate is fixed at 6M */ + v8 = rtw_read8(adapter, 0x6DF); + v8 = (v8 & 0xC0) | 0x4; + rtw_write8(adapter, 0x6DF, v8); + /* Grouping bitmap parameters */ + rtw_write32(adapter, 0x1C94, 0xAFFFAFFF); +} + +void rtl8821c_phy_bf_enter(PADAPTER adapter, struct sta_info *sta) +{ + struct beamforming_info *info; + struct beamformer_entry *bfer; + + + + RTW_INFO("+%s: " MAC_FMT "\n", __FUNCTION__, MAC_ARG(sta->cmn.mac_addr)); + + info = GET_BEAMFORM_INFO(adapter); + bfer = rtw_bf_bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr); + + + info->bSetBFHwConfigInProgess = _TRUE; + + if (bfer) { + bfer->state = BEAMFORM_ENTRY_HW_STATE_ADDING; + + if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_MU)) + _config_beamformer_mu(adapter, bfer); + else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) + _config_beamformer_su(adapter, bfer); + + bfer->state = BEAMFORM_ENTRY_HW_STATE_ADDED; + } + + info->bSetBFHwConfigInProgess = _FALSE; + + RTW_INFO("-%s\n", __FUNCTION__); +} + +void rtl8821c_phy_bf_leave(PADAPTER adapter, u8 *addr) +{ + struct beamforming_info *info; + struct beamformer_entry *bfer; + + + RTW_INFO("+%s: " MAC_FMT "\n", __FUNCTION__, MAC_ARG(addr)); + + info = GET_BEAMFORM_INFO(adapter); + + bfer = rtw_bf_bfer_get_entry_by_addr(adapter, addr); + + + /* Clear P_AID of Beamformee */ + /* Clear MAC address of Beamformer */ + /* Clear Associated Bfmee Sel */ + if (bfer) { + bfer->state = BEAMFORM_ENTRY_HW_STATE_DELETING; + + rtw_write8(adapter, REG_SND_PTCL_CTRL_8821C, 0xD8); + + if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_MU)) + _reset_beamformer_mu(adapter, bfer); + else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) + _reset_beamformer_su(adapter, bfer); + + bfer->state = BEAMFORM_ENTRY_HW_STATE_NONE; + bfer->cap = BEAMFORMING_CAP_NONE; + bfer->used = _FALSE; + } + + + RTW_INFO("-%s\n", __FUNCTION__); +} + +void rtl8821c_phy_bf_set_gid_table(PADAPTER adapter, + struct beamformer_entry *bfer_info) +{ + struct beamformer_entry *bfer; + struct beamforming_info *info; + u32 gid_valid[2] = {0}; + u32 user_position[4] = {0}; + int i; + + /* update bfer info */ + bfer = rtw_bf_bfer_get_entry_by_addr(adapter, bfer_info->mac_addr); + if (!bfer) { + RTW_INFO("%s: Cannot find BFer entry!!\n", __func__); + return; + } + _rtw_memcpy(bfer->gid_valid, bfer_info->gid_valid, 8); + _rtw_memcpy(bfer->user_position, bfer_info->user_position, 16); + + info = GET_BEAMFORM_INFO(adapter); + info->bSetBFHwConfigInProgess = _TRUE; + + /* For GID 0~31 */ + for (i = 0; i < 4; i++) + gid_valid[0] |= (bfer->gid_valid[i] << (i << 3)); + + for (i = 0; i < 8; i++) { + if (i < 4) + user_position[0] |= (bfer->user_position[i] << (i << 3)); + else + user_position[1] |= (bfer->user_position[i] << ((i - 4) << 3)); + } + + RTW_INFO("%s: STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n", + __func__, gid_valid[0], user_position[0], user_position[1]); + + /* For GID 32~64 */ + for (i = 4; i < 8; i++) + gid_valid[1] |= (bfer->gid_valid[i] << ((i - 4) << 3)); + + for (i = 8; i < 16; i++) { + if (i < 12) + user_position[2] |= (bfer->user_position[i] << ((i - 8) << 3)); + else + user_position[3] |= (bfer->user_position[i] << ((i - 12) << 3)); + } + + RTW_INFO("%s: STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n", + __func__, gid_valid[1], user_position[2], user_position[3]); + + rtw_halmac_bf_cfg_mu_bfee(adapter_to_dvobj(adapter), gid_valid, user_position); + + info->bSetBFHwConfigInProgess = _FALSE; +} +#endif /* RTW_BEAMFORMING_VERSION_2 */ +#endif /* CONFIG_BEAMFORMING */ #ifdef CONFIG_MP_INCLUDED /* * Description: @@ -1034,7 +1413,7 @@ void rtl8821c_mp_config_rfpath(PADAPTER adapter) PHAL_DATA_TYPE hal; PMPT_CONTEXT mpt; ANTENNA_PATH anttx, antrx; - enum odm_rf_path_e rxant; + enum rf_path rxant; hal = GET_HAL_DATA(adapter); diff --git a/halmac.mk b/halmac.mk new file mode 100644 index 0000000..95887f8 --- /dev/null +++ b/halmac.mk @@ -0,0 +1,68 @@ +# All needed files would be added to _HAL_INTFS_FILES, and it would include +# hal/hal_halmac.c and all related files in directory hal/halmac/. +# Before include this makefile, be sure interface (CONFIG_*_HCI) and IC +# (CONFIG_RTL*) setting are all ready! + +# Base directory +path_hm := hal/halmac +# Level 1 directory +path_hm_d1 := $(path_hm)/halmac_88xx + +ifeq ($(CONFIG_PCI_HCI), y) +pci := y +endif +ifeq ($(CONFIG_SDIO_HCI), y) +sdio := y +endif +ifeq ($(CONFIG_USB_HCI), y) +usb := y +endif + +ifeq ($(CONFIG_RTL8822B), y) +ic := 8822b +endif + +ifeq ($(CONFIG_RTL8822C), y) +ic := 8822c +endif + +ifeq ($(CONFIG_RTL8821C), y) +ic := 8821c +endif + +ifeq ($(CONFIG_RTL8814B), y) +v1 := "_v1" +ic := 8814b +endif + +halmac-y += $(path_hm)/halmac_api.o + +# Modify level 1 directory if needed +path_hm_d1 := $(path_hm_d1)$(v1) +halmac-y += $(path_hm_d1)/halmac_bb_rf_88xx$(v1).o \ + $(path_hm_d1)/halmac_cfg_wmac_88xx$(v1).o \ + $(path_hm_d1)/halmac_common_88xx$(v1).o \ + $(path_hm_d1)/halmac_efuse_88xx$(v1).o \ + $(path_hm_d1)/halmac_flash_88xx$(v1).o \ + $(path_hm_d1)/halmac_fw_88xx$(v1).o \ + $(path_hm_d1)/halmac_gpio_88xx$(v1).o \ + $(path_hm_d1)/halmac_init_88xx$(v1).o \ + $(path_hm_d1)/halmac_mimo_88xx$(v1).o +halmac-$(pci) += $(path_hm_d1)/halmac_pcie_88xx$(v1).o +halmac-$(sdio) += $(path_hm_d1)/halmac_sdio_88xx$(v1).o +halmac-$(usb) += $(path_hm_d1)/halmac_usb_88xx$(v1).o + +# Level 2 directory +path_hm_d2 := $(path_hm_d1)/halmac_$(ic) +halmac-y += $(path_hm_d2)/halmac_cfg_wmac_$(ic).o \ + $(path_hm_d2)/halmac_common_$(ic).o \ + $(path_hm_d2)/halmac_gpio_$(ic).o \ + $(path_hm_d2)/halmac_init_$(ic).o \ + $(path_hm_d2)/halmac_phy_$(ic).o \ + $(path_hm_d2)/halmac_pwr_seq_$(ic).o +halmac-$(pci) += $(path_hm_d2)/halmac_pcie_$(ic).o +halmac-$(sdio) += $(path_hm_d2)/halmac_sdio_$(ic).o +halmac-$(usb) += $(path_hm_d2)/halmac_usb_$(ic).o + +_HAL_INTFS_FILES += hal/hal_halmac.o +_HAL_INTFS_FILES += $(halmac-y) diff --git a/ifcfg-wlan0 b/ifcfg-wlan0 index 20dcbec..7ecb7ae 100644 --- a/ifcfg-wlan0 +++ b/ifcfg-wlan0 @@ -1,4 +1,4 @@ -#DHCP client -DEVICE=wlan0 -BOOTPROTO=dhcp +#DHCP client +DEVICE=wlan0 +BOOTPROTO=dhcp ONBOOT=yes \ No newline at end of file diff --git a/include/Hal8188EPhyCfg.h b/include/Hal8188EPhyCfg.h index c0558bc..3fc0b11 100644 --- a/include/Hal8188EPhyCfg.h +++ b/include/Hal8188EPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8188EPHYCFG_H__ #define __INC_HAL8188EPHYCFG_H__ @@ -68,11 +63,11 @@ void PHY_SetBBReg8188E(IN PADAPTER Adapter, IN u32 BitMask, IN u32 Data); u32 PHY_QueryRFReg8188E(IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask); void PHY_SetRFReg8188E(IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask, IN u32 Data); @@ -86,7 +81,7 @@ int PHY_BBConfig8188E(IN PADAPTER Adapter); int PHY_RFConfig8188E(IN PADAPTER Adapter); /* RF config */ -int rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 *pFileName, u8 eRFPath); +int rtl8188e_PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN u8 *pFileName, enum rf_path eRFPath); /* * RF Power setting @@ -108,14 +103,14 @@ VOID PHY_SetTxPowerIndex_8188E( IN PADAPTER Adapter, IN u32 PowerIndex, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ); u8 PHY_GetTxPowerIndex_8188E( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, IN u8 BandWidth, IN u8 Channel, @@ -127,7 +122,7 @@ PHY_GetTxPowerIndex_8188E( */ /* extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); */ void PHY_SetBWMode8188E(IN PADAPTER pAdapter, - IN CHANNEL_WIDTH ChnlWidth, + IN enum channel_width ChnlWidth, IN unsigned char Offset); /* @@ -155,7 +150,7 @@ VOID PHY_SetSwChnlBWMode8188E( IN PADAPTER Adapter, IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, + IN enum channel_width Bandwidth, IN u8 Offset40, IN u8 Offset80 ); @@ -167,7 +162,7 @@ PHY_SetRFEReg_8188E( /* * BB/MAC/RF other monitor API * */ -VOID phy_set_rf_path_switch_8188e(IN PADAPTER pAdapter, IN bool bMain); +VOID phy_set_rf_path_switch_8188e(IN struct dm_struct *phydm, IN bool bMain); extern VOID PHY_SwitchEphyParameter( diff --git a/include/Hal8188EPhyReg.h b/include/Hal8188EPhyReg.h index 783ea64..2eab831 100644 --- a/include/Hal8188EPhyReg.h +++ b/include/Hal8188EPhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8188EPHYREG_H__ #define __INC_HAL8188EPHYREG_H__ /*--------------------------Define Parameters-------------------------------*/ diff --git a/include/Hal8188EPwrSeq.h b/include/Hal8188EPwrSeq.h index 385722a..46c61ab 100644 --- a/include/Hal8188EPwrSeq.h +++ b/include/Hal8188EPwrSeq.h @@ -1,7 +1,6 @@ - /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,12 +11,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ + #ifndef __HAL8188EPWRSEQ_H__ #define __HAL8188EPWRSEQ_H__ diff --git a/include/Hal8188FPhyCfg.h b/include/Hal8188FPhyCfg.h index 410d9c3..1f03a33 100644 --- a/include/Hal8188FPhyCfg.h +++ b/include/Hal8188FPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8188FPHYCFG_H__ #define __INC_HAL8188FPHYCFG_H__ @@ -60,7 +55,7 @@ PHY_SetBBReg_8188F( u32 PHY_QueryRFReg_8188F( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask ); @@ -68,7 +63,7 @@ PHY_QueryRFReg_8188F( VOID PHY_SetRFReg_8188F( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask, IN u32 Data @@ -84,22 +79,22 @@ s32 PHY_MACConfig8188F(PADAPTER padapter); int PHY_ConfigRFWithParaFile_8188F( IN PADAPTER Adapter, - IN u8 *pFileName, - RF_PATH eRFPath + IN u8 *pFileName, + enum rf_path eRFPath ); VOID PHY_SetTxPowerIndex_8188F( IN PADAPTER Adapter, IN u32 PowerIndex, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ); u8 PHY_GetTxPowerIndex_8188F( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, IN u8 BandWidth, IN u8 Channel, @@ -122,13 +117,13 @@ VOID PHY_SetSwChnlBWMode8188F( IN PADAPTER Adapter, IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, + IN enum channel_width Bandwidth, IN u8 Offset40, IN u8 Offset80 ); VOID phy_set_rf_path_switch_8188f( - IN PADAPTER pAdapter, + IN struct dm_struct *phydm, IN bool bMain ); diff --git a/include/Hal8188FPhyReg.h b/include/Hal8188FPhyReg.h index 8d38c0f..a831faa 100644 --- a/include/Hal8188FPhyReg.h +++ b/include/Hal8188FPhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8188FPHYREG_H__ #define __INC_HAL8188FPHYREG_H__ diff --git a/include/Hal8188FPwrSeq.h b/include/Hal8188FPwrSeq.h index 81e6132..5cad428 100644 --- a/include/Hal8188FPwrSeq.h +++ b/include/Hal8188FPwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8188F #define REALTEK_POWER_SEQUENCE_8188F diff --git a/include/Hal8192EPhyCfg.h b/include/Hal8192EPhyCfg.h index 17dd982..d6394c6 100644 --- a/include/Hal8192EPhyCfg.h +++ b/include/Hal8192EPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8192EPHYCFG_H__ #define __INC_HAL8192EPHYCFG_H__ @@ -64,11 +59,11 @@ void PHY_SetBBReg8192E(IN PADAPTER Adapter, IN u32 BitMask, IN u32 Data); u32 PHY_QueryRFReg8192E(IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask); void PHY_SetRFReg8192E(IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask, IN u32 Data); @@ -95,14 +90,14 @@ VOID PHY_SetTxPowerIndex_8192E( IN PADAPTER Adapter, IN u32 PowerIndex, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ); u8 PHY_GetTxPowerIndex_8192E( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, IN u8 BandWidth, IN u8 Channel, @@ -116,7 +111,7 @@ VOID PHY_SetSwChnlBWMode8192E( IN PADAPTER Adapter, IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, + IN enum channel_width Bandwidth, IN u8 Offset40, IN u8 Offset80 ); @@ -145,7 +140,7 @@ phy_SpurCalibration_8192E_NBI( VOID phy_set_rf_path_switch_8192e( - IN PADAPTER pAdapter, + IN struct dm_struct *phydm, IN bool bMain ); diff --git a/include/Hal8192EPhyReg.h b/include/Hal8192EPhyReg.h index cd13c22..30b7711 100644 --- a/include/Hal8192EPhyReg.h +++ b/include/Hal8192EPhyReg.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2012 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ /***************************************************************************** * Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved. * diff --git a/include/Hal8192EPwrSeq.h b/include/Hal8192EPwrSeq.h index 12bb2fb..1f2ba87 100644 --- a/include/Hal8192EPwrSeq.h +++ b/include/Hal8192EPwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2012 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8192E #define REALTEK_POWER_SEQUENCE_8192E diff --git a/include/Hal8192FPhyCfg.h b/include/Hal8192FPhyCfg.h new file mode 100644 index 0000000..db396d4 --- /dev/null +++ b/include/Hal8192FPhyCfg.h @@ -0,0 +1,131 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __INC_HAL8192FPHYCFG_H__ +#define __INC_HAL8192FPHYCFG_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define LOOP_LIMIT 5 +#define MAX_STALL_TIME 50 /* us */ +#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ +#define MAX_TXPWR_IDX_NMODE_92S 63 +#define Reset_Cnt_Limit 3 + +#ifdef CONFIG_PCI_HCI + #define MAX_AGGR_NUM 0x0B +#else + #define MAX_AGGR_NUM 0x07 +#endif /* CONFIG_PCI_HCI */ + + +/*--------------------------Define Parameters End-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ + +/*------------------------------Define structure End----------------------------*/ + +/*--------------------------Exported Function prototype---------------------*/ +u32 +PHY_QueryBBReg_8192F( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask +); + +VOID +PHY_SetBBReg_8192F( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +); + +u32 +PHY_QueryRFReg_8192F( + IN PADAPTER Adapter, + IN enum rf_path eRFPath, + IN u32 RegAddr, + IN u32 BitMask +); + +VOID +PHY_SetRFReg_8192F( + IN PADAPTER Adapter, + IN enum rf_path eRFPath, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +); + +/* MAC/BB/RF HAL config */ +int PHY_BBConfig8192F(PADAPTER Adapter ); + +int PHY_RFConfig8192F(PADAPTER Adapter); + +s32 PHY_MACConfig8192F(PADAPTER padapter); + +int +PHY_ConfigRFWithParaFile_8192F( + IN PADAPTER Adapter, + IN u8 *pFileName, + enum rf_path eRFPath +); + +VOID +PHY_SetTxPowerIndex_8192F( + IN PADAPTER Adapter, + IN u32 PowerIndex, + IN enum rf_path RFPath, + IN u8 Rate +); + +u8 +PHY_GetTxPowerIndex_8192F( + IN PADAPTER pAdapter, + IN enum rf_path RFPath, + IN u8 Rate, + IN u8 BandWidth, + IN u8 Channel, + struct txpwr_idx_comp *tic +); + +VOID +PHY_GetTxPowerLevel8192F( + IN PADAPTER Adapter, + OUT s32 *powerlevel +); + +VOID +PHY_SetTxPowerLevel8192F( + IN PADAPTER Adapter, + IN u8 channel +); + +VOID +PHY_SetSwChnlBWMode8192F( + IN PADAPTER Adapter, + IN u8 channel, + IN enum channel_width Bandwidth, + IN u8 Offset40, + IN u8 Offset80 +); + +VOID phy_set_rf_path_switch_8192f( + IN PADAPTER pAdapter, + IN bool bMain +); +/*--------------------------Exported Function prototype End---------------------*/ + +#endif diff --git a/include/Hal8192FPhyReg.h b/include/Hal8192FPhyReg.h new file mode 100644 index 0000000..b82f7f9 --- /dev/null +++ b/include/Hal8192FPhyReg.h @@ -0,0 +1,1134 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __INC_HAL8192FPHYREG_H__ +#define __INC_HAL8192FPHYREG_H__ + +#define rSYM_WLBT_PAPE_SEL 0x64 +/* + * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF + * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF + * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 + * 3. RF register 0x00-2E + * 4. Bit Mask for BB/RF register + * 5. Other definition for BB/RF R/W + * */ + + +/* + * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF + * 1. Page1(0x100) + * */ +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +/* + * 2. Page2(0x200) + * + * The following two definition are only used for USB interface. */ +#define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ +#define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ + +/* + * 3. Page8(0x800) + * */ +#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC // RF BW Setting?? */ + +#define rFPGA0_TxInfo 0x804 /* Status report?? */ +#define rFPGA0_PSDFunction 0x808 + +#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ + +#define rFPGA0_RFTiming1 0x810 /* Useless now */ +#define rFPGA0_RFTiming2 0x814 + +#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rTxAGC_B_Rate18_06 0x830 +#define rTxAGC_B_Rate54_24 0x834 +#define rTxAGC_B_CCK1_55_Mcs32 0x838 +#define rTxAGC_B_Mcs03_Mcs00 0x83c + +#define rTxAGC_B_Mcs07_Mcs04 0x848 +#define rTxAGC_B_Mcs11_Mcs08 0x84c + +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 + +#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ +#define rFPGA0_RFSleepUpParameter 0x854 + +#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ +#define rFPGA0_XCD_SwitchControl 0x85c + +#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ +#define rFPGA0_XB_RFInterfaceOE 0x864 + +#define rTxAGC_B_Mcs15_Mcs12 0x868 +#define rTxAGC_B_CCK11_A_CCK2_11 0x86c + +#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ +#define rFPGA0_XCD_RFInterfaceSW 0x874 + +#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ +#define rFPGA0_XCD_RFParameter 0x87c + +#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 /* Useless now */ +#define rFPGA0_AnalogParameter4 0x88c + +#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac + +#define rFPGA0_PSDReport 0x8b4 /* Useless now */ +#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ +#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now // RF Interface Readback Value */ +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ + +/* + * 4. Page9(0x900) + * */ +#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC // RF BW Setting?? */ +#define rFPGA1_TxBlock 0x904 /* Useless now */ +#define rFPGA1_DebugSelect 0x908 /* Useless now */ +#define rFPGA1_TxInfo 0x90c /* Useless now // Status report?? */ +#define rDPDT_control 0x92c +#define rfe_ctrl_anta_src 0x930 +#define rS0S1_PathSwitch 0x948 +#define rBBrx_DFIR 0x954 + +/* + * 5. PageA(0xA00) + * + * Set Control channel to upper or lower. These settings are required only for 40MHz */ +#define rCCK0_System 0xa00 + +#define rCCK0_AFESetting 0xa04 /* Disable init gain now // Select RX path by RSSI */ +#define rCCK0_CCA 0xa08 /* Disable init gain now // Init gain */ + +#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ +#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ + +#define rCCK0_RxHP 0xa14 + +#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ +#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ + +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ +#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 /* 0xa57 */ +#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ +#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ + +/* + * PageB(0xB00) + * */ +#define rPdp_AntA 0xb00 +#define rPdp_AntA_4 0xb04 +#define rPdp_AntA_8 0xb08 +#define rPdp_AntA_C 0xb0c +#define rPdp_AntA_10 0xb10 +#define rPdp_AntA_14 0xb14 +#define rPdp_AntA_18 0xb18 +#define rPdp_AntA_1C 0xb1c +#define rPdp_AntA_20 0xb20 +#define rPdp_AntA_24 0xb24 + +#define rConfig_Pmpd_AntA 0xb28 +#define rConfig_ram64x16 0xb2c + +#define rBndA 0xb30 +#define rHssiPar 0xb34 + +#define rConfig_AntA 0xb68 +#define rConfig_AntB 0xb6c + +#define rPdp_AntB 0xb70 +#define rPdp_AntB_4 0xb74 +#define rPdp_AntB_8 0xb78 +#define rPdp_AntB_C 0xb7c +#define rPdp_AntB_10 0xb80 +#define rPdp_AntB_14 0xb84 +#define rPdp_AntB_18 0xb88 +#define rPdp_AntB_1C 0xb8c +#define rPdp_AntB_20 0xb90 +#define rPdp_AntB_24 0xb94 + +#define rConfig_Pmpd_AntB 0xb98 + +#define rBndB 0xba0 + +#define rAPK 0xbd8 +#define rPm_Rx0_AntA 0xbdc +#define rPm_Rx1_AntA 0xbe0 +#define rPm_Rx2_AntA 0xbe4 +#define rPm_Rx3_AntA 0xbe8 +#define rPm_Rx0_AntB 0xbec +#define rPm_Rx1_AntB 0xbf0 +#define rPm_Rx2_AntB 0xbf4 +#define rPm_Rx3_AntB 0xbf8 +/* + * 6. PageC(0xC00) + * */ +#define rOFDM0_LSTF 0xc00 + +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c + +#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ +#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c + +#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD // DM tune init gain */ +#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ +#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ +#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ + +#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ +#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ +#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ +#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ + +#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c + +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c + +#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c + +#define rOFDM0_RxIQExtAnta 0xca0 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 + +/* + * 7. PageD(0xD00) + * */ +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 + +#define rOFDM1_CFO 0xd08 /* No setting now */ +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 + +#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ +#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ +#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ + +#define rOFDM_ShortCFOAB 0xdac /* No setting now */ +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + + +/* + * 8. PageE(0xE00) + * */ +#define rTxAGC_A_Rate18_06 0xe00 +#define rTxAGC_A_Rate54_24 0xe04 +#define rTxAGC_A_CCK1_Mcs32 0xe08 +#define rTxAGC_A_Mcs03_Mcs00 0xe10 +#define rTxAGC_A_Mcs07_Mcs04 0xe14 +#define rTxAGC_A_Mcs11_Mcs08 0xe18 +#define rTxAGC_A_Mcs15_Mcs12 0xe1c + +#define rFPGA0_IQK 0xe28 +#define rTx_IQK_Tone_A 0xe30 +#define rRx_IQK_Tone_A 0xe34 +#define rTx_IQK_PI_A 0xe38 +#define rRx_IQK_PI_A 0xe3c + +#define rTx_IQK 0xe40 +#define rRx_IQK 0xe44 +#define rIQK_AGC_Pts 0xe48 +#define rIQK_AGC_Rsp 0xe4c +#define rTx_IQK_Tone_B 0xe50 +#define rRx_IQK_Tone_B 0xe54 +#define rTx_IQK_PI_B 0xe58 +#define rRx_IQK_PI_B 0xe5c +#define rIQK_AGC_Cont 0xe60 + +#define rBlue_Tooth 0xe6c +#define rRx_Wait_CCA 0xe70 +#define rTx_CCK_RFON 0xe74 +#define rTx_CCK_BBON 0xe78 +#define rTx_OFDM_RFON 0xe7c +#define rTx_OFDM_BBON 0xe80 +#define rTx_To_Rx 0xe84 +#define rTx_To_Tx 0xe88 +#define rRx_CCK 0xe8c + +#define rTx_Power_Before_IQK_A 0xe94 +#define rTx_Power_After_IQK_A 0xe9c + +#define rRx_Power_Before_IQK_A 0xea0 +#define rRx_Power_Before_IQK_A_2 0xea4 +#define rRx_Power_After_IQK_A 0xea8 +#define rRx_Power_After_IQK_A_2 0xeac + +#define rTx_Power_Before_IQK_B 0xeb4 +#define rTx_Power_After_IQK_B 0xebc + +#define rRx_Power_Before_IQK_B 0xec0 +#define rRx_Power_Before_IQK_B_2 0xec4 +#define rRx_Power_After_IQK_B 0xec8 +#define rRx_Power_After_IQK_B_2 0xecc + +#define rRx_OFDM 0xed0 +#define rRx_Wait_RIFS 0xed4 +#define rRx_TO_Rx 0xed8 +#define rStandby 0xedc +#define rSleep 0xee0 +#define rPMPD_ANAEN 0xeec + +/* + * 7. RF Register 0x00-0x2E (RF 8256) + * RF-0222D 0x00-3F + * + * Zebra1 */ +#define rZebra1_HSSIEnable 0x0 /* Useless now */ +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +#define rZebra1_Channel 0x7 /* RF channel switch */ + +/* #endif */ +#define rZebra1_TxGain 0x8 /* Useless now */ +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +/* Zebra4 */ +#define rGlobalCtrl 0 /* Useless now */ +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +/* RTL8258 */ +#define rRTL8258_TxLPF 0x11 /* Useless now */ +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +/* + * RL6052 Register definition + * */ +#define RF_AC 0x00 /* */ + +#define RF_IQADJ_G1 0x01 /* */ +#define RF_IQADJ_G2 0x02 /* */ +#define RF_BS_PA_APSET_G1_G4 0x03 +#define RF_BS_PA_APSET_G5_G8 0x04 +#define RF_POW_TRSW 0x05 /* */ + +#define RF_GAIN_RX 0x06 /* */ +#define RF_GAIN_TX 0x07 /* */ + +#define RF_TXM_IDAC 0x08 /* */ +#define RF_IPA_G 0x09 /* */ +#define RF_TXBIAS_G 0x0A +#define RF_TXPA_AG 0x0B +#define RF_IPA_A 0x0C /* */ +#define RF_TXBIAS_A 0x0D +#define RF_BS_PA_APSET_G9_G11 0x0E +#define RF_BS_IQGEN 0x0F /* */ + +#define RF_MODE1 0x10 /* */ +#define RF_MODE2 0x11 /* */ + +#define RF_RX_AGC_HP 0x12 /* */ +#define RF_TX_AGC 0x13 /* */ +#define RF_BIAS 0x14 /* */ +#define RF_IPA 0x15 /* */ +#define RF_TXBIAS 0x16 +#define RF_POW_ABILITY 0x17 /* */ +#define RF_MODE_AG 0x18 /* */ +#define rRfChannel 0x18 /* RF channel and BW switch */ +#define RF_CHNLBW 0x18 /* RF channel and BW switch */ +#define RF_TOP 0x19 /* */ + +#define RF_RX_G1 0x1A /* */ +#define RF_RX_G2 0x1B /* */ + +#define RF_RX_BB2 0x1C /* */ +#define RF_RX_BB1 0x1D /* */ + +#define RF_RCK1 0x1E /* */ +#define RF_RCK2 0x1F /* */ + +#define RF_TX_G1 0x20 /* */ +#define RF_TX_G2 0x21 /* */ +#define RF_TX_G3 0x22 /* */ + +#define RF_TX_BB1 0x23 /* */ + +#define RF_T_METER 0x24 /* */ + +#define RF_SYN_G1 0x25 /* RF TX Power control */ +#define RF_SYN_G2 0x26 /* RF TX Power control */ +#define RF_SYN_G3 0x27 /* RF TX Power control */ +#define RF_SYN_G4 0x28 /* RF TX Power control */ +#define RF_SYN_G5 0x29 /* RF TX Power control */ +#define RF_SYN_G6 0x2A /* RF TX Power control */ +#define RF_SYN_G7 0x2B /* RF TX Power control */ +#define RF_SYN_G8 0x2C /* RF TX Power control */ + +#define RF_RCK_OS 0x30 /* RF TX PA control */ + +#define RF_TXPA_G1 0x31 /* RF TX PA control */ +#define RF_TXPA_G2 0x32 /* RF TX PA control */ +#define RF_TXPA_G3 0x33 /* RF TX PA control */ +#define RF_TX_BIAS_A 0x35 +#define RF_TX_BIAS_D 0x36 +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C /* */ +#define RF_TRSW 0x3F + +#define RF_TXRF_A2 0x41 +#define RF_T_METER_88E 0x42 +#define RF_TXPA_G4 0x46 +#define RF_TXPA_A4 0x4B +#define RF_0x52 0x52 +#define RF_WE_LUT 0xEF +#define RF_S0S1 0xB0 + +/* + * Bit Mask + * + * 1. Page1(0x100) */ +#define bBBResetB 0x100 /* Useless now? */ +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) +#define RF_TX_GAIN_OFFSET_8192F(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0)) + +/* 2. Page8(0x800) */ +#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 + +#define bOFDMRxADCPhase 0x10000 /* Useless now */ +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f + +#define bAntennaSelect 0x0300 + +#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 + +#define bPAStart 0xf0000000 /* Useless now */ +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf /* Reg0x814 */ +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 /* T2R */ +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 /* chane gain at continue Tx */ +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 + +#define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ +#define b3WireAddressLength 0x400 + +#define b3WireRFPowerDown 0x1 /* Useless now + * #define bHWSISelect 0x8 */ +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf + +#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ + +#define bRFSI_TRSW 0x20 /* Useless now */ +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 + +#define bLSSIReadAddress 0x7f800000 /* T65 RF */ + +#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ + +#define bLSSIReadBackData 0xfffff /* T65 RF */ + +#define bLSSIReadOKFlag 0x1000 /* Useless now */ +#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 + +#define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ + +#define b80MClkDelay 0x18000000 /* Useless */ +#define bAFEWatchDogEnable 0x20000000 + +#define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bXtalCap 0x0f000000 + +#define bIntDifClkEnable 0x400 /* Useless */ +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 +#define bCCKRxAGCFormat 0x200 +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +/* 3. Page9(0x900) */ +#define bOFDMTxSC 0x30000000 /* Useless */ +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ +#define bDebugItem 0xff /* reset debug page and LWord */ +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +/* 4. PageA(0xA00) */ +#define bCCKBBMode 0x3 /* Useless */ +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 + +#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ + +#define bCCKScramble 0x8 /* Useless */ +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ +#define bCCKFixedRxAGC 0x8000 +/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +/* 5. PageC(0xC00) */ +#define bNumOfSTF 0x3 /* Useless */ +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 /* the threshold for high power */ +#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +/* #define bRxMF_Hold 0x3800 */ +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 +#define bDAFormat 0x40000 +#define bTxChEmuEnable 0x01000000 +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 +#define bExtLNAGain 0x7c00 + +/* 6. PageE(0xE00) */ +#define bSTBCEn 0x4 /* Useless */ +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +/* #define bRxPath1 0x01 */ +/* #define bRxPath2 0x02 */ +/* #define bRxPath3 0x04 */ +/* #define bRxPath4 0x08 */ +/* #define bTxPath1 0x10 */ +/* #define bTxPath2 0x20 */ +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 /* total */ +#define bShortCFOFLength 11 /* fraction */ +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf /* Useless */ +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 /* Useless */ +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 /* Useless */ +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +/* Rx Pseduo noise */ +#define bRxPesudoNoiseOn 0x20000000 /* Useless */ +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +/* 7. RF Register + * Zebra1 */ +#define bZebra1_HSSIEnable 0x8 /* Useless */ +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +/* Zebra4 */ +#define bRTL8256RegModeCtrl1 0x100 /* Useless */ +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +/* RTL8258 */ +#define bRTL8258_TxLPFBW 0xc /* Useless */ +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + + +/* + * Other Definition + * */ + +/* byte endable for sb_write */ +#define bByte0 0x1 /* Useless */ +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +/* for PutRegsetting & GetRegSetting BitMask */ +#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff +#define bMaskH3Bytes 0xffffff00 +#define bMask12Bits 0xfff +#define bMaskH4Bits 0xf0000000 +#define bMaskOFDM_D 0xffc00000 +#define bMaskCCK 0x3f3f3f3f + + +#define bEnable 0x1 /* Useless */ +#define bDisable 0x0 + +#define LeftAntenna 0x0 /* Useless */ +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 /* 500ms // Useless */ +#define tUpdateRxCounter 100 /* 100ms */ + +#define rateCCK 0 /* Useless */ +#define rateOFDM 1 +#define rateHT 2 + +/* define Register-End */ +#define bPMAC_End 0x1ff /* Useless */ +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + +/* define max debug item in each debug page + * #define bMaxItem_FPGA_PHY0 0x9 + * #define bMaxItem_FPGA_PHY1 0x3 + * #define bMaxItem_PHY_11B 0x16 + * #define bMaxItem_OFDM_PHY0 0x29 + * #define bMaxItem_OFDM_PHY1 0x0 */ + +#define bPMACControl 0x0 /* Useless */ +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#define PathA 0x0 /* Useless */ +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +#endif diff --git a/include/Hal8192FPwrSeq.h b/include/Hal8192FPwrSeq.h new file mode 100644 index 0000000..91f1256 --- /dev/null +++ b/include/Hal8192FPwrSeq.h @@ -0,0 +1,221 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef REALTEK_POWER_SEQUENCE_8192F +#define REALTEK_POWER_SEQUENCE_8192F +#define POWER_SEQUENCE_8192F_VER 02 +/* #include "PwrSeqCmd.h" */ +#include "HalPwrSeqCmd.h" + +/* + Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transition from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS 38 +#define RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS 9 +#define RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS 7 +#define RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS 5 +#define RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS 8 +#define RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS 8 +#define RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS 4 +#define RTL8192F_TRANS_PDN_TO_CARDEMU_STEPS 1 +#define RTL8192F_TRANS_ACT_TO_LPS_STEPS 13 +#define RTL8192F_TRANS_LPS_TO_ACT_STEPS 11 +#define RTL8192F_TRANS_END_STEPS 1 + + +#define RTL8192F_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ + {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ + {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \ + {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ + {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, (BIT1|BIT0), 0}, \ + {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* SWR OCP enable 0x10[18]=1*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \ + {0x007f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x7c[31]=1,LDO has max output capability*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \ + {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\ + {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 data mode*/\ + {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\ + {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\ + {0x0068, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/*RF HW ON/OFF Enable*/\ + {0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/*Register Lock Disable*/\ + {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\ + {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\ + {0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\ + {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\ + {0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\ + {0x0097, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*AFE_Ctrl*/\ + {0x00DC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xCC},/*AFE_Ctrl*/\ + {0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x18, 0x00},/*AFE_Ctrl 0x24[4:3]=00 for xtal gmn*/\ + {0x1050, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[7:0] Pull down software register*/\ + {0x1051, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[15:8] Pull down software register*/\ + {0x1052, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[23:16] Pull down software register*/\ + {0x1053, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[31:24] Pull down software register*/\ + {0x105B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_B[7:0] Pull down software register*/\ + {0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*Register Lock Enable*/\ + {0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT7|BIT6), 0x3},/*set HCI Power sequence state delay time:0*/ + + +#define RTL8192F_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + /*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x2[0]=0 Reset BB,RF enter Power Down mode*/ \ + {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \ + {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x10[18] = 0 to disable ocp*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ + {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\ + {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\ + + +#define RTL8192F_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 USB|SDIO SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8192F_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + + +#define RTL8192F_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/ \ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8192F_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ + {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x10[18] = 1 to enable ocp*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ + + +#define RTL8192F_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8192F_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +#define RTL8192F_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ + + +#define RTL8192F_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8192F_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8192F_power_on_flow[RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192F_radio_off_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192F_card_disable_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS+RTL8192F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192F_card_enable_flow[RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192F_suspend_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192F_resume_flow[RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192F_hwpdn_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192F_enter_lps_flow[RTL8192F_TRANS_ACT_TO_LPS_STEPS+RTL8192F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8192F_leave_lps_flow[RTL8192F_TRANS_LPS_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS]; + +#endif diff --git a/include/Hal8703BPhyCfg.h b/include/Hal8703BPhyCfg.h index a038bcc..f5b995c 100644 --- a/include/Hal8703BPhyCfg.h +++ b/include/Hal8703BPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8703BPHYCFG_H__ #define __INC_HAL8703BPHYCFG_H__ @@ -59,16 +54,16 @@ PHY_SetBBReg_8703B( u32 PHY_QueryRFReg_8703B( - IN PADAPTER Adapter, - IN u8 eRFPath, + IN PADAPTER Adapter, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask ); VOID PHY_SetRFReg_8703B( - IN PADAPTER Adapter, - IN u8 eRFPath, + IN PADAPTER Adapter, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask, IN u32 Data @@ -84,22 +79,22 @@ s32 PHY_MACConfig8703B(PADAPTER padapter); int PHY_ConfigRFWithParaFile_8703B( IN PADAPTER Adapter, - IN u8 *pFileName, - RF_PATH eRFPath + IN u8 *pFileName, + enum rf_path eRFPath ); VOID PHY_SetTxPowerIndex_8703B( IN PADAPTER Adapter, IN u32 PowerIndex, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ); u8 PHY_GetTxPowerIndex_8703B( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, IN u8 BandWidth, IN u8 Channel, @@ -122,13 +117,13 @@ VOID PHY_SetSwChnlBWMode8703B( IN PADAPTER Adapter, IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, + IN enum channel_width Bandwidth, IN u8 Offset40, IN u8 Offset80 ); VOID phy_set_rf_path_switch_8703b( - IN PADAPTER pAdapter, + IN struct dm_struct *phydm, IN bool bMain ); diff --git a/include/Hal8703BPhyReg.h b/include/Hal8703BPhyReg.h index e8eb664..881a13c 100644 --- a/include/Hal8703BPhyReg.h +++ b/include/Hal8703BPhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8703BPHYREG_H__ #define __INC_HAL8703BPHYREG_H__ diff --git a/include/Hal8703BPwrSeq.h b/include/Hal8703BPwrSeq.h index a53ca9a..0dac13e 100644 --- a/include/Hal8703BPwrSeq.h +++ b/include/Hal8703BPwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8703B #define REALTEK_POWER_SEQUENCE_8703B diff --git a/include/Hal8710BPhyCfg.h b/include/Hal8710BPhyCfg.h new file mode 100644 index 0000000..4d72f7a --- /dev/null +++ b/include/Hal8710BPhyCfg.h @@ -0,0 +1,127 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __INC_HAL8710BPHYCFG_H__ +#define __INC_HAL8710BPHYCFG_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define LOOP_LIMIT 5 +#define MAX_STALL_TIME 50 /* us */ +#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ +#define MAX_TXPWR_IDX_NMODE_92S 63 +#define Reset_Cnt_Limit 3 + +#ifdef CONFIG_PCI_HCI + #define MAX_AGGR_NUM 0x0B +#else + #define MAX_AGGR_NUM 0x07 +#endif /* CONFIG_PCI_HCI */ + + +/*--------------------------Define Parameters End-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ + +/*------------------------------Define structure End----------------------------*/ + +/*--------------------------Exported Function prototype---------------------*/ +u32 +PHY_QueryBBReg_8710B( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask +); + +VOID +PHY_SetBBReg_8710B( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +); + +u32 +PHY_QueryRFReg_8710B( + IN PADAPTER Adapter, + IN enum rf_path eRFPath, + IN u32 RegAddr, + IN u32 BitMask +); + +VOID +PHY_SetRFReg_8710B( + IN PADAPTER Adapter, + IN enum rf_path eRFPath, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +); + +/* MAC/BB/RF HAL config */ +int PHY_BBConfig8710B(PADAPTER Adapter); + +int PHY_RFConfig8710B(PADAPTER Adapter); + +s32 PHY_MACConfig8710B(PADAPTER padapter); + +int +PHY_ConfigRFWithParaFile_8710B( + IN PADAPTER Adapter, + IN u8 *pFileName, + enum rf_path eRFPath +); + +VOID +PHY_SetTxPowerIndex_8710B( + IN PADAPTER Adapter, + IN u32 PowerIndex, + IN enum rf_path RFPath, + IN u8 Rate +); + +u8 +PHY_GetTxPowerIndex_8710B( + IN PADAPTER pAdapter, + IN enum rf_path RFPath, + IN u8 Rate, + IN u8 BandWidth, + IN u8 Channel, + struct txpwr_idx_comp *tic +); + +VOID +PHY_GetTxPowerLevel8710B( + IN PADAPTER Adapter, + OUT s32 *powerlevel +); + +VOID +PHY_SetTxPowerLevel8710B( + IN PADAPTER Adapter, + IN u8 channel +); + +VOID +PHY_SetSwChnlBWMode8710B( + IN PADAPTER Adapter, + IN u8 channel, + IN enum channel_width Bandwidth, + IN u8 Offset40, + IN u8 Offset80 +); + +/*--------------------------Exported Function prototype End---------------------*/ + +#endif diff --git a/include/Hal8710BPhyReg.h b/include/Hal8710BPhyReg.h new file mode 100644 index 0000000..337e032 --- /dev/null +++ b/include/Hal8710BPhyReg.h @@ -0,0 +1,1134 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __INC_HAL8710BPHYREG_H__ +#define __INC_HAL8710BPHYREG_H__ + +#define rSYM_WLBT_PAPE_SEL 0x64 +/* + * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF + * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF + * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 + * 3. RF register 0x00-2E + * 4. Bit Mask for BB/RF register + * 5. Other definition for BB/RF R/W + * */ + + +/* + * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF + * 1. Page1(0x100) + * */ +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +/* + * 2. Page2(0x200) + * + * The following two definition are only used for USB interface. */ +#define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ +#define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ + +/* + * 3. Page8(0x800) + * */ +#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC // RF BW Setting?? */ + +#define rFPGA0_TxInfo 0x804 /* Status report?? */ +#define rFPGA0_PSDFunction 0x808 + +#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ + +#define rFPGA0_RFTiming1 0x810 /* Useless now */ +#define rFPGA0_RFTiming2 0x814 + +#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rTxAGC_B_Rate18_06 0x830 +#define rTxAGC_B_Rate54_24 0x834 +#define rTxAGC_B_CCK1_55_Mcs32 0x838 +#define rTxAGC_B_Mcs03_Mcs00 0x83c + +#define rTxAGC_B_Mcs07_Mcs04 0x848 +#define rTxAGC_B_Mcs11_Mcs08 0x84c + +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 + +#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ +#define rFPGA0_RFSleepUpParameter 0x854 + +#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ +#define rFPGA0_XCD_SwitchControl 0x85c + +#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ +#define rFPGA0_XB_RFInterfaceOE 0x864 + +#define rTxAGC_B_Mcs15_Mcs12 0x868 +#define rTxAGC_B_CCK11_A_CCK2_11 0x86c + +#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ +#define rFPGA0_XCD_RFInterfaceSW 0x874 + +#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ +#define rFPGA0_XCD_RFParameter 0x87c + +#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 /* Useless now */ +#define rFPGA0_AnalogParameter4 0x88c + +#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac + +#define rFPGA0_PSDReport 0x8b4 /* Useless now */ +#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ +#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now // RF Interface Readback Value */ +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ + +/* + * 4. Page9(0x900) + * */ +#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC // RF BW Setting?? */ +#define rFPGA1_TxBlock 0x904 /* Useless now */ +#define rFPGA1_DebugSelect 0x908 /* Useless now */ +#define rFPGA1_TxInfo 0x90c /* Useless now // Status report?? */ +#define rDPDT_control 0x92c +#define rfe_ctrl_anta_src 0x930 +#define rS0S1_PathSwitch 0x948 +#define rBBrx_DFIR 0x954 + +/* + * 5. PageA(0xA00) + * + * Set Control channel to upper or lower. These settings are required only for 40MHz */ +#define rCCK0_System 0xa00 + +#define rCCK0_AFESetting 0xa04 /* Disable init gain now // Select RX path by RSSI */ +#define rCCK0_CCA 0xa08 /* Disable init gain now // Init gain */ + +#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ +#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ + +#define rCCK0_RxHP 0xa14 + +#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ +#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ + +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ +#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 /* 0xa57 */ +#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ +#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ + +/* + * PageB(0xB00) + * */ +#define rPdp_AntA 0xb00 +#define rPdp_AntA_4 0xb04 +#define rPdp_AntA_8 0xb08 +#define rPdp_AntA_C 0xb0c +#define rPdp_AntA_10 0xb10 +#define rPdp_AntA_14 0xb14 +#define rPdp_AntA_18 0xb18 +#define rPdp_AntA_1C 0xb1c +#define rPdp_AntA_20 0xb20 +#define rPdp_AntA_24 0xb24 + +#define rConfig_Pmpd_AntA 0xb28 +#define rConfig_ram64x16 0xb2c + +#define rBndA 0xb30 +#define rHssiPar 0xb34 + +#define rConfig_AntA 0xb68 +#define rConfig_AntB 0xb6c + +#define rPdp_AntB 0xb70 +#define rPdp_AntB_4 0xb74 +#define rPdp_AntB_8 0xb78 +#define rPdp_AntB_C 0xb7c +#define rPdp_AntB_10 0xb80 +#define rPdp_AntB_14 0xb84 +#define rPdp_AntB_18 0xb88 +#define rPdp_AntB_1C 0xb8c +#define rPdp_AntB_20 0xb90 +#define rPdp_AntB_24 0xb94 + +#define rConfig_Pmpd_AntB 0xb98 + +#define rBndB 0xba0 + +#define rAPK 0xbd8 +#define rPm_Rx0_AntA 0xbdc +#define rPm_Rx1_AntA 0xbe0 +#define rPm_Rx2_AntA 0xbe4 +#define rPm_Rx3_AntA 0xbe8 +#define rPm_Rx0_AntB 0xbec +#define rPm_Rx1_AntB 0xbf0 +#define rPm_Rx2_AntB 0xbf4 +#define rPm_Rx3_AntB 0xbf8 +/* + * 6. PageC(0xC00) + * */ +#define rOFDM0_LSTF 0xc00 + +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c + +#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ +#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c + +#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD // DM tune init gain */ +#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ +#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ +#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ + +#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ +#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ +#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ +#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ + +#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c + +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c + +#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c + +#define rOFDM0_RxIQExtAnta 0xca0 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 + +/* + * 7. PageD(0xD00) + * */ +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 + +#define rOFDM1_CFO 0xd08 /* No setting now */ +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 + +#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ +#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ +#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ + +#define rOFDM_ShortCFOAB 0xdac /* No setting now */ +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + + +/* + * 8. PageE(0xE00) + * */ +#define rTxAGC_A_Rate18_06 0xe00 +#define rTxAGC_A_Rate54_24 0xe04 +#define rTxAGC_A_CCK1_Mcs32 0xe08 +#define rTxAGC_A_Mcs03_Mcs00 0xe10 +#define rTxAGC_A_Mcs07_Mcs04 0xe14 +#define rTxAGC_A_Mcs11_Mcs08 0xe18 +#define rTxAGC_A_Mcs15_Mcs12 0xe1c + +#define rFPGA0_IQK 0xe28 +#define rTx_IQK_Tone_A 0xe30 +#define rRx_IQK_Tone_A 0xe34 +#define rTx_IQK_PI_A 0xe38 +#define rRx_IQK_PI_A 0xe3c + +#define rTx_IQK 0xe40 +#define rRx_IQK 0xe44 +#define rIQK_AGC_Pts 0xe48 +#define rIQK_AGC_Rsp 0xe4c +#define rTx_IQK_Tone_B 0xe50 +#define rRx_IQK_Tone_B 0xe54 +#define rTx_IQK_PI_B 0xe58 +#define rRx_IQK_PI_B 0xe5c +#define rIQK_AGC_Cont 0xe60 + +#define rBlue_Tooth 0xe6c +#define rRx_Wait_CCA 0xe70 +#define rTx_CCK_RFON 0xe74 +#define rTx_CCK_BBON 0xe78 +#define rTx_OFDM_RFON 0xe7c +#define rTx_OFDM_BBON 0xe80 +#define rTx_To_Rx 0xe84 +#define rTx_To_Tx 0xe88 +#define rRx_CCK 0xe8c + +#define rTx_Power_Before_IQK_A 0xe94 +#define rTx_Power_After_IQK_A 0xe9c + +#define rRx_Power_Before_IQK_A 0xea0 +#define rRx_Power_Before_IQK_A_2 0xea4 +#define rRx_Power_After_IQK_A 0xea8 +#define rRx_Power_After_IQK_A_2 0xeac + +#define rTx_Power_Before_IQK_B 0xeb4 +#define rTx_Power_After_IQK_B 0xebc + +#define rRx_Power_Before_IQK_B 0xec0 +#define rRx_Power_Before_IQK_B_2 0xec4 +#define rRx_Power_After_IQK_B 0xec8 +#define rRx_Power_After_IQK_B_2 0xecc + +#define rRx_OFDM 0xed0 +#define rRx_Wait_RIFS 0xed4 +#define rRx_TO_Rx 0xed8 +#define rStandby 0xedc +#define rSleep 0xee0 +#define rPMPD_ANAEN 0xeec + +/* + * 7. RF Register 0x00-0x2E (RF 8256) + * RF-0222D 0x00-3F + * + * Zebra1 */ +#define rZebra1_HSSIEnable 0x0 /* Useless now */ +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +#define rZebra1_Channel 0x7 /* RF channel switch */ + +/* #endif */ +#define rZebra1_TxGain 0x8 /* Useless now */ +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +/* Zebra4 */ +#define rGlobalCtrl 0 /* Useless now */ +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +/* RTL8258 */ +#define rRTL8258_TxLPF 0x11 /* Useless now */ +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +/* + * RL6052 Register definition + * */ +#define RF_AC 0x00 /* */ + +#define RF_IQADJ_G1 0x01 /* */ +#define RF_IQADJ_G2 0x02 /* */ +#define RF_BS_PA_APSET_G1_G4 0x03 +#define RF_BS_PA_APSET_G5_G8 0x04 +#define RF_POW_TRSW 0x05 /* */ + +#define RF_GAIN_RX 0x06 /* */ +#define RF_GAIN_TX 0x07 /* */ + +#define RF_TXM_IDAC 0x08 /* */ +#define RF_IPA_G 0x09 /* */ +#define RF_TXBIAS_G 0x0A +#define RF_TXPA_AG 0x0B +#define RF_IPA_A 0x0C /* */ +#define RF_TXBIAS_A 0x0D +#define RF_BS_PA_APSET_G9_G11 0x0E +#define RF_BS_IQGEN 0x0F /* */ + +#define RF_MODE1 0x10 /* */ +#define RF_MODE2 0x11 /* */ + +#define RF_RX_AGC_HP 0x12 /* */ +#define RF_TX_AGC 0x13 /* */ +#define RF_BIAS 0x14 /* */ +#define RF_IPA 0x15 /* */ +#define RF_TXBIAS 0x16 +#define RF_POW_ABILITY 0x17 /* */ +#define RF_MODE_AG 0x18 /* */ +#define rRfChannel 0x18 /* RF channel and BW switch */ +#define RF_CHNLBW 0x18 /* RF channel and BW switch */ +#define RF_TOP 0x19 /* */ + +#define RF_RX_G1 0x1A /* */ +#define RF_RX_G2 0x1B /* */ + +#define RF_RX_BB2 0x1C /* */ +#define RF_RX_BB1 0x1D /* */ + +#define RF_RCK1 0x1E /* */ +#define RF_RCK2 0x1F /* */ + +#define RF_TX_G1 0x20 /* */ +#define RF_TX_G2 0x21 /* */ +#define RF_TX_G3 0x22 /* */ + +#define RF_TX_BB1 0x23 /* */ + +#define RF_T_METER 0x24 /* */ + +#define RF_SYN_G1 0x25 /* RF TX Power control */ +#define RF_SYN_G2 0x26 /* RF TX Power control */ +#define RF_SYN_G3 0x27 /* RF TX Power control */ +#define RF_SYN_G4 0x28 /* RF TX Power control */ +#define RF_SYN_G5 0x29 /* RF TX Power control */ +#define RF_SYN_G6 0x2A /* RF TX Power control */ +#define RF_SYN_G7 0x2B /* RF TX Power control */ +#define RF_SYN_G8 0x2C /* RF TX Power control */ + +#define RF_RCK_OS 0x30 /* RF TX PA control */ + +#define RF_TXPA_G1 0x31 /* RF TX PA control */ +#define RF_TXPA_G2 0x32 /* RF TX PA control */ +#define RF_TXPA_G3 0x33 /* RF TX PA control */ +#define RF_TX_BIAS_A 0x35 +#define RF_TX_BIAS_D 0x36 +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C /* */ +#define RF_TRSW 0x3F + +#define RF_TXRF_A2 0x41 +#define RF_T_METER_88E 0x42 +#define RF_TXPA_G4 0x46 +#define RF_TXPA_A4 0x4B +#define RF_0x52 0x52 +#define RF_WE_LUT 0xEF +#define RF_S0S1 0xB0 + +/* + * Bit Mask + * + * 1. Page1(0x100) */ +#define bBBResetB 0x100 /* Useless now? */ +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) +#define RF_TX_GAIN_OFFSET_8710B(_val) (abs((_val)) | (((_val) > 0) ? BIT(4) : 0)) + +/* 2. Page8(0x800) */ +#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 + +#define bOFDMRxADCPhase 0x10000 /* Useless now */ +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f + +#define bAntennaSelect 0x0300 + +#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 + +#define bPAStart 0xf0000000 /* Useless now */ +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf /* Reg0x814 */ +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 /* T2R */ +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 /* chane gain at continue Tx */ +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 + +#define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ +#define b3WireAddressLength 0x400 + +#define b3WireRFPowerDown 0x1 /* Useless now + * #define bHWSISelect 0x8 */ +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf + +#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ + +#define bRFSI_TRSW 0x20 /* Useless now */ +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 + +#define bLSSIReadAddress 0x7f800000 /* T65 RF */ + +#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ + +#define bLSSIReadBackData 0xfffff /* T65 RF */ + +#define bLSSIReadOKFlag 0x1000 /* Useless now */ +#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 + +#define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ + +#define b80MClkDelay 0x18000000 /* Useless */ +#define bAFEWatchDogEnable 0x20000000 + +#define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bXtalCap 0x0f000000 + +#define bIntDifClkEnable 0x400 /* Useless */ +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 +#define bCCKRxAGCFormat 0x200 +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +/* 3. Page9(0x900) */ +#define bOFDMTxSC 0x30000000 /* Useless */ +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ +#define bDebugItem 0xff /* reset debug page and LWord */ +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +/* 4. PageA(0xA00) */ +#define bCCKBBMode 0x3 /* Useless */ +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 + +#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ + +#define bCCKScramble 0x8 /* Useless */ +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ +#define bCCKFixedRxAGC 0x8000 +/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +/* 5. PageC(0xC00) */ +#define bNumOfSTF 0x3 /* Useless */ +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 /* the threshold for high power */ +#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +/* #define bRxMF_Hold 0x3800 */ +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 +#define bDAFormat 0x40000 +#define bTxChEmuEnable 0x01000000 +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 +#define bExtLNAGain 0x7c00 + +/* 6. PageE(0xE00) */ +#define bSTBCEn 0x4 /* Useless */ +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +/* #define bRxPath1 0x01 */ +/* #define bRxPath2 0x02 */ +/* #define bRxPath3 0x04 */ +/* #define bRxPath4 0x08 */ +/* #define bTxPath1 0x10 */ +/* #define bTxPath2 0x20 */ +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 /* total */ +#define bShortCFOFLength 11 /* fraction */ +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf /* Useless */ +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 /* Useless */ +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 /* Useless */ +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +/* Rx Pseduo noise */ +#define bRxPesudoNoiseOn 0x20000000 /* Useless */ +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +/* 7. RF Register + * Zebra1 */ +#define bZebra1_HSSIEnable 0x8 /* Useless */ +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +/* Zebra4 */ +#define bRTL8256RegModeCtrl1 0x100 /* Useless */ +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +/* RTL8258 */ +#define bRTL8258_TxLPFBW 0xc /* Useless */ +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + + +/* + * Other Definition + * */ + +/* byte endable for sb_write */ +#define bByte0 0x1 /* Useless */ +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +/* for PutRegsetting & GetRegSetting BitMask */ +#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff +#define bMaskH3Bytes 0xffffff00 +#define bMask12Bits 0xfff +#define bMaskH4Bits 0xf0000000 +#define bMaskOFDM_D 0xffc00000 +#define bMaskCCK 0x3f3f3f3f + + +#define bEnable 0x1 /* Useless */ +#define bDisable 0x0 + +#define LeftAntenna 0x0 /* Useless */ +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 /* 500ms // Useless */ +#define tUpdateRxCounter 100 /* 100ms */ + +#define rateCCK 0 /* Useless */ +#define rateOFDM 1 +#define rateHT 2 + +/* define Register-End */ +#define bPMAC_End 0x1ff /* Useless */ +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + +/* define max debug item in each debug page + * #define bMaxItem_FPGA_PHY0 0x9 + * #define bMaxItem_FPGA_PHY1 0x3 + * #define bMaxItem_PHY_11B 0x16 + * #define bMaxItem_OFDM_PHY0 0x29 + * #define bMaxItem_OFDM_PHY1 0x0 */ + +#define bPMACControl 0x0 /* Useless */ +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#define PathA 0x0 /* Useless */ +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +#endif diff --git a/include/Hal8710BPwrSeq.h b/include/Hal8710BPwrSeq.h new file mode 100644 index 0000000..31ad29c --- /dev/null +++ b/include/Hal8710BPwrSeq.h @@ -0,0 +1,167 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef REALTEK_POWER_SEQUENCE_8710B +#define REALTEK_POWER_SEQUENCE_8710B + +/* #include "PwrSeqCmd.h" */ +#include "HalPwrSeqCmd.h" + +/* + Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transition from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS 5 +#define RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS 4 +#define RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS 7 +#define RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS 15 +#define RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS 15 +#define RTL8710B_TRANS_PDN_TO_CARDEMU_STEPS 15 +#define RTL8710B_TRANS_ACT_TO_LPS_STEPS 15 +#define RTL8710B_TRANS_LPS_TO_ACT_STEPS 15 +#define RTL8710B_TRANS_ACT_TO_SWLPS_STEPS 22 +#define RTL8710B_TRANS_SWLPS_TO_ACT_STEPS 15 +#define RTL8710B_TRANS_END_STEPS 1 + + +#define RTL8710B_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x005D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*AFE power mode selection:1: LDO mode ,0: Power-cut mode*/\ + {0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\ + {0x0056, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x0E},\ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ + + +#define RTL8710B_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + /*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1|BIT2), 0},/*0x04[24:26] = 0 turn off RF*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1), 0},/*0x04[16:17] = 0 BB reset*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x20[1] = 1 turn off MAC by HW state machine*/ \ + {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x20[1] = 0 polling until return 0 to disable*/ \ + + +#define RTL8710B_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ + +#define RTL8710B_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + + +#define RTL8710B_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + +#define RTL8710B_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + + +#define RTL8710B_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8710B_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +#define RTL8710B_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ + + +#define RTL8710B_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8710B_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8710B_power_on_flow[RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8710B_radio_off_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8710B_card_disable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8710B_card_enable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8710B_suspend_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8710B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8710B_resume_flow[RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8710B_hwpdn_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8710B_enter_lps_flow[RTL8710B_TRANS_ACT_TO_LPS_STEPS+RTL8710B_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8710B_leave_lps_flow[RTL8710B_TRANS_LPS_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS]; + +#endif diff --git a/include/Hal8723BPhyCfg.h b/include/Hal8723BPhyCfg.h index 0fa8964..18c0a78 100644 --- a/include/Hal8723BPhyCfg.h +++ b/include/Hal8723BPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8723BPHYCFG_H__ #define __INC_HAL8723BPHYCFG_H__ @@ -60,7 +55,7 @@ PHY_SetBBReg_8723B( u32 PHY_QueryRFReg_8723B( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask ); @@ -68,7 +63,7 @@ PHY_QueryRFReg_8723B( VOID PHY_SetRFReg_8723B( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask, IN u32 Data @@ -84,22 +79,22 @@ s32 PHY_MACConfig8723B(PADAPTER padapter); int PHY_ConfigRFWithParaFile_8723B( IN PADAPTER Adapter, - IN u8 *pFileName, - RF_PATH eRFPath + IN u8 *pFileName, + enum rf_path eRFPath ); VOID PHY_SetTxPowerIndex_8723B( IN PADAPTER Adapter, IN u32 PowerIndex, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ); u8 PHY_GetTxPowerIndex_8723B( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, IN u8 BandWidth, IN u8 Channel, @@ -122,13 +117,13 @@ VOID PHY_SetSwChnlBWMode8723B( IN PADAPTER Adapter, IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, + IN enum channel_width Bandwidth, IN u8 Offset40, IN u8 Offset80 ); VOID phy_set_rf_path_switch_8723b( - IN PADAPTER pAdapter, + IN struct dm_struct *phydm, IN bool bMain ); diff --git a/include/Hal8723BPhyReg.h b/include/Hal8723BPhyReg.h index 551c0a5..ce485c2 100644 --- a/include/Hal8723BPhyReg.h +++ b/include/Hal8723BPhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8723BPHYREG_H__ #define __INC_HAL8723BPHYREG_H__ diff --git a/include/Hal8723BPwrSeq.h b/include/Hal8723BPwrSeq.h index 6b89562..1aec885 100644 --- a/include/Hal8723BPwrSeq.h +++ b/include/Hal8723BPwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8723B #define REALTEK_POWER_SEQUENCE_8723B diff --git a/include/Hal8723DPhyCfg.h b/include/Hal8723DPhyCfg.h index f3ce170..8dd4819 100644 --- a/include/Hal8723DPhyCfg.h +++ b/include/Hal8723DPhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8723DPHYCFG_H__ #define __INC_HAL8723DPHYCFG_H__ @@ -59,16 +54,16 @@ PHY_SetBBReg_8723D( u32 PHY_QueryRFReg_8723D( - IN PADAPTER Adapter, - IN u8 eRFPath, + IN PADAPTER Adapter, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask ); VOID PHY_SetRFReg_8723D( - IN PADAPTER Adapter, - IN u8 eRFPath, + IN PADAPTER Adapter, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask, IN u32 Data @@ -85,21 +80,21 @@ int PHY_ConfigRFWithParaFile_8723D( IN PADAPTER Adapter, IN u8 *pFileName, - RF_PATH eRFPath + enum rf_path eRFPath ); VOID PHY_SetTxPowerIndex_8723D( IN PADAPTER Adapter, IN u32 PowerIndex, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ); u8 PHY_GetTxPowerIndex_8723D( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, IN u8 BandWidth, IN u8 Channel, @@ -122,13 +117,13 @@ VOID PHY_SetSwChnlBWMode8723D( IN PADAPTER Adapter, IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, + IN enum channel_width Bandwidth, IN u8 Offset40, IN u8 Offset80 ); VOID phy_set_rf_path_switch_8723d( - IN PADAPTER pAdapter, + IN struct dm_struct *phydm, IN bool bMain ); /*--------------------------Exported Function prototype End---------------------*/ diff --git a/include/Hal8723DPhyReg.h b/include/Hal8723DPhyReg.h index 9fb0cc1..036144a 100644 --- a/include/Hal8723DPhyReg.h +++ b/include/Hal8723DPhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8723DPHYREG_H__ #define __INC_HAL8723DPHYREG_H__ diff --git a/include/Hal8723DPwrSeq.h b/include/Hal8723DPwrSeq.h index 5032e7c..60cb53b 100644 --- a/include/Hal8723DPwrSeq.h +++ b/include/Hal8723DPwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8723D #define REALTEK_POWER_SEQUENCE_8723D @@ -42,7 +56,6 @@ /* format */ \ /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \ {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \ - {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \ {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \ {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \ diff --git a/include/Hal8723PwrSeq.h b/include/Hal8723PwrSeq.h index 6669641..22de833 100644 --- a/include/Hal8723PwrSeq.h +++ b/include/Hal8723PwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __HAL8723PWRSEQ_H__ #define __HAL8723PWRSEQ_H__ /* diff --git a/include/Hal8812PhyCfg.h b/include/Hal8812PhyCfg.h index 05a5fe2..0d5282a 100644 --- a/include/Hal8812PhyCfg.h +++ b/include/Hal8812PhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8812PHYCFG_H__ #define __INC_HAL8812PHYCFG_H__ @@ -66,11 +61,11 @@ void PHY_SetBBReg8812(IN PADAPTER Adapter, IN u32 BitMask, IN u32 Data); u32 PHY_QueryRFReg8812(IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask); void PHY_SetRFReg8812(IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask, IN u32 Data); @@ -101,7 +96,7 @@ void PHY_SetTxPowerLevel8812(IN PADAPTER Adapter, IN u8 Channel); BOOLEAN PHY_UpdateTxPowerDbm8812(IN PADAPTER Adapter, IN int powerInDbm); u8 PHY_GetTxPowerIndex_8812A( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, IN u8 BandWidth, IN u8 Channel, @@ -111,15 +106,15 @@ u8 PHY_GetTxPowerIndex_8812A( u32 phy_get_tx_bb_swing_8812a( IN PADAPTER Adapter, IN BAND_TYPE Band, - IN u8 RFPath + IN enum rf_path RFPath ); VOID PHY_SetTxPowerIndex_8812A( - IN PADAPTER Adapter, - IN u4Byte PowerIndex, - IN u1Byte RFPath, - IN u1Byte Rate + IN PADAPTER Adapter, + IN u32 PowerIndex, + IN enum rf_path RFPath, + IN u8 Rate ); /* @@ -129,7 +124,7 @@ VOID PHY_SetSwChnlBWMode8812( IN PADAPTER Adapter, IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, + IN enum channel_width Bandwidth, IN u8 Offset40, IN u8 Offset80 ); @@ -140,7 +135,7 @@ PHY_SetSwChnlBWMode8812( VOID phy_set_rf_path_switch_8812a( - IN PADAPTER pAdapter, + IN struct dm_struct *phydm, IN bool bMain ); diff --git a/include/Hal8812PhyReg.h b/include/Hal8812PhyReg.h index 5009750..521ebb2 100644 --- a/include/Hal8812PhyReg.h +++ b/include/Hal8812PhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8812PHYREG_H__ #define __INC_HAL8812PHYREG_H__ /*--------------------------Define Parameters-------------------------------*/ @@ -168,6 +163,8 @@ #define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */ #define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */ #define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */ +#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ +#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ #define bMask_RFEInv_Jaguar 0x3ff00000 #define bMask_AntselPathFollow_Jaguar 0x00030000 diff --git a/include/Hal8812PwrSeq.h b/include/Hal8812PwrSeq.h index e089c1a..498faf8 100644 --- a/include/Hal8812PwrSeq.h +++ b/include/Hal8812PwrSeq.h @@ -1,7 +1,6 @@ - /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,12 +11,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ + #ifndef __HAL8812PWRSEQ_H__ #define __HAL8812PWRSEQ_H__ @@ -64,7 +59,9 @@ /*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, disable HWPDN 0x04[15]=0*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \ - {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \ + {0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x24[1] Choose the type of buffer after xosc: nand*/ \ + {0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /* 0x28[33] Choose the type of buffer after xosc: nand*/ #define RTL8812_TRANS_ACT_TO_CARDEMU \ /* format */ \ @@ -143,7 +140,9 @@ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \ {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \ {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/ \ - {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ + {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ \ + {0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /* 0x24[1] Choose the type of buffer after xosc: schmitt trigger*/ \ + {0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x28[33] Choose the type of buffer after xosc: schmitt trigger*/ #define RTL8812_TRANS_CARDEMU_TO_PDN \ diff --git a/include/Hal8814PhyCfg.h b/include/Hal8814PhyCfg.h index 9aaaf38..96f0794 100644 --- a/include/Hal8814PhyCfg.h +++ b/include/Hal8814PhyCfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8814PHYCFG_H__ #define __INC_HAL8814PHYCFG_H__ @@ -74,14 +69,14 @@ PHY_SetBBReg8814A(IN PADAPTER Adapter, extern u32 PHY_QueryRFReg8814A(IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask); void PHY_SetRFReg8814A(IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 RegAddr, IN u32 BitMask, IN u32 Data); @@ -129,17 +124,17 @@ PHY_SetTxPowerLevel8814( u8 phy_get_tx_power_index_8814a( - IN PADAPTER Adapter, - IN u8 RFPath, + IN PADAPTER Adapter, + IN enum rf_path RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, + IN enum channel_width BandWidth, IN u8 Channel ); u8 PHY_GetTxPowerIndex8814A( - IN PADAPTER Adapter, - IN u8 RFPath, + IN PADAPTER Adapter, + IN enum rf_path RFPath, IN u8 Rate, IN u8 BandWidth, IN u8 Channel, @@ -148,9 +143,9 @@ PHY_GetTxPowerIndex8814A( VOID PHY_SetTxPowerIndex_8814A( - IN PADAPTER Adapter, + IN PADAPTER Adapter, IN u32 PowerIndex, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ); @@ -166,18 +161,18 @@ u32 PHY_GetTxBBSwing_8814A( IN PADAPTER Adapter, IN BAND_TYPE Band, - IN u8 RFPath + IN enum rf_path RFPath ); /* 1 6. Channel setting API */ - +#if 0 VOID PHY_SwChnlTimerCallback8814A( IN struct timer_list *p_timer ); - +#endif VOID PHY_SwChnlWorkItemCallback8814A( IN PVOID pContext @@ -204,7 +199,7 @@ PHY_HandleSwChnlAndSetBW8814A( IN BOOLEAN bSwitchChannel, IN BOOLEAN bSetBandWidth, IN u8 ChannelNum, - IN CHANNEL_WIDTH ChnlWidth, + IN enum channel_width ChnlWidth, IN u8 ChnlOffsetOf40MHz, IN u8 ChnlOffsetOf80MHz, IN u8 CenterFrequencyIndex1 @@ -252,7 +247,7 @@ VOID PHY_SetSwChnlBWMode8814( IN PADAPTER Adapter, IN u8 channel, - IN CHANNEL_WIDTH Bandwidth, + IN enum channel_width Bandwidth, IN u8 Offset40, IN u8 Offset80 ); diff --git a/include/Hal8814PhyReg.h b/include/Hal8814PhyReg.h index 0aec994..21851a8 100644 --- a/include/Hal8814PhyReg.h +++ b/include/Hal8814PhyReg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __INC_HAL8814PHYREG_H__ #define __INC_HAL8814PHYREG_H__ /*--------------------------Define Parameters-------------------------------*/ @@ -202,6 +197,8 @@ #define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */ #define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */ #define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */ +#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ +#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ #define bMask_RFEInv_Jaguar 0x3ff00000 #define bMask_AntselPathFollow_Jaguar 0x00030000 diff --git a/include/Hal8814PwrSeq.h b/include/Hal8814PwrSeq.h index 696959b..5f4097d 100644 --- a/include/Hal8814PwrSeq.h +++ b/include/Hal8814PwrSeq.h @@ -1,7 +1,6 @@ - /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,12 +11,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ + #ifndef __HAL8814PWRSEQ_H__ #define __HAL8814PWRSEQ_H__ diff --git a/include/Hal8821APwrSeq.h b/include/Hal8821APwrSeq.h index 393068b..568b8e5 100644 --- a/include/Hal8821APwrSeq.h +++ b/include/Hal8821APwrSeq.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef REALTEK_POWER_SEQUENCE_8821 #define REALTEK_POWER_SEQUENCE_8821 diff --git a/include/HalPwrSeqCmd.h b/include/HalPwrSeqCmd.h index b511436..f67ed22 100644 --- a/include/HalPwrSeqCmd.h +++ b/include/HalPwrSeqCmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HALPWRSEQCMD_H__ #define __HALPWRSEQCMD_H__ diff --git a/include/HalVerDef.h b/include/HalVerDef.h index 0288b43..ab1c578 100644 --- a/include/HalVerDef.h +++ b/include/HalVerDef.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_VERSION_DEF_H__ #define __HAL_VERSION_DEF_H__ @@ -40,7 +35,10 @@ typedef enum tag_HAL_IC_Type_Definition { CHIP_8188F = 12, CHIP_8822B = 13, CHIP_8723D = 14, - CHIP_8821C = 15 + CHIP_8821C = 15, + CHIP_8710B = 16, + CHIP_8192F = 17, + CHIP_8188GTV = 18, } HAL_IC_TYPE_E; /* HAL_CHIP_TYPE_E */ @@ -117,6 +115,7 @@ typedef struct tag_HAL_VERSION { #define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? TRUE : FALSE) #define IS_8188F(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE) +#define IS_8188GTV(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188GTV) ? TRUE : FALSE) #define IS_8192E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192E) ? TRUE : FALSE) #define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? TRUE : FALSE) #define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? TRUE : FALSE) @@ -125,8 +124,11 @@ typedef struct tag_HAL_VERSION { #define IS_8703B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8703B) ? TRUE : FALSE) #define IS_8822B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8822B) ? TRUE : FALSE) #define IS_8821C_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE) -#define IS_8723D_SERIES(version)\ - ((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE) +#define IS_8723D_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE) +#define IS_8710B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8710B) ? TRUE : FALSE) + +#define IS_8192F_SERIES(version)\ + ((GET_CVID_IC_TYPE(version) == CHIP_8192F) ? TRUE : FALSE) /* HAL_CHIP_TYPE_E */ #define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? TRUE : FALSE) #define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE) @@ -178,11 +180,7 @@ typedef struct tag_HAL_VERSION { #define IS_8723A_A_CUT(version) ((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE) #define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE) #endif -#ifdef CONFIG_USB_HCI -#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) (FALSE) -#else #define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE) -#endif #define IS_VENDOR_8812A_TEST_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) #define IS_VENDOR_8812A_MP_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) #define IS_VENDOR_8812A_C_CUT(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE) diff --git a/include/autoconf.h b/include/autoconf.h index 50ab405..100ef7d 100644 --- a/include/autoconf.h +++ b/include/autoconf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /***** temporarily flag *******/ #define CONFIG_SINGLE_IMG /* #define CONFIG_DISABLE_ODM */ @@ -29,15 +24,22 @@ #define DRV_NAME "rtl8821ce" #define CONFIG_PCI_HCI -#define CONFIG_PCIE_HCI #define PLATFORM_LINUX /* * Wi-Fi Functions Config */ -#define CONFIG_80211N_HT + #define CONFIG_RECV_REORDERING_CTRL + +#define CONFIG_80211N_HT #define CONFIG_80211AC_VHT +#ifdef CONFIG_80211AC_VHT + #ifndef CONFIG_80211N_HT + #define CONFIG_80211N_HT + #endif +#endif + #define CONFIG_IEEE80211_BAND_5GHZ /*#define CONFIG_IOCTL_CFG80211*/ @@ -56,6 +58,7 @@ /*#define CONFIG_H2CLBK*/ #define CONFIG_TRX_BD_ARCH /* PCI only */ #define USING_RX_TAG +/*#define CONFIG_64BIT_DMA*/ /* Enable PCI 64bit DMA */ #define CONFIG_EMBEDDED_FWIMG @@ -69,46 +72,38 @@ #define CONFIG_ACTIVE_KEEP_ALIVE_CHECK #endif -/*#define CONFIG_TCP_CSUM_OFFLOAD_RX*/ - -/*#define CONFIG_DRVEXT_MODULE*/ - - /*#define CONFIG_DISABLE_MCS13TO15 1*/ /* Disable MSC13-15 rates for more stable TX throughput with some 5G APs */ #define BUF_DESC_ARCH /* if defined, hardware follows Rx buffer descriptor architecture */ -#define CONFIG_IPS +#ifdef CONFIG_POWER_SAVING + #define CONFIG_IPS #ifdef CONFIG_IPS - /*#define CONFIG_IPS_LEVEL_2*/ /* enable this to set default IPS mode to IPS_LEVEL_2 */ -#endif -/*#define SUPPORT_HW_RFOFF_DETECTED*/ - -#define CONFIG_HIGH_CHAN_SUPER_CALIBRATION -/*#define CONFIG_LPS*/ + /*#define CONFIG_IPS_LEVEL_2*/ /* enable this to set default IPS mode to IPS_LEVEL_2 */ + #endif + /*#define SUPPORT_HW_RFOFF_DETECTED*/ -#if defined(CONFIG_LPS) - /*#define CONFIG_LPS_LCLK*/ /* 32K */ -#endif + #define CONFIG_LPS + #if defined(CONFIG_LPS) + /*#define CONFIG_LPS_LCLK*/ /* 32K */ + #endif + #ifdef CONFIG_LPS_LCLK + #define CONFIG_XMIT_THREAD_MODE + #define LPS_RPWM_WAIT_MS 300 + #endif -#ifdef CONFIG_LPS_LCLK - #define CONFIG_XMIT_THREAD_MODE + #ifdef CONFIG_LPS + #define CONFIG_WMMPS_STA 1 + #endif /* CONFIG_LPS */ #endif /*#define CONFIG_PCI_ASPM*/ -/*#define CONFIG_ANTENNA_DIVERSITY*/ +/*#define SUPPORT_HW_RFOFF_DETECTED*/ +#define CONFIG_HIGH_CHAN_SUPER_CALIBRATION -/*#define CONFIG_CONCURRENT_MODE*/ -#ifdef CONFIG_CONCURRENT_MODE - /*#define CONFIG_HWPORT_SWAP*/ /* Port0->Sec, Port1->Pri */ - /*#define CONFIG_RUNTIME_PORT_SWITCH*/ - /*#define DBG_RUNTIME_PORT_SWITCH*/ - #define CONFIG_SCAN_BACKOP - /*#define CONFIG_ATMEL_RC_PATCH*/ - /*#define CONFIG_TSF_RESET_OFFLOAD*/ /* For 2 PORT TSF SYNC. */ -#endif +/*#define CONFIG_ANTENNA_DIVERSITY*/ #define CONFIG_AP_MODE #ifdef CONFIG_AP_MODE @@ -142,7 +137,7 @@ /*#define CONFIG_P2P_IPS*/ #define CONFIG_P2P_OP_CHK_SOCIAL_CH #define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT /* replace CONFIG_P2P_CHK_INVITE_CH_LIST flag */ - #define CONFIG_P2P_INVITE_IOT + /*#define CONFIG_P2P_INVITE_IOT*/ #endif /* Added by Kurt 20110511 */ @@ -160,16 +155,18 @@ #define CONFIG_SKB_COPY /* for amsdu */ -/*#define CONFIG_LED*/ -#ifdef CONFIG_LED - /*#define CONFIG_SW_LED*/ - #ifdef CONFIG_SW_LED - /*#define CONFIG_LED_HANDLED_BY_CMD_THREAD*/ +/*#define CONFIG_RTW_LED*/ +#ifdef CONFIG_RTW_LED + /*#define CONFIG_RTW_SW_LED*/ + #ifdef CONFIG_RTW_SW_LED + /*#define CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD*/ #endif -#endif /* CONFIG_LED */ +#endif /* CONFIG_RTW_LED */ #define CONFIG_GLOBAL_UI_PID +/*#define CONFIG_RTW_80211K*/ + #define CONFIG_LAYER2_ROAMING #define CONFIG_LAYER2_ROAMING_RESUME /*#define CONFIG_ADAPTOR_INFO_CACHING_FILE*/ /* now just applied on 8192cu only, should make it general...*/ @@ -219,10 +216,7 @@ #define DISABLE_BB_RF 0 #ifdef CONFIG_WOWLAN #define CONFIG_GTK_OL - #define CONFIG_ARP_KEEP_ALIVE - #ifndef CONFIG_DEFAULT_PATTERNS_EN - #define CONFIG_DEFAULT_PATTERNS_EN - #endif + /* #define CONFIG_ARP_KEEP_ALIVE */ #endif /* CONFIG_WOWLAN */ #ifdef CONFIG_GPIO_WAKEUP @@ -264,13 +258,6 @@ #define RTL8192E_EARLY_MODE_PKT_NUM_10 0 #endif -/* Try to handle the Beacon error found in some types of TP-LINK APs */ -#define CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR - -#define CONFIG_80211D - -/* #define CONFIG_LAMODE */ - /* * Debug Related Config */ @@ -314,3 +301,5 @@ /* RX use 1 urb */ #define CONFIG_SINGLE_RECV_BUF #endif + +#define DBG_TXBD_DESC_DUMP diff --git a/include/basic_types.h b/include/basic_types.h index 245286d..c0737f5 100644 --- a/include/basic_types.h +++ b/include/basic_types.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __BASIC_TYPES_H__ #define __BASIC_TYPES_H__ @@ -100,9 +95,14 @@ #define UINT u32 #define ULONG u32 - #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) - typedef _Bool bool; - #endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) +typedef _Bool bool; + +enum { + false = 0, + true = 1 +}; +#endif typedef void (*proc_t)(void *); @@ -110,6 +110,36 @@ typedef __kernel_ssize_t SSIZE_T; #define FIELD_OFFSET(s, field) ((SSIZE_T)&((s *)(0))->field) +#define u1Byte u8 +#define pu1Byte u8* + +#define u2Byte u16 +#define pu2Byte u16* + +#define u4Byte u32 +#define pu4Byte u32* + +#define u8Byte u64 +#define pu8Byte u64* + +#define s1Byte s8 +#define ps1Byte s8* + +#define s2Byte s16 +#define ps2Byte s16* + +#define s4Byte s32 +#define ps4Byte s32* + +#define s8Byte s64 +#define ps8Byte s64* + +#define UCHAR u8 +#define USHORT u16 +#define UINT u32 +#define ULONG u32 +#define PULONG u32* + #endif diff --git a/include/byteorder/big_endian.h b/include/byteorder/big_endian.h index 345e9d8..6b1dc44 100644 --- a/include/byteorder/big_endian.h +++ b/include/byteorder/big_endian.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H #define _LINUX_BYTEORDER_BIG_ENDIAN_H diff --git a/include/byteorder/generic.h b/include/byteorder/generic.h index 02cf675..f85114b 100644 --- a/include/byteorder/generic.h +++ b/include/byteorder/generic.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_BYTEORDER_GENERIC_H #define _LINUX_BYTEORDER_GENERIC_H diff --git a/include/byteorder/little_endian.h b/include/byteorder/little_endian.h index 0b77336..c4b6451 100644 --- a/include/byteorder/little_endian.h +++ b/include/byteorder/little_endian.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H #define _LINUX_BYTEORDER_LITTLE_ENDIAN_H diff --git a/include/byteorder/swab.h b/include/byteorder/swab.h index d6d81b5..a8dd46b 100644 --- a/include/byteorder/swab.h +++ b/include/byteorder/swab.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_BYTEORDER_SWAB_H #define _LINUX_BYTEORDER_SWAB_H diff --git a/include/byteorder/swabb.h b/include/byteorder/swabb.h index ce33424..634519a 100644 --- a/include/byteorder/swabb.h +++ b/include/byteorder/swabb.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_BYTEORDER_SWABB_H #define _LINUX_BYTEORDER_SWABB_H diff --git a/include/circ_buf.h b/include/circ_buf.h index 2352316..7a5b8ef 100644 --- a/include/circ_buf.h +++ b/include/circ_buf.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __CIRC_BUF_H_ #define __CIRC_BUF_H_ 1 diff --git a/include/cmd_osdep.h b/include/cmd_osdep.h index 9c63a1c..e4ba2b6 100644 --- a/include/cmd_osdep.h +++ b/include/cmd_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __CMD_OSDEP_H_ #define __CMD_OSDEP_H_ diff --git a/include/cmn_info/rtw_sta_info.h b/include/cmn_info/rtw_sta_info.h new file mode 100644 index 0000000..edb8082 --- /dev/null +++ b/include/cmn_info/rtw_sta_info.h @@ -0,0 +1,250 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + /*This header file is for all driver teams to use the same station info. +If you want to change this file please make sure notify all driver teams maintainers.*/ + +/*Created by YuChen 20170301*/ + +#ifndef __INC_RTW_STA_INFO_H +#define __INC_RTW_STA_INFO_H + +/*--------------------Define ---------------------------------------*/ + +#define STA_DM_CTRL_ACTIVE BIT(0) +#define STA_DM_CTRL_CFO_TRACKING BIT(1) + +#ifdef CONFIG_BEAMFORMING +#define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT(0) /*Declare sta support beamformer*/ +#define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT(1) /*Declare sta support beamformee*/ +#define BEAMFORMING_HT_BEAMFORMER_TEST BIT(2) /*Transmiting Beamforming no matter the target supports it or not*/ +#define BEAMFORMING_HT_BEAMFORMER_STEER_NUM (BIT(4)|BIT(5)) /*Sta Bfer's capability*/ +#define BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP (BIT(6)|BIT(7)) /*Sta BFee's capability*/ + +#define BEAMFORMING_VHT_BEAMFORMER_ENABLE BIT(0) /*Declare sta support beamformer*/ +#define BEAMFORMING_VHT_BEAMFORMEE_ENABLE BIT(1) /*Declare sta support beamformee*/ +#define BEAMFORMING_VHT_MU_MIMO_AP_ENABLE BIT(2) /*Declare sta support MU beamformer*/ +#define BEAMFORMING_VHT_MU_MIMO_STA_ENABLE BIT(3) /*Declare sta support MU beamformer*/ +#define BEAMFORMING_VHT_BEAMFORMER_TEST BIT(4) /*Transmiting Beamforming no matter the target supports it or not*/ +#define BEAMFORMING_VHT_BEAMFORMER_STS_CAP (BIT(8)|BIT(9)|BIT(10)) /*Sta BFee's capability*/ +#define BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM (BIT(12)|BIT(13)|BIT(14)) /*Sta Bfer's capability*/ +#endif + +#define HT_STBC_EN BIT(0) +#define VHT_STBC_EN BIT(1) + +#define HT_LDPC_EN BIT(0) +#define VHT_LDPC_EN BIT(1) + +#define SM_PS_STATIC 0 +#define SM_PS_DYNAMIC 1 +#define SM_PS_INVALID 2 +#define SM_PS_DISABLE 3 + + +/*cmn_sta_info.ra_sta_info.txrx_state*/ +#define TX_STATE 0 +#define RX_STATE 1 +#define BI_DIRECTION_STATE 2 + +/*--------------------Define Enum-----------------------------------*/ +enum channel_width { + CHANNEL_WIDTH_20 = 0, + CHANNEL_WIDTH_40 = 1, + CHANNEL_WIDTH_80 = 2, + CHANNEL_WIDTH_160 = 3, + CHANNEL_WIDTH_80_80 = 4, + CHANNEL_WIDTH_5 = 5, + CHANNEL_WIDTH_10 = 6, + CHANNEL_WIDTH_MAX = 7, +}; + +enum rf_type { + RF_1T1R = 0, + RF_1T2R = 1, + RF_2T2R = 2, + RF_2T3R = 3, + RF_2T4R = 4, + RF_3T3R = 5, + RF_3T4R = 6, + RF_4T4R = 7, + RF_TYPE_MAX, +}; + +enum bb_path { + BB_PATH_A = 0x00000001, + BB_PATH_B = 0x00000002, + BB_PATH_C = 0x00000004, + BB_PATH_D = 0x00000008, + + BB_PATH_AB = (BB_PATH_A | BB_PATH_B), + BB_PATH_AC = (BB_PATH_A | BB_PATH_C), + BB_PATH_AD = (BB_PATH_A | BB_PATH_D), + BB_PATH_BC = (BB_PATH_B | BB_PATH_C), + BB_PATH_BD = (BB_PATH_B | BB_PATH_D), + BB_PATH_CD = (BB_PATH_C | BB_PATH_D), + + BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), + BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), + BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), + BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), + + BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), +}; + +enum rf_path { + RF_PATH_A = 0, + RF_PATH_B = 1, + RF_PATH_C = 2, + RF_PATH_D = 3, + RF_PATH_AB, + RF_PATH_AC, + RF_PATH_AD, + RF_PATH_BC, + RF_PATH_BD, + RF_PATH_CD, + RF_PATH_ABC, + RF_PATH_ACD, + RF_PATH_BCD, + RF_PATH_ABCD, +}; + +enum wireless_set { + WIRELESS_CCK = 0x00000001, + WIRELESS_OFDM = 0x00000002, + WIRELESS_HT = 0x00000004, + WIRELESS_VHT = 0x00000008, +}; + +/*--------------------Define MACRO---------------------------------*/ + +/*--------------------Define Struct-----------------------------------*/ + +#ifdef CONFIG_BEAMFORMING +struct bf_cmn_info { + u8 ht_beamform_cap; /*Sta capablity*/ + u16 vht_beamform_cap; /*Sta capablity*/ + u16 p_aid; + u8 g_id; +}; +#endif +struct rssi_info { + s8 rssi; + s8 rssi_cck; + s8 rssi_ofdm; + u8 packet_map; + u8 ofdm_pkt_cnt; + u8 cck_pkt_cnt; + u16 cck_sum_power; + u8 is_send_rssi; + u8 valid_bit; + s16 rssi_acc; /*accumulate RSSI for per packet MA sum*/ +}; + +struct ra_sta_info { + u8 rate_id; /*[PHYDM] ratr_idx*/ + u8 rssi_level; /*[PHYDM]*/ + u8 is_first_connect:1; /*[PHYDM] CE: ra_rpt_linked, AP: H2C_rssi_rpt*/ + u8 is_support_sgi:1; /*[driver]*/ + u8 is_vht_enable:2; /*[driver]*/ + u8 disable_ra:1; /*[driver]*/ + u8 disable_pt:1; /*[driver] remove is_disable_power_training*/ + u8 txrx_state:2; /*[PHYDM] 0: Tx, 1:Rx, 2:bi-direction*/ + u8 is_noisy:1; /*[PHYDM]*/ + u8 curr_tx_rate; /*[PHYDM] FW->Driver*/ + enum channel_width ra_bw_mode; /*[Driver] max bandwidth, for RA only*/ + enum channel_width curr_tx_bw; /*[PHYDM] FW->Driver*/ + u8 curr_retry_ratio; /*[PHYDM] FW->Driver*/ + u64 ramask; +}; + +struct dtp_info { + u8 dyn_tx_power; /*Dynamic Tx power offset*/ + u8 last_tx_power; + u8 sta_tx_high_power_lvl:4; + u8 sta_last_dtp_lvl:4; +}; + +struct cmn_sta_info { + u16 dm_ctrl; /*[Driver]*/ + enum channel_width bw_mode; /*[Driver] max support BW*/ + u8 mac_id; /*[Driver]*/ + u8 mac_addr[6]; /*[Driver]*/ + u16 aid; /*[Driver]*/ + enum rf_type mimo_type; /*[Driver] sta XTXR*/ + struct rssi_info rssi_stat; /*[PHYDM]*/ + struct ra_sta_info ra_info; /*[Driver&PHYDM]*/ + u16 tx_moving_average_tp; /*[Driver] tx average MBps*/ + u16 rx_moving_average_tp; /*[Driver] rx average MBps*/ + u8 stbc_en:2; /*[Driver] really transmitt STBC*/ + u8 ldpc_en:2; /*[Driver] really transmitt LDPC*/ + enum wireless_set support_wireless_set;/*[Driver]*/ +#ifdef CONFIG_BEAMFORMING + struct bf_cmn_info bf_info; /*[Driver]*/ +#endif + u8 sm_ps:2; /*[Driver]*/ + struct dtp_info dtp_stat; /*[PHYDM] Dynamic Tx power offset*/ + /*u8 pw2cca_over_TH_cnt;*/ + /*u8 total_pw2cca_cnt;*/ +}; + +struct phydm_phyinfo_struct { + u8 rx_pwdb_all; + u8 signal_quality; /* OFDM: signal_quality=rx_mimo_signal_quality[0], CCK: signal qualityin 0-100 index. */ + u8 rx_mimo_signal_strength[4]; /* RSSI in 0~100 index */ + s8 rx_mimo_signal_quality[4]; /* OFDM: per-path's EVM translate to 0~100% , no used for CCK*/ + u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */ + s16 cfo_short[4]; /* per-path's cfo_short */ + s16 cfo_tail[4]; /* per-path's cfo_tail */ + s8 rx_power; /* in dBm Translate from PWdB */ + s8 recv_signal_power; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ + u8 bt_rx_rssi_percentage; + u8 signal_strength; /* in 0-100 index. */ + s8 rx_pwr[4]; /* per-path's pwdb */ + s8 rx_snr[4]; /* per-path's SNR */ +/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/ + u8 rx_count:2; /* RX path counter---*/ + u8 band_width:2; + u8 rxsc:4; /* sub-channel---*/ + u8 channel; /* channel number---*/ + u8 is_mu_packet:1; /* is MU packet or not---boolean*/ + u8 is_beamformed:1; /* BF packet---boolean*/ + u8 cnt_pw2cca; + u8 cnt_cca2agc_rdy; +/*ODM_PHY_STATUS_NEW_TYPE_SUPPORT*/ +}; + +struct phydm_perpkt_info_struct { + u8 data_rate; + u8 station_id; + u8 is_cck_rate: 1; + u8 rate_ss:3; /*spatial stream of data rate*/ + u8 is_packet_match_bssid:1; /*boolean*/ + u8 is_packet_to_self:1; /*boolean*/ + u8 is_packet_beacon:1; /*boolean*/ + u8 is_to_self:1; /*boolean*/ + u8 ppdu_cnt; +}; + +/*--------------------Export global variable----------------------------*/ + +/*--------------------Function declaration-----------------------------*/ + +#endif diff --git a/include/custom_gpio.h b/include/custom_gpio.h index 5691d9a..49411b6 100644 --- a/include/custom_gpio.h +++ b/include/custom_gpio.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __CUSTOM_GPIO_H__ #define __CUSTOM_GPIO_H___ diff --git a/include/drv_conf.h b/include/drv_conf.h index 19a4a6f..5436c91 100644 --- a/include/drv_conf.h +++ b/include/drv_conf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_CONF_H__ #define __DRV_CONF_H__ #include "autoconf.h" @@ -27,6 +22,26 @@ #error "Shall be Linux or Windows, but not both!\n" #endif +#define CONFIG_RSSI_PRIORITY +#ifdef CONFIG_RTW_REPEATER_SON + #ifndef CONFIG_AP + #define CONFIG_AP + #endif + #ifndef CONFIG_CONCURRENT_MODE + #define CONFIG_CONCURRENT_MODE + #endif + #ifndef CONFIG_BR_EXT + #define CONFIG_BR_EXT + #endif + #ifndef CONFIG_RTW_REPEATER_SON_ID + #define CONFIG_RTW_REPEATER_SON_ID 0x02040608 + #endif + //#define CONFIG_RTW_REPEATER_SON_ROOT + #ifndef CONFIG_RTW_REPEATER_SON_ROOT + #define CONFIG_LAYER2_ROAMING_ACTIVE + #endif + #undef CONFIG_POWER_SAVING +#endif #if defined(CONFIG_MCC_MODE) && (!defined(CONFIG_CONCURRENT_MODE)) @@ -100,9 +115,50 @@ #define CONFIG_USB_VENDOR_REQ_MUTEX #endif +#if defined(CONFIG_DFS_SLAVE_WITH_RADAR_DETECT) && !defined(CONFIG_DFS_MASTER) + #define CONFIG_DFS_MASTER +#endif + #if !defined(CONFIG_AP_MODE) && defined(CONFIG_DFS_MASTER) - #warning "undef CONFIG_DFS_MASTER because CONFIG_AP_MODE is not defined" - #undef CONFIG_DFS_MASTER + #error "enable CONFIG_DFS_MASTER without CONFIG_AP_MODE" +#endif + +#ifdef CONFIG_RTW_MESH + #ifndef CONFIG_RTW_MESH_ACNODE_PREVENT + #define CONFIG_RTW_MESH_ACNODE_PREVENT 1 + #endif + + #ifndef CONFIG_RTW_MESH_OFFCH_CAND + #define CONFIG_RTW_MESH_OFFCH_CAND 1 + #endif + + #ifndef CONFIG_RTW_MESH_PEER_BLACKLIST + #define CONFIG_RTW_MESH_PEER_BLACKLIST 1 + #endif + + #ifndef CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + #define CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST 1 + #endif + #ifndef CONFIG_RTW_MESH_CTO_MGATE_CARRIER + #define CONFIG_RTW_MESH_CTO_MGATE_CARRIER CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + #endif + + #ifndef CONFIG_RTW_MPM_TX_IES_SYNC_BSS + #define CONFIG_RTW_MPM_TX_IES_SYNC_BSS 1 + #endif + #if CONFIG_RTW_MPM_TX_IES_SYNC_BSS + #ifndef CONFIG_RTW_MESH_AEK + #define CONFIG_RTW_MESH_AEK + #endif + #endif + + #ifndef CONFIG_RTW_MESH_DATA_BMC_TO_UC + #define CONFIG_RTW_MESH_DATA_BMC_TO_UC 1 + #endif +#endif + +#if !defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) +#define CONFIG_SCAN_BACKOP #endif #define RTW_SCAN_SPARSE_MIRACAST 1 @@ -113,10 +169,6 @@ #define CONFIG_RTW_HIQ_FILTER 1 #endif -#ifndef CONFIG_RTW_FORCE_IGI_LB - #define CONFIG_RTW_FORCE_IGI_LB 0 -#endif - #ifndef CONFIG_RTW_ADAPTIVITY_EN #define CONFIG_RTW_ADAPTIVITY_EN 0 #endif @@ -125,14 +177,6 @@ #define CONFIG_RTW_ADAPTIVITY_MODE 0 #endif -#ifndef CONFIG_RTW_ADAPTIVITY_DML - #define CONFIG_RTW_ADAPTIVITY_DML 0 -#endif - -#ifndef CONFIG_RTW_ADAPTIVITY_DC_BACKOFF - #define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 2 -#endif - #ifndef CONFIG_RTW_ADAPTIVITY_TH_L2H_INI #define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0 #endif @@ -156,6 +200,10 @@ #define CONFIG_TXPWR_LIMIT_EN 2 /* by efuse */ #endif +#ifndef CONFIG_RTW_CHPLAN +#define CONFIG_RTW_CHPLAN 0xFF /* RTW_CHPLAN_UNSPECIFIED */ +#endif + /* compatible with old fashion configuration */ #if defined(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY) #undef CONFIG_TXPWR_BY_RATE_EN @@ -181,6 +229,22 @@ #define CONFIG_TXPWR_LIMIT_EN 1 #endif +#if !defined(CONFIG_TXPWR_LIMIT) && CONFIG_TXPWR_LIMIT_EN + #define CONFIG_TXPWR_LIMIT +#endif + +#ifdef CONFIG_RTW_IPCAM_APPLICATION + #undef CONFIG_TXPWR_BY_RATE_EN + #define CONFIG_TXPWR_BY_RATE_EN 1 + #define CONFIG_RTW_CUSTOMIZE_BEEDCA 0x0000431C + #define CONFIG_RTW_CUSTOMIZE_BWMODE 0x00 + #define CONFIG_RTW_CUSTOMIZE_RLSTA 0x7 +#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B) + #define CONFIG_RTW_TX_2PATH_EN /* mutually incompatible with STBC_TX & Beamformer */ +#endif +#endif +/*#define CONFIG_EXTEND_LOWRATE_TXOP */ + #ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS #define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS {0xFF, 0xFF, 0xFF, 0xFF} #endif @@ -261,11 +325,33 @@ #endif #if (CONFIG_IFACE_NUMBER == 0) - #error "CONFIG_IFACE_NUMBER cound not equel to 0 !!" + #error "CONFIG_IFACE_NUMBER cound not be 0 !!" +#endif + +#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8188F) || \ +defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8192F) || \ +defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8710B) || \ +defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D) +#define CONFIG_HWMPCAP_GEN1 +#elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) /*|| defined(CONFIG_RTL8814A)*/ +#define CONFIG_HWMPCAP_GEN2 +#elif defined(CONFIG_RTL8814B) /*Address CAM - 128*/ +#define CONFIG_HWMPCAP_GEN3 +#endif + +#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 2) + #ifdef CONFIG_POWER_SAVING + /*#warning "Disable PS when CONFIG_IFACE_NUMBER > 2"*/ + #undef CONFIG_POWER_SAVING + #endif + + #ifdef CONFIG_WOWLAN + #error "This IC can't support MI and WoWLan at the same time" + #endif #endif -#if (CONFIG_IFACE_NUMBER > 3) - #error "Not support over 3 interfaces yet !!" +#if (CONFIG_IFACE_NUMBER > 4) + #error "Not support over 4 interfaces yet !!" #endif #if (CONFIG_IFACE_NUMBER > 8) /*IFACE_ID_MAX*/ @@ -283,10 +369,28 @@ #endif #ifdef CONFIG_AP_MODE + #define CONFIG_SUPPORT_MULTI_BCN + #define CONFIG_SWTIMER_BASED_TXBCN - /*#define CONFIG_FW_BASED_BCN*/ - #endif -#endif + + #ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/ + #define CONFIG_FW_HANDLE_TXBCN + + #ifdef CONFIG_FW_HANDLE_TXBCN + #ifdef CONFIG_SWTIMER_BASED_TXBCN + #undef CONFIG_SWTIMER_BASED_TXBCN + #endif + + #define CONFIG_LIMITED_AP_NUM 4 + #endif + #endif /*CONFIG_HWMPCAP_GEN2*/ + #endif /*CONFIG_AP_MODE*/ + + #ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/ + #define CONFIG_CLIENT_PORT_CFG + #define CONFIG_NEW_NETDEV_HDL + #endif/*CONFIG_HWMPCAP_GEN2*/ +#endif/*(CONFIG_IFACE_NUMBER > 2)*/ #define MACID_NUM_SW_LIMIT 32 #define SEC_CAM_ENT_NUM_SW_LIMIT 32 @@ -295,10 +399,18 @@ #define CONFIG_IEEE80211_BAND_5GHZ #endif -#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)) +#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814A)) #define CONFIG_WOW_PATTERN_HW_CAM #endif +#ifndef CONFIG_TSF_UPDATE_PAUSE_FACTOR +#define CONFIG_TSF_UPDATE_PAUSE_FACTOR 200 +#endif + +#ifndef CONFIG_TSF_UPDATE_RESTORE_FACTOR +#define CONFIG_TSF_UPDATE_RESTORE_FACTOR 5 +#endif + /* Mark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20 If the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle, @@ -311,6 +423,7 @@ /*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC */ +/*#define CONFIG_PHDYM_FW_FIXRATE */ /* Another way to fix tx rate */ /*Don't release SDIO irq in suspend/resume procedure*/ #define CONFIG_RTW_SDIO_KEEP_IRQ 0 @@ -323,4 +436,43 @@ #define RTW_RX_AGGREGATION #endif /* CONFIG_SDIO_HCI || CONFIG_USB_RX_AGGREGATION */ +#ifdef CONFIG_RTW_HOSTAPD_ACS + #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) + #ifndef CONFIG_FIND_BEST_CHANNEL + #define CONFIG_FIND_BEST_CHANNEL + #endif + #else + #ifdef CONFIG_FIND_BEST_CHANNEL + #undef CONFIG_FIND_BEST_CHANNEL + #endif + #ifndef CONFIG_RTW_ACS + #define CONFIG_RTW_ACS + #endif + #ifndef CONFIG_BACKGROUND_NOISE_MONITOR + #define CONFIG_BACKGROUND_NOISE_MONITOR + #endif + #endif +#endif + +#ifdef CONFIG_RTW_80211K + #ifndef CONFIG_RTW_ACS + #define CONFIG_RTW_ACS + #endif +#endif /*CONFIG_RTW_80211K*/ + +#ifdef DBG_CONFIG_ERROR_RESET +#ifndef CONFIG_IPS +#define CONFIG_IPS +#endif +#endif + +#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME +#ifndef CONFIG_RTL8822B + #error "Only 8822B support RTW_REDUCE_SCAN_SWITCH_CH_TIME" +#endif + #ifndef RTW_CHANNEL_SWITCH_OFFLOAD + #define RTW_CHANNEL_SWITCH_OFFLOAD + #endif +#endif + #endif /* __DRV_CONF_H__ */ diff --git a/include/drv_types.h b/include/drv_types.h index b82a4d5..ddf7da7 100644 --- a/include/drv_types.h +++ b/include/drv_types.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /*------------------------------------------------------------------------------- For type defines and data structure defines @@ -63,7 +58,9 @@ enum _NIC_VERSION { typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include +#include #include +#include "../core/rtw_chplan.h" #ifdef CONFIG_80211N_HT #include @@ -83,6 +80,7 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #include #include +#include #ifdef CONFIG_BEAMFORMING #include @@ -112,6 +110,9 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #include #include +#ifdef CONFIG_RTW_MESH +#include "../core/mesh/rtw_mesh.h" +#endif #include #include #include @@ -130,10 +131,6 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #endif /* CONFIG_WAPI_SUPPORT */ -#ifdef CONFIG_DRVEXT_MODULE - #include -#endif /* CONFIG_DRVEXT_MODULE */ - #ifdef CONFIG_MP_INCLUDED #include #endif /* CONFIG_MP_INCLUDED */ @@ -154,14 +151,16 @@ typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; #include #include -#ifdef CONFIG_BT_COEXIST - #include -#endif /* CONFIG_BT_COEXIST */ +#include #ifdef CONFIG_MCC_MODE #include #endif /*CONFIG_MCC_MODE */ +#ifdef CONFIG_RTW_REPEATER_SON + #include +#endif /*CONFIG_RTW_REPEATER_SON */ + #define SPEC_DEV_ID_NONE BIT(0) #define SPEC_DEV_ID_DISABLE_HT BIT(1) #define SPEC_DEV_ID_ENABLE_PS BIT(2) @@ -199,12 +198,17 @@ struct registry_priv { u8 power_mgnt; u8 ips_mode; u8 lps_level; + u8 lps_chk_by_tp; u8 smart_ps; +#ifdef CONFIG_WMMPS_STA + u8 wmm_smart_ps; +#endif /* CONFIG_WMMPS_STA */ u8 usb_rxagg_mode; u8 dynamic_agg_enable; u8 long_retry_lmt; u8 short_retry_lmt; u16 busy_thresh; + u16 max_bss_cnt; u8 ack_policy; u8 mp_mode; #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) @@ -217,19 +221,21 @@ struct registry_priv { u8 early_mode; #endif u8 acm_method; - /* UAPSD */ + /* WMM */ u8 wmm_enable; - u8 uapsd_enable; - u8 uapsd_max_sp; - u8 uapsd_acbk_en; - u8 uapsd_acbe_en; - u8 uapsd_acvi_en; - u8 uapsd_acvo_en; +#ifdef CONFIG_WMMPS_STA + /* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */ + u8 uapsd_max_sp_len; + /* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */ + u8 uapsd_ac_enable; +#endif /* CONFIG_WMMPS_STA */ WLAN_BSSID_EX dev_network; u8 tx_bw_mode; - +#ifdef CONFIG_AP_MODE + u8 bmc_tx_rate; +#endif #ifdef CONFIG_80211N_HT u8 ht_enable; /* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz */ @@ -325,21 +331,14 @@ struct registry_priv { u8 notch_filter; -#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - u8 force_ant;/* 0 normal,1 main,2 aux */ - u8 force_igi;/* 0 normal */ -#endif - - u8 force_igi_lb; - /* for pll reference clock selction */ u8 pll_ref_clk_sel; /* define for tx power adjust */ +#ifdef CONFIG_TXPWR_LIMIT u8 RegEnableTxPowerLimit; +#endif u8 RegEnableTxPowerByRate; - u8 RegPowerBase; - u8 RegPwrTblSel; u8 target_tx_pwr_valid; s8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM]; @@ -347,6 +346,9 @@ struct registry_priv { s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1]; #endif + u8 tsf_update_pause_factor; + u8 tsf_update_restore_factor; + s8 TxBBSwing_2G; s8 TxBBSwing_5G; u8 AmplifierType_2G; @@ -370,16 +372,18 @@ struct registry_priv { u8 hiq_filter; u8 adaptivity_en; u8 adaptivity_mode; - u8 adaptivity_dml; - u8 adaptivity_dc_backoff; s8 adaptivity_th_l2h_ini; s8 adaptivity_th_edcca_hl_diff; u8 boffefusemask; BOOLEAN bFileMaskEfuse; -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - u8 acs_mode; +#ifdef CONFIG_RTW_ACS u8 acs_auto_scan; + u8 acs_mode; +#endif + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + u8 nm_mode; #endif u32 reg_rxgain_offset_2g; u32 reg_rxgain_offset_5gl; @@ -401,27 +405,58 @@ struct registry_priv { u32 rtw_mcc_sta_bw80_target_tx_tp; s8 rtw_mcc_policy_table_idx; u8 rtw_mcc_duration; - u8 rtw_mcc_tsf_sync_offset; - u8 rtw_mcc_start_time_offset; - u8 rtw_mcc_interval; - s8 rtw_mcc_guard_offset0; - s8 rtw_mcc_guard_offset1; + u8 rtw_mcc_enable_runtime_duration; #endif /* CONFIG_MCC_MODE */ #ifdef CONFIG_RTW_NAPI u8 en_napi; +#ifdef CONFIG_RTW_NAPI_DYNAMIC + u32 napi_threshold; /* unit: Mbps */ +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ #ifdef CONFIG_RTW_GRO u8 en_gro; #endif /* CONFIG_RTW_GRO */ #endif /* CONFIG_RTW_NAPI */ - bool default_patterns_en; +#ifdef CONFIG_WOWLAN + u8 wakeup_event; +#endif + #ifdef CONFIG_SUPPORT_TRX_SHARED u8 trx_share_mode; #endif u8 check_hw_status; u32 pci_aspm_config; + + u8 iqk_fw_offload; + u8 ch_switch_offload; + +#ifdef CONFIG_TDLS + u8 en_tdls; +#endif + +#ifdef CONFIG_ADVANCE_OTA + u8 adv_ota; +#endif + +#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT + u8 fw_param_init; +#endif +#ifdef CONFIG_DYNAMIC_SOML + u8 dyn_soml_en; + u8 dyn_soml_train_num; + u8 dyn_soml_interval; + u8 dyn_soml_period; + u8 dyn_soml_delay; +#endif +#ifdef CONFIG_FW_HANDLE_TXBCN + u8 fw_tbtt_rpt; +#endif + +#ifdef DBG_LA_MODE + u8 la_mode_en; +#endif }; /* For registry parameters */ @@ -444,8 +479,13 @@ struct registry_priv { #define BW_MODE_2G(bw_mode) ((bw_mode) & 0x0F) #define BW_MODE_5G(bw_mode) ((bw_mode) >> 4) +#ifdef CONFIG_80211N_HT #define REGSTY_BW_2G(regsty) BW_MODE_2G((regsty)->bw_mode) #define REGSTY_BW_5G(regsty) BW_MODE_5G((regsty)->bw_mode) +#else +#define REGSTY_BW_2G(regsty) CHANNEL_WIDTH_20 +#define REGSTY_BW_5G(regsty) CHANNEL_WIDTH_20 +#endif #define REGSTY_IS_BW_2G_SUPPORT(regsty, bw) (REGSTY_BW_2G((regsty)) >= (bw)) #define REGSTY_IS_BW_5G_SUPPORT(regsty, bw) (REGSTY_BW_5G((regsty)) >= (bw)) @@ -658,12 +698,6 @@ struct debug_priv { u64 dbg_rx_fifo_last_overflow; u64 dbg_rx_fifo_curr_overflow; u64 dbg_rx_fifo_diff_overflow; - u64 dbg_rx_ampdu_drop_count; - u64 dbg_rx_ampdu_forced_indicate_count; - u64 dbg_rx_ampdu_loss_count; - u64 dbg_rx_dup_mgt_frame_drop_count; - u64 dbg_rx_ampdu_window_shift_cnt; - u64 dbg_rx_conflic_mac_addr_cnt; }; struct rtw_traffic_statistics { @@ -673,7 +707,7 @@ struct rtw_traffic_statistics { u64 tx_drop; u64 cur_tx_bytes; u64 last_tx_bytes; - u32 cur_tx_tp; /* Tx throughput in MBps. */ + u32 cur_tx_tp; /* Tx throughput in Mbps. */ /* rx statistics */ u64 rx_bytes; @@ -681,7 +715,7 @@ struct rtw_traffic_statistics { u64 rx_drop; u64 cur_rx_bytes; u64 last_rx_bytes; - u32 cur_rx_tp; /* Rx throughput in MBps. */ + u32 cur_rx_tp; /* Rx throughput in Mbps. */ }; #define SEC_CAP_CHK_BMC BIT0 @@ -724,6 +758,8 @@ struct sec_cam_ent { ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \ ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] +#define RTW_DEFAULT_MGMT_MACID 1 + struct macid_bmp { u32 m0; #if (MACID_NUM_SW_LIMIT > 32) @@ -737,20 +773,44 @@ struct macid_bmp { #endif }; +#ifdef CONFIG_CLIENT_PORT_CFG +struct clt_port_t{ + _lock lock; + u8 bmp; + s8 num; +}; +#define get_clt_num(adapter) (adapter_to_dvobj(adapter)->clt_port.num) +#endif + struct macid_ctl_t { _lock lock; u8 num; struct macid_bmp used; struct macid_bmp bmc; struct macid_bmp if_g[CONFIG_IFACE_NUMBER]; - u8 iface_bmc[CONFIG_IFACE_NUMBER];/*for bc-sta of AP or Adhoc mode*/ struct macid_bmp ch_g[2]; /* 2 ch concurrency */ + + u8 iface_bmc[CONFIG_IFACE_NUMBER]; /* bmc TX macid for each iface*/ + u8 h2c_msr[MACID_NUM_SW_LIMIT]; u8 bw[MACID_NUM_SW_LIMIT]; u8 vht_en[MACID_NUM_SW_LIMIT]; u32 rate_bmp0[MACID_NUM_SW_LIMIT]; u32 rate_bmp1[MACID_NUM_SW_LIMIT]; - struct sta_info *sta[MACID_NUM_SW_LIMIT]; + + struct sta_info *sta[MACID_NUM_SW_LIMIT]; /* corresponding stainfo when macid is not shared */ + + /* macid sleep registers */ + u16 reg_sleep_m0; +#if (MACID_NUM_SW_LIMIT > 32) + u16 reg_sleep_m1; +#endif +#if (MACID_NUM_SW_LIMIT > 64) + u16 reg_sleep_m2; +#endif +#if (MACID_NUM_SW_LIMIT > 96) + u16 reg_sleep_m3; +#endif }; /* used for rf_ctl_t.rate_bmp_cck_ofdm */ @@ -786,7 +846,33 @@ struct macid_ctl_t { #define RATE_BMP_GET_VHT_2SS(_bmp_vht) ((_bmp_vht & RATE_BMP_VHT_2SS) >> 10) #define RATE_BMP_GET_VHT_3SS(_bmp_vht) ((_bmp_vht & RATE_BMP_VHT_3SS) >> 20) +#define TXPWR_LMT_REF_VHT_FROM_HT BIT0 +#define TXPWR_LMT_REF_HT_FROM_VHT BIT1 + +#define TXPWR_LMT_HAS_CCK_1T BIT0 +#define TXPWR_LMT_HAS_CCK_2T BIT1 +#define TXPWR_LMT_HAS_CCK_3T BIT2 +#define TXPWR_LMT_HAS_CCK_4T BIT3 +#define TXPWR_LMT_HAS_OFDM_1T BIT4 +#define TXPWR_LMT_HAS_OFDM_2T BIT5 +#define TXPWR_LMT_HAS_OFDM_3T BIT6 +#define TXPWR_LMT_HAS_OFDM_4T BIT7 + +#define OFFCHS_NONE 0 +#define OFFCHS_LEAVING_OP 1 +#define OFFCHS_LEAVE_OP 2 +#define OFFCHS_BACKING_OP 3 + struct rf_ctl_t { + const struct country_chplan *country_ent; + u8 ChannelPlan; + u8 max_chan_nums; + RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM]; + struct p2p_channels channel_list; + + _mutex offch_mutex; + u8 offch_state; + /* used for debug or by tx power limit */ u16 rate_bmp_cck_ofdm; /* 20MHz */ u32 rate_bmp_ht_by_bw[2]; /* 20MHz, 40MHz. 4SS supported */ @@ -796,30 +882,70 @@ struct rf_ctl_t { u8 highest_ht_rate_bw_bmp; u8 highest_vht_rate_bw_bmp; +#ifdef CONFIG_TXPWR_LIMIT + _mutex txpwr_lmt_mutex; + _list reg_exc_list; + u8 regd_exc_num; + _list txpwr_lmt_list; + u8 txpwr_regd_num; + const char *regd_name; + + u8 txpwr_lmt_2g_cck_ofdm_state; + #ifdef CONFIG_IEEE80211_BAND_5GHZ + u8 txpwr_lmt_5g_cck_ofdm_state; + u8 txpwr_lmt_5g_20_40_ref; + #endif +#endif + + u8 ch_sel_same_band_prefer; + +#ifdef CONFIG_DFS + u8 csa_ch; + #ifdef CONFIG_DFS_MASTER + _timer radar_detect_timer; bool radar_detect_by_others; - u8 dfs_master_enabled; + u8 radar_detect_enabled; bool radar_detected; u8 radar_detect_ch; u8 radar_detect_bw; u8 radar_detect_offset; - u32 cac_start_time; - u32 cac_end_time; + systime cac_start_time; + systime cac_end_time; + u8 cac_force_stop; +#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT + u8 dfs_slave_with_rd; +#endif u8 dfs_ch_sel_d_flags; - u8 dbg_dfs_master_fake_radar_detect_cnt; - u8 dbg_dfs_master_radar_detect_trigger_non; - u8 dbg_dfs_master_choose_dfs_ch_first; -#endif + u8 dbg_dfs_fake_radar_detect_cnt; + u8 dbg_dfs_radar_detect_trigger_non; + u8 dbg_dfs_choose_dfs_ch_first; +#endif /* CONFIG_DFS_MASTER */ +#endif /* CONFIG_DFS */ }; #define RTW_CAC_STOPPED 0 +#ifdef CONFIG_DFS_MASTER #define IS_CAC_STOPPED(rfctl) ((rfctl)->cac_end_time == RTW_CAC_STOPPED) -#define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && time_after((unsigned long)(rfctl)->cac_end_time, (unsigned long)rtw_get_current_time())) -#define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && time_after((unsigned long)rtw_get_current_time(), (unsigned long)(rfctl)->cac_start_time)) +#define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && rtw_time_after((rfctl)->cac_end_time, rtw_get_current_time())) +#define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && rtw_time_after(rtw_get_current_time(), (rfctl)->cac_start_time)) +#define IS_RADAR_DETECTED(rfctl) ((rfctl)->radar_detected) +#else +#define IS_CAC_STOPPED(rfctl) 1 +#define IS_CH_WAITING(rfctl) 0 +#define IS_UNDER_CAC(rfctl) 0 +#define IS_RADAR_DETECTED(rfctl) 0 +#endif /* CONFIG_DFS_MASTER */ + +#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT +#define IS_DFS_SLAVE_WITH_RD(rfctl) ((rfctl)->dfs_slave_with_rd) +#else +#define IS_DFS_SLAVE_WITH_RD(rfctl) 0 +#endif #ifdef CONFIG_MBSSID_CAM #define TOTAL_MBID_CAM_NUM 8 @@ -851,6 +977,7 @@ struct halmacpriv { /* For asynchronous functions */ struct halmac_indicator *indicator; + /* Hardware parameters */ #ifdef CONFIG_SDIO_HCI /* Store hardware tx queue page number setting */ u16 txpage[HW_QUEUE_ENTRY]; @@ -858,6 +985,21 @@ struct halmacpriv { }; #endif /* RTW_HALMAC */ +#ifdef CONFIG_FW_MULTI_PORT_SUPPORT +/*info for H2C-0x2C*/ +struct dft_info { + u8 port_id; + u8 mac_id; +}; +#endif + +#ifdef CONFIG_HW_P0_TSF_SYNC +struct tsf_info { + u8 sync_port;/*port_x's tsf sync to port_0*/ + u8 offset; /*tsf timer offset*/ +}; +#endif + struct dvobj_priv { /*-------- below is common data --------*/ u8 chip_type; @@ -887,20 +1029,41 @@ struct dvobj_priv { _mutex sd_indirect_access_mutex; #endif +#ifdef CONFIG_SYSON_INDIRECT_ACCESS + _mutex syson_indirect_access_mutex; /* System On Reg R/W */ +#endif + unsigned char oper_channel; /* saved channel info when call set_channel_bw */ unsigned char oper_bwmode; unsigned char oper_ch_offset;/* PRIME_CHNL_OFFSET */ - u32 on_oper_ch_time; + systime on_oper_ch_time; _adapter *padapters[CONFIG_IFACE_NUMBER];/*IFACE_ID_MAX*/ u8 iface_nums; /* total number of ifaces used runtime */ struct mi_state iface_state; #ifdef CONFIG_AP_MODE - u8 nr_ap_if; /* total interface s number of ap/go mode. */ - u32 inter_bcn_space; /* unit:ms */ + #ifdef CONFIG_SUPPORT_MULTI_BCN + u8 nr_ap_if; /* total interface number of ap /go /mesh / nan mode. */ + u16 inter_bcn_space; /* unit:ms */ _queue ap_if_q; + u8 vap_map; + u8 fw_bcn_offload; + u8 vap_tbtt_rpt_map; + #endif /*CONFIG_SUPPORT_MULTI_BCN*/ + #ifdef CONFIG_RTW_REPEATER_SON + struct rtw_rson_struct rson_data; + #endif #endif +#ifdef CONFIG_CLIENT_PORT_CFG + struct clt_port_t clt_port; +#endif + +#ifdef CONFIG_HW_P0_TSF_SYNC + struct tsf_info p0_tsf; +#endif + systime periodic_tsf_update_etime; + _timer periodic_tsf_update_end_timer; struct macid_ctl_t macid_ctl; @@ -947,6 +1110,10 @@ struct dvobj_priv { _timer txbcn_timer; #endif _timer dynamic_chk_timer; /* dynamic/periodic check timer */ + +#ifdef CONFIG_RTW_NAPI_DYNAMIC + u8 en_napi_dynamic; +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ #ifdef RTW_HALMAC void *halmac; @@ -954,8 +1121,14 @@ struct dvobj_priv { #endif /* RTW_HALMAC */ #ifdef CONFIG_FW_MULTI_PORT_SUPPORT - u8 default_port_id; + /*info for H2C-0x2C*/ + struct dft_info dft; #endif + +#ifdef CONFIG_RTW_WIFI_HAL + u32 nodfs; +#endif + /*-------- below is for SDIO INTERFACE --------*/ #ifdef INTF_DATA @@ -1083,10 +1256,18 @@ struct dvobj_priv { #define DEV_STA_NUM(_dvobj) MSTATE_STA_NUM(&((_dvobj)->iface_state)) #define DEV_STA_LD_NUM(_dvobj) MSTATE_STA_LD_NUM(&((_dvobj)->iface_state)) #define DEV_STA_LG_NUM(_dvobj) MSTATE_STA_LG_NUM(&((_dvobj)->iface_state)) +#define DEV_TDLS_LD_NUM(_dvobj) MSTATE_TDLS_LD_NUM(&((_dvobj)->iface_state)) #define DEV_AP_NUM(_dvobj) MSTATE_AP_NUM(&((_dvobj)->iface_state)) +#define DEV_AP_STARTING_NUM(_dvobj) MSTATE_AP_STARTING_NUM(&((_dvobj)->iface_state)) #define DEV_AP_LD_NUM(_dvobj) MSTATE_AP_LD_NUM(&((_dvobj)->iface_state)) #define DEV_ADHOC_NUM(_dvobj) MSTATE_ADHOC_NUM(&((_dvobj)->iface_state)) #define DEV_ADHOC_LD_NUM(_dvobj) MSTATE_ADHOC_LD_NUM(&((_dvobj)->iface_state)) +#define DEV_MESH_NUM(_dvobj) MSTATE_MESH_NUM(&((_dvobj)->iface_state)) +#define DEV_MESH_LD_NUM(_dvobj) MSTATE_MESH_LD_NUM(&((_dvobj)->iface_state)) +#define DEV_P2P_DV_NUM(_dvobj) MSTATE_P2P_DV_NUM(&((_dvobj)->iface_state)) +#define DEV_P2P_GC_NUM(_dvobj) MSTATE_P2P_GC_NUM(&((_dvobj)->iface_state)) +#define DEV_P2P_GO_NUM(_dvobj) MSTATE_P2P_GO_NUM(&((_dvobj)->iface_state)) +#define DEV_SCAN_NUM(_dvobj) MSTATE_SCAN_NUM(&((_dvobj)->iface_state)) #define DEV_WPS_NUM(_dvobj) MSTATE_WPS_NUM(&((_dvobj)->iface_state)) #define DEV_ROCH_NUM(_dvobj) MSTATE_ROCH_NUM(&((_dvobj)->iface_state)) #define DEV_MGMT_TX_NUM(_dvobj) MSTATE_MGMT_TX_NUM(&((_dvobj)->iface_state)) @@ -1125,7 +1306,7 @@ static inline void dev_clr_drv_stopped(struct dvobj_priv *dvobj) #define dev_is_drv_stopped(dvobj) (ATOMIC_READ(&dvobj->bDriverStopped) == _TRUE) #ifdef PLATFORM_LINUX -static struct device *dvobj_to_dev(struct dvobj_priv *dvobj) +static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj) { /* todo: get interface type from dvobj and the return the dev accordingly */ #ifdef RTW_DVOBJ_CHIP_HW_TYPE @@ -1160,6 +1341,19 @@ enum _hw_port { MAX_HW_PORT, }; +#ifdef CONFIG_CLIENT_PORT_CFG +enum _client_port { + CLT_PORT0 = HW_PORT1, + CLT_PORT1 = HW_PORT2, + CLT_PORT2 = HW_PORT3, + CLT_PORT3 = HW_PORT4, + CLT_PORT_INVALID = HW_PORT0, +}; + +#define MAX_CLIENT_PORT_NUM 4 +#define get_clt_port(adapter) (adapter->client_port) +#endif + enum _ADAPTER_TYPE { PRIMARY_ADAPTER, VIRTUAL_ADAPTER, @@ -1207,11 +1401,6 @@ typedef struct loopbackdata { } LOOPBACKDATA, *PLOOPBACKDATA; #endif -struct tsf_info { - u8 sync_port;/*tsf sync from portx*/ - u8 offset; /*tsf timer offset*/ -}; - #define ADAPTER_TX_BW_2G(adapter) BW_MODE_2G((adapter)->driver_tx_bw_mode) #define ADAPTER_TX_BW_5G(adapter) BW_MODE_5G((adapter)->driver_tx_bw_mode) @@ -1220,13 +1409,19 @@ struct _ADAPTER { int pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */ int bDongle;/* build-in module or external dongle */ + #if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN) _list list; - + u8 vap_id; + #endif struct dvobj_priv *dvobj; struct mlme_priv mlmepriv; struct mlme_ext_priv mlmeextpriv; struct cmd_priv cmdpriv; struct evt_priv evtpriv; + +#ifdef CONFIG_RTW_80211K + struct rm_priv rmpriv; +#endif /* struct io_queue *pio_queue; */ struct io_priv iopriv; struct xmit_priv xmitpriv; @@ -1236,8 +1431,6 @@ struct _ADAPTER { _lock security_key_mutex; /* add for CONFIG_IEEE80211W, none 11w also can use */ struct registry_priv registrypriv; - struct led_priv ledpriv; - #ifdef CONFIG_RTW_NAPI struct napi_struct napi; u8 napi_state; @@ -1247,10 +1440,6 @@ struct _ADAPTER { struct mp_priv mppriv; #endif -#ifdef CONFIG_DRVEXT_MODULE - struct drvext_priv drvextpriv; -#endif - #ifdef CONFIG_AP_MODE struct hostapd_priv *phostapdpriv; #endif @@ -1276,6 +1465,9 @@ struct _ADAPTER { RT_WAPI_T wapiInfo; #endif +#ifdef CONFIG_RTW_REPEATER_SON + u8 rtw_rson_scanstage; +#endif #ifdef CONFIG_WFD struct wifi_display_info wfd_info; @@ -1307,22 +1499,21 @@ struct _ADAPTER { } gpiointpriv; #endif _thread_hdl_ cmdThread; +#ifdef CONFIG_EVENT_THREAD_MODE _thread_hdl_ evtThread; +#endif +#ifdef CONFIG_XMIT_THREAD_MODE _thread_hdl_ xmitThread; +#endif +#ifdef CONFIG_RECV_THREAD_MODE _thread_hdl_ recvThread; - +#endif u8 registered; #ifndef PLATFORM_LINUX NDIS_STATUS(*dvobj_init)(struct dvobj_priv *dvobj); void (*dvobj_deinit)(struct dvobj_priv *dvobj); #endif - u32(*intf_init)(struct dvobj_priv *dvobj); - void (*intf_deinit)(struct dvobj_priv *dvobj); - int (*intf_alloc_irq)(struct dvobj_priv *dvobj); - void (*intf_free_irq)(struct dvobj_priv *dvobj); - - void (*intf_start)(_adapter *adapter); void (*intf_stop)(_adapter *adapter); @@ -1382,13 +1573,11 @@ struct _ADAPTER { u8 netif_up; - u8 bFWReady; - u8 bBTFWReady; u8 bLinkInfoDump; - u8 bRxRSSIDisplay; /* Added by Albert 2012/10/26 */ /* The driver will show up the desired channel number when this flag is 1. */ u8 bNotifyChannelChange; + u8 bsta_tp_dump; #ifdef CONFIG_P2P /* Added by Albert 2012/12/06 */ /* The driver will show the current P2P status when the upper application reads it. */ @@ -1405,12 +1594,14 @@ struct _ADAPTER { ** refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.*/ u8 adapter_type;/*be used in Multi-interface to recognize whether is PRIMARY_ADAPTER or not(PRIMARY_ADAPTER/VIRTUAL_ADAPTER) .*/ u8 hw_port; /*interface port type, it depends on HW port */ - struct tsf_info tsf; + #ifdef CONFIG_CLIENT_PORT_CFG + u8 client_id; + u8 client_port; + #endif + /*struct tsf_info tsf;*//*reserve define for 8814B*/ /*extend to support multi interface*/ - /*IFACE_ID0 is equals to PRIMARY_ADAPTER - IFACE_ID1 is equals to VIRTUAL_ADAPTER*/ u8 iface_id; #ifdef CONFIG_BR_EXT @@ -1438,6 +1629,9 @@ struct _ADAPTER { #ifdef CONFIG_MAC_LOOPBACK_DRIVER PLOOPBACKDATA ploopback; #endif +#ifdef CONFIG_AP_MODE + u8 bmc_tx_rate; +#endif /* for debug purpose */ u8 fix_rate; @@ -1447,6 +1641,11 @@ struct _ADAPTER { u8 driver_tx_bw_mode; u8 rsvd_page_offset; u8 rsvd_page_num; +#ifdef CONFIG_SUPPORT_FIFO_DUMP + u8 fifo_sel; + u32 fifo_addr; + u32 fifo_size; +#endif u8 driver_vcs_en; /* Enable=1, Disable=0 driver control vrtl_carrier_sense for tx */ u8 driver_vcs_type;/* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */ @@ -1460,7 +1659,6 @@ struct _ADAPTER { u16 tx_amsdu_rate; #endif u8 driver_tx_max_agg_num; /*fix tx desc max agg num , 0xff: disable drv ctrl*/ - unsigned char in_cta_test; #ifdef DBG_RX_COUNTER_DUMP u8 dump_rx_cnt_mode;/*BIT0:drv,BIT1:mac,BIT2:phy*/ u32 drv_rx_cnt_ok; @@ -1477,6 +1675,16 @@ struct _ADAPTER { #ifdef CONFIG_MCC_MODE struct mcc_adapter_priv mcc_adapterpriv; #endif /* CONFIG_MCC_MODE */ + +#ifdef CONFIG_RTW_MESH + struct rtw_mesh_cfg mesh_cfg; + struct rtw_mesh_info mesh_info; + _timer mesh_path_timer; + _timer mesh_path_root_timer; + _timer mesh_atlm_param_req_timer; /* airtime link metrics param request timer */ + _workitem mesh_work; + unsigned long wrkq_flags; +#endif /* CONFIG_RTW_MESH */ }; #define adapter_to_dvobj(adapter) ((adapter)->dvobj) @@ -1490,8 +1698,15 @@ struct _ADAPTER { #endif #define adapter_to_rfctl(adapter) dvobj_to_rfctl(adapter_to_dvobj((adapter))) +#define adapter_to_macidctl(adapter) dvobj_to_macidctl(adapter_to_dvobj((adapter))) #define adapter_mac_addr(adapter) (adapter->mac_addr) +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI +#define adapter_pno_mac_addr(adapter) \ + ((adapter_wdev_data(adapter))->pno_mac_addr) +#endif + +#define adapter_to_chset(adapter) (adapter_to_rfctl((adapter))->channel_set) #define mlme_to_adapter(mlme) container_of((mlme), struct _ADAPTER, mlmepriv) #define tdls_info_to_adapter(tdls) container_of((tdls), struct _ADAPTER, tdlsinfo) diff --git a/include/drv_types_ce.h b/include/drv_types_ce.h index fc26389..c00dea8 100644 --- a/include/drv_types_ce.h +++ b/include/drv_types_ce.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_CE_H__ #define __DRV_TYPES_CE_H__ diff --git a/include/drv_types_gspi.h b/include/drv_types_gspi.h index f0efc8c..c22c497 100644 --- a/include/drv_types_gspi.h +++ b/include/drv_types_gspi.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_GSPI_H__ #define __DRV_TYPES_GSPI_H__ diff --git a/include/drv_types_linux.h b/include/drv_types_linux.h index 812b744..91ca68b 100644 --- a/include/drv_types_linux.h +++ b/include/drv_types_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_LINUX_H__ #define __DRV_TYPES_LINUX_H__ diff --git a/include/drv_types_pci.h b/include/drv_types_pci.h index c03657f..a3a4927 100644 --- a/include/drv_types_pci.h +++ b/include/drv_types_pci.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_PCI_H__ #define __DRV_TYPES_PCI_H__ diff --git a/include/drv_types_sdio.h b/include/drv_types_sdio.h index 3cc3f14..9feca12 100644 --- a/include/drv_types_sdio.h +++ b/include/drv_types_sdio.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_SDIO_H__ #define __DRV_TYPES_SDIO_H__ diff --git a/include/drv_types_xp.h b/include/drv_types_xp.h index 93766be..81c4504 100644 --- a/include/drv_types_xp.h +++ b/include/drv_types_xp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __DRV_TYPES_XP_H__ #define __DRV_TYPES_XP_H__ diff --git a/include/ethernet.h b/include/ethernet.h index e127605..2bafa4d 100644 --- a/include/ethernet.h +++ b/include/ethernet.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /*! \file */ #ifndef __INC_ETHERNET_H #define __INC_ETHERNET_H diff --git a/include/gspi_hal.h b/include/gspi_hal.h index 98fec09..6da0f07 100644 --- a/include/gspi_hal.h +++ b/include/gspi_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __GSPI_HAL_H__ #define __GSPI_HAL_H__ diff --git a/include/gspi_ops.h b/include/gspi_ops.h index 7a8cb63..bcfaad2 100644 --- a/include/gspi_ops.h +++ b/include/gspi_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __GSPI_OPS_H__ #define __GSPI_OPS_H__ diff --git a/include/gspi_ops_linux.h b/include/gspi_ops_linux.h index 9bd18da..0ba263d 100644 --- a/include/gspi_ops_linux.h +++ b/include/gspi_ops_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_OPS_LINUX_H__ #define __SDIO_OPS_LINUX_H__ diff --git a/include/gspi_osintf.h b/include/gspi_osintf.h index e51d2e4..6393f77 100644 --- a/include/gspi_osintf.h +++ b/include/gspi_osintf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_OSINTF_H__ #define __SDIO_OSINTF_H__ diff --git a/include/h2clbk.h b/include/h2clbk.h index e7f0df5..4e22afc 100644 --- a/include/h2clbk.h +++ b/include/h2clbk.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _H2CLBK_H_ diff --git a/include/hal_btcoex.h b/include/hal_btcoex.h index 531e91b..03021fe 100644 --- a/include/hal_btcoex.h +++ b/include/hal_btcoex.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_BTCOEX_H__ #define __HAL_BTCOEX_H__ @@ -42,6 +37,7 @@ void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum); u8 hal_btcoex_Initialize(PADAPTER padapter); void hal_btcoex_PowerOnSetting(PADAPTER padapter); +void hal_btcoex_AntInfoSetting(PADAPTER padapter); void hal_btcoex_PowerOffSetting(PADAPTER padapter); void hal_btcoex_PreLoadFirmware(PADAPTER padapter); void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly); @@ -91,6 +87,8 @@ u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data); u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val); void hal_btcoex_set_rfe_type(u8 type); void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type); +void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length); +void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id); #ifdef CONFIG_RF4CE_COEXIST void hal_btcoex_set_rf4ce_link_state(u8 state); diff --git a/include/hal_btcoex_wifionly.h b/include/hal_btcoex_wifionly.h index 2633d95..c18d20e 100644 --- a/include/hal_btcoex_wifionly.h +++ b/include/hal_btcoex_wifionly.h @@ -1,9 +1,32 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __HALBTC_WIFIONLY_H__ #define __HALBTC_WIFIONLY_H__ #include #include +/* Define the ICs that support wifi only cfg in coex. codes */ +#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) +#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 1 +#else +#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 0 +#endif + +#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1) + typedef enum _WIFIONLY_CHIP_INTERFACE { WIFIONLY_INTF_UNKNOWN = 0, WIFIONLY_INTF_PCI = 1, @@ -38,10 +61,21 @@ u8 halwifionly_read1byte(PVOID pwifionlyContext, u32 RegAddr); u16 halwifionly_read2byte(PVOID pwifionlyContext, u32 RegAddr); u32 halwifionly_read4byte(PVOID pwifionlyContext, u32 RegAddr); void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMask, u8 data); -void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); +void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data); void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data); void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter); void hal_btcoex_wifionly_scan_notify(PADAPTER padapter); +void hal_btcoex_wifionly_connect_notify(PADAPTER padapter); void hal_btcoex_wifionly_hw_config(PADAPTER padapter); void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter); +void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter); +#else +#define hal_btcoex_wifionly_switchband_notify(padapter) +#define hal_btcoex_wifionly_scan_notify(padapter) +#define hal_btcoex_wifionly_connect_notify(padapter) +#define hal_btcoex_wifionly_hw_config(padapter) +#define hal_btcoex_wifionly_initlizevariables(padapter) +#define hal_btcoex_wifionly_AntInfoSetting(padapter) +#endif + #endif diff --git a/include/hal_com.h b/include/hal_com.h index 77d13f4..11ee575 100644 --- a/include/hal_com.h +++ b/include/hal_com.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_COMMON_H__ #define __HAL_COMMON_H__ @@ -270,6 +265,8 @@ struct dbg_rx_counter { u32 rx_ht_fa; }; +u8 rtw_hal_get_port(_adapter *adapter); + #ifdef CONFIG_MBSSID_CAM #define DBG_MBID_CAM_DUMP @@ -280,12 +277,19 @@ struct dbg_rx_counter { u8 rtw_get_mbid_cam_entry_num(_adapter *adapter); int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name , _adapter *adapter); int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter); - void rtw_mbid_cam_restore(_adapter *adapter); + void rtw_mi_set_mbid_cam(_adapter *adapter); + u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr); + void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num); + void rtw_mbid_cam_enable(_adapter *adapter); #endif #ifdef CONFIG_MI_WITH_MBSSID_CAM void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr); void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr); + #ifdef CONFIG_SWTIMER_BASED_TXBCN + u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval); + #endif + void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode); #endif void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter); @@ -332,6 +336,10 @@ void rtw_hal_config_rftype(PADAPTER padapter); #define WL_FUNC_FTM BIT3 #define WL_FUNC_BIT_NUM 4 +#define TBTT_PROHIBIT_SETUP_TIME 0x04 /* 128us, unit is 32us */ +#define TBTT_PROHIBIT_HOLD_TIME 0x80 /* 4ms, unit is 32us*/ +#define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 /* 3.2ms unit is 32us*/ + int hal_spec_init(_adapter *adapter); void dump_hal_spec(void *sel, _adapter *adapter); @@ -345,7 +353,7 @@ u8 hal_largest_bw(_adapter *adapter, u8 in_bw); bool hal_chk_wl_func(_adapter *adapter, u8 func); -u8 hal_com_config_channel_plan( +void hal_com_config_channel_plan( IN PADAPTER padapter, IN char *hw_alpha2, IN u8 hw_chplan, @@ -356,6 +364,10 @@ u8 hal_com_config_channel_plan( ); int hal_config_macaddr(_adapter *adapter, bool autoload_fail); +#ifdef RTW_HALMAC +void rtw_hal_hw_port_enable(_adapter *adapter); +void rtw_hal_hw_port_disable(_adapter *adapter); +#endif BOOLEAN HAL_IsLegalChannel( @@ -379,7 +391,8 @@ Hal_MappingOutPipe( ); void rtw_dump_fw_info(void *sel, _adapter *adapter); -void rtw_restore_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/ +void rtw_restore_hw_port_cfg(_adapter *adapter); +void rtw_mi_set_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/ void rtw_hal_dump_macaddr(void *sel, _adapter *adapter); void rtw_init_hal_com_default_value(PADAPTER Adapter); @@ -394,9 +407,12 @@ void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len); void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len); #endif -u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta); u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type); -void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta); + +void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta); +s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta); +s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta); +void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta); /* access HW only */ u32 rtw_sec_read_cam(_adapter *adapter, u8 addr); @@ -406,15 +422,20 @@ void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id); bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id); -void rtw_hal_set_msr(_adapter *adapter, u8 net_type); -void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val); -void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr); +u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit); -void rtw_hal_set_bssid(_adapter *adapter, u8 *val); +u8 rtw_hal_rcr_add(_adapter *adapter, u32 add); +u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear); +void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action); + +void rtw_iface_enable_tsf_update(_adapter *adapter); +void rtw_iface_disable_tsf_update(_adapter *adapter); +void rtw_hal_periodic_tsf_update_chk(_adapter *adapter); +void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx); void hw_var_port_switch(_adapter *adapter); -void SetHwReg(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg(PADAPTER padapter, u8 variable, u8 *val); void rtw_hal_check_rxfifo_full(_adapter *adapter); void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid); @@ -486,13 +507,12 @@ void linked_info_dump(_adapter *padapter, u8 benable); #endif void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe); #define HWSET_MAX_SIZE 1024 + #ifdef CONFIG_EFUSE_CONFIG_FILE - #define EFUSE_FILE_COLUMN_NUM 16 - u32 Hal_readPGDataFromConfigFile(PADAPTER padapter); - u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr); +u32 Hal_readPGDataFromConfigFile(PADAPTER padapter); +u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr); #endif /* CONFIG_EFUSE_CONFIG_FILE */ -int check_phy_efuse_tx_power_info_valid(PADAPTER padapter); int hal_efuse_macaddr_offset(_adapter *adapter); int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr); void rtw_dump_cur_efuse(PADAPTER padapter); @@ -503,32 +523,17 @@ void rtw_dump_cur_efuse(PADAPTER padapter); void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer); u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel); -void GetHalODMVar( - PADAPTER Adapter, - HAL_ODM_VARIABLE eVariable, - PVOID pValue1, - PVOID pValue2); -void SetHalODMVar( - PADAPTER Adapter, - HAL_ODM_VARIABLE eVariable, - PVOID pValue1, - BOOLEAN bSet); - -#ifdef CONFIG_BACKGROUND_NOISE_MONITOR -struct noise_info { - u8 bPauseDIG; - u8 IGIValue; - u32 max_time;/* ms */ - u8 chan; -}; -#endif -void rtw_get_noise(_adapter *padapter); -u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid); -u8 rtw_get_current_tx_sgi(_adapter *padapter, u8 macid); -void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength, u8 *StaAddr, u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave); +u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta); +u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta); void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished); +u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter); + +#ifdef CONFIG_TSF_RESET_OFFLOAD +int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port); +#endif +u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port); #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW @@ -536,7 +541,7 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished); #endif #endif #if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) -s32 rtw_hal_set_wifi_port_id_cmd(_adapter *adapter); +s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter); #endif #ifdef CONFIG_GPIO_API @@ -557,50 +562,6 @@ void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case); void rtw_hal_set_input_gpio(_adapter *padapter, u8 index); #endif -typedef enum _HAL_PHYDM_OPS { - HAL_PHYDM_DIS_ALL_FUNC, - HAL_PHYDM_FUNC_SET, - HAL_PHYDM_FUNC_CLR, - HAL_PHYDM_ABILITY_BK, - HAL_PHYDM_ABILITY_RESTORE, - HAL_PHYDM_ABILITY_SET, - HAL_PHYDM_ABILITY_GET, -} HAL_PHYDM_OPS; - - -#define DYNAMIC_FUNC_DISABLE (0x0) -u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability); - -#define rtw_phydm_func_disable_all(adapter) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0) - -#define rtw_phydm_func_for_offchannel(adapter) \ - do { \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \ - if (rtw_odm_adaptivity_needed(adapter)) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \ - } while (0) - -#define rtw_phydm_func_set(adapter, ability) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ability) - -#define rtw_phydm_func_clr(adapter, ability) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability) - -#define rtw_phydm_ability_backup(adapter) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0) - -#define rtw_phydm_ability_restore(adapter) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0) - -#define rtw_phydm_ability_set(adapter, ability) \ - rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_SET, ability) - -static inline u32 rtw_phydm_ability_get(_adapter *adapter) -{ - return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0); -} - #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE extern char *rtw_phy_file_path; extern char rtw_phy_para_file_path[PATH_LENGTH_MAX]; @@ -609,19 +570,10 @@ static inline u32 rtw_phydm_ability_get(_adapter *adapter) void update_IOT_info(_adapter *padapter); -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - void rtw_acs_start(_adapter *padapter, bool bStart); -#endif - void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap); -void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf); void ResumeTxBeacon(_adapter *padapter); void StopTxBeacon(_adapter *padapter); -#ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/ - void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode); - u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr); -#endif #ifdef CONFIG_ANTENNA_DIVERSITY u8 rtw_hal_antdiv_before_linked(_adapter *padapter); @@ -651,13 +603,17 @@ void StopTxBeacon(_adapter *padapter); enum lps_pg_hdl_id { LPS_PG_INFO_CFG = 0, LPS_PG_REDLEMEM, - LPS_PG_RESEND_H2C, + LPS_PG_PHYDM_DIS, + LPS_PG_PHYDM_EN, }; u8 rtw_hal_set_lps_pg_info(_adapter *adapter); #endif int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size); +void rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength); +void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength, + u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave); #ifdef CONFIG_WOWLAN struct rtl_wow_pattern { @@ -671,14 +627,41 @@ void rtw_wow_pattern_cam_dump(_adapter *adapter); void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_pattern *context); void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx); #endif -#endif + +struct rtw_ndp_info { + u8 enable:1; + u8 check_remote_ip:1; /* Need to Check Sender IP or not */ + u8 rsvd:6; + u8 num_of_target_ip; /* Number of Check IP which NA query IP */ + u8 target_link_addr[6]; /* DUT's MAC address */ + u8 remote_ipv6_addr[16]; /* Just respond IP */ + u8 target_ipv6_addr[16]; /* target IP */ +}; +#define REMOTE_INFO_CTRL_SET_VALD_EN(target, _value) \ + SET_BITS_TO_LE_4BYTE(target + 0, 0, 8, _value) +#define REMOTE_INFO_CTRL_SET_PTK_EN(target, _value) \ + SET_BITS_TO_LE_4BYTE(target + 1, 0, 1, _value) +#define REMOTE_INFO_CTRL_SET_GTK_EN(target, _value) \ + SET_BITS_TO_LE_4BYTE(target + 1, 1, 1, _value) +#define REMOTE_INFO_CTRL_SET_GTK_IDX(target, _value) \ + SET_BITS_TO_LE_4BYTE(target + 2, 0, 8, _value) +#endif /*CONFIG_WOWLAN*/ + void rtw_dump_phy_cap(void *sel, _adapter *adapter); void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num); +#ifdef CONFIG_SUPPORT_FIFO_DUMP +void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size); +#endif #ifdef CONFIG_FW_MULTI_PORT_SUPPORT s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id); s32 rtw_set_default_port_id(_adapter *adapter); s32 rtw_set_ps_rsvd_page(_adapter *adapter); + +#define get_dft_portid(adapter) (adapter_to_dvobj(adapter)->dft.port_id) +#define get_dft_macid(adapter) (adapter_to_dvobj(adapter)->dft.mac_id) + +/*void rtw_search_default_port(_adapter *adapter);*/ #endif #ifdef CONFIG_P2P_PS @@ -687,4 +670,35 @@ void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state); #endif #endif +#ifdef RTW_CHANNEL_SWITCH_OFFLOAD +void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw); +#endif + +s16 translate_dbm_to_percentage(s16 signal); + +#ifdef CONFIG_SUPPORT_MULTI_BCN +void rtw_ap_multi_bcn_cfg(_adapter *adapter); +#endif + +#ifdef CONFIG_SWTIMER_BASED_TXBCN +#ifdef CONFIG_BCN_RECOVERY +u8 rtw_ap_bcn_recovery(_adapter *padapter); +#endif +#ifdef CONFIG_BCN_XMIT_PROTECT +u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms); +#endif +#endif /*CONFIG_SWTIMER_BASED_TXBCN*/ + +#ifdef CONFIG_FW_HANDLE_TXBCN +void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 mbcn_id); +void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 mbcn_id); +#endif + +void rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type, + enum bb_path *tx, enum bb_path *rx); +#ifdef CONFIG_BEAMFORMING +#ifdef RTW_BEAMFORMING_VERSION_2 +void rtw_hal_beamforming_config_csirate(PADAPTER adapter); +#endif +#endif #endif /* __HAL_COMMON_H__ */ diff --git a/include/hal_com_h2c.h b/include/hal_com_h2c.h index e80701c..a7bccaa 100644 --- a/include/hal_com_h2c.h +++ b/include/hal_com_h2c.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __COMMON_H2C_H__ #define __COMMON_H2C_H__ @@ -40,14 +35,16 @@ enum h2c_cmd { H2C_FCS_INFO = 0x11, H2C_AP_WOW_GPIO_CTRL = 0x13, #ifdef CONFIG_MCC_MODE - H2C_MCC_UPDATE_PARAM = 0x15, + H2C_MCC_RQT_TSF = 0x15, H2C_MCC_MACID_BITMAP = 0x16, H2C_MCC_LOCATION = 0x10, + H2C_MCC_CTRL_V2 = 0x17, H2C_MCC_CTRL = 0x18, - H2C_MCC_NOA_PARAM = 0x19, + H2C_MCC_TIME_SETTING = 0x19, H2C_MCC_IQK_PARAM = 0x1A, #endif /* CONFIG_MCC_MODE */ H2C_CHNL_SWITCH_OPER_OFFLOAD = 0x1C, + H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D, /* PoweSave Class: 001 */ H2C_SET_PWR_MODE = 0x20, @@ -83,7 +80,9 @@ enum h2c_cmd { H2C_DYNAMIC_TX_PATH = 0x48,/* for 8814A */ H2C_FW_TRACE_EN = 0x49, - +#ifdef RTW_PER_CMD_SUPPORT_FW + H2C_REQ_PER_RPT = 0x4e, +#endif /* BT Class: 011 */ H2C_B_TYPE_TDMA = 0x60, H2C_BT_INFO = 0x61, @@ -111,12 +110,19 @@ enum h2c_cmd { H2C_AOAC_RSVDPAGE3 = 0x88, H2C_P2P_OFFLOAD_RSVD_PAGE = 0x8A, H2C_P2P_OFFLOAD = 0x8B, - +#ifdef CONFIG_FW_HANDLE_TXBCN + H2C_FW_BCN_OFFLOAD = 0xBA, +#endif H2C_RESET_TSF = 0xC0, +#ifdef CONFIG_FW_CORRECT_BCN H2C_BCNHWSEQ = 0xC5, +#endif H2C_CUSTOMER_STR_W1 = 0xC6, H2C_CUSTOMER_STR_W2 = 0xC7, H2C_CUSTOMER_STR_W3 = 0xC8, +#ifdef DBG_FW_DEBUG_MSG_PKT + H2C_FW_DBG_MSG_PKT = 0xE1, +#endif /*DBG_FW_DEBUG_MSG_PKT*/ H2C_MAXID, }; @@ -137,7 +143,7 @@ enum h2c_cmd { #define H2C_PSTUNEPARAM_LEN 4 #define H2C_MACID_CFG_LEN 7 #define H2C_BTMP_OPER_LEN 5 -#define H2C_WOWLAN_LEN 5 +#define H2C_WOWLAN_LEN 7 #define H2C_REMOTE_WAKE_CTRL_LEN 3 #define H2C_AOAC_GLOBAL_INFO_LEN 2 #define H2C_AOAC_RSVDPAGE_LOC_LEN 7 @@ -152,10 +158,14 @@ enum h2c_cmd { #define H2C_P2P_OFFLOAD_LEN 3 #ifdef CONFIG_MCC_MODE #define H2C_MCC_CTRL_LEN 7 +#ifdef CONFIG_MCC_MODE_V2 + #define H2C_MCC_LOCATION_LEN 7 +#else #define H2C_MCC_LOCATION_LEN 3 +#endif #define H2C_MCC_MACID_BITMAP_LEN 6 - #define H2C_MCC_UPDATE_INFO_LEN 4 - #define H2C_MCC_NOA_PARAM_LEN 4 + #define H2C_MCC_RQT_TSF_LEN 1 + #define H2C_MCC_TIME_SETTING_LEN 6 #define H2C_MCC_IQK_PARAM_LEN 7 #endif /* CONFIG_MCC_MODE */ #ifdef CONFIG_LPS_PG @@ -170,35 +180,19 @@ enum h2c_cmd { #if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) #define H2C_BTC_WL_PORT_ID_LEN 1 #endif + +#ifdef DBG_FW_DEBUG_MSG_PKT + #define H2C_FW_DBG_MSG_PKT_LEN 2 +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + +#define H2C_SINGLE_CHANNELSWITCH_V2_LEN 2 + #define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0) #define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5]) #define cpIpAddr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3]) #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -/* -* ARP packet -* -* LLC Header */ -#define GET_ARP_PKT_LLC_TYPE(__pHeader) ReadLE2Byte(((u8 *)(__pHeader)) + 6) - -/* ARP element */ -#define GET_ARP_PKT_OPERATION(__pHeader) ReadLE2Byte(((u8 *)(__pHeader)) + 6) -#define GET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cp_mac_addr((u8 *)(_val), ((u8 *)(__pHeader))+8) -#define GET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr((u8 *)(_val), ((u8 *)(__pHeader))+14) -#define GET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cp_mac_addr((u8 *)(_val), ((u8 *)(__pHeader))+18) -#define GET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr((u8 *)(_val), ((u8 *)(__pHeader))+24) - -#define SET_ARP_PKT_HW(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 0, __Value) -#define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 2, __Value) -#define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 4, __Value) -#define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 5, __Value) -#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 6, __Value) -#define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cp_mac_addr(((u8 *)(__pHeader))+8, (u8 *)(_val)) -#define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8 *)(__pHeader))+14, (u8 *)(_val)) -#define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cp_mac_addr(((u8 *)(__pHeader))+18, (u8 *)(_val)) -#define SET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr(((u8 *)(__pHeader))+24, (u8 *)(_val)) - #define FW_WOWLAN_FUN_EN BIT(0) #define FW_WOWLAN_PATTERN_MATCH BIT(1) #define FW_WOWLAN_MAGIC_PKT BIT(2) @@ -254,7 +248,8 @@ enum h2c_cmd { #define H2C_MSR_ROLE_GO 4 #define H2C_MSR_ROLE_TDLS 5 #define H2C_MSR_ROLE_ADHOC 6 -#define H2C_MSR_ROLE_MAX 7 +#define H2C_MSR_ROLE_MESH 7 +#define H2C_MSR_ROLE_MAX 8 extern const char *const _h2c_msr_role_str[]; #define h2c_msr_role_str(role) (((role) >= H2C_MSR_ROLE_MAX) ? _h2c_msr_role_str[H2C_MSR_ROLE_MAX] : _h2c_msr_role_str[(role)]) @@ -362,12 +357,36 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); #ifdef CONFIG_MCC_MODE /* MCC LOC CMD 0x10 */ #define SET_H2CCMD_MCC_RSVDPAGE_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 1, __Value) +#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 4, 4, __Value) +#define SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 4, 0, 8, __Value) + +/* MCC RQT TSF 0x15 */ +#define SET_H2CCMD_MCC_RQT_TSFX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_H2CCMD_MCC_RQT_TSFY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) /* MCC MAC ID CMD 0x16 */ #define SET_H2CCMD_MCC_MACID_BITMAP_L(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) #define SET_H2CCMD_MCC_MACID_BITMAP_H(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -/* MCC INFO CMD 0x18 */ +/* NEW MCC CTRL CMD 0x17 */ +#define SET_H2CCMD_MCC_CTRL_V2_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_INCURCH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_C2HRPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 6, 2, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_TSFX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 4, 4, __Value) +#define SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value) + + +/* MCC CTRL CMD 0x18 */ #define SET_H2CCMD_MCC_CTRL_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) #define SET_H2CCMD_MCC_CTRL_TOTALNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) #define SET_H2CCMD_MCC_CTRL_CHIDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) @@ -384,12 +403,16 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); #define SET_H2CCMD_MCC_CTRL_C2HRPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 5, 2, __Value) #define SET_H2CCMD_MCC_CTRL_CHSCAN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value) -/* MCC NoA CMD 0x19 */ -#define SET_H2CCMD_MCC_NOA_FW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_H2CCMD_MCC_NOA_TSF_SYNC_OFFSET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value) -#define SET_H2CCMD_MCC_NOA_START_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) -#define SET_H2CCMD_MCC_NOA_INTERVAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) -#define SET_H2CCMD_MCC_EARLY_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +/* MCC Time CMD 0x19 */ +#define SET_H2CCMD_MCC_TIME_SETTING_FW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_START_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 4, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 1, __Value) +#define SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 1, 7, __Value) /* MCC IQK CMD 0x1A */ #define SET_H2CCMD_MCC_IQK_READY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) @@ -412,6 +435,12 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); #define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 5, 3, __Value) #define SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 4, __Value) +/* H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D */ +#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 4, __Value) +#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 4, 4, __Value) + + #if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT) #define SET_H2CCMD_BTC_WL_PORT_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) #endif @@ -437,6 +466,9 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); #define SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value) #define SET_H2CCMD_WOWLAN_TAKE_PDN_UPHY_DIS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value) #define SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value) +#define SET_H2CCMD_WOWLAN_DEV2HST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 7, 1, __Value) +#define SET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) +#define SET_H2CCMD_WOWLAN_RISE_HST2DEV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 2, 1, __Value) /* _REMOTE_WAKEUP_CMD_0x81 */ #define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) @@ -466,6 +498,8 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); #ifdef CONFIG_GTK_OL #define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) #endif /* CONFIG_GTK_OL */ +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(__pH2CCmd, __Value) \ + SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value) /* AOAC_RSVDPAGE_2_0x84 */ @@ -504,6 +538,11 @@ s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); #define SET_H2CCMD_LPSPG_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)/*Loc_LPS_PG*/ #endif +#ifdef DBG_FW_DEBUG_MSG_PKT +#define SET_H2CCMD_FW_DBG_MSG_PKT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*sniffer_dbg_en*/ +#define SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) /*loc_debug_packet*/ +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + /* --------------------------------------------------------------------------------------------------------- * ------------------------------------------- Structure -------------------------------------------------- * --------------------------------------------------------------------------------------------------------- */ @@ -524,6 +563,7 @@ typedef struct _RSVDPAGE_LOC { #ifdef CONFIG_GTK_OL u8 LocGTKEXTMEM; #endif /* CONFIG_GTK_OL */ + u8 LocNDPInfo; u8 LocAOACReport; #ifdef CONFIG_PNO_SUPPORT u8 LocPNOInfo; @@ -540,6 +580,9 @@ typedef struct _RSVDPAGE_LOC { u8 LocInviteRsp; u8 LocPDRsp; #endif /* CONFIG_P2P_WOWLAN */ +#ifdef DBG_FW_DEBUG_MSG_PKT + u8 loc_fw_dbg_msg_pkt; +#endif /*DBG_FW_DEBUG_MSG_PKT*/ } RSVDPAGE_LOC, *PRSVDPAGE_LOC; #endif @@ -555,3 +598,8 @@ u8 rtw_hal_set_fw_media_status_cmd(_adapter *adapter, u8 mstatus, u8 macid); u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter); #endif /* CONFIG_P2P_WOWLAN */ #endif + +#ifdef RTW_PER_CMD_SUPPORT_FW +u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid, + u8 rpt_type, u32 macid_bitmap); +#endif diff --git a/include/hal_com_led.h b/include/hal_com_led.h index e3c2cd9..d88556d 100644 --- a/include/hal_com_led.h +++ b/include/hal_com_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,16 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_COMMON_LED_H_ #define __HAL_COMMON_LED_H_ +#define NO_LED 0 +#define HW_LED 1 +#ifdef CONFIG_RTW_LED #define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) /* ******************************************************************************** @@ -103,17 +101,21 @@ typedef enum _LED_CTL_MODE { LED_CTL_POWER_ON = 1, LED_CTL_LINK = 2, LED_CTL_NO_LINK = 3, - LED_CTL_TX = 4, - LED_CTL_RX = 5, - LED_CTL_SITE_SURVEY = 6, - LED_CTL_POWER_OFF = 7, - LED_CTL_START_TO_LINK = 8, - LED_CTL_START_WPS = 9, - LED_CTL_STOP_WPS = 10, - LED_CTL_START_WPS_BOTTON = 11, /* added for runtop */ - LED_CTL_STOP_WPS_FAIL = 12, /* added for ALPHA */ - LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, /* added for BELKIN */ - LED_CTL_CONNECTION_NO_TRANSFER = 14, + LED_CTL_TX = 4, /* unspecific data TX, including single & group addressed */ + LED_CTL_RX = 5, /* unspecific data RX, including single & group addressed */ + LED_CTL_UC_TX = 6, /* single addressed data TX */ + LED_CTL_UC_RX = 7, /* single addressed data RX */ + LED_CTL_BMC_TX = 8, /* group addressed data TX */ + LED_CTL_BMC_RX = 9, /* group addressed data RX */ + LED_CTL_SITE_SURVEY = 10, + LED_CTL_POWER_OFF = 11, + LED_CTL_START_TO_LINK = 12, + LED_CTL_START_WPS = 13, + LED_CTL_STOP_WPS = 14, + LED_CTL_START_WPS_BOTTON = 15, /* added for runtop */ + LED_CTL_STOP_WPS_FAIL = 16, /* added for ALPHA */ + LED_CTL_STOP_WPS_FAIL_OVERLAP = 17, /* added for BELKIN */ + LED_CTL_CONNECTION_NO_TRANSFER = 18, } LED_CTL_MODE; typedef enum _LED_STATE { @@ -159,6 +161,8 @@ typedef enum _LED_PIN { * ******************************************************************************** */ #ifdef CONFIG_PCI_HCI typedef enum _LED_STRATEGY_PCIE { + /* start from 2 */ + SW_LED_MODE_UC_TRX_ONLY = 2, SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */ SW_LED_MODE1, /* SW control for PCI Express */ SW_LED_MODE2, /* SW control for Cameo. */ @@ -172,7 +176,6 @@ typedef enum _LED_STRATEGY_PCIE { SW_LED_MODE10, /* added by chiyokolin, for Edimax-ASUS */ SW_LED_MODE11, /* added by hpfan, for Xavi */ SW_LED_MODE12, /* added by chiyokolin, for Azurewave */ - HW_LED, /* HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes) */ } LED_STRATEGY_PCIE, *PLED_STRATEGY_PCIE; typedef struct _LED_PCIE { @@ -220,6 +223,8 @@ gen_RefreshLedState( typedef enum _LED_STRATEGY_USB { + /* start from 2 */ + SW_LED_MODE_UC_TRX_ONLY = 2, SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */ SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */ SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */ @@ -236,7 +241,6 @@ typedef enum _LED_STRATEGY_USB { SW_LED_MODE13, /* for Netgear A6100, 8811Au */ SW_LED_MODE14, /* for Buffalo, DNI, 8811Au */ SW_LED_MODE15, /* for DLINK, 8811Au/8812AU */ - HW_LED, /* HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) */ } LED_STRATEGY_USB, *PLED_STRATEGY_USB; @@ -269,12 +273,13 @@ typedef struct _LED_USB { typedef struct _LED_USB LED_DATA, *PLED_DATA; typedef enum _LED_STRATEGY_USB LED_STRATEGY, *PLED_STRATEGY; - +#ifdef CONFIG_RTW_SW_LED VOID LedControlUSB( IN PADAPTER Adapter, IN LED_CTL_MODE LedAction ); +#endif /* ******************************************************************************** @@ -291,6 +296,8 @@ LedControlUSB( typedef enum _LED_STRATEGY_SDIO { + /* start from 2 */ + SW_LED_MODE_UC_TRX_ONLY = 2, SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */ SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */ SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */ @@ -298,7 +305,6 @@ typedef enum _LED_STRATEGY_SDIO { SW_LED_MODE4, /* for Edimax / Belkin */ SW_LED_MODE5, /* for Sercomm / Belkin */ SW_LED_MODE6, /* for 88CU minicard, porting from ce SW_LED_MODE7 */ - HW_LED, /* HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) */ } LED_STRATEGY_SDIO, *PLED_STRATEGY_SDIO; typedef struct _LED_SDIO { @@ -339,41 +345,33 @@ LedControlSDIO( #endif struct led_priv { - /* add for led controll */ + LED_STRATEGY LedStrategy; +#ifdef CONFIG_RTW_SW_LED LED_DATA SwLed0; LED_DATA SwLed1; LED_DATA SwLed2; - LED_STRATEGY LedStrategy; u8 bRegUseLed; + u8 iface_en_mask; + u32 ctl_en_mask[CONFIG_IFACE_NUMBER]; void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction); void (*SwLedOn)(_adapter *padapter, PLED_DATA pLed); void (*SwLedOff)(_adapter *padapter, PLED_DATA pLed); - /* add for led controll */ +#endif }; -#ifdef CONFIG_SW_LED -#define rtw_led_control(adapter, LedAction) \ - do { \ - if ((adapter)->ledpriv.LedControlHandler) \ - (adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \ - } while (0) -#else /* CONFIG_SW_LED */ -#define rtw_led_control(adapter, LedAction) -#endif /* CONFIG_SW_LED */ - #define SwLedOn(adapter, pLed) \ do { \ - if ((adapter)->ledpriv.SwLedOn) \ - (adapter)->ledpriv.SwLedOn((adapter), (pLed)); \ + if (adapter_to_led(adapter)->SwLedOn) \ + adapter_to_led(adapter)->SwLedOn((adapter), (pLed)); \ } while (0) #define SwLedOff(adapter, pLed) \ do { \ - if ((adapter)->ledpriv.SwLedOff) \ - (adapter)->ledpriv.SwLedOff((adapter), (pLed)); \ + if (adapter_to_led(adapter)->SwLedOff) \ + adapter_to_led(adapter)->SwLedOff((adapter), (pLed)); \ } while (0) -void BlinkTimerCallback(struct timer_list *t); +void BlinkTimerCallback(void *data); void BlinkWorkItemCallback(_workitem *work); void ResetLedStatus(PLED_DATA pLed); @@ -392,5 +390,48 @@ DeInitLed( /* hal... */ extern void BlinkHandler(PLED_DATA pLed); +void dump_led_config(void *sel, _adapter *adapter); +void rtw_led_set_strategy(_adapter *adapter, u8 strategy); +#endif /* CONFIG_RTW_LED */ + +#if defined(CONFIG_RTW_LED) +#define rtw_led_get_strategy(adapter) (adapter_to_led(adapter)->LedStrategy) +#else +#define rtw_led_get_strategy(adapter) NO_LED +#endif + +#define IS_NO_LED_STRATEGY(s) ((s) == NO_LED) +#define IS_HW_LED_STRATEGY(s) ((s) == HW_LED) +#define IS_SW_LED_STRATEGY(s) ((s) != NO_LED && (s) != HW_LED) + +#if defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) + +#ifndef CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY +#define CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY 0 +#endif + +#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY +void rtw_sw_led_blink_uc_trx_only(LED_DATA *led); +void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl); +#endif +void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl); +void rtw_led_tx_control(_adapter *adapter, const u8 *da); +void rtw_led_rx_control(_adapter *adapter, const u8 *da); +void rtw_led_set_iface_en(_adapter *adapter, u8 en); +void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask); +void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask); +void rtw_led_set_ctl_en_mask_primary(_adapter *adapter); +void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter); +#else +#define rtw_led_control(adapter, ctl) do {} while (0) +#define rtw_led_tx_control(adapter, da) do {} while (0) +#define rtw_led_rx_control(adapter, da) do {} while (0) +#define rtw_led_set_iface_en(adapter, en) do {} while (0) +#define rtw_led_set_iface_en_mask(adapter, mask) do {} while (0) +#define rtw_led_set_ctl_en_mask(adapter, ctl_mask) do {} while (0) +#define rtw_led_set_ctl_en_mask_primary(adapter) do {} while (0) +#define rtw_led_set_ctl_en_mask_virtual(adapter) do {} while (0) +#endif /* defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) */ + +#endif /*__HAL_COMMON_LED_H_*/ -#endif /* __RTW_LED_H_ */ diff --git a/include/hal_com_phycfg.h b/include/hal_com_phycfg.h index fb86c2b..51d6429 100644 --- a/include/hal_com_phycfg.h +++ b/include/hal_com_phycfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_COM_PHYCFG_H__ #define __HAL_COM_PHYCFG_H__ @@ -34,20 +29,6 @@ typedef enum _RF_TX_NUM { RF_TX_NUM_NONIMPLEMENT, } RF_TX_NUM; -#define MAX_POWER_INDEX 0x3F - -typedef enum _REGULATION_TXPWR_LMT { - TXPWR_LMT_FCC = 0, - TXPWR_LMT_MKK = 1, - TXPWR_LMT_ETSI = 2, - TXPWR_LMT_WW = 3, - - TXPWR_LMT_MAX_REGULATION_NUM = 4 -} REGULATION_TXPWR_LMT; - -#define TX_PWR_LMT_REF_VHT_FROM_HT BIT0 -#define TX_PWR_LMT_REF_HT_FROM_VHT BIT1 - /*------------------------------Define structure----------------------------*/ typedef struct _BB_REGISTER_DEFINITION { u32 rfintfs; /* set software control: */ @@ -79,7 +60,6 @@ PHY_GetTxPowerByRateBase( IN PADAPTER Adapter, IN u8 Band, IN u8 RfPath, - IN u8 TxNum, IN RATE_SECTION RateSection ); @@ -102,7 +82,7 @@ PHY_GetRateIndexOfTxPowerByRate( VOID phy_set_tx_power_index_by_rate_section( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Channel, IN u8 RateSection ); @@ -111,8 +91,7 @@ s8 _PHY_GetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, + IN enum rf_path RFPath, IN u8 RateIndex ); @@ -120,28 +99,15 @@ s8 PHY_GetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, + IN enum rf_path RFPath, IN u8 RateIndex ); -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI -s8 -PHY_GetTxPowerByRateOriginal( - IN PADAPTER pAdapter, - IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, - IN u8 Rate -); -#endif - VOID PHY_SetTxPowerByRate( IN PADAPTER pAdapter, IN u8 Band, - IN u8 RFPath, - IN u8 TxNum, + IN enum rf_path RFPath, IN u8 Rate, IN s8 Value ); @@ -156,8 +122,8 @@ phy_set_tx_power_level_by_path( VOID PHY_SetTxPowerIndexByRateArray( IN PADAPTER pAdapter, - IN u8 RFPath, - IN CHANNEL_WIDTH BandWidth, + IN enum rf_path RFPath, + IN enum channel_width BandWidth, IN u8 Channel, IN u8 *Rates, IN u8 RateArraySize @@ -187,66 +153,47 @@ PHY_TxPowerByRateConfiguration( u8 PHY_GetTxPowerIndexBase( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, + u8 ntx_idx, + IN enum channel_width BandWidth, IN u8 Channel, OUT PBOOLEAN bIn24G ); -s8 -PHY_GetTxPowerLimit( - IN PADAPTER Adapter, - IN u32 RegPwrTblSel, - IN BAND_TYPE Band, - IN CHANNEL_WIDTH Bandwidth, - IN u8 RfPath, - IN u8 DataRate, - IN u8 Channel +#ifdef CONFIG_TXPWR_LIMIT +s8 phy_get_txpwr_lmt_abs(_adapter *adapter + , const char *regd_name + , BAND_TYPE band, enum channel_width bw + , u8 tlrs, u8 ntx_idx, u8 cch, u8 lock ); -s8 -PHY_GetTxPowerLimit_no_sc( - IN PADAPTER Adapter, - IN u32 RegPwrTblSel, - IN BAND_TYPE Band, - IN CHANNEL_WIDTH Bandwidth, - IN u8 RfPath, - IN u8 DataRate, - IN u8 Channel -); - -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI -s8 -PHY_GetTxPowerLimitOriginal( - IN PADAPTER Adapter, - IN u32 RegPwrTblSel, - IN BAND_TYPE Band, - IN CHANNEL_WIDTH Bandwidth, - IN u8 RfPath, - IN u8 DataRate, - IN u8 Channel +s8 phy_get_txpwr_lmt(_adapter *adapter + , const char *regd_name + , BAND_TYPE band, enum channel_width bw + , u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock ); -#endif -VOID -PHY_ConvertTxPowerLimitToPowerIndex( - IN PADAPTER Adapter -); - -VOID -PHY_InitTxPowerLimit( - IN PADAPTER Adapter +s8 PHY_GetTxPowerLimit(_adapter *adapter + , const char *regd_name + , BAND_TYPE band, enum channel_width bw + , u8 rfpath, u8 rate, u8 ntx_idx, u8 cch ); +#else +#define phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max) +#define phy_get_txpwr_lmt(adapter, regd_name, band, bw, rfpath, rs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max) +#define PHY_GetTxPowerLimit(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch) (GET_HAL_SPEC(adapter)->txgi_max) +#endif /* CONFIG_TXPWR_LIMIT */ s8 PHY_GetTxPowerTrackingOffset( PADAPTER pAdapter, - u8 Rate, - u8 RFPath + enum rf_path RFPath, + u8 Rate ); struct txpwr_idx_comp { + u8 ntx_idx; u8 base; s8 by_rate; s8 limit; @@ -257,9 +204,9 @@ struct txpwr_idx_comp { u8 phy_get_tx_power_index( IN PADAPTER pAdapter, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate, - IN CHANNEL_WIDTH BandWidth, + IN enum channel_width BandWidth, IN u8 Channel ); @@ -267,7 +214,7 @@ VOID PHY_SetTxPowerIndex( IN PADAPTER pAdapter, IN u32 PowerIndex, - IN u8 RFPath, + IN enum rf_path RFPath, IN u8 Rate ); @@ -278,15 +225,18 @@ void dump_tx_power_idx(void *sel, _adapter *adapter); bool phy_is_tx_power_limit_needed(_adapter *adapter); bool phy_is_tx_power_by_rate_needed(_adapter *adapter); int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file); +#ifdef CONFIG_TXPWR_LIMIT int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file); +#endif void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file); void phy_reload_tx_power_ext_info(_adapter *adapter); void phy_reload_default_tx_power_ext_info(_adapter *adapter); const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter); -void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt); -void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt); +#ifdef CONFIG_EFUSE_CONFIG_FILE +int check_phy_efuse_tx_power_info_valid(_adapter *adapter); +#endif void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt); void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt); @@ -301,7 +251,6 @@ void hal_load_txpwr_info( void dump_tx_power_ext_info(void *sel, _adapter *adapter); void dump_target_tx_power(void *sel, _adapter *adapter); void dump_tx_power_by_rate(void *sel, _adapter *adapter); -void dump_tx_power_limit(void *sel, _adapter *adapter); int rtw_get_phy_file_path(_adapter *adapter, const char *file_name); @@ -338,11 +287,13 @@ int phy_ConfigMACWithParaFile(IN PADAPTER Adapter, IN char *pFileName); int phy_ConfigBBWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN u32 ConfigType); int phy_ConfigBBWithPgParaFile(IN PADAPTER Adapter, IN const char *pFileName); int phy_ConfigBBWithMpParaFile(IN PADAPTER Adapter, IN char *pFileName); -int PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN u8 eRFPath); +int PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN enum rf_path eRFPath); int PHY_ConfigRFWithTxPwrTrackParaFile(IN PADAPTER Adapter, IN char *pFileName); +#ifdef CONFIG_TXPWR_LIMIT int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER Adapter, IN const char *pFileName); +#endif void phy_free_filebuf_mask(_adapter *padapter, u8 mask); void phy_free_filebuf(_adapter *padapter); #endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */ - +u8 phy_check_under_survey_ch(_adapter *adapter); #endif /* __HAL_COMMON_H__ */ diff --git a/include/hal_com_reg.h b/include/hal_com_reg.h index debcc13..0611ff5 100644 --- a/include/hal_com_reg.h +++ b/include/hal_com_reg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_COMMON_REG_H__ #define __HAL_COMMON_REG_H__ @@ -262,7 +257,7 @@ #define REG_LIFETIME_CTRL 0x0426 #define REG_MULTI_BCNQ_OFFSET 0x0427 #define REG_SPEC_SIFS 0x0428 -#define REG_RL 0x042A +#define REG_RETRY_LIMIT 0x042A #define REG_DARFRC 0x0430 #define REG_RARFRC 0x0438 #define REG_RRSR 0x0440 @@ -318,6 +313,11 @@ #define REG_MACID_SLEEP 0x04D4 #define REG_NQOS_SEQ 0x04DC +#define REG_HW_SEQ0 0x04D8 +#define REG_HW_SEQ1 0x04DA +#define REG_HW_SEQ2 0x04DC +#define REG_HW_SEQ3 0x04DE + #define REG_QOS_SEQ 0x04DE #define REG_NEED_CPU_HANDLE 0x04E0 #define REG_PKT_LOSE_RPT 0x04E1 @@ -369,7 +369,7 @@ #define REG_BCN_CTRL_1 0x0551 #define REG_MBID_NUM 0x0552 #define REG_DUAL_TSF_RST 0x0553 -#define REG_BCN_INTERVAL 0x0554 /* The same as REG_MBSSID_BCN_SPACE */ +#define REG_MBSSID_BCN_SPACE 0x0554 #define REG_DRVERLYINT 0x0558 #define REG_BCNDMATIM 0x0559 #define REG_ATIMWND 0x055A @@ -384,6 +384,7 @@ #define REG_PSTIMER 0x0580 #define REG_TIMER0 0x0584 #define REG_TIMER1 0x0588 +#define REG_HIQ_NO_LMT_EN 0x05A7 #define REG_ACMHWCTRL 0x05C0 #define REG_NOA_DESC_SEL 0x05CF #define REG_NOA_DESC_DURATION 0x05E0 @@ -428,6 +429,8 @@ #define REG_CTS2TO 0x0641 #define REG_EIFS 0x0642 +/*REG_TCR*/ +#define BIT_PWRBIT_OW_EN BIT(7) /* RXERR_RPT */ #define RXERR_TYPE_OFDM_PPDU 0 @@ -489,9 +492,20 @@ #define REG_BCN_PSR_RPT 0x06A8 #define REG_BT_COEX_TABLE 0x06C0 +#define BIT_WKFCAM_WE BIT(16) +#define BIT_WKFCAM_POLLING_V1 BIT(31) +#define BIT_WKFCAM_CLR_V1 BIT(30) +#define BIT_SHIFT_WKFCAM_ADDR_V2 8 +#define BIT_MASK_WKFCAM_ADDR_V2 0xff +#define BIT_WKFCAM_ADDR_V2(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) + /* Hardware Port 1 */ #define REG_MACID1 0x0700 #define REG_BSSID1 0x0708 + +/* Enable/Disable Port 0 and Port 1 for Specific ICs (ex. 8192F)*/ +#define REG_WLAN_ACT_MASK_CTRL_1 0x076C + /* Hardware Port 2 */ #define REG_MACID2 0x1620 #define REG_BSSID2 0x1628 @@ -709,6 +723,7 @@ Default: 00b. ** REG_CCK_CHECK (offset 0x454) ------------------------------------------------------------------------------*/ #define BIT_BCN_PORT_SEL BIT(5) +#define BIT_EN_BCN_PKT_REL BIT(6) #endif /* RTW_HALMAC */ @@ -1377,7 +1392,8 @@ Current IOREG MAP #define QUEUE_LOW 1 #define QUEUE_NORMAL 2 #define QUEUE_HIGH 3 - +#define QUEUE_EXTRA_1 4 +#define QUEUE_EXTRA_2 5 /* 2 TRXFF_BNDY */ @@ -1479,9 +1495,20 @@ Current IOREG MAP #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) /* 2 RL */ -#define RETRY_LIMIT_SHORT_SHIFT 8 -#define RETRY_LIMIT_LONG_SHIFT 0 +#define BIT_SHIFT_SRL 8 +#define BIT_MASK_SRL 0x3f +#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL) + +#define BIT_SHIFT_LRL 0 +#define BIT_MASK_LRL 0x3f +#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL) +#define RL_VAL_AP 7 +#ifdef CONFIG_RTW_CUSTOMIZE_RLSTA +#define RL_VAL_STA CONFIG_RTW_CUSTOMIZE_RLSTA +#else +#define RL_VAL_STA 0x30 +#endif /* ----------------------------------------------------- * * 0x0500h ~ 0x05FFh EDCA Configuration @@ -1494,11 +1521,6 @@ Current IOREG MAP #define AC_PARAM_ECW_MIN_OFFSET 8 #define AC_PARAM_AIFS_OFFSET 0 - -#define _LRL(x) ((x) & 0x3F) -#define _SRL(x) (((x) & 0x3F) << 8) - - /* 2 BCN_CTRL */ #define EN_TXBCN_RPT BIT(2) #define EN_BCN_FUNCTION BIT(3) @@ -1509,19 +1531,14 @@ Current IOREG MAP #define DIS_BCNQ_SUB BIT(1) #define DIS_TSF_UDT BIT(4) -/* The same function but different bit field. */ -#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) -#define DIS_TSF_UDT0_TEST_CHIP BIT(5) - - /* 2 ACMHWCTRL */ #define AcmHw_HwEn BIT(0) -#define AcmHw_BeqEn BIT(1) +#define AcmHw_VoqEn BIT(1) #define AcmHw_ViqEn BIT(2) -#define AcmHw_VoqEn BIT(3) -#define AcmHw_BeqStatus BIT(4) -#define AcmHw_ViqStatus BIT(5) -#define AcmHw_VoqStatus BIT(6) +#define AcmHw_BeqEn BIT(3) +#define AcmHw_VoqStatus BIT(5) +#define AcmHw_ViqStatus BIT(6) +#define AcmHw_BeqStatus BIT(7) /* 2 */ /* REG_DUAL_TSF_RST (0x553) */ #define DUAL_TSF_RST_P2P BIT(4) @@ -1602,6 +1619,13 @@ Current IOREG MAP #define BIT_LSIC_TXOP_EN BIT(17) #define BIT_CTS_EN BIT(16) +/*REG_RXFLTMAP1 (Offset 0x6A2)*/ +#define BIT_CTRLFLT10EN BIT(10) /*PS-POLL*/ + +/*REG_WLAN_ACT_MASK_CTRL_1 (Offset 0x76C)*/ +#define EN_PORT_0_FUNCTION BIT(12) +#define EN_PORT_1_FUNCTION BIT(13) + /* ----------------------------------------------------- * * SDIO Bus Specification @@ -1643,6 +1667,7 @@ Current IOREG MAP #define SDIO_MAX_RX_QUEUE 1 #define SDIO_REG_TX_CTRL 0x0000 /* SDIO Tx Control */ +#define SDIO_REG_TIMEOUT 0x0002/*SDIO status timeout*/ #define SDIO_REG_HIMR 0x0014 /* SDIO Host Interrupt Mask */ #define SDIO_REG_HISR 0x0018 /* SDIO Host Interrupt Service Routine */ #define SDIO_REG_HCPWM 0x0019 /* HCI Current Power Mode */ @@ -1737,6 +1762,19 @@ Current IOREG MAP #define SDIO_TX_FREE_PG_QUEUE 4 /* The number of Tx FIFO free page */ #define SDIO_TX_FIFO_PAGE_SZ 128 +/* indirect access */ +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +#define SDIO_REG_INDIRECT_REG_CFG 0x40 +#define SDIO_REG_INDIRECT_REG_DATA 0x44 +#define SET_INDIRECT_REG_ADDR(_cmd, _addr) SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr)) +#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0) +#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1) +#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2) +#define SET_INDIRECT_REG_WRITE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1) +#define SET_INDIRECT_REG_READ(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1) +#define GET_INDIRECT_REG_RDY(_cmd) LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1) +#endif/*CONFIG_SDIO_INDIRECT_ACCESS*/ + #ifdef CONFIG_SDIO_HCI #define MAX_TX_AGG_PACKET_NUMBER 0x8 #else @@ -1803,15 +1841,21 @@ Current IOREG MAP * General definitions * ******************************************************** */ -#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) (IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175) +#ifdef CONFIG_USB_HCI + #define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) (175) +#else + #define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) (IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175) +#endif #define LAST_ENTRY_OF_TX_PKT_BUFFER_8812 255 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B 255 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C 255 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8703B 255 #define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8188F 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188GTV 255 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8723D 255 - +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8710B 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192F 255 #define POLLING_LLT_THRESHOLD 20 #if defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI) #define POLLING_READY_TIMEOUT_COUNT 6000 diff --git a/include/hal_data.h b/include/hal_data.h index ab33b05..bc46e87 100755 --- a/include/hal_data.h +++ b/include/hal_data.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_DATA_H__ #define __HAL_DATA_H__ @@ -26,6 +21,7 @@ #ifdef CONFIG_BT_COEXIST #include #endif + #include #ifdef CONFIG_SDIO_HCI #include @@ -33,6 +29,11 @@ #ifdef CONFIG_GSPI_HCI #include #endif + +#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR) +#include "../hal/hal_dm_acs.h" +#endif + /* * For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. * */ @@ -96,21 +97,6 @@ typedef enum _RT_AMPDU_BRUST_MODE { #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */ - -/* ###### duplicate code,will move to ODM ######### */ -/* #define IQK_MAC_REG_NUM 4 */ -/* #define IQK_ADDA_REG_NUM 16 */ - -/* #define IQK_BB_REG_NUM 10 */ -#define IQK_BB_REG_NUM_92C 9 -#define IQK_BB_REG_NUM_92D 10 -#define IQK_BB_REG_NUM_test 6 - -#define IQK_Matrix_Settings_NUM_92D (1+24+21) - -/* #define HP_THERMAL_NUM 8 */ -/* ###### duplicate code,will move to ODM ######### */ - #ifdef RTW_RX_AGGREGATION typedef enum _RX_AGG_MODE { RX_AGG_DISABLE, @@ -148,10 +134,19 @@ typedef enum _RX_AGG_MODE { #ifdef CONFIG_RTL8188F #define EFUSE_MAP_SIZE 512 #endif +#ifdef CONFIG_RTL8188GTV + #define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8710B + #define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8192F + #define EFUSE_MAP_SIZE 512 +#endif #if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) #define EFUSE_MAX_SIZE 1024 -#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8703B) +#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B) #define EFUSE_MAX_SIZE 256 #else #define EFUSE_MAX_SIZE 512 @@ -199,24 +194,6 @@ typedef struct _BB_INIT_REGISTER { #define HCI_SUS_ENTERING 3 #define HCI_SUS_ERR 4 -#ifdef CONFIG_AUTO_CHNL_SEL_NHM -typedef enum _ACS_OP { - ACS_INIT, /*ACS - Variable init*/ - ACS_RESET, /*ACS - NHM Counter reset*/ - ACS_SELECT, /*ACS - NHM Counter Statistics */ -} ACS_OP; - -typedef enum _ACS_STATE { - ACS_DISABLE, - ACS_ENABLE, -} ACS_STATE; - -struct auto_chan_sel { - ATOMIC_T state; - u8 ch; /* previous channel*/ -}; -#endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ - #define EFUSE_FILE_UNUSED 0 #define EFUSE_FILE_FAILED 1 #define EFUSE_FILE_LOADED 2 @@ -225,9 +202,6 @@ struct auto_chan_sel { #define MACADDR_FILE_FAILED 1 #define MACADDR_FILE_LOADED 2 -#define KFREE_FLAG_ON BIT(0) -#define KFREE_FLAG_THERMAL_K_ON BIT(1) - #define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 #define MAX_IQK_INFO_BACKUP_REG_NUM 10 @@ -253,6 +227,8 @@ struct hal_spec_t { u8 rfpath_num_2g:4; /* used for tx power index path */ u8 rfpath_num_5g:4; /* used for tx power index path */ + u8 txgi_max; /* maximum tx power gain index */ + u8 txgi_pdbm; /* tx power gain index per dBm */ u8 max_tx_cnt; u8 tx_nss_num:4; @@ -262,6 +238,12 @@ struct hal_spec_t { u8 port_num; u8 proto_cap; /* value of PROTO_CAP_XXX */ u8 wl_func; /* value of WL_FUNC_XXX */ + + u8 rx_tsf_filter:1; + + u8 pg_txpwr_saddr; /* starting address of PG tx power info */ + u8 pg_txgi_diff_factor; /* PG tx power gain index diff to tx power gain index */ + u8 hci_type; /* value of HCI Type */ }; @@ -322,6 +304,38 @@ typedef struct hal_p2p_ps_para { u32 noa_count_para; } HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA; +#define TXPWR_LMT_RS_CCK 0 +#define TXPWR_LMT_RS_OFDM 1 +#define TXPWR_LMT_RS_HT 2 +#define TXPWR_LMT_RS_VHT 3 +#define TXPWR_LMT_RS_NUM 4 + +#define TXPWR_LMT_RS_NUM_2G 4 /* CCK, OFDM, HT, VHT */ +#define TXPWR_LMT_RS_NUM_5G 3 /* OFDM, HT, VHT */ + +#ifdef CONFIG_TXPWR_LIMIT +extern const char *const _txpwr_lmt_rs_str[]; +#define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)]) + +struct txpwr_lmt_ent { + _list list; + + s8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM] + [TXPWR_LMT_RS_NUM_2G] + [CENTER_CH_2G_NUM] + [MAX_TX_COUNT]; + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + s8 lmt_5g[MAX_5G_BANDWIDTH_NUM] + [TXPWR_LMT_RS_NUM_5G] + [CENTER_CH_5G_ALL_NUM] + [MAX_TX_COUNT]; +#endif + + char regd_name[0]; +}; +#endif /* CONFIG_TXPWR_LIMIT */ + typedef struct hal_com_data { HAL_VERSION version_id; RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */ @@ -335,13 +349,14 @@ typedef struct hal_com_data { u16 firmware_sub_version; u16 FirmwareSignature; u8 RegFWOffload; + u8 bFWReady; + u8 bBTFWReady; u8 fw_ractrl; - u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/ u8 LastHMEBoxNum; /* H2C - for host message to fw */ /****** current WIFI_PHY values ******/ WIRELESS_MODE CurrentWirelessMode; - CHANNEL_WIDTH current_channel_bw; + enum channel_width current_channel_bw; BAND_TYPE current_band_type; /* 0:2.4G, 1:5G */ BAND_TYPE BandSet; u8 current_channel; @@ -355,6 +370,7 @@ typedef struct hal_com_data { u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ u16 BasicRateSet; u32 ReceiveConfig; + u32 rcr_backup; /* used for switching back from monitor mode */ u8 rx_tsf_addr_filter_config; /* for 8822B/8821C USE */ BOOLEAN bSwChnl; BOOLEAN bSetChnlBW; @@ -362,22 +378,25 @@ typedef struct hal_com_data { BOOLEAN bSWToBW80M; BOOLEAN bChnlBWInitialized; u32 BackUp_BB_REG_4_2nd_CCA[3]; -#ifdef CONFIG_AUTO_CHNL_SEL_NHM + +#ifdef CONFIG_RTW_ACS struct auto_chan_sel acs; #endif +#ifdef CONFIG_BCN_RECOVERY + u8 issue_bcn_fail; +#endif /*CONFIG_BCN_RECOVERY*/ + /****** rf_ctrl *****/ u8 rf_chip; - u8 rf_type; + u8 rf_type; /*enum rf_type*/ u8 PackageType; u8 NumTotalRFPath; u8 antenna_test; /****** Debug ******/ u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ - u8 u1ForcedIgiLb; /* forced IGI lower bound */ u8 bDumpRxPkt; u8 bDumpTxPkt; - u8 bDisableTXPowerTraining; u8 dis_turboedca; @@ -425,7 +444,9 @@ typedef struct hal_com_data { #endif /*CONFIG_RF_POWER_TRIM*/ #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \ - defined(CONFIG_RTL8723D) + defined(CONFIG_RTL8723D) || \ + defined(CONFIG_RTL8192F) + u8 adjuseVoltageVal; u8 need_restore; #endif @@ -453,74 +474,17 @@ typedef struct hal_com_data { s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; #endif - u8 Regulation2_4G; - u8 Regulation5G; - - /******************************** - * TX power by rate table at most 4RF path. - * The register is - * - * VHT TX power by rate off setArray = - * Band:-2G&5G = 0 / 1 - * RF: at most 4*4 = ABCD=0/1/2/3 - * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 - **********************************/ - u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND] [TX_PWR_BY_RATE_NUM_RF]; s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] - [TX_PWR_BY_RATE_NUM_RF] [TX_PWR_BY_RATE_NUM_RF] [TX_PWR_BY_RATE_NUM_RATE]; -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI - s8 TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND] - [TX_PWR_BY_RATE_NUM_RF] - [TX_PWR_BY_RATE_NUM_RF] - [TX_PWR_BY_RATE_NUM_RATE]; -#endif - /* --------------------------------------------------------------------------------- */ - - u8 tx_pwr_lmt_5g_20_40_ref; - - /* Power Limit Table for 2.4G */ - s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] - [MAX_2_4G_BANDWIDTH_NUM] - [MAX_RATE_SECTION_NUM] - [CENTER_CH_2G_NUM] - [MAX_RF_PATH]; - - /* Power Limit Table for 5G */ - s8 TxPwrLimit_5G[MAX_REGULATION_NUM] - [MAX_5G_BANDWIDTH_NUM] - [MAX_RATE_SECTION_NUM] - [CENTER_CH_5G_ALL_NUM] - [MAX_RF_PATH]; - - -#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI - s8 TxPwrLimit_2_4G_Original[MAX_REGULATION_NUM] - [MAX_2_4G_BANDWIDTH_NUM] - [MAX_RATE_SECTION_NUM] - [CENTER_CH_2G_NUM] - [MAX_RF_PATH]; - - - s8 TxPwrLimit_5G_Original[MAX_REGULATION_NUM] - [MAX_5G_BANDWIDTH_NUM] - [MAX_RATE_SECTION_NUM] - [CENTER_CH_5G_ALL_NUM] - [MAX_RF_PATH]; - -#endif - - /* Store the original power by rate value of the base of each rate section of rf path A & B */ + /* Store the original power by rate value of the base rate for each rate section and rf path */ u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] - [TX_PWR_BY_RATE_NUM_RF] [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] - [TX_PWR_BY_RATE_NUM_RF] [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; u8 txpwr_by_rate_loaded:1; @@ -557,15 +521,7 @@ typedef struct hal_com_data { /* RDG enable */ BOOLEAN bRDGEnable; - u8 RegTxPause; - /* Beacon function related global variable. */ - u8 RegBcnCtrlVal; - u8 RegFwHwTxQCtrl; - u8 RegReg542; - u8 RegCR_1; - u8 Reg837; - u16 RegRRSR; - + u16 RegRRSR; /****** antenna diversity ******/ u8 AntDivCfg; u8 with_extenal_ant_switch; @@ -578,17 +534,16 @@ typedef struct hal_com_data { u8 sw_antdiv_bl_state; /******** PHY DM & DM Section **********/ - u8 DM_Type; _lock IQKSpinLock; u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; - /* Upper and Lower Signal threshold for Rate Adaptive*/ - int entry_min_undecorated_smoothed_pwdb; - int entry_max_undecorated_smoothed_pwdb; - int min_undecorated_pwdb_for_dm; - struct PHY_DM_STRUCT odmpriv; + + struct dm_struct odmpriv; + u64 bk_rf_ability; u8 bIQKInitialized; u8 bNeedIQK; - u8 IQK_MP_Switch; + u8 neediqk_24g; + u8 IQK_MP_Switch; + u8 bScanInProcess; /******** PHY DM & DM Section **********/ @@ -608,6 +563,8 @@ typedef struct hal_com_data { u8 RegIQKFWOffload; struct submit_ctx iqk_sctx; + u8 ch_switch_offload; + struct submit_ctx chsw_sctx; RT_AMPDU_BRUST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */ @@ -640,7 +597,11 @@ typedef struct hal_com_data { /* SDIO Tx FIFO related. */ /* */ /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */ +#ifdef CONFIG_RTL8192F + u16 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; +#else u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; +#endif/*CONFIG_RTL8192F*/ _lock SdioTxFIFOFreePageLock; u8 SdioTxOQTMaxFreeSpace; u8 SdioTxOQTFreeSpace; @@ -663,7 +624,7 @@ typedef struct hal_com_data { u16 tx_normal_page; u16 tx_extra_page; u16 tx_pub_page; - u16 max_oqt_page; + u8 max_oqt_size; #ifdef XMIT_BUF_SIZE u32 max_xmit_size_vovi; u32 max_xmit_size_bebk; @@ -728,6 +689,9 @@ typedef struct hal_com_data { u8 bDisableTxInt; u16 RxTag; +#ifdef CONFIG_PCI_DYNAMIC_ASPM + BOOLEAN bAspmL1LastIdle; +#endif #endif /* CONFIG_PCI_HCI */ @@ -741,7 +705,7 @@ typedef struct hal_com_data { #endif /* CONFIG_BT_COEXIST */ #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \ - || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8723D) + || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D)|| defined(CONFIG_RTL8192F) #ifndef CONFIG_PCI_HCI /* mutual exclusive with PCI -- so they're SDIO and GSPI */ /* Interrupt relatd register information. */ u32 SysIntrStatus; @@ -772,7 +736,7 @@ typedef struct hal_com_data { #endif #ifdef CONFIG_BACKGROUND_NOISE_MONITOR - s16 noise[ODM_MAX_CHANNEL_NUM]; + struct noise_monitor nm; #endif struct hal_spec_t hal_spec; @@ -804,14 +768,19 @@ typedef struct hal_com_data { #endif /* CONFIG_BEAMFORMING */ u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/ -} HAL_DATA_COMMON, *PHAL_DATA_COMMON; + u8 phydm_op_mode; + u8 in_cta_test; +#ifdef CONFIG_RTW_LED + struct led_priv led; +#endif +} HAL_DATA_COMMON, *PHAL_DATA_COMMON; typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; -#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) +#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData)) #define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec)) -#define GET_ODM(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->odmpriv)) +#define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led)) #define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath) #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) @@ -825,16 +794,10 @@ typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; #define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) #define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) #define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) +#define rtw_set_hw_init_completed(adapter, cmp) (GET_HAL_DATA(adapter)->hw_init_completed = cmp) #define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) #endif -#ifdef CONFIG_AUTO_CHNL_SEL_NHM -#define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state)) -#define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state)) -#define rtw_get_acs_channel(padapter) (GET_HAL_DATA(padapter)->acs.ch) -#define rtw_set_acs_channel(padapter, survey_ch) (GET_HAL_DATA(padapter)->acs.ch = survey_ch) -#endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ - #ifdef RTW_HALMAC int rtw_halmac_deinit_adapter(struct dvobj_priv *); #endif /* RTW_HALMAC */ diff --git a/include/hal_gspi.h b/include/hal_gspi.h index 68119c5..51d491c 100644 --- a/include/hal_gspi.h +++ b/include/hal_gspi.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_GSPI_H_ #define __HAL_GSPI_H_ diff --git a/include/hal_ic_cfg.h b/include/hal_ic_cfg.h index 782ffed..8fe3516 100644 --- a/include/hal_ic_cfg.h +++ b/include/hal_ic_cfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_IC_CFG_H__ #define __HAL_IC_CFG_H__ @@ -26,6 +21,7 @@ #define RTL8723B_SUPPORT 0 #define RTL8723D_SUPPORT 0 #define RTL8192E_SUPPORT 0 +#define RTL8192F_SUPPORT 0 #define RTL8814A_SUPPORT 0 #define RTL8195A_SUPPORT 0 #define RTL8197F_SUPPORT 0 @@ -36,7 +32,10 @@ #define RTL8821C_SUPPORT 0 #define RTL8710B_SUPPORT 0 #define RTL8814B_SUPPORT 0 - +#define RTL8824B_SUPPORT 0 +#define RTL8198F_SUPPORT 0 +#define RTL8195B_SUPPORT 0 +#define RTL8822C_SUPPORT 0 /*#if (RTL8188E_SUPPORT==1)*/ #define RATE_ADAPTIVE_SUPPORT 0 #define POWER_TRAINING_ACTIVE 0 @@ -52,7 +51,6 @@ #define RTL8188E_SUPPORT 1 #define RATE_ADAPTIVE_SUPPORT 1 #define POWER_TRAINING_ACTIVE 1 - #define CONFIG_GET_RAID_BY_DRV #endif #ifdef CONFIG_RTL8812A @@ -79,6 +77,19 @@ #endif #endif +#ifdef CONFIG_RTL8192F + #undef RTL8192F_SUPPORT + #define RTL8192F_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif + #ifndef CONFIG_RTW_MAC_HIDDEN_RPT + #define CONFIG_RTW_MAC_HIDDEN_RPT + #endif + /*#define CONFIG_AMPDU_PRETX_CD*/ + /*#define DBG_LA_MODE*/ +#endif + #ifdef CONFIG_RTL8723B #undef RTL8723B_SUPPORT #define RTL8723B_SUPPORT 1 @@ -107,6 +118,7 @@ #ifndef CONFIG_FW_C2H_PKT #define CONFIG_FW_C2H_PKT #endif + #define CONFIG_FW_CORRECT_BCN #endif #ifdef CONFIG_RTL8703B @@ -134,6 +146,20 @@ #endif #endif +#ifdef CONFIG_RTL8188GTV + #undef RTL8188F_SUPPORT + #define RTL8188F_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif + #ifndef CONFIG_RTW_MAC_HIDDEN_RPT + #define CONFIG_RTW_MAC_HIDDEN_RPT + #endif + #ifndef CONFIG_RTW_CUSTOMER_STR + #define CONFIG_RTW_CUSTOMER_STR + #endif +#endif + #ifdef CONFIG_RTL8822B #undef RTL8822B_SUPPORT #define RTL8822B_SUPPORT 1 @@ -145,19 +171,15 @@ #ifdef CONFIG_WOWLAN #define CONFIG_GTK_OL - #define CONFIG_ARP_KEEP_ALIVE - #ifndef CONFIG_DEFAULT_PATTERNS_EN - #warning "Force to enable CONFIG_DEFAULT_PATTERNS_EN under WOW" - #define CONFIG_DEFAULT_PATTERNS_EN - #endif /* !CONFIG_DEFAULT_PATTERNS_EN */ + /*#define CONFIG_ARP_KEEP_ALIVE*/ #ifdef CONFIG_GPIO_WAKEUP #ifndef WAKEUP_GPIO_IDX #define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */ #endif /* !WAKEUP_GPIO_IDX */ #endif /* CONFIG_GPIO_WAKEUP */ - #endif /* CONFIG_WOWLAN */ + #ifdef CONFIG_CONCURRENT_MODE #define CONFIG_AP_PORT_SWAP #define CONFIG_FW_MULTI_PORT_SUPPORT @@ -166,10 +188,6 @@ /* * Beamforming related definition */ - #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_BEAMFORMING) - #undef CONFIG_BEAMFORMING - #warning "Not support Beamforming in concurrent mode yet!!" - #endif /* CONFIG_CONCURRENT_MODE && CONFIG_BEAMFORMING */ /* Beamforming mechanism is on driver not phydm, always disable it */ #define BEAMFORMING_SUPPORT 0 /* Only support new beamforming mechanism */ @@ -184,6 +202,33 @@ #ifndef DBG_RX_DFRAME_RAW_DATA #define DBG_RX_DFRAME_RAW_DATA #endif /* DBG_RX_DFRAME_RAW_DATA */ + + #ifndef RTW_IQK_FW_OFFLOAD + #define RTW_IQK_FW_OFFLOAD + #endif /* RTW_IQK_FW_OFFLOAD */ + #define CONFIG_ADVANCE_OTA + + #ifdef CONFIG_MCC_MODE + #define CONFIG_MCC_MODE_V2 + #endif /* CONFIG_MCC_MODE */ + + #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) + #define CONFIG_TDLS_CH_SW_V2 + #endif + + #ifndef RTW_CHANNEL_SWITCH_OFFLOAD + #ifdef CONFIG_TDLS_CH_SW_V2 + #define RTW_CHANNEL_SWITCH_OFFLOAD + #endif + #endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ + + #if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW) + /* Supported since fw v22.1 */ + #define RTW_PER_CMD_SUPPORT_FW + #endif /* RTW_PER_CMD_SUPPORT_FW */ + #define CONFIG_SUPPORT_FIFO_DUMP + #define CONFIG_HW_P0_TSF_SYNC + #define CONFIG_BCN_RECV_TIME #endif /* CONFIG_RTL8822B */ #ifdef CONFIG_RTL8821C @@ -208,6 +253,29 @@ #define CONFIG_FW_MULTI_PORT_SUPPORT #endif #define CONFIG_SUPPORT_FIFO_DUMP + #ifndef RTW_IQK_FW_OFFLOAD + #define RTW_IQK_FW_OFFLOAD + #endif /* RTW_IQK_FW_OFFLOAD */ + /*#define CONFIG_AMPDU_PRETX_CD*/ + /*#define DBG_PRE_TX_HANG*/ + + /* Beamforming related definition */ + /* Beamforming mechanism is on driver not phydm, always disable it */ + #define BEAMFORMING_SUPPORT 0 + /* Only support new beamforming mechanism */ + #ifdef CONFIG_BEAMFORMING + #define RTW_BEAMFORMING_VERSION_2 + #endif /* CONFIG_BEAMFORMING */ + #define CONFIG_HW_P0_TSF_SYNC + #define CONFIG_BCN_RECV_TIME +#endif /*CONFIG_RTL8821C*/ + +#ifdef CONFIG_RTL8710B + #undef RTL8710B_SUPPORT + #define RTL8710B_SUPPORT 1 + #ifndef CONFIG_FW_C2H_PKT + #define CONFIG_FW_C2H_PKT + #endif #endif #endif /*__HAL_IC_CFG_H__*/ diff --git a/include/hal_intf.h b/include/hal_intf.h index 5d9e0b9..9a5e8d6 100644 --- a/include/hal_intf.h +++ b/include/hal_intf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_INTF_H__ #define __HAL_INTF_H__ @@ -39,9 +34,12 @@ enum _CHIP_TYPE { RTL8814A, RTL8703B, RTL8188F, + RTL8188GTV, RTL8822B, RTL8723D, RTL8821C, + RTL8710B, + RTL8192F, MAX_CHIP_TYPE }; @@ -72,8 +70,9 @@ typedef enum _HW_VARIABLES { HW_VAR_BASIC_RATE, HW_VAR_TXPAUSE, HW_VAR_BCN_FUNC, + HW_VAR_BCN_CTRL_ADDR, HW_VAR_CORRECT_TSF, - HW_VAR_CHECK_BSSID, + HW_VAR_RCR, HW_VAR_MLME_DISCONNECT, HW_VAR_MLME_SITESURVEY, HW_VAR_MLME_JOIN, @@ -87,6 +86,8 @@ typedef enum _HW_VARIABLES { HW_VAR_SEC_DK_CFG, HW_VAR_BCN_VALID, HW_VAR_RF_TYPE, + HW_VAR_FREECNT, + /* PHYDM odm->SupportAbility */ HW_VAR_CAM_EMPTY_ENTRY, HW_VAR_CAM_INVALID_ALL, @@ -95,11 +96,13 @@ typedef enum _HW_VARIABLES { HW_VAR_AC_PARAM_BE, HW_VAR_AC_PARAM_BK, HW_VAR_ACM_CTRL, -#ifdef CONFIG_WMMPS +#ifdef CONFIG_WMMPS_STA HW_VAR_UAPSD_TID, -#endif +#endif /* CONFIG_WMMPS_STA */ HW_VAR_AMPDU_MIN_SPACE, +#ifdef CONFIG_80211N_HT HW_VAR_AMPDU_FACTOR, +#endif /* CONFIG_80211N_HT */ HW_VAR_RXDMA_AGG_PG_TH, HW_VAR_SET_RPWM, HW_VAR_CPWM, @@ -146,13 +149,15 @@ typedef enum _HW_VARIABLES { HW_VAR_RPT_TIMER_SETTING, HW_VAR_TX_RPT_MAX_MACID, HW_VAR_CHK_HI_QUEUE_EMPTY, + HW_VAR_CHK_MGQ_CPU_EMPTY, HW_VAR_DL_BCN_SEL, HW_VAR_AMPDU_MAX_TIME, HW_VAR_WIRELESS_MODE, HW_VAR_USB_MODE, HW_VAR_PORT_SWITCH, + HW_VAR_PORT_CFG, HW_VAR_DO_IQK, - HW_VAR_DM_IN_LPS, + HW_VAR_DM_IN_LPS_LCLK,/*flag CONFIG_LPS_LCLK_WD_TIMER*/ HW_VAR_SET_REQ_FW_PS, HW_VAR_FW_PS_STATE, HW_VAR_SOUNDING_ENTER, @@ -172,8 +177,6 @@ typedef enum _HW_VARIABLES { HW_VAR_DL_RSVD_PAGE, HW_VAR_MACID_LINK, HW_VAR_MACID_NOLINK, - HW_VAR_MACID_SLEEP, - HW_VAR_MACID_WAKEUP, HW_VAR_DUMP_MAC_QUEUE_INFO, HW_VAR_ASIX_IOT, #ifdef CONFIG_MBSSID_CAM @@ -191,12 +194,19 @@ typedef enum _HW_VARIABLES { HW_VAR_L1OFF_CAPABILITY, HW_VAR_L1OFF_NIC_SUPPORT, #ifdef CONFIG_TDLS - HW_VAR_TDLS_WRCR, - HW_VAR_TDLS_RS_RCR, #ifdef CONFIG_TDLS_CH_SW - HW_VAR_TDLS_BCN_EARLY_C2H_RPT + HW_VAR_TDLS_BCN_EARLY_C2H_RPT, #endif #endif + HW_VAR_DUMP_MAC_TXFIFO, + HW_VAR_PWR_CMD, +#ifdef CONFIG_FW_HANDLE_TXBCN + HW_VAR_BCN_HEAD_SEL, +#endif + HW_VAR_SET_SOML_PARAM, + HW_VAR_ENABLE_RX_BAR, + HW_VAR_TSF_AUTO_SYNC, + HW_VAR_LPS_STATE_CHK, } HW_VARIABLES; typedef enum _HAL_DEF_VARIABLE { @@ -233,8 +243,6 @@ typedef enum _HAL_DEF_VARIABLE { HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, /* Determine if the L1 Backdoor setting is turned on. */ HAL_DEF_PCI_AMD_L1_SUPPORT, HAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */ - HAL_DEF_MACID_SLEEP, /* Support for MACID sleep */ - HAL_DEF_DBG_DIS_PWT, /* disable Tx power training or not. */ HAL_DEF_EFUSE_USAGE, /* Get current EFUSE utilization. 2008.12.19. Added by Roger. */ HAL_DEF_EFUSE_BYTES, HW_VAR_BEST_AMPDU_DENSITY, @@ -244,17 +252,10 @@ typedef enum _HAL_ODM_VARIABLE { HAL_ODM_STA_INFO, HAL_ODM_P2P_STATE, HAL_ODM_WIFI_DISPLAY_STATE, - HAL_ODM_NOISE_MONITOR, HAL_ODM_REGULATION, HAL_ODM_INITIAL_GAIN, - HAL_ODM_FA_CNT_DUMP, - HAL_ODM_DBG_FLAG, - HAL_ODM_DBG_LEVEL, HAL_ODM_RX_INFO_DUMP, HAL_ODM_RX_Dframe_INFO, -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - HAL_ODM_AUTO_CHNL_SEL, -#endif #ifdef CONFIG_ANTENNA_DIVERSITY HAL_ODM_ANTDIV_SELECT #endif @@ -269,17 +270,6 @@ typedef s32(*c2h_id_filter)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *paylo struct txpwr_idx_comp; -struct macid_cfg { - u8 mac_id; - u8 rate_id; - u8 bandwidth; - u8 short_gi; - u8 ignore_bw; - u8 rsvd; - u16 rsvd1; - u64 ra_mask; -}; - struct hal_ops { /*** initialize section ***/ void (*read_chip_version)(_adapter *padapter); @@ -335,25 +325,21 @@ struct hal_ops { #endif /*** DM section ***/ - +#ifdef CONFIG_RTW_SW_LED void (*InitSwLeds)(_adapter *padapter); void (*DeInitSwLeds)(_adapter *padapter); - - void (*set_chnl_bw_handler)(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); +#endif + void (*set_chnl_bw_handler)(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80); void (*set_tx_power_level_handler)(_adapter *padapter, u8 channel); void (*get_tx_power_level_handler)(_adapter *padapter, s32 *powerlevel); - void (*set_tx_power_index_handler)(_adapter *padapter, u32 powerindex, u8 rfpath, u8 rate); - u8(*get_tx_power_index_handler)(_adapter *padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); + void (*set_tx_power_index_handler)(_adapter *padapter, u32 powerindex, enum rf_path rfpath, u8 rate); + u8 (*get_tx_power_index_handler)(_adapter *padapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); void (*hal_dm_watchdog)(_adapter *padapter); -#ifdef CONFIG_LPS_LCLK_WD_TIMER - void (*hal_dm_watchdog_in_lps)(_adapter *padapter); -#endif - - void (*set_hw_reg_handler)(_adapter *padapter, u8 variable, u8 *val); + u8 (*set_hw_reg_handler)(_adapter *padapter, u8 variable, u8 *val); void (*GetHwRegHandler)(_adapter *padapter, u8 variable, u8 *val); @@ -366,16 +352,20 @@ struct hal_ops { void (*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2); void (*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet); - void (*update_ra_mask_handler)(_adapter *padapter, struct sta_info *psta, struct macid_cfg *h2c_macid_cfg); void (*SetBeaconRelatedRegistersHandler)(_adapter *padapter); u8(*interface_ps_func)(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val); u32(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask); void (*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); - u32(*read_rfreg)(_adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask); - void (*write_rfreg)(_adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); - + u32 (*read_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask); + void (*write_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data); +#ifdef CONFIG_SYSON_INDIRECT_ACCESS + u32 (*read_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask); + void (*write_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); +#endif + void (*read_wmmedca_reg)(_adapter *padapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params); + #ifdef CONFIG_HOSTAPD_MLME s32(*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt); #endif @@ -389,6 +379,9 @@ struct hal_ops { int (*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); u8(*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); BOOLEAN(*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); +#if defined(CONFIG_RTL8710B) + BOOLEAN(*efuse_indirect_read4)(_adapter *padapter, u16 regaddr, u8 *value); +#endif #ifdef DBG_CONFIG_ERROR_DETECT void (*sreset_init_value)(_adapter *padapter); @@ -428,7 +421,9 @@ struct hal_ops { int (*hal_gpio_func_check)(_adapter *padapter, u8 gpio_num); void (*hal_gpio_multi_func_reset)(_adapter *padapter, u8 gpio_num); #endif +#ifdef CONFIG_FW_CORRECT_BCN void (*fw_correct_bcn)(PADAPTER padapter); +#endif #ifdef RTW_HALMAC u8(*init_mac_register)(PADAPTER); @@ -439,6 +434,10 @@ struct hal_ops { void (*hal_set_l1ssbackdoor_handler)(_adapter *padapter, u8 enable); #endif +#ifdef CONFIG_RFKILL_POLL + bool (*hal_radio_onoff_check)(_adapter *adapter, u8 *valid); +#endif + }; typedef enum _RT_EEPROM_TYPE { @@ -487,12 +486,18 @@ typedef enum _HARDWARE_TYPE { HARDWARE_TYPE_RTL8188FE, HARDWARE_TYPE_RTL8188FU, HARDWARE_TYPE_RTL8188FS, + HARDWARE_TYPE_RTL8188GTVU, + HARDWARE_TYPE_RTL8188GTVS, HARDWARE_TYPE_RTL8723DE, HARDWARE_TYPE_RTL8723DU, HARDWARE_TYPE_RTL8723DS, HARDWARE_TYPE_RTL8821CE, HARDWARE_TYPE_RTL8821CU, HARDWARE_TYPE_RTL8821CS, + HARDWARE_TYPE_RTL8710BU, + HARDWARE_TYPE_RTL8192FS, + HARDWARE_TYPE_RTL8192FU, + HARDWARE_TYPE_RTL8192FE, HARDWARE_TYPE_MAX, } HARDWARE_TYPE; @@ -566,6 +571,18 @@ typedef enum _HARDWARE_TYPE { IS_HARDWARE_TYPE_8723DU(_Adapter) || \ IS_HARDWARE_TYPE_8723DS(_Adapter)) +/* RTL8192F Series */ +#define IS_HARDWARE_TYPE_8192FS(_Adapter)\ + (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FS) +#define IS_HARDWARE_TYPE_8192FU(_Adapter)\ + (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FU) +#define IS_HARDWARE_TYPE_8192FE(_Adapter)\ + (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FE) +#define IS_HARDWARE_TYPE_8192F(_Adapter)\ + (IS_HARDWARE_TYPE_8192FS(_Adapter) ||\ + IS_HARDWARE_TYPE_8192FU(_Adapter) ||\ + IS_HARDWARE_TYPE_8192FE(_Adapter)) + /* RTL8188F Series */ #define IS_HARDWARE_TYPE_8188FE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE) #define IS_HARDWARE_TYPE_8188FS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS) @@ -573,6 +590,15 @@ typedef enum _HARDWARE_TYPE { #define IS_HARDWARE_TYPE_8188F(_Adapter) \ (IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter)) +#define IS_HARDWARE_TYPE_8188GTVU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVU) +#define IS_HARDWARE_TYPE_8188GTVS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVS) +#define IS_HARDWARE_TYPE_8188GTV(_Adapter) \ + (IS_HARDWARE_TYPE_8188GTVU(_Adapter) || IS_HARDWARE_TYPE_8188GTVS(_Adapter)) + +/* RTL8710B Series */ +#define IS_HARDWARE_TYPE_8710BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8710BU) +#define IS_HARDWARE_TYPE_8710B(_Adapter) (IS_HARDWARE_TYPE_8710BU(_Adapter)) + #define IS_HARDWARE_TYPE_8821BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE) #define IS_HARDWARE_TYPE_8821BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU) #define IS_HARDWARE_TYPE_8821BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS) @@ -623,16 +649,20 @@ void rtw_hal_free_data(_adapter *padapter); void rtw_hal_dm_init(_adapter *padapter); void rtw_hal_dm_deinit(_adapter *padapter); +#ifdef CONFIG_RTW_SW_LED void rtw_hal_sw_led_init(_adapter *padapter); void rtw_hal_sw_led_deinit(_adapter *padapter); - +#endif u32 rtw_hal_power_on(_adapter *padapter); void rtw_hal_power_off(_adapter *padapter); uint rtw_hal_init(_adapter *padapter); +#ifdef CONFIG_NEW_NETDEV_HDL +uint rtw_hal_iface_init(_adapter *adapter); +#endif uint rtw_hal_deinit(_adapter *padapter); void rtw_hal_stop(_adapter *padapter); -void rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val); +u8 rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val); void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val); void rtw_hal_chip_configure(_adapter *padapter); @@ -677,8 +707,7 @@ void rtw_hal_free_xmit_priv(_adapter *padapter); s32 rtw_hal_init_recv_priv(_adapter *padapter); void rtw_hal_free_recv_priv(_adapter *padapter); -void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level, u8 is_update_bw); -void rtw_update_ramask(_adapter *padapter, struct sta_info *psta, u32 mac_id, u8 rssi_level, u8 is_update_bw); +void rtw_hal_update_ra_mask(struct sta_info *psta); void rtw_hal_start_thread(_adapter *padapter); void rtw_hal_stop_thread(_adapter *padapter); @@ -687,8 +716,8 @@ void rtw_hal_bcn_related_reg_setting(_adapter *padapter); u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask); void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); -u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask); -void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); +u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask); +void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data); #define phy_query_bb_reg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask)) @@ -696,10 +725,16 @@ void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMa #define phy_query_rf_reg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask)) #define phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) +#ifdef CONFIG_SYSON_INDIRECT_ACCESS +u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask); +void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); +#define hal_query_syson_reg(Adapter, RegAddr, BitMask) rtw_hal_read_syson_reg((Adapter), (RegAddr), (BitMask)) +#define hal_set_syson_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_syson_reg((Adapter), (RegAddr), (BitMask), (Data)) +#endif + #define phy_set_mac_reg phy_set_bb_reg #define phy_query_mac_reg phy_query_bb_reg - #if defined(CONFIG_PCI_HCI) s32 rtw_hal_interrupt_handler(_adapter *padapter); #endif @@ -707,7 +742,7 @@ void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMa void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf); #endif -void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); +void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80); void rtw_hal_dm_watchdog(_adapter *padapter); void rtw_hal_dm_watchdog_in_lps(_adapter *padapter); @@ -760,8 +795,10 @@ s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter); -s32 rtw_hal_macid_sleep(PADAPTER padapter, u8 macid); -s32 rtw_hal_macid_wakeup(PADAPTER padapter, u8 macid); +s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid); +s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid); +s32 rtw_hal_macid_sleep_all_used(_adapter *adapter); +s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter); s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen, @@ -773,16 +810,18 @@ void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag); int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num); void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num); #endif - +#ifdef CONFIG_FW_CORRECT_BCN void rtw_hal_fw_correct_bcn(_adapter *padapter); +#endif s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan); #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) void rtw_hal_clear_interrupt(_adapter *padapter); #endif -void rtw_hal_set_tx_power_index(PADAPTER, u32 powerindex, u8 rfpath, u8 rate); -u8 rtw_hal_get_tx_power_index(PADAPTER, u8 rfpath, u8 rate, u8 bandwidth, u8 channel,struct txpwr_idx_comp *tic); +void rtw_hal_set_tx_power_index(PADAPTER adapter, u32 powerindex, enum rf_path rfpath, u8 rate); +u8 rtw_hal_get_tx_power_index(PADAPTER adapter, enum rf_path + rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); u8 rtw_hal_ops_check(_adapter *padapter); @@ -792,4 +831,8 @@ u8 rtw_hal_ops_check(_adapter *padapter); s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem); #endif /* RTW_HALMAC */ +#ifdef CONFIG_RFKILL_POLL +bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid); +#endif + #endif /* __HAL_INTF_H__ */ diff --git a/include/hal_pg.h b/include/hal_pg.h index b0a86c5..b807ca8 100644 --- a/include/hal_pg.h +++ b/include/hal_pg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_PG_H__ #define __HAL_PG_H__ @@ -34,8 +29,6 @@ /* **************************************************** * EEPROM/Efuse PG Offset for 88EE/88EU/88ES * **************************************************** */ -#define EEPROM_TX_PWR_INX_88E 0x10 - #define EEPROM_ChannelPlan_88E 0xB8 #define EEPROM_XTAL_88E 0xB9 #define EEPROM_THERMAL_METER_88E 0xBA @@ -74,9 +67,6 @@ #define PPG_BB_GAIN_2G_TXA_OFFSET_8192E 0x1F6 #define PPG_THERMAL_OFFSET_8192E 0x1F5 -/* 0x10 ~ 0x63 = TX power area. */ -#define EEPROM_TX_PWR_INX_8192E 0x10 - #define EEPROM_ChannelPlan_8192E 0xB8 #define EEPROM_XTAL_8192E 0xB9 #define EEPROM_THERMAL_METER_8192E 0xBA @@ -117,10 +107,8 @@ #define EEPROM_MAC_ADDR_8192ES 0x11A /* **************************************************** * EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS - * **************************************************** - * 0x10 ~ 0x63 = TX power area. */ + * *****************************************************/ #define EEPROM_USB_MODE_8812 0x08 -#define EEPROM_TX_PWR_INX_8812 0x10 #define EEPROM_ChannelPlan_8812 0xB8 #define EEPROM_XTAL_8812 0xB9 @@ -185,7 +173,6 @@ #define PPG_THERMAL_OFFSET_8814A 0x3EF -#define EEPROM_TX_PWR_INX_8814 0x10 #define EEPROM_USB_MODE_8814A 0x0E #define EEPROM_ChannelPlan_8814 0xB8 #define EEPROM_XTAL_8814 0xB9 @@ -233,8 +220,6 @@ #define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A 0x1F1 #define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A 0x1F0 -#define EEPROM_TX_PWR_INX_8821 0x10 - #define EEPROM_ChannelPlan_8821 0xB8 #define EEPROM_XTAL_8821 0xB9 #define EEPROM_THERMAL_METER_8821 0xBA @@ -302,9 +287,6 @@ #define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xEE #define PPG_THERMAL_OFFSET_8188F 0xEF -/* 0x10 ~ 0x63 = TX power area. */ -#define EEPROM_TX_PWR_INX_8188F 0x10 - #define EEPROM_ChannelPlan_8188F 0xB8 #define EEPROM_XTAL_8188F 0xB9 #define EEPROM_THERMAL_METER_8188F 0xBA @@ -338,12 +320,53 @@ #define EEPROM_MAC_ADDR_8188FS 0x11A #define EEPROM_Voltage_ADDR_8188F 0x8 +/* ==================================================== + EEPROM/Efuse PG Offset for 8188GTV/8188GTVS + ==================================================== + */ + +#define GET_PG_KFREE_ON_8188GTV(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8188GTV(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8188GTV 0xEE +#define PPG_THERMAL_OFFSET_8188GTV 0xEF + +#define EEPROM_ChannelPlan_8188GTV 0xB8 +#define EEPROM_XTAL_8188GTV 0xB9 +#define EEPROM_THERMAL_METER_8188GTV 0xBA +#define EEPROM_IQK_LCK_8188GTV 0xBB +#define EEPROM_2G_5G_PA_TYPE_8188GTV 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8188GTV 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8188GTV 0xBF + +#define EEPROM_RF_BOARD_OPTION_8188GTV 0xC1 +#define EEPROM_FEATURE_OPTION_8188GTV 0xC2 +#define EEPROM_RF_BT_SETTING_8188GTV 0xC3 +#define EEPROM_VERSION_8188GTV 0xC4 +#define EEPROM_CustomID_8188GTV 0xC5 +#define EEPROM_TX_BBSWING_2G_8188GTV 0xC6 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8188GTV 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8188GTV 0xC9 +#define EEPROM_RFE_OPTION_8188GTV 0xCA +#define EEPROM_COUNTRY_CODE_8188GTV 0xCB +#define EEPROM_CUSTOMER_ID_8188GTV 0x7F +#define EEPROM_SUBCUSTOMER_ID_8188GTV 0x59 + +/* RTL8188GTVU */ +#define EEPROM_MAC_ADDR_8188GTVU 0xD7 +#define EEPROM_VID_8188GTVU 0xD0 +#define EEPROM_PID_8188GTVU 0xD2 +#define EEPROM_PA_TYPE_8188GTVU 0xBC +#define EEPROM_LNA_TYPE_2G_8188GTVU 0xBD +#define EEPROM_USB_OPTIONAL_FUNCTION0_8188GTVU 0xD4 + +/* RTL8188GTVS */ +#define EEPROM_MAC_ADDR_8188GTVS 0x11A +#define EEPROM_Voltage_ADDR_8188GTV 0x8 + /* **************************************************** * EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS - * **************************************************** - * 0x10 ~ 0x63 = TX power area. */ -#define EEPROM_TX_PWR_INX_8723B 0x10 - + * *****************************************************/ #define EEPROM_ChannelPlan_8723B 0xB8 #define EEPROM_XTAL_8723B 0xB9 #define EEPROM_THERMAL_METER_8723B 0xBA @@ -391,8 +414,6 @@ #define PPG_BB_GAIN_2G_TXA_OFFSET_8703B 0xEE #define PPG_THERMAL_OFFSET_8703B 0xEF -#define EEPROM_TX_PWR_INX_8703B 0x10 - #define EEPROM_ChannelPlan_8703B 0xB8 #define EEPROM_XTAL_8703B 0xB9 #define EEPROM_THERMAL_METER_8703B 0xBA @@ -429,8 +450,6 @@ * EEPROM/Efuse PG Offset for 8822B * ==================================================== */ -#define EEPROM_TX_PWR_INX_8822B 0x10 - #define EEPROM_ChannelPlan_8822B 0xB8 #define EEPROM_XTAL_8822B 0xB9 #define EEPROM_THERMAL_METER_8822B 0xBA @@ -473,8 +492,6 @@ * EEPROM/Efuse PG Offset for 8821C * ==================================================== */ -#define EEPROM_TX_PWR_INX_8821C 0x10 - #define EEPROM_CHANNEL_PLAN_8821C 0xB8 #define EEPROM_XTAL_8821C 0xB9 #define EEPROM_THERMAL_METER_8821C 0xBA @@ -528,8 +545,6 @@ #define PPG_BB_GAIN_2G_TX_OFFSET_8723D 0x1EE #define PPG_THERMAL_OFFSET_8723D 0xEF -#define EEPROM_TX_PWR_INX_8723D 0x10 - #define EEPROM_ChannelPlan_8723D 0xB8 #define EEPROM_XTAL_8723D 0xB9 #define EEPROM_THERMAL_METER_8723D 0xBA @@ -566,10 +581,82 @@ #define EEPROM_MAC_ADDR_8723DS 0x11A #define EEPROM_Voltage_ADDR_8723D 0x8 +/* **************************************************** + * EEPROM/Efuse PG Offset for 8192F + * **************************************************** */ +#define EEPROM_ChannelPlan_8192F 0xB8 +#define EEPROM_XTAL_8192F 0xB9 +#define EEPROM_THERMAL_METER_8192F 0xBA +#define EEPROM_IQK_LCK_8192F 0xBB +#define EEPROM_2G_5G_PA_TYPE_8192F 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192F 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192F 0xBF + +#define EEPROM_RF_BOARD_OPTION_8192F 0xC1 +#define EEPROM_FEATURE_OPTION_8192F 0xC2 +#define EEPROM_RF_BT_SETTING_8192F 0xC3 +#define EEPROM_VERSION_8192F 0xC4 +#define EEPROM_CustomID_8192F 0xC5 +#define EEPROM_TX_BBSWING_2G_8192F 0xC6 +#define EEPROM_TX_BBSWING_5G_8192F 0xC7 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8192F 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8192F 0xC9 +#define EEPROM_RFE_OPTION_8192F 0xCA +#define EEPROM_COUNTRY_CODE_8192F 0xCB +/*RTL8192FS*/ +#define EEPROM_MAC_ADDR_8192FS 0x11A +#define EEPROM_Voltage_ADDR_8192F 0x8 +/* RTL8192FU */ +#define EEPROM_MAC_ADDR_8192FU 0x107 +#define EEPROM_VID_8192FU 0x100 +#define EEPROM_PID_8192FU 0x102 +#define EEPROM_USB_OPTIONAL_FUNCTION0_8192FU 0x104 +/* RTL8192FE */ +#define EEPROM_MAC_ADDR_8192FE 0xD0 +#define EEPROM_VID_8192FE 0xD6 +#define EEPROM_DID_8192FE 0xD8 +#define EEPROM_SVID_8192FE 0xDA +#define EEPROM_SMID_8192FE 0xDC + +/* **************************************************** + * EEPROM/Efuse PG Offset for 8710B + * **************************************************** */ +#define RTL_EEPROM_ID_8710B 0x8195 +#define EEPROM_Default_ThermalMeter_8710B 0x1A + +#define EEPROM_CHANNEL_PLAN_8710B 0xC8 +#define EEPROM_XTAL_8710B 0xC9 +#define EEPROM_THERMAL_METER_8710B 0xCA +#define EEPROM_IQK_LCK_8710B 0xCB +#define EEPROM_2G_5G_PA_TYPE_8710B 0xCC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8710B 0xCD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8710B 0xCF +#define EEPROM_TX_KFREE_8710B 0xEE //Physical Efuse Address +#define EEPROM_THERMAL_8710B 0xEF //Physical Efuse Address +#define EEPROM_PACKAGE_TYPE_8710B 0xF8 //Physical Efuse Address + +#define EEPROM_RF_BOARD_OPTION_8710B 0x131 +#define EEPROM_RF_FEATURE_OPTION_8710B 0x132 +#define EEPROM_RF_BT_SETTING_8710B 0x133 +#define EEPROM_VERSION_8710B 0x134 +#define EEPROM_CUSTOM_ID_8710B 0x135 +#define EEPROM_TX_BBSWING_2G_8710B 0x136 +#define EEPROM_TX_BBSWING_5G_8710B 0x137 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8710B 0x138 +#define EEPROM_RF_ANTENNA_OPT_8710B 0x139 +#define EEPROM_RFE_OPTION_8710B 0x13A +#define EEPROM_COUNTRY_CODE_8710B 0x13B +#define EEPROM_COUNTRY_CODE_2_8710B 0x13C + +#define EEPROM_MAC_ADDR_8710B 0x11A +#define EEPROM_VID_8710BU 0x1C0 +#define EEPROM_PID_8710BU 0x1C2 + /* **************************************************** * EEPROM/Efuse Value Type * **************************************************** */ #define EETYPE_TX_PWR 0x0 +#define EETYPE_MAX_RFE_8192F 0x31 /* **************************************************** * EEPROM/Efuse Default Value * **************************************************** */ @@ -617,8 +704,9 @@ #define EEPROM_Default_ThermalMeter_8703B 0x18 #define EEPROM_Default_ThermalMeter_8723D 0x18 #define EEPROM_Default_ThermalMeter_8188F 0x18 +#define EEPROM_Default_ThermalMeter_8188GTV 0x18 #define EEPROM_Default_ThermalMeter_8814A 0x18 - +#define EEPROM_Default_ThermalMeter_8192F 0x1A #define EEPROM_Default_CrystalCap 0x0 #define EEPROM_Default_CrystalCap_8723A 0x20 @@ -630,6 +718,8 @@ #define EEPROM_Default_CrystalCap_8703B 0x20 #define EEPROM_Default_CrystalCap_8723D 0x20 #define EEPROM_Default_CrystalCap_8188F 0x20 +#define EEPROM_Default_CrystalCap_8188GTV 0x20 +#define EEPROM_Default_CrystalCap_8192F 0x20 #define EEPROM_Default_CrystalFreq 0x0 #define EEPROM_Default_TxPowerLevel_92C 0x22 #define EEPROM_Default_TxPowerLevel_2G 0x2C @@ -777,7 +867,8 @@ typedef enum _BT_CoType { BT_RTL8703B = 12, BT_RTL8822B = 13, BT_RTL8723D = 14, - BT_RTL8821C = 15 + BT_RTL8821C = 15, + BT_RTL8192F = 16, } BT_CoType, *PBT_CoType; typedef enum _BT_RadioShared { diff --git a/include/hal_phy.h b/include/hal_phy.h index af1dcad..342613b 100644 --- a/include/hal_phy.h +++ b/include/hal_phy.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_PHY_H__ #define __HAL_PHY_H__ @@ -56,20 +51,15 @@ /*--------------------------Define Parameters-------------------------------*/ -typedef enum _RF_TYPE { - RF_TYPE_MIN = 0, /* 0 */ +typedef enum _RF_CHIP { + RF_CHIP_MIN = 0, /* 0 */ RF_8225 = 1, /* 1 11b/g RF for verification only */ RF_8256 = 2, /* 2 11b/g/n */ RF_8258 = 3, /* 3 11a/b/g/n RF */ RF_6052 = 4, /* 4 11b/g/n RF */ RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */ - RF_TYPE_MAX -} RF_TYPE_E, *PRF_TYPE_E; - -#define TX_1S 0 -#define TX_2S 1 -#define TX_3S 2 -#define TX_4S 3 + RF_CHIP_MAX +} RF_CHIP_E, *PRF_CHIP_E; typedef enum _ANTENNA_PATH { ANTENNA_NONE = 0, @@ -161,6 +151,14 @@ typedef struct _R_ANTENNA_SELECT_CCK { u8 r_ccktx_enable:4; } R_ANTENNA_SELECT_CCK; + +/*--------------------------Exported Function prototype---------------------*/ +u32 +PHY_CalculateBitShift( + u32 BitMask +); + +#ifdef CONFIG_RF_SHADOW_RW typedef struct RF_Shadow_Compare_Map { /* Shadow register value */ u32 Value; @@ -174,36 +172,29 @@ typedef struct RF_Shadow_Compare_Map { u8 Driver_Write; } RF_SHADOW_T; -/*--------------------------Exported Function prototype---------------------*/ - -u32 -PHY_CalculateBitShift( - u32 BitMask -); - u32 PHY_RFShadowRead( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset); VOID PHY_RFShadowWrite( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u32 Data); BOOLEAN PHY_RFShadowCompare( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset); VOID PHY_RFShadowRecorver( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset); VOID @@ -217,14 +208,14 @@ PHY_RFShadowRecorverAll( VOID PHY_RFShadowCompareFlagSet( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u8 Type); VOID PHY_RFShadowRecorverFlagSet( IN PADAPTER Adapter, - IN u8 eRFPath, + IN enum rf_path eRFPath, IN u32 Offset, IN u8 Type); @@ -239,5 +230,5 @@ PHY_RFShadowRecorverFlagSetAll( VOID PHY_RFShadowRefresh( IN PADAPTER Adapter); - +#endif /*#CONFIG_RF_SHADOW_RW*/ #endif /* __HAL_COMMON_H__ */ diff --git a/include/hal_phy_reg.h b/include/hal_phy_reg.h index 9a92e40..6e6a99e 100644 --- a/include/hal_phy_reg.h +++ b/include/hal_phy_reg.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_PHY_REG_H__ #define __HAL_PHY_REG_H__ diff --git a/include/hal_sdio.h b/include/hal_sdio.h index 0a83372..c3578e2 100644 --- a/include/hal_sdio.h +++ b/include/hal_sdio.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __HAL_SDIO_H_ #define __HAL_SDIO_H_ @@ -25,7 +20,7 @@ u8 rtw_hal_sdio_max_txoqt_free_space(_adapter *padapter); u8 rtw_hal_sdio_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum); void rtw_hal_sdio_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum); -void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ); +void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ, u8 div_num); u32 rtw_hal_get_sdio_tx_max_length(PADAPTER padapter, u8 queue_idx); bool sdio_power_on_check(PADAPTER padapter); @@ -33,4 +28,29 @@ bool sdio_power_on_check(PADAPTER padapter); void sd_c2h_hisr_hdl(_adapter *adapter); #endif +#if defined(CONFIG_RTL8188F) || defined (CONFIG_RTL8188GTV) || defined (CONFIG_RTL8192F) +#define SDIO_LOCAL_CMD_ADDR(addr) ((SDIO_LOCAL_DEVICE_ID << 13) | ((addr) & SDIO_LOCAL_MSK)) +#endif + +#ifdef CONFIG_SDIO_CHK_HCI_RESUME +bool sdio_chk_hci_resume(struct intf_hdl *pintfhdl); +void sdio_chk_hci_suspend(struct intf_hdl *pintfhdl); +#else +#define sdio_chk_hci_resume(pintfhdl) _FALSE +#define sdio_chk_hci_suspend(pintfhdl) do {} while (0) +#endif /* CONFIG_SDIO_CHK_HCI_RESUME */ + +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +/* program indirect access register in sdio local to read/write page0 registers */ +s32 sdio_iread(PADAPTER padapter, u32 addr, u8 size, u8 *v); +s32 sdio_iwrite(PADAPTER padapter, u32 addr, u8 size, u8 *v); +u8 sdio_iread8(struct intf_hdl *pintfhdl, u32 addr); +u16 sdio_iread16(struct intf_hdl *pintfhdl, u32 addr); +u32 sdio_iread32(struct intf_hdl *pintfhdl, u32 addr); +s32 sdio_iwrite8(struct intf_hdl *pintfhdl, u32 addr, u8 val); +s32 sdio_iwrite16(struct intf_hdl *pintfhdl, u32 addr, u16 val); +s32 sdio_iwrite32(struct intf_hdl *pintfhdl, u32 addr, u32 val); +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +u32 cmd53_4byte_alignment(struct intf_hdl *pintfhdl, u32 addr); + #endif /* __HAL_SDIO_H_ */ diff --git a/include/ieee80211.h b/include/ieee80211.h index 915bcd8..c87a5b2 100644 --- a/include/ieee80211.h +++ b/include/ieee80211.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __IEEE80211_H #define __IEEE80211_H @@ -156,6 +151,58 @@ extern u8 RSN_CIPHER_SUITE_WRAP[]; extern u8 RSN_CIPHER_SUITE_CCMP[]; extern u8 RSN_CIPHER_SUITE_WEP104[]; +/* IEEE 802.11i */ +#define PMKID_LEN 16 +#define PMK_LEN 32 +#define PMK_LEN_SUITE_B_192 48 +#define PMK_LEN_MAX 48 +#define WPA_REPLAY_COUNTER_LEN 8 +#define WPA_NONCE_LEN 32 +#define WPA_KEY_RSC_LEN 8 +#define WPA_GMK_LEN 32 +#define WPA_GTK_MAX_LEN 32 + +/* IEEE 802.11, 8.5.2 EAPOL-Key frames */ +#define WPA_KEY_INFO_TYPE_MASK ((u16) (BIT(0) | BIT(1) | BIT(2))) +#define WPA_KEY_INFO_TYPE_AKM_DEFINED 0 +#define WPA_KEY_INFO_TYPE_HMAC_MD5_RC4 BIT(0) +#define WPA_KEY_INFO_TYPE_HMAC_SHA1_AES BIT(1) +#define WPA_KEY_INFO_TYPE_AES_128_CMAC 3 +#define WPA_KEY_INFO_KEY_TYPE BIT(3) /* 1 = Pairwise, 0 = Group key */ +/* bit4..5 is used in WPA, but is reserved in IEEE 802.11i/RSN */ +#define WPA_KEY_INFO_KEY_INDEX_MASK (BIT(4) | BIT(5)) +#define WPA_KEY_INFO_KEY_INDEX_SHIFT 4 +#define WPA_KEY_INFO_INSTALL BIT(6) /* pairwise */ +#define WPA_KEY_INFO_TXRX BIT(6) /* group */ +#define WPA_KEY_INFO_ACK BIT(7) +#define WPA_KEY_INFO_MIC BIT(8) +#define WPA_KEY_INFO_SECURE BIT(9) +#define WPA_KEY_INFO_ERROR BIT(10) +#define WPA_KEY_INFO_REQUEST BIT(11) +#define WPA_KEY_INFO_ENCR_KEY_DATA BIT(12) /* IEEE 802.11i/RSN only */ +#define WPA_KEY_INFO_SMK_MESSAGE BIT(13) + +struct ieee802_1x_hdr { + u8 version; + u8 type; + u16 length; + /* followed by length octets of data */ +}; + +struct wpa_eapol_key { + u8 type; + /* Note: key_info, key_length, and key_data_length are unaligned */ + u8 key_info[2]; /* big endian */ + u8 key_length[2]; /* big endian */ + u8 replay_counter[WPA_REPLAY_COUNTER_LEN]; + u8 key_nonce[WPA_NONCE_LEN]; + u8 key_iv[16]; + u8 key_rsc[WPA_KEY_RSC_LEN]; + u8 key_id[8]; /* Reserved in IEEE 802.11i/RSN */ + u8 key_mic[16]; + u8 key_data_length[2]; /* big endian */ + /* followed by key_data_length bytes of key_data */ +}; typedef enum _RATEID_IDX_ { RATEID_IDX_BGN_40M_2SS = 0, @@ -206,7 +253,7 @@ enum NETWORK_TYPE { WIRELESS_11A_5N = (WIRELESS_11A | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ WIRELESS_11B_24N = (WIRELESS_11B | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ WIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ - WIRELESS_11_24AC = (WIRELESS_11G | WIRELESS_11AC), + WIRELESS_11_24AC = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11AC), WIRELESS_11_5AC = (WIRELESS_11A | WIRELESS_11AC), @@ -396,6 +443,28 @@ struct eapol { u16 length; } __attribute__((packed)); +struct rtw_ieee80211s_hdr { + u8 flags; + u8 ttl; + u32 seqnum; + u8 eaddr1[ETH_ALEN]; + u8 eaddr2[ETH_ALEN]; +} __attribute__((packed)); + +/** + * struct rtw_ieee80211_rann_ie + * + * This structure refers to "Root Announcement information element" + */ + struct rtw_ieee80211_rann_ie { + u8 rann_flags; + u8 rann_hopcount; + u8 rann_ttl; + u8 rann_addr[ETH_ALEN]; + u32 rann_seq; + u32 rann_interval; + u32 rann_metric; +} __attribute__((packed)); #endif @@ -636,10 +705,33 @@ struct ieee80211_snap_hdr { #define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 #define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 #define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 +#define WLAN_REASON_MESH_PEER_CANCELED 52 +#define WLAN_REASON_MESH_MAX_PEERS 53 +#define WLAN_REASON_MESH_CONFIG 54 +#define WLAN_REASON_MESH_CLOSE 55 +#define WLAN_REASON_MESH_MAX_RETRIES 56 +#define WLAN_REASON_MESH_CONFIRM_TIMEOUT 57 +#define WLAN_REASON_MESH_INVALID_GTK 58 +#define WLAN_REASON_MESH_INCONSISTENT_PARAM 59 +#define WLAN_REASON_MESH_INVALID_SECURITY 60 +#define WLAN_REASON_MESH_PATH_NOPROXY 61 +#define WLAN_REASON_MESH_PATH_NOFORWARD 62 +#define WLAN_REASON_MESH_PATH_DEST_UNREACHABLE 63 +#define WLAN_REASON_MAC_EXISTS_IN_MBSS 64 +#define WLAN_REASON_MESH_CHAN_REGULATORY 65 +#define WLAN_REASON_MESH_CHAN 66 +#define WLAN_REASON_SA_QUERY_TIMEOUT 65532 #define WLAN_REASON_ACTIVE_ROAM 65533 #define WLAN_REASON_JOIN_WRONG_CHANNEL 65534 #define WLAN_REASON_EXPIRATION_CHK 65535 +#define WLAN_REASON_IS_PRIVATE(reason) ( \ + reason == WLAN_REASON_EXPIRATION_CHK \ + || reason == WLAN_REASON_JOIN_WRONG_CHANNEL \ + || reason == WLAN_REASON_ACTIVE_ROAM \ + || reason == WLAN_REASON_SA_QUERY_TIMEOUT \ + ) + /* Information Element IDs */ #define WLAN_EID_SSID 0 #define WLAN_EID_SUPP_RATES 1 @@ -675,6 +767,15 @@ struct ieee80211_snap_hdr { #define WLAN_EID_20_40_BSS_INTOLERANT 73 #define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74 #define WLAN_EID_MMIE 76 +#define WLAN_EID_MESH_CONFIG 113 +#define WLAN_EID_MESH_ID 114 +#define WLAN_EID_MPM 117 +#define WLAN_EID_RANN 126 +#define WLAN_EID_PREQ 130 +#define WLAN_EID_PREP 131 +#define WLAN_EID_PERR 132 +#define WLAN_EID_AMPE 139 +#define WLAN_EID_MIC 140 #define WLAN_EID_VENDOR_SPECIFIC 221 #define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC) #define WLAN_EID_VHT_CAPABILITY 191 @@ -1104,11 +1205,8 @@ struct ieee80211_softmac_stats { #define WEP_KEYS 4 #define WEP_KEY_LEN 13 - -#ifdef CONFIG_IEEE80211W - #define BIP_MAX_KEYID 5 - #define BIP_AAD_SIZE 20 -#endif /* CONFIG_IEEE80211W */ +#define BIP_MAX_KEYID 5 +#define BIP_AAD_SIZE 20 #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) @@ -1542,19 +1640,34 @@ enum rtw_ieee80211_category { RTW_WLAN_CATEGORY_DLS = 2, RTW_WLAN_CATEGORY_BACK = 3, RTW_WLAN_CATEGORY_PUBLIC = 4, /* IEEE 802.11 public action frames */ - RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5, + RTW_WLAN_CATEGORY_RADIO_MEAS = 5, RTW_WLAN_CATEGORY_FT = 6, RTW_WLAN_CATEGORY_HT = 7, RTW_WLAN_CATEGORY_SA_QUERY = 8, RTW_WLAN_CATEGORY_WNM = 10, RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, /* add for CONFIG_IEEE80211W, none 11w also can use */ RTW_WLAN_CATEGORY_TDLS = 12, - RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, /* add for CONFIG_IEEE80211W, none 11w also can use */ + RTW_WLAN_CATEGORY_MESH = 13, + RTW_WLAN_CATEGORY_MULTIHOP = 14, + RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, RTW_WLAN_CATEGORY_WMM = 17, RTW_WLAN_CATEGORY_VHT = 21, RTW_WLAN_CATEGORY_P2P = 0x7f,/* P2P action frames */ }; +#define CATEGORY_IS_GROUP_PRIVACY(cat) \ + (cat == RTW_WLAN_CATEGORY_MESH || cat == RTW_WLAN_CATEGORY_MULTIHOP) + +#define CATEGORY_IS_NON_ROBUST(cat) \ + (cat == RTW_WLAN_CATEGORY_PUBLIC \ + || cat == RTW_WLAN_CATEGORY_HT \ + || cat == RTW_WLAN_CATEGORY_UNPROTECTED_WNM \ + || cat == RTW_WLAN_CATEGORY_SELF_PROTECTED \ + || cat == RTW_WLAN_CATEGORY_VHT \ + || cat == RTW_WLAN_CATEGORY_P2P) + +#define CATEGORY_IS_ROBUST(cat) !CATEGORY_IS_NON_ROBUST(cat) + /* SPECTRUM_MGMT action code */ enum rtw_ieee80211_spectrum_mgmt_actioncode { RTW_WLAN_ACTION_SPCT_MSR_REQ = 0, @@ -1565,6 +1678,32 @@ enum rtw_ieee80211_spectrum_mgmt_actioncode { RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, }; +/* SELF_PROTECTED action code */ +enum rtw_ieee80211_self_protected_actioncode { + RTW_ACT_SELF_PROTECTED_RSVD = 0, + RTW_ACT_SELF_PROTECTED_MESH_OPEN = 1, + RTW_ACT_SELF_PROTECTED_MESH_CONF = 2, + RTW_ACT_SELF_PROTECTED_MESH_CLOSE = 3, + RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM = 4, + RTW_ACT_SELF_PROTECTED_MESH_GK_ACK = 5, + RTW_ACT_SELF_PROTECTED_NUM, +}; + +/* MESH action code */ +enum rtw_ieee80211_mesh_actioncode { + RTW_ACT_MESH_LINK_METRIC_REPORT, + RTW_ACT_MESH_HWMP_PATH_SELECTION, + RTW_ACT_MESH_GATE_ANNOUNCEMENT, + RTW_ACT_MESH_CONGESTION_CONTROL_NOTIFICATION, + RTW_ACT_MESH_MCCA_SETUP_REQUEST, + RTW_ACT_MESH_MCCA_SETUP_REPLY, + RTW_ACT_MESH_MCCA_ADVERTISEMENT_REQUEST, + RTW_ACT_MESH_MCCA_ADVERTISEMENT, + RTW_ACT_MESH_MCCA_TEARDOWN, + RTW_ACT_MESH_TBTT_ADJUSTMENT_REQUEST, + RTW_ACT_MESH_TBTT_ADJUSTMENT_RESPONSE, +}; + enum _PUBLIC_ACTION { ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */ ACT_PUBLIC_DSE_ENABLE = 1, @@ -1649,14 +1788,22 @@ enum rtw_ieee80211_vht_actioncode { #ifdef CONFIG_RTW_80211R enum rtw_ieee80211_ft_actioncode { RTW_WLAN_ACTION_FT_RESV, - RTW_WLAN_ACTION_FT_REQUEST, - RTW_WLAN_ACTION_FT_RESPONSE, - RTW_WLAN_ACTION_FT_CONFIRM, + RTW_WLAN_ACTION_FT_REQ, + RTW_WLAN_ACTION_FT_RSP, + RTW_WLAN_ACTION_FT_CONF, RTW_WLAN_ACTION_FT_ACK, RTW_WLAN_ACTION_FT_MAX, }; #endif +#ifdef CONFIG_RTW_WNM +enum rtw_ieee80211_wnm_actioncode { + RTW_WLAN_ACTION_WNM_BTM_QUERY = 6, + RTW_WLAN_ACTION_WNM_BTM_REQ = 7, + RTW_WLAN_ACTION_WNM_BTM_RSP = 8, +}; +#endif + #define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs) * 00:50:F2 */ #ifndef PLATFORM_FREEBSD /* Baron BSD has defined */ @@ -1684,6 +1831,55 @@ enum rtw_ieee80211_ft_actioncode { #define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */ +enum rtw_ieee80211_rann_flags { + RTW_RANN_FLAG_IS_GATE = 1 << 0, +}; + +/** + * enum rtw_ieee80211_preq_flags - mesh PREQ element flags + * + * @RTW_IEEE80211_PREQ_IS_GATE_FLAG: Gate Announcement subfield + * @RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG: proactive PREP subfield + */ +enum rtw_ieee80211_preq_flags { + RTW_IEEE80211_PREQ_IS_GATE_FLAG = 1 << 0, + RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG = 1 << 2, +}; + +/** + * enum rtw_ieee80211_preq_target_flags - mesh PREQ element per target flags + * + * @RTW_IEEE80211_PREQ_TO_FLAG: target only subfield + * @RTW_IEEE80211_PREQ_USN_FLAG: unknown target HWMP sequence number subfield + */ +enum rtw_ieee80211_preq_target_flags { + RTW_IEEE80211_PREQ_TO_FLAG = 1<<0, + RTW_IEEE80211_PREQ_USN_FLAG = 1<<2, +}; + +/** + * enum rtw_ieee80211_root_mode_identifier - root mesh STA mode identifier + * + * These attribute are used by dot11MeshHWMPRootMode to set root mesh STA mode + * + * @RTW_IEEE80211_ROOTMODE_NO_ROOT: the mesh STA is not a root mesh STA (default) + * @RTW_IEEE80211_ROOTMODE_ROOT: the mesh STA is a root mesh STA if greater than + * this value + * @RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP: the mesh STA is a root mesh STA supports + * the proactive PREQ with proactive PREP subfield set to 0 + * @RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP: the mesh STA is a root mesh STA + * supports the proactive PREQ with proactive PREP subfield set to 1 + * @RTW_IEEE80211_PROACTIVE_RANN: the mesh STA is a root mesh STA supports + * the proactive RANN + */ +enum rtw_ieee80211_root_mode_identifier { + RTW_IEEE80211_ROOTMODE_NO_ROOT = 0, + RTW_IEEE80211_ROOTMODE_ROOT = 1, + RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP = 2, + RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP = 3, + RTW_IEEE80211_PROACTIVE_RANN = 4, +}; + /** * enum rtw_ieee80211_channel_flags - channel flags * @@ -1806,6 +2002,18 @@ struct rtw_ieee802_11_elems { u8 vht_operation_len; u8 *vht_op_mode_notify; u8 vht_op_mode_notify_len; + u8 *rm_en_cap; + u8 rm_en_cap_len; +#ifdef CONFIG_RTW_MESH + u8 *preq; + u8 preq_len; + u8 *prep; + u8 prep_len; + u8 *perr; + u8 perr_len; + u8 *rann; + u8 rann_len; +#endif }; typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes; @@ -1815,7 +2023,7 @@ ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, int show_errors); u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen); -u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen); +u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, const u8 *source, uint *frlen); enum secondary_ch_offset { SCN = 0, /* no secondary channel */ @@ -1828,25 +2036,48 @@ u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset); u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence); -u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit); -u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen); +u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit); +int rtw_remove_ie_g_rate(u8 *ie, uint *ie_len, uint offset, u8 eid); +u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen); int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len); void rtw_set_supported_rate(u8 *SupportedRates, uint mode) ; +#define GET_RSN_CAP_MFP_OPTION(cap) LE_BITS_TO_2BYTE(((u8 *)(cap)), 6, 2) + +#define MFP_NO 0 +#define MFP_INVALID 1 +#define MFP_OPTIONAL 2 +#define MFP_REQUIRED 3 + +struct rsne_info { + u8 *gcs; + u16 pcs_cnt; + u8 *pcs_list; + u16 akm_cnt; + u8 *akm_list; + u8 *cap; + u16 pmkid_cnt; + u8 *pmkid_list; + u8 *gmcs; + + u8 err; +}; +int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info); + unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit); unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit); int rtw_get_wpa_cipher_suite(u8 *s); int rtw_get_wpa2_cipher_suite(u8 *s); int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len); int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); -int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); +int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x, u8 *mfp_opt); int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len); u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen); -u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, u8 frame_type); -u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); +u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type); +u8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr); u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content); @@ -1859,17 +2090,21 @@ u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 #define for_each_ie(ie, buf, buf_len) \ for (ie = (void *)buf; (((u8 *)ie) - ((u8 *)buf) + 1) < buf_len; ie = (void *)(((u8 *)ie) + *(((u8 *)ie)+1) + 2)) -void dump_ies(void *sel, u8 *buf, u32 buf_len); +void dump_ies(void *sel, const u8 *buf, u32 buf_len); #ifdef CONFIG_80211N_HT -void dump_ht_cap_ie_content(void *sel, u8 *buf, u32 buf_len); +#define HT_SC_OFFSET_MAX 4 +extern const char *const _ht_sc_offset_str[]; +#define ht_sc_offset_str(sc) (((sc) >= HT_SC_OFFSET_MAX) ? _ht_sc_offset_str[2] : _ht_sc_offset_str[(sc)]) + +void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len); #endif -void dump_wps_ie(void *sel, u8 *ie, u32 ie_len); +void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len); -void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset); +void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht); -void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset); +void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht); bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a , u8 ch_b, u8 bw_b, u8 offset_b); @@ -1878,8 +2113,8 @@ void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len); int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie); -void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len); -u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen); +void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len); +u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen); u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr); u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content); u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr); @@ -1889,8 +2124,8 @@ u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen); void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex); void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); -void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len); -u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); +void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len); +u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr); u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content); uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg); @@ -1909,7 +2144,7 @@ int rtw_get_bit_value_from_ieee_value(u8 val); uint rtw_is_cckrates_included(u8 *rate); uint rtw_is_cckratesonly_included(u8 *rate); - +uint rtw_get_cckrate_size(u8 *rate,u32 rate_length); int rtw_check_network_type(unsigned char *rate, int ratelen, int channel); void rtw_get_bcn_info(struct wlan_network *pnetwork); diff --git a/include/ieee80211_ext.h b/include/ieee80211_ext.h index 03cc330..94a8e58 100644 --- a/include/ieee80211_ext.h +++ b/include/ieee80211_ext.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __IEEE80211_EXT_H #define __IEEE80211_EXT_H diff --git a/include/if_ether.h b/include/if_ether.h index 9d08f56..a3007c4 100644 --- a/include/if_ether.h +++ b/include/if_ether.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_IF_ETHER_H #define _LINUX_IF_ETHER_H diff --git a/include/ip.h b/include/ip.h index c78034d..4feb98f 100644 --- a/include/ip.h +++ b/include/ip.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_IP_H #define _LINUX_IP_H diff --git a/include/linux/wireless.h b/include/linux/wireless.h index b4bb716..c7f4a6c 100644 --- a/include/linux/wireless.h +++ b/include/linux/wireless.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _LINUX_WIRELESS_H #define _LINUX_WIRELESS_H diff --git a/include/mlme_osdep.h b/include/mlme_osdep.h index 5b85fc3..131eb09 100644 --- a/include/mlme_osdep.h +++ b/include/mlme_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,20 +11,10 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __MLME_OSDEP_H_ #define __MLME_OSDEP_H_ - -#if defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) - extern int time_after(u32 now, u32 old); -#endif - extern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated); extern void rtw_os_indicate_connect(_adapter *adapter); void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted); diff --git a/include/mp_custom_oid.h b/include/mp_custom_oid.h index 7ca76ad..8ed1441 100644 --- a/include/mp_custom_oid.h +++ b/include/mp_custom_oid.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __CUSTOM_OID_H #define __CUSTOM_OID_H diff --git a/include/nic_spec.h b/include/nic_spec.h index c0a952f..913ef9b 100644 --- a/include/nic_spec.h +++ b/include/nic_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __NIC_SPEC_H__ diff --git a/include/osdep_intf.h b/include/osdep_intf.h index 6d5e9f3..7be0880 100644 --- a/include/osdep_intf.h +++ b/include/osdep_intf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __OSDEP_INTF_H_ #define __OSDEP_INTF_H_ @@ -127,6 +122,8 @@ u16 rtw_recv_select_queue(struct sk_buff *skb); int rtw_ndev_notifier_register(void); void rtw_ndev_notifier_unregister(void); +void rtw_inetaddr_notifier_register(void); +void rtw_inetaddr_notifier_unregister(void); #include "../os_dep/linux/rtw_proc.h" @@ -160,9 +157,8 @@ void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj); #endif void rtw_ndev_destructor(_nic_hdl ndev); - #ifdef CONFIG_ARP_KEEP_ALIVE -int rtw_gw_addr_query(_adapter *padapter); +int rtw_gw_addr_query(_adapter *padapter); #endif int rtw_suspend_common(_adapter *padapter); diff --git a/include/osdep_service.h b/include/osdep_service.h index ef43d85..35988cc 100644 --- a/include/osdep_service.h +++ b/include/osdep_service.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __OSDEP_SERVICE_H_ #define __OSDEP_SERVICE_H_ @@ -29,6 +24,9 @@ #define RTW_RBUF_UNAVAIL 5 #define RTW_RBUF_PKT_UNAVAIL 6 #define RTW_SDIO_READ_PORT_FAIL 7 +#define RTW_ALREADY 8 +#define RTW_RA_RESOLVING 9 +#define RTW_BMC_NO_NEED 10 /* #define RTW_STATUS_TIMEDOUT -110 */ @@ -44,7 +42,11 @@ #endif #ifdef PLATFORM_LINUX + #include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)) #include + #include +#endif #include #endif @@ -138,12 +140,13 @@ typedef enum mstat_status { #ifdef DBG_MEM_ALLOC void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz); void rtw_mstat_dump(void *sel); -u8 *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); -u8 *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); -void dbg_rtw_vmfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); -u8 *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line); -u8 *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); -void dbg_rtw_mfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); +bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size); +void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_vmfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); +void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_mfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line); void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); @@ -210,12 +213,13 @@ void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dm #else /* DBG_MEM_ALLOC */ #define rtw_mstat_update(flag, status, sz) do {} while (0) #define rtw_mstat_dump(sel) do {} while (0) -u8 *_rtw_vmalloc(u32 sz); -u8 *_rtw_zvmalloc(u32 sz); -void _rtw_vmfree(u8 *pbuf, u32 sz); -u8 *_rtw_zmalloc(u32 sz); -u8 *_rtw_malloc(u32 sz); -void _rtw_mfree(u8 *pbuf, u32 sz); +#define match_mstat_sniff_rules(flags, size) _FALSE +void *_rtw_vmalloc(u32 sz); +void *_rtw_zvmalloc(u32 sz); +void _rtw_vmfree(void *pbuf, u32 sz); +void *_rtw_zmalloc(u32 sz); +void *_rtw_malloc(u32 sz); +void _rtw_mfree(void *pbuf, u32 sz); struct sk_buff *_rtw_skb_alloc(u32 sz); void _rtw_skb_free(struct sk_buff *skb); @@ -284,6 +288,11 @@ void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_a extern void *rtw_malloc2d(int h, int w, size_t size); extern void rtw_mfree2d(void *pbuf, int h, int w, int size); +void rtw_os_pkt_free(_pkt *pkt); +_pkt *rtw_os_pkt_copy(_pkt *pkt); +void *rtw_os_pkt_data(_pkt *pkt); +u32 rtw_os_pkt_len(_pkt *pkt); + extern void _rtw_memcpy(void *dec, const void *sour, u32 sz); extern void _rtw_memmove(void *dst, const void *src, u32 sz); extern int _rtw_memcmp(const void *dst, const void *src, u32 sz); @@ -293,10 +302,20 @@ extern void _rtw_init_listhead(_list *list); extern u32 rtw_is_list_empty(_list *phead); extern void rtw_list_insert_head(_list *plist, _list *phead); extern void rtw_list_insert_tail(_list *plist, _list *phead); +void rtw_list_splice(_list *list, _list *head); +void rtw_list_splice_init(_list *list, _list *head); +void rtw_list_splice_tail(_list *list, _list *head); + #ifndef PLATFORM_FREEBSD extern void rtw_list_delete(_list *plist); #endif /* PLATFORM_FREEBSD */ +void rtw_hlist_head_init(rtw_hlist_head *h); +void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h); +void rtw_hlist_del(rtw_hlist_node *n); +void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h); +void rtw_hlist_del_rcu(rtw_hlist_node *n); + extern void _rtw_init_sema(_sema *sema, int init_val); extern void _rtw_free_sema(_sema *sema); extern void _rtw_up_sema(_sema *sema); @@ -317,11 +336,36 @@ extern void _rtw_deinit_queue(_queue *pqueue); extern u32 _rtw_queue_empty(_queue *pqueue); extern u32 rtw_end_of_queue_search(_list *queue, _list *pelement); -extern u32 rtw_get_current_time(void); -extern u32 rtw_systime_to_ms(u32 systime); -extern u32 rtw_ms_to_systime(u32 ms); -extern s32 rtw_get_passing_time_ms(u32 start); -extern s32 rtw_get_time_interval_ms(u32 start, u32 end); +extern systime _rtw_get_current_time(void); +extern u32 _rtw_systime_to_ms(systime stime); +extern systime _rtw_ms_to_systime(u32 ms); +extern systime _rtw_us_to_systime(u32 us); +extern s32 _rtw_get_passing_time_ms(systime start); +extern s32 _rtw_get_remaining_time_ms(systime end); +extern s32 _rtw_get_time_interval_ms(systime start, systime end); +extern bool _rtw_time_after(systime a, systime b); + +#ifdef DBG_SYSTIME +#define rtw_get_current_time() ({systime __stime = _rtw_get_current_time(); __stime;}) +#define rtw_systime_to_ms(stime) ({u32 __ms = _rtw_systime_to_ms(stime); typecheck(systime, stime); __ms;}) +#define rtw_ms_to_systime(ms) ({systime __stime = _rtw_ms_to_systime(ms); __stime;}) +#define rtw_us_to_systime(us) ({systime __stime = _rtw_us_to_systime(us); __stime;}) +#define rtw_get_passing_time_ms(start) ({u32 __ms = _rtw_get_passing_time_ms(start); typecheck(systime, start); __ms;}) +#define rtw_get_remaining_time_ms(end) ({u32 __ms = _rtw_get_remaining_time_ms(end); typecheck(systime, end); __ms;}) +#define rtw_get_time_interval_ms(start, end) ({u32 __ms = _rtw_get_time_interval_ms(start, end); typecheck(systime, start); typecheck(systime, end); __ms;}) +#define rtw_time_after(a,b) ({bool __r = _rtw_time_after(a,b); typecheck(systime, a); typecheck(systime, b); __r;}) +#define rtw_time_before(a,b) ({bool __r = _rtw_time_after(b, a); typecheck(systime, a); typecheck(systime, b); __r;}) +#else +#define rtw_get_current_time() _rtw_get_current_time() +#define rtw_systime_to_ms(stime) _rtw_systime_to_ms(stime) +#define rtw_ms_to_systime(ms) _rtw_ms_to_systime(ms) +#define rtw_us_to_systime(us) _rtw_us_to_systime(us) +#define rtw_get_passing_time_ms(start) _rtw_get_passing_time_ms(start) +#define rtw_get_remaining_time_ms(end) _rtw_get_remaining_time_ms(end) +#define rtw_get_time_interval_ms(start, end) _rtw_get_time_interval_ms(start, end) +#define rtw_time_after(a,b) _rtw_time_after(a,b) +#define rtw_time_before(a,b) _rtw_time_after(b,a) +#endif extern void rtw_sleep_schedulable(int ms); @@ -343,7 +387,7 @@ extern void rtw_udelay_os(int us); extern void rtw_yield_os(void); -extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc); +extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx); __inline static unsigned char _cancel_timer_ex(_timer *ptimer) @@ -358,9 +402,6 @@ __inline static unsigned char _cancel_timer_ex(_timer *ptimer) static __inline void thread_enter(char *name) { #ifdef PLATFORM_LINUX -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) - daemonize("%s", name); -#endif allow_signal(SIGTERM); #endif #ifdef PLATFORM_FREEBSD @@ -371,14 +412,29 @@ void thread_exit(_completion *comp); void _rtw_init_completion(_completion *comp); void _rtw_wait_for_comp_timeout(_completion *comp); void _rtw_wait_for_comp(_completion *comp); -#if 1 -#define rtw_wait_for_thread_stop(_comp) _rtw_wait_for_comp_timeout(_comp) -#else -#define rtw_wait_for_thread_stop(_comp) _rtw_wait_for_comp(_comp) -#endif -bool rtw_thread_stop(_thread_hdl_ th); -bool rtw_thread_should_stop(void); +static inline bool rtw_thread_stop(_thread_hdl_ th) +{ +#ifdef PLATFORM_LINUX + return kthread_stop(th); +#endif +} +static inline void rtw_thread_wait_stop(void) +{ +#ifdef PLATFORM_LINUX + #if 0 + while (!kthread_should_stop()) + rtw_msleep_os(10); + #else + set_current_state(TASK_INTERRUPTIBLE); + while (!kthread_should_stop()) { + schedule(); + set_current_state(TASK_INTERRUPTIBLE); + } + __set_current_state(TASK_RUNNING); + #endif +#endif +} __inline static void flush_signals_thread(void) { @@ -522,6 +578,7 @@ static inline int largest_bit(u32 bitmask) return i; } +#define rtw_abs(a) (a < 0 ? -a : a) #define rtw_min(a, b) ((a > b) ? b : a) #define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b))) #define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b))) @@ -533,16 +590,14 @@ static inline int largest_bit(u32 bitmask) #define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] #endif +bool rtw_macaddr_is_larger(const u8 *a, const u8 *b); extern void rtw_suspend_lock_init(void); extern void rtw_suspend_lock_uninit(void); extern void rtw_lock_suspend(void); extern void rtw_unlock_suspend(void); extern void rtw_lock_suspend_timeout(u32 timeout_ms); -extern void rtw_lock_ext_suspend_timeout(u32 timeout_ms); -extern void rtw_lock_rx_suspend_timeout(u32 timeout_ms); extern void rtw_lock_traffic_suspend_timeout(u32 timeout_ms); -extern void rtw_lock_resume_scan_timeout(u32 timeout_ms); extern void rtw_resume_lock_suspend(void); extern void rtw_resume_unlock_suspend(void); #ifdef CONFIG_AP_WOWLAN @@ -550,6 +605,10 @@ extern void rtw_softap_lock_suspend(void); extern void rtw_softap_unlock_suspend(void); #endif +extern void rtw_set_bit(int nr, unsigned long *addr); +extern void rtw_clear_bit(int nr, unsigned long *addr); +extern int rtw_test_and_clear_bit(int nr, unsigned long *addr); + extern void ATOMIC_SET(ATOMIC_T *v, int i); extern int ATOMIC_READ(ATOMIC_T *v); extern void ATOMIC_ADD(ATOMIC_T *v, int i); @@ -560,6 +619,7 @@ extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i); extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i); extern int ATOMIC_INC_RETURN(ATOMIC_T *v); extern int ATOMIC_DEC_RETURN(ATOMIC_T *v); +extern bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u); /* File operation APIs, just for linux now */ extern int rtw_is_file_readable(const char *path); @@ -642,6 +702,17 @@ extern u32 rtw_random32(void); (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \ (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \ (((u64) (a)[1]) << 8) | ((u64) (a)[0])) +#define RTW_PUT_LE64(a, val) \ + do { \ + (a)[7] = (u8) ((((u64) (val)) >> 56) & 0xff); \ + (a)[6] = (u8) ((((u64) (val)) >> 48) & 0xff); \ + (a)[5] = (u8) ((((u64) (val)) >> 40) & 0xff); \ + (a)[4] = (u8) ((((u64) (val)) >> 32) & 0xff); \ + (a)[3] = (u8) ((((u64) (val)) >> 24) & 0xff); \ + (a)[2] = (u8) ((((u64) (val)) >> 16) & 0xff); \ + (a)[1] = (u8) ((((u64) (val)) >> 8) & 0xff); \ + (a)[0] = (u8) (((u64) (val)) & 0xff); \ + } while (0) void rtw_buf_free(u8 **buf, u32 *buf_len); void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len); @@ -685,6 +756,18 @@ struct map_t { int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf); u8 map_read8(const struct map_t *map, u16 offset); +struct blacklist_ent { + _list list; + u8 addr[ETH_ALEN]; + systime exp_time; +}; + +int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms); +int rtw_blacklist_del(_queue *blist, const u8 *addr); +int rtw_blacklist_search(_queue *blist, const u8 *addr); +void rtw_blacklist_flush(_queue *blist); +void dump_blacklist(void *sel, _queue *blist, const char *title); + /* String handler */ BOOLEAN is_null(char c); @@ -695,6 +778,10 @@ BOOLEAN IsHexDigit(char chTmp); BOOLEAN is_alpha(char chTmp); char alpha_to_upper(char c); +int hex2num_i(char c); +int hex2byte_i(const char *hex); +int hexstr2bin(const char *hex, u8 *buf, size_t len); + /* * Write formatted output to sized buffer */ diff --git a/include/osdep_service_bsd.h b/include/osdep_service_bsd.h index 24d5bf6..4412963 100644 --- a/include/osdep_service_bsd.h +++ b/include/osdep_service_bsd.h @@ -1,670 +1,664 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __OSDEP_BSD_SERVICE_H_ -#define __OSDEP_BSD_SERVICE_H_ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include "usbdevs.h" - -#define USB_DEBUG_VAR rum_debug -#include - -#if 1 //Baron porting from linux, it's all temp solution, needs to check again -#include -#include /* XXX for PCPU_GET */ -// typedef struct semaphore _sema; - typedef struct sema _sema; -// typedef spinlock_t _lock; - typedef struct mtx _lock; - typedef struct mtx _mutex; - typedef struct timer_list _timer; - struct list_head { - struct list_head *next, *prev; - }; - struct __queue { - struct list_head queue; - _lock lock; - }; - - //typedef struct sk_buff _pkt; - typedef struct mbuf _pkt; - typedef struct mbuf _buffer; - - typedef struct __queue _queue; - typedef struct list_head _list; - typedef int _OS_STATUS; - //typedef u32 _irqL; - typedef unsigned long _irqL; - typedef struct ifnet * _nic_hdl; - - typedef pid_t _thread_hdl_; -// typedef struct thread _thread_hdl_; - typedef void thread_return; - typedef void* thread_context; - - typedef void timer_hdl_return; - typedef void* timer_hdl_context; - typedef struct work_struct _workitem; - -#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) -/* emulate a modern version */ -#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35) - -#define WIRELESS_EXT -1 -#define HZ hz -#define spin_lock_irqsave mtx_lock_irqsave -#define spin_lock_bh mtx_lock_irqsave -#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));} -//#define IFT_RTW 0xf9 //ifnet allocate type for RTW -#define free_netdev if_free -#define LIST_CONTAINOR(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) -#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n)) -/* - * Linux timers are emulated using FreeBSD callout functions - * (and taskqueue functionality). - * - * Currently no timer stats functionality. - * - * See (linux_compat) processes.c - * - */ -struct timer_list { +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __OSDEP_BSD_SERVICE_H_ +#define __OSDEP_BSD_SERVICE_H_ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include "usbdevs.h" + +#define USB_DEBUG_VAR rum_debug +#include + +#if 1 //Baron porting from linux, it's all temp solution, needs to check again +#include +#include /* XXX for PCPU_GET */ +// typedef struct semaphore _sema; + typedef struct sema _sema; +// typedef spinlock_t _lock; + typedef struct mtx _lock; + typedef struct mtx _mutex; + typedef struct rtw_timer_list _timer; + struct list_head { + struct list_head *next, *prev; + }; + struct __queue { + struct list_head queue; + _lock lock; + }; + + typedef struct mbuf _pkt; + typedef struct mbuf _buffer; + + typedef struct __queue _queue; + typedef struct list_head _list; + typedef int _OS_STATUS; + //typedef u32 _irqL; + typedef unsigned long _irqL; + typedef struct ifnet * _nic_hdl; + + typedef pid_t _thread_hdl_; +// typedef struct thread _thread_hdl_; + typedef void thread_return; + typedef void* thread_context; + + typedef void timer_hdl_return; + typedef void* timer_hdl_context; + typedef struct work_struct _workitem; + +#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) +/* emulate a modern version */ +#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35) + +#define WIRELESS_EXT -1 +#define HZ hz +#define spin_lock_irqsave mtx_lock_irqsave +#define spin_lock_bh mtx_lock_irqsave +#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));} +//#define IFT_RTW 0xf9 //ifnet allocate type for RTW +#define free_netdev if_free +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) +#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n)) +/* + * Linux timers are emulated using FreeBSD callout functions + * (and taskqueue functionality). + * + * Currently no timer stats functionality. + * + * See (linux_compat) processes.c + * + */ +struct rtw_timer_list { struct callout callout; void (*function)(void *); void *arg; }; - -struct workqueue_struct; -struct work_struct; -typedef void (*work_func_t)(struct work_struct *work); -/* Values for the state of an item of work (work_struct) */ -typedef enum work_state { - WORK_STATE_UNSET = 0, - WORK_STATE_CALLOUT_PENDING = 1, - WORK_STATE_TASK_PENDING = 2, - WORK_STATE_WORK_CANCELLED = 3 -} work_state_t; - -struct work_struct { - struct task task; /* FreeBSD task */ - work_state_t state; /* the pending or otherwise state of work. */ - work_func_t func; -}; -#define spin_unlock_irqrestore mtx_unlock_irqrestore -#define spin_unlock_bh mtx_unlock_irqrestore -#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock); -extern void _rtw_spinlock_init(_lock *plock); - -//modify private structure to match freebsd -#define BITS_PER_LONG 32 -union ktime { - s64 tv64; -#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR) - struct { -#ifdef __BIG_ENDIAN - s32 sec, nsec; -#else - s32 nsec, sec; -#endif - } tv; -#endif -}; -#define kmemcheck_bitfield_begin(name) -#define kmemcheck_bitfield_end(name) -#define CHECKSUM_NONE 0 -typedef unsigned char *sk_buff_data_t; -typedef union ktime ktime_t; /* Kill this */ - -void rtw_mtx_lock(_lock *plock); - -void rtw_mtx_unlock(_lock *plock); - -/** - * struct sk_buff - socket buffer - * @next: Next buffer in list - * @prev: Previous buffer in list - * @sk: Socket we are owned by - * @tstamp: Time we arrived - * @dev: Device we arrived on/are leaving by - * @transport_header: Transport layer header - * @network_header: Network layer header - * @mac_header: Link layer header - * @_skb_refdst: destination entry (with norefcount bit) - * @sp: the security path, used for xfrm - * @cb: Control buffer. Free for use by every layer. Put private vars here - * @len: Length of actual data - * @data_len: Data length - * @mac_len: Length of link layer header - * @hdr_len: writable header length of cloned skb - * @csum: Checksum (must include start/offset pair) - * @csum_start: Offset from skb->head where checksumming should start - * @csum_offset: Offset from csum_start where checksum should be stored - * @local_df: allow local fragmentation - * @cloned: Head may be cloned (check refcnt to be sure) - * @nohdr: Payload reference only, must not modify header - * @pkt_type: Packet class - * @fclone: skbuff clone status - * @ip_summed: Driver fed us an IP checksum - * @priority: Packet queueing priority - * @users: User count - see {datagram,tcp}.c - * @protocol: Packet protocol from driver - * @truesize: Buffer size - * @head: Head of buffer - * @data: Data head pointer - * @tail: Tail pointer - * @end: End pointer - * @destructor: Destruct function - * @mark: Generic packet mark - * @nfct: Associated connection, if any - * @ipvs_property: skbuff is owned by ipvs - * @peeked: this packet has been seen already, so stats have been - * done for it, don't do them again - * @nf_trace: netfilter packet trace flag - * @nfctinfo: Relationship of this skb to the connection - * @nfct_reasm: netfilter conntrack re-assembly pointer - * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c - * @skb_iif: ifindex of device we arrived on - * @rxhash: the packet hash computed on receive - * @queue_mapping: Queue mapping for multiqueue devices - * @tc_index: Traffic control index - * @tc_verd: traffic control verdict - * @ndisc_nodetype: router type (from link layer) - * @dma_cookie: a cookie to one of several possible DMA operations - * done by skb DMA functions - * @secmark: security marking - * @vlan_tci: vlan tag control information - */ - -struct sk_buff { - /* These two members must be first. */ - struct sk_buff *next; - struct sk_buff *prev; - - ktime_t tstamp; - - struct sock *sk; - //struct net_device *dev; - struct ifnet *dev; - - /* - * This is the control buffer. It is free to use for every - * layer. Please put your private variables there. If you - * want to keep them across layers you have to do a skb_clone() - * first. This is owned by whoever has the skb queued ATM. - */ - char cb[48] __aligned(8); - - unsigned long _skb_refdst; -#ifdef CONFIG_XFRM - struct sec_path *sp; -#endif - unsigned int len, - data_len; - u16 mac_len, - hdr_len; - union { - u32 csum; - struct { - u16 csum_start; - u16 csum_offset; - }smbol2; - }smbol1; - u32 priority; - kmemcheck_bitfield_begin(flags1); - u8 local_df:1, - cloned:1, - ip_summed:2, - nohdr:1, - nfctinfo:3; - u8 pkt_type:3, - fclone:2, - ipvs_property:1, - peeked:1, - nf_trace:1; - kmemcheck_bitfield_end(flags1); - u16 protocol; - - void (*destructor)(struct sk_buff *skb); -#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) - struct nf_conntrack *nfct; - struct sk_buff *nfct_reasm; -#endif -#ifdef CONFIG_BRIDGE_NETFILTER - struct nf_bridge_info *nf_bridge; -#endif - - int skb_iif; -#ifdef CONFIG_NET_SCHED - u16 tc_index; /* traffic control index */ -#ifdef CONFIG_NET_CLS_ACT - u16 tc_verd; /* traffic control verdict */ -#endif -#endif - - u32 rxhash; - - kmemcheck_bitfield_begin(flags2); - u16 queue_mapping:16; -#ifdef CONFIG_IPV6_NDISC_NODETYPE - u8 ndisc_nodetype:2, - deliver_no_wcard:1; -#else - u8 deliver_no_wcard:1; -#endif - kmemcheck_bitfield_end(flags2); - - /* 0/14 bit hole */ - -#ifdef CONFIG_NET_DMA - dma_cookie_t dma_cookie; -#endif -#ifdef CONFIG_NETWORK_SECMARK - u32 secmark; -#endif - union { - u32 mark; - u32 dropcount; - }symbol3; - - u16 vlan_tci; - - sk_buff_data_t transport_header; - sk_buff_data_t network_header; - sk_buff_data_t mac_header; - /* These elements must be at the end, see alloc_skb() for details. */ - sk_buff_data_t tail; - sk_buff_data_t end; - unsigned char *head, - *data; - unsigned int truesize; - atomic_t users; -}; -struct sk_buff_head { - /* These two members must be first. */ - struct sk_buff *next; - struct sk_buff *prev; - - u32 qlen; - _lock lock; -}; -#define skb_tail_pointer(skb) skb->tail -static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len) -{ - unsigned char *tmp = skb_tail_pointer(skb); - //SKB_LINEAR_ASSERT(skb); - skb->tail += len; - skb->len += len; - return tmp; -} - -static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len) -{ - skb->len -= len; - if(skb->len < skb->data_len) - printf("%s(),%d,error!\n",__FUNCTION__,__LINE__); - return skb->data += len; -} -static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len) -{ - #ifdef PLATFORM_FREEBSD - return __skb_pull(skb, len); - #else - return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len); - #endif //PLATFORM_FREEBSD -} -static inline u32 skb_queue_len(const struct sk_buff_head *list_) -{ - return list_->qlen; -} -static inline void __skb_insert(struct sk_buff *newsk, - struct sk_buff *prev, struct sk_buff *next, - struct sk_buff_head *list) -{ - newsk->next = next; - newsk->prev = prev; - next->prev = prev->next = newsk; - list->qlen++; -} -static inline void __skb_queue_before(struct sk_buff_head *list, - struct sk_buff *next, - struct sk_buff *newsk) -{ - __skb_insert(newsk, next->prev, next, list); -} -static inline void skb_queue_tail(struct sk_buff_head *list, - struct sk_buff *newsk) -{ - mtx_lock(&list->lock); - __skb_queue_before(list, (struct sk_buff *)list, newsk); - mtx_unlock(&list->lock); -} -static inline struct sk_buff *skb_peek(struct sk_buff_head *list_) -{ - struct sk_buff *list = ((struct sk_buff *)list_)->next; - if (list == (struct sk_buff *)list_) - list = NULL; - return list; -} -static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list) -{ - struct sk_buff *next, *prev; - - list->qlen--; - next = skb->next; - prev = skb->prev; - skb->next = skb->prev = NULL; - next->prev = prev; - prev->next = next; -} - -static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list) -{ - mtx_lock(&list->lock); - - struct sk_buff *skb = skb_peek(list); - if (skb) - __skb_unlink(skb, list); - - mtx_unlock(&list->lock); - - return skb; -} -static inline void skb_reserve(struct sk_buff *skb, int len) -{ - skb->data += len; - skb->tail += len; -} -static inline void __skb_queue_head_init(struct sk_buff_head *list) -{ - list->prev = list->next = (struct sk_buff *)list; - list->qlen = 0; -} -/* - * This function creates a split out lock class for each invocation; - * this is needed for now since a whole lot of users of the skb-queue - * infrastructure in drivers have different locking usage (in hardirq) - * than the networking core (in softirq only). In the long run either the - * network layer or drivers should need annotation to consolidate the - * main types of usage into 3 classes. - */ -static inline void skb_queue_head_init(struct sk_buff_head *list) -{ - _rtw_spinlock_init(&list->lock); - __skb_queue_head_init(list); -} -unsigned long copy_from_user(void *to, const void *from, unsigned long n); -unsigned long copy_to_user(void *to, const void *from, unsigned long n); -struct sk_buff * dev_alloc_skb(unsigned int size); -struct sk_buff *skb_clone(const struct sk_buff *skb); -void dev_kfree_skb_any(struct sk_buff *skb); -#endif //Baron porting from linux, it's all temp solution, needs to check again - - -#if 1 // kenny add Linux compatibility code for Linux USB driver -#include - -#define __init // __attribute ((constructor)) -#define __exit // __attribute ((destructor)) - -/* - * Definitions for module_init and module_exit macros. - * - * These macros will use the SYSINIT framework to call a specified - * function (with no arguments) on module loading or unloading. - * - */ - -void module_init_exit_wrapper(void *arg); - -#define module_init(initfn) \ - SYSINIT(mod_init_ ## initfn, \ - SI_SUB_KLD, SI_ORDER_FIRST, \ - module_init_exit_wrapper, initfn) - -#define module_exit(exitfn) \ - SYSUNINIT(mod_exit_ ## exitfn, \ - SI_SUB_KLD, SI_ORDER_ANY, \ - module_init_exit_wrapper, exitfn) - -/* - * The usb_register and usb_deregister functions are used to register - * usb drivers with the usb subsystem. - */ -int usb_register(struct usb_driver *driver); -int usb_deregister(struct usb_driver *driver); - -/* - * usb_get_dev and usb_put_dev - increment/decrement the reference count - * of the usb device structure. - * - * Original body of usb_get_dev: - * - * if (dev) - * get_device(&dev->dev); - * return dev; - * - * Reference counts are not currently used in this compatibility - * layer. So these functions will do nothing. - */ -static inline struct usb_device * -usb_get_dev(struct usb_device *dev) -{ - return dev; -} - -static inline void -usb_put_dev(struct usb_device *dev) -{ - return; -} - - -// rtw_usb_compat_linux -int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags); -int rtw_usb_unlink_urb(struct urb *urb); -int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe); -int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe, - uint8_t request, uint8_t requesttype, - uint16_t value, uint16_t index, void *data, - uint16_t size, usb_timeout_t timeout); -int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index); -int rtw_usb_setup_endpoint(struct usb_device *dev, - struct usb_host_endpoint *uhe, usb_size_t bufsize); -struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags); -struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep); -struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index); -struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no); -void *rtw_usbd_get_intfdata(struct usb_interface *intf); -void rtw_usb_linux_register(void *arg); -void rtw_usb_linux_deregister(void *arg); -void rtw_usb_linux_free_device(struct usb_device *dev); -void rtw_usb_free_urb(struct urb *urb); -void rtw_usb_init_urb(struct urb *urb); -void rtw_usb_kill_urb(struct urb *urb); -void rtw_usb_set_intfdata(struct usb_interface *intf, void *data); -void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev, - struct usb_host_endpoint *uhe, void *buf, - int length, usb_complete_t callback, void *arg); -int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe, - void *data, int len, uint16_t *pactlen, usb_timeout_t timeout); -void *usb_get_intfdata(struct usb_interface *intf); -int usb_linux_init_endpoints(struct usb_device *udev); - - - -typedef struct urb * PURB; - -typedef unsigned gfp_t; -#define __GFP_WAIT ((gfp_t)0x10u) /* Can wait and reschedule? */ -#define __GFP_HIGH ((gfp_t)0x20u) /* Should access emergency pools? */ -#define __GFP_IO ((gfp_t)0x40u) /* Can start physical IO? */ -#define __GFP_FS ((gfp_t)0x80u) /* Can call down to low-level FS? */ -#define __GFP_COLD ((gfp_t)0x100u) /* Cache-cold page required */ -#define __GFP_NOWARN ((gfp_t)0x200u) /* Suppress page allocation failure warning */ -#define __GFP_REPEAT ((gfp_t)0x400u) /* Retry the allocation. Might fail */ -#define __GFP_NOFAIL ((gfp_t)0x800u) /* Retry for ever. Cannot fail */ -#define __GFP_NORETRY ((gfp_t)0x1000u)/* Do not retry. Might fail */ -#define __GFP_NO_GROW ((gfp_t)0x2000u)/* Slab internal usage */ -#define __GFP_COMP ((gfp_t)0x4000u)/* Add compound page metadata */ -#define __GFP_ZERO ((gfp_t)0x8000u)/* Return zeroed page on success */ -#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */ -#define __GFP_HARDWALL ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */ - -/* This equals 0, but use constants in case they ever change */ -#define GFP_NOWAIT (GFP_ATOMIC & ~__GFP_HIGH) -/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */ -#define GFP_ATOMIC (__GFP_HIGH) -#define GFP_NOIO (__GFP_WAIT) -#define GFP_NOFS (__GFP_WAIT | __GFP_IO) -#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS) -#define GFP_USER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL) -#define GFP_HIGHUSER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \ - __GFP_HIGHMEM) - - -#endif // kenny add Linux compatibility code for Linux USB - -__inline static _list *get_next(_list *list) -{ - return list->next; -} - -__inline static _list *get_list_head(_queue *queue) -{ - return (&(queue->queue)); -} - - -#define LIST_CONTAINOR(ptr, type, member) \ - ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) - - -__inline static void _enter_critical(_lock *plock, _irqL *pirqL) -{ - spin_lock_irqsave(plock, *pirqL); -} - -__inline static void _exit_critical(_lock *plock, _irqL *pirqL) -{ - spin_unlock_irqrestore(plock, *pirqL); -} - -__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) -{ - spin_lock_irqsave(plock, *pirqL); -} - -__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) -{ - spin_unlock_irqrestore(plock, *pirqL); -} - -__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) -{ - spin_lock_bh(plock, *pirqL); -} - -__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) -{ - spin_unlock_bh(plock, *pirqL); -} - -__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - - mtx_lock(pmutex); - -} - - -__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - - mtx_unlock(pmutex); - -} -static inline void __list_del(struct list_head * prev, struct list_head * next) -{ - next->prev = prev; - prev->next = next; -} -static inline void INIT_LIST_HEAD(struct list_head *list) -{ - list->next = list; - list->prev = list; -} -__inline static void rtw_list_delete(_list *plist) -{ - __list_del(plist->prev, plist->next); - INIT_LIST_HEAD(plist); -} - + +struct workqueue_struct; +struct work_struct; +typedef void (*work_func_t)(struct work_struct *work); +/* Values for the state of an item of work (work_struct) */ +typedef enum work_state { + WORK_STATE_UNSET = 0, + WORK_STATE_CALLOUT_PENDING = 1, + WORK_STATE_TASK_PENDING = 2, + WORK_STATE_WORK_CANCELLED = 3 +} work_state_t; + +struct work_struct { + struct task task; /* FreeBSD task */ + work_state_t state; /* the pending or otherwise state of work. */ + work_func_t func; +}; +#define spin_unlock_irqrestore mtx_unlock_irqrestore +#define spin_unlock_bh mtx_unlock_irqrestore +#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock); +extern void _rtw_spinlock_init(_lock *plock); + +//modify private structure to match freebsd +#define BITS_PER_LONG 32 +union ktime { + s64 tv64; +#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR) + struct { +#ifdef __BIG_ENDIAN + s32 sec, nsec; +#else + s32 nsec, sec; +#endif + } tv; +#endif +}; +#define kmemcheck_bitfield_begin(name) +#define kmemcheck_bitfield_end(name) +#define CHECKSUM_NONE 0 +typedef unsigned char *sk_buff_data_t; +typedef union ktime ktime_t; /* Kill this */ + +void rtw_mtx_lock(_lock *plock); + +void rtw_mtx_unlock(_lock *plock); + +/** + * struct sk_buff - socket buffer + * @next: Next buffer in list + * @prev: Previous buffer in list + * @sk: Socket we are owned by + * @tstamp: Time we arrived + * @dev: Device we arrived on/are leaving by + * @transport_header: Transport layer header + * @network_header: Network layer header + * @mac_header: Link layer header + * @_skb_refdst: destination entry (with norefcount bit) + * @sp: the security path, used for xfrm + * @cb: Control buffer. Free for use by every layer. Put private vars here + * @len: Length of actual data + * @data_len: Data length + * @mac_len: Length of link layer header + * @hdr_len: writable header length of cloned skb + * @csum: Checksum (must include start/offset pair) + * @csum_start: Offset from skb->head where checksumming should start + * @csum_offset: Offset from csum_start where checksum should be stored + * @local_df: allow local fragmentation + * @cloned: Head may be cloned (check refcnt to be sure) + * @nohdr: Payload reference only, must not modify header + * @pkt_type: Packet class + * @fclone: skbuff clone status + * @ip_summed: Driver fed us an IP checksum + * @priority: Packet queueing priority + * @users: User count - see {datagram,tcp}.c + * @protocol: Packet protocol from driver + * @truesize: Buffer size + * @head: Head of buffer + * @data: Data head pointer + * @tail: Tail pointer + * @end: End pointer + * @destructor: Destruct function + * @mark: Generic packet mark + * @nfct: Associated connection, if any + * @ipvs_property: skbuff is owned by ipvs + * @peeked: this packet has been seen already, so stats have been + * done for it, don't do them again + * @nf_trace: netfilter packet trace flag + * @nfctinfo: Relationship of this skb to the connection + * @nfct_reasm: netfilter conntrack re-assembly pointer + * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c + * @skb_iif: ifindex of device we arrived on + * @rxhash: the packet hash computed on receive + * @queue_mapping: Queue mapping for multiqueue devices + * @tc_index: Traffic control index + * @tc_verd: traffic control verdict + * @ndisc_nodetype: router type (from link layer) + * @dma_cookie: a cookie to one of several possible DMA operations + * done by skb DMA functions + * @secmark: security marking + * @vlan_tci: vlan tag control information + */ + +struct sk_buff { + /* These two members must be first. */ + struct sk_buff *next; + struct sk_buff *prev; + + ktime_t tstamp; + + struct sock *sk; + //struct net_device *dev; + struct ifnet *dev; + + /* + * This is the control buffer. It is free to use for every + * layer. Please put your private variables there. If you + * want to keep them across layers you have to do a skb_clone() + * first. This is owned by whoever has the skb queued ATM. + */ + char cb[48] __aligned(8); + + unsigned long _skb_refdst; +#ifdef CONFIG_XFRM + struct sec_path *sp; +#endif + unsigned int len, + data_len; + u16 mac_len, + hdr_len; + union { + u32 csum; + struct { + u16 csum_start; + u16 csum_offset; + }smbol2; + }smbol1; + u32 priority; + kmemcheck_bitfield_begin(flags1); + u8 local_df:1, + cloned:1, + ip_summed:2, + nohdr:1, + nfctinfo:3; + u8 pkt_type:3, + fclone:2, + ipvs_property:1, + peeked:1, + nf_trace:1; + kmemcheck_bitfield_end(flags1); + u16 protocol; + + void (*destructor)(struct sk_buff *skb); +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) + struct nf_conntrack *nfct; + struct sk_buff *nfct_reasm; +#endif +#ifdef CONFIG_BRIDGE_NETFILTER + struct nf_bridge_info *nf_bridge; +#endif + + int skb_iif; +#ifdef CONFIG_NET_SCHED + u16 tc_index; /* traffic control index */ +#ifdef CONFIG_NET_CLS_ACT + u16 tc_verd; /* traffic control verdict */ +#endif +#endif + + u32 rxhash; + + kmemcheck_bitfield_begin(flags2); + u16 queue_mapping:16; +#ifdef CONFIG_IPV6_NDISC_NODETYPE + u8 ndisc_nodetype:2, + deliver_no_wcard:1; +#else + u8 deliver_no_wcard:1; +#endif + kmemcheck_bitfield_end(flags2); + + /* 0/14 bit hole */ + +#ifdef CONFIG_NET_DMA + dma_cookie_t dma_cookie; +#endif +#ifdef CONFIG_NETWORK_SECMARK + u32 secmark; +#endif + union { + u32 mark; + u32 dropcount; + }symbol3; + + u16 vlan_tci; + + sk_buff_data_t transport_header; + sk_buff_data_t network_header; + sk_buff_data_t mac_header; + /* These elements must be at the end, see alloc_skb() for details. */ + sk_buff_data_t tail; + sk_buff_data_t end; + unsigned char *head, + *data; + unsigned int truesize; + atomic_t users; +}; +struct sk_buff_head { + /* These two members must be first. */ + struct sk_buff *next; + struct sk_buff *prev; + + u32 qlen; + _lock lock; +}; +#define skb_tail_pointer(skb) skb->tail +static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len) +{ + unsigned char *tmp = skb_tail_pointer(skb); + //SKB_LINEAR_ASSERT(skb); + skb->tail += len; + skb->len += len; + return tmp; +} + +static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len) +{ + skb->len -= len; + if(skb->len < skb->data_len) + printf("%s(),%d,error!\n",__FUNCTION__,__LINE__); + return skb->data += len; +} +static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len) +{ + #ifdef PLATFORM_FREEBSD + return __skb_pull(skb, len); + #else + return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len); + #endif //PLATFORM_FREEBSD +} +static inline u32 skb_queue_len(const struct sk_buff_head *list_) +{ + return list_->qlen; +} +static inline void __skb_insert(struct sk_buff *newsk, + struct sk_buff *prev, struct sk_buff *next, + struct sk_buff_head *list) +{ + newsk->next = next; + newsk->prev = prev; + next->prev = prev->next = newsk; + list->qlen++; +} +static inline void __skb_queue_before(struct sk_buff_head *list, + struct sk_buff *next, + struct sk_buff *newsk) +{ + __skb_insert(newsk, next->prev, next, list); +} +static inline void skb_queue_tail(struct sk_buff_head *list, + struct sk_buff *newsk) +{ + mtx_lock(&list->lock); + __skb_queue_before(list, (struct sk_buff *)list, newsk); + mtx_unlock(&list->lock); +} +static inline struct sk_buff *skb_peek(struct sk_buff_head *list_) +{ + struct sk_buff *list = ((struct sk_buff *)list_)->next; + if (list == (struct sk_buff *)list_) + list = NULL; + return list; +} +static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list) +{ + struct sk_buff *next, *prev; + + list->qlen--; + next = skb->next; + prev = skb->prev; + skb->next = skb->prev = NULL; + next->prev = prev; + prev->next = next; +} + +static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list) +{ + mtx_lock(&list->lock); + + struct sk_buff *skb = skb_peek(list); + if (skb) + __skb_unlink(skb, list); + + mtx_unlock(&list->lock); + + return skb; +} +static inline void skb_reserve(struct sk_buff *skb, int len) +{ + skb->data += len; + skb->tail += len; +} +static inline void __skb_queue_head_init(struct sk_buff_head *list) +{ + list->prev = list->next = (struct sk_buff *)list; + list->qlen = 0; +} +/* + * This function creates a split out lock class for each invocation; + * this is needed for now since a whole lot of users of the skb-queue + * infrastructure in drivers have different locking usage (in hardirq) + * than the networking core (in softirq only). In the long run either the + * network layer or drivers should need annotation to consolidate the + * main types of usage into 3 classes. + */ +static inline void skb_queue_head_init(struct sk_buff_head *list) +{ + _rtw_spinlock_init(&list->lock); + __skb_queue_head_init(list); +} +unsigned long copy_from_user(void *to, const void *from, unsigned long n); +unsigned long copy_to_user(void *to, const void *from, unsigned long n); +struct sk_buff * dev_alloc_skb(unsigned int size); +struct sk_buff *skb_clone(const struct sk_buff *skb); +void dev_kfree_skb_any(struct sk_buff *skb); +#endif //Baron porting from linux, it's all temp solution, needs to check again + + +#if 1 // kenny add Linux compatibility code for Linux USB driver +#include + +#define __init // __attribute ((constructor)) +#define __exit // __attribute ((destructor)) + +/* + * Definitions for module_init and module_exit macros. + * + * These macros will use the SYSINIT framework to call a specified + * function (with no arguments) on module loading or unloading. + * + */ + +void module_init_exit_wrapper(void *arg); + +#define module_init(initfn) \ + SYSINIT(mod_init_ ## initfn, \ + SI_SUB_KLD, SI_ORDER_FIRST, \ + module_init_exit_wrapper, initfn) + +#define module_exit(exitfn) \ + SYSUNINIT(mod_exit_ ## exitfn, \ + SI_SUB_KLD, SI_ORDER_ANY, \ + module_init_exit_wrapper, exitfn) + +/* + * The usb_register and usb_deregister functions are used to register + * usb drivers with the usb subsystem. + */ +int usb_register(struct usb_driver *driver); +int usb_deregister(struct usb_driver *driver); + +/* + * usb_get_dev and usb_put_dev - increment/decrement the reference count + * of the usb device structure. + * + * Original body of usb_get_dev: + * + * if (dev) + * get_device(&dev->dev); + * return dev; + * + * Reference counts are not currently used in this compatibility + * layer. So these functions will do nothing. + */ +static inline struct usb_device * +usb_get_dev(struct usb_device *dev) +{ + return dev; +} + +static inline void +usb_put_dev(struct usb_device *dev) +{ + return; +} + + +// rtw_usb_compat_linux +int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags); +int rtw_usb_unlink_urb(struct urb *urb); +int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe); +int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe, + uint8_t request, uint8_t requesttype, + uint16_t value, uint16_t index, void *data, + uint16_t size, usb_timeout_t timeout); +int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index); +int rtw_usb_setup_endpoint(struct usb_device *dev, + struct usb_host_endpoint *uhe, usb_size_t bufsize); +struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags); +struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep); +struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index); +struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no); +void *rtw_usbd_get_intfdata(struct usb_interface *intf); +void rtw_usb_linux_register(void *arg); +void rtw_usb_linux_deregister(void *arg); +void rtw_usb_linux_free_device(struct usb_device *dev); +void rtw_usb_free_urb(struct urb *urb); +void rtw_usb_init_urb(struct urb *urb); +void rtw_usb_kill_urb(struct urb *urb); +void rtw_usb_set_intfdata(struct usb_interface *intf, void *data); +void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev, + struct usb_host_endpoint *uhe, void *buf, + int length, usb_complete_t callback, void *arg); +int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe, + void *data, int len, uint16_t *pactlen, usb_timeout_t timeout); +void *usb_get_intfdata(struct usb_interface *intf); +int usb_linux_init_endpoints(struct usb_device *udev); + + + +typedef struct urb * PURB; + +typedef unsigned gfp_t; +#define __GFP_WAIT ((gfp_t)0x10u) /* Can wait and reschedule? */ +#define __GFP_HIGH ((gfp_t)0x20u) /* Should access emergency pools? */ +#define __GFP_IO ((gfp_t)0x40u) /* Can start physical IO? */ +#define __GFP_FS ((gfp_t)0x80u) /* Can call down to low-level FS? */ +#define __GFP_COLD ((gfp_t)0x100u) /* Cache-cold page required */ +#define __GFP_NOWARN ((gfp_t)0x200u) /* Suppress page allocation failure warning */ +#define __GFP_REPEAT ((gfp_t)0x400u) /* Retry the allocation. Might fail */ +#define __GFP_NOFAIL ((gfp_t)0x800u) /* Retry for ever. Cannot fail */ +#define __GFP_NORETRY ((gfp_t)0x1000u)/* Do not retry. Might fail */ +#define __GFP_NO_GROW ((gfp_t)0x2000u)/* Slab internal usage */ +#define __GFP_COMP ((gfp_t)0x4000u)/* Add compound page metadata */ +#define __GFP_ZERO ((gfp_t)0x8000u)/* Return zeroed page on success */ +#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */ +#define __GFP_HARDWALL ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */ + +/* This equals 0, but use constants in case they ever change */ +#define GFP_NOWAIT (GFP_ATOMIC & ~__GFP_HIGH) +/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */ +#define GFP_ATOMIC (__GFP_HIGH) +#define GFP_NOIO (__GFP_WAIT) +#define GFP_NOFS (__GFP_WAIT | __GFP_IO) +#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS) +#define GFP_USER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL) +#define GFP_HIGHUSER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \ + __GFP_HIGHMEM) + + +#endif // kenny add Linux compatibility code for Linux USB + +__inline static _list *get_next(_list *list) +{ + return list->next; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + + +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) + + +__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_lock_bh(plock, *pirqL); +} + +__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_unlock_bh(plock, *pirqL); +} + +__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + + mtx_lock(pmutex); + +} + + +__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + + mtx_unlock(pmutex); + +} +static inline void __list_del(struct list_head * prev, struct list_head * next) +{ + next->prev = prev; + prev->next = next; +} +static inline void INIT_LIST_HEAD(struct list_head *list) +{ + list->next = list; + list->prev = list; +} +__inline static void rtw_list_delete(_list *plist) +{ + __list_del(plist->prev, plist->next); + INIT_LIST_HEAD(plist); +} + static inline void timer_hdl(void *ctx) { _timer *timer = (_timer *)ctx; @@ -696,67 +690,67 @@ static inline void _init_timer(_timer *ptimer, _nic_hdl padapter, void *pfunc, v callout_init(&ptimer->callout, CALLOUT_MPSAFE); } -__inline static void _set_timer(_timer *ptimer,u32 delay_time) -{ +__inline static void _set_timer(_timer *ptimer,u32 delay_time) +{ if (ptimer->function && ptimer->arg) { - rtw_mtx_lock(NULL); + rtw_mtx_lock(NULL); callout_reset(&ptimer->callout, delay_time, timer_hdl, ptimer); - rtw_mtx_unlock(NULL); - } -} - -__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) -{ - rtw_mtx_lock(NULL); - callout_drain(&ptimer->callout); - rtw_mtx_unlock(NULL); + rtw_mtx_unlock(NULL); + } +} + +__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) +{ + rtw_mtx_lock(NULL); + callout_drain(&ptimer->callout); + rtw_mtx_unlock(NULL); *bcancelled = 1; /* assume an pending timer to be canceled */ -} - -__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) -{ - printf("%s Not implement yet! \n",__FUNCTION__); -} - -__inline static void _set_workitem(_workitem *pwork) -{ - printf("%s Not implement yet! \n",__FUNCTION__); -// schedule_work(pwork); -} - -// -// Global Mutex: can only be used at PASSIVE level. -// - -#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ -} - -#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ -} - -#define ATOMIC_INIT(i) { (i) } - -static __inline void thread_enter(char *name); - -//Atomic integer operations -typedef uint32_t ATOMIC_T ; - -#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc) - -#define rtw_free_netdev(netdev) if_free((netdev)) - -#define NDEV_FMT "%s" -#define NDEV_ARG(ndev) "" -#define ADPT_FMT "%s" -#define ADPT_ARG(adapter) "" -#define FUNC_NDEV_FMT "%s" -#define FUNC_NDEV_ARG(ndev) __func__ -#define FUNC_ADPT_FMT "%s" -#define FUNC_ADPT_ARG(adapter) __func__ - -#define STRUCT_PACKED - -#endif - +} + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + printf("%s Not implement yet! \n",__FUNCTION__); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + printf("%s Not implement yet! \n",__FUNCTION__); +// schedule_work(pwork); +} + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ +} + +#define ATOMIC_INIT(i) { (i) } + +static __inline void thread_enter(char *name); + +//Atomic integer operations +typedef uint32_t ATOMIC_T ; + +#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc) + +#define rtw_free_netdev(netdev) if_free((netdev)) + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + +#endif + diff --git a/include/osdep_service_ce.h b/include/osdep_service_ce.h index 4b5b779..2bf65ef 100644 --- a/include/osdep_service_ce.h +++ b/include/osdep_service_ce.h @@ -1,7 +1,7 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. @@ -11,119 +11,114 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ - -#ifndef __OSDEP_CE_SERVICE_H_ -#define __OSDEP_CE_SERVICE_H_ - - -#include -#include - -#ifdef CONFIG_SDIO_HCI -#include "SDCardDDK.h" -#endif - -#ifdef CONFIG_USB_HCI -#include -#endif - -typedef HANDLE _sema; -typedef LIST_ENTRY _list; -typedef NDIS_STATUS _OS_STATUS; - -typedef NDIS_SPIN_LOCK _lock; - -typedef HANDLE _rwlock; //Mutex - -typedef u32 _irqL; - -typedef NDIS_HANDLE _nic_hdl; - -struct timer_list { + *****************************************************************************/ + +#ifndef __OSDEP_CE_SERVICE_H_ +#define __OSDEP_CE_SERVICE_H_ + + +#include +#include + +#ifdef CONFIG_SDIO_HCI +#include "SDCardDDK.h" +#endif + +#ifdef CONFIG_USB_HCI +#include +#endif + +typedef HANDLE _sema; +typedef LIST_ENTRY _list; +typedef NDIS_STATUS _OS_STATUS; + +typedef NDIS_SPIN_LOCK _lock; + +typedef HANDLE _rwlock; //Mutex + +typedef u32 _irqL; + +typedef NDIS_HANDLE _nic_hdl; + +struct rtw_timer_list { NDIS_MINIPORT_TIMER ndis_timer; void (*function)(void *); void *arg; }; - -struct __queue { - LIST_ENTRY queue; - _lock lock; -}; - -typedef NDIS_PACKET _pkt; -typedef NDIS_BUFFER _buffer; -typedef struct __queue _queue; - -typedef HANDLE _thread_hdl_; -typedef DWORD thread_return; -typedef void* thread_context; -typedef NDIS_WORK_ITEM _workitem; - - - -#define SEMA_UPBND (0x7FFFFFFF) //8192 - -__inline static _list *get_prev(_list *list) -{ - return list->Blink; -} - -__inline static _list *get_next(_list *list) -{ - return list->Flink; -} - -__inline static _list *get_list_head(_queue *queue) -{ - return (&(queue->queue)); -} - -#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) - -__inline static void _enter_critical(_lock *plock, _irqL *pirqL) -{ - NdisAcquireSpinLock(plock); -} - -__inline static void _exit_critical(_lock *plock, _irqL *pirqL) -{ - NdisReleaseSpinLock(plock); -} - -__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) -{ - NdisDprAcquireSpinLock(plock); -} - -__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) -{ - NdisDprReleaseSpinLock(plock); -} - - -__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL) -{ - WaitForSingleObject(*prwlock, INFINITE ); - -} - -__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL) -{ - ReleaseMutex(*prwlock); -} - -__inline static void rtw_list_delete(_list *plist) -{ - RemoveEntryList(plist); - InitializeListHead(plist); -} - + +struct __queue { + LIST_ENTRY queue; + _lock lock; +}; + +typedef NDIS_PACKET _pkt; +typedef NDIS_BUFFER _buffer; +typedef struct __queue _queue; + +typedef HANDLE _thread_hdl_; +typedef DWORD thread_return; +typedef void* thread_context; +typedef NDIS_WORK_ITEM _workitem; + + + +#define SEMA_UPBND (0x7FFFFFFF) //8192 + +__inline static _list *get_prev(_list *list) +{ + return list->Blink; +} + +__inline static _list *get_next(_list *list) +{ + return list->Flink; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + +#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) + +__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +{ + NdisAcquireSpinLock(plock); +} + +__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +{ + NdisReleaseSpinLock(plock); +} + +__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + + +__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL) +{ + WaitForSingleObject(*prwlock, INFINITE ); + +} + +__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL) +{ + ReleaseMutex(*prwlock); +} + +__inline static void rtw_list_delete(_list *plist) +{ + RemoveEntryList(plist); + InitializeListHead(plist); +} + static inline void timer_hdl( IN PVOID SystemSpecific1, IN PVOID FunctionContext, @@ -151,55 +146,55 @@ static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled) { NdisMCancelTimer(ptimer, bcancelled); } - -__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) -{ - - NdisInitializeWorkItem(pwork, pfunc, cntx); -} - -__inline static void _set_workitem(_workitem *pwork) -{ - NdisScheduleWorkItem(pwork); -} - -#define ATOMIC_INIT(i) { (i) } - -// -// Global Mutex: can only be used at PASSIVE level. -// - -#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ - { \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ - NdisMSleep(10000); \ - } \ -} - -#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ -} - -// limitation of path length -#define PATH_LENGTH_MAX MAX_PATH - -//Atomic integer operations -#define ATOMIC_T LONG - -#define NDEV_FMT "%s" -#define NDEV_ARG(ndev) "" -#define ADPT_FMT "%s" -#define ADPT_ARG(adapter) "" -#define FUNC_NDEV_FMT "%s" -#define FUNC_NDEV_ARG(ndev) __func__ -#define FUNC_ADPT_FMT "%s" -#define FUNC_ADPT_ARG(adapter) __func__ - -#define STRUCT_PACKED - - -#endif - + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + + NdisInitializeWorkItem(pwork, pfunc, cntx); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + NdisScheduleWorkItem(pwork); +} + +#define ATOMIC_INIT(i) { (i) } + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ + { \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ + NdisMSleep(10000); \ + } \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ +} + +// limitation of path length +#define PATH_LENGTH_MAX MAX_PATH + +//Atomic integer operations +#define ATOMIC_T LONG + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + + +#endif + diff --git a/include/osdep_service_linux.h b/include/osdep_service_linux.h index 5510009..2f84f97 100644 --- a/include/osdep_service_linux.h +++ b/include/osdep_service_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __OSDEP_LINUX_SERVICE_H_ #define __OSDEP_LINUX_SERVICE_H_ @@ -33,6 +28,7 @@ #endif /* #include */ #include +#include #include #include #include @@ -49,6 +45,7 @@ #include #include #include +#include #include #include #include @@ -86,15 +83,16 @@ #include #endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29)) + #define CONFIG_IEEE80211_HT_ADDT_INFO +#endif + #ifdef CONFIG_IOCTL_CFG80211 /* #include */ #include #endif /* CONFIG_IOCTL_CFG80211 */ -#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX - #include - #include -#endif #ifdef CONFIG_HAS_EARLYSUSPEND #include @@ -158,7 +156,13 @@ typedef spinlock_t _lock; #else typedef struct semaphore _mutex; #endif -typedef struct timer_list _timer; +struct rtw_timer_list { + struct timer_list timer; + void (*function)(void *); + void *arg; +}; + +typedef struct rtw_timer_list _timer; typedef struct completion _completion; struct __queue { @@ -171,6 +175,25 @@ typedef unsigned char _buffer; typedef struct __queue _queue; typedef struct list_head _list; + +/* hlist */ +typedef struct hlist_head rtw_hlist_head; +typedef struct hlist_node rtw_hlist_node; + +/* RCU */ +typedef struct rcu_head rtw_rcu_head; +#define rtw_rcu_dereference(p) rcu_dereference((p)) +#define rtw_rcu_dereference_protected(p, c) rcu_dereference_protected(p, c) +#define rtw_rcu_assign_pointer(p, v) rcu_assign_pointer((p), (v)) +#define rtw_rcu_read_lock() rcu_read_lock() +#define rtw_rcu_read_unlock() rcu_read_unlock() +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34)) +#define rtw_rcu_access_pointer(p) rcu_access_pointer(p) +#endif + +/* rhashtable */ +#include "../os_dep/linux/rtw_rhashtable.h" + typedef int _OS_STATUS; /* typedef u32 _irqL; */ typedef unsigned long _irqL; @@ -193,6 +216,8 @@ typedef void *timer_hdl_context; #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) #endif +typedef unsigned long systime; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22)) /* Porting from linux kernel, for compatible with old kernel. */ static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb) @@ -216,20 +241,31 @@ static inline unsigned char *skb_end_pointer(const struct sk_buff *skb) } #endif -__inline static _list *get_next(_list *list) +__inline static void rtw_list_delete(_list *plist) { - return list->next; + list_del_init(plist); } -__inline static _list *get_list_head(_queue *queue) +__inline static _list *get_next(_list *list) { - return &(queue->queue); + return list->next; } - #define LIST_CONTAINOR(ptr, type, member) \ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) +#define rtw_list_first_entry(ptr, type, member) list_first_entry(ptr, type, member) + +#define rtw_hlist_for_each_entry(pos, head, member) hlist_for_each_entry(pos, head, member) +#define rtw_hlist_for_each_safe(pos, n, head) hlist_for_each_safe(pos, n, head) +#define rtw_hlist_entry(ptr, type, member) hlist_entry(ptr, type, member) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) +#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, n, head, member) +#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, head, member) +#else +#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, np, n, head, member) +#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, node, head, member) +#endif __inline static void _enter_critical(_lock *plock, _irqL *pirqL) { @@ -261,6 +297,16 @@ __inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) spin_unlock_bh(plock); } +__inline static void enter_critical_bh(_lock *plock) +{ + spin_lock_bh(plock); +} + +__inline static void exit_critical_bh(_lock *plock) +{ + spin_unlock_bh(plock); +} + __inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) { int ret = 0; @@ -274,6 +320,17 @@ __inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) } +__inline static int _enter_critical_mutex_lock(_mutex *pmutex, _irqL *pirqL) +{ + int ret = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + mutex_lock(pmutex); +#else + down(pmutex); +#endif + return ret; +} + __inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) @@ -283,25 +340,48 @@ __inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) #endif } -__inline static void rtw_list_delete(_list *plist) +__inline static _list *get_list_head(_queue *queue) { - list_del_init(plist); + return &(queue->queue); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) +static inline void timer_hdl(struct timer_list *in_timer) +#else +static inline void timer_hdl(unsigned long cntx) +#endif +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + _timer *ptimer = from_timer(ptimer, in_timer, timer); +#else + _timer *ptimer = (_timer *)cntx; +#endif + ptimer->function(ptimer->arg); } -__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc) +__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx) { + ptimer->function = pfunc; + ptimer->arg = cntx; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + timer_setup(&ptimer->timer, timer_hdl, 0); +#else /* setup_timer(ptimer, pfunc,(u32)cntx); */ - timer_setup(ptimer, pfunc, 0); + ptimer->timer.function = timer_hdl; + ptimer->timer.data = (unsigned long)ptimer; + init_timer(&ptimer->timer); +#endif } __inline static void _set_timer(_timer *ptimer, u32 delay_time) { - mod_timer(ptimer , (jiffies + (delay_time * HZ / 1000))); + mod_timer(&ptimer->timer , (jiffies + (delay_time * HZ / 1000))); } __inline static void _cancel_timer(_timer *ptimer, u8 *bcancelled) { - *bcancelled = del_timer_sync(ptimer) == 1 ? 1 : 0; + *bcancelled = del_timer_sync(&ptimer->timer) == 1 ? 1 : 0; } static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx) @@ -389,11 +469,23 @@ static inline void rtw_netif_stop_queue(struct net_device *pnetdev) netif_stop_queue(pnetdev); #endif } -static inline void rtw_netif_carrier_on(struct net_device *pnetdev) +static inline void rtw_netif_device_attach(struct net_device *pnetdev) { netif_device_attach(pnetdev); +} +static inline void rtw_netif_device_detach(struct net_device *pnetdev) +{ + netif_device_detach(pnetdev); +} +static inline void rtw_netif_carrier_on(struct net_device *pnetdev) +{ netif_carrier_on(pnetdev); } +static inline void rtw_netif_carrier_off(struct net_device *pnetdev) +{ + netif_carrier_off(pnetdev); +} + static inline int rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2) { int len = 0; diff --git a/include/osdep_service_xp.h b/include/osdep_service_xp.h index e0c3e70..57e6f31 100644 --- a/include/osdep_service_xp.h +++ b/include/osdep_service_xp.h @@ -1,138 +1,133 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#ifndef __OSDEP_LINUX_SERVICE_H_ -#define __OSDEP_LINUX_SERVICE_H_ - - #include - #include - #include - #include - -#ifdef CONFIG_USB_HCI - #include - #include - #include -#endif - - typedef KSEMAPHORE _sema; - typedef LIST_ENTRY _list; - typedef NDIS_STATUS _OS_STATUS; - - - typedef NDIS_SPIN_LOCK _lock; - - typedef KMUTEX _mutex; - - typedef KIRQL _irqL; - - // USB_PIPE for WINCE , but handle can be use just integer under windows - typedef NDIS_HANDLE _nic_hdl; - - struct timer_list { +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __OSDEP_LINUX_SERVICE_H_ +#define __OSDEP_LINUX_SERVICE_H_ + + #include + #include + #include + #include + +#ifdef CONFIG_USB_HCI + #include + #include + #include +#endif + + typedef KSEMAPHORE _sema; + typedef LIST_ENTRY _list; + typedef NDIS_STATUS _OS_STATUS; + + + typedef NDIS_SPIN_LOCK _lock; + + typedef KMUTEX _mutex; + + typedef KIRQL _irqL; + + // USB_PIPE for WINCE , but handle can be use just integer under windows + typedef NDIS_HANDLE _nic_hdl; + + struct rtw_timer_list { NDIS_MINIPORT_TIMER ndis_timer; void (*function)(void *); void *arg; }; - - struct __queue { - LIST_ENTRY queue; - _lock lock; - }; - - typedef NDIS_PACKET _pkt; - typedef NDIS_BUFFER _buffer; - typedef struct __queue _queue; - - typedef PKTHREAD _thread_hdl_; - typedef void thread_return; - typedef void* thread_context; - - typedef NDIS_WORK_ITEM _workitem; - - - #define HZ 10000000 - #define SEMA_UPBND (0x7FFFFFFF) //8192 - -__inline static _list *get_next(_list *list) -{ - return list->Flink; -} - -__inline static _list *get_list_head(_queue *queue) -{ - return (&(queue->queue)); -} - - -#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) - - -__inline static _enter_critical(_lock *plock, _irqL *pirqL) -{ - NdisAcquireSpinLock(plock); -} - -__inline static _exit_critical(_lock *plock, _irqL *pirqL) -{ - NdisReleaseSpinLock(plock); -} - - -__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) -{ - NdisDprAcquireSpinLock(plock); -} - -__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) -{ - NdisDprReleaseSpinLock(plock); -} - -__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) -{ - NdisDprAcquireSpinLock(plock); -} - -__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) -{ - NdisDprReleaseSpinLock(plock); -} - -__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL); -} - - -__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) -{ - KeReleaseMutex(pmutex, FALSE); -} - - -__inline static void rtw_list_delete(_list *plist) -{ - RemoveEntryList(plist); - InitializeListHead(plist); -} - + + struct __queue { + LIST_ENTRY queue; + _lock lock; + }; + + typedef NDIS_PACKET _pkt; + typedef NDIS_BUFFER _buffer; + typedef struct __queue _queue; + + typedef PKTHREAD _thread_hdl_; + typedef void thread_return; + typedef void* thread_context; + + typedef NDIS_WORK_ITEM _workitem; + + + #define HZ 10000000 + #define SEMA_UPBND (0x7FFFFFFF) //8192 + +__inline static _list *get_next(_list *list) +{ + return list->Flink; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + + +#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) + + +__inline static _enter_critical(_lock *plock, _irqL *pirqL) +{ + NdisAcquireSpinLock(plock); +} + +__inline static _exit_critical(_lock *plock, _irqL *pirqL) +{ + NdisReleaseSpinLock(plock); +} + + +__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + +__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + +__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL); +} + + +__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + KeReleaseMutex(pmutex, FALSE); +} + + +__inline static void rtw_list_delete(_list *plist) +{ + RemoveEntryList(plist); + InitializeListHead(plist); +} + static inline void timer_hdl( IN PVOID SystemSpecific1, IN PVOID FunctionContext, @@ -160,56 +155,56 @@ static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled) { NdisMCancelTimer(ptimer, bcancelled); } - -__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) -{ - - NdisInitializeWorkItem(pwork, pfunc, cntx); -} - -__inline static void _set_workitem(_workitem *pwork) -{ - NdisScheduleWorkItem(pwork); -} - - -#define ATOMIC_INIT(i) { (i) } - -// -// Global Mutex: can only be used at PASSIVE level. -// - -#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ - { \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ - NdisMSleep(10000); \ - } \ -} - -#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ -{ \ - NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ -} - -// limitation of path length -#define PATH_LENGTH_MAX MAX_PATH - -//Atomic integer operations -#define ATOMIC_T LONG - - -#define NDEV_FMT "%s" -#define NDEV_ARG(ndev) "" -#define ADPT_FMT "%s" -#define ADPT_ARG(adapter) "" -#define FUNC_NDEV_FMT "%s" -#define FUNC_NDEV_ARG(ndev) __func__ -#define FUNC_ADPT_FMT "%s" -#define FUNC_ADPT_ARG(adapter) __func__ - -#define STRUCT_PACKED - -#endif - + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + + NdisInitializeWorkItem(pwork, pfunc, cntx); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + NdisScheduleWorkItem(pwork); +} + + +#define ATOMIC_INIT(i) { (i) } + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ + { \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ + NdisMSleep(10000); \ + } \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ +} + +// limitation of path length +#define PATH_LENGTH_MAX MAX_PATH + +//Atomic integer operations +#define ATOMIC_T LONG + + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + +#endif + diff --git a/include/pci_hal.h b/include/pci_hal.h index 8aa1a56..15e4a79 100644 --- a/include/pci_hal.h +++ b/include/pci_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PCI_HAL_H__ #define __PCI_HAL_H__ @@ -32,6 +27,10 @@ void rtl8192ee_set_hal_ops(_adapter *padapter); #endif +#if defined(CONFIG_RTL8192F) + void rtl8192fe_set_hal_ops(_adapter *padapter); +#endif + #ifdef CONFIG_RTL8723B void rtl8723be_set_hal_ops(_adapter *padapter); #endif diff --git a/include/pci_ops.h b/include/pci_ops.h index dda0f36..cc341b6 100644 --- a/include/pci_ops.h +++ b/include/pci_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PCI_OPS_H_ #define __PCI_OPS_H_ @@ -53,6 +48,17 @@ void rtl8192ee_set_intf_ops(struct _io_ops *pops); #endif +#ifdef CONFIG_RTL8192F + u32 rtl8192fe_init_desc_ring(_adapter *padapter); + u32 rtl8192fe_free_desc_ring(_adapter *padapter); + void rtl8192fe_reset_desc_ring(_adapter *padapter); + int rtl8192fe_interrupt(PADAPTER Adapter); + void rtl8192fe_recv_tasklet(void *priv); + void rtl8192fe_prepare_bcn_tasklet(void *priv); + void rtl8192fe_set_intf_ops(struct _io_ops *pops); + u8 check_tx_desc_resource(_adapter *padapter, int prio); +#endif + #ifdef CONFIG_RTL8723B u32 rtl8723be_init_desc_ring(_adapter *padapter); u32 rtl8723be_free_desc_ring(_adapter *padapter); diff --git a/include/pci_osintf.h b/include/pci_osintf.h index 93392cb..c6a0fdd 100644 --- a/include/pci_osintf.h +++ b/include/pci_osintf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PCI_OSINTF_H #define __PCI_OSINTF_H @@ -45,6 +40,9 @@ void rtw_pci_enable_aspm(_adapter *padapter); void PlatformClearPciPMEStatus(PADAPTER Adapter); void rtw_pci_aspm_config(_adapter *padapter); void rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble); +#ifdef CONFIG_PCI_DYNAMIC_ASPM +void rtw_pci_aspm_config_dynamic_l1_ilde_time(_adapter *padapter); +#endif #ifdef CONFIG_64BIT_DMA u8 PlatformEnableDMA64(PADAPTER Adapter); #endif diff --git a/include/recv_osdep.h b/include/recv_osdep.h index fb3c7e3..8c569b6 100644 --- a/include/recv_osdep.h +++ b/include/recv_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RECV_OSDEP_H_ #define __RECV_OSDEP_H_ @@ -26,12 +21,15 @@ extern void _rtw_free_recv_priv(struct recv_priv *precvpriv); extern s32 rtw_recv_entry(union recv_frame *precv_frame); +void rtw_rframe_set_os_pkt(union recv_frame *rframe); extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame); extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt); extern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame); +#ifdef CONFIG_HOSTAPD_MLME extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame); +#endif struct sta_info; extern void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup); @@ -50,8 +48,8 @@ void rtw_os_free_recvframe(union recv_frame *precvframe); int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf); int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf); -_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 *pdata); -void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attrib *pattrib); +_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa, u8 *msdu ,u16 msdu_len); +void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe); void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf); @@ -60,6 +58,9 @@ void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf); #include /* struct napi_struct */ int rtw_recv_napi_poll(struct napi_struct *, int budget); +#ifdef CONFIG_RTW_NAPI_DYNAMIC +void dynamic_napi_th_chk (_adapter *adapter); +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ #endif /* CONFIG_RTW_NAPI */ #endif /* PLATFORM_LINUX */ diff --git a/include/rtl8188e_cmd.h b/include/rtl8188e_cmd.h index a3d6e01..aba0bec 100644 --- a/include/rtl8188e_cmd.h +++ b/include/rtl8188e_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_CMD_H__ #define __RTL8188E_CMD_H__ @@ -140,8 +135,6 @@ typedef struct _RSVDPAGE_LOC_88E { /* host message to firmware cmd */ void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); -u8 rtl8188e_set_rssi_cmd(PADAPTER padapter, u8 *param); -u8 rtl8188e_set_raid_cmd(_adapter *padapter, u32 bitmap, u8 *arg, u8 bw); s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); /* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */ u8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan); @@ -151,13 +144,6 @@ u8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan); void rtl8188e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); - -#ifdef CONFIG_TSF_RESET_OFFLOAD - /* u8 rtl8188e_reset_tsf(_adapter *padapter, u8 reset_port); */ - int reset_tsf(PADAPTER Adapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - /* #define H2C_8188E_RSVDPAGE_LOC_LEN 5 */ /* #define H2C_8188E_AOAC_RSVDPAGE_LOC_LEN 7 */ diff --git a/include/rtl8188e_dm.h b/include/rtl8188e_dm.h index a4c2527..501d3a9 100644 --- a/include/rtl8188e_dm.h +++ b/include/rtl8188e_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_DM_H__ #define __RTL8188E_DM_H__ diff --git a/include/rtl8188e_hal.h b/include/rtl8188e_hal.h index 824836d..a344e49 100644 --- a/include/rtl8188e_hal.h +++ b/include/rtl8188e_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_HAL_H__ #define __RTL8188E_HAL_H__ @@ -115,7 +110,11 @@ typedef struct _RT_8188E_FIRMWARE_HDR { /* #define MAX_RX_DMA_BUFFER_SIZE_88E 0x2400 */ /* 9k for 88E nornal chip , */ /* MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */ -#define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2800:0x4000) +#ifdef CONFIG_USB_HCI + #define RX_DMA_SIZE_88E(__Adapter) 0x2800 +#else + #define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2800:0x4000) +#endif #ifdef CONFIG_WOWLAN #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ @@ -129,16 +128,18 @@ typedef struct _RT_8188E_FIRMWARE_HDR { #define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */ +#define PAGE_SIZE_TX_88E PAGE_SIZE_128 /* Note: We will divide number of page equally for each queue other than public queue! * 22k = 22528 bytes = 176 pages (@page = 128 bytes) - * must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) - * 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS null-data */ + * BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_88E + * 1 ps-poll / 1 null-data /1 prob_rsp /1 QOS null-data = 4 pages */ -#define BCNQ_PAGE_NUM_88E 0x09 +#define BCNQ_PAGE_NUM_88E (MAX_BEACON_LEN / PAGE_SIZE_TX_88E + 4) /*0x09*/ /* For WoWLan , more reserved page */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_88E 0x00 + /* 1 ArpRsp + 2 NbrAdv + 2 NDPInfo + 1 RCI + 1 AOAC = 7 pages */ + #define WOWLAN_PAGE_NUM_88E 0x07 #else #define WOWLAN_PAGE_NUM_88E 0x00 #endif @@ -148,7 +149,11 @@ Tx FIFO Size : previous CUT:22K /I_CUT after:32KB Tx page Size : 128B Total page numbers : 176(0xB0) / 256(0x100) */ -#define TOTAL_PAGE_NUMBER_88E(_Adapter) ((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - 1)/* must reserved 1 page for dma issue */ +#ifdef CONFIG_USB_HCI + #define TOTAL_PAGE_NUMBER_88E(_Adapter) (0xB0 - 1) +#else + #define TOTAL_PAGE_NUMBER_88E(_Adapter) ((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - 1)/* must reserved 1 page for dma issue */ +#endif #define TX_TOTAL_PAGE_NUMBER_88E(_Adapter) (TOTAL_PAGE_NUMBER_88E(_Adapter) - BCNQ_PAGE_NUM_88E - WOWLAN_PAGE_NUM_88E) #define TX_PAGE_BOUNDARY_88E(_Adapter) (TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1) /* beacon header start address */ @@ -280,14 +285,13 @@ BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter); void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); #endif /*CONFIG_RF_POWER_TRIM*/ -void rtl8188e_init_default_value(_adapter *adapter); + +void InitBeaconParameters_8188e(_adapter *adapter); +void SetBeaconRelatedRegisters8188E(PADAPTER padapter); void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8188e(_adapter *adapter); -/* register */ -void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits); - void rtl8188e_start_thread(_adapter *padapter); void rtl8188e_stop_thread(_adapter *padapter); @@ -297,7 +301,7 @@ void rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER *Adapter, int data_len); #endif/* CONFIG_IOL_EFUSE_PATCH */ void _InitTransferPageSize(PADAPTER padapter); -void SetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val); u8 diff --git a/include/rtl8188e_led.h b/include/rtl8188e_led.h index 8d0feee..ef05467 100644 --- a/include/rtl8188e_led.h +++ b/include/rtl8188e_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,15 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_LED_H__ #define __RTL8188E_LED_H__ +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. @@ -38,3 +34,4 @@ #endif #endif +#endif /*CONFIG_RTW_SW_LED*/ diff --git a/include/rtl8188e_recv.h b/include/rtl8188e_recv.h index 2f574a8..92425a8 100644 --- a/include/rtl8188e_recv.h +++ b/include/rtl8188e_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_RECV_H__ #define __RTL8188E_RECV_H__ @@ -34,11 +29,7 @@ /* #define MAX_RECVBUF_SZ (32768) */ /* 32k */ /* #define MAX_RECVBUF_SZ (16384) */ /* 16K */ /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ - #ifdef CONFIG_PLATFORM_MSTAR - #define MAX_RECVBUF_SZ (8192) /* 8K */ - #else - #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ - #endif + #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ #else #define MAX_RECVBUF_SZ (4000) /* about 4K */ diff --git a/include/rtl8188e_rf.h b/include/rtl8188e_rf.h index 6588126..f5c5fbd 100644 --- a/include/rtl8188e_rf.h +++ b/include/rtl8188e_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_RF_H__ #define __RTL8188E_RF_H__ @@ -27,6 +22,6 @@ void rtl8188e_RF_ChangeTxPath(IN PADAPTER Adapter, IN u16 DataRate); void rtl8188e_PHY_RF6052SetBandwidth( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); #endif/* __RTL8188E_RF_H__ */ diff --git a/include/rtl8188e_spec.h b/include/rtl8188e_spec.h index 64d4fb3..802659a 100644 --- a/include/rtl8188e_spec.h +++ b/include/rtl8188e_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_SPEC_H__ #define __RTL8188E_SPEC_H__ diff --git a/include/rtl8188e_sreset.h b/include/rtl8188e_sreset.h index d0214ac..f4ec2d8 100644 --- a/include/rtl8188e_sreset.h +++ b/include/rtl8188e_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8188E_SRESET_H_ #define _RTL8188E_SRESET_H_ diff --git a/include/rtl8188e_xmit.h b/include/rtl8188e_xmit.h index c04a66c..f625576 100644 --- a/include/rtl8188e_xmit.h +++ b/include/rtl8188e_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188E_XMIT_H__ #define __RTL8188E_XMIT_H__ diff --git a/include/rtl8188f_cmd.h b/include/rtl8188f_cmd.h index 953d8c4..5e1bc9a 100644 --- a/include/rtl8188f_cmd.h +++ b/include/rtl8188f_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_CMD_H__ #define __RTL8188F_CMD_H__ @@ -118,7 +113,6 @@ enum h2c_cmd_8188F { #define SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) #define SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8188F_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) #define GET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) @@ -183,11 +177,9 @@ enum h2c_cmd_8188F { /* host message to firmware cmd */ void rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); -void rtl8188f_set_rssi_cmd(PADAPTER padapter, u8 *param); void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8188f_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); void rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST @@ -197,8 +189,6 @@ void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus); void rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); - #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW void rtl8188f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); @@ -211,9 +201,6 @@ void rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter); void rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); -#ifdef CONFIG_TSF_RESET_OFFLOAD -u8 rtl8188f_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ s32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan); #endif diff --git a/include/rtl8188f_dm.h b/include/rtl8188f_dm.h index 78aeab0..342ade9 100644 --- a/include/rtl8188f_dm.h +++ b/include/rtl8188f_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_DM_H__ #define __RTL8188F_DM_H__ /* ************************************************************ @@ -40,8 +35,5 @@ void rtl8188f_deinit_dm_priv(PADAPTER padapter); void rtl8188f_InitHalDm(PADAPTER padapter); void rtl8188f_HalDmWatchDog(PADAPTER padapter); -void rtl8188f_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8188f_hal_dm_in_lps(PADAPTER padapter); - #endif diff --git a/include/rtl8188f_hal.h b/include/rtl8188f_hal.h index 874a3b2..9d5da6a 100644 --- a/include/rtl8188f_hal.h +++ b/include/rtl8188f_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_HAL_H__ #define __RTL8188F_HAL_H__ @@ -109,23 +104,17 @@ typedef struct _RT_8188F_FIRMWARE_HDR { /* Note: We will divide number of page equally for each queue other than public queue! */ /* For General Reserved Page Number(Beacon Queue is reserved page) - * Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */ -#define BCNQ_PAGE_NUM_8188F 0x08 -#ifdef CONFIG_CONCURRENT_MODE - #define BCNQ1_PAGE_NUM_8188F 0x08 /* 0x04 */ -#else - #define BCNQ1_PAGE_NUM_8188F 0x00 -#endif + * BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8188F, + * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1, CTS-2-SELF / LTE QoS Null */ -#ifdef CONFIG_PNO_SUPPORT -#undef BCNQ1_PAGE_NUM_8188F -#define BCNQ1_PAGE_NUM_8188F 0x00 /* 0x04 */ -#endif +#define BCNQ_PAGE_NUM_8188F (MAX_BEACON_LEN / PAGE_SIZE_TX_8188F + 6) /*0x08*/ /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt:1 ,PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt:1 ,PNO: 6 + * NS offload:2 NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8188F 0x08 + #define WOWLAN_PAGE_NUM_8188F 0x0b #else #define WOWLAN_PAGE_NUM_8188F 0x00 #endif @@ -139,7 +128,7 @@ typedef struct _RT_8188F_FIRMWARE_HDR { #define AP_WOWLAN_PAGE_NUM_8188F 0x02 #endif -#define TX_TOTAL_PAGE_NUMBER_8188F (0xFF - BCNQ_PAGE_NUM_8188F - BCNQ1_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F) +#define TX_TOTAL_PAGE_NUMBER_8188F (0xFF - BCNQ_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F) #define TX_PAGE_BOUNDARY_8188F (TX_TOTAL_PAGE_NUMBER_8188F + 1) #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F TX_TOTAL_PAGE_NUMBER_8188F @@ -226,7 +215,7 @@ void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel); void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8188f(_adapter *adapter); -void SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); diff --git a/include/rtl8188f_led.h b/include/rtl8188f_led.h index 232ede5..ef5d1a7 100644 --- a/include/rtl8188f_led.h +++ b/include/rtl8188f_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,14 +11,10 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_LED_H__ #define __RTL8188F_LED_H__ +#ifdef CONFIG_RTW_SW_LED #include #include @@ -46,3 +42,4 @@ void rtl8188fe_DeInitSwLeds(PADAPTER padapter); #endif #endif +#endif/*CONFIG_RTW_SW_LED*/ diff --git a/include/rtl8188f_recv.h b/include/rtl8188f_recv.h index 8652fd6..6366b81 100644 --- a/include/rtl8188f_recv.h +++ b/include/rtl8188f_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_RECV_H__ #define __RTL8188F_RECV_H__ diff --git a/include/rtl8188f_rf.h b/include/rtl8188f_rf.h index 185d2d0..bf4f591 100644 --- a/include/rtl8188f_rf.h +++ b/include/rtl8188f_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_RF_H__ #define __RTL8188F_RF_H__ @@ -25,6 +20,6 @@ int PHY_RF6052_Config8188F(IN PADAPTER Adapter); VOID PHY_RF6052SetBandwidth8188F( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); #endif diff --git a/include/rtl8188f_spec.h b/include/rtl8188f_spec.h index 7282cc1..d947ba8 100644 --- a/include/rtl8188f_spec.h +++ b/include/rtl8188f_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_SPEC_H__ #define __RTL8188F_SPEC_H__ @@ -154,18 +150,6 @@ #define SDIO_REG_HCPWM1_8188F 0x0038 -/* indirect access */ -#define SDIO_REG_INDIRECT_REG_CFG_8188F 0x40 -#define SET_INDIRECT_REG_ADDR(_cmd, _addr) SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr)) -#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0) -#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1) -#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2) -#define SET_INDIRECT_REG_WRITE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1) -#define SET_INDIRECT_REG_READ(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1) -#define GET_INDIRECT_REG_RDY(_cmd) LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1) - -#define SDIO_REG_INDIRECT_REG_DATA_8188F 0x44 - /* **************************************************************************** * 8188 Regsiter Bit and Content definition * **************************************************************************** */ diff --git a/include/rtl8188f_sreset.h b/include/rtl8188f_sreset.h index ef5b0ff..fe56567 100644 --- a/include/rtl8188f_sreset.h +++ b/include/rtl8188f_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8188F_SRESET_H_ #define _RTL8188F_SRESET_H_ diff --git a/include/rtl8188f_xmit.h b/include/rtl8188f_xmit.h index be88ca4..40493ce 100644 --- a/include/rtl8188f_xmit.h +++ b/include/rtl8188f_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8188F_XMIT_H__ #define __RTL8188F_XMIT_H__ @@ -189,13 +184,15 @@ #define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) /* Dword 7 */ -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#ifdef CONFIG_PCI_HCI #define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#else +#endif + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) #define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) #endif #define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) -#if (DEV_BUS_TYPE == RT_SDIO_INTERFACE) +#ifdef CONFIG_SDIO_HCI #define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) #endif @@ -306,9 +303,10 @@ thread_return rtl8188fs_xmit_thread(thread_context context); #endif #ifdef CONFIG_USB_HCI +#ifdef CONFIG_XMIT_THREAD_MODE s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter); #define hal_xmit_handler rtl8188fu_xmit_buf_handler - +#endif s32 rtl8188fu_init_xmit_priv(PADAPTER padapter); void rtl8188fu_free_xmit_priv(PADAPTER padapter); diff --git a/include/rtl8192e_cmd.h b/include/rtl8192e_cmd.h index 78d476b..5efdf99 100644 --- a/include/rtl8192e_cmd.h +++ b/include/rtl8192e_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_CMD_H__ #define __RTL8192E_CMD_H__ @@ -106,7 +101,6 @@ typedef struct _RSVDPAGE_LOC_92E { #define SET_8192E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) #define SET_8192E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8192E_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) #define GET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) /* _P2P_PS_OFFLOAD */ @@ -121,8 +115,6 @@ typedef struct _RSVDPAGE_LOC_92E { /* host message to firmware cmd */ void rtl8192e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8192e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); -u8 rtl8192e_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8192e_set_raid_cmd(PADAPTER padapter, u32 bitmap, u8 *arg, u8 bw); s32 FillH2CCmd_8192E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8192E(_adapter *padapter, bool wowlan); /* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */ @@ -134,18 +126,12 @@ s32 c2h_handler_8192e(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); void rtl8192e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); - #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW void rtl8192e_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); #endif #endif -#ifdef CONFIG_TSF_RESET_OFFLOAD - int reset_tsf(PADAPTER Adapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - /* / TX Feedback Content */ #define USEC_UNIT_FOR_8192E_C2H_TX_RPT_QUEUE_TIME 256 diff --git a/include/rtl8192e_dm.h b/include/rtl8192e_dm.h index ff1b341..5f6ee4b 100644 --- a/include/rtl8192e_dm.h +++ b/include/rtl8192e_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_DM_H__ #define __RTL8192E_DM_H__ diff --git a/include/rtl8192e_hal.h b/include/rtl8192e_hal.h index dc64a2b..716995f 100644 --- a/include/rtl8192e_hal.h +++ b/include/rtl8192e_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_HAL_H__ #define __RTL8192E_HAL_H__ @@ -126,14 +121,21 @@ typedef struct _RT_FIRMWARE_8192E { #endif #define MAX_RX_DMA_BUFFER_SIZE_8192E (RX_DMA_SIZE_8192E-RX_DMA_RESERVED_SIZE_8192E) /*RX 16K*/ + +#define PAGE_SIZE_TX_92E PAGE_SIZE_256 + /* For General Reserved Page Number(Beacon Queue is reserved page) * if (CONFIG_2BCN_EN) Beacon:4, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1 - * Beacon:2, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1 */ -#define RSVD_PAGE_NUM_8192E 0x08 + * Beacon: MAX_BEACON_LEN / PAGE_SIZE_TX_92E + * PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1,CTS-2-SELF / LTE QoS Null*/ + +#define RSVD_PAGE_NUM_8192E (MAX_BEACON_LEN / PAGE_SIZE_TX_92E + 6) /*0x08*/ /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6 + * NS offload: 2 NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8192E 0x08 + #define WOWLAN_PAGE_NUM_8192E 0x0b #else #define WOWLAN_PAGE_NUM_8192E 0x00 #endif @@ -157,7 +159,6 @@ Total page numbers : 256(0x100) #define TX_PAGE_BOUNDARY_8192E (TX_TOTAL_PAGE_NUMBER_8192E) /* beacon header start address */ -#define PAGE_SIZE_TX_92E PAGE_SIZE_256 #define RSVD_PKT_LEN_92E (TOTAL_RSVD_PAGE_NUMBER_8192E * PAGE_SIZE_TX_92E) #define TX_PAGE_LOAD_FW_BOUNDARY_8192E 0x47 /* 0xA5 */ @@ -276,7 +277,6 @@ void _InitID_8192E(IN PADAPTER Adapter); VOID _InitNetworkType_8192E(IN PADAPTER Adapter); VOID _InitWMACSetting_8192E(IN PADAPTER Adapter); VOID _InitAdaptiveCtrl_8192E(IN PADAPTER Adapter); -VOID _InitRateFallback_8192E(IN PADAPTER Adapter); VOID _InitEDCA_8192E(IN PADAPTER Adapter); VOID _InitRetryFunction_8192E(IN PADAPTER Adapter); VOID _BBTurnOnBlock_8192E(IN PADAPTER Adapter); @@ -290,7 +290,7 @@ VOID hal_ReadRFType_8192E(PADAPTER Adapter); /* RTL8192E-MAC Setting ***********************************************************/ -void SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val); +u8 SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val); void GetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val); u8 SetHalDefVar8192E( @@ -308,15 +308,13 @@ GetHalDefVar8192E( void rtl8192e_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8192e(_adapter *adapter); void rtl8192e_init_default_value(_adapter *padapter); -/* register */ -void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits); void rtl8192e_start_thread(_adapter *padapter); void rtl8192e_stop_thread(_adapter *padapter); #ifdef CONFIG_PCI_HCI BOOLEAN InterruptRecognized8192EE(PADAPTER Adapter); - u16 get_txdesc_buf_addr(u16 ff_hwaddr); + u16 get_txbd_rw_reg(u16 ff_hwaddr); #endif #ifdef CONFIG_SDIO_HCI diff --git a/include/rtl8192e_led.h b/include/rtl8192e_led.h index d79bd91..3d795c4 100644 --- a/include/rtl8192e_led.h +++ b/include/rtl8192e_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,16 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_LED_H__ #define __RTL8192E_LED_H__ - +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -38,3 +33,4 @@ #endif #endif +#endif/*CONFIG_RTW_SW_LED*/ diff --git a/include/rtl8192e_recv.h b/include/rtl8192e_recv.h index 34f081c..6ccb8e9 100644 --- a/include/rtl8192e_recv.h +++ b/include/rtl8192e_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_RECV_H__ #define __RTL8192E_RECV_H__ @@ -40,6 +35,10 @@ /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ /* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */ /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ + #ifdef CONFIG_PLATFORM_NOVATEK_NT72668 + #undef MAX_RECVBUF_SZ + #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ + #endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */ #endif #endif #endif /* !MAX_RECVBUF_SZ */ @@ -144,6 +143,12 @@ #define GET_RX_STATUS_DESC_UNICAST_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) #define GET_RX_STATUS_DESC_MAGIC_WAKE_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) +/* DWORD 6 */ +#define GET_RX_STATUS_DESC_SPLCP_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1) +#define GET_RX_STATUS_DESC_LDPC_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1) +#define GET_RX_STATUS_DESC_STBC_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1) +#define GET_RX_STATUS_DESC_BW_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2) + /* DWORD 5 */ #define GET_RX_STATUS_DESC_TSFL_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) @@ -155,6 +160,7 @@ #ifdef CONFIG_SDIO_HCI s32 rtl8192es_init_recv_priv(PADAPTER padapter); void rtl8192es_free_recv_priv(PADAPTER padapter); + s32 rtl8192es_recv_hdl(_adapter *padapter); #endif #ifdef CONFIG_USB_HCI diff --git a/include/rtl8192e_rf.h b/include/rtl8192e_rf.h index cd344a4..f15e070 100644 --- a/include/rtl8192e_rf.h +++ b/include/rtl8192e_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,19 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_RF_H__ #define __RTL8192E_RF_H__ VOID PHY_RF6052SetBandwidth8192E( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); int diff --git a/include/rtl8192e_spec.h b/include/rtl8192e_spec.h index 8a5c5f8..c9b2b41 100644 --- a/include/rtl8192e_spec.h +++ b/include/rtl8192e_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_SPEC_H__ #define __RTL8192E_SPEC_H__ diff --git a/include/rtl8192e_sreset.h b/include/rtl8192e_sreset.h index 7430d9a..78109ae 100644 --- a/include/rtl8192e_sreset.h +++ b/include/rtl8192e_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL88812A_SRESET_H_ #define _RTL8812A_SRESET_H_ diff --git a/include/rtl8192e_xmit.h b/include/rtl8192e_xmit.h index 23deb8d..559eefe 100644 --- a/include/rtl8192e_xmit.h +++ b/include/rtl8192e_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2012 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8192E_XMIT_H__ #define __RTL8192E_XMIT_H__ @@ -322,9 +317,11 @@ typedef struct txdescriptor_8192e { #define SET_TX_DESC_ANTSEL_D_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) /* Dword 7 */ -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#ifdef CONFIG_PCI_HCI #define SET_TX_DESC_TX_BUFFER_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#else +#endif + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) #define SET_TX_DESC_TX_DESC_CHECKSUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) #endif #define SET_TX_DESC_USB_TXAGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) @@ -445,6 +442,8 @@ void fill_txdesc_vcs(struct pkt_attrib *pattrib, u8 *ptxdesc); #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); + void fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc); void rtl8192e_fixed_rate(_adapter *padapter, u8 *ptxdesc); diff --git a/include/rtl8192f_cmd.h b/include/rtl8192f_cmd.h new file mode 100644 index 0000000..fedfd7f --- /dev/null +++ b/include/rtl8192f_cmd.h @@ -0,0 +1,194 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8192F_CMD_H__ +#define __RTL8192F_CMD_H__ + +/* --------------------------------------------------------------------------------------------------------- + * ---------------------------------- H2C CMD DEFINITION ------------------------------------------------ + * --------------------------------------------------------------------------------------------------------- */ + +enum h2c_cmd_8192F { + /* Common Class: 000 */ + H2C_8192F_RSVD_PAGE = 0x00, + H2C_8192F_MEDIA_STATUS_RPT = 0x01, + H2C_8192F_SCAN_ENABLE = 0x02, + H2C_8192F_KEEP_ALIVE = 0x03, + H2C_8192F_DISCON_DECISION = 0x04, + H2C_8192F_PSD_OFFLOAD = 0x05, + H2C_8192F_AP_OFFLOAD = 0x08, + H2C_8192F_BCN_RSVDPAGE = 0x09, + H2C_8192F_PROBERSP_RSVDPAGE = 0x0A, + H2C_8192F_FCS_RSVDPAGE = 0x10, + H2C_8192F_FCS_INFO = 0x11, + H2C_8192F_AP_WOW_GPIO_CTRL = 0x13, + + /* PoweSave Class: 001 */ + H2C_8192F_SET_PWR_MODE = 0x20, + H2C_8192F_PS_TUNING_PARA = 0x21, + H2C_8192F_PS_TUNING_PARA2 = 0x22, + H2C_8192F_P2P_LPS_PARAM = 0x23, + H2C_8192F_P2P_PS_OFFLOAD = 0x24, + H2C_8192F_PS_SCAN_ENABLE = 0x25, + H2C_8192F_SAP_PS_ = 0x26, + H2C_8192F_INACTIVE_PS_ = 0x27,/* Inactive_PS */ + H2C_8192F_FWLPS_IN_IPS_ = 0x28, + + /* Dynamic Mechanism Class: 010 */ + H2C_8192F_MACID_CFG = 0x40, + H2C_8192F_TXBF = 0x41, + H2C_8192F_RSSI_SETTING = 0x42, + H2C_8192F_AP_REQ_TXRPT = 0x43, + H2C_8192F_INIT_RATE_COLLECT = 0x44, + H2C_8192F_RA_PARA_ADJUST = 0x46, + + /* BT Class: 011 */ + H2C_8192F_B_TYPE_TDMA = 0x60, + H2C_8192F_BT_INFO = 0x61, + H2C_8192F_FORCE_BT_TXPWR = 0x62, + H2C_8192F_BT_IGNORE_WLANACT = 0x63, + H2C_8192F_DAC_SWING_VALUE = 0x64, + H2C_8192F_ANT_SEL_RSV = 0x65, + H2C_8192F_WL_OPMODE = 0x66, + H2C_8192F_BT_MP_OPER = 0x67, + H2C_8192F_BT_CONTROL = 0x68, + H2C_8192F_BT_WIFI_CTRL = 0x69, + H2C_8192F_BT_FW_PATCH = 0x6A, + H2C_8192F_BT_WLAN_CALIBRATION = 0x6D, + + /* WOWLAN Class: 100 */ + H2C_8192F_WOWLAN = 0x80, + H2C_8192F_REMOTE_WAKE_CTRL = 0x81, + H2C_8192F_AOAC_GLOBAL_INFO = 0x82, + H2C_8192F_AOAC_RSVD_PAGE = 0x83, + H2C_8192F_AOAC_RSVD_PAGE2 = 0x84, + H2C_8192F_D0_SCAN_OFFLOAD_CTRL = 0x85, + H2C_8192F_D0_SCAN_OFFLOAD_INFO = 0x86, + H2C_8192F_CHNL_SWITCH_OFFLOAD = 0x87, + H2C_8192F_P2P_OFFLOAD_RSVD_PAGE = 0x8A, + H2C_8192F_P2P_OFFLOAD = 0x8B, + + H2C_8192F_RESET_TSF = 0xC0, + H2C_8192F_MAXID, +}; + +/* --------------------------------------------------------------------------------------------------------- + * ---------------------------------- H2C CMD CONTENT -------------------------------------------------- + * --------------------------------------------------------------------------------------------------------- + * _RSVDPAGE_LOC_CMD_0x00 */ +#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8192F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8192F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8192F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) + +/*_MEDIA_STATUS_RPT_PARM_CMD_0x01*/ +#define SET_8192F_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) +/* _PWR_MOD_CMD_0x20 */ +#define SET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8192F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) +#define SET_8192F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) +#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8192F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) +#define SET_8192F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) + +#define GET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) + +/* _PS_TUNE_PARAM_CMD_0x21 */ +#define SET_8192F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8192F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value) +#define SET_8192F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value) +#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) + +/* _MACID_CFG_CMD_0x40 */ +#define SET_8192F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8192F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value) +#define SET_8192F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value) +#define SET_8192F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value) +#define SET_8192F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value) +#define SET_8192F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value) +#define SET_8192F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value) +#define SET_8192F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value) +#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) +#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) +#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value) +#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value) + +/* _RSSI_SETTING_CMD_0x42 */ +#define SET_8192F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8192F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value) +#define SET_8192F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) + +/* _AP_REQ_TXRPT_CMD_0x43 */ +#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) + +/* _FORCE_BT_TXPWR_CMD_0x62 */ +#define SET_8192F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) + +/* _FORCE_BT_MP_OPER_CMD_0x67 */ +#define SET_8192F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_8192F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) +#define SET_8192F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8192F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) +#define SET_8192F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) +#define SET_8192F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) + +/* _BT_FW_PATCH_0x6A */ +#define SET_8192F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value) +#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) + +/* --------------------------------------------------------------------------------------------------------- + * ------------------------------------------- Structure -------------------------------------------------- + * --------------------------------------------------------------------------------------------------------- */ + + +/* --------------------------------------------------------------------------------------------------------- + * ---------------------------------- Function Statement -------------------------------------------------- + * --------------------------------------------------------------------------------------------------------- */ + +/* host message to firmware cmd */ +void rtl8192f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); +void rtl8192f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); +/* s32 rtl8192f__set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ +void rtl8192f_set_FwPsTuneParam_cmd(PADAPTER padapter); +void rtl8192f_download_rsvd_page(PADAPTER padapter, u8 mstatus); +#ifdef CONFIG_BT_COEXIST + void rtl8192f__download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); +#endif /* CONFIG_BT_COEXIST */ +#ifdef CONFIG_P2P + void rtl8192f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); +#endif /* CONFIG_P2P */ + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW +void rtl8192f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); +#endif +#endif + +#ifdef CONFIG_P2P_WOWLAN + void rtl8192f_set_p2p_wowlan_offload_cmd(PADAPTER padapter); +#endif + +s32 FillH2CCmd8192F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); +u8 GetTxBufferRsvdPageNum8192F(_adapter *padapter, bool wowlan); +#endif diff --git a/include/rtl8192f_dm.h b/include/rtl8192f_dm.h new file mode 100644 index 0000000..e8e6adb --- /dev/null +++ b/include/rtl8192f_dm.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * + * Copyright(c) 2012 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8192F_DM_H__ +#define __RTL8192F_DM_H__ + + +void rtl8192f_init_dm_priv(IN PADAPTER Adapter); +void rtl8192f_deinit_dm_priv(IN PADAPTER Adapter); +void rtl8192f_InitHalDm(IN PADAPTER Adapter); +void rtl8192f_HalDmWatchDog(IN PADAPTER Adapter); + +/* VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); */ + +/* void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); */ + +#endif diff --git a/include/rtl8192f_hal.h b/include/rtl8192f_hal.h new file mode 100644 index 0000000..c8a828a --- /dev/null +++ b/include/rtl8192f_hal.h @@ -0,0 +1,315 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8192F_HAL_H__ +#define __RTL8192F_HAL_H__ + +#include "hal_data.h" + +#include "rtl8192f_spec.h" +#include "rtl8192f_rf.h" +#include "rtl8192f_dm.h" +#include "rtl8192f_recv.h" +#include "rtl8192f_xmit.h" +#include "rtl8192f_cmd.h" +#include "rtl8192f_led.h" +#include "Hal8192FPwrSeq.h" +#include "Hal8192FPhyReg.h" +#include "Hal8192FPhyCfg.h" +#ifdef DBG_CONFIG_ERROR_DETECT +#include "rtl8192f_sreset.h" +#endif +#ifdef CONFIG_LPS_POFF + #include "rtl8192f_lps_poff.h" +#endif + +#define FW_8192F_SIZE 0x8000 +#define FW_8192F_START_ADDRESS 0x4000 +#define FW_8192F_END_ADDRESS 0x5000 /* brian_zhang@realsil.com.cn */ + +#define IS_FW_HEADER_EXIST_8192F(_pFwHdr)\ + ((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x92F0) + +typedef struct _RT_FIRMWARE { + FIRMWARE_SOURCE eFWSource; +#ifdef CONFIG_EMBEDDED_FWIMG + u8 *szFwBuffer; +#else + u8 szFwBuffer[FW_8192F_SIZE]; +#endif + u32 ulFwLength; +} RT_FIRMWARE_8192F, *PRT_FIRMWARE_8192F; + +/* + * This structure must be cared byte-ordering + * + * Added by tynli. 2009.12.04. */ +typedef struct _RT_8192F_FIRMWARE_HDR { + /* 8-byte alinment required */ + + /* --- LONG WORD 0 ---- */ + u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */ + u8 Category; /* AP/NIC and USB/PCI */ + u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ + u16 Version; /* FW Version */ + u16 Subversion; /* FW Subversion, default 0x00 */ + + /* --- LONG WORD 1 ---- */ + u8 Month; /* Release time Month field */ + u8 Date; /* Release time Date field */ + u8 Hour; /* Release time Hour field */ + u8 Minute; /* Release time Minute field */ + u16 RamCodeSize; /* The size of RAM code */ + u16 Rsvd2; + + /* --- LONG WORD 2 ---- */ + u32 SvnIdx; /* The SVN entry index */ + u32 Rsvd3; + + /* --- LONG WORD 3 ---- */ + u32 Rsvd4; + u32 Rsvd5; +} RT_8192F_FIRMWARE_HDR, *PRT_8192F_FIRMWARE_HDR; +#define DRIVER_EARLY_INT_TIME_8192F 0x05 +#define BCN_DMA_ATIME_INT_TIME_8192F 0x02 +/* for 8192F + * TX 64K, RX 16K, Page size 256B for TX*/ +#define PAGE_SIZE_TX_8192F 256 +#define PAGE_SIZE_RX_8192F 8 +#define TX_DMA_SIZE_8192F 0x10000/* 64K(TX) */ +#define RX_DMA_SIZE_8192F 0x4000/* 16K(RX) */ +#ifdef CONFIG_WOWLAN + #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ +#else + #define RESV_FMWF 0 +#endif + +#ifdef CONFIG_FW_C2H_DEBUG + #define RX_DMA_RESERVED_SIZE_8192F 0x100 /* 256B, reserved for c2h debug message */ +#else + #define RX_DMA_RESERVED_SIZE_8192F 0xc0 /* 192B, reserved for tx report 24*8=192*/ +#endif +#define RX_DMA_BOUNDARY_8192F\ + (RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F - 1) + + +/* Note: We will divide number of page equally for each queue other than public queue! */ + +/* For General Reserved Page Number(Beacon Queue is reserved page) + * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8192F + * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/ +#define BCNQ_PAGE_NUM_8192F (MAX_BEACON_LEN/PAGE_SIZE_TX_8192F + 6) /*0x08*/ + + +/* For WoWLan , more reserved page + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6 + * NS offload: 2 NDP info: 1 + */ +#ifdef CONFIG_WOWLAN + #define WOWLAN_PAGE_NUM_8192F 0x07 +#else + #define WOWLAN_PAGE_NUM_8192F 0x00 +#endif + +#ifdef CONFIG_PNO_SUPPORT + #undef WOWLAN_PAGE_NUM_8192F + #define WOWLAN_PAGE_NUM_8192F 0x15 +#endif + +#ifdef CONFIG_AP_WOWLAN + #define AP_WOWLAN_PAGE_NUM_8192F 0x02 +#endif + +#ifdef DBG_LA_MODE + #define LA_MODE_PAGE_NUM 0xE0 +#endif + +#define MAX_RX_DMA_BUFFER_SIZE_8192F (RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F) + +#ifdef DBG_LA_MODE + #define TX_TOTAL_PAGE_NUMBER_8192F (0xFF - LA_MODE_PAGE_NUM) +#else + #define TX_TOTAL_PAGE_NUMBER_8192F (0xFF - BCNQ_PAGE_NUM_8192F - WOWLAN_PAGE_NUM_8192F) +#endif + +#define TX_PAGE_BOUNDARY_8192F (TX_TOTAL_PAGE_NUMBER_8192F + 1) + +#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F \ + TX_TOTAL_PAGE_NUMBER_8192F +#define WMM_NORMAL_TX_PAGE_BOUNDARY_8192F \ + (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F + 1) + +/* For Normal Chip Setting + * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192F */ +#define NORMAL_PAGE_NUM_HPQ_8192F 0x8 +#define NORMAL_PAGE_NUM_LPQ_8192F 0x8 +#define NORMAL_PAGE_NUM_NPQ_8192F 0x8 +#define NORMAL_PAGE_NUM_EPQ_8192F 0x00 + +/* Note: For Normal Chip Setting, modify later */ +#define WMM_NORMAL_PAGE_NUM_HPQ_8192F 0x30 +#define WMM_NORMAL_PAGE_NUM_LPQ_8192F 0x20 +#define WMM_NORMAL_PAGE_NUM_NPQ_8192F 0x20 +#define WMM_NORMAL_PAGE_NUM_EPQ_8192F 0x00 + + +#include "HalVerDef.h" +#include "hal_com.h" + +#define EFUSE_OOB_PROTECT_BYTES 56 /*0x1C8~0x1FF*/ + +#define HAL_EFUSE_MEMORY +#define HWSET_MAX_SIZE_8192F 512 +#define EFUSE_REAL_CONTENT_LEN_8192F 512 +#define EFUSE_MAP_LEN_8192F 512 +#define EFUSE_MAX_SECTION_8192F 64 + +/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/ +#define EFUSE_IC_ID_OFFSET 506 +#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8192F) + +#define EFUSE_ACCESS_ON 0x69 +#define EFUSE_ACCESS_OFF 0x00 + +/* ******************************************************** + * EFUSE for BT definition + * ******************************************************** */ +#define BANK_NUM 1 +#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512 +#define EFUSE_BT_REAL_CONTENT_LEN 1536/*512 * 3 */ +/* (EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)*/ +#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ +#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */ +#define EFUSE_PROTECT_BYTES_BANK 16 + +typedef enum tag_Package_Definition { + PACKAGE_DEFAULT, + PACKAGE_QFN32, + PACKAGE_QFN40, + PACKAGE_QFN46 +} PACKAGE_TYPE_E; + +#define INCLUDE_MULTI_FUNC_BT(_Adapter) \ + (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) +#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \ + (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) + +#ifdef CONFIG_FILE_FWIMG + extern char *rtw_fw_file_path; + extern char *rtw_fw_wow_file_path; + #ifdef CONFIG_MP_INCLUDED + extern char *rtw_fw_mp_bt_file_path; + #endif /* CONFIG_MP_INCLUDED */ +#endif /* CONFIG_FILE_FWIMG */ + +/* rtl8192f_hal_init.c */ +s32 rtl8192f_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw); +void rtl8192f_FirmwareSelfReset(PADAPTER padapter); +void rtl8192f_InitializeFirmwareVars(PADAPTER padapter); + +void rtl8192f_InitAntenna_Selection(PADAPTER padapter); +void rtl8192f_DeinitAntenna_Selection(PADAPTER padapter); +void rtl8192f_CheckAntenna_Selection(PADAPTER padapter); +void rtl8192f_init_default_value(PADAPTER padapter); + +s32 rtl8192f_InitLLTTable(PADAPTER padapter); + +s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU); +s32 CardDisableWithoutHWSM(PADAPTER padapter); + +/* EFuse */ +u8 GetEEPROMSize8192F(PADAPTER padapter); +void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent); +void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo); +void Hal_EfuseParseTxPowerInfo_8192F(PADAPTER padapter, + u8 *PROMContent, BOOLEAN AutoLoadFail); +/* +void Hal_EfuseParseBTCoexistInfo_8192F(PADAPTER padapter, + u8 *hwinfo, BOOLEAN AutoLoadFail); +*/ +void Hal_EfuseParseEEPROMVer_8192F(PADAPTER padapter, + u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseChnlPlan_8192F(PADAPTER padapter, + u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseCustomerID_8192F(PADAPTER padapter, + u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseAntennaDiversity_8192F(PADAPTER padapter, + u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseXtal_8192F(PADAPTER pAdapter, + u8 *hwinfo, u8 AutoLoadFail); +void Hal_EfuseParseThermalMeter_8192F(PADAPTER padapter, + u8 *hwinfo, u8 AutoLoadFail); +VOID Hal_EfuseParseVoltage_8192F(PADAPTER pAdapter, + u8 *hwinfo, BOOLEAN AutoLoadFail); +VOID Hal_EfuseParseBoardType_8192F(PADAPTER Adapter, + u8 *PROMContent, BOOLEAN AutoloadFail); +u8 Hal_ReadRFEType_8192F(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); +void rtl8192f_set_hal_ops(struct hal_ops *pHalFunc); +void init_hal_spec_8192f(_adapter *adapter); +u8 SetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val); +void GetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); +u8 GetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); + +/* register */ +void rtl8192f_InitBeaconParameters(PADAPTER padapter); +void rtl8192f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); + +void _InitMacAPLLSetting_8192F(PADAPTER Adapter); +void _8051Reset8192F(PADAPTER padapter); +#ifdef CONFIG_WOWLAN + void Hal_DetectWoWMode(PADAPTER pAdapter); +#endif /* CONFIG_WOWLAN */ + +void rtl8192f_start_thread(_adapter *padapter); +void rtl8192f_stop_thread(_adapter *padapter); + +#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) + void rtl8192fs_init_checkbthang_workqueue(_adapter *adapter); + void rtl8192fs_free_checkbthang_workqueue(_adapter *adapter); + void rtl8192fs_cancle_checkbthang_workqueue(_adapter *adapter); + void rtl8192fs_hal_check_bt_hang(_adapter *adapter); +#endif + +#ifdef CONFIG_GPIO_WAKEUP + void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); +#endif +#ifdef CONFIG_MP_INCLUDED +int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); +#endif +void CCX_FwC2HTxRpt_8192f(PADAPTER padapter, u8 *pdata, u8 len); + +u8 MRateToHwRate8192F(u8 rate); +u8 HwRateToMRate8192F(u8 rate); + +#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) + void check_bt_status_work(void *data); +#endif + + +void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc); + +#ifdef CONFIG_AMPDU_PRETX_CD +void rtl8192f_pretx_cd_config(_adapter *adapter); +#endif + +#ifdef CONFIG_PCI_HCI + BOOLEAN InterruptRecognized8192FE(PADAPTER Adapter); + VOID UpdateInterruptMask8192FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); + VOID InitMAC_TRXBD_8192FE(PADAPTER Adapter); + + u16 get_txbd_rw_reg(u16 ff_hwaddr); +#endif + +#endif diff --git a/include/rtl8192f_led.h b/include/rtl8192f_led.h new file mode 100644 index 0000000..22530b4 --- /dev/null +++ b/include/rtl8192f_led.h @@ -0,0 +1,42 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8192F_LED_H__ +#define __RTL8192F_LED_H__ + +#include +#include +#include + +#ifdef CONFIG_RTW_SW_LED +/* ******************************************************************************** + * Interface to manipulate LED objects. + * ******************************************************************************** */ +#ifdef CONFIG_USB_HCI +void rtl8192fu_InitSwLeds(PADAPTER padapter); +void rtl8192fu_DeInitSwLeds(PADAPTER padapter); +#endif + +#ifdef CONFIG_SDIO_HCI +void rtl8192fs_InitSwLeds(PADAPTER padapter); +void rtl8192fs_DeInitSwLeds(PADAPTER padapter); +#endif + +#ifdef CONFIG_PCI_HCI +void rtl8192fe_InitSwLeds(PADAPTER padapter); +void rtl8192fe_DeInitSwLeds(PADAPTER padapter); +#endif +#endif /*#ifdef CONFIG_RTW_SW_LED*/ + +#endif diff --git a/include/rtl8192f_recv.h b/include/rtl8192f_recv.h new file mode 100644 index 0000000..989551b --- /dev/null +++ b/include/rtl8192f_recv.h @@ -0,0 +1,111 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8192F_RECV_H__ +#define __RTL8192F_RECV_H__ + +#define RECV_BLK_SZ 512 +#define RECV_BLK_CNT 16 +#define RECV_BLK_TH RECV_BLK_CNT + +#if defined(CONFIG_USB_HCI) + + #ifndef MAX_RECVBUF_SZ + #ifdef PLATFORM_OS_CE + #define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */ + #else + #ifndef CONFIG_MINIMAL_MEMORY_USAGE + /* #define MAX_RECVBUF_SZ (32768) */ /* 32k */ + /* #define MAX_RECVBUF_SZ (16384) */ /* 16K */ + /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ + #ifdef CONFIG_PLATFORM_MSTAR + #define MAX_RECVBUF_SZ (8192) /* 8K */ + #else + #define MAX_RECVBUF_SZ (32768) /* 32k */ + #endif + /* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */ + #else + #define MAX_RECVBUF_SZ (4000) /* about 4K */ + #endif + #endif + #endif /* !MAX_RECVBUF_SZ */ + +#elif defined(CONFIG_PCI_HCI) + #define MAX_RECVBUF_SZ (4000) /* about 4K */ + +#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + + #define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8192F + 1) + +#endif + +/* Rx smooth factor */ +#define Rx_Smooth_Factor (20) + +#ifdef CONFIG_SDIO_HCI + #ifndef CONFIG_SDIO_RX_COPY + #undef MAX_RECVBUF_SZ + #define MAX_RECVBUF_SZ (RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F) + #endif /* !CONFIG_SDIO_RX_COPY */ +#endif /* CONFIG_SDIO_HCI */ + +/*-----------------------------------------------------------------*/ +/* RTL8192F RX BUFFER DESC */ +/*-----------------------------------------------------------------*/ +/*DWORD 0*/ +#define SET_RX_BUFFER_DESC_DATA_LENGTH_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) +#define SET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value) +#define SET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value) +#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value) + +#define GET_RX_BUFFER_DESC_OWN_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) +#define GET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) +#define GET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1) +#ifdef USING_RX_TAG + #define GET_RX_BUFFER_DESC_RX_TAG_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13) +#else + #define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15) +#endif + +/*DWORD 1*/ +#define SET_RX_BUFFER_PHYSICAL_LOW_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value) + +/*DWORD 2*/ +#ifdef CONFIG_64BIT_DMA + #define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value) +#else + #define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value) +#endif + + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + s32 rtl8192fs_init_recv_priv(PADAPTER padapter); + void rtl8192fs_free_recv_priv(PADAPTER padapter); + s32 rtl8192fs_recv_hdl(_adapter *padapter); +#endif + +#ifdef CONFIG_USB_HCI + int rtl8192fu_init_recv_priv(_adapter *padapter); + void rtl8192fu_free_recv_priv(_adapter *padapter); + void rtl8192fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); +#endif + +#ifdef CONFIG_PCI_HCI + s32 rtl8192fe_init_recv_priv(_adapter *padapter); + void rtl8192fe_free_recv_priv(_adapter *padapter); +#endif + +void rtl8192f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); + +#endif /* __RTL8192F_RECV_H__ */ diff --git a/include/rtl8192f_rf.h b/include/rtl8192f_rf.h new file mode 100644 index 0000000..1d3b759 --- /dev/null +++ b/include/rtl8192f_rf.h @@ -0,0 +1,22 @@ +/****************************************************************************** + * + * Copyright(c) 2012 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8192F_RF_H__ +#define __RTL8192F_RF_H__ + +int PHY_RF6052_Config8192F(IN PADAPTER pdapter); + +void PHY_RF6052SetBandwidth8192F(IN PADAPTER Adapter, IN enum channel_width Bandwidth); + +#endif/* __RTL8192F_RF_H__ */ diff --git a/include/rtl8192f_spec.h b/include/rtl8192f_spec.h new file mode 100644 index 0000000..54d3ae0 --- /dev/null +++ b/include/rtl8192f_spec.h @@ -0,0 +1,534 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8192F_SPEC_H__ +#define __RTL8192F_SPEC_H__ + +#include + + +#define HAL_NAV_UPPER_UNIT_8192F 128 /* micro-second */ + +/* ----------------------------------------------------- + * + * 0x0000h ~ 0x00FFh System Configuration + * + * ----------------------------------------------------- */ +#define REG_SYS_ISO_CTRL_8192F 0x0000 /* 2 Byte */ +#define REG_SYS_FUNC_EN_8192F 0x0002 /* 2 Byte */ +#define REG_APS_FSMCO_8192F 0x0004 /* 4 Byte */ +#define REG_SYS_CLKR_8192F 0x0008 /* 2 Byte */ +#define REG_9346CR_8192F 0x000A /* 2 Byte */ +#define REG_EE_VPD_8192F 0x000C /* 2 Byte */ +#define REG_AFE_MISC_8192F 0x0010 /* 1 Byte */ +#define REG_SPS0_CTRL_8192F 0x0011 /* 7 Byte */ +#define REG_SPS_OCP_CFG_8192F 0x0018 /* 4 Byte */ +#define REG_RSV_CTRL_8192F 0x001C /* 3 Byte */ +#define REG_RF_CTRL_8192F 0x001F /* 1 Byte */ +#define REG_LPLDO_CTRL_8192F 0x0023 /* 1 Byte */ +#define REG_AFE_XTAL_CTRL_8192F 0x0024 /* 4 Byte */ +#define REG_AFE_PLL_CTRL_8192F 0x0028 /* 4 Byte */ +#define REG_MAC_PLL_CTRL_EXT_8192F 0x002c /* 4 Byte */ +#define REG_EFUSE_CTRL_8192F 0x0030 +#define REG_EFUSE_TEST_8192F 0x0034 +#define REG_PWR_DATA_8192F 0x0038 +#define REG_CAL_TIMER_8192F 0x003C +#define REG_ACLK_MON_8192F 0x003E +#define REG_GPIO_MUXCFG_8192F 0x0040 +#define REG_GPIO_IO_SEL_8192F 0x0042 +#define REG_MAC_PINMUX_CFG_8192F 0x0043 +#define REG_GPIO_PIN_CTRL_8192F 0x0044 +#define REG_GPIO_INTM_8192F 0x0048 +#define REG_LEDCFG0_8192F 0x004C +#define REG_LEDCFG1_8192F 0x004D +#define REG_LEDCFG2_8192F 0x004E +#define REG_LEDCFG3_8192F 0x004F +#define REG_FSIMR_8192F 0x0050 +#define REG_FSISR_8192F 0x0054 +#define REG_HSIMR_8192F 0x0058 +#define REG_HSISR_8192F 0x005c +#define REG_GPIO_EXT_CTRL 0x0060 +#define REG_PAD_CTRL1_8192F 0x0064 +#define REG_MULTI_FUNC_CTRL_8192F 0x0068 +#define REG_GPIO_STATUS_8192F 0x006C +#define REG_SDIO_CTRL_8192F 0x0070 +#define REG_OPT_CTRL_8192F 0x0074 +#define REG_AFE_CTRL_4_8192F 0x0078 +#define REG_MCUFWDL_8192F 0x0080 +#define REG_8051FW_CTRL_8192F 0x0080 +#define REG_HMEBOX_DBG_0_8192F 0x0088 +#define REG_HMEBOX_DBG_1_8192F 0x008A +#define REG_HMEBOX_DBG_2_8192F 0x008C +#define REG_HMEBOX_DBG_3_8192F 0x008E +#define REG_WLLPS_CTRL 0x0090 +#define REG_HIMR0_8192F 0x00B0 +#define REG_HISR0_8192F 0x00B4 +#define REG_HIMR1_8192F 0x00B8 +#define REG_HISR1_8192F 0x00BC +#define REG_PMC_DBG_CTRL2_8192F 0x00CC +#define REG_EFUSE_BURN_GNT_8192F 0x00CF +#define REG_HPON_FSM_8192F 0x00EC +#define REG_SYS_CFG1_8192F 0x00F0 +#define REG_SYS_CFG2_8192F 0x00FC +#define REG_ROM_VERSION 0x00FD + +/* ----------------------------------------------------- + * + * 0x0100h ~ 0x01FFh MACTOP General Configuration + * + * ----------------------------------------------------- */ +#define REG_CR_8192F 0x0100 +#define REG_PBP_8192F 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL_8192F 0x0106 +#define REG_TRXDMA_CTRL_8192F 0x010C +#define REG_TRXFF_BNDY_8192F 0x0114 +#define REG_TRXFF_STATUS_8192F 0x0118 +#define REG_RXFF_PTR_8192F 0x011C +#define REG_CPWM_8192F 0x012C +#define REG_FWIMR_8192F 0x0130 +#define REG_FWISR_8192F 0x0134 +#define REG_FTIMR_8192F 0x0138 +#define REG_PKTBUF_DBG_CTRL_8192F 0x0140 +#define REG_RXPKTBUF_CTRL_8192F 0x0142 +#define REG_PKTBUF_DBG_DATA_L_8192F 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8192F 0x0148 + +#define REG_TC0_CTRL_8192F 0x0150 +#define REG_TC1_CTRL_8192F 0x0154 +#define REG_TC2_CTRL_8192F 0x0158 +#define REG_TC3_CTRL_8192F 0x015C +#define REG_TC4_CTRL_8192F 0x0160 +#define REG_TCUNIT_BASE_8192F 0x0164 +#define REG_RSVD3_8192F 0x0168 +#define REG_C2HEVT_CMD_ID_8192F 0x01A0 +#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 +#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 +#define REG_C2HEVT_CMD_LEN_8192F 0x01AE +#define REG_C2HEVT_CLEAR_8192F 0x01AF +#define REG_MCUTST_1_8192F 0x01C0 +#define REG_WOWLAN_WAKE_REASON 0x01C7 +#define REG_FMETHR_8192F 0x01C8 +#define REG_HMETFR_8192F 0x01CC +#define REG_HMEBOX_0_8192F 0x01D0 +#define REG_HMEBOX_1_8192F 0x01D4 +#define REG_HMEBOX_2_8192F 0x01D8 +#define REG_HMEBOX_3_8192F 0x01DC +#define REG_LLT_INIT_8192F 0x01E0 +#define REG_HMEBOX_EXT0_8192F 0x01F0 +#define REG_HMEBOX_EXT1_8192F 0x01F4 +#define REG_HMEBOX_EXT2_8192F 0x01F8 +#define REG_HMEBOX_EXT3_8192F 0x01FC + +/* ----------------------------------------------------- + * + * 0x0200h ~ 0x027Fh TXDMA Configuration + * + * ----------------------------------------------------- */ +#define REG_RQPN_8192F 0x0200 +#define REG_FIFOPAGE_8192F 0x0204 +#define REG_DWBCN0_CTRL_8192F REG_TDECTRL +#define REG_TXDMA_OFFSET_CHK_8192F 0x020C +#define REG_TXDMA_STATUS_8192F 0x0210 +#define REG_RQPN_NPQ_8192F 0x0214 +#define REG_DWBCN1_CTRL_8192F 0x0228 +#define REG_RQPN_EXQ1_EXQ2 0x0230 + +/* ----------------------------------------------------- + * + * 0x0280h ~ 0x02FFh RXDMA Configuration + * + * ----------------------------------------------------- */ +#define REG_RXDMA_AGG_PG_TH_8192F 0x0280 +#define REG_FW_UPD_RDPTR_8192F 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ +#define REG_RXDMA_CONTROL_8192F 0x0286 /* Control the RX DMA. */ +#define REG_RXDMA_STATUS_8192F 0x0288 +#define REG_RXDMA_MODE_CTRL_8192F 0x0290 +#define REG_EARLY_MODE_CONTROL_8192F 0x02BC +#define REG_RSVD5_8192F 0x02F0 +#define REG_RSVD6_8192F 0x02F4 + +/* ----------------------------------------------------- + * + * 0x0300h ~ 0x03FFh PCIe + * + * ----------------------------------------------------- */ +#define REG_PCIE_CTRL_REG_8192F 0x0300 +#define REG_INT_MIG_8192F 0x0304 /* Interrupt Migration */ +#define REG_BCNQ_TXBD_DESA_8192F 0x0308 /* TX Beacon Descriptor Address */ +#define REG_MGQ_TXBD_DESA_8192F 0x0310 /* TX Manage Queue Descriptor Address */ +#define REG_VOQ_TXBD_DESA_8192F 0x0318 /* TX VO Queue Descriptor Address */ +#define REG_VIQ_TXBD_DESA_8192F 0x0320 /* TX VI Queue Descriptor Address */ +#define REG_BEQ_TXBD_DESA_8192F 0x0328 /* TX BE Queue Descriptor Address */ +#define REG_BKQ_TXBD_DESA_8192F 0x0330 /* TX BK Queue Descriptor Address */ +#define REG_RXQ_RXBD_DESA_8192F 0x0338 /* RX Queue Descriptor Address */ +#define REG_HI0Q_TXBD_DESA_8192F 0x0340 +#define REG_HI1Q_TXBD_DESA_8192F 0x0348 +#define REG_HI2Q_TXBD_DESA_8192F 0x0350 +#define REG_HI3Q_TXBD_DESA_8192F 0x0358 +#define REG_HI4Q_TXBD_DESA_8192F 0x0360 +#define REG_HI5Q_TXBD_DESA_8192F 0x0368 +#define REG_HI6Q_TXBD_DESA_8192F 0x0370 +#define REG_HI7Q_TXBD_DESA_8192F 0x0378 +#define REG_MGQ_TXBD_NUM_8192F 0x0380 +#define REG_RX_RXBD_NUM_8192F 0x0382 +#define REG_VOQ_TXBD_NUM_8192F 0x0384 +#define REG_VIQ_TXBD_NUM_8192F 0x0386 +#define REG_BEQ_TXBD_NUM_8192F 0x0388 +#define REG_BKQ_TXBD_NUM_8192F 0x038A +#define REG_HI0Q_TXBD_NUM_8192F 0x038C +#define REG_HI1Q_TXBD_NUM_8192F 0x038E +#define REG_HI2Q_TXBD_NUM_8192F 0x0390 +#define REG_HI3Q_TXBD_NUM_8192F 0x0392 +#define REG_HI4Q_TXBD_NUM_8192F 0x0394 +#define REG_HI5Q_TXBD_NUM_8192F 0x0396 +#define REG_HI6Q_TXBD_NUM_8192F 0x0398 +#define REG_HI7Q_TXBD_NUM_8192F 0x039A +#define REG_TSFTIMER_HCI_8192F 0x039C +#define REG_BD_RW_PTR_CLR_8192F 0x039C + +/* Read Write Point */ +#define REG_VOQ_TXBD_IDX_8192F 0x03A0 +#define REG_VIQ_TXBD_IDX_8192F 0x03A4 +#define REG_BEQ_TXBD_IDX_8192F 0x03A8 +#define REG_BKQ_TXBD_IDX_8192F 0x03AC +#define REG_MGQ_TXBD_IDX_8192F 0x03B0 +#define REG_RXQ_TXBD_IDX_8192F 0x03B4 +#define REG_HI0Q_TXBD_IDX_8192F 0x03B8 +#define REG_HI1Q_TXBD_IDX_8192F 0x03BC +#define REG_HI2Q_TXBD_IDX_8192F 0x03C0 +#define REG_HI3Q_TXBD_IDX_8192F 0x03C4 +#define REG_HI4Q_TXBD_IDX_8192F 0x03C8 +#define REG_HI5Q_TXBD_IDX_8192F 0x03CC +#define REG_HI6Q_TXBD_IDX_8192F 0x03D0 +#define REG_HI7Q_TXBD_IDX_8192F 0x03D4 +#define REG_DBI_WDATA_V1_8192F 0x03E8 +#define REG_DBI_RDATA_V1_8192F 0x03EC +#define REG_DBI_FLAG_V1_8192F 0x03F0 +#define REG_MDIO_V1_8192F 0x03F4 +#define REG_HCI_MIX_CFG_8192F 0x03FC +#define REG_PCIE_HCPWM_8192FE 0x03D8 +#define REG_PCIE_HRPWM_8192FE 0x03DC +#define REG_PCIE_MIX_CFG_8192F 0x03F8 + +/* ----------------------------------------------------- + * + * 0x0400h ~ 0x047Fh Protocol Configuration + * + * ----------------------------------------------------- */ +#define REG_QUEUELIST_INFO0_8192F 0x0400 +#define REG_QUEUELIST_INFO1_8192F 0x0404 +#define REG_QUEUELIST_INFO2_8192F 0x0414 +#define REG_TXPKT_EMPTY_8192F 0x0418 + +#define REG_FWHW_TXQ_CTRL_8192F 0x0420 +#define REG_HWSEQ_CTRL_8192F 0x0423 +#define REG_TXPKTBUF_BCNQ_BDNY_8192F 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY_8192F 0x0425 +#define REG_LIFECTRL_CTRL_8192F 0x0426 +#define REG_MULTI_BCNQ_OFFSET_8192F 0x0427 +#define REG_SPEC_SIFS_8192F 0x0428 +#define REG_RL_8192F 0x042A +#define REG_TXBF_CTRL_8192F 0x042C +#define REG_DARFRC_8192F 0x0430 +#define REG_RARFRC_8192F 0x0438 +#define REG_RRSR_8192F 0x0440 +#define REG_ARFR0_8192F 0x0444 +#define REG_ARFR1_8192F 0x044C +#define REG_CCK_CHECK_8192F 0x0454 +#define REG_AMPDU_MAX_TIME_8192F 0x0456 +#define REG_TXPKTBUF_BCNQ_BDNY1_8192F 0x0457 + +#define REG_AMPDU_MAX_LENGTH_8192F 0x0458 +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8192F 0x045D +#define REG_NDPA_OPT_CTRL_8192F 0x045F +#define REG_FAST_EDCA_CTRL_8192F 0x0460 +#define REG_RD_RESP_PKT_TH_8192F 0x0463 +#define REG_DATA_SC_8192F 0x0483 +#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_POWER_STAGE1_8192F 0x04B4 +#define REG_POWER_STAGE2_8192F 0x04B8 +#define REG_AMPDU_BURST_MODE_8192F 0x04BC +#define REG_PKT_VO_VI_LIFE_TIME_8192F 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME_8192F 0x04C2 +#define REG_STBC_SETTING_8192F 0x04C4 +#define REG_HT_SINGLE_AMPDU_8192F 0x04C7 +#define REG_PROT_MODE_CTRL_8192F 0x04C8 +#define REG_MAX_AGGR_NUM_8192F 0x04CA +#define REG_RTS_MAX_AGGR_NUM_8192F 0x04CB +#define REG_BAR_MODE_CTRL_8192F 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8192F 0x04CF +#define REG_MACID_PKT_DROP0_8192F 0x04D0 +#define REG_MACID_PKT_SLEEP_8192F 0x04D4 +#define REG_PRECNT_CTRL_8192F 0x04E5 +/* ----------------------------------------------------- + * + * 0x0500h ~ 0x05FFh EDCA Configuration + * + * ----------------------------------------------------- */ +#define REG_EDCA_VO_PARAM_8192F 0x0500 +#define REG_EDCA_VI_PARAM_8192F 0x0504 +#define REG_EDCA_BE_PARAM_8192F 0x0508 +#define REG_EDCA_BK_PARAM_8192F 0x050C +#define REG_BCNTCFG_8192F 0x0510 +#define REG_PIFS_8192F 0x0512 +#define REG_RDG_PIFS_8192F 0x0513 +#define REG_SIFS_CTX_8192F 0x0514 +#define REG_SIFS_TRX_8192F 0x0516 +#define REG_AGGR_BREAK_TIME_8192F 0x051A +#define REG_SLOT_8192F 0x051B +#define REG_TX_PTCL_CTRL_8192F 0x0520 +#define REG_TXPAUSE_8192F 0x0522 +#define REG_DIS_TXREQ_CLR_8192F 0x0523 +#define REG_RD_CTRL_8192F 0x0524 +/* + * Format for offset 540h-542h: + * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. + * [7:4]: Reserved. + * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. + * [23:20]: Reserved + * Description: + * | + * |<--Setup--|--Hold------------>| + * --------------|---------------------- + * | + * TBTT + * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. + * Described by Designer Tim and Bruce, 2011-01-14. + * */ +#define REG_TBTT_PROHIBIT_8192F 0x0540 +#define REG_RD_NAV_NXT_8192F 0x0544 +#define REG_NAV_PROT_LEN_8192F 0x0546 +#define REG_BCN_CTRL_8192F 0x0550 +#define REG_BCN_CTRL_1_8192F 0x0551 +#define REG_MBID_NUM_8192F 0x0552 +#define REG_DUAL_TSF_RST_8192F 0x0553 +#define REG_BCN_INTERVAL_8192F 0x0554 +#define REG_DRVERLYINT_8192F 0x0558 +#define REG_BCNDMATIM_8192F 0x0559 +#define REG_ATIMWND_8192F 0x055A +#define REG_USTIME_TSF_8192F 0x055C +#define REG_BCN_MAX_ERR_8192F 0x055D +#define REG_RXTSF_OFFSET_CCK_8192F 0x055E +#define REG_RXTSF_OFFSET_OFDM_8192F 0x055F +#define REG_TSFTR_8192F 0x0560 +#define REG_CTWND_8192F 0x0572 +#define REG_SECONDARY_CCA_CTRL_8192F 0x0577 +#define REG_PSTIMER_8192F 0x0580 +#define REG_TIMER0_8192F 0x0584 +#define REG_TIMER1_8192F 0x0588 +#define REG_ACMHWCTRL_8192F 0x05C0 +#define REG_SCH_TXCMD_8192F 0x05F8 + +/* ----------------------------------------------------- + * + * 0x0600h ~ 0x07FFh WMAC Configuration + * + * ----------------------------------------------------- */ +#define REG_MAC_CR_8192F 0x0600 +#define REG_TCR_8192F 0x0604 +#define REG_RCR_8192F 0x0608 +#define REG_RX_PKT_LIMIT_8192F 0x060C +#define REG_RX_DLK_TIME_8192F 0x060D +#define REG_RX_DRVINFO_SZ_8192F 0x060F + +#define REG_MACID_8192F 0x0610 +#define REG_BSSID_8192F 0x0618 +#define REG_MAR_8192F 0x0620 +#define REG_MBIDCAMCFG_8192F 0x0628 + + +#define REG_USTIME_EDCA_8192F 0x0638 +#define REG_MAC_SPEC_SIFS_8192F 0x063A +#define REG_RESP_SIFP_CCK_8192F 0x063C +#define REG_RESP_SIFS_OFDM_8192F 0x063E +#define REG_ACKTO_8192F 0x0640 +#define REG_CTS2TO_8192F 0x0641 +#define REG_EIFS_8192F 0x0642 + +#define REG_NAV_UPPER_8192F 0x0652 /* unit of 128*/ +#define REG_TRXPTCL_CTL_8192F 0x0668 + +/* Security*/ +#define REG_CAMCMD_8192F 0x0670 +#define REG_CAMWRITE_8192F 0x0674 +#define REG_CAMREAD_8192F 0x0678 +#define REG_CAMDBG_8192F 0x067C +#define REG_SECCFG_8192F 0x0680 + +/* Power */ +#define REG_WOW_CTRL_8192F 0x0690 +#define REG_PS_RX_INFO_8192F 0x0692 +#define REG_UAPSD_TID_8192F 0x0693 +#define REG_WKFMCAM_CMD_8192F 0x0698 +#define REG_WKFMCAM_NUM_8192F 0x0698 +#define REG_WKFMCAM_RWD_8192F 0x069C +#define REG_RXFLTMAP0_8192F 0x06A0 +#define REG_RXFLTMAP1_8192F 0x06A2 +#define REG_RXFLTMAP2_8192F 0x06A4 +#define REG_BCN_PSR_RPT_8192F 0x06A8 +#define REG_BT_COEX_TABLE_8192F 0x06C0 +#define REG_BFMER0_INFO_8192F 0x06E4 +#define REG_BFMER1_INFO_8192F 0x06EC +#define REG_CSI_RPT_PARAM_BW20_8192F 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_8192F 0x06F8 +#define REG_CSI_RPT_PARAM_BW80_8192F 0x06FC + +/* Hardware Port 2 */ +#define REG_MACID1_8192F 0x0700 +#define REG_BSSID1_8192F 0x0708 +#define REG_BFMEE_SEL_8192F 0x0714 +#define REG_SND_PTCL_CTRL_8192F 0x0718 + +/* LTR */ +#define REG_LTR_CTRL_BASIC_8192F 0x07A4 +#define REG_LTR_IDLE_LATENCY_V1_8192F 0x0798 +#define REG_LTR_ACTIVE_LATENCY_V1_8192F 0x079C + + +/* ************************************************************ + * SDIO Bus Specification + * ************************************************************ */ + +/* ----------------------------------------------------- + * SDIO CMD Address Mapping + * ----------------------------------------------------- */ + +/* ----------------------------------------------------- + * I/O bus domain (Host) + * ----------------------------------------------------- */ +/*SDIO Host Interrupt Mask Register */ +#define SDIO_HIMR_CRCERR_MSK BIT(31) +/* SDIO Host Interrupt Service Routine */ +#define SDIO_HISR_HEISR_IND_INT BIT(28) +#define SDIO_HISR_HSISR2_IND_INT BIT(29) +#define SDIO_HISR_HSISR3_IND_INT BIT(30) +#define SDIO_HISR_SDIO_CRCERR BIT(31) +/* ----------------------------------------------------- + * SDIO register + * ----------------------------------------------------- */ +#define SDIO_REG_HCPWM1_8192F 0x038/* HCI Current Power Mode 1 */ +#define SDIO_REG_FREE_TXPG1_8192F 0x0020 /* Free Tx Buffer Page1*/ +#define SDIO_REG_FREE_TXPG2_8192F 0x0024 /* Free Tx Buffer Page1*/ +#define SDIO_REG_FREE_TXPG3_8192F 0x0028 +#define SDIO_REG_AC_OQT_FREEPG_8192F 0x002A +#define SDIO_REG_NOAC_OQT_FREEPG_8192F 0x002B +/* **************************************************************************** + * 8192F Regsiter Bit and Content definition + * **************************************************************************** */ + +#define BIT_USB_RXDMA_AGG_EN BIT(31) +#define RXDMA_AGG_MODE_EN BIT(1) + +#ifdef CONFIG_WOWLAN + #define RXPKT_RELEASE_POLL BIT(16) + #define RXDMA_IDLE BIT(17) + #define RW_RELEASE_EN BIT(18) +#endif + +#ifdef CONFIG_AMPDU_PRETX_CD +/*#define BIT_ERRORHDL_INT BIT(2)*/ +/*#define BIT_MACTX_ERR_3 BIT(4)*/ +#define BIT_PRE_TX_CMD_8192F BIT(6) +#define BIT_EN_PRECNT_8192F BIT(11) +#endif +/* SDIO Host Interrupt Service Routine */ +#define SDIO_HISR_HEISR_IND_INT BIT(28) +#define SDIO_HISR_HSISR2_IND_INT BIT(29) +#define SDIO_HISR_HSISR3_IND_INT BIT(30) +#define SDIO_HISR_SDIO_CRCERR BIT(31) + +/* PCIE Host Interrupt Mask Register (HIMR) */ +#ifdef CONFIG_PCI_HCI +/* ---------------------------------------------------------------------------- + * * 8192F IMR/ISR bits (offset 0xB0, 8bits) + * * ---------------------------------------------------------------------------- */ + +#define IMR_DISABLED_8192F 0 +/* IMR DW0(0x00B0-00B3) Bit 0-31 */ +#define IMR_TIMER2_8192F BIT(31) /* Timeout interrupt 2 */ +#define IMR_TIMER1_8192F BIT(30) /* Timeout interrupt 1 */ +#define IMR_PSTIMEOUT_8192F BIT(29) /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_8192F BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_8192F BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TXBCN0ERR_8192F BIT(26) /* Transmit Beacon0 Error */ +#define IMR_TXBCN0OK_8192F BIT(25) /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_8192F BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ +#define IMR_BCNDMAINT0_8192F BIT(20) /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_8192F BIT(16) /* Beacon Queue DMA OK0 */ +#define IMR_HSISR_IND_ON_INT_8192F BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_8192F BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_8192F BIT(12) /* CTWidnow End or ATIM Window End */ +#define IMR_C2HCMD_8192F BIT(10) /* CPU to Host Command INT status, Write 1 clear */ +#define IMR_CPWM2_8192F BIT(9) /* CPU power mode exchange INT status, Write 1 clear */ +#define IMR_CPWM_8192F BIT(8) /* CPU power mode exchange INT status, Write 1 clear */ +#define IMR_HIGHDOK_8192F BIT(7) /* High Queue DMA OK */ +#define IMR_MGNTDOK_8192F BIT(6) /* Management Queue DMA OK */ +#define IMR_BKDOK_8192F BIT(5) /* AC_BK DMA OK */ +#define IMR_BEDOK_8192F BIT(4) /* AC_BE DMA OK */ +#define IMR_VIDOK_8192F BIT(3) /* AC_VI DMA OK */ +#define IMR_VODOK_8192F BIT(2) /* AC_VO DMA OK */ +#define IMR_RDU_8192F BIT(1) /* Rx Descriptor Unavailable */ +#define IMR_ROK_8192F BIT(0) /* Receive DMA OK */ + +/* IMR DW1(0x00B4-00B7) Bit 0-31 */ +#define IMR_MCUERR_8192F BIT(28) +#define IMR_BCNDMAINT7_8192F BIT(27) /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_8192F BIT(26) /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_8192F BIT(25) /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_8192F BIT(24) /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_8192F BIT(23) /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_8192F BIT(22) /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_8192F BIT(21) /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDOK7_8192F BIT(20) /* Beacon Queue DMA OK Interrup 7 */ +#define IMR_BCNDOK6_8192F BIT(19) /* Beacon Queue DMA OK Interrup 6 */ +#define IMR_BCNDOK5_8192F BIT(18) /* Beacon Queue DMA OK Interrup 5 */ +#define IMR_BCNDOK4_8192F BIT(17) /* Beacon Queue DMA OK Interrup 4 */ +#define IMR_BCNDOK3_8192F BIT(16) /* Beacon Queue DMA OK Interrup 3 */ +#define IMR_BCNDOK2_8192F BIT(15) /* Beacon Queue DMA OK Interrup 2 */ +#define IMR_BCNDOK1_8192F BIT(14) /* Beacon Queue DMA OK Interrup 1 */ +#define IMR_ATIMEND_E_8192F BIT(13) /* ATIM Window End Extension for Win7 */ +#define IMR_TXERR_8192F BIT(11) /* Tx Error Flag Interrupt status, write 1 clear. */ +#define IMR_RXERR_8192F BIT(10) /* Rx Error Flag INT status, Write 1 clear */ +#define IMR_TXFOVW_8192F BIT(9) /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_8192F BIT(8) /* Receive FIFO Overflow */ + +/* #define IMR_RX_MASK (IMR_ROK_8192F|IMR_RDU_8192F|IMR_RXFOVW_8192F) */ +#define IMR_TX_MASK (IMR_VODOK_8192F | IMR_VIDOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F | IMR_MGNTDOK_8192F | IMR_HIGHDOK_8192F) +#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8192F | IMR_TXBCN0OK_8192F | IMR_TXBCN0ERR_8192F | IMR_BCNDERR0_8192F) +#define RT_AC_INT_MASKS (IMR_VIDOK_8192F | IMR_VODOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F) +#endif /* CONFIG_PCI_HCI */ + +/* 2 HSISR + * interrupt mask which needs to clear */ +#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ + HSISR_SPS_OCP_INT |\ + HSISR_RON_INT |\ + HSISR_PDNINT |\ + HSISR_GPIO9_INT) + +#define _TXDMA_HIQ_MAP_8192F(x) (((x) & 0x7) << 19) +#define _TXDMA_MGQ_MAP_8192F(x) (((x) & 0x7) << 16) +#define _TXDMA_BKQ_MAP_8192F(x) (((x) & 0x7) << 13) +#define _TXDMA_BEQ_MAP_8192F(x) (((x) & 0x7) << 10) +#define _TXDMA_VIQ_MAP_8192F(x) (((x) & 0x7) << 7) +#define _TXDMA_VOQ_MAP_8192F(x) (((x) & 0x7) << 4) + +/*mac queue info*/ +#define QUEUE_TOTAL_NUM 20/*reg414h : 0~f ac queue 0x10~0x13MGQ HIQ BCNQ CMDQ*/ +#define QUEUE_ACQ_NUM 16 +#define QUEUE_INDEX_MGQ 0x10 +#define QUEUE_INDEX_HIQ 0x11 +#define QUEUE_INDEX_BCNQ 0x12 +#define QUEUE_INDEX_CMDQ 0x13 +#endif /* __RTL8192F_SPEC_H__ */ diff --git a/include/rtl8192f_sreset.h b/include/rtl8192f_sreset.h new file mode 100644 index 0000000..cf881c4 --- /dev/null +++ b/include/rtl8192f_sreset.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTL8192F_SRESET_H_ +#define _RTL8192F_SRESET_H_ + +#include + +#ifdef DBG_CONFIG_ERROR_DETECT + extern void rtl8192f_sreset_xmit_status_check(_adapter *padapter); + extern void rtl8192f_sreset_linked_status_check(_adapter *padapter); +#endif /* DBG_CONFIG_ERROR_DETECT */ +#endif /* _RTL8192F_SRESET_H_ */ \ No newline at end of file diff --git a/include/rtl8192f_xmit.h b/include/rtl8192f_xmit.h new file mode 100644 index 0000000..6e0f1ea --- /dev/null +++ b/include/rtl8192f_xmit.h @@ -0,0 +1,531 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8192F_XMIT_H__ +#define __RTL8192F_XMIT_H__ + + +#define MAX_TID (15) + + +#ifndef __INC_HAL8192FDESC_H +#define __INC_HAL8192FDESC_H + +#define RX_STATUS_DESC_SIZE_8192F 24 +#define RX_DRV_INFO_SIZE_UNIT_8192F 8 + + +/* DWORD 0 */ +#define SET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) +#define SET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) +#define SET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) + +#define GET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) +#define GET_RX_STATUS_DESC_CRC32_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) +#define GET_RX_STATUS_DESC_ICV_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) +#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) +#define GET_RX_STATUS_DESC_SECURITY_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) +#define GET_RX_STATUS_DESC_QOS_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) +#define GET_RX_STATUS_DESC_SHIFT_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) +#define GET_RX_STATUS_DESC_PHY_STATUS_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) +#define GET_RX_STATUS_DESC_SWDEC_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) +#define GET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) +#define GET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) + +/* DWORD 1 */ +#define GET_RX_STATUS_DESC_MACID_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) +#define GET_RX_STATUS_DESC_TID_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) +#define GET_RX_STATUS_DESC_AMSDU_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) +#define GET_RX_STATUS_DESC_RXID_MATCH_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) +#define GET_RX_STATUS_DESC_PAGGR_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) +#define GET_RX_STATUS_DESC_A1_FIT_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) +#define GET_RX_STATUS_DESC_CHKERR_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) +#define GET_RX_STATUS_DESC_IPVER_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) +#define GET_RX_STATUS_DESC_IS_TCPUDP__8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) +#define GET_RX_STATUS_DESC_CHK_VLD_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) +#define GET_RX_STATUS_DESC_PAM_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) +#define GET_RX_STATUS_DESC_PWR_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) +#define GET_RX_STATUS_DESC_MORE_DATA_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) +#define GET_RX_STATUS_DESC_MORE_FRAG_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) +#define GET_RX_STATUS_DESC_TYPE_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) +#define GET_RX_STATUS_DESC_MC_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) +#define GET_RX_STATUS_DESC_BC_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) + +/* DWORD 2 */ +#define GET_RX_STATUS_DESC_SEQ_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) +#define GET_RX_STATUS_DESC_FRAG_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) +#define GET_RX_STATUS_DESC_RX_IS_QOS_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) +#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) +#define GET_RX_STATUS_DESC_RPT_SEL_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) +#define GET_RX_STATUS_DESC_FCS_OK_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1) + +/* DWORD 3 */ +#define GET_RX_STATUS_DESC_RX_RATE_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) +#define GET_RX_STATUS_DESC_HTC_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) +#define GET_RX_STATUS_DESC_EOSP_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) +#define GET_RX_STATUS_DESC_BSSID_FIT_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) +#ifdef CONFIG_USB_RX_AGGREGATION +#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) +#endif +#define GET_RX_STATUS_DESC_PATTERN_MATCH_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) +#define GET_RX_STATUS_DESC_UNICAST_MATCH_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) +#define GET_RX_STATUS_DESC_MAGIC_MATCH_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) + +/* DWORD 6 */ +#define GET_RX_STATUS_DESC_MATCH_ID_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7) + +/* DWORD 5 */ +#define GET_RX_STATUS_DESC_TSFL_8192F(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) + +#define GET_RX_STATUS_DESC_BUFF_ADDR64_8192F(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) + + + +/* Dword 0, rsvd: bit26, bit28 */ +#define GET_TX_DESC_OWN_8192F(__pTxDesc)\ + LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) + +#define SET_TX_DESC_PKT_SIZE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) +#define SET_TX_DESC_OFFSET_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) +#define SET_TX_DESC_BMC_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) +#define SET_TX_DESC_HTC_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) +#define SET_TX_DESC_AMSDU_PAD_EN_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) +#define SET_TX_DESC_NO_ACM_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) +#define SET_TX_DESC_GF_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) + +/* Dword 1 */ +#define SET_TX_DESC_MACID_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) +#define SET_TX_DESC_QUEUE_SEL_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) +#define SET_TX_DESC_RDG_NAV_EXT_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) +#define SET_TX_DESC_LSIG_TXOP_EN_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) +#define SET_TX_DESC_PIFS_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) +#define SET_TX_DESC_RATE_ID_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) +#define SET_TX_DESC_EN_DESC_ID_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) +#define SET_TX_DESC_SEC_TYPE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) +#define SET_TX_DESC_PKT_OFFSET_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) +#define SET_TX_DESC_MORE_DATA_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value) + +/* Dword 2 ADD HW_DIG*/ +#define SET_TX_DESC_PAID_92F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) +#define SET_TX_DESC_CCA_RTS_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) +#define SET_TX_DESC_AGG_ENABLE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) +#define SET_TX_DESC_RDG_ENABLE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) +#define SET_TX_DESC_NULL0_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value) +#define SET_TX_DESC_NULL1_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value) +#define SET_TX_DESC_BK_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) +#define SET_TX_DESC_MORE_FRAG_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) +#define SET_TX_DESC_RAW_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) +#define SET_TX_DESC_CCX_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) +#define SET_TX_DESC_AMPDU_DENSITY_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) +#define SET_TX_DESC_BT_INT_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) +#define SET_TX_DESC_HW_DIG_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 7, __Value) + +/* Dword 3 */ +#define SET_TX_DESC_HWSEQ_SEL_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) +#define SET_TX_DESC_USE_RATE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) +#define SET_TX_DESC_DISABLE_RTS_FB_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) +#define SET_TX_DESC_DISABLE_FB_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) +#define SET_TX_DESC_CTS2SELF_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) +#define SET_TX_DESC_RTS_ENABLE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) +#define SET_TX_DESC_HW_RTS_ENABLE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) +#define SET_TX_DESC_CHK_EN_92F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value) +#define SET_TX_DESC_NAV_USE_HDR_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) +#define SET_TX_DESC_USE_MAX_LEN_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) +#define SET_TX_DESC_MAX_AGG_NUM_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) +#define SET_TX_DESC_NDPA_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) +#define SET_TX_DESC_AMPDU_MAX_TIME_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) + +/* Dword 4 */ +#define SET_TX_DESC_TX_RATE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) +#define SET_TX_DESC_TX_TRY_RATE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value) +#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) +#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) +#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) +#define SET_TX_DESC_DATA_RETRY_LIMIT_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) +#define SET_TX_DESC_RTS_RATE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) +#define SET_TX_DESC_PCTS_EN_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value) +#define SET_TX_DESC_PCTS_MASK_IDX_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value) + +/* Dword 5 */ +#define SET_TX_DESC_DATA_SC_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) +#define SET_TX_DESC_DATA_SHORT_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) +#define SET_TX_DESC_DATA_BW_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) +#define SET_TX_DESC_DATA_LDPC_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) +#define SET_TX_DESC_DATA_STBC_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) +#define SET_TX_DESC_RTS_STBC_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) +#define SET_TX_DESC_RTS_SHORT_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) +#define SET_TX_DESC_RTS_SC_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) +#define SET_TX_DESC_PORT_ID_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 1, __Value) +#define SET_TX_DESC_DROP_ID_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 22, 2, __Value) +#define SET_TX_DESC_PATH_A_EN_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value) +#define SET_TX_DESC_PATH_B_EN_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 25, 1, __Value) +#define SET_TX_DESC_TXPWR_OF_SET_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value) + +/* Dword 6 */ +#define SET_TX_DESC_SW_DEFINE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) +#define SET_TX_DESC_MBSSID_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) +#define SET_TX_DESC_RF_SEL_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) + +/* Dword 7 */ +#ifdef CONFIG_PCI_HCI +#define SET_TX_DESC_TX_BUFFER_SIZE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) +#endif + +#ifdef CONFIG_USB_HCI +#define SET_TX_DESC_TX_DESC_CHECKSUM_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) +#endif + +#ifdef CONFIG_SDIO_HCI +#define SET_TX_DESC_TX_TIMESTAMP_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value) +#endif + +#define SET_TX_DESC_USB_TXAGG_NUM_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) + +/* Dword 8 */ +#define SET_TX_DESC_RTS_RC_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value) +#define SET_TX_DESC_BAR_RC_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value) +#define SET_TX_DESC_DATA_RC_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value) +#define SET_TX_DESC_HWSEQ_EN_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) +#define SET_TX_DESC_NEXTHEADPAGE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) +#define SET_TX_DESC_TAILPAGE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value) + +/* Dword 9 */ +#define SET_TX_DESC_PADDING_LEN_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value) +#define SET_TX_DESC_SEQ_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) +#define SET_TX_DESC_FINAL_DATA_RATE_8192F(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value) + + +#define SET_EARLYMODE_PKTNUM_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) +#define SET_EARLYMODE_LEN0_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) +#define SET_EARLYMODE_LEN1_1_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) +#define SET_EARLYMODE_LEN1_2_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) +#define SET_EARLYMODE_LEN2_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) +#define SET_EARLYMODE_LEN3_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) + + +/*-----------------------------------------------------------------*/ +/* RTL8192F TX BUFFER DESC */ +/*-----------------------------------------------------------------*/ +#ifdef CONFIG_64BIT_DMA + #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu) + #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu) + #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu) + #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu) +#else + #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu) + #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu) + #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu) + #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) /* 64 BIT mode only */ +#endif +/* ********************************************************* */ + +/* 64 bits -- 32 bits */ +/* ======= ======= */ +/* Dword 0 0 */ +#define SET_TX_BUFF_DESC_LEN_0_8192F(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu) +#define SET_TX_BUFF_DESC_PSB_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value) +#define SET_TX_BUFF_DESC_OWN_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) + +/* Dword 1 1 */ +#define SET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value) +#define GET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32) +/* Dword 2 NA */ +#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value) +#ifdef CONFIG_64BIT_DMA + #define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32) +#else + #define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) 0 +#endif +/* Dword 3 NA */ +/* RESERVED 0 */ +/* Dword 4 2 */ +#define SET_TX_BUFF_DESC_LEN_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value) +#define SET_TX_BUFF_DESC_AMSDU_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value) +/* Dword 5 3 */ +#define SET_TX_BUFF_DESC_ADDR_LOW_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value) +/* Dword 6 NA */ +#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value) +/* Dword 7 NA */ +/*RESERVED 0 */ +/* Dword 8 4 */ +#define SET_TX_BUFF_DESC_LEN_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value) +#define SET_TX_BUFF_DESC_AMSDU_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value) +/* Dword 9 5 */ +#define SET_TX_BUFF_DESC_ADDR_LOW_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value) +/* Dword 10 NA */ +#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value) +/* Dword 11 NA */ +/*RESERVED 0 */ +/* Dword 12 6 */ +#define SET_TX_BUFF_DESC_LEN_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value) +#define SET_TX_BUFF_DESC_AMSDU_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value) +/* Dword 13 7 */ +#define SET_TX_BUFF_DESC_ADDR_LOW_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value) +/* Dword 14 NA */ +#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value) +/* Dword 15 NA */ +/*RESERVED 0 */ + + +#endif +/* ----------------------------------------------------------- + * + * Rate + * + * ----------------------------------------------------------- + * CCK Rates, TxHT = 0 */ +#define DESC8192F_RATE1M 0x00 +#define DESC8192F_RATE2M 0x01 +#define DESC8192F_RATE5_5M 0x02 +#define DESC8192F_RATE11M 0x03 + +/* OFDM Rates, TxHT = 0 */ +#define DESC8192F_RATE6M 0x04 +#define DESC8192F_RATE9M 0x05 +#define DESC8192F_RATE12M 0x06 +#define DESC8192F_RATE18M 0x07 +#define DESC8192F_RATE24M 0x08 +#define DESC8192F_RATE36M 0x09 +#define DESC8192F_RATE48M 0x0a +#define DESC8192F_RATE54M 0x0b + +/* MCS Rates, TxHT = 1 */ +#define DESC8192F_RATEMCS0 0x0c +#define DESC8192F_RATEMCS1 0x0d +#define DESC8192F_RATEMCS2 0x0e +#define DESC8192F_RATEMCS3 0x0f +#define DESC8192F_RATEMCS4 0x10 +#define DESC8192F_RATEMCS5 0x11 +#define DESC8192F_RATEMCS6 0x12 +#define DESC8192F_RATEMCS7 0x13 +#define DESC8192F_RATEMCS8 0x14 +#define DESC8192F_RATEMCS9 0x15 +#define DESC8192F_RATEMCS10 0x16 +#define DESC8192F_RATEMCS11 0x17 +#define DESC8192F_RATEMCS12 0x18 +#define DESC8192F_RATEMCS13 0x19 +#define DESC8192F_RATEMCS14 0x1a +#define DESC8192F_RATEMCS15 0x1b +#define DESC8192F_RATEVHTSS1MCS0 0x2c +#define DESC8192F_RATEVHTSS1MCS1 0x2d +#define DESC8192F_RATEVHTSS1MCS2 0x2e +#define DESC8192F_RATEVHTSS1MCS3 0x2f +#define DESC8192F_RATEVHTSS1MCS4 0x30 +#define DESC8192F_RATEVHTSS1MCS5 0x31 +#define DESC8192F_RATEVHTSS1MCS6 0x32 +#define DESC8192F_RATEVHTSS1MCS7 0x33 +#define DESC8192F_RATEVHTSS1MCS8 0x34 +#define DESC8192F_RATEVHTSS1MCS9 0x35 +#define DESC8192F_RATEVHTSS2MCS0 0x36 +#define DESC8192F_RATEVHTSS2MCS1 0x37 +#define DESC8192F_RATEVHTSS2MCS2 0x38 +#define DESC8192F_RATEVHTSS2MCS3 0x39 +#define DESC8192F_RATEVHTSS2MCS4 0x3a +#define DESC8192F_RATEVHTSS2MCS5 0x3b +#define DESC8192F_RATEVHTSS2MCS6 0x3c +#define DESC8192F_RATEVHTSS2MCS7 0x3d +#define DESC8192F_RATEVHTSS2MCS8 0x3e +#define DESC8192F_RATEVHTSS2MCS9 0x3f + + +#define RX_HAL_IS_CCK_RATE_8192F(pDesc)\ + (GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE1M || \ + GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE2M || \ + GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE5_5M || \ + GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE11M) + +#ifdef CONFIG_TRX_BD_ARCH + struct tx_desc; +#endif + +void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc); +void rtl8192f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); +void rtl8192f_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); +void rtl8192f_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); +void rtl8192f_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); +void rtl8192f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); + +#if defined(CONFIG_CONCURRENT_MODE) + void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); +#endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + s32 rtl8192fs_init_xmit_priv(PADAPTER padapter); + void rtl8192fs_free_xmit_priv(PADAPTER padapter); + s32 rtl8192fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); + s32 rtl8192fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); + s32 rtl8192fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); + s32 rtl8192fs_xmit_buf_handler(PADAPTER padapter); + thread_return rtl8192fs_xmit_thread(thread_context context); + #define hal_xmit_handler rtl8192fs_xmit_buf_handler +#endif + +#ifdef CONFIG_USB_HCI + s32 rtl8192fu_init_xmit_priv(PADAPTER padapter); + void rtl8192fu_free_xmit_priv(PADAPTER padapter); + s32 rtl8192fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); + s32 rtl8192fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); + s32 rtl8192fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); + s32 rtl8192fu_xmit_buf_handler(PADAPTER padapter); + #define hal_xmit_handler rtl8192fu_xmit_buf_handler + void rtl8192fu_xmit_tasklet(void *priv); + s32 rtl8192fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); + void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc); +#endif + +#ifdef CONFIG_PCI_HCI + s32 rtl8192fe_init_xmit_priv(PADAPTER padapter); + void rtl8192fe_free_xmit_priv(PADAPTER padapter); + struct xmit_buf *rtl8192fe_dequeue_xmitbuf(struct rtw_tx_ring *ring); + void rtl8192fe_xmitframe_resume(_adapter *padapter); + s32 rtl8192fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); + s32 rtl8192fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); + s32 rtl8192fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); + void rtl8192fe_xmit_tasklet(void *priv); +#endif + +u8 BWMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib); +u8 SCMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib); + +#endif diff --git a/include/rtl8703b_cmd.h b/include/rtl8703b_cmd.h index 0e798f0..dd0439b 100644 --- a/include/rtl8703b_cmd.h +++ b/include/rtl8703b_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_CMD_H__ #define __RTL8703B_CMD_H__ @@ -118,7 +113,6 @@ enum h2c_cmd_8703B { #define SET_8703B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) #define SET_8703B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8703B_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) #define GET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) @@ -182,11 +176,9 @@ enum h2c_cmd_8703B { /* host message to firmware cmd */ void rtl8703b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8703b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); -void rtl8703b_set_rssi_cmd(PADAPTER padapter, u8 *param); void rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8703b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8703b_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); void rtl8703b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST @@ -196,8 +188,6 @@ void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus); void rtl8703b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); - #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW void rtl8703b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); @@ -210,9 +200,6 @@ void CheckFwRsvdPageContent(PADAPTER padapter); void rtl8703b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); -#ifdef CONFIG_TSF_RESET_OFFLOAD - u8 rtl8703b_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ s32 FillH2CCmd8703B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8703B(_adapter *padapter, bool wowlan); #endif diff --git a/include/rtl8703b_dm.h b/include/rtl8703b_dm.h index 4ee834d..912c7da 100644 --- a/include/rtl8703b_dm.h +++ b/include/rtl8703b_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_DM_H__ #define __RTL8703B_DM_H__ /* ************************************************************ @@ -40,8 +35,5 @@ void rtl8703b_deinit_dm_priv(PADAPTER padapter); void rtl8703b_InitHalDm(PADAPTER padapter); void rtl8703b_HalDmWatchDog(PADAPTER padapter); -void rtl8703b_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8703b_hal_dm_in_lps(PADAPTER padapter); - #endif diff --git a/include/rtl8703b_hal.h b/include/rtl8703b_hal.h index 432ba27..f75cc30 100644 --- a/include/rtl8703b_hal.h +++ b/include/rtl8703b_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_HAL_H__ #define __RTL8703B_HAL_H__ @@ -111,23 +106,17 @@ typedef struct _RT_8703B_FIRMWARE_HDR { /* Note: We will divide number of page equally for each queue other than public queue! */ /* For General Reserved Page Number(Beacon Queue is reserved page) - * Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */ -#define BCNQ_PAGE_NUM_8703B 0x08 -#ifdef CONFIG_CONCURRENT_MODE - #define BCNQ1_PAGE_NUM_8703B 0x08 /* 0x04 */ -#else - #define BCNQ1_PAGE_NUM_8703B 0x00 -#endif + * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8703B + * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/ -#ifdef CONFIG_PNO_SUPPORT - #undef BCNQ1_PAGE_NUM_8703B - #define BCNQ1_PAGE_NUM_8703B 0x00 /* 0x04 */ -#endif +#define BCNQ_PAGE_NUM_8703B (MAX_BEACON_LEN/PAGE_SIZE_TX_8703B + 6) /*0x08*/ /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1 PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1 PNO: 6 + * NS offload: 2NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8703B 0x08 + #define WOWLAN_PAGE_NUM_8703B 0x0b #else #define WOWLAN_PAGE_NUM_8703B 0x00 #endif @@ -141,7 +130,7 @@ typedef struct _RT_8703B_FIRMWARE_HDR { #define AP_WOWLAN_PAGE_NUM_8703B 0x02 #endif -#define TX_TOTAL_PAGE_NUMBER_8703B (0xFF - BCNQ_PAGE_NUM_8703B - BCNQ1_PAGE_NUM_8703B - WOWLAN_PAGE_NUM_8703B) +#define TX_TOTAL_PAGE_NUMBER_8703B (0xFF - BCNQ_PAGE_NUM_8703B - WOWLAN_PAGE_NUM_8703B) #define TX_PAGE_BOUNDARY_8703B (TX_TOTAL_PAGE_NUMBER_8703B + 1) #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B TX_TOTAL_PAGE_NUMBER_8703B @@ -230,7 +219,7 @@ VOID Hal_EfuseParseBoardType_8703B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN Au void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8703b(_adapter *adapter); -void SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val); u8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); diff --git a/include/rtl8703b_led.h b/include/rtl8703b_led.h index fb11fdd..99e590d 100644 --- a/include/rtl8703b_led.h +++ b/include/rtl8703b_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_LED_H__ #define __RTL8703B_LED_H__ @@ -24,7 +19,7 @@ #include #include - +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -45,4 +40,5 @@ void rtl8703be_DeInitSwLeds(PADAPTER padapter); #endif -#endif +#endif/*CONFIG_RTW_SW_LED*/ +#endif /*__RTL8703B_LED_H__*/ diff --git a/include/rtl8703b_recv.h b/include/rtl8703b_recv.h index 4c82652..e796e6e 100644 --- a/include/rtl8703b_recv.h +++ b/include/rtl8703b_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_RECV_H__ #define __RTL8703B_RECV_H__ diff --git a/include/rtl8703b_rf.h b/include/rtl8703b_rf.h index 0d3d0aa..8d980a8 100644 --- a/include/rtl8703b_rf.h +++ b/include/rtl8703b_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_RF_H__ #define __RTL8703B_RF_H__ @@ -25,6 +20,6 @@ int PHY_RF6052_Config8703B(IN PADAPTER Adapter); VOID PHY_RF6052SetBandwidth8703B( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); #endif diff --git a/include/rtl8703b_spec.h b/include/rtl8703b_spec.h index e9a13d2..633b23b 100644 --- a/include/rtl8703b_spec.h +++ b/include/rtl8703b_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_SPEC_H__ #define __RTL8703B_SPEC_H__ diff --git a/include/rtl8703b_sreset.h b/include/rtl8703b_sreset.h index fbed1fb..5fe53cf 100644 --- a/include/rtl8703b_sreset.h +++ b/include/rtl8703b_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8703B_SRESET_H_ #define _RTL8703B_SRESET_H_ diff --git a/include/rtl8703b_xmit.h b/include/rtl8703b_xmit.h index c44609c..40c7bb2 100644 --- a/include/rtl8703b_xmit.h +++ b/include/rtl8703b_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8703B_XMIT_H__ #define __RTL8703B_XMIT_H__ @@ -189,13 +184,14 @@ #define SET_TX_DESC_ANTSEL_D_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) /* Dword 7 */ - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + #ifdef CONFIG_PCI_HCI #define SET_TX_DESC_TX_BUFFER_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) - #else + #endif /*CONFIG_PCI_HCI*/ + #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) #define SET_TX_DESC_TX_DESC_CHECKSUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) #endif #define SET_TX_DESC_USB_TXAGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) - #if (DEV_BUS_TYPE == RT_SDIO_INTERFACE) + #ifdef CONFIG_SDIO_HCI #define SET_TX_DESC_SDIO_TXSEQ_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) #endif @@ -293,6 +289,7 @@ void rtl8703b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 I #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) s32 rtl8703bs_init_xmit_priv(PADAPTER padapter); diff --git a/include/rtl8710b_cmd.h b/include/rtl8710b_cmd.h new file mode 100644 index 0000000..8b2e8fa --- /dev/null +++ b/include/rtl8710b_cmd.h @@ -0,0 +1,175 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8710B_CMD_H__ +#define __RTL8710B_CMD_H__ + +/* --------------------------------------------------------------------------------------------------------- + * ---------------------------------- H2C CMD DEFINITION ------------------------------------------------ + * --------------------------------------------------------------------------------------------------------- */ + +enum h2c_cmd_8710B { + /* Common Class: 000 */ + H2C_8710B_RSVD_PAGE = 0x00, + H2C_8710B_MEDIA_STATUS_RPT = 0x01, + H2C_8710B_SCAN_ENABLE = 0x02, + H2C_8710B_KEEP_ALIVE = 0x03, + H2C_8710B_DISCON_DECISION = 0x04, + H2C_8710B_PSD_OFFLOAD = 0x05, + H2C_8710B_AP_OFFLOAD = 0x08, + H2C_8710B_BCN_RSVDPAGE = 0x09, + H2C_8710B_PROBERSP_RSVDPAGE = 0x0A, + H2C_8710B_FCS_RSVDPAGE = 0x10, + H2C_8710B_FCS_INFO = 0x11, + H2C_8710B_AP_WOW_GPIO_CTRL = 0x13, + + /* PoweSave Class: 001 */ + H2C_8710B_SET_PWR_MODE = 0x20, + H2C_8710B_PS_TUNING_PARA = 0x21, + H2C_8710B_PS_TUNING_PARA2 = 0x22, + H2C_8710B_P2P_LPS_PARAM = 0x23, + H2C_8710B_P2P_PS_OFFLOAD = 0x24, + H2C_8710B_PS_SCAN_ENABLE = 0x25, + H2C_8710B_SAP_PS_ = 0x26, + H2C_8710B_INACTIVE_PS_ = 0x27, /* Inactive_PS */ + H2C_8710B_FWLPS_IN_IPS_ = 0x28, + + /* Dynamic Mechanism Class: 010 */ + H2C_8710B_MACID_CFG = 0x40, + H2C_8710B_TXBF = 0x41, + H2C_8710B_RSSI_SETTING = 0x42, + H2C_8710B_AP_REQ_TXRPT = 0x43, + H2C_8710B_INIT_RATE_COLLECT = 0x44, + H2C_8710B_RA_PARA_ADJUST = 0x46, + + /* WOWLAN Class: 100 */ + H2C_8710B_WOWLAN = 0x80, + H2C_8710B_REMOTE_WAKE_CTRL = 0x81, + H2C_8710B_AOAC_GLOBAL_INFO = 0x82, + H2C_8710B_AOAC_RSVD_PAGE = 0x83, + H2C_8710B_AOAC_RSVD_PAGE2 = 0x84, + H2C_8710B_D0_SCAN_OFFLOAD_CTRL = 0x85, + H2C_8710B_D0_SCAN_OFFLOAD_INFO = 0x86, + H2C_8710B_CHNL_SWITCH_OFFLOAD = 0x87, + H2C_8710B_P2P_OFFLOAD_RSVD_PAGE = 0x8A, + H2C_8710B_P2P_OFFLOAD = 0x8B, + + H2C_8710B_RESET_TSF = 0xC0, + H2C_8710B_MAXID, +}; + +/* --------------------------------------------------------------------------------------------------------- + * ---------------------------------- H2C CMD CONTENT -------------------------------------------------- + * --------------------------------------------------------------------------------------------------------- + * _RSVDPAGE_LOC_CMD_0x00 */ +#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8710B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8710B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8710B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) + +/* _PWR_MOD_CMD_0x20 */ +#define SET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8710B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) +#define SET_8710B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) +#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8710B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) +#define SET_8710B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) + +#define GET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) + +/* _PS_TUNE_PARAM_CMD_0x21 */ +#define SET_8710B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8710B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value) +#define SET_8710B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value) +#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) + +/* _MACID_CFG_CMD_0x40 */ +#define SET_8710B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8710B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value) +#define SET_8710B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value) +#define SET_8710B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value) +#define SET_8710B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value) +#define SET_8710B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value) +#define SET_8710B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value) +#define SET_8710B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value) +#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) +#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) +#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value) +#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value) + +/* _RSSI_SETTING_CMD_0x42 */ +#define SET_8710B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8710B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value) +#define SET_8710B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) + +/* _AP_REQ_TXRPT_CMD_0x43 */ +#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) + +/* _FORCE_BT_TXPWR_CMD_0x62 */ +#define SET_8710B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) + +/* _FORCE_BT_MP_OPER_CMD_0x67 */ +#define SET_8710B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_8710B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) +#define SET_8710B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8710B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) +#define SET_8710B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) +#define SET_8710B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) + +/* _BT_FW_PATCH_0x6A */ +#define SET_8710B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value) +#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) + +/* --------------------------------------------------------------------------------------------------------- + * ------------------------------------------- Structure -------------------------------------------------- + * --------------------------------------------------------------------------------------------------------- */ + + +/* --------------------------------------------------------------------------------------------------------- + * ---------------------------------- Function Statement -------------------------------------------------- + * --------------------------------------------------------------------------------------------------------- */ + +/* host message to firmware cmd */ +void rtl8710b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); +void rtl8710b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); +/* s32 rtl8710b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ +void rtl8710b_set_FwPsTuneParam_cmd(PADAPTER padapter); +void rtl8710b_download_rsvd_page(PADAPTER padapter, u8 mstatus); +#ifdef CONFIG_BT_COEXIST + void rtl8710b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); +#endif /* CONFIG_BT_COEXIST */ +#ifdef CONFIG_P2P + void rtl8710b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); +#endif /* CONFIG_P2P */ + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW +void rtl8710b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); +#endif +#endif + +#ifdef CONFIG_P2P_WOWLAN + void rtl8710b_set_p2p_wowlan_offload_cmd(PADAPTER padapter); +#endif + +s32 FillH2CCmd8710B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); +u8 GetTxBufferRsvdPageNum8710B(_adapter *padapter, bool wowlan); +#endif diff --git a/include/rtl8710b_dm.h b/include/rtl8710b_dm.h new file mode 100644 index 0000000..9a131ba --- /dev/null +++ b/include/rtl8710b_dm.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8710B_DM_H__ +#define __RTL8710B_DM_H__ +/* ************************************************************ + * Description: + * + * This file is for 8710B dynamic mechanism only + * + * + * ************************************************************ */ + +/* ************************************************************ + * structure and define + * ************************************************************ */ + +/* ************************************************************ + * function prototype + * ************************************************************ */ + +void rtl8710b_init_dm_priv(PADAPTER padapter); +void rtl8710b_deinit_dm_priv(PADAPTER padapter); + +void rtl8710b_InitHalDm(PADAPTER padapter); +void rtl8710b_HalDmWatchDog(PADAPTER padapter); + +#endif diff --git a/include/rtl8710b_hal.h b/include/rtl8710b_hal.h new file mode 100644 index 0000000..b01dab0 --- /dev/null +++ b/include/rtl8710b_hal.h @@ -0,0 +1,277 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8710B_HAL_H__ +#define __RTL8710B_HAL_H__ + +#include "hal_data.h" + +#include "rtl8710b_spec.h" +#include "rtl8710b_rf.h" +#include "rtl8710b_dm.h" +#include "rtl8710b_recv.h" +#include "rtl8710b_xmit.h" +#include "rtl8710b_cmd.h" +#include "rtl8710b_led.h" +#include "Hal8710BPwrSeq.h" +#include "Hal8710BPhyReg.h" +#include "Hal8710BPhyCfg.h" +#ifdef DBG_CONFIG_ERROR_DETECT + #include "rtl8710b_sreset.h" +#endif +#ifdef CONFIG_LPS_POFF + #include "rtl8710b_lps_poff.h" +#endif + +#define FW_8710B_SIZE 0x8000 +#define FW_8710B_START_ADDRESS 0x1000 +#define FW_8710B_END_ADDRESS 0x1FFF /* 0x5FFF */ + +typedef struct _RT_FIRMWARE { + FIRMWARE_SOURCE eFWSource; +#ifdef CONFIG_EMBEDDED_FWIMG + u8 *szFwBuffer; +#else + u8 szFwBuffer[FW_8710B_SIZE]; +#endif + u32 ulFwLength; +} RT_FIRMWARE_8710B, *PRT_FIRMWARE_8710B; + +/* + * This structure must be cared byte-ordering + * + * Added by tynli. 2009.12.04. */ +typedef struct _RT_8710B_FIRMWARE_HDR { + /* 8-byte alinment required */ + + /* --- LONG WORD 0 ---- */ + u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */ + u8 Category; /* AP/NIC and USB/PCI */ + u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ + u16 Version; /* FW Version */ + u16 Subversion; /* FW Subversion, default 0x00 */ + + /* --- LONG WORD 1 ---- */ + u8 Month; /* Release time Month field */ + u8 Date; /* Release time Date field */ + u8 Hour; /* Release time Hour field */ + u8 Minute; /* Release time Minute field */ + u16 RamCodeSize; /* The size of RAM code */ + u16 Rsvd2; + + /* --- LONG WORD 2 ---- */ + u32 SvnIdx; /* The SVN entry index */ + u32 Rsvd3; + + /* --- LONG WORD 3 ---- */ + u32 Rsvd4; + u32 Rsvd5; +} RT_8710B_FIRMWARE_HDR, *PRT_8710B_FIRMWARE_HDR; + +#define DRIVER_EARLY_INT_TIME_8710B 0x05 +#define BCN_DMA_ATIME_INT_TIME_8710B 0x02 + +/* for 8710B + * TX 32K, RX 16K, Page size 128B for TX, 8B for RX */ +#define PAGE_SIZE_TX_8710B 128 +#define PAGE_SIZE_RX_8710B 8 + +#define TX_DMA_SIZE_8710B 0x8000 /* 32K(TX) */ +#define RX_DMA_SIZE_8710B 0x4000 /* 16K(RX) */ + +#ifdef CONFIG_WOWLAN + #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ +#else + #define RESV_FMWF 0 +#endif + +#ifdef CONFIG_FW_C2H_DEBUG + #define RX_DMA_RESERVED_SIZE_8710B 0x100 /* 256B, reserved for c2h debug message */ +#else + #define RX_DMA_RESERVED_SIZE_8710B 0x80 /* 128B, reserved for tx report */ +#endif +#define RX_DMA_BOUNDARY_8710B\ + (RX_DMA_SIZE_8710B - RX_DMA_RESERVED_SIZE_8710B - 1) + + +/* Note: We will divide number of page equally for each queue other than public queue! */ + +/* For General Reserved Page Number(Beacon Queue is reserved page) + * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8710B + * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/ +#define BCNQ_PAGE_NUM_8710B (MAX_BEACON_LEN/PAGE_SIZE_TX_8710B + 6) /*0x08*/ + + +/* For WoWLan , more reserved page + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6 + * NS offload: 2 NDP info: 1 + */ +#ifdef CONFIG_WOWLAN + #define WOWLAN_PAGE_NUM_8710B 0x0b +#else + #define WOWLAN_PAGE_NUM_8710B 0x00 +#endif + +#ifdef CONFIG_PNO_SUPPORT + #undef WOWLAN_PAGE_NUM_8710B + #define WOWLAN_PAGE_NUM_8710B 0x15 +#endif + +#ifdef CONFIG_AP_WOWLAN + #define AP_WOWLAN_PAGE_NUM_8710B 0x02 +#endif + +#define TX_TOTAL_PAGE_NUMBER_8710B\ + (0xFF - BCNQ_PAGE_NUM_8710B -WOWLAN_PAGE_NUM_8710B) +#define TX_PAGE_BOUNDARY_8710B (TX_TOTAL_PAGE_NUMBER_8710B + 1) + +#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B TX_TOTAL_PAGE_NUMBER_8710B +#define WMM_NORMAL_TX_PAGE_BOUNDARY_8710B\ + (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B + 1) + +/* For Normal Chip Setting + * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8710B */ +#define NORMAL_PAGE_NUM_HPQ_8710B 0x0C +#define NORMAL_PAGE_NUM_LPQ_8710B 0x02 +#define NORMAL_PAGE_NUM_NPQ_8710B 0x02 +#define NORMAL_PAGE_NUM_EPQ_8710B 0x04 + +/* Note: For Normal Chip Setting, modify later */ +#define WMM_NORMAL_PAGE_NUM_HPQ_8710B 0x30 +#define WMM_NORMAL_PAGE_NUM_LPQ_8710B 0x20 +#define WMM_NORMAL_PAGE_NUM_NPQ_8710B 0x20 +#define WMM_NORMAL_PAGE_NUM_EPQ_8710B 0x00 + + +#include "HalVerDef.h" +#include "hal_com.h" + +#define EFUSE_OOB_PROTECT_BYTES (96 + 1) + +#define HAL_EFUSE_MEMORY +#define HWSET_MAX_SIZE_8710B 512 +#define EFUSE_REAL_CONTENT_LEN_8710B 512 +#define EFUSE_MAP_LEN_8710B 512 +#define EFUSE_MAX_SECTION_8710B 64 + +/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/ +#define EFUSE_IC_ID_OFFSET 506 +#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8710B) + +#define EFUSE_ACCESS_ON 0x69 +#define EFUSE_ACCESS_OFF 0x00 + +#define PACKAGE_QFN32_S 0 +#define PACKAGE_QFN48M_S 1 //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xFE +#define PACKAGE_QFN48_S 2 +#define PACKAGE_QFN64_S 3 +#define PACKAGE_QFN32_U 4 +#define PACKAGE_QFN48M_U 5 //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xEE +#define PACKAGE_QFN48_U 6 +#define PACKAGE_QFN68_U 7 + +typedef enum _PACKAGE_TYPE_E +{ + PACKAGE_DEFAULT, + PACKAGE_QFN68, + PACKAGE_TFBGA90, + PACKAGE_TFBGA80, + PACKAGE_TFBGA79 +}PACKAGE_TYPE_E; + +#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \ + (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) + +#ifdef CONFIG_FILE_FWIMG + extern char *rtw_fw_file_path; + extern char *rtw_fw_wow_file_path; + #ifdef CONFIG_MP_INCLUDED + extern char *rtw_fw_mp_bt_file_path; + #endif /* CONFIG_MP_INCLUDED */ +#endif /* CONFIG_FILE_FWIMG */ + +/* rtl8710b_hal_init.c */ +s32 rtl8710b_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw); +void rtl8710b_FirmwareSelfReset(PADAPTER padapter); +void rtl8710b_InitializeFirmwareVars(PADAPTER padapter); + +void rtl8710b_InitAntenna_Selection(PADAPTER padapter); +void rtl8710b_DeinitAntenna_Selection(PADAPTER padapter); +void rtl8710b_CheckAntenna_Selection(PADAPTER padapter); +void rtl8710b_init_default_value(PADAPTER padapter); + + +u32 indirect_read32_8710b(PADAPTER padapter, u32 regaddr); +VOID indirect_write32_8710b(PADAPTER padapter, u32 regaddr, u32 data); +u32 hal_query_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask); +VOID hal_set_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask, u32 data); +#define HAL_SetSYSOnReg hal_set_syson_reg_8710b + + +/* EFuse */ +u8 GetEEPROMSize8710B(PADAPTER padapter); + +#if 0 +void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent); +void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo); +void Hal_EfuseParseTxPowerInfo_8710B(PADAPTER padapter, + u8 *PROMContent, BOOLEAN AutoLoadFail); +void Hal_EfuseParseEEPROMVer_8710B(PADAPTER padapter, + u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParsePackageType_8710B(PADAPTER pAdapter, + u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseChnlPlan_8710B(PADAPTER padapter, + u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseCustomerID_8710B(PADAPTER padapter, + u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseAntennaDiversity_8710B(PADAPTER padapter, + u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseXtal_8710B(PADAPTER pAdapter, + u8 *hwinfo, u8 AutoLoadFail); +void Hal_EfuseParseThermalMeter_8710B(PADAPTER padapter, + u8 *hwinfo, u8 AutoLoadFail); +VOID Hal_EfuseParseBoardType_8710B(PADAPTER Adapter, + u8 *PROMContent, BOOLEAN AutoloadFail); +#endif + +void rtl8710b_set_hal_ops(struct hal_ops *pHalFunc); +void init_hal_spec_8710b(_adapter *adapter); +u8 SetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val); +void GetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); +u8 GetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); + +/* register */ +void rtl8710b_InitBeaconParameters(PADAPTER padapter); +void rtl8710b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); +void _8051Reset8710(PADAPTER padapter); + +void rtl8710b_start_thread(_adapter *padapter); +void rtl8710b_stop_thread(_adapter *padapter); + +#ifdef CONFIG_GPIO_WAKEUP + void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); +#endif + +void CCX_FwC2HTxRpt_8710b(PADAPTER padapter, u8 *pdata, u8 len); + +u8 MRateToHwRate8710B(u8 rate); +u8 HwRateToMRate8710B(u8 rate); + +#ifdef CONFIG_USB_HCI + void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc); +#endif + + +#endif diff --git a/include/rtl8710b_led.h b/include/rtl8710b_led.h new file mode 100644 index 0000000..8ca346d --- /dev/null +++ b/include/rtl8710b_led.h @@ -0,0 +1,44 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8710B_LED_H__ +#define __RTL8710B_LED_H__ + +#include +#include +#include + +#ifdef CONFIG_RTW_SW_LED +/* ******************************************************************************** + * Interface to manipulate LED objects. + * ******************************************************************************** */ +#ifdef CONFIG_USB_HCI + void rtl8710bu_InitSwLeds(PADAPTER padapter); + void rtl8710bu_DeInitSwLeds(PADAPTER padapter); +#endif +#ifdef CONFIG_SDIO_HCI + void rtl8710bs_InitSwLeds(PADAPTER padapter); + void rtl8710bs_DeInitSwLeds(PADAPTER padapter); +#endif +#ifdef CONFIG_GSPI_HCI + void rtl8710bs_InitSwLeds(PADAPTER padapter); + void rtl8710bs_DeInitSwLeds(PADAPTER padapter); +#endif +#ifdef CONFIG_PCI_HCI + void rtl8710be_InitSwLeds(PADAPTER padapter); + void rtl8710be_DeInitSwLeds(PADAPTER padapter); +#endif + +#endif /*#ifdef CONFIG_RTW_SW_LED*/ +#endif diff --git a/include/rtl8710b_lps_poff.h b/include/rtl8710b_lps_poff.h new file mode 100644 index 0000000..ea9c60e --- /dev/null +++ b/include/rtl8710b_lps_poff.h @@ -0,0 +1,56 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/******************************************** CONST ************************/ +#define NUM_OF_REGISTER_BANK 13 +#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64) +#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8) +#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE) +#define LPS_POFF_DYNAMIC_FILE_LEN (512 + TXDESC_SIZE) +/******************************************** CONST ************************/ + +/******************************************** MACRO ************************/ +/* HOIE Entry Definition */ +#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \ + SET_BITS_TO_LE_4BYTE((__pHOIE), 0, 16, __Value) +#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \ + SET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value) +#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \ + SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value) +#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \ + SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value) +#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \ + SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value) +#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \ + SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value) +#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \ + SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value) +#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \ + SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value) +#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \ + SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value) +#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \ + SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value) +#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \ + SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value) + +/*********************Function Definition*******************************************/ +void rtl8710b_lps_poff_init(PADAPTER padapter); +void rtl8710b_lps_poff_deinit(PADAPTER padapter); +bool rtl8710b_lps_poff_get_txbndy_status(PADAPTER padapter); +void rtl8710b_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable); +void rtl8710b_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS); +bool rtl8710b_lps_poff_get_status(PADAPTER padapter); +void rtl8710b_lps_poff_wow(PADAPTER padapter); diff --git a/include/rtl8710b_recv.h b/include/rtl8710b_recv.h new file mode 100644 index 0000000..f99c331 --- /dev/null +++ b/include/rtl8710b_recv.h @@ -0,0 +1,85 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8710B_RECV_H__ +#define __RTL8710B_RECV_H__ + +#define RECV_BLK_SZ 512 +#define RECV_BLK_CNT 16 +#define RECV_BLK_TH RECV_BLK_CNT + +#if defined(CONFIG_USB_HCI) + #ifndef MAX_RECVBUF_SZ + #ifdef PLATFORM_OS_CE + #define MAX_RECVBUF_SZ (8192+1024) /* 8K+1k */ + #else + #ifdef CONFIG_MINIMAL_MEMORY_USAGE + #define MAX_RECVBUF_SZ (4000) /* about 4K */ + #else + #ifdef CONFIG_PLATFORM_MSTAR + #define MAX_RECVBUF_SZ (8192) /* 8K */ + #elif defined(CONFIG_PLATFORM_HISILICON) + #define MAX_RECVBUF_SZ (16384) /* 16k */ + #else + #define MAX_RECVBUF_SZ (15360) /* 15k < 16k */ + /* #define MAX_RECVBUF_SZ (32768) */ /* 32k */ + /* #define MAX_RECVBUF_SZ (20480) */ /* 20K */ + /* #define MAX_RECVBUF_SZ (10240) */ /* 10K */ + /* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */ + #endif + #endif + #endif + #endif /* !MAX_RECVBUF_SZ */ +#endif + +/* Rx smooth factor */ +#define Rx_Smooth_Factor (20) + +/*-----------------------------------------------------------------*/ +/* RTL8710B RX BUFFER DESC */ +/*-----------------------------------------------------------------*/ +/*DWORD 0*/ +#define SET_RX_BUFFER_DESC_DATA_LENGTH_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) +#define SET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value) +#define SET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value) +#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value) + +#define GET_RX_BUFFER_DESC_OWN_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) +#define GET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) +#define GET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1) +#ifdef USING_RX_TAG + #define GET_RX_BUFFER_DESC_RX_TAG_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13) +#else + #define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15) +#endif + +/*DWORD 1*/ +#define SET_RX_BUFFER_PHYSICAL_LOW_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value) + +/*DWORD 2*/ +#ifdef CONFIG_64BIT_DMA + #define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value) +#else + #define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value) +#endif + +#ifdef CONFIG_USB_HCI + int rtl8710bu_init_recv_priv(_adapter *padapter); + void rtl8710bu_free_recv_priv(_adapter *padapter); + void rtl8710bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); +#endif + +void rtl8710b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); + +#endif /* __RTL8710B_RECV_H__ */ diff --git a/include/rtl8710b_rf.h b/include/rtl8710b_rf.h new file mode 100644 index 0000000..2f176e6 --- /dev/null +++ b/include/rtl8710b_rf.h @@ -0,0 +1,20 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8710B_RF_H__ +#define __RTL8710B_RF_H__ + +int PHY_RF6052_Config8710B(IN PADAPTER pdapter); + +#endif diff --git a/include/rtl8710b_spec.h b/include/rtl8710b_spec.h new file mode 100644 index 0000000..309c3ee --- /dev/null +++ b/include/rtl8710b_spec.h @@ -0,0 +1,481 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8710B_SPEC_H__ +#define __RTL8710B_SPEC_H__ + +#include + + +#define HAL_NAV_UPPER_UNIT_8710B 128 /* micro-second */ + +/* ----------------------------------------------------- + * + * 0x0000h ~ 0x00FFh System Configuration + * + * ----------------------------------------------------- */ +#define REG_SYS_ISO_CTRL_8710B 0x0000 /* 2 Byte */ +#define REG_APS_FSMCO_8710B 0x0004 /* 4 Byte */ +#define REG_SYS_CLKR_8710B 0x0008 /* 2 Byte */ +#define REG_9346CR_8710B 0x000A /* 2 Byte */ +#define REG_EE_VPD_8710B 0x000C /* 2 Byte */ +#define REG_AFE_MISC_8710B 0x0010 /* 1 Byte */ +#define REG_SPS0_CTRL_8710B 0x0011 /* 7 Byte */ +#define REG_SPS_OCP_CFG_8710B 0x0018 /* 4 Byte */ +#define REG_RSV_CTRL_8710B 0x001C /* 3 Byte */ +#define REG_RF_CTRL_8710B 0x001F /* 1 Byte */ +#define REG_LPLDO_CTRL_8710B 0x0023 /* 1 Byte */ +#define REG_AFE_XTAL_CTRL_8710B 0x0024 /* 4 Byte */ +#define REG_AFE_PLL_CTRL_8710B 0x0028 /* 4 Byte */ +#define REG_MAC_PLL_CTRL_EXT_8710B 0x002c /* 4 Byte */ +#define REG_EFUSE_CTRL_8710B 0x0030 +#define REG_EFUSE_TEST_8710B 0x0034 +#define REG_PWR_DATA_8710B 0x0038 +#define REG_CAL_TIMER_8710B 0x003C +#define REG_ACLK_MON_8710B 0x003E +#define REG_GPIO_MUXCFG_8710B 0x0040 +#define REG_GPIO_IO_SEL_8710B 0x0042 +#define REG_MAC_PINMUX_CFG_8710B 0x0043 +#define REG_GPIO_PIN_CTRL_8710B 0x0044 +#define REG_GPIO_INTM_8710B 0x0048 +#define REG_LEDCFG0_8710B 0x004C +#define REG_LEDCFG1_8710B 0x004D +#define REG_LEDCFG2_8710B 0x004E +#define REG_LEDCFG3_8710B 0x004F +#define REG_FSIMR_8710B 0x0050 +#define REG_FSISR_8710B 0x0054 +#define REG_HSIMR_8710B 0x0058 +#define REG_HSISR_8710B 0x005c +#define REG_GPIO_EXT_CTRL 0x0060 +#define REG_PAD_CTRL1_8710B 0x0064 +#define REG_MULTI_FUNC_CTRL_8710B 0x0068 +#define REG_GPIO_STATUS_8710B 0x006C +#define REG_SDIO_CTRL_8710B 0x0070 +#define REG_OPT_CTRL_8710B 0x0074 +#define REG_AFE_CTRL_4_8710B 0x0078 +#define REG_MCUFWDL_8710B 0x0080 +#define REG_8051FW_CTRL_8710B 0x0080 +#define REG_HMEBOX_DBG_0_8710B 0x0088 +#define REG_HMEBOX_DBG_1_8710B 0x008A +#define REG_HMEBOX_DBG_2_8710B 0x008C +#define REG_HMEBOX_DBG_3_8710B 0x008E +#define REG_WLLPS_CTRL 0x0090 + +#define REG_PMC_DBG_CTRL2_8710B 0x00CC +#define REG_EFUSE_BURN_GNT_8710B 0x00CF +#define REG_HPON_FSM_8710B 0x00EC +#define REG_SYS_CFG1_8710B 0x00F0 +#define REG_SYS_CFG_8710B 0x00FC +#define REG_ROM_VERSION 0x00FD + +/* ----------------------------------------------------- + * + * 0x0100h ~ 0x01FFh MACTOP General Configuration + * + * ----------------------------------------------------- */ +#define REG_C2HEVT_CMD_ID_8710B 0x01A0 +#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 +#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 +#define REG_C2HEVT_CMD_LEN_8710B 0x01AE +#define REG_C2HEVT_CLEAR_8710B 0x01AF +#define REG_MCUTST_1_8710B 0x01C0 +#define REG_WOWLAN_WAKE_REASON 0x01C7 +#define REG_FMETHR_8710B 0x01C8 +#define REG_HMETFR_8710B 0x01CC +#define REG_HMEBOX_0_8710B 0x01D0 +#define REG_HMEBOX_1_8710B 0x01D4 +#define REG_HMEBOX_2_8710B 0x01D8 +#define REG_HMEBOX_3_8710B 0x01DC +#define REG_LLT_INIT_8710B 0x01E0 +#define REG_HMEBOX_EXT0_8710B 0x01F0 +#define REG_HMEBOX_EXT1_8710B 0x01F4 +#define REG_HMEBOX_EXT2_8710B 0x01F8 +#define REG_HMEBOX_EXT3_8710B 0x01FC + +/* ----------------------------------------------------- + * + * 0x0200h ~ 0x027Fh TXDMA Configuration + * + * ----------------------------------------------------- */ +#define REG_RQPN_8710B 0x0200 +#define REG_FIFOPAGE_8710B 0x0204 +#define REG_DWBCN0_CTRL_8710B REG_TDECTRL +#define REG_TXDMA_OFFSET_CHK_8710B 0x020C +#define REG_TXDMA_STATUS_8710B 0x0210 +#define REG_RQPN_NPQ_8710B 0x0214 +#define REG_DWBCN1_CTRL_8710B 0x0228 + + +/* ----------------------------------------------------- + * + * 0x0280h ~ 0x02FFh RXDMA Configuration + * + * ----------------------------------------------------- */ +#define REG_RXDMA_AGG_PG_TH_8710B 0x0280 +#define REG_FW_UPD_RDPTR_8710B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ +#define REG_RXDMA_CONTROL_8710B 0x0286 /* Control the RX DMA. */ +#define REG_RXDMA_STATUS_8710B 0x0288 +#define REG_RXDMA_MODE_CTRL_8710B 0x0290 +#define REG_EARLY_MODE_CONTROL_8710B 0x02BC +#define REG_RSVD5_8710B 0x02F0 +#define REG_RSVD6_8710B 0x02F4 + +/* ----------------------------------------------------- + * + * 0x0300h ~ 0x03FFh PCIe + * + * ----------------------------------------------------- */ +#define REG_PCIE_CTRL_REG_8710B 0x0300 +#define REG_INT_MIG_8710B 0x0304 /* Interrupt Migration */ +#define REG_BCNQ_TXBD_DESA_8710B 0x0308 /* TX Beacon Descriptor Address */ +#define REG_MGQ_TXBD_DESA_8710B 0x0310 /* TX Manage Queue Descriptor Address */ +#define REG_VOQ_TXBD_DESA_8710B 0x0318 /* TX VO Queue Descriptor Address */ +#define REG_VIQ_TXBD_DESA_8710B 0x0320 /* TX VI Queue Descriptor Address */ +#define REG_BEQ_TXBD_DESA_8710B 0x0328 /* TX BE Queue Descriptor Address */ +#define REG_BKQ_TXBD_DESA_8710B 0x0330 /* TX BK Queue Descriptor Address */ +#define REG_RXQ_RXBD_DESA_8710B 0x0338 /* RX Queue Descriptor Address */ +#define REG_HI0Q_TXBD_DESA_8710B 0x0340 +#define REG_HI1Q_TXBD_DESA_8710B 0x0348 +#define REG_HI2Q_TXBD_DESA_8710B 0x0350 +#define REG_HI3Q_TXBD_DESA_8710B 0x0358 +#define REG_HI4Q_TXBD_DESA_8710B 0x0360 +#define REG_HI5Q_TXBD_DESA_8710B 0x0368 +#define REG_HI6Q_TXBD_DESA_8710B 0x0370 +#define REG_HI7Q_TXBD_DESA_8710B 0x0378 +#define REG_MGQ_TXBD_NUM_8710B 0x0380 +#define REG_RX_RXBD_NUM_8710B 0x0382 +#define REG_VOQ_TXBD_NUM_8710B 0x0384 +#define REG_VIQ_TXBD_NUM_8710B 0x0386 +#define REG_BEQ_TXBD_NUM_8710B 0x0388 +#define REG_BKQ_TXBD_NUM_8710B 0x038A +#define REG_HI0Q_TXBD_NUM_8710B 0x038C +#define REG_HI1Q_TXBD_NUM_8710B 0x038E +#define REG_HI2Q_TXBD_NUM_8710B 0x0390 +#define REG_HI3Q_TXBD_NUM_8710B 0x0392 +#define REG_HI4Q_TXBD_NUM_8710B 0x0394 +#define REG_HI5Q_TXBD_NUM_8710B 0x0396 +#define REG_HI6Q_TXBD_NUM_8710B 0x0398 +#define REG_HI7Q_TXBD_NUM_8710B 0x039A +#define REG_TSFTIMER_HCI_8710B 0x039C +#define REG_BD_RW_PTR_CLR_8710B 0x039C + +/* Read Write Point */ +#define REG_VOQ_TXBD_IDX_8710B 0x03A0 +#define REG_VIQ_TXBD_IDX_8710B 0x03A4 +#define REG_BEQ_TXBD_IDX_8710B 0x03A8 +#define REG_BKQ_TXBD_IDX_8710B 0x03AC +#define REG_MGQ_TXBD_IDX_8710B 0x03B0 +#define REG_RXQ_TXBD_IDX_8710B 0x03B4 +#define REG_HI0Q_TXBD_IDX_8710B 0x03B8 +#define REG_HI1Q_TXBD_IDX_8710B 0x03BC +#define REG_HI2Q_TXBD_IDX_8710B 0x03C0 +#define REG_HI3Q_TXBD_IDX_8710B 0x03C4 +#define REG_HI4Q_TXBD_IDX_8710B 0x03C8 +#define REG_HI5Q_TXBD_IDX_8710B 0x03CC +#define REG_HI6Q_TXBD_IDX_8710B 0x03D0 +#define REG_HI7Q_TXBD_IDX_8710B 0x03D4 + +#define REG_PCIE_HCPWM_8710BE 0x03D8 /* ?????? */ +#define REG_PCIE_HRPWM_8710BE 0x03DC /* PCIe RPWM ?????? */ +#define REG_DBI_WDATA_V1_8710B 0x03E8 +#define REG_DBI_RDATA_V1_8710B 0x03EC +#define REG_DBI_FLAG_V1_8710B 0x03F0 +#define REG_MDIO_V1_8710B 0x03F4 +#define REG_PCIE_MIX_CFG_8710B 0x03F8 +#define REG_HCI_MIX_CFG_8710B 0x03FC + +/* ----------------------------------------------------- + * + * 0x0400h ~ 0x047Fh Protocol Configuration + * + * ----------------------------------------------------- */ +#define REG_VOQ_INFORMATION_8710B 0x0400 +#define REG_VIQ_INFORMATION_8710B 0x0404 +#define REG_BEQ_INFORMATION_8710B 0x0408 +#define REG_BKQ_INFORMATION_8710B 0x040C +#define REG_MGQ_INFORMATION_8710B 0x0410 +#define REG_HGQ_INFORMATION_8710B 0x0414 +#define REG_BCNQ_INFORMATION_8710B 0x0418 +#define REG_TXPKT_EMPTY_8710B 0x041A + +#define REG_FWHW_TXQ_CTRL_8710B 0x0420 +#define REG_HWSEQ_CTRL_8710B 0x0423 +#define REG_TXPKTBUF_BCNQ_BDNY_8710B 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY_8710B 0x0425 +#define REG_LIFECTRL_CTRL_8710B 0x0426 +#define REG_MULTI_BCNQ_OFFSET_8710B 0x0427 +#define REG_SPEC_SIFS_8710B 0x0428 +#define REG_RL_8710B 0x042A +#define REG_TXBF_CTRL_8710B 0x042C +#define REG_DARFRC_8710B 0x0430 +#define REG_RARFRC_8710B 0x0438 +#define REG_RRSR_8710B 0x0440 +#define REG_ARFR0_8710B 0x0444 +#define REG_ARFR1_8710B 0x044C +#define REG_CCK_CHECK_8710B 0x0454 +#define REG_AMPDU_MAX_TIME_8710B 0x0456 +#define REG_TXPKTBUF_BCNQ_BDNY1_8710B 0x0457 + +#define REG_AMPDU_MAX_LENGTH_8710B 0x0458 +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8710B 0x045D +#define REG_NDPA_OPT_CTRL_8710B 0x045F +#define REG_FAST_EDCA_CTRL_8710B 0x0460 +#define REG_RD_RESP_PKT_TH_8710B 0x0463 +#define REG_DATA_SC_8710B 0x0483 +#ifdef CONFIG_WOWLAN + #define REG_TXPKTBUF_IV_LOW 0x0484 + #define REG_TXPKTBUF_IV_HIGH 0x0488 +#endif +#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_POWER_STAGE1_8710B 0x04B4 +#define REG_POWER_STAGE2_8710B 0x04B8 +#define REG_AMPDU_BURST_MODE_8710B 0x04BC +#define REG_PKT_VO_VI_LIFE_TIME_8710B 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME_8710B 0x04C2 +#define REG_STBC_SETTING_8710B 0x04C4 +#define REG_HT_SINGLE_AMPDU_8710B 0x04C7 +#define REG_PROT_MODE_CTRL_8710B 0x04C8 +#define REG_MAX_AGGR_NUM_8710B 0x04CA +#define REG_RTS_MAX_AGGR_NUM_8710B 0x04CB +#define REG_BAR_MODE_CTRL_8710B 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8710B 0x04CF +#define REG_MACID_PKT_DROP0_8710B 0x04D0 +#define REG_MACID_PKT_SLEEP_8710B 0x04D4 + +/* ----------------------------------------------------- + * + * 0x0500h ~ 0x05FFh EDCA Configuration + * + * ----------------------------------------------------- */ +#define REG_EDCA_VO_PARAM_8710B 0x0500 +#define REG_EDCA_VI_PARAM_8710B 0x0504 +#define REG_EDCA_BE_PARAM_8710B 0x0508 +#define REG_EDCA_BK_PARAM_8710B 0x050C +#define REG_BCNTCFG_8710B 0x0510 +#define REG_PIFS_8710B 0x0512 +#define REG_RDG_PIFS_8710B 0x0513 +#define REG_SIFS_CTX_8710B 0x0514 +#define REG_SIFS_TRX_8710B 0x0516 +#define REG_AGGR_BREAK_TIME_8710B 0x051A +#define REG_SLOT_8710B 0x051B +#define REG_TX_PTCL_CTRL_8710B 0x0520 +#define REG_TXPAUSE_8710B 0x0522 +#define REG_DIS_TXREQ_CLR_8710B 0x0523 +#define REG_RD_CTRL_8710B 0x0524 +/* + * Format for offset 540h-542h: + * [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. + * [7:4]: Reserved. + * [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. + * [23:20]: Reserved + * Description: + * | + * |<--Setup--|--Hold------------>| + * --------------|---------------------- + * | + * TBTT + * Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. + * Described by Designer Tim and Bruce, 2011-01-14. + * */ +#define REG_TBTT_PROHIBIT_8710B 0x0540 +#define REG_RD_NAV_NXT_8710B 0x0544 +#define REG_NAV_PROT_LEN_8710B 0x0546 +#define REG_BCN_CTRL_8710B 0x0550 +#define REG_BCN_CTRL_1_8710B 0x0551 +#define REG_MBID_NUM_8710B 0x0552 +#define REG_DUAL_TSF_RST_8710B 0x0553 +#define REG_BCN_INTERVAL_8710B 0x0554 +#define REG_DRVERLYINT_8710B 0x0558 +#define REG_BCNDMATIM_8710B 0x0559 +#define REG_ATIMWND_8710B 0x055A +#define REG_USTIME_TSF_8710B 0x055C +#define REG_BCN_MAX_ERR_8710B 0x055D +#define REG_RXTSF_OFFSET_CCK_8710B 0x055E +#define REG_RXTSF_OFFSET_OFDM_8710B 0x055F +#define REG_TSFTR_8710B 0x0560 +#define REG_CTWND_8710B 0x0572 +#define REG_SECONDARY_CCA_CTRL_8710B 0x0577 +#define REG_PSTIMER_8710B 0x0580 +#define REG_TIMER0_8710B 0x0584 +#define REG_TIMER1_8710B 0x0588 +#define REG_ACMHWCTRL_8710B 0x05C0 +#define REG_SCH_TXCMD_8710B 0x05F8 + +/* ----------------------------------------------------- + * + * 0x0600h ~ 0x07FFh WMAC Configuration + * + * ----------------------------------------------------- */ +#define REG_MAC_CR_8710B 0x0600 +#define REG_TCR_8710B 0x0604 +#define REG_RCR_8710B 0x0608 +#define REG_RX_PKT_LIMIT_8710B 0x060C +#define REG_RX_DLK_TIME_8710B 0x060D +#define REG_RX_DRVINFO_SZ_8710B 0x060F + +#define REG_MACID_8710B 0x0610 +#define REG_BSSID_8710B 0x0618 +#define REG_MAR_8710B 0x0620 +#define REG_MBIDCAMCFG_8710B 0x0628 +#define REG_WOWLAN_GTK_DBG1 0x630 +#define REG_WOWLAN_GTK_DBG2 0x634 + +#define REG_USTIME_EDCA_8710B 0x0638 +#define REG_MAC_SPEC_SIFS_8710B 0x063A +#define REG_RESP_SIFP_CCK_8710B 0x063C +#define REG_RESP_SIFS_OFDM_8710B 0x063E +#define REG_ACKTO_8710B 0x0640 +#define REG_CTS2TO_8710B 0x0641 +#define REG_EIFS_8710B 0x0642 + +#define REG_NAV_UPPER_8710B 0x0652 /* unit of 128 */ +#define REG_TRXPTCL_CTL_8710B 0x0668 + +/* Security */ +#define REG_CAMCMD_8710B 0x0670 +#define REG_CAMWRITE_8710B 0x0674 +#define REG_CAMREAD_8710B 0x0678 +#define REG_CAMDBG_8710B 0x067C +#define REG_SECCFG_8710B 0x0680 + +/* Power */ +#define REG_WOW_CTRL_8710B 0x0690 +#define REG_PS_RX_INFO_8710B 0x0692 +#define REG_UAPSD_TID_8710B 0x0693 +#define REG_WKFMCAM_CMD_8710B 0x0698 +#define REG_WKFMCAM_NUM_8710B 0x0698 +#define REG_WKFMCAM_RWD_8710B 0x069C +#define REG_RXFLTMAP0_8710B 0x06A0 +#define REG_RXFLTMAP1_8710B 0x06A2 +#define REG_RXFLTMAP2_8710B 0x06A4 +#define REG_BCN_PSR_RPT_8710B 0x06A8 +#define REG_BT_COEX_TABLE_8710B 0x06C0 +#define REG_BFMER0_INFO_8710B 0x06E4 +#define REG_BFMER1_INFO_8710B 0x06EC +#define REG_CSI_RPT_PARAM_BW20_8710B 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_8710B 0x06F8 +#define REG_CSI_RPT_PARAM_BW80_8710B 0x06FC + +/* Hardware Port 2 */ +#define REG_MACID1_8710B 0x0700 +#define REG_BSSID1_8710B 0x0708 +#define REG_BFMEE_SEL_8710B 0x0714 +#define REG_SND_PTCL_CTRL_8710B 0x0718 + +/* LTR */ +#define REG_LTR_CTRL_BASIC_8710B 0x07A4 +#define REG_LTR_IDLE_LATENCY_V1_8710B 0x0798 +#define REG_LTR_ACTIVE_LATENCY_V1_8710B 0x079C + +/* LTE_COEX */ +#define REG_LTECOEX_CTRL 0x07C0 +#define REG_LTECOEX_WRITE_DATA 0x07C4 +#define REG_LTECOEX_READ_DATA 0x07C8 +#define REG_LTECOEX_PATH_CONTROL 0x70 + +/* Other */ +#define REG_USB_ACCESS_TIMEOUT 0xFE4C + +/* ----------------------------------------------------- + * SYSON_REG_SPEC + * ----------------------------------------------------- */ +#define SYSON_REG_BASE_ADDR_8710B 0x40000000 +#define REG_SYS_XTAL_CTRL0 0x0060 +#define REG_SYS_SYSTEM_CFG0 0x1F0 +#define REG_SYS_SYSTEM_CFG1 0x1F4 +#define REG_SYS_SYSTEM_CFG2 0x1F8 +#define REG_SYS_EEPROM_CTRL0 0x0E0 + + +/* ----------------------------------------------------- + * Indirect_R/W_SPEC + * ----------------------------------------------------- */ +#define NORMAL_REG_READ_OFFSET 0x83000000 +#define NORMAL_REG_WRITE_OFFSET 0x84000000 +#define EFUSE_READ_OFFSET 0x85000000 +#define EFUSE_WRITE_OFFSET 0x86000000 + + +/* ----------------------------------------------------- + * PAGE0_WLANON_REG_SPEC + * ----------------------------------------------------- */ +#define PAGE0_OFFSET 0x0 // WLANON_PAGE0_REG needs to add an offset. + + + +/* **************************************************************************** + * 8723 Regsiter Bit and Content definition + * **************************************************************************** */ + + /* ----------------------------------------------------- + * REG_SYS_SYSTEM_CFG0 + * ----------------------------------------------------- */ +#define BIT_RTL_ID_8710B BIT(16) + +#define BIT_MASK_CHIP_VER_8710B 0xf +#define BIT_GET_CHIP_VER_8710B(x) ((x) & BIT_MASK_CHIP_VER_8710B) + +#define BIT_SHIFT_VENDOR_ID_8710B 4 +#define BIT_MASK_VENDOR_ID_8710B 0xf +#define BIT_GET_VENDOR_ID_8710B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8710B) & BIT_MASK_VENDOR_ID_8710B) + + /* ----------------------------------------------------- + * REG_SYS_SYSTEM_CFG1 + * ----------------------------------------------------- */ +#define BIT_SPSLDO_SEL_8710B BIT(25) + + /* ----------------------------------------------------- + * REG_SYS_SYSTEM_CFG2 + * ----------------------------------------------------- */ +#define BIT_MASK_RF_RL_ID_8710B 0xf +#define BIT_GET_RF_RL_ID_8710B(x) ((x) & BIT_MASK_RF_RL_ID_8710B) + + /* ----------------------------------------------------- + * REG_SYS_SYSTEM_CFG2 + * ----------------------------------------------------- */ +#define BIT_EERPOMSEL_8710B BIT(4) +#define BIT_AUTOLOAD_SUS_8710B BIT(5) + + + /* ----------------------------------------------------- + * Other + * ----------------------------------------------------- */ + + +#define BIT_USB_RXDMA_AGG_EN BIT(31) +#define RXDMA_AGG_MODE_EN BIT(1) + +#ifdef CONFIG_WOWLAN + #define RXPKT_RELEASE_POLL BIT(16) + #define RXDMA_IDLE BIT(17) + #define RW_RELEASE_EN BIT(18) +#endif + +/* 2 HSISR + * interrupt mask which needs to clear */ +#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ + HSISR_SPS_OCP_INT |\ + HSISR_RON_INT |\ + HSISR_PDNINT |\ + HSISR_GPIO9_INT) + +#ifdef CONFIG_RF_POWER_TRIM + #ifdef CONFIG_RTL8710B + #define EEPROM_RF_GAIN_OFFSET 0xC1 + #endif + + #define EEPROM_RF_GAIN_VAL 0x1F6 +#endif /*CONFIG_RF_POWER_TRIM*/ + +#endif /* __RTL8710B_SPEC_H__ */ diff --git a/include/rtl8710b_sreset.h b/include/rtl8710b_sreset.h new file mode 100644 index 0000000..ac5c64e --- /dev/null +++ b/include/rtl8710b_sreset.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef _RTL8710B_SRESET_H_ +#define _RTL8710B_SRESET_H_ + +#include + +#ifdef DBG_CONFIG_ERROR_DETECT + extern void rtl8710b_sreset_xmit_status_check(_adapter *padapter); + extern void rtl8710b_sreset_linked_status_check(_adapter *padapter); +#endif +#endif diff --git a/include/rtl8710b_xmit.h b/include/rtl8710b_xmit.h new file mode 100644 index 0000000..a6b49cd --- /dev/null +++ b/include/rtl8710b_xmit.h @@ -0,0 +1,522 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTL8710B_XMIT_H__ +#define __RTL8710B_XMIT_H__ + + +#define MAX_TID (15) + + +#ifndef __INC_HAL8710BDESC_H +#define __INC_HAL8710BDESC_H + +#define RX_STATUS_DESC_SIZE_8710B 24 +#define RX_DRV_INFO_SIZE_UNIT_8710B 8 + + +/* DWORD 0 */ +#define SET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value) +#define SET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value) +#define SET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value) + +#define GET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14) +#define GET_RX_STATUS_DESC_CRC32_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1) +#define GET_RX_STATUS_DESC_ICV_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1) +#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4) +#define GET_RX_STATUS_DESC_SECURITY_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3) +#define GET_RX_STATUS_DESC_QOS_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1) +#define GET_RX_STATUS_DESC_SHIFT_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2) +#define GET_RX_STATUS_DESC_PHY_STATUS_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1) +#define GET_RX_STATUS_DESC_SWDEC_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1) +#define GET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1) +#define GET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1) + +/* DWORD 1 */ +#define GET_RX_STATUS_DESC_MACID_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) +#define GET_RX_STATUS_DESC_TID_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) +#define GET_RX_STATUS_DESC_AMSDU_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) +#define GET_RX_STATUS_DESC_RXID_MATCH_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1) +#define GET_RX_STATUS_DESC_PAGGR_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1) +#define GET_RX_STATUS_DESC_A1_FIT_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4) +#define GET_RX_STATUS_DESC_CHKERR_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1) +#define GET_RX_STATUS_DESC_IPVER_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) +#define GET_RX_STATUS_DESC_IS_TCPUDP__8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) +#define GET_RX_STATUS_DESC_CHK_VLD_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) +#define GET_RX_STATUS_DESC_PAM_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1) +#define GET_RX_STATUS_DESC_PWR_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1) +#define GET_RX_STATUS_DESC_MORE_DATA_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1) +#define GET_RX_STATUS_DESC_MORE_FRAG_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1) +#define GET_RX_STATUS_DESC_TYPE_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2) +#define GET_RX_STATUS_DESC_MC_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1) +#define GET_RX_STATUS_DESC_BC_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1) + +/* DWORD 2 */ +#define GET_RX_STATUS_DESC_SEQ_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12) +#define GET_RX_STATUS_DESC_FRAG_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4) +#define GET_RX_STATUS_DESC_RX_IS_QOS_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1) +#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6) +#define GET_RX_STATUS_DESC_RPT_SEL_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1) +#define GET_RX_STATUS_DESC_FCS_OK_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1) + +/* DWORD 3 */ +#define GET_RX_STATUS_DESC_RX_RATE_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7) +#define GET_RX_STATUS_DESC_HTC_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1) +#define GET_RX_STATUS_DESC_EOSP_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1) +#define GET_RX_STATUS_DESC_BSSID_FIT_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2) +#ifdef CONFIG_USB_RX_AGGREGATION +#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8) +#endif +#define GET_RX_STATUS_DESC_PATTERN_MATCH_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1) +#define GET_RX_STATUS_DESC_UNICAST_MATCH_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1) +#define GET_RX_STATUS_DESC_MAGIC_MATCH_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1) + +/* DWORD 6 */ +#define GET_RX_STATUS_DESC_MATCH_ID_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7) + +/* DWORD 5 */ +#define GET_RX_STATUS_DESC_TSFL_8710B(__pRxStatusDesc) \ + LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32) + +#define GET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) +#define GET_RX_STATUS_DESC_BUFF_ADDR64_8710B(__pRxDesc) \ + LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) + +#define SET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) + + +/* Dword 0, rsvd: bit26, bit28 */ +#define GET_TX_DESC_OWN_8710B(__pTxDesc)\ + LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) + +#define SET_TX_DESC_PKT_SIZE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) +#define SET_TX_DESC_OFFSET_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) +#define SET_TX_DESC_BMC_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) +#define SET_TX_DESC_HTC_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) +#define SET_TX_DESC_AMSDU_PAD_EN_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) +#define SET_TX_DESC_NO_ACM_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) +#define SET_TX_DESC_GF_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) + +/* Dword 1 */ +#define SET_TX_DESC_MACID_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) +#define SET_TX_DESC_QUEUE_SEL_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) +#define SET_TX_DESC_RDG_NAV_EXT_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) +#define SET_TX_DESC_LSIG_TXOP_EN_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) +#define SET_TX_DESC_PIFS_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) +#define SET_TX_DESC_RATE_ID_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) +#define SET_TX_DESC_EN_DESC_ID_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) +#define SET_TX_DESC_SEC_TYPE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) +#define SET_TX_DESC_PKT_OFFSET_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) +#define SET_TX_DESC_MORE_DATA_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value) + +/* Dword 2 remove P_AID, G_ID field*/ +#define SET_TX_DESC_CCA_RTS_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) +#define SET_TX_DESC_AGG_ENABLE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) +#define SET_TX_DESC_RDG_ENABLE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) +#define SET_TX_DESC_NULL0_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value) +#define SET_TX_DESC_NULL1_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value) +#define SET_TX_DESC_BK_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) +#define SET_TX_DESC_MORE_FRAG_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) +#define SET_TX_DESC_RAW_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) +#define SET_TX_DESC_CCX_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) +#define SET_TX_DESC_AMPDU_DENSITY_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) +#define SET_TX_DESC_BT_INT_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) +#define SET_TX_DESC_FTM_EN_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value) + +/* Dword 3 */ +#define SET_TX_DESC_NAV_USE_HDR_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) +#define SET_TX_DESC_HWSEQ_SEL_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) +#define SET_TX_DESC_USE_RATE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) +#define SET_TX_DESC_DISABLE_RTS_FB_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) +#define SET_TX_DESC_DISABLE_FB_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) +#define SET_TX_DESC_CTS2SELF_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) +#define SET_TX_DESC_RTS_ENABLE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) +#define SET_TX_DESC_HW_RTS_ENABLE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) +#define SET_TX_DESC_PORT_ID_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value) +#define SET_TX_DESC_USE_MAX_LEN_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) +#define SET_TX_DESC_MAX_AGG_NUM_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) +#define SET_TX_DESC_AMPDU_MAX_TIME_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) + +/* Dword 4 */ +#define SET_TX_DESC_TX_RATE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) +#define SET_TX_DESC_TX_TRY_RATE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value) +#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) +#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) +#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) +#define SET_TX_DESC_DATA_RETRY_LIMIT_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) +#define SET_TX_DESC_RTS_RATE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) +#define SET_TX_DESC_PCTS_EN_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value) +#define SET_TX_DESC_PCTS_MASK_IDX_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value) + +/* Dword 5 */ +#define SET_TX_DESC_DATA_SC_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) +#define SET_TX_DESC_DATA_SHORT_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) +#define SET_TX_DESC_DATA_BW_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) +#define SET_TX_DESC_DATA_STBC_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) +#define SET_TX_DESC_RTS_STBC_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) +#define SET_TX_DESC_RTS_SHORT_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) +#define SET_TX_DESC_RTS_SC_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) +#define SET_TX_DESC_PATH_A_EN_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value) +#define SET_TX_DESC_TXPWR_OF_SET_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value) + +/* Dword 6 */ +#define SET_TX_DESC_SW_DEFINE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) +#define SET_TX_DESC_MBSSID_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) +#define SET_TX_DESC_RF_SEL_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) + +/* Dword 7 */ +#ifdef CONFIG_PCI_HCI +#define SET_TX_DESC_TX_BUFFER_SIZE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) +#endif + +#ifdef CONFIG_USB_HCI +#define SET_TX_DESC_TX_DESC_CHECKSUM_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) +#endif + +#ifdef CONFIG_SDIO_HCI +#define SET_TX_DESC_TX_TIMESTAMP_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value) +#endif + +#define SET_TX_DESC_USB_TXAGG_NUM_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) + +/* Dword 8 */ +#define SET_TX_DESC_RTS_RC_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value) +#define SET_TX_DESC_BAR_RC_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value) +#define SET_TX_DESC_DATA_RC_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value) +#define SET_TX_DESC_HWSEQ_EN_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) +#define SET_TX_DESC_NEXTHEADPAGE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) +#define SET_TX_DESC_TAILPAGE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value) + +/* Dword 9 */ +#define SET_TX_DESC_PADDING_LEN_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value) +#define SET_TX_DESC_SEQ_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) +#define SET_TX_DESC_FINAL_DATA_RATE_8710B(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value) + + +#define SET_EARLYMODE_PKTNUM_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) +#define SET_EARLYMODE_LEN0_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) +#define SET_EARLYMODE_LEN1_1_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) +#define SET_EARLYMODE_LEN1_2_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) +#define SET_EARLYMODE_LEN2_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) +#define SET_EARLYMODE_LEN3_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) + + +/*-----------------------------------------------------------------*/ +/* RTL8710B TX BUFFER DESC */ +/*-----------------------------------------------------------------*/ +#ifdef CONFIG_64BIT_DMA + #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu) + #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu) + #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu) + #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu) +#else + #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu) + #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu) + #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu) + #define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) /* 64 BIT mode only */ +#endif +/* ********************************************************* */ + +/* 64 bits -- 32 bits */ +/* ======= ======= */ +/* Dword 0 0 */ +#define SET_TX_BUFF_DESC_LEN_0_8710B(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu) +#define SET_TX_BUFF_DESC_PSB_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value) +#define SET_TX_BUFF_DESC_OWN_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) + +/* Dword 1 1 */ +#define SET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value) +#define GET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32) +/* Dword 2 NA */ +#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value) +#ifdef CONFIG_64BIT_DMA + #define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32) +#else + #define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) 0 +#endif +/* Dword 3 NA */ +/* RESERVED 0 */ +/* Dword 4 2 */ +#define SET_TX_BUFF_DESC_LEN_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value) +#define SET_TX_BUFF_DESC_AMSDU_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value) +/* Dword 5 3 */ +#define SET_TX_BUFF_DESC_ADDR_LOW_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value) +/* Dword 6 NA */ +#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value) +/* Dword 7 NA */ +/*RESERVED 0 */ +/* Dword 8 4 */ +#define SET_TX_BUFF_DESC_LEN_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value) +#define SET_TX_BUFF_DESC_AMSDU_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value) +/* Dword 9 5 */ +#define SET_TX_BUFF_DESC_ADDR_LOW_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value) +/* Dword 10 NA */ +#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value) +/* Dword 11 NA */ +/*RESERVED 0 */ +/* Dword 12 6 */ +#define SET_TX_BUFF_DESC_LEN_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value) +#define SET_TX_BUFF_DESC_AMSDU_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value) +/* Dword 13 7 */ +#define SET_TX_BUFF_DESC_ADDR_LOW_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value) +/* Dword 14 NA */ +#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value) +/* Dword 15 NA */ +/*RESERVED 0 */ + + +#endif +/* ----------------------------------------------------------- + * + * Rate + * + * ----------------------------------------------------------- + * CCK Rates, TxHT = 0 */ +#define DESC8710B_RATE1M 0x00 +#define DESC8710B_RATE2M 0x01 +#define DESC8710B_RATE5_5M 0x02 +#define DESC8710B_RATE11M 0x03 + +/* OFDM Rates, TxHT = 0 */ +#define DESC8710B_RATE6M 0x04 +#define DESC8710B_RATE9M 0x05 +#define DESC8710B_RATE12M 0x06 +#define DESC8710B_RATE18M 0x07 +#define DESC8710B_RATE24M 0x08 +#define DESC8710B_RATE36M 0x09 +#define DESC8710B_RATE48M 0x0a +#define DESC8710B_RATE54M 0x0b + +/* MCS Rates, TxHT = 1 */ +#define DESC8710B_RATEMCS0 0x0c +#define DESC8710B_RATEMCS1 0x0d +#define DESC8710B_RATEMCS2 0x0e +#define DESC8710B_RATEMCS3 0x0f +#define DESC8710B_RATEMCS4 0x10 +#define DESC8710B_RATEMCS5 0x11 +#define DESC8710B_RATEMCS6 0x12 +#define DESC8710B_RATEMCS7 0x13 +#define DESC8710B_RATEMCS8 0x14 +#define DESC8710B_RATEMCS9 0x15 +#define DESC8710B_RATEMCS10 0x16 +#define DESC8710B_RATEMCS11 0x17 +#define DESC8710B_RATEMCS12 0x18 +#define DESC8710B_RATEMCS13 0x19 +#define DESC8710B_RATEMCS14 0x1a +#define DESC8710B_RATEMCS15 0x1b +#define DESC8710B_RATEVHTSS1MCS0 0x2c +#define DESC8710B_RATEVHTSS1MCS1 0x2d +#define DESC8710B_RATEVHTSS1MCS2 0x2e +#define DESC8710B_RATEVHTSS1MCS3 0x2f +#define DESC8710B_RATEVHTSS1MCS4 0x30 +#define DESC8710B_RATEVHTSS1MCS5 0x31 +#define DESC8710B_RATEVHTSS1MCS6 0x32 +#define DESC8710B_RATEVHTSS1MCS7 0x33 +#define DESC8710B_RATEVHTSS1MCS8 0x34 +#define DESC8710B_RATEVHTSS1MCS9 0x35 +#define DESC8710B_RATEVHTSS2MCS0 0x36 +#define DESC8710B_RATEVHTSS2MCS1 0x37 +#define DESC8710B_RATEVHTSS2MCS2 0x38 +#define DESC8710B_RATEVHTSS2MCS3 0x39 +#define DESC8710B_RATEVHTSS2MCS4 0x3a +#define DESC8710B_RATEVHTSS2MCS5 0x3b +#define DESC8710B_RATEVHTSS2MCS6 0x3c +#define DESC8710B_RATEVHTSS2MCS7 0x3d +#define DESC8710B_RATEVHTSS2MCS8 0x3e +#define DESC8710B_RATEVHTSS2MCS9 0x3f + + +#define RX_HAL_IS_CCK_RATE_8710B(pDesc)\ + (GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE1M || \ + GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE2M || \ + GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE5_5M || \ + GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE11M) + +#ifdef CONFIG_TRX_BD_ARCH + struct tx_desc; +#endif + +void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc); +void rtl8710b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); +void rtl8710b_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); +void rtl8710b_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); +void rtl8710b_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc); +void rtl8710b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); + +#if defined(CONFIG_CONCURRENT_MODE) + void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); +#endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + s32 rtl8710bs_init_xmit_priv(PADAPTER padapter); + void rtl8710bs_free_xmit_priv(PADAPTER padapter); + s32 rtl8710bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); + s32 rtl8710bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); + s32 rtl8710bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); + s32 rtl8710bs_xmit_buf_handler(PADAPTER padapter); + thread_return rtl8710bs_xmit_thread(thread_context context); + #define hal_xmit_handler rtl8710bs_xmit_buf_handler +#endif + +#ifdef CONFIG_USB_HCI + s32 rtl8710bu_xmit_buf_handler(PADAPTER padapter); + #define hal_xmit_handler rtl8710bu_xmit_buf_handler + s32 rtl8710bu_init_xmit_priv(PADAPTER padapter); + void rtl8710bu_free_xmit_priv(PADAPTER padapter); + s32 rtl8710bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); + s32 rtl8710bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); + s32 rtl8710bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); + void rtl8710bu_xmit_tasklet(void *priv); + s32 rtl8710bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); + void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc); +#endif + +#ifdef CONFIG_PCI_HCI + s32 rtl8710be_init_xmit_priv(PADAPTER padapter); + void rtl8710be_free_xmit_priv(PADAPTER padapter); + struct xmit_buf *rtl8710be_dequeue_xmitbuf(struct rtw_tx_ring *ring); + void rtl8710be_xmitframe_resume(_adapter *padapter); + s32 rtl8710be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); + s32 rtl8710be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); + s32 rtl8710be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); + void rtl8710be_xmit_tasklet(void *priv); +#endif + +u8 BWMapping_8710B(PADAPTER Adapter, struct pkt_attrib *pattrib); +u8 SCMapping_8710B(PADAPTER Adapter, struct pkt_attrib *pattrib); + +#endif diff --git a/include/rtl8723b_cmd.h b/include/rtl8723b_cmd.h index 1000d20..4f542da 100644 --- a/include/rtl8723b_cmd.h +++ b/include/rtl8723b_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_CMD_H__ #define __RTL8723B_CMD_H__ @@ -118,7 +113,6 @@ enum h2c_cmd_8723B { #define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) #define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8723B_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) #define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) @@ -182,11 +176,9 @@ enum h2c_cmd_8723B { /* host message to firmware cmd */ void rtl8723b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8723b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); -void rtl8723b_set_rssi_cmd(PADAPTER padapter, u8 *param); void rtl8723b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8723b_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8723b_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); void rtl8723b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST @@ -196,8 +188,6 @@ void rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus); void rtl8723b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); - #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW void rtl8723b_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); @@ -210,9 +200,6 @@ void CheckFwRsvdPageContent(PADAPTER padapter); void rtl8723b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); -#ifdef CONFIG_TSF_RESET_OFFLOAD - u8 rtl8723b_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ s32 FillH2CCmd8723B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8723B(_adapter *padapter, bool wowlan); #endif diff --git a/include/rtl8723b_dm.h b/include/rtl8723b_dm.h index a3bb7df..ea51717 100644 --- a/include/rtl8723b_dm.h +++ b/include/rtl8723b_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_DM_H__ #define __RTL8723B_DM_H__ /* ************************************************************ @@ -40,8 +35,4 @@ void rtl8723b_deinit_dm_priv(PADAPTER padapter); void rtl8723b_InitHalDm(PADAPTER padapter); void rtl8723b_HalDmWatchDog(PADAPTER padapter); -void rtl8723b_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8723b_hal_dm_in_lps(PADAPTER padapter); - - #endif diff --git a/include/rtl8723b_hal.h b/include/rtl8723b_hal.h index b7c8bc5..5ab8b35 100755 --- a/include/rtl8723b_hal.h +++ b/include/rtl8723b_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_HAL_H__ #define __RTL8723B_HAL_H__ @@ -111,23 +106,17 @@ typedef struct _RT_8723B_FIRMWARE_HDR { /* Note: We will divide number of page equally for each queue other than public queue! */ /* For General Reserved Page Number(Beacon Queue is reserved page) - * Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */ -#define BCNQ_PAGE_NUM_8723B 0x08 -#ifdef CONFIG_CONCURRENT_MODE - #define BCNQ1_PAGE_NUM_8723B 0x08 /* 0x04 */ -#else - #define BCNQ1_PAGE_NUM_8723B 0x00 -#endif + * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723B + * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/ +#define BCNQ_PAGE_NUM_8723B (MAX_BEACON_LEN / PAGE_SIZE_TX_8723B + 6) /*0x08*/ -#ifdef CONFIG_PNO_SUPPORT - #undef BCNQ1_PAGE_NUM_8723B - #define BCNQ1_PAGE_NUM_8723B 0x00 /* 0x04 */ -#endif /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6 + * NS offload: 2 NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8723B 0x08 + #define WOWLAN_PAGE_NUM_8723B 0x0b #else #define WOWLAN_PAGE_NUM_8723B 0x00 #endif @@ -141,7 +130,7 @@ typedef struct _RT_8723B_FIRMWARE_HDR { #define AP_WOWLAN_PAGE_NUM_8723B 0x02 #endif -#define TX_TOTAL_PAGE_NUMBER_8723B (0xFF - BCNQ_PAGE_NUM_8723B - BCNQ1_PAGE_NUM_8723B - WOWLAN_PAGE_NUM_8723B) +#define TX_TOTAL_PAGE_NUMBER_8723B (0xFF - BCNQ_PAGE_NUM_8723B - WOWLAN_PAGE_NUM_8723B) #define TX_PAGE_BOUNDARY_8723B (TX_TOTAL_PAGE_NUMBER_8723B + 1) #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B TX_TOTAL_PAGE_NUMBER_8723B @@ -152,11 +141,13 @@ typedef struct _RT_8723B_FIRMWARE_HDR { #define NORMAL_PAGE_NUM_HPQ_8723B 0x0C #define NORMAL_PAGE_NUM_LPQ_8723B 0x02 #define NORMAL_PAGE_NUM_NPQ_8723B 0x02 +#define NORMAL_PAGE_NUM_EPQ_8723B 0x04 /* Note: For Normal Chip Setting, modify later */ #define WMM_NORMAL_PAGE_NUM_HPQ_8723B 0x30 #define WMM_NORMAL_PAGE_NUM_LPQ_8723B 0x20 #define WMM_NORMAL_PAGE_NUM_NPQ_8723B 0x20 +#define WMM_NORMAL_PAGE_NUM_EPQ_8723B 0x00 #include "HalVerDef.h" @@ -231,7 +222,7 @@ VOID Hal_EfuseParseBoardType_8723B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN Au void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8723b(_adapter *adapter); -void SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val); u8 SetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); diff --git a/include/rtl8723b_led.h b/include/rtl8723b_led.h index 0a7b2c9..6b772cc 100755 --- a/include/rtl8723b_led.h +++ b/include/rtl8723b_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_LED_H__ #define __RTL8723B_LED_H__ @@ -24,7 +19,7 @@ #include #include - +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -46,3 +41,4 @@ #endif #endif +#endif/*CONFIG_RTW_SW_LED*/ diff --git a/include/rtl8723b_recv.h b/include/rtl8723b_recv.h index fd9faef..cf5e18b 100755 --- a/include/rtl8723b_recv.h +++ b/include/rtl8723b_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_RECV_H__ #define __RTL8723B_RECV_H__ diff --git a/include/rtl8723b_rf.h b/include/rtl8723b_rf.h index bf56dde..6325ad5 100644 --- a/include/rtl8723b_rf.h +++ b/include/rtl8723b_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_RF_H__ #define __RTL8723B_RF_H__ @@ -25,6 +20,6 @@ int PHY_RF6052_Config8723B(IN PADAPTER Adapter); VOID PHY_RF6052SetBandwidth8723B( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); #endif diff --git a/include/rtl8723b_spec.h b/include/rtl8723b_spec.h index f8e8a65..b0fb4aa 100755 --- a/include/rtl8723b_spec.h +++ b/include/rtl8723b_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_SPEC_H__ #define __RTL8723B_SPEC_H__ diff --git a/include/rtl8723b_sreset.h b/include/rtl8723b_sreset.h index 8067359..c97f264 100644 --- a/include/rtl8723b_sreset.h +++ b/include/rtl8723b_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8723B_SRESET_H_ #define _RTL8723B_SRESET_H_ diff --git a/include/rtl8723b_xmit.h b/include/rtl8723b_xmit.h index 7cc33e1..22b3bac 100755 --- a/include/rtl8723b_xmit.h +++ b/include/rtl8723b_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723B_XMIT_H__ #define __RTL8723B_XMIT_H__ @@ -189,13 +184,14 @@ #define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) /* Dword 7 */ - #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + #ifdef CONFIG_PCI_HCI #define SET_TX_DESC_TX_BUFFER_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) - #else + #endif + #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI) #define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) #endif #define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) - #if (DEV_BUS_TYPE == RT_SDIO_INTERFACE) + #ifdef CONFIG_SDIO_HCI #define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) #endif @@ -293,6 +289,7 @@ void rtl8723b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 I #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) s32 rtl8723bs_init_xmit_priv(PADAPTER padapter); diff --git a/include/rtl8723d_cmd.h b/include/rtl8723d_cmd.h index e00b7ed..2226959 100644 --- a/include/rtl8723d_cmd.h +++ b/include/rtl8723d_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_CMD_H__ #define __RTL8723D_CMD_H__ @@ -98,26 +93,14 @@ enum h2c_cmd_8723D { #define SET_8723D_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #define SET_8723D_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -/* _KEEP_ALIVE_CMD_0x03 */ -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) -#define SET_8723D_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) - -/* _DISCONNECT_DECISION_CMD_0x04 */ -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) -#define SET_8723D_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) - /* _PWR_MOD_CMD_0x20 */ #define SET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) #define SET_8723D_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) #define SET_8723D_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) #define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) #define SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) #define SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8723D_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) #define GET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) @@ -181,12 +164,8 @@ enum h2c_cmd_8723D { /* host message to firmware cmd */ void rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); void rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); -void rtl8723d_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8723d_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); /* s32 rtl8723d_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */ void rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter); -void rtl8723d_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask, u8 ignore_bw); -void rtl8723d_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus); #ifdef CONFIG_BT_COEXIST void rtl8723d_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); @@ -195,17 +174,16 @@ void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus); void rtl8723d_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); #endif /* CONFIG_P2P */ -void CheckFwRsvdPageContent(PADAPTER padapter); +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW +void rtl8723d_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); +#endif +#endif #ifdef CONFIG_P2P_WOWLAN void rtl8723d_set_p2p_wowlan_offload_cmd(PADAPTER padapter); #endif -void rtl8723d_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); - -#ifdef CONFIG_TSF_RESET_OFFLOAD - u8 rtl8723d_reset_tsf(_adapter *padapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ s32 FillH2CCmd8723D(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); u8 GetTxBufferRsvdPageNum8723D(_adapter *padapter, bool wowlan); #endif diff --git a/include/rtl8723d_dm.h b/include/rtl8723d_dm.h index bae086d..0612f06 100644 --- a/include/rtl8723d_dm.h +++ b/include/rtl8723d_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_DM_H__ #define __RTL8723D_DM_H__ /* ************************************************************ @@ -40,8 +35,5 @@ void rtl8723d_deinit_dm_priv(PADAPTER padapter); void rtl8723d_InitHalDm(PADAPTER padapter); void rtl8723d_HalDmWatchDog(PADAPTER padapter); -void rtl8723d_HalDmWatchDog_in_LPS(PADAPTER padapter); -void rtl8723d_hal_dm_in_lps(PADAPTER padapter); - #endif diff --git a/include/rtl8723d_hal.h b/include/rtl8723d_hal.h index 494dad3..49bfc5e 100644 --- a/include/rtl8723d_hal.h +++ b/include/rtl8723d_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_HAL_H__ #define __RTL8723D_HAL_H__ @@ -116,23 +111,17 @@ typedef struct _RT_8723D_FIRMWARE_HDR { /* Note: We will divide number of page equally for each queue other than public queue! */ /* For General Reserved Page Number(Beacon Queue is reserved page) - * Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 */ -#define BCNQ_PAGE_NUM_8723D 0x08 -#ifdef CONFIG_CONCURRENT_MODE - #define BCNQ1_PAGE_NUM_8723D 0x08 /* 0x04 */ -#else - #define BCNQ1_PAGE_NUM_8723D 0x00 -#endif + * Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723D + * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/ -#ifdef CONFIG_PNO_SUPPORT - #undef BCNQ1_PAGE_NUM_8723D - #define BCNQ1_PAGE_NUM_8723D 0x00 /* 0x04 */ -#endif +#define BCNQ_PAGE_NUM_8723D (MAX_BEACON_LEN/PAGE_SIZE_TX_8723D + 6) /*0x08*/ /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6 + * NS offload: 2 NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8723D 0x08 + #define WOWLAN_PAGE_NUM_8723D 0x0b #else #define WOWLAN_PAGE_NUM_8723D 0x00 #endif @@ -147,7 +136,7 @@ typedef struct _RT_8723D_FIRMWARE_HDR { #endif #define TX_TOTAL_PAGE_NUMBER_8723D\ - (0xFF - BCNQ_PAGE_NUM_8723D - BCNQ1_PAGE_NUM_8723D - WOWLAN_PAGE_NUM_8723D) + (0xFF - BCNQ_PAGE_NUM_8723D - WOWLAN_PAGE_NUM_8723D) #define TX_PAGE_BOUNDARY_8723D (TX_TOTAL_PAGE_NUMBER_8723D + 1) #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D TX_TOTAL_PAGE_NUMBER_8723D @@ -159,11 +148,13 @@ typedef struct _RT_8723D_FIRMWARE_HDR { #define NORMAL_PAGE_NUM_HPQ_8723D 0x0C #define NORMAL_PAGE_NUM_LPQ_8723D 0x02 #define NORMAL_PAGE_NUM_NPQ_8723D 0x02 +#define NORMAL_PAGE_NUM_EPQ_8723D 0x04 /* Note: For Normal Chip Setting, modify later */ #define WMM_NORMAL_PAGE_NUM_HPQ_8723D 0x30 #define WMM_NORMAL_PAGE_NUM_LPQ_8723D 0x20 #define WMM_NORMAL_PAGE_NUM_NPQ_8723D 0x20 +#define WMM_NORMAL_PAGE_NUM_EPQ_8723D 0x00 #include "HalVerDef.h" @@ -241,8 +232,6 @@ void Hal_EfuseParseBTCoexistInfo_8723D(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); void Hal_EfuseParseEEPROMVer_8723D(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); -void Hal_EfuseParsePackageType_8723D(PADAPTER pAdapter, - u8 *hwinfo, BOOLEAN AutoLoadFail); void Hal_EfuseParseChnlPlan_8723D(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); void Hal_EfuseParseCustomerID_8723D(PADAPTER padapter, @@ -260,7 +249,7 @@ VOID Hal_EfuseParseBoardType_8723D(PADAPTER Adapter, void rtl8723d_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8723d(_adapter *adapter); -void SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val); +u8 SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val); void GetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val); u8 SetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); @@ -268,8 +257,6 @@ u8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); /* register */ void rtl8723d_InitBeaconParameters(PADAPTER padapter); void rtl8723d_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); -void _InitBurstPktLen_8723DS(PADAPTER Adapter); -void _InitLTECoex_8723DS(PADAPTER Adapter); void _InitMacAPLLSetting_8723D(PADAPTER Adapter); void _8051Reset8723(PADAPTER padapter); #ifdef CONFIG_WOWLAN @@ -310,7 +297,7 @@ void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); #ifdef CONFIG_PCI_HCI BOOLEAN InterruptRecognized8723DE(PADAPTER Adapter); VOID UpdateInterruptMask8723DE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); - u16 get_txbufdesc_idx_hwaddr(u16 ff_hwaddr); + u16 get_txbd_rw_reg(u16 ff_hwaddr); #endif #endif diff --git a/include/rtl8723d_led.h b/include/rtl8723d_led.h index 439ee82..1905e8b 100644 --- a/include/rtl8723d_led.h +++ b/include/rtl8723d_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_LED_H__ #define __RTL8723D_LED_H__ @@ -24,7 +19,7 @@ #include #include - +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -45,4 +40,5 @@ void rtl8723de_DeInitSwLeds(PADAPTER padapter); #endif +#endif /*#ifdef CONFIG_RTW_SW_LED*/ #endif diff --git a/include/rtl8723d_lps_poff.h b/include/rtl8723d_lps_poff.h index c466d40..138a0ca 100644 --- a/include/rtl8723d_lps_poff.h +++ b/include/rtl8723d_lps_poff.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /******************************************** CONST ************************/ #define NUM_OF_REGISTER_BANK 13 diff --git a/include/rtl8723d_recv.h b/include/rtl8723d_recv.h index 6343ec8..03539a8 100644 --- a/include/rtl8723d_recv.h +++ b/include/rtl8723d_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_RECV_H__ #define __RTL8723D_RECV_H__ @@ -102,6 +97,7 @@ #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) s32 rtl8723ds_init_recv_priv(PADAPTER padapter); void rtl8723ds_free_recv_priv(PADAPTER padapter); + s32 rtl8723ds_recv_hdl(_adapter *padapter); #endif #ifdef CONFIG_USB_HCI diff --git a/include/rtl8723d_rf.h b/include/rtl8723d_rf.h index 0aa5813..733eb0a 100644 --- a/include/rtl8723d_rf.h +++ b/include/rtl8723d_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,16 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_RF_H__ #define __RTL8723D_RF_H__ int PHY_RF6052_Config8723D(IN PADAPTER pdapter); -void PHY_RF6052SetBandwidth8723D(IN PADAPTER Adapter, IN CHANNEL_WIDTH Bandwidth); +void PHY_RF6052SetBandwidth8723D(IN PADAPTER Adapter, IN enum channel_width Bandwidth); #endif diff --git a/include/rtl8723d_spec.h b/include/rtl8723d_spec.h index 21653f2..5106b23 100644 --- a/include/rtl8723d_spec.h +++ b/include/rtl8723d_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_SPEC_H__ #define __RTL8723D_SPEC_H__ @@ -83,6 +79,7 @@ #define REG_PMC_DBG_CTRL2_8723D 0x00CC #define REG_EFUSE_BURN_GNT_8723D 0x00CF #define REG_HPON_FSM_8723D 0x00EC +#define REG_SYS_CFG1_8723D 0x00F0 #define REG_SYS_CFG_8723D 0x00FC #define REG_ROM_VERSION 0x00FD @@ -380,6 +377,11 @@ #define REG_BFMEE_SEL_8723D 0x0714 #define REG_SND_PTCL_CTRL_8723D 0x0718 +/* LTR */ +#define REG_LTR_CTRL_BASIC_8723D 0x07A4 +#define REG_LTR_IDLE_LATENCY_V1_8723D 0x0798 +#define REG_LTR_ACTIVE_LATENCY_V1_8723D 0x079C + /* LTE_COEX */ #define REG_LTECOEX_CTRL 0x07C0 #define REG_LTECOEX_WRITE_DATA 0x07C4 diff --git a/include/rtl8723d_sreset.h b/include/rtl8723d_sreset.h index aafe7c8..db75dba 100644 --- a/include/rtl8723d_sreset.h +++ b/include/rtl8723d_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8723D_SRESET_H_ #define _RTL8723D_SRESET_H_ diff --git a/include/rtl8723d_xmit.h b/include/rtl8723d_xmit.h index 20f98b0..b1636ad 100644 --- a/include/rtl8723d_xmit.h +++ b/include/rtl8723d_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8723D_XMIT_H__ #define __RTL8723D_XMIT_H__ @@ -217,9 +212,8 @@ SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value) /* Dword 3 */ -#define SET_TX_DESC_NAV_USE_HDR_8723D(__pTxDesc, __Value) \ - SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) -#define SET_TX_DESC_HWSEQ_SEL_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) +#define SET_TX_DESC_HWSEQ_SEL_8723D(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) #define SET_TX_DESC_USE_RATE_8723D(__pTxDesc, __Value) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) #define SET_TX_DESC_DISABLE_RTS_FB_8723D(__pTxDesc, __Value) \ @@ -234,6 +228,8 @@ SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) #define SET_TX_DESC_PORT_ID_8723D(__pTxDesc, __Value) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value) +#define SET_TX_DESC_NAV_USE_HDR_8723D(__pTxDesc, __Value) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) #define SET_TX_DESC_USE_MAX_LEN_8723D(__pTxDesc, __Value) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) #define SET_TX_DESC_MAX_AGG_NUM_8723D(__pTxDesc, __Value) \ @@ -290,13 +286,17 @@ SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) /* Dword 7 */ -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#ifdef CONFIG_PCI_HCI #define SET_TX_DESC_TX_BUFFER_SIZE_8723D(__pTxDesc, __Value) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#elif(DEV_BUS_TYPE == RT_USB_INTERFACE) +#endif + +#ifdef CONFIG_USB_HCI #define SET_TX_DESC_TX_DESC_CHECKSUM_8723D(__pTxDesc, __Value) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#else +#endif + +#ifdef CONFIG_SDIO_HCI #define SET_TX_DESC_TX_TIMESTAMP_8723D(__pTxDesc, __Value) \ SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value) #endif @@ -480,6 +480,7 @@ void rtl8723d_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 I #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) s32 rtl8723ds_init_xmit_priv(PADAPTER padapter); diff --git a/include/rtl8812a_cmd.h b/include/rtl8812a_cmd.h index 3891bd0..5b55fdf 100644 --- a/include/rtl8812a_cmd.h +++ b/include/rtl8812a_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_CMD_H__ #define __RTL8812A_CMD_H__ @@ -89,7 +84,6 @@ struct H2C_SS_RFOFF_PARAM { #define SET_8812_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #define SET_8812_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) #define SET_8812_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8812_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) #define GET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) @@ -103,14 +97,13 @@ struct H2C_SS_RFOFF_PARAM { #define SET_8812_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) -void set_ra_ldpc_8812(struct sta_info *psta, BOOLEAN bLDPC); +void set_ra_ldpc_8812(struct cmn_sta_info *cmn_sta_info, BOOLEAN bLDPC); /* host message to firmware cmd */ s32 fill_h2c_cmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); void rtl8812_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode); void rtl8812_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); u8 rtl8812_set_rssi_cmd(PADAPTER padapter, u8 *param); -void rtl8812_set_raid_cmd(PADAPTER padapter, u32 bitmap, u8 *arg, u8 bw); void rtl8812_set_wowlan_cmd(_adapter *padapter, u8 enable); u8 GetTxBufferRsvdPageNum8812(_adapter *padapter, bool wowlan); @@ -125,18 +118,12 @@ void rtl8812_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); void rtl8812_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); #endif -void CheckFwRsvdPageContent(PADAPTER padapter); - #ifdef CONFIG_TDLS #ifdef CONFIG_TDLS_CH_SW void rtl8812_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); #endif #endif -#ifdef CONFIG_TSF_RESET_OFFLOAD -int reset_tsf(PADAPTER Adapter, u8 reset_port); -#endif /* CONFIG_TSF_RESET_OFFLOAD */ - /* ------------------------------------ * C2H format * ------------------------------------ */ diff --git a/include/rtl8812a_dm.h b/include/rtl8812a_dm.h index fef5824..584f6d3 100644 --- a/include/rtl8812a_dm.h +++ b/include/rtl8812a_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_DM_H__ #define __RTL8812A_DM_H__ diff --git a/include/rtl8812a_hal.h b/include/rtl8812a_hal.h index e8a29e9..1ecfb72 100644 --- a/include/rtl8812a_hal.h +++ b/include/rtl8812a_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_HAL_H__ #define __RTL8812A_HAL_H__ @@ -140,12 +135,18 @@ typedef struct _RT_FIRMWARE_8812 { #endif #define RX_DMA_BOUNDARY_8812 (MAX_RX_DMA_BUFFER_SIZE_8812 - RX_DMA_RESERVED_SIZE_8812 - 1) -#define BCNQ_PAGE_NUM_8812 0x07 +#define PAGE_SIZE_TX_8812A PAGE_SIZE_512 + +/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8812A + * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/ +#define BCNQ_PAGE_NUM_8812 (MAX_BEACON_LEN / PAGE_SIZE_TX_8812A + 6) /*0x07*/ /* For WoWLan , more reserved page - * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, AOAC rpt: 1,PNO: 6 */ + * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, AOAC rpt: 1,PNO: 6 + * NS offload: 1 NDP info: 1 + */ #ifdef CONFIG_WOWLAN - #define WOWLAN_PAGE_NUM_8812 0x06 + #define WOWLAN_PAGE_NUM_8812 0x08 #else #define WOWLAN_PAGE_NUM_8812 0x00 #endif @@ -157,7 +158,13 @@ typedef struct _RT_FIRMWARE_8812 { #define FW_NDPA_PAGE_NUM 0x00 #endif -#define TX_TOTAL_PAGE_NUMBER_8812 (0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812-FW_NDPA_PAGE_NUM) +#ifdef DBG_FW_DEBUG_MSG_PKT + #define FW_DBG_MSG_PKT_PAGE_NUM_8812 0x01 +#else + #define FW_DBG_MSG_PKT_PAGE_NUM_8812 0x00 +#endif /*DBG_FW_DEBUG_MSG_PKT*/ + +#define TX_TOTAL_PAGE_NUMBER_8812 (0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 - FW_NDPA_PAGE_NUM - FW_DBG_MSG_PKT_PAGE_NUM_8812) #define TX_PAGE_BOUNDARY_8812 (TX_TOTAL_PAGE_NUMBER_8812 + 1) #define TX_PAGE_BOUNDARY_WOWLAN_8812 (0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 + 1) @@ -190,12 +197,11 @@ typedef struct _RT_FIRMWARE_8812 { #endif #define RX_DMA_BOUNDARY_8821 (MAX_RX_DMA_BUFFER_SIZE_8821 - RX_DMA_RESERVED_SIZE_8821 - 1) -#define BCNQ_PAGE_NUM_8821 0x08 -#ifdef CONFIG_CONCURRENT_MODE - #define BCNQ1_PAGE_NUM_8821 0x04 -#else - #define BCNQ1_PAGE_NUM_8821 0x00 -#endif +/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8821A + * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/ + +#define BCNQ_PAGE_NUM_8821 (MAX_BEACON_LEN / PAGE_SIZE_TX_8821A + 6) /*0x08*/ + /* For WoWLan , more reserved page * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, PNO: 6 */ @@ -205,7 +211,7 @@ typedef struct _RT_FIRMWARE_8812 { #define WOWLAN_PAGE_NUM_8821 0x00 #endif -#define TX_TOTAL_PAGE_NUMBER_8821 (0xFF - BCNQ_PAGE_NUM_8821 - BCNQ1_PAGE_NUM_8821 - WOWLAN_PAGE_NUM_8821) +#define TX_TOTAL_PAGE_NUMBER_8821 (0xFF - BCNQ_PAGE_NUM_8821 - WOWLAN_PAGE_NUM_8821) #define TX_PAGE_BOUNDARY_8821 (TX_TOTAL_PAGE_NUMBER_8821 + 1) /* #define TX_PAGE_BOUNDARY_WOWLAN_8821 0xE0 */ @@ -217,10 +223,12 @@ typedef struct _RT_FIRMWARE_8812 { #define NORMAL_PAGE_NUM_LPQ_8821 0x08/* 0x10 */ #define NORMAL_PAGE_NUM_HPQ_8821 0x08/* 0x10 */ #define NORMAL_PAGE_NUM_NPQ_8821 0x00 +#define NORMAL_PAGE_NUM_EPQ_8821 0x04 #define WMM_NORMAL_PAGE_NUM_HPQ_8821 0x30 #define WMM_NORMAL_PAGE_NUM_LPQ_8821 0x20 #define WMM_NORMAL_PAGE_NUM_NPQ_8821 0x20 +#define WMM_NORMAL_PAGE_NUM_EPQ_8821 0x00 #define MCC_NORMAL_PAGE_NUM_HPQ_8821 0x10 #define MCC_NORMAL_PAGE_NUM_LPQ_8821 0x10 @@ -329,7 +337,7 @@ void SetBeaconRelatedRegisters8812A(PADAPTER padapter); void ReadRFType8812A(PADAPTER padapter); void InitDefaultValue8821A(PADAPTER padapter); -void SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval); +u8 SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval); void GetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval); u8 SetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); @@ -339,9 +347,6 @@ void init_hal_spec_8821a(_adapter *adapter); u32 upload_txpktbuf_8812au(_adapter *adapter, u8 *buf, u32 buflen); -/* register */ -void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits); - void rtl8812_start_thread(PADAPTER padapter); void rtl8812_stop_thread(PADAPTER padapter); diff --git a/include/rtl8812a_led.h b/include/rtl8812a_led.h index 28840be..30c676e 100644 --- a/include/rtl8812a_led.h +++ b/include/rtl8812a_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,16 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_LED_H__ #define __RTL8812A_LED_H__ - - +#ifdef CONFIG_RTW_LED +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -33,9 +28,14 @@ void rtl8812ae_InitSwLeds(PADAPTER padapter); void rtl8812ae_DeInitSwLeds(PADAPTER padapter); #endif #ifdef CONFIG_SDIO_HCI -void rtl8821as_hw_led_config(PADAPTER adapter); void rtl8821as_InitSwLeds(PADAPTER padapter); void rtl8821as_DeInitSwLeds(PADAPTER padapter); #endif +#endif/*CONFIG_RTW_SW_LED*/ +#endif/*#ifdef CONFIG_RTW_LED*/ +#ifdef CONFIG_SDIO_HCI +void rtl8821as_init_led_circuit(PADAPTER adapter); #endif + +#endif /*__RTL8812A_LED_H__*/ diff --git a/include/rtl8812a_recv.h b/include/rtl8812a_recv.h index 4e7b4ed..bf1d4b6 100644 --- a/include/rtl8812a_recv.h +++ b/include/rtl8812a_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_RECV_H__ #define __RTL8812A_RECV_H__ diff --git a/include/rtl8812a_rf.h b/include/rtl8812a_rf.h index 9a7175d..9a7b60e 100644 --- a/include/rtl8812a_rf.h +++ b/include/rtl8812a_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,19 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_RF_H__ #define __RTL8812A_RF_H__ VOID PHY_RF6052SetBandwidth8812( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); int diff --git a/include/rtl8812a_spec.h b/include/rtl8812a_spec.h index 81a410c..37ba247 100644 --- a/include/rtl8812a_spec.h +++ b/include/rtl8812a_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_SPEC_H__ #define __RTL8812A_SPEC_H__ diff --git a/include/rtl8812a_sreset.h b/include/rtl8812a_sreset.h index 1d166dc..d4bbd58 100644 --- a/include/rtl8812a_sreset.h +++ b/include/rtl8812a_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL88812A_SRESET_H_ #define _RTL8812A_SRESET_H_ diff --git a/include/rtl8812a_xmit.h b/include/rtl8812a_xmit.h index 9fe4dfb..6105a8e 100644 --- a/include/rtl8812a_xmit.h +++ b/include/rtl8812a_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812A_XMIT_H__ #define __RTL8812A_XMIT_H__ @@ -326,6 +321,7 @@ void rtl8812a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); #ifdef CONFIG_USB_HCI s32 rtl8812au_init_xmit_priv(PADAPTER padapter); diff --git a/include/rtl8814a_cmd.h b/include/rtl8814a_cmd.h index ddd7fa6..1c3e48b 100755 --- a/include/rtl8814a_cmd.h +++ b/include/rtl8814a_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_CMD_H__ #define __RTL8814A_CMD_H__ #include "hal_com_h2c.h" @@ -36,7 +31,6 @@ #define SET_8814A_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) #define SET_8814A_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) #define SET_8814A_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) -#define SET_8814A_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) #define GET_8814A_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) @@ -141,12 +135,10 @@ void rtl8814_fw_update_beacon_cmd(_adapter *padapter); #define SET_8814A_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) s32 FillH2CCmd_8814(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); -void rtl8814_set_raid_cmd(PADAPTER padapter, u64 bitmap, u8 *arg, u8 bw); void rtl8814_set_wowlan_cmd(_adapter *padapter, u8 enable); void rtl8814_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus); void rtl8814_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode); u8 GetTxBufferRsvdPageNum8814(_adapter *padapter, bool wowlan); -u8 rtl8814_set_rssi_cmd(_adapter *padapter, u8 *param); void rtl8814_req_txrpt_cmd(PADAPTER padapter, u8 macid); #ifdef CONFIG_TDLS diff --git a/include/rtl8814a_dm.h b/include/rtl8814a_dm.h index bb925e4..afbc8be 100644 --- a/include/rtl8814a_dm.h +++ b/include/rtl8814a_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_DM_H__ #define __RTL8814A_DM_H__ diff --git a/include/rtl8814a_hal.h b/include/rtl8814a_hal.h index b5f6a51..aa7b498 100755 --- a/include/rtl8814a_hal.h +++ b/include/rtl8814a_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_HAL_H__ #define __RTL8814A_HAL_H__ @@ -56,7 +51,10 @@ typedef struct _RT_FIRMWARE_8814 { } RT_FIRMWARE_8814, *PRT_FIRMWARE_8814; #define PAGE_SIZE_TX_8814 PAGE_SIZE_128 -#define BCNQ_PAGE_NUM_8814 0x08 +/* BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8814 + * PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/ + +#define BCNQ_PAGE_NUM_8814 (MAX_BEACON_LEN / PAGE_SIZE_TX_8814 + 6) /*0x08*/ #define Rtl8814A_NIC_PWR_ON_FLOW rtl8814A_power_on_flow #define Rtl8814A_NIC_RF_OFF_FLOW rtl8814A_radio_off_flow @@ -201,12 +199,12 @@ Chip specific /* pic buffer descriptor */ #if 1 /* according to the define in the rtw_xmit.h, rtw_recv.h */ #define RTL8814AE_SEG_NUM TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */ - #define TX_DESC_NUM_8814A TXDESC_NUM /* 128 */ + #define TX_DESC_NUM_8814A TX_BD_NUM /* 128 */ #define RX_DESC_NUM_8814A PCI_MAX_RX_COUNT /* 128 */ #ifdef CONFIG_CONCURRENT_MODE - #define BE_QUEUE_TX_DESC_NUM_8814A (TXDESC_NUM<<1) /* 256 */ + #define BE_QUEUE_TX_DESC_NUM_8814A (TX_BD_NUM<<1) /* 256 */ #else - #define BE_QUEUE_TX_DESC_NUM_8814A (TXDESC_NUM+(TXDESC_NUM>>1)) /* 192 */ + #define BE_QUEUE_TX_DESC_NUM_8814A (TX_BD_NUM+(TX_BD_NUM>>1)) /* 192 */ #endif #else #define RTL8814AE_SEG_NUM TX_BUFFER_SEG_NUM /* 0:2 seg, 1: 4 seg, 2: 8 seg */ @@ -307,16 +305,13 @@ void SetBeaconRelatedRegisters8814A(PADAPTER padapter); void ReadRFType8814A(PADAPTER padapter); void InitDefaultValue8814A(PADAPTER padapter); -void SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); +u8 SetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); void GetHwReg8814A(PADAPTER padapter, u8 variable, u8 *pval); u8 SetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); u8 GetHalDefVar8814A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); void rtl8814_set_hal_ops(struct hal_ops *pHalFunc); void init_hal_spec_8814a(_adapter *adapter); -/* register */ -void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits); -void SetBcnCtrlReg(PADAPTER Adapter, u8 SetBits, u8 ClearBits); void rtl8814_start_thread(PADAPTER padapter); void rtl8814_stop_thread(PADAPTER padapter); @@ -325,7 +320,7 @@ void rtl8814_stop_thread(PADAPTER padapter); BOOLEAN InterruptRecognized8814AE(PADAPTER Adapter); VOID UpdateInterruptMask8814AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); VOID InitMAC_TRXBD_8814AE(PADAPTER Adapter); - u16 get_txbd_idx_addr(u16 ff_hwaddr); + u16 get_txbd_rw_reg(u16 ff_hwaddr); #endif #ifdef CONFIG_BT_COEXIST diff --git a/include/rtl8814a_led.h b/include/rtl8814a_led.h index 1137a9b..cc45792 100644 --- a/include/rtl8814a_led.h +++ b/include/rtl8814a_led.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,16 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_LED_H__ #define __RTL8814A_LED_H__ - +#ifdef CONFIG_RTW_SW_LED /* ******************************************************************************** * Interface to manipulate LED objects. * ******************************************************************************** */ @@ -38,3 +33,4 @@ #endif /* CONFIG_SDIO_HCI */ #endif /* __RTL8814A_LED_H__ */ +#endif /*CONFIG_RTW_SW_LED*/ diff --git a/include/rtl8814a_recv.h b/include/rtl8814a_recv.h index e9626f3..c6792d8 100755 --- a/include/rtl8814a_recv.h +++ b/include/rtl8814a_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_RECV_H__ #define __RTL8814A_RECV_H__ diff --git a/include/rtl8814a_rf.h b/include/rtl8814a_rf.h index 7b11d99..e374439 100644 --- a/include/rtl8814a_rf.h +++ b/include/rtl8814a_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,19 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_RF_H__ #define __RTL8814A_RF_H__ VOID PHY_RF6052SetBandwidth8814A( IN PADAPTER Adapter, - IN CHANNEL_WIDTH Bandwidth); + IN enum channel_width Bandwidth); int diff --git a/include/rtl8814a_spec.h b/include/rtl8814a_spec.h index 8a4bb91..917b961 100755 --- a/include/rtl8814a_spec.h +++ b/include/rtl8814a_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_SPEC_H__ #define __RTL8814A_SPEC_H__ @@ -483,6 +479,13 @@ #define REG_DDMA_CHKSUM 0x12F0 #define REG_DDMA_MONITER 0x12FC +#define REG_Q0_Q1_INFO_8814A 0x1400 +#define REG_Q2_Q3_INFO_8814A 0x1404 +#define REG_Q4_Q5_INFO_8814A 0x1408 +#define REG_Q6_Q7_INFO_8814A 0x140C +#define REG_MGQ_HIQ_INFO_8814A 0x1410 +#define REG_CMDQ_BCNQ_INFO_8814A 0x1414 + #define DDMA_LEN_MASK 0x0001FFFF #define FW_CHKSUM_DUMMY_SZ 8 #define DDMA_CH_CHKSUM_CNT BIT(24) diff --git a/include/rtl8814a_sreset.h b/include/rtl8814a_sreset.h index 5d95e1f..d65cb98 100644 --- a/include/rtl8814a_sreset.h +++ b/include/rtl8814a_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL88814A_SRESET_H_ #define _RTL8814A_SRESET_H_ diff --git a/include/rtl8814a_xmit.h b/include/rtl8814a_xmit.h index 5881aaa..e3b6311 100755 --- a/include/rtl8814a_xmit.h +++ b/include/rtl8814a_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8814A_XMIT_H__ #define __RTL8814A_XMIT_H__ @@ -223,9 +218,10 @@ typedef struct txdescriptor_8814 { /* Dword 7 */ -#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#ifdef CONFIG_PCI_HCI #define SET_TX_DESC_TX_BUFFER_SIZE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) -#else +#endif +#if defined(CONFIG_SDIO_HCI)|| defined(CONFIG_USB_HCI) #define SET_TX_DESC_TX_DESC_CHECKSUM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) #endif #define SET_TX_DESC_NTX_MAP_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 20, 4, __Value) @@ -238,9 +234,10 @@ typedef struct txdescriptor_8814 { #define SET_TX_DESC_DATA_RC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value) #define SET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 14, 1, __Value) #define SET_TX_DESC_HWSEQ_EN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) -#if (DEV_BUS_TYPE != RT_SDIO_INTERFACE) +#if defined(CONFIG_PCI_HCI)|| defined(CONFIG_USB_HCI) #define SET_TX_DESC_NEXT_HEAD_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) -#else +#endif +#ifdef CONFIG_SDIO_HCI #define SET_TX_DESC_SDIO_SEQ_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value) /* 20130415 KaiYuan add for 8814AS */ #endif #define SET_TX_DESC_TAIL_PAGE_L_8814A(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value) @@ -270,6 +267,7 @@ void rtl8814a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 #if defined(CONFIG_CONCURRENT_MODE) void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc); #endif +void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc); #ifdef CONFIG_USB_HCI s32 rtl8814au_init_xmit_priv(PADAPTER padapter); diff --git a/include/rtl8821a_spec.h b/include/rtl8821a_spec.h index f5edf37..1379ffc 100644 --- a/include/rtl8821a_spec.h +++ b/include/rtl8821a_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8821A_SPEC_H__ #define __RTL8821A_SPEC_H__ diff --git a/include/rtl8821a_xmit.h b/include/rtl8821a_xmit.h index d7a97e3..5d973cd 100644 --- a/include/rtl8821a_xmit.h +++ b/include/rtl8821a_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8821A_XMIT_H__ #define __RTL8821A_XMIT_H__ diff --git a/include/rtl8821c_dm.h b/include/rtl8821c_dm.h index 6cdcb0a..b1e4fe6 100644 --- a/include/rtl8821c_dm.h +++ b/include/rtl8821c_dm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8812C_DM_H__ #define __RTL8812C_DM_H__ @@ -24,7 +19,5 @@ void rtl8821c_phy_init_dm_priv(PADAPTER); void rtl8821c_phy_deinit_dm_priv(PADAPTER); void rtl8821c_phy_init_haldm(PADAPTER); void rtl8821c_phy_haldm_watchdog(PADAPTER); -void rtl8821c_phy_haldm_in_lps(PADAPTER); -void rtl8821c_phy_haldm_watchdog_in_lps(PADAPTER); #endif diff --git a/include/rtl8821c_hal.h b/include/rtl8821c_hal.h index c3020f4..41d222e 100644 --- a/include/rtl8821c_hal.h +++ b/include/rtl8821c_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8821C_HAL_H_ #define _RTL8821C_HAL_H_ @@ -49,7 +44,7 @@ #ifndef MAX_RECVBUF_SZ #ifndef CONFIG_MINIMAL_MEMORY_USAGE /* 8821C - RX FIFO :16K ,for RX agg DMA mode = 16K, Rx agg USB mode could large than 16k*/ - /* #define MAX_RECVBUF_SZ (HALMAC_RX_FIFO_SIZE_8821C + RX_FIFO_EXPANDING)*/ + /* #define MAX_RECVBUF_SZ (16384 + RX_FIFO_EXPANDING)*/ /* For Max throughput issue , need to use USB AGG mode to replace DMA AGG mode*/ #define MAX_RECVBUF_SZ (32768) @@ -71,15 +66,19 @@ /*#endif*/ #elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - #define MAX_RECVBUF_SZ (HALMAC_RX_FIFO_SIZE_8821C + RX_FIFO_EXPANDING) + #define MAX_RECVBUF_SZ (16384 + RX_FIFO_EXPANDING) #endif void init_hal_spec_rtl8821c(PADAPTER); /* MP Functions */ #ifdef CONFIG_MP_INCLUDED -void rtl8821c_phy_init_haldm(PADAPTER); /* rtw_mp.c */ void rtl8821c_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ void rtl8821c_mp_config_rfpath(PADAPTER); /* hal_mp.c */ #endif +void rtl8821c_dl_rsvd_page(PADAPTER adapter, u8 mstatus); + +#ifdef CONFIG_PCI_HCI +u16 get_txbd_rw_reg(u16 q_idx); +#endif #endif /* _RTL8821C_HAL_H_ */ diff --git a/include/rtl8821c_spec.h b/include/rtl8821c_spec.h index 0ee5473..949f349 100644 --- a/include/rtl8821c_spec.h +++ b/include/rtl8821c_spec.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #ifndef __RTL8821C_SPEC_H__ #define __RTL8821C_SPEC_H__ @@ -33,8 +29,7 @@ #define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */ -#define REG_TSFTR1 REG_FREERUN_CNT_8821C /* hal_com.c */ -#define REG_RXFLTMAP2 REG_RXFLTMAP_8821C /* rtw_mp.c */ + #define REG_WOWLAN_WAKE_REASON 0x01C7 #define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8821C @@ -117,7 +112,18 @@ #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ -#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ +/* RFE */ +#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ +#define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */ +#define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */ +#define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */ +#define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */ +#define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */ +#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ +#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ +#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ +#define bMask_RFEInv_Jaguar 0x3FF00000 +#define bMask_AntselPathFollow_Jaguar 0x00030000 #define rOFDM1_LSTF 0xD00 #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ @@ -136,7 +142,6 @@ #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ -#define rB_RFE_Pinmux_Jaguar 0xEB0 /* hal_mp.c */ /* Page1(0x100) */ #define bBBResetB 0x100 @@ -182,8 +187,8 @@ struct hw_port_reg { u32 net_type; /*reg_offset*/ u8 net_type_shift; - u32 macaddr; /*reg_offset*/ - u32 bssid; /*reg_offset*/ + u32 macaddr; /*reg_offset*/ + u32 bssid; /*reg_offset*/ u32 bcn_ctl; /*reg_offset*/ u32 tsf_rst; /*reg_offset*/ u8 tsf_rst_bit; @@ -191,6 +196,7 @@ struct hw_port_reg { u8 bcn_space_shift; u16 bcn_space_mask; u32 ps_aid; /*reg_offset*/ + u32 ta; /*reg_offset*/ }; #endif /* __RTL8192E_SPEC_H__ */ diff --git a/include/rtl8821ce_hal.h b/include/rtl8821ce_hal.h index c6334bd..426002a 100755 --- a/include/rtl8821ce_hal.h +++ b/include/rtl8821ce_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8821CE_HAL_H_ #define _RTL8821CE_HAL_H_ diff --git a/include/rtl8821cs_hal.h b/include/rtl8821cs_hal.h index 97df6e9..ceecc15 100644 --- a/include/rtl8821cs_hal.h +++ b/include/rtl8821cs_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8821CS_HAL_H_ #define _RTL8821CS_HAL_H_ diff --git a/include/rtl8821cu_hal.h b/include/rtl8821cu_hal.h index 63c25a8..aec4372 100644 --- a/include/rtl8821cu_hal.h +++ b/include/rtl8821cu_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2016 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8821CU_HAL_H_ #define _RTL8821CU_HAL_H_ diff --git a/include/rtl8822b_hal.h b/include/rtl8822b_hal.h index 191dd6f..076f824 100644 --- a/include/rtl8822b_hal.h +++ b/include/rtl8822b_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8822B_HAL_H_ #define _RTL8822B_HAL_H_ @@ -25,7 +20,11 @@ #include "../hal/halmac/halmac_api.h" /* MAC REG definition */ -#define MAX_RECVBUF_SZ HALMAC_RX_FIFO_SIZE_8822B +#ifdef CONFIG_SUPPORT_TRX_SHARED +#define MAX_RECVBUF_SZ 46080 /* 45KB, TX: (256-64)KB */ +#else /* !CONFIG_SUPPORT_TRX_SHARED */ +#define MAX_RECVBUF_SZ 24576 /* 24KB, TX: 256KB */ +#endif /* !CONFIG_SUPPORT_TRX_SHARED */ /* * MAC Register definition @@ -39,8 +38,7 @@ #define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8822B /* hal_com.c */ -#define REG_TSFTR1 REG_FREERUN_CNT_8822B /* hal_com.c */ -#define REG_RXFLTMAP2 REG_RXFLTMAP_8822B /* rtw_mp.c */ + #define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c */ #define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8822B /* hal_com.c */ @@ -130,7 +128,6 @@ #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ -#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ #define rOFDM1_LSTF 0xD00 #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ @@ -149,7 +146,22 @@ #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ -#define rB_RFE_Pinmux_Jaguar 0xEB0 /* hal_mp.c */ +/* RFE */ +#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ +#define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */ +#define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */ +#define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */ +#define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */ +#define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */ +#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ +#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ +#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ +#define bMask_RFEInv_Jaguar 0x3FF00000 +#define bMask_AntselPathFollow_Jaguar 0x00030000 + +#define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux*/ +#define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux*/ +#define rA_RFE_Sel_Jaguar2 0x1990 /* Page1(0x100) */ #define bBBResetB 0x100 @@ -202,10 +214,10 @@ void rtl8822b_init_hal_spec(PADAPTER); /* hal/hal_com.c */ #ifdef CONFIG_MP_INCLUDED /* MP Functions */ #include /* struct mp_priv */ -void rtl8822b_phy_init_haldm(PADAPTER); /* rtw_mp.c */ void rtl8822b_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ void rtl8822b_mp_config_rfpath(PADAPTER); /* hal_mp.c */ #endif +void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus); #ifdef CONFIG_USB_HCI #include diff --git a/include/rtl8822be_hal.h b/include/rtl8822be_hal.h index 8379fab..a81445f 100755 --- a/include/rtl8822be_hal.h +++ b/include/rtl8822be_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8822BE_HAL_H_ #define _RTL8822BE_HAL_H_ @@ -26,5 +21,7 @@ /* rtl8822be_ops.c */ void UpdateInterruptMask8822BE(PADAPTER, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); +u16 get_txbd_rw_reg(u16 q_idx); + #endif /* _RTL8822BE_HAL_H_ */ diff --git a/include/rtl8822bs_hal.h b/include/rtl8822bs_hal.h index 313036d..ffaddee 100644 --- a/include/rtl8822bs_hal.h +++ b/include/rtl8822bs_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8822BS_HAL_H_ #define _RTL8822BS_HAL_H_ @@ -25,6 +20,10 @@ /* rtl8822bs_ops.c */ void rtl8822bs_set_hal_ops(PADAPTER); +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) +void rtl8822bs_disable_interrupt_but_cpwm2(PADAPTER adapter); +#endif + /* rtl8822bs_xmit.c */ s32 rtl8822bs_dequeue_writeport(PADAPTER); #define _dequeue_writeport(a) rtl8822bs_dequeue_writeport(a) diff --git a/include/rtl8822bu_hal.h b/include/rtl8822bu_hal.h index df16056..39618c9 100644 --- a/include/rtl8822bu_hal.h +++ b/include/rtl8822bu_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL8822BU_HAL_H_ #define _RTL8822BU_HAL_H_ @@ -43,7 +38,14 @@ #define MAX_RECVBUF_SZ (8192+1024) #else /* !PLATFORM_OS_CE */ #ifndef CONFIG_MINIMAL_MEMORY_USAGE + #ifdef CONFIG_PLATFORM_NOVATEK_NT72668 + #define MAX_RECVBUF_SZ (15360) /* 15k */ + #elif defined(CONFIG_PLATFORM_HISILICON) + /* use 16k to workaround for HISILICON platform */ + #define MAX_RECVBUF_SZ (16384) + #else #define MAX_RECVBUF_SZ (32768) + #endif #else #define MAX_RECVBUF_SZ (4000) #endif diff --git a/include/rtw_android.h b/include/rtw_android.h index 2015afe..9d8eb0b 100644 --- a/include/rtw_android.h +++ b/include/rtw_android.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_ANDROID_H__ #define __RTW_ANDROID_H__ @@ -74,6 +69,7 @@ enum ANDROID_WIFI_CMD { ANDROID_WIFI_CMD_GTK_REKEY_OFFLOAD, #endif /* CONFIG_GTK_OL */ ANDROID_WIFI_CMD_P2P_DISABLE, + ANDROID_WIFI_CMD_SET_AEK, ANDROID_WIFI_CMD_DRIVERVERSION, ANDROID_WIFI_CMD_MAX }; @@ -97,11 +93,11 @@ int wifi_set_power(int on, unsigned long msec); int wifi_get_mac_addr(unsigned char *buf); void *wifi_get_country_code(char *ccode); #else -static int rtw_android_wifictrl_func_add(void) +static inline int rtw_android_wifictrl_func_add(void) { return 0; } -static void rtw_android_wifictrl_func_del(void) {} +static inline void rtw_android_wifictrl_func_del(void) {} #endif /* defined(RTW_ENABLE_WIFI_CONTROL_FUNC) */ #ifdef CONFIG_GPIO_WAKEUP diff --git a/include/rtw_ap.h b/include/rtw_ap.h index 6245f58..7ad94d6 100644 --- a/include/rtw_ap.h +++ b/include/rtw_ap.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_AP_H_ #define __RTW_AP_H_ @@ -30,12 +25,16 @@ extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info void init_mlme_ap_info(_adapter *padapter); void free_mlme_ap_info(_adapter *padapter); +u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period + , const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie); /* void update_BCNTIM(_adapter *padapter); */ void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len); void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index); void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *tag); #define update_beacon(adapter, ie_id, oui, tx) _update_beacon((adapter), (ie_id), (oui), (tx), __func__) -void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_update_bw); + +void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta); + void expire_timeout_chk(_adapter *padapter); void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta); void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter); @@ -44,11 +43,15 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len); void rtw_ap_restore_network(_adapter *padapter); #if CONFIG_RTW_MACADDR_ACL -void rtw_set_macaddr_acl(_adapter *adapter, int mode); -int rtw_acl_add_sta(_adapter *adapter, const u8 *addr); -int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr); +void rtw_macaddr_acl_init(_adapter *adapter, u8 period); +void rtw_macaddr_acl_deinit(_adapter *adapter, u8 period); +void rtw_macaddr_acl_clear(_adapter *adapter, u8 period); +void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode); +int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr); +int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr); #endif /* CONFIG_RTW_MACADDR_ACL */ +u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk); u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta); int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid); int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx); @@ -67,22 +70,43 @@ void stop_ap_mode(_adapter *padapter); #endif void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset); -bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow); +u8 rtw_ap_chbw_decision(_adapter *adapter, u8 ifbmp, u8 excl_ifbmp + , s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow); #ifdef CONFIG_AUTO_AP_MODE +void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos); extern void rtw_start_auto_ap(_adapter *adapter); #endif /* CONFIG_AUTO_AP_MODE */ -#endif /* end of CONFIG_AP_MODE */ +void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap); +u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len); +u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems); +void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len); +void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems); +void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems); -#endif void update_bmc_sta(_adapter *padapter); +#ifdef CONFIG_BMC_TX_RATE_SELECT +void rtw_update_bmc_sta_tx_rate(_adapter *adapter); +#endif + void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field); void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len); +#ifdef CONFIG_80211N_HT int rtw_ht_operation_update(_adapter *padapter); +#endif /* CONFIG_80211N_HT */ +u8 rtw_ap_sta_states_check(_adapter *adapter); + +#ifdef CONFIG_FW_HANDLE_TXBCN +#define rtw_ap_get_nums(adapter) (adapter_to_dvobj(adapter)->nr_ap_if) +bool rtw_ap_nums_check(_adapter *adapter); +#endif #ifdef CONFIG_SWTIMER_BASED_TXBCN void tx_beacon_handlder(struct dvobj_priv *pdvobj); void tx_beacon_timer_handlder(void *ctx); -#endif +#endif /*CONFIG_SWTIMER_BASED_TXBCN*/ + +#endif /* end of CONFIG_AP_MODE */ +#endif /*__RTW_AP_H_*/ diff --git a/include/rtw_beamforming.h b/include/rtw_beamforming.h index 919388b..cca5bcc 100644 --- a/include/rtw_beamforming.h +++ b/include/rtw_beamforming.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_BEAMFORMING_H_ #define __RTW_BEAMFORMING_H_ @@ -106,7 +101,7 @@ struct beamformee_entry { /* Used to fill Reg6E4 to fill Mac address of CSI report frame */ u8 mac_addr[ETH_ALEN]; /* Sounding BandWidth */ - CHANNEL_WIDTH sound_bw; + enum channel_width sound_bw; u16 sound_period; enum beamforming_cap cap; @@ -121,7 +116,7 @@ struct beamformee_entry { u8 bApplySounding; /* information for sounding judgement */ - u32 tx_timestamp; + systime tx_timestamp; u64 tx_bytes; u16 LogStatusFailCnt:5; /* 0~21 */ @@ -213,6 +208,7 @@ struct beamforming_info { u32 beamformee_mu_reg_maping; u8 first_mu_bfee_index; u8 mu_bfer_curidx; + u8 cur_csi_rpt_rate; struct sounding_info sounding_info; /* schedule regular timer for sounding */ @@ -262,6 +258,21 @@ void rtw_bf_update_traffic(PADAPTER); #define beamforming_wk_cmd rtw_bf_cmd #define update_attrib_txbf_info rtw_bf_update_attrib +#define HT_BF_CAP(adapter) ((adapter)->mlmepriv.htpriv.beamform_cap) +#define VHT_BF_CAP(adapter) ((adapter)->mlmepriv.vhtpriv.beamform_cap) + +#define IS_HT_BEAMFORMEE(adapter) \ + (HT_BF_CAP(adapter) & \ + (BEAMFORMING_HT_BEAMFORMEE_ENABLE)) + +#define IS_VHT_BEAMFORMEE(adapter) \ + (VHT_BF_CAP(adapter) & \ + (BEAMFORMING_VHT_BEAMFORMEE_ENABLE | \ + BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) + +#define IS_BEAMFORMEE(adapter) (IS_HT_BEAMFORMEE(adapter) | \ + IS_VHT_BEAMFORMEE(adapter)) + #else /* !RTW_BEAMFORMING_VERSION_2 */ #if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/ @@ -316,8 +327,8 @@ struct beamforming_entry { u16 mac_id; /* Used to Set Reg42C in IBSS mode. */ u16 p_aid; /* Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ u16 g_id; - u8 mac_addr[6];/* Used to fill Reg6E4 to fill Mac address of CSI report frame. */ - CHANNEL_WIDTH sound_bw; /* Sounding BandWidth */ + u8 mac_addr[ETH_ALEN];/* Used to fill Reg6E4 to fill Mac address of CSI report frame. */ + enum channel_width sound_bw; /* Sounding BandWidth */ u16 sound_period; BEAMFORMING_CAP beamforming_entry_cap; BEAMFORMING_ENTRY_STATE beamforming_entry_state; @@ -335,7 +346,7 @@ struct beamforming_entry { struct sounding_info { u8 sound_idx; - CHANNEL_WIDTH sound_bw; + enum channel_width sound_bw; SOUNDING_MODE sound_mode; u16 sound_period; }; @@ -360,8 +371,8 @@ BEAMFORMING_CAP beamforming_get_entry_beam_cap_by_mac_id(PVOID pmlmepriv , u8 ma void beamforming_notify(PADAPTER adapter); BEAMFORMING_CAP beamforming_get_beamform_cap(struct beamforming_info *pBeamInfo); -BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx); -BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx); +BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx); +BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx); void beamforming_check_sounding_success(PADAPTER Adapter, BOOLEAN status); diff --git a/include/rtw_br_ext.h b/include/rtw_br_ext.h index 1df8dc6..54ba75e 100644 --- a/include/rtw_br_ext.h +++ b/include/rtw_br_ext.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_BR_EXT_H_ #define _RTW_BR_EXT_H_ diff --git a/include/rtw_bt_mp.h b/include/rtw_bt_mp.h index 0383d08..a152d18 100644 --- a/include/rtw_bt_mp.h +++ b/include/rtw_bt_mp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_BT_MP_H #define __RTW_BT_MP_H @@ -190,7 +185,7 @@ MPTBT_FwC2hBtMpCtrl( u1Byte length ); -void MPh2c_timeout_handle(struct timer_list *t); +void MPh2c_timeout_handle(void *FunctionContext); VOID mptbt_BtControlProcess( PADAPTER Adapter, diff --git a/include/rtw_btcoex.h b/include/rtw_btcoex.h index 2374fb1..fd42248 100644 --- a/include/rtw_btcoex.h +++ b/include/rtw_btcoex.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,9 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ +#ifdef CONFIG_BT_COEXIST + #ifndef __RTW_BTCOEX_H__ #define __RTW_BTCOEX_H__ @@ -369,6 +366,7 @@ struct bt_coex_info { void rtw_btcoex_Initialize(PADAPTER); void rtw_btcoex_PowerOnSetting(PADAPTER padapter); +void rtw_btcoex_AntInfoSetting(PADAPTER padapter); void rtw_btcoex_PowerOffSetting(PADAPTER padapter); void rtw_btcoex_PreLoadFirmware(PADAPTER padapter); void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly); @@ -384,6 +382,8 @@ void rtw_btcoex_BtMpRptNotify(PADAPTER, u8 length, u8 *tmpBuf); void rtw_btcoex_SuspendNotify(PADAPTER, u8 state); void rtw_btcoex_HaltNotify(PADAPTER); void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type); +void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length); +void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id); void rtw_btcoex_SwitchBtTRxMask(PADAPTER); void rtw_btcoex_Switch(PADAPTER, u8 enable); u8 rtw_btcoex_IsBtDisabled(PADAPTER); @@ -449,3 +449,7 @@ void rtw_btcoex_LPS_Enter(PADAPTER padapter); u8 rtw_btcoex_LPS_Leave(PADAPTER padapter); #endif /* __RTW_BTCOEX_H__ */ +#endif /* CONFIG_BT_COEXIST */ + +void rtw_btcoex_set_ant_info(PADAPTER padapter); + diff --git a/include/rtw_btcoex_wifionly.h b/include/rtw_btcoex_wifionly.h index 11d36f7..93087eb 100644 --- a/include/rtw_btcoex_wifionly.h +++ b/include/rtw_btcoex_wifionly.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,17 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_BTCOEX_WIFIONLY_H__ #define __RTW_BTCOEX_WIFIONLY_H__ void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter); void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter); +void rtw_btcoex_wifionly_connect_notify(PADAPTER padapter); void rtw_btcoex_wifionly_hw_config(PADAPTER padapter); void rtw_btcoex_wifionly_initialize(PADAPTER padapter); +void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter); #endif diff --git a/include/rtw_byteorder.h b/include/rtw_byteorder.h index 70482d2..8e6bb7a 100644 --- a/include/rtw_byteorder.h +++ b/include/rtw_byteorder.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTL871X_BYTEORDER_H_ #define _RTL871X_BYTEORDER_H_ diff --git a/include/rtw_cmd.h b/include/rtw_cmd.h index 63387e9..9d1994a 100644 --- a/include/rtw_cmd.h +++ b/include/rtw_cmd.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_CMD_H_ #define __RTW_CMD_H_ @@ -60,9 +55,8 @@ enum { struct cmd_priv { _sema cmd_queue_sema; /* _sema cmd_done_sema; */ - /*_sema terminate_cmdthread_sema;*/ _sema start_cmdthread_sema; - _completion cmdthread_comp; + _queue cmd_queue; u8 cmd_seq; u8 *cmd_buf; /* shall be non-paged, and 4 bytes aligned */ @@ -74,7 +68,7 @@ struct cmd_priv { u32 rsp_cnt; ATOMIC_T cmdthd_running; /* u8 cmdthd_running; */ - u8 stop_req; + _adapter *padapter; _mutex sctx_mutex; }; @@ -92,7 +86,7 @@ struct evt_obj { struct evt_priv { #ifdef CONFIG_EVENT_THREAD_MODE _sema evt_notify; - _sema terminate_evtthread_sema; + _queue evt_queue; #endif @@ -211,9 +205,21 @@ u8 p2p_roch_cmd(_adapter *adapter , u8 flags ); u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags); + #endif /* CONFIG_IOCTL_CFG80211 */ #endif /* CONFIG_P2P */ +#ifdef CONFIG_IOCTL_CFG80211 +u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags); +struct mgnt_tx_parm { + u8 tx_ch; + u8 no_cck; + const u8 *buf; + size_t len; + int wait_ack; +}; +#endif + #else /* #include */ #endif /* CONFIG_RTL8711FW */ @@ -240,12 +246,22 @@ enum rtw_drvextra_cmd_id { BEAMFORMING_WK_CID, LPS_CHANGE_DTIM_CID, BTINFO_WK_CID, - DFS_MASTER_WK_CID, + DFS_RADAR_DETECT_WK_CID, + DFS_RADAR_DETECT_EN_DEC_WK_CID, SESSION_TRACKER_WK_CID, EN_HW_UPDATE_TSF_WK_CID, + PERIOD_TSF_UPDATE_END_WK_CID, TEST_H2C_CID, MP_CMD_WK_CID, CUSTOMER_STR_WK_CID, +#ifdef CONFIG_RTW_REPEATER_SON + RSON_SCAN_WK_CID, +#endif + MGNT_TX_WK_CID, +#ifdef CONFIG_MCC_MODE + MCC_SET_DURATION_WK_CID, +#endif /* CONFIG_MCC_MODE */ + REQ_PER_CMD_WK_CID, MAX_WK_CID }; @@ -330,7 +346,9 @@ Command Mode struct createbss_parm { bool adhoc; - /* used by AP mode now */ + /* used by AP/Mesh mode now */ + u8 ifbmp; + u8 excl_ifbmp; s16 req_ch; s8 req_bw; s8 req_offset; @@ -374,6 +392,11 @@ struct sitesurvey_parm { u8 ch_num; NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; + + u32 token; /* 80211k use it to identify caller */ + u16 duration; /* 0: use default, otherwise: channel scan time */ + u8 igi; /* 0: use defalut */ + u8 bw; /* 0: use default */ }; /* @@ -405,7 +428,6 @@ when 802.1x ==> keyid > 2 ==> unicast key struct setkey_parm { u8 algorithm; /* encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 */ u8 keyid; - u8 grpkey; /* 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x */ u8 set_tx; /* 1: main tx key for wep. 0: other key. */ u8 key[16]; /* this could be 40 or 104 */ }; @@ -420,10 +442,11 @@ when shared key ==> algorithm/keyid */ struct set_stakey_parm { - u8 addr[ETH_ALEN]; - u8 algorithm; - u8 keyid; - u8 key[16]; + u8 addr[ETH_ALEN]; + u8 algorithm; + u8 keyid; + u8 key[16]; + u8 gk; }; struct set_stakey_rsp { @@ -942,11 +965,6 @@ struct LedBlink_param { PVOID pLed; }; -/*H2C Handler index: 61 */ -struct SetChannelSwitch_param { - u8 new_ch_no; -}; - /*H2C Handler index: 62 */ struct TDLSoption_param { u8 addr[ETH_ALEN]; @@ -986,14 +1004,22 @@ struct RunInThread_param { #define H2C_RESERVED 0x07 #define H2C_ENQ_HEAD 0x08 #define H2C_ENQ_HEAD_FAIL 0x09 +#define H2C_CMD_FAIL 0x0A extern u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr); extern u8 rtw_setstandby_cmd(_adapter *padapter, uint action); -u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, struct rtw_ieee80211_channel *ch, int ch_num); - +void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm); +u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm); u8 rtw_create_ibss_cmd(_adapter *adapter, int flags); u8 rtw_startbss_cmd(_adapter *adapter, int flags); -u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags, s16 req_ch, s8 req_bw, s8 req_offset); + +#define REQ_CH_NONE -1 +#define REQ_BW_NONE -1 +#define REQ_BW_ORI -2 +#define REQ_OFFSET_NONE -1 + +u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags + , u8 ifbmp, u8 excl_ifbmp, s16 req_ch, s8 req_bw, s8 req_offset); extern u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch); @@ -1003,7 +1029,7 @@ extern u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enque extern u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork); u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags); -extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue); +extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags); extern u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset); extern u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset); extern u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr); @@ -1024,7 +1050,7 @@ extern u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr); extern u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq); /* add for CONFIG_IEEE80211W, none 11w also can use */ extern u8 rtw_reset_securitypriv_cmd(_adapter *padapter); -extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter); +extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter, u8 lock_scanned_queue, int flags); extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter); u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue); @@ -1043,21 +1069,17 @@ u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta); extern u8 rtw_ps_cmd(_adapter *padapter); +#ifdef CONFIG_DFS +void rtw_dfs_ch_switch_hdl(struct dvobj_priv *dvobj); +#endif + #ifdef CONFIG_AP_MODE u8 rtw_chk_hi_queue_cmd(_adapter *padapter); #ifdef CONFIG_DFS_MASTER -u8 rtw_dfs_master_cmd(_adapter *adapter, bool enqueue); -void rtw_dfs_master_timer_hdl(void *ctx); -void rtw_dfs_master_enable(_adapter *adapter, u8 ch, u8 bw, u8 offset); -void rtw_dfs_master_disable(_adapter *adapter, u8 ch, u8 bw, u8 offset, bool by_others); -enum { - MLME_STA_CONNECTING, - MLME_STA_CONNECTED, - MLME_STA_DISCONNECTED, - MLME_AP_STARTED, - MLME_AP_STOPPED, -}; -void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action); +u8 rtw_dfs_rd_cmd(_adapter *adapter, bool enqueue); +void rtw_dfs_rd_timer_hdl(void *ctx); +void rtw_dfs_rd_en_decision(_adapter *adapter, u8 mlme_act, u8 excl_ifbmp); +u8 rtw_dfs_rd_en_decision_cmd(_adapter *adapter); #endif /* CONFIG_DFS_MASTER */ #endif /* CONFIG_AP_MODE */ @@ -1068,14 +1090,15 @@ u8 rtw_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length); u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len); u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter); +u8 rtw_periodic_tsf_update_end_cmd(_adapter *adapter); -u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue); +u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags); u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig); u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig); extern u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed); -extern u8 rtw_set_csa_cmd(_adapter *padapter, u8 new_ch_no); +extern u8 rtw_set_csa_cmd(_adapter *adapter); extern u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option); u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags); @@ -1092,12 +1115,22 @@ u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt); u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length); #endif +#ifdef CONFIG_RTW_REPEATER_SON +#define RSON_SCAN_PROCESS 10 +#define RSON_SCAN_DISABLE 11 +u8 rtw_rson_scan_wk_cmd(_adapter *adapter, int op); +#endif + u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context); u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta); u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); +#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW) +u8 rtw_req_per_cmd(_adapter * adapter); +#endif + u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf); extern void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); @@ -1194,6 +1227,7 @@ enum rtw_h2c_cmd { GEN_CMD_CODE(_RunInThreadCMD), /*64*/ GEN_CMD_CODE(_AddBARsp) , /*65*/ + GEN_CMD_CODE(_RM_POST_EVENT), /*66*/ MAX_H2CCMD }; @@ -1281,6 +1315,7 @@ struct _cmd_callback rtw_cmd_callback[] = { {GEN_CMD_CODE(_RunInThreadCMD), NULL},/*64*/ {GEN_CMD_CODE(_AddBARsp), NULL}, /*65*/ + {GEN_CMD_CODE(_RM_POST_EVENT), NULL}, /*66*/ }; #endif diff --git a/include/rtw_debug.h b/include/rtw_debug.h index 5ce87ae..e13413e 100644 --- a/include/rtw_debug.h +++ b/include/rtw_debug.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_DEBUG_H__ #define __RTW_DEBUG_H__ @@ -68,15 +63,11 @@ extern void rtl871x_cedbg(const char *fmt, ...); #define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) #define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) #define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) -#define _RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) -#define _RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) #define RTW_DBG_EXPR(EXPR) do {} while (0) #define RTW_DBGDUMP 0 /* 'stream' for _dbgdump */ -/* don't use these 3 APIs anymore, will be removed later */ -#define RT_TRACE(_Comp, _Level, Fmt) do {} while (0) #undef _dbgdump @@ -84,18 +75,29 @@ extern void rtl871x_cedbg(const char *fmt, ...); #if defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_XP) #define _dbgdump DbgPrint + #define KERN_CONT #define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg) #elif defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_CE) #define _dbgdump rtl871x_cedbg + #define KERN_CONT #define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg) #elif defined PLATFORM_LINUX #define _dbgdump printk + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) + #define KERN_CONT + #endif #define _seqdump seq_printf #elif defined PLATFORM_FREEBSD #define _dbgdump printf + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24)) + #define KERN_CONT + #endif #define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg) #endif +void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring, + bool _idx_show, const u8 *_hexdata, int _hexdatalen); + #ifdef CONFIG_RTW_DEBUG #ifndef _OS_INTFS_C_ @@ -147,65 +149,25 @@ extern uint rtw_drv_log_level; } \ } while (0) - #undef RTW_INFO_DUMP -#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) \ - do {\ - if (_DRV_INFO_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump("%s", DRIVER_PREFIX); \ - _dbgdump(_TitleString); \ - for (__i = 0; __i < (int)_HexDataLen; __i++) { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) \ - _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } \ - } while (0) +#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) \ + RTW_BUF_DUMP_SEL(_DRV_INFO_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen) #undef RTW_DBG_DUMP -#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) \ - do {\ - if (_DRV_DEBUG_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump("%s", DRIVER_PREFIX); \ - _dbgdump(_TitleString); \ - for (__i = 0; __i < (int)_HexDataLen; __i++) { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) \ - _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } \ - } while (0) +#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) \ + RTW_BUF_DUMP_SEL(_DRV_DEBUG_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen) #undef RTW_PRINT_DUMP -#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) \ - do {\ - if (_DRV_ALWAYS_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump("%s", DRIVER_PREFIX); \ - _dbgdump(_TitleString); \ - for (__i = 0; __i < (int)_HexDataLen; __i++) { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) \ - _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } \ - } while (0) +#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) \ + RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, RTW_DBGDUMP, _TitleString, _FALSE, _HexData, _HexDataLen) /* without driver-defined prefix */ #undef _RTW_PRINT #define _RTW_PRINT(fmt, arg...) \ do {\ if (_DRV_ALWAYS_ <= rtw_drv_log_level) {\ - _dbgdump(fmt, ##arg);\ + _dbgdump(KERN_CONT fmt, ##arg);\ } \ } while (0) @@ -213,7 +175,7 @@ extern uint rtw_drv_log_level; #define _RTW_ERR(fmt, arg...) \ do {\ if (_DRV_ERR_ <= rtw_drv_log_level) {\ - _dbgdump(fmt, ##arg);\ + _dbgdump(KERN_CONT fmt, ##arg);\ } \ } while (0) @@ -222,7 +184,7 @@ extern uint rtw_drv_log_level; #define _RTW_WARN(fmt, arg...) \ do {\ if (_DRV_WARNING_ <= rtw_drv_log_level) {\ - _dbgdump(fmt, ##arg);\ + _dbgdump(KERN_CONT fmt, ##arg);\ } \ } while (0) @@ -230,7 +192,7 @@ extern uint rtw_drv_log_level; #define _RTW_INFO(fmt, arg...) \ do {\ if (_DRV_INFO_ <= rtw_drv_log_level) {\ - _dbgdump(fmt, ##arg);\ + _dbgdump(KERN_CONT fmt, ##arg);\ } \ } while (0) @@ -238,39 +200,11 @@ extern uint rtw_drv_log_level; #define _RTW_DBG(fmt, arg...) \ do {\ if (_DRV_DEBUG_ <= rtw_drv_log_level) {\ - _dbgdump(fmt, ##arg);\ + _dbgdump(KERN_CONT fmt, ##arg);\ } \ } while (0) -#undef _RTW_INFO_DUMP -#define _RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) \ - if (_DRV_INFO_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump(_TitleString); \ - for (__i = 0; __i<(int)_HexDataLen; __i++) \ - { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } - -#undef _RTW_DBG_DUMP -#define _RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) \ - if (_DRV_DEBUG_ <= rtw_drv_log_level) { \ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - _dbgdump(_TitleString); \ - for (__i = 0; __i<(int)_HexDataLen; __i++) \ - { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } - /* other debug APIs */ #undef RTW_DBG_EXPR #define RTW_DBG_EXPR(EXPR) do { if (_DRV_DEBUG_ <= rtw_drv_log_level) EXPR; } while (0) @@ -303,31 +237,12 @@ extern uint rtw_drv_log_level; } while (0) /* dump message to selected 'stream' */ -#undef _RTW_DUMP_SEL -#define _RTW_DUMP_SEL(sel, _HexData, _HexDataLen) \ - do {\ - if (sel == RTW_DBGDUMP) {\ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - for (__i = 0; __i < (int)_HexDataLen; __i++) { \ - _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) \ - _dbgdump("\n"); \ - } \ - _dbgdump("\n"); \ - } \ - else {\ - int __i; \ - u8 *ptr = (u8 *)_HexData; \ - for (__i = 0; __i < (int)_HexDataLen; __i++) { \ - _seqdump(sel, "%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ - if (((__i + 1) % 16) == 0) \ - _seqdump(sel, "\n"); \ - } \ - _seqdump(sel, "\n"); \ - } \ - } while (0) +#undef RTW_DUMP_SEL +#define RTW_DUMP_SEL(sel, _HexData, _HexDataLen) \ + RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, NULL, _FALSE, _HexData, _HexDataLen) +#define RTW_MAP_DUMP_SEL(sel, _TitleString, _HexData, _HexDataLen) \ + RTW_BUF_DUMP_SEL(_DRV_ALWAYS_, sel, _TitleString, _TRUE, _HexData, _HexDataLen) #endif /* defined(_seqdump) */ @@ -351,7 +266,7 @@ void bb_reg_dump(void *sel, _adapter *adapter); void bb_reg_dump_ex(void *sel, _adapter *adapter); void rf_reg_dump(void *sel, _adapter *adapter); -void rtw_sink_rtp_seq_dbg(_adapter *adapter, _pkt *pkt); +void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos); struct sta_info; void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta); @@ -391,15 +306,16 @@ int proc_get_rf_info(struct seq_file *m, void *v); int proc_get_scan_param(struct seq_file *m, void *v); ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_scan_abort(struct seq_file *m, void *v); -#ifdef CONFIG_SCAN_BACKOP -int proc_get_backop_flags_sta(struct seq_file *m, void *v); -ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_backop_flags_ap(struct seq_file *m, void *v); -ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#endif /* CONFIG_SCAN_BACKOP */ +#ifdef CONFIG_RTW_REPEATER_SON +int proc_get_rson_data(struct seq_file *m, void *v); +ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif int proc_get_survey_info(struct seq_file *m, void *v); ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_ap_info(struct seq_file *m, void *v); +#ifdef ROKU_PRIVATE +int proc_get_infra_ap(struct seq_file *m, void *v); +#endif /* ROKU_PRIVATE */ ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_trx_info(struct seq_file *m, void *v); ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); @@ -413,8 +329,11 @@ ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t cou int proc_get_rx_cnt_dump(struct seq_file *m, void *v); ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif -int proc_get_dis_pwt(struct seq_file *m, void *v); -ssize_t proc_set_dis_pwt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +#ifdef CONFIG_AP_MODE +int proc_get_bmc_tx_rate(struct seq_file *m, void *v); +ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /*CONFIG_AP_MODE*/ int proc_get_ps_dbg_info(struct seq_file *m, void *v); ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); @@ -424,16 +343,17 @@ bool rtw_fwdl_test_trigger_wintint_rdy_fail(void); ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void); ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#ifdef CONFIG_DFS_MASTER -int proc_get_dfs_master_test_case(struct seq_file *m, void *v); -ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -#endif /* CONFIG_DFS_MASTER */ u32 rtw_get_wait_hiq_empty_ms(void); ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); void rtw_sta_linking_test_set_start(void); bool rtw_sta_linking_test_wait_done(void); bool rtw_sta_linking_test_force_fail(void); ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#ifdef CONFIG_AP_MODE +u16 rtw_ap_linking_test_force_auth_fail(void); +u16 rtw_ap_linking_test_force_asoc_fail(void); +ssize_t proc_set_ap_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif int proc_get_rx_stat(struct seq_file *m, void *v); int proc_get_tx_stat(struct seq_file *m, void *v); @@ -452,10 +372,15 @@ ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size int proc_get_trx_info_debug(struct seq_file *m, void *v); +#ifdef CONFIG_HUAWEI_PROC +int proc_get_huawei_trx_info(struct seq_file *m, void *v); +#endif + int proc_get_rx_signal(struct seq_file *m, void *v); ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_hw_status(struct seq_file *m, void *v); ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_mac_rptbuf(struct seq_file *m, void *v); #ifdef CONFIG_80211N_HT int proc_get_ht_enable(struct seq_file *m, void *v); @@ -467,8 +392,6 @@ ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t co int proc_get_ampdu_enable(struct seq_file *m, void *v); ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); -int proc_get_mac_rptbuf(struct seq_file *m, void *v); - void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter); int proc_get_rx_ampdu(struct seq_file *m, void *v); ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); @@ -544,12 +467,26 @@ int proc_get_int_logs(struct seq_file *m, void *v); int proc_get_rx_ring(struct seq_file *m, void *v); int proc_get_tx_ring(struct seq_file *m, void *v); int proc_get_pci_aspm(struct seq_file *m, void *v); +int proc_get_pci_conf_space(struct seq_file *m, void *v); +ssize_t proc_set_pci_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_pci_bridge_conf_space(struct seq_file *m, void *v); +ssize_t proc_set_pci_bridge_conf_space(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + + +#ifdef DBG_TXBD_DESC_DUMP +int proc_get_tx_ring_ext(struct seq_file *m, void *v); +ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif #endif #ifdef CONFIG_WOWLAN int proc_get_pattern_info(struct seq_file *m, void *v); ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_wakeup_event(struct seq_file *m, void *v); +ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data); int proc_get_wakeup_reason(struct seq_file *m, void *v); #endif @@ -568,9 +505,15 @@ ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_ #ifdef CONFIG_POWER_SAVING int proc_get_ps_info(struct seq_file *m, void *v); +#ifdef CONFIG_WMMPS_STA +int proc_get_wmmps_info(struct seq_file *m, void *v); +ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /* CONFIG_WMMPS_STA */ #endif /* CONFIG_POWER_SAVING */ #ifdef CONFIG_TDLS +int proc_get_tdls_enable(struct seq_file *m, void *v); +ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_tdls_info(struct seq_file *m, void *v); #endif @@ -603,6 +546,7 @@ ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t #ifdef CONFIG_MCC_MODE int proc_get_mcc_info(struct seq_file *m, void *v); ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); ssize_t proc_set_mcc_ap_bw20_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); ssize_t proc_set_mcc_ap_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); @@ -611,12 +555,30 @@ ssize_t proc_set_mcc_sta_bw20_target_tp(struct file *file, const char __user *bu ssize_t proc_set_mcc_sta_bw40_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); int proc_get_mcc_policy_table(struct seq_file *m, void *v); -ssize_t proc_set_mcc_policy_table(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); #endif /* CONFIG_MCC_MODE */ int proc_get_ack_timeout(struct seq_file *m, void *v); ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_fw_offload(struct seq_file *m, void *v); +ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +#ifdef CONFIG_FW_HANDLE_TXBCN +ssize_t proc_set_fw_tbtt_rpt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_fw_tbtt_rpt(struct seq_file *m, void *v); +#endif + +#ifdef CONFIG_DBG_RF_CAL +int proc_get_iqk_info(struct seq_file *m, void *v); +ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_lck_info(struct seq_file *m, void *v); +ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /*CONFIG_DBG_RF_CAL*/ + +#ifdef CONFIG_LPS_CHK_BY_TP +ssize_t proc_set_lps_chk_tp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_lps_chk_tp(struct seq_file *m, void *v); +#endif #define _drv_always_ 1 #define _drv_emerg_ 2 diff --git a/include/rtw_eeprom.h b/include/rtw_eeprom.h index 1d10c20..62304d5 100644 --- a/include/rtw_eeprom.h +++ b/include/rtw_eeprom.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_EEPROM_H__ #define __RTW_EEPROM_H__ diff --git a/include/rtw_efuse.h b/include/rtw_efuse.h index 3b14573..3052702 100644 --- a/include/rtw_efuse.h +++ b/include/rtw_efuse.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_EFUSE_H__ #define __RTW_EFUSE_H__ @@ -52,8 +47,10 @@ enum _EFUSE_DEF_TYPE { #define EFUSE_MAX_HW_SIZE 1024 #define EFUSE_MAX_SECTION_BASE 16 +#define EFUSE_MAX_SECTION_NUM 128 +#define EFUSE_MAX_BANK_SIZE 512 -/*RTL8822B 8821C BT EFUSE Define 1 BANK 128 size logical map 1024*/ +/*RTL8822B 8821C BT EFUSE Define 1 BANK 128 size logical map 1024*/ #ifdef RTW_HALMAC #define BANK_NUM 1 #define EFUSE_BT_REAL_BANK_CONTENT_LEN 128 @@ -178,6 +175,12 @@ extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; extern u8 fakeBTEfuseInitMap[]; extern u8 fakeBTEfuseModifiedMap[]; /*------------------------Export global variable----------------------------*/ +#define MAX_SEGMENT_SIZE 200 +#define MAX_SEGMENT_NUM 200 +#define MAX_BUF_SIZE (MAX_SEGMENT_SIZE*MAX_SEGMENT_NUM) +#define TMP_BUF_SIZE 100 +#define rtprintf dcmd_Store_Return_Buf + u8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size); u16 efuse_bt_GetMaxSize(PADAPTER padapter); u16 efuse_GetavailableSize(PADAPTER adapter); @@ -198,6 +201,8 @@ u8 Efuse_CalculateWordCnts(u8 word_en); void ReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ; void EFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest); u8 efuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN bPseudoTest); +#define efuse_onebyte_read(adapter, addr, data, pseudo_test) efuse_OneByteRead((adapter), (addr), (data), (pseudo_test)) + u8 efuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN bPseudoTest); void BTEfuse_PowerSwitch(PADAPTER pAdapter, u8 bWrite, u8 PwrState); @@ -208,6 +213,10 @@ void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata); u8 Efuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); void EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); void EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value); +#define efuse_logical_map_read(adapter, type, offset, value) EFUSE_ShadowRead((adapter), (type), (offset), (value)) + +BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset); +BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset); VOID hal_ReadEFuse_BT_logic_map( PADAPTER padapter, @@ -223,6 +232,7 @@ u8 EfusePgPacketWrite_BT( u8 bPseudoTest); u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter); void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray); +void rtw_efuse_analyze(PADAPTER padapter, u8 Type, u8 Fake); #define MAC_HIDDEN_MAX_BW_NUM 8 extern const u8 _mac_hidden_max_bw_to_hal_bw_cap[]; diff --git a/include/rtw_event.h b/include/rtw_event.h index 4516e5c..8e4d5d6 100644 --- a/include/rtw_event.h +++ b/include/rtw_event.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_EVENT_H_ #define _RTW_EVENT_H_ diff --git a/include/rtw_ht.h b/include/rtw_ht.h index 8ae15ed..8237bbe 100644 --- a/include/rtw_ht.h +++ b/include/rtw_ht.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,15 +11,12 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_HT_H_ #define _RTW_HT_H_ +#define HT_CAP_IE_LEN 26 +#define HT_OP_IE_LEN 22 struct ht_priv { u8 ht_option; @@ -47,9 +44,27 @@ struct ht_priv { u8 beamform_cap; u8 smps_cap; /*spatial multiplexing power save mode. 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/ + u8 op_present:1; /* ht_op is present */ + struct rtw_ieee80211_ht_cap ht_cap; + u8 ht_op[HT_OP_IE_LEN]; + +}; +#ifdef ROKU_PRIVATE +struct ht_priv_infra_ap { + + /*Infra mode, only store AP's info , not intersection of STA and AP*/ + u8 channel_width_infra_ap; + u8 sgi_20m_infra_ap; + u8 sgi_40m_infra_ap; + u8 ldpc_cap_infra_ap; + u8 stbc_cap_infra_ap; + u8 MCS_set_infra_ap[16]; + u8 Rx_ss_infra_ap; + u16 rx_highest_data_rate_infra_ap; }; +#endif /* ROKU_PRIVATE */ typedef enum AGGRE_SIZE { HT_AGG_SIZE_8K = 0, @@ -62,23 +77,6 @@ typedef enum AGGRE_SIZE { VHT_AGG_SIZE_1024K = 7, } AGGRE_SIZE_E, *PAGGRE_SIZE_E; -typedef enum _RT_HT_INF0_CAP { - RT_HT_CAP_USE_TURBO_AGGR = 0x01, - RT_HT_CAP_USE_LONG_PREAMBLE = 0x02, - RT_HT_CAP_USE_AMPDU = 0x04, - RT_HT_CAP_USE_WOW = 0x8, - RT_HT_CAP_USE_SOFTAP = 0x10, - RT_HT_CAP_USE_92SE = 0x20, - RT_HT_CAP_USE_88C_92C = 0x40, - RT_HT_CAP_USE_AP_CLIENT_MODE = 0x80, /* AP team request to reserve this bit, by Emily */ -} RT_HT_INF0_CAPBILITY, *PRT_HT_INF0_CAPBILITY; - -typedef enum _RT_HT_INF1_CAP { - RT_HT_CAP_USE_VIDEO_CLIENT = 0x01, - RT_HT_CAP_USE_JAGUAR_BCUT = 0x02, - RT_HT_CAP_USE_JAGUAR_CCUT = 0x04, -} RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY; - #define LDPC_HT_ENABLE_RX BIT0 #define LDPC_HT_ENABLE_TX BIT1 #define LDPC_HT_TEST_TX_ENABLE BIT2 @@ -89,12 +87,6 @@ typedef enum _RT_HT_INF1_CAP { #define STBC_HT_TEST_TX_ENABLE BIT2 #define STBC_HT_CAP_TX BIT3 -#define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */ -#define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */ -#define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 /* Transmiting Beamforming no matter the target supports it or not */ -#define BEAMFORMING_HT_BEAMFORMER_STEER_NUM (BIT4 | BIT5) -#define BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP (BIT6 | BIT7) - /* ------------------------------------------------------------ * The HT Control field * ------------------------------------------------------------ */ @@ -149,6 +141,9 @@ typedef enum _RT_HT_INF1_CAP { , (1 << (13+GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(((u8 *)x)-2)))-1 \ , GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(((u8 *)x)-2) +#define SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val) +#define SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 3, _val) + /* Supported MCS Set field */ #define HT_CAP_ELE_SUP_MCS_SET(_pEleStart) (((u8 *)(_pEleStart))+3) #define HT_CAP_ELE_RX_MCS_MAP(_pEleStart) HT_CAP_ELE_SUP_MCS_SET(_pEleStart) @@ -158,11 +153,14 @@ typedef enum _RT_HT_INF1_CAP { #define GET_HT_CAP_ELE_TX_MAX_SS(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 2, 2) #define GET_HT_CAP_ELE_TX_UEQM(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 4, 1) -#define HT_SUP_MCS_SET_FMT "%02x %02x %02x %02x %02x%02x%02x%02x%02x%02x" \ +#define HT_RX_MCS_BMP_FMT "%02x %02x %02x %02x %02x%02x%02x%02x%02x%02x" +#define HT_RX_MCS_BMP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \ + ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9] + +#define HT_SUP_MCS_SET_FMT HT_RX_MCS_BMP_FMT \ /* "\n%02x%02x%02x%02x%02x%02x" */\ " %uMbps %s%s%s" -#define HT_SUP_MCS_SET_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \ - ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9] \ +#define HT_SUP_MCS_SET_ARG(x) HT_RX_MCS_BMP_ARG(x) \ /*,((u8 *)(x))[10], ((u8 *)(x))[11], ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] */\ , GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(((u8 *)x)-3) \ , GET_HT_CAP_ELE_TX_MCS_DEF(((u8 *)x)-3) ? "TX_MCS_DEF " : "" \ diff --git a/include/rtw_io.h b/include/rtw_io.h index 44a1749..cafb12d 100644 --- a/include/rtw_io.h +++ b/include/rtw_io.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_IO_H_ #define _RTW_IO_H_ @@ -400,10 +395,12 @@ u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int extern void _rtw_write_port_cancel(_adapter *adapter); #ifdef DBG_IO -bool match_read_sniff_ranges(u32 addr, u16 len); -bool match_write_sniff_ranges(u32 addr, u16 len); -bool match_rf_read_sniff_ranges(u8 path, u32 addr, u32 mask); -bool match_rf_write_sniff_ranges(u8 path, u32 addr, u32 mask); +struct rtw_io_sniff_ent; +const char *rtw_io_sniff_ent_get_tag(const struct rtw_io_sniff_ent *ent); +const struct rtw_io_sniff_ent *match_read_sniff(_adapter *adapter, u32 addr, u16 len, u32 val); +const struct rtw_io_sniff_ent *match_write_sniff(_adapter *adapter, u32 addr, u16 len, u32 val); +bool match_rf_read_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask); +bool match_rf_write_sniff_ranges(_adapter *adapter, u8 path, u32 addr, u32 mask); extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line); extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line); @@ -460,10 +457,6 @@ int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller #endif /* CONFIG_SDIO_HCI */ #else /* DBG_IO */ -#define match_read_sniff_ranges(addr, len) _FALSE -#define match_write_sniff_ranges(addr, len) _FALSE -#define match_rf_read_sniff_ranges(path, addr, mask) _FALSE -#define match_rf_write_sniff_ranges(path, addr, mask) _FALSE #define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr)) #define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr)) #define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr)) diff --git a/include/rtw_ioctl.h b/include/rtw_ioctl.h index 98f05e7..4924751 100644 --- a/include/rtw_ioctl.h +++ b/include/rtw_ioctl.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_IOCTL_H_ #define _RTW_IOCTL_H_ diff --git a/include/rtw_ioctl_query.h b/include/rtw_ioctl_query.h index a74d13d..cc7b557 100644 --- a/include/rtw_ioctl_query.h +++ b/include/rtw_ioctl_query.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_IOCTL_QUERY_H_ #define _RTW_IOCTL_QUERY_H_ diff --git a/include/rtw_ioctl_rtl.h b/include/rtw_ioctl_rtl.h index ddf798f..2df8713 100644 --- a/include/rtw_ioctl_rtl.h +++ b/include/rtw_ioctl_rtl.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_IOCTL_RTL_H_ #define _RTW_IOCTL_RTL_H_ diff --git a/include/rtw_ioctl_set.h b/include/rtw_ioctl_set.h index 1f87214..2bfe570 100644 --- a/include/rtw_ioctl_set.h +++ b/include/rtw_ioctl_set.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_IOCTL_SET_H_ #define __RTW_IOCTL_SET_H_ @@ -51,17 +46,14 @@ void rtw_pnp_sleep_wk(void *context); #endif -u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key); u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode); u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid); u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep); u8 rtw_set_802_11_disassociate(_adapter *padapter); -u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num, struct rtw_ieee80211_channel *ch, int ch_num); +u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm); u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype); -u8 rtw_set_802_11_remove_wep(_adapter *padapter, u32 keyindex); u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid); u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid); -u8 rtw_set_802_11_remove_key(_adapter *padapter, NDIS_802_11_REMOVE_KEY *key); u8 rtw_validate_bssid(u8 *bssid); u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid); diff --git a/include/rtw_iol.h b/include/rtw_iol.h index b68a525..fa35a59 100644 --- a/include/rtw_iol.h +++ b/include/rtw_iol.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_IOL_H_ #define __RTW_IOL_H_ diff --git a/include/rtw_mcc.h b/include/rtw_mcc.h index 8a85fb0..718036c 100644 --- a/include/rtw_mcc.h +++ b/include/rtw_mcc.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - ******************************************************************************/ + *****************************************************************************/ #ifdef CONFIG_MCC_MODE #ifndef _RTW_MCC_H_ @@ -32,6 +28,7 @@ #define MCC_SWCH_FW_EARLY_TIME 10 /* ms */ #define MCC_EXPIRE_TIME 50 /* ms */ #define MCC_TOLERANCE_TIME 2 /* 2*2 = 4s */ +#define MCC_UPDATE_PARAMETER_THRESHOLD 5 /* ms */ #define MCC_ROLE_STA_GC_MGMT_QUEUE_MACID 0 #define MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID 1 @@ -59,8 +56,19 @@ #define MAX_MCC_NUM 2 #define MCC_STOP(adapter) (adapter->mcc_adapterpriv.mcc_tx_stop) -#define MCC_EN(adapter) (adapter->registrypriv.en_mcc) - +#define MCC_EN(adapter) (adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc) +#define SET_MCC_EN_FLAG(adapter, flag)\ + do { \ + adapter_to_dvobj(adapter)->mcc_objpriv.en_mcc = (flag); \ + } while (0) +#define SET_MCC_DURATION(adapter, val)\ + do { \ + adapter_to_dvobj(adapter)->mcc_objpriv.duration = (val); \ + } while (0) +#define SET_MCC_RUNTIME_DURATION(adapter, flag)\ + do { \ + adapter_to_dvobj(adapter)->mcc_objpriv.enable_runtime_duration = (flag); \ + } while (0) /* Represent Channel Tx Null setting */ enum mcc_channel_tx_null { MCC_ENABLE_TX_NULL = 0, @@ -88,10 +96,11 @@ enum mcc_status_rpt { MCC_RPT_READY = 3, MCC_RPT_SWICH_CHANNEL_NOTIFY = 7, MCC_RPT_UPDATE_NOA_START_TIME = 8, + MCC_RPT_TSF = 9, MCC_RPT_MAX, }; -enum MCC_ROLE { +enum mcc_role { MCC_ROLE_STA = 0, MCC_ROLE_AP = 1, MCC_ROLE_GC = 2, @@ -106,10 +115,21 @@ struct mcc_iqk_backup { u16 RX_Y; }; +enum MCC_DURATION_SETTING { + MCC_DURATION_MAPPING = 0, + MCC_DURATION_DIRECET = 1, +}; + +enum MCC_SCHED_MODE { + MCC_FAIR_SCHEDULE = 0, + MCC_FAVOE_STA = 1, + MCC_FAVOE_P2P = 2, +}; + /* mcc data for adapter */ struct mcc_adapter_priv { u8 order; /* FW document, softap/AP must be 0 */ - u8 role; /* MCC role(AP,STA,GO,GC) */ + enum mcc_role role; /* MCC role(AP,STA,GO,GC) */ u8 mcc_duration; /* channel stay period, UNIT:1TU */ /* flow control */ @@ -138,10 +158,20 @@ struct mcc_adapter_priv { u8 p2p_go_noa_ie[MAX_P2P_IE_LEN]; u32 p2p_go_noa_ie_len; + u64 tsf; +#ifdef CONFIG_TDLS + u8 backup_tdls_en; +#endif /* CONFIG_TDLS */ + + u8 null_early; + u8 null_rty_num; }; struct mcc_obj_priv { - u8 duration; /* channel stay period, UNIT:1TU */ + u8 en_mcc; /* enable MCC or not */ + u8 duration; /* store duration(%) from registry, for primary adapter */ + u8 interval; + u8 start_time; u8 mcc_c2h_status; u8 cur_mcc_success_cnt; /* used for check mcc switch channel success */ u8 prev_mcc_success_cnt; /* used for check mcc switch channel success */ @@ -149,11 +179,25 @@ struct mcc_obj_priv { u8 mcc_loc_rsvd_paga[MAX_MCC_NUM]; /* mcc rsvd page */ u8 mcc_status; /* mcc status stop or start .... */ u8 policy_index; - u32 mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */ + u8 mcc_stop_threshold; + u8 current_order; + u8 last_tsfdiff; + systime mcc_launch_time; /* mcc launch time, used for starting detect mcc switch channel success */ _mutex mcc_mutex; _lock mcc_lock; PADAPTER iface[MAX_MCC_NUM]; /* by order, use for mcc parameter cmd */ struct submit_ctx mcc_sctx; + struct submit_ctx mcc_tsf_req_sctx; + _mutex mcc_tsf_req_mutex; + u8 mcc_tsf_req_sctx_order; /* record current order for mcc_tsf_req_sctx */ +#ifdef CONFIG_MCC_MODE_V2 + u8 mcc_iqk_value_rsvd_page[3]; +#endif /* CONFIG_MCC_MODE_V2 */ + u8 mcc_pwr_idx_rsvd_page[MAX_MCC_NUM]; + u8 enable_runtime_duration; + u32 backup_phydm_ability; + /* for LG */ + u8 mchan_sched_mode; }; /* backup IQK val */ @@ -170,7 +214,7 @@ void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status); /* dl mcc rsvd page */ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index - , u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len, RSVDPAGE_LOC *rsvd_page_loc); + , u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num); /* handle C2H */ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf); @@ -212,9 +256,16 @@ void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode); u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len); -void rtw_hal_mcc_update_switch_channel_policy_table(PADAPTER padapter); - void rtw_hal_dump_mcc_policy_table(void *sel); +void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add); + +void rtw_hal_mcc_process_noa(PADAPTER padapter); + +void rtw_hal_mcc_parameter_init(PADAPTER padapter); + +u8 rtw_set_mcc_duration_hdl(PADAPTER adapter, u8 type, const u8 *val); + +u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val); #endif /* _RTW_MCC_H_ */ #endif /* CONFIG_MCC_MODE */ diff --git a/include/rtw_mem.h b/include/rtw_mem.h index ae6049f..229028c 100644 --- a/include/rtw_mem.h +++ b/include/rtw_mem.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_MEM_H__ #define __RTW_MEM_H__ diff --git a/include/rtw_mi.h b/include/rtw_mi.h index 84bcc8c..26db46b 100644 --- a/include/rtw_mi.h +++ b/include/rtw_mi.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,36 +11,50 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_MI_H_ #define __RTW_MI_H_ void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw); +u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter); +u8 rtw_mi_stayin_union_band_chk(_adapter *adapter); + +int rtw_mi_get_ch_setting_union_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, u8 *ch, u8 *bw, u8 *offset); int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); struct mi_state { - u8 sta_num; /*WIFI_FW_STATION_STATE*/ - u8 ld_sta_num; /*WIFI_FW_STATION_STATE |_FW_LINKED*/ - u8 lg_sta_num; /*WIFI_FW_STATION_STATE |_FW_UNDER_LINKING*/ - u8 ap_num; /*WIFI_FW_AP_STATE|_FW_LINKED*/ - u8 ld_ap_num; /*WIFI_FW_AP_STATE|_FW_LINKED && asoc_sta_count > 2*/ - u8 adhoc_num; /* WIFI_FW_ADHOC_STATE */ - u8 ld_adhoc_num; /* WIFI_FW_ADHOC_STATE && asoc_sta_count > 2 */ - u8 uwps_num; /*WIFI_UNDER_WPS*/ - + u8 sta_num; /* WIFI_STATION_STATE */ + u8 ld_sta_num; /* WIFI_STATION_STATE && _FW_LINKED */ + u8 lg_sta_num; /* WIFI_STATION_STATE && _FW_UNDER_LINKING */ +#ifdef CONFIG_TDLS + u8 ld_tdls_num; /* adapter.tdlsinfo.link_established */ +#endif +#ifdef CONFIG_AP_MODE + u8 ap_num; /* WIFI_AP_STATE && _FW_LINKED */ + u8 starting_ap_num; /*WIFI_FW_AP_STATE*/ + u8 ld_ap_num; /* WIFI_AP_STATE && _FW_LINKED && asoc_sta_count > 2 */ +#endif + u8 adhoc_num; /* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && _FW_LINKED */ + u8 ld_adhoc_num; /* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && _FW_LINKED && asoc_sta_count > 2 */ +#ifdef CONFIG_RTW_MESH + u8 mesh_num; /* WIFI_MESH_STATE && _FW_LINKED */ + u8 ld_mesh_num; /* WIFI_MESH_STATE && _FW_LINKED && asoc_sta_count > 2 */ +#endif + u8 scan_num; /* WIFI_SITE_MONITOR */ + u8 scan_enter_num; /* WIFI_SITE_MONITOR && !SCAN_DISABLE && !SCAN_BACK_OP */ + u8 uwps_num; /* WIFI_UNDER_WPS */ #ifdef CONFIG_IOCTL_CFG80211 #ifdef CONFIG_P2P u8 roch_num; #endif u8 mgmt_tx_num; #endif - +#ifdef CONFIG_P2P + u8 p2p_device_num; + u8 p2p_gc; + u8 p2p_go; +#endif u8 union_ch; u8 union_bw; u8 union_offset; @@ -49,10 +63,36 @@ struct mi_state { #define MSTATE_STA_NUM(_mstate) ((_mstate)->sta_num) #define MSTATE_STA_LD_NUM(_mstate) ((_mstate)->ld_sta_num) #define MSTATE_STA_LG_NUM(_mstate) ((_mstate)->lg_sta_num) + +#ifdef CONFIG_TDLS +#define MSTATE_TDLS_LD_NUM(_mstate) ((_mstate)->ld_tdls_num) +#else +#define MSTATE_TDLS_LD_NUM(_mstate) 0 +#endif + +#ifdef CONFIG_AP_MODE #define MSTATE_AP_NUM(_mstate) ((_mstate)->ap_num) +#define MSTATE_AP_STARTING_NUM(_mstate) ((_mstate)->starting_ap_num) #define MSTATE_AP_LD_NUM(_mstate) ((_mstate)->ld_ap_num) +#else +#define MSTATE_AP_NUM(_mstate) 0 +#define MSTATE_AP_STARTING_NUM(_mstate) 0 +#define MSTATE_AP_LD_NUM(_mstate) 0 +#endif + #define MSTATE_ADHOC_NUM(_mstate) ((_mstate)->adhoc_num) #define MSTATE_ADHOC_LD_NUM(_mstate) ((_mstate)->ld_adhoc_num) + +#ifdef CONFIG_RTW_MESH +#define MSTATE_MESH_NUM(_mstate) ((_mstate)->mesh_num) +#define MSTATE_MESH_LD_NUM(_mstate) ((_mstate)->ld_mesh_num) +#else +#define MSTATE_MESH_NUM(_mstate) 0 +#define MSTATE_MESH_LD_NUM(_mstate) 0 +#endif + +#define MSTATE_SCAN_NUM(_mstate) ((_mstate)->scan_num) +#define MSTATE_SCAN_ENTER_NUM(_mstate) ((_mstate)->scan_enter_num) #define MSTATE_WPS_NUM(_mstate) ((_mstate)->uwps_num) #if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P) @@ -61,6 +101,16 @@ struct mi_state { #define MSTATE_ROCH_NUM(_mstate) 0 #endif +#ifdef CONFIG_P2P +#define MSTATE_P2P_DV_NUM(_mstate) ((_mstate)->p2p_device_num) +#define MSTATE_P2P_GC_NUM(_mstate) ((_mstate)->p2p_gc) +#define MSTATE_P2P_GO_NUM(_mstate) ((_mstate)->p2p_go) +#else +#define MSTATE_P2P_DV_NUM(_mstate) 0 +#define MSTATE_P2P_GC_NUM(_mstate) 0 +#define MSTATE_P2P_GO_NUM(_mstate) 0 +#endif + #if defined(CONFIG_IOCTL_CFG80211) #define MSTATE_MGMT_TX_NUM(_mstate) ((_mstate)->mgmt_tx_num) #else @@ -77,28 +127,40 @@ struct mi_state { #define rtw_mi_get_assoced_sta_num(adapter) DEV_STA_LD_NUM(adapter_to_dvobj(adapter)) #define rtw_mi_get_ap_num(adapter) DEV_AP_NUM(adapter_to_dvobj(adapter)) +#define rtw_mi_get_mesh_num(adapter) DEV_MESH_NUM(adapter_to_dvobj(adapter)) +u8 rtw_mi_get_assoc_if_num(_adapter *adapter); /* For now, not return union_ch/bw/offset */ +void rtw_mi_status_by_ifbmp(struct dvobj_priv *dvobj, u8 ifbmp, struct mi_state *mstate); void rtw_mi_status(_adapter *adapter, struct mi_state *mstate); void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate); +void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate); -void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state); +/* For now, not handle union_ch/bw/offset */ +void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a); -u8 rtw_mi_mp_mode_check(_adapter *padapter); +void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state); -u8 rtw_mi_netif_stop_queue(_adapter *padapter, bool carrier_off); -u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter, bool carrier_off); +u8 rtw_mi_netif_stop_queue(_adapter *padapter); +u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter); u8 rtw_mi_netif_wake_queue(_adapter *padapter); u8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter); u8 rtw_mi_netif_carrier_on(_adapter *padapter); u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter); +u8 rtw_mi_netif_carrier_off(_adapter *padapter); +u8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter); + +u8 rtw_mi_netif_caroff_qstop(_adapter *padapter); +u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter); +u8 rtw_mi_netif_caron_qstart(_adapter *padapter); +u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter); void rtw_mi_scan_abort(_adapter *adapter, bool bwait); void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait); -void rtw_mi_start_drv_threads(_adapter *adapter); -void rtw_mi_buddy_start_drv_threads(_adapter *adapter); +u32 rtw_mi_start_drv_threads(_adapter *adapter); +u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter); void rtw_mi_stop_drv_threads(_adapter *adapter); void rtw_mi_buddy_stop_drv_threads(_adapter *adapter); void rtw_mi_cancel_all_timer(_adapter *adapter); @@ -113,6 +175,9 @@ void rtw_mi_buddy_intf_start(_adapter *adapter); void rtw_mi_intf_stop(_adapter *adapter); void rtw_mi_buddy_intf_stop(_adapter *adapter); +#ifdef CONFIG_NEW_NETDEV_HDL +u8 rtw_mi_hal_iface_init(_adapter *padapter); +#endif void rtw_mi_suspend_free_assoc_resource(_adapter *adapter); void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter); @@ -127,9 +192,6 @@ void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms); u8 rtw_mi_is_scan_deny(_adapter *adapter); u8 rtw_mi_buddy_is_scan_deny(_adapter *adapter); -u8 rtw_mi_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); -u8 rtw_mi_buddy_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); - void rtw_mi_beacon_update(_adapter *padapter); void rtw_mi_buddy_beacon_update(_adapter *padapter); @@ -157,6 +219,8 @@ enum { MI_AP_ASSOC, MI_ADHOC, MI_ADHOC_ASSOC, + MI_MESH, + MI_MESH_ASSOC, MI_STA_NOLINK, /* this is misleading, but not used now */ MI_STA_LINKED, MI_STA_LINKING, @@ -193,9 +257,6 @@ void rtw_mi_buddy_adapter_reset(_adapter *padapter); u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter); u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter); -u8 rtw_mi_dev_unload(_adapter *padapter); -u8 rtw_mi_buddy_dev_unload(_adapter *padapter); - extern void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter); u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter); u8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter); @@ -210,6 +271,9 @@ extern void sreset_start_adapter(_adapter *padapter); extern void sreset_stop_adapter(_adapter *padapter); u8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart); u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart); +#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE) +void rtw_mi_ap_info_restore(_adapter *adapter); +#endif u8 rtw_mi_tx_beacon_hdl(_adapter *padapter); u8 rtw_mi_buddy_tx_beacon_hdl(_adapter *padapter); @@ -225,7 +289,7 @@ u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter); #endif _adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id); -_adapter *rtw_get_iface_by_macddr(_adapter *padapter, u8 *mac_addr); +_adapter *rtw_get_iface_by_macddr(_adapter *padapter, const u8 *mac_addr); _adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port); void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status); @@ -235,6 +299,8 @@ void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvf _adapter *rtw_mi_get_ap_adapter(_adapter *padapter); #endif +u8 rtw_mi_get_ld_sta_ifbmp(_adapter *adapter); +u8 rtw_mi_get_ap_mesh_ifbmp(_adapter *adapter); void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b); #endif /*__RTW_MI_H_*/ diff --git a/include/rtw_mlme.h b/include/rtw_mlme.h index c98a28b..8f2646c 100644 --- a/include/rtw_mlme.h +++ b/include/rtw_mlme.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_MLME_H_ #define __RTW_MLME_H_ @@ -29,11 +24,6 @@ /* Commented by Albert 20101105 * Increase the scanning timeout because of increasing the SURVEY_TO value. */ -#define SCANNING_TIMEOUT 8000 -#ifdef CONFIG_SCAN_BACKOP -#define CONC_SCANNING_TIMEOUT_SINGLE_BAND 10000 -#define CONC_SCANNING_TIMEOUT_DUAL_BAND 15000 -#endif #ifdef PALTFORM_OS_WINCE #define SCANQUEUE_LIFETIME 12000000 /* unit:us */ @@ -51,7 +41,7 @@ #define WIFI_ADHOC_MASTER_STATE 0x00000040 #define WIFI_UNDER_LINKING 0x00000080 #define WIFI_UNDER_WPS 0x00000100 -/*#define WIFI_UNDEFINED_STATE 0x00000200*/ +#define WIFI_MESH_STATE 0x00000200 #define WIFI_STA_ALIVE_CHK_STATE 0x00000400 #define WIFI_SITE_MONITOR 0x00000800 /* under site surveying */ #define WIFI_WDS 0x00001000 @@ -66,7 +56,7 @@ #define WIFI_MP_CTX_CCK_CS 0x00200000 /* in continuous tx with carrier suppression */ #define WIFI_MP_LPBK_STATE 0x00400000 #define WIFI_OP_CH_SWITCHING 0x00800000 -/*#define WIFI_UNDEFINED_STATE 0x01000000*/ +#define WIFI_UNDER_KEY_HANDSHAKE 0x01000000 /*#define WIFI_UNDEFINED_STATE 0x02000000*/ /*#define WIFI_UNDEFINED_STATE 0x04000000*/ /*#define WIFI_UNDEFINED_STATE 0x08000000*/ @@ -88,13 +78,16 @@ const char *get_miracast_mode_str(int mode); void rtw_wfd_st_switch(struct sta_info *sta, bool on); #define MLME_STATE(adapter) get_fwstate(&((adapter)->mlmepriv)) - -#define MLME_IS_STA(adapter) (MLME_STATE((adapter)) & WIFI_STATION_STATE) -#define MLME_IS_AP(adapter) (MLME_STATE((adapter)) & WIFI_AP_STATE) -#define MLME_IS_ADHOC(adapter) (MLME_STATE((adapter)) & WIFI_ADHOC_STATE) -#define MLME_IS_ADHOC_MASTER(adapter) (MLME_STATE((adapter)) & WIFI_ADHOC_MASTER_STATE) -#define MLME_IS_MONITOR(adapter) (MLME_STATE((adapter)) & WIFI_MONITOR_STATE) -#define MLME_IS_MP(adapter) (MLME_STATE((adapter)) & WIFI_MP_STATE) +#define CHK_MLME_STATE(adapter, state) check_fwstate(&((adapter)->mlmepriv), (state)) + +#define MLME_IS_NULL(adapter) CHK_MLME_STATE(adapter, WIFI_NULL_STATE) +#define MLME_IS_STA(adapter) CHK_MLME_STATE(adapter, WIFI_STATION_STATE) +#define MLME_IS_AP(adapter) CHK_MLME_STATE(adapter, WIFI_AP_STATE) +#define MLME_IS_ADHOC(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_STATE) +#define MLME_IS_ADHOC_MASTER(adapter) CHK_MLME_STATE(adapter, WIFI_ADHOC_MASTER_STATE) +#define MLME_IS_MESH(adapter) CHK_MLME_STATE(adapter, WIFI_MESH_STATE) +#define MLME_IS_MONITOR(adapter) CHK_MLME_STATE(adapter, WIFI_MONITOR_STATE) +#define MLME_IS_MP(adapter) CHK_MLME_STATE(adapter, WIFI_MP_STATE) #ifdef CONFIG_P2P #define MLME_IS_PD(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_DEVICE) #define MLME_IS_GC(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_CLIENT) @@ -105,15 +98,21 @@ void rtw_wfd_st_switch(struct sta_info *sta, bool on); #define MLME_IS_GO(adapter) 0 #endif /* !CONFIG_P2P */ +#define MLME_IS_MSRC(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SOURCE) +#define MLME_IS_MSINK(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SINK) + +#define MLME_IS_SCAN(adapter) CHK_MLME_STATE(adapter, WIFI_SITE_MONITOR) +#define MLME_IS_LINKING(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_LINKING) +#define MLME_IS_ASOC(adapter) CHK_MLME_STATE(adapter, WIFI_ASOC_STATE) +#define MLME_IS_OPCH_SW(adapter) CHK_MLME_STATE(adapter, WIFI_OP_CH_SWITCHING) +#define MLME_IS_WPS(adapter) CHK_MLME_STATE(adapter, WIFI_UNDER_WPS) + #if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_P2P) #define MLME_IS_ROCH(adapter) (rtw_cfg80211_get_is_roch(adapter) == _TRUE) #else #define MLME_IS_ROCH(adapter) 0 #endif -#define MLME_IS_MSRC(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SOURCE) -#define MLME_IS_MSINK(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SINK) - #ifdef CONFIG_IOCTL_CFG80211 #define MLME_IS_MGMT_TX(adapter) rtw_cfg80211_get_is_mgmt_tx(adapter) #else @@ -126,20 +125,42 @@ void rtw_wfd_st_switch(struct sta_info *sta, bool on); MLME_IS_AP((adapter)) ? (MLME_IS_GO((adapter)) ? " GO" : " AP") : \ MLME_IS_ADHOC((adapter)) ? " ADHOC" : \ MLME_IS_ADHOC_MASTER((adapter)) ? " ADHOC_M" : \ + MLME_IS_MESH((adapter)) ? " MESH" : \ MLME_IS_MONITOR((adapter)) ? " MONITOR" : \ MLME_IS_MP((adapter)) ? " MP" : "", \ MLME_IS_PD((adapter)) ? " PD" : "", \ MLME_IS_MSRC((adapter)) ? " MSRC" : "", \ MLME_IS_MSINK((adapter)) ? " MSINK" : "", \ - (MLME_STATE((adapter)) & WIFI_SITE_MONITOR) ? " SCAN" : "", \ - (MLME_STATE((adapter)) & WIFI_UNDER_LINKING) ? " LINKING" : "", \ - (MLME_STATE((adapter)) & WIFI_ASOC_STATE) ? " ASOC" : "", \ - (MLME_STATE((adapter)) & WIFI_OP_CH_SWITCHING) ? " OP_CH_SW" : "", \ - (MLME_STATE((adapter)) & WIFI_UNDER_WPS) ? " WPS" : "", \ + MLME_IS_SCAN((adapter)) ? " SCAN" : "", \ + MLME_IS_LINKING((adapter)) ? " LINKING" : "", \ + MLME_IS_ASOC((adapter)) ? " ASOC" : "", \ + MLME_IS_OPCH_SW((adapter)) ? " OPCH_SW" : "", \ + MLME_IS_WPS((adapter)) ? " WPS" : "", \ MLME_IS_ROCH((adapter)) ? " ROCH" : "", \ MLME_IS_MGMT_TX((adapter)) ? " MGMT_TX" : "", \ (MLME_STATE((adapter)) & WIFI_SLEEP_STATE) ? " SLEEP" : "" +enum { + MLME_ACTION_UNKNOWN, + MLME_ACTION_NONE, + MLME_SCAN_ENABLE, /* WIFI_SITE_MONITOR */ + MLME_SCAN_ENTER, /* WIFI_SITE_MONITOR && !SCAN_DISABLE && !SCAN_BACK_OP */ + MLME_SCAN_DONE, /* WIFI_SITE_MONITOR && (SCAN_DISABLE || SCAN_BACK_OP) */ + MLME_SCAN_DISABLE, /* WIFI_SITE_MONITOR is going to be cleared */ + MLME_STA_CONNECTING, + MLME_STA_CONNECTED, + MLME_STA_DISCONNECTED, + MLME_TDLS_LINKED, + MLME_TDLS_NOLINK, + MLME_AP_STARTED, + MLME_AP_STOPPED, + MLME_ADHOC_STARTED, + MLME_ADHOC_STOPPED, + MLME_MESH_STARTED, + MLME_MESH_STOPPED, + MLME_OPCH_SWITCH, +}; + #define _FW_UNDER_LINKING WIFI_UNDER_LINKING #define _FW_LINKED WIFI_ASOC_STATE #define _FW_UNDER_SURVEY WIFI_SITE_MONITOR @@ -309,7 +330,7 @@ struct cfg80211_wifidirect_info { u64 remain_on_ch_cookie; bool is_ro_ch; struct wireless_dev *ro_ch_wdev; - u32 last_ro_ch_time; /* this will be updated at the beginning and end of ro_ch */ + systime last_ro_ch_time; /* this will be updated at the beginning and end of ro_ch */ }; #endif /* CONFIG_IOCTL_CFG80211 */ @@ -379,7 +400,7 @@ struct wifidirect_info { u8 p2p_peer_device_addr[ETH_ALEN]; u8 peer_intent; /* Included the intent value and tie breaker value. */ u8 device_name[WPS_MAX_DEVICE_NAME_LEN]; /* Device name for displaying on searching device screen */ - u8 device_name_len; + u16 device_name_len; u8 profileindex; /* Used to point to the index of profileinfo array */ u8 peer_operating_ch; u8 find_phase_state_exchange_cnt; @@ -479,13 +500,14 @@ struct tdls_info { _lock hdl_lock; u8 watchdog_count; u8 dev_discovered; /* WFD_TDLS: for sigma test */ - u8 tdls_enable; /* Let wpa_supplicant to setup*/ u8 driver_setup; #ifdef CONFIG_WFD struct wifi_display_info *wfd_info; #endif + + struct submit_ctx *tdls_sctx; }; struct tdls_txmgmt { @@ -516,9 +538,10 @@ struct beacon_keys { int is_8021x; }; #ifdef CONFIG_RTW_80211R -#define FT_ACTION_REQ_LIMIT 4 +#define RTW_FT_ACTION_REQ_LMT 4 +#define RTW_FT_MAX_IE_SZ 256 -typedef enum _RTW_WIFI_FT_STA_STATUS { +enum _rtw_ft_sta_status { RTW_FT_UNASSOCIATED_STA = 0, RTW_FT_AUTHENTICATING_STA, RTW_FT_AUTHENTICATED_STA, @@ -528,73 +551,221 @@ typedef enum _RTW_WIFI_FT_STA_STATUS { RTW_FT_REQUESTED_STA, RTW_FT_CONFIRMED_STA, RTW_FT_UNSPECIFIED_STA -} RTW_WIFI_FT_STA_STATUS; +}; + +#define rtw_ft_chk_status(a, s) \ + ((a)->mlmepriv.ft_roam.ft_status == (s)) + +#define rtw_ft_roam_status(a, s) \ + ((rtw_to_roam(a) > 0) && rtw_ft_chk_status(a, s)) -#define rtw_chk_ft_status(adapter, status) ((adapter)->mlmepriv.ftpriv.ft_status == status) -#define rtw_set_ft_status(adapter, status) \ +#define rtw_ft_authed_sta(a) \ + ((rtw_ft_chk_status(a, RTW_FT_AUTHENTICATED_STA)) || \ + (rtw_ft_chk_status(a, RTW_FT_ASSOCIATING_STA)) || \ + (rtw_ft_chk_status(a, RTW_FT_ASSOCIATED_STA))) + +#define rtw_ft_set_status(a, s) \ do { \ - ((adapter)->mlmepriv.ftpriv.ft_status = status); \ + ((a)->mlmepriv.ft_roam.ft_status = (s)); \ } while (0) -#define rtw_reset_ft_status(adapter) \ +#define rtw_ft_lock_set_status(a, s, irq) \ do { \ - ((adapter)->mlmepriv.ftpriv.ft_status = RTW_FT_UNASSOCIATED_STA); \ + _enter_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq))); \ + ((a)->mlmepriv.ft_roam.ft_status = (s)); \ + _exit_critical_bh(&(a)->mlmepriv.lock, ((_irqL *)(irq))); \ } while (0) -typedef enum _RTW_WIFI_FT_CAPABILITY { - RTW_FT_STA_SUPPORTED = BIT0, - RTW_FT_STA_OVER_DS_SUPPORTED = BIT1, - RTW_FT_SUPPORTED = BIT2, - RTW_FT_OVER_DS_SUPPORTED = BIT3, -} RTW_WIFI_FT_CAPABILITY; +#define rtw_ft_reset_status(a) \ + do { \ + ((a)->mlmepriv.ft_roam.ft_status = RTW_FT_UNASSOCIATED_STA); \ + } while (0) + +enum rtw_ft_capability { + RTW_FT_EN = BIT0, + RTW_FT_OTD_EN = BIT1, + RTW_FT_PEER_EN = BIT2, + RTW_FT_PEER_OTD_EN = BIT3, + RTW_FT_BTM_ROAM = BIT4, +}; -#define rtw_chk_ft_flags(adapter, flags) ((adapter)->mlmepriv.ftpriv.ft_flags & (flags)) -#define rtw_set_ft_flags(adapter, flags) \ +#define rtw_ft_chk_flags(a, f) \ + ((a)->mlmepriv.ft_roam.ft_flags & (f)) + +#define rtw_ft_set_flags(a, f) \ do { \ - ((adapter)->mlmepriv.ftpriv.ft_flags |= (flags)); \ + ((a)->mlmepriv.ft_roam.ft_flags |= (f)); \ } while (0) -#define rtw_clr_ft_flags(adapter, flags) \ +#define rtw_ft_clr_flags(a, f) \ do { \ - ((adapter)->mlmepriv.ftpriv.ft_flags &= ~(flags)); \ + ((a)->mlmepriv.ft_roam.ft_flags &= ~(f)); \ } while (0) -#define RTW_MAX_FTIE_SZ 256 -typedef struct _ft_priv { +#define rtw_ft_roam(a) \ + ((rtw_to_roam(a) > 0) && rtw_ft_chk_flags(a, RTW_FT_PEER_EN)) + +#define rtw_ft_valid_akm(a, t) \ + ((rtw_ft_chk_flags(a, RTW_FT_EN)) && \ + (((t) == 3) || ((t) == 4))) + +#define rtw_ft_roam_expired(a, r) \ + ((rtw_chk_roam_flags(a, RTW_ROAM_ON_EXPIRED)) \ + && (r == WLAN_REASON_ACTIVE_ROAM)) + +#define rtw_ft_otd_roam_en(a) \ + ((rtw_ft_chk_flags(a, RTW_FT_OTD_EN)) \ + && ((a)->mlmepriv.ft_roam.ft_roam_on_expired == _FALSE) \ + && ((a)->mlmepriv.ft_roam.ft_cap & 0x01)) + +#define rtw_ft_otd_roam(a) \ + rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN) + +#define rtw_ft_valid_otd_candidate(a, p) \ + ((rtw_ft_chk_flags(a, RTW_FT_OTD_EN)) \ + && ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN) \ + && ((*((p)+4) & 0x01) == 0)) \ + || ((rtw_ft_chk_flags(a, RTW_FT_PEER_OTD_EN) == 0) \ + && (*((p)+4) & 0x01)))) + +struct ft_roam_info { u16 mdid; - u8 ft_cap; /*b0: FT over DS, b1: Resource Req Protocol Cap, b2~b7: Reserved*/ - u8 updated_ft_ies[RTW_MAX_FTIE_SZ]; + u8 ft_cap; + /*b0: FT over DS, b1: Resource Req Protocol Cap, b2~b7: Reserved*/ + u8 updated_ft_ies[RTW_FT_MAX_IE_SZ]; u16 updated_ft_ies_len; - u8 ft_action[RTW_MAX_FTIE_SZ]; + u8 ft_action[RTW_FT_MAX_IE_SZ]; u16 ft_action_len; struct cfg80211_ft_event_params ft_event; u8 ft_roam_on_expired; u8 ft_flags; u32 ft_status; u32 ft_req_retry_cnt; -} ft_priv; + bool ft_updated_bcn; +}; +#endif + +#ifdef CONFIG_LAYER2_ROAMING +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) +#define RTW_RRM_NB_RPT_EN BIT(1) +#define RTW_MAX_NB_RPT_NUM 8 + +#define rtw_roam_busy_scan(a, nb) \ + (((a)->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE) && \ + (((a)->mlmepriv.ch_cnt) < ((nb)->nb_rpt_ch_list_num))) + +#define rtw_wnm_btm_preference_cap(a) \ + ((a)->mlmepriv.nb_info.preference_en == _TRUE) + +#define rtw_wnm_btm_diff_bss(a) \ + ((rtw_wnm_btm_preference_cap(a)) && \ + (is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \ + (_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\ + (a)->mlmepriv.cur_network.network.MacAddress, ETH_ALEN) == _FALSE)) + +#define rtw_wnm_btm_roam_candidate(a, c) \ + ((rtw_wnm_btm_preference_cap(a)) && \ + (is_zero_mac_addr((a)->mlmepriv.nb_info.roam_target_addr) == _FALSE) && \ + (_rtw_memcmp((a)->mlmepriv.nb_info.roam_target_addr,\ + (c)->network.MacAddress, ETH_ALEN))) + +#define rtw_wnm_set_ext_cap_btm(_pEleStart, _val) \ + SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 3, 1, _val) + +#define wnm_btm_bss_term_inc(p) (*((u8 *)((p)+3)) & BSS_TERMINATION_INCLUDED) + +#define wnm_btm_ess_disassoc_im(p) (*((u8 *)((p)+3)) & ESS_DISASSOC_IMMINENT) + +#define wnm_btm_req_mode(p) (*((u8 *)((p)+3))) + +#define wnm_btm_disassoc_timer(p) (*((u16 *)((p)+4))) + +#define wnm_btm_valid_interval(p) (*((u8 *)((p)+6))) + +#define wnm_btm_term_duration_offset(p) ((p)+7) + +/*IEEE Std 80211k Figure 7-95b Neighbor Report element format*/ +struct nb_rpt_hdr { + u8 id; /*0x34: Neighbor Report Element ID*/ + u8 len; + u8 bssid[ETH_ALEN]; + u32 bss_info; + u8 reg_class; + u8 ch_num; + u8 phy_type; +}; + +/*IEEE Std 80211v, Figure 7-95e2¡XBSS Termination Duration subelement field format */ +struct btm_term_duration { + u8 id; + u8 len; + u64 tsf; + u16 duration; +}; + +/*IEEE Std 80211v, Figure 7-101n8¡XBSS Transition Management Request frame body format */ +struct btm_req_hdr { + u8 req_mode; + u16 disassoc_timer; + u8 validity_interval; + struct btm_term_duration term_duration; +}; + +/*IEEE Std 80211v, Table 7-43b Optional Subelement IDs for Neighbor Report*/ +/* BSS Transition Candidate Preference */ +#define WNM_BTM_CAND_PREF_SUBEID 0x03 + +/* BSS Termination Duration */ +#define WNM_BTM_TERM_DUR_SUBEID 0x04 + +struct wnm_btm_cant { + struct nb_rpt_hdr nb_rpt; + u8 preference; /* BSS Transition Candidate Preference */ +}; + +enum rtw_btm_req_mod { + PREFERRED_CANDIDATE_LIST_INCLUDED = BIT0, + ABRIDGED = BIT1, + DISASSOC_IMMINENT = BIT2, + BSS_TERMINATION_INCLUDED = BIT3, + ESS_DISASSOC_IMMINENT = BIT4, +}; + +struct roam_nb_info { + struct nb_rpt_hdr nb_rpt[RTW_MAX_NB_RPT_NUM]; + struct rtw_ieee80211_channel nb_rpt_ch_list[RTW_MAX_NB_RPT_NUM]; + bool nb_rpt_valid; + u8 nb_rpt_ch_list_num; + u8 preference_en; + u8 roam_target_addr[ETH_ALEN]; + u32 last_nb_rpt_entries; + bool nb_rpt_is_same; + _timer roam_scan_timer; +}; +#endif /* defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) */ #endif struct mlme_priv { _lock lock; sint fw_state; /* shall we protect this variable? maybe not necessarily... */ - u8 bScanInProcess; u8 to_join; /* flag */ + u16 join_status; #ifdef CONFIG_LAYER2_ROAMING u8 to_roam; /* roaming trying times */ struct wlan_network *roam_network; /* the target of active roam */ u8 roam_flags; u8 roam_rssi_diff_th; /* rssi difference threshold for active scan candidate selection */ - u32 roam_scan_int_ms; /* scan interval for active roam */ + u32 roam_scan_int; /* scan interval for active roam (Unit:2 second)*/ u32 roam_scanr_exp_ms; /* scan result expire time in ms for roam */ u8 roam_tgt_addr[ETH_ALEN]; /* request to roam to speicific target without other consideration */ u8 roam_rssi_threshold; + systime last_roaming; bool need_to_roam; #endif u8 *nic_hdl; - + u32 max_bss_cnt; /* The size of scan queue */ _list *pscanned; _queue free_bss_pool; _queue scanned_queue; @@ -609,14 +780,16 @@ struct mlme_priv { /* bcn check info */ struct beacon_keys cur_beacon_keys; /* save current beacon keys */ +#ifdef CONFIG_BCN_CNT_CONFIRM_HDL struct beacon_keys new_beacon_keys; /* save new beacon keys */ u8 new_beacon_cnts; /* if new_beacon_cnts >= threshold, ap beacon is changed */ +#endif #ifdef CONFIG_ARP_KEEP_ALIVE /* for arp offload keep alive */ u8 bGetGateway; u8 GetGatewayTryCnt; - u8 gw_mac_addr[6]; + u8 gw_mac_addr[ETH_ALEN]; u8 gw_ip[4]; #endif @@ -630,12 +803,13 @@ struct mlme_priv { uint assoc_by_rssi; _timer scan_to_timer; /* driver itself handles scan_timeout status. */ - u32 scan_start_time; /* used to evaluate the time spent in scanning */ + systime scan_start_time; /* used to evaluate the time spent in scanning */ #ifdef CONFIG_SET_SCAN_DENY_TIMER _timer set_scan_deny_timer; ATOMIC_T set_scan_deny; /* 0: allowed, 1: deny */ #endif + u8 wpa_phase;/*wpa_phase after wps finished*/ struct qos_priv qospriv; @@ -656,7 +830,16 @@ struct mlme_priv { #ifdef CONFIG_80211AC_VHT struct vht_priv vhtpriv; +#ifdef ROKU_PRIVATE + /*infra mode, used to store AP's info*/ + struct vht_priv_infra_ap vhtpriv_infra_ap; +#endif /* ROKU_PRIVATE */ #endif + +#ifdef ROKU_PRIVATE + struct ht_priv_infra_ap htpriv_infra_ap; +#endif /* ROKU_PRIVATE */ + #ifdef CONFIG_BEAMFORMING #ifndef RTW_BEAMFORMING_VERSION_2 #if (BEAMFORMING_SUPPORT == 0)/*for driver beamforming*/ @@ -665,22 +848,17 @@ struct mlme_priv { #endif /* !RTW_BEAMFORMING_VERSION_2 */ #endif -#ifdef CONFIG_DFS - u8 handle_dfs; -#endif -#ifdef CONFIG_DFS_MASTER - /* TODO: move to rfctl */ - _timer dfs_master_timer; -#endif #ifdef CONFIG_RTW_80211R - ft_priv ftpriv; + struct ft_roam_info ft_roam; +#endif +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) + struct roam_nb_info nb_info; + u8 ch_cnt; #endif RT_LINK_DETECT_T LinkDetectInfo; u8 acm_mask; /* for wmm acm mask */ - const struct country_chplan *country_ent; - u8 ChannelPlan; RT_SCAN_TYPE scan_mode; /* active: 1, passive: 0 */ u8 *wps_probe_req_ie; @@ -770,6 +948,9 @@ struct mlme_priv { u8 ori_ch; u8 ori_bw; u8 ori_offset; + #ifdef CONFIG_80211AC_VHT + u8 ori_vht_en; + #endif #endif /* #if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) */ #if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) @@ -824,16 +1005,11 @@ struct mlme_priv { u8 p2p_reject_disable; /* When starting NL80211 wpa_supplicant/hostapd, it will call netdev_close */ /* such that it will cause p2p disabled. Use this flag to reject. */ #endif /* CONFIG_INTEL_WIDI */ - u32 lastscantime; + systime lastscantime; #ifdef CONFIG_CONCURRENT_MODE u8 scanning_via_buddy_intf; #endif -#if 0 - u8 NumOfBcnInfoChkFail; - u32 timeBcnInfoChkStart; -#endif - #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE u32 vendor_ie_mask[WLAN_MAX_VENDOR_IE_NUM]; u8 vendor_ie[WLAN_MAX_VENDOR_IE_NUM][WLAN_MAX_VENDOR_IE_LEN]; @@ -852,10 +1028,11 @@ struct mlme_priv { adapter->mlmepriv.auto_scan_int_ms = ms; \ } while (0) -#define RTW_AUTO_SCAN_REASON_UNSPECIFIED 0 -#define RTW_AUTO_SCAN_REASON_2040_BSS BIT0 -#define RTW_AUTO_SCAN_REASON_ACS BIT1 -#define RTW_AUTO_SCAN_REASON_ROAM BIT2 +#define RTW_AUTO_SCAN_REASON_UNSPECIFIED 0 +#define RTW_AUTO_SCAN_REASON_2040_BSS BIT0 +#define RTW_AUTO_SCAN_REASON_ACS BIT1 +#define RTW_AUTO_SCAN_REASON_ROAM BIT2 +#define RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND BIT3 void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason); @@ -876,12 +1053,13 @@ extern void hostapd_mode_unload(_adapter *padapter); #endif -extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf); +extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf, u16 status); extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf); +void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id); void rtw_sta_mstatus_report(_adapter *adapter); extern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf); extern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf); @@ -890,9 +1068,15 @@ extern void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf); void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf); #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_RTW_80211R -void rtw_update_ft_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork); +void rtw_ft_info_init(struct ft_roam_info *pft); +u8 rtw_ft_chk_roaming_candidate(_adapter *padapter, + struct wlan_network *competitor); +void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork); void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf); #endif +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) +void rtw_roam_nb_info_init(_adapter *padapter); +#endif thread_return event_thread(thread_context context); @@ -942,32 +1126,17 @@ extern void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state); static inline void set_fwstate(struct mlme_priv *pmlmepriv, sint state) { pmlmepriv->fw_state |= state; - - /*bScanInProcess hook in phydm*/ - if (_FW_UNDER_SURVEY == state) - pmlmepriv->bScanInProcess = _TRUE; - rtw_mi_update_iface_status(pmlmepriv, state); } static inline void init_fwstate(struct mlme_priv *pmlmepriv, sint state) { pmlmepriv->fw_state = state; - - /*bScanInProcess hook in phydm*/ - if (_FW_UNDER_SURVEY == state) - pmlmepriv->bScanInProcess = _TRUE; - rtw_mi_update_iface_status(pmlmepriv, state); } static inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state) { pmlmepriv->fw_state &= ~state; - - /*bScanInProcess hook in phydm*/ - if (_FW_UNDER_SURVEY == state) - pmlmepriv->bScanInProcess = _FALSE; - rtw_mi_update_iface_status(pmlmepriv, state); } @@ -1013,15 +1182,16 @@ __inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint v } extern u16 rtw_get_capability(WLAN_BSSID_EX *bss); -extern void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target); +extern bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target); extern void rtw_disconnect_hdl_under_linked(_adapter *adapter, struct sta_info *psta, u8 free_assoc); extern void rtw_generate_random_ibss(u8 *pibss); -extern struct wlan_network *rtw_find_network(_queue *scanned_queue, u8 *addr); +struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr); +struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr); extern struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue); struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network); struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network); -extern void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue); +extern void rtw_free_assoc_resources(_adapter *adapter, u8 lock_scanned_queue); extern void rtw_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated); extern void rtw_indicate_connect(_adapter *adapter); void rtw_indicate_scan_done(_adapter *padapter, bool aborted); @@ -1031,8 +1201,13 @@ void rtw_scan_wait_completed(_adapter *adapter); u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms); void rtw_scan_abort_no_wait(_adapter *adapter); void rtw_scan_abort(_adapter *adapter); +u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms); -extern int rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len); +extern int rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie); +#ifdef CONFIG_WMMPS_STA +void rtw_uapsd_use_default_setting(_adapter *padapter); +bool rtw_is_wmmps_mode(_adapter *padapter); +#endif /* CONFIG_WMMPS_STA */ extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len); extern void rtw_init_registrypriv_dev_network(_adapter *adapter); @@ -1040,17 +1215,39 @@ extern void rtw_update_registrypriv_dev_network(_adapter *adapter); extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter); -extern void rtw_join_timeout_handler(struct timer_list *t); -extern void rtw_join_timeout(struct mlme_priv *pmlmepriv); -extern void rtw_scan_timeout_handler(struct timer_list *t); +extern void rtw_join_timeout_handler(void *ctx); +extern void rtw_scan_timeout_handler(void *ctx); -extern void rtw_dynamic_check_timer_handlder(struct timer_list *t); +extern void rtw_dynamic_check_timer_handlder(void *ctx); extern void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter); +enum { + SS_DENY_MP_MODE, + SS_DENY_RSON_SCANING, + SS_DENY_BLOCK_SCAN, + SS_DENY_BY_DRV, + SS_DENY_SELF_AP_UNDER_WPS, + SS_DENY_SELF_AP_UNDER_LINKING, + SS_DENY_SELF_AP_UNDER_SURVEY, + /*SS_DENY_SELF_STA_UNDER_WPS,*/ + SS_DENY_SELF_STA_UNDER_LINKING, + SS_DENY_SELF_STA_UNDER_SURVEY, + SS_DENY_BUDDY_UNDER_LINK_WPS, + SS_DENY_BUDDY_UNDER_SURVEY, + SS_DENY_BUSY_TRAFFIC, + SS_ALLOW, +#ifdef DBG_LA_MODE + SS_DENY_LA_MODE, +#endif +}; + +u8 _rtw_sitesurvey_condition_check(const char *caller, _adapter *adapter, bool check_sc_interval); +#define rtw_sitesurvey_condition_check(adapter, check_sc_interval) _rtw_sitesurvey_condition_check(__func__, adapter, check_sc_interval) + #ifdef CONFIG_SET_SCAN_DENY_TIMER bool rtw_is_scan_deny(_adapter *adapter); void rtw_clear_scan_deny(_adapter *adapter); -void rtw_set_scan_deny_timer_hdl(struct timer_list *t); +void rtw_set_scan_deny_timer_hdl(void *ctx); void rtw_set_scan_deny(_adapter *adapter, u32 ms); #else #define rtw_is_scan_deny(adapter) _FALSE @@ -1080,9 +1277,6 @@ extern struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv); extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall); extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork); - -extern struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr); - extern void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall); extern sint rtw_if_up(_adapter *padapter); @@ -1156,6 +1350,7 @@ struct sta_media_status_rpt_cmd_parm { void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected); u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected); void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm); +void rtw_sta_traffic_info(void *sel, _adapter *adapter); #ifdef CONFIG_INTEL_PROXIM void rtw_proxim_enable(_adapter *padapter); @@ -1163,6 +1358,40 @@ void rtw_proxim_disable(_adapter *padapter); void rtw_proxim_send_packet(_adapter *padapter, u8 *pbuf, u16 len, u8 m_rate); #endif /* CONFIG_INTEL_PROXIM */ +#define GET_ARP_HTYPE(_arp) BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 0, 0, 16) +#define GET_ARP_PTYPE(_arp) BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 2, 0, 16) +#define GET_ARP_HLEN(_arp) BE_BITS_TO_1BYTE(((u8 *)(_arp)) + 4, 0, 8) +#define GET_ARP_PLEN(_arp) BE_BITS_TO_1BYTE(((u8 *)(_arp)) + 5, 0, 8) +#define GET_ARP_OPER(_arp) BE_BITS_TO_2BYTE(((u8 *)(_arp)) + 6, 0, 16) + +#define SET_ARP_HTYPE(_arp, _val) SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 0, 0, 16, _val) +#define SET_ARP_PTYPE(_arp, _val) SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 2, 0, 16, _val) +#define SET_ARP_HLEN(_arp, _val) SET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 4, 0, 8, _val) +#define SET_ARP_PLEN(_arp, _val) SET_BITS_TO_BE_1BYTE(((u8 *)(_arp)) + 5, 0, 8, _val) +#define SET_ARP_OPER(_arp, _val) SET_BITS_TO_BE_2BYTE(((u8 *)(_arp)) + 6, 0, 16, _val) + +#define ARP_SHA(_arp, _hlen, _plen) (((u8 *)(_arp)) + 8) +#define ARP_SPA(_arp, _hlen, _plen) (((u8 *)(_arp)) + 8 + (_hlen)) +#define ARP_THA(_arp, _hlen, _plen) (((u8 *)(_arp)) + 8 + (_hlen) + (_plen)) +#define ARP_TPA(_arp, _hlen, _plen) (((u8 *)(_arp)) + 8 + 2 * (_hlen) + (_plen)) + +#define ARP_SENDER_MAC_ADDR(_arp) ARP_SHA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN) +#define ARP_SENDER_IP_ADDR(_arp) ARP_SPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN) +#define ARP_TARGET_MAC_ADDR(_arp) ARP_THA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN) +#define ARP_TARGET_IP_ADDR(_arp) ARP_TPA(_arp, ETH_ALEN, RTW_IP_ADDR_LEN) + +#define GET_ARP_SENDER_MAC_ADDR(_arp, _val) _rtw_memcpy(_val, ARP_SENDER_MAC_ADDR(_arp), ETH_ALEN) +#define GET_ARP_SENDER_IP_ADDR(_arp, _val) _rtw_memcpy(_val, ARP_SENDER_IP_ADDR(_arp), RTW_IP_ADDR_LEN) +#define GET_ARP_TARGET_MAC_ADDR(_arp, _val) _rtw_memcpy(_val, ARP_TARGET_MAC_ADDR(_arp), ETH_ALEN) +#define GET_ARP_TARGET_IP_ADDR(_arp, _val) _rtw_memcpy(_val, ARP_TARGET_IP_ADDR(_arp), RTW_IP_ADDR_LEN) + +#define SET_ARP_SENDER_MAC_ADDR(_arp, _val) _rtw_memcpy(ARP_SENDER_MAC_ADDR(_arp), _val, ETH_ALEN) +#define SET_ARP_SENDER_IP_ADDR(_arp, _val) _rtw_memcpy(ARP_SENDER_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN) +#define SET_ARP_TARGET_MAC_ADDR(_arp, _val) _rtw_memcpy(ARP_TARGET_MAC_ADDR(_arp), _val, ETH_ALEN) +#define SET_ARP_TARGET_IP_ADDR(_arp, _val) _rtw_memcpy(ARP_TARGET_IP_ADDR(_arp), _val, RTW_IP_ADDR_LEN) + +void dump_arp_pkt(void *sel, u8 *da, u8 *sa, u8 *arp, bool tx); + #define IPV4_SRC(_iphdr) (((u8 *)(_iphdr)) + 12) #define IPV4_DST(_iphdr) (((u8 *)(_iphdr)) + 16) #define GET_IPV4_IHL(_iphdr) BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 0, 0, 4) diff --git a/include/rtw_mlme_ext.h b/include/rtw_mlme_ext.h index 5ab8088..923ef83 100644 --- a/include/rtw_mlme_ext.h +++ b/include/rtw_mlme_ext.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_MLME_EXT_H_ #define __RTW_MLME_EXT_H_ @@ -26,8 +21,8 @@ * The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. * So, this driver tried to extend the dwell time for each scanning channel. * This will increase the chance to receive the probe response from SoftAP. */ - #define SURVEY_TO (100) + #define REAUTH_TO (300) /* (50) */ #define REASSOC_TO (300) /* (50) */ /* #define DISCONNECT_TO (3000) */ @@ -93,199 +88,11 @@ extern unsigned char P2P_OUI[]; extern unsigned char WMM_INFO_OUI[]; extern unsigned char WMM_PARA_OUI[]; -typedef enum _RT_CHANNEL_DOMAIN { - /* ===== 0x00 ~ 0x1F, legacy channel plan ===== */ - RTW_CHPLAN_FCC = 0x00, - RTW_CHPLAN_IC = 0x01, - RTW_CHPLAN_ETSI = 0x02, - RTW_CHPLAN_SPAIN = 0x03, - RTW_CHPLAN_FRANCE = 0x04, - RTW_CHPLAN_MKK = 0x05, - RTW_CHPLAN_MKK1 = 0x06, - RTW_CHPLAN_ISRAEL = 0x07, - RTW_CHPLAN_TELEC = 0x08, - RTW_CHPLAN_GLOBAL_DOAMIN = 0x09, - RTW_CHPLAN_WORLD_WIDE_13 = 0x0A, - RTW_CHPLAN_TAIWAN = 0x0B, - RTW_CHPLAN_CHINA = 0x0C, - RTW_CHPLAN_SINGAPORE_INDIA_MEXICO = 0x0D, - RTW_CHPLAN_KOREA = 0x0E, - RTW_CHPLAN_TURKEY = 0x0F, - RTW_CHPLAN_JAPAN = 0x10, - RTW_CHPLAN_FCC_NO_DFS = 0x11, - RTW_CHPLAN_JAPAN_NO_DFS = 0x12, - RTW_CHPLAN_WORLD_WIDE_5G = 0x13, - RTW_CHPLAN_TAIWAN_NO_DFS = 0x14, - - /* ===== 0x20 ~ 0x7F, new channel plan ===== */ - RTW_CHPLAN_WORLD_NULL = 0x20, - RTW_CHPLAN_ETSI1_NULL = 0x21, - RTW_CHPLAN_FCC1_NULL = 0x22, - RTW_CHPLAN_MKK1_NULL = 0x23, - RTW_CHPLAN_ETSI2_NULL = 0x24, - RTW_CHPLAN_FCC1_FCC1 = 0x25, - RTW_CHPLAN_WORLD_ETSI1 = 0x26, - RTW_CHPLAN_MKK1_MKK1 = 0x27, - RTW_CHPLAN_WORLD_KCC1 = 0x28, - RTW_CHPLAN_WORLD_FCC2 = 0x29, - RTW_CHPLAN_FCC2_NULL = 0x2A, - RTW_CHPLAN_WORLD_FCC3 = 0x30, - RTW_CHPLAN_WORLD_FCC4 = 0x31, - RTW_CHPLAN_WORLD_FCC5 = 0x32, - RTW_CHPLAN_WORLD_FCC6 = 0x33, - RTW_CHPLAN_FCC1_FCC7 = 0x34, - RTW_CHPLAN_WORLD_ETSI2 = 0x35, - RTW_CHPLAN_WORLD_ETSI3 = 0x36, - RTW_CHPLAN_MKK1_MKK2 = 0x37, - RTW_CHPLAN_MKK1_MKK3 = 0x38, - RTW_CHPLAN_FCC1_NCC1 = 0x39, - RTW_CHPLAN_FCC1_NCC2 = 0x40, - RTW_CHPLAN_GLOBAL_NULL = 0x41, - RTW_CHPLAN_ETSI1_ETSI4 = 0x42, - RTW_CHPLAN_FCC1_FCC2 = 0x43, - RTW_CHPLAN_FCC1_NCC3 = 0x44, - RTW_CHPLAN_WORLD_ETSI5 = 0x45, - RTW_CHPLAN_FCC1_FCC8 = 0x46, - RTW_CHPLAN_WORLD_ETSI6 = 0x47, - RTW_CHPLAN_WORLD_ETSI7 = 0x48, - RTW_CHPLAN_WORLD_ETSI8 = 0x49, - RTW_CHPLAN_WORLD_ETSI9 = 0x50, - RTW_CHPLAN_WORLD_ETSI10 = 0x51, - RTW_CHPLAN_WORLD_ETSI11 = 0x52, - RTW_CHPLAN_FCC1_NCC4 = 0x53, - RTW_CHPLAN_WORLD_ETSI12 = 0x54, - RTW_CHPLAN_FCC1_FCC9 = 0x55, - RTW_CHPLAN_WORLD_ETSI13 = 0x56, - RTW_CHPLAN_FCC1_FCC10 = 0x57, - RTW_CHPLAN_MKK2_MKK4 = 0x58, - RTW_CHPLAN_WORLD_ETSI14 = 0x59, - RTW_CHPLAN_FCC1_FCC5 = 0x60, - RTW_CHPLAN_FCC2_FCC7 = 0x61, - RTW_CHPLAN_FCC2_FCC1 = 0x62, - RTW_CHPLAN_WORLD_ETSI15 = 0x63, - RTW_CHPLAN_MKK2_MKK5 = 0x64, - RTW_CHPLAN_ETSI1_ETSI16 = 0x65, - RTW_CHPLAN_FCC1_FCC14 = 0x66, - RTW_CHPLAN_FCC1_FCC12 = 0x67, - RTW_CHPLAN_FCC2_FCC14 = 0x68, - RTW_CHPLAN_FCC2_FCC12 = 0x69, - RTW_CHPLAN_ETSI1_ETSI17 = 0x6A, - RTW_CHPLAN_WORLD_FCC16 = 0x6B, - RTW_CHPLAN_WORLD_FCC13 = 0x6C, - RTW_CHPLAN_FCC2_FCC15 = 0x6D, - RTW_CHPLAN_WORLD_FCC12 = 0x6E, - RTW_CHPLAN_NULL_ETSI8 = 0x6F, - RTW_CHPLAN_NULL_ETSI18 = 0x70, - RTW_CHPLAN_NULL_ETSI17 = 0x71, - RTW_CHPLAN_NULL_ETSI19 = 0x72, - - RTW_CHPLAN_MAX, - RTW_CHPLAN_REALTEK_DEFINE = 0x7F, -} RT_CHANNEL_DOMAIN, *PRT_CHANNEL_DOMAIN; - -typedef enum _RT_CHANNEL_DOMAIN_2G { - RTW_RD_2G_NULL = 0, - RTW_RD_2G_WORLD = 1, /* Worldwird 13 */ - RTW_RD_2G_ETSI1 = 2, /* Europe */ - RTW_RD_2G_FCC1 = 3, /* US */ - RTW_RD_2G_MKK1 = 4, /* Japan */ - RTW_RD_2G_ETSI2 = 5, /* France */ - RTW_RD_2G_GLOBAL = 6, /* Global domain */ - RTW_RD_2G_MKK2 = 7, /* Japan */ - RTW_RD_2G_FCC2 = 8, /* US */ - - RTW_RD_2G_MAX, -} RT_CHANNEL_DOMAIN_2G, *PRT_CHANNEL_DOMAIN_2G; - -typedef enum _RT_CHANNEL_DOMAIN_5G { - RTW_RD_5G_NULL = 0, /* */ - RTW_RD_5G_ETSI1 = 1, /* Europe */ - RTW_RD_5G_ETSI2 = 2, /* Australia, New Zealand */ - RTW_RD_5G_ETSI3 = 3, /* Russia */ - RTW_RD_5G_FCC1 = 4, /* US */ - RTW_RD_5G_FCC2 = 5, /* FCC w/o DFS Channels */ - RTW_RD_5G_FCC3 = 6, /* Bolivia, Chile, El Salvador, Venezuela */ - RTW_RD_5G_FCC4 = 7, /* Venezuela */ - RTW_RD_5G_FCC5 = 8, /* China */ - RTW_RD_5G_FCC6 = 9, /* */ - RTW_RD_5G_FCC7 = 10, /* US Canada(w/o Weather radar) */ - RTW_RD_5G_KCC1 = 11, /* Korea */ - RTW_RD_5G_MKK1 = 12, /* Japan */ - RTW_RD_5G_MKK2 = 13, /* Japan (W52, W53) */ - RTW_RD_5G_MKK3 = 14, /* Japan (W56) */ - RTW_RD_5G_NCC1 = 15, /* Taiwan, (w/o Weather radar) */ - RTW_RD_5G_NCC2 = 16, /* Taiwan, Band2, Band4 */ - RTW_RD_5G_NCC3 = 17, /* Taiwan w/o DFS, Band4 only */ - RTW_RD_5G_ETSI4 = 18, /* Europe w/o DFS, Band1 only */ - RTW_RD_5G_ETSI5 = 19, /* Australia, New Zealand(w/o Weather radar) */ - RTW_RD_5G_FCC8 = 20, /* Latin America */ - RTW_RD_5G_ETSI6 = 21, /* Israel, Bahrain, Egypt, India, China, Malaysia */ - RTW_RD_5G_ETSI7 = 22, /* China */ - RTW_RD_5G_ETSI8 = 23, /* Jordan */ - RTW_RD_5G_ETSI9 = 24, /* Lebanon */ - RTW_RD_5G_ETSI10 = 25, /* Qatar */ - RTW_RD_5G_ETSI11 = 26, /* Russia */ - RTW_RD_5G_NCC4 = 27, /* Taiwan, (w/o Weather radar) */ - RTW_RD_5G_ETSI12 = 28, /* Indonesia */ - RTW_RD_5G_FCC9 = 29, /* (w/o Weather radar) */ - RTW_RD_5G_ETSI13 = 30, /* (w/o Weather radar) */ - RTW_RD_5G_FCC10 = 31, /* Argentina(w/o Weather radar) */ - RTW_RD_5G_MKK4 = 32, /* Japan (W52) */ - RTW_RD_5G_ETSI14 = 33, /* Russia */ - RTW_RD_5G_FCC11 = 34, /* US(include CH144) */ - RTW_RD_5G_ETSI15 = 35, /* Malaysia */ - RTW_RD_5G_MKK5 = 36, /* Japan */ - RTW_RD_5G_ETSI16 = 37, /* Europe */ - RTW_RD_5G_ETSI17 = 38, /* Europe */ - RTW_RD_5G_FCC12 = 39, /* FCC */ - RTW_RD_5G_FCC13 = 40, /* FCC */ - RTW_RD_5G_FCC14 = 41, /* FCC w/o Weather radar(w/o 5600~5650MHz) */ - RTW_RD_5G_FCC15 = 42, /* FCC w/o Band3 */ - RTW_RD_5G_FCC16 = 43, /* FCC w/o Band3 */ - RTW_RD_5G_ETSI18 = 44, /* ETSI w/o DFS Band2&3 */ - RTW_RD_5G_ETSI19 = 45, /* Europe */ - - /* === Below are driver defined for legacy channel plan compatible, DON'T assign index ==== */ - RTW_RD_5G_OLD_FCC1, - RTW_RD_5G_OLD_NCC1, - RTW_RD_5G_OLD_KCC1, - - RTW_RD_5G_MAX, -} RT_CHANNEL_DOMAIN_5G, *PRT_CHANNEL_DOMAIN_5G; - -bool rtw_chplan_is_empty(u8 id); -#define rtw_is_channel_plan_valid(chplan) (((chplan) < RTW_CHPLAN_MAX || (chplan) == RTW_CHPLAN_REALTEK_DEFINE) && !rtw_chplan_is_empty(chplan)) -#define rtw_is_legacy_channel_plan(chplan) ((chplan) < 0x20) - typedef struct _RT_CHANNEL_PLAN { unsigned char Channel[MAX_CHANNEL_NUM]; unsigned char Len; } RT_CHANNEL_PLAN, *PRT_CHANNEL_PLAN; -struct ch_list_t { - u8 *len_ch; -}; - -#define CH_LIST_ENT(_len, arg...) \ - {.len_ch = (u8[_len + 1]) {_len, ##arg}, } - -#define CH_LIST_LEN(_ch_list) (_ch_list.len_ch[0]) -#define CH_LIST_CH(_ch_list, _i) (_ch_list.len_ch[_i + 1]) - -typedef struct _RT_CHANNEL_PLAN_MAP { - u8 Index2G; -#ifdef CONFIG_IEEE80211_BAND_5GHZ - u8 Index5G; -#endif - u8 regd; /* value of REGULATION_TXPWR_LMT */ -} RT_CHANNEL_PLAN_MAP, *PRT_CHANNEL_PLAN_MAP; - -#ifdef CONFIG_IEEE80211_BAND_5GHZ -#define CHPLAN_ENT(i2g, i5g, regd) {i2g, i5g, regd} -#else -#define CHPLAN_ENT(i2g, i5g, regd) {i2g, regd} -#endif - enum Associated_AP { atherosAP = 0, broadcomAP = 1, @@ -320,6 +127,24 @@ typedef enum _HT_IOT_PEER { HT_IOT_PEER_MAX = 18 } HT_IOT_PEER_E, *PHTIOT_PEER_E; + +typedef enum _RT_HT_INF0_CAP { + RT_HT_CAP_USE_TURBO_AGGR = 0x01, + RT_HT_CAP_USE_LONG_PREAMBLE = 0x02, + RT_HT_CAP_USE_AMPDU = 0x04, + RT_HT_CAP_USE_WOW = 0x8, + RT_HT_CAP_USE_SOFTAP = 0x10, + RT_HT_CAP_USE_92SE = 0x20, + RT_HT_CAP_USE_88C_92C = 0x40, + RT_HT_CAP_USE_AP_CLIENT_MODE = 0x80, /* AP team request to reserve this bit, by Emily */ +} RT_HT_INF0_CAPBILITY, *PRT_HT_INF0_CAPBILITY; + +typedef enum _RT_HT_INF1_CAP { + RT_HT_CAP_USE_VIDEO_CLIENT = 0x01, + RT_HT_CAP_USE_JAGUAR_BCUT = 0x02, + RT_HT_CAP_USE_JAGUAR_CCUT = 0x04, +} RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY; + struct mlme_handler { unsigned int num; char *str; @@ -376,17 +201,23 @@ struct ss_res { #endif int scan_mode; u16 scan_ch_ms; + u32 scan_timeout_ms; u8 rx_ampdu_accept; u8 rx_ampdu_size; u8 igi_scan; u8 igi_before_scan; /* used for restoring IGI value without enable DIG & FA_CNT */ #ifdef CONFIG_SCAN_BACKOP u8 backop_flags_sta; /* policy for station mode*/ + #ifdef CONFIG_AP_MODE u8 backop_flags_ap; /* policy for ap mode */ + #endif + #ifdef CONFIG_RTW_MESH + u8 backop_flags_mesh; /* policy for mesh mode */ + #endif u8 backop_flags; /* per backop runtime decision */ u8 scan_cnt; u8 scan_cnt_max; - u32 backop_time; /* the start time of backop */ + systime backop_time; /* the start time of backop */ u16 backop_ms; #endif #if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) @@ -396,6 +227,11 @@ struct ss_res { u8 ch_num; NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; + + u32 token; /* 0: use to identify caller */ + u16 duration; /* 0: use default */ + u8 igi; /* 0: use defalut */ + u8 bw; /* 0: use default */ }; /* #define AP_MODE 0x0C */ @@ -432,7 +268,9 @@ enum TDLS_option { TDLS_CH_SW_END, TDLS_RS_RCR, TDLS_TEARDOWN_STA, + TDLS_TEARDOWN_STA_NO_WAIT, TDLS_TEARDOWN_STA_LOCALLY, + TDLS_TEARDOWN_STA_LOCALLY_POST, maxTDLS, }; @@ -464,6 +302,9 @@ enum TDLS_option { #define RTW_BACK_OP_CH_MS 400 #endif +#define RTW_IP_ADDR_LEN 4 +#define RTW_IPv6_ADDR_LEN 16 + struct mlme_ext_info { u32 state; #ifdef CONFIG_MI_WITH_MBSSID_CAM @@ -474,6 +315,7 @@ struct mlme_ext_info { u32 link_count; u32 auth_seq; u32 auth_algo; /* 802.11 auth, could be open, shared, auto */ + u16 auth_status; u32 authModeToggle; u32 enc_algo;/* encrypt algorithm; */ u32 key_index; /* this is only valid for legendary wep, 0~3 for key id. */ @@ -505,11 +347,19 @@ struct mlme_ext_info { u8 hidden_ssid_mode; u8 VHT_enable; + u8 ip_addr[RTW_IP_ADDR_LEN]; + u8 ip6_addr[RTW_IPv6_ADDR_LEN]; + struct ADDBA_request ADDBA_req; struct WMM_para_element WMM_param; struct HT_caps_element HT_caps; struct HT_info_element HT_info; WLAN_BSSID_EX network;/* join network or bss_network, if in ap mode, it is the same to cur_network.network */ +#ifdef ROKU_PRIVATE + /*infra mode, store supported rates from AssocRsp*/ + NDIS_802_11_RATES_EX SupportedRates_infra_ap; + u8 ht_vht_received;/*ht_vht_received used to show debug msg BIT(0):HT BIT(1):VHT */ +#endif /* ROKU_PRIVATE */ }; /* The channel information about this channel including joining, scanning, and power constraints. */ @@ -524,34 +374,40 @@ typedef struct _RT_CHANNEL_INFO { #endif #ifdef CONFIG_DFS #ifdef CONFIG_DFS_MASTER - u32 non_ocp_end_time; + systime non_ocp_end_time; #endif u8 hidden_bss_cnt; /* per scan count */ #endif } RT_CHANNEL_INFO, *PRT_CHANNEL_INFO; -#define DFS_MASTER_TIMER_MS 100 #define CAC_TIME_MS (60*1000) #define CAC_TIME_CE_MS (10*60*1000) #define NON_OCP_TIME_MS (30*60*1000) +#ifdef CONFIG_TXPWR_LIMIT +void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl); +#endif void rtw_rfctl_init(_adapter *adapter); +void rtw_rfctl_deinit(_adapter *adapter); #ifdef CONFIG_DFS_MASTER struct rf_ctl_t; -#define CH_IS_NON_OCP(rt_ch_info) (time_after((unsigned long)(rt_ch_info)->non_ocp_end_time, (unsigned long)rtw_get_current_time())) -bool rtw_is_cac_reset_needed(_adapter *adapter, u8 ch, u8 bw, u8 offset); +#define CH_IS_NON_OCP(rt_ch_info) (rtw_time_after((rt_ch_info)->non_ocp_end_time, rtw_get_current_time())) +bool rtw_is_cac_reset_needed(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset); bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset); bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl); bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl); -bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); +bool rtw_chset_is_chbw_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); +bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch); void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms); -u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms); -void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset); +u32 rtw_get_ch_waiting_ms(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms); +void rtw_reset_cac(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset); +u32 rtw_force_stop_cac(struct rf_ctl_t *rfctl, u32 timeout_ms); #else #define CH_IS_NON_OCP(rt_ch_info) 0 -#define rtw_chset_is_ch_non_ocp(ch_set, ch, bw, offset) _FALSE +#define rtw_chset_is_chbw_non_ocp(ch_set, ch, bw, offset) _FALSE +#define rtw_chset_is_ch_non_ocp(ch_set, ch) _FALSE #define rtw_rfctl_is_tx_blocked_by_ch_waiting(rfctl) _FALSE #endif @@ -565,17 +421,17 @@ enum { RTW_CHF_NON_OCP = BIT6, }; -bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags); +bool rtw_choose_shortest_waiting_ch(struct rf_ctl_t *rfctl, u8 sel_ch, u8 max_bw + , u8 *dec_ch, u8 *dec_bw, u8 *dec_offset + , u8 d_flags, u8 cur_ch, u8 same_band_prefer, u8 mesh_only); -void dump_country_chplan(void *sel, const struct country_chplan *ent); -void dump_country_chplan_map(void *sel); -void dump_chplan_id_list(void *sel); -void dump_chplan_test(void *sel); void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set); -void dump_cur_chset(void *sel, _adapter *adapter); +void dump_cur_chset(void *sel, struct rf_ctl_t *rfctl); int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch); u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); +void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset + , u8 *g_ch, u8 *g_bw, u8 *g_offset); bool rtw_mlme_band_check(_adapter *adapter, const u32 ch); @@ -630,9 +486,7 @@ struct mlme_ext_priv { u16 mgnt_seq; #ifdef CONFIG_IEEE80211W u16 sa_query_seq; - u64 mgnt_80211w_IPN; - u64 mgnt_80211w_IPN_rx; -#endif /* CONFIG_IEEE80211W */ +#endif /* struct fw_priv fwpriv; */ unsigned char cur_channel; @@ -640,9 +494,6 @@ struct mlme_ext_priv { unsigned char cur_ch_offset;/* PRIME_CHNL_OFFSET */ unsigned char cur_wireless_mode; /* NETWORK_TYPE */ - unsigned char max_chan_nums; - RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM]; - struct p2p_channels channel_list; unsigned char basicrate[NumRates]; unsigned char datarate[NumRates]; #ifdef CONFIG_80211N_HT @@ -654,27 +505,33 @@ struct mlme_ext_priv { * for ap mode, network includes ap's cap_info */ _timer survey_timer; _timer link_timer; + +#ifdef CONFIG_RTW_REPEATER_SON + _timer rson_scan_timer; +#endif #ifdef CONFIG_RTW_80211R _timer ft_link_timer; _timer ft_roam_timer; #endif - u32 last_scan_time; + systime last_scan_time; u8 scan_abort; + u8 join_abort; u8 tx_rate; /* TXRATE when USERATE is set. */ u32 retry; /* retry for issue probereq */ u64 TSFValue; - - /* for LPS-32K to adaptive bcn early and timeout */ - u8 adaptive_tsf_done; - u32 bcn_delay_cnt[9]; - u32 bcn_delay_ratio[9]; u32 bcn_cnt; - u8 DrvBcnEarly; - u8 DrvBcnTimeOut; - + u32 last_bcn_cnt; + u8 cur_bcn_cnt;/*2s*/ + u8 dtim;/*DTIM Period*/ +#ifdef DBG_RX_BCN + u8 tim[4]; +#endif +#ifdef CONFIG_BCN_RECV_TIME + u16 bcn_rx_time; +#endif #ifdef CONFIG_AP_MODE unsigned char bstart_bss; #endif @@ -692,8 +549,18 @@ struct mlme_ext_priv { #ifdef DBG_FIXED_CHAN u8 fixed_chan; #endif - /* set hw sync bcn tsf register or not */ - u8 en_hw_update_tsf; + + u8 tsf_update_required:1; + u8 en_hw_update_tsf:1; /* set hw sync bcn tsf register or not */ + systime tsf_update_pause_stime; + u8 tsf_update_pause_factor; /* num of bcn intervals to stay TSF update pause status */ + u8 tsf_update_restore_factor; /* num of bcn interval to stay TSF update restore status */ +}; + +struct support_rate_handler { + u8 rate; + bool basic; + bool existence; }; static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state) @@ -704,6 +571,8 @@ static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state) return _FALSE; } +void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state); + #define mlmeext_msr(mlmeext) ((mlmeext)->mlmext_info.state & 0x03) #define mlmeext_scan_state(mlmeext) ((mlmeext)->sitesurvey_res.state) #define mlmeext_scan_state_str(mlmeext) scan_state_str((mlmeext)->sitesurvey_res.state) @@ -712,7 +581,9 @@ static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state) do { \ ((mlmeext)->sitesurvey_res.state = (_state)); \ ((mlmeext)->sitesurvey_res.next_state = (_state)); \ + rtw_mi_update_iface_status(&((container_of(mlmeext, _adapter, mlmeextpriv)->mlmepriv)), 0); \ /* RTW_INFO("set_scan_state:%s\n", scan_state_str(_state)); */ \ + sitesurvey_set_offch_state(container_of(mlmeext, _adapter, mlmeextpriv), _state); \ } while (0) #define mlmeext_scan_next_state(mlmeext) ((mlmeext)->sitesurvey_res.next_state) @@ -737,13 +608,6 @@ static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state) do { \ ((mlmeext)->sitesurvey_res.backop_flags_sta = (flags)); \ } while (0) - -#define mlmeext_scan_backop_flags_ap(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_ap) -#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_ap & (flags)) -#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) \ - do { \ - ((mlmeext)->sitesurvey_res.backop_flags_ap = (flags)); \ - } while (0) #else #define mlmeext_scan_backop_flags(mlmeext) (0) #define mlmeext_chk_scan_backop_flags(mlmeext, flags) (0) @@ -752,11 +616,35 @@ static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state) #define mlmeext_scan_backop_flags_sta(mlmeext) (0) #define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) (0) #define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) do {} while (0) +#endif /* CONFIG_SCAN_BACKOP */ +#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) +#define mlmeext_scan_backop_flags_ap(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_ap) +#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_ap & (flags)) +#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) \ + do { \ + ((mlmeext)->sitesurvey_res.backop_flags_ap = (flags)); \ + } while (0) +#else #define mlmeext_scan_backop_flags_ap(mlmeext) (0) #define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) (0) #define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) do {} while (0) -#endif +#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE) */ + +#if defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH) +#define mlmeext_scan_backop_flags_mesh(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_mesh) +#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_mesh & (flags)) +#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) \ + do { \ + ((mlmeext)->sitesurvey_res.backop_flags_mesh = (flags)); \ + } while (0) +#else +#define mlmeext_scan_backop_flags_mesh(mlmeext) (0) +#define mlmeext_chk_scan_backop_flags_mesh(mlmeext, flags) (0) +#define mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags) do {} while (0) +#endif /* defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_RTW_MESH) */ + +u32 rtw_scan_timeout_decision(_adapter *padapter); void init_mlme_default_rate_set(_adapter *padapter); int init_mlme_ext_priv(_adapter *padapter); @@ -766,10 +654,6 @@ extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv); struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv); /* void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv); */ -#ifdef CONFIG_GET_RAID_BY_DRV -unsigned char networktype_to_raid(_adapter *adapter, struct sta_info *psta); -unsigned char networktype_to_raid_ex(_adapter *adapter, struct sta_info *psta); -#endif u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen); void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len); void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask); @@ -786,11 +670,10 @@ void rtw_set_oper_bw(_adapter *adapter, u8 bw); u8 rtw_get_oper_choffset(_adapter *adapter); void rtw_set_oper_choffset(_adapter *adapter, u8 offset); u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset); -u32 rtw_get_on_oper_ch_time(_adapter *adapter); -u32 rtw_get_on_cur_ch_time(_adapter *adapter); +systime rtw_get_on_oper_ch_time(_adapter *adapter); +systime rtw_get_on_cur_ch_time(_adapter *adapter); u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset); -u8 rtw_get_offset_by_ch(u8 channel); void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode); @@ -821,7 +704,6 @@ void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType); u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid); void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter *padapter, bool update_ie); -int get_bsstype(unsigned short capability); u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork); u16 get_beacon_interval(WLAN_BSSID_EX *bss); @@ -830,6 +712,10 @@ int is_client_associated_to_ibss(_adapter *padapter); int is_IBSS_empty(_adapter *padapter); unsigned char check_assoc_AP(u8 *pframe, uint len); +void get_assoc_AP_Vendor(char *vendor, u8 assoc_AP_vendor); +#ifdef CONFIG_80211AC_VHT +unsigned char get_vht_mu_bfer_cap(u8 *pframe, uint len); +#endif int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); #ifdef CONFIG_WFD @@ -839,13 +725,24 @@ void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag void WMMOnAssocRsp(_adapter *padapter); void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +#ifdef ROKU_PRIVATE +void HT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +#endif void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); void HTOnAssocRsp(_adapter *padapter); +#ifdef ROKU_PRIVATE +void Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void Extended_Supported_rate_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +#endif + void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); void VCS_update(_adapter *padapter, struct sta_info *psta); void update_ldpc_stbc_cap(struct sta_info *psta); +bool rtw_validate_value(u16 EID, u8 *p, u16 len); +bool hidden_ssid_ap(WLAN_BSSID_EX *snetwork); +void rtw_absorb_ssid_ifneed(_adapter *padapter, WLAN_BSSID_EX *bssid, u8 *pframe); int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len, struct beacon_keys *recv_beacon); int validate_beacon_len(u8 *pframe, uint len); @@ -853,7 +750,7 @@ void rtw_dump_bcn_keys(struct beacon_keys *recv_beacon); int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len); void update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta); #ifdef CONFIG_DFS -void process_csa_ie(_adapter *padapter, u8 *pframe, uint len); +void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len); #endif /* CONFIG_DFS */ void update_capinfo(PADAPTER Adapter, u16 updateCap); void update_wireless_mode(_adapter *padapter); @@ -870,12 +767,17 @@ void set_sta_rate(_adapter *padapter, struct sta_info *psta); unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated); -unsigned char get_highest_rate_idx(u32 mask); +unsigned char get_highest_rate_idx(u64 mask); +unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit); +#define get_lowest_rate_idx(mask) get_lowest_rate_idx_ex(mask, 0) + int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode); unsigned int is_ap_in_tkip(_adapter *padapter); unsigned int is_ap_in_wep(_adapter *padapter); unsigned int should_forbid_n_rate(_adapter *padapter); +void parsing_eapol_packet(_adapter *padapter, u8 *key_payload, struct sta_info *psta, u8 trx_type); + bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap); void _rtw_camctl_set_flags(_adapter *adapter, u32 flags); void rtw_camctl_set_flags(_adapter *adapter, u32 flags); @@ -890,7 +792,7 @@ void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map); bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id); bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id); s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk); -s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used); +s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool *used); void rtw_camid_free(_adapter *adapter, u8 cam_id); u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id); @@ -898,9 +800,12 @@ struct macid_bmp; struct macid_ctl_t; void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num); bool rtw_macid_is_set(struct macid_bmp *map, u8 id); +void rtw_macid_map_clr(struct macid_bmp *map, u8 id); bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id); bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id); -s8 rtw_macid_get_if_g(struct macid_ctl_t *macid_ctl, u8 id); +u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id); +bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id); +bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter); s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id); void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta); void rtw_release_macid(_adapter *padapter, struct sta_info *psta); @@ -910,11 +815,29 @@ void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw); void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en); void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp); void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp); +void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3); void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl); void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl); u8 rtw_iface_bcmc_id_get(_adapter *padapter); +void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id); +#if defined(DBG_CONFIG_ERROR_RESET) && defined(CONFIG_CONCURRENT_MODE) +void rtw_iface_bcmc_sec_cam_map_restore(_adapter *adapter); +#endif +bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id); +void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id); +void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id); +bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len); +bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len); -u32 report_join_res(_adapter *padapter, int res); +#ifdef CONFIG_AP_MODE +bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id); +void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id); +void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id); +bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map); +bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map); +#endif /* CONFIG_AP_MODE */ + +u32 report_join_res(_adapter *padapter, int aid_res, u16 status); void report_survey_event(_adapter *padapter, union recv_frame *precv_frame); void report_surveydone_event(_adapter *padapter); u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated); @@ -936,6 +859,7 @@ s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntfram s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms); #ifdef CONFIG_P2P +int get_reg_classes_full_count(struct p2p_channels *channel_list); void issue_probersp_p2p(_adapter *padapter, unsigned char *da); void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr); void issue_p2p_GO_request(_adapter *padapter, u8 *raddr); @@ -951,11 +875,10 @@ void issue_assocreq(_adapter *padapter); void issue_reassocreq(_adapter *padapter); void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type); void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status); -void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da); -s32 issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms); +void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da); +s32 issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms); int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); -s32 issue_nulldata_in_interrupt(PADAPTER padapter, u8 *da, unsigned int power_mode); -int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms); +int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms); int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason); int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, int wait_ms); void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset); @@ -964,6 +887,7 @@ void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms); void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator); int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator, int try_cnt, int wait_ms); +void issue_action_BSSCoexistPacket(_adapter *padapter); #ifdef CONFIG_IEEE80211W void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type); @@ -1027,17 +951,38 @@ unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame); #ifdef CONFIG_IEEE80211W unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame); #endif /* CONFIG_IEEE80211W */ +unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame); unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame); #ifdef CONFIG_RTW_80211R -void start_clnt_ft_action(_adapter *padapter, u8 *pTargetAddr); -void issue_action_ft_request(_adapter *padapter, u8 *pTargetAddr); -void report_ft_event(_adapter *padapter); -void report_ft_reassoc_event(_adapter *padapter, u8 *pMacAddr); -void ft_link_timer_hdl(void *ctx); -void ft_roam_timer_hdl(void *ctx); +void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame); +void rtw_ft_start_clnt_join(_adapter *padapter); +u8 rtw_ft_update_rsnie(_adapter *padapter, u8 bwrite, + struct pkt_attrib *pattrib, u8 **pframe); +void rtw_ft_build_auth_req_ies(_adapter *padapter, + struct pkt_attrib *pattrib, u8 **pframe); +void rtw_ft_build_assoc_req_ies(_adapter *padapter, + u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe); +u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len); +void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr); +void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr); +void rtw_ft_report_evt(_adapter *padapter); +void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr); +void rtw_ft_link_timer_hdl(void *ctx); +void rtw_ft_roam_timer_hdl(void *ctx); +void rtw_ft_roam_status_reset(_adapter *padapter); +#endif +#ifdef CONFIG_RTW_WNM +void rtw_wnm_roam_scan_hdl(void *ctx); +void rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len); +void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb); +void rtw_wnm_reset_btm_state(_adapter *padapter); +void rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason); +#endif +#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K) +u32 rtw_wnm_btm_candidates_survey(_adapter *padapter, u8* pframe, u32 elem_len, u8 is_preference); #endif void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res); void mlmeext_sta_del_event_callback(_adapter *padapter); @@ -1045,11 +990,17 @@ void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta); void linked_status_chk(_adapter *padapter, u8 from_timer); +#define rtw_get_bcn_cnt(adapter) (adapter->mlmeextpriv.cur_bcn_cnt) +void rtw_collect_bcn_info(_adapter *adapter); + void _linked_info_dump(_adapter *padapter); -void survey_timer_hdl(struct timer_list *t); -void link_timer_hdl(struct timer_list *t); -void addba_timer_hdl(struct timer_list *t); +void survey_timer_hdl(void *ctx); +#ifdef CONFIG_RTW_REPEATER_SON +void rson_timer_hdl(void *ctx); +#endif +void link_timer_hdl(void *ctx); +void addba_timer_hdl(void *ctx); #ifdef CONFIG_IEEE80211W void sa_query_timer_hdl(void *ctx); #endif /* CONFIG_IEEE80211W */ @@ -1070,17 +1021,23 @@ void reassoc_timer_hdl(_adapter *padapter); _set_timer(&(mlmeext)->link_timer, (ms)); \ } while (0) +bool rtw_is_basic_rate_cck(u8 rate); +bool rtw_is_basic_rate_ofdm(u8 rate); +bool rtw_is_basic_rate_mix(u8 rate); + extern int cckrates_included(unsigned char *rate, int ratelen); extern int cckratesonly_included(unsigned char *rate, int ratelen); extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr); extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); -extern void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext); -extern void adaptive_early_32k(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); +extern void correct_TSF(_adapter *padapter, u8 mlme_state); +#ifdef CONFIG_BCN_RECV_TIME +void rtw_rx_bcn_time_update(_adapter *adapter, uint bcn_len, u8 data_rate); +#endif extern u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer); - +void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame); void rtw_join_done_chk_ch(_adapter *padapter, int join_res); int rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset); @@ -1096,6 +1053,8 @@ struct cmd_hdl { u8(*h2cfuns)(struct _ADAPTER *padapter, u8 *pbuf); }; +void rtw_leave_opch(_adapter *adapter); +void rtw_back_opch(_adapter *adapter); u8 read_macreg_hdl(_adapter *padapter, u8 *pbuf); u8 write_macreg_hdl(_adapter *padapter, u8 *pbuf); @@ -1125,7 +1084,7 @@ u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf); u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf); u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf); u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf); -u8 set_ch_hdl(_adapter *padapter, u8 *pbuf); +u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf); u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf); u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf); u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf); /* Kurt: Handling DFS channel switch announcement ie. */ @@ -1185,7 +1144,7 @@ struct cmd_hdl wlancmds[] = { GEN_MLME_EXT_HANDLER(0, NULL) GEN_MLME_EXT_HANDLER(0, NULL) GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl) - GEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), set_ch_hdl) /* 46 */ + GEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), rtw_set_chbw_hdl) /* 46 */ GEN_MLME_EXT_HANDLER(0, NULL) GEN_MLME_EXT_HANDLER(0, NULL) GEN_MLME_EXT_HANDLER(0, NULL) @@ -1203,11 +1162,12 @@ struct cmd_hdl wlancmds[] = { GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param), set_chplan_hdl) /*59*/ GEN_MLME_EXT_HANDLER(sizeof(struct LedBlink_param), led_blink_hdl) /*60*/ - GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelSwitch_param), set_csa_hdl) /*61*/ + GEN_MLME_EXT_HANDLER(0, set_csa_hdl) /*61*/ GEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param), tdls_hdl) /*62*/ GEN_MLME_EXT_HANDLER(0, chk_bmc_sleepq_hdl) /*63*/ GEN_MLME_EXT_HANDLER(sizeof(struct RunInThread_param), run_in_thread_hdl) /*64*/ GEN_MLME_EXT_HANDLER(sizeof(struct addBaRsp_parm), add_ba_rsp_hdl) /* 65 */ + GEN_MLME_EXT_HANDLER(sizeof(struct rm_event), rm_post_event_hdl) /* 66 */ }; #endif diff --git a/include/rtw_mp.h b/include/rtw_mp.h index 4cd7f32..6dbdd87 100644 --- a/include/rtw_mp.h +++ b/include/rtw_mp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_MP_H_ #define _RTW_MP_H_ @@ -102,39 +97,7 @@ struct mp_tx { #define MP_MAX_LINES 1000 #define MP_MAX_LINES_BYTES 256 -#define u1Byte u8 -#define s1Byte s8 -#define u4Byte u32 -#define s4Byte s32 -#define u1Byte u8 -#define pu1Byte u8* - -#define u2Byte u16 -#define pu2Byte u16* - -#define u4Byte u32 -#define pu4Byte u32* - -#define u8Byte u64 -#define pu8Byte u64* - -#define s1Byte s8 -#define ps1Byte s8* -#define s2Byte s16 -#define ps2Byte s16* - -#define s4Byte s32 -#define ps4Byte s32* - -#define s8Byte s64 -#define ps8Byte s64* - -#define UCHAR u8 -#define USHORT u16 -#define UINT u32 -#define ULONG u32 -#define PULONG u32* typedef struct _RT_PMAC_PKT_INFO { UCHAR MCS; @@ -308,6 +271,7 @@ enum { MP_STOP, MP_RATE, MP_CHANNEL, + MP_CHL_OFFSET, MP_BANDWIDTH, MP_TXPOWER, MP_ANT_TX, @@ -340,8 +304,12 @@ enum { MP_HW_TX_MODE, MP_GET_TXPOWER_INX, MP_CUSTOMER_STR, - MP_NULL, + MP_PWRLMT, + MP_PWRBYRATE, + BT_EFUSE_FILE, MP_SetBT, + MP_SWRFPath, + MP_NULL, #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE VENDOR_IE_SET , VENDOR_IE_GET , @@ -384,6 +352,7 @@ struct mp_priv { u32 rx_pktloss; BOOLEAN rx_bindicatePkt; struct recv_stat rxstat; + BOOLEAN brx_filter_beacon; /* RF/BB relative */ u8 channel; @@ -408,6 +377,9 @@ struct mp_priv { u8 mac_filter[ETH_ALEN]; u8 bmac_filter; + /* RF PATH Setting for WLG WLA BTG BT */ + u8 rf_path_cfg; + struct wlan_network mp_network; NDIS_802_11_MAC_ADDRESS network_macaddr; @@ -445,11 +417,13 @@ struct mp_priv { BOOLEAN bRTWSmbCfg; BOOLEAN bloopback; BOOLEAN bloadefusemap; + BOOLEAN bloadBTefusemap; MPT_CONTEXT mpt_ctx; u8 *TXradomBuffer; + u8 CureFuseBTCoex; }; typedef struct _IOCMD_STRUCT_ { @@ -732,7 +706,9 @@ extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask); extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val); extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr); extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val); - +#ifdef CONFIG_ANTENNA_DIVERSITY +u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain); +#endif void SetChannel(PADAPTER pAdapter); void SetBandwidth(PADAPTER pAdapter); int SetTxPower(PADAPTER pAdapter); @@ -757,7 +733,7 @@ void GetPowerTracking(PADAPTER padapter, u8 *enable); u32 mp_query_psd(PADAPTER pAdapter, u8 *data); void rtw_mp_trigger_iqk(PADAPTER padapter); void rtw_mp_trigger_lck(PADAPTER padapter); - +u8 rtw_mp_mode_check(PADAPTER padapter); void hal_mpt_SwitchRfSetting(PADAPTER pAdapter); @@ -779,6 +755,7 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart); void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); void mpt_ProSetPMacTx(PADAPTER Adapter); void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain); +void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate); u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter); ULONG mpt_ProQueryCalTxPower(PADAPTER pAdapter, u8 RfPath); void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart); @@ -848,6 +825,9 @@ int rtw_mp_rate(struct net_device *dev, int rtw_mp_channel(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); +int rtw_mp_ch_offset(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_bandwidth(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); @@ -905,6 +885,9 @@ int rtw_mp_phypara(struct net_device *dev, int rtw_mp_SetRFPath(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); +int rtw_mp_switch_rf_path(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); int rtw_mp_QueryDrv(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); @@ -917,12 +900,21 @@ int rtw_mp_getver(struct net_device *dev, int rtw_mp_mon(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); +int rtw_mp_pwrlmt(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_pwrbyrate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_efuse_mask_file(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); int rtw_efuse_file_map(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); +int rtw_bt_efuse_file_map(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); int rtw_mp_SetBT(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra); @@ -940,7 +932,7 @@ u8 HwRateToMPTRate(u8 rate); int rtw_mp_iqk(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra); -int rtw_mp_lck(struct net_device *dev, - struct iw_request_info *info, +int rtw_mp_lck(struct net_device *dev, + struct iw_request_info *info, struct iw_point *wrqu, char *extra); #endif /* _RTW_MP_H_ */ diff --git a/include/rtw_mp_ioctl.h b/include/rtw_mp_ioctl.h index e6a9a23..a9dabfc 100644 --- a/include/rtw_mp_ioctl.h +++ b/include/rtw_mp_ioctl.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_MP_IOCTL_H_ #define _RTW_MP_IOCTL_H_ diff --git a/include/rtw_mp_phy_regdef.h b/include/rtw_mp_phy_regdef.h index 5f79e46..be62780 100644 --- a/include/rtw_mp_phy_regdef.h +++ b/include/rtw_mp_phy_regdef.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /***************************************************************************** * * Module: __RTW_MP_PHY_REGDEF_H_ diff --git a/include/rtw_odm.h b/include/rtw_odm.h index e14119a..15fa2b9 100644 --- a/include/rtw_odm.h +++ b/include/rtw_odm.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_ODM_H__ #define __RTW_ODM_H__ @@ -25,29 +20,76 @@ /* * This file provides utilities/wrappers for rtw driver to use ODM */ +typedef enum _HAL_PHYDM_OPS { + HAL_PHYDM_DIS_ALL_FUNC, + HAL_PHYDM_FUNC_SET, + HAL_PHYDM_FUNC_CLR, + HAL_PHYDM_ABILITY_BK, + HAL_PHYDM_ABILITY_RESTORE, + HAL_PHYDM_ABILITY_SET, + HAL_PHYDM_ABILITY_GET, +} HAL_PHYDM_OPS; -void rtw_odm_init_ic_type(_adapter *adapter); +#define DYNAMIC_FUNC_DISABLE (0x0) + u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability); + +#define rtw_phydm_func_disable_all(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0) + +#ifdef CONFIG_RTW_ACS +#define rtw_phydm_func_for_offchannel(adapter) \ + do { \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \ + if (rtw_odm_adaptivity_needed(adapter)) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \ + if (IS_ACS_ENABLE(adapter))\ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ENV_MONITOR); \ + } while (0) +#else +#define rtw_phydm_func_for_offchannel(adapter) \ + do { \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \ + if (rtw_odm_adaptivity_needed(adapter)) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \ + } while (0) +#endif + +#define rtw_phydm_func_clr(adapter, ability) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability) -void rtw_odm_set_force_igi_lb(_adapter *adapter, u8 lb); -u8 rtw_odm_get_force_igi_lb(_adapter *adapter); +#define rtw_phydm_ability_backup(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0) + +#define rtw_phydm_ability_restore(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0) + + +static inline u32 rtw_phydm_ability_get(_adapter *adapter) +{ + return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0); +} + + +void rtw_odm_init_ic_type(_adapter *adapter); void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter); bool rtw_odm_adaptivity_needed(_adapter *adapter); void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter); -void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff, s8 th_l2h_ini_mode2, s8 th_edcca_hl_diff_mode2, u8 edcca_enable); +void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff); void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter); void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type); void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type); -u8 rtw_odm_get_dfs_domain(_adapter *adapter); -u8 rtw_odm_dfs_domain_unknown(_adapter *adapter); +u8 rtw_odm_get_dfs_domain(struct dvobj_priv *dvobj); +u8 rtw_odm_dfs_domain_unknown(struct dvobj_priv *dvobj); #ifdef CONFIG_DFS_MASTER VOID rtw_odm_radar_detect_reset(_adapter *adapter); VOID rtw_odm_radar_detect_disable(_adapter *adapter); VOID rtw_odm_radar_detect_enable(_adapter *adapter); BOOLEAN rtw_odm_radar_detect(_adapter *adapter); +u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj); #endif /* CONFIG_DFS_MASTER */ void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys); diff --git a/include/rtw_p2p.h b/include/rtw_p2p.h index 844f7ec..1f985ad 100644 --- a/include/rtw_p2p.h +++ b/include/rtw_p2p.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_P2P_H_ #define __RTW_P2P_H_ @@ -75,6 +70,7 @@ u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue); #endif /* CONFIG_P2P_PS */ #ifdef CONFIG_IOCTL_CFG80211 +u8 roch_stay_in_cur_chan(_adapter *padapter); void rtw_init_cfg80211_wifidirect_info(_adapter *padapter); int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx); #endif /* CONFIG_IOCTL_CFG80211 */ @@ -106,11 +102,8 @@ static inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo) } } #endif -static inline void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) -{ - if (wdinfo->role != role) - wdinfo->role = role; -} +void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role); + static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo) { return wdinfo->p2p_state; diff --git a/include/rtw_pwrctrl.h b/include/rtw_pwrctrl.h index eb35edf..45822ef 100644 --- a/include/rtw_pwrctrl.h +++ b/include/rtw_pwrctrl.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_PWRCTRL_H_ #define __RTW_PWRCTRL_H_ @@ -45,17 +40,13 @@ #endif /* CONFIG_BT_COEXIST */ #ifdef CONFIG_WOWLAN -#ifdef CONFIG_DEFAULT_PATTERNS_EN #ifdef CONFIG_PLATFORM_ANDROID_INTEL_X86 /* TCP/ICMP/UDP multicast with specific IP addr */ - #define DEFAULT_PATTERN_NUM 3 + #define DEFAULT_PATTERN_NUM 4 #else /* TCP/ICMP */ - #define DEFAULT_PATTERN_NUM 2 + #define DEFAULT_PATTERN_NUM 3 #endif -#else - #define DEFAULT_PATTERN_NUM 0 -#endif /*CONFIG_DEFAULT_PATTERNS_EN*/ #ifdef CONFIG_WOW_PATTERN_HW_CAM /* Frame Mask Cam number for pattern match */ #define MAX_WKFM_CAM_NUM 12 @@ -180,7 +171,7 @@ __inline static void _exit_pwrlock(_pwrlock *plock) _rtw_up_sema(plock); } -#define LPS_DELAY_TIME 1*HZ /* 1 sec */ +#define LPS_DELAY_MS 1000 /* 1 sec */ #define EXE_PWR_NONE 0x01 #define EXE_PWR_IPS 0x02 @@ -312,21 +303,43 @@ struct aoac_report { u8 group_key[32]; u8 key_index; u8 security_type; + u8 wow_pattern_idx; + u8 version_info; + u8 rekey_ok:1; + u8 dummy:7; + u8 reserved[3]; + u8 rxptk_iv[8]; + u8 rxgtk_iv[4][8]; }; struct pwrctrl_priv { - _adapter *adapter; _pwrlock lock; _pwrlock check_32k_lock; volatile u8 rpwm; /* requested power state for fw */ volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */ volatile u8 tog; /* toggling */ volatile u8 cpwm_tog; /* toggling */ + u8 rpwm_retry; u8 pwr_mode; u8 smart_ps; u8 bcn_ant_mode; u8 dtim; +#ifdef CONFIG_LPS_CHK_BY_TP + u8 lps_chk_by_tp; + u16 lps_tx_tp_th;/*Mbps*/ + u16 lps_rx_tp_th;/*Mbps*/ + u16 lps_bi_tp_th;/*Mbps*//*TRX TP*/ + int lps_chk_cnt_th; + int lps_chk_cnt; + u32 lps_tx_pkts; + u32 lps_rx_pkts; + +#endif + +#ifdef CONFIG_WMMPS_STA + u8 wmm_smart_ps; +#endif /* CONFIG_WMMPS_STA */ u32 alives; _workitem cpwm_event; @@ -356,7 +369,7 @@ struct pwrctrl_priv { u8 ips_org_mode; u8 ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */ uint bips_processing; - u32 ips_deny_time; /* will deny IPS when system time is smaller than this */ + systime ips_deny_time; /* will deny IPS when system time is smaller than this */ u8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */ /* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */ @@ -373,12 +386,14 @@ struct pwrctrl_priv { u8 power_mgnt; u8 org_power_mgnt; u8 bFwCurrentInPSMode; - u32 DelayLPSLastTimeStamp; + systime DelayLPSLastTimeStamp; s32 pnp_current_pwr_state; u8 pnp_bstop_trx; - + #ifdef CONFIG_AUTOSUSPEND + int ps_flag; /* used by autosuspend */ u8 bInternalAutoSuspend; + #endif u8 bInSuspend; #ifdef CONFIG_BT_COEXIST u8 bAutoResume; @@ -391,13 +406,19 @@ struct pwrctrl_priv { u8 wowlan_mode; u8 wowlan_p2p_mode; u8 wowlan_pno_enable; + u8 wowlan_in_resume; + #ifdef CONFIG_GPIO_WAKEUP u8 is_high_active; #endif /* CONFIG_GPIO_WAKEUP */ + u8 hst2dev_high_active; #ifdef CONFIG_WOWLAN + bool default_patterns_en; +#ifdef CONFIG_IPV6 + u8 wowlan_ns_offload_en; +#endif /*CONFIG_IPV6*/ u8 wowlan_txpause_status; u8 wowlan_pattern_idx; - u8 wowlan_in_resume; u64 wowlan_fw_iv; struct rtl_priv_pattern patterns[MAX_WKFM_CAM_NUM]; #ifdef CONFIG_PNO_SUPPORT @@ -411,12 +432,12 @@ struct pwrctrl_priv { #endif u8 wowlan_aoac_rpt_loc; struct aoac_report wowlan_aoac_rpt; + u8 wowlan_dis_lps;/*for debug purpose*/ #endif /* CONFIG_WOWLAN */ _timer pwr_state_check_timer; int pwr_state_check_interval; u8 pwr_state_check_cnts; - int ps_flag; /* used by autosuspend */ rt_rf_power_state rf_pwrstate;/* cur power state, only for IPS */ /* rt_rf_power_state current_rfpwrstate; */ @@ -450,12 +471,23 @@ struct pwrctrl_priv { #ifdef CONFIG_LPS_POFF lps_poff_info_t *plps_poff_info; #endif + u8 lps_level_bk; u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/ #ifdef CONFIG_LPS_PG u8 lpspg_rsvd_page_locate; u8 blpspg_info_up; #endif u8 current_lps_hw_port_id; + +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + systime radio_on_start_time; + systime pwr_saving_start_time; + u32 pwr_saving_time; + u32 on_time; + u32 tx_time; + u32 rx_time; +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + }; #define rtw_get_ips_mode_req(pwrctl) \ @@ -512,16 +544,24 @@ rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter); #endif +#ifdef DBG_CHECK_FW_PS_STATE int rtw_fw_ps_state(PADAPTER padapter); +#endif #ifdef CONFIG_LPS s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms); void LPS_Enter(PADAPTER padapter, const char *msg); void LPS_Leave(PADAPTER padapter, const char *msg); +#ifdef CONFIG_CHECK_LEAVE_LPS +#ifdef CONFIG_LPS_CHK_BY_TP +void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta); +#endif void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets); +#endif /*CONFIG_CHECK_LEAVE_LPS*/ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg); void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable); -void rtw_set_rpwm(_adapter *padapter, u8 val8); +u8 rtw_set_rpwm(_adapter *padapter, u8 val8); +void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en); #endif #ifdef CONFIG_RESUME_IN_WORKQUEUE diff --git a/include/rtw_qos.h b/include/rtw_qos.h index 57555e1..8e1d013 100644 --- a/include/rtw_qos.h +++ b/include/rtw_qos.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,24 +11,56 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_QOS_H_ #define _RTW_QOS_H_ +#define DRV_CFG_UAPSD_VO BIT0 +#define DRV_CFG_UAPSD_VI BIT1 +#define DRV_CFG_UAPSD_BK BIT2 +#define DRV_CFG_UAPSD_BE BIT3 + +#define WMM_IE_UAPSD_VO BIT0 +#define WMM_IE_UAPSD_VI BIT1 +#define WMM_IE_UAPSD_BK BIT2 +#define WMM_IE_UAPSD_BE BIT3 +#define WMM_TID0 BIT0 +#define WMM_TID1 BIT1 +#define WMM_TID2 BIT2 +#define WMM_TID3 BIT3 +#define WMM_TID4 BIT4 +#define WMM_TID5 BIT5 +#define WMM_TID6 BIT6 +#define WMM_TID7 BIT7 + +#define AP_SUPPORTED_UAPSD BIT7 +/* TC = Traffic Category, TID0~7 represents TC */ +#define BIT_MASK_TID_TC 0xff +/* TS = Traffic Stream, TID8~15 represents TS */ +#define BIT_MASK_TID_TS 0xff00 +#define ALL_TID_TC_SUPPORTED_UAPSD 0xff struct qos_priv { unsigned int qos_option; /* bit mask option: u-apsd, s-apsd, ts, block ack... */ +#ifdef CONFIG_WMMPS_STA + /* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */ + u8 uapsd_max_sp_len; + /* declare uapsd_tid as a bitmap for the uapsd setting of TID 0~15 */ + u16 uapsd_tid; + /* declare uapsd_tid_delivery_enabled as a bitmap for the delivery-enabled setting of TID 0~7 */ + u8 uapsd_tid_delivery_enabled; + /* declare uapsd_tid_trigger_enabled as a bitmap for the trigger-enabled setting of TID 0~7 */ + u8 uapsd_tid_trigger_enabled; + /* declare uapsd_ap_supported to record whether the connected ap supports uapsd or not */ + u8 uapsd_ap_supported; +#endif /* CONFIG_WMMPS_STA */ + }; -#endif /* _RTL871X_QOS_H_ */ +#endif /* _RTL871X_QOS_H_ */ \ No newline at end of file diff --git a/include/rtw_recv.h b/include/rtw_recv.h index 4c90ebb..a17b3b6 100644 --- a/include/rtw_recv.h +++ b/include/rtw_recv.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,15 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_RECV_H_ #define _RTW_RECV_H_ +#define RTW_RX_MSDU_ACT_NONE 0 +#define RTW_RX_MSDU_ACT_INDICATE BIT0 +#define RTW_RX_MSDU_ACT_FORWARD BIT1 + #ifdef PLATFORM_OS_XP #ifdef CONFIG_SDIO_HCI #define NR_RECVBUFF 1024/* 512 */ /* 128 */ @@ -85,24 +84,15 @@ #define RX_CMD_QUEUE 1 #define RX_MAX_QUEUE 2 -static u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37}; - -static u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3}; -static u8 SNAP_ETH_TYPE_APPLETALK_DDP[2] = {0x80, 0x9b}; -static u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d}; -static u8 SNAP_HDR_APPLETALK_DDP[3] = {0x08, 0x00, 0x07}; /* Datagram Delivery Protocol */ - -static u8 oui_8021h[] = {0x00, 0x00, 0xf8}; -static u8 oui_rfc1042[] = {0x00, 0x00, 0x00}; - #define MAX_SUBFRAME_COUNT 64 -static u8 rtw_rfc1042_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 }; /* Bridge-Tunnel header (for EtherTypes ETH_P_AARP and ETH_P_IPX) */ -static u8 rtw_bridge_tunnel_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 }; +extern u8 rtw_bridge_tunnel_header[]; +extern u8 rtw_rfc1042_header[]; /* for Rx reordering buffer control */ struct recv_reorder_ctrl { _adapter *padapter; + u8 tid; u8 enable; u16 indicate_seq;/* =wstart_b, init_value=0xffff */ u16 wend_b; @@ -115,6 +105,8 @@ struct recv_reorder_ctrl { struct stainfo_rxcache { u16 tid_rxseq[16]; + u8 iv[16][8]; + u8 last_tid; #if 0 unsigned short tid0_rxseq; unsigned short tid1_rxseq; @@ -149,69 +141,6 @@ struct signal_stat { u32 total_num; /* num of valid elements */ u32 total_val; /* sum of valid elements */ }; -#if 0 -typedef struct _ODM_Phy_Status_Info_ { - /* */ - /* Be care, if you want to add any element please insert between */ - /* RxPWDBAll & SignalStrength. */ - /* */ -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) - u4Byte RxPWDBAll; -#else - u1Byte RxPWDBAll; -#endif - - u1Byte SignalQuality; /* in 0-100 index. */ - s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */ - u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ - - u1Byte RxMIMOSignalStrength[4];/* in 0~100 index */ - - u2Byte Cfo_short[4]; /* per-path's Cfo_short */ - u2Byte Cfo_tail[4]; /* per-path's Cfo_tail */ - -#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) - s1Byte RxPower; /* in dBm Translate from PWdB */ - s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ - u1Byte BTRxRSSIPercentage; - u1Byte SignalStrength; /* in 0-100 index. */ - - u1Byte RxPwr[4]; /* per-path's pwdb */ -#endif - u1Byte RxSNR[4]; /* per-path's SNR */ - u1Byte BandWidth; - u1Byte btCoexPwrAdjust; -} ODM_PHY_INFO_T, *PODM_PHY_INFO_T; -#endif - -struct phy_info { - u8 RxPWDBAll; - u8 SignalQuality; /* in 0-100 index. */ - s8 RxMIMOSignalQuality[4]; /* per-path's EVM */ - u8 RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ - u8 RxMIMOSignalStrength[4]; /* in 0~100 index */ - s16 Cfo_short[4]; /* per-path's Cfo_short */ - s16 Cfo_tail[4]; /* per-path's Cfo_tail */ - s8 RxPower; /* in dBm Translate from PWdB */ - s8 RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ - u8 BTRxRSSIPercentage; - u8 SignalStrength; /* in 0-100 index. */ - s8 RxPwr[4]; /* per-path's pwdb */ - s8 RxSNR[4]; -#if ((RTL8822B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - u8 RxCount:2; - u8 BandWidth:2; - u8 rxsc:4; -#else - u8 BandWidth; -#endif - u8 btCoexPwrAdjust; -#if ((RTL8822B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8821C_SUPPORT == 1)) - u8 channel; /* channel number---*/ - BOOLEAN bMuPacket; /* is MU packet or not---*/ - BOOLEAN bBeamformed; -#endif -}; struct rx_raw_rssi { u8 data_rate; @@ -226,6 +155,8 @@ struct rx_raw_rssi { }; +#include "cmn_info/rtw_sta_info.h" + struct rx_pkt_attrib { u16 pkt_len; u8 physt; @@ -257,14 +188,15 @@ struct rx_pkt_attrib { u8 ta[ETH_ALEN]; u8 ra[ETH_ALEN]; u8 bssid[ETH_ALEN]; +#ifdef CONFIG_RTW_MESH + u8 msa[ETH_ALEN]; /* mesh sa */ + u8 mda[ETH_ALEN]; /* mesh da */ + u8 mesh_ctrl_present; + u8 mesh_ctrl_len; /* length of mesh control field */ +#endif u8 ack_policy; -/* #ifdef CONFIG_TCP_CSUM_OFFLOAD_RX */ - u8 tcpchk_valid; /* 0: invalid, 1: valid */ - u8 ip_chkrpt; /* 0: incorrect, 1: correct */ - u8 tcp_chkrpt; /* 0: incorrect, 1: correct */ -/* #endif */ u8 key_index; u8 data_rate; @@ -277,17 +209,15 @@ struct rx_pkt_attrib { u32 tsfl; u32 MacIDValidEntry[2]; /* 64 bits present 64 entry. */ u8 ppdu_cnt; - -#if 0 - u8 signal_qual; - s8 rx_mimo_signal_qual[2]; - u8 signal_strength; - u32 RxPWDBAll; - s32 RecvSignalPower; -#endif - struct phy_info phy_info; + u32 free_cnt; /* free run counter */ + struct phydm_phyinfo_struct phy_info; }; +#ifdef CONFIG_RTW_MESH +#define RATTRIB_GET_MCTRL_LEN(rattrib) ((rattrib)->mesh_ctrl_len) +#else +#define RATTRIB_GET_MCTRL_LEN(rattrib) 0 +#endif /* These definition is used for Rx packet reordering. */ #define SN_LESS(a, b) (((a-b) & 0x800) != 0) @@ -296,7 +226,11 @@ struct rx_pkt_attrib { /* #define REORDER_ENTRY_NUM 128 */ #define REORDER_WAIT_TIME (50) /* (ms) */ -#define RECVBUFF_ALIGN_SZ 8 +#if defined(CONFIG_PLATFORM_RTK390X) && defined(CONFIG_USB_HCI) + #define RECVBUFF_ALIGN_SZ 32 +#else + #define RECVBUFF_ALIGN_SZ 8 +#endif #ifdef CONFIG_TRX_BD_ARCH #define RX_WIFI_INFO_SIZE 24 @@ -375,13 +309,17 @@ accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(pas using enter_critical section to protect */ + +#ifndef DBG_RX_BH_TRACKING +#define DBG_RX_BH_TRACKING 0 +#endif + struct recv_priv { _lock lock; #ifdef CONFIG_RECV_THREAD_MODE _sema recv_sema; - /*_sema terminate_recvthread_sema;*/ - _completion recvthread_comp; + #endif /* _queue blk_strms[MAX_RX_NUMBLKS]; */ /* keeping the block ack frame until return ack */ @@ -395,6 +333,17 @@ struct recv_priv { uint free_recvframe_cnt; + #if DBG_RX_BH_TRACKING + u32 rx_bh_stage; + u32 rx_bh_buf_dq_cnt; + void *rx_bh_lbuf; + void *rx_bh_cbuf; + void *rx_bh_cbuf_data; + u32 rx_bh_cbuf_dlen; + u32 rx_bh_cbuf_pos; + void *rx_bh_cframe; + #endif + _adapter *adapter; #ifdef PLATFORM_WINDOWS @@ -415,6 +364,14 @@ struct recv_priv { u64 rx_pkts; u64 rx_drop; + u64 dbg_rx_drop_count; + u64 dbg_rx_ampdu_drop_count; + u64 dbg_rx_ampdu_forced_indicate_count; + u64 dbg_rx_ampdu_loss_count; + u64 dbg_rx_dup_mgt_frame_drop_count; + u64 dbg_rx_ampdu_window_shift_cnt; + u64 dbg_rx_conflic_mac_addr_cnt; + uint rx_icv_err; uint rx_largepacket_crcerr; uint rx_smallpacket_crcerr; @@ -480,7 +437,6 @@ struct recv_priv { s8 rssi; /* translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); */ struct rx_raw_rssi raw_rssi_info; /* s8 rxpwdb; */ - s16 noise; /* int RxSNRdB[2]; */ /* s8 RxRssi[2]; */ /* int FalseAlmCnt_all; */ @@ -501,6 +457,30 @@ struct recv_priv { BOOLEAN store_law_data_flag; }; +#define RX_BH_STG_UNKNOWN 0 +#define RX_BH_STG_HDL_ENTER 1 +#define RX_BH_STG_HDL_EXIT 2 +#define RX_BH_STG_NEW_BUF 3 +#define RX_BH_STG_NEW_FRAME 4 +#define RX_BH_STG_NORMAL_RX 5 +#define RX_BH_STG_NORMAL_RX_END 6 +#define RX_BH_STG_C2H 7 +#define RX_BH_STG_C2H_END 8 + +#if DBG_RX_BH_TRACKING +void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s); +void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen); +void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos); +void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame); +void dump_rx_bh_tk(void *sel, struct recv_priv *recv); +#else +#define rx_bh_tk_set_stage(recv, s) do {} while (0) +#define rx_bh_tk_set_buf(recv, buf, data, dlen) do {} while (0) +#define rx_bh_tk_set_buf_pos(recv, pos) do {} while (0) +#define rx_bh_tk_set_frame(recv, frame) do {} while (0) +#define dump_rx_bh_tk(sel, recv) do {} while (0) +#endif + #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS #define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval) #endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */ @@ -514,6 +494,9 @@ struct sta_recv_priv { _queue defrag_q; /* keeping the fragment frame until defrag */ struct stainfo_rxcache rxcache; + u16 bmc_tid_rxseq[16]; + u16 nonqos_rxseq; + u16 nonqos_bmc_rxseq; /* uint sta_rx_bytes; */ /* uint sta_rx_pkts; */ @@ -561,12 +544,11 @@ struct recv_buf { #endif -#ifdef PLATFORM_LINUX - _pkt *pskb; -#endif -#ifdef PLATFORM_FREEBSD /* skb solution */ +#if defined(PLATFORM_LINUX) + _pkt *pskb; +#elif defined(PLATFORM_FREEBSD) /* skb solution */ struct sk_buff *pskb; -#endif /* PLATFORM_FREEBSD */ /* skb solution */ +#endif }; @@ -587,13 +569,7 @@ struct recv_buf { */ struct recv_frame_hdr { _list list; -#ifndef CONFIG_BSD_RX_USE_MBUF - struct sk_buff *pkt; - struct sk_buff *pkt_newalloc; -#else /* CONFIG_BSD_RX_USE_MBUF */ - _pkt *pkt; - _pkt *pkt_newalloc; -#endif /* CONFIG_BSD_RX_USE_MBUF */ + _pkt *pkt; _adapter *adapter; @@ -667,7 +643,9 @@ sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue); sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue); struct recv_buf *rtw_dequeue_recvbuf(_queue *queue); -void rtw_reordering_ctrl_timeout_handler(struct timer_list *t); +#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) +void rtw_reordering_ctrl_timeout_handler(void *pcontext); +#endif void rx_query_phy_status(union recv_frame *rframe, u8 *phy_stat); int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index); @@ -882,25 +860,19 @@ __inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex) { s32 SignalPower; /* in dBm. */ -#ifdef CONFIG_SIGNAL_SCALE_MAPPING - /* Translate to dBm (x=0.5y-95). */ - SignalPower = (s32)((SignalStrengthIndex + 1) >> 1); - SignalPower -= 95; -#else /* Translate to dBm (x=y-100) */ SignalPower = SignalStrengthIndex - 100; -#endif - return SignalPower; } - struct sta_info; extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv); extern void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame); +u8 adapter_allow_bmc_data_rx(_adapter *adapter); s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status); +void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta); #endif diff --git a/include/rtw_rf.h b/include/rtw_rf.h index c855808..5882b90 100644 --- a/include/rtw_rf.h +++ b/include/rtw_rf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,17 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_RF_H_ #define __RTW_RF_H_ #define NumRates (13) - +#define B_MODE_RATE_NUM (4) +#define G_MODE_RATE_NUM (8) +#define G_MODE_BASIC_RATE_NUM (3) /* slot time for 11g */ #define SHORT_SLOT_TIME 9 #define NON_SHORT_SLOT_TIME 20 @@ -84,13 +81,6 @@ enum _REG_PREAMBLE_MODE { PREAMBLE_SHORT = 3, }; -typedef enum _RF_PATH { - RF_PATH_A = 0, - RF_PATH_B = 1, - RF_PATH_C = 2, - RF_PATH_D = 3, -} RF_PATH, *PRF_PATH; - #define rf_path_char(path) (((path) >= RF_PATH_MAX) ? 'X' : 'A' + (path)) /* Bandwidth Offset */ @@ -111,22 +101,12 @@ extern const char *const _band_str[]; extern const u8 _band_to_band_cap[]; #define band_to_band_cap(band) (((band) >= BAND_MAX) ? _band_to_band_cap[BAND_MAX] : _band_to_band_cap[(band)]) -/* Represent Channel Width in HT Capabilities - * */ -typedef enum _CHANNEL_WIDTH { - CHANNEL_WIDTH_20 = 0, - CHANNEL_WIDTH_40 = 1, - CHANNEL_WIDTH_80 = 2, - CHANNEL_WIDTH_160 = 3, - CHANNEL_WIDTH_80_80 = 4, - CHANNEL_WIDTH_MAX = 5, -} CHANNEL_WIDTH, *PCHANNEL_WIDTH; extern const char *const _ch_width_str[]; -#define ch_width_str(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _ch_width_str[CHANNEL_WIDTH_MAX] : _ch_width_str[(bw)]) +#define ch_width_str(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_str[(bw)] : "CHANNEL_WIDTH_MAX") extern const u8 _ch_width_to_bw_cap[]; -#define ch_width_to_bw_cap(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] : _ch_width_to_bw_cap[(bw)]) +#define ch_width_to_bw_cap(bw) (((bw) < CHANNEL_WIDTH_MAX) ? _ch_width_to_bw_cap[(bw)] : 0) /* * Represent Extention Channel Offset in HT Capabilities @@ -159,21 +139,7 @@ typedef enum _PROTECTION_MODE { PROTECTION_MODE_FORCE_DISABLE = 2, } PROTECTION_MODE, *PPROTECTION_MODE; -typedef enum _RT_RF_TYPE_DEFINITION { - RF_1T2R = 0, - RF_2T4R = 1, - RF_2T2R = 2, - RF_1T1R = 3, - RF_2T2R_GREEN = 4, - RF_2T3R = 5, - RF_3T3R = 6, - RF_3T4R = 7, - RF_4T4R = 8, - - RF_TYPE_AUTO, -} RT_RF_TYPE_DEF_E; - -#define RF_TYPE_VALID(rf_type) (rf_type < RF_TYPE_AUTO) +#define RF_TYPE_VALID(rf_type) (rf_type < RF_TYPE_MAX) extern const u8 _rf_type_to_rf_tx_cnt[]; #define rf_type_to_rf_tx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_tx_cnt[rf_type] : 0) @@ -185,42 +151,47 @@ int rtw_ch2freq(int chan); int rtw_freq2ch(int freq); bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo); -#define RTW_MODULE_RTL8821AE_HMC_M2 BIT0 /* RTL8821AE(HMC + M.2) */ -#define RTW_MODULE_RTL8821AU BIT1 /* RTL8821AU */ -#define RTW_MODULE_RTL8812AENF_NGFF BIT2 /* RTL8812AENF(8812AE+8761)_NGFF */ -#define RTW_MODULE_RTL8812AEBT_HMC BIT3 /* RTL8812AEBT(8812AE+8761)_HMC */ -#define RTW_MODULE_RTL8188EE_HMC_M2 BIT4 /* RTL8188EE(HMC + M.2) */ -#define RTW_MODULE_RTL8723BE_HMC_M2 BIT5 /* RTL8723BE(HMC + M.2) */ -#define RTW_MODULE_RTL8723BS_NGFF1216 BIT6 /* RTL8723BS(NGFF1216) */ -#define RTW_MODULE_RTL8192EEBT_HMC_M2 BIT7 /* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */ -#define RTW_MODULE_RTL8723DE_NGFF1630 BIT8 /* RTL8723DE(NGFF1630) */ - -#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF) - -struct country_chplan { - char alpha2[2]; - u8 chplan; -#ifdef CONFIG_80211AC_VHT - u8 en_11ac; -#endif -#if RTW_DEF_MODULE_REGULATORY_CERT - u16 def_module_flags; /* RTW_MODULE_RTLXXX */ -#endif +struct rf_ctl_t; + +typedef enum _REGULATION_TXPWR_LMT { + TXPWR_LMT_NONE = 0, /* no limit */ + TXPWR_LMT_FCC = 1, + TXPWR_LMT_MKK = 2, + TXPWR_LMT_ETSI = 3, + TXPWR_LMT_IC = 4, + TXPWR_LMT_KCC = 5, + TXPWR_LMT_ACMA = 6, + TXPWR_LMT_CHILE = 7, + TXPWR_LMT_WW = 8, /* smallest of all available limit, keep last */ +} REGULATION_TXPWR_LMT; + +extern const char *const _regd_str[]; +#define regd_str(regd) (((regd) > TXPWR_LMT_WW) ? _regd_str[TXPWR_LMT_WW] : _regd_str[(regd)]) + +#ifdef CONFIG_TXPWR_LIMIT +struct regd_exc_ent { + _list list; + char country[2]; + u8 domain; + char regd_name[0]; }; -#ifdef CONFIG_80211AC_VHT -#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac) -#else -#define COUNTRY_CHPLAN_EN_11AC(_ent) 0 -#endif - -#if RTW_DEF_MODULE_REGULATORY_CERT -#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) ((_ent)->def_module_flags) -#else -#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) 0 -#endif - -const struct country_chplan *rtw_get_chplan_from_country(const char *country_code); +void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl); +void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen); +void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name); +struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain); +struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain); +void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl); + +void dump_txpwr_lmt(void *sel, _adapter *adapter); +void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen + , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt); +void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name + , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt); +struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name); +struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name); +void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl); +#endif /* CONFIG_TXPWR_LIMIT */ #define BB_GAIN_2G 0 #ifdef CONFIG_IEEE80211_BAND_5GHZ @@ -241,10 +212,22 @@ int rtw_ch_to_bb_gain_sel(int ch); void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset); void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch); -u8 rtw_is_5g_band1(u8 ch); -u8 rtw_is_5g_band2(u8 ch); -u8 rtw_is_5g_band3(u8 ch); -u8 rtw_is_5g_band4(u8 ch); +/* only check channel ranges */ +#define rtw_is_2g_ch(ch) (ch >= 1 && ch <= 14) +#define rtw_is_5g_ch(ch) ((ch) >= 36 && (ch) <= 177) +#define rtw_is_same_band(a, b) \ + ((rtw_is_2g_ch(a) && rtw_is_2g_ch(b)) \ + || (rtw_is_5g_ch(a) && rtw_is_5g_ch(b))) + +#define rtw_is_5g_band1(ch) ((ch) >= 36 && (ch) <= 48) +#define rtw_is_5g_band2(ch) ((ch) >= 52 && (ch) <= 64) +#define rtw_is_5g_band3(ch) ((ch) >= 100 && (ch) <= 144) +#define rtw_is_5g_band4(ch) ((ch) >= 149 && (ch) <= 177) +#define rtw_is_same_5g_band(a, b) \ + ((rtw_is_5g_band1(a) && rtw_is_5g_band1(b)) \ + || (rtw_is_5g_band2(a) && rtw_is_5g_band2(b)) \ + || (rtw_is_5g_band3(a) && rtw_is_5g_band3(b)) \ + || (rtw_is_5g_band4(a) && rtw_is_5g_band4(b))) u8 rtw_is_dfs_range(u32 hi, u32 lo); u8 rtw_is_dfs_ch(u8 ch); diff --git a/include/rtw_rm.h b/include/rtw_rm.h new file mode 100644 index 0000000..9efcf13 --- /dev/null +++ b/include/rtw_rm.h @@ -0,0 +1,88 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __RTW_RM_H_ +#define __RTW_RM_H_ + +u8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf); + +#define RM_TIMER_NUM 32 +#define RM_ALL_MEAS BIT(1) +#define RM_ID_FOR_ALL(aid) ((aid<<16)|RM_ALL_MEAS) + +#define RM_CAP_ARG(x) ((u8 *)(x))[4], ((u8 *)(x))[3], ((u8 *)(x))[2], ((u8 *)(x))[1], ((u8 *)(x))[0] +#define RM_CAP_FMT "%02x %02x%02x %02x%02x" + +/* remember to modify rm_event_name() when adding new event */ +enum RM_EV_ID { + RM_EV_state_in, + RM_EV_busy_timer_expire, + RM_EV_delay_timer_expire, + RM_EV_meas_timer_expire, + RM_EV_retry_timer_expire, + RM_EV_repeat_delay_expire, + RM_EV_request_timer_expire, + RM_EV_wait_report, + RM_EV_start_meas, + RM_EV_survey_done, + RM_EV_recv_rep, + RM_EV_cancel, + RM_EV_state_out, + RM_EV_max +}; + +struct rm_event { + u32 rmid; + enum RM_EV_ID evid; + _list list; +}; + +#ifdef CONFIG_RTW_80211K + +struct rm_clock { + struct rm_obj *prm; + ATOMIC_T counter; + enum RM_EV_ID evid; +}; + +struct rm_priv { + u8 enable; + _queue ev_queue; + _queue rm_queue; + _timer rm_timer; + + struct rm_clock clock[RM_TIMER_NUM]; + u8 rm_en_cap_def[5]; + u8 rm_en_cap_assoc[5]; + + /* rm debug */ + void *prm_sel; +}; + +int rtw_init_rm(_adapter *padapter); +int rtw_free_rm_priv(_adapter *padapter); + +unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame); +void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter, + struct sta_info *psta, struct rtw_ieee802_11_elems *elems); + +int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid); +void rm_handler(_adapter *padapter, struct rm_event *pev); + +u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta); + +#endif /*CONFIG_RTW_80211K */ +#endif /* __RTW_RM_H_ */ diff --git a/include/rtw_rm_fsm.h b/include/rtw_rm_fsm.h new file mode 100644 index 0000000..ba903a9 --- /dev/null +++ b/include/rtw_rm_fsm.h @@ -0,0 +1,389 @@ + +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __RTW_RM_FSM_H_ +#define __RTW_RM_FSM_H_ + +#ifdef CONFIG_RTW_80211K + +#define RM_SUPPORT_IWPRIV_DBG 1 +#define RM_MORE_DBG_MSG 0 + +#define DBG_BCN_REQ_DETAIL 0 +#define DBG_BCN_REQ_WILDCARD 0 +#define DBG_BCN_REQ_SSID 0 +#define DBG_BCN_REQ_SSID_NAME "RealKungFu" + +#define RM_REQ_TIMEOUT 10000 /* 10 seconds */ +#define RM_MEAS_TIMEOUT 10000 /* 10 seconds */ +#define RM_REPT_SCAN_INTVL 5000 /* 5 seconds */ +#define RM_REPT_POLL_INTVL 2000 /* 2 seconds */ +#define RM_COND_INTVL 2000 /* 2 seconds */ +#define RM_SCAN_DENY_TIMES 10 +#define RM_BUSY_TRAFFIC_TIMES 10 +#define RM_WAIT_BUSY_TIMEOUT 1000 /* 1 seconds */ + +#define MEAS_REQ_MOD_PARALLEL BIT(0) +#define MEAS_REQ_MOD_ENABLE BIT(1) +#define MEAS_REQ_MOD_REQUEST BIT(2) +#define MEAS_REQ_MOD_REPORT BIT(3) +#define MEAS_REQ_MOD_DUR_MAND BIT(4) + +#define MEAS_REP_MOD_LATE BIT(0) +#define MEAS_REP_MOD_INCAP BIT(1) +#define MEAS_REP_MOD_REFUSE BIT(2) + +#define RM_MASTER BIT(0) /* STA who issue meas_req */ +#define RM_SLAVE 0 /* STA who do measurement */ + +#define CLOCK_UNIT 10 /* ms */ +#define RTW_MAX_NB_RPT_IE_NUM 16 + +#define RM_GET_AID(rmid) ((rmid&0xffff0000)>>16) +#define RM_IS_ID_FOR_ALL(rmid) (rmid&RM_ALL_MEAS) + +/* + * define the following channels as the max channels in each channel plan. + * 2G, total 14 chnls + * {1,2,3,4,5,6,7,8,9,10,11,12,13,14} + * 5G, total 25 chnls + * {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,144,149,153,157,161,165} + */ +#define MAX_OP_CHANNEL_SET_NUM 11 +typedef struct _RT_OPERATING_CLASS { + int global_op_class; + int Len; + u16 Channel[MAX_OP_CHANNEL_SET_NUM]; +} RT_OPERATING_CLASS, *PRT_OPERATING_CLASS; + +/* IEEE 802.11-2012 Table 8-59 Measurement Type definitions +* for measurement request +* modify rm_meas_type_req_name() when adding new type +*/ +enum meas_type_of_req { + basic_req, /* spectrum measurement */ + cca_req, + rpi_histo_req, + ch_load_req, + noise_histo_req, + bcn_req, + frame_req, + sta_statis_req, + lci_req, + meas_type_req_max, +}; + +/* IEEE 802.11-2012 Table 8-81 Measurement Type definitions +* for measurement report +* modify rm_type_rep_name() when adding new type +*/ +enum meas_type_of_rep { + basic_rep, /* spectrum measurement */ + cca_rep, + rpi_histo_rep, + ch_load_rep, /* radio measurement */ + noise_histo_rep, + bcn_rep, + frame_rep, + sta_statis_rep, /* Radio measurement and WNM */ + lci_rep, + meas_type_rep_max +}; + +/* +* Beacon request +*/ +/* IEEE 802.11-2012 Table 8-64 Measurement mode for Beacon Request element */ +enum bcn_req_meas_mode { + bcn_req_passive, + bcn_req_active, + bcn_req_bcn_table +}; + +/* IEEE 802.11-2012 Table 8-65 optional subelement IDs for Beacon Request */ +enum bcn_req_opt_sub_id{ + bcn_req_ssid = 0, /* len 0-32 */ + bcn_req_rep_info = 1, /* len 2 */ + bcn_req_rep_detail = 2, /* len 1 */ + bcn_req_req = 10, /* len 0-237 */ + bcn_req_ac_ch_rep = 51 /* len 1-237 */ +}; + +/* IEEE 802.11-2012 Table 8-66 Reporting condition of Beacon Report */ +enum bcn_rep_cound_id{ + bcn_rep_cond_immediately, /* default */ + bcn_req_cond_rcpi_greater, + bcn_req_cond_rcpi_less, + bcn_req_cond_rsni_greater, + bcn_req_cond_rsni_less, + bcn_req_cond_max +}; + +struct opt_rep_info { + u8 cond; + u8 threshold; +}; + +#define BCN_REQ_OPT_MAX_NUM 16 +struct bcn_req_opt { + /* all req cmd id */ + u8 opt_id[BCN_REQ_OPT_MAX_NUM]; + u8 opt_id_num; + u8 rep_detail; + NDIS_802_11_SSID ssid; + + /* bcn report condition */ + struct opt_rep_info rep_cond; + + /* 0:default(Report to be issued after each measurement) */ + u8 *req_start; /*id : 10 request;start */ + u8 req_len; /*id : 10 request;length */ +}; + +/* +* channel load +*/ +/* IEEE 802.11-2012 Table 8-60 optional subelement IDs for channel load request */ +enum ch_load_opt_sub_id{ + ch_load_rsvd, + ch_load_rep_info +}; + +/* IEEE 802.11-2012 Table 8-61 Reporting condition for channel load Report */ +enum ch_load_cound_id{ + ch_load_cond_immediately, /* default */ + ch_load_cond_anpi_equal_greater, + ch_load_cond_anpi_equal_less, + ch_load_cond_max +}; + +/* +* Noise histogram +*/ +/* IEEE 802.11-2012 Table 8-62 optional subelement IDs for noise histogram */ +enum noise_histo_opt_sub_id{ + noise_histo_rsvd, + noise_histo_rep_info +}; + +/* IEEE 802.11-2012 Table 8-63 Reporting condition for noise historgarm Report */ +enum noise_histo_cound_id{ + noise_histo_cond_immediately, /* default */ + noise_histo_cond_anpi_equal_greater, + noise_histo_cond_anpi_equal_less, + noise_histo_cond_max +}; + +struct meas_req_opt { + /* report condition */ + struct opt_rep_info rep_cond; +}; + +/* +* State machine +*/ + +enum RM_STATE { + RM_ST_IDLE, + RM_ST_DO_MEAS, + RM_ST_WAIT_MEAS, + RM_ST_SEND_REPORT, + RM_ST_RECV_REPORT, + RM_ST_END, + RM_ST_MAX +}; + +struct rm_meas_req { + u8 category; + u8 action_code; /* T8-206 */ + u8 diag_token; + u16 rpt; + + u8 e_id; + u8 len; + u8 m_token; + u8 m_mode; /* req:F8-105, rep:F8-141 */ + u8 m_type; /* T8-59 */ + u8 op_class; + u8 ch_num; + u16 rand_intvl; /* units of TU */ + u16 meas_dur; /* units of TU */ + + u8 bssid[6]; /* for bcn_req */ + + u8 *pssid; + u8 *opt_s_elem_start; + int opt_s_elem_len; + + union { + struct bcn_req_opt bcn; + struct meas_req_opt clm; + struct meas_req_opt nhm; + }opt; + + struct rtw_ieee80211_channel ch_set[MAX_OP_CHANNEL_SET_NUM]; + u8 ch_set_ch_amount; +}; + +struct rm_meas_rep { + u8 category; + u8 action_code; /* T8-206 */ + u8 diag_token; + + u8 e_id; /* T8-54, 38 request; 39 report */ + u8 len; + u8 m_token; + u8 m_mode; /* req:F8-105, rep:F8-141 */ + u8 m_type; /* T8-59 */ + u8 op_class; + u8 ch_num; + + u8 ch_load; + u8 anpi; + u8 ipi[11]; + + u16 rpt; + u8 bssid[6]; /* for bcn_req */ +}; + +#define MAX_BUF_NUM 128 +struct data_buf { + u8 *pbuf; + u16 len; +}; + +struct rm_obj { + + /* aid << 16 + |diag_token << 8 + |B(1) 1/0:All_AID/UNIC + |B(0) 1/0:RM_MASTER/RM_SLAVE */ + u32 rmid; + + enum RM_STATE state; + struct rm_meas_req q; + struct rm_meas_rep p; + struct sta_info *psta; + struct rm_clock *pclock; + + /* meas report */ + u64 meas_start_time; + u64 meas_end_time; + int wait_busy; + u8 poll_mode; + + struct data_buf buf[MAX_BUF_NUM]; + + _list list; +}; + +/* +* Measurement +*/ +struct opt_subelement { + u8 id; + u8 length; + u8 *data; +}; + +/* 802.11-2012 Table 8-206 Radio Measurment Action field */ +enum rm_action_code { + RM_ACT_RADIO_MEAS_REQ, + RM_ACT_RADIO_MEAS_REP, + RM_ACT_LINK_MEAS_REQ, + RM_ACT_LINK_MEAS_REP, + RM_ACT_NB_REP_REQ, /* 4 */ + RM_ACT_NB_REP_RESP, + RM_ACT_RESV, + RM_ACT_MAX +}; + +/* 802.11-2012 Table 8-119 RM Enabled Capabilities definition */ +enum rm_cap_en { + RM_LINK_MEAS_CAP_EN, + RM_NB_REP_CAP_EN, /* neighbor report */ + RM_PARAL_MEAS_CAP_EN, /* parallel report */ + RM_REPEAT_MEAS_CAP_EN, + RM_BCN_PASSIVE_MEAS_CAP_EN, + RM_BCN_ACTIVE_MEAS_CAP_EN, + RM_BCN_TABLE_MEAS_CAP_EN, + RM_BCN_MEAS_REP_COND_CAP_EN, /* conditions */ + + RM_FRAME_MEAS_CAP_EN, + RM_CH_LOAD_CAP_EN, + RM_NOISE_HISTO_CAP_EN, /* noise historgram */ + RM_STATIS_MEAS_CAP_EN, /* statistics */ + RM_LCI_MEAS_CAP_EN, /* 12 */ + RM_LCI_AMIMUTH_CAP_EN, + RM_TRANS_STREAM_CAT_MEAS_CAP_EN, + RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN, + + RM_AP_CH_REP_CAP_EN, + RM_RM_MIB_CAP_EN, + RM_OP_CH_MAX_MEAS_DUR0, /* 18-20 */ + RM_OP_CH_MAX_MEAS_DUR1, + RM_OP_CH_MAX_MEAS_DUR2, + RM_NONOP_CH_MAX_MEAS_DUR0, /* 21-23 */ + RM_NONOP_CH_MAX_MEAS_DUR1, + RM_NONOP_CH_MAX_MEAS_DUR2, + + RM_MEAS_PILOT_CAP0, /* 24-26 */ + RM_MEAS_PILOT_CAP1, + RM_MEAS_PILOT_CAP2, + RM_MEAS_PILOT_TRANS_INFO_CAP_EN, + RM_NB_REP_TSF_OFFSET_CAP_EN, + RM_RCPI_MEAS_CAP_EN, /* 29 */ + RM_RSNI_MEAS_CAP_EN, + RM_BSS_AVG_ACCESS_DELAY_CAP_EN, + + RM_AVALB_ADMIS_CAPACITY_CAP_EN, + RM_ANT_CAP_EN, + RM_RSVD, /* 34-39 */ + RM_MAX +}; + +char *rm_state_name(enum RM_STATE state); +char *rm_event_name(enum RM_EV_ID evid); +char *rm_type_req_name(u8 meas_type); +int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid); +int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *obj, bool to_head); + +void rm_free_rmobj(struct rm_obj *prm); +struct rm_obj *rm_alloc_rmobj(_adapter *padapter); +struct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid); +struct sta_info *rm_get_psta(_adapter *padapter, u32 rmid); + +int retrieve_radio_meas_result(struct rm_obj *prm); +int rm_radio_meas_report_cond(struct rm_obj *prm); +int rm_recv_radio_mens_req(_adapter *padapter, + union recv_frame *precv_frame,struct sta_info *psta); +int rm_recv_radio_mens_rep(_adapter *padapter, + union recv_frame *precv_frame, struct sta_info *psta); +int rm_radio_mens_nb_rep(_adapter *padapter, + union recv_frame *precv_frame, struct sta_info *psta); +int issue_null_reply(struct rm_obj *prm); +int issue_beacon_rep(struct rm_obj *prm); +int issue_nb_req(struct rm_obj *prm); +int issue_radio_meas_req(struct rm_obj *prm); +int issue_radio_meas_rep(struct rm_obj *prm); + +void rm_set_rep_mode(struct rm_obj *prm, u8 mode); + +int ready_for_scan(struct rm_obj *prm); +int rm_sitesurvey(struct rm_obj *prm); + +#endif /*CONFIG_RTW_80211K*/ +#endif /*__RTW_RM_FSM_H_*/ diff --git a/include/rtw_rson.h b/include/rtw_rson.h new file mode 100644 index 0000000..6996738 --- /dev/null +++ b/include/rtw_rson.h @@ -0,0 +1,61 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_RSON_H_ +#define __RTW_RSON_H_ + + +#define RTW_RSON_VER 1 + +#define RTW_RSON_SCORE_NOTSUP 0x0 +#define RTW_RSON_SCORE_NOTCNNT 0x1 +#define RTW_RSON_SCORE_MAX 0xFF +#define RTW_RSON_HC_NOTREADY 0xFF +#define RTW_RSON_HC_ROOT 0x0 +#define RTW_RSON_ALLOWCONNECT 0x1 +#define RTW_RSON_DENYCONNECT 0x0 + + + +/* for rtw self-origanization spec 1 */ +struct rtw_rson_struct { + u8 ver; + u32 id; + u8 hopcnt; + u8 connectible; + u8 loading; + u8 res[16]; +} __attribute__((__packed__)); + +void init_rtw_rson_data(struct dvobj_priv *dvobj); +void rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str); +int rtw_rson_set_property(_adapter *padapter, char *field, char *value); +int rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor); +int rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct rtw_rson_struct *rson_data); +u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI Rssi); +void rtw_rson_handle_ie(WLAN_BSSID_EX *bssid, u8 ie_offset); +u32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len); +void rtw_rson_do_disconnect(_adapter *padapter); +void rtw_rson_join_done(_adapter *padapter); +int rtw_rson_isupdate_roamcan(struct mlme_priv *mlme, struct wlan_network **candidate, struct wlan_network *competitor); +void rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead); +u8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset); +u8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op); +void rtw_rson_scan_cmd_hdl(_adapter *padapter, int op); +#endif /* __RTW_RSON_H_ */ diff --git a/include/rtw_sdio.h b/include/rtw_sdio.h index da86a3a..7490b54 100644 --- a/include/rtw_sdio.h +++ b/include/rtw_sdio.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * Copyright(c) 2015 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_SDIO_H_ #define _RTW_SDIO_H_ diff --git a/include/rtw_security.h b/include/rtw_security.h index d413216..ac8432e 100644 --- a/include/rtw_security.h +++ b/include/rtw_security.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_SECURITY_H_ #define __RTW_SECURITY_H_ @@ -27,16 +22,18 @@ #define _TKIP_WTMIC_ 0x3 #define _AES_ 0x4 #define _WEP104_ 0x5 -#define _WEP_WPA_MIXED_ 0x07 /* WEP + WPA */ #define _SMS4_ 0x06 -#ifdef CONFIG_IEEE80211W +#define _WEP_WPA_MIXED_ 0x07 /* WEP + WPA */ #define _BIP_ 0x8 -#endif /* CONFIG_IEEE80211W */ + /* 802.11W use wrong key */ #define IEEE80211W_RIGHT_KEY 0x0 #define IEEE80211W_WRONG_KEY 0x1 #define IEEE80211W_NO_KEY 0x2 +#define CCMPH_2_PN(ch) ((ch) & 0x000000000000ffff) \ + | (((ch) & 0xffffffff00000000) >> 16) + #define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_)) const char *security_type_str(u8 value); @@ -129,23 +126,24 @@ struct security_priv { /* WEP */ u32 dot11PrivacyKeyIndex; /* this is only valid for legendary wep, 0~3 for key id. (tx key index) */ - union Keytype dot11DefKey[4]; /* this is only valid for def. key */ - u32 dot11DefKeylen[4]; - u8 dot11Def_camid[4]; + union Keytype dot11DefKey[6]; /* this is only valid for def. key */ + u32 dot11DefKeylen[6]; + u8 dot11Def_camid[6]; u8 key_mask; /* use to restore wep key after hal_init */ u32 dot118021XGrpPrivacy; /* This specify the privacy algthm. used for Grp key */ u32 dot118021XGrpKeyid; /* key id used for Grp Key ( tx key index) */ - union Keytype dot118021XGrpKey[4]; /* 802.1x Group Key, for inx0 and inx1 */ - union Keytype dot118021XGrptxmickey[4]; - union Keytype dot118021XGrprxmickey[4]; + union Keytype dot118021XGrpKey[6]; /* 802.1x Group Key, for inx0 and inx1 */ + union Keytype dot118021XGrptxmickey[6]; + union Keytype dot118021XGrprxmickey[6]; union pn48 dot11Grptxpn; /* PN48 used for Grp Key xmit. */ union pn48 dot11Grprxpn; /* PN48 used for Grp Key recv. */ + u8 iv_seq[4][8]; #ifdef CONFIG_IEEE80211W u32 dot11wBIPKeyid; /* key id used for BIP Key ( tx key index) */ union Keytype dot11wBIPKey[6]; /* BIP Key, for index4 and index5 */ - union pn48 dot11wBIPtxpn; /* PN48 used for Grp Key xmit. */ - union pn48 dot11wBIPrxpn; /* PN48 used for Grp Key recv. */ + union pn48 dot11wBIPtxpn; /* PN48 used for BIP xmit. */ + union pn48 dot11wBIPrxpn; /* PN48 used for BIP recv. */ #endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_AP_MODE /* extend security capabilities for AP_MODE */ @@ -155,6 +153,7 @@ struct security_priv { unsigned int wpa2_group_cipher; unsigned int wpa_pairwise_cipher; unsigned int wpa2_pairwise_cipher; + u8 mfp_opt; #endif #ifdef CONFIG_CONCURRENT_MODE u8 dot118021x_bmc_cam_id; @@ -202,10 +201,10 @@ struct security_priv { /* for tkip countermeasure */ - u32 last_mic_err_time; + systime last_mic_err_time; u8 btkip_countermeasure; u8 btkip_wait_report; - u32 btkip_countermeasure_time; + systime btkip_countermeasure_time; /* --------------------------------------------------------------------------- */ /* For WPA2 Pre-Authentication. */ @@ -244,6 +243,12 @@ struct security_priv { #endif /* DBG_SW_SEC_CNT */ }; +#ifdef CONFIG_IEEE80211W +#define SEC_IS_BIP_KEY_INSTALLED(sec) ((sec)->binstallBIPkey) +#else +#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE +#endif + struct sha256_state { u64 length; u32 state[8], curlen; @@ -405,11 +410,6 @@ static inline u32 rotr(u32 val, int bits) (a)[7] = (u8) (((u64) (val)) & 0xff); \ } while (0) -/* ===== start - public domain SHA256 implementation ===== */ - -/* This is based on SHA256 implementation in LibTomCrypt that was released into - * public domain by Tom St Denis. */ - /* the K array */ static const unsigned long K[64] = { 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL, @@ -444,8 +444,14 @@ static const unsigned long K[64] = { #define MIN(x, y) (((x) < (y)) ? (x) : (y)) #endif #ifdef CONFIG_IEEE80211W -int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac); +int omac1_aes_128(const u8 *key, const u8 *data, size_t data_len, u8 *mac); #endif /* CONFIG_IEEE80211W */ +#ifdef CONFIG_RTW_MESH_AEK +int aes_siv_encrypt(const u8 *key, const u8 *pw, size_t pwlen + , size_t num_elem, const u8 *addr[], const size_t *len, u8 *out); +int aes_siv_decrypt(const u8 *key, const u8 *iv_crypt, size_t iv_c_len + , size_t num_elem, const u8 *addr[], const size_t *len, u8 *out); +#endif void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key); void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b); void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nBytes); @@ -467,8 +473,9 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe); u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe); void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe); #ifdef CONFIG_IEEE80211W -u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe); -#endif /* CONFIG_IEEE80211W */ +u32 rtw_BIP_verify(_adapter *padapter, u8 *whdr_pos, sint flen + , const u8 *key, u16 id, u64* ipn); +#endif #ifdef CONFIG_TDLS void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta); int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq, diff --git a/include/rtw_sreset.h b/include/rtw_sreset.h index 0ecdfc7..1fd999a 100644 --- a/include/rtw_sreset.h +++ b/include/rtw_sreset.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_SRESET_H_ #define _RTW_SRESET_H_ @@ -26,16 +21,27 @@ enum { SRESET_TGP_NULL = 0, SRESET_TGP_XMIT_STATUS = 1, SRESET_TGP_LINK_STATUS = 2, + SRESET_TGP_INFO = 99, }; struct sreset_priv { _mutex silentreset_mutex; u8 silent_reset_inprogress; u8 Wifi_Error_Status; - unsigned long last_tx_time; - unsigned long last_tx_complete_time; + systime last_tx_time; + systime last_tx_complete_time; s32 dbg_trigger_point; + u64 self_dect_tx_cnt; + u64 self_dect_rx_cnt; + u64 self_dect_fw_cnt; + u64 tx_dma_status_cnt; + u64 rx_dma_status_cnt; + u8 rx_cnt; + u8 self_dect_fw; + u8 self_dect_case; + u16 last_mac_rxff_ptr; + u8 dbg_sreset_ctrl; }; diff --git a/include/rtw_tdls.h b/include/rtw_tdls.h index ad16d66..5c23e4e 100644 --- a/include/rtw_tdls.h +++ b/include/rtw_tdls.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_TDLS_H_ #define __RTW_TDLS_H_ @@ -63,13 +58,23 @@ enum TDLS_CH_SW_CHNL { TDLS_CH_SW_OFF_CHNL }; +#define TDLS_MIC_CTRL_LEN 2 +#define TDLS_FTIE_DATA_LEN (TDLS_MIC_CTRL_LEN + TDLS_MIC_LEN + \ + WPA_NONCE_LEN + WPA_NONCE_LEN) struct wpa_tdls_ftie { u8 ie_type; /* FTIE */ u8 ie_len; - u8 mic_ctrl[2]; - u8 mic[TDLS_MIC_LEN]; - u8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */ - u8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */ + union { + struct { + u8 mic_ctrl[TDLS_MIC_CTRL_LEN]; + u8 mic[TDLS_MIC_LEN]; + u8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */ + u8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */ + }; + struct { + u8 data[TDLS_FTIE_DATA_LEN]; + }; + }; /* followed by optional elements */ } ; @@ -103,18 +108,26 @@ static u8 TDLS_SRC[] = { 0x01, 0x01, 0x02, 0x03, 0x04, 0x0c, 0x16, 0x17, 0x18, 0 int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len); int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len); +void rtw_set_tdls_enable(_adapter *padapter, u8 enable); +u8 rtw_is_tdls_enabled(_adapter *padapter); +u8 rtw_is_tdls_sta_existed(_adapter *padapter); u8 rtw_tdls_is_setup_allowed(_adapter *padapter); #ifdef CONFIG_TDLS_CH_SW u8 rtw_tdls_is_chsw_allowed(_adapter *padapter); #endif +void rtw_tdls_set_link_established(_adapter *adapter, bool en); void rtw_reset_tdls_info(_adapter *padapter); int rtw_init_tdls_info(_adapter *padapter); void rtw_free_tdls_info(struct tdls_info *ptdlsinfo); +void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd); +void rtw_enable_tdls_func(_adapter *padapter); +void rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd); int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta); -void rtw_free_tdls_timer(struct sta_info *psta); -void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta); +void rtw_cancel_tdls_timer(struct sta_info *psta); +void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta); +void rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd); #ifdef CONFIG_TDLS_CH_SW void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable); @@ -140,31 +153,30 @@ int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta); int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack); #endif sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame); -sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame); -int On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame); -int On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame); +sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +int On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +int On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); int On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame); -int On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame); -int On_TDLS_Peer_Traffic_Indication(_adapter *adapter, union recv_frame *precv_frame); -int On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame); +int On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +int On_TDLS_Peer_Traffic_Indication(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +int On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); #ifdef CONFIG_TDLS_CH_SW -sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame); -sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame); -void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); -void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta); +void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); +void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); #endif -void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); -void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); -void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); -void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); +void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); +void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); +void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); void rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy); -void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); -void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); +void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta); void rtw_build_tunneled_probe_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe); void rtw_build_tunneled_probe_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe); -u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta); int rtw_tdls_is_driver_setup(_adapter *padapter); void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta); const char *rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action); diff --git a/include/rtw_version.h b/include/rtw_version.h index 012654a..6d7c432 100644 --- a/include/rtw_version.h +++ b/include/rtw_version.h @@ -1,2 +1,2 @@ -#define DRIVERVERSION "v5.2.5_1.26055.20180108.1" -#define BTCOEXVERSION "COEX20170310-1212" +#define DRIVERVERSION "v5.5.2_34066.20190614_COEX20180712-3232" +#define BTCOEXVERSION "COEX20180712-3232" diff --git a/include/rtw_vht.h b/include/rtw_vht.h index dda83f9..8812222 100644 --- a/include/rtw_vht.h +++ b/include/rtw_vht.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,15 +11,13 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_VHT_H_ #define _RTW_VHT_H_ +#define VHT_CAP_IE_LEN 12 +#define VHT_OP_IE_LEN 5 + #define LDPC_VHT_ENABLE_RX BIT0 #define LDPC_VHT_ENABLE_TX BIT1 #define LDPC_VHT_TEST_TX_ENABLE BIT2 @@ -30,15 +28,6 @@ #define STBC_VHT_TEST_TX_ENABLE BIT2 #define STBC_VHT_CAP_TX BIT3 -#define BEAMFORMING_VHT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */ -#define BEAMFORMING_VHT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */ -#define BEAMFORMING_VHT_MU_MIMO_AP_ENABLE BIT2 /*Declare our NIC support MU-MIMO AP mode*/ -#define BEAMFORMING_VHT_MU_MIMO_STA_ENABLE BIT3 /*Declare our NIC support MU-MIMO STA mode*/ -#define BEAMFORMING_VHT_BEAMFORMER_TEST BIT4 /*Transmiting Beamforming no matter the target supports it or not*/ -#define BEAMFORMING_VHT_BEAMFORMER_STS_CAP (BIT8 | BIT9 | BIT10) /*Asoc rsp cap*/ -#define BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM (BIT12 | BIT13 | BIT14) /*Asoc rsp cap*/ - - /* VHT capability info */ #define SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) #define SET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val) @@ -107,23 +96,61 @@ #define SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+7, 6, 1, _val) #define GET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+7, 6, 1) +#define VHT_MAX_MPDU_LEN_MAX 3 +extern const u16 _vht_max_mpdu_len[]; +#define vht_max_mpdu_len(val) (((val) >= VHT_MAX_MPDU_LEN_MAX) ? _vht_max_mpdu_len[VHT_MAX_MPDU_LEN_MAX] : _vht_max_mpdu_len[(val)]) + +#define VHT_SUP_CH_WIDTH_SET_MAX 3 +extern const u8 _vht_sup_ch_width_set_to_bw_cap[]; +#define vht_sup_ch_width_set_to_bw_cap(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_to_bw_cap[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_to_bw_cap[(set)]) +extern const char *const _vht_sup_ch_width_set_str[]; +#define vht_sup_ch_width_set_str(set) (((set) >= VHT_SUP_CH_WIDTH_SET_MAX) ? _vht_sup_ch_width_set_str[VHT_SUP_CH_WIDTH_SET_MAX] : _vht_sup_ch_width_set_str[(set)]) + +#define VHT_MAX_AMPDU_LEN(f) ((1 << (13 + f)) - 1) +void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len); + +#define VHT_OP_CH_WIDTH_MAX 4 +extern const char *const _vht_op_ch_width_str[]; +#define vht_op_ch_width_str(ch_width) (((ch_width) >= VHT_OP_CH_WIDTH_MAX) ? _vht_op_ch_width_str[VHT_OP_CH_WIDTH_MAX] : _vht_op_ch_width_str[(ch_width)]) + +void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len); + struct vht_priv { u8 vht_option; u8 ldpc_cap; u8 stbc_cap; u16 beamform_cap; + u8 ap_is_mu_bfer; u8 sgi_80m;/* short GI */ u8 ampdu_len; - u8 vht_op_mode_notify; u8 vht_highest_rate; u8 vht_mcs_map[2]; - u8 vht_cap[32]; + u8 op_present:1; /* vht_op is present */ + u8 notify_present:1; /* vht_op_mode_notify is present */ + + u8 vht_cap[32]; + u8 vht_op[VHT_OP_IE_LEN]; + u8 vht_op_mode_notify; }; +#ifdef ROKU_PRIVATE +struct vht_priv_infra_ap { + + /* Infra mode, only store for AP's info, not intersection of STA and AP*/ + u8 ldpc_cap_infra_ap; + u8 stbc_cap_infra_ap; + u16 beamform_cap_infra_ap; + u8 vht_mcs_map_infra_ap[2]; + u8 vht_mcs_map_tx_infra_ap[2]; + u8 channel_width_infra_ap; + u8 number_of_streams_infra_ap; +}; +#endif /* ROKU_PRIVATE */ + u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map); u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate); u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss); @@ -134,11 +161,16 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf); void update_sta_vht_info_apmode(_adapter *padapter, PVOID psta); void update_hw_vht_param(_adapter *padapter); void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +#ifdef ROKU_PRIVATE +void VHT_caps_handler_infra_ap(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +#endif /* ROKU_PRIVATE */ void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta); u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len); void VHTOnAssocRsp(_adapter *padapter); u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map); void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map); - +void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pcur_network); +void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pcur_network); +void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len); #endif /* _RTW_VHT_H_ */ diff --git a/include/rtw_wapi.h b/include/rtw_wapi.h index 635aec0..512bb7f 100644 --- a/include/rtw_wapi.h +++ b/include/rtw_wapi.h @@ -1,3 +1,17 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ #ifndef __INC_WAPI_H #define __INC_WAPI_H @@ -179,7 +193,7 @@ u8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data); void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame); -u8 rtw_wapi_check_for_drop(_adapter *padapter, union recv_frame *precv_frame); +u8 rtw_wapi_check_for_drop(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_ops); void rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib); @@ -211,4 +225,6 @@ u8 WapiIncreasePN(u8 *PN, u8 AddCount); bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA); +void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param); + #endif diff --git a/include/rtw_wifi_regd.h b/include/rtw_wifi_regd.h index 2182712..8e42fce 100644 --- a/include/rtw_wifi_regd.h +++ b/include/rtw_wifi_regd.h @@ -1,6 +1,15 @@ /****************************************************************************** * - * Copyright(c) 2009-2010 Realtek Corporation. + * Copyright(c) 2009-2010 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. * *****************************************************************************/ @@ -19,7 +28,7 @@ enum country_code_type_t { COUNTRY_CODE_MAX }; -int rtw_regd_init(_adapter *padapter); -void rtw_reg_notify_by_driver(_adapter *adapter); +void rtw_regd_apply_flags(struct wiphy *wiphy); +int rtw_regd_init(struct wiphy *wiphy); #endif /* __RTW_WIFI_REGD_H__ */ diff --git a/include/rtw_xmit.h b/include/rtw_xmit.h index 00ce966..d196c68 100644 --- a/include/rtw_xmit.h +++ b/include/rtw_xmit.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_XMIT_H_ #define _RTW_XMIT_H_ @@ -32,6 +27,7 @@ #if defined CONFIG_SDIO_HCI #define NR_XMITBUFF (16) + #define SDIO_TX_DIV_NUM (2) #endif #if defined(CONFIG_GSPI_HCI) #define NR_XMITBUFF (128) @@ -89,13 +85,15 @@ #endif #ifdef CONFIG_RTL8812A - #define MAX_CMDBUF_SZ (512*14) + #define MAX_CMDBUF_SZ (512 * 18) #elif defined(CONFIG_RTL8723D) && defined(CONFIG_LPS_POFF) #define MAX_CMDBUF_SZ (128*70) /*(8960)*/ #else #define MAX_CMDBUF_SZ (5120) /* (4096) */ #endif +#define MAX_BEACON_LEN 512 + #define MAX_NUMBLKS (1) #define XMIT_VO_QUEUE (0) @@ -124,16 +122,17 @@ #define WEP_IV(pattrib_iv, dot11txpn, keyidx)\ do {\ + dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val + 1);\ pattrib_iv[0] = dot11txpn._byte_.TSC0;\ pattrib_iv[1] = dot11txpn._byte_.TSC1;\ pattrib_iv[2] = dot11txpn._byte_.TSC2;\ pattrib_iv[3] = ((keyidx & 0x3)<<6);\ - dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val+1);\ } while (0) #define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\ do {\ + dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\ pattrib_iv[0] = dot11txpn._byte_.TSC1;\ pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\ pattrib_iv[2] = dot11txpn._byte_.TSC0;\ @@ -142,11 +141,11 @@ pattrib_iv[5] = dot11txpn._byte_.TSC3;\ pattrib_iv[6] = dot11txpn._byte_.TSC4;\ pattrib_iv[7] = dot11txpn._byte_.TSC5;\ - dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\ } while (0) #define AES_IV(pattrib_iv, dot11txpn, keyidx)\ do {\ + dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\ pattrib_iv[0] = dot11txpn._byte_.TSC0;\ pattrib_iv[1] = dot11txpn._byte_.TSC1;\ pattrib_iv[2] = 0;\ @@ -155,7 +154,6 @@ pattrib_iv[5] = dot11txpn._byte_.TSC3;\ pattrib_iv[6] = dot11txpn._byte_.TSC4;\ pattrib_iv[7] = dot11txpn._byte_.TSC5;\ - dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\ } while (0) /* Check if AMPDU Tx is supported or not. If it is supported, @@ -187,7 +185,8 @@ #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) ||\ defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8192E) ||\ defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8703B) ||\ - defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8723D) + defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) ||\ + defined(CONFIG_RTL8710B) || defined(CONFIG_RTL8192F) #define TXDESC_SIZE 40 #elif defined(CONFIG_RTL8822B) #define TXDESC_SIZE 48 /* HALMAC_TX_DESC_SIZE_8822B */ @@ -241,7 +240,8 @@ enum TXDESC_SC { #define TXDESC_64_BYTES #endif #elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8723B) \ - || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8723D) + || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) \ + || defined(CONFIG_RTL8192F) #define TXDESC_40_BYTES #endif @@ -324,6 +324,21 @@ struct rtw_tx_ring { u16 hw_rp_cache; #endif }; + +#ifdef DBG_TXBD_DESC_DUMP + +#define TX_BAK_FRMAE_CNT 10 +#define TX_BAK_DESC_LEN 48 /* byte */ +#define TX_BAK_DATA_LEN 30 /* byte */ + +struct rtw_tx_desc_backup { + int tx_bak_rp; + int tx_bak_wp; + u8 tx_bak_desc[TX_BAK_DESC_LEN]; + u8 tx_bak_data_hdr[TX_BAK_DATA_LEN]; + u8 tx_desc_size; +}; +#endif #endif struct hw_xmit { @@ -380,9 +395,6 @@ struct pkt_attrib { u16 seqnum; struct sta_info *psta; -#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX - u8 hw_tcp_csum; -#endif }; #else /* reduce size */ @@ -415,6 +427,20 @@ struct pkt_attrib { u8 src[ETH_ALEN]; u8 ta[ETH_ALEN]; u8 ra[ETH_ALEN]; +#ifdef CONFIG_RTW_MESH + u8 mda[ETH_ALEN]; /* mesh da */ + u8 msa[ETH_ALEN]; /* mesh sa */ + u8 meshctrl_len; /* Length of Mesh Control field */ + u8 mesh_frame_mode; + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + u8 mb2u; + #endif + u8 mfwd_ttl; + u32 mseq; +#endif +#ifdef CONFIG_TX_CSUM_OFFLOAD + u8 hw_csum; +#endif u8 key_idx; u8 qos_en; u8 ht_en; @@ -438,10 +464,11 @@ struct pkt_attrib { u8 mbssid; u8 ldpc; u8 stbc; +#ifdef CONFIG_WMMPS_STA + u8 trigger_frame; +#endif /* CONFIG_WMMPS_STA */ + struct sta_info *psta; -#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX - u8 hw_tcp_csum; -#endif u8 rtsen; u8 cts2self; @@ -473,6 +500,12 @@ struct pkt_attrib { }; #endif +#ifdef CONFIG_RTW_MESH +#define XATTRIB_GET_MCTRL_LEN(xattrib) ((xattrib)->meshctrl_len) +#else +#define XATTRIB_GET_MCTRL_LEN(xattrib) 0 +#endif + #ifdef CONFIG_TX_AMSDU enum { RTW_AMSDU_TIMER_UNSET = 0, @@ -505,7 +538,7 @@ enum { bool rtw_xmit_ac_blocked(_adapter *adapter); struct submit_ctx { - u32 submit_time; /* */ + systime submit_time; /* */ u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */ int status; /* status for operation */ #ifdef PLATFORM_LINUX @@ -709,8 +742,6 @@ struct xmit_priv { _lock lock; _sema xmit_sema; - /*_sema terminate_xmitthread_sema;*/ - _completion xmitthread_comp; /* _queue blk_strms[MAX_NUMBLKS]; */ _queue be_pending; @@ -800,8 +831,6 @@ struct xmit_priv { #else _thread_hdl_ SdioXmitThread; _sema SdioXmitSema; - /*_sema SdioXmitTerminateSema;*/ - _completion sdio_xmit_thread_comp; #endif /* CONFIG_SDIO_TX_TASKLET */ #endif /* CONFIG_SDIO_HCI */ @@ -855,10 +884,12 @@ struct xmit_priv { u32 amsdu_debug_coalesce_one; u32 amsdu_debug_coalesce_two; +#endif +#ifdef DBG_TXBD_DESC_DUMP + BOOLEAN dump_txbd_desc; #endif _lock lock_sctx; - u8 stop_req; }; extern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, @@ -888,8 +919,11 @@ extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitb void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz); extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len); -static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta); -static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta); + +#ifdef CONFIG_WMMPS_STA +static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib); +#endif /* CONFIG_WMMPS_STA */ + extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib); extern s32 rtw_put_snap(u8 *data, u16 h_proto); @@ -906,9 +940,9 @@ extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib); #define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib) extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); -#ifdef CONFIG_IEEE80211W +#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); -#endif /* CONFIG_IEEE80211W */ +#endif #ifdef CONFIG_TDLS extern struct tdls_txmgmt *ptxmgmt; s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt); @@ -932,6 +966,7 @@ void rtw_free_hwxmits(_adapter *padapter); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev); #endif +s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt); s32 rtw_xmit(_adapter *padapter, _pkt **pkt); bool xmitframe_hiq_filter(struct xmit_frame *xmitframe); #if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) @@ -981,7 +1016,12 @@ extern s32 check_amsdu_tx_support(_adapter *padapter); extern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame); #endif -static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib); +#ifdef DBG_TXBD_DESC_DUMP +void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq); +void rtw_tx_desc_backup_reset(void); +u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak); +#endif + u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe); #ifdef CONFIG_XMIT_ACK diff --git a/include/sdio_hal.h b/include/sdio_hal.h index c8f554d..6e49835 100644 --- a/include/sdio_hal.h +++ b/include/sdio_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_HAL_H__ #define __SDIO_HAL_H__ @@ -51,4 +46,12 @@ void rtl8723ds_set_hal_ops(PADAPTER padapter); void rtl8188fs_set_hal_ops(PADAPTER padapter); #endif +#ifdef CONFIG_RTL8188GTV +void rtl8188gtvs_set_hal_ops(PADAPTER padapter); +#endif + +#ifdef CONFIG_RTL8192F +void rtl8192fs_set_hal_ops(PADAPTER padapter); +#endif + #endif /* __SDIO_HAL_H__ */ diff --git a/include/sdio_ops.h b/include/sdio_ops.h index 5deec1b..613613d 100644 --- a/include/sdio_ops.h +++ b/include/sdio_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_OPS_H__ #define __SDIO_OPS_H__ @@ -52,6 +47,11 @@ struct async_context { extern void sdio_set_intf_ops(_adapter *padapter, struct _io_ops *pops); void dump_sdio_card_info(void *sel, struct dvobj_priv *dvobj); +u32 sdio_init(struct dvobj_priv *dvobj); +void sdio_deinit(struct dvobj_priv *dvobj); +int sdio_alloc_irq(struct dvobj_priv *dvobj); +void sdio_free_irq(struct dvobj_priv *dvobj); + #if 0 extern void sdio_func1cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); extern void sdio_func1cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); @@ -91,7 +91,7 @@ void ClearInterrupt8821AS(PADAPTER padapter); #endif /* CONFIG_RTL8821A */ #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) -#ifdef CONFIG_RTL8821C +#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) u8 rtw_hal_enable_cpwm2(_adapter *adapter); #endif extern u8 RecvOnePkt(PADAPTER padapter); @@ -146,6 +146,20 @@ extern void ClearInterrupt8723DSdio(PADAPTER padapter); #endif /* CONFIG_WOWLAN */ #endif +#ifdef CONFIG_RTL8192F +extern void InitInterrupt8192FSdio(PADAPTER padapter); +extern void InitSysInterrupt8192FSdio(PADAPTER padapter); +extern void EnableInterrupt8192FSdio(PADAPTER padapter); +extern void DisableInterrupt8192FSdio(PADAPTER padapter); +extern void UpdateInterruptMask8192FSdio(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); +extern u8 HalQueryTxBufferStatus8192FSdio(PADAPTER padapter); +extern u8 HalQueryTxOQTBufferStatus8192FSdio(PADAPTER padapter); +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) +extern void DisableInterruptButCpwm2192fSdio(PADAPTER padapter); +extern void ClearInterrupt8192FSdio(PADAPTER padapter); +#endif /* CONFIG_WOWLAN */ +#endif + #ifdef CONFIG_RTL8188F extern void InitInterrupt8188FSdio(PADAPTER padapter); extern void InitSysInterrupt8188FSdio(PADAPTER padapter); @@ -159,4 +173,52 @@ extern void ClearInterrupt8188FSdio(PADAPTER padapter); #endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */ #endif +#ifdef CONFIG_RTL8188GTV +extern void InitInterrupt8188GTVSdio(PADAPTER padapter); +extern void InitSysInterrupt8188GTVSdio(PADAPTER padapter); +extern void EnableInterrupt8188GTVSdio(PADAPTER padapter); +extern void DisableInterrupt8188GTVSdio(PADAPTER padapter); +extern u8 HalQueryTxBufferStatus8188GTVSdio(PADAPTER padapter); +extern u8 HalQueryTxOQTBufferStatus8188GTVSdio(PADAPTER padapter); +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) +extern void DisableInterruptButCpwm28188GTVSdio(PADAPTER padapter); +extern void ClearInterrupt8188GTVSdio(PADAPTER padapter); +#endif /* defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) */ +#endif + +/** + * rtw_sdio_get_block_size() - Get block size of SDIO transfer + * @d struct dvobj_priv* + * + * The unit of return value is byte. + */ +static inline u32 rtw_sdio_get_block_size(struct dvobj_priv *d) +{ + return d->intf_data.block_transfer_len; +} + +/** + * rtw_sdio_cmd53_align_size() - Align size to one CMD53 could complete + * @d struct dvobj_priv* + * @len length to align + * + * Adjust len to align block size, and the new size could be transfered by one + * CMD53. + * If len < block size, it would keep original value, otherwise the value + * would be rounded up by block size. + * + * Return adjusted length. + */ +static inline size_t rtw_sdio_cmd53_align_size(struct dvobj_priv *d, size_t len) +{ + u32 blk_sz; + + + blk_sz = rtw_sdio_get_block_size(d); + if (len <= blk_sz) + return len; + + return _RND(len, blk_sz); +} + #endif /* !__SDIO_OPS_H__ */ diff --git a/include/sdio_ops_ce.h b/include/sdio_ops_ce.h index 59ca381..d542cb7 100644 --- a/include/sdio_ops_ce.h +++ b/include/sdio_ops_ce.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _SDIO_OPS_WINCE_H_ #define _SDIO_OPS_WINCE_H_ diff --git a/include/sdio_ops_linux.h b/include/sdio_ops_linux.h index 29677b3..4bbd8fe 100644 --- a/include/sdio_ops_linux.h +++ b/include/sdio_ops_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_OPS_LINUX_H__ #define __SDIO_OPS_LINUX_H__ @@ -41,7 +36,12 @@ void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err); #endif /* RTW_HALMAC */ bool rtw_is_sdio30(_adapter *adapter); -inline u32 rtw_sdio_get_clock(struct dvobj_priv *d); + +/* The unit of return value is Hz */ +static inline u32 rtw_sdio_get_clock(struct dvobj_priv *d) +{ + return d->intf_data.clock; +} s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); s32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata); @@ -53,4 +53,6 @@ int __must_check rtw_sdio_raw_read(struct dvobj_priv *d, unsigned int addr, void *buf, size_t len, bool fixed); int __must_check rtw_sdio_raw_write(struct dvobj_priv *d, unsigned int addr, void *buf, size_t len, bool fixed); -#endif + +#endif /* __SDIO_OPS_LINUX_H__ */ + diff --git a/include/sdio_ops_xp.h b/include/sdio_ops_xp.h index 5020365..d3d8764 100644 --- a/include/sdio_ops_xp.h +++ b/include/sdio_ops_xp.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _SDIO_OPS_XP_H_ #define _SDIO_OPS_XP_H_ diff --git a/include/sdio_osintf.h b/include/sdio_osintf.h index d2906bd..7c2abd1 100644 --- a/include/sdio_osintf.h +++ b/include/sdio_osintf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __SDIO_OSINTF_H__ #define __SDIO_OSINTF_H__ diff --git a/include/sta_info.h b/include/sta_info.h index bada1a7..9357664 100644 --- a/include/sta_info.h +++ b/include/sta_info.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,15 +11,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __STA_INFO_H_ #define __STA_INFO_H_ +#include #define IBSS_START_MAC_ID 2 #define NUM_STA MACID_NUM_SW_LIMIT @@ -33,14 +29,21 @@ #endif #define NUM_ACL 16 + +#define RTW_ACL_PERIOD_DEV 0 +#define RTW_ACL_PERIOD_BSS 1 +#define RTW_ACL_PERIOD_NUM 2 + #define RTW_ACL_MODE_DISABLED 0 #define RTW_ACL_MODE_ACCEPT_UNLESS_LISTED 1 #define RTW_ACL_MODE_DENY_UNLESS_LISTED 2 #define RTW_ACL_MODE_MAX 3 #if CONFIG_RTW_MACADDR_ACL -extern const char *const _acl_mode_str[]; -#define acl_mode_str(mode) (((mode) >= RTW_ACL_MODE_MAX) ? _acl_mode_str[RTW_ACL_MODE_DISABLED] : _acl_mode_str[(mode)]) +extern const char *const _acl_period_str[RTW_ACL_PERIOD_NUM]; +#define acl_period_str(mode) (((mode) >= RTW_ACL_PERIOD_NUM) ? "INVALID" : _acl_period_str[(mode)]) +extern const char *const _acl_mode_str[RTW_ACL_MODE_MAX]; +#define acl_mode_str(mode) (((mode) >= RTW_ACL_MODE_MAX) ? "INVALID" : _acl_mode_str[(mode)]) #endif #ifndef RTW_PRE_LINK_STA_NUM @@ -92,56 +95,73 @@ struct wlan_acl_pool { _queue acl_node_q; }; -typedef struct _RSSI_STA { - - s32 undecorated_smoothed_pwdb; - s32 undecorated_smoothed_cck; - s32 undecorated_smoothed_ofdm; - u8 ofdm_pkt; - u8 cck_pkt; - u16 cck_sum_power; - u8 is_send_rssi; - u64 packet_map; - u8 valid_bit; -} RSSI_STA, *PRSSI_STA; - struct stainfo_stats { + systime last_rx_time; u64 rx_mgnt_pkts; - u64 rx_beacon_pkts; - u64 rx_probereq_pkts; - u64 rx_probersp_pkts; - u64 rx_probersp_bm_pkts; - u64 rx_probersp_uo_pkts; + u64 rx_beacon_pkts; + u64 rx_probereq_pkts; + u64 rx_probersp_pkts; /* unicast to self */ + u64 rx_probersp_bm_pkts; + u64 rx_probersp_uo_pkts; /* unicast to others */ u64 rx_ctrl_pkts; u64 rx_data_pkts; - u64 rx_data_last_pkts; /* For Read & Clear requirement in proc_get_rx_stat() */ - u64 rx_data_qos_pkts[TID_NUM]; + u64 rx_data_bc_pkts; + u64 rx_data_mc_pkts; + u64 rx_data_qos_pkts[TID_NUM]; /* unicast only */ + u64 last_rx_mgnt_pkts; - u64 last_rx_beacon_pkts; - u64 last_rx_probereq_pkts; - u64 last_rx_probersp_pkts; - u64 last_rx_probersp_bm_pkts; - u64 last_rx_probersp_uo_pkts; + u64 last_rx_beacon_pkts; + u64 last_rx_probereq_pkts; + u64 last_rx_probersp_pkts; /* unicast to self */ + u64 last_rx_probersp_bm_pkts; + u64 last_rx_probersp_uo_pkts; /* unicast to others */ u64 last_rx_ctrl_pkts; u64 last_rx_data_pkts; - u64 last_rx_data_qos_pkts[TID_NUM]; + u64 last_rx_data_bc_pkts; + u64 last_rx_data_mc_pkts; + u64 last_rx_data_qos_pkts[TID_NUM]; /* unicast only */ + #ifdef CONFIG_TDLS u64 rx_tdls_disc_rsp_pkts; u64 last_rx_tdls_disc_rsp_pkts; #endif + u64 rx_bytes; - u64 rx_drops; + u64 rx_bc_bytes; + u64 rx_mc_bytes; + u64 last_rx_bytes; + u64 last_rx_bc_bytes; + u64 last_rx_mc_bytes; + u64 rx_drops; /* TBD */ + u32 rx_tp_kbits; + u32 smooth_rx_tp_kbits; u64 tx_pkts; + u64 last_tx_pkts; + u64 tx_bytes; - u64 tx_drops; + u64 last_tx_bytes; + u64 tx_drops; /* TBD */ + u32 tx_tp_kbits; + u32 smooth_tx_tp_kbits; + +#ifdef CONFIG_LPS_CHK_BY_TP + u64 acc_tx_bytes; + u64 acc_rx_bytes; +#endif + /* unicast only */ + u64 last_rx_data_uc_pkts; /* For Read & Clear requirement in proc_get_rx_stat() */ u32 duplicate_cnt; /* Read & Clear, in proc_get_rx_stat() */ u32 rxratecnt[128]; /* Read & Clear, in proc_get_rx_stat() */ u32 tx_ok_cnt; /* Read & Clear, in proc_get_tx_stat() */ u32 tx_fail_cnt; /* Read & Clear, in proc_get_tx_stat() */ u32 tx_retry_cnt; /* Read & Clear, in proc_get_tx_stat() */ +#ifdef CONFIG_RTW_MESH + u32 rx_hwmp_pkts; + u32 last_rx_hwmp_pkts; +#endif }; #ifndef DBG_SESSION_TRACKER @@ -162,7 +182,7 @@ struct session_tracker { u16 local_port; u32 remote_naddr; u16 remote_port; - u32 set_time; + systime set_time; u8 status; }; @@ -201,6 +221,7 @@ void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_regist void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id); bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto); bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); +void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos); void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl); #ifdef CONFIG_TDLS @@ -222,6 +243,21 @@ struct sta_recv_dframe_info { }; #endif +#ifdef CONFIG_RTW_MESH +struct mesh_plink_ent; +struct rtw_ewma_err_rate { + unsigned long internal; +}; + +/* Mesh airtime link metrics parameters */ +struct rtw_atlm_param { + struct rtw_ewma_err_rate err_rate; /* Now is PACKET error rate */ + u16 data_rate; /* The unit is 100Kbps */ + u16 total_pkt; + u16 overhead; /* Channel access overhead */ +}; +#endif + struct sta_info { _lock lock; @@ -231,23 +267,26 @@ struct sta_info { /* _list sleep_list; */ /* sleep_q */ /* _list wakeup_list; */ /* wakeup_q */ _adapter *padapter; + struct cmn_sta_info cmn; struct sta_xmit_priv sta_xmitpriv; struct sta_recv_priv sta_recvpriv; #ifdef DBG_RX_DFRAME_RAW_DATA struct sta_recv_dframe_info sta_dframe_info; + struct sta_recv_dframe_info sta_dframe_info_bmc; #endif _queue sleep_q; unsigned int sleepq_len; uint state; - uint aid; - uint mac_id; uint qos_option; - u8 hwaddr[ETH_ALEN]; u16 hwseq; - u8 ra_rpt_linked; + +#ifdef CONFIG_RTW_80211K + u8 rm_en_cap[5]; + u8 rm_diag_token; +#endif /* CONFIG_RTW_80211K */ uint ieee8021x_blocked; /* 0: allowed, 1:blocked */ uint dot118021XPrivacy; /* aes, tkip... */ @@ -255,39 +294,38 @@ struct sta_info { union Keytype dot11tkiprxmickey; union Keytype dot118021x_UncstKey; union pn48 dot11txpn; /* PN48 used for Unicast xmit */ + union pn48 dot11rxpn; /* PN48 used for Unicast recv. */ +#ifdef CONFIG_RTW_MESH + /* peer's GTK, RX only */ + u8 group_privacy; + u8 gtk_bmp; + union Keytype gtk; + union pn48 gtk_pn; + #ifdef CONFIG_IEEE80211W + /* peer's IGTK, RX only */ + u8 igtk_bmp; + u8 igtk_id; + union Keytype igtk; + union pn48 igtk_pn; + #endif /* CONFIG_IEEE80211W */ +#endif /* CONFIG_RTW_MESH */ #ifdef CONFIG_GTK_OL u8 kek[RTW_KEK_LEN]; u8 kck[RTW_KCK_LEN]; u8 replay_ctr[RTW_REPLAY_CTR_LEN]; #endif /* CONFIG_GTK_OL */ #ifdef CONFIG_IEEE80211W - union pn48 dot11wtxpn; /* PN48 used for Unicast mgmt xmit. */ _timer dot11w_expire_timer; #endif /* CONFIG_IEEE80211W */ - union pn48 dot11rxpn; /* PN48 used for Unicast recv. */ - u8 bssrateset[16]; u32 bssratelen; - s32 rssi; - s32 signal_quality; u8 cts2self; u8 rtsen; - u8 raid; u8 init_rate; - u64 ra_mask; u8 wireless_mode; /* NETWORK_TYPE */ - u8 bw_mode; - - u8 ldpc; - u8 stbc; - -#ifdef CONFIG_BEAMFORMING - u16 txbf_paid; - u16 txbf_gid; -#endif struct stainfo_stats sta_stats; @@ -429,50 +467,47 @@ struct sta_info { #endif /* CONFIG_AP_MODE */ +#ifdef CONFIG_RTW_MESH + struct mesh_plink_ent *plink; + + u8 local_mps; + u8 peer_mps; + u8 nonpeer_mps; + + struct rtw_atlm_param metrics; +#endif + #ifdef CONFIG_IOCTL_CFG80211 u8 *passoc_req; u32 assoc_req_len; #endif - /* for DM */ - RSSI_STA rssi_stat; - - /* ODM_STA_INFO_T */ - /* ================ODM Relative Info======================= */ - /* Please be care, dont declare too much structure here. It will cost memory * STA support num. */ - /* */ - /* */ - /* 2011/10/20 MH Add for ODM STA info. */ - /* */ - /* Driver Write */ - u8 bValid; /* record the sta status link or not? */ - /* u8 WirelessMode; */ /* */ u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ - /* ODM Write */ - /* 1 PHY_STATUS_INFO */ - u8 RSSI_Path[4]; /* */ - u8 RSSI_Ave; - u8 RXEVM[4]; - u8 RXSNR[4]; - - u8 rssi_level; /* for Refresh RA mask */ #ifdef CONFIG_LPS_PG u8 lps_pg_rssi_lv; #endif - /* ODM Write */ - /* 1 TX_INFO (may changed by IC) */ - /* TX_INFO_T pTxInfo; */ /* Define in IC folder. Move lower layer. */ - /* */ - /* ================ODM Relative Info======================= */ - /* */ /* To store the sequence number of received management frame */ u16 RxMgmtFrameSeqNum; struct st_ctl_t st_ctl; u8 max_agg_num_minimal_record; /*keep minimal tx desc max_agg_num setting*/ + u8 curr_rx_rate; + u8 curr_rx_rate_bmc; }; +#ifdef CONFIG_RTW_MESH +#define STA_SET_MESH_PLINK(sta, link) (sta)->plink = link +#else +#define STA_SET_MESH_PLINK(sta, link) do {} while (0) +#endif + +#define sta_tx_pkts(sta) \ + (sta->sta_stats.tx_pkts) + +#define sta_last_tx_pkts(sta) \ + (sta->sta_stats.last_tx_pkts) + #define sta_rx_pkts(sta) \ (sta->sta_stats.rx_mgnt_pkts \ + sta->sta_stats.rx_ctrl_pkts \ @@ -483,15 +518,15 @@ struct sta_info { + sta->sta_stats.last_rx_ctrl_pkts \ + sta->sta_stats.last_rx_data_pkts) -#define sta_rx_data_pkts(sta) \ - (sta->sta_stats.rx_data_pkts) +#define sta_rx_data_pkts(sta) (sta->sta_stats.rx_data_pkts) +#define sta_last_rx_data_pkts(sta) (sta->sta_stats.last_rx_data_pkts) + +#define sta_rx_data_uc_pkts(sta) (sta->sta_stats.rx_data_pkts - sta->sta_stats.rx_data_bc_pkts - sta->sta_stats.rx_data_mc_pkts) +#define sta_last_rx_data_uc_pkts(sta) (sta->sta_stats.last_rx_data_pkts - sta->sta_stats.last_rx_data_bc_pkts - sta->sta_stats.last_rx_data_mc_pkts) #define sta_rx_data_qos_pkts(sta, i) \ (sta->sta_stats.rx_data_qos_pkts[i]) -#define sta_last_rx_data_pkts(sta) \ - (sta->sta_stats.last_rx_data_pkts) - #define sta_last_rx_data_qos_pkts(sta, i) \ (sta->sta_stats.last_rx_data_qos_pkts[i]) @@ -531,8 +566,19 @@ struct sta_info { #define sta_last_rx_probersp_uo_pkts(sta) \ (sta->sta_stats.last_rx_probersp_uo_pkts) +#ifdef CONFIG_RTW_MESH +#define update_last_rx_hwmp_pkts(sta) \ + do { \ + sta->sta_stats.last_rx_hwmp_pkts = sta->sta_stats.rx_hwmp_pkts; \ + } while(0) +#else +#define update_last_rx_hwmp_pkts(sta) do {} while(0) +#endif + #define sta_update_last_rx_pkts(sta) \ do { \ + int __i; \ + \ sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \ sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \ sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \ @@ -540,7 +586,13 @@ struct sta_info { sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \ sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \ sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \ + update_last_rx_hwmp_pkts(sta); \ + \ sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \ + sta->sta_stats.last_rx_data_bc_pkts = sta->sta_stats.rx_data_bc_pkts; \ + sta->sta_stats.last_rx_data_mc_pkts = sta->sta_stats.rx_data_mc_pkts; \ + for (__i = 0; __i < TID_NUM; __i++) \ + sta->sta_stats.last_rx_data_qos_pkts[__i] = sta->sta_stats.rx_data_qos_pkts[__i]; \ } while (0) #define STA_RX_PKTS_ARG(sta) \ @@ -560,6 +612,9 @@ struct sta_info { #define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)" +#define sta_rx_uc_bytes(sta) (sta->sta_stats.rx_bytes - sta->sta_stats.rx_bc_bytes - sta->sta_stats.rx_mc_bytes) +#define sta_last_rx_uc_bytes(sta) (sta->sta_stats.last_rx_bytes - sta->sta_stats.last_rx_bc_bytes - sta->sta_stats.last_rx_mc_bytes) + #ifdef CONFIG_WFD #define STA_OP_WFD_MODE(sta) (sta)->op_wfd_mode #define STA_SET_OP_WFD_MODE(sta, mode) (sta)->op_wfd_mode = (mode) @@ -568,6 +623,8 @@ struct sta_info { #define STA_SET_OP_WFD_MODE(sta, mode) do {} while (0) #endif +#define AID_BMP_LEN(max_aid) ((max_aid + 1) / 8 + (((max_aid + 1) % 8) ? 1 : 0)) + struct sta_priv { u8 *pallocated_stainfo_buf; @@ -596,19 +653,22 @@ struct sta_priv { unsigned int assoc_to; /* sec, time to expire before associating. */ unsigned int expire_to; /* sec , time to expire after associated. */ - /* pointers to STA info; based on allocated AID or NULL if AID free - * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 - * and so on - */ - struct sta_info *sta_aid[NUM_STA]; - - u16 sta_dz_bitmap;/* only support 15 stations, staion aid bitmap for sleeping sta. */ - u16 tim_bitmap;/* only support 15 stations, aid=0~15 mapping bit0~bit15 */ + /* + * pointers to STA info; based on allocated AID or NULL if AID free + * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 + */ + struct sta_info **sta_aid; + u16 max_aid; + u16 started_aid; /* started AID for allocation search */ + bool rr_aid; /* round robin AID allocation, will modify started_aid */ + u8 aid_bmp_len; /* in byte */ + u8 *sta_dz_bitmap; + u8 *tim_bitmap; u16 max_num_sta; #if CONFIG_RTW_MACADDR_ACL - struct wlan_acl_pool acl_list; + struct wlan_acl_pool acl_list[RTW_ACL_PERIOD_NUM]; #endif #if CONFIG_RTW_PRE_LINK_STA @@ -620,12 +680,13 @@ struct sta_priv { #ifdef CONFIG_ATMEL_RC_PATCH u8 atmel_rc_pattern[6]; #endif - struct sta_info *c2h_sta; + u8 c2h_sta_mac[ETH_ALEN]; + u8 c2h_adapter_id; struct submit_ctx *gotc2h; }; -__inline static u32 wifi_mac_hash(u8 *mac) +__inline static u32 wifi_mac_hash(const u8 *mac) { u32 x; @@ -650,15 +711,20 @@ extern u32 _rtw_free_sta_priv(struct sta_priv *pstapriv); int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta); struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset); -extern struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); +extern struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr); extern u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta); extern void rtw_free_all_stainfo(_adapter *padapter); -extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); +extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr); extern u32 rtw_init_bcmc_stainfo(_adapter *padapter); extern struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter); +#ifdef CONFIG_AP_MODE +u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta); +void dump_aid_status(void *sel, _adapter *adapter); +#endif + #if CONFIG_RTW_MACADDR_ACL -extern u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr); +extern u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr); void dump_macaddr_acl(void *sel, _adapter *adapter); #endif diff --git a/include/usb_hal.h b/include/usb_hal.h index 7e556e4..0074d3f 100644 --- a/include/usb_hal.h +++ b/include/usb_hal.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __USB_HAL_H__ #define __USB_HAL_H__ @@ -53,6 +48,10 @@ void rtl8814au_set_hal_ops(_adapter *padapter); void rtl8188fu_set_hal_ops(_adapter *padapter); #endif +#ifdef CONFIG_RTL8188GTV +void rtl8188gtvu_set_hal_ops(_adapter *padapter); +#endif + #ifdef CONFIG_RTL8703B void rtl8703bu_set_hal_ops(_adapter *padapter); #endif @@ -61,6 +60,14 @@ void rtl8703bu_set_hal_ops(_adapter *padapter); void rtl8723du_set_hal_ops(_adapter *padapter); #endif +#ifdef CONFIG_RTL8710B +void rtl8710bu_set_hal_ops(_adapter *padapter); +#endif + +#ifdef CONFIG_RTL8192F +void rtl8192fu_set_hal_ops(_adapter *padapter); +#endif /* CONFIG_RTL8192F */ + #ifdef CONFIG_INTEL_PROXIM extern _adapter *rtw_usb_get_sw_pointer(void); #endif /* CONFIG_INTEL_PROXIM */ diff --git a/include/usb_ops.h b/include/usb_ops.h index 350a675..6d5435d 100644 --- a/include/usb_ops.h +++ b/include/usb_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __USB_OPS_H_ #define __USB_OPS_H_ @@ -75,6 +70,13 @@ void interrupt_handler_8188fu(_adapter *padapter, u16 pkt_len, u8 *pbuf); #endif #endif +#ifdef CONFIG_RTL8188GTV +void rtl8188gtvu_set_hw_type(struct dvobj_priv *pdvobj); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8188gtvu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif +#endif + #ifdef CONFIG_RTL8723B void rtl8723bu_set_hw_type(struct dvobj_priv *pdvobj); #ifdef CONFIG_SUPPORT_USB_INT @@ -101,6 +103,24 @@ void interrupt_handler_8723du(_adapter *padapter, u16 pkt_len, u8 *pbuf); #endif /* CONFIG_SUPPORT_USB_INT */ #endif /* CONFIG_RTL8723D */ +#ifdef CONFIG_RTL8710B +void rtl8710bu_set_hw_type(struct dvobj_priv *pdvobj); +void rtl8710bu_set_intf_ops(struct _io_ops *pops); +void rtl8710bu_recv_tasklet(void *priv); +void rtl8710bu_xmit_tasklet(void *priv); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8710bu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif /* CONFIG_SUPPORT_USB_INT */ +#endif /* CONFIG_RTL8710B */ + +#ifdef CONFIG_RTL8192F +void rtl8192fu_set_hw_type(struct dvobj_priv *pdvobj); +void rtl8192fu_xmit_tasklet(void *priv); +#ifdef CONFIG_SUPPORT_USB_INT +void rtl8192fu_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif /* CONFIG_SUPPORT_USB_INT */ +#endif /* CONFIG_RTL8192F */ + enum RTW_USB_SPEED { RTW_USB_SPEED_UNKNOWN = 0, RTW_USB_SPEED_1_1 = 1, @@ -122,7 +142,7 @@ static inline u8 rtw_usb_bulk_size_boundary(_adapter *padapter, int buf_len) if (IS_SUPER_SPEED_USB(padapter)) rst = (0 == (buf_len) % USB_SUPER_SPEED_BULK_SIZE) ? _TRUE : _FALSE; - if (IS_HIGH_SPEED_USB(padapter)) + else if (IS_HIGH_SPEED_USB(padapter)) rst = (0 == (buf_len) % USB_HIGH_SPEED_BULK_SIZE) ? _TRUE : _FALSE; else rst = (0 == (buf_len) % USB_FULL_SPEED_BULK_SIZE) ? _TRUE : _FALSE; diff --git a/include/usb_ops_linux.h b/include/usb_ops_linux.h index adf0750..bf59ca0 100644 --- a/include/usb_ops_linux.h +++ b/include/usb_ops_linux.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __USB_OPS_LINUX_H__ #define __USB_OPS_LINUX_H__ diff --git a/include/usb_osintf.h b/include/usb_osintf.h index 9c39520..7e5feed 100644 --- a/include/usb_osintf.h +++ b/include/usb_osintf.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __USB_OSINTF_H #define __USB_OSINTF_H diff --git a/include/usb_vendor_req.h b/include/usb_vendor_req.h index 2281d36..a003bfb 100644 --- a/include/usb_vendor_req.h +++ b/include/usb_vendor_req.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _USB_VENDOR_REQUEST_H_ #define _USB_VENDOR_REQUEST_H_ diff --git a/include/wifi.h b/include/wifi.h index 94338bf..f216423 100644 --- a/include/wifi.h +++ b/include/wifi.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,21 +11,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _WIFI_H_ #define _WIFI_H_ -#ifdef BIT -/* #error "BIT define occurred earlier elsewhere!\n" */ -#undef BIT -#endif +#ifndef BIT #define BIT(x) (1 << (x)) +#endif #define WLAN_ETHHDR_LEN 14 @@ -49,6 +42,7 @@ #define WLAN_MAX_ETHFRM_LEN 1514 #define WLAN_ETHHDR_LEN 14 #define WLAN_WMM_LEN 24 +#define VENDOR_NAME_LEN 20 #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE #define WLAN_MAX_VENDOR_IE_LEN 255 @@ -97,6 +91,7 @@ enum WIFI_FRAME_SUBTYPE { /* below is for control frame */ WIFI_BF_REPORT_POLL = (BIT(6) | WIFI_CTRL_TYPE), WIFI_NDPA = (BIT(6) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_BAR = (BIT(7) | WIFI_CTRL_TYPE), WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), @@ -405,31 +400,26 @@ enum WIFI_REG_DOMAIN { } while (0) -#define SetPriority(pbuf, tid) \ - do { \ - *(unsigned short *)(pbuf) |= cpu_to_le16(tid & 0xf); \ - } while (0) - -#define GetPriority(pbuf) ((le16_to_cpu(*(unsigned short *)(pbuf))) & 0xf) - -#define SetEOSP(pbuf, eosp) \ - do { \ - *(unsigned short *)(pbuf) |= cpu_to_le16((eosp & 1) << 4); \ - } while (0) +/* QoS control field */ +#define SetPriority(qc, tid) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 0, 4, tid) +#define SetEOSP(qc, eosp) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 4, 1, eosp) +#define SetAckpolicy(qc, ack) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 5, 2, ack) +#define SetAMsdu(qc, amsdu) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 7, 1, amsdu) -#define SetAckpolicy(pbuf, ack) \ - do { \ - *(unsigned short *)(pbuf) |= cpu_to_le16((ack & 3) << 5); \ - } while (0) +#define GetPriority(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 0, 4) +#define GetEOSP(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 4, 1) +#define GetAckpolicy(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 5, 2) +#define GetAMsdu(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 7, 1) -#define GetAckpolicy(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 5) & 0x3) +/* QoS control field (MSTA only) */ +#define set_mctrl_present(qc, p) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 8, 1, p) +#define set_mps_lv(qc, lv) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 9, 1, lv) +#define set_rspi(qc, rspi) SET_BITS_TO_LE_2BYTE(((u8 *)(qc)), 10, 1, rspi) -#define GetAMsdu(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 7) & 0x1) +#define get_mctrl_present(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 8, 1) +#define get_mps_lv(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 9, 1) +#define get_rspi(qc) LE_BITS_TO_2BYTE(((u8 *)(qc)), 10, 1) -#define SetAMsdu(pbuf, amsdu) \ - do { \ - *(unsigned short *)(pbuf) |= cpu_to_le16((amsdu & 1) << 7); \ - } while (0) #define GetAid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff) @@ -451,7 +441,7 @@ enum WIFI_REG_DOMAIN { (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \ ) -__inline static int IS_MCAST(unsigned char *da) +__inline static int IS_MCAST(const u8 *da) { if ((*da) & 0x01) return _TRUE; @@ -472,6 +462,7 @@ __inline static unsigned char *get_ta(unsigned char *pframe) return ta; } +/* can't apply to mesh mode */ __inline static unsigned char *get_da(unsigned char *pframe) { unsigned char *da; @@ -495,7 +486,7 @@ __inline static unsigned char *get_da(unsigned char *pframe) return da; } - +/* can't apply to mesh mode */ __inline static unsigned char *get_sa(unsigned char *pframe) { unsigned char *sa; @@ -519,6 +510,7 @@ __inline static unsigned char *get_sa(unsigned char *pframe) return sa; } +/* can't apply to mesh mode */ __inline static unsigned char *get_hdr_bssid(unsigned char *pframe) { unsigned char *sa = NULL; @@ -550,6 +542,22 @@ __inline static int IsFrameTypeCtrl(unsigned char *pframe) else return _FALSE; } +static inline int IsFrameTypeMgnt(unsigned char *pframe) +{ + if (GetFrameType(pframe) == WIFI_MGT_TYPE) + return _TRUE; + else + return _FALSE; +} +static inline int IsFrameTypeData(unsigned char *pframe) +{ + if (GetFrameType(pframe) == WIFI_DATA_TYPE) + return _TRUE; + else + return _FALSE; +} + + /*----------------------------------------------------------------------------- Below is for the security related definition ------------------------------------------------------------------------------*/ @@ -587,19 +595,22 @@ __inline static int IsFrameTypeCtrl(unsigned char *pframe) #define _CHLGETXT_IE_ 16 #define _SUPPORTED_CH_IE_ 36 #define _CH_SWTICH_ANNOUNCE_ 37 /* Secondary Channel Offset */ +#define _MEAS_REQ_IE_ 38 +#define _MEAS_RSP_IE_ 39 #define _RSN_IE_2_ 48 #define _SSN_IE_1_ 221 #define _ERPINFO_IE_ 42 #define _EXT_SUPPORTEDRATES_IE_ 50 #define _HT_CAPABILITY_IE_ 45 -#define _MDIE_ 54 -#define _FTIE_ 55 +#define _MDIE_ 54 +#define _FTIE_ 55 #define _TIMEOUT_ITVL_IE_ 56 #define _SRC_IE_ 59 #define _HT_EXTRA_INFO_IE_ 61 #define _HT_ADD_INFO_IE_ 61 /* _HT_EXTRA_INFO_IE_ */ -#define _WAPI_IE_ 68 +#define _WAPI_IE_ 68 +#define _EID_RRM_EN_CAP_IE_ 70 /* #define EID_BSSCoexistence 72 */ /* 20/40 BSS Coexistence @@ -742,9 +753,8 @@ typedef enum _ELEMENT_ID { #define _WEP_WPA_MIXED_PRIVACY_ 6 /* WEP + WPA */ #endif -#ifdef CONFIG_IEEE80211W #define _MME_IE_LENGTH_ 18 -#endif /* CONFIG_IEEE80211W */ + /*----------------------------------------------------------------------------- Below is the definition for WMM ------------------------------------------------------------------------------*/ @@ -817,6 +827,7 @@ struct rtw_ieee80211_ht_cap { * This structure refers to "HT information element" as * described in 802.11n draft section 7.3.2.53 */ +#ifndef CONFIG_IEEE80211_HT_ADDT_INFO struct ieee80211_ht_addt_info { unsigned char control_chan; unsigned char ht_param; @@ -824,7 +835,7 @@ struct ieee80211_ht_addt_info { unsigned short stbc_param; unsigned char basic_set[16]; } __attribute__((packed)); - +#endif struct HT_caps_element { union { @@ -1361,10 +1372,8 @@ enum P2P_PS_MODE { #define WFD_DEVINFO_PC_TDLS 0x0080 #define WFD_DEVINFO_HDCP_SUPPORT 0x0100 -#ifdef CONFIG_TX_MCAST2UNI #define IP_MCAST_MAC(mac) ((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e)) #define ICMPV6_MCAST_MAC(mac) ((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff)) -#endif /* CONFIG_TX_MCAST2UNI */ #ifdef CONFIG_IOCTL_CFG80211 /* Regulatroy Domain */ diff --git a/include/wlan_bssdef.h b/include/wlan_bssdef.h index dd39e0c..b3296d5 100644 --- a/include/wlan_bssdef.h +++ b/include/wlan_bssdef.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __WLAN_BSSDEF_H__ #define __WLAN_BSSDEF_H__ @@ -30,7 +25,7 @@ #define NDIS_802_11_LENGTH_RATES 8 #define NDIS_802_11_LENGTH_RATES_EX 16 -typedef unsigned char NDIS_802_11_MAC_ADDRESS[6]; +typedef unsigned char NDIS_802_11_MAC_ADDRESS[ETH_ALEN]; typedef long NDIS_802_11_RSSI; /* in dBm */ typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; /* Set of 8 data rates */ typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; /* Set of 16 data rates */ @@ -82,6 +77,7 @@ typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE { Ndis802_11InfrastructureMax, /* Not a real value, defined as upper bound */ Ndis802_11APMode, Ndis802_11Monitor, + Ndis802_11_mesh, } NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE; @@ -279,7 +275,7 @@ typedef struct _NDIS_802_11_TEST { #define NDIS_802_11_LENGTH_RATES 8 #define NDIS_802_11_LENGTH_RATES_EX 16 -typedef unsigned char NDIS_802_11_MAC_ADDRESS[6]; +typedef unsigned char NDIS_802_11_MAC_ADDRESS[ETH_ALEN]; typedef long NDIS_802_11_RSSI; /* in dBm */ typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; /* Set of 8 data rates */ typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; /* Set of 16 data rates */ @@ -526,7 +522,12 @@ typedef struct _WLAN_PHY_INFO { u8 SignalStrength;/* (in percentage) */ u8 SignalQuality;/* (in percentage) */ u8 Optimum_antenna; /* for Antenna diversity */ - u8 Reserved_0; + u8 is_cck_rate; /* 1:cck_rate */ + s8 rx_snr[4]; +#ifdef CONFIG_RTW_80211K + u32 free_cnt; /* freerun counter */ + u8 rm_en_cap[5]; +#endif } WLAN_PHY_INFO, *PWLAN_PHY_INFO; typedef struct _WLAN_BCN_INFO { @@ -542,6 +543,13 @@ typedef struct _WLAN_BCN_INFO { unsigned char ht_info_infos_0; } WLAN_BCN_INFO, *PWLAN_BCN_INFO; +enum bss_type { + BSS_TYPE_UNDEF, + BSS_TYPE_BCN = 1, + BSS_TYPE_PROB_REQ = 2, + BSS_TYPE_PROB_RSP = 3, +}; + /* temporally add #pragma pack for structure alignment issue of * WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz() */ @@ -552,8 +560,9 @@ typedef struct _WLAN_BCN_INFO { typedef struct _WLAN_BSSID_EX { ULONG Length; NDIS_802_11_MAC_ADDRESS MacAddress; - UCHAR Reserved[2];/* [0]: IS beacon frame */ + UCHAR Reserved[2];/* [0]: IS beacon frame , bss_type*/ NDIS_802_11_SSID Ssid; + NDIS_802_11_SSID mesh_id; ULONG Privacy; NDIS_802_11_RSSI Rssi;/* (in dBM,raw data ,get from PHY) */ NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; @@ -574,7 +583,7 @@ WLAN_BSSID_EX, *PWLAN_BSSID_EX; #define BSS_EX_IES(bss_ex) ((bss_ex)->IEs) #define BSS_EX_IES_LEN(bss_ex) ((bss_ex)->IELength) -#define BSS_EX_FIXED_IE_OFFSET(bss_ex) ((bss_ex)->Reserved[0] == 2 ? 0 : 12) +#define BSS_EX_FIXED_IE_OFFSET(bss_ex) ((bss_ex)->Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12) #define BSS_EX_TLV_IES(bss_ex) (BSS_EX_IES((bss_ex)) + BSS_EX_FIXED_IE_OFFSET((bss_ex))) #define BSS_EX_TLV_IES_LEN(bss_ex) (BSS_EX_IES_LEN((bss_ex)) - BSS_EX_FIXED_IE_OFFSET((bss_ex))) @@ -608,7 +617,13 @@ struct wlan_network { _list list; int network_type; /* refer to ieee80211.h for WIRELESS_11A/B/G */ int fixed; /* set to fixed when not to be removed as site-surveying */ - unsigned long last_scanned; /* timestamp for the network */ + systime last_scanned; /* timestamp for the network */ +#ifdef CONFIG_RTW_MESH +#if CONFIG_RTW_MESH_ACNODE_PREVENT + systime acnode_stime; + systime acnode_notify_etime; +#endif +#endif int aid; /* will only be valid when a BSS is joinned. */ int join_res; WLAN_BSSID_EX network; /* must be the last item */ diff --git a/include/xmit_osdep.h b/include/xmit_osdep.h index ea5725d..70070a8 100644 --- a/include/xmit_osdep.h +++ b/include/xmit_osdep.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __XMIT_OSDEP_H_ #define __XMIT_OSDEP_H_ diff --git a/os_dep/linux/custom_gpio_linux.c b/os_dep/linux/custom_gpio_linux.c index 4f10bbe..23401b7 100644 --- a/os_dep/linux/custom_gpio_linux.c +++ b/os_dep/linux/custom_gpio_linux.c @@ -1,7 +1,6 @@ /****************************************************************************** - * Customer code to add GPIO control during WLAN start/stop * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -12,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include "drv_types.h" #ifdef CONFIG_PLATFORM_SPRD diff --git a/os_dep/linux/ioctl_cfg80211.c b/os_dep/linux/ioctl_cfg80211.c index c96b1a3..b7740e0 100644 --- a/os_dep/linux/ioctl_cfg80211.c +++ b/os_dep/linux/ioctl_cfg80211.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _IOCTL_CFG80211_C_ #include @@ -24,11 +19,27 @@ #ifdef CONFIG_IOCTL_CFG80211 +#ifndef DBG_RTW_CFG80211_STA_PARAM +#define DBG_RTW_CFG80211_STA_PARAM 0 +#endif + +#ifndef DBG_RTW_CFG80211_MESH_CONF +#define DBG_RTW_CFG80211_MESH_CONF 0 +#endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) -#define STATION_INFO_SIGNAL BIT(NL80211_STA_INFO_SIGNAL) +#define STATION_INFO_INACTIVE_TIME BIT(NL80211_STA_INFO_INACTIVE_TIME) +#define STATION_INFO_LLID BIT(NL80211_STA_INFO_LLID) +#define STATION_INFO_PLID BIT(NL80211_STA_INFO_PLID) +#define STATION_INFO_PLINK_STATE BIT(NL80211_STA_INFO_PLINK_STATE) +#define STATION_INFO_SIGNAL BIT(NL80211_STA_INFO_SIGNAL) #define STATION_INFO_TX_BITRATE BIT(NL80211_STA_INFO_TX_BITRATE) #define STATION_INFO_RX_PACKETS BIT(NL80211_STA_INFO_RX_PACKETS) #define STATION_INFO_TX_PACKETS BIT(NL80211_STA_INFO_TX_PACKETS) +#define STATION_INFO_TX_FAILED BIT(NL80211_STA_INFO_TX_FAILED) +#define STATION_INFO_LOCAL_PM BIT(NL80211_STA_INFO_LOCAL_PM) +#define STATION_INFO_PEER_PM BIT(NL80211_STA_INFO_PEER_PM) +#define STATION_INFO_NONPEER_PM BIT(NL80211_STA_INFO_NONPEER_PM) #define STATION_INFO_ASSOC_REQ_IES 0 #endif /* Linux kernel >= 4.0.0 */ @@ -68,6 +79,15 @@ #define WLAN_AKM_SUITE_FT_PSK 0x000FAC04 #endif +/* + * In the current design of Wi-Fi driver, it will return success to the system (e.g. supplicant) + * when Wi-Fi driver decides to abort the scan request in the scan flow by default. + * Defining this flag makes Wi-Fi driver to return -EBUSY to the system if Wi-Fi driver is too busy to do the scan. + */ +#ifndef CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY + #define CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY 0 +#endif + static const u32 rtw_cipher_suites[] = { WLAN_CIPHER_SUITE_WEP40, WLAN_CIPHER_SUITE_WEP104, @@ -175,6 +195,247 @@ static struct ieee80211_channel rtw_5ghz_a_channels[MAX_CHANNEL_NUM_5G] = { CHAN5G(165, 0), CHAN5G(169, 0), CHAN5G(173, 0), CHAN5G(177, 0), }; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) +static const char *nl80211_channel_type_str(enum nl80211_channel_type ctype) +{ + switch (ctype) { + case NL80211_CHAN_NO_HT: + return "NO_HT"; + case NL80211_CHAN_HT20: + return "HT20"; + case NL80211_CHAN_HT40MINUS: + return "HT40-"; + case NL80211_CHAN_HT40PLUS: + return "HT40+"; + default: + return "INVALID"; + }; +} + +static enum nl80211_channel_type rtw_chbw_to_nl80211_channel_type(u8 ch, u8 bw, u8 offset, u8 ht) +{ + rtw_warn_on(!ht && (bw >= CHANNEL_WIDTH_40 || offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE)); + + if (!ht) + return NL80211_CHAN_NO_HT; + if (bw >= CHANNEL_WIDTH_40) { + if (offset == HAL_PRIME_CHNL_OFFSET_UPPER) + return NL80211_CHAN_HT40MINUS; + else if (offset == HAL_PRIME_CHNL_OFFSET_LOWER) + return NL80211_CHAN_HT40PLUS; + else + rtw_warn_on(1); + } + return NL80211_CHAN_HT20; +} + +static void rtw_get_chbw_from_nl80211_channel_type(struct ieee80211_channel *chan, enum nl80211_channel_type ctype, u8 *ht, u8 *ch, u8 *bw, u8 *offset) +{ + int pri_freq; + + pri_freq = rtw_ch2freq(chan->hw_value); + if (!pri_freq) { + RTW_INFO("invalid channel:%d\n", chan->hw_value); + rtw_warn_on(1); + *ch = 0; + return; + } + *ch = chan->hw_value; + + switch (ctype) { + case NL80211_CHAN_NO_HT: + *ht = 0; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + case NL80211_CHAN_HT20: + *ht = 1; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + case NL80211_CHAN_HT40MINUS: + *ht = 1; + *bw = CHANNEL_WIDTH_40; + *offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + case NL80211_CHAN_HT40PLUS: + *ht = 1; + *bw = CHANNEL_WIDTH_40; + *offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + default: + *ht = 0; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + RTW_INFO("unsupported ctype:%s\n", nl80211_channel_type_str(ctype)); + rtw_warn_on(1); + }; +} +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) */ + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) +static const char *nl80211_chan_width_str(enum nl80211_chan_width cwidth) +{ + switch (cwidth) { + case NL80211_CHAN_WIDTH_20_NOHT: + return "20_NOHT"; + case NL80211_CHAN_WIDTH_20: + return "20"; + case NL80211_CHAN_WIDTH_40: + return "40"; + case NL80211_CHAN_WIDTH_80: + return "80"; + case NL80211_CHAN_WIDTH_80P80: + return "80+80"; + case NL80211_CHAN_WIDTH_160: + return "160"; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + case NL80211_CHAN_WIDTH_5: + return "5"; + case NL80211_CHAN_WIDTH_10: + return "10"; +#endif + default: + return "INVALID"; + }; +} + +static u8 rtw_chbw_to_cfg80211_chan_def(struct wiphy *wiphy, struct cfg80211_chan_def *chdef, u8 ch, u8 bw, u8 offset, u8 ht) +{ + int freq, cfreq; + struct ieee80211_channel *chan; + u8 ret = _FAIL; + + freq = rtw_ch2freq(ch); + if (!freq) + goto exit; + + cfreq = rtw_get_center_ch(ch, bw, offset); + if (!cfreq) + goto exit; + cfreq = rtw_ch2freq(cfreq); + if (!cfreq) + goto exit; + + chan = ieee80211_get_channel(wiphy, freq); + if (!chan) + goto exit; + + if (bw == CHANNEL_WIDTH_20) + chdef->width = ht ? NL80211_CHAN_WIDTH_20 : NL80211_CHAN_WIDTH_20_NOHT; + else if (bw == CHANNEL_WIDTH_40) + chdef->width = NL80211_CHAN_WIDTH_40; + else if (bw == CHANNEL_WIDTH_80) + chdef->width = NL80211_CHAN_WIDTH_80; + else if (bw == CHANNEL_WIDTH_160) + chdef->width = NL80211_CHAN_WIDTH_160; + else { + rtw_warn_on(1); + goto exit; + } + + chdef->chan = chan; + chdef->center_freq1 = cfreq; + chdef->center_freq2 = 0; + + ret = _SUCCESS; + +exit: + return ret; +} + +static void rtw_get_chbw_from_cfg80211_chan_def(struct cfg80211_chan_def *chdef, u8 *ht, u8 *ch, u8 *bw, u8 *offset) +{ + int pri_freq; + struct ieee80211_channel *chan = chdef->chan; + + pri_freq = rtw_ch2freq(chan->hw_value); + if (!pri_freq) { + RTW_INFO("invalid channel:%d\n", chan->hw_value); + rtw_warn_on(1); + *ch = 0; + return; + } + + switch (chdef->width) { + case NL80211_CHAN_WIDTH_20_NOHT: + *ht = 0; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *ch = chan->hw_value; + break; + case NL80211_CHAN_WIDTH_20: + *ht = 1; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + *ch = chan->hw_value; + break; + case NL80211_CHAN_WIDTH_40: + *ht = 1; + *bw = CHANNEL_WIDTH_40; + *offset = pri_freq > chdef->center_freq1 ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER; + if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset)) + *ch = chan->hw_value; + break; + case NL80211_CHAN_WIDTH_80: + *ht = 1; + *bw = CHANNEL_WIDTH_80; + if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset)) + *ch = chan->hw_value; + break; + case NL80211_CHAN_WIDTH_160: + *ht = 1; + *bw = CHANNEL_WIDTH_160; + if (rtw_get_offset_by_chbw(chan->hw_value, *bw, offset)) + *ch = chan->hw_value; + break; + case NL80211_CHAN_WIDTH_80P80: + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + case NL80211_CHAN_WIDTH_5: + case NL80211_CHAN_WIDTH_10: + #endif + default: + *ht = 0; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + RTW_INFO("unsupported cwidth:%s\n", nl80211_chan_width_str(chdef->width)); + rtw_warn_on(1); + }; +} +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) */ + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) +u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 ht) +{ + struct wiphy *wiphy = adapter_to_wiphy(adapter); + u8 ret = _SUCCESS; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + struct cfg80211_chan_def chdef; + + ret = rtw_chbw_to_cfg80211_chan_def(wiphy, &chdef, ch, bw, offset, ht); + if (ret != _SUCCESS) + goto exit; + + cfg80211_ch_switch_notify(adapter->pnetdev, &chdef); + +#else + int freq = rtw_ch2freq(ch); + enum nl80211_channel_type ctype; + + if (!freq) { + ret = _FAIL; + goto exit; + } + + ctype = rtw_chbw_to_nl80211_channel_type(ch, bw, offset, ht); + cfg80211_ch_switch_notify(adapter->pnetdev, freq, ctype); +#endif + +exit: + return ret; +} +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) */ void rtw_2g_channels_init(struct ieee80211_channel *channels) { @@ -200,17 +461,15 @@ void rtw_5g_rates_init(struct ieee80211_rate *rates) ); } -struct ieee80211_supported_band *rtw_spt_band_alloc( - enum nl80211_band band -) +struct ieee80211_supported_band *rtw_spt_band_alloc(BAND_TYPE band) { struct ieee80211_supported_band *spt_band = NULL; int n_channels, n_bitrates; - if (band == NL80211_BAND_2GHZ) { + if (band == BAND_ON_2_4G) { n_channels = MAX_CHANNEL_NUM_2G; n_bitrates = RTW_G_RATES_NUM; - } else if (band == NL80211_BAND_5GHZ) { + } else if (band == BAND_ON_5G) { n_channels = MAX_CHANNEL_NUM_5G; n_bitrates = RTW_A_RATES_NUM; } else @@ -226,14 +485,14 @@ struct ieee80211_supported_band *rtw_spt_band_alloc( spt_band->channels = (struct ieee80211_channel *)(((u8 *)spt_band) + sizeof(struct ieee80211_supported_band)); spt_band->bitrates = (struct ieee80211_rate *)(((u8 *)spt_band->channels) + sizeof(struct ieee80211_channel) * n_channels); - spt_band->band = band; + spt_band->band = rtw_band_to_nl80211_band(band); spt_band->n_channels = n_channels; spt_band->n_bitrates = n_bitrates; - if (band == NL80211_BAND_2GHZ) { + if (band == BAND_ON_2_4G) { rtw_2g_channels_init(spt_band->channels); rtw_2g_rates_init(spt_band->bitrates); - } else if (band == NL80211_BAND_5GHZ) { + } else if (band == BAND_ON_5G) { rtw_5g_channels_init(spt_band->channels); rtw_5g_rates_init(spt_band->bitrates); } @@ -252,19 +511,11 @@ void rtw_spt_band_free(struct ieee80211_supported_band *spt_band) if (!spt_band) return; -#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) if (spt_band->band == NL80211_BAND_2GHZ) { -#else - if (spt_band->band == IEEE80211_BAND_2GHZ) { -#endif size = sizeof(struct ieee80211_supported_band) + sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_2G + sizeof(struct ieee80211_rate) * RTW_G_RATES_NUM; -#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) } else if (spt_band->band == NL80211_BAND_5GHZ) { -#else - } else if (spt_band->band == IEEE80211_BAND_5GHZ) { -#endif size = sizeof(struct ieee80211_supported_band) + sizeof(struct ieee80211_channel) * MAX_CHANNEL_NUM_5G + sizeof(struct ieee80211_rate) * RTW_A_RATES_NUM; @@ -329,28 +580,118 @@ static const struct ieee80211_txrx_stypes BIT(IEEE80211_STYPE_PROBE_REQ >> 4) }, #endif +#if defined(CONFIG_RTW_MESH) + [NL80211_IFTYPE_MESH_POINT] = { + .tx = 0xffff, + .rx = BIT(IEEE80211_STYPE_ACTION >> 4) + | BIT(IEEE80211_STYPE_AUTH >> 4) + }, +#endif + }; #endif +NDIS_802_11_NETWORK_INFRASTRUCTURE nl80211_iftype_to_rtw_network_type(enum nl80211_iftype type) +{ + switch (type) { + case NL80211_IFTYPE_ADHOC: + return Ndis802_11IBSS; + + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + case NL80211_IFTYPE_P2P_CLIENT: + #endif + case NL80211_IFTYPE_STATION: + return Ndis802_11Infrastructure; + +#ifdef CONFIG_AP_MODE + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + case NL80211_IFTYPE_P2P_GO: + #endif + case NL80211_IFTYPE_AP: + return Ndis802_11APMode; +#endif + +#ifdef CONFIG_RTW_MESH + case NL80211_IFTYPE_MESH_POINT: + return Ndis802_11_mesh; +#endif + + case NL80211_IFTYPE_MONITOR: + return Ndis802_11Monitor; + + default: + return Ndis802_11InfrastructureMax; + } +} + +u32 nl80211_iftype_to_rtw_mlme_state(enum nl80211_iftype type) +{ + switch (type) { + case NL80211_IFTYPE_ADHOC: + return WIFI_ADHOC_STATE; + + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + case NL80211_IFTYPE_P2P_CLIENT: + #endif + case NL80211_IFTYPE_STATION: + return WIFI_STATION_STATE; + +#ifdef CONFIG_AP_MODE + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + case NL80211_IFTYPE_P2P_GO: + #endif + case NL80211_IFTYPE_AP: + return WIFI_AP_STATE; +#endif + +#ifdef CONFIG_RTW_MESH + case NL80211_IFTYPE_MESH_POINT: + return WIFI_MESH_STATE; +#endif + + case NL80211_IFTYPE_MONITOR: + return WIFI_MONITOR_STATE; + + default: + return WIFI_NULL_STATE; + } +} + +static int rtw_cfg80211_sync_iftype(_adapter *adapter) +{ + struct wireless_dev *rtw_wdev = adapter->rtw_wdev; + + if (!(nl80211_iftype_to_rtw_mlme_state(rtw_wdev->iftype) & MLME_STATE(adapter))) { + /* iftype and mlme state is not syc */ + NDIS_802_11_NETWORK_INFRASTRUCTURE network_type; + + network_type = nl80211_iftype_to_rtw_network_type(rtw_wdev->iftype); + if (network_type != Ndis802_11InfrastructureMax) { + if (rtw_pwr_wakeup(adapter) == _FAIL) { + RTW_WARN(FUNC_ADPT_FMT" call rtw_pwr_wakeup fail\n", FUNC_ADPT_ARG(adapter)); + return _FAIL; + } + + rtw_set_802_11_infrastructure_mode(adapter, network_type); + rtw_setopmode_cmd(adapter, network_type, RTW_CMDF_WAIT_ACK); + } else { + rtw_warn_on(1); + RTW_WARN(FUNC_ADPT_FMT" iftype:%u is not support\n", FUNC_ADPT_ARG(adapter), rtw_wdev->iftype); + return _FAIL; + } + } + + return _SUCCESS; +} + static u64 rtw_get_systime_us(void) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39) && LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)) - struct timespec ts; - get_monotonic_boottime(&ts); - return ((u64)ts.tv_sec * 1000000) + ts.tv_nsec / 1000; -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)) return ktime_to_us(ktime_get_boottime()); -#else - struct timeval tv; - do_gettimeofday(&tv); - return ((u64)tv.tv_sec * 1000000) + tv.tv_usec; -#endif } /* Try to remove non target BSS's SR to reduce PBC overlap rate */ static int rtw_cfg80211_clear_wps_sr_of_non_target_bss(_adapter *padapter, struct wlan_network *pnetwork, struct cfg80211_ssid *req_ssid) { - struct rtw_wdev_priv *wdev_data = adapter_wdev_data(padapter); int ret = 0; u8 *psr = NULL, sr = 0; NDIS_802_11_SSID *pssid = &pnetwork->network.Ssid; @@ -473,7 +814,7 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_net SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); /* pmlmeext->mgnt_seq++; */ - if (pnetwork->network.Reserved[0] == 1) { /* WIFI_BEACON */ + if (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); set_frame_sub_type(pbuf, WIFI_BEACON); } else { @@ -515,7 +856,7 @@ struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_net #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 38)) #ifndef COMPAT_KERNEL_RELEASE /* patch for cfg80211, update beacon ies to information_elements */ - if (pnetwork->network.Reserved[0] == 1) { /* WIFI_BEACON */ + if (pnetwork->network.Reserved[0] == BSS_TYPE_BCN) { /* WIFI_BEACON */ if (bss->len_information_elements != bss->len_beacon_ies) { bss->information_elements = bss->beacon_ies; @@ -591,7 +932,6 @@ void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_network *cur_network = &(pmlmepriv->cur_network); struct wireless_dev *pwdev = padapter->rtw_wdev; - struct cfg80211_bss *bss = NULL; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) struct wiphy *wiphy = pwdev->wiphy; int freq = 2412; @@ -600,13 +940,6 @@ void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) - freq = rtw_ch2freq(cur_network->network.Configuration.DSConfig); - - if (0) - RTW_INFO("chan: %d, freq: %d\n", cur_network->network.Configuration.DSConfig, freq); -#endif - if (pwdev->iftype != NL80211_IFTYPE_ADHOC) return; @@ -649,6 +982,9 @@ void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) } /* notify cfg80211 that device joined an IBSS */ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) + freq = rtw_ch2freq(cur_network->network.Configuration.DSConfig); + if (1) + RTW_INFO("chan: %d, freq: %d\n", cur_network->network.Configuration.DSConfig, freq); notify_channel = ieee80211_get_channel(wiphy, freq); cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, notify_channel, GFP_ATOMIC); #else @@ -666,7 +1002,9 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif - struct cfg80211_bss *bss = NULL; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) + struct cfg80211_roam_info roam_info ={}; +#endif RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); if (pwdev->iftype != NL80211_IFTYPE_STATION @@ -676,7 +1014,7 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) ) return; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (!MLME_IS_STA(padapter)) return; #ifdef CONFIG_P2P @@ -730,7 +1068,6 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) struct wiphy *wiphy = pwdev->wiphy; struct ieee80211_channel *notify_channel; - struct cfg80211_roam_info roam_info = {}; u32 freq; u16 channel = cur_network->network.Configuration.DSConfig; @@ -738,8 +1075,7 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) notify_channel = ieee80211_get_channel(wiphy, freq); #endif - RTW_INFO(FUNC_ADPT_FMT" call cfg80211_roamed\n", FUNC_ADPT_ARG(padapter)); - roam_info.channel = notify_channel; + #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) roam_info.bssid = cur_network->network.MacAddress; roam_info.req_ie = pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2; roam_info.req_ie_len = pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2; @@ -747,20 +1083,37 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) roam_info.resp_ie_len = pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6; cfg80211_roamed(padapter->pnetdev, &roam_info, GFP_ATOMIC); + #else + cfg80211_roamed(padapter->pnetdev + #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) + , notify_channel + #endif + , cur_network->network.MacAddress + , pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2 + , pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2 + , pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 + , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 + , GFP_ATOMIC); + #endif /*LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0)*/ + + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_roamed\n", FUNC_ADPT_ARG(padapter)); + #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) - rtw_set_ft_status(padapter, RTW_FT_ASSOCIATED_STA); + if (rtw_ft_roam(padapter)) + rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA); #endif } else { #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state); #endif - rtw_cfg80211_connect_result(pwdev, cur_network->network.MacAddress - , pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2 - , pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2 - , pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 - , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 - , WLAN_STATUS_SUCCESS, GFP_ATOMIC); + + if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) + rtw_cfg80211_connect_result(pwdev, cur_network->network.MacAddress + , pmlmepriv->assoc_req + sizeof(struct rtw_ieee80211_hdr_3addr) + 2 + , pmlmepriv->assoc_req_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 2 + , pmlmepriv->assoc_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6 + , pmlmepriv->assoc_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6 + , WLAN_STATUS_SUCCESS, GFP_ATOMIC); #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state); #endif @@ -773,7 +1126,6 @@ void rtw_cfg80211_indicate_connect(_adapter *padapter) void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated) { - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wireless_dev *pwdev = padapter->rtw_wdev; struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); _irqL irqL; @@ -784,7 +1136,7 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); /*always replace privated definitions with wifi reserved value 0*/ - if ((reason == WLAN_REASON_ACTIVE_ROAM) || (reason == WLAN_REASON_JOIN_WRONG_CHANNEL) || (reason == WLAN_REASON_EXPIRATION_CHK)) + if (WLAN_REASON_IS_PRIVATE(reason)) reason = 0; if (pwdev->iftype != NL80211_IFTYPE_STATION @@ -794,7 +1146,7 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally ) return; - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + if (!MLME_IS_STA(padapter)) return; #ifdef CONFIG_P2P @@ -820,18 +1172,21 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) RTW_INFO("pwdev->sme_state(b)=%d\n", pwdev->sme_state); - if (pwdev->sme_state == CFG80211_SME_CONNECTING) + if (pwdev->sme_state == CFG80211_SME_CONNECTING) { + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter)); rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0, - WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC); - else if (pwdev->sme_state == CFG80211_SME_CONNECTED) + reason, GFP_ATOMIC); + } else if (pwdev->sme_state == CFG80211_SME_CONNECTED) { + RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); + } RTW_INFO("pwdev->sme_state(a)=%d\n", pwdev->sme_state); #else if (pwdev_priv->connect_req) { RTW_INFO(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter)); rtw_cfg80211_connect_result(pwdev, NULL, NULL, 0, NULL, 0, - WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC); + reason, GFP_ATOMIC); } else { RTW_INFO(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); rtw_cfg80211_disconnected(pwdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); @@ -846,13 +1201,13 @@ void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally #ifdef CONFIG_AP_MODE -static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param) { int ret = 0; - u32 wep_key_idx, wep_key_len, wep_total_len; + u32 wep_key_idx, wep_key_len; struct sta_info *psta = NULL, *pbcmc_sta = NULL; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &(padapter->securitypriv); struct sta_priv *pstapriv = &padapter->stapriv; @@ -861,20 +1216,11 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa param->u.crypt.err = 0; param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; - /* sizeof(struct ieee_param) = 64 bytes; */ - /* if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) */ - if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len) { - ret = -EINVAL; - goto exit; - } - - if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + if (is_broadcast_mac_addr(param->sta_addr)) { if (param->u.crypt.idx >= WEP_KEYS -#ifdef CONFIG_IEEE80211W + #ifdef CONFIG_IEEE80211W && param->u.crypt.idx > BIP_MAX_KEYID -#endif /* CONFIG_IEEE80211W */ + #endif ) { ret = -EINVAL; goto exit; @@ -882,8 +1228,9 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } else { psta = rtw_get_stainfo(pstapriv, param->sta_addr); if (!psta) { - /* ret = -EINVAL; */ - RTW_INFO("rtw_set_encryption(), sta has already been removed or never been added\n"); + ret = -EINVAL; + RTW_INFO(FUNC_ADPT_FMT", sta "MAC_FMT" not found\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(param->sta_addr)); goto exit; } } @@ -939,76 +1286,64 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } - - if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) { /* group key */ - if (param->u.crypt.set_tx == 0) { /* group key */ + if (!psta) { /* group key */ + if (param->u.crypt.set_tx == 0) { /* group key, TX only */ if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RTW_INFO("%s, set group_key, WEP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - psecuritypriv->dot118021XGrpPrivacy = _WEP40_; if (param->u.crypt.key_len == 13) psecuritypriv->dot118021XGrpPrivacy = _WEP104_; } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - RTW_INFO("%s, set group_key, TKIP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); psecuritypriv->dot118021XGrpPrivacy = _TKIP_; - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ /* set mic key */ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); - psecuritypriv->busetkipkey = _TRUE; } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - RTW_INFO("%s, set group_key, CCMP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); psecuritypriv->dot118021XGrpPrivacy = _AES_; - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - } -#ifdef CONFIG_IEEE80211W - else if (strcmp(param->u.crypt.alg, "BIP") == 0) { - int no; - RTW_INFO("BIP key_len=%d , index=%d\n", param->u.crypt.key_len, param->u.crypt.idx); - /* save the IGTK key, length 16 bytes */ + #ifdef CONFIG_IEEE80211W + } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set TX IGTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - /* RTW_INFO("IGTK key below:\n"); - for(no=0;no<16;no++) - printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); - RTW_INFO("\n"); */ padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; + psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq); padapter->securitypriv.binstallBIPkey = _TRUE; - RTW_INFO(" ~~~~set sta key:IGKT\n"); goto exit; - } -#endif /* CONFIG_IEEE80211W */ - else { - RTW_INFO("%s, set group_key, none\n", __FUNCTION__); + #endif /* CONFIG_IEEE80211W */ + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx); psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + } else { + RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n" + , FUNC_ADPT_ARG(padapter)); + goto exit; } psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; - - psecuritypriv->binstallGrpkey = _TRUE; - - psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ - - rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); if (pbcmc_sta) { + pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); pbcmc_sta->ieee8021x_blocked = _FALSE; pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ } + psecuritypriv->binstallGrpkey = _TRUE; + psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); } goto exit; @@ -1016,102 +1351,113 @@ static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_pa } if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */ - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - if (param->u.crypt.set_tx == 1) { /* pairwise key */ - _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RTW_INFO("%s, set pairwise key, WEP\n", __FUNCTION__); - - psta->dot118021XPrivacy = _WEP40_; - if (param->u.crypt.key_len == 13) - psta->dot118021XPrivacy = _WEP104_; - } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - RTW_INFO("%s, set pairwise key, TKIP\n", __FUNCTION__); - - psta->dot118021XPrivacy = _TKIP_; - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ - /* set mic key */ - _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); - _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); - - psecuritypriv->busetkipkey = _TRUE; - - } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - - RTW_INFO("%s, set pairwise key, CCMP\n", __FUNCTION__); + if (param->u.crypt.set_tx == 1) { + /* pairwise key */ + _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - psta->dot118021XPrivacy = _AES_; - } else { - RTW_INFO("%s, set pairwise key, none\n", __FUNCTION__); + if (strcmp(param->u.crypt.alg, "WEP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + psta->dot118021XPrivacy = _WEP40_; + if (param->u.crypt.key_len == 13) + psta->dot118021XPrivacy = _WEP104_; - psta->dot118021XPrivacy = _NO_PRIVACY_; - } + } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + psta->dot118021XPrivacy = _TKIP_; + /* set mic key */ + _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); + psecuritypriv->busetkipkey = _TRUE; - rtw_ap_set_pairwise_key(padapter, psta); + } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + psta->dot118021XPrivacy = _AES_; + + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx); + psta->dot118021XPrivacy = _NO_PRIVACY_; + } else { + RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + goto exit; + } - psta->ieee8021x_blocked = _FALSE; + psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->ieee8021x_blocked = _FALSE; + if (psta->dot118021XPrivacy != _NO_PRIVACY_) { psta->bpairwise_key_installed = _TRUE; - } else { /* group key??? */ - if (strcmp(param->u.crypt.alg, "WEP") == 0) { - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - psecuritypriv->dot118021XGrpPrivacy = _WEP40_; - if (param->u.crypt.key_len == 13) - psecuritypriv->dot118021XGrpPrivacy = _WEP104_; - } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - psecuritypriv->dot118021XGrpPrivacy = _TKIP_; - - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ - /* set mic key */ - _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); - _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); - - psecuritypriv->busetkipkey = _TRUE; - - } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - psecuritypriv->dot118021XGrpPrivacy = _AES_; - - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - } else - psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; - - psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; - - psecuritypriv->binstallGrpkey = _TRUE; - - psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ - - rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); - - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); - if (pbcmc_sta) { - pbcmc_sta->ieee8021x_blocked = _FALSE; - pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ - } + /* WPA2 key-handshake has completed */ + if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) + psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE); + } + rtw_ap_set_pairwise_key(padapter, psta); + } else { + /* peer's group key, RX only */ + #ifdef CONFIG_RTW_MESH + if (strcmp(param->u.crypt.alg, "CCMP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set CCMP GTK of "MAC_FMT", idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + psta->group_privacy = _AES_; + _rtw_memcpy(psta->gtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + psta->gtk_bmp |= BIT(param->u.crypt.idx); + psta->gtk_pn.val = RTW_GET_LE64(param->u.crypt.seq); + + #ifdef CONFIG_IEEE80211W + } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set IGTK of "MAC_FMT", idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); + _rtw_memcpy(psta->igtk.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + psta->igtk_bmp |= BIT(param->u.crypt.idx); + psta->igtk_id = param->u.crypt.idx; + psta->igtk_pn.val = RTW_GET_LE64(param->u.crypt.seq); + goto exit; + #endif /* CONFIG_IEEE80211W */ + + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear group key of "MAC_FMT", idx:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx); + psta->group_privacy = _NO_PRIVACY_; + psta->gtk_bmp &= ~BIT(param->u.crypt.idx); + } else + #endif /* CONFIG_RTW_MESH */ + { + RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + goto exit; } + #ifdef CONFIG_RTW_MESH + rtw_ap_set_sta_key(padapter, psta->cmn.mac_addr, psta->group_privacy + , param->u.crypt.key, param->u.crypt.idx, 1); + #endif } } exit: - return ret; - } -#endif +#endif /* CONFIG_AP_MODE */ -static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param) { int ret = 0; - u32 wep_key_idx, wep_key_len, wep_total_len; + u32 wep_key_idx, wep_key_len; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &padapter->securitypriv; @@ -1119,24 +1465,16 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param struct wifidirect_info *pwdinfo = &padapter->wdinfo; #endif /* CONFIG_P2P */ - RTW_INFO("%s\n", __func__); param->u.crypt.err = 0; param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; - if (param_len < (u32)((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) { - ret = -EINVAL; - goto exit; - } - - if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && - param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && - param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + if (is_broadcast_mac_addr(param->sta_addr)) { if (param->u.crypt.idx >= WEP_KEYS -#ifdef CONFIG_IEEE80211W + #ifdef CONFIG_IEEE80211W && param->u.crypt.idx > BIP_MAX_KEYID -#endif /* CONFIG_IEEE80211W */ + #endif ) { ret = -EINVAL; goto exit; @@ -1157,7 +1495,7 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param wep_key_idx = param->u.crypt.idx; wep_key_len = param->u.crypt.key_len; - if ((wep_key_idx > WEP_KEYS) || (wep_key_len <= 0)) { + if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) { ret = -EINVAL; goto exit; } @@ -1196,7 +1534,7 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */ #ifdef CONFIG_RTW_80211R - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_flags(padapter, RTW_FT_SUPPORTED)) + if (rtw_ft_roam(padapter)) psta = rtw_get_stainfo(pstapriv, pmlmepriv->assoc_bssid); else #endif @@ -1209,61 +1547,53 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param if (strcmp(param->u.crypt.alg, "none") != 0) psta->ieee8021x_blocked = _FALSE; - if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) || (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; if (param->u.crypt.set_tx == 1) { /* pairwise key */ - - RTW_INFO("%s, : param->u.crypt.set_tx ==1\n", __func__); - + RTW_INFO(FUNC_ADPT_FMT" set %s PTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */ - /* DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); - padapter->securitypriv.busetkipkey = _FALSE; } + psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq); psta->bpairwise_key_installed = _TRUE; -#ifdef CONFIG_RTW_80211R + #ifdef CONFIG_RTW_80211R psta->ft_pairwise_key_installed = _TRUE; -#endif - /* DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); */ - RTW_INFO(" ~~~~set sta key:unicastkey\n"); - + #endif rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE); + } else { /* group key */ if (strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); padapter->securitypriv.binstallGrpkey = _TRUE; - /* DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */ - RTW_INFO(" ~~~~set sta key:groupkey\n"); - + if (param->u.crypt.idx < 4) + _rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8); padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx; rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE); - } -#ifdef CONFIG_IEEE80211W - else if (strcmp(param->u.crypt.alg, "BIP") == 0) { - int no; - /* RTW_INFO("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx); */ - /* save the IGTK key, length 16 bytes */ + + #ifdef CONFIG_IEEE80211W + } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set IGTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - /*RTW_INFO("IGTK key below:\n"); - for(no=0;no<16;no++) - printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); - RTW_INFO("\n");*/ - padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; - padapter->securitypriv.binstallBIPkey = _TRUE; - RTW_INFO(" ~~~~set sta key:IGKT\n"); + psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx; + psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq); + psecuritypriv->binstallBIPkey = _TRUE; + #endif /* CONFIG_IEEE80211W */ + } -#endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_P2P if (pwdinfo->driver_interface == DRIVER_CFG80211) { @@ -1272,6 +1602,9 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param } #endif /* CONFIG_P2P */ + /* WPA/WPA2 key-handshake has completed */ + clr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE); + } } @@ -1291,64 +1624,10 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param } } -#ifdef CONFIG_WAPI_SUPPORT - if (strcmp(param->u.crypt.alg, "SMS4") == 0) { - PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; - PRT_WAPI_STA_INFO pWapiSta; - u8 WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - - if (param->u.crypt.set_tx == 1) { - list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (_rtw_memcmp(pWapiSta->PeerMacAddr, param->sta_addr, 6)) { - _rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16); - - pWapiSta->wapiUsk.bSet = true; - _rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16); - _rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16); - pWapiSta->wapiUsk.keyId = param->u.crypt.idx ; - pWapiSta->wapiUsk.bTxEnable = true; - - _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16); - pWapiSta->wapiUskUpdate.bTxEnable = false; - pWapiSta->wapiUskUpdate.bSet = false; - - if (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) { - /* set unicast key for ASUE */ - rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false); - } - } - } - } else { - list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (_rtw_memcmp(pWapiSta->PeerMacAddr, get_bssid(pmlmepriv), 6)) { - pWapiSta->wapiMsk.bSet = true; - _rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16); - _rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16); - pWapiSta->wapiMsk.keyId = param->u.crypt.idx ; - pWapiSta->wapiMsk.bTxEnable = false; - if (!pWapiSta->bSetkeyOk) - pWapiSta->bSetkeyOk = true; - pWapiSta->bAuthenticateInProgress = false; - - _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); - - if (psecuritypriv->sw_decrypt == false) { - /* set rx broadcast key for ASUE */ - rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false); - } - } - - } - } - } -#endif - + #ifdef CONFIG_WAPI_SUPPORT + if (strcmp(param->u.crypt.alg, "SMS4") == 0) + rtw_wapi_set_set_encryption(padapter, param); + #endif exit: @@ -1358,13 +1637,12 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param return ret; } -static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, +static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev + , u8 key_index #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - u8 key_index, bool pairwise, const u8 *mac_addr, -#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - u8 key_index, const u8 *mac_addr, -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - struct key_params *params) + , bool pairwise +#endif + , const u8 *mac_addr, struct key_params *params) { char *alg_name; u32 param_len; @@ -1377,17 +1655,21 @@ static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, struct sta_info *ptdls_sta; #endif /* CONFIG_TDLS */ - RTW_INFO(FUNC_NDEV_FMT" adding key for %pM\n", FUNC_NDEV_ARG(ndev), mac_addr); - RTW_INFO("cipher=0x%x\n", params->cipher); - RTW_INFO("key_len=0x%x\n", params->key_len); - RTW_INFO("seq_len=0x%x\n", params->seq_len); - RTW_INFO("key_index=%d\n", key_index); + if (mac_addr) + RTW_INFO(FUNC_NDEV_FMT" adding key for %pM\n", FUNC_NDEV_ARG(ndev), mac_addr); + RTW_INFO(FUNC_NDEV_FMT" cipher=0x%x\n", FUNC_NDEV_ARG(ndev), params->cipher); + RTW_INFO(FUNC_NDEV_FMT" key_len=%d, key_index=%d\n", FUNC_NDEV_ARG(ndev), params->key_len, key_index); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - RTW_INFO("pairwise=%d\n", pairwise); -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ + RTW_INFO(FUNC_NDEV_FMT" pairwise=%d\n", FUNC_NDEV_ARG(ndev), pairwise); +#endif + + if (rtw_cfg80211_sync_iftype(padapter) != _SUCCESS) { + ret = -ENOTSUPP; + goto addkey_end; + } param_len = sizeof(struct ieee_param) + params->key_len; - param = (struct ieee_param *)rtw_malloc(param_len); + param = rtw_malloc(param_len); if (param == NULL) return -1; @@ -1440,18 +1722,23 @@ static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN); - if (!mac_addr || is_broadcast_ether_addr(mac_addr)) { + if (!mac_addr || is_broadcast_ether_addr(mac_addr) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + || !pairwise + #endif + ) { param->u.crypt.set_tx = 0; /* for wpa/wpa2 group key */ } else { param->u.crypt.set_tx = 1; /* for wpa/wpa2 pairwise key */ } - - /* param->u.crypt.idx = key_index - 1; */ param->u.crypt.idx = key_index; - if (params->seq_len && params->seq) + if (params->seq_len && params->seq) { _rtw_memcpy(param->u.crypt.seq, (u8 *)params->seq, params->seq_len); + RTW_INFO(FUNC_NDEV_FMT" seq_len:%u, seq:0x%llx\n", FUNC_NDEV_ARG(ndev) + , params->seq_len, RTW_GET_LE64(param->u.crypt.seq)); + } if (params->key_len && params->key) { param->u.crypt.key_len = params->key_len; @@ -1469,62 +1756,194 @@ static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, } } #endif /* CONFIG_TDLS */ - - ret = rtw_cfg80211_set_encryption(ndev, param, param_len); - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + ret = rtw_cfg80211_set_encryption(ndev, param); + } else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { #ifdef CONFIG_AP_MODE if (mac_addr) _rtw_memcpy(param->sta_addr, (void *)mac_addr, ETH_ALEN); - ret = rtw_cfg80211_ap_set_encryption(ndev, param, param_len); + ret = rtw_cfg80211_ap_set_encryption(ndev, param); #endif } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE ) { /* RTW_INFO("@@@@@@@@@@ fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); */ - ret = rtw_cfg80211_set_encryption(ndev, param, param_len); + ret = rtw_cfg80211_set_encryption(ndev, param); } else RTW_INFO("error! fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); addkey_end: if (param) - rtw_mfree((u8 *)param, param_len); + rtw_mfree(param, param_len); return ret; } -static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev, +static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev + , u8 keyid #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) - u8 key_index, bool pairwise, const u8 *mac_addr, -#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - u8 key_index, const u8 *mac_addr, -#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) */ - void *cookie, - void (*callback)(void *cookie, struct key_params *)) + , bool pairwise +#endif + , const u8 *mac_addr, void *cookie + , void (*callback)(void *cookie, struct key_params *)) { -#if 0 - struct iwm_priv *iwm = ndev_to_iwm(ndev); - struct iwm_key *key = &iwm->keys[key_index]; +#define GET_KEY_PARAM_FMT_S " keyid=%d" +#define GET_KEY_PARAM_ARG_S , keyid +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + #define GET_KEY_PARAM_FMT_2_6_37 ", pairwise=%d" + #define GET_KEY_PARAM_ARG_2_6_37 , pairwise +#else + #define GET_KEY_PARAM_FMT_2_6_37 "" + #define GET_KEY_PARAM_ARG_2_6_37 +#endif +#define GET_KEY_PARAM_FMT_E ", addr=%pM" +#define GET_KEY_PARAM_ARG_E , mac_addr + + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + struct security_priv *sec = &adapter->securitypriv; + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta = NULL; + u32 cipher = _NO_PRIVACY_; + union Keytype *key = NULL; + u8 key_len = 0; + u64 *pn = NULL; + u8 pn_len = 0; + u8 pn_val[8] = {0}; + struct key_params params; + int ret = -ENOENT; + + if (keyid >= WEP_KEYS + #ifdef CONFIG_IEEE80211W + && keyid > BIP_MAX_KEYID + #endif + ) + goto exit; + + if (!mac_addr || is_broadcast_ether_addr(mac_addr) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + || (MLME_IS_STA(adapter) && !pairwise) + #endif + ) { + /* WEP key, TX GTK/IGTK, RX GTK/IGTK(for STA mode) */ + if (is_wep_enc(sec->dot118021XGrpPrivacy)) { + if (keyid >= WEP_KEYS) + goto exit; + if (!(sec->key_mask & BIT(keyid))) + goto exit; + cipher = sec->dot118021XGrpPrivacy; + key = &sec->dot11DefKey[keyid]; + } else { + if (keyid < WEP_KEYS) { + if (sec->binstallGrpkey != _TRUE) + goto exit; + cipher = sec->dot118021XGrpPrivacy; + key = &sec->dot118021XGrpKey[keyid]; + sta = rtw_get_bcmc_stainfo(adapter); + if (sta) + pn = &sta->dot11txpn.val; + #ifdef CONFIG_IEEE80211W + } else if (keyid < BIP_MAX_KEYID) { + if (SEC_IS_BIP_KEY_INSTALLED(sec) != _TRUE) + goto exit; + cipher = _BIP_; + key = &sec->dot11wBIPKey[keyid]; + pn = &sec->dot11wBIPtxpn.val; + #endif + } + } + } else { + /* Pairwise key, RX GTK/IGTK for specific peer */ + sta = rtw_get_stainfo(stapriv, mac_addr); + if (!sta) + goto exit; + + if (keyid < WEP_KEYS && pairwise) { + if (sta->bpairwise_key_installed != _TRUE) + goto exit; + cipher = sta->dot118021XPrivacy; + key = &sta->dot118021x_UncstKey; + #ifdef CONFIG_RTW_MESH + } else if (keyid < WEP_KEYS && !pairwise) { + if (!(sta->gtk_bmp & BIT(keyid))) + goto exit; + cipher = sta->group_privacy; + key = &sta->gtk; + #ifdef CONFIG_IEEE80211W + } else if (keyid < BIP_MAX_KEYID && !pairwise) { + if (!(sta->igtk_bmp & BIT(keyid))) + goto exit; + cipher = _BIP_; + key = &sta->igtk; + pn = &sta->igtk_pn.val; + #endif + #endif /* CONFIG_RTW_MESH */ + } + } + + if (!key) + goto exit; - IWM_DBG_WEXT(iwm, DBG, "Getting key %d\n", key_index); + if (cipher == _WEP40_) { + cipher = WLAN_CIPHER_SUITE_WEP40; + key_len = sec->dot11DefKeylen[keyid]; + } else if (cipher == _WEP104_) { + cipher = WLAN_CIPHER_SUITE_WEP104; + key_len = sec->dot11DefKeylen[keyid]; + } else if (cipher == _TKIP_) { + cipher = WLAN_CIPHER_SUITE_TKIP; + key_len = 16; + } else if (cipher == _AES_) { + cipher = WLAN_CIPHER_SUITE_CCMP; + key_len = 16; + #ifdef CONFIG_IEEE80211W + } else if (cipher == _BIP_) { + cipher = WLAN_CIPHER_SUITE_AES_CMAC; + key_len = 16; + #endif + } else { + RTW_WARN(FUNC_NDEV_FMT" unknown cipher:%u\n", FUNC_NDEV_ARG(ndev), cipher); + rtw_warn_on(1); + goto exit; + } - memset(¶ms, 0, sizeof(params)); + if (pn) { + *((u64 *)pn_val) = cpu_to_le64(*pn); + pn_len = 6; + } - params.cipher = key->cipher; - params.key_len = key->key_len; - params.seq_len = key->seq_len; - params.seq = key->seq; - params.key = key->key; + ret = 0; + +exit: + RTW_INFO(FUNC_NDEV_FMT + GET_KEY_PARAM_FMT_S + GET_KEY_PARAM_FMT_2_6_37 + GET_KEY_PARAM_FMT_E + " ret %d\n", FUNC_NDEV_ARG(ndev) + GET_KEY_PARAM_ARG_S + GET_KEY_PARAM_ARG_2_6_37 + GET_KEY_PARAM_ARG_E + , ret); + if (pn) + RTW_INFO(FUNC_NDEV_FMT " seq:0x%llx\n", FUNC_NDEV_ARG(ndev), *pn); + + if (ret == 0) { + _rtw_memset(¶ms, 0, sizeof(params)); + + params.cipher = cipher; + params.key = key->skey; + params.key_len = key_len; + if (pn) { + params.seq = pn_val; + params.seq_len = pn_len; + } - callback(cookie, ¶ms); + callback(cookie, ¶ms); + } - return key->key_len ? 0 : -ENOENT; -#endif - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); - return 0; + return ret; } static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev, @@ -1537,7 +1956,7 @@ static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev, _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct security_priv *psecuritypriv = &padapter->securitypriv; - RTW_INFO(FUNC_NDEV_FMT" key_index=%d\n", FUNC_NDEV_ARG(ndev), key_index); + RTW_INFO(FUNC_NDEV_FMT" key_index=%d, addr=%pM\n", FUNC_NDEV_ARG(ndev), key_index, mac_addr); if (key_index == psecuritypriv->dot11PrivacyKeyIndex) { /* clear the flag of wep default key set. */ @@ -1593,6 +2012,24 @@ static int cfg80211_rtw_set_default_key(struct wiphy *wiphy, return 0; } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)) +int cfg80211_rtw_set_default_mgmt_key(struct wiphy *wiphy, + struct net_device *ndev, u8 key_index) +{ +#define SET_DEF_KEY_PARAM_FMT " key_index=%d" +#define SET_DEF_KEY_PARAM_ARG , key_index + + RTW_INFO(FUNC_NDEV_FMT + SET_DEF_KEY_PARAM_FMT + "\n", FUNC_NDEV_ARG(ndev) + SET_DEF_KEY_PARAM_ARG + ); + + return 0; +} +#endif + #if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) static int cfg80211_rtw_set_rekey_data(struct wiphy *wiphy, struct net_device *ndev, @@ -1628,6 +2065,101 @@ static int cfg80211_rtw_set_rekey_data(struct wiphy *wiphy, return 0; } #endif /*CONFIG_GTK_OL*/ + +#ifdef CONFIG_RTW_MESH +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) +static enum nl80211_mesh_power_mode rtw_mesh_ps_to_nl80211_mesh_power_mode(u8 ps) +{ + if (ps == RTW_MESH_PS_UNKNOWN) + return NL80211_MESH_POWER_UNKNOWN; + if (ps == RTW_MESH_PS_ACTIVE) + return NL80211_MESH_POWER_ACTIVE; + if (ps == RTW_MESH_PS_LSLEEP) + return NL80211_MESH_POWER_LIGHT_SLEEP; + if (ps == RTW_MESH_PS_DSLEEP) + return NL80211_MESH_POWER_DEEP_SLEEP; + + rtw_warn_on(1); + return NL80211_MESH_POWER_UNKNOWN; +} +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +enum nl80211_plink_state rtw_plink_state_to_nl80211_plink_state(u8 plink_state) +{ + if (plink_state == RTW_MESH_PLINK_UNKNOWN) + return NUM_NL80211_PLINK_STATES; + if (plink_state == RTW_MESH_PLINK_LISTEN) + return NL80211_PLINK_LISTEN; + if (plink_state == RTW_MESH_PLINK_OPN_SNT) + return NL80211_PLINK_OPN_SNT; + if (plink_state == RTW_MESH_PLINK_OPN_RCVD) + return NL80211_PLINK_OPN_RCVD; + if (plink_state == RTW_MESH_PLINK_CNF_RCVD) + return NL80211_PLINK_CNF_RCVD; + if (plink_state == RTW_MESH_PLINK_ESTAB) + return NL80211_PLINK_ESTAB; + if (plink_state == RTW_MESH_PLINK_HOLDING) + return NL80211_PLINK_HOLDING; + if (plink_state == RTW_MESH_PLINK_BLOCKED) + return NL80211_PLINK_BLOCKED; + + rtw_warn_on(1); + return NUM_NL80211_PLINK_STATES; +} + +u8 nl80211_plink_state_to_rtw_plink_state(enum nl80211_plink_state plink_state) +{ + if (plink_state == NL80211_PLINK_LISTEN) + return RTW_MESH_PLINK_LISTEN; + if (plink_state == NL80211_PLINK_OPN_SNT) + return RTW_MESH_PLINK_OPN_SNT; + if (plink_state == NL80211_PLINK_OPN_RCVD) + return RTW_MESH_PLINK_OPN_RCVD; + if (plink_state == NL80211_PLINK_CNF_RCVD) + return RTW_MESH_PLINK_CNF_RCVD; + if (plink_state == NL80211_PLINK_ESTAB) + return RTW_MESH_PLINK_ESTAB; + if (plink_state == NL80211_PLINK_HOLDING) + return RTW_MESH_PLINK_HOLDING; + if (plink_state == NL80211_PLINK_BLOCKED) + return RTW_MESH_PLINK_BLOCKED; + + rtw_warn_on(1); + return RTW_MESH_PLINK_UNKNOWN; +} +#endif + +static void rtw_cfg80211_fill_mesh_only_sta_info(struct mesh_plink_ent *plink, struct sta_info *sta, struct station_info *sinfo) +{ + sinfo->filled |= STATION_INFO_LLID; + sinfo->llid = plink->llid; + sinfo->filled |= STATION_INFO_PLID; + sinfo->plid = plink->plid; + sinfo->filled |= STATION_INFO_PLINK_STATE; + sinfo->plink_state = rtw_plink_state_to_nl80211_plink_state(plink->plink_state); + if (!sta && plink->scanned) { + sinfo->filled |= STATION_INFO_SIGNAL; + sinfo->signal = translate_percentage_to_dbm(plink->scanned->network.PhyInfo.SignalStrength); + sinfo->filled |= STATION_INFO_INACTIVE_TIME; + if (plink->plink_state == RTW_MESH_PLINK_UNKNOWN) + sinfo->inactive_time = 0 - 1; + else + sinfo->inactive_time = rtw_get_passing_time_ms(plink->scanned->last_scanned); + } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + if (sta) { + sinfo->filled |= STATION_INFO_LOCAL_PM; + sinfo->local_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->local_mps); + sinfo->filled |= STATION_INFO_PEER_PM; + sinfo->peer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->peer_mps); + sinfo->filled |= STATION_INFO_NONPEER_PM; + sinfo->nonpeer_pm = rtw_mesh_ps_to_nl80211_mesh_power_mode(sta->nonpeer_mps); + } +#endif +} +#endif /* CONFIG_RTW_MESH */ + static int cfg80211_rtw_get_station(struct wiphy *wiphy, struct net_device *ndev, #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)) @@ -1642,6 +2174,9 @@ static int cfg80211_rtw_get_station(struct wiphy *wiphy, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; +#ifdef CONFIG_RTW_MESH + struct mesh_plink_ent *plink = NULL; +#endif sinfo->filled = 0; @@ -1651,9 +2186,23 @@ static int cfg80211_rtw_get_station(struct wiphy *wiphy, goto exit; } - psta = rtw_get_stainfo(pstapriv, (u8 *)mac); - if (psta == NULL) { - RTW_INFO("%s, sta_info is null\n", __func__); + psta = rtw_get_stainfo(pstapriv, mac); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + if (psta) + plink = psta->plink; + if (!plink) + plink = rtw_mesh_plink_get(padapter, mac); + } +#endif /* CONFIG_RTW_MESH */ + + if ((!MLME_IS_MESH(padapter) && !psta) + #ifdef CONFIG_RTW_MESH + || (MLME_IS_MESH(padapter) && !plink) + #endif + ) { + RTW_INFO(FUNC_NDEV_FMT" no sta info for mac="MAC_FMT"\n" + , FUNC_NDEV_ARG(ndev), MAC_ARG(mac)); ret = -ENOENT; goto exit; } @@ -1679,23 +2228,29 @@ static int cfg80211_rtw_get_station(struct wiphy *wiphy, sinfo->filled |= STATION_INFO_TX_BITRATE; sinfo->txrate.legacy = rtw_get_cur_max_rate(padapter); + } + if (psta) { + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE + || check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE + ) { + sinfo->filled |= STATION_INFO_SIGNAL; + sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi); + } + sinfo->filled |= STATION_INFO_INACTIVE_TIME; + sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time); sinfo->filled |= STATION_INFO_RX_PACKETS; sinfo->rx_packets = sta_rx_data_pkts(psta); - sinfo->filled |= STATION_INFO_TX_PACKETS; sinfo->tx_packets = psta->sta_stats.tx_pkts; - + sinfo->filled |= STATION_INFO_TX_FAILED; + sinfo->tx_failed = psta->sta_stats.tx_fail_cnt; } - /* for Ad-Hoc/AP mode */ - if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) - || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) - || check_fwstate(pmlmepriv, WIFI_AP_STATE)) - && check_fwstate(pmlmepriv, _FW_LINKED) - ) { - /* TODO: should acquire station info... */ - } +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo); +#endif exit: return ret; @@ -1723,6 +2278,9 @@ enum nl80211_iftype { static int cfg80211_rtw_change_iface(struct wiphy *wiphy, struct net_device *ndev, enum nl80211_iftype type, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) + u32 *flags, +#endif struct vif_params *params) { enum nl80211_iftype old_type; @@ -1835,6 +2393,12 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, break; +#ifdef CONFIG_RTW_MESH + case NL80211_IFTYPE_MESH_POINT: + networkType = Ndis802_11_mesh; + break; +#endif + case NL80211_IFTYPE_MONITOR: networkType = Ndis802_11Monitor; #if 0 @@ -1855,7 +2419,7 @@ static int cfg80211_rtw_change_iface(struct wiphy *wiphy, goto exit; } - rtw_setopmode_cmd(padapter, networkType, _TRUE); + rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK); exit: @@ -1904,7 +2468,7 @@ u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms) { struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter); u8 empty = _FALSE; - u32 start; + systime start; u32 pass_ms; start = rtw_get_current_time(); @@ -1982,17 +2546,17 @@ int rtw_cfg80211_is_target_wps_scan(struct cfg80211_scan_request *scan_req, stru static void _rtw_cfg80211_surveydone_event_callback(_adapter *padapter, struct cfg80211_scan_request *scan_req) { + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + RT_CHANNEL_INFO *chset = rfctl->channel_set; _irqL irqL; _list *plist, *phead; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); _queue *queue = &(pmlmepriv->scanned_queue); struct wlan_network *pnetwork = NULL; - u32 cnt = 0; - u32 wait_for_surveydone; - sint wait_status; struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); struct cfg80211_ssid target_ssid; u8 target_wps_scan = 0; + u8 ch; #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s\n", __func__); @@ -2017,11 +2581,15 @@ static void _rtw_cfg80211_surveydone_event_callback(_adapter *padapter, struct c break; pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + ch = pnetwork->network.Configuration.DSConfig; /* report network only if the current channel set contains the channel to which this network belongs */ - if (rtw_chset_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 - && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE + if (rtw_chset_search_ch(chset, ch) >= 0 + && rtw_mlme_band_check(padapter, ch) == _TRUE && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) + && (!IS_DFS_SLAVE_WITH_RD(rfctl) + || rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)) + || !rtw_chset_is_ch_non_ocp(chset, ch)) ) { if (target_wps_scan) rtw_cfg80211_clear_wps_sr_of_non_target_bss(padapter, pnetwork, &target_ssid); @@ -2222,10 +2790,11 @@ void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_ab indicate_buddy_scan = _FALSE; _enter_critical_bh(&wdev_priv->scan_req_lock, &irqL); - if (wdev_priv->scan_request && mlmepriv->scanning_via_buddy_intf == _TRUE) { + if (mlmepriv->scanning_via_buddy_intf == _TRUE) { mlmepriv->scanning_via_buddy_intf = _FALSE; clr_fwstate(mlmepriv, _FW_UNDER_SURVEY); - indicate_buddy_scan = _TRUE; + if (wdev_priv->scan_request) + indicate_buddy_scan = _TRUE; } _exit_critical_bh(&wdev_priv->scan_req_lock, &irqL); @@ -2245,24 +2814,18 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy #endif , struct cfg80211_scan_request *request) { - int i, chan_num = 0; + int i; u8 _status = _FALSE; int ret = 0; - NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; - struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; - struct rtw_ieee80211_channel *pch; + struct sitesurvey_parm parm; _irqL irqL; - u8 *wps_ie = NULL; - uint wps_ielen = 0; - u8 *p2p_ie = NULL; - uint p2p_ielen = 0; u8 survey_times = 3; u8 survey_times_for_one_ch = 6; struct cfg80211_ssid *ssids = request->ssids; int social_channel = 0, j = 0; bool need_indicate_scan_done = _FALSE; bool ps_denied = _FALSE; - + u8 ssc_chk; _adapter *padapter; struct wireless_dev *wdev; struct rtw_wdev_priv *pwdev_priv; @@ -2302,27 +2865,15 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy RTW_INFO(FUNC_ADPT_FMT"%s\n", FUNC_ADPT_ARG(padapter) , wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : ""); -#ifdef CONFIG_MP_INCLUDED - if (rtw_mi_mp_mode_check(padapter)) { - RTW_INFO("MP mode block Scan request\n"); - ret = -EPERM; - goto exit; - } -#endif - - if (adapter_wdev_data(padapter)->block_scan == _TRUE) { - RTW_INFO(FUNC_ADPT_FMT" wdev_priv.block_scan is set\n", FUNC_ADPT_ARG(padapter)); - need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; - } - - rtw_ps_deny(padapter, PS_DENY_SCAN); - ps_denied = _TRUE; - if (_FAIL == rtw_pwr_wakeup(padapter)) { - need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; - } +#if 1 + ssc_chk = rtw_sitesurvey_condition_check(padapter, _TRUE); + if (ssc_chk == SS_DENY_MP_MODE) + goto bypass_p2p_chk; +#ifdef DBG_LA_MODE + if (ssc_chk == SS_DENY_LA_MODE) + goto bypass_p2p_chk; +#endif #ifdef CONFIG_P2P if (pwdinfo->driver_interface == DRIVER_CFG80211) { if (ssids->ssid != NULL @@ -2352,20 +2903,154 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy if (request->ie && request->ie_len > 0) rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len); - if (rtw_is_scan_deny(padapter)) { - RTW_INFO(FUNC_ADPT_FMT ": scan deny\n", FUNC_ADPT_ARG(padapter)); - need_indicate_scan_done = _TRUE; - goto check_need_indicate_scan_done; - } +bypass_p2p_chk: - /* check fw state*/ - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + switch (ssc_chk) { + case SS_ALLOW : + break; -#ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO(FUNC_ADPT_FMT" under WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter)); -#endif + case SS_DENY_MP_MODE: + ret = -EPERM; + goto exit; + #ifdef DBG_LA_MODE + case SS_DENY_LA_MODE: + ret = -EPERM; + goto exit; + #endif + #ifdef CONFIG_RTW_REPEATER_SON + case SS_DENY_RSON_SCANING : + #endif + case SS_DENY_BLOCK_SCAN : + case SS_DENY_SELF_AP_UNDER_WPS : + case SS_DENY_SELF_AP_UNDER_LINKING : + case SS_DENY_SELF_AP_UNDER_SURVEY : + case SS_DENY_SELF_STA_UNDER_SURVEY : + #ifdef CONFIG_CONCURRENT_MODE + case SS_DENY_BUDDY_UNDER_LINK_WPS : + #endif + case SS_DENY_BUSY_TRAFFIC : + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; - if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS | _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) { + case SS_DENY_BY_DRV : + #if CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY + ret = -EBUSY; + goto exit; + #else + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + #endif + break; + + case SS_DENY_SELF_STA_UNDER_LINKING : + ret = -EBUSY; + goto check_need_indicate_scan_done; + + #ifdef CONFIG_CONCURRENT_MODE + case SS_DENY_BUDDY_UNDER_SURVEY : + { + bool scan_via_buddy = rtw_cfg80211_scan_via_buddy(padapter, request); + + if (scan_via_buddy == _FALSE) + need_indicate_scan_done = _TRUE; + + goto check_need_indicate_scan_done; + } + #endif + + default : + RTW_ERR("site survey check code (%d) unknown\n", ssc_chk); + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } + + rtw_ps_deny(padapter, PS_DENY_SCAN); + ps_denied = _TRUE; + if (_FAIL == rtw_pwr_wakeup(padapter)) { + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } + +#else + + +#ifdef CONFIG_MP_INCLUDED + if (rtw_mp_mode_check(padapter)) { + RTW_INFO("MP mode block Scan request\n"); + ret = -EPERM; + goto exit; + } +#endif + +#ifdef CONFIG_P2P + if (pwdinfo->driver_interface == DRIVER_CFG80211) { + if (ssids->ssid != NULL + && _rtw_memcmp(ssids->ssid, "DIRECT-", 7) + && rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL) + ) { + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); + else { + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + #ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); + #endif + } + rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); + + if (request->n_channels == 3 && + request->channels[0]->hw_value == 1 && + request->channels[1]->hw_value == 6 && + request->channels[2]->hw_value == 11 + ) + social_channel = 1; + } + } +#endif /*CONFIG_P2P*/ + + if (request->ie && request->ie_len > 0) + rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len); + +#ifdef CONFIG_RTW_REPEATER_SON + if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) { + RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter)); + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } +#endif + + if (adapter_wdev_data(padapter)->block_scan == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" wdev_priv.block_scan is set\n", FUNC_ADPT_ARG(padapter)); + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } + + rtw_ps_deny(padapter, PS_DENY_SCAN); + ps_denied = _TRUE; + if (_FAIL == rtw_pwr_wakeup(padapter)) { + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } + + if (rtw_is_scan_deny(padapter)) { + RTW_INFO(FUNC_ADPT_FMT ": scan deny\n", FUNC_ADPT_ARG(padapter)); +#if CONFIG_NOTIFY_SCAN_ABORT_WITH_BUSY + ret = -EBUSY; + goto exit; +#else + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; +#endif + } + + /* check fw state*/ + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + +#ifdef CONFIG_DEBUG_CFG80211 + RTW_INFO(FUNC_ADPT_FMT" under WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter)); +#endif + + if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS | _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) { RTW_INFO("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state); if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) @@ -2407,11 +3092,11 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy need_indicate_scan_done = _TRUE; goto check_need_indicate_scan_done; } +#endif #ifdef CONFIG_P2P if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) { rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); - rtw_free_network_queue(padapter, _TRUE); if (social_channel == 0) rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); @@ -2420,46 +3105,42 @@ static int cfg80211_rtw_scan(struct wiphy *wiphy } #endif /* CONFIG_P2P */ + rtw_init_sitesurvey_parm(padapter, &parm); - _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID) * RTW_SSID_SCAN_AMOUNT); /* parsing request ssids, n_ssids */ for (i = 0; i < request->n_ssids && i < RTW_SSID_SCAN_AMOUNT; i++) { #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("ssid=%s, len=%d\n", ssids[i].ssid, ssids[i].ssid_len); #endif - _rtw_memcpy(ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len); - ssid[i].SsidLength = ssids[i].ssid_len; + _rtw_memcpy(&parm.ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len); + parm.ssid[i].SsidLength = ssids[i].ssid_len; } + parm.ssid_num = i; /* parsing channels, n_channels */ - _rtw_memset(ch, 0, sizeof(struct rtw_ieee80211_channel) * RTW_CHANNEL_SCAN_AMOUNT); for (i = 0; i < request->n_channels && i < RTW_CHANNEL_SCAN_AMOUNT; i++) { #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO(FUNC_ADPT_FMT CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(request->channels[i])); #endif - ch[i].hw_value = request->channels[i]->hw_value; - ch[i].flags = request->channels[i]->flags; + parm.ch[i].hw_value = request->channels[i]->hw_value; + parm.ch[i].flags = request->channels[i]->flags; } + parm.ch_num = i; if (request->n_channels == 1) { for (i = 1; i < survey_times_for_one_ch; i++) - _rtw_memcpy(&ch[i], &ch[0], sizeof(struct rtw_ieee80211_channel)); - pch = ch; - chan_num = survey_times_for_one_ch; + _rtw_memcpy(&parm.ch[i], &parm.ch[0], sizeof(struct rtw_ieee80211_channel)); + parm.ch_num = survey_times_for_one_ch; } else if (request->n_channels <= 4) { for (j = request->n_channels - 1; j >= 0; j--) for (i = 0; i < survey_times; i++) - _rtw_memcpy(&ch[j * survey_times + i], &ch[j], sizeof(struct rtw_ieee80211_channel)); - pch = ch; - chan_num = survey_times * request->n_channels; - } else { - pch = ch; - chan_num = request->n_channels; + _rtw_memcpy(&parm.ch[j * survey_times + i], &parm.ch[j], sizeof(struct rtw_ieee80211_channel)); + parm.ch_num = survey_times * request->n_channels; } _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); _enter_critical_bh(&pmlmepriv->lock, &irqL); - _status = rtw_sitesurvey_cmd(padapter, ssid, RTW_SSID_SCAN_AMOUNT, pch, chan_num); + _status = rtw_sitesurvey_cmd(padapter, &parm); if (_status == _SUCCESS) pwdev_priv->scan_request = request; else @@ -2699,8 +3380,8 @@ static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) { u8 *buf = NULL, *pos = NULL; - u32 left; int group_cipher = 0, pairwise_cipher = 0; + u8 mfp_opt = MFP_NO; int ret = 0; int wpa_ielen = 0; int wpa2_ielen = 0; @@ -2726,13 +3407,8 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) _rtw_memcpy(buf, pie , ielen); - /* dump */ - { - int i; - RTW_INFO("set wpa_ie(length:%zu):\n", ielen); - for (i = 0; i < ielen; i = i + 8) - RTW_INFO("0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x\n", buf[i], buf[i + 1], buf[i + 2], buf[i + 3], buf[i + 4], buf[i + 5], buf[i + 6], buf[i + 7]); - } + RTW_INFO("set wpa_ie(length:%zu):\n", ielen); + RTW_INFO_DUMP(NULL, buf, ielen); pos = buf; if (ielen < RSN_HEADER_LEN) { @@ -2753,7 +3429,7 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) pwpa2 = rtw_get_wpa2_ie(buf, &wpa2_ielen, ielen); if (pwpa2 && wpa2_ielen > 0) { - if (rtw_parse_wpa2_ie(pwpa2, wpa2_ielen + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + if (rtw_parse_wpa2_ie(pwpa2, wpa2_ielen + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) { padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; _rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa2[0], wpa2_ielen + 2); @@ -2813,6 +3489,13 @@ static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) break; } + if (mfp_opt == MFP_INVALID) { + RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter)); + ret = -EINVAL; + goto exit; + } + padapter->securitypriv.mfp_opt = mfp_opt; + {/* handle wps_ie */ uint wps_ielen; u8 *wps_ie; @@ -2899,10 +3582,7 @@ static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev, _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); NDIS_802_11_SSID ndis_ssid; struct security_priv *psecuritypriv = &padapter->securitypriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) struct cfg80211_chan_def *pch_def; #endif @@ -2926,11 +3606,6 @@ static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev, goto exit; } - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - ret = -EPERM; - goto exit; - } - rtw_ps_deny(padapter, PS_DENY_JOIN); if (_FAIL == rtw_pwr_wakeup(padapter)) { ret = -EPERM; @@ -2980,13 +3655,14 @@ static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev) { _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); struct wireless_dev *rtw_wdev = padapter->rtw_wdev; - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); enum nl80211_iftype old_type; int ret = 0; RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); - rtw_wdev_set_not_indic_disco(pwdev_priv, 1); +#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT) + rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 1); +#endif old_type = rtw_wdev->iftype; @@ -3003,12 +3679,62 @@ static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev) ret = -EPERM; goto leave_ibss; } - rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, _TRUE); + rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK); } leave_ibss: - rtw_wdev_set_not_indic_disco(pwdev_priv, 0); +#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT) + rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 0); +#endif + + return 0; +} + +bool rtw_cfg80211_is_connect_requested(_adapter *adapter) +{ + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + _irqL irqL; + bool requested; + + _enter_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + requested = pwdev_priv->connect_req ? 1 : 0; + _exit_critical_bh(&pwdev_priv->connect_req_lock, &irqL); + + return requested; +} + +static int _rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + + + /* if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) */ + { + rtw_scan_abort(padapter); + rtw_join_abort_timeout(padapter, 300); + LeaveAllPowerSaveMode(padapter); + rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK); +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_do_disconnect(padapter); +#endif + RTW_INFO("%s...call rtw_indicate_disconnect\n", __func__); + + rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK); + + /* indicate locally_generated = 0 when suspend */ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) + rtw_indicate_disconnect(padapter, 0, wiphy->dev.power.is_prepared ? _FALSE : _TRUE); + #else + /* + * for kernel < 4.2, DISCONNECT event is hardcoded with + * NL80211_ATTR_DISCONNECTED_BY_AP=1 in NL80211 layer + * no need to judge if under suspend + */ + rtw_indicate_disconnect(padapter, 0, _TRUE); + #endif + rtw_pwr_wakeup(padapter); + } return 0; } @@ -3016,35 +3742,37 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, struct cfg80211_connect_params *sme) { int ret = 0; - struct wlan_network *pnetwork = NULL; NDIS_802_11_AUTHENTICATION_MODE authmode; NDIS_802_11_SSID ndis_ssid; - u8 *dst_ssid, *src_ssid; - u8 *dst_bssid, *src_bssid; /* u8 matched_by_bssid=_FALSE; */ /* u8 matched_by_ssid=_FALSE; */ - u8 matched = _FALSE; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &padapter->securitypriv; - _queue *queue = &pmlmepriv->scanned_queue; - struct wireless_dev *pwdev = padapter->rtw_wdev; struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); _irqL irqL; +#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT) rtw_wdev_set_not_indic_disco(pwdev_priv, 1); +#endif RTW_INFO("=>"FUNC_NDEV_FMT" - Start to Connection\n", FUNC_NDEV_ARG(ndev)); RTW_INFO("privacy=%d, key=%p, key_len=%d, key_idx=%d, auth_type=%d\n", sme->privacy, sme->key, sme->key_len, sme->key_idx, sme->auth_type); - if (pwdev_priv->block == _TRUE) { ret = -EBUSY; RTW_INFO("%s wdev_priv.block is set\n", __FUNCTION__); goto exit; } + if (check_fwstate(pmlmepriv, _FW_LINKED | _FW_UNDER_LINKING) == _TRUE) { + + _rtw_disconnect(wiphy, ndev); + RTW_INFO("%s disconnect before connecting! fw_state=0x%x\n", + __FUNCTION__, pmlmepriv->fw_state); + } + #ifdef CONFIG_PLATFORM_MSTAR_SCAN_BEFORE_CONNECT printk("MStar Android!\n"); if (pwdev_priv->bandroid_scan == _FALSE) { @@ -3076,17 +3804,9 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, goto cancel_ps_deny; } - if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - ret = -EPERM; - goto cancel_ps_deny; - } - - if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { - ret = -EBUSY; - RTW_INFO("%s, fw_state=0x%x, goto exit\n", __func__, pmlmepriv->fw_state); - goto cancel_ps_deny; - } + rtw_mi_scan_abort(padapter, _TRUE); + rtw_join_abort_timeout(padapter, 300); #ifdef CONFIG_CONCURRENT_MODE if (rtw_mi_buddy_check_fwstate(padapter, _FW_UNDER_LINKING)) { ret = -EINVAL; @@ -3094,8 +3814,6 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, } #endif - rtw_mi_scan_abort(padapter, _TRUE); - _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); ndis_ssid.SsidLength = sme->ssid_len; _rtw_memcpy(ndis_ssid.Ssid, (u8 *)sme->ssid, sme->ssid_len); @@ -3263,7 +3981,9 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, exit: RTW_INFO("<=%s, ret %d\n", __FUNCTION__, ret); +#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT) rtw_wdev_set_not_indic_disco(pwdev_priv, 0); +#endif return ret; } @@ -3272,29 +3992,26 @@ static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev, u16 reason_code) { _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); RTW_INFO(FUNC_NDEV_FMT" - Start to Disconnect\n", FUNC_NDEV_ARG(ndev)); - rtw_wdev_set_not_indic_disco(pwdev_priv, 1); +#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + if (!wiphy->dev.power.is_prepared) + #endif + rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 1); +#endif rtw_set_to_roam(padapter, 0); /* if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) */ { - rtw_scan_abort(padapter); - LeaveAllPowerSaveMode(padapter); - rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK); - - RTW_INFO("%s...call rtw_indicate_disconnect\n", __func__); - - rtw_free_assoc_resources(padapter, 1); - rtw_indicate_disconnect(padapter, 0, _TRUE); - - rtw_pwr_wakeup(padapter); + _rtw_disconnect(wiphy, ndev); } - rtw_wdev_set_not_indic_disco(pwdev_priv, 0); +#if (RTW_CFG80211_BLOCK_STA_DISCON_EVENT & RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT) + rtw_wdev_set_not_indic_disco(adapter_wdev_data(padapter), 0); +#endif RTW_INFO(FUNC_NDEV_FMT" return 0\n", FUNC_NDEV_ARG(ndev)); return 0; @@ -3482,10 +4199,12 @@ static int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy, #ifdef CONFIG_AP_MODE void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) { +#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE) s32 freq; int channel; struct wireless_dev *pwdev = padapter->rtw_wdev; struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); +#endif struct net_device *ndev = padapter->pnetdev; RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); @@ -3530,8 +4249,9 @@ void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint f } -void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason) +void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason) { +#if !defined(RTW_USE_CFG80211_STA_EVENT) && !defined(COMPAT_KERNEL_RELEASE) s32 freq; int channel; u8 *pmgmt_frame; @@ -3542,6 +4262,7 @@ void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, u struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct wireless_dev *wdev = padapter->rtw_wdev; +#endif struct net_device *ndev = padapter->pnetdev; RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); @@ -3610,17 +4331,27 @@ static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_de int snap_len = 6; unsigned char *pdata; u16 frame_ctl; - unsigned char src_mac_addr[6]; - unsigned char dst_mac_addr[6]; + unsigned char src_mac_addr[ETH_ALEN]; + unsigned char dst_mac_addr[ETH_ALEN]; struct rtw_ieee80211_hdr *dot11_hdr; struct ieee80211_radiotap_header *rtap_hdr; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); +#ifdef CONFIG_DFS_MASTER + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); +#endif RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); if (skb) rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); + if (IS_CH_WAITING(rfctl)) { + #ifdef CONFIG_DFS_MASTER + if (rtw_rfctl_overlap_radar_detect_ch(rfctl)) + goto fail; + #endif + } + if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) goto fail; @@ -3808,8 +4539,11 @@ static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct ne mon_ndev->type = ARPHRD_IEEE80211_RADIOTAP; strncpy(mon_ndev->name, name, IFNAMSIZ); mon_ndev->name[IFNAMSIZ - 1] = 0; +#if (LINUX_VERSION_CODE > KERNEL_VERSION(4, 11, 8)) mon_ndev->priv_destructor = rtw_ndev_destructor; - mon_ndev->needs_free_netdev = true; +#else + mon_ndev->destructor = rtw_ndev_destructor; +#endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) mon_ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops; @@ -3875,7 +4609,11 @@ static int #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) unsigned char name_assign_type, #endif - enum nl80211_iftype type, struct vif_params *params) + enum nl80211_iftype type, + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) + u32 *flags, + #endif + struct vif_params *params) { int ret = 0; struct wireless_dev *wdev = NULL; @@ -3901,6 +4639,9 @@ static int #endif case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_AP: +#ifdef CONFIG_RTW_MESH + case NL80211_IFTYPE_MESH_POINT: +#endif padapter = dvobj_get_unregisterd_adapter(dvobj); if (!padapter) { RTW_WARN("adapter pool empty!\n"); @@ -3929,7 +4670,6 @@ static int case NL80211_IFTYPE_ADHOC: case NL80211_IFTYPE_AP_VLAN: case NL80211_IFTYPE_WDS: - case NL80211_IFTYPE_MESH_POINT: default: ret = -ENODEV; RTW_INFO("Unsupported interface type\n"); @@ -4010,7 +4750,6 @@ static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, co u8 *pbuf = NULL; uint len, wps_ielen = 0; uint p2p_ielen = 0; - u8 *p2p_ie; u8 got_p2p_ie = _FALSE; struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); /* struct sta_priv *pstapriv = &padapter->stapriv; */ @@ -4025,6 +4764,12 @@ static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, co if (head_len < 24) return -EINVAL; + #ifdef CONFIG_FW_HANDLE_TXBCN + if (!rtw_ap_nums_check(adapter)) { + RTW_ERR(FUNC_ADPT_FMT"failed, con't support over %d BCN\n", FUNC_ADPT_ARG(adapter), CONFIG_LIMITED_AP_NUM); + return -EINVAL; + } + #endif /*CONFIG_FW_HANDLE_TXBCN*/ pbuf = rtw_zmalloc(head_len + tail_len); if (!pbuf) @@ -4050,7 +4795,6 @@ static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, co if (adapter->wdinfo.driver_interface == DRIVER_CFG80211) { /* check p2p if enable */ if (rtw_get_p2p_ie(pbuf + _FIXED_IE_LENGTH_, len - _FIXED_IE_LENGTH_, NULL, &p2p_ielen)) { - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; struct wifidirect_info *pwdinfo = &(adapter->wdinfo); RTW_INFO("got p2p_ie, len=%d\n", p2p_ielen); @@ -4104,8 +4848,16 @@ static int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *ndev, _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) { + ret = -ENOTSUPP; + goto exit; + } + rtw_mi_scan_abort(adapter, _TRUE); + rtw_mi_buddy_set_scan_deny(adapter, 300); ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len); +exit: return ret; } @@ -4126,8 +4878,13 @@ static int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *ndev, static int cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev) { + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure); + rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK); + return 0; } #else @@ -4140,6 +4897,12 @@ static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, RTW_INFO(FUNC_NDEV_FMT" hidden_ssid:%d, auth_type:%d\n", FUNC_NDEV_ARG(ndev), settings->hidden_ssid, settings->auth_type); + if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) { + ret = -ENOTSUPP; + goto exit; + } + rtw_mi_scan_abort(adapter, _TRUE); + rtw_mi_buddy_set_scan_deny(adapter, 300); ret = rtw_add_beacon(adapter, settings->beacon.head, settings->beacon.head_len, settings->beacon.tail, settings->beacon.tail_len); @@ -4165,6 +4928,7 @@ static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); } +exit: return ret; } @@ -4183,10 +4947,15 @@ static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *nd static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev) { + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure); + rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK); + return 0; } - #endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) */ #if CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) @@ -4200,6 +4969,7 @@ static int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev if (!params) { RTW_WARN(FUNC_ADPT_FMT" params NULL\n", FUNC_ADPT_ARG(adapter)); + rtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS); goto exit; } @@ -4211,44 +4981,352 @@ static int cfg80211_rtw_set_mac_acl(struct wiphy *wiphy, struct net_device *ndev else if (params->acl_policy == NL80211_ACL_POLICY_DENY_UNLESS_LISTED) acl_mode = RTW_ACL_MODE_DENY_UNLESS_LISTED; - if (!params->n_acl_entries) { - if (acl_mode != RTW_ACL_MODE_DISABLED) - RTW_WARN(FUNC_ADPT_FMT" acl_policy:%d with no entry\n" - , FUNC_ADPT_ARG(adapter), params->acl_policy); - acl_mode = RTW_ACL_MODE_DISABLED; - goto exit; - } + rtw_macaddr_acl_clear(adapter, RTW_ACL_PERIOD_BSS); + + rtw_set_macaddr_acl(adapter, RTW_ACL_PERIOD_BSS, acl_mode); for (i = 0; i < params->n_acl_entries; i++) - rtw_acl_add_sta(adapter, params->mac_addrs[i].addr); + rtw_acl_add_sta(adapter, RTW_ACL_PERIOD_BSS, params->mac_addrs[i].addr); ret = 0; exit: - rtw_set_macaddr_acl(adapter, acl_mode); return ret; } #endif /* CONFIG_RTW_MACADDR_ACL && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) */ -static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev, -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)) - u8 *mac, -#else - const u8 *mac, +const char *_nl80211_sta_flags_str[] = { + "INVALID", + "AUTHORIZED", + "SHORT_PREAMBLE", + "WME", + "MFP", + "AUTHENTICATED", + "TDLS_PEER", + "ASSOCIATED", +}; + +#define nl80211_sta_flags_str(_f) ((_f <= NL80211_STA_FLAG_MAX) ? _nl80211_sta_flags_str[_f] : _nl80211_sta_flags_str[0]) + +const char *_nl80211_plink_state_str[] = { + "LISTEN", + "OPN_SNT", + "OPN_RCVD", + "CNF_RCVD", + "ESTAB", + "HOLDING", + "BLOCKED", + "UNKNOWN", +}; + +#define nl80211_plink_state_str(_s) ((_s < NUM_NL80211_PLINK_STATES) ? _nl80211_plink_state_str[_s] : _nl80211_plink_state_str[NUM_NL80211_PLINK_STATES]) + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)) +#define NL80211_PLINK_ACTION_NO_ACTION PLINK_ACTION_INVALID +#define NL80211_PLINK_ACTION_OPEN PLINK_ACTION_OPEN +#define NL80211_PLINK_ACTION_BLOCK PLINK_ACTION_BLOCK +#define NUM_NL80211_PLINK_ACTIONS 3 #endif - struct station_parameters *params) + +const char *_nl80211_plink_actions_str[] = { + "NO_ACTION", + "OPEN", + "BLOCK", + "UNKNOWN", +}; + +#define nl80211_plink_actions_str(_a) ((_a < NUM_NL80211_PLINK_ACTIONS) ? _nl80211_plink_actions_str[_a] : _nl80211_plink_actions_str[NUM_NL80211_PLINK_ACTIONS]) + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) +const char *_nl80211_mesh_power_mode_str[] = { + "UNKNOWN", + "ACTIVE", + "LIGHT_SLEEP", + "DEEP_SLEEP", +}; + +#define nl80211_mesh_power_mode_str(_p) ((_p <= NL80211_MESH_POWER_MAX) ? _nl80211_mesh_power_mode_str[_p] : _nl80211_mesh_power_mode_str[0]) +#endif + +void dump_station_parameters(void *sel, struct wiphy *wiphy, const struct station_parameters *params) { - int ret = 0; -#ifdef CONFIG_TDLS - _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); - struct sta_priv *pstapriv = &padapter->stapriv; - struct sta_info *psta; -#endif /* CONFIG_TDLS */ - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); +#if DBG_RTW_CFG80211_STA_PARAM + if (params->supported_rates_len) { + #define SUPP_RATES_BUF_LEN (3 * RTW_G_RATES_NUM + 1) + int i; + char supp_rates_buf[SUPP_RATES_BUF_LEN] = {0}; + u8 cnt = 0; -#ifdef CONFIG_TDLS - psta = rtw_get_stainfo(pstapriv, (u8 *)mac); - if (psta == NULL) { + rtw_warn_on(params->supported_rates_len > RTW_G_RATES_NUM); + + for (i = 0; i < params->supported_rates_len; i++) { + if (i >= RTW_G_RATES_NUM) + break; + cnt += snprintf(supp_rates_buf + cnt, SUPP_RATES_BUF_LEN - cnt -1 + , "%02X ", params->supported_rates[i]); + if (cnt >= SUPP_RATES_BUF_LEN - 1) + break; + } + + RTW_PRINT_SEL(sel, "supported_rates:%s\n", supp_rates_buf); + } + + if (params->vlan) + RTW_PRINT_SEL(sel, "vlan:"NDEV_FMT"\n", NDEV_ARG(params->vlan)); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) + if (params->sta_flags_mask) { + #define STA_FLAGS_BUF_LEN 128 + int i = 0; + char sta_flags_buf[STA_FLAGS_BUF_LEN] = {0}; + u8 cnt = 0; + + for (i = 1; i <= NL80211_STA_FLAG_MAX; i++) { + if (params->sta_flags_mask & BIT(i)) { + cnt += snprintf(sta_flags_buf + cnt, STA_FLAGS_BUF_LEN - cnt -1, "%s=%u " + , nl80211_sta_flags_str(i), (params->sta_flags_set & BIT(i)) ? 1 : 0); + if (cnt >= STA_FLAGS_BUF_LEN - 1) + break; + } + } + + RTW_PRINT_SEL(sel, "sta_flags:%s\n", sta_flags_buf); + } +#else + u32 station_flags; + #error "TBD\n" +#endif + + if (params->listen_interval != -1) + RTW_PRINT_SEL(sel, "listen_interval:%d\n", params->listen_interval); + + if (params->aid) + RTW_PRINT_SEL(sel, "aid:%u\n", params->aid); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)) + if (params->peer_aid) + RTW_PRINT_SEL(sel, "peer_aid:%u\n", params->peer_aid); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) + if (params->plink_action != NL80211_PLINK_ACTION_NO_ACTION) + RTW_PRINT_SEL(sel, "plink_action:%s\n", nl80211_plink_actions_str(params->plink_action)); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + if (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE) + #endif + RTW_PRINT_SEL(sel, "plink_state:%s\n" + , nl80211_plink_state_str(params->plink_state)); +#endif + +#if 0 /* TODO */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)) + const struct ieee80211_ht_cap *ht_capa; +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + const struct ieee80211_vht_cap *vht_capa; +#endif +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + if (params->sta_modify_mask & STATION_PARAM_APPLY_UAPSD) + RTW_PRINT_SEL(sel, "uapsd_queues:0x%02x\n", params->uapsd_queues); + if (params->max_sp) + RTW_PRINT_SEL(sel, "max_sp:%u\n", params->max_sp); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + if (params->local_pm != NL80211_MESH_POWER_UNKNOWN) { + RTW_PRINT_SEL(sel, "local_pm:%s\n" + , nl80211_mesh_power_mode_str(params->local_pm)); + } + + if (params->sta_modify_mask & STATION_PARAM_APPLY_CAPABILITY) + RTW_PRINT_SEL(sel, "capability:0x%04x\n", params->capability); + +#if 0 /* TODO */ + const u8 *ext_capab; + u8 ext_capab_len; +#endif +#endif + +#if 0 /* TODO */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)) + const u8 *supported_channels; + u8 supported_channels_len; + const u8 *supported_oper_classes; + u8 supported_oper_classes_len; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) + u8 opmode_notif; + bool opmode_notif_used; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) + int support_p2p_ps; +#endif +#endif +#endif /* DBG_RTW_CFG80211_STA_PARAM */ +} + +static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0)) + u8 *mac, +#else + const u8 *mac, +#endif + struct station_parameters *params) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); +#if defined(CONFIG_TDLS) || defined(CONFIG_RTW_MESH) + struct sta_priv *pstapriv = &padapter->stapriv; +#endif +#ifdef CONFIG_TDLS + struct sta_info *psta; +#endif /* CONFIG_TDLS */ + + RTW_INFO(FUNC_NDEV_FMT" mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac)); + +#if CONFIG_RTW_MACADDR_ACL + if (rtw_access_ctrl(padapter, mac) == _FALSE) { + RTW_INFO(FUNC_NDEV_FMT" deny by macaddr ACL\n", FUNC_NDEV_ARG(ndev)); + ret = -EINVAL; + goto exit; + } +#endif + + dump_station_parameters(RTW_DBGDUMP, wiphy, params); + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + struct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg; + struct rtw_mesh_info *minfo = &padapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *plink = NULL; + struct wlan_network *scanned = NULL; + bool acnode = 0; + u8 add_new_sta = 0, probe_req = 0; + _irqL irqL; + + if (params->plink_state != NL80211_PLINK_LISTEN) { + RTW_WARN(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(ndev), nl80211_plink_state_str(params->plink_state)); + rtw_warn_on(1); + } + if (!params->aid || params->aid > pstapriv->max_aid) { + RTW_WARN(FUNC_NDEV_FMT" invalid aid:%u\n", FUNC_NDEV_ARG(ndev), params->aid); + rtw_warn_on(1); + ret = -EINVAL; + goto exit; + } + + _enter_critical_bh(&(plink_ctl->lock), &irqL); + + plink = _rtw_mesh_plink_get(padapter, mac); + if (plink) + goto release_plink_ctl; + + #if CONFIG_RTW_MESH_PEER_BLACKLIST + if (rtw_mesh_peer_blacklist_search(padapter, mac)) { + RTW_INFO(FUNC_NDEV_FMT" deny by peer blacklist\n" + , FUNC_NDEV_ARG(ndev)); + ret = -EINVAL; + goto release_plink_ctl; + } + #endif + + scanned = rtw_find_network(&padapter->mlmepriv.scanned_queue, mac); + if (!scanned + || rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms + ) { + if (!scanned) + RTW_INFO(FUNC_NDEV_FMT" corresponding network not found\n", FUNC_NDEV_ARG(ndev)); + else + RTW_INFO(FUNC_NDEV_FMT" corresponding network too old\n", FUNC_NDEV_ARG(ndev)); + + if (adapter_to_rfctl(padapter)->offch_state == OFFCHS_NONE) + probe_req = 1; + + ret = -EINVAL; + goto release_plink_ctl; + } + + #if CONFIG_RTW_MESH_ACNODE_PREVENT + if (plink_ctl->acnode_rsvd) + acnode = rtw_mesh_scanned_is_acnode_confirmed(padapter, scanned); + #endif + + /* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */ + if (plink_ctl->num >= mcfg->max_peer_links + acnode ? 1 : 0) { + RTW_INFO(FUNC_NDEV_FMT" exceed max_peer_links:%u%s\n" + , FUNC_NDEV_ARG(ndev), mcfg->max_peer_links, acnode ? " acn" : ""); + ret = -EINVAL; + goto release_plink_ctl; + } + + if (!rtw_bss_is_candidate_mesh_peer(&padapter->mlmepriv.cur_network.network, &scanned->network, 1, 1)) { + RTW_WARN(FUNC_NDEV_FMT" corresponding network is not candidate with same ch\n" + , FUNC_NDEV_ARG(ndev)); + ret = -EINVAL; + goto release_plink_ctl; + } + + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + if (!rtw_mesh_cto_mgate_network_filter(padapter, scanned)) { + RTW_INFO(FUNC_NDEV_FMT" peer filtered out by cto_mgate check\n" + , FUNC_NDEV_ARG(ndev)); + ret = -EINVAL; + goto release_plink_ctl; + } + #endif + + if (_rtw_mesh_plink_add(padapter, mac) == _SUCCESS) { + /* hook corresponding network in scan queue */ + plink = _rtw_mesh_plink_get(padapter, mac); + plink->aid = params->aid; + plink->scanned = scanned; + + #if CONFIG_RTW_MESH_ACNODE_PREVENT + if (acnode) { + RTW_INFO(FUNC_ADPT_FMT" acnode "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(scanned->network.MacAddress)); + } + #endif + + add_new_sta = 1; + } else { + RTW_WARN(FUNC_NDEV_FMT" rtw_mesh_plink_add not success\n" + , FUNC_NDEV_ARG(ndev)); + ret = -EINVAL; + } +release_plink_ctl: + _exit_critical_bh(&(plink_ctl->lock), &irqL); + + if (probe_req) + issue_probereq(padapter, &padapter->mlmepriv.cur_network.network.mesh_id, mac); + + if (add_new_sta) { + struct station_info sinfo; + + #ifdef CONFIG_DFS_MASTER + if (IS_UNDER_CAC(adapter_to_rfctl(padapter))) + rtw_force_stop_cac(adapter_to_rfctl(padapter), 300); + #endif + + /* indicate new sta */ + _rtw_memset(&sinfo, 0, sizeof(sinfo)); + cfg80211_new_sta(ndev, mac, &sinfo, GFP_ATOMIC); + } + goto exit; + } +#endif /* CONFIG_RTW_MESH */ + +#ifdef CONFIG_TDLS + psta = rtw_get_stainfo(pstapriv, (u8 *)mac); + if (psta == NULL) { psta = rtw_alloc_stainfo(pstapriv, (u8 *)mac); if (psta == NULL) { RTW_INFO("[%s] Alloc station for "MAC_FMT" fail\n", __FUNCTION__, MAC_ARG(mac)); @@ -4282,17 +5360,16 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct sta_priv *pstapriv = &padapter->stapriv; - RTW_INFO("+"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); - - #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)) target_mac = mac; #else target_mac = params->mac; #endif - if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE) { - RTW_INFO("%s, fw_state != FW_LINKED|WIFI_AP_STATE\n", __func__); + RTW_INFO("+"FUNC_NDEV_FMT" mac=%pM\n", FUNC_NDEV_ARG(ndev), target_mac); + + if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE)) != _TRUE) { + RTW_INFO("%s, fw_state != FW_LINKED|WIFI_AP_STATE|WIFI_MESH_STATE\n", __func__); return -EINVAL; } @@ -4302,8 +5379,9 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev flush_all_cam_entry(padapter); /* clear CAM */ +#ifdef CONFIG_AP_MODE ret = rtw_sta_flush(padapter, _TRUE); - +#endif return ret; } @@ -4327,17 +5405,18 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev plist = get_next(plist); - if (_rtw_memcmp((u8 *)target_mac, psta->hwaddr, ETH_ALEN)) { + if (_rtw_memcmp((u8 *)target_mac, psta->cmn.mac_addr, ETH_ALEN)) { if (psta->dot8021xalg == 1 && psta->bpairwise_key_installed == _FALSE) RTW_INFO("%s, sta's dot8021xalg = 1 and key_installed = _FALSE\n", __func__); else { - RTW_INFO("free psta=%p, aid=%d\n", psta, psta->aid); + RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid); rtw_list_delete(&psta->asoc_list); pstapriv->asoc_list_cnt--; + STA_SET_MESH_PLINK(psta, NULL); /* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ - if (check_fwstate(pmlmepriv, (WIFI_AP_STATE)) == _TRUE) + if (MLME_IS_AP(padapter)) updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE); else updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); @@ -4356,6 +5435,11 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_mesh_plink_del(padapter, target_mac); +#endif + RTW_INFO("-"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); return ret; @@ -4370,15 +5454,131 @@ static int cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *n #endif struct station_parameters *params) { - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); +#ifdef CONFIG_RTW_MESH + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta = NULL; + _irqL irqL; +#endif + int ret = 0; - return 0; -} + RTW_INFO(FUNC_NDEV_FMT" mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac)); -struct sta_info *rtw_sta_info_get_by_idx(const int idx, struct sta_priv *pstapriv) + dump_station_parameters(RTW_DBGDUMP, wiphy, params); -{ +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + enum cfg80211_station_type sta_type = CFG80211_STA_MESH_PEER_USER; + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl; + struct mesh_plink_ent *plink = NULL; + _irqL irqL2; + struct sta_info *del_sta = NULL; + + ret = cfg80211_check_station_change(wiphy, params, sta_type); + if (ret) { + RTW_INFO("cfg80211_check_station_change return %d\n", ret); + goto exit; + } + + _enter_critical_bh(&(plink_ctl->lock), &irqL2); + + plink = _rtw_mesh_plink_get(adapter, mac); + if (!plink) { + ret = -ENOENT; + goto release_plink_ctl; + } + + plink->plink_state = nl80211_plink_state_to_rtw_plink_state(params->plink_state); + + #if CONFIG_RTW_MESH_ACNODE_PREVENT + if (params->plink_state == NL80211_PLINK_OPN_SNT + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + && (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE) + #endif + ) { + if (rtw_mesh_scanned_is_acnode_confirmed(adapter, plink->scanned) + && rtw_mesh_acnode_prevent_allow_sacrifice(adapter) + ) { + struct sta_info *sac = rtw_mesh_acnode_prevent_pick_sacrifice(adapter); + + if (sac) { + del_sta = sac; + _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + if (!rtw_is_list_empty(&del_sta->asoc_list)) { + rtw_list_delete(&del_sta->asoc_list); + stapriv->asoc_list_cnt--; + STA_SET_MESH_PLINK(del_sta, NULL); + } + _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + RTW_INFO(FUNC_ADPT_FMT" sacrifice "MAC_FMT" for acnode\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(del_sta->cmn.mac_addr)); + } + } + } else + #endif + if ((params->plink_state == NL80211_PLINK_OPN_RCVD + || params->plink_state == NL80211_PLINK_CNF_RCVD + || params->plink_state == NL80211_PLINK_ESTAB) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + && (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE) + #endif + ) { + sta = rtw_get_stainfo(stapriv, mac); + if (!sta) { + sta = rtw_alloc_stainfo(stapriv, mac); + if (!sta) + goto release_plink_ctl; + } + if (params->plink_state == NL80211_PLINK_ESTAB) { + if (rtw_mesh_peer_establish(adapter, plink, sta) != _SUCCESS) { + rtw_free_stainfo(adapter, sta); + ret = -ENOENT; + goto release_plink_ctl; + } + } + } + else if (params->plink_state == NL80211_PLINK_HOLDING + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + && (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE) + #endif + ) { + del_sta = rtw_get_stainfo(stapriv, mac); + if (!del_sta) + goto release_plink_ctl; + + _enter_critical_bh(&stapriv->asoc_list_lock, &irqL); + if (!rtw_is_list_empty(&del_sta->asoc_list)) { + rtw_list_delete(&del_sta->asoc_list); + stapriv->asoc_list_cnt--; + STA_SET_MESH_PLINK(del_sta, NULL); + } + _exit_critical_bh(&stapriv->asoc_list_lock, &irqL); + } + +release_plink_ctl: + _exit_critical_bh(&(plink_ctl->lock), &irqL2); + + if (del_sta) { + u8 sta_addr[ETH_ALEN]; + u8 updated = _FALSE; + + _rtw_memcpy(sta_addr, del_sta->cmn.mac_addr, ETH_ALEN); + updated = ap_free_sta(adapter, del_sta, 0, 0, 1); + rtw_mesh_expire_peer(stapriv->padapter, sta_addr); + + associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL); + } + } +#endif /* CONFIG_RTW_MESH */ + +exit: + return ret; +} + +struct sta_info *rtw_sta_info_get_by_idx(struct sta_priv *pstapriv, const int idx, u8 *asoc_list_num) +{ _list *phead, *plist; struct sta_info *psta = NULL; int i = 0; @@ -4393,32 +5593,75 @@ struct sta_info *rtw_sta_info_get_by_idx(const int idx, struct sta_priv *pstapri plist = get_next(plist); i++; } + + if (asoc_list_num) + *asoc_list_num = i; + return psta; } static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *ndev, int idx, u8 *mac, struct station_info *sinfo) { +#define DBG_DUMP_STATION 0 int ret = 0; _irqL irqL; _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); - struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + struct sta_info *psta = NULL; +#ifdef CONFIG_RTW_MESH + struct mesh_plink_ent *plink = NULL; +#endif + u8 asoc_list_num; + + if (DBG_DUMP_STATION) + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); - psta = rtw_sta_info_get_by_idx(idx, pstapriv); + psta = rtw_sta_info_get_by_idx(pstapriv, idx, &asoc_list_num); _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); - if (NULL == psta) { - RTW_INFO("Station is not found\n"); + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + if (psta) + plink = psta->plink; + if (!plink) + plink = rtw_mesh_plink_get_no_estab_by_idx(padapter, idx - asoc_list_num); + } +#endif /* CONFIG_RTW_MESH */ + + if ((!MLME_IS_MESH(padapter) && !psta) + #ifdef CONFIG_RTW_MESH + || (MLME_IS_MESH(padapter) && !plink) + #endif + ) { + if (DBG_DUMP_STATION) + RTW_INFO(FUNC_NDEV_FMT" end with idx:%d\n", FUNC_NDEV_ARG(ndev), idx); ret = -ENOENT; goto exit; } - _rtw_memcpy(mac, psta->hwaddr, ETH_ALEN); + + if (psta) + _rtw_memcpy(mac, psta->cmn.mac_addr, ETH_ALEN); + #ifdef CONFIG_RTW_MESH + else + _rtw_memcpy(mac, plink->addr, ETH_ALEN); + #endif + sinfo->filled = 0; - sinfo->filled |= STATION_INFO_SIGNAL; - sinfo->signal = psta->rssi; + + if (psta) { + sinfo->filled |= STATION_INFO_SIGNAL; + sinfo->signal = translate_percentage_to_dbm(psta->cmn.rssi_stat.rssi); + sinfo->filled |= STATION_INFO_INACTIVE_TIME; + sinfo->inactive_time = rtw_get_passing_time_ms(psta->sta_stats.last_rx_time); + } + +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) + rtw_cfg80211_fill_mesh_only_sta_info(plink, psta, sinfo); +#endif exit: return ret; @@ -4427,8 +5670,6 @@ static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *nde static int cfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *ndev, struct bss_parameters *params) { - u8 i; - RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); /* RTW_INFO("use_cts_prot=%d\n", params->use_cts_prot); @@ -4444,6 +5685,97 @@ static int cfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *ndev, } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) +static int cfg80211_rtw_set_txq_params(struct wiphy *wiphy +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + , struct net_device *ndev +#endif + , struct ieee80211_txq_params *params) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + _adapter *padapter = rtw_netdev_priv(ndev); +#else + _adapter *padapter = wiphy_to_adapter(wiphy); +#endif + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 ac, AIFS, ECWMin, ECWMax, aSifsTime; + u16 TXOP; + u8 shift_count = 0; + u32 acParm; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + ac = params->ac; +#else + ac = params->queue; +#endif + +#if 0 + RTW_INFO("ac=%d\n", ac); + RTW_INFO("txop=%u\n", params->txop); + RTW_INFO("cwmin=%u\n", params->cwmin); + RTW_INFO("cwmax=%u\n", params->cwmax); + RTW_INFO("aifs=%u\n", params->aifs); +#endif + + if (is_supported_5g(pmlmeext->cur_wireless_mode) || + (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) + aSifsTime = 16; + else + aSifsTime = 10; + + AIFS = params->aifs * pmlmeinfo->slotTime + aSifsTime; + + while ((params->cwmin + 1) >> shift_count != 1) { + shift_count++; + if (shift_count == 15) + break; + } + + ECWMin = shift_count; + + shift_count = 0; + while ((params->cwmax + 1) >> shift_count != 1) { + shift_count++; + if (shift_count == 15) + break; + } + + ECWMax = shift_count; + + TXOP = le16_to_cpu(params->txop); + + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + + switch (ac) { + case NL80211_TXQ_Q_VO: + RTW_INFO(FUNC_NDEV_FMT" AC_VO = 0x%08x\n", FUNC_ADPT_ARG(padapter), acParm); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); + break; + + case NL80211_TXQ_Q_VI: + RTW_INFO(FUNC_NDEV_FMT" AC_VI = 0x%08x\n", FUNC_ADPT_ARG(padapter), acParm); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); + break; + + case NL80211_TXQ_Q_BE: + RTW_INFO(FUNC_NDEV_FMT" AC_BE = 0x%08x\n", FUNC_ADPT_ARG(padapter), acParm); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); + break; + + case NL80211_TXQ_Q_BK: + RTW_INFO(FUNC_NDEV_FMT" AC_BK = 0x%08x\n", FUNC_ADPT_ARG(padapter), acParm); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); + break; + + default: + break; + } + + return 0; +} +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) */ + static int cfg80211_rtw_set_channel(struct wiphy *wiphy #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) , struct net_device *ndev @@ -4483,7 +5815,10 @@ static int cfg80211_rtw_set_channel(struct wiphy *wiphy break; } - set_channel_bwmode(padapter, chan_target, chan_offset, chan_width); + RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n" + , FUNC_ADPT_ARG(padapter), chan_target, chan_width, chan_offset); + + rtw_set_chbw_cmd(padapter, chan_target, chan_width, chan_offset, RTW_CMDF_WAIT_ACK); return 0; } @@ -4579,8 +5914,10 @@ static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy break; } #endif + RTW_INFO(FUNC_ADPT_FMT" ch:%d bw:%d, offset:%d\n" + , FUNC_ADPT_ARG(padapter), target_channal, target_width, target_offset); - set_channel_bwmode(padapter, target_channal, target_offset, target_width); + rtw_set_chbw_cmd(padapter, target_channal, target_width, target_offset, RTW_CMDF_WAIT_ACK); return 0; } @@ -4605,7 +5942,6 @@ static int cfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *ndev, void rtw_cfg80211_rx_probe_request(_adapter *adapter, union recv_frame *rframe) { struct wireless_dev *wdev = adapter->rtw_wdev; - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); u8 *frame = get_recvframe_data(rframe); uint frame_len = rframe->u.hdr.len; s32 freq; @@ -4615,7 +5951,8 @@ void rtw_cfg80211_rx_probe_request(_adapter *adapter, union recv_frame *rframe) freq = rtw_ch2freq(ch); #ifdef CONFIG_DEBUG_CFG80211 - RTW_INFO("RTW_Rx: probe request, ch=%d(%d)\n", ch, sch); + RTW_INFO("RTW_Rx: probe request, ch=%d(%d), ta="MAC_FMT"\n" + , ch, sch, MAC_ARG(get_addr2_ptr(frame))); #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) @@ -4638,7 +5975,8 @@ void rtw_cfg80211_rx_action_p2p(_adapter *adapter, union recv_frame *rframe) ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; freq = rtw_ch2freq(ch); - RTW_INFO("RTW_Rx:ch=%d(%d)\n", ch, sch); + RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n" + , ch, sch, MAC_ARG(get_addr2_ptr(frame))); #ifdef CONFIG_P2P type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE); if (type >= 0) @@ -4671,7 +6009,8 @@ void rtw_cfg80211_rx_p2p_action_public(_adapter *adapter, union recv_frame *rfra ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; freq = rtw_ch2freq(ch); - RTW_INFO("RTW_Rx:ch=%d(%d)\n", ch, sch); + RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n" + , ch, sch, MAC_ARG(get_addr2_ptr(frame))); #ifdef CONFIG_P2P type = rtw_p2p_check_frames(adapter, frame, frame_len, _FALSE); if (type >= 0) { @@ -4699,6 +6038,7 @@ void rtw_cfg80211_rx_p2p_action_public(_adapter *adapter, union recv_frame *rfra break; case P2P_PROVISION_DISC_RESP: case P2P_INVIT_RESP: + rtw_clear_scan_deny(adapter); #if !RTW_P2P_GROUP_INTERFACE rtw_mi_buddy_set_scan_deny(adapter, 2000); #endif @@ -4727,34 +6067,98 @@ void rtw_cfg80211_rx_p2p_action_public(_adapter *adapter, union recv_frame *rfra void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg) { struct wireless_dev *wdev = adapter->rtw_wdev; - struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); u8 *frame = get_recvframe_data(rframe); uint frame_len = rframe->u.hdr.len; s32 freq; u8 ch, sch = rtw_get_oper_ch(adapter); u8 category, action; + int type = -1; ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; freq = rtw_ch2freq(ch); - rtw_action_frame_parse(frame, frame_len, &category, &action); + RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n" + , ch, sch, MAC_ARG(get_addr2_ptr(frame))); - if (action == ACT_PUBLIC_GAS_INITIAL_REQ) { - rtw_mi_set_scan_deny(adapter, 200); - rtw_mi_scan_abort(adapter, _FALSE); /*rtw_scan_abort_no_wait*/ +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(adapter)) { + type = rtw_mesh_check_frames_rx(adapter, frame, frame_len); + if (type >= 0) + goto indicate; + } +#endif + rtw_action_frame_parse(frame, frame_len, &category, &action); + if (category == RTW_WLAN_CATEGORY_PUBLIC) { + if (action == ACT_PUBLIC_GAS_INITIAL_REQ) { + rtw_mi_set_scan_deny(adapter, 200); + rtw_mi_scan_abort(adapter, _FALSE); /*rtw_scan_abort_no_wait*/ + } } +indicate: #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); #else cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); #endif - RTW_INFO("RTW_Rx:ch=%d(%d)\n", ch, sch); - if (msg) - RTW_INFO("RTW_Rx:%s\n", msg); - else - RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action); + if (type == -1) { + if (msg) + RTW_INFO("RTW_Rx:%s\n", msg); + else + RTW_INFO("RTW_Rx:category(%u), action(%u)\n", category, action); + } +} + +#ifdef CONFIG_RTW_80211K +void rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe) +{ + struct wireless_dev *wdev = adapter->rtw_wdev; + u8 *frame = get_recvframe_data(rframe); + uint frame_len = rframe->u.hdr.len; + s32 freq; + u8 ch, sch = rtw_get_oper_ch(adapter); + + ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; + freq = rtw_ch2freq(ch); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); +#else + cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); +#endif + RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n" + , ch, sch, MAC_ARG(get_addr2_ptr(frame))); +} +#endif /* CONFIG_RTW_80211K */ + +void rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg) +{ + struct wireless_dev *wdev = adapter->rtw_wdev; + u8 *frame = get_recvframe_data(rframe); + uint frame_len = rframe->u.hdr.len; + s32 freq; + u8 ch, sch = rtw_get_oper_ch(adapter); + + ch = rframe->u.hdr.attrib.ch ? rframe->u.hdr.attrib.ch : sch; + freq = rtw_ch2freq(ch); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, frame_len, GFP_ATOMIC); +#else + cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); +#endif + + RTW_INFO("RTW_Rx:ch=%d(%d), ta="MAC_FMT"\n", ch, sch, MAC_ARG(get_addr2_ptr(frame))); + #ifdef CONFIG_RTW_MESH + if (!rtw_sae_check_frames(adapter, frame, frame_len, _FALSE)) + #endif + { + if (msg) + RTW_INFO("RTW_Rx:%s\n", msg); + else + RTW_INFO("RTW_Rx:frame_control:0x%02x\n", le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)rframe)->frame_ctl)); + } } #ifdef CONFIG_P2P @@ -4787,7 +6191,6 @@ void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, unsigned short *fctrl; struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); struct wifidirect_info *pwdinfo = &(padapter->wdinfo); u8 *frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); @@ -4988,7 +6391,7 @@ static s32 cfg80211_rtw_update_ft_ies(struct wiphy *wiphy, { _adapter *padapter = NULL; struct mlme_priv *pmlmepriv = NULL; - ft_priv *pftpriv = NULL; + struct ft_roam_info *pft_roam = NULL; _irqL irqL; u8 *p; u8 *pie = NULL; @@ -4999,24 +6402,22 @@ static s32 cfg80211_rtw_update_ft_ies(struct wiphy *wiphy, padapter = (_adapter *)rtw_netdev_priv(ndev); pmlmepriv = &(padapter->mlmepriv); - pftpriv = &pmlmepriv->ftpriv; + pft_roam = &(pmlmepriv->ft_roam); p = (u8 *)ftie->ie; - if (ftie->ie_len <= sizeof(pftpriv->updated_ft_ies)) { + if (ftie->ie_len <= sizeof(pft_roam->updated_ft_ies)) { _enter_critical_bh(&pmlmepriv->lock, &irqL); - _rtw_memcpy(pftpriv->updated_ft_ies, ftie->ie, ftie->ie_len); - pftpriv->updated_ft_ies_len = ftie->ie_len; + _rtw_memcpy(pft_roam->updated_ft_ies, ftie->ie, ftie->ie_len); + pft_roam->updated_ft_ies_len = ftie->ie_len; _exit_critical_bh(&pmlmepriv->lock, &irqL); } else { RTW_ERR("FTIEs parsing fail!\n"); return -EINVAL; } - if ((rtw_to_roam(padapter) > 0) && rtw_chk_ft_status(padapter, RTW_FT_AUTHENTICATED_STA)) { + if (rtw_ft_roam_status(padapter, RTW_FT_AUTHENTICATED_STA)) { RTW_PRINT("auth success, start reassoc\n"); - _enter_critical_bh(&pmlmepriv->lock, &irqL); - rtw_set_ft_status(padapter, RTW_FT_ASSOCIATING_STA); - _exit_critical_bh(&pmlmepriv->lock, &irqL); + rtw_ft_lock_set_status(padapter, RTW_FT_ASSOCIATING_STA, &irqL); start_clnt_assoc(padapter); } @@ -5035,6 +6436,24 @@ inline bool rtw_cfg80211_get_is_roch(_adapter *adapter) return adapter->cfg80211_wdinfo.is_ro_ch; } +inline bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter) +{ + return adapter->cfg80211_wdinfo.last_ro_ch_time ? 1 : 0; +} + +inline void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter) +{ + adapter->cfg80211_wdinfo.last_ro_ch_time = rtw_get_current_time(); + + if (!adapter->cfg80211_wdinfo.last_ro_ch_time) + adapter->cfg80211_wdinfo.last_ro_ch_time++; +} + +inline s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter) +{ + return rtw_get_passing_time_ms(adapter->cfg80211_wdinfo.last_ro_ch_time); +} + static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) struct wireless_dev *wdev, @@ -5049,21 +6468,12 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, { s32 err = 0; u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq); - u8 union_ch = 0, union_bw = 0, union_offset = 0; - u8 i; - u8 ready_on_channel = _FALSE; _adapter *padapter = NULL; - _adapter *iface; - struct dvobj_priv *dvobj; struct rtw_wdev_priv *pwdev_priv; - struct mlme_ext_priv *pmlmeext; struct wifidirect_info *pwdinfo; struct cfg80211_wifidirect_info *pcfg80211_wdinfo; +#ifdef CONFIG_CONCURRENT_MODE u8 is_p2p_find = _FALSE; - -#ifndef CONFIG_RADIO_WORK -#define RTW_ROCH_DURATION_ENLARGE -#define RTW_ROCH_BACK_OP #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) @@ -5089,9 +6499,7 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, wdev = ndev_to_wdev(ndev); #endif - dvobj = adapter_to_dvobj(padapter); pwdev_priv = adapter_wdev_data(padapter); - pmlmeext = &padapter->mlmeextpriv; pwdinfo = &padapter->wdinfo; pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; #ifdef CONFIG_CONCURRENT_MODE @@ -5104,14 +6512,14 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, , FUNC_ADPT_ARG(padapter), wdev == wiphy_to_pd_wdev(wiphy) ? " PD" : "" , remain_ch, duration, *cookie); - if (rtw_chset_search_ch(pmlmeext->channel_set, remain_ch) < 0) { + if (rtw_chset_search_ch(adapter_to_chset(padapter), remain_ch) < 0) { RTW_WARN(FUNC_ADPT_FMT" invalid ch:%u\n", FUNC_ADPT_ARG(padapter), remain_ch); err = -EFAULT; goto exit; } #ifdef CONFIG_MP_INCLUDED - if (rtw_mi_mp_mode_check(padapter)) { + if (rtw_mp_mode_check(padapter)) { RTW_INFO("MP mode block remain_on_channel request\n"); err = -EFAULT; goto exit; @@ -5142,7 +6550,7 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, RTW_INFO(FUNC_ADPT_FMT" init listen_channel %u\n" , FUNC_ADPT_ARG(padapter), padapter->wdinfo.listen_channel); } else if (rtw_p2p_chk_state(pwdinfo , P2P_STATE_LISTEN) - && (time_after_eq((unsigned long)rtw_get_current_time(), (unsigned long)pwdev_priv->probe_resp_ie_update_time) + && (time_after_eq(rtw_get_current_time(), pwdev_priv->probe_resp_ie_update_time) && rtw_get_passing_time_ms(pwdev_priv->probe_resp_ie_update_time) < 50) ) { if (padapter->wdinfo.listen_channel != remain_ch) { @@ -5152,17 +6560,9 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, } } else { rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); - #ifdef CONFIG_DEBUG_CFG80211 +#ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); - #endif - } - - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS) == _TRUE) { - RTW_INFO(ADPT_FMT"- _FW_UNDER_LINKING |WIFI_UNDER_WPS (mlme state:0x%x)\n", ADPT_ARG(iface), get_fwstate(&iface->mlmepriv)); - remain_ch = iface->mlmeextpriv.cur_channel; - } +#endif } rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); @@ -5184,60 +6584,17 @@ static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, rtw_cfg80211_set_is_roch(padapter, _TRUE); pcfg80211_wdinfo->ro_ch_wdev = wdev; pcfg80211_wdinfo->remain_on_ch_cookie = *cookie; - pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); + rtw_cfg80211_set_last_ro_ch_time(padapter); _rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel)); #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) pcfg80211_wdinfo->remain_on_ch_type = channel_type; #endif pcfg80211_wdinfo->restore_channel = rtw_get_oper_ch(padapter); -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED) && (0 != rtw_mi_get_union_chan(padapter))) { - if ((remain_ch != rtw_mi_get_union_chan(padapter)) && !check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { - if (ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1 || - (remain_ch != pmlmeext->cur_channel)) { - - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); - ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); - - #ifdef RTW_ROCH_BACK_OP - RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, duration - pwdinfo->ext_listen_interval); - _set_timer(&pwdinfo->ap_p2p_switch_timer, duration - pwdinfo->ext_listen_interval); - #endif - } - } - ready_on_channel = _TRUE; - } else -#endif /* CONFIG_CONCURRENT_MODE */ - { - if (remain_ch != rtw_get_oper_ch(padapter)) - ready_on_channel = _TRUE; - } - - if (ready_on_channel == _TRUE) { - #ifndef RTW_SINGLE_WIPHY - if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) - #endif - { - #ifdef CONFIG_CONCURRENT_MODE - if (rtw_get_oper_ch(padapter) != remain_ch) - #endif - { - /* if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) */ - set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - } - } - } - -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_ScanNotify(padapter, _TRUE); -#endif - - RTW_INFO("%s, set ro ch timer, duration=%d\n", __func__, duration); - _set_timer(&pcfg80211_wdinfo->remain_on_ch_timer, duration); + p2p_roch_cmd(padapter, *cookie, wdev, channel, pcfg80211_wdinfo->remain_on_ch_type, + duration, RTW_CMDF_WAIT_ACK); rtw_cfg80211_ready_on_channel(wdev, *cookie, channel, channel_type, duration, GFP_KERNEL); - exit: return err; } @@ -5298,9 +6655,6 @@ static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy, inline int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter) { - struct wiphy *wiphy = adapter_to_wiphy(adapter); - struct rtw_wdev_priv *wdev_data = adapter_wdev_data(adapter); - #if RTW_P2P_GROUP_INTERFACE if (is_primary_adapter(adapter)) return 0; @@ -5497,18 +6851,19 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const int ret = _FAIL; bool ack = _TRUE; struct rtw_ieee80211_hdr *pwlanhdr; +#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE) struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); +#endif struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - + u8 u_ch = rtw_mi_get_union_chan(padapter); + u8 leave_op = 0; #ifdef CONFIG_P2P + struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; + #ifdef CONFIG_CONCURRENT_MODE struct wifidirect_info *pwdinfo = &padapter->wdinfo; -#endif /* CONFIG_P2P */ - /* struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; */ - - rtw_mi_set_scan_deny(padapter, 1000); - rtw_mi_scan_abort(padapter, _TRUE); + #endif +#endif rtw_cfg80211_set_is_mgmt_tx(padapter, 1); @@ -5535,46 +6890,31 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const } #endif /* CONFIG_MCC_MODE */ -#ifdef CONFIG_CONCURRENT_MODE - if (rtw_mi_check_status(padapter, MI_LINKED)) { - u8 union_ch = rtw_mi_get_union_chan(padapter); - u8 co_channel = 0xff; - co_channel = rtw_get_oper_ch(padapter); + if (rtw_mi_check_status(padapter, MI_LINKED) + && tx_ch != u_ch + ) { + rtw_leave_opch(padapter); + leave_op = 1; - if (tx_ch != union_ch) { + #if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE) + if (rtw_cfg80211_get_is_roch(padapter) + && ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1 + ) { u16 ext_listen_period; - if (ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1) { - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); - ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); - /* RTW_INFO("%s, set switch ch timer, period=%d\n", __func__, pwdinfo->ext_listen_period); */ - /* _set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period); */ - } - if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) - ext_listen_period = 500;/*500ms*/ -#ifdef CONFIG_P2P + ext_listen_period = 500; else ext_listen_period = pwdinfo->ext_listen_period; - + ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); _set_timer(&pwdinfo->ap_p2p_switch_timer, ext_listen_period); -#endif RTW_INFO("%s, set switch ch timer, period=%d\n", __func__, ext_listen_period); } + #endif /* RTW_ROCH_BACK_OP && CONFIG_P2P && CONFIG_CONCURRENT_MODE */ + } - if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) - pmlmeext->cur_channel = tx_ch; - - if (tx_ch != co_channel) - set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - } else -#endif /* CONFIG_CONCURRENT_MODE */ - /* if (tx_ch != pmlmeext->cur_channel) { */ - if (tx_ch != rtw_get_oper_ch(padapter)) { - if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) - pmlmeext->cur_channel = tx_ch; + if (tx_ch != rtw_get_oper_ch(padapter)) set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); - } issue_mgmt_frame: /* starting alloc mgmt frame to dump it */ @@ -5627,7 +6967,8 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const } else { #ifdef CONFIG_XMIT_ACK - rtw_msleep_os(50); + if (!MLME_IS_MESH(padapter)) /* TODO: remove this sleep for all mode */ + rtw_msleep_os(50); #endif #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO("%s, ack=%d, ok!\n", __func__, ack); @@ -5638,7 +6979,29 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const dump_mgntframe(padapter, pmgntframe); ret = _SUCCESS; } + exit: + #ifdef CONFIG_P2P + if (rtw_cfg80211_get_is_roch(padapter) + && !roch_stay_in_cur_chan(padapter) + && pcfg80211_wdinfo->remain_on_ch_channel.hw_value != u_ch + ) { + /* roch is ongoing, switch back to rch */ + if (pcfg80211_wdinfo->remain_on_ch_channel.hw_value != tx_ch) + set_channel_bwmode(padapter, pcfg80211_wdinfo->remain_on_ch_channel.hw_value + , HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } else + #endif + if (leave_op) { + if (rtw_mi_check_status(padapter, MI_LINKED)) { + u8 u_bw = rtw_mi_get_union_bw(padapter); + u8 u_offset = rtw_mi_get_union_offset(padapter); + + set_channel_bwmode(padapter, u_ch, u_offset, u_bw); + } + rtw_back_opch(padapter); + } + rtw_cfg80211_set_is_mgmt_tx(padapter, 0); #ifdef CONFIG_BT_COEXIST @@ -5653,6 +7016,18 @@ static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, u8 no_cck, const } +u8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf) +{ + u8 rst = H2C_CMD_FAIL; + struct mgnt_tx_parm *mgnt_parm = (struct mgnt_tx_parm *)buf; + + if (_cfg80211_rtw_mgmt_tx(adapter, mgnt_parm->tx_ch, mgnt_parm->no_cck, + mgnt_parm->buf, mgnt_parm->len, mgnt_parm->wait_ack) == _SUCCESS) + rst = H2C_SUCCESS; + + return rst; +} + static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) struct wireless_dev *wdev, @@ -5687,30 +7062,35 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(COMPAT_KERNEL_RELEASE) struct ieee80211_channel *chan = params->chan; - bool offchan = params->offchan; - unsigned int wait = params->wait; const u8 *buf = params->buf; size_t len = params->len; bool no_cck = params->no_cck; - bool dont_wait_for_ack = params->dont_wait_for_ack; #endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 2, 0)) bool no_cck = 0; #endif int ret = 0; - int tx_ret; + u8 tx_ret; int wait_ack = 1; + const u8 *dump_buf = buf; + size_t dump_len = len; u32 dump_limit = RTW_MAX_MGMT_TX_CNT; u32 dump_cnt = 0; + u32 sleep_ms = 0; + u32 retry_guarantee_ms = 0; bool ack = _TRUE; u8 tx_ch; u8 category, action; u8 frame_styp; +#ifdef CONFIG_P2P + u8 is_p2p = 0; +#endif int type = (-1); - u32 start = rtw_get_current_time(); + systime start = rtw_get_current_time(); _adapter *padapter; struct dvobj_priv *dvobj; struct rtw_wdev_priv *pwdev_priv; + struct rf_ctl_t *rfctl; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) #if defined(RTW_DEDICATED_P2P_DEVICE) @@ -5740,13 +7120,22 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, goto exit; } + rfctl = adapter_to_rfctl(padapter); tx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq); + if (IS_CH_WAITING(rfctl)) { + #ifdef CONFIG_DFS_MASTER + if (_rtw_rfctl_overlap_radar_detect_ch(rfctl, tx_ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE)) { + ret = -EINVAL; + goto exit; + } + #endif + } dvobj = adapter_to_dvobj(padapter); pwdev_priv = adapter_wdev_data(padapter); /* cookie generation */ - *cookie = (unsigned long) buf; + *cookie = pwdev_priv->mgmt_tx_cookie++; #ifdef CONFIG_DEBUG_CFG80211 RTW_INFO(FUNC_ADPT_FMT"%s len=%zu, ch=%d" @@ -5782,9 +7171,18 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, wait_ack = 0; goto dump; } +#ifdef CONFIG_RTW_MESH + else if (frame_styp == RTW_IEEE80211_STYPE_AUTH) { + RTW_INFO("RTW_Tx:tx_ch=%d, no_cck=%u, da="MAC_FMT"\n", tx_ch, no_cck, MAC_ARG(GetAddr1Ptr(buf))); + if (!rtw_sae_check_frames(padapter, buf, len, _TRUE)) + RTW_INFO("RTW_Tx:AUTH\n"); + dump_limit = 1; + goto dump; + } +#endif if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) { - RTW_INFO(FUNC_ADPT_FMT" frame_control:0x%x\n", FUNC_ADPT_ARG(padapter), + RTW_INFO(FUNC_ADPT_FMT" frame_control:0x%02x\n", FUNC_ADPT_ARG(padapter), le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl)); goto exit; } @@ -5793,12 +7191,34 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, #ifdef CONFIG_P2P type = rtw_p2p_check_frames(padapter, buf, len, _TRUE); if (type >= 0) { + is_p2p = 1; no_cck = 1; /* force no CCK for P2P frames */ goto dump; } #endif - if (category == RTW_WLAN_CATEGORY_PUBLIC) +#ifdef CONFIG_RTW_MESH + if (MLME_IS_MESH(padapter)) { + type = rtw_mesh_check_frames_tx(padapter, &dump_buf, &dump_len); + if (type >= 0) { + dump_limit = 1; + goto dump; + } + } +#endif + if (category == RTW_WLAN_CATEGORY_PUBLIC) { RTW_INFO("RTW_Tx:%s\n", action_public_str(action)); + switch (action) { + case ACT_PUBLIC_GAS_INITIAL_REQ: + case ACT_PUBLIC_GAS_INITIAL_RSP: + sleep_ms = 50; + retry_guarantee_ms = RTW_MAX_MGMT_TX_MS_GAS; + break; + } + } +#ifdef CONFIG_RTW_80211K + else if (category == RTW_WLAN_CATEGORY_RADIO_MEAS) + RTW_INFO("RTW_Tx: RRM Action\n"); +#endif else RTW_INFO("RTW_Tx:category(%u), action(%u)\n", category, action); @@ -5811,19 +7231,11 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, } while (1) { - u32 sleep_ms = 0; - u32 retry_guarantee_ms = 0; - dump_cnt++; - tx_ret = _cfg80211_rtw_mgmt_tx(padapter, tx_ch, no_cck, buf, len, wait_ack); - - switch (action) { - case ACT_PUBLIC_GAS_INITIAL_REQ: - case ACT_PUBLIC_GAS_INITIAL_RSP: - sleep_ms = 50; - retry_guarantee_ms = RTW_MAX_MGMT_TX_MS_GAS; - } + rtw_mi_set_scan_deny(padapter, 1000); + rtw_mi_scan_abort(padapter, _TRUE); + tx_ret = rtw_mgnt_tx_cmd(padapter, tx_ch, no_cck, dump_buf, dump_len, wait_ack, RTW_CMDF_WAIT_ACK); if (tx_ret == _SUCCESS || (dump_cnt >= dump_limit && rtw_get_passing_time_ms(start) >= retry_guarantee_ms)) break; @@ -5837,44 +7249,52 @@ static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, tx_ret == _SUCCESS ? "OK" : "FAIL", dump_cnt, dump_limit, rtw_get_passing_time_ms(start)); } - switch (type) { - case P2P_GO_NEGO_CONF: - if (0) { - RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n" - , FUNC_ADPT_ARG(padapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status - , MAC_ARG(pwdev_priv->nego_info.iface_addr)); - } - if (pwdev_priv->nego_info.state == 2 - && pwdev_priv->nego_info.status == 0 - && rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE - ) { - _adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr); - - if (intended_iface) { - RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n" - , FUNC_ADPT_ARG(padapter), ADPT_ARG(intended_iface)); - /* allow only intended_iface to do scan for 2000 ms */ - rtw_mi_set_scan_deny(padapter, 2000); - rtw_clear_scan_deny(intended_iface); +#ifdef CONFIG_P2P + if (is_p2p) { + switch (type) { + case P2P_GO_NEGO_CONF: + if (0) { + RTW_INFO(FUNC_ADPT_FMT" Nego confirm. state=%u, status=%u, iaddr="MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), pwdev_priv->nego_info.state, pwdev_priv->nego_info.status + , MAC_ARG(pwdev_priv->nego_info.iface_addr)); } + if (pwdev_priv->nego_info.state == 2 + && pwdev_priv->nego_info.status == 0 + && rtw_check_invalid_mac_address(pwdev_priv->nego_info.iface_addr, _FALSE) == _FALSE + ) { + _adapter *intended_iface = dvobj_get_adapter_by_addr(dvobj, pwdev_priv->nego_info.iface_addr); + + if (intended_iface) { + RTW_INFO(FUNC_ADPT_FMT" Nego confirm. Allow only "ADPT_FMT" to scan for 2000 ms\n" + , FUNC_ADPT_ARG(padapter), ADPT_ARG(intended_iface)); + /* allow only intended_iface to do scan for 2000 ms */ + rtw_mi_set_scan_deny(padapter, 2000); + rtw_clear_scan_deny(intended_iface); + } + } + break; + case P2P_INVIT_RESP: + if (pwdev_priv->invit_info.flags & BIT(0) + && pwdev_priv->invit_info.status == 0 + ) { + rtw_clear_scan_deny(padapter); + RTW_INFO(FUNC_ADPT_FMT" agree with invitation of persistent group\n", + FUNC_ADPT_ARG(padapter)); + #if !RTW_P2P_GROUP_INTERFACE + rtw_mi_buddy_set_scan_deny(padapter, 5000); + #endif + rtw_pwr_wakeup_ex(padapter, 5000); + } + break; } - break; - case P2P_INVIT_RESP: - if (pwdev_priv->invit_info.flags & BIT(0) - && pwdev_priv->invit_info.status == 0 - ) { - RTW_INFO(FUNC_ADPT_FMT" agree with invitation of persistent group\n", - FUNC_ADPT_ARG(padapter)); - #if !RTW_P2P_GROUP_INTERFACE - rtw_mi_buddy_set_scan_deny(padapter, 5000); - #endif - rtw_pwr_wakeup_ex(padapter, 5000); - } - break; } +#endif /* CONFIG_P2P */ cancel_ps_deny: rtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX); + + if (dump_buf != buf) + rtw_mfree((u8 *)dump_buf, dump_len); exit: return ret; } @@ -5954,6 +7374,11 @@ static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy, goto discard; } + if (rtw_is_tdls_enabled(padapter) == _FALSE) { + RTW_INFO("TDLS is not enabled\n"); + goto discard; + } + if (rtw_tdls_is_driver_setup(padapter)) { RTW_INFO("Discard tdls action:%d, let driver to set up direct link\n", action_code); goto discard; @@ -6007,94 +7432,1082 @@ static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy, break; } -bad: - if (txmgmt.buf) - rtw_mfree(txmgmt.buf, txmgmt.len); +bad: + if (txmgmt.buf) + rtw_mfree(txmgmt.buf, txmgmt.len); + +discard: + return ret; +} + +static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy, + struct net_device *ndev, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + const u8 *peer, +#else + u8 *peer, +#endif + enum nl80211_tdls_operation oper) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct tdls_txmgmt txmgmt; + struct sta_info *ptdls_sta = NULL; + + RTW_INFO(FUNC_NDEV_FMT", nl80211_tdls_operation:%d\n", FUNC_NDEV_ARG(ndev), oper); + + if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { + RTW_INFO("Discard tdls oper:%d, since hal doesn't support tdls\n", oper); + return 0; + } + + if (rtw_is_tdls_enabled(padapter) == _FALSE) { + RTW_INFO("TDLS is not enabled\n"); + return 0; + } + +#ifdef CONFIG_LPS + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); +#endif /* CONFIG_LPS */ + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + if (peer) + _rtw_memcpy(txmgmt.peer, peer, ETH_ALEN); + + if (rtw_tdls_is_driver_setup(padapter)) { + /* these two cases are done by driver itself */ + if (oper == NL80211_TDLS_ENABLE_LINK || oper == NL80211_TDLS_DISABLE_LINK) + return 0; + } + + switch (oper) { + case NL80211_TDLS_DISCOVERY_REQ: + issue_tdls_dis_req(padapter, &txmgmt); + break; + case NL80211_TDLS_SETUP: +#ifdef CONFIG_WFD + if (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) { + if (padapter->wdinfo.wfd_tdls_weaksec == _TRUE) + issue_tdls_setup_req(padapter, &txmgmt, _TRUE); + else + RTW_INFO("[%s] Current link is not AES, SKIP sending the tdls setup request!!\n", __FUNCTION__); + } else +#endif /* CONFIG_WFD */ + { + issue_tdls_setup_req(padapter, &txmgmt, _TRUE); + } + break; + case NL80211_TDLS_TEARDOWN: + ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer); + if (ptdls_sta != NULL) { + txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; + issue_tdls_teardown(padapter, &txmgmt, _TRUE); + } else + RTW_INFO("TDLS peer not found\n"); + break; + case NL80211_TDLS_ENABLE_LINK: + RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_ENABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer)); + ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer); + if (ptdls_sta != NULL) { + rtw_tdls_set_link_established(padapter, _TRUE); + ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; + ptdls_sta->state |= _FW_LINKED; + rtw_tdls_cmd(padapter, txmgmt.peer, TDLS_ESTABLISHED); + } + break; + case NL80211_TDLS_DISABLE_LINK: + RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_DISABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer)); + ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer); + if (ptdls_sta != NULL) { + rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta); + rtw_tdls_cmd(padapter, (u8 *)peer, TDLS_TEARDOWN_STA_LOCALLY_POST); + } + break; + } + return 0; +} +#endif /* CONFIG_TDLS */ + +#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) + +#if DBG_RTW_CFG80211_MESH_CONF +#define LEGACY_RATES_STR_LEN (RTW_G_RATES_NUM * 5 + 1) +int get_legacy_rates_str(struct wiphy *wiphy, enum nl80211_band band, u32 mask, char *buf) +{ + int i; + int cnt = 0; + + for (i = 0; i < wiphy->bands[band]->n_bitrates; i++) { + if (mask & BIT(i)) { + cnt += snprintf(buf + cnt, LEGACY_RATES_STR_LEN - cnt -1, "%d.%d " + , wiphy->bands[band]->bitrates[i].bitrate / 10 + , wiphy->bands[band]->bitrates[i].bitrate % 10); + if (cnt >= LEGACY_RATES_STR_LEN - 1) + break; + } + } + + return cnt; +} + +void dump_mesh_setup(void *sel, struct wiphy *wiphy, const struct mesh_setup *setup) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef); +#endif + struct ieee80211_channel *chan; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + chan = (struct ieee80211_channel *)chdef->chan; +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + chan = (struct ieee80211_channel *)setup->channel; +#endif + + RTW_PRINT_SEL(sel, "mesh_id:\"%s\", len:%u\n", setup->mesh_id, setup->mesh_id_len); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + RTW_PRINT_SEL(sel, "sync_method:%u\n", setup->sync_method); +#endif + RTW_PRINT_SEL(sel, "path_sel_proto:%u, path_metric:%u\n", setup->path_sel_proto, setup->path_metric); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + RTW_PRINT_SEL(sel, "auth_id:%u\n", setup->auth_id); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + if (setup->ie && setup->ie_len) { + RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->ie, setup->ie_len); + dump_ies(RTW_DBGDUMP, setup->ie, setup->ie_len); + } +#else + if (setup->vendor_ie && setup->vendor_ie_len) { + RTW_PRINT_SEL(sel, "ie:%p, len:%u\n", setup->vendor_ie, setup->vendor_ie_len); + dump_ies(RTW_DBGDUMP, setup->vendor_ie, setup->vendor_ie_len); + } +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + RTW_PRINT_SEL(sel, "is_authenticated:%d, is_secure:%d\n", setup->is_authenticated, setup->is_secure); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + RTW_PRINT_SEL(sel, "user_mpm:%d\n", setup->user_mpm); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + RTW_PRINT_SEL(sel, "dtim_period:%u, beacon_interval:%u\n", setup->dtim_period, setup->beacon_interval); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, width:%s, cfreq1:%u, cfreq2:%u\n" + , chan->center_freq, chan->hw_value, nl80211_chan_width_str(chdef->width), chdef->center_freq1, chdef->center_freq2); +#else + RTW_PRINT_SEL(sel, "center_freq:%u, ch:%u, channel_type:%s\n" + , chan->center_freq, chan->hw_value, nl80211_channel_type_str(setup->channel_type)); +#endif +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + if (setup->mcast_rate[chan->band]) { + RTW_PRINT_SEL(sel, "mcast_rate:%d.%d\n" + , wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate / 10 + , wiphy->bands[chan->band]->bitrates[setup->mcast_rate[chan->band] - 1].bitrate % 10 + ); + } +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + if (setup->basic_rates) { + char buf[LEGACY_RATES_STR_LEN] = {0}; + + get_legacy_rates_str(wiphy, chan->band, setup->basic_rates, buf); + RTW_PRINT_SEL(sel, "basic_rates:%s\n", buf); + } +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)) + if (setup->beacon_rate.control[chan->band].legacy) { + char buf[LEGACY_RATES_STR_LEN] = {0}; + + get_legacy_rates_str(wiphy, chan->band, setup->beacon_rate.control[chan->band].legacy, buf); + RTW_PRINT_SEL(sel, "beacon_rate.legacy:%s\n", buf); + } + if (*((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[0])) + || *((u32 *)&(setup->beacon_rate.control[chan->band].ht_mcs[4])) + || *((u16 *)&(setup->beacon_rate.control[chan->band].ht_mcs[8])) + ) { + RTW_PRINT_SEL(sel, "beacon_rate.ht_mcs:"HT_RX_MCS_BMP_FMT"\n" + , HT_RX_MCS_BMP_ARG(setup->beacon_rate.control[chan->band].ht_mcs)); + } + + if (setup->beacon_rate.control[chan->band].vht_mcs[0] + || setup->beacon_rate.control[chan->band].vht_mcs[1] + || setup->beacon_rate.control[chan->band].vht_mcs[2] + || setup->beacon_rate.control[chan->band].vht_mcs[3] + ) { + int i; + + for (i = 0; i < 4; i++) {/* parsing up to 4SS */ + u16 mcs_mask = setup->beacon_rate.control[chan->band].vht_mcs[i]; + + RTW_PRINT_SEL(sel, "beacon_rate.vht_mcs[%d]:%s\n", i + , mcs_mask == 0x00FF ? "0~7" : mcs_mask == 0x01FF ? "0~8" : mcs_mask == 0x03FF ? "0~9" : "invalid"); + } + } + + if (setup->beacon_rate.control[chan->band].gi) { + RTW_PRINT_SEL(sel, "beacon_rate.gi:%s\n" + , setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_SGI ? "SGI" : + setup->beacon_rate.control[chan->band].gi == NL80211_TXRATE_FORCE_LGI ? "LGI" : "invalid" + ); + } +#endif +} + +void dump_mesh_config(void *sel, const struct mesh_config *conf) +{ + RTW_PRINT_SEL(sel, "dot11MeshRetryTimeout:%u\n", conf->dot11MeshRetryTimeout); + RTW_PRINT_SEL(sel, "dot11MeshConfirmTimeout:%u\n", conf->dot11MeshConfirmTimeout); + RTW_PRINT_SEL(sel, "dot11MeshHoldingTimeout:%u\n", conf->dot11MeshHoldingTimeout); + RTW_PRINT_SEL(sel, "dot11MeshMaxPeerLinks:%u\n", conf->dot11MeshMaxPeerLinks); + RTW_PRINT_SEL(sel, "dot11MeshMaxRetries:%u\n", conf->dot11MeshMaxRetries); + RTW_PRINT_SEL(sel, "dot11MeshTTL:%u\n", conf->dot11MeshTTL); + RTW_PRINT_SEL(sel, "element_ttl:%u\n", conf->element_ttl); + RTW_PRINT_SEL(sel, "auto_open_plinks:%d\n", conf->auto_open_plinks); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + RTW_PRINT_SEL(sel, "dot11MeshNbrOffsetMaxNeighbor:%u\n", conf->dot11MeshNbrOffsetMaxNeighbor); +#endif + + RTW_PRINT_SEL(sel, "dot11MeshHWMPmaxPREQretries:%u\n", conf->dot11MeshHWMPmaxPREQretries); + RTW_PRINT_SEL(sel, "path_refresh_time:%u\n", conf->path_refresh_time); + RTW_PRINT_SEL(sel, "min_discovery_timeout:%u\n", conf->min_discovery_timeout); + RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathTimeout:%u\n", conf->dot11MeshHWMPactivePathTimeout); + RTW_PRINT_SEL(sel, "dot11MeshHWMPpreqMinInterval:%u\n", conf->dot11MeshHWMPpreqMinInterval); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + RTW_PRINT_SEL(sel, "dot11MeshHWMPperrMinInterval:%u\n", conf->dot11MeshHWMPperrMinInterval); +#endif + RTW_PRINT_SEL(sel, "dot11MeshHWMPnetDiameterTraversalTime:%u\n", conf->dot11MeshHWMPnetDiameterTraversalTime); + RTW_PRINT_SEL(sel, "dot11MeshHWMPRootMode:%u\n", conf->dot11MeshHWMPRootMode); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + RTW_PRINT_SEL(sel, "dot11MeshHWMPRannInterval:%u\n", conf->dot11MeshHWMPRannInterval); + RTW_PRINT_SEL(sel, "dot11MeshGateAnnouncementProtocol:%d\n", conf->dot11MeshGateAnnouncementProtocol); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) + RTW_PRINT_SEL(sel, "dot11MeshForwarding:%d\n", conf->dot11MeshForwarding); + RTW_PRINT_SEL(sel, "rssi_threshold:%d\n", conf->rssi_threshold); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + RTW_PRINT_SEL(sel, "ht_opmode:0x%04x\n", conf->ht_opmode); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + RTW_PRINT_SEL(sel, "dot11MeshHWMPactivePathToRootTimeout:%u\n", conf->dot11MeshHWMPactivePathToRootTimeout); + RTW_PRINT_SEL(sel, "dot11MeshHWMProotInterval:%u\n", conf->dot11MeshHWMProotInterval); + RTW_PRINT_SEL(sel, "dot11MeshHWMPconfirmationInterval:%u\n", conf->dot11MeshHWMPconfirmationInterval); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + RTW_PRINT_SEL(sel, "power_mode:%s\n", nl80211_mesh_power_mode_str(conf->power_mode)); + RTW_PRINT_SEL(sel, "dot11MeshAwakeWindowDuration:%u\n", conf->dot11MeshAwakeWindowDuration); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + RTW_PRINT_SEL(sel, "plink_timeout:%u\n", conf->plink_timeout); +#endif +} +#endif /* DBG_RTW_CFG80211_MESH_CONF */ + +static void rtw_cfg80211_mesh_info_set_profile(struct rtw_mesh_info *minfo, const struct mesh_setup *setup) +{ + _rtw_memcpy(minfo->mesh_id, setup->mesh_id, setup->mesh_id_len); + minfo->mesh_id_len = setup->mesh_id_len; + minfo->mesh_pp_id = setup->path_sel_proto; + minfo->mesh_pm_id = setup->path_metric; + minfo->mesh_cc_id = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + minfo->mesh_sp_id = setup->sync_method; +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + minfo->mesh_auth_id = setup->auth_id; +#else + if (setup->is_authenticated) { + u8 *rsn_ie; + sint rsn_ie_len; + struct rsne_info info; + u8 *akm; + u8 AKM_SUITE_SAE[4] = {0x00, 0x0F, 0xAC, 0x08}; + + rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len); + if (!rsn_ie || !rsn_ie_len) { + rtw_warn_on(1); + return; + } + + if (rtw_rsne_info_parse(rsn_ie, rsn_ie_len + 2, &info) != _SUCCESS) { + rtw_warn_on(1); + return; + } + + if (!info.akm_list || !info.akm_cnt) { + rtw_warn_on(1); + return; + } + + akm = info.akm_list; + while (akm < info.akm_list + info.akm_cnt * 4) { + if (_rtw_memcmp(akm, AKM_SUITE_SAE, 4) == _TRUE) { + minfo->mesh_auth_id = 0x01; + break; + } + } + + if (!minfo->mesh_auth_id) { + rtw_warn_on(1); + return; + } + } +#endif +} + +static inline bool chk_mesh_attr(enum nl80211_meshconf_params parm, u32 mask) +{ + return (mask >> (parm - 1)) & 0x1; +} + +static void rtw_cfg80211_mesh_cfg_set(_adapter *adapter, const struct mesh_config *conf, u32 mask) +{ + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + +#if 0 /* driver MPM */ + if (chk_mesh_attr(NL80211_MESHCONF_RETRY_TIMEOUT, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_CONFIRM_TIMEOUT, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_HOLDING_TIMEOUT, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_MAX_PEER_LINKS, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_MAX_RETRIES, mask)); +#endif + + if (chk_mesh_attr(NL80211_MESHCONF_TTL, mask)) + mcfg->dot11MeshTTL = conf->dot11MeshTTL; + if (chk_mesh_attr(NL80211_MESHCONF_ELEMENT_TTL, mask)) + mcfg->element_ttl = conf->element_ttl; + +#if 0 /* driver MPM */ + if (chk_mesh_attr(NL80211_MESHCONF_AUTO_OPEN_PLINKS, mask)); +#endif + +#if 0 /* TBD: synchronization */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_SYNC_OFFSET_MAX_NEIGHBOR, mask)); +#endif +#endif + + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_MAX_PREQ_RETRIES, mask)) + mcfg->dot11MeshHWMPmaxPREQretries = conf->dot11MeshHWMPmaxPREQretries; + if (chk_mesh_attr(NL80211_MESHCONF_PATH_REFRESH_TIME, mask)) + mcfg->path_refresh_time = conf->path_refresh_time; + if (chk_mesh_attr(NL80211_MESHCONF_MIN_DISCOVERY_TIMEOUT, mask)) + mcfg->min_discovery_timeout = conf->min_discovery_timeout; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ACTIVE_PATH_TIMEOUT, mask)) + mcfg->dot11MeshHWMPactivePathTimeout = conf->dot11MeshHWMPactivePathTimeout; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PREQ_MIN_INTERVAL, mask)) + mcfg->dot11MeshHWMPpreqMinInterval = conf->dot11MeshHWMPpreqMinInterval; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PERR_MIN_INTERVAL, mask)) + mcfg->dot11MeshHWMPperrMinInterval = conf->dot11MeshHWMPperrMinInterval; +#endif + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_NET_DIAM_TRVS_TIME, mask)) + mcfg->dot11MeshHWMPnetDiameterTraversalTime = conf->dot11MeshHWMPnetDiameterTraversalTime; + + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOTMODE, mask)) + mcfg->dot11MeshHWMPRootMode = conf->dot11MeshHWMPRootMode; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_GATE_ANNOUNCEMENTS, mask)) + mcfg->dot11MeshGateAnnouncementProtocol = conf->dot11MeshGateAnnouncementProtocol; + /* our current gate annc implementation rides on root annc with gate annc bit in PREQ flags */ + if (mcfg->dot11MeshGateAnnouncementProtocol + && mcfg->dot11MeshHWMPRootMode <= RTW_IEEE80211_ROOTMODE_ROOT + ) { + mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_PROACTIVE_RANN; + RTW_INFO(ADPT_FMT" enable PROACTIVE_RANN becaue gate annc is needed\n", ADPT_ARG(adapter)); + } + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_RANN_INTERVAL, mask)) + mcfg->dot11MeshHWMPRannInterval = conf->dot11MeshHWMPRannInterval; +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_FORWARDING, mask)) + mcfg->dot11MeshForwarding = conf->dot11MeshForwarding; + + if (chk_mesh_attr(NL80211_MESHCONF_RSSI_THRESHOLD, mask)) + mcfg->rssi_threshold = conf->rssi_threshold; +#endif + +#if 0 /* controlled by driver */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_HT_OPMODE, mask)); +#endif +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_PATH_TO_ROOT_TIMEOUT, mask)) + mcfg->dot11MeshHWMPactivePathToRootTimeout = conf->dot11MeshHWMPactivePathToRootTimeout; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_ROOT_INTERVAL, mask)) + mcfg->dot11MeshHWMProotInterval = conf->dot11MeshHWMProotInterval; + if (chk_mesh_attr(NL80211_MESHCONF_HWMP_CONFIRMATION_INTERVAL, mask)) + mcfg->dot11MeshHWMPconfirmationInterval = conf->dot11MeshHWMPconfirmationInterval; +#endif + +#if 0 /* TBD */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_POWER_MODE, mask)); + if (chk_mesh_attr(NL80211_MESHCONF_AWAKE_WINDOW, mask)); +#endif +#endif + +#if 0 /* driver MPM */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + if (chk_mesh_attr(NL80211_MESHCONF_PLINK_TIMEOUT, mask)); +#endif +#endif +} + +u8 *rtw_cfg80211_construct_mesh_beacon_ies(struct wiphy *wiphy, _adapter *adapter + , const struct mesh_config *conf, const struct mesh_setup *setup + , uint *ies_len) +{ + struct rtw_mesh_info *minfo = &adapter->mesh_info; + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + struct cfg80211_chan_def *chdef = (struct cfg80211_chan_def *)(&setup->chandef); +#endif + struct ieee80211_channel *chan; + u8 ch, bw, offset; +#endif + uint len; + u8 n_bitrates; + u8 ht = 0; + u8 vht = 0; + u8 *rsn_ie = NULL; + sint rsn_ie_len = 0; + u8 *ies = NULL, *c; + u8 supported_rates[RTW_G_RATES_NUM] = {0}; + int i; + + *ies_len = 0; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + chan = (struct ieee80211_channel *)chdef->chan; +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + chan = (struct ieee80211_channel *)setup->channel; +#endif + + n_bitrates = wiphy->bands[chan->band]->n_bitrates; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + rtw_get_chbw_from_cfg80211_chan_def(chdef, &ht, &ch, &bw, &offset); +#else + rtw_get_chbw_from_nl80211_channel_type(chan, setup->channel_type, &ht, &ch, &bw, &offset); +#endif + if (!ch) + goto exit; + +#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + vht = ht && ch > 14 && bw >= CHANNEL_WIDTH_80; /* VHT40/VHT20? */ +#endif + + RTW_INFO(FUNC_ADPT_FMT" => ch:%u,%u,%u, ht:%u, vht:%u\n" + , FUNC_ADPT_ARG(adapter), ch, bw, offset, ht, vht); +#endif + + rsn_ie = rtw_get_ie(setup->ie, WLAN_EID_RSN, &rsn_ie_len, setup->ie_len); + if (rsn_ie && !rsn_ie_len) { + rtw_warn_on(1); + rsn_ie = NULL; + } + + len = _BEACON_IE_OFFSET_ + + 2 /* 0-length SSID */ + + (n_bitrates >= 8 ? 8 : n_bitrates) + 2 /* Supported Rates */ + + 3 /* DS parameter set */ + + 6 /* TIM */ + + (n_bitrates > 8 ? n_bitrates - 8 + 2 : 0) /* Extended Supported Rates */ + + (rsn_ie ? rsn_ie_len + 2 : 0) /* RSN */ + #if defined(CONFIG_80211N_HT) + + (ht ? HT_CAP_IE_LEN + 2 + HT_OP_IE_LEN + 2 : 0) /* HT */ + #endif + #if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + + (vht ? VHT_CAP_IE_LEN + 2 + VHT_OP_IE_LEN + 2 : 0) /* VHT */ + #endif + + minfo->mesh_id_len + 2 /* Mesh ID */ + + 9 /* Mesh configuration */ + ; + + ies = rtw_zmalloc(len); + if (!ies) + goto exit; + + /* timestamp */ + c = ies + 8; + + /* beacon interval */ + RTW_PUT_LE16(c , setup->beacon_interval); + c += 2; + + /* capability */ + if (rsn_ie) + *((u16 *)c) |= cpu_to_le16(cap_Privacy); + c += 2; + + /* SSID */ + c = rtw_set_ie(c, WLAN_EID_SSID, 0, NULL, NULL); + + /* Supported Rates */ + for (i = 0; i < n_bitrates; i++) { + supported_rates[i] = wiphy->bands[chan->band]->bitrates[i].bitrate / 5; + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + if (setup->basic_rates & BIT(i)) + #else + if (rtw_is_basic_rate_mix(supported_rates[i])) + #endif + supported_rates[i] |= IEEE80211_BASIC_RATE_MASK; + } + c = rtw_set_ie(c, WLAN_EID_SUPP_RATES, (n_bitrates >= 8 ? 8 : n_bitrates), supported_rates, NULL); + + /* DS parameter set */ + c = rtw_set_ie(c, WLAN_EID_DS_PARAMS, 1, &ch, NULL); + + /* TIM */ + *c = WLAN_EID_TIM; + *(c + 1) = 4; + c += 6; + //c = rtw_set_ie(c, _TIM_IE_, 4, NULL, NULL); + + /* Extended Supported Rates */ + if (n_bitrates > 8) + c = rtw_set_ie(c, WLAN_EID_EXT_SUPP_RATES, n_bitrates - 8, supported_rates + 8, NULL); + + /* RSN */ + if (rsn_ie) + c = rtw_set_ie(c, WLAN_EID_RSN, rsn_ie_len, rsn_ie + 2, NULL); + +#if defined(CONFIG_80211N_HT) + if (ht) { + struct ieee80211_sta_ht_cap *sta_ht_cap = &wiphy->bands[chan->band]->ht_cap; + u8 ht_cap[HT_CAP_IE_LEN]; + u8 ht_op[HT_OP_IE_LEN]; + + _rtw_memset(ht_cap, 0, HT_CAP_IE_LEN); + _rtw_memset(ht_op, 0, HT_OP_IE_LEN); + + /* WLAN_EID_HT_CAP */ + RTW_PUT_LE16(HT_CAP_ELE_CAP_INFO(ht_cap), sta_ht_cap->cap); + SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(ht_cap, sta_ht_cap->ampdu_factor); + SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(ht_cap, sta_ht_cap->ampdu_density); + _rtw_memcpy(HT_CAP_ELE_SUP_MCS_SET(ht_cap), &sta_ht_cap->mcs, 16); + c = rtw_set_ie(c, WLAN_EID_HT_CAP, HT_CAP_IE_LEN, ht_cap, NULL); + + /* WLAN_EID_HT_OPERATION */ + SET_HT_OP_ELE_PRI_CHL(ht_op, ch); + switch (offset) { + case HAL_PRIME_CHNL_OFFSET_LOWER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCA); + break; + case HAL_PRIME_CHNL_OFFSET_UPPER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCB); + break; + case HAL_PRIME_CHNL_OFFSET_DONT_CARE: + default: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op, SCN); + break; + } + if (bw >= CHANNEL_WIDTH_40) + SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 1); + else + SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op, 0); + c = rtw_set_ie(c, WLAN_EID_HT_OPERATION, HT_OP_IE_LEN, ht_op, NULL); + } +#endif /* defined(CONFIG_80211N_HT) */ + +#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + if (vht) { + struct ieee80211_sta_vht_cap *sta_vht_cap = &wiphy->bands[chan->band]->vht_cap; + u8 vht_cap[VHT_CAP_IE_LEN]; + u8 vht_op[VHT_OP_IE_LEN]; + u8 cch = rtw_get_center_ch(ch, bw, offset); + + _rtw_memset(vht_op, 0, VHT_OP_IE_LEN); + + /* WLAN_EID_VHT_CAPABILITY */ + _rtw_memcpy(vht_cap, &sta_vht_cap->cap, 4); + _rtw_memcpy(vht_cap + 4, &sta_vht_cap->vht_mcs, 8); + c = rtw_set_ie(c, WLAN_EID_VHT_CAPABILITY, VHT_CAP_IE_LEN, vht_cap, NULL); + + /* WLAN_EID_VHT_OPERATION */ + if (bw < CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0); + } else if (bw == CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op, 1); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op, cch); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op, 0); + } else { + RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw); + rtw_warn_on(1); + rtw_mfree(ies, len); + goto exit; + } + + /* Hard code 1 stream, MCS0-7 is a min Basic VHT MCS rates */ + vht_op[3] = 0xfc; + vht_op[4] = 0xff; + c = rtw_set_ie(c, WLAN_EID_VHT_OPERATION, VHT_OP_IE_LEN, vht_op, NULL); + } +#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */ + + /* Mesh ID */ + c = rtw_set_ie_mesh_id(c, NULL, minfo->mesh_id, minfo->mesh_id_len); + + /* Mesh configuration */ + c = rtw_set_ie_mesh_config(c, NULL + , minfo->mesh_pp_id + , minfo->mesh_pm_id + , minfo->mesh_cc_id + , minfo->mesh_sp_id + , minfo->mesh_auth_id + , 0, 0, 0 + , 1 + , 0, 0 + , mcfg->dot11MeshForwarding + , 0, 0, 0 + ); + +#if DBG_RTW_CFG80211_MESH_CONF + RTW_INFO(FUNC_ADPT_FMT" ies_len:%u\n", FUNC_ADPT_ARG(adapter), len); + dump_ies(RTW_DBGDUMP, ies + _BEACON_IE_OFFSET_, len - _BEACON_IE_OFFSET_); +#endif + +exit: + if (ies) + *ies_len = len; + return ies; +} + +static int cfg80211_rtw_get_mesh_config(struct wiphy *wiphy, struct net_device *dev + , struct mesh_config *conf) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_cfg *mesh_cfg = &adapter->mesh_cfg; + int ret = 0; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + + /* driver MPM */ + conf->dot11MeshRetryTimeout = 0; + conf->dot11MeshConfirmTimeout = 0; + conf->dot11MeshHoldingTimeout = 0; + conf->dot11MeshMaxPeerLinks = mesh_cfg->max_peer_links; + conf->dot11MeshMaxRetries = 0; + + conf->dot11MeshTTL = mesh_cfg->dot11MeshTTL; + conf->element_ttl = mesh_cfg->element_ttl; + + /* driver MPM */ + conf->auto_open_plinks = 0; + + /* TBD: synchronization */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + conf->dot11MeshNbrOffsetMaxNeighbor = 0; +#endif + + conf->dot11MeshHWMPmaxPREQretries = mesh_cfg->dot11MeshHWMPmaxPREQretries; + conf->path_refresh_time = mesh_cfg->path_refresh_time; + conf->min_discovery_timeout = mesh_cfg->min_discovery_timeout; + conf->dot11MeshHWMPactivePathTimeout = mesh_cfg->dot11MeshHWMPactivePathTimeout; + conf->dot11MeshHWMPpreqMinInterval = mesh_cfg->dot11MeshHWMPpreqMinInterval; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + conf->dot11MeshHWMPperrMinInterval = mesh_cfg->dot11MeshHWMPperrMinInterval; +#endif + conf->dot11MeshHWMPnetDiameterTraversalTime = mesh_cfg->dot11MeshHWMPnetDiameterTraversalTime; + conf->dot11MeshHWMPRootMode = mesh_cfg->dot11MeshHWMPRootMode; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) + conf->dot11MeshHWMPRannInterval = mesh_cfg->dot11MeshHWMPRannInterval; +#endif + conf->dot11MeshGateAnnouncementProtocol = mesh_cfg->dot11MeshGateAnnouncementProtocol; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)) + conf->dot11MeshForwarding = mesh_cfg->dot11MeshForwarding; + conf->rssi_threshold = mesh_cfg->rssi_threshold; +#endif + + /* TBD */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) + conf->ht_opmode = 0xffff; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + conf->dot11MeshHWMPactivePathToRootTimeout = mesh_cfg->dot11MeshHWMPactivePathToRootTimeout; + conf->dot11MeshHWMProotInterval = mesh_cfg->dot11MeshHWMProotInterval; + conf->dot11MeshHWMPconfirmationInterval = mesh_cfg->dot11MeshHWMPconfirmationInterval; +#endif + + /* TBD: power save */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)) + conf->power_mode = NL80211_MESH_POWER_ACTIVE; + conf->dot11MeshAwakeWindowDuration = 0; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + conf->plink_timeout = mesh_cfg->plink_timeout; +#endif + + return ret; +} + +static void rtw_mbss_info_change_notify(_adapter *adapter, bool minfo_changed, bool need_work) +{ + if (need_work) + rtw_mesh_work(&adapter->mesh_work); +} + +static int cfg80211_rtw_update_mesh_config(struct wiphy *wiphy, struct net_device *dev + , u32 mask, const struct mesh_config *nconf) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + int ret = 0; + bool minfo_changed = _FALSE, need_work = _FALSE; + + RTW_INFO(FUNC_ADPT_FMT" mask:0x%08x\n", FUNC_ADPT_ARG(adapter), mask); + + rtw_cfg80211_mesh_cfg_set(adapter, nconf, mask); + update_beacon(adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE); +#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER + if (rtw_mesh_cto_mgate_required(adapter)) + rtw_netif_carrier_off(adapter->pnetdev); + else + rtw_netif_carrier_on(adapter->pnetdev); +#endif + need_work = rtw_ieee80211_mesh_root_setup(adapter); + + rtw_mbss_info_change_notify(adapter, minfo_changed, need_work); + + return ret; +} + +static int cfg80211_rtw_join_mesh(struct wiphy *wiphy, struct net_device *dev, + const struct mesh_config *conf, const struct mesh_setup *setup) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 *ies = NULL; + uint ies_len; + int ret = 0; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + +#if DBG_RTW_CFG80211_MESH_CONF + RTW_INFO(FUNC_ADPT_FMT" mesh_setup:\n", FUNC_ADPT_ARG(adapter)); + dump_mesh_setup(RTW_DBGDUMP, wiphy, setup); + RTW_INFO(FUNC_ADPT_FMT" mesh_config:\n", FUNC_ADPT_ARG(adapter)); + dump_mesh_config(RTW_DBGDUMP, conf); +#endif + + if (rtw_cfg80211_sync_iftype(adapter) != _SUCCESS) { + ret = -ENOTSUPP; + goto exit; + } + + /* initialization */ + rtw_mesh_init_mesh_info(adapter); + + /* apply cfg80211 settings*/ + rtw_cfg80211_mesh_info_set_profile(&adapter->mesh_info, setup); + rtw_cfg80211_mesh_cfg_set(adapter, conf, 0xFFFFFFFF); + + /* apply cfg80211 settings (join only) */ + rtw_mesh_cfg_init_max_peer_links(adapter, conf->dot11MeshMaxPeerLinks); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + rtw_mesh_cfg_init_plink_timeout(adapter, conf->plink_timeout); + #endif + + rtw_ieee80211_mesh_root_setup(adapter); + + ies = rtw_cfg80211_construct_mesh_beacon_ies(wiphy, adapter, conf, setup, &ies_len); + if (!ies) { + ret = -EINVAL; + goto exit; + } + + /* start mbss */ + if (rtw_check_beacon_data(adapter, ies, ies_len) != _SUCCESS) { + ret = -EINVAL; + goto exit; + } + + rtw_mesh_work(&adapter->mesh_work); + +exit: + if (ies) + rtw_mfree(ies, ies_len); + if (ret) + rtw_mesh_deinit_mesh_info(adapter); + + return ret; +} + +static int cfg80211_rtw_leave_mesh(struct wiphy *wiphy, struct net_device *dev) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + int ret = 0; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + + rtw_mesh_deinit_mesh_info(adapter); + + rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11Infrastructure); + rtw_setopmode_cmd(adapter, Ndis802_11Infrastructure, RTW_CMDF_WAIT_ACK); + + return ret; +} + +static int cfg80211_rtw_add_mpath(struct wiphy *wiphy, struct net_device *dev + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + , const u8 *dst, const u8 *next_hop + #else + , u8 *dst, u8 *next_hop + #endif +) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta; + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + sta = rtw_get_stainfo(stapriv, next_hop); + if (!sta) { + ret = -ENOENT; + goto exit; + } + + mpath = rtw_mesh_path_add(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; + } + + rtw_mesh_path_fix_nexthop(mpath, sta); + +exit: + rtw_rcu_read_unlock(); + + return ret; +} + +static int cfg80211_rtw_del_mpath(struct wiphy *wiphy, struct net_device *dev + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + , const u8 *dst + #else + , u8 *dst + #endif +) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + int ret = 0; + + if (dst) { + if (rtw_mesh_path_del(adapter, dst)) { + ret = -ENOENT; + goto exit; + } + } else { + rtw_mesh_path_flush_by_iface(adapter); + } + +exit: + return ret; +} + +static int cfg80211_rtw_change_mpath(struct wiphy *wiphy, struct net_device *dev + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + , const u8 *dst, const u8 *next_hop + #else + , u8 *dst, u8 *next_hop + #endif +) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta; + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + sta = rtw_get_stainfo(stapriv, next_hop); + if (!sta) { + ret = -ENOENT; + goto exit; + } + + mpath = rtw_mesh_path_lookup(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; + } + + rtw_mesh_path_fix_nexthop(mpath, sta); + +exit: + rtw_rcu_read_unlock(); + + return ret; +} + +static void rtw_cfg80211_mpath_set_pinfo(struct rtw_mesh_path *mpath, u8 *next_hop, struct mpath_info *pinfo) +{ + struct sta_info *next_hop_sta = rtw_rcu_dereference(mpath->next_hop); + + if (next_hop_sta) + _rtw_memcpy(next_hop, next_hop_sta->cmn.mac_addr, ETH_ALEN); + else + _rtw_memset(next_hop, 0, ETH_ALEN); + + _rtw_memset(pinfo, 0, sizeof(*pinfo)); + + pinfo->generation = mpath->adapter->mesh_info.mesh_paths_generation; + + pinfo->filled = 0 + | MPATH_INFO_FRAME_QLEN + | MPATH_INFO_SN + | MPATH_INFO_METRIC + | MPATH_INFO_EXPTIME + | MPATH_INFO_DISCOVERY_TIMEOUT + | MPATH_INFO_DISCOVERY_RETRIES + | MPATH_INFO_FLAGS + ; + + pinfo->frame_qlen = mpath->frame_queue_len; + pinfo->sn = mpath->sn; + pinfo->metric = mpath->metric; + if (rtw_time_after(mpath->exp_time, rtw_get_current_time())) + pinfo->exptime = rtw_get_remaining_time_ms(mpath->exp_time); + pinfo->discovery_timeout = rtw_systime_to_ms(mpath->discovery_timeout); + pinfo->discovery_retries = mpath->discovery_retries; + if (mpath->flags & RTW_MESH_PATH_ACTIVE) + pinfo->flags |= NL80211_MPATH_FLAG_ACTIVE; + if (mpath->flags & RTW_MESH_PATH_RESOLVING) + pinfo->flags |= NL80211_MPATH_FLAG_RESOLVING; + if (mpath->flags & RTW_MESH_PATH_SN_VALID) + pinfo->flags |= NL80211_MPATH_FLAG_SN_VALID; + if (mpath->flags & RTW_MESH_PATH_FIXED) + pinfo->flags |= NL80211_MPATH_FLAG_FIXED; + if (mpath->flags & RTW_MESH_PATH_RESOLVED) + pinfo->flags |= NL80211_MPATH_FLAG_RESOLVED; +} + +static int cfg80211_rtw_get_mpath(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *next_hop, struct mpath_info *pinfo) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + mpath = rtw_mesh_path_lookup(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; + } + + rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo); + +exit: + rtw_rcu_read_unlock(); + + return ret; +} + +static int cfg80211_rtw_dump_mpath(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *next_hop, struct mpath_info *pinfo) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + mpath = rtw_mesh_path_lookup_by_idx(adapter, idx); + if (!mpath) { + ret = -ENOENT; + goto exit; + } + + _rtw_memcpy(dst, mpath->dst, ETH_ALEN); + rtw_cfg80211_mpath_set_pinfo(mpath, next_hop, pinfo); + +exit: + rtw_rcu_read_unlock(); -discard: return ret; } -static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy, - struct net_device *ndev, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) - const u8 *peer, -#else - u8 *peer, -#endif - enum nl80211_tdls_operation oper) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) +static void rtw_cfg80211_mpp_set_pinfo(struct rtw_mesh_path *mpath, u8 *mpp, struct mpath_info *pinfo) { - _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - struct tdls_txmgmt txmgmt; - struct sta_info *ptdls_sta = NULL; + _rtw_memcpy(mpp, mpath->mpp, ETH_ALEN); - RTW_INFO(FUNC_NDEV_FMT", nl80211_tdls_operation:%d\n", FUNC_NDEV_ARG(ndev), oper); + _rtw_memset(pinfo, 0, sizeof(*pinfo)); + pinfo->generation = mpath->adapter->mesh_info.mpp_paths_generation; +} - if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { - RTW_INFO("Discard tdls oper:%d, since hal doesn't support tdls\n", oper); - return 0; +static int cfg80211_rtw_get_mpp(struct wiphy *wiphy, struct net_device *dev, u8 *dst, u8 *mpp, struct mpath_info *pinfo) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + mpath = rtw_mpp_path_lookup(adapter, dst); + if (!mpath) { + ret = -ENOENT; + goto exit; } -#ifdef CONFIG_LPS - rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); -#endif /* CONFIG_LPS */ + rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo); - _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - if (peer) - _rtw_memcpy(txmgmt.peer, peer, ETH_ALEN); +exit: + rtw_rcu_read_unlock(); - if (rtw_tdls_is_driver_setup(padapter)) { - /* these two cases are done by driver itself */ - if (oper == NL80211_TDLS_ENABLE_LINK || oper == NL80211_TDLS_DISABLE_LINK) - return 0; - } + return ret; +} - switch (oper) { - case NL80211_TDLS_DISCOVERY_REQ: - issue_tdls_dis_req(padapter, &txmgmt); - break; - case NL80211_TDLS_SETUP: -#ifdef CONFIG_WFD - if (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) { - if (padapter->wdinfo.wfd_tdls_weaksec == _TRUE) - issue_tdls_setup_req(padapter, &txmgmt, _TRUE); - else - RTW_INFO("[%s] Current link is not AES, SKIP sending the tdls setup request!!\n", __FUNCTION__); - } else -#endif /* CONFIG_WFD */ - { - issue_tdls_setup_req(padapter, &txmgmt, _TRUE); - } - break; - case NL80211_TDLS_TEARDOWN: - ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), txmgmt.peer); - if (ptdls_sta != NULL) { - txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; - issue_tdls_teardown(padapter, &txmgmt, _TRUE); - } else - RTW_INFO("TDLS peer not found\n"); - break; - case NL80211_TDLS_ENABLE_LINK: - RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_ENABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer)); - ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer); - if (ptdls_sta != NULL) { - ptdlsinfo->link_established = _TRUE; - ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; - ptdls_sta->state |= _FW_LINKED; - rtw_tdls_cmd(padapter, txmgmt.peer, TDLS_ESTABLISHED); - } - break; - case NL80211_TDLS_DISABLE_LINK: - RTW_INFO(FUNC_NDEV_FMT", NL80211_TDLS_DISABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer)); - ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer); - if (ptdls_sta != NULL) - rtw_tdls_cmd(padapter, (u8 *)peer, TDLS_TEARDOWN_STA_LOCALLY); - break; +static int cfg80211_rtw_dump_mpp(struct wiphy *wiphy, struct net_device *dev, int idx, u8 *dst, u8 *mpp, struct mpath_info *pinfo) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_path *mpath; + int ret = 0; + + rtw_rcu_read_lock(); + + mpath = rtw_mpp_path_lookup_by_idx(adapter, idx); + if (!mpath) { + ret = -ENOENT; + goto exit; } - return 0; + + _rtw_memcpy(dst, mpath->dst, ETH_ALEN); + rtw_cfg80211_mpp_set_pinfo(mpath, mpp, pinfo); + +exit: + rtw_rcu_read_unlock(); + + return ret; } -#endif /* CONFIG_TDLS */ +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) */ + +#endif /* defined(CONFIG_RTW_MESH) */ #if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, @@ -6104,6 +8517,10 @@ static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct cfg80211_ssid *ssids; + int n_ssids = 0; + int interval = 0; + int i = 0; u8 ret; if (padapter->bup == _FALSE) { @@ -6122,10 +8539,31 @@ static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, RTW_INFO("%s: invalid cfg80211_requests parameters.\n", __func__); return -EINVAL; } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0) - ret = rtw_android_cfg80211_pno_setup(dev, request->ssids, - request->n_ssids, request->interval); - +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) + interval = request->scan_plans->interval; +#else + interval = request->interval; +#endif + n_ssids = request->n_match_sets; + ssids = (struct cfg80211_ssid *)rtw_zmalloc(n_ssids * sizeof(struct cfg80211_ssid)); + if(ssids == NULL) { + RTW_ERR("Fail to allocate ssids for PNO\n"); + return -ENOMEM; + } + for (i=0;in_match_sets;i++) { + ssids[i].ssid_len = request->match_sets[i].ssid.ssid_len; + memcpy(ssids[i].ssid, request->match_sets[i].ssid.ssid, + request->match_sets[i].ssid.ssid_len); + } +#else + interval = request->interval; + n_ssids = request->n_ssids; + ssids = request->ssids; +#endif +ret = rtw_android_cfg80211_pno_setup(dev, ssids, + n_ssids, interval); if (ret < 0) { RTW_INFO("%s ret: %d\n", __func__, ret); goto exit; @@ -6145,6 +8583,63 @@ static int cfg80211_rtw_sched_scan_stop(struct wiphy *wiphy, { return rtw_android_pno_enable(dev, _FALSE); } + +int cfg80211_rtw_suspend(struct wiphy *wiphy, struct cfg80211_wowlan *wow) { + RTW_DBG("==> %s\n",__func__); + RTW_DBG("<== %s\n",__func__); + return 0; +} + +int cfg80211_rtw_resume(struct wiphy *wiphy) { + + _adapter *padapter; + struct pwrctrl_priv *pwrpriv; + struct mlme_priv *pmlmepriv; + padapter = wiphy_to_adapter(wiphy); + pwrpriv = adapter_to_pwrctl(padapter); + pmlmepriv = &padapter->mlmepriv; + struct sitesurvey_parm parm; + int i, len; + + + RTW_DBG("==> %s\n",__func__); + if (pwrpriv->wowlan_last_wake_reason == RX_PNO) { + + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + _irqL irqL; + int PNOWakeupScanWaitCnt = 0; + + rtw_cfg80211_disconnected(padapter->rtw_wdev, 0, NULL, 0, 1, GFP_ATOMIC); + + rtw_init_sitesurvey_parm(padapter, &parm); + for (i=0;ipnlo_info->ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) { + len = pwrpriv->pno_ssid_list->node[i].SSID_len; + _rtw_memcpy(&parm.ssid[i].Ssid, pwrpriv->pno_ssid_list->node[i].SSID, len); + parm.ssid[i].SsidLength = len; + } + parm.ssid_num = pwrpriv->pnlo_info->ssid_num; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + //This modification fix PNO wakeup reconnect issue with hidden SSID AP. + //rtw_sitesurvey_cmd(padapter, NULL); + rtw_sitesurvey_cmd(padapter, &parm); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + for (PNOWakeupScanWaitCnt = 0; PNOWakeupScanWaitCnt < 10; PNOWakeupScanWaitCnt++) { + if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _FALSE) + break; + rtw_msleep_os(1000); + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + cfg80211_sched_scan_results(padapter->rtw_wdev->wiphy); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + } + RTW_DBG("<== %s\n",__func__); + return 0; + +} #endif /* CONFIG_PNO_SUPPORT */ static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len) @@ -6504,7 +8999,9 @@ int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, } -static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, struct ieee80211_sta_ht_cap *ht_cap, enum nl80211_band band, u8 rf_type) +#ifdef CONFIG_80211N_HT +static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter + , struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type) { struct registry_priv *pregistrypriv = &padapter->registrypriv; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -6524,9 +9021,9 @@ static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, struct ieee80211_s /* RX STBC */ if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) { /*rtw_rx_stbc 0: disable, bit(0):enable 2.4g, bit(1):enable 5g*/ - if (band == NL80211_BAND_2GHZ) + if (band == BAND_ON_2_4G) stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(0)) ? _TRUE : _FALSE; - if (band == NL80211_BAND_5GHZ) + if (band == BAND_ON_5G) stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(1)) ? _TRUE : _FALSE; if (stbc_rx_enable) { @@ -6552,12 +9049,17 @@ static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, struct ieee80211_s } } -static void rtw_cfg80211_init_ht_capab(_adapter *padapter, struct ieee80211_sta_ht_cap *ht_cap, enum nl80211_band band, u8 rf_type) +static void rtw_cfg80211_init_ht_capab(_adapter *padapter + , struct ieee80211_sta_ht_cap *ht_cap, BAND_TYPE band, u8 rf_type) { + struct registry_priv *regsty = &padapter->registrypriv; struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); u8 rx_nss = 0; - ht_cap->ht_supported = _TRUE; + if (!regsty->ht_enable || !is_supported_ht(regsty->wireless_mode)) + return; + + ht_cap->ht_supported = 1; ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20 | @@ -6600,12 +9102,34 @@ static void rtw_cfg80211_init_ht_capab(_adapter *padapter, struct ieee80211_sta_ RTW_INFO("%s, error rf_type=%d\n", __func__, rf_type); }; - ht_cap->mcs.rx_highest = rtw_mcs_rate(rf_type - , hal_is_bw_support(padapter, CHANNEL_WIDTH_40) - , hal_is_bw_support(padapter, CHANNEL_WIDTH_40) ? ht_cap->cap & IEEE80211_HT_CAP_SGI_40 : ht_cap->cap & IEEE80211_HT_CAP_SGI_20 - , ht_cap->mcs.rx_mask - ); + ht_cap->mcs.rx_highest = cpu_to_le16( + rtw_mcs_rate(rf_type + , hal_is_bw_support(padapter, CHANNEL_WIDTH_40) + , hal_is_bw_support(padapter, CHANNEL_WIDTH_40) ? ht_cap->cap & IEEE80211_HT_CAP_SGI_40 : ht_cap->cap & IEEE80211_HT_CAP_SGI_20 + , ht_cap->mcs.rx_mask) / 10); +} +#endif /* CONFIG_80211N_HT */ + +#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +static void rtw_cfg80211_init_vht_capab(_adapter *padapter + , struct ieee80211_sta_vht_cap *sta_vht_cap, BAND_TYPE band, u8 rf_type) +{ + struct registry_priv *regsty = &padapter->registrypriv; + u8 vht_cap_ie[2 + 12] = {0}; + + if (!REGSTY_IS_11AC_ENABLE(regsty) || !is_supported_vht(regsty->wireless_mode)) + return; + + rtw_vht_use_default_setting(padapter); + rtw_build_vht_cap_ie(padapter, vht_cap_ie); + + sta_vht_cap->vht_supported = 1; + + _rtw_memcpy(&sta_vht_cap->cap, vht_cap_ie + 2, 4); + _rtw_memcpy(&sta_vht_cap->vht_mcs, vht_cap_ie + 2 + 4, 8); } +#endif /* defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) */ + void rtw_cfg80211_init_wdev_data(_adapter *padapter) { #ifdef CONFIG_CONCURRENT_MODE @@ -6618,7 +9142,7 @@ void rtw_cfg80211_init_wdev_data(_adapter *padapter) void rtw_cfg80211_init_wiphy(_adapter *padapter) { u8 rf_type; - struct ieee80211_supported_band *bands; + struct ieee80211_supported_band *band; struct wireless_dev *pwdev = padapter->rtw_wdev; struct wiphy *wiphy = pwdev->wiphy; @@ -6627,19 +9151,26 @@ void rtw_cfg80211_init_wiphy(_adapter *padapter) RTW_INFO("%s:rf_type=%d\n", __func__, rf_type); if (IsSupported24G(padapter->registrypriv.wireless_mode)) { - bands = wiphy->bands[NL80211_BAND_2GHZ]; - if (bands) - rtw_cfg80211_init_ht_capab(padapter, &bands->ht_cap, NL80211_BAND_2GHZ, rf_type); + band = wiphy->bands[NL80211_BAND_2GHZ]; + if (band) { + #if defined(CONFIG_80211N_HT) + rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_2_4G, rf_type); + #endif + } } #ifdef CONFIG_IEEE80211_BAND_5GHZ if (is_supported_5g(padapter->registrypriv.wireless_mode)) { - bands = wiphy->bands[NL80211_BAND_5GHZ]; - if (bands) - rtw_cfg80211_init_ht_capab(padapter, &bands->ht_cap, NL80211_BAND_5GHZ, rf_type); + band = wiphy->bands[NL80211_BAND_5GHZ]; + if (band) { + #if defined(CONFIG_80211N_HT) + rtw_cfg80211_init_ht_capab(padapter, &band->ht_cap, BAND_ON_5G, rf_type); + #endif + #if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + rtw_cfg80211_init_vht_capab(padapter, &band->vht_cap, BAND_ON_5G, rf_type); + #endif + } } #endif - /* init regulary domain */ - rtw_regd_init(padapter); /* copy mac_addr to wiphy */ _rtw_memcpy(wiphy->perm_addr, adapter_mac_addr(padapter), ETH_ALEN); @@ -6668,7 +9199,13 @@ struct ieee80211_iface_limit rtw_limits[] = { { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) - } + }, + #endif + #if defined(CONFIG_RTW_MESH) + { + .max = 1, + .types = BIT(NL80211_IFTYPE_MESH_POINT) + }, #endif }; @@ -6719,9 +9256,19 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) #if defined(RTW_DEDICATED_P2P_DEVICE) | BIT(NL80211_IFTYPE_P2P_DEVICE) #endif +#endif +#ifdef CONFIG_RTW_MESH + | BIT(NL80211_IFTYPE_MESH_POINT) /* 2.6.26 */ #endif ; +#if defined(CONFIG_ANDROID) && !defined(RTW_SINGLE_WIPHY) + if (is_primary_adapter(adapter)) { + wiphy->interface_modes &= ~(BIT(NL80211_IFTYPE_P2P_GO) | BIT(NL80211_IFTYPE_P2P_CLIENT)); + RTW_INFO("%s primary- don't set p2p capability\n", __func__); + } +#endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) #ifdef CONFIG_AP_MODE wiphy->mgmt_stypes = rtw_cfg80211_default_mgmt_stypes; @@ -6743,11 +9290,11 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites); if (IsSupported24G(adapter->registrypriv.wireless_mode)) - wiphy->bands[NL80211_BAND_2GHZ] = rtw_spt_band_alloc(NL80211_BAND_2GHZ); + wiphy->bands[NL80211_BAND_2GHZ] = rtw_spt_band_alloc(BAND_ON_2_4G); #ifdef CONFIG_IEEE80211_BAND_5GHZ if (is_supported_5g(adapter->registrypriv.wireless_mode)) - wiphy->bands[NL80211_BAND_5GHZ] = rtw_spt_band_alloc(NL80211_BAND_5GHZ); + wiphy->bands[NL80211_BAND_5GHZ] = rtw_spt_band_alloc(BAND_ON_5G); #endif #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38) && LINUX_VERSION_CODE < KERNEL_VERSION(3, 0, 0)) @@ -6761,10 +9308,14 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) /* wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX | WIPHY_FLAG_HAVE_AP_SME; */ #endif -#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) - wiphy->max_sched_scan_reqs = 1; +#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0)) + wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN; #ifdef CONFIG_PNO_SUPPORT wiphy->max_sched_scan_ssids = MAX_PNO_LIST_COUNT; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0) + wiphy->max_match_sets = MAX_PNO_LIST_COUNT; +#endif #endif #endif @@ -6792,7 +9343,197 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)) /* wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM; */ #endif + +#ifdef CONFIG_RTW_MESH + wiphy->flags |= 0 + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + | WIPHY_FLAG_IBSS_RSN + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + | WIPHY_FLAG_MESH_AUTH + #endif + ; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) + wiphy->features |= 0 + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + | NL80211_FEATURE_USERSPACE_MPM + #endif + ; +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 3, 0)) */ +#endif /* CONFIG_RTW_MESH */ +} + +#ifdef CONFIG_RFKILL_POLL +void rtw_cfg80211_init_rfkill(struct wiphy *wiphy) +{ + wiphy_rfkill_set_hw_state(wiphy, 0); + wiphy_rfkill_start_polling(wiphy); +} + +void rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy) +{ + wiphy_rfkill_stop_polling(wiphy); +} + +static void cfg80211_rtw_rfkill_poll(struct wiphy *wiphy) +{ + _adapter *padapter = NULL; + bool blocked = _FALSE; + u8 valid = 0; + + padapter = wiphy_to_adapter(wiphy); + + if (adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) { + /*RTW_INFO("cfg80211_rtw_rfkill_poll: device is removed!\n");*/ + return; + } + + blocked = rtw_hal_rfkill_poll(padapter, &valid); + /*RTW_INFO("cfg80211_rtw_rfkill_poll: valid=%d, blocked=%d\n", + valid, blocked);*/ + + if (valid) + wiphy_rfkill_set_hw_state(wiphy, blocked); +} +#endif + +#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) +#define SURVEY_INFO_TIME SURVEY_INFO_CHANNEL_TIME +#define SURVEY_INFO_TIME_BUSY SURVEY_INFO_CHANNEL_TIME_BUSY +#define SURVEY_INFO_TIME_EXT_BUSY SURVEY_INFO_CHANNEL_TIME_EXT_BUSY +#define SURVEY_INFO_TIME_RX SURVEY_INFO_CHANNEL_TIME_RX +#define SURVEY_INFO_TIME_TX SURVEY_INFO_CHANNEL_TIME_TX +#endif + +#ifdef CONFIG_FIND_BEST_CHANNEL +static void rtw_cfg80211_set_survey_info_with_find_best_channel(struct wiphy *wiphy + , struct net_device *netdev, int idx, struct survey_info *info) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + RT_CHANNEL_INFO *ch_set = rfctl->channel_set; + u8 ch_num = rfctl->max_chan_nums; + u32 total_rx_cnt = 0; + int i; + + s8 noise = -50; /*channel noise in dBm. This and all following fields are optional */ + u64 time = 100; /*amount of time in ms the radio was turn on (on the channel)*/ + u64 time_busy = 0; /*amount of time the primary channel was sensed busy*/ + + info->filled = SURVEY_INFO_NOISE_DBM + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + | SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY + #endif + ; + + for (i = 0; i < ch_num; i++) + total_rx_cnt += ch_set[i].rx_count; + + time_busy = ch_set[idx].rx_count * time / total_rx_cnt; + noise += ch_set[idx].rx_count * 50 / total_rx_cnt; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) + info->channel_time = time; + info->channel_time_busy = time_busy; + #else + info->time = time; + info->time_busy = time_busy; + #endif +#endif + info->noise = noise; + + /* reset if final channel is got */ + if (idx == ch_num - 1) { + for (i = 0; i < ch_num; i++) + ch_set[i].rx_count = 0; + } +} +#endif /* CONFIG_FIND_BEST_CHANNEL */ + +#if defined(CONFIG_RTW_ACS) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) +static void rtw_cfg80211_set_survey_info_with_clm(PADAPTER padapter, int idx, struct survey_info *pinfo) +{ + s8 noise = -50; /*channel noise in dBm. This and all following fields are optional */ + u64 time = SURVEY_TO; /*amount of time in ms the radio was turn on (on the channel)*/ + u64 time_busy = 0; /*amount of time the primary channel was sensed busy*/ + u8 chan = (u8)idx; + + if ((idx < 0) || (pinfo == NULL)) + return; + + pinfo->filled = SURVEY_INFO_NOISE_DBM + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + | SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY + #endif + ; + + time_busy = rtw_acs_get_clm_ratio_by_ch_idx(padapter, chan); + noise = rtw_noise_query_by_chan_idx(padapter, chan); + /* RTW_INFO("%s: ch-idx:%d time=%llu(ms), time_busy=%llu(ms), noise=%d(dbm)\n", __func__, idx, time, time_busy, noise); */ + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) + #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) + pinfo->channel_time = time; + pinfo->channel_time_busy = time_busy; + #else + pinfo->time = time; + pinfo->time_busy = time_busy; + #endif +#endif + pinfo->noise = noise; +} +#endif + +int rtw_hostapd_acs_dump_survey(struct wiphy *wiphy, struct net_device *netdev, int idx, struct survey_info *info) +{ + PADAPTER padapter = (_adapter *)rtw_netdev_priv(netdev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + RT_CHANNEL_INFO *pch_set = rfctl->channel_set; + u8 max_chan_nums = rfctl->max_chan_nums; + u32 freq = 0; + u8 ret = 0; + u16 channel = 0; + + if (!netdev || !info) { + RTW_INFO("%s: invial parameters.\n", __func__); + return -EINVAL; + } + + _rtw_memset(info, 0, sizeof(struct survey_info)); + if (padapter->bup == _FALSE) { + RTW_INFO("%s: net device is down.\n", __func__); + return -EIO; + } + + if (idx >= max_chan_nums) + return -ENOENT; + + channel = pch_set[idx].ChannelNum; + freq = rtw_ch2freq(channel); + info->channel = ieee80211_get_channel(wiphy, freq); + /* RTW_INFO("%s: channel %d, freq %d\n", __func__, channel, freq); */ + + if (!info->channel) + return -EINVAL; + + if (info->channel->flags == IEEE80211_CHAN_DISABLED) + return ret; + +#ifdef CONFIG_FIND_BEST_CHANNEL + rtw_cfg80211_set_survey_info_with_find_best_channel(wiphy, netdev, idx, info); +#elif defined(CONFIG_RTW_ACS) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) + rtw_cfg80211_set_survey_info_with_clm(padapter, idx, info); +#else + RTW_ERR("%s: unknown acs operation!\n", __func__); +#endif + + return ret; } +#endif /* defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) */ static struct cfg80211_ops rtw_cfg80211_ops = { .change_virtual_intf = cfg80211_rtw_change_iface, @@ -6800,6 +9541,9 @@ static struct cfg80211_ops rtw_cfg80211_ops = { .get_key = cfg80211_rtw_get_key, .del_key = cfg80211_rtw_del_key, .set_default_key = cfg80211_rtw_set_default_key, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)) + .set_default_mgmt_key = cfg80211_rtw_set_default_mgmt_key, +#endif #if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) .set_rekey_data = cfg80211_rtw_set_rekey_data, #endif /*CONFIG_GTK_OL*/ @@ -6840,6 +9584,9 @@ static struct cfg80211_ops rtw_cfg80211_ops = { .change_station = cfg80211_rtw_change_station, .dump_station = cfg80211_rtw_dump_station, .change_bss = cfg80211_rtw_change_bss, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) + .set_txq_params = cfg80211_rtw_set_txq_params, +#endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) .set_channel = cfg80211_rtw_set_channel, #endif @@ -6847,6 +9594,22 @@ static struct cfg80211_ops rtw_cfg80211_ops = { /* .assoc = cfg80211_rtw_assoc, */ #endif /* CONFIG_AP_MODE */ +#if defined(CONFIG_RTW_MESH) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) + .get_mesh_config = cfg80211_rtw_get_mesh_config, + .update_mesh_config = cfg80211_rtw_update_mesh_config, + .join_mesh = cfg80211_rtw_join_mesh, + .leave_mesh = cfg80211_rtw_leave_mesh, + .add_mpath = cfg80211_rtw_add_mpath, + .del_mpath = cfg80211_rtw_del_mpath, + .change_mpath = cfg80211_rtw_change_mpath, + .get_mpath = cfg80211_rtw_get_mpath, + .dump_mpath = cfg80211_rtw_dump_mpath, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) + .get_mpp = cfg80211_rtw_get_mpp, + .dump_mpp = cfg80211_rtw_dump_mpp, + #endif +#endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) .set_monitor_channel = cfg80211_rtw_set_monitor_channel, #endif @@ -6879,7 +9642,15 @@ static struct cfg80211_ops rtw_cfg80211_ops = { #if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) .sched_scan_start = cfg80211_rtw_sched_scan_start, .sched_scan_stop = cfg80211_rtw_sched_scan_stop, + .suspend = cfg80211_rtw_suspend, + .resume = cfg80211_rtw_resume, #endif /* CONFIG_PNO_SUPPORT */ +#ifdef CONFIG_RFKILL_POLL + .rfkill_poll = cfg80211_rtw_rfkill_poll, +#endif +#if defined(CONFIG_RTW_HOSTAPD_ACS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33)) + .dump_survey = rtw_hostapd_acs_dump_survey, +#endif }; struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev) @@ -6937,6 +9708,8 @@ int rtw_wiphy_register(struct wiphy *wiphy) rtw_cfgvendor_attach(wiphy); #endif + rtw_regd_init(wiphy); + return wiphy_register(wiphy); } @@ -6973,11 +9746,7 @@ int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy) } wdev->wiphy = wiphy; wdev->netdev = pnetdev; - - wdev->iftype = NL80211_IFTYPE_STATION; /* will be init in rtw_hal_init() */ - /* Must sync with _rtw_init_mlme_priv() */ - /* pmlmepriv->fw_state = WIFI_STATION_STATE */ - /* wdev->iftype = NL80211_IFTYPE_MONITOR; */ /* for rtw_setopmode_cmd() in cfg80211_rtw_change_iface() */ + wdev->iftype = NL80211_IFTYPE_STATION; padapter->rtw_wdev = wdev; pnetdev->ieee80211_ptr = wdev; @@ -7011,6 +9780,13 @@ int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy) ATOMIC_SET(&pwdev_priv->switch_ch_to, 1); #endif +#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR + pwdev_priv->rssi_monitor_enable = 0; + pwdev_priv->rssi_monitor_max = 0; + pwdev_priv->rssi_monitor_min = 0; +#endif + + exit: return ret; } @@ -7121,6 +9897,10 @@ int rtw_cfg80211_ndev_res_register(_adapter *adapter) RTW_INFO("%s rtw_wiphy_register fail for if%d\n", __func__, (adapter->iface_id + 1)); goto exit; } + +#ifdef CONFIG_RFKILL_POLL + rtw_cfg80211_init_rfkill(adapter_to_wiphy(adapter)); +#endif #endif ret = _SUCCESS; @@ -7170,6 +9950,10 @@ int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj) #if defined(RTW_SINGLE_WIPHY) if (rtw_wiphy_register(dvobj_to_wiphy(dvobj)) != 0) goto exit; + +#ifdef CONFIG_RFKILL_POLL + rtw_cfg80211_init_rfkill(dvobj_to_wiphy(dvobj)); +#endif #endif ret = _SUCCESS; @@ -7181,6 +9965,9 @@ int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj) void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj) { #if defined(RTW_SINGLE_WIPHY) +#ifdef CONFIG_RFKILL_POLL + rtw_cfg80211_deinit_rfkill(dvobj_to_wiphy(dvobj)); +#endif rtw_wiphy_unregister(dvobj_to_wiphy(dvobj)); #endif } diff --git a/os_dep/linux/ioctl_cfg80211.h b/os_dep/linux/ioctl_cfg80211.h index af281ab..d16cfdd 100644 --- a/os_dep/linux/ioctl_cfg80211.h +++ b/os_dep/linux/ioctl_cfg80211.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,18 +11,19 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __IOCTL_CFG80211_H__ #define __IOCTL_CFG80211_H__ +#define RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT BIT0 +#define RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT BIT1 -#ifndef RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT - #define RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT 1 +#ifndef RTW_CFG80211_BLOCK_STA_DISCON_EVENT +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) +#define RTW_CFG80211_BLOCK_STA_DISCON_EVENT (RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT) +#else +#define RTW_CFG80211_BLOCK_STA_DISCON_EVENT (RTW_CFG80211_BLOCK_DISCON_WHEN_CONNECT | RTW_CFG80211_BLOCK_DISCON_WHEN_DISCONNECT) +#endif #endif #if defined(RTW_USE_CFG80211_STA_EVENT) @@ -55,6 +56,11 @@ #endif #endif +#ifndef CONFIG_RADIO_WORK +#define RTW_ROCH_DURATION_ENLARGE +#define RTW_ROCH_BACK_OP +#endif + #if !defined(CONFIG_P2P) && RTW_P2P_GROUP_INTERFACE #error "RTW_P2P_GROUP_INTERFACE can't be enabled when CONFIG_P2P is disabled\n" #endif @@ -67,6 +73,12 @@ #error "RTW_DEDICATED_P2P_DEVICE can't be enabled when kernel < 3.7.0\n" #endif +#ifdef CONFIG_RTW_MESH + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)) + #error "CONFIG_RTW_MESH can't be enabled when kernel < 3.10.0\n" + #endif +#endif + struct rtw_wdev_invit_info { u8 state; /* 0: req, 1:rep */ u8 peer_mac[ETH_ALEN]; @@ -130,7 +142,7 @@ struct rtw_wdev_priv { _adapter *padapter; - #if !RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT + #if RTW_CFG80211_BLOCK_STA_DISCON_EVENT u8 not_indic_disco; #endif @@ -144,7 +156,7 @@ struct rtw_wdev_priv { char ifname_mon[IFNAMSIZ + 1]; /* interface name for monitor interface */ u8 p2p_enabled; - u32 probe_resp_ie_update_time; + systime probe_resp_ie_update_time; u8 provdisc_req_issued; @@ -160,6 +172,7 @@ struct rtw_wdev_priv { u16 report_mgmt; u8 is_mgmt_tx; + u16 mgmt_tx_cookie; _mutex roch_mutex; @@ -167,14 +180,27 @@ struct rtw_wdev_priv { ATOMIC_T switch_ch_to; #endif +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + u8 pno_mac_addr[ETH_ALEN]; + u16 pno_scan_seq_num; +#endif + +#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR + s8 rssi_monitor_max; + s8 rssi_monitor_min; + u8 rssi_monitor_enable; +#endif + }; -#if RTW_CFG80211_ALWAYS_INFORM_STA_DISCONNECT_EVENT -#define rtw_wdev_not_indic_disco(rtw_wdev_data) 0 -#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do {} while (0) -#else +bool rtw_cfg80211_is_connect_requested(_adapter *adapter); + +#if RTW_CFG80211_BLOCK_STA_DISCON_EVENT #define rtw_wdev_not_indic_disco(rtw_wdev_data) ((rtw_wdev_data)->not_indic_disco) #define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do { (rtw_wdev_data)->not_indic_disco = (val); } while (0) +#else +#define rtw_wdev_not_indic_disco(rtw_wdev_data) 0 +#define rtw_wdev_set_not_indic_disco(rtw_wdev_data, val) do {} while (0) #endif #define rtw_wdev_free_connect_req(rtw_wdev_data) \ @@ -262,12 +288,15 @@ void rtw_cfg80211_indicate_scan_done_for_buddy(_adapter *padapter, bool bscan_ab #ifdef CONFIG_AP_MODE void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); -void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason); +void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, const u8 *da, unsigned short reason); #endif /* CONFIG_AP_MODE */ #ifdef CONFIG_P2P void rtw_cfg80211_set_is_roch(_adapter *adapter, bool val); bool rtw_cfg80211_get_is_roch(_adapter *adapter); +bool rtw_cfg80211_is_ro_ch_once(_adapter *adapter); +void rtw_cfg80211_set_last_ro_ch_time(_adapter *adapter); +s32 rtw_cfg80211_get_last_ro_ch_passing_ms(_adapter *adapter); int rtw_cfg80211_iface_has_p2p_group_cap(_adapter *adapter); int rtw_cfg80211_is_p2p_scan(_adapter *adapter); @@ -281,17 +310,27 @@ void rtw_pd_iface_free(struct wiphy *wiphy); void rtw_cfg80211_set_is_mgmt_tx(_adapter *adapter, u8 val); u8 rtw_cfg80211_get_is_mgmt_tx(_adapter *adapter); +u8 rtw_mgnt_tx_handler(_adapter *adapter, u8 *buf); void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len); void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, union recv_frame *rframe); void rtw_cfg80211_rx_action_p2p(_adapter *padapter, union recv_frame *rframe); void rtw_cfg80211_rx_action(_adapter *adapter, union recv_frame *rframe, const char *msg); +void rtw_cfg80211_rx_mframe(_adapter *adapter, union recv_frame *rframe, const char *msg); void rtw_cfg80211_rx_probe_request(_adapter *padapter, union recv_frame *rframe); int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type); bool rtw_cfg80211_pwr_mgmt(_adapter *adapter); +#ifdef CONFIG_RTW_80211K +void rtw_cfg80211_rx_rrm_action(_adapter *adapter, union recv_frame *rframe); +#endif + +#ifdef CONFIG_RFKILL_POLL +void rtw_cfg80211_init_rfkill(struct wiphy *wiphy); +void rtw_cfg80211_deinit_rfkill(struct wiphy *wiphy); +#endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE) #define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, buf, len, gfp) @@ -344,10 +383,27 @@ bool rtw_cfg80211_pwr_mgmt(_adapter *adapter); #endif #endif -#if (KERNEL_VERSION(4, 7, 0) >= LINUX_VERSION_CODE) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +#define rtw_cfg80211_notify_new_peer_candidate(wdev, addr, ie, ie_len, gfp) cfg80211_notify_new_peer_candidate(wdev_to_ndev(wdev), addr, ie, ie_len, gfp) +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)) +u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, u8 ht); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 26)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 7, 0)) +#define NL80211_BAND_2GHZ IEEE80211_BAND_2GHZ +#define NL80211_BAND_5GHZ IEEE80211_BAND_5GHZ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) +#define NL80211_BAND_60GHZ IEEE80211_BAND_60GHZ +#endif #define NUM_NL80211_BANDS IEEE80211_NUM_BANDS #endif +#define rtw_band_to_nl80211_band(band) \ + (band == BAND_ON_2_4G) ? NL80211_BAND_2GHZ : \ + (band == BAND_ON_5G) ? NL80211_BAND_5GHZ : NUM_NL80211_BANDS + #include "rtw_cfgvendor.h" #endif /* __IOCTL_CFG80211_H__ */ diff --git a/os_dep/linux/ioctl_linux.c b/os_dep/linux/ioctl_linux.c index d17bdfc..f169dc9 100644 --- a/os_dep/linux/ioctl_linux.c +++ b/os_dep/linux/ioctl_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _IOCTL_LINUX_C_ #include @@ -42,6 +37,7 @@ extern int rtw_ht_enable; #define SCAN_ITEM_SIZE 768 #define MAX_CUSTOM_LEN 64 #define RATE_COUNT 4 +#define MAX_SCAN_BUFFER_LEN 65535 #ifdef CONFIG_GLOBAL_UI_PID extern int ui_pid[3]; @@ -73,29 +69,6 @@ static const char *const iw_operation_mode[] = { "Auto", "Ad-Hoc", "Managed", "Master", "Repeater", "Secondary", "Monitor" }; -static int hex2num_i(char c) -{ - if (c >= '0' && c <= '9') - return c - '0'; - if (c >= 'a' && c <= 'f') - return c - 'a' + 10; - if (c >= 'A' && c <= 'F') - return c - 'A' + 10; - return -1; -} - -static int hex2byte_i(const char *hex) -{ - int a, b; - a = hex2num_i(*hex++); - if (a < 0) - return -1; - b = hex2num_i(*hex++); - if (b < 0) - return -1; - return (a << 4) | b; -} - /** * hwaddr_aton - Convert ASCII string to MAC address * @txt: MAC address as a string (e.g., "00:11:22:33:44:55") @@ -125,7 +98,7 @@ static int hwaddr_aton_i(const char *txt, u8 *addr) static void indicate_wx_custom_event(_adapter *padapter, char *msg) { - u8 *buff, *p; + u8 *buff; union iwreq_data wrqu; if (strlen(msg) > IW_CUSTOM_MAX) { @@ -212,7 +185,6 @@ void rtw_request_wps_pbc_event(_adapter *padapter) void indicate_wx_scan_complete_event(_adapter *padapter) { union iwreq_data wrqu; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); @@ -446,18 +418,24 @@ static inline char *iwe_stream_protocol_process(_adapter *padapter, u16 ht_cap = _FALSE, vht_cap = _FALSE; u32 ht_ielen = 0, vht_ielen = 0; char *p; - u8 ie_offset = (pnetwork->network.Reserved[0] == 2 ? 0 : 12); /* Probe Request */ + u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request */ +#ifdef CONFIG_80211N_HT /* parsing HT_CAP_IE */ - p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset); - if (p && ht_ielen > 0) - ht_cap = _TRUE; + if(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) { + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset); + if (p && ht_ielen > 0) + ht_cap = _TRUE; + } +#endif #ifdef CONFIG_80211AC_VHT /* parsing VHT_CAP_IE */ - p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset); - if (p && vht_ielen > 0) - vht_cap = _TRUE; + if(padapter->registrypriv.wireless_mode & WIRELESS_11AC) { + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset); + if (p && vht_ielen > 0) + vht_cap = _TRUE; + } #endif /* Add the protocol name */ iwe->cmd = SIOCGIWNAME; @@ -506,36 +484,39 @@ static inline char *iwe_stream_rate_process(_adapter *padapter, u8 bw_40MHz = 0, short_GI = 0, bw_160MHz = 0, vht_highest_rate = 0; u16 mcs_rate = 0, vht_data_rate = 0; char custom[MAX_CUSTOM_LEN] = {0}; - u8 ie_offset = (pnetwork->network.Reserved[0] == 2 ? 0 : 12); /* Probe Request */ + u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); /* Probe Request */ /* parsing HT_CAP_IE */ - p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset); - if (p && ht_ielen > 0) { - struct rtw_ieee80211_ht_cap *pht_capie; - ht_cap = _TRUE; - pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2); - _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); - bw_40MHz = (pht_capie->cap_info & IEEE80211_HT_CAP_SUP_WIDTH) ? 1 : 0; - short_GI = (pht_capie->cap_info & (IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40)) ? 1 : 0; + if(is_supported_ht(padapter->registrypriv.wireless_mode)) { + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset); + if (p && ht_ielen > 0) { + struct rtw_ieee80211_ht_cap *pht_capie; + ht_cap = _TRUE; + pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2); + _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); + bw_40MHz = (pht_capie->cap_info & IEEE80211_HT_CAP_SUP_WIDTH) ? 1 : 0; + short_GI = (pht_capie->cap_info & (IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40)) ? 1 : 0; + } } - #ifdef CONFIG_80211AC_VHT /* parsing VHT_CAP_IE */ - p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset); - if (p && vht_ielen > 0) { - u8 mcs_map[2]; - - vht_cap = _TRUE; - bw_160MHz = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2); - if (bw_160MHz) - short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI160M(p + 2); - else - short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI80M(p + 2); + if(padapter->registrypriv.wireless_mode & WIRELESS_11AC){ + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset); + if (p && vht_ielen > 0) { + u8 mcs_map[2]; + + vht_cap = _TRUE; + bw_160MHz = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2); + if (bw_160MHz) + short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI160M(p + 2); + else + short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI80M(p + 2); - _rtw_memcpy(mcs_map, GET_VHT_CAPABILITY_ELE_TX_MCS(p + 2), 2); + _rtw_memcpy(mcs_map, GET_VHT_CAPABILITY_ELE_TX_MCS(p + 2), 2); - vht_highest_rate = rtw_get_vht_highest_rate(mcs_map); - vht_data_rate = rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, short_GI, vht_highest_rate); + vht_highest_rate = rtw_get_vht_highest_rate(mcs_map); + vht_data_rate = rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, short_GI, vht_highest_rate); + } } #endif @@ -594,7 +575,7 @@ static inline char *iwe_stream_wpa_wpa2_process(_adapter *padapter, p = pbuf; /* parsing WPA/WPA2 IE */ - if (pnetwork->network.Reserved[0] != 2) { /* Probe Request */ + if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */ out_len = rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, rsn_ie, &rsn_len, wpa_ie, &wpa_len); if (wpa_len > 0) { @@ -653,12 +634,12 @@ static inline char *iwe_stream_wps_process(_adapter *padapter, uint cnt = 0, total_ielen; u8 *wpsie_ptr = NULL; uint wps_ielen = 0; - u8 ie_offset = (pnetwork->network.Reserved[0] == 2 ? 0 : 12); + u8 ie_offset = (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12); u8 *ie_ptr = pnetwork->network.IEs + ie_offset; total_ielen = pnetwork->network.IELength - ie_offset; - if (pnetwork->network.Reserved[0] == 2) { /* Probe Request */ + if (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) { /* Probe Request */ ie_ptr = pnetwork->network.IEs; total_ielen = pnetwork->network.IELength; } else { /* Beacon or Probe Respones */ @@ -684,7 +665,7 @@ static inline char *iwe_stream_wapi_process(_adapter *padapter, #ifdef CONFIG_WAPI_SUPPORT char *p; - if (pnetwork->network.Reserved[0] != 2) { /* Probe Request */ + if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ) { /* Probe Request */ sint out_len_wapi = 0; /* here use static for stack size */ static u8 buf_wapi[MAX_WAPI_IE_LEN * 2] = {0}; @@ -726,11 +707,14 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, { u8 ss, sq; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + s16 noise = 0; +#endif /* Add quality statistics */ iwe->cmd = IWEVQUAL; iwe->u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR | IW_QUAL_NOISE_UPDATED #else | IW_QUAL_NOISE_INVALID @@ -753,17 +737,7 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, #ifdef CONFIG_SIGNAL_DISPLAY_DBM iwe->u.qual.level = (u8) translate_percentage_to_dbm(ss); /* dbm */ #else -#ifdef CONFIG_SIGNAL_SCALE_MAPPING iwe->u.qual.level = (u8)ss; /* % */ -#else - { - /* Do signal scale mapping when using percentage as the unit of signal strength, since the scale mapping is skipped in odm */ - - HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); - - iwe->u.qual.level = (u8)odm_signal_scale_mapping(&pHal->odmpriv, ss); - } -#endif #endif iwe->u.qual.qual = (u8)sq; /* signal quality */ @@ -771,11 +745,13 @@ static inline char *iwe_stream_rssi_process(_adapter *padapter, #ifdef CONFIG_PLATFORM_ROCKCHIPS iwe->u.qual.noise = -100; /* noise level suggest by zhf@rockchips */ #else -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - { - s16 tmp_noise = 0; - rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(pnetwork->network.Configuration.DSConfig), &(tmp_noise)); - iwe->u.qual.noise = tmp_noise ; +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + if (IS_NM_ENABLE(padapter)) { + noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig); + #ifndef CONFIG_SIGNAL_DISPLAY_DBM + noise = translate_dbm_to_percentage(noise);/*percentage*/ + #endif + iwe->u.qual.noise = noise; } #else iwe->u.qual.noise = 0; /* noise level */ @@ -794,7 +770,6 @@ static inline char *iwe_stream_net_rsv_process(_adapter *padapter, { u8 buf[32] = {0}; u8 *p, *pos; - int len; p = buf; pos = pnetwork->network.Reserved; @@ -806,7 +781,6 @@ static inline char *iwe_stream_net_rsv_process(_adapter *padapter, return start; } -#if 1 static char *translate_scan(_adapter *padapter, struct iw_request_info *info, struct wlan_network *pnetwork, char *start, char *stop) @@ -821,7 +795,7 @@ static char *translate_scan(_adapter *padapter, start = iwe_stream_mac_addr_proess(padapter, info, pnetwork, start, stop, &iwe); start = iwe_stream_essid_proess(padapter, info, pnetwork, start, stop, &iwe); start = iwe_stream_protocol_process(padapter, info, pnetwork, start, stop, &iwe); - if (pnetwork->network.Reserved[0] == 2) /* Probe Request */ + if (pnetwork->network.Reserved[0] == BSS_TYPE_PROB_REQ) /* Probe Request */ cap = 0; else { _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); @@ -840,374 +814,6 @@ static char *translate_scan(_adapter *padapter, return start; } -#else -static char *translate_scan(_adapter *padapter, - struct iw_request_info *info, struct wlan_network *pnetwork, - char *start, char *stop) -{ - struct iw_event iwe; - u16 cap; - u32 ht_ielen = 0, vht_ielen = 0; - char custom[MAX_CUSTOM_LEN]; - char *p; - u16 max_rate = 0, rate, ht_cap = _FALSE, vht_cap = _FALSE; - u32 i = 0; - char *current_val; - long rssi; - u8 bw_40MHz = 0, short_GI = 0, bw_160MHz = 0, vht_highest_rate = 0; - u16 mcs_rate = 0, vht_data_rate = 0; - u8 ie_offset = (pnetwork->network.Reserved[0] == 2 ? 0 : 12); - struct registry_priv *pregpriv = &padapter->registrypriv; - - if (_FALSE == search_p2p_wfd_ie(padapter, info, pnetwork, start, stop)) - return start; - - /* AP MAC address */ - iwe.cmd = SIOCGIWAP; - iwe.u.ap_addr.sa_family = ARPHRD_ETHER; - - _rtw_memcpy(iwe.u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN); - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_ADDR_LEN); - - /* Add the ESSID */ - iwe.cmd = SIOCGIWESSID; - iwe.u.data.flags = 1; - iwe.u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32); - start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid); - - /* parsing HT_CAP_IE */ - if (pnetwork->network.Reserved[0] == 2) /* Probe Request */ - p = rtw_get_ie(&pnetwork->network.IEs[0], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength); - else - p = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - 12); - if (p && ht_ielen > 0) { - struct rtw_ieee80211_ht_cap *pht_capie; - ht_cap = _TRUE; - pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2); - _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); - bw_40MHz = (pht_capie->cap_info & IEEE80211_HT_CAP_SUP_WIDTH) ? 1 : 0; - short_GI = (pht_capie->cap_info & (IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40)) ? 1 : 0; - } - -#ifdef CONFIG_80211AC_VHT - /* parsing VHT_CAP_IE */ - p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset); - if (p && vht_ielen > 0) { - u8 mcs_map[2]; - - vht_cap = _TRUE; - bw_160MHz = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2); - if (bw_160MHz) - short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI160M(p + 2); - else - short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI80M(p + 2); - - _rtw_memcpy(mcs_map, GET_VHT_CAPABILITY_ELE_TX_MCS(p + 2), 2); - - vht_highest_rate = rtw_get_vht_highest_rate(mcs_map); - vht_data_rate = rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, short_GI, vht_highest_rate); - } -#endif - - /* Add the protocol name */ - iwe.cmd = SIOCGIWNAME; - if ((rtw_is_cckratesonly_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) { - if (ht_cap == _TRUE) - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bn"); - else - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b"); - } else if ((rtw_is_cckrates_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) { - if (ht_cap == _TRUE) - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bgn"); - else - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bg"); - } else { - if (pnetwork->network.Configuration.DSConfig > 14) { - if (vht_cap == _TRUE) - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11AC"); - else if (ht_cap == _TRUE) - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11an"); - else - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a"); - } else { - if (ht_cap == _TRUE) - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11gn"); - else - snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g"); - } - } - - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_CHAR_LEN); - - /* Add mode */ - if (pnetwork->network.Reserved[0] == 2) /* Probe Request */ - cap = 0; - else { - iwe.cmd = SIOCGIWMODE; - _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); - cap = le16_to_cpu(cap); - } - - if (cap & (WLAN_CAPABILITY_IBSS | WLAN_CAPABILITY_BSS)) { - if (cap & WLAN_CAPABILITY_BSS) - iwe.u.mode = IW_MODE_MASTER; - else - iwe.u.mode = IW_MODE_ADHOC; - - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_UINT_LEN); - } - - if (pnetwork->network.Configuration.DSConfig < 1 /*|| pnetwork->network.Configuration.DSConfig>14*/) - pnetwork->network.Configuration.DSConfig = 1; - - /* Add frequency/channel */ - iwe.cmd = SIOCGIWFREQ; - iwe.u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000; - iwe.u.freq.e = 1; - iwe.u.freq.i = pnetwork->network.Configuration.DSConfig; - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_FREQ_LEN); - - /* Add encryption capability */ - iwe.cmd = SIOCGIWENCODE; - if (cap & WLAN_CAPABILITY_PRIVACY) - iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; - else - iwe.u.data.flags = IW_ENCODE_DISABLED; - iwe.u.data.length = 0; - start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid); - - /*Add basic and extended rates */ - max_rate = 0; - p = custom; - p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): "); - while (pnetwork->network.SupportedRates[i] != 0) { - rate = pnetwork->network.SupportedRates[i] & 0x7F; - if (rate > max_rate) - max_rate = rate; - p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), - "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); - i++; - } - - if (vht_cap == _TRUE) - max_rate = vht_data_rate; - else if (ht_cap == _TRUE) { - if (mcs_rate & 0x8000) /* MCS15 */ - max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130); - - else if (mcs_rate & 0x0080) /* MCS7 */ - max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65); - else { /* default MCS7 */ - /* RTW_INFO("wx_get_scan, mcs_rate_bitmap=0x%x\n", mcs_rate); */ - max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65); - } - - max_rate = max_rate * 2; /* Mbps/2; */ - } - - iwe.cmd = SIOCGIWRATE; - iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0; - iwe.u.bitrate.value = max_rate * 500000; - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_PARAM_LEN); - - /* parsing WPA/WPA2 IE */ - if (pnetwork->network.Reserved[0] != 2) { /* Probe Request */ - u8 buf[MAX_WPA_IE_LEN * 2]; - u8 wpa_ie[255], rsn_ie[255]; - u16 wpa_len = 0, rsn_len = 0; - u8 *p; - sint out_len = 0; - out_len = rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, rsn_ie, &rsn_len, wpa_ie, &wpa_len); - - if (wpa_len > 0) { - p = buf; - _rtw_memset(buf, 0, MAX_WPA_IE_LEN * 2); - p += sprintf(p, "wpa_ie="); - for (i = 0; i < wpa_len; i++) - p += sprintf(p, "%02x", wpa_ie[i]); - - if (wpa_len > 100) { - printk("-----------------Len %d----------------\n", wpa_len); - for (i = 0; i < wpa_len; i++) - printk("%02x ", wpa_ie[i]); - printk("\n"); - printk("-----------------Len %d----------------\n", wpa_len); - } - - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVCUSTOM; - iwe.u.data.length = strlen(buf); - start = iwe_stream_add_point(info, start, stop, &iwe, buf); - - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVGENIE; - iwe.u.data.length = wpa_len; - start = iwe_stream_add_point(info, start, stop, &iwe, wpa_ie); - } - if (rsn_len > 0) { - p = buf; - _rtw_memset(buf, 0, MAX_WPA_IE_LEN * 2); - p += sprintf(p, "rsn_ie="); - for (i = 0; i < rsn_len; i++) - p += sprintf(p, "%02x", rsn_ie[i]); - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVCUSTOM; - iwe.u.data.length = strlen(buf); - start = iwe_stream_add_point(info, start, stop, &iwe, buf); - - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVGENIE; - iwe.u.data.length = rsn_len; - start = iwe_stream_add_point(info, start, stop, &iwe, rsn_ie); - } - } - - { /* parsing WPS IE */ - uint cnt = 0, total_ielen; - u8 *wpsie_ptr = NULL; - uint wps_ielen = 0; - - u8 *ie_ptr = pnetwork->network.IEs + ie_offset; - total_ielen = pnetwork->network.IELength - ie_offset; - - if (pnetwork->network.Reserved[0] == 2) { /* Probe Request */ - ie_ptr = pnetwork->network.IEs; - total_ielen = pnetwork->network.IELength; - } else { /* Beacon or Probe Respones */ - ie_ptr = pnetwork->network.IEs + _FIXED_IE_LENGTH_; - total_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_; - } - - while (cnt < total_ielen) { - if (rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen > 2)) { - wpsie_ptr = &ie_ptr[cnt]; - iwe.cmd = IWEVGENIE; - iwe.u.data.length = (u16)wps_ielen; - start = iwe_stream_add_point(info, start, stop, &iwe, wpsie_ptr); - } - cnt += ie_ptr[cnt + 1] + 2; /* goto next */ - } - } - -#ifdef CONFIG_WAPI_SUPPORT - if (pnetwork->network.Reserved[0] != 2) { /* Probe Request */ - sint out_len_wapi = 0; - /* here use static for stack size */ - static u8 buf_wapi[MAX_WAPI_IE_LEN * 2]; - static u8 wapi_ie[MAX_WAPI_IE_LEN]; - u16 wapi_len = 0; - u16 i; - - _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN); - _rtw_memset(wapi_ie, 0, MAX_WAPI_IE_LEN); - - out_len_wapi = rtw_get_wapi_ie(pnetwork->network.IEs , pnetwork->network.IELength, wapi_ie, &wapi_len); - - RTW_INFO("rtw_wx_get_scan: %s ", pnetwork->network.Ssid.Ssid); - RTW_INFO("rtw_wx_get_scan: ssid = %d ", wapi_len); - - - if (wapi_len > 0) { - p = buf_wapi; - _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN * 2); - p += sprintf(p, "wapi_ie="); - for (i = 0; i < wapi_len; i++) - p += sprintf(p, "%02x", wapi_ie[i]); - - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVCUSTOM; - iwe.u.data.length = strlen(buf_wapi); - start = iwe_stream_add_point(info, start, stop, &iwe, buf_wapi); - - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVGENIE; - iwe.u.data.length = wapi_len; - start = iwe_stream_add_point(info, start, stop, &iwe, wapi_ie); - } - } -#endif - - { - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - u8 ss, sq; - - /* Add quality statistics */ - iwe.cmd = IWEVQUAL; - iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - | IW_QUAL_NOISE_UPDATED -#else - | IW_QUAL_NOISE_INVALID -#endif -#ifdef CONFIG_SIGNAL_DISPLAY_DBM - | IW_QUAL_DBM -#endif - ; - - if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && - is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { - ss = padapter->recvpriv.signal_strength; - sq = padapter->recvpriv.signal_qual; - } else { - ss = pnetwork->network.PhyInfo.SignalStrength; - sq = pnetwork->network.PhyInfo.SignalQuality; - } - - -#ifdef CONFIG_SIGNAL_DISPLAY_DBM - iwe.u.qual.level = (u8) translate_percentage_to_dbm(ss); /* dbm */ -#else -#ifdef CONFIG_SIGNAL_SCALE_MAPPING - iwe.u.qual.level = (u8)ss; /* % */ -#else - { - /* Do signal scale mapping when using percentage as the unit of signal strength, since the scale mapping is skipped in odm */ - - HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); - - iwe.u.qual.level = (u8)odm_signal_scale_mapping(&pHal->odmpriv, ss); - } -#endif -#endif - - iwe.u.qual.qual = (u8)sq; /* signal quality */ - -#ifdef CONFIG_PLATFORM_ROCKCHIPS - iwe.u.qual.noise = -100; /* noise level suggest by zhf@rockchips */ -#else -#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) - { - s16 tmp_noise = 0; - rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(pnetwork->network.Configuration.DSConfig), &(tmp_noise)); - iwe.u.qual.noise = tmp_noise ; - } -#else - iwe.u.qual.noise = 0; /* noise level */ -#endif -#endif /* CONFIG_PLATFORM_ROCKCHIPS */ - - /* RTW_INFO("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); */ - - start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_QUAL_LEN); - } - - { - u8 buf[MAX_WPA_IE_LEN]; - u8 *p, *pos; - int len; - p = buf; - pos = pnetwork->network.Reserved; - _rtw_memset(buf, 0, MAX_WPA_IE_LEN); - p += sprintf(p, "fm=%02X%02X", pos[1], pos[0]); - _rtw_memset(&iwe, 0, sizeof(iwe)); - iwe.cmd = IWEVCUSTOM; - iwe.u.data.length = strlen(buf); - start = iwe_stream_add_point(info, start, stop, &iwe, buf); - } - - return start; -} -#endif static int wpa_set_auth_algs(struct net_device *dev, u32 value) { @@ -1257,7 +863,7 @@ static int wpa_set_auth_algs(struct net_device *dev, u32 value) static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) { int ret = 0; - u32 wep_key_idx, wep_key_len, wep_total_len; + u32 wep_key_idx, wep_key_len; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &padapter->securitypriv; @@ -1302,7 +908,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, wep_key_idx = param->u.crypt.idx; wep_key_len = param->u.crypt.key_len; - if ((wep_key_idx > WEP_KEYS) || (wep_key_len <= 0)) { + if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) { ret = -EINVAL; goto exit; } @@ -1330,6 +936,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, psecuritypriv->key_mask |= BIT(wep_key_idx); + padapter->mlmeextpriv.mlmext_info.key_index = wep_key_idx; goto exit; } @@ -1351,25 +958,23 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; if (param->u.crypt.set_tx == 1) { /* pairwise key */ + RTW_INFO(FUNC_ADPT_FMT" set %s PTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */ - /* DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); - padapter->securitypriv.busetkipkey = _FALSE; } - - /* DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); */ - RTW_INFO(" ~~~~set sta key:unicastkey\n"); - - rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE); - + psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq); psta->bpairwise_key_installed = _TRUE; + rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE); } else { /* group key */ if (strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set %s GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.alg, param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); /* only TKIP group key need to install this */ @@ -1378,35 +983,31 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); } padapter->securitypriv.binstallGrpkey = _TRUE; - /* DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */ - RTW_INFO(" ~~~~set sta key:groupkey\n"); - + if (param->u.crypt.idx < 4) + _rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8); padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx; - rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE); - } -#ifdef CONFIG_IEEE80211W - else if (strcmp(param->u.crypt.alg, "BIP") == 0) { - int no; - /* printk("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx); */ - /* save the IGTK key, length 16 bytes */ + + #ifdef CONFIG_IEEE80211W + } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set IGTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - /*printk("IGTK key below:\n"); - for(no=0;no<16;no++) - printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); - printk("\n");*/ - padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; - padapter->securitypriv.binstallBIPkey = _TRUE; - RTW_INFO(" ~~~~set sta key:IGKT\n"); + psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx; + psecuritypriv->dot11wBIPrxpn.val = RTW_GET_LE64(param->u.crypt.seq); + psecuritypriv->binstallBIPkey = _TRUE; + #endif /* CONFIG_IEEE80211W */ + } -#endif /* CONFIG_IEEE80211W */ #ifdef CONFIG_P2P if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE); #endif /* CONFIG_P2P */ + /* WPA/WPA2 key-handshake has completed */ + clr_fwstate(pmlmepriv, WIFI_UNDER_KEY_HANDSHAKE); } } @@ -1427,61 +1028,8 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, } #ifdef CONFIG_WAPI_SUPPORT - if (strcmp(param->u.crypt.alg, "SMS4") == 0) { - PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; - PRT_WAPI_STA_INFO pWapiSta; - u8 WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ; - - if (param->u.crypt.set_tx == 1) { - list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (_rtw_memcmp(pWapiSta->PeerMacAddr, param->sta_addr, 6)) { - _rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16); - - pWapiSta->wapiUsk.bSet = true; - _rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16); - _rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16); - pWapiSta->wapiUsk.keyId = param->u.crypt.idx ; - pWapiSta->wapiUsk.bTxEnable = true; - - _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16); - _rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16); - pWapiSta->wapiUskUpdate.bTxEnable = false; - pWapiSta->wapiUskUpdate.bSet = false; - - if (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) { - /* set unicast key for ASUE */ - rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false); - } - } - } - } else { - list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { - if (_rtw_memcmp(pWapiSta->PeerMacAddr, get_bssid(pmlmepriv), 6)) { - pWapiSta->wapiMsk.bSet = true; - _rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16); - _rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16); - pWapiSta->wapiMsk.keyId = param->u.crypt.idx ; - pWapiSta->wapiMsk.bTxEnable = false; - if (!pWapiSta->bSetkeyOk) - pWapiSta->bSetkeyOk = true; - pWapiSta->bAuthenticateInProgress = false; - - _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); - - if (psecuritypriv->sw_decrypt == false) { - /* set rx broadcast key for ASUE */ - rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false); - } - } - - } - } - } + if (strcmp(param->u.crypt.alg, "SMS4") == 0) + rtw_wapi_set_set_encryption(padapter, param); #endif exit: @@ -1493,8 +1041,8 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) { u8 *buf = NULL, *pos = NULL; - u32 left; int group_cipher = 0, pairwise_cipher = 0; + u8 mfp_opt = MFP_NO; int ret = 0; u8 null_addr[] = {0, 0, 0, 0, 0, 0}; #ifdef CONFIG_P2P @@ -1532,26 +1080,13 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) goto exit; } -#if 0 - pos += RSN_HEADER_LEN; - left = ielen - RSN_HEADER_LEN; - - if (left >= RSN_SELECTOR_LEN) { - pos += RSN_SELECTOR_LEN; - left -= RSN_SELECTOR_LEN; - } else if (left > 0) { - ret = -1; - goto exit; - } -#endif - if (rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); } - if (rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + if (rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) { padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); @@ -1608,6 +1143,13 @@ static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) break; } + if (mfp_opt == MFP_INVALID) { + RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter)); + ret = -EINVAL; + goto exit; + } + padapter->securitypriv.mfp_opt = mfp_opt; + _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); {/* set wps_ie */ u16 cnt = 0; @@ -1661,7 +1203,6 @@ static int rtw_wx_get_name(struct net_device *dev, union iwreq_data *wrqu, char *extra) { _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - u16 cap; u32 ht_ielen = 0; char *p; u8 ht_cap = _FALSE, vht_cap = _FALSE; @@ -1673,17 +1214,18 @@ static int rtw_wx_get_name(struct net_device *dev, if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) { /* parsing HT_CAP_IE */ - p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength - 12); - if (p && ht_ielen > 0) - ht_cap = _TRUE; - + if( is_supported_ht(padapter->registrypriv.wireless_mode)&&(padapter->registrypriv.ht_enable)) { + p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength - 12); + if (p && ht_ielen > 0 ) + ht_cap = _TRUE; + } #ifdef CONFIG_80211AC_VHT - if (pmlmepriv->vhtpriv.vht_option == _TRUE) + if ((padapter->registrypriv.wireless_mode & WIRELESS_11AC) && + (pmlmepriv->vhtpriv.vht_option == _TRUE)) vht_cap = _TRUE; #endif prates = &pcur_bss->SupportedRates; - if (rtw_is_cckratesonly_included((u8 *)prates) == _TRUE) { if (ht_cap == _TRUE) snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bn"); @@ -1692,8 +1234,12 @@ static int rtw_wx_get_name(struct net_device *dev, } else if ((rtw_is_cckrates_included((u8 *)prates)) == _TRUE) { if (ht_cap == _TRUE) snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bgn"); - else - snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bg"); + else { + if(padapter->registrypriv.wireless_mode & WIRELESS_11G) + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bg"); + else + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b"); + } } else { if (pcur_bss->Configuration.DSConfig > 14) { #ifdef CONFIG_80211AC_VHT @@ -1730,16 +1276,14 @@ static int rtw_wx_set_freq(struct net_device *dev, { _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct wlan_network *cur_network = &(pmlmepriv->cur_network); int exp = 1, freq = 0, div = 0; - - + rtw_ps_deny(padapter, PS_DENY_IOCTL); + if (rtw_pwr_wakeup(padapter) == _FALSE) + goto exit; if (wrqu->freq.m <= 1000) { if (wrqu->freq.flags == IW_FREQ_AUTO) { - if (rtw_chset_search_ch(padapter->mlmeextpriv.channel_set, wrqu->freq.m) > 0) { + if (rtw_chset_search_ch(adapter_to_chset(padapter), wrqu->freq.m) > 0) { padapter->mlmeextpriv.cur_channel = wrqu->freq.m; RTW_INFO("%s: channel is auto, set to channel %d\n", __func__, wrqu->freq.m); } else { @@ -1777,9 +1321,8 @@ static int rtw_wx_set_freq(struct net_device *dev, padapter->mlmeextpriv.cur_channel = rtw_freq2ch(freq); RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel); } - rtw_ps_deny(padapter, PS_DENY_IOCTL); - LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */ set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); +exit: rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); return 0; @@ -1863,7 +1406,6 @@ static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, case IW_MODE_MASTER: networkType = Ndis802_11APMode; RTW_INFO("set_mode = IW_MODE_MASTER\n"); - /* rtw_setopmode_cmd(padapter, networkType,_TRUE); */ break; case IW_MODE_INFRA: networkType = Ndis802_11Infrastructure; @@ -1875,17 +1417,6 @@ static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, goto exit; } - /* - if(Ndis802_11APMode == networkType) - { - rtw_setopmode_cmd(padapter, networkType,_TRUE); - } - else - { - rtw_setopmode_cmd(padapter, Ndis802_11AutoUnknown,_TRUE); - } - */ - if (rtw_set_802_11_infrastructure_mode(padapter, networkType) == _FALSE) { ret = -EPERM; @@ -1893,7 +1424,7 @@ static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, } - rtw_setopmode_cmd(padapter, networkType, _TRUE); + rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK); if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) rtw_indicate_connect(padapter); @@ -1939,7 +1470,6 @@ static int rtw_wx_set_pmkid(struct net_device *dev, _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); u8 j, blInserted = _FALSE; int intReturn = _FALSE; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &padapter->securitypriv; struct iw_pmksa *pPMK = (struct iw_pmksa *) extra; u8 strZeroMacAddress[ETH_ALEN] = { 0x00 }; @@ -2047,8 +1577,7 @@ static int rtw_wx_get_range(struct net_device *dev, { struct iw_range *range = (struct iw_range *)extra; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u16 val; int i; @@ -2089,7 +1618,6 @@ static int rtw_wx_get_range(struct net_device *dev, * If percentage range is 0~100 * Signal strength dbm range logical is -100 ~ 0 * but usually value is -90 ~ -20 - * When CONFIG_SIGNAL_SCALE_MAPPING is defined, dbm range is -95 ~ -45 */ range->max_qual.qual = 100; #ifdef CONFIG_SIGNAL_DISPLAY_DBM @@ -2148,12 +1676,12 @@ static int rtw_wx_get_range(struct net_device *dev, * range->min_r_time; Minimal retry lifetime * range->max_r_time; Maximal retry lifetime */ - for (i = 0, val = 0; i < pmlmeext->max_chan_nums; i++) { + for (i = 0, val = 0; i < rfctl->max_chan_nums; i++) { /* Include only legal frequencies for some countries */ - if (pmlmeext->channel_set[i].ChannelNum != 0) { - range->freq[val].i = pmlmeext->channel_set[i].ChannelNum; - range->freq[val].m = rtw_ch2freq(pmlmeext->channel_set[i].ChannelNum) * 100000; + if (rfctl->channel_set[i].ChannelNum != 0) { + range->freq[val].i = rfctl->channel_set[i].ChannelNum; + range->freq[val].m = rtw_ch2freq(rfctl->channel_set[i].ChannelNum) * 100000; range->freq[val].e = 1; val++; } @@ -2387,7 +1915,9 @@ static int rtw_wx_set_mlme(struct net_device *dev, default: return -EOPNOTSUPP; } - +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_do_disconnect(padapter); +#endif return ret; } @@ -2397,20 +1927,55 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, u8 _status = _FALSE; int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; - + /*struct mlme_priv *pmlmepriv = &padapter->mlmepriv;*/ + struct sitesurvey_parm parm; + u8 ssc_chk; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &(padapter->wdinfo); #endif /* CONFIG_P2P */ - #ifdef DBG_IOCTL RTW_INFO("DBG_IOCTL %s:%d\n", __FUNCTION__, __LINE__); #endif +#if 1 + ssc_chk = rtw_sitesurvey_condition_check(padapter, _FALSE); + + #ifdef CONFIG_DOSCAN_IN_BUSYTRAFFIC + if ((ssc_chk != SS_ALLOW) && (ssc_chk != SS_DENY_BUSY_TRAFFIC)) + #else + /* When Busy Traffic, driver do not site survey. So driver return success. */ + /* wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. */ + /* modify by thomas 2011-02-22. */ + if (ssc_chk != SS_ALLOW) + #endif + { + if (ssc_chk == SS_DENY_MP_MODE) + ret = -EPERM; + #ifdef DBG_LA_MODE + else if (ssc_chk == SS_DENY_LA_MODE) + ret = -EPERM; + #endif + else + indicate_wx_scan_complete_event(padapter); + + goto exit; + } else + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + rtw_ps_deny(padapter, PS_DENY_SCAN); + if (_FAIL == rtw_pwr_wakeup(padapter)) { + ret = -1; + goto cancel_ps_deny; + } + if (!rtw_is_adapter_up(padapter)) { + ret = -1; + goto cancel_ps_deny; + } +#else + #ifdef CONFIG_MP_INCLUDED - if (rtw_mi_mp_mode_check(padapter)) { + if (rtw_mp_mode_check(padapter)) { RTW_INFO("MP mode block Scan request\n"); ret = -EPERM; goto exit; @@ -2441,7 +2006,13 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, goto cancel_ps_deny; } #endif - +#ifdef CONFIG_RTW_REPEATER_SON + if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS) { + RTW_INFO(FUNC_ADPT_FMT" blocking scan for under rson scanning process\n", FUNC_ADPT_ARG(padapter)); + indicate_wx_scan_complete_event(padapter); + goto cancel_ps_deny; + } +#endif if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { RTW_INFO("AP mode process WPS\n"); indicate_wx_scan_complete_event(padapter); @@ -2461,6 +2032,7 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, goto cancel_ps_deny; } #endif +#endif #ifdef CONFIG_P2P if (pwdinfo->p2p_state != P2P_STATE_NONE) { @@ -2471,8 +2043,6 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, } #endif /* CONFIG_P2P */ - _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID) * RTW_SSID_SCAN_AMOUNT); - #if WIRELESS_EXT >= 17 if (wrqu->data.length == sizeof(struct iw_scan_req)) { struct iw_scan_req *req = (struct iw_scan_req *)extra; @@ -2480,12 +2050,14 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, if (wrqu->data.flags & IW_SCAN_THIS_ESSID) { int len = min((int)req->essid_len, IW_ESSID_MAX_SIZE); - _rtw_memcpy(ssid[0].Ssid, req->essid, len); - ssid[0].SsidLength = len; + rtw_init_sitesurvey_parm(padapter, &parm); + _rtw_memcpy(&parm.ssid[0].Ssid, &req->essid, len); + parm.ssid[0].SsidLength = len; + parm.ssid_num = 1; RTW_INFO("IW_SCAN_THIS_ESSID, ssid=%s, len=%d\n", req->essid, req->essid_len); - _status = rtw_set_802_11_bssid_list_scan(padapter, ssid, 1, NULL, 0); + _status = rtw_set_802_11_bssid_list_scan(padapter, &parm); } else if (req->scan_type == IW_SCAN_TYPE_PASSIVE) RTW_INFO("rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\n"); @@ -2503,6 +2075,7 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, int ssid_index = 0; /* RTW_INFO("%s COMBO_SCAN header is recognized\n", __FUNCTION__); */ + rtw_init_sitesurvey_parm(padapter, &parm); while (len >= 1) { section = *(pos++); @@ -2520,10 +2093,12 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, len -= 1; if (sec_len > 0 && sec_len <= len) { - ssid[ssid_index].SsidLength = sec_len; - _rtw_memcpy(ssid[ssid_index].Ssid, pos, ssid[ssid_index].SsidLength); - /* RTW_INFO("%s COMBO_SCAN with specific ssid:%s, %d\n", __FUNCTION__ */ - /* , ssid[ssid_index].Ssid, ssid[ssid_index].SsidLength); */ + + parm.ssid[ssid_index].SsidLength = sec_len; + _rtw_memcpy(&parm.ssid[ssid_index].Ssid, pos, sec_len); + + /* RTW_INFO("%s COMBO_SCAN with specific parm.ssid:%s, %d\n", __FUNCTION__ */ + /* , parm.ssid[ssid_index].Ssid, parm.ssid[ssid_index].SsidLength); */ ssid_index++; } @@ -2570,13 +2145,14 @@ static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, /* RTW_INFO("len:%d\n", len); */ } + parm.ssid_num = ssid_index; /* jeff: it has still some scan paramater to parse, we only do this now... */ - _status = rtw_set_802_11_bssid_list_scan(padapter, ssid, RTW_SSID_SCAN_AMOUNT, NULL, 0); + _status = rtw_set_802_11_bssid_list_scan(padapter, &parm); } else - _status = rtw_set_802_11_bssid_list_scan(padapter, NULL, 0, NULL, 0); + _status = rtw_set_802_11_bssid_list_scan(padapter, NULL); if (_status == _FALSE) ret = -1; @@ -2598,15 +2174,17 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, _irqL irqL; _list *plist, *phead; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + RT_CHANNEL_INFO *chset = rfctl->channel_set; struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); _queue *queue = &(pmlmepriv->scanned_queue); struct wlan_network *pnetwork = NULL; char *ev = extra; char *stop = ev + wrqu->data.length; u32 ret = 0; - u32 cnt = 0; u32 wait_for_surveydone; sint wait_status; + u8 ch; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &padapter->wdinfo; @@ -2668,17 +2246,26 @@ static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, break; if ((stop - ev) < SCAN_ITEM_SIZE) { + if(wrqu->data.length == MAX_SCAN_BUFFER_LEN){ /*max buffer len defined by iwlist*/ + ret = 0; + RTW_INFO("%s: Scan results incomplete\n", __FUNCTION__); + break; + } ret = -E2BIG; break; } pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + ch = pnetwork->network.Configuration.DSConfig; /* report network only if the current channel set contains the channel to which this network belongs */ - if (rtw_chset_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 - && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE - && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) - ) + if (rtw_chset_search_ch(chset, ch) >= 0 + && rtw_mlme_band_check(padapter, ch) == _TRUE + && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) + && (!IS_DFS_SLAVE_WITH_RD(rfctl) + || rtw_odm_dfs_domain_unknown(rfctl_to_dvobj(rfctl)) + || !rtw_chset_is_ch_non_ocp(chset, ch)) + ) ev = translate_scan(padapter, a, pnetwork, ev, stop); plist = get_next(plist); @@ -2715,7 +2302,6 @@ static int rtw_wx_set_essid(struct net_device *dev, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; _queue *queue = &pmlmepriv->scanned_queue; _list *phead; - s8 status = _TRUE; struct wlan_network *pnetwork = NULL; NDIS_802_11_AUTHENTICATION_MODE authmode; NDIS_802_11_SSID ndis_ssid; @@ -3356,11 +2942,14 @@ static int rtw_wx_set_auth(struct net_device *dev, { _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct iw_param *param = (struct iw_param *)&(wrqu->param); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct security_priv *psecuritypriv = &padapter->securitypriv; +#ifdef CONFIG_WAPI_SUPPORT +#ifndef CONFIG_IOCTL_CFG80211 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct security_priv *psecuritypriv = &padapter->securitypriv; u32 value = param->value; +#endif +#endif int ret = 0; switch (param->flags & IW_AUTH_INDEX) { @@ -3450,10 +3039,10 @@ static int rtw_wx_set_auth(struct net_device *dev, */ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { LeaveAllPowerSaveMode(padapter); - rtw_disassoc_cmd(padapter, 500, RTW_CMDF_DIRECTLY); + rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK); RTW_INFO("%s...call rtw_indicate_disconnect\n ", __FUNCTION__); rtw_indicate_disconnect(padapter, 0, _FALSE); - rtw_free_assoc_resources(padapter, 1); + rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK); } #endif @@ -3825,6 +3414,22 @@ static int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a, return -1; } +#ifdef CONFIG_RTW_80211K +extern void rm_dbg_cmd(_adapter *padapter, char *s); +static int rtw_wx_priv_rrm(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u32 path, addr, data32; + + + rm_dbg_cmd(padapter, b); + wrqu->data.length = strlen(b); + + return 0; +} +#endif + static int dummy(struct net_device *dev, struct iw_request_info *a, union iwreq_data *wrqu, char *b) { @@ -3842,7 +3447,6 @@ static int rtw_wx_set_channel_plan(struct net_device *dev, union iwreq_data *wrqu, char *extra) { _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; u8 channel_plan_req = (u8)(*((int *)wrqu)); if (_SUCCESS != rtw_set_channel_plan(padapter, channel_plan_req)) @@ -3878,122 +3482,17 @@ static int rtw_wx_get_sensitivity(struct net_device *dev, return 0; } -static int rtw_wx_set_mtk_wps_ie(struct net_device *dev, - struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ -#ifdef CONFIG_PLATFORM_MT53XX - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - return rtw_set_wpa_ie(padapter, wrqu->data.pointer, wrqu->data.length); -#else - return 0; -#endif -} - -/* -typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info, - union iwreq_data *wrqu, char *extra); -*/ -/* - * For all data larger than 16 octets, we need to use a - * pointer to memory allocated in user space. - */ -static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info, - union iwreq_data *wrqu, char *extra) -{ - -#if 0 - struct iw_point { - void __user *pointer; /* Pointer to the data (in user space) */ - __u16 length; /* number of fields or size in bytes */ - __u16 flags; /* Optional params */ - }; -#endif - -#ifdef CONFIG_DRVEXT_MODULE - u8 res; - struct drvext_handler *phandler; - struct drvext_oidparam *poidparam; - int ret; - u16 len; - u8 *pparmbuf, bset; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *p = &wrqu->data; - - if ((!p->length) || (!p->pointer)) { - ret = -EINVAL; - goto _rtw_drvext_hdl_exit; - } - - - bset = (u8)(p->flags & 0xFFFF); - len = p->length; - pparmbuf = (u8 *)rtw_malloc(len); - if (pparmbuf == NULL) { - ret = -ENOMEM; - goto _rtw_drvext_hdl_exit; - } - - if (bset) { /* set info */ - if (copy_from_user(pparmbuf, p->pointer, len)) { - rtw_mfree(pparmbuf, len); - ret = -EFAULT; - goto _rtw_drvext_hdl_exit; - } - } else { /* query info */ - - } - - - /* */ - poidparam = (struct drvext_oidparam *)pparmbuf; - - - - /* check subcode */ - if (poidparam->subcode >= MAX_DRVEXT_HANDLERS) { - ret = -EINVAL; - goto _rtw_drvext_hdl_exit; - } - - - if (poidparam->subcode >= MAX_DRVEXT_OID_SUBCODES) { - ret = -EINVAL; - goto _rtw_drvext_hdl_exit; - } - - - phandler = drvextoidhandlers + poidparam->subcode; - - if (poidparam->len != phandler->parmsize) { - ret = -EINVAL; - goto _rtw_drvext_hdl_exit; - } - - - res = phandler->handler(&padapter->drvextpriv, bset, poidparam->data); - - if (res == 0) { - ret = 0; - - if (bset == 0x00) {/* query info */ - /* _rtw_memcpy(p->pointer, pparmbuf, len); */ - if (copy_to_user(p->pointer, pparmbuf, len)) - ret = -EFAULT; - } - } else - ret = -EFAULT; - - -_rtw_drvext_hdl_exit: - - return ret; - -#endif +static int rtw_wx_set_mtk_wps_ie(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +#ifdef CONFIG_PLATFORM_MT53XX + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + return rtw_set_wpa_ie(padapter, wrqu->data.pointer, wrqu->data.length); +#else return 0; - +#endif } static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len) @@ -4206,7 +3705,7 @@ static int rtw_get_ap_info(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - int bssid_match, ret = 0; + int ret = 0; u32 cnt = 0, wpa_ielen; _irqL irqL; _list *plist, *phead; @@ -4380,8 +3879,6 @@ static int rtw_wext_p2p_enable(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; enum P2P_ROLE init_role = P2P_ROLE_DISABLE; @@ -4447,8 +3944,6 @@ static int rtw_p2p_set_go_nego_ssid(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); RTW_INFO("[%s] ssid = %s, len = %zu\n", __FUNCTION__, extra, strlen(extra)); @@ -4613,7 +4108,6 @@ static int rtw_p2p_get_status(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); if (padapter->bShowGetP2PState) { @@ -4644,7 +4138,6 @@ static int rtw_p2p_get_req_cm(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); sprintf(extra, "\n\nCM=%s\n", pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req); @@ -4661,10 +4154,8 @@ static int rtw_p2p_get_role(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); @@ -4683,7 +4174,6 @@ static int rtw_p2p_get_peer_ifaddr(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); @@ -4707,7 +4197,6 @@ static int rtw_p2p_get_peer_devaddr(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), @@ -4731,7 +4220,6 @@ static int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), @@ -4755,7 +4243,6 @@ static int rtw_p2p_get_groupid(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); sprintf(extra, "\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X %s", @@ -4776,7 +4263,6 @@ static int rtw_p2p_get_op_ch(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); @@ -4868,7 +4354,6 @@ static int rtw_p2p_get_peer_wfd_port(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); RTW_INFO("[%s] p2p_state = %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo)); @@ -4888,7 +4373,6 @@ static int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); sprintf(extra, "\n\nwfd_pc=%d\n", pwdinfo->wfd_info->wfd_pc); @@ -4907,7 +4391,6 @@ static int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); sprintf(extra, "\n\nwfd_sa=%d\n", pwdinfo->wfd_info->peer_session_avail); @@ -5241,7 +4724,6 @@ static int rtw_p2p_connect(struct net_device *dev, struct wifidirect_info *pwdinfo = &(padapter->wdinfo); u8 peerMAC[ETH_ALEN] = { 0x00 }; int jj, kk; - u8 peerMACStr[ETH_ALEN * 2] = { 0x00 }; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; _irqL irqL; _list *plist, *phead; @@ -5332,10 +4814,9 @@ static int rtw_p2p_connect(struct net_device *dev, u8 union_ch = rtw_mi_get_union_chan(padapter); u8 union_bw = rtw_mi_get_union_bw(padapter); u8 union_offset = rtw_mi_get_union_offset(padapter); - /* Have to enter the power saving with the AP */ - set_channel_bwmode(padapter, union_ch, union_offset, union_bw); - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + rtw_leave_opch(padapter); } #endif /* CONFIG_CONCURRENT_MODE */ @@ -5362,7 +4843,7 @@ static int rtw_p2p_connect(struct net_device *dev, * driver will do scanning itself */ _enter_critical_bh(&pmlmepriv->lock, &irqL); - rtw_sitesurvey_cmd(padapter, NULL, 0, NULL, 0); + rtw_sitesurvey_cmd(padapter, NULL); _exit_critical_bh(&pmlmepriv->lock, &irqL); #endif /* CONFIG_INTEL_WIDI */ ret = -1; @@ -5378,16 +4859,14 @@ static int rtw_p2p_invite_req(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); int jj, kk; - u8 peerMACStr[ETH_ALEN * 2] = { 0x00 }; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; _list *plist, *phead; _queue *queue = &(pmlmepriv->scanned_queue); struct wlan_network *pnetwork = NULL; uint uintPeerChannel = 0; - u8 attr_content[50] = { 0x00 }, _status = 0; + u8 attr_content[50] = { 0x00 }; u8 *p2pie; uint p2pielen = 0, attr_contentlen = 0; _irqL irqL; @@ -5524,15 +5003,15 @@ static int rtw_p2p_invite_req(struct net_device *dev, u8 union_ch = rtw_mi_get_union_chan(padapter); u8 union_bw = rtw_mi_get_union_bw(padapter); u8 union_offset = rtw_mi_get_union_offset(padapter); - /* Have to enter the power saving with the AP */ + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + rtw_leave_opch(padapter); - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); } else set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); #else set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); -#endif +#endif/*CONFIG_CONCURRENT_MODE*/ _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); @@ -5561,20 +5040,7 @@ static int rtw_p2p_set_persistent(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - int jj, kk; - u8 peerMACStr[ETH_ALEN * 2] = { 0x00 }; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - _list *plist, *phead; - _queue *queue = &(pmlmepriv->scanned_queue); - struct wlan_network *pnetwork = NULL; - uint uintPeerChannel = 0; - u8 attr_content[50] = { 0x00 }, _status = 0; - u8 *p2pie; - uint p2pielen = 0, attr_contentlen = 0; - _irqL irqL; - struct tx_invite_req_info *pinvite_req_info = &pwdinfo->invitereq_info; /* Commented by Albert 20120328 */ /* The input data is 0 or 1 */ @@ -5602,23 +5068,6 @@ static int rtw_p2p_set_persistent(struct net_device *dev, } -static int hexstr2bin(const char *hex, u8 *buf, size_t len) -{ - size_t i; - int a; - const char *ipos = hex; - u8 *opos = buf; - - for (i = 0; i < len; i++) { - a = hex2byte_i(ipos); - if (a < 0) - return -1; - *opos++ = a; - ipos += 2; - } - return 0; -} - static int uuid_str2bin(const char *str, u8 *bin) { const char *pos; @@ -5682,16 +5131,14 @@ static int rtw_p2p_set_pc(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); u8 peerMAC[ETH_ALEN] = { 0x00 }; int jj, kk; - u8 peerMACStr[ETH_ALEN * 2] = { 0x00 }; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; _list *plist, *phead; _queue *queue = &(pmlmepriv->scanned_queue); struct wlan_network *pnetwork = NULL; - u8 attr_content[50] = { 0x00 }, _status = 0; + u8 attr_content[50] = { 0x00 }; u8 *p2pie; uint p2pielen = 0, attr_contentlen = 0; _irqL irqL; @@ -5798,7 +5245,6 @@ static int rtw_p2p_set_wfd_device_type(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; @@ -5872,9 +5318,7 @@ static int rtw_p2p_set_sa(struct net_device *dev, int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct iw_point *pdata = &wrqu->data; struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); @@ -5907,13 +5351,12 @@ static int rtw_p2p_prov_disc(struct net_device *dev, struct wifidirect_info *pwdinfo = &(padapter->wdinfo); u8 peerMAC[ETH_ALEN] = { 0x00 }; int jj, kk; - u8 peerMACStr[ETH_ALEN * 2] = { 0x00 }; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; _list *plist, *phead; _queue *queue = &(pmlmepriv->scanned_queue); struct wlan_network *pnetwork = NULL; uint uintPeerChannel = 0; - u8 attr_content[100] = { 0x00 }, _status = 0; + u8 attr_content[100] = { 0x00 }; u8 *p2pie; uint p2pielen = 0, attr_contentlen = 0; _irqL irqL; @@ -6087,10 +5530,9 @@ static int rtw_p2p_prov_disc(struct net_device *dev, u8 union_bw = rtw_mi_get_union_bw(padapter); u8 union_offset = rtw_mi_get_union_offset(padapter); - /* Have to enter the power saving with the AP */ set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + rtw_leave_opch(padapter); - rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500); } else set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); #else @@ -6116,7 +5558,7 @@ static int rtw_p2p_prov_disc(struct net_device *dev, rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); rtw_free_network_queue(padapter, _TRUE); _enter_critical_bh(&pmlmepriv->lock, &irqL); - rtw_sitesurvey_cmd(padapter, NULL, 0, NULL, 0); + rtw_sitesurvey_cmd(padapter, NULL); _exit_critical_bh(&pmlmepriv->lock, &irqL); #endif /* CONFIG_INTEL_WIDI */ } @@ -6168,15 +5610,9 @@ static int rtw_p2p_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - int ret = 0; #ifdef CONFIG_P2P - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct iw_point *pdata = &wrqu->data; - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra); @@ -6262,16 +5698,9 @@ static int rtw_p2p_get(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { - int ret = 0; - #ifdef CONFIG_P2P - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct iw_point *pdata = &wrqu->data; - struct wifidirect_info *pwdinfo = &(padapter->wdinfo); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; if (padapter->bShowGetP2PState) RTW_INFO("[%s] extra = %s\n", __FUNCTION__, (char *) wrqu->data.pointer); @@ -6367,27 +5796,19 @@ static int rtw_cta_test_start(struct net_device *dev, { int ret = 0; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + RTW_INFO("%s %s\n", __func__, extra); if (!strcmp(extra, "1")) - padapter->in_cta_test = 1; + hal_data->in_cta_test = 1; else - padapter->in_cta_test = 0; + hal_data->in_cta_test = 0; + + rtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE); - if (padapter->in_cta_test) { - u32 v = rtw_read32(padapter, REG_RCR); - v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); /* | RCR_ADF */ - rtw_write32(padapter, REG_RCR, v); - RTW_INFO("enable RCR_ADF\n"); - } else { - u32 v = rtw_read32(padapter, REG_RCR); - v |= RCR_CBSSID_DATA | RCR_CBSSID_BCN ;/* | RCR_ADF */ - rtw_write32(padapter, REG_RCR, v); - RTW_INFO("disable RCR_ADF\n"); - } return ret; } - extern int rtw_change_ifname(_adapter *padapter, const char *ifname); static int rtw_rereg_nd_name(struct net_device *dev, struct iw_request_info *info, @@ -6430,8 +5851,6 @@ static int rtw_rereg_nd_name(struct net_device *dev, goto exit; if (_rtw_memcmp(rereg_priv->old_ifname, "disable%d", 9) == _TRUE) { - padapter->ledpriv.bRegUseLed = rereg_priv->old_bRegUseLed; - rtw_hal_sw_led_init(padapter); /* rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode); */ } @@ -6444,12 +5863,6 @@ static int rtw_rereg_nd_name(struct net_device *dev, /* free network queue for Android's timming issue */ rtw_free_network_queue(padapter, _TRUE); - /* close led */ - rtw_led_control(padapter, LED_CTL_POWER_OFF); - rereg_priv->old_bRegUseLed = padapter->ledpriv.bRegUseLed; - padapter->ledpriv.bRegUseLed = _FALSE; - rtw_hal_sw_led_deinit(padapter); - /* the interface is being "disabled", we can do deeper IPS */ /* rereg_priv->old_ips_mode = rtw_get_ips_mode_req(&padapter->pwrctrlpriv); */ /* rtw_ips_mode_req(&padapter->pwrctrlpriv, IPS_NORMAL); */ @@ -6462,15 +5875,13 @@ static int rtw_rereg_nd_name(struct net_device *dev, #ifdef CONFIG_IOL #include #endif - +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +#include "../../hal/hal_dm_acs.h" +#endif #ifdef DBG_CMD_QUEUE u8 dump_cmd_id = 0; #endif -/* -#ifdef DBG_DUMP_TSF_BY_PORT -extern void get_tsf_by_port(_adapter *adapter, u8 *tsftr, u8 hw_port); -#endif -*/ + static int rtw_dbg_port(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) @@ -6754,11 +6165,6 @@ static int rtw_dbg_port(struct net_device *dev, psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); break; - case 0x02: - RTW_INFO("pmlmeinfo->state=0x%x\n", pmlmeinfo->state); - RTW_INFO("DrvBcnEarly=%d\n", pmlmeext->DrvBcnEarly); - RTW_INFO("DrvBcnTimeOut=%d\n", pmlmeext->DrvBcnTimeOut); - break; case 0x03: RTW_INFO("qos_option=%d\n", pmlmepriv->qospriv.qos_option); #ifdef CONFIG_80211N_HT @@ -6779,13 +6185,15 @@ static int rtw_dbg_port(struct net_device *dev, psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); if (psta) { RTW_INFO("SSID=%s\n", cur_network->network.Ssid.Ssid); - RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); RTW_INFO("cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); - RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); + RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); #ifdef CONFIG_80211N_HT RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); - RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n" + , psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); #endif /* CONFIG_80211N_HT */ @@ -6795,12 +6203,10 @@ static int rtw_dbg_port(struct net_device *dev, RTW_INFO("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); break; case 0x06: { - #ifdef DBG_DUMP_TSF_BY_PORT u64 tsf = 0; - get_tsf_by_port(padapter, (u8 *)&tsf, extra_arg); - RTW_INFO(" PORT-%d TSF :%lld\n", extra_arg, tsf); - #endif + tsf = rtw_hal_get_tsftr_by_port(padapter, extra_arg); + RTW_INFO(" PORT-%d TSF :%21lld\n", extra_arg, tsf); } break; case 0x07: @@ -6828,7 +6234,8 @@ static int rtw_dbg_port(struct net_device *dev, _list *plist, *phead; #ifdef CONFIG_AP_MODE - RTW_INFO("sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap); + RTW_INFO_DUMP("sta_dz_bitmap:", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); + RTW_INFO_DUMP("tim_bitmap:", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); #endif _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); @@ -6841,13 +6248,15 @@ static int rtw_dbg_port(struct net_device *dev, plist = get_next(plist); - if (extra_arg == psta->aid) { - RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + if (extra_arg == psta->cmn.aid) { + RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr)); RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); - RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); + RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", + psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id); #ifdef CONFIG_80211N_HT RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); - RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, + RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", + psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); @@ -7087,17 +6496,9 @@ static int rtw_dbg_port(struct net_device *dev, break; #ifdef CONFIG_BACKGROUND_NOISE_MONITOR case 0x1e: { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - u8 chan = rtw_get_oper_ch(padapter); RTW_INFO("===========================================\n"); - odm_inband_noise_monitor(pDM_Odm, _TRUE, 0x1e, 100); - RTW_INFO("channel(%d),noise_a = %d, noise_b = %d , noise_all:%d\n", - chan, pDM_Odm->noise_level.noise[ODM_RF_PATH_A], - pDM_Odm->noise_level.noise[ODM_RF_PATH_B], - pDM_Odm->noise_level.noise_all); + rtw_noise_measure_curchan(padapter); RTW_INFO("===========================================\n"); - } break; #endif @@ -7162,9 +6563,6 @@ static int rtw_dbg_port(struct net_device *dev, { if (arg == 0xAA) { u8 page_offset, page_num; - u32 page_size = 0; - u8 *buffer = NULL; - u32 buf_size = 0; page_offset = (u8)(extra_arg >> 16); page_num = (u8)(extra_arg & 0xFF); @@ -7174,22 +6572,11 @@ static int rtw_dbg_port(struct net_device *dev, else { u8 fifo_sel; u32 addr, size; - u8 *buffer = NULL; fifo_sel = (u8)(arg & 0x0F); addr = (extra_arg >> 16) & 0xFFFF; size = extra_arg & 0xFFFF; - - RTW_INFO("fifo_sel:%d, start_addr:0x%04x, size:%d\n", fifo_sel, addr, size); - if (size) { - size = RND4(size); - buffer = rtw_zvmalloc(size); - if (NULL == buffer) - size = 0; - } - rtw_halmac_dump_fifo(adapter_to_dvobj(padapter), fifo_sel, addr, size, buffer); - if (buffer) - rtw_vmfree(buffer, size); + rtw_dump_fifo(RTW_DBGDUMP, padapter, fifo_sel, addr, size); } #endif } @@ -7328,7 +6715,6 @@ static int rtw_dbg_port(struct net_device *dev, static int wpa_set_param(struct net_device *dev, u8 name, u32 value) { uint ret = 0; - u32 flags; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); switch (name) { @@ -7461,7 +6847,9 @@ static int wpa_mlme(struct net_device *dev, u32 command, u32 reason) ret = -EOPNOTSUPP; break; } - +#ifdef CONFIG_RTW_REPEATER_SON + rtw_rson_do_disconnect(padapter); +#endif return ret; } @@ -7663,72 +7051,61 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) /* */ { /* group key */ if (param->u.crypt.set_tx == 1) { if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RTW_INFO("%s, set group_key, WEP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set WEP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - psecuritypriv->dot118021XGrpPrivacy = _WEP40_; if (param->u.crypt.key_len == 13) psecuritypriv->dot118021XGrpPrivacy = _WEP104_; } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - RTW_INFO("%s, set group_key, TKIP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set TKIP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); psecuritypriv->dot118021XGrpPrivacy = _TKIP_; - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ /* set mic key */ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); - psecuritypriv->busetkipkey = _TRUE; } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - RTW_INFO("%s, set group_key, CCMP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set CCMP TX GTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); psecuritypriv->dot118021XGrpPrivacy = _AES_; - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - } -#ifdef CONFIG_IEEE80211W - else if (strcmp(param->u.crypt.alg, "BIP") == 0) { - int no; - RTW_INFO("BIP key_len=%d , index=%d\n", param->u.crypt.key_len, param->u.crypt.idx); - /* save the IGTK key, length 16 bytes */ + #ifdef CONFIG_IEEE80211W + } else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set TX IGTK idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx, param->u.crypt.key_len); _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - /* RTW_INFO("IGTK key below:\n"); - for(no=0;no<16;no++) - printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); - RTW_INFO("\n"); */ - padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; - padapter->securitypriv.binstallBIPkey = _TRUE; - RTW_INFO(" ~~~~set sta key:IGKT\n"); + psecuritypriv->dot11wBIPKeyid = param->u.crypt.idx; + psecuritypriv->dot11wBIPtxpn.val = RTW_GET_LE64(param->u.crypt.seq); + psecuritypriv->binstallBIPkey = _TRUE; goto exit; - } -#endif /* CONFIG_IEEE80211W */ - else { - RTW_INFO("%s, set group_key, none\n", __FUNCTION__); + #endif /* CONFIG_IEEE80211W */ + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear group key, idx:%u\n" + , FUNC_ADPT_ARG(padapter), param->u.crypt.idx); psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + } else { + RTW_WARN(FUNC_ADPT_FMT" set group key, not support\n" + , FUNC_ADPT_ARG(padapter)); + goto exit; } psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; - - psecuritypriv->binstallGrpkey = _TRUE; - - psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ - - rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); if (pbcmc_sta) { + pbcmc_sta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); pbcmc_sta->ieee8021x_blocked = _FALSE; pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ } + psecuritypriv->binstallGrpkey = _TRUE; + psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); } goto exit; @@ -7741,80 +7118,58 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); if (strcmp(param->u.crypt.alg, "WEP") == 0) { - RTW_INFO("%s, set pairwise key, WEP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set WEP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _WEP40_; if (param->u.crypt.key_len == 13) psta->dot118021XPrivacy = _WEP104_; - } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - RTW_INFO("%s, set pairwise key, TKIP\n", __FUNCTION__); + } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { + RTW_INFO(FUNC_ADPT_FMT" set TKIP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _TKIP_; - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ /* set mic key */ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); - psecuritypriv->busetkipkey = _TRUE; } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - - RTW_INFO("%s, set pairwise key, CCMP\n", __FUNCTION__); - + RTW_INFO(FUNC_ADPT_FMT" set CCMP PTK of "MAC_FMT" idx:%u, len:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx, param->u.crypt.key_len); psta->dot118021XPrivacy = _AES_; - } else { - RTW_INFO("%s, set pairwise key, none\n", __FUNCTION__); + } else if (strcmp(param->u.crypt.alg, "none") == 0) { + RTW_INFO(FUNC_ADPT_FMT" clear pairwise key of "MAC_FMT" idx:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr) + , param->u.crypt.idx); psta->dot118021XPrivacy = _NO_PRIVACY_; - } - rtw_ap_set_pairwise_key(padapter, psta); + } else { + RTW_WARN(FUNC_ADPT_FMT" set pairwise key of "MAC_FMT", not support\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + goto exit; + } + psta->dot11txpn.val = RTW_GET_LE64(param->u.crypt.seq); + psta->dot11rxpn.val = RTW_GET_LE64(param->u.crypt.seq); psta->ieee8021x_blocked = _FALSE; - psta->bpairwise_key_installed = _TRUE; - - } else { /* group key??? */ - if (strcmp(param->u.crypt.alg, "WEP") == 0) { - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - psecuritypriv->dot118021XGrpPrivacy = _WEP40_; - if (param->u.crypt.key_len == 13) - psecuritypriv->dot118021XGrpPrivacy = _WEP104_; - } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { - psecuritypriv->dot118021XGrpPrivacy = _TKIP_; - - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - - /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ - /* set mic key */ - _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); - _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); - - psecuritypriv->busetkipkey = _TRUE; - - } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { - psecuritypriv->dot118021XGrpPrivacy = _AES_; - - _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); - } else - psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; - - psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; - - psecuritypriv->binstallGrpkey = _TRUE; - - psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ - - rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); + if (psta->dot118021XPrivacy != _NO_PRIVACY_) { + psta->bpairwise_key_installed = _TRUE; - pbcmc_sta = rtw_get_bcmc_stainfo(padapter); - if (pbcmc_sta) { - pbcmc_sta->ieee8021x_blocked = _FALSE; - pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ + /* WPA2 key-handshake has completed */ + if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) + psta->state &= (~WIFI_UNDER_KEY_HANDSHAKE); } + rtw_ap_set_pairwise_key(padapter, psta); + } else { + RTW_WARN(FUNC_ADPT_FMT" set group key of "MAC_FMT", not support\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr)); + goto exit; } } @@ -7872,16 +7227,15 @@ static int rtw_hostapd_sta_flush(struct net_device *dev) RTW_INFO("%s\n", __FUNCTION__); flush_all_cam_entry(padapter); /* clear CAM */ - +#ifdef CONFIG_AP_MODE ret = rtw_sta_flush(padapter, _TRUE); - +#endif return ret; } static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) { - _irqL irqL; int ret = 0; struct sta_info *psta = NULL; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); @@ -7916,7 +7270,7 @@ static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) /* RTW_INFO("rtw_add_sta(), init sta's variables, psta=%p\n", psta); */ - psta->aid = param->u.add_sta.aid;/* aid=1~2007 */ + psta->cmn.aid = param->u.add_sta.aid;/* aid=1~2007 */ _rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16); @@ -7933,7 +7287,9 @@ static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) #ifdef CONFIG_80211N_HT /* chec 802.11n ht cap. */ - if (WLAN_STA_HT & flags) { + if (padapter->registrypriv.ht_enable && + is_supported_ht(padapter->registrypriv.wireless_mode) && + (WLAN_STA_HT & flags)) { psta->htpriv.ht_option = _TRUE; psta->qos_option = 1; _rtw_memcpy((void *)&psta->htpriv.ht_cap, (void *)¶m->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); @@ -7942,6 +7298,7 @@ static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) if (pmlmepriv->htpriv.ht_option == _FALSE) psta->htpriv.ht_option = _FALSE; + #endif @@ -7978,7 +7335,7 @@ static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) if (psta) { u8 updated = _FALSE; - /* RTW_INFO("free psta=%p, aid=%d\n", psta, psta->aid); */ + /* RTW_INFO("free psta=%p, aid=%d\n", psta, psta->cmn.aid); */ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { @@ -8043,7 +7400,7 @@ static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *par u64 tx_drops; } get_sta; #endif - psta_data->aid = (u16)psta->aid; + psta_data->aid = (u16)psta->cmn.aid; psta_data->capability = psta->capability; psta_data->flags = psta->flags; @@ -8066,7 +7423,8 @@ static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *par psta_data->tx_supp_rates_len = psta->bssratelen; _rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen); #ifdef CONFIG_80211N_HT - _rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); + if(padapter->registrypriv.ht_enable && is_supported_ht(padapter->registrypriv.wireless_mode)) + _rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); #endif /* CONFIG_80211N_HT */ psta_data->rx_pkts = psta->sta_stats.rx_data_pkts; psta_data->rx_bytes = psta->sta_stats.rx_bytes; @@ -8133,7 +7491,6 @@ static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); int ie_len; RTW_INFO("%s, len=%d\n", __FUNCTION__, len); @@ -8310,7 +7667,7 @@ static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *p param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) return -EINVAL; - ret = rtw_acl_remove_sta(padapter, param->sta_addr); + ret = rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr); return ret; @@ -8330,7 +7687,7 @@ static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *para param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) return -EINVAL; - ret = rtw_acl_add_sta(padapter, param->sta_addr); + ret = rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, param->sta_addr); return ret; @@ -8345,7 +7702,7 @@ static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param * if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) return -EINVAL; - rtw_set_macaddr_acl(padapter, param->u.mlme.command); + rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, param->u.mlme.command); return ret; } @@ -8502,7 +7859,9 @@ static int rtw_wx_set_priv(struct net_device *dev, int ret = 0; int len = 0; char *ext; +#ifdef CONFIG_ANDROID int i; +#endif _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct iw_point *dwrq = (struct iw_point *)awrq; @@ -8667,7 +8026,7 @@ static int rtw_wowlan_ctrl(struct net_device *dev, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sta_info *psta = NULL; int ret = 0; - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); poidparam.subcode = 0; RTW_INFO("+rtw_wowlan_ctrl: %s\n", extra); @@ -8738,7 +8097,7 @@ static int rtw_wowlan_set_pattern(struct net_device *dev, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wowlan_ioctl_param poidparam; int ret = 0, len = 0, i = 0; - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); u8 input[wrqu->data.length]; u8 index = 0; @@ -8809,7 +8168,7 @@ static int rtw_ap_wowlan_ctrl(struct net_device *dev, struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct sta_info *psta = NULL; int ret = 0; - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); poidparam.subcode = 0; RTW_INFO("+rtw_ap_wowlan_ctrl: %s\n", extra); @@ -9071,7 +8430,6 @@ static int rtw_mp_efuse_get(struct net_device *dev, PEFUSE_HAL pEfuseHal; struct iw_point *wrqu; - u8 *PROMContent = pHalData->efuse_eeprom_data; u8 ips_mode = IPS_NUM; /* init invalid value */ u8 lps_mode = PS_MODE_NUM; /* init invalid value */ struct pwrctrl_priv *pwrctrlpriv ; @@ -9083,6 +8441,7 @@ static int rtw_mp_efuse_get(struct net_device *dev, u16 mask_len; u8 mask_buf[64] = ""; int err; + char *pextra = NULL; #ifdef CONFIG_IOL u8 org_fw_iol = padapter->registrypriv.fw_iol;/* 0:Disable, 1:enable, 2:by usb speed */ #endif @@ -9107,6 +8466,9 @@ static int rtw_mp_efuse_get(struct net_device *dev, err = -EFAULT; goto exit; } + + *(extra + wrqu->length) = '\0'; + #ifdef CONFIG_LPS lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */ rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); @@ -9159,16 +8521,17 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 0; i < cnt; i += 16) { - sprintf(extra, "%s0x%02x\t", extra, shift + i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); for (j = 0; j < 8; j++) - sprintf(extra, "%s%02X ", extra, efuse[i + j]); - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) - sprintf(extra, "%s%02X ", extra, efuse[i + j]); - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\n"); } if ((shift + cnt) < mapLen) - sprintf(extra, "%s\t...more (left:%d/%d)\n", extra, mapLen-(shift + cnt), mapLen); + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); } else if (strcmp(tmp[0], "realmap") == 0) { static u8 order = 0; @@ -9209,16 +8572,17 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 0; i < cnt; i += 16) { - sprintf(extra, "%s0x%02x\t", extra, shift + i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); for (j = 0; j < 8; j++) - sprintf(extra, "%s%02X ", extra, efuse[i + j]); - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) - sprintf(extra, "%s%02X ", extra, efuse[i + j]); - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\n"); } if ((shift + cnt) < mapLen) - sprintf(extra, "%s\t...more (left:%d/%d)\n", extra, mapLen-(shift + cnt), mapLen); + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); } else if (strcmp(tmp[0], "rmap") == 0) { if ((tmp[1] == NULL) || (tmp[2] == NULL)) { RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); @@ -9253,9 +8617,10 @@ static int rtw_mp_efuse_get(struct net_device *dev, /* RTW_INFO("%s: data={", __FUNCTION__); */ *extra = 0; + pextra = extra; for (i = 0; i < cnts; i++) { /* RTW_INFO("0x%02x ", data[i]); */ - sprintf(extra, "%s0x%02X ", extra, data[i]); + pextra += sprintf(pextra, "0x%02X ", data[i]); } /* RTW_INFO("}\n"); */ } else if (strcmp(tmp[0], "realraw") == 0) { @@ -9286,16 +8651,17 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 0; i < cnt; i += 16) { - sprintf(extra, "%s0x%02x\t", extra, shift + i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); for (j = 0; j < 8; j++) - sprintf(extra, "%s%02X ", extra, rawdata[i + j]); - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "%02X ", rawdata[i + j]); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) - sprintf(extra, "%s%02X ", extra, rawdata[i + j]); - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "%02X ", rawdata[i + j]); + pextra += sprintf(pextra, "\n"); } if ((shift + cnt) < mapLen) - sprintf(extra, "%s\t...more (left:%d/%d)\n", extra, mapLen-(shift + cnt), mapLen); + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); } else if (strcmp(tmp[0], "btrealraw") == 0) { static u8 bt_raw_order = 0; @@ -9333,16 +8699,17 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 0; i < cnt; i += 16) { - sprintf(extra, "%s0x%02x\t", extra, shift + i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); for (j = 0; j < 8; j++) - sprintf(extra, "%s%02X ", extra, rawdata[i + j]); - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "%02X ", rawdata[i + j]); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) - sprintf(extra, "%s%02X ", extra, rawdata[i + j]); - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "%02X ", rawdata[i + j]); + pextra += sprintf(pextra, "\n"); } if ((shift + cnt) < mapLen) - sprintf(extra, "%s\t...more (left:%d/%d)\n", extra, mapLen-(shift + cnt), mapLen); + pextra += sprintf(pextra, "\t...more (left:%d/%d)\n", mapLen-(shift + cnt), mapLen); } else if (strcmp(tmp[0], "mac") == 0) { if (hal_efuse_macaddr_offset(padapter) == -1) { @@ -9368,12 +8735,13 @@ static int rtw_mp_efuse_get(struct net_device *dev, /* RTW_INFO("%s: MAC address={", __FUNCTION__); */ *extra = 0; + pextra = extra; for (i = 0; i < cnts; i++) { /* RTW_INFO("%02X", data[i]); */ - sprintf(extra, "%s%02X", extra, data[i]); + pextra += sprintf(pextra, "%02X", data[i]); if (i != (cnts - 1)) { /* RTW_INFO(":"); */ - sprintf(extra, "%s:", extra); + pextra += sprintf(pextra, ":"); } } /* RTW_INFO("}\n"); */ @@ -9403,6 +8771,10 @@ static int rtw_mp_efuse_get(struct net_device *dev, addr = EEPROM_VID_8188FU; #endif /* CONFIG_RTL8188F */ +#ifdef CONFIG_RTL8188GTV + addr = EEPROM_VID_8188GTVU; +#endif + #ifdef CONFIG_RTL8703B #ifdef CONFIG_USB_HCI addr = EEPROM_VID_8703BU; @@ -9431,12 +8803,13 @@ static int rtw_mp_efuse_get(struct net_device *dev, /* RTW_INFO("%s: {VID,PID}={", __FUNCTION__); */ *extra = 0; + pextra = extra; for (i = 0; i < cnts; i++) { /* RTW_INFO("0x%02x", data[i]); */ - sprintf(extra, "%s0x%02X", extra, data[i]); + pextra += sprintf(pextra, "0x%02X", data[i]); if (i != (cnts - 1)) { /* RTW_INFO(","); */ - sprintf(extra, "%s,", extra); + pextra += sprintf(pextra, ","); } } /* RTW_INFO("}\n"); */ @@ -9467,19 +8840,20 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 0; i < 512; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */ /* RTW_INFO("0x%03x\t", i); */ - sprintf(extra, "%s0x%03x\t", extra, i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%03x\t", i); for (j = 0; j < 8; j++) { /* RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); } /* RTW_INFO("\t"); */ - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) { /* RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); } /* RTW_INFO("\n"); */ - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "\n"); } /* RTW_INFO("\n"); */ } else if (strcmp(tmp[0], "btbmap") == 0) { @@ -9496,19 +8870,20 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 512; i < 1024 ; i += 16) { /* RTW_INFO("0x%03x\t", i); */ - sprintf(extra, "%s0x%03x\t", extra, i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%03x\t", i); for (j = 0; j < 8; j++) { /* RTW_INFO("%02X ", data[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); } /* RTW_INFO("\t"); */ - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) { /* RTW_INFO("%02X ", data[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->BTEfuseInitMap[i+j]); } /* RTW_INFO("\n"); */ - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "\n"); } /* RTW_INFO("\n"); */ } else if (strcmp(tmp[0], "btrmap") == 0) { @@ -9556,10 +8931,11 @@ static int rtw_mp_efuse_get(struct net_device *dev, } *extra = 0; + pextra = extra; /* RTW_INFO("%s: bt efuse data={", __FUNCTION__); */ for (i = 0; i < cnts; i++) { /* RTW_INFO("0x%02x ", data[i]); */ - sprintf(extra, "%s 0x%02X ", extra, data[i]); + pextra += sprintf(pextra, " 0x%02X ", data[i]); } /* RTW_INFO("}\n"); */ RTW_INFO(FUNC_ADPT_FMT ": BT MAC=[%s]\n", FUNC_ADPT_ARG(padapter), extra); @@ -9568,19 +8944,20 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 0; i < 512; i += 16) { /* RTW_INFO("0x%03x\t", i); */ - sprintf(extra, "%s0x%03x\t", extra, i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%03x\t", i); for (j = 0; j < 8; j++) { /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); } /* RTW_INFO("\t"); */ - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) { /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); } /* RTW_INFO("\n"); */ - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "\n"); } /* RTW_INFO("\n"); */ } else if (strcmp(tmp[0], "btbfake") == 0) { @@ -9588,19 +8965,20 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 512; i < 1024; i += 16) { /* RTW_INFO("0x%03x\t", i); */ - sprintf(extra, "%s0x%03x\t", extra, i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%03x\t", i); for (j = 0; j < 8; j++) { /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); } /* RTW_INFO("\t"); */ - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) { /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ - sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + pextra += sprintf(pextra, "%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); } /* RTW_INFO("\n"); */ - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "\n"); } /* RTW_INFO("\n"); */ } else if (strcmp(tmp[0], "wlrfkmap") == 0) { @@ -9623,16 +9001,17 @@ static int rtw_mp_efuse_get(struct net_device *dev, sprintf(extra, "\n"); for (i = 0; i < cnt; i += 16) { - sprintf(extra, "%s0x%02x\t", extra, shift + i); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "0x%02x\t", shift + i); for (j = 0; j < 8; j++) - sprintf(extra, "%s%02X ", extra, efuse[i + j]); - sprintf(extra, "%s\t", extra); + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\t"); for (; j < 16; j++) - sprintf(extra, "%s%02X ", extra, efuse[i + j]); - sprintf(extra, "%s\n", extra); + pextra += sprintf(pextra, "%02X ", efuse[i + j]); + pextra += sprintf(pextra, "\n"); } if ((shift + cnt) < mapLen) - sprintf(extra, "%s\t...more\n", extra); + pextra += sprintf(pextra, "\t...more\n"); } else if (strcmp(tmp[0], "wlrfkrmap") == 0) { if ((tmp[1] == NULL) || (tmp[2] == NULL)) { @@ -9654,9 +9033,10 @@ static int rtw_mp_efuse_get(struct net_device *dev, /* RTW_INFO("%s: data={", __FUNCTION__); */ *extra = 0; + pextra = extra; for (i = 0; i < cnts; i++) { RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeEfuseModifiedMap[addr + i]); - sprintf(extra, "%s0x%02X ", extra, pEfuseHal->fakeEfuseModifiedMap[addr + i]); + pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeEfuseModifiedMap[addr+i]); } } else if (strcmp(tmp[0], "btrfkrmap") == 0) { if ((tmp[1] == NULL) || (tmp[2] == NULL)) { @@ -9678,9 +9058,10 @@ static int rtw_mp_efuse_get(struct net_device *dev, /* RTW_INFO("%s: data={", __FUNCTION__); */ *extra = 0; + pextra = extra; for (i = 0; i < cnts; i++) { RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeBTEfuseModifiedMap[addr + i]); - sprintf(extra, "%s0x%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[addr + i]); + pextra += sprintf(pextra, "0x%02X ", pEfuseHal->fakeBTEfuseModifiedMap[addr+i]); } } else if (strcmp(tmp[0], "mask") == 0) { *extra = 0; @@ -9691,8 +9072,9 @@ static int rtw_mp_efuse_get(struct net_device *dev, _rtw_memcpy(mask_buf, maskfileBuffer, mask_len); sprintf(extra, "\n"); + pextra = extra + strlen(extra); for (i = 0; i < mask_len; i++) - sprintf(extra, "%s0x%02X\n", extra, mask_buf[i]); + pextra += sprintf(pextra, "0x%02X\n", mask_buf[i]); } else sprintf(extra, "Command not found!"); @@ -9721,6 +9103,8 @@ static int rtw_mp_efuse_get(struct net_device *dev, return err; } + +#ifdef CONFIG_MP_INCLUDED static int rtw_mp_efuse_set(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wdata, char *extra) @@ -9744,6 +9128,8 @@ static int rtw_mp_efuse_set(struct net_device *dev, u16 addr = 0xFF, cnts = 0, BTStatus = 0 , max_available_len = 0; u16 wifimaplen; int err; + boolean bcmpchk = _TRUE; + wrqu = (struct iw_point *)wdata; padapter = rtw_netdev_priv(dev); @@ -9758,6 +9144,8 @@ static int rtw_mp_efuse_set(struct net_device *dev, if (copy_from_user(extra, wrqu->pointer, wrqu->length)) return -EFAULT; + *(extra + wrqu->length) = '\0'; + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&wifimaplen, _FALSE); setdata = rtw_zmalloc(1024); @@ -10028,6 +9416,10 @@ static int rtw_mp_efuse_set(struct net_device *dev, addr = EEPROM_VID_8188FU; #endif +#ifdef CONFIG_RTL8188GTV + addr = EEPROM_VID_8188GTVU; +#endif + #ifdef CONFIG_RTL8703B #ifdef CONFIG_USB_HCI addr = EEPROM_VID_8703BU; @@ -10268,7 +9660,8 @@ static int rtw_mp_efuse_set(struct net_device *dev, if (padapter->registrypriv.bFileMaskEfuse != _TRUE && pmp_priv->bloadefusemap == _TRUE) { RTW_INFO("%s: File eFuse mask file not to be loaded\n", __FUNCTION__); - sprintf(extra, "Not load eFuse mask file yet, Please use the efuse_mask CMD.\n"); + sprintf(extra, "Not load eFuse mask file yet, Please use the efuse_mask CMD, now remove the interface !!!!\n"); + rtw_set_surprise_removed(padapter); err = 0; goto exit; } @@ -10284,18 +9677,42 @@ static int rtw_mp_efuse_set(struct net_device *dev, } if (rtw_efuse_mask_map_read(padapter, 0x00, wifimaplen, ShadowMapWiFi) == _SUCCESS) { - if (_rtw_memcmp((void *)ShadowMapWiFi , (void *)pEfuseHal->fakeEfuseModifiedMap, cnts)) { - RTW_INFO("%s: WiFi write map afterf compare OK\n", __FUNCTION__); - sprintf(extra, "WiFi write map compare OK\n"); - err = 0; - goto exit; - } else { - sprintf(extra, "WiFi write map compare FAIL\n"); - RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__); - err = 0; - goto exit; + addr = 0x00; + err = _TRUE; + + for (i = 0; i < cnts; i++) { + if (padapter->registrypriv.boffefusemask == 0) { + if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { + if (rtw_file_efuse_IsMasked(padapter, addr + i) == _TRUE) /*use file efuse mask. */ + bcmpchk = _FALSE; + } else { + if (efuse_IsMasked(padapter, addr + i) == _TRUE) + bcmpchk = _FALSE; + } + } + + if (bcmpchk == _TRUE) { + RTW_INFO("compare readMapWiFi[0x%02x] = %x, ModifiedMap = %x\n", addr + i, ShadowMapWiFi[ addr + i], pEfuseHal->fakeEfuseModifiedMap[addr + i]); + if (_rtw_memcmp((void *) &ShadowMapWiFi[addr + i], (void *)&pEfuseHal->fakeEfuseModifiedMap[addr + i], 1) == _FALSE){ + err = _FALSE; + break; + } + } + bcmpchk = _TRUE; } } + + if (err) { + RTW_INFO("%s: WiFi write map afterf compare OK\n", __FUNCTION__); + sprintf(extra, "WiFi write map compare OK\n"); + err = 0; + goto exit; + } else { + sprintf(extra, "WiFi write map compare FAIL\n"); + RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__); + err = 0; + goto exit; + } } else if (strcmp(tmp[0], "wlwfake") == 0) { if ((tmp[1] == NULL) || (tmp[2] == NULL)) { err = -EINVAL; @@ -10386,8 +9803,12 @@ static int rtw_mp_efuse_set(struct net_device *dev, } _rtw_memset(extra, '\0', strlen(extra)); sprintf(extra, "eFuse Update OK\n"); - } + } else if (strcmp(tmp[0], "analyze") == 0) { + rtw_efuse_analyze(padapter, EFUSE_WIFI, 0); + _rtw_memset(extra, '\0', strlen(extra)); + sprintf(extra, "eFuse Analyze OK,please to check kernel log\n"); + } exit: if (setdata) rtw_mfree(setdata, 1024); @@ -10413,8 +9834,6 @@ static int rtw_mp_efuse_set(struct net_device *dev, return err; } -#ifdef CONFIG_MP_INCLUDED - #ifdef CONFIG_RTW_CUSTOMER_STR static int rtw_mp_customer_str( struct net_device *dev, @@ -10437,7 +9856,7 @@ static int rtw_mp_customer_str( || !adapter->registrypriv.mp_customer_str) return -EFAULT; - len = wrqu->data.length; + len = wrqu->data.length + 1; pbuf = (u8 *)rtw_zmalloc(len); if (pbuf == NULL) { @@ -10445,7 +9864,7 @@ static int rtw_mp_customer_str( return -ENOMEM; } - if (copy_from_user(pbuf, wrqu->data.pointer, len)) { + if (copy_from_user(pbuf, wrqu->data.pointer, wrqu->data.length)) { rtw_mfree(pbuf, len); RTW_WARN("%s: copy from user fail!\n", __func__); return -EFAULT; @@ -10521,6 +9940,14 @@ static int rtw_priv_mp_set(struct net_device *dev, struct iw_point *wrqu = (struct iw_point *)wdata; u32 subcmd = wrqu->flags; +#ifdef CONFIG_CONCURRENT_MODE + PADAPTER padapter = rtw_netdev_priv(dev); +#endif + + if (!is_primary_adapter(padapter)) { + RTW_INFO("MP mode only primary Adapter support\n"); + return -EIO; + } switch (subcmd) { case CTA_TEST: @@ -10554,6 +9981,14 @@ static int rtw_priv_mp_get(struct net_device *dev, struct iw_point *wrqu = (struct iw_point *)wdata; u32 subcmd = wrqu->flags; +#ifdef CONFIG_CONCURRENT_MODE + PADAPTER padapter = rtw_netdev_priv(dev); +#endif + + if (!is_primary_adapter(padapter)) { + RTW_INFO("MP mode only primary Adapter support\n"); + return -EIO; + } switch (subcmd) { case MP_START: @@ -10590,6 +10025,10 @@ static int rtw_priv_mp_get(struct net_device *dev, RTW_INFO("set case mp_channel\n"); rtw_mp_channel(dev , info, wrqu, extra); break; + case MP_CHL_OFFSET: + RTW_INFO("set case mp_ch_offset\n"); + rtw_mp_ch_offset(dev , info, wrqu, extra); + break; case READ_REG: RTW_INFO("mp_get READ_REG\n"); rtw_mp_read_reg(dev, info, wrqu, extra); @@ -10649,10 +10088,12 @@ static int rtw_priv_mp_get(struct net_device *dev, RTW_INFO("set case MP_PWRTRK\n"); rtw_mp_pwrtrk(dev, info, wrqu, extra); break; +#ifdef CONFIG_MP_INCLUDED case EFUSE_SET: RTW_INFO("set case efuse set\n"); rtw_mp_efuse_set(dev, info, wdata, extra); break; +#endif case EFUSE_GET: RTW_INFO("efuse get EFUSE_GET\n"); rtw_mp_efuse_get(dev, info, wdata, extra); @@ -10695,6 +10136,22 @@ static int rtw_priv_mp_get(struct net_device *dev, rtw_mp_customer_str(dev, info, wdata, extra); break; #endif + case MP_PWRLMT: + RTW_INFO("mp_get MP_SETPWRLMT\n"); + rtw_mp_pwrlmt(dev, info, wdata, extra); + break; + case MP_PWRBYRATE: + RTW_INFO("mp_get MP_SETPWRBYRATE\n"); + rtw_mp_pwrbyrate(dev, info, wdata, extra); + break; + case BT_EFUSE_FILE: + RTW_INFO("mp_get BT EFUSE_FILE\n"); + rtw_bt_efuse_file_map(dev, info, wdata, extra); + break; + case MP_SWRFPath: + RTW_INFO("mp_get MP_SWRFPath\n"); + rtw_mp_switch_rf_path(dev, info, wrqu, extra); + break; default: return -EIO; } @@ -10933,7 +10390,7 @@ static int rtw_priv_get(struct net_device *dev, if (subcmd < MP_NULL) { #ifdef CONFIG_MP_INCLUDED rtw_priv_mp_get(dev, info, wdata, extra); -#endif +#endif return 0; } @@ -11023,57 +10480,14 @@ static int rtw_tdls_enable(struct net_device *dev, int ret = 0; #ifdef CONFIG_TDLS - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; - _irqL irqL; - _list *plist, *phead; - s32 index; - struct sta_info *psta = NULL; - struct sta_priv *pstapriv = &padapter->stapriv; - u8 tdls_sta[NUM_STA][ETH_ALEN]; - u8 empty_hwaddr[ETH_ALEN] = { 0x00 }; - struct tdls_txmgmt txmgmt; RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1); - _rtw_memset(tdls_sta, 0x00, sizeof(tdls_sta)); - _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); - - if (extra[0] == '0') { - ptdlsinfo->tdls_enable = 0; - - if (pstapriv->asoc_sta_count == 1) - return ret; - - _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); - for (index = 0; index < NUM_STA; index++) { - phead = &(pstapriv->sta_hash[index]); - plist = get_next(phead); - - while (rtw_end_of_queue_search(phead, plist) == _FALSE) { - psta = LIST_CONTAINOR(plist, struct sta_info , hash_list); - - plist = get_next(plist); - - if (psta->tdls_sta_state != TDLS_STATE_NONE) - _rtw_memcpy(tdls_sta[index], psta->hwaddr, ETH_ALEN); - } - } - _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); - - for (index = 0; index < NUM_STA; index++) { - if (!_rtw_memcmp(tdls_sta[index], empty_hwaddr, ETH_ALEN)) { - RTW_INFO("issue tear down to "MAC_FMT"\n", MAC_ARG(tdls_sta[index])); - txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; - _rtw_memcpy(txmgmt.peer, tdls_sta[index], ETH_ALEN); - issue_tdls_teardown(padapter, &txmgmt, _TRUE); - } - } - rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR); - rtw_reset_tdls_info(padapter); - } else if (extra[0] == '1') - ptdlsinfo->tdls_enable = 1; + if (extra[0] == '0') + rtw_disable_tdls_func(padapter, _TRUE); + else if (extra[0] == '1') + rtw_enable_tdls_func(padapter); #endif /* CONFIG_TDLS */ return ret; @@ -11233,11 +10647,11 @@ static int rtw_tdls_ch_switch(struct net_device *dev, bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20; central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset); if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) >= 0) - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); else - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_PREPARE); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE); } else - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START); /* issue_tdls_ch_switch_req(padapter, ptdls_sta); */ /* RTW_INFO("issue tdls ch switch req\n"); */ @@ -11281,7 +10695,7 @@ static int rtw_tdls_ch_switch_off(struct net_device *dev, if (ptdls_sta == NULL) return ret; - rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL); + rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL); pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE | TDLS_CH_SWITCH_ON_STATE | @@ -11405,7 +10819,7 @@ static int rtw_tdls_pson(struct net_device *dev, ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 1, 3, 500); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 3, 500); #endif /* CONFIG_TDLS */ @@ -11432,7 +10846,7 @@ static int rtw_tdls_psoff(struct net_device *dev, ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); if (ptdls_sta) - issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 0, 3, 500); + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 3, 500); #endif /* CONFIG_TDLS */ @@ -11605,7 +11019,7 @@ static int rtw_wfd_tdls_status(struct net_device *dev, , ptdlsinfo->link_established, ptdlsinfo->sta_cnt, ptdlsinfo->sta_maximum, ptdlsinfo->cur_channel, - ptdlsinfo->tdls_enable + rtw_is_tdls_enabled(padapter) #ifdef CONFIG_TDLS_CH_SW , ptdlsinfo->chsw_info.ch_sw_state, @@ -11674,49 +11088,49 @@ static int rtw_tdls_get_best_ch(struct net_device *dev, { #ifdef CONFIG_FIND_BEST_CHANNEL _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0; - for (i = 0; i < pmlmeext->max_chan_nums && pmlmeext->channel_set[i].ChannelNum != 0; i++) { - if (pmlmeext->channel_set[i].ChannelNum == 1) + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { + if (rfctl->channel_set[i].ChannelNum == 1) index_24G = i; - if (pmlmeext->channel_set[i].ChannelNum == 36) + if (rfctl->channel_set[i].ChannelNum == 36) index_5G = i; } - for (i = 0; i < pmlmeext->max_chan_nums && pmlmeext->channel_set[i].ChannelNum != 0; i++) { + for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) { /* 2.4G */ - if (pmlmeext->channel_set[i].ChannelNum == 6 || pmlmeext->channel_set[i].ChannelNum == 11) { - if (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_24G].rx_count) { + if (rfctl->channel_set[i].ChannelNum == 6 || rfctl->channel_set[i].ChannelNum == 11) { + if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) { index_24G = i; - best_channel_24G = pmlmeext->channel_set[i].ChannelNum; + best_channel_24G = rfctl->channel_set[i].ChannelNum; } } /* 5G */ - if (pmlmeext->channel_set[i].ChannelNum >= 36 - && pmlmeext->channel_set[i].ChannelNum < 140) { + if (rfctl->channel_set[i].ChannelNum >= 36 + && rfctl->channel_set[i].ChannelNum < 140) { /* Find primary channel */ - if (((pmlmeext->channel_set[i].ChannelNum - 36) % 8 == 0) - && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) { + if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0) + && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { index_5G = i; - best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + best_channel_5G = rfctl->channel_set[i].ChannelNum; } } - if (pmlmeext->channel_set[i].ChannelNum >= 149 - && pmlmeext->channel_set[i].ChannelNum < 165) { + if (rfctl->channel_set[i].ChannelNum >= 149 + && rfctl->channel_set[i].ChannelNum < 165) { /* Find primary channel */ - if (((pmlmeext->channel_set[i].ChannelNum - 149) % 8 == 0) - && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) { + if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0) + && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) { index_5G = i; - best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + best_channel_5G = rfctl->channel_set[i].ChannelNum; } } #if 1 /* debug */ RTW_INFO("The rx cnt of channel %3d = %d\n", - pmlmeext->channel_set[i].ChannelNum, - pmlmeext->channel_set[i].rx_count); + rfctl->channel_set[i].ChannelNum, + rfctl->channel_set[i].rx_count); #endif } @@ -11753,8 +11167,8 @@ static int rtw_tdls(struct net_device *dev, return 0; } - if (padapter->tdlsinfo.tdls_enable == 0) { - RTW_INFO("tdls haven't enabled\n"); + if (rtw_is_tdls_enabled(padapter) == _FALSE) { + RTW_INFO("TDLS is not enabled\n"); return 0; } @@ -11926,6 +11340,11 @@ extern void rtl8723b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf #define fill_default_txdesc rtl8723d_fill_default_txdesc #endif /* CONFIG_RTL8723D */ +#if defined(CONFIG_RTL8710B) +#define cal_txdesc_chksum rtl8710b_cal_txdesc_chksum +#define fill_default_txdesc rtl8710b_fill_default_txdesc +#endif /* CONFIG_RTL8710B */ + #if defined(CONFIG_RTL8192E) extern void rtl8192e_cal_txdesc_chksum(struct tx_desc *ptxdesc); #define cal_txdesc_chksum rtl8192e_cal_txdesc_chksum @@ -11935,6 +11354,13 @@ extern void rtl8192es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbu #endif /* CONFIG_SDIO_HCI */ #endif /* CONFIG_RTL8192E */ +#if defined(CONFIG_RTL8192F) +/* extern void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc); */ +#define cal_txdesc_chksum rtl8192f_cal_txdesc_chksum +/* extern void rtl8192f_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */ +#define fill_default_txdesc rtl8192f_fill_default_txdesc +#endif /* CONFIG_RTL8192F */ + static s32 initLoopback(PADAPTER padapter) { PLOOPBACKDATA ploopback; @@ -11979,7 +11405,7 @@ static s32 initpseudoadhoc(PADAPTER padapter) if (err == _FALSE) return _FAIL; - err = rtw_setopmode_cmd(padapter, networkType, _TRUE); + err = rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_WAIT_ACK); if (err == _FAIL) return _FAIL; @@ -12046,7 +11472,7 @@ static s32 createpseudoadhoc(PADAPTER padapter) /* 3 join psudo AdHoc */ pcur_network->join_res = 1; - pcur_network->aid = psta->aid = 1; + pcur_network->aid = psta->cmn.aid = 1; _rtw_memcpy(&pcur_network->network, pdev_network, get_WLAN_BSSID_EX_sz(pdev_network)); /* set msr to WIFI_FW_ADHOC_STATE */ @@ -12124,14 +11550,12 @@ static struct xmit_frame *createloopbackpkt(PADAPTER padapter, u32 size) pattrib->qos_en = _FALSE; bmcast = IS_MCAST(pattrib->ra); - if (bmcast) { - pattrib->mac_id = 1; + if (bmcast) pattrib->psta = rtw_get_bcmc_stainfo(padapter); - } else { - pattrib->mac_id = 0; + else pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); - } + pattrib->mac_id = pattrib->psta->cmn.mac_id; pattrib->pktlen = size; pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; @@ -12264,7 +11688,7 @@ static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) rxpktsize = prxreport->pktlen; phal = GET_HAL_DATA(padapter); - if (phal->ReceiveConfig & RCR_APPFCS) + if (rtw_hal_rcr_check(padapter, RCR_APPFCS)) fcssize = IEEE80211_FCS_LEN; else fcssize = 0; @@ -12446,6 +11870,7 @@ static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8 *pmsg) ploopback->lbkthread = kthread_run(lbk_thread, padapter, "RTW_LBK_THREAD"); if (IS_ERR(padapter->lbkthread)) { freeLoopback(padapter); + ploopback->lbkthread = NULL; sprintf(pmsg, "loopback start FAIL! cnt=%d", cnt); return; } @@ -12469,17 +11894,20 @@ static int rtw_test( RTW_INFO("+%s\n", __func__); len = wrqu->data.length; - pbuf = (u8 *)rtw_zmalloc(len); + pbuf = (u8 *)rtw_zmalloc(len + 1); if (pbuf == NULL) { RTW_INFO("%s: no memory!\n", __func__); return -ENOMEM; } if (copy_from_user(pbuf, wrqu->data.pointer, len)) { - rtw_mfree(pbuf, len); + rtw_mfree(pbuf, len + 1); RTW_INFO("%s: copy from user fail!\n", __func__); return -EFAULT; } + + pbuf[len] = '\0'; + RTW_INFO("%s: string=\"%s\"\n", __func__, pbuf); ptmp = (char *)pbuf; @@ -12727,13 +12155,18 @@ static const struct iw_priv_args rtw_private_args[] = { SIOCIWFIRSTPRIV + 0x16, IW_PRIV_TYPE_CHAR | 64, 0, "pm_set" }, - +#ifdef CONFIG_RTW_80211K + { + SIOCIWFIRSTPRIV + 0x17, + IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , "rrm" + }, +#endif {SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | IFNAMSIZ , 0 , "rereg_nd_name"}, #ifdef CONFIG_MP_INCLUDED {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0, "NULL"}, {SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL"}, #else - {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0, "efuse_set"}, + {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0, "NULL"}, {SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get"}, #endif { @@ -12785,6 +12218,7 @@ static const struct iw_priv_args rtw_mp_private_args[] = { { MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" }, { MP_STOP , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_stop" }, { MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" }, + { MP_CHL_OFFSET , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ch_offset" }, { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_bandwidth"}, { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_reset_stats"}, @@ -12817,9 +12251,13 @@ static const struct iw_priv_args rtw_mp_private_args[] = { { MP_TX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_tx" }, { MP_RX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rx" }, { MP_HW_TX_MODE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_hxtx" }, + { MP_PWRLMT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrlmt" }, + { MP_PWRBYRATE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrbyrate" }, { CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, "cta_test"}, { MP_IQK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_iqk"}, { MP_LCK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_lck"}, + { BT_EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "bt_efuse_file" }, + { MP_SWRFPath, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_swrfpath" }, #ifdef CONFIG_RTW_CUSTOMER_STR { MP_CUSTOMER_STR, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "customer_str" }, #endif @@ -12830,7 +12268,7 @@ static const struct iw_priv_args rtw_mp_private_args[] = { static iw_handler rtw_private_handler[] = { rtw_wx_write32, /* 0x00 */ rtw_wx_read32, /* 0x01 */ - rtw_drvext_hdl, /* 0x02 */ + NULL, /* 0x02 */ #ifdef MP_IOCTL_HDL rtw_mp_ioctl_hdl, /* 0x03 */ #else @@ -12867,14 +12305,18 @@ static iw_handler rtw_private_handler[] = { rtw_tdls_get, /* 0x15 */ rtw_pm_set, /* 0x16 */ +#ifdef CONFIG_RTW_80211K + rtw_wx_priv_rrm, /* 0x17 */ +#else rtw_wx_priv_null, /* 0x17 */ +#endif rtw_rereg_nd_name, /* 0x18 */ rtw_wx_priv_null, /* 0x19 */ #ifdef CONFIG_MP_INCLUDED rtw_wx_priv_null, /* 0x1A */ rtw_wx_priv_null, /* 0x1B */ #else - rtw_mp_efuse_set, /* 0x1A */ + rtw_wx_priv_null, /* 0x1A */ rtw_mp_efuse_get, /* 0x1B */ #endif NULL, /* 0x1C is reserved for hostapd */ @@ -12903,22 +12345,18 @@ static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) #ifdef CONFIG_SIGNAL_DISPLAY_DBM tmp_level = translate_percentage_to_dbm(padapter->recvpriv.signal_strength); #else -#ifdef CONFIG_SIGNAL_SCALE_MAPPING tmp_level = padapter->recvpriv.signal_strength; -#else - { - /* Do signal scale mapping when using percentage as the unit of signal strength, since the scale mapping is skipped in odm */ - - HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); - - tmp_level = (u8)odm_signal_scale_mapping(&pHal->odmpriv, padapter->recvpriv.signal_strength); - } -#endif #endif tmp_qual = padapter->recvpriv.signal_qual; - rtw_get_noise(padapter); - tmp_noise = padapter->recvpriv.noise; + #ifdef CONFIG_BACKGROUND_NOISE_MONITOR + if (IS_NM_ENABLE(padapter)) { + tmp_noise = rtw_noise_measure_curchan(padapter); + #ifndef CONFIG_SIGNAL_DISPLAY_DBM + tmp_noise = translate_dbm_to_percentage(tmp_noise);/*percentage*/ + #endif + } + #endif /* RTW_INFO("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi); */ piwstats->qual.level = tmp_level; @@ -13118,6 +12556,11 @@ static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq goto exit; } + if (k >= num_priv_args) { + err = -EINVAL; + goto exit; + } + /* If we have to set some data */ if ((priv_args[k].set_args & IW_PRIV_TYPE_MASK) && (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) { @@ -13362,7 +12805,6 @@ static int rtw_ioctl_compat_wext_private(struct net_device *dev, struct ifreq *r static int rtw_ioctl_standard_wext_private(struct net_device *dev, struct ifreq *rq) { struct iw_point *iwp; - struct ifreq ifrq; union iwreq_data wrq_data; int err = 0; iwp = &wrq_data.data; diff --git a/os_dep/linux/ioctl_mp.c b/os_dep/linux/ioctl_mp.c index 47b48aa..c88e4d5 100644 --- a/os_dep/linux/ioctl_mp.c +++ b/os_dep/linux/ioctl_mp.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #if defined(CONFIG_MP_INCLUDED) #include @@ -42,17 +37,21 @@ int rtw_mp_write_reg(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - char *pch, *pnext, *ptmp; + char *pch, *pnext; char *width_str; - char width, buf[5]; + char width; u32 addr, data; int ret; PADAPTER padapter = rtw_netdev_priv(dev); - char input[wrqu->length]; + char input[wrqu->length + 1]; + + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; + _rtw_memset(extra, 0, wrqu->length); pch = input; @@ -130,22 +129,24 @@ int rtw_mp_read_reg(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - char input[wrqu->length]; - char *pch, *pnext, *ptmp; + char input[wrqu->length + 1]; + char *pch, *pnext; char *width_str; char width; - char data[20], tmp[20], buf[3]; + char data[20], tmp[20]; u32 addr = 0, strtout = 0; u32 i = 0, j = 0, ret = 0, data32 = 0; PADAPTER padapter = rtw_netdev_priv(dev); - + char *pextra = extra; if (wrqu->length > 128) return -EFAULT; + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; _rtw_memset(extra, 0, wrqu->length); _rtw_memset(data, '\0', sizeof(data)); _rtw_memset(tmp, '\0', sizeof(tmp)); @@ -198,7 +199,7 @@ int rtw_mp_read_reg(struct net_device *dev, if (*pnext != '\0') { /*strtout = simple_strtoul(pnext , &ptmp, 16);*/ ret = sscanf(pnext, "%x", &strtout); - sprintf(extra, "%s %d" , extra , strtout); + pextra += sprintf(pextra, " %d", strtout); } else break; pch = pnext; @@ -230,7 +231,7 @@ int rtw_mp_read_reg(struct net_device *dev, pnext++; if (*pnext != '\0') { ret = sscanf(pnext, "%x", &strtout); - sprintf(extra, "%s %d" , extra , strtout); + pextra += sprintf(pextra, " %d", strtout); } else break; pch = pnext; @@ -305,11 +306,12 @@ int rtw_mp_read_rf(struct net_device *dev, struct iw_point *wrqu, char *extra) { char input[wrqu->length]; - char *pch, *pnext, *ptmp; - char data[20], tmp[20], buf[3]; + char *pch, *pnext; + char data[20], tmp[20]; u32 path, addr, strtou; u32 ret, i = 0 , j = 0; PADAPTER padapter = rtw_netdev_priv(dev); + char *pextra = extra; if (wrqu->length > 128) return -EFAULT; @@ -349,7 +351,7 @@ int rtw_mp_read_rf(struct net_device *dev, if (*pnext != '\0') { /*strtou =simple_strtoul(pnext , &ptmp, 16);*/ ret = sscanf(pnext, "%x", &strtou); - sprintf(extra, "%s %d" , extra , strtou); + pextra += sprintf(pextra, " %d", strtou); } else break; pch = pnext; @@ -365,10 +367,7 @@ int rtw_mp_start(struct net_device *dev, struct iw_point *wrqu, char *extra) { int ret = 0; - u8 val8; PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct hal_ops *pHalFunc = &padapter->hal_func; rtw_pm_set_ips(padapter, IPS_NONE); LeaveAllPowerSaveMode(padapter); @@ -394,7 +393,6 @@ int rtw_mp_stop(struct net_device *dev, { int ret = 0; PADAPTER padapter = rtw_netdev_priv(dev); - struct hal_ops *pHalFunc = &padapter->hal_func; if (rtw_mp_cmd(padapter, MP_STOP, RTW_CMDF_WAIT_ACK) != _SUCCESS) ret = -EPERM; @@ -412,13 +410,15 @@ int rtw_mp_rate(struct net_device *dev, struct iw_point *wrqu, char *extra) { u32 rate = MPT_RATE_1M; - u8 input[wrqu->length]; + u8 input[wrqu->length + 1]; PADAPTER padapter = rtw_netdev_priv(dev); PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; rate = rtw_mpRateParseFunc(padapter, input); padapter->mppriv.rateidx = rate; @@ -460,13 +460,14 @@ int rtw_mp_channel(struct net_device *dev, PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - u8 input[wrqu->length]; + u8 input[wrqu->length + 1]; u32 channel = 1; - int cur_ch_offset; + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; channel = rtw_atoi(input); /*RTW_INFO("%s: channel=%d\n", __func__, channel);*/ _rtw_memset(extra, 0, wrqu->length); @@ -480,12 +481,37 @@ int rtw_mp_channel(struct net_device *dev, } +int rtw_mp_ch_offset(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + + PADAPTER padapter = rtw_netdev_priv(dev); + u8 input[wrqu->length + 1]; + u32 ch_offset = 0; + + _rtw_memset(input, 0, sizeof(input)); + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + input[wrqu->length] = '\0'; + ch_offset = rtw_atoi(input); + /*RTW_INFO("%s: channel=%d\n", __func__, channel);*/ + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "Change prime channel offset %d to %d", padapter->mppriv.prime_channel_offset , ch_offset); + padapter->mppriv.prime_channel_offset = ch_offset; + SetChannel(padapter); + + wrqu->length = strlen(extra); + return 0; +} + + int rtw_mp_bandwidth(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { u32 bandwidth = 0, sg = 0; - int cur_ch_offset; PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); u8 input[wrqu->length]; @@ -508,8 +534,7 @@ int rtw_mp_bandwidth(struct net_device *dev, SetBandwidth(padapter); pHalData->current_channel_bw = bandwidth; - /*cur_ch_offset = rtw_get_offset_by_ch(padapter->mppriv.channel);*/ - /*set_channel_bwmode(padapter, padapter->mppriv.channel, cur_ch_offset, bandwidth);*/ + wrqu->length = strlen(extra); return 0; @@ -521,19 +546,41 @@ int rtw_mp_txpower_index(struct net_device *dev, struct iw_point *wrqu, char *extra) { PADAPTER padapter = rtw_netdev_priv(dev); - char input[wrqu->length]; + HAL_DATA_TYPE *phal_data = GET_HAL_DATA(padapter); + char input[wrqu->length + 1]; u32 rfpath; u32 txpower_inx; if (wrqu->length > 128) return -EFAULT; + _rtw_memset(input, 0, sizeof(input)); + if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; - rfpath = rtw_atoi(input); - txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath); - sprintf(extra, " %d", txpower_inx); + input[wrqu->length] = '\0'; + + if (wrqu->length == 2) { + rfpath = rtw_atoi(input); + txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath); + sprintf(extra, " %d", txpower_inx); + } else { + txpower_inx = mpt_ProQueryCalTxPower(padapter, 0); + sprintf(extra, "patha=%d", txpower_inx); + if (phal_data->rf_type > RF_1T2R) { + txpower_inx = mpt_ProQueryCalTxPower(padapter, 1); + sprintf(extra, "%s,pathb=%d", extra, txpower_inx); + } + if (phal_data->rf_type > RF_2T4R) { + txpower_inx = mpt_ProQueryCalTxPower(padapter, 2); + sprintf(extra, "%s,pathc=%d", extra, txpower_inx); + } + if (phal_data->rf_type > RF_3T4R) { + txpower_inx = mpt_ProQueryCalTxPower(padapter, 3); + sprintf(extra, "%s,pathd=%d", extra, txpower_inx); + } + } wrqu->length = strlen(extra); return 0; @@ -544,7 +591,7 @@ int rtw_mp_txpower(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - u32 idx_a = 0, idx_b = 0, idx_c = 0, idx_d = 0, status = 0; + u32 idx_a = 0, idx_b = 0, idx_c = 0, idx_d = 0; int MsetPower = 1; u8 input[wrqu->length]; @@ -565,10 +612,10 @@ int rtw_mp_txpower(struct net_device *dev, sprintf(extra, "Set power level path_A:%d path_B:%d path_C:%d path_D:%d", idx_a , idx_b , idx_c , idx_d); padapter->mppriv.txpoweridx = (u8)idx_a; - pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)idx_a; - pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)idx_b; - pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)idx_c; - pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)idx_d; + pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)idx_a; + pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)idx_b; + pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)idx_c; + pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)idx_d; padapter->mppriv.bSetTxPower = 1; SetTxPower(padapter); @@ -584,14 +631,16 @@ int rtw_mp_ant_tx(struct net_device *dev, struct iw_point *wrqu, char *extra) { u8 i; - u8 input[wrqu->length]; + u8 input[wrqu->length + 1]; u16 antenna = 0; PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; sprintf(extra, "switch Tx antenna to %s", input); for (i = 0; i < strlen(input); i++) { @@ -630,12 +679,15 @@ int rtw_mp_ant_rx(struct net_device *dev, { u8 i; u16 antenna = 0; - u8 input[wrqu->length]; + u8 input[wrqu->length + 1]; PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + + input[wrqu->length] = '\0'; /*RTW_INFO("%s: input=%s\n", __func__, input);*/ _rtw_memset(extra, 0, wrqu->length); @@ -716,6 +768,7 @@ int rtw_mp_ctx(struct net_device *dev, if (copy_from_user(extra, wrqu->pointer, wrqu->length)) return -EFAULT; + *(extra + wrqu->length) = '\0'; RTW_INFO("%s: in=%s\n", __func__, extra); #ifdef CONFIG_CONCURRENT_MODE if (!is_primary_adapter(padapter)) { @@ -802,16 +855,20 @@ int rtw_mp_disable_bt_coexist(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { +#ifdef CONFIG_BT_COEXIST PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct hal_ops *pHalFunc = &padapter->hal_func; - u8 input[wrqu->data.length]; +#endif + u8 input[wrqu->data.length + 1]; u32 bt_coexist; + _rtw_memset(input, 0, sizeof(input)); + if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; + input[wrqu->data.length] = '\0'; + bt_coexist = rtw_atoi(input); if (bt_coexist == 0) { @@ -838,11 +895,11 @@ int rtw_mp_arx(struct net_device *dev, struct iw_request_info *info, struct iw_point *wrqu, char *extra) { - int bStartRx = 0, bStopRx = 0, bQueryPhy = 0, bQueryMac = 0, bSetBssid = 0; - int bmac_filter = 0, bfilter_init = 0, bmon = 0, bSmpCfg = 0, bloopbk = 0; + int bStartRx = 0, bStopRx = 0, bQueryPhy = 0, bQueryMac = 0, bSetBssid = 0, bSetRxframe = 0; + int bmac_filter = 0, bmon = 0, bSmpCfg = 0; u8 input[wrqu->length]; - char *pch, *ptmp, *token, *tmp[2] = {0x00, 0x00}; - u32 i = 0, ii = 0, jj = 0, kk = 0, cnts = 0, ret; + char *pch, *token, *tmp[2] = {0x00, 0x00}; + u32 i = 0, jj = 0, kk = 0, cnts = 0, ret; PADAPTER padapter = rtw_netdev_priv(dev); struct mp_priv *pmppriv = &padapter->mppriv; struct dbg_rx_counter rx_counter; @@ -863,6 +920,7 @@ int rtw_mp_arx(struct net_device *dev, bQueryPhy = (strncmp(input, "phy", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ bQueryMac = (strncmp(input, "mac", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ bSetBssid = (strncmp(input, "setbssid=", 8) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + bSetRxframe = (strncmp(input, "frametype", 9) == 0) ? 1 : 0; /*bfilter_init = (strncmp(input, "filter_init",11)==0)?1:0;*/ bmac_filter = (strncmp(input, "accept_mac", 10) == 0) ? 1 : 0; bmon = (strncmp(input, "mon=", 4) == 0) ? 1 : 0; @@ -892,6 +950,12 @@ int rtw_mp_arx(struct net_device *dev, pmppriv->bSetRxBssid = _TRUE; } + if (bSetRxframe) { + if (strncmp(input, "frametype beacon", 16) == 0) + pmppriv->brx_filter_beacon = _TRUE; + else + pmppriv->brx_filter_beacon = _FALSE; + } if (bmac_filter) { pmppriv->bmac_filter = bmac_filter; @@ -1018,7 +1082,6 @@ int rtw_mp_pwrtrk(struct net_device *dev, u32 thermal; s32 ret; PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); u8 input[wrqu->length]; if (copy_from_user(input, wrqu->pointer, wrqu->length)) @@ -1057,11 +1120,13 @@ int rtw_mp_psd(struct net_device *dev, struct iw_point *wrqu, char *extra) { PADAPTER padapter = rtw_netdev_priv(dev); - u8 input[wrqu->length]; + u8 input[wrqu->length + 1]; + _rtw_memset(input, 0, sizeof(input)); if (copy_from_user(input, wrqu->pointer, wrqu->length)) return -EFAULT; + input[wrqu->length] = '\0'; strcpy(extra, input); wrqu->length = mp_query_psd(padapter, extra); @@ -1086,6 +1151,9 @@ int rtw_mp_thermal(struct net_device *dev, #ifdef CONFIG_RTL8192E u16 addr = EEPROM_THERMAL_METER_8192E; #endif +#ifdef CONFIG_RTL8192F + u16 addr = EEPROM_THERMAL_METER_8192F; +#endif #ifdef CONFIG_RTL8723B u16 addr = EEPROM_THERMAL_METER_8723B; #endif @@ -1098,11 +1166,17 @@ int rtw_mp_thermal(struct net_device *dev, #ifdef CONFIG_RTL8188F u16 addr = EEPROM_THERMAL_METER_8188F; #endif +#ifdef CONFIG_RTL8188GTV + u16 addr = EEPROM_THERMAL_METER_8188GTV; +#endif #ifdef CONFIG_RTL8822B u16 addr = EEPROM_THERMAL_METER_8822B; #endif #ifdef CONFIG_RTL8821C u16 addr = EEPROM_THERMAL_METER_8821C; +#endif +#ifdef CONFIG_RTL8710B + u16 addr = EEPROM_THERMAL_METER_8710B; #endif u16 cnt = 1; u16 max_available_size = 0; @@ -1141,7 +1215,6 @@ int rtw_mp_reset_stats(struct net_device *dev, struct iw_point *wrqu, char *extra) { struct mp_priv *pmp_priv; - struct pkt_attrib *pattrib; PADAPTER padapter = rtw_netdev_priv(dev); pmp_priv = &padapter->mppriv; @@ -1168,11 +1241,7 @@ int rtw_mp_dump(struct net_device *dev, struct iw_point *wrqu, char *extra) { struct mp_priv *pmp_priv; - struct pkt_attrib *pattrib; - u32 value; u8 input[wrqu->length]; - u8 rf_type, path_nums = 0; - u32 i, j = 1, path; PADAPTER padapter = rtw_netdev_priv(dev); pmp_priv = &padapter->mppriv; @@ -1224,6 +1293,9 @@ int rtw_mp_SetRFPath(struct net_device *dev, PADAPTER padapter = rtw_netdev_priv(dev); char input[wrqu->length]; int bMain = 1, bTurnoff = 1; +#ifdef CONFIG_ANTENNA_DIVERSITY + u8 ret = _TRUE; +#endif RTW_INFO("%s:iwpriv in=%s\n", __func__, input); @@ -1234,6 +1306,14 @@ int rtw_mp_SetRFPath(struct net_device *dev, bTurnoff = strncmp(input, "0", 3); /* strncmp TRUE is 0*/ _rtw_memset(extra, 0, wrqu->length); +#ifdef CONFIG_ANTENNA_DIVERSITY + if (bMain == 0) + ret = rtw_mp_set_antdiv(padapter, _TRUE); + else + ret = rtw_mp_set_antdiv(padapter, _FALSE); + if (ret == _FALSE) + RTW_INFO("%s:ANTENNA_DIVERSITY FAIL\n", __func__); +#endif if (bMain == 0) { MP_PHY_SetRFPathSwitch(padapter, _TRUE); @@ -1256,6 +1336,56 @@ int rtw_mp_SetRFPath(struct net_device *dev, } +int rtw_mp_switch_rf_path(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv; + char input[wrqu->length]; + int bwlg = 1, bwla = 1, btg = 1, bbt=1; + u8 ret = 0; + + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + pmp_priv = &padapter->mppriv; + + RTW_INFO("%s: in=%s\n", __func__, input); + + bwlg = strncmp(input, "WLG", 3); /* strncmp TRUE is 0*/ + bwla = strncmp(input, "WLA", 3); /* strncmp TRUE is 0*/ + btg = strncmp(input, "BTG", 3); /* strncmp TRUE is 0*/ + bbt = strncmp(input, "BT", 3); /* strncmp TRUE is 0*/ + + _rtw_memset(extra, 0, wrqu->length); +#ifdef CONFIG_RTL8821C /* only support for 8821c wlg/wla/btg/bt RF switch path */ + if (bwlg == 0) { + pmp_priv->rf_path_cfg = SWITCH_TO_WLG; + sprintf(extra, "switch rf path WLG\n"); + } else if (bwla == 0) { + pmp_priv->rf_path_cfg = SWITCH_TO_WLA; + sprintf(extra, "switch rf path WLA\n"); + } else if (btg == 0) { + pmp_priv->rf_path_cfg = SWITCH_TO_BTG; + sprintf(extra, "switch rf path BTG\n"); + } else if (bbt == 0) { + pmp_priv->rf_path_cfg = SWITCH_TO_BT; + sprintf(extra, "switch rf path BG\n"); + } else { + sprintf(extra, "Error set %s\n", __func__); + return -EFAULT; + } + + mp_phy_switch_rf_path_set(padapter, &pmp_priv->rf_path_cfg); +#endif + + wrqu->length = strlen(extra); + + return ret; + +} int rtw_mp_QueryDrv(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) @@ -1364,6 +1494,7 @@ int rtw_mp_mon(struct net_device *dev, if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; + *(extra + wrqu->data.length) = '\0'; rtw_pm_set_ips(padapter, IPS_NONE); LeaveAllPowerSaveMode(padapter); @@ -1393,7 +1524,7 @@ int rtw_mp_mon(struct net_device *dev, if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { rtw_disassoc_cmd(padapter, 500, 0); rtw_indicate_disconnect(padapter, 0, _FALSE); - /*rtw_free_assoc_resources(padapter, 1);*/ + /*rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);*/ } rtw_pm_set_ips(padapter, IPS_NORMAL); sprintf(extra, "monitor mode Stop\n"); @@ -1405,9 +1536,8 @@ int rtw_mp_mon(struct net_device *dev, int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) { - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct mp_priv *pmp_priv = &padapter->mppriv; - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + char *pextra = extra; switch (pmp_priv->mode) { @@ -1417,7 +1547,8 @@ int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) pmp_priv->mode = MP_ON; sprintf(extra, "Stop continuous Tx"); } else if (pmp_priv->tx.stop == 1) { - sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500 count=%u\n", extra, pmp_priv->tx.count); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "\nStart continuous DA=ffffffffffff len=1500 count=%u\n", pmp_priv->tx.count); pmp_priv->tx.stop = 0; SetPacketTx(padapter); } else @@ -1425,26 +1556,26 @@ int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) return 0; case MP_SINGLE_TONE_TX: if (bStartTest != 0) - sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); SetSingleToneTx(padapter, (u8)bStartTest); break; case MP_CONTINUOUS_TX: if (bStartTest != 0) - sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); SetContinuousTx(padapter, (u8)bStartTest); break; case MP_CARRIER_SUPPRISSION_TX: if (bStartTest != 0) { if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_11M) - sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); else - sprintf(extra, "%s\nSpecify carrier suppression but not CCK rate", extra); + strcat(extra, "\nSpecify carrier suppression but not CCK rate"); } SetCarrierSuppressionTx(padapter, (u8)bStartTest); break; case MP_SINGLE_CARRIER_TX: if (bStartTest != 0) - sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + strcat(extra, "\nStart continuous DA=ffffffffffff len=1500\n infinite=yes."); SetSingleCarrierTx(padapter, (u8)bStartTest); break; @@ -1461,7 +1592,9 @@ int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) rtw_msleep_os(5); } #ifdef CONFIG_80211N_HT - pmp_priv->tx.attrib.ht_en = 1; + if(padapter->registrypriv.ht_enable && + is_supported_ht(padapter->registrypriv.wireless_mode)) + pmp_priv->tx.attrib.ht_en = 1; #endif pmp_priv->tx.stop = 0; pmp_priv->tx.count = 1; @@ -1491,10 +1624,12 @@ int rtw_mp_tx(struct net_device *dev, HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct mp_priv *pmp_priv = &padapter->mppriv; PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); - struct registry_priv *pregistrypriv = &padapter->registrypriv; - + char *pextra = extra; u32 bandwidth = 0, sg = 0, channel = 6, txpower = 40, rate = 108, ant = 0, txmode = 1, count = 0; - u8 i = 0, j = 0, bStartTest = 1, status = 0, Idx = 0, tmpU1B = 0; + u8 bStartTest = 1, status = 0; +#ifdef CONFIG_MP_VHT_HW_TX_MODE + u8 Idx = 0, tmpU1B; +#endif u16 antenna = 0; if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) @@ -1522,13 +1657,13 @@ int rtw_mp_tx(struct net_device *dev, return 0; } else if (strncmp(extra, "setting", 7) == 0) { _rtw_memset(extra, 0, wrqu->data.length); - sprintf(extra, "Current Setting :\n Channel:%d", pmp_priv->channel); - sprintf(extra, "%s\n Bandwidth:%d", extra, pmp_priv->bandwidth); - sprintf(extra, "%s\n Rate index:%d", extra, pmp_priv->rateidx); - sprintf(extra, "%s\n TxPower index:%d", extra, pmp_priv->txpoweridx); - sprintf(extra, "%s\n Antenna TxPath:%d", extra, pmp_priv->antenna_tx); - sprintf(extra, "%s\n Antenna RxPath:%d", extra, pmp_priv->antenna_rx); - sprintf(extra, "%s\n MP Mode:%d", extra, pmp_priv->mode); + pextra += sprintf(pextra, "Current Setting :\n Channel:%d", pmp_priv->channel); + pextra += sprintf(pextra, "\n Bandwidth:%d", pmp_priv->bandwidth); + pextra += sprintf(pextra, "\n Rate index:%d", pmp_priv->rateidx); + pextra += sprintf(pextra, "\n TxPower index:%d", pmp_priv->txpoweridx); + pextra += sprintf(pextra, "\n Antenna TxPath:%d", pmp_priv->antenna_tx); + pextra += sprintf(pextra, "\n Antenna RxPath:%d", pmp_priv->antenna_rx); + pextra += sprintf(pextra, "\n MP Mode:%d", pmp_priv->mode); wrqu->data.length = strlen(extra); return 0; #ifdef CONFIG_MP_VHT_HW_TX_MODE @@ -1666,22 +1801,23 @@ int rtw_mp_tx(struct net_device *dev, if (sscanf(extra, "ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d", &channel, &bandwidth, &rate, &txpower, &ant, &txmode) < 6) { RTW_INFO("Invalid format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode); _rtw_memset(extra, 0, wrqu->data.length); - sprintf(extra, "\n Please input correct format as bleow:\n"); - sprintf(extra, "%s\t ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d\n", extra, channel, bandwidth, rate, txpower, ant, txmode); - sprintf(extra, "%s\n [ ch : BGN = <1~14> , A or AC = <36~165> ]", extra); - sprintf(extra, "%s\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]", extra); - sprintf(extra, "%s\n [ rate : CCK: 1 2 5.5 11M X 2 = < 2 4 11 22 >]", extra); - sprintf(extra, "%s\n [ OFDM: 6 9 12 18 24 36 48 54M X 2 = < 12 18 24 36 48 72 96 108>", extra); - sprintf(extra, "%s\n [ HT 1S2SS MCS0 ~ MCS15 : < [MCS0]=128 ~ [MCS7]=135 ~ [MCS15]=143 >", extra); - sprintf(extra, "%s\n [ HT 3SS MCS16 ~ MCS32 : < [MCS16]=144 ~ [MCS23]=151 ~ [MCS32]=159 >", extra); - sprintf(extra, "%s\n [ VHT 1SS MCS0 ~ MCS9 : < [MCS0]=160 ~ [MCS9]=169 >", extra); - sprintf(extra, "%s\n [ txpower : 1~63 power index", extra); - sprintf(extra, "%s\n [ ant : ,2T ex: AB=3 BC=6 CD=12", extra); - sprintf(extra, "%s\n [ txmode : < 0 = CONTINUOUS_TX, 1 = PACKET_TX, 2 = SINGLE_TONE_TX, 3 = CARRIER_SUPPRISSION_TX, 4 = SINGLE_CARRIER_TX>\n", extra); + pextra += sprintf(pextra, "\n Please input correct format as bleow:\n"); + pextra += sprintf(pextra, "\t ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d\n", channel, bandwidth, rate, txpower, ant, txmode); + pextra += sprintf(pextra, "\n [ ch : BGN = <1~14> , A or AC = <36~165> ]"); + pextra += sprintf(pextra, "\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]"); + pextra += sprintf(pextra, "\n [ rate : CCK: 1 2 5.5 11M X 2 = < 2 4 11 22 >]"); + pextra += sprintf(pextra, "\n [ OFDM: 6 9 12 18 24 36 48 54M X 2 = < 12 18 24 36 48 72 96 108>"); + pextra += sprintf(pextra, "\n [ HT 1S2SS MCS0 ~ MCS15 : < [MCS0]=128 ~ [MCS7]=135 ~ [MCS15]=143 >"); + pextra += sprintf(pextra, "\n [ HT 3SS MCS16 ~ MCS32 : < [MCS16]=144 ~ [MCS23]=151 ~ [MCS32]=159 >"); + pextra += sprintf(pextra, "\n [ VHT 1SS MCS0 ~ MCS9 : < [MCS0]=160 ~ [MCS9]=169 >"); + pextra += sprintf(pextra, "\n [ txpower : 1~63 power index"); + pextra += sprintf(pextra, "\n [ ant : ,2T ex: AB=3 BC=6 CD=12"); + pextra += sprintf(pextra, "\n [ txmode : < 0 = CONTINUOUS_TX, 1 = PACKET_TX, 2 = SINGLE_TONE_TX, 3 = CARRIER_SUPPRISSION_TX, 4 = SINGLE_CARRIER_TX>\n"); wrqu->data.length = strlen(extra); return status; } else { + char *pextra = extra; RTW_INFO("Got format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode); _rtw_memset(extra, 0, wrqu->data.length); sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel); @@ -1693,18 +1829,20 @@ int rtw_mp_tx(struct net_device *dev, bandwidth = CHANNEL_WIDTH_40; else if (bandwidth == 2) bandwidth = CHANNEL_WIDTH_80; - sprintf(extra, "%s\nChange Current Bandwidth %d to Bandwidth %d", extra, padapter->mppriv.bandwidth , bandwidth); + pextra = extra + strlen(pextra); + pextra += sprintf(pextra, "\nChange Current Bandwidth %d to Bandwidth %d", padapter->mppriv.bandwidth, bandwidth); padapter->mppriv.bandwidth = (u8)bandwidth; padapter->mppriv.preamble = sg; SetBandwidth(padapter); pHalData->current_channel_bw = bandwidth; - sprintf(extra, "%s\nSet power level :%d", extra, txpower); + pextra += sprintf(pextra, "\nSet power level :%d", txpower); padapter->mppriv.txpoweridx = (u8)txpower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)txpower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)txpower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)txpower; - pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)txpower; + pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)txpower; + pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)txpower; + pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)txpower; + pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)txpower; + SetTxPower(padapter); RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth, sg); @@ -1722,13 +1860,13 @@ int rtw_mp_tx(struct net_device *dev, RTW_INFO("%s: rate index=%d\n", __func__, rate); if (rate >= MPT_RATE_LAST) return -EINVAL; - sprintf(extra, "%s\nSet data rate to %d index %d", extra, padapter->mppriv.rateidx, rate); + pextra += sprintf(pextra, "\nSet data rate to %d index %d", padapter->mppriv.rateidx, rate); padapter->mppriv.rateidx = rate; pMptCtx->mpt_rate_index = rate; SetDataRate(padapter); - sprintf(extra, "%s\nSet Antenna Path :%d", extra, ant); + pextra += sprintf(pextra, "\nSet Antenna Path :%d", ant); switch (ant) { case 1: antenna = ANTENNA_A; @@ -1808,8 +1946,7 @@ int rtw_mp_rx(struct net_device *dev, PADAPTER padapter = rtw_netdev_priv(dev); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct mp_priv *pmp_priv = &padapter->mppriv; - PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); - + char *pextra = extra; u32 bandwidth = 0, sg = 0, channel = 6, ant = 0; u16 antenna = 0; u8 bStartRx = 0; @@ -1836,15 +1973,16 @@ int rtw_mp_rx(struct net_device *dev, } else if (sscanf(extra, "ch=%d,bw=%d,ant=%d", &channel, &bandwidth, &ant) < 3) { RTW_INFO("Invalid format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant); _rtw_memset(extra, 0, wrqu->data.length); - sprintf(extra, "\n Please input correct format as bleow:\n"); - sprintf(extra, "%s\t ch=%d,bw=%d,ant=%d\n", extra, channel, bandwidth, ant); - sprintf(extra, "%s\n [ ch : BGN = <1~14> , A or AC = <36~165> ]", extra); - sprintf(extra, "%s\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]", extra); - sprintf(extra, "%s\n [ ant : ,2T ex: AB=3 BC=6 CD=12", extra); + pextra += sprintf(pextra, "\n Please input correct format as bleow:\n"); + pextra += sprintf(pextra, "\t ch=%d,bw=%d,ant=%d\n", channel, bandwidth, ant); + pextra += sprintf(pextra, "\n [ ch : BGN = <1~14> , A or AC = <36~165> ]"); + pextra += sprintf(pextra, "\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]"); + pextra += sprintf(pextra, "\n [ ant : ,2T ex: AB=3 BC=6 CD=12"); wrqu->data.length = strlen(extra); return 0; } else { + char *pextra = extra; bStartRx = 1; RTW_INFO("Got format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant); _rtw_memset(extra, 0, wrqu->data.length); @@ -1857,13 +1995,14 @@ int rtw_mp_rx(struct net_device *dev, bandwidth = CHANNEL_WIDTH_40; else if (bandwidth == 2) bandwidth = CHANNEL_WIDTH_80; - sprintf(extra, "%s\nChange Current Bandwidth %d to Bandwidth %d", extra, padapter->mppriv.bandwidth , bandwidth); + pextra = extra + strlen(extra); + pextra += sprintf(pextra, "\nChange Current Bandwidth %d to Bandwidth %d", padapter->mppriv.bandwidth, bandwidth); padapter->mppriv.bandwidth = (u8)bandwidth; padapter->mppriv.preamble = sg; SetBandwidth(padapter); pHalData->current_channel_bw = bandwidth; - sprintf(extra, "%s\nSet Antenna Path :%d", extra, ant); + pextra += sprintf(pextra, "\nSet Antenna Path :%d", ant); switch (ant) { case 1: antenna = ANTENNA_A; @@ -1914,7 +2053,7 @@ int rtw_mp_rx(struct net_device *dev, pHalData->antenna_tx_path = antenna; SetAntenna(padapter); - sprintf(extra, "%s\nstart Rx", extra); + strcat(extra, "\nstart Rx"); SetPacketRx(padapter, bStartRx, _FALSE); } wrqu->data.length = strlen(extra); @@ -1927,7 +2066,6 @@ int rtw_mp_hwtx(struct net_device *dev, union iwreq_data *wrqu, char *extra) { PADAPTER padapter = rtw_netdev_priv(dev); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct mp_priv *pmp_priv = &padapter->mppriv; PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); @@ -1939,16 +2077,79 @@ int rtw_mp_hwtx(struct net_device *dev, _rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(RT_PMAC_TX_INFO)); _rtw_memcpy((void *)&pMptCtx->PMacTxInfo, (void *)input, sizeof(RT_PMAC_TX_INFO)); + _rtw_memset(wrqu->data.pointer, 0, wrqu->data.length); - mpt_ProSetPMacTx(padapter); - sprintf(extra, "Set PMac Tx Mode start\n"); - + if (pMptCtx->PMacTxInfo.bEnPMacTx == 1 && pmp_priv->mode != MP_ON) { + sprintf(extra, "MP Tx Running, Please Set PMac Tx Mode Stop\n"); + RTW_INFO("Error !!! MP Tx Running, Please Set PMac Tx Mode Stop\n"); + } else { + RTW_INFO("To set MAC Tx mode\n"); + mpt_ProSetPMacTx(padapter); + sprintf(extra, "Set PMac Tx Mode OK\n"); + } wrqu->data.length = strlen(extra); #endif return 0; } +int rtw_mp_pwrlmt(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + struct registry_priv *registry_par = &padapter->registrypriv; + u8 pwrlimtstat = 0; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + *(extra + wrqu->data.length) = '\0'; +#ifdef CONFIG_TXPWR_LIMIT + pwrlimtstat = registry_par->RegEnableTxPowerLimit; + if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { + padapter->registrypriv.RegEnableTxPowerLimit = 0; + sprintf(extra, "Turn off Power Limit\n"); + + } else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) { + padapter->registrypriv.RegEnableTxPowerLimit = 1; + sprintf(extra, "Turn on Power Limit\n"); + + } else +#endif + sprintf(extra, "Get Power Limit Status:%s\n", (pwrlimtstat == 1) ? "ON" : "OFF"); + + + wrqu->data.length = strlen(extra); + return 0; +} + +int rtw_mp_pwrbyrate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + *(extra + wrqu->data.length) = '\0'; + if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { + padapter->registrypriv.RegEnableTxPowerByRate = 0; + sprintf(extra, "Turn off Tx Power by Rate\n"); + + } else if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) { + padapter->registrypriv.RegEnableTxPowerByRate = 1; + sprintf(extra, "Turn On Tx Power by Rate\n"); + + } else { + sprintf(extra, "Get Power by Rate Status:%s\n", (padapter->registrypriv.RegEnableTxPowerByRate == 1) ? "ON" : "OFF"); + } + + wrqu->data.length = strlen(extra); + return 0; +} + int rtw_efuse_mask_file(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) @@ -1962,6 +2163,7 @@ int rtw_efuse_mask_file(struct net_device *dev, if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; + *(extra + wrqu->data.length) = '\0'; if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { padapter->registrypriv.boffefusemask = 1; sprintf(extra, "Turn off Efuse Mask\n"); @@ -1975,11 +2177,10 @@ int rtw_efuse_mask_file(struct net_device *dev, return 0; } if (strncmp(extra, "data,", 5) == 0) { - u8 *pch, *pdata; + u8 *pch; char *ptmp, tmp; u8 count = 0; u8 i = 0; - u32 datalen = 0; ptmp = extra; pch = strsep(&ptmp, ","); @@ -2019,9 +2220,14 @@ int rtw_efuse_mask_file(struct net_device *dev, if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) { RTW_INFO("%s do rtw_efuse_mask_file_read = %s! ,sizeof maskfileBuffer %zu\n", __func__, rtw_efuse_mask_file_path, sizeof(maskfileBuffer)); Status = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, maskfileBuffer, sizeof(maskfileBuffer)); - if (Status == _TRUE) + if (Status == _TRUE) { padapter->registrypriv.bFileMaskEfuse = _TRUE; - sprintf(extra, "efuse mask file read OK\n"); + sprintf(extra, "efuse mask file read OK\n"); + } else { + padapter->registrypriv.bFileMaskEfuse = _FALSE; + sprintf(extra, "read efuse mask file FAIL\n"); + RTW_INFO("%s rtw_efuse_file_read mask fail!\n", __func__); + } } else { padapter->registrypriv.bFileMaskEfuse = _FALSE; sprintf(extra, "efuse mask file readable FAIL\n"); @@ -2069,6 +2275,43 @@ int rtw_efuse_file_map(struct net_device *dev, return 0; } +int rtw_bt_efuse_file_map(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *rtw_efuse_file_map_path; + u8 Status; + PEFUSE_HAL pEfuseHal; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; + + pEfuseHal = &pHalData->EfuseHal; + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + rtw_efuse_file_map_path = extra; + + _rtw_memset(pEfuseHal->fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); + + if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) { + RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path); + Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeBTEfuseModifiedMap, sizeof(pEfuseHal->fakeBTEfuseModifiedMap)); + if (Status == _TRUE) { + pmp_priv->bloadBTefusemap = _TRUE; + sprintf(extra, "BT efuse file file_read OK\n"); + } else { + pmp_priv->bloadBTefusemap = _FALSE; + sprintf(extra, "BT efuse file file_read FAIL\n"); + } + } else { + sprintf(extra, "BT efuse file readable FAIL\n"); + RTW_INFO("%s rtw_is_file_readable fail!\n", __func__); + } + wrqu->data.length = strlen(extra); + return 0; +} + #if defined(CONFIG_RTL8723B) int rtw_mp_SetBT(struct net_device *dev, struct iw_request_info *info, @@ -2094,6 +2337,9 @@ int rtw_mp_SetBT(struct net_device *dev, if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) return -EFAULT; + + *(extra + wrqu->data.length) = '\0'; + if (strlen(extra) < 1) return -EFAULT; @@ -2110,7 +2356,7 @@ int rtw_mp_SetBT(struct net_device *dev, if (strncmp(extra, "dlbt", 4) == 0) { pHalData->LastHMEBoxNum = 0; - padapter->bBTFWReady = _FALSE; + pHalData->bBTFWReady = _FALSE; rtw_write8(padapter, 0xa3, 0x05); BTStatus = rtw_read8(padapter, 0xa0); RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus); @@ -2142,7 +2388,7 @@ int rtw_mp_SetBT(struct net_device *dev, pBTFirmware = (PRT_MP_FIRMWARE)rtw_zmalloc(sizeof(RT_MP_FIRMWARE)); if (pBTFirmware == NULL) goto exit; - padapter->bBTFWReady = _FALSE; + pHalData->bBTFWReady = _FALSE; FirmwareDownloadBT(padapter, pBTFirmware); if (pBTFirmware) rtw_mfree((u8 *)pBTFirmware, sizeof(RT_MP_FIRMWARE)); @@ -2171,7 +2417,7 @@ int rtw_mp_SetBT(struct net_device *dev, } if (strncmp(extra, "dlfw", 4) == 0) { pHalData->LastHMEBoxNum = 0; - padapter->bBTFWReady = _FALSE; + pHalData->bBTFWReady = _FALSE; rtw_write8(padapter, 0xa3, 0x05); BTStatus = rtw_read8(padapter, 0xa0); RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus); @@ -2279,7 +2525,7 @@ int rtw_mp_SetBT(struct net_device *dev, } if (strncmp(extra, "h2c", 3) == 0) { RTW_INFO("SetBT h2c !\n"); - padapter->bBTFWReady = _TRUE; + pHalData->bBTFWReady = _TRUE; rtw_hal_fill_h2c_cmd(padapter, 0x63, 1, u1H2CBtMpOperParm); goto exit; } @@ -2380,7 +2626,7 @@ int rtw_mp_SetBT(struct net_device *dev, todo: _rtw_memset(extra, '\0', wrqu->data.length); - if (padapter->bBTFWReady == _FALSE) { + if (pHalData->bBTFWReady == _FALSE) { sprintf(extra, "BTFWReady = FALSE.\n"); goto exit; } diff --git a/os_dep/linux/mlme_linux.c b/os_dep/linux/mlme_linux.c index cffdbcf..39c0ac1 100644 --- a/os_dep/linux/mlme_linux.c +++ b/os_dep/linux/mlme_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _MLME_OSDEP_C_ @@ -72,7 +67,13 @@ void rtw_os_indicate_connect(_adapter *adapter) #endif /* CONFIG_IOCTL_CFG80211 */ rtw_indicate_wx_assoc_event(adapter); - netif_carrier_on(adapter->pnetdev); + +#ifdef CONFIG_RTW_MESH +#if CONFIG_RTW_MESH_CTO_MGATE_CARRIER + if (!rtw_mesh_cto_mgate_required(adapter)) +#endif +#endif + rtw_netif_carrier_on(adapter->pnetdev); if (adapter->pid[2] != 0) rtw_signal_process(adapter->pid[2], SIGALRM); @@ -101,7 +102,6 @@ void rtw_reset_securitypriv(_adapter *adapter) u32 backupTKIPcountermeasure_time = 0; /* add for CONFIG_IEEE80211W, none 11w also can use */ _irqL irqL; - struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; _enter_critical_bh(&adapter->security_key_mutex, &irqL); @@ -118,10 +118,6 @@ void rtw_reset_securitypriv(_adapter *adapter) backupPMKIDIndex = adapter->securitypriv.PMKIDIndex; backupTKIPCountermeasure = adapter->securitypriv.btkip_countermeasure; backupTKIPcountermeasure_time = adapter->securitypriv.btkip_countermeasure_time; -#ifdef CONFIG_IEEE80211W - /* reset RX BIP packet number */ - pmlmeext->mgnt_80211w_IPN_rx = 0; -#endif /* CONFIG_IEEE80211W */ _rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof(struct security_priv)); /* Added by Albert 2009/02/18 */ @@ -161,7 +157,7 @@ void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_gener /* RT_PMKID_LIST backupPMKIDList[NUM_PMKID_CACHE]; */ - netif_carrier_off(adapter->pnetdev); /* Do it first for tx broadcast pkt after disconnection issue! */ + rtw_netif_carrier_off(adapter->pnetdev); /* Do it first for tx broadcast pkt after disconnection issue! */ #ifdef CONFIG_IOCTL_CFG80211 rtw_cfg80211_indicate_disconnect(adapter, reason, locally_generated); @@ -233,16 +229,16 @@ void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta) if (psta == NULL) return; - if (psta->aid > NUM_STA) + if (psta->cmn.aid > pstapriv->max_aid) return; - if (pstapriv->sta_aid[psta->aid - 1] != psta) + if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta) return; wrqu.addr.sa_family = ARPHRD_ETHER; - _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN); RTW_INFO("+rtw_indicate_sta_assoc_event\n"); @@ -260,16 +256,16 @@ void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta) if (psta == NULL) return; - if (psta->aid > NUM_STA) + if (psta->cmn.aid > pstapriv->max_aid) return; - if (pstapriv->sta_aid[psta->aid - 1] != psta) + if (pstapriv->sta_aid[psta->cmn.aid - 1] != psta) return; wrqu.addr.sa_family = ARPHRD_ETHER; - _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(wrqu.addr.sa_data, psta->cmn.mac_addr, ETH_ALEN); RTW_INFO("+rtw_indicate_sta_disassoc_event\n"); @@ -303,7 +299,7 @@ static int mgnt_netdev_open(struct net_device *pnetdev) rtw_netif_wake_queue(pnetdev); - netif_carrier_on(pnetdev); + rtw_netif_carrier_on(pnetdev); /* rtw_write16(phostapdpriv->padapter, 0x0116, 0x0100); */ /* only excluding beacon */ @@ -317,7 +313,7 @@ static int mgnt_netdev_close(struct net_device *pnetdev) usb_kill_anchored_urbs(&phostapdpriv->anchored); - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); @@ -387,9 +383,6 @@ int hostapd_mode_init(_adapter *padapter) /* pnetdev->wireless_handlers = NULL; */ -#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX - pnetdev->features |= NETIF_F_IP_CSUM; -#endif @@ -410,7 +403,7 @@ int hostapd_mode_init(_adapter *padapter) _rtw_memcpy(pnetdev->dev_addr, mac, ETH_ALEN); - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); /* Tell the network stack we exist */ diff --git a/os_dep/linux/os_intfs.c b/os_dep/linux/os_intfs.c index 03ad593..4e10ee6 100644 --- a/os_dep/linux/os_intfs.c +++ b/os_dep/linux/os_intfs.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _OS_INTFS_C_ #include @@ -38,20 +33,21 @@ MODULE_VERSION(DRIVERVERSION); int rtw_chip_version = 0x00; int rtw_rfintfs = HWPI; int rtw_lbkmode = 0;/* RTL8712_AIR_TRX; */ - - +#ifdef DBG_LA_MODE +int rtw_la_mode_en=1; +module_param(rtw_la_mode_en, int, 0644); +#endif int rtw_network_mode = Ndis802_11IBSS;/* Ndis802_11Infrastructure; */ /* infra, ad-hoc, auto */ /* NDIS_802_11_SSID ssid; */ int rtw_channel = 1;/* ad-hoc support requirement */ int rtw_wireless_mode = WIRELESS_MODE_MAX; +module_param(rtw_wireless_mode, int, 0644); int rtw_vrtl_carrier_sense = AUTO_VCS; int rtw_vcs_type = RTS_CTS; int rtw_rts_thresh = 2347; int rtw_frag_thresh = 2346; int rtw_preamble = PREAMBLE_LONG;/* long, short, auto */ int rtw_scan_mode = 1;/* active, passive */ -int rtw_adhoc_tx_pwr = 1; -int rtw_soft_ap = 0; /* int smart_ps = 1; */ #ifdef CONFIG_POWER_SAVING int rtw_power_mgnt = PS_MODE_MAX; @@ -59,28 +55,57 @@ int rtw_soft_ap = 0; int rtw_ips_mode = IPS_LEVEL_2; #else int rtw_ips_mode = IPS_NORMAL; - #endif + #endif /*CONFIG_IPS_LEVEL_2*/ + + #ifdef CONFIG_USB_HCI + int rtw_lps_level = LPS_NORMAL; /*USB default LPS level*/ + #else /*SDIO,PCIE*/ + #if defined(CONFIG_LPS_PG) + /*int rtw_lps_level = LPS_PG;*//*FW not support yet*/ + int rtw_lps_level = LPS_LCLK; + #elif defined(CONFIG_LPS_PG_DDMA) + int rtw_lps_level = LPS_PG; + #elif defined(CONFIG_LPS_LCLK) + int rtw_lps_level = LPS_LCLK; + #else + int rtw_lps_level = LPS_NORMAL; + #endif + #endif/*CONFIG_USB_HCI*/ + int rtw_lps_chk_by_tp = 1; #else /* !CONFIG_POWER_SAVING */ int rtw_power_mgnt = PS_MODE_ACTIVE; int rtw_ips_mode = IPS_NONE; + int rtw_lps_level = LPS_NORMAL; + int rtw_lps_chk_by_tp = 0; #endif /* CONFIG_POWER_SAVING */ -#if defined(CONFIG_LPS_PG) -/*int rtw_lps_level = LPS_PG;*//*FW not support yet*/ -int rtw_lps_level = LPS_LCLK; -#elif defined(CONFIG_LPS_LCLK) -int rtw_lps_level = LPS_LCLK; -#else -int rtw_lps_level = LPS_NORMAL; -#endif + module_param(rtw_ips_mode, int, 0644); MODULE_PARM_DESC(rtw_ips_mode, "The default IPS mode"); module_param(rtw_lps_level, int, 0644); MODULE_PARM_DESC(rtw_lps_level, "The default LPS level"); +module_param(rtw_lps_chk_by_tp, int, 0644); + +/* LPS: + * rtw_smart_ps = 0 => TX: pwr bit = 1, RX: PS_Poll + * rtw_smart_ps = 1 => TX: pwr bit = 0, RX: PS_Poll + * rtw_smart_ps = 2 => TX: pwr bit = 0, RX: NullData with pwr bit = 0 +*/ int rtw_smart_ps = 2; +int rtw_max_bss_cnt = 0; +module_param(rtw_max_bss_cnt, int, 0644); +#ifdef CONFIG_WMMPS_STA +/* WMMPS: + * rtw_smart_ps = 0 => Only for fw test + * rtw_smart_ps = 1 => Refer to Beacon's TIM Bitmap + * rtw_smart_ps = 2 => Don't refer to Beacon's TIM Bitmap +*/ +int rtw_wmm_smart_ps = 2; +#endif /* CONFIG_WMMPS_STA */ + int rtw_check_fw_ps = 1; #ifdef CONFIG_TX_EARLY_MODE @@ -96,6 +121,7 @@ module_param(rtw_dynamic_agg_enable, int, 0644); /* set log level when inserting driver module, default log level is _DRV_INFO_ = 4, * please refer to "How_to_set_driver_debug_log_level.doc" to set the available level. */ +#ifdef CONFIG_RTW_DEBUG #ifdef RTW_LOG_LEVEL uint rtw_drv_log_level = (uint)RTW_LOG_LEVEL; /* from Makefile */ #else @@ -103,7 +129,7 @@ module_param(rtw_dynamic_agg_enable, int, 0644); #endif module_param(rtw_drv_log_level, uint, 0644); MODULE_PARM_DESC(rtw_drv_log_level, "set log level when insert driver module, default log level is _DRV_INFO_ = 4"); - +#endif int rtw_radio_enable = 1; int rtw_long_retry_lmt = 7; int rtw_short_retry_lmt = 7; @@ -125,15 +151,18 @@ int rtw_software_decrypt = 0; int rtw_acm_method = 0;/* 0:By SW 1:By HW. */ int rtw_wmm_enable = 1;/* default is set to enable the wmm. */ -int rtw_uapsd_enable = 0; + +#ifdef CONFIG_WMMPS_STA +/* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */ +/* 0: NO_LIMIT, 1: TWO_MSDU, 2: FOUR_MSDU, 3: SIX_MSDU */ int rtw_uapsd_max_sp = NO_LIMIT; -int rtw_uapsd_acbk_en = 0; -int rtw_uapsd_acbe_en = 0; -int rtw_uapsd_acvi_en = 0; -int rtw_uapsd_acvo_en = 0; +/* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */ +int rtw_uapsd_ac_enable = 0x0; +#endif /* CONFIG_WMMPS_STA */ + #if defined(CONFIG_RTL8814A) int rtw_pwrtrim_enable = 2; /* disable kfree , rename to power trim disable */ -#elif defined(CONFIG_RTL8821C) /*|| defined(CONFIG_RTL8822B)*/ +#elif defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) /*PHYDM API, must enable by default*/ int rtw_pwrtrim_enable = 1; #else @@ -144,12 +173,21 @@ uint rtw_tx_bw_mode = 0x21; module_param(rtw_tx_bw_mode, uint, 0644); MODULE_PARM_DESC(rtw_tx_bw_mode, "The max tx bw for 2.4G and 5G. format is the same as rtw_bw_mode"); +#ifdef CONFIG_FW_HANDLE_TXBCN +uint rtw_tbtt_rpt = 0; /*ROOT AP - BIT0, VAP1 - BIT1, VAP2 - BIT2, VAP3 - VAP3, FW report TBTT INT by C2H*/ +module_param(rtw_tbtt_rpt, uint, 0644); +#endif + #ifdef CONFIG_80211N_HT int rtw_ht_enable = 1; /* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz * 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 * 0x21 means enable 2.4G 40MHz & 5G 80MHz */ +#ifdef CONFIG_RTW_CUSTOMIZE_BWMODE +int rtw_bw_mode = CONFIG_RTW_CUSTOMIZE_BWMODE; +#else int rtw_bw_mode = 0x21; +#endif int rtw_ampdu_enable = 1;/* for enable tx_ampdu , */ /* 0: disable, 0x1:enable */ int rtw_rx_stbc = 1;/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */ #if (defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)) && defined(CONFIG_PCI_HCI) @@ -221,7 +259,7 @@ MODULE_PARM_DESC(rtw_vht_rx_mcs_map, "VHT RX MCS map"); int rtw_lowrate_two_xmit = 1;/* Use 2 path Tx to transmit MCS0~7 and legacy mode */ -int rtw_rf_config = RF_TYPE_AUTO; +int rtw_rf_config = RF_TYPE_MAX; module_param(rtw_rf_config, int, 0644); /* 0: not check in watch dog, 1: check in watch dog */ @@ -234,12 +272,6 @@ int rtw_low_power = 0; int rtw_wifi_spec = 0; #endif -#ifdef CONFIG_DEFAULT_PATTERNS_EN - bool rtw_support_default_patterns = _TRUE; -#else - bool rtw_support_default_patterns = _FALSE; -#endif - int rtw_special_rf_path = 0; /* 0: 2T2R ,1: only turn on path A 1T1R */ char rtw_country_unspecified[] = {0xFF, 0xFF, 0x00}; @@ -247,7 +279,7 @@ char *rtw_country_code = rtw_country_unspecified; module_param(rtw_country_code, charp, 0644); MODULE_PARM_DESC(rtw_country_code, "The default country code (in alpha2)"); -int rtw_channel_plan = RTW_CHPLAN_MAX; +int rtw_channel_plan = CONFIG_RTW_CHPLAN; module_param(rtw_channel_plan, int, 0644); MODULE_PARM_DESC(rtw_channel_plan, "The default chplan ID when rtw_alpha2 is not specified or valid"); @@ -321,22 +353,11 @@ int rtw_80211d = 0; #ifdef CONFIG_PCI_ASPM /* CLK_REQ:BIT0 L0s:BIT1 ASPM_L1:BIT2 L1Off:BIT3*/ -int rtw_pci_aspm_enable = 0xF; +int rtw_pci_aspm_enable = 0x5; #else int rtw_pci_aspm_enable; #endif -#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV -int rtw_force_ant = 2;/* 0 :normal, 1:Main ant, 2:Aux ant */ -int rtw_force_igi = 0; /* 0 :normal */ -module_param(rtw_force_ant, int, 0644); -module_param(rtw_force_igi, int, 0644); -#endif - -int rtw_force_igi_lb = CONFIG_RTW_FORCE_IGI_LB; -module_param(rtw_force_igi_lb, int, 0644); -MODULE_PARM_DESC(rtw_force_igi_lb, "force IGI low-bound, 0:no specified"); - #ifdef CONFIG_QOS_OPTIMIZATION int rtw_qos_opt_enable = 1; /* 0: disable,1:enable */ #else @@ -344,13 +365,17 @@ int rtw_qos_opt_enable = 0; /* 0: disable,1:enable */ #endif module_param(rtw_qos_opt_enable, int, 0644); -#ifdef CONFIG_AUTO_CHNL_SEL_NHM -int rtw_acs_mode = 1; /*0:disable, 1:enable*/ -module_param(rtw_acs_mode, int, 0644); - +#ifdef CONFIG_RTW_ACS int rtw_acs_auto_scan = 0; /*0:disable, 1:enable*/ module_param(rtw_acs_auto_scan, int, 0644); +int rtw_acs = 1; +module_param(rtw_acs, int, 0644); +#endif + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +int rtw_nm = 1;/*noise monitor*/ +module_param(rtw_nm, int, 0644); #endif char *ifname = "wlan%d"; @@ -377,7 +402,9 @@ char *rtw_initmac = 0; /* temp mac address if users want to use instead of the #endif #endif - +#ifdef CONFIG_AP_MODE +u8 rtw_bmc_tx_rate = MGN_UNKNOWN; +#endif module_param(rtw_pwrtrim_enable, int, 0644); module_param(rtw_initmac, charp, 0644); module_param(rtw_special_rf_path, int, 0644); @@ -388,6 +415,11 @@ module_param(rtw_network_mode, int, 0644); module_param(rtw_channel, int, 0644); module_param(rtw_mp_mode, int, 0644); module_param(rtw_wmm_enable, int, 0644); +#ifdef CONFIG_WMMPS_STA +module_param(rtw_uapsd_max_sp, int, 0644); +module_param(rtw_uapsd_ac_enable, int, 0644); +module_param(rtw_wmm_smart_ps, int, 0644); +#endif /* CONFIG_WMMPS_STA */ module_param(rtw_vrtl_carrier_sense, int, 0644); module_param(rtw_vcs_type, int, 0644); module_param(rtw_busy_thresh, int, 0644); @@ -477,6 +509,14 @@ module_param(rtw_80211d, int, 0644); MODULE_PARM_DESC(rtw_80211d, "Enable 802.11d mechanism"); #endif +#ifdef CONFIG_ADVANCE_OTA +/* BIT(0): OTA continuous rotated test within low RSSI,1R CCA in path B + BIT(1) & BIT(2): OTA continuous rotated test with low high RSSI */ +/* Experimental environment: shielding room with half of absorber and 2~3 rotation per minute */ +int rtw_advnace_ota; +module_param(rtw_advnace_ota, int, 0644); +#endif + uint rtw_notch_filter = RTW_NOTCH_FILTER; module_param(rtw_notch_filter, uint, 0644); MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P"); @@ -493,14 +533,6 @@ uint rtw_adaptivity_mode = CONFIG_RTW_ADAPTIVITY_MODE; module_param(rtw_adaptivity_mode, uint, 0644); MODULE_PARM_DESC(rtw_adaptivity_mode, "0:normal, 1:carrier sense"); -uint rtw_adaptivity_dml = CONFIG_RTW_ADAPTIVITY_DML; -module_param(rtw_adaptivity_dml, uint, 0644); -MODULE_PARM_DESC(rtw_adaptivity_dml, "0:disable, 1:enable"); - -uint rtw_adaptivity_dc_backoff = CONFIG_RTW_ADAPTIVITY_DC_BACKOFF; -module_param(rtw_adaptivity_dc_backoff, uint, 0644); -MODULE_PARM_DESC(rtw_adaptivity_dc_backoff, "DC backoff for Adaptivity"); - int rtw_adaptivity_th_l2h_ini = CONFIG_RTW_ADAPTIVITY_TH_L2H_INI; module_param(rtw_adaptivity_th_l2h_ini, int, 0644); MODULE_PARM_DESC(rtw_adaptivity_th_l2h_ini, "th_l2h_ini for Adaptivity"); @@ -567,7 +599,6 @@ uint rtw_rxgain_offset_5gh = 0; module_param(rtw_rxgain_offset_5gh, uint, 0644); MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GL Offset value:0"); - uint rtw_pll_ref_clk_sel = CONFIG_RTW_PLL_REF_CLK_SEL; module_param(rtw_pll_ref_clk_sel, uint, 0644); MODULE_PARM_DESC(rtw_pll_ref_clk_sel, "force pll_ref_clk_sel, 0xF:use autoload value"); @@ -576,9 +607,11 @@ int rtw_tx_pwr_by_rate = CONFIG_TXPWR_BY_RATE_EN; module_param(rtw_tx_pwr_by_rate, int, 0644); MODULE_PARM_DESC(rtw_tx_pwr_by_rate, "0:Disable, 1:Enable, 2: Depend on efuse"); +#ifdef CONFIG_TXPWR_LIMIT int rtw_tx_pwr_lmt_enable = CONFIG_TXPWR_LIMIT_EN; module_param(rtw_tx_pwr_lmt_enable, int, 0644); MODULE_PARM_DESC(rtw_tx_pwr_lmt_enable, "0:Disable, 1:Enable, 2: Depend on efuse"); +#endif static int rtw_target_tx_pwr_2g_a[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_A; static int rtw_target_tx_pwr_2g_a_num = 0; @@ -622,6 +655,14 @@ module_param_array(rtw_target_tx_pwr_5g_d, int, &rtw_target_tx_pwr_5g_d_num, 064 MODULE_PARM_DESC(rtw_target_tx_pwr_5g_d, "5G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined"); #endif /* CONFIG_IEEE80211_BAND_5GHZ */ +int rtw_tsf_update_pause_factor = CONFIG_TSF_UPDATE_PAUSE_FACTOR; +module_param(rtw_tsf_update_pause_factor, int, 0644); +MODULE_PARM_DESC(rtw_tsf_update_pause_factor, "num of bcn intervals to stay TSF update pause status"); + +int rtw_tsf_update_restore_factor = CONFIG_TSF_UPDATE_RESTORE_FACTOR; +module_param(rtw_tsf_update_restore_factor, int, 0644); +MODULE_PARM_DESC(rtw_tsf_update_restore_factor, "num of bcn intervals to stay TSF update restore status"); + #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE char *rtw_phy_file_path = REALTEK_CONFIG_PATH; module_param(rtw_phy_file_path, charp, 0644); @@ -652,6 +693,29 @@ module_param(rtw_trx_share_mode, int, 0644); MODULE_PARM_DESC(rtw_trx_share_mode, "TRx FIFO Shared"); #endif +#ifdef CONFIG_DYNAMIC_SOML +uint rtw_dynamic_soml_en = 1; +module_param(rtw_dynamic_soml_en, int, 0644); +MODULE_PARM_DESC(rtw_dynamic_soml_en, "0: disable, 1: enable with default param, 2: enable with specified param."); + +uint rtw_dynamic_soml_train_num = 0; +module_param(rtw_dynamic_soml_train_num, int, 0644); +MODULE_PARM_DESC(rtw_dynamic_soml_train_num, "SOML training number"); + +uint rtw_dynamic_soml_interval = 0; +module_param(rtw_dynamic_soml_interval, int, 0644); +MODULE_PARM_DESC(rtw_dynamic_soml_interval, "SOML training interval"); + +uint rtw_dynamic_soml_period = 0; +module_param(rtw_dynamic_soml_period, int, 0644); +MODULE_PARM_DESC(rtw_dynamic_soml_period, "SOML training period"); + +uint rtw_dynamic_soml_delay = 0; +module_param(rtw_dynamic_soml_delay, int, 0644); +MODULE_PARM_DESC(rtw_dynamic_soml_delay, "SOML training delay"); +#endif + + int _netdev_open(struct net_device *pnetdev); int netdev_open(struct net_device *pnetdev); static int netdev_close(struct net_device *pnetdev); @@ -672,11 +736,7 @@ int rtw_mcc_sta_bw80_target_tx_tp = MCC_STA_BW80_TARGET_TX_TP; int rtw_mcc_single_tx_cri = MCC_SINGLE_TX_CRITERIA; int rtw_mcc_policy_table_idx = 0; int rtw_mcc_duration = 0; -int rtw_mcc_tsf_sync_offset = 0; -int rtw_mcc_start_time_offset = 0; -int rtw_mcc_interval = 0; -int rtw_mcc_guard_offset0 = -1; -int rtw_mcc_guard_offset1 = -1; +int rtw_mcc_enable_runtime_duration = 1; module_param(rtw_en_mcc, int, 0644); module_param(rtw_mcc_single_tx_cri, int, 0644); module_param(rtw_mcc_ap_bw20_target_tx_tp, int, 0644); @@ -687,11 +747,6 @@ module_param(rtw_mcc_sta_bw40_target_tx_tp, int, 0644); module_param(rtw_mcc_sta_bw80_target_tx_tp, int, 0644); module_param(rtw_mcc_policy_table_idx, int, 0644); module_param(rtw_mcc_duration, int, 0644); -module_param(rtw_mcc_tsf_sync_offset, int, 0644); -module_param(rtw_mcc_start_time_offset, int, 0644); -module_param(rtw_mcc_interval, int, 0644); -module_param(rtw_mcc_guard_offset0, int, 0644); -module_param(rtw_mcc_guard_offset1, int, 0644); #endif /*CONFIG_MCC_MODE */ #ifdef CONFIG_RTW_NAPI @@ -699,6 +754,10 @@ module_param(rtw_mcc_guard_offset1, int, 0644); enable napi only = 1, disable napi = 0*/ int rtw_en_napi = 1; module_param(rtw_en_napi, int, 0644); +#ifdef CONFIG_RTW_NAPI_DYNAMIC +int rtw_napi_threshold = 100; /* unit: Mbps */ +module_param(rtw_napi_threshold, int, 0644); +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ #ifdef CONFIG_RTW_GRO /*following setting should define GRO in Makefile enable gro = 1, disable gro = 0*/ @@ -707,6 +766,40 @@ module_param(rtw_en_gro, int, 0644); #endif /* CONFIG_RTW_GRO */ #endif /* CONFIG_RTW_NAPI */ +#ifdef RTW_IQK_FW_OFFLOAD +int rtw_iqk_fw_offload = 1; +#else +int rtw_iqk_fw_offload; +#endif /* RTW_IQK_FW_OFFLOAD */ +module_param(rtw_iqk_fw_offload, int, 0644); + +#ifdef RTW_CHANNEL_SWITCH_OFFLOAD +int rtw_ch_switch_offload = 0; +#else +int rtw_ch_switch_offload; +#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ +module_param(rtw_ch_switch_offload, int, 0644); + +#ifdef CONFIG_TDLS +int rtw_en_tdls = 1; +module_param(rtw_en_tdls, int, 0644); +#endif + +#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT +int rtw_fw_param_init = 1; +module_param(rtw_fw_param_init, int, 0644); +#endif + +#ifdef CONFIG_WOWLAN +/* + * bit[0]: magic packet wake up + * bit[1]: unucast packet(HW/FW unuicast) + * bit[2]: deauth wake up + */ +uint rtw_wakeup_event = RTW_WAKEUP_EVENT; +module_param(rtw_wakeup_event, uint, 0644); +#endif + void rtw_regsty_load_target_tx_power(struct registry_priv *regsty) { int path, rs; @@ -814,17 +907,17 @@ uint loadparam(_adapter *padapter) registry_par->frag_thresh = (u16)rtw_frag_thresh; registry_par->preamble = (u8)rtw_preamble; registry_par->scan_mode = (u8)rtw_scan_mode; - registry_par->adhoc_tx_pwr = (u8)rtw_adhoc_tx_pwr; - registry_par->soft_ap = (u8)rtw_soft_ap; registry_par->smart_ps = (u8)rtw_smart_ps; registry_par->check_fw_ps = (u8)rtw_check_fw_ps; registry_par->power_mgnt = (u8)rtw_power_mgnt; registry_par->ips_mode = (u8)rtw_ips_mode; registry_par->lps_level = (u8)rtw_lps_level; + registry_par->lps_chk_by_tp = (u8)rtw_lps_chk_by_tp; registry_par->radio_enable = (u8)rtw_radio_enable; registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt; registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt; registry_par->busy_thresh = (u16)rtw_busy_thresh; + registry_par->max_bss_cnt = (u16)rtw_max_bss_cnt; /* registry_par->qos_enable = (u8)rtw_qos_enable; */ registry_par->ack_policy = (u8)rtw_ack_policy; registry_par->mp_mode = (u8)rtw_mp_mode; @@ -838,14 +931,15 @@ uint loadparam(_adapter *padapter) registry_par->usb_rxagg_mode = (u8)rtw_usb_rxagg_mode; registry_par->dynamic_agg_enable = (u8)rtw_dynamic_agg_enable; - /* UAPSD */ + /* WMM */ registry_par->wmm_enable = (u8)rtw_wmm_enable; - registry_par->uapsd_enable = (u8)rtw_uapsd_enable; - registry_par->uapsd_max_sp = (u8)rtw_uapsd_max_sp; - registry_par->uapsd_acbk_en = (u8)rtw_uapsd_acbk_en; - registry_par->uapsd_acbe_en = (u8)rtw_uapsd_acbe_en; - registry_par->uapsd_acvi_en = (u8)rtw_uapsd_acvi_en; - registry_par->uapsd_acvo_en = (u8)rtw_uapsd_acvo_en; + +#ifdef CONFIG_WMMPS_STA + /* UAPSD */ + registry_par->uapsd_max_sp_len= (u8)rtw_uapsd_max_sp; + registry_par->uapsd_ac_enable = (u8)rtw_uapsd_ac_enable; + registry_par->wmm_smart_ps = (u8)rtw_wmm_smart_ps; +#endif /* CONFIG_WMMPS_STA */ registry_par->RegPwrTrimEnable = (u8)rtw_pwrtrim_enable; @@ -853,20 +947,32 @@ uint loadparam(_adapter *padapter) #ifdef CONFIG_80211N_HT registry_par->ht_enable = (u8)rtw_ht_enable; - registry_par->bw_mode = (u8)rtw_bw_mode; - registry_par->ampdu_enable = (u8)rtw_ampdu_enable; - registry_par->rx_stbc = (u8)rtw_rx_stbc; - registry_par->rx_ampdu_amsdu = (u8)rtw_rx_ampdu_amsdu; - registry_par->tx_ampdu_amsdu = (u8)rtw_tx_ampdu_amsdu; - registry_par->short_gi = (u8)rtw_short_gi; - registry_par->ldpc_cap = (u8)rtw_ldpc_cap; - registry_par->stbc_cap = (u8)rtw_stbc_cap; - registry_par->beamform_cap = (u8)rtw_beamform_cap; - registry_par->beamformer_rf_num = (u8)rtw_bfer_rf_number; - registry_par->beamformee_rf_num = (u8)rtw_bfee_rf_number; - rtw_regsty_init_rx_ampdu_sz_limit(registry_par); + if (registry_par->ht_enable && is_supported_ht(registry_par->wireless_mode)) { + registry_par->bw_mode = (u8)rtw_bw_mode; + registry_par->ampdu_enable = (u8)rtw_ampdu_enable; + registry_par->rx_stbc = (u8)rtw_rx_stbc; + registry_par->rx_ampdu_amsdu = (u8)rtw_rx_ampdu_amsdu; + registry_par->tx_ampdu_amsdu = (u8)rtw_tx_ampdu_amsdu; + registry_par->short_gi = (u8)rtw_short_gi; + registry_par->ldpc_cap = (u8)rtw_ldpc_cap; +#if defined(CONFIG_CUSTOMER01_SMART_ANTENNA) + rtw_stbc_cap = 0x0; +#elif defined(CONFIG_RTW_TX_2PATH_EN) + rtw_stbc_cap &= ~(BIT1|BIT5); +#endif + registry_par->stbc_cap = (u8)rtw_stbc_cap; +#if defined(CONFIG_RTW_TX_2PATH_EN) + rtw_beamform_cap &= ~(BIT0|BIT2|BIT4); +#endif + registry_par->beamform_cap = (u8)rtw_beamform_cap; + registry_par->beamformer_rf_num = (u8)rtw_bfer_rf_number; + registry_par->beamformee_rf_num = (u8)rtw_bfee_rf_number; + rtw_regsty_init_rx_ampdu_sz_limit(registry_par); + } +#endif +#ifdef DBG_LA_MODE + registry_par->la_mode_en = (u8)rtw_la_mode_en; #endif - #ifdef CONFIG_80211AC_VHT registry_par->vht_enable = (u8)rtw_vht_enable; registry_par->ampdu_factor = (u8)rtw_ampdu_factor; @@ -954,25 +1060,21 @@ uint loadparam(_adapter *padapter) registry_par->notch_filter = (u8)rtw_notch_filter; -#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV - registry_par->force_ant = (u8)rtw_force_ant; - registry_par->force_igi = (u8)rtw_force_igi; -#endif - #ifdef CONFIG_CONCURRENT_MODE registry_par->virtual_iface_num = (u8)rtw_virtual_iface_num; #endif - - registry_par->force_igi_lb = (u8)rtw_force_igi_lb; - registry_par->pll_ref_clk_sel = (u8)rtw_pll_ref_clk_sel; +#ifdef CONFIG_TXPWR_LIMIT registry_par->RegEnableTxPowerLimit = (u8)rtw_tx_pwr_lmt_enable; +#endif registry_par->RegEnableTxPowerByRate = (u8)rtw_tx_pwr_by_rate; rtw_regsty_load_target_tx_power(registry_par); - registry_par->RegPowerBase = 14; + registry_par->tsf_update_pause_factor = (u8)rtw_tsf_update_pause_factor; + registry_par->tsf_update_restore_factor = (u8)rtw_tsf_update_restore_factor; + registry_par->TxBBSwing_2G = (s8)rtw_TxBBSwing_2G; registry_par->TxBBSwing_5G = (s8)rtw_TxBBSwing_5G; registry_par->bEn_RFE = 1; @@ -991,16 +1093,26 @@ uint loadparam(_adapter *padapter) registry_par->adaptivity_en = (u8)rtw_adaptivity_en; registry_par->adaptivity_mode = (u8)rtw_adaptivity_mode; - registry_par->adaptivity_dml = (u8)rtw_adaptivity_dml; - registry_par->adaptivity_dc_backoff = (u8)rtw_adaptivity_dc_backoff; registry_par->adaptivity_th_l2h_ini = (s8)rtw_adaptivity_th_l2h_ini; registry_par->adaptivity_th_edcca_hl_diff = (s8)rtw_adaptivity_th_edcca_hl_diff; +#ifdef CONFIG_DYNAMIC_SOML + registry_par->dyn_soml_en = (u8)rtw_dynamic_soml_en; + registry_par->dyn_soml_train_num = (u8)rtw_dynamic_soml_train_num; + registry_par->dyn_soml_interval = (u8)rtw_dynamic_soml_interval; + registry_par->dyn_soml_period = (u8)rtw_dynamic_soml_period; + registry_par->dyn_soml_delay = (u8)rtw_dynamic_soml_delay; +#endif + registry_par->boffefusemask = (u8)rtw_OffEfuseMask; registry_par->bFileMaskEfuse = (u8)rtw_FileMaskEfuse; -#ifdef CONFIG_AUTO_CHNL_SEL_NHM - registry_par->acs_mode = (u8)rtw_acs_mode; + +#ifdef CONFIG_RTW_ACS + registry_par->acs_mode = (u8)rtw_acs; registry_par->acs_auto_scan = (u8)rtw_acs_auto_scan; +#endif +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + registry_par->nm_mode = (u8)rtw_nm; #endif registry_par->reg_rxgain_offset_2g = (u32) rtw_rxgain_offset_2g; registry_par->reg_rxgain_offset_5gl = (u32) rtw_rxgain_offset_5gl; @@ -1022,14 +1134,11 @@ uint loadparam(_adapter *padapter) registry_par->rtw_mcc_single_tx_cri = (u32)rtw_mcc_single_tx_cri; registry_par->rtw_mcc_policy_table_idx = rtw_mcc_policy_table_idx; registry_par->rtw_mcc_duration = (u8)rtw_mcc_duration; - registry_par->rtw_mcc_tsf_sync_offset = (u8)rtw_mcc_tsf_sync_offset; - registry_par->rtw_mcc_start_time_offset = (u8)rtw_mcc_start_time_offset; - registry_par->rtw_mcc_interval = (u8)rtw_mcc_interval; - registry_par->rtw_mcc_guard_offset0 = rtw_mcc_guard_offset0; - registry_par->rtw_mcc_guard_offset1 = rtw_mcc_guard_offset1; + registry_par->rtw_mcc_enable_runtime_duration = rtw_mcc_enable_runtime_duration; #endif /*CONFIG_MCC_MODE */ -#ifdef CONFIG_DEFAULT_PATTERNS_EN - registry_par->default_patterns_en = rtw_support_default_patterns; + +#ifdef CONFIG_WOWLAN + registry_par->wakeup_event = rtw_wakeup_event; #endif #ifdef CONFIG_SUPPORT_TRX_SHARED @@ -1042,6 +1151,9 @@ uint loadparam(_adapter *padapter) #ifdef CONFIG_RTW_NAPI registry_par->en_napi = (u8)rtw_en_napi; +#ifdef CONFIG_RTW_NAPI_DYNAMIC + registry_par->napi_threshold = (u32)rtw_napi_threshold; +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ #ifdef CONFIG_RTW_GRO registry_par->en_gro = (u8)rtw_en_gro; if (!registry_par->en_napi && registry_par->en_gro) { @@ -1051,6 +1163,26 @@ uint loadparam(_adapter *padapter) #endif /* CONFIG_RTW_GRO */ #endif /* CONFIG_RTW_NAPI */ + registry_par->iqk_fw_offload = (u8)rtw_iqk_fw_offload; + registry_par->ch_switch_offload = (u8)rtw_ch_switch_offload; + +#ifdef CONFIG_TDLS + registry_par->en_tdls = rtw_en_tdls; +#endif + +#ifdef CONFIG_ADVANCE_OTA + registry_par->adv_ota = rtw_advnace_ota; +#endif +#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT + registry_par->fw_param_init = rtw_fw_param_init; +#endif +#ifdef CONFIG_AP_MODE + registry_par->bmc_tx_rate = rtw_bmc_tx_rate; +#endif +#ifdef CONFIG_FW_HANDLE_TXBCN + registry_par->fw_tbtt_rpt = rtw_tbtt_rpt; +#endif + return status; } @@ -1190,23 +1322,11 @@ unsigned int rtw_classify8021d(struct sk_buff *skb) } -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,19,0)) -static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb - , struct net_device *sb_dev - #if (LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0)) - , select_queue_fallback_t fallback - #endif -) -#else static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) - , void *accel_priv - #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) - , select_queue_fallback_t fallback - #endif + , struct net_device *sb_dev #endif ) -#endif { _adapter *padapter = rtw_netdev_priv(dev); struct mlme_priv *pmlmepriv = &padapter->mlmepriv; @@ -1248,39 +1368,53 @@ u16 rtw_recv_select_queue(struct sk_buff *skb) } #endif -static int rtw_ndev_notifier_call(struct notifier_block *nb, unsigned long state, void *ptr) + +static u8 is_rtw_ndev(struct net_device *ndev) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) - struct net_device *dev = netdev_notifier_info_to_dev(ptr); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) + return ndev->netdev_ops + && ndev->netdev_ops->ndo_do_ioctl + && ndev->netdev_ops->ndo_do_ioctl == rtw_ioctl; #else - struct net_device *dev = ptr; + return ndev->do_ioctl + && ndev->do_ioctl == rtw_ioctl; #endif +} - if (dev == NULL) - return NOTIFY_DONE; - -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) - if (dev->netdev_ops == NULL) - return NOTIFY_DONE; +static int rtw_ndev_notifier_call(struct notifier_block *nb, unsigned long state, void *ptr) +{ + struct net_device *ndev; - if (dev->netdev_ops->ndo_do_ioctl == NULL) + if (ptr == NULL) return NOTIFY_DONE; - if (dev->netdev_ops->ndo_do_ioctl != rtw_ioctl) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + ndev = netdev_notifier_info_to_dev(ptr); #else - if (dev->do_ioctl == NULL) + ndev = ptr; +#endif + + if (ndev == NULL) return NOTIFY_DONE; - if (dev->do_ioctl != rtw_ioctl) -#endif + if (!is_rtw_ndev(ndev)) return NOTIFY_DONE; - RTW_INFO(FUNC_NDEV_FMT" state:%lu\n", FUNC_NDEV_ARG(dev), state); + RTW_INFO(FUNC_NDEV_FMT" state:%lu\n", FUNC_NDEV_ARG(ndev), state); switch (state) { case NETDEV_CHANGENAME: - rtw_adapter_proc_replace(dev); + rtw_adapter_proc_replace(ndev); break; + #ifdef CONFIG_NEW_NETDEV_HDL + case NETDEV_PRE_UP : + { + _adapter *adapter = rtw_netdev_priv(ndev); + + rtw_pwr_wakeup(adapter); + } + break; + #endif } return NOTIFY_DONE; @@ -1300,7 +1434,6 @@ void rtw_ndev_notifier_unregister(void) unregister_netdevice_notifier(&rtw_ndev_notifier); } - int rtw_ndev_init(struct net_device *dev) { _adapter *adapter = rtw_netdev_priv(dev); @@ -1341,9 +1474,8 @@ static const struct net_device_ops rtw_netdev_ops = { int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) { - _adapter *padapter = rtw_netdev_priv(pnetdev); - #ifdef CONFIG_EASY_REPLACEMENT + _adapter *padapter = rtw_netdev_priv(pnetdev); struct net_device *TargetNetdev = NULL; _adapter *TargetAdapter = NULL; struct net *devnet = NULL; @@ -1379,7 +1511,7 @@ int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) if (dev_alloc_name(pnetdev, ifname) < 0) RTW_ERR("dev_alloc_name, fail!\n"); - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); /* rtw_netif_stop_queue(pnetdev); */ return 0; @@ -1431,10 +1563,27 @@ struct net_device *rtw_init_netdev(_adapter *old_padapter) rtw_hook_vir_if_ops(pnetdev); #endif /* CONFIG_CONCURRENT_MODE */ -#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX - pnetdev->features |= NETIF_F_IP_CSUM; + +#ifdef CONFIG_TX_CSUM_OFFLOAD + pnetdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39) + pnetdev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); +#endif +#endif + +#ifdef CONFIG_RTW_NETIF_SG + pnetdev->features |= NETIF_F_SG; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39) + pnetdev->hw_features |= NETIF_F_SG; +#endif #endif + if ((pnetdev->features & NETIF_F_SG) && (pnetdev->features & NETIF_F_IP_CSUM)) { + pnetdev->features |= (NETIF_F_TSO | NETIF_F_GSO); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39) + pnetdev->hw_features |= (NETIF_F_TSO | NETIF_F_GSO); +#endif + } /* pnetdev->tx_timeout = NULL; */ pnetdev->watchdog_timeo = HZ * 3; /* 3 second timeout */ @@ -1492,6 +1641,12 @@ void rtw_os_ndev_free(_adapter *adapter) rtw_cfg80211_ndev_res_free(adapter); #endif + /* free the old_pnetdev */ + if (adapter->rereg_nd_name_priv.old_pnetdev) { + rtw_free_netdev(adapter->rereg_nd_name_priv.old_pnetdev); + adapter->rereg_nd_name_priv.old_pnetdev = NULL; + } + if (adapter->pnetdev) { rtw_free_netdev(adapter->pnetdev); adapter->pnetdev = NULL; @@ -1516,7 +1671,9 @@ int rtw_os_ndev_register(_adapter *adapter, const char *name) goto exit; } #endif - +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_PCI_HCI) + ndev->gro_flush_timeout = 100000; +#endif /* alloc netdev name */ rtw_init_netdev_name(ndev, name); @@ -1578,6 +1735,9 @@ void rtw_os_ndev_unregister(_adapter *adapter) } #if defined(CONFIG_IOCTL_CFG80211) && !defined(RTW_SINGLE_WIPHY) +#ifdef CONFIG_RFKILL_POLL + rtw_cfg80211_deinit_rfkill(adapter_to_wiphy(adapter)); +#endif rtw_wiphy_unregister(adapter_to_wiphy(adapter)); #endif @@ -1713,39 +1873,60 @@ u32 rtw_start_drv_threads(_adapter *padapter) { u32 _status = _SUCCESS; + RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter)); #ifdef CONFIG_XMIT_THREAD_MODE #if defined(CONFIG_SDIO_HCI) if (is_primary_adapter(padapter)) #endif { - padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD"); - if (IS_ERR(padapter->xmitThread)) - _status = _FAIL; + if (padapter->xmitThread == NULL) { + RTW_INFO(FUNC_ADPT_FMT " start RTW_XMIT_THREAD\n", FUNC_ADPT_ARG(padapter)); + padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD"); + if (IS_ERR(padapter->xmitThread)) { + padapter->xmitThread = NULL; + _status = _FAIL; + } + } } #endif /* #ifdef CONFIG_XMIT_THREAD_MODE */ #ifdef CONFIG_RECV_THREAD_MODE if (is_primary_adapter(padapter)) { - padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD"); - if (IS_ERR(padapter->recvThread)) - _status = _FAIL; + if (padapter->recvThread == NULL) { + RTW_INFO(FUNC_ADPT_FMT " start RTW_RECV_THREAD\n", FUNC_ADPT_ARG(padapter)); + padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD"); + if (IS_ERR(padapter->recvThread)) { + padapter->recvThread = NULL; + _status = _FAIL; + } + } } #endif if (is_primary_adapter(padapter)) { - padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD"); - if (IS_ERR(padapter->cmdThread)) - _status = _FAIL; - else - _rtw_down_sema(&padapter->cmdpriv.start_cmdthread_sema); /* wait for cmd_thread to run */ + if (padapter->cmdThread == NULL) { + RTW_INFO(FUNC_ADPT_FMT " start RTW_CMD_THREAD\n", FUNC_ADPT_ARG(padapter)); + padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD"); + if (IS_ERR(padapter->cmdThread)) { + padapter->cmdThread = NULL; + _status = _FAIL; + } + else + _rtw_down_sema(&padapter->cmdpriv.start_cmdthread_sema); /* wait for cmd_thread to run */ + } } #ifdef CONFIG_EVENT_THREAD_MODE - padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD"); - if (IS_ERR(padapter->evtThread)) - _status = _FAIL; + if (padapter->evtThread == NULL) { + RTW_INFO(FUNC_ADPT_FMT " start RTW_EVENT_THREAD\n", FUNC_ADPT_ARG(padapter)); + padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD"); + if (IS_ERR(padapter->evtThread)) { + padapter->evtThread = NULL; + _status = _FAIL; + } + } #endif rtw_hal_start_thread(padapter); @@ -1755,14 +1936,16 @@ u32 rtw_start_drv_threads(_adapter *padapter) void rtw_stop_drv_threads(_adapter *padapter) { - + RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter)); if (is_primary_adapter(padapter)) rtw_stop_cmd_thread(padapter); #ifdef CONFIG_EVENT_THREAD_MODE - _rtw_up_sema(&padapter->evtpriv.evt_notify); - if (padapter->evtThread) - _rtw_down_sema(&padapter->evtpriv.terminate_evtthread_sema); + if (padapter->evtThread) { + _rtw_up_sema(&padapter->evtpriv.evt_notify); + rtw_thread_stop(padapter->evtThread); + padapter->evtThread = NULL; + } #endif #ifdef CONFIG_XMIT_THREAD_MODE @@ -1772,34 +1955,31 @@ void rtw_stop_drv_threads(_adapter *padapter) if (is_primary_adapter(padapter)) #endif /*SDIO_HCI */ { - if (padapter->xmitpriv.stop_req == 0) { + if (padapter->xmitThread) { _rtw_up_sema(&padapter->xmitpriv.xmit_sema); - /*_rtw_down_sema(&padapter->xmitpriv.terminate_xmitthread_sema);*/ - rtw_wait_for_thread_stop(&padapter->xmitpriv.xmitthread_comp); - padapter->xmitpriv.stop_req = 1; + rtw_thread_stop(padapter->xmitThread); + padapter->xmitThread = NULL; } } #endif #ifdef CONFIG_RECV_THREAD_MODE - if (is_primary_adapter(padapter)) { + if (is_primary_adapter(padapter) && padapter->recvThread) { /* Below is to termindate rx_thread... */ _rtw_up_sema(&padapter->recvpriv.recv_sema); - /*_rtw_down_sema(&padapter->recvpriv.terminate_recvthread_sema);*/ - rtw_wait_for_thread_stop(&padapter->recvpriv.recvthread_comp); + rtw_thread_stop(padapter->recvThread); + padapter->recvThread = NULL; } #endif rtw_hal_stop_thread(padapter); } -u8 rtw_init_default_value(_adapter *padapter); u8 rtw_init_default_value(_adapter *padapter) { u8 ret = _SUCCESS; struct registry_priv *pregistrypriv = &padapter->registrypriv; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &padapter->securitypriv; /* xmit_priv */ @@ -1844,6 +2024,11 @@ u8 rtw_init_default_value(_adapter *padapter) /* hal_priv */ rtw_hal_def_value_init(padapter); +#ifdef CONFIG_MCC_MODE + /* MCC parameter */ + rtw_hal_mcc_parameter_init(padapter); +#endif /* CONFIG_MCC_MODE */ + /* misc. */ RTW_ENABLE_FUNC(padapter, DF_RX_BIT); RTW_ENABLE_FUNC(padapter, DF_TX_BIT); @@ -1860,7 +2045,9 @@ u8 rtw_init_default_value(_adapter *padapter) padapter->power_offset = 0; padapter->rsvd_page_offset = 0; padapter->rsvd_page_num = 0; - +#ifdef CONFIG_AP_MODE + padapter->bmc_tx_rate = pregistrypriv->bmc_tx_rate; +#endif padapter->driver_tx_bw_mode = pregistrypriv->tx_bw_mode; padapter->driver_ampdu_spacing = 0xFF; @@ -1882,11 +2069,25 @@ u8 rtw_init_default_value(_adapter *padapter) #ifdef CONFIG_RTW_NAPI padapter->napi_state = NAPI_DISABLE; #endif - padapter->tsf.sync_port = MAX_HW_PORT; - padapter->tsf.offset = 0; +#ifdef CONFIG_RTW_ACS + if (pregistrypriv->acs_mode) + rtw_acs_start(padapter); + else + rtw_acs_stop(padapter); +#endif +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + if (pregistrypriv->nm_mode) + rtw_nm_enable(padapter); + else + rtw_nm_disable(padapter); +#endif return ret; } +#ifdef CONFIG_CLIENT_PORT_CFG +extern void rtw_clt_port_init(struct clt_port_t *cltp); +extern void rtw_clt_port_deinit(struct clt_port_t *cltp); +#endif struct dvobj_priv *devobj_init(void) { @@ -1904,7 +2105,9 @@ struct dvobj_priv *devobj_init(void) #ifdef CONFIG_SDIO_INDIRECT_ACCESS _rtw_mutex_init(&pdvobj->sd_indirect_access_mutex); #endif - +#ifdef CONFIG_SYSON_INDIRECT_ACCESS + _rtw_mutex_init(&pdvobj->syson_indirect_access_mutex); +#endif #ifdef CONFIG_RTW_CUSTOMER_STR _rtw_mutex_init(&pdvobj->customer_str_mutex); _rtw_memset(pdvobj->customer_str, 0xFF, RTW_CUSTOMER_STR_LEN); @@ -1915,6 +2118,9 @@ struct dvobj_priv *devobj_init(void) ATOMIC_SET(&pdvobj->disable_func, 0); rtw_macid_ctl_init(&pdvobj->macid_ctl); +#ifdef CONFIG_CLIENT_PORT_CFG + rtw_clt_port_init(&pdvobj->clt_port); +#endif _rtw_spinlock_init(&pdvobj->cam_ctl.lock); _rtw_mutex_init(&pdvobj->cam_ctl.sec_cam_access_mutex); #if defined(RTK_129X_PLATFORM) && defined(CONFIG_PCI_HCI) @@ -1925,21 +2131,31 @@ struct dvobj_priv *devobj_init(void) #endif #ifdef CONFIG_AP_MODE + #ifdef CONFIG_SUPPORT_MULTI_BCN pdvobj->nr_ap_if = 0; pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL; /* default value is equal to the default beacon_interval (100ms) */ _rtw_init_queue(&pdvobj->ap_if_q); -#ifdef CONFIG_SWTIMER_BASED_TXBCN + pdvobj->vap_map = 0; + #endif /*CONFIG_SUPPORT_MULTI_BCN*/ + #ifdef CONFIG_SWTIMER_BASED_TXBCN rtw_init_timer(&(pdvobj->txbcn_timer), NULL, tx_beacon_timer_handlder, pdvobj); -#endif + #endif #endif - rtw_init_timer(&(pdvobj->dynamic_chk_timer), NULL, rtw_dynamic_check_timer_handlder); + rtw_init_timer(&(pdvobj->dynamic_chk_timer), NULL, rtw_dynamic_check_timer_handlder, pdvobj); + rtw_init_timer(&(pdvobj->periodic_tsf_update_end_timer), NULL, rtw_hal_periodic_tsf_update_end_timer_hdl, pdvobj); #ifdef CONFIG_MCC_MODE _rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_mutex)); + _rtw_mutex_init(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex)); _rtw_spinlock_init(&pdvobj->mcc_objpriv.mcc_lock); #endif /* CONFIG_MCC_MODE */ +#ifdef CONFIG_RTW_NAPI_DYNAMIC + pdvobj->en_napi_dynamic = 0; +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ + + return pdvobj; } @@ -1956,6 +2172,7 @@ void devobj_deinit(struct dvobj_priv *pdvobj) #ifdef CONFIG_MCC_MODE _rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_mutex)); + _rtw_mutex_free(&(pdvobj->mcc_objpriv.mcc_tsf_req_mutex)); _rtw_spinlock_free(&pdvobj->mcc_objpriv.mcc_lock); #endif /* CONFIG_MCC_MODE */ @@ -1972,8 +2189,15 @@ void devobj_deinit(struct dvobj_priv *pdvobj) #ifdef CONFIG_SDIO_INDIRECT_ACCESS _rtw_mutex_free(&pdvobj->sd_indirect_access_mutex); #endif +#ifdef CONFIG_SYSON_INDIRECT_ACCESS + _rtw_mutex_free(&pdvobj->syson_indirect_access_mutex); +#endif rtw_macid_ctl_deinit(&pdvobj->macid_ctl); +#ifdef CONFIG_CLIENT_PORT_CFG + rtw_clt_port_deinit(&pdvobj->clt_port); +#endif + _rtw_spinlock_free(&pdvobj->cam_ctl.lock); _rtw_mutex_free(&pdvobj->cam_ctl.sec_cam_access_mutex); @@ -1983,9 +2207,9 @@ void devobj_deinit(struct dvobj_priv *pdvobj) #ifdef CONFIG_MBSSID_CAM rtw_mbid_cam_deinit(pdvobj); #endif - +#ifdef CONFIG_SUPPORT_MULTI_BCN _rtw_spinlock_free(&(pdvobj->ap_if_q.lock)); - +#endif rtw_mfree((u8 *)pdvobj, sizeof(*pdvobj)); } @@ -2030,15 +2254,11 @@ u8 rtw_reset_drv_sw(_adapter *padapter) struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); /* hal_priv */ - if (is_primary_adapter(padapter)) - rtw_hal_def_value_init(padapter); + rtw_hal_def_value_init(padapter); RTW_ENABLE_FUNC(padapter, DF_RX_BIT); RTW_ENABLE_FUNC(padapter, DF_TX_BIT); - padapter->tsf.sync_port = MAX_HW_PORT; - padapter->tsf.offset = 0; - padapter->bLinkInfoDump = 0; padapter->xmitpriv.tx_pkts = 0; @@ -2077,12 +2297,25 @@ u8 rtw_reset_drv_sw(_adapter *padapter) u8 rtw_init_drv_sw(_adapter *padapter) { - u8 ret8 = _SUCCESS; +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); +#endif - + #if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN) _rtw_init_listhead(&padapter->list); + #ifdef CONFIG_FW_HANDLE_TXBCN + padapter->vap_id = CONFIG_LIMITED_AP_NUM; + if (is_primary_adapter(padapter)) + adapter_to_dvobj(padapter)->vap_tbtt_rpt_map = adapter_to_regsty(padapter)->fw_tbtt_rpt; + #endif + #endif + + #ifdef CONFIG_CLIENT_PORT_CFG + padapter->client_id = MAX_CLIENT_PORT_NUM; + padapter->client_port = CLT_PORT_INVALID; + #endif ret8 = rtw_init_default_value(padapter); @@ -2098,7 +2331,8 @@ u8 rtw_init_drv_sw(_adapter *padapter) goto exit; } - rtw_rfctl_init(padapter); + if (is_primary_adapter(padapter)) + rtw_rfctl_init(padapter); if (rtw_init_mlme_priv(padapter) == _FAIL) { ret8 = _FAIL; @@ -2131,6 +2365,10 @@ u8 rtw_init_drv_sw(_adapter *padapter) } #endif /* CONFIG_TDLS */ +#ifdef CONFIG_RTW_MESH + rtw_mesh_cfg_init(padapter); +#endif + if (_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL) { RTW_INFO("Can't _rtw_init_xmit_priv\n"); ret8 = _FAIL; @@ -2154,7 +2392,6 @@ u8 rtw_init_drv_sw(_adapter *padapter) goto exit; } - padapter->stapriv.padapter = padapter; padapter->setband = WIFI_FREQUENCY_BAND_AUTO; padapter->fix_rate = 0xFF; padapter->power_offset = 0; @@ -2182,7 +2419,7 @@ u8 rtw_init_drv_sw(_adapter *padapter) #endif rtw_hal_dm_init(padapter); -#ifdef CONFIG_SW_LED +#ifdef CONFIG_RTW_SW_LED rtw_hal_sw_led_init(padapter); #endif #ifdef DBG_CONFIG_ERROR_DETECT @@ -2212,6 +2449,18 @@ u8 rtw_init_drv_sw(_adapter *padapter) #endif /* RTW_BEAMFORMING_VERSION_2 */ #endif /* CONFIG_BEAMFORMING */ +#ifdef CONFIG_RTW_REPEATER_SON + init_rtw_rson_data(adapter_to_dvobj(padapter)); +#endif + +#ifdef CONFIG_RTW_80211K + rtw_init_rm(padapter); +#endif + +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + memset(pwdev_priv->pno_mac_addr, 0xFF, ETH_ALEN); +#endif + exit: @@ -2235,14 +2484,15 @@ void rtw_cancel_all_timer(_adapter *padapter) _cancel_timer_ex(&padapter->mlmepriv.scan_to_timer); #ifdef CONFIG_DFS_MASTER - _cancel_timer_ex(&padapter->mlmepriv.dfs_master_timer); + _cancel_timer_ex(&adapter_to_rfctl(padapter)->radar_detect_timer); #endif _cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer); - + _cancel_timer_ex(&adapter_to_dvobj(padapter)->periodic_tsf_update_end_timer); +#ifdef CONFIG_RTW_SW_LED /* cancel sw led timer */ rtw_hal_sw_led_deinit(padapter); - +#endif _cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_state_check_timer)); #ifdef CONFIG_TX_AMSDU @@ -2320,12 +2570,19 @@ u8 rtw_free_drv_sw(_adapter *padapter) /* rtw_free_tdls_info(&padapter->tdlsinfo); */ #endif /* CONFIG_TDLS */ +#ifdef CONFIG_RTW_80211K + rtw_free_rm_priv(padapter); +#endif + rtw_free_cmd_priv(&padapter->cmdpriv); rtw_free_evt_priv(&padapter->evtpriv); rtw_free_mlme_priv(&padapter->mlmepriv); + if (is_primary_adapter(padapter)) + rtw_rfctl_deinit(padapter); + /* free_io_queue(padapter); */ _rtw_free_xmit_priv(&padapter->xmitpriv); @@ -2338,19 +2595,8 @@ u8 rtw_free_drv_sw(_adapter *padapter) /* rtw_mfree((void *)padapter, sizeof (padapter)); */ -#ifdef CONFIG_DRVEXT_MODULE - free_drvext(&padapter->drvextpriv); -#endif - rtw_hal_free_data(padapter); - - /* free the old_pnetdev */ - if (padapter->rereg_nd_name_priv.old_pnetdev) { - free_netdev(padapter->rereg_nd_name_priv.old_pnetdev); - padapter->rereg_nd_name_priv.old_pnetdev = NULL; - } - return _SUCCESS; } @@ -2366,6 +2612,7 @@ void rtw_intf_stop(_adapter *adapter) } #ifdef CONFIG_CONCURRENT_MODE +#ifndef CONFIG_NEW_NETDEV_HDL int _netdev_vir_if_open(struct net_device *pnetdev) { _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); @@ -2407,7 +2654,6 @@ int _netdev_vir_if_open(struct net_device *pnetdev) if (padapter->bup == _FALSE && primary_padapter->bup == _TRUE && rtw_is_hw_init_completed(primary_padapter)) { - padapter->bFWReady = primary_padapter->bFWReady; #if 0 /*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/ rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */ #endif @@ -2452,7 +2698,7 @@ int _netdev_vir_if_open(struct net_device *pnetdev) } #endif - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); return -1; @@ -2501,13 +2747,19 @@ static int netdev_vir_if_close(struct net_device *pnetdev) return 0; } +#endif /*#ifndef CONFIG_NEW_NETDEV_HDL*/ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) static const struct net_device_ops rtw_netdev_vir_if_ops = { .ndo_init = rtw_ndev_init, .ndo_uninit = rtw_ndev_uninit, + #ifdef CONFIG_NEW_NETDEV_HDL + .ndo_open = netdev_open, + .ndo_stop = netdev_close, + #else .ndo_open = netdev_vir_if_open, .ndo_stop = netdev_vir_if_close, + #endif .ndo_start_xmit = rtw_xmit_entry, .ndo_set_mac_address = rtw_net_set_mac_address, .ndo_get_stats = rtw_net_get_stats, @@ -2525,8 +2777,14 @@ static void rtw_hook_vir_if_ops(struct net_device *ndev) #else ndev->init = rtw_ndev_init; ndev->uninit = rtw_ndev_uninit; + #ifdef CONFIG_NEW_NETDEV_HDL + ndev->open = netdev_open; + ndev->stop = netdev_close; + #else ndev->open = netdev_vir_if_open; ndev->stop = netdev_vir_if_close; + #endif + ndev->set_mac_address = rtw_net_set_mac_address; #endif } @@ -2603,6 +2861,10 @@ _adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, #ifdef CONFIG_P2P rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); #endif + + rtw_led_set_ctl_en_mask_virtual(padapter); + rtw_led_set_iface_en(padapter, 1); + res = _SUCCESS; free_drv_sw: @@ -2624,6 +2886,7 @@ void rtw_drv_stop_vir_if(_adapter *padapter) if (padapter == NULL) return; + RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(padapter)); pnetdev = padapter->pnetdev; @@ -2631,7 +2894,7 @@ void rtw_drv_stop_vir_if(_adapter *padapter) rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); #ifdef CONFIG_AP_MODE - if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { free_mlme_ap_info(padapter); #ifdef CONFIG_HOSTAPD_MLME hostapd_mode_unload(padapter); @@ -2646,11 +2909,14 @@ void rtw_drv_stop_vir_if(_adapter *padapter) #endif rtw_intf_stop(padapter); - + #ifndef CONFIG_NEW_NETDEV_HDL rtw_stop_drv_threads(padapter); - + #endif padapter->bup = _FALSE; } + #ifdef CONFIG_NEW_NETDEV_HDL + rtw_stop_drv_threads(padapter); + #endif /* cancel timer after thread stop */ rtw_cancel_all_timer(padapter); } @@ -2686,42 +2952,157 @@ void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj) rtw_drv_free_vir_if(dvobj->padapters[i]); } -void rtw_drv_del_vir_if(_adapter *padapter) -{ - rtw_drv_stop_vir_if(padapter); - rtw_drv_free_vir_if(padapter); -} -void rtw_drv_del_vir_ifaces(_adapter *primary_padapter) +#endif /*end of CONFIG_CONCURRENT_MODE*/ + +/* IPv4, IPv6 IP addr notifier */ +static int rtw_inetaddr_notifier_call(struct notifier_block *nb, + unsigned long action, void *data) { - int i; - struct dvobj_priv *dvobj = primary_padapter->dvobj; + struct in_ifaddr *ifa = (struct in_ifaddr *)data; + struct net_device *ndev; + struct mlme_ext_priv *pmlmeext = NULL; + struct mlme_ext_info *pmlmeinfo = NULL; + _adapter *adapter = NULL; - for (i = VIF_START_ID; i < dvobj->iface_nums; i++) - rtw_drv_del_vir_if(dvobj->padapters[i]); + if (!ifa || !ifa->ifa_dev || !ifa->ifa_dev->dev) + return NOTIFY_DONE; -} + ndev = ifa->ifa_dev->dev; -#endif /*end of CONFIG_CONCURRENT_MODE*/ + if (!is_rtw_ndev(ndev)) + return NOTIFY_DONE; -int rtw_os_ndevs_register(struct dvobj_priv *dvobj) -{ - int i, status = _SUCCESS; - struct registry_priv *regsty = dvobj_to_regsty(dvobj); - _adapter *adapter; + adapter = (_adapter *)rtw_netdev_priv(ifa->ifa_dev->dev); -#if defined(CONFIG_IOCTL_CFG80211) - if (rtw_cfg80211_dev_res_register(dvobj) != _SUCCESS) { - rtw_warn_on(1); - status = _FAIL; - goto exit; + if (adapter == NULL) + return NOTIFY_DONE; + + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + switch (action) { + case NETDEV_UP: + _rtw_memcpy(pmlmeinfo->ip_addr, &ifa->ifa_address, + RTW_IP_ADDR_LEN); + RTW_DBG("%s[%s]: up IP: %pI4\n", __func__, + ifa->ifa_label, pmlmeinfo->ip_addr); + break; + case NETDEV_DOWN: + _rtw_memset(pmlmeinfo->ip_addr, 0, RTW_IP_ADDR_LEN); + RTW_DBG("%s[%s]: down IP: %pI4\n", __func__, + ifa->ifa_label, pmlmeinfo->ip_addr); + break; + default: + RTW_DBG("%s: default action\n", __func__); + break; } -#endif + return NOTIFY_DONE; +} - for (i = 0; i < dvobj->iface_nums; i++) { +#ifdef CONFIG_IPV6 +static int rtw_inet6addr_notifier_call(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct inet6_ifaddr *inet6_ifa = data; + struct net_device *ndev; + struct pwrctrl_priv *pwrctl = NULL; + struct mlme_ext_priv *pmlmeext = NULL; + struct mlme_ext_info *pmlmeinfo = NULL; + _adapter *adapter = NULL; - if (i >= CONFIG_IFACE_NUMBER) { - RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER); + if (!inet6_ifa || !inet6_ifa->idev || !inet6_ifa->idev->dev) + return NOTIFY_DONE; + + ndev = inet6_ifa->idev->dev; + + if (!is_rtw_ndev(ndev)) + return NOTIFY_DONE; + + adapter = (_adapter *)rtw_netdev_priv(inet6_ifa->idev->dev); + + if (adapter == NULL) + return NOTIFY_DONE; + + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + pwrctl = adapter_to_pwrctl(adapter); + + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + switch (action) { + case NETDEV_UP: +#ifdef CONFIG_WOWLAN + pwrctl->wowlan_ns_offload_en = _TRUE; +#endif + _rtw_memcpy(pmlmeinfo->ip6_addr, &inet6_ifa->addr, + RTW_IPv6_ADDR_LEN); + RTW_DBG("%s: up IPv6 addrs: %pI6\n", __func__, + pmlmeinfo->ip6_addr); + break; + case NETDEV_DOWN: +#ifdef CONFIG_WOWLAN + pwrctl->wowlan_ns_offload_en = _FALSE; +#endif + _rtw_memset(pmlmeinfo->ip6_addr, 0, RTW_IPv6_ADDR_LEN); + RTW_DBG("%s: down IPv6 addrs: %pI6\n", __func__, + pmlmeinfo->ip6_addr); + break; + default: + RTW_DBG("%s: default action\n", __func__); + break; + } + return NOTIFY_DONE; +} +#endif + +static struct notifier_block rtw_inetaddr_notifier = { + .notifier_call = rtw_inetaddr_notifier_call +}; + +#ifdef CONFIG_IPV6 +static struct notifier_block rtw_inet6addr_notifier = { + .notifier_call = rtw_inet6addr_notifier_call +}; +#endif + +void rtw_inetaddr_notifier_register(void) +{ + RTW_INFO("%s\n", __func__); + register_inetaddr_notifier(&rtw_inetaddr_notifier); +#ifdef CONFIG_IPV6 + register_inet6addr_notifier(&rtw_inet6addr_notifier); +#endif +} + +void rtw_inetaddr_notifier_unregister(void) +{ + RTW_INFO("%s\n", __func__); + unregister_inetaddr_notifier(&rtw_inetaddr_notifier); +#ifdef CONFIG_IPV6 + unregister_inet6addr_notifier(&rtw_inet6addr_notifier); +#endif +} + +int rtw_os_ndevs_register(struct dvobj_priv *dvobj) +{ + int i, status = _SUCCESS; + struct registry_priv *regsty = dvobj_to_regsty(dvobj); + _adapter *adapter; + +#if defined(CONFIG_IOCTL_CFG80211) + if (rtw_cfg80211_dev_res_register(dvobj) != _SUCCESS) { + rtw_warn_on(1); + status = _FAIL; + goto exit; + } +#endif + + for (i = 0; i < dvobj->iface_nums; i++) { + + if (i >= CONFIG_IFACE_NUMBER) { + RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER); rtw_warn_on(1); continue; } @@ -2871,6 +3252,116 @@ void netdev_br_init(struct net_device *netdev) } #endif /* CONFIG_BR_EXT */ +#ifdef CONFIG_NEW_NETDEV_HDL +int _netdev_open(struct net_device *pnetdev) +{ + uint status; + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + RTW_INFO(FUNC_NDEV_FMT" start\n", FUNC_NDEV_ARG(pnetdev)); + + #ifdef CONFIG_AUTOSUSPEND + if (pwrctrlpriv->ps_flag == _TRUE) { + padapter->net_closed = _FALSE; + goto netdev_open_normal_process; + } + #endif /*CONFIG_AUTOSUSPEND*/ + + if (!rtw_is_hw_init_completed(padapter)) { // ips + rtw_clr_surprise_removed(padapter); + rtw_clr_drv_stopped(padapter); + RTW_ENABLE_FUNC(padapter, DF_RX_BIT); + RTW_ENABLE_FUNC(padapter, DF_TX_BIT); + status = rtw_hal_init(padapter); + if (status == _FAIL) + goto netdev_open_error; + rtw_led_control(padapter, LED_CTL_NO_LINK); + #ifndef RTW_HALMAC + status = rtw_mi_start_drv_threads(padapter); + if (status == _FAIL) { + RTW_ERR(FUNC_NDEV_FMT "Initialize driver thread failed!\n", FUNC_NDEV_ARG(pnetdev)); + goto netdev_open_error; + } + + rtw_intf_start(GET_PRIMARY_ADAPTER(padapter)); + #endif /* !RTW_HALMAC */ + + { + #ifdef CONFIG_BT_COEXIST_SOCKET_TRX + _adapter *prim_adpt = GET_PRIMARY_ADAPTER(padapter); + + if (prim_adpt && (_TRUE == prim_adpt->EEPROMBluetoothCoexist)) { + rtw_btcoex_init_socket(prim_adpt); + prim_adpt->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04; + rtw_btcoex_SetHciVersion(prim_adpt, 0x04); + } + #endif /* CONFIG_BT_COEXIST_SOCKET_TRX */ + + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); + + #ifndef CONFIG_IPS_CHECK_IN_WD + rtw_set_pwr_state_check_timer(pwrctrlpriv); + #endif /*CONFIG_IPS_CHECK_IN_WD*/ + } + + } + + /*if (padapter->bup == _FALSE) */ + { + rtw_hal_iface_init(padapter); + + #ifdef CONFIG_RTW_NAPI + if(padapter->napi_state == NAPI_DISABLE) { + napi_enable(&padapter->napi); + padapter->napi_state = NAPI_ENABLE; + } + #endif + + #ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_init_wiphy(padapter); + rtw_cfg80211_init_wdev_data(padapter); + #endif + /* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */ + rtw_netif_wake_queue(pnetdev); + + #ifdef CONFIG_BR_EXT + if (is_primary_adapter(padapter)) + netdev_br_init(pnetdev); + #endif /* CONFIG_BR_EXT */ + + + padapter->bup = _TRUE; + padapter->net_closed = _FALSE; + padapter->netif_up = _TRUE; + pwrctrlpriv->bips_processing = _FALSE; + } + + +netdev_open_normal_process: + RTW_INFO(FUNC_NDEV_FMT" Success (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); + return 0; + +netdev_open_error: + padapter->bup = _FALSE; + + #ifdef CONFIG_RTW_NAPI + if(padapter->napi_state == NAPI_ENABLE) { + napi_disable(&padapter->napi); + padapter->napi_state = NAPI_DISABLE; + } + #endif + + rtw_netif_carrier_off(pnetdev); + rtw_netif_stop_queue(pnetdev); + + RTW_ERR(FUNC_NDEV_FMT" Failed!! (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); + + return -1; + +} + +#else int _netdev_open(struct net_device *pnetdev) { uint status; @@ -2889,10 +3380,12 @@ int _netdev_open(struct net_device *pnetdev) rtw_sdio_set_power(1); #endif /* CONFIG_PLATFORM_INTEL_BYT */ + #ifdef CONFIG_AUTOSUSPEND if (pwrctrlpriv->ps_flag == _TRUE) { padapter->net_closed = _FALSE; goto netdev_open_normal_process; } + #endif if (padapter->bup == _FALSE) { #ifdef CONFIG_PLATFORM_INTEL_BYT @@ -2917,11 +3410,13 @@ int _netdev_open(struct net_device *pnetdev) RTW_INFO("MAC Address = "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr)); +#ifndef RTW_HALMAC status = rtw_start_drv_threads(padapter); if (status == _FAIL) { RTW_INFO("Initialize driver software resource Failed!\n"); goto netdev_open_error; } +#endif /* !RTW_HALMAC */ #ifdef CONFIG_RTW_NAPI if(padapter->napi_state == NAPI_DISABLE) { @@ -2930,10 +3425,9 @@ int _netdev_open(struct net_device *pnetdev) } #endif -#ifdef CONFIG_DRVEXT_MODULE - init_drvext(padapter); -#endif +#ifndef RTW_HALMAC rtw_intf_start(padapter); +#endif /* !RTW_HALMAC */ #ifdef CONFIG_IOCTL_CFG80211 rtw_cfg80211_init_wiphy(padapter); @@ -2959,7 +3453,7 @@ int _netdev_open(struct net_device *pnetdev) rtw_set_pwr_state_check_timer(pwrctrlpriv); #endif - /* netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */ + /* rtw_netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */ rtw_netif_wake_queue(pnetdev); #ifdef CONFIG_BR_EXT @@ -2989,6 +3483,15 @@ int _netdev_open(struct net_device *pnetdev) } #endif +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + pwrctrlpriv->radio_on_start_time = rtw_get_current_time(); + pwrctrlpriv->pwr_saving_start_time = rtw_get_current_time(); + pwrctrlpriv->pwr_saving_time = 0; + pwrctrlpriv->on_time = 0; + pwrctrlpriv->tx_time = 0; + pwrctrlpriv->rx_time = 0; +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + RTW_INFO("-871x_drv - drv_open, bup=%d\n", padapter->bup); return 0; @@ -3004,7 +3507,7 @@ int _netdev_open(struct net_device *pnetdev) } #endif - netif_carrier_off(pnetdev); + rtw_netif_carrier_off(pnetdev); rtw_netif_stop_queue(pnetdev); RTW_INFO("-871x_drv - drv_open fail, bup=%d\n", padapter->bup); @@ -3012,7 +3515,7 @@ int _netdev_open(struct net_device *pnetdev) return -1; } - +#endif int netdev_open(struct net_device *pnetdev) { int ret = _FALSE; @@ -3025,11 +3528,15 @@ int netdev_open(struct net_device *pnetdev) } _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); +#ifdef CONFIG_NEW_NETDEV_HDL + ret = _netdev_open(pnetdev); +#else if (is_primary_adapter(padapter)) ret = _netdev_open(pnetdev); #ifdef CONFIG_CONCURRENT_MODE else ret = _netdev_vir_if_open(pnetdev); +#endif #endif _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); @@ -3055,15 +3562,26 @@ int ips_netdrv_open(_adapter *padapter) rtw_clr_drv_stopped(padapter); /* padapter->bup = _TRUE; */ - +#ifdef CONFIG_NEW_NETDEV_HDL + if (!rtw_is_hw_init_completed(padapter)) { + status = rtw_hal_init(padapter); + if (status == _FAIL) { + goto netdev_open_error; + } + rtw_mi_hal_iface_init(padapter); + } +#else status = rtw_hal_init(padapter); if (status == _FAIL) { goto netdev_open_error; } +#endif #if 0 - rtw_restore_mac_addr(padapter); + rtw_mi_set_mac_addr(padapter); #endif +#ifndef RTW_HALMAC rtw_intf_start(padapter); +#endif /* !RTW_HALMAC */ #ifndef CONFIG_IPS_CHECK_IN_WD rtw_set_pwr_state_check_timer(adapter_to_pwrctl(padapter)); @@ -3079,15 +3597,16 @@ int ips_netdrv_open(_adapter *padapter) return _FAIL; } - int rtw_ips_pwr_up(_adapter *padapter) { int result; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); +#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) #ifdef DBG_CONFIG_ERROR_DETECT + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); struct sreset_priv *psrtpriv = &pHalData->srestpriv; #endif/* #ifdef DBG_CONFIG_ERROR_DETECT */ - u32 start_time = rtw_get_current_time(); +#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */ + systime start_time = rtw_get_current_time(); RTW_INFO("===> rtw_ips_pwr_up..............\n"); #if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) @@ -3108,7 +3627,7 @@ int rtw_ips_pwr_up(_adapter *padapter) void rtw_ips_pwr_down(_adapter *padapter) { - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); RTW_INFO("===> rtw_ips_pwr_down...................\n"); padapter->net_closed = _TRUE; @@ -3119,12 +3638,12 @@ void rtw_ips_pwr_down(_adapter *padapter) #endif void rtw_ips_dev_unload(_adapter *padapter) { - struct net_device *pnetdev = (struct net_device *)padapter->pnetdev; - struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); +#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) #ifdef DBG_CONFIG_ERROR_DETECT + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); struct sreset_priv *psrtpriv = &pHalData->srestpriv; #endif/* #ifdef DBG_CONFIG_ERROR_DETECT */ +#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */ RTW_INFO("====> %s...\n", __FUNCTION__); @@ -3142,8 +3661,97 @@ void rtw_ips_dev_unload(_adapter *padapter) rtw_hal_deinit(padapter); } +#ifdef CONFIG_NEW_NETDEV_HDL +int _pm_netdev_open(_adapter *padapter) +{ + uint status; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + struct net_device *pnetdev = padapter->pnetdev; + RTW_INFO(FUNC_NDEV_FMT" start\n", FUNC_NDEV_ARG(pnetdev)); + #ifdef CONFIG_AUTOSUSPEND + if (pwrctrlpriv->ps_flag == _TRUE) { + padapter->net_closed = _FALSE; + goto netdev_open_normal_process; + } + #endif /*CONFIG_AUTOSUSPEND*/ + + if (!rtw_is_hw_init_completed(padapter)) { // ips + rtw_clr_surprise_removed(padapter); + rtw_clr_drv_stopped(padapter); + status = rtw_hal_init(padapter); + if (status == _FAIL) + goto netdev_open_error; + rtw_led_control(padapter, LED_CTL_NO_LINK); + #ifndef RTW_HALMAC + status = rtw_mi_start_drv_threads(padapter); + if (status == _FAIL) { + RTW_ERR(FUNC_NDEV_FMT "Initialize driver thread failed!\n", FUNC_NDEV_ARG(pnetdev)); + goto netdev_open_error; + } + + rtw_intf_start(GET_PRIMARY_ADAPTER(padapter)); + #endif /* !RTW_HALMAC */ + + { + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); + + #ifndef CONFIG_IPS_CHECK_IN_WD + rtw_set_pwr_state_check_timer(pwrctrlpriv); + #endif /*CONFIG_IPS_CHECK_IN_WD*/ + } + + } + + /*if (padapter->bup == _FALSE) */ + { + rtw_hal_iface_init(padapter); + + padapter->bup = _TRUE; + padapter->net_closed = _FALSE; + padapter->netif_up = _TRUE; + pwrctrlpriv->bips_processing = _FALSE; + } + + +netdev_open_normal_process: + RTW_INFO(FUNC_NDEV_FMT" Success (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); + return 0; + +netdev_open_error: + padapter->bup = _FALSE; + + rtw_netif_carrier_off(pnetdev); + rtw_netif_stop_queue(pnetdev); + + RTW_ERR(FUNC_NDEV_FMT" Failed!! (bup=%d)\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); + + return -1; + +} +int _mi_pm_netdev_open(struct net_device *pnetdev) +{ + int i; + int status = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface->netif_up) { + status = _pm_netdev_open(iface); + if (status == -1) { + RTW_ERR("%s failled\n", __func__); + break; + } + } + } + + return status; +} +#endif /*CONFIG_NEW_NETDEV_HDL*/ int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) { int status = 0; @@ -3152,10 +3760,11 @@ int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) if (_TRUE == bnormal) { _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + #ifdef CONFIG_NEW_NETDEV_HDL + status = _mi_pm_netdev_open(pnetdev); + #else status = _netdev_open(pnetdev); -#if 0 - rtw_restore_mac_addr(padapter); -#endif + #endif _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); } #ifdef CONFIG_IPS @@ -3165,7 +3774,9 @@ int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) return status; } - +#ifdef CONFIG_CLIENT_PORT_CFG +extern void rtw_hw_client_port_release(_adapter *adapter); +#endif static int netdev_close(struct net_device *pnetdev) { _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); @@ -3177,15 +3788,21 @@ static int netdev_close(struct net_device *pnetdev) RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); #ifndef CONFIG_PLATFORM_INTEL_BYT + #ifdef CONFIG_AUTOSUSPEND if (pwrctl->bInternalAutoSuspend == _TRUE) { /* rtw_pwr_wakeup(padapter); */ if (pwrctl->rf_pwrstate == rf_off) pwrctl->ps_flag = _TRUE; } + #endif padapter->net_closed = _TRUE; padapter->netif_up = _FALSE; pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; +#ifdef CONFIG_CLIENT_PORT_CFG + if (MLME_IS_STA(padapter)) + rtw_hw_client_port_release(padapter); +#endif /* if (!rtw_is_hw_init_completed(padapter)) { RTW_INFO("(1)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter)?"_TRUE":"_FALSE"); @@ -3204,16 +3821,14 @@ static int netdev_close(struct net_device *pnetdev) #ifndef CONFIG_ANDROID /* s2. */ LeaveAllPowerSaveMode(padapter); - rtw_disassoc_cmd(padapter, 500, RTW_CMDF_DIRECTLY); + rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK); /* s2-2. indicate disconnect to os */ rtw_indicate_disconnect(padapter, 0, _FALSE); /* s2-3. */ - rtw_free_assoc_resources(padapter, 1); + rtw_free_assoc_resources_cmd(padapter, _TRUE, RTW_CMDF_WAIT_ACK); /* s2-4. */ rtw_free_network_queue(padapter, _TRUE); #endif - /* Close LED */ - rtw_led_control(padapter, LED_CTL_POWER_OFF); } #ifdef CONFIG_BR_EXT @@ -3229,8 +3844,8 @@ static int netdev_close(struct net_device *pnetdev) rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); #endif /* CONFIG_P2P */ + rtw_scan_abort(padapter); /* stop scanning process before wifi is going to down */ #ifdef CONFIG_IOCTL_CFG80211 - rtw_scan_abort(padapter); rtw_cfg80211_wait_scan_req_empty(padapter, 200); adapter_wdev_data(padapter)->bandroid_scan = _FALSE; /* padapter->rtw_wdev->iftype = NL80211_IFTYPE_MONITOR; */ /* set this at the end */ @@ -3289,6 +3904,7 @@ void rtw_ndev_destructor(struct net_device *ndev) if (ndev->ieee80211_ptr) rtw_mfree((u8 *)ndev->ieee80211_ptr, sizeof(struct wireless_dev)); #endif + free_netdev(ndev); } #ifdef CONFIG_ARP_KEEP_ALIVE @@ -3414,7 +4030,11 @@ static int route_dump(u32 *gw_addr , int *gw_index) oldfs = get_fs(); set_fs(KERNEL_DS); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) + err = sock_recvmsg(sock, &msg, MSG_DONTWAIT); +#else err = sock_recvmsg(sock, &msg, PAGE_SIZE, MSG_DONTWAIT); +#endif set_fs(oldfs); if (err < 0) @@ -3572,7 +4192,7 @@ int rtw_gw_addr_query(_adapter *padapter) pmlmepriv->gw_ip[1] = (gw_addr & 0xff00) >> 8; pmlmepriv->gw_ip[2] = (gw_addr & 0xff0000) >> 16; pmlmepriv->gw_ip[3] = (gw_addr & 0xff000000) >> 24; - _rtw_memcpy(pmlmepriv->gw_mac_addr, gw_mac, 6); + _rtw_memcpy(pmlmepriv->gw_mac_addr, gw_mac, ETH_ALEN); RTW_INFO("%s Gateway Mac:\t" MAC_FMT "\n", __FUNCTION__, MAC_ARG(pmlmepriv->gw_mac_addr)); RTW_INFO("%s Gateway IP:\t" IP_FMT "\n", __FUNCTION__, IP_ARG(pmlmepriv->gw_ip)); } else @@ -3584,17 +4204,22 @@ int rtw_gw_addr_query(_adapter *padapter) void rtw_dev_unload(PADAPTER padapter) { - struct net_device *pnetdev = (struct net_device *)padapter->pnetdev; struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); struct dvobj_priv *pobjpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &pobjpriv->drv_dbg; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 cnt = 0; - if (padapter->bup == _TRUE) { RTW_INFO("==> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); +#ifdef CONFIG_WOWLAN +#ifdef CONFIG_GPIO_WAKEUP + /*default wake up pin change to BT*/ + RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__); + rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _FALSE); +#endif /* CONFIG_GPIO_WAKEUP */ +#endif /* CONFIG_WOWLAN */ + rtw_set_drv_stopped(padapter); #ifdef CONFIG_XMIT_ACK if (padapter->xmitpriv.ack_tx) @@ -3603,22 +4228,17 @@ void rtw_dev_unload(PADAPTER padapter) rtw_intf_stop(padapter); - + #ifdef CONFIG_AUTOSUSPEND if (!pwrctl->bInternalAutoSuspend) + #endif + { rtw_stop_drv_threads(padapter); - while (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) { - if (cnt > 5) { - RTW_INFO("stop cmdthd timeout\n"); - break; - } else { - cnt++; - RTW_INFO("cmdthd is running(%d)\n", cnt); - rtw_msleep_os(10); + if (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) { + RTW_ERR("cmd_thread not stop !!\n"); + rtw_warn_on(1); } } - - /* check the status of IPS */ if (rtw_hal_check_ips_status(padapter) == _TRUE || pwrctl->rf_pwrstate == rf_off) { /* check HW status and SW state */ RTW_PRINT("%s: driver in IPS-FWLPS\n", __func__); @@ -3655,7 +4275,6 @@ void rtw_dev_unload(PADAPTER padapter) int rtw_suspend_free_assoc_resource(_adapter *padapter) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct net_device *pnetdev = padapter->pnetdev; #ifdef CONFIG_P2P struct wifidirect_info *pwdinfo = &padapter->wdinfo; #endif /* CONFIG_P2P */ @@ -3664,16 +4283,20 @@ int rtw_suspend_free_assoc_resource(_adapter *padapter) if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) { if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) - && check_fwstate(pmlmepriv, _FW_LINKED) -#ifdef CONFIG_P2P - && rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) -#endif /* CONFIG_P2P */ - ) { + && check_fwstate(pmlmepriv, _FW_LINKED) + #ifdef CONFIG_P2P + && (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) + #if defined(CONFIG_IOCTL_CFG80211) && RTW_P2P_GROUP_INTERFACE + || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) + #endif + ) + #endif /* CONFIG_P2P */ + ) { RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__, - pmlmepriv->cur_network.network.Ssid.Ssid, + pmlmepriv->cur_network.network.Ssid.Ssid, MAC_ARG(pmlmepriv->cur_network.network.MacAddress), - pmlmepriv->cur_network.network.Ssid.SsidLength, - pmlmepriv->assoc_ssid.SsidLength); + pmlmepriv->cur_network.network.Ssid.SsidLength, + pmlmepriv->assoc_ssid.SsidLength); rtw_set_to_roam(padapter, 1); } } @@ -3684,12 +4307,12 @@ int rtw_suspend_free_assoc_resource(_adapter *padapter) rtw_indicate_disconnect(padapter, 0, _FALSE); } #ifdef CONFIG_AP_MODE - else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) + else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) rtw_sta_flush(padapter, _TRUE); #endif /* s2-3. */ - rtw_free_assoc_resources(padapter, 1); + rtw_free_assoc_resources(padapter, _TRUE); /* s2-4. */ #ifdef CONFIG_AUTOSUSPEND @@ -3717,14 +4340,8 @@ int rtw_suspend_wow(_adapter *padapter) { u8 ch, bw, offset; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct net_device *pnetdev = padapter->pnetdev; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct wowlan_ioctl_param poidparam; - int i; - _adapter *iface = NULL; u8 ps_mode; int ret = _SUCCESS; @@ -3738,43 +4355,38 @@ int rtw_suspend_wow(_adapter *padapter) #endif if (pwrpriv->wowlan_mode == _TRUE) { -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT); -#endif - - if (pnetdev) - rtw_netif_stop_queue(pnetdev); - rtw_mi_buddy_netif_stop_queue(padapter, _TRUE); + rtw_mi_netif_stop_queue(padapter); + #ifdef CONFIG_CONCURRENT_MODE + rtw_mi_buddy_netif_carrier_off(padapter); + #endif /* 0. Power off LED */ rtw_led_control(padapter, LED_CTL_POWER_OFF); + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + /* 2.only for SDIO disable interrupt */ + rtw_intf_stop(padapter); + + /* 2.1 clean interrupt */ + rtw_hal_clear_interrupt(padapter); +#endif /* CONFIG_SDIO_HCI */ + /* 1. stop thread */ rtw_set_drv_stopped(padapter); /*for stop thread*/ - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if ((iface) && (iface->bup == _TRUE)) - rtw_stop_drv_threads(iface); - } + rtw_mi_stop_drv_threads(padapter); + rtw_clr_drv_stopped(padapter); /*for 32k command*/ /* #ifdef CONFIG_LPS */ /* rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); */ /* #endif */ -#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) - /* 2. disable interrupt */ - rtw_mi_intf_stop(padapter); - - /* 2.1 clean interupt */ - rtw_hal_clear_interrupt(padapter); -#endif /* CONFIG_SDIO_HCI */ - + #ifdef CONFIG_SDIO_HCI /* 2.2 free irq */ - /* sdio_free_irq(adapter_to_dvobj(padapter)); */ -#if !(CONFIG_RTW_SDIO_KEEP_IRQ) - if (padapter->intf_free_irq) - padapter->intf_free_irq(adapter_to_dvobj(padapter)); -#endif + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + sdio_free_irq(adapter_to_dvobj(padapter)); + #endif + #endif/*CONFIG_SDIO_HCI*/ #ifdef CONFIG_RUNTIME_PORT_SWITCH if (rtw_port_switch_chk(padapter)) { @@ -3823,11 +4435,14 @@ int rtw_suspend_wow(_adapter *padapter) rtw_mi_update_union_chan_inf(padapter, ch, offset, bw); } #endif - #ifdef CONFIG_CONCURRENT_MODE rtw_mi_buddy_suspend_free_assoc_resource(padapter); #endif +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT); +#endif + if (pwrpriv->wowlan_pno_enable) { RTW_PRINT("%s: pno: %d\n", __func__, pwrpriv->wowlan_pno_enable); @@ -3836,8 +4451,12 @@ int rtw_suspend_wow(_adapter *padapter) #endif } #ifdef CONFIG_LPS - else - rtw_set_ps_mode(padapter, PS_MODE_MAX, 0, 0, "WOWLAN"); + else { + if (!(pwrpriv->wowlan_dis_lps)) { + rtw_wow_lps_level_decide(padapter, _TRUE); + rtw_set_ps_mode(padapter, PS_MODE_MAX, 0, 0, "WOWLAN"); + } + } #endif /* #ifdef CONFIG_LPS */ } else @@ -3852,13 +4471,8 @@ int rtw_suspend_ap_wow(_adapter *padapter) { u8 ch, bw, offset; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); struct wowlan_ioctl_param poidparam; - int i; - _adapter *iface = NULL; u8 ps_mode; int ret = _SUCCESS; @@ -3868,34 +4482,29 @@ int rtw_suspend_ap_wow(_adapter *padapter) RTW_INFO("wowlan_ap_mode: %d\n", pwrpriv->wowlan_ap_mode); -#ifdef CONFIG_BT_COEXIST - rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT); -#endif - - rtw_mi_netif_stop_queue(padapter, _FALSE); + rtw_mi_netif_stop_queue(padapter); /* 0. Power off LED */ rtw_led_control(padapter, LED_CTL_POWER_OFF); - /* 1. stop thread */ - rtw_set_drv_stopped(padapter); /*for stop thread*/ - for (i = 0; i < dvobj->iface_nums; i++) { - iface = dvobj->padapters[i]; - if ((iface) && (iface->bup == _TRUE)) - rtw_stop_drv_threads(iface); - } - rtw_clr_drv_stopped(padapter); /*for 32k command*/ - #ifdef CONFIG_SDIO_HCI - /* 2. disable interrupt*/ - rtw_mi_intf_stop(padapter); + /* 2.only for SDIO disable interrupt*/ + rtw_intf_stop(padapter); - /* 2.1 clean interupt */ + /* 2.1 clean interrupt */ rtw_hal_clear_interrupt(padapter); #endif /* CONFIG_SDIO_HCI */ + /* 1. stop thread */ + rtw_set_drv_stopped(padapter); /*for stop thread*/ + rtw_mi_stop_drv_threads(padapter); + rtw_clr_drv_stopped(padapter); /*for 32k command*/ + + #ifdef CONFIG_SDIO_HCI /* 2.2 free irq */ - if (padapter->intf_free_irq) - padapter->intf_free_irq(adapter_to_dvobj(padapter)); + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + sdio_free_irq(adapter_to_dvobj(padapter)); + #endif + #endif/*CONFIG_SDIO_HCI*/ #ifdef CONFIG_RUNTIME_PORT_SWITCH if (rtw_port_switch_chk(padapter)) { @@ -3933,15 +4542,22 @@ int rtw_suspend_ap_wow(_adapter *padapter) for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if ((iface) && rtw_is_adapter_up(iface)) { - if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | _FW_LINKED)) - rtw_mi_buddy_suspend_free_assoc_resource(iface); + if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE) + rtw_suspend_free_assoc_resource(iface); } } } +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT); +#endif + #ifdef CONFIG_LPS - rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, 0, "AP-WOWLAN"); + if (!(pwrpriv->wowlan_dis_lps)) { + rtw_wow_lps_level_decide(padapter, _TRUE); + rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, 0, "AP-WOWLAN"); + } #endif RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); @@ -3952,8 +4568,6 @@ int rtw_suspend_ap_wow(_adapter *padapter) int rtw_suspend_normal(_adapter *padapter) { - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); int ret = _SUCCESS; RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); @@ -3961,8 +4575,7 @@ int rtw_suspend_normal(_adapter *padapter) #ifdef CONFIG_BT_COEXIST rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND); #endif - - rtw_mi_netif_stop_queue(padapter, _TRUE); + rtw_mi_netif_caroff_qstop(padapter); rtw_mi_suspend_free_assoc_resource(padapter); @@ -3980,14 +4593,13 @@ int rtw_suspend_normal(_adapter *padapter) #endif rtw_dev_unload(padapter); - /* sdio_deinit(adapter_to_dvobj(padapter)); */ - if (padapter->intf_deinit) - padapter->intf_deinit(adapter_to_dvobj(padapter)); + #ifdef CONFIG_SDIO_HCI + sdio_deinit(adapter_to_dvobj(padapter)); -#if !(CONFIG_RTW_SDIO_KEEP_IRQ) - if(padapter->intf_free_irq) - padapter->intf_free_irq(adapter_to_dvobj(padapter)); -#endif + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + sdio_free_irq(adapter_to_dvobj(padapter)); + #endif + #endif /*CONFIG_SDIO_HCI*/ RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); return ret; @@ -3995,13 +4607,15 @@ int rtw_suspend_normal(_adapter *padapter) int rtw_suspend_common(_adapter *padapter) { - struct dvobj_priv *psdpriv = padapter->dvobj; - struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; - struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(psdpriv); + struct dvobj_priv *dvobj = padapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); +#ifdef CONFIG_WOWLAN struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#endif int ret = 0; - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); RTW_PRINT(" suspend start\n"); RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid); @@ -4034,7 +4648,6 @@ int rtw_suspend_common(_adapter *padapter) rtw_mi_cancel_all_timer(padapter); LeaveAllPowerSaveModeDirect(padapter); - rtw_stop_cmd_thread(padapter); rtw_ps_deny_cancel(padapter, PS_DENY_SUSPEND); @@ -4082,7 +4695,6 @@ int rtw_resume_process_wow(_adapter *padapter) struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - struct net_device *pnetdev = padapter->pnetdev; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; @@ -4093,7 +4705,6 @@ int rtw_resume_process_wow(_adapter *padapter) RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); if (padapter) { - pnetdev = padapter->pnetdev; pwrpriv = adapter_to_pwrctl(padapter); } else { pdbgpriv->dbg_resume_error_cnt++; @@ -4119,7 +4730,10 @@ int rtw_resume_process_wow(_adapter *padapter) if (pwrpriv->wowlan_mode == _TRUE) { #ifdef CONFIG_LPS - rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); + if (!(pwrpriv->wowlan_dis_lps)) { + rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "WOWLAN"); + rtw_wow_lps_level_decide(padapter, _FALSE); + } #endif /* CONFIG_LPS */ pwrpriv->bFwCurrentInPSMode = _FALSE; @@ -4129,13 +4743,14 @@ int rtw_resume_process_wow(_adapter *padapter) rtw_hal_clear_interrupt(padapter); #endif -#if !(CONFIG_RTW_SDIO_KEEP_IRQ) - /* if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { */ - if ((padapter->intf_alloc_irq) && (padapter->intf_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)) { + #ifdef CONFIG_SDIO_HCI + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { ret = -1; goto exit; } -#endif + #endif + #endif/*CONFIG_SDIO_HCI*/ /* Disable WOW, set H2C command */ poidparam.subcode = WOWLAN_DISABLE; @@ -4162,8 +4777,8 @@ int rtw_resume_process_wow(_adapter *padapter) #endif /* start netif queue */ - if (pnetdev) - rtw_netif_wake_queue(pnetdev); + rtw_mi_netif_wake_queue(padapter); + } else RTW_PRINT("%s: ### ERROR ### wowlan_mode=%d\n", __FUNCTION__, pwrpriv->wowlan_mode); @@ -4186,7 +4801,7 @@ int rtw_resume_process_wow(_adapter *padapter) rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)), 0); - rtw_free_assoc_resources(padapter, 1); + rtw_free_assoc_resources(padapter, _TRUE); pmlmeinfo->state = WIFI_FW_NULL_STATE; } else { @@ -4195,21 +4810,6 @@ int rtw_resume_process_wow(_adapter *padapter) } } - if (pwrpriv->wowlan_wake_reason == FW_DECISION_DISCONNECT) - rtw_lock_ext_suspend_timeout(2000); - - if (pwrpriv->wowlan_wake_reason == RX_GTK || - pwrpriv->wowlan_wake_reason == RX_DISASSOC|| - pwrpriv->wowlan_wake_reason == RX_DEAUTH) - rtw_lock_ext_suspend_timeout(8000); - - if (pwrpriv->wowlan_wake_reason == RX_PNO) { - #ifdef CONFIG_IOCTL_CFG80211 - rtw_cfg80211_disconnected(padapter->rtw_wdev, 0, NULL, 0, 1, GFP_ATOMIC); - #endif - rtw_lock_ext_suspend_timeout(10000); - } - if (pwrpriv->wowlan_mode == _TRUE) { pwrpriv->bips_processing = _FALSE; _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); @@ -4222,7 +4822,7 @@ int rtw_resume_process_wow(_adapter *padapter) pwrpriv->wowlan_mode = _FALSE; /* Power On LED */ -#ifdef CONFIG_SW_LED +#ifdef CONFIG_RTW_SW_LED if (pwrpriv->wowlan_wake_reason == RX_DISASSOC|| pwrpriv->wowlan_wake_reason == RX_DEAUTH|| @@ -4249,7 +4849,6 @@ int rtw_resume_process_wow(_adapter *padapter) int rtw_resume_process_ap_wow(_adapter *padapter) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct net_device *pnetdev = padapter->pnetdev; struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); struct dvobj_priv *psdpriv = padapter->dvobj; struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; @@ -4261,7 +4860,6 @@ int rtw_resume_process_ap_wow(_adapter *padapter) RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); if (padapter) { - pnetdev = padapter->pnetdev; pwrpriv = adapter_to_pwrctl(padapter); } else { pdbgpriv->dbg_resume_error_cnt++; @@ -4271,7 +4869,10 @@ int rtw_resume_process_ap_wow(_adapter *padapter) #ifdef CONFIG_LPS - rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "AP-WOWLAN"); + if (!(pwrpriv->wowlan_dis_lps)) { + rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "AP-WOWLAN"); + rtw_wow_lps_level_decide(padapter, _FALSE); + } #endif /* CONFIG_LPS */ pwrpriv->bFwCurrentInPSMode = _FALSE; @@ -4280,12 +4881,14 @@ int rtw_resume_process_ap_wow(_adapter *padapter) rtw_hal_clear_interrupt(padapter); - /* if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { */ - if ((padapter->intf_alloc_irq) && (padapter->intf_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)) { + #ifdef CONFIG_SDIO_HCI + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { ret = -1; goto exit; } - + #endif + #endif/*CONFIG_SDIO_HCI*/ /* Disable WOW, set H2C command */ poidparam.subcode = WOWLAN_AP_DISABLE; rtw_hal_set_hwreg(padapter, HW_VAR_WOWLAN, (u8 *)&poidparam); @@ -4321,13 +4924,15 @@ int rtw_resume_process_ap_wow(_adapter *padapter) for (i = 0; i < dvobj->iface_nums; i++) { iface = dvobj->padapters[i]; if ((iface) && rtw_is_adapter_up(iface)) { - if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | _FW_LINKED)) + if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE | _FW_LINKED)) rtw_reset_drv_sw(iface); } } } rtw_mi_intf_start(padapter); + + /* start netif queue */ rtw_mi_netif_wake_queue(padapter); if (padapter->pid[1] != 0) { @@ -4339,9 +4944,6 @@ int rtw_resume_process_ap_wow(_adapter *padapter) /* rtw_unlock_suspend(); */ #endif /* CONFIG_RESUME_IN_WORKQUEUE */ - if (pwrpriv->wowlan_wake_reason == AP_OFFLOAD_WAKEUP) - rtw_lock_ext_suspend_timeout(8000); - pwrpriv->bips_processing = _FALSE; _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); #ifndef CONFIG_IPS_CHECK_IN_WD @@ -4355,7 +4957,7 @@ int rtw_resume_process_ap_wow(_adapter *padapter) #endif /* CONFIG_BT_COEXIST */ /* Power On LED */ -#ifdef CONFIG_SW_LED +#ifdef CONFIG_RTW_SW_LED rtw_led_control(padapter, LED_CTL_LINK); #endif @@ -4378,18 +4980,18 @@ void rtw_mi_resume_process_normal(_adapter *padapter) pmlmepriv = &iface->mlmepriv; if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv)); - if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) - rtw_roaming(padapter, NULL); + if (rtw_chk_roam_flags(iface, RTW_ROAM_ON_RESUME)) + rtw_roaming(iface, NULL); - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); - rtw_ap_restore_network(padapter); + } else if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) { + RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(iface), MLME_IS_AP(iface) ? "AP" : "MESH"); + rtw_ap_restore_network(iface); } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) - RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv)); else - RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(iface), get_fwstate(pmlmepriv)); } } } @@ -4414,21 +5016,26 @@ int rtw_resume_process_normal(_adapter *padapter) pdbgpriv = &psdpriv->drv_dbg; RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); + + #ifdef CONFIG_SDIO_HCI /* interface init */ - /* if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) */ - if ((padapter->intf_init) && (padapter->intf_init(adapter_to_dvobj(padapter)) != _SUCCESS)) { + if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) { ret = -1; goto exit; } + #endif/*CONFIG_SDIO_HCI*/ + rtw_clr_surprise_removed(padapter); rtw_hal_disable_interrupt(padapter); -#if !(CONFIG_RTW_SDIO_KEEP_IRQ) - /* if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) */ - if ((padapter->intf_alloc_irq) && (padapter->intf_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)) { + + #ifdef CONFIG_SDIO_HCI + #if !(CONFIG_RTW_SDIO_KEEP_IRQ) + if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) { ret = -1; goto exit; } -#endif + #endif + #endif/*CONFIG_SDIO_HCI*/ rtw_mi_reset_drv_sw(padapter); @@ -4441,7 +5048,7 @@ int rtw_resume_process_normal(_adapter *padapter) goto exit; } - rtw_mi_netif_carrier_on(padapter); + rtw_mi_netif_caron_qstart(padapter); if (padapter->pid[1] != 0) { RTW_INFO("pid[1]:%d\n", padapter->pid[1]); @@ -4466,10 +5073,8 @@ int rtw_resume_process_normal(_adapter *padapter) int rtw_resume_common(_adapter *padapter) { int ret = 0; - u32 start_time = rtw_get_current_time(); + systime start_time = rtw_get_current_time(); struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - if (pwrpriv->bInSuspend == _FALSE) return 0; @@ -4495,9 +5100,7 @@ int rtw_resume_common(_adapter *padapter) if (pwrpriv) { pwrpriv->bInSuspend = _FALSE; -#ifdef CONFIG_WOWLAN pwrpriv->wowlan_in_resume = _FALSE; -#endif } RTW_PRINT("%s:%d in %d ms\n", __FUNCTION__ , ret, rtw_get_passing_time_ms(start_time)); diff --git a/os_dep/linux/pci_intf.c b/os_dep/linux/pci_intf.c index 7b915c2..4aeb9a3 100644 --- a/os_dep/linux/pci_intf.c +++ b/os_dep/linux/pci_intf.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _HCI_INTF_C_ #include @@ -57,6 +52,7 @@ int rtw_resume_process(_adapter *padapter); static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid); static void rtw_dev_remove(struct pci_dev *pdev); +static void rtw_dev_shutdown(struct pci_dev *pdev); static struct specific_device_id specific_device_id_tbl[] = { {.idVendor = 0x0b05, .idProduct = 0x1791, .flags = SPEC_DEV_ID_DISABLE_HT}, @@ -77,6 +73,9 @@ struct pci_device_id rtw_pci_id_tbl[] = { #ifdef CONFIG_RTL8192E {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x818B), .driver_data = RTL8192E}, #endif +#ifdef CONFIG_RTL8192F + {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xf192), .driver_data = RTL8192F}, +#endif #ifdef CONFIG_RTL8723B {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xb723), .driver_data = RTL8723B}, #endif @@ -108,7 +107,7 @@ static struct pci_drv_priv pci_drvpriv = { .rtw_pci_drv.name = (char *)DRV_NAME, .rtw_pci_drv.probe = rtw_drv_init, .rtw_pci_drv.remove = rtw_dev_remove, - .rtw_pci_drv.shutdown = rtw_dev_remove, + .rtw_pci_drv.shutdown = rtw_dev_shutdown, .rtw_pci_drv.id_table = rtw_pci_id_tbl, #ifdef CONFIG_PM .rtw_pci_drv.suspend = rtw_pci_suspend, @@ -220,6 +219,16 @@ void rtw_pci_aspm_config_clkreql0sl1(_adapter *padapter) else tmp8 &= (~BIT7); + /* Default set L1 entrance latency to 16us */ + /* L0s: b[0-2], L1: b[3-5]*/ + if (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1) { + tmp8 &= (~0x38); + tmp8 |= 0x20; +#ifdef CONFIG_PCI_DYNAMIC_ASPM + pHalData->bAspmL1LastIdle = 1; +#endif + } + rtw_hal_pci_dbi_write(padapter, 0x70f, tmp8); @@ -277,6 +286,65 @@ void rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 enablel1off) } +#ifdef CONFIG_PCI_DYNAMIC_ASPM +void rtw_pci_aspm_config_dynamic_l1_ilde_time(_adapter *padapter) +{ + BOOLEAN bCurrentIdle = 1; /* Default idle 4us (0x70F = 0x17)*/ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + int current_tx_tp = pdvobjpriv->traffic_stat.cur_tx_tp; + int current_rx_tp = pdvobjpriv->traffic_stat.cur_rx_tp; + int current_tp = current_tx_tp + current_rx_tp; + u8 tmp8 = 0; + + if (padapter->registrypriv.wifi_spec) + return; + + if (!(pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1)) + return; + +#if 0 + RTW_INFO("current_tx_tp = %d\n", current_tx_tp); + RTW_INFO("current_rx_tp = %d\n", current_rx_tp); + RTW_INFO("current_tp = %d\n", current_tp); +#endif + + if ((rtw_linked_check(padapter) == _TRUE) && + ((current_tx_tp >= 50)|| + (current_rx_tp >= 50))) + /*(current_rx_tp >= 10))*/ + /*(current_tp >= 10))*/ + { + bCurrentIdle = 0; + } + else + { + bCurrentIdle = 1; + } + + if(bCurrentIdle != pHalData->bAspmL1LastIdle) + { + pHalData->bAspmL1LastIdle = bCurrentIdle; + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70F); + tmp8 &= (~0x38); + + if(bCurrentIdle) { + /*tmp8 |= 0x10; *//*L1 entrance latency: 4us*/ + /*tmp8 |= 0x18; *//*L1 entrance latency: 8us*/ + tmp8 |= 0x20; /*L1 entrance latency: 16us*/ + rtw_hal_pci_dbi_write(padapter, 0x70F, tmp8 ); + } + else { + tmp8 |= 0x28; /*L1 entrance latency: 32us*/ + rtw_hal_pci_dbi_write(padapter, 0x70F, tmp8 ); + } + } + +} +#endif + void rtw_pci_dump_aspm_info(_adapter *padapter) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); @@ -285,6 +353,7 @@ void rtw_pci_dump_aspm_info(_adapter *padapter) u8 tmp8 = 0; u16 tmp16 = 0; u32 tmp32 = 0; + u8 l1_idle = 0; RTW_INFO("***** ASPM Capability *****\n"); @@ -316,6 +385,7 @@ void rtw_pci_dump_aspm_info(_adapter *padapter) RTW_INFO("CLK REQ: %s\n", (tmp8 & BIT4) ? "Enable" : "Disable"); tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f); + l1_idle = tmp8 & 0x38; RTW_INFO("ASPM L0s: %s\n", (tmp8&BIT7) ? "Enable" : "Disable"); tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); @@ -323,6 +393,9 @@ void rtw_pci_dump_aspm_info(_adapter *padapter) tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718); RTW_INFO("ASPM L1OFF:%s\n", (tmp8 & BIT5) ? "Enable" : "Disable"); + + RTW_INFO("********* MISC **********\n"); + RTW_INFO("ASPM L1 Idel Time: 0x%x\n", l1_idle>>3); RTW_INFO("*************************\n"); } @@ -660,7 +733,7 @@ static s32 rtw_pci_parse_configuration(struct pci_dev *pdev, struct dvobj_priv * /* PPCI_COMMON_CONFIG pPciConfig = (PPCI_COMMON_CONFIG) pucBuffer; */ /* u16 usPciCommand = pPciConfig->Command; */ u16 usPciCommand = 0; - int Result, ret; + int Result, ret = _FAIL; u8 CapabilityOffset; RT_PCI_CAPABILITIES_HEADER CapabilityHdr; u8 PCIeCap; @@ -1062,6 +1135,12 @@ static void rtw_decide_chip_type_by_pci_driver_data(struct dvobj_priv *pdvobj, c } #endif +#ifdef CONFIG_RTL8192F + if (pdvobj->chip_type == RTL8192F) { + pdvobj->HardwareType = HARDWARE_TYPE_RTL8192FE; + RTW_INFO("CHIP TYPE: RTL8192FE\n"); + } +#endif #ifdef CONFIG_RTL8814A if (pdvobj->chip_type == RTL8814A) { pdvobj->HardwareType = HARDWARE_TYPE_RTL8814AE; @@ -1134,6 +1213,7 @@ static struct dvobj_priv *pci_dvobj_init(struct pci_dev *pdev, const struct pci_ goto disable_picdev; } } + dvobj->bdma64 = _FALSE; } pci_set_master(pdev); @@ -1351,6 +1431,11 @@ u8 rtw_set_hal_ops(_adapter *padapter) rtl8192ee_set_hal_ops(padapter); #endif +#ifdef CONFIG_RTL8192F + if (rtw_get_chip_type(padapter) == RTL8192F) + rtl8192fe_set_hal_ops(padapter); +#endif + #ifdef CONFIG_RTL8814A if (rtw_get_chip_type(padapter) == RTL8814A) rtl8814ae_set_hal_ops(padapter); @@ -1401,6 +1486,11 @@ void pci_set_intf_ops(_adapter *padapter, struct _io_ops *pops) rtl8192ee_set_intf_ops(pops); #endif +#ifdef CONFIG_RTL8192F + if (rtw_get_chip_type(padapter) == RTL8192F) + rtl8192fe_set_intf_ops(pops); +#endif + #ifdef CONFIG_RTL8814A if (rtw_get_chip_type(padapter) == RTL8814A) rtl8814ae_set_intf_ops(pops); @@ -1569,27 +1659,23 @@ static int rtw_pci_resume(struct pci_dev *pdev) device_set_wakeup_enable(&pdev->dev, false); #endif - if (pwrpriv->bInternalAutoSuspend) + if (pwrpriv->wowlan_mode || pwrpriv->wowlan_ap_mode) { + rtw_resume_lock_suspend(); err = rtw_resume_process(padapter); - else { - if (pwrpriv->wowlan_mode || pwrpriv->wowlan_ap_mode) { + rtw_resume_unlock_suspend(); + } else { +#ifdef CONFIG_RESUME_IN_WORKQUEUE + rtw_resume_in_workqueue(pwrpriv); +#else + if (rtw_is_earlysuspend_registered(pwrpriv)) { + /* jeff: bypass resume here, do in late_resume */ + rtw_set_do_late_resume(pwrpriv, _TRUE); + } else { rtw_resume_lock_suspend(); err = rtw_resume_process(padapter); rtw_resume_unlock_suspend(); - } else { -#ifdef CONFIG_RESUME_IN_WORKQUEUE - rtw_resume_in_workqueue(pwrpriv); -#else - if (rtw_is_earlysuspend_registered(pwrpriv)) { - /* jeff: bypass resume here, do in late_resume */ - rtw_set_do_late_resume(pwrpriv, _TRUE); - } else { - rtw_resume_lock_suspend(); - err = rtw_resume_process(padapter); - rtw_resume_unlock_suspend(); - } -#endif } +#endif } exit: @@ -1644,6 +1730,11 @@ _adapter *rtw_pci_primary_adapter_init(struct dvobj_priv *dvobj, struct pci_dev /* .4 */ rtw_hal_chip_configure(padapter); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_Initialize(padapter); +#endif + rtw_btcoex_wifionly_initialize(padapter); + /* step 4. read efuse/eeprom data and get mac_addr */ if (rtw_hal_read_chip_info(padapter) == _FAIL) goto free_hal_data; @@ -1652,15 +1743,6 @@ _adapter *rtw_pci_primary_adapter_init(struct dvobj_priv *dvobj, struct pci_dev if (rtw_init_drv_sw(padapter) == _FAIL) goto free_hal_data; -#ifdef CONFIG_BT_COEXIST - if (GET_HAL_DATA(padapter)->EEPROMBluetoothCoexist) - rtw_btcoex_Initialize(padapter); - else - rtw_btcoex_wifionly_initialize(padapter); -#else /* !CONFIG_BT_COEXIST */ - rtw_btcoex_wifionly_initialize(padapter); -#endif /* CONFIG_BT_COEXIST */ - if (rtw_hal_inirp_init(padapter) == _FAIL) goto free_hal_data; @@ -1693,6 +1775,9 @@ _adapter *rtw_pci_primary_adapter_init(struct dvobj_priv *dvobj, struct pci_dev free_adapter: if (status != _SUCCESS && padapter) { + #ifdef RTW_HALMAC + rtw_halmac_deinit_adapter(dvobj); + #endif rtw_vmfree((u8 *)padapter, sizeof(*padapter)); padapter = NULL; } @@ -1710,7 +1795,7 @@ static void rtw_pci_primary_adapter_deinit(_adapter *padapter) rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); #ifdef CONFIG_AP_MODE - if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) { free_mlme_ap_info(padapter); #ifdef CONFIG_HOSTAPD_MLME hostapd_mode_unload(padapter); @@ -1848,7 +1933,6 @@ static void rtw_dev_remove(struct pci_dev *pdev) _adapter *padapter = dvobj_get_primary_adapter(pdvobjpriv); struct net_device *pnetdev = padapter->pnetdev; - if (pdvobjpriv->processing_dev_remove == _TRUE) { RTW_WARN("%s-line%d: Warning! device has been removed!\n", __func__, __LINE__); return; @@ -1876,7 +1960,7 @@ static void rtw_dev_remove(struct pci_dev *pdev) /*else { - GET_HAL_DATA(padapter)->hw_init_completed = _FALSE; + rtw_set_hw_init_completed(padapter, _FALSE); }*/ #endif @@ -1886,7 +1970,7 @@ static void rtw_dev_remove(struct pci_dev *pdev) rtw_unregister_early_suspend(dvobj_to_pwrctl(pdvobjpriv)); #endif - if (padapter->bFWReady == _TRUE) { + if (GET_HAL_DATA(padapter)->bFWReady == _TRUE) { rtw_pm_set_ips(padapter, IPS_NONE); rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); @@ -1920,6 +2004,23 @@ static void rtw_dev_remove(struct pci_dev *pdev) return; } +static void rtw_dev_shutdown(struct pci_dev *pdev) +{ + struct dvobj_priv *pdvobjpriv = pci_get_drvdata(pdev); + _adapter *padapter = dvobj_get_primary_adapter(pdvobjpriv); + struct net_device *pnetdev = padapter->pnetdev; + +#ifdef CONFIG_RTL8723D + if (IS_HARDWARE_TYPE_8723DE(padapter)) { + u1Byte u1Tmp; + + u1Tmp = PlatformEFIORead1Byte(padapter, 0x75 /*REG_HCI_OPT_CTRL_8723D+1*/); + PlatformEFIOWrite1Byte(padapter, 0x75 /*REG_HCI_OPT_CTRL_8723D+1*/, (u1Tmp|BIT0));/*Disable USB Suspend Signal*/ + } +#endif + + rtw_dev_remove(pdev); +} static int __init rtw_drv_entry(void) { @@ -1939,6 +2040,7 @@ static int __init rtw_drv_entry(void) rtw_suspend_lock_init(); rtw_drv_proc_init(); rtw_ndev_notifier_register(); + rtw_inetaddr_notifier_register(); ret = pci_register_driver(&pci_drvpriv.rtw_pci_drv); @@ -1947,6 +2049,7 @@ static int __init rtw_drv_entry(void) rtw_suspend_lock_uninit(); rtw_drv_proc_deinit(); rtw_ndev_notifier_unregister(); + rtw_inetaddr_notifier_unregister(); goto exit; } @@ -1966,6 +2069,7 @@ static void __exit rtw_drv_halt(void) rtw_suspend_lock_uninit(); rtw_drv_proc_deinit(); rtw_ndev_notifier_unregister(); + rtw_inetaddr_notifier_unregister(); RTW_PRINT("module exit success\n"); diff --git a/os_dep/linux/pci_ops_linux.c b/os_dep/linux/pci_ops_linux.c index 5eed11a..b7ee82b 100644 --- a/os_dep/linux/pci_ops_linux.c +++ b/os_dep/linux/pci_ops_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,11 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - *******************************************************************************/ + *****************************************************************************/ #define _PCI_OPS_LINUX_C_ #include diff --git a/os_dep/linux/recv_linux.c b/os_dep/linux/recv_linux.c index 48fdb42..632d32b 100644 --- a/os_dep/linux/recv_linux.c +++ b/os_dep/linux/recv_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _RECV_OSDEP_C_ #include @@ -25,7 +20,6 @@ int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pclonef { int res = _SUCCESS; _pkt *pkt_copy = NULL; - struct rx_pkt_attrib *pattrib = &pcloneframe->u.hdr.attrib; if (pskb == NULL) { RTW_INFO("%s [WARN] skb == NULL, drop frag frame\n", __func__); @@ -166,8 +160,7 @@ int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 void rtw_os_free_recvframe(union recv_frame *precvframe) { if (precvframe->u.hdr.pkt) { - rtw_skb_free(precvframe->u.hdr.pkt);/* free skb by driver */ - + rtw_os_pkt_free(precvframe->u.hdr.pkt); precvframe->u.hdr.pkt = NULL; } } @@ -190,7 +183,7 @@ int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe) { int res = _SUCCESS; - precvframe->u.hdr.pkt_newalloc = precvframe->u.hdr.pkt = NULL; + precvframe->u.hdr.pkt = NULL; return res; } @@ -210,10 +203,7 @@ void rtw_os_recv_resource_free(struct recv_priv *precvpriv) #endif /* CONFIG_RTW_NAPI */ for (i = 0; i < NR_RECVFRAME; i++) { - if (precvframe->u.hdr.pkt) { - rtw_skb_free(precvframe->u.hdr.pkt);/* free skb by driver */ - precvframe->u.hdr.pkt = NULL; - } + rtw_os_free_recvframe(precvframe); precvframe++; } } @@ -224,8 +214,10 @@ int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf) int res = _SUCCESS; #ifdef CONFIG_USB_HCI +#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); struct usb_device *pusbd = pdvobjpriv->pusbdev; +#endif precvbuf->irp_pending = _FALSE; precvbuf->purb = usb_alloc_urb(0, GFP_KERNEL); @@ -290,7 +282,7 @@ int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf) } -_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 *pdata) +_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa, u8 *msdu ,u16 msdu_len) { u16 eth_type; u8 *data_ptr; @@ -300,19 +292,19 @@ _pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 pattrib = &prframe->u.hdr.attrib; #ifdef CONFIG_SKB_COPY - sub_skb = rtw_skb_alloc(nSubframe_Length + 12); + sub_skb = rtw_skb_alloc(msdu_len + 14); if (sub_skb) { - skb_reserve(sub_skb, 12); - data_ptr = (u8 *)skb_put(sub_skb, nSubframe_Length); - _rtw_memcpy(data_ptr, (pdata + ETH_HLEN), nSubframe_Length); + skb_reserve(sub_skb, 14); + data_ptr = (u8 *)skb_put(sub_skb, msdu_len); + _rtw_memcpy(data_ptr, msdu, msdu_len); } else #endif /* CONFIG_SKB_COPY */ { sub_skb = rtw_skb_clone(prframe->u.hdr.pkt); if (sub_skb) { - sub_skb->data = pdata + ETH_HLEN; - sub_skb->len = nSubframe_Length; - skb_set_tail_pointer(sub_skb, nSubframe_Length); + sub_skb->data = msdu; + sub_skb->len = msdu_len; + skb_set_tail_pointer(sub_skb, msdu_len); } else { RTW_INFO("%s(): rtw_skb_clone() Fail!!!\n", __FUNCTION__); return NULL; @@ -321,21 +313,23 @@ _pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 eth_type = RTW_GET_BE16(&sub_skb->data[6]); - if (sub_skb->len >= 8 && - ((_rtw_memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE) && - eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || - _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE))) { + if (sub_skb->len >= 8 + && ((_rtw_memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE) + && eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) + || _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE)) + ) { /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ skb_pull(sub_skb, SNAP_SIZE); - _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); - _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN); } else { - u16 len; /* Leave Ethernet header part of hdr and full payload */ + u16 len; + len = htons(sub_skb->len); _rtw_memcpy(skb_push(sub_skb, 2), &len, 2); - _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); - _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), sa, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), da, ETH_ALEN); } return sub_skb; @@ -391,20 +385,39 @@ int rtw_recv_napi_poll(struct napi_struct *napi, int budget) work_done = napi_recv(padapter, budget); if (work_done < budget) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_PCI_HCI) + napi_complete_done(napi, work_done); +#else napi_complete(napi); +#endif if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue)) napi_schedule(napi); } return work_done; } -#endif /* CONFIG_RTW_NAPI */ -#ifdef DBG_UDP_PKT_LOSE_11AC - #define PAYLOAD_LEN_LOC_OF_IP_HDR 0x10 /*ethernet payload length location of ip header (DA + SA+eth_type+(version&hdr_len)) */ -#endif +#ifdef CONFIG_RTW_NAPI_DYNAMIC +void dynamic_napi_th_chk (_adapter *adapter) +{ -void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attrib *pattrib) + if (adapter->registrypriv.en_napi) { + struct dvobj_priv *dvobj; + struct registry_priv *registry; + + dvobj = adapter_to_dvobj(adapter); + registry = &adapter->registrypriv; + if (dvobj->traffic_stat.cur_rx_tp > registry->napi_threshold) + dvobj->en_napi_dynamic = 1; + else + dvobj->en_napi_dynamic = 0; + } + +} +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ +#endif /* CONFIG_RTW_NAPI */ + +void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct recv_priv *precvpriv = &(padapter->recvpriv); @@ -416,22 +429,26 @@ void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attri /* Indicat the packets to upper layer */ if (pkt) { - if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + struct ethhdr *ehdr = (struct ethhdr *)pkt->data; + + DBG_COUNTER(padapter->rx_logs.os_indicate); + + if (MLME_IS_AP(padapter)) { _pkt *pskb2 = NULL; struct sta_info *psta = NULL; struct sta_priv *pstapriv = &padapter->stapriv; - int bmcast = IS_MCAST(pattrib->dst); + int bmcast = IS_MCAST(ehdr->h_dest); /* RTW_INFO("bmcast=%d\n", bmcast); */ - if (_rtw_memcmp(pattrib->dst, adapter_mac_addr(padapter), ETH_ALEN) == _FALSE) { - /* RTW_INFO("not ap psta=%p, addr=%pM\n", psta, pattrib->dst); */ + if (_rtw_memcmp(ehdr->h_dest, adapter_mac_addr(padapter), ETH_ALEN) == _FALSE) { + /* RTW_INFO("not ap psta=%p, addr=%pM\n", psta, ehdr->h_dest); */ if (bmcast) { psta = rtw_get_bcmc_stainfo(padapter); pskb2 = rtw_skb_clone(pkt); } else - psta = rtw_get_stainfo(pstapriv, pattrib->dst); + psta = rtw_get_stainfo(pstapriv, ehdr->h_dest); if (psta) { struct net_device *pnetdev = (struct net_device *)padapter->pnetdev; @@ -440,9 +457,9 @@ void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attri /* skb->ip_summed = CHECKSUM_NONE; */ pkt->dev = pnetdev; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) skb_set_queue_mapping(pkt, rtw_recv_select_queue(pkt)); -#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) */ + #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) */ _rtw_xmit_entry(pkt, pnetdev); @@ -461,69 +478,57 @@ void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attri } #ifdef CONFIG_BR_EXT - /* Insert NAT2.5 RX here! */ -#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) - br_port = padapter->pnetdev->br_port; -#else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ - rcu_read_lock(); - br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); - rcu_read_unlock(); -#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */ - - - if (br_port && (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) { - int nat25_handle_frame(_adapter *priv, struct sk_buff *skb); - if (nat25_handle_frame(padapter, pkt) == -1) { - /* priv->ext_stats.rx_data_drops++; */ - /* DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); */ - /* return FAIL; */ - -#if 1 - /* bypass this frame to upper layer!! */ -#else - rtw_skb_free(sub_skb); - continue; -#endif + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) { + /* Insert NAT2.5 RX here! */ + #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + br_port = padapter->pnetdev->br_port; + #else + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); + #endif + + if (br_port) { + int nat25_handle_frame(_adapter *priv, struct sk_buff *skb); + + if (nat25_handle_frame(padapter, pkt) == -1) { + /* priv->ext_stats.rx_data_drops++; */ + /* DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); */ + /* return FAIL; */ + + #if 1 + /* bypass this frame to upper layer!! */ + #else + rtw_skb_free(sub_skb); + continue; + #endif + } } } #endif /* CONFIG_BR_EXT */ - if (precvpriv->sink_udpport > 0) - rtw_sink_rtp_seq_dbg(padapter, pkt); -#ifdef DBG_UDP_PKT_LOSE_11AC - /* After eth_type_trans process , pkt->data pointer will move from ethrnet header to ip header , - * we have to check ethernet type , so this debug must be print before eth_type_trans - */ - if (*((unsigned short *)(pkt->data + ETH_ALEN * 2)) == htons(ETH_P_ARP)) { - /* ARP Payload length will be 42bytes or 42+18(tailer)=60bytes*/ - if (pkt->len != 42 && pkt->len != 60) - RTW_INFO("Error !!%s,ARP Payload length %u not correct\n" , __func__ , pkt->len); - } else if (*((unsigned short *)(pkt->data + ETH_ALEN * 2)) == htons(ETH_P_IP)) { - if (be16_to_cpu(*((u16 *)(pkt->data + PAYLOAD_LEN_LOC_OF_IP_HDR))) != (pkt->len) - ETH_HLEN) { - RTW_INFO("Error !!%s,Payload length not correct\n" , __func__); - RTW_INFO("%s, IP header describe Total length=%u\n" , __func__ , be16_to_cpu(*((u16 *)(pkt->data + PAYLOAD_LEN_LOC_OF_IP_HDR)))); - RTW_INFO("%s, Pkt real length=%u\n" , __func__ , (pkt->len) - ETH_HLEN); - } - } -#endif + /* After eth_type_trans process , pkt->data pointer will move from ethrnet header to ip header */ pkt->protocol = eth_type_trans(pkt, padapter->pnetdev); pkt->dev = padapter->pnetdev; - -#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX - if ((pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1)) - pkt->ip_summed = CHECKSUM_UNNECESSARY; - else - pkt->ip_summed = CHECKSUM_NONE; -#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */ - pkt->ip_summed = CHECKSUM_NONE; -#endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */ + pkt->ip_summed = CHECKSUM_NONE; /* CONFIG_TCP_CSUM_OFFLOAD_RX */ #ifdef CONFIG_RTW_NAPI - if (pregistrypriv->en_napi) { +#ifdef CONFIG_RTW_NAPI_DYNAMIC + if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue) + && !adapter_to_dvobj(padapter)->en_napi_dynamic + ) + napi_recv(padapter, RTL_NAPI_WEIGHT); +#endif + + if (pregistrypriv->en_napi + #ifdef CONFIG_RTW_NAPI_DYNAMIC + && adapter_to_dvobj(padapter)->en_napi_dynamic + #endif + ) { skb_queue_tail(&precvpriv->rx_napi_skb_queue, pkt); -#ifndef CONFIG_RTW_NAPI_V2 + #ifndef CONFIG_RTW_NAPI_V2 napi_schedule(&padapter->napi); -#endif /* !CONFIG_RTW_NAPI_V2 */ + #endif return; } #endif /* CONFIG_RTW_NAPI */ @@ -543,9 +548,8 @@ void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup #endif union iwreq_data wrqu; struct iw_michaelmicfailure ev; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct security_priv *psecuritypriv = &padapter->securitypriv; - u32 cur_time = 0; + systime cur_time = 0; if (psecuritypriv->last_mic_err_time == 0) psecuritypriv->last_mic_err_time = rtw_get_current_time(); @@ -566,7 +570,7 @@ void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup else key_type |= NL80211_KEYTYPE_PAIRWISE; - cfg80211_michael_mic_failure(padapter->pnetdev, sta->hwaddr, key_type, -1, NULL, GFP_ATOMIC); + cfg80211_michael_mic_failure(padapter->pnetdev, sta->cmn.mac_addr, key_type, -1, NULL, GFP_ATOMIC); #endif _rtw_memset(&ev, 0x00, sizeof(ev)); @@ -576,7 +580,7 @@ void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup ev.flags |= IW_MICFAILURE_PAIRWISE; ev.src_addr.sa_family = ARPHRD_ETHER; - _rtw_memcpy(ev.src_addr.sa_data, sta->hwaddr, ETH_ALEN); + _rtw_memcpy(ev.src_addr.sa_data, sta->cmn.mac_addr, ETH_ALEN); _rtw_memset(&wrqu, 0x00, sizeof(wrqu)); wrqu.data.length = sizeof(ev); @@ -586,9 +590,9 @@ void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup #endif } +#ifdef CONFIG_HOSTAPD_MLME void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame) { -#ifdef CONFIG_HOSTAPD_MLME _pkt *skb; struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; struct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev; @@ -623,52 +627,8 @@ void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame) rtw_netif_rx(pmgnt_netdev, skb); precv_frame->u.hdr.pkt = NULL; /* set pointer to NULL before rtw_free_recvframe() if call rtw_netif_rx() */ -#endif -} - -#ifdef CONFIG_AUTO_AP_MODE -static void rtw_os_ksocket_send(_adapter *padapter, union recv_frame *precv_frame) -{ - _pkt *skb = precv_frame->u.hdr.pkt; - struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; - struct sta_info *psta = precv_frame->u.hdr.psta; - - RTW_INFO("eth rx: got eth_type=0x%x\n", pattrib->eth_type); - - if (psta && psta->isrc && psta->pid > 0) { - u16 rx_pid; - - rx_pid = *(u16 *)(skb->data + ETH_HLEN); - - RTW_INFO("eth rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n", - rx_pid, MAC_ARG(psta->hwaddr), psta->pid); - - if (rx_pid == psta->pid) { - int i; - u16 len = *(u16 *)(skb->data + ETH_HLEN + 2); - /* u16 ctrl_type = *(u16*)(skb->data+ETH_HLEN+4); */ - - /* RTW_INFO("eth, RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); */ - RTW_INFO("eth, RC: len=0x%x\n", len); - - for (i = 0; i < len; i++) - RTW_INFO("0x%x\n", *(skb->data + ETH_HLEN + 4 + i)); - /* RTW_INFO("0x%x\n", *(skb->data+ETH_HLEN+6+i)); */ - - RTW_INFO("eth, RC-end\n"); - -#if 0 - /* send_sz = ksocket_send(padapter->ksock_send, &padapter->kaddr_send, (skb->data+ETH_HLEN+2), len); */ - rtw_recv_ksocket_send_cmd(padapter, (skb->data + ETH_HLEN + 2), len); - - /* RTW_INFO("ksocket_send size=%d\n", send_sz); */ -#endif - } - - } - } -#endif /* CONFIG_AUTO_AP_MODE */ +#endif /* CONFIG_HOSTAPD_MLME */ int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame) { @@ -676,7 +636,6 @@ int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame) struct recv_priv *precvpriv; _queue *pfree_recv_queue; _pkt *skb; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct rx_pkt_attrib *pattrib; if (NULL == precv_frame) @@ -716,136 +675,37 @@ int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame) } +inline void rtw_rframe_set_os_pkt(union recv_frame *rframe) +{ + _pkt *skb = rframe->u.hdr.pkt; + + skb->data = rframe->u.hdr.rx_data; + skb_set_tail_pointer(skb, rframe->u.hdr.len); + skb->len = rframe->u.hdr.len; +} + int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame) { struct recv_priv *precvpriv; _queue *pfree_recv_queue; - _pkt *skb; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct rx_pkt_attrib *pattrib; - - if (NULL == precv_frame) - goto _recv_indicatepkt_drop; - DBG_COUNTER(padapter->rx_logs.os_indicate); - pattrib = &precv_frame->u.hdr.attrib; precvpriv = &(padapter->recvpriv); pfree_recv_queue = &(precvpriv->free_recv_queue); -#ifdef CONFIG_DRVEXT_MODULE - if (drvext_rx_handler(padapter, precv_frame->u.hdr.rx_data, precv_frame->u.hdr.len) == _SUCCESS) - goto _recv_indicatepkt_drop; -#endif - -#ifdef CONFIG_WAPI_SUPPORT - if (rtw_wapi_check_for_drop(padapter, precv_frame)) { - WAPI_TRACE(WAPI_ERR, "%s(): Rx Reorder Drop case!!\n", __FUNCTION__); - goto _recv_indicatepkt_drop; - } -#endif - - skb = precv_frame->u.hdr.pkt; - if (skb == NULL) { + if (precv_frame->u.hdr.pkt == NULL) goto _recv_indicatepkt_drop; - } - - - skb->data = precv_frame->u.hdr.rx_data; - - skb_set_tail_pointer(skb, precv_frame->u.hdr.len); - - skb->len = precv_frame->u.hdr.len; - - - if (pattrib->eth_type == 0x888e) - RTW_PRINT("recv eapol packet\n"); - -#ifdef CONFIG_AUTO_AP_MODE -#if 1 /* for testing */ -#if 1 - if (0x8899 == pattrib->eth_type) { - rtw_os_ksocket_send(padapter, precv_frame); - /* goto _recv_indicatepkt_drop; */ - } -#else - if (0x8899 == pattrib->eth_type) { - rtw_auto_ap_mode_rx(padapter, precv_frame); - - goto _recv_indicatepkt_end; - } -#endif -#endif -#endif /* CONFIG_AUTO_AP_MODE */ - - /* TODO: move to core */ - { - _pkt *pkt = skb; - struct ethhdr *etherhdr = (struct ethhdr *)pkt->data; - struct sta_info *sta = precv_frame->u.hdr.psta; - - if (!sta) - goto bypass_session_tracker; - - if (ntohs(etherhdr->h_proto) == ETH_P_IP) { - u8 *ip = pkt->data + 14; - - if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */ - && rtw_st_ctl_chk_reg_s_proto(&sta->st_ctl, 0x06) == _TRUE - ) { - u8 *tcp = ip + GET_IPV4_IHL(ip) * 4; - - if (rtw_st_ctl_chk_reg_rule(&sta->st_ctl, padapter, IPV4_DST(ip), TCP_DST(tcp), IPV4_SRC(ip), TCP_SRC(tcp)) == _TRUE) { - if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) { - session_tracker_add_cmd(padapter, sta - , IPV4_DST(ip), TCP_DST(tcp) - , IPV4_SRC(ip), TCP_SRC(tcp)); - if (DBG_SESSION_TRACKER) - RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n" - , FUNC_ADPT_ARG(padapter) - , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) - , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); - } - if (GET_TCP_FIN(tcp)) { - session_tracker_del_cmd(padapter, sta - , IPV4_DST(ip), TCP_DST(tcp) - , IPV4_SRC(ip), TCP_SRC(tcp)); - if (DBG_SESSION_TRACKER) - RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n" - , FUNC_ADPT_ARG(padapter) - , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) - , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); - } - } - - } - } -bypass_session_tracker: - ; - } - - rtw_os_recv_indicate_pkt(padapter, skb, pattrib); + rtw_os_recv_indicate_pkt(padapter, precv_frame->u.hdr.pkt, precv_frame); _recv_indicatepkt_end: - - precv_frame->u.hdr.pkt = NULL; /* pointers to NULL before rtw_free_recvframe() */ - + precv_frame->u.hdr.pkt = NULL; rtw_free_recvframe(precv_frame, pfree_recv_queue); - - - return _SUCCESS; _recv_indicatepkt_drop: - - /* enqueue back to free_recv_queue */ - if (precv_frame) - rtw_free_recvframe(precv_frame, pfree_recv_queue); - + rtw_free_recvframe(precv_frame, pfree_recv_queue); DBG_COUNTER(padapter->rx_logs.os_indicate_err); - return _FAIL; - } void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf) diff --git a/os_dep/linux/rhashtable.c b/os_dep/linux/rhashtable.c new file mode 100644 index 0000000..0163a4b --- /dev/null +++ b/os_dep/linux/rhashtable.c @@ -0,0 +1,844 @@ +/* + * Resizable, Scalable, Concurrent Hash Table + * + * Copyright (c) 2015 Herbert Xu + * Copyright (c) 2014-2015 Thomas Graf + * Copyright (c) 2008-2014 Patrick McHardy + * + * Code partially derived from nft_hash + * Rewritten with rehash code from br_multicast plus single list + * pointer as suggested by Josh Triplett + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HASH_DEFAULT_SIZE 64UL +#define HASH_MIN_SIZE 4U +#define BUCKET_LOCKS_PER_CPU 128UL + +static u32 head_hashfn(struct rhashtable *ht, + const struct bucket_table *tbl, + const struct rhash_head *he) +{ + return rht_head_hashfn(ht, tbl, he, ht->p); +} + +#ifdef CONFIG_PROVE_LOCKING +#define ASSERT_RHT_MUTEX(HT) BUG_ON(!lockdep_rht_mutex_is_held(HT)) + +int lockdep_rht_mutex_is_held(struct rhashtable *ht) +{ + return (debug_locks) ? lockdep_is_held(&ht->mutex) : 1; +} + +int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash) +{ + spinlock_t *lock = rht_bucket_lock(tbl, hash); + + return (debug_locks) ? lockdep_is_held(lock) : 1; +} +#else +#define ASSERT_RHT_MUTEX(HT) +#endif + + +static int alloc_bucket_locks(struct rhashtable *ht, struct bucket_table *tbl, + gfp_t gfp) +{ + unsigned int i, size; +#if defined(CONFIG_PROVE_LOCKING) + unsigned int nr_pcpus = 2; +#else + unsigned int nr_pcpus = num_possible_cpus(); +#endif + + nr_pcpus = min_t(unsigned int, nr_pcpus, 32UL); + size = roundup_pow_of_two(nr_pcpus * ht->p.locks_mul); + + /* Never allocate more than 0.5 locks per bucket */ + size = min_t(unsigned int, size, tbl->size >> 1); + + if (sizeof(spinlock_t) != 0) { +#ifdef CONFIG_NUMA + if (size * sizeof(spinlock_t) > PAGE_SIZE && + gfp == GFP_KERNEL) + tbl->locks = vmalloc(size * sizeof(spinlock_t)); + else +#endif + tbl->locks = kmalloc_array(size, sizeof(spinlock_t), + gfp); + if (!tbl->locks) + return -ENOMEM; + for (i = 0; i < size; i++) + spin_lock_init(&tbl->locks[i]); + } + tbl->locks_mask = size - 1; + + return 0; +} + +static void bucket_table_free(const struct bucket_table *tbl) +{ + if (tbl) + kvfree(tbl->locks); + + kvfree(tbl); +} + +static void bucket_table_free_rcu(struct rcu_head *head) +{ + bucket_table_free(container_of(head, struct bucket_table, rcu)); +} + +static struct bucket_table *bucket_table_alloc(struct rhashtable *ht, + size_t nbuckets, + gfp_t gfp) +{ + struct bucket_table *tbl = NULL; + size_t size; + int i; + + size = sizeof(*tbl) + nbuckets * sizeof(tbl->buckets[0]); + if (size <= (PAGE_SIZE << PAGE_ALLOC_COSTLY_ORDER) || + gfp != GFP_KERNEL) + tbl = kzalloc(size, gfp | __GFP_NOWARN | __GFP_NORETRY); + if (tbl == NULL && gfp == GFP_KERNEL) + tbl = vzalloc(size); + if (tbl == NULL) + return NULL; + + tbl->size = nbuckets; + + if (alloc_bucket_locks(ht, tbl, gfp) < 0) { + bucket_table_free(tbl); + return NULL; + } + + INIT_LIST_HEAD(&tbl->walkers); + + get_random_bytes(&tbl->hash_rnd, sizeof(tbl->hash_rnd)); + + for (i = 0; i < nbuckets; i++) + INIT_RHT_NULLS_HEAD(tbl->buckets[i], ht, i); + + return tbl; +} + +static struct bucket_table *rhashtable_last_table(struct rhashtable *ht, + struct bucket_table *tbl) +{ + struct bucket_table *new_tbl; + + do { + new_tbl = tbl; + tbl = rht_dereference_rcu(tbl->future_tbl, ht); + } while (tbl); + + return new_tbl; +} + +static int rhashtable_rehash_one(struct rhashtable *ht, unsigned int old_hash) +{ + struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht); + struct bucket_table *new_tbl = rhashtable_last_table(ht, + rht_dereference_rcu(old_tbl->future_tbl, ht)); + struct rhash_head __rcu **pprev = &old_tbl->buckets[old_hash]; + int err = -ENOENT; + struct rhash_head *head, *next, *entry; + spinlock_t *new_bucket_lock; + unsigned int new_hash; + + rht_for_each(entry, old_tbl, old_hash) { + err = 0; + next = rht_dereference_bucket(entry->next, old_tbl, old_hash); + + if (rht_is_a_nulls(next)) + break; + + pprev = &entry->next; + } + + if (err) + goto out; + + new_hash = head_hashfn(ht, new_tbl, entry); + + new_bucket_lock = rht_bucket_lock(new_tbl, new_hash); + + spin_lock_nested(new_bucket_lock, SINGLE_DEPTH_NESTING); + head = rht_dereference_bucket(new_tbl->buckets[new_hash], + new_tbl, new_hash); + + RCU_INIT_POINTER(entry->next, head); + + rcu_assign_pointer(new_tbl->buckets[new_hash], entry); + spin_unlock(new_bucket_lock); + + rcu_assign_pointer(*pprev, next); + +out: + return err; +} + +static void rhashtable_rehash_chain(struct rhashtable *ht, + unsigned int old_hash) +{ + struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht); + spinlock_t *old_bucket_lock; + + old_bucket_lock = rht_bucket_lock(old_tbl, old_hash); + + spin_lock_bh(old_bucket_lock); + while (!rhashtable_rehash_one(ht, old_hash)) + ; + old_tbl->rehash++; + spin_unlock_bh(old_bucket_lock); +} + +static int rhashtable_rehash_attach(struct rhashtable *ht, + struct bucket_table *old_tbl, + struct bucket_table *new_tbl) +{ + /* Protect future_tbl using the first bucket lock. */ + spin_lock_bh(old_tbl->locks); + + /* Did somebody beat us to it? */ + if (rcu_access_pointer(old_tbl->future_tbl)) { + spin_unlock_bh(old_tbl->locks); + return -EEXIST; + } + + /* Make insertions go into the new, empty table right away. Deletions + * and lookups will be attempted in both tables until we synchronize. + */ + rcu_assign_pointer(old_tbl->future_tbl, new_tbl); + + /* Ensure the new table is visible to readers. */ + smp_wmb(); + + spin_unlock_bh(old_tbl->locks); + + return 0; +} + +static int rhashtable_rehash_table(struct rhashtable *ht) +{ + struct bucket_table *old_tbl = rht_dereference(ht->tbl, ht); + struct bucket_table *new_tbl; + struct rhashtable_walker *walker; + unsigned int old_hash; + + new_tbl = rht_dereference(old_tbl->future_tbl, ht); + if (!new_tbl) + return 0; + + for (old_hash = 0; old_hash < old_tbl->size; old_hash++) + rhashtable_rehash_chain(ht, old_hash); + + /* Publish the new table pointer. */ + rcu_assign_pointer(ht->tbl, new_tbl); + + spin_lock(&ht->lock); + list_for_each_entry(walker, &old_tbl->walkers, list) + walker->tbl = NULL; + spin_unlock(&ht->lock); + + /* Wait for readers. All new readers will see the new + * table, and thus no references to the old table will + * remain. + */ + call_rcu(&old_tbl->rcu, bucket_table_free_rcu); + + return rht_dereference(new_tbl->future_tbl, ht) ? -EAGAIN : 0; +} + +/** + * rhashtable_expand - Expand hash table while allowing concurrent lookups + * @ht: the hash table to expand + * + * A secondary bucket array is allocated and the hash entries are migrated. + * + * This function may only be called in a context where it is safe to call + * synchronize_rcu(), e.g. not within a rcu_read_lock() section. + * + * The caller must ensure that no concurrent resizing occurs by holding + * ht->mutex. + * + * It is valid to have concurrent insertions and deletions protected by per + * bucket locks or concurrent RCU protected lookups and traversals. + */ +static int rhashtable_expand(struct rhashtable *ht) +{ + struct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht); + int err; + + ASSERT_RHT_MUTEX(ht); + + old_tbl = rhashtable_last_table(ht, old_tbl); + + new_tbl = bucket_table_alloc(ht, old_tbl->size * 2, GFP_KERNEL); + if (new_tbl == NULL) + return -ENOMEM; + + err = rhashtable_rehash_attach(ht, old_tbl, new_tbl); + if (err) + bucket_table_free(new_tbl); + + return err; +} + +/** + * rhashtable_shrink - Shrink hash table while allowing concurrent lookups + * @ht: the hash table to shrink + * + * This function shrinks the hash table to fit, i.e., the smallest + * size would not cause it to expand right away automatically. + * + * The caller must ensure that no concurrent resizing occurs by holding + * ht->mutex. + * + * The caller must ensure that no concurrent table mutations take place. + * It is however valid to have concurrent lookups if they are RCU protected. + * + * It is valid to have concurrent insertions and deletions protected by per + * bucket locks or concurrent RCU protected lookups and traversals. + */ +static int rhashtable_shrink(struct rhashtable *ht) +{ + struct bucket_table *new_tbl, *old_tbl = rht_dereference(ht->tbl, ht); + unsigned int size; + int err; + + ASSERT_RHT_MUTEX(ht); + + size = roundup_pow_of_two(atomic_read(&ht->nelems) * 3 / 2); + if (size < ht->p.min_size) + size = ht->p.min_size; + + if (old_tbl->size <= size) + return 0; + + if (rht_dereference(old_tbl->future_tbl, ht)) + return -EEXIST; + + new_tbl = bucket_table_alloc(ht, size, GFP_KERNEL); + if (new_tbl == NULL) + return -ENOMEM; + + err = rhashtable_rehash_attach(ht, old_tbl, new_tbl); + if (err) + bucket_table_free(new_tbl); + + return err; +} + +static void rht_deferred_worker(struct work_struct *work) +{ + struct rhashtable *ht; + struct bucket_table *tbl; + int err = 0; + + ht = container_of(work, struct rhashtable, run_work); + mutex_lock(&ht->mutex); + + tbl = rht_dereference(ht->tbl, ht); + tbl = rhashtable_last_table(ht, tbl); + + if (rht_grow_above_75(ht, tbl)) + rhashtable_expand(ht); + else if (ht->p.automatic_shrinking && rht_shrink_below_30(ht, tbl)) + rhashtable_shrink(ht); + + err = rhashtable_rehash_table(ht); + + mutex_unlock(&ht->mutex); + + if (err) + schedule_work(&ht->run_work); +} + +static bool rhashtable_check_elasticity(struct rhashtable *ht, + struct bucket_table *tbl, + unsigned int hash) +{ + unsigned int elasticity = ht->elasticity; + struct rhash_head *head; + + rht_for_each(head, tbl, hash) + if (!--elasticity) + return true; + + return false; +} + +int rhashtable_insert_rehash(struct rhashtable *ht, + struct bucket_table *tbl) +{ + struct bucket_table *old_tbl; + struct bucket_table *new_tbl; + unsigned int size; + int err; + + old_tbl = rht_dereference_rcu(ht->tbl, ht); + + size = tbl->size; + + err = -EBUSY; + + if (rht_grow_above_75(ht, tbl)) + size *= 2; + /* Do not schedule more than one rehash */ + else if (old_tbl != tbl) + goto fail; + + err = -ENOMEM; + + new_tbl = bucket_table_alloc(ht, size, GFP_ATOMIC); + if (new_tbl == NULL) + goto fail; + + err = rhashtable_rehash_attach(ht, tbl, new_tbl); + if (err) { + bucket_table_free(new_tbl); + if (err == -EEXIST) + err = 0; + } else + schedule_work(&ht->run_work); + + return err; + +fail: + /* Do not fail the insert if someone else did a rehash. */ + if (likely(rcu_dereference_raw(tbl->future_tbl))) + return 0; + + /* Schedule async rehash to retry allocation in process context. */ + if (err == -ENOMEM) + schedule_work(&ht->run_work); + + return err; +} + +struct bucket_table *rhashtable_insert_slow(struct rhashtable *ht, + const void *key, + struct rhash_head *obj, + struct bucket_table *tbl) +{ + struct rhash_head *head; + unsigned int hash; + int err; + + tbl = rhashtable_last_table(ht, tbl); + hash = head_hashfn(ht, tbl, obj); + spin_lock_nested(rht_bucket_lock(tbl, hash), SINGLE_DEPTH_NESTING); + + err = -EEXIST; + if (key && rhashtable_lookup_fast(ht, key, ht->p)) + goto exit; + + err = -E2BIG; + if (unlikely(rht_grow_above_max(ht, tbl))) + goto exit; + + err = -EAGAIN; + if (rhashtable_check_elasticity(ht, tbl, hash) || + rht_grow_above_100(ht, tbl)) + goto exit; + + err = 0; + + head = rht_dereference_bucket(tbl->buckets[hash], tbl, hash); + + RCU_INIT_POINTER(obj->next, head); + + rcu_assign_pointer(tbl->buckets[hash], obj); + + atomic_inc(&ht->nelems); + +exit: + spin_unlock(rht_bucket_lock(tbl, hash)); + + if (err == 0) + return NULL; + else if (err == -EAGAIN) + return tbl; + else + return ERR_PTR(err); +} + +/** + * rhashtable_walk_init - Initialise an iterator + * @ht: Table to walk over + * @iter: Hash table Iterator + * + * This function prepares a hash table walk. + * + * Note that if you restart a walk after rhashtable_walk_stop you + * may see the same object twice. Also, you may miss objects if + * there are removals in between rhashtable_walk_stop and the next + * call to rhashtable_walk_start. + * + * For a completely stable walk you should construct your own data + * structure outside the hash table. + * + * This function may sleep so you must not call it from interrupt + * context or with spin locks held. + * + * You must call rhashtable_walk_exit if this function returns + * successfully. + */ +int rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter) +{ + iter->ht = ht; + iter->p = NULL; + iter->slot = 0; + iter->skip = 0; + + iter->walker = kmalloc(sizeof(*iter->walker), GFP_KERNEL); + if (!iter->walker) + return -ENOMEM; + + spin_lock(&ht->lock); + iter->walker->tbl = + rcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock)); + list_add(&iter->walker->list, &iter->walker->tbl->walkers); + spin_unlock(&ht->lock); + + return 0; +} + +/** + * rhashtable_walk_exit - Free an iterator + * @iter: Hash table Iterator + * + * This function frees resources allocated by rhashtable_walk_init. + */ +void rhashtable_walk_exit(struct rhashtable_iter *iter) +{ + spin_lock(&iter->ht->lock); + if (iter->walker->tbl) + list_del(&iter->walker->list); + spin_unlock(&iter->ht->lock); + kfree(iter->walker); +} + +/** + * rhashtable_walk_start - Start a hash table walk + * @iter: Hash table iterator + * + * Start a hash table walk. Note that we take the RCU lock in all + * cases including when we return an error. So you must always call + * rhashtable_walk_stop to clean up. + * + * Returns zero if successful. + * + * Returns -EAGAIN if resize event occured. Note that the iterator + * will rewind back to the beginning and you may use it immediately + * by calling rhashtable_walk_next. + */ +int rhashtable_walk_start(struct rhashtable_iter *iter) + __acquires(RCU) +{ + struct rhashtable *ht = iter->ht; + + rcu_read_lock(); + + spin_lock(&ht->lock); + if (iter->walker->tbl) + list_del(&iter->walker->list); + spin_unlock(&ht->lock); + + if (!iter->walker->tbl) { + iter->walker->tbl = rht_dereference_rcu(ht->tbl, ht); + return -EAGAIN; + } + + return 0; +} + +/** + * rhashtable_walk_next - Return the next object and advance the iterator + * @iter: Hash table iterator + * + * Note that you must call rhashtable_walk_stop when you are finished + * with the walk. + * + * Returns the next object or NULL when the end of the table is reached. + * + * Returns -EAGAIN if resize event occured. Note that the iterator + * will rewind back to the beginning and you may continue to use it. + */ +void *rhashtable_walk_next(struct rhashtable_iter *iter) +{ + struct bucket_table *tbl = iter->walker->tbl; + struct rhashtable *ht = iter->ht; + struct rhash_head *p = iter->p; + + if (p) { + p = rht_dereference_bucket_rcu(p->next, tbl, iter->slot); + goto next; + } + + for (; iter->slot < tbl->size; iter->slot++) { + int skip = iter->skip; + + rht_for_each_rcu(p, tbl, iter->slot) { + if (!skip) + break; + skip--; + } + +next: + if (!rht_is_a_nulls(p)) { + iter->skip++; + iter->p = p; + return rht_obj(ht, p); + } + + iter->skip = 0; + } + + iter->p = NULL; + + /* Ensure we see any new tables. */ + smp_rmb(); + + iter->walker->tbl = rht_dereference_rcu(tbl->future_tbl, ht); + if (iter->walker->tbl) { + iter->slot = 0; + iter->skip = 0; + return ERR_PTR(-EAGAIN); + } + + return NULL; +} + +/** + * rhashtable_walk_stop - Finish a hash table walk + * @iter: Hash table iterator + * + * Finish a hash table walk. + */ +void rhashtable_walk_stop(struct rhashtable_iter *iter) + __releases(RCU) +{ + struct rhashtable *ht; + struct bucket_table *tbl = iter->walker->tbl; + + if (!tbl) + goto out; + + ht = iter->ht; + + spin_lock(&ht->lock); + if (tbl->rehash < tbl->size) + list_add(&iter->walker->list, &tbl->walkers); + else + iter->walker->tbl = NULL; + spin_unlock(&ht->lock); + + iter->p = NULL; + +out: + rcu_read_unlock(); +} + +static size_t rounded_hashtable_size(const struct rhashtable_params *params) +{ + return max(roundup_pow_of_two(params->nelem_hint * 4 / 3), + (unsigned long)params->min_size); +} + +static u32 rhashtable_jhash2(const void *key, u32 length, u32 seed) +{ + return jhash2(key, length, seed); +} + +/** + * rhashtable_init - initialize a new hash table + * @ht: hash table to be initialized + * @params: configuration parameters + * + * Initializes a new hash table based on the provided configuration + * parameters. A table can be configured either with a variable or + * fixed length key: + * + * Configuration Example 1: Fixed length keys + * struct test_obj { + * int key; + * void * my_member; + * struct rhash_head node; + * }; + * + * struct rhashtable_params params = { + * .head_offset = offsetof(struct test_obj, node), + * .key_offset = offsetof(struct test_obj, key), + * .key_len = sizeof(int), + * .hashfn = jhash, + * .nulls_base = (1U << RHT_BASE_SHIFT), + * }; + * + * Configuration Example 2: Variable length keys + * struct test_obj { + * [...] + * struct rhash_head node; + * }; + * + * u32 my_hash_fn(const void *data, u32 len, u32 seed) + * { + * struct test_obj *obj = data; + * + * return [... hash ...]; + * } + * + * struct rhashtable_params params = { + * .head_offset = offsetof(struct test_obj, node), + * .hashfn = jhash, + * .obj_hashfn = my_hash_fn, + * }; + */ +int rhashtable_init(struct rhashtable *ht, + const struct rhashtable_params *params) +{ + struct bucket_table *tbl; + size_t size; + + size = HASH_DEFAULT_SIZE; + + if ((!params->key_len && !params->obj_hashfn) || + (params->obj_hashfn && !params->obj_cmpfn)) + return -EINVAL; + + if (params->nulls_base && params->nulls_base < (1U << RHT_BASE_SHIFT)) + return -EINVAL; + + memset(ht, 0, sizeof(*ht)); + mutex_init(&ht->mutex); + spin_lock_init(&ht->lock); + memcpy(&ht->p, params, sizeof(*params)); + + if (params->min_size) + ht->p.min_size = roundup_pow_of_two(params->min_size); + + if (params->max_size) + ht->p.max_size = rounddown_pow_of_two(params->max_size); + + if (params->insecure_max_entries) + ht->p.insecure_max_entries = + rounddown_pow_of_two(params->insecure_max_entries); + else + ht->p.insecure_max_entries = ht->p.max_size * 2; + + ht->p.min_size = max(ht->p.min_size, HASH_MIN_SIZE); + + if (params->nelem_hint) + size = rounded_hashtable_size(&ht->p); + + /* The maximum (not average) chain length grows with the + * size of the hash table, at a rate of (log N)/(log log N). + * The value of 16 is selected so that even if the hash + * table grew to 2^32 you would not expect the maximum + * chain length to exceed it unless we are under attack + * (or extremely unlucky). + * + * As this limit is only to detect attacks, we don't need + * to set it to a lower value as you'd need the chain + * length to vastly exceed 16 to have any real effect + * on the system. + */ + if (!params->insecure_elasticity) + ht->elasticity = 16; + + if (params->locks_mul) + ht->p.locks_mul = roundup_pow_of_two(params->locks_mul); + else + ht->p.locks_mul = BUCKET_LOCKS_PER_CPU; + + ht->key_len = ht->p.key_len; + if (!params->hashfn) { + ht->p.hashfn = jhash; + + if (!(ht->key_len & (sizeof(u32) - 1))) { + ht->key_len /= sizeof(u32); + ht->p.hashfn = rhashtable_jhash2; + } + } + + tbl = bucket_table_alloc(ht, size, GFP_KERNEL); + if (tbl == NULL) + return -ENOMEM; + + atomic_set(&ht->nelems, 0); + + RCU_INIT_POINTER(ht->tbl, tbl); + + INIT_WORK(&ht->run_work, rht_deferred_worker); + + return 0; +} + +/** + * rhashtable_free_and_destroy - free elements and destroy hash table + * @ht: the hash table to destroy + * @free_fn: callback to release resources of element + * @arg: pointer passed to free_fn + * + * Stops an eventual async resize. If defined, invokes free_fn for each + * element to releasal resources. Please note that RCU protected + * readers may still be accessing the elements. Releasing of resources + * must occur in a compatible manner. Then frees the bucket array. + * + * This function will eventually sleep to wait for an async resize + * to complete. The caller is responsible that no further write operations + * occurs in parallel. + */ +void rhashtable_free_and_destroy(struct rhashtable *ht, + void (*free_fn)(void *ptr, void *arg), + void *arg) +{ + const struct bucket_table *tbl; + unsigned int i; + + cancel_work_sync(&ht->run_work); + + mutex_lock(&ht->mutex); + tbl = rht_dereference(ht->tbl, ht); + if (free_fn) { + for (i = 0; i < tbl->size; i++) { + struct rhash_head *pos, *next; + + for (pos = rht_dereference(tbl->buckets[i], ht), + next = !rht_is_a_nulls(pos) ? + rht_dereference(pos->next, ht) : NULL; + !rht_is_a_nulls(pos); + pos = next, + next = !rht_is_a_nulls(pos) ? + rht_dereference(pos->next, ht) : NULL) + free_fn(rht_obj(ht, pos), arg); + } + } + + bucket_table_free(tbl); + mutex_unlock(&ht->mutex); +} + +void rhashtable_destroy(struct rhashtable *ht) +{ + return rhashtable_free_and_destroy(ht, NULL, NULL); +} + diff --git a/os_dep/linux/rhashtable.h b/os_dep/linux/rhashtable.h new file mode 100644 index 0000000..b47107f --- /dev/null +++ b/os_dep/linux/rhashtable.h @@ -0,0 +1,827 @@ +/* + * Resizable, Scalable, Concurrent Hash Table + * + * Copyright (c) 2015 Herbert Xu + * Copyright (c) 2014-2015 Thomas Graf + * Copyright (c) 2008-2014 Patrick McHardy + * + * Code partially derived from nft_hash + * Rewritten with rehash code from br_multicast plus single list + * pointer as suggested by Josh Triplett + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LINUX_RHASHTABLE_H +#define _LINUX_RHASHTABLE_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The end of the chain is marked with a special nulls marks which has + * the following format: + * + * +-------+-----------------------------------------------------+-+ + * | Base | Hash |1| + * +-------+-----------------------------------------------------+-+ + * + * Base (4 bits) : Reserved to distinguish between multiple tables. + * Specified via &struct rhashtable_params.nulls_base. + * Hash (27 bits): Full hash (unmasked) of first element added to bucket + * 1 (1 bit) : Nulls marker (always set) + * + * The remaining bits of the next pointer remain unused for now. + */ +#define RHT_BASE_BITS 4 +#define RHT_HASH_BITS 27 +#define RHT_BASE_SHIFT RHT_HASH_BITS + +/* Base bits plus 1 bit for nulls marker */ +#define RHT_HASH_RESERVED_SPACE (RHT_BASE_BITS + 1) + +struct rhash_head { + struct rhash_head __rcu *next; +}; + +/** + * struct bucket_table - Table of hash buckets + * @size: Number of hash buckets + * @rehash: Current bucket being rehashed + * @hash_rnd: Random seed to fold into hash + * @locks_mask: Mask to apply before accessing locks[] + * @locks: Array of spinlocks protecting individual buckets + * @walkers: List of active walkers + * @rcu: RCU structure for freeing the table + * @future_tbl: Table under construction during rehashing + * @buckets: size * hash buckets + */ +struct bucket_table { + unsigned int size; + unsigned int rehash; + u32 hash_rnd; + unsigned int locks_mask; + spinlock_t *locks; + struct list_head walkers; + struct rcu_head rcu; + + struct bucket_table __rcu *future_tbl; + + struct rhash_head __rcu *buckets[] ____cacheline_aligned_in_smp; +}; + +/** + * struct rhashtable_compare_arg - Key for the function rhashtable_compare + * @ht: Hash table + * @key: Key to compare against + */ +struct rhashtable_compare_arg { + struct rhashtable *ht; + const void *key; +}; + +typedef u32 (*rht_hashfn_t)(const void *data, u32 len, u32 seed); +typedef u32 (*rht_obj_hashfn_t)(const void *data, u32 len, u32 seed); +typedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *arg, + const void *obj); + +struct rhashtable; + +/** + * struct rhashtable_params - Hash table construction parameters + * @nelem_hint: Hint on number of elements, should be 75% of desired size + * @key_len: Length of key + * @key_offset: Offset of key in struct to be hashed + * @head_offset: Offset of rhash_head in struct to be hashed + * @insecure_max_entries: Maximum number of entries (may be exceeded) + * @max_size: Maximum size while expanding + * @min_size: Minimum size while shrinking + * @nulls_base: Base value to generate nulls marker + * @insecure_elasticity: Set to true to disable chain length checks + * @automatic_shrinking: Enable automatic shrinking of tables + * @locks_mul: Number of bucket locks to allocate per cpu (default: 128) + * @hashfn: Hash function (default: jhash2 if !(key_len % 4), or jhash) + * @obj_hashfn: Function to hash object + * @obj_cmpfn: Function to compare key with object + */ +struct rhashtable_params { + size_t nelem_hint; + size_t key_len; + size_t key_offset; + size_t head_offset; + unsigned int insecure_max_entries; + unsigned int max_size; + unsigned int min_size; + u32 nulls_base; + bool insecure_elasticity; + bool automatic_shrinking; + size_t locks_mul; + rht_hashfn_t hashfn; + rht_obj_hashfn_t obj_hashfn; + rht_obj_cmpfn_t obj_cmpfn; +}; + +/** + * struct rhashtable - Hash table handle + * @tbl: Bucket table + * @nelems: Number of elements in table + * @key_len: Key length for hashfn + * @elasticity: Maximum chain length before rehash + * @p: Configuration parameters + * @run_work: Deferred worker to expand/shrink asynchronously + * @mutex: Mutex to protect current/future table swapping + * @lock: Spin lock to protect walker list + */ +struct rhashtable { + struct bucket_table __rcu *tbl; + atomic_t nelems; + unsigned int key_len; + unsigned int elasticity; + struct rhashtable_params p; + struct work_struct run_work; + struct mutex mutex; + spinlock_t lock; +}; + +/** + * struct rhashtable_walker - Hash table walker + * @list: List entry on list of walkers + * @tbl: The table that we were walking over + */ +struct rhashtable_walker { + struct list_head list; + struct bucket_table *tbl; +}; + +/** + * struct rhashtable_iter - Hash table iterator, fits into netlink cb + * @ht: Table to iterate through + * @p: Current pointer + * @walker: Associated rhashtable walker + * @slot: Current slot + * @skip: Number of entries to skip in slot + */ +struct rhashtable_iter { + struct rhashtable *ht; + struct rhash_head *p; + struct rhashtable_walker *walker; + unsigned int slot; + unsigned int skip; +}; + +static inline unsigned long rht_marker(const struct rhashtable *ht, u32 hash) +{ + return NULLS_MARKER(ht->p.nulls_base + hash); +} + +#define INIT_RHT_NULLS_HEAD(ptr, ht, hash) \ + ((ptr) = (typeof(ptr)) rht_marker(ht, hash)) + +static inline bool rht_is_a_nulls(const struct rhash_head *ptr) +{ + return ((unsigned long) ptr & 1); +} + +static inline unsigned long rht_get_nulls_value(const struct rhash_head *ptr) +{ + return ((unsigned long) ptr) >> 1; +} + +static inline void *rht_obj(const struct rhashtable *ht, + const struct rhash_head *he) +{ + return (char *)he - ht->p.head_offset; +} + +static inline unsigned int rht_bucket_index(const struct bucket_table *tbl, + unsigned int hash) +{ + return (hash >> RHT_HASH_RESERVED_SPACE) & (tbl->size - 1); +} + +static inline unsigned int rht_key_hashfn( + struct rhashtable *ht, const struct bucket_table *tbl, + const void *key, const struct rhashtable_params params) +{ + unsigned int hash; + + /* params must be equal to ht->p if it isn't constant. */ + if (!__builtin_constant_p(params.key_len)) + hash = ht->p.hashfn(key, ht->key_len, tbl->hash_rnd); + else if (params.key_len) { + unsigned int key_len = params.key_len; + + if (params.hashfn) + hash = params.hashfn(key, key_len, tbl->hash_rnd); + else if (key_len & (sizeof(u32) - 1)) + hash = jhash(key, key_len, tbl->hash_rnd); + else + hash = jhash2(key, key_len / sizeof(u32), + tbl->hash_rnd); + } else { + unsigned int key_len = ht->p.key_len; + + if (params.hashfn) + hash = params.hashfn(key, key_len, tbl->hash_rnd); + else + hash = jhash(key, key_len, tbl->hash_rnd); + } + + return rht_bucket_index(tbl, hash); +} + +static inline unsigned int rht_head_hashfn( + struct rhashtable *ht, const struct bucket_table *tbl, + const struct rhash_head *he, const struct rhashtable_params params) +{ + const char *ptr = rht_obj(ht, he); + + return likely(params.obj_hashfn) ? + rht_bucket_index(tbl, params.obj_hashfn(ptr, params.key_len ?: + ht->p.key_len, + tbl->hash_rnd)) : + rht_key_hashfn(ht, tbl, ptr + params.key_offset, params); +} + +/** + * rht_grow_above_75 - returns true if nelems > 0.75 * table-size + * @ht: hash table + * @tbl: current table + */ +static inline bool rht_grow_above_75(const struct rhashtable *ht, + const struct bucket_table *tbl) +{ + /* Expand table when exceeding 75% load */ + return atomic_read(&ht->nelems) > (tbl->size / 4 * 3) && + (!ht->p.max_size || tbl->size < ht->p.max_size); +} + +/** + * rht_shrink_below_30 - returns true if nelems < 0.3 * table-size + * @ht: hash table + * @tbl: current table + */ +static inline bool rht_shrink_below_30(const struct rhashtable *ht, + const struct bucket_table *tbl) +{ + /* Shrink table beneath 30% load */ + return atomic_read(&ht->nelems) < (tbl->size * 3 / 10) && + tbl->size > ht->p.min_size; +} + +/** + * rht_grow_above_100 - returns true if nelems > table-size + * @ht: hash table + * @tbl: current table + */ +static inline bool rht_grow_above_100(const struct rhashtable *ht, + const struct bucket_table *tbl) +{ + return atomic_read(&ht->nelems) > tbl->size && + (!ht->p.max_size || tbl->size < ht->p.max_size); +} + +/** + * rht_grow_above_max - returns true if table is above maximum + * @ht: hash table + * @tbl: current table + */ +static inline bool rht_grow_above_max(const struct rhashtable *ht, + const struct bucket_table *tbl) +{ + return ht->p.insecure_max_entries && + atomic_read(&ht->nelems) >= ht->p.insecure_max_entries; +} + +/* The bucket lock is selected based on the hash and protects mutations + * on a group of hash buckets. + * + * A maximum of tbl->size/2 bucket locks is allocated. This ensures that + * a single lock always covers both buckets which may both contains + * entries which link to the same bucket of the old table during resizing. + * This allows to simplify the locking as locking the bucket in both + * tables during resize always guarantee protection. + * + * IMPORTANT: When holding the bucket lock of both the old and new table + * during expansions and shrinking, the old bucket lock must always be + * acquired first. + */ +static inline spinlock_t *rht_bucket_lock(const struct bucket_table *tbl, + unsigned int hash) +{ + return &tbl->locks[hash & tbl->locks_mask]; +} + +#ifdef CONFIG_PROVE_LOCKING +int lockdep_rht_mutex_is_held(struct rhashtable *ht); +int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, u32 hash); +#else +static inline int lockdep_rht_mutex_is_held(struct rhashtable *ht) +{ + return 1; +} + +static inline int lockdep_rht_bucket_is_held(const struct bucket_table *tbl, + u32 hash) +{ + return 1; +} +#endif /* CONFIG_PROVE_LOCKING */ + +int rhashtable_init(struct rhashtable *ht, + const struct rhashtable_params *params); + +struct bucket_table *rhashtable_insert_slow(struct rhashtable *ht, + const void *key, + struct rhash_head *obj, + struct bucket_table *old_tbl); +int rhashtable_insert_rehash(struct rhashtable *ht, struct bucket_table *tbl); + +int rhashtable_walk_init(struct rhashtable *ht, struct rhashtable_iter *iter); +void rhashtable_walk_exit(struct rhashtable_iter *iter); +int rhashtable_walk_start(struct rhashtable_iter *iter) __acquires(RCU); +void *rhashtable_walk_next(struct rhashtable_iter *iter); +void rhashtable_walk_stop(struct rhashtable_iter *iter) __releases(RCU); + +void rhashtable_free_and_destroy(struct rhashtable *ht, + void (*free_fn)(void *ptr, void *arg), + void *arg); +void rhashtable_destroy(struct rhashtable *ht); + +#define rht_dereference(p, ht) \ + rcu_dereference_protected(p, lockdep_rht_mutex_is_held(ht)) + +#define rht_dereference_rcu(p, ht) \ + rcu_dereference_check(p, lockdep_rht_mutex_is_held(ht)) + +#define rht_dereference_bucket(p, tbl, hash) \ + rcu_dereference_protected(p, lockdep_rht_bucket_is_held(tbl, hash)) + +#define rht_dereference_bucket_rcu(p, tbl, hash) \ + rcu_dereference_check(p, lockdep_rht_bucket_is_held(tbl, hash)) + +#define rht_entry(tpos, pos, member) \ + ({ tpos = container_of(pos, typeof(*tpos), member); 1; }) + +/** + * rht_for_each_continue - continue iterating over hash chain + * @pos: the &struct rhash_head to use as a loop cursor. + * @head: the previous &struct rhash_head to continue from + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + */ +#define rht_for_each_continue(pos, head, tbl, hash) \ + for (pos = rht_dereference_bucket(head, tbl, hash); \ + !rht_is_a_nulls(pos); \ + pos = rht_dereference_bucket((pos)->next, tbl, hash)) + +/** + * rht_for_each - iterate over hash chain + * @pos: the &struct rhash_head to use as a loop cursor. + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + */ +#define rht_for_each(pos, tbl, hash) \ + rht_for_each_continue(pos, (tbl)->buckets[hash], tbl, hash) + +/** + * rht_for_each_entry_continue - continue iterating over hash chain + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct rhash_head to use as a loop cursor. + * @head: the previous &struct rhash_head to continue from + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * @member: name of the &struct rhash_head within the hashable struct. + */ +#define rht_for_each_entry_continue(tpos, pos, head, tbl, hash, member) \ + for (pos = rht_dereference_bucket(head, tbl, hash); \ + (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member); \ + pos = rht_dereference_bucket((pos)->next, tbl, hash)) + +/** + * rht_for_each_entry - iterate over hash chain of given type + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct rhash_head to use as a loop cursor. + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * @member: name of the &struct rhash_head within the hashable struct. + */ +#define rht_for_each_entry(tpos, pos, tbl, hash, member) \ + rht_for_each_entry_continue(tpos, pos, (tbl)->buckets[hash], \ + tbl, hash, member) + +/** + * rht_for_each_entry_safe - safely iterate over hash chain of given type + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct rhash_head to use as a loop cursor. + * @next: the &struct rhash_head to use as next in loop cursor. + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * @member: name of the &struct rhash_head within the hashable struct. + * + * This hash chain list-traversal primitive allows for the looped code to + * remove the loop cursor from the list. + */ +#define rht_for_each_entry_safe(tpos, pos, next, tbl, hash, member) \ + for (pos = rht_dereference_bucket((tbl)->buckets[hash], tbl, hash), \ + next = !rht_is_a_nulls(pos) ? \ + rht_dereference_bucket(pos->next, tbl, hash) : NULL; \ + (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member); \ + pos = next, \ + next = !rht_is_a_nulls(pos) ? \ + rht_dereference_bucket(pos->next, tbl, hash) : NULL) + +/** + * rht_for_each_rcu_continue - continue iterating over rcu hash chain + * @pos: the &struct rhash_head to use as a loop cursor. + * @head: the previous &struct rhash_head to continue from + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * + * This hash chain list-traversal primitive may safely run concurrently with + * the _rcu mutation primitives such as rhashtable_insert() as long as the + * traversal is guarded by rcu_read_lock(). + */ +#define rht_for_each_rcu_continue(pos, head, tbl, hash) \ + for (({barrier(); }), \ + pos = rht_dereference_bucket_rcu(head, tbl, hash); \ + !rht_is_a_nulls(pos); \ + pos = rcu_dereference_raw(pos->next)) + +/** + * rht_for_each_rcu - iterate over rcu hash chain + * @pos: the &struct rhash_head to use as a loop cursor. + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * + * This hash chain list-traversal primitive may safely run concurrently with + * the _rcu mutation primitives such as rhashtable_insert() as long as the + * traversal is guarded by rcu_read_lock(). + */ +#define rht_for_each_rcu(pos, tbl, hash) \ + rht_for_each_rcu_continue(pos, (tbl)->buckets[hash], tbl, hash) + +/** + * rht_for_each_entry_rcu_continue - continue iterating over rcu hash chain + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct rhash_head to use as a loop cursor. + * @head: the previous &struct rhash_head to continue from + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * @member: name of the &struct rhash_head within the hashable struct. + * + * This hash chain list-traversal primitive may safely run concurrently with + * the _rcu mutation primitives such as rhashtable_insert() as long as the + * traversal is guarded by rcu_read_lock(). + */ +#define rht_for_each_entry_rcu_continue(tpos, pos, head, tbl, hash, member) \ + for (({barrier(); }), \ + pos = rht_dereference_bucket_rcu(head, tbl, hash); \ + (!rht_is_a_nulls(pos)) && rht_entry(tpos, pos, member); \ + pos = rht_dereference_bucket_rcu(pos->next, tbl, hash)) + +/** + * rht_for_each_entry_rcu - iterate over rcu hash chain of given type + * @tpos: the type * to use as a loop cursor. + * @pos: the &struct rhash_head to use as a loop cursor. + * @tbl: the &struct bucket_table + * @hash: the hash value / bucket index + * @member: name of the &struct rhash_head within the hashable struct. + * + * This hash chain list-traversal primitive may safely run concurrently with + * the _rcu mutation primitives such as rhashtable_insert() as long as the + * traversal is guarded by rcu_read_lock(). + */ +#define rht_for_each_entry_rcu(tpos, pos, tbl, hash, member) \ + rht_for_each_entry_rcu_continue(tpos, pos, (tbl)->buckets[hash],\ + tbl, hash, member) + +static inline int rhashtable_compare(struct rhashtable_compare_arg *arg, + const void *obj) +{ + struct rhashtable *ht = arg->ht; + const char *ptr = obj; + + return memcmp(ptr + ht->p.key_offset, arg->key, ht->p.key_len); +} + +/** + * rhashtable_lookup_fast - search hash table, inlined version + * @ht: hash table + * @key: the pointer to the key + * @params: hash table parameters + * + * Computes the hash value for the key and traverses the bucket chain looking + * for a entry with an identical key. The first matching entry is returned. + * + * Returns the first entry on which the compare function returned true. + */ +static inline void *rhashtable_lookup_fast( + struct rhashtable *ht, const void *key, + const struct rhashtable_params params) +{ + struct rhashtable_compare_arg arg = { + .ht = ht, + .key = key, + }; + const struct bucket_table *tbl; + struct rhash_head *he; + unsigned int hash; + + rcu_read_lock(); + + tbl = rht_dereference_rcu(ht->tbl, ht); +restart: + hash = rht_key_hashfn(ht, tbl, key, params); + rht_for_each_rcu(he, tbl, hash) { + if (params.obj_cmpfn ? + params.obj_cmpfn(&arg, rht_obj(ht, he)) : + rhashtable_compare(&arg, rht_obj(ht, he))) + continue; + rcu_read_unlock(); + return rht_obj(ht, he); + } + + /* Ensure we see any new tables. */ + smp_rmb(); + + tbl = rht_dereference_rcu(tbl->future_tbl, ht); + if (unlikely(tbl)) + goto restart; + rcu_read_unlock(); + + return NULL; +} + +/* Internal function, please use rhashtable_insert_fast() instead */ +static inline int __rhashtable_insert_fast( + struct rhashtable *ht, const void *key, struct rhash_head *obj, + const struct rhashtable_params params) +{ + struct rhashtable_compare_arg arg = { + .ht = ht, + .key = key, + }; + struct bucket_table *tbl, *new_tbl; + struct rhash_head *head; + spinlock_t *lock; + unsigned int elasticity; + unsigned int hash; + int err; + +restart: + rcu_read_lock(); + + tbl = rht_dereference_rcu(ht->tbl, ht); + + /* All insertions must grab the oldest table containing + * the hashed bucket that is yet to be rehashed. + */ + for (;;) { + hash = rht_head_hashfn(ht, tbl, obj, params); + lock = rht_bucket_lock(tbl, hash); + spin_lock_bh(lock); + + if (tbl->rehash <= hash) + break; + + spin_unlock_bh(lock); + tbl = rht_dereference_rcu(tbl->future_tbl, ht); + } + + new_tbl = rht_dereference_rcu(tbl->future_tbl, ht); + if (unlikely(new_tbl)) { + tbl = rhashtable_insert_slow(ht, key, obj, new_tbl); + if (!IS_ERR_OR_NULL(tbl)) + goto slow_path; + + err = PTR_ERR(tbl); + goto out; + } + + err = -E2BIG; + if (unlikely(rht_grow_above_max(ht, tbl))) + goto out; + + if (unlikely(rht_grow_above_100(ht, tbl))) { +slow_path: + spin_unlock_bh(lock); + err = rhashtable_insert_rehash(ht, tbl); + rcu_read_unlock(); + if (err) + return err; + + goto restart; + } + + err = -EEXIST; + elasticity = ht->elasticity; + rht_for_each(head, tbl, hash) { + if (key && + unlikely(!(params.obj_cmpfn ? + params.obj_cmpfn(&arg, rht_obj(ht, head)) : + rhashtable_compare(&arg, rht_obj(ht, head))))) + goto out; + if (!--elasticity) + goto slow_path; + } + + err = 0; + + head = rht_dereference_bucket(tbl->buckets[hash], tbl, hash); + + RCU_INIT_POINTER(obj->next, head); + + rcu_assign_pointer(tbl->buckets[hash], obj); + + atomic_inc(&ht->nelems); + if (rht_grow_above_75(ht, tbl)) + schedule_work(&ht->run_work); + +out: + spin_unlock_bh(lock); + rcu_read_unlock(); + + return err; +} + +/** + * rhashtable_insert_fast - insert object into hash table + * @ht: hash table + * @obj: pointer to hash head inside object + * @params: hash table parameters + * + * Will take a per bucket spinlock to protect against mutual mutations + * on the same bucket. Multiple insertions may occur in parallel unless + * they map to the same bucket lock. + * + * It is safe to call this function from atomic context. + * + * Will trigger an automatic deferred table resizing if the size grows + * beyond the watermark indicated by grow_decision() which can be passed + * to rhashtable_init(). + */ +static inline int rhashtable_insert_fast( + struct rhashtable *ht, struct rhash_head *obj, + const struct rhashtable_params params) +{ + return __rhashtable_insert_fast(ht, NULL, obj, params); +} + +/** + * rhashtable_lookup_insert_fast - lookup and insert object into hash table + * @ht: hash table + * @obj: pointer to hash head inside object + * @params: hash table parameters + * + * Locks down the bucket chain in both the old and new table if a resize + * is in progress to ensure that writers can't remove from the old table + * and can't insert to the new table during the atomic operation of search + * and insertion. Searches for duplicates in both the old and new table if + * a resize is in progress. + * + * This lookup function may only be used for fixed key hash table (key_len + * parameter set). It will BUG() if used inappropriately. + * + * It is safe to call this function from atomic context. + * + * Will trigger an automatic deferred table resizing if the size grows + * beyond the watermark indicated by grow_decision() which can be passed + * to rhashtable_init(). + */ +static inline int rhashtable_lookup_insert_fast( + struct rhashtable *ht, struct rhash_head *obj, + const struct rhashtable_params params) +{ + const char *key = rht_obj(ht, obj); + + BUG_ON(ht->p.obj_hashfn); + + return __rhashtable_insert_fast(ht, key + ht->p.key_offset, obj, + params); +} + +/** + * rhashtable_lookup_insert_key - search and insert object to hash table + * with explicit key + * @ht: hash table + * @key: key + * @obj: pointer to hash head inside object + * @params: hash table parameters + * + * Locks down the bucket chain in both the old and new table if a resize + * is in progress to ensure that writers can't remove from the old table + * and can't insert to the new table during the atomic operation of search + * and insertion. Searches for duplicates in both the old and new table if + * a resize is in progress. + * + * Lookups may occur in parallel with hashtable mutations and resizing. + * + * Will trigger an automatic deferred table resizing if the size grows + * beyond the watermark indicated by grow_decision() which can be passed + * to rhashtable_init(). + * + * Returns zero on success. + */ +static inline int rhashtable_lookup_insert_key( + struct rhashtable *ht, const void *key, struct rhash_head *obj, + const struct rhashtable_params params) +{ + BUG_ON(!ht->p.obj_hashfn || !key); + + return __rhashtable_insert_fast(ht, key, obj, params); +} + +/* Internal function, please use rhashtable_remove_fast() instead */ +static inline int __rhashtable_remove_fast( + struct rhashtable *ht, struct bucket_table *tbl, + struct rhash_head *obj, const struct rhashtable_params params) +{ + struct rhash_head __rcu **pprev; + struct rhash_head *he; + spinlock_t * lock; + unsigned int hash; + int err = -ENOENT; + + hash = rht_head_hashfn(ht, tbl, obj, params); + lock = rht_bucket_lock(tbl, hash); + + spin_lock_bh(lock); + + pprev = &tbl->buckets[hash]; + rht_for_each(he, tbl, hash) { + if (he != obj) { + pprev = &he->next; + continue; + } + + rcu_assign_pointer(*pprev, obj->next); + err = 0; + break; + } + + spin_unlock_bh(lock); + + return err; +} + +/** + * rhashtable_remove_fast - remove object from hash table + * @ht: hash table + * @obj: pointer to hash head inside object + * @params: hash table parameters + * + * Since the hash chain is single linked, the removal operation needs to + * walk the bucket chain upon removal. The removal operation is thus + * considerable slow if the hash table is not correctly sized. + * + * Will automatically shrink the table via rhashtable_expand() if the + * shrink_decision function specified at rhashtable_init() returns true. + * + * Returns zero on success, -ENOENT if the entry could not be found. + */ +static inline int rhashtable_remove_fast( + struct rhashtable *ht, struct rhash_head *obj, + const struct rhashtable_params params) +{ + struct bucket_table *tbl; + int err; + + rcu_read_lock(); + + tbl = rht_dereference_rcu(ht->tbl, ht); + + /* Because we have already taken (and released) the bucket + * lock in old_tbl, if we find that future_tbl is not yet + * visible then that guarantees the entry to still be in + * the old tbl if it exists. + */ + while ((err = __rhashtable_remove_fast(ht, tbl, obj, params)) && + (tbl = rht_dereference_rcu(tbl->future_tbl, ht))) + ; + + if (err) + goto out; + + atomic_dec(&ht->nelems); + if (unlikely(ht->p.automatic_shrinking && + rht_shrink_below_30(ht, tbl))) + schedule_work(&ht->run_work); + +out: + rcu_read_unlock(); + + return err; +} + +#endif /* _LINUX_RHASHTABLE_H */ + diff --git a/os_dep/linux/rtw_android.c b/os_dep/linux/rtw_android.c index b6df6a0..04073df 100644 --- a/os_dep/linux/rtw_android.c +++ b/os_dep/linux/rtw_android.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifdef CONFIG_GPIO_WAKEUP #include @@ -98,6 +93,7 @@ const char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = { #endif /* CONFIG_GTK_OL */ /* Private command for P2P disable*/ "P2P_DISABLE", + "SET_AEK", "DRIVER_VERSION" }; @@ -310,7 +306,10 @@ int rtw_android_cfg80211_pno_setup(struct net_device *net, memcpy(pno_ssids_local[index].SSID, ssids[index].ssid, ssids[index].ssid_len); } - +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0) + if(ssids) + rtw_mfree((u8 *)ssids, (n_ssids * sizeof(struct cfg80211_ssid))); +#endif pno_time = (interval / 1000); RTW_INFO("%s: nssids: %d, pno_time=%d\n", __func__, nssid, pno_time); @@ -381,8 +380,6 @@ int rtw_android_get_rssi(struct net_device *net, char *command, int total_len) int rtw_android_get_link_speed(struct net_device *net, char *command, int total_len) { _adapter *padapter = (_adapter *)rtw_netdev_priv(net); - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); - struct wlan_network *pcur_network = &pmlmepriv->cur_network; int bytes_written = 0; u16 link_speed = 0; @@ -394,7 +391,6 @@ int rtw_android_get_link_speed(struct net_device *net, char *command, int total_ int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len) { - _adapter *adapter = (_adapter *)rtw_netdev_priv(net); int bytes_written = 0; bytes_written = snprintf(command, total_len, "Macaddr = "MAC_FMT, MAC_ARG(net->dev_addr)); @@ -566,8 +562,41 @@ int rtw_gtk_offload(struct net_device *net, u8 *cmd_ptr) } #endif /* CONFIG_GTK_OL */ +#ifdef CONFIG_RTW_MESH_AEK +static int rtw_android_set_aek(struct net_device *ndev, char *command, int total_len) +{ +#define SET_AEK_DATA_LEN (ETH_ALEN + 32) + + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + u8 *addr; + u8 *aek; + int err = 0; + + if (total_len - strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) - 1 != SET_AEK_DATA_LEN) { + err = -EINVAL; + goto exit; + } + + addr = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AEK]) + 1; + aek = addr + ETH_ALEN; + + RTW_PRINT(FUNC_NDEV_FMT" addr="MAC_FMT"\n" + , FUNC_NDEV_ARG(ndev), MAC_ARG(addr)); + if (0) + RTW_PRINT(FUNC_NDEV_FMT" aek="KEY_FMT KEY_FMT"\n" + , FUNC_NDEV_ARG(ndev), KEY_ARG(aek), KEY_ARG(aek + 16)); + + if (rtw_mesh_plink_set_aek(adapter, addr, aek) != _SUCCESS) + err = -ENOENT; + +exit: + return err; +} +#endif /* CONFIG_RTW_MESH_AEK */ + int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) { + #define PRIVATE_COMMAND_MAX_LEN 8192 int ret = 0; char *command = NULL; int cmd_num; @@ -619,18 +648,21 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) goto exit; } /*RTW_INFO("%s priv_cmd.buf=%p priv_cmd.total_len=%d priv_cmd.used_len=%d\n",__func__,priv_cmd.buf,priv_cmd.total_len,priv_cmd.used_len);*/ - command = rtw_zmalloc(priv_cmd.total_len); + if (priv_cmd.total_len > PRIVATE_COMMAND_MAX_LEN || priv_cmd.total_len < 0) { + RTW_WARN("%s: invalid private command (%d)\n", __FUNCTION__, + priv_cmd.total_len); + ret = -EFAULT; + goto exit; + } + + command = rtw_zmalloc(priv_cmd.total_len+1); if (!command) { RTW_INFO("%s: failed to allocate memory\n", __FUNCTION__); ret = -ENOMEM; goto exit; } -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0) - if (!access_ok(priv_cmd.buf, priv_cmd.total_len)) { -#else - if (!access_ok(VERIFY_READ, priv_cmd.buf, priv_cmd.total_len)) { -#endif + if (!access_ok(priv_cmd.buf, priv_cmd.total_len)) { RTW_INFO("%s: failed to access memory\n", __FUNCTION__); ret = -EFAULT; goto exit; @@ -639,7 +671,7 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) ret = -EFAULT; goto exit; } - + command[priv_cmd.total_len] = '\0'; RTW_INFO("%s: Android private cmd \"%s\" on %s\n" , __FUNCTION__, command, ifr->ifr_name); @@ -826,7 +858,7 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) /* wpa_cli driver wfd-set-tcpport = 554 */ if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) - rtw_wfd_set_ctrl_port(padapter, (u16)get_int_from_command(priv_cmd.buf)); + rtw_wfd_set_ctrl_port(padapter, (u16)get_int_from_command(command)); break; } case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT: { @@ -838,7 +870,7 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) pwfd_info = &padapter->wfd_info; if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) { - pwfd_info->wfd_device_type = (u8) get_int_from_command(priv_cmd.buf); + pwfd_info->wfd_device_type = (u8) get_int_from_command(command); pwfd_info->wfd_device_type &= WFD_DEVINFO_DUAL; } break; @@ -847,7 +879,7 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) case ANDROID_WIFI_CMD_CHANGE_DTIM: { #ifdef CONFIG_LPS u8 dtim; - u8 *ptr = (u8 *) &priv_cmd.buf; + u8 *ptr = (u8 *) command; ptr += 9;/* string command length of "SET_DTIM"; */ @@ -862,19 +894,19 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) #if CONFIG_RTW_MACADDR_ACL case ANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL: { - rtw_set_macaddr_acl(padapter, get_int_from_command(command)); + rtw_set_macaddr_acl(padapter, RTW_ACL_PERIOD_BSS, get_int_from_command(command)); break; } case ANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA: { u8 addr[ETH_ALEN] = {0x00}; macstr2num(addr, command + strlen("HOSTAPD_ACL_ADD_STA") + 3); /* 3 is space bar + "=" + space bar these 3 chars */ - rtw_acl_add_sta(padapter, addr); + rtw_acl_add_sta(padapter, RTW_ACL_PERIOD_BSS, addr); break; } case ANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA: { u8 addr[ETH_ALEN] = {0x00}; macstr2num(addr, command + strlen("HOSTAPD_ACL_REMOVE_STA") + 3); /* 3 is space bar + "=" + space bar these 3 chars */ - rtw_acl_remove_sta(padapter, addr); + rtw_acl_remove_sta(padapter, RTW_ACL_PERIOD_BSS, addr); break; } #endif /* CONFIG_RTW_MACADDR_ACL */ @@ -885,14 +917,17 @@ int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) #endif /* CONFIG_GTK_OL */ case ANDROID_WIFI_CMD_P2P_DISABLE: { #ifdef CONFIG_P2P - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - u8 channel, ch_offset; - u16 bwmode; - rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); #endif /* CONFIG_P2P */ break; } + +#ifdef CONFIG_RTW_MESH_AEK + case ANDROID_WIFI_CMD_SET_AEK: + bytes_written = rtw_android_set_aek(net, command, priv_cmd.total_len); + break; +#endif + case ANDROID_WIFI_CMD_DRIVERVERSION: { bytes_written = strlen(DRIVERVERSION); snprintf(command, bytes_written + 1, DRIVERVERSION); @@ -1060,8 +1095,8 @@ static int wifi_probe(struct platform_device *pdev) wifi_wake_gpio = wifi_irqres->start; #ifdef CONFIG_GPIO_WAKEUP - printk("%s: gpio:%d wifi_wake_gpio:%d\n", __func__, - wifi_irqres->start, wifi_wake_gpio); + RTW_INFO("%s: gpio:%d wifi_wake_gpio:%d\n", __func__, + (int)wifi_irqres->start, wifi_wake_gpio); if (wifi_wake_gpio > 0) { #ifdef CONFIG_PLATFORM_INTEL_BYT @@ -1071,10 +1106,10 @@ static int wifi_probe(struct platform_device *pdev) gpio_direction_input(wifi_wake_gpio); oob_irq = gpio_to_irq(wifi_wake_gpio); #endif /* CONFIG_PLATFORM_INTEL_BYT */ - printk("%s oob_irq:%d\n", __func__, oob_irq); + RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq); } else if (wifi_irqres) { oob_irq = wifi_irqres->start; - printk("%s oob_irq:%d\n", __func__, oob_irq); + RTW_INFO("%s oob_irq:%d\n", __func__, oob_irq); } #endif wifi_control_data = wifi_ctrl; @@ -1103,6 +1138,14 @@ static void shutdown_card(void) LeaveAllPowerSaveMode(g_test_adapter); #endif /* CONFIG_FWLPS_IN_IPS */ +#ifdef CONFIG_WOWLAN +#ifdef CONFIG_GPIO_WAKEUP + /*default wake up pin change to BT*/ + RTW_INFO("%s:default wake up pin change to BT\n", __FUNCTION__); + rtw_hal_switch_gpio_wl_ctrl(g_test_adapter, WAKEUP_GPIO_IDX, _FALSE); +#endif /* CONFIG_GPIO_WAKEUP */ +#endif /* CONFIG_WOWLAN */ + /* Leave SDIO HCI Suspend */ addr = 0x10250086; rtw_write8(g_test_adapter, addr, 0); diff --git a/os_dep/linux/rtw_cfgvendor.c b/os_dep/linux/rtw_cfgvendor.c index b8497d9..d906163 100644 --- a/os_dep/linux/rtw_cfgvendor.c +++ b/os_dep/linux/rtw_cfgvendor.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include @@ -214,22 +209,34 @@ static int rtw_cfgvendor_send_cmd_reply(struct wiphy *wiphy, return rtw_cfg80211_vendor_cmd_reply(skb); } -#define WIFI_FEATURE_INFRA 0x0001 /* Basic infrastructure mode */ -#define WIFI_FEATURE_INFRA_5G 0x0002 /* Support for 5 GHz Band */ -#define WIFI_FEATURE_HOTSPOT 0x0004 /* Support for GAS/ANQP */ -#define WIFI_FEATURE_P2P 0x0008 /* Wifi-Direct */ -#define WIFI_FEATURE_SOFT_AP 0x0010 /* Soft AP */ -#define WIFI_FEATURE_GSCAN 0x0020 /* Google-Scan APIs */ -#define WIFI_FEATURE_NAN 0x0040 /* Neighbor Awareness Networking */ -#define WIFI_FEATURE_D2D_RTT 0x0080 /* Device-to-device RTT */ -#define WIFI_FEATURE_D2AP_RTT 0x0100 /* Device-to-AP RTT */ -#define WIFI_FEATURE_BATCH_SCAN 0x0200 /* Batched Scan (legacy) */ -#define WIFI_FEATURE_PNO 0x0400 /* Preferred network offload */ -#define WIFI_FEATURE_ADDITIONAL_STA 0x0800 /* Support for two STAs */ -#define WIFI_FEATURE_TDLS 0x1000 /* Tunnel directed link setup */ -#define WIFI_FEATURE_TDLS_OFFCHANNEL 0x2000 /* Support for TDLS off channel */ -#define WIFI_FEATURE_EPR 0x4000 /* Enhanced power reporting */ -#define WIFI_FEATURE_AP_STA 0x8000 /* Support for AP STA Concurrency */ +/* Feature enums */ +#define WIFI_FEATURE_INFRA 0x0001 // Basic infrastructure mode +#define WIFI_FEATURE_INFRA_5G 0x0002 // Support for 5 GHz Band +#define WIFI_FEATURE_HOTSPOT 0x0004 // Support for GAS/ANQP +#define WIFI_FEATURE_P2P 0x0008 // Wifi-Direct +#define WIFI_FEATURE_SOFT_AP 0x0010 // Soft AP +#define WIFI_FEATURE_GSCAN 0x0020 // Google-Scan APIs +#define WIFI_FEATURE_NAN 0x0040 // Neighbor Awareness Networking +#define WIFI_FEATURE_D2D_RTT 0x0080 // Device-to-device RTT +#define WIFI_FEATURE_D2AP_RTT 0x0100 // Device-to-AP RTT +#define WIFI_FEATURE_BATCH_SCAN 0x0200 // Batched Scan (legacy) +#define WIFI_FEATURE_PNO 0x0400 // Preferred network offload +#define WIFI_FEATURE_ADDITIONAL_STA 0x0800 // Support for two STAs +#define WIFI_FEATURE_TDLS 0x1000 // Tunnel directed link setup +#define WIFI_FEATURE_TDLS_OFFCHANNEL 0x2000 // Support for TDLS off channel +#define WIFI_FEATURE_EPR 0x4000 // Enhanced power reporting +#define WIFI_FEATURE_AP_STA 0x8000 // Support for AP STA Concurrency +#define WIFI_FEATURE_LINK_LAYER_STATS 0x10000 // Link layer stats collection +#define WIFI_FEATURE_LOGGER 0x20000 // WiFi Logger +#define WIFI_FEATURE_HAL_EPNO 0x40000 // WiFi PNO enhanced +#define WIFI_FEATURE_RSSI_MONITOR 0x80000 // RSSI Monitor +#define WIFI_FEATURE_MKEEP_ALIVE 0x100000 // WiFi mkeep_alive +#define WIFI_FEATURE_CONFIG_NDO 0x200000 // ND offload configure +#define WIFI_FEATURE_TX_TRANSMIT_POWER 0x400000 // Capture Tx transmit power levels +#define WIFI_FEATURE_CONTROL_ROAMING 0x800000 // Enable/Disable firmware roaming +#define WIFI_FEATURE_IE_WHITELIST 0x1000000 // Support Probe IE white listing +#define WIFI_FEATURE_SCAN_RAND 0x2000000 // Support MAC & Probe Sequence Number randomization +// Add more features here #define MAX_FEATURE_SET_CONCURRRENT_GROUPS 3 @@ -244,14 +251,31 @@ int rtw_dev_get_feature_set(struct net_device *dev) feature_set |= WIFI_FEATURE_INFRA; - if (IS_8814A_SERIES(*hal_ver) || IS_8812_SERIES(*hal_ver) || - IS_8821_SERIES(*hal_ver)) +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (is_supported_5g(adapter_to_regsty(adapter)->wireless_mode)) feature_set |= WIFI_FEATURE_INFRA_5G; +#endif feature_set |= WIFI_FEATURE_P2P; feature_set |= WIFI_FEATURE_SOFT_AP; feature_set |= WIFI_FEATURE_ADDITIONAL_STA; +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + feature_set |= WIFI_FEATURE_LINK_LAYER_STATS; +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ + +#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR + feature_set |= WIFI_FEATURE_RSSI_MONITOR; +#endif + +#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER + feature_set |= WIFI_FEATURE_LOGGER; +#endif + +#ifdef CONFIG_RTW_WIFI_HAL + feature_set |= WIFI_FEATURE_CONFIG_NDO; + feature_set |= WIFI_FEATURE_SCAN_RAND; +#endif return feature_set; } @@ -367,8 +391,8 @@ static int rtw_cfgvendor_get_feature_set_matrix(struct wiphy *wiphy, } #if defined(GSCAN_SUPPORT) && 0 -int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, - struct net_device *dev, void *data, int len, wl_vendor_event_t event) +int rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy, + struct net_device *dev, void *data, int len, rtw_vendor_event_t event) { u16 kflags; const void *ptr; @@ -418,7 +442,7 @@ int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, } -static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy, +static int rtw_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -445,7 +469,7 @@ static int wl_cfgvendor_gscan_get_capabilities(struct wiphy *wiphy, return err; } -static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy, +static int rtw_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0, type, band; @@ -492,7 +516,7 @@ static int wl_cfgvendor_gscan_get_channel_list(struct wiphy *wiphy, return err; } -static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, +static int rtw_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -576,7 +600,7 @@ static int wl_cfgvendor_gscan_get_batch_results(struct wiphy *wiphy, return rtw_cfg80211_vendor_cmd_reply(skb); } -static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy, +static int rtw_cfgvendor_initiate_gscan(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -606,7 +630,7 @@ static int wl_cfgvendor_initiate_gscan(struct wiphy *wiphy, } -static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy, +static int rtw_cfgvendor_enable_full_scan_result(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -630,7 +654,7 @@ static int wl_cfgvendor_enable_full_scan_result(struct wiphy *wiphy, return err; } -static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy, +static int rtw_cfgvendor_set_scan_cfg(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -722,7 +746,7 @@ static int wl_cfgvendor_set_scan_cfg(struct wiphy *wiphy, } -static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy, +static int rtw_cfgvendor_hotlist_cfg(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -788,7 +812,7 @@ static int wl_cfgvendor_hotlist_cfg(struct wiphy *wiphy, kfree(hotlist_params); return err; } -static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy, +static int rtw_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0, tmp, type; @@ -825,7 +849,7 @@ static int wl_cfgvendor_set_batch_scan_cfg(struct wiphy *wiphy, return err; } -static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy, +static int rtw_cfgvendor_significant_change_cfg(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -899,7 +923,7 @@ static int wl_cfgvendor_significant_change_cfg(struct wiphy *wiphy, #endif /* GSCAN_SUPPORT */ #if defined(RTT_SUPPORT) && 0 -void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data) +void rtw_cfgvendor_rtt_evt(void *ctx, void *rtt_data) { struct wireless_dev *wdev = (struct wireless_dev *)ctx; struct wiphy *wiphy; @@ -963,7 +987,7 @@ void wl_cfgvendor_rtt_evt(void *ctx, void *rtt_data) return; } -static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev *wdev, +static int rtw_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0, rem, rem1, rem2, type; @@ -1050,7 +1074,7 @@ static int wl_cfgvendor_rtt_set_config(struct wiphy *wiphy, struct wireless_dev return err; } -static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_dev *wdev, +static int rtw_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0, rem, type, target_cnt = 0; @@ -1090,7 +1114,7 @@ static int wl_cfgvendor_rtt_cancel_config(struct wiphy *wiphy, struct wireless_d kfree(mac_list); return err; } -static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_dev *wdev, +static int rtw_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int len) { int err = 0; @@ -1112,57 +1136,611 @@ static int wl_cfgvendor_rtt_get_capability(struct wiphy *wiphy, struct wireless_ } #endif /* RTT_SUPPORT */ -static int wl_cfgvendor_priv_string_handler(struct wiphy *wiphy, - struct wireless_dev *wdev, const void *data, int len) + +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS +enum { + LSTATS_SUBCMD_GET_INFO = ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START, + LSTATS_SUBCMD_SET_INFO, + LSTATS_SUBCMD_CLEAR_INFO, +}; +static void LinkLayerStats(_adapter *padapter) +{ + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct recv_priv *precvpriv = &(padapter->recvpriv); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + u32 ps_time, trx_total_time; + u64 tx_bytes, rx_bytes, trx_total_bytes = 0; + u64 tmp = 0; + + RTW_DBG("%s adapter type : %u\n", __func__, padapter->adapter_type); + + tx_bytes = 0; + rx_bytes = 0; + ps_time = 0; + trx_total_time = 0; + + if ( padapter->netif_up == _TRUE ) { + + pwrpriv->on_time = rtw_get_passing_time_ms(pwrpriv->radio_on_start_time); + + if (rtw_mi_check_fwstate(padapter, _FW_LINKED)) { + if ( pwrpriv->bpower_saving == _TRUE ) { + pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time); + pwrpriv->pwr_saving_start_time = rtw_get_current_time(); + } + } else { +#ifdef CONFIG_IPS + if ( pwrpriv->bpower_saving == _TRUE ) { + pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time); + pwrpriv->pwr_saving_start_time = rtw_get_current_time(); + } +#else + pwrpriv->pwr_saving_time = pwrpriv->on_time; +#endif + } + + ps_time = pwrpriv->pwr_saving_time; + + /* Deviation caused by caculation start time */ + if ( ps_time > pwrpriv->on_time ) + ps_time = pwrpriv->on_time; + + tx_bytes = pdvobjpriv->traffic_stat.last_tx_bytes; + rx_bytes = pdvobjpriv->traffic_stat.last_rx_bytes; + trx_total_bytes = tx_bytes + rx_bytes; + + trx_total_time = pwrpriv->on_time - ps_time; + + if ( trx_total_bytes == 0) { + pwrpriv->tx_time = 0; + pwrpriv->rx_time = 0; + } else { + + /* tx_time = (trx_total_time * tx_total_bytes) / trx_total_bytes; */ + /* rx_time = (trx_total_time * rx_total_bytes) / trx_total_bytes; */ + + tmp = (tx_bytes * trx_total_time); + tmp = rtw_division64(tmp, trx_total_bytes); + pwrpriv->tx_time = tmp; + + tmp = (rx_bytes * trx_total_time); + tmp = rtw_division64(tmp, trx_total_bytes); + pwrpriv->rx_time = tmp; + + } + + } + else { + pwrpriv->on_time = 0; + pwrpriv->tx_time = 0; + pwrpriv->rx_time = 0; + } + +#ifdef CONFIG_RTW_WIFI_HAL_DEBUG + RTW_INFO("- tx_bytes : %llu rx_bytes : %llu total bytes : %llu\n", tx_bytes, rx_bytes, trx_total_bytes); + RTW_INFO("- netif_up = %s, on_time : %u ms\n", padapter->netif_up ? "1":"0", pwrpriv->on_time); + RTW_INFO("- pwr_saving_time : %u (%u) ms\n", pwrpriv->pwr_saving_time, ps_time); + RTW_INFO("- trx_total_time : %u ms\n", trx_total_time); + RTW_INFO("- tx_time : %u ms\n", pwrpriv->tx_time); + RTW_INFO("- rx_time : %u ms\n", pwrpriv->rx_time); +#endif /* CONFIG_RTW_WIFI_HAL_DEBUG */ + +} + +#define DUMMY_TIME_STATICS 99 +static int rtw_cfgvendor_lstats_get_info(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) { int err = 0; - u8 resp[1] = {'\0'}; + _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy)); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + wifi_radio_stat_internal *radio; + wifi_iface_stat *iface; + char *output; + + output = rtw_malloc(sizeof(wifi_radio_stat_internal) + sizeof(wifi_iface_stat)); + if (output == NULL) { + RTW_DBG("Allocate lstats info buffer fail!\n"); + } - RTW_PRINT(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char *)data); - err = rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), resp, 1); + radio = (wifi_radio_stat_internal *)output; + + radio->num_channels = 0; + radio->radio = 1; + + /* to get on_time, tx_time, rx_time */ + LinkLayerStats(padapter); + + radio->on_time = pwrpriv->on_time; + radio->tx_time = pwrpriv->tx_time; + radio->rx_time = pwrpriv->rx_time; + radio->on_time_scan = 0; + radio->on_time_nbd = 0; + radio->on_time_gscan = 0; + radio->on_time_pno_scan = 0; + radio->on_time_hs20 = 0; + #ifdef CONFIG_RTW_WIFI_HAL_DEBUG + RTW_INFO("==== %s ====\n", __func__); + RTW_INFO("radio->radio : %d\n", (radio->radio)); + RTW_INFO("pwrpriv->on_time : %u ms\n", (pwrpriv->on_time)); + RTW_INFO("pwrpriv->tx_time : %u ms\n", (pwrpriv->tx_time)); + RTW_INFO("pwrpriv->rx_time : %u ms\n", (pwrpriv->rx_time)); + RTW_INFO("radio->on_time : %u ms\n", (radio->on_time)); + RTW_INFO("radio->tx_time : %u ms\n", (radio->tx_time)); + RTW_INFO("radio->rx_time : %u ms\n", (radio->rx_time)); + #endif /* CONFIG_RTW_WIFI_HAL_DEBUG */ + + RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data); + err = rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), + output, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat_internal)); if (unlikely(err)) - RTW_ERR(FUNC_NDEV_FMT"Vendor Command reply failed ret:%d\n" + RTW_ERR(FUNC_NDEV_FMT"Vendor Command reply failed ret:%d \n" , FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err); - + rtw_mfree(output, sizeof(wifi_iface_stat) + sizeof(wifi_radio_stat_internal)); return err; -#if 0 - struct bcm_cfg80211 *cfg = wiphy_priv(wiphy); +} +static int rtw_cfgvendor_lstats_set_info(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ int err = 0; - int data_len = 0; + RTW_INFO("%s\n", __func__); + return err; +} +static int rtw_cfgvendor_lstats_clear_info(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int err = 0; + RTW_INFO("%s\n", __func__); + return err; +} +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ +#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR +static int rtw_cfgvendor_set_rssi_monitor(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy)); + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + + struct recv_priv *precvpriv = &padapter->recvpriv; + int err = 0, rem, type; + const struct nlattr *iter; - bzero(cfg->ioctl_buf, WLC_IOCTL_MAXLEN); + RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data); + + nla_for_each_attr(iter, data, len, rem) { + type = nla_type(iter); - if (strncmp((char *)data, BRCM_VENDOR_SCMD_CAPA, strlen(BRCM_VENDOR_SCMD_CAPA)) == 0) { - err = wldev_iovar_getbuf(bcmcfg_to_prmry_ndev(cfg), "cap", NULL, 0, - cfg->ioctl_buf, WLC_IOCTL_MAXLEN, &cfg->ioctl_buf_sync); - if (unlikely(err)) { - WL_ERR(("error (%d)\n", err)); - return err; + switch (type) { + case RSSI_MONITOR_ATTRIBUTE_MAX_RSSI: + pwdev_priv->rssi_monitor_max = (s8)nla_get_u32(iter);; + break; + case RSSI_MONITOR_ATTRIBUTE_MIN_RSSI: + pwdev_priv->rssi_monitor_min = (s8)nla_get_u32(iter); + break; + case RSSI_MONITOR_ATTRIBUTE_START: + pwdev_priv->rssi_monitor_enable = (u8)nla_get_u32(iter); + break; } - data_len = strlen(cfg->ioctl_buf); - cfg->ioctl_buf[data_len] = '\0'; } - err = rtw_cfgvendor_send_cmd_reply(wiphy, bcmcfg_to_prmry_ndev(cfg), - cfg->ioctl_buf, data_len + 1); + return err; +} + +void rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter) { + struct wireless_dev *wdev = padapter->rtw_wdev; + struct wiphy *wiphy= wdev->wiphy; + struct recv_priv *precvpriv = &padapter->recvpriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wlan_network *pcur_network = &pmlmepriv->cur_network; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + struct sk_buff *skb; + u32 tot_len = NLMSG_DEFAULT_SIZE; + gfp_t kflags; + rssi_monitor_evt data ; + s8 rssi = precvpriv->rssi; + + if (pwdev_priv->rssi_monitor_enable == 0 || check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) + return; + + if (rssi < pwdev_priv->rssi_monitor_max || rssi > pwdev_priv->rssi_monitor_min) + return; + + kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL; + + /* Alloc the SKB for vendor_event */ + skb = rtw_cfg80211_vendor_event_alloc(wiphy, wdev, tot_len, GOOGLE_RSSI_MONITOR_EVENT, kflags); + if (!skb) { + goto exit; + } + + _rtw_memset(&data, 0, sizeof(data)); + + data.version = RSSI_MONITOR_EVT_VERSION; + data.cur_rssi = rssi; + _rtw_memcpy(data.BSSID, pcur_network->network.MacAddress, sizeof(mac_addr)); + + nla_append(skb, sizeof(data), &data); + + rtw_cfg80211_vendor_event(skb, kflags); +exit: + return; +} +#endif /* CONFIG_RTW_CFGVEDNOR_RSSIMONITR */ + +#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER +static int rtw_cfgvendor_logger_start_logging(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int ret = 0, rem, type; + char ring_name[32] = {0}; + int log_level = 0, flags = 0, time_intval = 0, threshold = 0; + const struct nlattr *iter; + + nla_for_each_attr(iter, data, len, rem) { + type = nla_type(iter); + switch (type) { + case LOGGER_ATTRIBUTE_RING_NAME: + strncpy(ring_name, nla_data(iter), + MIN(sizeof(ring_name) -1, nla_len(iter))); + break; + case LOGGER_ATTRIBUTE_LOG_LEVEL: + log_level = nla_get_u32(iter); + break; + case LOGGER_ATTRIBUTE_RING_FLAGS: + flags = nla_get_u32(iter); + break; + case LOGGER_ATTRIBUTE_LOG_TIME_INTVAL: + time_intval = nla_get_u32(iter); + break; + case LOGGER_ATTRIBUTE_LOG_MIN_DATA_SIZE: + threshold = nla_get_u32(iter); + break; + default: + RTW_ERR("Unknown type: %d\n", type); + ret = WIFI_ERROR_INVALID_ARGS; + goto exit; + } + } + +exit: + return ret; +} +static int rtw_cfgvendor_logger_get_feature(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int err = 0; + u32 supported_features = 0; + + err = rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), &supported_features, sizeof(supported_features)); + if (unlikely(err)) - WL_ERR(("Vendor Command reply failed ret:%d\n", err)); - else - WL_INFORM(("Vendor Command reply sent successfully!\n")); + RTW_ERR(FUNC_NDEV_FMT" Vendor Command reply failed ret:%d\n" + , FUNC_NDEV_ARG(wdev_to_ndev(wdev)), err); + + return err; +} +static int rtw_cfgvendor_logger_get_version(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy)); + HAL_DATA_TYPE *hal = GET_HAL_DATA(padapter); + int ret = 0, rem, type; + int buf_len = 1024; + char *buf_ptr; + const struct nlattr *iter; + gfp_t kflags; + + kflags = in_atomic() ? GFP_ATOMIC : GFP_KERNEL; + buf_ptr = kzalloc(buf_len, kflags); + if (!buf_ptr) { + RTW_ERR("failed to allocate the buffer for version n"); + ret = -ENOMEM; + goto exit; + } + nla_for_each_attr(iter, data, len, rem) { + type = nla_type(iter); + switch (type) { + case LOGGER_ATTRIBUTE_GET_DRIVER: + memcpy(buf_ptr, DRIVERVERSION, strlen(DRIVERVERSION)+1); + break; + case LOGGER_ATTRIBUTE_GET_FW: + sprintf(buf_ptr, "v%d.%d", hal->firmware_version, hal->firmware_sub_version); + break; + default: + RTW_ERR("Unknown type: %d\n", type); + ret = -EINVAL; + goto exit; + } + } + if (ret < 0) { + RTW_ERR("failed to get the version %d\n", ret); + goto exit; + } + + + ret = rtw_cfgvendor_send_cmd_reply(wiphy, wdev_to_ndev(wdev), buf_ptr, strlen(buf_ptr)); +exit: + kfree(buf_ptr); + return ret; +} + +static int rtw_cfgvendor_logger_get_ring_status(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int ret = 0; + int ring_id; + char ring_buf_name[] = "RTW_RING_BUFFER"; + + struct sk_buff *skb; + wifi_ring_buffer_status ring_status; + + + _rtw_memcpy(ring_status.name, ring_buf_name, strlen(ring_buf_name)+1); + ring_status.ring_id = 1; + /* Alloc the SKB for vendor_event */ + skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, + sizeof(wifi_ring_buffer_status)); + if (!skb) { + RTW_ERR("skb allocation is failed\n"); + ret = FAIL; + goto exit; + } + + nla_put_u32(skb, LOGGER_ATTRIBUTE_RING_NUM, 1); + nla_put(skb, LOGGER_ATTRIBUTE_RING_STATUS, sizeof(wifi_ring_buffer_status), + &ring_status); + ret = cfg80211_vendor_cmd_reply(skb); + + if (ret) { + RTW_ERR("Vendor Command reply failed ret:%d \n", ret); + } +exit: + return ret; +} + +static int rtw_cfgvendor_logger_get_ring_data(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int ret = 0, rem, type; + char ring_name[32] = {0}; + const struct nlattr *iter; + + nla_for_each_attr(iter, data, len, rem) { + type = nla_type(iter); + switch (type) { + case LOGGER_ATTRIBUTE_RING_NAME: + strncpy(ring_name, nla_data(iter), + MIN(sizeof(ring_name) -1, nla_len(iter))); + RTW_INFO(" %s LOGGER_ATTRIBUTE_RING_NAME : %s\n", __func__, ring_name); + break; + default: + RTW_ERR("Unknown type: %d\n", type); + return ret; + } + } + + + return ret; +} + +static int rtw_cfgvendor_logger_get_firmware_memory_dump(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int ret = WIFI_ERROR_NOT_SUPPORTED; + + return ret; +} + +static int rtw_cfgvendor_logger_start_pkt_fate_monitoring(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int ret = WIFI_SUCCESS; + + return ret; +} + +static int rtw_cfgvendor_logger_get_tx_pkt_fates(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int ret = WIFI_SUCCESS; + + return ret; +} + +static int rtw_cfgvendor_logger_get_rx_pkt_fates(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int ret = WIFI_SUCCESS; + + return ret; +} + +#endif /* CONFIG_RTW_CFGVENDOR_WIFI_LOGGER */ +#ifdef CONFIG_RTW_WIFI_HAL +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + +#ifndef ETHER_ISMULTI +#define ETHER_ISMULTI(ea) (((const u8 *)(ea))[0] & 1) +#endif + + +static u8 null_addr[ETH_ALEN] = {0}; +static void rtw_hal_random_gen_mac_addr(u8 *mac_addr) +{ + do { + get_random_bytes(&mac_addr[3], ETH_ALEN-3); + if (memcmp(mac_addr, null_addr, ETH_ALEN) != 0) + break; + } while(1); +} + +void rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter) +{ + u8 mac_addr[ETH_ALEN]; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + + memcpy(mac_addr, pwdev_priv->pno_mac_addr, ETH_ALEN); + if (mac_addr[0] == 0xFF) return; + rtw_hal_random_gen_mac_addr(mac_addr); + memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN); +#ifdef CONFIG_RTW_DEBUG + print_hex_dump(KERN_DEBUG, "pno_mac_addr: ", + DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr, + ETH_ALEN, 1); +#endif +} + +void rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr) +{ + rtw_ps_deny(adapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(adapter); + + rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, mac_addr); +#ifdef CONFIG_RTW_DEBUG + rtw_hal_dump_macaddr(RTW_DBGDUMP, adapter); +#endif + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); +} + +static int rtw_cfgvendor_set_rand_mac_oui(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int err = 0; + PADAPTER adapter; + void *devaddr; + struct net_device *netdev; + int type, mac_len; + u8 pno_random_mac_oui[3]; + u8 mac_addr[ETH_ALEN] = {0}; + struct pwrctrl_priv *pwrctl; + struct rtw_wdev_priv *pwdev_priv; + + type = nla_type(data); + mac_len = nla_len(data); + if (mac_len != 3) { + RTW_ERR("%s oui len error %d != 3\n", __func__, mac_len); + return -1; + } + + if (type == ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI) { + memcpy(pno_random_mac_oui, nla_data(data), 3); + print_hex_dump(KERN_DEBUG, "pno_random_mac_oui: ", + DUMP_PREFIX_OFFSET, 16, 1, pno_random_mac_oui, + 3, 1); + + if (ETHER_ISMULTI(pno_random_mac_oui)) { + pr_err("%s: oui is multicast address\n", __func__); + return -1; + } + + adapter = wiphy_to_adapter(wiphy); + if (adapter == NULL) { + pr_err("%s: wiphy_to_adapter == NULL\n", __func__); + return -1; + } + + pwdev_priv = adapter_wdev_data(adapter); + + memcpy(mac_addr, pno_random_mac_oui, 3); + rtw_hal_random_gen_mac_addr(mac_addr); + memcpy(pwdev_priv->pno_mac_addr, mac_addr, ETH_ALEN); +#ifdef CONFIG_RTW_DEBUG + print_hex_dump(KERN_DEBUG, "pno_mac_addr: ", + DUMP_PREFIX_OFFSET, 16, 1, pwdev_priv->pno_mac_addr, + ETH_ALEN, 1); +#endif + } else { + RTW_ERR("%s oui type error %x != 0x2\n", __func__, type); + err = -1; + } + return err; +} + #endif + + +static int rtw_cfgvendor_set_nodfs_flag(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int err = 0; + int type; + u32 nodfs = 0; + _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy)); + + RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data); + + type = nla_type(data); + if (type == ANDR_WIFI_ATTRIBUTE_NODFS_SET) { + nodfs = nla_get_u32(data); + adapter_to_dvobj(padapter)->nodfs = nodfs; + } else { + err = -EINVAL; + } + + RTW_INFO("%s nodfs=%d, err=%d\n", __func__, nodfs, err); + + return err; } +static int rtw_cfgvendor_set_country(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ +#define CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NUL */ + int err = 0, rem, type; + char country_code[CNTRY_BUF_SZ] = {0}; + const struct nlattr *iter; + _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy)); + + RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data); + + nla_for_each_attr(iter, data, len, rem) { + type = nla_type(iter); + switch (type) { + case ANDR_WIFI_ATTRIBUTE_COUNTRY: + _rtw_memcpy(country_code, nla_data(iter), + MIN(nla_len(iter), CNTRY_BUF_SZ)); + break; + default: + RTW_ERR("Unknown type: %d\n", type); + return -EINVAL; + } + } + + RTW_INFO("%s country_code:\"%c%c\" \n", __func__, country_code[0], country_code[1]); + + rtw_set_country(padapter, country_code); + + return err; +} + +static int rtw_cfgvendor_set_nd_offload(struct wiphy *wiphy, + struct wireless_dev *wdev, const void *data, int len) +{ + int err = 0; + int type; + u8 nd_en = 0; + _adapter *padapter = GET_PRIMARY_ADAPTER(wiphy_to_adapter(wiphy)); + + RTW_DBG(FUNC_NDEV_FMT" %s\n", FUNC_NDEV_ARG(wdev_to_ndev(wdev)), (char*)data); + + type = nla_type(data); + if (type == ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE) { + nd_en = nla_get_u8(data); + /* ND has been enabled when wow is enabled */ + } else { + err = -EINVAL; + } + + RTW_INFO("%s nd_en=%d, err=%d\n", __func__, nd_en, err); + + return err; +} +#endif /* CONFIG_RTW_WIFI_HAL */ + static const struct wiphy_vendor_command rtw_vendor_cmds[] = { - { - { - .vendor_id = OUI_BRCM, - .subcmd = BRCM_VENDOR_SCMD_PRIV_STR - }, - .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_priv_string_handler - }, #if defined(GSCAN_SUPPORT) && 0 { { @@ -1170,7 +1748,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_GET_CAPABILITIES }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_gscan_get_capabilities + .doit = rtw_cfgvendor_gscan_get_capabilities }, { { @@ -1178,7 +1756,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_set_scan_cfg + .doit = rtw_cfgvendor_set_scan_cfg }, { { @@ -1186,7 +1764,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_set_batch_scan_cfg + .doit = rtw_cfgvendor_set_batch_scan_cfg }, { { @@ -1194,7 +1772,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_ENABLE_GSCAN }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_initiate_gscan + .doit = rtw_cfgvendor_initiate_gscan }, { { @@ -1202,7 +1780,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_enable_full_scan_result + .doit = rtw_cfgvendor_enable_full_scan_result }, { { @@ -1210,7 +1788,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_HOTLIST }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_hotlist_cfg + .doit = rtw_cfgvendor_hotlist_cfg }, { { @@ -1218,7 +1796,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_significant_change_cfg + .doit = rtw_cfgvendor_significant_change_cfg }, { { @@ -1226,7 +1804,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_gscan_get_batch_results + .doit = rtw_cfgvendor_gscan_get_batch_results }, { { @@ -1234,7 +1812,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_gscan_get_channel_list + .doit = rtw_cfgvendor_gscan_get_channel_list }, #endif /* GSCAN_SUPPORT */ #if defined(RTT_SUPPORT) && 0 @@ -1244,7 +1822,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = RTT_SUBCMD_SET_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_rtt_set_config + .doit = rtw_cfgvendor_rtt_set_config }, { { @@ -1252,7 +1830,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = RTT_SUBCMD_CANCEL_CONFIG }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_rtt_cancel_config + .doit = rtw_cfgvendor_rtt_cancel_config }, { { @@ -1260,13 +1838,160 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { .subcmd = RTT_SUBCMD_GETCAPABILITY }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, - .doit = wl_cfgvendor_rtt_get_capability + .doit = rtw_cfgvendor_rtt_get_capability }, #endif /* RTT_SUPPORT */ +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LSTATS_SUBCMD_GET_INFO + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_lstats_get_info + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LSTATS_SUBCMD_SET_INFO + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_lstats_set_info + }, { { .vendor_id = OUI_GOOGLE, - .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET + .subcmd = LSTATS_SUBCMD_CLEAR_INFO + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_lstats_clear_info + }, +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ +#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = WIFI_SUBCMD_SET_RSSI_MONITOR + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_set_rssi_monitor + }, +#endif /* CONFIG_RTW_CFGVEDNOR_RSSIMONITOR */ +#ifdef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LOGGER_START_LOGGING + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_logger_start_logging + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LOGGER_GET_FEATURE + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_logger_get_feature + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LOGGER_GET_VER + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_logger_get_version + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LOGGER_GET_RING_STATUS + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_logger_get_ring_status + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LOGGER_GET_RING_DATA + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_logger_get_ring_data + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LOGGER_TRIGGER_MEM_DUMP + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_logger_get_firmware_memory_dump + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LOGGER_START_PKT_FATE_MONITORING + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_logger_start_pkt_fate_monitoring + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LOGGER_GET_TX_PKT_FATES + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_logger_get_tx_pkt_fates + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = LOGGER_GET_RX_PKT_FATES + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_logger_get_rx_pkt_fates + }, +#endif /* CONFIG_RTW_CFGVENDOR_WIFI_LOGGER */ +#ifdef CONFIG_RTW_WIFI_HAL +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_set_rand_mac_oui + }, +#endif + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = WIFI_SUBCMD_NODFS_SET + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_set_nodfs_flag + + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = WIFI_SUBCMD_SET_COUNTRY_CODE + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_set_country + }, + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = WIFI_SUBCMD_CONFIG_ND_OFFLOAD + }, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, + .doit = rtw_cfgvendor_set_nd_offload + }, +#endif /* CONFIG_RTW_WIFI_HAL */ + { + { + .vendor_id = OUI_GOOGLE, + .subcmd = WIFI_SUBCMD_GET_FEATURE_SET }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, .doit = rtw_cfgvendor_get_feature_set @@ -1274,7 +1999,7 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { { { .vendor_id = OUI_GOOGLE, - .subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX + .subcmd = WIFI_SUBCMD_GET_FEATURE_SET_MATRIX }, .flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV, .doit = rtw_cfgvendor_get_feature_set_matrix @@ -1282,20 +2007,23 @@ static const struct wiphy_vendor_command rtw_vendor_cmds[] = { }; static const struct nl80211_vendor_cmd_info rtw_vendor_events[] = { - { OUI_BRCM, BRCM_VENDOR_EVENT_UNSPEC }, - { OUI_BRCM, BRCM_VENDOR_EVENT_PRIV_STR }, #if defined(GSCAN_SUPPORT) && 0 - { OUI_GOOGLE, GOOGLE_GSCAN_SIGNIFICANT_EVENT }, - { OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT }, - { OUI_GOOGLE, GOOGLE_GSCAN_BATCH_SCAN_EVENT }, - { OUI_GOOGLE, GOOGLE_SCAN_FULL_RESULTS_EVENT }, + { OUI_GOOGLE, GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS }, + { OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_FOUND }, + { OUI_GOOGLE, GSCAN_EVENT_SCAN_RESULTS_AVAILABLE }, + { OUI_GOOGLE, GSCAN_EVENT_FULL_SCAN_RESULTS }, #endif /* GSCAN_SUPPORT */ #if defined(RTT_SUPPORT) && 0 - { OUI_GOOGLE, GOOGLE_RTT_COMPLETE_EVENT }, + { OUI_GOOGLE, RTT_EVENT_COMPLETE }, #endif /* RTT_SUPPORT */ + +#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR + { OUI_GOOGLE, GOOGLE_RSSI_MONITOR_EVENT }, +#endif /* RTW_CFGVEDNOR_RSSIMONITR */ + #if defined(GSCAN_SUPPORT) && 0 - { OUI_GOOGLE, GOOGLE_SCAN_COMPLETE_EVENT }, - { OUI_GOOGLE, GOOGLE_GSCAN_GEOFENCE_LOST_EVENT } + { OUI_GOOGLE, GSCAN_EVENT_COMPLETE_SCAN }, + { OUI_GOOGLE, GSCAN_EVENT_HOTLIST_RESULTS_LOST } #endif /* GSCAN_SUPPORT */ }; diff --git a/os_dep/linux/rtw_cfgvendor.h b/os_dep/linux/rtw_cfgvendor.h index 2ed3a9e..af423fc 100644 --- a/os_dep/linux/rtw_cfgvendor.h +++ b/os_dep/linux/rtw_cfgvendor.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,19 +11,12 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef _RTW_CFGVENDOR_H_ #define _RTW_CFGVENDOR_H_ -#define OUI_BRCM 0x001018 #define OUI_GOOGLE 0x001A11 -#define BRCM_VENDOR_SUBCMD_PRIV_STR 1 #define ATTRIBUTE_U32_LEN (NLA_HDRLEN + 4) #define VENDOR_ID_OVERHEAD ATTRIBUTE_U32_LEN #define VENDOR_SUBCMD_OVERHEAD ATTRIBUTE_U32_LEN @@ -44,53 +37,106 @@ VENDOR_SUBCMD_OVERHEAD + \ VENDOR_DATA_OVERHEAD) typedef enum { - /* don't use 0 as a valid subcommand */ - VENDOR_NL80211_SUBCMD_UNSPECIFIED, + /* don't use 0 as a valid subcommand */ + VENDOR_NL80211_SUBCMD_UNSPECIFIED, + + /* define all vendor startup commands between 0x0 and 0x0FFF */ + VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001, + VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF, + + /* define all GScan related commands between 0x1000 and 0x10FF */ + ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000, + ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF, + + /* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */ + ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100, + ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF, - /* define all vendor startup commands between 0x0 and 0x0FFF */ - VENDOR_NL80211_SUBCMD_RANGE_START = 0x0001, - VENDOR_NL80211_SUBCMD_RANGE_END = 0x0FFF, + /* define all RTT related commands between 0x1100 and 0x11FF */ + ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100, + ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF, - /* define all GScan related commands between 0x1000 and 0x10FF */ - ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START = 0x1000, - ANDROID_NL80211_SUBCMD_GSCAN_RANGE_END = 0x10FF, + ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200, + ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF, - /* define all NearbyDiscovery related commands between 0x1100 and 0x11FF */ - ANDROID_NL80211_SUBCMD_NBD_RANGE_START = 0x1100, - ANDROID_NL80211_SUBCMD_NBD_RANGE_END = 0x11FF, + /* define all Logger related commands between 0x1400 and 0x14FF */ + ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START = 0x1400, + ANDROID_NL80211_SUBCMD_DEBUG_RANGE_END = 0x14FF, - /* define all RTT related commands between 0x1100 and 0x11FF */ - ANDROID_NL80211_SUBCMD_RTT_RANGE_START = 0x1100, - ANDROID_NL80211_SUBCMD_RTT_RANGE_END = 0x11FF, + /* define all wifi offload related commands between 0x1600 and 0x16FF */ + ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_START = 0x1600, + ANDROID_NL80211_SUBCMD_WIFI_OFFLOAD_RANGE_END = 0x16FF, - ANDROID_NL80211_SUBCMD_LSTATS_RANGE_START = 0x1200, - ANDROID_NL80211_SUBCMD_LSTATS_RANGE_END = 0x12FF, + /* define all NAN related commands between 0x1700 and 0x17FF */ + ANDROID_NL80211_SUBCMD_NAN_RANGE_START = 0x1700, + ANDROID_NL80211_SUBCMD_NAN_RANGE_END = 0x17FF, - ANDROID_NL80211_SUBCMD_TDLS_RANGE_START = 0x1300, - ANDROID_NL80211_SUBCMD_TDLS_RANGE_END = 0x13FF, - /* This is reserved for future usage */ + /* define all Android Packet Filter related commands between 0x1800 and 0x18FF */ + ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START = 0x1800, + ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_END = 0x18FF, + + /* This is reserved for future usage */ } ANDROID_VENDOR_SUB_COMMAND; -enum wl_vendor_subcmd { - BRCM_VENDOR_SCMD_UNSPEC, - BRCM_VENDOR_SCMD_PRIV_STR, - GSCAN_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START, - GSCAN_SUBCMD_SET_CONFIG, - GSCAN_SUBCMD_SET_SCAN_CONFIG, - GSCAN_SUBCMD_ENABLE_GSCAN, - GSCAN_SUBCMD_GET_SCAN_RESULTS, - GSCAN_SUBCMD_SCAN_RESULTS, - GSCAN_SUBCMD_SET_HOTLIST, - GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG, - GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS, - GSCAN_SUBCMD_GET_CHANNEL_LIST, - ANDR_WIFI_SUBCMD_GET_FEATURE_SET, - ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX, +enum rtw_vendor_subcmd { + GSCAN_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_GSCAN_RANGE_START, + + GSCAN_SUBCMD_SET_CONFIG, /* 0x1001 */ + + GSCAN_SUBCMD_SET_SCAN_CONFIG, /* 0x1002 */ + GSCAN_SUBCMD_ENABLE_GSCAN, /* 0x1003 */ + GSCAN_SUBCMD_GET_SCAN_RESULTS, /* 0x1004 */ + GSCAN_SUBCMD_SCAN_RESULTS, /* 0x1005 */ + + GSCAN_SUBCMD_SET_HOTLIST, /* 0x1006 */ + + GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG, /* 0x1007 */ + GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS, /* 0x1008 */ + GSCAN_SUBCMD_GET_CHANNEL_LIST, /* 0x1009 */ + + WIFI_SUBCMD_GET_FEATURE_SET, /* 0x100A */ + WIFI_SUBCMD_GET_FEATURE_SET_MATRIX, /* 0x100B */ + WIFI_SUBCMD_SET_PNO_RANDOM_MAC_OUI, /* 0x100C */ + WIFI_SUBCMD_NODFS_SET, /* 0x100D */ + WIFI_SUBCMD_SET_COUNTRY_CODE, /* 0x100E */ + /* Add more sub commands here */ + GSCAN_SUBCMD_SET_EPNO_SSID, /* 0x100F */ + + WIFI_SUBCMD_SET_SSID_WHITE_LIST, /* 0x1010 */ + WIFI_SUBCMD_SET_ROAM_PARAMS, /* 0x1011 */ + WIFI_SUBCMD_ENABLE_LAZY_ROAM, /* 0x1012 */ + WIFI_SUBCMD_SET_BSSID_PREF, /* 0x1013 */ + WIFI_SUBCMD_SET_BSSID_BLACKLIST, /* 0x1014 */ + + GSCAN_SUBCMD_ANQPO_CONFIG, /* 0x1015 */ + WIFI_SUBCMD_SET_RSSI_MONITOR, /* 0x1016 */ + WIFI_SUBCMD_CONFIG_ND_OFFLOAD, /* 0x1017 */ + /* Add more sub commands here */ + + GSCAN_SUBCMD_MAX, + RTT_SUBCMD_SET_CONFIG = ANDROID_NL80211_SUBCMD_RTT_RANGE_START, RTT_SUBCMD_CANCEL_CONFIG, RTT_SUBCMD_GETCAPABILITY, - /* Add more sub commands here */ + + APF_SUBCMD_GET_CAPABILITIES = ANDROID_NL80211_SUBCMD_PKT_FILTER_RANGE_START, + APF_SUBCMD_SET_FILTER, + + LOGGER_START_LOGGING = ANDROID_NL80211_SUBCMD_DEBUG_RANGE_START, + LOGGER_TRIGGER_MEM_DUMP, + LOGGER_GET_MEM_DUMP, + LOGGER_GET_VER, + LOGGER_GET_RING_STATUS, + LOGGER_GET_RING_DATA, + LOGGER_GET_FEATURE, + LOGGER_RESET_LOGGING, + LOGGER_TRIGGER_DRIVER_MEM_DUMP, + LOGGER_GET_DRIVER_MEM_DUMP, + LOGGER_START_PKT_FATE_MONITORING, + LOGGER_GET_TX_PKT_FATES, + LOGGER_GET_RX_PKT_FATES, + VENDOR_SUBCMD_MAX }; @@ -169,6 +215,13 @@ enum gscan_ch_attributes { GSCAN_ATTRIBUTE_CH_ID_7 }; +enum wifi_rssi_monitor_attr { + RSSI_MONITOR_ATTRIBUTE_MAX_RSSI, + RSSI_MONITOR_ATTRIBUTE_MIN_RSSI, + RSSI_MONITOR_ATTRIBUTE_START, +}; + + enum rtt_attributes { RTT_ATTRIBUTE_TARGET_CNT, RTT_ATTRIBUTE_TARGET_INFO, @@ -183,24 +236,49 @@ enum rtt_attributes { RTT_ATTRIBUTE_TARGET_NUM_RETRY }; -typedef enum wl_vendor_event { - BRCM_VENDOR_EVENT_UNSPEC, - BRCM_VENDOR_EVENT_PRIV_STR, - GOOGLE_GSCAN_SIGNIFICANT_EVENT, - GOOGLE_GSCAN_GEOFENCE_FOUND_EVENT, - GOOGLE_GSCAN_BATCH_SCAN_EVENT, - GOOGLE_SCAN_FULL_RESULTS_EVENT, - GOOGLE_RTT_COMPLETE_EVENT, - GOOGLE_SCAN_COMPLETE_EVENT, - GOOGLE_GSCAN_GEOFENCE_LOST_EVENT -} wl_vendor_event_t; +enum logger_attributes { + LOGGER_ATTRIBUTE_GET_DRIVER, + LOGGER_ATTRIBUTE_GET_FW, + LOGGER_ATTRIBUTE_RING_ID, + LOGGER_ATTRIBUTE_RING_NAME, + LOGGER_ATTRIBUTE_RING_FLAGS, + LOGGER_ATTRIBUTE_LOG_LEVEL, + LOGGER_ATTRIBUTE_LOG_TIME_INTVAL, + LOGGER_ATTRIBUTE_LOG_MIN_DATA_SIZE, + LOGGER_ATTRIBUTE_FW_DUMP_LEN, + LOGGER_ATTRIBUTE_FW_DUMP_DATA, + LOGGERG_ATTRIBUTE_RING_DATA, + LOGGER_ATTRIBUTE_RING_STATUS, + LOGGER_ATTRIBUTE_RING_NUM +}; +typedef enum rtw_vendor_event { + RTK_RESERVED1, + RTK_RESERVED2, + GSCAN_EVENT_SIGNIFICANT_CHANGE_RESULTS , + GSCAN_EVENT_HOTLIST_RESULTS_FOUND, + GSCAN_EVENT_SCAN_RESULTS_AVAILABLE, + GSCAN_EVENT_FULL_SCAN_RESULTS, + RTT_EVENT_COMPLETE, + GSCAN_EVENT_COMPLETE_SCAN, + GSCAN_EVENT_HOTLIST_RESULTS_LOST, + GSCAN_EVENT_EPNO_EVENT, + GOOGLE_DEBUG_RING_EVENT, + GOOGLE_DEBUG_MEM_DUMP_EVENT, + GSCAN_EVENT_ANQPO_HOTSPOT_MATCH, + GOOGLE_RSSI_MONITOR_EVENT +} rtw_vendor_event_t; enum andr_wifi_feature_set_attr { ANDR_WIFI_ATTRIBUTE_NUM_FEATURE_SET, - ANDR_WIFI_ATTRIBUTE_FEATURE_SET + ANDR_WIFI_ATTRIBUTE_FEATURE_SET, + ANDR_WIFI_ATTRIBUTE_RANDOM_MAC_OUI, + ANDR_WIFI_ATTRIBUTE_NODFS_SET, + ANDR_WIFI_ATTRIBUTE_COUNTRY, + ANDR_WIFI_ATTRIBUTE_ND_OFFLOAD_VALUE + // Add more attribute here }; -typedef enum wl_vendor_gscan_attribute { +typedef enum rtw_vendor_gscan_attribute { ATTR_START_GSCAN, ATTR_STOP_GSCAN, ATTR_SET_SCAN_BATCH_CFG_ID, /* set batch scan params */ @@ -210,7 +288,7 @@ typedef enum wl_vendor_gscan_attribute { ATTR_GET_GSCAN_CAPABILITIES_ID, /* Add more sub commands here */ ATTR_GSCAN_MAX -} wl_vendor_gscan_attribute_t; +} rtw_vendor_gscan_attribute_t; typedef enum gscan_batch_attribute { ATTR_GSCAN_BATCH_BESTN, @@ -227,9 +305,309 @@ typedef enum gscan_complete_event { WIFI_SCAN_BUFFER_FULL, WIFI_SCAN_COMPLETE } gscan_complete_event_t; +/* wifi_hal.h */ +/* WiFi Common definitions */ +typedef unsigned char byte; +typedef int wifi_request_id; +typedef int wifi_channel; // indicates channel frequency in MHz +typedef int wifi_rssi; +typedef byte mac_addr[6]; +typedef byte oui[3]; +typedef int64_t wifi_timestamp; // In microseconds (us) +typedef int64_t wifi_timespan; // In picoseconds (ps) + +struct wifi_info; +struct wifi_interface_info; +typedef struct wifi_info *wifi_handle; +typedef struct wifi_interface_info *wifi_interface_handle; + +/* channel operating width */ +typedef enum { + WIFI_CHAN_WIDTH_20 = 0, + WIFI_CHAN_WIDTH_40 = 1, + WIFI_CHAN_WIDTH_80 = 2, + WIFI_CHAN_WIDTH_160 = 3, + WIFI_CHAN_WIDTH_80P80 = 4, + WIFI_CHAN_WIDTH_5 = 5, + WIFI_CHAN_WIDTH_10 = 6, + WIFI_CHAN_WIDTH_INVALID = -1 +} wifi_channel_width; + +typedef int wifi_radio; + +typedef struct { + wifi_channel_width width; + int center_frequency0; + int center_frequency1; + int primary_frequency; +} wifi_channel_spec; + +typedef enum { + WIFI_SUCCESS = 0, + WIFI_ERROR_NONE = 0, + WIFI_ERROR_UNKNOWN = -1, + WIFI_ERROR_UNINITIALIZED = -2, + WIFI_ERROR_NOT_SUPPORTED = -3, + WIFI_ERROR_NOT_AVAILABLE = -4, // Not available right now, but try later + WIFI_ERROR_INVALID_ARGS = -5, + WIFI_ERROR_INVALID_REQUEST_ID = -6, + WIFI_ERROR_TIMED_OUT = -7, + WIFI_ERROR_TOO_MANY_REQUESTS = -8, // Too many instances of this request + WIFI_ERROR_OUT_OF_MEMORY = -9, + WIFI_ERROR_BUSY = -10, +} wifi_error; + +typedef int wifi_ring_buffer_id; +/* ring buffer params */ +/** + * written_bytes and read_bytes implement a producer consumer API + * hence written_bytes >= read_bytes + * a modulo arithmetic of the buffer size has to be applied to those counters: + * actual offset into ring buffer = written_bytes % ring_buffer_byte_size + * + */ +typedef struct { + u8 name[32]; + u32 flags; + wifi_ring_buffer_id ring_id; // unique integer representing the ring + u32 ring_buffer_byte_size; // total memory size allocated for the buffer + u32 verbose_level; // verbose level for ring buffer + u32 written_bytes; // number of bytes that was written to the buffer by driver, + // monotonously increasing integer + u32 read_bytes; // number of bytes that was read from the buffer by user land, + // monotonously increasing integer + u32 written_records; // number of records that was written to the buffer by driver, + // monotonously increasing integer +} wifi_ring_buffer_status; + +#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS +#define STATS_MAJOR_VERSION 1 +#define STATS_MINOR_VERSION 0 +#define STATS_MICRO_VERSION 0 + +typedef enum { + WIFI_DISCONNECTED = 0, + WIFI_AUTHENTICATING = 1, + WIFI_ASSOCIATING = 2, + WIFI_ASSOCIATED = 3, + WIFI_EAPOL_STARTED = 4, // if done by firmware/driver + WIFI_EAPOL_COMPLETED = 5, // if done by firmware/driver +} wifi_connection_state; + +typedef enum { + WIFI_ROAMING_IDLE = 0, + WIFI_ROAMING_ACTIVE = 1, +} wifi_roam_state; + +typedef enum { + WIFI_INTERFACE_STA = 0, + WIFI_INTERFACE_SOFTAP = 1, + WIFI_INTERFACE_IBSS = 2, + WIFI_INTERFACE_P2P_CLIENT = 3, + WIFI_INTERFACE_P2P_GO = 4, + WIFI_INTERFACE_NAN = 5, + WIFI_INTERFACE_MESH = 6, + WIFI_INTERFACE_UNKNOWN = -1 + } wifi_interface_mode; + +#define WIFI_CAPABILITY_QOS 0x00000001 // set for QOS association +#define WIFI_CAPABILITY_PROTECTED 0x00000002 // set for protected association (802.11 beacon frame control protected bit set) +#define WIFI_CAPABILITY_INTERWORKING 0x00000004 // set if 802.11 Extended Capabilities element interworking bit is set +#define WIFI_CAPABILITY_HS20 0x00000008 // set for HS20 association +#define WIFI_CAPABILITY_SSID_UTF8 0x00000010 // set is 802.11 Extended Capabilities element UTF-8 SSID bit is set +#define WIFI_CAPABILITY_COUNTRY 0x00000020 // set is 802.11 Country Element is present + +typedef struct { + wifi_interface_mode mode; // interface mode + u8 mac_addr[6]; // interface mac address (self) + wifi_connection_state state; // connection state (valid for STA, CLI only) + wifi_roam_state roaming; // roaming state + u32 capabilities; // WIFI_CAPABILITY_XXX (self) + u8 ssid[33]; // null terminated SSID + u8 bssid[6]; // bssid + u8 ap_country_str[3]; // country string advertised by AP + u8 country_str[3]; // country string for this association +} wifi_interface_link_layer_info; + +/* channel information */ +typedef struct { + wifi_channel_width width; // channel width (20, 40, 80, 80+80, 160) + wifi_channel center_freq; // primary 20 MHz channel + wifi_channel center_freq0; // center frequency (MHz) first segment + wifi_channel center_freq1; // center frequency (MHz) second segment +} wifi_channel_info; + +/* wifi rate */ +typedef struct { + u32 preamble :3; // 0: OFDM, 1:CCK, 2:HT 3:VHT 4..7 reserved + u32 nss :2; // 0:1x1, 1:2x2, 3:3x3, 4:4x4 + u32 bw :3; // 0:20MHz, 1:40Mhz, 2:80Mhz, 3:160Mhz + u32 rateMcsIdx :8; // OFDM/CCK rate code would be as per ieee std in the units of 0.5mbps + // HT/VHT it would be mcs index + u32 reserved :16; // reserved + u32 bitrate; // units of 100 Kbps +} wifi_rate; + +/* channel statistics */ +typedef struct { + wifi_channel_info channel; // channel + u32 on_time; // msecs the radio is awake (32 bits number accruing over time) + u32 cca_busy_time; // msecs the CCA register is busy (32 bits number accruing over time) +} wifi_channel_stat; + +// Max number of tx power levels. The actual number vary per device and is specified by |num_tx_levels| +#define RADIO_STAT_MAX_TX_LEVELS 256 + +/* Internal radio statistics structure in the driver */ +typedef struct { + wifi_radio radio; // wifi radio (if multiple radio supported) + u32 on_time; // msecs the radio is awake (32 bits number accruing over time) + u32 tx_time; // msecs the radio is transmitting (32 bits number accruing over time) + u32 rx_time; // msecs the radio is in active receive (32 bits number accruing over time) + u32 on_time_scan; // msecs the radio is awake due to all scan (32 bits number accruing over time) + u32 on_time_nbd; // msecs the radio is awake due to NAN (32 bits number accruing over time) + u32 on_time_gscan; // msecs the radio is awake due to G?scan (32 bits number accruing over time) + u32 on_time_roam_scan; // msecs the radio is awake due to roam?scan (32 bits number accruing over time) + u32 on_time_pno_scan; // msecs the radio is awake due to PNO scan (32 bits number accruing over time) + u32 on_time_hs20; // msecs the radio is awake due to HS2.0 scans and GAS exchange (32 bits number accruing over time) + u32 num_channels; // number of channels + wifi_channel_stat channels[]; // channel statistics +} wifi_radio_stat_internal; + +/** + * Packet statistics reporting by firmware is performed on MPDU basi (i.e. counters increase by 1 for each MPDU) + * As well, "data packet" in associated comments, shall be interpreted as 802.11 data packet, + * that is, 802.11 frame control subtype == 2 and excluding management and control frames. + * + * As an example, in the case of transmission of an MSDU fragmented in 16 MPDUs which are transmitted + * OTA in a 16 units long a-mpdu, for which a block ack is received with 5 bits set: + * tx_mpdu : shall increase by 5 + * retries : shall increase by 16 + * tx_ampdu : shall increase by 1 + * data packet counters shall not increase regardless of the number of BAR potentially sent by device for this a-mpdu + * data packet counters shall not increase regardless of the number of BA received by device for this a-mpdu + * + * For each subsequent retransmission of the 11 remaining non ACK'ed mpdus + * (regardless of the fact that they are transmitted in a-mpdu or not) + * retries : shall increase by 1 + * + * If no subsequent BA or ACK are received from AP, until packet lifetime expires for those 11 packet that were not ACK'ed + * mpdu_lost : shall increase by 11 + */ + +/* per rate statistics */ +typedef struct { + wifi_rate rate; // rate information + u32 tx_mpdu; // number of successfully transmitted data pkts (ACK rcvd) + u32 rx_mpdu; // number of received data pkts + u32 mpdu_lost; // number of data packet losses (no ACK) + u32 retries; // total number of data pkt retries + u32 retries_short; // number of short data pkt retries + u32 retries_long; // number of long data pkt retries +} wifi_rate_stat; + +/* access categories */ +typedef enum { + WIFI_AC_VO = 0, + WIFI_AC_VI = 1, + WIFI_AC_BE = 2, + WIFI_AC_BK = 3, + WIFI_AC_MAX = 4, +} wifi_traffic_ac; + +/* wifi peer type */ +typedef enum +{ + WIFI_PEER_STA, + WIFI_PEER_AP, + WIFI_PEER_P2P_GO, + WIFI_PEER_P2P_CLIENT, + WIFI_PEER_NAN, + WIFI_PEER_TDLS, + WIFI_PEER_INVALID, +} wifi_peer_type; + +/* per peer statistics */ +typedef struct { + wifi_peer_type type; // peer type (AP, TDLS, GO etc.) + u8 peer_mac_address[6]; // mac address + u32 capabilities; // peer WIFI_CAPABILITY_XXX + u32 num_rate; // number of rates + wifi_rate_stat rate_stats[]; // per rate statistics, number of entries = num_rate +} wifi_peer_info; + +/* Per access category statistics */ +typedef struct { + wifi_traffic_ac ac; // access category (VI, VO, BE, BK) + u32 tx_mpdu; // number of successfully transmitted unicast data pkts (ACK rcvd) + u32 rx_mpdu; // number of received unicast data packets + u32 tx_mcast; // number of succesfully transmitted multicast data packets + // STA case: implies ACK received from AP for the unicast packet in which mcast pkt was sent + u32 rx_mcast; // number of received multicast data packets + u32 rx_ampdu; // number of received unicast a-mpdus; support of this counter is optional + u32 tx_ampdu; // number of transmitted unicast a-mpdus; support of this counter is optional + u32 mpdu_lost; // number of data pkt losses (no ACK) + u32 retries; // total number of data pkt retries + u32 retries_short; // number of short data pkt retries + u32 retries_long; // number of long data pkt retries + u32 contention_time_min; // data pkt min contention time (usecs) + u32 contention_time_max; // data pkt max contention time (usecs) + u32 contention_time_avg; // data pkt avg contention time (usecs) + u32 contention_num_samples; // num of data pkts used for contention statistics +} wifi_wmm_ac_stat; + +/* interface statistics */ +typedef struct { + wifi_interface_handle iface; // wifi interface + wifi_interface_link_layer_info info; // current state of the interface + u32 beacon_rx; // access point beacon received count from connected AP + u64 average_tsf_offset; // average beacon offset encountered (beacon_TSF - TBTT) + // The average_tsf_offset field is used so as to calculate the + // typical beacon contention time on the channel as well may be + // used to debug beacon synchronization and related power consumption issue + u32 leaky_ap_detected; // indicate that this AP typically leaks packets beyond the driver guard time. + u32 leaky_ap_avg_num_frames_leaked; // average number of frame leaked by AP after frame with PM bit set was ACK'ed by AP + u32 leaky_ap_guard_time; // guard time currently in force (when implementing IEEE power management based on + // frame control PM bit), How long driver waits before shutting down the radio and + // after receiving an ACK for a data frame with PM bit set) + u32 mgmt_rx; // access point mgmt frames received count from connected AP (including Beacon) + u32 mgmt_action_rx; // action frames received count + u32 mgmt_action_tx; // action frames transmit count + wifi_rssi rssi_mgmt; // access Point Beacon and Management frames RSSI (averaged) + wifi_rssi rssi_data; // access Point Data Frames RSSI (averaged) from connected AP + wifi_rssi rssi_ack; // access Point ACK RSSI (averaged) from connected AP + wifi_wmm_ac_stat ac[WIFI_AC_MAX]; // per ac data packet statistics + u32 num_peers; // number of peers + wifi_peer_info peer_info[]; // per peer statistics +} wifi_iface_stat; + +/* configuration params */ +typedef struct { + u32 mpdu_size_threshold; // threshold to classify the pkts as short or long + // packet size < mpdu_size_threshold => short + u32 aggressive_statistics_gathering; // set for field debug mode. Driver should collect all statistics regardless of performance impact. +} wifi_link_layer_params; + +#define RSSI_MONITOR_EVT_VERSION 1 +typedef struct { + u8 version; + s8 cur_rssi; + mac_addr BSSID; +} rssi_monitor_evt; + + +/* wifi statistics bitmap */ +#define WIFI_STATS_RADIO 0x00000001 // all radio statistics +#define WIFI_STATS_RADIO_CCA 0x00000002 // cca_busy_time (within radio statistics) +#define WIFI_STATS_RADIO_CHANNELS 0x00000004 // all channel statistics (within radio statistics) +#define WIFI_STATS_RADIO_SCAN 0x00000008 // all scan statistics (within radio statistics) +#define WIFI_STATS_IFACE 0x00000010 // all interface statistics +#define WIFI_STATS_IFACE_TXRATE 0x00000020 // all tx rate statistics (within interface statistics) +#define WIFI_STATS_IFACE_AC 0x00000040 // all ac statistics (within interface statistics) +#define WIFI_STATS_IFACE_CONTENTION 0x00000080 // all contention (min, max, avg) statistics (within ac statisctics) + +#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */ -/* Capture the BRCM_VENDOR_SUBCMD_PRIV_STRINGS* here */ -#define BRCM_VENDOR_SCMD_CAPA "cap" #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) extern int rtw_cfgvendor_attach(struct wiphy *wiphy); @@ -237,9 +615,19 @@ extern int rtw_cfgvendor_detach(struct wiphy *wiphy); extern int rtw_cfgvendor_send_async_event(struct wiphy *wiphy, struct net_device *dev, int event_id, const void *data, int len); #if defined(GSCAN_SUPPORT) && 0 -extern int wl_cfgvendor_send_hotlist_event(struct wiphy *wiphy, - struct net_device *dev, void *data, int len, wl_vendor_event_t event); +extern int rtw_cfgvendor_send_hotlist_event(struct wiphy *wiphy, + struct net_device *dev, void *data, int len, rtw_vendor_event_t event); #endif #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) || defined(RTW_VENDOR_EXT_SUPPORT) */ +#ifdef CONFIG_RTW_CFGVEDNOR_RSSIMONITOR +void rtw_cfgvendor_rssi_monitor_evt(_adapter *padapter); +#endif + +#ifdef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI +void rtw_hal_pno_random_gen_mac_addr(PADAPTER adapter); +void rtw_hal_set_hw_mac_addr(PADAPTER adapter, u8 *mac_addr); +#endif + + #endif /* _RTW_CFGVENDOR_H_ */ diff --git a/os_dep/linux/rtw_proc.c b/os_dep/linux/rtw_proc.c index 6bf16a3..f92735e 100644 --- a/os_dep/linux/rtw_proc.c +++ b/os_dep/linux/rtw_proc.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,20 +11,13 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include /* tolower() */ #include #include #include "rtw_proc.h" -#ifdef CONFIG_BT_COEXIST #include -#endif #ifdef CONFIG_PROC_DEBUG @@ -127,7 +120,8 @@ static ssize_t proc_set_log_level(struct file *file, const char __user *buffer, int num = sscanf(tmp, "%d ", &log_level); - if (log_level >= _DRV_NONE_ && log_level <= _DRV_MAX_) { + if (num == 1 && + log_level >= _DRV_NONE_ && log_level <= _DRV_MAX_) { rtw_drv_log_level = log_level; printk("rtw_drv_log_level:%d\n", rtw_drv_log_level); } @@ -166,6 +160,27 @@ static int proc_get_chplan_test(struct seq_file *m, void *v) return 0; } +static int proc_get_chplan_ver(struct seq_file *m, void *v) +{ + dump_chplan_ver(m); + return 0; +} + +#ifdef RTW_HALMAC +extern void rtw_halmac_get_version(char *str, u32 len); + +static int proc_get_halmac_info(struct seq_file *m, void *v) +{ + char ver[30] = {0}; + + + rtw_halmac_get_version(ver, 30); + RTW_PRINT_SEL(m, "version: %s\n", ver); + + return 0; +} +#endif + /* * rtw_drv_proc: * init/deinit when register/unregister driver @@ -180,6 +195,10 @@ const struct rtw_proc_hdl drv_proc_hdls[] = { RTW_PROC_HDL_SSEQ("country_chplan_map", proc_get_country_chplan_map, NULL), RTW_PROC_HDL_SSEQ("chplan_id_list", proc_get_chplan_id_list, NULL), RTW_PROC_HDL_SSEQ("chplan_test", proc_get_chplan_test, NULL), + RTW_PROC_HDL_SSEQ("chplan_ver", proc_get_chplan_ver, NULL), +#ifdef RTW_HALMAC + RTW_PROC_HDL_SSEQ("halmac_info", proc_get_halmac_info, NULL), +#endif /* RTW_HALMAC */ }; const int drv_proc_hdls_num = sizeof(drv_proc_hdls) / sizeof(struct rtw_proc_hdl); @@ -382,17 +401,6 @@ static int proc_get_sdio_card_info(struct seq_file *m, void *v) } #endif /* CONFIG_SDIO_HCI */ -#ifdef RTW_HALMAC -#include "../../hal/hal_halmac.h" -static int proc_get_halmac_info(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - - rtw_dump_halmac_info(m); - return 0; -} -#endif static int proc_get_fw_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -441,6 +449,93 @@ static int proc_get_rf_reg_dump(struct seq_file *m, void *v) return 0; } +#ifdef CONFIG_RTW_LED +int proc_get_led_config(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_led_config(m, adapter); + + return 0; +} + +ssize_t proc_set_led_config(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + char tmp[32]; + u8 strategy; + u8 iface_en_mask; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hhx", &strategy, &iface_en_mask); + + if (num >= 1) + rtw_led_set_strategy(adapter, strategy); + if (num >= 2) + rtw_led_set_iface_en_mask(adapter, iface_en_mask); + } + + return count; +} +#endif /* CONFIG_RTW_LED */ + +#ifdef CONFIG_AP_MODE +int proc_get_aid_status(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_aid_status(m, adapter); + + return 0; +} + +ssize_t proc_set_aid_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_priv *stapriv = &adapter->stapriv; + + char tmp[32]; + u8 rr; + u16 started_aid; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hu", &rr, &started_aid); + + if (num >= 1) + stapriv->rr_aid = rr ? 1 : 0; + if (num >= 2) { + started_aid = started_aid % (stapriv->max_aid + 1); + stapriv->started_aid = started_aid ? started_aid : 1; + } + } + + return count; +} +#endif /* CONFIG_AP_MODE */ + static int proc_get_dump_tx_rate_bmp(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -483,6 +578,130 @@ static int proc_get_customer_str(struct seq_file *m, void *v) } #endif /* CONFIG_RTW_CUSTOMER_STR */ +#ifdef CONFIG_SCAN_BACKOP +static int proc_get_backop_flags_sta(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_sta(mlmeext)); + + return 0; +} + +static ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + char tmp[32]; + u8 flags; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &flags); + + if (num == 1) + mlmeext_assign_scan_backop_flags_sta(mlmeext, flags); + } + + return count; +} + +#ifdef CONFIG_AP_MODE +static int proc_get_backop_flags_ap(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_ap(mlmeext)); + + return 0; +} + +static ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + char tmp[32]; + u8 flags; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &flags); + + if (num == 1) + mlmeext_assign_scan_backop_flags_ap(mlmeext, flags); + } + + return count; +} +#endif /* CONFIG_AP_MODE */ + +#ifdef CONFIG_RTW_MESH +static int proc_get_backop_flags_mesh(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + RTW_PRINT_SEL(m, "0x%02x\n", mlmeext_scan_backop_flags_mesh(mlmeext)); + + return 0; +} + +static ssize_t proc_set_backop_flags_mesh(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + char tmp[32]; + u8 flags; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &flags); + + if (num == 1) + mlmeext_assign_scan_backop_flags_mesh(mlmeext, flags); + } + + return count; +} +#endif /* CONFIG_RTW_MESH */ + +#endif /* CONFIG_SCAN_BACKOP */ + /* gpio setting */ #ifdef CONFIG_GPIO_API static ssize_t proc_set_config_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) @@ -574,6 +793,7 @@ static ssize_t proc_set_gpio(struct file *file, const char __user *buffer, size_ return count; } #endif + static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { @@ -599,7 +819,8 @@ static ssize_t proc_set_rx_info_msg(struct file *file, const char __user *buffer if (buffer && !copy_from_user(tmp, buffer, count)) { int num = sscanf(tmp, "%d", &phy_info_flag); - precvpriv->store_law_data_flag = (BOOLEAN) phy_info_flag; + if (num == 1) + precvpriv->store_law_data_flag = (BOOLEAN) phy_info_flag; /*RTW_INFO("precvpriv->store_law_data_flag = %d\n",( BOOLEAN )(precvpriv->store_law_data_flag));*/ } @@ -618,11 +839,9 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) _irqL irqL; struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); - struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); struct sta_info *psta; - u8 bc_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - u8 null_addr[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); struct sta_priv *pstapriv = &padapter->stapriv; int i; @@ -633,10 +852,12 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); - if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE)) + if (MLME_IS_STA(padapter)) status = "station mode"; - else if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE)) + else if (MLME_IS_AP(padapter)) status = "AP mode"; + else if (MLME_IS_MESH(padapter)) + status = "mesh mode"; else status = " "; _RTW_PRINT_SEL(m, "status=%s\n", status); @@ -650,11 +871,11 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) plist = get_next(plist); - if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE) - && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), 6) != _TRUE)) { + if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) != _TRUE) + && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN) != _TRUE)) { - switch (psta->bw_mode) { + switch (psta->cmn.bw_mode) { case CHANNEL_WIDTH_20: BW = "20M"; @@ -676,11 +897,11 @@ static int proc_get_tx_info_msg(struct seq_file *m, void *v) BW = ""; break; } - current_rate_id = rtw_get_current_tx_rate(adapter, psta->mac_id); - current_sgi = rtw_get_current_tx_sgi(adapter, psta->mac_id); + current_rate_id = rtw_get_current_tx_rate(adapter, psta); + current_sgi = rtw_get_current_tx_sgi(adapter, psta); RTW_PRINT_SEL(m, "==============================\n"); - _RTW_PRINT_SEL(m, "macaddr=" MAC_FMT"\n", MAC_ARG(psta->hwaddr)); + _RTW_PRINT_SEL(m, "macaddr=" MAC_FMT"\n", MAC_ARG(psta->cmn.mac_addr)); _RTW_PRINT_SEL(m, "Tx_Data_Rate=%s\n", HDATA_RATE(current_rate_id)); _RTW_PRINT_SEL(m, "BW=%s,sgi=%u\n", BW, current_sgi); @@ -747,32 +968,34 @@ static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *b return count; } -static int proc_get_turboedca_ctrl(struct seq_file *m, void *v) + +static int proc_get_sta_tp_dump(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); - if (hal_data) - RTW_PRINT_SEL(m, "Turbo-EDCA :%s\n", (hal_data->dis_turboedca) ? "Disable" : "Enable"); + if (padapter) + RTW_PRINT_SEL(m, "sta_tp_dump :%s\n", (padapter->bsta_tp_dump) ? "enable" : "disable"); return 0; } -static ssize_t proc_set_turboedca_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +static ssize_t proc_set_sta_tp_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); char tmp[32] = {0}; - int mode = 0, num = 0; + int mode = 0; + int num = 0; if (count < 1) return -EFAULT; - if (count > sizeof(tmp)) + if (count > sizeof(tmp)) { + rtw_warn_on(1); return -EFAULT; + } if (buffer && !copy_from_user(tmp, buffer, count)) { @@ -782,79 +1005,174 @@ static ssize_t proc_set_turboedca_ctrl(struct file *file, const char __user *buf RTW_INFO("argument number is wrong\n"); return -EFAULT; } - hal_data->dis_turboedca = mode; + if (padapter) + padapter->bsta_tp_dump = mode; } return count; } -static int proc_get_mac_qinfo(struct seq_file *m, void *v) +static int proc_get_sta_tp_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - rtw_hal_get_hwreg(adapter, HW_VAR_DUMP_MAC_QUEUE_INFO, (u8 *)m); + if (padapter) + rtw_sta_traffic_info(m, padapter); return 0; } -int proc_get_wifi_spec(struct seq_file *m, void *v) +static int proc_get_turboedca_ctrl(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - struct registry_priv *pregpriv = &padapter->registrypriv; - - RTW_PRINT_SEL(m, "wifi_spec=%d\n", pregpriv->wifi_spec); - return 0; -} - -static int proc_get_chan_plan(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); - dump_cur_chset(m, adapter); + if (hal_data) + RTW_PRINT_SEL(m, "Turbo-EDCA :%s\n", (hal_data->dis_turboedca) ? "Disable" : "Enable"); return 0; } -static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +static ssize_t proc_set_turboedca_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 chan_plan = RTW_CHPLAN_MAX; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); - if (!padapter) - return -EFAULT; + char tmp[32] = {0}; + int mode = 0, num = 0; - if (count < 1) { - RTW_INFO("argument size is less than 1\n"); + if (count < 1) return -EFAULT; - } - if (count > sizeof(tmp)) { - rtw_warn_on(1); + if (count > sizeof(tmp)) return -EFAULT; - } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhx", &chan_plan); - if (num != 1) - return count; - } - rtw_set_channel_plan(padapter, chan_plan); + num = sscanf(tmp, "%d ", &mode); - return count; -} + if (num != 1) { + RTW_INFO("argument number is wrong\n"); + return -EFAULT; + } + hal_data->dis_turboedca = mode; + } + return count; +} +#ifdef CONFIG_WOWLAN +static int proc_get_wow_lps_ctrl(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + + if (pwrctl) + RTW_PRINT_SEL(m, "WOW lps :%s\n", (pwrctl->wowlan_dis_lps) ? "Disable" : "Enable"); + + return 0; +} + +static ssize_t proc_set_wow_lps_ctrl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + + char tmp[32] = {0}; + int mode = 0, num = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) + return -EFAULT; + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + num = sscanf(tmp, "%d ", &mode); + + if (num != 1) { + RTW_INFO("argument number is wrong\n"); + return -EFAULT; + } + pwrctl->wowlan_dis_lps = mode; + RTW_INFO("WOW lps :%s\n", (pwrctl->wowlan_dis_lps) ? "Disable" : "Enable"); + } + return count; +} +#endif + +static int proc_get_mac_qinfo(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_hal_get_hwreg(adapter, HW_VAR_DUMP_MAC_QUEUE_INFO, (u8 *)m); + + return 0; +} + +int proc_get_wifi_spec(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + RTW_PRINT_SEL(m, "wifi_spec=%d\n", pregpriv->wifi_spec); + return 0; +} + +static int proc_get_chan_plan(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_cur_chset(m, adapter_to_rfctl(adapter)); + + return 0; +} + +static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 chan_plan = RTW_CHPLAN_UNSPECIFIED; + + if (!padapter) + return -EFAULT; + + if (count < 1) { + RTW_INFO("argument size is less than 1\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%hhx", &chan_plan); + if (num != 1) + return count; + } + + rtw_set_channel_plan(padapter, chan_plan); + + return count; +} static int proc_get_country_code(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); - if (adapter->mlmepriv.country_ent) - dump_country_chplan(m, adapter->mlmepriv.country_ent); + if (rfctl->country_ent) + dump_country_chplan(m, rfctl->country_ent); else RTW_PRINT_SEL(m, "unspecified\n"); @@ -904,12 +1222,26 @@ ssize_t proc_set_macaddr_acl(struct file *file, const char __user *buffer, size_ { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *mlme = &adapter->mlmepriv; - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; char tmp[17 * NUM_ACL + 32] = {0}; + u8 period; + char cmd[32]; u8 mode; u8 addr[ETH_ALEN]; +#define MAC_ACL_CMD_MODE 0 +#define MAC_ACL_CMD_ADD 1 +#define MAC_ACL_CMD_DEL 2 +#define MAC_ACL_CMD_CLR 3 +#define MAC_ACL_CMD_NUM 4 + + static const char * const mac_acl_cmd_str[] = { + "mode", + "add", + "del", + "clr", + }; + u8 cmd_id = MAC_ACL_CMD_NUM; + if (count < 1) return -EFAULT; @@ -919,36 +1251,93 @@ ssize_t proc_set_macaddr_acl(struct file *file, const char __user *buffer, size_ } if (buffer && !copy_from_user(tmp, buffer, count)) { - /* mode [] */ + /* + * mode [] + * mode + * add [] + * del [] + * clr + */ char *c, *next; + int i; + u8 is_bcast; next = tmp; c = strsep(&next, " \t"); + if (!c || sscanf(c, "%hhu", &period) != 1) + goto exit; - if (sscanf(c, "%hhu", &mode) != 1) - return count; + if (period >= RTW_ACL_PERIOD_NUM) { + RTW_WARN(FUNC_ADPT_FMT" invalid period:%u", FUNC_ADPT_ARG(adapter), period); + goto exit; + } - if (mode >= RTW_ACL_MODE_MAX) - mode = RTW_ACL_MODE_DISABLED; + c = strsep(&next, " \t"); + if (!c || sscanf(c, "%s", cmd) != 1) + goto exit; - rtw_set_macaddr_acl(adapter, RTW_ACL_MODE_DISABLED); /* deinit first */ - if (mode == RTW_ACL_MODE_DISABLED) - return count; + for (i = 0; i < MAC_ACL_CMD_NUM; i++) + if (strcmp(mac_acl_cmd_str[i], cmd) == 0) + cmd_id = i; - rtw_set_macaddr_acl(adapter, mode); + switch (cmd_id) { + case MAC_ACL_CMD_MODE: + c = strsep(&next, " \t"); + if (!c || sscanf(c, "%hhu", &mode) != 1) + goto exit; - /* macaddr list */ + if (mode >= RTW_ACL_MODE_MAX) { + RTW_WARN(FUNC_ADPT_FMT" invalid mode:%u", FUNC_ADPT_ARG(adapter), mode); + goto exit; + } + break; + + case MAC_ACL_CMD_ADD: + case MAC_ACL_CMD_DEL: + break; + + case MAC_ACL_CMD_CLR: + /* clear settings */ + rtw_macaddr_acl_clear(adapter, period); + goto exit; + + default: + RTW_WARN(FUNC_ADPT_FMT" invalid cmd:\"%s\"", FUNC_ADPT_ARG(adapter), cmd); + goto exit; + } + + /* check for macaddr list */ c = strsep(&next, " \t"); + if (!c && cmd_id == MAC_ACL_CMD_MODE) { + /* set mode only */ + rtw_set_macaddr_acl(adapter, period, mode); + goto exit; + } + + if (cmd_id == MAC_ACL_CMD_MODE) { + /* set mode and entire macaddr list */ + rtw_macaddr_acl_clear(adapter, period); + rtw_set_macaddr_acl(adapter, period, mode); + } + while (c != NULL) { if (sscanf(c, MAC_SFMT, MAC_SARG(addr)) != 6) break; - if (rtw_check_invalid_mac_address(addr, 0) == _FALSE) - rtw_acl_add_sta(adapter, addr); - + is_bcast = is_broadcast_mac_addr(addr); + if (is_bcast + || rtw_check_invalid_mac_address(addr, 0) == _FALSE + ) { + if (cmd_id == MAC_ACL_CMD_DEL) { + rtw_acl_remove_sta(adapter, period, addr); + if (is_bcast) + break; + } else if (!is_bcast) + rtw_acl_add_sta(adapter, period, addr); + } + c = strsep(&next, " \t"); } - } exit: @@ -1044,13 +1433,97 @@ ssize_t proc_set_pre_link_sta(struct file *file, const char __user *buffer, size } #endif /* CONFIG_RTW_PRE_LINK_STA */ +static int proc_get_ch_sel_policy(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + RTW_PRINT_SEL(m, "%-16s\n", "same_band_prefer"); + + RTW_PRINT_SEL(m, "%16u\n", rfctl->ch_sel_same_band_prefer); + + return 0; +} + +static ssize_t proc_set_ch_sel_policy(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + char tmp[32]; + u8 sb_prefer; + int num; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (!buffer || copy_from_user(tmp, buffer, count)) + goto exit; + + num = sscanf(tmp, "%hhu", &sb_prefer); + if (num >= 1) + rfctl->ch_sel_same_band_prefer = sb_prefer; + +exit: + return count; +} + #ifdef CONFIG_DFS_MASTER +static int proc_get_dfs_test_case(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + RTW_PRINT_SEL(m, "%-24s %-19s\n", "radar_detect_trigger_non", "choose_dfs_ch_first"); + RTW_PRINT_SEL(m, "%24hhu %19hhu\n" + , rfctl->dbg_dfs_radar_detect_trigger_non + , rfctl->dbg_dfs_choose_dfs_ch_first + ); + + return 0; +} + +static ssize_t proc_set_dfs_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + char tmp[32]; + u8 radar_detect_trigger_non; + u8 choose_dfs_ch_first; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%hhu %hhu", &radar_detect_trigger_non, &choose_dfs_ch_first); + + if (num >= 1) + rfctl->dbg_dfs_radar_detect_trigger_non = radar_detect_trigger_non; + if (num >= 2) + rfctl->dbg_dfs_choose_dfs_ch_first = choose_dfs_ch_first; + } + + return count; +} + ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *mlme = &adapter->mlmepriv; - struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); char tmp[32]; u8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; int ms = -1; @@ -1071,10 +1544,10 @@ ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, si goto exit; if (bw == CHANNEL_WIDTH_20) - rtw_chset_update_non_ocp_ms(mlmeext->channel_set + rtw_chset_update_non_ocp_ms(rfctl->channel_set , ch, bw, HAL_PRIME_CHNL_OFFSET_DONT_CARE, ms); else - rtw_chset_update_non_ocp_ms(mlmeext->channel_set + rtw_chset_update_non_ocp_ms(rfctl->channel_set , ch, bw, offset, ms); } @@ -1105,7 +1578,7 @@ ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size if (num < 1) goto exit; - rfctl->dbg_dfs_master_fake_radar_detect_cnt = fake_radar_detect_cnt; + rfctl->dbg_dfs_fake_radar_detect_cnt = fake_radar_detect_cnt; } exit: @@ -1144,7 +1617,7 @@ static ssize_t proc_set_dfs_ch_sel_d_flags(struct file *file, const char __user goto exit; num = sscanf(tmp, "%hhx", &d_flags); - if (num != 1) + if (num != 1) goto exit; rfctl->dfs_ch_sel_d_flags = d_flags; @@ -1152,6 +1625,54 @@ static ssize_t proc_set_dfs_ch_sel_d_flags(struct file *file, const char __user exit: return count; } + +#ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT +static int proc_get_dfs_slave_with_rd(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + RTW_PRINT_SEL(m, "%u\n", rfctl->dfs_slave_with_rd); + + return 0; +} + +static ssize_t proc_set_dfs_slave_with_rd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + char tmp[32]; + u8 rd; + int num; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (!buffer || copy_from_user(tmp, buffer, count)) + goto exit; + + num = sscanf(tmp, "%hhu", &rd); + if (num != 1) + goto exit; + + rd = rd ? 1 : 0; + + if (rfctl->dfs_slave_with_rd != rd) { + rfctl->dfs_slave_with_rd = rd; + rtw_dfs_rd_en_decision_cmd(adapter); + } + +exit: + return count; +} +#endif /* CONFIG_DFS_SLAVE_WITH_RADAR_DETECT */ #endif /* CONFIG_DFS_MASTER */ #ifdef CONFIG_80211N_HT @@ -1269,7 +1790,7 @@ static int proc_get_macid_info(struct seq_file *m, void *v) _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); - u8 chip_type = rtw_get_chip_type(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); u8 i; u8 null_addr[ETH_ALEN] = {0}; u8 *macaddr; @@ -1281,10 +1802,10 @@ static int proc_get_macid_info(struct seq_file *m, void *v) dump_macid_map(m, &macid_ctl->used, macid_ctl->num); RTW_PRINT_SEL(m, "\n"); - RTW_PRINT_SEL(m, "%-3s %-3s %-4s %-4s %-17s %-6s %-3s" - , "id", "bmc", "if_g", "ch_g", "macaddr", "bw", "vht"); + RTW_PRINT_SEL(m, "%-3s %-3s %-5s %-4s %-17s %-6s %-3s" + , "id", "bmc", "ifbmp", "ch_g", "macaddr", "bw", "vht"); - if (chip_type == RTL8814A) + if (hal_spec->tx_nss_num > 2) _RTW_PRINT_SEL(m, " %-10s", "rate_bmp1"); _RTW_PRINT_SEL(m, " %-10s %s\n", "rate_bmp0", "status"); @@ -1294,21 +1815,21 @@ static int proc_get_macid_info(struct seq_file *m, void *v) || macid_ctl->h2c_msr[i] ) { if (macid_ctl->sta[i]) - macaddr = macid_ctl->sta[i]->hwaddr; + macaddr = macid_ctl->sta[i]->cmn.mac_addr; else macaddr = null_addr; - RTW_PRINT_SEL(m, "%3u %3u %4d %4d "MAC_FMT" %6s %3u" + RTW_PRINT_SEL(m, "%3u %3u 0x%02x %4d "MAC_FMT" %6s %3u" , i , rtw_macid_is_bmc(macid_ctl, i) - , rtw_macid_get_if_g(macid_ctl, i) + , rtw_macid_get_iface_bmp(macid_ctl, i) , rtw_macid_get_ch_g(macid_ctl, i) , MAC_ARG(macaddr) , ch_width_str(macid_ctl->bw[i]) , macid_ctl->vht_en[i] ); - if (chip_type == RTL8814A) + if (hal_spec->tx_nss_num > 2) _RTW_PRINT_SEL(m, " 0x%08X", macid_ctl->rate_bmp1[i]); _RTW_PRINT_SEL(m, " 0x%08X "H2C_MSR_FMT" %s\n" @@ -1410,11 +1931,12 @@ static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *bu { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - struct mlme_priv *mlme = &(adapter->mlmepriv); - struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + int i; char tmp[32]; s16 ch; - s8 bw = -1, offset = -1; + s8 bw = REQ_BW_NONE, offset = REQ_OFFSET_NONE; + u8 ifbmp = 0; if (count < 1) return -EFAULT; @@ -1426,13 +1948,27 @@ static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *bu if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hd %hhd %hhd", &ch, &bw, &offset); + int num = sscanf(tmp, "%hd %hhd %hhd %hhx", &ch, &bw, &offset, &ifbmp); if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3)) goto exit; - if (check_fwstate(mlme, WIFI_AP_STATE) && check_fwstate(mlme, WIFI_ASOC_STATE)) - rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_WAIT_ACK, ch, bw, offset); + if (num < 4) + ifbmp = BIT(adapter->iface_id); + else + ifbmp &= (1 << dvobj->iface_nums) - 1; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (!(ifbmp & BIT(i)) || !dvobj->padapters[i]) + continue; + + if (!CHK_MLME_STATE(dvobj->padapters[i], WIFI_AP_STATE | WIFI_MESH_STATE) + || !MLME_IS_ASOC(dvobj->padapters[i])) + ifbmp &= ~BIT(i); + } + + if (ifbmp) + rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_WAIT_ACK, ifbmp, 0, ch, bw, offset); } exit: @@ -1456,7 +1992,6 @@ static ssize_t proc_set_tx_bw_mode(struct file *file, const char __user *buffer, struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; - struct mlme_priv *mlme = &(adapter->mlmepriv); struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); char tmp[32]; u8 bw_mode; @@ -1492,7 +2027,7 @@ static ssize_t proc_set_tx_bw_mode(struct file *file, const char __user *buffer, for (i = 0; i < MACID_NUM_SW_LIMIT; i++) { sta = macid_ctl->sta[i]; - if (sta && !is_broadcast_mac_addr(sta->hwaddr)) + if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) rtw_dm_ra_mask_wk_cmd(adapter, (u8 *)sta); } } @@ -1539,15 +2074,17 @@ static int proc_get_tx_power_by_rate(struct seq_file *m, void *v) return 0; } +#ifdef CONFIG_TXPWR_LIMIT static int proc_get_tx_power_limit(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - dump_tx_power_limit(m, adapter); + dump_txpwr_lmt(m, adapter); return 0; } +#endif /* CONFIG_TXPWR_LIMIT */ static int proc_get_tx_power_ext_info(struct seq_file *m, void *v) { @@ -1584,13 +2121,15 @@ static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user * #endif rtw_ps_deny(adapter, PS_DENY_IOCTL); - LeaveAllPowerSaveModeDirect(adapter); + if (rtw_pwr_wakeup(adapter) == _FALSE) + goto clear_ps_deny; if (strcmp("default", cmd) == 0) rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_default_tx_power_ext_info)), adapter); else rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_tx_power_ext_info)), adapter); +clear_ps_deny: rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); } @@ -1599,10 +2138,7 @@ static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user * static void *proc_start_tx_power_idx(struct seq_file *m, loff_t *pos) { - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); u8 path = ((*pos) & 0xFF00) >> 8; - u8 rs = *pos & 0xFF; if (path >= RF_PATH_MAX) return NULL; @@ -1611,14 +2147,10 @@ static void *proc_start_tx_power_idx(struct seq_file *m, loff_t *pos) } static void proc_stop_tx_power_idx(struct seq_file *m, void *v) { - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); } static void *proc_next_tx_power_idx(struct seq_file *m, void *v, loff_t *pos) { - struct net_device *dev = m->private; - _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); u8 path = ((*pos) & 0xFF00) >> 8; u8 rs = *pos & 0xFF; @@ -1733,10 +2265,9 @@ static ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buff { struct net_device *dev = data; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); char tmp[BB_GAIN_NUM * RF_PATH_MAX] = {0}; - u8 path, chidx; + u8 chidx; s8 bb_gain[BB_GAIN_NUM]; char ch_band_Group[6]; @@ -1848,7 +2379,6 @@ static ssize_t proc_set_tx_gain_offset(struct file *file, const char __user *buf } if (buffer && !copy_from_user(tmp, buffer, count)) { - u8 write_value; int num = sscanf(tmp, "%hhu %hhd", &rf_path, &offset); if (num < 2) @@ -2213,26 +2743,38 @@ static ssize_t proc_set_skip_band(struct file *file, const char __user *buffer, } -#ifdef CONFIG_AUTO_CHNL_SEL_NHM -static int proc_get_best_chan(struct seq_file *m, void *v) +#ifdef CONFIG_RTW_ACS +static int proc_get_chan_info(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - u8 best_24g_ch = 0, best_5g_ch = 0; - rtw_hal_get_odm_var(adapter, HAL_ODM_AUTO_CHNL_SEL, &(best_24g_ch), &(best_5g_ch)); + rtw_acs_chan_info_dump(m, adapter); + return 0; +} + +static int proc_get_best_chan(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - RTW_PRINT_SEL(m, "Best 2.4G CH:%u\n", best_24g_ch); - RTW_PRINT_SEL(m, "Best 5G CH:%u\n", best_5g_ch); + if (IS_ACS_ENABLE(adapter)) + rtw_acs_info_dump(m, adapter); + else + _RTW_PRINT_SEL(m,"ACS disabled\n"); return 0; } static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { +#ifdef CONFIG_RTW_ACS_DBG struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; - u8 acs_satae = 0; + u8 acs_state = 0; + u16 scan_ch_ms= 0, acs_scan_ch_ms = 0; + u8 scan_type = SCAN_ACTIVE, igi= 0, bw = 0; + u8 acs_scan_type = SCAN_ACTIVE, acs_igi= 0, acs_bw = 0; if (count < 1) return -EFAULT; @@ -2243,20 +2785,75 @@ static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t } if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%hhu", &acs_satae); + int num = sscanf(tmp, "%hhu %hhu %hu %hhx %hhu", + &acs_state, &scan_type, &scan_ch_ms, &igi, &bw); if (num < 1) return -EINVAL; - if (1 == acs_satae) - rtw_acs_start(padapter, _TRUE); + if (acs_state) + rtw_acs_start(padapter); else - rtw_acs_start(padapter, _FALSE); + rtw_acs_stop(padapter); + num = num -1; + + if(num) { + if (num-- > 0) + acs_scan_type = scan_type; + if (num-- > 0) + acs_scan_ch_ms = scan_ch_ms; + if (num-- > 0) + acs_igi = igi; + if (num-- > 0) + acs_bw = bw; + rtw_acs_adv_setting(padapter, acs_scan_type, acs_scan_ch_ms, acs_igi, acs_bw); + } + } +#endif /*CONFIG_RTW_ACS_DBG*/ + return count; +} +#endif /*CONFIG_RTW_ACS*/ + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +static int proc_get_nm(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_noise_info_dump(m, adapter); + return 0; +} + +static ssize_t proc_set_nm(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 nm_state = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu", &nm_state); + + if (num < 1) + return -EINVAL; + + if (nm_state) + rtw_nm_enable(padapter); + else + rtw_nm_disable(padapter); } return count; } -#endif +#endif /*CONFIG_RTW_ACS*/ static int proc_get_hal_spec(struct seq_file *m, void *v) { @@ -2273,8 +2870,10 @@ static int proc_get_phy_cap(struct seq_file *m, void *v) _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); rtw_dump_phy_cap(m, adapter); +#ifdef CONFIG_80211N_HT rtw_dump_drv_phy_cap(m, adapter); rtw_get_dft_phy_cap(m, adapter); +#endif /* CONFIG_80211N_HT */ return 0; } @@ -2324,13 +2923,13 @@ static ssize_t proc_set_rsvd_page_info(struct file *file, const char __user *buf return count; } -#if 0 /*#ifdef CONFIG_SUPPORT_FIFO_DUMP*/ +#ifdef CONFIG_SUPPORT_FIFO_DUMP static int proc_dump_fifo(struct seq_file *m, void *v) { struct net_device *dev = m->private; _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); - /*dump fifo*/ + rtw_dump_fifo(m, adapter, adapter->fifo_sel, adapter->fifo_addr, adapter->fifo_size); return 0; } static ssize_t proc_set_fifo_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) @@ -2338,7 +2937,9 @@ static ssize_t proc_set_fifo_info(struct file *file, const char __user *buffer, struct net_device *dev = data; _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; - u8 acs_satae = 0; + u8 fifo_sel = 0; + u32 fifo_addr = 0; + u32 fifo_size = 0; if (count < 3) return -EFAULT; @@ -2348,18 +2949,15 @@ static ssize_t proc_set_fifo_info(struct file *file, const char __user *buffer, return -EFAULT; } if (buffer && !copy_from_user(tmp, buffer, count)) { - /* get fifo_sel, start addr, size - int num = sscanf(tmp, "%hhu", &acs_satae); - if (num < 1) - return -EINVAL; + int num = sscanf(tmp, "%hhu %x %d", &fifo_sel, &fifo_addr, &fifo_size); - if (1 == acs_satae) - rtw_acs_start(padapter, _TRUE); - else - rtw_acs_start(padapter, _FALSE); - */ + if (num < 3) + return -EINVAL; + padapter->fifo_sel = fifo_sel; + padapter->fifo_addr = fifo_addr; + padapter->fifo_size = fifo_size; } return count; } @@ -2390,6 +2988,8 @@ static int proc_get_napi_info(struct seq_file *m, void *v) struct registry_priv *pregistrypriv = &adapter->registrypriv; u8 napi = 0, gro = 0; u32 weight = 0; + struct dvobj_priv *d; + d = adapter_to_dvobj(adapter); #ifdef CONFIG_RTW_NAPI @@ -2404,15 +3004,72 @@ static int proc_get_napi_info(struct seq_file *m, void *v) #endif /* CONFIG_RTW_GRO */ #endif /* CONFIG_RTW_NAPI */ - if (napi) + if (napi) { RTW_PRINT_SEL(m, "NAPI enable, weight=%d\n", weight); - else +#ifdef CONFIG_RTW_NAPI_DYNAMIC + RTW_PRINT_SEL(m, "Dynamaic NAPI mechanism is on, current NAPI %s\n", + d->en_napi_dynamic ? "enable" : "disable"); + RTW_PRINT_SEL(m, "Dynamaic NAPI info:\n" + "\ttcp_rx_threshold = %d Mbps\n" + "\tcur_rx_tp = %d Mbps\n", + pregistrypriv->napi_threshold, + d->traffic_stat.cur_rx_tp); +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ + } else { RTW_PRINT_SEL(m, "NAPI disable\n"); + } RTW_PRINT_SEL(m, "GRO %s\n", gro?"enable":"disable"); return 0; + } +#ifdef CONFIG_RTW_NAPI_DYNAMIC +static ssize_t proc_set_napi_th(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + struct _ADAPTER *adapter = (struct _ADAPTER *)rtw_netdev_priv(dev); + struct registry_priv *registry = &adapter->registrypriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + PADAPTER iface = NULL; + char tmp[32] = {0}; + int thrshld = 0; + int num = 0, i = 0; + + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + RTW_INFO("%s: Last threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold); + + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + if (buffer && !copy_from_user(tmp, buffer, count)) { + registry = &iface->registrypriv; + num = sscanf(tmp, "%d", &thrshld); + if (num > 0) { + if (thrshld > 0) + registry->napi_threshold = thrshld; + } + } + } + } + RTW_INFO("%s: New threshold = %d Mbps\n", __FUNCTION__, registry->napi_threshold); + RTW_INFO("%s: Current RX throughput = %d Mbps\n", + __FUNCTION__, adapter_to_dvobj(adapter)->traffic_stat.cur_rx_tp); + + return count; +} +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ + + ssize_t proc_set_dynamic_agg_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) { struct net_device *dev = data; @@ -2461,6 +3118,403 @@ static int proc_get_dynamic_agg_enable(struct seq_file *m, void *v) return 0; } +#ifdef CONFIG_RTW_MESH +static int proc_get_mesh_peer_sel_policy(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_mesh_peer_sel_policy(m, adapter); + + return 0; +} + +#if CONFIG_RTW_MESH_ACNODE_PREVENT +static int proc_get_mesh_acnode_prevent(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + dump_mesh_acnode_prevent_settings(m, adapter); + + return 0; +} + +static ssize_t proc_set_mesh_acnode_prevent(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + u8 enable; + u32 conf_timeout_ms; + u32 notify_timeout_ms; + int num = sscanf(tmp, "%hhu %u %u", &enable, &conf_timeout_ms, ¬ify_timeout_ms); + + if (num >= 1) + peer_sel_policy->acnode_prevent = enable; + if (num >= 2) + peer_sel_policy->acnode_conf_timeout_ms = conf_timeout_ms; + if (num >= 3) + peer_sel_policy->acnode_notify_timeout_ms = notify_timeout_ms; + } + +exit: + return count; +} +#endif /* CONFIG_RTW_MESH_ACNODE_PREVENT */ + +#if CONFIG_RTW_MESH_OFFCH_CAND +static int proc_get_mesh_offch_cand(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + dump_mesh_offch_cand_settings(m, adapter); + + return 0; +} + +static ssize_t proc_set_mesh_offch_cand(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + u8 enable; + u32 find_int_ms; + int num = sscanf(tmp, "%hhu %u", &enable, &find_int_ms); + + if (num >= 1) + peer_sel_policy->offch_cand = enable; + if (num >= 2) + peer_sel_policy->offch_find_int_ms = find_int_ms; + } + +exit: + return count; +} +#endif /* CONFIG_RTW_MESH_OFFCH_CAND */ + +#if CONFIG_RTW_MESH_PEER_BLACKLIST +static int proc_get_mesh_peer_blacklist(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) { + dump_mesh_peer_blacklist_settings(m, adapter); + if (MLME_IS_ASOC(adapter)) + dump_mesh_peer_blacklist(m, adapter); + } + + return 0; +} + +static ssize_t proc_set_mesh_peer_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + u32 conf_timeout_ms; + u32 blacklist_timeout_ms; + int num = sscanf(tmp, "%u %u", &conf_timeout_ms, &blacklist_timeout_ms); + + if (num >= 1) + peer_sel_policy->peer_conf_timeout_ms = conf_timeout_ms; + if (num >= 2) + peer_sel_policy->peer_blacklist_timeout_ms = blacklist_timeout_ms; + } + +exit: + return count; +} +#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */ + +#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST +static int proc_get_mesh_cto_mgate_require(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + RTW_PRINT_SEL(m, "%u\n", adapter->mesh_cfg.peer_sel_policy.cto_mgate_require); + + return 0; +} + +static ssize_t proc_set_mesh_cto_mgate_require(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + u8 require; + int num = sscanf(tmp, "%hhu", &require); + + if (num >= 1) { + peer_sel_policy->cto_mgate_require = require; + #if CONFIG_RTW_MESH_CTO_MGATE_CARRIER + if (rtw_mesh_cto_mgate_required(adapter)) + rtw_netif_carrier_off(adapter->pnetdev); + else + rtw_netif_carrier_on(adapter->pnetdev); + #endif + } + } + +exit: + return count; +} + +static int proc_get_mesh_cto_mgate_blacklist(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) { + dump_mesh_cto_mgate_blacklist_settings(m, adapter); + if (MLME_IS_ASOC(adapter)) + dump_mesh_cto_mgate_blacklist(m, adapter); + } + + return 0; +} + +static ssize_t proc_set_mesh_cto_mgate_blacklist(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy; + u32 conf_timeout_ms; + u32 blacklist_timeout_ms; + int num = sscanf(tmp, "%u %u", &conf_timeout_ms, &blacklist_timeout_ms); + + if (num >= 1) + peer_sel_policy->cto_mgate_conf_timeout_ms = conf_timeout_ms; + if (num >= 2) + peer_sel_policy->cto_mgate_blacklist_timeout_ms = blacklist_timeout_ms; + } + +exit: + return count; +} +#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */ + +static int proc_get_mesh_networks(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_mesh_networks(m, adapter); + + return 0; +} + +static int proc_get_mesh_plink_ctl(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + dump_mesh_plink_ctl(m, adapter); + + return 0; +} + +static int proc_get_mesh_mpp(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) + dump_mpp(m, adapter); + + return 0; +} + +static int proc_get_mesh_known_gates(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + dump_known_gates(m, adapter); + + return 0; +} + +#if CONFIG_RTW_MESH_DATA_BMC_TO_UC +static int proc_get_mesh_b2u_flags(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + dump_mesh_b2u_flags(m, adapter); + + return 0; +} + +static ssize_t proc_set_mesh_b2u_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + u8 msrc, mfwd; + int num = sscanf(tmp, "%hhx %hhx", &msrc, &mfwd); + + if (num >= 1) + mcfg->b2u_flags_msrc = msrc; + if (num >= 2) + mcfg->b2u_flags_mfwd = mfwd; + } + +exit: + return count; +} +#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */ + +static int proc_get_mesh_stats(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + dump_mesh_stats(m, adapter); + + return 0; +} + +static int proc_get_mesh_gate_timeout(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (MLME_IS_MESH(adapter)) + RTW_PRINT_SEL(m, "%u factor\n", + adapter->mesh_cfg.path_gate_timeout_factor); + + return 0; +} + +static ssize_t proc_set_mesh_gate_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + u32 timeout; + int num = sscanf(tmp, "%u", &timeout); + + if (num < 1) + goto exit; + + mcfg->path_gate_timeout_factor = timeout; + } + +exit: + return count; +} + +static int proc_get_mesh_gate_state(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg; + u8 cto_mgate = 0; + + if (MLME_IS_MESH(adapter)) { + if (rtw_mesh_is_primary_gate(adapter)) + RTW_PRINT_SEL(m, "PG\n"); + else if (mcfg->dot11MeshGateAnnouncementProtocol) + RTW_PRINT_SEL(m, "G\n"); + else if (rtw_mesh_gate_num(adapter)) + RTW_PRINT_SEL(m, "C\n"); + else + RTW_PRINT_SEL(m, "N\n"); + } + + return 0; +} + +#endif /* CONFIG_RTW_MESH */ + /* * rtw_adapter_proc: * init/deinit when register/unregister net_device @@ -2486,15 +3540,25 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("scan_abort", proc_get_scan_abort, NULL), #ifdef CONFIG_SCAN_BACKOP RTW_PROC_HDL_SSEQ("backop_flags_sta", proc_get_backop_flags_sta, proc_set_backop_flags_sta), + #ifdef CONFIG_AP_MODE RTW_PROC_HDL_SSEQ("backop_flags_ap", proc_get_backop_flags_ap, proc_set_backop_flags_ap), + #endif + #ifdef CONFIG_RTW_MESH + RTW_PROC_HDL_SSEQ("backop_flags_mesh", proc_get_backop_flags_mesh, proc_set_backop_flags_mesh), + #endif +#endif +#ifdef CONFIG_RTW_REPEATER_SON + RTW_PROC_HDL_SSEQ("rson_data", proc_get_rson_data, proc_set_rson_data), #endif RTW_PROC_HDL_SSEQ("survey_info", proc_get_survey_info, proc_set_survey_info), RTW_PROC_HDL_SSEQ("ap_info", proc_get_ap_info, NULL), +#ifdef ROKU_PRIVATE + RTW_PROC_HDL_SSEQ("infra_ap", proc_get_infra_ap, NULL), +#endif /* ROKU_PRIVATE */ RTW_PROC_HDL_SSEQ("trx_info", proc_get_trx_info, proc_reset_trx_info), RTW_PROC_HDL_SSEQ("tx_power_offset", proc_get_tx_power_offset, proc_set_tx_power_offset), RTW_PROC_HDL_SSEQ("rate_ctl", proc_get_rate_ctl, proc_set_rate_ctl), RTW_PROC_HDL_SSEQ("bw_ctl", proc_get_bw_ctl, proc_set_bw_ctl), - RTW_PROC_HDL_SSEQ("dis_pwt_ctl", proc_get_dis_pwt, proc_set_dis_pwt), RTW_PROC_HDL_SSEQ("mac_qinfo", proc_get_mac_qinfo, NULL), RTW_PROC_HDL_SSEQ("macid_info", proc_get_macid_info, NULL), RTW_PROC_HDL_SSEQ("bcmc_info", proc_get_mi_ap_bc_info, NULL), @@ -2522,14 +3586,23 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("del_rx_ampdu_test_case", NULL, proc_set_del_rx_ampdu_test_case), RTW_PROC_HDL_SSEQ("wait_hiq_empty", NULL, proc_set_wait_hiq_empty), RTW_PROC_HDL_SSEQ("sta_linking_test", NULL, proc_set_sta_linking_test), +#ifdef CONFIG_AP_MODE + RTW_PROC_HDL_SSEQ("ap_linking_test", NULL, proc_set_ap_linking_test), +#endif RTW_PROC_HDL_SSEQ("mac_reg_dump", proc_get_mac_reg_dump, NULL), RTW_PROC_HDL_SSEQ("bb_reg_dump", proc_get_bb_reg_dump, NULL), RTW_PROC_HDL_SSEQ("bb_reg_dump_ex", proc_get_bb_reg_dump_ex, NULL), RTW_PROC_HDL_SSEQ("rf_reg_dump", proc_get_rf_reg_dump, NULL), +#ifdef CONFIG_RTW_LED + RTW_PROC_HDL_SSEQ("led_config", proc_get_led_config, proc_set_led_config), +#endif + #ifdef CONFIG_AP_MODE + RTW_PROC_HDL_SSEQ("aid_status", proc_get_aid_status, proc_set_aid_status), RTW_PROC_HDL_SSEQ("all_sta_info", proc_get_all_sta_info, NULL), + RTW_PROC_HDL_SSEQ("bmc_tx_rate", proc_get_bmc_tx_rate, proc_set_bmc_tx_rate), #endif /* CONFIG_AP_MODE */ #ifdef DBG_MEMORY_LEAK @@ -2542,7 +3615,7 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("rx_signal", proc_get_rx_signal, proc_set_rx_signal), RTW_PROC_HDL_SSEQ("hw_info", proc_get_hw_status, proc_set_hw_status), - + RTW_PROC_HDL_SSEQ("mac_rptbuf", proc_get_mac_rptbuf, NULL), #ifdef CONFIG_80211N_HT RTW_PROC_HDL_SSEQ("ht_enable", proc_get_ht_enable, proc_set_ht_enable), RTW_PROC_HDL_SSEQ("bw_mode", proc_get_bw_mode, proc_set_bw_mode), @@ -2552,15 +3625,14 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("rx_ampdu_factor", proc_get_rx_ampdu_factor, proc_set_rx_ampdu_factor), RTW_PROC_HDL_SSEQ("rx_ampdu_density", proc_get_rx_ampdu_density, proc_set_rx_ampdu_density), RTW_PROC_HDL_SSEQ("tx_ampdu_density", proc_get_tx_ampdu_density, proc_set_tx_ampdu_density), + RTW_PROC_HDL_SSEQ("tx_max_agg_num", proc_get_tx_max_agg_num, proc_set_tx_max_agg_num), #ifdef CONFIG_TX_AMSDU RTW_PROC_HDL_SSEQ("tx_amsdu", proc_get_tx_amsdu, proc_set_tx_amsdu), RTW_PROC_HDL_SSEQ("tx_amsdu_rate", proc_get_tx_amsdu_rate, proc_set_tx_amsdu_rate), #endif #endif /* CONFIG_80211N_HT */ - RTW_PROC_HDL_SSEQ("tx_max_agg_num", proc_get_tx_max_agg_num, proc_set_tx_max_agg_num), RTW_PROC_HDL_SSEQ("en_fwps", proc_get_en_fwps, proc_set_en_fwps), - RTW_PROC_HDL_SSEQ("mac_rptbuf", proc_get_mac_rptbuf, NULL), /* RTW_PROC_HDL_SSEQ("path_rssi", proc_get_two_path_rssi, NULL), * RTW_PROC_HDL_SSEQ("rssi_disp",proc_get_rssi_disp, proc_set_rssi_disp), */ @@ -2580,10 +3652,17 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("sreset", proc_get_sreset, proc_set_sreset), #endif /* DBG_CONFIG_ERROR_DETECT */ RTW_PROC_HDL_SSEQ("trx_info_debug", proc_get_trx_info_debug, NULL), + +#ifdef CONFIG_HUAWEI_PROC + RTW_PROC_HDL_SSEQ("huawei_trx_info", proc_get_huawei_trx_info, NULL), +#endif RTW_PROC_HDL_SSEQ("linked_info_dump", proc_get_linked_info_dump, proc_set_linked_info_dump), + RTW_PROC_HDL_SSEQ("sta_tp_dump", proc_get_sta_tp_dump, proc_set_sta_tp_dump), + RTW_PROC_HDL_SSEQ("sta_tp_info", proc_get_sta_tp_info, NULL), RTW_PROC_HDL_SSEQ("dis_turboedca", proc_get_turboedca_ctrl, proc_set_turboedca_ctrl), RTW_PROC_HDL_SSEQ("tx_info_msg", proc_get_tx_info_msg, NULL), RTW_PROC_HDL_SSEQ("rx_info_msg", proc_get_rx_info_msg, proc_set_rx_info_msg), + #ifdef CONFIG_GPIO_API RTW_PROC_HDL_SSEQ("gpio_info", proc_get_gpio, proc_set_gpio), RTW_PROC_HDL_SSEQ("gpio_set_output_value", NULL, proc_set_gpio_output_value), @@ -2596,18 +3675,34 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("int_logs", proc_get_int_logs, NULL), #endif +#ifdef CONFIG_DBG_RF_CAL + RTW_PROC_HDL_SSEQ("iqk", proc_get_iqk_info, proc_set_iqk), + RTW_PROC_HDL_SSEQ("lck", proc_get_lck_info, proc_set_lck), +#endif + #ifdef CONFIG_PCI_HCI RTW_PROC_HDL_SSEQ("rx_ring", proc_get_rx_ring, NULL), RTW_PROC_HDL_SSEQ("tx_ring", proc_get_tx_ring, NULL), +#ifdef DBG_TXBD_DESC_DUMP + RTW_PROC_HDL_SSEQ("tx_ring_ext", proc_get_tx_ring_ext, proc_set_tx_ring_ext), +#endif RTW_PROC_HDL_SSEQ("pci_aspm", proc_get_pci_aspm, NULL), + + RTW_PROC_HDL_SSEQ("pci_conf_space", proc_get_pci_conf_space, proc_set_pci_conf_space), + + RTW_PROC_HDL_SSEQ("pci_bridge_conf_space", proc_get_pci_bridge_conf_space, proc_set_pci_bridge_conf_space), + #endif #ifdef CONFIG_WOWLAN RTW_PROC_HDL_SSEQ("wow_pattern_info", proc_get_pattern_info, proc_set_pattern_info), + RTW_PROC_HDL_SSEQ("wow_wakeup_event", proc_get_wakeup_event, + proc_set_wakeup_event), RTW_PROC_HDL_SSEQ("wowlan_last_wake_reason", proc_get_wakeup_reason, NULL), #ifdef CONFIG_WOW_PATTERN_HW_CAM RTW_PROC_HDL_SSEQ("wow_pattern_cam", proc_dump_pattern_cam, NULL), #endif + RTW_PROC_HDL_SSEQ("dis_wow_lps", proc_get_wow_lps_ctrl, proc_set_wow_lps_ctrl), #endif #ifdef CONFIG_GPIO_WAKEUP @@ -2624,13 +3719,19 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #if CONFIG_RTW_PRE_LINK_STA RTW_PROC_HDL_SSEQ("pre_link_sta", proc_get_pre_link_sta, proc_set_pre_link_sta), #endif + RTW_PROC_HDL_SSEQ("ch_sel_policy", proc_get_ch_sel_policy, proc_set_ch_sel_policy), #ifdef CONFIG_DFS_MASTER - RTW_PROC_HDL_SSEQ("dfs_master_test_case", proc_get_dfs_master_test_case, proc_set_dfs_master_test_case), + RTW_PROC_HDL_SSEQ("dfs_test_case", proc_get_dfs_test_case, proc_set_dfs_test_case), RTW_PROC_HDL_SSEQ("update_non_ocp", NULL, proc_set_update_non_ocp), RTW_PROC_HDL_SSEQ("radar_detect", NULL, proc_set_radar_detect), RTW_PROC_HDL_SSEQ("dfs_ch_sel_d_flags", proc_get_dfs_ch_sel_d_flags, proc_set_dfs_ch_sel_d_flags), + #ifdef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT + RTW_PROC_HDL_SSEQ("dfs_slave_with_rd", proc_get_dfs_slave_with_rd, proc_set_dfs_slave_with_rd), + #endif #endif +#ifdef CONFIG_BCN_CNT_CONFIRM_HDL RTW_PROC_HDL_SSEQ("new_bcn_max", proc_get_new_bcn_max, proc_set_new_bcn_max), +#endif RTW_PROC_HDL_SSEQ("sink_udpport", proc_get_udpport, proc_set_udpport), #ifdef DBG_RX_COUNTER_DUMP RTW_PROC_HDL_SSEQ("dump_rx_cnt_mode", proc_get_rx_cnt_dump, proc_set_rx_cnt_dump), @@ -2640,7 +3741,9 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("hal_txpwr_info", proc_get_hal_txpwr_info, NULL), RTW_PROC_HDL_SSEQ("target_tx_power", proc_get_target_tx_power, NULL), RTW_PROC_HDL_SSEQ("tx_power_by_rate", proc_get_tx_power_by_rate, NULL), +#ifdef CONFIG_TXPWR_LIMIT RTW_PROC_HDL_SSEQ("tx_power_limit", proc_get_tx_power_limit, NULL), +#endif RTW_PROC_HDL_SSEQ("tx_power_ext_info", proc_get_tx_power_ext_info, proc_set_tx_power_ext_info), RTW_PROC_HDL_SEQ("tx_power_idx", &seq_ops_tx_power_idx, NULL), #ifdef CONFIG_RF_POWER_TRIM @@ -2651,15 +3754,25 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { #endif #ifdef CONFIG_POWER_SAVING RTW_PROC_HDL_SSEQ("ps_info", proc_get_ps_info, NULL), +#ifdef CONFIG_WMMPS_STA + RTW_PROC_HDL_SSEQ("wmmps_info", proc_get_wmmps_info, proc_set_wmmps_info), +#endif /* CONFIG_WMMPS_STA */ #endif #ifdef CONFIG_TDLS RTW_PROC_HDL_SSEQ("tdls_info", proc_get_tdls_info, NULL), + RTW_PROC_HDL_SSEQ("tdls_enable", proc_get_tdls_enable, proc_set_tdls_enable), #endif RTW_PROC_HDL_SSEQ("monitor", proc_get_monitor, proc_set_monitor), -#ifdef CONFIG_AUTO_CHNL_SEL_NHM +#ifdef CONFIG_RTW_ACS RTW_PROC_HDL_SSEQ("acs", proc_get_best_chan, proc_set_acs), + RTW_PROC_HDL_SSEQ("chan_info", proc_get_chan_info, NULL), +#endif + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + RTW_PROC_HDL_SSEQ("noise_monitor", proc_get_nm, proc_set_nm), #endif + #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER RTW_PROC_HDL_SSEQ("rtkm_info", proc_get_rtkm_info, NULL), #endif @@ -2682,10 +3795,11 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("tx_stat", proc_get_tx_stat, NULL), /**** PHY Capability ****/ RTW_PROC_HDL_SSEQ("phy_cap", proc_get_phy_cap, NULL), - +#ifdef CONFIG_80211N_HT RTW_PROC_HDL_SSEQ("rx_stbc", proc_get_rx_stbc, proc_set_rx_stbc), RTW_PROC_HDL_SSEQ("stbc_cap", proc_get_stbc_cap, proc_set_stbc_cap), RTW_PROC_HDL_SSEQ("ldpc_cap", proc_get_ldpc_cap, proc_set_ldpc_cap), +#endif /* CONFIG_80211N_HT */ #ifdef CONFIG_BEAMFORMING RTW_PROC_HDL_SSEQ("txbf_cap", proc_get_txbf_cap, proc_set_txbf_cap), #endif @@ -2694,22 +3808,58 @@ const struct rtw_proc_hdl adapter_proc_hdls[] = { RTW_PROC_HDL_SSEQ("trx_share_mode", proc_get_trx_share_mode, NULL), #endif RTW_PROC_HDL_SSEQ("napi_info", proc_get_napi_info, NULL), +#ifdef CONFIG_RTW_NAPI_DYNAMIC + RTW_PROC_HDL_SSEQ("napi_th", proc_get_napi_info, proc_set_napi_th), +#endif /* CONFIG_RTW_NAPI_DYNAMIC */ + RTW_PROC_HDL_SSEQ("rsvd_page", proc_dump_rsvd_page, proc_set_rsvd_page_info), -#if 0 /*def CONFIG_SUPPORT_FIFO_DUMP*/ - /*RTW_PROC_HDL_SSEQ("fifo_dump", proc_dump_fifo, proc_set_fifo_info),*/ +#ifdef CONFIG_SUPPORT_FIFO_DUMP + RTW_PROC_HDL_SSEQ("fifo_dump", proc_dump_fifo, proc_set_fifo_info), #endif RTW_PROC_HDL_SSEQ("fw_info", proc_get_fw_info, NULL), -#ifdef RTW_HALMAC - RTW_PROC_HDL_SSEQ("halmac_info", proc_get_halmac_info, NULL), -#endif #ifdef DBG_XMIT_BLOCK RTW_PROC_HDL_SSEQ("xmit_block", proc_get_xmit_block, proc_set_xmit_block), #endif RTW_PROC_HDL_SSEQ("ack_timeout", proc_get_ack_timeout, proc_set_ack_timeout), + RTW_PROC_HDL_SSEQ("dynamic_agg_enable", proc_get_dynamic_agg_enable, proc_set_dynamic_agg_enable), + RTW_PROC_HDL_SSEQ("fw_offload", proc_get_fw_offload, proc_set_fw_offload), + +#ifdef CONFIG_RTW_MESH + #if CONFIG_RTW_MESH_ACNODE_PREVENT + RTW_PROC_HDL_SSEQ("mesh_acnode_prevent", proc_get_mesh_acnode_prevent, proc_set_mesh_acnode_prevent), + #endif + #if CONFIG_RTW_MESH_OFFCH_CAND + RTW_PROC_HDL_SSEQ("mesh_offch_cand", proc_get_mesh_offch_cand, proc_set_mesh_offch_cand), + #endif + #if CONFIG_RTW_MESH_PEER_BLACKLIST + RTW_PROC_HDL_SSEQ("mesh_peer_blacklist", proc_get_mesh_peer_blacklist, proc_set_mesh_peer_blacklist), + #endif + #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST + RTW_PROC_HDL_SSEQ("mesh_cto_mgate_require", proc_get_mesh_cto_mgate_require, proc_set_mesh_cto_mgate_require), + RTW_PROC_HDL_SSEQ("mesh_cto_mgate_blacklist", proc_get_mesh_cto_mgate_blacklist, proc_set_mesh_cto_mgate_blacklist), + #endif + RTW_PROC_HDL_SSEQ("mesh_peer_sel_policy", proc_get_mesh_peer_sel_policy, NULL), + RTW_PROC_HDL_SSEQ("mesh_networks", proc_get_mesh_networks, NULL), + RTW_PROC_HDL_SSEQ("mesh_plink_ctl", proc_get_mesh_plink_ctl, NULL), + RTW_PROC_HDL_SSEQ("mesh_mpp", proc_get_mesh_mpp, NULL), + RTW_PROC_HDL_SSEQ("mesh_known_gates", proc_get_mesh_known_gates, NULL), + #if CONFIG_RTW_MESH_DATA_BMC_TO_UC + RTW_PROC_HDL_SSEQ("mesh_b2u_flags", proc_get_mesh_b2u_flags, proc_set_mesh_b2u_flags), + #endif + RTW_PROC_HDL_SSEQ("mesh_stats", proc_get_mesh_stats, NULL), + RTW_PROC_HDL_SSEQ("mesh_gate_timeout_factor", proc_get_mesh_gate_timeout, proc_set_mesh_gate_timeout), + RTW_PROC_HDL_SSEQ("mesh_gate_state", proc_get_mesh_gate_state, NULL), +#endif +#ifdef CONFIG_FW_HANDLE_TXBCN + RTW_PROC_HDL_SSEQ("fw_tbtt_rpt", proc_get_fw_tbtt_rpt, proc_set_fw_tbtt_rpt), +#endif +#ifdef CONFIG_LPS_CHK_BY_TP + RTW_PROC_HDL_SSEQ("lps_chk_tp", proc_get_lps_chk_tp, proc_set_lps_chk_tp), +#endif }; @@ -2767,45 +3917,6 @@ static const struct file_operations rtw_adapter_proc_sseq_fops = { .write = rtw_adapter_proc_write, }; - -int proc_get_odm_force_igi_lb(struct seq_file *m, void *v) -{ - struct net_device *dev = m->private; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - - RTW_PRINT_SEL(m, "force_igi_lb:0x%02x\n", rtw_odm_get_force_igi_lb(padapter)); - - return 0; -} - -ssize_t proc_set_odm_force_igi_lb(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) -{ - struct net_device *dev = data; - _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); - char tmp[32]; - u8 force_igi_lb; - - if (count < 1) - return -EFAULT; - - if (count > sizeof(tmp)) { - rtw_warn_on(1); - return -EFAULT; - } - - if (buffer && !copy_from_user(tmp, buffer, count)) { - - int num = sscanf(tmp, "%hhx", &force_igi_lb); - - if (num != 1) - return count; - - rtw_odm_set_force_igi_lb(padapter, force_igi_lb); - } - - return count; -} - int proc_get_odm_adaptivity(struct seq_file *m, void *v) { struct net_device *dev = m->private; @@ -2822,10 +3933,7 @@ ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, si _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); char tmp[32]; u32 th_l2h_ini; - u32 th_l2h_ini_mode2; s8 th_edcca_hl_diff; - s8 th_edcca_hl_diff_mode2; - u8 edcca_enable; if (count < 1) return -EFAULT; @@ -2837,12 +3945,12 @@ ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, si if (buffer && !copy_from_user(tmp, buffer, count)) { - int num = sscanf(tmp, "%x %hhd %x %hhd %hhu", &th_l2h_ini, &th_edcca_hl_diff, &th_l2h_ini_mode2, &th_edcca_hl_diff_mode2, &edcca_enable); + int num = sscanf(tmp, "%x %hhd", &th_l2h_ini, &th_edcca_hl_diff); - if (num != 5) + if (num != 2) return count; - rtw_odm_adaptivity_parm_set(padapter, (s8)th_l2h_ini, th_edcca_hl_diff, (s8)th_l2h_ini_mode2, th_edcca_hl_diff_mode2, edcca_enable); + rtw_odm_adaptivity_parm_set(padapter, (s8)th_l2h_ini, th_edcca_hl_diff); } return count; @@ -2855,14 +3963,12 @@ int proc_get_phydm_cmd(struct seq_file *m, void *v) { struct net_device *netdev; PADAPTER padapter; - PHAL_DATA_TYPE pHalData; - struct PHY_DM_STRUCT *phydm; + struct dm_struct *phydm; netdev = m->private; padapter = (PADAPTER)rtw_netdev_priv(netdev); - pHalData = GET_HAL_DATA(padapter); - phydm = &pHalData->odmpriv; + phydm = adapter_to_phydm(padapter); if (NULL == phydm_msg) { phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN); @@ -2884,15 +3990,13 @@ ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t { struct net_device *netdev; PADAPTER padapter; - PHAL_DATA_TYPE pHalData; - struct PHY_DM_STRUCT *phydm; + struct dm_struct *phydm; char tmp[64] = {0}; netdev = (struct net_device *)data; padapter = (PADAPTER)rtw_netdev_priv(netdev); - pHalData = GET_HAL_DATA(padapter); - phydm = &pHalData->odmpriv; + phydm = adapter_to_phydm(padapter); if (count < 1) return -EFAULT; @@ -2919,97 +4023,13 @@ ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t return count; } -#ifdef CONFIG_LAMODE -static void *proc_start_lamode_dump(struct seq_file *m, loff_t *pos) -{ - _adapter *adapter = (_adapter *)rtw_netdev_priv(m->private); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp); - static unsigned long index; - static unsigned long max; - - - if (*pos == 0) { - rtw_pm_set_ips(adapter, IPS_NONE); - rtw_pm_set_lps(adapter, PS_MODE_ACTIVE); - ADCSmp_Start(pDM_Odm, AdcSmp); - index = 0; - *pos = max = ADCSmp_Get_SampleCounts(pDM_Odm); - if (max == 0) - return NULL; - } else if (index >= max) { - return NULL; - } - - return &index; -} - -static void proc_stop_lamode_dump(struct seq_file *m, void *v) -{ - /* v is a NULL in kernel 3.19.0-25 */ -} - -static void *proc_next_lamode_dump(struct seq_file *m, void *v, loff_t *pos) -{ - _adapter *adapter = (_adapter *)rtw_netdev_priv(m->private); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - unsigned long *index = v; - - - *index += 2; - if (*index >= *pos) { - ADCSmp_DeInit(pDM_Odm); - if (phydm_msg) { - _RTW_PRINT_SEL(m, "%s", phydm_msg); - rtw_mfree(phydm_msg, PHYDM_MSG_LEN); - phydm_msg = NULL; - } - return NULL; - } - return index; -} - -static int proc_show_lamode_data(struct seq_file *m, void *v) -{ - _adapter *adapter = (_adapter *)rtw_netdev_priv(m->private); - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); - struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; - unsigned long *index = v; - char line[32]; - int rtn; - - - memset(line, 0, sizeof(line)); - rtn = ADCSmp_Query_SingleData(pDM_Odm, line, sizeof(line), *index); - _RTW_PRINT_SEL(m, "%s", line); - - if (rtn<0) - return -1; - - return 0; -} - -static struct seq_operations seq_ops_lamode = { - .start = proc_start_lamode_dump, - .stop = proc_stop_lamode_dump, - .next = proc_next_lamode_dump, - .show = proc_show_lamode_data, -}; -#endif /* CONFIG_LAMODE */ - /* * rtw_odm_proc: * init/deinit when register/unregister net_device, along with rtw_adapter_proc */ const struct rtw_proc_hdl odm_proc_hdls[] = { RTW_PROC_HDL_SSEQ("adaptivity", proc_get_odm_adaptivity, proc_set_odm_adaptivity), - RTW_PROC_HDL_SSEQ("force_igi_lb", proc_get_odm_force_igi_lb, proc_set_odm_force_igi_lb), RTW_PROC_HDL_SSEQ("cmd", proc_get_phydm_cmd, proc_set_phydm_cmd), -#ifdef CONFIG_LAMODE - RTW_PROC_HDL_SEQ("lamode", &seq_ops_lamode, proc_set_phydm_cmd) -#endif /* CONFIG_LAMODE */ }; const int odm_proc_hdls_num = sizeof(odm_proc_hdls) / sizeof(struct rtw_proc_hdl); @@ -3142,6 +4162,7 @@ void rtw_odm_proc_deinit(_adapter *adapter) const struct rtw_proc_hdl mcc_proc_hdls[] = { RTW_PROC_HDL_SSEQ("mcc_info", proc_get_mcc_info, NULL), RTW_PROC_HDL_SSEQ("mcc_enable", proc_get_mcc_info, proc_set_mcc_enable), + RTW_PROC_HDL_SSEQ("mcc_duration", proc_get_mcc_info, proc_set_mcc_duration), RTW_PROC_HDL_SSEQ("mcc_single_tx_criteria", proc_get_mcc_info, proc_set_mcc_single_tx_criteria), RTW_PROC_HDL_SSEQ("mcc_ap_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw20_target_tp), RTW_PROC_HDL_SSEQ("mcc_ap_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_ap_bw40_target_tp), @@ -3149,7 +4170,7 @@ const struct rtw_proc_hdl mcc_proc_hdls[] = { RTW_PROC_HDL_SSEQ("mcc_sta_bw20_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw20_target_tp), RTW_PROC_HDL_SSEQ("mcc_sta_bw40_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw40_target_tp), RTW_PROC_HDL_SSEQ("mcc_sta_bw80_target_tp", proc_get_mcc_info, proc_set_mcc_sta_bw80_target_tp), - RTW_PROC_HDL_SSEQ("mcc_policy_table", proc_get_mcc_policy_table, proc_set_mcc_policy_table), + RTW_PROC_HDL_SSEQ("mcc_policy_table", proc_get_mcc_policy_table, NULL), }; const int mcc_proc_hdls_num = sizeof(mcc_proc_hdls) / sizeof(struct rtw_proc_hdl); @@ -3276,7 +4297,6 @@ struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) struct proc_dir_entry *dir_dev = NULL; struct proc_dir_entry *entry = NULL; _adapter *adapter = rtw_netdev_priv(dev); - u8 rf_type; ssize_t i; if (drv_proc == NULL) { diff --git a/os_dep/linux/rtw_proc.h b/os_dep/linux/rtw_proc.h index 0ab929c..c2c7c8e 100644 --- a/os_dep/linux/rtw_proc.h +++ b/os_dep/linux/rtw_proc.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __RTW_PROC_H__ #define __RTW_PROC_H__ diff --git a/os_dep/linux/rtw_rhashtable.c b/os_dep/linux/rtw_rhashtable.c new file mode 100644 index 0000000..4d51f04 --- /dev/null +++ b/os_dep/linux/rtw_rhashtable.c @@ -0,0 +1,74 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifdef CONFIG_RTW_MESH /* for now, only promised for kernel versions we support mesh */ + +#include + +int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) + return rhashtable_walk_init((ht), (iter), GFP_ATOMIC); +#else + /* kernel >= 4.4.0 rhashtable_walk_init use GFP_KERNEL to alloc, spin_lock for assignment */ + iter->ht = ht; + iter->p = NULL; + iter->slot = 0; + iter->skip = 0; + + iter->walker = kmalloc(sizeof(*iter->walker), GFP_ATOMIC); + if (!iter->walker) + return -ENOMEM; + + spin_lock(&ht->lock); + iter->walker->tbl = + rcu_dereference_protected(ht->tbl, lockdep_is_held(&ht->lock)); + list_add(&iter->walker->list, &iter->walker->tbl->walkers); + spin_unlock(&ht->lock); + + return 0; +#endif +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) +static inline int is_vmalloc_addr(const void *x) +{ +#ifdef CONFIG_MMU + unsigned long addr = (unsigned long)x; + + return addr >= VMALLOC_START && addr < VMALLOC_END; +#else + return 0; +#endif +} +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) */ + +void kvfree(const void *addr) +{ + if (is_vmalloc_addr(addr)) + vfree(addr); + else + kfree(addr); +} +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) */ + +#include "rhashtable.c" + +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */ + +#endif /* CONFIG_RTW_MESH */ + diff --git a/os_dep/linux/rtw_rhashtable.h b/os_dep/linux/rtw_rhashtable.h new file mode 100644 index 0000000..567ab39 --- /dev/null +++ b/os_dep/linux/rtw_rhashtable.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __RTW_RHASHTABLE_H__ +#define __RTW_RHASHTABLE_H__ + +#ifdef CONFIG_RTW_MESH /* for now, only promised for kernel versions we support mesh */ + +/* directly reference rhashtable in kernel */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) +#include +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) */ + +/* Use rhashtable from kernel 4.4 */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) +#define NULLS_MARKER(value) (1UL | (((long)value) << 1)) +#endif +#include "rhashtable.h" +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)) */ + +typedef struct rhashtable rtw_rhashtable; +typedef struct rhash_head rtw_rhash_head; +typedef struct rhashtable_params rtw_rhashtable_params; + +#define rtw_rhashtable_init(ht, params) rhashtable_init(ht, params) + +typedef struct rhashtable_iter rtw_rhashtable_iter; + +int rtw_rhashtable_walk_enter(rtw_rhashtable *ht, rtw_rhashtable_iter *iter); +#define rtw_rhashtable_walk_exit(iter) rhashtable_walk_exit(iter) +#define rtw_rhashtable_walk_start(iter) rhashtable_walk_start(iter) +#define rtw_rhashtable_walk_next(iter) rhashtable_walk_next(iter) +#define rtw_rhashtable_walk_stop(iter) rhashtable_walk_stop(iter) + +#define rtw_rhashtable_free_and_destroy(ht, free_fn, arg) rhashtable_free_and_destroy((ht), (free_fn), (arg)) +#define rtw_rhashtable_lookup_fast(ht, key, params) rhashtable_lookup_fast((ht), (key), (params)) +#define rtw_rhashtable_lookup_insert_fast(ht, obj, params) rhashtable_lookup_insert_fast((ht), (obj), (params)) +#define rtw_rhashtable_remove_fast(ht, obj, params) rhashtable_remove_fast((ht), (obj), (params)) + +#endif /* CONFIG_RTW_MESH */ + +#endif /* __RTW_RHASHTABLE_H__ */ + diff --git a/os_dep/linux/wifi_regd.c b/os_dep/linux/wifi_regd.c index 601ecff..4c10f84 100644 --- a/os_dep/linux/wifi_regd.c +++ b/os_dep/linux/wifi_regd.c @@ -1,6 +1,15 @@ /****************************************************************************** * - * Copyright(c) 2009-2010 Realtek Corporation. + * Copyright(c) 2009-2010 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. * *****************************************************************************/ @@ -146,7 +155,7 @@ static void _rtw_reg_apply_beaconing_flags(struct wiphy *wiphy, u32 bandwidth = 0; int r; - for (band = 0; band < IEEE80211_NUM_BANDS; band++) { + for (band = 0; band < NUM_NL80211_BANDS; band++) { if (!wiphy->bands[band]) continue; @@ -243,68 +252,12 @@ static void _rtw_reg_apply_active_scan_flags(struct wiphy *wiphy, } #endif -/* - * Always apply Radar/DFS rules on - * freq range 5260 MHz - 5700 MHz - */ -static void _rtw_reg_apply_radar_flags(struct wiphy *wiphy) -{ - struct ieee80211_supported_band *sband; - struct ieee80211_channel *ch; - unsigned int i; - - if (!wiphy->bands[NL80211_BAND_5GHZ]) - return; - - sband = wiphy->bands[NL80211_BAND_5GHZ]; - - for (i = 0; i < sband->n_channels; i++) { - ch = &sband->channels[i]; - if (!rtw_is_dfs_ch(ch->hw_value)) - continue; -#ifdef CONFIG_DFS - if (!(ch->flags & IEEE80211_CHAN_DISABLED) - #if defined(CONFIG_DFS_MASTER) - && rtw_odm_dfs_domain_unknown(wiphy_to_adapter(wiphy)) - #endif - ) { - ch->flags |= IEEE80211_CHAN_RADAR; - #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) - ch->flags |= (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); - #else - ch->flags |= IEEE80211_CHAN_NO_IR; - #endif - } -#endif /* CONFIG_DFS */ - -#if 0 - /* - * We always enable radar detection/DFS on this - * frequency range. Additionally we also apply on - * this frequency range: - * - If STA mode does not yet have DFS supports disable - * active scanning - * - If adhoc mode does not support DFS yet then disable - * adhoc in the frequency. - * - If AP mode does not yet support radar detection/DFS - * do not allow AP mode - */ - if (!(ch->flags & IEEE80211_CHAN_DISABLED)) - ch->flags |= IEEE80211_CHAN_RADAR | - IEEE80211_CHAN_NO_IBSS | - IEEE80211_CHAN_PASSIVE_SCAN; -#endif - } -} - -static void _rtw_reg_apply_flags(struct wiphy *wiphy) +void rtw_regd_apply_flags(struct wiphy *wiphy) { -#if 1 /* by channel plan */ - _adapter *padapter = wiphy_to_adapter(wiphy); - u8 channel_plan = padapter->mlmepriv.ChannelPlan; - struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - RT_CHANNEL_INFO *channel_set = pmlmeext->channel_set; - u8 max_chan_nums = pmlmeext->max_chan_nums; + struct dvobj_priv *dvobj = wiphy_to_dvobj(wiphy); + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + RT_CHANNEL_INFO *channel_set = rfctl->channel_set; + u8 max_chan_nums = rfctl->max_chan_nums; struct ieee80211_supported_band *sband; struct ieee80211_channel *ch; @@ -332,109 +285,37 @@ static void _rtw_reg_apply_flags(struct wiphy *wiphy) freq = rtw_ch2freq(channel); ch = ieee80211_get_channel(wiphy, freq); - if (ch) { - if (channel_set[i].ScanType == SCAN_PASSIVE - #if defined(CONFIG_DFS_MASTER) - && rtw_odm_dfs_domain_unknown(wiphy_to_adapter(wiphy)) - #endif - ) { - #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) - ch->flags = (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); - #else - ch->flags = IEEE80211_CHAN_NO_IR; - #endif - } else - ch->flags = 0; - } - } - -#else - struct ieee80211_supported_band *sband; - struct ieee80211_channel *ch; - unsigned int i, j; - u16 channels[37] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, - 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, - 149, 153, - 157, 161, 165 - }; - u16 channel; - u32 freq; - - for (i = 0; i < NUM_NL80211_BANDS; i++) { - sband = wiphy->bands[i]; - - if (sband) - for (j = 0; j < sband->n_channels; j++) { - ch = &sband->channels[j]; - - if (ch) - ch->flags = IEEE80211_CHAN_DISABLED; - } - } + if (!ch) + continue; - for (i = 0; i < 37; i++) { - channel = channels[i]; - freq = rtw_ch2freq(channel); + if (channel_set[i].ScanType == SCAN_PASSIVE + #if defined(CONFIG_DFS_MASTER) + && rtw_odm_dfs_domain_unknown(dvobj) + #endif + ) { + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + ch->flags = (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); + #else + ch->flags = IEEE80211_CHAN_NO_IR; + #endif + } else + ch->flags = 0; - ch = ieee80211_get_channel(wiphy, freq); - if (ch) { - if (channel <= 11) - ch->flags = 0; - else - ch->flags = 0; /* IEEE80211_CHAN_PASSIVE_SCAN; */ + #ifdef CONFIG_DFS + if (rtw_is_dfs_ch(ch->hw_value) + #if defined(CONFIG_DFS_MASTER) + && rtw_odm_dfs_domain_unknown(dvobj) + #endif + ) { + ch->flags |= IEEE80211_CHAN_RADAR; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + ch->flags |= (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_PASSIVE_SCAN); + #else + ch->flags |= IEEE80211_CHAN_NO_IR; + #endif } - /* printk("%s: freq %d(%d) flag 0x%02X\n", __func__, freq, channel, ch->flags); */ + #endif /* CONFIG_DFS */ } -#endif -} - -static void _rtw_reg_apply_world_flags(struct wiphy *wiphy, - enum nl80211_reg_initiator initiator, - struct rtw_regulatory *reg) -{ - /* _rtw_reg_apply_beaconing_flags(wiphy, initiator); */ - /* _rtw_reg_apply_active_scan_flags(wiphy, initiator); */ - return; -} - -static int _rtw_reg_notifier_apply(struct wiphy *wiphy, - struct regulatory_request *request, - struct rtw_regulatory *reg) -{ - - /* Hard code flags */ - _rtw_reg_apply_flags(wiphy); - - /* We always apply this */ - _rtw_reg_apply_radar_flags(wiphy); - - switch (request->initiator) { - case NL80211_REGDOM_SET_BY_DRIVER: - RTW_INFO("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_DRIVER"); - _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, - reg); - break; - case NL80211_REGDOM_SET_BY_CORE: - RTW_INFO("%s: %s\n", __func__, - "NL80211_REGDOM_SET_BY_CORE to DRV"); - _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, - reg); - break; - case NL80211_REGDOM_SET_BY_USER: - RTW_INFO("%s: %s\n", __func__, - "NL80211_REGDOM_SET_BY_USER to DRV"); - _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, - reg); - break; - case NL80211_REGDOM_SET_BY_COUNTRY_IE: - RTW_INFO("%s: %s\n", __func__, - "NL80211_REGDOM_SET_BY_COUNTRY_IE"); - _rtw_reg_apply_world_flags(wiphy, request->initiator, reg); - break; - } - - return 0; } static const struct ieee80211_regdomain *_rtw_regdomain_select(struct @@ -452,41 +333,45 @@ static const struct ieee80211_regdomain *_rtw_regdomain_select(struct #endif } -void _rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) +static void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) { - struct rtw_regulatory *reg = NULL; - - RTW_INFO("%s\n", __func__); + switch (request->initiator) { + case NL80211_REGDOM_SET_BY_DRIVER: + RTW_INFO("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_DRIVER"); + break; + case NL80211_REGDOM_SET_BY_CORE: + RTW_INFO("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_CORE"); + break; + case NL80211_REGDOM_SET_BY_USER: + RTW_INFO("%s: %s alpha2:%c%c\n", __func__, "NL80211_REGDOM_SET_BY_USER" + , request->alpha2[0], request->alpha2[1]); + rtw_set_country(wiphy_to_adapter(wiphy), request->alpha2); + break; + case NL80211_REGDOM_SET_BY_COUNTRY_IE: + RTW_INFO("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_COUNTRY_IE"); + break; + } - _rtw_reg_notifier_apply(wiphy, request, reg); + rtw_regd_apply_flags(wiphy); } #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0)) -int rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) -#else -void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) -#endif +static int rtw_reg_notifier_return(struct wiphy *wiphy, struct regulatory_request *request) { - _rtw_reg_notifier(wiphy, request); -#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0)) + rtw_reg_notifier(wiphy, request); return 0; -#endif -} - -void rtw_reg_notify_by_driver(_adapter *adapter) -{ - if ((adapter->rtw_wdev != NULL) && (adapter->rtw_wdev->wiphy)) { - struct regulatory_request request; - request.initiator = NL80211_REGDOM_SET_BY_DRIVER; - rtw_reg_notifier(adapter->rtw_wdev->wiphy, &request); - } } +#endif static void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, struct wiphy *wiphy) { const struct ieee80211_regdomain *regd; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0)) + wiphy->reg_notifier = rtw_reg_notifier_return; +#else wiphy->reg_notifier = rtw_reg_notifier; +#endif #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY; @@ -501,10 +386,7 @@ static void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, struct wiphy *wiphy regd = _rtw_regdomain_select(reg); wiphy_apply_custom_regulatory(wiphy, regd); - /* Hard code flags */ - _rtw_reg_apply_flags(wiphy); - _rtw_reg_apply_radar_flags(wiphy); - _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, reg); + rtw_regd_apply_flags(wiphy); } static struct country_code_to_enum_rd *_rtw_regd_find_country(u16 countrycode) @@ -518,10 +400,8 @@ static struct country_code_to_enum_rd *_rtw_regd_find_country(u16 countrycode) return NULL; } -int rtw_regd_init(_adapter *padapter) +int rtw_regd_init(struct wiphy *wiphy) { - struct wiphy *wiphy = padapter->rtw_wdev->wiphy; - #if 0 if (rtw_regd == NULL) { rtw_regd = (struct rtw_regulatory *) diff --git a/os_dep/linux/xmit_linux.c b/os_dep/linux/xmit_linux.c index 7721b7d..3c42eb5 100644 --- a/os_dep/linux/xmit_linux.c +++ b/os_dep/linux/xmit_linux.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _XMIT_OSDEP_C_ #include @@ -70,36 +65,48 @@ sint rtw_endofpktfile(struct pkt_file *pfile) void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib) { - -#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX +#ifdef CONFIG_TX_CSUM_OFFLOAD struct sk_buff *skb = (struct sk_buff *)pkt; - pattrib->hw_tcp_csum = 0; - - if (skb->ip_summed == CHECKSUM_PARTIAL) { - if (skb_shinfo(skb)->nr_frags == 0) { - const struct iphdr *ip = ip_hdr(skb); - if (ip->protocol == IPPROTO_TCP) { - /* TCP checksum offload by HW */ - RTW_INFO("CHECKSUM_PARTIAL TCP\n"); - pattrib->hw_tcp_csum = 1; - /* skb_checksum_help(skb); */ - } else if (ip->protocol == IPPROTO_UDP) { - /* RTW_INFO("CHECKSUM_PARTIAL UDP\n"); */ -#if 1 - skb_checksum_help(skb); -#else - /* Set UDP checksum = 0 to skip checksum check */ - struct udphdr *udp = skb_transport_header(skb); - udp->check = 0; -#endif - } else { - RTW_INFO("%s-%d TCP CSUM offload Error!!\n", __FUNCTION__, __LINE__); - WARN_ON(1); /* we need a WARN() */ - } - } else { /* IP fragmentation case */ - RTW_INFO("%s-%d nr_frags != 0, using skb_checksum_help(skb);!!\n", __FUNCTION__, __LINE__); + struct iphdr *iph = NULL; + struct ipv6hdr *i6ph = NULL; + struct udphdr *uh = NULL; + struct tcphdr *th = NULL; + u8 protocol = 0xFF; + + if (skb->protocol == htons(ETH_P_IP)) { + iph = (struct iphdr *)skb_network_header(skb); + protocol = iph->protocol; + } else if (skb->protocol == htons(ETH_P_IPV6)) { + i6ph = (struct ipv6hdr *)skb_network_header(skb); + protocol = i6ph->nexthdr; + } else + {} + + /* HW unable to compute CSUM if header & payload was be encrypted by SW(cause TXDMA error) */ + if (pattrib->bswenc == _TRUE) { + if (skb->ip_summed == CHECKSUM_PARTIAL) skb_checksum_help(skb); - } + return; + } + + /* For HW rule, clear ipv4_csum & UDP/TCP_csum if it is UDP/TCP packet */ + switch (protocol) { + case IPPROTO_UDP: + uh = (struct udphdr *)skb_transport_header(skb); + uh->check = 0; + if (iph) + iph->check = 0; + pattrib->hw_csum = _TRUE; + break; + case IPPROTO_TCP: + th = (struct tcphdr *)skb_transport_header(skb); + th->check = 0; + if (iph) + iph->check = 0; + pattrib->hw_csum = _TRUE; + break; + default: + break; } #endif @@ -200,6 +207,12 @@ static inline bool rtw_os_need_wake_queue(_adapter *padapter, u16 qidx) if (padapter->registrypriv.wifi_spec) { if (pxmitpriv->hwxmits[qidx].accnt < WMM_XMIT_THRESHOLD) return _TRUE; +#ifdef DBG_CONFIG_ERROR_DETECT +#ifdef DBG_CONFIG_ERROR_RESET + } else if (rtw_hal_sreset_inprogress(padapter) == _TRUE) { + return _FALSE; +#endif/* #ifdef DBG_CONFIG_ERROR_RESET */ +#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */ } else { #ifdef CONFIG_MCC_MODE if (MCC_EN(padapter)) { @@ -312,7 +325,6 @@ void rtw_os_xmit_schedule(_adapter *padapter) static bool rtw_check_xmit_resource(_adapter *padapter, _pkt *pkt) { bool busy = _FALSE; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) u16 qidx; @@ -403,9 +415,9 @@ int rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb) } /* avoid come from STA1 and send back STA1 */ - if (_rtw_memcmp(psta->hwaddr, &skb->data[6], 6) == _TRUE - || _rtw_memcmp(psta->hwaddr, null_addr, 6) == _TRUE - || _rtw_memcmp(psta->hwaddr, bc_addr, 6) == _TRUE + if (_rtw_memcmp(psta->cmn.mac_addr, &skb->data[6], ETH_ALEN) == _TRUE + || _rtw_memcmp(psta->cmn.mac_addr, null_addr, ETH_ALEN) == _TRUE + || _rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) == _TRUE ) { DBG_COUNTER(padapter->tx_logs.os_tx_m2u_ignore_self); continue; @@ -416,7 +428,7 @@ int rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb) newskb = rtw_skb_copy(skb); if (newskb) { - _rtw_memcpy(newskb->data, psta->hwaddr, 6); + _rtw_memcpy(newskb->data, psta->cmn.mac_addr, ETH_ALEN); res = rtw_xmit(padapter, &newskb); if (res < 0) { DBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry_err_xmit); @@ -444,14 +456,14 @@ int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); struct xmit_priv *pxmitpriv = &padapter->xmitpriv; #ifdef CONFIG_TX_MCAST2UNI - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; extern int rtw_mc2u_disable; #endif /* CONFIG_TX_MCAST2UNI */ - s32 res = 0; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) - u16 queue; +#ifdef CONFIG_TX_CSUM_OFFLOAD + struct sk_buff *skb = pkt; + struct sk_buff *segs, *nskb; + netdev_features_t features = padapter->pnetdev->features; #endif - + s32 res = 0; if (padapter->registrypriv.mp_mode) { RTW_INFO("MP_TX_DROP_OS_FRAME\n"); @@ -471,7 +483,7 @@ int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) #ifdef CONFIG_TX_MCAST2UNI if (!rtw_mc2u_disable - && check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE + && MLME_IS_AP(padapter) && (IP_MCAST_MAC(pkt->data) || ICMPV6_MCAST_MAC(pkt->data) #ifdef CONFIG_TX_BCAST2UNI @@ -492,6 +504,33 @@ int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) } #endif /* CONFIG_TX_MCAST2UNI */ +#ifdef CONFIG_TX_CSUM_OFFLOAD + if (skb_shinfo(skb)->gso_size) { + /* split a big(65k) skb into several small(1.5k) skbs */ + features &= ~(NETIF_F_TSO | NETIF_F_TSO6); + segs = skb_gso_segment(skb, features); + if (IS_ERR(segs) || !segs) + goto drop_packet; + + do { + nskb = segs; + segs = segs->next; + nskb->next = NULL; + rtw_mstat_update( MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, nskb->truesize); + res = rtw_xmit(padapter, &nskb); + if (res < 0) { + #ifdef DBG_TX_DROP_FRAME + RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__); + #endif + pxmitpriv->tx_drop++; + rtw_os_pkt_complete(padapter, nskb); + } + } while (segs); + rtw_os_pkt_complete(padapter, skb); + goto exit; + } +#endif + res = rtw_xmit(padapter, &pkt); if (res < 0) { #ifdef DBG_TX_DROP_FRAME diff --git a/os_dep/osdep_service.c b/os_dep/osdep_service.c index 0f4ea5b..c4a2519 100644 --- a/os_dep/osdep_service.c +++ b/os_dep/osdep_service.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * Copyright(c) 2007 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #define _OSDEP_SERVICE_C_ @@ -78,9 +73,9 @@ u32 rtw_atoi(u8 *s) } -inline u8 *_rtw_vmalloc(u32 sz) +inline void *_rtw_vmalloc(u32 sz) { - u8 *pbuf; + void *pbuf; #ifdef PLATFORM_LINUX pbuf = vmalloc(sz); #endif @@ -104,9 +99,9 @@ inline u8 *_rtw_vmalloc(u32 sz) return pbuf; } -inline u8 *_rtw_zvmalloc(u32 sz) +inline void *_rtw_zvmalloc(u32 sz) { - u8 *pbuf; + void *pbuf; #ifdef PLATFORM_LINUX pbuf = _rtw_vmalloc(sz); if (pbuf != NULL) @@ -124,7 +119,7 @@ inline u8 *_rtw_zvmalloc(u32 sz) return pbuf; } -inline void _rtw_vmfree(u8 *pbuf, u32 sz) +inline void _rtw_vmfree(void *pbuf, u32 sz) { #ifdef PLATFORM_LINUX vfree(pbuf); @@ -144,15 +139,14 @@ inline void _rtw_vmfree(u8 *pbuf, u32 sz) #endif /* DBG_MEMORY_LEAK */ } -u8 *_rtw_malloc(u32 sz) +void *_rtw_malloc(u32 sz) { - - u8 *pbuf = NULL; + void *pbuf = NULL; #ifdef PLATFORM_LINUX #ifdef RTK_DMP_PLATFORM if (sz > 0x4000) - pbuf = (u8 *)dvr_malloc(sz); + pbuf = dvr_malloc(sz); else #endif pbuf = kmalloc(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); @@ -181,12 +175,12 @@ u8 *_rtw_malloc(u32 sz) } -u8 *_rtw_zmalloc(u32 sz) +void *_rtw_zmalloc(u32 sz) { #ifdef PLATFORM_FREEBSD return malloc(sz, M_DEVBUF, M_ZERO | M_NOWAIT); #else /* PLATFORM_FREEBSD */ - u8 *pbuf = _rtw_malloc(sz); + void *pbuf = _rtw_malloc(sz); if (pbuf != NULL) { @@ -204,7 +198,7 @@ u8 *_rtw_zmalloc(u32 sz) #endif /* PLATFORM_FREEBSD */ } -void _rtw_mfree(u8 *pbuf, u32 sz) +void _rtw_mfree(void *pbuf, u32 sz) { #ifdef PLATFORM_LINUX @@ -241,8 +235,8 @@ struct sk_buff *dev_alloc_skb(unsigned int size) struct sk_buff *skb = NULL; u8 *data = NULL; - /* skb = (struct sk_buff *)_rtw_zmalloc(sizeof(struct sk_buff)); */ /* for skb->len, etc. */ - skb = (struct sk_buff *)_rtw_malloc(sizeof(struct sk_buff)); + /* skb = _rtw_zmalloc(sizeof(struct sk_buff)); */ /* for skb->len, etc. */ + skb = _rtw_malloc(sizeof(struct sk_buff)); if (!skb) goto out; data = _rtw_malloc(size); @@ -259,7 +253,7 @@ struct sk_buff *dev_alloc_skb(unsigned int size) out: return skb; nodata: - _rtw_mfree((u8 *)skb, sizeof(struct sk_buff)); + _rtw_mfree(skb, sizeof(struct sk_buff)); skb = NULL; goto out; @@ -272,7 +266,7 @@ void dev_kfree_skb_any(struct sk_buff *skb) _rtw_mfree(skb->head, 0); /* printf("%s()-%d: skb = %p\n", __FUNCTION__, __LINE__, skb); */ if (skb) - _rtw_mfree((u8 *)skb, 0); + _rtw_mfree(skb, 0); } struct sk_buff *skb_clone(const struct sk_buff *skb) { @@ -483,7 +477,7 @@ void rtw_mstat_dump(void *sel) void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz) { - static u32 update_time = 0; + static systime update_time = 0; int peak, alloc; int i; @@ -574,9 +568,9 @@ bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size) return _FALSE; } -inline u8 *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) { - u8 *p; + void *p; if (match_mstat_sniff_rules(flags, sz)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); @@ -592,9 +586,9 @@ inline u8 *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, c return p; } -inline u8 *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) { - u8 *p; + void *p; if (match_mstat_sniff_rules(flags, sz)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); @@ -610,7 +604,7 @@ inline u8 *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, return p; } -inline void dbg_rtw_vmfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void dbg_rtw_vmfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) { if (match_mstat_sniff_rules(flags, sz)) @@ -625,9 +619,9 @@ inline void dbg_rtw_vmfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const cha ); } -inline u8 *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line) { - u8 *p; + void *p; if (match_mstat_sniff_rules(flags, sz)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); @@ -643,9 +637,9 @@ inline u8 *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, co return p; } -inline u8 *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) { - u8 *p; + void *p; if (match_mstat_sniff_rules(flags, sz)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); @@ -661,7 +655,7 @@ inline u8 *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, c return p; } -inline void dbg_rtw_mfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) +inline void dbg_rtw_mfree(void *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) { if (match_mstat_sniff_rules(flags, sz)) RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); @@ -884,6 +878,50 @@ void rtw_mfree2d(void *pbuf, int h, int w, int size) rtw_mfree((u8 *)pbuf, h * sizeof(void *) + w * h * size); } +inline void rtw_os_pkt_free(_pkt *pkt) +{ +#if defined(PLATFORM_LINUX) + rtw_skb_free(pkt); +#elif defined(PLATFORM_FREEBSD) + m_freem(pkt); +#else + #error "TBD\n" +#endif +} + +inline _pkt *rtw_os_pkt_copy(_pkt *pkt) +{ +#if defined(PLATFORM_LINUX) + return rtw_skb_copy(pkt); +#elif defined(PLATFORM_FREEBSD) + return m_dup(pkt, M_NOWAIT); +#else + #error "TBD\n" +#endif +} + +inline void *rtw_os_pkt_data(_pkt *pkt) +{ +#if defined(PLATFORM_LINUX) + return pkt->data; +#elif defined(PLATFORM_FREEBSD) + return pkt->m_data; +#else + #error "TBD\n" +#endif +} + +inline u32 rtw_os_pkt_len(_pkt *pkt) +{ +#if defined(PLATFORM_LINUX) + return pkt->len; +#elif defined(PLATFORM_FREEBSD) + return pkt->m_pkthdr.len; +#else + #error "TBD\n" +#endif +} + void _rtw_memcpy(void *dst, const void *src, u32 sz) { @@ -906,7 +944,7 @@ inline void _rtw_memmove(void *dst, const void *src, u32 sz) #if defined(PLATFORM_LINUX) memmove(dst, src, sz); #else - #warning "no implementation\n" + #error "TBD\n" #endif } @@ -1066,12 +1104,89 @@ void rtw_list_insert_tail(_list *plist, _list *phead) } -void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc) +inline void rtw_list_splice(_list *list, _list *head) +{ +#ifdef PLATFORM_LINUX + list_splice(list, head); +#else + #error "TBD\n" +#endif +} + +inline void rtw_list_splice_init(_list *list, _list *head) +{ +#ifdef PLATFORM_LINUX + list_splice_init(list, head); +#else + #error "TBD\n" +#endif +} + +inline void rtw_list_splice_tail(_list *list, _list *head) +{ +#ifdef PLATFORM_LINUX + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 27)) + if (!list_empty(list)) + __list_splice(list, head); + #else + list_splice_tail(list, head); + #endif +#else + #error "TBD\n" +#endif +} + +inline void rtw_hlist_head_init(rtw_hlist_head *h) +{ +#ifdef PLATFORM_LINUX + INIT_HLIST_HEAD(h); +#else + #error "TBD\n" +#endif +} + +inline void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h) +{ +#ifdef PLATFORM_LINUX + hlist_add_head(n, h); +#else + #error "TBD\n" +#endif +} + +inline void rtw_hlist_del(rtw_hlist_node *n) +{ +#ifdef PLATFORM_LINUX + hlist_del(n); +#else + #error "TBD\n" +#endif +} + +inline void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h) +{ +#ifdef PLATFORM_LINUX + hlist_add_head_rcu(n, h); +#else + #error "TBD\n" +#endif +} + +inline void rtw_hlist_del_rcu(rtw_hlist_node *n) +{ +#ifdef PLATFORM_LINUX + hlist_del_rcu(n); +#else + #error "TBD\n" +#endif +} + +void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx) { _adapter *adapter = (_adapter *)padapter; #ifdef PLATFORM_LINUX - _init_timer(ptimer, adapter->pnetdev, pfunc); + _init_timer(ptimer, adapter->pnetdev, pfunc, ctx); #endif #ifdef PLATFORM_FREEBSD _init_timer(ptimer, adapter->pifp, pfunc, ctx); @@ -1214,20 +1329,6 @@ inline void _rtw_wait_for_comp(_completion *comp) #endif } -inline bool rtw_thread_stop(_thread_hdl_ th) -{ -#ifdef PLATFORM_LINUX - return kthread_stop(th); -#endif -} - -inline bool rtw_thread_should_stop(void) -{ -#ifdef PLATFORM_LINUX - return kthread_should_stop(); -#endif -} - void _rtw_mutex_init(_mutex *pmutex) { #ifdef PLATFORM_LINUX @@ -1434,7 +1535,7 @@ u32 rtw_end_of_queue_search(_list *head, _list *plist) } -u32 rtw_get_current_time(void) +systime _rtw_get_current_time(void) { #ifdef PLATFORM_LINUX @@ -1448,27 +1549,27 @@ u32 rtw_get_current_time(void) #ifdef PLATFORM_WINDOWS LARGE_INTEGER SystemTime; NdisGetCurrentSystemTime(&SystemTime); - return (u32)(SystemTime.LowPart);/* count of 100-nanosecond intervals */ + return SystemTime.LowPart;/* count of 100-nanosecond intervals */ #endif } -inline u32 rtw_systime_to_ms(u32 systime) +inline u32 _rtw_systime_to_ms(systime stime) { #ifdef PLATFORM_LINUX - return systime * 1000 / HZ; + return jiffies_to_msecs(stime); #endif #ifdef PLATFORM_FREEBSD - return systime * 1000; + return stime * 1000; #endif #ifdef PLATFORM_WINDOWS - return systime / 10000 ; + return stime / 10000 ; #endif } -inline u32 rtw_ms_to_systime(u32 ms) +inline systime _rtw_ms_to_systime(u32 ms) { #ifdef PLATFORM_LINUX - return ms * HZ / 1000; + return msecs_to_jiffies(ms); #endif #ifdef PLATFORM_FREEBSD return ms / 1000; @@ -1478,36 +1579,40 @@ inline u32 rtw_ms_to_systime(u32 ms) #endif } -/* the input parameter start use the same unit as returned by rtw_get_current_time */ -inline s32 rtw_get_passing_time_ms(u32 start) +inline systime _rtw_us_to_systime(u32 us) { #ifdef PLATFORM_LINUX - return rtw_systime_to_ms(jiffies - start); -#endif -#ifdef PLATFORM_FREEBSD - return rtw_systime_to_ms(rtw_get_current_time()); -#endif -#ifdef PLATFORM_WINDOWS - LARGE_INTEGER SystemTime; - NdisGetCurrentSystemTime(&SystemTime); - return rtw_systime_to_ms((u32)(SystemTime.LowPart) - start) ; + return usecs_to_jiffies(us); +#else + #error "TBD\n" #endif } -inline s32 rtw_get_time_interval_ms(u32 start, u32 end) +/* the input parameter start use the same unit as returned by rtw_get_current_time */ +inline s32 _rtw_get_passing_time_ms(systime start) +{ + return _rtw_systime_to_ms(_rtw_get_current_time() - start); +} + +inline s32 _rtw_get_remaining_time_ms(systime end) +{ + return _rtw_systime_to_ms(end - _rtw_get_current_time()); +} + +inline s32 _rtw_get_time_interval_ms(systime start, systime end) +{ + return _rtw_systime_to_ms(end - start); +} + +inline bool _rtw_time_after(systime a, systime b) { #ifdef PLATFORM_LINUX - return rtw_systime_to_ms(end - start); -#endif -#ifdef PLATFORM_FREEBSD - return rtw_systime_to_ms(rtw_get_current_time()); -#endif -#ifdef PLATFORM_WINDOWS - return rtw_systime_to_ms(end - start); + return time_after(a, b); +#else + #error "TBD\n" #endif } - void rtw_sleep_schedulable(int ms) { @@ -1703,56 +1808,49 @@ void rtw_yield_os(void) #endif } +bool rtw_macaddr_is_larger(const u8 *a, const u8 *b) +{ + u32 va, vb; + + va = be32_to_cpu(*((u32 *)a)); + vb = be32_to_cpu(*((u32 *)b)); + if (va > vb) + return 1; + else if (va < vb) + return 0; + + return be16_to_cpu(*((u16 *)(a + 4))) > be16_to_cpu(*((u16 *)(b + 4))); +} + #define RTW_SUSPEND_LOCK_NAME "rtw_wifi" -#define RTW_SUSPEND_EXT_LOCK_NAME "rtw_wifi_ext" -#define RTW_SUSPEND_RX_LOCK_NAME "rtw_wifi_rx" #define RTW_SUSPEND_TRAFFIC_LOCK_NAME "rtw_wifi_traffic" #define RTW_SUSPEND_RESUME_LOCK_NAME "rtw_wifi_resume" -#define RTW_RESUME_SCAN_LOCK_NAME "rtw_wifi_scan" #ifdef CONFIG_WAKELOCK static struct wake_lock rtw_suspend_lock; -static struct wake_lock rtw_suspend_ext_lock; -static struct wake_lock rtw_suspend_rx_lock; static struct wake_lock rtw_suspend_traffic_lock; static struct wake_lock rtw_suspend_resume_lock; -static struct wake_lock rtw_resume_scan_lock; #elif defined(CONFIG_ANDROID_POWER) static android_suspend_lock_t rtw_suspend_lock = { .name = RTW_SUSPEND_LOCK_NAME }; -static android_suspend_lock_t rtw_suspend_ext_lock = { - .name = RTW_SUSPEND_EXT_LOCK_NAME -}; -static android_suspend_lock_t rtw_suspend_rx_lock = { - .name = RTW_SUSPEND_RX_LOCK_NAME -}; static android_suspend_lock_t rtw_suspend_traffic_lock = { .name = RTW_SUSPEND_TRAFFIC_LOCK_NAME }; static android_suspend_lock_t rtw_suspend_resume_lock = { .name = RTW_SUSPEND_RESUME_LOCK_NAME }; -static android_suspend_lock_t rtw_resume_scan_lock = { - .name = RTW_RESUME_SCAN_LOCK_NAME -}; #endif inline void rtw_suspend_lock_init(void) { #ifdef CONFIG_WAKELOCK wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME); - wake_lock_init(&rtw_suspend_ext_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_EXT_LOCK_NAME); - wake_lock_init(&rtw_suspend_rx_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RX_LOCK_NAME); wake_lock_init(&rtw_suspend_traffic_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_TRAFFIC_LOCK_NAME); wake_lock_init(&rtw_suspend_resume_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RESUME_LOCK_NAME); - wake_lock_init(&rtw_resume_scan_lock, WAKE_LOCK_SUSPEND, RTW_RESUME_SCAN_LOCK_NAME); #elif defined(CONFIG_ANDROID_POWER) android_init_suspend_lock(&rtw_suspend_lock); - android_init_suspend_lock(&rtw_suspend_ext_lock); - android_init_suspend_lock(&rtw_suspend_rx_lock); android_init_suspend_lock(&rtw_suspend_traffic_lock); android_init_suspend_lock(&rtw_suspend_resume_lock); - android_init_suspend_lock(&rtw_resume_scan_lock); #endif } @@ -1760,18 +1858,12 @@ inline void rtw_suspend_lock_uninit(void) { #ifdef CONFIG_WAKELOCK wake_lock_destroy(&rtw_suspend_lock); - wake_lock_destroy(&rtw_suspend_ext_lock); - wake_lock_destroy(&rtw_suspend_rx_lock); wake_lock_destroy(&rtw_suspend_traffic_lock); wake_lock_destroy(&rtw_suspend_resume_lock); - wake_lock_destroy(&rtw_resume_scan_lock); #elif defined(CONFIG_ANDROID_POWER) android_uninit_suspend_lock(&rtw_suspend_lock); - android_uninit_suspend_lock(&rtw_suspend_ext_lock); - android_uninit_suspend_lock(&rtw_suspend_rx_lock); android_uninit_suspend_lock(&rtw_suspend_traffic_lock); android_uninit_suspend_lock(&rtw_suspend_resume_lock); - android_uninit_suspend_lock(&rtw_resume_scan_lock); #endif } @@ -1836,45 +1928,42 @@ inline void rtw_lock_suspend_timeout(u32 timeout_ms) #endif } -inline void rtw_lock_ext_suspend_timeout(u32 timeout_ms) + +inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms) { #ifdef CONFIG_WAKELOCK - wake_lock_timeout(&rtw_suspend_ext_lock, rtw_ms_to_systime(timeout_ms)); + wake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); #elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend_auto_expire(&rtw_suspend_ext_lock, rtw_ms_to_systime(timeout_ms)); + android_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); #endif - /* RTW_INFO("EXT lock timeout:%d\n", timeout_ms); */ + /* RTW_INFO("traffic lock timeout:%d\n", timeout_ms); */ } -inline void rtw_lock_rx_suspend_timeout(u32 timeout_ms) +inline void rtw_set_bit(int nr, unsigned long *addr) { -#ifdef CONFIG_WAKELOCK - wake_lock_timeout(&rtw_suspend_rx_lock, rtw_ms_to_systime(timeout_ms)); -#elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend_auto_expire(&rtw_suspend_rx_lock, rtw_ms_to_systime(timeout_ms)); +#ifdef PLATFORM_LINUX + set_bit(nr, addr); +#else + #error "TBD\n"; #endif - /* RTW_INFO("RX lock timeout:%d\n", timeout_ms); */ } - -inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms) +inline void rtw_clear_bit(int nr, unsigned long *addr) { -#ifdef CONFIG_WAKELOCK - wake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); -#elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); +#ifdef PLATFORM_LINUX + clear_bit(nr, addr); +#else + #error "TBD\n"; #endif - /* RTW_INFO("traffic lock timeout:%d\n", timeout_ms); */ } -inline void rtw_lock_resume_scan_timeout(u32 timeout_ms) +inline int rtw_test_and_clear_bit(int nr, unsigned long *addr) { -#ifdef CONFIG_WAKELOCK - wake_lock_timeout(&rtw_resume_scan_lock, rtw_ms_to_systime(timeout_ms)); -#elif defined(CONFIG_ANDROID_POWER) - android_lock_suspend_auto_expire(&rtw_resume_scan_lock, rtw_ms_to_systime(timeout_ms)); +#ifdef PLATFORM_LINUX + return test_and_clear_bit(nr, addr); +#else + #error "TBD\n"; #endif - /* RTW_INFO("resume scan lock:%d\n", timeout_ms); */ } inline void ATOMIC_SET(ATOMIC_T *v, int i) @@ -1990,6 +2079,23 @@ inline int ATOMIC_DEC_RETURN(ATOMIC_T *v) #endif } +inline bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u) +{ +#ifdef PLATFORM_LINUX +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 15)) + return atomic_add_unless(v, 1, u); +#else + /* only make sure not exceed after this function */ + if (ATOMIC_INC_RETURN(v) > u) { + ATOMIC_DEC(v); + return 0; + } + return 1; +#endif +#else + #error "TBD\n" +#endif +} #ifdef PLATFORM_LINUX /* @@ -2029,11 +2135,21 @@ static int readFile(struct file *fp, char *buf, int len) { int rlen = 0, sum = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + if (!(fp->f_mode & FMODE_CAN_READ)) +#else if (!fp->f_op || !fp->f_op->read) +#endif return -EPERM; while (sum < len) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) + rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos); +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos); +#else rlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos); +#endif if (rlen > 0) sum += rlen; else if (0 != rlen) @@ -2728,6 +2844,167 @@ u8 map_read8(const struct map_t *map, u16 offset) return val; } +int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms) +{ + struct blacklist_ent *ent; + _list *list, *head; + u8 exist = _FALSE, timeout = _FALSE; + + enter_critical_bh(&blist->lock); + + head = &blist->queue; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + + if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) { + exist = _TRUE; + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) + timeout = _TRUE; + ent->exp_time = rtw_get_current_time() + + rtw_ms_to_systime(timeout_ms); + break; + } + + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } + } + + if (exist == _FALSE) { + ent = rtw_malloc(sizeof(struct blacklist_ent)); + if (ent) { + _rtw_memcpy(ent->addr, addr, ETH_ALEN); + ent->exp_time = rtw_get_current_time() + + rtw_ms_to_systime(timeout_ms); + rtw_list_insert_tail(&ent->list, head); + } + } + + exit_critical_bh(&blist->lock); + +exit: + return (exist == _TRUE && timeout == _FALSE) ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL); +} + +int rtw_blacklist_del(_queue *blist, const u8 *addr) +{ + struct blacklist_ent *ent = NULL; + _list *list, *head; + u8 exist = _FALSE; + + enter_critical_bh(&blist->lock); + head = &blist->queue; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + + if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + exist = _TRUE; + break; + } + + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } + } + + exit_critical_bh(&blist->lock); + +exit: + return exist == _TRUE ? _SUCCESS : RTW_ALREADY; +} + +int rtw_blacklist_search(_queue *blist, const u8 *addr) +{ + struct blacklist_ent *ent = NULL; + _list *list, *head; + u8 exist = _FALSE; + + enter_critical_bh(&blist->lock); + head = &blist->queue; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + + if (_rtw_memcmp(ent->addr, addr, ETH_ALEN) == _TRUE) { + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } else + exist = _TRUE; + break; + } + + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) { + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } + } + + exit_critical_bh(&blist->lock); + +exit: + return exist; +} + +void rtw_blacklist_flush(_queue *blist) +{ + struct blacklist_ent *ent; + _list *list, *head; + _list tmp; + + _rtw_init_listhead(&tmp); + + enter_critical_bh(&blist->lock); + rtw_list_splice_init(&blist->queue, &tmp); + exit_critical_bh(&blist->lock); + + head = &tmp; + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + rtw_list_delete(&ent->list); + rtw_mfree(ent, sizeof(struct blacklist_ent)); + } +} + +void dump_blacklist(void *sel, _queue *blist, const char *title) +{ + struct blacklist_ent *ent = NULL; + _list *list, *head; + + enter_critical_bh(&blist->lock); + head = &blist->queue; + list = get_next(head); + + if (rtw_end_of_queue_search(head, list) == _FALSE) { + if (title) + RTW_PRINT_SEL(sel, "%s:\n", title); + + while (rtw_end_of_queue_search(head, list) == _FALSE) { + ent = LIST_CONTAINOR(list, struct blacklist_ent, list); + list = get_next(list); + + if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) + RTW_PRINT_SEL(sel, MAC_FMT" expired\n", MAC_ARG(ent->addr)); + else + RTW_PRINT_SEL(sel, MAC_FMT" %u\n", MAC_ARG(ent->addr) + , rtw_get_remaining_time_ms(ent->exp_time)); + } + + } + exit_critical_bh(&blist->lock); +} + /** * is_null - * @@ -2816,3 +3093,44 @@ inline char alpha_to_upper(char c) c = 'A' + (c - 'a'); return c; } + +int hex2num_i(char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + return -1; +} + +int hex2byte_i(const char *hex) +{ + int a, b; + a = hex2num_i(*hex++); + if (a < 0) + return -1; + b = hex2num_i(*hex++); + if (b < 0) + return -1; + return (a << 4) | b; +} + +int hexstr2bin(const char *hex, u8 *buf, size_t len) +{ + size_t i; + int a; + const char *ipos = hex; + u8 *opos = buf; + + for (i = 0; i < len; i++) { + a = hex2byte_i(ipos); + if (a < 0) + return -1; + *opos++ = a; + ipos += 2; + } + return 0; +} + diff --git a/platform/custom_country_chplan.h b/platform/custom_country_chplan.h index 4a40b9f..f8cc13b 100644 --- a/platform/custom_country_chplan.h +++ b/platform/custom_country_chplan.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,17 +11,12 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #error "You have defined CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP to use a customized map of your own instead of the default one" #error "Before removing these error notifications, please make sure regulatory certification requirements of your target markets" static const struct country_chplan CUSTOMIZED_country_chplan_map[] = { - COUNTRY_CHPLAN_ENT("TW", 0x62, 1, 0x1FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("TW", 0x76, 1, 0x3FF), /* Taiwan */ }; diff --git a/platform/platform_ARM_SUN50IW1P1_sdio.c b/platform/platform_ARM_SUN50IW1P1_sdio.c index 44bd7de..2586455 100644 --- a/platform/platform_ARM_SUN50IW1P1_sdio.c +++ b/platform/platform_ARM_SUN50IW1P1_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* * Description: * This file can be applied to following platforms: diff --git a/platform/platform_ARM_SUNnI_sdio.c b/platform/platform_ARM_SUNnI_sdio.c index 612dfba..8a52aa9 100644 --- a/platform/platform_ARM_SUNnI_sdio.c +++ b/platform/platform_ARM_SUNnI_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* * Description: * This file can be applied to following platforms: diff --git a/platform/platform_ARM_SUNxI_sdio.c b/platform/platform_ARM_SUNxI_sdio.c index 6eed7b1..795b7e7 100644 --- a/platform/platform_ARM_SUNxI_sdio.c +++ b/platform/platform_ARM_SUNxI_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #ifdef CONFIG_MMC_SUNXI_POWER_CONTROL diff --git a/platform/platform_ARM_SUNxI_usb.c b/platform/platform_ARM_SUNxI_usb.c index b2c8a28..9c2abc4 100644 --- a/platform/platform_ARM_SUNxI_usb.c +++ b/platform/platform_ARM_SUNxI_usb.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* * Description: * This file can be applied to following platforms: diff --git a/platform/platform_ARM_WMT_sdio.c b/platform/platform_ARM_WMT_sdio.c index 159a5ac..d85002c 100644 --- a/platform/platform_ARM_WMT_sdio.c +++ b/platform/platform_ARM_WMT_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include #include #include diff --git a/platform/platform_RTK_DMP_usb.c b/platform/platform_RTK_DMP_usb.c index af845f7..cb740b2 100644 --- a/platform/platform_RTK_DMP_usb.c +++ b/platform/platform_RTK_DMP_usb.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include int platform_wifi_power_on(void) diff --git a/platform/platform_aml_s905_sdio.c b/platform/platform_aml_s905_sdio.c new file mode 100644 index 0000000..334ca03 --- /dev/null +++ b/platform/platform_aml_s905_sdio.c @@ -0,0 +1,54 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include /* pr_info(() */ +#include /* msleep() */ +#include "platform_aml_s905_sdio.h" /* sdio_reinit() and etc */ + + +/* + * Return: + * 0: power on successfully + * others: power on failed + */ +int platform_wifi_power_on(void) +{ + int ret = 0; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + ret = wifi_setup_dt(); + if (ret) { + pr_err("%s: setup dt failed!!(%d)\n", __func__, ret); + return -1; + } +#endif /* kernel < 3.14.0 */ + +#if 0 /* Seems redundancy? Already done before insert driver */ + pr_info("######%s:\n", __func__); + extern_wifi_set_enable(0); + msleep(500); + extern_wifi_set_enable(1); + msleep(500); + sdio_reinit(); +#endif + + return ret; +} + +void platform_wifi_power_off(void) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + wifi_teardown_dt(); +#endif /* kernel < 3.14.0 */ +} diff --git a/platform/platform_aml_s905_sdio.h b/platform/platform_aml_s905_sdio.h new file mode 100644 index 0000000..2b87576 --- /dev/null +++ b/platform/platform_aml_s905_sdio.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PLATFORM_AML_S905_SDIO_H__ +#define __PLATFORM_AML_S905_SDIO_H__ + +#include /* Linux vresion */ + +extern void sdio_reinit(void); +extern void extern_wifi_set_enable(int is_on); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) +extern void wifi_teardown_dt(void); +extern int wifi_setup_dt(void); +#endif /* kernel < 3.14.0 */ + +#endif /* __PLATFORM_AML_S905_SDIO_H__ */ diff --git a/platform/platform_arm_act_sdio.c b/platform/platform_arm_act_sdio.c index 539bb17..ad7b6cf 100644 --- a/platform/platform_arm_act_sdio.c +++ b/platform/platform_arm_act_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ /* * Description: * This file can be applied to following platforms: diff --git a/platform/platform_hisilicon_hi3798_sdio.c b/platform/platform_hisilicon_hi3798_sdio.c new file mode 100644 index 0000000..11a0832 --- /dev/null +++ b/platform/platform_hisilicon_hi3798_sdio.c @@ -0,0 +1,110 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include /* mdelay() */ +#include /* __io_address(), readl(), writel() */ +#include "platform_hisilicon_hi3798_sdio.h" /* HI_S32() and etc. */ + +typedef enum hi_GPIO_DIR_E { + HI_DIR_OUT = 0, + HI_DIR_IN = 1, +} HI_GPIO_DIR_E; + +#define RTL_REG_ON_GPIO (4*8 + 3) + +#define REG_BASE_CTRL __io_address(0xf8a20008) + +int gpio_wlan_reg_on = RTL_REG_ON_GPIO; +#if 0 +module_param(gpio_wlan_reg_on, uint, 0644); +MODULE_PARM_DESC(gpio_wlan_reg_on, "wlan reg_on gpio num (default:gpio4_3)"); +#endif + +static int hi_gpio_set_value(u32 gpio, u32 value) +{ + HI_S32 s32Status; + + s32Status = HI_DRV_GPIO_SetDirBit(gpio, HI_DIR_OUT); + if (s32Status != HI_SUCCESS) { + pr_err("gpio(%d) HI_DRV_GPIO_SetDirBit HI_DIR_OUT failed\n", + gpio); + return -1; + } + + s32Status = HI_DRV_GPIO_WriteBit(gpio, value); + if (s32Status != HI_SUCCESS) { + pr_err("gpio(%d) HI_DRV_GPIO_WriteBit value(%d) failed\n", + gpio, value); + return -1; + } + + return 0; +} + +static int hisi_wlan_set_carddetect(bool present) +{ + u32 regval; + u32 mask; + + +#ifndef CONFIG_HISI_SDIO_ID + return; +#endif + pr_info("SDIO ID=%d\n", CONFIG_HISI_SDIO_ID); +#if (CONFIG_HISI_SDIO_ID == 1) + mask = 1; +#elif (CONFIG_HISI_SDIO_ID == 0) + mask = 2; +#endif + + regval = readl(REG_BASE_CTRL); + if (present) { + pr_info("====== Card detection to detect SDIO card! ======\n"); + /* set card_detect low to detect card */ + regval |= mask; + } else { + pr_info("====== Card detection to remove SDIO card! ======\n"); + /* set card_detect high to remove card */ + regval &= ~(mask); + } + writel(regval, REG_BASE_CTRL); + + return 0; +} + +/* + * Return: + * 0: power on successfully + * others: power on failed + */ +int platform_wifi_power_on(void) +{ + int ret = 0; + + + hi_gpio_set_value(gpio_wlan_reg_on, 1); + mdelay(100); + hisi_wlan_set_carddetect(1); + mdelay(2000); + pr_info("======== set_carddetect delay 2s! ========\n"); + + return ret; +} + +void platform_wifi_power_off(void) +{ + hisi_wlan_set_carddetect(0); + mdelay(100); + hi_gpio_set_value(gpio_wlan_reg_on, 0); +} diff --git a/platform/platform_hisilicon_hi3798_sdio.h b/platform/platform_hisilicon_hi3798_sdio.h new file mode 100644 index 0000000..1ad4240 --- /dev/null +++ b/platform/platform_hisilicon_hi3798_sdio.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * + * Copyright(c) 2017 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PLATFORM_HISILICON_HI3798_SDIO_H__ +#define __PLATFORM_HISILICON_HI3798_SDIO_H__ + +typedef unsigned int HI_U32; + +typedef int HI_S32; + +#define HI_SUCCESS 0 +#define HI_FAILURE (-1) + +extern HI_S32 HI_DRV_GPIO_SetDirBit(HI_U32 u32GpioNo, HI_U32 u32DirBit); +extern HI_S32 HI_DRV_GPIO_WriteBit(HI_U32 u32GpioNo, HI_U32 u32BitValue); + +#endif /* __PLATFORM_HISILICON_HI3798_SDIO_H__ */ diff --git a/platform/platform_ops.c b/platform/platform_ops.c index 95da669..10766aa 100644 --- a/platform/platform_ops.c +++ b/platform/platform_ops.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef CONFIG_PLATFORM_OPS /* * Return: diff --git a/platform/platform_ops.h b/platform/platform_ops.h index b8314bb..12caf3c 100644 --- a/platform/platform_ops.h +++ b/platform/platform_ops.h @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #ifndef __PLATFORM_OPS_H__ #define __PLATFORM_OPS_H__ diff --git a/platform/platform_sprd_sdio.c b/platform/platform_sprd_sdio.c index c5ffd14..34061d0 100644 --- a/platform/platform_sprd_sdio.c +++ b/platform/platform_sprd_sdio.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * Copyright(c) 2013 - 2017 Realtek Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of version 2 of the GNU General Public License as @@ -11,12 +11,7 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ + *****************************************************************************/ #include extern void sdhci_bus_scan(void); diff --git a/platform/platform_zte_zx296716_sdio.c b/platform/platform_zte_zx296716_sdio.c new file mode 100644 index 0000000..472d24d --- /dev/null +++ b/platform/platform_zte_zx296716_sdio.c @@ -0,0 +1,53 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include /* pr_info(() */ +#include /* msleep() */ +#include "platform_zte_zx296716_sdio.h" /* sdio_reinit() and etc */ + + +/* + * Return: + * 0: power on successfully + * others: power on failed + */ +int platform_wifi_power_on(void) +{ + int ret = 0; + + pr_info("######%s: disable--1--\n", __func__); + extern_wifi_set_enable(0); + /*msleep(500);*/ /* add in function:extern_wifi_set_enable */ + pr_info("######%s: enable--2---\n", __func__); + extern_wifi_set_enable(1); + /*msleep(500);*/ + sdio_reinit(); + + return ret; +} + +void platform_wifi_power_off(void) +{ + int card_val; + + pr_info("######%s:\n", __func__); +#ifdef CONFIG_A16T03_BOARD + card_val = sdio_host_is_null(); + if (card_val) + remove_card(); +#endif /* CONFIG_A16T03_BOARD */ + extern_wifi_set_enable(0); + + /*msleep(500);*/ +} diff --git a/platform/platform_zte_zx296716_sdio.h b/platform/platform_zte_zx296716_sdio.h new file mode 100644 index 0000000..3a4fba1 --- /dev/null +++ b/platform/platform_zte_zx296716_sdio.h @@ -0,0 +1,25 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2018 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __PLATFORM_ZTE_ZX296716_SDIO_H__ +#define __PLATFORM_ZTE_ZX296716_SDIO_H__ + +extern void sdio_reinit(void); +extern void extern_wifi_set_enable(int val); +#ifdef CONFIG_A16T03_BOARD +extern int sdio_host_is_null(void); +extern void remove_card(void); +#endif /* CONFIG_A16T03_BOARD */ + +#endif /* __PLATFORM_ZTE_ZX296716_SDIO_H__ */ diff --git a/rtl8821c.mk b/rtl8821c.mk index bf8162e..a6a79c6 100644 --- a/rtl8821c.mk +++ b/rtl8821c.mk @@ -1,44 +1,15 @@ -RTL871X := rtl8821c EXTRA_CFLAGS += -DCONFIG_RTL8821C ifeq ($(CONFIG_USB_HCI), y) -MODULE_NAME = 8821cu +FILE_NAME = 8821cu endif ifeq ($(CONFIG_PCI_HCI), y) -MODULE_NAME = 8821ce +FILE_NAME = 8821ce endif ifeq ($(CONFIG_SDIO_HCI), y) -MODULE_NAME = 8821cs +FILE_NAME = 8821cs endif -ifeq ($(CONFIG_PLATFORM_NV_TK1), n) -ifeq ($(CONFIG_PLATFORM_RTK129X), n) -ifeq ($(CONFIG_MP_INCLUDED), y) -### 8821C Default Enable VHT MP HW TX MODE ### -EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE -CONFIG_MP_VHT_HW_TX_MODE = y -endif -endif -endif - -_HAL_HALMAC_FILES += hal/halmac/halmac_api.o - -_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_api_88xx.o \ - hal/halmac/halmac_88xx/halmac_func_88xx.o \ - hal/halmac/halmac_88xx/halmac_api_88xx_usb.o \ - hal/halmac/halmac_88xx/halmac_api_88xx_sdio.o \ - hal/halmac/halmac_88xx/halmac_api_88xx_pcie.o - -_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.o \ - hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.o \ - hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.o \ - hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.o \ - hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.o \ - hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.o \ - hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_phy.o - -_HAL_INTFS_FILES += hal/hal_halmac.o - _HAL_INTFS_FILES += hal/rtl8821c/rtl8821c_halinit.o \ hal/rtl8821c/rtl8821c_mac.o \ hal/rtl8821c/rtl8821c_cmd.o \ @@ -47,13 +18,13 @@ _HAL_INTFS_FILES += hal/rtl8821c/rtl8821c_halinit.o \ hal/rtl8821c/rtl8821c_ops.o \ hal/rtl8821c/hal8821c_fw.o -_HAL_INTFS_FILES += hal/rtl8821c/$(HCI_NAME)/rtl$(MODULE_NAME)_halinit.o \ - hal/rtl8821c/$(HCI_NAME)/rtl$(MODULE_NAME)_halmac.o \ - hal/rtl8821c/$(HCI_NAME)/rtl$(MODULE_NAME)_io.o \ - hal/rtl8821c/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \ - hal/rtl8821c/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o \ - hal/rtl8821c/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \ - hal/rtl8821c/$(HCI_NAME)/rtl$(MODULE_NAME)_ops.o +_HAL_INTFS_FILES += hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_halinit.o \ + hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_halmac.o \ + hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_io.o \ + hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_xmit.o \ + hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_recv.o \ + hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_led.o \ + hal/rtl8821c/$(HCI_NAME)/rtl$(FILE_NAME)_ops.o ifeq ($(CONFIG_SDIO_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821C_SDIO.o @@ -65,12 +36,10 @@ ifeq ($(CONFIG_PCI_HCI), y) _HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821C_PCIE.o endif -_OUTSRC_FILES += hal/phydm/rtl8821c/halhwimg8821c_bb.o \ - hal/phydm/rtl8821c/halhwimg8821c_mac.o \ - hal/phydm/rtl8821c/halhwimg8821c_rf.o \ - hal/phydm/rtl8821c/phydm_hal_api8821c.o \ - hal/phydm/rtl8821c/phydm_regconfig8821c.o\ - hal/phydm/rtl8821c/halphyrf_8821c.o\ - hal/phydm/rtl8821c/phydm_iqk_8821c.o +include $(srctree)/$(src)/halmac.mk -_HAL_INTFS_FILES += $(_HAL_HALMAC_FILES) +_BTC_FILES += hal/btc/halbtc8821cwifionly.o +ifeq ($(CONFIG_BT_COEXIST), y) +_BTC_FILES += hal/btc/halbtc8821c1ant.o \ + hal/btc/halbtc8821c2ant.o +endif